diff --git a/build_scripts/build_all.sh b/build_scripts/build_all.sh
new file mode 100755
index 0000000..111d8c1
--- /dev/null
+++ b/build_scripts/build_all.sh
@@ -0,0 +1,157 @@
+#!/bin/bash
+
+set -e
+
+top_dir=$(readlink -e $(dirname $0)/../../)
+
+declare -A PRODUCT_LIST=([sirocco]="sirocco-p1 sirocco-b1 sirocco-b3 sirocco-b4")
+
+function Help() {
+  echo "Usage: $0  <eureka_workspace> <product/board> [optional build number] [other options]"
+  echo "  valid product : sirocco"
+  echo "  available options: --venv_root=<venv_root>"
+}
+
+function parse_args() {
+  readonly eureka_src_path="$( cd "$( dirname "${1}" )" && pwd )/$(basename $1)"
+  # Set the target profile as per SOC
+  product=""
+  revision=""
+  # Check if user specify product or board
+  if [[ "$2" =~ ^.+-[pb][0-9]$ ]]; then
+    product=`echo $2 | cut -d "-" -f1`
+    revision=`echo $2 | cut -d "-" -f2`
+  else
+    product=$2
+  fi
+  readonly product
+  readonly revision
+
+  deterministic_build=""
+
+  shift # product
+  shift # eureka_src_path
+
+  for arg in "$@"
+  do
+    case $arg in
+      --venv_root=*)
+        pyvenv_path="${arg#*=}"
+        shift # past argument=value
+      ;;
+      *[!0-9]* | '') # not a number
+        echo "unknown option ${arg}"
+      ;;
+      *)
+        build_number=$arg
+        shift
+      ;;
+    esac
+  done
+
+  if [ -z "$build_number" ]; then
+    build_number="${USER}-private_build"
+  else
+    # If we were supplied a build number, this is probably a build server build so
+    # build kernel deterministically
+    deterministic_build="-d"
+  fi
+}
+
+function setup_pyvenv() {
+  if [ -d "${pyvenv_path}" -a -f "${pyvenv_path}/bin/activate" ]; then
+    source ${pyvenv_path}/bin/activate
+    echo "activated virtual environment at ${pyvenv_path}"
+  fi
+}
+
+function IsProductValid() {
+  local available_product
+  local ret=1
+
+  for available_product in ${!PRODUCT_LIST[@]}; do
+    if [ "${available_product}" == "$1" ]; then
+      ret=0
+      break
+    fi
+  done
+
+  return ${ret}
+}
+
+function build_for_board() {
+  board=$1
+
+  # Build kernel
+  pushd ${top_dir}/kernel
+  echo "Build kernel for ${board}..."
+  ./build.sh ${deterministic_build} ${board} ${eureka_src_path}
+  popd
+
+  # Build u-boot
+  pushd ${top_dir}/bootloader
+  echo "Build bootloader for ${board}..."
+  ./build.sh ${deterministic_build} ${board} ${eureka_src_path}
+  popd
+}
+
+function BuildAll() {
+  if [ -z ${eureka_src_path} ]; then
+    echo "eureka_src_path doesn't exist"
+    exit 1
+  fi
+
+  if ! IsProductValid ${product}; then
+    echo "Invalid product: $product"
+    Help
+    exit 1
+  fi
+
+
+  if [ $revision ]; then
+    echo "Build for board ${product}-${revision}"
+    build_for_board $product-$revision
+  else
+    echo "Build for all board revisions for product: ${product}"
+    for board in ${PRODUCT_LIST[${product}]}; do
+      build_for_board $board
+    done
+  fi
+
+  # Build sdk modules
+  pushd ${top_dir}/sdk/qca-ssdk
+  ./build.sh ${product} ${eureka_src_path}
+  popd
+
+  pushd ${top_dir}/sdk/qca-nss-dp
+  ./build.sh ${product} ${eureka_src_path}
+  popd
+
+  pushd ${top_dir}/sdk/qca-nss-sfe
+  ./build.sh ${product} ${eureka_src_path}
+  popd
+
+  pushd ${top_dir}/sdk/qca-nss-ecm
+  ./build.sh ${product} ${eureka_src_path}
+  popd
+}
+
+#########################
+####### Main Entry ######
+#########################
+if [[ "$#" -lt 2 ]] || [[ "$#" -gt 4 ]]; then
+  echo "Error: Incorrect arguments."
+  Help
+  exit 1
+fi
+
+parse_args $@
+
+# Create SDK Version number
+mkdir -p ${eureka_src_path}/vendor/qualcomm/${product}
+sdk_version_manifest=${eureka_src_path}/vendor/qualcomm/${product}/SDK_VERSION
+echo "Build #${build_number}|$(TZ='America/Los_Angeles' date)" > $sdk_version_manifest
+
+setup_pyvenv
+
+BuildAll
diff --git a/build_scripts/release_oss.sh b/build_scripts/release_oss.sh
new file mode 100755
index 0000000..732d06e
--- /dev/null
+++ b/build_scripts/release_oss.sh
@@ -0,0 +1,60 @@
+#!/bin/bash
+# Script for releasing SDK open source software on eureka-partner.
+# Usage:
+#   release_oss.sh <oss_target_directory>
+#
+# Output is chromecast_sdk_oss.tgz in <oss_target_directory>.
+
+# Release all source code under ./kernel.
+function release_kernel() {
+  src=$1/kernel
+  dst=$2/kernel
+  echo "Copying kernel from $src ==> $dst..."
+
+  mkdir -p ${dst}
+  # Clean up source tree.
+  pushd ${src} && git clean -dfx && popd
+
+  rsync -av ${src}/ ${dst} --exclude .git
+}
+
+# Release source code under ./bootloader
+function release_bootloader() {
+  src=$1/bootloader
+  dst=$2/u-boot
+  echo "Copying bootloader from $src ==> $dst..."
+
+  mkdir -p ${dst}
+  # Clean up source tree.
+  pushd ${src} && git clean -dfx && popd
+
+  rsync -av ${src}/ ${dst} --exclude .git
+}
+
+sdk_root=$(readlink -f $(dirname $0)/../../)
+
+if [[ $# != 1 ]]; then
+  echo "Usage: $0 OSS_RELEASE_DIR"
+  exit 1
+fi
+
+oss_root=$(readlink -f $1)
+oss_tmp_dir=${oss_root}/chromecast_sdk_oss
+
+if [[ ${oss_root} == ${sdk_root}/* ]]; then
+  echo "OSS_RELEASE_DIR can't be sub-dir of sdk_root $sdk_root"
+  exit 1
+fi
+
+# Clear and create output dir.
+rm -rf ${oss_tmp_dir}
+mkdir -p ${oss_tmp_dir}
+
+release_kernel ${sdk_root} $oss_tmp_dir
+
+release_bootloader ${sdk_root} ${oss_tmp_dir}
+
+tar zcvf ${oss_root}/chromecast_sdk_oss.tgz -C ${oss_root} chromecast_sdk_oss
+rm -rf ${oss_tmp_dir}
+
+echo "Open Source Software has been released to ${oss_root}/chromecast_sdk_oss.tgz".
diff --git a/build_scripts/setup_env.sh b/build_scripts/setup_env.sh
new file mode 100644
index 0000000..a658366
--- /dev/null
+++ b/build_scripts/setup_env.sh
@@ -0,0 +1,62 @@
+#!/bin/bash
+# Usage:
+#   source setup_env.sh
+#
+# Inputs:
+#   TOP_DIR: where the .repo of prebuilts reside
+#            It is optional. Default is this script's <dir>/ ../..
+#   ENABLE_64BIT_BUILD: if we are building 64bit prebuilts
+#            It is optional. Default is TRUE.
+# Exports:
+#   used for kernel or kernel module configs
+#
+#   CROSS_COMPILER_DIR: where cross compilers are
+#   ARCH: arm or arm64
+#   CROSS_COMPILE: the prefix of cross compiler
+#   LD: the linker to use
+#   PATH: new PATH includes the cross compiler
+#   CROSS_MAKE: make cmd with essential paramerters to do cross make
+#
+# Functions
+#   GetModulePath:
+#     Take <eureka_src_path> and <product> to generate target
+#     kernel module path
+
+if [ ! -d "${TOP_DIR}" ]; then
+  TOP_DIR="$(readlink -e $(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)/../..)"
+fi
+ENABLE_64BIT_BUILD=${ENABLE_64BIT_BUILD:-"false"}
+
+_toolchain_dir=$(readlink -e ${TOP_DIR}/prebuilt/toolchain)
+_num_jobs=$(grep -c processor /proc/cpuinfo)
+
+if [ "${ENABLE_64BIT_BUILD}" = "false" ]; then
+  export CROSS_COMPILER_DIR=${_toolchain_dir}/armv7a/bin
+  export ARCH=arm
+  export CROSS_COMPILE=armv7a-cros-linux-gnueabihf-
+  export LD=${CROSS_COMPILE}ld
+  export CC=${CROSS_COMPILE}gcc
+else
+  export CROSS_COMPILER_DIR=${_toolchain_dir}/aarch64/bin
+  export ARCH=arm64
+  export CROSS_COMPILE=aarch64-cros-linux-gnu-
+  export LD=${CROSS_COMPILE}ld.bfd
+  export CC=${CROSS_COMPILE}clang
+fi
+
+function GetModulePath() {
+  local eureka_src_path=$1
+  local product=$2
+
+  echo "${eureka_src_path}/vendor/qualcomm/${product}/prebuilt/systemfs_overlay/lib/modules"
+}
+
+function GetKernelPath() {
+  local eureka_src_path=$1
+  local product=$2
+
+  echo ${eureka_src_path}/vendor/qualcomm/${product}/prebuilt/kernel
+}
+
+export PATH=${CROSS_COMPILER_DIR}:$PATH
+export CROSS_MAKE="make -j${_num_jobs} CC=${CC} LD=${LD}"
diff --git a/ecm_wifi_plugins/Makefile b/ecm_wifi_plugins/Makefile
new file mode 100644
index 0000000..0a379b2
--- /dev/null
+++ b/ecm_wifi_plugins/Makefile
@@ -0,0 +1,11 @@
+# Makefile for ecm wifi plugin module
+ccflags-y += -I$(obj)/../exports -I$(obj)/..
+ccflags-y += -DECM_WIFI_PLUGIN_BUILD_ID="$(BUILD_ID)"
+ccflags-y += -DECM_WIFI_PLUGIN_DEBUG_LEVEL=2
+ccflags-y += -Wall -Werror
+obj-m += ecm-wifi-plugin.o
+ecm-wifi-plugin-objs := \
+                        ecm_wifi_plugin_emesh.o \
+                        ecm_wifi_plugin_mscs.o \
+                        ecm_wifi_plugin_init.o
+
diff --git a/ecm_wifi_plugins/ecm_wifi_plugin.h b/ecm_wifi_plugins/ecm_wifi_plugin.h
new file mode 100644
index 0000000..2328df1
--- /dev/null
+++ b/ecm_wifi_plugins/ecm_wifi_plugin.h
@@ -0,0 +1,85 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+
+#include <qca_mscs_if.h>
+#include <qca_mesh_latency_if.h>
+#include <ecm_classifier_mscs_public.h>
+#include <ecm_classifier_emesh_public.h>
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define ecm_wifi_plugin_warning(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define ecm_wifi_plugin_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define ecm_wifi_plugin_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#if (ECM_WIFI_PLUGIN_DEBUG_LEVEL < 2)
+#define ecm_wifi_plugin_warning(s, ...)
+#else
+#define ecm_wifi_plugin_warning(s, ...) pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (ECM_WIFI_PLUGIN_DEBUG_LEVEL < 3)
+#define ecm_wifi_plugin_info(s, ...)
+#else
+#define ecm_wifi_plugin_info(s, ...)   pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (ECM_WIFI_PLUGIN_DEBUG_LEVEL < 4)
+#define ecm_wifi_plugin_trace(s, ...)
+#else
+#define ecm_wifi_plugin_trace(s, ...)  pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif
+
+/*
+ * ecm_wifi_plugin_mscs_register()
+ *	API to register mscs callbacks.
+ */
+extern int ecm_wifi_plugin_mscs_register(void);
+
+/*
+ * ecm_wifi_plugin_emesh_register()
+ *	API to register emesh callbacks.
+ */
+extern int ecm_wifi_plugin_emesh_register(void);
+
+/*
+ * ecm_wifi_plugin_mscs_unregister()
+ *	API to unregister the mscs callbacks.
+ */
+extern void ecm_wifi_plugin_mscs_unregister(void);
+
+/*
+ * ecm_wifi_plugin_emesh_unregister()
+ *	API to unregister the emesh callbacks.
+ */
+extern void ecm_wifi_plugin_emesh_unregister(void);
diff --git a/ecm_wifi_plugins/ecm_wifi_plugin_emesh.c b/ecm_wifi_plugins/ecm_wifi_plugin_emesh.c
new file mode 100644
index 0000000..5fa3b3e
--- /dev/null
+++ b/ecm_wifi_plugins/ecm_wifi_plugin_emesh.c
@@ -0,0 +1,59 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+
+#include "ecm_wifi_plugin.h"
+
+/*
+ * ecm_wifi_plugin_emesh
+ * 	Register EMESH client callback with ECM EMSH classifier to update peer mesh latency parameters.
+ */
+static struct ecm_classifier_emesh_callbacks ecm_wifi_plugin_emesh = {
+	.update_peer_mesh_latency_params = qca_mesh_latency_update_peer_parameter,
+};
+
+/*
+ * ecm_wifi_plugin_emesh_register()
+ *	Register emesh callbacks.
+ */
+int ecm_wifi_plugin_emesh_register(void)
+{
+	if (ecm_classifier_emesh_latency_config_callback_register(&ecm_wifi_plugin_emesh)) {
+		ecm_wifi_plugin_warning("ecm emesh classifier callback registration failed.\n");
+		return -1;
+	}
+
+	ecm_wifi_plugin_info("EMESH classifier callbacks registered\n");
+	return 0;
+}
+
+/*
+ * ecm_wifi_plugin_emesh_unregister()
+ *	unregister the emesh callbacks.
+ */
+void ecm_wifi_plugin_emesh_unregister(void)
+{
+	ecm_classifier_emesh_latency_config_callback_unregister();
+	ecm_wifi_plugin_info("EMESH classifier callbacks unregistered\n");
+}
diff --git a/ecm_wifi_plugins/ecm_wifi_plugin_init.c b/ecm_wifi_plugins/ecm_wifi_plugin_init.c
new file mode 100644
index 0000000..af82045
--- /dev/null
+++ b/ecm_wifi_plugins/ecm_wifi_plugin_init.c
@@ -0,0 +1,67 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+
+#include "ecm_wifi_plugin.h"
+
+/*
+ * ecm_wifi_plugin_init_module()
+ *	ECM_WIFI_PLUGIN module init function
+ */
+int __init ecm_wifi_plugin_init_module(void)
+{
+	int ret = 0;
+
+	ret = ecm_wifi_plugin_mscs_register();
+	if (ret) {
+		ecm_wifi_plugin_warning("MSCS callback registration failed\n");
+		return ret;
+	}
+
+	ret = ecm_wifi_plugin_emesh_register();
+	if (ret) {
+		ecm_wifi_plugin_warning("EMESH callback registration failed\n");
+		return ret;
+	}
+
+	ecm_wifi_plugin_info("ECM_WIFI_PLUGIN module loaded");
+	return 0;
+}
+
+/*
+ * ecm_wifi_plugin_exit_module()
+ *	ECM_WIFI_PLUGIN module exit function
+ */
+static void __exit ecm_wifi_plugin_exit_module(void)
+{
+	ecm_wifi_plugin_mscs_unregister();
+	ecm_wifi_plugin_emesh_unregister();
+	ecm_wifi_plugin_info("ECM_WIFI_PLUGIN unloaded\n");
+}
+
+module_init(ecm_wifi_plugin_init_module);
+module_exit(ecm_wifi_plugin_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("ECM_WIFI_PLUGIN module");
diff --git a/ecm_wifi_plugins/ecm_wifi_plugin_mscs.c b/ecm_wifi_plugins/ecm_wifi_plugin_mscs.c
new file mode 100644
index 0000000..b781108
--- /dev/null
+++ b/ecm_wifi_plugins/ecm_wifi_plugin_mscs.c
@@ -0,0 +1,59 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+
+#include "ecm_wifi_plugin.h"
+
+/*
+ * ecm_wifi_plugin
+ * 	Register MSCS client callback with ECM MSCS classifier to support MSCS wifi peer lookup.
+ */
+static struct ecm_classifier_mscs_callbacks ecm_wifi_plugin_mscs = {
+	.get_peer_priority = qca_mscs_peer_lookup_n_get_priority,
+};
+
+/*
+ * ecm_wifi_plugin_mscs_register()
+ *	register mscs callbacks.
+ */
+int ecm_wifi_plugin_mscs_register(void)
+{
+	if (ecm_classifier_mscs_callback_register(&ecm_wifi_plugin_mscs)) {
+		ecm_wifi_plugin_warning("ecm mscs classifier callback registration failed.\n");
+		return -1;
+	}
+
+	ecm_wifi_plugin_info("MSCS callbacks registered\n");
+	return 0;
+}
+
+/*
+ * ecm_wifi_plugin_mscs_unregister()
+ *	unregister the mscs callbacks.
+ */
+void ecm_wifi_plugin_mscs_unregister(void)
+{
+	ecm_classifier_mscs_callback_unregister();
+	ecm_wifi_plugin_info("MSCS callbacks unregistered\n");
+}
diff --git a/nat46/.gitignore b/nat46/.gitignore
new file mode 100644
index 0000000..bd9c9a7
--- /dev/null
+++ b/nat46/.gitignore
@@ -0,0 +1,15 @@
+
+# Ignore general build intermediate files
+*.o
+*.o.d
+*.cmd
+*.ko
+*.mod.*
+*.mod
+Module.symvers
+modules.order
+.tmp_versions
+built-in.a
+
+# don't ignore .gitignore itself
+!.gitignore
diff --git a/nat46/README.md b/nat46/README.md
new file mode 100644
index 0000000..ddebbdd
--- /dev/null
+++ b/nat46/README.md
@@ -0,0 +1,32 @@
+nat46
+=====
+
+This is an OpenWRT feed with a Linux kernel module implementing flexible NAT46.
+
+Compiling
+=========
+
+With Barrier Breaker (trunk), add the following line to *feeds.conf.default*:
+```
+src-git nat46 https://github.com/ayourtch/nat46.git
+```
+
+then issue:
+
+```
+./scripts/feeds update -a
+./scripts/feeds install -a -p nat46
+```
+
+This will cause the following to appear in the "make menuconfig":
+
+ * Kernel modules -> Network Support -> kmod-nat46
+
+Managing
+========
+
+The management of the NAT46 interfaces is done via the /proc/net/nat46/control file.
+
+For more information about the module, take a look at the nat46/modules/README file.
+
+
diff --git a/nat46/build.sh b/nat46/build.sh
new file mode 100755
index 0000000..9fccc30
--- /dev/null
+++ b/nat46/build.sh
@@ -0,0 +1,101 @@
+#!/bin/bash
+
+set -e
+set -o errtrace
+trap 'echo Fatal error: script $0 aborting at line $LINENO, command \"$BASH_COMMAND\" returned $?; exit 1' ERR
+
+PRODUCT_LIST="sirocco"
+
+NUM_JOBS=$(grep -c processor /proc/cpuinfo)
+
+MODULE_NAME="nat46"
+###################################################
+# Setup build toollchain
+###################################################
+sdk_top_dir=$(readlink -e $(dirname $0)/..)
+TOP_DIR=$(readlink -e ${sdk_top_dir}/..)
+
+#export ARCH and build related envs.
+source ${TOP_DIR}/sdk/build_scripts/setup_env.sh
+
+kernel_path=$(readlink -e ${sdk_top_dir}/../kernel)
+soc_type=ipq50xx
+nat64_version="1.0"
+extra_cflags=-D"NAT46_VERSION='\"1.0\"'"
+if [ "${ENABLE_64BIT_BUILD}" == "false" ]; then
+  extra_cflags="${extra_cflags} -mlong-calls"
+fi
+
+##################################################
+# Build Kernel Module
+##################################################
+function BuildKModule() {
+    # make kernel module
+    echo "Build ${MODULE_NAME}"
+    ${CROSS_MAKE} -C ${kernel_path} M=${sdk_top_dir}/${MODULE_NAME}/${MODULE_NAME}/modules SoC=${soc_type} EXTRA_CFLAGS="${extra_cflags}" V=1
+}
+
+##################################################
+# Build & Install
+##################################################
+function BuildAndInstall() {
+    local product=$1
+    local eureka_src_path=$(readlink -e $2)
+    if [ -z ${eureka_src_path} ]; then
+      echo "eureka_src_path doesn't exist"
+      exit 1
+    fi
+
+    # clean previous build
+    find . -name "*.o" -delete
+    find . -name "*.cmd" -delete
+    find . -name "*.ko" -delete
+    find . -name "*.mod.*" -delete
+    find . -name "*.mod" -delete
+    find . -name Module.symvers -delete
+
+    # build module
+    BuildKModule
+
+    # install module
+    echo "Install ${MODULE_NAME}.ko"
+    local module_target_dir="$(GetModulePath ${eureka_src_path} ${product})"
+    mkdir -p ${module_target_dir}
+    cp -f ${MODULE_NAME}/modules/${MODULE_NAME}.ko ${module_target_dir}/.
+}
+
+function Usage() {
+    cat << EOF
+Usage:
+    $0 <product> <eureka_src_path>
+    Valid products: ${PRODUCT_LIST}
+EOF
+}
+
+function IsProductValid() {
+  local product
+  local ret=1
+
+  for product in ${PRODUCT_LIST}; do
+    if [ "${product}" == "$1" ]; then
+      ret=0
+      break
+    fi
+  done
+
+  return ${ret}
+}
+
+#########################
+####### Main Entry ######
+#########################
+if (( $# < 2 )); then
+  Usage
+else
+  if IsProductValid $1; then
+    BuildAndInstall $1 $2
+  else
+    echo "$1 is a invalid product"
+    Usage
+  fi
+fi
diff --git a/nat46/nat46/Makefile b/nat46/nat46/Makefile
new file mode 100644
index 0000000..daedbac
--- /dev/null
+++ b/nat46/nat46/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright (C) 2006-2012 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=nat46
+PKG_VERSION:=0000000
+
+include $(INCLUDE_DIR)/package.mk
+
+define KernelPackage/nat46
+  DEPENDS:=+kmod-ipv6
+  TITLE:=Stateless NAT46 translation kernel module
+  SECTION:=kernel
+  SUBMENU:=Network Support
+  FILES:=$(PKG_BUILD_DIR)/modules/nat46.ko 
+endef
+
+
+define Build/Prepare
+	$(call Build/Prepare/Default)
+	$(CP) -r ./* $(PKG_BUILD_DIR)/
+endef
+
+
+MAKE_KMOD := $(MAKE) -C "$(LINUX_DIR)" \
+		CROSS_COMPILE="$(TARGET_CROSS)" \
+		ARCH="$(LINUX_KARCH)" \
+		PATH="$(TARGET_PATH)" \
+		SUBDIRS="$(PKG_BUILD_DIR)/kmod" \
+
+define Build/Compile
+	# Compile the kernel part
+	$(MAKE_KMOD) \
+		SUBDIRS="$(PKG_BUILD_DIR)/modules" \
+		MODFLAGS="-DMODULE -mlong-calls" \
+		modules
+	pwd
+endef
+
+define KernelPackage/nat46/install
+	$(CP) -r ./files/* $(1)/
+endef
+
+$(eval $(call KernelPackage,nat46))
+
+
+
diff --git a/nat46/nat46/README.md b/nat46/nat46/README.md
new file mode 100644
index 0000000..71c6547
--- /dev/null
+++ b/nat46/nat46/README.md
@@ -0,0 +1,2 @@
+See README in modules/
+
diff --git a/nat46/nat46/files/etc/modules.d/33-nat46 b/nat46/nat46/files/etc/modules.d/33-nat46
new file mode 100644
index 0000000..89285cb
--- /dev/null
+++ b/nat46/nat46/files/etc/modules.d/33-nat46
@@ -0,0 +1,2 @@
+nat46
+
diff --git a/nat46/nat46/modules/Makefile b/nat46/nat46/modules/Makefile
new file mode 100644
index 0000000..9380882
--- /dev/null
+++ b/nat46/nat46/modules/Makefile
@@ -0,0 +1,9 @@
+obj-m += nat46.o
+nat46-objs := nat46-netdev.o nat46-module.o nat46-core.o nat46-glue.o
+CFLAGS_nat46.o := -DDEBUG
+
+all:
+	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
+
+clean:
+	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
diff --git a/nat46/nat46/modules/README b/nat46/nat46/modules/README
new file mode 100644
index 0000000..b2c0bd3
--- /dev/null
+++ b/nat46/nat46/modules/README
@@ -0,0 +1,155 @@
+ABOUT AND USAGE
+---------------
+
+This is a generic stateless NAT46 kernel module for Linux.
+
+It supports multiple simultaneous instances of NAT46 on the same host,
+allowing to implement sophisticated translation strategies just 
+by using routing to direct the packets to the appropriate interface.
+
+Upon loading, it creates a file /proc/net/nat46/control, which is used 
+to interact with it.
+
+echo add <ifname> | sudo tee /proc/net/nat46/control
+	create a new nat46 interface with a specified name
+
+echo del <ifname> | sudo tee /proc/net/nat46/control
+	delete the existing nat46 interface with a specified name
+
+echo config <ifname> <cfg-strings> | sudo tee /proc/net/nat46/control
+	pass the <cfg-strings> data to configuration routine of
+	the respective nat46 interface. In case multiple rules are
+	present - this command controls the very last one in the ruleset.
+
+echo insert <ifname> <cfg-strings> | sudo tee /proc/net/nat46/control
+	insert a new rule with the specified config string at the head
+	of the rule set for the device.
+
+CONFIGURING NAT46 DEVICE
+-----------------------
+
+Configuration parameters for the device take form of "name value" pairs,
+with the following values:
+
+debug <level>
+	set the debug level on the device to <level>
+
+local.<param> <value>
+	set the local side translation rule's parameter <param> to <value>
+
+remote.<param> <value>
+	set the remote side tranlation rule's parameter <param> to <value>
+
+
+The rules for local and remote addresses are using the same mechanism for translation
+for greater flexibility and allow several arguments. The most important argument is 
+"style", which determines what kind of the translation mechanism is employed for 
+this rule:
+
+<rule>.style NONE
+	this is a very simplistic style: it always fails, unless you configure 
+	a /32 IPv4 prefix and a /128 IPv6 prefix - at which point it starts to 
+	function as a single 1:1 translation rule.
+
+	<rule>.v4 <v4addr>/32
+	<rule>.v6 <v6addr>/128
+		both of these parameters must be set for this translation style
+		to function properly. They define the two addresses for 
+		the 1:1 mapping.
+
+	<rule>.ea-len
+	<rule>.psid-offset
+	<rule>.fmr-flag
+		ignored in this translation style
+
+	NB: in the future this translation mechanism may be extended to allow 1:1
+	subnet mapping.
+
+<rule>.style RFC6052
+	this is a rule which allows to implement the mapping used in NAT64
+	environments to represent the entire IPv4 internet as an IPv6 prefix.
+
+	<rule>.v6 <v6pref>/<v6prefixlen>
+		this defines IPv6 prefix length to translate the IPv4 internet into.
+		The allowed prefix lengths are 32, 40, 48, 56, 64, 96.
+		If a disallowed length is used, the translation fails.
+
+	<rule>.v4 <v4pref>/<v4prefixlen>
+		this parameter is ignored for now in this translation style. 
+		For backwards compatibility it should be 0.0.0.0/0
+
+	<rule>.ea-len
+	<rule>.psid-offset
+	<rule>.fmr-flag
+		ignored in this translation style
+
+<rule>.style MAP
+	this is a translation rule for the MAP (Mapping Address and Port) algorithm,
+	which may include the layer 4 identifier (tcp/udp port or ICMP id).
+
+	<rule>.v6 <v6pref>/<v6prefixlen>
+		this parameter defines the MAP domain IPv6 prefix
+
+	<rule>.v4 <v6pref>/<v6prefixlen>
+		this parameter defines the MAP domain IPv4 prefix
+
+	<rule>.ea-len
+		this parameter defines the length of the embedded address bits
+		within the IPv6 prefix that has been allocated.
+
+	<rule>.psid-offset
+		this parameter specifies how many bits to the right to shift
+		the bits of the psid within the port value.
+
+	<rule>.fmr-flag
+		this parameter allows the "local" rule to be tried as a "remote" rule 
+		as well. In MAP terminology, this allows to implement FMR rule by just
+		setting this flag. This flag is used only on the "local" side, and is
+		ignored for the "remote" side.
+
+
+CODE STRUCTURE
+--------------
+
+There are several groups of files:
+
+nat46-module.*
+	These files deal with the overall Linux module handling: loading / unloading,
+	creating and destroying the /proc control file, as well as parsing the commands
+	to pass on to the netdev portion of the code.
+
+nat46-netdev.*
+	Network device management code. This module accepts the high-level commands and
+	performs the device-level work: locating the devices in the chain, grouping
+	the functions into the device structures, etc. This module adds the pointers 
+	the processing functions which are defined in the core group.
+
+nat46-core.*
+	Core processing routines. These do not do any netdevice/module work, they use 
+	primarily sk_buff and nat64_instance_t data structures in order to operate.
+	They use the Linux kernel and glue functions.
+
+nat46-glue.*
+	These are the "adaptation" functions, over time it is expected there will
+	be almost nothing. The reason for the "glue" code to exist is to share
+	the core code with userland implementations.
+
+
+ACKNOWLEDGEMENTS
+----------------
+
+This code has been inspired or uses some parts of the following:
+
+* CERNET MAP implementation
+
+  https://github.com/cernet/MAP
+
+* Stateful NAT64 kernel module implementation by Julius Kriukas
+
+  https://github.com/fln/nat64
+
+* Stateless NAT46 kernel module implementation by Tomasz Mrugalski
+
+  https://github.com/tomaszmrugalski/ip46nat
+
+
diff --git a/nat46/nat46/modules/nat46-core.c b/nat46/nat46/modules/nat46-core.c
new file mode 100644
index 0000000..4f152a7
--- /dev/null
+++ b/nat46/nat46/modules/nat46-core.c
@@ -0,0 +1,2489 @@
+/*
+ * core nat46 functionality.
+ * It does not know about network devices, modules or anything similar:
+ * those are abstracted away by other layers.
+ *
+ * Copyright (c) 2013-2014 Andrew Yourtchenko <ayourtch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <net/route.h>
+#include <linux/version.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,4,0)
+#include <net/ipv6_frag.h>
+#endif
+#include <net/netfilter/ipv6/nf_defrag_ipv6.h>
+
+#include "nat46-glue.h"
+#include "nat46-core.h"
+#include "nat46-module.h"
+
+static uint16_t xlate_pkt_in_err_v4_to_v6(nat46_instance_t *nat46, struct iphdr *iph,
+			struct sk_buff *old_skb, uint16_t *sport, uint16_t *dport);
+static DEFINE_SPINLOCK(port_id_lock);
+
+void
+nat46debug_dump(nat46_instance_t *nat46, int level, void *addr, int len)
+{
+  char tohex[] = "0123456789ABCDEF";
+  int i = 0;
+  int k = 0;
+  unsigned char *pc = addr;
+
+  char buf0[32];                // offset
+  char buf1[64];                // hex
+  char buf2[64];                // literal
+
+  char *pc1 = buf1;
+  char *pc2 = buf2;
+
+  while(--len >= 0) {
+    if(i % 16 == 0) {
+      for(k=0; k<9; k++) {
+        buf0[k] = 0;
+      }
+      for(k=0; k<8; k++) {
+        buf0[7-k] = tohex[ 0xf & (i >> k) ];
+      }
+      buf0[8] = 0;
+      buf1[0] = 0;
+      buf2[0] = 0;
+      pc1 = buf1;
+      pc2 = buf2;
+    }
+    *pc1++ = tohex[*pc >> 4];
+    *pc1++ = tohex[*pc & 15];
+    *pc1++ = ' ';
+
+    if(*pc >= 32 && *pc < 127) {
+      *pc2++ = *pc;
+    } else {
+      *pc2++ = '.';
+    }
+    i++;
+    pc++;
+    if(i % 16 == 0) {
+      *pc1 = 0;
+      *pc2 = 0;
+      nat46debug(level, "%s:   %s  %s", buf0, buf1, buf2);
+    }
+
+  }
+  if(i % 16 != 0) {
+    while(i % 16 != 0) {
+      *pc1++ = ' ';
+      *pc1++ = ' ';
+      *pc1++ = ' ';
+      *pc2++ = ' ';
+      i++;
+    }
+    *pc1 = 0;
+    *pc2 = 0;
+    nat46debug(level, "%s:   %s  %s", buf0, buf1, buf2);
+  }
+}
+
+/* return the current arg, and advance the tail to the next space-separated word */
+char *get_next_arg(char **ptail) {
+  char *pc = NULL;
+  while ((*ptail) && (**ptail) && ((**ptail == ' ') || (**ptail == '\n'))) {
+    **ptail = 0;
+    (*ptail)++;
+  }
+  pc = *ptail;
+
+  while ((*ptail) && (**ptail) && ((**ptail != ' ') && (**ptail != '\n'))) {
+    (*ptail)++;
+  }
+
+  while ((*ptail) && (**ptail) && ((**ptail == ' ') || (**ptail == '\n'))) {
+    **ptail = 0;
+    (*ptail)++;
+  }
+
+  if ((pc) && (0 == *pc)) {
+    pc = NULL;
+  }
+  return pc;
+}
+
+/*
+ * Parse an IPv6 address (if pref_len is NULL), or prefix (if it isn't).
+ * parses destructively (places \0 between address and prefix len)
+ */
+int try_parse_ipv6_prefix(struct in6_addr *pref, int *pref_len, char *arg) {
+  int err = 0;
+  char *arg_plen = strchr(arg, '/');
+  if (arg_plen) {
+    *arg_plen++ = 0;
+    if (pref_len) {
+      *pref_len = simple_strtol(arg_plen, NULL, 10);
+
+      /*
+       * ipv6 prefix should be <= 128
+       */
+      if (*pref_len > IPV6_BITS_MAX) {
+        return -1;
+      }
+    }
+  }
+  err = (1 != in6_pton(arg, -1, (u8 *)pref, '\0', NULL));
+  return err;
+}
+
+int try_parse_ipv4_prefix(u32 *v4addr, int *pref_len, char *arg) {
+  int err = 0;
+  char *arg_plen = strchr(arg, '/');
+  if (arg_plen) {
+    *arg_plen++ = 0;
+    if (pref_len) {
+      *pref_len = simple_strtol(arg_plen, NULL, 10);
+
+      /*
+       * ipv4 prefix len should be <= 32
+       */
+      if (*pref_len > IPV4_BITS_MAX) {
+        return -1;
+      }
+    }
+  }
+  err = (1 != in4_pton(arg, -1, (u8 *)v4addr, '/', NULL));
+  return err;
+}
+
+
+/*
+ * parse a rule argument and put config into a rule.
+ * advance the tail to prepare for the next arg parsing.
+ * destructive.
+ */
+
+int try_parse_rule_arg(nat46_xlate_rule_t *rule, char *arg_name, char **ptail) {
+  int err = 0;
+  char *val = get_next_arg(ptail);
+  if (NULL == val) {
+    err = -1;
+  } else if (0 == strcmp(arg_name, "v6")) {
+    err = try_parse_ipv6_prefix(&rule->v6_pref, &rule->v6_pref_len, val);
+  } else if (0 == strcmp(arg_name, "v4")) {
+    err = try_parse_ipv4_prefix(&rule->v4_pref, &rule->v4_pref_len, val);
+  } else if (0 == strcmp(arg_name, "ea-len")) {
+    rule->ea_len = simple_strtol(val, NULL, 10);
+  } else if (0 == strcmp(arg_name, "psid-offset")) {
+    rule->psid_offset = simple_strtol(val, NULL, 10);
+  } else if (0 == strcmp(arg_name, "style")) {
+    if (0 == strcmp("MAP", val)) {
+      rule->style = NAT46_XLATE_MAP;
+    } else if (0 == strcmp("MAP0", val)) {
+      rule->style = NAT46_XLATE_MAP0;
+    } else if (0 == strcmp("RFC6052", val)) {
+      rule->style = NAT46_XLATE_RFC6052;
+    } else if (0 == strcmp("NONE", val)) {
+      rule->style = NAT46_XLATE_NONE;
+    } else {
+      err = 1;
+    }
+  }
+  return err;
+}
+
+static inline void nat46_swap(nat46_xlate_rulepair_t *var1, nat46_xlate_rulepair_t *var2) {
+	nat46_xlate_rulepair_t temp;
+	temp = *var1;
+	*var1 = *var2;
+	*var2 = temp;
+}
+
+/*
+ * Sort rule pairs based on prefix length.
+ */
+void nat46_sort_rule_array(nat46_instance_t *nat46) {
+	int i, j;
+	int nelem = nat46->npairs;
+	nat46_xlate_rulepair_t *array = NULL;
+
+	memcpy(nat46->sorted_ipv4_local_pairs, nat46->pairs, nelem * sizeof(nat46_xlate_rulepair_t));
+	memcpy(nat46->sorted_ipv4_remote_pairs, nat46->pairs, nelem * sizeof(nat46_xlate_rulepair_t));
+	memcpy(nat46->sorted_ipv6_local_pairs, nat46->pairs, nelem * sizeof(nat46_xlate_rulepair_t));
+	memcpy(nat46->sorted_ipv6_remote_pairs, nat46->pairs, nelem * sizeof(nat46_xlate_rulepair_t));
+
+	array = &nat46->sorted_ipv4_local_pairs[0];
+	for (i = 0; i < nelem - 1; i++) {
+		for (j = 0; j < nelem - i - 1; j++) {
+			if (array[j].local.v4_pref_len < array[j+1].local.v4_pref_len) {
+				nat46_swap (&array[j], &array[j+1]);
+			}
+		}
+	}
+
+	array = &nat46->sorted_ipv4_remote_pairs[0];
+	for (i = 0; i < nelem - 1; i++) {
+		for (j = 0; j < nelem - i - 1; j++) {
+			if (array[j].remote.v4_pref_len < array[j+1].remote.v4_pref_len) {
+				nat46_swap (&array[j], &array[j+1]);
+			}
+		}
+	}
+
+	array = &nat46->sorted_ipv6_local_pairs[0];
+	for (i = 0; i < nelem - 1; i++) {
+		for (j = 0; j < nelem - i - 1; j++) {
+			if (array[j].local.v6_pref_len < array[j+1].local.v6_pref_len) {
+				nat46_swap (&array[j], &array[j+1]);
+			}
+		}
+	}
+
+	array = &nat46->sorted_ipv6_remote_pairs[0];
+	for (i = 0; i < nelem - 1; i++) {
+		for (j = 0; j < nelem - i - 1; j++) {
+			if (array[j].remote.v6_pref_len < array[j+1].remote.v6_pref_len) {
+				nat46_swap (&array[j], &array[j+1]);
+			}
+		}
+	}
+}
+
+bool nat46_validate_RFC6052_style(nat46_instance_t *nat46, nat46_xlate_rule_t rule)
+{
+	if (rule.style == NAT46_XLATE_RFC6052) {
+		if (!((rule.v6_pref_len == 32) || (rule.v6_pref_len == 40) ||
+					(rule.v6_pref_len == 48) || (rule.v6_pref_len == 56) ||
+					(rule.v6_pref_len == 64) || (rule.v6_pref_len == 96))) {
+			nat46debug(3, "IPv6 prefix len is invalid");
+			return false;
+		}
+	}
+	return true;
+}
+
+bool nat46_validate_MAP_style(nat46_instance_t *nat46, nat46_xlate_rule_t rule)
+{
+	int psid_len;
+	if (rule.style == NAT46_XLATE_MAP) {
+
+		/*
+		 * max ea_len is 48
+		 */
+		if (rule.ea_len > EA_LEN_MAX) {
+			nat46debug(3, "EA-length should not exceed 48");
+			return false;
+		}
+
+		if (rule.v4_pref_len + rule.ea_len > IPV4_BITS_MAX) {
+			psid_len = rule.ea_len - (IPV4_BITS_MAX - rule.v4_pref_len);
+		} else {
+			psid_len = 0;
+		}
+
+		if (psid_len + rule.psid_offset > PSID_LEN_MAX) {
+			nat46debug(3, "psid_len + psid_offset should not exceed 16");
+			return false;
+		}
+	}
+	return true;
+}
+
+int nat46_validate_ipair_config(nat46_instance_t *nat46, nat46_xlate_rulepair_t *apair)
+{
+	if (!nat46_validate_RFC6052_style(nat46, apair->local)) {
+		return -1;
+	}
+
+	if (!nat46_validate_RFC6052_style(nat46, apair->remote)) {
+		return -1;
+	}
+
+	if (!nat46_validate_MAP_style(nat46, apair->local)) {
+		return -1;
+	}
+
+	if (!nat46_validate_MAP_style(nat46, apair->remote)) {
+		return -1;
+	}
+	return 0;
+}
+
+/*
+ * Parse the config commands in the buffer,
+ * destructive (puts zero between the args)
+ */
+int nat46_set_ipair_config(nat46_instance_t *nat46, int ipair, char *buf, int count) {
+  char *tail = buf;
+  char *arg_name;
+  int err = 0;
+  char *val;
+  nat46_xlate_rulepair_t *apair = NULL;
+
+  if ((ipair < 0) || (ipair >= nat46->npairs)) {
+    return -1;
+  }
+
+  apair = &nat46->pairs[ipair];
+
+  while ((0 == err) && (NULL != (arg_name = get_next_arg(&tail)))) {
+    if (0 == strcmp(arg_name, "debug")) {
+      val = get_next_arg(&tail);
+      if (val) {
+        nat46->debug = simple_strtol(val, NULL, 10);
+      }
+    } else if (arg_name == strstr(arg_name, "local.")) {
+      arg_name += strlen("local.");
+      nat46debug(13, "Setting local xlate parameter");
+      err = try_parse_rule_arg(&apair->local, arg_name, &tail);
+    } else if (arg_name == strstr(arg_name, "remote.")) {
+      arg_name += strlen("remote.");
+      nat46debug(13, "Setting remote xlate parameter");
+      err = try_parse_rule_arg(&apair->remote, arg_name, &tail);
+    }
+  }
+
+  err = nat46_validate_ipair_config(nat46, apair);
+  if (err) {
+    return err;
+  }
+
+  /*
+   * sort nat46->pairs based on prefix length.
+   */
+  nat46_sort_rule_array(nat46);
+
+  return 0;
+}
+
+int nat46_set_config(nat46_instance_t *nat46, char *buf, int count) {
+  int ret = -1;
+  if (nat46->npairs > 0) {
+    ret = nat46_set_ipair_config(nat46, nat46->npairs-1, buf, count);
+  }
+  return ret;
+}
+
+char *xlate_style_to_string(nat46_xlate_style_t style) {
+  switch(style) {
+    case NAT46_XLATE_NONE:
+      return "NONE";
+    case NAT46_XLATE_MAP:
+      return "MAP";
+    case NAT46_XLATE_MAP0:
+      return "MAP0";
+    case NAT46_XLATE_RFC6052:
+      return "RFC6052";
+  }
+  return "unknown";
+}
+
+/*
+ * Get the nat46 configuration into a supplied buffer (if non-null).
+ */
+int nat46_get_ipair_config(nat46_instance_t *nat46, int ipair, char *buf, int count) {
+  int ret = 0;
+  nat46_xlate_rulepair_t *apair = NULL;
+  char *format = "local.v4 %pI4/%d local.v6 %pI6c/%d local.style %s local.ea-len %d local.psid-offset %d remote.v4 %pI4/%d remote.v6 %pI6c/%d remote.style %s remote.ea-len %d remote.psid-offset %d debug %d";
+
+  if ((ipair < 0) || (ipair >= nat46->npairs)) {
+    return ret;
+  }
+  apair = &nat46->pairs[ipair];
+
+  ret = snprintf(buf, count, format,
+		&apair->local.v4_pref, apair->local.v4_pref_len,
+		&apair->local.v6_pref, apair->local.v6_pref_len,
+		xlate_style_to_string(apair->local.style),
+		apair->local.ea_len, apair->local.psid_offset,
+
+		&apair->remote.v4_pref, apair->remote.v4_pref_len,
+		&apair->remote.v6_pref, apair->remote.v6_pref_len,
+		xlate_style_to_string(apair->remote.style),
+		apair->remote.ea_len, apair->remote.psid_offset,
+
+		nat46->debug);
+  return ret;
+}
+
+int nat46_get_config(nat46_instance_t *nat46, char *buf, int count) {
+  int ret = 0;
+  if (nat46->npairs > 0) {
+    ret = nat46_get_ipair_config(nat46, nat46->npairs-1, buf, count);
+  } else {
+    nat46debug(0, "nat46_get_config: npairs is 0");
+  }
+  return ret;
+}
+
+
+/********************************************************************
+
+From RFC6052, section 2.2:
+
+    +--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
+    |PL| 0-------------32--40--48--56--64--72--80--88--96--104---------|
+    +--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
+    |32|     prefix    |v4(32)         | u | suffix                    |
+    +--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
+    |40|     prefix        |v4(24)     | u |(8)| suffix                |
+    +--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
+    |48|     prefix            |v4(16) | u | (16)  | suffix            |
+    +--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
+    |56|     prefix                |(8)| u |  v4(24)   | suffix        |
+    +--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
+    |64|     prefix                    | u |   v4(32)      | suffix    |
+    +--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
+    |96|     prefix                                    |    v4(32)     |
+    +--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
+
+********************************************************************/
+
+void xlate_v4_to_nat64(nat46_instance_t *nat46, nat46_xlate_rule_t *rule, void *pipv4, void *pipv6) {
+  char *ipv4 = pipv4;
+  char *ipv6 = pipv6;
+
+  /* 'u' byte and suffix are zero */
+  memset(&ipv6[8], 0, 8);
+  switch(rule->v6_pref_len) {
+    case 32:
+      memcpy(ipv6, &rule->v6_pref, 4);
+      memcpy(&ipv6[4], ipv4, 4);
+      break;
+    case 40:
+      memcpy(ipv6, &rule->v6_pref, 5);
+      memcpy(&ipv6[5], ipv4, 3);
+      ipv6[9] = ipv4[3];
+      break;
+    case 48:
+      memcpy(ipv6, &rule->v6_pref, 6);
+      ipv6[6] = ipv4[0];
+      ipv6[7] = ipv4[1];
+      ipv6[9] = ipv4[2];
+      ipv6[10] = ipv4[3];
+      break;
+    case 56:
+      memcpy(ipv6, &rule->v6_pref, 7);
+      ipv6[7] = ipv4[0];
+      ipv6[9] = ipv4[1];
+      ipv6[10] = ipv4[2];
+      ipv6[11] = ipv4[3];
+      break;
+    case 64:
+      memcpy(ipv6, &rule->v6_pref, 8);
+      memcpy(&ipv6[9], ipv4, 4);
+      break;
+    case 96:
+      memcpy(ipv6, &rule->v6_pref, 12);
+      memcpy(&ipv6[12], ipv4, 4);
+      break;
+  }
+}
+
+int xlate_nat64_to_v4(nat46_instance_t *nat46, nat46_xlate_rule_t *rule, void *pipv6, void *pipv4) {
+  char *ipv4 = pipv4;
+  char *ipv6 = pipv6;
+  int cmp = -1;
+  int v6_pref_len = rule->v6_pref_len;
+
+  switch(v6_pref_len) {
+    case 32:
+      cmp = memcmp(ipv6, &rule->v6_pref, 4);
+      break;
+    case 40:
+      cmp = memcmp(ipv6, &rule->v6_pref, 5);
+      break;
+    case 48:
+      cmp = memcmp(ipv6, &rule->v6_pref, 6);
+      break;
+    case 56:
+      cmp = memcmp(ipv6, &rule->v6_pref, 7);
+      break;
+    case 64:
+      cmp = memcmp(ipv6, &rule->v6_pref, 8);
+      break;
+    case 96:
+      cmp = memcmp(ipv6, &rule->v6_pref, 12);
+      break;
+  }
+  if (cmp) {
+    /* Not in NAT64 prefix */
+    return 0;
+  }
+  switch(v6_pref_len) {
+    case 32:
+      memcpy(ipv4, &ipv6[4], 4);
+      break;
+    case 40:
+      memcpy(ipv4, &ipv6[5], 3);
+      ipv4[3] = ipv6[9];
+      break;
+    case 48:
+      ipv4[0] = ipv6[6];
+      ipv4[1] = ipv6[7];
+      ipv4[2] = ipv6[9];
+      ipv4[3] = ipv6[10];
+      break;
+    case 56:
+      ipv4[0] = ipv6[7];
+      ipv4[1] = ipv6[9];
+      ipv4[2] = ipv6[10];
+      ipv4[3] = ipv6[11];
+      break;
+    case 64:
+      memcpy(ipv4, &ipv6[9], 4);
+      break;
+    case 96:
+      memcpy(ipv4, &ipv6[12], 4);
+      break;
+  }
+  return 1;
+}
+
+/*
+
+The below bitarray copy code is from
+
+http://stackoverflow.com/questions/3534535/whats-a-time-efficient-algorithm-to-copy-unaligned-bit-arrays
+
+*/
+
+#define CHAR_BIT 8
+#define PREPARE_FIRST_COPY()                                      \
+    do {                                                          \
+    if (src_len >= (CHAR_BIT - dst_offset_modulo)) {              \
+        *dst     &= reverse_mask[dst_offset_modulo];              \
+        src_len -= CHAR_BIT - dst_offset_modulo;                  \
+    } else {                                                      \
+        *dst     &= reverse_mask[dst_offset_modulo]               \
+              | reverse_mask_xor[dst_offset_modulo + src_len + 1];\
+         c       &= reverse_mask[dst_offset_modulo + src_len    ];\
+        src_len = 0;                                              \
+    } } while (0)
+
+
+static void
+bitarray_copy(const void *src_org, int src_offset, int src_len,
+                    void *dst_org, int dst_offset)
+{
+/*
+    static const unsigned char mask[] =
+        { 0x55, 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff };
+*/
+    static const unsigned char reverse_mask[] =
+        { 0x55, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe, 0xff };
+    static const unsigned char reverse_mask_xor[] =
+        { 0xff, 0x7f, 0x3f, 0x1f, 0x0f, 0x07, 0x03, 0x01, 0x00 };
+
+    if (src_len) {
+        const unsigned char *src;
+              unsigned char *dst;
+        int                  src_offset_modulo,
+                             dst_offset_modulo;
+
+        src = src_org + (src_offset / CHAR_BIT);
+        dst = dst_org + (dst_offset / CHAR_BIT);
+
+        src_offset_modulo = src_offset % CHAR_BIT;
+        dst_offset_modulo = dst_offset % CHAR_BIT;
+
+        if (src_offset_modulo == dst_offset_modulo) {
+            int              byte_len;
+            int              src_len_modulo;
+            if (src_offset_modulo) {
+                unsigned char   c;
+
+                c = reverse_mask_xor[dst_offset_modulo]     & *src++;
+
+                PREPARE_FIRST_COPY();
+                *dst++ |= c;
+            }
+
+            byte_len = src_len / CHAR_BIT;
+            src_len_modulo = src_len % CHAR_BIT;
+
+            if (byte_len) {
+                memcpy(dst, src, byte_len);
+                src += byte_len;
+                dst += byte_len;
+            }
+            if (src_len_modulo) {
+                *dst     &= reverse_mask_xor[src_len_modulo];
+                *dst |= reverse_mask[src_len_modulo]     & *src;
+            }
+        } else {
+            int             bit_diff_ls,
+                            bit_diff_rs;
+            int             byte_len;
+            int             src_len_modulo;
+            unsigned char   c;
+            /*
+             * Begin: Line things up on destination.
+             */
+            if (src_offset_modulo > dst_offset_modulo) {
+                bit_diff_ls = src_offset_modulo - dst_offset_modulo;
+                bit_diff_rs = CHAR_BIT - bit_diff_ls;
+
+                c = *src++ << bit_diff_ls;
+                c |= *src >> bit_diff_rs;
+                c     &= reverse_mask_xor[dst_offset_modulo];
+            } else {
+                bit_diff_rs = dst_offset_modulo - src_offset_modulo;
+                bit_diff_ls = CHAR_BIT - bit_diff_rs;
+
+                c = *src >> bit_diff_rs     &
+                    reverse_mask_xor[dst_offset_modulo];
+            }
+            PREPARE_FIRST_COPY();
+            *dst++ |= c;
+
+            /*
+             * Middle: copy with only shifting the source.
+             */
+            byte_len = src_len / CHAR_BIT;
+
+            while (--byte_len >= 0) {
+                c = *src++ << bit_diff_ls;
+                c |= *src >> bit_diff_rs;
+                *dst++ = c;
+            }
+
+            /*
+             * End: copy the remaining bits;
+             */
+            src_len_modulo = src_len % CHAR_BIT;
+            if (src_len_modulo) {
+                c = *src++ << bit_diff_ls;
+                c |= *src >> bit_diff_rs;
+                c     &= reverse_mask[src_len_modulo];
+
+                *dst     &= reverse_mask_xor[src_len_modulo];
+                *dst |= c;
+            }
+        }
+    }
+}
+
+int xlate_map_v4_to_v6(nat46_instance_t *nat46, nat46_xlate_rule_t *rule, void *pipv4, void *pipv6, uint16_t *pl4id, int map_version) {
+  int ret = 0;
+  u32 *pv4u32 = pipv4;
+  uint8_t *p6 = pipv6;
+
+  uint16_t psid;
+  uint16_t l4id = pl4id ? *pl4id : 0;
+  uint8_t psid_bits_len = rule->ea_len - (32 - rule->v4_pref_len);
+  uint8_t v4_lsb_bits_len = 32 - rule->v4_pref_len;
+
+  /* check that the ipv4 address is within the IPv4 map domain and reject if not */
+
+  if ( (ntohl(*pv4u32) & (0xffffffff << v4_lsb_bits_len)) != ntohl(rule->v4_pref) ) {
+    nat46debug(5, "xlate_map_v4_to_v6: IPv4 address %pI4 outside of MAP domain %pI4/%d", pipv4, &rule->v4_pref, rule->v4_pref_len);
+    return 0;
+  }
+
+  if (rule->ea_len < (32 - rule->v4_pref_len) ) {
+    nat46debug(0, "xlate_map_v4_to_v6: rule->ea_len < (32 - rule->v4_pref_len)");
+    return 0;
+  }
+
+  if (!pl4id && psid_bits_len) {
+    nat46debug(5, "xlate_map_v4_to_v6: l4id required for MAP domain %pI4/%d (ea-len %d)", &rule->v4_pref, rule->v4_pref_len, rule->ea_len);
+    return 0;
+  }
+
+  /* zero out the IPv6 address */
+  memset(pipv6, 0, 16);
+
+  psid = (ntohs(l4id) >> (16 - psid_bits_len - rule->psid_offset)) & (0xffff >> (16 - psid_bits_len));
+  nat46debug(10, "xlate_map_v4_to_v6: ntohs(l4id): %04x psid_bits_len: %d, rule psid-offset: %d, psid: %d\n", ntohs(l4id), psid_bits_len, rule->psid_offset, psid);
+
+  /*
+   *     create the IID. pay the attention there can be two formats:
+   *
+   *     draft-ietf-softwire-map-t-00:
+   *
+   *
+   *   +--+---+---+---+---+---+---+---+---+
+   *   |PL|   8  16  24  32  40  48  56   |
+   *   +--+---+---+---+---+---+---+---+---+
+   *   |64| u | IPv4 address  |  PSID | 0 |
+   *   +--+---+---+---+---+---+---+---+---+
+   *
+   *
+   *     latest draft-ietf-softwire-map-t:
+   *
+   *   |        128-n-o-s bits            |
+   *   | 16 bits|    32 bits     | 16 bits|
+   *   +--------+----------------+--------+
+   *   |   0    |  IPv4 address  |  PSID  |
+   *   +--------+----------------+--------+
+   *
+   *   In the case of an IPv4 prefix, the IPv4 address field is right-padded
+   *   with zeros up to 32 bits.  The PSID is zero left-padded to create a
+   *   16 bit field.  For an IPv4 prefix or a complete IPv4 address, the
+   *   PSID field is zero.
+   *
+   *   If the End-user IPv6 prefix length is larger than 64, the most
+   *   significant parts of the interface identifier is overwritten by the
+   *   prefix.
+   *
+   */
+  if (map_version) {
+    p6[8] = p6[9] = 0;
+    p6[10] = 0xff & (ntohl(*pv4u32) >> 24);
+    p6[11] = 0xff & (ntohl(*pv4u32) >> 16);
+    p6[12] = 0xff & (ntohl(*pv4u32) >> 8);
+    p6[13] = 0xff & (ntohl(*pv4u32));
+    p6[14] = 0xff & (psid >> 8);
+    p6[15] = 0xff & (psid);
+  } else {
+    p6[8]  = 0;
+    p6[9]  = 0xff & (ntohl(*pv4u32) >> 24);
+    p6[10] = 0xff & (ntohl(*pv4u32) >> 16);
+    p6[11] = 0xff & (ntohl(*pv4u32) >> 8);
+    p6[12] = 0xff & (ntohl(*pv4u32));
+    p6[13] = 0xff & (psid >> 8);
+    p6[14] = 0xff & (psid);
+    p6[15] = 0;
+    /* old EID */
+  }
+
+  /* copy the necessary part of domain IPv6 prefix into place, w/o overwriting the existing data */
+  bitarray_copy(&rule->v6_pref, 0, rule->v6_pref_len, p6, 0);
+
+  if (v4_lsb_bits_len) {
+    /* insert the lower 32-v4_pref_len bits of IPv4 address at rule->v6_pref_len */
+    bitarray_copy(pipv4, rule->v4_pref_len, v4_lsb_bits_len, p6, rule->v6_pref_len);
+  }
+
+  if (psid_bits_len) {
+    /* insert the psid bits at rule->v6_pref_len + v4_lsb_bits */
+    bitarray_copy(&l4id, rule->psid_offset, psid_bits_len, p6, rule->v6_pref_len + v4_lsb_bits_len);
+  }
+
+  ret = 1;
+
+  return ret;
+}
+
+int xlate_map_v6_to_v4(nat46_instance_t *nat46, nat46_xlate_rule_t *rule, void *pipv6, void *pipv4, int version) {
+  uint8_t v4_lsb_bits_len = 32 - rule->v4_pref_len;
+
+  if (memcmp(pipv6, &rule->v6_pref, rule->v6_pref_len/8)) {
+    /* address not within the MAP IPv6 prefix */
+    nat46debug(5, "xlate_map_v6_to_v4: IPv6 address %pI6 outside of MAP domain %pI6/%d", pipv6, &rule->v6_pref, rule->v6_pref_len);
+    return 0;
+  }
+  if (rule->v6_pref_len % 8) {
+    uint8_t mask = 0xff << (8 - (rule->v6_pref_len % 8));
+    uint8_t *pa1 = (uint8_t *)pipv6 + (rule->v6_pref_len/8);
+    uint8_t *pa2 = (uint8_t *)&rule->v6_pref + (rule->v6_pref_len/8);
+
+    if ( (*pa1 & mask) != (*pa2 & mask) ) {
+      nat46debug(5, "xlate_map_v6_to_v4: IPv6 address %pI6 outside of MAP domain %pI6/%d (LSB)", pipv6, &rule->v6_pref, rule->v6_pref_len);
+      return 0;
+    }
+  }
+
+  if (rule->ea_len < (32 - rule->v4_pref_len) ) {
+    nat46debug(0, "xlate_map_v6_to_v4: rule->ea_len < (32 - rule->v4_pref_len)");
+    return 0;
+  }
+
+  memcpy(pipv4, &rule->v4_pref, 4);
+  if (v4_lsb_bits_len) {
+    bitarray_copy(pipv6, rule->v6_pref_len, v4_lsb_bits_len, pipv4, rule->v4_pref_len);
+  }
+  /*
+   * I do not verify the PSID here. The idea is that if the destination port is incorrect, this
+   * will be caught in the NAT44 module.
+   */
+  return 1;
+}
+
+int xlate_v4_to_v6(nat46_instance_t *nat46, nat46_xlate_rule_t *rule, void *pipv4, void *pipv6, uint16_t *pl4id) {
+  int ret = 0;
+  switch(rule->style) {
+    case NAT46_XLATE_NONE: /* always fail unless it is a host 1:1 translation */
+      if ( (rule->v6_pref_len == 128) && (rule->v4_pref_len == 32) &&
+           (0 == memcmp(pipv4, &rule->v4_pref, sizeof(rule->v4_pref))) ) {
+         memcpy(pipv6, &rule->v6_pref, sizeof(rule->v6_pref));
+         ret = 1;
+      }
+      break;
+    case NAT46_XLATE_MAP0:
+      ret = xlate_map_v4_to_v6(nat46, rule, pipv4, pipv6, pl4id, 0);
+      break;
+    case NAT46_XLATE_MAP:
+      ret = xlate_map_v4_to_v6(nat46, rule, pipv4, pipv6, pl4id, 1);
+      break;
+    case NAT46_XLATE_RFC6052:
+      xlate_v4_to_nat64(nat46, rule, pipv4, pipv6);
+      /* NAT46 rules using RFC6052 always succeed since they can map any IPv4 address */
+      ret = 1;
+      break;
+  }
+  return ret;
+}
+
+int xlate_v6_to_v4(nat46_instance_t *nat46, nat46_xlate_rule_t *rule, void *pipv6, void *pipv4) {
+  int ret = 0;
+  switch(rule->style) {
+    case NAT46_XLATE_NONE: /* always fail unless it is a host 1:1 translation */
+      if ( (rule->v6_pref_len == 128) && (rule->v4_pref_len == 32) &&
+           (0 == memcmp(pipv6, &rule->v6_pref, sizeof(rule->v6_pref))) ) {
+         memcpy(pipv4, &rule->v4_pref, sizeof(rule->v4_pref));
+         ret = 1;
+      }
+      break;
+    case NAT46_XLATE_MAP0:
+      ret = xlate_map_v6_to_v4(nat46, rule, pipv6, pipv4, 0);
+      break;
+    case NAT46_XLATE_MAP:
+      ret = xlate_map_v6_to_v4(nat46, rule, pipv6, pipv4, 1);
+      break;
+    case NAT46_XLATE_RFC6052:
+      ret = xlate_nat64_to_v4(nat46, rule, pipv6, pipv4);
+      break;
+  }
+  return ret;
+}
+
+__sum16 csum16_upd(__sum16 csum, u16 old, u16 new) {
+  u32 s;
+  csum = ntohs(~csum);
+  s = (u32)csum + ntohs(~old) + ntohs(new);
+  s = ((s >> 16) & 0xffff) + (s & 0xffff);
+  s += ((s >> 16) & 0xffff);
+  return htons((u16)(~s));
+}
+
+/* Add the TCP/UDP pseudoheader, basing on the existing checksum */
+
+__sum16 csum_tcpudp_remagic(__be32 saddr, __be32 daddr, unsigned short len,
+                  unsigned char proto, u16 csum) {
+  u16 *pdata;
+  u16 len0, len1;
+
+  pdata = (u16 *)&saddr;
+  csum = csum16_upd(csum, 0, *pdata++);
+  csum = csum16_upd(csum, 0, *pdata++);
+  pdata = (u16 *)&daddr;
+  csum = csum16_upd(csum, 0, *pdata++);
+  csum = csum16_upd(csum, 0, *pdata++);
+
+  csum = csum16_upd(csum, 0, htons(proto));
+  len1 = htons( (len >> 16) & 0xffff );
+  len0 = htons(len & 0xffff);
+  csum = csum16_upd(csum, 0, len1);
+  csum = csum16_upd(csum, 0, len0);
+  return csum;
+}
+
+/* Undo the IPv6 pseudoheader inclusion into the checksum */
+__sum16 csum_ipv6_unmagic(nat46_instance_t *nat46, const struct in6_addr *saddr,
+                        const struct in6_addr *daddr,
+                        __u32 len, unsigned short proto,
+                        __sum16 csum) {
+  u16 *pdata;
+  int i;
+  u16 len0, len1;
+
+  pdata = (u16 *)saddr;
+  for(i=0;i<8;i++) {
+    csum = csum16_upd(csum, *pdata, 0);
+    pdata++;
+  }
+  pdata = (u16 *)daddr;
+  for(i=0;i<8;i++) {
+    csum = csum16_upd(csum, *pdata, 0);
+    pdata++;
+  }
+  csum = csum16_upd(csum, htons(proto), 0);
+  len1 = htons( (len >> 16) & 0xffff );
+  len0 = htons(len & 0xffff);
+  csum = csum16_upd(csum, len1, 0);
+  csum = csum16_upd(csum, len0, 0);
+  return csum;
+}
+
+/* Update ICMPv6 type/code with incremental checksum adjustment */
+void update_icmp6_type_code(nat46_instance_t *nat46, struct icmp6hdr *icmp6h, u8 type, u8 code) {
+  u16 old_tc = *((u16 *)icmp6h);
+  u16 new_tc;
+  u16 old_csum = icmp6h->icmp6_cksum;
+  u16 new_csum;
+  icmp6h->icmp6_type = type;
+  icmp6h->icmp6_code = code;
+  new_tc = *((u16 *)icmp6h);
+  /* https://tools.ietf.org/html/rfc1624 */
+  new_csum = csum16_upd(old_csum, old_tc, new_tc);
+  nat46debug(1, "Updating the ICMPv6 type to ICMP type %d and code to %d. Old T/C: %04X, New T/C: %04X, Old CS: %04X, New CS: %04X", type, code, old_tc, new_tc, old_csum, new_csum);
+  icmp6h->icmp6_cksum = new_csum;
+}
+
+
+u16 get_next_ip_id(void) {
+  static u16 id = 0;
+  return id++;
+}
+
+u16 fold_ipv6_frag_id(u32 v6id) {
+  return ((0xffff & (v6id >> 16)) ^ (v6id & 0xffff));
+}
+
+void *add_offset(void *ptr, u16 offset) {
+  return (((char *)ptr)+offset);
+}
+
+
+/* FIXME: traverse the headers properly */
+void *get_next_header_ptr6(void *pv6, int v6_len) {
+  struct ipv6hdr *ip6h = pv6;
+  void *ret = (ip6h+1);
+
+  if (ip6h->nexthdr == NEXTHDR_FRAGMENT) {
+    struct frag_hdr *fh = (struct frag_hdr*)(ip6h + 1);
+    if(fh->frag_off == 0) {
+      /* Atomic fragment */
+      ret = add_offset(ret, 8);
+    }
+  }
+  return ret;
+}
+
+void fill_v6hdr_from_v4hdr(struct iphdr *iph, struct ipv6hdr *ip6h) {
+  *((__be16 *)ip6h) = htons((6 << 12) | (iph->tos << 4));	/* Version, Traffic Class */
+  memset(&(ip6h->flow_lbl), 0, sizeof(ip6h->flow_lbl));		/* Flowlabel */
+  ip6h->payload_len = htons(ntohs(iph->tot_len) - IPV4HDRSIZE);
+  ip6h->nexthdr = iph->protocol;
+  ip6h->hop_limit = iph->ttl;
+}
+
+void fill_v4hdr_from_v6hdr(struct iphdr * iph, struct ipv6hdr *ip6h, __u32 v4saddr, __u32 v4daddr, __u16 id, __u16 frag_off, __u16 proto, int l3_payload_len) {
+  uint32_t ver_class_flow = ntohl(*(__be32 *)ip6h);
+  iph->ttl = ip6h->hop_limit;
+  iph->saddr = v4saddr;
+  iph->daddr = v4daddr;
+  iph->protocol = proto;
+  *((__be16 *)iph) = htons((4 << 12) | (5 << 8) | ((ver_class_flow >> 20) & 0xff));
+  iph->frag_off = frag_off;
+  iph->id = id;
+  iph->tot_len = htons( l3_payload_len + IPV4HDRSIZE );
+  iph->check = 0;
+  iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
+}
+
+u16 unchecksum16(void *p, int count, u16 csum) {
+  u16 *pu16 = p;
+  int i = count;
+  while(i--) {
+    csum = csum16_upd(csum, *pu16++, 0);
+  }
+  return csum;
+}
+
+u16 rechecksum16(void *p, int count, u16 csum) {
+  u16 *pu16 = p;
+  int i = count;
+  while(i--) {
+    csum = csum16_upd(csum, 0, *pu16++);
+  }
+  return csum;
+}
+
+/* Last rule in group must not have "none" as either source or destination */
+int is_last_pair_in_group(nat46_xlate_rulepair_t *apair) {
+  return ( (apair->local.style != NAT46_XLATE_NONE) && (apair->remote.style != NAT46_XLATE_NONE) );
+}
+
+nat46_xlate_rulepair_t *nat46_lpm(nat46_instance_t *nat46, nat46_rule_type_t type, void *paddr) {
+	int ipair = 0;
+	nat46_xlate_rulepair_t *apair = NULL;
+	uint32_t mask = 0;
+	uint8_t *pa1;
+	uint8_t *pa2;
+
+	if(!nat46 || !paddr) {
+		return NULL;
+	}
+
+	switch (type) {
+	case NAT46_IPV4_LOCAL:
+		for (ipair = 0; ipair < nat46->npairs; ipair++) {
+			apair = &nat46->sorted_ipv4_local_pairs[ipair];
+
+			/*
+			 * For a 32-bit number, if the shift count is 32, then the
+			 * result of the left shift operation is always 0.
+			 */
+			if (apair->local.v4_pref_len) {
+				mask = htonl(U32_MASK << (IPV4_BITS_MAX - apair->local.v4_pref_len));
+			}
+
+			if((*(uint32_t *)paddr & mask) == (apair->local.v4_pref & mask)) {
+				return apair;
+			}
+		}
+		break;
+	case NAT46_IPV4_REMOTE:
+		for (ipair = 0; ipair < nat46->npairs; ipair++) {
+			apair = &nat46->sorted_ipv4_remote_pairs[ipair];
+
+			/*
+			 * For a 32-bit number, if the shift count is 32, then the
+			 * result of the left shift operation is always 0.
+			 */
+			if (apair->remote.v4_pref_len) {
+				mask = htonl(U32_MASK << (IPV4_BITS_MAX - apair->remote.v4_pref_len));
+			}
+
+			if((*(uint32_t *)paddr & mask) == (apair->remote.v4_pref & mask)) {
+				return apair;
+			}
+		}
+		break;
+	case NAT46_IPV6_LOCAL:
+		for (ipair = 0; ipair < nat46->npairs; ipair++) {
+			apair = &nat46->sorted_ipv6_local_pairs[ipair];
+			if(memcmp(paddr, &apair->local.v6_pref, apair->local.v6_pref_len / BITS_PER_BYTE)) {
+				continue;
+			}
+			if(apair->local.v6_pref_len % BITS_PER_BYTE) {
+				mask = U8_MASK << (BITS_PER_BYTE - (apair->local.v6_pref_len % BITS_PER_BYTE));
+				pa1 = (uint8_t *)paddr + (apair->local.v6_pref_len / BITS_PER_BYTE);
+				pa2 = (uint8_t *)&apair->local.v6_pref + (apair->local.v6_pref_len / BITS_PER_BYTE);
+
+				if ((*pa1 & mask) == (*pa2 & mask)) {
+					return apair;
+				}
+			}
+			else
+				return apair;
+		}
+		break;
+	case NAT46_IPV6_REMOTE:
+		for (ipair = 0; ipair < nat46->npairs; ipair++) {
+			apair = &nat46->sorted_ipv6_remote_pairs[ipair];
+			if(memcmp(paddr, &apair->remote.v6_pref, apair->remote.v6_pref_len / BITS_PER_BYTE)) {
+				continue;
+			}
+			if(apair->remote.v6_pref_len % BITS_PER_BYTE) {
+				mask = U8_MASK << (BITS_PER_BYTE - (apair->remote.v6_pref_len % BITS_PER_BYTE));
+				pa1 = (uint8_t *)paddr + (apair->remote.v6_pref_len / BITS_PER_BYTE);
+				pa2 = (uint8_t *)&apair->remote.v6_pref + (apair->remote.v6_pref_len / BITS_PER_BYTE);
+
+				if((*pa1 & mask) == (*pa2 & mask)) {
+					return apair;
+				}
+			}
+			else
+				return apair;
+		}
+		break;
+	default:
+		nat46debug(0, "%s : Invalid prefix type.\n", __func__);
+	}
+	return NULL;
+}
+
+void pairs_xlate_v6_to_v4_inner(nat46_instance_t *nat46, struct ipv6hdr *ip6h, __u32 *pv4saddr, __u32 *pv4daddr) {
+  int ipair = 0;
+  nat46_xlate_rulepair_t *apair = NULL;
+  int xlate_src = -1;
+  int xlate_dst = -1;
+
+  apair = nat46_lpm(nat46, NAT46_IPV6_REMOTE, &ip6h->daddr);
+  if (!apair) {
+    return;
+  }
+
+  if (xlate_v6_to_v4(nat46, &apair->remote, &ip6h->daddr, pv4daddr)) {
+    xlate_dst = ipair;
+  }
+  if (xlate_v6_to_v4(nat46, &apair->local, &ip6h->saddr, pv4saddr)) {
+    xlate_src = ipair;
+  }
+
+  if ((xlate_src >= 0) && (xlate_dst >= 0)) {
+    /* we did manage to translate it */
+    nat46debug(5, "[nat46payload] xlate results: src %d dst %d", xlate_src, xlate_dst);
+  } else {
+    nat46debug(1, "[nat46] Could not find a translation pair v6->v4 src %pI6c dst %pI6c", &ip6h->saddr, &ip6h->daddr);
+  }
+}
+
+/*
+ * pv6 is pointing to the ipv6 header inside the payload.
+ * Translate this header and attempt to extract the sport/dport
+ * so the callers can use them for translation as well.
+ */
+int xlate_payload6_to4(nat46_instance_t *nat46, void *pv6, void *ptrans_hdr, int v6_len, u16 *ul_sum, int *ptailTruncSize) {
+  struct ipv6hdr *ip6h = pv6;
+  __u32 v4saddr, v4daddr;
+  struct iphdr new_ipv4;
+  struct iphdr *iph = &new_ipv4;
+  u16 proto = ip6h->nexthdr;
+  u16 ipid = 0;
+  u16 ipflags = htons(IP_DF);
+  int infrag_payload_len = ntohs(ip6h->payload_len);
+
+  /*
+   * The packet is supposedly our own packet after translation - so the rules
+   * will be swapped compared to translation of the outer packet
+   */
+  pairs_xlate_v6_to_v4_inner(nat46, pv6, &v4saddr, &v4daddr);
+
+  if (proto == NEXTHDR_FRAGMENT) {
+    struct frag_hdr *fh = (struct frag_hdr*)(ip6h + 1);
+    if(fh->frag_off == 0) {
+      /* Atomic fragment */
+      proto = fh->nexthdr;
+      ipid = fold_ipv6_frag_id(fh->identification);
+      v6_len -= 8;
+      infrag_payload_len -= 8;
+      *ptailTruncSize += 8;
+      ipflags = 0;
+    }
+  }
+
+
+  switch(proto) {
+    case NEXTHDR_TCP: {
+      struct tcphdr *th = ptrans_hdr;
+      u16 sum1 = csum_ipv6_unmagic(nat46, &ip6h->saddr, &ip6h->daddr, infrag_payload_len, NEXTHDR_TCP, th->check);
+      u16 sum2 = csum_tcpudp_remagic(v4saddr, v4daddr, infrag_payload_len, NEXTHDR_TCP, sum1); /* add pseudoheader */
+      if(ul_sum) {
+        *ul_sum = csum16_upd(*ul_sum, th->check, sum2);
+        }
+      th->check = sum2;
+      break;
+      }
+    case NEXTHDR_UDP: {
+      struct udphdr *udp = ptrans_hdr;
+      u16 sum1 = csum_ipv6_unmagic(nat46, &ip6h->saddr, &ip6h->daddr, infrag_payload_len, NEXTHDR_UDP, udp->check);
+      u16 sum2 = csum_tcpudp_remagic(v4saddr, v4daddr, infrag_payload_len, NEXTHDR_UDP, sum1); /* add pseudoheader */
+      if(ul_sum) {
+        *ul_sum = csum16_upd(*ul_sum, udp->check, sum2);
+        }
+      udp->check = sum2;
+      break;
+      }
+    case NEXTHDR_ICMP: {
+      struct icmp6hdr *icmp6h = ptrans_hdr;
+      u16 sum0 = icmp6h->icmp6_cksum;
+      u16 sum1 = csum_ipv6_unmagic(nat46, &ip6h->saddr, &ip6h->daddr, infrag_payload_len, NEXTHDR_ICMP, icmp6h->icmp6_cksum);
+      if(ul_sum) {
+        *ul_sum = csum16_upd(*ul_sum, sum0, sum1);
+        }
+      icmp6h->icmp6_cksum = sum1;
+      proto = IPPROTO_ICMP;
+      switch(icmp6h->icmp6_type) {
+        case ICMPV6_ECHO_REQUEST:
+          update_icmp6_type_code(nat46, icmp6h, ICMP_ECHO, icmp6h->icmp6_code);
+          break;
+        case ICMPV6_ECHO_REPLY:
+          update_icmp6_type_code(nat46, icmp6h, ICMP_ECHOREPLY, icmp6h->icmp6_code);
+          break;
+        default:
+          break;
+      }
+    }
+  }
+
+  fill_v4hdr_from_v6hdr(iph, ip6h, v4saddr, v4daddr, ipid, ipflags, proto, infrag_payload_len);
+  if(ul_sum) {
+    *ul_sum = unchecksum16(pv6, (((u8 *)ptrans_hdr)-((u8 *)pv6))/2, *ul_sum);
+    *ul_sum = rechecksum16(iph, 10, *ul_sum);
+  }
+
+  memmove(((char *)pv6) + IPV4HDRSIZE, get_next_header_ptr6(ip6h, v6_len), v6_len - IPV4HDRSIZE);
+  memcpy(pv6, iph, IPV4HDRSIZE);
+  *ptailTruncSize += IPV6V4HDRDELTA;
+  return (v6_len - IPV6V4HDRDELTA);
+}
+
+u8 *icmp_parameter_ptr(struct icmphdr *icmph) {
+  u8 *icmp_pptr = ((u8 *)(icmph))+4;
+  return icmp_pptr;
+}
+
+u32 *icmp6_parameter_ptr(struct icmp6hdr *icmp6h) {
+  u32 *icmp6_pptr = ((u32 *)(icmp6h))+1;
+  return icmp6_pptr;
+}
+
+static void nat46_fixup_icmp6_dest_unreach(nat46_instance_t *nat46, struct ipv6hdr *ip6h, struct icmp6hdr *icmp6h, struct sk_buff *old_skb, int *ptailTruncSize) {
+  /*
+   * Destination Unreachable (Type 1)  Set the Type to 3, and adjust
+   * the ICMP checksum both to take the type/code change into
+   * account and to exclude the ICMPv6 pseudo-header.
+   *
+   * Translate the Code as follows:
+   *
+   * Code 0 (No route to destination):  Set the Code to 1 (Host
+   *            unreachable).
+   *
+   * Code 1 (Communication with destination administratively
+   *        prohibited):  Set the Code to 10 (Communication with
+   *        destination host administratively prohibited).
+   *
+   * Code 2 (Beyond scope of source address):  Set the Code to 1
+   *        (Host unreachable).  Note that this error is very unlikely
+   *        since an IPv4-translatable source address is typically
+   *        considered to have global scope.
+   *
+   * Code 3 (Address unreachable):  Set the Code to 1 (Host
+   *        unreachable).
+   *
+   * Code 4 (Port unreachable):  Set the Code to 3 (Port
+   *        unreachable).
+   *
+   * Other Code values:  Silently drop.
+   */
+
+  int len;
+
+  switch(icmp6h->icmp6_code) {
+    case 0:
+    case 2:
+    case 3:
+      update_icmp6_type_code(nat46, icmp6h, 3, 1);
+      break;
+    case 1:
+      update_icmp6_type_code(nat46, icmp6h, 3, 10);
+      break;
+    case 4:
+      update_icmp6_type_code(nat46, icmp6h, 3, 3);
+      break;
+    default:
+      ip6h->nexthdr = NEXTHDR_NONE;
+  }
+  len = ntohs(ip6h->payload_len)-sizeof(*icmp6h);
+  len = xlate_payload6_to4(nat46, (icmp6h + 1), get_next_header_ptr6((icmp6h + 1), len), len, &icmp6h->icmp6_cksum, ptailTruncSize);
+}
+
+static void nat46_fixup_icmp6_pkt_toobig(nat46_instance_t *nat46, struct ipv6hdr *ip6h, struct icmp6hdr *icmp6h, struct sk_buff *old_skb, int *ptailTruncSize) {
+  /*
+   * Packet Too Big (Type 2):  Translate to an ICMPv4 Destination
+   * Unreachable (Type 3) with Code 4, and adjust the ICMPv4
+   * checksum both to take the type change into account and to
+   * exclude the ICMPv6 pseudo-header.  The MTU field MUST be
+   * adjusted for the difference between the IPv4 and IPv6 header
+   * sizes, taking into account whether or not the packet in error
+   * includes a Fragment Header, i.e., minimum(advertised MTU-20,
+   * MTU_of_IPv4_nexthop, (MTU_of_IPv6_nexthop)-20).
+   *
+   * See also the requirements in Section 6.
+   *
+   * Section 6 says this for v6->v4 side translation:
+   *
+   * 2.  In the IPv6-to-IPv4 direction:
+   *
+   *        A.  If there is a Fragment Header in the IPv6 packet, the last 16
+   *            bits of its value MUST be used for the IPv4 identification
+   *            value.
+   *
+   *        B.  If there is no Fragment Header in the IPv6 packet:
+   *
+   *            a.  If the packet is less than or equal to 1280 bytes:
+   *
+   *                -  The translator SHOULD set DF to 0 and generate an IPv4
+   *                   identification value.
+   *
+   *                -  To avoid the problems described in [RFC4963], it is
+   *                   RECOMMENDED that the translator maintain 3-tuple state
+   *                   for generating the IPv4 identification value.
+   *
+   *            b.  If the packet is greater than 1280 bytes, the translator
+   *                SHOULD set the IPv4 DF bit to 1.
+   */
+  int len = ntohs(ip6h->payload_len)-sizeof(*icmp6h);
+  u16 *pmtu = ((u16 *)icmp6h) + 3; /* IPv4-compatible MTU value is 16 bit */
+  u16 old_csum = icmp6h->icmp6_cksum;
+
+  if (ntohs(*pmtu) > IPV6V4HDRDELTA) {
+    icmp6h->icmp6_cksum = csum16_upd(old_csum, *pmtu, htons(ntohs(*pmtu) - IPV6V4HDRDELTA));
+    *pmtu = htons(ntohs(*pmtu) - IPV6V4HDRDELTA);
+  }
+
+  len = xlate_payload6_to4(nat46, (icmp6h + 1), get_next_header_ptr6((icmp6h + 1), len), len, &icmp6h->icmp6_cksum, ptailTruncSize);
+
+  update_icmp6_type_code(nat46, icmp6h, 3, 4);
+
+}
+
+static void nat46_fixup_icmp6_time_exceed(nat46_instance_t *nat46, struct ipv6hdr *ip6h, struct icmp6hdr *icmp6h, struct sk_buff *old_skb, int *ptailTruncSize) {
+  /*
+   * Time Exceeded (Type 3):  Set the Type to 11, and adjust the ICMPv4
+   * checksum both to take the type change into account and to
+   * exclude the ICMPv6 pseudo-header.  The Code is unchanged.
+   */
+  int len = ntohs(ip6h->payload_len)-sizeof(*icmp6h);
+  len = xlate_payload6_to4(nat46, (icmp6h + 1), get_next_header_ptr6((icmp6h + 1), len), len, &icmp6h->icmp6_cksum, ptailTruncSize);
+
+  update_icmp6_type_code(nat46, icmp6h, 11, icmp6h->icmp6_code);
+}
+
+static void nat46_fixup_icmp6_paramprob(nat46_instance_t *nat46, struct ipv6hdr *ip6h, struct icmp6hdr *icmp6h, struct sk_buff *old_skb, int *ptailTruncSize) {
+  /*
+   *         Parameter Problem (Type 4):  Translate the Type and Code as
+   *         follows, and adjust the ICMPv4 checksum both to take the type/
+   *         code change into account and to exclude the ICMPv6 pseudo-
+   *         header.
+   *
+   *         Translate the Code as follows:
+   *
+   *         Code 0 (Erroneous header field encountered):  Set to Type 12,
+   *            Code 0, and update the pointer as defined in Figure 6.  (If
+   *            the Original IPv6 Pointer Value is not listed or the
+   *            Translated IPv4 Pointer Value is listed as "n/a", silently
+   *            drop the packet.)
+   *
+   *         Code 1 (Unrecognized Next Header type encountered):  Translate
+   *            this to an ICMPv4 protocol unreachable (Type 3, Code 2).
+   *
+   *         Code 2 (Unrecognized IPv6 option encountered):  Silently drop.
+   *
+   *      Unknown error messages:  Silently drop.
+   *
+   *     +--------------------------------+--------------------------------+
+   *     |   Original IPv6 Pointer Value  | Translated IPv4 Pointer Value  |
+   *     +--------------------------------+--------------------------------+
+   *     |  0  | Version/Traffic Class    |  0  | Version/IHL, Type Of Ser |
+   *     |  1  | Traffic Class/Flow Label |  1  | Type Of Service          |
+   *     | 2,3 | Flow Label               | n/a |                          |
+   *     | 4,5 | Payload Length           |  2  | Total Length             |
+   *     |  6  | Next Header              |  9  | Protocol                 |
+   *     |  7  | Hop Limit                |  8  | Time to Live             |
+   *     | 8-23| Source Address           | 12  | Source Address           |
+   *     |24-39| Destination Address      | 16  | Destination Address      |
+   *     +--------------------------------+--------------------------------+
+   */
+  static int ptr6_4[] = { 0, 1, -1, -1, 2, 2, 9, 8,
+                          12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12,
+                          16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, -1 };
+  u32 *pptr6 = icmp6_parameter_ptr(icmp6h);
+  u8 *pptr4 = icmp_parameter_ptr((struct icmphdr *)icmp6h);
+  int8_t new_pptr = -1;
+  int len = ntohs(ip6h->payload_len)-sizeof(*icmp6h);
+
+  switch(icmp6h->icmp6_code) {
+    case 1:
+      update_icmp6_type_code(nat46, icmp6h, 3, 2);
+      break;
+    case 0:
+      if(*pptr6 < sizeof(ptr6_4)/sizeof(ptr6_4[0])) {
+        new_pptr = ptr6_4[*pptr6];
+        if (new_pptr >= 0) {
+          icmp6h->icmp6_cksum = csum16_upd(icmp6h->icmp6_cksum, (*pptr6 & 0xffff), (new_pptr << 8));
+          *pptr4 = 0xff & new_pptr;
+          update_icmp6_type_code(nat46, icmp6h, 12, 0);
+          break;
+        }
+      }
+#if __has_attribute(__fallthrough__)
+       __attribute__((__fallthrough__));
+#endif
+    case 2: /* fallthrough to default */
+    default:
+      ip6h->nexthdr = NEXTHDR_NONE;
+      return;
+  }
+
+  len = xlate_payload6_to4(nat46, (icmp6h + 1), get_next_header_ptr6((icmp6h + 1), len), len, &icmp6h->icmp6_cksum, ptailTruncSize);
+}
+
+/* Fixup ICMP6->ICMP before IP header translation, according to http://tools.ietf.org/html/rfc6145 */
+
+static void nat46_fixup_icmp6(nat46_instance_t *nat46, struct ipv6hdr *ip6h, struct icmp6hdr *icmp6h, struct sk_buff *old_skb, int *ptailTruncSize) {
+
+  if(icmp6h->icmp6_type & 128) {
+    /* Informational ICMP */
+    switch(icmp6h->icmp6_type) {
+      case ICMPV6_ECHO_REQUEST:
+        update_icmp6_type_code(nat46, icmp6h, ICMP_ECHO, icmp6h->icmp6_code);
+        break;
+      case ICMPV6_ECHO_REPLY:
+        update_icmp6_type_code(nat46, icmp6h, ICMP_ECHOREPLY, icmp6h->icmp6_code);
+        break;
+      default:
+        ip6h->nexthdr = NEXTHDR_NONE;
+    }
+  } else {
+    /* ICMPv6 errors */
+    switch(icmp6h->icmp6_type) {
+      case ICMPV6_DEST_UNREACH:
+        nat46_fixup_icmp6_dest_unreach(nat46, ip6h, icmp6h, old_skb, ptailTruncSize);
+        break;
+      case ICMPV6_PKT_TOOBIG:
+        nat46_fixup_icmp6_pkt_toobig(nat46, ip6h, icmp6h, old_skb, ptailTruncSize);
+        break;
+      case ICMPV6_TIME_EXCEED:
+        nat46_fixup_icmp6_time_exceed(nat46, ip6h, icmp6h, old_skb, ptailTruncSize);
+        break;
+      case ICMPV6_PARAMPROB:
+        nat46_fixup_icmp6_paramprob(nat46, ip6h, icmp6h, old_skb, ptailTruncSize);
+        break;
+      default:
+        ip6h->nexthdr = NEXTHDR_NONE;
+    }
+  }
+}
+
+
+int ip6_input_not_interested(nat46_instance_t *nat46, struct ipv6hdr *ip6h, struct sk_buff *old_skb) {
+  if (old_skb->protocol != htons(ETH_P_IPV6)) {
+    nat46debug(3, "Not an IPv6 packet");
+    return 1;
+  }
+  if(old_skb->len < sizeof(struct ipv6hdr) || ip6h->version != 6) {
+    nat46debug(3, "Len short or not correct version: %d", ip6h->version);
+    return 1;
+  }
+  if (!(ipv6_addr_type(&ip6h->saddr) & IPV6_ADDR_UNICAST)) {
+    nat46debug(3, "Source address not unicast");
+    return 1;
+  }
+  return 0;
+}
+
+static uint16_t nat46_fixup_icmp_time_exceeded(nat46_instance_t *nat46, struct iphdr *iph,
+			struct icmphdr *icmph, struct sk_buff *old_skb, uint16_t *sport, uint16_t *dport) {
+  /*
+   * Set the Type to 3, and adjust the
+   * ICMP checksum both to take the type change into account and
+   * to include the ICMPv6 pseudo-header.  The Code is unchanged.
+   */
+  icmph->type = 3;
+  return xlate_pkt_in_err_v4_to_v6(nat46, iph, old_skb, sport, dport);
+}
+
+static uint16_t nat46_fixup_icmp_parameterprob(nat46_instance_t *nat46, struct iphdr *iph,
+			struct icmphdr *icmph, struct sk_buff *old_skb, uint16_t *sport, uint16_t *dport) {
+  /*
+   * Set the Type to 4, and adjust the
+   * ICMP checksum both to take the type/code change into account
+   * and to include the ICMPv6 pseudo-header.
+   *
+   * Translate the Code as follows:
+   *
+   * Code 0 (Pointer indicates the error):  Set the Code to 0
+   * (Erroneous header field encountered) and update the
+   * pointer as defined in Figure 3.  (If the Original IPv4
+   * Pointer Value is not listed or the Translated IPv6
+   * Pointer Value is listed as "n/a", silently drop the
+   * packet.)
+   *
+   * Code 1 (Missing a required option):  Silently drop.
+   *
+   * Code 2 (Bad length):  Set the Code to 0 (Erroneous header
+   * field encountered) and update the pointer as defined in
+   * Figure 3.  (If the Original IPv4 Pointer Value is not
+   * listed or the Translated IPv6 Pointer Value is listed as
+   * "n/a", silently drop the packet.)
+   *
+   *            Other Code values:  Silently drop.
+   *
+   *     +--------------------------------+--------------------------------+
+   *     |   Original IPv4 Pointer Value  | Translated IPv6 Pointer Value  |
+   *     +--------------------------------+--------------------------------+
+   *     |  0  | Version/IHL              |  0  | Version/Traffic Class    |
+   *     |  1  | Type Of Service          |  1  | Traffic Class/Flow Label |
+   *     | 2,3 | Total Length             |  4  | Payload Length           |
+   *     | 4,5 | Identification           | n/a |                          |
+   *     |  6  | Flags/Fragment Offset    | n/a |                          |
+   *     |  7  | Fragment Offset          | n/a |                          |
+   *     |  8  | Time to Live             |  7  | Hop Limit                |
+   *     |  9  | Protocol                 |  6  | Next Header              |
+   *     |10,11| Header Checksum          | n/a |                          |
+   *     |12-15| Source Address           |  8  | Source Address           |
+   *     |16-19| Destination Address      | 24  | Destination Address      |
+   *     +--------------------------------+--------------------------------+
+   */
+  static int ptr4_6[] = { 0, 1, 4, 4, -1, -1, -1, -1, 7, 6, -1, -1, 8, 8, 8, 8, 24, 24, 24, 24, -1 };
+  u8 *icmp_pptr = icmp_parameter_ptr(icmph);
+  u32 *icmp6_pptr = icmp6_parameter_ptr((struct icmp6hdr *)icmph);
+  int8_t new_pptr = -1;
+
+  icmph->type = 4;
+
+  switch (icmph->code) {
+    case 0:
+    case 2:
+      if (*icmp_pptr < (sizeof(ptr4_6)/sizeof(ptr4_6[0]))) {
+        icmph->code = 0;
+        new_pptr = ptr4_6[*icmp_pptr];
+        if (new_pptr >= 0) {
+          *icmp6_pptr = new_pptr;
+          return xlate_pkt_in_err_v4_to_v6(nat46, iph, old_skb, sport, dport);
+        }
+      }
+#if __has_attribute(__fallthrough__)
+      __attribute__((__fallthrough__));
+#endif
+    default:
+      iph->protocol = NEXTHDR_NONE;
+  }
+  return 0;
+}
+
+static uint16_t nat46_fixup_icmp_dest_unreach(nat46_instance_t *nat46, struct iphdr *iph,
+			struct icmphdr *icmph, struct sk_buff *old_skb, uint16_t *sport, uint16_t *dport) {
+  /*
+   *    Translate the Code as
+   *    described below, set the Type to 1, and adjust the ICMP
+   *    checksum both to take the type/code change into account and
+   *    to include the ICMPv6 pseudo-header.
+   *
+   *    Translate the Code as follows:
+   *
+   *    Code 0, 1 (Net Unreachable, Host Unreachable):  Set the Code
+   *       to 0 (No route to destination).
+   *
+   *    Code 2 (Protocol Unreachable):  Translate to an ICMPv6
+   *       Parameter Problem (Type 4, Code 1) and make the Pointer
+   *       point to the IPv6 Next Header field.
+   *
+   *    Code 3 (Port Unreachable):  Set the Code to 4 (Port
+   *       unreachable).
+   *
+   *    Code 4 (Fragmentation Needed and DF was Set):  Translate to
+   *       an ICMPv6 Packet Too Big message (Type 2) with Code set
+   *       to 0.  The MTU field MUST be adjusted for the difference
+   *       between the IPv4 and IPv6 header sizes, i.e.,
+   *       minimum(advertised MTU+20, MTU_of_IPv6_nexthop,
+   *       (MTU_of_IPv4_nexthop)+20).  Note that if the IPv4 router
+   *       set the MTU field to zero, i.e., the router does not
+   *       implement [RFC1191], then the translator MUST use the
+   *       plateau values specified in [RFC1191] to determine a
+   *       likely path MTU and include that path MTU in the ICMPv6
+   *       packet.  (Use the greatest plateau value that is less
+   *       than the returned Total Length field.)
+   *
+   *       See also the requirements in Section 6.
+   *
+   *    Code 5 (Source Route Failed):  Set the Code to 0 (No route
+   *       to destination).  Note that this error is unlikely since
+   *       source routes are not translated.
+   *
+   *    Code 6, 7, 8:  Set the Code to 0 (No route to destination).
+   *
+   *    Code 9, 10 (Communication with Destination Host
+   *       Administratively Prohibited):  Set the Code to 1
+   *       (Communication with destination administratively
+   *       prohibited).
+   *
+   *    Code 11, 12:  Set the Code to 0 (No route to destination).
+   *
+   *    Code 13 (Communication Administratively Prohibited):  Set
+   *       the Code to 1 (Communication with destination
+   *       administratively prohibited).
+   *
+   *    Code 14 (Host Precedence Violation):  Silently drop.
+   *
+   *    Code 15 (Precedence cutoff in effect):  Set the Code to 1
+   *       (Communication with destination administratively
+   *       prohibited).
+   *
+   *    Other Code values:  Silently drop.
+   *
+   */
+
+  u16 *pmtu = ((u16 *)icmph) + 3; /* IPv4-compatible MTU value is 16 bit */
+
+  icmph->type = 1;
+
+  switch (icmph->code) {
+    case 0:
+    case 1:
+      icmph->code = 0;
+      break;
+    case 2: {
+      u32 *icmp6_pptr = icmp6_parameter_ptr((struct icmp6hdr *)icmph);
+      *icmp6_pptr = 6; /* Offset to Next Proto field in IPv6 header. */
+      icmph->type = 4;
+      icmph->code = 1;
+      nat46debug(3, "ICMP Proto Unreachable translated into IPv6 Param Prob.\n");
+      break;
+    }
+    case 3:
+      icmph->code = 4;
+      break;
+    case 4:
+      /*
+       * On adjusting the signaled MTU within packet:
+       *
+       * IPv4 has 20 bytes smaller header size, so, standard says
+       * we can advertise a higher MTU here. However, then we will
+       * need to ensure it does not overshoot our egress link MTU,
+       * which implies knowing the egress interface, which is
+       * not trivial in the current model.
+       *
+       * So, we'd want to leave the MTU as aside. But, the Section 6
+       * has something more to say:
+       *
+       *   1.  In the IPv4-to-IPv6 direction: if the MTU value of ICMPv4 Packet
+       *     Too Big (PTB) messages is less than 1280, change it to 1280.
+       *     This is intended to cause the IPv6 host and IPv6 firewall to
+       *     process the ICMP PTB message and generate subsequent packets to
+       *     this destination with an IPv6 Fragment Header.
+       *
+       */
+      icmph->type = 2;
+      icmph->code = 0;
+      if (ntohs(*pmtu) < 1280) {
+        *pmtu = htons(1280);
+      }
+      break;
+    case 5:
+    case 6:
+    case 7:
+    case 8:
+      icmph->code = 0;
+      break;
+    case 9:
+    case 10:
+      icmph->code = 1;
+      break;
+    case 11:
+    case 12:
+      icmph->code = 0;
+      break;
+    case 13:
+    case 15:
+      icmph->code = 1;
+      break;
+    default:
+      iph->protocol = NEXTHDR_NONE;
+      return 0;
+  }
+  return xlate_pkt_in_err_v4_to_v6(nat46, iph, old_skb, sport, dport);
+}
+
+/* Fixup ICMP->ICMP6 before IP header translation, according to http://tools.ietf.org/html/rfc6145 */
+
+static uint16_t nat46_fixup_icmp(nat46_instance_t *nat46, struct iphdr *iph,
+			struct sk_buff *old_skb, uint16_t *sport, uint16_t *dport) {
+  struct icmphdr *icmph = (struct icmphdr *)(iph+1);
+  uint16_t ret = 0;
+
+  iph->protocol = NEXTHDR_ICMP;
+
+  switch(icmph->type) {
+    case ICMP_ECHO:
+      icmph->type = ICMPV6_ECHO_REQUEST;
+      *sport = *dport = icmph->un.echo.id;
+      nat46debug(3, "ICMP echo request translated into IPv6, id: %d", ntohs(ret));
+      break;
+    case ICMP_ECHOREPLY:
+      icmph->type = ICMPV6_ECHO_REPLY;
+      *sport = *dport = icmph->un.echo.id;
+      nat46debug(3, "ICMP echo reply translated into IPv6, id: %d", ntohs(ret));
+      break;
+    case ICMP_TIME_EXCEEDED:
+      ret = nat46_fixup_icmp_time_exceeded(nat46, iph, icmph, old_skb, sport, dport);
+      break;
+    case ICMP_PARAMETERPROB:
+      ret = nat46_fixup_icmp_parameterprob(nat46, iph, icmph, old_skb, sport, dport);
+      break;
+    case ICMP_DEST_UNREACH:
+      ret = nat46_fixup_icmp_dest_unreach(nat46, iph, icmph, old_skb, sport, dport);
+      break;
+    default:
+      /* Silently drop. */
+      iph->protocol = NEXTHDR_NONE;
+  }
+  return ret;
+}
+
+int pairs_xlate_v6_to_v4_outer(nat46_instance_t *nat46, nat46_xlate_rulepair_t **papair,
+		struct ipv6hdr *ip6h, uint16_t proto, __u32 *pv4saddr, __u32 *pv4daddr) {
+  int ipair = 0;
+  int xlate_src = -1;
+  int xlate_dst = -1;
+  nat46_xlate_rulepair_t *apair;
+
+  apair = nat46_lpm(nat46, NAT46_IPV6_REMOTE, &ip6h->saddr);
+  if (!apair) {
+    return 0;
+  }
+
+  *papair = apair;
+  if (xlate_v6_to_v4(nat46, &apair->local, &ip6h->daddr, pv4daddr)) {
+    nat46debug(5, "Dst addr %pI6 to %pI4 \n", &ip6h->daddr, pv4daddr);
+    xlate_dst = ipair;
+  }
+  if (xlate_v6_to_v4(nat46, &apair->remote, &ip6h->saddr, pv4saddr)) {
+    nat46debug(5, "Src addr %pI6 to %pI4 \n", &ip6h->saddr, pv4saddr);
+    xlate_src = ipair;
+  }
+  if (xlate_dst >= 0) {
+    if (xlate_src < 0) {
+      if (proto == NEXTHDR_ICMP) {
+        nat46debug(1, "[nat46] Could not translate remote address v6->v4, ipair %d, for ICMP6 use dest addr", ipair);
+        *pv4saddr = *pv4daddr;
+        xlate_src = xlate_dst;
+      } else {
+        nat46debug(5, "[nat46] Could not translate remote address v6->v4, ipair %d", ipair);
+      }
+    }
+  } else {
+    nat46debug(1, "[nat46] Could not find a translation pair v6->v4 src %pI6c dst %pI6c", &ip6h->saddr, &ip6h->daddr);
+  }
+  nat46debug(5, "[nat46] pairs_xlate_v6_to_v4_outer result src %d dst %d", xlate_src, xlate_dst);
+  return ( (xlate_src >= 0) && (xlate_dst >= 0) );
+}
+
+int xlate_6_to_4(struct net_device *dev, struct ipv6hdr *ip6h, uint16_t proto, __u32 *pv4saddr, __u32 *pv4daddr) {
+	nat46_xlate_rulepair_t *apair;
+	return pairs_xlate_v6_to_v4_outer(netdev_nat46_instance(dev), &apair, ip6h, proto, pv4saddr, pv4daddr);
+}
+EXPORT_SYMBOL(xlate_6_to_4);
+
+void nat46_ipv6_input(struct sk_buff *old_skb) {
+  struct ipv6hdr *ip6h = ipv6_hdr(old_skb);
+  nat46_xlate_rulepair_t *apair;
+  nat46_instance_t *nat46 = get_nat46_instance(old_skb);
+  uint16_t proto;
+  uint16_t frag_off;
+  uint16_t frag_id;
+
+  struct iphdr * iph;
+  __u32 v4saddr, v4daddr;
+  struct sk_buff *new_skb = NULL;
+  struct sk_buff *reasm_skb = NULL;
+  int truncSize = 0;
+  int tailTruncSize = 0;
+  int v6packet_l3size = sizeof(*ip6h);
+  int l3_infrag_payload_len = ntohs(ip6h->payload_len);
+  int check_for_l4 = 0;
+
+  if (nat46 == NULL) {
+    printk("nat46:%p skb is dropped for no valid instance found\n", old_skb);
+    return;
+  }
+
+  nat46debug(4, "nat46_ipv6_input packet");
+
+  if(ip6_input_not_interested(nat46, ip6h, old_skb)) {
+    nat46debug(1, "nat46_ipv6_input not interested");
+    goto done;
+  }
+  nat46debug(5, "nat46_ipv6_input next hdr: %d, len: %d, is_fragment: %d",
+                ip6h->nexthdr, old_skb->len, ip6h->nexthdr == NEXTHDR_FRAGMENT);
+  proto = ip6h->nexthdr;
+  if (proto == NEXTHDR_FRAGMENT) {
+    struct frag_hdr *fh = (struct frag_hdr*)(ip6h + 1);
+    v6packet_l3size += sizeof(struct frag_hdr);
+    l3_infrag_payload_len -= sizeof(struct frag_hdr);
+    nat46debug(2, "Fragment ID: %08X", fh->identification);
+    nat46debug_dump(nat46, 6, fh, ntohs(ip6h->payload_len));
+
+    if(fh->frag_off == 0) {
+      /* Atomic fragment */
+      proto = fh->nexthdr;
+      frag_off = 0; /* no DF bit */
+      frag_id = fold_ipv6_frag_id(fh->identification);
+      nat46debug(2, "Atomic fragment");
+      check_for_l4 = 1;
+    } else {
+      if (0 == (ntohs(fh->frag_off) & IP6_OFFSET)) {
+        /* First fragment. Pretend business as usual, but when creating IP, set the "MF" bit. */
+        frag_off = htons(((ntohs(fh->frag_off) & 7) << 13) + (((ntohs(fh->frag_off) >> 3) & 0x1FFF)));
+        frag_id = fold_ipv6_frag_id(fh->identification);
+	/* ntohs(fh->frag_off) & IP6_MF */
+        proto = fh->nexthdr;
+        check_for_l4 = 1;
+        nat46debug(2, "First fragment, frag_off: %04X, frag id: %04X orig frag_off: %04X", ntohs(frag_off), frag_id, ntohs(fh->frag_off));
+      } else {
+        /* Not the first fragment - leave as is, allow to translate IPv6->IPv4 */
+        proto = fh->nexthdr;
+        frag_off = htons(((ntohs(fh->frag_off) & 7) << 13) + (((ntohs(fh->frag_off) >> 3) & 0x1FFF)));
+        frag_id = fold_ipv6_frag_id(fh->identification);
+        nat46debug(2, "Not first fragment, frag_off: %04X, frag id: %04X orig frag_off: %04X", ntohs(frag_off), frag_id, ntohs(fh->frag_off));
+      }
+
+      /* ICMPv6 counts the pseudo ipv6 header into its checksum, but ICMP doesn't
+       * but the length filed of the pseudo header count in all fragmented
+       * packets, so we need gather the framented packets into one packet to
+       * get the l3 payload length.
+       */
+      if (proto == NEXTHDR_ICMP) {
+        struct sk_buff *skb = skb_get(old_skb);
+	int err;
+	if (skb == NULL) {
+          goto done;
+	}
+
+        err = nf_ct_frag6_gather(dev_net(old_skb->dev), skb, IP6_DEFRAG_LOCAL_DELIVER);
+
+	/* EINPROGRESS means the skb was queued but the gather not finished yet */
+        if (err == -EINPROGRESS) {
+          goto done;
+        }
+
+	reasm_skb = skb;
+	/* other than EINPROGRESS error returned means the skb wasn't queued
+	 * 0 returned means that all fragments are all gathered
+	 * and the original skb was queued
+	 */
+        if (err != 0) {
+          goto done;
+        }
+
+        /* Use the reassembly packet as the input */
+        ip6h = ipv6_hdr(reasm_skb);
+        proto = ip6h->nexthdr;
+        v6packet_l3size = sizeof(*ip6h);
+
+	/* No fragment header in the re-assembly packet */
+        frag_off = 0;
+        l3_infrag_payload_len = ntohs(ip6h->payload_len);
+        old_skb = reasm_skb;
+	check_for_l4 = 1;
+      }
+    }
+  } else {
+    frag_off = htons(IP_DF);
+    frag_id = get_next_ip_id();
+    check_for_l4 = 1;
+  }
+
+  if (!pairs_xlate_v6_to_v4_outer(nat46, &apair, ip6h, proto, &v4saddr, &v4daddr)) {
+    if (proto == NEXTHDR_ICMP) {
+      struct icmp6hdr *icmp6h = add_offset(ip6h, v6packet_l3size);
+      struct ipv6hdr *ip6h_inner = (struct ipv6hdr *) (icmp6h + 1);
+      struct ipv6hdr hdr6;
+      switch(icmp6h->icmp6_type) {
+        case ICMPV6_DEST_UNREACH:
+        case ICMPV6_PKT_TOOBIG:
+        case ICMPV6_TIME_EXCEED:
+        case ICMPV6_PARAMPROB:
+          /*
+           * For icmpv6 error message, using the original message
+           * address to  locate the apair one more time according
+           * to the RFC 2473, and use the ipv4 address of the
+           * tunnel as SRC ipv4 address
+           */
+          memcpy(&hdr6.saddr, &ip6h_inner->daddr, 16);
+          memcpy(&hdr6.daddr, &ip6h_inner->saddr, 16);
+          if (!pairs_xlate_v6_to_v4_outer(nat46, &apair, &hdr6, proto, &v4saddr, &v4daddr)) {
+            if (net_ratelimit()) {
+              nat46debug(0, "[nat46] Could not translate v6->v4");
+            }
+            goto done;
+          }
+          v4saddr = apair->local.v4_pref;
+          break;
+        default:
+          nat46debug(0, "[nat46] Could not translate v6->v4");
+          goto done;
+      }
+    } else {
+      nat46debug(0, "[nat46] Could not translate v6->v4");
+      goto done;
+    }
+  }
+
+  if (check_for_l4) {
+    switch(proto) {
+      /* CHECKSUMS UPDATE */
+      case NEXTHDR_TCP: {
+        struct tcphdr *th = add_offset(ip6h, v6packet_l3size);
+
+	/* TCP payload length won't change, needn't unmagic its value. */
+        u16 sum1 = csum_ipv6_unmagic(nat46, &ip6h->saddr, &ip6h->daddr, 0, NEXTHDR_TCP, th->check);
+        u16 sum2 = csum_tcpudp_remagic(v4saddr, v4daddr, 0, NEXTHDR_TCP, sum1);
+        th->check = sum2;
+        break;
+        }
+      case NEXTHDR_UDP: {
+        struct udphdr *udp = add_offset(ip6h, v6packet_l3size);
+
+	/* UDP payload length won't change, needn't unmagic its value.
+	 * UDP checksum zero then skip the calculation of the checksum.
+	 */
+	if (udp->check) {
+          u16 sum1 = csum_ipv6_unmagic(nat46, &ip6h->saddr, &ip6h->daddr, 0, NEXTHDR_UDP, udp->check);
+          u16 sum2 = csum_tcpudp_remagic(v4saddr, v4daddr, 0, NEXTHDR_UDP, sum1);
+          udp->check = sum2;
+	}
+        break;
+        }
+      case NEXTHDR_ICMP: {
+        struct icmp6hdr *icmp6h = add_offset(ip6h, v6packet_l3size);
+
+	/* ICMPv6 count the pseudo IPv6 header into its checksum, but icmp
+	 * doesn't, unmagic the whole the pseudo IPv6 header from the checksum.
+	 */
+        u16 sum1 = csum_ipv6_unmagic(nat46, &ip6h->saddr, &ip6h->daddr, l3_infrag_payload_len, NEXTHDR_ICMP, icmp6h->icmp6_cksum);
+        icmp6h->icmp6_cksum = sum1;
+        nat46debug_dump(nat46, 10, icmp6h, l3_infrag_payload_len);
+        nat46_fixup_icmp6(nat46, ip6h, icmp6h, old_skb, &tailTruncSize);
+        proto = IPPROTO_ICMP;
+        break;
+        }
+      default:
+        break;
+    }
+  } else {
+    if(NEXTHDR_ICMP == proto) {
+      proto = IPPROTO_ICMP;
+    }
+  }
+
+  new_skb = skb_copy(old_skb, GFP_ATOMIC); // other possible option: GFP_ATOMIC
+  if (!new_skb) {
+    nat46debug(0, "[nat46] Could not copy v6 skb");
+    goto done;
+  }
+
+  /* Remove any debris in the socket control block */
+  memset(IPCB(new_skb), 0, sizeof(struct inet_skb_parm));
+  /* Remove netfilter references to IPv6 packet, new netfilter references will be created based on IPv4 packet */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0)
+  nf_reset(new_skb);
+#else
+  skb_ext_reset(new_skb);
+  nf_reset_ct(new_skb);
+#endif
+
+  /* modify packet: actual IPv6->IPv4 transformation */
+  truncSize = v6packet_l3size - sizeof(struct iphdr); /* chop first 20 bytes */
+  skb_pull(new_skb, truncSize);
+  skb_put(new_skb, -tailTruncSize);
+  l3_infrag_payload_len -= tailTruncSize;
+  skb_reset_network_header(new_skb);
+  skb_set_transport_header(new_skb,IPV4HDRSIZE); /* transport (TCP/UDP/ICMP/...) header starts after 20 bytes */
+
+  /* build IPv4 header */
+  iph = ip_hdr(new_skb);
+  fill_v4hdr_from_v6hdr(iph, ip6h, v4saddr, v4daddr, frag_id, frag_off, proto, l3_infrag_payload_len);
+  new_skb->protocol = htons(ETH_P_IP);
+
+  nat46debug(5, "about to send v4 packet, flags: %02x",  IPCB(new_skb)->flags);
+  nat46_netdev_count_xmit(new_skb, old_skb->dev);
+
+  /* set skb->iif */
+  new_skb->skb_iif = old_skb->skb_iif;
+
+  netif_rx(new_skb);
+
+  /* TBD: should copy be released here? */
+
+done:
+  if (reasm_skb) {
+    kfree_skb(reasm_skb);
+  }
+  release_nat46_instance(nat46);
+}
+
+void ip6_update_csum(struct sk_buff * skb, struct ipv6hdr * ip6hdr, int do_atomic_frag)
+{
+  u32 sum1=0;
+  u16 sum2=0;
+  __sum16 oldsum = 0;
+
+  switch (ip6hdr->nexthdr) {
+    case IPPROTO_TCP: {
+      struct tcphdr *th = tcp_hdr(skb);
+      unsigned tcplen = 0;
+
+      oldsum = th->check;
+      tcplen = ntohs(ip6hdr->payload_len) - (do_atomic_frag?8:0); /* TCP header + payload */
+      th->check = 0;
+      sum1 = csum_partial((char*)th, tcplen, 0); /* calculate checksum for TCP hdr+payload */
+      sum2 = csum_ipv6_magic(&ip6hdr->saddr, &ip6hdr->daddr, tcplen, ip6hdr->nexthdr, sum1); /* add pseudoheader */
+      th->check = sum2;
+      break;
+      }
+    case IPPROTO_UDP: {
+      struct udphdr *udp = udp_hdr(skb);
+      unsigned udplen = ntohs(ip6hdr->payload_len) - (do_atomic_frag?8:0); /* UDP hdr + payload */
+
+      oldsum = udp->check;
+      udp->check = 0;
+
+      sum1 = csum_partial((char*)udp, udplen, 0); /* calculate checksum for UDP hdr+payload */
+      sum2 = csum_ipv6_magic(&ip6hdr->saddr, &ip6hdr->daddr, udplen, ip6hdr->nexthdr, sum1); /* add pseudoheader */
+
+      udp->check = sum2;
+
+      break;
+      }
+    case NEXTHDR_ICMP: {
+      struct icmp6hdr *icmp6h = icmp6_hdr(skb);
+      unsigned icmp6len = 0;
+      icmp6len = ntohs(ip6hdr->payload_len) - (do_atomic_frag?8:0); /* ICMP header + payload */
+      icmp6h->icmp6_cksum = 0;
+      sum1 = csum_partial((char*)icmp6h, icmp6len, 0); /* calculate checksum for TCP hdr+payload */
+      sum2 = csum_ipv6_magic(&ip6hdr->saddr, &ip6hdr->daddr, icmp6len, ip6hdr->nexthdr, sum1); /* add pseudoheader */
+      icmp6h->icmp6_cksum = sum2;
+      break;
+      }
+    }
+}
+EXPORT_SYMBOL(ip6_update_csum);
+
+int ip4_input_not_interested(nat46_instance_t *nat46, struct iphdr *iph, struct sk_buff *old_skb) {
+  if (old_skb->protocol != htons(ETH_P_IP)) {
+    nat46debug(3, "Not an IPv4 packet");
+    return 1;
+  }
+  // FIXME: check source to be within our prefix
+  return 0;
+}
+
+int pairs_xlate_v4_to_v6_outer(nat46_instance_t *nat46, nat46_xlate_rulepair_t *apair,
+		struct iphdr *hdr4, uint16_t *sport, uint16_t *dport, void *v6saddr, void *v6daddr) {
+  int ipair = 0;
+  int xlate_src = -1;
+  int xlate_dst = -1;
+  int ret = 0;
+
+  apair = nat46_lpm(nat46, NAT46_IPV4_REMOTE, &hdr4->daddr);
+  if (!apair) {
+    return 0;
+  }
+
+  if (xlate_v4_to_v6(nat46, &apair->local, &hdr4->saddr, v6saddr, sport)) {
+    nat46debug(5, "Src addr %pI4 to %pI6 \n", &hdr4->saddr, v6saddr);
+    xlate_src = ipair;
+  }
+  if (xlate_v4_to_v6(nat46, &apair->remote, &hdr4->daddr, v6daddr, dport)) {
+    nat46debug(5, "Dst addr %pI4 to %pI6 \n", &hdr4->daddr, v6daddr);
+    xlate_dst = ipair;
+  }
+  nat46debug(5, "[nat46] pairs_xlate_v4_to_v6_outer result: src %d dst %d", xlate_src, xlate_dst);
+  if ( (xlate_src >= 0) && (xlate_dst >= 0) ) {
+    ret = 1;
+  } else {
+    nat46debug(1, "[nat46] Could not find a translation pair v4->v6");
+  }
+  return ret;
+}
+
+int xlate_4_to_6(struct net_device *dev, struct iphdr *hdr4, uint16_t sport, uint16_t dport, void *v6saddr, void *v6daddr) {
+	nat46_xlate_rulepair_t apair;
+	return pairs_xlate_v4_to_v6_outer(netdev_nat46_instance(dev), &apair, hdr4, &sport, &dport, v6saddr, v6daddr);
+}
+EXPORT_SYMBOL(xlate_4_to_6);
+
+/*
+ * The sport & dport in inner header will be dport & sport of the outer header, respectively.
+ * Hence, dest. and source ips of inner header will be found in local & remote rules, respectively.
+ */
+int pairs_xlate_v4_to_v6_inner(nat46_instance_t *nat46, struct iphdr *iph,
+		uint16_t sport, uint16_t dport, void *v6saddr, void *v6daddr) {
+	int ipair = 0;
+	nat46_xlate_rulepair_t *apair = NULL;
+	int xlate_src = -1;
+	int xlate_dst = -1;
+
+	apair = nat46_lpm(nat46, NAT46_IPV4_REMOTE, &iph->saddr);
+	if (!apair) {
+		return 0;
+	}
+
+	if (xlate_v4_to_v6(nat46, &apair->local, &iph->daddr, v6daddr, &dport)) {
+		nat46debug(3, "Dst addr %pI4 to %pI6 \n", &iph->daddr, v6daddr);
+		xlate_dst = ipair;
+	}
+	if (xlate_v4_to_v6(nat46, &apair->remote, &iph->saddr, v6saddr, &sport)) {
+		nat46debug(3, "Src addr %pI4 to %pI6 \n", &iph->saddr, v6saddr);
+		xlate_src = ipair;
+	}
+	if ((xlate_src >= 0) && (xlate_dst >= 0)) {
+		/* we did manage to translate it */
+		nat46debug(5, "[nat46] Inner header xlate results: src %d dst %d", xlate_src, xlate_dst);
+		return 1;
+	} else {
+		nat46debug(1, "[nat46] Could not find a translation pair v4->v6");
+	}
+
+	return 0;
+}
+
+static uint16_t xlate_pkt_in_err_v4_to_v6(nat46_instance_t *nat46, struct iphdr *iph,
+					struct sk_buff *old_skb, uint16_t *sport, uint16_t *dport) {
+	struct ipv6hdr ip6h;
+	char v6saddr[16], v6daddr[16];
+	uint16_t temp_port = 0;
+	int ret = 0;
+	struct icmphdr *icmph = (struct icmphdr *)(iph + 1);
+	struct iphdr *iiph = (struct iphdr *)(icmph + 1);
+
+	switch (iiph->protocol) {
+	case IPPROTO_TCP: {
+		struct tcphdr *th = (struct tcphdr *)(iiph + 1);
+		*sport = th->source;
+		*dport = th->dest;
+		iiph->protocol = NEXTHDR_TCP;
+		break;
+	}
+	case IPPROTO_UDP: {
+		struct udphdr *udp = (struct udphdr *)(iiph + 1);
+		*sport = udp->source;
+		*dport = udp->dest;
+		iiph->protocol = NEXTHDR_UDP;
+		break;
+	}
+	case IPPROTO_ICMP: {
+		struct icmphdr *icmph = (struct icmphdr *)(iiph + 1);
+		iiph->protocol = NEXTHDR_ICMP;
+		switch (icmph->type) {
+		case ICMP_ECHO:
+			icmph->type = ICMPV6_ECHO_REQUEST;
+			*sport = *dport = icmph->un.echo.id;
+			break;
+		case ICMP_ECHOREPLY:
+			icmph->type = ICMPV6_ECHO_REPLY;
+			*sport = *dport = icmph->un.echo.id;
+			break;
+		default:
+			nat46debug(3, "ICMP Error message can't be inside another ICMP Error messgae.");
+			*sport = *dport = 0;
+			return 0;
+		}
+		break;
+	}
+	default:
+		nat46debug(3, "[ICMPv4] Next header: %u. Only TCP, UDP, and ICMP are supported.", iiph->protocol);
+		*sport = *dport = 0;
+		return 0;
+	}
+
+	nat46debug(3, "Retrieved from pkt in error: dest port %d, and src port %d.", ntohs(*dport), ntohs(*sport));
+
+	if (!pairs_xlate_v4_to_v6_inner(nat46, iiph, *sport, *dport, v6saddr, v6daddr)) {
+		nat46debug(0, "[nat46] Could not translate inner header v4->v6");
+		*sport = *dport = 0;
+		return 0;
+	}
+
+	fill_v6hdr_from_v4hdr (iiph, &ip6h);
+	memcpy(&ip6h.saddr, v6saddr, sizeof(ip6h.saddr));
+	memcpy(&ip6h.daddr, v6daddr, sizeof(ip6h.daddr));
+
+	if (skb_tailroom(old_skb) >= IPV6V4HDRDELTA){
+		skb_put(old_skb, IPV6V4HDRDELTA);
+		/* ErrorICMP size is less than 576, the inner ipv4 packet will be trimmed */
+		memmove(((char *)iiph + IPV6HDRSIZE), (iiph + 1),
+		ntohs(iph->tot_len) - 2 * IPV4HDRSIZE - sizeof(struct icmphdr));
+		memcpy(iiph, &ip6h, IPV6HDRSIZE);
+	}
+	else {
+		ret = pskb_expand_head(old_skb, 0, IPV6V4HDRDELTA, GFP_ATOMIC);
+		if (unlikely(ret)) {
+			nat46debug(0, "[nat46] Could not copy v4 skb");
+			*sport = *dport = 0;
+			return 0;
+		}
+
+		skb_put(old_skb, IPV6V4HDRDELTA);
+		iiph = (struct iphdr *)(icmp_hdr(old_skb) + 1);
+		/* ErrorICMP size is less than 576, the inner ipv4 packet will be trimmed */
+		memmove(((char *)iiph + IPV6HDRSIZE), (iiph + 1),
+		ntohs(iph->tot_len) - 2 * IPV4HDRSIZE - sizeof(struct icmphdr));
+		memcpy(iiph, &ip6h, IPV6HDRSIZE);
+	}
+	iph->tot_len = htons(ntohs(iph->tot_len) + IPV6V4HDRDELTA);
+
+	/* Swapping Ports for outer header */
+	/* Another work-around till LPM is not present. */
+	temp_port = *sport;
+	*sport = *dport;
+	*dport = temp_port;
+
+	return 1;
+}
+
+/* Return the port number from CE's port set */
+static uint16_t nat46_get_ce_port(nat46_xlate_rulepair_t *pair, uint16_t sport)
+{
+	/*
+	 * 'psid_bits_len' represents number of bits in PSID.
+	 * 'offset' represents offset of PSID in a port number.
+	 */
+	uint8_t psid_bits_len, offset, port_set_bitmask;
+
+	/*
+	 * 'psid16' represent PSID value.
+	 * 'm' represents number of bits in excluded port set.
+	 * 'a' represents number of bits in a 16-bit port number after PSID.
+	 *     It is used to control number of port in one contiguous port set.
+	 *
+	 * Name of a variable 'a' and 'm' is as per Appendix B of [RFC7597].
+	 */
+	uint16_t psid16, value, m, a;
+	nat46_xlate_rule_t *rule;
+
+	/* stores to last port number from CE's port set */
+	static uint16_t port_num;
+
+	rule = &pair->local;
+	offset = rule->psid_offset;
+
+	if (rule->ea_len + rule->v4_pref_len > IPV4_BITS_MAX) {
+		psid_bits_len = rule->ea_len - (IPV4_BITS_MAX - rule->v4_pref_len);
+	} else {
+		return 0;
+	}
+	a = PSID_LEN_MAX - offset - psid_bits_len;
+	psid16 = (ntohs(sport) >> a) & (0xffff >> (PSID_LEN_MAX - psid_bits_len));
+
+	spin_lock(&port_id_lock);
+
+	/* Start case */
+	if (0 == port_num) {
+		m = (offset) ? 1 : 0;
+		port_num = (m << (PSID_LEN_MAX - offset)) | (psid16 << a);
+		value = port_num;
+		spin_unlock(&port_id_lock);
+		return value;
+	}
+
+	/* End of one port set */
+	port_set_bitmask = (1 << a) - 1;
+	value = port_num & port_set_bitmask;
+	if (0 == (value ^ port_set_bitmask)) {
+		m = port_num >> (PSID_LEN_MAX - offset);
+		m++;
+		/* End case */
+		if (m >= (1 << offset)) {
+			m = (offset) ? 1 : 0;
+		}
+		port_num = (m << (PSID_LEN_MAX - offset)) | (psid16 << a);
+		value = port_num;
+		spin_unlock(&port_id_lock);
+		return value;
+	}
+
+	port_num++;
+	value = port_num;
+	spin_unlock(&port_id_lock);
+	return value;
+}
+
+void nat46_ipv4_input(struct sk_buff *old_skb) {
+  nat46_instance_t *nat46 = get_nat46_instance(old_skb);
+  nat46_xlate_rulepair_t apair;
+  struct sk_buff *new_skb;
+  uint16_t sport = 0, dport = 0, ret = 0;
+
+  uint8_t tclass;
+  int flowlabel = 0;
+  int check_for_l4 = 0;
+  int having_l4 = 0;
+  int add_frag_header = 0;
+
+  struct ipv6hdr * hdr6;
+  struct iphdr * hdr4 = ip_hdr(old_skb);
+
+  char v6saddr[16], v6daddr[16];
+
+  if (nat46 == NULL) {
+    printk("nat46:%p skb is dropped for no valid instance found\n", old_skb);
+    return;
+  }
+
+  tclass = hdr4->tos;
+
+  memset(v6saddr, 1, 16);
+  memset(v6daddr, 2, 16);
+
+  if (ip4_input_not_interested(nat46, hdr4, old_skb)) {
+    goto done;
+  }
+  nat46debug(1, "nat46_ipv4_input packet");
+  nat46debug(5, "nat46_ipv4_input protocol: %d, len: %d, flags: %02x", hdr4->protocol, old_skb->len, IPCB(old_skb)->flags);
+  if(0 == (ntohs(hdr4->frag_off) & 0x3FFF) ) { /* Checking for MF */
+    check_for_l4 = 1;
+    if (0 == (ntohs(hdr4->frag_off) & IP_DF)) {
+      if (add_dummy_header) {
+        add_frag_header = 1;
+      }
+      old_skb->ignore_df = 1;
+    }
+  } else {
+    add_frag_header = 1;
+    if (0 == (ntohs(hdr4->frag_off) & 0x1FFF)) { /* Checking for Frag Offset */
+      check_for_l4 = 1;
+    }
+  }
+
+  if (check_for_l4) {
+    switch(hdr4->protocol) {
+      case IPPROTO_TCP: {
+	struct tcphdr *th = tcp_hdr(old_skb);
+	sport = th->source;
+	dport = th->dest;
+	having_l4 = 1;
+	break;
+	}
+      case IPPROTO_UDP: {
+	struct udphdr *udp = udp_hdr(old_skb);
+	sport = udp->source;
+	dport = udp->dest;
+	having_l4 = 1;
+	break;
+	}
+      case IPPROTO_ICMP:
+        ret = nat46_fixup_icmp(nat46, hdr4, old_skb, &sport, &dport);
+        nat46debug(3, "ICMP translated to dest port %d, and src port %d.", ntohs(dport), ntohs(sport));
+        having_l4 = 1;
+        break;
+      default:
+	break;
+    }
+  } else {
+    if (IPPROTO_ICMP == hdr4->protocol) {
+      hdr4->protocol = NEXTHDR_ICMP;
+    }
+    dport = 0;
+    sport = 0;
+    having_l4 = 1;
+  }
+
+  if(!pairs_xlate_v4_to_v6_outer(nat46, &apair, hdr4, having_l4 ? &sport : NULL, having_l4 ? &dport : NULL, v6saddr, v6daddr)) {
+    if (net_ratelimit()) {
+      nat46debug(0, "[nat46] Could not translate v4->v6");
+    }
+    goto done;
+  }
+
+  new_skb = skb_copy(old_skb, GFP_ATOMIC);
+  if (!new_skb) {
+    nat46debug(0, "[nat46] Could not copy v4 skb");
+    goto done;
+  }
+
+  /* Remove any debris in the socket control block */
+  memset(IPCB(new_skb), 0, sizeof(struct inet_skb_parm));
+  /* Remove netfilter references to IPv4 packet, new netfilter references will be created based on IPv6 packet */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0)
+  nf_reset(new_skb);
+#else
+  skb_ext_reset(new_skb);
+  nf_reset_ct(new_skb);
+#endif
+
+  /* expand header (add 20 extra bytes at the beginning of sk_buff) */
+  pskb_expand_head(new_skb, IPV6V4HDRDELTA + (add_frag_header?8:0), 0, GFP_ATOMIC);
+
+  skb_push(new_skb, IPV6V4HDRDELTA + (add_frag_header?8:0)); /* push boundary by extra 20 bytes */
+
+  skb_reset_network_header(new_skb);
+  skb_set_transport_header(new_skb, IPV6HDRSIZE + (add_frag_header?8:0) ); /* transport (TCP/UDP/ICMP/...) header starts after 40 bytes */
+
+  hdr6 = ipv6_hdr(new_skb);
+  memset(hdr6, 0, sizeof(*hdr6) + (add_frag_header?8:0));
+
+  /* build IPv6 header */
+  *(__be32 *)hdr6 = htonl(0x60000000 | (tclass << 20)) | flowlabel; /* version, priority, flowlabel */
+
+  /* IPv6 length is a payload length, IPv4 is hdr+payload */
+  hdr6->payload_len = htons(ntohs(hdr4->tot_len) - sizeof(struct iphdr) + (add_frag_header?8:0));
+  hdr6->nexthdr = hdr4->protocol;
+  hdr6->hop_limit = hdr4->ttl;
+  memcpy(&hdr6->saddr, v6saddr, 16);
+  memcpy(&hdr6->daddr, v6daddr, 16);
+
+  new_skb->protocol = htons(ETH_P_IPV6);
+
+  if (add_frag_header) {
+    struct frag_hdr *fh = (struct frag_hdr*)(hdr6 + 1);
+    uint16_t ce_port_num = 0;
+
+    /* Flag to represent whether PSID is assigned to MAP-T node or not */
+    bool is_psid = false;
+
+    fh->frag_off = htons(((ntohs(hdr4->frag_off) >> 13) & 7) + ((ntohs(hdr4->frag_off) & 0x1FFF) << 3));
+    fh->nexthdr = hdr4->protocol;
+
+    /*
+     * PSID assigned MAP-T node will have non-zero ea_len and we are currently
+     * only supporting NAT46_XLATE_MAP as the CE's rule style.
+     */
+    is_psid = (apair.local.style == NAT46_XLATE_MAP) && apair.local.ea_len;
+    if (is_psid) {
+      ce_port_num = nat46_get_ce_port(nat46->pairs, sport);
+      nat46debug(10, "\n ce port number is %02x\n", ce_port_num);
+
+      /* Assign CE's port number as the fragment identifier */
+      if (ce_port_num) {
+        fh->identification = htonl(ce_port_num);
+      } else {
+        fh->identification = htonl(ntohs(hdr4->id));
+      }
+    } else {
+      fh->identification = htonl(ntohs(hdr4->id));
+    }
+
+
+  }
+  ip6_update_csum(new_skb, hdr6, add_frag_header);
+
+  hdr6->nexthdr = add_frag_header ? NEXTHDR_FRAGMENT : hdr4->protocol;
+
+
+  // FIXME: check if you can not fit the packet into the cached MTU
+  // if (dst_mtu(skb_dst(new_skb))==0) { }
+
+  nat46debug(5, "about to send v6 packet, flags: %02x",  IPCB(new_skb)->flags);
+  nat46_netdev_count_xmit(new_skb, old_skb->dev);
+
+  /* set skb->iif */
+  new_skb->skb_iif = old_skb->skb_iif;
+
+  netif_rx(new_skb);
+
+done:
+  release_nat46_instance(nat46);
+}
+
+int nat46_get_npairs(struct net_device *dev) {
+	nat46_instance_t *nat46 = netdev_nat46_instance(dev);
+	return nat46->npairs;
+}
+EXPORT_SYMBOL(nat46_get_npairs);
+
+bool nat46_get_rule_config(struct net_device *dev, nat46_xlate_rulepair_t **nat46_rule_pair, int *count) {
+	nat46_instance_t *nat46 = netdev_nat46_instance(dev);
+	if (nat46->npairs < 1) {
+		/*
+		 * no rules ?
+		 */
+		return false;
+	}
+	*count = nat46->npairs;
+	*nat46_rule_pair = nat46->pairs;
+	return true;
+}
+EXPORT_SYMBOL(nat46_get_rule_config);
+
+/*
+ * Function to get MAP-T rules and flags.
+ */
+bool nat46_get_info(struct net_device *dev, nat46_xlate_rulepair_t **nat46_rule_pair,
+		 int *count, u8 *flag) {
+	if ((!dev) || (!nat46_rule_pair) || (!count) || (!flag)) {
+		return false;
+	}
+
+	if (!nat46_get_rule_config(dev, nat46_rule_pair, count)) {
+		return false;
+	}
+
+	/* Check add dummy header flag */
+	if (add_dummy_header) {
+		*flag = ADD_DUMMY_HEADER;
+	}
+	return true;
+}
+EXPORT_SYMBOL(nat46_get_info);
diff --git a/nat46/nat46/modules/nat46-core.h b/nat46/nat46/modules/nat46-core.h
new file mode 100644
index 0000000..fd72daf
--- /dev/null
+++ b/nat46/nat46/modules/nat46-core.h
@@ -0,0 +1,119 @@
+/*
+ * NAT46 core definitions
+ *
+ * Copyright (c) 2013-2014 Andrew Yourtchenko <ayourtch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __NAT46_CORE_H__
+#define __NAT46_CORE_H__
+
+#include "nat46-glue.h"
+
+// #define nat46debug(level, format, ...) debug(DBG_V6, level, format, __VA_ARGS__)
+// #define nat46debug(level, format, ...)
+#define nat46debug(level, format, ...) do { if(nat46->debug >= level) { printk(format "\n", ##__VA_ARGS__); } } while (0)
+
+#define U8_MASK (uint8_t)(0xFF)
+#define U32_MASK (uint32_t)(~0U)
+#define BITS_PER_BYTE 8
+#define PSID_LEN_MAX 16
+#define NUM_RULE_PAIRS_MAX 32
+#define IPV4_BITS_MAX 32
+#define EA_LEN_MAX 48
+#define IPV6_BITS_MAX 128
+
+/* Flag definations for MAP-T */
+#define ADD_DUMMY_HEADER 0x01
+
+#define IPV6HDRSIZE 40
+#define IPV4HDRSIZE 20
+#define IPV6V4HDRDELTA (IPV6HDRSIZE - IPV4HDRSIZE)
+
+/* 
+ * A generic v4<->v6 translation structure.
+ * The currently supported translation styles:
+ */
+
+typedef enum {
+  NAT46_XLATE_NONE = 0,
+  NAT46_XLATE_MAP,
+  NAT46_XLATE_MAP0,
+  NAT46_XLATE_RFC6052
+} nat46_xlate_style_t;
+
+/*
+ * Enumeration for sorting pairs based on
+ * type of prefix length.
+ */
+typedef enum {
+  NAT46_IPV4_LOCAL = 0,
+  NAT46_IPV4_REMOTE,
+  NAT46_IPV6_LOCAL,
+  NAT46_IPV6_REMOTE
+} nat46_rule_type_t;
+
+#define NAT46_SIGNATURE 0x544e3634
+#define FREED_NAT46_SIGNATURE 0xdead544e
+
+typedef struct nat46_xlate_rule {
+  nat46_xlate_style_t style;
+  struct in6_addr v6_pref;
+  int v6_pref_len;
+  u32 v4_pref;
+  int v4_pref_len;
+  int ea_len;
+  int psid_offset;
+  int fmr_flag;
+} nat46_xlate_rule_t;
+
+typedef struct nat46_xlate_rulepair {
+  nat46_xlate_rule_t local;
+  nat46_xlate_rule_t remote;
+} nat46_xlate_rulepair_t;
+
+typedef struct {
+  u32 sig; /* nat46 signature */
+  int refcount;
+  int debug;
+
+  int npairs;
+  nat46_xlate_rulepair_t pairs[NUM_RULE_PAIRS_MAX]; /* npairs */
+  nat46_xlate_rulepair_t sorted_ipv4_local_pairs[NUM_RULE_PAIRS_MAX]; /* npairs */
+  nat46_xlate_rulepair_t sorted_ipv4_remote_pairs[NUM_RULE_PAIRS_MAX]; /* npairs */
+  nat46_xlate_rulepair_t sorted_ipv6_local_pairs[NUM_RULE_PAIRS_MAX]; /* npairs */
+  nat46_xlate_rulepair_t sorted_ipv6_remote_pairs[NUM_RULE_PAIRS_MAX]; /* npairs */
+} nat46_instance_t;
+
+void nat46_ipv6_input(struct sk_buff *old_skb);
+void nat46_ipv4_input(struct sk_buff *old_skb);
+
+int nat46_set_ipair_config(nat46_instance_t *nat46, int ipair, char *buf, int count);
+int nat46_set_config(nat46_instance_t *nat46, char *buf, int count);
+
+int nat46_get_ipair_config(nat46_instance_t *nat46, int ipair, char *buf, int count);
+int nat46_get_config(nat46_instance_t *nat46, char *buf, int count);
+
+char *get_next_arg(char **ptail);
+nat46_instance_t *get_nat46_instance(struct sk_buff *sk);
+
+nat46_instance_t *alloc_nat46_instance(int npairs, nat46_instance_t *old, int from_ipair, int to_ipair);
+void release_nat46_instance(nat46_instance_t *nat46);
+
+int xlate_6_to_4(struct net_device *dev, struct ipv6hdr *ip6h, uint16_t proto, __u32 *pv4saddr, __u32 *pv4daddr);
+int xlate_4_to_6(struct net_device *dev, struct iphdr *hdr4, uint16_t sport, uint16_t dport, void *v6saddr, void *v6daddr);
+void ip6_update_csum(struct sk_buff * skb, struct ipv6hdr * ip6hdr, int do_atomic_frag);
+bool nat46_get_rule_config(struct net_device *dev, nat46_xlate_rulepair_t **nat46_rule_pair, int *count);
+int nat46_get_npairs(struct net_device *dev);
+bool nat46_get_info(struct net_device *dev, nat46_xlate_rulepair_t **nat46_rule_pair,
+		int *count, u8 *flag);
+#endif
diff --git a/nat46/nat46/modules/nat46-glue.c b/nat46/nat46/modules/nat46-glue.c
new file mode 100644
index 0000000..06751fb
--- /dev/null
+++ b/nat46/nat46/modules/nat46-glue.c
@@ -0,0 +1,71 @@
+/*
+ * glue functions, candidates to go to -core
+ *
+ * Copyright (c) 2013-2014 Andrew Yourtchenko <ayourtch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+
+#include "nat46-glue.h"
+#include "nat46-core.h"
+
+static DEFINE_MUTEX(ref_lock);
+int is_valid_nat46(nat46_instance_t *nat46) {
+  return (nat46 && (nat46->sig == NAT46_SIGNATURE));
+}
+
+nat46_instance_t *alloc_nat46_instance(int npairs, nat46_instance_t *old, int from_ipair, int to_ipair) {
+  nat46_instance_t *nat46 = kzalloc(sizeof(nat46_instance_t) + npairs*sizeof(nat46_xlate_rulepair_t), GFP_KERNEL);
+  if (!nat46) {
+    printk("[nat46] make_nat46_instance: can not alloc a nat46 instance with %d pairs\n", npairs);
+    return NULL;
+  } else {
+    printk("[nat46] make_nat46_instance: allocated nat46 instance with %d pairs\n", npairs);
+  }
+  nat46->sig = NAT46_SIGNATURE;
+  nat46->npairs = npairs;
+  nat46->refcount = 1; /* The caller gets the reference */
+  if (old) {
+    nat46->debug = old->debug;
+    for(; (from_ipair >= 0) && (to_ipair >= 0) &&
+          (from_ipair < old->npairs) && (to_ipair < nat46->npairs); from_ipair++, to_ipair++) {
+      nat46->pairs[to_ipair] = old->pairs[from_ipair];
+    }
+  }
+  return nat46;
+}
+
+
+nat46_instance_t *get_nat46_instance(struct sk_buff *sk) {
+  nat46_instance_t *nat46 = netdev_nat46_instance(sk->dev);
+  mutex_lock(&ref_lock);
+  if (is_valid_nat46(nat46)) {
+    nat46->refcount++;
+    mutex_unlock(&ref_lock);
+    return nat46;
+  } else {
+    mutex_unlock(&ref_lock);
+    printk("[nat46] get_nat46_instance: Could not find a valid NAT46 instance!");
+    return NULL;
+  }
+}
+
+void release_nat46_instance(nat46_instance_t *nat46) {
+  mutex_lock(&ref_lock);
+  nat46->refcount--;
+  if(0 == nat46->refcount) {
+    nat46->sig = FREED_NAT46_SIGNATURE;
+    printk("[nat46] release_nat46_instance: freeing nat46 instance with %d pairs\n", nat46->npairs);
+    kfree(nat46);
+  }
+  mutex_unlock(&ref_lock);
+}
diff --git a/nat46/nat46/modules/nat46-glue.h b/nat46/nat46/modules/nat46-glue.h
new file mode 100644
index 0000000..bbd71f5
--- /dev/null
+++ b/nat46/nat46/modules/nat46-glue.h
@@ -0,0 +1,32 @@
+/*
+ * Glue headers, not much here.
+ *
+ * Copyright (c) 2013-2014 Andrew Yourtchenko <ayourtch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <net/ip.h>
+#include <net/ipv6.h>
+#include <linux/icmp.h>
+#include <linux/skbuff.h>
+#include <net/ip6_route.h>
+#include <linux/inet.h>
+#include <net/ip6_checksum.h>
+#include "nat46-netdev.h"
+
+
+#ifndef IP6_OFFSET
+#define IP6_OFFSET      0xFFF8
+#endif
+
+#define assert(x) printk("Assertion failed: %s", #x)
+
diff --git a/nat46/nat46/modules/nat46-module.c b/nat46/nat46/modules/nat46-module.c
new file mode 100644
index 0000000..fdb20ba
--- /dev/null
+++ b/nat46/nat46/modules/nat46-module.c
@@ -0,0 +1,200 @@
+/*
+ *
+ * module-wide functions, mostly boilerplate
+ *
+ * Copyright (c) 2013-2014 Andrew Yourtchenko <ayourtch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/ip.h>
+#include <linux/icmp.h>
+#include <linux/inet.h>
+#include <linux/icmpv6.h>
+#include <linux/inetdevice.h>
+#include <linux/types.h>
+#include <linux/netfilter_ipv4.h>
+
+
+#include <linux/fs.h>           // for basic filesystem
+#include <linux/proc_fs.h>      // for the proc filesystem
+#include <linux/seq_file.h>     // for sequence files
+
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <net/udp.h>
+#include <net/icmp.h>
+#include <net/route.h>
+#include <net/ip6_route.h>
+
+#include <net/ipv6.h>
+
+#include "nat46-core.h"
+#include "nat46-netdev.h"
+
+#define NAT46_PROC_NAME	"nat46"
+#define NAT46_CONTROL_PROC_NAME "control"
+
+#ifndef NAT46_VERSION
+#define NAT46_VERSION __DATE__ " " __TIME__
+#endif
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Andrew Yourtchenko <ayourtch@gmail.com>");
+MODULE_DESCRIPTION("NAT46 stateless translation");
+
+int debug = 0;
+module_param(debug, int, 0);
+MODULE_PARM_DESC(debug, "debugging messages level (default=1)");
+bool add_dummy_header = 0;
+module_param(add_dummy_header, bool, 0);
+MODULE_PARM_DESC(add_dummy_header, "Add dummy fragment header");
+
+static DEFINE_MUTEX(add_del_lock);
+static struct proc_dir_entry *nat46_proc_entry;
+static struct proc_dir_entry *nat46_proc_parent;
+
+
+static int nat46_proc_show(struct seq_file *m, void *v)
+{
+	nat64_show_all_configs(m);
+	return 0;
+}
+
+
+static int nat46_proc_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, nat46_proc_show, NULL);
+}
+
+static char *get_devname(char **ptail)
+{
+	const int maxlen = IFNAMSIZ-1;
+	char *devname = get_next_arg(ptail);
+	if(strlen(devname) > maxlen) {
+		printk(KERN_INFO "nat46: '%s' is "
+			"longer than %d chars, truncating\n", devname, maxlen);
+		devname[maxlen] = 0;
+	}
+	return devname;
+}
+
+static ssize_t nat46_proc_write(struct file *file, const char __user *buffer,
+                              size_t count, loff_t *ppos)
+{
+	char *buf = NULL;
+	char *tail = NULL;
+	char *devname = NULL;
+	char *arg_name = NULL;
+
+	buf = kmalloc(sizeof(char) * (count + 1), GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	if (copy_from_user(buf, buffer, count)) {
+		kfree(buf);
+		return -EFAULT;
+	}
+	tail = buf;
+	buf[count] = '\0';
+	if( (count > 0) && (buf[count-1] == '\n') ) {
+		buf[count-1] = '\0';
+	}
+
+	while (NULL != (arg_name = get_next_arg(&tail))) {
+		if (0 == strcmp(arg_name, "add")) {
+			devname = get_devname(&tail);
+			printk(KERN_INFO "nat46: adding device (%s)\n", devname);
+			mutex_lock(&add_del_lock);
+			nat46_create(devname);
+			mutex_unlock(&add_del_lock);
+		} else if (0 == strcmp(arg_name, "del")) {
+			devname = get_devname(&tail);
+			printk(KERN_INFO "nat46: deleting device (%s)\n", devname);
+			mutex_lock(&add_del_lock);
+			nat46_destroy(devname);
+			mutex_unlock(&add_del_lock);
+		} else if (0 == strcmp(arg_name, "config")) {
+			devname = get_devname(&tail);
+			printk(KERN_INFO "nat46: configure device (%s) with '%s'\n", devname, tail);
+			mutex_lock(&add_del_lock);
+			nat46_configure(devname, tail);
+			mutex_unlock(&add_del_lock);
+		} else if (0 == strcmp(arg_name, "insert")) {
+			devname = get_devname(&tail);
+			printk(KERN_INFO "nat46: insert new rule into device (%s) with '%s'\n", devname, tail);
+			mutex_lock(&add_del_lock);
+			nat46_insert(devname, tail);
+			mutex_unlock(&add_del_lock);
+		}
+	}
+
+	kfree(buf);
+	return count;
+}
+
+static const struct file_operations nat46_proc_fops = {
+	.owner		= THIS_MODULE,
+	.open		= nat46_proc_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+	.write		= nat46_proc_write,
+};
+
+
+int create_nat46_proc_entry(void) {
+	nat46_proc_parent = proc_mkdir(NAT46_PROC_NAME, init_net.proc_net);
+	if (nat46_proc_parent) {
+		nat46_proc_entry = proc_create(NAT46_CONTROL_PROC_NAME, 0644, nat46_proc_parent, &nat46_proc_fops );
+		if(!nat46_proc_entry) {
+			printk(KERN_INFO "Error creating proc entry");
+			return -ENOMEM;
+		}
+	}
+	return 0;
+}
+
+
+static int __init nat46_init(void)
+{
+	int ret = 0;
+
+	printk("nat46: module (version %s) loaded.\n", NAT46_VERSION);
+	ret = create_nat46_proc_entry();
+	if(ret) {
+		goto error;
+	}
+	return 0;
+
+error:
+	return ret;
+}
+
+static void __exit nat46_exit(void)
+{
+	nat46_destroy_all();
+	if (nat46_proc_parent) {
+		if (nat46_proc_entry) {
+			remove_proc_entry(NAT46_CONTROL_PROC_NAME, nat46_proc_parent);
+		}
+		remove_proc_entry(NAT46_PROC_NAME, init_net.proc_net);
+	}
+	printk("nat46: module unloaded.\n");
+}
+
+module_init(nat46_init);
+module_exit(nat46_exit);
+
+
diff --git a/nat46/nat46/modules/nat46-module.h b/nat46/nat46/modules/nat46-module.h
new file mode 100644
index 0000000..ffb0a76
--- /dev/null
+++ b/nat46/nat46/modules/nat46-module.h
@@ -0,0 +1,17 @@
+/*
+ *
+ * Copyright (c) 2013-2014 Andrew Yourtchenko <ayourtch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+extern int debug;
+extern bool add_dummy_header;
diff --git a/nat46/nat46/modules/nat46-netdev.c b/nat46/nat46/modules/nat46-netdev.c
new file mode 100644
index 0000000..b845020
--- /dev/null
+++ b/nat46/nat46/modules/nat46-netdev.c
@@ -0,0 +1,402 @@
+/*
+ * Network device related boilerplate functions
+ *
+ * Copyright (c) 2013-2014 Andrew Yourtchenko <ayourtch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+
+
+#include <linux/if_arp.h>
+#include <linux/netdevice.h>
+#include <linux/route.h>
+#include <linux/skbuff.h>
+#include <net/ip6_fib.h>
+#include <net/ip6_route.h>
+#include <net/ipv6.h>
+#include <linux/version.h>
+#include <net/ip_tunnels.h>
+#include <linux/radix-tree.h>
+#include "nat46-core.h"
+#include "nat46-module.h"
+
+#define NETDEV_DEFAULT_NAME "nat46."
+static RADIX_TREE(netdev_tree, GFP_ATOMIC);
+
+typedef struct {
+  u32 sig;
+  nat46_instance_t *nat46;
+} nat46_netdev_priv_t;
+
+static u8 netdev_count = 0;
+
+static int nat46_netdev_up(struct net_device *dev);
+static int nat46_netdev_down(struct net_device *dev);
+static int nat46_netdev_init(struct net_device *dev);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,4,0)
+static void nat46_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *tot);
+#else
+static struct rtnl_link_stats64 *nat46_get_stats64(struct net_device *dev,
+                                                   struct rtnl_link_stats64 *tot);
+#endif
+static netdev_tx_t nat46_netdev_xmit(struct sk_buff *skb, struct net_device *dev);
+
+
+static const struct net_device_ops nat46_netdev_ops = {
+	.ndo_init       = nat46_netdev_init,	/* device specific initialization */
+	.ndo_open       = nat46_netdev_up,      /* Called at ifconfig nat46 up */
+	.ndo_stop       = nat46_netdev_down,    /* Called at ifconfig nat46 down */
+	.ndo_start_xmit = nat46_netdev_xmit,    /* REQUIRED, must return NETDEV_TX_OK */
+	.ndo_get_stats64 = nat46_get_stats64,	/* 64 bit device stats */
+};
+
+static int nat46_netdev_init(struct net_device *dev)
+{
+	int i;
+	dev->tstats = alloc_percpu(struct pcpu_sw_netstats);
+	if (!dev->tstats) {
+		return -ENOMEM;
+	}
+
+	for_each_possible_cpu(i) {
+		struct pcpu_sw_netstats *ipt_stats;
+		ipt_stats = per_cpu_ptr(dev->tstats, i);
+		u64_stats_init(&ipt_stats->syncp);
+	}
+	return 0;
+}
+
+static void nat46_netdev_resource_free(struct net_device *dev)
+{
+	free_percpu(dev->tstats);
+}
+
+static int nat46_netdev_up(struct net_device *dev)
+{
+	netif_start_queue(dev);
+	return 0;
+}
+
+static int nat46_netdev_down(struct net_device *dev)
+{
+	netif_stop_queue(dev);
+	return 0;
+}
+
+static netdev_tx_t nat46_netdev_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct pcpu_sw_netstats *tstats = get_cpu_ptr(dev->tstats);
+
+	u64_stats_update_begin(&tstats->syncp);
+	tstats->rx_packets++;
+	tstats->rx_bytes += skb->len;
+	u64_stats_update_end(&tstats->syncp);
+	put_cpu_ptr(tstats);
+	if(ETH_P_IP == ntohs(skb->protocol)) {
+		nat46_ipv4_input(skb);
+	}
+	if(ETH_P_IPV6 == ntohs(skb->protocol)) {
+		nat46_ipv6_input(skb);
+	}
+	kfree_skb(skb);
+	return NETDEV_TX_OK;
+}
+
+void nat46_netdev_count_xmit(struct sk_buff *skb, struct net_device *dev) {
+	struct pcpu_sw_netstats *tstats = get_cpu_ptr(dev->tstats);
+
+	u64_stats_update_begin(&tstats->syncp);
+	tstats->tx_packets++;
+	tstats->tx_bytes += skb->len;
+	u64_stats_update_end(&tstats->syncp);
+	put_cpu_ptr(tstats);
+}
+
+void nat46_update_stats(struct net_device *dev, uint32_t rx_packets, uint32_t rx_bytes,
+			uint32_t tx_packets, uint32_t tx_bytes, uint32_t rx_dropped, uint32_t tx_dropped)
+{
+	struct pcpu_sw_netstats *tstats = get_cpu_ptr(dev->tstats);
+
+	u64_stats_update_begin(&tstats->syncp);
+	tstats->rx_packets += rx_packets;
+	tstats->rx_bytes += rx_bytes;
+	tstats->tx_packets += tx_packets;
+	tstats->tx_bytes += tx_bytes;
+	dev->stats.rx_dropped += rx_dropped;
+	dev->stats.tx_dropped += tx_dropped;
+	u64_stats_update_end(&tstats->syncp);
+	put_cpu_ptr(tstats);
+}
+EXPORT_SYMBOL(nat46_update_stats);
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,4,0)
+static void nat46_get_stats64(struct net_device *dev,
+#else
+static struct rtnl_link_stats64 *nat46_get_stats64(struct net_device *dev,
+#endif
+		struct rtnl_link_stats64 *tot)
+{
+	ip_tunnel_get_stats64(dev, tot);
+}
+
+void *netdev_nat46_instance(struct net_device *dev) {
+	nat46_netdev_priv_t *priv = netdev_priv(dev);
+	return priv->nat46;
+}
+
+static void netdev_nat46_set_instance(struct net_device *dev, nat46_instance_t *new_nat46) {
+	nat46_netdev_priv_t *priv = netdev_priv(dev);
+	if(priv->nat46) {
+		release_nat46_instance(priv->nat46);
+	}
+	priv->nat46 = new_nat46;
+}
+
+static void nat46_netdev_setup(struct net_device *dev)
+{
+	nat46_netdev_priv_t *priv = netdev_priv(dev);
+	nat46_instance_t *nat46 = alloc_nat46_instance(1, NULL, -1, -1);
+
+	memset(priv, 0, sizeof(*priv));
+	priv->sig = NAT46_DEVICE_SIGNATURE;
+	priv->nat46 = nat46;
+
+	dev->netdev_ops = &nat46_netdev_ops;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,4,0)
+	dev->priv_destructor = nat46_netdev_resource_free;
+#else
+	dev->destructor = nat46_netdev_resource_free;
+#endif
+	dev->type = ARPHRD_NONE;
+	dev->hard_header_len = 0;
+	dev->addr_len = 0;
+	dev->mtu = 16384; /* iptables does reassembly. Rather than using ETH_DATA_LEN, let's try to get as much mileage as we can with the Linux stack */
+	dev->features = NETIF_F_NETNS_LOCAL;
+	dev->flags = IFF_NOARP | IFF_POINTOPOINT;
+}
+
+int nat46_netdev_create(char *basename, struct net_device **dev)
+{
+	int ret = 0;
+	char *devname = NULL;
+	int automatic_name = 0;
+
+	if (basename && strcmp("", basename)) {
+		devname = kmalloc(strlen(basename)+1, GFP_KERNEL);
+	} else {
+		devname = kmalloc(strlen(NETDEV_DEFAULT_NAME)+3+1, GFP_KERNEL);
+		automatic_name = 1;
+	}
+	if (!devname) {
+		printk("nat46: can not allocate memory to store device name.\n");
+		ret = -ENOMEM;
+		goto err;
+	}
+	if (automatic_name) {
+		snprintf(devname, strlen(NETDEV_DEFAULT_NAME)+3, "%s%d", NETDEV_DEFAULT_NAME, netdev_count);
+		netdev_count++;
+	} else {
+		strcpy(devname, basename);
+	}
+
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(3,17,0)
+	*dev = alloc_netdev(sizeof(nat46_instance_t), devname, nat46_netdev_setup);
+#else
+	*dev = alloc_netdev(sizeof(nat46_instance_t), devname, NET_NAME_UNKNOWN, nat46_netdev_setup);
+#endif
+	if (!*dev) {
+		printk("nat46: Unable to allocate nat46 device '%s'.\n", devname);
+		ret = -ENOMEM;
+		goto err_alloc_dev;
+	}
+
+	ret = register_netdev(*dev);
+	if(ret) {
+		printk("nat46: Unable to register nat46 device.\n");
+		ret = -ENOMEM;
+		goto err_register_dev;
+	}
+
+	printk("nat46: netdevice nat46 '%s' created successfully.\n", devname);
+	kfree(devname);
+
+	/*
+	 * add this netdevice to list
+	 */
+	radix_tree_insert(&netdev_tree, (*dev)->ifindex, (void *)*dev);
+
+	return 0;
+
+err_register_dev:
+	free_netdev(*dev);
+err_alloc_dev:
+	kfree(devname);
+err:
+	return ret;
+}
+
+void nat46_netdev_destroy(struct net_device *dev)
+{
+	netdev_nat46_set_instance(dev, NULL);
+	unregister_netdev(dev);
+	radix_tree_delete(&netdev_tree, dev->ifindex);
+	printk("nat46: Destroying nat46 device.\n");
+}
+
+bool is_map_t_dev(struct net_device *dev)
+{
+	if(!dev) {
+		return false;
+	}
+
+	if(radix_tree_lookup(&netdev_tree, dev->ifindex)) {
+		return true;
+	}
+	return false;
+}
+EXPORT_SYMBOL(is_map_t_dev);
+
+static int is_nat46(struct net_device *dev) {
+	nat46_netdev_priv_t *priv = netdev_priv(dev);
+	return (priv && (NAT46_DEVICE_SIGNATURE == priv->sig));
+}
+
+
+static struct net_device *find_dev(char *name) {
+	struct net_device *dev;
+	struct net_device *out = NULL;
+
+	if(!name) {
+		return NULL;
+	}
+
+	read_lock(&dev_base_lock);
+	dev = first_net_device(&init_net);
+	while (dev) {
+		if((0 == strcmp(dev->name, name)) && is_nat46(dev)) {
+			if(debug) {
+				printk(KERN_INFO "found [%s]\n", dev->name);
+			}
+			out = dev;
+			break;
+		}
+		dev = next_net_device(dev);
+	}
+	read_unlock(&dev_base_lock);
+	return out;
+}
+
+int nat46_create(char *devname) {
+	int ret = 0;
+	struct net_device *dev = find_dev(devname);
+	if (dev) {
+		printk("Can not add: device '%s' already exists!\n", devname);
+		return -1;
+	}
+	ret = nat46_netdev_create(devname, &dev);
+	return ret;
+}
+
+int nat46_destroy(char *devname) {
+	struct net_device *dev = find_dev(devname);
+	if(dev) {
+		printk("Destroying '%s'\n", devname);
+		nat46_netdev_destroy(dev);
+		return 0;
+	} else {
+		printk("Could not find device '%s'\n", devname);
+		return -1;
+	}
+}
+
+int nat46_insert(char *devname, char *buf) {
+	struct net_device *dev = find_dev(devname);
+	int ret = -1;
+	if(dev) {
+		nat46_instance_t *nat46 = netdev_nat46_instance(dev);
+		nat46_instance_t *nat46_new;
+		if(nat46->npairs == NUM_RULE_PAIRS_MAX) {
+			printk("Could not insert a new rule on device %s\n", devname);
+			return ret;
+		}
+
+		nat46_new = alloc_nat46_instance(nat46->npairs+1, nat46, 0, 1);
+		if(nat46_new) {
+			netdev_nat46_set_instance(dev, nat46_new);
+			ret = nat46_set_ipair_config(nat46_new, 0, buf, strlen(buf));
+		} else {
+			printk("Could not insert a new rule on device %s\n", devname);
+		}
+	}
+	return ret;
+}
+
+int nat46_configure(char *devname, char *buf) {
+	struct net_device *dev = find_dev(devname);
+	if(dev) {
+		nat46_instance_t *nat46 = netdev_nat46_instance(dev);
+		return nat46_set_config(nat46, buf, strlen(buf));
+	} else {
+		return -1;
+	}
+}
+
+void nat64_show_all_configs(struct seq_file *m) {
+        struct net_device *dev;
+	read_lock(&dev_base_lock);
+	dev = first_net_device(&init_net);
+	while (dev) {
+		if(is_nat46(dev)) {
+			nat46_instance_t *nat46 = netdev_nat46_instance(dev);
+			int buflen = 1024;
+			int ipair = -1;
+			char *buf = kmalloc(buflen+1, GFP_KERNEL);
+			seq_printf(m, "add %s\n", dev->name);
+			if(buf) {
+				for(ipair = 0; ipair < nat46->npairs; ipair++) {
+					nat46_get_ipair_config(nat46, ipair, buf, buflen);
+					if(ipair < nat46->npairs-1) {
+						seq_printf(m,"insert %s %s\n", dev->name, buf);
+					} else {
+						seq_printf(m,"config %s %s\n", dev->name, buf);
+					}
+				}
+				seq_printf(m,"\n");
+				kfree(buf);
+			}
+		}
+		dev = next_net_device(dev);
+	}
+	read_unlock(&dev_base_lock);
+
+}
+
+void nat46_destroy_all(void) {
+        struct net_device *dev;
+        struct net_device *nat46dev;
+	do {
+		read_lock(&dev_base_lock);
+		nat46dev = NULL;
+		dev = first_net_device(&init_net);
+		while (dev) {
+			if(is_nat46(dev)) {
+				nat46dev = dev;
+			}
+			dev = next_net_device(dev);
+		}
+		read_unlock(&dev_base_lock);
+		if(nat46dev) {
+			nat46_netdev_destroy(nat46dev);
+		}
+	} while (nat46dev);
+
+}
diff --git a/nat46/nat46/modules/nat46-netdev.h b/nat46/nat46/modules/nat46-netdev.h
new file mode 100644
index 0000000..a9e8596
--- /dev/null
+++ b/nat46/nat46/modules/nat46-netdev.h
@@ -0,0 +1,29 @@
+/*
+ *
+ * Copyright (c) 2013-2014 Andrew Yourtchenko <ayourtch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define NAT46_DEVICE_SIGNATURE 0x544e36dd
+
+int nat46_create(char *devname);
+int nat46_destroy(char *devname);
+int nat46_insert(char *devname, char *buf);
+int nat46_configure(char *devname, char *buf);
+void nat46_destroy_all(void);
+void nat64_show_all_configs(struct seq_file *m);
+void nat46_netdev_count_xmit(struct sk_buff *skb, struct net_device *dev);
+void *netdev_nat46_instance(struct net_device *dev);
+
+void nat46_update_stats(struct net_device *dev, uint32_t rx_packets, uint32_t rx_bytes, uint32_t tx_packets, uint32_t tx_bytes,
+							uint32_t rx_dropped, uint32_t tx_dropped);
+bool is_map_t_dev(struct net_device *dev);
diff --git a/qca-nss-clients/.gitignore b/qca-nss-clients/.gitignore
new file mode 100644
index 0000000..cb831ad
--- /dev/null
+++ b/qca-nss-clients/.gitignore
@@ -0,0 +1,14 @@
+
+# Ignore general build intermediate files
+*.o
+*.cmd
+*.ko
+*.mod.*
+*.mod
+Module.symvers
+modules.order
+/.tmp_versions/
+built-in.a
+
+# don't ignore .gitignore itself
+!.gitignore
diff --git a/qca-nss-clients/Makefile b/qca-nss-clients/Makefile
new file mode 100644
index 0000000..b0fb42d
--- /dev/null
+++ b/qca-nss-clients/Makefile
@@ -0,0 +1,47 @@
+# Makefile for the clients using the NSS driver
+
+ccflags-y := -I$(obj) -I$(obj)/..
+
+export BUILD_ID = "Build ID $(shell git rev-parse HEAD | head -c 8)"
+ccflags-y += -DNSS_CLIENT_BUILD_ID=$(BUILD_ID)
+
+qca-nss-tun6rd-objs := nss_connmgr_tun6rd.o
+
+ccflags-y += -DNSS_TUN6RD_DEBUG_LEVEL=0
+ccflags-y += -Werror
+
+KERNELVERSION := $(word 1, $(subst ., ,$(KERNELVERSION))).$(word 2, $(subst ., ,$(KERNELVERSION)))
+
+obj-$(bridge-mgr)+= bridge/
+obj-$(capwapmgr)+= capwapmgr/
+obj-$(dtlsmgr)+= dtls/$(DTLSMGR_DIR)/
+obj-$(gre)+= gre/
+obj-$(ipsecmgr)+= ipsecmgr/$(IPSECMGR_DIR)/
+obj-$(ipsecmgr-klips)+= ipsecmgr/$(IPSECMGR_DIR)/plugins/klips/
+obj-$(ipsecmgr-xfrm)+= ipsecmgr/$(IPSECMGR_DIR)/plugins/xfrm/
+obj-$(l2tpv2)+= l2tp/l2tpv2/
+obj-$(lag-mgr)+= lag/
+obj-$(map-t)+= map/map-t/
+obj-$(portifmgr)+= portifmgr/
+obj-$(pptp)+= pptp/
+obj-$(profile)+= profiler/
+obj-$(tunipip6)+= tunipip6/
+obj-$(tun6rd)+= qca-nss-tun6rd.o
+obj-$(qdisc)+= nss_qdisc/
+obj-$(vlan-mgr)+= vlan/
+obj-$(vxlanmgr)+= vxlanmgr/
+obj-$(pvxlanmgr)+= pvxlanmgr/
+obj-$(pppoe)+= pppoe/
+obj-$(ovpn-mgr)+= openvpn/
+obj-$(eogremgr)+= eogremgr/
+obj-$(clmapmgr)+= clmapmgr/
+obj-$(match)+= match/
+obj-$(tlsmgr)+= tls/
+obj-$(mirror)+= mirror/
+obj-$(mscs)+= mscs/
+obj-$(wifi-meshmgr)+= wifi_meshmgr/
+
+#NSS NETLINK
+obj-$(netlink)+= netlink/
+
+obj ?= .
diff --git a/qca-nss-clients/Makefile.fsm b/qca-nss-clients/Makefile.fsm
new file mode 100644
index 0000000..0ff2994
--- /dev/null
+++ b/qca-nss-clients/Makefile.fsm
@@ -0,0 +1,19 @@
+# Makefile for the clients using the NSS driver
+
+ccflags-y := -I$(obj) -I$(obj)/..
+export SoC = fsm9010
+
+export BUILD_ID = \"Build Id: $(shell date +'%m/%d/%y, %H:%M:%S')\"
+ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)"
+
+# Profiler
+obj-y+= profiler/
+
+#IPsec manager
+obj-y+= ipsecmgr/
+
+#NSS NETLINK
+obj-y+= netlink/
+
+obj ?= .
+
diff --git a/qca-nss-clients/bridge/Makefile b/qca-nss-clients/bridge/Makefile
new file mode 100644
index 0000000..80cec23
--- /dev/null
+++ b/qca-nss-clients/bridge/Makefile
@@ -0,0 +1,20 @@
+ccflags-y := -I$(obj)/../exports -I$(obj)/..  -I$(obj)/nss_hal/include
+ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)"
+ccflags-$(NSS_BRIDGE_MGR_OVS_ENABLE) += -DNSS_BRIDGE_MGR_OVS_ENABLE
+
+obj-m += qca-nss-bridge-mgr.o
+qca-nss-bridge-mgr-objs := nss_bridge_mgr.o
+ifeq ($(NSS_BRIDGE_MGR_OVS_ENABLE), y)
+qca-nss-bridge-mgr-objs += nss_bridge_mgr_ovs.o
+endif
+
+ccflags-y += -DNSS_BRIDGE_MGR_DEBUG_LEVEL=0
+ccflags-y += -Wall -Werror
+
+ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64 ipq60xx ipq60xx_64))
+ccflags-y += -DNSS_BRIDGE_MGR_PPE_SUPPORT
+endif
+
+ifneq (,$(filter $(CONFIG_BONDING),y m))
+ccflags-y += -DBONDING_SUPPORT
+endif
diff --git a/qca-nss-clients/bridge/nss_bridge_mgr.c b/qca-nss-clients/bridge/nss_bridge_mgr.c
new file mode 100644
index 0000000..57f1e2d
--- /dev/null
+++ b/qca-nss-clients/bridge/nss_bridge_mgr.c
@@ -0,0 +1,1644 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_bridge_mgr.c
+ *	NSS to HLOS Bridge Interface manager
+ */
+#include <linux/sysctl.h>
+#include <linux/etherdevice.h>
+#include <linux/if_vlan.h>
+#include <linux/of.h>
+#include <linux/if_bridge.h>
+#include <net/bonding.h>
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+#include <ref/ref_vsi.h>
+#include <nss_vlan_mgr.h>
+#include <fal/fal_fdb.h>
+#include <fal/fal_stp.h>
+#include <fal/fal_acl.h>
+#include <fal/fal_api.h>
+#include <fal/fal_port_ctrl.h>
+#endif
+#include <nss_api_if.h>
+
+#if defined(NSS_BRIDGE_MGR_OVS_ENABLE)
+#include <ovsmgr.h>
+#endif
+
+#include "nss_bridge_mgr_priv.h"
+
+/*
+ * Module parameter to enable/disable OVS bridge.
+ */
+static bool ovs_enabled = false;
+
+static struct nss_bridge_mgr_context br_mgr_ctx;
+
+/*
+ * nss_bridge_mgr_create_instance()
+ *	Create a bridge instance.
+ */
+static struct nss_bridge_pvt *nss_bridge_mgr_create_instance(struct net_device *dev)
+{
+	struct nss_bridge_pvt *br;
+
+#if !defined(NSS_BRIDGE_MGR_OVS_ENABLE)
+	if (!netif_is_bridge_master(dev))
+		return NULL;
+#else
+	/*
+	 * When OVS is enabled, we have to check for both bridge master
+	 * and OVS master.
+	 */
+	if (!netif_is_bridge_master(dev) && !ovsmgr_is_ovs_master(dev))
+		return NULL;
+#endif
+
+	br = kzalloc(sizeof(*br), GFP_KERNEL);
+	if (!br)
+		return NULL;
+
+	INIT_LIST_HEAD(&br->list);
+
+	return br;
+}
+
+/*
+ * nss_bridge_mgr_delete_instance()
+ *	Delete a bridge instance from bridge list and free the bridge instance.
+ */
+static void nss_bridge_mgr_delete_instance(struct nss_bridge_pvt *br)
+{
+	spin_lock(&br_mgr_ctx.lock);
+	if (!list_empty(&br->list))
+		list_del(&br->list);
+
+	spin_unlock(&br_mgr_ctx.lock);
+
+	kfree(br);
+}
+
+/*
+ * nss_bridge_mgr_find_instance()
+ *	Find a bridge instance from bridge list.
+ */
+struct nss_bridge_pvt *nss_bridge_mgr_find_instance(struct net_device *dev)
+{
+	struct nss_bridge_pvt *br;
+
+#if !defined(NSS_BRIDGE_MGR_OVS_ENABLE)
+	if (!netif_is_bridge_master(dev))
+		return NULL;
+#else
+	/*
+	 * When OVS is enabled, we have to check for both bridge master
+	 * and OVS master.
+	 */
+	if (!netif_is_bridge_master(dev) && !ovsmgr_is_ovs_master(dev))
+		return NULL;
+#endif
+	/*
+	 * Do we have it on record?
+	 */
+	spin_lock(&br_mgr_ctx.lock);
+	list_for_each_entry(br, &br_mgr_ctx.list, list) {
+		if (br->dev == dev) {
+			spin_unlock(&br_mgr_ctx.lock);
+			return br;
+		}
+	}
+
+	spin_unlock(&br_mgr_ctx.lock);
+	return NULL;
+}
+
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+/*
+ * nss_bridge_mgr_enable_fdb_learning()
+ *	Enable fdb learning in PPE.
+ */
+static int nss_bridge_mgr_enable_fdb_learning(struct nss_bridge_pvt *br)
+{
+	fal_vsi_newaddr_lrn_t newaddr_lrn;
+	fal_vsi_stamove_t sta_move;
+
+	/*
+	 * Enable station move
+	 */
+	sta_move.stamove_en = 1;
+	sta_move.action = FAL_MAC_FRWRD;
+	if (fal_vsi_stamove_set(NSS_BRIDGE_MGR_SWITCH_ID, br->vsi, &sta_move)) {
+		nss_bridge_mgr_warn("%px: Failed to enable station move for Bridge vsi\n", br);
+		return -1;
+	}
+
+	/*
+	 * Enable FDB learning in PPE
+	 */
+	newaddr_lrn.lrn_en = 1;
+	newaddr_lrn.action = FAL_MAC_FRWRD;
+	if (fal_vsi_newaddr_lrn_set(NSS_BRIDGE_MGR_SWITCH_ID, br->vsi, &newaddr_lrn)) {
+		nss_bridge_mgr_warn("%px: Failed to enable FDB learning for Bridge vsi\n", br);
+		goto disable_sta_move;
+	}
+
+	/*
+	 * Send a notification to NSS for FDB learning enable.
+	 */
+	if (nss_bridge_tx_set_fdb_learn_msg(br->ifnum, NSS_BRIDGE_FDB_LEARN_ENABLE) != NSS_TX_SUCCESS) {
+		nss_bridge_mgr_warn("%px: Tx message failed for FDB learning status\n", br);
+		goto disable_fdb_learning;
+	}
+
+	return 0;
+
+disable_fdb_learning:
+	newaddr_lrn.lrn_en = 0;
+	newaddr_lrn.action = FAL_MAC_FRWRD;
+	if (fal_vsi_newaddr_lrn_set(NSS_BRIDGE_MGR_SWITCH_ID, br->vsi, &newaddr_lrn))
+		nss_bridge_mgr_warn("%px: Failed to disable FDB learning for Bridge vsi\n", br);
+
+disable_sta_move:
+	sta_move.stamove_en = 0;
+	sta_move.action = FAL_MAC_FRWRD;
+	if (fal_vsi_stamove_set(NSS_BRIDGE_MGR_SWITCH_ID, br->vsi, &sta_move))
+		nss_bridge_mgr_warn("%px: Failed to disable station move for Bridge vsi\n", br);
+
+	return -1;
+}
+
+/*
+ * nss_bridge_mgr_disable_fdb_learning()
+ *	Disable fdb learning in PPE
+ *
+ * For the first time a bond interface join bridge, we need to use flow based rule.
+ * FDB learing/station move need to be disabled.
+ */
+static int nss_bridge_mgr_disable_fdb_learning(struct nss_bridge_pvt *br)
+{
+	fal_vsi_newaddr_lrn_t newaddr_lrn;
+	fal_vsi_stamove_t sta_move;
+
+	/*
+	 * Disable station move
+	 */
+	sta_move.stamove_en = 0;
+	sta_move.action = FAL_MAC_FRWRD;
+	if (fal_vsi_stamove_set(NSS_BRIDGE_MGR_SWITCH_ID, br->vsi, &sta_move)) {
+		nss_bridge_mgr_warn("%px: Failed to disable station move for Bridge vsi\n", br);
+		return -1;
+	}
+
+	/*
+	 * Disable FDB learning in PPE
+	 */
+	newaddr_lrn.lrn_en = 0;
+	newaddr_lrn.action = FAL_MAC_FRWRD;
+	if (fal_vsi_newaddr_lrn_set(NSS_BRIDGE_MGR_SWITCH_ID, br->vsi, &newaddr_lrn)) {
+		nss_bridge_mgr_warn("%px: Failed to disable FDB learning for Bridge vsi\n", br);
+		goto enable_sta_move;
+	}
+
+	/*
+	 * Flush FDB table for the bridge vsi
+	 */
+	if (fal_fdb_entry_del_byfid(NSS_BRIDGE_MGR_SWITCH_ID, br->vsi, FAL_FDB_DEL_STATIC)) {
+		nss_bridge_mgr_warn("%px: Failed to flush FDB table for vsi:%d in PPE\n", br, br->vsi);
+		goto enable_fdb_learning;
+	}
+
+	/*
+	 * Send a notification to NSS for FDB learning disable.
+	 */
+	if (nss_bridge_tx_set_fdb_learn_msg(br->ifnum, NSS_BRIDGE_FDB_LEARN_DISABLE) != NSS_TX_SUCCESS) {
+		nss_bridge_mgr_warn("%px: Tx message failed for FDB learning status\n", br);
+		goto enable_fdb_learning;
+	}
+
+	return 0;
+
+enable_fdb_learning:
+	newaddr_lrn.lrn_en = 1;
+	newaddr_lrn.action = FAL_MAC_FRWRD;
+	if (fal_vsi_newaddr_lrn_set(NSS_BRIDGE_MGR_SWITCH_ID, br->vsi, &newaddr_lrn))
+		nss_bridge_mgr_warn("%px: Failed to enable FDB learning for Bridge vsi\n", br);
+
+enable_sta_move:
+	sta_move.stamove_en = 1;
+	sta_move.action = FAL_MAC_FRWRD;
+	if (fal_vsi_stamove_set(NSS_BRIDGE_MGR_SWITCH_ID, br->vsi, &sta_move))
+		nss_bridge_mgr_warn("%px: Failed to enable station move for Bridge vsi\n", br);
+
+	return -1;
+}
+
+/*
+ * nss_bridge_mgr_add_bond_slave()
+ *	A slave interface being added to a bond master that belongs to a bridge.
+ */
+static int nss_bridge_mgr_add_bond_slave(struct net_device *bond_master,
+		struct net_device *slave, struct nss_bridge_pvt *b_pvt)
+{
+	uint32_t *port_vsi;
+	int32_t port_id;
+	int32_t ifnum;
+	int32_t lagid = 0;
+	int32_t bondid = -1;
+
+	/*
+	 * Figure out the aggregation id of this slave
+	 */
+#if defined(BONDING_SUPPORT)
+	bondid = bond_get_id(bond_master);
+#endif
+	if (bondid < 0) {
+		nss_bridge_mgr_warn("%px: Invalid LAG group id 0x%x\n",
+				b_pvt, bondid);
+		return -1;
+	}
+
+	lagid = bondid + NSS_LAG0_INTERFACE_NUM;
+
+	nss_bridge_mgr_trace("%px: Bond Slave %s is added bridge\n",
+			b_pvt, slave->name);
+
+	ifnum = nss_cmn_get_interface_number_by_dev(slave);
+
+	/*
+	 * Hardware supports only PHYSICAL Ports as trunk ports
+	 */
+	if (!NSS_BRIDGE_MGR_IF_IS_TYPE_PHYSICAL(ifnum)) {
+		nss_bridge_mgr_warn("%px: Interface %s is not Physical Interface\n",
+				b_pvt, slave->name);
+		return -1;
+	}
+
+	nss_bridge_mgr_trace("%px: Interface %s adding into bridge\n",
+			b_pvt, slave->name);
+	port_id = ifnum;
+
+	/*
+	 * Take bridge lock as we are updating vsi and port forwarding
+	 * details in PPE Hardware
+	 */
+	spin_lock(&br_mgr_ctx.lock);
+	port_vsi = &b_pvt->port_vsi[port_id - 1];
+
+	if (ppe_port_vsi_get(NSS_BRIDGE_MGR_SWITCH_ID, port_id, port_vsi)) {
+		spin_unlock(&br_mgr_ctx.lock);
+		nss_bridge_mgr_warn("%px: Couldn't get VSI for port %d\n",
+				b_pvt, port_id);
+		return -1;
+	}
+
+	if (ppe_port_vsi_set(NSS_BRIDGE_MGR_SWITCH_ID, port_id, b_pvt->vsi)) {
+		spin_unlock(&br_mgr_ctx.lock);
+		nss_bridge_mgr_warn("%px: Couldn't set bridge VSI for port %d\n",
+				b_pvt, port_id);
+		return -1;
+	}
+	spin_unlock(&br_mgr_ctx.lock);
+
+	if (nss_bridge_tx_join_msg(b_pvt->ifnum,
+				slave) != NSS_TX_SUCCESS) {
+		if (ppe_port_vsi_set(NSS_BRIDGE_MGR_SWITCH_ID, port_id, *port_vsi))
+			nss_bridge_mgr_warn("%px: Couldn't set bridge VSI for port %d\n", b_pvt, port_id);
+		nss_bridge_mgr_warn("%px: Couldn't add port %d in bridge",
+				b_pvt, port_id);
+		return -1;
+	}
+
+	spin_lock(&br_mgr_ctx.lock);
+	b_pvt->lag_ports[port_id - 1] = lagid;
+	spin_unlock(&br_mgr_ctx.lock);
+
+	return 0;
+}
+
+/*
+ * nss_bridge_mgr_del_bond_slave()
+ *	A slave interface being removed from a bond master that belongs to a bridge.
+ */
+static int nss_bridge_mgr_del_bond_slave(struct net_device *bond_master,
+		struct net_device *slave, struct nss_bridge_pvt *b_pvt)
+{
+	uint32_t *port_vsi;
+	int32_t port_id;
+	int32_t ifnum;
+	int32_t lagid = 0;
+	int32_t bondid = -1;
+
+	/*
+	 * Figure out the aggregation id of this slave
+	 */
+#if defined(BONDING_SUPPORT)
+	bondid = bond_get_id(bond_master);
+#endif
+	if (bondid < 0) {
+		nss_bridge_mgr_warn("%px: Invalid LAG group id 0x%x\n",
+				b_pvt, bondid);
+		return -1;
+	}
+
+	lagid = bondid + NSS_LAG0_INTERFACE_NUM;
+
+	nss_bridge_mgr_trace("%px: Bond Slave %s leaving bridge\n",
+			b_pvt, slave->name);
+
+	ifnum = nss_cmn_get_interface_number_by_dev(slave);
+
+	/*
+	 * Hardware supports only PHYSICAL Ports as trunk ports
+	 */
+	if (!NSS_BRIDGE_MGR_IF_IS_TYPE_PHYSICAL(ifnum)) {
+		nss_bridge_mgr_warn("%px: Interface %s is not Physical Interface\n",
+				b_pvt, slave->name);
+		return -1;
+	}
+
+	nss_bridge_mgr_trace("%px: Interface %s leaving from bridge\n",
+			b_pvt, slave->name);
+
+	port_id = (fal_port_t)ifnum;
+
+	/*
+	 * Take bridge lock as we are updating vsi and port forwarding
+	 * details in PPE Hardware
+	 */
+	spin_lock(&br_mgr_ctx.lock);
+	port_vsi = &b_pvt->port_vsi[port_id - 1];
+
+	if (b_pvt->lag_ports[port_id - 1] != lagid) {
+		spin_unlock(&br_mgr_ctx.lock);
+		return -1;
+	}
+
+	if (ppe_port_vsi_set(NSS_BRIDGE_MGR_SWITCH_ID, port_id, *port_vsi)) {
+		spin_unlock(&br_mgr_ctx.lock);
+		nss_bridge_mgr_warn("%px: failed to restore port VSI for port %d\n", b_pvt, port_id);
+		return -1;
+	}
+	spin_unlock(&br_mgr_ctx.lock);
+
+	if (nss_bridge_tx_leave_msg(b_pvt->ifnum,
+				slave) != NSS_TX_SUCCESS) {
+		ppe_port_vsi_set(NSS_BRIDGE_MGR_SWITCH_ID, port_id, b_pvt->vsi);
+		nss_bridge_mgr_trace("%px: Failed to remove port %d from bridge\n",
+				b_pvt, port_id);
+		return -1;
+	}
+
+	spin_lock(&br_mgr_ctx.lock);
+	b_pvt->lag_ports[port_id - 1] = 0;
+	spin_unlock(&br_mgr_ctx.lock);
+
+	/*
+	 * Set STP state to forwarding after bond physical port leaves bridge
+	 */
+	fal_stp_port_state_set(NSS_BRIDGE_MGR_SWITCH_ID, NSS_BRIDGE_MGR_SPANNING_TREE_ID,
+					port_id, FAL_STP_FORWARDING);
+	return 0;
+}
+
+/*
+ * nss_bridge_mgr_bond_master_join()
+ *	Add a bond interface to bridge
+ */
+static int nss_bridge_mgr_bond_master_join(struct net_device *bond_master,
+		struct nss_bridge_pvt *b_pvt)
+{
+	struct net_device *slave;
+
+	/*
+	 * bond enslave/release path is protected by rtnl lock
+	 */
+	ASSERT_RTNL();
+
+	/*
+	 * Wait for RCU QS
+	 */
+	synchronize_rcu();
+
+	/*
+	 * Join each of the bonded slaves to the VSI group
+	 */
+	for_each_netdev(&init_net, slave) {
+		if (netdev_master_upper_dev_get(slave) != bond_master) {
+			continue;
+		}
+
+		if (nss_bridge_mgr_add_bond_slave(bond_master, slave, b_pvt)) {
+			nss_bridge_mgr_warn("%px: Failed to add slave (%s) state in Bridge\n", b_pvt, slave->name);
+			goto cleanup;
+		}
+	}
+
+	/*
+	 * If already other bond devices are attached to bridge,
+	 * only increment bond_slave_num,
+	 */
+	spin_lock(&br_mgr_ctx.lock);
+	if (b_pvt->bond_slave_num) {
+		b_pvt->bond_slave_num++;
+		spin_unlock(&br_mgr_ctx.lock);
+		return NOTIFY_DONE;
+	}
+	spin_unlock(&br_mgr_ctx.lock);
+
+	/*
+	 * This is the first bond device being attached to bridge. In order to enforce Linux
+	 * bond slave selection in bridge flows involving bond interfaces, we need to disable
+	 * fdb learning on this bridge master to allow flow based bridging.
+	 */
+	if (!nss_bridge_mgr_disable_fdb_learning(b_pvt)) {
+		spin_lock(&br_mgr_ctx.lock);
+		b_pvt->bond_slave_num = 1;
+		spin_unlock(&br_mgr_ctx.lock);
+
+		return NOTIFY_DONE;
+	}
+
+cleanup:
+
+	for_each_netdev(&init_net, slave) {
+		if (netdev_master_upper_dev_get(slave) != bond_master) {
+			continue;
+		}
+
+		if (nss_bridge_mgr_del_bond_slave(bond_master, slave, b_pvt)) {
+			nss_bridge_mgr_warn("%px: Failed to remove slave (%s) from Bridge\n", b_pvt, slave->name);
+		}
+	}
+
+	return NOTIFY_BAD;
+}
+
+/*
+ * nss_bridge_mgr_bond_master_leave()
+ *	Remove a bond interface from bridge
+ */
+static int nss_bridge_mgr_bond_master_leave(struct net_device *bond_master,
+		struct nss_bridge_pvt *b_pvt)
+{
+	struct net_device *slave;
+
+	nss_bridge_mgr_assert(b_pvt->bond_slave_num == 0);
+
+	ASSERT_RTNL();
+
+	synchronize_rcu();
+
+	/*
+	 * Remove each of the bonded slaves from the VSI group
+	 */
+	for_each_netdev(&init_net, slave) {
+		if (netdev_master_upper_dev_get(slave) != bond_master) {
+			continue;
+		}
+
+		if (nss_bridge_mgr_del_bond_slave(bond_master, slave, b_pvt)) {
+			nss_bridge_mgr_warn("%px: Failed to remove slave (%s) from Bridge\n", b_pvt, slave->name);
+			goto cleanup;
+		}
+	}
+
+	/*
+	 * If more than one bond devices are attached to bridge,
+	 * only decrement the bond_slave_num
+	 */
+	spin_lock(&br_mgr_ctx.lock);
+	if (b_pvt->bond_slave_num > 1) {
+		b_pvt->bond_slave_num--;
+		spin_unlock(&br_mgr_ctx.lock);
+		return NOTIFY_DONE;
+	}
+	spin_unlock(&br_mgr_ctx.lock);
+
+	/*
+	 * The last bond interface is removed from bridge, we can switch back to FDB
+	 * learning mode.
+	 */
+	if (!nss_bridge_mgr_enable_fdb_learning(b_pvt)) {
+		spin_lock(&br_mgr_ctx.lock);
+		b_pvt->bond_slave_num = 0;
+		spin_unlock(&br_mgr_ctx.lock);
+
+		return NOTIFY_DONE;
+	}
+
+cleanup:
+	for_each_netdev(&init_net, slave) {
+		if (netdev_master_upper_dev_get(slave) != bond_master) {
+			continue;
+		}
+
+		if (nss_bridge_mgr_add_bond_slave(bond_master, slave, b_pvt)) {
+			nss_bridge_mgr_warn("%px: Failed to add slave (%s) state in Bridge\n", b_pvt, slave->name);
+		}
+	}
+
+	return NOTIFY_BAD;
+}
+
+/*
+ * nss_bridge_mgr_l2_exception_acl_enable()
+ *	Create ACL rule to enable L2 exception.
+ */
+static bool nss_bridge_mgr_l2_exception_acl_enable(void)
+{
+	sw_error_t error;
+	fal_acl_rule_t rule;
+
+	memset(&rule, 0, sizeof(rule));
+	error = fal_acl_list_creat(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID,
+				NSS_BRIDGE_MGR_ACL_LIST_PRIORITY);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("List creation failed with error = %d\n", error);
+		return false;
+	}
+
+	/*
+	 * Enable excpetion for packets with fragments.
+	 */
+	rule.rule_type = FAL_ACL_RULE_IP4;
+	rule.is_fragement_mask = 1;
+	rule.is_fragement_val = A_TRUE;
+	FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_L3_FRAGMENT);
+	FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_RDTCPU);
+
+	error = fal_acl_rule_add(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID,
+				NSS_BRIDGE_MGR_ACL_FRAG_RULE_ID, NSS_BRIDGE_MGR_ACL_RULE_NR, &rule);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("Could not add fragment acl rule, error = %d\n", error);
+		goto frag_fail;
+	}
+
+	/*
+	 * Enable excpetion for TCP FIN.
+	 */
+	memset(&rule, 0, sizeof(rule));
+
+	rule.rule_type = FAL_ACL_RULE_IP4;
+	rule.tcp_flag_val = 0x1 & 0x3f;
+	rule.tcp_flag_mask = 0x1 & 0x3f;
+	FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_TCP_FLAG);
+	FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_RDTCPU);
+
+	error = fal_acl_rule_add(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID,
+				NSS_BRIDGE_MGR_ACL_FIN_RULE_ID, NSS_BRIDGE_MGR_ACL_RULE_NR, &rule);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("Could not add TCP FIN rule, error = %d\n", error);
+		goto fin_fail;
+	}
+
+	/*
+	 * Enable excpetion for TCP SYN.
+	 */
+	memset(&rule, 0, sizeof(rule));
+
+	rule.rule_type = FAL_ACL_RULE_IP4;
+	rule.tcp_flag_val = 0x2 & 0x3f;
+	rule.tcp_flag_mask = 0x2 & 0x3f;
+	FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_TCP_FLAG);
+	FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_RDTCPU);
+
+	error = fal_acl_rule_add(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID,
+				NSS_BRIDGE_MGR_ACL_SYN_RULE_ID, NSS_BRIDGE_MGR_ACL_RULE_NR, &rule);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("Could not add TCP SYN rule, error = %d\n", error);
+		goto syn_fail;
+	}
+
+	/*
+	 * Enable excpetion for TCP RST.
+	 */
+	memset(&rule, 0, sizeof(rule));
+
+	rule.rule_type = FAL_ACL_RULE_IP4;
+	rule.tcp_flag_val = 0x4 & 0x3f;
+	rule.tcp_flag_mask = 0x4 & 0x3f;
+	FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_TCP_FLAG);
+	FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_RDTCPU);
+
+	error = fal_acl_rule_add(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID,
+				NSS_BRIDGE_MGR_ACL_RST_RULE_ID, NSS_BRIDGE_MGR_ACL_RULE_NR, &rule);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("Could not add TCP RST rule, error = %d\n", error);
+		goto rst_fail;
+	}
+
+	/*
+	 * Bind ACL list with service code
+	 */
+	error = fal_acl_list_bind(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID,
+				FAL_ACL_DIREC_IN, FAL_ACL_BIND_SERVICE_CODE, NSS_PPE_SC_VLAN_FILTER_BYPASS);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("Could not bind ACL list, error = %d\n", error);
+		goto bind_fail;
+	}
+
+	nss_bridge_mgr_info("Created ACL rule\n");
+	return true;
+
+bind_fail:
+	error = fal_acl_rule_delete(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID,
+				NSS_BRIDGE_MGR_ACL_RST_RULE_ID, NSS_BRIDGE_MGR_ACL_RULE_NR);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("TCP RST rule deletion failed, error %d\n", error);
+	}
+
+rst_fail:
+	error = fal_acl_rule_delete(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID,
+				NSS_BRIDGE_MGR_ACL_SYN_RULE_ID, NSS_BRIDGE_MGR_ACL_RULE_NR);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("TCP SYN rule deletion failed, error %d\n", error);
+	}
+
+syn_fail:
+	error = fal_acl_rule_delete(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID,
+				NSS_BRIDGE_MGR_ACL_FIN_RULE_ID, NSS_BRIDGE_MGR_ACL_RULE_NR);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("TCP FIN rule deletion failed, error %d\n", error);
+	}
+
+fin_fail:
+	error = fal_acl_rule_delete(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID,
+				NSS_BRIDGE_MGR_ACL_FRAG_RULE_ID, NSS_BRIDGE_MGR_ACL_RULE_NR);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("IP fragmentation rule deletion failed, error %d\n", error);
+	}
+
+frag_fail:
+	error = fal_acl_list_destroy(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("ACL list destroy failed, error %d\n", error);
+	}
+
+	return false;
+}
+
+/*
+ * nss_bridge_mgr_l2_exception_acl_disable()
+ *	Destroy ACL list and rule created by the driver.
+ */
+static void nss_bridge_mgr_l2_exception_acl_disable(void)
+{
+	sw_error_t error;
+
+	error = fal_acl_rule_delete(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID,
+				NSS_BRIDGE_MGR_ACL_SYN_RULE_ID, NSS_BRIDGE_MGR_ACL_RULE_NR);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("TCP SYN rule deletion failed, error %d\n", error);
+	}
+
+	error = fal_acl_rule_delete(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID,
+				NSS_BRIDGE_MGR_ACL_FIN_RULE_ID, NSS_BRIDGE_MGR_ACL_RULE_NR);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("TCP FIN rule deletion failed, error %d\n", error);
+	}
+
+	error = fal_acl_rule_delete(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID,
+				NSS_BRIDGE_MGR_ACL_RST_RULE_ID, NSS_BRIDGE_MGR_ACL_RULE_NR);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("TCP RST rule deletion failed, error %d\n", error);
+	}
+
+	error = fal_acl_rule_delete(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID,
+				NSS_BRIDGE_MGR_ACL_FRAG_RULE_ID, NSS_BRIDGE_MGR_ACL_RULE_NR);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("IP fragmentation rule deletion failed, error %d\n", error);
+	}
+
+	error = fal_acl_list_destroy(NSS_BRIDGE_MGR_ACL_DEV_ID, NSS_BRIDGE_MGR_ACL_LIST_ID);
+	if (error != SW_OK) {
+		nss_bridge_mgr_warn("ACL list destroy failed, error %d\n", error);
+	}
+}
+
+#endif
+
+/*
+ * nss_bridge_mgr_join_bridge()
+ *	Netdevice join bridge and send netdevice joining bridge message to NSS FW.
+ */
+int nss_bridge_mgr_join_bridge(struct net_device *dev, struct nss_bridge_pvt *br)
+{
+	int32_t ifnum;
+
+	ifnum = nss_cmn_get_interface_number_by_dev(dev);
+	if (ifnum < 0) {
+		nss_bridge_mgr_warn("%s: failed to find interface number\n", dev->name);
+		return -EINVAL;
+	}
+
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+	if (NSS_BRIDGE_MGR_IF_IS_TYPE_PHYSICAL(ifnum)) {
+		fal_port_t port_num = (fal_port_t)ifnum;
+
+		/*
+		 * If there is a wan interface added in bridge, create a
+		 * separate VSI for it, hence avoiding FDB based forwarding.
+		 * This is done by not sending join message to the bridge in NSS.
+		 */
+		if (br_mgr_ctx.wan_if_num == ifnum) {
+			br->wan_if_enabled = true;
+			br->wan_if_num = ifnum;
+			nss_bridge_mgr_info("if_num %d is added as WAN interface \n", ifnum);
+			return 0;
+		}
+
+		if (ppe_port_vsi_get(NSS_BRIDGE_MGR_SWITCH_ID, port_num, &br->port_vsi[port_num - 1])) {
+			nss_bridge_mgr_warn("%px: failed to save port VSI of physical interface\n", br);
+			return -EIO;
+		}
+
+		if (ppe_port_vsi_set(NSS_BRIDGE_MGR_SWITCH_ID, port_num, br->vsi)) {
+			nss_bridge_mgr_warn("%px: failed to set bridge VSI for physical interface\n", br);
+			return -EIO;
+		}
+	} else if (is_vlan_dev(dev)) {
+		struct net_device *real_dev;
+
+		/*
+		 * Find real_dev associated with the VLAN
+		 */
+		real_dev = nss_vlan_mgr_get_real_dev(dev);
+		if (real_dev && is_vlan_dev(real_dev))
+			real_dev = nss_vlan_mgr_get_real_dev(real_dev);
+		if (real_dev == NULL) {
+			nss_bridge_mgr_warn("%px: real dev for the vlan: %s in NULL\n", br, dev->name);
+			return -EINVAL;
+		}
+
+		/*
+		 * This is a valid vlan dev, add the vlan dev to bridge
+		 */
+		if (nss_vlan_mgr_join_bridge(dev, br->vsi)) {
+			nss_bridge_mgr_warn("%px: vlan device failed to join bridge\n", br);
+			return -ENODEV;
+		}
+
+		/*
+		 * dev is a bond with VLAN and VLAN is added to bridge
+		 */
+		if (netif_is_bond_master(real_dev)) {
+			if (nss_bridge_tx_join_msg(br->ifnum, dev) != NSS_TX_SUCCESS) {
+				nss_bridge_mgr_warn("%px: Interface %s join bridge failed\n", br, dev->name);
+				nss_vlan_mgr_leave_bridge(dev, br->vsi);
+				return -ENOENT;
+			}
+
+			/*
+			 * Add the bond_master to bridge.
+			 */
+			if (nss_bridge_mgr_bond_master_join(real_dev, br) != NOTIFY_DONE) {
+				nss_bridge_mgr_warn("%px: Slaves of bond interface %s join bridge failed\n", br, real_dev->name);
+				nss_bridge_tx_leave_msg(br->ifnum, dev);
+				nss_vlan_mgr_leave_bridge(dev, br->vsi);
+				return -EINVAL;
+			}
+
+			return 0;
+		}
+	}
+#endif
+
+	if (nss_bridge_tx_join_msg(br->ifnum, dev) != NSS_TX_SUCCESS) {
+		nss_bridge_mgr_warn("%px: Interface %s join bridge failed\n", br, dev->name);
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+		if (NSS_BRIDGE_MGR_IF_IS_TYPE_PHYSICAL(ifnum)) {
+			fal_port_t port_num = (fal_port_t)ifnum;
+			ppe_port_vsi_set(NSS_BRIDGE_MGR_SWITCH_ID, port_num, br->port_vsi[port_num - 1]);
+		}
+#endif
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_bridge_mgr_leave_bridge()
+ *	Netdevice leave bridge and send netdevice leaving bridge message to NSS FW.
+ */
+int nss_bridge_mgr_leave_bridge(struct net_device *dev, struct nss_bridge_pvt *br)
+{
+	int32_t ifnum;
+
+	ifnum = nss_cmn_get_interface_number_by_dev(dev);
+	if (ifnum < 0) {
+		nss_bridge_mgr_warn("%s: failed to find interface number\n", dev->name);
+		return -1;
+	}
+
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+	if (NSS_BRIDGE_MGR_IF_IS_TYPE_PHYSICAL(ifnum)) {
+		fal_port_t port_num = (fal_port_t)ifnum;
+
+		if (fal_stp_port_state_set(NSS_BRIDGE_MGR_SWITCH_ID, NSS_BRIDGE_MGR_SPANNING_TREE_ID, port_num, FAL_STP_FORWARDING)) {
+			nss_bridge_mgr_warn("%px: faied to set the STP state to forwarding\n", br);
+			return -1;
+		}
+
+		/*
+		 * If there is a wan interface added in bridge, a separate
+		 * VSI is created for it by not sending join message to NSS.
+		 * Hence a leave message should also be avaoided.
+		 */
+		if ((br->wan_if_enabled) && (br->wan_if_num == ifnum)) {
+			br->wan_if_enabled = false;
+			br->wan_if_num = -1;
+			nss_bridge_mgr_info("if_num %d is added as WAN interface\n", ifnum);
+			return 0;
+		}
+
+		if (ppe_port_vsi_set(NSS_BRIDGE_MGR_SWITCH_ID, port_num, br->port_vsi[port_num - 1])) {
+			nss_bridge_mgr_warn("%px: failed to restore port VSI of physical interface\n", br);
+			fal_stp_port_state_set(NSS_BRIDGE_MGR_SWITCH_ID, NSS_BRIDGE_MGR_SPANNING_TREE_ID, port_num, FAL_STP_DISABLED);
+			return -1;
+		}
+	} else if (is_vlan_dev(dev)) {
+		struct net_device *real_dev;
+
+		/*
+		 * Find real_dev associated with the VLAN.
+		 */
+		real_dev = nss_vlan_mgr_get_real_dev(dev);
+		if (real_dev && is_vlan_dev(real_dev))
+			real_dev = nss_vlan_mgr_get_real_dev(real_dev);
+		if (real_dev == NULL) {
+			nss_bridge_mgr_warn("%px: real dev for the vlan: %s in NULL\n", br, dev->name);
+			return -1;
+		}
+
+		/*
+		 * This is a valid vlan dev, remove the vlan dev from bridge.
+		 */
+		if (nss_vlan_mgr_leave_bridge(dev, br->vsi)) {
+			nss_bridge_mgr_warn("%px: vlan device failed to leave bridge\n", br);
+			return -1;
+		}
+
+		/*
+		 * dev is a bond with VLAN and VLAN is removed from bridge
+		 */
+		if (netif_is_bond_master(real_dev)) {
+			if (nss_bridge_tx_leave_msg(br->ifnum, dev) != NSS_TX_SUCCESS) {
+				nss_bridge_mgr_warn("%px: Interface %s leave bridge failed\n", br, dev->name);
+				nss_vlan_mgr_join_bridge(dev, br->vsi);
+				nss_bridge_tx_join_msg(br->ifnum, dev);
+				return -1;
+			}
+
+			/*
+			 * Remove the bond_master from bridge.
+			 */
+			if (nss_bridge_mgr_bond_master_leave(real_dev, br) != NOTIFY_DONE) {
+				nss_bridge_mgr_warn("%px: Slaves of bond interface %s leave bridge failed\n", br, real_dev->name);
+				nss_vlan_mgr_join_bridge(dev, br->vsi);
+				nss_bridge_tx_join_msg(br->ifnum, dev);
+				return -1;
+			}
+
+			return 0;
+		}
+	}
+#endif
+
+	if (nss_bridge_tx_leave_msg(br->ifnum, dev) != NSS_TX_SUCCESS) {
+		nss_bridge_mgr_warn("%px: Interface %s leave bridge failed\n", br, dev->name);
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+		if (is_vlan_dev(dev)) {
+			nss_vlan_mgr_join_bridge(dev, br->vsi);
+			nss_bridge_tx_join_msg(br->ifnum, dev);
+		} else if (NSS_BRIDGE_MGR_IF_IS_TYPE_PHYSICAL(ifnum)) {
+			fal_port_t port_num = (fal_port_t)ifnum;
+
+			fal_stp_port_state_set(NSS_BRIDGE_MGR_SWITCH_ID, NSS_BRIDGE_MGR_SPANNING_TREE_ID, port_num, FAL_STP_DISABLED);
+			ppe_port_vsi_set(NSS_BRIDGE_MGR_SWITCH_ID, port_num, br->vsi);
+		}
+#endif
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_bridge_mgr_unregister_br()
+ *	Unregister bridge device, dev, from bridge manager database.
+ */
+int nss_bridge_mgr_unregister_br(struct net_device *dev)
+{
+	struct nss_bridge_pvt *b_pvt;
+
+	/*
+	 * Do we have it on record?
+	 */
+	b_pvt = nss_bridge_mgr_find_instance(dev);
+	if (!b_pvt)
+		return -1;
+
+	/*
+	 * sequence of free:
+	 * 1. issue VSI unassign to NSS
+	 * 2. free VSI
+	 * 3. flush bridge FDB table
+	 * 4. unregister bridge netdevice from data plane
+	 * 5. deallocate dynamic interface associated with bridge netdevice
+	 * 6. free bridge netdevice
+	 */
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+	/*
+	 * VSI unassign function in NSS firmware only returns
+	 * CNODE_SEND_NACK in the beginning of the function when it
+	 * detects that bridge VSI is not assigned for the bridge.
+	 * Please refer to the function bridge_configure_vsi_unassign
+	 * in NSS firmware for detailed operation.
+	 */
+	if (nss_bridge_tx_vsi_unassign_msg(b_pvt->ifnum, b_pvt->vsi) != NSS_TX_SUCCESS)
+		nss_bridge_mgr_warn("%px: failed to unassign vsi\n", b_pvt);
+
+	ppe_vsi_free(NSS_BRIDGE_MGR_SWITCH_ID, b_pvt->vsi);
+
+	/*
+	 * It may happen that the same VSI is allocated again,
+	 * so there is a need to flush bridge FDB table.
+	 */
+	if (fal_fdb_entry_del_byfid(NSS_BRIDGE_MGR_SWITCH_ID, b_pvt->vsi, FAL_FDB_DEL_STATIC)) {
+		nss_bridge_mgr_warn("%px: Failed to flush FDB table for vsi:%d in PPE\n", b_pvt, b_pvt->vsi);
+	}
+#endif
+
+	nss_bridge_mgr_trace("%px: Bridge %s unregsitered. Freeing bridge di %d\n", b_pvt, dev->name, b_pvt->ifnum);
+
+	nss_bridge_unregister(b_pvt->ifnum);
+
+	if (nss_dynamic_interface_dealloc_node(b_pvt->ifnum, NSS_DYNAMIC_INTERFACE_TYPE_BRIDGE) != NSS_TX_SUCCESS) {
+		nss_bridge_mgr_warn("%px: dealloc bridge di failed\n", b_pvt);
+	}
+
+	nss_bridge_mgr_delete_instance(b_pvt);
+	return 0;
+}
+
+/*
+ * nss_bridge_mgr_register_br()
+ *	Register new bridge instance in bridge manager database.
+ */
+int nss_bridge_mgr_register_br(struct net_device *dev)
+{
+	struct nss_bridge_pvt *b_pvt;
+	int ifnum;
+	int err;
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+	uint32_t vsi_id = 0;
+#endif
+
+	nss_bridge_mgr_info("%px: Bridge register: %s\n", dev, dev->name);
+
+	b_pvt = nss_bridge_mgr_create_instance(dev);
+	if (!b_pvt)
+		return -EINVAL;
+
+	b_pvt->dev = dev;
+
+	ifnum = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_BRIDGE);
+	if (ifnum < 0) {
+		nss_bridge_mgr_warn("%px: failed to alloc bridge di\n", b_pvt);
+		nss_bridge_mgr_delete_instance(b_pvt);
+		return -EFAULT;
+	}
+
+	if (!nss_bridge_register(ifnum, dev, NULL, NULL, 0, b_pvt)) {
+		nss_bridge_mgr_warn("%px: failed to register bridge di to NSS\n", b_pvt);
+		goto fail;
+	}
+
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+	err = ppe_vsi_alloc(NSS_BRIDGE_MGR_SWITCH_ID, &vsi_id);
+	if (err) {
+		nss_bridge_mgr_warn("%px: failed to alloc bridge vsi, error = %d\n", b_pvt, err);
+		goto fail_1;
+	}
+
+	b_pvt->vsi = vsi_id;
+
+	err = nss_bridge_tx_vsi_assign_msg(ifnum, vsi_id);
+	if (err != NSS_TX_SUCCESS) {
+		nss_bridge_mgr_warn("%px: failed to assign vsi msg, error = %d\n", b_pvt, err);
+		goto fail_2;
+	}
+#endif
+
+	err = nss_bridge_tx_set_mac_addr_msg(ifnum, dev->dev_addr);
+	if (err != NSS_TX_SUCCESS) {
+		nss_bridge_mgr_warn("%px: failed to set mac_addr msg, error = %d\n", b_pvt, err);
+		goto fail_3;
+	}
+
+	err = nss_bridge_tx_set_mtu_msg(ifnum, dev->mtu);
+	if (err != NSS_TX_SUCCESS) {
+		nss_bridge_mgr_warn("%px: failed to set mtu msg, error = %d\n", b_pvt, err);
+		goto fail_3;
+	}
+
+	/*
+	 * All done, take a snapshot of the current mtu and mac addrees
+	 */
+	b_pvt->ifnum = ifnum;
+	b_pvt->mtu = dev->mtu;
+	b_pvt->wan_if_num = -1;
+	b_pvt->wan_if_enabled = false;
+	ether_addr_copy(b_pvt->dev_addr, dev->dev_addr);
+	spin_lock(&br_mgr_ctx.lock);
+	list_add(&b_pvt->list, &br_mgr_ctx.list);
+	spin_unlock(&br_mgr_ctx.lock);
+
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+	/*
+	 * Disable FDB learning if OVS is enabled for
+	 * all bridges (including Linux bridge).
+	 */
+	if (ovs_enabled) {
+		nss_bridge_mgr_disable_fdb_learning(b_pvt);
+	}
+#endif
+	return 0;
+
+fail_3:
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+	if (nss_bridge_tx_vsi_unassign_msg(ifnum, vsi_id) != NSS_TX_SUCCESS) {
+		nss_bridge_mgr_warn("%px: failed to unassign vsi\n", b_pvt);
+	}
+
+fail_2:
+	ppe_vsi_free(NSS_BRIDGE_MGR_SWITCH_ID, vsi_id);
+
+fail_1:
+#endif
+	nss_bridge_unregister(ifnum);
+
+fail:
+	if (nss_dynamic_interface_dealloc_node(ifnum, NSS_DYNAMIC_INTERFACE_TYPE_BRIDGE) != NSS_TX_SUCCESS) {
+		nss_bridge_mgr_warn("%px: failed to dealloc bridge di\n", b_pvt);
+	}
+
+	nss_bridge_mgr_delete_instance(b_pvt);
+	return -EFAULT;
+}
+
+/*
+ * nss_bridge_mgr_bond_slave_changeupper()
+ *	Add bond slave to bridge VSI
+ */
+static int nss_bridge_mgr_bond_slave_changeupper(struct netdev_notifier_changeupper_info *cu_info,
+		struct net_device *bond_slave)
+{
+	struct net_device *master;
+	struct nss_bridge_pvt *b_pvt;
+
+	/*
+	 * Checking if our bond master is part of a bridge
+	 */
+	master = netdev_master_upper_dev_get(cu_info->upper_dev);
+	if (!master)
+		return NOTIFY_DONE;
+
+	b_pvt = nss_bridge_mgr_find_instance(master);
+	if (!b_pvt) {
+		nss_bridge_mgr_warn("The bond master is not part of Bridge dev:%s\n", master->name);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Add or remove the slave based based on linking event
+	 */
+	if (cu_info->linking) {
+		if (nss_bridge_mgr_add_bond_slave(cu_info->upper_dev, bond_slave, b_pvt)) {
+			nss_bridge_mgr_warn("%px: Failed to add slave (%s) state in Bridge %s\n", b_pvt,
+					cu_info->upper_dev->name, master->name);
+		}
+	} else {
+		if (nss_bridge_mgr_del_bond_slave(cu_info->upper_dev, bond_slave, b_pvt)) {
+			nss_bridge_mgr_warn("%px: Failed to remove slave (%s) state in Bridge %s\n", b_pvt,
+					cu_info->upper_dev->name, master->name);
+		}
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_bridge_mgr_changemtu_event()
+ *	Change bridge MTU and send change bridge MTU message to NSS FW.
+ */
+static int nss_bridge_mgr_changemtu_event(struct netdev_notifier_info *info)
+{
+	struct net_device *dev = netdev_notifier_info_to_dev(info);
+	struct nss_bridge_pvt *b_pvt = nss_bridge_mgr_find_instance(dev);
+
+	if (!b_pvt)
+		return NOTIFY_DONE;
+
+	spin_lock(&br_mgr_ctx.lock);
+	if (b_pvt->mtu == dev->mtu) {
+		spin_unlock(&br_mgr_ctx.lock);
+		return NOTIFY_DONE;
+	}
+	spin_unlock(&br_mgr_ctx.lock);
+
+	nss_bridge_mgr_trace("%px: MTU changed to %d, send message to NSS\n", b_pvt, dev->mtu);
+
+	if (nss_bridge_tx_set_mtu_msg(b_pvt->ifnum, dev->mtu) != NSS_TX_SUCCESS) {
+		nss_bridge_mgr_warn("%px: Failed to send change MTU message to NSS\n", b_pvt);
+		return NOTIFY_DONE;
+	}
+
+	spin_lock(&br_mgr_ctx.lock);
+	b_pvt->mtu = dev->mtu;
+	spin_unlock(&br_mgr_ctx.lock);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_bridge_mgr_changeaddr_event()
+ *	Change bridge MAC address and send change bridge address message to NSS FW.
+ */
+static int nss_bridge_mgr_changeaddr_event(struct netdev_notifier_info *info)
+{
+	struct net_device *dev = netdev_notifier_info_to_dev(info);
+	struct nss_bridge_pvt *b_pvt = nss_bridge_mgr_find_instance(dev);
+
+	if (!b_pvt)
+		return NOTIFY_DONE;
+
+	spin_lock(&br_mgr_ctx.lock);
+	if (!memcmp(b_pvt->dev_addr, dev->dev_addr, ETH_ALEN)) {
+		spin_unlock(&br_mgr_ctx.lock);
+		nss_bridge_mgr_trace("%px: MAC are the same..skip processing it\n", b_pvt);
+		return NOTIFY_DONE;
+	}
+	spin_unlock(&br_mgr_ctx.lock);
+
+	nss_bridge_mgr_trace("%px: MAC changed to %pM, update NSS\n", b_pvt, dev->dev_addr);
+
+	if (nss_bridge_tx_set_mac_addr_msg(b_pvt->ifnum, dev->dev_addr) != NSS_TX_SUCCESS) {
+		nss_bridge_mgr_warn("%px: Failed to send change MAC address message to NSS\n", b_pvt);
+		return NOTIFY_DONE;
+	}
+
+	spin_lock(&br_mgr_ctx.lock);
+	ether_addr_copy(b_pvt->dev_addr, dev->dev_addr);
+	spin_unlock(&br_mgr_ctx.lock);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_bridge_mgr_changeupper_event()
+ *	Bridge manager handles netdevice joining or leaving bridge notification.
+ */
+static int nss_bridge_mgr_changeupper_event(struct netdev_notifier_info *info)
+{
+	struct net_device *dev = netdev_notifier_info_to_dev(info);
+	struct net_device *master_dev;
+	struct netdev_notifier_changeupper_info *cu_info;
+	struct nss_bridge_pvt *b_pvt;
+
+	cu_info = (struct netdev_notifier_changeupper_info *)info;
+
+	/*
+	 * Check if the master pointer is valid
+	 */
+	if (!cu_info->master)
+		return NOTIFY_DONE;
+
+	/*
+	 * The master is a bond that we don't need to process, but the bond might be part of a bridge.
+	 */
+	if (netif_is_bond_slave(dev))
+		return nss_bridge_mgr_bond_slave_changeupper(cu_info, dev);
+
+	master_dev = cu_info->upper_dev;
+
+	/*
+	 * Check if upper_dev is a known bridge.
+	 */
+	b_pvt = nss_bridge_mgr_find_instance(master_dev);
+	if (!b_pvt)
+		return NOTIFY_DONE;
+
+	/*
+	 * Slave device is bond master and it is added/removed to/from bridge
+	 */
+	if (netif_is_bond_master(dev)) {
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+		if (cu_info->linking)
+			return nss_bridge_mgr_bond_master_join(dev, b_pvt);
+		else
+			return nss_bridge_mgr_bond_master_leave(dev, b_pvt);
+#endif
+	}
+
+	if (cu_info->linking) {
+		nss_bridge_mgr_trace("%px: Interface %s joining bridge %s\n", b_pvt, dev->name, master_dev->name);
+		if (nss_bridge_mgr_join_bridge(dev, b_pvt)) {
+			nss_bridge_mgr_warn("%px: Interface %s failed to join bridge %s\n", b_pvt, dev->name, master_dev->name);
+		}
+
+		return NOTIFY_DONE;
+	}
+
+	nss_bridge_mgr_trace("%px: Interface %s leaving bridge %s\n", b_pvt, dev->name, master_dev->name);
+	if (nss_bridge_mgr_leave_bridge(dev, b_pvt)) {
+		nss_bridge_mgr_warn("%px: Interface %s failed to leave bridge %s\n", b_pvt, dev->name, master_dev->name);
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_bridge_mgr_register_event()
+ *	Bridge manager handles bridge registration notification.
+ */
+static int nss_bridge_mgr_register_event(struct netdev_notifier_info *info)
+{
+	nss_bridge_mgr_register_br(netdev_notifier_info_to_dev(info));
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_bridge_mgr_unregister_event()
+ *	Bridge manager handles bridge unregistration notification.
+ */
+static int nss_bridge_mgr_unregister_event(struct netdev_notifier_info *info)
+{
+	nss_bridge_mgr_unregister_br(netdev_notifier_info_to_dev(info));
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_bridge_mgr_netdevice_event()
+ *	Bridge manager handles bridge operation notifications.
+ */
+static int nss_bridge_mgr_netdevice_event(struct notifier_block *unused,
+				unsigned long event, void *ptr)
+{
+	struct netdev_notifier_info *info = (struct netdev_notifier_info *)ptr;
+
+	switch (event) {
+	case NETDEV_CHANGEUPPER:
+		return nss_bridge_mgr_changeupper_event(info);
+	case NETDEV_CHANGEADDR:
+		return nss_bridge_mgr_changeaddr_event(info);
+	case NETDEV_CHANGEMTU:
+		return nss_bridge_mgr_changemtu_event(info);
+	case NETDEV_REGISTER:
+		return nss_bridge_mgr_register_event(info);
+	case NETDEV_UNREGISTER:
+		return nss_bridge_mgr_unregister_event(info);
+	}
+
+	/*
+	 * Notify done for all the events we don't care
+	 */
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block nss_bridge_mgr_netdevice_nb __read_mostly = {
+	.notifier_call = nss_bridge_mgr_netdevice_event,
+};
+
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+/*
+ * nss_bridge_mgr_is_physical_dev()
+ *	Check if the device is on physical device.
+ */
+static bool nss_bridge_mgr_is_physical_dev(struct net_device *dev)
+{
+	struct net_device *root_dev = dev;
+	uint32_t ifnum;
+
+	if (!dev)
+		return false;
+
+	/*
+	 * Check if it is VLAN first because VLAN can be over bond interface.
+	 * However, the bond over VLAN is not supported in our driver.
+	 */
+	if (is_vlan_dev(dev)) {
+		root_dev = nss_vlan_mgr_get_real_dev(dev);
+		if (!root_dev)
+			goto error;
+
+		if (is_vlan_dev(root_dev))
+			root_dev = nss_vlan_mgr_get_real_dev(root_dev);
+
+		if (!root_dev)
+			goto error;
+	}
+
+	/*
+	 * Don't consider bond interface because FDB learning is disabled.
+	 */
+	if (netif_is_bond_master(root_dev))
+		return false;
+
+	ifnum = nss_cmn_get_interface_number_by_dev(root_dev);
+	if (!NSS_BRIDGE_MGR_IF_IS_TYPE_PHYSICAL(ifnum)) {
+		nss_bridge_mgr_warn("%px: interface %s is not physical interface\n",
+				root_dev, root_dev->name);
+		return false;
+	}
+
+	return true;
+
+error:
+	nss_bridge_mgr_warn("%px: cannot find the real device for VLAN %s\n", dev, dev->name);
+	return false;
+}
+
+/*
+ * nss_bridge_mgr_fdb_update_callback()
+ *	Get invoked when there is a FDB update.
+ */
+static int nss_bridge_mgr_fdb_update_callback(struct notifier_block *notifier,
+					      unsigned long val, void *ctx)
+{
+	struct br_fdb_event *event = (struct br_fdb_event *)ctx;
+	struct nss_bridge_pvt *b_pvt = NULL;
+	struct net_device *br_dev = NULL;
+	fal_fdb_entry_t entry;
+
+	if (!event->br)
+		return NOTIFY_DONE;
+
+	br_dev = br_fdb_bridge_dev_get_and_hold(event->br);
+	if (!br_dev) {
+		nss_bridge_mgr_warn("%px: bridge device not found\n", event->br);
+		return NOTIFY_DONE;
+	}
+
+	nss_bridge_mgr_trace("%px: MAC: %pM, original source: %s, new source: %s, bridge: %s\n",
+			event, event->addr, event->orig_dev->name, event->dev->name, br_dev->name);
+
+	/*
+	 * When a MAC address move from a physical interface to a non-physical
+	 * interface, the FDB entry in the PPE needs to be flushed.
+	 */
+	if (!nss_bridge_mgr_is_physical_dev(event->orig_dev)) {
+		nss_bridge_mgr_trace("%px: original source is not a physical interface\n", event->orig_dev);
+		dev_put(br_dev);
+		return NOTIFY_DONE;
+	}
+
+	if (nss_bridge_mgr_is_physical_dev(event->dev)) {
+		nss_bridge_mgr_trace("%px: new source is not a non-physical interface\n", event->dev);
+		dev_put(br_dev);
+		return NOTIFY_DONE;
+	}
+
+	b_pvt = nss_bridge_mgr_find_instance(br_dev);
+	dev_put(br_dev);
+	if (!b_pvt) {
+		nss_bridge_mgr_warn("%px: bridge instance not found\n", event->br);
+		return NOTIFY_DONE;
+	}
+
+	memset(&entry, 0, sizeof(entry));
+	memcpy(&entry.addr, event->addr, ETH_ALEN);
+	entry.fid = b_pvt->vsi;
+	if (SW_OK != fal_fdb_entry_del_bymac(NSS_BRIDGE_MGR_SWITCH_ID, &entry)) {
+		nss_bridge_mgr_warn("%px: FDB entry delete failed with MAC %pM and fid %d\n",
+				    b_pvt, &entry.addr, entry.fid);
+		return NOTIFY_DONE;
+	}
+	return NOTIFY_OK;
+}
+
+/*
+ * Notifier block for FDB update
+ */
+static struct notifier_block nss_bridge_mgr_fdb_update_notifier = {
+	.notifier_call = nss_bridge_mgr_fdb_update_callback,
+};
+
+/*
+ * nss_bridge_mgr_wan_inf_add_handler
+ *	Marks an interface as a WAN interface for special handling by bridge.
+ */
+static int nss_bridge_mgr_wan_intf_add_handler(struct ctl_table *table,
+						int write, void __user *buffer,
+						size_t *lenp, loff_t *ppos)
+{
+	struct net_device *dev;
+	char *dev_name;
+	char *if_name;
+	int32_t if_num;
+	int ret;
+
+	/*
+	 * Find the string, return an error if not found
+	 */
+	ret = proc_dostring(table, write, buffer, lenp, ppos);
+	if (ret || !write) {
+		return ret;
+	}
+
+	if_name = br_mgr_ctx.wan_ifname;
+	dev_name = strsep(&if_name, " ");
+	dev = dev_get_by_name(&init_net, dev_name);
+	if (!dev) {
+		nss_bridge_mgr_warn("Cannot find the net device associated with %s\n", dev_name);
+		return -ENODEV;
+	}
+
+	if_num = nss_cmn_get_interface_number_by_dev(dev);
+	if (!NSS_BRIDGE_MGR_IF_IS_TYPE_PHYSICAL(if_num)) {
+		dev_put(dev);
+		nss_bridge_mgr_warn("Only physical interfaces can be marked as WAN interface: if_num %d\n", if_num);
+		return -ENOMSG;
+	}
+
+	if (br_mgr_ctx.wan_if_num != -1) {
+		dev_put(dev);
+		nss_bridge_mgr_warn("Cannot overwrite a pre-existing wan interface\n");
+		return -ENOMSG;
+	}
+
+	br_mgr_ctx.wan_if_num = if_num;
+	dev_put(dev);
+	nss_bridge_mgr_always("For adding if_num: %d as WAN interface, do a network restart\n", if_num);
+	return ret;
+}
+
+/*
+ * nss_bridge_mgr_wan_inf_del_handler
+ *	Un-marks an interface as a WAN interface.
+ */
+static int nss_bridge_mgr_wan_intf_del_handler(struct ctl_table *table,
+						int write, void __user *buffer,
+						size_t *lenp, loff_t *ppos)
+{
+	struct net_device *dev;
+	char *dev_name;
+	char *if_name;
+	int32_t if_num;
+	int ret;
+
+	ret = proc_dostring(table, write, buffer, lenp, ppos);
+	if (ret)
+		return ret;
+
+	if (!write)
+		return ret;
+
+	if_name = br_mgr_ctx.wan_ifname;
+	dev_name = strsep(&if_name, " ");
+	dev = dev_get_by_name(&init_net, dev_name);
+	if (!dev) {
+		nss_bridge_mgr_warn("Cannot find the net device associated with %s\n", dev_name);
+		return -ENODEV;
+	}
+
+	if_num = nss_cmn_get_interface_number_by_dev(dev);
+	if (!NSS_BRIDGE_MGR_IF_IS_TYPE_PHYSICAL(if_num)) {
+		dev_put(dev);
+		nss_bridge_mgr_warn("Only physical interfaces can be marked/unmarked, if_num: %d\n", if_num);
+		return -ENOMSG;
+	}
+
+	if (br_mgr_ctx.wan_if_num != if_num) {
+		dev_put(dev);
+		nss_bridge_mgr_warn("This interface is not marked as a WAN interface\n");
+		return -ENOMSG;
+	}
+
+	br_mgr_ctx.wan_if_num = -1;
+	dev_put(dev);
+	nss_bridge_mgr_always("For deleting if_num: %d as WAN interface, do a network restart\n", if_num);
+	return ret;
+}
+
+static struct ctl_table nss_bridge_mgr_table[] = {
+	{
+		.procname	= "add_wanif",
+		.data           = &br_mgr_ctx.wan_ifname,
+		.maxlen         = sizeof(char) * IFNAMSIZ,
+		.mode           = 0644,
+		.proc_handler   = &nss_bridge_mgr_wan_intf_add_handler,
+	},
+	{
+		.procname	= "del_wanif",
+		.data           = &br_mgr_ctx.wan_ifname,
+		.maxlen         = sizeof(char) * IFNAMSIZ,
+		.mode           = 0644,
+		.proc_handler   = &nss_bridge_mgr_wan_intf_del_handler,
+	},
+	{ }
+};
+
+static struct ctl_table nss_bridge_mgr_dir[] = {
+	{
+		.procname	= "bridge_mgr",
+		.mode		= 0555,
+		.child		= nss_bridge_mgr_table,
+	},
+	{ }
+};
+
+static struct ctl_table nss_bridge_mgr_root_dir[] = {
+	{
+		.procname	= "nss",
+		.mode		= 0555,
+		.child		= nss_bridge_mgr_dir,
+	},
+	{ }
+};
+#endif
+
+/*
+ * nss_bridge_mgr_init_module()
+ *	bridge_mgr module init function
+ */
+int __init nss_bridge_mgr_init_module(void)
+{
+	/*
+	 * Monitor bridge activity only on supported platform
+	 */
+	if (!of_machine_is_compatible("qcom,ipq807x") && !of_machine_is_compatible("qcom,ipq6018") && !of_machine_is_compatible("qcom,ipq8074"))
+		return 0;
+
+	INIT_LIST_HEAD(&br_mgr_ctx.list);
+	spin_lock_init(&br_mgr_ctx.lock);
+	register_netdevice_notifier(&nss_bridge_mgr_netdevice_nb);
+	nss_bridge_mgr_info("Module (Build %s) loaded\n", NSS_CLIENT_BUILD_ID);
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+	br_mgr_ctx.wan_if_num = -1;
+	br_fdb_update_register_notify(&nss_bridge_mgr_fdb_update_notifier);
+	br_mgr_ctx.nss_bridge_mgr_header = register_sysctl_table(nss_bridge_mgr_root_dir);
+
+	/*
+	 * Enable ACL rule to enable L2 exception. This is needed if PPE Virtual ports is added to bridge.
+	 *  It is assumed that VP is using flow based bridging, hence L2 exceptions will need to be enabled on PPE bridge.
+	 */
+	if (!nss_bridge_mgr_l2_exception_acl_enable()) {
+		nss_bridge_mgr_warn("Failed to enable ACL\n");
+	}
+#endif
+#if defined (NSS_BRIDGE_MGR_OVS_ENABLE)
+	nss_bridge_mgr_ovs_init();
+#endif
+	return 0;
+}
+
+/*
+ * nss_bridge_mgr_exit_module()
+ *	bridge_mgr module exit function
+ */
+void __exit nss_bridge_mgr_exit_module(void)
+{
+	unregister_netdevice_notifier(&nss_bridge_mgr_netdevice_nb);
+	nss_bridge_mgr_info("Module unloaded\n");
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+	br_fdb_update_unregister_notify(&nss_bridge_mgr_fdb_update_notifier);
+
+	if (br_mgr_ctx.nss_bridge_mgr_header) {
+		unregister_sysctl_table(br_mgr_ctx.nss_bridge_mgr_header);
+	}
+
+	/*
+	 * Disable the PPE L2 exceptions which were enabled during module init for PPE virtual ports.
+	 */
+	nss_bridge_mgr_l2_exception_acl_disable();
+
+#endif
+#if defined (NSS_BRIDGE_MGR_OVS_ENABLE)
+	nss_bridge_mgr_ovs_exit();
+#endif
+}
+
+module_init(nss_bridge_mgr_init_module);
+module_exit(nss_bridge_mgr_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS bridge manager");
+
+module_param(ovs_enabled, bool, 0644);
+MODULE_PARM_DESC(ovs_enabled, "OVS bridge is enabled");
diff --git a/qca-nss-clients/bridge/nss_bridge_mgr_ovs.c b/qca-nss-clients/bridge/nss_bridge_mgr_ovs.c
new file mode 100644
index 0000000..b1468c7
--- /dev/null
+++ b/qca-nss-clients/bridge/nss_bridge_mgr_ovs.c
@@ -0,0 +1,200 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_bridge_mgr_ovs.c
+ *	Handle OVS bridge notifications.
+ */
+#include <linux/netdevice.h>
+#include <linux/notifier.h>
+#include <ovsmgr.h>
+#include <nss_vlan_mgr.h>
+
+#include "nss_bridge_mgr_priv.h"
+
+/*
+ * nss_bridge_mgr_ovs_handle_port_event()
+ *	Handle OVS bridge port events
+ */
+static int nss_bridge_mgr_ovs_handle_port_event(struct ovsmgr_notifiers_info *ovs_info, unsigned long event)
+{
+	struct ovsmgr_dp_port_info *port;
+	struct nss_bridge_pvt *b_pvt;
+	struct net_device *master_dev, *dev;
+	int err;
+
+	port = ovs_info->port;
+	if (!port || !port->master || !port->dev) {
+		nss_bridge_mgr_warn("%px: Invalid ovs_info\n", ovs_info);
+		return -EINVAL;
+	}
+
+	master_dev = port->master;
+	dev = port->dev;
+
+	/*
+	 * Check if upper_dev is a known bridge.
+	 */
+	b_pvt = nss_bridge_mgr_find_instance(master_dev);
+	if (!b_pvt) {
+		nss_bridge_mgr_warn("%px: Couldn't find bridge instance for master: %s\n", port, master_dev->name);
+		return -ENOENT;
+	}
+
+	/*
+	 * add port to the bridge.
+	 */
+	if (event == OVSMGR_DP_PORT_ADD) {
+		nss_bridge_mgr_trace("%px: Interface %s joining bridge %s\n", b_pvt, dev->name, master_dev->name);
+
+		err = nss_bridge_mgr_join_bridge(dev, b_pvt);
+		if (err) {
+			nss_bridge_mgr_warn("%px: Interface %s failed to join bridge %s\n", b_pvt, dev->name, master_dev->name);
+			return err;
+		}
+
+		return 0;
+	}
+
+	/*
+	 * delete port from bridge.
+	 */
+	nss_bridge_mgr_trace("%px: Interface %s leaving bridge %s\n", b_pvt, dev->name, master_dev->name);
+
+	err = nss_bridge_mgr_leave_bridge(dev, b_pvt);
+	if (err) {
+		nss_bridge_mgr_warn("%px: Interface %s failed to leave bridge %s\n", b_pvt, dev->name, master_dev->name);
+		return err;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_bridge_mgr_ovs_handle_vlan_event()
+ *	Handle VLAN events OVS bridge port
+ */
+static void nss_bridge_mgr_ovs_handle_vlan_event(struct ovsmgr_notifiers_info *ovs_info, unsigned long event)
+{
+	struct ovsmgr_dp_port_vlan_info *vlan;
+	struct nss_bridge_pvt *b_pvt;
+	struct net_device *master_dev, *dev;
+
+	vlan = ovs_info->vlan;
+	if (!vlan || !vlan->master || !vlan->dev) {
+		nss_bridge_mgr_warn("%px: Invalid ovs_info\n", ovs_info);
+		return;
+	}
+
+	master_dev = vlan->master;
+	dev = vlan->dev;
+
+	/*
+	 * Check if upper_dev is a known bridge.
+	 */
+	b_pvt = nss_bridge_mgr_find_instance(master_dev);
+	if (!b_pvt) {
+		nss_bridge_mgr_warn("%px: Couldn't find bridge instance for master: %s\n", vlan, master_dev->name);
+		return;
+	}
+
+	if (event == OVSMGR_DP_VLAN_ADD) {
+		/*
+		 * add VLAN in bridge.
+		 */
+		nss_bridge_mgr_trace("%px: VLAN = %d, add on port %s, bridge %s\n",
+				b_pvt, vlan->vh.h_vlan_TCI, dev->name, master_dev->name);
+
+		nss_vlan_mgr_add_vlan_rule(dev, b_pvt->vsi, vlan->vh.h_vlan_TCI);
+		return;
+	}
+
+	/*
+	 * delete VLAN from bridge.
+	 */
+	nss_bridge_mgr_trace("%px: VLAN = %d, delete on port %s, bridge %s\n",
+					b_pvt, vlan->vh.h_vlan_TCI, dev->name, master_dev->name);
+	nss_vlan_mgr_del_vlan_rule(dev, b_pvt->vsi, vlan->vh.h_vlan_TCI);
+}
+
+/*
+ * nss_bridge_mgr_ovs_notifier_callback()
+ *	Netdevice notifier callback to inform us of change of state of a netdevice
+ */
+static int nss_bridge_mgr_ovs_notifier_callback(struct notifier_block *nb, unsigned long event, void *data)
+{
+	struct ovsmgr_notifiers_info *ovs_info = (struct ovsmgr_notifiers_info *)data;
+
+	nss_bridge_mgr_info("OVS notifier event: %lu\n", event);
+
+	switch (event) {
+	case OVSMGR_DP_BR_ADD:
+		nss_bridge_mgr_register_br(ovs_info->dev);
+		break;
+	case OVSMGR_DP_BR_DEL:
+		nss_bridge_mgr_unregister_br(ovs_info->dev);
+		break;
+	case OVSMGR_DP_PORT_ADD:
+	case OVSMGR_DP_PORT_DEL:
+		nss_bridge_mgr_ovs_handle_port_event(ovs_info, event);
+		break;
+	case OVSMGR_DP_VLAN_ADD:
+	case OVSMGR_DP_VLAN_DEL:
+		nss_bridge_mgr_ovs_handle_vlan_event(ovs_info, event);
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * struct notifier_block nss_bridge_mgr_ovs_notifier
+ *	Registration for OVS events
+ */
+static struct notifier_block ovs_notifier __read_mostly = {
+	.notifier_call = nss_bridge_mgr_ovs_notifier_callback,
+};
+
+/*
+ * nss_bridge_mgr_is_ovs_port()
+ *	Return true if dev is an OVS port.
+ */
+int nss_bridge_mgr_is_ovs_port(struct net_device *dev)
+{
+	if (dev->priv_flags & IFF_OVS_DATAPATH) {
+		return true;
+	}
+
+	return false;
+}
+
+/*
+ * nss_bridge_mgr_ovs_exit()
+ *	Cleanup OVS bridge handlers.
+ */
+void nss_bridge_mgr_ovs_exit(void)
+{
+	ovsmgr_notifier_unregister(&ovs_notifier);
+}
+
+/*
+ * nss_bridge_mgr_exit_module()
+ *	Initialize OVS bridge handlers.
+ */
+void nss_bridge_mgr_ovs_init(void)
+{
+	ovsmgr_notifier_register(&ovs_notifier);
+}
diff --git a/qca-nss-clients/bridge/nss_bridge_mgr_priv.h b/qca-nss-clients/bridge/nss_bridge_mgr_priv.h
new file mode 100644
index 0000000..2ca505e
--- /dev/null
+++ b/qca-nss-clients/bridge/nss_bridge_mgr_priv.h
@@ -0,0 +1,131 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef _NSS_BRIDGE_MGR_PRIV_H_
+#define _NSS_BRIDGE_MGR_PRIV_H_
+
+#if (NSS_BRIDGE_MGR_DEBUG_LEVEL < 1)
+#define nss_bridge_mgr_assert(fmt, args...)
+#else
+#define nss_bridge_mgr_assert(c) BUG_ON(!(c))
+#endif /* NSS_BRIDGE_MGR_DEBUG_LEVEL */
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_bridge_mgr_always(s, ...) pr_alert(s, ##__VA_ARGS__)
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_bridge_mgr_warn(s, ...) \
+		pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_bridge_mgr_info(s, ...) \
+		pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_bridge_mgr_trace(s, ...) \
+		pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#else /* CONFIG_DYNAMIC_DEBUG */
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_BRIDGE_MGR_DEBUG_LEVEL < 2)
+#define nss_bridge_mgr_warn(s, ...)
+#else
+#define nss_bridge_mgr_warn(s, ...) \
+		pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_BRIDGE_MGR_DEBUG_LEVEL < 3)
+#define nss_bridge_mgr_info(s, ...)
+#else
+#define nss_bridge_mgr_info(s, ...) \
+		pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_BRIDGE_MGR_DEBUG_LEVEL < 4)
+#define nss_bridge_mgr_trace(s, ...)
+#else
+#define nss_bridge_mgr_trace(s, ...) \
+		pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+/*
+ * nss interface check
+ */
+#define NSS_BRIDGE_MGR_PHY_PORT_MIN 1
+#define NSS_BRIDGE_MGR_PHY_PORT_MAX 6
+#define NSS_BRIDGE_MGR_IF_IS_TYPE_PHYSICAL(if_num) \
+	(((if_num) >= NSS_BRIDGE_MGR_PHY_PORT_MIN) && \
+	((if_num) <= NSS_BRIDGE_MGR_PHY_PORT_MAX))
+
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+#define NSS_BRIDGE_MGR_SWITCH_ID	0
+#define NSS_BRIDGE_MGR_SPANNING_TREE_ID	0
+#define NSS_BRIDGE_MGR_DISABLE_PPE_EXCEPTION	0
+#define NSS_BRIDGE_MGR_ENABLE_PPE_EXCEPTION	1
+
+#define NSS_BRIDGE_MGR_ACL_DEV_ID 0
+#define NSS_BRIDGE_MGR_ACL_LIST_ID 61
+#define NSS_BRIDGE_MGR_ACL_LIST_PRIORITY 0
+#define NSS_BRIDGE_MGR_ACL_RULE_NR 1
+#define NSS_BRIDGE_MGR_ACL_FRAG_RULE_ID 0
+#define NSS_BRIDGE_MGR_ACL_FIN_RULE_ID 1
+#define NSS_BRIDGE_MGR_ACL_SYN_RULE_ID 2
+#define NSS_BRIDGE_MGR_ACL_RST_RULE_ID 3
+
+#endif
+
+/*
+ * bridge manager context structure
+ */
+struct nss_bridge_mgr_context {
+	struct list_head list;		/* List of bridge instance */
+	spinlock_t lock;		/* Lock to protect bridge instance */
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+	int32_t wan_if_num;		/* WAN interface number */
+	char wan_ifname[IFNAMSIZ];	/* WAN interface name */
+	struct ctl_table_header *nss_bridge_mgr_header;	/* bridge sysctl */
+#endif
+};
+
+/*
+ * bridge manager private structure
+ */
+struct nss_bridge_pvt {
+	struct list_head list;			/* List of bridge instance */
+	struct net_device *dev;			/* Bridge netdevice */
+	uint32_t ifnum;				/* Dynamic interface for bridge */
+#if defined(NSS_BRIDGE_MGR_PPE_SUPPORT)
+	uint32_t vsi;				/* VSI set for bridge */
+	uint32_t port_vsi[NSS_BRIDGE_MGR_PHY_PORT_MAX];	/* port VSI set for physical interfaces	*/
+	uint32_t lag_ports[NSS_BRIDGE_MGR_PHY_PORT_MAX];	/* List of slave ports in LAG */
+	int bond_slave_num;			/* Total number of bond devices added into
+						   bridge device */
+	bool wan_if_enabled;			/* Is WAN interface enabled? */
+	int32_t wan_if_num;			/* WAN interface number, if enabled */
+#endif
+	uint32_t mtu;				/* MTU for bridge */
+	uint8_t dev_addr[ETH_ALEN];		/* MAC address for bridge */
+};
+
+int nss_bridge_mgr_register_br(struct net_device *dev);
+int nss_bridge_mgr_unregister_br(struct net_device *dev);
+struct nss_bridge_pvt *nss_bridge_mgr_find_instance(struct net_device *dev);
+int nss_bridge_mgr_join_bridge(struct net_device *dev, struct nss_bridge_pvt *br);
+int nss_bridge_mgr_leave_bridge(struct net_device *dev, struct nss_bridge_pvt *br);
+void nss_bridge_mgr_ovs_init(void);
+void nss_bridge_mgr_ovs_exit(void);
+
+#endif
diff --git a/qca-nss-clients/build.sh b/qca-nss-clients/build.sh
new file mode 100755
index 0000000..88fb760
--- /dev/null
+++ b/qca-nss-clients/build.sh
@@ -0,0 +1,116 @@
+#!/bin/bash
+
+set -e
+set -o errtrace
+trap 'echo Fatal error: script $0 aborting at line $LINENO, command \"$BASH_COMMAND\" returned $?; exit 1' ERR
+
+PRODUCT_LIST="sirocco"
+
+NUM_JOBS=$(grep -c processor /proc/cpuinfo)
+
+MODULE_NAME="qca-nss-clients"
+###################################################
+# Setup build toollchain
+###################################################
+sdk_top_dir=$(readlink -e $(dirname $0)/..)
+TOP_DIR=$(readlink -e ${sdk_top_dir}/..)
+
+#export ARCH and build related envs.
+source ${TOP_DIR}/sdk/build_scripts/setup_env.sh
+
+kernel_path=$(readlink -e ${sdk_top_dir}/../kernel)
+qca_ssdk_include_path=$(readlink -e ${sdk_top_dir}/qca-ssdk/include)
+qca_ssdk_common_path=$(readlink -e ${sdk_top_dir}/qca-ssdk/include/common)
+qca_ssdk_sal_path=$(readlink -e ${sdk_top_dir}/qca-ssdk/include/sal/os)
+qca_ssdk_sal_linux_path=$(readlink -e ${sdk_top_dir}/qca-ssdk/include/sal/os/linux)
+qca_nss_drv_export_path=$(readlink -e ${sdk_top_dir}/qca-nss-drv/exports)
+qca_nss_drv_dependency=$(readlink -e ${sdk_top_dir}/qca-nss-drv)
+soc_type=ipq50xx
+
+export SoC=${soc_type}
+
+dtlsmgr_ver="v2.0"
+ipsecmgr_ver="v2.0"
+
+extra_cflags="-I${qca_nss_drv_export_path} -I${qca_ssdk_include_path} -I${qca_ssdk_common_path} -I${qca_ssdk_sal_path} -I${qca_ssdk_sal_linux_path}"
+
+make_modules="wifi-meshmgr"
+
+make_opts=""
+for module in ${make_modules}; do
+  make_opts="${make_opts} ${module}=y"
+done
+
+##################################################
+# Build Kernel Module
+##################################################
+function BuildKModule() {
+    # make kernel module
+    echo "Build ${MODULE_NAME}"
+    ${CROSS_MAKE} -C ${kernel_path} ${make_opts} M=${sdk_top_dir}/${MODULE_NAME} SoC=${soc_type} EXTRA_CFLAGS=${extra_cflags} DTLSMGR_DIR=${dtlsmgr_ver} IPSECMGR_DIR=${ipsecmgr_ver} KBUILD_EXTRA_SYMBOLS=${qca_nss_drv_dependency}/Module.symvers V=1
+}
+
+##################################################
+# Build & Install
+##################################################
+function BuildAndInstall() {
+    local product=$1
+    local eureka_src_path=$(readlink -e $2)
+    if [ -z ${eureka_src_path} ]; then
+      echo "eureka_src_path doesn't exist"
+      exit 1
+    fi
+
+    # clean previous build
+    find . -name "*.o" -delete
+    find . -name "*.cmd" -delete
+    find . -name "*.ko" -delete
+    find . -name "*.mod.*" -delete
+    find . -name "*.mod" -delete
+    find . -name Module.symvers -delete
+
+    # build module
+    BuildKModule
+
+    # install module
+    echo "Install ${MODULE_NAME} modules: ${make_modules}"
+    local module_target_dir="$(GetModulePath ${eureka_src_path} ${product})"
+    mkdir -p ${module_target_dir}
+    cp -f wifi_meshmgr/qca-nss-wifi-meshmgr.ko ${module_target_dir}/.
+}
+
+function Usage() {
+    cat << EOF
+Usage:
+    $0 <product> <eureka_src_path>
+    Valid products: ${PRODUCT_LIST}
+EOF
+}
+
+function IsProductValid() {
+  local product
+  local ret=1
+
+  for product in ${PRODUCT_LIST}; do
+    if [ "${product}" == "$1" ]; then
+      ret=0
+      break
+    fi
+  done
+
+  return ${ret}
+}
+
+#########################
+####### Main Entry ######
+#########################
+if (( $# < 2 )); then
+  Usage
+else
+  if IsProductValid $1; then
+    BuildAndInstall $1 $2
+  else
+    echo "$1 is a invalid product"
+    Usage
+  fi
+fi
diff --git a/qca-nss-clients/capwapmgr/Makefile b/qca-nss-clients/capwapmgr/Makefile
new file mode 100644
index 0000000..0e1450c
--- /dev/null
+++ b/qca-nss-clients/capwapmgr/Makefile
@@ -0,0 +1,17 @@
+ccflags-y := -I$(obj)/../exports -I$(obj)/..  -I$(obj)/nss_hal/include
+ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)"
+
+#
+# If you want only one netdev for all the CAPWAP tunnels, then
+# set NSS_CAPWAPMGR_ONE_NETDEV.
+#     ccflags-y += -DNSS_CAPWAPMGR_ONE_NETDEV
+#
+# If you want one netdevice per-CAPWAP tunnel, then don't set
+# NSS_CAPWAPMGR_ONE_NETDEV.
+#
+obj-m += qca-nss-capwapmgr.o
+qca-nss-capwapmgr-objs := nss_capwapmgr.o
+ccflags-y += -DNSS_CAPWAPMGR_DEBUG_LEVEL=6
+
+ccflags-y += $(NSS_CCFLAGS) -DNSS_DEBUG_LEVEL=0 -DNSS_PKT_STATS_ENABLED=0
+ccflags-y += -Wall -Werror
diff --git a/qca-nss-clients/capwapmgr/nss_capwapmgr.c b/qca-nss-clients/capwapmgr/nss_capwapmgr.c
new file mode 100644
index 0000000..62068b6
--- /dev/null
+++ b/qca-nss-clients/capwapmgr/nss_capwapmgr.c
@@ -0,0 +1,3484 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_capwapmgr.c
+ *	NSS to HLOS CAPWAP manager
+ */
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/of.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <net/ipv6.h>
+#include <linux/version.h>
+
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3,9,0))
+#include <net/ipip.h>
+#else
+#include <net/ip_tunnels.h>
+#endif
+
+#include <linux/if_arp.h>
+#include <linux/etherdevice.h>
+#include <nss_api_if.h>
+#include <linux/in.h>
+#include <nss_cmn.h>
+#include <nss_capwap.h>
+#include <nss_capwapmgr.h>
+#include <nss_capwap_user.h>
+#include <fal/fal_qos.h>
+#include <fal/fal_acl.h>
+
+#define NSS_CAPWAPMGR_NETDEV_NAME	"nsscapwap"
+
+/*
+ * This file is responsible for interacting with qca-nss-drv's
+ * CAPWAP API to manage CAPWAP tunnels.
+ *
+ * This driver also exposes few APIs which can be used by
+ * another module to perform operations on CAPWAP tunnels. However, we create
+ * one netdevice for all the CAPWAP tunnels which is done at the module's
+ * init time if NSS_CAPWAPMGR_ONE_NETDEV is set in the Makefile.
+ *
+ * If your requirement is to create one netdevice per-CAPWAP tunnel, then
+ * netdevice needs to be created before CAPWAP tunnel create. Netdevice are
+ * created using nss_capwapmgr_netdev_create() API.
+ *
+ */
+
+/*
+ * NSS capwap mgr macros
+ */
+#define NSS_CAPWAPMGR_NORMAL_FRAME_MTU 1500
+
+/*
+ * Ethernet types.
+ */
+#define NSS_CAPWAPMGR_ETH_TYPE_MASK 0xFFFF
+#define NSS_CAPWAPMGR_ETH_TYPE_TRUSTSEC 0x8909
+#define NSS_CAPWAPMGR_ETH_TYPE_IPV4 ETH_P_IP
+#define NSS_CAPWAPMGR_ETH_TYPE_IPV6 ETH_P_IPV6
+#define NSS_CAPWAPMGR_DSCP_MAX 64
+
+/*
+ * ACL specific parameters.
+ */
+#define NSS_CAPWAPMGR_ETH_HDR_OFFSET 6
+#define NSS_CAPWAPMGR_IPV4_OFFSET 8
+#define NSS_CAPWAPMGR_DSCP_MASK_IPV4_SHIFT 2
+#define NSS_CAPWAPMGR_DSCP_MASK_IPV6_SHIFT 6
+#define NSS_CAPWAPMGR_DEV_ID 0
+#define NSS_CAPWAPMGR_GROUP_ID 0
+#define NSS_CAPWAPMGR_RULE_NR 1
+
+/*
+ * ACL rule bind bitmap for all physical ports (1 through 6)
+ */
+#define NSS_CAPWAPMGR_BIND_BITMAP 0x7E
+
+/*
+ * We need 4 ACL rules - 2 rules for each v4 and v6 classification.
+ */
+#define NSS_CAPWAPMGR_ACL_RULES_PER_LIST 4
+
+/*
+ * We currently have list-id 60 reserved for this purpose.
+ * TODO: Find a better approach to reserve list-id.
+ */
+#define NSS_CAPWAPMGR_ACL_LIST_START 60
+#define NSS_CAPWAPMGR_ACL_LIST_CNT 1
+
+#define NSS_CAPWAPMGR_NORMAL_FRAME_MTU 1500
+
+#if (NSS_CAPWAPMGR_DEBUG_LEVEL < 1)
+#define nss_capwapmgr_assert(fmt, args...)
+#else
+#define nss_capwapmgr_assert(c) if (!(c)) { BUG_ON(!(c)); }
+#endif /* NSS_CAPWAPMGR_DEBUG_LEVEL */
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_capwapmgr_warn(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_capwapmgr_info(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_capwapmgr_trace(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#else /* CONFIG_DYNAMIC_DEBUG */
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_CAPWAPMGR_DEBUG_LEVEL < 2)
+#define nss_capwapmgr_warn(s, ...)
+#else
+#define nss_capwapmgr_warn(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_CAPWAPMGR_DEBUG_LEVEL < 3)
+#define nss_capwapmgr_info(s, ...)
+#else
+#define nss_capwapmgr_info(s, ...)   pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_CAPWAPMGR_DEBUG_LEVEL < 4)
+#define nss_capwapmgr_trace(s, ...)
+#else
+#define nss_capwapmgr_trace(s, ...)  pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+/*
+ * nss_capwapmgr_ip_response
+ *	Response structure for IPv4 and IPv6 messages
+ */
+static struct nss_capwapmgr_ip_response {
+	struct semaphore sem;
+	wait_queue_head_t wq;
+	enum nss_cmn_response response;
+	bool cond;
+} ip_response;
+
+/*
+ * nss_capwapmgr_acl
+ *	Object containing rule related info.
+ */
+struct nss_capwapmgr_acl {
+	bool in_use;			/* Set when rule is in use. */
+	uint8_t uid;			/* Unique ID for this rule object. */
+	uint8_t list_id;		/* List on which this rule resides. */
+	uint8_t rule_id;		/* Rule-id of this rule. */
+	uint8_t dscp_value;		/* DSCP value */
+	uint8_t dscp_mask;		/* DSCP mask */
+};
+
+/*
+ * nss_capwapmgr_acl_list
+ */
+struct nss_capwapmgr_acl_list {
+	struct nss_capwapmgr_acl rule[NSS_CAPWAPMGR_ACL_RULES_PER_LIST];
+					/* Rules on this ACL list. */
+};
+
+/*
+ * nss_capwapmgr_global
+ *	Global structure for capwapmgr.
+ */
+static struct nss_capwapmgr_global {
+	uint32_t count;				/* Counter for driver queue selection. */
+	struct nss_capwap_tunnel_stats tunneld;	/* What tunnels that don't exist any more. */
+	struct nss_capwapmgr_acl_list acl_list[NSS_CAPWAPMGR_ACL_LIST_CNT];
+						/* Set when ACL rule is in use. */
+} global;
+
+static void nss_capwapmgr_receive_pkt(struct net_device *dev, struct sk_buff *skb, struct napi_struct *napi);
+
+#if defined(NSS_CAPWAPMGR_ONE_NETDEV)
+/*
+ * If you want only one netdev for all the tunnels. If you don't want
+ * to create one netdev for all the tunnels, then netdev must be
+ * created using nss_capwapmgr_netdev_create() before every tunnel create
+ * operation.
+ */
+static struct net_device *nss_capwapmgr_ndev = NULL;
+#endif
+
+/*
+ * nss_capwapmgr_open()
+ *	Netdev's open call.
+ */
+static int nss_capwapmgr_open(struct net_device *dev)
+{
+	netif_start_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_capwapmgr_close()
+ *	Netdev's close call.
+ */
+static int nss_capwapmgr_close(struct net_device *dev)
+{
+	netif_stop_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_capwapmgr_decongestion_callback()
+ *	Wakeup netif queue if we were stopped by start_xmit
+ */
+static void nss_capwapmgr_decongestion_callback(void *arg)
+{
+	struct net_device *dev = arg;
+
+	if (netif_queue_stopped(dev)) {
+		netif_wake_queue(dev);
+	}
+}
+
+/*
+ * nss_capwapmgr_start_xmit()
+ *	Transmit's skb to NSS FW over CAPWAP if_num_inner.
+ *
+ * Please make sure to leave headroom of NSS_CAPWAP_HEADROOM with every
+ * packet so that NSS can encap eth,vlan,ip,udp,capwap headers.
+ * Also, skb->len must include size of metaheader. Essentially skb->len is
+ * size of CAPWAP Payload (including wireless info sections) and metaheader.
+ */
+static netdev_tx_t nss_capwapmgr_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct net_device_stats *stats = &dev->stats;
+	struct nss_capwapmgr_priv *priv;
+	struct nss_capwap_metaheader *pre;
+	uint32_t if_num_inner;
+	nss_tx_status_t status;
+
+	priv = netdev_priv(dev);
+	pre = (struct nss_capwap_metaheader *)skb->data;
+
+	if (unlikely(pre->tunnel_id > NSS_CAPWAPMGR_MAX_TUNNELS)) {
+		nss_capwapmgr_warn("%px: (CAPWAP packet) tunnel-id invalid: %d\n", dev, pre->tunnel_id);
+		kfree_skb(skb);
+		stats->tx_dropped++;
+		return NETDEV_TX_OK;
+	}
+
+	if_num_inner = priv->tunnel[pre->tunnel_id].if_num_inner;
+	if (unlikely(if_num_inner == -1)) {
+		nss_capwapmgr_warn("%px: (CAPWAP packet) if_num_inner in the tunnel not set pre->tunnel_id %d\n", dev,
+				pre->tunnel_id);
+		kfree_skb(skb);
+		stats->tx_dropped++;
+		return NETDEV_TX_OK;
+	}
+
+	/*
+	 * We use the lowest bit in the inner flow_id to determine which Tx ring
+	 * to use (drv uses queue mapping to select Tx ring).
+	 *
+	 * This ring distribution will in turn get used in NSS firmware
+	 * for better thread distribution of encap operation.
+	 */
+	skb_set_queue_mapping(skb, pre->flow_id & 0x1);
+
+	status = nss_capwap_tx_buf(priv->nss_ctx, skb, if_num_inner);
+	if (unlikely(status != NSS_TX_SUCCESS)) {
+		if (status == NSS_TX_FAILURE_QUEUE) {
+			nss_capwapmgr_warn("%px: netdev :%px queue is full", dev, dev);
+			if (!netif_queue_stopped(dev)) {
+				netif_stop_queue(dev);
+			}
+		}
+
+		return NETDEV_TX_BUSY;
+	}
+
+	return NETDEV_TX_OK;
+}
+
+/*
+ * nss_capwapmgr_fill_up_stats()
+ *	Fills up stats in netdev's stats.
+ */
+static void nss_capwapmgr_fill_up_stats(struct rtnl_link_stats64 *stats, struct nss_capwap_tunnel_stats *tstats)
+{
+	stats->rx_packets += tstats->pnode_stats.rx_packets;
+	stats->rx_dropped += tstats->pnode_stats.rx_dropped;
+
+	/* rx_fifo_errors will appear as rx overruns in ifconfig */
+	stats->rx_fifo_errors += (tstats->rx_n2h_drops + tstats->rx_n2h_queue_full_drops);
+	stats->rx_errors += (tstats->rx_mem_failure_drops + tstats->rx_oversize_drops + tstats->rx_frag_timeout_drops);
+	stats->rx_bytes += tstats->pnode_stats.rx_bytes;
+
+	/* tx_fifo_errors  will appear as tx overruns in ifconfig */
+	stats->tx_fifo_errors += tstats->tx_queue_full_drops;
+	stats->tx_errors += tstats->tx_mem_failure_drops;
+	stats->tx_bytes += tstats->pnode_stats.tx_bytes;
+
+	stats->tx_dropped += (tstats->tx_dropped_sg_ref + tstats->tx_dropped_ver_mis + tstats->tx_dropped_hroom
+			 + tstats->tx_dropped_dtls + tstats->tx_dropped_nwireless);
+	stats->tx_packets += tstats->pnode_stats.tx_packets;
+}
+
+/*
+ * nss_capwapmgr_get_tunnel_stats()
+ *	Netdev get stats function to get tunnel stats
+ */
+static struct rtnl_link_stats64 *nss_capwapmgr_get_tunnel_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	struct nss_capwap_tunnel_stats tstats;
+	int i;
+
+	if (!stats) {
+		nss_capwapmgr_warn("%px: invalid rtnl structure\n", dev);
+		return stats;
+	}
+
+	/*
+	 * Netdev seems to be incrementing rx_dropped because we don't give IP header.
+	 * So reset it as it's of no use for us.
+	 */
+	atomic_long_set(&dev->rx_dropped, 0);
+
+	memset(stats, 0, sizeof (struct rtnl_link_stats64));
+	nss_capwapmgr_fill_up_stats(stats, &global.tunneld);
+
+	for (i = NSS_DYNAMIC_IF_START; i <= (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES); i++) {
+		if (nss_capwap_get_stats(i, &tstats) == false) {
+			continue;
+		}
+
+		nss_capwapmgr_fill_up_stats(stats, &tstats);
+	}
+
+	return stats;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0))
+/*
+ * nss_capwapmgr_dev_tunnel_stats()
+ *	Netdev ops function to retrieve stats for kernel version < 4.6
+ */
+static struct rtnl_link_stats64 *nss_capwapmgr_dev_tunnel_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	return nss_capwapmgr_get_tunnel_stats(dev, stats);
+}
+#else
+/*
+ * nss_capwapmgr_dev_tunnel_stats()
+ *	Netdev ops function to retrieve stats for kernel version > 4.6
+ */
+static void nss_capwapmgr_dev_tunnel_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	nss_capwapmgr_get_tunnel_stats(dev, stats);
+}
+#endif
+
+/*
+ * nss_capwapmgr_netdev_ops
+ *	Netdev operations.
+ */
+static const struct net_device_ops nss_capwapmgr_netdev_ops = {
+	.ndo_open		= nss_capwapmgr_open,
+	.ndo_stop		= nss_capwapmgr_close,
+	.ndo_start_xmit		= nss_capwapmgr_start_xmit,
+	.ndo_set_mac_address	= eth_mac_addr,
+	.ndo_change_mtu		= eth_change_mtu,
+	.ndo_get_stats64	= nss_capwapmgr_dev_tunnel_stats,
+};
+
+/*
+ * nss_capwapmgr_dummpy_netdev_setup()
+ *	Netdev setup function.
+ */
+static void nss_capwapmgr_dummpy_netdev_setup(struct net_device *dev)
+{
+	dev->addr_len = ETH_ALEN;
+	dev->mtu = ETH_DATA_LEN;
+	dev->needed_headroom = NSS_CAPWAP_HEADROOM;
+	dev->needed_tailroom = 4;
+	dev->type = ARPHRD_VOID;
+	dev->ethtool_ops = NULL;
+	dev->header_ops = NULL;
+	dev->netdev_ops = &nss_capwapmgr_netdev_ops;
+
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 11, 8))
+	dev->destructor = NULL;
+#else
+	dev->priv_destructor = NULL;
+#endif
+	memcpy(dev->dev_addr, "\x00\x00\x00\x00\x00\x00", dev->addr_len);
+	memset(dev->broadcast, 0xff, dev->addr_len);
+	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
+}
+
+/*
+ * nss_capwapmgr_msg_event_receive()
+ *	CAPWAP message callback for responses to commands sent to NSS FW
+ *
+ * This is command hanlder for all the messages since all we do is wake-up
+ * the caller who is sending message to NSS FW.
+ */
+static void nss_capwapmgr_msg_event_receive(void *app_data, struct nss_capwap_msg *nim)
+{
+	struct net_device *dev = app_data;
+	struct nss_cmn_msg *ncm = (struct nss_cmn_msg *)nim;
+	struct nss_capwapmgr_response *r;
+	struct nss_capwapmgr_priv *priv;
+	uint32_t if_num;
+
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		return;
+	}
+
+	/*
+	 * Since all CAPWAP messages are sync in nature we need to wake-up caller.
+	 */
+	if_num = ncm->interface - NSS_DYNAMIC_IF_START;
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+	r = &priv->resp[if_num];
+
+	/*
+	 * If somebody is waiting...
+	 */
+	if (atomic_read(&r->seq) != 0) {
+		if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+			r->error = ncm->error;
+		}
+
+		r->response = ncm->response;
+		atomic_dec(&r->seq);
+		wake_up(&r->wq);
+	}
+
+	dev_put(dev);
+}
+/*
+ * nss_capwapmgr_ip_common_handler()
+ *	Common Callback handler for IPv4 and IPv6 messages
+ */
+static void nss_capwapmgr_ip_common_handler(struct nss_cmn_msg *ncm)
+{
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		return;
+	}
+
+	ip_response.response = ncm->response;
+	ip_response.cond = 0;
+	wake_up(&ip_response.wq);
+}
+
+/*
+ * nss_capwapmgr_ipv4_handler()
+ *	Callback handler for IPv4 messages
+ */
+static void nss_capwapmgr_ipv4_handler(void *app_data, struct nss_ipv4_msg *nim)
+{
+	nss_capwapmgr_ip_common_handler(&nim->cm);
+}
+
+/*
+ * nss_capwapmgr_ipv6_handler()
+ *	Callback handler for IPv4 messages
+ */
+static void nss_capwapmgr_ipv6_handler(void *app_data, struct nss_ipv6_msg *nim)
+{
+	nss_capwapmgr_ip_common_handler(&nim->cm);
+}
+
+/*
+ * nss_capwap_remap_error()
+ *	Remaps NSS FW response error to nss_capwapmgr_status_t
+ */
+static nss_capwapmgr_status_t nss_capwap_remap_error(nss_capwap_msg_response_t error)
+{
+	nss_capwapmgr_status_t status;
+
+	switch (error) {
+	case NSS_CAPWAP_ERROR_MSG_INVALID_REASSEMBLY_TIMEOUT:
+		status = NSS_CAPWAPMGR_FAILURE_INVALID_REASSEMBLY_TIMEOUT;
+		break;
+	case NSS_CAPWAP_ERROR_MSG_INVALID_PATH_MTU:
+		status = NSS_CAPWAPMGR_FAILURE_INVALID_PATH_MTU;
+		break;
+	case NSS_CAPWAP_ERROR_MSG_INVALID_MAX_FRAGMENT:
+		status = NSS_CAPWAPMGR_FAILURE_INVALID_MAX_FRAGMENT;
+		break;
+	case NSS_CAPWAP_ERROR_MSG_INVALID_BUFFER_SIZE:
+		status = NSS_CAPWAPMGR_FAILURE_INVALID_BUFFER_SIZE;
+		break;
+	case NSS_CAPWAP_ERROR_MSG_INVALID_L3_PROTO:
+		status = NSS_CAPWAPMGR_FAILURE_INVALID_L3_PROTO;
+		break;
+	case NSS_CAPWAP_ERROR_MSG_INVALID_UDP_PROTO:
+		status = NSS_CAPWAPMGR_FAILURE_INVALID_UDP_PROTO;
+		break;
+	case NSS_CAPWAP_ERROR_MSG_INVALID_VERSION:
+		status = NSS_CAPWAPMGR_FAILURE_INVALID_VERSION;
+		break;
+	case NSS_CAPWAP_ERROR_MSG_TUNNEL_DISABLED:
+		status = NSS_CAPWAPMGR_FAILURE_TUNNEL_DISABLED;
+		break;
+	case NSS_CAPWAP_ERROR_MSG_TUNNEL_ENABLED:
+		status = NSS_CAPWAPMGR_FAILURE_TUNNEL_ENABLED;
+		break;
+	case NSS_CAPWAP_ERROR_MSG_TUNNEL_NOT_CFG:
+		status = NSS_CAPWAPMGR_FAILURE_TUNNEL_NOT_CFG;
+		break;
+	case NSS_CAPWAP_ERROR_MSG_INVALID_IP_NODE:
+		status = NSS_CAPWAPMGR_FAILURE_INVALID_IP_NODE;
+		break;
+	case NSS_CAPWAP_ERROR_MSG_INVALID_TYPE_FLAG:
+		status = NSS_CAPWAPMGR_FAILURE_INVALID_TYPE_FLAG;
+		break;
+	case NSS_CAPWAP_ERROR_MSG_INVALID_DTLS_CFG:
+		status = NSS_CAPWAPMGR_FAILURE_INVALID_DTLS_CFG;
+		break;
+	default:
+		status = NSS_CAPWAPMGR_FAILURE;
+	}
+
+	return status;
+}
+
+/*
+ * nss_capwapmgr_verify_tunnel_param()
+ *	Common function to verify tunnel_id and returns pointer to tunnel.
+ *
+ * The caller of the function should hold reference to the net device before calling.
+ */
+static struct nss_capwapmgr_tunnel *nss_capwapmgr_verify_tunnel_param(struct net_device *dev, uint8_t tunnel_id)
+{
+	struct nss_capwapmgr_priv *priv;
+	struct nss_capwapmgr_tunnel *t;
+
+	if (!dev) {
+		nss_capwapmgr_warn("Invalid net_device\n");
+		return NULL;
+	}
+
+	if (tunnel_id > NSS_CAPWAPMGR_MAX_TUNNELS) {
+		nss_capwapmgr_warn("%px: tunnel_id: %d out of range (%d)\n", dev, tunnel_id, NSS_CAPWAPMGR_MAX_TUNNELS);
+		return NULL;
+	}
+
+	priv = netdev_priv(dev);
+	t = &priv->tunnel[tunnel_id];
+	if ( (t->if_num_inner == -1) || (t->if_num_outer == -1) ) {
+		return NULL;
+	}
+
+	return t;
+}
+
+/*
+ * nss_capwapmgr_netdev_create()
+ *	API to create a CAPWAP netdev
+ */
+struct net_device *nss_capwapmgr_netdev_create()
+{
+	struct nss_capwapmgr_priv *priv;
+	struct nss_capwapmgr_response *r;
+	struct net_device *ndev;
+	int i;
+	int err;
+
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 16, 0))
+	ndev = alloc_netdev(sizeof(struct nss_capwapmgr_priv),
+					"nsscapwap%d", nss_capwapmgr_dummpy_netdev_setup);
+#else
+	ndev = alloc_netdev(sizeof(struct nss_capwapmgr_priv),
+					"nsscapwap%d", NET_NAME_ENUM, nss_capwapmgr_dummpy_netdev_setup);
+#endif
+	if (!ndev) {
+		nss_capwapmgr_warn("Error allocating netdev\n");
+		return NULL;
+	}
+
+	err = register_netdev(ndev);
+	if (err) {
+		nss_capwapmgr_warn("register_netdev() fail with error :%d\n", err);
+		free_netdev(ndev);
+		return NULL;
+	}
+
+	priv = netdev_priv(ndev);
+	priv->nss_ctx = nss_capwap_get_ctx();
+	priv->tunnel = kmalloc(sizeof(struct nss_capwapmgr_tunnel) * NSS_CAPWAPMGR_MAX_TUNNELS, GFP_ATOMIC);
+	if (!priv->tunnel) {
+		nss_capwapmgr_warn("%px: failed to allocate tunnel memory\n", ndev);
+		goto fail1;
+	}
+	memset(priv->tunnel, 0, sizeof(struct nss_capwapmgr_tunnel) * NSS_CAPWAPMGR_MAX_TUNNELS);
+	for (i = 0; i < NSS_CAPWAPMGR_MAX_TUNNELS; i++) {
+		priv->tunnel[i].if_num_inner = -1;
+		priv->tunnel[i].if_num_outer = -1;
+	}
+
+	priv->resp = kmalloc(sizeof(struct nss_capwapmgr_response) * NSS_MAX_DYNAMIC_INTERFACES, GFP_ATOMIC);
+	if (!priv->resp) {
+		nss_capwapmgr_warn("%px: failed to allocate tunnel response memory\n", ndev);
+		goto fail2;
+	}
+	for (i = 0; i < NSS_MAX_DYNAMIC_INTERFACES; i++) {
+		r = &priv->resp[i];
+		init_waitqueue_head(&r->wq);
+
+		/*
+		 * CAPWAP interface is limited to one command per-tunnel.
+		 */
+		sema_init(&r->sem, 1);
+	}
+
+	priv->if_num_to_tunnel_id = kmalloc(sizeof(uint8_t) * NSS_MAX_NET_INTERFACES, GFP_ATOMIC);
+	if (!priv->if_num_to_tunnel_id) {
+		nss_capwapmgr_warn("%px: failed to allocate if_num to tunnel_id memory\n", ndev);
+		goto fail3;
+	}
+	memset(priv->if_num_to_tunnel_id, 0, sizeof(uint8_t) * NSS_MAX_NET_INTERFACES);
+
+	if (nss_cmn_register_queue_decongestion(priv->nss_ctx, nss_capwapmgr_decongestion_callback, ndev) != NSS_CB_REGISTER_SUCCESS) {
+		nss_capwapmgr_warn("%px: failed to register decongestion callback\n", ndev);
+		goto fail4;
+	}
+
+	return ndev;
+fail4:
+	kfree(priv->if_num_to_tunnel_id);
+fail3:
+	kfree(priv->resp);
+fail2:
+	kfree(priv->tunnel);
+fail1:
+	unregister_netdev(ndev);
+	free_netdev(ndev);
+	return NULL;
+}
+EXPORT_SYMBOL(nss_capwapmgr_netdev_create);
+
+/*
+ * nss_capwapmgr_netdev_destroy()
+ *	API for destroying a netdevice.
+ *
+ * All the CAPWAP tunnels must be destroyed first before netdevice.
+ */
+nss_capwapmgr_status_t nss_capwapmgr_netdev_destroy(struct net_device *dev)
+{
+	rtnl_is_locked() ? unregister_netdevice(dev) : unregister_netdev(dev);
+	return NSS_CAPWAPMGR_SUCCESS;
+}
+EXPORT_SYMBOL(nss_capwapmgr_netdev_destroy);
+
+/*
+ * nss_capwapmgr_register_with_nss()
+ *	Internal function to register with NSS FW.
+ */
+static nss_capwapmgr_status_t nss_capwapmgr_register_with_nss(uint32_t interface_num, struct net_device *dev)
+{
+	struct nss_ctx_instance *ctx;
+
+	/* features denote the skb_types supported */
+	uint32_t features = 0;
+
+	ctx = nss_capwap_data_register(interface_num, nss_capwapmgr_receive_pkt, dev, features);
+	if (!ctx) {
+		nss_capwapmgr_warn("%px: %d: nss_capwapmgr_data_register failed\n", dev, interface_num);
+		return NSS_CAPWAPMGR_FAILURE;
+	}
+
+	return NSS_CAPWAPMGR_SUCCESS;
+}
+
+/*
+ * nss_capwapmgr_unregister_with_nss()
+ *	Internal function to unregister with NSS FW
+ */
+static void nss_capwapmgr_unregister_with_nss(uint32_t if_num)
+{
+	nss_capwapmgr_trace("%d: unregister with NSS FW\n", if_num);
+	nss_capwap_data_unregister(if_num);
+}
+
+/*
+ * nss_capwapmgr_destroy_ipv4_rule()
+ *	Destroy a given connection in the NSS
+ */
+static nss_tx_status_t nss_capwapmgr_destroy_ipv4_rule(void *ctx, struct nss_ipv4_destroy *unid)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *) ctx;
+	struct nss_ipv4_msg nim;
+	struct nss_ipv4_rule_destroy_msg *nirdm;
+	nss_tx_status_t status;
+
+	nss_capwapmgr_info("%px: ctx: Destroy IPv4: %pI4h:%d, %pI4h:%d, p: %d\n", nss_ctx,
+		&unid->src_ip, ntohs(unid->src_port), &unid->dest_ip, ntohs(unid->dest_port), unid->protocol);
+
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_DESTROY_RULE_MSG,
+			sizeof(struct nss_ipv4_rule_destroy_msg), nss_capwapmgr_ipv4_handler, NULL);
+
+	nirdm = &nim.msg.rule_destroy;
+
+	nirdm->tuple.protocol = (uint8_t)unid->protocol;
+	nirdm->tuple.flow_ip = unid->src_ip;
+	nirdm->tuple.flow_ident = (uint32_t)unid->src_port;
+	nirdm->tuple.return_ip = unid->dest_ip;
+	nirdm->tuple.return_ident = (uint32_t)unid->dest_port;
+
+	down(&ip_response.sem);
+	status = nss_ipv4_tx(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		up(&ip_response.sem);
+		nss_capwapmgr_warn("%px: Destroy IPv4 message failed %d\n", ctx, status);
+		return status;
+	}
+
+	ip_response.cond = 1;
+	if (!wait_event_timeout(ip_response.wq, ip_response.cond == 0, 5 * HZ)) {
+		nss_capwapmgr_warn("%px: Destroy IPv4 command msg response timeout\n", ctx);
+		status = NSS_TX_FAILURE;
+	} else if (ip_response.response != NSS_CMN_RESPONSE_ACK) {
+		nss_capwapmgr_warn("%px: Destroy IPv4 command msg failed with response : %d\n", ctx, ip_response.response);
+		status = NSS_TX_FAILURE;
+	}
+
+	up(&ip_response.sem);
+	return status;
+}
+
+/*
+ * nss_capwapmgr_unconfigure_ipv4_rule()
+ *	Internal function to unconfigure IPv4 rule.
+ */
+static nss_tx_status_t nss_capwapmgr_unconfigure_ipv4_rule(struct nss_ipv4_destroy *destroy)
+{
+	void *ctx;
+
+	ctx = nss_ipv4_get_mgr();
+	if (!ctx) {
+		nss_capwapmgr_warn("%s: couldn't get IPv4 ctx\n", "CAPWAP");
+		return NSS_TX_FAILURE_NOT_READY;
+	}
+
+	return nss_capwapmgr_destroy_ipv4_rule(ctx, destroy);
+}
+
+/*
+ * nss_capwapmgr_unconfigure_ipv6_rule()
+ *	Internal function to unconfigure IPv6 rule.
+ */
+static nss_tx_status_t nss_capwapmgr_unconfigure_ipv6_rule(struct nss_ipv6_destroy *unid)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_ipv6_msg nim;
+	struct nss_ipv6_rule_destroy_msg *nirdm;
+	nss_tx_status_t status;
+
+	nss_ctx = nss_ipv6_get_mgr();
+	if (!nss_ctx) {
+		nss_capwapmgr_warn("%s: couldn't get IPv6 ctx\n", "CAPWAP");
+		return NSS_TX_FAILURE_NOT_READY;
+	}
+
+	nss_capwapmgr_info("%px: ctx: Destroy IPv4: %x:%d, %x:%d, p: %d\n", nss_ctx,
+		unid->src_ip[0], ntohs(unid->src_port), unid->dest_ip[0], ntohs(unid->dest_port), unid->protocol);
+
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_DESTROY_RULE_MSG,
+			sizeof(struct nss_ipv6_rule_destroy_msg), nss_capwapmgr_ipv6_handler, NULL);
+
+	nirdm = &nim.msg.rule_destroy;
+
+	nirdm->tuple.protocol = (uint8_t)unid->protocol;
+	nirdm->tuple.flow_ident = (uint32_t)unid->src_port;
+	nirdm->tuple.flow_ip[0] = unid->src_ip[0];
+	nirdm->tuple.flow_ip[1] = unid->src_ip[1];
+	nirdm->tuple.flow_ip[2] = unid->src_ip[2];
+	nirdm->tuple.flow_ip[3] = unid->src_ip[3];
+
+	nirdm->tuple.return_ident = (uint32_t)unid->dest_port;
+	nirdm->tuple.return_ip[0] = unid->dest_ip[0];
+	nirdm->tuple.return_ip[1] = unid->dest_ip[1];
+	nirdm->tuple.return_ip[2] = unid->dest_ip[2];
+	nirdm->tuple.return_ip[3] = unid->dest_ip[3];
+
+	down(&ip_response.sem);
+	status = nss_ipv6_tx(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		up(&ip_response.sem);
+		nss_capwapmgr_warn("%px: Destroy IPv6 message failed %d\n", nss_ctx, status);
+		return status;
+	}
+
+	ip_response.cond = 1;
+	if (!wait_event_timeout(ip_response.wq, ip_response.cond == 0, 5 * HZ)) {
+		nss_capwapmgr_warn("%px: Destroy IPv6 command msg response timeout\n", nss_ctx);
+		status = NSS_TX_FAILURE;
+	} else if (ip_response.response != NSS_CMN_RESPONSE_ACK) {
+		nss_capwapmgr_warn("%px: Destroy IPv6 command msg failed with response : %d\n", nss_ctx, ip_response.response);
+		status = NSS_TX_FAILURE;
+	}
+
+	up(&ip_response.sem);
+	return status;
+}
+
+/*
+ * nss_capwapmgr_create_ipv4_rule()
+ *	Create a nss entry to accelerate the given connection
+ */
+static nss_tx_status_t nss_capwapmgr_create_ipv4_rule(void *ctx, struct nss_ipv4_create *unic, uint16_t rule_flags, uint16_t valid_flags)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *) ctx;
+	struct nss_ipv4_msg nim;
+	struct nss_ipv4_rule_create_msg *nircm;
+	nss_tx_status_t status;
+
+	nss_capwapmgr_info("%px: ctx: Create IPv4: %pI4h:%d (%pI4h:%d), %pI4h:%d (%pI4h:%d), p: %d\n", nss_ctx,
+		&unic->src_ip, unic->src_port, &unic->src_ip_xlate, unic->src_port_xlate,
+		&unic->dest_ip, unic->dest_port, &unic->dest_ip_xlate, unic->dest_port_xlate,
+		unic->protocol);
+
+	memset(&nim, 0, sizeof (struct nss_ipv4_msg));
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_CREATE_RULE_MSG,
+			sizeof(struct nss_ipv4_rule_create_msg), nss_capwapmgr_ipv4_handler, NULL);
+
+	nircm = &nim.msg.rule_create;
+	nircm->valid_flags = 0;
+	nircm->rule_flags = 0;
+
+	/*
+	 * Copy over the 5 tuple details.
+	 */
+	nircm->tuple.protocol = (uint8_t)unic->protocol;
+	nircm->tuple.flow_ip = unic->src_ip;
+	nircm->tuple.flow_ident = (uint32_t)unic->src_port;
+	nircm->tuple.return_ip = unic->dest_ip;
+	nircm->tuple.return_ident = (uint32_t)unic->dest_port;
+
+	/*
+	 * Copy over the connection rules and set the CONN_VALID flag
+	 */
+	nircm->conn_rule.flow_interface_num = unic->src_interface_num;
+	nircm->conn_rule.flow_mtu = unic->from_mtu;
+	nircm->conn_rule.flow_ip_xlate = unic->src_ip_xlate;
+	nircm->conn_rule.flow_ident_xlate = (uint32_t)unic->src_port_xlate;
+	memcpy(nircm->conn_rule.flow_mac, unic->src_mac, 6);
+	nircm->conn_rule.return_interface_num = unic->dest_interface_num;
+	nircm->conn_rule.return_mtu = unic->to_mtu;
+	nircm->conn_rule.return_ip_xlate = unic->dest_ip_xlate;
+	nircm->conn_rule.return_ident_xlate = (uint32_t)unic->dest_port_xlate;
+	if (nircm->tuple.return_ip != nircm->conn_rule.return_ip_xlate ||
+		nircm->tuple.return_ident != nircm->conn_rule.return_ident_xlate) {
+		memcpy(nircm->conn_rule.return_mac, unic->dest_mac_xlate, 6);
+	} else {
+		memcpy(nircm->conn_rule.return_mac, unic->dest_mac, 6);
+	}
+
+	/*
+	 * Copy over the DSCP rule parameters
+	 */
+	if (unic->flags & NSS_IPV4_CREATE_FLAG_DSCP_MARKING) {
+		nircm->dscp_rule.flow_dscp = unic->flow_dscp;
+		nircm->dscp_rule.return_dscp = unic->return_dscp;
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_DSCP_MARKING;
+		nircm->valid_flags |= NSS_IPV4_RULE_CREATE_DSCP_MARKING_VALID;
+	}
+
+	nircm->valid_flags |= NSS_IPV4_RULE_CREATE_CONN_VALID;
+
+	/*
+	 * Copy over the pppoe rules and set the PPPOE_VALID flag.
+	 */
+	nircm->pppoe_rule.flow_if_exist = unic->flow_pppoe_if_exist;
+	nircm->pppoe_rule.flow_if_num = unic->flow_pppoe_if_num;
+	nircm->pppoe_rule.return_if_exist = unic->return_pppoe_if_exist;
+	nircm->pppoe_rule.return_if_num = unic->return_pppoe_if_num;
+	nircm->valid_flags |= NSS_IPV4_RULE_CREATE_PPPOE_VALID;
+
+	/*
+	 * Copy over the vlan rules and set the VLAN_VALID flag
+	 */
+	nircm->vlan_primary_rule.ingress_vlan_tag = unic->in_vlan_tag[0];
+	nircm->vlan_primary_rule.egress_vlan_tag = unic->out_vlan_tag[0];
+	nircm->vlan_secondary_rule.ingress_vlan_tag = unic->in_vlan_tag[1];
+	nircm->vlan_secondary_rule.egress_vlan_tag = unic->out_vlan_tag[1];
+	nircm->valid_flags |= NSS_IPV4_RULE_CREATE_VLAN_VALID;
+
+	/*
+	 * Copy over the qos rules and set the QOS_VALID flag
+	 */
+	if (unic->flags & NSS_IPV6_CREATE_FLAG_QOS_VALID) {
+		nircm->qos_rule.flow_qos_tag = unic->flow_qos_tag;
+		nircm->qos_rule.return_qos_tag = unic->return_qos_tag;
+		nircm->valid_flags |= NSS_IPV4_RULE_CREATE_QOS_VALID;
+	}
+
+	if (unic->flags & NSS_IPV4_CREATE_FLAG_NO_SEQ_CHECK) {
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_NO_SEQ_CHECK;
+	}
+
+	if (unic->flags & NSS_IPV4_CREATE_FLAG_BRIDGE_FLOW) {
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_BRIDGE_FLOW;
+	}
+
+	if (unic->flags & NSS_IPV4_CREATE_FLAG_ROUTED) {
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_ROUTED;
+	}
+
+	/*
+	 * Set the flag NSS_IPV4_RULE_CREATE_FLAG_ICMP_NO_CME_FLUSH so that
+	 * rule is not flushed when NSS FW receives ICMP errors/packets.
+	 */
+	nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_ICMP_NO_CME_FLUSH;
+
+	/*
+	 * Add any other additional flags which caller has requested.
+	 * For example: update MTU, update destination MAC address.
+	 */
+	nircm->rule_flags |= rule_flags;
+	nircm->valid_flags |= valid_flags;
+
+	down(&ip_response.sem);
+	status = nss_ipv4_tx(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		up(&ip_response.sem);
+		nss_capwapmgr_warn("%px: Create IPv4 message failed %d\n", ctx, status);
+		return status;
+	}
+
+	ip_response.cond = 1;
+	if (!wait_event_timeout(ip_response.wq, ip_response.cond == 0, 5 * HZ)) {
+		nss_capwapmgr_warn("%px: Create IPv4 command msg response timeout\n", ctx);
+		status = NSS_TX_FAILURE;
+	} else if (ip_response.response != NSS_CMN_RESPONSE_ACK) {
+		nss_capwapmgr_warn("%px: Create IPv4 command msg failed with response: %d\n", ctx, ip_response.response);
+		status = NSS_TX_FAILURE;
+	}
+
+	up(&ip_response.sem);
+	return status;
+}
+
+/*
+ * nss_capwapmgr_create_ipv6_rule()
+ *	Create a nss entry to accelerate the given connection
+ */
+static nss_tx_status_t nss_capwapmgr_create_ipv6_rule(void *ctx, struct nss_ipv6_create *unic, uint16_t rule_flags, uint16_t valid_flags)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *) ctx;
+	struct nss_ipv6_msg nim;
+	struct nss_ipv6_rule_create_msg *nircm;
+	nss_tx_status_t status;
+
+	nss_capwapmgr_info("%px: Create IPv6: %pI6:%d, %pI6:%d, p: %d\n", nss_ctx,
+		unic->src_ip, unic->src_port, unic->dest_ip, unic->dest_port, unic->protocol);
+
+	memset(&nim, 0, sizeof (struct nss_ipv6_msg));
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_CREATE_RULE_MSG,
+			sizeof(struct nss_ipv6_rule_create_msg), nss_capwapmgr_ipv6_handler, NULL);
+
+	nircm = &nim.msg.rule_create;
+
+	nircm->rule_flags = 0;
+	nircm->valid_flags = 0;
+
+	/*
+	 * Copy over the 5 tuple information.
+	 */
+	nircm->tuple.protocol = (uint8_t)unic->protocol;
+	nircm->tuple.flow_ip[0] = unic->src_ip[0];
+	nircm->tuple.flow_ip[1] = unic->src_ip[1];
+	nircm->tuple.flow_ip[2] = unic->src_ip[2];
+	nircm->tuple.flow_ip[3] = unic->src_ip[3];
+	nircm->tuple.flow_ident = (uint32_t)unic->src_port;
+
+	nircm->tuple.return_ip[0] = unic->dest_ip[0];
+	nircm->tuple.return_ip[1] = unic->dest_ip[1];
+	nircm->tuple.return_ip[2] = unic->dest_ip[2];
+	nircm->tuple.return_ip[3] = unic->dest_ip[3];
+	nircm->tuple.return_ident = (uint32_t)unic->dest_port;
+
+	/*
+	 * Copy over the connection rules and set CONN_VALID flag
+	 */
+	nircm->conn_rule.flow_interface_num = unic->src_interface_num;
+	nircm->conn_rule.flow_mtu = unic->from_mtu;
+	nircm->conn_rule.return_interface_num = unic->dest_interface_num;
+	nircm->conn_rule.return_mtu = unic->to_mtu;
+	memcpy(nircm->conn_rule.flow_mac, unic->src_mac, 6);
+	memcpy(nircm->conn_rule.return_mac, unic->dest_mac, 6);
+	nircm->valid_flags |= NSS_IPV6_RULE_CREATE_CONN_VALID;
+
+	/*
+	 * Copy over the DSCP rule parameters
+	 */
+	if (unic->flags & NSS_IPV6_CREATE_FLAG_DSCP_MARKING) {
+		nircm->dscp_rule.flow_dscp = unic->flow_dscp;
+		nircm->dscp_rule.return_dscp = unic->return_dscp;
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_DSCP_MARKING;
+		nircm->valid_flags |= NSS_IPV6_RULE_CREATE_DSCP_MARKING_VALID;
+	}
+
+	/*
+	 * Copy over the pppoe rules and set PPPOE_VALID flag
+	 */
+	nircm->pppoe_rule.flow_if_exist = unic->flow_pppoe_if_exist;
+	nircm->pppoe_rule.flow_if_num = unic->flow_pppoe_if_num;
+	nircm->pppoe_rule.return_if_exist = unic->return_pppoe_if_exist;
+	nircm->pppoe_rule.return_if_num = unic->return_pppoe_if_num;
+	nircm->valid_flags |= NSS_IPV6_RULE_CREATE_PPPOE_VALID;
+
+	/*
+	 * Copy over the tcp rules and set TCP_VALID flag
+	 */
+	nircm->tcp_rule.flow_window_scale = unic->flow_window_scale;
+	nircm->tcp_rule.flow_max_window = unic->flow_max_window;
+	nircm->tcp_rule.flow_end = unic->flow_end;
+	nircm->tcp_rule.flow_max_end = unic->flow_max_end;
+	nircm->tcp_rule.return_window_scale = unic->return_window_scale;
+	nircm->tcp_rule.return_max_window = unic->return_max_window;
+	nircm->tcp_rule.return_end = unic->return_end;
+	nircm->tcp_rule.return_max_end = unic->return_max_end;
+	nircm->valid_flags |= NSS_IPV6_RULE_CREATE_TCP_VALID;
+
+	/*
+	 * Copy over the vlan rules and set the VLAN_VALID flag
+	 */
+	nircm->vlan_primary_rule.egress_vlan_tag = unic->out_vlan_tag[0];
+	nircm->vlan_primary_rule.ingress_vlan_tag = unic->in_vlan_tag[0];
+	nircm->vlan_secondary_rule.egress_vlan_tag = unic->out_vlan_tag[1];
+	nircm->vlan_secondary_rule.ingress_vlan_tag = unic->in_vlan_tag[1];
+	nircm->valid_flags |= NSS_IPV6_RULE_CREATE_VLAN_VALID;
+
+	/*
+	 * Copy over the qos rules and set the QOS_VALID flag
+	 */
+	if (unic->flags & NSS_IPV6_CREATE_FLAG_QOS_VALID) {
+		nircm->qos_rule.flow_qos_tag = unic->flow_qos_tag;
+		nircm->qos_rule.return_qos_tag = unic->return_qos_tag;
+		nircm->valid_flags |= NSS_IPV6_RULE_CREATE_QOS_VALID;
+	}
+
+	if (unic->flags & NSS_IPV6_CREATE_FLAG_NO_SEQ_CHECK) {
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_NO_SEQ_CHECK;
+	}
+
+	if (unic->flags & NSS_IPV6_CREATE_FLAG_BRIDGE_FLOW) {
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_BRIDGE_FLOW;
+	}
+
+	if (unic->flags & NSS_IPV6_CREATE_FLAG_ROUTED) {
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_ROUTED;
+	}
+
+	/*
+	 * Set the flag NSS_IPV6_RULE_CREATE_FLAG_ICMP_NO_CME_FLUSH so that
+	 * rule is not flushed when NSS FW receives ICMP errors/packets.
+	 */
+	nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_ICMP_NO_CME_FLUSH;
+
+	/*
+	 * Add any other additional flags which caller has requested.
+	 * For example: update MTU, Update destination MAC address.
+	 */
+	nircm->rule_flags |= rule_flags;
+	nircm->valid_flags |= valid_flags;
+
+	down(&ip_response.sem);
+	status = nss_ipv6_tx(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		up(&ip_response.sem);
+		nss_capwapmgr_warn("%px: Create IPv6 message failed %d\n", ctx, status);
+		return status;
+	}
+
+	ip_response.cond = 1;
+	if (!wait_event_timeout(ip_response.wq, ip_response.cond == 0, 5 * HZ)) {
+		nss_capwapmgr_warn("%px: Create IPv6 command msg response timeout\n", ctx);
+		status = NSS_TX_FAILURE;
+	} else if (ip_response.response != NSS_CMN_RESPONSE_ACK) {
+		nss_capwapmgr_warn("%px: Create IPv6 command msg failed with response: %d\n", ctx, ip_response.response);
+		status = NSS_TX_FAILURE;
+	}
+
+	up(&ip_response.sem);
+	return status;
+}
+
+/*
+ * nss_capwapmgr_configure_ipv4()
+ *	Internal function for configuring IPv4 connection
+ */
+static nss_tx_status_t nss_capwapmgr_configure_ipv4(struct nss_ipv4_create *pcreate, uint16_t rule_flags, uint16_t valid_flags)
+{
+	nss_tx_status_t status;
+	void *ctx;
+
+	ctx = nss_ipv4_get_mgr();
+	if (!ctx) {
+		nss_capwapmgr_warn("%s couldn't get IPv4 ctx\n", "CAPWAP");
+		return NSS_TX_FAILURE_NOT_READY;
+	}
+
+	status = nss_capwapmgr_create_ipv4_rule(ctx, pcreate, rule_flags, valid_flags);
+	if (status != NSS_TX_SUCCESS) {
+		nss_capwapmgr_warn("%px: ctx: nss_ipv4_tx() failed with %d\n", ctx, status);
+		return status;
+	}
+
+	return NSS_TX_SUCCESS;
+}
+
+/*
+ * nss_capwapmgr_configure_ipv6()
+ *	Internal function for configuring IPv4 connection
+ */
+static nss_tx_status_t nss_capwapmgr_configure_ipv6(struct nss_ipv6_create *pcreate, uint16_t rule_flags, uint16_t valid_flags)
+{
+	nss_tx_status_t status;
+	void *ctx;
+
+	ctx = nss_ipv6_get_mgr();
+	if (!ctx) {
+		nss_capwapmgr_warn("%s couldn't get IPv6 ctx\n", "CAPWAP");
+		return NSS_TX_FAILURE_NOT_READY;
+	}
+
+	status = nss_capwapmgr_create_ipv6_rule(ctx, pcreate, rule_flags, valid_flags);
+	if (status != NSS_TX_SUCCESS) {
+		nss_capwapmgr_warn("%px: ctx: nss_ipv6_tx() failed with %d\n", ctx, status);
+		return status;
+	}
+
+	return NSS_TX_SUCCESS;
+}
+
+/*
+ * nss_capwapmgr_tx_msg_sync()
+ *	Waits for message to return.
+ */
+static nss_capwapmgr_status_t nss_capwapmgr_tx_msg_sync(struct nss_ctx_instance *ctx, struct net_device *dev, struct nss_capwap_msg *msg)
+{
+	struct nss_capwapmgr_priv *priv;
+	struct nss_capwapmgr_response *r;
+	uint32_t if_num;
+	nss_capwapmgr_status_t status;
+
+	if_num = msg->cm.interface - NSS_DYNAMIC_IF_START;
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+	r = &priv->resp[if_num];
+	down(&r->sem);
+	r->response = NSS_CMN_RESPONSE_ACK;
+	atomic_set(&r->seq, 1);		/* Indicate that we are waiting */
+
+	/*
+	 * Call NSS driver
+	 */
+	status = nss_capwap_tx_msg(ctx, msg);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		up(&r->sem);
+		dev_put(dev);
+		return status;
+	}
+
+	if (!wait_event_timeout(r->wq, atomic_read(&r->seq) == 0, 5 * HZ)) {
+		atomic_set(&r->seq, 0);		/* Indicate that we are no longer waiting */
+		up(&r->sem);
+		nss_capwapmgr_warn("%px: CAPWAP command msg response timeout\n", ctx);
+		dev_put(dev);
+		return NSS_CAPWAPMGR_FAILURE_CMD_TIMEOUT;
+	}
+
+	/*
+	 * If NSS FW responded back with an error.
+	 */
+	if (r->response != NSS_CMN_RESPONSE_ACK) {
+		up(&r->sem);
+		nss_capwapmgr_warn("%px: CAPWAP command msg response : %d, error:%d\n", ctx,
+				r->response, r->error);
+		dev_put(dev);
+		return nss_capwap_remap_error(r->error);
+	}
+
+	up(&r->sem);
+	dev_put(dev);
+	return status;
+}
+
+/*
+ * nss_capwapmgr_create_capwap_rule()
+ *	Internal function to create a CAPWAP rule
+ */
+static nss_capwapmgr_status_t nss_capwapmgr_create_capwap_rule(struct net_device *dev,
+	uint32_t if_num, struct nss_capwap_rule_msg *msg, uint16_t type_flags)
+{
+	struct nss_ctx_instance *ctx = nss_capwap_get_ctx();
+	struct nss_capwap_msg capwapmsg;
+	struct nss_capwap_rule_msg *capwapcfg;
+	nss_tx_status_t status;
+
+	nss_capwapmgr_info("%px: ctx: CAPWAP Rule src_port: 0x%d dest_port:0x%d\n", ctx,
+	    ntohl(msg->encap.src_port), ntohl(msg->encap.dest_port));
+
+	/*
+	 * Verify CAPWAP rule parameters.
+	 */
+	if (ntohl(msg->decap.reassembly_timeout) > NSS_CAPWAP_MAX_REASSEMBLY_TIMEOUT) {
+		nss_capwapmgr_warn("%px: invalid reassem timeout: %d, max: %d\n",
+			ctx, ntohl(msg->decap.reassembly_timeout), NSS_CAPWAP_MAX_REASSEMBLY_TIMEOUT);
+		return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+	}
+
+	if (msg->decap.reassembly_timeout == 0) {
+		msg->decap.reassembly_timeout = htonl(10);	/* 10 milli-seconds */
+	}
+
+	if (ntohl(msg->decap.max_fragments) > NSS_CAPWAP_MAX_FRAGMENTS) {
+		nss_capwapmgr_warn("%px: invalid fragment setting: %d, max: %d\n",
+			ctx, ntohl(msg->decap.max_fragments), NSS_CAPWAP_MAX_FRAGMENTS);
+		return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+	}
+
+	if (msg->decap.max_fragments == 0) {
+		msg->decap.max_fragments = htonl(NSS_CAPWAP_MAX_FRAGMENTS);
+	}
+
+	if (ntohl(msg->decap.max_buffer_size) > NSS_CAPWAP_MAX_BUFFER_SIZE) {
+		nss_capwapmgr_warn("%px: invalid buffer size: %d, max: %d\n",
+			ctx, ntohl(msg->decap.max_buffer_size), NSS_CAPWAP_MAX_BUFFER_SIZE);
+		return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+	}
+
+	if (msg->decap.max_buffer_size == 0) {
+		msg->decap.max_buffer_size = htonl(nss_capwap_get_max_buf_size(ctx));
+	}
+
+	if (ntohl(msg->encap.path_mtu) > NSS_CAPWAP_MAX_MTU) {
+		nss_capwapmgr_warn("%px: invalid path_mtu: %d, max: %d\n",
+			ctx, ntohl(msg->encap.path_mtu), NSS_CAPWAP_MAX_MTU);
+		return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+	}
+
+	if (msg->encap.path_mtu == 0) {
+		msg->encap.path_mtu = htonl(NSS_CAPWAPMGR_NORMAL_FRAME_MTU);
+	}
+
+	msg->type_flags = type_flags;
+
+	/*
+	 * Prepare the tunnel configuration parameter to send to NSS FW
+	 */
+	memset(&capwapmsg, 0, sizeof(struct nss_capwap_msg));
+	capwapcfg = &capwapmsg.msg.rule;
+	memcpy(capwapcfg, msg, sizeof(struct nss_capwap_rule_msg));
+
+	/*
+	 * Send CAPWAP tunnel create command to NSS
+	 */
+	nss_capwap_msg_init(&capwapmsg, if_num, NSS_CAPWAP_MSG_TYPE_CFG_RULE,
+			sizeof(struct nss_capwap_rule_msg),
+			nss_capwapmgr_msg_event_receive, dev);
+
+	status = nss_capwapmgr_tx_msg_sync(ctx, dev, &capwapmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_capwapmgr_warn("%px: ctx: create encap data tunnel error %d \n", ctx, status);
+		return status;
+	}
+
+	return NSS_CAPWAPMGR_SUCCESS;
+}
+
+/*
+ * nss_capwapmgr_tx_msg_enable_tunnel()
+ *	Common function to send CAPWAP tunnel enable msg
+ */
+static nss_tx_status_t nss_capwapmgr_tx_msg_enable_tunnel(struct nss_ctx_instance *ctx, struct net_device *dev, uint32_t if_num, uint32_t sibling_if_num)
+{
+	struct nss_capwap_msg capwapmsg;
+	nss_tx_status_t status;
+
+	/*
+	 * Prepare the tunnel configuration parameter to send to NSS FW
+	 */
+	memset(&capwapmsg, 0, sizeof(struct nss_capwap_msg));
+	capwapmsg.msg.enable_tunnel.sibling_if_num = sibling_if_num;
+
+	/*
+	 * Send CAPWAP data tunnel command to NSS
+	 */
+	nss_capwap_msg_init(&capwapmsg, if_num, NSS_CAPWAP_MSG_TYPE_ENABLE_TUNNEL, sizeof(struct nss_capwap_enable_tunnel_msg), nss_capwapmgr_msg_event_receive, dev);
+
+	status = nss_capwapmgr_tx_msg_sync(ctx, dev, &capwapmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_capwapmgr_warn("%px: ctx: CMD: %d Tunnel error : %d \n", ctx, NSS_CAPWAP_MSG_TYPE_ENABLE_TUNNEL, status);
+	}
+
+	return status;
+}
+
+/*
+ * nss_capwapmgr_tunnel_action()
+ *	Common function for CAPWAP tunnel operation messages without
+ *	any message data structures.
+ */
+static nss_tx_status_t nss_capwapmgr_tunnel_action(struct nss_ctx_instance *ctx, struct net_device *dev, uint32_t if_num, nss_capwap_msg_type_t cmd)
+{
+	struct nss_capwap_msg capwapmsg;
+	nss_tx_status_t status;
+
+	/*
+	 * Prepare the tunnel configuration parameter to send to NSS FW
+	 */
+	memset(&capwapmsg, 0, sizeof(struct nss_capwap_msg));
+
+	/*
+	 * Send CAPWAP data tunnel command to NSS
+	 */
+	nss_capwap_msg_init(&capwapmsg, if_num, cmd, 0, nss_capwapmgr_msg_event_receive, dev);
+
+	status = nss_capwapmgr_tx_msg_sync(ctx, dev, &capwapmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_capwapmgr_warn("%px: ctx: CMD: %d Tunnel error : %d \n", ctx, cmd, status);
+	}
+
+	return status;
+}
+
+/*
+ * nss_capwapmgr_get_dtls_netdev()
+ *	API for getting the dtls netdev associated to the capwap tunnel
+ *
+ * The caller is expected to do a dev_put() to release the reference.
+ */
+struct net_device *nss_capwapmgr_get_dtls_netdev(struct net_device *capwap_dev, uint8_t tunnel_id)
+{
+	struct nss_capwapmgr_tunnel *t;
+	struct net_device *dtls_dev;
+
+	dev_hold(capwap_dev);
+	t = nss_capwapmgr_verify_tunnel_param(capwap_dev, tunnel_id);
+	if (!t) {
+		nss_capwapmgr_warn("%px: can't find tunnel: %d\n", capwap_dev, tunnel_id);
+		dev_put(capwap_dev);
+		return NULL;
+	}
+
+	dtls_dev = t->dtls_dev;
+	dev_hold(dtls_dev);
+
+	dev_put(capwap_dev);
+
+	return dtls_dev;
+}
+EXPORT_SYMBOL(nss_capwapmgr_get_dtls_netdev);
+
+/*
+ * nss_capwapmgr_update_path_mtu()
+ *	API for updating Path MTU
+ */
+nss_capwapmgr_status_t nss_capwapmgr_update_path_mtu(struct net_device *dev, uint8_t tunnel_id, uint32_t mtu)
+{
+	struct nss_capwapmgr_priv *priv;
+	struct nss_capwap_msg capwapmsg;
+	struct nss_capwapmgr_tunnel *t;
+	nss_capwapmgr_status_t status;
+	nss_tx_status_t nss_status;
+
+	if (mtu > NSS_CAPWAP_MAX_MTU) {
+		nss_capwapmgr_warn("%px: invalid path_mtu: %d, max: %d\n", dev, mtu, NSS_CAPWAP_MAX_MTU);
+		return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+	}
+
+	dev_hold(dev);
+	t = nss_capwapmgr_verify_tunnel_param(dev, tunnel_id);
+	if (!t) {
+		nss_capwapmgr_warn("%px: can't find tunnel: %d\n", dev, tunnel_id);
+		dev_put(dev);
+		return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+	}
+
+	priv = netdev_priv(dev);
+	nss_capwapmgr_info("%px: %d: tunnel update MTU is being called\n", dev, t->if_num_inner);
+
+	/*
+	 * Prepare the tunnel configuration parameter to send to NSS FW
+	 */
+	memset(&capwapmsg, 0, sizeof(struct nss_capwap_msg));
+
+	/*
+	 * Send CAPWAP data tunnel command to NSS
+	 */
+	nss_capwap_msg_init(&capwapmsg, t->if_num_inner, NSS_CAPWAP_MSG_TYPE_UPDATE_PATH_MTU,
+		sizeof(struct nss_capwap_path_mtu_msg), nss_capwapmgr_msg_event_receive, dev);
+	capwapmsg.msg.mtu.path_mtu = htonl(mtu);
+	status = nss_capwapmgr_tx_msg_sync(priv->nss_ctx, dev, &capwapmsg);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_capwapmgr_warn("%px: Update Path MTU CAPWAP tunnel error : %d \n", dev, status);
+		dev_put(dev);
+		return NSS_CAPWAPMGR_FAILURE_CAPWAP_RULE;
+	}
+
+	/*
+	 * Update the IPv4/IPv6 rule with the new MTU for flow and return
+	 * TODO: Change rule flag to valid flag
+	 */
+	if (t->capwap_rule.l3_proto == NSS_CAPWAP_TUNNEL_IPV4) {
+		struct nss_ipv4_create *v4;
+
+		v4 = &t->ip_rule.v4;
+		v4->from_mtu = v4->to_mtu = mtu;
+		nss_status = nss_capwapmgr_configure_ipv4(v4, NSS_IPV4_RULE_UPDATE_FLAG_CHANGE_MTU, 0);
+		if (nss_status != NSS_TX_SUCCESS) {
+			v4->from_mtu = v4->to_mtu = ntohl(t->capwap_rule.encap.path_mtu);
+		}
+	} else {
+		struct nss_ipv6_create *v6;
+
+		v6 = &t->ip_rule.v6;
+		v6->from_mtu = v6->to_mtu = mtu;
+		nss_status = nss_capwapmgr_configure_ipv6(v6, NSS_IPV6_RULE_UPDATE_FLAG_CHANGE_MTU, 0);
+		if (nss_status != NSS_TX_SUCCESS) {
+			v6->from_mtu = v6->to_mtu = ntohl(t->capwap_rule.encap.path_mtu);
+		}
+	}
+
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_capwapmgr_warn("%px: Update Path MTU IP RULE tunnel error : %d \n", dev, nss_status);
+		capwapmsg.msg.mtu.path_mtu = t->capwap_rule.encap.path_mtu;
+		status = nss_capwapmgr_tx_msg_sync(priv->nss_ctx, dev, &capwapmsg);
+		if (status != NSS_CAPWAPMGR_SUCCESS) {
+			nss_capwapmgr_warn("%px: Restore Path MTU CAPWAP tunnel error : %d \n", dev, status);
+		}
+
+		dev_put(dev);
+		return NSS_CAPWAPMGR_FAILURE_IP_RULE;
+	}
+
+	t->capwap_rule.encap.path_mtu = htonl(mtu);
+	dev_put(dev);
+	return status;
+}
+EXPORT_SYMBOL(nss_capwapmgr_update_path_mtu);
+
+/*
+ * nss_capwapmgr_update_dest_mac_addr()
+ *	API for updating Destination Mac Addr
+ */
+nss_capwapmgr_status_t nss_capwapmgr_update_dest_mac_addr(struct net_device *dev, uint8_t tunnel_id, uint8_t *mac_addr)
+{
+	struct nss_capwapmgr_priv *priv;
+	struct nss_capwapmgr_tunnel *t;
+	nss_tx_status_t nss_status;
+	nss_capwapmgr_status_t status = NSS_CAPWAPMGR_SUCCESS;
+	struct nss_ipv6_create *v6;
+	uint8_t mac_addr_old[ETH_ALEN];
+
+	dev_hold(dev);
+	t = nss_capwapmgr_verify_tunnel_param(dev, tunnel_id);
+	if (!t) {
+		nss_capwapmgr_warn("%px: can't find tunnel: %d\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+
+	priv = netdev_priv(dev);
+	nss_capwapmgr_info("%px: %d: tunnel update mac Addr is being called\n", dev, tunnel_id);
+
+	/*
+	 * Update the IPv4/IPv6 rule with the new destination mac address for flow and return.
+	 * Since the encap direction is handled by the return rule, we are updating the src_mac.
+	 */
+	if (t->capwap_rule.l3_proto == NSS_CAPWAP_TUNNEL_IPV4) {
+		struct nss_ipv4_create *v4;
+
+		v4 = &t->ip_rule.v4;
+		memcpy(mac_addr_old, v4->src_mac, ETH_ALEN);
+		memcpy(v4->src_mac, mac_addr, ETH_ALEN);
+		nss_status = nss_capwapmgr_configure_ipv4(v4, 0, NSS_IPV4_RULE_CREATE_DEST_MAC_VALID);
+
+		if (nss_status != NSS_TX_SUCCESS) {
+			nss_capwapmgr_warn("%px: Update Destination Mac for tunnel error : %d \n", dev, nss_status);
+			memcpy(t->ip_rule.v4.src_mac, mac_addr_old, ETH_ALEN);
+			status = NSS_CAPWAPMGR_FAILURE_IP_RULE;
+		}
+
+		goto done;
+	}
+
+	v6 = &t->ip_rule.v6;
+	memcpy(mac_addr_old, v6->src_mac, ETH_ALEN);
+	memcpy(v6->src_mac, mac_addr, ETH_ALEN);
+	nss_status = nss_capwapmgr_configure_ipv6(v6, 0, NSS_IPV6_RULE_CREATE_DEST_MAC_VALID);
+
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_capwapmgr_warn("%px: Update Destination Mac for tunnel error : %d \n", dev, nss_status);
+		memcpy(t->ip_rule.v6.src_mac, mac_addr_old, ETH_ALEN);
+		status = NSS_CAPWAPMGR_FAILURE_IP_RULE;
+	}
+
+done:
+	dev_put(dev);
+	return status;
+}
+EXPORT_SYMBOL(nss_capwapmgr_update_dest_mac_addr);
+
+/*
+ * nss_capwapmgr_update_src_interface()
+ *	API for updating Source Interface
+ */
+nss_capwapmgr_status_t nss_capwapmgr_update_src_interface(struct net_device *dev, uint8_t tunnel_id, uint32_t src_interface_num)
+{
+	struct nss_capwapmgr_priv *priv;
+	struct nss_capwapmgr_tunnel *t;
+	nss_tx_status_t nss_status;
+	uint32_t outer_trustsec_enabled, dtls_enabled, forward_if_num, src_interface_num_temp;
+
+	dev_hold(dev);
+	t = nss_capwapmgr_verify_tunnel_param(dev, tunnel_id);
+	if (!t) {
+		nss_capwapmgr_warn("%px: can't find tunnel: %d\n", dev, tunnel_id);
+		dev_put(dev);
+		return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+	}
+
+
+	priv = netdev_priv(dev);
+	nss_capwapmgr_info("%px: %d: tunnel update source interface is being called\n", dev, tunnel_id);
+	outer_trustsec_enabled = t->capwap_rule.enabled_features & NSS_CAPWAPMGR_FEATURE_OUTER_TRUSTSEC_ENABLED;
+	dtls_enabled = t->capwap_rule.enabled_features & NSS_CAPWAPMGR_FEATURE_DTLS_ENABLED;
+
+	/*
+	 * If trustsec is enabled, just update the next node of trustsec.
+	 */
+	if (outer_trustsec_enabled) {
+		if (!dtls_enabled) {
+			forward_if_num = nss_capwap_ifnum_with_core_id(t->if_num_outer);
+		} else {
+			forward_if_num = nss_dtlsmgr_get_interface(t->dtls_dev, NSS_DTLSMGR_INTERFACE_TYPE_OUTER);
+		}
+
+		nss_status = nss_trustsec_tx_update_nexthop(forward_if_num, src_interface_num, t->capwap_rule.outer_sgt_value);
+		if (nss_status != NSS_TX_SUCCESS) {
+			nss_capwapmgr_warn("%px: unconfigure trustsec_tx failed\n", dev);
+			dev_put(dev);
+			return NSS_CAPWAPMGR_FAILURE_UNCONFIGURE_TRUSTSEC_TX;
+		}
+
+		if (t->capwap_rule.l3_proto == NSS_CAPWAP_TUNNEL_IPV4) {
+			t->ip_rule.v4.src_interface_num = src_interface_num;
+		} else {
+			t->ip_rule.v6.src_interface_num = src_interface_num;
+		}
+		dev_put(dev);
+		return NSS_CAPWAPMGR_SUCCESS;
+	}
+
+	/*
+	 * Destroy/Re-Create the IPv4/IPv6 rule with the new Interface number for flow and return
+	 */
+	if (t->capwap_rule.l3_proto == NSS_CAPWAP_TUNNEL_IPV4) {
+
+		/*
+		 * Destroy the IP rule only if it already exist.
+		 */
+		if (t->tunnel_state & NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED) {
+			struct nss_ipv4_destroy v4_destroy;
+			v4_destroy.protocol = IPPROTO_UDP;
+			v4_destroy.src_ip = t->ip_rule.v4.src_ip;
+			v4_destroy.dest_ip = t->ip_rule.v4.dest_ip;
+			v4_destroy.src_port = t->ip_rule.v4.src_port;
+			v4_destroy.dest_port = t->ip_rule.v4.dest_port;
+			nss_status = nss_capwapmgr_unconfigure_ipv4_rule(&v4_destroy);
+			if (nss_status != NSS_TX_SUCCESS) {
+				nss_capwapmgr_warn("%px: unconfigure ipv4 rule failed : %d\n", dev, nss_status);
+				dev_put(dev);
+				return NSS_CAPWAPMGR_FAILURE_IP_DESTROY_RULE;
+			}
+
+			t->tunnel_state &= ~NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED;
+		}
+
+		src_interface_num_temp = t->ip_rule.v4.src_interface_num;
+		t->ip_rule.v4.src_interface_num = src_interface_num;
+		nss_capwapmgr_configure_ipv4(&t->ip_rule.v4, 0, 0);
+		if (nss_status != NSS_TX_SUCCESS) {
+			nss_capwapmgr_warn("%px: configure ipv4 rule failed : %d\n", dev, nss_status);
+			t->ip_rule.v4.src_interface_num = src_interface_num_temp;
+			dev_put(dev);
+			return NSS_CAPWAPMGR_FAILURE_IP_RULE;
+		}
+	} else {
+		/*
+		 * Destroy the IP rule only if it already exist.
+		 */
+		if (t->tunnel_state & NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED) {
+			struct nss_ipv6_destroy v6_destroy;
+
+			if (t->capwap_rule.which_udp == NSS_CAPWAP_TUNNEL_UDP) {
+				v6_destroy.protocol = IPPROTO_UDP;
+			} else {
+				v6_destroy.protocol = IPPROTO_UDPLITE;
+			}
+
+			v6_destroy.src_ip[0] = t->ip_rule.v6.src_ip[0];
+			v6_destroy.src_ip[1] = t->ip_rule.v6.src_ip[1];
+			v6_destroy.src_ip[2] = t->ip_rule.v6.src_ip[2];
+			v6_destroy.src_ip[3] = t->ip_rule.v6.src_ip[3];
+
+			v6_destroy.dest_ip[0] = t->ip_rule.v6.dest_ip[0];
+			v6_destroy.dest_ip[1] = t->ip_rule.v6.dest_ip[1];
+			v6_destroy.dest_ip[2] = t->ip_rule.v6.dest_ip[2];
+			v6_destroy.dest_ip[3] = t->ip_rule.v6.dest_ip[3];
+
+			v6_destroy.src_port = t->ip_rule.v6.src_port;
+			v6_destroy.dest_port = t->ip_rule.v6.dest_port;
+			nss_status = nss_capwapmgr_unconfigure_ipv6_rule(&v6_destroy);
+			if (nss_status != NSS_TX_SUCCESS) {
+				nss_capwapmgr_warn("%px: unconfigure ipv6 rule failed : %d\n", dev, nss_status);
+				dev_put(dev);
+				return NSS_CAPWAPMGR_FAILURE_IP_DESTROY_RULE;
+			}
+
+			t->tunnel_state &= ~NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED;
+		}
+
+		src_interface_num_temp = t->ip_rule.v6.src_interface_num;
+		t->ip_rule.v6.src_interface_num = src_interface_num;
+		nss_capwapmgr_configure_ipv6(&t->ip_rule.v6, 0, 0);
+		if (nss_status != NSS_TX_SUCCESS) {
+			nss_capwapmgr_warn("%px: configure ipv6 rule failed : %d\n", dev, nss_status);
+			t->ip_rule.v6.src_interface_num = src_interface_num_temp;
+			dev_put(dev);
+			return NSS_CAPWAPMGR_FAILURE_IP_RULE;
+		}
+	}
+	t->tunnel_state |= NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED;
+	dev_put(dev);
+	return NSS_CAPWAPMGR_SUCCESS;
+}
+EXPORT_SYMBOL(nss_capwapmgr_update_src_interface);
+
+/*
+ * nss_capwapmgr_dscp_rule_destroy()
+ *	API to destroy previously created DSCP rule.
+ */
+nss_capwapmgr_status_t nss_capwapmgr_dscp_rule_destroy(uint8_t id)
+{
+	sw_error_t rv;
+	fal_qos_cosmap_t cosmap;
+	struct nss_capwapmgr_acl *acl_rule;
+	uint8_t dev_id = NSS_CAPWAPMGR_DEV_ID;
+	uint8_t rule_nr = NSS_CAPWAPMGR_RULE_NR;
+	uint8_t group_id = NSS_CAPWAPMGR_GROUP_ID;
+	uint8_t i, j, list_id, v4_rule_id, v6_rule_id, dscp_value, dscp_mask;
+
+	for (i = 0; i < NSS_CAPWAPMGR_ACL_LIST_CNT; i++) {
+		for (j = 0; j < NSS_CAPWAPMGR_ACL_RULES_PER_LIST; j++) {
+			if (global.acl_list[i].rule[j].uid == id) {
+				acl_rule = &global.acl_list[i].rule[j];
+				goto found;
+			}
+		}
+	}
+
+	nss_capwapmgr_warn("Invalid id: %u\n", id);
+	return NSS_CAPWAPMGR_FAILURE_DSCP_RULE_ID_INVALID;
+
+found:
+	if (!acl_rule->in_use) {
+		nss_capwapmgr_warn("Rule matching id: %d not in use\n", id);
+		return NSS_CAPWAPMGR_FAILURE_DSCP_RULE_ID_NOT_IN_USE;
+	}
+
+	dscp_value = acl_rule->dscp_value;
+	dscp_mask = acl_rule->dscp_mask;
+
+	/*
+	 * Reset all classification fields on cosmap table.
+	 */
+	cosmap.internal_pcp = 0;
+	cosmap.internal_dei = 0;
+	cosmap.internal_pri = 0;
+	cosmap.internal_dscp = 0;
+	cosmap.internal_dp = 0;
+
+	for (i = 0; i < NSS_CAPWAPMGR_DSCP_MAX; i++) {
+		if ((i & dscp_mask) != dscp_value) {
+			continue;
+		}
+
+		nss_capwapmgr_trace("dscpmap: resetting for dscp %u\n", i);
+		rv = fal_qos_cosmap_dscp_set(dev_id, group_id, i, &cosmap);
+		if (rv != SW_OK) {
+			nss_capwapmgr_warn("Failed to reset cosmap for dscp %d - code: %d\n", i, rv);
+			return NSS_CAPWAPMGR_FAILURE_DSCP_RULE_DELETE_FAILED;
+		}
+	}
+
+	/*
+	 * Since we use 2 ACL entries per rule (i.e. v4/v6) we multiply by
+	 * two to get rule_ids.
+	 */
+	v4_rule_id = acl_rule->rule_id * 2;
+	v6_rule_id = v4_rule_id + 1;
+	list_id = NSS_CAPWAPMGR_ACL_LIST_START + acl_rule->list_id;
+
+	rv = fal_acl_rule_delete(dev_id, list_id, v6_rule_id, rule_nr);
+	if (rv != SW_OK) {
+		nss_capwapmgr_warn("Failed to del ACL v6_rule %d from list %d - code: %d\n", v6_rule_id, list_id, rv);
+		return NSS_CAPWAPMGR_FAILURE_DSCP_RULE_DELETE_FAILED;
+	}
+
+	rv = fal_acl_rule_delete(dev_id, list_id, v4_rule_id, rule_nr);
+	if (rv != SW_OK) {
+		nss_capwapmgr_warn("Failed to del ACL v4_rule %d from list %d - code: %d\n", v4_rule_id, list_id, rv);
+		return NSS_CAPWAPMGR_FAILURE_DSCP_RULE_DELETE_FAILED;
+	}
+
+	acl_rule->in_use = false;
+	return NSS_CAPWAPMGR_SUCCESS;
+}
+EXPORT_SYMBOL(nss_capwapmgr_dscp_rule_destroy);
+
+/*
+ * nss_capwapmgr_dscp_rule_create()
+ *	API to prioritize packets based on DSCP.
+ */
+nss_capwapmgr_status_t nss_capwapmgr_dscp_rule_create(uint8_t dscp_value, uint8_t dscp_mask, uint8_t pri, uint8_t *id)
+{
+	sw_error_t rv;
+	fal_qos_cosmap_t cosmap;
+	fal_qos_cosmap_t *orig_cosmap;
+	fal_acl_rule_t *acl_rule;
+	uint8_t dev_id = NSS_CAPWAPMGR_DEV_ID;
+	uint8_t group_id = NSS_CAPWAPMGR_GROUP_ID;
+	uint8_t rule_nr = NSS_CAPWAPMGR_RULE_NR;
+	uint8_t list_id, v4_rule_id, v6_rule_id;
+	uint8_t lid, rid, i, j;
+	int8_t err, fail_dscp;
+	int8_t uid = -1;
+
+	nss_capwapmgr_info("Setting priority %u for dscp %u mask %u\n", pri, dscp_value, dscp_mask);
+
+	orig_cosmap = kzalloc(NSS_CAPWAPMGR_DSCP_MAX * sizeof(*orig_cosmap), GFP_KERNEL);
+	if (!orig_cosmap) {
+		nss_capwapmgr_warn("Failed to alloc memory for orig_cosmap\n");
+		return NSS_CAPWAPMGR_FAILURE_MEM_UNAVAILABLE;
+	}
+
+	acl_rule = kzalloc(sizeof(*acl_rule), GFP_KERNEL);
+	if (!acl_rule) {
+		nss_capwapmgr_warn("Failed to alloc memory for acl_rule\n");
+		kfree(orig_cosmap);
+		return NSS_CAPWAPMGR_FAILURE_MEM_UNAVAILABLE;
+	}
+
+	/*
+	 * Get an empty acl rule.
+	 */
+	for (i = 0; i < NSS_CAPWAPMGR_ACL_LIST_CNT; i++) {
+		for (j = 0; j < NSS_CAPWAPMGR_ACL_RULES_PER_LIST; j++) {
+			if (global.acl_list[i].rule[j].in_use) {
+				continue;
+			}
+
+			uid = global.acl_list[i].rule[j].uid;
+			rid = global.acl_list[i].rule[j].rule_id;
+			lid = global.acl_list[i].rule[j].list_id;
+			goto found;
+		}
+	}
+
+found:
+	if (uid < 0) {
+		nss_capwapmgr_warn("No free ACL rules available\n");
+		err = NSS_CAPWAPMGR_FAILURE_ACL_UNAVAILABLE;
+		goto fail1;
+	};
+
+	/*
+	 * Since we use 2 ACL entries per rule (i.e. v4/v6) we multiply rid by
+	 * two to get rule_id.
+	 */
+	v4_rule_id = rid * 2;
+	v6_rule_id = v4_rule_id + 1;
+	list_id = NSS_CAPWAPMGR_ACL_LIST_START + lid;
+
+	nss_capwapmgr_info("Using ACL rules: %d & %d from list: %d\n", v4_rule_id, v6_rule_id, list_id);
+
+	/*
+	 * Prioritize packets with the dscp value. For trustsec packets, we need to specify
+	 * the location of the dscp value with ACL configuration.
+	 * ACL rule always start from the L2 header. It will be trustsec header for our case.
+	 * We need two user defined profile to set beginning of the
+	 * Profile 0 is for start of the ethernet type.
+	 * Profile 1 is for the start of the ip header.
+	 */
+	rv = fal_acl_udf_profile_set(dev_id, FAL_ACL_UDF_NON_IP, 0, FAL_ACL_UDF_TYPE_L3, NSS_CAPWAPMGR_ETH_HDR_OFFSET);
+	if (rv != SW_OK) {
+		nss_capwapmgr_warn("Failed to create UDF 0 Map - code: %d\n", rv);
+		err = NSS_CAPWAPMGR_FAILURE_CREATE_UDF_PROFILE;
+		goto fail1;
+	}
+
+	rv = fal_acl_udf_profile_set(dev_id, FAL_ACL_UDF_NON_IP, 1, FAL_ACL_UDF_TYPE_L3, NSS_CAPWAPMGR_IPV4_OFFSET);
+	if (rv != SW_OK) {
+		nss_capwapmgr_warn("Failed to create UDF 1 Map - code: %d\n", rv);
+		err = NSS_CAPWAPMGR_FAILURE_CREATE_UDF_PROFILE;
+		goto fail1;
+	}
+
+	acl_rule->rule_type = FAL_ACL_RULE_MAC;
+
+	/*
+	 * Sets valid flags for the acl rule.
+	 * Following rules are valid:
+	 * - Ethernet type
+	 * - User defined field 0. Correspond to ethernet type (ipv4/ipv6)
+	 * - User defined field 1. Correspond to DSCP value (dscp_value)
+	 */
+	FAL_FIELD_FLG_SET(acl_rule->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+	FAL_FIELD_FLG_SET(acl_rule->field_flg, FAL_ACL_FIELD_UDF0);
+	FAL_FIELD_FLG_SET(acl_rule->field_flg, FAL_ACL_FIELD_UDF1);
+	FAL_ACTION_FLG_SET(acl_rule->action_flg, FAL_ACL_ACTION_PERMIT);
+	FAL_ACTION_FLG_SET(acl_rule->action_flg, FAL_ACL_ACTION_ENQUEUE_PRI);
+
+	/*
+	 * Set common parameters for ipv4/ipv6
+	 */
+	acl_rule->ethtype_val = NSS_CAPWAPMGR_ETH_TYPE_TRUSTSEC;
+	acl_rule->ethtype_mask = NSS_CAPWAPMGR_ETH_TYPE_MASK;
+	acl_rule->udf0_op = FAL_ACL_FIELD_MASK;
+	acl_rule->udf1_op = FAL_ACL_FIELD_MASK;
+	acl_rule->enqueue_pri = pri;
+
+	/*
+	 * Create ACL rule for IPv4
+	 */
+	acl_rule->udf0_val = NSS_CAPWAPMGR_ETH_TYPE_IPV4;
+	acl_rule->udf0_mask = NSS_CAPWAPMGR_ETH_TYPE_MASK;
+	acl_rule->udf1_val = dscp_value << NSS_CAPWAPMGR_DSCP_MASK_IPV4_SHIFT;
+	acl_rule->udf1_mask = dscp_mask << NSS_CAPWAPMGR_DSCP_MASK_IPV4_SHIFT;
+
+	rv = fal_acl_rule_query(dev_id, list_id, v4_rule_id, acl_rule);
+	if (rv != SW_NOT_FOUND) {
+		nss_capwapmgr_warn("ACL rule already exist for list_id: %u, rule_id: %u - code: %d\n", list_id, v4_rule_id, rv);
+		err = NSS_CAPWAPMGR_FAILURE_ACL_RULE_ALREADY_EXIST;
+		goto fail1;
+	}
+
+	rv = fal_acl_list_unbind(dev_id, list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORTBITMAP, NSS_CAPWAPMGR_BIND_BITMAP);
+	if (rv != SW_OK) {
+		nss_capwapmgr_warn("Failed to unbind list: %d - code: %d\n", list_id, rv);
+		err = NSS_CAPWAPMGR_FAILURE_ADD_ACL_RULE;
+		goto fail1;
+	}
+
+	rv = fal_acl_rule_add(dev_id, list_id, v4_rule_id, rule_nr, acl_rule);
+	if (rv != SW_OK) {
+		nss_capwapmgr_warn("Failed to add ACL v4_rule: %d - code: %d\n", rv, v4_rule_id);
+		err = NSS_CAPWAPMGR_FAILURE_ADD_ACL_RULE;
+		goto fail1;
+	}
+
+	/*
+	 * Create ACL rule for IPv6
+	 */
+	acl_rule->udf0_val = NSS_CAPWAPMGR_ETH_TYPE_IPV6;
+	acl_rule->udf0_mask = NSS_CAPWAPMGR_ETH_TYPE_MASK;
+	acl_rule->udf1_val = dscp_value << NSS_CAPWAPMGR_DSCP_MASK_IPV6_SHIFT;
+	acl_rule->udf1_mask = dscp_mask << NSS_CAPWAPMGR_DSCP_MASK_IPV6_SHIFT;
+
+	rv = fal_acl_rule_add(dev_id, list_id, v6_rule_id, rule_nr, acl_rule);
+	if (rv != SW_OK) {
+		nss_capwapmgr_warn("Failed to add ACL v6_rule: %d - code: %d\n", rv, v6_rule_id);
+		err = NSS_CAPWAPMGR_FAILURE_ADD_ACL_RULE;
+		goto fail2;
+	}
+
+	/*
+	 * Bind list to all ethernet ports
+	 */
+	rv = fal_acl_list_bind(dev_id, list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORTBITMAP, NSS_CAPWAPMGR_BIND_BITMAP);
+	if (rv != SW_OK) {
+		nss_capwapmgr_warn("Failed to bind ACL list: %d - code: %d\n", list_id, rv);
+		err = NSS_CAPWAPMGR_FAILURE_BIND_ACL_LIST;
+		goto fail3;
+	}
+
+	/*
+	 * Set ACL as in_use and save dscp value and mask.
+	 */
+	global.acl_list[lid].rule[rid].in_use = true;
+	global.acl_list[lid].rule[rid].dscp_value = dscp_value;
+	global.acl_list[lid].rule[rid].dscp_mask = dscp_mask;
+
+	/*
+	 * Prioritize packets with the dscp value is dscp_value for non trustsec packets.
+	 * These packets do not require any ACL Rule.
+	 */
+	cosmap.internal_pcp = 0;
+	cosmap.internal_dei = 0;
+	cosmap.internal_pri = pri;
+	cosmap.internal_dscp = 0;
+	cosmap.internal_dp = 0;
+	for (i = 0; i < NSS_CAPWAPMGR_DSCP_MAX; i++) {
+		if ((i & dscp_mask) != dscp_value) {
+			continue;
+		}
+
+		rv = fal_qos_cosmap_dscp_get(dev_id, group_id, i, &orig_cosmap[i]);
+		if (rv != SW_OK) {
+			nss_capwapmgr_warn("dscpmap: failed to get cosmap for dscp %d\n", i);
+			err = NSS_CAPWAPMGR_FAILURE_CONFIGURE_DSCP_MAP;
+			goto fail4;
+		}
+
+		nss_capwapmgr_trace("dscpmap: setting priority %u for dscp %u\n", pri, i);
+		rv = fal_qos_cosmap_dscp_set(dev_id, group_id, i, &cosmap);
+		if (rv != SW_OK) {
+			nss_capwapmgr_warn("Failed to configure cosmap for dscp %d - code: %d\n", i, rv);
+			err = NSS_CAPWAPMGR_FAILURE_CONFIGURE_DSCP_MAP;
+			goto fail4;
+		}
+	}
+
+	kfree(acl_rule);
+	kfree(orig_cosmap);
+
+	*id = uid;
+
+	return NSS_CAPWAPMGR_SUCCESS;
+
+fail4:
+	fail_dscp = i;
+	for (i = 0; i < fail_dscp; i++) {
+		if ((i & dscp_mask) != dscp_value) {
+			continue;
+		}
+
+		nss_capwapmgr_trace("dscpmap: resetting to priority %u for dscp %u\n", orig_cosmap[i].internal_pri, i);
+		rv = fal_qos_cosmap_dscp_set(dev_id, group_id, i, &orig_cosmap[i]);
+		if (rv != SW_OK) {
+			nss_capwapmgr_warn("Failed to reset cosmap for dscp %d - code: %d\n", i, rv);
+		}
+	}
+
+fail3:
+	rv = fal_acl_rule_delete(dev_id, list_id, v6_rule_id, rule_nr);
+	if (rv != SW_OK) {
+		nss_capwapmgr_warn("Failed to del ACL v6_rule %d from list %d - code: %d\n", v6_rule_id, list_id, rv);
+	}
+
+fail2:
+	rv = fal_acl_rule_delete(dev_id, list_id, v4_rule_id, rule_nr);
+	if (rv != SW_OK) {
+		nss_capwapmgr_warn("Failed to del ACL v4_rule %d from list %d - code: %d\n", v4_rule_id, list_id, rv);
+	}
+
+fail1:
+	kfree(orig_cosmap);
+	kfree(acl_rule);
+
+	return err;
+}
+EXPORT_SYMBOL(nss_capwapmgr_dscp_rule_create);
+
+/*
+ * nss_capwapmgr_configure_dtls
+ *	Enable or disable DTLS of a capwap tunnel
+ */
+nss_capwapmgr_status_t nss_capwapmgr_configure_dtls(struct net_device *dev, uint8_t tunnel_id, uint8_t enable_dtls, struct nss_dtlsmgr_config *in_data)
+{
+	struct nss_capwapmgr_priv *priv;
+	struct nss_capwap_msg capwapmsg_inner, capwapmsg_outer;
+	struct nss_capwapmgr_tunnel *t;
+	struct nss_ipv4_destroy v4;
+	struct nss_ipv6_destroy v6;
+	nss_tx_status_t nss_status = NSS_TX_SUCCESS;
+	nss_capwapmgr_status_t status;
+	uint32_t ip_if_num, dtls_enabled, outer_trustsec_enabled;
+
+	dev_hold(dev);
+	t = nss_capwapmgr_verify_tunnel_param(dev, tunnel_id);
+	if (!t) {
+		nss_capwapmgr_warn("%px: can't find tunnel: %d\n", dev, tunnel_id);
+		dev_put(dev);
+		return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+	}
+
+	outer_trustsec_enabled = t->capwap_rule.enabled_features & NSS_CAPWAPMGR_FEATURE_OUTER_TRUSTSEC_ENABLED;
+	dtls_enabled = t->capwap_rule.enabled_features & NSS_CAPWAPMGR_FEATURE_DTLS_ENABLED;
+	if ((enable_dtls && dtls_enabled) || (!enable_dtls && !dtls_enabled)) {
+		nss_capwapmgr_warn("%px: nothing changed for tunnel: %d\n", dev, tunnel_id);
+		dev_put(dev);
+		return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+	}
+
+	/*
+	 * We don't allow configuring dtls on tunnel if it's still
+	 * enabled.
+	 */
+	if (t->tunnel_state & NSS_CAPWAPMGR_TUNNEL_STATE_ENABLED) {
+		nss_capwapmgr_warn("%px: tunnel %d is already enabled\n", dev, tunnel_id);
+		dev_put(dev);
+		return NSS_CAPWAPMGR_FAILURE_TUNNEL_ENABLED;
+	}
+
+	/*
+	 * Prepare DTLS configure message
+	 */
+	memset(&capwapmsg_inner, 0, sizeof(struct nss_capwap_msg));
+	nss_capwap_msg_init(&capwapmsg_inner, t->if_num_inner, NSS_CAPWAP_MSG_TYPE_DTLS,
+		sizeof(struct nss_capwap_dtls_msg), nss_capwapmgr_msg_event_receive, dev);
+
+	memset(&capwapmsg_outer, 0, sizeof(struct nss_capwap_msg));
+	nss_capwap_msg_init(&capwapmsg_outer, t->if_num_outer, NSS_CAPWAP_MSG_TYPE_DTLS,
+		sizeof(struct nss_capwap_dtls_msg), nss_capwapmgr_msg_event_receive, dev);
+
+
+	if (!enable_dtls) {
+		nss_capwapmgr_info("%px disabling DTLS for tunnel: %d\n", dev, tunnel_id);
+
+		ip_if_num = nss_capwap_ifnum_with_core_id(t->if_num_outer);
+		capwapmsg_inner.msg.dtls.enable = 0;
+		capwapmsg_inner.msg.dtls.dtls_inner_if_num = t->capwap_rule.dtls_inner_if_num;
+		capwapmsg_inner.msg.dtls.mtu_adjust = 0;
+
+		capwapmsg_outer.msg.dtls.enable = 0;
+
+		/*
+		 * Unconfigure trustsec tx first
+		 */
+		if (outer_trustsec_enabled) {
+			nss_status = nss_trustsec_tx_unconfigure_sgt(t->capwap_rule.dtls_inner_if_num, t->capwap_rule.outer_sgt_value);
+			if (nss_status != NSS_TX_SUCCESS) {
+				nss_capwapmgr_warn("%px: unconfigure trustsec_tx failed\n", dev);
+				dev_put(dev);
+				return NSS_CAPWAPMGR_FAILURE_UNCONFIGURE_TRUSTSEC_TX;
+			}
+		}
+	} else {
+		nss_capwapmgr_info("%px enabling DTLS for tunnel: %d\n", dev, tunnel_id);
+
+		if (!t->capwap_rule.dtls_inner_if_num) {
+			/*
+			 * Create a DTLS node, we only validate caller is providing a DTLS
+			 * configuration structure, the correctness of these settings are
+			 * validated by dtlsmgr
+			 */
+			if (!in_data) {
+				nss_capwapmgr_info("%px: dtls in_data required to create dtls tunnel\n", dev);
+				dev_put(dev);
+				return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+			}
+
+			/*
+			 * We only support the METADATA mode for pure DTLS tunnels; in CAPWAP-DTLS
+			 * the offload will not send the packets starting with Metadata. We need to
+			 * ensure that the user does not configure this mode accidentally.
+			 */
+			in_data->flags &= ~NSS_DTLSMGR_ENCAP_METADATA;
+			in_data->decap.nexthop_ifnum = nss_capwap_ifnum_with_core_id(t->if_num_outer);
+
+			t->dtls_dev = nss_dtlsmgr_session_create(in_data);
+			if (!t->dtls_dev) {
+				nss_capwapmgr_warn("%px: cannot create DTLS session\n", dev);
+				dev_put(dev);
+				return NSS_CAPWAPMGR_FAILURE_DI_ALLOC_FAILED;
+			}
+
+			/* Store the DTLS encap and decap interface numbers */
+			t->capwap_rule.dtls_inner_if_num = nss_dtlsmgr_get_interface(t->dtls_dev,
+										     NSS_DTLSMGR_INTERFACE_TYPE_INNER);
+			t->capwap_rule.mtu_adjust = t->dtls_dev->needed_headroom + t->dtls_dev->needed_tailroom;
+			nss_capwapmgr_info("%px: created dtls node for tunnel: %d if_num: %d mtu_adjust: %d\n",
+					   dev, tunnel_id, t->capwap_rule.dtls_inner_if_num, t->capwap_rule.mtu_adjust);
+		}
+
+		ip_if_num = nss_dtlsmgr_get_interface(t->dtls_dev, NSS_DTLSMGR_INTERFACE_TYPE_OUTER);
+
+		capwapmsg_inner.msg.dtls.enable = 1;
+		capwapmsg_inner.msg.dtls.dtls_inner_if_num = t->capwap_rule.dtls_inner_if_num;
+		capwapmsg_inner.msg.dtls.mtu_adjust = t->capwap_rule.mtu_adjust;
+
+		capwapmsg_outer.msg.dtls.enable = 1;
+
+		/*
+		 * Unconfigure trustsec tx first
+		 */
+		if (outer_trustsec_enabled) {
+			nss_status = nss_trustsec_tx_unconfigure_sgt(t->if_num_outer, t->capwap_rule.outer_sgt_value);
+			if (nss_status != NSS_TX_SUCCESS) {
+				nss_capwapmgr_warn("%px: unconfigure trustsec_tx failed\n", dev);
+				dev_put(dev);
+				return NSS_CAPWAPMGR_FAILURE_UNCONFIGURE_TRUSTSEC_TX;
+			}
+		}
+	}
+
+	/*
+	 * Re-configure trustsec_tx
+	 */
+	if (outer_trustsec_enabled) {
+		nss_status = nss_trustsec_tx_configure_sgt(ip_if_num, t->capwap_rule.gmac_ifnum, t->capwap_rule.outer_sgt_value);
+		if (nss_status != NSS_TX_SUCCESS) {
+			nss_capwapmgr_warn("%px: configure trustsec_tx failed\n", dev);
+			dev_put(dev);
+			return NSS_CAPWAPMGR_FAILURE_CONFIGURE_TRUSTSEC_TX;
+		}
+	}
+
+	priv = netdev_priv(dev);
+
+	/*
+	 * Recreate ipv4/v6 rules with the new interface number
+	 */
+	if (t->capwap_rule.l3_proto == NSS_CAPWAP_TUNNEL_IPV4) {
+		if (t->tunnel_state & NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED) {
+			v4.protocol = IPPROTO_UDP;
+			v4.src_ip = t->ip_rule.v4.src_ip;
+			v4.dest_ip = t->ip_rule.v4.dest_ip;
+			v4.src_port = t->ip_rule.v4.src_port;
+			v4.dest_port = t->ip_rule.v4.dest_port;
+			nss_status = nss_capwapmgr_unconfigure_ipv4_rule(&v4);
+			if (nss_status != NSS_TX_SUCCESS) {
+				nss_capwapmgr_warn("%px: unconfigure ipv4 rule failed : %d\n", dev, nss_status);
+				dev_put(dev);
+				return NSS_CAPWAPMGR_FAILURE_IP_DESTROY_RULE;
+			}
+			t->tunnel_state &= ~NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED;
+		}
+
+		t->ip_rule.v4.dest_interface_num = ip_if_num;
+		nss_status = nss_capwapmgr_configure_ipv4(&t->ip_rule.v4, 0, 0);
+	} else {
+		if (t->tunnel_state & NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED) {
+			if (t->capwap_rule.which_udp == NSS_CAPWAP_TUNNEL_UDP) {
+				v6.protocol = IPPROTO_UDP;
+			} else {
+				v6.protocol = IPPROTO_UDPLITE;
+			}
+
+			v6.src_ip[0] = t->ip_rule.v6.src_ip[0];
+			v6.src_ip[1] = t->ip_rule.v6.src_ip[1];
+			v6.src_ip[2] = t->ip_rule.v6.src_ip[2];
+			v6.src_ip[3] = t->ip_rule.v6.src_ip[3];
+
+			v6.dest_ip[0] = t->ip_rule.v6.dest_ip[0];
+			v6.dest_ip[1] = t->ip_rule.v6.dest_ip[1];
+			v6.dest_ip[2] = t->ip_rule.v6.dest_ip[2];
+			v6.dest_ip[3] = t->ip_rule.v6.dest_ip[3];
+
+			v6.src_port = t->ip_rule.v6.src_port;
+			v6.dest_port = t->ip_rule.v6.dest_port;
+			nss_status = nss_capwapmgr_unconfigure_ipv6_rule(&v6);
+			if (nss_status != NSS_TX_SUCCESS) {
+				nss_capwapmgr_warn("%px: unconfigure ipv6 rule failed : %d\n", dev, nss_status);
+				dev_put(dev);
+				return NSS_CAPWAPMGR_FAILURE_IP_DESTROY_RULE;
+			}
+			t->tunnel_state &= ~NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED;
+		}
+		t->ip_rule.v6.dest_interface_num = ip_if_num;
+		nss_status = nss_capwapmgr_configure_ipv6(&t->ip_rule.v6, 0, 0);
+	}
+
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_capwapmgr_warn("%px: configure ip rule failed : %d\n", dev, nss_status);
+		dev_put(dev);
+		return NSS_CAPWAPMGR_FAILURE_IP_RULE;
+	}
+
+	/*
+	 * Now configure capwap dtls
+	 */
+	t->tunnel_state |= NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED;
+	status = nss_capwapmgr_tx_msg_sync(priv->nss_ctx, dev, &capwapmsg_inner);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_capwapmgr_warn("%px: configure DTLS failed for inner node: %d\n", dev, status);
+		dev_put(dev);
+		return status;
+	}
+
+	status = nss_capwapmgr_tx_msg_sync(priv->nss_ctx, dev, &capwapmsg_outer);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_capwapmgr_warn("%px: configure DTLS failed for outer node: %d\n", dev, status);
+		dev_put(dev);
+		return status;
+	}
+
+	if (enable_dtls) {
+		t->capwap_rule.enabled_features |= NSS_CAPWAPMGR_FEATURE_DTLS_ENABLED;
+	} else {
+		t->capwap_rule.enabled_features &= ~NSS_CAPWAPMGR_FEATURE_DTLS_ENABLED;
+	}
+	dev_put(dev);
+	return NSS_CAPWAPMGR_SUCCESS;
+}
+EXPORT_SYMBOL(nss_capwapmgr_configure_dtls);
+
+/*
+ * nss_capwapmgr_verify_dtls_rekey_param()
+ *	Validate the rekey param for a DTLS tunnel and return the DTLS netdevice
+ *
+ *  The caller should hold the reference on the net device before calling.
+ */
+static inline struct net_device *nss_capwapmgr_verify_dtls_rekey_param(struct net_device *dev, uint8_t tunnel_id,
+								 struct nss_dtlsmgr_config_update *udata)
+{
+	struct nss_capwapmgr_tunnel *t;
+
+	if (!udata) {
+		nss_capwapmgr_info("%px: dtls session update data required\n", dev);
+		return NULL;
+	}
+
+	t = nss_capwapmgr_verify_tunnel_param(dev, tunnel_id);
+	if (!t) {
+		nss_capwapmgr_warn("%px: can't find tunnel: %d\n", dev, tunnel_id);
+		return NULL;
+	}
+
+	if (!(t->capwap_rule.enabled_features & NSS_CAPWAPMGR_FEATURE_DTLS_ENABLED)) {
+		nss_capwapmgr_warn("%px: tunnel does not enable DTLS: %d\n", dev, tunnel_id);
+		return NULL;
+	}
+
+	return t->dtls_dev;
+}
+
+/*
+ * nss_capwapmgr_dtls_rekey_rx_cipher_update()
+ *	Update the rx cipher key for an DTLS tunnel
+ */
+nss_capwapmgr_status_t nss_capwapmgr_dtls_rekey_rx_cipher_update(struct net_device *dev, uint8_t tunnel_id,
+								 struct nss_dtlsmgr_config_update *udata)
+{
+	struct net_device *dtls_ndev;
+
+	dev_hold(dev);
+	dtls_ndev = nss_capwapmgr_verify_dtls_rekey_param(dev, tunnel_id, udata);
+	dev_put(dev);
+
+	if (!dtls_ndev) {
+		goto fail;
+	}
+
+	/*
+	 * Calling dtlsmgr for rekey
+	 */
+	if (nss_dtlsmgr_session_update_decap(dtls_ndev, udata) != NSS_DTLSMGR_OK) {
+		goto fail;
+	}
+	return NSS_CAPWAPMGR_SUCCESS;
+
+fail:
+	nss_capwapmgr_warn("%px: tunnel: %d rekey rx cipher update failed\n", dtls_ndev, tunnel_id);
+	return NSS_CAPWAPMGR_FAILURE_INVALID_DTLS_CFG;
+}
+EXPORT_SYMBOL(nss_capwapmgr_dtls_rekey_rx_cipher_update);
+
+/*
+ * nss_capwapmgr_dtls_rekey_tx_cipher_update()
+ *	Update the tx cipher key for an DTLS tunnel
+ */
+nss_capwapmgr_status_t nss_capwapmgr_dtls_rekey_tx_cipher_update(struct net_device *dev, uint8_t tunnel_id,
+								 struct nss_dtlsmgr_config_update *udata)
+{
+	struct net_device *dtls_ndev;
+
+	dev_hold(dev);
+	dtls_ndev = nss_capwapmgr_verify_dtls_rekey_param(dev, tunnel_id, udata);
+	dev_put(dev);
+
+	if (!dtls_ndev) {
+		goto fail;
+	}
+
+	/*
+	 * Calling dtlsmgr for rekey
+	 */
+	if (nss_dtlsmgr_session_update_encap(dtls_ndev, udata) != NSS_DTLSMGR_OK) {
+		goto fail;
+	}
+	return NSS_CAPWAPMGR_SUCCESS;
+
+fail:
+	nss_capwapmgr_warn("%px: tunnel: %d rekey rx cipher update failed\n", dtls_ndev, tunnel_id);
+	return NSS_CAPWAPMGR_FAILURE_INVALID_DTLS_CFG;
+}
+EXPORT_SYMBOL(nss_capwapmgr_dtls_rekey_tx_cipher_update);
+
+/*
+ * nss_capwapmgr_dtls_rekey_rx_cipher_switch()
+ *	Switch the rx cipher key for an DTLS tunnel
+ */
+nss_capwapmgr_status_t nss_capwapmgr_dtls_rekey_rx_cipher_switch(struct net_device *dev, uint8_t tunnel_id)
+{
+	struct nss_capwapmgr_tunnel *t;
+	nss_capwapmgr_status_t status = NSS_CAPWAPMGR_SUCCESS;
+
+	dev_hold(dev);
+	t = nss_capwapmgr_verify_tunnel_param(dev, tunnel_id);
+	if (!t) {
+		nss_capwapmgr_warn("%px: can't find tunnel: %d\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+	if (!(t->capwap_rule.enabled_features & NSS_CAPWAPMGR_FEATURE_DTLS_ENABLED)) {
+		nss_capwapmgr_warn("%px: tunnel does not enable DTLS: %d\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+	/*
+	 * Calling dtlsmgr for rekey switch
+	 */
+	if (!nss_dtlsmgr_session_switch_decap(t->dtls_dev)) {
+		nss_capwapmgr_warn("%px: tunnel: %d rekey rx cipher switch failed\n", t->dtls_dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_INVALID_DTLS_CFG;
+	}
+
+done:
+	dev_put(dev);
+	return status;
+}
+EXPORT_SYMBOL(nss_capwapmgr_dtls_rekey_rx_cipher_switch);
+
+/*
+ * nss_capwapmgr_dtls_rekey_tx_cipher_switch()
+ *	Switch the tx cipher key for an DTLS tunnel
+ */
+nss_capwapmgr_status_t nss_capwapmgr_dtls_rekey_tx_cipher_switch(struct net_device *dev, uint8_t tunnel_id)
+{
+	struct nss_capwapmgr_tunnel *t;
+	nss_capwapmgr_status_t status = NSS_CAPWAPMGR_SUCCESS;
+
+	dev_hold(dev);
+	t = nss_capwapmgr_verify_tunnel_param(dev, tunnel_id);
+	if (!t) {
+		nss_capwapmgr_warn("%px: can't find tunnel: %d\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+	if (!(t->capwap_rule.enabled_features & NSS_CAPWAPMGR_FEATURE_DTLS_ENABLED)) {
+		nss_capwapmgr_warn("%px: tunnel does not enable DTLS: %d\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+	/*
+	 * Calling dtlsmgr for rekey switch
+	 */
+	if (!nss_dtlsmgr_session_switch_encap(t->dtls_dev)) {
+		nss_capwapmgr_warn("%px: tunnel: %d rekey tx cipher switch failed\n", t->dtls_dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_INVALID_DTLS_CFG;
+	}
+
+done:
+	dev_put(dev);
+	return status;
+}
+EXPORT_SYMBOL(nss_capwapmgr_dtls_rekey_tx_cipher_switch);
+
+/*
+ * nss_capwapmgr_change_version()
+ *	Change CAPWAP version
+ */
+
+nss_capwapmgr_status_t nss_capwapmgr_change_version(struct net_device *dev, uint8_t tunnel_id, uint8_t ver)
+{
+	struct nss_capwapmgr_priv *priv;
+	struct nss_capwap_msg capwapmsg;
+	struct nss_capwapmgr_tunnel *t;
+	nss_capwapmgr_status_t status = NSS_CAPWAPMGR_SUCCESS;
+
+	dev_hold(dev);
+	t = nss_capwapmgr_verify_tunnel_param(dev, tunnel_id);
+	if (!t) {
+		nss_capwapmgr_warn("%px: can't find tunnel: %d\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+	if (ver > NSS_CAPWAP_VERSION_V2) {
+		nss_capwapmgr_warn("%px: un-supported Version: %d\n", dev, ver);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+	priv = netdev_priv(dev);
+
+	/*
+	 * Prepare the tunnel configuration parameter to send to NSS FW
+	 */
+	memset(&capwapmsg, 0, sizeof(struct nss_capwap_msg));
+
+	/*
+	 * Send CAPWAP data tunnel command to NSS
+	 */
+	nss_capwap_msg_init(&capwapmsg, t->if_num_inner, NSS_CAPWAP_MSG_TYPE_VERSION,
+		sizeof(struct nss_capwap_version_msg), nss_capwapmgr_msg_event_receive, dev);
+	capwapmsg.msg.version.version = ver;
+	status = nss_capwapmgr_tx_msg_sync(priv->nss_ctx, dev, &capwapmsg);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_capwapmgr_warn("%px: Update Path MTU Tunnel error : %d \n", dev, status);
+	}
+
+done:
+	dev_put(dev);
+	return status;
+}
+EXPORT_SYMBOL(nss_capwapmgr_change_version);
+
+/*
+ * nss_capwapmgr_enable_tunnel()
+ *	API for enabling a data tunnel
+ */
+nss_capwapmgr_status_t nss_capwapmgr_enable_tunnel(struct net_device *dev, uint8_t tunnel_id)
+{
+	struct nss_capwapmgr_priv *priv;
+	struct nss_capwapmgr_tunnel *t;
+	nss_capwapmgr_status_t status = NSS_CAPWAPMGR_SUCCESS;
+
+	dev_hold(dev);
+	t = nss_capwapmgr_verify_tunnel_param(dev, tunnel_id);
+	if (!t) {
+		nss_capwapmgr_warn("%px: can't find tunnel: %d\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+	if (t->tunnel_state & NSS_CAPWAPMGR_TUNNEL_STATE_ENABLED) {
+		nss_capwapmgr_warn("%px: tunnel %d is already enabled\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_TUNNEL_ENABLED;
+		goto done;
+	}
+
+	priv = netdev_priv(dev);
+	nss_capwapmgr_info("%px: Inner:%d Outer:%d. Tunnel enable is being called\n", dev, t->if_num_inner, t->if_num_outer);
+
+	status = nss_capwapmgr_tx_msg_enable_tunnel(priv->nss_ctx, dev, t->if_num_inner,t->if_num_outer);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		goto done;
+	}
+
+	status = nss_capwapmgr_tx_msg_enable_tunnel(priv->nss_ctx, dev, t->if_num_outer,t->if_num_inner);
+	if(status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_capwapmgr_tunnel_action(priv->nss_ctx, dev, t->if_num_inner,NSS_CAPWAP_MSG_TYPE_DISABLE_TUNNEL);
+		goto done;
+	}
+
+	t->tunnel_state |= NSS_CAPWAPMGR_TUNNEL_STATE_ENABLED;
+
+done:
+	dev_put(dev);
+	return status;
+}
+EXPORT_SYMBOL(nss_capwapmgr_enable_tunnel);
+
+/*
+ * nss_capwapmgr_disable_tunnel()
+ *	API for disabling a data tunnel
+ */
+nss_capwapmgr_status_t nss_capwapmgr_disable_tunnel(struct net_device *dev, uint8_t tunnel_id)
+{
+	struct nss_capwapmgr_priv *priv;
+	struct nss_capwapmgr_tunnel *t;
+	nss_capwapmgr_status_t status = NSS_CAPWAPMGR_SUCCESS;
+
+	dev_hold(dev);
+	t = nss_capwapmgr_verify_tunnel_param(dev, tunnel_id);
+	if (!t) {
+		nss_capwapmgr_warn("%px: can't find tunnel: %d\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+	if (!(t->tunnel_state & NSS_CAPWAPMGR_TUNNEL_STATE_ENABLED)) {
+		nss_capwapmgr_warn("%px: tunnel %d is already disabled\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_TUNNEL_DISABLED;
+		goto done;
+	}
+
+	priv = netdev_priv(dev);
+	nss_capwapmgr_info("%px: Inner:%d Outer:%d. Tunnel disable is being called\n", dev, t->if_num_inner, t->if_num_outer);
+
+	status = nss_capwapmgr_tunnel_action(priv->nss_ctx, dev, t->if_num_inner,NSS_CAPWAP_MSG_TYPE_DISABLE_TUNNEL);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		status = NSS_CAPWAPMGR_FAILURE_TUNNEL_DISABLED;
+		nss_capwapmgr_warn("%px: tunnel %d disable failed\n", dev, tunnel_id);
+		goto done;
+	}
+
+	status = nss_capwapmgr_tunnel_action(priv->nss_ctx, dev, t->if_num_outer,NSS_CAPWAP_MSG_TYPE_DISABLE_TUNNEL);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_capwapmgr_warn("%px: tunnel %d disable failed\n", dev, tunnel_id);
+		nss_capwapmgr_tx_msg_enable_tunnel(priv->nss_ctx, dev, t->if_num_inner, t->if_num_outer);
+		goto done;
+	}
+
+	t->tunnel_state &= ~NSS_CAPWAPMGR_TUNNEL_STATE_ENABLED;
+
+done:
+	dev_put(dev);
+	return status;
+}
+EXPORT_SYMBOL(nss_capwapmgr_disable_tunnel);
+
+/*
+ * nss_capwapmgr_tunnel_create_common()
+ *	Common handling for creating IPv4 or IPv6 tunnel
+ */
+static nss_capwapmgr_status_t nss_capwapmgr_tunnel_create_common(struct net_device *dev, uint8_t tunnel_id,
+	struct nss_ipv4_create *v4, struct nss_ipv6_create *v6, struct nss_capwap_rule_msg *capwap_rule, struct nss_dtlsmgr_config *in_data)
+{
+	struct nss_capwapmgr_priv *priv;
+	struct nss_capwapmgr_tunnel *t;
+	nss_capwapmgr_status_t status = NSS_CAPWAPMGR_SUCCESS;
+	int32_t capwap_if_num_inner, capwap_if_num_outer, forward_if_num;
+	uint16_t type_flags = 0;
+	nss_tx_status_t nss_status = NSS_TX_SUCCESS;
+	uint32_t dtls_enabled = capwap_rule->enabled_features & NSS_CAPWAPMGR_FEATURE_DTLS_ENABLED;
+	uint32_t outer_trustsec_enabled = capwap_rule->enabled_features & NSS_CAPWAPMGR_FEATURE_OUTER_TRUSTSEC_ENABLED;
+
+	if (!v4 && !v6) {
+		nss_capwapmgr_warn("%px: invalid ip create rule for tunnel: %d\n", dev, tunnel_id);
+		return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+	}
+
+	if (tunnel_id > NSS_CAPWAPMGR_MAX_TUNNELS) {
+		nss_capwapmgr_warn("%px: invalid tunnel_id: %d max: NSS_CAPWAPMGR_MAX_TUNNELS\n", dev, tunnel_id);
+		return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+	}
+
+	if (!(capwap_rule->l3_proto == NSS_CAPWAP_TUNNEL_IPV4 ||
+		capwap_rule->l3_proto == NSS_CAPWAP_TUNNEL_IPV6)) {
+		nss_capwapmgr_warn("%px: tunnel %d: wrong argument for l3_proto\n", dev, tunnel_id);
+		return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+	}
+
+	if (!(capwap_rule->which_udp == NSS_CAPWAP_TUNNEL_UDP ||
+		capwap_rule->which_udp == NSS_CAPWAP_TUNNEL_UDPLite)) {
+		nss_capwapmgr_warn("%px: tunnel %d: wrong argument for which_udp\n", dev, tunnel_id);
+		return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+	}
+
+	if (dtls_enabled && !in_data) {
+		nss_capwapmgr_warn("%px: need to supply in_data if DTLS is enabled\n", dev);
+		return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+	}
+
+	dev_hold(dev);
+	t = nss_capwapmgr_verify_tunnel_param(dev, tunnel_id);
+	if (t) {
+		nss_capwapmgr_warn("%px: tunnel: %d already created\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_TUNNEL_EXISTS;
+		goto done;
+	}
+
+	capwap_if_num_inner = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_HOST_INNER);
+	if (capwap_if_num_inner < 0) {
+		nss_capwapmgr_warn("%px: di returned error : %d\n", dev, capwap_if_num_inner);
+		status = NSS_CAPWAPMGR_FAILURE_DI_ALLOC_FAILED;
+		goto done;
+	}
+
+	if (nss_capwapmgr_register_with_nss(capwap_if_num_inner, dev) != NSS_CAPWAPMGR_SUCCESS) {
+		nss_capwapmgr_warn("%d: NSS CAPWAP register with NSS failed", capwap_if_num_inner);
+		status = NSS_CAPWAPMGR_FAILURE_REGISTER_NSS;
+		goto fail1;
+	}
+
+	capwap_if_num_outer = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_OUTER);
+	if (capwap_if_num_outer < 0) {
+		nss_capwapmgr_warn("%px: di returned error : %d\n", dev, capwap_if_num_outer);
+		status = NSS_CAPWAPMGR_FAILURE_DI_ALLOC_FAILED;
+		goto fail2;
+	}
+
+	if (nss_capwapmgr_register_with_nss(capwap_if_num_outer, dev) != NSS_CAPWAPMGR_SUCCESS) {
+		nss_capwapmgr_warn("%d: NSS CAPWAP register with NSS failed", capwap_if_num_outer);
+		status = NSS_CAPWAPMGR_FAILURE_REGISTER_NSS;
+		goto fail3;
+	}
+
+	if (!dtls_enabled) {
+		capwap_rule->mtu_adjust = 0;
+		capwap_rule->dtls_inner_if_num = 0;
+		forward_if_num = nss_capwap_ifnum_with_core_id(capwap_if_num_outer);
+	} else {
+		/*
+		 * We only support the METADATA mode for pure DTLS tunnels; in CAPWAP-DTLS
+		 * the offload will not send the packets starting with Metadata. We need to
+		 * ensure that the user does not configure this mode accidentally.
+		 */
+		in_data->flags &= ~NSS_DTLSMGR_ENCAP_METADATA;
+		in_data->decap.nexthop_ifnum = nss_capwap_ifnum_with_core_id(capwap_if_num_outer);
+
+		t->dtls_dev = nss_dtlsmgr_session_create(in_data);
+		if (!t->dtls_dev) {
+			nss_capwapmgr_warn("%px: NSS DTLS node alloc failed\n", dev);
+			status = NSS_CAPWAPMGR_FAILURE_DI_ALLOC_FAILED;
+			goto fail4;
+		}
+		capwap_rule->dtls_inner_if_num = nss_dtlsmgr_get_interface(t->dtls_dev, NSS_DTLSMGR_INTERFACE_TYPE_INNER);
+		forward_if_num = nss_dtlsmgr_get_interface(t->dtls_dev, NSS_DTLSMGR_INTERFACE_TYPE_OUTER);
+		capwap_rule->mtu_adjust = t->dtls_dev->needed_headroom + t->dtls_dev->needed_tailroom;
+	}
+
+	if (outer_trustsec_enabled) {
+		nss_capwapmgr_info("%px: configure TrustsecTx with sgt value: %x\n", dev, capwap_rule->outer_sgt_value);
+		if (v4) {
+			capwap_rule->gmac_ifnum = v4->src_interface_num;
+			nss_status = nss_trustsec_tx_configure_sgt(forward_if_num, v4->src_interface_num, capwap_rule->outer_sgt_value);
+			v4->src_interface_num = NSS_TRUSTSEC_TX_INTERFACE;
+		} else {
+			capwap_rule->gmac_ifnum = v6->src_interface_num;
+			nss_status = nss_trustsec_tx_configure_sgt(forward_if_num, v6->src_interface_num, capwap_rule->outer_sgt_value);
+			v6->src_interface_num = NSS_TRUSTSEC_TX_INTERFACE;
+		}
+		if (nss_status != NSS_TX_SUCCESS) {
+			nss_capwapmgr_warn("%px: configure trustsectx node failed\n", dev);
+			status = NSS_CAPWAPMGR_FAILURE_CONFIGURE_TRUSTSEC_TX;
+			goto fail5;
+		}
+	}
+
+	/*
+	 * We use type_flags to determine the correct header sizes
+	 * for a frame when encaping. CAPWAP processing node in the
+	 * NSS FW does not know anything about IP rule information.
+	 */
+	if (v4) {
+		if ((v4->out_vlan_tag[0] & 0xFFF) != 0xFFF) {
+			type_flags |= NSS_CAPWAP_RULE_CREATE_VLAN_CONFIGURED;
+		}
+
+		if (v4->flow_pppoe_if_exist) {
+			type_flags |= NSS_CAPWAP_RULE_CREATE_PPPOE_CONFIGURED;
+		}
+	} else {
+		if ((v6->out_vlan_tag[0] & 0xFFF) != 0xFFF) {
+			type_flags |= NSS_CAPWAP_RULE_CREATE_VLAN_CONFIGURED;
+		}
+
+		if (v6->flow_pppoe_if_exist) {
+			type_flags |= NSS_CAPWAP_RULE_CREATE_PPPOE_CONFIGURED;
+		}
+	}
+
+	if (capwap_rule->l3_proto == NSS_CAPWAP_TUNNEL_IPV6 && capwap_rule->which_udp == NSS_CAPWAP_TUNNEL_UDPLite) {
+		type_flags |= NSS_CAPWAP_ENCAP_UDPLITE_HDR_CSUM;
+	}
+
+	/*
+	 * Copy over the IP rule information to capwap rule for encap side.
+	 * This will avoid any confusions because IP rule direction is AC->AP and
+	 * capwap encap rule direction is AP->AC.
+	 */
+	if (v4) {
+		capwap_rule->encap.src_port = htonl(v4->dest_port);
+		capwap_rule->encap.src_ip.ip.ipv4 = htonl(v4->dest_ip);
+
+		capwap_rule->encap.dest_port = htonl(v4->src_port);
+		capwap_rule->encap.dest_ip.ip.ipv4 = htonl(v4->src_ip);
+	} else {
+		capwap_rule->encap.src_port = htonl(v6->dest_port);
+		capwap_rule->encap.src_ip.ip.ipv6[0] = htonl(v6->dest_ip[0]);
+		capwap_rule->encap.src_ip.ip.ipv6[1] = htonl(v6->dest_ip[1]);
+		capwap_rule->encap.src_ip.ip.ipv6[2] = htonl(v6->dest_ip[2]);
+		capwap_rule->encap.src_ip.ip.ipv6[3] = htonl(v6->dest_ip[3]);
+
+		capwap_rule->encap.dest_port = htonl(v6->src_port);
+		capwap_rule->encap.dest_ip.ip.ipv6[0] = htonl(v6->src_ip[0]);
+		capwap_rule->encap.dest_ip.ip.ipv6[1] = htonl(v6->src_ip[1]);
+		capwap_rule->encap.dest_ip.ip.ipv6[2] = htonl(v6->src_ip[2]);
+		capwap_rule->encap.dest_ip.ip.ipv6[3] = htonl(v6->src_ip[3]);
+	}
+
+	status = nss_capwapmgr_create_capwap_rule(dev, capwap_if_num_inner, capwap_rule, type_flags);
+	nss_capwapmgr_info("%px: dynamic interface if_num is :%d and capwap tunnel status:%d\n", dev, capwap_if_num_inner, status);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_capwapmgr_warn("%px: %d: CAPWAP rule create failed with status: %d", dev, capwap_if_num_inner, status);
+		status = NSS_CAPWAPMGR_FAILURE_CAPWAP_RULE;
+		goto fail5;
+	}
+
+	status = nss_capwapmgr_create_capwap_rule(dev, capwap_if_num_outer, capwap_rule, type_flags);
+	nss_capwapmgr_info("%px: dynamic interface if_num is :%d and capwap tunnel status:%d\n", dev, capwap_if_num_outer, status);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_capwapmgr_warn("%px: %d: CAPWAP rule create failed with status: %d", dev, capwap_if_num_outer, status);
+		status = NSS_CAPWAPMGR_FAILURE_CAPWAP_RULE;
+		goto fail5;
+	}
+
+	if (v4) {
+		v4->dest_interface_num = forward_if_num;
+		nss_status = nss_capwapmgr_configure_ipv4(v4, 0, 0);
+	} else {
+		v6->dest_interface_num = forward_if_num;
+		nss_status = nss_capwapmgr_configure_ipv6(v6, 0, 0);
+	}
+
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_capwapmgr_warn("%px: %d: IPv4/IPv6 rule create failed with status: %d", dev, forward_if_num, nss_status);
+		status = NSS_CAPWAPMGR_FAILURE_IP_RULE;
+		goto fail5;
+	}
+
+	priv = netdev_priv(dev);
+	t = &priv->tunnel[tunnel_id];
+	nss_capwapmgr_info("%px: %d: %d: CAPWAP TUNNEL CREATE DONE tunnel_id:%d (%px)\n", dev, capwap_if_num_inner, capwap_if_num_outer, tunnel_id, t);
+
+	/*
+	 * Keep a copy of rule information.
+	 */
+	if (v4) {
+		memcpy(&t->ip_rule.v4, v4, sizeof (struct nss_ipv4_create));
+	} else {
+		memcpy(&t->ip_rule.v6, v6, sizeof (struct nss_ipv6_create));
+	}
+
+	memcpy(&t->capwap_rule, capwap_rule, sizeof (struct nss_capwap_rule_msg));
+
+	/*
+	 * Make it globally visible inside the netdev.
+	 */
+	t->if_num_inner = capwap_if_num_inner;
+	t->if_num_outer = capwap_if_num_outer;
+	priv->if_num_to_tunnel_id[capwap_if_num_inner] = tunnel_id;
+	priv->if_num_to_tunnel_id[capwap_if_num_outer] = tunnel_id;
+	t->tunnel_state |= NSS_CAPWAPMGR_TUNNEL_STATE_CONFIGURED;
+	t->tunnel_state |= NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED;
+	t->type_flags = type_flags;
+
+	goto done;
+
+fail5:
+	if (dtls_enabled) {
+		if (nss_dtlsmgr_session_destroy(t->dtls_dev) != NSS_DTLSMGR_OK) {
+			nss_capwapmgr_warn("%px: failed to destroy DTLS session", t->dtls_dev);
+		}
+	}
+fail4:
+	nss_capwapmgr_unregister_with_nss(capwap_if_num_outer);
+fail3:
+	(void)nss_dynamic_interface_dealloc_node(capwap_if_num_outer, NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_OUTER);
+fail2:
+	nss_capwapmgr_unregister_with_nss(capwap_if_num_inner);
+fail1:
+	(void)nss_dynamic_interface_dealloc_node(capwap_if_num_inner, NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_HOST_INNER);
+
+done:
+	dev_put(dev);
+	return status;
+}
+
+/*
+ * nss_capwapmgr_ipv4_tunnel_create()
+ *	API for creating IPv4 and CAPWAP rule.
+ */
+nss_capwapmgr_status_t nss_capwapmgr_ipv4_tunnel_create(struct net_device *dev, uint8_t tunnel_id,
+			struct nss_ipv4_create *ip_rule, struct nss_capwap_rule_msg *capwap_rule, struct nss_dtlsmgr_config *in_data)
+{
+	return nss_capwapmgr_tunnel_create_common(dev, tunnel_id, ip_rule, NULL, capwap_rule, in_data);
+}
+EXPORT_SYMBOL(nss_capwapmgr_ipv4_tunnel_create);
+
+/*
+ * nss_capwapmgr_ipv6_tunnel_create()
+ *	API for creating IPv6 and CAPWAP rule.
+ */
+nss_capwapmgr_status_t nss_capwapmgr_ipv6_tunnel_create(struct net_device *dev, uint8_t tunnel_id,
+			struct nss_ipv6_create *ip_rule, struct nss_capwap_rule_msg *capwap_rule, struct nss_dtlsmgr_config *in_data)
+{
+	return nss_capwapmgr_tunnel_create_common(dev, tunnel_id, NULL, ip_rule, capwap_rule, in_data);
+}
+EXPORT_SYMBOL(nss_capwapmgr_ipv6_tunnel_create);
+
+/*
+ * nss_capwapmgr_tunnel_save_stats()
+ *	Internal function to save tunnel stats when a tunnel is being
+ *	destroyed.
+ */
+static void nss_capwapmgr_tunnel_save_stats(struct nss_capwap_tunnel_stats *save, struct nss_capwap_tunnel_stats *fstats)
+{
+	save->dtls_pkts += fstats->dtls_pkts;
+
+	save->rx_segments += fstats->rx_segments;
+	save->rx_dup_frag += fstats->rx_dup_frag;
+	save->rx_oversize_drops += fstats->rx_oversize_drops;
+	save->rx_frag_timeout_drops += fstats->rx_frag_timeout_drops;
+	save->rx_n2h_drops += fstats->rx_n2h_drops;
+	save->rx_n2h_queue_full_drops += fstats->rx_n2h_queue_full_drops;
+	save->rx_mem_failure_drops += fstats->rx_mem_failure_drops;
+	save->rx_csum_drops += fstats->rx_csum_drops;
+	save->rx_malformed += fstats->rx_malformed;
+	save->rx_frag_gap_drops += fstats->rx_frag_gap_drops;
+
+	save->tx_segments += fstats->tx_segments;
+	save->tx_queue_full_drops += fstats->tx_queue_full_drops;
+	save->tx_mem_failure_drops += fstats->tx_mem_failure_drops;
+	save->tx_dropped_sg_ref += fstats->tx_dropped_sg_ref;
+	save->tx_dropped_ver_mis += fstats->tx_dropped_ver_mis;
+	save->tx_dropped_hroom += fstats->tx_dropped_hroom;
+	save->tx_dropped_dtls += fstats->tx_dropped_dtls;
+	save->tx_dropped_nwireless += fstats->tx_dropped_nwireless;
+
+	/*
+	 * add pnode stats now.
+	 */
+	save->pnode_stats.rx_packets += fstats->pnode_stats.rx_packets;
+	save->pnode_stats.rx_bytes += fstats->pnode_stats.rx_bytes;
+	save->pnode_stats.rx_dropped += fstats->pnode_stats.rx_dropped;
+	save->pnode_stats.tx_packets += fstats->pnode_stats.tx_packets;
+	save->pnode_stats.tx_bytes += fstats->pnode_stats.tx_bytes;
+}
+
+/*
+ * nss_capwapmgr_tunnel_destroy()
+ *	API for destroying a tunnel. CAPWAP tunnel must be first disabled.
+ */
+nss_capwapmgr_status_t nss_capwapmgr_tunnel_destroy(struct net_device *dev, uint8_t tunnel_id)
+{
+	struct nss_capwap_tunnel_stats stats;
+	struct nss_ipv4_destroy v4;
+	struct nss_ipv6_destroy v6;
+	struct nss_capwapmgr_priv *priv;
+	struct nss_capwapmgr_tunnel *t;
+	nss_tx_status_t nss_status = NSS_TX_SUCCESS;
+	uint32_t if_num_inner, if_num_outer;
+	nss_capwapmgr_status_t status = NSS_CAPWAPMGR_SUCCESS;
+
+	dev_hold(dev);
+	t = nss_capwapmgr_verify_tunnel_param(dev, tunnel_id);
+	if (!t) {
+		nss_capwapmgr_warn("%px: tunnel %d: wrong argument for tunnel destroy\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+	if (!(t->tunnel_state & NSS_CAPWAPMGR_TUNNEL_STATE_CONFIGURED)) {
+		nss_capwapmgr_warn("%px: tunnel %d is not configured yet\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_TUNNEL_NOT_CFG;
+		goto done;
+	}
+
+	/*
+	 * We don't allow destroy operation on tunnel if it's still enabled.
+	 */
+	if (t->tunnel_state & NSS_CAPWAPMGR_TUNNEL_STATE_ENABLED) {
+		nss_capwapmgr_warn("%px: no destroy alloed for an eanbled tunnel: %d\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_TUNNEL_ENABLED;
+		goto done;
+	}
+
+	if (!(t->capwap_rule.l3_proto == NSS_CAPWAP_TUNNEL_IPV4 ||
+		t->capwap_rule.l3_proto == NSS_CAPWAP_TUNNEL_IPV6)) {
+		nss_capwapmgr_warn("%px: tunnel %d: wrong argument for l3_proto\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+	if (!(t->capwap_rule.which_udp == NSS_CAPWAP_TUNNEL_UDP ||
+		t->capwap_rule.which_udp == NSS_CAPWAP_TUNNEL_UDPLite)) {
+		nss_capwapmgr_warn("%px: tunnel %d: wrong argument for which_udp(%d)\n", dev, tunnel_id, t->capwap_rule.which_udp);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+	priv = netdev_priv(dev);
+	nss_capwapmgr_info("%px: %d: tunnel destroy is being called\n", dev, tunnel_id);
+
+	if_num_inner = t->if_num_inner;
+	if_num_outer = t->if_num_outer;
+
+	if (priv->if_num_to_tunnel_id[if_num_inner] != tunnel_id) {
+		nss_capwapmgr_warn("%px: %d: tunnel_id %d didn't match with tunnel_id :%d\n",
+			dev, if_num_inner, tunnel_id, priv->if_num_to_tunnel_id[if_num_inner]);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+	if (priv->if_num_to_tunnel_id[if_num_outer] != tunnel_id) {
+		nss_capwapmgr_warn("%px: %d: tunnel_id %d didn't match with tunnel_id :%d\n",
+			dev, if_num_outer, tunnel_id, priv->if_num_to_tunnel_id[if_num_outer]);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+	if (nss_capwap_get_stats(if_num_inner, &stats) == true) {
+		nss_capwapmgr_tunnel_save_stats(&global.tunneld, &stats);
+	}
+
+	if (nss_capwap_get_stats(if_num_outer, &stats) == true) {
+		nss_capwapmgr_tunnel_save_stats(&global.tunneld, &stats);
+	}
+
+	/*
+	 * Destroy IP rule first.
+	 */
+	if (t->tunnel_state & NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED) {
+		if (t->capwap_rule.l3_proto == NSS_CAPWAP_TUNNEL_IPV4) {
+			memset(&v4, 0, sizeof (struct nss_ipv4_destroy));
+			v4.protocol = IPPROTO_UDP;
+			v4.src_ip = t->ip_rule.v4.src_ip;
+			v4.dest_ip = t->ip_rule.v4.dest_ip;
+			v4.src_port = t->ip_rule.v4.src_port;
+			v4.dest_port = t->ip_rule.v4.dest_port;
+			nss_status = nss_capwapmgr_unconfigure_ipv4_rule(&v4);
+		} else {
+			memset(&v6, 0, sizeof (struct nss_ipv6_destroy));
+			if (t->capwap_rule.which_udp == NSS_CAPWAP_TUNNEL_UDP) {
+				v6.protocol = IPPROTO_UDP;
+			} else {
+				v6.protocol = IPPROTO_UDPLITE;
+			}
+
+			v6.src_ip[0] = t->ip_rule.v6.src_ip[0];
+			v6.src_ip[1] = t->ip_rule.v6.src_ip[1];
+			v6.src_ip[2] = t->ip_rule.v6.src_ip[2];
+			v6.src_ip[3] = t->ip_rule.v6.src_ip[3];
+
+			v6.dest_ip[0] = t->ip_rule.v6.dest_ip[0];
+			v6.dest_ip[1] = t->ip_rule.v6.dest_ip[1];
+			v6.dest_ip[2] = t->ip_rule.v6.dest_ip[2];
+			v6.dest_ip[3] = t->ip_rule.v6.dest_ip[3];
+
+			v6.src_port = t->ip_rule.v6.src_port;
+			v6.dest_port = t->ip_rule.v6.dest_port;
+			nss_status = nss_capwapmgr_unconfigure_ipv6_rule(&v6);
+		}
+
+		if (nss_status != NSS_TX_SUCCESS) {
+			nss_capwapmgr_warn("%px: Unconfigure IP rule failed for tunnel : %d\n",
+				dev, tunnel_id);
+			status = NSS_CAPWAPMGR_FAILURE_IP_DESTROY_RULE;
+			goto done;
+		}
+		t->tunnel_state &= ~NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED;
+	}
+
+	/*
+	 * Destroy CAPWAP rule now.
+	 */
+	status = nss_capwapmgr_tunnel_action(priv->nss_ctx, dev, if_num_outer, NSS_CAPWAP_MSG_TYPE_UNCFG_RULE);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_capwapmgr_warn("%px: %d: Unconfigure CAPWAP rule failed for tunnel : %d\n",
+			dev, if_num_outer, tunnel_id);
+		goto fail;
+
+	}
+
+	status = nss_capwapmgr_tunnel_action(priv->nss_ctx, dev, if_num_inner, NSS_CAPWAP_MSG_TYPE_UNCFG_RULE);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_capwapmgr_warn("%px: %d: Unconfigure CAPWAP rule failed for tunnel : %d\n",
+			dev, if_num_inner, tunnel_id);
+		status = nss_capwapmgr_create_capwap_rule(dev, if_num_outer, &(t->capwap_rule), t->type_flags);
+			if (status != NSS_CAPWAPMGR_SUCCESS) {
+				nss_capwapmgr_warn("%px: %d: re creating the CAPWAP rule failed for tunnel : %d\n",
+			dev, if_num_inner, tunnel_id);
+				goto done;
+			}
+
+		goto fail;
+
+	}
+
+	nss_capwapmgr_unregister_with_nss(if_num_outer);
+	nss_capwapmgr_unregister_with_nss(if_num_inner);
+
+	/*
+	 * Deallocate dynamic interface
+	 */
+	nss_status = nss_dynamic_interface_dealloc_node(if_num_outer, NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_OUTER);
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_capwapmgr_warn("%px: %d: Dealloc of dynamic interface failed for tunnel : %d\n",
+			dev, if_num_outer, tunnel_id);
+	}
+
+	nss_status = nss_dynamic_interface_dealloc_node(if_num_inner, NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_HOST_INNER);
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_capwapmgr_warn("%px: %d: Dealloc of dynamic interface failed for tunnel : %d\n",
+			dev, if_num_inner, tunnel_id);
+	}
+
+	/*
+	 * Unconfigure Trustsec Tx
+	 */
+	 if (t->capwap_rule.enabled_features & NSS_CAPWAPMGR_FEATURE_OUTER_TRUSTSEC_ENABLED) {
+		if (t->capwap_rule.enabled_features & NSS_CAPWAPMGR_FEATURE_DTLS_ENABLED) {
+			nss_status = nss_trustsec_tx_unconfigure_sgt(t->capwap_rule.dtls_inner_if_num, t->capwap_rule.outer_sgt_value);
+		} else {
+			nss_status = nss_trustsec_tx_unconfigure_sgt(t->if_num_outer, t->capwap_rule.outer_sgt_value);
+		}
+
+		if (nss_status != NSS_TX_SUCCESS) {
+			nss_capwapmgr_warn("%px: unconfigure trustsec_tx failed\n", dev);
+		}
+	 }
+
+	/*
+	 * Destroy DTLS node if there is one associated to this tunnel
+	 */
+	if (t->capwap_rule.dtls_inner_if_num) {
+		if (nss_dtlsmgr_session_destroy(t->dtls_dev) != NSS_DTLSMGR_OK) {
+			nss_capwapmgr_warn("%px: failed to destroy DTLS session", t->dtls_dev);
+		}
+	}
+
+	t->tunnel_state &= ~NSS_CAPWAPMGR_TUNNEL_STATE_CONFIGURED;
+	priv->if_num_to_tunnel_id[if_num_inner] = -1;
+	priv->if_num_to_tunnel_id[if_num_outer] = -1;
+
+	memset(t, 0, sizeof(struct nss_capwapmgr_tunnel));
+
+	t->if_num_inner = -1;
+	t->if_num_outer = -1;
+
+	nss_capwapmgr_info("%px: Tunnel %d is completely destroyed\n", dev , tunnel_id);
+	status = NSS_CAPWAPMGR_SUCCESS;
+	goto done;
+
+fail:
+	if (t->capwap_rule.l3_proto == NSS_CAPWAP_TUNNEL_IPV4) {
+		nss_status = nss_capwapmgr_configure_ipv4(&t->ip_rule.v4, 0, 0);
+	} else {
+		nss_status = nss_capwapmgr_configure_ipv6(&t->ip_rule.v6, 0, 0);
+	}
+
+	if (nss_status == NSS_TX_SUCCESS) {
+		t->tunnel_state |= NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED;
+	}
+
+	status = NSS_CAPWAPMGR_FAILURE_CAPWAP_DESTROY_RULE;
+
+done:
+	dev_put(dev);
+	return status;
+}
+EXPORT_SYMBOL(nss_capwapmgr_tunnel_destroy);
+
+/*
+ * nss_capwapmgr_flow_rule_action()
+ */
+static inline nss_capwapmgr_status_t nss_capwapmgr_flow_rule_action(struct net_device *dev, uint8_t tunnel_id,
+						nss_capwap_msg_type_t cmd, uint16_t ip_version,
+						uint16_t protocol, uint32_t *src_ip, uint32_t *dst_ip,
+						uint16_t src_port, uint16_t dst_port, uint32_t flow_id)
+{
+	struct nss_capwapmgr_priv *priv;
+	struct nss_capwap_msg capwapmsg;
+	struct nss_capwap_flow_rule_msg *ncfrm;
+	struct nss_capwapmgr_tunnel *t;
+	nss_capwapmgr_status_t status;
+
+	dev_hold(dev);
+	t = nss_capwapmgr_verify_tunnel_param(dev, tunnel_id);
+	if (!t) {
+		nss_capwapmgr_warn("%px: can't find tunnel: %d\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+	priv = netdev_priv(dev);
+
+	memset(&capwapmsg, 0, sizeof(struct nss_capwap_msg));
+	nss_capwap_msg_init(&capwapmsg, t->if_num_outer, cmd,
+		sizeof(struct nss_capwap_flow_rule_msg), nss_capwapmgr_msg_event_receive, dev);
+
+	/*
+	 * Set flow rule message
+	 */
+	if (cmd == NSS_CAPWAP_MSG_TYPE_FLOW_RULE_ADD) {
+		ncfrm = &capwapmsg.msg.flow_rule_add;
+	} else {
+		ncfrm = &capwapmsg.msg.flow_rule_del;
+	}
+	ncfrm->protocol = protocol;
+	ncfrm->src_port = src_port;
+	ncfrm->dst_port = dst_port;
+	ncfrm->ip_version = ip_version;
+	memcpy(ncfrm->src_ip, src_ip, sizeof(struct in6_addr));
+	memcpy(ncfrm->dst_ip, dst_ip, sizeof(struct in6_addr));
+	ncfrm->flow_id = flow_id;
+
+	/*
+	 * Send flow rule message to NSS core
+	 */
+	status = nss_capwapmgr_tx_msg_sync(priv->nss_ctx, dev, &capwapmsg);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_capwapmgr_warn("%px: send flow rule message failed with error: %d\n", dev, status);
+	}
+
+done:
+	dev_put(dev);
+	return status;
+}
+
+/*
+ * nss_capwapmgr_add_flow_rule()
+ *	Send a capwap flow rule add message to NSS core.
+ */
+nss_capwapmgr_status_t nss_capwapmgr_add_flow_rule(struct net_device *dev, uint8_t tunnel_id, uint16_t ip_version,
+						uint16_t protocol, uint32_t *src_ip, uint32_t *dst_ip,
+						uint16_t src_port, uint16_t dst_port, uint32_t flow_id)
+{
+	return nss_capwapmgr_flow_rule_action(dev, tunnel_id, NSS_CAPWAP_MSG_TYPE_FLOW_RULE_ADD, ip_version,
+											protocol, src_ip, dst_ip, src_port, dst_port, flow_id);
+}
+EXPORT_SYMBOL(nss_capwapmgr_add_flow_rule);
+
+/*
+ * nss_capwapmgr_del_flow_rule()
+ *	Send a capwap flow rule del message to NSS core.
+ */
+nss_capwapmgr_status_t nss_capwapmgr_del_flow_rule(struct net_device *dev, uint8_t tunnel_id, uint16_t ip_version,
+						uint16_t protocol, uint32_t *src_ip, uint32_t *dst_ip,
+						uint16_t src_port, uint16_t dst_port)
+{
+	return nss_capwapmgr_flow_rule_action(dev, tunnel_id, NSS_CAPWAP_MSG_TYPE_FLOW_RULE_DEL, ip_version,
+											protocol, src_ip, dst_ip, src_port, dst_port, 0);
+}
+EXPORT_SYMBOL(nss_capwapmgr_del_flow_rule);
+
+/*
+ * nss_capwapmgr_tunnel_stats()
+ *	Gets tunnel stats from netdev
+ */
+nss_capwapmgr_status_t nss_capwapmgr_tunnel_stats(struct net_device *dev,
+		uint8_t tunnel_id, struct nss_capwap_tunnel_stats *stats)
+{
+	struct nss_capwapmgr_tunnel *t;
+	struct nss_capwap_tunnel_stats stats_temp;
+	nss_capwapmgr_status_t status = NSS_CAPWAPMGR_SUCCESS;
+
+	if (!stats) {
+		nss_capwapmgr_warn("%px: invalid rtnl structure\n", dev);
+		return NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+	}
+
+	dev_hold(dev);
+	t = nss_capwapmgr_verify_tunnel_param(dev, tunnel_id);
+	if (!t) {
+		nss_capwapmgr_trace("%px: can't find tunnel: %d\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_BAD_PARAM;
+		goto done;
+	}
+
+	if (!(t->tunnel_state & NSS_CAPWAPMGR_TUNNEL_STATE_CONFIGURED)) {
+		nss_capwapmgr_trace("%px: tunnel: %d not configured yet\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_TUNNEL_NOT_CFG;
+		goto done;
+	}
+
+	/*
+	 * Copy the inner interface stats.
+	 */
+	if (nss_capwap_get_stats(t->if_num_inner, &stats_temp) == false) {
+		nss_capwapmgr_warn("%px: tunnel %d not ready yet\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_NOT_READY;
+		goto done;
+	}
+
+	stats->dtls_pkts += stats_temp.dtls_pkts;
+	stats->tx_segments += stats_temp.tx_segments;
+	stats->tx_queue_full_drops += stats_temp.tx_queue_full_drops;
+	stats->tx_mem_failure_drops += stats_temp.tx_mem_failure_drops;
+	stats->tx_dropped_sg_ref += stats_temp.tx_dropped_sg_ref;
+	stats->tx_dropped_ver_mis += stats_temp.tx_dropped_ver_mis;
+	stats->tx_dropped_hroom += stats_temp.tx_dropped_hroom;
+	stats->tx_dropped_dtls += stats_temp.tx_dropped_dtls;
+	stats->tx_dropped_nwireless += stats_temp.tx_dropped_nwireless;
+
+	/*
+	 * Pnode tx stats for Inner node.
+	 */
+	stats->pnode_stats.tx_packets += stats_temp.pnode_stats.tx_packets;
+	stats->pnode_stats.tx_bytes += stats_temp.pnode_stats.tx_bytes;
+	stats->tx_dropped_inner += stats_temp.tx_dropped_inner;
+
+	/*
+	 * Copy the outer interface stats.
+	 */
+	if (nss_capwap_get_stats(t->if_num_outer, &stats_temp) == false) {
+		nss_capwapmgr_warn("%px: tunnel %d not ready yet\n", dev, tunnel_id);
+		status = NSS_CAPWAPMGR_FAILURE_NOT_READY;
+		goto done;
+	}
+
+	stats->rx_segments += stats_temp.rx_segments;
+	stats->dtls_pkts += stats_temp.dtls_pkts;
+	stats->rx_dup_frag += stats_temp.rx_dup_frag;
+	stats->rx_oversize_drops += stats_temp.rx_oversize_drops;
+	stats->rx_frag_timeout_drops += stats_temp.rx_frag_timeout_drops;
+	stats->rx_n2h_drops += stats_temp.rx_n2h_drops;
+	stats->rx_n2h_queue_full_drops += stats_temp.rx_n2h_queue_full_drops;
+	stats->rx_mem_failure_drops += stats_temp.rx_mem_failure_drops;
+	stats->rx_csum_drops += stats_temp.rx_csum_drops;
+	stats->rx_malformed += stats_temp.rx_malformed;
+	stats->rx_frag_gap_drops += stats_temp.rx_frag_gap_drops;
+
+	/*
+	 * Pnode rx stats for outer node.
+	 */
+	stats->pnode_stats.rx_packets += stats_temp.pnode_stats.rx_packets;
+	stats->pnode_stats.rx_bytes += stats_temp.pnode_stats.rx_bytes;
+	stats->pnode_stats.rx_dropped += stats_temp.pnode_stats.rx_dropped;
+
+done:
+	dev_put(dev);
+	return status;
+}
+EXPORT_SYMBOL(nss_capwapmgr_tunnel_stats);
+
+/*
+ * nss_capwapmgr_receive_pkt()
+ *	Receives a pkt from NSS
+ */
+static void nss_capwapmgr_receive_pkt(struct net_device *dev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	struct nss_capwapmgr_priv *priv;
+	struct nss_capwap_metaheader *pre = (struct nss_capwap_metaheader *)skb->data;
+	int32_t if_num;
+
+	if (unlikely(skb->len < sizeof(struct nss_capwap_metaheader))) {
+		nss_capwapmgr_warn("%px: skb len is short :%d", dev, skb->len);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	/* SKB NETIF START */
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+	if_num = pre->tunnel_id;	/* NSS FW sends interface number */
+	if (unlikely(if_num > NSS_MAX_NET_INTERFACES)) {
+		nss_capwapmgr_warn("%px: if_num %d is wrong for skb\n", dev, if_num);
+		pre->tunnel_id = 0xFF;
+	} else {
+		/*
+		 * Remap interface number to tunnel_id.
+		 */
+		pre->tunnel_id = priv->if_num_to_tunnel_id[if_num];
+	}
+
+	skb->dev = dev;
+	skb->pkt_type = PACKET_HOST;
+	skb->skb_iif = dev->ifindex;
+	skb_reset_mac_header(skb);
+	skb_reset_transport_header(skb);
+	(void)netif_receive_skb(skb);
+	/* SKB NETIF END */
+	dev_put(dev);
+}
+
+/*
+ * nss_capwapmgr_acl_init()
+ *	Initializes ACL related tables and objects.
+ */
+bool nss_capwapmgr_acl_init(void)
+{
+	sw_error_t rv;
+	int i, j, uid = 0;
+
+	/*
+	 * Create and bind the ACL list we will be using for dscp prioritization.
+	 */
+	for (i = 0; i < NSS_CAPWAPMGR_ACL_LIST_CNT; i++) {
+		int list_id = NSS_CAPWAPMGR_ACL_LIST_START + i;
+		rv = fal_acl_list_creat(0, list_id, 0);
+		if (rv != SW_OK) {
+			nss_capwapmgr_warn("Failed to create ACL list err:%d\n", rv);
+			return false;
+		}
+
+		rv = fal_acl_list_bind(0, list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORTBITMAP, NSS_CAPWAPMGR_BIND_BITMAP);
+		if (rv != SW_OK) {
+			nss_capwapmgr_warn("Failed to bind ACL list err:%d\n", rv);
+			return false;
+		}
+	}
+
+	/*
+	 * Initialize the globacl ACL table.
+	 */
+	for (i = 0; i < NSS_CAPWAPMGR_ACL_LIST_CNT; i++) {
+		for (j = 0; j < NSS_CAPWAPMGR_ACL_RULES_PER_LIST; j++) {
+			global.acl_list[i].rule[j].uid = uid++;
+			global.acl_list[i].rule[j].rule_id = j;
+			global.acl_list[i].rule[j].list_id = i;
+		}
+	}
+
+	return true;
+}
+
+#if defined(NSS_CAPWAPMGR_ONE_NETDEV)
+/*
+ * nss_capwapmgr_get_netdev()
+ *	Returns net device used.
+ */
+struct net_device *nss_capwapmgr_get_netdev(void)
+{
+	return nss_capwapmgr_ndev;
+}
+EXPORT_SYMBOL(nss_capwapmgr_get_netdev);
+#endif
+
+/*
+ * nss_capwapmgr_netdev_up()
+ *	NSS CAPWAP Tunnel device i/f up handler
+ */
+static int nss_capwapmgr_netdev_up(struct net_device *netdev)
+{
+	uint8_t i;
+	for (i = 0; i < NSS_CAPWAPMGR_MAX_TUNNELS; i++) {
+		(void)nss_capwapmgr_enable_tunnel(nss_capwapmgr_ndev, i);
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_capwapmgr_netdev_down()
+ *	NSS CAPWAP Tunnel device i/f up handler
+ */
+static int nss_capwapmgr_netdev_down(struct net_device *netdev)
+{
+	uint8_t i;
+	for (i = 0; i < NSS_CAPWAPMGR_MAX_TUNNELS; i++) {
+		(void)nss_capwapmgr_disable_tunnel(nss_capwapmgr_ndev, i);
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_capwapmgr_netdev_event()
+ *	Net device notifier for NSS CAPWAP manager module
+ */
+static int nss_capwapmgr_netdev_event(struct notifier_block *nb, unsigned long event, void *dev)
+{
+	struct net_device *netdev = (struct net_device *)dev;
+
+	if (strstr(netdev->name, NSS_CAPWAPMGR_NETDEV_NAME) == NULL) {
+		return NOTIFY_DONE;
+	}
+
+	switch (event) {
+	case NETDEV_UP:
+		nss_capwapmgr_trace("%px: NETDEV_UP: event %lu name %s\n", netdev, event, netdev->name);
+		return nss_capwapmgr_netdev_up(netdev);
+
+	case NETDEV_DOWN:
+		nss_capwapmgr_trace("%px: NETDEV_DOWN: event %lu name %s\n", netdev, event, netdev->name);
+		return nss_capwapmgr_netdev_down(netdev);
+
+	default:
+		nss_capwapmgr_trace("%px: Unhandled notifier event %lu name %s\n", netdev, event, netdev->name);
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * Linux netdev event function.
+ */
+static int nss_capwapmgr_netdev_event(struct notifier_block  *nb, unsigned long event, void  *dev);
+
+/*
+ * Linux Net device Notifier
+ */
+struct notifier_block nss_capwapmgr_netdev_notifier = {
+	.notifier_call = nss_capwapmgr_netdev_event,
+};
+
+/*
+ * nss_capwapmgr_init_module()
+ *	Tunnel CAPWAP module init function
+ */
+int __init nss_capwapmgr_init_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+	nss_capwapmgr_info("module (platform - IPQ806x, %s) loaded\n",
+			   NSS_CLIENT_BUILD_ID);
+
+	register_netdevice_notifier(&nss_capwapmgr_netdev_notifier);
+
+#if defined(NSS_CAPWAPMGR_ONE_NETDEV)
+	/*
+	 * In this code, we create a single netdev for all the CAPWAP
+	 * tunnels.
+	 */
+	nss_capwapmgr_ndev = nss_capwapmgr_netdev_create();
+	if (!nss_capwapmgr_ndev) {
+		nss_capwapmgr_warn("Couldn't create capwap interface\n");
+		return -1;
+	}
+#endif
+
+	memset(&global.tunneld, 0, sizeof(struct nss_capwap_tunnel_stats));
+
+	/*
+	 * Initialize ACL related objects and tables.
+	 */
+	if (!nss_capwapmgr_acl_init()) {
+		nss_capwapmgr_warn("Couldn't initialize ACL objects/tables\n");
+		return -1;
+	}
+
+	sema_init(&ip_response.sem, 1);
+	init_waitqueue_head(&ip_response.wq);
+
+	return 0;
+}
+
+/*
+ * nss_capwapmgr_exit_module()
+ *	Tunnel CAPWAP module exit function
+ */
+void __exit nss_capwapmgr_exit_module(void)
+{
+#if defined(NSS_CAPWAPMGR_ONE_NETDEV)
+	struct nss_capwapmgr_priv *priv;
+	uint8_t i;
+#endif
+
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return;
+	}
+#endif
+
+#if defined(NSS_CAPWAPMGR_ONE_NETDEV)
+	priv = netdev_priv(nss_capwapmgr_ndev);
+	for (i = 0; i < NSS_CAPWAPMGR_MAX_TUNNELS; i++) {
+		(void) nss_capwapmgr_disable_tunnel(nss_capwapmgr_ndev, i);
+		(void) nss_capwapmgr_tunnel_destroy(nss_capwapmgr_ndev, i);
+	}
+	kfree(priv->if_num_to_tunnel_id);
+	kfree(priv->resp);
+	kfree(priv->tunnel);
+	unregister_netdev(nss_capwapmgr_ndev);
+	nss_capwapmgr_ndev = NULL;
+#endif
+	unregister_netdevice_notifier(&nss_capwapmgr_netdev_notifier);
+
+	nss_capwapmgr_info("module unloaded\n");
+}
+
+module_init(nss_capwapmgr_init_module);
+module_exit(nss_capwapmgr_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS CAPWAP manager");
diff --git a/qca-nss-clients/clmapmgr/Makefile b/qca-nss-clients/clmapmgr/Makefile
new file mode 100644
index 0000000..1131778
--- /dev/null
+++ b/qca-nss-clients/clmapmgr/Makefile
@@ -0,0 +1,5 @@
+ccflags-y := -I$(obj)/../exports -I$(obj)/..  \
+	-DNSS_CLIENT_BUILD_ID="$(BUILD_ID)" -DNSS_CLMAPMGR_DEBUG_LEVEL=2 -Wall -Werror
+
+obj-m += qca-nss-clmapmgr.o
+qca-nss-clmapmgr-objs := nss_clmapmgr.o
diff --git a/qca-nss-clients/clmapmgr/nss_clmapmgr.c b/qca-nss-clients/clmapmgr/nss_clmapmgr.c
new file mode 100644
index 0000000..9574706
--- /dev/null
+++ b/qca-nss-clients/clmapmgr/nss_clmapmgr.c
@@ -0,0 +1,996 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_clmapmgr.c
+ *  This file implements client for CLient map manager.
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/if_ether.h>
+#include <linux/if_vlan.h>
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+
+#include "nss_clmapmgr_private.h"
+#include "nss_clmapmgr.h"
+#include "nss_eogremgr.h"
+
+#define NSS_CLMAPMGR_CMD_MAX_RETRY_COUNT 3
+#define NSS_CLMAP_MAX_HEADROOM NSS_EOGREMGR_MAX_HEADROOM
+
+/*
+ * nss_clmapmgr_dev_xmit()
+ *	Netdev ops function to send packet to NSS.
+ */
+static netdev_tx_t nss_clmapmgr_dev_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	nss_tx_status_t status;
+	int if_number;
+	struct nss_ctx_instance *clmap_ctx;
+	struct nss_clmapmgr_priv_t *priv = netdev_priv(dev);
+
+	if_number = priv->nss_if_number_us;
+	if (unlikely(if_number <= 0)) {
+		nss_clmapmgr_info("%px: clmapmgr dev is not registered with nss\n", dev);
+		goto fail;
+	}
+
+	clmap_ctx = nss_clmap_get_ctx();
+	if (unlikely(!clmap_ctx)) {
+		nss_clmapmgr_info("%px: NSS clmapmgr context not found.\n", dev);
+		goto fail;
+	}
+
+	status = nss_clmap_tx_buf(clmap_ctx, skb, (uint32_t)if_number);
+	if (unlikely(status != NSS_TX_SUCCESS)) {
+		if (likely(status == NSS_TX_FAILURE_QUEUE)) {
+			nss_clmapmgr_warning("%px: netdev :%px queue is full", dev, dev);
+			if (!netif_queue_stopped(dev)) {
+				netif_stop_queue(dev);
+			}
+			nss_clmapmgr_warning("%px: (CLMAP packet) Failed to xmit the packet because of tx queue full, status: %d\n", dev, status);
+			return NETDEV_TX_BUSY;
+		}
+		nss_clmapmgr_info("%px: NSS clmapmgr could not send packet to NSS %d\n", dev, if_number);
+		goto fail;
+	}
+
+	return NETDEV_TX_OK;
+
+fail:
+	dev->stats.tx_dropped++;
+	dev_kfree_skb_any(skb);
+	return NETDEV_TX_OK;
+}
+
+/*
+ * nss_clmapmgr_get_dev_stats64()
+ *	Netdev ops function to retrieve stats.
+ */
+static struct rtnl_link_stats64 *nss_clmapmgr_get_dev_stats64(struct net_device *dev,
+						struct rtnl_link_stats64 *stats)
+{
+	struct nss_clmapmgr_priv_t *priv;
+
+	if (!stats) {
+		nss_clmapmgr_warning("%px: invalid rtnl structure\n", dev);
+		return stats;
+	}
+
+	dev_hold(dev);
+
+	/*
+	 * Netdev seems to be incrementing rx_dropped because we don't give IP header.
+	 * So reset it as it's of no use for us.
+	 */
+	atomic_long_set(&dev->rx_dropped, 0);
+	priv = netdev_priv(dev);
+	memset(stats, 0, sizeof(struct rtnl_link_stats64));
+	memcpy(stats, &priv->stats, sizeof(struct rtnl_link_stats64));
+	dev_put(dev);
+
+	return stats;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0))
+/*
+ * nss_clmapmgr_dev_stats64()
+ *	Netdev ops function to retrieve stats for kernel version < 4.6
+ */
+static struct rtnl_link_stats64 *nss_clmapmgr_dev_stats64(struct net_device *dev,
+						struct rtnl_link_stats64 *tot)
+{
+	return nss_clmapmgr_get_dev_stats64(dev, tot);
+}
+#else
+/*
+ * nss_clmapmgr_dev_stats64()
+ *	Netdev ops function to retrieve stats for kernel version >= 4.6
+ */
+static void nss_clmapmgr_dev_stats64(struct net_device *dev,
+				struct rtnl_link_stats64 *tot)
+{
+	nss_clmapmgr_get_dev_stats64(dev, tot);
+}
+#endif
+
+/*
+ * nss_clmapmgr_dev_init()
+ *	Netdev ops function to intialize netdevice.
+ */
+static int nss_clmapmgr_dev_init(struct net_device *dev)
+{
+	dev->mtu = ETH_DATA_LEN;
+	dev->needed_headroom = NSS_CLMAP_MAX_HEADROOM;
+	return 0;
+}
+
+/*
+ * nss_clmapmgr_dev_open()
+ *	Netdev ops function to open netdevice.
+ */
+static int nss_clmapmgr_dev_open(struct net_device *dev)
+{
+	netif_start_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_clmapmgr_dev_close()
+ *	Netdevice ops function to close netdevice.
+ */
+static int nss_clmapmgr_dev_close(struct net_device *dev)
+{
+	netif_stop_queue(dev);
+	return 0;
+}
+
+/*
+ * clmap netdevice ops
+ */
+static const struct net_device_ops nss_clmapmgr_ops = {
+	.ndo_init = nss_clmapmgr_dev_init,
+	.ndo_open = nss_clmapmgr_dev_open,
+	.ndo_stop = nss_clmapmgr_dev_close,
+	.ndo_set_mac_address = eth_mac_addr,
+	.ndo_validate_addr = eth_validate_addr,
+	.ndo_start_xmit = nss_clmapmgr_dev_xmit,
+	.ndo_get_stats64 = nss_clmapmgr_dev_stats64,
+};
+
+/*
+ * nss_clmapmgr_setup()
+ */
+static void nss_clmapmgr_setup(struct net_device *dev)
+{
+	char name[IFNAMSIZ] = {0};
+
+	strlcpy(name, "nssclmap%d", IFNAMSIZ);
+	memcpy(dev->name, name, IFNAMSIZ);
+	dev->netdev_ops = &nss_clmapmgr_ops;
+	eth_hw_addr_random(dev);
+}
+
+/*
+ * nss_clmapmgr_ds_exception()
+ *	Client map manager ds exception handler to receive packet from NSS.
+ */
+static void nss_clmapmgr_ds_exception(struct net_device *dev, struct sk_buff *skb,
+				       __attribute__((unused)) struct napi_struct *napi)
+{
+	/*
+	 * Note: preheader needs to be processed by the user
+	 * before processing the ethernet packet
+	 */
+	skb->protocol = eth_type_trans(skb, dev);
+	netif_receive_skb(skb);
+}
+
+/*
+ * nss_clmapmgr_us_exception()
+ *	Client map manager us exception handler to receive packet from NSS.
+ */
+static void nss_clmapmgr_us_exception(struct net_device *dev, struct sk_buff *skb,
+				       __attribute__((unused)) struct napi_struct *napi)
+{
+	/*
+	 * This is an error packet and needs to be dropped.
+	 */
+	nss_clmapmgr_warning("%px: upstream packet got exceptioned, dropping the packet..", dev);
+	dev_kfree_skb_any(skb);
+}
+
+/*
+ * nss_clmapmgr_event_receive()
+ *	Event Callback to receive events from NSS
+ */
+static void nss_clmapmgr_event_receive(void *if_ctx, struct nss_cmn_msg *cmsg)
+{
+	struct net_device *dev = (struct net_device *)if_ctx;
+	struct nss_clmapmgr_priv_t *priv;
+	struct nss_clmap_msg *clmsg = (struct nss_clmap_msg *)cmsg;
+	struct nss_clmap_stats_msg *stats = &clmsg->msg.stats;
+	struct rtnl_link_stats64 *netdev_stats;
+	enum nss_dynamic_interface_type interface_type;
+	uint64_t dropped = 0;
+
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+	netdev_stats = &priv->stats;
+
+	switch (clmsg->cm.type) {
+	case NSS_CLMAP_MSG_TYPE_SYNC_STATS:
+		interface_type = nss_dynamic_interface_get_type(nss_clmap_get_ctx(), clmsg->cm.interface);
+		if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US) {
+			netdev_stats->tx_packets += stats->node_stats.tx_packets;
+			netdev_stats->tx_bytes += stats->node_stats.tx_bytes;
+			dropped += stats->dropped_macdb_lookup_failed;
+			dropped += stats->dropped_invalid_packet_size;
+			dropped += stats->dropped_low_hroom;
+		} else if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_DS) {
+			netdev_stats->rx_packets += stats->node_stats.rx_packets;
+			netdev_stats->rx_bytes += stats->node_stats.rx_bytes;
+			dropped += stats->dropped_pbuf_alloc_failed;
+			dropped += stats->dropped_linear_failed;
+			dropped += stats->shared_packet_count;
+			dropped += stats->ethernet_frame_error;
+		}
+		dropped += stats->dropped_next_node_queue_full;
+		netdev_stats->tx_dropped += dropped;
+		if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_DS) {
+			netdev_stats->rx_dropped += nss_cmn_rx_dropped_sum(&stats->node_stats);
+		}
+		break;
+
+	default:
+		nss_clmapmgr_info("%px: Unknown Event from NSS\n", dev);
+		break;
+	}
+
+	dev_put(dev);
+}
+
+/*
+ * nss_clmapmgr_us_get_if_num
+ * 	return us NSS interface number
+ */
+int nss_clmapmgr_us_get_if_num(struct net_device *dev)
+{
+	struct nss_clmapmgr_priv_t *priv;
+
+	if (!dev) {
+		nss_clmapmgr_info("Netdev is NULL");
+		return -1;
+	}
+
+	priv = (struct nss_clmapmgr_priv_t *)netdev_priv(dev);
+	return priv->nss_if_number_us;
+}
+EXPORT_SYMBOL(nss_clmapmgr_us_get_if_num);
+
+/*
+ * nss_clmapmgr_ds_get_if_num
+ * 	return ds NSS interface number
+ */
+int nss_clmapmgr_ds_get_if_num(struct net_device *dev)
+{
+	struct nss_clmapmgr_priv_t *priv;
+
+	if (!dev) {
+		nss_clmapmgr_info("Netdev is NULL");
+		return -1;
+	}
+
+	priv = (struct nss_clmapmgr_priv_t *)netdev_priv(dev);
+	return priv->nss_if_number_ds;
+}
+EXPORT_SYMBOL(nss_clmapmgr_ds_get_if_num);
+
+/*
+ * nss_clmapmgr_mac_add()
+ * 	API to send notification to NSS to add the MAC entry.
+ */
+nss_clmapmgr_status_t nss_clmapmgr_mac_add(struct net_device *dev, struct nss_clmapmgr_msg *clmapmsg)
+{
+	struct nss_clmap_msg req;
+	struct nss_clmap_mac_msg *mmsg;
+	int us_if, next_ifnum;
+	struct nss_ctx_instance *nss_ctx = NULL;
+	nss_tx_status_t status;
+
+	if (!dev) {
+		nss_clmapmgr_info("Netdev is NULL !!\n");
+		return NSS_CLMAPMGR_ERR_BAD_PARAM;
+	}
+
+	if (!clmapmsg) {
+		nss_clmapmgr_info("%px: nss_clmapmgr_msg is NULL !!\n", dev);
+		return NSS_CLMAPMGR_ERR_BAD_PARAM;
+	}
+
+	/*
+	 * Get Interface number, based on tunnel type
+	 */
+	switch (clmapmsg->tunnel_type) {
+	case NSS_CLMAPMGR_TUNNEL_EOGRE:
+		/*
+		 * For EoGRE tunnel, the next node for the packet from clmap node in NSS
+		 * would be GRE inner node. Get the GRE inner interface.
+		 */
+		next_ifnum = nss_eogremgr_get_if_num_inner(clmapmsg->tunnel_id);
+		if (next_ifnum < 0) {
+			nss_clmapmgr_info("%px: No NSS interface registered for the tunnel id: %d\n", dev, clmapmsg->tunnel_id);
+			return NSS_CLMAPMGR_ERR_TUNNEL_NOT_FOUND;
+		}
+		break;
+	default:
+		nss_clmapmgr_info("%px: Invalid tunnel type: %d\n", dev, clmapmsg->tunnel_type);
+		return NSS_CLMAPMGR_ERR_BAD_PARAM;
+	}
+
+	nss_ctx = nss_clmap_get_ctx();
+
+	/*
+	 * Check if upstream clmap interface is registered with NSS.
+	 */
+	us_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US);
+	if (us_if < 0) {
+		nss_clmapmgr_info("%px: Net device is not registered with nss\n", dev);
+		dev_put(dev);
+		return NSS_CLMAPMGR_ERR_NETDEV_UNKNOWN;
+	}
+
+	memset(&req, 0, sizeof(struct nss_clmap_msg));
+	mmsg = &req.msg.mac_add;
+
+	/*
+	 * Set mac_add message.
+	 */
+	memcpy(mmsg->mac_addr, clmapmsg->mac_addr, ETH_ALEN);
+	mmsg->flags = clmapmsg->flags;
+	mmsg->vlan_id = clmapmsg->vlan_id;
+	mmsg->needed_headroom = clmapmsg->needed_headroom;
+	mmsg->nexthop_ifnum = next_ifnum;
+	nss_clmap_msg_init(&req, us_if, NSS_CLMAP_MSG_TYPE_MAC_ADD, sizeof(struct nss_clmap_mac_msg), NULL, NULL);
+	status = nss_clmap_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_clmapmgr_warning("%px: nss clmap mac add command error:%d if_num: %d\n", dev, status, us_if);
+		dev_put(dev);
+		return NSS_CLMAPMGR_ERR_MAC_ADD_FAILED;
+	}
+
+	return NSS_CLMAPMGR_SUCCESS;
+}
+EXPORT_SYMBOL(nss_clmapmgr_mac_add);
+
+/*
+ * nss_clmapmgr_mac_remove()
+ * 	API to send notification to NSS to delete the MAC entry.
+ */
+nss_clmapmgr_status_t nss_clmapmgr_mac_remove(struct net_device *dev, uint8_t *mac_addr)
+{
+	struct nss_clmap_msg req;
+	struct nss_clmap_mac_msg *mmsg;
+	int us_if;
+	struct nss_ctx_instance *nss_ctx = NULL;
+	nss_tx_status_t status;
+
+	if (!dev) {
+		nss_clmapmgr_info("Netdev is NULL !!\n");
+		return NSS_CLMAPMGR_ERR_BAD_PARAM;
+	}
+
+	if (!mac_addr) {
+		nss_clmapmgr_info("%px: mac address is NULL !!\n", dev);
+		return NSS_CLMAPMGR_ERR_BAD_PARAM;
+	}
+
+	nss_ctx = nss_clmap_get_ctx();
+
+	/*
+	 * Check if upstream clmap interface is registered with NSS
+	 */
+	us_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US);
+	if (us_if < 0) {
+		nss_clmapmgr_info("%px: Net device is not registered with nss\n", dev);
+		dev_put(dev);
+		return NSS_CLMAPMGR_ERR_NETDEV_UNKNOWN;
+	}
+
+	memset(&req, 0, sizeof(struct nss_clmap_msg));
+	mmsg = &req.msg.mac_add;
+
+	/*
+	 * Set mac_del message. Only MAC address is required, the other
+	 * fields as set to 0.
+	 *
+	 */
+	memcpy(mmsg->mac_addr, mac_addr, ETH_ALEN);
+	nss_clmap_msg_init(&req, us_if, NSS_CLMAP_MSG_TYPE_MAC_DEL, sizeof(struct nss_clmap_mac_msg), NULL, NULL);
+	status = nss_clmap_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_clmapmgr_warning("%px: NSS clmap mac del command error:%d if_num: %d\n", dev, status, us_if);
+		dev_put(dev);
+		return NSS_CLMAPMGR_ERR_MAC_DEL_FAILED;
+	}
+
+	return NSS_CLMAPMGR_SUCCESS;
+}
+EXPORT_SYMBOL(nss_clmapmgr_mac_remove);
+
+/*
+ * nss_clmapmgr_mac_flush()
+ * 	API to send notification to NSS to flush MAC entry.
+ */
+nss_clmapmgr_status_t nss_clmapmgr_mac_flush(struct net_device *dev, uint32_t tunnel_id, nss_clmapmgr_tunnel_type_t tunnel_type)
+{
+	struct nss_clmap_msg req;
+	struct nss_clmap_flush_mac_msg *mmsg = &req.msg.mac_flush;
+	int us_if, next_ifnum;
+	struct nss_ctx_instance *nss_ctx = NULL;
+	nss_tx_status_t status;
+
+	if (!dev) {
+		nss_clmapmgr_info("Netdev is NULL !!\n");
+		return NSS_CLMAPMGR_ERR_BAD_PARAM;
+	}
+
+	switch (tunnel_type) {
+	case NSS_CLMAPMGR_TUNNEL_EOGRE:
+		/*
+		 * Get GRE inner interface number
+		 */
+		next_ifnum = nss_eogremgr_get_if_num_inner(tunnel_id);
+		if (next_ifnum < 0) {
+			nss_clmapmgr_info("%px: No NSS interface registered for the tunnel id: %d\n", dev, tunnel_id);
+			return NSS_CLMAPMGR_ERR_TUNNEL_NOT_FOUND;
+		}
+		break;
+	default:
+		nss_clmapmgr_info("%px: Invalid tunnel type: %d\n", dev, tunnel_type);
+		return NSS_CLMAPMGR_ERR_BAD_PARAM;
+	}
+
+	nss_ctx = nss_clmap_get_ctx();
+
+	/*
+	 * Check if upstream clmap interface is registered with NSS
+	 */
+	us_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US);
+	if (us_if < 0) {
+		nss_clmapmgr_info("%px: Net device is not registered with nss\n", dev);
+		dev_put(dev);
+		return NSS_CLMAPMGR_ERR_NETDEV_UNKNOWN;
+	}
+
+	/*
+	 * Set mac_flush message
+	 */
+	mmsg->nexthop_ifnum = next_ifnum;
+	nss_clmap_msg_init(&req, us_if, NSS_CLMAP_MSG_TYPE_MAC_FLUSH, sizeof(struct nss_clmap_mac_msg), NULL, NULL);
+	status = nss_clmap_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_clmapmgr_warning("%px: NSS clmap mac flush command error:%d if_num: %d\n", dev, status, us_if);
+		dev_put(dev);
+		return NSS_CLMAPMGR_ERR_MAC_FLUSH_FAILED;
+	}
+
+	return NSS_CLMAPMGR_SUCCESS;
+}
+EXPORT_SYMBOL(nss_clmapmgr_mac_flush);
+
+/*
+ * nss_clmapmgr_netdev_enable()
+ *	Call back to enable NSS for clmap device.
+ */
+int nss_clmapmgr_netdev_enable(struct net_device *dev)
+{
+	struct nss_clmap_msg req;
+	int us_if, ds_if;
+	struct nss_ctx_instance *nss_ctx = NULL;
+	struct nss_clmapmgr_priv_t *priv;
+	nss_tx_status_t status;
+
+	if (!dev) {
+		nss_clmapmgr_info("Netdev is NULL !!\n");
+		return NOTIFY_DONE;
+	}
+
+	nss_ctx = nss_clmap_get_ctx();
+
+	/*
+	 * Check if upstream clmap interface is registered with NSS
+	 */
+	us_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US);
+	if (us_if < 0) {
+		nss_clmapmgr_info("%px: Net device is not registered with nss\n", dev);
+		goto release_ref;
+	}
+
+	/*
+	 * Check if downstream clmap interface is registered with NSS
+	 */
+	ds_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_DS);
+	if (ds_if < 0) {
+		nss_clmapmgr_info("%px: Net device is not registered with nss\n", dev);
+		goto release_ref;
+	}
+
+	/*
+	 * Send enable session command for upstream interface
+	 */
+	nss_clmap_msg_init(&req, us_if, NSS_CLMAP_MSG_TYPE_INTERFACE_ENABLE, 0, NULL, NULL);
+	status = nss_clmap_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_clmapmgr_warning("%px: NSS clmap enable command error:%d if_num: %d\n", dev, status, us_if);
+		goto release_ref;
+	}
+
+	/*
+	 * Send enable session command for downstream interface
+	 */
+	nss_clmap_msg_init(&req, ds_if, NSS_CLMAP_MSG_TYPE_INTERFACE_ENABLE, 0, NULL, NULL);
+	status = nss_clmap_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_clmapmgr_warning("%px: NSS clmap enable command error:%d if_num: %d\n", dev, status, ds_if);
+		goto disable_us;
+	}
+
+	/*
+	 * Open the netdev to accept packets
+	 */
+	priv = (struct nss_clmapmgr_priv_t *)netdev_priv(dev);
+	priv->clmap_enabled = true;
+	nss_clmapmgr_dev_open(dev);
+
+	return NOTIFY_OK;
+
+disable_us:
+	nss_clmap_msg_init(&req, us_if, NSS_CLMAP_MSG_TYPE_INTERFACE_DISABLE, 0, NULL, NULL);
+	status = nss_clmap_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_clmapmgr_warning("%px: NSS clmap enable command error:%d if_num: %d\n", dev, status, us_if);
+	}
+
+release_ref:
+	return NOTIFY_DONE;
+}
+EXPORT_SYMBOL(nss_clmapmgr_netdev_enable);
+
+/*
+ * nss_clmapmgr_netdev_disable()
+ *	Call back to disable clmap interface in NSS.
+ */
+int nss_clmapmgr_netdev_disable(struct net_device *dev)
+{
+	struct nss_clmap_msg req;
+	int us_if, ds_if;
+	struct nss_ctx_instance *nss_ctx = NULL;
+	struct nss_clmapmgr_priv_t *priv;
+	nss_tx_status_t status;
+
+	if (!dev) {
+		nss_clmapmgr_info("Netdev is NULL !!\n");
+		return NOTIFY_DONE;
+	}
+
+	nss_ctx = nss_clmap_get_ctx();
+
+	/*
+	 * Check if upstream clmap interface is registered with NSS
+	 */
+	us_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US);
+	if (us_if < 0) {
+		nss_clmapmgr_info("%px: Net device is not registered with NSS\n", dev);
+		goto release_ref;
+	}
+
+	/*
+	 * Check if downstream clmap interface is registered with NSS
+	 */
+	ds_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_DS);
+	if (ds_if < 0) {
+		nss_clmapmgr_info("%px: Net device is not registered with NSS\n", dev);
+		goto release_ref;
+	}
+
+	/*
+	 * Send disable session command for upstream interface
+	 */
+	nss_clmap_msg_init(&req, us_if, NSS_CLMAP_MSG_TYPE_INTERFACE_DISABLE, 0, NULL, NULL);
+	status = nss_clmap_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_clmapmgr_warning("%px: NSS clmap disable command error:%d if_num: %d\n", dev, status, us_if);
+		goto release_ref;
+	}
+
+	/*
+	 * Send disable session command for downstream interface
+	 */
+	nss_clmap_msg_init(&req, ds_if, NSS_CLMAP_MSG_TYPE_INTERFACE_DISABLE, 0, NULL, NULL);
+	status = nss_clmap_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_clmapmgr_warning("%px: NSS clmap disable command error:%d if_num: %d\n", dev, status, ds_if);
+		goto enable_us;
+	}
+
+	/*
+	 * Close the netdev
+	 */
+	priv = (struct nss_clmapmgr_priv_t *)netdev_priv(dev);
+	priv->clmap_enabled = false;
+	nss_clmapmgr_dev_close(dev);
+
+	return NOTIFY_OK;
+
+enable_us:
+	nss_clmap_msg_init(&req, us_if, NSS_CLMAP_MSG_TYPE_INTERFACE_ENABLE, 0, NULL, NULL);
+	status = nss_clmap_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_clmapmgr_warning("%px: NSS clmap disable command error:%d if_num: %d\n", dev, status, us_if);
+	}
+
+release_ref:
+	return NOTIFY_DONE;
+}
+EXPORT_SYMBOL(nss_clmapmgr_netdev_disable);
+
+/*
+ * nss_clmapmgr_dev_event()
+ *	Netdevice notifier call back function.
+ */
+static int nss_clmapmgr_dev_event(struct notifier_block  *nb,
+		unsigned long event, void  *dev)
+{
+	struct net_device *netdev;
+	netdev = netdev_notifier_info_to_dev(dev);
+
+	switch (event) {
+	case NETDEV_UP:
+		return nss_clmapmgr_netdev_enable(netdev);
+
+	case NETDEV_DOWN:
+		return nss_clmapmgr_netdev_disable(netdev);
+
+	default:
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_clmapmgr_destroy_us_interface()
+ *	Destroy upstream clmap interface.
+ */
+static nss_clmapmgr_status_t nss_clmapmgr_destroy_us_interface(struct net_device *dev, int interface_num)
+{
+	nss_tx_status_t status;
+	int retry = 0;
+
+	if (!nss_clmap_unregister(interface_num)) {
+		nss_clmapmgr_warning("%px: clmap NSS upstream interface unregister failed\n.", dev);
+		return NSS_CLMAPMGR_ERR_NSSIF_UNREGISTER_FAILED;
+	}
+
+dealloc_us:
+	status = nss_dynamic_interface_dealloc_node(interface_num, NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US);
+	if (status != NSS_TX_SUCCESS) {
+		nss_clmapmgr_info("%px: clmap dealloc node failure for interface_num = %d\n", dev, interface_num);
+		if (++retry <= NSS_CLMAPMGR_CMD_MAX_RETRY_COUNT) {
+			goto dealloc_us;
+		}
+
+		nss_clmapmgr_error("%px: fatal Error, failed to dealloc upstream clmap NSS interface.\n", dev);
+		return NSS_CLMAPMGR_ERR_NSSIF_DEALLOC_FAILED;
+	}
+
+	return NSS_CLMAPMGR_SUCCESS;
+}
+
+/*
+ * nss_clmapmgr_destroy_ds_interface()
+ *	Destroy downstream clmap interface.
+ */
+static nss_clmapmgr_status_t nss_clmapmgr_destroy_ds_interface(struct net_device *dev, int interface_num)
+{
+	nss_tx_status_t status;
+	int retry = 0;
+
+	if (!nss_clmap_unregister(interface_num)) {
+		nss_clmapmgr_warning("%px: clmap NSS downstream interface unregister failed\n.", dev);
+		return NSS_CLMAPMGR_ERR_NSSIF_UNREGISTER_FAILED;
+	}
+
+dealloc_ds:
+	status = nss_dynamic_interface_dealloc_node(interface_num, NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_DS);
+	if (status != NSS_TX_SUCCESS) {
+		nss_clmapmgr_info("%px: clmap dealloc node failure for ds_if = %d\n", dev, interface_num);
+		if (++retry <= NSS_CLMAPMGR_CMD_MAX_RETRY_COUNT) {
+			goto dealloc_ds;
+		}
+
+		nss_clmapmgr_error("%px: fatal Error, failed to dealloc downstream clmap NSS interface.\n", dev);
+		return NSS_CLMAPMGR_ERR_NSSIF_DEALLOC_FAILED;
+	}
+
+	return NSS_CLMAPMGR_SUCCESS;
+}
+
+/*
+ * nss_clmapmgr_decongestion_callback()
+ * 	Wakeup netif queue if we were stopped by start_xmit
+ */
+static void nss_clmapmgr_decongestion_callback(void *arg) {
+	struct net_device *dev = arg;
+	struct nss_clmapmgr_priv_t *priv;
+
+	priv = (struct nss_clmapmgr_priv_t *)netdev_priv(dev);
+	if (unlikely(!priv->clmap_enabled)) {
+		return;
+	}
+
+	if (netif_queue_stopped(dev)) {
+		netif_wake_queue(dev);
+	}
+}
+
+/*
+ * nss_clmapmgr_netdev_destroy()
+ * 	API for destroying a netdevice.
+ * 	Note: User needs to flush all MAC entries in the clmap before destroying the clmap netdevice
+ */
+nss_clmapmgr_status_t nss_clmapmgr_netdev_destroy(struct net_device *dev)
+{
+	int us_if, ds_if;
+	nss_clmapmgr_status_t ret;
+
+	netif_tx_disable(dev);
+
+	/*
+	 * Deregister decongestion callback
+	 */
+	if (nss_cmn_unregister_queue_decongestion(nss_clmap_get_ctx(), nss_clmapmgr_decongestion_callback) != NSS_CB_UNREGISTER_SUCCESS) {
+		nss_clmapmgr_info("%px: failed to unregister decongestion callback\n", dev);
+	}
+
+	/*
+	 * Check if upstream clmap interface is registered with NSS
+	 */
+	us_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US);
+	if (us_if < 0) {
+		nss_clmapmgr_info("%px: Net device is not registered with NSS\n", dev);
+		return NSS_CLMAPMGR_ERR_NETDEV_UNKNOWN;
+	}
+
+	/*
+	 * Check if downstream clmap interface is registered with NSS
+	 */
+	ds_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_DS);
+	if (ds_if < 0) {
+		nss_clmapmgr_info("%px: Net device is not registered with NSS\n", dev);
+		return NSS_CLMAPMGR_ERR_NETDEV_UNKNOWN;
+	}
+
+	ret = nss_clmapmgr_destroy_us_interface(dev, us_if);
+	if (ret != NSS_CLMAPMGR_SUCCESS) {
+		nss_clmapmgr_warning("%px: failed to destroy clmap upstream interface: %d\n", dev, us_if);
+		return ret;
+	}
+
+	ret = nss_clmapmgr_destroy_ds_interface(dev, ds_if);
+	if (ret != NSS_CLMAPMGR_SUCCESS) {
+		nss_clmapmgr_warning("%px: failed to destroy clmap downstream interface: %d\n", dev, ds_if);
+		return ret;
+	}
+
+	nss_clmapmgr_info("%px: deleted clmap instance, us_if = %d ds_if = %d\n",
+			dev, us_if, ds_if);
+
+	unregister_netdev(dev);
+	free_netdev(dev);
+	return NSS_CLMAPMGR_SUCCESS;
+}
+EXPORT_SYMBOL(nss_clmapmgr_netdev_destroy);
+
+/*
+ * nss_clmapmgr_netdev_create()
+ *	User API to create clmap interface
+ */
+struct net_device *nss_clmapmgr_netdev_create(void)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct net_device *dev = NULL;
+	struct nss_clmapmgr_priv_t *priv;
+	nss_tx_status_t status;
+	uint32_t features = 0;
+	int32_t us_if, ds_if;
+	int ret = -1, retry = 0;
+
+	dev = alloc_etherdev(sizeof(struct nss_clmapmgr_priv_t));
+	if (!dev) {
+		nss_clmapmgr_warning("Allocation of netdev failed\n");
+		return NULL;
+	}
+
+	nss_clmapmgr_setup(dev);
+
+	/*
+	 * Register net_device
+	 */
+	ret = register_netdev(dev);
+	if (ret) {
+		nss_clmapmgr_warning("%px: Netdevice registration failed\n", dev);
+		free_netdev(dev);
+		return NULL;
+	}
+
+	/*
+	 * Create NSS clmap downstream dynamic interface
+	 */
+	ds_if = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_DS);
+	if (ds_if < 0) {
+		nss_clmapmgr_warning("%px: NSS dynamic interface alloc failed for clmap downstream\n", dev);
+		goto deregister_netdev;
+	}
+
+	/*
+	 * Create NSS clmap upstream dynamic interface
+	 */
+	us_if = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US);
+	if (us_if < 0) {
+		nss_clmapmgr_warning("%px: NSS dynamic interface alloc failed for clmap upstream\n", dev);
+		goto dealloc_ds_node;
+	}
+
+	priv = (struct nss_clmapmgr_priv_t *)netdev_priv(dev);
+	priv->clmap_enabled = false;
+	priv->nss_if_number_us = us_if;
+	priv->nss_if_number_ds = ds_if;
+
+	/*
+	 * Register downstream clmap interface with NSS
+	 */
+	nss_ctx = nss_clmap_register(ds_if,
+				NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_DS,
+				nss_clmapmgr_ds_exception,
+	 			nss_clmapmgr_event_receive,
+				dev,
+				features);
+	if (!nss_ctx) {
+		nss_clmapmgr_info("%px: nss_clmap_register failed for downstream interface\n", dev);
+		goto dealloc_us_node;
+	}
+
+	/*
+	 * Register upstream clmap interface with NSS
+	 */
+	nss_ctx = nss_clmap_register(us_if,
+				NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US,
+				nss_clmapmgr_us_exception,
+	 			nss_clmapmgr_event_receive,
+				dev,
+				features);
+	if (!nss_ctx) {
+		nss_clmapmgr_info("%px: nss_clmap_register failed for upstream interface\n", dev);
+		goto unregister_ds;
+	}
+
+	/*
+	 * Register decongestion callback
+	 */
+	if (nss_cmn_register_queue_decongestion(nss_clmap_get_ctx(), nss_clmapmgr_decongestion_callback, dev) != NSS_CB_REGISTER_SUCCESS) {
+		nss_clmapmgr_warning("%px: failed to register decongestion callback\n", dev);
+		goto unregister_us;
+	}
+
+	/*
+	 * Success
+	 */
+	nss_clmapmgr_info("%px: nss_clmap_register() successful. nss_ctx = %px\n", dev, nss_ctx);
+	return dev;
+
+unregister_us:
+	nss_clmap_unregister(us_if);
+
+unregister_ds:
+	nss_clmap_unregister(ds_if);
+
+dealloc_us_node:
+	status = nss_dynamic_interface_dealloc_node(us_if, NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US);
+	if (status != NSS_TX_SUCCESS) {
+		if (++retry <= NSS_CLMAPMGR_CMD_MAX_RETRY_COUNT) {
+			goto dealloc_us_node;
+		}
+		nss_clmapmgr_error("%px: fatal Error, Unable to dealloc the node[%d] in the NSS FW!\n", dev, us_if);
+	}
+
+	retry = 0;
+dealloc_ds_node:
+	status = nss_dynamic_interface_dealloc_node(ds_if, NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_DS);
+	if (status != NSS_TX_SUCCESS) {
+		if (++retry <= NSS_CLMAPMGR_CMD_MAX_RETRY_COUNT) {
+			goto dealloc_ds_node;
+		}
+		nss_clmapmgr_error("%px: fatal Error, Unable to dealloc the node[%d] in the NSS FW!\n", dev, ds_if);
+	}
+
+deregister_netdev:
+	unregister_netdev(dev);
+	free_netdev(dev);
+
+	return NULL;
+}
+EXPORT_SYMBOL(nss_clmapmgr_netdev_create);
+
+/*
+ * Linux Net device Notifier
+ */
+static struct notifier_block nss_clmapmgr_notifier = {
+	.notifier_call = nss_clmapmgr_dev_event,
+};
+
+/*
+ * nss_clmapmgr_dev_init_module()
+ *	Client map module init function
+ */
+static int __init nss_clmapmgr_dev_init_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+	register_netdevice_notifier(&nss_clmapmgr_notifier);
+
+	return 0;
+}
+
+/*
+ * nss_clmapmgr_exit_module
+ *	Client map module exit function
+ */
+static void __exit nss_clmapmgr_exit_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return;
+	}
+#endif
+	/*
+	 * Unregister clmap interfaces created
+	 */
+	unregister_netdevice_notifier(&nss_clmapmgr_notifier);
+}
+
+module_init(nss_clmapmgr_dev_init_module);
+module_exit(nss_clmapmgr_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS client map manager");
diff --git a/qca-nss-clients/clmapmgr/nss_clmapmgr_private.h b/qca-nss-clients/clmapmgr/nss_clmapmgr_private.h
new file mode 100644
index 0000000..28b44d6
--- /dev/null
+++ b/qca-nss-clients/clmapmgr/nss_clmapmgr_private.h
@@ -0,0 +1,92 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_clmapmgr_private.h
+ *
+ * Private header file for NSS clmapmgr
+ */
+
+#ifndef _NSS_CLMAPMGR_PRIVATE_H_
+#define _NSS_CLMAPMGR_PRIVATE_H_
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/if_ether.h>
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+
+#include "nss_clmapmgr.h"
+
+/*
+ * clmap debug macros
+ */
+#if (NSS_CLMAPMGR_DEBUG_LEVEL < 1)
+#define nss_clmapmgr_assert(fmt, args...)
+#else
+#define nss_clmapmgr_assert(c)  BUG_ON(!(c));
+#endif
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_clmapmgr_warning(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_clmapmgr_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_clmapmgr_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_CLMAPMGR_DEBUG_LEVEL < 2)
+#define nss_clmapmgr_warning(s, ...)
+#else
+#define nss_clmapmgr_warning(s, ...) pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_CLMAPMGR_DEBUG_LEVEL < 3)
+#define nss_clmapmgr_info(s, ...)
+#else
+#define nss_clmapmgr_info(s, ...)   pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_CLMAPMGR_DEBUG_LEVEL < 4)
+#define nss_clmapmgr_trace(s, ...)
+#else
+#define nss_clmapmgr_trace(s, ...)  pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif
+#define nss_clmapmgr_error(s, ...) pr_err("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+/*
+ * nss_clmapmgr_priv_t
+ * 	Private structure for NSS clmapmgr.
+ */
+struct nss_clmapmgr_priv_t {
+	bool clmap_enabled;			/* Clmap status */
+	int nss_if_number_us;			/* Clmapmgr upstream NSS interface number */
+	int nss_if_number_ds;			/* Clmapmgr downstream NSS interface number */
+	struct rtnl_link_stats64 stats;		/* Netdev stats */
+};
+
+#endif
diff --git a/qca-nss-clients/dtls/v1.0/Makefile b/qca-nss-clients/dtls/v1.0/Makefile
new file mode 100644
index 0000000..410482a
--- /dev/null
+++ b/qca-nss-clients/dtls/v1.0/Makefile
@@ -0,0 +1,7 @@
+# Makefile for DTLS manager
+
+ccflags-y += $(NSS_CCFLAGS) -I$(obj)/../../exports
+ccflags-y += -DNSS_DTLSMGR_DEBUG_LEVEL=0
+
+obj-m += qca-nss-dtlsmgr.o
+qca-nss-dtlsmgr-objs := nss_connmgr_dtls.o nss_connmgr_dtls_netdev.o
diff --git a/qca-nss-clients/dtls/v1.0/nss_connmgr_dtls.c b/qca-nss-clients/dtls/v1.0/nss_connmgr_dtls.c
new file mode 100644
index 0000000..ec1356e
--- /dev/null
+++ b/qca-nss-clients/dtls/v1.0/nss_connmgr_dtls.c
@@ -0,0 +1,1047 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_connmgr_dtls.c
+ *	NSS DTLS Manager
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <net/ipv6.h>
+#include <linux/if_arp.h>
+#include <linux/etherdevice.h>
+#include <linux/atomic.h>
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+
+#include "nss_connmgr_dtls.h"
+
+/*
+ * Global DTLS context
+ */
+static struct nss_dtlsmgr_ctx g_ctx;
+
+static struct nss_dtlsmgr_crypto_algo dtlsmgr_algo[NSS_DTLSMGR_ALGO_MAX] = {
+	[NSS_DTLSMGR_ALGO_AES_CBC_SHA1_HMAC] = {
+		.cipher_algo = NSS_CRYPTO_CIPHER_AES_CBC,
+		.auth_algo = NSS_CRYPTO_AUTH_SHA1_HMAC,
+		.hash_len = NSS_CRYPTO_MAX_HASHLEN_SHA1 ,
+		.iv_len = NSS_CRYPTO_MAX_IVLEN_AES,
+	},
+	[NSS_DTLSMGR_ALGO_AES_CBC_SHA256_HMAC] = {
+		.cipher_algo = NSS_CRYPTO_CIPHER_AES_CBC,
+		.auth_algo = NSS_CRYPTO_AUTH_SHA256_HMAC,
+		.hash_len = NSS_CRYPTO_MAX_HASHLEN_SHA256 ,
+		.iv_len = NSS_CRYPTO_MAX_IVLEN_AES,
+	},
+	[NSS_DTLSMGR_ALGO_3DES_CBC_SHA1_HMAC] = {
+		.cipher_algo = NSS_CRYPTO_CIPHER_DES,
+		.auth_algo = NSS_CRYPTO_AUTH_SHA1_HMAC,
+		.hash_len = NSS_CRYPTO_MAX_HASHLEN_SHA1 ,
+		.iv_len = NSS_CRYPTO_MAX_IVLEN_DES,
+	},
+	[NSS_DTLSMGR_ALGO_3DES_CBC_SHA256_HMAC] = {
+		.cipher_algo = NSS_CRYPTO_CIPHER_DES,
+		.auth_algo = NSS_CRYPTO_AUTH_SHA256_HMAC,
+		.hash_len = NSS_CRYPTO_MAX_HASHLEN_SHA256,
+		.iv_len = NSS_CRYPTO_MAX_IVLEN_DES,
+	}
+};
+
+/*
+ * nss_dtlsmgr_session_insert()
+ *	Insert a DTLS session into global list of sessions.
+ *	Must be called with global context lock held.
+ */
+static bool nss_dtlsmgr_session_insert(struct nss_dtlsmgr_session *s)
+{
+	int32_t i;
+
+	assert_spin_locked(&g_ctx.lock);
+
+	for (i = 0; i < NSS_MAX_DTLS_SESSIONS; i++) {
+		if (g_ctx.session[i] == NULL) {
+			g_ctx.session[i] = s;
+			return true;
+		}
+	}
+
+	return false;
+}
+
+/*
+ * nss_dtlsmgr_session_remove()
+ *	Remove a DTLS session from list of sessions.
+ *	Must be called with global context lock held.
+ */
+static struct nss_dtlsmgr_session *nss_dtlsmgr_session_remove(uint32_t sif)
+{
+	int32_t i;
+	struct nss_dtlsmgr_session *s;
+
+	assert_spin_locked(&g_ctx.lock);
+
+	for (i = 0; i < NSS_MAX_DTLS_SESSIONS; i++) {
+		s = g_ctx.session[i];
+		if (!s)
+			continue;
+
+		nss_dtlsmgr_assert(s->magic == NSS_DTLSMGR_SESSION_MAGIC);
+		if (s->nss_dtls_if == sif) {
+			g_ctx.session[i] = NULL;
+			return s;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_dtlsmgr_session_find()
+ *	Find a DTLS session from list of sessions.
+ *	Must be called with global context lock held.
+ */
+static struct nss_dtlsmgr_session *nss_dtlsmgr_session_find(uint32_t sif)
+{
+	int32_t i;
+	struct nss_dtlsmgr_session *s;
+
+	assert_spin_locked(&g_ctx.lock);
+
+	for (i = 0; i < NSS_MAX_DTLS_SESSIONS; i++) {
+		s = g_ctx.session[i];
+		if (!s)
+			continue;
+
+		nss_dtlsmgr_assert(s->magic == NSS_DTLSMGR_SESSION_MAGIC);
+		if (s->nss_dtls_if == sif)
+			return s;
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_dtlsmgr_session_cleanup()
+ *	Cleanup DTLS session
+ */
+static void nss_dtlsmgr_session_cleanup(struct nss_dtlsmgr_session *ds)
+{
+	nss_crypto_status_t crypto_status;
+
+	nss_dtlsmgr_info("%px: DTLS session I/F %u cleanup\n",
+			 &g_ctx, ds->nss_dtls_if);
+
+	nss_dtls_unregister_if(ds->nss_dtls_if);
+
+	nss_dtlsmgr_netdev_destroy(ds);
+
+	nss_dynamic_interface_dealloc_node(ds->nss_dtls_if,
+					   NSS_DYNAMIC_INTERFACE_TYPE_DTLS);
+
+	crypto_status = nss_crypto_session_free(g_ctx.crypto_hdl,
+						ds->crypto_idx_encap);
+	if (crypto_status != NSS_CRYPTO_STATUS_OK) {
+		nss_dtlsmgr_info("%px: dtls I/F:%u, unable to free crypto session id:%d\n",
+				 &g_ctx, ds->nss_dtls_if, ds->crypto_idx_encap);
+	}
+
+	crypto_status = nss_crypto_session_free(g_ctx.crypto_hdl,
+						ds->crypto_idx_decap);
+	if (crypto_status != NSS_CRYPTO_STATUS_OK) {
+		nss_dtlsmgr_info("%px: dtls I/F:%u, unable to free crypto session id:%d\n",
+				 &g_ctx, ds->nss_dtls_if, ds->crypto_idx_decap);
+	}
+
+	if (ds->cidx_decap_pending != NSS_CRYPTO_MAX_IDXS) {
+		crypto_status = nss_crypto_session_free(g_ctx.crypto_hdl,
+							ds->cidx_decap_pending);
+		if (crypto_status != NSS_CRYPTO_STATUS_OK) {
+			nss_dtlsmgr_info("%px: dtls I/F:%u, unable to free crypto session id:%d\n", &g_ctx, ds->nss_dtls_if, ds->cidx_decap_pending);
+		}
+	}
+
+	if (ds->cidx_encap_pending != NSS_CRYPTO_MAX_IDXS) {
+		crypto_status = nss_crypto_session_free(g_ctx.crypto_hdl,
+							ds->cidx_encap_pending);
+		if (crypto_status != NSS_CRYPTO_STATUS_OK) {
+			nss_dtlsmgr_info("%px: dtls I/F:%u, unable to free crypto session id:%d\n", &g_ctx, ds->nss_dtls_if, ds->cidx_encap_pending);
+		}
+	}
+
+	ds->magic = 0;
+	kfree(ds);
+}
+
+/*
+ * nss_dtlsmgr_session_find_and_ref()
+ *	Find a DTLS session from list of sessions and
+ *	increments reference count. Must be called with
+ *	global context lock held.
+ */
+static struct nss_dtlsmgr_session *nss_dtlsmgr_session_find_and_ref(uint32_t sif)
+{
+	struct nss_dtlsmgr_session *s;
+
+	s = nss_dtlsmgr_session_find(sif);
+	if (atomic_inc_and_test(&s->ref)) {
+		nss_dtlsmgr_assert(false);
+	}
+
+	return s;
+}
+
+/*
+ * nss_dtlsmgr_session_ref_dec()
+ *	Decrement reference count of a DTLS session.
+ *	Perform session cleanup if reference count falls to zero.
+ */
+static void nss_dtlsmgr_session_ref_dec(struct nss_dtlsmgr_session *s)
+{
+	if (atomic_dec_and_test(&s->ref)) {
+		nss_dtlsmgr_session_cleanup(s);
+	}
+}
+
+/*
+ * nss_connmgr_dtls_data_receive()
+ *	Handler to receive packets from NSS.
+ */
+static void nss_connmgr_dtls_data_receive(struct net_device *dev,
+					  struct sk_buff *skb,
+					  struct napi_struct *napi)
+{
+	struct nss_dtlsmgr_netdev_priv *priv;
+	struct nss_dtlsmgr_session *s;
+	__be32 meta;
+
+	BUG_ON(dev == NULL);
+	BUG_ON(skb == NULL);
+
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+	s = priv->s;
+
+	/*
+	 * Get DTLS metadata
+	 */
+	meta = *(__be32 *)skb->data;
+	meta = ntohl(meta);
+	if (NSS_DTLSMGR_METADATA_CTYPE(meta) != NSS_DTLSMGR_CTYPE_APP) {
+		nss_dtlsmgr_info("%px: Dropping non app dtls pkt\n", skb);
+		dev_kfree_skb_any(skb);
+		dev_put(dev);
+		return;
+	}
+
+	if (NSS_DTLSMGR_METADATA_ERROR(meta) != NSS_DTLSMGR_METADATA_ERROR_OK) {
+		nss_dtlsmgr_info("%px: Dropping error pkt\n", skb);
+		dev_kfree_skb_any(skb);
+		dev_put(dev);
+		return;
+	}
+
+	/*
+	 * Remove four bytes at start of
+	 * buffer containing the DTLS metadata.
+	 */
+	skb_pull(skb, NSS_DTLSMGR_METADATA_LEN);
+
+	skb_reset_network_header(skb);
+	skb->pkt_type = PACKET_HOST;
+	skb->skb_iif = dev->ifindex;
+	skb->dev = dev;
+	if (s->flags & NSS_DTLSMGR_HDR_IPV6)
+		skb->protocol = htons(ETH_P_IPV6);
+	else
+		skb->protocol = htons(ETH_P_IP);
+
+	netif_receive_skb(skb);
+	dev_put(dev);
+}
+
+/*
+ * nss_connmgr_dtls_event_receive()
+ *	Event Callback to receive events from NSS
+ */
+static void nss_connmgr_dtls_event_receive(void *if_ctx,
+					   struct nss_dtls_msg *tnlmsg)
+{
+	struct nss_dtlsmgr_session *ds = (struct nss_dtlsmgr_session *)if_ctx;
+	struct nss_dtlsmgr_session_stats_update stats;
+	struct nss_dtls_session_stats *msg_stats;
+
+	spin_lock(&g_ctx.lock);
+	ds = nss_dtlsmgr_session_find_and_ref(tnlmsg->cm.interface);
+	spin_unlock(&g_ctx.lock);
+
+	if (!ds) {
+		return;
+	}
+
+	switch (tnlmsg->cm.type) {
+	case NSS_DTLS_MSG_SESSION_STATS:
+		if (ds->stats_update_cb == NULL)
+			break;
+
+		memset(&stats, 0, sizeof(struct nss_dtlsmgr_session_stats_update));
+		msg_stats = &tnlmsg->msg.stats;
+
+		stats.tx_pkts = msg_stats->node_stats.tx_packets;
+		stats.rx_pkts = msg_stats->node_stats.rx_packets;
+		stats.rx_dropped = nss_cmn_rx_dropped_sum(&msg_stats->node_stats);
+		stats.tx_auth_done = msg_stats->tx_auth_done;
+		stats.rx_auth_done = msg_stats->rx_auth_done;
+		stats.tx_cipher_done = msg_stats->tx_cipher_done;
+		stats.rx_cipher_done = msg_stats->rx_cipher_done;
+		stats.tx_cbuf_alloc_fail = msg_stats->tx_cbuf_alloc_fail;
+		stats.rx_cbuf_alloc_fail = msg_stats->rx_cbuf_alloc_fail;
+		stats.tx_cenqueue_fail = msg_stats->tx_cenqueue_fail;
+		stats.rx_cenqueue_fail = msg_stats->rx_cenqueue_fail;
+		stats.tx_dropped_hroom = msg_stats->tx_dropped_hroom;
+		stats.tx_dropped_troom = msg_stats->tx_dropped_troom;
+		stats.tx_forward_enqueue_fail = msg_stats->tx_forward_enqueue_fail;
+		stats.rx_forward_enqueue_fail = msg_stats->rx_forward_enqueue_fail;
+		stats.rx_invalid_version = msg_stats->rx_invalid_version;
+		stats.rx_invalid_epoch = msg_stats->rx_invalid_epoch;
+		stats.rx_malformed = msg_stats->rx_malformed;
+		stats.rx_cipher_fail = msg_stats->rx_cipher_fail;
+		stats.rx_auth_fail = msg_stats->rx_auth_fail;
+		stats.rx_capwap_classify_fail = msg_stats->rx_capwap_classify_fail;
+		stats.rx_replay_fail = msg_stats->rx_replay_fail;
+		stats.rx_replay_duplicate = msg_stats->rx_replay_duplicate;
+		stats.rx_replay_out_of_window = msg_stats->rx_replay_out_of_window;
+		stats.outflow_queue_full = msg_stats->outflow_queue_full;
+		stats.decap_queue_full = msg_stats->decap_queue_full;
+		stats.pbuf_alloc_fail = msg_stats->pbuf_alloc_fail;
+		stats.pbuf_copy_fail = msg_stats->pbuf_copy_fail;
+		stats.epoch = msg_stats->epoch;
+		stats.tx_seq_high = msg_stats->tx_seq_high;
+		stats.tx_seq_low = msg_stats->tx_seq_low;
+
+		ds->stats_update_cb(ds->nss_dtls_if, &stats);
+		break;
+
+	default:
+		nss_dtlsmgr_info("%px: Unknown Event from NSS\n", &g_ctx);
+		break;
+	}
+
+	nss_dtlsmgr_session_ref_dec(ds);
+}
+
+/*
+ * nss_dtlsmgr_alloc_crypto()
+ *	Allocate a crypto session and update encrypt/decrypt session parameters.
+ */
+nss_dtlsmgr_status_t nss_dtlsmgr_alloc_crypto(struct nss_dtlsmgr_crypto *crypto, uint32_t *crypto_idx, bool encrypt)
+{
+	struct nss_dtlsmgr_crypto_algo *algo;
+	struct nss_crypto_params params;
+	struct nss_crypto_key cipher;
+	struct nss_crypto_key auth;
+
+	memset(&cipher, 0, sizeof(struct nss_crypto_key));
+	memset(&auth, 0, sizeof(struct nss_crypto_key));
+
+	if (crypto->algo >= NSS_DTLSMGR_ALGO_MAX) {
+		nss_dtlsmgr_info("%px: invalid algorithm type %d", &g_ctx, crypto->algo);
+		return NSS_DTLSMGR_FAIL_NOCRYPTO;
+	}
+
+	algo = &dtlsmgr_algo[crypto->algo];
+
+	cipher.algo = algo->cipher_algo;
+	cipher.key = crypto->cipher_key.data;
+	cipher.key_len = crypto->cipher_key.len;
+
+	auth.algo = algo->auth_algo;
+	auth.key = crypto->auth_key.data;
+	auth.key_len = crypto->auth_key.len;
+
+	if (nss_crypto_session_alloc(g_ctx.crypto_hdl, &cipher, &auth, crypto_idx) != NSS_CRYPTO_STATUS_OK) {
+		nss_dtlsmgr_info("%px: DTLS crypto alloc failed\n", &g_ctx);
+		return NSS_DTLSMGR_FAIL_NOCRYPTO;
+	}
+
+	/*
+	 * Update crypto session
+	 */
+	memset(&params, 0, sizeof(struct nss_crypto_params));
+	params.cipher_skip = NSS_DTLSMGR_HDR_LEN + algo->iv_len;
+	params.auth_skip = 0;
+	params.req_type = (encrypt ? NSS_CRYPTO_REQ_TYPE_ENCRYPT : NSS_CRYPTO_REQ_TYPE_DECRYPT);
+	params.req_type |= NSS_CRYPTO_REQ_TYPE_AUTH;
+
+	if (nss_crypto_session_update(g_ctx.crypto_hdl, *crypto_idx, &params) != NSS_CRYPTO_STATUS_OK) {
+		nss_dtlsmgr_info("%px: failed to update crypto session %d", &g_ctx, *crypto_idx);
+		nss_crypto_session_free(g_ctx.crypto_hdl, *crypto_idx);
+		return NSS_DTLSMGR_FAIL_NOCRYPTO;
+	}
+
+	nss_dtlsmgr_info("%px: auth_skip:%d cipher_skip:%d\n", &g_ctx, params.auth_skip, params.cipher_skip);
+	return NSS_DTLSMGR_OK;
+}
+
+/*
+ * nss_dtlsmgr_session_create()
+ *	Create DTLS session and associated crypto sessions.
+ */
+struct net_device *nss_dtlsmgr_session_create(struct nss_dtlsmgr_config *cfg)
+{
+	struct nss_dtlsmgr_session *ds;
+	struct nss_dtls_msg dtlsmsg;
+	int32_t i = 0;
+	struct nss_dtlsmgr_crypto_algo *encap_algo, *decap_algo;
+	struct nss_dtls_session_configure *scfg;
+	nss_tx_status_t status;
+	nss_crypto_status_t crypto_status;
+	enum nss_dtlsmgr_status ret = NSS_DTLSMGR_FAIL;
+	uint32_t features = 0;
+	uint32_t mtu_adjust;
+
+	if ((cfg->encap.ver != NSS_DTLSMGR_VERSION_1_0) && (cfg->encap.ver != NSS_DTLSMGR_VERSION_1_2)) {
+		nss_dtlsmgr_warn("%px: Invalid DTLS version\n", &g_ctx);
+		return NULL;
+	}
+
+	/*
+	 * Allocate memory for new dtls session
+	 */
+	ds = kzalloc(sizeof(struct nss_dtlsmgr_session), GFP_KERNEL);
+	if (!ds) {
+		nss_dtlsmgr_info("%px: DTLS client allocation failed\n", &g_ctx);
+		return NULL;
+	}
+
+	/*
+	 * Create crypto session for encap
+	 */
+	ret = nss_dtlsmgr_alloc_crypto(&cfg->encap.crypto, &ds->crypto_idx_encap, true);
+	if (ret != NSS_DTLSMGR_OK) {
+		nss_dtlsmgr_info("failed to create encap session %d", ret);
+		goto dtls_crypto_encap_alloc_fail;
+	}
+
+	/*
+	 * Create crypto session for decap
+	 */
+	ret = nss_dtlsmgr_alloc_crypto(&cfg->decap.crypto, &ds->crypto_idx_decap, false);
+	if (ret != NSS_DTLSMGR_OK) {
+		nss_dtlsmgr_info("failed to create decap session %d", ret);
+		goto dtls_crypto_decap_alloc_fail;
+	}
+
+	/*
+	 * Allocate NSS dynamic interface
+	 */
+	ds->nss_dtls_if = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_DTLS);
+	if (ds->nss_dtls_if == -1) {
+		nss_dtlsmgr_info("%px: DTLS dynamic I/F alloc failed\n", &g_ctx);
+		goto dtls_dynamic_if_alloc_fail;
+	}
+
+	/*
+	 * Create netdevice
+	 */
+	if (nss_dtlsmgr_netdev_create(ds) != NSS_DTLSMGR_OK) {
+		nss_dtlsmgr_info("%px: DTLS netdev creation failed\n", &g_ctx);
+		goto dtls_netdev_create_fail;
+	}
+
+	/*
+	 * Register NSS DTLS I/F
+	 */
+	ds->nss_ctx = nss_dtls_register_if(ds->nss_dtls_if,
+					   nss_connmgr_dtls_data_receive,
+					   nss_connmgr_dtls_event_receive,
+					   ds->netdev, features,
+					   (void *)ds);
+	if (ds->nss_ctx == NULL) {
+		nss_dtlsmgr_info("%px: DTLS dynamic I/F register failed\n", &g_ctx);
+		goto dtls_dynamic_if_register_fail;
+	}
+
+	/*
+	 * Initialize DTLS manager session
+	 */
+	ds->magic = NSS_DTLSMGR_SESSION_MAGIC;
+	ds->flags = cfg->flags;
+	ds->ver = cfg->encap.ver;
+	ds->sport = cfg->encap.sport;
+	ds->dport = cfg->encap.dport;
+	ds->epoch = cfg->encap.epoch;
+	ds->ip_ttl = cfg->encap.ip_ttl;
+	ds->nss_app_if = cfg->decap.nexthop_ifnum;
+	ds->window_size = cfg->decap.window_size;
+	ds->stats_update_cb = NULL; /* TODO */
+	ds->cidx_encap_pending = NSS_CRYPTO_MAX_IDXS;
+	ds->cidx_decap_pending = NSS_CRYPTO_MAX_IDXS;
+	atomic_set(&ds->ref, 1);
+
+	if (ds->flags & NSS_DTLSMGR_HDR_IPV6) {
+		for (i = 0; i < 4 ; i++) {
+			ds->sip.ipv6[i] = cfg->encap.sip[i];
+			ds->dip.ipv6[i] = cfg->encap.dip[i];
+		}
+	} else {
+		ds->sip.ipv4 = cfg->encap.sip[0];
+		ds->dip.ipv4 = cfg->encap.dip[0];
+	}
+
+	/*
+	 * Insert session into DTLS manager list
+	 */
+	spin_lock_bh(&g_ctx.lock);
+	if (!nss_dtlsmgr_session_insert(ds)) {
+		spin_unlock_bh(&g_ctx.lock);
+		goto dtls_session_insert_fail;
+	}
+	spin_unlock_bh(&g_ctx.lock);
+
+	/*
+	 * Send DTLS configure message to NSS
+	 */
+	memset(&dtlsmsg, 0, sizeof(struct nss_dtls_msg));
+	nss_dtls_msg_init(&dtlsmsg, ds->nss_dtls_if,
+			  NSS_DTLS_MSG_SESSION_CONFIGURE,
+			  sizeof(struct nss_dtls_session_configure),
+			  NULL, NULL);
+
+	encap_algo = &dtlsmgr_algo[cfg->encap.crypto.algo];
+	decap_algo = &dtlsmgr_algo[cfg->decap.crypto.algo];
+
+	scfg = &dtlsmsg.msg.cfg;
+	scfg->ver = ds->ver;
+	scfg->flags = ds->flags;
+	scfg->crypto_idx_encap = ds->crypto_idx_encap;
+	scfg->crypto_idx_decap = ds->crypto_idx_decap;
+	scfg->iv_len_encap = encap_algo->iv_len;
+	scfg->iv_len_decap = decap_algo->iv_len;
+	scfg->hash_len_encap = encap_algo->hash_len;
+	scfg->hash_len_decap = decap_algo->hash_len;
+	scfg->cipher_algo_encap = encap_algo->cipher_algo;
+	scfg->cipher_algo_decap = decap_algo->cipher_algo;
+	scfg->auth_algo_encap = encap_algo->auth_algo;
+	scfg->auth_algo_decap = decap_algo->auth_algo;
+	scfg->nss_app_if = ds->nss_app_if;
+	scfg->sport = ds->sport;
+	scfg->dport = ds->dport;
+	scfg->epoch = ds->epoch;
+	scfg->window_size = ds->window_size;
+	scfg->oip_ttl = ds->ip_ttl;
+
+	if (ds->flags & NSS_DTLSMGR_HDR_IPV6) {
+		for (i = 0; i < 4; i++) {
+			scfg->sip[i] = ds->sip.ipv6[i];
+			scfg->dip[i] = ds->dip.ipv6[i];
+		}
+	} else {
+		scfg->sip[0] = ds->sip.ipv4;
+		scfg->dip[0] = ds->dip.ipv4;
+	}
+
+	status = nss_dtls_tx_msg_sync(ds->nss_ctx, &dtlsmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_dtlsmgr_info("%px: DTLS cfg msg tx failed\n", &g_ctx);
+		goto dtls_msg_tx_fail;
+	}
+
+	/*
+	 * Adjust MTU of netdev
+	 */
+	mtu_adjust = NSS_DTLSMGR_HDR_LEN;
+	mtu_adjust += sizeof(struct udphdr);
+
+	if (ds->flags & NSS_DTLSMGR_HDR_IPV6)
+		mtu_adjust += sizeof(struct ipv6hdr);
+	else
+		mtu_adjust += sizeof(struct iphdr);
+
+	if (ds->flags & NSS_DTLSMGR_HDR_CAPWAP)
+		mtu_adjust += NSS_DTLSMGR_CAPWAPHDR_LEN;
+
+	mtu_adjust += ((scfg->iv_len_encap * 2) + scfg->hash_len_encap);
+
+	ds->netdev->mtu -= mtu_adjust;
+
+	nss_dtlsmgr_info("%px: NSS DTLS session I/F:%d(%s) created\n",
+			 &g_ctx, ds->nss_dtls_if, ds->netdev->name);
+
+	return ds->netdev;
+
+dtls_msg_tx_fail:
+	spin_lock_bh(&g_ctx.lock);
+	nss_dtlsmgr_session_remove(ds->nss_dtls_if);
+	spin_unlock_bh(&g_ctx.lock);
+
+dtls_session_insert_fail:
+	nss_dtls_unregister_if(ds->nss_dtls_if);
+
+dtls_dynamic_if_register_fail:
+	nss_dtlsmgr_netdev_destroy(ds);
+
+dtls_netdev_create_fail:
+	nss_dynamic_interface_dealloc_node(ds->nss_dtls_if,
+					   NSS_DYNAMIC_INTERFACE_TYPE_DTLS);
+
+dtls_dynamic_if_alloc_fail:
+	crypto_status = nss_crypto_session_free(g_ctx.crypto_hdl,
+						ds->crypto_idx_decap);
+	if (crypto_status != NSS_CRYPTO_STATUS_OK) {
+		nss_dtlsmgr_info("%px: dtls I/F:%u, unable to free crypto session id:%d\n", &g_ctx, ds->nss_dtls_if, ds->crypto_idx_decap);
+	}
+
+dtls_crypto_decap_alloc_fail:
+	crypto_status = nss_crypto_session_free(g_ctx.crypto_hdl,
+						ds->crypto_idx_encap);
+	if (crypto_status != NSS_CRYPTO_STATUS_OK) {
+		nss_dtlsmgr_info("%px: dtls I/F:%u, unable to free crypto session id:%d\n", &g_ctx, ds->nss_dtls_if, ds->crypto_idx_encap);
+	}
+
+dtls_crypto_encap_alloc_fail:
+	ds->magic = 0;
+	kfree(ds);
+	return NULL;
+}
+EXPORT_SYMBOL(nss_dtlsmgr_session_create);
+
+/*
+ * nss_dtlsmgr_session_destroy()
+ *	Destroy DTLS session
+ */
+nss_dtlsmgr_status_t nss_dtlsmgr_session_destroy(struct net_device *dev)
+{
+	struct nss_dtlsmgr_netdev_priv *priv;
+	struct nss_dtlsmgr_session *ds;
+	nss_tx_status_t nss_status;
+	struct nss_dtls_msg dtlsmsg;
+
+	priv = netdev_priv(dev);
+	ds = priv->s;
+
+	if (!ds) {
+		return NSS_DTLSMGR_FAIL;
+	}
+
+	/*
+	 * Send DTLS session destroy command to FW
+	 */
+	memset(&dtlsmsg, 0, sizeof(struct nss_dtls_msg));
+	nss_dtls_msg_init(&dtlsmsg, (uint16_t)ds->nss_dtls_if,
+			  NSS_DTLS_MSG_SESSION_DESTROY, 0, NULL, NULL);
+
+	nss_status = nss_dtls_tx_msg_sync(ds->nss_ctx, &dtlsmsg);
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_dtlsmgr_warn("%px: Failed to send DTLS session destroy for I/F %u", &g_ctx, ds->nss_dtls_if);
+
+		return NSS_DTLSMGR_FAIL;
+	}
+
+	spin_lock_bh(&g_ctx.lock);
+	ds = nss_dtlsmgr_session_remove(ds->nss_dtls_if);
+	spin_unlock_bh(&g_ctx.lock);
+
+	if (!ds) {
+		return NSS_DTLSMGR_FAIL;
+	}
+
+	/*
+	 * Decrement reference count so as to drop it to zero
+	 */
+	nss_dtlsmgr_session_ref_dec(ds);
+
+	nss_dtlsmgr_info("%px: DTLS session I/F %u disabled\n", &g_ctx, ds->nss_dtls_if);
+
+	return NSS_DTLSMGR_OK;
+}
+EXPORT_SYMBOL(nss_dtlsmgr_session_destroy);
+
+/*
+ * nss_dtlsmgr_session_update_decap()
+ *	Update pending decap cipher of a DTLS session.
+ */
+nss_dtlsmgr_status_t nss_dtlsmgr_session_update_decap(struct net_device *dev, struct nss_dtlsmgr_config_update *udata)
+{
+	struct nss_dtlsmgr_netdev_priv *priv;
+	struct nss_dtlsmgr_session *ds;
+	nss_tx_status_t nss_status;
+	nss_crypto_status_t crypto_status;
+	enum nss_dtlsmgr_status ret;
+	struct nss_dtls_msg dtlsmsg;
+	struct nss_dtls_session_cipher_update *update;
+	struct nss_dtlsmgr_crypto_algo *decap_algo;
+
+	priv = netdev_priv(dev);
+	ds = priv->s;
+	if (!ds) {
+		return NSS_DTLSMGR_FAIL;
+	}
+
+	/*
+	 * Free any crypto session, for the decap pending cipher
+	 * state, allocated by a previous call to this API but
+	 * were subsequently not used for packet processing.
+	 */
+	if (ds->cidx_decap_pending != NSS_CRYPTO_MAX_IDXS) {
+		crypto_status = nss_crypto_session_free(g_ctx.crypto_hdl, ds->cidx_decap_pending);
+		if (crypto_status != NSS_CRYPTO_STATUS_OK) {
+			nss_dtlsmgr_info("%px: dtls I/F:%u, unable to free crypto session id:%d\n",
+					 &g_ctx, ds->nss_dtls_if, ds->cidx_decap_pending);
+		}
+
+		ds->cidx_decap_pending = NSS_CRYPTO_MAX_IDXS;
+	}
+
+	/*
+	 * Alloc crypto session for decap
+	 */
+	ret = nss_dtlsmgr_alloc_crypto(&udata->crypto, &ds->cidx_decap_pending, false);
+	if (ret != NSS_DTLSMGR_OK) {
+		nss_dtlsmgr_info("failed to rekey decap session %d", ret);
+		ds->cidx_decap_pending = NSS_CRYPTO_MAX_IDXS;
+		nss_dtlsmgr_session_ref_dec(ds);
+		return NSS_DTLSMGR_FAIL_NOCRYPTO;
+	}
+
+	decap_algo = &dtlsmgr_algo[udata->crypto.algo];
+
+	/*
+	 * Initialize DTLS session Rx cipher update message
+	 */
+	memset(&dtlsmsg, 0, sizeof(struct nss_dtls_msg));
+	update = &dtlsmsg.msg.cipher_update;
+	update->crypto_idx = ds->cidx_decap_pending;
+	update->epoch = udata->epoch;
+	update->iv_len = decap_algo->iv_len;
+	update->hash_len = decap_algo->hash_len;
+	update->auth_algo = decap_algo->auth_algo;
+	update->cipher_algo = decap_algo->cipher_algo;
+
+	nss_dtls_msg_init(&dtlsmsg, (uint16_t)ds->nss_dtls_if,
+			  NSS_DTLS_MSG_REKEY_DECAP_CIPHER_UPDATE,
+			  sizeof(struct nss_dtls_session_cipher_update), NULL, NULL);
+
+	/*
+	 * Send DTLS session Rx cipher update command to FW
+	 */
+	nss_status = nss_dtls_tx_msg_sync(ds->nss_ctx, &dtlsmsg);
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_crypto_session_free(g_ctx.crypto_hdl,
+					ds->cidx_decap_pending);
+		ds->cidx_decap_pending = NSS_CRYPTO_MAX_IDXS;
+		nss_dtlsmgr_session_ref_dec(ds);
+		return NSS_DTLSMGR_FAIL;
+	}
+
+	nss_dtlsmgr_session_ref_dec(ds);
+	return NSS_DTLSMGR_OK;
+}
+EXPORT_SYMBOL(nss_dtlsmgr_session_update_decap);
+
+/*
+ * nss_dtlsmgr_session_update_encap()
+ *	Update pending encap cipher of a DTLS session.
+ */
+nss_dtlsmgr_status_t nss_dtlsmgr_session_update_encap(struct net_device *dev, struct nss_dtlsmgr_config_update *udata)
+{
+	struct nss_dtlsmgr_netdev_priv *priv;
+	struct nss_dtlsmgr_session *ds;
+	nss_tx_status_t nss_status;
+	nss_crypto_status_t crypto_status;
+	enum nss_dtlsmgr_status ret;
+	struct nss_dtls_msg dtlsmsg;
+	struct nss_dtls_session_cipher_update *update;
+	struct nss_dtlsmgr_crypto_algo *encap_algo;
+
+	priv = netdev_priv(dev);
+	ds = priv->s;
+	if (!ds) {
+		return NSS_DTLSMGR_FAIL;
+	}
+
+	/*
+	 * Free any crypto session, for the encap pending cipher
+	 * state, allocated by a previous call to this API but
+	 * were subsequently not used for packet processing.
+	 */
+	if (ds->cidx_encap_pending != NSS_CRYPTO_MAX_IDXS) {
+		crypto_status = nss_crypto_session_free(g_ctx.crypto_hdl,
+							ds->cidx_encap_pending);
+		if (crypto_status != NSS_CRYPTO_STATUS_OK) {
+			nss_dtlsmgr_info("%px: dtls I/F:%u, unable to free crypto session id:%d\n", &g_ctx, ds->nss_dtls_if, ds->cidx_encap_pending);
+		}
+
+		ds->cidx_encap_pending = NSS_CRYPTO_MAX_IDXS;
+	}
+
+	/*
+	 * Alloc crypto session for decap
+	 */
+	ret = nss_dtlsmgr_alloc_crypto(&udata->crypto, &ds->cidx_encap_pending, true);
+	if (ret != NSS_DTLSMGR_OK) {
+		nss_dtlsmgr_info("failed to rekey encap session %d", ret);
+		ds->cidx_encap_pending = NSS_CRYPTO_MAX_IDXS;
+		nss_dtlsmgr_session_ref_dec(ds);
+		return NSS_DTLSMGR_FAIL_NOCRYPTO;
+	}
+
+	encap_algo = &dtlsmgr_algo[udata->crypto.algo];
+
+	/*
+	 * Initialize DTLS session Tx cipher update message
+	 */
+	memset(&dtlsmsg, 0, sizeof(struct nss_dtls_msg));
+	update = &dtlsmsg.msg.cipher_update;
+	update->crypto_idx = ds->cidx_encap_pending;
+	update->epoch = udata->epoch;
+	update->iv_len = encap_algo->iv_len;
+	update->hash_len = encap_algo->hash_len;
+	update->auth_algo = encap_algo->auth_algo;
+	update->cipher_algo = encap_algo->cipher_algo;
+
+	nss_dtls_msg_init(&dtlsmsg, (uint16_t)ds->nss_dtls_if,
+			  NSS_DTLS_MSG_REKEY_ENCAP_CIPHER_UPDATE,
+			  sizeof(struct nss_dtls_session_cipher_update), NULL, NULL);
+
+	/*
+	 * Send DTLS session Rx cipher update command to FW
+	 */
+	nss_status = nss_dtls_tx_msg_sync(ds->nss_ctx, &dtlsmsg);
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_crypto_session_free(g_ctx.crypto_hdl,
+					ds->cidx_encap_pending);
+		ds->cidx_encap_pending = NSS_CRYPTO_MAX_IDXS;
+		nss_dtlsmgr_session_ref_dec(ds);
+		return NSS_DTLSMGR_FAIL;
+	}
+
+	nss_dtlsmgr_session_ref_dec(ds);
+	return NSS_DTLSMGR_OK;
+}
+EXPORT_SYMBOL(nss_dtlsmgr_session_update_encap);
+
+/*
+ * nss_dtlsmgr_session_switch_decap()
+ *	Set pending decap cipher state of a DTLS session to current.
+ */
+bool nss_dtlsmgr_session_switch_decap(struct net_device *dev)
+{
+	struct nss_dtlsmgr_netdev_priv *priv;
+	struct nss_dtlsmgr_session *ds;
+	nss_tx_status_t nss_status;
+	struct nss_dtls_msg dtlsmsg;
+
+	priv = netdev_priv(dev);
+	ds = priv->s;
+	if (!ds) {
+		return false;
+	}
+
+	memset(&dtlsmsg, 0, sizeof(struct nss_dtls_msg));
+	nss_dtls_msg_init(&dtlsmsg, (uint16_t)ds->nss_dtls_if,
+			  NSS_DTLS_MSG_REKEY_DECAP_CIPHER_SWITCH,
+			  0, NULL, NULL);
+
+	/*
+	 * Send DTLS session Rx cipher switch command to FW
+	 */
+	nss_status = nss_dtls_tx_msg_sync(ds->nss_ctx, &dtlsmsg);
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_dtlsmgr_session_ref_dec(ds);
+		return false;
+	}
+
+	ds->crypto_idx_decap = ds->cidx_decap_pending;
+	ds->cidx_decap_pending = NSS_CRYPTO_MAX_IDXS;
+
+	nss_dtlsmgr_session_ref_dec(ds);
+	return true;
+}
+EXPORT_SYMBOL(nss_dtlsmgr_session_switch_decap);
+
+/*
+ * nss_dtlsmgr_session_switch_encap()
+ *	Set pending encap cipher state of a DTLS session to current.
+ */
+bool nss_dtlsmgr_session_switch_encap(struct net_device *dev)
+{
+	struct nss_dtlsmgr_netdev_priv *priv;
+	struct nss_dtlsmgr_session *ds;
+	nss_tx_status_t nss_status;
+	struct nss_dtls_msg dtlsmsg;
+
+	priv = netdev_priv(dev);
+	ds = priv->s;
+	if (!ds) {
+		return false;
+	}
+
+	memset(&dtlsmsg, 0, sizeof(struct nss_dtls_msg));
+	nss_dtls_msg_init(&dtlsmsg, (uint16_t)ds->nss_dtls_if,
+			  NSS_DTLS_MSG_REKEY_ENCAP_CIPHER_SWITCH,
+			  0, NULL, NULL);
+
+	/*
+	 * Send DTLS session Tx cipher switch command to FW
+	 */
+	nss_status = nss_dtls_tx_msg_sync(ds->nss_ctx, &dtlsmsg);
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_dtlsmgr_session_ref_dec(ds);
+		return false;
+	}
+
+	ds->crypto_idx_encap = ds->cidx_encap_pending;
+	ds->cidx_encap_pending = NSS_CRYPTO_MAX_IDXS;
+
+	nss_dtlsmgr_session_ref_dec(ds);
+	return true;
+}
+EXPORT_SYMBOL(nss_dtlsmgr_session_switch_encap);
+
+/*
+ * nss_dtlsmgr_get_interface()
+ *	Returns NSS DTLS interface number for encap/decap on success.
+ */
+int32_t nss_dtlsmgr_get_interface(struct net_device *dev, enum nss_dtlsmgr_interface_type type)
+{
+	int32_t ifnum;
+
+	if (type > NSS_DTLSMGR_INTERFACE_TYPE_MAX) {
+		nss_dtlsmgr_warn("%px: invalid interface type %d", dev, type);
+		return -EINVAL;
+	}
+
+	ifnum = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_DTLS);
+	if (ifnum < 0) {
+		nss_dtlsmgr_warn("%px: couldn't find DTLS interface number (%d)", dev, ifnum);
+		return ifnum;
+	}
+
+	ifnum = nss_dtls_get_ifnum_with_coreid(ifnum);
+
+	return ifnum;
+}
+EXPORT_SYMBOL(nss_dtlsmgr_get_interface);
+
+/*
+ * nss_dtls_crypto_attach()
+ */
+static nss_crypto_user_ctx_t nss_dtls_crypto_attach(nss_crypto_handle_t crypto)
+{
+	struct nss_dtlsmgr_ctx *sc = &g_ctx;
+
+	sc->crypto_hdl = crypto;
+	nss_dtlsmgr_info("%px: DTLS client crypto attach\n", &g_ctx);
+	return (nss_crypto_user_ctx_t)sc;
+}
+
+/*
+ * nss_dtls_crypto_detach()
+ */
+static void nss_dtls_crypto_detach(nss_crypto_user_ctx_t uctx)
+{
+	struct nss_dtlsmgr_ctx *sc = NULL;
+
+	sc = (struct nss_dtlsmgr_ctx *)uctx;
+	nss_dtlsmgr_assert(sc == &g_ctx);
+
+	sc->crypto_hdl = NULL;
+	nss_dtlsmgr_info("%px: DTLS client crypto detach\n", &g_ctx);
+}
+
+/*
+ * nss_dtls_init_module()
+ */
+int __init nss_dtls_init_module(void)
+{
+	int32_t i;
+
+	nss_dtlsmgr_info("%px: NSS DTLS Manager\n", &g_ctx);
+
+	for (i = 0; i < NSS_MAX_DTLS_SESSIONS; i++) {
+		g_ctx.session[i] = NULL;
+	}
+
+	spin_lock_init(&(g_ctx.lock));
+	nss_crypto_register_user(nss_dtls_crypto_attach,
+				 nss_dtls_crypto_detach,
+				 "nss-dtls");
+	return 0;
+}
+
+/*
+ * nss_dtls_destroy_all_sessions()
+ */
+static void nss_dtls_destroy_all_sessions(void)
+{
+	nss_tx_status_t nss_status;
+	struct nss_dtls_msg dtlsmsg;
+	struct nss_dtlsmgr_session *ds;
+	int32_t i;
+
+	for (i = 0; i < NSS_MAX_DTLS_SESSIONS; i++) {
+		spin_lock_bh(&g_ctx.lock);
+		if (g_ctx.session[i] == NULL) {
+			spin_unlock_bh(&g_ctx.lock);
+			continue;
+		}
+
+		/*
+		 * Remove session from list of sessions
+		 */
+		ds = g_ctx.session[i];
+		g_ctx.session[i] = NULL;
+		spin_unlock_bh(&g_ctx.lock);
+
+		nss_dtlsmgr_assert(ds->magic == NSS_DTLSMGR_SESSION_MAGIC);
+
+		/*
+		 * Send DTLS session destroy command to FW
+		 */
+		memset(&dtlsmsg, 0, sizeof(struct nss_dtls_msg));
+		nss_dtls_msg_init(&dtlsmsg, (uint16_t)ds->nss_dtls_if,
+				  NSS_DTLS_MSG_SESSION_DESTROY, 0,
+				  NULL, NULL);
+
+		nss_status = nss_dtls_tx_msg_sync(ds->nss_ctx, &dtlsmsg);
+		if (nss_status != NSS_TX_SUCCESS)
+			nss_dtlsmgr_warn("%px: Failed to send DTLS session destroy for I/F %u\n", &g_ctx, ds->nss_dtls_if);
+
+		nss_dtlsmgr_session_ref_dec(ds);
+	}
+}
+
+/*
+ * nss_dtls_exit_module()
+ */
+void __exit nss_dtls_exit_module(void)
+{
+	nss_dtls_destroy_all_sessions();
+	nss_crypto_unregister_user(g_ctx.crypto_hdl);
+}
+
+module_init(nss_dtls_init_module);
+module_exit(nss_dtls_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS DTLS manager");
diff --git a/qca-nss-clients/dtls/v1.0/nss_connmgr_dtls.h b/qca-nss-clients/dtls/v1.0/nss_connmgr_dtls.h
new file mode 100644
index 0000000..b116c86
--- /dev/null
+++ b/qca-nss-clients/dtls/v1.0/nss_connmgr_dtls.h
@@ -0,0 +1,215 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_connnmgr_dtls.h
+ */
+
+#ifndef _NSS_CONNMGR_DTLS_H_
+#define _NSS_CONNMGR_DTLS_H_
+
+#include <nss_dtlsmgr.h>
+#include <nss_crypto_if.h>
+
+/*
+ * Debug macros
+ */
+#if (NSS_DTLSMGR_DEBUG_LEVEL < 1)
+#define nss_dtlsmgr_assert(fmt, args...)
+#else
+#define nss_dtlsmgr_assert(c) BUG_ON(!(c))
+#endif
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_dtlsmgr_warn(s, ...) pr_debug("%s[%d]:" s, __func__, \
+					  __LINE__, ##__VA_ARGS__)
+#define nss_dtlsmgr_info(s, ...) pr_debug("%s[%d]:" s, __func__, \
+					  __LINE__, ##__VA_ARGS__)
+#define nss_dtlsmgr_trace(s, ...) pr_debug("%s[%d]:" s, __func__, \
+					   __LINE__, ##__VA_ARGS__)
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_DTLSMGR_DEBUG_LEVEL < 2)
+#define nss_dtlsmgr_warn(s, ...)
+#else
+#define nss_dtlsmgr_warn(s, ...) pr_warn("%s[%d]:" s, __func__, \
+					 __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_DTLSMGR_DEBUG_LEVEL < 3)
+#define nss_dtlsmgr_info(s, ...)
+#else
+#define nss_dtlsmgr_info(s, ...) pr_notice("%s[%d]:" s, __func__, \
+					   __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_DTLSMGR_DEBUG_LEVEL < 4)
+#define nss_dtlsmgr_trace(s, ...)
+#else
+#define nss_dtlsmgr_trace(s, ...)  pr_info("%s[%d]:" s, __func__, \
+					   __LINE__, ##__VA_ARGS__)
+#endif
+#endif
+
+#define NSS_DTLSMGR_HDR_LEN 13			/* DTLS header length */
+#define NSS_DTLSMGR_CAPWAPHDR_LEN 4		/* CAPWAP-DTLS header length */
+#define NSS_DTLSMGR_SESSION_MAGIC 0x5d7eb219	/* DTLS session magic value */
+
+/*
+ * DTLS payload content type
+ */
+#define NSS_DTLSMGR_CTYPE_APP 23		/* Application data */
+
+/*
+ * DTLS metadata
+ */
+#define NSS_DTLSMGR_METADATA_LEN 4		/* DTLS metadata length */
+#define NSS_DTLSMGR_METADATA_CTYPE(m) (m >> 24)	/* DTLS metadata content type */
+#define NSS_DTLSMGR_METADATA_ERROR(m) ((m >> 16) & 0x00FF)
+						/* DTLS metadata error */
+/*
+ * DTLS metadata error types
+ */
+#define NSS_DTLSMGR_METADATA_ERROR_OK 0
+
+/**
+ * NSS DTLS crypto data
+ */
+struct nss_dtlsmgr_crypto_algo {
+	enum nss_crypto_cipher cipher_algo;
+	enum nss_crypto_auth auth_algo;
+	uint32_t iv_len;
+	uint32_t hash_len;
+};
+
+/**
+ * NSS DTLS session stats update
+ */
+struct nss_dtlsmgr_session_stats_update {
+	uint32_t tx_pkts;		/**< Tx packets */
+	uint32_t rx_pkts;		/**< Rx packets */
+	uint32_t rx_dropped;		/**< Rx drops */
+	uint32_t tx_auth_done;		/**< Tx authentication done */
+	uint32_t rx_auth_done;		/**< Rx successful authentication */
+	uint32_t tx_cipher_done;	/**< Tx cipher done */
+	uint32_t rx_cipher_done;	/**< Rx cipher done */
+	uint32_t tx_cbuf_alloc_fail;	/**< Tx crypto buffer allocation fail */
+	uint32_t rx_cbuf_alloc_fail;	/**< Rx crypto buffer allocation fail */
+	uint32_t tx_cenqueue_fail;	/**< Tx crypto enqueue fail */
+	uint32_t rx_cenqueue_fail;	/**< Rx crypto enqueue fail */
+	uint32_t tx_dropped_hroom;	/**< Tx drop due to
+					     insufficient headroom */
+	uint32_t tx_dropped_troom;	/**< Tx drop due to
+					     insufficient tailroom */
+	uint32_t tx_forward_enqueue_fail;
+					/**< Enqueue failed to forwarding
+					     node after encap */
+	uint32_t rx_forward_enqueue_fail;
+					/**< Enqueue failed to receiving
+					     node after decap */
+	uint32_t rx_invalid_version;	/**< Rx invalid DTLS version */
+	uint32_t rx_invalid_epoch;	/**< Rx invalid DTLS epoch */
+	uint32_t rx_malformed;		/**< Rx malformed DTLS record */
+	uint32_t rx_cipher_fail;	/**< Rx cipher fail */
+	uint32_t rx_auth_fail;		/**< Rx authentication fail */
+	uint32_t rx_capwap_classify_fail;
+					/**< Rx CAPWAP classification fail */
+	uint32_t rx_replay_fail;	/**< Rx anti-replay failures */
+	uint32_t rx_replay_duplicate;	/**< Rx anti-replay fail for
+					     duplicate record */
+	uint32_t rx_replay_out_of_window;
+					/**< Rx anti-replay fail for out
+					     of window record */
+	uint32_t outflow_queue_full;	/**< Tx drop due to encap queue full */
+	uint32_t decap_queue_full;	/**< Rx drop due to decap queue full */
+	uint32_t pbuf_alloc_fail;	/**< Buffer allocation fail */
+	uint32_t pbuf_copy_fail;	/**< Buffer copy fail */
+	uint16_t epoch;			/**< Current Epoch */
+	uint16_t tx_seq_high;		/**< Upper 16-bits of current
+					     sequence number */
+	uint32_t tx_seq_low;		/**< Lower 32-bits of current
+					     sequence number */
+};
+
+/**
+ * NSS DTLS session stats update callback
+ */
+typedef void (*nss_dtlsmgr_session_stats_update_cb_t)(uint32_t dtls_if, struct nss_dtlsmgr_session_stats_update *supdate);
+
+/**
+ *  * @brief IPv4/IPv6 address
+ *   */
+union nss_dtlsmgr_ip {
+        uint32_t ipv4;                  /**< IPv4 address */
+        uint32_t ipv6[4];               /**< IPv6 address */
+};
+
+/*
+ * DTLS Manager session
+ */
+struct nss_dtlsmgr_session {
+	uint32_t magic;			/* Magic value used to
+					   verify DTLS session */
+	atomic_t ref;			/* Reference counter */
+	uint32_t ver;			/* DTLS version */
+	uint32_t flags;			/* Session flags */
+	uint32_t crypto_idx_encap;	/* Current encap crypto session idx */
+	uint32_t crypto_idx_decap;	/* Current decap crypto session idx */
+	uint32_t cidx_encap_pending;	/* Pending encap crypto session idx */
+	uint32_t cidx_decap_pending;	/* Pending decap crypto session idx */
+	nss_dtlsmgr_session_stats_update_cb_t stats_update_cb;
+					/* Callback for Stats update */
+	uint32_t nss_dtls_if;		/* NSS DTLS session I/F */
+	struct nss_ctx_instance *nss_ctx;
+					/* NSS context */
+	struct net_device *netdev;	/* Netdevice */
+	uint16_t sport;			/* Source UDP/UDPLite port */
+	uint16_t dport;			/* Destination UDP/UDPLite port */
+	uint16_t window_size;		/* Anit-replay window size */
+	uint16_t epoch;			/* Current Epoch */
+	union nss_dtlsmgr_ip sip;	/* Source IPv4/IPv6 address */
+	union nss_dtlsmgr_ip dip;	/* Destination IPv4/IPv6 address */
+	uint32_t nss_app_if;		/* NSS I/F of application using
+					   this DTLS session */
+	uint8_t ip_ttl;			/* IP Time To Live */
+};
+
+/*
+ * DTLS Manager global context type
+ */
+struct nss_dtlsmgr_ctx {
+	nss_crypto_handle_t crypto_hdl;
+	spinlock_t lock;
+	struct nss_dtlsmgr_session *session[NSS_MAX_DTLS_SESSIONS];
+};
+
+/*
+ * DTLS Manager per session netdev private data
+ */
+struct nss_dtlsmgr_netdev_priv {
+	struct nss_dtlsmgr_session *s;
+};
+
+nss_dtlsmgr_status_t nss_dtlsmgr_netdev_create(struct nss_dtlsmgr_session *ds);
+nss_dtlsmgr_status_t nss_dtlsmgr_netdev_destroy(struct nss_dtlsmgr_session *ds);
+
+#endif
diff --git a/qca-nss-clients/dtls/v1.0/nss_connmgr_dtls_netdev.c b/qca-nss-clients/dtls/v1.0/nss_connmgr_dtls_netdev.c
new file mode 100644
index 0000000..06cdbe3
--- /dev/null
+++ b/qca-nss-clients/dtls/v1.0/nss_connmgr_dtls_netdev.c
@@ -0,0 +1,222 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_connmgr_dtls_netdev.c
+ *	NSS DTLS Manager netdev module
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <net/ipv6.h>
+#include <linux/if_arp.h>
+#include <linux/etherdevice.h>
+#include <linux/udp.h>
+#include <linux/ipv6.h>
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+
+#include "nss_connmgr_dtls.h"
+
+/*
+ * Maximum tailroom required by crypto
+ */
+#define NSS_DTLSMGR_TROOM (128 + (2 * NSS_CRYPTO_MAX_HASHLEN_SHA256))
+
+/*
+ * Maximum headroom for encapsulating headers
+ */
+#define NSS_DTLSMGR_MAX_HDR_LEN ((NSS_DTLSMGR_HDR_LEN + 3)	\
+				 + NSS_DTLSMGR_CAPWAPHDR_LEN	\
+				 + (2 * NSS_CRYPTO_MAX_IVLEN_AES)	\
+				 + sizeof(struct ipv6hdr)	\
+				 + sizeof(struct udphdr))
+
+/*
+ * nss_dtlsmgr_session_xmit()
+ */
+static netdev_tx_t nss_dtlsmgr_session_xmit(struct sk_buff *skb,
+					    struct net_device *dev)
+{
+	struct nss_dtlsmgr_netdev_priv *priv;
+	struct nss_dtlsmgr_session *s;
+	int32_t  nhead, ntail;
+
+	priv = netdev_priv(dev);
+	s = priv->s;
+
+	switch (skb->protocol) {
+	case htons(ETH_P_IP):
+		if (s->flags & NSS_DTLSMGR_HDR_IPV6) {
+			nss_dtlsmgr_info("%px: NSS DTLS I/F %d: skb(%px) invalid L3 protocol 0x%x\n", dev, s->nss_dtls_if, skb, ETH_P_IP);
+			return NETDEV_TX_BUSY;
+		}
+		break;
+
+	case htons(ETH_P_IPV6):
+		if (!(s->flags & NSS_DTLSMGR_HDR_IPV6)) {
+			nss_dtlsmgr_info("%px: NSS DTLS I/F %d: skb(%px) invalid L3 protocol 0x%x\n", dev, s->nss_dtls_if, skb, ETH_P_IPV6);
+			return NETDEV_TX_BUSY;
+		}
+		break;
+
+	default:
+		nss_dtlsmgr_info("%px: NSS DTLS I/F %d: skb(%px) unsupported IP protocol 0x%x\n", dev, s->nss_dtls_if, skb, ntohs(skb->protocol));
+		return NETDEV_TX_BUSY;
+	}
+
+	nhead = dev->needed_headroom;
+	ntail = dev->needed_tailroom;
+
+	if (skb_is_nonlinear(skb)) {
+		nss_dtlsmgr_info("%px: NSS DTLS does not support non-linear skb %px\n", dev, skb);
+		return NETDEV_TX_BUSY;
+	}
+
+	if (unlikely(skb_shared(skb))) {
+		nss_dtlsmgr_info("%px: Shared skb:%px is not supported\n",
+				 dev, skb);
+		return NETDEV_TX_BUSY;
+	}
+
+	if (skb_cloned(skb) || (skb_headroom(skb) < nhead)
+	    || (skb_tailroom(skb) < ntail)) {
+		if (pskb_expand_head(skb, nhead, ntail, GFP_KERNEL)) {
+			nss_dtlsmgr_info("%px: skb:%px unable to expand buffer\n",
+					 dev, skb);
+			return NETDEV_TX_BUSY;
+		}
+	}
+
+	if (skb->data != skb_network_header(skb)) {
+		skb_pull(skb, skb_network_offset(skb));
+	}
+
+	if (nss_dtls_tx_buf(skb, s->nss_dtls_if, s->nss_ctx) != NSS_TX_SUCCESS) {
+		return NETDEV_TX_BUSY;
+	}
+
+	return NETDEV_TX_OK;
+}
+
+/*
+ * nss_dtlsmgr_session_stop()
+ */
+static int nss_dtlsmgr_session_stop(struct net_device *dev)
+{
+	netif_stop_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_dtlsmgr_session_open()
+ */
+static int nss_dtlsmgr_session_open(struct net_device *dev)
+{
+	netif_start_queue(dev);
+	return 0;
+}
+
+/*
+ * DTLS netdev ops
+ */
+static const struct net_device_ops nss_dtlsmgr_session_ops = {
+	.ndo_start_xmit = nss_dtlsmgr_session_xmit,
+	.ndo_open = nss_dtlsmgr_session_open,
+	.ndo_stop = nss_dtlsmgr_session_stop,
+	.ndo_set_mac_address = eth_mac_addr,
+};
+
+/*
+ * nss_dtlsmgr_dev_setup()
+ */
+static void nss_dtlsmgr_dev_setup(struct net_device *dev)
+{
+	dev->addr_len = ETH_ALEN;
+	dev->mtu = ETH_DATA_LEN;
+	dev->hard_header_len = NSS_DTLSMGR_MAX_HDR_LEN;
+	dev->needed_headroom = 0;
+	dev->needed_tailroom = NSS_DTLSMGR_TROOM;
+
+	dev->type = ARPHRD_ETHER;
+	dev->ethtool_ops = NULL;
+	dev->header_ops = NULL;
+	dev->netdev_ops = &nss_dtlsmgr_session_ops;
+	dev->destructor = NULL;
+
+	memcpy(dev->dev_addr, "\xaa\xbb\xcc\xdd\xee\xff", dev->addr_len);
+	memset(dev->broadcast, 0xff, dev->addr_len);
+	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
+}
+
+/*
+ * nss_dtlsmgr_netdev_create()
+ */
+nss_dtlsmgr_status_t nss_dtlsmgr_netdev_create(struct nss_dtlsmgr_session *ds)
+{
+	struct net_device *dev;
+	struct nss_dtlsmgr_netdev_priv *priv;
+	int32_t err = 0;
+
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 16, 0))
+	dev = alloc_netdev(sizeof(struct nss_dtlsmgr_netdev_priv),
+			   "qca-nss-dtls%d", nss_dtlsmgr_dev_setup);
+#else
+	dev = alloc_netdev(sizeof(struct nss_dtlsmgr_netdev_priv),
+			   "qca-nss-dtls%d", NET_NAME_UNKNOWN,
+			   nss_dtlsmgr_dev_setup);
+#endif
+
+	if (!dev) {
+		nss_dtlsmgr_info("DTLS netdev alloc failed\n");
+		return NSS_DTLSMGR_FAIL;
+	}
+
+	priv = netdev_priv(dev);
+	priv->s = ds;
+
+	err = rtnl_is_locked() ? register_netdevice(dev) : register_netdev(dev);
+	if (err < 0) {
+		nss_dtlsmgr_info("DTLS netdev register failed\n");
+		free_netdev(dev);
+		return NSS_DTLSMGR_FAIL;
+	}
+
+	ds->netdev = dev;
+	return NSS_DTLSMGR_OK;
+}
+
+/*
+ * nss_dtlsmgr_netdev_destroy()
+ */
+nss_dtlsmgr_status_t nss_dtlsmgr_netdev_destroy(struct nss_dtlsmgr_session *ds)
+{
+	if (!ds || !ds->netdev) {
+		return NSS_DTLSMGR_FAIL;
+	}
+
+	rtnl_is_locked() ? unregister_netdevice(ds->netdev)
+			 : unregister_netdev(ds->netdev);
+
+	free_netdev(ds->netdev);
+	ds->netdev = NULL;
+	return NSS_DTLSMGR_OK;
+}
diff --git a/qca-nss-clients/dtls/v2.0/Makefile b/qca-nss-clients/dtls/v2.0/Makefile
new file mode 100644
index 0000000..adf87de
--- /dev/null
+++ b/qca-nss-clients/dtls/v2.0/Makefile
@@ -0,0 +1,12 @@
+# Makefile for DTLS manager
+
+ccflags-y += $(NSS_CCFLAGS) -I$(obj)/../../exports
+ccflags-y += -DNSS_DTLSMGR_DEBUG_LEVEL=0
+ccflags-y += -DNSS_DTLSMGR_BUILD_ID=\"'Build_ID - $(shell date +'%m/%d/%y, %H:%M:%S') SoC=$(SoC)'\"
+ccflags-y += -Wall -Werror
+
+obj-m += qca-nss-dtlsmgr.o
+qca-nss-dtlsmgr-objs += nss_dtlsmgr.o
+qca-nss-dtlsmgr-objs += nss_dtlsmgr_ctx.o
+qca-nss-dtlsmgr-objs += nss_dtlsmgr_ctx_dev.o
+qca-nss-dtlsmgr-objs += nss_dtlsmgr_ctx_stats.o
diff --git a/qca-nss-clients/dtls/v2.0/nss_dtlsmgr.c b/qca-nss-clients/dtls/v2.0/nss_dtlsmgr.c
new file mode 100644
index 0000000..3285fc1
--- /dev/null
+++ b/qca-nss-clients/dtls/v2.0/nss_dtlsmgr.c
@@ -0,0 +1,177 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_dtlsmgr.c
+ *	NSS DTLS Manager
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/crypto.h>
+#include <linux/debugfs.h>
+#include <linux/rtnetlink.h>
+#include <net/ipv6.h>
+#include <linux/if_arp.h>
+#include <linux/etherdevice.h>
+#include <linux/atomic.h>
+
+#include <crypto/algapi.h>
+#include <crypto/aead.h>
+#include <crypto/aes.h>
+#include <crypto/authenc.h>
+#include <crypto/des.h>
+#include <crypto/sha.h>
+#include <crypto/skcipher.h>
+#include <crypto/hash.h>
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+
+#include <nss_cryptoapi.h>
+#include <nss_dtls_cmn.h>
+#include <nss_dtlsmgr.h>
+
+#include "nss_dtlsmgr_private.h"
+
+/*
+ * Global DTLS context
+ */
+struct nss_dtlsmgr g_dtls = {0};
+
+/*
+ * nss_dtlsmgr_node_configure_done()
+ *	Check and set the configured flag if the DTLS firmware package is successfully configured.
+ */
+static void nss_dtlsmgr_node_configure_done(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_dtlsmgr *drv = app_data;
+
+	nss_dtlsmgr_info("%px: configure node(%u) response(%d) error(%d)\n", drv,
+			 ncm->interface, ncm->response, ncm->error);
+	atomic_cmpxchg(&drv->is_configured, false, (ncm->response == NSS_CMN_RESPONSE_ACK) ||
+			(ncm->error == NSS_DTLS_CMN_ERROR_ALREADY_CONFIGURED));
+}
+
+/*
+ * nss_dtlsmgr_node_configure()
+ *	Send a configure message to the DTLS firmware package.
+ */
+static void nss_dtlsmgr_node_configure(struct nss_dtlsmgr *drv, uint32_t if_num)
+{
+	struct nss_dtls_cmn_msg ndcm = {0};
+	nss_tx_status_t nss_status;
+
+	/*
+	 * Send DTLS configure message to NSS
+	 */
+	nss_dtls_cmn_msg_init(&ndcm, if_num, NSS_DTLS_CMN_MSG_TYPE_CONFIGURE_NODE, 0,
+			      nss_dtlsmgr_node_configure_done, drv);
+
+	nss_status = nss_dtls_cmn_tx_msg(drv->nss_ctx, &ndcm);
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_dtlsmgr_warn("%px: unable to send node configure (%u)\n", drv, if_num);
+		return;
+	}
+}
+
+/*
+ * nss_dtlsmgr_rx_event()
+ *	Handle the response notification from the firmware.
+ */
+static void nss_dtlsmgr_rx_event(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_dtlsmgr *drv = app_data;
+
+	nss_dtlsmgr_trace("%px: received Node stats sync:%u\n", drv, ncm->interface);
+
+	/*
+	 * The firmware DTLS should not configure its DMA rings till it
+	 * knows that the HW is fully configured by host crypto driver.
+	 * Since, the firmware boots independent of the host. There is no
+	 * guarantee that the DMA will be ready for configuration when the
+	 * firmware is configuring itself. Thus our approach is to notify
+	 * the firmware to setup its DMA after the host is ready. Here we
+	 * use a simple approach of module load order where the DTLS Manager
+	 * loads after the crypto driver. The expectation is that the crypto
+	 * driver would configure the HW correctly and other modules dependent
+	 * upon it would get the chance to load. Once, the configuration is
+	 * done for DTLS when would like to avoid further configuration of the
+	 * DMA.
+	 *
+	 * TODO: Multiple items
+	 * - Use a nss_cryptoapi_xxx to detect whether the crypto is ready.
+	 * - Add a mechanism to switch to pointer for first time configuration
+	 * - Add support for node stats. Eventhough the node stats is already
+	 * captured in NSS driver.
+	 */
+	if (!atomic_read(&drv->is_configured)) {
+		nss_dtlsmgr_node_configure(drv, ncm->interface);
+		return;
+	}
+}
+
+/*
+ * nss_dtlsmgr_init_module()
+ *	Initialize the DTLS manager module.
+ */
+int __init nss_dtlsmgr_init_module(void)
+{
+	struct nss_dtlsmgr *drv = &g_dtls;
+
+	atomic_set(&drv->is_configured, false);
+
+	nss_dtlsmgr_trace("registering for base interface(%u)", NSS_DTLS_INTERFACE);
+	drv->nss_ctx = nss_dtls_cmn_notify_register(NSS_DTLS_INTERFACE, nss_dtlsmgr_rx_event, drv);
+	if (!drv->nss_ctx) {
+		nss_dtlsmgr_warn("%px: DTLS NSS context instance is NULL", drv);
+		return -ENODEV;
+	}
+
+	drv->root_dir = debugfs_create_dir("qca-nss-dtlsmgr", NULL);
+	if (!drv->root_dir)
+		nss_dtlsmgr_warn("Failed to create debugfs directory");
+
+	pr_info("qca-nss-dtlsmgr module loaded (%s)\n", NSS_DTLSMGR_BUILD_ID);
+	return 0;
+}
+
+/*
+ * nss_dtlsmgr_exit_module()
+ *	Remove the DTLS manager module.
+ */
+void __exit nss_dtlsmgr_exit_module(void)
+{
+	struct nss_dtlsmgr *drv = &g_dtls;
+
+	nss_dtls_cmn_notify_unregister(NSS_DTLS_INTERFACE);
+
+	debugfs_remove_recursive(drv->root_dir);
+
+	atomic_set(&drv->is_configured, false);
+
+	nss_dtlsmgr_info("dtls manger is unloaded");
+}
+
+module_init(nss_dtlsmgr_init_module);
+module_exit(nss_dtlsmgr_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS DTLS manager");
diff --git a/qca-nss-clients/dtls/v2.0/nss_dtlsmgr_ctx.c b/qca-nss-clients/dtls/v2.0/nss_dtlsmgr_ctx.c
new file mode 100644
index 0000000..f8432e0
--- /dev/null
+++ b/qca-nss-clients/dtls/v2.0/nss_dtlsmgr_ctx.c
@@ -0,0 +1,879 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_dtlsmgr_ctx.c
+ *	NSS DTLS Manager Context
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/crypto.h>
+#include <linux/debugfs.h>
+#include <linux/rtnetlink.h>
+#include <net/ipv6.h>
+#include <net/vxlan.h>
+#include <linux/if_arp.h>
+#include <linux/etherdevice.h>
+#include <linux/atomic.h>
+#include <asm/cmpxchg.h>
+
+#include <crypto/algapi.h>
+#include <crypto/aead.h>
+#include <crypto/aes.h>
+#include <crypto/authenc.h>
+#include <crypto/des.h>
+#include <crypto/sha.h>
+#include <crypto/skcipher.h>
+#include <crypto/hash.h>
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+
+#include <nss_cryptoapi.h>
+#include <nss_dtls_cmn.h>
+#include <nss_dtlsmgr.h>
+
+#include "nss_dtlsmgr_private.h"
+
+#define NSS_DTLSMGR_KEY_PARAM_SIZE RTA_SPACE(sizeof(struct crypto_authenc_key_param))
+
+extern struct nss_dtlsmgr g_dtls;
+
+static struct nss_dtlsmgr_algo_info dtlsmgr_algo_info[NSS_DTLSMGR_ALGO_MAX] = {
+	{"echainiv(authenc(hmac(sha1),cbc(aes)))", NSS_DTLSMGR_KEY_PARAM_SIZE},
+	{"echainiv(authenc(hmac(sha256),cbc(aes)))", NSS_DTLSMGR_KEY_PARAM_SIZE},
+	{"echainiv(authenc(hmac(sha1),cbc(des3_ede)))", NSS_DTLSMGR_KEY_PARAM_SIZE},
+	{"echainiv(authenc(hmac(sha256),cbc(des3_ede)))", NSS_DTLSMGR_KEY_PARAM_SIZE},
+	{"rfc4106(gcm(aes))", 0}
+};
+
+/*
+ * nss_dtlsmgr_ctx_alloc_crypto()
+ *	Allocate a crypto session through Linux CryptoAPI framework.
+ */
+static int nss_dtlsmgr_ctx_alloc_crypto(struct nss_dtlsmgr_ctx *ctx, struct nss_dtlsmgr_dtls_data *dtls,
+					struct nss_dtlsmgr_crypto *crypto)
+{
+	struct crypto_authenc_key_param *key_param;
+	struct nss_dtlsmgr_algo_info *info;
+	struct rtattr *rta;
+	char *keys, *p;
+	uint16_t keylen;
+
+	if (crypto->algo >= ARRAY_SIZE(dtlsmgr_algo_info)) {
+		nss_dtlsmgr_warn("%px: invalid crypto algorithm", ctx);
+		return -EINVAL;
+	}
+
+	info = &dtlsmgr_algo_info[crypto->algo];
+	dtls->aead = crypto_alloc_aead(info->name, 0, 0);
+	if (IS_ERR(dtls->aead)) {
+		nss_dtlsmgr_warn("%px: failed to allocate crypto aead context", ctx);
+		return -ENOMEM;
+	}
+
+	nss_dtlsmgr_trace("cipher_keylen:%d auth_keylen:%d nonce_len:%d\n",
+			  crypto->cipher_key.len, crypto->auth_key.len, crypto->nonce.len);
+
+	/*
+	 * Construct keys
+	 */
+	keylen = info->rta_key_size;
+	keylen += crypto->cipher_key.len;
+	keylen += crypto->auth_key.len;
+	keylen += crypto->nonce.len;
+
+	keys = vzalloc(keylen);
+	if (!keys) {
+		nss_dtlsmgr_warn("%px: failed to allocate key memory", ctx);
+		crypto_free_aead(dtls->aead);
+		return -ENOMEM;
+	}
+
+	if (crypto->algo == NSS_DTLSMGR_ALGO_AES_GCM) {
+		memcpy(keys, crypto->cipher_key.data, crypto->cipher_key.len);
+		/* Copy nonce after the key */
+		memcpy(keys + crypto->cipher_key.len, crypto->nonce.data, crypto->nonce.len);
+		goto setkey;
+	}
+
+	p = keys;
+	rta = (void *)p;
+	rta->rta_type = CRYPTO_AUTHENC_KEYA_PARAM;
+	rta->rta_len = RTA_LENGTH(sizeof(*key_param));
+	key_param = RTA_DATA(rta);
+	p += RTA_SPACE(sizeof(*key_param));
+
+	/*
+	 * Copy authentication key
+	 */
+	memcpy(p, crypto->auth_key.data, crypto->auth_key.len);
+	p += crypto->auth_key.len;
+
+	/*
+	 * Copy cipher Key
+	 */
+	key_param->enckeylen = cpu_to_be32(crypto->cipher_key.len);
+	memcpy(p, crypto->cipher_key.data, crypto->cipher_key.len);
+
+setkey:
+
+	if (crypto_aead_setkey(dtls->aead, keys, keylen)) {
+		nss_dtlsmgr_warn("%px: failed to configure keys", ctx);
+		vfree(keys);
+		crypto_free_aead(dtls->aead);
+		return -ENOSPC;
+	}
+
+	nss_cryptoapi_aead_ctx2session(dtls->aead, &dtls->crypto_idx);
+	dtls->blk_len = (uint8_t)crypto_aead_blocksize(dtls->aead);
+	dtls->hash_len = (uint8_t)crypto_aead_authsize(dtls->aead);
+	dtls->iv_len = (uint8_t)crypto_aead_ivsize(dtls->aead);
+
+	vfree(keys);
+	return 0;
+}
+
+/*
+ * nss_dtlsmgr_ctx_alloc_dtls()
+ *	Allocate a DTLS session.
+ */
+static struct nss_dtlsmgr_dtls_data *nss_dtlsmgr_ctx_alloc_dtls(struct nss_dtlsmgr_ctx *ctx,
+								struct nss_dtlsmgr_ctx_data *data,
+								struct nss_dtlsmgr_crypto *crypto)
+{
+	struct nss_dtlsmgr_dtls_data *dtls;
+	int error;
+
+	nss_dtlsmgr_trace("%px: allocating context data(%u)", ctx, data->di_type);
+
+	dtls = vzalloc(sizeof(*dtls));
+	if (!dtls) {
+		nss_dtlsmgr_warn("%px: failed to allocate dtls data(%u) ", ctx, data->di_type);
+		return NULL;
+	}
+
+	INIT_LIST_HEAD(&dtls->list);
+
+	error = nss_dtlsmgr_ctx_alloc_crypto(ctx, dtls, crypto);
+	if (error < 0) {
+		nss_dtlsmgr_warn("%px: unable to allocate crypto(%u) - error(%d)", ctx, data->di_type, error);
+		vfree(dtls);
+		return NULL;
+	}
+
+	nss_dtlsmgr_trace("%px: crypto_aead allocated", ctx);
+	return dtls;
+}
+
+/*
+ * nss_dtlsmgr_ctx_free_dtls()
+ *	Free the DTLS context.
+ */
+static void nss_dtlsmgr_ctx_free_dtls(struct nss_dtlsmgr_dtls_data *dtls)
+{
+	crypto_free_aead(dtls->aead);
+	vfree(dtls);
+}
+
+/*
+ * nss_dtlsmgr_ctx_configure_hdr()
+ *	Configure the DTLS header related information.
+ */
+static bool nss_dtlsmgr_ctx_configure_hdr(struct nss_dtlsmgr_ctx_data *data)
+{
+	const uint32_t type = NSS_DTLS_CMN_MSG_TYPE_CONFIGURE_HDR;
+	enum nss_dtls_cmn_error resp = NSS_DTLS_CMN_ERROR_NONE;
+	struct nss_dtls_cmn_ctx_config_hdr *cfg;
+	struct nss_dtls_cmn_msg ndcm = { {0} };
+	nss_tx_status_t status;
+	uint32_t mask = 0;
+
+	BUG_ON(in_atomic());
+
+	mask |= NSS_DTLS_CMN_CTX_HDR_IPV6;
+	mask |= NSS_DTLS_CMN_CTX_HDR_UDPLITE;
+	mask |= NSS_DTLS_CMN_CTX_HDR_CAPWAP;
+	mask |= NSS_DTLS_CMN_CTX_CIPHER_MODE_GCM;
+	mask |= NSS_DTLS_CMN_CTX_ENCAP_UDPLITE_CSUM;
+	mask |= NSS_DTLS_CMN_CTX_ENCAP_METADATA;
+	mask |= NSS_DTLS_CMN_CTX_DECAP_ACCEPT_ALL;
+
+	cfg = &ndcm.msg.hdr_cfg;
+	cfg->flags = data->flags & mask;
+	cfg->dest_ifnum = data->dest_ifnum;
+	cfg->src_ifnum = data->src_ifnum;
+
+	memcpy(cfg->sip, data->flow.sip, sizeof(cfg->sip));
+	memcpy(cfg->dip, data->flow.dip, sizeof(cfg->dip));
+
+	cfg->sport = data->flow.sport;
+	cfg->dport = data->flow.dport;
+	cfg->hop_limit_ttl = data->flow.hop_limit_ttl;
+	cfg->dscp = data->flow.dscp;
+	cfg->dscp_copy = data->flow.dscp_copy;
+	cfg->df = data->flow.df;
+
+	nss_dtlsmgr_trace("flags:0x%x dest_ifnum:0x%x src_ifnum:0x%x sport:0x%x dport:0x%x sip:0x%x dip:0x%x",
+			  cfg->flags, cfg->dest_ifnum, cfg->src_ifnum, cfg->sport, cfg->dport,
+			  cfg->sip[0], cfg->dip[0]);
+
+	status = nss_dtls_cmn_tx_msg_sync(data->nss_ctx, data->ifnum, type, sizeof(*cfg), &ndcm, &resp);
+	if (status != NSS_TX_SUCCESS) {
+		nss_dtlsmgr_warn("%px: msg_sync failed, if_num(%u), status(%d), type(%d), resp(%d)",
+				 data, data->ifnum, type, status, resp);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_dtlsmgr_ctx_configure_dtls()
+ *	Configure the DTLS version, crypto related data, window size and epoch.
+ */
+static bool nss_dtlsmgr_ctx_configure_dtls(struct nss_dtlsmgr_ctx_data *data, struct nss_dtlsmgr_dtls_data *dtls)
+{
+	const uint32_t type = NSS_DTLS_CMN_MSG_TYPE_CONFIGURE_DTLS;
+	enum nss_dtls_cmn_error resp = NSS_DTLS_CMN_ERROR_NONE;
+	struct nss_dtls_cmn_ctx_config_dtls *cfg;
+	struct nss_dtls_cmn_msg ndcm = {0};
+	nss_tx_status_t status;
+
+	BUG_ON(in_atomic());
+
+	cfg = &ndcm.msg.dtls_cfg;
+	cfg->ver = dtls->ver;
+	cfg->crypto_idx = dtls->crypto_idx;
+	cfg->epoch = dtls->epoch;
+	cfg->window_size = dtls->window_size;
+	cfg->iv_len = dtls->iv_len;
+	cfg->hash_len = dtls->hash_len;
+	cfg->blk_len = dtls->blk_len;
+
+	status = nss_dtls_cmn_tx_msg_sync(data->nss_ctx, data->ifnum, type, sizeof(*cfg), &ndcm, &resp);
+	if (status != NSS_TX_SUCCESS) {
+		nss_dtlsmgr_warn("%px: msg_sync failed, if_num(%u), status(%d), type(%d), resp(%d)",
+				data, data->ifnum, type, status, resp);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_dtlsmgr_ctx_deconfigure()
+ *	Deconfigure the DTLS context and free all the related data.
+ */
+static bool nss_dtlsmgr_ctx_deconfigure(struct nss_dtlsmgr_ctx *ctx, struct nss_dtlsmgr_ctx_data *data)
+{
+	const uint32_t type = NSS_DTLS_CMN_MSG_TYPE_DECONFIGURE;
+	enum nss_dtls_cmn_error resp = NSS_DTLS_CMN_ERROR_NONE;
+	struct nss_dtls_cmn_msg ndcm = {0};
+	struct nss_dtlsmgr_dtls_data *cur;
+	nss_tx_status_t status;
+
+	status = nss_dtls_cmn_tx_msg_sync(data->nss_ctx, data->ifnum, type, 0, &ndcm, &resp);
+	if (status != NSS_TX_SUCCESS) {
+		nss_dtlsmgr_warn("%px: msg_sync failed, if_num(%u), status(%d), type(%d), resp(%d)",
+				ctx, data->ifnum, type, status, resp);
+		return false;
+	}
+
+	nss_dtls_cmn_unregister_if(data->ifnum);
+
+	for (;;) {
+		write_lock(&ctx->lock);
+		cur = list_first_entry_or_null(&data->dtls_active, struct nss_dtlsmgr_dtls_data, list);
+		if (!cur) {
+			write_unlock(&ctx->lock);
+			break;
+		}
+
+		list_del(&cur->list);
+		write_unlock(&ctx->lock);
+		nss_dtlsmgr_ctx_free_dtls(cur);
+	}
+
+	status = nss_dynamic_interface_dealloc_node(data->ifnum, data->di_type);
+	if (status != NSS_TX_SUCCESS) {
+		nss_dtlsmgr_warn("%px: fail to deallocate dynamic(%d) interface(%u)", ctx, data->di_type, data->ifnum);
+		return false;
+	}
+
+	data->ifnum = -1;
+	return true;
+}
+
+/*
+ * nss_dtlsmgr_ctx_create_encap()
+ *	Create DTLS encapsulation dynamic interface and configure the DTLS context.
+ */
+static int nss_dtlsmgr_ctx_create_encap(struct nss_dtlsmgr_ctx *ctx, uint32_t ifnum,
+					uint32_t src_ifnum, struct nss_dtlsmgr_config *ndc)
+{
+	struct nss_dtlsmgr_encap_config *cfg = &ndc->encap;
+	struct nss_dtlsmgr_ctx_data *data = &ctx->encap;
+	struct nss_dtlsmgr_flow_data *flow = &data->flow;
+	struct nss_dtlsmgr_dtls_data *dtls;
+
+	dtls = nss_dtlsmgr_ctx_alloc_dtls(ctx, &ctx->encap, &cfg->crypto);
+	if (!dtls) {
+		nss_dtlsmgr_warn("%px: unable to allocate encap context data", ctx);
+		return -ENOMEM;
+	}
+
+	INIT_LIST_HEAD(&data->dtls_active);
+
+	data->di_type = NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_INNER;
+	data->ifnum = ifnum;
+	data->src_ifnum = src_ifnum;
+	data->flags = ndc->flags & (NSS_DTLSMGR_HDR_MASK | NSS_DTLSMGR_CRYPTO_MASK | NSS_DTLSMGR_ENCAP_MASK);
+	data->tailroom = dtls->blk_len + dtls->hash_len;
+	data->headroom = dtls->iv_len;
+
+	memcpy(&flow->sip, cfg->sip, sizeof(flow->sip));
+	memcpy(&flow->dip, cfg->dip, sizeof(flow->dip));
+
+	flow->sport = cfg->sport;
+	flow->dport = cfg->dport;
+	flow->dscp = cfg->dscp;
+	flow->dscp_copy = cfg->dscp_copy;
+	flow->df = cfg->df;
+	flow->hop_limit_ttl = cfg->ip_ttl;
+
+	dtls->epoch = cfg->epoch;
+	dtls->ver = cfg->ver;
+
+	data->headroom += NSS_DTLSMGR_DTLS_HDR_SZ;
+
+	/*
+	 * We need to provide the firmware the source and
+	 * destination interface number. This allows it
+	 * to work with dynamically created interfaces
+	 *
+	 */
+	switch (data->flags & (NSS_DTLSMGR_HDR_IPV6 | NSS_DTLSMGR_HDR_CAPWAP)) {
+	case NSS_DTLSMGR_HDR_IPV6 | NSS_DTLSMGR_HDR_CAPWAP:
+		data->dest_ifnum = NSS_IPV6_RX_INTERFACE;
+		data->headroom += sizeof(struct ipv6hdr);
+		data->headroom += NSS_DTLSMGR_CAPWAP_DTLS_HDR_SZ;
+		data->headroom += NSS_DTLSMGR_SGT_HDR_SZ;
+		break;
+	case NSS_DTLSMGR_HDR_IPV6:
+		data->dest_ifnum = NSS_IPV6_RX_INTERFACE;
+		data->headroom += sizeof(struct ipv6hdr);
+		break;
+	case NSS_DTLSMGR_HDR_CAPWAP:
+		data->dest_ifnum = NSS_IPV4_RX_INTERFACE;
+		data->headroom += sizeof(struct iphdr);
+		data->headroom += NSS_DTLSMGR_CAPWAP_DTLS_HDR_SZ;
+		data->headroom += NSS_DTLSMGR_SGT_HDR_SZ;
+		break;
+	default:
+		data->dest_ifnum = NSS_IPV4_RX_INTERFACE;
+		data->headroom += sizeof(struct iphdr);
+		break;
+	}
+
+	/*
+	 * Header size is same for UDP and UDPLite
+	 */
+	data->headroom += sizeof(struct ethhdr) + sizeof(struct vlan_hdr) + sizeof(struct udphdr);
+
+	nss_dtlsmgr_trace("%px: encap ifnum(%u), src(%u), dest(0x%x)", ctx, data->ifnum,
+			  data->src_ifnum, data->dest_ifnum);
+
+	/*
+	 * Register NSS DTLS Encap I/F
+	 */
+	data->nss_ctx = nss_dtls_cmn_register_if(data->ifnum,
+						nss_dtlsmgr_ctx_dev_rx_inner,
+						nss_dtlsmgr_ctx_dev_event_inner,
+						ctx->dev,
+						0,
+						data->di_type,
+						(void *)data);
+	if (!data->nss_ctx) {
+		nss_dtlsmgr_warn("%px: NSS register interface(%u) failed", ctx, data->ifnum);
+		nss_dtlsmgr_ctx_free_dtls(dtls);
+		return -ENODEV;
+	}
+
+	if (!nss_dtlsmgr_ctx_configure_hdr(data)) {
+		nss_dtlsmgr_warn("%px: unable to configure(%d) hdr", ctx, data->di_type);
+		goto fail;
+	}
+
+	if (!nss_dtlsmgr_ctx_configure_dtls(data, dtls)) {
+		nss_dtlsmgr_warn("%px: unable to configure(%d) dtls", ctx, data->di_type);
+		goto fail;
+	}
+
+	write_lock(&ctx->lock);
+	list_add(&dtls->list, &data->dtls_active);
+	write_unlock(&ctx->lock);
+
+	return 0;
+fail:
+	nss_dtls_cmn_unregister_if(data->ifnum);
+	nss_dtlsmgr_ctx_free_dtls(dtls);
+	return -EBUSY;
+}
+
+/*
+ * nss_dtlsmgr_ctx_create_decap()
+ *	Create DTLS decapsulation dynamic interface and configure the DTLS context.
+ */
+static int nss_dtlsmgr_ctx_create_decap(struct nss_dtlsmgr_ctx *ctx, uint32_t ifnum, uint32_t src_ifnum,
+					struct nss_dtlsmgr_config *cfg)
+{
+	struct nss_dtlsmgr_ctx_data *data = &ctx->decap;
+	struct nss_dtlsmgr_dtls_data *dtls;
+
+	dtls = nss_dtlsmgr_ctx_alloc_dtls(ctx, &ctx->decap, &cfg->decap.crypto);
+	if (!dtls) {
+		nss_dtlsmgr_warn("%px: unable to allocate decap context data", ctx);
+		return -ENOMEM;
+	}
+
+	INIT_LIST_HEAD(&data->dtls_active);
+
+	data->di_type = NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_OUTER;
+	data->ifnum = ifnum;
+
+	/*
+	 * We need to provide the firmware the source and
+	 * destination interface number. This allows it
+	 * to work with dynamically created interfaces
+	 *
+	 */
+	data->src_ifnum = src_ifnum;
+	data->dest_ifnum = cfg->decap.nexthop_ifnum;
+	data->tailroom = data->headroom = 0;
+	data->flags = cfg->flags & (NSS_DTLSMGR_HDR_MASK | NSS_DTLSMGR_CRYPTO_MASK | NSS_DTLSMGR_DECAP_MASK);
+
+	nss_dtlsmgr_trace("%px: decap ifnum(%u), src(%u), dest(%u)", ctx, data->ifnum,
+			  data->src_ifnum, data->dest_ifnum);
+
+	dtls->window_size = cfg->decap.window_size;
+	dtls->ver = cfg->encap.ver;
+
+	/*
+	 * Register NSS DTLS Decap I/F
+	 */
+	data->nss_ctx = nss_dtls_cmn_register_if(data->ifnum,
+						nss_dtlsmgr_ctx_dev_rx_outer,
+						nss_dtlsmgr_ctx_dev_event_outer,
+						ctx->dev,
+						0,
+						data->di_type,
+						(void *)data);
+	if (!data->nss_ctx) {
+		nss_dtlsmgr_warn("%px: NSS register interface(%u) failed", ctx, data->ifnum);
+		nss_dtlsmgr_ctx_free_dtls(dtls);
+		return -ENODEV;
+	}
+
+	if (!nss_dtlsmgr_ctx_configure_hdr(data)) {
+		nss_dtlsmgr_warn("%px: unable to configure(%d) hdr", ctx, data->di_type);
+		goto fail;
+	}
+
+	if (!nss_dtlsmgr_ctx_configure_dtls(data, dtls)) {
+		nss_dtlsmgr_warn("%px: unable to configure(%d) hdr", ctx, data->di_type);
+		goto fail;
+	}
+
+	write_lock(&ctx->lock);
+	list_add(&dtls->list, &data->dtls_active);
+	write_unlock(&ctx->lock);
+
+	return 0;
+fail:
+	nss_dtls_cmn_unregister_if(data->ifnum);
+	nss_dtlsmgr_ctx_free_dtls(dtls);
+	return -EBUSY;
+}
+
+/*
+ * nss_dtlsmgr_session_switch()
+ *	Send a switch message to firmware to use new cipher spec
+ *
+ * Note: This deletes the older cipher spec and pops the next cipher spec
+ * for use.
+ */
+static bool nss_dtlsmgr_session_switch(struct nss_dtlsmgr_ctx *ctx, struct nss_dtlsmgr_ctx_data *data)
+{
+	const uint32_t type = NSS_DTLS_CMN_MSG_TYPE_SWITCH_DTLS;
+	enum nss_dtls_cmn_error resp = NSS_DTLS_CMN_ERROR_NONE;
+	struct nss_dtls_cmn_msg ndcm = {0};
+	struct nss_dtlsmgr_dtls_data *dtls;
+	nss_tx_status_t status;
+
+	BUG_ON(in_atomic());
+
+	/*
+	 * TODO: Add retry messaging to ensure that in case of failures, due to queue
+	 * full conditions we do attempt few retries before aborting.
+	 */
+	status = nss_dtls_cmn_tx_msg_sync(data->nss_ctx, data->ifnum, type, 0, &ndcm, &resp);
+	if (status != NSS_TX_SUCCESS) {
+		nss_dtlsmgr_warn("%px: msg_sync failed, if_num(%u), status(%d), type(%d), resp(%d)",
+				ctx, data->ifnum, type, status, resp);
+		return false;
+	}
+
+	/*
+	 * We essentially pop the head of the dtls list.
+	 * It is expected that an update should have already
+	 * added a new dtls entry at the tail of the list
+	 */
+	write_lock(&ctx->lock);
+	dtls = list_first_entry_or_null(&data->dtls_active, struct nss_dtlsmgr_dtls_data, list);
+	if (!dtls) {
+		write_unlock(&ctx->lock);
+		return false;
+	}
+
+	list_del(&dtls->list);
+	write_unlock(&ctx->lock);
+
+	nss_dtlsmgr_ctx_free_dtls(dtls);
+	return true;
+}
+
+/*
+ * nss_dtlsmgr_session_create()
+ *	Create DTLS session and associated crypto sessions.
+ */
+struct net_device *nss_dtlsmgr_session_create(struct nss_dtlsmgr_config *cfg)
+{
+	struct nss_dtlsmgr *drv = &g_dtls;
+	struct nss_dtlsmgr_ctx *ctx = NULL;
+	struct net_device *dev;
+	int32_t encap_ifnum;
+	int32_t decap_ifnum;
+	int error;
+
+	if (!atomic_read(&drv->is_configured)) {
+		nss_dtlsmgr_warn("%px: dtls firmware not ready", drv);
+		return NULL;
+	}
+
+	if ((cfg->encap.ver != NSS_DTLSMGR_VERSION_1_0) && (cfg->encap.ver != NSS_DTLSMGR_VERSION_1_2)) {
+		nss_dtlsmgr_warn("%px: invalid encapsulation version(%d)", drv, cfg->encap.ver);
+		return NULL;
+	}
+
+	encap_ifnum = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_INNER);
+	if (encap_ifnum < 0) {
+		nss_dtlsmgr_warn("%px: failed to allocate encap dynamic interface(%u)", drv, encap_ifnum);
+		return NULL;
+	}
+
+	decap_ifnum = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_OUTER);
+	if (decap_ifnum < 0) {
+		nss_dtlsmgr_warn("%px: failed to allocate decap dynamic interface(%u)", drv, decap_ifnum);
+		goto dealloc_encap_node;
+	}
+
+	nss_dtlsmgr_trace("dynamic interfaces, encap(%u), decap(%u)", encap_ifnum, decap_ifnum);
+
+	dev = alloc_netdev(sizeof(*ctx), "dtls%d", NET_NAME_ENUM, nss_dtlsmgr_ctx_dev_setup);
+	if (!dev) {
+		nss_dtlsmgr_warn("%px: unable to allocate dtls device", ctx);
+		goto dealloc_decap_node;
+	}
+
+	ctx = netdev_priv(dev);
+	ctx->dev = dev;
+	rwlock_init(&ctx->lock);
+
+	NSS_DTLSMGR_SET_MAGIC(ctx, NSS_DTLSMGR_CTX_MAGIC);
+
+	error = nss_dtlsmgr_ctx_create_encap(ctx, encap_ifnum, decap_ifnum, cfg);
+	if (error < 0) {
+		nss_dtlsmgr_warn("%px: unable to create encap context, error(%d)", ctx, error);
+		goto free_dev;
+	}
+
+	error = nss_dtlsmgr_ctx_create_decap(ctx, decap_ifnum, encap_ifnum, cfg);
+	if (error < 0) {
+		nss_dtlsmgr_warn("%px: unable to create decap context, error(%d)", ctx, error);
+		goto destroy_encap;
+	}
+
+	/*
+	 * Set the needed headroom and tailroom as a multiple of 4 bytes
+	 * so that the skb data pointer remains 4 byte aligned when the
+	 * headroom/tailroom is adjusted.
+	 */
+	dev->needed_headroom = NSS_DTLSMGR_NEEDED_HEADROOM_SZ;
+	dev->needed_tailroom = NSS_DTLSMGR_NEEDED_TAILROOM_SZ;
+
+	ctx->app_data = cfg->app_data;
+	ctx->notify_cb = cfg->notify;
+	ctx->data_cb = cfg->data;
+
+	/*
+	 * If, the user has not provided the callback function then
+	 * we will register the default callback handler
+	 */
+	if (!ctx->data_cb) {
+		ctx->data_cb = nss_dtlsmgr_ctx_dev_data_callback;
+		ctx->app_data = ctx;
+	}
+
+	error = register_netdev(dev);
+	if (error < 0) {
+		nss_dtlsmgr_warn("%px: unable register net_device(%s)", ctx, dev->name);
+		goto destroy_decap;
+	}
+
+	dev->mtu = dev->mtu - (ctx->encap.headroom + ctx->encap.tailroom);
+
+	nss_dtlsmgr_trace("%px: dtls session(%s) created, encap(%u), decap(%u)",
+			  ctx, dev->name, ctx->encap.ifnum, ctx->decap.ifnum);
+
+	if (nss_dtlsmgr_create_debugfs(ctx)) {
+		nss_dtlsmgr_warn("Failed to create debugfs for ctx(%px)", ctx);
+	}
+
+	return dev;
+
+destroy_decap:
+	nss_dtlsmgr_ctx_deconfigure(ctx, &ctx->decap);
+
+destroy_encap:
+	nss_dtlsmgr_ctx_deconfigure(ctx, &ctx->encap);
+
+free_dev:
+	free_netdev(dev);
+
+dealloc_decap_node:
+	nss_dynamic_interface_dealloc_node(decap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_OUTER);
+
+dealloc_encap_node:
+	nss_dynamic_interface_dealloc_node(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_INNER);
+	return NULL;
+}
+EXPORT_SYMBOL(nss_dtlsmgr_session_create);
+
+/*
+ * nss_dtlsmgr_session_destroy()
+ *	Destroy DTLS session
+ */
+nss_dtlsmgr_status_t nss_dtlsmgr_session_destroy(struct net_device *dev)
+{
+	struct nss_dtlsmgr_ctx *ctx = netdev_priv(dev);
+	NSS_DTLSMGR_VERIFY_MAGIC(ctx);
+
+	/*
+	 * Reset the callback handlers atomically
+	 */
+	xchg(&ctx->notify_cb, NULL);
+	xchg(&ctx->data_cb, NULL);
+
+	nss_dtlsmgr_trace("%px: destroying encap(%u) and decap(%u) sessions",
+			  ctx, ctx->encap.ifnum, ctx->decap.ifnum);
+
+	if (!nss_dtlsmgr_ctx_deconfigure(ctx, &ctx->encap)) {
+		nss_dtlsmgr_warn("%px: unable to deconfigure encap", ctx);
+		return NSS_DTLSMGR_FAIL;
+	}
+
+	if (!nss_dtlsmgr_ctx_deconfigure(ctx, &ctx->decap)) {
+		nss_dtlsmgr_warn("%px: unable to deconfigure decap", ctx);
+		return NSS_DTLSMGR_FAIL;
+	}
+
+	NSS_DTLSMGR_SET_MAGIC(ctx, 0);
+
+	unregister_netdev(dev);
+
+	return NSS_DTLSMGR_OK;
+}
+EXPORT_SYMBOL(nss_dtlsmgr_session_destroy);
+
+/*
+ * nss_dtlsmgr_session_update_encap()
+ *	Update the encapsulation crypto keys.
+ */
+nss_dtlsmgr_status_t nss_dtlsmgr_session_update_encap(struct net_device *dev, struct nss_dtlsmgr_config_update *cfg)
+{
+	struct nss_dtlsmgr_ctx *ctx = netdev_priv(dev);
+	struct nss_dtlsmgr_ctx_data *data = &ctx->encap;
+	struct nss_dtlsmgr_dtls_data *dtls, *prev_dtls;
+
+	NSS_DTLSMGR_VERIFY_MAGIC(ctx);
+
+	dtls = nss_dtlsmgr_ctx_alloc_dtls(ctx, &ctx->encap, &cfg->crypto);
+	if (!dtls) {
+		nss_dtlsmgr_warn("%px: unable to update encap context data", ctx);
+		return NSS_DTLSMGR_FAIL_NOMEM;
+	}
+
+	/*
+	 * Get the first entry in the list to compare the crypto key lengths
+	 */
+	prev_dtls = list_first_entry_or_null(&data->dtls_active, struct nss_dtlsmgr_dtls_data, list);
+	if (!prev_dtls) {
+		nss_dtlsmgr_warn("%px: dtls list is emtpy\n", ctx);
+		return NSS_DTLSMGR_FAIL_NOCRYPTO;
+	}
+
+	/*
+	 * If the new keys lengths are longer, then there isn't enough headroom and tailroom.
+	 */
+	BUG_ON(prev_dtls->iv_len < dtls->iv_len);
+	BUG_ON(prev_dtls->blk_len < dtls->blk_len);
+	BUG_ON(prev_dtls->hash_len < dtls->hash_len);
+
+	nss_dtlsmgr_trace("%px: encap context update allocated (%u)", ctx, ctx->encap.ifnum);
+
+	dtls->epoch = cfg->epoch;
+	dtls->window_size = cfg->window_size;
+
+	if (!nss_dtlsmgr_ctx_configure_dtls(&ctx->encap, dtls)) {
+		nss_dtlsmgr_warn("%px: unable to configure encap dtls", ctx);
+		nss_dtlsmgr_ctx_free_dtls(dtls);
+		return NSS_DTLSMGR_FAIL_MESSAGE;
+	}
+
+	write_lock(&ctx->lock);
+	list_add_tail(&dtls->list, &ctx->encap.dtls_active);
+	write_unlock(&ctx->lock);
+
+	nss_dtlsmgr_trace("%px: encap context update done", ctx);
+	return NSS_DTLSMGR_OK;
+}
+EXPORT_SYMBOL(nss_dtlsmgr_session_update_encap);
+
+/*
+ * nss_dtlsmgr_session_update_decap()
+ *	Update the decapsulation crypto keys.
+ */
+nss_dtlsmgr_status_t nss_dtlsmgr_session_update_decap(struct net_device *dev, struct nss_dtlsmgr_config_update *cfg)
+{
+	struct nss_dtlsmgr_ctx *ctx = netdev_priv(dev);
+	struct nss_dtlsmgr_dtls_data *dtls;
+
+	NSS_DTLSMGR_VERIFY_MAGIC(ctx);
+
+	dtls = nss_dtlsmgr_ctx_alloc_dtls(ctx, &ctx->decap, &cfg->crypto);
+	if (!dtls) {
+		nss_dtlsmgr_warn("%px: unable to update decap context data", ctx);
+		return NSS_DTLSMGR_FAIL_NOMEM;
+	}
+
+	nss_dtlsmgr_trace("%px: decap context update allocated (%u)", ctx, ctx->decap.ifnum);
+
+	dtls->epoch = cfg->epoch;
+	dtls->window_size = cfg->window_size;
+
+	if (!nss_dtlsmgr_ctx_configure_dtls(&ctx->decap, dtls)) {
+		nss_dtlsmgr_warn("%px: unable to configure decap dtls", ctx);
+		nss_dtlsmgr_ctx_free_dtls(dtls);
+		return NSS_DTLSMGR_FAIL_MESSAGE;
+	}
+
+	write_lock(&ctx->lock);
+	list_add_tail(&dtls->list, &ctx->decap.dtls_active);
+	write_unlock(&ctx->lock);
+
+	nss_dtlsmgr_trace("%px: decap context update done", ctx);
+	return NSS_DTLSMGR_OK;
+}
+EXPORT_SYMBOL(nss_dtlsmgr_session_update_decap);
+
+/*
+ * nss_dtlsmgr_session_switch_encap()
+ *	Send a message to encapsulation DTLS interface to switch to the new crypto keys.
+ */
+bool nss_dtlsmgr_session_switch_encap(struct net_device *dev)
+{
+	struct nss_dtlsmgr_ctx *ctx = netdev_priv(dev);
+	struct nss_dtlsmgr_ctx_data *data = &ctx->encap;
+
+	NSS_DTLSMGR_VERIFY_MAGIC(ctx);
+
+	if (!nss_dtlsmgr_session_switch(ctx, data)) {
+		nss_dtlsmgr_warn("%px: failed to send encap switch_dtls(%u)", ctx, data->ifnum);
+		return false;
+	}
+
+	nss_dtlsmgr_trace("%px: encap(%u) cipher switch done", ctx, data->ifnum);
+	return true;
+}
+EXPORT_SYMBOL(nss_dtlsmgr_session_switch_encap);
+
+/*
+ * nss_dtlsmgr_session_switch_decap()
+ *	Send a message to decapsulation DTLS interface to switch to the new crypto keys.
+ */
+bool nss_dtlsmgr_session_switch_decap(struct net_device *dev)
+{
+	struct nss_dtlsmgr_ctx *ctx = netdev_priv(dev);
+	struct nss_dtlsmgr_ctx_data *data = &ctx->decap;
+
+	NSS_DTLSMGR_VERIFY_MAGIC(ctx);
+
+	if (!nss_dtlsmgr_session_switch(ctx, data)) {
+		nss_dtlsmgr_warn("%px: failed to send decap switch_dtls(%u)", ctx, data->ifnum);
+		return false;
+	}
+
+	nss_dtlsmgr_trace("%px: decap(%u) cipher switch done", ctx, data->ifnum);
+	return true;
+}
+EXPORT_SYMBOL(nss_dtlsmgr_session_switch_decap);
+
+/*
+ * nss_dtlsmgr_get_interface()
+ *	Returns NSS DTLS interface number for encap/decap on success.
+ */
+int32_t nss_dtlsmgr_get_interface(struct net_device *dev, enum nss_dtlsmgr_interface_type type)
+{
+	int32_t ifnum;
+
+	switch (type) {
+	case NSS_DTLSMGR_INTERFACE_TYPE_INNER:
+		ifnum = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_INNER);
+		break;
+
+	case NSS_DTLSMGR_INTERFACE_TYPE_OUTER:
+		ifnum = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_OUTER);
+		break;
+
+	default:
+		nss_dtlsmgr_warn("%px: invalid interface type %d", dev, type);
+		return -EINVAL;
+	}
+
+	if (ifnum < 0) {
+		nss_dtlsmgr_warn("%px: couldn't find DTLS interface number (%d)", dev, ifnum);
+		return ifnum;
+	}
+
+	return nss_dtls_cmn_get_ifnum(ifnum);
+}
+EXPORT_SYMBOL(nss_dtlsmgr_get_interface);
diff --git a/qca-nss-clients/dtls/v2.0/nss_dtlsmgr_ctx_dev.c b/qca-nss-clients/dtls/v2.0/nss_dtlsmgr_ctx_dev.c
new file mode 100644
index 0000000..4bb736e
--- /dev/null
+++ b/qca-nss-clients/dtls/v2.0/nss_dtlsmgr_ctx_dev.c
@@ -0,0 +1,532 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017 - 2018, 2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_connmgr_dtls_ctx_dev.c
+ *	NSS DTLS Manager context device
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/etherdevice.h>
+#include <linux/udp.h>
+#include <linux/ipv6.h>
+#include <net/ip.h>
+#include <net/ip6_route.h>
+#include <net/ipv6.h>
+#include <net/protocol.h>
+#include <net/route.h>
+#include <crypto/aes.h>
+#include <crypto/sha.h>
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+#include <nss_dtls_cmn.h>
+#include <nss_dtlsmgr.h>
+
+#include "nss_dtlsmgr_private.h"
+
+/*
+ * nss_dtlsmgr_ctx_dev_event()
+ *	Event Callback to receive events from NSS.
+ */
+static void nss_dtlsmgr_ctx_dev_update_stats(struct nss_dtlsmgr_ctx *ctx,
+				struct nss_dtls_cmn_ctx_stats *msg_stats,
+				struct nss_dtlsmgr_stats *stats,
+				bool encap)
+{
+	int i;
+
+	dev_hold(ctx->dev);
+
+	stats->tx_packets += msg_stats->pkt.tx_packets;
+	stats->tx_bytes += msg_stats->pkt.tx_bytes;
+
+	stats->rx_packets += msg_stats->pkt.rx_packets;
+	stats->rx_bytes += msg_stats->pkt.rx_bytes;
+	stats->rx_dropped += nss_cmn_rx_dropped_sum(&msg_stats->pkt);
+	stats->rx_single_rec += msg_stats->rx_single_rec;
+	stats->rx_multi_rec += msg_stats->rx_multi_rec;
+
+	stats->fail_crypto_resource += msg_stats->fail_crypto_resource;
+	stats->fail_crypto_enqueue += msg_stats->fail_crypto_enqueue;
+	stats->fail_headroom += msg_stats->fail_headroom;
+	stats->fail_tailroom += msg_stats->fail_tailroom;
+	stats->fail_ver += msg_stats->fail_ver;
+	stats->fail_epoch += msg_stats->fail_epoch;
+	stats->fail_dtls_record += msg_stats->fail_dtls_record;
+	stats->fail_capwap += msg_stats->fail_capwap;
+	stats->fail_replay += msg_stats->fail_replay;
+	stats->fail_replay_dup += msg_stats->fail_replay_dup;
+	stats->fail_replay_win += msg_stats->fail_replay_win;
+	stats->fail_queue += msg_stats->fail_queue;
+	stats->fail_queue_nexthop += msg_stats->fail_queue_nexthop;
+	stats->fail_pbuf_alloc += msg_stats->fail_pbuf_alloc;
+	stats->fail_pbuf_linear += msg_stats->fail_pbuf_linear;
+	stats->fail_pbuf_stats += msg_stats->fail_pbuf_stats;
+	stats->fail_pbuf_align += msg_stats->fail_pbuf_align;
+	stats->fail_ctx_active += msg_stats->fail_ctx_active;
+	stats->fail_hwctx_active += msg_stats->fail_hwctx_active;
+	stats->fail_cipher += msg_stats->fail_cipher;
+	stats->fail_auth += msg_stats->fail_auth;
+	stats->fail_seq_ovf += msg_stats->fail_seq_ovf;
+	stats->fail_blk_len += msg_stats->fail_blk_len;
+	stats->fail_hash_len += msg_stats->fail_hash_len;
+
+	stats->fail_hw.len_error += msg_stats->fail_hw.len_error;
+	stats->fail_hw.token_error += msg_stats->fail_hw.token_error;
+	stats->fail_hw.bypass_error += msg_stats->fail_hw.bypass_error;
+	stats->fail_hw.config_error += msg_stats->fail_hw.config_error;
+	stats->fail_hw.algo_error += msg_stats->fail_hw.algo_error;
+	stats->fail_hw.hash_ovf_error += msg_stats->fail_hw.hash_ovf_error;
+	stats->fail_hw.ttl_error += msg_stats->fail_hw.ttl_error;
+	stats->fail_hw.csum_error += msg_stats->fail_hw.csum_error;
+	stats->fail_hw.timeout_error += msg_stats->fail_hw.timeout_error;
+
+	for (i = 0; i < NSS_DTLS_CMN_CLE_MAX; i++)
+		stats->fail_cle[i] += msg_stats->fail_cle[i];
+
+	if (ctx->notify_cb)
+		ctx->notify_cb(ctx->app_data, ctx->dev, stats, encap);
+
+	dev_put(ctx->dev);
+}
+
+/*
+ * nss_dtlsmgr_ctx_dev_event_inner()
+ *	Event handler for DTLS inner interface
+ */
+void nss_dtlsmgr_ctx_dev_event_inner(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_dtlsmgr_ctx_data *data = (struct nss_dtlsmgr_ctx_data *)app_data;
+	struct nss_dtls_cmn_msg *ndcm = (struct nss_dtls_cmn_msg *)ncm;
+	struct nss_dtls_cmn_ctx_stats *msg_stats = &ndcm->msg.stats;
+	struct nss_dtlsmgr_ctx *ctx;
+
+	if (ncm->type != NSS_DTLS_CMN_MSG_TYPE_SYNC_STATS) {
+		nss_dtlsmgr_warn("%px: unsupported message type(%d)", data, ncm->type);
+		return;
+	}
+
+	ctx = container_of(data, struct nss_dtlsmgr_ctx, encap);
+	NSS_DTLSMGR_VERIFY_MAGIC(ctx);
+
+	nss_dtlsmgr_ctx_dev_update_stats(ctx, msg_stats, &data->stats, true);
+}
+
+/*
+ * nss_dtlsmgr_ctx_dev_event_outer()
+ *	Event handler for DTLS outer interface
+ */
+void nss_dtlsmgr_ctx_dev_event_outer(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_dtlsmgr_ctx_data *data = (struct nss_dtlsmgr_ctx_data *)app_data;
+	struct nss_dtls_cmn_msg *ndcm = (struct nss_dtls_cmn_msg *)ncm;
+	struct nss_dtls_cmn_ctx_stats *msg_stats = &ndcm->msg.stats;
+	struct nss_dtlsmgr_ctx *ctx;
+
+	if (ncm->type != NSS_DTLS_CMN_MSG_TYPE_SYNC_STATS) {
+		nss_dtlsmgr_warn("%px: unsupported message type(%d)", data, ncm->type);
+		return;
+	}
+
+	ctx = container_of(data, struct nss_dtlsmgr_ctx, decap);
+	NSS_DTLSMGR_VERIFY_MAGIC(ctx);
+
+	nss_dtlsmgr_ctx_dev_update_stats(ctx, msg_stats, &data->stats, false);
+}
+
+/*
+ * nss_dtls_ctx_dev_data_callback()
+ *	Default callback if the user does not provide one
+ */
+void nss_dtlsmgr_ctx_dev_data_callback(void *app_data, struct sk_buff *skb)
+{
+	struct nss_dtlsmgr_metadata *ndm;
+	struct nss_dtlsmgr_stats *stats;
+	struct nss_dtlsmgr_ctx *ctx;
+
+	ctx = (struct nss_dtlsmgr_ctx *)app_data;
+	NSS_DTLSMGR_VERIFY_MAGIC(ctx);
+
+	stats = &ctx->decap.stats;
+	ndm = (struct nss_dtlsmgr_metadata *)skb->data;
+	if (ndm->result != NSS_DTLSMGR_METADATA_RESULT_OK) {
+		nss_dtlsmgr_warn("%px: DTLS packets has error(s): %d", skb->dev, ndm->result);
+		dev_kfree_skb_any(skb);
+		stats->fail_host_rx++;
+		return;
+	}
+
+	/*
+	 * Remove the DTLS metadata and indicate it up the stack
+	 */
+	skb_pull(skb, sizeof(*ndm));
+	skb_reset_mac_header(skb);
+	skb_reset_network_header(skb);
+
+	/*
+	 * Check IP version to identify if it is an IP packet
+	 */
+	switch (ip_hdr(skb)->version) {
+	case IPVERSION:
+		skb->protocol = htons(ETH_P_IP);
+		skb_set_transport_header(skb, sizeof(struct iphdr));
+		break;
+
+	case 6:
+		skb->protocol = htons(ETH_P_IPV6);
+		skb_set_transport_header(skb, sizeof(struct ipv6hdr));
+		break;
+
+	default:
+		nss_dtlsmgr_trace("%px: non-IP packet received (ifnum:%d)", ctx, ctx->decap.ifnum);
+	}
+
+	netif_receive_skb(skb);
+}
+
+/*
+ * nss_dtlsmgr_ctx_dev_rx_inner()
+ *	Receive and process packet after DTLS decapsulation
+ */
+void nss_dtlsmgr_ctx_dev_rx_inner(struct net_device *dev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	struct nss_dtlsmgr_ctx *ctx;
+	struct nss_dtlsmgr_stats *stats;
+
+	BUG_ON(!dev);
+	BUG_ON(!skb);
+
+	dev_hold(dev);
+
+	ctx = netdev_priv(dev);
+	NSS_DTLSMGR_VERIFY_MAGIC(ctx);
+
+	stats = &ctx->decap.stats;
+
+	nss_dtlsmgr_trace("%px: RX DTLS decapsulated packet, ifnum(%d)", dev, ctx->decap.ifnum);
+
+	skb->pkt_type = PACKET_HOST;
+	skb->skb_iif = dev->ifindex;
+	skb->dev = dev;
+
+	ctx->data_cb(ctx->app_data, skb);
+	dev_put(dev);
+}
+
+/*
+ * nss_dtlsmgr_ctx_dev_rx_outer()
+ *	Receive and process packet from NSS after encapsulation.
+ */
+void nss_dtlsmgr_ctx_dev_rx_outer(struct net_device *dev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	struct nss_dtlsmgr_ctx *ctx;
+	struct nss_dtlsmgr_stats *stats;
+
+	BUG_ON(!dev);
+	BUG_ON(!skb);
+
+	dev_hold(dev);
+
+	ctx = netdev_priv(dev);
+	NSS_DTLSMGR_VERIFY_MAGIC(ctx);
+
+	stats = &ctx->encap.stats;
+
+	nss_dtlsmgr_trace("%px: RX DTLS encapsulated packet, ifnum(%d)", dev, ctx->encap.ifnum);
+
+	skb->pkt_type = PACKET_HOST;
+	skb->skb_iif = dev->ifindex;
+	skb->dev = dev;
+
+	skb_reset_mac_header(skb);
+	skb_reset_network_header(skb);
+
+	/*
+	 * Check IP version to identify if it is an IP packet
+	 */
+	switch (ip_hdr(skb)->version) {
+	case IPVERSION: {
+		struct rtable *rt;
+		struct iphdr *iph;
+
+		skb->protocol = htons(ETH_P_IP);
+		skb_set_transport_header(skb, sizeof(struct iphdr));
+
+		iph = ip_hdr(skb);
+		rt = ip_route_output(&init_net, iph->daddr, iph->saddr, 0, 0);
+		if (IS_ERR(rt)) {
+			nss_dtlsmgr_warn("%px: No IPv4 route or out dev", dev);
+			dev_kfree_skb_any(skb);
+			stats->fail_host_rx++;
+			break;
+		}
+
+		skb_dst_set(skb, &rt->dst);
+		skb->ip_summed = CHECKSUM_COMPLETE;
+		ip_local_out(&init_net, NULL, skb);
+		break;
+	}
+
+	case 6: {
+		struct ipv6hdr *ip6h;
+		struct dst_entry *dst;
+		struct flowi6 fl6;
+
+		skb->protocol = htons(ETH_P_IPV6);
+		skb_set_transport_header(skb, sizeof(struct ipv6hdr));
+
+		ip6h = ipv6_hdr(skb);
+		memset(&fl6, 0, sizeof(fl6));
+		memcpy(&fl6.daddr, &ip6h->daddr, sizeof(fl6.daddr));
+		memcpy(&fl6.saddr, &ip6h->saddr, sizeof(fl6.saddr));
+
+		dst = ip6_route_output(&init_net, NULL, &fl6);
+		if (IS_ERR(dst)) {
+			nss_dtlsmgr_warn("%px: No IPv6 route or out dev", dev);
+			dev_kfree_skb_any(skb);
+			stats->fail_host_rx++;
+			break;
+		}
+
+		skb_dst_set(skb, dst);
+		skb->ip_summed = CHECKSUM_COMPLETE;
+		ip6_local_out(&init_net, NULL, skb);
+		break;
+	}
+
+	default:
+		/*
+		 * For a non-IP packet, if there is no registered
+		 * callback then it has to be dropped.
+		 */
+		nss_dtlsmgr_trace("%px: received non-IP packet", ctx);
+		dev_kfree_skb_any(skb);
+		stats->fail_host_rx++;
+	}
+
+	dev_put(dev);
+	return;
+}
+
+/*
+ * nss_dtlsmgr_ctx_dev_tx()
+ *	Transmit packet to DTLS node in NSS firmware.
+ */
+static netdev_tx_t nss_dtlsmgr_ctx_dev_tx(struct sk_buff *skb, struct net_device *dev)
+{
+	struct nss_dtlsmgr_ctx *ctx = netdev_priv(dev);
+	struct nss_dtlsmgr_metadata *ndm = NULL;
+	struct nss_dtlsmgr_ctx_data *encap;
+	struct nss_dtlsmgr_stats *stats;
+	struct sk_buff *skb2;
+	bool mdata_init;
+	bool expand_skb;
+	int nhead, ntail;
+
+	NSS_DTLSMGR_VERIFY_MAGIC(ctx);
+	encap = &ctx->encap;
+	stats = &encap->stats;
+
+	nhead = dev->needed_headroom;
+	ntail = dev->needed_tailroom;
+
+	/*
+	 * Check if skb is shared; unshare in case it is shared
+	 */
+	if (skb_shared(skb))
+		skb = skb_unshare(skb, in_atomic() ? GFP_ATOMIC : GFP_KERNEL);
+
+	nss_dtlsmgr_trace("%px: TX packet for DTLS encapsulation, ifnum(%d)", dev, encap->ifnum);
+
+	if (encap->flags & NSS_DTLSMGR_ENCAP_METADATA) {
+		ndm = (struct nss_dtlsmgr_metadata *)skb->data;
+
+		/*
+		 * Check if metadata is initialized
+		 */
+		mdata_init = ndm->flags & NSS_DTLSMGR_METADATA_FLAG_ENC;
+		if (unlikely(!mdata_init))
+			goto free;
+
+	}
+
+	/*
+	 * For all these cases
+	 * - create a writable copy of buffer
+	 * - increase the head room
+	 * - increase the tail room
+	 * - skb->data is not 4-byte aligned
+	 */
+	expand_skb = skb_cloned(skb) || (skb_headroom(skb) < nhead) || (skb_tailroom(skb) < ntail)
+			|| !IS_ALIGNED((unsigned long)skb->data, sizeof(uint32_t));
+
+	if (expand_skb) {
+		skb2 = skb_copy_expand(skb, nhead, ntail, GFP_ATOMIC);
+		if (!skb2) {
+			nss_dtlsmgr_trace("%px: unable to expand buffer for (%s)", ctx, dev->name);
+			/*
+			 * Update stats based on whether headroom or tailroom or both failed
+			 */
+			stats->fail_headroom = stats->fail_headroom + (skb_headroom(skb) < nhead);
+			stats->fail_tailroom = stats->fail_tailroom + (skb_tailroom(skb) < ntail);
+			goto free;
+		}
+
+		dev_kfree_skb_any(skb);
+		skb = skb2;
+	}
+
+	if (nss_dtls_cmn_tx_buf(skb, encap->ifnum, encap->nss_ctx) != NSS_TX_SUCCESS) {
+		nss_dtlsmgr_trace("%px: unable to tx buffer for (%u)", ctx, encap->ifnum);
+		return NETDEV_TX_BUSY;
+	}
+
+	return NETDEV_TX_OK;
+free:
+	dev_kfree_skb_any(skb);
+	stats->fail_host_tx++;
+	return NETDEV_TX_OK;
+}
+
+/*
+ * nss_dtlsmgr_ctx_dev_close()
+ *	Stop packet transmission on the DTLS network device.
+ */
+static int nss_dtlsmgr_ctx_dev_close(struct net_device *dev)
+{
+	netif_stop_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_dtlsmgr_ctx_dev_open()
+ *	Start processing packets on the DTLS network device.
+ */
+static int nss_dtlsmgr_ctx_dev_open(struct net_device *dev)
+{
+	netif_start_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_dtlsmgr_ctx_dev_free()
+ *	Free an existing DTLS context device.
+ */
+static void nss_dtlsmgr_ctx_dev_free(struct net_device *dev)
+{
+	struct nss_dtlsmgr_ctx *ctx = netdev_priv(dev);
+
+	nss_dtlsmgr_trace("%px: free dtls context device(%s)", dev, dev->name);
+
+	if (ctx->dentry)
+		debugfs_remove_recursive(ctx->dentry);
+
+	free_netdev(dev);
+}
+
+/*
+ * nss_dtlsmgr_ctx_get_dev_stats64()
+ *	To get the netdev stats
+ */
+static struct rtnl_link_stats64 *nss_dtlsmgr_ctx_get_dev_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	struct nss_dtlsmgr_ctx *ctx = netdev_priv(dev);
+	struct nss_dtlsmgr_stats *encap_stats, *decap_stats;
+
+	encap_stats = &ctx->encap.stats;
+	decap_stats = &ctx->decap.stats;
+
+	stats->rx_packets = decap_stats->rx_packets;
+	stats->rx_bytes = decap_stats->rx_bytes;
+	stats->rx_dropped = decap_stats->rx_dropped;
+
+	stats->tx_bytes = encap_stats->tx_bytes;
+	stats->tx_packets = encap_stats->tx_packets;
+	stats->tx_dropped = encap_stats->fail_headroom + encap_stats->fail_tailroom;
+
+	return stats;
+}
+
+/*
+ * nss_dtlsmgr_ctx_dev_stats64()
+ *	Report packet statistics to Linux.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0))
+static struct rtnl_link_stats64 *nss_dtlsmgr_ctx_dev_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	return nss_dtlsmgr_ctx_get_dev_stats64(dev, stats);
+}
+#else
+static void nss_dtlsmgr_ctx_dev_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	nss_dtlsmgr_ctx_get_dev_stats64(dev, stats);
+}
+#endif
+
+/*
+ * nss_dtlsmgr_ctx_dev_change_mtu()
+ *	Change MTU size of DTLS context device.
+ */
+static int32_t nss_dtlsmgr_ctx_dev_change_mtu(struct net_device *dev, int32_t mtu)
+{
+	dev->mtu = mtu;
+	return 0;
+}
+
+/*
+ * DTLS netdev ops
+ */
+static const struct net_device_ops nss_dtlsmgr_ctx_dev_ops = {
+	.ndo_start_xmit = nss_dtlsmgr_ctx_dev_tx,
+	.ndo_open = nss_dtlsmgr_ctx_dev_open,
+	.ndo_stop = nss_dtlsmgr_ctx_dev_close,
+	.ndo_get_stats64 = nss_dtlsmgr_ctx_dev_stats64,
+	.ndo_change_mtu = nss_dtlsmgr_ctx_dev_change_mtu,
+};
+
+/*
+ * nss_dtlsmgr_ctx_dev_setup()
+ *	Setup the DTLS network device.
+ */
+void nss_dtlsmgr_ctx_dev_setup(struct net_device *dev)
+{
+	dev->addr_len = ETH_ALEN;
+	dev->mtu = ETH_DATA_LEN;
+	dev->hard_header_len = 0;
+	dev->needed_headroom = 0;
+	dev->needed_tailroom = 0;
+
+	dev->type = ARPHRD_TUNNEL;
+	dev->ethtool_ops = NULL;
+	dev->header_ops = NULL;
+	dev->netdev_ops = &nss_dtlsmgr_ctx_dev_ops;
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 11, 8))
+	dev->destructor = nss_dtlsmgr_ctx_dev_free;
+#else
+	dev->priv_destructor = nss_dtlsmgr_ctx_dev_free;
+#endif
+	memcpy(dev->dev_addr, "\xaa\xbb\xcc\xdd\xee\xff", dev->addr_len);
+	memset(dev->broadcast, 0xff, dev->addr_len);
+	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
+}
diff --git a/qca-nss-clients/dtls/v2.0/nss_dtlsmgr_ctx_stats.c b/qca-nss-clients/dtls/v2.0/nss_dtlsmgr_ctx_stats.c
new file mode 100644
index 0000000..5d2b4f3
--- /dev/null
+++ b/qca-nss-clients/dtls/v2.0/nss_dtlsmgr_ctx_stats.c
@@ -0,0 +1,240 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_dtlsmgr_ctx_stats.c
+ *	NSS DTLS Manager context statistics
+ */
+
+#include <linux/atomic.h>
+#include <linux/crypto.h>
+#include <linux/debugfs.h>
+#include <linux/module.h>
+#include <linux/rtnetlink.h>
+#include <linux/types.h>
+#include <linux/version.h>
+
+#include <nss_api_if.h>
+#include <nss_dtlsmgr.h>
+
+#include "nss_dtlsmgr_private.h"
+
+#define NSS_DTLSMGR_STATS_MAX_STR_LENGTH 64
+#define NSS_DTLSMGR_STATS_EXTRA_LINES 16
+
+extern struct nss_dtlsmgr g_dtls;
+
+/*
+ * nss_dtlsmgr_ctx_fill_hw_error_stats()
+ *	Fill hardware error statistics
+ */
+static ssize_t nss_dtlsmgr_ctx_fill_hw_error_stats(struct nss_dtlsmgr_stats *stats, char *buf,
+						   ssize_t max_buf_len, ssize_t len)
+{
+	int i;
+
+	len += snprintf(buf + len, max_buf_len, "\nHardware Errors\n---------------\n");
+	len += snprintf(buf + len, max_buf_len, "length_error        = %lld\n", stats->fail_hw.len_error);
+	len += snprintf(buf + len, max_buf_len, "token_error         = %lld\n", stats->fail_hw.token_error);
+	len += snprintf(buf + len, max_buf_len, "bypass_error        = %lld\n", stats->fail_hw.bypass_error);
+	len += snprintf(buf + len, max_buf_len, "config_error        = %lld\n", stats->fail_hw.config_error);
+	len += snprintf(buf + len, max_buf_len, "algo_error          = %lld\n", stats->fail_hw.algo_error);
+	len += snprintf(buf + len, max_buf_len, "hash_ovf_error      = %lld\n", stats->fail_hw.hash_ovf_error);
+	len += snprintf(buf + len, max_buf_len, "ttl_error           = %lld\n", stats->fail_hw.ttl_error);
+	len += snprintf(buf + len, max_buf_len, "csum_error          = %lld\n", stats->fail_hw.csum_error);
+	len += snprintf(buf + len, max_buf_len, "timeout_error       = %lld\n", stats->fail_hw.timeout_error);
+
+	len += snprintf(buf + len, max_buf_len, "\nClassifcation Errors\n---------------------\n");
+	for (i = 0; i < NSS_DTLS_CMN_CLE_MAX; i++) {
+		/*
+		 * Don't print if there are no errors
+		 */
+		if (!stats->fail_cle[i])
+			continue;
+		len += snprintf(buf + len, max_buf_len, "cle_error_%02d   - %lld\n", i, stats->fail_cle[i]);
+	}
+
+	return len;
+}
+
+/*
+ * nss_dtlsmgr_ctx_encap_stats_read()
+ *	Read the DTLS encapsulation statistics.
+ */
+static ssize_t nss_dtlsmgr_ctx_encap_stats_read(struct file *filep, char __user *buffer, size_t count, loff_t *ppos)
+{
+	struct nss_dtlsmgr_ctx *ctx = filep->private_data;
+	struct nss_dtlsmgr_stats *stats;
+	ssize_t max_buf_len, len, ret;
+	char *buf;
+
+	NSS_DTLSMGR_VERIFY_MAGIC(ctx);
+
+	/*
+	 * (Lines of output) * (Max string length)
+	 */
+	max_buf_len = ((sizeof(*stats) / sizeof(uint64_t)) + NSS_DTLSMGR_STATS_EXTRA_LINES) *
+		      NSS_DTLSMGR_STATS_MAX_STR_LENGTH;
+
+	buf = vzalloc(max_buf_len);
+	if (!buf) {
+		nss_dtlsmgr_warn("Failed to allocate memory for statistic buffer");
+		return 0;
+	}
+
+	/*
+	 * Fill encap statistics
+	 */
+	stats = &ctx->encap.stats;
+	len = snprintf(buf, max_buf_len, "ENCAPSULATION INTERFACE (%d) STATISTICS\n", ctx->encap.ifnum);
+	len += snprintf(buf + len, max_buf_len - len, "rx_packets           = %lld\n", stats->rx_packets);
+	len += snprintf(buf + len, max_buf_len - len, "rx_bytes             = %lld\n", stats->rx_bytes);
+	len += snprintf(buf + len, max_buf_len - len, "rx_dropped           = %lld\n", stats->rx_dropped);
+	len += snprintf(buf + len, max_buf_len - len, "rx_single_rec        = %lld\n", stats->rx_single_rec);
+	len += snprintf(buf + len, max_buf_len - len, "rx_multi_rec         = %lld\n", stats->rx_multi_rec);
+	len += snprintf(buf + len, max_buf_len - len, "tx_packets           = %lld\n", stats->tx_packets);
+	len += snprintf(buf + len, max_buf_len - len, "tx_bytes             = %lld\n", stats->tx_bytes);
+	len += snprintf(buf + len, max_buf_len - len, "fail_crypto_resource = %lld\n", stats->fail_crypto_resource);
+	len += snprintf(buf + len, max_buf_len - len, "fail_crypto_enqueue  = %lld\n", stats->fail_crypto_enqueue);
+	len += snprintf(buf + len, max_buf_len - len, "fail_headroom        = %lld\n", stats->fail_headroom);
+	len += snprintf(buf + len, max_buf_len - len, "fail_tailroom        = %lld\n", stats->fail_tailroom);
+	len += snprintf(buf + len, max_buf_len - len, "fail_queue           = %lld\n", stats->fail_queue);
+	len += snprintf(buf + len, max_buf_len - len, "fail_queue_nexthop   = %lld\n", stats->fail_queue_nexthop);
+	len += snprintf(buf + len, max_buf_len - len, "fail_pbuf_alloc      = %lld\n", stats->fail_pbuf_alloc);
+	len += snprintf(buf + len, max_buf_len - len, "fail_pbuf_linear     = %lld\n", stats->fail_pbuf_linear);
+	len += snprintf(buf + len, max_buf_len - len, "fail_pbuf_stats      = %lld\n", stats->fail_pbuf_stats);
+	len += snprintf(buf + len, max_buf_len - len, "fail_pbuf_align      = %lld\n", stats->fail_pbuf_align);
+	len += snprintf(buf + len, max_buf_len - len, "fail_ctx_active      = %lld\n", stats->fail_ctx_active);
+	len += snprintf(buf + len, max_buf_len - len, "fail_hwctx_active    = %lld\n", stats->fail_hwctx_active);
+	len += snprintf(buf + len, max_buf_len - len, "fail_cipher          = %lld\n", stats->fail_cipher);
+	len += snprintf(buf + len, max_buf_len - len, "fail_auth            = %lld\n", stats->fail_auth);
+	len += snprintf(buf + len, max_buf_len - len, "fail_seq_overflow    = %lld\n", stats->fail_seq_ovf);
+	len += snprintf(buf + len, max_buf_len - len, "fail_host_tx         = %lld\n", stats->fail_host_tx);
+	len += snprintf(buf + len, max_buf_len - len, "fail_host_rx         = %lld\n", stats->fail_host_rx);
+
+	/* Returns total number of bytes written to the buffer */
+	len = nss_dtlsmgr_ctx_fill_hw_error_stats(stats, buf, max_buf_len, len);
+
+	ret = simple_read_from_buffer(buffer, count, ppos, buf, len);
+	vfree(buf);
+
+	return ret;
+}
+/*
+ * nss_dtlsmgr_ctx_decap_stats_read()
+ *	Read the DTLS decapsulation statistics.
+ */
+static ssize_t nss_dtlsmgr_ctx_decap_stats_read(struct file *filep, char __user *buffer, size_t count, loff_t *ppos)
+{
+	struct nss_dtlsmgr_ctx *ctx = filep->private_data;
+	struct nss_dtlsmgr_stats *stats;
+	ssize_t max_buf_len, ret;
+	ssize_t len = 0;
+	char *buf;
+
+	NSS_DTLSMGR_VERIFY_MAGIC(ctx);
+
+	/*
+	 * (Lines of output) * (Max string length)
+	 */
+	max_buf_len = ((sizeof(*stats) / sizeof(uint64_t)) + NSS_DTLSMGR_STATS_EXTRA_LINES) *
+		      NSS_DTLSMGR_STATS_MAX_STR_LENGTH;
+
+	buf = vzalloc(max_buf_len);
+	if (!buf) {
+		nss_dtlsmgr_warn("Failed to allocate memory for statistic buffer");
+		return 0;
+	}
+
+	/*
+	 * Fill decap statistics
+	 */
+	stats = &ctx->decap.stats;
+	len += snprintf(buf, max_buf_len - len, "DECAPSULATION INTERFACE (%d) STATISTICS\n", ctx->decap.ifnum);
+	len += snprintf(buf + len, max_buf_len - len, "rx_packets           = %lld\n", stats->rx_packets);
+	len += snprintf(buf + len, max_buf_len - len, "rx_bytes             = %lld\n", stats->rx_bytes);
+	len += snprintf(buf + len, max_buf_len - len, "rx_dropped           = %lld\n", stats->rx_dropped);
+	len += snprintf(buf + len, max_buf_len - len, "rx_single_rec        = %lld\n", stats->rx_single_rec);
+	len += snprintf(buf + len, max_buf_len - len, "rx_multi_rec         = %lld\n", stats->rx_multi_rec);
+	len += snprintf(buf + len, max_buf_len - len, "tx_packets           = %lld\n", stats->tx_packets);
+	len += snprintf(buf + len, max_buf_len - len, "tx_bytes             = %lld\n", stats->tx_bytes);
+	len += snprintf(buf + len, max_buf_len - len, "fail_crypto_resource = %lld\n", stats->fail_crypto_resource);
+	len += snprintf(buf + len, max_buf_len - len, "fail_crypto_enqueue  = %lld\n", stats->fail_crypto_enqueue);
+	len += snprintf(buf + len, max_buf_len - len, "fail_version         = %lld\n", stats->fail_ver);
+	len += snprintf(buf + len, max_buf_len - len, "fail_epoch           = %lld\n", stats->fail_epoch);
+	len += snprintf(buf + len, max_buf_len - len, "fail_dtls_record     = %lld\n", stats->fail_dtls_record);
+	len += snprintf(buf + len, max_buf_len - len, "fail_capwap          = %lld\n", stats->fail_capwap);
+	len += snprintf(buf + len, max_buf_len - len, "fail_replay          = %lld\n", stats->fail_replay);
+	len += snprintf(buf + len, max_buf_len - len, "fail_replay_dup      = %lld\n", stats->fail_replay_dup);
+	len += snprintf(buf + len, max_buf_len - len, "fail_replay_window   = %lld\n", stats->fail_replay_win);
+	len += snprintf(buf + len, max_buf_len - len, "fail_queue           = %lld\n", stats->fail_queue);
+	len += snprintf(buf + len, max_buf_len - len, "fail_queue_nexthop   = %lld\n", stats->fail_queue_nexthop);
+	len += snprintf(buf + len, max_buf_len - len, "fail_pbuf_alloc      = %lld\n", stats->fail_pbuf_alloc);
+	len += snprintf(buf + len, max_buf_len - len, "fail_pbuf_linear     = %lld\n", stats->fail_pbuf_linear);
+	len += snprintf(buf + len, max_buf_len - len, "fail_pbuf_stats      = %lld\n", stats->fail_pbuf_stats);
+	len += snprintf(buf + len, max_buf_len - len, "fail_pbuf_align      = %lld\n", stats->fail_pbuf_align);
+	len += snprintf(buf + len, max_buf_len - len, "fail_ctx_active      = %lld\n", stats->fail_ctx_active);
+	len += snprintf(buf + len, max_buf_len - len, "fail_hwctx_active    = %lld\n", stats->fail_hwctx_active);
+	len += snprintf(buf + len, max_buf_len - len, "fail_cipher          = %lld\n", stats->fail_cipher);
+	len += snprintf(buf + len, max_buf_len - len, "fail_auth            = %lld\n", stats->fail_auth);
+	len += snprintf(buf + len, max_buf_len - len, "fail_seq_overflow    = %lld\n", stats->fail_seq_ovf);
+	len += snprintf(buf + len, max_buf_len - len, "fail_block_length    = %lld\n", stats->fail_blk_len);
+	len += snprintf(buf + len, max_buf_len - len, "fail_hash_length     = %lld\n", stats->fail_hash_len);
+	len += snprintf(buf + len, max_buf_len - len, "fail_host_tx         = %lld\n", stats->fail_host_tx);
+	len += snprintf(buf + len, max_buf_len - len, "fail_host_rx         = %lld\n", stats->fail_host_rx);
+
+	/* Returns total number of bytes written to the buffer */
+	len = nss_dtlsmgr_ctx_fill_hw_error_stats(stats, buf, max_buf_len, len);
+
+	ret = simple_read_from_buffer(buffer, count, ppos, buf, len);
+	vfree(buf);
+
+	return ret;
+}
+
+/*
+ * Context file operation structure instance
+ */
+static const struct file_operations nss_dtlsmgr_encap_stats_op = {
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.read = nss_dtlsmgr_ctx_encap_stats_read,
+};
+
+static const struct file_operations nss_dtlsmgr_decap_stats_op = {
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.read = nss_dtlsmgr_ctx_decap_stats_read,
+};
+
+/*
+ * nss_dtlmsgr_create_debugfs()
+ *	Create debugfs files to display session statistics.
+ */
+int nss_dtlsmgr_create_debugfs(struct nss_dtlsmgr_ctx *ctx)
+{
+	struct nss_dtlsmgr *drv = &g_dtls;
+
+	ctx->dentry = debugfs_create_dir(ctx->dev->name, drv->root_dir);
+	if (!ctx->dentry) {
+		nss_dtlsmgr_warn("failed to create debugfs directory");
+		return -1;
+	}
+
+	debugfs_create_file("encap_stats", S_IRUGO, ctx->dentry, ctx, &nss_dtlsmgr_encap_stats_op);
+	debugfs_create_file("decap_stats", S_IRUGO, ctx->dentry, ctx, &nss_dtlsmgr_decap_stats_op);
+	return 0;
+}
diff --git a/qca-nss-clients/dtls/v2.0/nss_dtlsmgr_private.h b/qca-nss-clients/dtls/v2.0/nss_dtlsmgr_private.h
new file mode 100644
index 0000000..131192c
--- /dev/null
+++ b/qca-nss-clients/dtls/v2.0/nss_dtlsmgr_private.h
@@ -0,0 +1,185 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_dtlsmgr_private.h
+ */
+
+#ifndef __NSS_DTLSMGR_PRIVATE_H_
+#define __NSS_DTLSMGR_PRIVATE_H_
+
+#define NSS_DTLSMGR_DEBUG_LEVEL_ERROR 1
+#define NSS_DTLSMGR_DEBUG_LEVEL_WARN 2
+#define NSS_DTLSMGR_DEBUG_LEVEL_INFO 3
+#define NSS_DTLSMGR_DEBUG_LEVEL_TRACE 4
+
+#define nss_dtlsmgr_error(s, ...) do {	\
+	if (net_ratelimit()) {	\
+		pr_alert("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+} while (0)
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_dtlsmgr_warn(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__)
+#define nss_dtlsmgr_info(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__)
+#define nss_dtlsmgr_trace(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__)
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#define nss_dtlsmgr_warn(s, ...) {	\
+	if (NSS_DTLSMGR_DEBUG_LEVEL > NSS_DTLSMGR_DEBUG_LEVEL_ERROR)	\
+		pr_warn("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__)	\
+}
+
+#define nss_dtlsmgr_info(s, ...) {	\
+	if (NSS_DTLSMGR_DEBUG_LEVEL > NSS_DTLSMGR_DEBUG_LEVEL_WARN)	\
+		pr_notice("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__)	\
+}
+
+#define nss_dtlsmgr_trace(s, ...) {	\
+	if (NSS_DTLSMGR_DEBUG_LEVEL > NSS_DTLSMGR_DEBUG_LEVEL_INFO)	\
+		pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__)	\
+}
+
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+#define NSS_DTLSMGR_DTLS_HDR_SZ 13			/* DTLS header length */
+#define NSS_DTLSMGR_CAPWAP_DTLS_HDR_SZ 4		/* CAPWAP-DTLS header length */
+#define NSS_DTLSMGR_CTX_MAGIC 0x5d7eb219		/* DTLS context magic value */
+#define NSS_DTLSMGR_EDMA_PRE_HDR_SZ 32			/* EDMA preheader size */
+#define NSS_DTLSMGR_SGT_HDR_SZ 8			/* Security group header size */
+
+
+#if defined (NSS_DTLSMGR_DEBUG)
+#define NSS_DTLSMGR_VERIFY_MAGIC(ctx) do { \
+	struct nss_dtlsmgr_ctx *__ctx = (ctx);	\
+	BUG_ON(__ctx->magic != NSS_DTLSMGR_CTX_MAGIC);	\
+} while(0)
+
+#define NSS_DTLSMGR_SET_MAGIC(ctx, magic) do {	\
+	struct nss_dtlsmgr_ctx *__ctx = (ctx);	\
+	__ctx->magic = (magic);	\
+} while(0)
+#else
+#define NSS_DTLSMGR_VERIFY_MAGIC(ctx)
+#define NSS_DTLSMGR_SET_MAGIC(ctx, magic)
+#endif
+
+/*
+ * DTLS algorithm information
+ */
+struct nss_dtlsmgr_algo_info {
+	char *name;				/* Linux crypto algorithm string. */
+	uint32_t rta_key_size;			/* RTA key attribute size. */
+};
+
+/*
+ * DTLS flow information
+ */
+struct nss_dtlsmgr_flow_data {
+	uint32_t sip[4];			/* Source IPv4/v6 address. */
+	uint32_t dip[4];			/* Destination IPv4/v6 address. */
+	uint32_t flags;				/* Transformation flags. */
+
+	uint16_t sport;				/* Source UDP/UPDLite port. */
+	uint16_t dport;				/* Destination UDP/UDPLite port. */
+
+	uint8_t dscp;				/* Dscp value incase of static. */
+	uint8_t hop_limit_ttl;			/* Hop limit or time to live. */
+	bool dscp_copy;				/* Copy dscp. */
+	bool df;				/* Do not fragment settings. */
+};
+
+/*
+ * DTLS configuration data
+ */
+struct nss_dtlsmgr_dtls_data {
+	struct list_head list;			/* List of crypto data. */
+	struct crypto_aead *aead;		/* Linux AEAD context. */
+	uint32_t crypto_idx;
+	uint32_t ver;				/* DTLS version. */
+
+	uint16_t window_size;			/* DTLS anti-replay window. */
+	uint16_t epoch;				/* Current epoch. */
+
+	uint8_t blk_len;			/* Cipher block length. */
+	uint8_t hash_len;			/* Hash length. */
+	uint8_t iv_len;				/* IV length. */
+	uint8_t res1;
+};
+
+/*
+ * DTLS context data
+ */
+struct nss_dtlsmgr_ctx_data {
+	struct nss_dtlsmgr_stats stats;		/* Statistics. */
+	struct nss_dtlsmgr_flow_data flow;	/* Flow data information. */
+	struct nss_ctx_instance *nss_ctx;	/* NSS context handle. */
+	struct list_head dtls_active;		/* List of active DTLS record(s). */
+
+	uint32_t headroom;			/* Headroom needed. */
+	uint32_t tailroom;			/* Tailroom needed. */
+	uint32_t ifnum;				/* NSS interface number. */
+	uint32_t src_ifnum;			/* Source interface number for NSS. */
+	uint32_t dest_ifnum;			/* Destination interface number for NSS. */
+	uint32_t flags;				/* DTLS flags. */
+	uint32_t di_type;			/* Dynamic interface type. */
+};
+
+/*
+ * DTLS manager context
+ */
+struct nss_dtlsmgr_ctx {
+	rwlock_t lock;				/* Context lock. */
+	struct net_device *dev;			/* Session netdevice. */
+	struct dentry *dentry;			/* Debugfs directory for ctx statistics. */
+
+	struct nss_dtlsmgr_ctx_data encap;	/* Encapsulation data. */
+	struct nss_dtlsmgr_ctx_data decap;	/* Decapsulation data. */
+
+	void *app_data;				/* Opaque data for callback */
+	nss_dtlsmgr_notify_callback_t notify_cb;/* Statistics notification callback. */
+	nss_dtlsmgr_data_callback_t data_cb;	/* Data callback. */
+
+#if defined (NSS_DTLSMGR_DEBUG)
+	uint32_t magic;				/* Magic check. */
+#endif
+};
+
+/*
+ * DTLS manager data
+ */
+struct nss_dtlsmgr {
+	atomic_t is_configured;			/* Firmware is configured. */
+	struct dentry *root_dir;		/* Debugfs root directory. */
+	struct nss_ctx_instance *nss_ctx;	/* NSS data/message handle. */
+};
+
+extern struct nss_dtlsmgr g_dtls;
+
+extern void nss_dtlsmgr_ctx_dev_event_inner(void *if_ctx, struct nss_cmn_msg *ndcm);
+extern void nss_dtlsmgr_ctx_dev_event_outer(void *if_ctx, struct nss_cmn_msg *ndcm);
+extern void nss_dtlsmgr_ctx_dev_data_callback(void *app_data, struct sk_buff *skb);
+extern void nss_dtlsmgr_ctx_dev_rx_inner(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+extern void nss_dtlsmgr_ctx_dev_rx_outer(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+extern void nss_dtlsmgr_ctx_dev_setup(struct net_device *dev);
+extern int nss_dtlsmgr_create_debugfs(struct nss_dtlsmgr_ctx *ctx);
+#endif /* !__NSS_DTLSMGR_PRIVATE_H_ */
diff --git a/qca-nss-clients/eogremgr/Makefile b/qca-nss-clients/eogremgr/Makefile
new file mode 100644
index 0000000..cea37c9
--- /dev/null
+++ b/qca-nss-clients/eogremgr/Makefile
@@ -0,0 +1,6 @@
+# Makefile for eogre client
+ccflags-y := -I$(obj)/../exports -I$(obj)/.. \
+	-DNSS_CLIENT_BUILD_ID="$(BUILD_ID)" -DNSS_EOGREMGR_DEBUG_LEVEL=2 -Wall -Werror
+
+obj-m += qca-nss-eogremgr.o
+qca-nss-eogremgr-objs := nss_eogremgr.o
diff --git a/qca-nss-clients/eogremgr/nss_eogremgr.c b/qca-nss-clients/eogremgr/nss_eogremgr.c
new file mode 100644
index 0000000..4861f35
--- /dev/null
+++ b/qca-nss-clients/eogremgr/nss_eogremgr.c
@@ -0,0 +1,587 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_eogremgr.c
+ *	NSS EOGRE manager
+ */
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include "nss_connmgr_gre_public.h"
+#include <linux/of.h>
+#include "nss_eogremgr.h"
+#include "nss_eogremgr_priv.h"
+
+/*
+ * Mapping table from tunnel-id to rule/GRE netdev
+ */
+struct nss_eogremgr_tunnel {
+	union {
+		struct nss_ipv4_rule_create_msg v4;	/* IPv4 rule structure. */
+		struct nss_ipv6_rule_create_msg v6;	/* IPv6 rule structure. */
+	} ip_rule;
+
+	bool is_ipv4;			/* Set when tunnel is ipv4. */
+	struct net_device *gre_dev;	/* Store the gre netdev associated with the tunnel. */
+};
+
+struct nss_eogremgr_tunnel *tunnels[NSS_EOGREMGR_MAX_TUNNELS] = {NULL};
+
+/*
+ * nss_eogremgr_get_if_num_inner()
+ * 	Get the GRE inner interface number associated with the tunnel.
+ */
+int nss_eogremgr_get_if_num_inner(uint32_t tunnel_id)
+{
+	int inner_ifnum;
+
+	/*
+	 * Check if the tunnel exists.
+	 */
+	if (!tunnels[tunnel_id]) {
+		nss_eogremgr_warn("Could not find tunnel data, for tunnel id : %d\n", tunnel_id);
+		return -1;
+	}
+
+	/*
+	 * Find inner ifnum for the GRE netdev.
+	 */
+	inner_ifnum = nss_cmn_get_interface_number_by_dev_and_type(
+			tunnels[tunnel_id]->gre_dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER);
+	if (inner_ifnum < 0) {
+		nss_eogremgr_warn("No GRE inner interface registered for tunnel id : %d\n", tunnel_id);
+		return -1;
+	}
+
+	/*
+	 * Append the core-id to the ifnum.
+	 */
+	return nss_gre_ifnum_with_core_id(inner_ifnum);
+}
+EXPORT_SYMBOL(nss_eogremgr_get_if_num_inner);
+
+/*
+ * nss_eogremgr_tunnel_disable()
+ * 	Function to disable eogre tunnel.
+ */
+nss_eogremgr_status_t nss_eogremgr_tunnel_disable(uint32_t tunnel_id)
+{
+	int ret;
+
+	/*
+	 * Check if the tunnel exists.
+	 */
+	if (!tunnels[tunnel_id]) {
+		nss_eogremgr_warn("Could not find tunnel data for tunnel id : %d\n", tunnel_id);
+		return NSS_EOGRE_ERR_NETDEV_DISABLE_FAILED;
+	}
+
+	/*
+	 * Notify GRE client to disable GRE tunnel.
+	 */
+	ret = nss_connmgr_gre_dev_close(tunnels[tunnel_id]->gre_dev);
+	if (ret != 0) {
+		nss_eogremgr_warn("%s: Unable to disable tunnel:%d\n\n",
+				tunnels[tunnel_id]->gre_dev->name, tunnel_id);
+		return NSS_EOGRE_ERR_NETDEV_DISABLE_FAILED;
+	}
+
+	return NSS_EOGRE_SUCCESS;
+}
+EXPORT_SYMBOL(nss_eogremgr_tunnel_disable);
+
+/*
+ * nss_eogremgr_tunnel_enable()
+ * 	Function to enable eogre tunnel.
+ */
+nss_eogremgr_status_t nss_eogremgr_tunnel_enable(uint32_t tunnel_id)
+{
+	int ret;
+
+	/*
+	 * Check if the tunnel exists.
+	 */
+	if (!tunnels[tunnel_id]) {
+		nss_eogremgr_warn("Could not find tunnel data for tunnel id : %d\n", tunnel_id);
+		return NSS_EOGRE_ERR_NETDEV_ENABLE_FAILED;
+	}
+
+	/*
+	 * Notify GRE client to enable GRE tunnel.
+	 */
+	ret = nss_connmgr_gre_dev_open(tunnels[tunnel_id]->gre_dev);
+	if (ret != 0) {
+		nss_eogremgr_warn("%s: Unable to enable tunnel:%d\n",
+				tunnels[tunnel_id]->gre_dev->name, tunnel_id);
+		return NSS_EOGRE_ERR_NETDEV_ENABLE_FAILED;
+	}
+
+	return NSS_EOGRE_SUCCESS;
+}
+EXPORT_SYMBOL(nss_eogremgr_tunnel_enable);
+
+/*
+ * nss_eogremgr_tunnel_destroy_ipv6_rule()
+ * 	Destroy a given IPv6 connection in the NSS
+ */
+static nss_tx_status_t nss_eogremgr_tunnel_destroy_ipv6_rule(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_5tuple *ni5t)
+{
+	struct nss_ipv6_msg nim;
+	nss_tx_status_t status;
+
+	nss_eogremgr_info("%px: ctx: Destroy IPv6: %pI6:%u, %pI6:%u, p: %d\n", nss_ctx,
+			&ni5t->flow_ip, ni5t->flow_ident, &ni5t->return_ip, ni5t->return_ident, ni5t->protocol);
+
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_DESTROY_RULE_MSG,
+			sizeof(struct nss_ipv6_rule_destroy_msg), NULL, NULL);
+
+	nim.msg.rule_destroy.tuple = *ni5t;
+	status = nss_ipv6_tx_sync(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_eogremgr_warn("%px: Destroy IPv6 message failed %d\n", nss_ctx, status);
+	}
+
+	return status;
+}
+
+/*
+ * nss_eogremgr_tunnel_destroy_ipv4_rule()
+ * 	Destroy a given IPv4 connection in the NSS
+ */
+static nss_tx_status_t nss_eogremgr_tunnel_destroy_ipv4_rule(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_5tuple *ni5t)
+{
+	struct nss_ipv4_msg nim;
+	nss_tx_status_t status;
+
+	nss_eogremgr_info("%px: ctx: Destroy IPv4: %pI4h :%u, %pI4h :%u, p: %d\n", nss_ctx,
+			&ni5t->flow_ip, ni5t->flow_ident, &ni5t->return_ip, ni5t->return_ident, ni5t->protocol);
+
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_DESTROY_RULE_MSG,
+			sizeof(struct nss_ipv4_rule_destroy_msg), NULL, NULL);
+
+	nim.msg.rule_destroy.tuple = *ni5t;
+	status = nss_ipv4_tx_sync(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_eogremgr_warn("%px: Destroy IPv4 message failed %d\n", nss_ctx, status);
+	}
+
+	return status;
+}
+
+/*
+ * nss_eogremgr_tunnel_create_ipv6_rule()
+ * 	Create a given IPv6 connection in the NSS
+ */
+static nss_tx_status_t nss_eogremgr_tunnel_create_ipv6_rule(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_rule_create_msg *nircm)
+{
+	struct nss_ipv6_msg nim;
+	nss_tx_status_t status;
+
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_CREATE_RULE_MSG,
+			sizeof(struct nss_ipv6_rule_create_msg), NULL, NULL);
+
+	nim.msg.rule_create = *nircm;
+	status = nss_ipv6_tx_sync(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_eogremgr_warn("%px: Create IPv6 message failed %d\n", nss_ctx, status);
+	}
+
+	return status;
+}
+
+/*
+ * nss_eogremgr_tunnel_create_ipv4_rule()
+ * 	Create a given IPv4 connection in the NSS
+ */
+static nss_tx_status_t nss_eogremgr_tunnel_create_ipv4_rule(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_rule_create_msg *nircm)
+{
+	struct nss_ipv4_msg nim;
+	nss_tx_status_t status;
+
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_CREATE_RULE_MSG,
+			sizeof(struct nss_ipv4_rule_create_msg), NULL, NULL);
+
+	nim.msg.rule_create = *nircm;
+	status = nss_ipv4_tx_sync(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_eogremgr_warn("%px: Create IPv4 message failed %d\n", nss_ctx, status);
+	}
+
+	return status;
+}
+
+/*
+ * nss_eogremgr_tunnel_destroy()
+ * 	Destroy the EoGRE tunnel.
+ */
+nss_eogremgr_status_t nss_eogremgr_tunnel_destroy(uint32_t tunnel_id)
+{
+	struct nss_ctx_instance *nss_ctx_v4, *nss_ctx_v6;
+	nss_tx_status_t status;
+	enum nss_connmgr_gre_err_codes err_code_gre;
+
+	/*
+	 * Check if tunnel_id is in range.
+	 */
+	if (tunnel_id >= NSS_EOGREMGR_MAX_TUNNELS) {
+		nss_eogremgr_warn("Invalid param tunnel_id: %d max: %d\n",
+				tunnel_id, NSS_EOGREMGR_MAX_TUNNELS);
+		return NSS_EOGRE_ERR_INVALID_TUNNEL_ID;
+	}
+
+	/*
+	 * Check if the tunnel_id exists.
+	 */
+	if (!tunnels[tunnel_id]) {
+		nss_eogremgr_warn("Could not find tunnel data for tunnel id : %d\n", tunnel_id);
+		return NSS_EOGRE_ERR_INVALID_TUNNEL_ID;
+	}
+
+	/*
+	 * Destroy IPv4/IPv6 rule
+	 */
+	if (tunnels[tunnel_id]->is_ipv4) {
+		nss_ctx_v4 = nss_ipv4_get_mgr();
+		if (!nss_ctx_v4) {
+			nss_eogremgr_warn("Tunnel: %d: could not get IPv4 ctx\n", tunnel_id);
+			return NSS_EOGRE_ERR_BAD_NSS_CTX;
+		}
+		status = nss_eogremgr_tunnel_destroy_ipv4_rule(nss_ctx_v4, &tunnels[tunnel_id]->ip_rule.v4.tuple);
+	} else {
+		nss_ctx_v6 = nss_ipv6_get_mgr();
+		if (!nss_ctx_v6) {
+			nss_eogremgr_warn("Tunnel: %d: could not get IPv6 ctx\n", tunnel_id);
+			return NSS_EOGRE_ERR_BAD_NSS_CTX;
+		}
+		status = nss_eogremgr_tunnel_destroy_ipv6_rule(nss_ctx_v6, &tunnels[tunnel_id]->ip_rule.v6.tuple);
+	}
+
+	if (status != NSS_TX_SUCCESS) {
+		nss_eogremgr_warn("Destroy IP rule failed for tunnel: %d\n", tunnel_id);
+		return NSS_EOGRE_ERR_DESTROY_IP_RULE_FAILED;
+	}
+
+	/*
+	 * Destroy GRE tunnel
+	 */
+	err_code_gre = nss_connmgr_gre_destroy_interface(tunnels[tunnel_id]->gre_dev);
+	if (err_code_gre != GRE_SUCCESS) {
+		nss_eogremgr_warn("Could not destroy GRE interface: %d, err=%d\n", tunnel_id, err_code_gre);
+
+		/*
+		 * Add the ipv4/upv6 rule back, since tunnel is not destroyed.
+		 */
+		if (tunnels[tunnel_id]->is_ipv4) {
+			status = nss_eogremgr_tunnel_create_ipv4_rule(
+					nss_ctx_v4, &tunnels[tunnel_id]->ip_rule.v4);
+		} else {
+			status = nss_eogremgr_tunnel_create_ipv6_rule(
+					nss_ctx_v6, &tunnels[tunnel_id]->ip_rule.v6);
+		}
+
+		if (status != NSS_TX_SUCCESS) {
+			nss_eogremgr_warn("IPv4/IPv6 rule create from nss_eogremgr_tunnel_destroy() failed with status: %d\n",
+					status);
+			return NSS_EOGRE_ERR_CREATE_IP_RULE_FAILED;
+		}
+
+		return NSS_EOGRE_TUNNEL_DESTROY_FAILED;
+	}
+
+	nss_eogremgr_info("Tunnel: %d is destroyed\n", tunnel_id);
+	kfree(tunnels[tunnel_id]);
+	tunnels[tunnel_id] = NULL;
+	return NSS_EOGRE_SUCCESS;
+}
+EXPORT_SYMBOL(nss_eogremgr_tunnel_destroy);
+
+/*
+ * nss_eogremgr_tunnel_ipv6_create()
+ * 	API to create EoGRE IPv6 tunnel and Push IPv6 rule to NSS.
+ */
+nss_eogremgr_status_t nss_eogremgr_tunnel_ipv6_create(struct nss_connmgr_gre_cfg *cfg,
+	       	struct nss_ipv6_rule_create_msg *nircm, uint32_t tunnel_id)
+{
+	struct net_device *gre_dev;
+	struct nss_ctx_instance *nss_ctx;
+	enum nss_connmgr_gre_err_codes err_code_gre;
+	nss_tx_status_t status;
+	int gre_outer_ifnum;
+
+	/*
+	 * Check if tunnel_id is in range.
+	 */
+	if (tunnel_id >= NSS_EOGREMGR_MAX_TUNNELS) {
+		nss_eogremgr_warn("Invalid tunnel_id: %d max: %d\n",
+				tunnel_id, NSS_EOGREMGR_MAX_TUNNELS);
+		return NSS_EOGRE_ERR_INVALID_TUNNEL_ID;
+	}
+
+	/*
+	 * Check if tunnel_id is already in use.
+	 */
+	if (tunnels[tunnel_id]) {
+		nss_eogremgr_warn("Tunnel already exist for this tunnel_id = %d, netdev = %s\n",
+				tunnel_id, tunnels[tunnel_id]->gre_dev->name);
+		return NSS_EOGRE_ERR_TUNNEL_ID_EXIST;
+	}
+
+	/*
+	 * GRE API to create GRE standard interface
+	 */
+	gre_dev = nss_connmgr_gre_create_interface(cfg, &err_code_gre);
+	if (!gre_dev) {
+		nss_eogremgr_warn("Could not create GRE interface, err=%d\n", err_code_gre);
+		return NSS_EOGRE_ERR_GRE_CREATE_FAILED;
+	}
+
+	nss_eogremgr_info("GRE interface %s created with tunnel_id: %u\n", gre_dev->name, tunnel_id);
+
+	gre_outer_ifnum = nss_cmn_get_interface_number_by_dev_and_type(
+			                        gre_dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER);
+	if (gre_outer_ifnum < 0) {
+		nss_eogremgr_warn("No GRE outer interface registered for gre netdev: %s\n", gre_dev->name);
+		nss_connmgr_gre_destroy_interface(gre_dev);
+		return NSS_EOGRE_ERR_INVALID_GRE_IFNUM;
+	}
+
+	nss_ctx = nss_ipv6_get_mgr();
+	if (!nss_ctx) {
+		nss_eogremgr_warn("Tunnel: %d could not get IPv6 ctx\n", tunnel_id);
+		nss_connmgr_gre_destroy_interface(gre_dev);
+		return NSS_EOGRE_ERR_BAD_NSS_CTX;
+	}
+
+	/*
+	 * Configure ifnum for GRE decap node before adding IPv6 rule.
+	 */
+	nircm->conn_rule.flow_interface_num = gre_outer_ifnum;
+
+	/*
+	 * Fill the flow/return ident with 32 bit key, to create a 5-tuple match for GRE with key
+	 */
+	if (cfg->okey_valid) {
+		nircm->tuple.flow_ident = cfg->okey;
+		nircm->tuple.return_ident = cfg->okey;
+	}
+
+	/*
+	 * Push IPv6 rule to NSS
+	 */
+	status = nss_eogremgr_tunnel_create_ipv6_rule(nss_ctx, nircm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_eogremgr_warn("IPv6 rule create failed with status: %d\n", status);
+		nss_connmgr_gre_destroy_interface(gre_dev);
+		return NSS_EOGRE_ERR_CREATE_IP_RULE_FAILED;
+	}
+
+	nss_eogremgr_info("EoGRE Tunnel create done tunnel_id:%d IPv6: %pI6h :%u, %pI6h :%u, p: %d\n",
+			tunnel_id, &nircm->tuple.flow_ip, nircm->tuple.flow_ident, &nircm->tuple.return_ip,
+			nircm->tuple.return_ident, nircm->tuple.protocol);
+
+	/*
+	 * Add EoGRE tunnel entry
+	 */
+	tunnels[tunnel_id] = kzalloc(sizeof(struct nss_eogremgr_tunnel), GFP_ATOMIC);
+	if(!tunnels[tunnel_id]) {
+		nss_eogremgr_warn("Failed to allocate tunnel memory for tunnel_id : %d\n", tunnel_id);
+		nss_eogremgr_tunnel_destroy_ipv6_rule(nss_ctx, &nircm->tuple);
+		nss_connmgr_gre_destroy_interface(gre_dev);
+		return NSS_EOGRE_ERR_ALLOC_TUNNEL_FAILED;
+	}
+
+	memcpy(&tunnels[tunnel_id]->ip_rule.v6, nircm, sizeof(struct nss_ipv6_rule_create_msg));
+	tunnels[tunnel_id]->is_ipv4 = false;
+	tunnels[tunnel_id]->gre_dev = gre_dev;
+
+	return NSS_EOGRE_SUCCESS;
+}
+EXPORT_SYMBOL(nss_eogremgr_tunnel_ipv6_create);
+
+/*
+ * nss_eogremgr_tunnel_ipv4_create()
+ * 	API to create EoGRE IPv4 tunnel and push IPv4 rule to NSS.
+ */
+nss_eogremgr_status_t nss_eogremgr_tunnel_ipv4_create(struct nss_connmgr_gre_cfg *cfg,
+	       	struct nss_ipv4_rule_create_msg *nircm, uint32_t tunnel_id)
+{
+	struct net_device *gre_dev;
+	struct nss_ctx_instance *nss_ctx;
+	int gre_outer_ifnum;
+	nss_tx_status_t status;
+	enum nss_connmgr_gre_err_codes err_code_gre;
+
+	/*
+	 * Check if tunnel_id is in range.
+	 */
+	if (tunnel_id >= NSS_EOGREMGR_MAX_TUNNELS) {
+		nss_eogremgr_warn("Invalid param tunnel_id: %d max: %d\n", tunnel_id, NSS_EOGREMGR_MAX_TUNNELS);
+		return NSS_EOGRE_ERR_INVALID_TUNNEL_ID;
+	}
+
+	/*
+	 * Check if tunnel_id is already in use.
+	 */
+	if (tunnels[tunnel_id]) {
+		nss_eogremgr_warn("Tunnel already exist for this tunnel_id = %d, netdev = %s\n",
+				tunnel_id, tunnels[tunnel_id]->gre_dev->name);
+		return NSS_EOGRE_ERR_TUNNEL_ID_EXIST;
+	}
+
+	/*
+	 * Create GRE standard interface
+	 */
+	gre_dev = nss_connmgr_gre_create_interface(cfg, &err_code_gre);
+	if (!gre_dev) {
+		nss_eogremgr_warn("Could not create GRE interface, err=%d\n", err_code_gre);
+		return NSS_EOGRE_ERR_GRE_CREATE_FAILED;
+	}
+
+	nss_eogremgr_info("GRE interface %s created with tunnel_id: %u\n", gre_dev->name, tunnel_id);
+
+	gre_outer_ifnum = nss_cmn_get_interface_number_by_dev_and_type(
+			gre_dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER);
+	if (gre_outer_ifnum < 0) {
+		nss_eogremgr_warn("No GRE outer interface registered for gre netdev: %s\n", gre_dev->name);
+		nss_connmgr_gre_destroy_interface(gre_dev);
+		return NSS_EOGRE_ERR_INVALID_GRE_IFNUM;
+	}
+
+	nss_ctx = nss_ipv4_get_mgr();
+	if (!nss_ctx) {
+		nss_eogremgr_warn("EoGRE couldn't get IPv4 ctx\n");
+		nss_connmgr_gre_destroy_interface(gre_dev);
+		return NSS_EOGRE_ERR_BAD_NSS_CTX;
+	}
+
+	/*
+	 * Configure ifnum for GRE decap node before adding IPv4 rule.
+	 */
+	nircm->conn_rule.flow_interface_num = gre_outer_ifnum;
+
+	/*
+	 * Fill the flow/return ident with 32 bit key, to create a 5-tuple match for GRE with key
+	 */
+	if (cfg->okey_valid) {
+		nircm->tuple.flow_ident = cfg->okey;
+		nircm->tuple.return_ident = cfg->okey;
+		nircm->conn_rule.flow_ident_xlate = cfg->okey;
+		nircm->conn_rule.return_ident_xlate = cfg->okey;
+	}
+
+	/*
+	 * Push IPv4 rule to NSS.
+	 */
+	status = nss_eogremgr_tunnel_create_ipv4_rule(nss_ctx, nircm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_eogremgr_warn("IPv4 rule create failed with status: %d\n", status);
+		nss_connmgr_gre_destroy_interface(gre_dev);
+		return NSS_EOGRE_ERR_CREATE_IP_RULE_FAILED;
+	}
+
+	nss_eogremgr_info("EoGRE Tunnel create done tunnel_id:%d IPv4: %pI4h :%u, %pI4h :%u, p: %d\n",
+			tunnel_id, &nircm->tuple.flow_ip, nircm->tuple.flow_ident, &nircm->tuple.return_ip,
+			nircm->tuple.return_ident, nircm->tuple.protocol);
+
+	/*
+	 * Add EoGRE tunnel entry
+	 */
+	tunnels[tunnel_id] = kzalloc(sizeof(struct nss_eogremgr_tunnel), GFP_ATOMIC);
+	if (!tunnels[tunnel_id]) {
+		nss_eogremgr_warn("Failed to allocate tunnel memory for tunnel_id : %d\n", tunnel_id);
+		nss_eogremgr_tunnel_destroy_ipv4_rule(nss_ctx, &nircm->tuple);
+		nss_connmgr_gre_destroy_interface(gre_dev);
+		return NSS_EOGRE_ERR_ALLOC_TUNNEL_FAILED;
+	}
+
+	memcpy(&tunnels[tunnel_id]->ip_rule.v4, nircm, sizeof(struct nss_ipv4_rule_create_msg));
+	tunnels[tunnel_id]->is_ipv4 = true;
+	tunnels[tunnel_id]->gre_dev = gre_dev;
+
+	return NSS_EOGRE_SUCCESS;
+}
+EXPORT_SYMBOL(nss_eogremgr_tunnel_ipv4_create);
+
+/*
+ * nss_eogremgr_destroy_tunnel_data()
+ * 	Destroy EoGRE global tunnel structure
+ */
+static int nss_eogremgr_destroy_tunnel_data(void)
+{
+	int tunnel_id, status, fail_count = 0;
+
+	for (tunnel_id = 0; tunnel_id < NSS_EOGREMGR_MAX_TUNNELS; tunnel_id++) {
+		if (!tunnels[tunnel_id]) {
+			continue;
+		}
+
+		status = nss_eogremgr_tunnel_destroy(tunnel_id);
+		if (!status) {
+			nss_eogremgr_warn("Unable to delete GRE netdev and IPv4/IPv6 rule for tunnel_id: %u\n", tunnel_id);
+			fail_count++;
+		}
+	}
+
+	return fail_count;
+}
+
+/*
+ * nss_eogremgr_exit_module()
+ * 	Tunnel EoGRE module exit function
+ */
+static void __exit nss_eogremgr_exit_module(void)
+{
+	int status;
+
+	/*
+	 * Destroy tunnel data
+	 */
+	status = nss_eogremgr_destroy_tunnel_data();
+	if (status) {
+		nss_eogremgr_info("Error in module unloading, Unable to delete %d tunnels \n", status);
+		return;
+	}
+
+	nss_eogremgr_info("module unloaded\n");
+}
+
+/*
+ * nss_eogremgr_init_module()
+ * 	Tunnel EoGRE module init function
+ */
+static int __init nss_eogremgr_init_module(void)
+{
+
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+
+	nss_eogremgr_info("module %s loaded\n", NSS_CLIENT_BUILD_ID);
+
+	return 0;
+
+}
+module_init(nss_eogremgr_init_module);
+module_exit(nss_eogremgr_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS EOGRE manager");
diff --git a/qca-nss-clients/eogremgr/nss_eogremgr_priv.h b/qca-nss-clients/eogremgr/nss_eogremgr_priv.h
new file mode 100644
index 0000000..c9824ec
--- /dev/null
+++ b/qca-nss-clients/eogremgr/nss_eogremgr_priv.h
@@ -0,0 +1,63 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_eogremgr_priv.h
+ *	EoGRE manager private defines
+ */
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <nss_api_if.h>
+#include <linux/in.h>
+#include <linux/etherdevice.h>
+#include <nss_cmn.h>
+
+#if (NSS_EOGREMGR_DEBUG_LEVEL < 1)
+#define nss_eogremgr_assert(fmt, args...)
+#else
+#define nss_eogremgr_assert(c) if (!(c)) { BUG_ON(!(c)); }
+#endif /* NSS_EOGREMGR_DEBUG_LEVEL */
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_eogremgr_warn(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_eogremgr_info(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_eogremgr_trace(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#else /* CONFIG_DYNAMIC_DEBUG */
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_EOGREMGR_DEBUG_LEVEL < 2)
+#define nss_eogremgr_warn(s, ...)
+#else
+#define nss_eogremgr_warn(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_EOGREMGR_DEBUG_LEVEL < 3)
+#define nss_eogremgr_info(s, ...)
+#else
+#define nss_eogremgr_info(s, ...)   pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_EOGREMGR_DEBUG_LEVEL < 4)
+#define nss_eogremgr_trace(s, ...)
+#else
+#define nss_eogremgr_trace(s, ...)  pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif /* CONFIG_DYNAMIC_DEBUG */
diff --git a/qca-nss-clients/exports/nss_capwap_user.h b/qca-nss-clients/exports/nss_capwap_user.h
new file mode 100644
index 0000000..ba4a684
--- /dev/null
+++ b/qca-nss-clients/exports/nss_capwap_user.h
@@ -0,0 +1,115 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_capwap_user.h
+ *	NSS CAPWAP definitions for kernel and user space
+ */
+
+#ifndef __NSS_CAPWAP_USER_H
+#define __NSS_CAPWAP_USER_H
+
+/**
+ * Maxmimum values for rule configuration parameters
+ */
+#define NSS_CAPWAP_MAX_MTU			9000
+				/**< maximum MTU supported by NSS FW */
+#define NSS_CAPWAP_MAX_BUFFER_SIZE		9000
+				/**< maximum buffer-size supported by NSS FW */
+#define NSS_CAPWAP_MAX_FRAGMENTS		10
+				/**< maximum fragments for reassembly */
+#define NSS_CAPWAP_MAX_REASSEMBLY_TIMEOUT	(10 * 1000)
+				/**< maximum timeout for reassembly - 10 seconds */
+
+/**
+ * CAPWAP Rule configure message flags
+ */
+#define NSS_CAPWAP_TUNNEL_IPV4		2
+				/**< IPv4 tunnel */
+#define NSS_CAPWAP_TUNNEL_IPV6		3
+				/**< IPv6 tunnel */
+#define NSS_CAPWAP_TUNNEL_UDP		4
+				/**< UDP tunnel */
+#define NSS_CAPWAP_TUNNEL_UDPLite	5
+				/**< UDPLite tunnel */
+
+/**
+ * CAPWAP tunnel create and type flags. These flags are used
+ * to determine packet header size during encapsulation.
+ */
+#define NSS_CAPWAP_RULE_CREATE_VLAN_CONFIGURED	0x1
+				/**< VLAN Configured for CAPWAP tunnel */
+#define NSS_CAPWAP_RULE_CREATE_PPPOE_CONFIGURED	0x2
+				/**< PPPoE configured for CAPWAP tunnel */
+#define NSS_CAPWAP_ENCAP_UDPLITE_HDR_CSUM	0x4
+				/**< Generate only UDP-Lite header checksum. Otherwise whole UDP-Lite payload */
+
+/**
+ * CAPWAP version
+ */
+#define NSS_CAPWAP_VERSION_V1		0x1
+				/**< RFC CAPWAP version */
+#define NSS_CAPWAP_VERSION_V2		0x2
+				/**< Initial CAPWAP version for a customer */
+
+/**
+ * Type of packet. These are mutually exclusive fields.
+ */
+#define NSS_CAPWAP_PKT_TYPE_UNKNOWN	0x0000
+				/**< Don't know the type of CAPWAP packet */
+#define NSS_CAPWAP_PKT_TYPE_CONTROL	0x0001
+				/** It's a control CAPWAP packet src_port=5247 */
+#define NSS_CAPWAP_PKT_TYPE_DATA	0x0002
+				/**< It's a data CAPWAP packet src_port=5246 */
+
+/**
+ * Addtional fields for identifying what's there in the packet.
+ */
+#define NSS_CAPWAP_PKT_TYPE_DTLS_ENABLED	0x0004
+				/**< It's a DTLS packet. */
+#define NSS_CAPWAP_PKT_TYPE_WIRELESS_INFO	0x0008
+				/**< W=1, wireless info present */
+#define NSS_CAPWAP_PKT_TYPE_802_11		0x0010
+				/**< T=1, then set wbid=1 */
+#define NSS_CAPWAP_PKT_TYPE_802_3		0x0020
+				/**< Data is in 802.3 format */
+
+/**
+ * CAPWAP metaheader per-packet for both encap (TX) and decap (RX).
+ */
+struct nss_capwap_metaheader {
+	uint8_t version;	/**< CAPWAP version */
+	uint8_t rid;		/**< Radio ID */
+	uint16_t tunnel_id;	/**< Tunnel-ID */
+	uint8_t dscp;		/**< DSCP value */
+	uint8_t vlan_pcp;	/**< VLAN priority .P marking */
+	uint16_t type;		/**< Type of CAPWAP packet & What was there in CAPWAP header */
+	uint16_t nwireless;	/**< Number of wireless info sections in CAPWAP header */
+	uint16_t wireless_qos;	/**< 802.11e qos info */
+	uint16_t outer_sgt;	/**< Security Group Tag value in the TrustSec header */
+	uint16_t inner_sgt;	/**< Security Group Tag value in the TrustSec header */
+	uint32_t flow_id;	/**< Flow identification */
+	uint16_t vapid;		/**< VAP ID info */
+
+	uint16_t magic;		/**< Magic for verification purpose. Use only for debugging */
+
+	/*
+	 * Put the wl_info at last so we don't have to do copy if 802.11 to 802.3 conversion did not happen.
+	 */
+	uint8_t wl_info[8];	/* Wireless info preserved from the original packet */
+} __packed __aligned(4);
+
+#endif /* __NSS_CAPWAP_USER_H */
diff --git a/qca-nss-clients/exports/nss_capwapmgr.h b/qca-nss-clients/exports/nss_capwapmgr.h
new file mode 100644
index 0000000..5833d35
--- /dev/null
+++ b/qca-nss-clients/exports/nss_capwapmgr.h
@@ -0,0 +1,413 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_capwapmgr.h
+ *	CAPWAP manager for NSS
+ */
+#ifndef __NSS_CAPWAPMGR_H
+#define __NSS_CAPWAPMGR_H
+
+#include <nss_dtlsmgr.h>
+
+/*
+ * Maximum number of tunnels currently supported
+ */
+#define NSS_CAPWAPMGR_MAX_TUNNELS		32
+
+#define NSS_CAPWAPMGR_TUNNEL_STATE_CONFIGURED		0x1
+					/**< Bit is set if tunnel has been configured */
+#define NSS_CAPWAPMGR_TUNNEL_STATE_ENABLED		0x2
+					/**< Bit is set if tunnel has been enabled */
+#define NSS_CAPWAPMGR_TUNNEL_STATE_IPRULE_CONFIGURED	0x4
+					/**< Bit is set if tunnel IP rule exist */
+
+/*
+ * Tunnel feature flags
+ */
+#define NSS_CAPWAPMGR_FEATURE_DTLS_ENABLED		0x00000001	/* Tunnel enabled DTLS. */
+#define NSS_CAPWAPMGR_FEATURE_INNER_TRUSTSEC_ENABLED	0x00000002	/* Tunnel enabled inner trustsec. */
+#define NSS_CAPWAPMGR_FEATURE_OUTER_TRUSTSEC_ENABLED	0x00000004	/* Tunnel enabled outer trustsec. */
+#define NSS_CAPWAPMGR_FEATURE_WIRELESS_QOS_ENABLED	0x00000008	/* Tunnel enabled wireless QoS. */
+
+/*
+ * All CAPWAP messages to NSS FW are sync in nature. It means we have
+ * to wait for ACK/NACK from NSS FW before proceeding further.
+ * Keep a NSS FW response table to wakeup sync message caller.
+ */
+struct nss_capwapmgr_response {
+	struct semaphore sem;
+	wait_queue_head_t wq;
+	enum nss_cmn_response response;
+	nss_capwap_msg_response_t error;
+	atomic_t seq;
+};
+
+/**
+ * Mapping table from tunnel-id to if_num and rule.
+ */
+struct nss_capwapmgr_tunnel {
+	struct net_device *dtls_dev;		/**< DTLS netdevice */
+	uint32_t if_num_inner;			/**< Interface number of the INNER CAPWAP node */
+	uint32_t if_num_outer;			/**< Interface number of the OUTER CAPWAP node */
+	uint32_t tunnel_state;			/**< Tunnel state */
+	uint16_t type_flags;            /**< Tunnel Type to determine header size */
+	union {
+		struct nss_ipv4_create v4;	/**< IPv4 rule structure */
+		struct nss_ipv6_create v6;	/**< IPv6 rule struture */
+	} ip_rule;
+	struct nss_capwap_rule_msg capwap_rule;	/**< Copy of CAPWAP rule */
+};
+
+/**
+ * Private structure to store information needed by a nss_capwap net_device
+ */
+struct nss_capwapmgr_priv {
+	struct nss_ctx_instance *nss_ctx;	/**< Pointer to NSS context */
+	struct nss_capwapmgr_tunnel *tunnel;	/**< Pointer to tunnel data */
+	uint8_t *if_num_to_tunnel_id;		/**< Mapping table from if_num to tunnel_id. */
+	struct nss_capwapmgr_response *resp;	/**< Response housekeeping */
+};
+
+/**
+ * CAPWAP status enums
+ */
+typedef enum {
+	/*
+	 * nss_tx_status_t enums
+	 */
+	NSS_CAPWAPMGR_SUCCESS = NSS_TX_SUCCESS,
+	NSS_CAPWAPMGR_FAILURE = NSS_TX_FAILURE,
+	NSS_CAPWAPMGR_FAILURE_QUEUE = NSS_TX_FAILURE_QUEUE,
+	NSS_CAPWAPMGR_FAILURE_NOT_READY = NSS_TX_FAILURE_NOT_READY,
+	NSS_CAPWAPMGR_FAILURE_TOO_LARGE = NSS_TX_FAILURE_TOO_LARGE,
+	NSS_CAPWAPMGR_FAILURE_TOO_SHORT = NSS_TX_FAILURE_TOO_SHORT,
+	NSS_CAPWAPMGR_FAILURE_NOT_SUPPORTED = NSS_TX_FAILURE_NOT_SUPPORTED,
+	NSS_CAPWAPMGR_FAILURE_BAD_PARAM = NSS_TX_FAILURE_BAD_PARAM,
+
+	/*
+	 * CAPWAP specific ones.
+	 */
+	NSS_CAPWAPMGR_FAILURE_TUNNEL_ENABLED = 100,	/**< Tunnel is enabled */
+	NSS_CAPWAPMGR_FAILURE_TUNNEL_DISABLED,		/**< Tunnel is disabled */
+	NSS_CAPWAPMGR_FAILURE_TUNNEL_NOT_CFG,		/**< Tunnel is not configured yet */
+	NSS_CAPWAPMGR_FAILURE_TUNNEL_EXISTS,		/**< Tunnel already exisits */
+	NSS_CAPWAPMGR_FAILURE_DI_ALLOC_FAILED,		/**< Dynamic interface alloc failed */
+	NSS_CAPWAPMGR_FAILURE_CAPWAP_RULE,		/**< Failed to create CAPWAP rule */
+	NSS_CAPWAPMGR_FAILURE_IP_RULE,			/**< Failed to create IP rule */
+	NSS_CAPWAPMGR_FAILURE_REGISTER_NSS,		/**< Failed to register with NSS */
+	NSS_CAPWAPMGR_FAILURE_CMD_TIMEOUT,		/**< NSS Driver Command timed-out */
+	NSS_CAPWAPMGR_FAILURE_INVALID_REASSEMBLY_TIMEOUT,/**< Invalid reasm timeout */
+	NSS_CAPWAPMGR_FAILURE_INVALID_PATH_MTU,		/**< Invalid path mtu */
+	NSS_CAPWAPMGR_FAILURE_INVALID_MAX_FRAGMENT,	/**< Invalid max fragment */
+	NSS_CAPWAPMGR_FAILURE_INVALID_BUFFER_SIZE,	/**< Invalid buffer size */
+	NSS_CAPWAPMGR_FAILURE_INVALID_L3_PROTO,		/**< Invalid Layer3 protocol */
+	NSS_CAPWAPMGR_FAILURE_INVALID_UDP_PROTO,	/**< Invalid UDP protocol */
+	NSS_CAPWAPMGR_FAILURE_INVALID_VERSION,		/**< Invalid capwap version */
+	NSS_CAPWAPMGR_FAILURE_IP_DESTROY_RULE,		/**< Destroy IP rule failed */
+	NSS_CAPWAPMGR_FAILURE_CAPWAP_DESTROY_RULE,	/**< Destroy capwap rule failed */
+	NSS_CAPWAPMGR_FAILURE_INVALID_IP_NODE,		/**< Invalid tunnel IP node */
+	NSS_CAPWAPMGR_FAILURE_INVALID_TYPE_FLAG,	/**< Invalid type */
+	NSS_CAPWAPMGR_FAILURE_INVALID_DTLS_CFG,		/**< Invalid DTLS configuration */
+	NSS_CAPWAPMGR_FAILURE_CONFIGURE_TRUSTSEC_TX,	/**< Failed to configure trustsectx */
+	NSS_CAPWAPMGR_FAILURE_UNCONFIGURE_TRUSTSEC_TX,	/**< Failed to unconfigure trustsectx */
+	NSS_CAPWAPMGR_FAILURE_CONFIGURE_DSCP_MAP,	/**< Failed to configure dscp_map */
+	NSS_CAPWAPMGR_FAILURE_CREATE_UDF_PROFILE,	/**< Failed creating user defined profile */
+	NSS_CAPWAPMGR_FAILURE_ACL_RULE_ALREADY_EXIST,	/**< ACL rule already exist */
+	NSS_CAPWAPMGR_FAILURE_ADD_ACL_RULE,		/**< Failed adding ACL rule */
+	NSS_CAPWAPMGR_FAILURE_BIND_ACL_LIST,		/**< Failed binding ACL list */
+	NSS_CAPWAPMGR_FAILURE_ACL_UNAVAILABLE,		/**< ACL rule unavailable */
+	NSS_CAPWAPMGR_FAILURE_MEM_UNAVAILABLE,		/**< Failed to alloc memory */
+	NSS_CAPWAPMGR_FAILURE_DSCP_RULE_ID_INVALID,	/**< DSCP rule ID invalid */
+	NSS_CAPWAPMGR_FAILURE_DSCP_RULE_ID_NOT_IN_USE,	/**< DSCP rule not in use */
+	NSS_CAPWAPMGR_FAILURE_DSCP_RULE_DELETE_FAILED,	/**< DSCP rule delete failed */
+} nss_capwapmgr_status_t;
+
+/**
+ * @brief Creates a CAPWAP netdevice
+ *
+ * @return Pointer to a newly created netdevice
+ *
+ * @note First CAPWAP interface name is capwap0 and so on
+ */
+extern struct net_device *nss_capwapmgr_netdev_create(void);
+
+/**
+ * @brief Creates a IPv4 CAPWAP tunnel
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param IPv4 rule structure
+ * @param CAPWAP rule structure
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_ipv4_tunnel_create(struct net_device *dev, uint8_t tunnel_id,
+			struct nss_ipv4_create *ip_rule, struct nss_capwap_rule_msg *capwap_rule,
+			struct nss_dtlsmgr_config *in_data);
+
+/**
+ * @brief Creates a IPv6 CAPWAP tunnel
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param IPv6 rule structure
+ * @param CAPWAP rule structure
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_ipv6_tunnel_create(struct net_device *dev, uint8_t tunnel_id,
+			struct nss_ipv6_create *ip_rule, struct nss_capwap_rule_msg *capwap_rule,
+			struct nss_dtlsmgr_config *in_data);
+
+/**
+ * @brief Enable a CAPWAP tunnel
+ *
+ * @param netdevice
+ * @param tunnel_id
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_enable_tunnel(struct net_device *dev, uint8_t tunnel_id);
+
+/**
+ * @brief Enable a CAPWAP tunnel
+ *
+ * @param netdevice
+ * @param tunnel_id
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_disable_tunnel(struct net_device *dev, uint8_t tunnel_id);
+
+/**
+ * @brief Updates Path MTU of a CAPWAP tunnel
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param New Path MTU
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_update_path_mtu(struct net_device *dev, uint8_t tunnel_id, uint32_t mtu);
+
+/**
+ * @brief Updates Destination MAC Address of a CAPWAP tunnel
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param New MAC Address
+ *
+ * @return nss_capwapmgr_status_t
+ */
+nss_capwapmgr_status_t nss_capwapmgr_update_dest_mac_addr(struct net_device *dev, uint8_t tunnel_id, uint8_t *mac_addr);
+
+/**
+ * @brief Updates Source Interface number
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param source interface number
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_update_src_interface(struct net_device *dev, uint8_t tunnel_id, uint32_t src_interface_num);
+
+/**
+ * @brief Delete a DSCP prioritization rule that was created.
+ *
+ * @param Rule ID
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_dscp_rule_destroy(uint8_t id);
+
+/**
+ * @brief Prioritize packets with certain dscp value. 0 - lowest priority, 3 - highest priority.
+ *
+ * @param DSCP value
+ * @param DSCP mask
+ * @param Priority[0-3]
+ * @param[out] Return rule ID
+ *
+ * @return nss_capwapmgr_status_t
+ */
+nss_capwapmgr_status_t nss_capwapmgr_dscp_rule_create(uint8_t dscp_value, uint8_t dscp_mask, uint8_t pri, uint8_t *id);
+
+/**
+ * @brief Get the DTLS net_device associated to the CAPWAP tunnel
+ *
+ * @param netdevice
+ * @param tunnel_id
+ *
+ * @return Pointer to struct net_device
+ *
+ * @note This API hold the NET_DEVICE reference; after use the caller must perform
+ * "dev_put" to release the reference.
+ */
+struct net_device *nss_capwapmgr_get_dtls_netdev(struct net_device *dev, uint8_t tunnel_id);
+
+/**
+ * @brief Changes version of a CAPWAP tunnel
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param New version
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_change_version(struct net_device *dev, uint8_t tunnel_id, uint8_t ver);
+
+/**
+ * @brief Configure dtls settings of a CAPWAP tunnel
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param enable or disable
+ * @param dtls configuration
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_configure_dtls(struct net_device *dev, uint8_t tunnel_id,
+							uint8_t enable_dtls, struct nss_dtlsmgr_config *in_data);
+
+/**
+ * @brief RX cipher update for a CAPWAP DTLS tunnel
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param dtls configuration update
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_dtls_rekey_rx_cipher_update(struct net_device *dev, uint8_t tunnel_id,
+									struct nss_dtlsmgr_config_update *udata);
+
+/**
+ * @brief TX cipher update for a CAPWAP DTLS tunnel
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param dtls configuration update
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_dtls_rekey_tx_cipher_update(struct net_device *dev, uint8_t tunnel_id,
+									struct nss_dtlsmgr_config_update *udata);
+
+/**
+ * @brief RX cipher switch for a CAPWAP DTLS tunnel
+ *
+ * @param netdevice
+ * @param tunnel_id
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_dtls_rekey_rx_cipher_switch(struct net_device *dev, uint8_t tunnel_id);
+
+/**
+ * @brief TX cipher switch for a CAPWAP DTLS tunnel
+ *
+ * @param netdevice
+ * @param tunnel_id
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_dtls_rekey_tx_cipher_switch(struct net_device *dev, uint8_t tunnel_id);
+
+/**
+ * @brief Destroy a CAPWAP tunnel
+ *
+ * @param netdevice
+ * @param tunnel_id
+ *
+ * @return nss_capwapmgr_status_t
+ *
+ * @note CAPWAP tunnel must be disabled before destroy operation.
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_tunnel_destroy(struct net_device *dev, uint8_t tunnel_id);
+
+/**
+ * @brief Send a flow rule add message to NSS
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param ip_version
+ * @param protocol
+ * @param src_ip
+ * @param dst_ip
+ * @param src_port
+ * @param dst_port
+ * @param flow_id
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_add_flow_rule(struct net_device *dev, uint8_t tunnel_id, uint16_t ip_version,
+						uint16_t protocol, uint32_t *src_ip, uint32_t *dst_ip,
+						uint16_t src_port, uint16_t dst_port, uint32_t flow_id);
+
+/**
+ * @brief Send a flow rule delete message to NSS
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param ip_version
+ * @param protocol
+ * @param src_ip
+ * @param dst_ip
+ * @param src_port
+ * @param dst_port
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_del_flow_rule(struct net_device *dev, uint8_t tunnel_id, uint16_t ip_version,
+						uint16_t protocol, uint32_t *src_ip, uint32_t *dst_ip,
+						uint16_t src_port, uint16_t dst_port);
+
+/**
+ * @brief Destroy a netdevice
+ *
+ * @param netdevice
+ *
+ * @return nss_capwapmgr_status_t
+ *
+ * @note CAPWAP tunnel must be destroyed first.
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_netdev_destroy(struct net_device *netdev);
+
+/**
+ * @brief Gets CAPWAP tunnel stats
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param pointer to struct nss_capwap_tunnel_stats
+ *
+ * @return nss_capwapmgr_status_t
+ */
+extern nss_capwapmgr_status_t nss_capwapmgr_tunnel_stats(struct net_device *dev, uint8_t tunnel_id,
+							struct nss_capwap_tunnel_stats *stats);
+
+#if defined(NSS_CAPWAPMGR_ONE_NETDEV)
+/**
+ * @brief Returns netdevice used by NSS CAPWAP manager
+ *
+ * @param void
+ *
+ * @return Pointer to struct net_device
+ */
+extern struct net_device *nss_capwapmgr_get_netdev(void);
+#endif /* NSS_CAPWAPMGR_ONE_NETDEV */
+#endif /* __NSS_CAPWAPMGR_H */
diff --git a/qca-nss-clients/exports/nss_clmapmgr.h b/qca-nss-clients/exports/nss_clmapmgr.h
new file mode 100644
index 0000000..000fb58
--- /dev/null
+++ b/qca-nss-clients/exports/nss_clmapmgr.h
@@ -0,0 +1,171 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_clmapmgr.h
+ *	Client map manager for NSS
+ */
+#ifndef __NSS_CLMAPMGR_H
+#define __NSS_CLMAPMGR_H
+
+#define NSS_CLMAPMGR_FLAG_VLAN_VALID 0x00000001
+
+/**
+ * Clmapmgr status enums.
+ */
+typedef enum nss_clmapmgr_status {
+	NSS_CLMAPMGR_SUCCESS,				/**< Success. */
+	NSS_CLMAPMGR_ERR_ALLOC_NETDEV_FAILED,		/**< Alloc netdevice failed. */
+	NSS_CLMAPMGR_ERR_NSSIF_UNREGISTER_FAILED,	/**< Unregister netdevice failed. */
+	NSS_CLMAPMGR_ERR_NETDEV_UNKNOWN,		/**< Netdev is not recognized by NSS. */
+	NSS_CLMAPMGR_ERR_NSSIF_DEALLOC_FAILED,		/**< Dynamic interface destroy failed. */
+	NSS_CLMAPMGR_ERR_BAD_PARAM,			/**< Clmapmgr bad parameter. */
+	NSS_CLMAPMGR_ERR_TUNNEL_NOT_FOUND,		/**< Clmapmgr tunnel already exist. */
+	NSS_CLMAPMGR_ERR_ALLOC_TUNNEL_FAILED,		/**< Clmapmgr tunnel alloc failure. */
+	NSS_CLMAPMGR_ERR_MAC_ADD_FAILED,		/**< Clmapmgr MAC addtion failure. */
+	NSS_CLMAPMGR_ERR_MAC_DEL_FAILED,		/**< Clmapmgr MAC deletion failure. */
+	NSS_CLMAPMGR_ERR_MAC_FLUSH_FAILED,		/**< Clmapmgr tunnel rule flush failure. */
+	NSS_CLMAPMGR_ERR_MAX
+} nss_clmapmgr_status_t;
+
+/**
+ * Clmapmgr tunnel type enums.
+ */
+typedef enum nss_clmapmgr_tunnel_type {
+	NSS_CLMAPMGR_TUNNEL_EOGRE = 0,			/**< EoGRE tunnel type. */
+} nss_clmapmgr_tunnel_type_t;
+
+/**
+ * Structure to provide MAC entry message parameters
+ */
+struct nss_clmapmgr_msg {
+	nss_clmapmgr_tunnel_type_t tunnel_type;		/**< Tunnel type. */
+	uint32_t vlan_id;				/**< VLAN id if present. */
+	uint32_t tunnel_id;				/**< Tunnel id. */
+	uint32_t needed_headroom;			/**< Minimum headroom needed in packet for upstream. */
+	uint16_t mac_addr[3];				/**< MAC address. */
+	uint8_t flags;					/**< Flags. */
+	uint8_t reserved;				/**< Reserved. */
+};
+
+/**
+ * @brief Get upstream NSS interface number for the clmap netdevice
+ *
+ * @param dev
+ * 	clmap netdevice
+ *
+ * @return upstream NSS interface number
+ */
+extern int nss_clmapmgr_us_get_if_num(struct net_device *dev);
+
+/**
+ * @brief Get downstream NSS interface number for the clmap netdevice
+ *
+ * @param dev
+ * 	clmap netdevice
+ *
+ * @return downstream NSS interface number
+ */
+extern int nss_clmapmgr_ds_get_if_num(struct net_device *dev);
+
+/**
+ * @brief Send a MAC flush message to NSS
+ *
+ * @param dev
+ * 	clmap netdevice
+ * @param tunnel_id
+ * 	tunnel id for which the MAC addresses needs to be flushed
+ * @param tunnel_type
+ * 	clmapmgr tunnel type of the tunnel
+ *
+ * @return nss_clmapmgr_status_t
+ * 	NSS clmapmgr command status
+ *
+ * @note The API should be used used to flush MAC entries for a tunnel before a tunnel destroy
+ */
+extern nss_clmapmgr_status_t nss_clmapmgr_mac_flush(struct net_device *dev, uint32_t tunnel_id, nss_clmapmgr_tunnel_type_t tunnel_type);
+
+/**
+ * @brief Send a MAC entry remove message to NSS
+ *
+ * @param dev
+ * 	clmap netdevice
+ * @param mac_addr
+ * 	MAC address to be removed
+ *
+ * @return nss_clmapmgr_status_t
+ * 	NSS clmapmgr command status
+ */
+extern nss_clmapmgr_status_t nss_clmapmgr_mac_remove(struct net_device *dev, uint8_t *mac_addr);
+
+/**
+ * @brief Send a MAC entry add message to NSS
+ *
+ * @param dev
+ * 	clmap netdevice
+ * @param clmapmsg
+ * 	tunnel parameters attached to a MAC address
+ *
+ * @return nss_clmapmgr_status_t
+ * 	NSS clmapmgr command status
+ */
+extern nss_clmapmgr_status_t nss_clmapmgr_mac_add(struct net_device *dev, struct nss_clmapmgr_msg *clmapmsg);
+
+/**
+ * @brief Disable a clmapmgr interface
+ *
+ * @param dev
+ * 	clmap netdevice
+ *
+ * @return int
+ * 	Return netdevice command status
+ */
+extern int nss_clmapmgr_netdev_disable(struct net_device *dev);
+
+/**
+ * @brief Enable a clmapmgr interface
+ *
+ * @param dev
+ * 	clmap netdevice
+ *
+ * @return int
+ * 	Return netdevice command status
+ */
+extern int nss_clmapmgr_netdev_enable(struct net_device *dev);
+
+/**
+ * @brief Destroy a clmapmgr netdevice
+ *
+ * @param dev
+ * 	clmap netdevice
+ *
+ * @return nss_clmapmgr_status_t
+ * 	NSS clmapmgr command status
+ *
+ * @note clmap MAC rules for the tunnels must be destroyed before calling this API
+ */
+extern nss_clmapmgr_status_t nss_clmapmgr_netdev_destroy(struct net_device *dev);
+
+/**
+ * @brief Creates a clmapmgr netdevice
+ *
+ * @return Pointer to a newly created netdevice
+ *
+ * @note First Client map interface name is nssclmap0 and so on
+ */
+extern struct net_device *nss_clmapmgr_netdev_create(void);
+
+#endif /* __NSS_CLMAPMGR_H */
diff --git a/qca-nss-clients/exports/nss_connmgr_gre_public.h b/qca-nss-clients/exports/nss_connmgr_gre_public.h
new file mode 100644
index 0000000..dcdeb37
--- /dev/null
+++ b/qca-nss-clients/exports/nss_connmgr_gre_public.h
@@ -0,0 +1,149 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef _NSS_CONNMGR_GRE_PUBLIC_H_
+#define _NSS_CONNMGR_GRE_PUBLIC_H_
+
+#include "nss_dynamic_interface.h"
+
+/**
+ * @brief tap/tun enums
+ *
+ * Only tap is supported
+ */
+enum nss_connmgr_gre_mode {
+	GRE_MODE_TUN,		/**< Tun interface */
+	GRE_MODE_TAP,		/**< Tap interface */
+	GRE_MODE_MAX		/**< Max type */
+};
+
+/**
+ * @brief ipv4/ipv6 tunnel
+ *
+ * Only ipv4 is supported
+ */
+enum nss_connmgr_gre_ip_type {
+	GRE_OVER_IPV4,		/**< IPv4 tunnel */
+	GRE_OVER_IPV6,		/**< IPv6 tunnel */
+};
+
+/**
+ * @brief GRE err codes
+ *
+ * Error codes
+ */
+enum nss_connmgr_gre_err_codes {
+	GRE_SUCCESS = 0,			/**< Success */
+	GRE_ERR_ALLOC_NETDEV = 1,		/**< Alloc netdevice failed */
+	GRE_ERR_NO_NETDEV = 2,			/**< No netdevice found */
+	GRE_ERR_NO_LOCAL_NETDEV = 3,		/**< No netdevice found for corresonding src IP address in cfg */
+	GRE_ERR_NO_NEXT_NETDEV = 4,		/**< No netdevice found for next device in cfg */
+	GRE_ERR_RADDR_ROUTE_LOOKUP = 5,		/**< Route look up failed for destination IP address  */
+	GRE_ERR_NOT_GRE_NETDEV = 6,		/**< Netdevice is not of type GRE */
+	GRE_ERR_NETDEV_REG_FAILED = 7,		/**< Netdevice registration failed */
+	GRE_ERR_INVALID_MODE = 8,		/**< Invalid GRE mode */
+	GRE_ERR_INVALID_MAC = 9,		/**< Invalid MAC */
+	GRE_ERR_NEIGH_CREATE = 10,		/**< Error in creating neigh entry for IP */
+	GRE_ERR_NEIGH_LOOKUP = 11,		/**< Neighbour lookup failed */
+	GRE_ERR_NEIGH_DEV_LOOPBACK = 12,	/**< Neighbour dev is loopback device */
+	GRE_ERR_NEIGH_DEV_NOARP = 13,		/**< Neighbour dev is no ARP device */
+	GRE_ERR_INVALID_IP = 14,		/**< Invalid IP address */
+	GRE_ERR_NODE_UNREG_IN_AE = 15,		/**< Node is not recognized by NSS */
+	GRE_ERR_NEXT_NODE_UNREG_IN_AE = 16,	/**< Next node is not registered in NSS */
+	GRE_ERR_DYNMAIC_IFACE_CREATE = 17,	/**< Dynamic interface creation failed */
+	GRE_ERR_DYNMAIC_IFACE_DESTROY = 18,	/**< Dynamic interface destroy failed */
+	GRE_ERR_GRE_IFACE_REG = 19,		/**< GRE iface register with NSS drv failed */
+	GRE_ERR_AE_CONFIG_FAILED = 20,		/**< AE engine config faild */
+	GRE_ERR_AE_DECONFIG_FAILED = 21,	/**< AE engine delete command faild */
+	GRE_ERR_AE_SET_NEXT_HOP = 22,		/**< Set next hop in AE failed */
+	GRE_ERR_UNSUPPORTED_CFG = 23,		/**< Unsupported configuration */
+	GRE_ERR_IN_INTERRUPT_CTX = 24,		/**< APIs invoked in interrupt context */
+	GRE_ERR_ALLOC_GRE_INSTANCE = 25,	/**< GRE interface instance allcation failed */
+	GRE_ERR_NO_GRE_INSTANCE = 26,		/**< GRE interface instance is not found */
+	GRE_ERR_MAX
+};
+
+/**
+ * @brief User config structure
+ *
+ * User of this client driver needs to fill in this structure and call
+ * nss_connmgr_gre_create_interface() API to create GRE tap interface.
+ * There is no support for Sequence number and checksum.
+ */
+struct nss_connmgr_gre_cfg {
+	enum nss_connmgr_gre_mode mode;		/**< GRE modes. (Mandatory field) */
+	enum nss_connmgr_gre_ip_type ip_type;	/**< IP types (Mandatory field) */
+
+	bool set_df;				/**< Set DF flag ? (Optional field) */
+	bool ikey_valid, okey_valid;		/**< Take care of keys ? (Optional field)*/
+	bool iseq_valid, oseq_valid;		/**< Take care of sequence number ? (No support)*/
+	bool icsum_valid, ocsum_valid;		/**< Take care of checksum ? (No support)*/
+	bool tos_inherit;			/**< Inherit TOS ? (Optional) */
+	bool ttl_inherit;			/**< Interit TTL ? (Optional) */
+	bool dscp_valid;			/**< Is DSCP provided per packet? (Optional) */
+	bool use_mac_hdr;			/**< Add MAC header which is provided (Optional field)*/
+	bool add_padding;			/**< Add padding to make GRE 4 byte aligned ? (Optional field) */
+	bool copy_metadata;			/**< Copy metadata during alignment ? (Optional field) */
+	bool is_ipv6;				/**< Set if addr is IPv6 (Mandatory field)*/
+
+	uint32_t src_ip[4];			/**< Src IP address (Mandatory field) */
+	uint32_t dest_ip[4];			/**< Dest IP address (Mandatory field)*/
+
+	uint16_t src_mac[3];			/**< Src MAC address (Depends on use_mac_hdr field) */
+	uint16_t dest_mac[3];			/**< Dest MAC address (Depends on use_mac_hdr field) */
+
+	uint32_t ikey;				/**< In Key (Optional field)*/
+	uint32_t okey;				/**< Out Key (Optional field)*/
+
+	struct net_device *next_dev;		/**< Next network device inner flow (Mandatory field)*/
+	enum nss_dynamic_interface_type inner_nss_if_type;	/**< Dynamic interface type of inner network device */
+
+	struct net_device *next_dev_outer;	/**< Next network device outer flow (Mandatory field)*/
+	enum nss_dynamic_interface_type outer_nss_if_type;	/**< Dynamic interface type of outer network device */
+
+	char *name;				/**< Name of GRE Tap interface (Optional field) */
+
+	uint8_t ttl;				/**< Time to Live (Depends on ttl_inherit field) */
+	uint8_t tos;				/**< Type of service (Depends on tos_inherit field) */
+	uint16_t reserved;			/**< Reserved for future use */
+};
+
+/**
+ * @brief GRE interface Create/Delete API
+ *
+ * API to create/delete GRE interface. These API should not
+ * be invoked in interrupt/softirq context
+ */
+struct net_device *nss_connmgr_gre_create_interface(
+		struct nss_connmgr_gre_cfg *cfg, enum nss_connmgr_gre_err_codes *err_code);
+
+enum nss_connmgr_gre_err_codes nss_connmgr_gre_destroy_interface(struct net_device *dev);
+
+/**
+ * @brief GRE interface Open API
+ *
+ * API to enable GRE interface.
+ */
+extern int nss_connmgr_gre_dev_open(struct net_device *dev);
+
+/**
+ * @brief GRE interface Close API
+ *
+ * API to disable GRE interface.
+ */
+extern int nss_connmgr_gre_dev_close(struct net_device *dev);
+
+#endif
diff --git a/qca-nss-clients/exports/nss_connmgr_tunipip6.h b/qca-nss-clients/exports/nss_connmgr_tunipip6.h
new file mode 100644
index 0000000..e1a5e21
--- /dev/null
+++ b/qca-nss-clients/exports/nss_connmgr_tunipip6.h
@@ -0,0 +1,103 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef _NSS_CONNMGR_TUNIPIP6_
+#define _NSS_CONNMGR_TUNIPIP6_
+
+/*
+ * Error codes.
+ */
+enum nss_connmgr_tunipip6_err_codes {
+	NSS_CONNMGR_TUNIPIP6_SUCCESS,			/**< Success. */
+	NSS_CONNMGR_TUNIPIP6_TUN_CREATE_FAILURE,	/**< Tunnel create failure. */
+	NSS_CONNMGR_TUNIPIP6_TUN_DESTROY_FAILURE,	/**< Tunnel destroy failure. */
+	NSS_CONNMGR_TUNIPIP6_TUN_NONE,			/**< Invalid tunnel type */
+	NSS_CONNMGR_TUNIPIP6_NETDEV_TYPE_FAILURE,	/**< Netdevice is not of type ipv6-in-ipv4. */
+	NSS_CONNMGR_TUNIPIP6_MAPRULE_ADD_FAILURE,	/**< BMR/FMR addition failure. */
+	NSS_CONNMGR_TUNIPIP6_MAPRULE_DEL_FAILURE,	/**< BMR/FMR deletion failure. */
+	NSS_CONNMGR_TUNIPIP6_FMR_RULE_FLUSH_FAILURE,	/**< FMR flush failure. */
+	NSS_CONNMGR_TUNIPIP6_NO_DEV,			/**< No NSS node found. */
+	NSS_CONNMGR_TUNIPIP6_INVALID_PARAM,		/**< Invalid tunnel parameters. */
+	NSS_CONNMGR_TUNIPIP6_INVALID_RULE_TYPE,		/**< Invalid maprule type. */
+	NSS_CONNMGR_TUNIPIP6_CONTEXT_FAILURE,		/**< Tunnel host context not found. */
+};
+
+/*
+ * IPIP6 tunnel types.
+ */
+enum nss_connmgr_tunipip6_type {
+	NSS_CONNMGR_TUNIPIP6_TUNNEL_4RD,		/**< Tunnel type 4RD. */
+	NSS_CONNMGR_TUNIPIP6_TUNNEL_MAPE,		/**< Tunnel type MAP-E. */
+	NSS_CONNMGR_TUNIPIP6_TUNNEL_MAPE_DRAFT03,	/**< Tunnel type MAP-E with draft03 enable. */
+};
+
+/*
+ * IPIP6 maprule types.
+ */
+typedef enum nss_connmgr_tunipip6_maprule_type {
+	NSS_CONNMGR_TUNIPIP6_RULE_BMR = 1,
+	NSS_CONNMGR_TUNIPIP6_RULE_FMR,
+} nss_connmgr_tunipip6_maprule_type_t;
+
+/**
+ * @brief User config structure
+ *
+ * User of this client driver needs to fill in this structure and call
+ * nss_connmgr_tunipip6_create_interface() API to create IPIP6 interface in NSS.
+ */
+struct nss_connmgr_tunipip6_tunnel_cfg {
+	uint32_t saddr[4];				/**< Tunnel source address. */
+	uint32_t daddr[4];				/**< Tunnel destination address. */
+	uint32_t flowlabel;				/**< Tunnel IPv6 flow label. */
+	uint32_t flags;					/**< Tunnel additional flags. */
+	uint32_t sibling_if_num;			/**< Sibling interface number. */
+	enum nss_connmgr_tunipip6_type tunnel_type;	/**< Tunnel type. */
+	uint8_t hop_limit;				/**< Tunnel IPv6 hop limit. */
+	bool ttl_inherit;				/**< Inherit IPv4 ttl to hoplimit. */
+	bool tos_inherit;				/**< Inherit IPv4 tos. */
+	bool frag_id_update;				/**< Enable fragment ID support. Applicable for MAP-E/4RD only. */
+	uint32_t fmr_max;				/**< Maximum number of FMR that can be configured. */
+};
+
+/**
+ * @brief User config structure
+ *
+ * User of this client driver needs to fill in this structure and call
+ * the below function to add/delete FMR rules.
+ *
+ * Add:	nss_connmgr_tunipip6_add_maprule()
+ * Delete: nss_connmgr_tunipip6_del_maprule()
+ */
+struct nss_connmgr_tunipip6_maprule_cfg {
+	nss_connmgr_tunipip6_maprule_type_t rule_type;	/**< Rule type. */
+	uint32_t ipv6_prefix[4];		/**< IPv6 prefix assigned by a mapping rule. */
+	uint32_t ipv6_prefix_len;		/**< IPv6 prefix length. */
+	uint32_t ipv4_prefix;			/**< IPv4 prefix assigned by a mapping rule. */
+	uint32_t ipv4_prefix_len;		/**< IPv4 prefix length. */
+	uint32_t ipv6_suffix[4];		/**< IPv6 suffix. */
+	uint32_t ipv6_suffix_len;		/**< IPv6 suffix length. */
+	uint32_t ea_len;			/**< Embedded Address (EA) bits. */
+	uint32_t psid_offset;			/**< PSID offset default 6. */
+};
+
+enum nss_connmgr_tunipip6_err_codes nss_connmgr_tunipip6_create_interface(struct net_device *netdev, struct nss_connmgr_tunipip6_tunnel_cfg *tnlcfg);
+enum nss_connmgr_tunipip6_err_codes nss_connmgr_tunipip6_destroy_interface(struct net_device *netdev);
+enum nss_connmgr_tunipip6_err_codes nss_connmgr_tunipip6_add_maprule(struct net_device *netdev, struct nss_connmgr_tunipip6_maprule_cfg *rulecfg);
+enum nss_connmgr_tunipip6_err_codes nss_connmgr_tunipip6_del_maprule(struct net_device *netdev, struct nss_connmgr_tunipip6_maprule_cfg *rulecfg);
+enum nss_connmgr_tunipip6_err_codes nss_connmgr_tunipip6_flush_fmr_rule(struct net_device *netdev);
+#endif
diff --git a/qca-nss-clients/exports/nss_dtlsmgr.h b/qca-nss-clients/exports/nss_dtlsmgr.h
new file mode 100644
index 0000000..75961a5
--- /dev/null
+++ b/qca-nss-clients/exports/nss_dtlsmgr.h
@@ -0,0 +1,470 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_dtlsmgr.h
+ *	DTLS manager interface definitions.
+ */
+#ifndef _NSS_DTLSMGR_H_
+#define _NSS_DTLSMGR_H_
+
+/**
+ * NSS DTLS manager flags
+ */
+#define NSS_DTLSMGR_HDR_IPV6		0x00000001	/**< L3 header is v6 or v4 */
+#define NSS_DTLSMGR_HDR_UDPLITE		0x00000002	/**< L4 header is UDP-Lite or UDP */
+#define NSS_DTLSMGR_HDR_CAPWAP		0x00000004	/**< CAPWAP-DTLS or DTLS header */
+#define NSS_DTLSMGR_CIPHER_MODE_GCM	0x00000008	/**< Cipher mode is GCM */
+#define NSS_DTLSMGR_ENCAP_UDPLITE_CSUM	0x00010000	/**< Checksum UDP-Lite header */
+#define NSS_DTLSMGR_ENCAP_METADATA	0x00020000	/**< Packets will have metadata for encapsulation. */
+#define NSS_DTLSMGR_DECAP_ACCEPT_ALL	0x00040000	/**< Send all error packets after DECAP */
+
+/*
+ * DTLS header mask
+ */
+#define NSS_DTLSMGR_HDR_MASK (NSS_DTLSMGR_HDR_IPV6 | NSS_DTLSMGR_HDR_UDPLITE | NSS_DTLSMGR_HDR_CAPWAP)
+
+/*
+ * DTLS crypto feature mask
+ */
+#define NSS_DTLSMGR_CRYPTO_MASK NSS_DTLSMGR_CIPHER_MODE_GCM
+
+/*
+ * DTLS encapsulation specific flags mask
+ */
+#define NSS_DTLSMGR_ENCAP_MASK (NSS_DTLSMGR_ENCAP_UDPLITE_CSUM | NSS_DTLSMGR_ENCAP_METADATA)
+
+/*
+ * DTLS decapsulation specific flags mask
+ */
+#define NSS_DTLSMGR_DECAP_MASK NSS_DTLSMGR_DECAP_ACCEPT_ALL
+
+/**
+ * NSS DTLS manager TX metadata flags
+ */
+#define NSS_DTLSMGR_METADATA_MAGIC 0x8993		/**< Magic in DTLS metadata */
+#define NSS_DTLSMGR_METADATA_FLAG_ENC 0x0001		/**< Metadata valid for encapsulation. */
+#define NSS_DTLSMGR_METADATA_FLAG_SEQ 0x0002		/**< Metadata has a valid sequence no. */
+#define NSS_DTLSMGR_METADATA_FLAG_CTYPE 0x0004		/**< Metadata has a valid DTLS content type */
+
+/*
+ * NSS DTLS manager reserved size of header
+ */
+#define NSS_DTLSMGR_NEEDED_HEADROOM_SZ 128
+#define NSS_DTLSMGR_NEEDED_TAILROOM_SZ 128
+
+/**
+ * NSS DTLS manager status
+ */
+typedef enum nss_dtlsmgr_status {
+	NSS_DTLSMGR_OK,			/**< Status ok. */
+	NSS_DTLSMGR_FAIL,		/**< Failed due to unknown reason. */
+	NSS_DTLSMGR_FAIL_NOMEM,		/**< Failed to allocate memory. */
+	NSS_DTLSMGR_FAIL_NOCRYPTO,	/**< Failed to allocate crypto resource. */
+	NSS_DTLSMGR_FAIL_MESSAGE,	/**< Failed to message the NSS. */
+	NSS_DTLSMGR_INVALID_VERSION,	/**< Invalid DTLS version. */
+	NSS_DTLSMGR_INVALID_ALGO,	/**< Invalid algorithm. */
+	NSS_DTLSMGR_INVALID_KEYLEN,	/**< Invalid key length for cipher/auth. */
+} nss_dtlsmgr_status_t;
+
+/**
+ * DTLS protocol version
+ */
+enum nss_dtlsmgr_dtlsver {
+	NSS_DTLSMGR_VERSION_1_0,	/**< Protocol v1.0. */
+	NSS_DTLSMGR_VERSION_1_2,	/**< Protocol v1.2. */
+};
+
+/**
+ * DTLS interface type
+ */
+enum nss_dtlsmgr_interface_type {
+	NSS_DTLSMGR_INTERFACE_TYPE_NONE,
+	NSS_DTLSMGR_INTERFACE_TYPE_INNER,	/**< DTLS encapsulation interface */
+	NSS_DTLSMGR_INTERFACE_TYPE_OUTER,	/**< DTLS decapsulation interface */
+	NSS_DTLSMGR_INTERFACE_TYPE_MAX
+};
+
+/**
+ * NSS DTLS manager supported cryptographic algorithms
+ */
+enum nss_dtlsmgr_algo {
+	NSS_DTLSMGR_ALGO_AES_CBC_SHA1_HMAC,	/**< AES_CBC_SHA1_HMAC. */
+	NSS_DTLSMGR_ALGO_AES_CBC_SHA256_HMAC,	/**< AES_CBC_SHA256_HMAC. */
+	NSS_DTLSMGR_ALGO_3DES_CBC_SHA1_HMAC,	/**< 3DES_CBC_SHA1_HMAC. */
+	NSS_DTLSMGR_ALGO_3DES_CBC_SHA256_HMAC,	/**< 3DES_CBC_SHA256_HMAC. */
+	NSS_DTLSMGR_ALGO_AES_GCM,		/**< AES_GCM. */
+	NSS_DTLSMGR_ALGO_MAX
+};
+
+/**
+ * NSS DTLS manager metadata ctype
+ */
+enum nss_dtlsmgr_metadata_ctype {
+	NSS_DTLSMGR_METADATA_CTYPE_CCS = 20,		/**< DTLS packet is change cipher specification.*/
+	NSS_DTLSMGR_METADATA_CTYPE_ALERT = 21,		/**< DTLS packet is Alert.*/
+	NSS_DTLSMGR_METADATA_CTYPE_HANDSHAKE = 22,	/**< DTLS packet is Handshake.*/
+	NSS_DTLSMGR_METADATA_CTYPE_APP = 23,		/**< DTLS packet is Application data. */
+};
+
+/**
+ * NSS DTLS manager metadata result type
+ */
+enum nss_dtlsmgr_metadata_result {
+	NSS_DTLSMGR_METADATA_RESULT_OK = 0,		/**< Result OK. */
+	NSS_DTLSMGR_METADATA_RESULT_AUTH_FAIL = 1,	/**< Authenication failure. */
+	NSS_DTLSMGR_METADATA_RESULT_CIPHER_FAIL = 2,	/**< Cipher failure. */
+	NSS_DTLSMGR_METADATA_RESULT_MAX,
+};
+
+/**
+ * NSS DTLS manager cryptographic structure to represent key and its length.
+ */
+struct nss_dtlsmgr_crypto_data {
+	const uint8_t *data;		/**< Pointer to key or nonce. */
+	uint16_t len;			/**< Length of the key. */
+};
+
+/**
+ * NSS DTLS manager cryptographic data
+ */
+struct nss_dtlsmgr_crypto {
+	enum nss_dtlsmgr_algo algo;			/**< DTLS manager cryptographic algorithm. */
+	struct nss_dtlsmgr_crypto_data cipher_key;	/**< Cipher key. */
+	struct nss_dtlsmgr_crypto_data auth_key;	/**< Authentication key. */
+	struct nss_dtlsmgr_crypto_data nonce;		/**< Nonce. */
+};
+
+/**
+ * NSS DTLS manager session encapsulation data
+ */
+struct nss_dtlsmgr_encap_config {
+	struct nss_dtlsmgr_crypto crypto;	/**< Encapsulation crypto configuration. */
+	enum nss_dtlsmgr_dtlsver ver;		/**< Version used in DTLS header. */
+	uint32_t sip[4];			/**< Source IP address. */
+	uint32_t dip[4];			/**< Destination IP address. */
+	uint16_t sport;				/**< Source UDP port. */
+	uint16_t dport;				/**< Destination UDP port. */
+	uint16_t epoch;				/**< Epoch. */
+	uint8_t ip_ttl;				/**< IP time to live. */
+	uint8_t dscp;				/**< DSCP. */
+	bool dscp_copy;				/**< Flag to check if DSCP needs to be copied. */
+	bool df;				/**< Flag to check fragmentation. */
+};
+
+/**
+ * NSS DTLS manager session decapsulation data
+ */
+struct nss_dtlsmgr_decap_config {
+	struct nss_dtlsmgr_crypto crypto;	/**< Decap Crypto configuration. */
+	uint32_t nexthop_ifnum;			/**< NSS I/F number to forward after de-capsulation. */
+	uint16_t window_size;			/**< Anti-Replay window size. */
+};
+
+/*
+ * NSS DTLS manager hardware statistics
+ */
+struct nss_dtlsmgr_hw_stats {
+	uint64_t len_error;             /**< Length error. */
+	uint64_t token_error;           /**< Token error, unknown token command/instruction. */
+	uint64_t bypass_error;          /**< Token contains too much bypass data. */
+	uint64_t config_error;          /**< Invalid command/algorithm/mode/combination. */
+	uint64_t algo_error;            /**< Unsupported algorithm. */
+	uint64_t hash_ovf_error;        /**< Hash input overflow. */
+	uint64_t ttl_error;             /**< TTL or HOP-Limit underflow. */
+	uint64_t csum_error;            /**< Checksum error. */
+	uint64_t timeout_error;         /**< Data timed-out. */
+};
+
+/**
+ * NSS DTLS manager session statistics
+ */
+struct nss_dtlsmgr_stats {
+	uint64_t tx_packets;		/**< Tx packets. */
+	uint64_t tx_bytes;		/**< Tx bytes. */
+	uint64_t rx_packets;		/**< Rx packets. */
+	uint64_t rx_bytes;		/**< Rx bytes. */
+	uint64_t rx_dropped;		/**< Rx drops. */
+	uint64_t rx_single_rec;		/**< Received single DTLS record datagrams. */
+	uint64_t rx_multi_rec;		/**< Received multiple DTLS record datagrams. */
+	uint64_t fail_crypto_resource;	/**< Failure in allocation of crypto resource. */
+	uint64_t fail_crypto_enqueue;	/**< Failure due to queue full in crypto or hardware. */
+	uint64_t fail_headroom;		/**< Failure in headroom check. */
+	uint64_t fail_tailroom;		/**< Failure in tailroom check. */
+	uint64_t fail_ver;		/**< Failure in DTLS version check. */
+	uint64_t fail_epoch;		/**< Failure in DTLS epoch check. */
+	uint64_t fail_dtls_record;	/**< Failure in reading DTLS record. */
+	uint64_t fail_capwap;		/**< Failure in Capwap classification. */
+	uint64_t fail_replay;		/**< Failure in anti-replay check. */
+	uint64_t fail_replay_dup;	/**< Failure in anti-replay; duplicate records. */
+	uint64_t fail_replay_win;	/**< Failure in anti-replay; packet outside the window. */
+	uint64_t fail_queue;		/**< Failure due to queue full in DTLS. */
+	uint64_t fail_queue_nexthop;	/**< Failure due to queue full in next_hop. */
+	uint64_t fail_pbuf_alloc;	/**< Failure in pbuf allocation. */
+	uint64_t fail_pbuf_linear;	/**< Failure in pbuf linearization. */
+	uint64_t fail_pbuf_stats;	/**< Failure in pbuf allocation for stats. */
+	uint64_t fail_pbuf_align;	/**< Failure in pbuf alignment. */
+	uint64_t fail_ctx_active;	/**< Failure in enqueue due to no active context. */
+	uint64_t fail_hwctx_active;	/**< Failure in enqueue due to no active HW context. */
+	uint64_t fail_cipher;		/**< Failure in decrypting the data. */
+	uint64_t fail_auth;		/**< Failure in authenticating the data. */
+	uint64_t fail_seq_ovf;		/**< Failure due to sequence number overflow. */
+	uint64_t fail_blk_len;		/**< Failure in decapsulation due to bad cipher block length. */
+	uint64_t fail_hash_len;		/**< Failure in decapsulation due to bad hash block length. */
+
+	struct nss_dtlsmgr_hw_stats fail_hw;
+					/**< Hardware failure statistics. */
+
+	uint64_t fail_cle[NSS_DTLS_CMN_CLE_MAX];
+					/**< Classification errors. */
+
+	uint64_t fail_host_tx;		/**< Failure at host TX. */
+	uint64_t fail_host_rx;		/**< Failure at host RX. */
+
+	uint32_t seq_low;		/**< Lower 32 bits of current Tx sequence number. */
+	uint32_t seq_high;		/**< Upper 16 bits of current Tx sequence number. */
+
+	uint16_t epoch;			/**< Current Epoch value. */
+};
+
+#ifdef __KERNEL__ /* only for kernel use. */
+
+/**
+ * NSS DTLS manager session stats update callback
+ */
+typedef void (*nss_dtlsmgr_notify_callback_t)(void *app_data, struct net_device *dev,
+						struct nss_dtlsmgr_stats *stats, bool encap);
+typedef void (*nss_dtlsmgr_data_callback_t)(void *app_data, struct sk_buff *skb);
+
+/**
+ * NSS DTLS manager session definition
+ */
+struct nss_dtlsmgr_config {
+	uint32_t flags;					/**< DTLS header flags. */
+	void *app_data;					/**< Opaque data returned in callback. */
+
+	nss_dtlsmgr_notify_callback_t notify;		/**< Statistics notifcation callback. */
+	nss_dtlsmgr_data_callback_t data;		/**< Data callback. */
+
+	struct nss_dtlsmgr_encap_config encap;		/**< Encap data. */
+	struct nss_dtlsmgr_decap_config decap;		/**< Decap data. */
+};
+
+#endif /* __KERNEL__ */
+/**
+ * NSS DTLS manager session tx/rx cipher update parameters
+ */
+struct nss_dtlsmgr_config_update {
+	struct nss_dtlsmgr_crypto crypto;	/**< Crypto algorithm and key data. */
+	uint16_t epoch;				/**< Epoch. */
+	uint16_t window_size;			/**< Anti-Replay window size. */
+};
+
+/**
+ * NSS DTLS manager metadata
+ */
+struct nss_dtlsmgr_metadata {
+	uint8_t ctype;		/**< Type of DTLS packet. */
+	uint8_t result;		/**< Error during DTLS decapsulation. */
+	uint16_t len;		/**< Length of DTLS payload. */
+	uint32_t seq;		/**< Sequence for encapsulation. */
+	uint16_t flags;		/**< Metadata flags. */
+	uint16_t magic;		/**< Magic. */
+};
+
+#ifdef __KERNEL__ /* only for kernel use. */
+
+/**
+ * nss_dtlsmgr_metadata_init
+ *	Initializes the metadata at SKB head
+ *
+ * @param skb[IN] Socket buffer
+ *
+ * @return
+ * Return NSS DTLSMGR metadata start address
+ */
+static inline struct nss_dtlsmgr_metadata *nss_dtlsmgr_metadata_init(struct sk_buff *skb)
+{
+	struct nss_dtlsmgr_metadata *ndm;
+
+	if (unlikely(skb_headroom(skb) < sizeof(*ndm)))
+		return NULL;
+
+	ndm = (struct nss_dtlsmgr_metadata *)skb_push(skb, sizeof(*ndm));
+	/*
+	 * Initialize the metadata with default values
+	 */
+	ndm->flags = NSS_DTLSMGR_METADATA_FLAG_ENC;
+	ndm->ctype = NSS_DTLSMGR_METADATA_CTYPE_APP;
+	ndm->magic = NSS_DTLSMGR_METADATA_MAGIC;
+	ndm->len = skb->len - sizeof(*ndm);
+	ndm->seq = U32_MAX;
+	ndm->result = 0;
+
+	return ndm;
+}
+
+/**
+ * nss_dtlsmgr_metadata_set_seq
+ *	Update the metadata with sequence number for the first encap packet
+ *
+ * @param ndtm[IN] NSS DTLSMGR metadata
+ * @param seq[IN]  Starting sequence number for the tunnel encapsulation
+ */
+static inline void nss_dtlsmgr_metadata_set_seq(struct nss_dtlsmgr_metadata *ndm, uint32_t seq)
+{
+	ndm->flags |= NSS_DTLSMGR_METADATA_FLAG_SEQ;
+	ndm->seq = seq;
+}
+
+/**
+ * nss_dtlsmgr_metadata_set_ctype
+ *	Update the metadata with DTLS content type
+ *
+ * @param ndtm[IN]  NSS DTLSMGR metadata
+ * @param ctype[IN] DTLS content type for encapsulation
+ */
+static inline void nss_dtlsmgr_metadata_set_ctype(struct nss_dtlsmgr_metadata *ndm, enum nss_dtlsmgr_metadata_ctype ctype)
+{
+	ndm->flags |= NSS_DTLSMGR_METADATA_FLAG_CTYPE;
+	ndm->ctype = ctype;
+}
+
+/**
+ * nss_dtlsmgr_metadata_get_ctype
+ *	Returns the type of DTLS payload
+ *
+ * @param ndm[IN] DTLS metadata header
+ *
+ * @return
+ * NSS_DTLSMGR_METADATA_CTYPE_APP for normal data
+ */
+static inline enum nss_dtlsmgr_metadata_ctype nss_dtlsmgr_metadata_get_ctype(struct nss_dtlsmgr_metadata *ndm)
+{
+	return ndm->ctype;
+}
+
+/**
+ * nss_dtlsmgr_metadata_get_error
+ *	Returns the error seen during decapsulation
+ *
+ * @param ndm[IN] DTLS metadata header
+ *
+ * @return
+ * NSS_DTLSMGR_METADATA_RESULT_OK for success
+ */
+static inline enum nss_dtlsmgr_metadata_result nss_dtlsmgr_metadata_get_result(struct nss_dtlsmgr_metadata *ndm)
+{
+	return ndm->result;
+}
+
+/**
+ * nss_dtlsmgr_metadata_verify_magic
+ *	Returns true if magic pattern matches
+ *
+ * @param ndm[IN] DTLS metadata header
+ *
+ * @return
+ * true for success
+ */
+static inline bool nss_dtlsmgr_metadata_verify_magic(struct nss_dtlsmgr_metadata *ndm)
+{
+	return ndm->magic == NSS_DTLSMGR_METADATA_MAGIC;
+}
+
+/**
+ * nss_dtlsmgr_session_create
+ *	Create a NSS DTLS session and associated crypto sessions
+ *
+ * @param in_data[IN] DTLS session create data
+ * @param out_data[out] Return parameters from DTLS session create operation
+ *
+ * @return
+ * NSS_DTLSMGR_OK for success
+ */
+struct net_device *nss_dtlsmgr_session_create(struct nss_dtlsmgr_config *cfg);
+
+/**
+ * nss_dtlsmgr_session_destroy
+ *	Destroy a NSS DTLS session and associated crypto sessions
+ *
+ * @param dtls_if[IN] NSS DTLS I/F
+ *
+ * @return
+ * NSS_DTLSMGR_OK for success
+ */
+nss_dtlsmgr_status_t nss_dtlsmgr_session_destroy(struct net_device *dev);
+
+/**
+ * nss_dtlsmgr_session_update_encap
+ *	Update encapsulation cipher state of a DTLS session.
+ *	Configures new parameters into the pending encapsulation cipher
+ *	state of a DTLS session. This has no effect on the current
+ *	cipher state and its processing of packets.
+ *
+ * @param dev[IN] DTLS network device
+ * @param cfg[IN] DTLS session update parameters
+ *
+ * @return NSS_DTLSMGR_OK for success
+ */
+nss_dtlsmgr_status_t nss_dtlsmgr_session_update_encap(struct net_device *dev, struct nss_dtlsmgr_config_update *cfg);
+
+/**
+ * nss_dtlsmgr_session_update_decap
+ *	Update decapsulation cipher state of a DTLS session.
+ *	Configures new parameters into the pending decapsulation cipher
+ *	state of a DTLS session. This has no effect on the current
+ *	cipher state and its processing of packets.
+ *
+ * @param dev[IN] DTLS network device
+ * @param cfg[IN] DTLS session update parameters
+ *
+ * @return NSS_DTLSMGR_OK for success
+ */
+nss_dtlsmgr_status_t nss_dtlsmgr_session_update_decap(struct net_device *dev, struct nss_dtlsmgr_config_update *cfg);
+
+/**
+ * nss_dtlsmgr_session_switch_encap
+ *	Switch DTLS session from current to new for encapsulation
+ *
+ * @param dev[in] DTLS network device
+ *
+ * @return TRUE for success
+ */
+bool nss_dtlsmgr_session_switch_encap(struct net_device *dev);
+
+/**
+ * nss_dtlsmgr_session_switch_decap
+ *	Switch DTLS session from current to new for de-capsulation
+ *
+ * @param dev[in] DTLS network device
+ *
+ * @return TRUE for success
+ */
+bool nss_dtlsmgr_session_switch_decap(struct net_device *dev);
+
+/**
+ * nss_dtlmsgr_get_interface
+ *	Get the NSS interface number for encap/decap interface.
+ *
+ * @param dev[in] DTLS network device
+ * @param type[in] DTLS interface type
+ *
+ * @return interface number for success
+ */
+int32_t nss_dtlsmgr_get_interface(struct net_device *dev, enum nss_dtlsmgr_interface_type type);
+#endif /* __KERNEL__ */
+#endif /* _NSS_DTLSMGR_H_ */
diff --git a/qca-nss-clients/exports/nss_eogremgr.h b/qca-nss-clients/exports/nss_eogremgr.h
new file mode 100644
index 0000000..29e940f
--- /dev/null
+++ b/qca-nss-clients/exports/nss_eogremgr.h
@@ -0,0 +1,120 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_eogremgr.h
+ *	Hedaer file of eogre manager
+ */
+#ifndef __NSS_EOGREMGR_H
+#define __NSS_EOGREMGR_H
+
+#include <linux/if_vlan.h>
+#include <net/gre.h>
+#include <net/ipv6.h>
+#include "nss_connmgr_gre_public.h"
+
+
+/*
+ * Maximum number of tunnels currently supported
+ */
+#define NSS_EOGREMGR_MAX_TUNNELS	64
+
+/*
+ * Maximum headroom required for an EoGRE tunnel. Include GRE key (4 bytes) in the calculation
+ */
+#define NSS_EOGREMGR_MAX_HEADROOM	sizeof(struct ethhdr) + sizeof(struct vlan_hdr) + sizeof(struct gre_base_hdr) + sizeof(uint32_t) + sizeof(struct ipv6hdr)
+
+typedef enum nss_eogremgr_err_code {
+	NSS_EOGRE_SUCCESS = 0,			/**< Eogre success */
+	NSS_EOGRE_ERR_INVALID_TUNNEL_ID = 1,		/**< Invalid tunnel id */
+	NSS_EOGRE_ERR_CREATE_IP_RULE_FAILED = 2,	/**< Create IP Rule failed */
+	NSS_EOGRE_ERR_DESTROY_IP_RULE_FAILED = 3,	/**< Destroy IP Rule failed */
+	NSS_EOGRE_ERR_BAD_NSS_CTX = 4,		/**< Failed to get NSS context */
+	NSS_EOGRE_ERR_NETDEV_DISABLE_FAILED = 5,	/**< Failed to disable netdev */
+	NSS_EOGRE_ERR_NETDEV_ENABLE_FAILED = 6,	/**< Failed to enable netdev */
+	NSS_EOGRE_ERR_ALLOC_TUNNEL_FAILED = 7,	/**< Alloc tunnel memory failed */
+	NSS_EOGRE_TUNNEL_DESTROY_FAILED = 8,	/**< Tunnel destroy failed */
+	NSS_EOGRE_ERR_GRE_CREATE_FAILED = 9,	/**< GRE interface create failed */
+	NSS_EOGRE_ERR_TUNNEL_ID_EXIST = 10,	/**< Tunnel id already exist */
+	NSS_EOGRE_ERR_INVALID_GRE_IFNUM = 11,	/**< Failed to get valid GRE interface number */
+	NSS_EOGRE_ERR_MAX
+} nss_eogremgr_status_t;
+
+/**
+ *
+ * @brief Get GRE inner NSS interface number associated with the tunnel_id
+ *
+ * @param[in] tunnel_id
+ *
+ * @return int
+ */
+extern int nss_eogremgr_get_if_num_inner(uint32_t tunnel_id);
+
+/**
+ *
+ * @brief Disable a EoGRE tunnel
+ *
+ * @param[in] tunnel_id
+ *
+ * @return nss_eogremgr_status_t
+ */
+extern nss_eogremgr_status_t nss_eogremgr_tunnel_disable(uint32_t tunnel_id);
+
+/**
+ *
+ * @brief Enable a EoGRE tunnel
+ *
+ * @param[in] tunnel_id
+ *
+ * @return nss_eogremgr_status_t
+ */
+extern nss_eogremgr_status_t nss_eogremgr_tunnel_enable(uint32_t tunnel_id);
+
+/**
+ *
+ * @brief Destroy the EoGRE tunnel for the given tunnel_id
+ *
+ * @param[in] tunnel_id
+ *
+ * @return nss_eogremgr_status_t
+ */
+extern nss_eogremgr_status_t nss_eogremgr_tunnel_destroy(uint32_t tunnel_id);
+
+/**
+ *
+ * @brief Create an IPv6 type EoGRE tunnel for the given tunnel_id
+ *
+ * @param[in] cfg        GRE configuration structure
+ * @param[in] nircm      IPv6 rule create message
+ * @param[in] tunnel_id  EoGRE tunnel_id
+ *
+ * @return nss_eogremgr_status_t
+ */
+extern nss_eogremgr_status_t nss_eogremgr_tunnel_ipv6_create(struct nss_connmgr_gre_cfg *cfg, struct nss_ipv6_rule_create_msg *nircm, uint32_t tunnel_id);
+
+/**
+ *
+ * @brief Create an IPv4 type EoGRE tunnel for the given tunnel_id
+ *
+ * @param[in] cfg        GRE configuration structure
+ * @param[in] nircm      IPv4 rule create message
+ * @param[in] tunnel_id  EoGRE tunnel_id
+ *
+ * @return nss_eogremgr_status_t
+ */
+extern nss_eogremgr_status_t nss_eogremgr_tunnel_ipv4_create(struct nss_connmgr_gre_cfg *cfg, struct nss_ipv4_rule_create_msg *nircm, uint32_t tunnel_id);
+
+#endif /* __NSS_EOGREMGR_H */
diff --git a/qca-nss-clients/exports/nss_ipsecmgr.h b/qca-nss-clients/exports/nss_ipsecmgr.h
new file mode 100644
index 0000000..e5d2b7b
--- /dev/null
+++ b/qca-nss-clients/exports/nss_ipsecmgr.h
@@ -0,0 +1,688 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2019, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_ipsecmgr.h
+ *	NSS IPSec Manager interface definitions.
+ */
+
+#ifndef __NSS_IPSECMGR_H
+#define __NSS_IPSECMGR_H
+
+/**
+ * @addtogroup nss_ipsec_manager_subsystem
+ * @{
+ */
+#define NSS_IPSECMGR_TUN_NAME "ipsectun%d"	/**< IPsec tunnel name. */
+
+/**
+ * Length of the header added after encapsulation.
+ *
+ * This estimate must be accurate but large enough to accomodate most use cases.
+ */
+#define NSS_IPSECMGR_TUN_MAX_HDR_LEN 96
+
+/*
+ * Space required in the head and tail of the buffer.
+ */
+#define NSS_IPSECMGR_TUN_HEADROOM 128		/**< Size of the buffer headroom. */
+#define NSS_IPSECMGR_TUN_TAILROOM 192		/**< Size of the buffer tailroom. */
+
+#define NSS_IPSECMGR_TUN_MTU(x) (x - NSS_IPSECMGR_TUN_MAX_HDR_LEN)
+						/**< MTU of the IPsec tunnel. */
+
+#define NSS_IPSECMGR_NATT_PORT_DATA 4500	/**< Number of the NATT port. */
+
+#define NSS_IPSECMGR_CIPHER_KEYLEN_MAX 32	/**< Max cipher key length. */
+#define NSS_IPSECMGR_AUTH_KEYLEN_MAX 32		/**< Max auth key length. */
+#define NSS_IPSECMGR_NONCE_SIZE_MAX 4		/**< Max nonce size. */
+
+/**
+ * nss_ipsecmgr_event_type
+ *	Event types for the IPsec manager.
+ */
+enum nss_ipsecmgr_event_type {
+	NSS_IPSECMGR_EVENT_NONE = 0,
+	NSS_IPSECMGR_EVENT_SA_STATS,	/**< Event type for IPsec mangager SA stats. */
+	NSS_IPSECMGR_EVENT_MAX
+};
+
+/**
+ * nss_ipsecmgr_status
+ * 	Return statuses for IPsec manager.
+ */
+typedef enum nss_ipsecmgr_status {
+	NSS_IPSECMGR_OK,		/**< Status ok. */
+	NSS_IPSECMGR_FAIL,		/**< Failed due to unknown reason. */
+	NSS_IPSECMGR_FAIL_NOMEM,	/**< Failed to allocate memory. */
+	NSS_IPSECMGR_FAIL_NOCRYPTO,	/**< Failed to allocate crypto resource. */
+	NSS_IPSECMGR_FAIL_MESSAGE,	/**< Failed to message the NSS. */
+	NSS_IPSECMGR_FAIL_ADD_DB,	/**< Failed to add to database. */
+	NSS_IPSECMGR_FAIL_FLOW_ALLOC,	/**< Failed to alloc flow. */
+	NSS_IPSECMGR_FAIL_FLOW,		/**< Failed to find the flow. */
+	NSS_IPSECMGR_INVALID_CTX,	/**< Invalid context */
+	NSS_IPSECMGR_INVALID_ALGO,	/**< Invalid algorithm. */
+	NSS_IPSECMGR_INVALID_IPVER,	/**< Invalid IP version. */
+	NSS_IPSECMGR_INVALID_CRYPTO_IDX,/**< Invalid crypto index */
+	NSS_IPSECMGR_INVALID_KEYLEN,	/**< Invalid key length for cipher or authentication. */
+	NSS_IPSECMGR_INVALID_WINDOW,	/**< Invalid window size. */
+	NSS_IPSECMGR_INVALID_SA,	/**< Ivalid SA. */
+	NSS_IPSECMGR_DUPLICATE_SA,	/**< Duplicate SA allocation. */
+	NSS_IPSECMGR_DUPLICATE_FLOW,	/**< Duplicate flow allocation. */
+} nss_ipsecmgr_status_t;
+
+/**
+ * nss_ipsecmgr_algo
+ * 	IPsec manager supported cryptographic algorithms.
+ */
+enum nss_ipsecmgr_algo {
+	NSS_IPSECMGR_ALGO_AES_CBC_SHA1_HMAC,		/**< AES_CBC_SHA1_HMAC. */
+	NSS_IPSECMGR_ALGO_AES_CBC_SHA256_HMAC,		/**< AES_CBC_SHA256_HMAC. */
+	NSS_IPSECMGR_ALGO_3DES_CBC_SHA1_HMAC,		/**< 3DES_CBC_SHA1_HMAC. */
+	NSS_IPSECMGR_ALGO_3DES_CBC_SHA256_HMAC,		/**< 3DES_CBC_SHA256_HMAC. */
+	NSS_IPSECMGR_ALGO_NULL_CIPHER_SHA1_HMAC,	/**< NULL_CIPHER_SHA1_HMAC. */
+	NSS_IPSECMGR_ALGO_NULL_CIPHER_SHA256_HMAC,	/**< NULL_CIPHER_SHA256_HMAC. */
+	NSS_IPSECMGR_ALGO_AES_GCM_GMAC_RFC4106,		/**< AES GCM/GMAC based on RFC4106 */
+	NSS_IPSECMGR_ALGO_AES_CBC_MD5_HMAC,		/**< AES_CBC_MD5_HMAC. */
+	NSS_IPSECMGR_ALGO_3DES_CBC_MD5_HMAC,		/**< 3DES_CBC_MD5_HMAC. */
+	NSS_IPSECMGR_ALGO_AES_CBC_SHA384_HMAC,		/**< AES CBC SHA384 HMAC. */
+	NSS_IPSECMGR_ALGO_AES_CBC_SHA512_HMAC,		/**< AES CBC SHA512 HMAC. */
+	NSS_IPSECMGR_ALGO_MAX
+};
+
+/**
+ * nss_ipsecmgr_sa_type
+ *	Types of security associations in IPsec manager.
+ */
+enum nss_ipsecmgr_sa_type {
+	NSS_IPSECMGR_SA_TYPE_NONE = 0,
+	NSS_IPSECMGR_SA_TYPE_ENCAP,	/**< Encap type SA. */
+	NSS_IPSECMGR_SA_TYPE_DECAP,	/**< Decap type SA. */
+	NSS_IPSECMGR_SA_TYPE_MAX
+};
+
+/**
+ * nss_ipsecmgr_crypto_keys
+ * 	Information required to configure crypto session for IPsec.
+ */
+struct nss_ipsecmgr_crypto_keys {
+	const uint8_t *cipher_key;	/**< Cipher key. */
+	const uint8_t *auth_key;	/**< Authentication key. */
+	const uint8_t *nonce;		/**< Nonce. */
+
+	uint16_t cipher_keylen;		/**< Cipher key length. */
+	uint16_t auth_keylen;		/**< Authentication key length. */
+	uint16_t nonce_size;		/**< Nonce size. */
+};
+
+/**
+ * nss_ipsecmgr_crypto_index
+ * 	Information about a pre-configured crypto session.
+ */
+struct nss_ipsecmgr_crypto_index {
+	uint16_t session;		/**< Crypto session index. */
+	uint8_t blk_len;		/**< Cipher block length. */
+	uint8_t iv_len;			/**< Cipher IV length. */
+};
+
+/**
+ * nss_ipsecmgr_sa_cmn
+ * 	Common information necessary to configure an SA.
+ */
+struct nss_ipsecmgr_sa_cmn {
+	enum nss_ipsecmgr_algo algo;		/**< Supported crypto algorithms */
+	struct nss_ipsecmgr_crypto_keys keys;	/**< Crypto keys */
+	struct nss_ipsecmgr_crypto_index index;	/**< Crypto index or offset */
+
+	uint8_t icv_len;			/**< Hash length. */
+
+	bool skip_trailer;			/**< Skip the ESP trailer for encapsulation. */
+	bool enable_esn;			/**< Enable the extended sequence number. */
+	bool enable_natt;			/**< NAT-T is required. */
+	bool crypto_has_keys;			/**< Crypto configured with keys. */
+	bool transport_mode;			/**< True, if IPSec is in transport mode. */
+};
+
+/**
+ * nss_ipsecmgr_sa_encap
+ *	SA information for an encapsulation flow.
+ *
+ * For DSCP marking, use the following settings:
+ * - Copy inner header to outer header:
+ *    - dscp_copy = 1
+ *    - dscp = 0
+ * - Fixed mark on outer header:
+ *    - dscp_copy = 0
+ *    - dscp = <0 to 63>
+ * - Transmit default
+ *	SA with TX default is used when host originating flows don't have
+ *	an explicit inner flow rule programmed for IPsec.
+ */
+struct nss_ipsecmgr_sa_encap {
+	uint32_t seq_start;	/**< Starting sequence number (Not used) */
+	uint8_t ttl_hop_limit;	/**< Time-to-Live or hop limit. */
+	uint8_t dscp;		/**< Default DSCP value of the security association. */
+	uint8_t df;		/**< Don't-Fragment value for the outer header, if nocopy is selected. */
+
+	bool copy_dscp;		/**< Copy DSCP from the inner header to the outer header. */
+	bool copy_df;		/**< Copy DF from the inner header to the outer header. */
+	bool tx_default;	/**< TX SA(one per tunnel) for host traffic, without a flow rule.*/
+};
+
+/**
+ * nss_ipsecmgr_sa_decap
+ *	SA information for a decapsulation flow.
+ */
+struct nss_ipsecmgr_sa_decap {
+	uint32_t replay_fail_thresh;	/**< Threshold for consecutive hash failures in replay. */
+	uint16_t replay_win;	/**< Sequence number window size for anti-replay. */
+};
+
+/**
+ * nss_ipsecmgr_sa_data
+ *	Security association information for the IPsec manager.
+ *
+ * Note: Zero out structure before filling the fields.
+ */
+struct nss_ipsecmgr_sa_data {
+	struct nss_ipsecmgr_sa_cmn cmn;		/**< Common configuration information for SA. */
+
+	enum nss_ipsecmgr_sa_type type;		/**< Type of SA. */
+	struct nss_ipsecmgr_sa_encap encap;	/**< Information for encap type SA. */
+	struct nss_ipsecmgr_sa_decap decap;	/**< Information for decap type SA. */
+};
+
+/**
+ * nss_ipsecmgr_sa_tuple
+ *	SA information for the IPsec manager.
+ *
+ * Note: Protocol/Next Header defaults to ESP for outer.
+ *	 Zero out structure before filling the fields.
+ */
+struct nss_ipsecmgr_sa_tuple {
+	uint32_t src_ip[4];	/**< IPv6 source IP. */
+	uint32_t dest_ip[4];	/**< IPv6 destination IP. */
+	uint32_t spi_index;	/**< SPI index of the encapsulating security payload (ESP). */
+	uint16_t sport;		/**< Source port. */
+	uint16_t dport;		/**< Destination port. */
+	uint8_t proto_next_hdr;	/**< Protocol (ESP or NAT-T) */
+	uint8_t ip_version;	/**< IP version 4/6. */
+	uint8_t res[2];		/**< Reserved */
+};
+
+/**
+ * nss_ipsecmgr_flow_tuple
+ *	Flow information for the IPsec manager.
+ *
+ * Note: Zero out structure before filling the fields.
+ */
+struct nss_ipsecmgr_flow_tuple {
+	uint32_t src_ip[4];		/**< Source IP. */
+	uint32_t dest_ip[4];		/**< Destination IP. */
+	uint32_t spi_index;		/**< ESP SPI index for decapsulation flows. */
+	uint16_t sport;			/**< Source Port (unused). */
+	uint16_t dport;			/**< Destination Port (unused). */
+	uint8_t proto_next_hdr;		/**< Transport layer proto_next_hdr. */
+	uint8_t ip_version;		/**< IP version 4/6. */
+	uint8_t use_pattern;		/**< User defined flow identifier. */
+};
+
+/**
+ * nss_ipsecmgr_sa_stats
+ *	Security association statistics exported by the IPsec manager.
+ */
+struct nss_ipsecmgr_sa_stats {
+	struct nss_ipsecmgr_sa_tuple sa;	/**< Security association information. */
+	uint64_t seq_start;			/**< Starting sequence number. */
+	uint64_t seq_cur;			/**< Current sequence number. */
+	uint32_t pkt_bytes;			/**< Number of bytes processed. */
+	uint32_t pkt_count;			/**< Number of packets processed. */
+	uint32_t pkt_failed;			/**< Number of packets failed in processing. */
+	uint16_t window_size;			/**< Current size of the window. */
+	uint16_t replay_fail_alarm;		/**< Alarm for consecutive hash fail. */
+	uint32_t fail_replay_win;		/**< Failure in anti-replay; packet outside the window */
+	uint32_t fail_replay_dup;		/**< Failure in anti-replay; duplicate records */
+	uint32_t fail_auth;			/**< Failure in authenticating the data */
+};
+
+/**
+ * nss_ipsecmgr_event
+ *	Event information for the IPsec manager.
+ */
+struct nss_ipsecmgr_event {
+	enum nss_ipsecmgr_event_type type;		/**< Event type. */
+	union {
+		struct nss_ipsecmgr_sa_stats stats; 	/**< Security association statistics. */
+	} data;						/**< Event information. */
+};
+
+/**
+ * nss_ipsecmgr_sa_info
+ * 	Crypto information for an already created SA.
+ */
+struct nss_ipsecmgr_sa_info {
+	uint16_t session_idx;		/**< Crypto Session index */
+	uint16_t hdr_len;		/**< Encap header length */
+	uint16_t trailer_len;		/**< Encap Trailer length */
+	uint8_t blk_len;		/**< Cipher Block length */
+	uint8_t iv_len;			/**< Cipher IV lengh */
+	uint8_t hash_len;		/**< Hash lengh */
+	uint8_t res[3];			/**< Reserved */
+};
+
+/**
+ * nss_ipsecmgr_sa_cmn_init_keys
+ * 	Fill and initialize common information for SA creation with crypto keys.
+ *
+ * @datatypes
+ * nss_ipsecmgr_sa_cmn \n
+ * nss_ipsecmgr_algo \n
+ *
+ * @param[in/out] cmn       Pointer to the common IPsec manager SA configuration information.
+ * @param[in] algo          The AEAD algorithm combination.
+ * @param[in] cipher_key    Pointer to the cipher key.
+ * @param[in] cipher_keylen Cipher key length.
+ * @param[in] auth_key      Pointer to the authentication key.
+ * @param[in] auth_keylen   Authentication key length.
+ * @param[in] nonce         Pointer to the nonce.
+ * @param[in] nonce_size    Size of the nonce.
+ * @param[in] hash_len      Length of hash to be computed.
+ * @param[in] no_trailer    ESP trailer is required or not.
+ * @param[in] esn           Extended Sequence Number is required or not.
+ * @param[in] natt          NAT-T is required or not.
+ *
+ * @return
+ * Success or failure.
+ */
+static inline bool nss_ipsecmgr_sa_cmn_init_keys(struct nss_ipsecmgr_sa_cmn *cmn, enum nss_ipsecmgr_algo algo,
+						const uint8_t *cipher_key, uint16_t cipher_keylen,
+						const uint8_t *auth_key, uint16_t auth_keylen,
+						const uint8_t *nonce, uint16_t nonce_size, uint8_t hash_len,
+						bool no_trailer, bool esn, bool natt)
+{
+	if (algo >= NSS_IPSECMGR_ALGO_MAX)
+		return false;
+
+	if (cipher_keylen > NSS_IPSECMGR_CIPHER_KEYLEN_MAX)
+		return false;
+
+	if (auth_keylen > NSS_IPSECMGR_AUTH_KEYLEN_MAX)
+		return false;
+
+	if (nonce_size > NSS_IPSECMGR_NONCE_SIZE_MAX)
+		return false;
+
+	if (!cipher_key || !auth_key)
+		return false;
+
+	cmn->algo = algo;
+	cmn->keys.cipher_key = cipher_key;
+	cmn->keys.auth_key = auth_key;
+	cmn->keys.nonce = nonce;
+
+	cmn->keys.cipher_keylen = cipher_keylen;
+	cmn->keys.auth_keylen = auth_keylen;
+	cmn->keys.nonce_size = nonce_size;
+
+	cmn->icv_len = hash_len;
+	cmn->skip_trailer = no_trailer;
+	cmn->enable_esn = esn;
+	cmn->enable_natt = natt;
+
+	cmn->crypto_has_keys = true;
+	cmn->transport_mode = false;
+
+	return true;
+}
+
+/**
+ * nss_ipsecmgr_sa_cmn_init_idx
+ * 	Fill and initialize common information for SA creation with crypto index or secure offset.
+ *
+ * @datatypes
+ * nss_ipsecmgr_sa_cmn \n
+ * nss_ipsecmgr_algo \n
+ *
+ * @param[in/out] cmn    Pointer to the common IPsec manager SA configuration information.
+ * @param[in] algo       The AEAD algorithm combination.
+ * @param[in] crypto_idx Crypto session index to be associated with this context.
+ * @param[in] hash_len   Length of hash to be computed.
+ * @param[in] secure_key Keys used for cipher and authentication are secure or not.
+ * @param[in] no_trailer ESP trailer is required or not.
+ * @param[in] esn        Extended Sequence Number is required or not.
+ * @param[in] natt       NAT-T is required or not.
+ *
+ * @return
+ * Success or failure.
+ */
+static inline bool nss_ipsecmgr_sa_cmn_init_idx(struct nss_ipsecmgr_sa_cmn *cmn, enum nss_ipsecmgr_algo algo,
+						uint16_t crypto_idx,  uint8_t blk_len, uint8_t iv_len,
+						uint8_t hash_len, bool transport_mode, bool no_trailer, bool esn,
+						bool natt)
+{
+	if (algo >= NSS_IPSECMGR_ALGO_MAX)
+		return false;
+
+	cmn->algo = algo;
+	cmn->index.session = crypto_idx;
+	cmn->index.blk_len = blk_len;
+	cmn->index.iv_len = iv_len;
+
+	cmn->icv_len = hash_len;
+	cmn->enable_esn = esn;
+	cmn->enable_natt = natt;
+	cmn->skip_trailer = no_trailer;
+
+	cmn->crypto_has_keys = false;
+	cmn->transport_mode = transport_mode;
+
+	return true;
+}
+
+/**
+ * nss_ipsecmgr_sa_set_transport
+ * 	Enable transport mode for an SA thats is getting initialized.
+ *
+ * @datatypes
+ * nss_ipsecmgr_sa_cmn \n
+ *
+ * @param[in/out] cmn    Pointer to the common IPsec manager SA configuration information.
+ */
+static inline void nss_ipsecmgr_sa_set_transport(struct nss_ipsecmgr_sa_cmn *cmn)
+{
+	cmn->transport_mode = true;
+}
+
+#ifdef __KERNEL__ /* only kernel will use. */
+
+/**
+ * Callback function for receiving IPsec data.
+ *
+ * @datatypes
+ * sk_buff
+ *
+ * @param[in] app_data  Pointer to the application data.
+ * @param[in] skb       Pointer to the data socket buffer.
+ */
+typedef void (*nss_ipsecmgr_data_callback_t)(void *app_data, struct sk_buff *skb);
+
+/**
+ * Callback function for receiving IPsec events.
+ *
+ * @datatypes
+ * nss_ipsecmgr_event
+ *
+ * @param[in] app_data  Pointer to the application data.
+ * @param[in] ev        Pointer to the event.
+ */
+typedef void (*nss_ipsecmgr_event_callback_t)(void *app_data, struct nss_ipsecmgr_event *ev);
+
+/**
+ * nss_ipsecmgr_callback
+ *	Callback information.
+ */
+struct nss_ipsecmgr_callback {
+	void *app_data;				/**< Context of the caller. */
+	struct net_device *skb_dev;		/**< Net device to use for Socket Buffer. */
+	nss_ipsecmgr_data_callback_t data_cb;	/**< Data callback function. */
+	nss_ipsecmgr_event_callback_t event_cb;	/**< Event callback function. */
+	nss_ipsecmgr_data_callback_t except_cb; /**< Outer exception callback function. */
+};
+
+/**
+ * nss_ipsecmgr_tunnel_add
+ *	Adds a new IPsec tunnel.
+ *
+ * @datatypes
+ * nss_ipsecmgr_callback
+ *
+ * @param[in] cb  Pointer to the message callback.
+ *
+ * @return
+ * Linux NETDEVICE or NULL.
+ */
+struct net_device *nss_ipsecmgr_tunnel_add(struct nss_ipsecmgr_callback *cb);
+
+/**
+ * nss_ipsecmgr_tunnel_del
+ *	Deletes an existing IPsec tunnel.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] tun  Pointer to the network device associated with the tunnel.
+ *
+ * @return
+ * Success or failure.
+ */
+void nss_ipsecmgr_tunnel_del(struct net_device *tun);
+
+/**
+ * nss_ipsecmgr_sa_add
+ *	Adds a security association to the offload database.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_ipsecmgr_sa_tuple \n
+ * nss_ipsecmgr_sa_data \n
+ *
+ * @param[in] tun     Pointer to the network device associated with the tunnel.
+ * @param[in] sa      Pointer to tuple representing the SA.
+ * @param[in] data    Pointer to the security association data to add.
+ * @param[out] if_num Pointer to the IPsec inner or outer interface number.
+ *
+ * @return
+ * nss_ipsecmgr_status.
+ */
+nss_ipsecmgr_status_t nss_ipsecmgr_sa_add(struct net_device *tun, struct nss_ipsecmgr_sa_tuple *sa,
+				struct nss_ipsecmgr_sa_data *data, uint32_t *if_num);
+
+/**
+ * nss_ipsecmgr_sa_add_sync
+ *	Adds a security association to the offload database synchronously.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_ipsecmgr_sa_tuple \n
+ * nss_ipsecmgr_sa_data \n
+ *
+ * @param[in] tun     Pointer to the network device associated with the tunnel.
+ * @param[in] sa      Pointer to tuple representing the SA.
+ * @param[in] data    Pointer to the security association data to add.
+ * @param[out] if_num Pointer to the IPsec inner or outer interface number.
+ *
+ * @return
+ * nss_ipsecmgr_status.
+ */
+nss_ipsecmgr_status_t nss_ipsecmgr_sa_add_sync(struct net_device *tun, struct nss_ipsecmgr_sa_tuple *sa,
+				struct nss_ipsecmgr_sa_data *data, uint32_t *if_num);
+
+/**
+ * nss_ipsecmgr_sa_del
+ *	Deletes a security association.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_ipsecmgr_sa_tuple
+ *
+ * @param[in] tun   Pointer to the network device associated with the tunnel.
+ * @param[in] tuple Pointer to SA tuple to delete.
+ *
+ * @return
+ */
+void nss_ipsecmgr_sa_del(struct net_device *tun, struct nss_ipsecmgr_sa_tuple *tuple);
+
+/**
+ * nss_ipsecmgr_flow_add
+ *	Adds an encapsulation flow rule to the IPsec offload database.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_ipsecmgr_flow_tuple \n
+ * nss_ipsecmgr_sa_tuple
+ *
+ * @param[in] tun   Pointer to the network device associated with the tunnel.
+ * @param[in] flow  Pointer to the inner flow to add.
+ * @param[in] sa    Pointer to the outer flow of the SA to be added to.
+ *
+ * @return
+ * nss_ipsecmgr_status.
+ */
+nss_ipsecmgr_status_t nss_ipsecmgr_flow_add(struct net_device *tun, struct nss_ipsecmgr_flow_tuple *flow,
+					struct nss_ipsecmgr_sa_tuple *sa);
+
+/**
+ * nss_ipsecmgr_flow_add_sync
+ *	Adds an encapsulation flow rule to the IPsec offload database.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_ipsecmgr_flow_tuple \n
+ * nss_ipsecmgr_sa_tuple
+ *
+ * @param[in] tun   Pointer to the network device associated with the tunnel.
+ * @param[in] flow  Pointer to the inner flow to add.
+ * @param[in] sa    Pointer to the outer flow of the SA to be added to.
+ *
+ * @return
+ * nss_ipsecmgr_status.
+ */
+nss_ipsecmgr_status_t nss_ipsecmgr_flow_add_sync(struct net_device *tun, struct nss_ipsecmgr_flow_tuple *flow,
+					struct nss_ipsecmgr_sa_tuple *sa);
+
+/**
+ * nss_ipsecmgr_flow_del
+ *	Deletes an encapsulation flow rule from the IPsec offload database.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_ipsecmgr_flow_tuple \n
+ * nss_ipsecmgr_sa_tuple
+ *
+ * @param[in] tun   Pointer to the network device associated with the tunnel.
+ * @param[in] flow  Pointer to the inner flow to delete.
+ * @param[in] sa    Pointer to the SA tuple to be deleted from.
+ *
+ * @return
+ */
+void nss_ipsecmgr_flow_del(struct net_device *tun, struct nss_ipsecmgr_flow_tuple *flow,
+			struct nss_ipsecmgr_sa_tuple *sa);
+
+/**
+ * nss_ipsecmgr_flow_get_sa
+ *	Finds SA associated with given Flow.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_ipsecmgr_flow_tuple \n
+ * nss_ipsecmgr_sa_tuple
+ *
+ * @param[in] tun   Pointer to the network device associated with the tunnel.
+ * @param[in] flow  Pointer to the inner flow to look.
+ * @param[out] sa   Pointer to SA tuple to fill.
+ *
+ * @return
+ * nss_ipsecmgr_status.
+ */
+nss_ipsecmgr_status_t nss_ipsecmgr_flow_get_sa(struct net_device *tun, struct nss_ipsecmgr_flow_tuple *flow,
+					struct nss_ipsecmgr_sa_tuple *sa);
+
+/*
+ * nss_ipsecmgr_sa_verify()
+ * 	Check if SA is present.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_ipsecmgr_sa_tuple
+ *
+ * @param[in] tun  Pointer to the network device associated with the tunnel.
+ * @param[in] sa   Pointer to SA tuple to use for tx.
+ *
+ * @return
+ * Returns true if the SA is present.
+ */
+bool nss_ipsecmgr_sa_verify(struct net_device *tun, struct nss_ipsecmgr_sa_tuple *sa);
+
+/*
+ * nss_ipsecmgr_sa_tx_inner()
+ * 	Offload given SKB to NSS for inner processing.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_ipsecmgr_sa_tuple \n
+ * sk_buff
+ *
+ * @param[in] tun  Pointer to the network device associated with the tunnel.
+ * @param[in] sa   Pointer to SA tuple to use for tx.
+ * @param[in] skb  Pointer to SKB to be offload.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+nss_ipsecmgr_status_t nss_ipsecmgr_sa_tx_inner(struct net_device *tun, struct nss_ipsecmgr_sa_tuple *sa,
+                                        struct sk_buff *skb);
+
+/*
+ * nss_ipsecmgr_sa_tx_outer()
+ * 	Offload given SKB to NSS for outer processing.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_ipsecmgr_sa_tuple \n
+ * sk_buff
+ *
+ * @param[in] tun  Pointer to the network device associated with the tunnel.
+ * @param[in] sa   Pointer to SA tuple to use for tx.
+ * @param[in] skb  Pointer to SKB to be offload.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+nss_ipsecmgr_status_t nss_ipsecmgr_sa_tx_outer(struct net_device *tun, struct nss_ipsecmgr_sa_tuple *sa,
+                                        struct sk_buff *skb);
+
+/*
+ * nss_ipsecmgr_cra_name2algo()
+ * 	Get ipsecmgr algo from cra name.
+ *
+ * @param[in] cra_name  Name of the crypto algo.
+ *
+ * @return
+ * nss_ipsecmgr_algo
+ */
+enum nss_ipsecmgr_algo nss_ipsecmgr_cra_name2algo(const char *cra_name);
+
+/*
+ * nss_ipsecmgr_sa_get_info()
+ * 	Get Crypto information for an already created SA.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_ipsecmgr_sa_tuple \n
+ * nss_ipsecmgr_sa_info
+ *
+ * @param[in] tun   Pointer to the network device associated with the tunnel.
+ * @param[in] sa    Pointer to the SA tuple for which info is to be retrieved.
+ * @param[out] info Pointer to the SA info to fill.
+ *
+ * @return
+ * Success or failure.
+ */
+bool nss_ipsecmgr_sa_get_info(struct net_device *tun, struct nss_ipsecmgr_sa_tuple *sa,
+			struct nss_ipsecmgr_sa_info *info);
+
+#endif /* __KERNEL__ */
+#endif /* __NSS_IPSECMGR_H */
diff --git a/qca-nss-clients/exports/nss_l2tpmgr.h b/qca-nss-clients/exports/nss_l2tpmgr.h
new file mode 100644
index 0000000..7595924
--- /dev/null
+++ b/qca-nss-clients/exports/nss_l2tpmgr.h
@@ -0,0 +1,81 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, 2021 The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#ifndef __NSS_L2TPMGR_H__
+#define __NSS_L2TPMGR_H__
+
+typedef int32_t (*get_ipsec_ifnum_by_dev_callback_t)(struct net_device *);
+typedef int32_t (*get_ipsec_ifnum_by_ipv4_addr_callback_t)(uint32_t *src_ip, uint32_t *dest_ip);
+
+/**
+ * l2tpmgr_ipsecmgr_cb
+ *	Callback to get the dummy IPSec interface number that was used to register with NSS
+ *	by the IPSec manager when given the IPSec Linux dev.
+ *	get_ifnum_by_dev: passes net_device ptr to get associated IPsec if_num in KLIPS
+ *	get_ifnum_by_ipv4_addr: passes IPv4 src & dest addr in Big-endian form to get IPsec if_num in XFRM
+ */
+struct l2tpmgr_ipsecmgr_cb {
+	get_ipsec_ifnum_by_dev_callback_t get_ifnum_by_dev;
+	get_ipsec_ifnum_by_ipv4_addr_callback_t get_ifnum_by_ipv4_addr;
+};
+
+#if defined(NSS_L2TP_IPSEC_BIND_BY_NETDEV)
+/**
+ * l2tpmgr_register_ipsecmgr_callback_by_netdev
+ * 	Register IPSecmgr callback function with l2tpmgr by netdev for KLIPS.
+ *
+ * @datatypes
+ * l2tpmgr_ipsecmgr_cb \n
+ *
+ * @param[in] cb    IPSecmgr callback function to be registered with l2tpmgr.
+ *
+ * @return
+ * none
+ */
+void l2tpmgr_register_ipsecmgr_callback_by_netdev(struct l2tpmgr_ipsecmgr_cb *cb);
+
+/**
+ * l2tpmgr_unregister_ipsecmgr_callback
+ * 	Unregister IPSecmgr callback function with l2tpmgr by netdev for KLIPS.
+ *
+ * @return
+ * none
+ */
+void l2tpmgr_unregister_ipsecmgr_callback_by_netdev(void);
+#endif
+
+/**
+ * l2tpmgr_register_ipsecmgr_callback_by_ipaddr
+ * 	Register IPSecmgr callback function with l2tpmgr by IP address for XFRM.
+ *
+ * @datatypes
+ * l2tpmgr_ipsecmgr_cb \n
+ *
+ * @param[in] cb    IPSecmgr callback function to be registered with l2tpmgr.
+ *
+ * @return
+ * none
+ */
+void l2tpmgr_register_ipsecmgr_callback_by_ipaddr(struct l2tpmgr_ipsecmgr_cb *cb);
+
+/**
+ * l2tpmgr_unregister_ipsecmgr_callback_by_ipaddr
+ * 	Unregister IPSecmgr callback function with l2tpmgr by IP address for XFRM.
+ *
+ * @return
+ * none
+ */
+void l2tpmgr_unregister_ipsecmgr_callback_by_ipaddr(void);
+#endif
diff --git a/qca-nss-clients/exports/nss_match_user.h b/qca-nss-clients/exports/nss_match_user.h
new file mode 100644
index 0000000..e59f3a5
--- /dev/null
+++ b/qca-nss-clients/exports/nss_match_user.h
@@ -0,0 +1,115 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_match_get_ifnum_by_table_index
+ * 	Returns match interface number given table index.
+ *
+ * @param[in] table_id  Table ID of match instance.
+ *
+ * @return
+ * Interface number of match instance, return -1 on failure.
+ */
+extern int nss_match_get_ifnum_by_table_id(uint32_t table_id);
+
+/**
+ * nss_match_vow_rule_add
+ * 	Add the VoW rule to the configured match instance.
+ *
+ * @datatype
+ * nss_ctx_instance \n
+ * nss_match_rule_vow_msg
+ *
+ * @param[in] nss_ctx   Pointer to NSS core context.
+ * @param[in] rule_msg  Pointer to VoW rule message.
+ * @param[in] table_id  Table ID of match instance.
+ *
+ * @return
+ * Rule ID of rule added, returns -1 on failure.
+ */
+extern int nss_match_vow_rule_add(struct nss_ctx_instance *nss_ctx, struct nss_match_rule_vow_msg *rule_msg, uint32_t table_id);
+
+/**
+ * nss_match_l2_rule_add
+ * 	Add the l2 rule to the configured match instance.
+ *
+ * @datatype
+ * nss_ctx_instance \n
+ * nss_match_rule_l2_msg
+ *
+ * @param[in] nss_ctx   Pointer to NSS core context.
+ * @param[in] rule_msg  Pointer to L2 rule message.
+ * @param[in] table_id  Table ID of match instance.
+ *
+ * @return
+ * Rule ID of rule added, returns -1 on failure.
+ */
+extern int nss_match_l2_rule_add(struct nss_ctx_instance *nss_ctx, struct nss_match_rule_l2_msg *rule_msg, uint32_t table_id);
+
+/**
+ * nss_match_rule_delete
+ * 	Deletes the rule from match instance.
+ *
+ * @datatype
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to NSS core context.
+ * @param[in] rule_id  Rule ID of match rule.
+ * @param[in] table_id Table ID of match instance.
+ *
+ * @return
+ * Error status of rule deletion.
+ */
+extern nss_match_status_t nss_match_rule_delete(struct nss_ctx_instance *nss_ctx, uint32_t rule_id, uint32_t table_id);
+
+/**
+ * nss_match_profile_configure
+ * 	Configures the match instance.
+ *
+ * @datatype
+ * nss_ctx_instance \n
+ * nss_match_profile_configure_msg
+ *
+ * @param[in] nss_ctx    Pointer to NSS core context.
+ * @param[in] config_msg Match message for configuration.
+ * @param[in] table_id   Table ID of match instance.
+ *
+ * @return
+ * Error status of configuration.
+ */
+extern nss_match_status_t nss_match_profile_configure(struct nss_ctx_instance *nss_ctx, struct nss_match_profile_configure_msg *config_msg, uint32_t table_id);
+
+/**
+ * nss_match_instance_create
+ * 	Creates the match instance.
+ *
+ * @return
+ * Table ID of match instance created, returns -1 on failure.
+ */
+extern int32_t nss_match_instance_create(void);
+
+/**
+ * nss_match_instance_destroy
+ * 	Deletes the match instance.
+ *
+ * @param[in] table_id  Table ID of match instance.
+ *
+ * @return
+ * Error status of deletion.
+ */
+extern nss_match_status_t nss_match_instance_destroy(uint32_t table_id);
diff --git a/qca-nss-clients/exports/nss_mirror_public.h b/qca-nss-clients/exports/nss_mirror_public.h
new file mode 100644
index 0000000..de3e227
--- /dev/null
+++ b/qca-nss-clients/exports/nss_mirror_public.h
@@ -0,0 +1,131 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+/**
+ * nss_mirror_public.h
+ *	NSS Mirror interface definitions.
+ */
+#ifndef __NSS_MIRROR_H
+#define __NSS_MIRROR_H
+
+#include <nss_api_if.h>
+
+/**
+ * nss_mirror_disable
+ *	API to send disable message to mirror interface in NSS firmware.
+ *
+ * @datatypes
+ * struct net_device \n
+ *
+ * @param[in] mirror_dev  Mirror netdevice pointer.
+ *
+ * @return
+ * Return 0 on success, -1 on failure.
+ */
+extern int nss_mirror_disable(struct net_device *mirror_dev);
+
+/**
+ * nss_mirror_enable
+ *	API to send enable message to mirror interface in NSS firmware.
+ *
+ * @datatypes
+ * struct net_device \n
+ *
+ * @param[in] mirror_dev  Mirror netdevice pointer.
+ *
+ * @return
+ * Return 0 on success, -1 on failure.
+ */
+extern int nss_mirror_enable(struct net_device *mirror_dev);
+
+/**
+ * nss_mirror_set_nexthop
+ *	API to send set nexthop message to mirror interface in NSS firmware.
+ *
+ * @datatypes
+ * struct net_device \n
+ *
+ * @param[in] mirror_dev       Mirror netdevice pointer.
+ * @param[in] mirror_next_hop  Nexthop interface number.
+ *
+ * @return
+ * Return 0 on success, -1 on failure.
+ */
+extern int nss_mirror_set_nexthop(struct net_device *mirror_dev, int32_t mirror_next_hop);
+
+/**
+ * nss_mirror_reset_nexthop
+ *	API to send reset nexthop message to mirror interface in NSS firmware.
+ *
+ * @datatypes
+ * struct net_device \n
+ *
+ * @param[in] mirror_dev  Mirror netdevice pointer.
+ *
+ * @return
+ * Return 0 on success, -1 on failure.
+ */
+extern int nss_mirror_reset_nexthop(struct net_device *mirror_dev);
+
+/**
+ * nss_mirror_configure
+ *	API to send configure message to mirror interface in NSS firmware.
+ *
+ * @datatypes
+ * struct net_device \n
+ * nss_mirror_pkt_clone_point \n
+ *
+ * @param[in] mirror_dev        Mirror netdevice pointer.
+ * @param[in] pkt_clone_point   Point in the packet to copy from.
+ * @param[in] pkt_clone_size    Number of bytes to copy.
+ * @param[in] pkt_clone_offset  Copy offset.
+ *
+ * @return
+ * Return 0 on success, -1 on failure.
+ */
+extern int nss_mirror_configure(struct net_device *mirror_dev, enum nss_mirror_pkt_clone_point pkt_clone_point,
+		 uint16_t pkt_clone_size, uint16_t pkt_clone_offset);
+
+/**
+ * nss_mirror_destroy
+ *	API to de-register and delete mirror interface.
+ *
+ * @datatypes
+ * struct net_device \n
+ *
+ * @param[in] mirror_dev  Mirror netdevice pointer.
+ *
+ * @return
+ * Return 0 on success, -1 on failure.
+ */
+extern int nss_mirror_destroy(struct net_device *mirror_dev);
+
+/**
+ * nss_mirror_create
+ *	API to create and register mirror interface.
+ *
+ * @datatypes
+ * struct net_device \n
+ *
+ * @return
+ * Return pointer of the newly created device.
+ */
+
+extern struct net_device *nss_mirror_create(void);
+
+#endif /* __NSS_MIRROR_H */
diff --git a/qca-nss-clients/exports/nss_ovpn_sk.h b/qca-nss-clients/exports/nss_ovpn_sk.h
new file mode 100644
index 0000000..da12dc3
--- /dev/null
+++ b/qca-nss-clients/exports/nss_ovpn_sk.h
@@ -0,0 +1,200 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_ovpn_sk.h
+ *	NSS OpenVPN (OVPN) Manager interface definitions.
+ */
+
+#ifndef _NSS_OVPN_SK_H_
+#define _NSS_OVPN_SK_H_
+
+#define NSS_OVPN_SK_CIPHER_KEYLEN_MAX   32
+#define NSS_OVPN_SK_AUTH_KEYLEN_MAX     32
+
+/*
+ * OVPN flags which define encapsulation header parameters.
+ */
+#define NSS_OVPN_SK_OVPN_HDR_FLAG_IPv6 0x1		/* Outer IP header is IPv6. */
+#define NSS_OVPN_SK_OVPN_HDR_FLAG_SHARED_KEY 0x2	/* Tunnel is established with shared key. */
+#define NSS_OVPN_SK_OVPN_HDR_FLAG_NO_IV 0x4		/* Do not transmit IV in data packet. */
+#define NSS_OVPN_SK_OVPN_HDR_FLAG_NO_AUTH 0x8		/* No HMAC Calculation. */
+#define NSS_OVPN_SK_OVPN_HDR_FLAG_NO_CIPHER 0x10	/* No Crypto operation. */
+#define NSS_OVPN_SK_OVPN_HDR_FLAG_FRAG 0x20		/* OpenVPN Fragmentation is enabled. */
+#define NSS_OVPN_SK_OVPN_HDR_FLAG_DISABLE_REPLAY 0x40	/* Disable replay attack check. */
+#define NSS_OVPN_SK_OVPN_HDR_FLAG_PID_LONG_FMT 0x80	/* Use long packet id: <sequence number><current time> */
+#define NSS_OVPN_SK_OVPN_HDR_FLAG_DATA_V2 0x100		/* Data packet type is V2, peer_id is valid */
+#define NSS_OVPN_SK_OVPN_HDR_FLAG_INHERIT_TOS 0x200	/* Copy TOS from inner to outer. */
+#define NSS_OVPN_SK_OVPN_HDR_FLAG_L4_PROTO_TCP 0x400	/* OpenVPN tunnel is TCP. */
+#define NSS_OVPN_SK_OVPN_HDR_FLAG_PEER_DATA_V2 0x800	/* Peer is configured to transmit V2 data packets. */
+
+/*
+ * Packet offload flags
+ */
+#define NSS_OVPN_SK_PKT_INFO_FLAG_DIR_DECAP 0x1		/* Encapsulate. */
+#define NSS_OVPN_SK_PKT_INFO_FLAG_PKT_TYPE_IPV6 0x2	/* IPv6 packet. */
+#define NSS_OVPN_SK_PKT_INFO_FLAG_PKT_TYPE_CTRL 0x4	/* Control packets in data channel. */
+
+/*
+ * OVPN socket ioctl options
+ */
+enum nss_ovpn_sk_sioc {
+	NSS_OVPN_SK_SIOC_APP_REG = SIOCPROTOPRIVATE,	/* Command to register OVPN application. */
+	NSS_OVPN_SK_SIOC_APP_DEREG,			/* Command to deregister OVPN application. */
+	NSS_OVPN_SK_SIOC_TUN_ADD,			/* Command to add tunnel. */
+	NSS_OVPN_SK_SIOC_TUN_DEL,			/* Command to delete tunnel. */
+	NSS_OVPN_SK_SIOC_ROUTE_ADD,			/* Command to add route. */
+	NSS_OVPN_SK_SIOC_ROUTE_DEL,			/* Command to delete route. */
+	NSS_OVPN_SK_SIOC_ROUTE_STATE_GET,		/* Command to get route state. */
+	NSS_OVPN_SK_SIOC_CRYPTO_KEY_ADD,		/* Command to add crypto key. */
+	NSS_OVPN_SK_SIOC_CRYPTO_KEY_DEL,		/* Command to delete crypto key. */
+	NSS_OVPN_SK_SIOC_STATS_GET			/* Command to get tunnel statistics. */
+};
+
+/*
+ * Application modes.
+ */
+enum nss_ovpn_sk_app_mode {
+	NSS_OVPN_SK_APP_MODE_CLIENT = 1,	/* Application mode is client. */
+	NSS_OVPN_SK_APP_MODE_SERVER = 2		/* Application mode is server. */
+};
+
+/*
+ * NSS OVPN manager supported crypto algorithms
+ */
+enum nss_ovpn_sk_algo {
+	NSS_OVPN_SK_ALGO_AES_CBC_SHA1_HMAC,		/* AEAD  - AES_CBC_SHA1_HMAC */
+	NSS_OVPN_SK_ALGO_AES_CBC_SHA256_HMAC,		/* AEAD  - AES_CBC_SHA256_HMAC */
+	NSS_OVPN_SK_ALGO_3DES_CBC_SHA1_HMAC,		/* AEAD  - 3DES_CBC_SHA1_HMAC */
+	NSS_OVPN_SK_ALGO_3DES_CBC_SHA256_HMAC,		/* AEAD  - 3DES_CBC_SHA256_HMAC */
+	NSS_OVPN_SK_ALGO_NULL_CIPHER_SHA1_HMAC,		/* AHASH - SHA1_HMAC */
+	NSS_OVPN_SK_ALGO_NULL_CIPHER_SHA256_HMAC,	/* AHASH - SHA256_HMAC */
+	NSS_OVPN_SK_ALGO_AES_CBC_NULL_AUTH,		/* ABLK  - AES_CBC */
+	NSS_OVPN_SK_ALGO_3DES_CBC_NULL_AUTH,		/* ABLK  - 3DES_CBC */
+	NSS_OVPN_SK_ALGO_NULL_CIPHER_NULL_AUTH,		/* Crypto is not enabled. */
+	NSS_OVPN_SK_ALGO_MAX
+};
+
+/*
+ * nss_ovpn_sk_ovpn_params
+ * 	OVPN header parameters.
+ */
+struct nss_ovpn_sk_ovpn_params {
+	uint32_t flags;	/* OpenVPN configuration flags. */
+	int32_t peer_id;			/* Peer id, maximum size is 24 bits. */
+	uint32_t tunnel_id;			/* Tunnel ID, generated to identify tunnel info. */
+};
+
+/*
+ * nss_ovpn_sk_tunnel_hdr
+ * 	Tunnel header parameters - IPv4/v6 and udp header parameters.
+ */
+struct nss_ovpn_sk_tunnel_hdr {
+	uint32_t src_ip[4];	/* IPv4/v6 source ip address. */
+	uint32_t dst_ip[4];	/* IPv4/v6 destination ip address. */
+	uint16_t src_port;	/* UDP source port. */
+	uint16_t dst_port;	/* UDP destination port. */
+	uint8_t hop_limit;	/* TTL or next hop limit. */
+	uint8_t res[3];		/* Reserved for Alignment. */
+};
+
+/*
+ * nss_ovpn_sk_crypto_key
+ *	Crypto keys.
+ */
+struct nss_ovpn_sk_crypto_key {
+	uint8_t cipher_key[NSS_OVPN_SK_CIPHER_KEYLEN_MAX];	/* Cipher key */
+	uint8_t hmac_key[NSS_OVPN_SK_AUTH_KEYLEN_MAX];		/* HMAC key */
+};
+
+/*
+ * nss_ovpn_sk_crypto_params
+ *	Crypto configuration parameters.
+ */
+struct nss_ovpn_sk_crypto_params {
+	enum nss_ovpn_sk_algo algo;	/* Crypto algorithm. */
+	uint16_t cipher_key_size;	/* Cipher key size. */
+	uint16_t hmac_key_size;		/* HMAC Key size. */
+};
+
+/*
+ * nss_ovpn_sk_crypto_session
+ *	Crypto session parameters parameters.
+ */
+struct nss_ovpn_sk_crypto_session {
+	uint32_t tunnel_id;				/* OVPN tunnel id. */
+	uint8_t key_id;					/* Crypto key id */
+	struct nss_ovpn_sk_crypto_params config;	/* Crytpto configuration parameters. */
+	struct nss_ovpn_sk_crypto_key encrypt;		/* Encryption/HMAC keys */
+	struct nss_ovpn_sk_crypto_key decrypt;		/* Decryption/HMAC keys */
+};
+
+/*
+ * nss_ovpn_sk_route_info
+ *	Route configuration information.
+ */
+struct nss_ovpn_sk_route_info {
+	uint32_t tunnel_id;	/* Tunnel id. */
+	uint8_t ip_version;	/* IPv4/v6 version. */
+	uint32_t ip_network[4];	/* IPv4/v6 network. */
+	uint32_t netmask_bits;	/* Network mask bits. */
+};
+
+/*
+ * nss_ovpn_sk_pkt_info
+ *	Packet offload details.
+ */
+struct nss_ovpn_sk_pkt_info {
+	uint32_t tunnel_id;			/* Tunnel id. */
+	uint32_t flags;	/* Packet info flags. */
+};
+
+/*
+ * nss_ovpn_sk_tunnel
+ *	Tunnel configuration parameters.
+ */
+struct nss_ovpn_sk_tunnel {
+	struct nss_ovpn_sk_ovpn_params ovpn;		/* OVPN tunnel parameters which define encap header parameters. */
+	struct nss_ovpn_sk_tunnel_hdr tun_hdr;		/* Tunnel header parameters. */
+	struct nss_ovpn_sk_crypto_session crypto;	/* Crypto parameters. */
+};
+
+/*
+ * nss_ovpn_sk_app_inst
+ * 	Register application with OVPN Manager.
+ */
+struct nss_ovpn_sk_app_inst {
+	char tun_dev[IFNAMSIZ];			/* Tun/tap device name. */
+	pid_t pid;				/* PID of the application. */
+	int tun_fd;				/* Tun/tap device fd. */
+	int udp_fd;				/* UDP socket fd. */
+	enum nss_ovpn_sk_app_mode app_mode;	/* Application mode. */
+};
+
+/*
+ * nss_ovpn_sk_tun_stats
+ *	Statistics.
+ */
+struct nss_ovpn_sk_tun_stats {
+	uint32_t tunnel_id;			/* Tunnel id. */
+	unsigned int tun_read_bytes;		/* Total number of bytes read from tun/tap device. */
+	unsigned int tun_write_bytes;		/* Total number of bytes written to tun/tap device. */
+	unsigned int link_read_bytes;		/* Total number of bytes read from UDP socket. */
+	unsigned int link_read_bytes_auth;	/* Total number of bytes authenticated from UDP socket. */
+	unsigned int link_write_bytes;		/* Total number of bytes written to UDP socket. */
+};
+
+#endif /* _NSS_OVPN_SK_H_ */
diff --git a/qca-nss-clients/exports/nss_ovpnmgr.h b/qca-nss-clients/exports/nss_ovpnmgr.h
new file mode 100644
index 0000000..737949c
--- /dev/null
+++ b/qca-nss-clients/exports/nss_ovpnmgr.h
@@ -0,0 +1,189 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_ovpnmgr.h
+ *	NSS OpenVPN (OVPN) Manager interface definitions.
+ */
+
+#ifndef _NSS_OVPNMGR_H_
+#define _NSS_OVPNMGR_H_
+
+#define NSS_OVPNMGR_CIPHER_KEYLEN_MAX 32
+#define NSS_OVPNMGR_AUTH_KEYLEN_MAX 32
+#define NSS_OVPNMGR_NONCE_SIZE_MAX 4
+/*
+ * TODO: Need to implement communication between NSS FW and OVPN manager
+ * to get offload capabilities. Maximum number of tunnels supported is one of
+ * the capabilities
+ */
+#define NSS_OVPNMGR_TUNNEL_MAX 32
+#define NSS_OVPNMGR_PEER_ID_MAX (1 << 24)
+/*
+ * Maximum headroom size
+ *	EDMA_PRE_HDR(32) + Ethernet (14) + VLAN (8) + PPPoE (8) + IPv6 (40) + UDP (8) + OVPN_HDR(4) +
+ *	HMAC_HASH(32) + PACKET_ID (4)
+ */
+#define NSS_OVPNMGR_TUN_HEADROOM 192		/* Headroom needed for encapsulation. */
+#define NSS_OVPNMGR_TUN_TAILROOM 256		/* Tailroom needed for decapsulation. */
+
+/*
+ * OpenVPN protocol definitions
+ */
+#define NSS_OVPNMGR_TUN_DATA_V1       6		/* Data version 1 packet. */
+#define NSS_OVPNMGR_TUN_DATA_V2       9		/* Data version 2 packet. */
+#define NSS_OVPNMGR_TUN_KEY_ID_SHIFT  24	/* Key ID shift, lower 3 bits - 26-24. */
+#define NSS_OVPNMGR_TUN_OPCODE_SHIFT  27	/* Opcode shift, upper 5 bits - 31-27. */
+#define NSS_OVPNMGR_TUN_PEER_ID_MASK  0xFFFFFF	/* Peer ID mask. */
+
+
+/*
+ * OVPN flags which define encapsulation header parameters.
+ */
+#define NSS_OVPNMGR_HDR_FLAG_IPV6 0x0001		/* Outer IP header is IPv6. */
+#define NSS_OVPNMGR_HDR_FLAG_SHARED_KEY 0x0002		/* Tunnel is established with shared key. */
+#define NSS_OVPNMGR_HDR_FLAG_NO_IV 0x0004		/* Do not transmit IV in data packet. */
+#define NSS_OVPNMGR_HDR_FLAG_NO_AUTH 0x0008		/* No HMAC Calculation. */
+#define NSS_OVPNMGR_HDR_FLAG_NO_CIPHER 0x0010		/* No Crypto operation. */
+#define NSS_OVPNMGR_HDR_FLAG_FRAG 0x0020		/* OpenVPN Fragmentation is enabled. */
+#define NSS_OVPNMGR_HDR_FLAG_NO_REPLAY 0x0040		/* Disable replay attack check. */
+#define NSS_OVPNMGR_HDR_FLAG_PID_LONG_FMT 0x0080	/* Use long packet id: <sequence number><current time> */
+#define NSS_OVPNMGR_HDR_FLAG_DATA_V2 0x0100		/* Data packet type is V2, peer_id is valid */
+#define NSS_OVPNMGR_HDR_FLAG_COPY_TOS 0x0200		/* Copy TOS from inner to outer. */
+#define NSS_OVPNMGR_HDR_FLAG_L4_PROTO_TCP 0x0400	/* OpenVPN tunnel is TCP. */
+#define NSS_OVPNMGR_HDR_FLAG_PEER_DATA_V2 0x0800	/* Peer is configured to transmit V2 data packets. */
+
+/*
+ * Packet offload flags
+ */
+#define NSS_OVPNMGR_METADATA_FLAG_PKT_DECAP 0x1		/* Decapsulate. */
+#define NSS_OVPNMGR_METADATA_FLAG_PKT_TYPE_IPV6 0x2	/* IPv6 packet. */
+#define NSS_OVPNMGR_METADATA_FLAG_PKT_TYPE_CTRL 0x4	/* Control packets in data channel. */
+
+/*
+ * Application modes.
+ */
+enum nss_ovpnmgr_app_mode {
+	NSS_OVPNMGR_APP_MODE_CLIENT = 1,	/* Application mode is client. */
+	NSS_OVPNMGR_APP_MODE_SERVER = 2		/* Application mode is server. */
+};
+
+/*
+ * NSS OVPN manager supported crypto algorithms
+ */
+enum nss_ovpnmgr_algo {
+	NSS_OVPNMGR_ALGO_AES_CBC_SHA1_HMAC,		/* AEAD  - AES_CBC_SHA1_HMAC */
+	NSS_OVPNMGR_ALGO_AES_CBC_SHA256_HMAC,		/* AEAD  - AES_CBC_SHA256_HMAC */
+	NSS_OVPNMGR_ALGO_3DES_CBC_SHA1_HMAC,		/* AEAD  - 3DES_CBC_SHA1_HMAC */
+	NSS_OVPNMGR_ALGO_3DES_CBC_SHA256_HMAC,		/* AEAD  - 3DES_CBC_SHA256_HMAC */
+	NSS_OVPNMGR_ALGO_NULL_CIPHER_SHA1_HMAC,		/* AHASH - SHA1_HMAC */
+	NSS_OVPNMGR_ALGO_NULL_CIPHER_SHA256_HMAC,	/* AHASH - SHA256_HMAC */
+	NSS_OVPNMGR_ALGO_AES_CBC_NULL_AUTH,		/* ABLK  - AES_CBC */
+	NSS_OVPNMGR_ALGO_3DES_CBC_NULL_AUTH,		/* ABLK  - 3DES_CBC */
+	NSS_OVPNMGR_ALGO_NULL_CIPHER_NULL_AUTH,		/* Crypto is not enabled. */
+	NSS_OVPNMGR_ALGO_MAX
+};
+
+/*
+ * nss_ovpnmgr_route_tuple
+ *	Route tuple for configuration of host based route (cache).
+ */
+struct nss_ovpnmgr_route_tuple {
+	uint32_t ip_addr[4];	/* IPv4/v6 address. */
+	uint8_t ip_version;	/* IPv4/v6 version. */
+};
+
+/*
+ * nss_ovpnmgr_crypto_key
+ */
+struct nss_ovpnmgr_crypto_key {
+	uint8_t cipher_key[NSS_OVPNMGR_CIPHER_KEYLEN_MAX];	/* Cipher key */
+	uint8_t hmac_key[NSS_OVPNMGR_AUTH_KEYLEN_MAX];		/* HMAC key */
+	uint8_t nonce[NSS_OVPNMGR_NONCE_SIZE_MAX];		/* Cryptographic nonse. */
+	uint16_t cipher_keylen;					/* Cipher key size. */
+	uint16_t hmac_keylen;					/* HMAC Key size. */
+};
+
+/*
+ * nss_ovpnmgr_crypto_config
+ */
+struct nss_ovpnmgr_crypto_config {
+	struct nss_ovpnmgr_crypto_key encrypt;	/* Encryption/HMAC keys */
+	struct nss_ovpnmgr_crypto_key decrypt;	/* Decryption/HMAC keys */
+	enum nss_ovpnmgr_algo algo;		/* Crypto algorithm. */
+};
+
+/*
+ * nss_ovpnmgr_tun_config
+ *	OVPN header configuration parameters.
+ */
+struct nss_ovpnmgr_tun_config {
+	uint32_t flags;		/* OpenVPN configuration flags. */
+	uint32_t peer_id;	/* Peer id, maximum size is 24 bits. */
+};
+
+/*
+ * nss_ovpnmgr_metadata
+ *	Metadata for sending/receiving packet to/from applcation.
+ */
+struct nss_ovpnmgr_metadata {
+	uint32_t flags;		/* Packet offload flags */
+	uint32_t tunnel_id;	/* OVPN tunnel ID. */
+};
+
+/*
+ * nss_ovpnmgr_tun_stats
+ *	OVPN tunnel statistics maintained by application.
+ */
+struct nss_ovpnmgr_tun_stats {
+	uint32_t tun_read_bytes;	/* Bytes (pkts * sizeof(each pkt)) from tun/tap device. */
+	uint32_t tun_write_bytes;	/* Bytes (pkts * sizeof(each pkt)) to tun/tap device. */
+	uint32_t link_read_bytes;	/* Bytes (pkts * sizeof(each pkt)) from UDP socket. */
+	uint32_t link_read_bytes_auth;	/* Bytes (pkts * sizeof(each pkt)) from UDP socket and authenticated. */
+	uint32_t link_write_bytes;	/* Bytes (pkts * sizeof(each pkt)) to UDP socket. */
+};
+
+/*
+ * nss_ovpnmgr_tun_tuple
+ *	Tunnel header parameters - IPv4/v6 and udp header parameters.
+ */
+struct nss_ovpnmgr_tun_tuple {
+	uint32_t src_ip[4];	/* IPv4/v6 source ip address. */
+	uint32_t dst_ip[4];	/* IPv4/v6 destination ip address. */
+	uint16_t src_port;	/* UDP source port. */
+	uint16_t dst_port;	/* UDP destination port. */
+	uint8_t hop_limit;	/* TTL or next hop limit. */
+	uint8_t res[3];		/* Reserved for Alignment. */
+};
+
+int nss_ovpnmgr_app_add(struct net_device *app_dev, enum nss_ovpnmgr_app_mode mode, void *app_data);
+int nss_ovpnmgr_app_del(struct net_device *app_dev);
+struct net_device *nss_ovpnmgr_app_find_tun(struct net_device *app_dev, struct nss_ovpnmgr_route_tuple *rt, uint32_t *ifnum);
+
+uint32_t nss_ovpnmgr_tun_add(struct net_device *app_dev, struct nss_ovpnmgr_tun_tuple *tuple,
+		struct nss_ovpnmgr_tun_config *tun_cfg, struct nss_ovpnmgr_crypto_config *crypto_cfg);
+int nss_ovpnmgr_tun_del(uint32_t tunnel_id);
+int nss_ovpnmgr_tun_tx(uint32_t tunnel_id, struct nss_ovpnmgr_metadata *mdata, struct sk_buff *skb);
+void nss_ovpnmgr_tun_route_update(uint32_t tunnel_id, uint32_t *from_addr, uint32_t *to_addr, int version);
+int nss_ovpnmgr_tun_stats_get(uint32_t tunnel_id, struct nss_ovpnmgr_tun_stats *stats);
+
+int nss_ovpnmgr_crypto_key_add(uint32_t tunnel_id, uint8_t key_id, struct nss_ovpnmgr_crypto_config *crypto_cfg);
+int nss_ovpnmgr_crypto_key_del(uint32_t tunnel_id);
+
+int nss_ovpnmgr_route_add(uint32_t tunnel_id, struct nss_ovpnmgr_route_tuple *route);
+int nss_ovpnmgr_route_del(uint32_t tunnel_id, struct nss_ovpnmgr_route_tuple *route);
+bool nss_ovpnmgr_route_is_active(uint32_t tunnel_id, struct nss_ovpnmgr_route_tuple *route);
+#endif /*_NSS_OVPNMGR_H_ */
diff --git a/qca-nss-clients/exports/nss_pvxlanmgr.h b/qca-nss-clients/exports/nss_pvxlanmgr.h
new file mode 100644
index 0000000..ea8390c
--- /dev/null
+++ b/qca-nss-clients/exports/nss_pvxlanmgr.h
@@ -0,0 +1,203 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_pvxlanmgr.h
+ *	Proxy VxLAN manager for NSS
+ */
+#ifndef __NSS_PVXLANMGR_H
+#define __NSS_PVXLANMGR_H
+
+/*
+ * Maximum number of tunnels currently supported
+ */
+#define NSS_PVXLANMGR_MAX_TUNNELS		64
+
+#define NSS_PVXLANMGR_TUNNEL_STATE_CONFIGURED	0x1
+					/**< Bit is set if tunnel has been configured. */
+
+/**
+ * PVXLAN status enums
+ */
+typedef enum nss_pvxlanmgr_status{
+	/*
+	 * nss_tx_status_t enums
+	 */
+	NSS_PVXLANMGR_SUCCESS = NSS_TX_SUCCESS,
+	NSS_PVXLANMGR_FAILURE = NSS_TX_FAILURE,
+	NSS_PVXLANMGR_FAILURE_QUEUE = NSS_TX_FAILURE_QUEUE,
+	NSS_PVXLANMGR_FAILURE_NOT_READY = NSS_TX_FAILURE_NOT_READY,
+	NSS_PVXLANMGR_FAILURE_TOO_LARGE = NSS_TX_FAILURE_TOO_LARGE,
+	NSS_PVXLANMGR_FAILURE_TOO_SHORT = NSS_TX_FAILURE_TOO_SHORT,
+	NSS_PVXLANMGR_FAILURE_NOT_SUPPORTED = NSS_TX_FAILURE_NOT_SUPPORTED,
+	NSS_PVXLANMGR_FAILURE_BAD_PARAM = NSS_TX_FAILURE_BAD_PARAM,
+
+	/*
+	 * PVXLAN specific ones.
+	 */
+	NSS_PVXLANMGR_FAILURE_TUNNEL_ENABLED = NSS_TX_FAILURE_MAX + 1,
+							/**< Tunnel is enabled. */
+	NSS_PVXLANMGR_FAILURE_TUNNEL_DISABLED,		/**< Tunnel is disabled. */
+	NSS_PVXLANMGR_FAILURE_TUNNEL_NOT_CREATED,	/**< Tunnel is not configured yet. */
+	NSS_PVXLANMGR_FAILURE_TUNNEL_EXISTS,		/**< Tunnel already exisits. */
+	NSS_PVXLANMGR_FAILURE_UNREGISTER_DECONGESTION_CB,
+							/**< Failed to unregister decongestion callback. */
+	NSS_PVXLANMGR_FAILURE_DI_ALLOC_FAILED,		/**< Dynamic interface alloc failed. */
+	NSS_PVXLANMGR_FAILURE_DI_DEALLOC_FAILED,	/**< Dynamic interface dealloc failed. */
+	NSS_PVXLANMGR_FAILURE_PVXLAN_RULE,		/**< Failed to create PVXLAN rule. */
+	NSS_PVXLANMGR_FAILURE_IP_RULE,			/**< Failed to create IP rule. */
+	NSS_PVXLANMGR_FAILURE_REGISTER_NSS,		/**< Failed to register with NSS. */
+	NSS_PVXLANMGR_FAILURE_CMD_TIMEOUT,		/**< NSS Driver Command timed-out. */
+	NSS_PVXLANMGR_FAILURE_INVALID_L3_PROTO,		/**< Invalid Layer3 protocol. */
+	NSS_PVXLANMGR_FAILURE_INVALID_UDP_PROTO,	/**< Invalid UDP protocol. */
+	NSS_PVXLANMGR_FAILURE_INVALID_VERSION,		/**< Invalid pvxlan version. */
+	NSS_PVXLANMGR_FAILURE_IP_DESTROY_RULE,		/**< Destroy IP rule failed. */
+	NSS_PVXLANMGR_FAILURE_PVXLAN_DESTROY_RULE,	/**< Destroy pvxlan rule failed. */
+	NSS_PVXLANMGR_FAILURE_INVALID_IP_NODE,		/**< Invalid tunnel IP node. */
+	NSS_PVXLANMGR_FAILURE_INVALID_TYPE_FLAG,	/**< Invalid type. */
+} nss_pvxlanmgr_status_t;
+
+/**
+ * Private structure to store vxlan header
+. */
+struct nss_pvxlanmgr_vxlan_hdr {
+	uint16_t flags;					/**< VxLAN specific flags. */
+	uint16_t gpid;					/**< Group Policy ID. */
+	uint32_t vnet_id;				/**< Virtual Net ID. */
+};
+
+/**
+ * @brief Send a MAC remove message to NSS
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param mac_addr
+ *
+ * @return nss_pvxlanmgr_status_t
+ */
+extern nss_pvxlanmgr_status_t nss_pvxlanmgr_tunnel_mac_remove(struct net_device *dev, uint32_t tunnel_id, uint8_t *mac_addr);
+
+/**
+ * @brief Send a MAC add message to NSS
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param mac_addr
+ * @param pvxch
+ *
+ * @return nss_pvxlanmgr_status_t
+ */
+extern nss_pvxlanmgr_status_t nss_pvxlanmgr_tunnel_mac_add(struct net_device *dev, uint32_t tunnel_id, uint8_t *mac_addr, struct nss_pvxlanmgr_vxlan_hdr *pvxch);
+
+/**
+ * @brief Disable a PVXLAN tunnel
+ *
+ * @param netdevice
+ *
+ * @return nss_pvxlanmgr_status_t
+ */
+extern nss_pvxlanmgr_status_t nss_pvxlanmgr_netdev_disable(struct net_device *dev);
+
+/**
+ * @brief Enable a PVXLAN tunnel
+ *
+ * @param netdevice
+ *
+ * @return nss_pvxlanmgr_status_t
+ */
+extern nss_pvxlanmgr_status_t nss_pvxlanmgr_netdev_enable(struct net_device *dev);
+
+/**
+ * @brief Destroy a PVXLAN tunnel
+ *
+ * @param netdevice
+ * @param tunnel_id
+ *
+ * @return nss_pvxlanmgr_status_t
+ *
+ * @note PVxLAN tunnel must be disabled before destroy operation.
+ */
+extern nss_pvxlanmgr_status_t nss_pvxlanmgr_tunnel_destroy(struct net_device *dev, uint32_t tunnel_id);
+
+/**
+ * @brief Creates a IPv4 Pvxlan tunnel
+ *
+ * Flow direction is expected to be ingress from the WAN port.
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param IPv4 rule structure
+ * @param tunnel UDP source port for encapsulation
+ *
+ * @return nss_pvxlanmgr_status_t
+ */
+extern nss_pvxlanmgr_status_t nss_pvxlanmgr_tunnel_ipv4_create(struct net_device *dev, uint32_t tunnel_id,
+							struct nss_ipv4_rule_create_msg *nircm, uint32_t pvxlan_src_port);
+
+/**
+ * @brief Creates a IPv6 Pvxlan tunnel
+ *
+ * Flow direction is expected to be ingress from the WAN port.
+ *
+ * @param netdevice
+ * @param tunnel_id
+ * @param IPv6 rule structure
+ * @param tunnel UDP source port for encapsulation
+ *
+ * @return nss_pvxlanmgr_status_t
+ */
+extern nss_pvxlanmgr_status_t nss_pvxlanmgr_tunnel_ipv6_create(struct net_device *dev, uint32_t tunnel_id,
+							struct nss_ipv6_rule_create_msg *nircm, uint32_t pvxlan_src_port);
+
+/**
+ * @brief Return PVxLAN outer interface number
+ *
+ * @param netdevice
+ *
+ * @return uint32_t
+ */
+extern uint32_t nss_pvxlanmgr_get_if_num_outer(struct net_device *dev);
+
+/**
+ * @brief Return PVxLAN host inner interface number
+ *
+ * @param netdevice
+ *
+ * @return uint32_t
+ */
+extern uint32_t nss_pvxlanmgr_get_if_num_host_inner(struct net_device *dev);
+
+/**
+ * @brief Destroy a PVxLAN netdevice
+ *
+ * @param netdevice
+ *
+ * @return nss_pvxlanmgr_status_t
+ *
+ * @note PVXLAN tunnel and any mac rule must be destroyed first.
+ */
+extern nss_pvxlanmgr_status_t nss_pvxlanmgr_netdev_destroy(struct net_device *dev);
+
+/**
+ * @brief Creates a PVXLAN netdevice
+ *
+ * @return Pointer to a newly created netdevice
+ *
+ * @note First Pvxlan interface name is pvxlan0 and so on
+ */
+extern struct net_device *nss_pvxlanmgr_netdev_create(void);
+
+#endif /* __NSS_PVXLANMGR_H */
diff --git a/qca-nss-clients/exports/nss_tlsmgr.h b/qca-nss-clients/exports/nss_tlsmgr.h
new file mode 100644
index 0000000..df5b91b
--- /dev/null
+++ b/qca-nss-clients/exports/nss_tlsmgr.h
@@ -0,0 +1,428 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+/*
+ * nss_tlsmgr.h
+ *	TLS manager interface definitions.
+ */
+#ifndef _NSS_TLSMGR_H_
+#define _NSS_TLSMGR_H_
+
+#define NSS_TLSMGR_REC_MAX 4
+#define NSS_TLSMGR_FRAG_MAX 4
+
+#define NSS_TLSMGR_REC_TYPE_CCS 20		/**< TLS packet is change cipher specification. */
+#define NSS_TLSMGR_REC_TYPE_ALERT 21		/**< TLS packet is Alert.*/
+#define NSS_TLSMGR_REC_TYPE_HANDSHAKE 22	/**< DTLS packet is Handshake.*/
+#define NSS_TLSMGR_REC_TYPE_DATA 23		/**< TLS packet is Application data. */
+
+struct nss_tlsmgr_buf;
+
+/**
+ * NSS TLS manager status
+ */
+typedef enum nss_tlsmgr_status {
+	NSS_TLSMGR_OK,			/**< Status ok. */
+	NSS_TLSMGR_FAIL,		/**< Failed due to unknown reason. */
+	NSS_TLSMGR_INVALID_REC_TYPE,	/**< Unsupported Record Type. */
+	NSS_TLSMGR_INVALID_ALGO,	/**< Invalid algorithm. */
+	NSS_TLSMGR_INVALID_KEYLEN,	/**< Invalid key length for cipher/auth. */
+	NSS_TLSMGR_FAIL_REC_VERSION,	/**< Invalid TLS version. */
+	NSS_TLSMGR_FAIL_REC_LEN,	/**< Invalid Record length. */
+	NSS_TLSMGR_FAIL_NOMEM,		/**< Failed to allocate memory. */
+	NSS_TLSMGR_FAIL_NOCRYPTO,	/**< Failed to allocate crypto resource. */
+	NSS_TLSMGR_FAIL_MESSAGE,	/**< Failed to message the NSS. */
+	NSS_TLSMGR_FAIL_BUF,		/**< Failed to allocate buffer. */
+	NSS_TLSMGR_FAIL_REC_RANGE,	/**< Record Index out of range. */
+	NSS_TLSMGR_FAIL_LINEARIZE,	/**< Failed to linearize SKB. */
+	NSS_TLSMGR_FAIL_DATA_QUEUE,	/**< NSS Queue Congested. */
+	NSS_TLSMGR_FAIL_QUEUE_FULL,	/**< Data Enqueue to NSS failed. */
+	NSS_TLSMGR_FAIL_TRANSFORM,	/**< Data transformation error. */
+} nss_tlsmgr_status_t;
+
+/**
+ * NSS TLS manager supported cryptographic algorithms
+ */
+enum nss_tlsmgr_algo {
+	NSS_TLSMGR_ALGO_NULL,			/**< NO Cipher, NO authentication. */
+	NSS_TLSMGR_ALGO_NULL_SHA1_HMAC,		/**< NULL_SHA1_HMAC. */
+	NSS_TLSMGR_ALGO_NULL_SHA256_HMAC,	/**< NULL_SHA256_HMAC. */
+	NSS_TLSMGR_ALGO_AES_CBC_SHA1_HMAC,	/**< AES_CBC_SHA1_HMAC. */
+	NSS_TLSMGR_ALGO_AES_CBC_SHA256_HMAC,	/**< AES_CBC_SHA256_HMAC. */
+	NSS_TLSMGR_ALGO_3DES_CBC_SHA1_HMAC,	/**< 3DES_CBC_SHA1_HMAC. */
+	NSS_TLSMGR_ALGO_3DES_CBC_SHA256_HMAC,	/**< 3DES_CBC_SHA256_HMAC. */
+	NSS_TLSMGR_ALGO_MAX
+};
+
+/**
+ * NSS tls manager per packet stattistics
+ */
+struct nss_tlsmgr_pkt_stats {
+	uint64_t tx_packets;		/**< Packets enqueued to Firmware. */
+	uint64_t tx_bytes;		/**< Bytes enqueued to Firmware. */
+	uint64_t tx_error;		/**< Error while enqueuing packet to hardware. */
+	uint64_t rx_packets;		/**< Packets processed by Firmware. */
+	uint64_t rx_bytes;		/**< Bytes processed by Firmware. */
+	uint64_t rx_errors;		/**< Error in processing packet. */
+};
+
+/**
+ * NSS TLS manager statistics
+ */
+struct nss_tlsmgr_stats {
+	struct nss_tlsmgr_pkt_stats encap;	/**< TLS manager encapsulation statistics. */
+	struct nss_tlsmgr_pkt_stats decap;	/**< TLS manager decapsulation statistics. */
+};
+
+/**
+ * NSS tls manager record structure
+ */
+struct nss_tlsmgr_rec {
+	struct scatterlist in[NSS_TLSMGR_FRAG_MAX];		/**< Scatterlist for input data. */
+	struct scatterlist out[NSS_TLSMGR_FRAG_MAX];		/**< Scatterlist for output data. */
+	uint8_t rec_type;					/**< Record type (20, 21, 22, 23). */
+	uint8_t error;						/**< Record error. */
+	uint8_t res[2];						/**< Reserved for Alignment. */
+};
+
+/**
+ * NSS TLS manager callback
+ */
+typedef void (*nss_tlsmgr_notify_callback_t)(void *app_data, struct net_device *dev, struct nss_tlsmgr_stats *stats);
+typedef void (*nss_tlsmgr_decongest_callback_t)(void *app_data, struct net_device *dev);
+typedef void (*nss_tlsmgr_data_callback_t)(void *app_data, struct nss_tlsmgr_buf *buf, nss_tlsmgr_status_t status);
+
+/**
+ * NSS TLS manager cryptographic structure to represent key and its length.
+ */
+struct nss_tlsmgr_crypto_data {
+	const uint8_t *data;            /**< Pointer to key or nonce. */
+	uint16_t len;                   /**< Length of the key. */
+};
+
+/**
+ * NSS tls manager base config
+ */
+struct nss_tlsmgr_config {
+	struct nss_tlsmgr_crypto_data cipher_key;	/**< Cipher key. */
+	struct nss_tlsmgr_crypto_data auth_key;		/**< Authentication key. */
+	struct nss_tlsmgr_crypto_data nonce;		/**< Nonce. */
+	enum nss_tlsmgr_algo algo;			/**< TLS manager cryptographic algorithm. */
+	uint16_t hdr_ver;				/* TLS version 1.1 or 1.2 */
+	uint16_t flags;					/* Configuration specific flags */
+};
+
+/**
+ * nss_tlsmgr_tun_add
+ *	Adds a new TLS tunnel.
+ *
+ * @datatypes
+ * nss_tlsmgr_decongest_callback_t \n
+ *
+ * @param[in]  nss_tlsmgr_decongest_callback_t     Decongestion callback.
+ * @param[in]  app_data      Pointer to Application Data.
+ *
+ * @return
+ * Linux NETDEVICE or NULL.
+ */
+struct net_device *nss_tlsmgr_tun_add(nss_tlsmgr_decongest_callback_t cb, void *app_data);
+
+/**
+ * nss_tlsmgr_tun_del
+ *	Unregister dynamic interface and deallocate inner and outer
+ *	Context. Also unregister the TLS netdevice.
+ *
+ * @datatypes
+ * struct net_device
+ *
+ * @param[IN] dev TLS network device
+ *
+ * @return
+ */
+void nss_tlsmgr_tun_del(struct net_device *tun);
+
+/**
+ * nss_tlsmgr_register_notify
+ *	Register notification callback
+ *
+ * @datatypes
+ * struct net_device
+ * nss_tlsmgr_notify_callback_t
+ * uint32_t
+ *
+ * @param[IN] dev       TLS network device
+ * @param[IN] cb        TLS notification callback
+ * @param[IN] app_data  Application data
+ * @param[IN] msecs     Notificaiton time in milliseconds
+ *
+ * @return
+ * true or false if it is already registered.
+ */
+bool nss_tlsmgr_register_notify(struct net_device *tun, nss_tlsmgr_notify_callback_t cb, void *app_data, uint32_t msecs);
+
+/**
+ * nss_tlsmgr_unregister_notify
+ *	Register notification callback
+ *
+ * @datatypes
+ * struct net_device
+ *
+ * @param[IN] dev TLS network device
+ *
+ * @return
+ */
+void nss_tlsmgr_unregister_notify(struct net_device *tun);
+
+/**
+ * nss_tlsmgr_crypto_update_encap
+ *	Update encapsulation cipher state of a TLS session.
+ *	Configures new parameters into the pending encapsulation cipher
+ *	state of a TLS session. This has no effect on the current
+ *	cipher state and its processing of packets.
+ *
+ * @datatypes
+ * struct net_device \n
+ * struct nss_tlsmgr_config \n
+ *
+ * @param[IN} dev TLS network device
+ * @param[IN] cfg TLS crypto update parameters
+ *
+ * @return NSS_TLSMGR_OK for success
+ */
+nss_tlsmgr_status_t nss_tlsmgr_crypto_update_encap(struct net_device *dev, struct nss_tlsmgr_config *cfg);
+
+/**
+ * nss_tlsmgr_crypto_update_decap
+ *	Update decapsulation cipher state of a TLS session.
+ *	Configures new parameters into the pending decapsulation cipher
+ *	state of a TLS session. This has no effect on the current
+ *	cipher state and its processing of packets.
+ *
+ * @datatypes
+ * struct net_device \n
+ * struct nss_tlsmgr_config \n
+ *
+ * @param[IN] dev TLS network device
+ * @param[IN] cfg TLS session update parameters
+ *
+ * @return NSS_TLSMGR_OK for success
+ */
+nss_tlsmgr_status_t nss_tlsmgr_crypto_update_decap(struct net_device *dev, struct nss_tlsmgr_config *cfg);
+
+/**
+ * nss_tlsmgr_tun_get_headroom
+ *	TLS buffer headroom requirment.
+ *
+ * @datatypes
+ * struct net_device \n
+ *
+ * @param[IN] dev TLS network device
+ *
+ * @return
+ * Header length
+ *
+ * Note: Headroom is the sum of header lenght.
+ */
+uint16_t nss_tlsmgr_tun_get_headroom(struct net_device *dev);
+
+/**
+ * nss_tlsmgr_tun_get_tailroom
+ *	TLS buffer tailroom requirment.
+ *
+ * @datatypes
+ * struct net_device \n
+ *
+ * @param[IN] dev TLS network device
+ *
+ * @return
+ * Header length + Trailer length
+ *
+ * Note: Tailroom is the sum of header lenght and trailer length.
+ */
+uint16_t nss_tlsmgr_tun_get_tailroom(struct net_device *dev);
+
+/**
+ * nss_tlsmgr_buf_alloc
+ *	Allocate TLS buffer
+ *
+ * Update decapsulation cipher state of a TLS session.
+ * Configures new parameters into the pending decapsulation cipher
+ * state of a TLS session. This has no effect on the current
+ * cipher state and its processing of packets.
+ *
+ * @datatypes
+ *
+ * @param[IN] priv User private data
+ *
+ * @return
+ * TLS manager buffer or NULL.
+ */
+struct nss_tlsmgr_buf *nss_tlsmgr_buf_alloc(struct net_device *dev, void *priv);
+
+/**
+ * nss_tlsmgr_buf_free
+ *	Free TLS buffer
+ *
+ * @datatypes
+ * struct nss_tlsmgr_buf
+ *
+ * @param[IN] buf TLS manager buffer to free
+ *
+ * @return
+ * TRUE or FALSE.
+ *
+ * Note: This does not ensure if any of the SG list is allocated by caller is freed or not.
+ */
+void nss_tlsmgr_buf_free(struct nss_tlsmgr_buf *buf);
+
+/**
+ * nss_tlsmgr_buf2skb
+ *	Get a SKB pointer from buffer
+ *
+ * @datatypes
+ *
+ * @param[IN] buf TLS buffer
+ *
+ * @return
+ * SKB pointer corresponding to the buffer.
+ */
+struct sk_buff *nss_tlsmgr_buf2skb(struct nss_tlsmgr_buf *buf);
+
+/**
+ * nss_tlsmgr_skb2buf
+ *	Get a buf pointer from SKB
+ *
+ * @datatypes
+ *
+ * @param[IN] SKB sk_buff
+ *
+ * @return
+ * TLS buffer corresponding to SKB.
+ */
+struct nss_tlsmgr_buf *nss_tlsmgr_skb2buf(struct sk_buff *skb);
+
+/**
+ * nss_tlsmgr_buf_get_priv
+ *	Get User private information.
+ *
+ * @datatypes
+ * struct nss_tlsmgr_buf \n
+ *
+ * @param[in] buf Buffer holding Packet information.
+ *
+ * @return
+ */
+void *nss_tlsmgr_buf_get_priv(struct nss_tlsmgr_buf *buf);
+
+/**
+ * nss_tlsmgr_buf_get_rec_cnt
+ *	Get number of records attached to buffer.
+ *
+ * @datatypes
+ * struct nss_tlsmgr_buf \n
+ *
+ * @param[in] buf Buffer holding Packet information.
+ *
+ * @return
+ * number of records.
+ */
+uint8_t nss_tlsmgr_buf_get_rec_cnt(struct nss_tlsmgr_buf *buf);
+
+/**
+ * nss_tlsmgr_buf_get_rec
+ *	Get a record from a buffer.
+ *
+ * @datatypes
+ * struct nss_tlsmgr_buf \n
+ * uint8_t rec_idx
+ *
+ * @param[in] buf      Buffer holding Packet information.
+ * @param[in] rec_idx  Index to a particular record.
+ *
+ * @return
+ * Pointer to a record structure.
+ * NULL if the rec_idx is invalid.
+ */
+struct nss_tlsmgr_rec *nss_tlsmgr_buf_get_rec(struct nss_tlsmgr_buf *buf, uint8_t rec_idx);
+
+/**
+ * nss_tlsmgr_buf_set_rec
+ *	Set a record in a buffer.
+ *
+ * @datatypes
+ * struct nss_tlsmgr_buf \n
+ *
+ * @param[in] buf Buffer holding Packet information.
+ *
+ * @return
+ * Pointer to a record structure.
+ * NULL if the set is attempted beyond the supported maximum size.
+ */
+struct nss_tlsmgr_rec *nss_tlsmgr_buf_set_rec(struct nss_tlsmgr_buf *buf, uint8_t in_segs, uint8_t out_segs);
+
+/**
+ * nss_tlsmgr_buf_decap_skb2rec
+ *	API used to add records to buffer for decapsulation.
+ *
+ * @datatypes
+ * struct nss_tlsmgr_buf \n
+ * struct sk_buff
+ *
+ * @param[in] buf Buffer holding Packet information.
+ * @param[in] SKB skb containing payload.
+ *
+ * @return
+ * TRUE or FALSE.
+ */
+nss_tlsmgr_status_t nss_tlsmgr_buf_decap_skb2recs(struct sk_buff *skb, struct nss_tlsmgr_buf *buf);
+
+/**
+ * nss_tlsmgr_buf_encap
+ *	API used to schedule TLS encapsulation.
+ *
+ * @datatypes
+ * struct nss_tlsmgr_buf \n
+ * nss_tlsmgr_data_callback_t
+ *
+ * @param[in] buf       Buffer holding Packet information.
+ * @param[in] cb        Application data callback handler.
+ * @param[in] app_data  Application data.
+ *
+ * @return
+ * NSS_TLSMGR_OK for success
+ */
+nss_tlsmgr_status_t nss_tlsmgr_buf_encap(struct nss_tlsmgr_buf *buf, nss_tlsmgr_data_callback_t cb, void *app_data);
+
+/**
+ * nss_tlsmgr_buf_decap
+ *	API used to schedule TLS decapsulation.
+ *
+ * @datatypes
+ * struct nss_tlsmgr_buf \n
+ * nss_tlsmgr_data_callback_t \n
+ *
+ * @param[in] buf   	Buffer holding Packet information.
+ * @param[in] cb    	Application data callback handler.
+ * @param[in] app_data  Application data.
+ *
+ * @return
+ * NSS_TLSMGR_OK for success
+ */
+nss_tlsmgr_status_t nss_tlsmgr_buf_decap(struct nss_tlsmgr_buf *buf, nss_tlsmgr_data_callback_t cb, void *app_data);
+
+#endif /* _NSS_TLSMGR_H_ */
diff --git a/qca-nss-clients/exports/nss_vlan_mgr.h b/qca-nss-clients/exports/nss_vlan_mgr.h
new file mode 100644
index 0000000..c0d7620
--- /dev/null
+++ b/qca-nss-clients/exports/nss_vlan_mgr.h
@@ -0,0 +1,94 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_vlan_mgr.h
+ *	vlan manager interface definitions.
+ */
+#ifndef _NSS_VLAN_MGR_H_
+#define _NSS_VLAN_MGR_H_
+
+/*
+ * nss_vlan_mgr_join_bridge()
+ *	update ingress and egress vlan translation rule to use bridge VSI
+ *
+ * @param dev[IN] vlan device which joined in bridge
+ * @param bridge_vsi[IN] bridge VSI to attach to
+ * @return 0 for success, -1 for failure
+ */
+int nss_vlan_mgr_join_bridge(struct net_device *dev, uint32_t bridge_vsi);
+
+/*
+ * nss_vlan_mgr_leave_bridge()
+ *	update ingress and egress vlan translation rule to restore vlan VSI
+ *
+ * @param dev[IN] vlan device which left from bridge
+ * @param bridge_vsi[IN] bridge VSI to detach from
+ * @return 0 for success, -1 for failure
+ */
+int nss_vlan_mgr_leave_bridge(struct net_device *dev, uint32_t bridge_vsi);
+
+#ifdef NSS_VLAN_MGR_PPE_SUPPORT
+/*
+ * nss_vlan_mgr_add_bond_slave()
+ *	update ingress and egress vlan translation rule to use bond slave
+ *
+ * @param bond_dev[IN] bond device
+ * @param slave_dev[IN] slave device
+ * @return 0 for success, -1 for failure
+ */
+int nss_vlan_mgr_add_bond_slave(struct net_device *bond_dev,
+				struct net_device *slave_dev);
+
+/*
+ * nss_vlan_mgr_delete_bond_slave()
+ *	update ingress and egress vlan translation rule to use bond slave
+ *
+ * @param slave_dev[IN] slave device
+ * @return 0 for success, -1 for failure
+ */
+int nss_vlan_mgr_delete_bond_slave(struct net_device *slave_dev);
+#endif
+
+/*
+ * nss_vlan_mgr_get_real_dev()
+ *	get real_dev for the vlan
+ *
+ * @param vlan_dev[IN] device
+ * @return real_dev
+ */
+struct net_device *nss_vlan_mgr_get_real_dev(struct net_device *dev);
+
+/*
+ * nss_vlan_mgr_add_vlan_rule()
+ *	Add VLAN translation rule in PPE
+ *
+ * @param dev[IN] physical device
+ * @param bridge_vsi[IN] bridge VSI
+ * @param vid[IN] VLAN ID
+ */
+void nss_vlan_mgr_add_vlan_rule(struct net_device *dev, int bridge_vsi, int vid);
+
+/*
+ * nss_vlan_mgr_del_vlan_rule()
+ *	Delete VLAN translation rule in PPE
+ *
+ * @param dev[IN] physical device
+ * @param bridge_vsi[IN] bridge VSI
+ * @param vid[IN] VLAN ID
+ */
+void nss_vlan_mgr_del_vlan_rule(struct net_device *dev, int bridge_vsi, int vid);
+#endif /* _NSS_VLAN_MGR_H_ */
diff --git a/qca-nss-clients/exports/nss_wifi_meshmgr.h b/qca-nss-clients/exports/nss_wifi_meshmgr.h
new file mode 100644
index 0000000..709a701
--- /dev/null
+++ b/qca-nss-clients/exports/nss_wifi_meshmgr.h
@@ -0,0 +1,632 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_wifi_meshmgr.h
+ *	Client WiFi-Mesh manager for NSS
+ */
+#ifndef ___NSS_WIFI_MESHMGR_H_
+#define ___NSS_WIFI_MESHMGR_H_
+
+#define NSS_WIFI_MESH_TX_TIMEOUT 3000	/**< Unit is in milliseconds. */
+#define NSS_WIFI_MESH_HANDLE_INVALID -1 /**< Invalid mesh handle ID. */
+
+/**
+ * Mesh status enums
+ */
+typedef enum {
+	/*
+	 * nss_tx_status_t enums
+	 */
+	NSS_WIFI_MESHMGR_SUCCESS = NSS_TX_SUCCESS,				/**< Wi-Fi mesh transmit success. */
+	NSS_WIFI_MESHMGR_FAILURE = NSS_TX_FAILURE,				/**< Wi-Fi mesh transmit failure. */
+	NSS_WIFI_MESHMGR_FAILURE_QUEUE = NSS_TX_FAILURE_QUEUE,			/**< Wi-Fi mesh transmit enqueue failed. */
+	NSS_WIFI_MESHMGR_FAILURE_NOT_READY = NSS_TX_FAILURE_NOT_READY,		/**< Wi-Fi mesh tranmsit core not ready. */
+	NSS_WIFI_MESHMGR_FAILURE_TOO_LARGE = NSS_TX_FAILURE_TOO_LARGE,		/**< Wi-Fi mesh transmit message too large. */
+	NSS_WIFI_MESHMGR_FAILURE_TOO_SHORT = NSS_TX_FAILURE_TOO_SHORT,		/**< WI-Fi mesh transmit message too short. */
+	NSS_WIFI_MESHMGR_FAILURE_NOT_SUPPORTED = NSS_TX_FAILURE_NOT_SUPPORTED,	/**< WI-Fi mesh transmit message not supported. */
+	NSS_WIFI_MESHMGR_FAILURE_BAD_PARAM = NSS_TX_FAILURE_BAD_PARAM,		/**< Wi-Fi mesh transmit invalid parameter. */
+	NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT = NSS_TX_FAILURE_SYNC_TIMEOUT,	/**< Wi-Fi mesh transmit transmit timed out. */
+
+	/*
+	 * Mesh specific ones.
+	 */
+	NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX = 100,			/**< Wi-Fi NULL mesh context. */
+	NSS_WIFI_MESHMGR_FAILURE_UNKNOWN_MSG,				/**< Wi-Fi mesh unknown message error. */
+	NSS_WIFI_MESHMGR_FAILURE_TTL_CONFIG,				/**< Wi-Fi mesh invalid ttl error. */
+	NSS_WIFI_MESHMGR_FAILURE_REFRESH_TIME_CONFIG,			/**< Wi-Fi mesh invalid refresh time. */
+	NSS_WIFI_MESHMGR_FAILURE_MPP_LEARNING_MODE_CONFIG,			/**< Wi-Fi mesh invalid mpp learning mode. */
+	NSS_WIFI_MESHMGR_FAILURE_PATH_ADD_MAX_RADIO_CNT,			/**< Wi-Fi mesh path add error due to max radio count */
+	NSS_WIFI_MESHMGR_FAILURE_PATH_ADD_INVALID_INTERFACE_NUM,		/**< Wi-Fi mesh path invalid interface number */
+	NSS_WIFI_MESHMGR_FAILURE_PATH_ADD_INTERFACE_NUM_NOT_FOUND,		/**< Wi-Fi mesh path interface number not found. */
+	NSS_WIFI_MESHMGR_FAILURE_PATH_TABLE_FULL,				/**< Wi-Fi mesh path table full error */
+	NSS_WIFI_MESHMGR_FAILURE_PATH_ALLOC_FAIL,				/**< Wi-Fi mesh path alloc error */
+	NSS_WIFI_MESHMGR_FAILURE_PATH_INSERT_FAIL,				/**< Wi-Fi mesh path insert fail */
+	NSS_WIFI_MESHMGR_FAILURE_PATH_NOT_FOUND,				/**< Wi-Fi mesh path not found error */
+	NSS_WIFI_MESHMGR_FAILURE_PATH_UNHASHED,				/**< Wi-Fi mesh proxy path unhashed error */
+	NSS_WIFI_MESHMGR_FAILURE_PATH_DELETE_FAIL,				/**< Wi-Fi mesh proxy path delete error */
+	NSS_WIFI_MESHMGR_FAILURE_PROXY_PATH_NOT_FOUND,			/**< Wi-Fi mesh proxy path not found error */
+	NSS_WIFI_MESHMGR_FAILURE_PROXY_PATH_UNHASHED,			/**< Wi-Fi mesh proxy path unhashed error */
+	NSS_WIFI_MESHMGR_FAILURE_PROXY_PATH_DELETE_FAIL,			/**< Wi-Fi mesh proxy path delete error */
+	NSS_WIFI_MESHMGR_FAILURE_PROXY_PATH_EXISTS,				/**< Wi-Fi mesh proxy path exists error */
+	NSS_WIFI_MESHMGR_FAILURE_PROXY_PATH_ALLOC_FAIL,			/**< Wi-Fi mesh proxy path alloc error */
+	NSS_WIFI_MESHMGR_FAILURE_PROXY_PATH_INSERT_FAIL,			/**< Wi-Fi mesh proxy path insert error */
+	NSS_WIFI_MESHMGR_FAILURE_PROXY_PATH_TABLE_FULL,			/**< Wi-Fi mesh proxy path table full error */
+	NSS_WIFI_MESHMGR_FAILURE_PB_ALLOC_FAIL,				/**< Wi-Fi mesh pb allocation failures */
+	NSS_WIFI_MESHMGR_FAILURE_ENQUEUE_TO_HOST_FAIL,			/**< Wi-Fi mesh enqueue to host failure */
+	NSS_WIFI_MESHMGR_FAILURE_ENABLE_INTERFACE_FAIL,			/**< Wi-Fi mesh enabling interface failure */
+	NSS_WIFI_MESHMGR_FAILURE_DISABLE_INTERFACE_FAIL,			/**< Wi-Fi mesh disabling interface failure */
+	NSS_WIFI_MESHMGR_FAILURE_INVALID_EXCEPTION_NUM,				/**< Wi-Fi mesh invalid exception number */
+	NSS_WIFI_MESHMGR_FAILURE_ONESHOT_ALREADY_ATTACHED,			/**< Wi-Fi mesh oneshot already attached error */
+} nss_wifi_meshmgr_status_t;
+
+/**
+ * nss_wifi_mesh_handle_t
+ *	Opaque mesh handler
+ */
+typedef int32_t nss_wifi_mesh_handle_t;
+
+/**
+ * nss_wifi_meshmgr_tx_buf
+ *	Sends a Wi-Fi mesh data packet to the NSS interface.
+ *
+ * Note: This API should is used in testing purpose for sending
+ * packets to NSS mesh I/F directly. It should be avoided by the
+ * user.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	os_buf		Pointer to the OS data buffer.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_tx_buf(nss_wifi_mesh_handle_t mesh_handle, struct sk_buff *os_buf);
+
+/**
+ * nss_wifi_meshmgr_if_down()
+ *	Make the NSS interface down synchronously.
+ *
+ * Note: This is blocking API and should not be called from
+ * atomic context.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_if_down(nss_wifi_mesh_handle_t mesh_handle);
+
+/**
+ * nss_wifi_meshmgr_if_up()
+ *	Make the NSS interface up synchronously.
+ *
+ * Note: This is blocking API and should not be called from
+ * atomic context.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_if_up(nss_wifi_mesh_handle_t mesh_handle);
+
+/**
+ * nss_wifi_meshmgr_dump_mesh_path()
+ *	Send dump mesh path table request.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_msg_callback_t \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	msg_cb		Callback for NACK/ACK messages from NSS.
+ * @param[in]	app_data	Application data for the message callback.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_dump_mesh_path(nss_wifi_mesh_handle_t mesh_handle,
+						       nss_wifi_mesh_msg_callback_t msg_cb,
+						       void *app_data);
+
+/**
+ * nss_wifi_meshmgr_dump_mesh_path_sync()
+ *	Send dump mesh path table request synchronously.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_dump_mesh_path_sync(nss_wifi_mesh_handle_t mesh_handle);
+
+/**
+ * nss_wifi_meshmgr_dump_mesh_proxy_path()
+ *	Dump mesh proxy path table request.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_msg_callback_t \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	msg_cb		Callback for NACK/ACK messages from NSS.
+ * @param[in]	app_data	Application data for the message callback.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_dump_mesh_proxy_path(nss_wifi_mesh_handle_t mesh_handle,
+							     nss_wifi_mesh_msg_callback_t msg_cb,
+							     void *app_data);
+
+/**
+ * nss_wifi_meshmgr_dump_mesh_proxy_path_sync()
+ *	Send dump mesh proxy path table request synchronously.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_dump_mesh_proxy_path_sync(nss_wifi_mesh_handle_t mesh_handle);
+
+/**
+ * nss_wifi_meshmgr_assoc_link_vap
+ *	Associate the link interface to the mesh I/F.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_assoc_link_vap \n
+ * nss_wifi_mesh_msg_callback_t \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmalv		WiFi interface link vap association message.
+ * @param[in]	msg_cb		Callback for NACK/ACK messages from NSS.
+ * @param[in]	app_data	Application data for the message callback.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_assoc_link_vap(nss_wifi_mesh_handle_t mesh_handle,
+						       struct nss_wifi_mesh_assoc_link_vap *wmalv,
+						       nss_wifi_mesh_msg_callback_t msg_cb,
+						       void *app_data);
+
+/**
+ * nss_wifi_meshmgr_assoc_link_vap_sync
+ *	Associate the link interface to the mesh I/F synchronously.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_assoc_link_vap \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmalv		WiFi interface link vap association message.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_assoc_link_vap_sync(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_assoc_link_vap *wmalv);
+
+/**
+ * nss_wifi_meshmgr_mesh_config_update
+ *	Update mesh configuration message.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_config_msg \n
+ * nss_wifi_mesh_msg_callback_t \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmcum		WiFi interface configuration message.
+ * @param[in]	msg_cb		Callback for NACK/ACK messages from NSS.
+ * @param[in]	app_data	Application data for the message callback.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_config_update(nss_wifi_mesh_handle_t mesh_handle,
+							   struct nss_wifi_mesh_config_msg *wmcum,
+							   nss_wifi_mesh_msg_callback_t msg_cb,
+							   void *app_data);
+/**
+ * nss_wifi_meshmgr_mesh_config_update_sync
+ *	Send mesh configuration update message synchronously.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_config_msg \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmcum		WiFi interface configuration message.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_config_update_sync(nss_wifi_mesh_handle_t mesh_handle,
+								struct nss_wifi_mesh_config_msg *wmcum);
+
+/**
+ * nss_wifi_meshmgr_mesh_proxy_path_delete
+ *	Send mesh proxy path delete.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_proxy_path_del_msg \n
+ * nss_wifi_mesh_msg_callback_t \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmppdm		WiFi mesh proxy path delete message.
+ * @param[in]	msg_cb		Callback for NACK/ACK messages from NSS.
+ * @param[in]	app_data	Application data for the message callback.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_proxy_path_delete(nss_wifi_mesh_handle_t mesh_handle,
+							       struct nss_wifi_mesh_proxy_path_del_msg *wmppdm,
+							       nss_wifi_mesh_msg_callback_t msg_cb,
+							       void *app_data);
+
+/**
+ * nss_wifi_meshmgr_mesh_proxy_path_delete_sync
+ *	Send mesh proxy path delete synchronously.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_proxy_path_del_msg \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmppdm		WiFi mesh proxy path delete message.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_proxy_path_delete_sync(nss_wifi_mesh_handle_t mesh_handle,
+								    struct nss_wifi_mesh_proxy_path_del_msg *wmppdm);
+
+/**
+ * nss_wifi_meshmgr_mesh_proxy_path_update
+ *	Send mesh proxy path update.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_proxy_path_update_msg \n
+ * nss_wifi_mesh_msg_callback_t \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmppum		WiFi mesh proxy path update message.
+ * @param[in]	msg_cb		Callback for NACK/ACK messages from NSS.
+ * @param[in]	app_data	Application data for the message callback.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_proxy_path_update(nss_wifi_mesh_handle_t mesh_handle,
+							       struct nss_wifi_mesh_proxy_path_update_msg *wmppum,
+							       nss_wifi_mesh_msg_callback_t msg_cb,
+							       void *app_data);
+
+/**
+ * nss_wifi_meshmgr_mesh_proxy_path_update_sync
+ *	Send mesh proxy path update synchronously
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_proxy_path_update_msg \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmppum		WiFi mesh proxy path update message.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_proxy_path_update_sync(nss_wifi_mesh_handle_t mesh_handle,
+								    struct nss_wifi_mesh_proxy_path_update_msg *wmppum);
+
+/**
+ * nss_wifi_meshmgr_mesh_proxy_path_add
+ *	Send mesh proxy path add message.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_proxy_path_add_msg\n
+ * nss_wifi_mesh_msg_callback_t \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmppam		WiFi mesh proxy path add message.
+ * @param[in]	msg_cb		Callback for NACK/ACK messages from NSS.
+ * @param[in]	app_data	Application data for the message callback.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_proxy_path_add(nss_wifi_mesh_handle_t mesh_handle,
+							    struct nss_wifi_mesh_proxy_path_add_msg *wmppam,
+							    nss_wifi_mesh_msg_callback_t msg_cb,
+							    void *app_data);
+
+/**
+ * nss_wifi_meshmgr_mesh_proxy_path_add_sync
+ *	Send mesh proxy path add message synchronously.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_proxy_path_add_msg\n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmppam		WiFi mesh proxy path add message.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_proxy_path_add_sync(nss_wifi_mesh_handle_t mesh_handle,
+								 struct nss_wifi_mesh_proxy_path_add_msg *wmppam);
+
+/**
+ * nss_wifi_meshmgr_mesh_path_delete
+ *	Send mesh path delete message.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_mpath_del_msg \n
+ * nss_wifi_mesh_msg_callback_t \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmpdm		WiFi mesh path delete message.
+ * @param[in]	msg_cb		Callback for NACK/ACK messages from NSS.
+ * @param[in]	app_data	Application data for the message callback.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_path_delete(nss_wifi_mesh_handle_t mesh_handle,
+							 struct nss_wifi_mesh_mpath_del_msg *wmpdm,
+							 nss_wifi_mesh_msg_callback_t msg_cb,
+							 void *app_data);
+
+/**
+ * nss_wifi_meshmgr_mesh_path_delete_sync
+ *	Send mesh path delete message synchronously.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_mpath_del_msg \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmpdm		WiFi mesh path delete message.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_path_delete_sync(nss_wifi_mesh_handle_t mesh_handle,
+							      struct nss_wifi_mesh_mpath_del_msg *wmpdm);
+
+/**
+ * nss_wifi_meshmgr_mesh_path_update
+ *	Send mesh path update message.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_mpath_update_msg \n
+ * nss_wifi_mesh_msg_callback_t \n
+ * msg_cb
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmpum		WiFi mesh path update message.
+ * @param[in]	msg_cb		Callback for NACK/ACK messages from NSS.
+ * @param[in]	app_data	Application data for the message callback.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_path_update(nss_wifi_mesh_handle_t mesh_handle,
+							 struct nss_wifi_mesh_mpath_update_msg *wmpum,
+							 nss_wifi_mesh_msg_callback_t msg_cb,
+							 void *app_data);
+
+/**
+ * nss_wifi_meshmgr_mesh_path_update_sync
+ *	Send mesh path update message synchronously.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_mpath_update_msg \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmpum		WiFi mesh path update message.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_path_update_sync(nss_wifi_mesh_handle_t mesh_handle,
+							      struct nss_wifi_mesh_mpath_update_msg *wmpum);
+
+/**
+ * nss_wifi_meshmgr_mesh_path_add
+ *	Send mesh path add message.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_mpath_add_msg \n
+ * nss_wifi_mesh_msg_callback_t \n
+ *
+ * @param[in]	mesh_handle     Pointer to the mesh handle.
+ * @param[in]	wmpam		WiFi mesh path add message.
+ * @param[in]	msg_cb		Callback for NACK/ACK messages from NSS.
+ * @param[in]	app_data	Application data for the message callback.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_path_add(nss_wifi_mesh_handle_t mesh_handle,
+						      struct nss_wifi_mesh_mpath_add_msg *wmpam,
+						      nss_wifi_mesh_msg_callback_t msg_cb,
+						      void *app_data);
+
+/**
+ * nss_wifi_meshmgr_mesh_path_add_sync
+ *	Send mesh path add message synchronously.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_mpath_add_msg \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmpam		WiFi mesh path add message.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_path_add_sync(nss_wifi_mesh_handle_t mesh_handle,
+							   struct nss_wifi_mesh_mpath_add_msg *wmpam);
+
+/**
+ * nss_wifi_meshmgr_mesh_path_exception
+ *	Send mesh path exception message.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_exception_flag_msg \n
+ * nss_wifi_mesh_msg_callback_t \n
+ *
+ * @param[in]	mesh_handle     Pointer to the mesh handle.
+ * @param[in]	wmpefm		WiFi mesh path exception message.
+ * @param[in]	msg_cb		Callback for NACK/ACK messages from NSS.
+ * @param[in]	app_data	Application data for the message callback.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_path_exception(nss_wifi_mesh_handle_t mesh_handle,
+						      struct nss_wifi_mesh_exception_flag_msg *wmpefm,
+						      nss_wifi_mesh_msg_callback_t msg_cb,
+						      void *app_data);
+
+/**
+ * nss_wifi_meshmgr_mesh_path_exception_sync
+ *	Send mesh path update message synchronously.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_exception_flag_msg \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmpefm		WiFi mesh path exception flag message.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_mesh_path_exception_sync(nss_wifi_mesh_handle_t mesh_handle,
+							      struct nss_wifi_mesh_exception_flag_msg *wmpefm);
+
+/**
+ * nss_wifi_meshmgr_config_mesh_exception
+ *	Configure mesh exceptions.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_rate_limit_config \n
+ * nss_wifi_mesh_msg_callback_t \n
+ *
+ * @param[in]	mesh_handle     Pointer to the mesh handle.
+ * @param[in]	wmrlc		WiFi mesh exception config message.
+ * @param[in]	msg_cb		Callback for NACK/ACK messages from NSS.
+ * @param[in]	app_data	Application data for the message callback.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_config_mesh_exception(nss_wifi_mesh_handle_t mesh_handle,
+						      struct nss_wifi_mesh_rate_limit_config *wmrlc,
+						      nss_wifi_mesh_msg_callback_t msg_cb,
+						      void *app_data);
+
+/**
+ * nss_wifi_meshmgr_config_mesh_exception_sync
+ *	configure mesh exception synchronously.
+ *
+ * @datatypes
+ * nss_wifi_mesh_handle_t \n
+ * nss_wifi_mesh_rate_limit_config \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ * @param[in]	wmrlc		WiFi mesh config exception message.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_config_mesh_exception_sync(nss_wifi_mesh_handle_t mesh_handle,
+							      struct nss_wifi_mesh_rate_limit_config *wmrlc);
+
+/**
+ * nss_wifi_meshmgr_mesh_if_destroy_sync
+ *	Destroy NSS mesh interfaces synchronously.
+ *
+ * @dataypes
+ * nss_wifi_mesh_handle_t \n
+ *
+ * @param[in]	mesh_handle	Pointer to the mesh handle.
+ *
+ * @return
+ * Status
+ */
+extern nss_wifi_meshmgr_status_t nss_wifi_meshmgr_if_destroy_sync(nss_wifi_mesh_handle_t mesh_handle);
+
+/**
+ * nss_wifi_meshmgr_mesh_if_create_sync
+ *	Create NSS mesh interface synchronously.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_wifi_mesh_config_msg \n
+ * nss_wifi_mesh_data_callback_t \n
+ * nss_wifi_mesh_ext_data_callback_t \n
+ * nss_wifi_mesh_msg_callback_t \n
+ *
+ * @param[in]		dev		Pointer to the associated network device.
+ * @param[in]		config_msg	Pointer to the mesh configuration message.
+ * @param[in]		data_cb		Callback for the Wi-Fi mesh device data.
+ * @param[in]		ext_data_cb	Callback for the extended data.
+ * @param[in]		event_cb	Callback for the NSS to Host notify mesage.
+ *
+ * @return
+ * Mesh handle
+ */
+extern nss_wifi_mesh_handle_t nss_wifi_meshmgr_if_create_sync(struct net_device *dev, struct nss_wifi_mesh_config_msg *config_msg,
+							      nss_wifi_mesh_data_callback_t data_cb,
+							      nss_wifi_mesh_ext_data_callback_t ext_data_cb,
+							      nss_wifi_mesh_msg_callback_t event_cb);
+#endif /* __NSS_WIFI_MESHMGR_H */
diff --git a/qca-nss-clients/gre/Makefile b/qca-nss-clients/gre/Makefile
new file mode 100644
index 0000000..2642f98
--- /dev/null
+++ b/qca-nss-clients/gre/Makefile
@@ -0,0 +1,8 @@
+# Makefile for gre client
+ccflags-y += -I$(obj)/../../exports -I$(obj)/../..
+ccflags-y += -DNSS_GRE_DEBUG_LEVEL=0
+ccflags-y += -Wall -Werror
+obj-m += qca-nss-gre.o
+qca-nss-gre-objs := nss_connmgr_gre.o nss_connmgr_gre_v4.o nss_connmgr_gre_v6.o
+
+obj-y+= test/
diff --git a/qca-nss-clients/gre/nss_connmgr_gre.c b/qca-nss-clients/gre/nss_connmgr_gre.c
new file mode 100644
index 0000000..4797264
--- /dev/null
+++ b/qca-nss-clients/gre/nss_connmgr_gre.c
@@ -0,0 +1,1868 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_connnmgr_gre.c
+ *  This file implements client for GRE.
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <net/ip_tunnels.h>
+#include <net/ip6_tunnel.h>
+#include <linux/if_ether.h>
+#include <net/gre.h>
+#include <net/ip.h>
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+#include <nss_cmn.h>
+#include "nss_connmgr_gre_public.h"
+#include "nss_connmgr_gre.h"
+
+#define MAX_RETRY_COUNT 100
+#define MAX_WIFI_HEADROOM 66
+
+/*
+ * GRE connection manager context structure
+ */
+struct nss_connmgr_gre_context {
+	struct list_head list;		/* List of GRE interface instances */
+	spinlock_t lock;		/* Lock to protect list */
+} gre_connmgr_ctx;
+
+/*
+ * GRE interface instance
+ */
+struct nss_gre_iface_instance {
+	struct list_head list;			/* List of GRE interface instances */
+	struct net_device *dev;			/* GRE netdevice */
+	struct nss_connmgr_gre_cfg gre_cfg;	/* GRE configuration */
+	enum nss_connmgr_gre_iftype gre_iftype;	/* GRE interface type */
+	uint32_t inner_ifnum;			/* GRE inner dynamic interface */
+	uint32_t outer_ifnum;			/* GRE outer dynamic interface */
+};
+
+/*
+ * Unaligned infra in nss is disabled by default
+ */
+static bool enable_unalign = 1;
+module_param(enable_unalign, bool, 0);
+
+/*
+ * nss_connmgr_gre_is_gre()
+ *	Check whether device is of type GRE Tap or GRE Tun.
+ */
+static bool nss_connmgr_gre_is_gre(struct net_device *dev)
+{
+	if ((dev->type == ARPHRD_IPGRE) ||
+	      (dev->type == ARPHRD_IP6GRE) || ((dev->type == ARPHRD_ETHER) &&
+	      (dev->priv_flags_ext & (IFF_EXT_GRE_V4_TAP | IFF_EXT_GRE_V6_TAP)))) {
+		return true;
+	}
+
+	return false;
+}
+
+/*
+ * nss_connmgr_gre_alloc_instance()
+ *	Allocate GRE interface instance.
+ */
+static struct nss_gre_iface_instance *nss_connmgr_gre_alloc_instance(struct net_device *dev)
+{
+	struct nss_gre_iface_instance *ngii;
+
+	if (!nss_connmgr_gre_is_gre(dev)) {
+		nss_connmgr_gre_warning("%px: dev is not a GRE interface\n", dev);
+		return NULL;
+	}
+
+	ngii = kzalloc(sizeof(*ngii), GFP_KERNEL);
+	if (!ngii)
+		return NULL;
+
+	INIT_LIST_HEAD(&ngii->list);
+	ngii->dev = dev;
+	return ngii;
+}
+
+/*
+ * nss_connmgr_gre_free_instance()
+ *	Free GRE interface instance.
+ */
+static void nss_connmgr_gre_free_instance(struct nss_gre_iface_instance *ngii)
+{
+	spin_lock(&gre_connmgr_ctx.lock);
+	ngii->dev = NULL;
+
+	if (!list_empty(&ngii->list))
+		list_del(&ngii->list);
+
+	spin_unlock(&gre_connmgr_ctx.lock);
+	kfree(ngii);
+}
+
+/*
+ * nss_connmgr_gre_find_instance()
+ *	Find GRE interface instance from list.
+ */
+static struct nss_gre_iface_instance *nss_connmgr_gre_find_instance(struct net_device *dev)
+{
+	struct nss_gre_iface_instance *ngii;
+
+	if (!nss_connmgr_gre_is_gre(dev)) {
+		nss_connmgr_gre_warning("%px: dev is not a GRE interface\n", dev);
+		return NULL;
+	}
+
+	/*
+	 * Check if dev instance is in the list
+	 */
+	spin_lock(&gre_connmgr_ctx.lock);
+	list_for_each_entry(ngii, &gre_connmgr_ctx.list, list) {
+		if (ngii->dev == dev) {
+			spin_unlock(&gre_connmgr_ctx.lock);
+			return ngii;
+		}
+	}
+
+	spin_unlock(&gre_connmgr_ctx.lock);
+	return NULL;
+}
+
+/*
+ * nss_connmgr_gre_dev_change_mtu()
+ *	Netdev ops function to modify MTU of netdevice.
+ */
+static int nss_connmgr_gre_dev_change_mtu(struct net_device *dev, int new_mtu)
+{
+	if (new_mtu < 68 ||
+	    new_mtu > 0xFFF8 - dev->needed_headroom) {
+		return -EINVAL;
+	}
+
+	dev->mtu = new_mtu;
+	return 0;
+}
+
+/*
+ * nss_connmgr_gre_dev_init()
+ *	Netdev ops function to intialize netdevice.
+ */
+static int nss_connmgr_gre_dev_init(struct net_device *dev)
+{
+	int i;
+	nss_connmgr_gre_priv_t *priv = netdev_priv(dev);
+	int32_t append = priv->pad_len + priv->gre_hlen;
+
+	dev->tstats = alloc_percpu(struct pcpu_sw_netstats);
+	if (!dev->tstats) {
+		return -ENOMEM;
+	}
+
+	for_each_possible_cpu(i) {
+		struct pcpu_sw_netstats *stats;
+		stats = per_cpu_ptr(dev->tstats, i);
+		u64_stats_init(&stats->syncp);
+	}
+
+	if ((dev->priv_flags_ext & IFF_EXT_GRE_V4_TAP) || (dev->type == ARPHRD_IPGRE)) {
+		dev->needed_headroom = sizeof(struct iphdr) + sizeof(struct ethhdr) + MAX_WIFI_HEADROOM + append;
+		dev->mtu = ETH_DATA_LEN - sizeof(struct iphdr) - append;
+		dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HIGHDMA;
+		dev->hw_features |= NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HIGHDMA;
+		return 0;
+	}
+
+	/*
+	 * Ipv6
+	 */
+	dev->needed_headroom = sizeof(struct ipv6hdr) + sizeof(struct ethhdr) + MAX_WIFI_HEADROOM + append;
+	dev->mtu = ETH_DATA_LEN - sizeof(struct ipv6hdr) - append;
+	if (dev->mtu < IPV6_MIN_MTU) {
+		dev->mtu = IPV6_MIN_MTU;
+	}
+
+	dev->features |= NETIF_F_NETNS_LOCAL;
+	return 0;
+}
+
+/*
+ * nss_connmgr_gre_dev_uninit()
+ *	Netdev ops function to unintialize netdevice.
+ */
+static void nss_connmgr_gre_dev_uninit(struct net_device *dev)
+{
+	free_percpu(dev->tstats);
+	return;
+}
+
+/*
+ * nss_connmgr_gre_dev_xmit()
+ *	Netdev ops function to send packet to NSS.
+ */
+static netdev_tx_t nss_connmgr_gre_dev_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	nss_tx_status_t status;
+	int if_number;
+	struct nss_ctx_instance *gre_ctx;
+	nss_connmgr_gre_priv_t *priv = netdev_priv(dev);
+
+	if_number = priv->nss_if_number_inner;
+	if (unlikely(if_number <= 0)) {
+		nss_connmgr_gre_info("%px: GRE dev is not registered with nss\n", dev);
+		goto fail;
+	}
+
+	gre_ctx = nss_gre_get_context();
+	if (unlikely(!gre_ctx)) {
+		nss_connmgr_gre_info("%px: NSS GRE context not found for if_number %d\n", dev, if_number);
+		goto fail;
+	}
+
+	/*
+	 * Make room for needed headroom and un-share
+	 * the SKB if it is cloned.
+	 */
+	if (skb_cow_head(skb, dev->needed_headroom)) {
+		nss_connmgr_gre_info("%px: NSS GRE insufficient headroom\n", dev);
+		goto fail;
+	}
+
+	status = nss_gre_tx_buf(gre_ctx, if_number, skb);
+	if (unlikely(status != NSS_TX_SUCCESS)) {
+		nss_connmgr_gre_info("%px: NSS GRE could not send packet to NSS %d\n", dev, if_number);
+		goto fail;
+	}
+
+	return NETDEV_TX_OK;
+
+fail:
+	dev->stats.tx_dropped++;
+	dev_kfree_skb_any(skb);
+	return NETDEV_TX_OK;
+}
+
+/*
+ * nss_connmgr_gre_get_dev_stats64()
+ *	To get the netdev stats
+ */
+static struct rtnl_link_stats64 *nss_connmgr_gre_get_dev_stats64(struct net_device *dev,
+						struct rtnl_link_stats64 *tot)
+{
+	uint64_t rx_packets, rx_bytes, tx_packets, tx_bytes;
+	unsigned int start;
+	int i;
+	for_each_possible_cpu(i) {
+		const struct pcpu_sw_netstats *tstats = per_cpu_ptr(dev->tstats, i);
+
+		do {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))
+			start = u64_stats_fetch_begin_bh(&tstats->syncp);
+#else
+			start = u64_stats_fetch_begin_irq(&tstats->syncp);
+#endif
+			rx_packets = tstats->rx_packets;
+			tx_packets = tstats->tx_packets;
+			rx_bytes = tstats->rx_bytes;
+			tx_bytes = tstats->tx_bytes;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))
+		} while (u64_stats_fetch_retry_bh(&tstats->syncp, start));
+#else
+		} while (u64_stats_fetch_retry_irq(&tstats->syncp, start));
+#endif
+
+		tot->rx_packets += rx_packets;
+		tot->tx_packets += tx_packets;
+		tot->rx_bytes   += rx_bytes;
+		tot->tx_bytes   += tx_bytes;
+
+		tot->rx_dropped = dev->stats.rx_dropped;
+		tot->tx_dropped = dev->stats.tx_dropped;
+	}
+
+	return tot;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0))
+/*
+ * nss_connmgr_gre_dev_stats64()
+ *	Netdev ops function to retrieve stats for kernel version < 4.6
+ */
+static struct rtnl_link_stats64 *nss_connmgr_gre_dev_stats64(struct net_device *dev,
+						struct rtnl_link_stats64 *tot)
+{
+	return nss_connmgr_gre_get_dev_stats64(dev, tot);
+}
+#else
+/*
+ * nss_connmgr_gre_dev_stats64()
+ *	Netdev ops function to retrieve stats
+ */
+static void nss_connmgr_gre_dev_stats64(struct net_device *dev,
+						struct rtnl_link_stats64 *tot)
+{
+	nss_connmgr_gre_get_dev_stats64(dev, tot);
+}
+#endif
+
+/*
+ * nss_connmgr_gre_dev_open()
+ *	Netdev ops function to open netdevice.
+ */
+int nss_connmgr_gre_dev_open(struct net_device *dev)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_gre_msg req;
+	struct nss_gre_linkup_msg *linkup = &req.msg.linkup;
+	struct nss_gre_linkdown_msg *linkdown = &req.msg.linkdown;
+	nss_tx_status_t status;
+	int32_t inner_if, outer_if;
+
+	inner_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER);
+	if (inner_if < 0) {
+		return -EINVAL;
+	}
+
+	outer_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER);
+	if (outer_if < 0) {
+		return -EINVAL;
+	}
+
+	nss_ctx = nss_gre_get_context();
+
+	memset(&req, 0, sizeof(struct nss_gre_msg));
+
+	/*
+	 * Open inner interface
+	 */
+	linkup->if_number = inner_if;
+	nss_gre_msg_init(&req, inner_if, NSS_IF_OPEN, sizeof(struct nss_gre_linkup_msg), NULL, NULL);
+
+	status = nss_gre_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_info("%px: open failed for inner interface %s", dev, dev->name);
+		return -EFAULT;
+	}
+
+	/*
+	 * Open outer interface
+	 */
+	linkup->if_number = outer_if;
+	nss_gre_msg_init(&req, outer_if, NSS_IF_OPEN, sizeof(struct nss_gre_linkup_msg), NULL, NULL);
+
+	status = nss_gre_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_info("%px: open failed for outer interface %s", dev, dev->name);
+		linkdown->if_number = inner_if;
+		nss_gre_msg_init(&req, inner_if, NSS_IF_CLOSE, sizeof(struct nss_gre_linkdown_msg), NULL, NULL);
+		status = nss_gre_tx_msg_sync(nss_ctx, &req);
+		if (status != NSS_TX_SUCCESS) {
+			nss_connmgr_gre_info("%px: close failed for inner interface %s", dev, dev->name);
+		}
+		return -EFAULT;
+	}
+
+	netif_start_queue(dev);
+	return 0;
+}
+EXPORT_SYMBOL(nss_connmgr_gre_dev_open);
+
+/*
+ * nss_connmgr_gre_dev_close()
+ *	Netdevice ops function to close netdevice.
+ */
+int nss_connmgr_gre_dev_close(struct net_device *dev)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_gre_msg req;
+	struct nss_gre_linkdown_msg *linkdown = &req.msg.linkdown;
+	struct nss_gre_linkup_msg *linkup = &req.msg.linkup;
+	nss_tx_status_t status;
+	int32_t inner_if, outer_if;
+
+	netif_stop_queue(dev);
+
+	inner_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER);
+	if (inner_if < 0) {
+		nss_connmgr_gre_info("%px: close failed for interface %s, inner interface: %d not valid", dev, dev->name, inner_if);
+		return -EINVAL;
+	}
+
+	outer_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER);
+	if (outer_if < 0) {
+		nss_connmgr_gre_info("%px: close failed for interface %s, outer interface: %d not valid", dev, dev->name, inner_if);
+		return -EINVAL;
+	}
+
+	nss_ctx = nss_gre_get_context();
+
+	memset(&req, 0, sizeof(struct nss_gre_msg));
+
+	/*
+	 * Close inner interface
+	 */
+	linkdown->if_number = inner_if;
+	nss_gre_msg_init(&req, inner_if, NSS_IF_CLOSE, sizeof(struct nss_gre_linkdown_msg), NULL, NULL);
+
+	status = nss_gre_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_info("%px: close failed for inner interface %s", dev, dev->name);
+		return -EFAULT;
+	}
+
+	/*
+	 * Close outer interface
+	 */
+	linkdown->if_number = outer_if;
+	nss_gre_msg_init(&req, outer_if, NSS_IF_CLOSE, sizeof(struct nss_gre_linkdown_msg), NULL, NULL);
+
+	status = nss_gre_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_info("%px: close failed for outer interface %s", dev, dev->name);
+		linkup->if_number = inner_if;
+		nss_gre_msg_init(&req, inner_if, NSS_IF_OPEN, sizeof(struct nss_gre_linkup_msg), NULL, NULL);
+		status = nss_gre_tx_msg_sync(nss_ctx, &req);
+		if (status != NSS_TX_SUCCESS) {
+			nss_connmgr_gre_info("%px: open failed for inner interface %s", dev, dev->name);
+		}
+		return -EFAULT;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(nss_connmgr_gre_dev_close);
+
+/*
+ * Tap net device ops
+ */
+static const struct net_device_ops nss_connmgr_gre_tap_ops = {
+	.ndo_init = nss_connmgr_gre_dev_init,
+	.ndo_uninit = nss_connmgr_gre_dev_uninit,
+	.ndo_open = nss_connmgr_gre_dev_open,
+	.ndo_stop = nss_connmgr_gre_dev_close,
+	.ndo_set_mac_address = eth_mac_addr,
+	.ndo_validate_addr = eth_validate_addr,
+	.ndo_change_mtu	= nss_connmgr_gre_dev_change_mtu,
+	.ndo_start_xmit = nss_connmgr_gre_dev_xmit,
+	.ndo_get_stats64 = nss_connmgr_gre_dev_stats64,
+};
+
+/*
+ * Tun netdevice ops
+ */
+static const struct net_device_ops nss_connmgr_gre_tun_ops = {
+	.ndo_init = nss_connmgr_gre_dev_init,
+	.ndo_uninit = nss_connmgr_gre_dev_uninit,
+	.ndo_open = nss_connmgr_gre_dev_open,
+	.ndo_stop = nss_connmgr_gre_dev_close,
+	.ndo_change_mtu	= nss_connmgr_gre_dev_change_mtu,
+	.ndo_start_xmit = nss_connmgr_gre_dev_xmit,
+	.ndo_get_stats64 = nss_connmgr_gre_dev_stats64,
+};
+
+/*
+ * nss_connmgr_gre_tun_setup()
+ */
+static void nss_connmgr_gre_tun_setup(struct net_device *dev)
+{
+	dev->addr_len = 4;
+	dev->flags = IFF_NOARP | IFF_POINTOPOINT;
+	dev->priv_flags	&= ~IFF_XMIT_DST_RELEASE;
+	dev->netdev_ops = &nss_connmgr_gre_tun_ops;
+}
+
+/*
+ * nss_connmgr_gre_tap_setup()
+ */
+static void nss_connmgr_gre_tap_setup(struct net_device *dev)
+{
+	dev->netdev_ops = &nss_connmgr_gre_tap_ops;
+	eth_hw_addr_random(dev);
+}
+
+/*
+ * nss_connmgr_gre_prepare_config_cmd()
+ *	Retrieve info from netdevie and fill it in config message to NSS.
+ */
+static int32_t nss_connmgr_gre_prepare_config_cmd(struct net_device *dev,
+						      struct nss_gre_msg *req,
+						      struct net_device **next_dev,
+						      bool hold)
+{
+	struct nss_gre_config_msg *cmsg = &req->msg.cmsg;
+
+	if ((dev->type == ARPHRD_ETHER) && (dev->priv_flags_ext & IFF_EXT_GRE_V4_TAP)) {
+		cmsg->mode = NSS_GRE_MODE_TAP;
+		cmsg->ip_type = NSS_GRE_IP_IPV4;
+		if (enable_unalign) {
+			cmsg->flags |= NSS_GRE_CONFIG_USE_UNALIGNED;
+		}
+		return nss_connmgr_gre_v4_get_config(dev, req, next_dev, hold);
+	}
+
+	if ((dev->type == ARPHRD_ETHER) && (dev->priv_flags_ext & IFF_EXT_GRE_V6_TAP)) {
+		cmsg->mode = NSS_GRE_MODE_TAP;
+		cmsg->ip_type = NSS_GRE_IP_IPV6;
+		if (enable_unalign) {
+			cmsg->flags |= NSS_GRE_CONFIG_USE_UNALIGNED;
+		}
+		return nss_connmgr_gre_v6_get_config(dev, req, next_dev, hold);
+	}
+
+	if (dev->type == ARPHRD_IPGRE) {
+		cmsg->mode = NSS_GRE_MODE_TUN;
+		cmsg->ip_type = NSS_GRE_IP_IPV4;
+		return nss_connmgr_gre_v4_get_config(dev, req, next_dev, hold);
+	}
+
+	if (dev->type == ARPHRD_IP6GRE) {
+		cmsg->mode = NSS_GRE_MODE_TUN;
+		cmsg->ip_type = NSS_GRE_IP_IPV6;
+		return nss_connmgr_gre_v6_get_config(dev, req, next_dev, hold);
+	}
+
+	return GRE_ERR_NOT_GRE_NETDEV;
+}
+
+/*
+ * nss_connmgr_gre_tap_inner_exception()
+ * 	Exception handler for GRETAP inner device
+ *
+ * These are the packets exceptioned after decapsulation,
+ * and we can send the packet to linux after modifying
+ * some skb fields.
+ */
+static void nss_connmgr_gre_tap_inner_exception(struct net_device *dev, struct sk_buff *skb,
+					  __attribute__((unused)) struct napi_struct *napi)
+{
+
+	struct ethhdr *eth_hdr = (struct ethhdr *)skb->data;
+
+	nss_connmgr_gre_trace("%px: eth_hdr->h_proto: %d\n", dev, eth_hdr->h_proto);
+
+	if (likely(ntohs(eth_hdr->h_proto) >= ETH_P_802_3_MIN)) {
+		switch (ntohs(eth_hdr->h_proto)) {
+		case ETH_P_IP:
+		case ETH_P_IPV6:
+			/*
+		 	 * These are decapped packets.
+		 	 */
+			skb->protocol = eth_type_trans(skb, dev);
+			netif_receive_skb(skb);
+			return;
+		default:
+			break;
+		}
+	}
+
+	/*
+	 * These are decapped and exceptioned non IP packets.
+	 */
+	skb->protocol = eth_type_trans(skb, dev);
+	netif_receive_skb(skb);
+	return;
+}
+
+/*
+ * nss_connmgr_gre_tap_outer_exception()
+ * 	Exception handler for GRETAP outer device
+ *
+ * These are the packets exceptioned after encapsulation,
+ * and we need to remove the GRE header of the packet and
+ * pass it to linux.
+ */
+static void nss_connmgr_gre_tap_outer_exception(struct net_device *dev, struct sk_buff *skb,
+					  __attribute__((unused)) struct napi_struct *napi)
+{
+
+	struct ethhdr *eth_hdr;
+
+	eth_hdr = (struct ethhdr *)skb->data;
+	nss_connmgr_gre_trace("%px: eth_hdr->h_proto: %d\n", dev, eth_hdr->h_proto);
+	if (likely(ntohs(eth_hdr->h_proto) >= ETH_P_802_3_MIN)) {
+		switch (ntohs(eth_hdr->h_proto)) {
+		case ETH_P_IP:
+			return nss_connmgr_gre_tap_v4_outer_exception(dev, skb);
+		case ETH_P_IPV6:
+			return nss_connmgr_gre_tap_v6_outer_exception(dev, skb);
+		default:
+			nss_connmgr_gre_warning("%px: invalid skb received:%px with protocol: %d. Freeing the skb.\n", dev, skb, ntohs(eth_hdr->h_proto));
+			dev_kfree_skb_any(skb);
+		}
+	}
+}
+
+/*
+ * nss_connmgr_gre_tun_inner_exception()
+ * 	Exception handler for GRETUN inner device
+ *
+ * These are the packets exceptioned after decapsulation,
+ * and we can send the packet to linux after modifying
+ * some skb fields.
+ */
+static void nss_connmgr_gre_tun_inner_exception(struct net_device *dev, struct sk_buff *skb,
+					  __attribute__((unused)) struct napi_struct *napi)
+{
+	struct iphdr *iph;
+
+	iph = (struct iphdr *)skb->data;
+	switch (iph->version) {
+	case 4:
+		skb->protocol = htons(ETH_P_IP);
+		break;
+	case 6:
+		skb->protocol = htons(ETH_P_IPV6);
+		break;
+	default:
+		nss_connmgr_gre_warning("%px: wrong IP version set to skb:%px\n", dev, skb);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	skb->pkt_type = PACKET_HOST;
+	skb->dev = dev;
+	netif_receive_skb(skb);
+}
+
+/*
+ * nss_connmgr_gre_tun_outer_exception()
+ * 	Exception handler for GRETUN outer device
+ *
+ * These are the packets exceptioned after encapsulation,
+ * and we need to remove the GRE header of the packet and
+ * pass it to linux.
+ */
+static void nss_connmgr_gre_tun_outer_exception(struct net_device *dev, struct sk_buff *skb,
+					  __attribute__((unused)) struct napi_struct *napi)
+{
+	struct iphdr *iph;
+
+	iph = (struct iphdr *)skb->data;
+	switch (iph->version) {
+	case 4:
+		return nss_connmgr_gre_tun_v4_outer_exception(dev, skb);
+	case 6:
+		return nss_connmgr_gre_tun_v6_outer_exception(dev, skb);
+	default:
+		nss_connmgr_gre_warning("%px: wrong IP version set to skb:%px\n", dev, skb);
+		dev_kfree_skb_any(skb);
+		break;
+	}
+}
+
+/*
+ * nss_connmgr_gre_rx_pkt()
+ *	GRE Tap function to receive packet from NSS.
+ */
+static void nss_connmgr_gre_rx_pkt(struct net_device *dev, struct sk_buff *skb,
+				       __attribute__((unused)) struct napi_struct *napi)
+{
+	skb->dev = dev;
+	skb->protocol = eth_type_trans(skb, dev);
+	netif_receive_skb(skb);
+}
+
+/*
+ * nss_connmgr_gre_event_receive()
+ *	Event Callback to receive events from NSS
+ */
+static void nss_connmgr_gre_event_receive(void *if_ctx, struct nss_gre_msg *tnlmsg)
+{
+	struct net_device *dev = if_ctx;
+	struct nss_cmn_node_stats *stats = &tnlmsg->msg.sstats.node_stats;
+	struct pcpu_sw_netstats *tstats;
+	enum nss_dynamic_interface_type interface_type;
+
+	switch (tnlmsg->cm.type) {
+	case NSS_GRE_MSG_SESSION_STATS:
+		interface_type = nss_dynamic_interface_get_type(nss_gre_get_context(), tnlmsg->cm.interface);
+		tstats = this_cpu_ptr(dev->tstats);
+		u64_stats_update_begin(&tstats->syncp);
+		if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER) {
+			tstats->tx_packets += stats->tx_packets;
+			tstats->tx_bytes += stats->tx_bytes;
+		} else if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER) {
+			tstats->rx_packets += stats->rx_packets;
+			tstats->rx_bytes += stats->rx_bytes;
+		}
+		u64_stats_update_end(&tstats->syncp);
+		dev->stats.rx_dropped += nss_cmn_rx_dropped_sum(stats);
+		break;
+
+	case NSS_GRE_MSG_BASE_STATS:
+		break;
+
+	default:
+		nss_connmgr_gre_info("%px: Unknown Event from NSS\n", dev);
+		break;
+	}
+}
+
+/*
+ * nss_connmgr_gre_make_name()
+ *	Generate a name for netdevice if user does not provide one.
+ */
+static void nss_connmgr_gre_make_name(struct nss_connmgr_gre_cfg *cfg, char *name)
+{
+	switch (cfg->mode) {
+	case GRE_MODE_TUN:
+		strlcpy(name, "tun-%d", IFNAMSIZ);
+		break;
+	case GRE_MODE_TAP:
+		strlcpy(name, "tap-%d", IFNAMSIZ);
+		break;
+	default:
+		break;
+	}
+}
+
+/*
+ * __nss_connmgr_gre_create_interface()
+ *	Creates GRE Tap/Tun netdevice and configure GRE node in NSS.
+ *	This should be called after acquiring rtnl_lock().
+ */
+static struct net_device *__nss_connmgr_gre_create_interface(struct nss_connmgr_gre_cfg *cfg,
+							     enum nss_connmgr_gre_err_codes *err_code)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct net_device *dev = NULL;
+	struct net_device *next_dev_inner = NULL;
+	struct net_device *next_dev_outer = NULL;
+	struct nss_gre_iface_instance *ngii;
+	struct nss_gre_msg req;
+	struct nss_gre_config_msg *cmsg = &req.msg.cmsg;
+	nss_connmgr_gre_priv_t *priv;
+	nss_tx_status_t status;
+	uint32_t features = 0;
+	int32_t inner_if, outer_if;
+	char name[IFNAMSIZ] = {0};
+	int ret = -1, retry, next_if_num_inner = 0, next_if_num_outer = 0;
+
+	if (cfg->name) {
+		strlcpy(name, cfg->name, IFNAMSIZ);
+	} else {
+		nss_connmgr_gre_make_name(cfg, name);
+	}
+
+	switch (cfg->mode) {
+	case GRE_MODE_TUN:
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0))
+		dev = alloc_netdev(sizeof(nss_connmgr_gre_priv_t), name, nss_connmgr_gre_tun_setup);
+#else
+		dev = alloc_netdev(sizeof(nss_connmgr_gre_priv_t), name, NET_NAME_UNKNOWN, nss_connmgr_gre_tun_setup);
+#endif
+
+		if (!dev) {
+			nss_connmgr_gre_warning("Allocation of netdev failed\n");
+			*err_code = GRE_ERR_ALLOC_NETDEV;
+			return NULL;
+		}
+
+		if (cfg->is_ipv6) {
+			dev->type = ARPHRD_IP6GRE;
+			ret = nss_connmgr_gre_v6_set_config(dev, cfg);
+		} else {
+			dev->type = ARPHRD_IPGRE;
+			ret = nss_connmgr_gre_v4_set_config(dev, cfg);
+		}
+
+		break;
+
+	case GRE_MODE_TAP:
+		dev = alloc_etherdev(sizeof(nss_connmgr_gre_priv_t));
+		if (!dev) {
+			nss_connmgr_gre_warning("Allocation of netdev failed\n");
+			*err_code = GRE_ERR_ALLOC_NETDEV;
+			return NULL;
+		}
+
+		nss_connmgr_gre_tap_setup(dev);
+
+		if (cfg->is_ipv6) {
+			dev->priv_flags_ext |= IFF_EXT_GRE_V6_TAP;
+			ret = nss_connmgr_gre_v6_set_config(dev, cfg);
+		} else {
+			dev->priv_flags_ext |= IFF_EXT_GRE_V4_TAP;
+			ret = nss_connmgr_gre_v4_set_config(dev, cfg);
+		}
+		break;
+
+	default:
+		nss_connmgr_gre_warning("Please Specify gre mode\n");
+		*err_code = GRE_ERR_INVALID_MODE;
+		goto release_ref;
+	}
+
+	if (ret) {
+		nss_connmgr_gre_warning("%px: gre interface configuration failed\n", dev);
+		*err_code = ret;
+		goto release_ref;
+	}
+
+	/*
+	 * Set name
+	 */
+	memcpy(dev->name, name, IFNAMSIZ);
+
+	/*
+	 * Create config cmd for acceleration engine
+	 */
+	memset(&req, 0, sizeof(struct nss_gre_msg));
+	ret = nss_connmgr_gre_prepare_config_cmd(dev, &req, &next_dev_inner, true);
+	if (ret) {
+		nss_connmgr_gre_warning("%px: gre get config failed\n", dev);
+		*err_code = ret;
+		goto release_ref;
+	}
+
+	/*
+	 *  Replace MAC addr and next node with user provided entries.
+	 */
+	if (cfg->use_mac_hdr) {
+		memcpy(cmsg->src_mac, cfg->src_mac, ETH_ALEN);
+		memcpy(cmsg->dest_mac, cfg->dest_mac, ETH_ALEN);
+		cmsg->flags |= NSS_GRE_CONFIG_SET_MAC;
+	}
+
+	/*
+	 * If next_dev is NULL, then the set MAC
+	 * flag can not be set. Because the packet
+	 * will be forwarded to ipv4_rx/ipv6_rx
+	 */
+	if (!cfg->next_dev) {
+		cmsg->flags &= ~NSS_GRE_CONFIG_SET_MAC;
+	}
+
+	/*
+	 * By now, we should have valid MAC addresses
+	 */
+	if (!is_valid_ether_addr((const u8 *)cmsg->src_mac) ||
+	    !is_valid_ether_addr((const u8 *)cmsg->dest_mac)) {
+		nss_connmgr_gre_warning("%px: Could not find MAC address for src/dest IP\n", dev);
+		*err_code = GRE_ERR_INVALID_MAC;
+		goto release_ref;
+	}
+
+	/*
+	 * Configure the inner nexthop ifnum
+	 */
+	if (cfg->next_dev) {
+		/*
+		 * Release hold on GRE inner's nexthop that we have found,
+		 * since it has been passed explicitly via the cfg
+		 */
+		if (next_dev_inner) {
+			dev_put(next_dev_inner);
+		}
+
+		dev_hold(cfg->next_dev);
+
+		/*
+		 * TODO: Use the dynamic interface type for the inner's nexthop, in addition to the next_dev.
+		 */
+		next_if_num_inner = nss_cmn_get_interface_number_by_dev(cfg->next_dev);
+		next_dev_inner = cfg->next_dev;
+		if (next_if_num_inner < 0) {
+			nss_connmgr_gre_warning("%px: Next dev inner device= %s is not registered with ae engine\n",
+						dev, cfg->next_dev->name);
+			*err_code = GRE_ERR_NEXT_NODE_UNREG_IN_AE;
+			goto release_ref;
+		}
+
+		cmsg->flags |= NSS_GRE_CONFIG_NEXT_NODE_AVAILABLE;
+	}
+
+	/*
+	 * Configure the outer nexthop ifnum
+	 */
+	if (cfg->next_dev_outer) {
+		dev_hold(cfg->next_dev_outer);
+
+		/*
+		 * Verify if dynamic interface type is in range.
+		 */
+		if (cfg->outer_nss_if_type >= NSS_DYNAMIC_INTERFACE_TYPE_MAX) {
+			nss_connmgr_gre_warning("%px: invalid cfg, outer nexthop type %d is not in range\n",
+				       dev, cfg->outer_nss_if_type);
+			goto release_ref;
+		}
+
+		next_if_num_outer = nss_cmn_get_interface_number_by_dev_and_type(cfg->next_dev_outer, cfg->outer_nss_if_type);
+		next_dev_outer = cfg->next_dev_outer;
+
+		if (next_if_num_outer < 0) {
+			nss_connmgr_gre_warning("%px: Next dev outer device %s with dynamic if num %d not registered with NSS\n",
+					dev, cfg->next_dev_outer->name, next_if_num_outer);
+			*err_code = GRE_ERR_NEXT_NODE_UNREG_IN_AE;
+			goto release_ref;
+		}
+
+		/*
+		 * Get the NSS ctx for the outer next hop
+		 */
+		nss_ctx = nss_dynamic_interface_get_nss_ctx_by_type(cfg->outer_nss_if_type);
+		if (!nss_ctx) {
+			nss_connmgr_gre_warning("Could not get NSS context for type : %d\n", cfg->outer_nss_if_type);
+			goto release_ref;
+		}
+
+		/*
+		 * Append the core-id for the outer next hop ifnum
+		 */
+		next_if_num_outer = nss_cmn_append_core_id(nss_ctx, next_if_num_outer);
+		if (!next_if_num_outer) {
+			nss_connmgr_gre_warning("%px: Could not get interface number with core ID for outer nexthop device %s with core ID.\n",
+				       nss_ctx, next_dev_outer->name);
+			goto release_ref;
+		}
+
+		cmsg->flags |= NSS_GRE_CONFIG_NEXT_NODE_AVAILABLE;
+	}
+
+	/*
+	 * By now, we should have a valid next node for either inner or outer
+	 */
+	if (!(cmsg->flags & NSS_GRE_CONFIG_NEXT_NODE_AVAILABLE)) {
+		nss_connmgr_gre_warning("%px: Next dev is not available\n", dev);
+		*err_code = GRE_ERR_NO_NEXT_NETDEV;
+		goto release_ref;
+	}
+
+	if (cfg->add_padding) {
+		cmsg->flags |= NSS_GRE_CONFIG_SET_PADDING;
+	}
+
+	if (cfg->copy_metadata) {
+		cmsg->flags |= NSS_GRE_CONFIG_COPY_METADATA;
+		cmsg->metadata_size = sizeof(struct nss_wifi_append_statsv2_metahdr);
+	}
+
+	/*
+	 * Set per packet DSCP configuration if needed
+	 */
+	if (cfg->dscp_valid) {
+		cmsg->flags |= NSS_GRE_CONFIG_DSCP_VALID;
+	}
+
+	/*
+	 * Register net_device
+	 */
+	ret = register_netdevice(dev);
+	if (ret) {
+		*err_code = GRE_ERR_NETDEV_REG_FAILED;
+		nss_connmgr_gre_warning("%px: Netdevice registration failed\n", dev);
+		goto release_ref;
+	}
+
+	/*
+	 * Create GRE interface instance
+	 */
+	ngii = nss_connmgr_gre_alloc_instance(dev);
+	if (!ngii) {
+		nss_connmgr_gre_warning("%px: GRE interfacen intance creation failed\n", dev);
+		*err_code = GRE_ERR_ALLOC_GRE_INSTANCE;
+		goto unregister_netdev;
+	}
+
+	/*
+	 * Create nss outer dynamic interface
+	 */
+	outer_if = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER);
+	if (outer_if < 0) {
+		nss_connmgr_gre_warning("%px: Request interface number failed\n", dev);
+		*err_code = GRE_ERR_DYNMAIC_IFACE_CREATE;
+		goto free_gre_instance;
+	}
+
+	ngii->outer_ifnum = outer_if;
+	priv = (nss_connmgr_gre_priv_t *)netdev_priv(dev);
+	priv->next_dev_outer = next_dev_outer;
+
+	/*
+	 * Create nss inner dynamic interface
+	 */
+	inner_if = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER);
+	if (inner_if < 0) {
+		nss_connmgr_gre_warning("%px: Request interface number failed\n", dev);
+		*err_code = GRE_ERR_DYNMAIC_IFACE_CREATE;
+		goto free_gre_instance;
+	}
+
+	ngii->inner_ifnum = inner_if;
+	priv->next_dev_inner = next_dev_inner;
+	priv->nss_if_number_inner = inner_if;
+
+	/*
+	 * Register outer gre tunnel with NSS
+	 */
+	nss_ctx = nss_gre_register_if(outer_if,
+				NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER,
+				nss_connmgr_gre_rx_pkt,
+	 			nss_connmgr_gre_event_receive,
+				dev,
+				features);
+	if (!nss_ctx) {
+		nss_connmgr_gre_info("%px: nss_register_gre_if failed\n", dev);
+		*err_code = GRE_ERR_GRE_IFACE_REG;
+		goto dealloc_inner_node;
+	}
+
+	/*
+	 * Register inner gre tunnel with NSS
+	 */
+	nss_ctx = nss_gre_register_if(inner_if,
+				NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER,
+				nss_connmgr_gre_rx_pkt,
+	 			nss_connmgr_gre_event_receive,
+				dev,
+				features);
+	if (!nss_ctx) {
+		nss_connmgr_gre_info("%px: nss_register_gre_if failed\n", dev);
+		*err_code = GRE_ERR_GRE_IFACE_REG;
+		goto dealloc_inner_node;
+	}
+
+	nss_connmgr_gre_info("%px: nss_register_gre_if() custom successful. nss_ctx = %px. inner_if: %d, outer_if: %d\n", dev, nss_ctx, inner_if, outer_if);
+
+	/*
+	 * Send encap config to AE
+	 */
+	cmsg->flags &= ~NSS_GRE_CONFIG_NEXT_NODE_AVAILABLE;
+
+	/*
+	 * Configure nexthop to inner node if available
+	 */
+	if (next_if_num_inner) {
+		cmsg->next_node_if_num = next_if_num_inner;
+		cmsg->flags |= NSS_GRE_CONFIG_NEXT_NODE_AVAILABLE;
+	}
+	cmsg->sibling_if_num = outer_if;
+	nss_gre_msg_init(&req, inner_if, NSS_GRE_MSG_ENCAP_CONFIGURE, sizeof(struct nss_gre_config_msg), NULL, NULL);
+	nss_connmgr_gre_info("%px: NSS_GRE_MSG_ENCAP_CONFIGURE:: nss_ctx = %px, flags:0x%x, ikey:0x%x, okey:0x%x, mode:%x, next_node_if_num:%u, sibling_if_num:%u, ttl:%u, tos:%u, metadata_size:%u\n",
+			dev, nss_ctx, cmsg->flags, cmsg->ikey, cmsg->okey, cmsg->mode, cmsg->next_node_if_num, cmsg->sibling_if_num, cmsg->ttl, cmsg->tos, cmsg->metadata_size);
+	status = nss_gre_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		*err_code = GRE_ERR_AE_CONFIG_FAILED;
+		nss_connmgr_gre_info("%px: Send Encap config to AE failed\n", next_dev_inner);
+		goto unregister_nss_interface;
+	}
+
+	/*
+	 * Send decap config to AE
+	 */
+	cmsg->flags &= ~NSS_GRE_CONFIG_NEXT_NODE_AVAILABLE;
+
+	/*
+	 * Configure nexthop to outer node if available
+	 */
+	if (next_if_num_outer) {
+		cmsg->next_node_if_num = next_if_num_outer;
+		cmsg->flags |= NSS_GRE_CONFIG_NEXT_NODE_AVAILABLE;
+	}
+	cmsg->sibling_if_num = inner_if;
+	nss_gre_msg_init(&req, outer_if, NSS_GRE_MSG_DECAP_CONFIGURE, sizeof(struct nss_gre_config_msg), NULL, NULL);
+	nss_connmgr_gre_info("%px: NSS_GRE_MSG_DECAP_CONFIGURE:: nss_ctx = %px, flags:0x%x, ikey:0x%x, okey:0x%x, mode:%x, next_node_if_num:%u, sibling_if_num:%u, ttl:%u, tos:%u, metadata_size:%u\n",
+			dev, nss_ctx, cmsg->flags, cmsg->ikey, cmsg->okey, cmsg->mode, cmsg->next_node_if_num, cmsg->sibling_if_num, cmsg->ttl, cmsg->tos, cmsg->metadata_size);
+	status = nss_gre_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		*err_code = GRE_ERR_AE_CONFIG_FAILED;
+		nss_connmgr_gre_info("%px: Send decap config to AE failed\n", next_dev_outer);
+		goto unregister_nss_interface;
+	}
+
+	/*
+	 * Set vap next hop if next_dev is configured
+	 * TODO: Do this in a more generic manner by checking the dynamic interface type of next_dev
+	 */
+	if (cfg->next_dev) {
+		ret = nss_connmgr_gre_set_wifi_next_hop(cfg->next_dev);
+		if (ret) {
+			nss_connmgr_gre_info("%px: Setting next hop of wifi vdev failed\n", dev);
+			*err_code = ret;
+			goto unregister_nss_interface;
+		}
+	}
+
+	memcpy(&ngii->gre_cfg, cfg, sizeof(*cfg));
+	ngii->gre_iftype = NSS_CONNMGR_GRE_IFTYPE_CUSTOM_GRE;
+
+	spin_lock(&gre_connmgr_ctx.lock);
+	list_add(&ngii->list, &gre_connmgr_ctx.list);
+	spin_unlock(&gre_connmgr_ctx.lock);
+
+	/*
+	 * Success
+	 */
+	*err_code = GRE_SUCCESS;
+	return dev;
+
+unregister_nss_interface:
+	nss_gre_unregister_if(inner_if);
+	nss_gre_unregister_if(outer_if);
+
+	retry = 0;
+dealloc_inner_node:
+	status = nss_dynamic_interface_dealloc_node(inner_if, NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER);
+	if (status != NSS_TX_SUCCESS) {
+		if (++retry <= MAX_RETRY_COUNT) {
+			goto dealloc_inner_node;
+		}
+		nss_connmgr_gre_error("%px: Fatal Error, Unable to dealloc the node[%d] in the NSS FW!\n", dev, inner_if);
+	}
+
+	retry = 0;
+dealloc_outer_node:
+	status = nss_dynamic_interface_dealloc_node(outer_if, NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER);
+	if (status != NSS_TX_SUCCESS) {
+		if (++retry <= MAX_RETRY_COUNT) {
+			goto dealloc_outer_node;
+		}
+		nss_connmgr_gre_error("%px: Fatal Error, Unable to dealloc the node[%d] in the NSS FW!\n", dev, outer_if);
+	}
+
+free_gre_instance:
+	nss_connmgr_gre_free_instance(ngii);
+
+unregister_netdev:
+	unregister_netdevice(dev);
+
+release_ref:
+	if (next_dev_inner) {
+		dev_put(next_dev_inner);
+	}
+
+	if (next_dev_outer) {
+		dev_put(next_dev_outer);
+	}
+
+	return dev;
+}
+
+/*
+ * nss_connmgr_gre_destroy_inner_interface()
+ *	Destroy inner GRE Tap/Tun interface.
+ */
+static enum nss_connmgr_gre_err_codes nss_connmgr_gre_destroy_inner_interface(struct net_device *dev, int interface_num)
+{
+	struct nss_gre_msg req;
+	struct nss_gre_deconfig_msg *dmsg;
+	nss_tx_status_t status;
+	int retry = 0;
+
+	memset(&req, 0, sizeof(struct nss_gre_msg));
+	dmsg = &req.msg.dmsg;
+	dmsg->if_number = interface_num;
+
+deconfig_inner:
+	nss_gre_msg_init(&req, interface_num, NSS_GRE_MSG_ENCAP_DECONFIGURE, sizeof(struct nss_gre_deconfig_msg), NULL, NULL);
+	status = nss_gre_tx_msg_sync(nss_gre_get_context(), &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_info("%px: gre instance deconfigure command failed, interface_num = %d\n", dev, interface_num);
+
+		if (++retry <= MAX_RETRY_COUNT) {
+			goto deconfig_inner;
+		}
+
+		nss_connmgr_gre_error("%px: Fatal Error, failed to send GRE deconfig command to NSS\n", dev);
+		return GRE_ERR_AE_DECONFIG_FAILED;
+	}
+	retry = 0;
+
+	nss_gre_unregister_if(interface_num);
+
+dealloc_inner:
+	status = nss_dynamic_interface_dealloc_node(interface_num, NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_info("%px: gre dealloc node failure for interface_num = %d\n", dev, interface_num);
+
+		if (++retry <= MAX_RETRY_COUNT) {
+			goto dealloc_inner;
+		}
+
+		nss_connmgr_gre_error("%px: Fatal Error, failed to send GRE dealloc command to NSS\n", dev);
+		return GRE_ERR_DYNMAIC_IFACE_DESTROY;
+	}
+
+	return GRE_SUCCESS;
+}
+
+/*
+ * nss_connmgr_gre_destroy_outer_interface()
+ *	Destroy outer GRE Tap/Tun interface.
+ */
+static enum nss_connmgr_gre_err_codes nss_connmgr_gre_destroy_outer_interface(struct net_device *dev, int interface_num)
+{
+	struct nss_gre_msg req;
+	struct nss_gre_deconfig_msg *dmsg;
+	nss_tx_status_t status;
+	int retry = 0;
+
+	memset(&req, 0, sizeof(struct nss_gre_msg));
+	dmsg = &req.msg.dmsg;
+	dmsg->if_number = interface_num;
+
+deconfig_outer:
+	nss_gre_msg_init(&req, interface_num, NSS_GRE_MSG_DECAP_DECONFIGURE, sizeof(struct nss_gre_deconfig_msg), NULL, NULL);
+	status = nss_gre_tx_msg_sync(nss_gre_get_context(), &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_info("%px: gre instance deconfigure command failed, interface_num = %d\n", dev, interface_num);
+
+		if (++retry <= MAX_RETRY_COUNT) {
+			goto deconfig_outer;
+		}
+
+		nss_connmgr_gre_error("%px: Fatal Error, failed to send GRE deconfig command to NSS\n", dev);
+		return GRE_ERR_AE_DECONFIG_FAILED;
+	}
+
+	nss_gre_unregister_if(interface_num);
+	retry = 0;
+
+dealloc_outer:
+	status = nss_dynamic_interface_dealloc_node(interface_num, NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_info("%px: gre dealloc node failure for inner_if = %d\n", dev, interface_num);
+
+		if (++retry <= MAX_RETRY_COUNT) {
+			goto dealloc_outer;
+		}
+
+		nss_connmgr_gre_error("%px: Fatal Error, failed to send GRE dealloc command to NSS\n", dev);
+		return GRE_ERR_DYNMAIC_IFACE_DESTROY;
+	}
+
+	return GRE_SUCCESS;
+}
+
+/*
+ * __nss_connmgr_gre_destroy_interface()
+ *	Destroy GRE Tap/Tun netdevice. Acquire rtnl_lock() before calling this
+ *	function.
+ */
+static enum nss_connmgr_gre_err_codes __nss_connmgr_gre_destroy_interface(struct net_device *dev)
+{
+	struct nss_gre_iface_instance *ngii;
+	nss_connmgr_gre_priv_t *priv;
+	enum nss_connmgr_gre_err_codes ret;
+
+	netif_tx_disable(dev);
+
+	ngii = nss_connmgr_gre_find_instance(dev);
+	if(!ngii) {
+		nss_connmgr_gre_warning("%px: GRE interface instance is not found.\n", dev);
+		return GRE_ERR_NO_GRE_INSTANCE;
+	}
+
+	/*
+	 * Decrement ref to next_dev
+	 */
+	priv = (nss_connmgr_gre_priv_t *)netdev_priv(dev);
+	if (priv->next_dev_inner) {
+		dev_put(priv->next_dev_inner);
+	}
+
+	if (priv->next_dev_outer) {
+		dev_put(priv->next_dev_outer);
+	}
+
+	ret = nss_connmgr_gre_destroy_inner_interface(dev, ngii->inner_ifnum);
+	if (ret != GRE_SUCCESS) {
+		nss_connmgr_gre_warning("%px: failed to destroy inner interface: %d\n", dev, ngii->inner_ifnum);
+		return ret;
+	}
+
+	ret = nss_connmgr_gre_destroy_outer_interface(dev, ngii->outer_ifnum);
+	if (ret != GRE_SUCCESS) {
+		nss_connmgr_gre_warning("%px: failed to destroy outer interface: %d\n", dev, ngii->outer_ifnum);
+		return ret;
+	}
+
+	nss_connmgr_gre_info("%px: deleted gre instance, inner_if = %d outer_if = %d\n",
+			dev, ngii->inner_ifnum, ngii->outer_ifnum);
+
+	nss_connmgr_gre_free_instance(ngii);
+	unregister_netdevice(dev);
+	return GRE_SUCCESS;
+}
+
+/*
+ * nss_connmgr_gre_validate_config()
+ *	No support for CSUM, SEQ number.
+ */
+static bool nss_connmgr_gre_validate_config(struct nss_connmgr_gre_cfg *cfg)
+{
+	/*
+	 * TODO:Disallow key for standard GRE TAP/TUN.
+	 */
+	if (cfg->iseq_valid || cfg->oseq_valid || cfg->icsum_valid || cfg->ocsum_valid) {
+		nss_connmgr_gre_info("Bad config, seq and csum are not supported.\n");
+		return false;
+	}
+
+	/*
+	 * Validate DSCP and ToS inherit flags.
+	 */
+	if (cfg->dscp_valid && cfg->tos_inherit) {
+		nss_connmgr_gre_info("Bad config, Both DSCP and ToS inherit flags are set.\n");
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_connmgr_gre_dev_up()
+ *	Netdevice notifier call back to configure NSS for GRE Tap/Tun device.
+ */
+static int nss_connmgr_gre_dev_up(struct net_device *dev)
+{
+	struct nss_gre_msg req;
+	struct nss_gre_config_msg *cmsg = &req.msg.cmsg;
+	int inner_if, outer_if;
+	uint32_t features = 0;
+	struct nss_ctx_instance *nss_ctx = NULL;
+	nss_tx_status_t status;
+	struct net_device *next_dev = NULL;
+
+	/*
+	 * If GRE interface instance is found return, dev is Custom GRE interface type.
+	 */
+	if (nss_connmgr_gre_find_instance(dev)) {
+		nss_connmgr_gre_info("%px: Custom GRE interface is up.\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Create config cmd for acceleration engine
+	 */
+	memset(&req, 0, sizeof(struct nss_gre_msg));
+	if (nss_connmgr_gre_prepare_config_cmd(dev, &req, &next_dev, false)) {
+		nss_connmgr_gre_info("%px: gre tunnel get config failed\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Ignore set_mac and next_dev flags for generic GRE
+	 */
+	cmsg->flags &= ~(NSS_GRE_CONFIG_SET_MAC | NSS_GRE_CONFIG_NEXT_NODE_AVAILABLE);
+
+	/*
+	 * Create nss outer dynamic interface
+	 */
+	outer_if = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER);
+	if (outer_if < 0) {
+		nss_connmgr_gre_warning("%px: Request interface number failed\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Create nss inner dynamic interface
+	 */
+	inner_if = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER);
+	if (inner_if < 0) {
+		nss_connmgr_gre_warning("%px: Request interface number failed\n", dev);
+		goto dealloc_outer;
+	}
+
+	/*
+	 * Register gre inner/outer interface with NSS
+	 */
+	if ((dev->type == ARPHRD_IPGRE) || (dev->type == ARPHRD_IP6GRE)) {
+		/*
+		 * GRE Tunnel mode
+		 */
+		nss_ctx = nss_gre_register_if(inner_if,
+				NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER,
+				nss_connmgr_gre_tun_inner_exception,
+				nss_connmgr_gre_event_receive,
+				dev,
+				features);
+
+		if (!nss_ctx) {
+			nss_connmgr_gre_info("%px: nss_register_gre_if failed\n", dev);
+			goto dealloc_inner;
+		}
+
+		nss_ctx = nss_gre_register_if(outer_if,
+				NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER,
+				nss_connmgr_gre_tun_outer_exception,
+				nss_connmgr_gre_event_receive,
+				dev,
+				features);
+	} else {
+		/*
+		 * GRE Tap mode
+		 */
+		nss_ctx = nss_gre_register_if(inner_if,
+				NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER,
+				nss_connmgr_gre_tap_inner_exception,
+				nss_connmgr_gre_event_receive,
+				dev,
+				features);
+
+		if (!nss_ctx) {
+			nss_connmgr_gre_info("%px: nss_register_gre_if failed\n", dev);
+			goto dealloc_inner;
+		}
+
+		nss_ctx = nss_gre_register_if(outer_if,
+				NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER,
+				nss_connmgr_gre_tap_outer_exception,
+				nss_connmgr_gre_event_receive,
+				dev,
+				features);
+	}
+
+	if (!nss_ctx) {
+		nss_connmgr_gre_info("%px: nss_register_gre_if failed\n", dev);
+		goto unregister_inner;
+	}
+
+	nss_connmgr_gre_info("%px: nss_register_gre_if() standard successful. nss_ctx = %px. inner_if: %d, outer_if: %d\n", dev, nss_ctx, inner_if, outer_if);
+
+	/*
+	 * Send configure command for inner interface
+	 */
+	cmsg->sibling_if_num = outer_if;
+	nss_gre_msg_init(&req, inner_if, NSS_GRE_MSG_ENCAP_CONFIGURE, sizeof(struct nss_gre_config_msg), NULL, NULL);
+	nss_connmgr_gre_info("%px: NSS_GRE_MSG_ENCAP_CONFIGURE:: nss_ctx = %px, flags:0x%x, ikey:0x%x, okey:0x%x, mode:%x, next_node_if_num:%u, sibling_if_num:%u, ttl:%u, tos:%u, metadata_size:%u\n",
+			dev, nss_ctx, cmsg->flags, cmsg->ikey, cmsg->okey, cmsg->mode, cmsg->next_node_if_num, cmsg->sibling_if_num, cmsg->ttl, cmsg->tos, cmsg->metadata_size);
+	status = nss_gre_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_warning("%px: nss gre std configure command error %d\n", dev, status);
+		goto unregister_outer;
+	}
+
+	/*
+	 * Send configure command for outer interface
+	 */
+	cmsg->sibling_if_num = inner_if;
+	nss_gre_msg_init(&req, outer_if, NSS_GRE_MSG_DECAP_CONFIGURE, sizeof(struct nss_gre_config_msg), NULL, NULL);
+	nss_connmgr_gre_info("%px: NSS_GRE_MSG_DECAP_CONFIGURE:: nss_ctx = %px, flags:0x%x, ikey:0x%x, okey:0x%x, mode:%x, next_node_if_num:%u, sibling_if_num:%u, ttl:%u, tos:%u, metadata_size:%u\n",
+			dev, nss_ctx, cmsg->flags, cmsg->ikey, cmsg->okey, cmsg->mode, cmsg->next_node_if_num, cmsg->sibling_if_num, cmsg->ttl, cmsg->tos, cmsg->metadata_size);
+	status = nss_gre_tx_msg_sync(nss_ctx, &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_warning("%px: nss gre std configure command error %d\n", dev, status);
+		goto unregister_outer;
+	}
+
+	/*
+	 * Open the netdev to accept packets
+	 */
+	if (nss_connmgr_gre_dev_open(dev)) {
+		nss_connmgr_gre_warning("%px: nss gre std device up command failed %d\n", dev, status);
+		goto unregister_outer;
+	}
+
+	return NOTIFY_DONE;
+
+unregister_outer:
+	nss_gre_unregister_if(outer_if);
+
+unregister_inner:
+	nss_gre_unregister_if(inner_if);
+
+dealloc_inner:
+	status = nss_dynamic_interface_dealloc_node(inner_if, NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_warning("%px: Unable to dealloc the node[%d] in the NSS fw!\n", dev, inner_if);
+	}
+
+dealloc_outer:
+	status = nss_dynamic_interface_dealloc_node(outer_if, NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_warning("%px: Unable to dealloc the node[%d] in the NSS fw!\n", dev, outer_if);
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_connmgr_gre_dev_down()
+ *	Netdevice notifier call back to destroy GRE interface in NSS.
+ */
+static int nss_connmgr_gre_dev_down(struct net_device *dev)
+{
+	struct nss_gre_msg req;
+	struct nss_gre_deconfig_msg *dmsg;
+	int inner_if, outer_if;
+	nss_tx_status_t status;
+
+	/*
+	 * If GRE interface instance is found return, dev is Custom GRE interface type.
+	 */
+	if (nss_connmgr_gre_find_instance(dev)) {
+		nss_connmgr_gre_info("%px: Custom GRE interface is down.\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Check if gre inner interface is registered with NSS
+	 */
+	inner_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER);
+	if (inner_if < 0) {
+		nss_connmgr_gre_info("%px: Net device is not registered with nss\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	outer_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER);
+	if (outer_if < 0) {
+		nss_connmgr_gre_info("%px: Net device is not registered with nss\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	memset(&req, 0, sizeof(struct nss_gre_msg));
+	dmsg = &req.msg.dmsg;
+	dmsg->if_number = inner_if;
+	nss_gre_msg_init(&req, inner_if, NSS_GRE_MSG_ENCAP_DECONFIGURE, sizeof(struct nss_gre_deconfig_msg), NULL, NULL);
+	status = nss_gre_tx_msg_sync(nss_gre_get_context(), &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_info("%px: gre instance deconfigure command fo encap failed, inner_if = %d\n", dev, inner_if);
+		return NOTIFY_DONE;
+	}
+
+	dmsg->if_number = outer_if;
+	nss_gre_msg_init(&req, outer_if, NSS_GRE_MSG_DECAP_DECONFIGURE, sizeof(struct nss_gre_deconfig_msg), NULL, NULL);
+	status = nss_gre_tx_msg_sync(nss_gre_get_context(), &req);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_info("%px: gre instance deconfigure command for decap failed, inner_if = %d\n", dev, inner_if);
+		return NOTIFY_DONE;
+	}
+
+	if (nss_connmgr_gre_dev_close(dev)) {
+		nss_connmgr_gre_info("%px: gre instance device close command failed, inner_if = %d\n", dev, inner_if);
+		return NOTIFY_DONE;
+	}
+
+	nss_gre_unregister_if(inner_if);
+	status = nss_dynamic_interface_dealloc_node(inner_if, NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_info("%px: gre dealloc node failure for inner_if = %d\n", dev, inner_if);
+		return NOTIFY_DONE;
+	}
+	nss_connmgr_gre_info("%px: deleting gre instance, inner_if = %d\n", dev, inner_if);
+
+	nss_gre_unregister_if(outer_if);
+	status = nss_dynamic_interface_dealloc_node(outer_if, NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_info("%px: gre dealloc node failure for outer_if = %d\n", dev, outer_if);
+		return NOTIFY_DONE;
+	}
+	nss_connmgr_gre_info("%px: deleted gre instance, outer_if = %d\n", dev, outer_if);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_connmgr_gre_dev_event()
+ *	Netdevice notifier call back function.
+ */
+static int nss_connmgr_gre_dev_event(struct notifier_block  *nb,
+		unsigned long event, void  *dev)
+{
+	struct net_device *netdev;
+	netdev = netdev_notifier_info_to_dev(dev);
+
+	switch (event) {
+	case NETDEV_UP:
+		return nss_connmgr_gre_dev_up(netdev);
+
+	case NETDEV_DOWN:
+		return nss_connmgr_gre_dev_down(netdev);
+
+	default:
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * Linux Net device Notifier
+ */
+static struct notifier_block nss_connmgr_gre_notifier = {
+	.notifier_call = nss_connmgr_gre_dev_event,
+};
+
+/*
+ * nss_connmgr_gre_dev_init_module()
+ *	Tunnel gre module init function
+ */
+static int __init nss_connmgr_gre_dev_init_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+	INIT_LIST_HEAD(&gre_connmgr_ctx.list);
+	spin_lock_init(&gre_connmgr_ctx.lock);
+	register_netdevice_notifier(&nss_connmgr_gre_notifier);
+
+	return 0;
+}
+
+/*
+ * nss_connmgr_gre_exit_module
+ *	Tunnel gre module exit function
+ */
+static void __exit nss_connmgr_gre_exit_module(void)
+{
+	struct nss_gre_iface_instance *ngii, *n;
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return;
+	}
+#endif
+	/*
+	 * Unregister GRE interfaces created and delete interface
+	 * instances.
+	 */
+	list_for_each_entry_safe(ngii, n, &gre_connmgr_ctx.list, list) {
+		rtnl_lock();
+		__nss_connmgr_gre_destroy_interface(ngii->dev);
+		rtnl_unlock();
+	}
+
+	unregister_netdevice_notifier(&nss_connmgr_gre_notifier);
+}
+
+/*
+ * nss_connmgr_gre_set_next_hop()
+ *	Function changes next hop of wifi_vdev to NSS_GRE_INTERFACE
+ */
+int nss_connmgr_gre_set_wifi_next_hop(struct net_device *wifi_vdev)
+{
+	nss_tx_status_t status;
+	void *ctx;
+	int ifnumber;
+
+	if (!wifi_vdev) {
+		nss_connmgr_gre_info("wifi interface is NULL\n");
+		return GRE_ERR_NO_NEXT_NETDEV;
+	}
+
+	ifnumber = nss_cmn_get_interface_number_by_dev(wifi_vdev);
+	if (ifnumber < 0) {
+		nss_connmgr_gre_info("%px: wifi interface is not recognized by NSS\n", wifi_vdev);
+		return GRE_ERR_NEXT_NODE_UNREG_IN_AE;
+	}
+
+	ctx = nss_wifi_get_context();
+	status = nss_wifi_vdev_set_next_hop(ctx, ifnumber, NSS_GRE_INTERFACE);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_gre_info("%px: wifi drv api failed to set next hop\n", wifi_vdev);
+		return GRE_ERR_AE_SET_NEXT_HOP;
+	}
+
+	return GRE_SUCCESS;
+}
+
+/*
+ * nss_connmgr_gre_get_hlen()
+ *	Calculates GRE header length
+ */
+uint32_t nss_connmgr_gre_get_hlen(struct nss_connmgr_gre_cfg *cfg)
+{
+	uint32_t size = 4;	/* minimum size of GRE packet */
+
+	if (cfg->okey_valid) {
+		size += 4;
+	}
+
+	if (cfg->oseq_valid) {
+		size += 4;
+	}
+
+	if (cfg->ocsum_valid) {
+		size += 4;
+	}
+
+	return size;
+}
+
+/*
+ * nss_connmgr_gre_set_gre_flags()
+ *	Map User configured flags to tunnel specific flag.
+ */
+void nss_connmgr_gre_set_gre_flags(struct nss_connmgr_gre_cfg *cfg,
+					   uint16_t *o_flags, uint16_t *i_flags)
+
+{
+	if (cfg->ikey_valid) {
+		*i_flags |= TUNNEL_KEY;
+	}
+
+	if (cfg->okey_valid) {
+		*o_flags |= TUNNEL_KEY;
+	}
+
+	if (cfg->iseq_valid) {
+		*i_flags |= TUNNEL_SEQ;
+	}
+
+	if (cfg->oseq_valid) {
+		*o_flags |= TUNNEL_SEQ;
+	}
+
+	if (cfg->icsum_valid) {
+		*i_flags |= TUNNEL_CSUM;
+	}
+
+	if (cfg->ocsum_valid) {
+		*o_flags |= TUNNEL_CSUM;
+	}
+}
+
+/*
+ * nss_connmgr_gre_get_nss_config_flags()
+ *	Map tunnel specific flags to NSS flags.
+ */
+uint32_t nss_connmgr_gre_get_nss_config_flags(uint16_t o_flags, uint16_t i_flags,
+						  uint8_t tos, uint8_t ttl,
+						  uint16_t frag_off)
+{
+	uint32_t gre_flags = 0;
+
+	if (i_flags & TUNNEL_KEY) {
+		gre_flags |= NSS_GRE_CONFIG_IKEY_VALID;
+	}
+
+	if (o_flags & TUNNEL_KEY) {
+		gre_flags |= NSS_GRE_CONFIG_OKEY_VALID;
+	}
+
+	if (i_flags & TUNNEL_SEQ) {
+		gre_flags |= NSS_GRE_CONFIG_ISEQ_VALID;
+	}
+
+	if (o_flags & TUNNEL_SEQ) {
+		gre_flags |= NSS_GRE_CONFIG_OSEQ_VALID;
+	}
+
+	if (i_flags & TUNNEL_CSUM) {
+		gre_flags |= NSS_GRE_CONFIG_ICSUM_VALID;
+	}
+
+	if (o_flags & TUNNEL_CSUM) {
+		gre_flags |= NSS_GRE_CONFIG_OCSUM_VALID;
+	}
+
+	if (tos & 0x1) {
+		gre_flags |= NSS_GRE_CONFIG_TOS_INHERIT;
+	}
+
+	if (!ttl) {
+		gre_flags |= NSS_GRE_CONFIG_TTL_INHERIT;
+	}
+
+	if (frag_off == htons(IP_DF)) {
+		gre_flags |= NSS_GRE_CONFIG_SET_DF;
+	}
+
+	return gre_flags;
+}
+
+ /*
+  * nss_connmgr_gre_destroy_interface()
+  *	User API to delete interface
+  */
+enum nss_connmgr_gre_err_codes nss_connmgr_gre_destroy_interface(struct net_device *dev)
+{
+	enum nss_connmgr_gre_err_codes ret;
+
+	if (!dev) {
+		nss_connmgr_gre_info("Please specifiy valid interface to be deleted\n");
+		return GRE_ERR_NO_NETDEV;
+	}
+
+	if (in_interrupt()) {
+		nss_connmgr_gre_info("%px: nss_connmgr_gre_destroy_interface() called in interrupt context\n", dev);
+		return GRE_ERR_IN_INTERRUPT_CTX;
+	}
+
+	rtnl_lock();
+	ret = __nss_connmgr_gre_destroy_interface(dev);
+	rtnl_unlock();
+
+	/*
+	 * free_netdev() should be called outside of rtnl lock
+	 */
+	if (!ret) {
+		free_netdev(dev);
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL(nss_connmgr_gre_destroy_interface);
+
+/*
+ * nss_connmgr_gre_create_interface()
+ *	User API to create gre standard interface
+ */
+struct net_device *nss_connmgr_gre_create_interface(struct nss_connmgr_gre_cfg *cfg,
+						    enum nss_connmgr_gre_err_codes *err_code)
+{
+	struct net_device *dev;
+
+	if ((!cfg) || (!err_code)) {
+		nss_connmgr_gre_info("parameter to this function should not be NULL\n");
+		return NULL;
+	}
+
+	if (in_interrupt()) {
+		nss_connmgr_gre_info("nss_connmgr_gre_create_interface() called in interrupt context\n");
+		*err_code = GRE_ERR_IN_INTERRUPT_CTX;
+		return NULL;
+	}
+
+	if (!nss_connmgr_gre_validate_config(cfg)) {
+		*err_code = GRE_ERR_UNSUPPORTED_CFG;
+		return NULL;
+	}
+
+	rtnl_lock();
+	dev = __nss_connmgr_gre_create_interface(cfg, err_code);
+	rtnl_unlock();
+
+	if (*err_code == GRE_SUCCESS) {
+		return dev;
+	}
+
+	if (dev) {
+		free_netdev(dev);
+	}
+
+	return NULL;
+}
+EXPORT_SYMBOL(nss_connmgr_gre_create_interface);
+
+module_init(nss_connmgr_gre_dev_init_module);
+module_exit(nss_connmgr_gre_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS gre offload manager");
diff --git a/qca-nss-clients/gre/nss_connmgr_gre.h b/qca-nss-clients/gre/nss_connmgr_gre.h
new file mode 100644
index 0000000..d426bd0
--- /dev/null
+++ b/qca-nss-clients/gre/nss_connmgr_gre.h
@@ -0,0 +1,103 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_connnmgr_gre.h
+ *
+ * Header file implementaion of nss_connmgr_gre
+ */
+
+#ifndef _NSS_CONNMGR_GRE_H_
+#define _NSS_CONNMGR_GRE_H_
+
+#include "nss_connmgr_gre_public.h"
+
+/*
+ * GRE debug macros
+ */
+#if (NSS_GRE_DEBUG_LEVEL < 1)
+#define nss_connmgr_gre_assert(fmt, args...)
+#else
+#define nss_connmgr_gre_assert(c)  BUG_ON(!(c));
+#endif
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_connmgr_gre_warning(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_connmgr_gre_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_connmgr_gre_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_GRE_DEBUG_LEVEL < 2)
+#define nss_connmgr_gre_warning(s, ...)
+#else
+#define nss_connmgr_gre_warning(s, ...) pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_GRE_DEBUG_LEVEL < 3)
+#define nss_connmgr_gre_info(s, ...)
+#else
+#define nss_connmgr_gre_info(s, ...)   pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_GRE_DEBUG_LEVEL < 4)
+#define nss_connmgr_gre_trace(s, ...)
+#else
+#define nss_connmgr_gre_trace(s, ...)  pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif
+#define nss_connmgr_gre_error(s, ...) pr_err("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+#define GRE_HDR_PAD_LEN 2
+
+enum nss_connmgr_gre_iftype {
+	NSS_CONNMGR_GRE_IFTYPE_NONE,
+	NSS_CONNMGR_GRE_IFTYPE_CUSTOM_GRE,
+	NSS_CONNMGR_GRE_IFTYPE_STD_GRE,
+	NSS_CONNMGR_GRE_IFTYPE_MAX
+};
+
+typedef struct nss_gre_info nss_connmgr_gre_priv_t;
+
+uint32_t nss_connmgr_gre_get_hlen(struct nss_connmgr_gre_cfg *cfg);
+void nss_connmgr_gre_set_gre_flags(struct nss_connmgr_gre_cfg *cfg,
+					   uint16_t *o_flags, uint16_t *i_flags);
+
+uint32_t nss_connmgr_gre_get_nss_config_flags(uint16_t o_flags, uint16_t i_flags,
+						  uint8_t tos, uint8_t ttl,
+						  uint16_t frag_off);
+int nss_connmgr_gre_set_wifi_next_hop(struct net_device *wifi_vdev);
+
+int nss_connmgr_gre_v4_set_config(struct net_device *dev, struct nss_connmgr_gre_cfg *cfg);
+int nss_connmgr_gre_v6_set_config(struct net_device *dev, struct nss_connmgr_gre_cfg *cfg);
+
+int nss_connmgr_gre_v4_get_config(struct net_device *dev, struct nss_gre_msg *req, struct net_device **next_dev, bool hold);
+int nss_connmgr_gre_v6_get_config(struct net_device *dev, struct nss_gre_msg *req, struct net_device **next_dev, bool hold);
+
+void nss_connmgr_gre_tap_v4_outer_exception(struct net_device *dev, struct sk_buff *skb);
+void nss_connmgr_gre_tap_v6_outer_exception(struct net_device *dev, struct sk_buff *skb);
+
+void nss_connmgr_gre_tun_v4_outer_exception(struct net_device *dev, struct sk_buff *skb);
+void nss_connmgr_gre_tun_v6_outer_exception(struct net_device *dev, struct sk_buff *skb);
+
+#endif
diff --git a/qca-nss-clients/gre/nss_connmgr_gre_v4.c b/qca-nss-clients/gre/nss_connmgr_gre_v4.c
new file mode 100644
index 0000000..d6c9927
--- /dev/null
+++ b/qca-nss-clients/gre/nss_connmgr_gre_v4.c
@@ -0,0 +1,367 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_connnmgr_gre_v4.c
+ *
+ *  This file implements client for GRE implementation.
+ */
+
+#include <linux/version.h>
+#include <linux/netdevice.h>
+#include <linux/inetdevice.h>
+#include <linux/etherdevice.h>
+#include <net/ip.h>
+#include <net/route.h>
+#include <net/ip_tunnels.h>
+#include <net/ip6_tunnel.h>
+#include <net/arp.h>
+#include <net/gre.h>
+
+#include <nss_api_if.h>
+#include "nss_connmgr_gre_public.h"
+#include "nss_connmgr_gre.h"
+
+/*
+ * nss_connmgr_gre_v4_get_tx_dev()
+ *	Find tx interface for IP address. Holds ref to next_dev.
+ */
+static struct net_device *nss_connmgr_gre_v4_get_tx_dev(uint32_t dest_ip)
+{
+	struct rtable *rt;
+	struct net_device *dev;
+	uint32_t ip_addr __attribute__ ((unused)) = ntohl(dest_ip);
+
+	rt = ip_route_output(&init_net, htonl(dest_ip), 0, 0, 0);
+	if (IS_ERR(rt)) {
+		nss_connmgr_gre_warning("Unable to lookup route for %pI4\n", &ip_addr);
+		return NULL;
+	}
+
+	dev = rt->dst.dev;
+	if (!dev) {
+		ip_rt_put(rt);
+		nss_connmgr_gre_warning("Unable to find route dev for %pI4\n", &ip_addr);
+		return NULL;
+	}
+
+	dev_hold(dev);
+	ip_rt_put(rt);
+	return dev;
+}
+
+/*
+ * nss_connmgr_gre_v4_get_mac_address()
+ *	Find source and destination MAC for source and destination IP address.
+ */
+static int nss_connmgr_gre_v4_get_mac_address(uint32_t src_ip, uint32_t dest_ip,
+					     uint8_t *src_mac, uint8_t *dest_mac)
+{
+	struct neighbour *neigh;
+	struct rtable *rt;
+	__be32 raddr = htonl(dest_ip);
+	__be32 laddr = htonl(src_ip);
+
+	/*
+	 * find local MAC address
+	 */
+	struct net_device *local_dev = ip_dev_find(&init_net, laddr);
+	if (!local_dev) {
+		nss_connmgr_gre_warning("Unable to find local dev for %pI4", &laddr);
+		return GRE_ERR_NO_LOCAL_NETDEV;
+	}
+	ether_addr_copy(src_mac, local_dev->dev_addr);
+	dev_put(local_dev);
+	nss_connmgr_gre_info("Src MAC address for %pI4 is %pM\n", &laddr, src_mac);
+
+	rt = ip_route_output(&init_net, raddr, 0, 0, 0);
+	if (IS_ERR(rt)) {
+		nss_connmgr_gre_warning("route look up failed for %pI4\n", &raddr);
+		return GRE_ERR_RADDR_ROUTE_LOOKUP;
+	}
+
+	neigh = dst_neigh_lookup(&rt->dst, (const void *)&raddr);
+	if (!neigh) {
+		neigh = neigh_lookup(&arp_tbl, (const void *)&raddr,  rt->dst.dev);
+	}
+
+	if (neigh) {
+		if (!(neigh->nud_state & NUD_VALID) || !is_valid_ether_addr(neigh->ha)) {
+			nss_connmgr_gre_info("neigh lookup failed for %pI4, state=%x, neigh->ha=%pM\n", &raddr, neigh->nud_state, neigh->ha);
+			neigh_release(neigh);
+			neigh = NULL;
+		}
+	}
+
+	/*
+	 * Send arp request
+	 */
+	if (!neigh) {
+		neigh = neigh_create(&arp_tbl, &raddr, rt->dst.dev);
+		if (IS_ERR_OR_NULL(neigh)) {
+			nss_connmgr_gre_warning("Unable to create ARP request neigh for %pI4\n", &raddr);
+			ip_rt_put(rt);
+			return GRE_ERR_NEIGH_CREATE;
+		}
+		nss_connmgr_gre_info("Send ARP request neigh for %pI4\n", &raddr);
+		neigh_event_send(neigh, NULL);
+
+		msleep(2000);
+	}
+
+	if (!(neigh->nud_state & NUD_VALID) || !is_valid_ether_addr(neigh->ha)) {
+		ip_rt_put(rt);
+		nss_connmgr_gre_warning("invalid neigh state (%x) or invalid MAC(%pM) for %pI4\n", neigh->nud_state, neigh->ha,  &raddr);
+		neigh_release(neigh);
+		return GRE_ERR_NEIGH_CREATE;
+	}
+
+	if (neigh->dev->type == ARPHRD_LOOPBACK) {
+		ip_rt_put(rt);
+		neigh_release(neigh);
+		nss_connmgr_gre_warning("Err in destination MAC address, neighbour dev is loop back for %pI4\n", &raddr);
+		return GRE_ERR_NEIGH_DEV_LOOPBACK;
+
+	}
+
+	if (neigh->dev->flags & IFF_NOARP) {
+		ip_rt_put(rt);
+		neigh_release(neigh);
+		nss_connmgr_gre_warning("Err in destination MAC address, neighbour dev is of type NO_ARP for %pI4\n", &raddr);
+		return GRE_ERR_NEIGH_DEV_NOARP;
+	}
+
+	ether_addr_copy(dest_mac, neigh->ha);
+	ip_rt_put(rt);
+	neigh_release(neigh);
+	nss_connmgr_gre_info("Destination MAC address for %pI4 is %pM\n", &raddr, dest_mac);
+	return GRE_SUCCESS;
+}
+
+/*
+ * nss_connmgr_gre_v4_set_config()
+ *	Set User configuration to netdevice
+ */
+int nss_connmgr_gre_v4_set_config(struct net_device *dev, struct nss_connmgr_gre_cfg *cfg)
+{
+	nss_connmgr_gre_priv_t *priv = netdev_priv(dev);
+	struct ip_tunnel *t = (struct ip_tunnel *)priv;
+	struct iphdr *iphdr;
+
+	/*
+	 * MAC address validate
+	 */
+	if (cfg->use_mac_hdr) {
+		if (!is_valid_ether_addr((const u8 *)cfg->src_mac) ||
+		    !is_valid_ether_addr((const u8 *)cfg->dest_mac)) {
+			nss_connmgr_gre_warning("User should provide valid MAC address if flag add_mac hdr is set\n");
+			return GRE_ERR_INVALID_MAC;
+		}
+	}
+
+	/*
+	 * IP address validate
+	 */
+	if ((cfg->src_ip == 0) || (cfg->dest_ip == 0)) {
+		nss_connmgr_gre_warning("Source ip/Destination IP is invalid");
+		return GRE_ERR_INVALID_IP;
+	}
+
+	memset(t, 0, sizeof(struct ip_tunnel));
+
+	priv->pad_len =  (cfg->add_padding) ? GRE_HDR_PAD_LEN : 0;
+	priv->gre_hlen = nss_connmgr_gre_get_hlen(cfg);
+
+	iphdr = (struct iphdr *)&(t->parms.iph);
+	iphdr->protocol = IPPROTO_GRE;
+
+	memcpy(&iphdr->saddr, (uint8_t *)cfg->src_ip, 4);
+	memcpy(&iphdr->daddr, (uint8_t *)cfg->dest_ip, 4);
+
+	iphdr->saddr = htonl(iphdr->saddr);
+	iphdr->daddr = htonl(iphdr->daddr);
+
+	iphdr->tos = cfg->tos << 2;
+	if (cfg->tos_inherit) {
+		iphdr->tos |= 0x1;
+	}
+
+	iphdr->ttl = cfg->ttl;
+	if (cfg->ttl_inherit) {
+		iphdr->ttl = 0;
+	}
+
+	if (cfg->set_df) {
+		iphdr->frag_off = htons(IP_DF);
+	}
+
+	if (cfg->ikey_valid) {
+		t->parms.i_key = cfg->ikey;
+	}
+
+	if (cfg->okey_valid) {
+		t->parms.o_key = cfg->okey;
+	}
+
+	nss_connmgr_gre_set_gre_flags(cfg, &t->parms.o_flags, &t->parms.i_flags);
+
+	strlcpy(t->parms.name, dev->name, IFNAMSIZ);
+	t->dev = dev;
+	return GRE_SUCCESS;
+}
+
+/*
+ * nss_connmgr_gre_tap_v4_outer_exception()
+ * 	Handle IPv4 exception for GRETAP outer device
+ */
+void nss_connmgr_gre_tap_v4_outer_exception(struct net_device *dev, struct sk_buff *skb)
+{
+	struct ethhdr *eth_hdr = (struct ethhdr *)skb->data;
+
+	/*
+	 * GRE encapsulated packet exceptioned, remove the encapsulation
+	 * and transmit on GRE interface.
+	 */
+	if (unlikely(!pskb_may_pull(skb, (sizeof(struct ethhdr) + sizeof(struct iphdr)
+				+ sizeof(struct gre_base_hdr))))) {
+		nss_connmgr_gre_warning("%px: pskb_may_pull failed for skb:%px\n", dev, skb);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	/*
+	 * TODO: Support parsing GRE options
+	 */
+	skb_pull(skb, (sizeof(struct ethhdr) + sizeof(struct iphdr)
+				+ sizeof(struct gre_base_hdr)));
+
+	if (unlikely(!pskb_may_pull(skb, sizeof(struct ethhdr)))) {
+		nss_connmgr_gre_warning("%px: pskb_may_pull failed for skb:%px\n", dev, skb);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+	skb->dev = dev;
+	if (likely(ntohs(eth_hdr->h_proto) >= ETH_P_802_3_MIN)) {
+		skb->protocol = eth_hdr->h_proto;
+	} else {
+		skb->protocol = htons(ETH_P_802_2);
+	}
+	skb_reset_mac_header(skb);
+	skb_reset_network_header(skb);
+	skb_reset_transport_header(skb);
+	skb_reset_mac_len(skb);
+	dev_queue_xmit(skb);
+}
+
+/*
+ * nss_connmgr_gre_tun_v4_outer_exception()
+ * 	Handle IPv4 exception for GRETUN outer device
+ */
+void nss_connmgr_gre_tun_v4_outer_exception(struct net_device *dev, struct sk_buff *skb)
+{
+	struct iphdr *iph;
+
+	/*
+	 * GRE encapsulated packet exceptioned, remove the encapsulation
+	 * and transmit on GRE interface.
+	 */
+	if (unlikely(!pskb_may_pull(skb, sizeof(struct iphdr) + sizeof(struct gre_base_hdr)))) {
+		nss_connmgr_gre_warning("%px: pskb_may_pull failed for skb:%px\n", dev, skb);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	/*
+	 * TODO: Support parsing GRE options
+	 */
+	skb_pull(skb, sizeof(struct iphdr) + sizeof(struct gre_base_hdr));
+	iph = (struct iphdr *)skb->data;
+	skb->dev = dev;
+
+	switch (iph->version) {
+	case 4:
+		skb->protocol = htons(ETH_P_IP);
+		break;
+	case 6:
+		skb->protocol = htons(ETH_P_IPV6);
+		break;
+	default:
+		nss_connmgr_gre_info("%px: wrong IP version in GRE encapped packet. skb: %px\n", dev, skb);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	skb_reset_mac_header(skb);
+	skb_reset_network_header(skb);
+	skb_reset_transport_header(skb);
+	skb_reset_mac_len(skb);
+	dev_queue_xmit(skb);
+}
+
+/*
+ * nss_connmgr_gre_v4_get_config()
+ *	Fill in config message to send to NSS.
+ */
+int nss_connmgr_gre_v4_get_config(struct net_device *dev, struct nss_gre_msg *req,
+				  struct net_device **next_dev, bool hold)
+{
+	uint32_t src_ip, dest_ip;
+	struct ip_tunnel *t = netdev_priv(dev);
+	struct iphdr *iphdr = (struct iphdr *)&(t->parms.iph);
+	struct net_device *out_dev;
+	struct nss_gre_config_msg *cmsg = &req->msg.cmsg;
+	int ret;
+
+	src_ip = ntohl(iphdr->saddr);
+	dest_ip = ntohl(iphdr->daddr);
+	memcpy(cmsg->src_ip, &src_ip, 4);
+	memcpy(cmsg->dest_ip, &dest_ip, 4);
+
+	cmsg->flags |= nss_connmgr_gre_get_nss_config_flags(t->parms.o_flags,
+								     t->parms.i_flags,
+								     iphdr->tos, iphdr->ttl,
+								     iphdr->frag_off);
+
+	cmsg->ikey = t->parms.i_key;
+	cmsg->okey = t->parms.o_key;
+	cmsg->ttl = iphdr->ttl;
+	cmsg->tos = iphdr->tos >> 2;
+
+	/*
+	 * fill in MAC addresses
+	 */
+	ret = nss_connmgr_gre_v4_get_mac_address(src_ip, dest_ip,
+						 (uint8_t *)cmsg->src_mac,
+						 (uint8_t *)cmsg->dest_mac);
+	if (!ret) {
+		cmsg->flags |= NSS_GRE_CONFIG_SET_MAC;
+	}
+
+	/*
+	 * fill in NSS interface number
+	 */
+	out_dev = nss_connmgr_gre_v4_get_tx_dev(dest_ip);
+	if (out_dev) {
+		cmsg->next_node_if_num = nss_cmn_get_interface_number_by_dev(out_dev);
+		cmsg->flags |= NSS_GRE_CONFIG_NEXT_NODE_AVAILABLE;
+		*next_dev = out_dev;
+		if (!hold) {
+			dev_put(out_dev);
+		}
+	}
+
+	return GRE_SUCCESS;
+}
diff --git a/qca-nss-clients/gre/nss_connmgr_gre_v6.c b/qca-nss-clients/gre/nss_connmgr_gre_v6.c
new file mode 100644
index 0000000..eb82663
--- /dev/null
+++ b/qca-nss-clients/gre/nss_connmgr_gre_v6.c
@@ -0,0 +1,395 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_connnmgr_gre_v6.c
+ *
+ *  This file implements client for GRE implementation.
+ */
+
+#include <linux/version.h>
+#include <linux/netdevice.h>
+#include <linux/inetdevice.h>
+#include <linux/etherdevice.h>
+#include <net/route.h>
+#include <net/ip6_route.h>
+#include <net/ip6_tunnel.h>
+#include <net/ip_tunnels.h>
+#include <net/addrconf.h>
+#include <net/gre.h>
+
+#include <nss_api_if.h>
+#include "nss_connmgr_gre_public.h"
+#include "nss_connmgr_gre.h"
+
+/*
+ * nss_connmgr_gre_v6_route_lookup()
+ *	Find IPv6 route for the IP address
+ */
+static inline struct rt6_info *nss_connmgr_gre_v6_route_lookup(struct net *net, struct in6_addr *addr)
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0))
+        return rt6_lookup(net, addr, NULL, 0, 0);
+#else
+	return rt6_lookup(net, addr, NULL, 0, 0, 0);
+#endif
+}
+
+/*
+ * nss_connmgr_gre_v6_get_tx_dev()
+ *	Find tx interface for the IP address.
+ */
+static struct net_device *nss_connmgr_gre_v6_get_tx_dev(uint8_t *dest_ip)
+{
+	struct rt6_info *rt;
+	struct in6_addr ipv6_addr;
+	struct net_device *dev;
+
+	memcpy(ipv6_addr.s6_addr, dest_ip, 16);
+
+	rt = nss_connmgr_gre_v6_route_lookup(&init_net, &ipv6_addr);
+	if (!rt) {
+		return NULL;
+	}
+
+	dev = rt->dst.dev;
+	if (!dev) {
+		ip6_rt_put(rt);
+		return NULL;
+	}
+
+	dev_hold(dev);
+	ip6_rt_put(rt);
+	return dev;
+}
+
+/*
+ * nss_connmgr_gre_v6_get_mac_address()
+ *	Find source and destination MAC address for source and destination IP
+ *	address.
+ */
+static int nss_connmgr_gre_v6_get_mac_address(uint8_t *src_ip, uint8_t *dest_ip,
+					     uint8_t *src_mac, uint8_t *dest_mac)
+{
+	struct neighbour *neigh;
+	struct rt6_info *rt;
+	struct in6_addr src_addr, dst_addr, mc_dst_addr;
+	struct net_device *local_dev;
+
+	memcpy(src_addr.s6_addr, src_ip, 16);
+	memcpy(dst_addr.s6_addr, dest_ip, 16);
+
+	/*
+	 * Find src MAC address
+	 */
+	local_dev = (struct net_device *)ipv6_dev_find(&init_net, &src_addr, 1);
+	if (!local_dev) {
+		nss_connmgr_gre_warning("Unable to find local dev for %pI6", src_ip);
+		return GRE_ERR_NO_LOCAL_NETDEV;
+	}
+	ether_addr_copy(src_mac, local_dev->dev_addr);
+	dev_put(local_dev);
+
+	/*
+	 * Find dest MAC address
+	 */
+
+	rt = nss_connmgr_gre_v6_route_lookup(&init_net, &dst_addr);
+	if (!rt) {
+		nss_connmgr_gre_warning("Unable to find route lookup for %pI6", dest_ip);
+		return GRE_ERR_NEIGH_LOOKUP;
+	}
+
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3,6,0))
+	neigh = rt->dst.ops->neigh_lookup(&rt->dst, &dst_addr);
+#else
+	neigh = rt->dst.ops->neigh_lookup(&rt->dst, NULL, &dst_addr);
+#endif
+	if (neigh) {
+		if (!(neigh->nud_state & NUD_VALID) || !is_valid_ether_addr(neigh->ha)) {
+			nss_connmgr_gre_warning("neigh state is either invalid (%x) or mac address is null (%pM) for %pI6", neigh->nud_state, neigh->ha, dest_ip);
+			neigh_release(neigh);
+			neigh = NULL;
+		}
+	}
+
+	if (!neigh) {
+
+		/*
+		 * Issue a Neighbour soliciation request
+	 	*/
+		nss_connmgr_gre_info("Issue Neighbour solicitation request\n");
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0))
+		ndisc_send_ns(local_dev, &dst_addr, &mc_dst_addr, &src_addr);
+#else
+		ndisc_send_ns(local_dev, &dst_addr, &mc_dst_addr, &src_addr, 0);
+#endif
+		msleep(2000);
+
+		/*
+		 * Release hold on existing route entry, and find the route entry again
+		 */
+		ip6_rt_put(rt);
+
+		rt = nss_connmgr_gre_v6_route_lookup(&init_net, &dst_addr);
+		if (!rt) {
+			nss_connmgr_gre_warning("Unable to find route lookup for %pI6\n", dest_ip);
+			return GRE_ERR_NEIGH_LOOKUP;
+		}
+
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3,6,0))
+		neigh = rt->dst.ops->neigh_lookup(&rt->dst, &dst_addr);
+#else
+		neigh = rt->dst.ops->neigh_lookup(&rt->dst, NULL, &dst_addr);
+#endif
+
+		if (!neigh) {
+			ip6_rt_put(rt);
+			nss_connmgr_gre_warning("Err in MAC address, neighbour look up failed\n");
+			return GRE_ERR_NEIGH_LOOKUP;
+		}
+
+		if (!(neigh->nud_state & NUD_VALID) || !is_valid_ether_addr(neigh->ha)) {
+			ip6_rt_put(rt);
+			nss_connmgr_gre_warning("Err in MAC address, invalid neigh state (%x) or invalid mac(%pM)\n", neigh->nud_state, neigh->ha);
+			neigh_release(neigh);
+			return GRE_ERR_NEIGH_LOOKUP;
+		}
+	}
+
+	ether_addr_copy(dest_mac, neigh->ha);
+
+	ip6_rt_put(rt);
+	neigh_release(neigh);
+	return GRE_SUCCESS;
+}
+
+/*
+ * nss_connmgr_gre_tap_v6_outer_exception()
+ * 	Handle IPv6 exception for GRETAP outer device
+ */
+void nss_connmgr_gre_tap_v6_outer_exception(struct net_device *dev, struct sk_buff *skb)
+{
+	struct ethhdr *eth = (struct ethhdr *)skb->data;
+
+	/*
+	 * GRE encapsulated packet exceptioned, remove the encapsulation
+	 * and transmit on GRE interface.
+	 */
+	if (unlikely(!pskb_may_pull(skb, (sizeof(struct ethhdr) + sizeof(struct ipv6hdr)
+				+ sizeof(struct gre_base_hdr))))) {
+		nss_connmgr_gre_warning("%px: pskb_may_pull failed for skb:%px\n", dev, skb);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	/*
+	 * TODO: Support parsing GRE options
+	 */
+	skb_pull(skb, (sizeof(struct ethhdr) + sizeof(struct ipv6hdr)
+				+ sizeof(struct gre_base_hdr)));
+
+	if (unlikely(!pskb_may_pull(skb, sizeof(struct ethhdr)))) {
+		nss_connmgr_gre_warning("%px: pskb_may_pull failed for skb:%px\n", dev, skb);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+	skb->dev = dev;
+	if (likely(ntohs(eth->h_proto) >= ETH_P_802_3_MIN)) {
+		skb->protocol = eth->h_proto;
+	} else {
+		skb->protocol = htons(ETH_P_802_2);
+	}
+	skb_reset_mac_header(skb);
+	skb_reset_network_header(skb);
+	skb_reset_transport_header(skb);
+	skb_reset_mac_len(skb);
+	dev_queue_xmit(skb);
+}
+
+/*
+ * nss_connmgr_gre_tun_v6_outer_exception()
+ * 	Handle IPv6 exception for GRETUN outer device
+ */
+void nss_connmgr_gre_tun_v6_outer_exception(struct net_device *dev, struct sk_buff *skb)
+{
+	struct ipv6hdr *ip6h;
+
+	/*
+	 * GRE encapsulated packet exceptioned, remove the encapsulation
+	 * and transmit on GRE interface.
+	 */
+	if (unlikely(!pskb_may_pull(skb, sizeof(struct ipv6hdr) + sizeof(struct gre_base_hdr)))) {
+		nss_connmgr_gre_warning("%px: pskb_may_pull failed for skb:%px\n", dev, skb);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	/*
+	 * TODO: Support parsing GRE options
+	 */
+	skb_pull(skb, sizeof(struct ipv6hdr) + sizeof(struct gre_base_hdr));
+
+	ip6h = (struct ipv6hdr *)skb->data;
+	skb->dev = dev;
+
+	switch (ip6h->version) {
+	case 4:
+		skb->protocol = htons(ETH_P_IP);
+		break;
+	case 6:
+		skb->protocol = htons(ETH_P_IPV6);
+		break;
+	default:
+		nss_connmgr_gre_info("%px: wrong IP version in GRE encapped packet. skb: %px\n", dev, skb);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	skb_reset_mac_header(skb);
+	skb_reset_network_header(skb);
+	skb_reset_transport_header(skb);
+	skb_reset_mac_len(skb);
+	dev_queue_xmit(skb);
+}
+
+/*
+ * nss_connmgr_gre_v6_set_config()
+ *	Set user config to dev inerface.
+ */
+int nss_connmgr_gre_v6_set_config(struct net_device *dev, struct nss_connmgr_gre_cfg *cfg)
+{
+	nss_connmgr_gre_priv_t *priv = netdev_priv(dev);
+	struct ip6_tnl *t = (struct ip6_tnl *)priv;
+
+	/*
+	 * IP address validate
+	 */
+	if (ipv6_addr_any(((const struct in6_addr *)&cfg->src_ip)) ||
+	    ipv6_addr_any(((const struct in6_addr *)&cfg->dest_ip))) {
+		nss_connmgr_gre_warning("Source ip/Destination IP is invalid");
+		return  GRE_ERR_INVALID_IP;
+	}
+
+	/*
+	 * MAC address validate
+	 */
+	if (cfg->use_mac_hdr) {
+		if (!is_valid_ether_addr((const u8 *)cfg->src_mac) ||
+		    !is_valid_ether_addr((const u8 *)cfg->dest_mac)) {
+			nss_connmgr_gre_warning("User should provide valid MAC address if flag add_mac hdr is set\n");
+			return GRE_ERR_INVALID_MAC;
+		}
+	}
+
+	memset(t, 0, sizeof(struct ip6_tnl));
+
+	priv->pad_len = (cfg->add_padding) ? GRE_HDR_PAD_LEN : 0;
+	priv->gre_hlen = nss_connmgr_gre_get_hlen(cfg);
+
+	memcpy(t->parms.laddr.s6_addr, &cfg->src_ip, 16);
+	memcpy(t->parms.raddr.s6_addr, &cfg->dest_ip, 16);
+
+	t->parms.flowinfo = cfg->tos << 2;
+	if (cfg->tos_inherit) {
+		t->parms.flowinfo |= 0x1;
+	}
+
+	t->parms.hop_limit = cfg->ttl;
+	if (cfg->ttl_inherit) {
+		t->parms.hop_limit = 0;
+	}
+
+	if (cfg->ikey_valid) {
+		t->parms.i_key = cfg->ikey;
+	}
+
+	if (cfg->okey_valid) {
+		t->parms.o_key = cfg->okey;
+	}
+
+	nss_connmgr_gre_set_gre_flags(cfg, &t->parms.o_flags, &t->parms.i_flags);
+
+	strlcpy(t->parms.name, dev->name, IFNAMSIZ);
+	t->dev = dev;
+	return GRE_SUCCESS;
+}
+
+/*
+ * nss_connmgr_gre_v6_get_config()
+ *	Fill info in config message to send to NSS.
+ */
+int nss_connmgr_gre_v6_get_config(struct net_device *dev, struct nss_gre_msg *req,
+				  struct net_device **next_dev, bool hold)
+{
+	struct ip6_tnl *t = netdev_priv(dev);
+	struct net_device *out_dev;
+	struct nss_gre_config_msg *cmsg = &req->msg.cmsg;
+	int ret;
+	struct in6_addr *src_ip = &t->parms.laddr;
+	struct in6_addr *dest_ip = &t->parms.raddr;
+
+	/*
+	 * Store IPv6 addresses in host endian in the message.
+	 */
+	cmsg->src_ip[0] = ntohl(src_ip->in6_u.u6_addr32[0]);
+	cmsg->src_ip[1] = ntohl(src_ip->in6_u.u6_addr32[1]);
+	cmsg->src_ip[2] = ntohl(src_ip->in6_u.u6_addr32[2]);
+	cmsg->src_ip[3] = ntohl(src_ip->in6_u.u6_addr32[3]);
+
+	cmsg->dest_ip[0] = ntohl(dest_ip->in6_u.u6_addr32[0]);
+	cmsg->dest_ip[1] = ntohl(dest_ip->in6_u.u6_addr32[1]);
+	cmsg->dest_ip[2] = ntohl(dest_ip->in6_u.u6_addr32[2]);
+	cmsg->dest_ip[3] = ntohl(dest_ip->in6_u.u6_addr32[3]);
+
+	/*
+	 * IPv6 outer tos field is always inherited from inner IP header.
+	 */
+	cmsg->flags |= nss_connmgr_gre_get_nss_config_flags(t->parms.o_flags,
+								     t->parms.i_flags,
+								     t->parms.flowinfo,
+								     t->parms.hop_limit, 0);
+
+	cmsg->ikey = t->parms.i_key;
+	cmsg->okey = t->parms.o_key;
+	cmsg->ttl = t->parms.hop_limit;
+	cmsg->tos = t->parms.flowinfo >> 2;
+
+	/*
+	 * fill in MAC addresses
+	 */
+	ret = nss_connmgr_gre_v6_get_mac_address(t->parms.laddr.s6_addr, t->parms.raddr.s6_addr,
+						 (uint8_t *)cmsg->src_mac,
+						 (uint8_t *)cmsg->dest_mac);
+	if (!ret) {
+		cmsg->flags |= NSS_GRE_CONFIG_SET_MAC;
+	}
+
+	/*
+	 * fill in NSS interface number
+	 */
+	out_dev = nss_connmgr_gre_v6_get_tx_dev(t->parms.raddr.s6_addr);
+	if (out_dev) {
+		cmsg->next_node_if_num = nss_cmn_get_interface_number_by_dev(out_dev);
+		cmsg->flags |= NSS_GRE_CONFIG_NEXT_NODE_AVAILABLE;
+		*next_dev = out_dev;
+		if (!hold) {
+			dev_put(out_dev);
+		}
+	}
+
+	return GRE_SUCCESS;
+}
diff --git a/qca-nss-clients/gre/test/Makefile b/qca-nss-clients/gre/test/Makefile
new file mode 100644
index 0000000..0cc6e5f
--- /dev/null
+++ b/qca-nss-clients/gre/test/Makefile
@@ -0,0 +1,6 @@
+# Makefile for custom gre test module
+ccflags-y += -I$(obj)/../../../exports -I$(obj)/../../.. -I$(obj)/../
+ccflags-y += -DNSS_GRE_DEBUG_LEVEL=0
+ccflags-y += -Wall -Werror
+obj-m +=  qca-nss-gre-test.o
+qca-nss-gre-test-objs := nss_connmgr_gre_test.o
diff --git a/qca-nss-clients/gre/test/nss_connmgr_gre_test.c b/qca-nss-clients/gre/test/nss_connmgr_gre_test.c
new file mode 100644
index 0000000..8e3974d
--- /dev/null
+++ b/qca-nss-clients/gre/test/nss_connmgr_gre_test.c
@@ -0,0 +1,270 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_connnmgr_gre_test.c
+ *	test module implementation
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/inet.h>
+#include <net/ipv6.h>
+#include <net/ip6_tunnel.h>
+#include <net/ip_tunnels.h>
+#include <linux/proc_fs.h>
+#include <linux/slab.h>
+
+#include <nss_api_if.h>
+
+#include "nss_connmgr_gre_public.h"
+#include "nss_connmgr_gre.h"
+
+#define MAX_PROC_SIZE 1024
+static struct proc_dir_entry *proc_entry;
+
+/*
+ * nss_connmgr_gre_test()
+ *	Function calls API (exported by client code) to create GRE tap interface
+ *	and destroy interface based on command writter to /proc/gre entry.
+ */
+static int nss_connmgr_gre_test(char *src_ip, char *dest_ip, char *next_dev_name)
+{
+	int ret = -1;
+	uint32_t sip, dip;
+	struct nss_connmgr_gre_cfg cfg;
+	struct net_device *dev, *next_dev;
+	enum nss_connmgr_gre_err_codes err_code;
+
+	ret = in4_pton(src_ip, -1, (uint8_t *)&sip, -1, NULL);
+	if (ret != 1) {
+		pr_err("Not a valid src ip\n");
+		return -1;
+	}
+
+	ret = in4_pton(dest_ip, -1, (uint8_t *)&dip, -1, NULL);
+	if (ret != 1) {
+		pr_err("Not a valid dest ip\n");
+		return -1;
+	}
+
+	sip = ntohl(sip);
+	dip = ntohl(dip);
+
+	if (!next_dev_name) {
+		pr_err("next_dev=%s is not a valid param", next_dev_name);
+		return -1;
+	}
+
+	next_dev = dev_get_by_name(&init_net, next_dev_name);
+	if (!next_dev) {
+		pr_err("next_dev=%s is not a valid param", next_dev_name);
+		return -1;
+	}
+
+	memset(&cfg, 0, sizeof(struct nss_connmgr_gre_cfg));
+
+	cfg.mode = GRE_MODE_TAP;
+	cfg.ip_type = GRE_OVER_IPV4;
+	cfg.ttl_inherit = true;
+	cfg.tos_inherit = true;
+	cfg.add_padding = false;
+	cfg.copy_metadata = true;
+	cfg.next_dev = next_dev;
+
+	cfg.src_ip[0] = sip;
+	cfg.dest_ip[0] = dip;
+
+	dev = nss_connmgr_gre_create_interface(&cfg, &err_code);
+	dev_put(next_dev);
+	if (!dev) {
+		pr_err("Could not create gre interface, err=%d\n", err_code);
+		return -1;
+	}
+
+	pr_info("Gre interface %s created\n", dev->name);
+	return 0;
+}
+
+/*
+ * nss_connmgr_gre_test_write_proc()
+ *	Write call back for proc entry.
+ */
+static ssize_t nss_connmgr_gre_test_write_proc(struct file *file, const char __user *buf, size_t count, loff_t *offset)
+{
+	char *token;
+	struct net_device *dev;
+	char saddr[20] = {0}, daddr[20] = {0}, dev_name[IFNAMSIZ] = {0};
+	bool saddr_valid = false, daddr_valid = false, dev_name_valid = false;
+	char *buffer = kzalloc(MAX_PROC_SIZE, GFP_KERNEL);
+	char *pfree;
+	int ret;
+
+	if (!buffer) {
+		return -ENOMEM;
+	}
+	pfree = buffer;
+
+	if (count > MAX_PROC_SIZE) {
+		count = MAX_PROC_SIZE;
+	}
+
+	if (copy_from_user(buffer, buf, count)) {
+		kfree(pfree);
+		return -EFAULT;
+	}
+
+	while (buffer) {
+		char *param, *value;
+		token = strsep(&buffer, " \n");
+		if (token[0] == 0) {
+			continue;
+		}
+
+		param = strsep(&token, "=");
+		value = token;
+
+		/*
+		 * parameter parsing for delete command
+		 */
+		if (!strcmp(param, "dev")) {
+			strlcpy(dev_name, value, IFNAMSIZ);
+			dev_name_valid = true;
+			break;
+		}
+
+		/*
+		 * Parse next_dev, src ip and dest ip for GRE
+		 * tap create command
+		 */
+		if (!strcmp(param, "next_dev")) {
+			strlcpy(dev_name, value, IFNAMSIZ);
+			dev_name_valid = true;
+			continue;
+		}
+
+		if (!strcmp(param, "saddr")) {
+			strlcpy(saddr, value, 20);
+			saddr_valid = true;
+			continue;
+		}
+
+		if (!strcmp(param, "daddr")) {
+			strlcpy(daddr, value, 20);
+			daddr_valid = true;
+			continue;
+		}
+
+	}
+
+	kfree(pfree);
+
+	if (dev_name_valid && !saddr_valid && !daddr_valid) {
+		dev = dev_get_by_name(&init_net, dev_name);
+		if (!dev) {
+			pr_err("Invalid arguments\n");
+			return -EINVAL;
+		}
+		dev_put(dev);
+
+		ret = nss_connmgr_gre_destroy_interface(dev);
+		if (ret) {
+			pr_err("Could not delete interface, failed with errcode=%d\n", ret);
+			return -EINVAL;
+		}
+
+		pr_info("Sucessfully deleted %s interface\n", dev_name);
+		return count;
+	}
+
+	if (!(dev_name_valid && saddr_valid && daddr_valid)) {
+		pr_err("Invalid arguments\n");
+		return -EINVAL;
+	}
+
+	if (nss_connmgr_gre_test(saddr, daddr, dev_name)) {
+		return -EFAULT;
+	}
+
+	return count;
+}
+
+/*
+ * nss_connmgr_gre_test_show_proc()
+ *	Displays help text on how to use this module.
+ */
+static int nss_connmgr_gre_test_show_proc(struct seq_file *filp, void *data)
+{
+	seq_printf(filp, "Help:\n** Create interface **\n");
+	seq_printf(filp, "echo \"saddr=192.168.10.1 daddr=192.168.10.100 next_dev=ath0\" > /proc/gre\n\n");
+	seq_printf(filp, "\n** Delete interface **\n");
+	seq_printf(filp, "echo \"dev=tap-0\" > /proc/gre\n\n");
+	return 0;
+}
+
+/*
+ * nss_connmgr_gre_test_open_proc()
+ *	Open call back for proc entry.
+ */
+static int nss_connmgr_gre_test_open_proc(struct inode *inode, struct file *filp)
+{
+	return single_open(filp, nss_connmgr_gre_test_show_proc, PDE_DATA(inode));
+}
+
+/*
+ * Proc ops
+ */
+static const struct file_operations nss_connmgr_gre_test_proc_ops =  {
+	.open =  nss_connmgr_gre_test_open_proc,
+	.write = nss_connmgr_gre_test_write_proc,
+	.read = seq_read,
+};
+
+/*
+ * nss_connmgr_gre_test_init_module()
+ *	Test module init function.
+ */
+static int __init nss_connmgr_gre_test_init_module(void)
+{
+	proc_entry = proc_create_data("gre", S_IWUGO, NULL,
+					    &nss_connmgr_gre_test_proc_ops,
+					    NULL);
+
+	if (!proc_entry) {
+		pr_err("Creation of proc entry faild\n");
+		return -1;
+	}
+
+	pr_info("Read Help: cat /proc/gre\n");
+	return 0;
+}
+
+/*
+ * nss_connmgr_gre_test_exit_module
+ *	Test module exit function
+ */
+static void __exit nss_connmgr_gre_test_exit_module(void)
+{
+	proc_remove(proc_entry);
+}
+
+module_init(nss_connmgr_gre_test_init_module);
+module_exit(nss_connmgr_gre_test_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS gre test module");
diff --git a/qca-nss-clients/ipsecmgr/v1.0/Makefile b/qca-nss-clients/ipsecmgr/v1.0/Makefile
new file mode 100644
index 0000000..5676f69
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v1.0/Makefile
@@ -0,0 +1,17 @@
+# Makefile for the ipsecmgr v1.0 client
+
+ccflags-y := -I$(obj) -I$(obj)/../..
+ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)"
+ccflags-y += -Wall -Werror
+ifeq ($(SoC), fsm9010)
+	ccflags-y += -DNSS_IPSECMGR_PMTU_SUPPORT
+endif
+
+obj-m += qca-nss-ipsecmgr.o
+qca-nss-ipsecmgr-objs := nss_ipsecmgr.o
+qca-nss-ipsecmgr-objs += nss_ipsecmgr_flow.o
+qca-nss-ipsecmgr-objs += nss_ipsecmgr_sa.o
+qca-nss-ipsecmgr-objs += nss_ipsecmgr_subnet.o
+ccflags-y += -DNSS_IPSECMGR_DEBUG_LEVEL=3
+
+obj ?= .
diff --git a/qca-nss-clients/ipsecmgr/v1.0/nss_ipsecmgr.c b/qca-nss-clients/ipsecmgr/v1.0/nss_ipsecmgr.c
new file mode 100644
index 0000000..2e2eaae
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v1.0/nss_ipsecmgr.c
@@ -0,0 +1,1425 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2017, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/* nss_ipsecmgr.c
+ *	NSS to HLOS IPSec Manager
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/of.h>
+#include <linux/ipv6.h>
+#include <linux/skbuff.h>
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/netdevice.h>
+#include <linux/rtnetlink.h>
+#include <linux/etherdevice.h>
+#include <linux/vmalloc.h>
+#include <linux/debugfs.h>
+#include <linux/atomic.h>
+#include <net/protocol.h>
+#include <net/route.h>
+#include <net/ip6_route.h>
+#include <net/esp.h>
+#include <net/xfrm.h>
+#include <net/icmp.h>
+
+#include <nss_api_if.h>
+#include <nss_ipsec.h>
+#include <nss_ipsecmgr.h>
+
+#include "nss_ipsecmgr_priv.h"
+#include <nss_tstamp.h>
+
+extern bool nss_cmn_get_nss_enabled(void);
+
+struct nss_ipsecmgr_drv *ipsecmgr_ctx;
+
+static bool gen_pmtu_error = true;
+module_param(gen_pmtu_error, bool, 0644);
+MODULE_PARM_DESC(gen_pmtu_error, "Support generation of PMTU error packet");
+
+/*
+ **********************
+ * Helper Functions
+ **********************
+ */
+
+/*
+ * nss_ipsecmgr_ref_no_update()
+ *     dummy functions for object owner when there is no update
+ */
+static void nss_ipsecmgr_ref_no_update(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_ref *child, struct nss_ipsec_msg *nim)
+{
+	nss_ipsecmgr_trace("ref_no_update triggered for child (%px)\n", child);
+	return;
+}
+
+/*
+ * nss_ipsecmgr_ref_no_free()
+ * 	dummy functions for object owner when there is no free
+ */
+static void nss_ipsecmgr_ref_no_free(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_ref *ref)
+{
+	nss_ipsecmgr_trace("%px:ref_no_free triggered\n", ref);
+	return;
+}
+
+/*
+ * nss_ipsecmgr_ref_no_overhead()
+ *	dummy functions for object owner when there is no overhead
+ */
+static uint32_t nss_ipsecmgr_ref_no_overhead(struct nss_ipsecmgr_ref *ref)
+{
+	nss_ipsecmgr_trace("%px:ref_get_no_overhead triggered\n", ref);
+	return 0;
+}
+
+/*
+ * nss_ipsecmgr_ref_set_overhead()
+ *	set the overhead function for reference object
+ */
+void nss_ipsecmgr_ref_set_overhead(struct nss_ipsecmgr_ref *ref, nss_ipsecmgr_ref_overhead_t overhead)
+{
+	ref->overhead = overhead;
+}
+
+/*
+ * nss_ipsecmgr_ref_init()
+ * 	initiaize the reference object
+ */
+void nss_ipsecmgr_ref_init(struct nss_ipsecmgr_ref *ref, nss_ipsecmgr_ref_update_t update, nss_ipsecmgr_ref_free_t free)
+{
+	INIT_LIST_HEAD(&ref->head);
+	INIT_LIST_HEAD(&ref->node);
+
+	ref->id = 0;
+	ref->parent = NULL;
+	ref->update = update ? update : nss_ipsecmgr_ref_no_update;
+	ref->free = free ? free : nss_ipsecmgr_ref_no_free;
+	ref->overhead = nss_ipsecmgr_ref_no_overhead;
+}
+
+/*
+ * nss_ipsecmgr_ref_add()
+ * 	add child reference to parent chain
+ */
+void nss_ipsecmgr_ref_add(struct nss_ipsecmgr_ref *child, struct nss_ipsecmgr_ref *parent)
+{
+	/*
+	 * if child is already part of an existing chain then remove it before
+	 * adding it to the new one. In case this is a new entry then the list
+	 * init during alloc would ensure that the "del_init" operation results
+	 * in a no-op
+	 */
+	list_del_init(&child->node);
+	list_add(&child->node, &parent->head);
+
+	child->parent = parent;
+}
+
+/*
+ * nss_ipsecmgr_ref_update()
+ * 	update the "ref" object and link it to the parent
+ */
+void nss_ipsecmgr_ref_update(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_ref *child, struct nss_ipsec_msg *nim)
+{
+	struct nss_ipsecmgr_ref *entry;
+
+	child->id++;
+	child->update(priv, child, nim);
+
+	/*
+	 * If, there are references to associated with this
+	 * object then notify them about the change. This allows
+	 * the "ref" objects to trigger notifications to NSS for
+	 * updates to SA
+	 */
+	list_for_each_entry(entry, &child->head, node) {
+		nss_ipsecmgr_ref_update(priv, entry, nim);
+	}
+}
+
+/*
+ * nss_ipsecmgr_ref_overhead()
+ *	Get the SA overhead of the reference passed
+ *
+ * note: ideally this will trigger a chain of callbacks till
+ * the SA
+ */
+uint32_t nss_ipsecmgr_ref_overhead(struct nss_ipsecmgr_ref *ref)
+{
+	if (!ref->parent)
+		return ref->overhead(ref);
+
+	return nss_ipsecmgr_ref_overhead(ref->parent);
+}
+
+/*
+ * nss_ipsecmgr_ref_free()
+ * 	Free all references from the "ref" object
+ *
+ * Note: If, the "ref" has child references then it
+ * will walk the child reference chain first and issue
+ * free for each of the associated "child ref" objects.
+ * At the end it will invoke free for the "parent" ref
+ * object.
+ *
+ * +-------+   +-------+   +-------+
+ * |  SA1  +--->   SA2 +--->  SA3  |
+ * +---+---+   +---+---+   +-------+
+ *     |
+ * +---V---+   +-------+   +-------+
+ * | Flow1 +---> Sub1  +---> Flow4 |
+ * +-------+   +---+---+   +-------+
+ *                 |
+ *             +---v---+
+ *             | Flow2 |
+ *             +---+---+
+ *                 |
+ *             +---v---+
+ *             | Flow3 |
+ *             +-------+
+ */
+void nss_ipsecmgr_ref_free(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_ref *entry;
+
+	while (!list_empty(&ref->head)) {
+		entry = list_first_entry(&ref->head, struct nss_ipsecmgr_ref, node);
+		nss_ipsecmgr_ref_free(priv, entry);
+	}
+
+	list_del_init(&ref->node);
+	ref->free(priv, ref);
+}
+
+/*
+ * nss_ipsecmgr_ref_is_child()
+ * 	return true if the child is direct sibling of parent
+ */
+bool nss_ipsecmgr_ref_is_child(struct nss_ipsecmgr_ref *child, struct nss_ipsecmgr_ref *parent)
+{
+	struct nss_ipsecmgr_ref *entry;
+
+	list_for_each_entry(entry, &parent->head, node) {
+		if (entry == child) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+/*
+ **********************
+ * Netdev ops
+ **********************
+ */
+
+/*
+ * nss_ipsecmgr_tunnel_open()
+ * 	open the tunnel for usage
+ */
+static int nss_ipsecmgr_tunnel_open(struct net_device *dev)
+{
+	struct nss_ipsecmgr_priv *priv;
+
+	priv = netdev_priv(dev);
+
+	netif_start_queue(dev);
+
+	return 0;
+}
+
+/*
+ * nss_ipsecmgr_tunnel_stop()
+ * 	stop the IPsec tunnel
+ */
+static int nss_ipsecmgr_tunnel_stop(struct net_device *dev)
+{
+	struct nss_ipsecmgr_priv *priv;
+
+	priv = netdev_priv(dev);
+
+	netif_stop_queue(dev);
+
+	return 0;
+}
+
+/*
+ * nss_ipsecmgr_tunnel_tx()
+ * 	tunnel transmit function
+ */
+static netdev_tx_t nss_ipsecmgr_tunnel_tx(struct sk_buff *skb, struct net_device *dev)
+{
+	struct nss_ipsecmgr_flow_data flow_data = {0};
+	bool process_mtu = gen_pmtu_error;
+	struct nss_ipsecmgr_priv *priv;
+	bool expand_skb = false;
+	int nhead, ntail;
+	bool tstamp_skb;
+
+	priv = netdev_priv(dev);
+	nhead = dev->needed_headroom;
+	ntail = dev->needed_tailroom;
+
+	tstamp_skb = skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
+
+	/*
+	 * Check if skb is non-linear
+	 */
+	if (skb_is_nonlinear(skb)) {
+		nss_ipsecmgr_trace("%s: NSS IPSEC does not support fragments %px\n", dev->name, skb);
+		goto free;
+	}
+
+	/*
+	 * Check if skb is shared
+	 */
+	if (unlikely(skb_shared(skb))) {
+		nss_ipsecmgr_trace("%s: Shared skb is not supported: %px\n", dev->name, skb);
+		goto free;
+	}
+
+	/*
+	 * Check if packet is given starting from network header
+	 */
+	if (skb->data != skb_network_header(skb)) {
+		nss_ipsecmgr_trace("%s: 'Skb data is not starting from IP header\n", dev->name);
+		goto free;
+	}
+
+	/*
+	 * For all these cases
+	 * - create a writable copy of buffer
+	 * - increase the head room
+	 * - increase the tail room
+	 */
+	if (skb_cloned(skb) || (skb_headroom(skb) < nhead) || (skb_tailroom(skb) < ntail)) {
+		expand_skb = true;
+	}
+
+	if (expand_skb && pskb_expand_head(skb, nhead, ntail, GFP_KERNEL)) {
+		nss_ipsecmgr_trace("%s: unable to expand buffer\n", dev->name);
+		goto free;
+	}
+
+	/*
+	 * Before proceeding check for the following conditions
+	 * For IPv4 packet if DF bit is set then process_mtu
+	 */
+	if (process_mtu && (skb->protocol == htons(ETH_P_IP)))
+		process_mtu = !!(ip_hdr(skb)->frag_off & htons(IP_DF));
+
+	/*
+	 * check whether the IPsec encapsulation can be offloaded to NSS
+	 *	- if the flow matches a subnet rule, then a new flow rule
+	 *		is added to NSS.
+	 *	- if the flow doesn't match any subnet, then the packet
+	 * 		is dropped
+	 */
+	if (!nss_ipsecmgr_flow_offload(priv, skb, &flow_data)) {
+		nss_ipsecmgr_warn("%px:failed to accelerate flow\n", dev);
+		goto free;
+	}
+
+	/*
+	 * Check if pre-fragmentation is not enabled or already a fragment.
+	 * then send the buffer on its way to NSS
+	 */
+	if (process_mtu && nss_ipsecmgr_flow_process_pmtu(priv, skb, &flow_data))
+		goto free;
+
+	/*
+	 * If the packet needs to timestamped. Send to
+	 * timestamping NSS module.
+	 */
+	if (unlikely(tstamp_skb)) {
+		if (nss_tstamp_tx_buf(ipsecmgr_ctx->nss_ctx, skb, NSS_IPSEC_ENCAP_IF_NUMBER))
+			goto free;
+
+		return NETDEV_TX_OK;
+	}
+
+	/*
+	 * Send the packet down
+	 */
+	if (nss_ipsec_tx_buf(skb, ipsecmgr_ctx->encap_ifnum) != 0) {
+		/*
+		 * TODO: NEED TO STOP THE QUEUE
+		 */
+		goto free;
+	}
+
+	return NETDEV_TX_OK;
+
+free:
+	dev_kfree_skb_any(skb);
+	return NETDEV_TX_OK;
+}
+
+/*
+ * nss_ipsecmgr_tunnel_stats()
+ * 	get tunnel statistics
+ */
+static struct rtnl_link_stats64 *nss_ipsecmgr_tunnel_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	struct nss_ipsecmgr_priv *priv = netdev_priv(dev);
+
+	memset(stats, 0, sizeof(struct rtnl_link_stats64));
+
+	/*
+	 * trigger a stats update chain
+	 */
+	read_lock_bh(&ipsecmgr_ctx->lock);
+	memcpy(stats, &priv->stats, sizeof(struct rtnl_link_stats64));
+	read_unlock_bh(&ipsecmgr_ctx->lock);
+
+	return stats;
+}
+
+/*
+ * nss_ipsecmgr_change_mtu()
+ * 	change MTU size of IPsec tunnel device
+ */
+static int32_t nss_ipsecmgr_change_mtu(struct net_device *dev, int32_t mtu)
+{
+	dev->mtu = mtu;
+	return 0;
+}
+
+/* NSS IPsec tunnel operation */
+static const struct net_device_ops nss_ipsecmgr_tunnel_ops = {
+	.ndo_open = nss_ipsecmgr_tunnel_open,
+	.ndo_stop = nss_ipsecmgr_tunnel_stop,
+	.ndo_start_xmit = nss_ipsecmgr_tunnel_tx,
+	.ndo_get_stats64 = nss_ipsecmgr_tunnel_stats64,
+	.ndo_change_mtu = nss_ipsecmgr_change_mtu,
+};
+
+/*
+ * nss_ipsecmgr_tunnel_free()
+ * 	free an existing IPsec tunnel interface
+ */
+static void nss_ipsecmgr_tunnel_free(struct net_device *dev)
+{
+	nss_ipsecmgr_info("IPsec tunnel device(%s) freed\n", dev->name);
+
+	free_netdev(dev);
+}
+
+/*
+ * nss_ipsecmr_setup_tunnel()
+ * 	setup the IPsec tunnel
+ */
+static void nss_ipsecmgr_tunnel_setup(struct net_device *dev)
+{
+	dev->addr_len = ETH_ALEN;
+	dev->mtu = NSS_IPSECMGR_TUN_MTU(ETH_DATA_LEN);
+
+	dev->hard_header_len = NSS_IPSECMGR_TUN_MAX_HDR_LEN;
+	dev->needed_headroom = NSS_IPSECMGR_TUN_HEADROOM;
+	dev->needed_tailroom = NSS_IPSECMGR_TUN_TAILROOM;
+
+	dev->type = NSS_IPSEC_ARPHRD_IPSEC;
+
+	dev->ethtool_ops = NULL;
+	dev->header_ops = NULL;
+	dev->netdev_ops = &nss_ipsecmgr_tunnel_ops;
+
+	dev->destructor = nss_ipsecmgr_tunnel_free;
+
+	/*
+	 * get the MAC address from the ethernet device
+	 */
+	random_ether_addr(dev->dev_addr);
+
+	memset(dev->broadcast, 0xff, dev->addr_len);
+	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
+}
+
+/*
+ * nss_ipsecmgr_tunnel_get_callback()
+ * 	get the callback entry for the dev index
+ *
+ * Note: this is typically expected in the RX BH path
+ */
+static struct nss_ipsecmgr_callback_entry *nss_ipsecmgr_tunnel_get_callback(int dev_index)
+{
+	struct nss_ipsecmgr_callback_db *cb_db = &ipsecmgr_ctx->cb_db;
+	struct nss_ipsecmgr_callback_entry *cb_entry;
+
+	if (!atomic_read(&cb_db->num_entries))
+		return NULL;
+
+	BUG_ON(!in_atomic());
+
+	/*
+	 * search the callback database to find if there
+	 * are any registered callback for the net_device
+	 */
+	read_lock(&ipsecmgr_ctx->lock);				/* lock */
+	list_for_each_entry(cb_entry, &cb_db->entries, node) {
+		if (cb_entry->dev_index == dev_index) {
+			read_unlock(&ipsecmgr_ctx->lock);	/* unlock */
+			return cb_entry;
+		}
+	}
+
+	read_unlock(&ipsecmgr_ctx->lock);			/* unlock */
+
+	return NULL;
+}
+
+/*
+ * nss_ipsecmgr_tunnel_get_dev()
+ *	Get the net_device associated with the packet.
+ */
+static struct net_device *nss_ipsecmgr_tunnel_get_dev(struct sk_buff *skb)
+{
+	struct nss_ipsecmgr_sa_entry *sa_entry;
+	struct nss_ipsec_tuple tuple;
+	struct nss_ipsecmgr_ref *ref;
+	struct nss_ipsecmgr_key key;
+	struct net_device *dev;
+	struct dst_entry *dst;
+	struct ip_esp_hdr *esph;
+	size_t hdr_sz = 0;
+
+	skb_reset_mac_header(skb);
+	skb_reset_network_header(skb);
+
+	switch (ip_hdr(skb)->version) {
+	case IPVERSION:
+	{
+		struct iphdr *iph = ip_hdr(skb);
+		struct rtable *rt;
+		bool is_encap;
+
+		hdr_sz = sizeof(struct iphdr);
+		skb->protocol = cpu_to_be16(ETH_P_IP);
+
+		/*
+		 * Set the transport header skb pointer
+		 */
+		skb_set_transport_header(skb, hdr_sz);
+
+		is_encap = (iph->protocol == IPPROTO_ESP);
+		if (!is_encap && (iph->protocol == IPPROTO_UDP)) {
+			if (udp_hdr(skb)->dest == NSS_IPSECMGR_NATT_PORT_DATA) {
+				hdr_sz += sizeof(struct udphdr);
+				is_encap = true;
+			}
+		}
+
+		if (!is_encap) {
+			rt = ip_route_output(&init_net, iph->saddr, 0, 0, 0);
+			if (IS_ERR(rt)) {
+				return NULL;
+			}
+
+			dst = (struct dst_entry *)rt;
+			dev = dst->dev;
+			dst_release(dst);
+			goto done;
+		}
+
+		nss_ipsecmgr_v4_hdr2tuple(iph, &tuple);
+		break;
+	}
+
+	case 6:
+	{
+		struct ipv6hdr *ip6h = ipv6_hdr(skb);
+		struct flowi6 fl6;
+
+		hdr_sz = sizeof(struct ipv6hdr);
+		skb->protocol = cpu_to_be16(ETH_P_IPV6);
+
+		nss_ipsecmgr_v6_hdr2tuple(ip6h, &tuple);
+
+		if (tuple.proto_next_hdr != IPPROTO_ESP) {
+			memset(&fl6, 0, sizeof(fl6));
+			memcpy(&fl6.daddr, &ip6h->saddr, sizeof(fl6.daddr));
+
+			dst = ip6_route_output(&init_net, NULL, &fl6);
+			if (IS_ERR(dst)) {
+				return NULL;
+			}
+
+			dev = dst->dev;
+			dst_release(dst);
+			goto done;
+		}
+
+		if (ip6h->nexthdr == NEXTHDR_FRAGMENT) {
+			hdr_sz += sizeof(struct frag_hdr);
+		}
+		break;
+	}
+	default:
+		nss_ipsecmgr_warn("%px:could not get dev for the flow\n", skb);
+		return NULL;
+	}
+
+	skb_set_transport_header(skb, hdr_sz);
+	esph = ip_esp_hdr(skb);
+	tuple.esp_spi = ntohl(esph->spi);
+
+	nss_ipsecmgr_sa_tuple2key(&tuple, &key);
+
+	ref = nss_ipsecmgr_sa_lookup(&key);
+	if (!ref) {
+		nss_ipsecmgr_trace("unable to find SA (%px)\n", skb);
+		return NULL;
+	}
+
+	sa_entry = container_of(ref, struct nss_ipsecmgr_sa_entry, ref);
+	dev = sa_entry->priv->dev;
+done:
+
+	skb->pkt_type = PACKET_HOST;
+	skb->skb_iif = dev->ifindex;
+	skb->dev = dev;
+	return dev;
+}
+
+/*
+ * nss_ipsecmgr_tunnel_rx()
+ *	receive NSS exception packets
+ */
+static void nss_ipsecmgr_tunnel_rx(struct net_device *dummy, struct sk_buff *skb, __attribute((unused)) struct napi_struct *napi)
+{
+	struct nss_ipsecmgr_callback_entry *cb_entry;
+	nss_ipsecmgr_data_cb_t cb_fn;
+	struct net_device *dev;
+
+	BUG_ON(dummy == NULL);
+	BUG_ON(skb == NULL);
+
+	dev = nss_ipsecmgr_tunnel_get_dev(skb);
+	if (unlikely(!dev)) {
+		nss_ipsecmgr_trace("cannot find a dev(%px)\n", skb);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	dev_hold(dev);
+
+	/*
+	 * search the device in the registered callback table;
+	 * if there is match then load the callback for indication
+	 */
+	cb_entry = nss_ipsecmgr_tunnel_get_callback(dev->ifindex);
+	if (!cb_entry) {
+		netif_receive_skb(skb);
+		goto done;
+	}
+
+	cb_fn = cb_entry->data;
+	BUG_ON(!cb_fn);
+
+	cb_fn(cb_entry->app_data, skb);
+done:
+	dev_put(dev);
+}
+
+/*
+ * nss_ipsecmgr_tunnel_update_stats()
+ *	Update tunnel stats
+ */
+static void nss_ipsecmgr_tunnel_update_stats(struct nss_ipsecmgr_priv *priv, struct nss_ipsec_msg *nim)
+{
+	struct rtnl_link_stats64 *tun_stats;
+	struct nss_ipsec_sa_stats *pkts;
+
+	tun_stats = &priv->stats;
+	pkts = &nim->msg.stats.sa;
+
+	if (nim->type == NSS_IPSEC_TYPE_ENCAP) {
+		/*
+		 * update tunnel specific stats
+		 */
+		tun_stats->tx_bytes += pkts->bytes;
+		tun_stats->tx_packets += pkts->count;
+
+		tun_stats->tx_dropped += pkts->no_headroom;
+		tun_stats->tx_dropped += pkts->no_tailroom;
+		tun_stats->tx_dropped += pkts->no_resource;
+		tun_stats->tx_dropped += pkts->fail_queue;
+		tun_stats->tx_dropped += pkts->fail_hash;
+		tun_stats->tx_dropped += pkts->fail_replay;
+		return;
+	}
+
+	/*
+	 * update tunnel specific stats
+	 */
+	if (nim->type == NSS_IPSEC_TYPE_ENCAP) {
+		tun_stats->tx_bytes += pkts->bytes;
+		tun_stats->tx_packets += pkts->count;
+
+		tun_stats->tx_dropped += pkts->no_headroom;
+		tun_stats->tx_dropped += pkts->no_tailroom;
+		tun_stats->tx_dropped += pkts->no_resource;
+		tun_stats->tx_dropped += pkts->fail_queue;
+		tun_stats->tx_dropped += pkts->fail_hash;
+		tun_stats->tx_dropped += pkts->fail_replay;
+		return;
+	}
+
+	tun_stats->rx_bytes += pkts->bytes;
+	tun_stats->rx_packets += pkts->count;
+
+	tun_stats->rx_dropped += pkts->no_headroom;
+	tun_stats->rx_dropped += pkts->no_tailroom;
+	tun_stats->rx_dropped += pkts->no_resource;
+	tun_stats->rx_dropped += pkts->fail_queue;
+	tun_stats->rx_dropped += pkts->fail_hash;
+	tun_stats->rx_dropped += pkts->fail_replay;
+}
+
+/*
+ * nss_ipsecmgr_tunnel_notify()
+ * 	asynchronous event reception
+ */
+static void nss_ipsecmgr_tunnel_notify(__attribute((unused))void *app_data, struct nss_ipsec_msg *nim)
+{
+	struct nss_ipsecmgr_node_stats *drv_stats;
+	struct nss_ipsec_node_stats *node_stats;
+	struct nss_ipsecmgr_sa_stats *sa_stats;
+	struct nss_ipsecmgr_event stats_event;
+	struct nss_ipsecmgr_sa_entry *sa;
+	struct nss_ipsec_sa_stats *pkts;
+	struct nss_ipsecmgr_priv *priv;
+	nss_ipsecmgr_event_cb_t cb_fn;
+	struct nss_ipsecmgr_ref *ref;
+	struct nss_ipsecmgr_key key;
+	bool reset_fail_hash;
+	struct net_device *dev;
+
+	BUG_ON(nim == NULL);
+
+	/*
+	 * this holds the ref_cnt for the device
+	 */
+	dev = dev_get_by_index(&init_net, nim->tunnel_id);
+	if (!dev) {
+		nss_ipsecmgr_info("event received on deallocated I/F (%d)\n", nim->tunnel_id);
+		return;
+	}
+
+	priv = netdev_priv(dev);
+
+	switch (nim->cm.type) {
+	case NSS_IPSEC_MSG_TYPE_SYNC_SA_STATS:
+
+		/*
+		 * prepare and lookup sa based on selector sent from nss
+		 */
+		nss_ipsecmgr_sa_tuple2key(&nim->tuple, &key);
+
+		write_lock(&ipsecmgr_ctx->lock);
+
+		ref = nss_ipsecmgr_sa_lookup(&key);
+		if (!ref) {
+			write_unlock(&ipsecmgr_ctx->lock);
+			nss_ipsecmgr_trace("event received on deallocated SA tunnel:(%d)\n", nim->tunnel_id);
+			goto done;
+		}
+
+		sa = container_of(ref, struct nss_ipsecmgr_sa_entry, ref);
+
+		/*
+		 * update sa stats in the local database
+		 */
+		nss_ipsecmgr_sa_stats_update(nim, sa);
+
+		sa_stats = &stats_event.data.stats;
+
+		/*
+		 * update tunnel stats
+		 */
+		sa_stats->fail_hash_alarm = false;
+		nss_ipsecmgr_tunnel_update_stats(priv, nim);
+
+		if ((nim->type == NSS_IPSEC_TYPE_DECAP) &&
+				sa->fail_hash_thresh) {
+			pkts = &nim->msg.stats.sa;
+
+			/*
+			 * If the fail_hash_count is zero and packet count is
+			 * non-zero. It indicates that the continuous hash
+			 * failure was a transient state hence reset the count
+			 */
+			reset_fail_hash = (!pkts->fail_hash_cont &&
+					pkts->count);
+			sa->pkts.fail_hash_cont = reset_fail_hash ? 0
+				: (sa->pkts.fail_hash_cont +
+						pkts->fail_hash_cont);
+
+			/*
+			 * Check the fail_hash_cont hash crossed the threshold,
+			 * if yes set the alarm.
+			 */
+			if (sa->pkts.fail_hash_cont >= sa->fail_hash_thresh) {
+				sa_stats->fail_hash_alarm = true;
+				sa->pkts.fail_hash_cont -= sa->fail_hash_thresh;
+			}
+		}
+
+		memcpy(&sa_stats->sa, &sa->sa_info,
+				sizeof(struct nss_ipsecmgr_sa));
+		sa_stats->crypto_index = sa->nim.msg.rule.data.crypto_index;
+		write_unlock(&ipsecmgr_ctx->lock);
+
+		/*
+		 * if event callback is available then post the statistics using the callback function
+		 */
+		cb_fn = priv->cb.event;
+		if (cb_fn) {
+			stats_event.type = NSS_IPSECMGR_EVENT_SA_STATS;
+
+			/*
+			 * copy stats and SA information
+			 */
+			sa_stats->seq_num = nim->msg.stats.sa.seq_num;
+
+			sa_stats->esn_enabled = nim->msg.stats.sa.esn_enabled;
+			sa_stats->window_max = nim->msg.stats.sa.window_max;
+			sa_stats->window_size = nim->msg.stats.sa.window_size;
+
+			sa_stats->pkts.count = nim->msg.stats.sa.count;
+			sa_stats->pkts.bytes = nim->msg.stats.sa.bytes;
+
+			cb_fn(priv->cb.app_data, &stats_event);
+		}
+
+		break;
+
+	case NSS_IPSEC_MSG_TYPE_SYNC_NODE_STATS:
+
+		drv_stats = &ipsecmgr_ctx->enc_stats;
+		if (unlikely(nim->type == NSS_IPSEC_TYPE_DECAP)) {
+			drv_stats = &ipsecmgr_ctx->dec_stats;
+		}
+
+		node_stats = &nim->msg.stats.node;
+		drv_stats->enqueued += node_stats->enqueued;
+		drv_stats->completed += node_stats->completed;
+		drv_stats->linearized += node_stats->linearized;
+		drv_stats->exceptioned += node_stats->exceptioned;
+		drv_stats->fail_enqueue += node_stats->fail_enqueue;
+
+		break;
+
+	default:
+		break;
+	}
+done:
+	dev_put(dev);
+}
+
+/*
+ * nss_ipsecmgr_node_stats_read()
+ * 	read node statistics
+ */
+static ssize_t nss_ipsecmgr_node_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	struct nss_ipsecmgr_node_stats *enc_stats = &ipsecmgr_ctx->enc_stats;
+	struct nss_ipsecmgr_node_stats *dec_stats = &ipsecmgr_ctx->dec_stats;
+	ssize_t ret = 0;
+	char *local;
+	int len;
+
+	local = vmalloc(NSS_IPSECMGR_MAX_BUF_SZ);
+
+	len = 0;
+	len += snprintf(local + len, NSS_IPSECMGR_MAX_BUF_SZ - len, "\tencap_enqueued: %lld\n", enc_stats->enqueued);
+	len += snprintf(local + len, NSS_IPSECMGR_MAX_BUF_SZ - len, "\tencap_completed: %lld\n", enc_stats->completed);
+	len += snprintf(local + len, NSS_IPSECMGR_MAX_BUF_SZ - len, "\tencap_exceptioned: %lld\n", enc_stats->exceptioned);
+	len += snprintf(local + len, NSS_IPSECMGR_MAX_BUF_SZ - len, "\tencap_enqueue_failed: %lld\n", enc_stats->fail_enqueue);
+
+	len += snprintf(local + len, NSS_IPSECMGR_MAX_BUF_SZ - len, "\tdecap_enqueued: %lld\n", dec_stats->enqueued);
+	len += snprintf(local + len, NSS_IPSECMGR_MAX_BUF_SZ - len, "\tdecap_completed: %lld\n", dec_stats->completed);
+	len += snprintf(local + len, NSS_IPSECMGR_MAX_BUF_SZ - len, "\tdecap_exceptioned: %lld\n", dec_stats->exceptioned);
+	len += snprintf(local + len, NSS_IPSECMGR_MAX_BUF_SZ - len, "\tdecap_enqueue_failed: %lld\n", dec_stats->fail_enqueue);
+
+	ret = simple_read_from_buffer(ubuf, sz, ppos, local, len + 1);
+
+	vfree(local);
+
+	return ret;
+}
+
+/*
+ * file operation structure instance
+ */
+static const struct file_operations node_stats_op = {
+	.open = simple_open,
+	.llseek = default_llseek,
+	.read = nss_ipsecmgr_node_stats_read,
+};
+
+/*
+ * nss_ipsecmgr_tunnel_add()
+ * 	add a IPsec pseudo tunnel device
+ */
+struct net_device *nss_ipsecmgr_tunnel_add(struct nss_ipsecmgr_callback *cb)
+{
+	struct nss_ipsecmgr_callback_db *cb_db = &ipsecmgr_ctx->cb_db;
+	struct nss_ipsecmgr_priv *priv;
+	struct net_device *dev;
+	int status;
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0)
+	dev = alloc_netdev(sizeof(struct nss_ipsecmgr_priv), NSS_IPSECMGR_TUN_NAME, nss_ipsecmgr_tunnel_setup);
+#else
+	dev = alloc_netdev(sizeof(struct nss_ipsecmgr_priv), NSS_IPSECMGR_TUN_NAME, NET_NAME_ENUM, nss_ipsecmgr_tunnel_setup);
+#endif
+	if (!dev) {
+		nss_ipsecmgr_error("unable to allocate a tunnel device\n");
+		return NULL;
+	}
+
+	priv = netdev_priv(dev);
+	priv->dev = dev;
+
+	INIT_LIST_HEAD(&priv->cb.node);
+	priv->cb.dev_index = dev->ifindex;
+	priv->cb.app_data = cb->ctx;
+	priv->cb.data = cb->data_fn;
+	priv->cb.event = cb->event_fn;
+
+	status = rtnl_is_locked() ? register_netdevice(dev) : register_netdev(dev);
+	if (status < 0) {
+		nss_ipsecmgr_error("register net dev failed :%s\n", dev->name);
+		goto fail;
+	}
+
+	/*
+	 * only register if data callback is available
+	 */
+	if (cb->data_fn){
+		write_lock_bh(&ipsecmgr_ctx->lock);
+		list_add(&priv->cb.node, &cb_db->entries);
+		atomic_inc(&cb_db->num_entries);
+		write_unlock_bh(&ipsecmgr_ctx->lock);
+	}
+
+	return dev;
+fail:
+	free_netdev(dev);
+	return NULL;
+}
+EXPORT_SYMBOL(nss_ipsecmgr_tunnel_add);
+
+/*
+ * nss_ipsecmgr_del_tunnel()
+ * 	delete an existing IPsec tunnel
+ */
+bool nss_ipsecmgr_tunnel_del(struct net_device *dev)
+{
+	struct nss_ipsecmgr_callback_db *cb_db = &ipsecmgr_ctx->cb_db;
+	struct nss_ipsecmgr_priv *priv = netdev_priv(dev);
+
+	write_lock_bh(&ipsecmgr_ctx->lock);
+	atomic_dec(&cb_db->num_entries);
+	list_del(&priv->cb.node);
+	write_unlock_bh(&ipsecmgr_ctx->lock);
+
+	nss_ipsecmgr_sa_flush_all(priv);
+
+	/*
+	 * The unregister should start here but the expectation is that the free would
+	 * happen when the reference count goes down to '0'
+	 */
+	rtnl_is_locked() ? unregister_netdevice(dev) : unregister_netdev(dev);
+
+	return true;
+}
+EXPORT_SYMBOL(nss_ipsecmgr_tunnel_del);
+
+/*
+ * nss_ipsecmgr_tunnel_update_callback()
+ * 	update the callback databse with the new device index
+ *
+ * Note: the callback is database that holds callback functions w.r.t a
+ * device index. The tunnel_add would typically load this with the device
+ * index of the tunnel. Overtime the caller can decide to update this with
+ * different device index. In cases where the IPsec stack typically creates
+ * a tunnel device of its own (KLIPS), the callback would then get mapped to
+ * these devices instead of the IPsec manager created tunnel netdevice
+ */
+void nss_ipsecmgr_tunnel_update_callback(struct net_device *tun, struct net_device *cur)
+{
+	struct nss_ipsecmgr_callback_db *cb_db = &ipsecmgr_ctx->cb_db;
+	struct nss_ipsecmgr_callback_entry *cb_entry;
+	int tun_dev_index = tun->ifindex;
+
+	if (!atomic_read(&cb_db->num_entries))
+		return;
+
+	/*
+	 * search the old device index in callback table
+	 * and replace it with the new index
+	 */
+	write_lock_bh(&ipsecmgr_ctx->lock);
+	list_for_each_entry(cb_entry, &cb_db->entries, node) {
+		if (cb_entry->dev_index == tun_dev_index) {
+			cb_entry->dev_index = cur->ifindex;
+			break;
+		}
+	}
+
+	write_unlock_bh(&ipsecmgr_ctx->lock);
+}
+EXPORT_SYMBOL(nss_ipsecmgr_tunnel_update_callback);
+
+static const struct net_device_ops nss_ipsecmgr_ipsec_ndev_ops;
+
+/*
+ * nss_ipsecmgr_dummy_netdevice_setup()
+ *	Setup function for dummy netdevice.
+ */
+static void nss_ipsecmgr_dummy_netdevice_setup(struct net_device *dev)
+{
+}
+
+/*
+ * flow file operation structure instance
+ */
+static const struct file_operations flow_stats_op = {
+	.open = simple_open,
+	.llseek = default_llseek,
+	.read = nss_ipsecmgr_flow_stats_read,
+};
+
+/*
+ * per flow file operation structure instance
+ */
+static const struct file_operations per_flow_stats_op = {
+	.open = simple_open,
+	.llseek = default_llseek,
+	.read = nss_ipsecmgr_per_flow_stats_read,
+	.write = nss_ipsecmgr_per_flow_stats_write,
+};
+
+/*
+ * SA file operation structure instance
+ */
+static const struct file_operations sa_stats_op = {
+	.open = simple_open,
+	.llseek = default_llseek,
+	.read = nss_ipsecmgr_sa_stats_read,
+};
+
+/*
+ * subnet file operation structure instance
+ */
+static const struct file_operations subnet_stats_op = {
+	.open = simple_open,
+	.llseek = default_llseek,
+	.read = nss_ipsecmgr_netmask_stats_read,
+};
+
+/*
+ * nss_ipsecmgr_init_stats_debugfs()
+ *	Initialize the debugfs tree.
+ */
+static int nss_ipsecmgr_init_stats_debugfs(struct dentry *stats_root)
+{
+	if (!debugfs_create_file("subnet", S_IRUGO, stats_root, (uint32_t *)NULL, &subnet_stats_op)) {
+		nss_ipsecmgr_error("Debugfs file creation failed for subnet\n");
+		return -1;
+	}
+
+	if (!debugfs_create_file("sa", S_IRUGO, stats_root, NULL, &sa_stats_op)) {
+		nss_ipsecmgr_error("Debugfs file creation failed for SA\n");
+		return -1;
+	}
+
+	if (!debugfs_create_file("flow", S_IRUGO, stats_root, NULL, &flow_stats_op)) {
+		nss_ipsecmgr_error("Debugfs file creation failed for flow\n");
+		return -1;
+	}
+
+	if (!debugfs_create_file("per_flow", S_IRWXUGO, stats_root, NULL, &per_flow_stats_op)) {
+		nss_ipsecmgr_error("Debugfs file creation failed for per flow\n");
+		return -1;
+	}
+
+	if (!debugfs_create_file("node", S_IRUGO, stats_root, NULL, &node_stats_op)) {
+		nss_ipsecmgr_error("Debugfs file creation failed for per node\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+#if defined NSS_IPSECMGR_PMTU_SUPPORT
+
+/*
+ * nss_ipsecmgr_esp4_rcv()
+ *	IPv4 Receive handler for ESP protocol
+ */
+static int nss_ipsecmgr_tunnel_rx_esp4(struct sk_buff *skb)
+{
+	/*
+	 * TODO:This can potentially receive ESP packets in when
+	 * the outer ESP rule is flushed. In which case the DECAP
+	 * packets entering linux must be bounced through offload
+	 */
+	dev_kfree_skb_any(skb);
+	return 0;
+}
+
+/*
+ * nss_ipsecmgr_esp4_err()
+ *	IPv4 Error handler for ESP protocol
+ */
+static void nss_ipsecmgr_tunnel_error_esp4(struct sk_buff *skb, uint32_t mtu)
+{
+	struct nss_ipsecmgr_sa_entry *sa_entry;
+	struct nss_ipsecmgr_key key = { {0} };
+	struct nss_ipsecmgr_sa_v4 sa = {0};
+	struct nss_ipsecmgr_priv *priv;
+	struct nss_ipsecmgr_ref *ref;
+	struct ip_esp_hdr *esph;
+	struct iphdr *iph;
+
+	/*
+	 * If the ICMP error is not PMTU then return
+	 */
+	if (icmp_hdr(skb)->type != ICMP_DEST_UNREACH)
+		return;
+
+	if (icmp_hdr(skb)->code != ICMP_FRAG_NEEDED)
+		return;
+
+	/*
+	 * Skb data now points to the IP header present in the
+	 * IMCP payload. It will be of the packet which generated the
+	 * PMTU error. Extract the ESP header from the payload.
+	 */
+	iph = (struct iphdr *)skb->data;
+	esph = (struct ip_esp_hdr *)(skb->data + (iph->ihl << 2));
+
+	sa.src_ip = ntohl(iph->saddr);
+	sa.dst_ip = ntohl(iph->daddr);
+	sa.spi_index = ntohl(esph->spi);
+
+	nss_ipsecmgr_v4_sa2key(&sa, &key);
+
+	/*
+	 * Get the SA corresponding to the ESP flow
+	 */
+	read_lock(&ipsecmgr_ctx->lock);
+	ref = nss_ipsecmgr_sa_lookup(&key);
+	if (!ref) {
+		read_unlock(&ipsecmgr_ctx->lock);
+		nss_ipsecmgr_trace("unable to find SA (%px)\n", skb);
+		return;
+	}
+
+	sa_entry = container_of(ref, struct nss_ipsecmgr_sa_entry, ref);
+	priv = sa_entry->priv;
+	BUG_ON(!priv);
+
+	atomic_set(&priv->outer_dst_mtu, mtu);
+	read_unlock(&ipsecmgr_ctx->lock);
+
+	/*
+	 * update new mtu for this flow
+	 */
+	BUG_ON(!dev_net(skb->dev));
+	ipv4_update_pmtu(skb, dev_net(skb->dev), mtu, 0, 0, IPPROTO_ESP, 0);
+	return;
+}
+
+/*
+ * protocol handler for IPv4 ESP
+ */
+static const struct net_protocol nss_ipsecmgr_proto_esp4 = {
+	.handler     = nss_ipsecmgr_tunnel_rx_esp4,
+	.err_handler = nss_ipsecmgr_tunnel_error_esp4,
+	.netns_ok    = 1,
+};
+
+/*
+ * nss_ipsecmgr_esp6_rcv()
+ *	IPV6 Receive handler for ESP protocol
+ */
+static int nss_ipsecmgr_tunnel_rx_esp6(struct sk_buff *skb)
+{
+	/*
+	 * TODO:This can potentially receive ESP packets in when
+	 * the outer ESP rule is flushed. In which case the DECAP
+	 * packets entering linux must be bounced through offload
+	 */
+	dev_kfree_skb_any(skb);
+	return 0;
+}
+
+/*
+ * nss_ipsecmgr_esp6_err()
+ *	IPV6 Error handler for ESP protocol
+ */
+static void nss_ipsecmgr_tunnel_error_esp6(struct sk_buff *skb, struct inet6_skb_parm *opt, uint8_t type,
+								uint8_t code, int32_t offset, uint32_t mtu)
+{
+	struct nss_ipsecmgr_sa_entry *sa_entry;
+	struct nss_ipsecmgr_sa_v6 sa = { {0} };
+	struct nss_ipsecmgr_key key = { {0} };
+	struct nss_ipsecmgr_priv *priv;
+	struct nss_ipsecmgr_ref *ref;
+	struct ip_esp_hdr *esph;
+	struct ipv6hdr *iph;
+
+	/*
+	 * If the ICMP type is not PMTU return
+	 */
+	if (type != ICMPV6_PKT_TOOBIG)
+		return;
+
+	/*
+	 * Skb data now points to the IP header present in the
+	 * IMCP payload. It will be of the packet which generated the
+	 * PMTU error. Extract the ESP header from the payload.
+	 */
+	esph = (struct ip_esp_hdr *)(skb->data + offset);
+	iph = (struct ipv6hdr *)skb->data;
+
+	/*
+	 * Get the selectors from IPv6 header. Compose the key and
+	 * get the decap SA
+	 */
+	nss_ipsecmgr_v6addr_ntoh(iph->daddr.s6_addr32, sa.dst_ip);
+	nss_ipsecmgr_v6addr_ntoh(iph->saddr.s6_addr32, sa.src_ip);
+	sa.spi_index = ntohl(esph->spi);
+
+	nss_ipsecmgr_v6_sa2key(&sa, &key);
+
+	read_lock(&ipsecmgr_ctx->lock);
+	ref = nss_ipsecmgr_sa_lookup(&key);
+	if (!ref) {
+		read_unlock(&ipsecmgr_ctx->lock);
+		nss_ipsecmgr_info("%px: unable to find SA\n", skb);
+		return;
+	}
+
+	sa_entry = container_of(ref, struct nss_ipsecmgr_sa_entry, ref);
+	priv = sa_entry->priv;
+	BUG_ON(!priv);
+
+	atomic_set(&priv->outer_dst_mtu, ntohl(mtu));
+	read_unlock(&ipsecmgr_ctx->lock);
+
+	/*
+	 * Update the PMTU
+	 */
+	BUG_ON(!dev_net(skb->dev));
+	ip6_update_pmtu(skb, dev_net(skb->dev), mtu, 0, 0);
+	return;
+}
+
+/*
+ * protocol handler for IPv6 ESP
+ */
+static struct inet6_protocol nss_ipsecmgr_proto_esp6 = {
+	.handler        =       nss_ipsecmgr_tunnel_rx_esp6,
+	.err_handler    =       nss_ipsecmgr_tunnel_error_esp6,
+	.flags          =       INET6_PROTO_NOPOLICY,
+};
+#endif
+
+/*
+ * nss_ipsecmgr_init()
+ *	module init
+ */
+static int __init nss_ipsecmgr_init(void)
+{
+	int status;
+
+	if (!nss_cmn_get_nss_enabled()) {
+		nss_ipsecmgr_info_always("NSS is not enabled in this platform\n");
+		return 0;
+	}
+
+	ipsecmgr_ctx = vzalloc(sizeof(struct nss_ipsecmgr_drv));
+	if (!ipsecmgr_ctx) {
+		nss_ipsecmgr_info_always("Allocating ipsecmgr context failed\n");
+		return 0;
+	}
+
+	ipsecmgr_ctx->nss_ctx = nss_ipsec_get_context();
+	if (!ipsecmgr_ctx->nss_ctx) {
+		nss_ipsecmgr_info_always("Getting NSS Context failed\n");
+		goto free;
+	}
+
+	ipsecmgr_ctx->data_ifnum = nss_ipsec_get_data_interface();
+	ipsecmgr_ctx->encap_ifnum = nss_ipsec_get_encap_interface();
+	ipsecmgr_ctx->decap_ifnum = nss_ipsec_get_decap_interface();
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0)
+	ipsecmgr_ctx->ndev = alloc_netdev(0, NSS_IPSECMGR_DEFAULT_TUN_NAME, nss_ipsecmgr_dummy_netdevice_setup);
+#else
+	ipsecmgr_ctx->ndev = alloc_netdev(0, NSS_IPSECMGR_DEFAULT_TUN_NAME, NET_NAME_UNKNOWN, nss_ipsecmgr_dummy_netdevice_setup);
+#endif
+	if (!ipsecmgr_ctx->ndev) {
+		nss_ipsecmgr_info_always("Ipsec: Could not allocate ipsec net_device\n");
+		goto free;
+	}
+
+	ipsecmgr_ctx->ndev->netdev_ops = &nss_ipsecmgr_ipsec_ndev_ops;
+
+	status = rtnl_is_locked() ? register_netdevice(ipsecmgr_ctx->ndev) : register_netdev(ipsecmgr_ctx->ndev);
+	if (status) {
+		nss_ipsecmgr_info_always("IPsec: Could not register ipsec net_device\n");
+		goto netdev_free;
+	}
+
+	rwlock_init(&ipsecmgr_ctx->lock);
+	nss_ipsecmgr_init_sa_db(&ipsecmgr_ctx->sa_db);
+	nss_ipsecmgr_init_netmask_db(&ipsecmgr_ctx->net_db);
+	nss_ipsecmgr_init_flow_db(&ipsecmgr_ctx->flow_db);
+	nss_ipsecmgr_init_callback_db(&ipsecmgr_ctx->cb_db);
+
+	nss_ipsec_data_register(ipsecmgr_ctx->data_ifnum, nss_ipsecmgr_tunnel_rx, ipsecmgr_ctx->ndev, 0);
+	nss_ipsec_notify_register(ipsecmgr_ctx->encap_ifnum, nss_ipsecmgr_tunnel_notify, NULL);
+	nss_ipsec_notify_register(ipsecmgr_ctx->decap_ifnum, nss_ipsecmgr_tunnel_notify, NULL);
+
+	/*
+	 * initialize debugfs.
+	 */
+	ipsecmgr_ctx->dentry = debugfs_create_dir("qca-nss-ipsecmgr", NULL);
+	if (!ipsecmgr_ctx->dentry) {
+		nss_ipsecmgr_info_always("Creating debug directory failed\n");
+		goto unregister_dev;
+
+	}
+
+	ipsecmgr_ctx->stats_dentry = debugfs_create_dir("stats", ipsecmgr_ctx->dentry);
+	if (!ipsecmgr_ctx->stats_dentry) {
+		debugfs_remove_recursive(ipsecmgr_ctx->dentry);
+		nss_ipsecmgr_info("Creating debug directory failed\n");
+		goto unregister_dev;
+
+	}
+
+	/*
+	 * Create debugfs entries for SA, flow and subnet
+	 */
+	if (nss_ipsecmgr_init_stats_debugfs(ipsecmgr_ctx->stats_dentry)) {
+		nss_ipsecmgr_info("Creating debug tree failed\n");
+		debugfs_remove_recursive(ipsecmgr_ctx->dentry);
+		goto unregister_dev;
+
+	}
+
+#if defined NSS_IPSECMGR_PMTU_SUPPORT
+
+	/*
+	 * Register a ESP protocol handler only when XFRM is not loaded
+	 */
+	status = inet_add_protocol(&nss_ipsecmgr_proto_esp4, IPPROTO_ESP);
+	if (status < 0) {
+		nss_ipsecmgr_warn("%px:%d in Registering ESP4 Handler\n",
+				ipsecmgr_ctx->nss_ctx, status);
+	}
+
+	status = inet6_add_protocol(&nss_ipsecmgr_proto_esp6, IPPROTO_ESP);
+	if (status < 0) {
+		nss_ipsecmgr_warn("%px:%d in Registering ESP6 Handler\n",
+				ipsecmgr_ctx->nss_ctx, status);
+	}
+#endif
+
+	init_completion(&ipsecmgr_ctx->complete);
+	sema_init(&ipsecmgr_ctx->sem, 1);
+	atomic_set(&ipsecmgr_ctx->seq_num, 0);
+
+	nss_ipsecmgr_info_always("NSS IPsec manager loaded: %s\n", NSS_CLIENT_BUILD_ID);
+	return 0;
+
+unregister_dev:
+	rtnl_is_locked() ? unregister_netdevice(ipsecmgr_ctx->ndev) : unregister_netdev(ipsecmgr_ctx->ndev);
+
+netdev_free:
+	free_netdev(ipsecmgr_ctx->ndev);
+
+free:
+	vfree(ipsecmgr_ctx);
+	ipsecmgr_ctx = NULL;
+
+	return 0;
+}
+
+/*
+ * nss_ipsecmgr_exit()
+ * 	module exit
+ */
+static void __exit nss_ipsecmgr_exit(void)
+{
+	if (!ipsecmgr_ctx) {
+		nss_ipsecmgr_info_always("Invalid ipsecmgr Context\n");
+		return;
+	}
+
+	if (!ipsecmgr_ctx->nss_ctx) {
+		nss_ipsecmgr_info_always("Invalid NSS Context\n");
+		vfree(ipsecmgr_ctx);
+		ipsecmgr_ctx = NULL;
+		return;
+	}
+
+	/*
+	 * Unregister the callbacks from the HLOS as we are no longer
+	 * interested in exception data & async messages
+	 */
+	nss_ipsec_data_unregister(ipsecmgr_ctx->nss_ctx, ipsecmgr_ctx->data_ifnum);
+
+	nss_ipsec_notify_unregister(ipsecmgr_ctx->nss_ctx, ipsecmgr_ctx->encap_ifnum);
+	nss_ipsec_notify_unregister(ipsecmgr_ctx->nss_ctx, ipsecmgr_ctx->decap_ifnum);
+
+	if (ipsecmgr_ctx->ndev) {
+		rtnl_is_locked() ? unregister_netdevice(ipsecmgr_ctx->ndev) : unregister_netdev(ipsecmgr_ctx->ndev);
+	}
+
+	/*
+	 * Remove debugfs directory and entries below that.
+	 */
+	if (ipsecmgr_ctx->dentry) {
+		debugfs_remove_recursive(ipsecmgr_ctx->dentry);
+	}
+
+	/*
+	 * Free the ipsecmgr ctx
+	 */
+	vfree(ipsecmgr_ctx);
+	ipsecmgr_ctx = NULL;
+
+	nss_ipsecmgr_info_always("NSS IPsec manager unloaded\n");
+
+}
+
+MODULE_LICENSE("Dual BSD/GPL");
+
+module_init(nss_ipsecmgr_init);
+module_exit(nss_ipsecmgr_exit);
diff --git a/qca-nss-clients/ipsecmgr/v1.0/nss_ipsecmgr_flow.c b/qca-nss-clients/ipsecmgr/v1.0/nss_ipsecmgr_flow.c
new file mode 100644
index 0000000..43a7993
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v1.0/nss_ipsecmgr_flow.c
@@ -0,0 +1,1125 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTUOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/inet.h>
+#include <linux/of.h>
+#include <linux/ipv6.h>
+#include <linux/kernel.h>
+#include <linux/skbuff.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/rtnetlink.h>
+#include <asm/atomic.h>
+#include <linux/debugfs.h>
+#include <linux/completion.h>
+#include <linux/vmalloc.h>
+#include <net/icmp.h>
+#include <net/route.h>
+#include <net/ip6_route.h>
+
+#include <nss_api_if.h>
+#include <nss_ipsec.h>
+#include <nss_ipsecmgr.h>
+
+#include "nss_ipsecmgr_priv.h"
+
+extern struct nss_ipsecmgr_drv *ipsecmgr_ctx;
+
+/*
+ *
+ * nss_ipsecmgr_flow_resp()
+ * 	response for the flow message
+ *
+ * Note: we don't have anything to process for flow responses as of now
+ */
+static void nss_ipsecmgr_flow_resp(void *app_data, struct nss_ipsec_msg *nim)
+{
+	struct nss_ipsecmgr_flow_entry *flow __attribute__((unused)) = app_data;
+
+	return;
+}
+
+/*
+ * nss_ipsecmgr_flow_update()
+ * 	update the flow with its associated data and notify NSS
+ */
+static void nss_ipsecmgr_flow_update(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_ref *ref, struct nss_ipsec_msg *nim)
+{
+	struct nss_ipsecmgr_flow_entry *flow;
+	struct nss_ipsec_tuple local_tuple;
+	struct nss_ipsec_tuple *flow_tuple;
+	struct nss_ipsec_msg nss_nim;
+
+	flow = container_of(ref, struct nss_ipsecmgr_flow_entry, ref);
+	flow_tuple = &flow->nim.tuple;
+
+	/*
+	 * Create a local copy of flow tuple
+	 */
+	memcpy(&local_tuple, flow_tuple, sizeof(struct nss_ipsec_tuple));
+	memcpy(&flow->nim, nim, sizeof(struct nss_ipsec_msg));
+	flow->data.sa_overhead = nss_ipsecmgr_ref_overhead(ref);
+
+	/*
+	 * If, this flow is only getting updated with a new SA contents. We
+	 * need to make sure that the existing selector remains the same
+	 */
+	if (nss_ipsecmgr_ref_is_updated(ref)) {
+		memcpy(flow_tuple, &local_tuple, sizeof(struct nss_ipsec_tuple));
+	}
+
+	/*
+	 * Convert the message to NSS format
+	 */
+	nss_ipsecmgr_copy_nim(&flow->nim, &nss_nim);
+
+	if (nss_ipsec_tx_msg(ipsecmgr_ctx->nss_ctx, &nss_nim) != NSS_TX_SUCCESS) {
+		/*
+		 * XXX: Stop the TX queue and add this "entry"
+		 * to pending queue
+		 */
+		nss_ipsecmgr_info("%px:unable to send the flow_update message\n", ref);
+		return;
+	}
+}
+
+/*
+ * nss_ipsecmgr_flow_free()
+ * 	free the associated flow entry and notify NSS
+ */
+static void nss_ipsecmgr_flow_free(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_flow_entry *flow = container_of(ref, struct nss_ipsecmgr_flow_entry, ref);
+	struct nss_ipsecmgr_flow_db *db = &ipsecmgr_ctx->flow_db;
+	struct nss_ipsec_msg nss_nim;
+
+	/*
+	 * update the common message structure
+	 */
+	flow->nim.cm.type = NSS_IPSEC_MSG_TYPE_DEL_RULE;
+
+	/*
+	 * Convert the message to NSS format
+	 */
+	nss_ipsecmgr_copy_nim(&flow->nim, &nss_nim);
+
+	if (nss_ipsec_tx_msg(ipsecmgr_ctx->nss_ctx, &nss_nim) != NSS_TX_SUCCESS) {
+		/*
+		 * XXX: add this "entry" to pending queue
+		 */
+		nss_ipsecmgr_info("%px:unable to send flow_free message\n", ref);
+	}
+
+	list_del_init(&flow->node);
+	atomic_dec(&db->num_entries);
+	kfree(flow);
+}
+
+/*
+ * nss_ipsecmgr_flow_dump()
+ *	Display the common info for one flow.
+ */
+static size_t nss_ipsecmgr_flow_dump(struct net_device *dev, struct nss_ipsec_msg *nim, char *buf, int max_len)
+{
+	struct nss_ipsec_tuple *tuple = &nim->tuple;
+	struct nss_ipsec_rule_oip *oip = &nim->msg.rule.oip;
+	uint32_t src_ip[4] = {0}, dst_ip[4] = {0};
+	uint32_t esp_spi;
+	size_t len;
+	char *type;
+
+	switch (nim->type) {
+	case NSS_IPSEC_TYPE_ENCAP:
+		type = "encap";
+		esp_spi = oip->esp_spi;
+		break;
+
+	case NSS_IPSEC_TYPE_DECAP:
+		type = "decap";
+		esp_spi = tuple->esp_spi;
+		break;
+
+	default:
+		nss_ipsecmgr_info("%px:Invalid interface type(%d)\n", nim, nim->type);
+		return 0;
+
+	}
+
+	switch (tuple->ip_ver) {
+	case IPVERSION:
+		len = snprintf(buf, max_len, "3-tuple type=%s tunnelid=%s ip_ver=4 src_ip=%pI4h dst_ip=%pI4h proto=%d spi=%x\n",
+				type, dev->name, &tuple->src_addr[0], &tuple->dst_addr[0], tuple->proto_next_hdr, esp_spi);
+		break;
+
+	case 6:
+		nss_ipsecmgr_v6addr_hton(tuple->dst_addr, dst_ip);
+		nss_ipsecmgr_v6addr_hton(tuple->src_addr, src_ip);
+
+		len = snprintf(buf, max_len, "3-tuple type=%s tunnelid=%s ip_ver=6 src_ip=%pI6c dst_ip=%pI6c proto=%d spi=%x\n",
+				type, dev->name, src_ip, dst_ip, tuple->proto_next_hdr, esp_spi);
+		break;
+
+	default:
+		nss_ipsecmgr_info("%px:Invalid IP_VERSION (%d)\n", tuple, tuple->ip_ver);
+		return 0;
+	}
+
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_flow_stats_read()
+ *	read flow statistics
+ */
+ssize_t nss_ipsecmgr_flow_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	struct nss_ipsecmgr_flow_db *db = &ipsecmgr_ctx->flow_db;
+	struct nss_ipsecmgr_flow_entry *entry;
+	struct nss_ipsec_rule_data *data;
+	struct net_device *dev;
+	struct list_head *head;
+	uint32_t num_entries;
+	uint32_t len;
+	ssize_t ret;
+	int max_len;
+	char *buf;
+	int i;
+
+	num_entries = atomic_read(&db->num_entries);
+	if (!num_entries) {
+		return 0;
+	}
+
+	len = 0;
+	max_len = (num_entries * NSS_IPSECMGR_PER_FLOW_STATS_SIZE);
+
+	buf = vzalloc(max_len);
+	if (!buf) {
+		nss_ipsecmgr_error("Memory allocation failed for buffer\n");
+		return 0;
+	}
+
+	read_lock_bh(&ipsecmgr_ctx->lock);
+
+	/*
+	 * Get the flow information from flow db. for both encap and decap
+	 */
+	head = db->entries;
+
+	for (i = NSS_IPSECMGR_MAX_FLOW; ((max_len - len) > 0) && i--; head++) {
+		list_for_each_entry(entry, head, node) {
+			dev = dev_get_by_index(&init_net, entry->nim.tunnel_id);
+			if (!dev) {
+
+				/*
+				 * If, the associated tunnel is deleted and
+				 * the flow remains in table then reassociate
+				 * the flow to the default tunnel
+				 */
+				dev = ipsecmgr_ctx->ndev;
+				dev_hold(dev);
+				entry->nim.tunnel_id = dev->ifindex;
+			}
+
+			if (unlikely((max_len - len) <= 0)) {
+				dev_put(dev);
+				break;
+			}
+
+			data = &entry->nim.msg.rule.data;
+			len += nss_ipsecmgr_flow_dump(dev, &entry->nim, buf + len, max_len - len);
+			len += snprintf(buf + len, max_len - len, "cindex:%d\n\n", data->crypto_index);
+
+			dev_put(dev);
+		}
+	}
+
+	read_unlock_bh(&ipsecmgr_ctx->lock);
+
+	ret = simple_read_from_buffer(ubuf, sz, ppos, buf, len);
+	vfree(buf);
+
+	return ret;
+}
+
+/*
+ * nss_ipsecmgr_per_flow_stats_resp()
+ *	response for the flow message
+ *	Note: we don't have anything to process for flow responses as of now
+ */
+static void nss_ipsecmgr_per_flow_stats_resp(void *app_data, struct nss_ipsec_msg *nim)
+{
+	struct nss_ipsec_msg *resp_nim = &ipsecmgr_ctx->resp_nim;
+
+	/*
+	 * Match the sequence number of the nim from NSS to that of the
+	 * global resp nim. This will ensure the response is valid against
+	 * flow parameters stored in global reponse nim. This will help to
+	 * discard any stale responses from NSS.
+	 */
+	if (nim->cm.app_data != atomic_read(&ipsecmgr_ctx->seq_num)) {
+		resp_nim->cm.response = NSS_CMN_RESPONSE_EMSG;
+		goto done;
+
+	}
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		resp_nim->cm.response = nim->cm.response;
+		goto done;
+	}
+
+	/*
+	 * Cannot copy entire nim because IP addresses will be in diffrent format in side the nim
+	 */
+	resp_nim->msg.stats.flow.processed  = nim->msg.stats.flow.processed;
+	resp_nim->cm.response = nim->cm.response;
+
+done:
+	complete(&ipsecmgr_ctx->complete);
+}
+
+/*
+ * nss_ipsecmgr_per_flow_stats_read()
+ *	read flow statistics
+ */
+ssize_t nss_ipsecmgr_per_flow_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	struct nss_ipsec_flow_stats *flow_stats;
+	struct nss_ipsec_msg *flow_nim, nss_nim;
+	ssize_t ret, len, max_len;
+	struct net_device *dev;
+	char *buf;
+
+	/*
+	 * only one caller will be allowed to send a message
+	 */
+	if (down_interruptible(&ipsecmgr_ctx->sem)) {
+		return 0;
+	}
+
+	flow_nim  = &ipsecmgr_ctx->resp_nim;
+
+	/*
+	 * The check is to ensure prevent the corrupted or uninitialized
+	 * nim to be send to NSS.
+	 */
+	if (flow_nim->cm.len != NSS_IPSEC_MSG_LEN) {
+		nss_ipsecmgr_error("wrong message length\n");
+		goto error;
+	}
+
+	/*
+	 * Update the sequence number in the app_data field of common message.
+	 */
+	flow_nim->cm.app_data = atomic_read(&ipsecmgr_ctx->seq_num);
+
+	/*
+	 * Before send the nim to NSS convert the ip addresses to NSS order
+	 */
+	nss_ipsecmgr_copy_nim(flow_nim, &nss_nim);
+
+	/*
+	 * send stats message to nss
+	 */
+	if (nss_ipsec_tx_msg(ipsecmgr_ctx->nss_ctx, &nss_nim) != NSS_TX_SUCCESS) {
+		nss_ipsecmgr_error("nss tx msg error\n");
+		goto error;
+	}
+
+	/*
+	 * Blocking call, wait till we get ACK for this msg.
+	 */
+	ret = wait_for_completion_timeout(&ipsecmgr_ctx->complete, NSS_IPSECMGR_MSG_SYNC_TIMEOUT_TICKS);
+	if (!ret) {
+		nss_ipsecmgr_error("nss stats message timed out \n");
+
+		/*
+		 * increment the seq_num so that if any stale response comes
+		 * it will get ignored.
+		 */
+		atomic_inc(&ipsecmgr_ctx->seq_num);
+
+		goto error;
+	}
+
+	/*
+	 * need to ensure that the response data has correctly arrived in
+	 * current CPU cache
+	 */
+	smp_rmb();
+
+	if (flow_nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		goto error;
+	}
+
+	buf = vzalloc(NSS_IPSECMGR_PER_FLOW_STATS_SIZE);
+	if (!buf) {
+		nss_ipsecmgr_error("Memory allocation failed for buffer\n");
+		goto error;
+	}
+
+	dev = dev_get_by_index(&init_net, flow_nim->tunnel_id);
+	if (!dev) {
+
+		/*
+		 * Clean the global response nim
+		 */
+		memset(&ipsecmgr_ctx->resp_nim, 0, sizeof(ipsecmgr_ctx->resp_nim));
+		vfree(buf);
+		goto error;
+	}
+
+	/*
+	 * packet stats
+	 */
+	max_len = NSS_IPSECMGR_PER_FLOW_STATS_SIZE;
+	len = nss_ipsecmgr_flow_dump(dev, flow_nim, buf, max_len);
+
+	max_len = max_len - len;
+	if (max_len <= 0) {
+		goto done;
+	}
+
+	flow_stats = &flow_nim->msg.stats.flow;
+	len += snprintf(buf + len, max_len, "processed: %d\n\n", flow_stats->processed);
+done:
+	ret = simple_read_from_buffer(ubuf, sz, ppos, buf, len);
+
+	dev_put(dev);
+	vfree(buf);
+	up(&ipsecmgr_ctx->sem);
+
+	return ret;
+
+error:
+	up(&ipsecmgr_ctx->sem);
+	return 0;
+}
+
+/*
+ * nss_ipsecmgr_per_flow_stats_write()
+ *	write flow entry
+ */
+ssize_t nss_ipsecmgr_per_flow_stats_write(struct file *file, const char __user *ubuf, size_t count, loff_t *f_pos)
+{
+	struct nss_ipsec_msg *resp_nim = &ipsecmgr_ctx->resp_nim;
+	uint8_t *buf, *src_ip, *dst_ip, *type, *tunnel_id;
+	uint32_t interface, ip_ver, proto;
+	struct nss_ipsec_tuple *tuple;
+	struct nss_ipsec_rule_oip *oip;
+	struct net_device *dev;
+	uint32_t buf_size;
+	ssize_t ret;
+	int status;
+
+	if (*f_pos > NSS_IPSECMGR_PER_FLOW_BUF_SIZE) {
+		return -EINVAL;
+	}
+
+	/*
+	 * add all the expected input buffers into a single
+	 * one
+	 */
+	buf_size = NSS_IPSECMGR_PER_FLOW_BUF_SIZE;
+	buf_size = buf_size + NSS_IPSECMGR_PER_FLOW_BUF_SRC_IP_SIZE;
+	buf_size = buf_size + NSS_IPSECMGR_PER_FLOW_BUF_DST_IP_SIZE;
+	buf_size = buf_size + NSS_IPSECMGR_PER_FLOW_BUF_TYPE_SIZE;
+	buf_size = buf_size + IFNAMSIZ;
+
+	buf = vzalloc(buf_size);
+	if (!buf) {
+		return -ENOMEM;
+	}
+
+	ret = simple_write_to_buffer(buf, NSS_IPSECMGR_PER_FLOW_BUF_SIZE, f_pos, ubuf, count);
+	if (ret < 0) {
+		vfree(buf);
+		return -ENOMEM;
+	}
+
+	/*
+	 * need to ensure that the buffer ends with NULL character
+	 */
+	buf[ret] = '\0';
+
+	/*
+	 * only one outstanding read or write is allowed
+	 */
+	if (down_interruptible(&ipsecmgr_ctx->sem)) {
+		vfree(buf);
+		return -EINTR;
+	}
+
+	/*
+	 * increment the sequence no. here to ensure
+	 * that the any pending responses after this
+	 * are invalid
+	 */
+	atomic_inc(&ipsecmgr_ctx->seq_num);
+
+	/*
+	 * prepare for string to numeric conversion of the data
+	 */
+	tuple  = &resp_nim->tuple;
+	oip  = &resp_nim->msg.rule.oip;
+	src_ip = buf + NSS_IPSECMGR_PER_FLOW_BUF_SIZE;
+	dst_ip = src_ip + NSS_IPSECMGR_PER_FLOW_BUF_SRC_IP_SIZE;
+	type = dst_ip + NSS_IPSECMGR_PER_FLOW_BUF_DST_IP_SIZE;
+	tunnel_id = type + NSS_IPSECMGR_PER_FLOW_BUF_TYPE_SIZE;
+
+	status = sscanf(buf, "type=%s tunnelid=%s ip_ver=%d src_ip=%s dst_ip=%s proto=%d spi=%x",
+			type, tunnel_id, &ip_ver, src_ip, dst_ip, &proto, &tuple->esp_spi);
+	if (status <= 0) {
+		goto error;
+	}
+
+	if (strcmp(type, "encap") && strcmp(type, "decap")) {
+		goto error;
+	}
+
+	if ((ip_ver != IPVERSION) && (ip_ver != 6)) {
+		goto error;
+	}
+
+	dev = dev_get_by_name(&init_net, tunnel_id);
+	if (!dev) {
+		nss_ipsecmgr_info("Invalid tunnel Id:%s\n", tunnel_id);
+		goto error;
+	}
+
+	resp_nim->tunnel_id = dev->ifindex;
+	dev_put(dev);
+
+	tuple->proto_next_hdr = proto;
+
+	switch (ip_ver) {
+	case IPVERSION: /* ipv4 */
+		in4_pton(src_ip, strlen(src_ip), (uint8_t *)&tuple->src_addr[0], '\0', NULL);
+		tuple->src_addr[0] = ntohl(tuple->src_addr[0]);
+
+		in4_pton(dst_ip, strlen(dst_ip), (uint8_t *)&tuple->dst_addr[0], '\0', NULL);
+		tuple->dst_addr[0] = ntohl(tuple->dst_addr[0]);
+
+		tuple->ip_ver = IPVERSION;
+		break;
+
+	case 6: /* ipv6 */
+		in6_pton(src_ip, strlen(src_ip), (uint8_t *)&tuple->src_addr[0], '\0', NULL);
+		nss_ipsecmgr_v6addr_ntoh(tuple->src_addr, tuple->src_addr);
+
+		in6_pton(dst_ip, strlen(dst_ip), (uint8_t *)&tuple->dst_addr[0], '\0', NULL);
+		nss_ipsecmgr_v6addr_ntoh(tuple->dst_addr, tuple->dst_addr);
+
+		tuple->ip_ver = 6;
+		break;
+
+	default:
+		BUG_ON(true);
+	}
+
+	/*
+	 * prepare IPsec message
+	 */
+	if (!strcmp(type, "encap")) {
+		interface = ipsecmgr_ctx->encap_ifnum;
+		resp_nim->type = NSS_IPSEC_TYPE_ENCAP;
+		oip->esp_spi = tuple->esp_spi;
+	} else {
+		interface = ipsecmgr_ctx->decap_ifnum;
+		resp_nim->type = NSS_IPSEC_TYPE_DECAP;
+	}
+
+	nss_ipsec_msg_init(resp_nim, interface, NSS_IPSEC_MSG_TYPE_SYNC_FLOW_STATS, NSS_IPSEC_MSG_LEN, nss_ipsecmgr_per_flow_stats_resp, NULL);
+
+	vfree(buf);
+	up(&ipsecmgr_ctx->sem);
+	return ret;
+
+error:
+	memset(resp_nim, 0, sizeof(struct nss_ipsec_msg));
+	vfree(buf);
+	up(&ipsecmgr_ctx->sem);
+	return -EINVAL;
+}
+
+/*
+ * nss_ipsecmgr_encap_flow_init()
+ * 	initiallize the encap flow with a particular type
+ */
+void nss_ipsecmgr_encap_flow_init(struct nss_ipsec_msg *nim, enum nss_ipsec_msg_type type, struct nss_ipsecmgr_priv *priv)
+{
+	memset(nim, 0, sizeof(struct nss_ipsec_msg));
+	nss_ipsec_msg_init(nim, ipsecmgr_ctx->encap_ifnum, type, NSS_IPSEC_MSG_LEN, nss_ipsecmgr_flow_resp, priv->dev);
+	nim->tunnel_id = priv->dev->ifindex;
+	nim->type = NSS_IPSEC_TYPE_ENCAP;
+}
+
+/*
+ * nss_ipsecmgr_decap_flow_init()
+ * 	initiallize the decap flow with a particular type
+ */
+void nss_ipsecmgr_decap_flow_init(struct nss_ipsec_msg *nim, enum nss_ipsec_msg_type type, struct nss_ipsecmgr_priv *priv)
+{
+	memset(nim, 0, sizeof(struct nss_ipsec_msg));
+	nss_ipsec_msg_init(nim, ipsecmgr_ctx->decap_ifnum, type, NSS_IPSEC_MSG_LEN, nss_ipsecmgr_flow_resp, priv->dev);
+	nim->tunnel_id = priv->dev->ifindex;
+	nim->type = NSS_IPSEC_TYPE_DECAP;
+}
+
+/*
+ * nss_ipsecmgr_copy_encap_v4_flow()
+ * 	copy flow data into the selector
+ */
+void nss_ipsecmgr_copy_encap_v4_flow(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_encap_v4_tuple *flow)
+{
+	struct nss_ipsec_tuple *tuple = &nim->tuple;
+
+	tuple->dst_addr[0] = flow->dst_ip;
+	tuple->src_addr[0] = flow->src_ip;
+	tuple->proto_next_hdr = flow->protocol;
+	tuple->ip_ver = IPVERSION;
+
+	tuple->esp_spi = 0;
+	tuple->dst_port = 0;
+	tuple->src_port = 0;
+}
+
+/*
+ * nss_ipsecmgr_copy_decap_v4_flow()
+ * 	copy decap flow
+ */
+void nss_ipsecmgr_copy_decap_v4_flow(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_sa_v4 *flow)
+{
+	struct nss_ipsec_tuple *tuple = &nim->tuple;
+
+	tuple->dst_addr[0] = flow->dst_ip;
+	tuple->src_addr[0] = flow->src_ip;
+	tuple->proto_next_hdr = IPPROTO_ESP;
+	tuple->esp_spi = flow->spi_index;
+	tuple->ip_ver = IPVERSION;
+
+	tuple->dst_port = 0;
+	tuple->src_port = 0;
+}
+
+/*
+ * nss_ipsecmgr_encap_v4_flow2key()
+ * 	convert an encap v4_flow into a key
+ */
+void nss_ipsecmgr_encap_v4_flow2key(struct nss_ipsecmgr_encap_v4_tuple *flow, struct nss_ipsecmgr_key *key)
+{
+	nss_ipsecmgr_key_reset(key);
+
+	nss_ipsecmgr_key_write_8(key, 4 /* v4 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+	nss_ipsecmgr_key_write_8(key, flow->protocol, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+	nss_ipsecmgr_key_write_32(key, flow->dst_ip, NSS_IPSECMGR_KEY_POS_IPV4_DST);
+	nss_ipsecmgr_key_write_32(key, flow->src_ip, NSS_IPSECMGR_KEY_POS_IPV4_SRC);
+
+	key->len = NSS_IPSECMGR_KEY_LEN_IPV4_ENCAP_FLOW;
+}
+
+/*
+ * nss_ipsecmgr_decap_v4_flow2key()
+ * 	convert a decap flow into a key
+ */
+void nss_ipsecmgr_decap_v4_flow2key(struct nss_ipsecmgr_sa_v4 *flow, struct nss_ipsecmgr_key *key)
+{
+	nss_ipsecmgr_key_reset(key);
+
+	nss_ipsecmgr_key_write_8(key, 4 /* v4 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+	nss_ipsecmgr_key_write_8(key, IPPROTO_ESP, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+	nss_ipsecmgr_key_write_32(key, flow->dst_ip, NSS_IPSECMGR_KEY_POS_IPV4_DST);
+	nss_ipsecmgr_key_write_32(key, flow->src_ip, NSS_IPSECMGR_KEY_POS_IPV4_SRC);
+	nss_ipsecmgr_key_write_32(key, flow->spi_index, NSS_IPSECMGR_KEY_POS_IPV4_ESP_SPI);
+
+	key->len = NSS_IPSECMGR_KEY_LEN_IPV4_DECAP_FLOW;
+}
+
+/*
+ * nss_ipsecmgr_encap_v4_tuple2key()
+ * 	convert a selector to key
+ */
+void nss_ipsecmgr_encap_tuple2key(struct nss_ipsec_tuple *tuple, struct nss_ipsecmgr_key *key)
+{
+	uint32_t i;
+
+	nss_ipsecmgr_key_reset(key);
+	switch (tuple->ip_ver) {
+	case IPVERSION:
+		nss_ipsecmgr_key_write_8(key, 4 /* v4 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+		nss_ipsecmgr_key_write_8(key, tuple->proto_next_hdr, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+		nss_ipsecmgr_key_write_32(key, nss_ipsecmgr_get_v4addr(tuple->dst_addr), NSS_IPSECMGR_KEY_POS_IPV4_DST);
+		nss_ipsecmgr_key_write_32(key, nss_ipsecmgr_get_v4addr(tuple->src_addr), NSS_IPSECMGR_KEY_POS_IPV4_SRC);
+
+		key->len = NSS_IPSECMGR_KEY_LEN_IPV4_ENCAP_FLOW;
+		break;
+
+	case 6:
+		nss_ipsecmgr_key_write_8(key, 6 /* v6 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+		nss_ipsecmgr_key_write_8(key, tuple->proto_next_hdr, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+
+		for (i  = 0; i < 4; i++) {
+			nss_ipsecmgr_key_write_32(key, tuple->dst_addr[i], NSS_IPSECMGR_KEY_POS_IPV6_DST + (i * 32));
+			nss_ipsecmgr_key_write_32(key, tuple->src_addr[i], NSS_IPSECMGR_KEY_POS_IPV6_SRC + (i * 32));
+		}
+
+		key->len = NSS_IPSECMGR_KEY_LEN_IPV6_ENCAP_FLOW;
+		break;
+
+	default:
+		nss_ipsecmgr_warn("%px:Invalid selector\n", tuple);
+		return;
+	}
+}
+
+/*
+ * nss_ipsecmgr_decap_tuple2key()
+ * 	convert a selector to key
+ */
+void nss_ipsecmgr_decap_tuple2key(struct nss_ipsec_tuple *tuple, struct nss_ipsecmgr_key *key)
+{
+	uint32_t i;
+
+	nss_ipsecmgr_key_reset(key);
+
+	switch (tuple->ip_ver) {
+	case IPVERSION:
+		nss_ipsecmgr_key_write_8(key, 4 /* v4 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+		nss_ipsecmgr_key_write_8(key, IPPROTO_ESP, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+		nss_ipsecmgr_key_write_32(key, nss_ipsecmgr_get_v4addr(tuple->dst_addr), NSS_IPSECMGR_KEY_POS_IPV4_DST);
+		nss_ipsecmgr_key_write_32(key, nss_ipsecmgr_get_v4addr(tuple->src_addr), NSS_IPSECMGR_KEY_POS_IPV4_SRC);
+		nss_ipsecmgr_key_write_32(key, tuple->esp_spi, NSS_IPSECMGR_KEY_POS_IPV4_ESP_SPI);
+
+		key->len = NSS_IPSECMGR_KEY_LEN_IPV4_DECAP_FLOW;
+		break;
+
+	case 6:
+		nss_ipsecmgr_key_write_8(key, 6 /* v6 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+		nss_ipsecmgr_key_write_8(key, IPPROTO_ESP, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+
+		for (i  = 0; i < 4; i++) {
+			nss_ipsecmgr_key_write_32(key, tuple->dst_addr[i], NSS_IPSECMGR_KEY_POS_IPV6_DST + (i * 32));
+			nss_ipsecmgr_key_write_32(key, tuple->src_addr[i], NSS_IPSECMGR_KEY_POS_IPV6_SRC + (i * 32));
+		}
+
+		nss_ipsecmgr_key_write_32(key, tuple->esp_spi, NSS_IPSECMGR_KEY_POS_IPV6_ESP_SPI);
+
+		key->len = NSS_IPSECMGR_KEY_LEN_IPV6_DECAP_FLOW;
+		break;
+
+	default:
+		nss_ipsecmgr_warn("%px:Invalid selector\n", tuple);
+		return;
+	}
+}
+
+/*
+ * nss_ipsecmgr_copy_encap_v6_flow()
+ * 	copy flow data into the selector
+ */
+void nss_ipsecmgr_copy_encap_v6_flow(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_encap_v6_tuple *flow)
+{
+	struct nss_ipsec_tuple *tuple = &nim->tuple;
+
+	memcpy(tuple->src_addr, flow->src_ip, sizeof(uint32_t) * 4);
+	memcpy(tuple->dst_addr, flow->dst_ip, sizeof(uint32_t) * 4);
+
+	tuple->proto_next_hdr = flow->next_hdr;
+	tuple->ip_ver = 6;
+
+	tuple->esp_spi = 0;
+	tuple->dst_port = 0;
+	tuple->src_port = 0;
+}
+
+/*
+ * nss_ipsecmgr_copy_decap_v6_flow()
+ * 	copy decap flow
+ */
+void nss_ipsecmgr_copy_decap_v6_flow(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_sa_v6 *flow)
+{
+	struct nss_ipsec_tuple *tuple = &nim->tuple;
+
+	memcpy(tuple->src_addr, flow->src_ip, sizeof(uint32_t) * 4);
+	memcpy(tuple->dst_addr, flow->dst_ip, sizeof(uint32_t) * 4);
+
+	tuple->esp_spi = flow->spi_index;
+	tuple->ip_ver = 6;
+
+	tuple->proto_next_hdr = IPPROTO_ESP;
+
+	tuple->dst_port = 0;
+	tuple->src_port = 0;
+}
+
+/*
+ * nss_ipsecmgr_encap_v6_flow2key()
+ * 	convert an encap v6_flow into a key
+ */
+void nss_ipsecmgr_encap_v6_flow2key(struct nss_ipsecmgr_encap_v6_tuple *flow, struct nss_ipsecmgr_key *key)
+{
+	uint32_t i;
+
+	nss_ipsecmgr_key_reset(key);
+
+	nss_ipsecmgr_key_write_8(key, 6 /* v6 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+	nss_ipsecmgr_key_write_8(key, flow->next_hdr, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+
+	for (i  = 0; i < 4; i++) {
+		nss_ipsecmgr_key_write_32(key, flow->dst_ip[i], NSS_IPSECMGR_KEY_POS_IPV6_DST + (i * 32));
+		nss_ipsecmgr_key_write_32(key, flow->src_ip[i], NSS_IPSECMGR_KEY_POS_IPV6_SRC + (i * 32));
+	}
+
+	key->len = NSS_IPSECMGR_KEY_LEN_IPV6_ENCAP_FLOW;
+}
+
+/*
+ * nss_ipsecmgr_decap_v6_flow2key()
+ * 	convert a decap flow into a key
+ */
+void nss_ipsecmgr_decap_v6_flow2key(struct nss_ipsecmgr_sa_v6 *flow, struct nss_ipsecmgr_key *key)
+{
+	uint32_t i;
+
+	nss_ipsecmgr_key_reset(key);
+
+	nss_ipsecmgr_key_write_8(key, 6 /* v6 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+	nss_ipsecmgr_key_write_8(key, IPPROTO_ESP, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+
+	for (i  = 0; i < 4; i++) {
+		nss_ipsecmgr_key_write_32(key, flow->dst_ip[i], NSS_IPSECMGR_KEY_POS_IPV6_DST + (i * 32));
+		nss_ipsecmgr_key_write_32(key, flow->src_ip[i], NSS_IPSECMGR_KEY_POS_IPV6_SRC + (i * 32));
+	}
+
+	nss_ipsecmgr_key_write_32(key, flow->spi_index, NSS_IPSECMGR_KEY_POS_IPV6_ESP_SPI);
+
+	key->len = NSS_IPSECMGR_KEY_LEN_IPV6_DECAP_FLOW;
+}
+
+/*
+ * nss_ipsecmgr_flow_lookup()
+ * 	lookup flow in flow_db
+ */
+struct nss_ipsecmgr_ref *nss_ipsecmgr_flow_lookup(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key)
+{
+	struct nss_ipsecmgr_flow_db *db = &ipsecmgr_ctx->flow_db;
+	struct nss_ipsecmgr_flow_entry *entry;
+	struct list_head *head;
+	int idx;
+
+	idx = nss_ipsecmgr_key_data2idx(key, NSS_IPSECMGR_MAX_FLOW);
+	head = &db->entries[idx];
+
+	list_for_each_entry(entry, head, node) {
+		if (nss_ipsecmgr_key_cmp(&entry->key, key)) {
+			return &entry->ref;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_ipsecmgr_flow_alloc()
+ * 	allocate a flow entry
+ */
+struct nss_ipsecmgr_ref *nss_ipsecmgr_flow_alloc(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key)
+{
+	struct nss_ipsecmgr_flow_entry *flow;
+	struct nss_ipsecmgr_flow_db *db;
+	struct nss_ipsecmgr_ref *ref;
+	int idx;
+
+	/*
+	 * flow lookup before allocating a new one
+	 */
+	ref = nss_ipsecmgr_flow_lookup(priv, key);
+	if (ref) {
+		return ref;
+	}
+
+	flow = kzalloc(sizeof(struct nss_ipsecmgr_flow_entry), GFP_ATOMIC);
+	if (!flow) {
+		nss_ipsecmgr_info("failed to alloc flow_entry\n");
+		return NULL;
+	}
+
+	flow->priv = priv;
+	ref = &flow->ref;
+
+	/*
+	 * add flow to the database
+	 */
+	db = &ipsecmgr_ctx->flow_db;
+	INIT_LIST_HEAD(&flow->node);
+
+	/*
+	 * update key
+	 */
+	idx = nss_ipsecmgr_key_data2idx(key, NSS_IPSECMGR_MAX_FLOW);
+
+	memcpy(&flow->key, key, sizeof(struct nss_ipsecmgr_key));
+	list_add(&flow->node, &db->entries[idx]);
+
+	atomic_inc(&db->num_entries);
+
+	/*
+	 * initiallize the reference object
+	 */
+	nss_ipsecmgr_ref_init(ref, nss_ipsecmgr_flow_update, nss_ipsecmgr_flow_free);
+
+	return ref;
+}
+
+/*
+ * nss_ipsecmgr_flow_process_pmtu()
+ *	process the mtu and send an ICMP error
+ *
+ * note: in case we do not send an ICMP error back to sender
+ * then we rely on post fragmentation to handle larger than
+ * MTU size packets
+ */
+bool nss_ipsecmgr_flow_process_pmtu(struct nss_ipsecmgr_priv *priv,
+			struct sk_buff *skb,
+			struct nss_ipsecmgr_flow_data *data)
+{
+	struct dst_entry *dst;
+	struct flowi6 fl6;
+	struct rtable *rt;
+	uint32_t mtu;
+
+	/*
+	 * If length of the packet is more than computed MTU,
+	 * then send ICMP PMTU error back to Linux
+	 */
+	mtu = atomic_read(&priv->outer_dst_mtu) - data->sa_overhead;
+	if (likely(mtu >= skb->len))
+		return false;
+
+	switch (skb->protocol) {
+	case htons(ETH_P_IP):
+		if (unlikely(skb_dst(skb)))
+			goto send_icmp;
+
+		rt = ip_route_output(&init_net, ip_hdr(skb)->daddr, 0, 0, 0);
+		if (IS_ERR(rt)) {
+			return false;
+		}
+
+		if (rt->rt_type != RTN_UNICAST && rt->rt_type != RTN_LOCAL) {
+			ip_rt_put(rt);
+			return false;
+		}
+
+		skb_dst_set(skb, &rt->dst);
+send_icmp:
+		icmp_send(skb, ICMP_DEST_UNREACH, ICMP_FRAG_NEEDED, htonl(mtu));
+		return true;
+
+	case htons(ETH_P_IPV6):
+
+		/*
+		 * If the computed MTU is less than IPV6_MIN_MTU[1280]
+		 * proceed with post fragmentation
+		 */
+		if (unlikely(mtu < IPV6_MIN_MTU))
+			return false;
+
+		if (likely(skb_dst(skb)))
+			goto send_icmp6;
+
+		memset(&fl6, 0, sizeof(fl6));
+		memcpy(&fl6.daddr, &ipv6_hdr(skb)->saddr, sizeof(fl6.daddr));
+
+		dst = ip6_route_output(&init_net, NULL, &fl6);
+		if (IS_ERR(dst)) {
+			return false;
+		}
+
+		skb_dst_set(skb, dst);
+send_icmp6:
+		icmpv6_send(skb, ICMPV6_PKT_TOOBIG, 0, mtu);
+		return true;
+
+	default:
+		BUG_ON(true);
+	}
+
+	return true;
+}
+
+/*
+ * nss_ipsecmgr_flow_offload()
+ * 	check if the flow can be offloaded to NSS for encapsulation
+ */
+bool nss_ipsecmgr_flow_offload(struct nss_ipsecmgr_priv *priv, struct sk_buff *skb, struct nss_ipsecmgr_flow_data *data)
+{
+	struct nss_ipsecmgr_ref *subnet_ref, *flow_ref;
+	struct nss_ipsecmgr_key subnet_key, flow_key;
+	struct nss_ipsecmgr_flow_entry *flow;
+	struct nss_ipsec_tuple *tuple;
+	struct nss_ipsec_msg nim;
+
+	nss_ipsecmgr_encap_flow_init(&nim, NSS_IPSEC_MSG_TYPE_ADD_RULE, priv);
+
+	switch (skb->protocol) {
+	case htons(ETH_P_IP):
+		tuple = &nim.tuple;
+
+		nss_ipsecmgr_v4_hdr2tuple(ip_hdr(skb), tuple);
+		nss_ipsecmgr_encap_tuple2key(tuple, &flow_key);
+
+		/*
+		 * flow lookup is done with read lock
+		 */
+		read_lock_bh(&ipsecmgr_ctx->lock);
+
+		/*
+		 * if flow is found then proceed with the TX
+		 */
+		flow_ref = nss_ipsecmgr_flow_lookup(priv, &flow_key);
+		if (flow_ref) {
+			flow = container_of(flow_ref, struct nss_ipsecmgr_flow_entry, ref);
+			memcpy(data, &flow->data, sizeof(*data));
+			read_unlock_bh(&ipsecmgr_ctx->lock);
+			return true;
+		}
+
+		read_unlock_bh(&ipsecmgr_ctx->lock);
+
+		/*
+		 * flow table miss results in lookup in the subnet table. If,
+		 * a match is found then a rule is inserted in NSS for encapsulating
+		 * this flow.
+		 */
+		nss_ipsecmgr_v4_subnet_tuple2key(tuple, &subnet_key);
+
+		/*
+		 * write lock as it can update the flow database
+		 */
+		write_lock_bh(&ipsecmgr_ctx->lock);
+
+		subnet_ref = nss_ipsecmgr_v4_subnet_match(priv, &subnet_key);
+		if (!subnet_ref) {
+			write_unlock_bh(&ipsecmgr_ctx->lock);
+			return false;
+		}
+
+		/*
+		 * copy nim data from subnet entry
+		 */
+		nss_ipsecmgr_copy_subnet(&nim, subnet_ref);
+
+		/*
+		 * if, the same flow was added in between then flow alloc will return the
+		 * same flow. The only side affect of this will be NSS getting duplicate
+		 * add requests and thus rejecting one of them
+		 */
+		flow_ref = nss_ipsecmgr_flow_alloc(priv, &flow_key);
+		if (!flow_ref) {
+			write_unlock_bh(&ipsecmgr_ctx->lock);
+			return false;
+		}
+
+		/*
+		 * add reference to subnet and trigger an update
+		 */
+		nss_ipsecmgr_ref_add(flow_ref, subnet_ref);
+		nss_ipsecmgr_ref_update(priv, flow_ref, &nim);
+
+		flow = container_of(flow_ref, struct nss_ipsecmgr_flow_entry, ref);
+		memcpy(data, &flow->data, sizeof(*data));
+		write_unlock_bh(&ipsecmgr_ctx->lock);
+
+		break;
+
+	case htons(ETH_P_IPV6):
+		tuple = &nim.tuple;
+
+		nss_ipsecmgr_v6_hdr2tuple((struct ipv6hdr *)skb_network_header(skb), tuple);
+		nss_ipsecmgr_encap_tuple2key(tuple, &flow_key);
+
+		/*
+		 * flow lookup is done with read lock
+		 */
+		read_lock_bh(&ipsecmgr_ctx->lock);
+
+		/*
+		 * if flow is found then proceed with the TX
+		 */
+		flow_ref = nss_ipsecmgr_flow_lookup(priv, &flow_key);
+		if (flow_ref) {
+			flow = container_of(flow_ref, struct nss_ipsecmgr_flow_entry, ref);
+			memcpy(data, &flow->data, sizeof(*data));
+			read_unlock_bh(&ipsecmgr_ctx->lock);
+			return true;
+		}
+
+		read_unlock_bh(&ipsecmgr_ctx->lock);
+
+		/*
+		 * flow table miss results in lookup in the subnet table. If,
+		 * a match is found then a rule is inserted in NSS for encapsulating
+		 * this flow.
+		 */
+		nss_ipsecmgr_v6_subnet_tuple2key(tuple, &subnet_key);
+
+		/*
+		 * write lock as it can update the flow database
+		 */
+		write_lock(&ipsecmgr_ctx->lock);
+
+		subnet_ref = nss_ipsecmgr_v6_subnet_match(priv, &subnet_key);
+		if (!subnet_ref) {
+			write_unlock(&ipsecmgr_ctx->lock);
+			return false;
+		}
+
+		/*
+		 * copy nim data from subnet entry
+		 */
+		nss_ipsecmgr_copy_subnet(&nim, subnet_ref);
+
+		/*
+		 * if, the same flow was added in between then flow alloc will return the
+		 * same flow. The only side affect of this will be NSS getting duplicate
+		 * add requests and thus rejecting one of them
+		 */
+		flow_ref = nss_ipsecmgr_flow_alloc(priv, &flow_key);
+		if (!flow_ref) {
+			write_unlock(&ipsecmgr_ctx->lock);
+			return false;
+		}
+
+		/*
+		 * add reference to subnet and trigger an update
+		 */
+		nss_ipsecmgr_ref_add(flow_ref, subnet_ref);
+		nss_ipsecmgr_ref_update(priv, flow_ref, &nim);
+
+		flow = container_of(flow_ref, struct nss_ipsecmgr_flow_entry, ref);
+		memcpy(data, &flow->data, sizeof(*data));
+		write_unlock(&ipsecmgr_ctx->lock);
+		break;
+
+	default:
+		nss_ipsecmgr_warn("%px:protocol(%d) offload not supported\n", priv->dev, ntohs(skb->protocol));
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/ipsecmgr/v1.0/nss_ipsecmgr_priv.h b/qca-nss-clients/ipsecmgr/v1.0/nss_ipsecmgr_priv.h
new file mode 100644
index 0000000..4d1bc3d
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v1.0/nss_ipsecmgr_priv.h
@@ -0,0 +1,1194 @@
+/*
+ * ********************************************************************************
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ **********************************************************************************
+ */
+
+#ifndef __NSS_IPSECMGR_PRIV_H
+#define __NSS_IPSECMGR_PRIV_H
+
+#include <net/ipv6.h>
+#include <nss_api_if.h>
+#include <nss_ipsec.h>
+#include <nss_ipsecmgr.h>
+
+#define NSS_IPSECMGR_DEBUG_LVL_ERROR 1		/**< Turn on debug for an error. */
+#define NSS_IPSECMGR_DEBUG_LVL_WARN 2		/**< Turn on debug for a warning. */
+#define NSS_IPSECMGR_DEBUG_LVL_INFO 3		/**< Turn on debug for information. */
+#define NSS_IPSECMGR_DEBUG_LVL_TRACE 4		/**< Turn on debug for trace. */
+
+#define nss_ipsecmgr_info_always(s, ...) pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+#define nss_ipsecmgr_error(s, ...) do {	\
+	if (net_ratelimit()) {	\
+		pr_alert("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+} while (0)
+
+#define nss_ipsecmgr_warn(s, ...) do {	\
+	if (net_ratelimit()) {	\
+		pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+} while (0)
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_ipsecmgr_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_ipsecmgr_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+#else
+/*
+ * Statically compile messages at different levels
+ */
+#define nss_ipsecmgr_info(s, ...) {	\
+	if (NSS_IPSECMGR_DEBUG_LEVEL > NSS_IPSECMGR_DEBUG_LVL_INFO) {	\
+		pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+#define nss_ipsecmgr_trace(s, ...) {	\
+	if (NSS_IPSECMGR_DEBUG_LEVEL > NSS_IPSECMGR_DEBUG_LVL_TRACE) {	\
+		pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+
+#endif /* !CONFIG_DYNAMIC_DEBUG */
+#define NSS_IPSECMGR_MAX_KEY_NAME 64 /* bytes */
+#define NSS_IPSECMGR_MAX_KEY_WORDS 16 /* word */
+
+#define NSS_IPSECMGR_MAX_KEY_BYTES (NSS_IPSECMGR_MAX_KEY_WORDS * sizeof(uint32_t))
+#define NSS_IPSECMGR_MAX_KEY_BITS (NSS_IPSECMGR_MAX_KEY_WORDS * sizeof(uint32_t) * BITS_PER_BYTE)
+#define NSS_IPSECMGR_CHK_POW2(x) (__builtin_constant_p(x) && !(~(x - 1) & (x >> 1)))
+
+#define NSS_IPSECMGR_MAX_NAME (NSS_IPSECMGR_MAX_KEY_NAME + 64)
+
+#define NSS_IPSECMGR_MAX_SA NSS_CRYPTO_MAX_IDXS /* Max SAs */
+#if (~(NSS_IPSECMGR_MAX_SA - 1) & (NSS_IPSEC_MAX_SA >> 1))
+#error "NSS_IPSECMGR_MAX_SA is not a power of 2"
+#endif
+
+#define NSS_IPSECMGR_MAX_FLOW 256 /* Max flows */
+#if (~(NSS_IPSECMGR_MAX_FLOW - 1) & (NSS_IPSECMGR_MAX_FLOW >> 1))
+#error "NSS_IPSECMGR_MAX_FLOW is not a power of 2"
+#endif
+
+#define NSS_IPSECMGR_MAX_SUBNET 16 /* Max subnets */
+#if (~(NSS_IPSECMGR_MAX_SUBNET - 1) & (NSS_IPSECMGR_MAX_SUBNET >> 1))
+#error "NSS_IPSECMGR_MAX_SUBNET is not a power of 2"
+#endif
+
+#define NSS_IPSECMGR_MAX_NETMASK 128 /* Max subnets */
+#if (~(NSS_IPSECMGR_MAX_NETMASK - 1) & (NSS_IPSECMGR_MAX_NETMASK >> 1))
+#error "NSS_IPSECMGR_MAX_NETMASK is not a power of 2"
+#endif
+
+#define NSS_IPSECMGR_NETMASK_BITMAP BITS_TO_LONGS(NSS_IPSECMGR_MAX_NETMASK)
+
+#define NSS_IPSECMGR_GENMASK(hi, lo) ((~0 >> (31 - hi)) << lo)
+
+#define NSS_IPSECMGR_MAX_BUF_SZ 2048
+#define NSS_IPSECMGR_PROTO_NEXT_HDR_ANY 0xff
+
+#define NSS_IPSECMGR_V6_SUBNET_BITS (sizeof(uint32_t) * 2 * BITS_PER_BYTE)
+
+#define NSS_IPSECMGR_SA_STATS_SIZE 512
+#define NSS_IPSECMGR_SUBNET_STATS_SIZE 100
+
+#define NSS_IPSECMGR_MSG_SYNC_TIMEOUT_MSECS 2000
+#define NSS_IPSECMGR_MSG_SYNC_TIMEOUT_TICKS msecs_to_jiffies(NSS_IPSECMGR_MSG_SYNC_TIMEOUT_MSECS)
+
+#define NSS_IPSECMGR_PER_FLOW_STATS_SIZE 200
+#define NSS_IPSECMGR_PER_FLOW_BUF_SIZE 500
+#define NSS_IPSECMGR_PER_FLOW_BUF_SRC_IP_SIZE 100
+#define NSS_IPSECMGR_PER_FLOW_BUF_DST_IP_SIZE 100
+#define NSS_IPSECMGR_PER_FLOW_BUF_TYPE_SIZE 100
+
+#define NSS_IPSECMGR_BITS_PER_WORD (sizeof(uint32_t) * BITS_PER_BYTE)
+#define NSS_IPSECMGR_BITS2WORD(p) ((p) / NSS_IPSECMGR_BITS_PER_WORD)
+
+#define NSS_IPSECMGR_DEFAULT_TUN_NAME "ipsecdummy"
+
+#define NSS_IPSECMGR_ESP_TRAIL_SZ 2 /* esp trailer size */
+#define NSS_IPSECMGR_ESP_PAD_SZ 14 /* maximum amount of padding */
+
+struct nss_ipsecmgr_ref;
+struct nss_ipsecmgr_key;
+struct nss_ipsecmgr_priv;
+/*
+ * IPsec manager key length for
+ *  - SA entries
+ *  - Flow entries
+ *  - Subnet entries
+ */
+enum nss_ipsecmgr_key_len {
+	NSS_IPSECMGR_KEY_LEN_NONE = 0,
+	NSS_IPSECMGR_KEY_LEN_IPV4_SA = 4,		/* 16 bytes */
+	NSS_IPSECMGR_KEY_LEN_IPV4_SUBNET = 2,		/* 8 bytes */
+	NSS_IPSECMGR_KEY_LEN_IPV4_ENCAP_FLOW = 3,	/* 12 bytes */
+	NSS_IPSECMGR_KEY_LEN_IPV4_DECAP_FLOW = 4,	/* 16 bytes */
+	NSS_IPSECMGR_KEY_LEN_IPV6_SA = 10,		/* 40 bytes */
+	NSS_IPSECMGR_KEY_LEN_IPV6_SUBNET = 5,		/* 20 bytes */
+	NSS_IPSECMGR_KEY_LEN_IPV6_ENCAP_FLOW = 9,	/* 36 bytes */
+	NSS_IPSECMGR_KEY_LEN_IPV6_DECAP_FLOW = 10,	/* 40 bytes */
+	NSS_IPSECMGR_KEY_LEN_MAX = NSS_IPSECMGR_MAX_KEY_WORDS
+};
+
+/*
+ * IPsec manager key map for header fields to key elements
+ */
+enum nss_ipsecmgr_key_pos {
+	NSS_IPSECMGR_KEY_POS_IP_VER = 0,		/* IP version, bits[0:7] */
+	NSS_IPSECMGR_KEY_POS_IP_PROTO = 8,		/* IPv4 Proto, bits[8:15] */
+	NSS_IPSECMGR_KEY_POS_IPV4_DST = 32,		/* IPv4 DST, bits[32:63] */
+	NSS_IPSECMGR_KEY_POS_IPV4_SRC = 64,		/* IPv4 SIP, bits[64:95] */
+	NSS_IPSECMGR_KEY_POS_IPV4_ESP_SPI = 96,		/* IPv4 ESP SPI, bits[96:127] */
+	NSS_IPSECMGR_KEY_POS_IPV6_DST = 32,		/* IPv6 DST, bits[32:159] */
+	NSS_IPSECMGR_KEY_POS_IPV6_SRC = 160,	 	/* IPv6 SIP, bits[160:287] */
+	NSS_IPSECMGR_KEY_POS_IPV6_ESP_SPI = 288,	/* IPv6 ESP SPI, bits[288:319] */
+
+
+};
+
+/*
+ * bits to mask within a key_word data, min - 0 & max - 31
+ */
+enum nss_ipsecmgr_key_mask {
+	NSS_IPSECMGR_KEY_MASK_IP_VER = NSS_IPSECMGR_GENMASK(7, 0),	/* IP version, #bits - 8 */
+	NSS_IPSECMGR_KEY_MASK_IP_PROTO = NSS_IPSECMGR_GENMASK(15, 8),	/* IP protocol, #bits - 8 */
+	NSS_IPSECMGR_KEY_MASK_IPV4_DST = NSS_IPSECMGR_GENMASK(31, 0),	/* IPv4 dst, #bits - 32 */
+	NSS_IPSECMGR_KEY_MASK_IPV4_SRC = NSS_IPSECMGR_GENMASK(31, 0),	/* IPv4 src, #bits - 32 */
+	NSS_IPSECMGR_KEY_MASK_ESP_SPI = NSS_IPSECMGR_GENMASK(31, 0),	/* ESP spi #bits - 32 */
+};
+
+struct nss_ipsecmgr_ref;
+struct nss_ipsecmgr_key;
+struct nss_ipsecmgr_priv;
+
+typedef void (*nss_ipsecmgr_ref_update_t)(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_ref *ref, struct nss_ipsec_msg *nim);
+typedef void (*nss_ipsecmgr_ref_free_t)(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_ref *ref);
+typedef uint32_t (*nss_ipsecmgr_ref_overhead_t)(struct nss_ipsecmgr_ref *ref);
+
+/*
+ * Key byte stream for lookup
+ */
+struct nss_ipsecmgr_key {
+	uint32_t data[NSS_IPSECMGR_MAX_KEY_WORDS];	/* Value N-bits */
+	uint32_t mask[NSS_IPSECMGR_MAX_KEY_WORDS];	/* Mask N-bits */
+	uint32_t len;					/* Length of the key */
+};
+
+/*
+ * IPsec manager reference object
+ */
+struct nss_ipsecmgr_ref {
+	struct list_head head;			/* parent "ref" */
+	struct list_head node;			/* child "ref" */
+
+	uint32_t id;				/* identifier */
+	struct nss_ipsecmgr_ref *parent;	/* reference to parent */
+
+	nss_ipsecmgr_ref_update_t update;	/* update function */
+	nss_ipsecmgr_ref_free_t free;		/* free function */
+	nss_ipsecmgr_ref_overhead_t overhead;	/* free function */
+};
+
+/*
+ * IPsec manager packets stats per SA
+ */
+struct nss_ipsecmgr_sa_pkt_stats {
+	uint64_t count;
+	uint64_t bytes;
+
+	uint64_t seq_num;
+	uint64_t window_max;
+	uint32_t window_size;
+
+	uint32_t no_headroom;
+	uint32_t no_tailroom;
+	uint32_t no_buf;
+	uint32_t fail_queue;
+	uint32_t fail_hash;
+	uint32_t fail_replay;
+	uint32_t fail_hash_cont;		/* Continous fail hash count */
+};
+
+/*
+ * IPsec manager node stats
+ */
+struct nss_ipsecmgr_node_stats {
+	uint64_t enqueued;		/* packets enqueued to the node */
+	uint64_t completed;		/* packets processed by the node */
+	uint64_t linearized;		/* linearized the packet */
+	uint64_t exceptioned;		/* packets exception from NSS */
+	uint64_t fail_enqueue;		/* packets failed to enqueue */
+};
+
+/*
+ * IPsec manager SA entry
+ */
+struct nss_ipsecmgr_sa_entry {
+	struct list_head node;			/* list instance */
+
+	struct nss_ipsecmgr_ref ref;		/* ref instance */
+	struct nss_ipsecmgr_key key;		/* key instance */
+
+	uint32_t ifnum;				/* SA interface */
+	uint32_t sa_overhead;			/* max header + trailer added for SA */
+	bool esn_enabled;			/* Is ESN enabled */
+
+	struct nss_ipsecmgr_sa_pkt_stats pkts;	/* packets processed per SA */
+	struct nss_ipsecmgr_priv *priv;		/* ipsecmgr private reference */
+	struct nss_ipsec_msg nim;		/* ipsec message */
+	struct nss_ipsecmgr_sa sa_info;		/* SA information */
+
+	uint32_t fail_hash_thresh;		/* continous hash fail
+						   threshold */
+};
+
+/*
+ * IPsec manager SA entry table
+ */
+struct nss_ipsecmgr_sa_db {
+	atomic_t num_entries;			/* active entries in the entity */
+
+	struct list_head entries[NSS_IPSECMGR_MAX_SA];
+};
+
+/*
+ * IPsec manager subnet entry
+ */
+struct nss_ipsecmgr_subnet_entry {
+	struct list_head node;			/* list node */
+	struct nss_ipsecmgr_ref ref;		/* reference node */
+	struct nss_ipsecmgr_key key;		/* key */
+
+	struct nss_ipsec_msg nim;		/* IPsec message */
+	struct nss_ipsecmgr_priv *priv;		/* ipsecmgr private reference */
+};
+
+/*
+ * IPsec netmask entry
+ */
+struct nss_ipsecmgr_netmask_entry {
+	uint32_t mask_bits;					/* no. of bits in netmask */
+	uint32_t count;						/* no. of subnets entries */
+	struct list_head subnets[NSS_IPSECMGR_MAX_SUBNET];	/* subnet database */
+};
+
+/*
+ * IPsec netmask database
+ *
+ * Note: this database is searched using bit positions present in bitmap
+ * where each bit in bitmap table represents a entry in the mask entry
+ * table
+ */
+struct nss_ipsecmgr_netmask_db {
+	atomic_t num_entries;							/* active entries in the entity */
+	unsigned long bitmap[NSS_IPSECMGR_NETMASK_BITMAP];			/* netmask bitmap */
+	struct nss_ipsecmgr_netmask_entry *entries[NSS_IPSECMGR_MAX_NETMASK];	/* netmask entry database */
+	struct nss_ipsecmgr_netmask_entry *default_entry;			/* default netmask */
+};
+
+/*
+ * IPsec manager flow data
+ */
+struct nss_ipsecmgr_flow_data {
+	uint32_t pkts_processed;	/* packets processed for this flow */
+	uint32_t sa_overhead;		/* max header + trailer added for SA */
+};
+
+/*
+ * IPsec manager flow entry
+ */
+struct nss_ipsecmgr_flow_entry {
+	struct list_head node;			/* list object */
+	struct nss_ipsecmgr_ref ref;		/* reference object */
+	struct nss_ipsecmgr_key key;		/* key object */
+
+	struct nss_ipsecmgr_priv *priv;		/* ipsecmgr private reference */
+	struct nss_ipsec_msg nim;		/* IPsec message */
+	struct nss_ipsecmgr_flow_data data;	/* Flow data */
+};
+
+/*
+ * Flow retry
+ */
+struct nss_ipsecmgr_flow_retry {
+	struct list_head node;			/* retry list node */
+	struct nss_ipsecmgr_key key;		/* flow key for lookup */
+	uint32_t ref_id;			/* refernce object id */
+};
+
+/*
+ * IPsec manager flow database
+ */
+struct nss_ipsecmgr_flow_db {
+	atomic_t num_entries;					/* active entries in the entity */
+	struct list_head entries[NSS_IPSECMGR_MAX_FLOW];	/* flow database */
+};
+
+/*
+ * IPsec manager callback database
+ */
+struct nss_ipsecmgr_callback_db {
+	atomic_t num_entries;			/* number of callback(s) registered */
+	struct list_head entries;		/* head of the first callback */
+};
+
+/*
+ * IPsec manager callback entry
+ */
+struct nss_ipsecmgr_callback_entry {
+	struct list_head node;			/* list node */
+	int dev_index;				/* device bound for callback */
+	void *app_data;				/* callback context */
+	nss_ipsecmgr_data_cb_t data;		/* data callback function */
+	nss_ipsecmgr_event_cb_t event;		/* event callback function */
+};
+
+/*
+ * IPsec manager private context
+ */
+struct nss_ipsecmgr_priv {
+	struct net_device *dev;			/* back pointer to tunnel device */
+	struct nss_ipsecmgr_callback_entry cb;	/* callback entry instance */
+	atomic_t outer_dst_mtu;			/* PMTU of outer tunnel DST */
+	struct rtnl_link_stats64 stats;		/* stats of IPsec tunnel */
+};
+
+/*
+ * IPsec manager drv instance
+ */
+struct nss_ipsecmgr_drv {
+	struct dentry *dentry;			/* Debugfs entry per ipsecmgr module. */
+	struct dentry *stats_dentry;		/* Debugfs entry per stats dir */
+	struct net_device *ndev;		/* IPsec dummy net device */
+
+	rwlock_t lock;				/* lock for all DB operations */
+
+	struct nss_ipsecmgr_sa_db sa_db;	/* SA database */
+	struct nss_ipsecmgr_netmask_db net_db;	/* Subnet mask database */
+	struct nss_ipsecmgr_flow_db flow_db;	/* flow database */
+	struct nss_ipsecmgr_callback_db cb_db;	/* callback database */
+	struct completion complete;		/* completion for flow stats nss msg */
+
+	int encap_ifnum;			/* NSS encap interface */
+	int decap_ifnum;			/* NSS decap interface */
+	int data_ifnum;			/* NSS data interface */
+
+	struct nss_ctx_instance *nss_ctx;	/* NSS context */
+
+	struct nss_ipsec_msg resp_nim;		/* nim for per_flow stats */
+	struct semaphore sem;			/* per flow semaphore lock */
+	atomic_t seq_num;			/* per flow seq no */
+
+	struct nss_ipsecmgr_node_stats enc_stats;	/* Encap node stats */
+	struct nss_ipsecmgr_node_stats dec_stats;	/* Decap node stats */
+};
+
+/*
+ * nss_ipsecmgr_ref_is_updated()
+ * 	return true if reference objects id is updated
+ */
+static inline bool nss_ipsecmgr_ref_is_updated(struct nss_ipsecmgr_ref *ref)
+{
+	return ref->id > 1;
+}
+
+/*
+ * nss_ipsecmgr_ref_get_id()
+ * 	return the reference object's id
+ */
+static inline uint32_t nss_ipsecmgr_ref_get_id(struct nss_ipsecmgr_ref *ref)
+{
+	return ref->id;
+}
+
+/*
+ * nss_ipsecmgr_ref_is_empty()
+ * 	check if the SA has any reference
+ */
+static inline bool nss_ipsecmgr_ref_is_empty(struct nss_ipsecmgr_ref *ref)
+{
+	return list_empty(&ref->head);
+}
+
+/*
+ * nss_ipsecmgr_key_reset()
+ * 	Reset the IPsec key
+ */
+static inline void nss_ipsecmgr_key_reset(struct nss_ipsecmgr_key *key)
+{
+	memset(key, 0, sizeof(struct nss_ipsecmgr_key));
+}
+
+/*
+ * nss_ipsecmgr_key_read_8()
+ * 	read value & mask from the specified position
+ */
+static inline uint8_t nss_ipsecmgr_key_read_8(struct nss_ipsecmgr_key *key, enum nss_ipsecmgr_key_pos p)
+{
+	uint32_t data;
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+	data = key->data[idx];
+
+	switch (p % NSS_IPSECMGR_BITS_PER_WORD) {
+	case 0: /* bits[0:7] */
+		return (uint8_t)data;
+	case 8: /* bits[8:15] */
+		return (uint8_t)(data >> 8);
+	case 16: /* bits[16:23] */
+		return (uint8_t)(data >> 16);
+	case 24: /* bits[24:31] */
+		return (uint8_t)(data >> 24);
+	default:
+		return 0;
+	}
+}
+
+/*
+ * nss_ipsecmgr_key_write_8()
+ * 	write 8-bit value from the specified position using mask
+ */
+static inline void nss_ipsecmgr_key_write_8(struct nss_ipsecmgr_key *key, uint8_t v, enum nss_ipsecmgr_key_pos p)
+{
+	uint32_t *data, *mask;
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+	data = &key->data[idx];
+	mask = &key->mask[idx];
+
+	/*
+	 * clear data with mask, update data & save mask
+	 */
+	switch (p % NSS_IPSECMGR_BITS_PER_WORD) {
+	case 0: /* bits[0:7] */
+		*data &= ~NSS_IPSECMGR_GENMASK(7, 0);
+		*data |= v;
+		*mask |= NSS_IPSECMGR_GENMASK(7, 0);
+		break;
+	case 8: /* bits[8:15] */
+		*data &= ~NSS_IPSECMGR_GENMASK(15, 8);
+		*data |= (v << 8);
+		*mask |= NSS_IPSECMGR_GENMASK(15, 8);
+		break;
+	case 16: /* bits[16:23] */
+		*data &= ~NSS_IPSECMGR_GENMASK(23, 16);
+		*data |= (v << 16);
+		*mask |= NSS_IPSECMGR_GENMASK(23, 16);
+		break;
+	case 24: /* bits[24:31] */
+		*data &= ~NSS_IPSECMGR_GENMASK(31, 24);
+		*data |= (v << 24);
+		*mask |= NSS_IPSECMGR_GENMASK(31, 24);
+		break;
+	default:
+		*data = 0;
+		*mask = 0;
+		break;
+	}
+}
+
+/*
+ * nss_ipsecmgr_key_clear_8()
+ * 	clear 8-bit mask from the specified position.
+ */
+static inline void nss_ipsecmgr_key_clear_8(struct nss_ipsecmgr_key *key, enum nss_ipsecmgr_key_pos p)
+{
+	uint32_t *mask;
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+	mask = &key->mask[idx];
+
+	/*
+	 * clear data with mask, update data & save mask
+	 */
+	switch (p % NSS_IPSECMGR_BITS_PER_WORD) {
+	case 0: /* bits[0:7] */
+		*mask &= ~NSS_IPSECMGR_GENMASK(7, 0);
+		break;
+	case 8: /* bits[8:15] */
+		*mask &= ~NSS_IPSECMGR_GENMASK(15, 8);
+		break;
+	case 16: /* bits[16:23] */
+		*mask &= ~NSS_IPSECMGR_GENMASK(23, 16);
+		break;
+	case 24: /* bits[24:31] */
+		*mask &= ~NSS_IPSECMGR_GENMASK(31, 24);
+		break;
+	default:
+		*mask = 0;
+		break;
+	}
+}
+
+/*
+ * nss_ipsecmgr_key_read_16()
+ * 	read value & mask from the specified position using mask
+ */
+static inline uint16_t nss_ipsecmgr_key_read_16(struct nss_ipsecmgr_key *key, enum nss_ipsecmgr_key_pos p)
+{
+	uint32_t data;
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+	data = key->data[idx];
+
+	switch (p % NSS_IPSECMGR_BITS_PER_WORD) {
+	case 0: /* bits[0:7] */
+		return (uint16_t)data;
+	case 16: /* bits[16:23] */
+		return (uint16_t)(data >> 16);
+	default:
+		return 0;
+	}
+}
+
+/*
+ * nss_ipsecmgr_key_write_16()
+ * 	write 16-bit value from the specified position using mask
+ */
+static inline void nss_ipsecmgr_key_write_16(struct nss_ipsecmgr_key *key, uint16_t v, enum nss_ipsecmgr_key_pos p)
+{
+	uint32_t *data, *mask;
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+	data = &key->data[idx];
+	mask = &key->mask[idx];
+
+	/*
+	 * clear data with mask, update data & save mask
+	 */
+	switch (p % NSS_IPSECMGR_BITS_PER_WORD) {
+	case 0: /* bits[0:15] */
+		*data &= ~NSS_IPSECMGR_GENMASK(15, 0);
+		*data |= v;
+		*mask |= NSS_IPSECMGR_GENMASK(15, 0);
+		break;
+	case 16: /* bits[16:31] */
+		*data &= ~NSS_IPSECMGR_GENMASK(31, 16);
+		*data |= (v << 16);
+		*mask |= NSS_IPSECMGR_GENMASK(31, 16);
+		break;
+	default:
+		*data = 0;
+		*mask = 0;
+		break;
+	}
+}
+
+/*
+ * nss_ipsecmgr_key_clear_16()
+ * 	clear 16-bit mask from the specified position
+ */
+static inline void nss_ipsecmgr_key_clear_16(struct nss_ipsecmgr_key *key, enum nss_ipsecmgr_key_pos p)
+{
+	uint32_t *mask;
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+	mask = &key->mask[idx];
+
+	/*
+	 * clear data with mask, update data & save mask
+	 */
+	switch (p % NSS_IPSECMGR_BITS_PER_WORD) {
+	case 0: /* bits[0:15] */
+		*mask &= ~NSS_IPSECMGR_GENMASK(15, 0);
+		break;
+	case 16: /* bits[16:31] */
+		*mask &= ~NSS_IPSECMGR_GENMASK(31, 16);
+		break;
+	default:
+		*mask = 0;
+		break;
+	}
+}
+
+/*
+ * nss_ipsecmgr_key_read_32()
+ * 	read value from the specified position using mask
+ */
+static inline uint32_t nss_ipsecmgr_key_read_32(struct nss_ipsecmgr_key *key, enum nss_ipsecmgr_key_pos p)
+{
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+	return key->data[idx];
+}
+
+/*
+ * nss_ipsecmgr_key_write_32()
+ * 	write 32-bit value from the specified position using mask
+ */
+static inline void nss_ipsecmgr_key_write_32(struct nss_ipsecmgr_key *key, uint32_t v, enum nss_ipsecmgr_key_pos p)
+{
+	uint32_t *data, *mask;
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+	data = &key->data[idx];
+	mask = &key->mask[idx];
+
+	/*
+	 * save data & mask, bits[0:31]
+	 */
+	*data = v;
+	*mask = NSS_IPSECMGR_GENMASK(31, 0);
+}
+
+/*
+ * nss_ipsecmgr_key_clear_32()
+ * 	clear 32-bit mask from the specified position
+ */
+static inline void nss_ipsecmgr_key_clear_32(struct nss_ipsecmgr_key *key, enum nss_ipsecmgr_key_pos p)
+{
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+	key->mask[idx] = 0;
+}
+
+/*
+ * nss_ipsecmgr_key_clear_64()
+ * 	clear 64-bit mask from the specified position
+ */
+static inline void nss_ipsecmgr_key_clear_64(struct nss_ipsecmgr_key *key, enum nss_ipsecmgr_key_pos p)
+{
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+	key->mask[idx] = 0;
+	key->mask[idx + 1] = 0;
+}
+
+/*
+ * nss_ipsecmgr_key_clear_128()
+ * 	clear 128-bit mask from the specified position
+ */
+static inline void nss_ipsecmgr_key_clear_128(struct nss_ipsecmgr_key *key, enum nss_ipsecmgr_key_pos p)
+{
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+
+	memset(&key->mask[idx], 0, sizeof(uint32_t) * 4);
+}
+
+/*
+ * nss_ipsecmgr_key_read_n()
+ * 	read n nnumber of values from the specified position using mask
+ */
+static inline void nss_ipsecmgr_key_read(struct nss_ipsecmgr_key *key, uint32_t *v, uint32_t *m, enum nss_ipsecmgr_key_pos p, uint32_t n)
+{
+	uint32_t *k_data, *k_mask;
+	uint16_t idx;
+	int delta;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+	delta = NSS_IPSECMGR_MAX_KEY_WORDS - idx;
+
+	n = n > delta ? delta : n;
+
+	k_data = &key->data[idx];
+	k_mask = &key->mask[idx];
+
+	for (; n--;) {
+		*v++ = *k_data++;
+		*m++ = *k_mask++;
+	}
+}
+
+/*
+ * nss_ipsecmgr_key_write()
+ * 	write value from the specified position using mask
+ */
+static inline void nss_ipsecmgr_key_write(struct nss_ipsecmgr_key *key, uint32_t *v, uint32_t *m, enum nss_ipsecmgr_key_pos p, uint32_t n)
+{
+	uint32_t *k_data, *k_mask;
+	uint16_t idx;
+	int delta;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+	delta = NSS_IPSECMGR_MAX_KEY_WORDS - idx;
+
+	n = n > delta ? delta : n;
+
+	k_data = &key->data[idx];
+	k_mask = &key->mask[idx];
+
+	for (; n--;) {
+		*k_data++ = *v++;
+		*k_mask++ = *m++;
+	}
+}
+
+/*
+ * nss_ipsecmgr_write_key_mask()
+ * 	write a mask starting from position
+ */
+static inline void nss_ipsecmgr_key_write_mask(struct nss_ipsecmgr_key *key, uint32_t m, enum nss_ipsecmgr_key_pos p)
+{
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+	key->mask[idx] = m;
+}
+
+/*
+ * nss_ipsecmgr_read_key_mask32()
+ * 	read a 32 bit mask starting from position
+ */
+static inline uint32_t nss_ipsecmgr_key_read_mask32(struct nss_ipsecmgr_key *key, enum nss_ipsecmgr_key_pos p)
+{
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+
+	return key->mask[idx];
+}
+
+/*
+ * nss_ipsecmgr_read_key_mask64()
+ * 	read a 64 bit mask starting from position
+ */
+static inline uint64_t nss_ipsecmgr_key_read_mask64(struct nss_ipsecmgr_key *key, enum nss_ipsecmgr_key_pos p)
+{
+	uint64_t *mask;
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+
+	mask = (uint64_t *)&key->mask[idx];
+
+	return *mask;
+}
+
+/*
+ * nss_ipsecmgr_key_lshift_mask()
+ * 	left shift mask by an amount 's'
+ */
+static inline void nss_ipsecmgr_key_lshift_mask(struct nss_ipsecmgr_key *key, uint32_t s, enum nss_ipsecmgr_key_pos p)
+{
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+	key->mask[idx] <<= s;
+}
+
+/*
+ * nss_ipsecmgr_key_lshift_mask64()
+ * 	left shift mask by an amount 's'
+ */
+static inline void nss_ipsecmgr_key_lshift_mask64(struct nss_ipsecmgr_key *key, uint32_t s, enum nss_ipsecmgr_key_pos p)
+{
+	uint64_t *mask;
+	uint16_t idx;
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+
+	mask = (uint64_t *)&key->mask[idx];
+	*mask <<= s;
+}
+
+/*
+ * nss_ipsecmgr_key_lshift_mask128()
+ * 	left shift mask by an amount 's'
+ */
+static inline void nss_ipsecmgr_key_lshift_mask128(struct nss_ipsecmgr_key *key, uint32_t s, enum nss_ipsecmgr_key_pos p)
+{
+	uint16_t idx;
+	uint32_t mask[4];
+
+	idx = NSS_IPSECMGR_BITS2WORD(p) % NSS_IPSECMGR_MAX_KEY_WORDS;
+
+	memcpy(mask, &key->mask[idx], sizeof(uint32_t) * 4);
+
+	bitmap_shift_left((unsigned long *)&key->mask[idx], (unsigned long *)mask, s, 128);
+}
+
+/*
+ * nss_ipsecmgr_key_cmp_data()
+ * 	compare source key with destination key
+ *
+ * Note: this applies the source mask before comparison
+ */
+static inline bool nss_ipsecmgr_key_cmp(struct nss_ipsecmgr_key *s_key, struct nss_ipsecmgr_key *d_key)
+{
+	uint32_t *mask = s_key->mask;
+	uint32_t *src = s_key->data;
+	uint32_t *dst = d_key->data;
+	int len = s_key->len;
+	uint32_t val_0;
+	uint32_t val_1;
+	bool status;
+
+	for (status = 0; !status && len; len--, mask++, src++, dst++) {
+		/*
+		 * the data for comparison should be used after
+		 * masking the bits corresponding to that word
+		 */
+		val_0 = *src & *mask;
+		val_1 = *dst & *mask;
+
+		status |= val_0 ^ val_1;
+	}
+
+	return status == 0;
+}
+
+/*
+ * nss_ipsecmgr_key_data2idx()
+ * 	convert word stream to index based on table size
+ */
+static inline uint32_t nss_ipsecmgr_key_data2idx(struct nss_ipsecmgr_key *key, const uint32_t table_sz)
+{
+	uint32_t *data = key->data;
+	uint32_t *mask = key->mask;
+	uint32_t len = key->len;
+	uint32_t idx;
+	uint32_t val;
+
+	/*
+	 * bug on if table_sz is not
+	 * - a constant
+	 * - and a power of 2
+	 */
+	BUG_ON(!NSS_IPSECMGR_CHK_POW2(table_sz));
+
+	for (idx = 0; len; len--, mask++, data++) {
+		val = *data & *mask;
+		idx ^= val;
+	}
+
+	return idx & (table_sz - 1);
+}
+
+/*
+ * nss_ipsecmgr_init_sa_db()
+ * 	initialize the SA database
+ */
+static inline void nss_ipsecmgr_init_sa_db(struct nss_ipsecmgr_sa_db *sa_db)
+{
+	struct list_head *head;
+	int i;
+
+	/*
+	 * initialize the SA database
+	 */
+	head = sa_db->entries;
+	for (i = 0; i < NSS_IPSECMGR_MAX_SA; i++, head++) {
+		INIT_LIST_HEAD(head);
+	}
+
+	atomic_set(&sa_db->num_entries, 0);
+}
+
+/*
+ * nss_ipsecmgr_init_netmask_db()
+ * 	initialize the netmask database
+ */
+static inline void nss_ipsecmgr_init_netmask_db(struct nss_ipsecmgr_netmask_db *net_db)
+{
+	memset(net_db, 0, sizeof(struct nss_ipsecmgr_netmask_db));
+
+	atomic_set(&net_db->num_entries, 0);
+}
+
+/*
+ * nss_ipsecmgr_init_subnet_db()
+ * 	initialize the subnet database
+ */
+static inline void nss_ipsecmgr_init_subnet_db(struct nss_ipsecmgr_netmask_entry *netmask)
+{
+	struct list_head *head;
+	int i;
+
+	/*
+	 * initialize the subnet database
+	 */
+	head = netmask->subnets;
+	for (i = 0; i < NSS_IPSECMGR_MAX_SUBNET; i++, head++) {
+		INIT_LIST_HEAD(head);
+	}
+}
+
+/*
+ * nss_ipsecmgr_init_flow_db()
+ *	Initialize the flow databases
+ */
+static inline void nss_ipsecmgr_init_flow_db(struct nss_ipsecmgr_flow_db *flow_db)
+{
+	struct list_head *head;
+	int i;
+
+	/*
+	 * initialize the flow database
+	 */
+	head = flow_db->entries;
+	for (i = 0; i < NSS_IPSECMGR_MAX_FLOW; i++, head++) {
+		INIT_LIST_HEAD(head);
+	}
+
+	atomic_set(&flow_db->num_entries, 0);
+}
+
+/*
+ * nss_ipsecmgr_init_callback_db()
+ * 	initialize the callback database
+ */
+static inline void nss_ipsecmgr_init_callback_db(struct nss_ipsecmgr_callback_db *cb_db)
+{
+	INIT_LIST_HEAD(&cb_db->entries);
+	atomic_set(&cb_db->num_entries, 0);
+}
+
+/*
+ * nss_ipsecmgr_v4_hdr2tuple()
+ * 	convert v4_hdr to message tuple
+ */
+static inline void nss_ipsecmgr_v4_hdr2tuple(struct iphdr *iph, struct nss_ipsec_tuple *tuple)
+{
+	tuple->dst_addr[0] = ntohl(iph->daddr);
+	tuple->src_addr[0] = ntohl(iph->saddr);
+	tuple->proto_next_hdr = iph->protocol;
+	tuple->ip_ver = IPVERSION;
+}
+
+/*
+ * nss_ipsecmgr_v6addr_swap()
+ * 	Swap the words in the array.
+ */
+static uint32_t *nss_ipsecmgr_v6addr_swap(uint32_t *src, uint32_t *dst)
+{
+	uint32_t temp[4];
+
+	if (src == dst) {
+		memcpy(temp, src, sizeof(temp));
+		src = temp;
+	}
+
+	dst[3] = src[0];
+	dst[2] = src[1];
+	dst[1] = src[2];
+	dst[0] = src[3];
+
+	return dst;
+}
+
+/*
+ * nss_ipsecmgr_v6addr_ntoh()
+ * 	convert the v6 address form network to host order.
+ */
+static inline uint32_t *nss_ipsecmgr_v6addr_ntoh(uint32_t *src, uint32_t *dst)
+{
+	uint32_t *dst_addr = nss_ipsecmgr_v6addr_swap(src, dst);
+
+	dst_addr[0] = ntohl(dst_addr[0]);
+	dst_addr[1] = ntohl(dst_addr[1]);
+	dst_addr[2] = ntohl(dst_addr[2]);
+	dst_addr[3] = ntohl(dst_addr[3]);
+
+	return dst_addr;
+}
+
+/*
+ * nss_ipsecmgr_v6addr_hton()
+ * 	convert the v6 address to host to network order.
+ */
+static inline uint32_t *nss_ipsecmgr_v6addr_hton(uint32_t *src, uint32_t *dst)
+{
+	uint32_t *dst_addr = nss_ipsecmgr_v6addr_swap(src, dst);
+
+	dst_addr[0] = htonl(dst_addr[0]);
+	dst_addr[1] = htonl(dst_addr[1]);
+	dst_addr[2] = htonl(dst_addr[2]);
+	dst_addr[3] = htonl(dst_addr[3]);
+
+	return dst_addr;
+}
+
+/*
+ * nss_ipsecmgr_copy_nim()
+ * 	copy nim from source to destination, also swap the v6 addresses if any
+ */
+static inline void nss_ipsecmgr_copy_nim(struct nss_ipsec_msg *src_nim, struct nss_ipsec_msg *dst_nim)
+{
+	struct nss_ipsec_rule *src_rule = &src_nim->msg.rule;
+	struct nss_ipsec_rule *dst_rule = &dst_nim->msg.rule;
+
+	memcpy(dst_nim, src_nim, sizeof(struct nss_ipsec_msg));
+
+	if (src_nim->tuple.ip_ver == 6) {
+		nss_ipsecmgr_v6addr_swap(src_nim->tuple.dst_addr, dst_nim->tuple.dst_addr);
+		nss_ipsecmgr_v6addr_swap(src_nim->tuple.src_addr, dst_nim->tuple.src_addr);
+	}
+
+	if (src_rule->oip.ip_ver == 6) {
+		nss_ipsecmgr_v6addr_swap(src_rule->oip.dst_addr, dst_rule->oip.dst_addr);
+		nss_ipsecmgr_v6addr_swap(src_rule->oip.src_addr, dst_rule->oip.src_addr);
+	}
+}
+
+/*
+ * nss_ipsecmgr_v6_hdr2tuple()
+ * 	convert v6_hdr to message tuple
+ */
+static inline void nss_ipsecmgr_v6_hdr2tuple(struct ipv6hdr *iph, struct nss_ipsec_tuple *tuple)
+{
+	uint8_t nexthdr = iph->nexthdr;
+	struct frag_hdr *frag;
+
+	/*
+	 * NSS IPsec module will not accelerate the flows which has ipv6 optional
+	 * headers after frag_hdr. Those flows will be descarded in ipsecmgr.
+	 * The NSS only accelerates when IP next header is L4 or fragment next header is L4.
+	 */
+	if (nexthdr == IPPROTO_FRAGMENT) {
+		frag = (struct frag_hdr *)((uint8_t *)iph + sizeof(struct ipv6hdr));
+		nexthdr = frag->nexthdr;
+	}
+
+	nss_ipsecmgr_v6addr_ntoh(iph->daddr.s6_addr32, tuple->dst_addr);
+	nss_ipsecmgr_v6addr_ntoh(iph->saddr.s6_addr32, tuple->src_addr);
+
+	tuple->proto_next_hdr = nexthdr;
+	tuple->ip_ver = 6;
+}
+
+/*
+ * nss_ipsecmgr_get_ipv4_addr()
+ * 	Return ipv4 part of the address.
+ */
+static inline uint32_t nss_ipsecmgr_get_v4addr(uint32_t *addr)
+{
+	return addr[0];
+}
+
+/*
+ * nss_ipsecmgr_verify_v4_subnet()
+ * 	verify if v4 subnet mask is not empty when v4 subnet is empty.
+ */
+static inline bool nss_ipsecmgr_verify_v4_subnet(struct nss_ipsecmgr_encap_v4_subnet *v4_subnet)
+{
+	return !v4_subnet->dst_subnet && v4_subnet->dst_mask;
+}
+
+/*
+ * nss_ipsecmgr_verify_v6_subnet()
+ * 	verify if v6 subnet mask is not empty when v6 subnet is empty.
+ */
+static inline bool nss_ipsecmgr_verify_v6_subnet(struct nss_ipsecmgr_encap_v6_subnet *v6_subnet)
+{
+	bool subnet, mask;
+
+	subnet = bitmap_empty((unsigned long *)v6_subnet->dst_subnet, NSS_IPSECMGR_V6_SUBNET_BITS);
+	mask = bitmap_empty((unsigned long *)v6_subnet->dst_mask, NSS_IPSECMGR_V6_SUBNET_BITS);
+
+	return subnet && !mask;
+}
+
+/*
+ * Reference Object API(s)
+ */
+void nss_ipsecmgr_ref_init(struct nss_ipsecmgr_ref *ref, nss_ipsecmgr_ref_update_t update, nss_ipsecmgr_ref_free_t free);
+void nss_ipsecmgr_ref_add(struct nss_ipsecmgr_ref *child, struct nss_ipsecmgr_ref *parent);
+void nss_ipsecmgr_ref_free(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_ref *ref);
+void nss_ipsecmgr_ref_update(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_ref *ref, struct nss_ipsec_msg *nim);
+bool nss_ipsecmgr_ref_is_child(struct nss_ipsecmgr_ref *child, struct nss_ipsecmgr_ref *parent);
+void nss_ipsecmgr_ref_set_overhead(struct nss_ipsecmgr_ref *ref,
+		nss_ipsecmgr_ref_overhead_t overhead);
+uint32_t nss_ipsecmgr_ref_overhead(struct nss_ipsecmgr_ref *ref);
+
+/*
+ * Encap flow API(s)
+ */
+void nss_ipsecmgr_copy_encap_v4_flow(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_encap_v4_tuple *flow);
+void nss_ipsecmgr_copy_encap_v6_flow(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_encap_v6_tuple *flow);
+void nss_ipsecmgr_encap_v4_flow2key(struct nss_ipsecmgr_encap_v4_tuple *flow, struct nss_ipsecmgr_key *key);
+void nss_ipsecmgr_encap_v6_flow2key(struct nss_ipsecmgr_encap_v6_tuple *flow, struct nss_ipsecmgr_key *key);
+void nss_ipsecmgr_encap_tuple2key(struct nss_ipsec_tuple *tuple, struct nss_ipsecmgr_key *key);
+void nss_ipsecmgr_encap_flow_init(struct nss_ipsec_msg *nim, enum nss_ipsec_msg_type type, struct nss_ipsecmgr_priv *priv);
+
+/*
+ * Decap flow API(s)
+ */
+void nss_ipsecmgr_copy_decap_v4_flow(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_sa_v4 *flow);
+void nss_ipsecmgr_copy_decap_v6_flow(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_sa_v6 *flow);
+void nss_ipsecmgr_decap_v4_flow2key(struct nss_ipsecmgr_sa_v4 *flow, struct nss_ipsecmgr_key *key);
+void nss_ipsecmgr_decap_v6_flow2key(struct nss_ipsecmgr_sa_v6 *flow, struct nss_ipsecmgr_key *key);
+void nss_ipsecmgr_decap_tuple2key(struct nss_ipsec_tuple *tuple, struct nss_ipsecmgr_key *key);
+void nss_ipsecmgr_decap_flow_init(struct nss_ipsec_msg *nim, enum nss_ipsec_msg_type type, struct nss_ipsecmgr_priv *priv);
+
+/*
+ * flow alloc/lookup API(s)
+ */
+struct nss_ipsecmgr_ref *nss_ipsecmgr_flow_alloc(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key);
+struct nss_ipsecmgr_ref *nss_ipsecmgr_flow_lookup(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key);
+bool nss_ipsecmgr_flow_offload(struct nss_ipsecmgr_priv *priv,
+		struct sk_buff *skb, struct nss_ipsecmgr_flow_data *data);
+bool nss_ipsecmgr_flow_process_pmtu(struct nss_ipsecmgr_priv *priv,
+		struct sk_buff *skb, struct nss_ipsecmgr_flow_data *data);
+
+/*
+ * Subnet API(s)
+ */
+void nss_ipsecmgr_copy_subnet(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_ref *subnet_ref);
+void nss_ipsecmgr_v4_subnet2key(struct nss_ipsecmgr_encap_v4_subnet *subnet, struct nss_ipsecmgr_key *key);
+void nss_ipsecmgr_v6_subnet2key(struct nss_ipsecmgr_encap_v6_subnet *subnet, struct nss_ipsecmgr_key *key);
+void nss_ipsecmgr_v4_subnet_tuple2key(struct nss_ipsec_tuple *tuple, struct nss_ipsecmgr_key *key);
+void nss_ipsecmgr_v6_subnet_tuple2key(struct nss_ipsec_tuple *tuple, struct nss_ipsecmgr_key *key);
+
+/*
+ * Subnet alloc/lookup API(s)
+ */
+struct nss_ipsecmgr_ref *nss_ipsecmgr_subnet_alloc(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key);
+struct nss_ipsecmgr_ref *nss_ipsecmgr_subnet_lookup(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key);
+struct nss_ipsecmgr_ref *nss_ipsecmgr_v4_subnet_match(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *tuple);
+struct nss_ipsecmgr_ref *nss_ipsecmgr_v6_subnet_match(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *tuple);
+
+/*
+ * SA API(s)
+ */
+void nss_ipsecmgr_copy_v4_sa(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_sa_v4 *sa);
+void nss_ipsecmgr_copy_v6_sa(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_sa_v6 *sa);
+void nss_ipsecmgr_copy_sa_data(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_sa_data *data);
+void nss_ipsecmgr_v4_sa2key(struct nss_ipsecmgr_sa_v4 *sa, struct nss_ipsecmgr_key *key);
+void nss_ipsecmgr_v6_sa2key(struct nss_ipsecmgr_sa_v6 *sa, struct nss_ipsecmgr_key *key);
+void nss_ipsecmgr_sa_tuple2key(struct nss_ipsec_tuple *tuple, struct nss_ipsecmgr_key *key);
+void nss_ipsecmgr_sa_stats_update(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_sa_entry *sa);
+
+/*
+ * SA alloc/lookup/flush API(s)
+ */
+struct nss_ipsecmgr_ref *nss_ipsecmgr_sa_alloc(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key);
+struct nss_ipsecmgr_ref *nss_ipsecmgr_sa_lookup(struct nss_ipsecmgr_key *key);
+void nss_ipsecmgr_sa_flush_all(struct nss_ipsecmgr_priv *priv);
+/*
+ * Stats op functions.
+ */
+ssize_t nss_ipsecmgr_netmask_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos);
+ssize_t nss_ipsecmgr_sa_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos);
+ssize_t nss_ipsecmgr_per_flow_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos);
+ssize_t nss_ipsecmgr_per_flow_stats_write(struct file *file, const char __user *buf, size_t count, loff_t *f_pos);
+ssize_t nss_ipsecmgr_flow_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos);
+
+#endif /* __NSS_IPSECMGR_PRIV_H */
diff --git a/qca-nss-clients/ipsecmgr/v1.0/nss_ipsecmgr_sa.c b/qca-nss-clients/ipsecmgr/v1.0/nss_ipsecmgr_sa.c
new file mode 100644
index 0000000..afecd2f
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v1.0/nss_ipsecmgr_sa.c
@@ -0,0 +1,990 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTUOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/of.h>
+#include <linux/ipv6.h>
+#include <linux/skbuff.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/rtnetlink.h>
+#include <net/route.h>
+#include <net/ip6_route.h>
+#include <asm/atomic.h>
+#include <linux/debugfs.h>
+#include <linux/vmalloc.h>
+
+#include <nss_api_if.h>
+#include <nss_ipsec.h>
+#include <nss_ipsecmgr.h>
+#if defined(NSS_IPSECMGR_IPQ807X_SUPPORT)
+#include <nss_crypto_api.h>
+#else
+#include <nss_crypto_if.h>
+#endif
+#include "nss_ipsecmgr_priv.h"
+
+extern struct nss_ipsecmgr_drv *ipsecmgr_ctx;
+
+/*
+ * SA operation info
+ */
+struct nss_ipsecmgr_sa_info {
+	struct nss_ipsec_msg nim;
+	struct nss_ipsecmgr_key sa_key;
+	struct nss_ipsecmgr_key child_key;
+	struct nss_ipsecmgr_sa *sa;
+	uint32_t fail_hash_thresh;
+	uint32_t sa_overhead;
+	uint32_t dst_mtu;
+
+	struct nss_ipsecmgr_ref * (*child_alloc)(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key);
+	struct nss_ipsecmgr_ref * (*child_lookup)(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key);
+};
+
+/*
+ * nss_ipsecmgr_sa_dump()
+ *	dump sa statistics
+ */
+static ssize_t nss_ipsecmgr_sa_dump(struct nss_ipsecmgr_sa_entry *sa, char *buf, ssize_t max_len)
+{
+	struct nss_ipsec_rule_data *data;
+	struct nss_ipsec_rule_oip *oip;
+	uint32_t addr[4];
+	ssize_t len;
+	char *type;
+
+	oip = &sa->nim.msg.rule.oip;
+	data = &sa->nim.msg.rule.data;
+
+	switch (sa->nim.type) {
+	case NSS_IPSEC_TYPE_ENCAP:
+		type = "encap";
+		break;
+
+	case NSS_IPSEC_TYPE_DECAP:
+		type = "decap";
+		break;
+
+	default:
+		return 0;
+	}
+
+	len = snprintf(buf, max_len, "Type:%s\n", type);
+
+	switch (oip->ip_ver) {
+	case IPVERSION:
+		len += snprintf(buf + len, max_len - len, "dst_ip: %pI4h\n", &oip->dst_addr[0]);
+		len += snprintf(buf + len, max_len - len, "src_ip: %pI4h\n", &oip->src_addr[0]);
+		break;
+
+	case 6:
+		len += snprintf(buf + len, max_len - len, "dst_ip: %pI6c\n", nss_ipsecmgr_v6addr_ntoh(oip->dst_addr, addr));
+		len += snprintf(buf + len, max_len - len, "src_ip: %pI6c\n", nss_ipsecmgr_v6addr_ntoh(oip->src_addr, addr));
+		break;
+	}
+
+	len += snprintf(buf + len, max_len - len, "spi_idx: 0x%x\n", oip->esp_spi);
+	len += snprintf(buf + len, max_len - len, "ttl: %d\n", oip->ttl_hop_limit);
+	len += snprintf(buf + len, max_len - len, "crypto session: %d\n", data->crypto_index);
+
+	len += snprintf(buf + len, max_len - len, "ESN: %d\n", data->enable_esn);
+	len += snprintf(buf + len, max_len - len, "seq_num: %llx\n\n", sa->pkts.seq_num);
+
+	/*
+	 * display window information only for decap SA
+	 */
+	len += snprintf(buf + len, max_len - len, "win_size: %d\n", sa->pkts.window_size);
+	len += snprintf(buf + len, max_len - len, "wmax: 0x%llx\n\n", sa->pkts.window_max);
+
+	/*
+	 * packet stats
+	 */
+	len += snprintf(buf + len, max_len - len, "processed: %llu\n", sa->pkts.count);
+	len += snprintf(buf + len, max_len - len, "no_headroom: %d\n", sa->pkts.no_headroom);
+	len += snprintf(buf + len, max_len - len, "no_tailroom: %d\n", sa->pkts.no_tailroom);
+	len += snprintf(buf + len, max_len - len, "no_buf: %d\n", sa->pkts.no_buf);
+	len += snprintf(buf + len, max_len - len, "fail_queue: %d\n", sa->pkts.fail_queue);
+	len += snprintf(buf + len, max_len - len, "fail_hash: %d\n", sa->pkts.fail_hash);
+	len += snprintf(buf + len, max_len - len, "fail_replay: %d\n\n\n", sa->pkts.fail_replay);
+
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_sa_stats_read()
+ * 	read sa statistics
+ */
+ssize_t nss_ipsecmgr_sa_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	struct nss_ipsecmgr_sa_db *sa_db;
+	struct nss_ipsecmgr_sa_entry *sa;
+	ssize_t len, max_len, ret;
+	struct list_head *head;
+	uint32_t num_entries;
+	char *buf;
+	int i;
+
+	sa_db = &ipsecmgr_ctx->sa_db;
+
+	num_entries = atomic_read(&sa_db->num_entries);
+	if (!num_entries) {
+		return 0;
+	}
+
+	len = 0;
+	max_len = num_entries * NSS_IPSECMGR_SA_STATS_SIZE;
+
+	buf = vzalloc(max_len);
+	if (!buf) {
+		nss_ipsecmgr_error("unable to allocate local buffer for SA stats\n");
+		return 0;
+	}
+
+	/*
+	 * walk the SA database for each entry and retrieve the stats
+	 */
+	read_lock_bh(&ipsecmgr_ctx->lock);
+
+	head = sa_db->entries;
+	for (i = NSS_IPSECMGR_MAX_SA; ((max_len - len) > 0) && i--; head++) {
+		list_for_each_entry(sa, head, node) {
+			if (unlikely((max_len - len) <= 0)) {
+				break;
+			}
+
+			len += nss_ipsecmgr_sa_dump(sa, buf + len, max_len - len);
+		}
+	}
+
+	read_unlock_bh(&ipsecmgr_ctx->lock);
+
+	ret = simple_read_from_buffer(ubuf, sz, ppos, buf, len);
+	vfree(buf);
+
+	return ret;
+}
+
+/*
+ * nss_ipsecmgr_sa_free()
+ * 	deallocate the SA if there are no references
+ */
+static void nss_ipsecmgr_sa_free(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_sa_entry *entry = container_of(ref, struct nss_ipsecmgr_sa_entry, ref);
+	struct nss_ipsecmgr_sa_db *db = &ipsecmgr_ctx->sa_db;
+
+	if (!nss_ipsecmgr_ref_is_empty(ref)) {
+		return;
+	}
+
+	/*
+	 * there should be no references remove it from
+	 * the sa_db and free the entry
+	 */
+	list_del_init(&entry->node);
+	atomic_dec(&db->num_entries);
+	kfree(entry);
+}
+
+/*
+ * nss_ipsecmgr_sa_get_overhead()
+ *	get overhead from SA
+ */
+static uint32_t nss_ipsecmgr_sa_overhead(struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_sa_entry *entry;
+	entry = container_of(ref, struct nss_ipsecmgr_sa_entry, ref);
+	return entry->sa_overhead;
+}
+
+/*
+ * nss_ipsecmgr_sa_del()
+ * 	delete sa/child from the reference chain
+ */
+static bool nss_ipsecmgr_sa_del(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_sa_info *info)
+{
+	struct nss_ipsecmgr_ref *sa_ref, *child_ref;
+
+	/*
+	 * lock database
+	 */
+	write_lock_bh(&ipsecmgr_ctx->lock);
+
+	/*
+	 * search the flow for deletion
+	 */
+	child_ref = info->child_lookup(priv, &info->child_key);
+	if (!child_ref) {
+		/*
+		 * unlock device
+		 */
+		write_unlock_bh(&ipsecmgr_ctx->lock);
+
+		nss_ipsecmgr_warn("%px:failed to lookup child_entry\n", priv->dev);
+		nss_ipsecmgr_trace("%px:child_lookup(%px)\n", priv, info->child_lookup);
+		return false;
+	}
+
+	/*
+	 * search the SA in sa_db
+	 */
+	sa_ref = nss_ipsecmgr_sa_lookup(&info->sa_key);
+	if (!sa_ref) {
+		write_unlock_bh(&ipsecmgr_ctx->lock);
+
+		nss_ipsecmgr_warn("%px:failed to lookup sa_entry\n", priv->dev);
+		return false;
+	}
+
+	/*
+	 * Remove the reference if it is associated the SA
+	 */
+	if (nss_ipsecmgr_ref_is_child(child_ref, sa_ref)) {
+		nss_ipsecmgr_ref_free(priv, child_ref);
+	}
+
+	/*
+	 * This deallocates the SA if there are no further references
+	 */
+	nss_ipsecmgr_sa_free(priv, sa_ref);
+
+	write_unlock_bh(&ipsecmgr_ctx->lock);
+	return true;
+}
+
+/*
+ * nss_ipsecmgr_sa_add()
+ * 	add sa/child from the reference chain
+ */
+static bool nss_ipsecmgr_sa_add(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_sa_info *info)
+{
+	struct nss_ipsecmgr_ref *sa_ref, *child_ref;
+	struct nss_ipsecmgr_sa_entry *sa;
+
+	BUG_ON(!info->child_alloc);
+	BUG_ON(!info->child_lookup);
+
+	/*
+	 * lock database
+	 */
+	write_lock_bh(&ipsecmgr_ctx->lock);
+
+	/*
+	 * allocate a flow, this returns either a new flow or an existing
+	 * one incase it is found
+	 */
+	child_ref = info->child_alloc(priv, &info->child_key);
+	if (!child_ref) {
+		/*
+		 * unlock device
+		 */
+		write_unlock_bh(&ipsecmgr_ctx->lock);
+
+		nss_ipsecmgr_warn("%px:failed to alloc child_entry\n", priv->dev);
+		nss_ipsecmgr_trace("%px:child_alloc(%px)\n", priv, info->child_alloc);
+		return false;
+	}
+
+	/*
+	 * allocate a SA, when flow alloc is successful. This returns either
+	 * new SA or an existing one incase it is found
+	 */
+	sa_ref = nss_ipsecmgr_sa_alloc(priv, &info->sa_key);
+	if (!sa_ref) {
+		/*
+		 * release the flow and unlock device
+		 */
+		nss_ipsecmgr_ref_free(priv, child_ref);
+		write_unlock_bh(&ipsecmgr_ctx->lock);
+
+		nss_ipsecmgr_warn("%px:failed to alloc sa_entry\n", priv->dev);
+		return false;
+	}
+
+	/*
+	 * we are only interested the storing the SA portion of the message
+	 */
+	sa = container_of(sa_ref, struct nss_ipsecmgr_sa_entry, ref);
+	sa->ifnum = info->nim.cm.interface;
+	sa->fail_hash_thresh = info->fail_hash_thresh;
+	sa->sa_overhead = info->sa_overhead;
+
+	/*
+	 * Set outer dst entry when overhead is non zero
+	 */
+	if (info->sa_overhead)
+		atomic_set(&priv->outer_dst_mtu, info->dst_mtu);
+
+	memcpy(&sa->nim, &info->nim, sizeof(struct nss_ipsec_msg));
+	memset(&sa->nim.tuple, 0, sizeof(struct nss_ipsec_tuple));
+
+	/*
+	 * Store the SA information to update user for stats reporting
+	 */
+	memcpy(&sa->sa_info, info->sa, sizeof(struct nss_ipsecmgr_sa));
+
+	/*
+	 * clear the stats information
+	 */
+	memset(&sa->pkts, 0, sizeof(struct nss_ipsecmgr_sa_pkt_stats));
+
+	/*
+	 * add child to parent
+	 */
+	nss_ipsecmgr_ref_add(child_ref, sa_ref);
+
+	/*
+	 * Trigger the notification chain for the child
+	 * Note: if there is change in any data then the trigger
+	 * will update the NSS for the change
+	 */
+	nss_ipsecmgr_ref_update(priv, child_ref, &info->nim);
+
+	write_unlock_bh(&ipsecmgr_ctx->lock);
+	return true;
+}
+
+/*
+ * nss_ipsecmgr_sa_alloc()
+ * 	allocate the SA if there is none in the DB
+ */
+struct nss_ipsecmgr_ref *nss_ipsecmgr_sa_alloc(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key)
+{
+	struct nss_ipsecmgr_sa_entry *sa;
+	struct nss_ipsecmgr_sa_db *db;
+	struct nss_ipsecmgr_ref *ref;
+	int idx;
+
+	/*
+	 * Search the object in the database first
+	 */
+	ref = nss_ipsecmgr_sa_lookup(key);
+	if (ref) {
+		return ref;
+	}
+
+	/*
+	 * Object doesn't exist, allocate it
+	 */
+	sa = kzalloc(sizeof(struct nss_ipsecmgr_sa_entry), GFP_ATOMIC);
+	if (!sa) {
+		nss_ipsecmgr_info("failed to alloc sa_entry\n");
+		return NULL;
+	}
+
+	/*
+	 * store tunnel private reference
+	 */
+	sa->priv = priv;
+
+	/*
+	 * initialize sa list node
+	 */
+	ref = &sa->ref;
+	db = &ipsecmgr_ctx->sa_db;
+	INIT_LIST_HEAD(&sa->node);
+
+	/*
+	 * update key
+	 */
+	idx = nss_ipsecmgr_key_data2idx(key, NSS_CRYPTO_MAX_IDXS);
+
+	memcpy(&sa->key, key, sizeof(struct nss_ipsecmgr_key));
+	list_add(&sa->node, &db->entries[idx]);
+
+	atomic_inc(&db->num_entries);
+
+	/*
+	 * initiallize the reference object
+	 */
+	nss_ipsecmgr_ref_init(&sa->ref, NULL, nss_ipsecmgr_sa_free);
+	nss_ipsecmgr_ref_set_overhead(&sa->ref, nss_ipsecmgr_sa_overhead);
+
+	return ref;
+}
+
+/*
+ * nss_ipsecmgr_sa_copy()
+ * 	update the SA entry with the SA data
+ */
+void nss_ipsecmgr_copy_v4_sa(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_sa_v4 *sa)
+{
+	struct nss_ipsec_rule_oip *oip = &nim->msg.rule.oip;
+
+	oip->dst_addr[0] = sa->dst_ip;
+	oip->src_addr[0] = sa->src_ip;
+	oip->ttl_hop_limit = sa->ttl;
+	oip->esp_spi = sa->spi_index;
+	oip->ip_ver = IPVERSION;
+	oip->dst_port = 0;
+	oip->src_port = 0;
+	oip->proto_next_hdr = 0;
+}
+
+/*
+ * nss_ipsecmgr_copy_v6_sa()
+ * 	update the SA entry with the SA data
+ */
+void nss_ipsecmgr_copy_v6_sa(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_sa_v6 *sa)
+{
+	struct nss_ipsec_rule_oip *oip = &nim->msg.rule.oip;
+
+	/*
+	 * copy outer header
+	 */
+	memcpy(oip->dst_addr, sa->dst_ip, sizeof(uint32_t) * 4);
+	memcpy(oip->src_addr, sa->src_ip, sizeof(uint32_t) * 4);
+
+	oip->esp_spi = sa->spi_index;
+	oip->ttl_hop_limit = sa->hop_limit;
+	oip->ip_ver = 6;
+	oip->dst_port = 0;
+	oip->src_port = 0;
+	oip->proto_next_hdr = 0;
+}
+
+/*
+ * nss_ipsecmgr_sa_copy()
+ * 	update the SA entry with the SA data
+ */
+void nss_ipsecmgr_copy_sa_data(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_sa_data *sa_data)
+{
+	struct nss_ipsec_rule_data *data = &nim->msg.rule.data;
+
+	data->crypto_index = (uint16_t)sa_data->crypto_index;
+
+	data->window_size = sa_data->esp.replay_win;
+	data->enable_esn = sa_data->enable_esn;
+
+	data->nat_t_req = sa_data->esp.nat_t_req;
+
+	data->cipher_blk_len = nss_crypto_get_cipher_block_len(data->crypto_index);
+	data->iv_len = nss_crypto_get_iv_len(data->crypto_index);
+
+	data->esp_icv_len = sa_data->esp.icv_len;
+	data->esp_seq_skip = sa_data->esp.seq_skip;
+	data->esp_tail_skip = sa_data->esp.trailer_skip;
+	data->use_pattern = sa_data->use_pattern;
+	data->dscp = sa_data->esp.dscp;
+	data->df = !!sa_data->esp.df;
+	data->copy_dscp = !!sa_data->esp.dscp_copy;
+	data->copy_df = !!sa_data->esp.df_copy;
+}
+
+/*
+ * nss_ipsecmgr_v4_sa2key()
+ * 	convert a SA into a key
+ */
+void nss_ipsecmgr_v4_sa2key(struct nss_ipsecmgr_sa_v4 *sa, struct nss_ipsecmgr_key *key)
+{
+	nss_ipsecmgr_key_reset(key);
+
+	nss_ipsecmgr_key_write_8(key, 4 /* v4 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+	nss_ipsecmgr_key_write_8(key, IPPROTO_ESP, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+	nss_ipsecmgr_key_write_32(key, sa->dst_ip, NSS_IPSECMGR_KEY_POS_IPV4_DST);
+	nss_ipsecmgr_key_write_32(key, sa->src_ip, NSS_IPSECMGR_KEY_POS_IPV4_SRC);
+	nss_ipsecmgr_key_write_32(key, sa->spi_index, NSS_IPSECMGR_KEY_POS_IPV4_ESP_SPI);
+
+	key->len = NSS_IPSECMGR_KEY_LEN_IPV4_SA;
+}
+
+/*
+ * nss_ipsecmgr_sa_tuple2key()
+ * 	convert a SA into a key
+ */
+void nss_ipsecmgr_sa_tuple2key(struct nss_ipsec_tuple *tuple, struct nss_ipsecmgr_key *key)
+{
+	uint32_t i;
+
+	nss_ipsecmgr_key_reset(key);
+
+	switch (tuple->ip_ver) {
+	case IPVERSION:
+		nss_ipsecmgr_key_write_8(key, 4 /* v4 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+		nss_ipsecmgr_key_write_8(key, IPPROTO_ESP, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+		nss_ipsecmgr_key_write_32(key, nss_ipsecmgr_get_v4addr(tuple->dst_addr), NSS_IPSECMGR_KEY_POS_IPV4_DST);
+		nss_ipsecmgr_key_write_32(key, nss_ipsecmgr_get_v4addr(tuple->src_addr), NSS_IPSECMGR_KEY_POS_IPV4_SRC);
+		nss_ipsecmgr_key_write_32(key, tuple->esp_spi, NSS_IPSECMGR_KEY_POS_IPV4_ESP_SPI);
+
+		key->len = NSS_IPSECMGR_KEY_LEN_IPV4_SA;
+		break;
+
+	case 6:
+		nss_ipsecmgr_key_write_8(key, 6 /* v6 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+		nss_ipsecmgr_key_write_8(key, IPPROTO_ESP, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+
+		nss_ipsecmgr_v6addr_swap(tuple->dst_addr, tuple->dst_addr);
+		nss_ipsecmgr_v6addr_swap(tuple->src_addr, tuple->src_addr);
+
+		for (i  = 0; i < 4; i++) {
+			nss_ipsecmgr_key_write_32(key, tuple->dst_addr[i], NSS_IPSECMGR_KEY_POS_IPV6_DST + (i * 32));
+			nss_ipsecmgr_key_write_32(key, tuple->src_addr[i], NSS_IPSECMGR_KEY_POS_IPV6_SRC + (i * 32));
+		}
+
+		nss_ipsecmgr_key_write_32(key, tuple->esp_spi, NSS_IPSECMGR_KEY_POS_IPV6_ESP_SPI);
+		key->len = NSS_IPSECMGR_KEY_LEN_IPV6_SA;
+		break;
+	}
+}
+
+/*
+ * nss_ipsecmgr_v6_sa2key()
+ * 	convert a SA into a key
+ */
+void nss_ipsecmgr_v6_sa2key(struct nss_ipsecmgr_sa_v6 *sa, struct nss_ipsecmgr_key *key)
+{
+	uint32_t i;
+
+	nss_ipsecmgr_key_reset(key);
+
+	nss_ipsecmgr_key_write_8(key, 6 /* v6 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+	nss_ipsecmgr_key_write_8(key, IPPROTO_ESP, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+
+	for (i  = 0; i < 4; i++) {
+		nss_ipsecmgr_key_write_32(key, sa->dst_ip[i], NSS_IPSECMGR_KEY_POS_IPV6_DST + (i * 32));
+		nss_ipsecmgr_key_write_32(key, sa->src_ip[i], NSS_IPSECMGR_KEY_POS_IPV6_SRC + (i * 32));
+	}
+
+	nss_ipsecmgr_key_write_32(key, sa->spi_index, NSS_IPSECMGR_KEY_POS_IPV6_ESP_SPI);
+
+	key->len = NSS_IPSECMGR_KEY_LEN_IPV6_SA;
+}
+
+/*
+ * nss_ipsecmgr_sa_stats_update()
+ * 	Update sa stats locally
+ */
+void nss_ipsecmgr_sa_stats_update(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_sa_entry *sa)
+{
+	struct nss_ipsecmgr_sa_pkt_stats *stats;
+	struct nss_ipsec_sa_stats *sa_stats;
+	struct nss_ipsec_sa_stats *pkts;
+
+	pkts = &nim->msg.stats.sa;
+
+	sa_stats = &nim->msg.stats.sa;
+	stats = &sa->pkts;
+
+	/*
+	 * update SA specific stats
+	 */
+	stats->count += pkts->count;
+	stats->bytes += pkts->bytes;
+
+	stats->no_headroom += pkts->no_headroom;
+	stats->no_tailroom += pkts->no_tailroom;
+	stats->no_buf += pkts->no_resource;
+
+	stats->fail_queue += pkts->fail_queue;
+	stats->fail_hash += pkts->fail_hash;
+	stats->fail_replay += pkts->fail_replay;
+
+	sa->esn_enabled = sa_stats->esn_enabled;
+
+	sa->pkts.seq_num = sa_stats->seq_num;
+	sa->pkts.window_max = sa_stats->window_max;
+	sa->pkts.window_size = sa_stats->window_size;
+}
+
+/*
+ * nss_ipsecmgr_sa_lookup()
+ * 	lookup the SA in the sa_db
+ */
+struct nss_ipsecmgr_ref *nss_ipsecmgr_sa_lookup(struct nss_ipsecmgr_key *key)
+{
+	struct nss_ipsecmgr_sa_db *db = &ipsecmgr_ctx->sa_db;
+	struct nss_ipsecmgr_sa_entry *entry;
+	struct list_head *head;
+	int idx;
+
+	idx = nss_ipsecmgr_key_data2idx(key, NSS_CRYPTO_MAX_IDXS);
+	head = &db->entries[idx];
+
+	list_for_each_entry(entry, head, node) {
+		if (nss_ipsecmgr_key_cmp(&entry->key, key)) {
+			return &entry->ref;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_ipsecmgr_sa_flush_all()
+ * 	remove all SA and its corresponding references
+ */
+void nss_ipsecmgr_sa_flush_all(struct nss_ipsecmgr_priv *priv)
+{
+	struct nss_ipsecmgr_sa_db *sa_db = &ipsecmgr_ctx->sa_db;
+	struct nss_ipsecmgr_sa_entry *entry;
+	struct nss_ipsecmgr_sa_entry *tmp;
+	int ifindex  = priv->dev->ifindex;
+	struct list_head *head;
+	int i;
+
+	/*
+	 * lock database
+	 */
+	write_lock_bh(&ipsecmgr_ctx->lock);
+
+	/*
+	 * walk the SA database for each entry and delete the attached SA.
+	 * Assumption is that single SA cannot be associated to multiple ipsectunX interfaces.
+	 */
+	for (i = 0, head = sa_db->entries; i < NSS_IPSECMGR_MAX_SA; i++, head++) {
+		list_for_each_entry_safe(entry, tmp, head, node) {
+			if (entry->nim.tunnel_id == ifindex) {
+				nss_ipsecmgr_ref_free(priv, &entry->ref);
+			}
+		}
+	}
+
+	/*
+	 * unlock database
+	 */
+	write_unlock_bh(&ipsecmgr_ctx->lock);
+}
+
+/*
+ * nss_ipsecmgr_encap_add()
+ * 	add encap flow/subnet to an existing or new SA
+ */
+bool nss_ipsecmgr_encap_add(struct net_device *tun, struct nss_ipsecmgr_encap_flow *flow,
+				struct nss_ipsecmgr_sa *sa, struct nss_ipsecmgr_sa_data *data)
+{
+	struct nss_ipsecmgr_priv *priv = netdev_priv(tun);
+	struct nss_ipsecmgr_sa_info info = { {{0} } };
+	struct dst_entry *dst;
+	struct flowi6 fl6;
+
+	nss_ipsecmgr_info("%px:encap_add initiated\n", tun);
+
+	info.sa_overhead = sizeof(struct ip_esp_hdr);
+	info.sa_overhead += NSS_IPSECMGR_ESP_PAD_SZ;
+	info.sa_overhead += NSS_IPSECMGR_ESP_TRAIL_SZ;
+	info.sa_overhead += ETH_HLEN;
+
+	nss_ipsecmgr_encap_flow_init(&info.nim, NSS_IPSEC_MSG_TYPE_ADD_RULE, priv);
+
+	switch (flow->type) {
+	case NSS_IPSECMGR_FLOW_TYPE_V4_TUPLE:
+		nss_ipsecmgr_copy_encap_v4_flow(&info.nim, &flow->data.v4_tuple);
+		nss_ipsecmgr_encap_v4_flow2key(&flow->data.v4_tuple, &info.child_key);
+
+		info.child_alloc = nss_ipsecmgr_flow_alloc;
+		info.child_lookup = nss_ipsecmgr_flow_lookup;
+		break;
+
+	case NSS_IPSECMGR_FLOW_TYPE_V4_SUBNET:
+		if (nss_ipsecmgr_verify_v4_subnet(&flow->data.v4_subnet)) {
+			nss_ipsecmgr_warn("%px:invalid subnet and mask\n", tun);
+			return false;
+		}
+
+		nss_ipsecmgr_v4_subnet2key(&flow->data.v4_subnet, &info.child_key);
+
+		info.child_alloc = nss_ipsecmgr_subnet_alloc;
+		info.child_lookup = nss_ipsecmgr_subnet_lookup;
+		break;
+
+	case NSS_IPSECMGR_FLOW_TYPE_V6_TUPLE:
+		nss_ipsecmgr_copy_encap_v6_flow(&info.nim, &flow->data.v6_tuple);
+		nss_ipsecmgr_encap_v6_flow2key(&flow->data.v6_tuple, &info.child_key);
+
+		info.child_alloc = nss_ipsecmgr_flow_alloc;
+		info.child_lookup = nss_ipsecmgr_flow_lookup;
+		break;
+
+	case NSS_IPSECMGR_FLOW_TYPE_V6_SUBNET:
+		if (nss_ipsecmgr_verify_v6_subnet(&flow->data.v6_subnet)) {
+			nss_ipsecmgr_warn("%px:invalid subnet and mask\n", tun);
+			return false;
+		}
+
+		nss_ipsecmgr_v6_subnet2key(&flow->data.v6_subnet, &info.child_key);
+
+		info.child_alloc = nss_ipsecmgr_subnet_alloc;
+		info.child_lookup = nss_ipsecmgr_subnet_lookup;
+		break;
+
+	default:
+		nss_ipsecmgr_warn("%px:unknown flow type(%d)\n", tun, flow->type);
+		return false;
+	}
+
+	switch (sa->type) {
+	case NSS_IPSECMGR_SA_TYPE_V4:
+
+		nss_ipsecmgr_copy_v4_sa(&info.nim, &sa->data.v4);
+		nss_ipsecmgr_copy_sa_data(&info.nim, data);
+		nss_ipsecmgr_v4_sa2key(&sa->data.v4, &info.sa_key);
+
+		info.sa_overhead += sizeof(struct iphdr);
+		info.sa_overhead += data->esp.nat_t_req ?
+			sizeof(struct udphdr) : 0;
+
+		/*
+		 * Update initial value for outer_dst_mtu
+		 * Further this value will be updated as per the PMTU error
+		 * generated for the Tunnel.
+		 */
+		dst = (struct dst_entry *)ip_route_output(&init_net,
+				htonl(sa->data.v4.dst_ip), 0, 0, 0);
+		if (IS_ERR(dst)) {
+			return false;
+		}
+		info.dst_mtu = dst_mtu(dst);
+		dst_release(dst);
+		break;
+
+	case NSS_IPSECMGR_SA_TYPE_V6:
+
+		nss_ipsecmgr_copy_v6_sa(&info.nim, &sa->data.v6);
+		nss_ipsecmgr_copy_sa_data(&info.nim, data);
+		nss_ipsecmgr_v6_sa2key(&sa->data.v6, &info.sa_key);
+
+		info.sa_overhead += sizeof(struct ipv6hdr);
+
+		nss_ipsecmgr_v6addr_ntoh((uint32_t *)&sa->data.v6.dst_ip, (uint32_t *)&fl6.daddr);
+
+		/*
+		 * Update initial value for outer_dst_mtu
+		 * Further this value will be updated as per the PMTU error
+		 * generated for the Tunnel.
+		 */
+		dst = ip6_route_output(&init_net, NULL, &fl6);
+		if (IS_ERR(dst)) {
+			return false;
+		}
+		info.dst_mtu = dst_mtu(dst);
+		dst_release(dst);
+		break;
+
+	default:
+		nss_ipsecmgr_warn("%px:unknown sa type(%d)\n", tun, sa->type);
+		return false;
+	}
+
+	/*
+	 * Compute additional overhead for this SA
+	 */
+	info.sa = sa;
+	info.sa_overhead += nss_crypto_get_iv_len(data->crypto_index);
+	info.sa_overhead += data->esp.icv_len;
+	return nss_ipsecmgr_sa_add(priv, &info);
+}
+EXPORT_SYMBOL(nss_ipsecmgr_encap_add);
+
+/*
+ * nss_ipsecmgr_encap_del()
+ * 	del encap flow/subnet to an existing SA
+ *
+ * Note: if this is the only/last flow or subnet in the SA then
+ * the SA will be also be deallocated
+ */
+bool nss_ipsecmgr_encap_del(struct net_device *tun, struct nss_ipsecmgr_encap_flow *flow, struct nss_ipsecmgr_sa *sa)
+{
+	struct nss_ipsecmgr_priv *priv = netdev_priv(tun);
+	struct nss_ipsecmgr_sa_info info;
+
+	nss_ipsecmgr_info("%px:encap_del initiated\n", tun);
+
+	memset(&info, 0, sizeof(struct nss_ipsecmgr_sa_info));
+	nss_ipsecmgr_encap_flow_init(&info.nim, NSS_IPSEC_MSG_TYPE_DEL_RULE, priv);
+
+	switch (flow->type) {
+	case NSS_IPSECMGR_FLOW_TYPE_V4_TUPLE:
+
+		nss_ipsecmgr_copy_encap_v4_flow(&info.nim, &flow->data.v4_tuple);
+		nss_ipsecmgr_copy_v4_sa(&info.nim, &sa->data.v4);
+
+		nss_ipsecmgr_encap_v4_flow2key(&flow->data.v4_tuple, &info.child_key);
+		nss_ipsecmgr_v4_sa2key(&sa->data.v4, &info.sa_key);
+
+		info.child_alloc = nss_ipsecmgr_flow_alloc;
+		info.child_lookup = nss_ipsecmgr_flow_lookup;
+		break;
+
+	case NSS_IPSECMGR_FLOW_TYPE_V4_SUBNET:
+
+		if (nss_ipsecmgr_verify_v4_subnet(&flow->data.v4_subnet)) {
+			nss_ipsecmgr_warn("%px:invalid subnet and mask\n", tun);
+			return false;
+		}
+
+		nss_ipsecmgr_copy_v4_sa(&info.nim, &sa->data.v4);
+
+		nss_ipsecmgr_v4_subnet2key(&flow->data.v4_subnet, &info.child_key);
+		nss_ipsecmgr_v4_sa2key(&sa->data.v4, &info.sa_key);
+
+		info.child_alloc = nss_ipsecmgr_subnet_alloc;
+		info.child_lookup = nss_ipsecmgr_subnet_lookup;
+		break;
+
+	case NSS_IPSECMGR_FLOW_TYPE_V6_TUPLE:
+
+		nss_ipsecmgr_copy_encap_v6_flow(&info.nim, &flow->data.v6_tuple);
+		nss_ipsecmgr_copy_v6_sa(&info.nim, &sa->data.v6);
+
+		nss_ipsecmgr_encap_v6_flow2key(&flow->data.v6_tuple, &info.child_key);
+		nss_ipsecmgr_v6_sa2key(&sa->data.v6, &info.sa_key);
+
+		info.child_alloc = nss_ipsecmgr_flow_alloc;
+		info.child_lookup = nss_ipsecmgr_flow_lookup;
+		break;
+
+	case NSS_IPSECMGR_FLOW_TYPE_V6_SUBNET:
+
+		if (nss_ipsecmgr_verify_v6_subnet(&flow->data.v6_subnet)) {
+			nss_ipsecmgr_warn("%px:invalid subnet and mask\n", tun);
+			return false;
+		}
+
+		nss_ipsecmgr_copy_v6_sa(&info.nim, &sa->data.v6);
+
+		nss_ipsecmgr_v6_subnet2key(&flow->data.v6_subnet, &info.child_key);
+		nss_ipsecmgr_v6_sa2key(&sa->data.v6, &info.sa_key);
+
+		info.child_alloc = nss_ipsecmgr_subnet_alloc;
+		info.child_lookup = nss_ipsecmgr_subnet_lookup;
+		break;
+
+	default:
+		nss_ipsecmgr_warn("%px:unknown flow type(%d)\n", tun, flow->type);
+		return false;
+	}
+
+	return nss_ipsecmgr_sa_del(priv, &info);
+}
+EXPORT_SYMBOL(nss_ipsecmgr_encap_del);
+
+/*
+ * nss_ipsecmgr_decap_add()
+ * 	add decap flow/subnet to an existing or new SA
+ *
+ * Note: In case of decap rule, sa become flow for lookup into flow table
+ */
+bool nss_ipsecmgr_decap_add(struct net_device *tun, struct nss_ipsecmgr_sa *sa, struct nss_ipsecmgr_sa_data *data)
+{
+	struct nss_ipsecmgr_priv *priv = netdev_priv(tun);
+	struct nss_ipsec_rule *ipsec_rule;
+	struct nss_ipsecmgr_sa_info info;
+
+	nss_ipsecmgr_info("%px:decap_add initiated\n", tun);
+
+	memset(&info, 0, sizeof(struct nss_ipsecmgr_sa_info));
+	nss_ipsecmgr_decap_flow_init(&info.nim, NSS_IPSEC_MSG_TYPE_ADD_RULE, priv);
+
+	switch (sa->type) {
+	case NSS_IPSECMGR_SA_TYPE_V4:
+		nss_ipsecmgr_copy_decap_v4_flow(&info.nim, &sa->data.v4);
+		nss_ipsecmgr_copy_v4_sa(&info.nim, &sa->data.v4);
+		nss_ipsecmgr_copy_sa_data(&info.nim, data);
+
+		/*
+		 * if NATT is set override the protocol and port numbers
+		 */
+		ipsec_rule = &info.nim.msg.rule;
+		if (ipsec_rule->data.nat_t_req) {
+			info.nim.tuple.proto_next_hdr = IPPROTO_UDP;
+			info.nim.tuple.dst_port = NSS_IPSECMGR_NATT_PORT_DATA;
+			info.nim.tuple.src_port = NSS_IPSECMGR_NATT_PORT_DATA;
+		}
+
+		nss_ipsecmgr_decap_v4_flow2key(&sa->data.v4, &info.child_key);
+		nss_ipsecmgr_v4_sa2key(&sa->data.v4, &info.sa_key);
+		break;
+
+	case NSS_IPSECMGR_SA_TYPE_V6:
+		nss_ipsecmgr_copy_decap_v6_flow(&info.nim, &sa->data.v6);
+		nss_ipsecmgr_copy_v6_sa(&info.nim, &sa->data.v6);
+		nss_ipsecmgr_copy_sa_data(&info.nim, data);
+
+		nss_ipsecmgr_decap_v6_flow2key(&sa->data.v6, &info.child_key);
+		nss_ipsecmgr_v6_sa2key(&sa->data.v6, &info.sa_key);
+		break;
+
+	default:
+		nss_ipsecmgr_warn("%px:unknown flow type(%d)\n", tun, sa->type);
+		return false;
+	}
+
+	/*
+	 * Store the fail_hash_threshold in the info
+	 */
+	info.sa = sa;
+	info.sa_overhead = 0;
+	info.fail_hash_thresh  = data->fail_hash_thresh;
+	info.child_alloc = nss_ipsecmgr_flow_alloc;
+	info.child_lookup = nss_ipsecmgr_flow_lookup;
+
+	return nss_ipsecmgr_sa_add(priv, &info);
+}
+EXPORT_SYMBOL(nss_ipsecmgr_decap_add);
+
+/*
+ * nss_ipsecmgr_sa_flush()
+ * 	flush sa and all associated references.
+ */
+bool nss_ipsecmgr_sa_flush(struct net_device *tun, struct nss_ipsecmgr_sa *sa)
+{
+	struct nss_ipsecmgr_priv *priv = netdev_priv(tun);
+	struct nss_ipsecmgr_key sa_key;
+	struct nss_ipsecmgr_ref *sa_ref;
+
+	switch (sa->type) {
+	case NSS_IPSECMGR_SA_TYPE_V4:
+		nss_ipsecmgr_v4_sa2key(&sa->data.v4, &sa_key);
+		break;
+
+	case NSS_IPSECMGR_SA_TYPE_V6:
+		nss_ipsecmgr_v6_sa2key(&sa->data.v6, &sa_key);
+		break;
+
+	default:
+		nss_ipsecmgr_warn("%px:Unsupported sa type (type - %d)\n", tun, sa->type);
+		return false;
+	}
+
+	/*
+	 * lock database
+	 */
+	write_lock_bh(&ipsecmgr_ctx->lock);
+
+	/*
+	 * search the SA in sa_db
+	 */
+	sa_ref = nss_ipsecmgr_sa_lookup(&sa_key);
+	if (!sa_ref) {
+		write_unlock_bh(&ipsecmgr_ctx->lock);
+		nss_ipsecmgr_warn("%px:failed to lookup SA\n", priv);
+		return false;
+	}
+
+	/*
+	 * remove the reference from its associated SA
+	 */
+	nss_ipsecmgr_ref_free(priv, sa_ref);
+
+	/*
+	 * unlock database
+	 */
+	write_unlock_bh(&ipsecmgr_ctx->lock);
+
+	return true;
+}
+EXPORT_SYMBOL(nss_ipsecmgr_sa_flush);
diff --git a/qca-nss-clients/ipsecmgr/v1.0/nss_ipsecmgr_subnet.c b/qca-nss-clients/ipsecmgr/v1.0/nss_ipsecmgr_subnet.c
new file mode 100644
index 0000000..e3c46ee
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v1.0/nss_ipsecmgr_subnet.c
@@ -0,0 +1,672 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/* nss_ipsecmgr_subnet.c
+ *	NSS IPsec manager subnet rules
+ */
+
+#include <linux/list.h>
+#include <linux/hashtable.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <net/ipv6.h>
+#include <linux/version.h>
+#include <linux/debugfs.h>
+#include <linux/vmalloc.h>
+
+#include <nss_ipsecmgr.h>
+
+#include "nss_ipsecmgr_priv.h"
+
+extern struct nss_ipsecmgr_drv *ipsecmgr_ctx;
+
+/*
+ * nss_ipsecmgr_subnet_key_data2idx()
+ * 	subnet specific api for converting word stream to index
+ */
+static uint32_t nss_ipsecmgr_subnet_key_data2idx(struct nss_ipsecmgr_key *key, const uint32_t table_sz)
+{
+	struct nss_ipsecmgr_key tmp_key;
+
+	/*
+	 * The subnet table is keyed without the protocol. This allows us to support
+	 * "any" protocol configuration
+	 */
+
+	memcpy(&tmp_key, key, sizeof(struct nss_ipsecmgr_key));
+	nss_ipsecmgr_key_clear_8(&tmp_key, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+
+	return nss_ipsecmgr_key_data2idx(&tmp_key, table_sz);
+}
+
+/*
+ * nss_ipsecmgr_netmask_is_default()
+ * 	confirm if key is for default netmask.
+ */
+static inline bool nss_ipsecmgr_netmask_is_default(struct nss_ipsecmgr_key *key)
+{
+	uint8_t ip_ver;
+	uint64_t mask64_low;
+	uint64_t mask64_high;
+
+	ip_ver = nss_ipsecmgr_key_read_8(key, NSS_IPSECMGR_KEY_POS_IP_VER);
+	if (likely(ip_ver == 4)) {
+		return !nss_ipsecmgr_key_read_mask32(key, NSS_IPSECMGR_KEY_POS_IPV4_DST);
+	}
+
+	mask64_low = nss_ipsecmgr_key_read_mask64(key, NSS_IPSECMGR_KEY_POS_IPV6_DST);
+	mask64_high = nss_ipsecmgr_key_read_mask64(key, NSS_IPSECMGR_KEY_POS_IPV6_DST + 64);
+
+	return !(mask64_low || mask64_high);
+}
+
+/*
+ * nss_ipsecmgr_netmask2idx()
+ * 	Get the index of the netmask array from key.
+ */
+static inline uint32_t nss_ipsecmgr_netmask2idx(struct nss_ipsecmgr_key *key)
+{
+	uint32_t mask32;
+	uint64_t mask64_low;
+	uint64_t mask64_high;
+	uint8_t ip_ver;
+
+	ip_ver = nss_ipsecmgr_key_read_8(key, NSS_IPSECMGR_KEY_POS_IP_VER);
+	if (likely(ip_ver == 4)) {
+		mask32  = nss_ipsecmgr_key_read_mask32(key, NSS_IPSECMGR_KEY_POS_IPV4_DST);
+		return ffs(mask32) - 1;
+	}
+
+	BUG_ON(ip_ver != 6);
+
+	mask64_low = nss_ipsecmgr_key_read_mask64(key, NSS_IPSECMGR_KEY_POS_IPV6_DST);
+	if (mask64_low) {
+		return __ffs64(mask64_low);
+	}
+
+	mask64_high = nss_ipsecmgr_key_read_mask64(key, NSS_IPSECMGR_KEY_POS_IPV6_DST + 64);
+	if (mask64_high) {
+		return __ffs64(mask64_high) + 64;
+	}
+
+	return NSS_IPSECMGR_MAX_NETMASK;
+}
+
+/*
+ * nss_ipsecmgr_netmask_free()
+ * 	deallocate a netmask entry
+ */
+static bool nss_ipsecmgr_netmask_free(struct nss_ipsecmgr_netmask_db *db, struct nss_ipsecmgr_key *key)
+{
+	struct nss_ipsecmgr_netmask_entry *entry;
+	bool is_default;
+	uint32_t idx;
+
+	is_default = nss_ipsecmgr_netmask_is_default(key);
+	entry = db->default_entry;
+
+	if (is_default && !entry) { /* default with no entry */
+		return false;
+	} else if (is_default && --entry->count) { /* default but more than 1 entry */
+		return false;
+	} else if (is_default) { /* default but last entry */
+		db->default_entry = NULL;
+		goto free;
+	}
+
+	/*
+	 * !default
+	 */
+	idx = nss_ipsecmgr_netmask2idx(key);
+	if (idx >= NSS_IPSECMGR_MAX_NETMASK) {
+		return false;
+	}
+
+	entry = db->entries[idx];
+	BUG_ON(!entry);
+
+	if (--entry->count) {
+		return false;
+	}
+
+	clear_bit(idx, db->bitmap);
+	db->entries[idx] = NULL;
+
+free:
+	kfree(entry);
+	return true;
+}
+
+/*
+ * nss_ipsecmgr_subnet_dump()
+ *	Dump single subnet stats
+ */
+static ssize_t nss_ipsecmgr_subnet_dump(struct nss_ipsecmgr_key *key, struct nss_ipsec_msg *nim, char *buf, ssize_t max_len)
+{
+	uint32_t subnet[4] = {0}, mask[4] = {0};
+	ssize_t len = 0;
+	uint8_t ip_ver;
+	uint8_t proto;
+
+	proto = nss_ipsecmgr_key_read_8(key, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+	ip_ver = nss_ipsecmgr_key_read_8(key, NSS_IPSECMGR_KEY_POS_IP_VER);
+
+	switch (ip_ver) {
+	case 4:
+		nss_ipsecmgr_key_read(key, subnet, mask, NSS_IPSECMGR_KEY_POS_IPV4_DST, 1);
+		len += snprintf(buf + len, max_len - len, "dst_ip: %pI4h\n", subnet);
+		len += snprintf(buf + len, max_len - len, "dst_mask: %pI4h\n", mask);
+		break;
+
+	case 6:
+		/*
+		 * The subnet and mask bits from the key are read to the upper words of the array
+		 * later converted to network order for display.
+		 */
+		nss_ipsecmgr_key_read(key, &subnet[0], &mask[0], NSS_IPSECMGR_KEY_POS_IPV6_DST, 4);
+		nss_ipsecmgr_v6addr_hton(subnet, subnet);
+		nss_ipsecmgr_v6addr_hton(mask, mask);
+
+		len += snprintf(buf + len, max_len - len, "dst_ip: %pI6c\n", subnet);
+		len += snprintf(buf + len, max_len - len, "dst_mask: %pI6c\n", mask);
+		break;
+
+	}
+
+	len += snprintf(buf + len, max_len - len, "proto: %d\n", proto);
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_subnet_read_stats()
+ * 	retreive subnet stats
+ */
+static ssize_t nss_ipsecmgr_subnet_read_stats(struct nss_ipsecmgr_netmask_entry *netmask, char *buf, uint32_t max_len)
+{
+	struct nss_ipsecmgr_subnet_entry *entry;
+	struct list_head *head;
+	ssize_t len = 0;
+	int idx;
+
+	/*
+	 * Check if we have valid entries in the netmask db
+	 */
+	if (!netmask || (netmask->count == 0)) {
+		return 0;
+	}
+
+	head = &netmask->subnets[0];
+	for (idx = NSS_IPSECMGR_MAX_SUBNET; (max_len > 0) && idx--; head++) {
+		list_for_each_entry(entry, head, node) {
+			if (unlikely(max_len <= 0)) {
+				break;
+			}
+
+			len += nss_ipsecmgr_subnet_dump(&entry->key, &entry->nim, buf + len, max_len);
+			max_len = max_len - len;
+		}
+	}
+
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_netmask_stats_read()
+ * 	read subnet statistics
+ */
+ssize_t nss_ipsecmgr_netmask_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	struct nss_ipsecmgr_netmask_db *net_db;
+	ssize_t len, max_len;
+	uint32_t num_entries;
+	ssize_t ret;
+	char *buf;
+	int i;
+
+	net_db = &ipsecmgr_ctx->net_db;
+
+	num_entries = atomic_read(&net_db->num_entries);
+	if (!num_entries) {
+		return 0;
+	}
+
+	max_len = num_entries * NSS_IPSECMGR_SUBNET_STATS_SIZE;
+
+	buf = vzalloc(max_len);
+	if (!buf) {
+		nss_ipsecmgr_error("unable to allocate local buffer for subnet stats\n");
+		return 0;
+	}
+
+	/*
+	 * Take the read lock.
+	 */
+	read_lock_bh(&ipsecmgr_ctx->lock);
+
+	/*
+	 * retreive the default subnet entry stats
+	 */
+	len = nss_ipsecmgr_subnet_read_stats(net_db->default_entry, buf, max_len);
+
+	/*
+	 * retreive the netmask entry db
+	 */
+	for (i = 0; i < NSS_IPSECMGR_MAX_NETMASK; i++) {
+		len += nss_ipsecmgr_subnet_read_stats(net_db->entries[i], buf + len, max_len - len);
+	}
+
+	read_unlock_bh(&ipsecmgr_ctx->lock);
+
+	ret = simple_read_from_buffer(ubuf, sz, ppos, buf, len);
+	vfree(buf);
+	return ret;
+}
+
+/*
+ * nss_ipsecmgr_subnet_update()
+ * 	update the subnet with its associated data
+ */
+static void nss_ipsecmgr_subnet_update(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_ref *ref, struct nss_ipsec_msg *nim)
+{
+	struct nss_ipsecmgr_subnet_entry *subnet;
+
+	subnet = container_of(ref, struct nss_ipsecmgr_subnet_entry, ref);
+
+	memcpy(&subnet->nim, nim, sizeof(struct nss_ipsec_msg));
+}
+
+/*
+ * nss_ipsecmgr_subnet_free()
+ * 	free the associated subnet entry and notify NSS
+ */
+static void nss_ipsecmgr_subnet_free(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_subnet_entry *subnet;
+	struct nss_ipsecmgr_netmask_db *db = &ipsecmgr_ctx->net_db;
+
+	subnet = container_of(ref, struct nss_ipsecmgr_subnet_entry, ref);
+
+	BUG_ON(nss_ipsecmgr_ref_is_empty(ref) == false);
+
+	/*
+	 * detach it from the netmask entry database and
+	 * check if the netmask entry is empty. The netmask
+	 * entry will get freed if there are no further entries
+	 * available
+	 */
+	list_del(&subnet->node);
+	atomic_dec(&db->num_entries);
+
+	nss_ipsecmgr_netmask_free(&ipsecmgr_ctx->net_db, &subnet->key);
+	kfree(subnet);
+}
+
+/*
+ * nss_ipsecmgr_netmask_lookup()
+ * 	lookup a netmask entry
+ */
+static inline struct nss_ipsecmgr_netmask_entry *nss_ipsecmgr_netmask_lookup(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key)
+{
+	struct nss_ipsecmgr_netmask_db *db = &ipsecmgr_ctx->net_db;
+	uint32_t idx;
+
+	if (nss_ipsecmgr_netmask_is_default(key)) {
+		return db->default_entry;
+	}
+
+	idx = nss_ipsecmgr_netmask2idx(key);
+	return (idx >= NSS_IPSECMGR_MAX_NETMASK) ? NULL : db->entries[idx];
+}
+
+/*
+ * nss_ipsecmgr_netmask_alloc()
+ * 	allocate a netmask entry
+ */
+static struct nss_ipsecmgr_netmask_entry *nss_ipsecmgr_netmask_alloc(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key)
+{
+	struct nss_ipsecmgr_netmask_db *db = &ipsecmgr_ctx->net_db;
+	struct nss_ipsecmgr_netmask_entry *entry;
+	uint32_t idx;
+
+	entry = nss_ipsecmgr_netmask_lookup(priv, key);
+	if (entry) {
+		return entry;
+	}
+
+	entry = kzalloc(sizeof(struct nss_ipsecmgr_netmask_entry), GFP_ATOMIC);
+	if (!entry) {
+		return NULL;
+	}
+
+	nss_ipsecmgr_init_subnet_db(entry);
+	entry->count = 1;
+
+	if (nss_ipsecmgr_netmask_is_default(key)) {
+		db->default_entry = entry;
+		return entry;
+	}
+
+	idx = nss_ipsecmgr_netmask2idx(key);
+	if (idx >= NSS_IPSECMGR_MAX_NETMASK) {
+		kfree(entry);
+		return NULL;
+	}
+
+	entry->mask_bits = NSS_IPSECMGR_MAX_NETMASK - idx;
+	set_bit(idx, db->bitmap);
+	db->entries[idx] = entry;
+
+	return entry;
+}
+
+
+/*
+ * nss_ipsecmgr_copy_subnet()
+ * 	copy subnet nim
+ */
+void nss_ipsecmgr_copy_subnet(struct nss_ipsec_msg *nim, struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_subnet_entry *entry;
+	struct nss_ipsec_rule_data *data;
+	struct nss_ipsec_rule_oip *oip;
+
+	entry = container_of(ref, struct nss_ipsecmgr_subnet_entry, ref);
+
+	oip = &entry->nim.msg.rule.oip;
+	data = &entry->nim.msg.rule.data;
+
+	memcpy(&nim->msg.rule.oip, oip, sizeof(struct nss_ipsec_rule_oip));
+	memcpy(&nim->msg.rule.data, data, sizeof(struct nss_ipsec_rule_data));
+}
+
+/*
+ * nss_ipsecmgr_v4_subnet_sel2key()
+ * 	convert subnet selector to key
+ */
+void nss_ipsecmgr_v4_subnet_tuple2key(struct nss_ipsec_tuple *tuple, struct nss_ipsecmgr_key *key)
+{
+	nss_ipsecmgr_key_reset(key);
+
+	nss_ipsecmgr_key_write_8(key, 4 /* ipv4 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+	nss_ipsecmgr_key_write_8(key, tuple->proto_next_hdr, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+	nss_ipsecmgr_key_write_32(key, nss_ipsecmgr_get_v4addr(tuple->dst_addr), NSS_IPSECMGR_KEY_POS_IPV4_DST);
+
+	key->len = NSS_IPSECMGR_KEY_LEN_IPV4_SUBNET;
+}
+
+/*
+ * nss_ipsecmgr_v6_subnet_sel2key()
+ * 	convert subnet selector to key
+ */
+void nss_ipsecmgr_v6_subnet_tuple2key(struct nss_ipsec_tuple *tuple, struct nss_ipsecmgr_key *key)
+{
+	uint32_t pos;
+	uint32_t i;
+
+	nss_ipsecmgr_key_reset(key);
+
+	nss_ipsecmgr_key_write_8(key, 6 /* ipv6 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+	nss_ipsecmgr_key_write_8(key, tuple->proto_next_hdr, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+
+	for (i = 0; i < 4; i++) {
+		pos = NSS_IPSECMGR_KEY_POS_IPV6_DST + (i * NSS_IPSECMGR_BITS_PER_WORD);
+		nss_ipsecmgr_key_write_32(key, tuple->dst_addr[i], pos);
+	}
+
+	key->len = NSS_IPSECMGR_KEY_LEN_IPV6_SUBNET;
+}
+
+
+/*
+ * nss_ipsecmgr_v4_subnet2key()
+ *      convert an v4 subnet into a key
+ */
+void nss_ipsecmgr_v4_subnet2key(struct nss_ipsecmgr_encap_v4_subnet *net, struct nss_ipsecmgr_key *key)
+{
+	nss_ipsecmgr_key_reset(key);
+
+	nss_ipsecmgr_key_write_8(key, 4 /* ipv4 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+	nss_ipsecmgr_key_write_8(key, (uint8_t)net->protocol, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+	nss_ipsecmgr_key_write(key, &net->dst_subnet, &net->dst_mask, NSS_IPSECMGR_KEY_POS_IPV4_DST, 1);
+
+	/*
+	 * clear mask if caller specify protocol as any (0xff).
+	 * this will serve as default entry for any-protocol.
+	 */
+	if (net->protocol == NSS_IPSECMGR_PROTO_NEXT_HDR_ANY) {
+		nss_ipsecmgr_key_clear_8(key, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+	}
+
+	key->len = NSS_IPSECMGR_KEY_LEN_IPV4_SUBNET;
+}
+
+/*
+ * nss_ipsecmgr_v6_subnet2key()
+ *      convert an v6 subnet into a key
+ */
+void nss_ipsecmgr_v6_subnet2key(struct nss_ipsecmgr_encap_v6_subnet *net, struct nss_ipsecmgr_key *key)
+{
+	nss_ipsecmgr_key_reset(key);
+
+	nss_ipsecmgr_key_write_8(key, 6 /* ipv6 */, NSS_IPSECMGR_KEY_POS_IP_VER);
+	nss_ipsecmgr_key_write_8(key, (uint8_t)net->next_hdr, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+	nss_ipsecmgr_key_write(key, net->dst_subnet, net->dst_mask, NSS_IPSECMGR_KEY_POS_IPV6_DST, 4);
+
+	/*
+	 * clear mask if caller specify protocol as any (0xff).
+	 * this will serve as default entry for any-protocol.
+	 */
+	if (net->next_hdr == NSS_IPSECMGR_PROTO_NEXT_HDR_ANY) {
+		nss_ipsecmgr_key_clear_8(key, NSS_IPSECMGR_KEY_POS_IP_PROTO);
+	}
+
+	key->len = NSS_IPSECMGR_KEY_LEN_IPV6_SUBNET;
+}
+
+
+/*
+ * nss_ipsecmgr_v4_subnet_match()
+ * 	peform a v4 subnet based match in netmask database
+ */
+struct nss_ipsecmgr_ref *nss_ipsecmgr_v4_subnet_match(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key)
+{
+	struct nss_ipsecmgr_netmask_db *db = &ipsecmgr_ctx->net_db;
+	struct nss_ipsecmgr_key tmp_key;
+	struct nss_ipsecmgr_ref *ref;
+	int i;
+
+	/*
+	 * cycle through the bitmap for each subnet
+	 */
+	for_each_set_bit(i, db->bitmap, 32) {
+
+		BUG_ON(db->entries[i] == NULL);
+		BUG_ON(db->entries[i]->count == 0);
+
+		memcpy(&tmp_key, key, sizeof(struct nss_ipsecmgr_key));
+
+		/*
+		 * set the key with the right mask for hash index computation;
+		 * each subnet index has its associated mask value
+		 */
+		nss_ipsecmgr_key_lshift_mask(&tmp_key, i, NSS_IPSECMGR_KEY_POS_IPV4_DST);
+
+		ref = nss_ipsecmgr_subnet_lookup(priv, &tmp_key);
+		if (ref) {
+			return ref;
+		}
+	}
+
+	memcpy(&tmp_key, key, sizeof(struct nss_ipsecmgr_key));
+	/*
+	 * normal lookup failed; check default subnet entry
+	 * - clear the destination netmask before lookup
+	 */
+	nss_ipsecmgr_key_clear_32(&tmp_key, NSS_IPSECMGR_KEY_POS_IPV4_DST);
+
+	ref = nss_ipsecmgr_subnet_lookup(priv, &tmp_key);
+	if (ref) {
+		return ref;
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_ipsecmgr_v6_subnet_match()
+ * 	peform a v6 subnet based match in netmask database
+ */
+struct nss_ipsecmgr_ref *nss_ipsecmgr_v6_subnet_match(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key)
+{
+	struct nss_ipsecmgr_netmask_db *db = &ipsecmgr_ctx->net_db;
+	struct nss_ipsecmgr_key tmp_key;
+	struct nss_ipsecmgr_ref *ref;
+	int i;
+
+	/*
+	 * cycle through the bitmap for each subnet
+	 */
+	for_each_set_bit(i, db->bitmap, NSS_IPSECMGR_MAX_NETMASK) {
+
+		BUG_ON(db->entries[i] == NULL);
+		BUG_ON(db->entries[i]->count == 0);
+		memcpy(&tmp_key, key, sizeof(struct nss_ipsecmgr_key));
+
+		nss_ipsecmgr_key_lshift_mask128(&tmp_key, i, NSS_IPSECMGR_KEY_POS_IPV6_DST);
+
+		ref = nss_ipsecmgr_subnet_lookup(priv, &tmp_key);
+		if (ref) {
+			return ref;
+		}
+	}
+
+	memcpy(&tmp_key, key, sizeof(struct nss_ipsecmgr_key));
+
+	/*
+	 * normal lookup failed; check default subnet entry
+	 * - clear the destination netmask before lookup
+	 */
+	nss_ipsecmgr_key_clear_128(&tmp_key, NSS_IPSECMGR_KEY_POS_IPV6_DST);
+
+	ref = nss_ipsecmgr_subnet_lookup(priv, &tmp_key);
+	if (ref) {
+		return ref;
+	}
+	return NULL;
+}
+
+/*
+ * nss_ipsecmgr_subnet_lookup()
+ * 	lookup a subnet entry
+ */
+struct nss_ipsecmgr_ref *nss_ipsecmgr_subnet_lookup(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key)
+{
+	struct nss_ipsecmgr_netmask_entry *netmask;
+	struct nss_ipsecmgr_subnet_entry *entry;
+	struct list_head *head;
+	int idx;
+
+	netmask = nss_ipsecmgr_netmask_lookup(priv, key);
+	if (!netmask) {
+		return NULL;
+	}
+
+	BUG_ON(netmask->count == 0);
+
+	idx = nss_ipsecmgr_subnet_key_data2idx(key, NSS_IPSECMGR_MAX_SUBNET);
+	head = &netmask->subnets[idx];
+
+	list_for_each_entry(entry, head, node) {
+		if (nss_ipsecmgr_key_cmp(&entry->key, key)) {
+			return &entry->ref;
+		}
+	}
+	return NULL;
+}
+
+/*
+ * nss_ipsecmgr_subnet_alloc()
+ *      allocate a subnet entry
+ */
+struct nss_ipsecmgr_ref *nss_ipsecmgr_subnet_alloc(struct nss_ipsecmgr_priv *priv, struct nss_ipsecmgr_key *key)
+{
+	struct nss_ipsecmgr_netmask_entry *netmask;
+	struct nss_ipsecmgr_subnet_entry *subnet;
+	struct nss_ipsecmgr_netmask_db *db;
+	struct nss_ipsecmgr_ref *ref;
+	uint32_t idx;
+
+	/*
+	 * subnet lookup before allocating a new one
+	 */
+	ref = nss_ipsecmgr_subnet_lookup(priv, key);
+	if (ref) {
+		return ref;
+	}
+
+	/*
+	 * allocate the netmask
+	 */
+	netmask = nss_ipsecmgr_netmask_alloc(priv, key);
+	if (!netmask) {
+		return NULL;
+	}
+
+	/*
+	 * allocate the subnet entry
+	 */
+	subnet = kzalloc(sizeof(struct nss_ipsecmgr_subnet_entry), GFP_ATOMIC);
+	if (!subnet) {
+		nss_ipsecmgr_netmask_free(&ipsecmgr_ctx->net_db, key);
+		return NULL;
+	}
+
+	subnet->priv = priv;
+	ref = &subnet->ref;
+
+	/*
+	 * add flow to the database
+	 */
+	INIT_LIST_HEAD(&subnet->node);
+
+	/*
+	 * update key
+	 */
+	idx = nss_ipsecmgr_subnet_key_data2idx(key, NSS_IPSECMGR_MAX_SUBNET);
+
+	/*
+	 * TODO
+	 * For subnet entry with any protocol, just add it to the tail.
+	 * This will force subnet with any-protcol to have least priority
+	 * over other specific protocol entries during subnet lookup.
+	 */
+	memcpy(&subnet->key, key, sizeof(struct nss_ipsecmgr_key));
+	list_add(&subnet->node, &netmask->subnets[idx]);
+	netmask->count++;
+
+	db = &ipsecmgr_ctx->net_db;
+	atomic_inc(&db->num_entries);
+
+	/*
+	 * initiallize the reference object
+	 */
+	nss_ipsecmgr_ref_init(&subnet->ref, nss_ipsecmgr_subnet_update, nss_ipsecmgr_subnet_free);
+
+	return ref;
+}
diff --git a/qca-nss-clients/ipsecmgr/v2.0/Makefile b/qca-nss-clients/ipsecmgr/v2.0/Makefile
new file mode 100644
index 0000000..4e5bd8f
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/Makefile
@@ -0,0 +1,19 @@
+# Makefile for the ipsecmgr v2.0 client
+
+ccflags-y += $(NSS_CCFLAGS) -I$(obj)/../../exports
+ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)"
+ccflags-y += -Wall -Werror
+
+obj-m += qca-nss-ipsecmgr.o
+qca-nss-ipsecmgr-objs := nss_ipsecmgr.o
+qca-nss-ipsecmgr-objs += nss_ipsecmgr_ref.o
+qca-nss-ipsecmgr-objs += nss_ipsecmgr_tunnel.o
+qca-nss-ipsecmgr-objs += nss_ipsecmgr_ctx.o
+qca-nss-ipsecmgr-objs += nss_ipsecmgr_sa.o
+qca-nss-ipsecmgr-objs += nss_ipsecmgr_flow.o
+ccflags-y += -DNSS_IPSECMGR_DEBUG_LEVEL=3
+
+ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64 ipq60xx ipq60xx_64))
+ccflags-y += -DNSS_IPSECMGR_PPE_SUPPORT
+ccflags-y += -DNSS_IPSECMGR_DMA_SUPPORT
+endif
diff --git a/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr.c b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr.c
new file mode 100644
index 0000000..aa5eb3e
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr.c
@@ -0,0 +1,354 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/* nss_ipsecmgr.c
+ *	IPSec Manager
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/of.h>
+#include <linux/ipv6.h>
+#include <linux/skbuff.h>
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/netdevice.h>
+#include <linux/rtnetlink.h>
+#include <linux/etherdevice.h>
+#include <linux/vmalloc.h>
+#include <linux/debugfs.h>
+#include <linux/atomic.h>
+#include <net/protocol.h>
+#include <net/route.h>
+#include <net/ip6_route.h>
+#include <net/esp.h>
+#include <net/xfrm.h>
+#include <net/icmp.h>
+
+#include <crypto/aead.h>
+#include <crypto/skcipher.h>
+#include <crypto/internal/hash.h>
+
+#include <nss_api_if.h>
+#include <nss_ipsec_cmn.h>
+#include <nss_ipsecmgr.h>
+#include <nss_cryptoapi.h>
+
+#ifdef NSS_IPSECMGR_PPE_SUPPORT
+#include <ref/ref_vsi.h>
+#endif
+
+#include "nss_ipsecmgr_ref.h"
+#include "nss_ipsecmgr_flow.h"
+#include "nss_ipsecmgr_sa.h"
+#include "nss_ipsecmgr_ctx.h"
+#include "nss_ipsecmgr_tunnel.h"
+#include "nss_ipsecmgr_priv.h"
+
+bool enable_ipsec_inline = false;
+module_param(enable_ipsec_inline, bool, S_IRUGO);
+MODULE_PARM_DESC(enable_ipsec_inline, "Enable IPsec Inline mode");
+
+struct nss_ipsecmgr_drv *ipsecmgr_drv;
+
+static const struct net_device_ops nss_ipsecmgr_dummy_ndev_ops;
+
+/*
+ * nss_ipsecmgr_dummy_free()
+ *	Setup function for dummy netdevice.
+ */
+static void nss_ipsecmgr_dummy_free(struct net_device *dev)
+{
+	free_netdev(dev);
+}
+
+/*
+ * nss_ipsecmgr_dummy_setup()
+ *	Setup function for dummy netdevice.
+ */
+static void nss_ipsecmgr_dummy_setup(struct net_device *dev)
+{
+	/*
+	 * Since, we want to start with fragmentation post IPsec
+	 * transform.
+	 */
+	dev->mtu = ETH_DATA_LEN;
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 11, 8))
+	dev->destructor = nss_ipsecmgr_dummy_free;
+#else
+	dev->priv_destructor = nss_ipsecmgr_dummy_free;
+#endif
+}
+
+/*
+ * nss_ipsecmgr_rx_notify()
+ *	RX notification on base node
+ */
+static void nss_ipsecmgr_rx_notify(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct net_device *dev = app_data;
+	nss_ipsecmgr_warn("%px: Notification received on base node", netdev_priv(dev));
+}
+
+/*
+ * nss_ipsecmgr_configure()
+ *	Send the configure node message
+ */
+static void nss_ipsecmgr_configure(struct work_struct *work)
+{
+	enum nss_ipsec_cmn_msg_type type = NSS_IPSEC_CMN_MSG_TYPE_NODE_CONFIG;
+	uint32_t ifnum = ipsecmgr_drv->ifnum;
+	struct nss_ipsec_cmn_msg nicm = {0};
+	nss_tx_status_t status;
+
+	/*
+	 * By making sure that cryptoapi is registered,
+	 * we are confirming that IPsec FW is initialized
+	 * and ready to be configured.
+	 */
+	if (!nss_cryptoapi_is_registered()) {
+		schedule_delayed_work(&ipsecmgr_drv->cfg_work, NSS_IPSECMGR_NODE_CONFIG_RETRY_TIMEOUT);
+		return;
+	}
+
+#ifdef NSS_IPSECMGR_DMA_SUPPORT
+	nicm.msg.node.dma_lookaside = true;
+	nicm.msg.node.dma_redirect = ipsecmgr_drv->ipsec_inline;
+#else
+	nicm.msg.node.dma_lookaside = false;
+	nicm.msg.node.dma_redirect = false;
+#endif
+
+	/*
+	 * Send DMA IPsec message to initialize the DMA rings.
+	 */
+	status = nss_ipsec_cmn_tx_msg_sync(ipsecmgr_drv->nss_ctx, ifnum, type, sizeof(nicm.msg.node), &nicm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ipsecmgr_trace("%px: failed to configure IPsec in NSS(%u)", ipsecmgr_drv, status);
+		/*
+		 * TODO: We need unwind in case of failure
+		 */
+		return;
+	}
+
+	/*
+	 * Program PPE for inline mode; if inline is enabled.
+	 */
+	if (ipsecmgr_drv->ipsec_inline) {
+
+#ifdef NSS_IPSECMGR_PPE_SUPPORT
+		struct nss_ipsecmgr_tunnel *tun = netdev_priv(ipsecmgr_drv->dev);
+		struct nss_ipsecmgr_ctx *redir;
+		uint32_t vsi_num = 0;
+
+		redir = nss_ipsecmgr_ctx_alloc(tun,
+						NSS_IPSEC_CMN_CTX_TYPE_REDIR,
+						NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_REDIRECT,
+						nss_ipsecmgr_ctx_rx_redir,
+						nss_ipsecmgr_ctx_rx_stats,
+						0);
+		if (!redir) {
+			nss_ipsecmgr_warn("%px: failed to allocate redirect context; disabling inline", tun);
+			ipsecmgr_drv->ipsec_inline = false;
+			return;
+		}
+
+		nss_ipsecmgr_ctx_set_except(redir, redir->ifnum);
+
+		if (!nss_ipsecmgr_ctx_config(redir)) {
+			nss_ipsecmgr_warn("%px: failed to configure redirect context; disabling inline", tun);
+			ipsecmgr_drv->ipsec_inline = false;
+			nss_ipsecmgr_ctx_free(redir);
+			return;
+		}
+
+		/*
+		 * Get port's default VSI.
+		 */
+		if (ppe_port_vsi_get(0, NSS_PPE_PORT_IPSEC, &vsi_num)) {
+			nss_ipsecmgr_warn("%px: Failed to get port VSI", ipsecmgr_drv);
+			nss_ipsecmgr_ctx_free(redir);
+			ipsecmgr_drv->ipsec_inline = false;
+			return;
+		}
+
+		/*
+		 * Configure PPE's inline port; Configure the redirect interface to receive
+		 * exception packets from inline path
+		 */
+		if (!nss_ipsec_cmn_ppe_port_config(ipsecmgr_drv->nss_ctx, ipsecmgr_drv->dev, redir->ifnum, vsi_num)) {
+			nss_ipsecmgr_warn("%px: Failed to configure PPE inline mode", ipsecmgr_drv);
+			nss_ipsecmgr_ctx_free(redir);
+			ipsecmgr_drv->ipsec_inline = false;
+			return;
+		}
+
+		nss_ipsecmgr_ctx_attach(&tun->ctx_db, redir);
+
+		debugfs_create_file("redir", S_IRUGO, tun->dentry, redir, &ipsecmgr_ctx_file_ops);
+#endif
+	}
+
+	nss_ipsecmgr_trace("%px: Configure node msg successful", ipsecmgr_drv);
+	return;
+}
+
+/*
+ * nss_ipsecmgr_init()
+ *	module init
+ */
+static int __init nss_ipsecmgr_init(void)
+{
+	struct nss_ipsecmgr_tunnel *tun;
+	struct net_device *dev = NULL;
+	int status;
+
+	ipsecmgr_drv = vzalloc(sizeof(*ipsecmgr_drv));
+	if (!ipsecmgr_drv) {
+		nss_ipsecmgr_warn("Failed to allocate IPsec manager context");
+		return -1;
+	}
+
+	ipsecmgr_drv->nss_ctx = nss_ipsec_cmn_get_context();
+	if (!ipsecmgr_drv->nss_ctx) {
+		nss_ipsecmgr_warn("%px: Failed to retrieve NSS context", ipsecmgr_drv);
+		goto free;
+	}
+
+#ifdef NSS_IPSECMGR_PPE_SUPPORT
+	ipsecmgr_drv->ipsec_inline = enable_ipsec_inline;
+#endif
+
+	dev = alloc_netdev(sizeof(*tun), NSS_IPSECMGR_DEFAULT_TUN_NAME, NET_NAME_UNKNOWN, nss_ipsecmgr_dummy_setup);
+	if (!dev) {
+		nss_ipsecmgr_warn("%px: Failed to allocate dummy netdevice", ipsecmgr_drv);
+		goto free;
+	}
+
+	tun = netdev_priv(dev);
+	tun->dev = dev;
+
+	nss_ipsecmgr_ref_init(&tun->ref, NULL, NULL);
+	INIT_LIST_HEAD(&tun->list);
+	INIT_LIST_HEAD(&tun->free_refs);
+
+	dev->netdev_ops = &nss_ipsecmgr_dummy_ndev_ops;
+	nss_ipsecmgr_db_init(&tun->ctx_db);
+
+	status = register_netdev(dev);
+	if (status) {
+		nss_ipsecmgr_info("%px: Failed to register dummy netdevice(%px)", ipsecmgr_drv, dev);
+		goto free;
+	}
+
+	ipsecmgr_drv->dev = dev;
+	ipsecmgr_drv->ifnum = NSS_IPSEC_CMN_INTERFACE;
+
+	rwlock_init(&ipsecmgr_drv->lock);
+	nss_ipsecmgr_db_init_entries(ipsecmgr_drv->sa_db, NSS_IPSECMGR_SA_MAX);
+	nss_ipsecmgr_db_init_entries(ipsecmgr_drv->flow_db, NSS_IPSECMGR_FLOW_MAX);
+	nss_ipsecmgr_db_init(&ipsecmgr_drv->tun_db);
+
+	nss_ipsec_cmn_notify_register(ipsecmgr_drv->ifnum, nss_ipsecmgr_rx_notify, ipsecmgr_drv->dev);
+	INIT_DELAYED_WORK(&ipsecmgr_drv->cfg_work, nss_ipsecmgr_configure);
+
+	/*
+	 * Initialize debugfs.
+	 */
+	ipsecmgr_drv->dentry = debugfs_create_dir("qca-nss-ipsecmgr", NULL);
+	if (ipsecmgr_drv->dentry) {
+		tun->dentry = debugfs_create_dir(dev->name, ipsecmgr_drv->dentry);
+	}
+
+	/*
+	 * Configure inline mode and the DMA rings.
+	 */
+	nss_ipsecmgr_configure(&ipsecmgr_drv->cfg_work.work);
+
+	write_lock(&ipsecmgr_drv->lock);
+	list_add(&tun->list, &ipsecmgr_drv->tun_db);
+
+	ipsecmgr_drv->max_mtu = dev->mtu;
+	write_unlock(&ipsecmgr_drv->lock);
+
+	nss_ipsecmgr_info("NSS IPsec manager loaded: %s\n", NSS_CLIENT_BUILD_ID);
+	return 0;
+
+free:
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 11, 8))
+	if (dev)
+		dev->destructor(dev);
+#endif
+	vfree(ipsecmgr_drv);
+	ipsecmgr_drv = NULL;
+	return -1;
+}
+
+/*
+ * nss_ipsecmgr_exit()
+ *	module exit
+ */
+static void __exit nss_ipsecmgr_exit(void)
+{
+	struct nss_ipsecmgr_tunnel *tun;
+
+	if (!ipsecmgr_drv) {
+		nss_ipsecmgr_warn("IPsec manager driver context empty");
+		return;
+	}
+
+	if (!ipsecmgr_drv->nss_ctx) {
+		nss_ipsecmgr_warn("%px: NSS Context empty", ipsecmgr_drv);
+		goto free;
+	}
+
+	tun = netdev_priv(ipsecmgr_drv->dev);
+
+	write_lock(&ipsecmgr_drv->lock);
+	list_del(&tun->list);
+
+	ipsecmgr_drv->max_mtu = U16_MAX;
+	write_unlock(&ipsecmgr_drv->lock);
+
+	BUG_ON(!list_empty(&ipsecmgr_drv->tun_db));
+
+	/*
+	 * Unregister the callbacks from the HLOS as we are no longer
+	 * interested in exception data & async messages
+	 */
+	nss_ipsec_cmn_notify_unregister(ipsecmgr_drv->nss_ctx, ipsecmgr_drv->ifnum);
+	unregister_netdev(ipsecmgr_drv->dev);
+
+	/*
+	 * Remove debugfs directory and entries below that.
+	 */
+	debugfs_remove_recursive(ipsecmgr_drv->dentry);
+
+free:
+	/*
+	 * Free the ipsecmgr ctx
+	 */
+	vfree(ipsecmgr_drv);
+	ipsecmgr_drv = NULL;
+
+	nss_ipsecmgr_info("NSS IPsec manager unloaded\n");
+
+}
+
+MODULE_LICENSE("Dual BSD/GPL");
+
+module_init(nss_ipsecmgr_init);
+module_exit(nss_ipsecmgr_exit);
diff --git a/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_ctx.c b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_ctx.c
new file mode 100644
index 0000000..63979c9
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_ctx.c
@@ -0,0 +1,981 @@
+/*
+ * ********************************************************************************
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ **********************************************************************************
+ */
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/inet.h>
+#include <linux/of.h>
+#include <linux/ipv6.h>
+#include <linux/kernel.h>
+#include <linux/skbuff.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/rtnetlink.h>
+#include <asm/atomic.h>
+#include <linux/debugfs.h>
+#include <linux/completion.h>
+#include <linux/vmalloc.h>
+#include <net/icmp.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/ip6_route.h>
+
+#include <nss_api_if.h>
+#include <nss_ipsec_cmn.h>
+#include <nss_ipsecmgr.h>
+
+#include "nss_ipsecmgr_ref.h"
+#include "nss_ipsecmgr_flow.h"
+#include "nss_ipsecmgr_sa.h"
+#include "nss_ipsecmgr_ctx.h"
+#include "nss_ipsecmgr_tunnel.h"
+#include "nss_ipsecmgr_priv.h"
+
+/*
+ * Context Host statistics print info
+ */
+static const struct nss_ipsecmgr_print ipsecmgr_print_ctx_host_stats[] = {
+	{"\tIPv4 notify", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tIPv4 notify drop", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tIPv4 route", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tIPv4 route drop", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tIPv6 notify", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tIPv6 notify drop", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tIPv6 route", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tIPv6 route drop", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tInner exp", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tInner exp drop", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tInner callbacks", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tInner fail dev", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tInner fail SA", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tInner fail flow", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tOuter exp", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tOuter exp drop", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tOuter callbacks", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tOuter fail dev", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tOuter fail SA", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tOuter fail flow", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tRedir exp", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tRedir exp drop", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tRedir callbacks", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tRedir fail dev", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tRedir fail SA", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tRedir fail flow", NSS_IPSECMGR_PRINT_DWORD},
+};
+
+/*
+ * Context statistics print info
+ */
+static const struct nss_ipsecmgr_print ipsecmgr_print_ctx_stats[] = {
+	{"\trx_packets", NSS_IPSECMGR_PRINT_DWORD},
+	{"\trx_bytes", NSS_IPSECMGR_PRINT_DWORD},
+	{"\ttx_packets", NSS_IPSECMGR_PRINT_DWORD},
+	{"\ttx_bytes", NSS_IPSECMGR_PRINT_DWORD},
+	{"\trx_dropped[0]", NSS_IPSECMGR_PRINT_DWORD},
+	{"\trx_dropped[1]", NSS_IPSECMGR_PRINT_DWORD},
+	{"\trx_dropped[2]", NSS_IPSECMGR_PRINT_DWORD},
+	{"\trx_dropped[3]", NSS_IPSECMGR_PRINT_DWORD},
+	{"\texceptioned", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tlinearized", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tredirected", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tdropped", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_sa", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_flow", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_stats", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_exception", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_transform", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_linearized", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_mdata_ver", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_ctx_active", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_pbuf_crypto", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_queue_crypto", NSS_IPSECMGR_PRINT_DWORD},
+};
+
+/*
+ * nss_ipsecmgr_ctx_stats_size()
+ * 	Calculate size of context stats
+ */
+static ssize_t nss_ipsecmgr_ctx_stats_size(void)
+{
+	const struct nss_ipsecmgr_print *prn = ipsecmgr_print_ctx_stats;
+	ssize_t len = NSS_IPSECMGR_CTX_PRINT_EXTRA;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ipsecmgr_print_ctx_stats); i++, prn++)
+		len += strlen(prn->str) + prn->var_size;
+
+	prn = ipsecmgr_print_ctx_host_stats;
+
+	len += NSS_IPSECMGR_CTX_PRINT_EXTRA;
+	for (i = 0; i < ARRAY_SIZE(ipsecmgr_print_ctx_host_stats); i++, prn++)
+		len += strlen(prn->str) + prn->var_size;
+
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_ctx_print_len()
+ * 	Return the length of context stats
+ */
+static ssize_t nss_ipsecmgr_ctx_print_len(struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_ctx *ctx = container_of(ref, struct nss_ipsecmgr_ctx, ref);
+	return ctx->state.print_len;
+}
+
+/*
+ * nss_ipsecmgr_ctx_print()
+ * 	Print context statistics
+ */
+static ssize_t nss_ipsecmgr_ctx_print(struct nss_ipsecmgr_ref *ref, char *buf)
+{
+	struct nss_ipsecmgr_ctx *ctx = container_of(ref, struct nss_ipsecmgr_ctx, ref);
+	const struct nss_ipsecmgr_print *prn = ipsecmgr_print_ctx_stats;
+	ssize_t max_len = ctx->state.print_len;
+	uint64_t *stats_word = (uint64_t *)&ctx->stats;
+	ssize_t len;
+	int i;
+
+	/*
+	 * This expects a strict order as per the stats structure
+	 */
+	len = snprintf(buf, max_len, "---- Context -----\n");
+	len += snprintf(buf + len, max_len - len, "stats: {\n");
+
+	for (i = 0; i < ARRAY_SIZE(ipsecmgr_print_ctx_stats); i++, prn++)
+		len += snprintf(buf + len, max_len - len, "%s: %llu\n", prn->str, *stats_word++);
+
+	len += snprintf(buf + len, max_len - len, "}\n");
+
+	stats_word = (uint64_t *)&ctx->hstats;
+	len += snprintf(buf + len, max_len - len, "Host stats: {\n");
+	prn = ipsecmgr_print_ctx_host_stats;
+
+	for (i = 0; i < ARRAY_SIZE(ipsecmgr_print_ctx_host_stats); i++, prn++)
+		len += snprintf(buf + len, max_len - len, "%s: %llu\n", prn->str, *stats_word++);
+
+	len += snprintf(buf + len, max_len - len, "}\n");
+
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_ctx_read()
+ *	Read context info
+ */
+static ssize_t nss_ipsecmgr_ctx_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	struct nss_ipsecmgr_ctx *ctx = fp->private_data;
+	ssize_t print_len = ctx->state.stats_len;
+	ssize_t len = 0, max_len;
+	char *buf;
+
+	buf = vzalloc(print_len);
+	if (!buf) {
+		nss_ipsecmgr_warn("%px: failed to allocate print buffer (req:%zd)", ctx, print_len);
+		return 0;
+	}
+
+	read_lock_bh(&ipsecmgr_drv->lock);
+	max_len = nss_ipsecmgr_ref_print_len(&ctx->ref);
+	if (max_len > print_len) {
+		read_unlock_bh(&ipsecmgr_drv->lock);
+		len += snprintf(buf, print_len, "print buffer size error (need:%zd), retry", max_len);
+		ctx->state.stats_len = max_len;
+		goto done;
+	}
+
+	/*
+	 * Walk the context reference tree and retrieve stats
+	 */
+	len = nss_ipsecmgr_ref_print(&ctx->ref, buf);
+	read_unlock_bh(&ipsecmgr_drv->lock);
+
+done:
+	len = simple_read_from_buffer(ubuf, sz, ppos, buf, len);
+	vfree(buf);
+
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_ctx_notify_ipv4()
+ * 	Notify Linux by route lookup for destination
+ */
+static void nss_ipsecmgr_ctx_notify_ipv4(struct sk_buff *skb, struct nss_ipsecmgr_ctx *ctx)
+{
+	struct iphdr *iph = ip_hdr(skb);
+	struct dst_entry *dst;
+	struct rtable *rt;
+
+	if (skb->dev != ipsecmgr_drv->dev)
+		goto notify;
+
+	/*
+	 * If, we could not find the flow then this must be a new
+	 * flow that coming in for the first time. We should query
+	 * the Linux to see the associated NETDEV
+	 */
+	rt = ip_route_output(&init_net, iph->saddr, 0, 0, 0);
+	if (IS_ERR(rt)) {
+		dev_kfree_skb_any(skb);
+		ctx->hstats.v4_notify_drop++;
+		return;
+	}
+
+	dst = (struct dst_entry *)rt;
+	skb->dev = dst->dev;
+	dst_release(dst);
+
+	skb->pkt_type = PACKET_HOST;
+	skb->protocol = htons(ETH_P_IP);
+
+notify:
+	ctx->hstats.v4_notify++;
+	netif_receive_skb(skb);
+}
+
+/*
+ * nss_ipsecmgr_ctx_route_ipv4()
+ *	Send IPv4 packet for routing
+ */
+static void nss_ipsecmgr_ctx_route_ipv4(struct sk_buff *skb, struct nss_ipsecmgr_ctx *ctx)
+{
+	struct iphdr *iph = ip_hdr(skb);
+	struct rtable *rt;
+
+	rt = ip_route_output(&init_net, iph->daddr, iph->saddr, 0, 0);
+	if (unlikely(IS_ERR(rt))) {
+		nss_ipsecmgr_warn("%pK: No route, drop packet.\n", skb);
+		dev_kfree_skb_any(skb);
+		ctx->hstats.v4_route_drop++;
+		return;
+	}
+
+	/*
+	 * Sets the 'dst' entry for SKB and sends the packet out directly to the physical
+	 * device associated with the IPsec tunnel interface.
+	 */
+	skb_dst_set(skb, &rt->dst);
+	skb->ip_summed = CHECKSUM_COMPLETE;
+
+	ctx->hstats.v4_route++;
+
+	ip_local_out(&init_net, NULL, skb);
+}
+
+/*
+ * nss_ipsecmgr_ctx_notify_ipv6()
+ * 	Notify Linux by route lookup for destination
+ */
+static void nss_ipsecmgr_ctx_notify_ipv6(struct sk_buff *skb, struct nss_ipsecmgr_ctx *ctx)
+{
+	struct ipv6hdr *ip6h = ipv6_hdr(skb);
+	struct dst_entry *dst;
+	struct flowi6 fl6;
+
+	if (skb->dev != ipsecmgr_drv->dev)
+		goto notify;
+
+	/*
+	 * If, we could not find the flow then this must be a new
+	 * flow that coming in for the first time. We should query
+	 * the Linux to see the associated NETDEV
+	 */
+	memset(&fl6, 0, sizeof(fl6));
+	memcpy(&fl6.daddr, &ip6h->saddr, sizeof(fl6.daddr));
+
+	dst = ip6_route_output(&init_net, NULL, &fl6);
+	if (IS_ERR(dst)) {
+		dev_kfree_skb_any(skb);
+		ctx->hstats.v6_notify_drop++;
+		return;
+	}
+
+	skb->dev = dst->dev;
+	dst_release(dst);
+
+	skb->pkt_type = PACKET_HOST;
+	skb->protocol = htons(ETH_P_IPV6);
+
+notify:
+	ctx->hstats.v6_notify++;
+	netif_receive_skb(skb);
+}
+
+/*
+ * nss_ipsecmgr_ctx_route_ipv6()
+ *	Send IPv6 packet for routing
+ */
+static void nss_ipsecmgr_ctx_route_ipv6(struct sk_buff *skb, struct nss_ipsecmgr_ctx *ctx)
+{
+	struct ipv6hdr *ip6h = ipv6_hdr(skb);
+	struct dst_entry *dst;
+	struct flowi6 fl6;
+
+	memset(&fl6, 0, sizeof(fl6));
+	memcpy(&fl6.daddr, &ip6h->daddr, sizeof(fl6.daddr));
+	memcpy(&fl6.saddr, &ip6h->saddr, sizeof(fl6.saddr));
+
+	dst = ip6_route_output(&init_net, NULL, &fl6);
+	if (unlikely(IS_ERR(dst))) {
+		nss_ipsecmgr_warn("%pK: No route, drop packet.\n", skb);
+		dev_kfree_skb_any(skb);
+
+		ctx->hstats.v6_notify_drop++;
+		return;
+	}
+
+	/*
+	 * Sets the 'dst' entry for SKB and sends the packet out directly to the physical
+	 * device associated with the IPsec tunnel interface.
+	 */
+	skb_dst_set(skb, dst);
+	skb->ip_summed = CHECKSUM_COMPLETE;
+
+	ctx->hstats.v6_route++;
+
+	ip6_local_out(&init_net, NULL, skb);
+}
+
+/*
+ * nss_ipsecmgr_ctx_del_ref()
+ * 	Delete context from context list
+ */
+static void nss_ipsecmgr_ctx_del_ref(struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_ctx *ctx = container_of(ref, struct nss_ipsecmgr_ctx, ref);
+	list_del_init(&ctx->list);
+}
+
+/*
+ * nss_ipsecmgr_ctx_free_ref()
+ * 	Free context
+ */
+static void nss_ipsecmgr_ctx_free_ref(struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_ctx *ctx = container_of(ref, struct nss_ipsecmgr_ctx, ref);
+	enum nss_dynamic_interface_type di_type = ctx->state.di_type;
+	bool status;
+
+	status = nss_ipsec_cmn_unregister_if(ctx->ifnum);
+	if (!status) {
+		nss_ipsecmgr_warn("%px: Failed to unregister, di_type(%u), I/F(%u)", ctx, di_type, ctx->ifnum);
+		return;
+	}
+
+	nss_ipsecmgr_ctx_free(ctx);
+}
+
+/*
+ * file operation structure instance
+ */
+const struct file_operations ipsecmgr_ctx_file_ops = {
+	.open = simple_open,
+	.llseek = default_llseek,
+	.read = nss_ipsecmgr_ctx_read,
+};
+
+/*
+ * nss_ipsecmgr_ctx_rx_redir()
+ *	NSS IPsec manager device receive function
+ */
+void nss_ipsecmgr_ctx_rx_redir(struct net_device *dev, struct sk_buff *skb,
+				__attribute__((unused))struct napi_struct *napi)
+{
+	void (*forward_fn)(struct sk_buff *skb, struct nss_ipsecmgr_ctx *ctx) = NULL;
+	struct nss_ipsec_cmn_sa_tuple sa_tuple = {0};
+	struct nss_ipsecmgr_tunnel *tun;
+	struct nss_ipsecmgr_sa *sa;
+	struct nss_ipsecmgr_ctx *ctx;
+	int tunnel_id;
+
+	ctx = nss_ipsecmgr_ctx_find(netdev_priv(dev), NSS_IPSEC_CMN_CTX_TYPE_REDIR);
+	if (!ctx) {
+		dev_kfree_skb_any(skb);
+		nss_ipsecmgr_warn("%px: ctx is NULL", dev);
+		return;
+	}
+
+	ctx->hstats.redir_exp++;
+
+	skb_reset_mac_header(skb);
+	skb_reset_network_header(skb);
+
+	/*
+	 * Set the default values
+	 */
+	skb->dev = dev;
+	skb->pkt_type = PACKET_HOST;
+	skb->skb_iif = skb->dev->ifindex;
+
+	switch (ip_hdr(skb)->version) {
+	case IPVERSION:
+	{
+		struct iphdr *iph = ip_hdr(skb);
+		struct udphdr *udph;
+
+		skb->protocol = ETH_P_IP;
+
+		/*
+		 * This will happen for exception after de-capsulation.
+		 */
+		if ((iph->protocol != IPPROTO_ESP) && (iph->protocol != IPPROTO_UDP)) {
+			nss_ipsecmgr_ctx_notify_ipv4(skb, ctx);
+			return;
+		}
+
+		/*
+		 * Note: For outer flows check if the SA entry is present.
+		 * This will happen for exception after encapsulation
+		 */
+		if (iph->protocol == IPPROTO_ESP) {
+			nss_ipsecmgr_sa_ipv4_outer2tuple(iph, &sa_tuple);
+
+			read_lock(&ipsecmgr_drv->lock);
+			sa = nss_ipsecmgr_sa_find(ipsecmgr_drv->sa_db, &sa_tuple);
+			if (!sa) {
+				read_unlock(&ipsecmgr_drv->lock);
+				dev_kfree_skb_any(skb);
+
+				ctx->hstats.redir_fail_sa++;
+				return;
+			}
+
+			tunnel_id = sa->tunnel_id;
+			read_unlock(&ipsecmgr_drv->lock);
+			forward_fn = nss_ipsecmgr_ctx_route_ipv4;
+			break;
+		}
+
+		/*
+		 * UDP NAT-T is for outer processing otherwise inner processing
+		 */
+		udph = (struct udphdr *)((uint8_t *)iph + sizeof(*iph));
+		if (udph->dest != ntohs(NSS_IPSECMGR_NATT_PORT_DATA)) {
+			nss_ipsecmgr_ctx_notify_ipv4(skb, ctx);
+			return;
+		}
+
+		nss_ipsecmgr_sa_ipv4_outer2tuple(iph, &sa_tuple);
+
+		read_lock(&ipsecmgr_drv->lock);
+		sa = nss_ipsecmgr_sa_find(ipsecmgr_drv->sa_db, &sa_tuple);
+		if (!sa) {
+			read_unlock(&ipsecmgr_drv->lock);
+			dev_kfree_skb_any(skb);
+
+			write_lock_bh(&ipsecmgr_drv->lock);
+			ctx->hstats.redir_fail_sa++;
+			write_unlock_bh(&ipsecmgr_drv->lock);
+
+			return;
+		}
+
+		tunnel_id = sa->tunnel_id;
+		read_unlock(&ipsecmgr_drv->lock);
+		forward_fn = nss_ipsecmgr_ctx_route_ipv4;
+		break;
+	}
+
+	case 6:
+	{
+		struct ipv6hdr *ip6h = ipv6_hdr(skb);
+		skb->protocol = ETH_P_IPV6;
+
+		if (ip6h->nexthdr == IPPROTO_ESP) {
+			nss_ipsecmgr_sa_ipv6_outer2tuple(ip6h, &sa_tuple);
+
+			read_lock(&ipsecmgr_drv->lock);
+			sa = nss_ipsecmgr_sa_find(ipsecmgr_drv->sa_db, &sa_tuple);
+			if (!sa) {
+				read_unlock(&ipsecmgr_drv->lock);
+				dev_kfree_skb_any(skb);
+
+				ctx->hstats.redir_fail_sa++;
+
+				return;
+			}
+
+			tunnel_id = sa->tunnel_id;
+			read_unlock(&ipsecmgr_drv->lock);
+			forward_fn = nss_ipsecmgr_ctx_route_ipv6;
+			break;
+		}
+
+		nss_ipsecmgr_ctx_notify_ipv6(skb, ctx);
+		return;
+	}
+
+	default:
+		nss_ipsecmgr_warn("%px: non IP packet received", dev);
+		ctx->hstats.redir_exp_drop++;
+
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	/*
+	 * Use the tunnel-ID to find the associated device
+	 */
+	dev = dev_get_by_index(&init_net, tunnel_id);
+	if (!dev) {
+		dev_kfree_skb_any(skb);
+		ctx->hstats.redir_fail_dev++;
+		return;
+	}
+
+	/*
+	 * Reset SKB fields with the actual values
+	 */
+	tun = netdev_priv(dev);
+	skb->dev = tun->cb.skb_dev;
+	skb->pkt_type = PACKET_HOST;
+	skb->skb_iif = skb->dev->ifindex;
+	dev_put(dev);
+
+	/*
+	 * If, data callback is available then send the packet to the
+	 * callback function
+	 */
+	if (tun->cb.except_cb) {
+		tun->cb.except_cb(tun->cb.app_data, skb);
+		ctx->hstats.redir_cb++;
+		return;
+	}
+
+	/*
+	 * Indicate up the stack
+	 */
+	forward_fn(skb, ctx);
+	return;
+}
+
+/*
+ * nss_ipsecmgr_ctx_rx_outer()
+ *	Process outer exception from NSS
+ */
+void nss_ipsecmgr_ctx_rx_outer(struct net_device *dev, struct sk_buff *skb,
+				__attribute__((unused)) struct napi_struct *napi)
+{
+	struct nss_ipsecmgr_tunnel *tun = netdev_priv(dev);
+	struct nss_ipsecmgr_ctx *ctx;
+	skb_reset_mac_header(skb);
+	skb_reset_network_header(skb);
+
+	skb->dev = tun->cb.skb_dev;
+	skb->skb_iif = skb->dev->ifindex;
+
+	ctx = nss_ipsecmgr_ctx_find(netdev_priv(dev), NSS_IPSEC_CMN_CTX_TYPE_OUTER);
+	if (!ctx) {
+		nss_ipsecmgr_warn("%px: Could not find ctx", dev);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	ctx->hstats.outer_exp++;
+
+	/*
+	 * Reaching this point means the outer ECM rule is non-existent
+	 * whereas the IPsec rules are still present in FW. So, this is an ESP
+	 * encapsulated packet that has been exception to host from NSS.
+	 * We can send it to Linux IP stack for further routing.
+	 */
+	switch (ip_hdr(skb)->version) {
+	case IPVERSION: {
+		struct iphdr *iph = ip_hdr(skb);
+		skb->protocol = cpu_to_be16(ETH_P_IP);
+
+		if ((iph->protocol != IPPROTO_UDP) && (iph->protocol != IPPROTO_ESP)) {
+			nss_ipsecmgr_warn("%px: Unsupported IPv4 protocol(%u)", dev, iph->protocol);
+			dev_kfree_skb_any(skb);
+
+			ctx->hstats.outer_exp_drop++;
+			return;
+		}
+
+		skb_set_transport_header(skb, sizeof(*iph));
+		if (tun->cb.except_cb) {
+			tun->cb.except_cb(tun->cb.app_data, skb);
+			ctx->hstats.outer_cb++;
+			return;
+		}
+		nss_ipsecmgr_ctx_route_ipv4(skb, ctx);
+		return;
+	}
+
+	case 6: {
+		struct ipv6hdr *ip6h = ipv6_hdr(skb);
+		skb->protocol = cpu_to_be16(ETH_P_IPV6);
+
+		if (ip6h->nexthdr != IPPROTO_ESP) {
+			nss_ipsecmgr_warn("%px: unsupported ipv6 next_hdr(%u)", dev, ip6h->nexthdr);
+			dev_kfree_skb_any(skb);
+
+			ctx->hstats.outer_exp_drop++;
+			return;
+		}
+
+		skb_set_transport_header(skb, sizeof(*ip6h));
+		if (tun->cb.except_cb) {
+			tun->cb.except_cb(tun->cb.app_data, skb);
+			ctx->hstats.outer_cb++;
+			return;
+		}
+		nss_ipsecmgr_ctx_route_ipv6(skb, ctx);
+		return;
+	}
+
+	default:
+		nss_ipsecmgr_warn("%px: non ip packet received after decapsulation", dev);
+		ctx->hstats.outer_exp_drop++;
+
+		dev_kfree_skb_any(skb);
+		return;
+	}
+}
+
+/*
+ * nss_ipsecmgr_ctx_rx_inner()
+ * 	Process inner exception from NSS
+ */
+void nss_ipsecmgr_ctx_rx_inner(struct net_device *dev, struct sk_buff *skb,
+				__attribute__((unused)) struct napi_struct *napi)
+{
+	struct nss_ipsecmgr_tunnel *tun = netdev_priv(dev);
+	struct nss_ipsecmgr_ctx *ctx;
+
+	ctx = nss_ipsecmgr_ctx_find(netdev_priv(dev), NSS_IPSEC_CMN_CTX_TYPE_INNER);
+	if (!ctx) {
+		nss_ipsecmgr_warn("%px: Could not find ctx", dev);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	ctx->hstats.inner_exp++;
+
+	skb_reset_mac_header(skb);
+	skb_reset_network_header(skb);
+
+	switch (ip_hdr(skb)->version) {
+	case IPVERSION:
+		skb->protocol = cpu_to_be16(ETH_P_IP);
+		skb_set_transport_header(skb, sizeof(struct iphdr));
+		break;
+
+	case 6:
+		skb->protocol = cpu_to_be16(ETH_P_IPV6);
+		skb_set_transport_header(skb, sizeof(struct ipv6hdr));
+		break;
+
+	default:
+		nss_ipsecmgr_warn("%px: Invalid IP header received for rx_inner", tun);
+		dev_kfree_skb_any(skb);
+
+		ctx->hstats.inner_exp_drop++;
+
+		return;
+	}
+
+	skb->dev = tun->cb.skb_dev;
+	skb->pkt_type = PACKET_HOST;
+	skb->skb_iif = skb->dev->ifindex;
+
+	/*
+	 * If, data callback is available then send the packet to the
+	 * callback funtion
+	 */
+	if (tun->cb.data_cb) {
+		tun->cb.data_cb(tun->cb.app_data, skb);
+		ctx->hstats.inner_cb++;
+		return;
+	}
+
+	netif_receive_skb(skb);
+}
+
+/*
+ * nss_ipsecmgr_ctx_rx_stats()
+ *	Asynchronous event for reception of stat
+ */
+void nss_ipsecmgr_ctx_rx_stats(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_ipsec_cmn_msg *nicm = (struct nss_ipsec_cmn_msg *)ncm;
+	struct nss_ipsecmgr_tunnel *tun;
+	struct nss_ipsecmgr_ctx *ctx;
+
+	ctx = app_data;
+	tun = ctx->tun;
+
+	switch (ncm->type) {
+
+	case NSS_IPSEC_CMN_MSG_TYPE_SA_SYNC: {
+		struct nss_ipsec_cmn_sa_sync *sync = &nicm->msg.sa_sync;
+		struct list_head *sa_db = ipsecmgr_drv->sa_db;
+		struct nss_ipsecmgr_event event = {0};
+		nss_ipsecmgr_event_callback_t ev_cb;
+		struct nss_ipsecmgr_sa *sa;
+		void *app_data;
+
+		event.type = NSS_IPSECMGR_EVENT_SA_STATS;
+		write_lock(&ipsecmgr_drv->lock);
+
+		sa = nss_ipsecmgr_sa_find(sa_db, &sync->sa_tuple);
+		if (!sa) {
+			write_unlock(&ipsecmgr_drv->lock);
+			break;
+		}
+
+		nss_ipsecmgr_sa_sync_state(sa, sync);
+
+		ev_cb = sa->cb.event_cb;
+		if (ev_cb) {
+			nss_ipsecmgr_sa_sync2stats(sa, sync, &event.data.stats);
+			app_data = sa->cb.app_data;
+		}
+
+		write_unlock(&ipsecmgr_drv->lock);
+
+		if (ev_cb)
+			ev_cb(app_data, &event);
+		break;
+	}
+
+	case NSS_IPSEC_CMN_MSG_TYPE_CTX_SYNC: {
+		struct nss_ipsec_cmn_ctx_sync *ctx_sync = &nicm->msg.ctx_sync;
+		uint32_t *msg_stats = (uint32_t *)&ctx_sync->stats;
+		uint64_t *ctx_stats = (uint64_t *)&ctx->stats;
+		int num;
+
+		write_lock(&ipsecmgr_drv->lock);
+
+		for (num = 0; num < sizeof(ctx->stats)/sizeof(*ctx_stats); num++) {
+			ctx_stats[num] += msg_stats[num];
+		}
+
+		write_unlock(&ipsecmgr_drv->lock);
+		break;
+	}
+
+	default:
+		nss_ipsecmgr_info("%px: unhandled ipsec message type(%u)", nicm, nicm->cm.type);
+		break;
+	}
+
+}
+
+/*
+ * nss_ipsecmgr_ctx_stats_read()
+ * 	Read context stats into Linux device stats
+ */
+void nss_ipsecmgr_ctx_stats_read(struct nss_ipsecmgr_ctx *ctx, struct rtnl_link_stats64 *dev_stats)
+{
+	struct nss_ipsecmgr_ctx_stats_priv *ctx_stats = &ctx->stats;
+	uint64_t *packets, *bytes, *dropped;
+	int i;
+
+	switch (ctx->state.type) {
+	case NSS_IPSEC_CMN_CTX_TYPE_INNER:
+	case NSS_IPSEC_CMN_CTX_TYPE_MDATA_INNER:
+		packets = &dev_stats->tx_packets;
+		bytes = &dev_stats->tx_bytes;
+		dropped = &dev_stats->tx_dropped;
+		break;
+
+	case NSS_IPSEC_CMN_CTX_TYPE_OUTER:
+	case NSS_IPSEC_CMN_CTX_TYPE_MDATA_OUTER:
+		packets = &dev_stats->rx_packets;
+		bytes = &dev_stats->rx_bytes;
+		dropped = &dev_stats->rx_dropped;
+		break;
+	default:
+		return;
+	}
+
+	*packets += ctx_stats->rx_packets;
+	*bytes += ctx_stats->rx_bytes;
+	*dropped += (ctx_stats->rx_packets - ctx_stats->tx_packets);
+
+	for (i = 0; i < ARRAY_SIZE(ctx_stats->rx_dropped); i++) {
+		*dropped += ctx_stats->rx_dropped[i];
+	}
+}
+
+/*
+ * nss_ipsecmgr_ctx_find()
+ * 	Find the context for the given type
+ */
+struct nss_ipsecmgr_ctx *nss_ipsecmgr_ctx_find(struct nss_ipsecmgr_tunnel *tun, enum nss_ipsec_cmn_ctx_type type)
+{
+	struct list_head *head = &tun->ctx_db;
+	struct nss_ipsecmgr_ctx *ctx;
+
+	/*
+	 * Linux does not provide any specific API(s) to test for RW locks. The caller
+	 * being internal is assumed to hold write lock before initiating this.
+	 */
+	list_for_each_entry(ctx, head, list) {
+		if (ctx->state.type == type)
+			return ctx;
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_ipsecmgr_ctx_find_by_sa()
+ *	Find the context for the given type
+ */
+struct nss_ipsecmgr_ctx *nss_ipsecmgr_ctx_find_by_sa(struct nss_ipsecmgr_tunnel *tun, enum nss_ipsecmgr_sa_type sa_type)
+{
+	struct list_head *head = &tun->ctx_db;
+	enum nss_ipsec_cmn_ctx_type ctx_type;
+	struct nss_ipsecmgr_ctx *ctx;
+
+	switch (sa_type) {
+	case NSS_IPSECMGR_SA_TYPE_ENCAP:
+		ctx_type = NSS_IPSEC_CMN_CTX_TYPE_INNER;
+		break;
+
+	case NSS_IPSECMGR_SA_TYPE_DECAP:
+		ctx_type = NSS_IPSEC_CMN_CTX_TYPE_OUTER;
+		break;
+
+	default:
+		nss_ipsecmgr_warn("%px: Unsupported SA type(%u)", tun, sa_type);
+		return NULL;
+	}
+
+	/*
+	 * Linux does not provide any specific API(s) to test for RW locks. The caller
+	 * being internal is assumed to hold write lock before initiating this.
+	 */
+	list_for_each_entry(ctx, head, list) {
+		if (ctx->state.type == ctx_type) {
+			return ctx;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_ipsecmgr_ctx_attach()
+ *	Attach context to the database
+ */
+void nss_ipsecmgr_ctx_attach(struct list_head *db, struct nss_ipsecmgr_ctx *ctx)
+{
+	struct nss_ipsecmgr_tunnel *tun = ctx->tun;
+
+	list_add(&ctx->list, db);
+
+	/*
+	 * Add ctx->ref to tun->ref
+	 */
+	write_lock_bh(&ipsecmgr_drv->lock);
+	nss_ipsecmgr_ref_add(&ctx->ref, &tun->ref);
+	write_unlock_bh(&ipsecmgr_drv->lock);
+}
+
+/*
+ * nss_ipsecmgr_ctx_config()
+ * 	Configure context
+ */
+bool nss_ipsecmgr_ctx_config(struct nss_ipsecmgr_ctx *ctx)
+{
+	enum nss_ipsec_cmn_msg_type msg_type = NSS_IPSEC_CMN_MSG_TYPE_CTX_CONFIG;
+	struct nss_ipsec_cmn_ctx *ctx_msg;
+	struct nss_ipsec_cmn_msg nicm;
+	nss_tx_status_t status;
+
+	memset(&nicm, 0, sizeof(struct nss_ipsec_cmn_msg));
+
+	ctx_msg = &nicm.msg.ctx;
+	ctx_msg->type = ctx->state.type;
+	ctx_msg->except_ifnum = ctx->state.except_ifnum;
+	ctx_msg->sibling_ifnum = ctx->state.sibling_ifnum;
+
+	status = nss_ipsec_cmn_tx_msg_sync(ctx->nss_ctx, ctx->ifnum, msg_type, sizeof(*ctx_msg), &nicm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ipsecmgr_warn("%px: Failed to configure the context (ctx_type:%u),(tx_status:%d),(error:%x)",
+				ctx, ctx->state.type, status, nicm.cm.error);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_ipsecmgr_ctx_free()
+ * 	Free context
+ */
+void nss_ipsecmgr_ctx_free(struct nss_ipsecmgr_ctx *ctx)
+{
+	nss_dynamic_interface_dealloc_node(ctx->ifnum, ctx->state.di_type);
+	kfree(ctx);
+}
+
+/*
+ * nss_ipsecmgr_ctx_alloc()
+ * 	Allocate context for type and dynamic interface(s)
+ */
+struct nss_ipsecmgr_ctx *nss_ipsecmgr_ctx_alloc(struct nss_ipsecmgr_tunnel *tun,
+						enum nss_ipsec_cmn_ctx_type ctx_type,
+						enum nss_dynamic_interface_type di_type,
+						nss_ipsec_cmn_data_callback_t rx_data,
+						nss_ipsec_cmn_msg_callback_t rx_stats,
+						uint32_t features)
+{
+	struct nss_ipsecmgr_ctx *ctx;
+	int32_t ifnum;
+
+	ctx = kzalloc(sizeof(*ctx), in_atomic() ? GFP_ATOMIC : GFP_KERNEL);
+	if (!ctx) {
+		nss_ipsecmgr_warn("%px: failed to allocate context memory", tun);
+		return NULL;
+	}
+
+	nss_ipsecmgr_trace("%px: Allocating dynamic interface type(%d)", ctx, di_type);
+
+	ctx->tun = tun;
+	ctx->state.type = ctx_type;
+	ctx->state.di_type = di_type;
+
+	ifnum = nss_dynamic_interface_alloc_node(di_type);
+	if (ifnum < 0) {
+		nss_ipsecmgr_warn("%px: failed to allocate dynamic interface(%d)", tun, di_type);
+		kfree(ctx);
+		return NULL;
+	}
+
+	ctx->ifnum = ifnum;
+	ctx->state.stats_len = ctx->state.print_len = nss_ipsecmgr_ctx_stats_size();
+	nss_ipsecmgr_ref_init(&ctx->ref, nss_ipsecmgr_ctx_del_ref, nss_ipsecmgr_ctx_free_ref);
+	nss_ipsecmgr_ref_init_print(&ctx->ref, nss_ipsecmgr_ctx_print_len, nss_ipsecmgr_ctx_print);
+
+	INIT_LIST_HEAD(&ctx->list);
+
+	ctx->nss_ctx = nss_ipsec_cmn_register_if(ctx->ifnum, tun->dev, rx_data, rx_stats, features, di_type, ctx);
+	if (!ctx->nss_ctx) {
+		nss_ipsecmgr_warn("%px: failed to register dynamic interface(%d, %d)", ctx, di_type, ctx->ifnum);
+		nss_dynamic_interface_dealloc_node(ctx->ifnum, di_type);
+		kfree(ctx);
+		return NULL;
+	}
+
+	return ctx;
+}
diff --git a/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_ctx.h b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_ctx.h
new file mode 100644
index 0000000..bf66219
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_ctx.h
@@ -0,0 +1,153 @@
+/*
+ * ********************************************************************************
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ **********************************************************************************
+ */
+
+#ifndef __NSS_IPSECMGR_CTX_H
+#define __NSS_IPSECMGR_CTX_H
+
+#define NSS_IPSECMGR_CTX_PRINT_EXTRA 64
+#define NSS_IPSECMGR_CTX_PRINT_LEN (PAGE_SIZE * NSS_IPSECMGR_PRINT_PAGES)
+#define NSS_IPSECMGR_CTX_FREE_TIMEOUT msecs_to_jiffies(100) /* msecs */
+
+/*
+ * Context host statistics
+ */
+struct nss_ipsecmgr_ctx_host_stats {
+	uint64_t v4_notify;		/* Host processed Exceptioned IPv4 inner packet */
+	uint64_t v4_notify_drop;	/* Host processed and dropped IPv4 inner packet */
+	uint64_t v4_route;		/* Host processed IPv4 outer packet */
+	uint64_t v4_route_drop;		/* Host processed and dropped IPv4 outer packet */
+	uint64_t v6_notify;		/* Host processed Exceptioned IPv6 inner packet */
+	uint64_t v6_notify_drop;	/* Host processed and dropped IPv6 inner packet */
+	uint64_t v6_route;		/* Host processed IPv6 outer packet */
+	uint64_t v6_route_drop;		/* Host processed and dropped IPv6 outer packet */
+	uint64_t inner_exp;		/* Host processed inner IPv4 exceptioned packet */
+	uint64_t inner_exp_drop;	/* Host processed and dropped inner exceptioned packet */
+	uint64_t inner_cb;		/* Number of times data call back called for inner packet */
+	uint64_t inner_fail_dev;	/* Failed to find netdevice for inner packet */
+	uint64_t inner_fail_sa;		/* Failed to find SA for inner packet */
+	uint64_t inner_fail_flow;	/* Failed to find flow for inner packet */
+	uint64_t outer_exp;		/* Host processed inner IPv6 exceptioned packet */
+	uint64_t outer_exp_drop;	/* Host processed and dropped inner IPv6 exceptioned packet */
+	uint64_t outer_cb;		/* Number of times exception call back called for outer packet */
+	uint64_t outer_fail_dev;	/* Failed to find netdevice for inner packet */
+	uint64_t outer_fail_sa;		/* Failed to find SA for outer packet */
+	uint64_t outer_fail_flow;	/* Failed to find flow for outer packet */
+	uint64_t redir_exp;		/* Redir exceptioned packet */
+	uint64_t redir_exp_drop;	/* Redir exceptioned and dropped */
+	uint64_t redir_cb;		/* Redir callback called */
+	uint64_t redir_fail_dev;	/* Failed to find netdevice */
+	uint64_t redir_fail_sa;		/* Failed to find SA */
+	uint64_t redir_fail_flow;	/* Failed to find flow */
+};
+
+/*
+ * Context statistics
+ */
+struct nss_ipsecmgr_ctx_stats_priv {
+	/* Packet counters */
+	uint64_t rx_packets;			/* Number of packets received. */
+	uint64_t rx_bytes;			/* Number of bytes received. */
+	uint64_t tx_packets;			/* Number of packets transmitted. */
+	uint64_t tx_bytes;			/* Number of bytes transmitted. */
+	uint64_t rx_dropped[NSS_MAX_NUM_PRI];	/* Packets dropped on receive due to queue full. */
+
+	/* Drop counters */
+	uint64_t exceptioned;		/* Exceptioned to host */
+	uint64_t linearized;		/* Linearized packets */
+	uint64_t redirected;		/* Redirected from inline */
+	uint64_t dropped;		/* Total dropped packets */
+	uint64_t fail_sa;		/* Failed to find SA */
+	uint64_t fail_flow;		/* Failed to find flow */
+	uint64_t fail_stats;		/* Failed to send statistics */
+	uint64_t fail_exception;	/* Failed to exception */
+	uint64_t fail_transform;	/* Failed to transform */
+	uint64_t fail_linearized;	/* Failed to linearized */
+	uint64_t fail_mdata_ver;	/* Invalid meta data version */
+	uint64_t fail_ctx_active;	/* Failed to queue as ctx is not active. */
+	uint64_t fail_pbuf_crypto;	/* Failed to allocate pbuf for crypto operation */
+	uint64_t fail_queue_crypto;	/* Failed to queue pbuf to crypto pnode */
+};
+
+/*
+ * Per context state
+ */
+struct nss_ipsecmgr_ctx_state {
+	ssize_t print_len;				/* Print buffer length */
+	ssize_t stats_len;				/* Total stats length */
+	uint32_t except_ifnum;				/* Exception interface number */
+	uint32_t sibling_ifnum;				/* Sibling interface number */
+	enum nss_ipsec_cmn_ctx_type type;		/* Type */
+	enum nss_dynamic_interface_type di_type;	/* Dynamic interface type */
+};
+
+/*
+ * IPsec manager Context (encap/decap/bounce)
+ */
+struct nss_ipsecmgr_ctx {
+	struct list_head list;				/* List node */
+	struct nss_ipsecmgr_ref ref;			/* Reference node */
+	struct nss_ipsecmgr_tunnel *tun;		/* IPsec tunnel */
+
+	uint32_t ifnum;					/* Interface number */
+	struct nss_ctx_instance *nss_ctx;		/* NSS context instance */
+
+	struct nss_ipsecmgr_ctx_state state;		/* Per context state */
+	struct nss_ipsecmgr_ctx_stats_priv stats;	/* Statistics */
+	struct nss_ipsecmgr_ctx_host_stats hstats;	/* Host statistics */
+};
+
+/*
+ * Set the exception interface number for context
+ */
+static inline void nss_ipsecmgr_ctx_set_except(struct nss_ipsecmgr_ctx *ctx, uint32_t except_ifnum)
+{
+	ctx->state.except_ifnum = except_ifnum;
+}
+
+/*
+ * Set the sibling interface number for context
+ */
+static inline void nss_ipsecmgr_ctx_set_sibling(struct nss_ipsecmgr_ctx *ctx, uint32_t sibling_ifnum)
+{
+	ctx->state.sibling_ifnum = sibling_ifnum;
+}
+
+extern const struct file_operations ipsecmgr_ctx_file_ops;
+
+/* API(s) for context specific operations */
+extern void nss_ipsecmgr_ctx_rx_stats(void *app_data, struct nss_cmn_msg *ncm);
+extern void nss_ipsecmgr_ctx_rx_redir(struct net_device *dev, struct sk_buff *skb, struct napi_struct *napi);
+extern void nss_ipsecmgr_ctx_rx_outer(struct net_device *dev, struct sk_buff *skb, struct napi_struct *napi);
+extern void nss_ipsecmgr_ctx_rx_inner(struct net_device *dev, struct sk_buff *skb, struct napi_struct *napi);
+
+extern void nss_ipsecmgr_ctx_attach(struct list_head *db, struct nss_ipsecmgr_ctx *ctx);
+extern bool nss_ipsecmgr_ctx_config(struct nss_ipsecmgr_ctx *ctx);
+extern void nss_ipsecmgr_ctx_free(struct nss_ipsecmgr_ctx *ctx);
+extern struct nss_ipsecmgr_ctx *nss_ipsecmgr_ctx_alloc(struct nss_ipsecmgr_tunnel *tun,
+							enum nss_ipsec_cmn_ctx_type ctx_type,
+							enum nss_dynamic_interface_type di_type,
+							nss_ipsec_cmn_data_callback_t rx_data,
+							nss_ipsec_cmn_msg_callback_t rx_stats,
+							uint32_t features);
+extern void nss_ipsecmgr_ctx_stats_read(struct nss_ipsecmgr_ctx *ctx, struct rtnl_link_stats64 *dev_stats);
+extern struct nss_ipsecmgr_ctx *nss_ipsecmgr_ctx_find(struct nss_ipsecmgr_tunnel *tun,
+							enum nss_ipsec_cmn_ctx_type type);
+extern struct nss_ipsecmgr_ctx *nss_ipsecmgr_ctx_find_by_sa(struct nss_ipsecmgr_tunnel *tun,
+							enum nss_ipsecmgr_sa_type sa_type);
+
+#endif /* !__NSS_IPSECMGR_CTX_H */
diff --git a/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_flow.c b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_flow.c
new file mode 100644
index 0000000..4d3619f
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_flow.c
@@ -0,0 +1,663 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTUOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/of.h>
+#include <linux/ipv6.h>
+#include <linux/skbuff.h>
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/netdevice.h>
+#include <linux/rtnetlink.h>
+#include <linux/etherdevice.h>
+#include <linux/vmalloc.h>
+#include <linux/debugfs.h>
+#include <linux/atomic.h>
+#include <net/protocol.h>
+#include <net/route.h>
+#include <net/ip6_route.h>
+
+#include <crypto/aead.h>
+#include <crypto/internal/hash.h>
+
+#include <nss_api_if.h>
+#include <nss_ipsec_cmn.h>
+#include <nss_ipsecmgr.h>
+
+#include "nss_ipsecmgr_ref.h"
+#include "nss_ipsecmgr_flow.h"
+#include "nss_ipsecmgr_sa.h"
+#include "nss_ipsecmgr_ctx.h"
+#include "nss_ipsecmgr_tunnel.h"
+#include "nss_ipsecmgr_priv.h"
+
+extern struct nss_ipsecmgr_drv *ipsecmgr_drv;
+
+/*
+ * Flow tuple print info
+ */
+static const struct nss_ipsecmgr_print ipsecmgr_print_flow_tuple[] = {
+	{"dest_ip", NSS_IPSECMGR_PRINT_IPADDR},
+	{"src_ip", NSS_IPSECMGR_PRINT_IPADDR},
+	{"spi", NSS_IPSECMGR_PRINT_WORD},
+	{"dst_port", NSS_IPSECMGR_PRINT_WORD},
+	{"src_port", NSS_IPSECMGR_PRINT_WORD},
+	{"user_pattern", NSS_IPSECMGR_PRINT_WORD},
+	{"protocol", NSS_IPSECMGR_PRINT_WORD},
+	{"ip_version", NSS_IPSECMGR_PRINT_WORD},
+};
+
+/*
+ * nss_ipsecmgr_flow_print_len()
+ * 	Print flow length
+ */
+static ssize_t nss_ipsecmgr_flow_print_len(struct nss_ipsecmgr_ref *ref)
+{
+	const struct nss_ipsecmgr_print *prn = ipsecmgr_print_flow_tuple;
+	ssize_t len = NSS_IPSECMGR_FLOW_PRINT_EXTRA;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ipsecmgr_print_flow_tuple); i++, prn++)
+		len += strlen(prn->str) + prn->var_size;
+
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_flow_print()
+ * 	Print flow
+ */
+static ssize_t nss_ipsecmgr_flow_print(struct nss_ipsecmgr_ref *ref, char *buf)
+{
+	struct nss_ipsecmgr_flow *flow = container_of(ref, struct nss_ipsecmgr_flow, ref);
+	const struct nss_ipsecmgr_print *prn = ipsecmgr_print_flow_tuple;
+	struct nss_ipsec_cmn_flow_tuple *tuple = &flow->state.tuple;
+	uint32_t dest_ip[4], src_ip[4];
+	ssize_t max_len, len = 0;
+
+	max_len = nss_ipsecmgr_flow_print_len(&flow->ref);
+	len += snprintf(buf + len, max_len - len, "Flow tuple: {");
+
+	switch (tuple->ip_ver) {
+	case IPVERSION:
+		len += snprintf(buf + len, max_len - len, "%s: %pI4h,", prn->str, tuple->dest_ip);
+		prn++;
+
+		len += snprintf(buf + len, max_len - len, "%s: %pI4h,", prn->str, tuple->src_ip);
+		prn++;
+
+		break;
+	case 6:
+		nss_ipsecmgr_hton_v6addr(src_ip, tuple->src_ip);
+		nss_ipsecmgr_hton_v6addr(dest_ip, tuple->dest_ip);
+
+		len += snprintf(buf + len, max_len - len, "%s: %pI6c,", prn->str, dest_ip);
+		prn++;
+
+		len += snprintf(buf + len, max_len - len, "%s: %pI6c,", prn->str, src_ip);
+		prn++;
+
+		break;
+	}
+
+	len += snprintf(buf + len, max_len - len, "%s: 0x%x,", prn->str, tuple->spi_index);
+	prn++;
+
+	len += snprintf(buf + len, max_len - len, "%s: %u,", prn->str, tuple->dst_port);
+	prn++;
+
+	len += snprintf(buf + len, max_len - len, "%s: %u,", prn->str, tuple->src_port);
+	prn++;
+
+	len += snprintf(buf + len, max_len - len, "%s: %u,", prn->str, tuple->user_pattern);
+	prn++;
+
+	len += snprintf(buf + len, max_len - len, "%s: %u,", prn->str, tuple->protocol);
+	prn++;
+
+	len += snprintf(buf + len, max_len - len, "%s: %u", prn->str, tuple->ip_ver);
+	prn++;
+
+	len += snprintf(buf + len, max_len - len, "}\n");
+
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_flow_update_db()
+ *	Add flow to DB.
+ */
+static bool nss_ipsecmgr_flow_update_db(struct nss_ipsecmgr_flow *flow)
+{
+	struct nss_ipsec_cmn_sa_tuple *sa_tuple = &flow->state.sa;
+	struct nss_ipsecmgr_sa *sa;
+	uint32_t hash_idx;
+
+	hash_idx = nss_ipsecmgr_flow_tuple2hash(&flow->state.tuple, NSS_IPSECMGR_FLOW_MAX);
+
+	write_lock(&ipsecmgr_drv->lock);
+	sa = nss_ipsecmgr_sa_find(ipsecmgr_drv->sa_db, sa_tuple);
+	if (!sa) {
+		write_unlock(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_trace("%px: failed to find SA during flow update", flow);
+		return false;
+	}
+
+	flow->sa = sa;
+	/*
+	 * Add reference of the flow to the SA associated with the outer.
+	 */
+	nss_ipsecmgr_ref_add(&flow->ref, &sa->ref);
+	list_add(&flow->list, &ipsecmgr_drv->flow_db[hash_idx]);
+	write_unlock(&ipsecmgr_drv->lock);
+	return true;
+}
+
+/*
+ * nss_ipsecmgr_flow_create_resp()
+ *	response for the flow message
+ */
+static void nss_ipsecmgr_flow_create_resp(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_ipsecmgr_flow *flow = app_data;
+
+	/*
+	 * If, NSS rejected the flow add then we will not
+	 * add it to our list
+	 */
+	if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+		nss_ipsecmgr_trace("%px: NSS response error (%u)", flow, ncm->error);
+		kfree(flow);
+		return;
+	}
+
+	if (!nss_ipsecmgr_flow_update_db(flow)) {
+		nss_ipsecmgr_trace("%px: failed to update flow in DB (%u)", flow, ncm->error);
+		kfree(flow);
+		return;
+	}
+
+	nss_ipsecmgr_trace("%px: Sucessfully updated flow in DB", flow);
+}
+
+/*
+ * nss_ipsecmgr_flow_free()
+ *	Free flow object
+ */
+static void nss_ipsecmgr_flow_free(struct nss_ipsecmgr_flow *flow)
+{
+	kfree(flow);
+}
+
+/*
+ * nss_ipsecmgr_flow_del_ref()
+ *	Unlink the flow entry
+ */
+static void nss_ipsecmgr_flow_del_ref(struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_flow *flow = container_of(ref, struct nss_ipsecmgr_flow, ref);
+
+	/*
+	 * Write lock needs to be held by the caller since flow db is
+	 * getting modified.
+	 */
+	nss_ipsecmgr_write_lock_is_held(&ipsecmgr_drv->lock);
+	list_del_init(&flow->list);
+}
+
+/*
+ * nss_ipsecmgr_flow_free_ref()
+ *	Free the flow entry
+ */
+static void nss_ipsecmgr_flow_free_ref(struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_flow *flow = container_of(ref, struct nss_ipsecmgr_flow, ref);
+	enum nss_ipsec_cmn_msg_type type = NSS_IPSEC_CMN_MSG_TYPE_FLOW_DESTROY;
+	struct nss_ipsec_cmn_msg nicm;
+	nss_tx_status_t status;
+
+	memset(&nicm, 0, sizeof(nicm));
+
+	memcpy(&nicm.msg.flow.flow_tuple, &flow->state.tuple, sizeof(nicm.msg.flow.flow_tuple));
+	memcpy(&nicm.msg.flow.sa_tuple, &flow->state.sa, sizeof(nicm.msg.flow.sa_tuple));
+
+	status = nss_ipsec_cmn_tx_msg_sync(flow->nss_ctx, flow->ifnum, type, sizeof(nicm.msg.flow), &nicm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ipsecmgr_info("%px: failed to send the flow message(%u)", flow, type);
+	}
+
+	if (nicm.cm.error != NSS_IPSEC_CMN_MSG_ERROR_NONE) {
+		nss_ipsecmgr_warn("%px: failed to free flow from NSS (%u)", flow, nicm.cm.error);
+	}
+
+	nss_ipsecmgr_flow_free(flow);
+}
+
+/*
+ * nss_ipsecmgr_flow_alloc()
+ *	Add a new flow to database
+ */
+static struct nss_ipsecmgr_flow *nss_ipsecmgr_flow_alloc(struct nss_ipsecmgr_sa *sa,
+							struct nss_ipsec_cmn_flow_tuple *flow_tuple,
+							struct nss_ipsec_cmn_sa_tuple *sa_tuple)
+{
+	struct nss_ipsecmgr_flow *flow = NULL;
+
+	flow = kzalloc(sizeof(*flow), GFP_ATOMIC);
+	if (!flow) {
+		write_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_info("%px: failed to allocate flow", sa);
+		return NULL;
+	}
+
+	/*
+	 * Initialize the flow entry
+	 */
+	flow->ifnum = sa->ifnum;
+	flow->nss_ctx = sa->nss_ctx;
+	flow->tunnel_id = sa->tunnel_id;
+
+	INIT_LIST_HEAD(&flow->list);
+	nss_ipsecmgr_ref_init(&flow->ref, nss_ipsecmgr_flow_del_ref, nss_ipsecmgr_flow_free_ref);
+	nss_ipsecmgr_ref_init_print(&flow->ref, nss_ipsecmgr_flow_print_len, nss_ipsecmgr_flow_print);
+
+	/*
+	 * Copy information received for flow creation
+	 */
+	memcpy(&flow->state.tuple, flow_tuple, sizeof(flow->state.tuple));
+	memcpy(&flow->state.sa, sa_tuple, sizeof(flow->state.sa));
+
+	return flow;
+}
+
+/*
+ * nss_ipsecmgr_flow_find()
+ *	Lookup flow_tuple in the flow data base
+ *
+ * Note: No locks are taken here; so it needs to be called with a read/write lock held.
+ */
+struct nss_ipsecmgr_flow *nss_ipsecmgr_flow_find(struct list_head *db, struct nss_ipsec_cmn_flow_tuple *tuple)
+{
+	uint32_t hash_idx = nss_ipsecmgr_flow_tuple2hash(tuple, NSS_IPSECMGR_FLOW_MAX);
+	struct list_head *head = &db[hash_idx];
+	struct nss_ipsecmgr_flow *flow;
+
+	/*
+	 * Linux does not provide any specific API(s) to test for RW locks. The caller
+	 * being internal is assumed to hold write lock before initiating this.
+	 */
+	list_for_each_entry(flow, head, list) {
+		if (nss_ipsecmgr_flow_tuple_match(&flow->state.tuple, tuple))
+			return flow;
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_ipsecmgr_flow_get_sa()
+ *	Lookup flow_tuple in flow database and return sa_tuple.
+ */
+nss_ipsecmgr_status_t nss_ipsecmgr_flow_get_sa(struct net_device *tun, struct nss_ipsecmgr_flow_tuple *flow_tuple,
+					struct nss_ipsecmgr_sa_tuple *sa_tuple)
+{
+	struct nss_ipsec_cmn_flow_tuple tuple;
+	struct nss_ipsecmgr_flow *flow;
+	struct nss_ipsecmgr_sa *sa;
+
+	nss_ipsecmgr_flow2tuple(flow_tuple, &tuple);
+	write_lock_bh(&ipsecmgr_drv->lock);
+
+	flow = nss_ipsecmgr_flow_find(ipsecmgr_drv->flow_db, &tuple);
+	if (!flow) {
+		write_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_trace("%px: Failed to find flow", tun);
+		return NSS_IPSECMGR_FAIL_FLOW;
+	}
+
+	sa = flow->sa;
+	if (!sa) {
+		write_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_error("%px: SA is not associated with flow", tun);
+		return NSS_IPSECMGR_INVALID_SA;
+	}
+
+	nss_ipsecmgr_sa_tuple2sa(&sa->state.tuple, sa_tuple);
+	write_unlock_bh(&ipsecmgr_drv->lock);
+
+	return NSS_IPSECMGR_OK;
+}
+EXPORT_SYMBOL(nss_ipsecmgr_flow_get_sa);
+
+/*
+ * nss_ipsecmgr_flow_del()
+ *	Delete a existing flow from the database
+ *
+ * Note: We will only delete the flow associated with the requested SA.
+ * If we donot find the association then the flow delete will not perform
+ * the delete
+ */
+void nss_ipsecmgr_flow_del(struct net_device *dev, struct nss_ipsecmgr_flow_tuple *f_tuple,
+				struct nss_ipsecmgr_sa_tuple *s_tuple)
+{
+	struct nss_ipsecmgr_tunnel *tun = netdev_priv(dev);
+	struct list_head *flow_db = ipsecmgr_drv->flow_db;
+	struct list_head *sa_db = ipsecmgr_drv->sa_db;
+	struct nss_ipsec_cmn_flow_tuple flow_tuple = {0};
+	struct nss_ipsec_cmn_sa_tuple sa_tuple = {0};
+	struct nss_ipsecmgr_flow *flow;
+	struct nss_ipsecmgr_sa *sa;
+
+	nss_ipsecmgr_flow2tuple(f_tuple, &flow_tuple);
+	nss_ipsecmgr_sa2tuple(s_tuple, &sa_tuple);
+
+	/*
+	 * Write lock needed here since Flow DB is looked up and removed
+	 * No one should be accessing flow at this point
+	 */
+	write_lock_bh(&ipsecmgr_drv->lock);
+
+	sa = nss_ipsecmgr_sa_find(sa_db, &sa_tuple);
+	if (!sa) {
+		write_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_warn("%px: failed to find SA during flow_del", tun);
+		return;
+	}
+
+	flow = nss_ipsecmgr_flow_find(flow_db, &flow_tuple);
+	if (!flow) {
+		write_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_warn("%px: failed to find flow for flow_del", tun);
+		return;
+	}
+
+	/*
+	 * Match if the SA provided in indeed associated with the flow. In case this is
+	 * not associated due to re-key then we should not remove the flow
+	 */
+	if (flow->sa != sa) {
+		write_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_warn("%px: failed to match the SA in flow(%px) delete", tun, flow);
+		return;
+	}
+
+	/*
+	 * Free the flow entry and reference.
+	 */
+	nss_ipsecmgr_ref_del(&flow->ref, &tun->free_refs);
+	write_unlock_bh(&ipsecmgr_drv->lock);
+
+	schedule_work(&tun->free_work);
+}
+EXPORT_SYMBOL(nss_ipsecmgr_flow_del);
+
+/*
+ * nss_ipsecmgr_flow_add()
+ *	Add a new flow to database asynchronously.
+ */
+nss_ipsecmgr_status_t nss_ipsecmgr_flow_add(struct net_device *dev, struct nss_ipsecmgr_flow_tuple *f_tuple,
+						struct nss_ipsecmgr_sa_tuple *s_tuple)
+{
+	enum nss_ipsec_cmn_msg_type type = NSS_IPSEC_CMN_MSG_TYPE_FLOW_CREATE;
+	struct nss_ipsecmgr_tunnel *tun = netdev_priv(dev);
+	struct nss_ipsec_cmn_flow_tuple *flow_tuple;
+	struct nss_ipsec_cmn_sa_tuple *sa_tuple;
+	struct nss_ipsec_cmn_msg nicm = {{0}};
+	struct nss_ipsecmgr_flow *flow;
+	struct nss_ipsecmgr_ctx *ctx;
+	struct nss_ipsecmgr_sa *sa;
+	nss_tx_status_t status;
+
+	dev_hold(dev);
+
+	flow_tuple = &nicm.msg.flow.flow_tuple;
+	sa_tuple = &nicm.msg.flow.sa_tuple;
+
+	nss_ipsecmgr_sa2tuple(s_tuple, sa_tuple);
+	nss_ipsecmgr_flow2tuple(f_tuple, flow_tuple);
+
+	/*
+	 * Write lock needed here since Flow DB is looked up and added
+	 * No one should be accessing/removing flow at this point
+	 */
+	write_lock_bh(&ipsecmgr_drv->lock);
+
+	/*
+	 * Check if the SA exists
+	 */
+	sa = nss_ipsecmgr_sa_find(ipsecmgr_drv->sa_db, sa_tuple);
+	if (!sa) {
+		write_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_warn("%px: failed to find SA during flow_add", tun);
+		dev_put(dev);
+		return NSS_IPSECMGR_INVALID_SA;
+	}
+
+	/*
+	 * Check if the context exists
+	 */
+	ctx = nss_ipsecmgr_ctx_find(tun, sa->type);
+	if (!ctx) {
+		write_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_warn("%px: Failed to find context (%u)", tun, sa->type);
+		dev_put(dev);
+		return NSS_IPSECMGR_INVALID_CTX;
+	}
+
+	/*
+	 * TODO: Why do we need this
+	 */
+	memcpy(sa_tuple, &sa->state.tuple, sizeof(*sa_tuple));
+
+	/*
+	 * At this point we do not know whether the flow is duplicate or not
+	 * we try to perform a flow lookup to determine whether the flow already
+	 * exists in the data base. Once, we have determined the flow then we check
+	 * if the caller is performing a SA switch.
+	 */
+	flow = nss_ipsecmgr_flow_find(ipsecmgr_drv->flow_db, flow_tuple);
+	if (flow) {
+		/*
+		 * Flow already exists; check if the SA entry is the same. In case
+		 * the SA is same then it is surely a duplicate entry. We need to
+		 * return from here without doing anything.
+		 */
+		if (flow->sa == sa) {
+			write_unlock_bh(&ipsecmgr_drv->lock);
+			nss_ipsecmgr_trace("%px: Duplicate flow in flow_add", ipsecmgr_drv);
+			dev_put(dev);
+			return NSS_IPSECMGR_DUPLICATE_FLOW;
+		}
+
+		/*
+		 * Detach the flow from the reference tree and flow database, then free the object.
+		 * Here we don't want to inform the NSS as it is not a real flow free.
+		 * We are just moving an existing flow to a new SA
+		 */
+		nss_ipsecmgr_ref_del(&flow->ref, NULL);
+		nss_ipsecmgr_flow_free(flow);
+	}
+
+	flow = nss_ipsecmgr_flow_alloc(sa, flow_tuple, sa_tuple);
+	if (!flow) {
+		write_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_info("%px: failed to allocate flow", tun);
+		dev_put(dev);
+		return NSS_IPSECMGR_FAIL_FLOW_ALLOC;
+	}
+
+	write_unlock_bh(&ipsecmgr_drv->lock);
+
+	/*
+	 * Initialize the IPsec message to be sent.
+	 */
+	nss_ipsec_cmn_msg_init(&nicm, flow->ifnum, type, sizeof(nicm.msg.flow), nss_ipsecmgr_flow_create_resp, flow);
+
+	/*
+	 * Note: We don't need to hold the lock for the accessing the flow since
+	 * it is not part of the list yet. Now, send a message to firmware for
+	 * updating the flow in its table. Once, NSS confirms it then we will
+	 * add the flow back in the database
+	 */
+	status = nss_ipsec_cmn_tx_msg(flow->nss_ctx, &nicm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ipsecmgr_info("%px: failed to send the flow create message", dev);
+		nss_ipsecmgr_flow_free(flow);
+		dev_put(dev);
+		return NSS_IPSECMGR_FAIL;
+	}
+
+	dev_put(dev);
+	return NSS_IPSECMGR_OK;
+}
+EXPORT_SYMBOL(nss_ipsecmgr_flow_add);
+
+/*
+ * nss_ipsecmgr_flow_add()
+ *	Add a new flow to database synchronously.
+ */
+nss_ipsecmgr_status_t nss_ipsecmgr_flow_add_sync(struct net_device *dev, struct nss_ipsecmgr_flow_tuple *f_tuple,
+						struct nss_ipsecmgr_sa_tuple *s_tuple)
+{
+
+	enum nss_ipsec_cmn_msg_type type = NSS_IPSEC_CMN_MSG_TYPE_FLOW_CREATE;
+	struct nss_ipsecmgr_tunnel *tun = netdev_priv(dev);
+	struct nss_ipsec_cmn_flow_tuple *flow_tuple;
+	struct nss_ipsec_cmn_sa_tuple *sa_tuple;
+	struct nss_ipsec_cmn_msg nicm = {{0}};
+	struct nss_ipsecmgr_flow *flow;
+	struct nss_ipsecmgr_ctx *ctx;
+	struct nss_ipsecmgr_sa *sa;
+	nss_tx_status_t status;
+
+	BUG_ON(in_atomic());
+
+	dev_hold(dev);
+
+	memset(&nicm, 0, sizeof(nicm));
+
+	flow_tuple = &nicm.msg.flow.flow_tuple;
+	sa_tuple = &nicm.msg.flow.sa_tuple;
+
+	nss_ipsecmgr_sa2tuple(s_tuple, sa_tuple);
+	nss_ipsecmgr_flow2tuple(f_tuple, flow_tuple);
+
+	/*
+	 * Write lock needed here since Flow DB is looked up and added
+	 * No one should be accessing/removing flow at this point
+	 */
+	write_lock_bh(&ipsecmgr_drv->lock);
+
+	/*
+	 * Check if the SA exists
+	 */
+	sa = nss_ipsecmgr_sa_find(ipsecmgr_drv->sa_db, sa_tuple);
+	if (!sa) {
+		write_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_warn("%px: failed to find SA during flow_add", tun);
+		dev_put(dev);
+		return NSS_IPSECMGR_INVALID_SA;
+	}
+
+	/*
+	 * Check if the context exists
+	 */
+	ctx = nss_ipsecmgr_ctx_find(tun, sa->type);
+	if (!ctx) {
+		write_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_warn("%px: Failed to find context (%u)", tun, sa->type);
+		dev_put(dev);
+		return NSS_IPSECMGR_INVALID_CTX;
+	}
+
+	/*
+	 * TODO: Why do we need this
+	 */
+	memcpy(sa_tuple, &sa->state.tuple, sizeof(*sa_tuple));
+
+	/*
+	 * At this point we do not know whether the flow is duplicate or not
+	 * we try to perform a flow lookup to determine whether the flow already
+	 * exists in the data base. Once, we have determined the flow then we check
+	 * if the caller is performing a SA switch.
+	 */
+	flow = nss_ipsecmgr_flow_find(ipsecmgr_drv->flow_db, flow_tuple);
+	if (flow) {
+		/*
+		 * Flow already exists; check if the SA entry is the same. In case
+		 * the SA is same then it is surely a duplicate entry. We need to
+		 * return from here without doing anything.
+		 */
+		if (flow->sa == sa) {
+			write_unlock_bh(&ipsecmgr_drv->lock);
+			nss_ipsecmgr_trace("%px: Duplicate flow in flow_add", ipsecmgr_drv);
+			dev_put(dev);
+			return NSS_IPSECMGR_DUPLICATE_FLOW;
+		}
+
+		/*
+		 * Detach the flow from the reference tree and flow database, then free the object.
+		 * Here we don't want to inform the NSS as it is not a real flow free.
+		 * We are just moving an existing flow to a new SA
+		 */
+		nss_ipsecmgr_ref_del(&flow->ref, NULL);
+		nss_ipsecmgr_flow_free(flow);
+	}
+
+	flow = nss_ipsecmgr_flow_alloc(sa, flow_tuple, sa_tuple);
+	if (!flow) {
+		write_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_info("%px: failed to allocate flow", tun);
+		dev_put(dev);
+		return NSS_IPSECMGR_FAIL_FLOW_ALLOC;
+	}
+
+	write_unlock_bh(&ipsecmgr_drv->lock);
+
+	/*
+	 * Initialize the IPsec message to be sent.
+	 */
+	nss_ipsec_cmn_msg_init(&nicm, flow->ifnum, type, sizeof(nicm.msg.flow), NULL, NULL);
+
+	/*
+	 * Note: We don't need to hold the lock for the accessing the flow since
+	 * it is not part of the list yet. Now, send a message to firmware for
+	 * updating the flow in its table. Once, NSS confirms it then we will
+	 * add the flow back in the database
+	 */
+	status = nss_ipsec_cmn_tx_msg_sync(flow->nss_ctx, flow->ifnum, type, sizeof(nicm.msg.flow), &nicm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ipsecmgr_info("%px: failed to send the flow create message", dev);
+		nss_ipsecmgr_flow_free(flow);
+		dev_put(dev);
+		return NSS_IPSECMGR_FAIL;
+	}
+
+	/*
+	 * Since, this is a synchronous call add it to the database directly
+	 */
+	if (!nss_ipsecmgr_flow_update_db(flow)) {
+		nss_ipsecmgr_info("%px: failed to add flow to DB", dev);
+		nss_ipsecmgr_flow_free(flow);
+		dev_put(dev);
+		return NSS_IPSECMGR_FAIL_ADD_DB;
+	}
+
+	dev_put(dev);
+	return NSS_IPSECMGR_OK;
+}
+EXPORT_SYMBOL(nss_ipsecmgr_flow_add_sync);
diff --git a/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_flow.h b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_flow.h
new file mode 100644
index 0000000..f60b17c
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_flow.h
@@ -0,0 +1,225 @@
+/*
+ * ********************************************************************************
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ **********************************************************************************
+ */
+#ifndef __NSS_IPSECMGR_FLOW_H
+#define __NSS_IPSECMGR_FLOW_H
+
+#define NSS_IPSECMGR_FLOW_MAX 1024 /* Maximum number of flow(s) */
+#if (~(NSS_IPSECMGR_FLOW_MAX - 1) & (NSS_IPSECMGR_FLOW_MAX >> 1))
+#error "NSS_IPSECMGR_FLOW_MAX is not a power of 2"
+#endif
+
+#define NSS_IPSECMGR_FLOW_PRINT_EXTRA 64
+#define NSS_IPSECMGR_FLOW_FREE_TIMEOUT msecs_to_jiffies(20) /* msecs */
+
+struct nss_ipsecmgr_sa;
+
+/*
+ * Per flow state
+ */
+struct nss_ipsecmgr_flow_state {
+	struct nss_ipsec_cmn_flow_tuple tuple;	/* Flow tuple */
+	struct nss_ipsec_cmn_sa_tuple sa;	/* SA tuple; used during deletion */
+};
+
+/*
+ * IPsec manager flow entry
+ */
+struct nss_ipsecmgr_flow {
+	struct list_head list;			/* List object. */
+	struct nss_ipsecmgr_ref ref;		/* Reference object. */
+	struct nss_ipsecmgr_sa *sa;		/* Parent SA object */
+
+	uint32_t ifnum;				/* NSS interface attached to flow */
+	struct nss_ctx_instance *nss_ctx;	/* NSS context */
+	struct nss_ipsecmgr_flow_state state;
+
+	int tunnel_id;				/* Linux device index */
+};
+
+/*
+ * nss_ipsecmgr_flow_ntoh_v6addr()
+ *	Network to host order and swap
+ */
+static inline void nss_ipsecmgr_flow_ntoh_v6addr(uint32_t *dest, uint32_t *src)
+{
+	dest[0] = ntohl(src[0]);
+	dest[1] = ntohl(src[1]);
+	dest[2] = ntohl(src[2]);
+	dest[3] = ntohl(src[3]);
+}
+
+/*
+ * nss_ipsecmgr_flow_tuple_match()
+ * 	Match flow tuple
+ */
+static inline bool nss_ipsecmgr_flow_tuple_match(struct nss_ipsec_cmn_flow_tuple *d, struct nss_ipsec_cmn_flow_tuple *s)
+{
+	uint32_t status = 0;
+
+	switch (d->ip_ver) {
+	case IPVERSION:
+		status += d->dest_ip[0] ^ s->dest_ip[0];
+		status += d->src_ip[0] ^ s->src_ip[0];
+		status += d->spi_index ^ s->spi_index;
+		status += d->protocol ^ s->protocol;
+		status += d->ip_ver ^ s->ip_ver;
+		status += d->user_pattern ^ s->user_pattern;
+		return !status;
+
+	default:
+		status += d->dest_ip[0] ^ s->dest_ip[0];
+		status += d->dest_ip[1] ^ s->dest_ip[1];
+		status += d->dest_ip[2] ^ s->dest_ip[2];
+		status += d->dest_ip[3] ^ s->dest_ip[3];
+		status += d->src_ip[0] ^ s->src_ip[0];
+		status += d->src_ip[1] ^ s->src_ip[1];
+		status += d->src_ip[2] ^ s->src_ip[2];
+		status += d->src_ip[3] ^ s->src_ip[3];
+		status += d->spi_index ^ s->spi_index;
+		status += d->protocol ^ s->protocol;
+		status += d->ip_ver ^ s->ip_ver;
+		status += d->user_pattern ^ s->user_pattern;
+		return !status;
+	}
+}
+
+/*
+ * nss_ipsecmgr_flow_tuple2index()
+ * 	Change tuple to hash index
+ */
+static inline uint32_t nss_ipsecmgr_flow_tuple2hash(struct nss_ipsec_cmn_flow_tuple *tuple, uint32_t max)
+{
+	uint32_t val = 0;
+
+	val ^= tuple->dest_ip[0];
+	val ^= tuple->src_ip[0];
+	val ^= tuple->dest_ip[1];
+	val ^= tuple->src_ip[1];
+	val ^= tuple->dest_ip[2];
+	val ^= tuple->src_ip[2];
+	val ^= tuple->dest_ip[3];
+	val ^= tuple->src_ip[3];
+	val ^= tuple->spi_index;
+	val ^= tuple->protocol;
+	val ^= tuple->ip_ver;
+	val ^= tuple->user_pattern;
+
+	return val & (max - 1);
+}
+
+/*
+ * nss_ipsecmgr_flow2tuple()
+ * 	Change flow to tuple
+ */
+static inline void nss_ipsecmgr_flow2tuple(struct nss_ipsecmgr_flow_tuple *f, struct nss_ipsec_cmn_flow_tuple *t)
+{
+	memcpy(t->dest_ip, f->dest_ip, sizeof(t->dest_ip));
+	memcpy(t->src_ip, f->src_ip, sizeof(t->src_ip));
+	t->spi_index = f->spi_index;
+	t->protocol = f->proto_next_hdr;
+	t->ip_ver = f->ip_version;
+	t->src_port = f->sport;
+	t->dst_port = f->dport;
+	t->user_pattern = f->use_pattern;
+}
+
+/*
+ * nss_ipsecmgr_flow_ipv4_inner2tuple()
+ * 	Change inner IPv4 flow to tuple
+ */
+static inline void nss_ipsecmgr_flow_ipv4_inner2tuple(struct iphdr *iph, struct nss_ipsec_cmn_flow_tuple *t)
+{
+	t->src_ip[0] = ntohl(iph->saddr);
+	t->dest_ip[0] = ntohl(iph->daddr);
+	t->ip_ver = IPVERSION;
+	t->protocol = iph->protocol;
+}
+
+/*
+ * nss_ipsecmgr_flow_ipv4_outer2tuple()
+ * 	Change outer IPv4 flow to tuple
+ */
+static inline void nss_ipsecmgr_flow_ipv4_outer2tuple(struct iphdr *iph, struct nss_ipsec_cmn_flow_tuple *t)
+{
+	uint8_t *data = (uint8_t *)iph;
+	struct ip_esp_hdr *esph;
+
+	WARN_ON((iph->protocol != IPPROTO_ESP) && (iph->protocol != IPPROTO_UDP));
+
+	t->src_ip[0] = ntohl(iph->saddr);
+	t->dest_ip[0] = ntohl(iph->daddr);
+	t->ip_ver = IPVERSION;
+	t->protocol = iph->protocol;
+
+	data += sizeof(*iph);
+
+	if (t->protocol == IPPROTO_UDP)
+		data += sizeof(struct udphdr);
+
+	esph = (struct ip_esp_hdr *)data;
+	t->spi_index = ntohl(esph->spi);
+}
+
+/*
+ * nss_ipsecmgr_flow_ipv6_inner2tuple()
+ * 	Change inner IPv6 flow to tuple
+ */
+static inline void nss_ipsecmgr_flow_ipv6_inner2tuple(struct ipv6hdr *ip6h, struct nss_ipsec_cmn_flow_tuple *t)
+{
+	uint8_t *data = (uint8_t *)ip6h;
+	struct frag_hdr *fragh;
+
+	nss_ipsecmgr_flow_ntoh_v6addr(t->src_ip, ip6h->saddr.s6_addr32);
+	nss_ipsecmgr_flow_ntoh_v6addr(t->dest_ip, ip6h->daddr.s6_addr32);
+
+	t->protocol = ip6h->nexthdr;
+	t->ip_ver = 6;
+
+	data += sizeof(*ip6h);
+
+	if (t->protocol == NEXTHDR_FRAGMENT) {
+		fragh = (struct frag_hdr *)data;
+		t->protocol = fragh->nexthdr;
+	}
+}
+
+/*
+ * nss_ipsecmgr_flow_ipv6_outer2tuple()
+ * 	Change inner IPv6 flow to tuple
+ */
+static inline void nss_ipsecmgr_flow_ipv6_outer2tuple(struct ipv6hdr *ip6h, struct nss_ipsec_cmn_flow_tuple *t)
+{
+	uint8_t *data = (uint8_t *)ip6h;
+	struct ip_esp_hdr *esph;
+
+	nss_ipsecmgr_flow_ntoh_v6addr(t->src_ip, ip6h->saddr.s6_addr32);
+	nss_ipsecmgr_flow_ntoh_v6addr(t->dest_ip, ip6h->daddr.s6_addr32);
+
+	t->protocol = ip6h->nexthdr;
+	t->ip_ver = 6;
+
+	WARN_ON(ip6h->nexthdr != IPPROTO_ESP);
+
+	data += sizeof(*ip6h);
+
+	esph = (struct ip_esp_hdr *)data;
+	t->spi_index = ntohl(esph->spi);
+}
+
+struct nss_ipsecmgr_flow *nss_ipsecmgr_flow_find(struct list_head *db, struct nss_ipsec_cmn_flow_tuple *t);
+#endif
diff --git a/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_priv.h b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_priv.h
new file mode 100644
index 0000000..395c8a6
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_priv.h
@@ -0,0 +1,157 @@
+/*
+ * ********************************************************************************
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ **********************************************************************************
+ */
+
+#ifndef __NSS_IPSECMGR_PRIV_H
+#define __NSS_IPSECMGR_PRIV_H
+
+#include <net/ipv6.h>
+#include <linux/lockdep.h>
+#include <linux/version.h>
+
+#define NSS_IPSECMGR_DEBUG_LVL_ERROR 1		/**< Turn on debug for an error. */
+#define NSS_IPSECMGR_DEBUG_LVL_WARN 2		/**< Turn on debug for a warning. */
+#define NSS_IPSECMGR_DEBUG_LVL_INFO 3		/**< Turn on debug for information. */
+#define NSS_IPSECMGR_DEBUG_LVL_TRACE 4		/**< Turn on debug for trace. */
+
+#define nss_ipsecmgr_info_always(s, ...) pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__)
+
+#define nss_ipsecmgr_error(s, ...) do {	\
+	if (net_ratelimit()) {	\
+		pr_alert("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+} while (0)
+
+#define nss_ipsecmgr_warn(s, ...) do {	\
+	if (net_ratelimit()) {	\
+		pr_warn("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+} while (0)
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_ipsecmgr_info(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__)
+#define nss_ipsecmgr_trace(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__)
+
+#else
+/*
+ * Statically compile messages at different levels
+ */
+#define nss_ipsecmgr_info(s, ...) {	\
+	if (NSS_IPSECMGR_DEBUG_LEVEL > NSS_IPSECMGR_DEBUG_LVL_INFO) {	\
+		pr_notice("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+#define nss_ipsecmgr_trace(s, ...) {	\
+	if (NSS_IPSECMGR_DEBUG_LEVEL > NSS_IPSECMGR_DEBUG_LVL_TRACE) {	\
+		pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+
+#endif /* !CONFIG_DYNAMIC_DEBUG */
+#define NSS_IPSECMGR_CHK_POW2(x) (__builtin_constant_p(x) && !(~(x - 1) & (x >> 1)))
+
+#define NSS_IPSECMGR_DEFAULT_TUN_NAME "ipsecdummy"
+#define NSS_IPSECMGR_ESP_TRAIL_SZ 2 /* esp trailer size. */
+#define NSS_IPSECMGR_ESP_PAD_SZ 14 /* maximum amount of padding. */
+
+#define NSS_IPSECMGR_PRINT_PAGES 2
+#define NSS_IPSECMGR_PRINT_BYTES(bytes) ((((bytes) * BITS_PER_BYTE) / 4) + 4)
+#define NSS_IPSECMGR_PRINT_DWORD NSS_IPSECMGR_PRINT_BYTES(8)
+#define NSS_IPSECMGR_PRINT_WORD NSS_IPSECMGR_PRINT_BYTES(4)
+#define NSS_IPSECMGR_PRINT_SHORT NSS_IPSECMGR_PRINT_BYTES(2)
+#define NSS_IPSECMGR_PRINT_BYTE NSS_IPSECMGR_PRINT_BYTES(1)
+#define NSS_IPSECMGR_PRINT_IPADDR (NSS_IPSECMGR_PRINT_WORD * 4)
+/*
+ * Check if lock is held
+ */
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 14, 196))
+#define nss_ipsecmgr_write_lock_is_held(x) BUG_ON(write_can_lock(x))
+#define nss_ipsecmgr_lock_is_held(x) BUG_ON(read_can_lock(x))
+#else
+#define nss_ipsecmgr_lock_is_held(x) lockdep_assert_held(x)
+#define nss_ipsecmgr_write_lock_is_held(x) lockdep_assert_held_write(x)
+#endif
+
+/*
+ * Statistics dump information
+ */
+struct nss_ipsecmgr_print {
+	char *str;		/* Name of variable. */
+	ssize_t var_size;	/* Size of variable in bytes. */
+};
+
+/*
+ * IPsec manager drv instance
+ */
+struct nss_ipsecmgr_drv {
+	struct dentry *dentry;			/* Debugfs entry per ipsecmgr module. */
+	struct net_device *dev;			/* IPsec dummy net device. */
+
+	rwlock_t lock;					/* lock for all DB operations. */
+	struct list_head sa_db[NSS_IPSECMGR_SA_MAX];	/* SA database. */
+	struct list_head flow_db[NSS_IPSECMGR_FLOW_MAX];/* Flow database. */
+	struct list_head tun_db;			/* Tunnel database. */
+
+	struct nss_ctx_instance *nss_ctx;	/* NSS context. */
+	struct delayed_work cfg_work;		/* Configure node work. */
+	uint32_t ifnum;				/* NSS IPsec base interface. */
+	uint16_t max_mtu;			/* Maximum MTU supported. */
+	bool ipsec_inline;			/* IPsec inline mode. */
+};
+
+/*
+ * nss_ipsecmgr_hton_v6addr()
+ *	Host to network order and swap
+ */
+static inline void nss_ipsecmgr_hton_v6addr(uint32_t *dest, uint32_t *src)
+{
+	dest[3] = htonl(src[3]);
+	dest[2] = htonl(src[2]);
+	dest[1] = htonl(src[1]);
+	dest[0] = htonl(src[0]);
+}
+
+/*
+ * nss_ipsecmgr_db_init_entries()
+ *	Initialize the entries databases
+ */
+static inline void nss_ipsecmgr_db_init_entries(struct list_head *db, uint32_t max)
+{
+	struct list_head *head = db;
+	int i;
+
+	/*
+	 * initialize the database
+	 */
+	for (i = 0; i < max; i++, head++)
+		INIT_LIST_HEAD(head);
+}
+
+/*
+ * nss_ipsecmgr_db_init()
+ *	Initialize the single entry database
+ */
+static inline void nss_ipsecmgr_db_init(struct list_head *db)
+{
+	INIT_LIST_HEAD(db);
+}
+
+extern struct nss_ipsecmgr_drv *ipsecmgr_drv;
+#endif
diff --git a/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_ref.c b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_ref.c
new file mode 100644
index 0000000..fb97532
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_ref.c
@@ -0,0 +1,246 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/* nss_ipsecmgr_ref.c
+ *	IPSec Manager reference routines
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/of.h>
+#include <linux/ipv6.h>
+#include <linux/skbuff.h>
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/netdevice.h>
+#include <linux/rtnetlink.h>
+#include <linux/etherdevice.h>
+#include <linux/vmalloc.h>
+#include <linux/debugfs.h>
+#include <linux/atomic.h>
+#include <net/protocol.h>
+#include <net/route.h>
+#include <net/ip6_route.h>
+#include <net/esp.h>
+#include <net/xfrm.h>
+#include <net/icmp.h>
+
+#include <crypto/aead.h>
+#include <crypto/skcipher.h>
+#include <crypto/internal/hash.h>
+
+#include <nss_api_if.h>
+#include <nss_ipsec_cmn.h>
+#include <nss_ipsecmgr.h>
+#include <nss_cryptoapi.h>
+
+#ifdef NSS_IPSECMGR_PPE_SUPPORT
+#include <ref/ref_vsi.h>
+#endif
+
+#include "nss_ipsecmgr_ref.h"
+#include "nss_ipsecmgr_flow.h"
+#include "nss_ipsecmgr_sa.h"
+#include "nss_ipsecmgr_ctx.h"
+#include "nss_ipsecmgr_tunnel.h"
+#include "nss_ipsecmgr_priv.h"
+
+extern struct nss_ipsecmgr_drv *ipsecmgr_drv;
+
+/*
+ * nss_ipsecmgr_ref_no_del()
+ *	dummy functions for object owner when there is no delete
+ */
+static void nss_ipsecmgr_ref_no_del(struct nss_ipsecmgr_ref *ref)
+{
+	nss_ipsecmgr_trace("%px: ref_no_del triggered\n", ref);
+	return;
+}
+
+/*
+ * nss_ipsecmgr_ref_no_free()
+ *	dummy functions for object owner when there is no free
+ */
+static void nss_ipsecmgr_ref_no_free(struct nss_ipsecmgr_ref *ref)
+{
+	nss_ipsecmgr_trace("%px: ref_no_free triggered\n", ref);
+	return;
+}
+
+/*
+ * nss_ipsecmgr_ref_no_print_len()
+ *	dummy functions for object owner when there is no stats length
+ */
+static ssize_t nss_ipsecmgr_ref_no_print_len(struct nss_ipsecmgr_ref *ref)
+{
+	nss_ipsecmgr_trace("%px: ref_no_free triggered\n", ref);
+	return 0;
+}
+
+/*
+ * nss_ipsecmgr_ref_no_print()
+ *	dummy functions for object owner when there is no stats dump
+ */
+static ssize_t nss_ipsecmgr_ref_no_print(struct nss_ipsecmgr_ref *ref, char *buf)
+{
+	nss_ipsecmgr_trace("%px: ref_no_free triggered\n", ref);
+	return 0;
+}
+
+/*
+ * nss_ipsecmgr_ref_init()
+ *	initiaize the reference object
+ */
+void nss_ipsecmgr_ref_init(struct nss_ipsecmgr_ref *ref, nss_ipsecmgr_ref_method_t del, nss_ipsecmgr_ref_method_t free)
+{
+	INIT_LIST_HEAD(&ref->head);
+	INIT_LIST_HEAD(&ref->node);
+
+	ref->id = 0;
+	ref->parent = NULL;
+	ref->free = free ? free : nss_ipsecmgr_ref_no_free;
+	ref->del = del ? del : nss_ipsecmgr_ref_no_del;
+	ref->print_len = nss_ipsecmgr_ref_no_print_len;
+	ref->print = nss_ipsecmgr_ref_no_print;
+}
+
+/*
+ * nss_ipsecmgr_ref_init_print
+ *	Initialize print methods
+ */
+void nss_ipsecmgr_ref_init_print(struct nss_ipsecmgr_ref *ref, nss_ipsecmgr_ref_get_method_t print_len,
+				nss_ipsecmgr_ref_print_method_t print)
+{
+	ref->print_len = print_len;
+	ref->print = print;
+}
+
+/*
+ * nss_ipsecmgr_ref_print()
+ *	Print reference node information and its children
+ */
+ssize_t nss_ipsecmgr_ref_print(struct nss_ipsecmgr_ref *ref, char *buf)
+{
+	struct nss_ipsecmgr_ref *entry;
+	size_t len = 0;
+
+	/*
+	 * DEBUG check to see if the lock is taken before touching the list
+	 */
+	nss_ipsecmgr_write_lock_is_held(&ipsecmgr_drv->lock);
+
+	len += ref->print(ref, buf);
+
+	list_for_each_entry(entry, &ref->head, node) {
+		len += nss_ipsecmgr_ref_print(entry, buf + len);
+	}
+
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_ref_print_len()
+ *	Get print length for the reference node and its children
+ */
+ssize_t nss_ipsecmgr_ref_print_len(struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_ref *entry;
+	size_t total_len = 0;
+
+	/*
+	 * DEBUG check to see if the lock is taken before touching the list
+	 */
+	nss_ipsecmgr_write_lock_is_held(&ipsecmgr_drv->lock);
+
+	list_for_each_entry(entry, &ref->head, node) {
+		total_len += nss_ipsecmgr_ref_print_len(entry);
+	}
+
+	return total_len + ref->print_len(ref);
+}
+
+/*
+ * nss_ipsecmgr_ref_del()
+ *	Delete child reference and add it to zombie list
+ *
+ * Note: If, the "ref" has child references then it
+ * will walk the child reference chain first and issue
+ * free for each of the associated "child ref" objects.
+ * At the end it will invoke free for the "parent" ref
+ * object.
+ *
+ * +-------+
+ * |  tun0 |
+ * +-------+
+ *     |
+ *     V
+ * +-------+    +-------+    +-------+
+ * |  SA1  |--->|  SA2  |--->|  SA3  |
+ * +-------+    +-------+    +-------+
+ *     |
+ *     V
+ * +-------+    +-------+    +-------+
+ * | Flow1 |--->| Flow2 |--->| Flow4 |
+ * +-------+    +-------+    +-------+
+ */
+void nss_ipsecmgr_ref_del(struct nss_ipsecmgr_ref *ref, struct list_head *free_q)
+{
+	struct nss_ipsecmgr_ref *entry;
+
+	/*
+	 * DEBUG check to see if the lock is taken before touching the list
+	 */
+	nss_ipsecmgr_write_lock_is_held(&ipsecmgr_drv->lock);
+
+	while (!list_empty(&ref->head)) {
+		entry = list_first_entry(&ref->head, struct nss_ipsecmgr_ref, node);
+		nss_ipsecmgr_ref_del(entry, free_q);
+	}
+
+	list_del_init(&ref->node);
+	ref->del(ref);
+
+	/*
+	 * If, free list is valid then add the reference node to zombie
+	 * list for delayed free
+	 */
+	if (free_q) {
+		list_add_tail(&ref->node, free_q);
+	}
+}
+
+/*
+ * nss_ipsecmgr_ref_add()
+ *	add child reference to parent chain
+ */
+void nss_ipsecmgr_ref_add(struct nss_ipsecmgr_ref *child, struct nss_ipsecmgr_ref *parent)
+{
+	/*
+	 * DEBUG check to see if the lock is taken before touching the list
+	 */
+	nss_ipsecmgr_write_lock_is_held(&ipsecmgr_drv->lock);
+
+	/*
+	 * if child is already part of an existing chain then remove it before
+	 * adding it to the new one. In case this is a new entry then the list
+	 * init during alloc would ensure that the "del_init" operation results
+	 * in a no-op
+	 */
+	list_del_init(&child->node);
+	list_add(&child->node, &parent->head);
+
+	child->parent = parent;
+}
diff --git a/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_ref.h b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_ref.h
new file mode 100644
index 0000000..dddab35
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_ref.h
@@ -0,0 +1,61 @@
+/*
+ * ********************************************************************************
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ **********************************************************************************
+ */
+
+#ifndef __NSS_IPSECMGR_REF_H
+#define __NSS_IPSECMGR_REF_H
+
+struct nss_ipsecmgr_ref;
+
+typedef void (*nss_ipsecmgr_ref_method_t)(struct nss_ipsecmgr_ref *ref);
+typedef ssize_t (*nss_ipsecmgr_ref_get_method_t)(struct nss_ipsecmgr_ref *ref);
+typedef ssize_t (*nss_ipsecmgr_ref_print_method_t)(struct nss_ipsecmgr_ref *ref, char *buf);
+
+/*
+ * IPsec manager reference object
+ */
+struct nss_ipsecmgr_ref {
+	struct list_head head;			/* parent "ref" */
+	struct list_head node;			/* child "ref" */
+
+	uint32_t id;				/* identifier */
+	struct nss_ipsecmgr_ref *parent;	/* reference to parent */
+
+	nss_ipsecmgr_ref_get_method_t print_len;	/* returns the statistics size for ref */
+	nss_ipsecmgr_ref_print_method_t print;		/* dumps the statistics in buffer */
+
+	nss_ipsecmgr_ref_method_t free;		/* free function */
+	nss_ipsecmgr_ref_method_t del;		/* unlink function */
+};
+
+/* Check if the reference tree is empty */
+static inline bool nss_ipsecmgr_ref_is_empty(struct nss_ipsecmgr_ref *ref)
+{
+	return list_empty(&ref->head);
+}
+
+/* functions to operate on reference object */
+extern ssize_t nss_ipsecmgr_ref_print_len(struct nss_ipsecmgr_ref *ref);
+extern ssize_t nss_ipsecmgr_ref_print(struct nss_ipsecmgr_ref *ref, char *buf);
+extern void nss_ipsecmgr_ref_del(struct nss_ipsecmgr_ref *ref, struct list_head *free_q);
+extern void nss_ipsecmgr_ref_add(struct nss_ipsecmgr_ref *child, struct nss_ipsecmgr_ref *parent);
+extern void nss_ipsecmgr_ref_init(struct nss_ipsecmgr_ref *ref, nss_ipsecmgr_ref_method_t del,
+				nss_ipsecmgr_ref_method_t free);
+extern void nss_ipsecmgr_ref_init_print(struct nss_ipsecmgr_ref *ref, nss_ipsecmgr_ref_get_method_t print_len,
+					nss_ipsecmgr_ref_print_method_t print);
+
+#endif
diff --git a/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_sa.c b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_sa.c
new file mode 100644
index 0000000..12f28af
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_sa.c
@@ -0,0 +1,1315 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTUOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/of.h>
+#include <linux/ipv6.h>
+#include <linux/skbuff.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/rtnetlink.h>
+#include <net/route.h>
+#include <net/ip6_route.h>
+#include <asm/atomic.h>
+#include <linux/debugfs.h>
+#include <linux/vmalloc.h>
+
+#include <crypto/algapi.h>
+#include <crypto/aead.h>
+#include <crypto/internal/hash.h>
+#include <crypto/authenc.h>
+#include <crypto/skcipher.h>
+
+#include <nss_api_if.h>
+#include <nss_ipsec_cmn.h>
+#include <nss_ipsecmgr.h>
+#include <nss_cryptoapi.h>
+
+#include "nss_ipsecmgr_ref.h"
+#include "nss_ipsecmgr_flow.h"
+#include "nss_ipsecmgr_sa.h"
+#include "nss_ipsecmgr_ctx.h"
+#include "nss_ipsecmgr_tunnel.h"
+#include "nss_ipsecmgr_priv.h"
+
+#define NSS_IPSECMGR_DEBUGFS_NAME_SZ 128 /* bytes */
+
+extern struct nss_ipsecmgr_drv *ipsecmgr_drv;
+
+/*
+ * Linux crypto algorithm names.
+ */
+static const char *ipsecmgr_algo_name[NSS_IPSECMGR_ALGO_MAX] = {
+	"echainiv(authenc(hmac(sha1),cbc(aes)))",
+	"echainiv(authenc(hmac(sha256),cbc(aes)))",
+	"echainiv(authenc(hmac(sha1),cbc(des3_ede)))",
+	"echainiv(authenc(hmac(sha256),cbc(des3_ede)))",
+	"hmac(sha1)",
+	"hmac(sha256)",
+	"seqiv(rfc4106(gcm(aes)))",
+	"echainiv(authenc(hmac(md5),cbc(aes)))",
+	"echainiv(authenc(hmac(md5),cbc(des3_ede)))",
+	"echainiv(authenc(hmac(sha384),cbc(aes)))",
+	"echainiv(authenc(hmac(sha512),cbc(aes)))",
+};
+
+/*
+ * SA tuple print info
+ */
+static const struct nss_ipsecmgr_print ipsecmgr_print_sa_tuple[] = {
+	{"dest_ip", NSS_IPSECMGR_PRINT_IPADDR},
+	{"dest_port", NSS_IPSECMGR_PRINT_WORD},
+	{"src_ip", NSS_IPSECMGR_PRINT_IPADDR},
+	{"src_port", NSS_IPSECMGR_PRINT_WORD},
+	{"spi", NSS_IPSECMGR_PRINT_WORD},
+	{"protocol", NSS_IPSECMGR_PRINT_WORD},
+	{"ip_version", NSS_IPSECMGR_PRINT_WORD},
+};
+
+/*
+ * SA replay print info
+ */
+static const struct nss_ipsecmgr_print ipsecmgr_print_sa_replay[] = {
+	{"replay_win_start", NSS_IPSECMGR_PRINT_DWORD},
+	{"replay_win_current", NSS_IPSECMGR_PRINT_DWORD},
+	{"replay_win_size", NSS_IPSECMGR_PRINT_WORD},
+};
+
+/*
+ * SA tx default print info
+ */
+static const struct nss_ipsecmgr_print ipsecmgr_print_sa_feature[] = {
+	{"tx_default", NSS_IPSECMGR_PRINT_BYTE},
+	{"flags", NSS_IPSECMGR_PRINT_WORD},
+};
+
+/*
+ * SA statistics print info
+ */
+static const struct nss_ipsecmgr_print ipsecmgr_print_sa_stats[] = {
+	{"\trx_packets", NSS_IPSECMGR_PRINT_DWORD},
+	{"\trx_bytes", NSS_IPSECMGR_PRINT_DWORD},
+	{"\ttx_packets", NSS_IPSECMGR_PRINT_DWORD},
+	{"\ttx_bytes", NSS_IPSECMGR_PRINT_DWORD},
+	{"\trx_dropped[0]", NSS_IPSECMGR_PRINT_DWORD},
+	{"\trx_dropped[1]", NSS_IPSECMGR_PRINT_DWORD},
+	{"\trx_dropped[2]", NSS_IPSECMGR_PRINT_DWORD},
+	{"\trx_dropped[3]", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_headroom", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_tailroom", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_replay", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_replay_dup", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_replay_win", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_pbuf_crypto", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_queue", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_queue_crypto", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_queue_nexthop", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_pbuf_alloc", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_pbuf_linear", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_pbuf_stats", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_pbuf_align", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_cipher", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_auth", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_seq_ovf", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_blk_len", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_hash_len", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_transform", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_crypto", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tfail_classification", NSS_IPSECMGR_PRINT_DWORD},
+	{"\tis_stopped", NSS_IPSECMGR_PRINT_DWORD},
+};
+
+/*
+ * nss_ipsecmgr_sa_tuple_print()
+ * 	Print SA tuple
+ */
+static ssize_t nss_ipsecmgr_sa_tuple_print(struct nss_ipsec_cmn_sa_tuple *tuple, char *buf, ssize_t max_len)
+{
+	const struct nss_ipsecmgr_print *prn = ipsecmgr_print_sa_tuple;
+	uint32_t dest_ip[4], src_ip[4];
+	ssize_t len = 0;
+
+	len += snprintf(buf + len, max_len - len, "SA tuple: {");
+	switch (tuple->ip_ver) {
+	case IPVERSION:
+		len += snprintf(buf + len, max_len - len, "%s: %pI4h,", prn->str, tuple->dest_ip);
+		prn++;
+
+		len += snprintf(buf + len, max_len - len, "%s: %u,", prn->str, tuple->dest_port);
+		prn++;
+
+		len += snprintf(buf + len, max_len - len, "%s: %pI4h,", prn->str, tuple->src_ip);
+		prn++;
+
+		len += snprintf(buf + len, max_len - len, "%s: %u,", prn->str, tuple->src_port);
+		prn++;
+
+		break;
+
+	case 6:
+		nss_ipsecmgr_hton_v6addr(src_ip, tuple->src_ip);
+		nss_ipsecmgr_hton_v6addr(dest_ip, tuple->dest_ip);
+
+		len += snprintf(buf + len, max_len - len, "%s: %pI6c,", prn->str, dest_ip);
+		prn++;
+
+		len += snprintf(buf + len, max_len - len, "%s: %u,", prn->str, tuple->dest_port);
+		prn++;
+
+		len += snprintf(buf + len, max_len - len, "%s: %pI6c,", prn->str, src_ip);
+		prn++;
+
+		len += snprintf(buf + len, max_len - len, "%s: %u,", prn->str, tuple->src_port);
+		prn++;
+
+		break;
+	}
+
+	len += snprintf(buf + len, max_len - len, "%s: 0x%x,", prn->str, tuple->spi_index);
+	prn++;
+
+	len += snprintf(buf + len, max_len - len, "%s: %u,", prn->str, tuple->protocol);
+	prn++;
+
+	len += snprintf(buf + len, max_len - len, "%s: %u", prn->str, tuple->ip_ver);
+	prn++;
+
+	len += snprintf(buf + len, max_len - len, "}\n");
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_sa_feature_print()
+ *	Print SA tx default value
+ */
+static ssize_t nss_ipsecmgr_sa_feature_print(struct nss_ipsecmgr_sa *sa, char *buf, ssize_t max_len)
+{
+	const struct nss_ipsecmgr_print *prn = ipsecmgr_print_sa_feature;
+	ssize_t len = 0;
+
+	len += snprintf(buf + len, max_len - len, "SA feature: {");
+	len += snprintf(buf + len, max_len - len, "%s: %u,", prn->str, sa->state.tx_default);
+	prn++;
+	len += snprintf(buf + len, max_len - len, "%s: 0x%x", prn->str, sa->state.data.flags);
+	len += snprintf(buf + len, max_len - len, "}\n");
+
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_sa_replay_print()
+ * 	Print SA replay state
+ */
+static ssize_t nss_ipsecmgr_sa_replay_print(struct nss_ipsec_cmn_sa_replay *replay, char *buf, ssize_t max_len)
+{
+	const struct nss_ipsecmgr_print *prn = ipsecmgr_print_sa_replay;
+	ssize_t len = 0;
+
+	len += snprintf(buf + len, max_len - len, "SA replay: {");
+
+	len += snprintf(buf + len, max_len - len, "%s: %llu,", prn->str, replay->seq_start);
+	prn++;
+
+	len += snprintf(buf + len, max_len - len, "%s: %llu,", prn->str, replay->seq_cur);
+	prn++;
+
+	len += snprintf(buf + len, max_len - len, "%s: %u", prn->str, replay->window_size);
+	prn++;
+
+	len += snprintf(buf + len, max_len - len, "}\n");
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_sa_stats_print()
+ * 	Print SA statistics
+ */
+static ssize_t nss_ipsecmgr_sa_stats_print(struct nss_ipsecmgr_sa_stats_priv *stats, char *buf, ssize_t max_len)
+{
+	const struct nss_ipsecmgr_print *prn = ipsecmgr_print_sa_stats;
+	uint64_t *stats_word = (uint64_t *)stats;
+	ssize_t len = 0;
+	int i;
+
+	/*
+	 * This expects a strict order as per the stats structure
+	 */
+	len += snprintf(buf + len, max_len - len, "SA stats: {\n");
+
+	for (i = 0; i < ARRAY_SIZE(ipsecmgr_print_sa_stats); i++, prn++)
+		len += snprintf(buf + len, max_len - len, "%s: %llu\n", prn->str, *stats_word++);
+
+	len += snprintf(buf + len, max_len - len, "}\n");
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_sa_print_len()
+ * 	Return the total length for printing
+ */
+static ssize_t nss_ipsecmgr_sa_print_len(struct nss_ipsecmgr_ref *ref)
+{
+	ssize_t len = NSS_IPSECMGR_SA_PRINT_EXTRA;
+	const struct nss_ipsecmgr_print *prn;
+	int i;
+
+	for (i = 0, prn = ipsecmgr_print_sa_tuple; i < ARRAY_SIZE(ipsecmgr_print_sa_tuple); i++, prn++)
+		len += strlen(prn->str) + prn->var_size;
+
+	for (i = 0, prn = ipsecmgr_print_sa_replay; i < ARRAY_SIZE(ipsecmgr_print_sa_replay); i++, prn++)
+		len += strlen(prn->str) + prn->var_size;
+
+	for (i = 0, prn = ipsecmgr_print_sa_stats; i < ARRAY_SIZE(ipsecmgr_print_sa_stats); i++, prn++)
+		len += strlen(prn->str) + prn->var_size;
+
+	for (i = 0, prn = ipsecmgr_print_sa_feature; i < ARRAY_SIZE(ipsecmgr_print_sa_feature); i++, prn++)
+		len += strlen(prn->str) + prn->var_size;
+
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_sa_print()
+ *	Print SA info
+ */
+static ssize_t nss_ipsecmgr_sa_print(struct nss_ipsecmgr_ref *ref, char *buf)
+{
+	struct nss_ipsecmgr_sa *sa = container_of(ref, struct nss_ipsecmgr_sa, ref);
+	ssize_t max_len = nss_ipsecmgr_sa_print_len(ref);
+	ssize_t len;
+
+	len = snprintf(buf, max_len, "---- SA(0x%x) -----\n", sa->state.tuple.spi_index);
+
+	len += nss_ipsecmgr_sa_tuple_print(&sa->state.tuple, buf + len, max_len - len);
+	len += nss_ipsecmgr_sa_replay_print(&sa->state.replay, buf + len, max_len - len);
+	len += nss_ipsecmgr_sa_feature_print(sa, buf + len, max_len - len);
+	len += nss_ipsecmgr_sa_stats_print(&sa->stats, buf + len, max_len - len);
+
+	return len;
+}
+
+/*
+ * nss_ipsecmgr_sa_crypto_alloc()
+ *	Allocate Crypto resources
+ */
+static nss_ipsecmgr_status_t nss_ipsecmgr_sa_crypto_alloc(struct nss_ipsecmgr_sa *sa,
+							  struct nss_ipsecmgr_sa_cmn *cmn,
+							  struct nss_ipsec_cmn_sa_tuple *tuple,
+						  	  struct nss_ipsec_cmn_sa_data *data)
+{
+	struct nss_ipsecmgr_crypto_keys *keys = &cmn->keys;
+	struct crypto_authenc_key_param *key_param;
+	struct rtattr *rta;
+	char *rt_keys, *p;
+	uint32_t index;
+	uint16_t keylen;
+
+	/*
+	 * If, crypto is programmed using index(s) skip key-based programming
+	 */
+	if (!cmn->crypto_has_keys) {
+		sa->aead = NULL;
+		data->blk_len = cmn->index.blk_len;
+		data->iv_len = cmn->index.iv_len;
+		data->icv_len = cmn->icv_len;
+		tuple->crypto_index = cmn->index.session;
+		return NSS_IPSECMGR_OK;
+	}
+
+	switch (cmn->algo) {
+	/*
+	 * AEAD Algorithms
+	 */
+	case NSS_IPSECMGR_ALGO_AES_CBC_MD5_HMAC:
+	case NSS_IPSECMGR_ALGO_AES_CBC_SHA1_HMAC:
+	case NSS_IPSECMGR_ALGO_AES_CBC_SHA256_HMAC:
+	case NSS_IPSECMGR_ALGO_3DES_CBC_MD5_HMAC:
+	case NSS_IPSECMGR_ALGO_3DES_CBC_SHA1_HMAC:
+	case NSS_IPSECMGR_ALGO_3DES_CBC_SHA256_HMAC:
+	case NSS_IPSECMGR_ALGO_AES_CBC_SHA384_HMAC:
+	case NSS_IPSECMGR_ALGO_AES_CBC_SHA512_HMAC:
+
+		sa->aead = crypto_alloc_aead(ipsecmgr_algo_name[cmn->algo], 0, 0);
+		if (IS_ERR(sa->aead)) {
+			nss_ipsecmgr_warn("%px: failed to allocate crypto aead context for algo=%s\n", sa,
+					  ipsecmgr_algo_name[cmn->algo]);
+			return NSS_IPSECMGR_FAIL_NOCRYPTO;
+		}
+
+		nss_ipsecmgr_trace("cipher_keylen:%d auth_keylen:%d\n", keys->cipher_keylen, keys->auth_keylen);
+
+		/*
+		 * Construct keys
+		 */
+		keylen = RTA_SPACE(sizeof(*key_param));
+		keylen += keys->cipher_keylen;
+		keylen += keys->auth_keylen;
+		keylen += keys->nonce_size;
+
+		rt_keys = vzalloc(keylen);
+		if (!rt_keys) {
+			nss_ipsecmgr_warn("%px: failed to allocate key memory\n", sa);
+			crypto_free_aead(sa->aead);
+			sa->aead = NULL;
+			return NSS_IPSECMGR_FAIL_NOMEM;
+		}
+
+		p = rt_keys;
+		rta = (void *)p;
+		rta->rta_type = CRYPTO_AUTHENC_KEYA_PARAM;
+		rta->rta_len = RTA_LENGTH(sizeof(*key_param));
+		key_param = RTA_DATA(rta);
+		p += RTA_SPACE(sizeof(*key_param));
+
+		/*
+		 * Copy authentication key
+		 */
+		memcpy(p, keys->auth_key, keys->auth_keylen);
+		p += keys->auth_keylen;
+
+		/*
+		 * Copy cipher Key
+		 */
+		key_param->enckeylen = cpu_to_be32(keys->cipher_keylen);
+		memcpy(p, keys->cipher_key, keys->cipher_keylen);
+
+		if (crypto_aead_setkey(sa->aead, rt_keys, keylen)) {
+			nss_ipsecmgr_warn("%px: failed to configure keys\n", sa);
+			crypto_free_aead(sa->aead);
+			sa->aead = NULL;
+			vfree(rt_keys);
+			return NSS_IPSECMGR_INVALID_KEYLEN;
+		}
+
+		nss_cryptoapi_aead_ctx2session(sa->aead, &index);
+		data->blk_len = (uint8_t)crypto_aead_blocksize(sa->aead);
+		data->iv_len = (uint8_t)crypto_aead_ivsize(sa->aead);
+		data->icv_len = cmn->icv_len;
+		tuple->crypto_index = (uint16_t)index;
+		vfree(rt_keys);
+		break;
+
+	/*
+	 * AHASH Algorithms
+	 */
+	case NSS_IPSECMGR_ALGO_NULL_CIPHER_SHA1_HMAC:
+	case NSS_IPSECMGR_ALGO_NULL_CIPHER_SHA256_HMAC:
+		sa->ahash = crypto_alloc_ahash(ipsecmgr_algo_name[cmn->algo], 0, 0);
+		if (IS_ERR(sa->ahash)) {
+			nss_ipsecmgr_warn("%px: failed to allocate crypto ahash context\n", sa);
+			return NSS_IPSECMGR_FAIL_NOCRYPTO;
+		}
+
+		if (crypto_ahash_setkey(sa->ahash, keys->auth_key, keys->auth_keylen)) {
+			nss_ipsecmgr_warn("%px: failed to configure keys\n", sa);
+			crypto_free_ahash(sa->ahash);
+			sa->ahash = NULL;
+			return NSS_IPSECMGR_INVALID_KEYLEN;
+		}
+
+		nss_cryptoapi_ahash_ctx2session(sa->ahash, &index);
+		data->flags |= NSS_IPSEC_CMN_FLAG_CIPHER_NULL;
+		data->icv_len = cmn->icv_len;
+		data->blk_len = 0;
+		data->iv_len = 0;
+		tuple->crypto_index = (uint16_t)index;
+		break;
+
+	/*
+	 * GCM Mode
+	 */
+	case NSS_IPSECMGR_ALGO_AES_GCM_GMAC_RFC4106:
+		sa->aead = crypto_alloc_aead(ipsecmgr_algo_name[cmn->algo], 0, 0);
+		if (IS_ERR(sa->aead)) {
+			nss_ipsecmgr_warn("%px: failed to allocate crypto aead context\n", sa);
+			return NSS_IPSECMGR_FAIL_NOCRYPTO;
+		}
+
+		keylen = keys->cipher_keylen + keys->nonce_size;
+
+		/*
+		 * Construct key with nonce
+		 */
+		rt_keys = vzalloc(keylen);
+		if (!rt_keys) {
+			nss_ipsecmgr_warn("%px: failed to allocate key memory\n", sa);
+			crypto_free_aead(sa->aead);
+			sa->aead = NULL;
+			return NSS_IPSECMGR_FAIL_NOMEM;
+		}
+
+		memcpy(rt_keys, keys->cipher_key, keys->cipher_keylen);
+		memcpy(rt_keys + keys->cipher_keylen, (uint8_t *)keys->nonce, keys->nonce_size);
+
+		if (crypto_aead_setkey(sa->aead, rt_keys, keylen)) {
+			nss_ipsecmgr_warn("%px: failed to configure keys\n", sa);
+			crypto_free_aead(sa->aead);
+			sa->aead = NULL;
+			vfree(rt_keys);
+			return NSS_IPSECMGR_INVALID_KEYLEN;
+		}
+
+		nss_cryptoapi_aead_ctx2session(sa->aead, &index);
+		data->blk_len = (uint8_t)crypto_aead_blocksize(sa->aead);
+		data->iv_len = (uint8_t)crypto_aead_ivsize(sa->aead);
+		data->icv_len = cmn->icv_len;
+		data->flags |= NSS_IPSEC_CMN_FLAG_CIPHER_GCM;
+		tuple->crypto_index = (uint16_t)index;
+		vfree(rt_keys);
+		break;
+
+	default:
+		nss_ipsecmgr_warn("%px: invalid crypto algorithm\n", sa);
+		return NSS_IPSECMGR_INVALID_ALGO;
+	}
+
+	return NSS_IPSECMGR_OK;
+}
+
+/*
+ * nss_ipsecmgr_sa_free()
+ *	Free the SA entry and any associated crypto context
+ */
+static void nss_ipsecmgr_sa_free(struct nss_ipsecmgr_sa *sa)
+{
+	if (sa->aead) {
+		crypto_free_aead(sa->aead);
+		sa->aead = NULL;
+	}
+
+	if (sa->ahash) {
+		crypto_free_ahash(sa->ahash);
+		sa->ahash = NULL;
+	}
+
+	kfree(sa);
+}
+
+/*
+ * nss_ipsecmgr_sa_del_ref()
+ *	Detach the SA entry from the list
+ */
+static void nss_ipsecmgr_sa_del_ref(struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_sa *sa = container_of(ref, struct nss_ipsecmgr_sa, ref);
+	struct nss_ipsecmgr_tunnel *tun = NULL;
+	struct net_device *dev;
+
+	/*
+	 * Linux does not provide any specific API(s) to test for RW locks. The caller
+	 * being internal is assumed to hold write lock before initiating this.
+	 */
+	nss_ipsecmgr_write_lock_is_held(&ipsecmgr_drv->lock);
+
+	list_del_init(&sa->list);
+
+	dev = dev_get_by_index(&init_net, sa->tunnel_id);
+	if (!dev) {
+		nss_ipsecmgr_trace("%px: Failed to find dev for tunnel-ID(%u)", sa, sa->tunnel_id);
+		return;
+	}
+
+	/*
+	 * Check the default transmit SA; if it matches then we clear it
+	 */
+	tun = netdev_priv(dev);
+	if (tun->tx_sa == sa) {
+		tun->tx_sa = NULL;
+	}
+
+	dev_put(dev);
+}
+
+/*
+ * nss_ipsecmgr_sa_free_ref()
+ *	Detach the SA entry from the list
+ */
+static void nss_ipsecmgr_sa_free_ref(struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_sa *sa = container_of(ref, struct nss_ipsecmgr_sa, ref);
+	enum nss_ipsec_cmn_msg_type type = NSS_IPSEC_CMN_MSG_TYPE_SA_DESTROY;
+	struct nss_ipsec_cmn_msg nicm;
+	nss_tx_status_t status;
+
+	/*
+	 * The free path can potentially sleep hence we detach the SA here but
+	 * free it later
+	 */
+	memset(&nicm, 0, sizeof(nicm));
+	memcpy(&nicm.msg.sa.sa_tuple, &sa->state.tuple, sizeof(nicm.msg.sa.sa_tuple));
+
+	status = nss_ipsec_cmn_tx_msg_sync(sa->nss_ctx, sa->ifnum, type, sizeof(nicm.msg.sa), &nicm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ipsecmgr_warn("%px: Failed to send message(%u) to NSS(%u)", sa->nss_ctx, type, status);
+	}
+
+	nss_ipsecmgr_sa_free(sa);
+}
+
+/*
+ * nss_ipsecmgr_sa_alloc()
+ *	Allocate SA and initialize it
+ */
+static struct nss_ipsecmgr_sa *nss_ipsecmgr_sa_alloc(struct nss_ipsecmgr_ctx *ctx)
+{
+	struct nss_ipsecmgr_tunnel *tun = ctx->tun;
+	struct nss_ipsecmgr_sa *sa;
+
+	/*
+	 * Allocate the SA entry
+	 */
+	sa = kzalloc(sizeof(*sa), GFP_ATOMIC);
+	if (!sa) {
+		nss_ipsecmgr_warn("%px: Failed to allocate SA", ctx);
+		return NULL;
+	}
+
+	sa->tunnel_id = tun->dev->ifindex;
+	sa->type = ctx->state.type;
+	sa->nss_ctx = ctx->nss_ctx;
+	sa->ifnum = ctx->ifnum;
+	sa->cb = tun->cb;
+
+	INIT_LIST_HEAD(&sa->list);
+	nss_ipsecmgr_ref_init(&sa->ref, nss_ipsecmgr_sa_del_ref, nss_ipsecmgr_sa_free_ref);
+	nss_ipsecmgr_ref_init_print(&sa->ref, nss_ipsecmgr_sa_print_len, nss_ipsecmgr_sa_print);
+
+	return sa;
+}
+
+/*
+ * nss_ipsecmgr_sa_update_db()
+ *	Update SA database
+ */
+static bool nss_ipsecmgr_sa_update_db(struct nss_ipsecmgr_sa *sa)
+{
+	struct list_head *db = ipsecmgr_drv->sa_db;
+	struct nss_ipsecmgr_tunnel *tun;
+	struct nss_ipsecmgr_ctx *ctx;
+	struct net_device *dev;
+	uint32_t hash_idx;
+
+	dev = dev_get_by_index(&init_net, sa->tunnel_id);
+	if (!dev) {
+		nss_ipsecmgr_warn("%px: Failed to find tunnel(%d) between SA creation\n", sa, sa->tunnel_id);
+		return false;
+	}
+
+	tun = netdev_priv(dev);
+
+	write_lock_bh(&ipsecmgr_drv->lock);
+
+	ctx = nss_ipsecmgr_ctx_find(tun, sa->type);
+	if (!ctx) {
+		nss_ipsecmgr_warn("%px: Failed to find context (%u) between SA creation\n", sa, sa->type);
+		write_unlock_bh(&ipsecmgr_drv->lock);
+		dev_put(dev);
+		return false;
+	}
+
+	/*
+	 * Save the SA for default TX on tunnel if enabled
+	 */
+	if (sa->state.tx_default) {
+		tun->tx_sa = sa;
+	}
+
+	/*
+	 * Compute the hash index and add SA reference to the context.
+	 */
+	hash_idx = nss_ipsecmgr_sa_tuple2hash(&sa->state.tuple, NSS_IPSECMGR_SA_MAX);
+
+	nss_ipsecmgr_ref_add(&sa->ref, &ctx->ref);
+	list_add(&sa->list, &db[hash_idx]);
+	write_unlock_bh(&ipsecmgr_drv->lock);
+
+	dev_put(dev);
+	return true;
+}
+
+/*
+ * nss_ipsecmgr_sa_create_resp()
+ *	SA create response callback
+ */
+static void nss_ipsecmgr_sa_create_resp(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_ipsecmgr_sa *sa = app_data;
+
+	if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+#ifdef NSS_IPSECMGR_DEBUG
+		if (ncm->error == NSS_IPSEC_CMN_MSG_ERROR_SA_DUP) {
+			write_lock_bh(&ipsecmgr_drv->lock);
+			if (!nss_ipsecmgr_sa_find(ipsecmgr_drv->sa_db, &sa->state.tuple)) {
+				nss_ipsecmgr_trace("%px: Duplicate SA in FW not in host (%u)\n", sa, ncm->error);
+			}
+			write_unlock_bh(&ipsecmgr_drv->lock);
+		}
+#endif
+		nss_ipsecmgr_trace("%px: NSS response error (%u)\n", sa, ncm->error);
+		nss_ipsecmgr_sa_free(sa);
+		return;
+	}
+
+	if (!nss_ipsecmgr_sa_update_db(sa)) {
+		nss_ipsecmgr_warn("%px: Failed to update SA database", sa);
+		nss_ipsecmgr_sa_free(sa);
+		return;
+	}
+}
+
+/*
+ * nss_ipsecmgr_sa_init_encap()
+ *	Initialize encapsulation SA
+ */
+static void nss_ipsecmgr_sa_init_encap(struct nss_ipsecmgr_sa *sa, struct nss_ipsecmgr_sa_data *data,
+					struct nss_ipsec_cmn_msg *nicm)
+{
+	struct nss_ipsec_cmn_sa_tuple *sa_tuple = &nicm->msg.sa.sa_tuple;
+	struct nss_ipsec_cmn_sa_data *sa_data = &nicm->msg.sa.sa_data;
+
+	sa_data->df = data->encap.df;
+	sa_data->dscp = data->encap.dscp;
+	sa_data->flags |= data->cmn.enable_natt ? NSS_IPSEC_CMN_FLAG_IPV4_NATT : 0;
+	sa_data->flags |= data->cmn.enable_esn ? NSS_IPSEC_CMN_FLAG_ESP_ESN : 0;
+	sa_data->flags |= data->cmn.skip_trailer ? NSS_IPSEC_CMN_FLAG_ESP_SKIP : 0;
+	sa_data->flags |= data->encap.copy_dscp ? NSS_IPSEC_CMN_FLAG_COPY_DSCP : 0;
+	sa_data->flags |= data->encap.copy_df ? NSS_IPSEC_CMN_FLAG_COPY_DF : 0;
+	sa_data->flags |= data->cmn.transport_mode ? NSS_IPSEC_CMN_FLAG_MODE_TRANS : 0;
+
+	if (sa_tuple->ip_ver == 6) {
+		sa_data->flags &= ~NSS_IPSEC_CMN_FLAG_HDR_MASK;
+		sa_data->flags |= NSS_IPSEC_CMN_FLAG_IPV6;
+	}
+
+	sa_tuple->hop_limit = data->encap.ttl_hop_limit;
+
+	/*
+	 * Copy tuple information for deletion
+	 */
+	memcpy(&sa->state.tuple, sa_tuple, sizeof(sa->state.tuple));
+	memcpy(&sa->state.data, sa_data, sizeof(sa->state.data));
+	sa->state.tx_default = !!data->encap.tx_default;
+
+	nss_ipsecmgr_trace("%px:Encapsulation SA initialized ", sa);
+}
+
+/*
+ * nss_ipsecmgr_sa_init_decap()
+ *	Initialize de-capsulation SA
+ */
+static void nss_ipsecmgr_sa_init_decap(struct nss_ipsecmgr_sa *sa, struct nss_ipsecmgr_sa_data *data,
+					struct nss_ipsec_cmn_msg *nicm)
+{
+	struct nss_ipsec_cmn_sa_tuple *sa_tuple = &nicm->msg.sa.sa_tuple;
+	struct nss_ipsec_cmn_sa_data *sa_data = &nicm->msg.sa.sa_data;
+
+	sa_data->window_size = data->decap.replay_win;
+
+	sa_data->flags |= data->cmn.enable_natt ? NSS_IPSEC_CMN_FLAG_IPV4_NATT : 0;
+	sa_data->flags |= data->cmn.enable_esn ? NSS_IPSEC_CMN_FLAG_ESP_ESN : 0;
+	sa_data->flags |= data->cmn.skip_trailer ? NSS_IPSEC_CMN_FLAG_ESP_SKIP : 0;
+	sa_data->flags |= data->cmn.transport_mode ? NSS_IPSEC_CMN_FLAG_MODE_TRANS : 0;
+	sa_data->flags |= data->decap.replay_win ? NSS_IPSEC_CMN_FLAG_ESP_REPLAY : 0;
+
+	if (sa_tuple->ip_ver == 6) {
+		sa_data->flags &= ~NSS_IPSEC_CMN_FLAG_HDR_MASK;
+		sa_data->flags |= NSS_IPSEC_CMN_FLAG_IPV6;
+	}
+
+	/*
+	 * Copy tuple information for deletion
+	 */
+	memcpy(&sa->state.tuple, sa_tuple, sizeof(sa->state.tuple));
+	memcpy(&sa->state.data, sa_data, sizeof(sa->state.data));
+
+	nss_ipsecmgr_trace("%px:Decapsulation SA initialized ", sa);
+}
+
+/*
+ * nss_ipsecmgr_sa_sync_state()
+ *	Update SA sync state
+ */
+void nss_ipsecmgr_sa_sync2stats(struct nss_ipsecmgr_sa *sa, struct nss_ipsec_cmn_sa_sync *sync,
+					struct nss_ipsecmgr_sa_stats *stats)
+{
+	struct nss_ipsec_cmn_sa_stats *sa_stats = &sync->stats;
+	struct nss_ipsec_cmn_sa_data *sa_data = &sa->state.data;
+	uint32_t *drop_counters;
+	size_t num_counters;
+	int i;
+
+	nss_ipsecmgr_sa_tuple2sa(&sync->sa_tuple, &stats->sa);
+
+	switch (sa->type) {
+	case NSS_IPSEC_CMN_CTX_TYPE_INNER:
+	case NSS_IPSEC_CMN_CTX_TYPE_MDATA_INNER:
+		stats->pkt_count = sa_stats->cmn_stats.tx_packets;
+		stats->pkt_bytes = sa_stats->cmn_stats.tx_bytes;
+		break;
+
+	case NSS_IPSEC_CMN_CTX_TYPE_OUTER:
+	case NSS_IPSEC_CMN_CTX_TYPE_MDATA_OUTER:
+		stats->pkt_count = sa_stats->cmn_stats.rx_packets;
+		stats->pkt_bytes = sa_stats->cmn_stats.rx_bytes;
+		break;
+	default:
+		return;
+
+	}
+
+	stats->pkt_failed = 0;
+	for (i = 0; i < ARRAY_SIZE(sa_stats->cmn_stats.rx_dropped); i++)
+		stats->pkt_failed += sa_stats->cmn_stats.rx_dropped[i];
+
+	/*
+	 * Drop counters starts after common stats counters
+	 */
+	drop_counters = (uint32_t *)((uint8_t *)sa_stats + sizeof(sa_stats->cmn_stats));
+	num_counters = (sizeof(*sa_stats) - sizeof(sa_stats->cmn_stats)) / sizeof(uint32_t);
+
+	for (i = 0; i < num_counters; i++)
+		stats->pkt_failed += drop_counters[i];
+
+	if (sa_data->window_size) {
+		stats->window_size = sa_data->window_size;
+		stats->seq_start = sync->replay.seq_start;
+		stats->seq_cur = sync->replay.seq_cur;
+	}
+
+	stats->fail_replay_win = sa_stats->fail_replay_win;
+	stats->fail_replay_dup = sa_stats->fail_replay_dup;
+	stats->fail_auth = sa_stats->fail_auth;
+}
+
+/*
+ * nss_ipsecmgr_sa_sync_state()
+ *	Update SA sync state
+ */
+void nss_ipsecmgr_sa_sync_state(struct nss_ipsecmgr_sa *sa, struct nss_ipsec_cmn_sa_sync *sa_sync)
+{
+	uint32_t *msg_stats = (uint32_t *)&sa_sync->stats;
+	uint64_t *sa_stats = (uint64_t *)&sa->stats;
+	int num;
+
+	/*
+	 * DEBUG check to see if the lock is taken before accessing
+	 * SA entry in the database
+	 */
+	nss_ipsecmgr_write_lock_is_held(&ipsecmgr_drv->lock);
+
+	for (num = 0; num < sizeof(sa->stats)/sizeof(*sa_stats); num++) {
+		sa_stats[num] += msg_stats[num];
+	}
+
+	memcpy(&sa->state.replay, &sa_sync->replay, sizeof(sa->state.replay));
+}
+
+/*
+ * nss_ipsecmgr_sa_find()
+ *	Find an SA using a SA tuple
+ */
+struct nss_ipsecmgr_sa *nss_ipsecmgr_sa_find(struct list_head *db, struct nss_ipsec_cmn_sa_tuple *tuple)
+{
+	struct nss_ipsecmgr_sa *sa;
+	uint32_t hash_idx;
+
+	hash_idx = nss_ipsecmgr_sa_tuple2hash(tuple, NSS_IPSECMGR_SA_MAX);
+
+	list_for_each_entry(sa, &db[hash_idx], list) {
+		if (nss_ipsecmgr_sa_tuple_match(&sa->state.tuple, tuple)) {
+			return sa;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_ipsecmgr_sa_del()
+ *	Delete an existing SA
+ */
+void nss_ipsecmgr_sa_del(struct net_device *dev, struct nss_ipsecmgr_sa_tuple *tuple)
+{
+	struct nss_ipsecmgr_tunnel *tun = netdev_priv(dev);
+	struct nss_ipsec_cmn_sa_tuple sa_tuple = {0};
+	struct nss_ipsecmgr_sa *sa;
+
+	nss_ipsecmgr_sa2tuple(tuple, &sa_tuple);
+
+	/*
+	 * Write lock needed here since SA and all related Flows
+	 * are removed from DB. This requires write lock since SA Delete
+	 * might be called in parallel from other cores as well
+	 */
+	write_lock_bh(&ipsecmgr_drv->lock);
+
+	sa = nss_ipsecmgr_sa_find(ipsecmgr_drv->sa_db, &sa_tuple);
+	if (!sa) {
+		write_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_warn("%px: failed to find SA for deletion\n", tun);
+		return;
+	}
+
+	/*
+	 * Free the entire reference hierarchy
+	 */
+	nss_ipsecmgr_ref_del(&sa->ref, &tun->free_refs);
+	write_unlock_bh(&ipsecmgr_drv->lock);
+
+	schedule_work(&tun->free_work);
+}
+EXPORT_SYMBOL(nss_ipsecmgr_sa_del);
+
+/*
+ * nss_ipsecmgr_sa_add()
+ *	Add a new SA for encapsulation or de-capsulation
+ */
+nss_ipsecmgr_status_t nss_ipsecmgr_sa_add(struct net_device *dev, struct nss_ipsecmgr_sa_tuple *tuple,
+					struct nss_ipsecmgr_sa_data *data, uint32_t *ifnum)
+{
+	const enum nss_ipsec_cmn_msg_type type = NSS_IPSEC_CMN_MSG_TYPE_SA_CREATE;
+	struct nss_ipsecmgr_tunnel *tun = netdev_priv(dev);
+	struct nss_ipsec_cmn_sa_tuple *msg_tuple;
+	struct nss_ipsec_cmn_sa_data *msg_data;
+	struct nss_ipsec_cmn_msg nicm = {{0}};
+	struct nss_ipsecmgr_sa *sa = NULL;
+	struct nss_ipsecmgr_ctx *ctx;
+	nss_tx_status_t status;
+
+	dev_hold(dev);
+
+	msg_tuple = &nicm.msg.sa.sa_tuple;
+	msg_data =  &nicm.msg.sa.sa_data;
+
+	nss_ipsecmgr_sa2tuple(tuple, msg_tuple);
+
+	/*
+	 * Check if the SA already exists or not
+	 */
+	read_lock_bh(&ipsecmgr_drv->lock);
+	if (nss_ipsecmgr_sa_find(ipsecmgr_drv->sa_db, msg_tuple)) {
+		read_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_trace("%px: Duplicate SA found", dev);
+		dev_put(dev);
+		return NSS_IPSECMGR_DUPLICATE_SA;
+	}
+
+	ctx = nss_ipsecmgr_ctx_find_by_sa(tun, data->type);
+	if (!ctx) {
+		nss_ipsecmgr_warn("%px: failed to find inner context associated with tunnel", tun);
+		read_unlock_bh(&ipsecmgr_drv->lock);
+		dev_put(dev);
+		return NSS_IPSECMGR_FAIL;
+	}
+
+	/*
+	 * Allocate the SA entry
+	 */
+	sa = nss_ipsecmgr_sa_alloc(ctx);
+	if (!sa) {
+		read_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_warn("%px: Failed to allocate SA for add", ctx);
+		dev_put(dev);
+		return NSS_IPSECMGR_FAIL_NOMEM;
+	}
+
+	/*
+	 * We are done with the net_device release the reference
+	 */
+	dev_put(dev);
+	read_unlock_bh(&ipsecmgr_drv->lock);
+
+	/*
+	 * Allocate crypto resources
+	 */
+	if (nss_ipsecmgr_sa_crypto_alloc(sa, &data->cmn, msg_tuple, msg_data)) {
+		nss_ipsecmgr_warn("%px: Failed to allocate crypto resource for SA add", ctx);
+		nss_ipsecmgr_sa_free(sa);
+		return NSS_IPSECMGR_FAIL_NOCRYPTO;
+	}
+
+	if (data->type == NSS_IPSECMGR_SA_TYPE_ENCAP) {
+		nss_ipsecmgr_sa_init_encap(sa, data, &nicm);
+	} else {
+		nss_ipsecmgr_sa_init_decap(sa, data, &nicm);
+	}
+
+	nss_ipsec_cmn_msg_init(&nicm, sa->ifnum, type, sizeof(nicm.msg.sa), nss_ipsecmgr_sa_create_resp, sa);
+
+	status = nss_ipsec_cmn_tx_msg(sa->nss_ctx, &nicm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ipsecmgr_warn("%px: Failed to send message(%u) to NSS(%u)\n", ctx, type, status);
+		nss_ipsecmgr_sa_free(sa);
+		return NSS_IPSECMGR_FAIL_MESSAGE;
+	}
+
+	*ifnum = nss_ipsec_cmn_get_ifnum_with_coreid(sa->ifnum);
+	return NSS_IPSECMGR_OK;
+}
+EXPORT_SYMBOL(nss_ipsecmgr_sa_add);
+
+/*
+ * nss_ipsecmgr_sa_add_sync()
+ *	Add a new SA for encapsulation or de-capsulation synchronously
+ */
+nss_ipsecmgr_status_t nss_ipsecmgr_sa_add_sync(struct net_device *dev, struct nss_ipsecmgr_sa_tuple *tuple,
+						struct nss_ipsecmgr_sa_data *data, uint32_t *ifnum)
+{
+	const enum nss_ipsec_cmn_msg_type type = NSS_IPSEC_CMN_MSG_TYPE_SA_CREATE;
+	struct nss_ipsecmgr_tunnel *tun = netdev_priv(dev);
+	struct nss_ipsec_cmn_sa_tuple *msg_tuple;
+	struct nss_ipsec_cmn_sa_data *msg_data;
+	struct nss_ipsec_cmn_msg nicm = {{0}};
+	struct nss_ipsecmgr_sa *sa = NULL;
+	struct nss_ipsecmgr_ctx *ctx;
+	nss_tx_status_t status;
+
+	dev_hold(dev);
+
+	msg_tuple = &nicm.msg.sa.sa_tuple;
+	msg_data =  &nicm.msg.sa.sa_data;
+
+	nss_ipsecmgr_sa2tuple(tuple, msg_tuple);
+
+	/*
+	 * Check if the SA already exists or not
+	 */
+	read_lock_bh(&ipsecmgr_drv->lock);
+	if (nss_ipsecmgr_sa_find(ipsecmgr_drv->sa_db, msg_tuple)) {
+		read_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_trace("%px: Duplicate SA found", dev);
+		dev_put(dev);
+		return NSS_IPSECMGR_DUPLICATE_SA;
+	}
+
+	ctx = nss_ipsecmgr_ctx_find_by_sa(tun, data->type);
+	if (!ctx) {
+		nss_ipsecmgr_warn("%px: failed to find inner context associated with tunnel", tun);
+		read_unlock_bh(&ipsecmgr_drv->lock);
+		dev_put(dev);
+		return NSS_IPSECMGR_FAIL;
+	}
+
+	/*
+	 * Allocate the SA entry
+	 */
+	sa = nss_ipsecmgr_sa_alloc(ctx);
+	if (!sa) {
+		read_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_warn("%px: Failed to allocate SA for add", ctx);
+		dev_put(dev);
+		return NSS_IPSECMGR_FAIL_NOMEM;
+	}
+
+	/*
+	 * We are done with the net_device release the reference
+	 */
+	dev_put(dev);
+	read_unlock_bh(&ipsecmgr_drv->lock);
+
+	/*
+	 * Allocate crypto resources
+	 */
+	if (nss_ipsecmgr_sa_crypto_alloc(sa, &data->cmn, msg_tuple, msg_data)) {
+		nss_ipsecmgr_warn("%px: Failed to allocate crypto resource for SA add", ctx);
+		nss_ipsecmgr_sa_free(sa);
+		return NSS_IPSECMGR_FAIL_NOCRYPTO;
+	}
+
+	if (data->type == NSS_IPSECMGR_SA_TYPE_ENCAP) {
+		nss_ipsecmgr_sa_init_encap(sa, data, &nicm);
+	} else {
+		nss_ipsecmgr_sa_init_decap(sa, data, &nicm);
+	}
+
+	nss_ipsec_cmn_msg_init(&nicm, sa->ifnum, type, sizeof(nicm.msg.sa), NULL, NULL);
+
+	status = nss_ipsec_cmn_tx_msg_sync(sa->nss_ctx, sa->ifnum, type, sizeof(nicm.msg.sa), &nicm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ipsecmgr_warn("%px: Failed to send message(%u) to NSS(%u)\n", ctx, type, status);
+		nss_ipsecmgr_sa_free(sa);
+		return NSS_IPSECMGR_FAIL_MESSAGE;
+	}
+
+	/*
+	 * Since, this is a synchronous call add it to the database directly
+	 */
+	if (!nss_ipsecmgr_sa_update_db(sa)) {
+		nss_ipsecmgr_warn("%px: Failed to update SA database", sa);
+		nss_ipsecmgr_sa_free(sa);
+		return NSS_IPSECMGR_FAIL_ADD_DB;
+	}
+
+	*ifnum = nss_ipsec_cmn_get_ifnum_with_coreid(sa->ifnum);
+	return NSS_IPSECMGR_OK;
+}
+EXPORT_SYMBOL(nss_ipsecmgr_sa_add_sync);
+
+/*
+ * nss_ipsecmgr_sa_verify()
+ * 	Confirm SA is present or not for sa tuple.
+ */
+bool nss_ipsecmgr_sa_verify(struct net_device *dev, struct nss_ipsecmgr_sa_tuple *tuple)
+{
+	struct nss_ipsec_cmn_sa_tuple sa_tuple = {0};
+	struct nss_ipsecmgr_sa *sa;
+
+	/*
+	 * Look for an existing SA.
+	 */
+	nss_ipsecmgr_sa2tuple(tuple, &sa_tuple);
+
+	read_lock_bh(&ipsecmgr_drv->lock);
+	sa = nss_ipsecmgr_sa_find(ipsecmgr_drv->sa_db, &sa_tuple);
+	read_unlock_bh(&ipsecmgr_drv->lock);
+
+	return !!sa;
+}
+EXPORT_SYMBOL(nss_ipsecmgr_sa_verify);
+
+/*
+ * nss_ipsecmgr_cra_name2algo()
+ * 	Returns nss_ipsecmgr_algo
+ */
+enum nss_ipsecmgr_algo nss_ipsecmgr_cra_name2algo(const char *cra_name)
+{
+	enum nss_ipsecmgr_algo algo = NSS_IPSECMGR_ALGO_AES_CBC_SHA1_HMAC;
+	const char **algo_name = ipsecmgr_algo_name;
+
+	for (; algo < NSS_IPSECMGR_ALGO_MAX; algo++, algo_name++) {
+		if (!strncmp(cra_name, *algo_name, strlen(*algo_name))) {
+			return algo;
+		}
+	}
+
+	return NSS_IPSECMGR_ALGO_MAX;
+}
+EXPORT_SYMBOL(nss_ipsecmgr_cra_name2algo);
+
+/*
+ * nss_ipsecmgr_sa_get_info()
+ * 	Get Crypto information for an already created SA.
+ */
+bool nss_ipsecmgr_sa_get_info(struct net_device *dev, struct nss_ipsecmgr_sa_tuple *tuple,
+		struct nss_ipsecmgr_sa_info *sa_info)
+{
+	struct nss_ipsec_cmn_sa_tuple sa_tuple = {0};
+	struct nss_ipsecmgr_sa *sa;
+	uint32_t mask;
+
+	/*
+	 * Look for an existing SA.
+	 */
+	nss_ipsecmgr_sa2tuple(tuple, &sa_tuple);
+
+	read_lock_bh(&ipsecmgr_drv->lock);
+	sa = nss_ipsecmgr_sa_find(ipsecmgr_drv->sa_db, &sa_tuple);
+	if (!sa) {
+		read_unlock_bh(&ipsecmgr_drv->lock);
+		return false;
+	}
+
+	sa_info->blk_len = sa->state.data.blk_len;
+	sa_info->iv_len = sa->state.data.iv_len;
+	sa_info->hash_len = sa->state.data.icv_len;
+	sa_info->session_idx = sa->state.tuple.crypto_index;
+
+	sa_info->hdr_len = sizeof(struct ip_esp_hdr) + sa_info->iv_len;
+	mask = NSS_IPSEC_CMN_FLAG_HDR_MASK | NSS_IPSEC_CMN_FLAG_MODE_TRANS;
+
+	switch (sa->state.data.flags & mask) {
+		case NSS_IPSEC_CMN_FLAG_IPV4_NATT | NSS_IPSEC_CMN_FLAG_MODE_TRANS:
+			sa_info->hdr_len += sizeof(struct udphdr);
+			break;
+		case NSS_IPSEC_CMN_FLAG_IPV6 | NSS_IPSEC_CMN_FLAG_MODE_TRANS:
+		case NSS_IPSEC_CMN_FLAG_MODE_TRANS:
+			break;
+		case NSS_IPSEC_CMN_FLAG_IPV4_NATT:
+			sa_info->hdr_len += sizeof(struct iphdr) + sizeof(struct udphdr);
+			break;
+		case NSS_IPSEC_CMN_FLAG_IPV6:
+			sa_info->hdr_len += sizeof(struct ipv6hdr);
+			break;
+		default:
+			sa_info->hdr_len += sizeof(struct iphdr);
+			break;
+	}
+
+	read_unlock_bh(&ipsecmgr_drv->lock);
+
+	/*
+	 * The user of trailer_len should take care of the odd length.
+	 */
+	sa_info->trailer_len = sa_info->blk_len + 1 + sa_info->hash_len;
+
+	return true;
+}
+EXPORT_SYMBOL(nss_ipsecmgr_sa_get_info);
+
+/*
+ * nss_ipsecmgr_sa_tx_inner()
+ * 	Offload given SKB to NSS for inner processing.
+ */
+nss_ipsecmgr_status_t nss_ipsecmgr_sa_tx_inner(struct net_device *dev, struct nss_ipsecmgr_sa_tuple *tuple,
+					struct sk_buff *skb)
+{
+	struct nss_ipsecmgr_tunnel *tun = netdev_priv(dev);
+	nss_ipsecmgr_status_t status = NSS_IPSECMGR_OK;
+	struct nss_ipsec_cmn_sa_tuple sa_tuple = {0};
+	struct nss_ipsec_cmn_mdata_encap *enc_mdata;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_ipsecmgr_ctx *ctx;
+	struct nss_ipsecmgr_sa *sa;
+	nss_tx_status_t tx_status;
+	uint16_t data_len;
+	uint32_t ifnum;
+
+	BUG_ON(skb_shared(skb));
+	WARN_ON(skb_is_nonlinear(skb) || skb_has_frag_list(skb));
+
+	dev_hold(dev);
+
+	nss_ipsecmgr_sa2tuple(tuple, &sa_tuple);
+	read_lock_bh(&ipsecmgr_drv->lock);
+
+	/*
+	 * Look for an existing SA.
+	 */
+	sa = nss_ipsecmgr_sa_find(ipsecmgr_drv->sa_db, &sa_tuple);
+	if (unlikely(!sa)) {
+		read_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_warn("%px: Failed to find SA", tun);
+		status = NSS_IPSECMGR_INVALID_SA;
+		goto done;
+	}
+
+	ctx = nss_ipsecmgr_ctx_find(tun, NSS_IPSEC_CMN_CTX_TYPE_MDATA_INNER);
+	if (unlikely(!ctx)) {
+		read_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_warn("%px: Failed to find context(%u)", tun, NSS_IPSEC_CMN_CTX_TYPE_MDATA_INNER);
+		status = NSS_IPSECMGR_INVALID_CTX;
+		goto done;
+	}
+
+	ifnum = ctx->ifnum;
+	nss_ctx = ctx->nss_ctx;
+	data_len = skb->len;
+
+	/*
+	 * Expand data area to cover tailroom used by NSS.
+	 */
+	skb_put(skb, dev->needed_tailroom);
+
+	/*
+	 * Add metadata and send SKB to IPsec meta data inner node for encapsulation.
+	 */
+	enc_mdata = nss_ipsecmgr_tunnel_push_mdata(skb);
+	enc_mdata->sa = sa->state.tuple;
+	enc_mdata->data_len = data_len;
+
+	read_unlock_bh(&ipsecmgr_drv->lock);
+
+	/*
+	 * Send the packet to NSS
+	 */
+	tx_status = nss_ipsec_cmn_tx_buf(nss_ctx, skb, ifnum);
+	if (unlikely(tx_status != NSS_TX_SUCCESS)) {
+		nss_ipsecmgr_warn("%px: Failed to send buffer to NSS; error(%u)", tun, tx_status);
+		nss_ipsecmgr_tunnel_pull_mdata(skb);
+		skb_trim(skb, data_len);
+		status = NSS_IPSECMGR_FAIL;
+		goto done;
+	}
+
+done:
+	dev_put(dev);
+	return status;
+}
+EXPORT_SYMBOL(nss_ipsecmgr_sa_tx_inner);
+
+/*
+ * nss_ipsecmgr_sa_tx_outer()
+ * 	Offload given SKB to NSS for outer processing.
+ */
+nss_ipsecmgr_status_t nss_ipsecmgr_sa_tx_outer(struct net_device *dev, struct nss_ipsecmgr_sa_tuple *tuple,
+					struct sk_buff *skb)
+{
+	struct nss_ipsecmgr_tunnel *tun = netdev_priv(dev);
+	nss_ipsecmgr_status_t status = NSS_IPSECMGR_OK;
+	struct nss_ipsec_cmn_sa_tuple sa_tuple = {0};
+	struct nss_ipsec_cmn_mdata_decap *dec_mdata;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_ipsecmgr_ctx *ctx;
+	struct nss_ipsecmgr_sa *sa;
+	nss_tx_status_t tx_status;
+	uint32_t ifnum;
+
+	BUG_ON(skb_shared(skb));
+
+	dev_hold(dev);
+
+	nss_ipsecmgr_sa2tuple(tuple, &sa_tuple);
+	read_lock_bh(&ipsecmgr_drv->lock);
+
+	/*
+	 * Look for an existing SA.
+	 */
+	sa = nss_ipsecmgr_sa_find(ipsecmgr_drv->sa_db, &sa_tuple);
+	if (unlikely(!sa)) {
+		read_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_warn("%px: Failed to find SA", tun);
+		status = NSS_IPSECMGR_INVALID_SA;
+		goto done;
+
+	}
+
+	ctx = nss_ipsecmgr_ctx_find(tun, NSS_IPSEC_CMN_CTX_TYPE_MDATA_OUTER);
+	if (unlikely(!ctx)) {
+		read_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_warn("%px: Failed to find context(%u)", tun, NSS_IPSEC_CMN_CTX_TYPE_MDATA_OUTER);
+		status = NSS_IPSECMGR_INVALID_CTX;
+		goto done;
+
+	}
+
+	ifnum = ctx->ifnum;
+	nss_ctx = ctx->nss_ctx;
+
+	/*
+	 * Add metadata and send SKB to IPsec meta data outer node for decapsulation.
+	 */
+	dec_mdata = nss_ipsecmgr_tunnel_push_mdata(skb);
+	dec_mdata->sa = sa->state.tuple;
+
+	read_unlock_bh(&ipsecmgr_drv->lock);
+
+	/*
+	 * Send the packet to NSS
+	 */
+	tx_status = nss_ipsec_cmn_tx_buf(nss_ctx, skb, ifnum);
+	if (unlikely(tx_status != NSS_TX_SUCCESS)) {
+		nss_ipsecmgr_warn("%px: Failed to send buffer to NSS; error(%u)", tun, tx_status);
+		nss_ipsecmgr_tunnel_pull_mdata(skb);
+		status = NSS_IPSECMGR_FAIL;
+		goto done;
+	}
+
+done:
+	dev_put(dev);
+	return status;
+}
+EXPORT_SYMBOL(nss_ipsecmgr_sa_tx_outer);
diff --git a/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_sa.h b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_sa.h
new file mode 100644
index 0000000..5be17dc
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_sa.h
@@ -0,0 +1,250 @@
+/*
+ * ********************************************************************************
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ **********************************************************************************
+ */
+
+#ifndef __NSS_IPSECMGR_SA_H
+#define __NSS_IPSECMGR_SA_H
+
+#define NSS_IPSECMGR_SA_MAX 64			/**< Maximum number of SA(s) */
+#if (~(NSS_IPSECMGR_SA_MAX - 1) & (NSS_IPSECMGR_SA_MAX >> 1))
+#error "NSS_IPSECMGR_SA_MAX is not a power of 2"
+#endif
+
+#define NSS_IPSECMGR_SA_PRINT_EXTRA 128
+#define NSS_IPSECMGR_SA_FREE_TIMEOUT msecs_to_jiffies(40) /* msecs */
+
+#define NSS_IPSECMGR_ESP_TRAIL_SZ 2 /* esp trailer size */
+#define NSS_IPSECMGR_ESP_PAD_SZ 14 /* maximum amount of padding */
+
+/*
+ * IPsec manager packets stats per SA
+ */
+struct nss_ipsecmgr_sa_stats_priv {
+	/* Packet counters */
+	uint64_t rx_packets;			/**< Number of packets received. */
+	uint64_t rx_bytes;			/**< Number of bytes received. */
+	uint64_t tx_packets;			/**< Number of packets transmitted. */
+	uint64_t tx_bytes;			/**< Number of bytes transmitted. */
+	uint64_t rx_dropped[NSS_MAX_NUM_PRI];	/**< Packets dropped on receive due to queue full. */
+
+	/* Drop counters */
+	uint64_t fail_headroom;			/**< Failed headroom check. */
+	uint64_t fail_tailroom;			/**< Failed tailroom check. */
+	uint64_t fail_replay;			/**< Failure in anti-replay check. */
+	uint64_t fail_replay_dup;		/**< Failure in anti-replay; duplicate records. */
+	uint64_t fail_replay_win;		/**< Failure in anti-replay; packet outside the window. */
+	uint64_t fail_pbuf_crypto;		/**< Failed to allocate crypto pbuf. */
+	uint64_t fail_queue;			/**< Failure due to queue full in IPsec. */
+	uint64_t fail_queue_crypto;		/**< Failure due to queue full in crypto. */
+	uint64_t fail_queue_nexthop;		/**< Failure due to queue full in next_hop. */
+	uint64_t fail_pbuf_alloc;		/**< Failure in pbuf allocation. */
+	uint64_t fail_pbuf_linear;		/**< Failure in pbuf linearization. */
+	uint64_t fail_pbuf_stats;		/**< Failure in pbuf allocation for stats. */
+	uint64_t fail_pbuf_align;		/**< Failure in pbuf access due non-word alignment. */
+	uint64_t fail_cipher;			/**< Failure in decrypting the data. */
+	uint64_t fail_auth;			/**< Failure in authenticating the data. */
+	uint64_t fail_seq_ovf;			/**< Failure due sequence no. roll over. */
+	uint64_t fail_blk_len;			/**< Failure in decap due to bad cipher block len. */
+	uint64_t fail_hash_len;			/**< Failure in decap due to bad hash block len. */
+	uint64_t fail_transform;		/**< Failure in transformation; general error. */
+	uint64_t fail_crypto;			/**< Failure in crypto transformation. */
+	uint64_t fail_cle;			/**< Failure in classification; general failure */
+	uint64_t is_stopped;			/**< Indicates if SA is stopped; eg: seq overflow */
+};
+
+/*
+ * IPsec manager SA state
+ */
+struct nss_ipsecmgr_sa_state {
+	struct nss_ipsec_cmn_sa_tuple tuple;		/* SA tuple */
+	struct nss_ipsec_cmn_sa_data data;		/* SA data */
+	struct nss_ipsec_cmn_sa_replay replay;		/* Per SA replay data */
+	bool tx_default;				/* SA used for tunnel TX */
+};
+
+/*
+ * IPsec manager SA entry
+ */
+struct nss_ipsecmgr_sa {
+	struct list_head list;				/* List node */
+	struct nss_ipsecmgr_ref ref;			/* Reference node */
+
+	struct crypto_aead *aead;			/* Linux crypto AEAD context */
+	struct crypto_ahash *ahash;			/* Linux crypto AHASH context */
+
+	uint32_t ifnum;					/* Interface number */
+	enum nss_ipsec_cmn_ctx_type type;		/* Type */
+	struct nss_ctx_instance *nss_ctx;		/* NSS context */
+
+	struct nss_ipsecmgr_sa_state state;		/* SA local state */
+	struct nss_ipsecmgr_sa_stats_priv stats;	/* SA statistics */
+
+	int tunnel_id;					/* Linux device index */
+	struct nss_ipsecmgr_callback cb;		/* Callback entry */
+};
+
+/*
+ * nss_ipsecmgr_sa_ntoh_v6addr()
+ *	Network to host order
+ */
+static inline void nss_ipsecmgr_sa_ntoh_v6addr(uint32_t *dest, uint32_t *src)
+{
+	dest[0] = ntohl(src[0]);
+	dest[1] = ntohl(src[1]);
+	dest[2] = ntohl(src[2]);
+	dest[3] = ntohl(src[3]);
+}
+
+/*
+ * nss_ipsecmgr_sa_tuple2index()
+ * 	Change tuple to hash index
+ */
+static inline uint32_t nss_ipsecmgr_sa_tuple2hash(struct nss_ipsec_cmn_sa_tuple *tuple, uint32_t max)
+{
+	uint32_t val = 0;
+
+	val ^= tuple->dest_ip[0];
+	val ^= tuple->src_ip[0];
+	val ^= tuple->dest_ip[1];
+	val ^= tuple->src_ip[1];
+	val ^= tuple->dest_ip[2];
+	val ^= tuple->src_ip[2];
+	val ^= tuple->dest_ip[3];
+	val ^= tuple->src_ip[3];
+	val ^= tuple->spi_index;
+	val ^= tuple->protocol;
+	val ^= tuple->ip_ver;
+
+	return val & (max - 1);
+}
+
+/*
+ * nss_ipsecmgr_sa_tuple_match()
+ * 	Match flow tuple
+ */
+static inline bool nss_ipsecmgr_sa_tuple_match(struct nss_ipsec_cmn_sa_tuple *d, struct nss_ipsec_cmn_sa_tuple *s)
+{
+	uint32_t status = 0;
+
+	switch (d->ip_ver) {
+	case IPVERSION:
+		status += d->dest_ip[0] ^ s->dest_ip[0];
+		status += d->src_ip[0] ^ s->src_ip[0];
+		status += d->spi_index ^ s->spi_index;
+		status += d->protocol ^ s->protocol;
+		status += d->ip_ver ^ s->ip_ver;
+		return !status;
+
+	default:
+		status += d->dest_ip[0] ^ s->dest_ip[0];
+		status += d->dest_ip[1] ^ s->dest_ip[1];
+		status += d->dest_ip[2] ^ s->dest_ip[2];
+		status += d->dest_ip[3] ^ s->dest_ip[3];
+		status += d->src_ip[0] ^ s->src_ip[0];
+		status += d->src_ip[1] ^ s->src_ip[1];
+		status += d->src_ip[2] ^ s->src_ip[2];
+		status += d->src_ip[3] ^ s->src_ip[3];
+		status += d->spi_index ^ s->spi_index;
+		status += d->protocol ^ s->protocol;
+		status += d->ip_ver ^ s->ip_ver;
+		return !status;
+	}
+}
+
+/*
+ * nss_ipsecmgr_sa_tuple2sa()
+ *	Convert tuple to sa
+ */
+static inline void nss_ipsecmgr_sa_tuple2sa(struct nss_ipsec_cmn_sa_tuple *tuple, struct nss_ipsecmgr_sa_tuple *sa)
+{
+	memcpy(sa->dest_ip, tuple->dest_ip, sizeof(sa->dest_ip));
+	memcpy(sa->src_ip, tuple->src_ip, sizeof(sa->src_ip));
+	sa->spi_index = tuple->spi_index;
+	sa->proto_next_hdr = tuple->protocol;
+	sa->ip_version = tuple->ip_ver;
+	sa->sport = tuple->src_port;
+	sa->dport = tuple->dest_port;
+}
+
+/*
+ * nss_ipsecmgr_sa2tuple()
+ *	Convert sa to tuple
+ */
+static inline void nss_ipsecmgr_sa2tuple(struct nss_ipsecmgr_sa_tuple *sa, struct nss_ipsec_cmn_sa_tuple *tuple)
+{
+	memcpy(tuple->dest_ip, sa->dest_ip, sizeof(tuple->dest_ip));
+	memcpy(tuple->src_ip, sa->src_ip, sizeof(tuple->src_ip));
+	tuple->spi_index = sa->spi_index;
+	tuple->protocol = sa->proto_next_hdr;
+	tuple->ip_ver = sa->ip_version;
+	tuple->src_port = sa->sport;
+	tuple->dest_port = sa->dport;
+}
+
+/*
+ * nss_ipsecmgr_sa_ipv4_outer2tuple()
+ * 	Change outer IPv4 SA to tuple
+ */
+static inline void nss_ipsecmgr_sa_ipv4_outer2tuple(struct iphdr *iph, struct nss_ipsec_cmn_sa_tuple *s)
+{
+	uint8_t *data = (uint8_t *)iph;
+	struct ip_esp_hdr *esph;
+
+	WARN_ON((iph->protocol != IPPROTO_ESP) && (iph->protocol != IPPROTO_UDP));
+
+	s->src_ip[0] = ntohl(iph->saddr);
+	s->dest_ip[0] = ntohl(iph->daddr);
+	s->ip_ver = IPVERSION;
+	s->protocol = iph->protocol;
+
+	data += sizeof(*iph);
+
+	if (s->protocol == IPPROTO_UDP)
+		data += sizeof(struct udphdr);
+
+	esph = (struct ip_esp_hdr *)data;
+	s->spi_index = ntohl(esph->spi);
+}
+
+/*
+ * nss_ipsecmgr_sa_ipv6_outer2tuple()
+ * 	Change inner IPv6 SA to tuple
+ */
+static inline void nss_ipsecmgr_sa_ipv6_outer2tuple(struct ipv6hdr *ip6h, struct nss_ipsec_cmn_sa_tuple *s)
+{
+	uint8_t *data = (uint8_t *)ip6h;
+	struct ip_esp_hdr *esph;
+
+	nss_ipsecmgr_sa_ntoh_v6addr(s->src_ip, ip6h->saddr.s6_addr32);
+	nss_ipsecmgr_sa_ntoh_v6addr(s->dest_ip, ip6h->daddr.s6_addr32);
+
+	s->protocol = ip6h->nexthdr;
+	s->ip_ver = 6;
+
+	WARN_ON(ip6h->nexthdr != IPPROTO_ESP);
+
+	data += sizeof(*ip6h);
+
+	esph = (struct ip_esp_hdr *)data;
+	s->spi_index = ntohl(esph->spi);
+}
+
+/* functions to operate on SA object */
+struct nss_ipsecmgr_sa *nss_ipsecmgr_sa_find(struct list_head *db, struct nss_ipsec_cmn_sa_tuple *tuple);
+void nss_ipsecmgr_sa_sync_state(struct nss_ipsecmgr_sa *sa, struct nss_ipsec_cmn_sa_sync *sync);
+void nss_ipsecmgr_sa_sync2stats(struct nss_ipsecmgr_sa *sa, struct nss_ipsec_cmn_sa_sync *sync, struct nss_ipsecmgr_sa_stats *stats);
+#endif
diff --git a/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_tunnel.c b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_tunnel.c
new file mode 100644
index 0000000..17afd09
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_tunnel.c
@@ -0,0 +1,656 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/* nss_ipsecmgr.c
+ *	NSS to HLOS IPSec Manager
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/of.h>
+#include <linux/ipv6.h>
+#include <linux/skbuff.h>
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/netdevice.h>
+#include <linux/rtnetlink.h>
+#include <linux/etherdevice.h>
+#include <linux/vmalloc.h>
+#include <linux/debugfs.h>
+#include <linux/atomic.h>
+#include <net/protocol.h>
+#include <net/route.h>
+#include <net/ip6_route.h>
+#include <net/esp.h>
+#include <net/xfrm.h>
+#include <net/icmp.h>
+
+#include <crypto/aead.h>
+#include <crypto/skcipher.h>
+#include <crypto/internal/hash.h>
+
+#include <nss_api_if.h>
+#include <nss_ipsec_cmn.h>
+#include <nss_ipsecmgr.h>
+#include <nss_cryptoapi.h>
+
+#include "nss_ipsecmgr_ref.h"
+#include "nss_ipsecmgr_flow.h"
+#include "nss_ipsecmgr_sa.h"
+#include "nss_ipsecmgr_ctx.h"
+#include "nss_ipsecmgr_tunnel.h"
+#include "nss_ipsecmgr_priv.h"
+
+/*
+ * nss_ipsecmgr_tunnel_open()
+ *	open the tunnel for usage
+ */
+static int nss_ipsecmgr_tunnel_open(struct net_device *dev)
+{
+	struct nss_ipsecmgr_tunnel *tun __attribute__((unused)) = netdev_priv(dev);
+
+	netif_start_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_ipsecmgr_tunnel_stop()
+ *	stop the IPsec tunnel
+ */
+static int nss_ipsecmgr_tunnel_stop(struct net_device *dev)
+{
+	struct nss_ipsecmgr_tunnel *tun __attribute__((unused)) = netdev_priv(dev);
+
+	netif_stop_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_ipsecmgr_tunnel_tx()
+ *	tunnel transmit function
+ */
+static netdev_tx_t nss_ipsecmgr_tunnel_tx(struct sk_buff *skb, struct net_device *dev)
+{
+	struct nss_ipsecmgr_tunnel *tun = netdev_priv(dev);
+	struct nss_ipsec_cmn_flow_tuple f_tuple = {{0}};
+	struct nss_ipsec_cmn_mdata_encap *mdata;
+	struct nss_ipsec_cmn_sa_tuple *sa_tuple;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_ipsecmgr_flow *flow;
+	struct nss_ipsecmgr_ctx *ctx;
+	struct nss_ipsecmgr_sa *sa;
+	bool expand_skb = false;
+	uint16_t data_len;
+	int nhead, ntail;
+	uint32_t ifnum;
+
+	nhead = dev->needed_headroom;
+	ntail = dev->needed_tailroom;
+
+	/*
+	 * Check if skb is shared
+	 */
+	if (unlikely(skb_shared(skb))) {
+		skb = skb_unshare(skb, in_atomic() ? GFP_ATOMIC : GFP_KERNEL);
+		if (!skb)
+			return NETDEV_TX_OK;
+	}
+
+	/*
+	 * Currently IPsec only supports tunnel mode hence non-IP frames are freed.
+	 * In transport mode we will encapsulate based on the skb->protocol
+	 */
+	switch (ip_hdr(skb)->version) {
+	case IPVERSION:
+		nss_ipsecmgr_flow_ipv4_inner2tuple(ip_hdr(skb), &f_tuple);
+		break;
+
+	case 6:
+		nss_ipsecmgr_flow_ipv6_inner2tuple(ipv6_hdr(skb), &f_tuple);
+		break;
+
+	default:
+		nss_ipsecmgr_warn("%px: Non-IP packet for encapsulation", dev);
+		goto free;
+	}
+
+	/*
+	 * Linearize the nonlinear SKB.
+	 */
+	if (skb_linearize(skb)) {
+		nss_ipsecmgr_trace("%s: unable to Linearize SKB\n", dev->name);
+		goto free;
+	}
+
+	/*
+	 * For all these cases
+	 * - create a writable copy of buffer
+	 * - increase the head room
+	 * - increase the tail room
+	 */
+	if (skb_cloned(skb) || (skb_headroom(skb) < nhead) || (skb_tailroom(skb) < ntail)) {
+		expand_skb = true;
+	}
+
+	if (expand_skb && pskb_expand_head(skb, nhead, ntail, GFP_KERNEL)) {
+		nss_ipsecmgr_trace("%s: unable to expand buffer\n", dev->name);
+		goto free;
+	}
+
+	/*
+	 * This packet is ready for NSS transformation. We will now insert the
+	 * metadata on top of the IP header and expand data area to cover tailroom for NSS.
+	 */
+	data_len = skb->len;
+	skb_put(skb, ntail);
+	mdata = nss_ipsecmgr_tunnel_push_mdata(skb);
+
+	read_lock_bh(&ipsecmgr_drv->lock);
+
+	ctx = nss_ipsecmgr_ctx_find(tun, NSS_IPSEC_CMN_CTX_TYPE_MDATA_INNER);
+	if (!ctx) {
+		read_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_warn("%px: failed to find inner metdata context for TX\n", tun);
+		goto free;
+	}
+
+	/*
+	 * Check if default SA is configured in tunnel. If found, fill sa_tuple in
+	 * metadata to be used for encap.
+	 */
+	sa = tun->tx_sa;
+	if (sa) {
+		sa_tuple = &sa->state.tuple;
+		goto fill_mdata;
+	}
+
+	/*
+	 * We search the flow if this has been programmed prior to sending the packets. If flow
+	 * is found, we send corresponding sa_tuple as metadata for encap, else drop the packet.
+	 */
+	flow = nss_ipsecmgr_flow_find(ipsecmgr_drv->flow_db, &f_tuple);
+	if (!flow) {
+		read_unlock_bh(&ipsecmgr_drv->lock);
+		nss_ipsecmgr_trace("%px, failed to find flow for TX", tun);
+		goto free;
+	}
+
+	sa_tuple = &flow->state.sa;
+
+fill_mdata:
+	mdata->flags = 0;
+	mdata->seq_num = 0;
+	mdata->sa = *sa_tuple;
+	mdata->data_len = data_len;
+
+	ifnum = ctx->ifnum;
+	nss_ctx = ctx->nss_ctx;
+	read_unlock_bh(&ipsecmgr_drv->lock);
+
+	/*
+	 * We are not expecting the packet to host; hence scrub it.
+	 * In case of exception the packet will be encapsulated which
+	 * is different from the one that went for transformation.
+	 *
+	 * Note: The SKB will be orphaned at this point. Ideally, this should
+	 * be charged to NSS pool which allow the accounting of all such buffers.
+	 */
+	skb_scrub_packet(skb, true);
+
+	/*
+	 * Send the packet down;
+	 * TODO: Use stop queue and start queue to restart in case of
+	 * queue full condition
+	 */
+	if (nss_ipsec_cmn_tx_buf(nss_ctx, skb, ifnum) != 0) {
+		goto free;
+	}
+
+	return NETDEV_TX_OK;
+
+free:
+	dev_kfree_skb_any(skb);
+	return NETDEV_TX_OK;
+}
+
+/*
+ * nss_ipsecmgr_tunnel_get_stats64()
+ *	Get device statistics
+ */
+static struct rtnl_link_stats64 *nss_ipsecmgr_tunnel_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	struct nss_ipsecmgr_tunnel *tun = netdev_priv(dev);
+	struct list_head *head = &tun->ctx_db;
+	struct nss_ipsecmgr_ctx *ctx;
+
+	memset(stats, 0, sizeof(*stats));
+
+	read_lock_bh(&ipsecmgr_drv->lock);
+	list_for_each_entry(ctx, head, list) {
+		nss_ipsecmgr_ctx_stats_read(ctx, stats);
+	}
+
+	read_unlock_bh(&ipsecmgr_drv->lock);
+	return stats;
+}
+
+/*
+ * nss_ipsecmgr_tunnel_stats64()
+ *	Sync statistics to linux
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0))
+static struct rtnl_link_stats64 *nss_ipsecmgr_tunnel_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	return nss_ipsecmgr_tunnel_get_stats64(dev, stats);
+}
+#else
+static void nss_ipsecmgr_tunnel_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	nss_ipsecmgr_tunnel_get_stats64(dev, stats);
+}
+#endif
+
+/*
+ * nss_ipsecmgr_tunnel_mtu_update()
+ *	Update tunnel max MTU
+ */
+static void nss_ipsecmgr_tunnel_mtu_update(struct list_head *head)
+{
+	struct nss_ipsecmgr_tunnel *tun;
+	uint16_t max_mtu = 0;
+	bool update_mtu = false;
+
+	write_lock(&ipsecmgr_drv->lock);
+	list_for_each_entry(tun, head, list) {
+		if (tun->dev->mtu > max_mtu)
+			max_mtu = tun->dev->mtu;
+	}
+
+	if (ipsecmgr_drv->max_mtu != max_mtu) {
+		ipsecmgr_drv->max_mtu = max_mtu;
+		update_mtu = true;
+	}
+
+	write_unlock(&ipsecmgr_drv->lock);
+
+#ifdef NSS_IPSECMGR_PPE_SUPPORT
+	/*
+	 * Set PPE inline port's MTU.
+	 * TODO: this needs to move to Virtual Port
+	 */
+	if (ipsecmgr_drv->ipsec_inline && update_mtu) {
+		struct nss_ipsecmgr_ctx *ctx;
+		uint32_t redir_ifnum;
+
+		read_lock_bh(&ipsecmgr_drv->lock);
+		ctx = nss_ipsecmgr_ctx_find(netdev_priv(ipsecmgr_drv->dev), NSS_IPSEC_CMN_CTX_TYPE_REDIR);
+		if (!ctx) {
+			read_unlock_bh(&ipsecmgr_drv->lock);
+			nss_ipsecmgr_warn("Unable to find REDIR interface for %s", ipsecmgr_drv->dev->name);
+			return;
+		}
+		redir_ifnum = ctx->ifnum;
+		read_unlock_bh(&ipsecmgr_drv->lock);
+
+		nss_ipsecmgr_info("Updating mtu for %s as %d", ipsecmgr_drv->dev->name, max_mtu);
+		nss_ipsec_cmn_ppe_mtu_update(ipsecmgr_drv->nss_ctx, redir_ifnum, max_mtu, max_mtu);
+	}
+#endif
+}
+
+/*
+ * nss_ipsecmgr_tunnel_mtu()
+ *	Change device MTU
+ */
+static int nss_ipsecmgr_tunnel_mtu(struct net_device *dev, int mtu)
+{
+	dev->mtu = mtu;
+	nss_ipsecmgr_tunnel_mtu_update(&ipsecmgr_drv->tun_db);
+	return 0;
+}
+
+/* NSS IPsec tunnel operation */
+static const struct net_device_ops ipsecmgr_dev_ops = {
+	.ndo_open = nss_ipsecmgr_tunnel_open,
+	.ndo_stop = nss_ipsecmgr_tunnel_stop,
+	.ndo_start_xmit = nss_ipsecmgr_tunnel_tx,
+	.ndo_get_stats64 = nss_ipsecmgr_tunnel_stats64,
+	.ndo_change_mtu = nss_ipsecmgr_tunnel_mtu,
+};
+
+/*
+ * nss_ipsecmgr_tunnel_free()
+ *	free an existing IPsec tunnel interface
+ */
+static void nss_ipsecmgr_tunnel_free(struct net_device *dev)
+{
+	struct nss_ipsecmgr_tunnel *tun = netdev_priv(dev);
+	struct nss_ipsecmgr_ref *ref, *tmp;
+	struct list_head free_refs;
+
+	nss_ipsecmgr_info("IPsec tunnel device(%s) freed\n", dev->name);
+
+	INIT_LIST_HEAD(&free_refs);
+
+	/*
+	 * Remove context(s) from the tunnel reference tree if it has been
+	 * added
+	 */
+	write_lock_bh(&ipsecmgr_drv->lock);
+	if (!nss_ipsecmgr_ref_is_empty(&tun->ref)) {
+		nss_ipsecmgr_ref_del(&tun->ref, &free_refs);
+	}
+
+	write_unlock_bh(&ipsecmgr_drv->lock);
+
+	list_for_each_entry_safe(ref, tmp, &free_refs, node) {
+		ref->free(ref);
+	}
+
+	free_netdev(dev);
+}
+
+/*
+ * nss_ipsecmgr_tunnel_free_work()
+ *	Drain all pending refs for free
+ */
+static void nss_ipsecmgr_tunnel_free_work(struct work_struct *work)
+{
+	struct nss_ipsecmgr_tunnel *tun = container_of(work, struct nss_ipsecmgr_tunnel, free_work);
+	struct nss_ipsecmgr_ref *ref, *tmp;
+	struct list_head tmp_head;
+	bool is_locked;
+
+	INIT_LIST_HEAD(&tmp_head);
+
+	write_lock_bh(&ipsecmgr_drv->lock);
+	list_splice_tail_init(&tun->free_refs, &tmp_head);
+	write_unlock_bh(&ipsecmgr_drv->lock);
+
+	is_locked = rtnl_trylock();
+	list_for_each_entry_safe(ref, tmp, &tmp_head, node) {
+		ref->free(ref);
+	}
+
+	if (is_locked)
+		rtnl_unlock();
+}
+
+/*
+ * nss_ipsecmgr_tunnel_free_ref()
+ *	Unregister IPsec tunnel interface
+ */
+static void nss_ipsecmgr_tunnel_free_ref(struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_tunnel *tun = container_of(ref, struct nss_ipsecmgr_tunnel, ref);
+
+	/*
+	 * The unregister should start here but the expectation is that the free would
+	 * happen when the reference count goes down to '0'
+	 */
+	if (tun->dev->reg_state == NETREG_REGISTERED) {
+		nss_ipsecmgr_tunnel_mtu_update(&ipsecmgr_drv->tun_db);
+		rtnl_is_locked() ? unregister_netdevice(tun->dev) : unregister_netdev(tun->dev);
+	}
+}
+
+/*
+ * nss_ipsecmgr_tunnel_del_ref()
+ *	Delete IPsec tunnel reference
+ */
+static void nss_ipsecmgr_tunnel_del_ref(struct nss_ipsecmgr_ref *ref)
+{
+	struct nss_ipsecmgr_tunnel *tun = container_of(ref, struct nss_ipsecmgr_tunnel, ref);
+	list_del(&tun->list);
+}
+
+/*
+ * nss_ipsecmr_dev_setup()
+ *	setup the IPsec tunnel
+ */
+static void nss_ipsecmgr_tunnel_setup(struct net_device *dev)
+{
+	dev->addr_len = ETH_ALEN;
+	dev->mtu = NSS_IPSECMGR_TUN_MTU(ETH_DATA_LEN);
+
+	dev->hard_header_len = NSS_IPSECMGR_TUN_MAX_HDR_LEN;
+	dev->needed_headroom = NSS_IPSECMGR_TUN_HEADROOM;
+	dev->needed_tailroom = NSS_IPSECMGR_TUN_TAILROOM;
+
+	dev->type = NSS_IPSEC_CMN_ARPHRD_IPSEC;
+
+	dev->ethtool_ops = NULL;
+	dev->header_ops = NULL;
+	dev->netdev_ops = &ipsecmgr_dev_ops;
+
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 11, 8))
+	dev->destructor = nss_ipsecmgr_tunnel_free;
+#else
+	dev->priv_destructor = nss_ipsecmgr_tunnel_free;
+#endif
+
+	/*
+	 * Get the MAC address from the ethernet device
+	 */
+	random_ether_addr(dev->dev_addr);
+
+	memset(dev->broadcast, 0xff, dev->addr_len);
+	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
+}
+
+/*
+ * nss_ipsecmgr_tunnel_del()
+ *	delete an existing IPsec tunnel
+ */
+void nss_ipsecmgr_tunnel_del(struct net_device *dev)
+{
+	struct nss_ipsecmgr_tunnel *tun = netdev_priv(dev);
+
+	debugfs_remove_recursive(tun->dentry);
+
+	/*
+	 * Flush all associated SA(s) and flow(s) with the tunnel
+	 */
+	write_lock_bh(&ipsecmgr_drv->lock);
+	nss_ipsecmgr_ref_del(&tun->ref, &tun->free_refs);
+	write_unlock_bh(&ipsecmgr_drv->lock);
+
+	schedule_work(&tun->free_work);
+	flush_work(&tun->free_work);
+}
+EXPORT_SYMBOL(nss_ipsecmgr_tunnel_del);
+
+/*
+ * nss_ipsecmgr_tunnel_add()
+ *	add a IPsec pseudo tunnel device
+ */
+struct net_device *nss_ipsecmgr_tunnel_add(struct nss_ipsecmgr_callback *cb)
+{
+	struct nss_ipsecmgr_ctx *inner, *mdata_inner;
+	struct nss_ipsecmgr_ctx *outer, *mdata_outer;
+	struct nss_ipsecmgr_tunnel *tun;
+	struct net_device *skb_dev;
+	struct net_device *dev;
+	int status;
+
+	dev = alloc_netdev(sizeof(*tun), NSS_IPSECMGR_TUN_NAME, NET_NAME_ENUM, nss_ipsecmgr_tunnel_setup);
+	if (!dev) {
+		nss_ipsecmgr_error("unable to allocate a tunnel device\n");
+		return NULL;
+	}
+
+	skb_dev = cb->skb_dev;
+	tun = netdev_priv(dev);
+
+	tun->dev = dev;
+	nss_ipsecmgr_ref_init(&tun->ref, nss_ipsecmgr_tunnel_del_ref, nss_ipsecmgr_tunnel_free_ref);
+
+	INIT_LIST_HEAD(&tun->list);
+	INIT_LIST_HEAD(&tun->free_refs);
+	INIT_WORK(&tun->free_work, nss_ipsecmgr_tunnel_free_work);
+
+	nss_ipsecmgr_db_init(&tun->ctx_db);
+
+	memcpy(&tun->cb, cb, sizeof(tun->cb));
+
+	/*
+	 * Use HLOS netdev if it is loaded in the callback context;
+	 * else use the NSS netdev
+	 */
+	if (!skb_dev)
+		tun->cb.skb_dev = dev;
+
+	/*
+	 * Inner context allocation
+	 */
+	inner = nss_ipsecmgr_ctx_alloc(tun,
+					NSS_IPSEC_CMN_CTX_TYPE_INNER,
+					NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_INNER,
+					nss_ipsecmgr_ctx_rx_inner,
+					nss_ipsecmgr_ctx_rx_stats,
+					NSS_IPSEC_CMN_FEATURE_INLINE_ACCEL);
+	if (!inner) {
+		nss_ipsecmgr_warn("%px: failed to allocate context inner\n", tun);
+		goto free;
+	}
+
+	nss_ipsecmgr_ctx_attach(&tun->ctx_db, inner);
+
+	/*
+	 * Inner Metadata context allocation
+	 */
+	mdata_inner = nss_ipsecmgr_ctx_alloc(tun,
+					NSS_IPSEC_CMN_CTX_TYPE_MDATA_INNER,
+					NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_MDATA_INNER,
+					nss_ipsecmgr_ctx_rx_inner,
+					nss_ipsecmgr_ctx_rx_stats,
+					0);
+	if (!mdata_inner) {
+		nss_ipsecmgr_warn("%px: failed to allocate context metadata inner\n", tun);
+		goto free;
+	}
+
+	nss_ipsecmgr_ctx_attach(&tun->ctx_db, mdata_inner);
+	/*
+	 * Outer context allocation
+	 */
+	outer = nss_ipsecmgr_ctx_alloc(tun,
+					NSS_IPSEC_CMN_CTX_TYPE_OUTER,
+					NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_OUTER,
+					nss_ipsecmgr_ctx_rx_outer,
+					nss_ipsecmgr_ctx_rx_stats,
+					NSS_IPSEC_CMN_FEATURE_INLINE_ACCEL);
+	if (!outer) {
+		nss_ipsecmgr_warn("%px: failed to allocate context outer\n", tun);
+		goto free;
+	}
+
+	nss_ipsecmgr_ctx_attach(&tun->ctx_db, outer);
+	/*
+	 * Outer metadata context allocation
+	 */
+	mdata_outer = nss_ipsecmgr_ctx_alloc(tun,
+					NSS_IPSEC_CMN_CTX_TYPE_MDATA_OUTER,
+					NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_MDATA_OUTER,
+					nss_ipsecmgr_ctx_rx_outer,
+					nss_ipsecmgr_ctx_rx_stats,
+					0);
+	if (!mdata_outer) {
+		nss_ipsecmgr_warn("%px: failed to allocate context metadata outer\n", tun);
+		goto free;
+	}
+
+	nss_ipsecmgr_ctx_attach(&tun->ctx_db, mdata_outer);
+
+	/*
+	 * We need to setup the exception interface number for inner & outer;
+	 * The exception interface is used by the NSS to send the packet back
+	 * to host when there is a rule miss after the processing (inner or outer).
+	 * In case of inner any exception after its processing must come with the
+	 * outer interface number. Similarly, for outer we have to do the opposite
+	 */
+	nss_ipsecmgr_ctx_set_except(inner, outer->ifnum);
+	nss_ipsecmgr_ctx_set_except(mdata_inner, outer->ifnum);
+	nss_ipsecmgr_ctx_set_except(outer, inner->ifnum);
+	nss_ipsecmgr_ctx_set_except(mdata_outer, inner->ifnum);
+
+	/*
+	 * We need to setup the sibling interface number for inner & outer;
+	 * The sibling interface is used by the NSS to configure SA on sibling.
+	 */
+	nss_ipsecmgr_ctx_set_sibling(inner, mdata_inner->ifnum);
+	nss_ipsecmgr_ctx_set_sibling(outer, mdata_outer->ifnum);
+
+	if (!nss_ipsecmgr_ctx_config(inner)) {
+		nss_ipsecmgr_warn("%px: failed to configure inner context\n", tun);
+		goto free;
+	}
+
+	if (!nss_ipsecmgr_ctx_config(mdata_inner)) {
+		nss_ipsecmgr_warn("%px: failed to configure metadata inner context\n", tun);
+		goto free;
+	}
+
+	if (!nss_ipsecmgr_ctx_config(outer)) {
+		nss_ipsecmgr_warn("%px: failed to configure outer context\n", tun);
+		goto free;
+	}
+
+	if (!nss_ipsecmgr_ctx_config(mdata_outer)) {
+		nss_ipsecmgr_warn("%px: failed to configure metadata outer context\n", tun);
+		goto free;
+	}
+
+	status = rtnl_is_locked() ? register_netdevice(dev) : register_netdev(dev);
+	if (status < 0) {
+		nss_ipsecmgr_warn("%px: register net dev failed :%s\n", tun, dev->name);
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 11, 8))
+		goto free;
+#else
+		/*
+		 * Later kernels invoke the destructor upon failure
+		 */
+		return NULL;
+#endif
+	}
+
+	write_lock(&ipsecmgr_drv->lock);
+	list_add(&tun->list, &ipsecmgr_drv->tun_db);
+	write_unlock(&ipsecmgr_drv->lock);
+
+	nss_ipsecmgr_tunnel_mtu(dev, skb_dev ? skb_dev->mtu : dev->mtu);
+
+	/*
+	 * Create debugfs entry for tunnel and its child context(s)
+	 */
+	tun->dentry = debugfs_create_dir(dev->name, ipsecmgr_drv->dentry);
+	if (tun->dentry) {
+		debugfs_create_file("inner", S_IRUGO, tun->dentry, inner, &ipsecmgr_ctx_file_ops);
+		debugfs_create_file("mdata_inner", S_IRUGO, tun->dentry, mdata_inner, &ipsecmgr_ctx_file_ops);
+		debugfs_create_file("outer", S_IRUGO, tun->dentry, outer, &ipsecmgr_ctx_file_ops);
+		debugfs_create_file("mdata_outer", S_IRUGO, tun->dentry, mdata_outer, &ipsecmgr_ctx_file_ops);
+	}
+
+	return dev;
+free:
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 11, 8))
+	dev->destructor(dev);
+#else
+	dev->priv_destructor(dev);
+#endif
+	return NULL;
+}
+EXPORT_SYMBOL(nss_ipsecmgr_tunnel_add);
diff --git a/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_tunnel.h b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_tunnel.h
new file mode 100644
index 0000000..82fcdae
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/nss_ipsecmgr_tunnel.h
@@ -0,0 +1,83 @@
+/*
+ * ********************************************************************************
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ **********************************************************************************
+ */
+
+#ifndef __NSS_IPSECMGR_TUNNEL_H
+#define __NSS_IPSECMGR_TUNNEL_H
+
+#define NSS_IPSECMGR_CHK_POW2(x) (__builtin_constant_p(x) && !(~(x - 1) & (x >> 1)))
+
+#define NSS_IPSECMGR_MAX_NAME (NSS_IPSECMGR_MAX_KEY_NAME + 64)
+#define NSS_IPSECMGR_NODE_STATS_SZ 512
+#define NSS_IPSECMGR_NODE_CONFIG_RETRY_TIMEOUT msecs_to_jiffies(500) /* msecs */
+
+#define NSS_IPSECMGR_DEFAULT_TUN_NAME "ipsecdummy"
+
+/*
+ * IPsec manager private context
+ */
+struct nss_ipsecmgr_tunnel {
+	struct list_head list;			/* List node */
+	struct nss_ipsecmgr_ref ref;		/* Ref objects under the tunnel */
+	struct list_head free_refs;		/* Refs objects needs to freed */
+	struct work_struct free_work;		/* Free work for pending refs */
+
+	struct net_device *dev;			/* back pointer to tunnel device */
+
+	size_t stats_buf_sz;			/* Size of statistics buffer */
+	struct dentry *dentry;			/* DebugFS entry */
+	struct list_head ctx_db;		/* Context database */
+	struct nss_ipsecmgr_callback cb;	/* Callback entry */
+	struct nss_ipsecmgr_sa *tx_sa;		/* Default SA for tunnel transmit */
+};
+
+/*
+ * Initialize the metadata in the header of SKB, and return the pointer to the start of metadata payload
+ */
+static inline void *nss_ipsecmgr_tunnel_push_mdata(struct sk_buff *skb)
+{
+	struct nss_ipsec_cmn_mdata *mo;
+	uint8_t *data = skb->data;
+	uint16_t len, max_len;
+	uint8_t *mo_ptr;
+
+	/*
+	 * Here we go backwards by the size of metadata + alignment
+	 * Then PTR_ALIGN will optionally shift it forward based
+	 * on the current alignment
+	 */
+	max_len = sizeof(*mo) + NSS_IPSEC_CMN_MDATA_ALIGN_SZ;
+	mo_ptr = PTR_ALIGN(data - max_len, NSS_IPSEC_CMN_MDATA_ALIGN_SZ);
+
+	len = data - mo_ptr;
+	mo = (struct nss_ipsec_cmn_mdata *)skb_push(skb, len);
+
+	nss_ipsec_cmn_mdata_init(mo, len);
+	return (void *)&mo->data;
+}
+
+/*
+ * Pull metdata from SKB
+ */
+static inline void *nss_ipsecmgr_tunnel_pull_mdata(struct sk_buff *skb)
+{
+	struct nss_ipsec_cmn_mdata *mo = (struct nss_ipsec_cmn_mdata *)skb->data;
+	BUG_ON(mo->cm.magic != NSS_IPSEC_CMN_MDATA_MAGIC);
+
+	return skb_pull(skb, mo->cm.len);
+}
+#endif
diff --git a/qca-nss-clients/ipsecmgr/v2.0/plugins/klips/Makefile b/qca-nss-clients/ipsecmgr/v2.0/plugins/klips/Makefile
new file mode 100644
index 0000000..28da146
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/plugins/klips/Makefile
@@ -0,0 +1,24 @@
+# Klip plugin Makefile
+
+NSS_IPSEC_MOD_NAME=qca-nss-ipsec-klips
+
+obj-m += $(NSS_IPSEC_MOD_NAME).o
+$(NSS_IPSEC_MOD_NAME)-objs = nss_ipsec_klips.o
+
+obj ?= .
+ccflags-y += -I$(obj)/../../include
+ccflags-y += -I$(obj)/
+ccflags-y += -DNSS_IPSEC_KLIPS_DEBUG_LEVEL=3
+ccflags-y += -DNSS_IPSEC_KLIPS_BUILD_ID="$(BUILD_ID)"
+ccflags-y += -Wall -Werror
+ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64))
+ccflags-y += -DNSS_CFI_IPQ807X_SUPPORT
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq60xx ipq60xx_64))
+ccflags-y += -DNSS_CFI_IPQ60XX_SUPPORT
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq50xx ipq50xx_64))
+ccflags-y += -DNSS_CFI_IPQ50XX_SUPPORT
+endif
diff --git a/qca-nss-clients/ipsecmgr/v2.0/plugins/klips/nss_ipsec_klips.c b/qca-nss-clients/ipsecmgr/v2.0/plugins/klips/nss_ipsec_klips.c
new file mode 100644
index 0000000..07eeb3a
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/plugins/klips/nss_ipsec_klips.c
@@ -0,0 +1,2106 @@
+/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ *
+ *
+ */
+
+/* nss_ipsec_klips.c
+ *	NSS IPsec offload glue for Openswan/KLIPS
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/memory.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/uaccess.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/vmalloc.h>
+#include <linux/if.h>
+#include <linux/list.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <crypto/aes.h>
+#include <crypto/des.h>
+#include <net/esp.h>
+#include <net/protocol.h>
+#include <linux/inetdevice.h>
+#include <net/addrconf.h>
+
+#include <nss_api_if.h>
+#include <nss_ipsec.h>
+#include <nss_cfi_if.h>
+#include <nss_ipsecmgr.h>
+#include <ecm_interface_ipsec.h>
+#include <ecm_notifier.h>
+#if defined(NSS_L2TPV2_ENABLED)
+#include <nss_l2tpmgr.h>
+#endif
+#include "nss_ipsec_klips.h"
+
+#define NSS_IPSEC_KLIPS_BASE_NAME "ipsec"
+#define NSS_IPSEC_KLIPS_TUNNEL_MAX 8
+#define NSS_IPSEC_KLIPS_SES_MASK 0xffff
+#define NSS_IPSEC_KLIPS_FLAG_NATT 0x00000001
+#define NSS_IPSEC_KLIPS_FLAG_TRANSPORT_MODE 0x00000002
+#define NSS_IPSEC_KLIPS_SKB_CB_MAGIC 0xAAAB
+
+/*
+ * This is used by KLIPS for communicate the device along with the
+ * packet. We need this to derive the mapping of the incoming flow
+ * to the IPsec tunnel
+ */
+struct nss_ipsec_klips_skb_cb {
+	struct net_device *hlos_dev;
+	struct sock *sk;
+	uint32_t flags;
+	uint16_t replay_win;
+	uint16_t magic;
+};
+
+/*
+ * Per tunnel object created w.r.t the HLOS IPsec stack
+ */
+struct nss_ipsec_klips_sa {
+	struct list_head list;
+	struct nss_ipsecmgr_sa_tuple outer;
+	uint32_t sid;
+	bool ecm_accel_outer;
+};
+
+/*
+ * 3-tuple information for each tunnel.
+ */
+struct nss_ipsec_klips_tun_addr {
+	uint32_t src[4];	/* Source IP address in network order */
+	uint32_t dest[4];	/* Destination IP address in network order */
+	uint8_t ver;		/* IP version 4 or 6 */
+	uint8_t res[3];		/* Reserved */
+};
+
+/*
+ * CFI IPsec netdevice  mapping between HLOS devices and NSS devices
+ * Essentially various HLOS IPsec devices will be used as indexes to
+ * map into the NSS devices. For example
+ * "ipsec0" --> "ipsectun0"
+ * "ipsec1" --> "ipsectun1"
+ *
+ * Where the numeric suffix of "ipsec0", "ipsec1" is used to index into
+ * the table
+ */
+struct nss_ipsec_klips_tun {
+	struct list_head sa_list;
+	struct nss_ipsec_klips_tun_addr addr;
+	sk_encap_rcv_method_t sk_encap_rcv;
+	struct net_device *klips_dev;
+	struct net_device *nss_dev;
+	struct sock *sk;
+};
+
+/*
+ * NSS IPsec CFI tunnel map table
+ */
+struct nss_ipsec_klips_tun_map {
+	uint16_t max;
+	uint16_t used;
+	rwlock_t lock;
+	struct nss_ipsec_klips_tun *tbl;
+};
+
+static int tunnel_max = NSS_IPSEC_KLIPS_TUNNEL_MAX;
+module_param(tunnel_max, int, 0644);
+MODULE_PARM_DESC(tunnel_max, "Maximum number of tunnels to offload");
+
+static struct nss_ipsec_klips_tun_map tunnel_map;	/* per tunnel device table */
+
+/*
+ * Original ESP ptotocol handlers
+ */
+static const struct net_protocol *klips_esp_handler;
+static const struct inet6_protocol *klips_esp6_handler;
+
+static int nss_ipsec_klips_offload_esp(struct sk_buff *skb);
+
+/*
+ * IPv4 ESP handler
+ */
+static struct net_protocol esp_protocol = {
+	.handler = nss_ipsec_klips_offload_esp,
+	.no_policy = 1,
+	.netns_ok  = 1,
+};
+
+/*
+ * IPv6 ESP handler
+ */
+static struct inet6_protocol esp6_protocol = {
+	.handler = nss_ipsec_klips_offload_esp,
+	.flags = INET6_PROTO_NOPOLICY,
+};
+
+/*
+ * nss_ipsec_klips_v6addr_ntoh()
+ *	Network to host order
+ */
+static inline void nss_ipsec_klips_v6addr_ntoh(uint32_t *dest, uint32_t *src)
+{
+	dest[0] = ntohl(src[0]);
+	dest[1] = ntohl(src[1]);
+	dest[2] = ntohl(src[2]);
+	dest[3] = ntohl(src[3]);
+}
+
+/*
+ * nss_ipsec_klips_get_blk_len
+ *	get ipsec algorithm specific iv and block len
+ */
+static int32_t nss_ipsec_klips_get_blk_len(enum nss_crypto_cmn_algo algo)
+{
+	switch (algo) {
+	case NSS_CRYPTO_CMN_ALGO_AES128_CBC_SHA160_HMAC:
+	case NSS_CRYPTO_CMN_ALGO_AES192_CBC_SHA160_HMAC:
+	case NSS_CRYPTO_CMN_ALGO_AES256_CBC_SHA160_HMAC:
+	case NSS_CRYPTO_CMN_ALGO_AES128_CBC_MD5_HMAC:
+	case NSS_CRYPTO_CMN_ALGO_AES192_CBC_MD5_HMAC:
+	case NSS_CRYPTO_CMN_ALGO_AES256_CBC_MD5_HMAC:
+		return AES_BLOCK_SIZE;
+
+	case NSS_CRYPTO_CMN_ALGO_3DES_CBC_SHA160_HMAC:
+	case NSS_CRYPTO_CMN_ALGO_3DES_CBC_MD5_HMAC:
+		return DES_BLOCK_SIZE;
+
+	case NSS_CRYPTO_CMN_ALGO_NULL:
+		return 0;
+
+	default:
+		nss_ipsec_klips_err("Invalid algorithm\n");
+		return -1;
+	}
+}
+
+/*
+ * nss_ipsec_klips_get_algo
+ *	get ipsec manager specfic algorithm
+ */
+static enum nss_ipsecmgr_algo nss_ipsec_klips_get_algo(enum nss_crypto_cmn_algo algo)
+{
+	switch (algo) {
+	case NSS_CRYPTO_CMN_ALGO_AES128_CBC_SHA160_HMAC:
+	case NSS_CRYPTO_CMN_ALGO_AES256_CBC_SHA160_HMAC:
+		return NSS_IPSECMGR_ALGO_AES_CBC_SHA1_HMAC;
+
+	case NSS_CRYPTO_CMN_ALGO_AES128_CBC_MD5_HMAC:
+	case NSS_CRYPTO_CMN_ALGO_AES192_CBC_MD5_HMAC:
+	case NSS_CRYPTO_CMN_ALGO_AES256_CBC_MD5_HMAC:
+		return NSS_IPSECMGR_ALGO_AES_CBC_MD5_HMAC;
+
+	case NSS_CRYPTO_CMN_ALGO_3DES_CBC_SHA160_HMAC:
+		return NSS_IPSECMGR_ALGO_3DES_CBC_SHA1_HMAC;
+
+	case NSS_CRYPTO_CMN_ALGO_3DES_CBC_MD5_HMAC:
+		return NSS_IPSECMGR_ALGO_3DES_CBC_MD5_HMAC;
+
+	default:
+		nss_ipsec_klips_err("Invalid algorithm\n");
+		return NSS_IPSECMGR_ALGO_MAX;
+	}
+}
+
+/*
+ * nss_ipsec_klips_get_skb_cb()
+ * 	Get pointer to skb->cb typecasted to private structure.
+ */
+static inline struct nss_ipsec_klips_skb_cb *nss_ipsec_klips_get_skb_cb(struct sk_buff *skb)
+{
+	struct nss_ipsec_klips_skb_cb *ipsec_cb;
+
+	/*
+	 * Force compilation error if structure size is bigger than the allowed size.
+	 */
+	BUILD_BUG_ON(sizeof(struct nss_ipsec_klips_skb_cb) > sizeof(skb->cb));
+
+	/*
+	 * Verify cb is not overwritten by anyone.
+	 */
+	ipsec_cb = (struct nss_ipsec_klips_skb_cb *)skb->cb;
+	BUG_ON(ipsec_cb->magic != NSS_IPSEC_KLIPS_SKB_CB_MAGIC);
+
+	return ipsec_cb;
+}
+
+/*
+ * nss_ipsec_klips_tun_match_addr()
+ * 	Compare tunnel address with ip header.
+ */
+static bool nss_ipsec_klips_tun_match_addr(struct sk_buff *skb, struct nss_ipsec_klips_tun *tun)
+{
+	struct nss_ipsec_klips_tun_addr *addr = &tun->addr;
+	uint8_t version = ip_hdr(skb)->version;
+	uint32_t status = 0;
+
+	status += addr->ver ^ version;
+
+	switch (version) {
+	case IPVERSION: {
+		struct iphdr *iph = ip_hdr(skb);
+
+		status += addr->src[0] ^ iph->saddr;
+		status += addr->dest[0] ^ iph->daddr;
+
+		return !status;
+	}
+
+	case 6: {
+		struct ipv6hdr *ip6h = ipv6_hdr(skb);
+
+		status += addr->src[0] ^ ip6h->saddr.s6_addr32[0];
+		status += addr->src[1] ^ ip6h->saddr.s6_addr32[1];
+		status += addr->src[2] ^ ip6h->saddr.s6_addr32[2];
+		status += addr->src[3] ^ ip6h->saddr.s6_addr32[3];
+
+		status += addr->dest[0] ^ ip6h->daddr.s6_addr32[0];
+		status += addr->dest[1] ^ ip6h->daddr.s6_addr32[1];
+		status += addr->dest[2] ^ ip6h->daddr.s6_addr32[2];
+		status += addr->dest[3] ^ ip6h->daddr.s6_addr32[3];
+
+		return !status;
+	}
+
+	default:
+		nss_ipsec_klips_warn("%px: non ip version:%u received", skb, version);
+		return false;
+	}
+}
+
+/*
+ * nss_ipsec_klips_get_tun()
+ * 	get tunnel entry for given klips dev.
+ */
+static struct nss_ipsec_klips_tun *nss_ipsec_klips_get_tun(struct net_device *klips_dev)
+{
+	struct nss_ipsec_klips_tun *tun;
+	int i;
+
+	/*
+	 * Read/write lock needs to taken by the caller since sa
+	 * table is looked up here
+	 */
+	BUG_ON(write_can_lock(&tunnel_map.lock));
+
+	if (!klips_dev) {
+		return NULL;
+	}
+
+	for (i = 0, tun = tunnel_map.tbl; i < tunnel_map.max; i++, tun++) {
+		if (!tun->nss_dev || !tun->klips_dev)
+			continue;
+
+		if (klips_dev == tun->klips_dev)
+			return tun;
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_ipsec_klips_get_tun_dev()
+ *	Get ipsecmgr tunnel netdevice for klips netdevice
+ *
+ * The device returned has had a reference added and the pointer is safe until
+ * the user calls dev_put to indicate they have finished with it
+ */
+static struct net_device *nss_ipsec_klips_get_tun_dev(struct net_device *klips_dev)
+{
+	struct nss_ipsec_klips_tun *tun;
+	struct net_device *tun_dev;
+
+	write_lock_bh(&tunnel_map.lock);
+
+	tun = nss_ipsec_klips_get_tun(klips_dev);
+	if (!tun) {
+		write_unlock_bh(&tunnel_map.lock);
+		return NULL;
+	}
+
+	tun_dev = tun->nss_dev;
+	dev_hold(tun_dev);
+	write_unlock_bh(&tunnel_map.lock);
+
+	return tun_dev;
+}
+
+#if defined(NSS_L2TPV2_ENABLED)
+/*
+ * nss_ipsec_klips_get_inner_ifnum()
+ * 	Get ipsecmgr interface number for klips netdevice
+ *
+ * Calls nss_ipsec_klips_get_tun_dev(), which holds reference for tunnel,
+ * which gets released at the end of this function.
+ */
+static int nss_ipsec_klips_get_inner_ifnum(struct net_device *klips_dev)
+{
+	struct net_device *tun_dev;
+	int32_t ipsec_ifnum;
+
+	tun_dev = nss_ipsec_klips_get_tun_dev(klips_dev);
+	if (!tun_dev) {
+		nss_ipsec_klips_warn("%px: Tunnel device not found for klips dev", klips_dev);
+		return -1;
+	}
+
+	ipsec_ifnum = nss_cmn_get_interface_number_by_dev_and_type(tun_dev, NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_INNER);
+	dev_put(tun_dev);
+
+	return ipsec_ifnum;
+}
+#endif
+
+/*
+ * nss_ipsec_klips_get_tun_by_addr()
+ * 	Get the tunnel entry for given ip header from tunnel map table.
+ */
+static struct nss_ipsec_klips_tun *nss_ipsec_klips_get_tun_by_addr(struct sk_buff *skb)
+{
+	struct nss_ipsec_klips_tun *tun;
+	int i;
+
+	/*
+	 * Read/write lock needs to be taken by the caller since tunnel
+	 * table is looked up here
+	 */
+	BUG_ON(write_can_lock(&tunnel_map.lock));
+
+	for (i = 0, tun = tunnel_map.tbl; i < tunnel_map.max; i++, tun++) {
+		if (!tun->klips_dev) {
+			continue;
+		}
+
+		if (nss_ipsec_klips_tun_match_addr(skb, tun)) {
+			return tun;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_ipsec_klips_get_index()
+ *	given an interface name retrived the numeric suffix
+ */
+static int16_t nss_ipsec_klips_get_index(uint8_t *name)
+{
+	uint8_t *next_char;
+	int16_t idx;
+
+	if (strncmp(name, NSS_IPSEC_KLIPS_BASE_NAME, strlen(NSS_IPSEC_KLIPS_BASE_NAME)))
+		return -1;
+
+	next_char = name + strlen(NSS_IPSEC_KLIPS_BASE_NAME);
+	if ((*next_char < '0') || (*next_char > '9'))
+		return -1;
+
+	for (idx = 0; (*next_char >= '0') && (*next_char <= '9'); next_char++)
+		idx = (*next_char - '0') + (idx * 10);
+
+	return idx;
+}
+
+/*
+ * nss_ipsec_klips_sa_lookup()
+ *	Look for an SA based on crypto index.
+ */
+static struct nss_ipsec_klips_sa *nss_ipsec_klips_sa_lookup(struct nss_ipsec_klips_tun *tun, uint16_t crypto_idx)
+{
+	struct list_head *head = &tun->sa_list;
+	struct nss_ipsec_klips_sa *sa;
+	struct nss_ipsec_klips_sa *tmp;
+
+	/*
+	 * Read/write lock needs to taken by the caller since sa
+	 * table is looked up here
+	 */
+	BUG_ON(write_can_lock(&tunnel_map.lock));
+
+	list_for_each_entry_safe(sa, tmp, head, list) {
+		if (sa->sid == crypto_idx)
+			return sa;
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_ipsec_klips_sa_flush()
+ *	Flush all SA entries
+ */
+static void nss_ipsec_klips_sa_flush(struct nss_ipsec_klips_tun *tun, struct net_device *nss_dev)
+{
+	struct list_head *head = &tun->sa_list;
+	struct nss_ipsec_klips_sa *sa;
+	struct nss_ipsec_klips_sa *tmp;
+
+	/*
+	 * Read/write lock needs to taken by the caller since sa
+	 * table is modified here
+	 */
+	BUG_ON(write_can_lock(&tunnel_map.lock));
+
+	list_for_each_entry_safe(sa, tmp, head, list) {
+		list_del_init(&sa->list);
+		nss_ipsecmgr_sa_del(nss_dev, &sa->outer);
+		kfree(sa);
+	}
+}
+
+/*
+ * nss_ipsec_klips_free_session()
+ *	Free particular session on NSS.
+ */
+static int32_t nss_ipsec_klips_free_session(uint32_t crypto_sid)
+{
+	uint16_t crypto_idx = crypto_sid & NSS_IPSEC_KLIPS_SES_MASK;
+	struct nss_ipsec_klips_tun *tun;
+	struct nss_ipsec_klips_sa *sa = NULL;
+	struct net_device *nss_dev;
+	int i;
+
+	/*
+	 * Write lock needs to be taken here since SA table is
+	 * getting modified
+	 */
+	write_lock_bh(&tunnel_map.lock);
+
+	for (i = 0, tun = tunnel_map.tbl; i < tunnel_map.max; i++, tun++) {
+		if (!tun->nss_dev || !tun->klips_dev)
+			continue;
+
+		sa = nss_ipsec_klips_sa_lookup(tun, crypto_idx);
+		if (sa) {
+			list_del_init(&sa->list);
+			break;
+		}
+	}
+
+	if (!sa) {
+		write_unlock_bh(&tunnel_map.lock);
+		return -ENOENT;
+	}
+
+	nss_dev = tun->nss_dev;
+	dev_hold(nss_dev);
+
+	write_unlock_bh(&tunnel_map.lock);
+
+	/*
+	 * The SA is now removed from the list hence
+	 * we can access it without locks
+	 */
+	nss_ipsecmgr_sa_del(nss_dev, &sa->outer);
+	dev_put(nss_dev);
+
+	kfree(sa);
+	return 0;
+}
+
+/*
+ * nss_ipsec_klips_outer2sa_tuple()
+ *	Fill sa_tuple from outer header and return start of payload
+ */
+static void *nss_ipsec_klips_outer2sa_tuple(uint8_t *outer, bool natt, struct nss_ipsecmgr_sa_tuple *tuple,
+				uint8_t *ttl, bool decap)
+{
+	struct ipv6hdr *ip6h = (struct ipv6hdr *)outer;
+	struct iphdr *ip4h = (struct iphdr *)outer;
+	struct ip_esp_hdr *esph;
+
+	memset(tuple, 0, sizeof(*tuple));
+	if (ip4h->version == IPVERSION) {
+		outer += sizeof(*ip4h);
+
+		tuple->src_ip[0] = ntohl(ip4h->saddr);
+		tuple->dest_ip[0] = ntohl(ip4h->daddr);
+		tuple->proto_next_hdr = ip4h->protocol;
+		tuple->ip_version = IPVERSION;
+		*ttl = ip4h->ttl;
+
+		/*
+		 * TODO: NAT-T ports can be programmable; Add
+		 * support for loading programmed ports by user
+		 */
+		if (natt) {
+			tuple->sport = NSS_IPSECMGR_NATT_PORT_DATA;
+			tuple->dport = NSS_IPSECMGR_NATT_PORT_DATA;
+			tuple->proto_next_hdr = IPPROTO_UDP;
+
+			/*
+			 * TODO: Find out why we need decap flag
+			 */
+			outer += decap ? sizeof(struct udphdr) : 0;
+		}
+
+		esph = (struct ip_esp_hdr *)outer;
+		tuple->spi_index = ntohl(esph->spi);
+
+		return outer + sizeof(*esph);
+	}
+
+	BUG_ON(ip6h->version != 6);
+	BUG_ON(ip6h->nexthdr != IPPROTO_ESP);
+
+	outer += sizeof(*ip6h);
+	esph = (struct ip_esp_hdr *)outer;
+	nss_ipsec_klips_v6addr_ntoh(tuple->src_ip, ip6h->saddr.s6_addr32);
+	nss_ipsec_klips_v6addr_ntoh(tuple->dest_ip, ip6h->daddr.s6_addr32);
+
+	tuple->spi_index = ntohl(esph->spi);
+	tuple->proto_next_hdr = IPPROTO_ESP;
+	*ttl = ip6h->hop_limit;
+	tuple->ip_version = 6;
+
+	return outer + sizeof(*esph);
+}
+
+/*
+ * nss_ipsec_klips_outer2flow_tuple()
+ *	Fill inner flow
+ */
+static bool nss_ipsec_klips_outer2flow_tuple(uint8_t *outer, bool natt, struct nss_ipsecmgr_flow_tuple *tuple)
+{
+	struct ipv6hdr *ip6h = (struct ipv6hdr *)outer;
+	struct iphdr *ip4h = (struct iphdr *)outer;
+	struct ip_esp_hdr *esph;
+
+	memset(tuple, 0, sizeof(*tuple));
+	if (ip4h->version == IPVERSION) {
+		outer += sizeof(*ip4h);
+
+		tuple->src_ip[0] = ntohl(ip4h->saddr);
+		tuple->dest_ip[0] = ntohl(ip4h->daddr);
+		tuple->proto_next_hdr = ip4h->protocol;
+		tuple->ip_version = IPVERSION;
+
+		if (natt) {
+			tuple->sport = NSS_IPSECMGR_NATT_PORT_DATA;
+			tuple->dport = NSS_IPSECMGR_NATT_PORT_DATA;
+			tuple->proto_next_hdr = IPPROTO_UDP;
+			outer += sizeof(struct udphdr);
+		}
+
+		esph = (struct ip_esp_hdr *)outer;
+		tuple->spi_index = ntohl(esph->spi);
+		return true;
+	}
+
+	if ((ip6h->version != 6) || (ip6h->nexthdr != IPPROTO_ESP)) {
+		return false;
+	}
+
+	outer += sizeof(*ip6h);
+	esph = (struct ip_esp_hdr *)outer;
+
+	nss_ipsec_klips_v6addr_ntoh(tuple->src_ip, ip6h->saddr.s6_addr32);
+	nss_ipsec_klips_v6addr_ntoh(tuple->dest_ip, ip6h->daddr.s6_addr32);
+
+	tuple->spi_index = ntohl(esph->spi);
+	tuple->proto_next_hdr = IPPROTO_ESP;
+	tuple->ip_version = 6;
+	return true;
+}
+
+/*
+ * nss_ipsec_klips_inner2flow_tuple()
+ *	Fill inner flow
+ */
+static void nss_ipsec_klips_inner2flow_tuple(uint8_t *ip, uint8_t proto, struct nss_ipsecmgr_flow_tuple *tuple)
+{
+	struct ipv6hdr *ip6h = (struct ipv6hdr *)ip;
+	struct iphdr *iph = (struct iphdr *)ip;
+
+	/*
+	 * TODO: Since, we are pushing 3-tuple for every 5-tuple
+	 * It is possible that the each 3-tuple maps to multiple unique
+	 * 5-tuple rules. Thus we need to add support for identifying
+	 * them and then allow adding or deleting of 3-tuple correctly
+	 */
+
+	tuple->sport = 0;
+	tuple->dport = 0;
+	tuple->use_pattern = 0;
+	tuple->ip_version = iph->version;
+
+	if (tuple->ip_version == IPVERSION) {
+		tuple->src_ip[0] = ntohl(iph->saddr);
+		tuple->dest_ip[0] = ntohl(iph->daddr);
+		tuple->proto_next_hdr = proto ? proto : iph->protocol;
+		return;
+	}
+
+	BUG_ON(tuple->ip_version != 6);
+
+	nss_ipsec_klips_v6addr_ntoh(tuple->src_ip, ip6h->saddr.s6_addr32);
+	nss_ipsec_klips_v6addr_ntoh(tuple->dest_ip, ip6h->daddr.s6_addr32);
+
+	if (ip6h->nexthdr == NEXTHDR_FRAGMENT) {
+		struct frag_hdr *fragh = (struct frag_hdr *)(ip + sizeof(*ip6h));
+		proto = fragh->nexthdr;
+	}
+
+	tuple->proto_next_hdr = proto ? proto : ip6h->nexthdr;
+}
+
+/*
+ * nss_ipsec_klips_sa2ecm_tuple()
+ *	Fill ecm connection tuple.
+ */
+static void nss_ipsec_klips_sa2ecm_tuple(struct nss_ipsecmgr_sa_tuple *sa, struct ecm_notifier_connection_tuple *tuple)
+{
+	tuple->dst_port = sa->dport;
+	tuple->src_port = sa->sport;
+	tuple->ip_ver = sa->ip_version;
+	tuple->protocol = sa->proto_next_hdr;
+
+	if (sa->ip_version == IPVERSION) {
+		tuple->src.in.s_addr = sa->src_ip[0];
+		tuple->dest.in.s_addr = sa->dest_ip[0];
+		return;
+	}
+
+	BUG_ON(sa->ip_version != 6);
+
+	tuple->src.in6.s6_addr32[0] = sa->src_ip[0];
+	tuple->src.in6.s6_addr32[1] = sa->src_ip[1];
+	tuple->src.in6.s6_addr32[2] = sa->src_ip[2];
+	tuple->src.in6.s6_addr32[3] = sa->src_ip[3];
+
+	tuple->dest.in6.s6_addr32[0] = sa->dest_ip[0];
+	tuple->dest.in6.s6_addr32[1] = sa->dest_ip[1];
+	tuple->dest.in6.s6_addr32[2] = sa->dest_ip[2];
+	tuple->dest.in6.s6_addr32[3] = sa->dest_ip[3];
+}
+
+/*
+ * nss_ipsec_klips_outer2tun_addr()
+ * 	Fill tunnel address information.
+ */
+static inline void nss_ipsec_klips_outer2tun_addr(uint8_t *iph, struct nss_ipsec_klips_tun_addr *addr)
+{
+	struct iphdr *ip4h = (struct iphdr *)iph;
+	struct ipv6hdr *ip6h;
+
+	addr->ver = ip4h->version;
+
+	if (ip4h->version == IPVERSION) {
+		addr->src[0] = ip4h->saddr;
+		addr->dest[0] = ip4h->daddr;
+		return;
+	}
+
+	ip6h = (struct ipv6hdr *)iph;
+	BUG_ON(ip6h->version != 6);
+
+	memcpy(addr->src, ip6h->saddr.s6_addr32, sizeof(addr->src));
+	memcpy(addr->dest, ip6h->daddr.s6_addr32, sizeof(addr->dest));
+}
+
+/*
+ * nss_ipsec_klips_fallback_esp_handler()
+ *	Fallback to original ESP protocol handler.
+ */
+static int nss_ipsec_klips_fallback_esp_handler(struct sk_buff *skb)
+{
+
+	switch (ip_hdr(skb)->version) {
+	case IPVERSION: {
+		struct net_protocol *esp_handler;
+		xchg(&esp_handler, klips_esp_handler);
+
+		if (esp_handler && esp_handler->handler) {
+			return esp_handler->handler(skb);
+		}
+
+		nss_ipsec_klips_warn("%px: Fallback ESP handler not present for IPv4\n", skb);
+		break;
+	}
+
+	case 6: {
+		struct inet6_protocol *esp_handler;
+		xchg(&esp_handler, klips_esp6_handler);
+
+		if (esp_handler && esp_handler->handler) {
+			return esp_handler->handler(skb);
+		}
+
+		nss_ipsec_klips_warn("%px: Fallback ESP handler not present for IPv6\n", skb);
+		break;
+	}
+
+	default:
+		nss_ipsec_klips_warn("%px: Invalid IP header version:%u\n", skb, ip_hdr(skb)->version);
+		break;
+	}
+
+	nss_ipsec_klips_warn("%px: Droping SKB", skb);
+	dev_kfree_skb_any(skb);
+	return 0;
+}
+
+/*
+ * nss_ipsec_klips_fallback_natt_handler()
+ *	Invoke KLIPS encap recieve handler for socket.
+ */
+static int nss_ipsec_klips_fallback_natt_handler(struct sock *sk, struct sk_buff *skb)
+{
+	struct nss_ipsec_klips_tun *tun;
+	sk_encap_rcv_method_t encap_rcv;
+
+	read_lock(&tunnel_map.lock);
+
+	tun = nss_ipsec_klips_get_tun_by_addr(skb);
+	if (!tun) {
+		read_unlock(&tunnel_map.lock);
+		nss_ipsec_klips_warn("%px: Unable to find tunnel assciated, dropping skb", skb);
+		goto drop_skb;
+	}
+
+	if (tun->sk != sk) {
+		read_unlock(&tunnel_map.lock);
+		nss_ipsec_klips_warn("%px: Packet recieved from incorrect socket, dropping skb", tun);
+		goto drop_skb;
+	}
+
+	encap_rcv = tun->sk_encap_rcv;
+	if (!encap_rcv) {
+		read_unlock(&tunnel_map.lock);
+		nss_ipsec_klips_warn("%px: NULL sk_encap_rcv, dropping skb", tun);
+		goto drop_skb;
+	}
+
+	read_unlock(&tunnel_map.lock);
+
+	return encap_rcv(sk, skb);
+
+drop_skb:
+	dev_kfree_skb_any(skb);
+	return 0;
+}
+
+/*
+ * nss_ipsec_klips_init_trans_offload()
+ * 	Reset all headers added by KLIPS for transport mode.
+ */
+static void nss_ipsec_klips_init_trans_offload(struct sk_buff *skb, int8_t iv_len, uint8_t hash_len)
+{
+	struct iphdr iph;
+	uint8_t ip_proto;
+	uint8_t *tail;
+	uint8_t pad;
+
+	/*
+	 * Note: We need to reset the SKB to the inner payload.
+	 * Strip the outer ESP header added by KLIPs, move outer
+	 * IP header before payload and trim the trailer by reading
+	 * the inner payload length
+	 */
+	skb_reset_network_header(skb);
+	tail = skb_tail_pointer(skb) - hash_len - (2 * sizeof(uint8_t));
+
+	ip_proto = tail[1];
+	pad = tail[0];
+	skb_trim(skb, (tail - skb->data) - pad);
+
+	if (ip_hdr(skb)->version == IPVERSION) {
+		memcpy(&iph, skb->data, sizeof(iph));
+		skb_pull(skb, sizeof(iph) + sizeof(struct ip_esp_hdr) + iv_len);
+		iph.protocol = ip_proto;
+		iph.tot_len = htons(skb->len + sizeof(iph));
+		memcpy(skb_push(skb, sizeof(iph)), &iph, sizeof(iph));
+		skb_reset_network_header(skb);
+		return;
+	}
+
+	BUG_ON(ip_hdr(skb)->version != IPVERSION);
+}
+
+/*
+ * nss_ipsec_klips_init_tun_offload()
+ * 	Reset all headers added by KLIPS for tunnel mode.
+ */
+static void nss_ipsec_klips_init_tun_offload(struct sk_buff *skb, int8_t iv_len)
+{
+	struct ipv6hdr *ip6h;
+	struct iphdr *iph;
+	int trim_len;
+
+	/*
+	 * Note: We need to reset the SKB to the inner payload.
+	 * Strip the outer header added by KLIPs and then trim
+	 * the trailer by reading the inner payload length
+	 */
+	skb_reset_network_header(skb);
+	iph = ip_hdr(skb);
+
+	skb_pull(skb, iph->version == IPVERSION ? sizeof(*iph) : sizeof(*ip6h));
+	skb_pull(skb, sizeof(struct ip_esp_hdr) + iv_len);
+
+	skb_reset_network_header(skb);
+	iph = ip_hdr(skb);
+
+	if (iph->version == IPVERSION) {
+		trim_len = ntohs(iph->tot_len);
+	} else {
+		ip6h = ipv6_hdr(skb);
+		trim_len = ntohs(ip6h->payload_len) + sizeof(*ip6h);
+	}
+
+	skb_trim(skb, trim_len);
+}
+
+/*
+ * nss_ipsec_klips_offload_inner()
+ * 	Offload SKB to NSS for encapsulation.
+ *
+ * This function will return 0 if packet is offloaded else return 1.
+ */
+static int32_t nss_ipsec_klips_offload_inner(struct sk_buff *orig_skb, struct nss_cfi_crypto_info *crypto)
+{
+	uint16_t crypto_idx = crypto->sid & NSS_IPSEC_KLIPS_SES_MASK;
+	struct nss_ipsecmgr_flow_tuple flow_tuple = {0};
+	struct nss_ipsec_klips_skb_cb *ipsec_cb;
+	struct nss_ipsecmgr_sa_tuple sa_tuple;
+	struct nss_ipsec_klips_tun *tun;
+	struct nss_ipsec_klips_sa *sa;
+	nss_ipsecmgr_status_t status;
+	struct net_device *nss_dev;
+	bool ecm_accel_outer;
+	struct sk_buff *skb;
+	int8_t iv_len;
+
+	iv_len = nss_ipsec_klips_get_blk_len(crypto->algo);
+	if (iv_len < 0) {
+		nss_ipsec_klips_warn("%px:Failed to map valid IV and block length\n", orig_skb);
+		return 0;
+	}
+
+	ipsec_cb = nss_ipsec_klips_get_skb_cb(orig_skb);
+	if (!ipsec_cb) {
+		nss_ipsec_klips_warn("%px:Unable to get ipsec cb\n", orig_skb);
+		return 0;
+	}
+
+	/*
+	 * Write lock needs to be taken here as the tunnel map table
+	 * field is modified.
+	 */
+	write_lock(&tunnel_map.lock);
+
+	tun = nss_ipsec_klips_get_tun(ipsec_cb->hlos_dev);
+	if (!tun) {
+		write_unlock(&tunnel_map.lock);
+		nss_ipsec_klips_warn("%px: Failed to find tun entry\n", ipsec_cb->hlos_dev);
+		return 1;
+	}
+
+	nss_dev = tun->nss_dev;
+	BUG_ON(!nss_dev);
+
+	sa = nss_ipsec_klips_sa_lookup(tun, crypto_idx);
+	if (!sa) {
+		write_unlock(&tunnel_map.lock);
+		nss_ipsec_klips_trace("%px: Failed to find SA entry(%u)\n", tun, crypto_idx);
+		return 1;
+	}
+
+	/*
+	 * Check if SA is present,else let it process through KLIPS.
+	 * Note: This can happen for the first few encapsulation packet
+	 */
+	if (!nss_ipsecmgr_sa_verify(nss_dev, &sa->outer)) {
+		write_unlock(&tunnel_map.lock);
+		return 1;
+	}
+
+	/*
+	 * Copy SA tuple.
+	 */
+	sa_tuple = sa->outer;
+	ecm_accel_outer = sa->ecm_accel_outer;
+
+	/*
+	 * Check if ECM has pushed the rule. If present than push the inner flow rule.
+	 */
+	if (!ecm_accel_outer) {
+		struct ecm_notifier_connection_tuple ecm_tuple = {0};
+		enum ecm_notifier_connection_state ecm_state;
+
+		nss_ipsec_klips_sa2ecm_tuple(&sa_tuple, &ecm_tuple);
+
+		ecm_state = ecm_notifier_connection_state_get(&ecm_tuple);
+		if (ecm_state == ECM_NOTIFIER_CONNECTION_STATE_ACCEL) {
+			ecm_accel_outer = sa->ecm_accel_outer = true;
+		}
+
+		nss_ipsec_klips_trace("%px: Get ecm connection state(%u)\n", tun, ecm_state);
+	}
+
+	dev_hold(nss_dev);
+	write_unlock(&tunnel_map.lock);
+
+	/*
+	 * If it is a IPv6 packet in transport mode, drop it as
+	 * this flow is not supported.
+	 */
+	if (ipsec_cb->flags & NSS_IPSEC_KLIPS_FLAG_TRANSPORT_MODE) {
+		skb_reset_network_header(orig_skb);
+		if (unlikely(ip_hdr(orig_skb)->version != IPVERSION)) {
+			nss_ipsec_klips_warn("%px:IPv6 transport mode offload is not supported\n", orig_skb);
+			dev_put(nss_dev);
+			return 1;
+		}
+	}
+
+	/*
+	 * Fix the original SKB and then do a copy of it for NSS.
+	 * We need to do this because the cache lines modified by KLIPS will not be
+	 * needed anymore. Addtionally, the dma_map_single only flush/invalidates the
+	 * SKB from head to tail. In this case the tail has shortened.
+	 */
+	if (ipsec_cb->flags & NSS_IPSEC_KLIPS_FLAG_TRANSPORT_MODE) {
+		nss_ipsec_klips_init_trans_offload(orig_skb, iv_len, crypto->hash_len);
+	} else {
+		nss_ipsec_klips_init_tun_offload(orig_skb, iv_len);
+	}
+
+	/*
+	 * We create a copy of the KLIPS skb; since this will be transmitted out
+	 * of NSS. We cannot expect it to return to host. Hence, we overwrite
+	 * the skb with the clone.
+	 */
+	skb = skb_copy_expand(orig_skb, nss_dev->needed_headroom, nss_dev->needed_tailroom, GFP_ATOMIC);
+	if (!skb) {
+		nss_ipsec_klips_err("%px: Unable to create copy of SKB\n", nss_dev);
+		dev_put(nss_dev);
+		return 0;
+	}
+
+	/*
+	 * We need to release all resources hold by SKB before sending it to NSS.
+	 * Reset the SKB and make it orphan.
+	 */
+	skb_scrub_packet(skb, true);
+	skb->skb_iif = orig_skb->skb_iif;
+
+	nss_ipsec_klips_inner2flow_tuple(skb->data, 0, &flow_tuple);
+
+	/*
+	 * Try to send packet to NSS and drop the packet incase of failure.
+	 * TODO: At higher packet rate, Initial packets can go out-of-order when ECM outer flow is
+	 * not present and packets has to go through exception path.
+	 */
+	status = nss_ipsecmgr_sa_tx_inner(nss_dev, &sa_tuple, skb);
+	if (status != NSS_IPSECMGR_OK) {
+		nss_ipsec_klips_trace("%px: Failed to transmit encap packet, error(%u)\n", skb, status);
+		dev_kfree_skb_any(skb);
+	}
+
+	/*
+	 * Enable the IPsec inner flow once ECM has accelerated the outer flow.
+	 * This will limit the packet rate in encap direction till ECM pushes the
+	 * rule and should minimize the out-of-order issue when ECM flow is not present.
+	 */
+	if (ecm_accel_outer) {
+		nss_ipsecmgr_flow_add(nss_dev, &flow_tuple, &sa_tuple);
+	}
+
+	dev_put(nss_dev);
+	return 0;
+}
+
+/*
+ * nss_ipsec_klips_offload_outer()
+ *	Offload IPsec encapsulated packets.
+ */
+static int nss_ipsec_klips_offload_outer(struct sk_buff *skb, struct nss_ipsecmgr_sa_tuple *sa_tuple,
+					struct nss_ipsecmgr_flow_tuple *flow_tuple)
+{
+	struct nss_ipsec_klips_tun *tun;
+	nss_ipsecmgr_status_t status;
+	struct net_device *nss_dev;
+	int ifindex;
+
+	/*
+	 * Check if we are tracking net_device for this IP.
+	 * If not then this is for IPsec bypass.
+	 */
+	write_lock(&tunnel_map.lock);
+	tun = nss_ipsec_klips_get_tun_by_addr(skb);
+	if (!tun) {
+		write_unlock(&tunnel_map.lock);
+		return -ENODEV;
+	}
+
+	ifindex = tun->klips_dev->ifindex;
+	nss_dev = tun->nss_dev;
+	dev_hold(nss_dev);
+
+	write_unlock(&tunnel_map.lock);
+
+	/*
+	 * Check if SA is present,else fallback to KLIPS.
+	 * Note: This can happen for the first few decapsulation packet
+	 */
+	if (!nss_ipsecmgr_sa_verify(nss_dev, sa_tuple)) {
+		dev_put(nss_dev);
+		return -ENODATA;
+	}
+
+	/*
+	 * In case of Decap, skb->data points to ESP header or UDP header for NATT.
+	 * Set the skb->data to outer IP header.
+	 */
+	skb_push(skb, skb->data - skb_network_header(skb));
+
+	/*
+	 * If skb was cloned (likely due to a packet sniffer), Make a copy.
+	 * skb_cow() has check for skb_cloned().
+	 */
+	if (skb_cow(skb, skb_headroom(skb))) {
+		nss_ipsec_klips_warn("%px: Failed to create writable copy, Droping", skb);
+		goto drop_skb;
+	}
+
+	/*
+	 * We need to release all resources hold by SKB before sending it to NSS.
+	 * Reset the SKB and make it orphan.
+	 */
+	skb_scrub_packet(skb, true);
+	skb->skb_iif = ifindex;
+
+	/*
+	 * Offload further processing to NSS.
+	 * Note: This can fail if the queue is full
+	 */
+	status = nss_ipsecmgr_sa_tx_outer(nss_dev, sa_tuple, skb);
+	if (status != NSS_IPSECMGR_OK) {
+		dev_kfree_skb_any(skb);
+	}
+
+	/*
+	 * Add outer flow as SKB is offloaded.
+	 */
+	nss_ipsecmgr_flow_add(nss_dev, flow_tuple, sa_tuple);
+
+	dev_put(nss_dev);
+	return 0;
+
+drop_skb:
+	dev_kfree_skb_any(skb);
+	dev_put(nss_dev);
+	return 0;
+}
+
+/*
+ * nss_ipsec_klips_offload_esp()
+ *	ESP Protocol handler for IPsec encapsulated packets.
+ */
+static int nss_ipsec_klips_offload_esp(struct sk_buff *skb)
+{
+	struct nss_ipsecmgr_flow_tuple flow_tuple = {0};
+	struct nss_ipsecmgr_sa_tuple sa_tuple = {0};
+	uint8_t ttl;
+	int ret;
+
+	nss_ipsec_klips_trace("%px: SKb recieved by KLIPS plugin\n", skb);
+
+	nss_ipsec_klips_outer2sa_tuple(skb_network_header(skb), false, &sa_tuple, &ttl, true);
+	nss_ipsec_klips_outer2flow_tuple(skb_network_header(skb), false, &flow_tuple);
+
+	ret = nss_ipsec_klips_offload_outer(skb, &sa_tuple, &flow_tuple);
+	if (ret) {
+		nss_ipsec_klips_trace("%px: Fallback to klips esp handler. error(%d)\n", skb, ret);
+		return nss_ipsec_klips_fallback_esp_handler(skb);
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ipsec_klips_offload_natt()
+ * 	Socket encap recieve handler for IPsec UDP encapsulated packets.
+ *
+ * Shell returns the following value:
+ * =0 if SKB is consumed.
+ * >0 if skb should be passed on to UDP.
+ * <0 if skb should be resubmitted.
+ */
+int nss_ipsec_klips_offload_natt(struct sock *sk, struct sk_buff *skb)
+{
+	size_t hdr_len = sizeof(struct udphdr) +  sizeof(struct ip_esp_hdr);
+	struct nss_ipsecmgr_flow_tuple flow_tuple = {0};
+	struct nss_ipsecmgr_sa_tuple sa_tuple = {0};
+	struct ip_esp_hdr *esph;
+	uint8_t ttl;
+	int status;
+
+	/*
+	 * Socket has to be of type UDP_ENCAP_ESPINUDP .
+	 */
+	BUG_ON(udp_sk(sk)->encap_type != UDP_ENCAP_ESPINUDP);
+
+	/*
+	 * NAT-keepalive packet has udphdr & one byte payload (rfc3948).
+	 */
+	if (skb->len < hdr_len) {
+		goto fallback;
+	}
+
+	/*
+	 * In case of non-linear SKB we would like to ensure that
+	 * all the required headers are present in the first segment
+	 */
+	if (skb_is_nonlinear(skb) && (skb_headlen(skb) < hdr_len)) {
+		if (skb_linearize(skb)) {
+			dev_kfree_skb_any(skb);
+			return 0;
+		}
+
+		/*
+		 * skb_linearize may change header. So, reload all required pointer.
+		 */
+		skb_reset_transport_header(skb);
+		skb_set_network_header(skb, -(int)sizeof(struct iphdr));
+	}
+
+	/*
+	 * Check if packet has non-ESP marker (rfc3948)
+	 */
+	esph = (struct ip_esp_hdr *)(skb_transport_header(skb) + sizeof(struct udphdr));
+	if (ntohl(esph->spi) == NSS_IPSEC_KLIPS_NON_ESP_MARKER) {
+		goto fallback;
+	}
+
+	/*
+	 * ESP packet recieved, offload it to NSS else send it to KLIPS.
+	 */
+	nss_ipsec_klips_outer2sa_tuple(skb_network_header(skb), true, &sa_tuple, &ttl, true);
+	nss_ipsec_klips_outer2flow_tuple(skb_network_header(skb), true, &flow_tuple);
+
+	status = nss_ipsec_klips_offload_outer(skb, &sa_tuple, &flow_tuple);
+	if (status) {
+		nss_ipsec_klips_trace("%px: Fallback to klips natt handler. error(%d)\n", skb, status);
+		goto fallback;
+	}
+
+	return 0;
+
+fallback:
+	return nss_ipsec_klips_fallback_natt_handler(sk, skb);
+}
+
+/*
+ * nss_ipsec_klips_register_natt_handler()
+ * 	Hold and set the encap recieve handler of socket with offload method.
+ */
+static void nss_ipsec_klips_register_natt_handler(struct nss_ipsec_klips_tun *tun, struct sock *sk)
+{
+	/*
+	 * write lock is needed as we are modifying tunnel entry.
+	 */
+	BUG_ON(write_can_lock(&tunnel_map.lock));
+
+	sock_hold(sk);
+	tun->sk_encap_rcv = udp_sk(sk)->encap_rcv;
+	tun->sk = sk;
+	xchg(&udp_sk(sk)->encap_rcv, nss_ipsec_klips_offload_natt);
+}
+
+/*
+ * nss_ipsec_klips_unregister_natt_handler()
+ * 	 Release socket and revert encap recieve handler to original.
+ */
+static void nss_ipsec_klips_unregister_natt_handler(struct nss_ipsec_klips_tun *tun, struct sock *sk)
+{
+	/*
+	 * write lock is needed as we are modifying tunnel entry.
+	 */
+	BUG_ON(write_can_lock(&tunnel_map.lock));
+
+	xchg(&udp_sk(tun->sk)->encap_rcv, tun->sk_encap_rcv);
+	sock_put(tun->sk);
+	tun->sk = NULL;
+	tun->sk_encap_rcv = NULL;
+}
+
+/*
+ * nss_ipsec_klips_trap_encap()
+ *	Trap IPsec pkts for sending encap fast path rules.
+ */
+static int32_t nss_ipsec_klips_trap_encap(struct sk_buff *skb, struct nss_cfi_crypto_info *crypto)
+{
+	uint16_t crypto_idx = crypto->sid & NSS_IPSEC_KLIPS_SES_MASK;
+	struct nss_ipsecmgr_sa_tuple sa_tuple = {0};
+	struct nss_ipsec_klips_skb_cb *ipsec_cb;
+	struct nss_ipsec_klips_sa *sa_entry;
+	struct nss_ipsecmgr_sa_data sa = {0};
+	struct nss_ipsec_klips_tun *tun;
+	nss_ipsecmgr_status_t status;
+	struct net_device *nss_dev;
+	enum nss_ipsecmgr_algo algo;
+	bool transport_mode;
+	bool natt;
+	int8_t iv_blk_len;
+	uint8_t *payload;
+	uint32_t if_num;
+	uint8_t ttl;
+
+	BUG_ON(skb_is_nonlinear(skb) || skb_has_frag_list(skb));
+
+	iv_blk_len = nss_ipsec_klips_get_blk_len(crypto->algo);
+	if (iv_blk_len < 0) {
+		nss_ipsec_klips_warn("%px:Failed to map valid IV and block length\n", skb);
+		return -EOPNOTSUPP;
+	}
+
+	algo = nss_ipsec_klips_get_algo(crypto->algo);
+	if (algo >= NSS_IPSECMGR_ALGO_MAX) {
+		nss_ipsec_klips_warn("%px:Failed to map valid algo\n", skb);
+		return -EOPNOTSUPP;
+	}
+
+	ipsec_cb = nss_ipsec_klips_get_skb_cb(skb);
+	if (!ipsec_cb) {
+		nss_ipsec_klips_warn("%px:Unable to get ipsec cb\n", skb);
+		return -ENOENT;
+	}
+
+	transport_mode = ipsec_cb->flags & NSS_IPSEC_KLIPS_FLAG_TRANSPORT_MODE;
+	natt = ipsec_cb->flags & NSS_IPSEC_KLIPS_FLAG_NATT;
+
+	/*
+	 * construct SA information
+	 */
+	nss_ipsecmgr_sa_cmn_init_idx(&sa.cmn, algo, crypto->sid,
+				iv_blk_len, iv_blk_len, crypto->hash_len,
+				transport_mode,			/* enable transport mode */
+				false,				/* no_trailer */
+				false,				/* esn */
+				natt);				/* natt */
+
+	/*
+	 * KLIPS adds NATT/UDP header after encrypt.
+	 */
+	payload = nss_ipsec_klips_outer2sa_tuple(skb->data, natt, &sa_tuple, &ttl, false);
+	BUG_ON(!payload);
+
+	sa.type = NSS_IPSECMGR_SA_TYPE_ENCAP;
+	sa.encap.ttl_hop_limit = ttl;
+
+	/*
+	 * Read lock needs to be taken here as the tunnel map table
+	 * is looked up
+	 */
+	write_lock(&tunnel_map.lock);
+
+	tun = nss_ipsec_klips_get_tun(ipsec_cb->hlos_dev);
+	if (!tun) {
+		write_unlock(&tunnel_map.lock);
+		nss_ipsec_klips_warn("%px:Failed to find NSS device mapped to KLIPS device\n", skb);
+		return -ENOENT;
+	}
+
+	nss_dev = tun->nss_dev;
+	BUG_ON(!nss_dev);
+
+	/*
+	 * This information is used by ECM to know input interface.
+	 */
+	skb->skb_iif = tun->klips_dev->ifindex;
+
+	sa_entry = nss_ipsec_klips_sa_lookup(tun, crypto_idx);
+	if (!sa_entry) {
+		/*
+		 * Allocate a new Entry
+		 */
+		sa_entry = kzalloc(sizeof(*sa_entry), GFP_ATOMIC);
+		if (!sa_entry) {
+			write_unlock(&tunnel_map.lock);
+			return -ENOMEM;
+		}
+
+		sa_entry->sid = crypto_idx;
+		memcpy(&sa_entry->outer, &sa_tuple, sizeof(sa_entry->outer));
+
+		INIT_LIST_HEAD(&sa_entry->list);
+		list_add_tail(&sa_entry->list, &tun->sa_list);
+	}
+
+	/*
+	 * We blindly attempt an add to the IPsec manager database
+	 * If, this is a duplicate entry then it will return a status then we
+	 * move forward with flow add. Otherwise we have stale entry
+	 * in our database which needs to be removed
+	 */
+
+	status = nss_ipsecmgr_sa_add(nss_dev, &sa_tuple, &sa, &if_num);
+
+	/*
+	 * If, SA add fails then there is no need to add the flow
+	 */
+	if ((status != NSS_IPSECMGR_OK) && (status != NSS_IPSECMGR_DUPLICATE_SA)) {
+		list_del_init(&sa_entry->list);
+		write_unlock(&tunnel_map.lock);
+		kfree(sa_entry);
+		return -EINVAL;
+	}
+
+	write_unlock(&tunnel_map.lock);
+	nss_ipsec_klips_trace("%px: Encap SA rule message sent\n", tun);
+
+	return 0;
+}
+
+/*
+ * nss_ipsec_klips_trap_decap()
+ *	Trap IPsec pkts for sending decap fast path rules.
+ */
+static int32_t nss_ipsec_klips_trap_decap(struct sk_buff *skb, struct nss_cfi_crypto_info *crypto)
+{
+	struct nss_ipsecmgr_flow_tuple flow_tuple = {0};
+	struct nss_ipsecmgr_sa_tuple sa_tuple = {0};
+	uint16_t crypto_idx = crypto->sid & NSS_IPSEC_KLIPS_SES_MASK;
+	struct nss_ipsec_klips_tun *tun;
+	struct nss_ipsec_klips_skb_cb *skb_cb;
+	struct nss_ipsecmgr_sa_data sa = {0};
+	struct nss_ipsec_klips_sa *sa_entry;
+	nss_ipsecmgr_status_t status;
+	struct net_device *nss_dev;
+	enum nss_ipsecmgr_algo algo;
+	bool transport_mode;
+	int8_t iv_blk_len;
+	uint32_t if_num;
+	uint8_t *payload;
+	uint8_t ttl;
+	bool natt;
+
+	iv_blk_len = nss_ipsec_klips_get_blk_len(crypto->algo);
+	if (iv_blk_len < 0) {
+		nss_ipsec_klips_warn("%px:Failed to map valid IV and block length\n", skb);
+		return -EOPNOTSUPP;
+	}
+
+	algo = nss_ipsec_klips_get_algo(crypto->algo);
+	if (algo >= NSS_IPSECMGR_ALGO_MAX) {
+		nss_ipsec_klips_warn("%px:Failed to map valid algo\n", skb);
+		return -EOPNOTSUPP;
+	}
+
+	skb_cb = nss_ipsec_klips_get_skb_cb(skb);
+	if (!skb_cb) {
+		nss_ipsec_klips_warn("%px:skb->cb is NULL\n", skb);
+		return -EINVAL;
+	}
+
+	transport_mode = skb_cb->flags & NSS_IPSEC_KLIPS_FLAG_TRANSPORT_MODE;
+	natt = skb_cb->flags & NSS_IPSEC_KLIPS_FLAG_NATT;
+
+	/*
+	 * construct SA information
+	 */
+	nss_ipsecmgr_sa_cmn_init_idx(&sa.cmn, algo, crypto->sid,
+				iv_blk_len, iv_blk_len, crypto->hash_len,
+				transport_mode,	/* enable transport mode */
+				false,	/* no_trailer */
+				false,	/* esn */
+				natt	/* natt */
+				);
+
+	/*
+	 * construct outer flow information
+	 */
+	payload = nss_ipsec_klips_outer2sa_tuple(skb_network_header(skb), natt, &sa_tuple, &ttl, true);
+	BUG_ON(!payload);
+
+	if (!nss_ipsec_klips_outer2flow_tuple(skb_network_header(skb), natt, &flow_tuple)) {
+		nss_ipsec_klips_warn("%px: Invalid packet\n", skb);
+		return -EINVAL;
+	}
+
+	sa.type = NSS_IPSECMGR_SA_TYPE_DECAP;
+	sa.decap.replay_win = NSS_IPSEC_KLIPS_BITS2BYTE(skb_cb->replay_win);
+
+	/*
+	 * Read lock needs to be taken here as the tunnel map table
+	 * is looked up
+	 */
+	write_lock(&tunnel_map.lock);
+
+	tun = nss_ipsec_klips_get_tun(skb_cb->hlos_dev);
+	if (!tun) {
+		write_unlock(&tunnel_map.lock);
+		nss_ipsec_klips_warn("%px:Failed to find NSS device mapped to KLIPS device\n", skb);
+		return -ENOENT;
+	}
+
+	nss_dev = tun->nss_dev;
+	BUG_ON(!nss_dev);
+
+	if (!tun->addr.ver) {
+		/*
+		 * Fill tunnel address.
+		 */
+		nss_ipsec_klips_outer2tun_addr(skb_network_header(skb), &tun->addr);
+		nss_ipsec_klips_trace("%px:Tunnel tuple configured\n", skb);
+	}
+
+	/*
+	 * This information is used by ECM to know input interface.
+	 */
+	skb->skb_iif = tun->klips_dev->ifindex;
+
+	sa_entry = nss_ipsec_klips_sa_lookup(tun, crypto_idx);
+	if (!sa_entry) {
+		/*
+		 * Allocate a new Entry
+		 */
+		sa_entry = kzalloc(sizeof(*sa_entry), GFP_ATOMIC);
+		if (!sa_entry) {
+			write_unlock(&tunnel_map.lock);
+			return -ENOMEM;
+		}
+
+		sa_entry->sid = crypto_idx;
+		memcpy(&sa_entry->outer, &sa_tuple, sizeof(sa_entry->outer));
+
+		INIT_LIST_HEAD(&sa_entry->list);
+		list_add_tail(&sa_entry->list, &tun->sa_list);
+	}
+
+	/*
+	 * We blindly attempt an add to the IPsec manager database
+	 * If, this is a duplicate entry then it will return a status then we
+	 * move forward with flow add. Otherwise we have stale entry
+	 * in our database which needs to be removed
+	 */
+
+	status = nss_ipsecmgr_sa_add(nss_dev, &sa_tuple, &sa, &if_num);
+
+	/*
+	 * If, SA add fails then there is no need to add the flow
+	 */
+	if ((status != NSS_IPSECMGR_OK) && (status != NSS_IPSECMGR_DUPLICATE_SA)) {
+		list_del_init(&sa_entry->list);
+		write_unlock(&tunnel_map.lock);
+		kfree(sa_entry);
+		return -EINVAL;
+	}
+
+	/*
+	 * Convert socket to use our (de)encapsulation routine and save original pointers in tun map.
+	 */
+	if (natt && !tun->sk && skb_cb->sk) {
+		nss_ipsec_klips_info("%px: Updating sock(%px) encap_rcv handler\n", tun, skb_cb->sk);
+		nss_ipsec_klips_register_natt_handler(tun, skb_cb->sk);
+	}
+
+	write_unlock(&tunnel_map.lock);
+
+	return 0;
+}
+
+/*
+ * nss_ipsec_klips_get_dev_and_type()
+ *	Get ipsecmgr tunnel netdevice and type for klips netdevice
+ */
+static struct net_device *nss_ipsec_klips_get_dev_and_type(struct net_device *klips_dev, struct sk_buff *skb,
+							int32_t *type)
+{
+
+	switch (ip_hdr(skb)->version) {
+	case 4: {
+		struct iphdr *iph = ip_hdr(skb);
+		uint16_t natt_port = ntohs(NSS_IPSECMGR_NATT_PORT_DATA);
+
+		/*
+		 * Protocol is ESP, type is OUTER
+		 */
+		if (iph->protocol == IPPROTO_ESP) {
+			*type = NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_OUTER;
+			break;
+		}
+
+		skb_set_transport_header(skb, sizeof(*iph));
+		if ((iph->protocol == IPPROTO_UDP) && (udp_hdr(skb)->dest == natt_port)) {
+			*type = NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_OUTER;
+			break;
+		}
+
+		*type = NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_INNER;
+		break;
+	}
+
+	case 6: {
+		struct ipv6hdr *ip6h = ipv6_hdr(skb);
+
+		/*
+		 * Protocol is ESP, type is OUTER
+		 */
+		if (ip6h->nexthdr == IPPROTO_ESP) {
+			*type = NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_OUTER;
+			break;
+		}
+
+		/*
+		 * All other case it is Inner
+		 */
+		*type = NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_INNER;
+		break;
+	}
+
+	default:
+		nss_ipsec_klips_warn("%px: Packet is not IPv4 or IPv6. version=%d\n", klips_dev, ip_hdr(skb)->version);
+		return NULL;
+	}
+
+	return nss_ipsec_klips_get_tun_dev(klips_dev);
+}
+
+/*
+ * nss_ipsec_klips_flow_delete()
+ *	Delete a ipsec flow.
+ */
+static bool nss_ipsec_klips_flow_delete(struct net_device *nss_dev, struct nss_ipsecmgr_flow_tuple *flow_tuple)
+{
+	struct nss_ipsecmgr_sa_tuple sa_tuple = {0};
+
+	nss_ipsec_klips_trace("%px: Flow delete for tuple src_ip= %u:%u:%u:%u, dest_ip= %u:%u:%u:%u,\
+			proto_next_hdr=%u, ip_version= %u\n", nss_dev, flow_tuple->src_ip[0],
+			flow_tuple->src_ip[1], flow_tuple->src_ip[2], flow_tuple->src_ip[3],
+			flow_tuple->dest_ip[0], flow_tuple->dest_ip[1], flow_tuple->dest_ip[2],
+			flow_tuple->dest_ip[3], flow_tuple->proto_next_hdr, flow_tuple->ip_version);
+
+	if (nss_ipsecmgr_flow_get_sa(nss_dev, flow_tuple, &sa_tuple) != NSS_IPSECMGR_OK) {
+		nss_ipsec_klips_trace("%px: SA not found\n", nss_dev);
+		return false;
+	}
+
+	nss_ipsecmgr_flow_del(nss_dev, flow_tuple, &sa_tuple);
+
+	/*
+	 * TODO:handle case when tx message to NSS fails in nss_ipsecmgr_flow_del()
+	 */
+	nss_ipsec_klips_trace("%px: IPSec Flow deleted\n", nss_dev);
+	return true;
+}
+
+/*
+ * nss_ipsec_klips_register_esp_handler()
+ * 	Register ESP handler.
+ */
+static void nss_ipsec_klips_register_esp_handler(void)
+{
+	const struct net_protocol *ip_prot;
+
+	/*
+	 * This function must be called with rtnl lock.
+	 */
+	ASSERT_RTNL();
+
+	if (klips_esp6_handler && klips_esp_handler) {
+		nss_ipsec_klips_trace("ESP handler already registered\n");
+		return;
+	}
+
+	if (inet_update_protocol(&esp_protocol, IPPROTO_ESP, &klips_esp_handler) < 0) {
+		nss_ipsec_klips_err("Failed to update ESP protocol handler for IPv4\n");
+
+		/*
+		 * In error case function is modifying this variable, revert it to NULL.
+		 */
+		xchg(&klips_esp_handler, NULL);
+		return;
+	}
+
+	if (inet6_update_protocol(&esp6_protocol, IPPROTO_ESP, &klips_esp6_handler) < 0) {
+		nss_ipsec_klips_err("Failed to update ESP protocol handler for IPv6\n");
+
+		/*
+		 * Revert v4 ESP handler to original handler.
+		 */
+		xchg(&klips_esp6_handler, NULL);
+		inet_update_protocol(klips_esp_handler, IPPROTO_ESP, &ip_prot);
+		xchg(&klips_esp_handler, NULL);
+		return;
+	}
+
+	nss_ipsec_klips_info("ESP handler registered\n");
+}
+
+/*
+ * nss_ipsec_klips_unregister_esp_handler()
+ * 	Unregister ESP handler.
+ */
+static void nss_ipsec_klips_unregister_esp_handler(void)
+{
+	const struct inet6_protocol *ip6_prot;
+	const struct net_protocol *ip_prot;
+
+	/*
+	 * This function must be called with rtnl lock.
+	 */
+	ASSERT_RTNL();
+
+	if (klips_esp_handler) {
+		inet_update_protocol(klips_esp_handler, IPPROTO_ESP, &ip_prot);
+		xchg(&klips_esp_handler, NULL);
+		nss_ipsec_klips_info("IPv4 ESP handler un-registered\n");
+	}
+
+	if (klips_esp6_handler) {
+		inet6_update_protocol(klips_esp6_handler, IPPROTO_ESP, &ip6_prot);
+		xchg(&klips_esp6_handler, NULL);
+		nss_ipsec_klips_info("IPv6 ESP handler un-registered\n");
+	}
+}
+
+/*
+ * nss_ipsec_klips_dev_event()
+ *	notifier function for IPsec device events.
+ */
+static int nss_ipsec_klips_dev_event(struct notifier_block *this, unsigned long event, void *ptr)
+{
+	struct net_device *klips_dev = netdev_notifier_info_to_dev(ptr);
+	struct nss_ipsecmgr_callback ipsec_cb = {0};
+	struct nss_ipsec_klips_tun *tun;
+	bool remove_esp_handler = false;
+	struct net_device *nss_dev;
+	int16_t index = 0;
+	int mtu = 0;
+
+	if (tunnel_map.max <= tunnel_map.used)
+		return NOTIFY_DONE;
+
+	switch (event) {
+	case NETDEV_REGISTER:
+		index = nss_ipsec_klips_get_index(klips_dev->name);
+		if ((index < 0) || (index >= tunnel_map.max)) {
+			nss_ipsec_klips_trace("Netdev(%s) is not KLIPS IPsec related\n", klips_dev->name);
+			return NOTIFY_DONE;
+		}
+
+		/*
+		 * All exception packets are handled by IPsec manager and
+		 * hence, the lack of need to register a data callback.
+		 * The event callback can be used, if the need arises
+		 * to send an asynchronous event to OCF layer.
+		 */
+		ipsec_cb.skb_dev = klips_dev;
+		ipsec_cb.data_cb = NULL;
+		ipsec_cb.event_cb = NULL;
+
+		nss_ipsec_klips_info("IPsec interface being registered: %s\n", klips_dev->name);
+
+		nss_dev = nss_ipsecmgr_tunnel_add(&ipsec_cb);
+		if (!nss_dev) {
+			nss_ipsec_klips_err("NSS IPsec tunnel dev allocation failed for %s\n", klips_dev->name);
+			return NOTIFY_DONE;
+		}
+
+		/*
+		 * Write lock is needed here since tunnel map table
+		 * is modified
+		 */
+		write_lock_bh(&tunnel_map.lock);
+
+		tunnel_map.used++;
+		tunnel_map.tbl[index].nss_dev = nss_dev;
+		tunnel_map.tbl[index].klips_dev = klips_dev;
+		tunnel_map.tbl[index].sk = NULL;
+		tunnel_map.tbl[index].sk_encap_rcv = NULL;
+		memset(&tunnel_map.tbl[index].addr, 0, sizeof(tunnel_map.tbl[index].addr));
+		dev_hold(klips_dev);
+
+		write_unlock_bh(&tunnel_map.lock);
+
+		/*
+		 * Register ESP handler.
+		 */
+		nss_ipsec_klips_register_esp_handler();
+		break;
+
+	case NETDEV_UNREGISTER:
+		index = nss_ipsec_klips_get_index(klips_dev->name);
+		if ((index < 0) || (index >= tunnel_map.max)) {
+			nss_ipsec_klips_trace("Netdev(%s) is not KLIPS IPsec related\n", klips_dev->name);
+			return NOTIFY_DONE;
+		}
+
+		/*
+		 * Read lock necessary as tunnel map table is accessed but
+		 * not modified
+		 */
+		write_lock_bh(&tunnel_map.lock);
+		tun = &tunnel_map.tbl[index];
+
+		if (!tun->klips_dev || !tun->nss_dev) {
+			write_unlock_bh(&tunnel_map.lock);
+			nss_ipsec_klips_err("%px:Failed to find tunnel map\n", klips_dev);
+			return NOTIFY_DONE;
+		}
+
+		if (tun->klips_dev != klips_dev) {
+			write_unlock_bh(&tunnel_map.lock);
+			nss_ipsec_klips_err("Failed to find NSS IPsec tunnel dev for %s\n", klips_dev->name);
+			return NOTIFY_DONE;
+		}
+
+		/*
+		 * Since, we created the NSS device then we should not never see this happen
+		 */
+		nss_dev = tun->nss_dev;
+		BUG_ON(!nss_dev);
+
+		nss_ipsec_klips_info("IPsec interface being unregistered: %s\n", klips_dev->name);
+		nss_ipsec_klips_sa_flush(tun, nss_dev);
+
+		/*
+		 * Write lock is needed here since tunnel map table
+		 * is modified
+		 */
+		tun->nss_dev = NULL;
+		tun->klips_dev = NULL;
+
+		/*
+		 * Revert socket encap_rcv. Those fields are only used for NATT.
+		 */
+		if (tun->sk) {
+			nss_ipsec_klips_info("%px: Releasing socket(%px)\n", tun, tun->sk);
+			nss_ipsec_klips_unregister_natt_handler(tun, tun->sk);
+		}
+
+		tunnel_map.used--;
+
+		/*
+		 * Unregister the ESP handler only when all tunnels are unregistered.
+		 */
+		remove_esp_handler = !tunnel_map.used;
+
+		write_unlock_bh(&tunnel_map.lock);
+
+		nss_ipsecmgr_tunnel_del(nss_dev);
+		dev_put(klips_dev);
+
+		if (remove_esp_handler) {
+			nss_ipsec_klips_unregister_esp_handler();
+		}
+		break;
+
+	case NETDEV_CHANGEMTU:
+		index = nss_ipsec_klips_get_index(klips_dev->name);
+		if ((index < 0) || (index >= tunnel_map.max)) {
+			nss_ipsec_klips_trace("Netdev(%s) is not KLIPS IPsec related\n", klips_dev->name);
+			return NOTIFY_DONE;
+		}
+
+		/*
+		 * Read lock necessary as tunnel map table is accessed but
+		 * not modified
+		 */
+		write_lock_bh(&tunnel_map.lock);
+		tun = &tunnel_map.tbl[index];
+
+		if (!tun->klips_dev || !tun->nss_dev) {
+			write_unlock_bh(&tunnel_map.lock);
+			nss_ipsec_klips_err("%px:Failed to find tunnel map\n", klips_dev);
+			return NOTIFY_DONE;
+		}
+
+		if (tun->klips_dev != klips_dev) {
+			write_unlock_bh(&tunnel_map.lock);
+			nss_ipsec_klips_err("Failed to find NSS IPsec tunnel dev for %s\n", klips_dev->name);
+			return NOTIFY_DONE;
+		}
+
+		nss_dev = tun->nss_dev;
+		mtu = klips_dev->mtu;
+		write_unlock_bh(&tunnel_map.lock);
+
+		dev_set_mtu(nss_dev, mtu);
+		break;
+
+	default:
+		return NOTIFY_DONE;
+	}
+
+	return NOTIFY_OK;
+}
+
+/*
+ * nss_ipsec_klips_ecm_conn_to_tuple()
+ * 	Converts ecm_notifier_connection_data to nss_ipsecmgr_flow_tuple.
+ */
+static inline bool nss_ipsec_klips_ecm_conn_to_tuple(struct ecm_notifier_connection_data *conn,
+		struct nss_ipsecmgr_flow_tuple *tuple, bool is_return)
+{
+	struct in6_addr *sip6, *dip6;
+	struct in_addr *sip, *dip;
+	int i;
+
+	memset(tuple, 0, sizeof(*tuple));
+	tuple->ip_version = conn->tuple.ip_ver;
+	tuple->proto_next_hdr = conn->tuple.protocol;
+
+	if (is_return) {
+		sip = &conn->tuple.dest.in;
+		dip = &conn->tuple.src.in;
+		sip6 = &conn->tuple.dest.in6;
+		dip6 = &conn->tuple.src.in6;
+		tuple->sport = conn->tuple.dst_port;
+		tuple->dport = conn->tuple.src_port;
+	} else {
+		dip = &conn->tuple.dest.in;
+		sip = &conn->tuple.src.in;
+		dip6 = &conn->tuple.dest.in6;
+		sip6 = &conn->tuple.src.in6;
+		tuple->dport = conn->tuple.dst_port;
+		tuple->sport = conn->tuple.src_port;
+	}
+
+	switch (tuple->ip_version) {
+	case 4:
+		tuple->dest_ip[0] = dip->s_addr;
+		tuple->src_ip[0] = sip->s_addr;
+		break;
+
+	case 6:
+		for (i = 0; i < 4; i++) {
+			tuple->dest_ip[i] = dip6->s6_addr32[i];
+			tuple->src_ip[i] = sip6->s6_addr32[i];
+		}
+		break;
+
+	default:
+		/*
+                 * Shouldn't come here.
+                 */
+                nss_ipsec_klips_err("%px: Invalid protocol\n", conn);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_ipsec_klips_ecm_conn_notify()
+ *	Notifier function for ECM connection events.
+ */
+static int nss_ipsec_klips_ecm_conn_notify(struct notifier_block *nb, unsigned long event, void *ptr)
+{
+	struct ecm_notifier_connection_data *conn = ptr;
+	struct nss_ipsecmgr_flow_tuple flow_tuple = {0};
+	struct net_device *nss_dev;
+	bool is_return = false;
+
+	if (event != ECM_NOTIFIER_ACTION_CONNECTION_REMOVED) {
+
+		/*
+		 * Invalid event, Do nothing.
+		 */
+		nss_ipsec_klips_trace("%px: Invalid event recieved\n", nb);
+		return NOTIFY_OK;
+	}
+
+	nss_ipsec_klips_trace("%px: Event ECM_NOTIFIER_ACTION_CONNECTION_REMOVE recieved\n", nb);
+
+	switch (conn->tuple.protocol) {
+	case IPPROTO_ESP:
+
+		/*
+		 * Connection belongs to outer flow and it will delete when parent SA gets deref.
+		 */
+		nss_ipsec_klips_trace("%px: Connection protocol is ESP, no action required\n", nb);
+		return NOTIFY_OK;
+
+	case IPPROTO_UDP:
+
+		/*
+		 * If Connection belongs to NAT-T (Outer flow) then it will delete when parent SA gets deref.
+		 */
+		if (conn->tuple.src_port == NSS_IPSECMGR_NATT_PORT_DATA) {
+			nss_ipsec_klips_trace("%px: Connection is with NAT-T source port, no action required\n", nb);
+			return NOTIFY_OK;
+		} else if (conn->tuple.dst_port == NSS_IPSECMGR_NATT_PORT_DATA) {
+			nss_ipsec_klips_trace("%px: Connection is with NAT-T dest port, no action required\n", nb);
+			return NOTIFY_OK;
+		}
+
+		break;
+
+	default:
+		break;
+	}
+
+	nss_dev = nss_ipsec_klips_get_tun_dev(conn->from_dev);
+	if (nss_dev) {
+		is_return = true;
+		nss_ipsec_klips_trace("%px: Tunnel Device found in 'from' dir\n", conn);
+		goto found;
+	}
+
+	nss_dev = nss_ipsec_klips_get_tun_dev(conn->to_dev);
+	if (!nss_dev) {
+		nss_ipsec_klips_trace("%px: Tunnel Device not found for 'to_dev' & 'from_dev'\n", conn);
+		return NOTIFY_DONE;
+	}
+
+	nss_ipsec_klips_trace("%px: Tunnel Device found in 'to' dir\n", conn);
+
+found:
+	if (!nss_ipsec_klips_ecm_conn_to_tuple(conn, &flow_tuple, is_return)) {
+		nss_ipsec_klips_err("%px: Invalid connection data\n", conn);
+		dev_put(nss_dev);
+		return NOTIFY_DONE;
+	}
+
+	if (!nss_ipsec_klips_flow_delete(nss_dev, &flow_tuple)) {
+		nss_ipsec_klips_trace("%px: nss_ipsec_klips_flow_delete failed\n", conn);
+	}
+
+	dev_put(nss_dev);
+	return NOTIFY_OK;
+}
+
+static struct notifier_block nss_ipsec_klips_notifier = {
+	.notifier_call = nss_ipsec_klips_dev_event,
+};
+
+static struct ecm_interface_ipsec_callback nss_ipsec_klips_ecm =  {
+	.tunnel_get_and_hold = nss_ipsec_klips_get_dev_and_type
+};
+
+static struct notifier_block nss_ipsec_klips_ecm_conn_notifier = {
+	.notifier_call = nss_ipsec_klips_ecm_conn_notify,
+};
+
+#if defined(NSS_L2TPV2_ENABLED)
+static struct l2tpmgr_ipsecmgr_cb nss_ipsec_klips_l2tp =  {
+	.get_ifnum_by_dev = nss_ipsec_klips_get_inner_ifnum,
+	.get_ifnum_by_ipv4_addr = NULL
+};
+#endif
+
+/*
+ * nss_ipsec_klips_init_module()
+ *	Initialize IPsec rule tables and register various callbacks
+ */
+int __init nss_ipsec_klips_init_module(void)
+{
+	struct nss_ipsec_klips_tun *tun;
+	int i;
+
+	nss_ipsec_klips_info("NSS IPsec (platform - IPQ807x , %s) loaded\n", NSS_IPSEC_KLIPS_BUILD_ID);
+
+	tunnel_map.tbl = vzalloc(sizeof(struct nss_ipsec_klips_tun) * tunnel_max);
+	if (!tunnel_map.tbl) {
+		nss_ipsec_klips_warn("Unable to allocate tunnel map table\n");
+		return -1;
+	}
+
+	for (i = 0, tun = tunnel_map.tbl; i < tunnel_max; i++, tun++) {
+		tun->nss_dev = NULL;
+		tun->klips_dev = NULL;
+		INIT_LIST_HEAD(&tun->sa_list);
+	}
+
+	rwlock_init(&tunnel_map.lock);
+
+	tunnel_map.max = tunnel_max;
+	tunnel_map.used = 0;
+
+	register_netdevice_notifier(&nss_ipsec_klips_notifier);
+	nss_cfi_ocf_register_ipsec(nss_ipsec_klips_trap_encap, nss_ipsec_klips_trap_decap, nss_ipsec_klips_free_session,
+					nss_ipsec_klips_offload_inner);
+
+	ecm_interface_ipsec_register_callbacks(&nss_ipsec_klips_ecm);
+	ecm_notifier_register_connection_notify(&nss_ipsec_klips_ecm_conn_notifier);
+#if defined(NSS_L2TPV2_ENABLED)
+	l2tpmgr_register_ipsecmgr_callback_by_netdev(&nss_ipsec_klips_l2tp);
+#endif
+	return 0;
+}
+
+/*
+ * nss_ipsec_klips_exit_module()
+ *	Unregister callbacks/notifiers and clear all stale data
+ */
+void __exit nss_ipsec_klips_exit_module(void)
+{
+	struct nss_ipsec_klips_tun *tun;
+	int i;
+
+	/*
+	 * Detach the trap handlers and Linux NETDEV notifiers, before
+	 * unwinding the tunnels
+	 */
+
+	ecm_notifier_unregister_connection_notify(&nss_ipsec_klips_ecm_conn_notifier);
+	ecm_interface_ipsec_unregister_callbacks();
+#if defined(NSS_L2TPV2_ENABLED)
+	l2tpmgr_unregister_ipsecmgr_callback_by_netdev();
+#endif
+
+	nss_cfi_ocf_unregister_ipsec();
+	unregister_netdevice_notifier(&nss_ipsec_klips_notifier);
+
+	/*
+	 * Write lock needs to be taken here since SA table is
+	 * getting modified
+	 */
+	write_lock_bh(&tunnel_map.lock);
+
+	for (i = 0, tun = tunnel_map.tbl; i < tunnel_map.max; i++, tun++) {
+		if (!tun->nss_dev || !tun->klips_dev)
+			continue;
+
+		/*
+		 * Find the NSS device associated with klips device
+		 */
+		nss_ipsec_klips_sa_flush(tun, tun->nss_dev);
+		nss_ipsecmgr_tunnel_del(tun->nss_dev);
+		BUG_ON(!list_empty(&tun->sa_list));
+
+		/*
+		 * Reset the tunnel entry
+		 */
+		tun->nss_dev = NULL;
+		tun->klips_dev = NULL;
+		tunnel_map.used--;
+	}
+
+	write_unlock_bh(&tunnel_map.lock);
+
+	tunnel_map.used = tunnel_max;
+	tunnel_map.max = 0;
+
+	vfree(tunnel_map.tbl);
+	nss_ipsec_klips_info("module unloaded\n");
+}
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS IPsec offload glue");
+
+module_init(nss_ipsec_klips_init_module);
+module_exit(nss_ipsec_klips_exit_module);
diff --git a/qca-nss-clients/ipsecmgr/v2.0/plugins/klips/nss_ipsec_klips.h b/qca-nss-clients/ipsecmgr/v2.0/plugins/klips/nss_ipsec_klips.h
new file mode 100644
index 0000000..1382d21
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/plugins/klips/nss_ipsec_klips.h
@@ -0,0 +1,135 @@
+/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/**
+ * @file nss_ipsec_klips.h
+ * 	 cfi plugin header file
+ */
+#ifndef __NSS_IPSEC_KLIPS_H
+#define __NSS_IPSEC_KLIPS_H
+
+/**
+ * @file klips plugin for ipsec manager.
+ */
+
+#define NSS_IPSEC_KLIPS_NON_ESP_MARKER 0x0000
+
+typedef int (*sk_encap_rcv_method_t)(struct sock *sk, struct sk_buff *skb);
+
+#define NSS_IPSEC_KLIPS_DEBUG_LVL_ERROR 1
+#define NSS_IPSEC_KLIPS_DEBUG_LVL_WARN 2
+#define NSS_IPSEC_KLIPS_DEBUG_LVL_INFO 3
+#define NSS_IPSEC_KLIPS_DEBUG_LVL_TRACE 4
+
+#define nss_ipsec_klips_info_always(s, ...) pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_ipsec_klips_err(s, ...) do {	\
+	if (net_ratelimit()) {	\
+		pr_alert("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+} while (0)
+
+#define nss_ipsec_klips_warn(s, ...) do {	\
+	if (net_ratelimit()) {	\
+		pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+} while (0)
+
+#define nss_ipsec_klips_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_ipsec_klips_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#define nss_ipsec_klips_err(s, ...) {	\
+	if (NSS_IPSEC_KLIPS_DEBUG_LEVEL > NSS_IPSEC_KLIPS_DEBUG_LVL_ERROR) {	\
+		pr_alert("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+#define nss_ipsec_klips_warn(s, ...) {	\
+	if (NSS_IPSEC_KLIPS_DEBUG_LEVEL > NSS_IPSEC_KLIPS_DEBUG_LVL_WARN) {	\
+		pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+#define nss_ipsec_klips_info(s, ...) {	\
+	if (NSS_IPSEC_KLIPS_DEBUG_LEVEL > NSS_IPSEC_KLIPS_DEBUG_LVL_INFO) {	\
+		pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+#define nss_ipsec_klips_trace(s, ...) {	\
+	if (NSS_IPSEC_KLIPS_DEBUG_LEVEL > NSS_IPSEC_KLIPS_DEBUG_LVL_TRACE) {	\
+		pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+
+#endif /* !CONFIG_DYNAMIC_DEBUG */
+
+#define NSS_IPSEC_KLIPS_BITS2BYTE(x) ((x) / BITS_PER_BYTE) /**< Bits to Bytes */
+#define nss_ipsec_klips_assert(expr) BUG_ON(!expr)
+
+#if !defined (CONFIG_NSS_IPSEC_KLIPS_DBG)
+#define nss_ipsec_klips_dbg(fmt, arg...)
+#define nss_ipsec_klips_dbg_skb(skb, limit)
+#define nss_ipsec_klips_dbg_data(data, len, c)
+
+#else
+#define nss_ipsec_klips_dbg(fmt, arg...)     printk(KERN_DEBUG fmt, ## arg)
+
+/**
+ * @brief print the skb contents till the limit
+ *
+ * @param skb[IN] skb data to print from
+ * @param limit[IN] limit for printing
+ */
+static inline void nss_ipsec_klips_dbg_skb(struct sk_buff *skb, uint32_t limit)
+{
+	uint32_t len;
+	int i;
+
+	len = (skb->len < limit) ? skb->len : limit;
+
+	printk("-- skb dump --\n");
+	for (i = 0; i < len; i++) {
+		printk("0x%02x ",skb->data[i]);
+	}
+	printk("\n");
+}
+
+/**
+ * @brief print data till length
+ *
+ * @param data[IN] data to print
+ * @param len[IN] length of data to print
+ * @param c[IN] charater to use between prints
+ */
+static inline void nss_ipsec_klips_dbg_data(uint8_t *data, uint16_t len, uint8_t c)
+{
+	int i = 0;
+
+	printk("-- data dump --\n");
+	for (i = 0; i < len; i++) {
+		printk("0x%02x%c", data[i], c);
+	}
+	printk("\n");
+}
+#endif
+
+#endif /* !__NSS_IPSEC_KLIPS_H */
diff --git a/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/Makefile b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/Makefile
new file mode 100644
index 0000000..b344da4
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/Makefile
@@ -0,0 +1,16 @@
+# XFRM plugin Makefile
+
+NSS_IPSEC_MOD_NAME=qca-nss-ipsec-xfrm
+
+obj-m += $(NSS_IPSEC_MOD_NAME).o
+
+$(NSS_IPSEC_MOD_NAME)-objs := nss_ipsec_xfrm.o
+$(NSS_IPSEC_MOD_NAME)-objs += nss_ipsec_xfrm_tunnel.o
+$(NSS_IPSEC_MOD_NAME)-objs += nss_ipsec_xfrm_sa.o
+$(NSS_IPSEC_MOD_NAME)-objs += nss_ipsec_xfrm_flow.o
+
+obj ?= .
+ccflags-y += -I$(obj)/
+ccflags-y += -DNSS_IPSEC_XFRM_DEBUG_LEVEL=3
+ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)"
+ccflags-y += -Wall -Werror
diff --git a/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm.c b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm.c
new file mode 100644
index 0000000..4ba7ab8
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm.c
@@ -0,0 +1,2400 @@
+/* Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/if.h>
+#include <linux/list.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <net/xfrm.h>
+#include <net/protocol.h>
+#include <linux/inetdevice.h>
+#include <linux/icmp.h>
+#include <net/addrconf.h>
+#include <linux/netfilter.h>
+#include <linux/debugfs.h>
+
+#include <nss_api_if.h>
+#include <nss_ipsec.h>
+#include <nss_ipsecmgr.h>
+#include <ecm_interface_ipsec.h>
+#include <ecm_notifier.h>
+#if defined(NSS_L2TPV2_ENABLED)
+#include <nss_l2tpmgr.h>
+#endif
+#include "nss_ipsec_xfrm_tunnel.h"
+#include "nss_ipsec_xfrm_sa.h"
+#include "nss_ipsec_xfrm_flow.h"
+#include "nss_ipsec_xfrm.h"
+
+/*
+ * Global NSS IPsec xfrm pluging instance
+ */
+static struct nss_ipsec_xfrm_drv g_ipsec_xfrm;
+
+/*
+ * Statistics print info
+ */
+static const struct nss_ipsec_xfrm_print nss_ipsec_xfrm_drv_stats[] = {
+	{"\tencap_nss", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\tencap_drop", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\tdecap_nss", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\tdecap_drop", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\tinner_except", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\tinner_drop", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\touter_except", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\touter_drop", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\ttun_alloced", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\ttun_dealloced", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\ttun_freed", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\tsa_alloced", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\tsa_dealloced", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\tsa_freed", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\tflow_alloced", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\tflow_dealloced", NSS_IPSEC_XFRM_PRINT_DWORD},
+	{"\tflow_freed", NSS_IPSEC_XFRM_PRINT_DWORD},
+};
+
+/*
+ * nss_ipsec_xfrm_drv_stats_size()
+ *	Calculate size of drv stats.
+ */
+static ssize_t nss_ipsec_xfrm_drv_stats_size(void)
+{
+	const struct nss_ipsec_xfrm_print *prn = nss_ipsec_xfrm_drv_stats;
+	ssize_t len = NSS_IPSEC_XFRM_PRINT_EXTRA;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(nss_ipsec_xfrm_drv_stats); i++, prn++)
+		len += strlen(prn->str) + prn->var_size;
+
+	return len;
+}
+
+/*
+ * nss_ipsec_xfrm_drv_print()
+ *	Print drv stats.
+ */
+static ssize_t nss_ipsec_xfrm_drv_print(struct nss_ipsec_xfrm_drv *drv , char *buf, ssize_t max_len)
+{
+	const struct nss_ipsec_xfrm_print *prn = nss_ipsec_xfrm_drv_stats;
+	atomic64_t *stats_dword = (atomic64_t *)&drv->stats;
+	ssize_t len = 0;
+	int i;
+
+	/*
+	 * This expects a strict order as per the stats structure
+	 */
+	len += snprintf(buf + len, max_len - len, "stats: {\n");
+
+	for (i = 0; i < ARRAY_SIZE(nss_ipsec_xfrm_drv_stats); i++, prn++, stats_dword++)
+		len += snprintf(buf + len, max_len - len, "%s: %llu\n", prn->str, (uint64_t)atomic64_read(stats_dword));
+
+	len += snprintf(buf + len, max_len - len, "}\n");
+
+	return len;
+}
+
+/*
+ * nss_ipsec_xfrm_drv_read()
+ *	Read nss ipsec xfrm drv info
+ */
+ssize_t nss_ipsec_xfrm_drv_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	struct nss_ipsec_xfrm_drv *drv = fp->private_data;
+	ssize_t print_len = drv->stats_len;
+	ssize_t len = 0;
+	char *buf;
+
+	buf = vzalloc(print_len);
+	if (!buf) {
+		nss_ipsec_xfrm_warn("%px: failed to allocate print buffer (req:%zd)", drv, print_len);
+		return 0;
+	}
+
+	len = nss_ipsec_xfrm_drv_print(drv, buf, print_len);
+
+	len = simple_read_from_buffer(ubuf, sz, ppos, buf, len);
+	vfree(buf);
+
+	return len;
+}
+
+/*
+ * file operation structure instance
+ */
+const struct file_operations nss_ipsec_xfrm_drv_file_ops = {
+	.open = simple_open,
+	.llseek = default_llseek,
+	.read = nss_ipsec_xfrm_drv_read,
+};
+
+/*
+ * nss_ipsec_xfrm_debugfs_deinit()
+ *	Remove debugfs.
+ */
+static void nss_ipsec_xfrm_debugfs_deinit(struct nss_ipsec_xfrm_drv *drv)
+{
+	debugfs_remove_recursive(drv->dentry);
+}
+
+/*
+ * nss_ipsec_xfrm_debugfs_init()
+ *	Init debugfs.
+ */
+static void nss_ipsec_xfrm_debugfs_init(struct nss_ipsec_xfrm_drv *drv)
+{
+	if (!debugfs_initialized())
+		return;
+
+	drv->dentry = debugfs_create_dir("qca-nss-ipsec-xfrm", NULL);
+	if (!drv->dentry) {
+		nss_ipsec_xfrm_err("%p: Failed to create debugfs\n", drv);
+		return;
+	}
+
+	drv->stats_len = nss_ipsec_xfrm_drv_stats_size();
+
+	debugfs_create_file("stats", S_IRUGO, drv->dentry, drv, &nss_ipsec_xfrm_drv_file_ops);
+}
+
+/*
+ * nss_ipsec_xfrm_hash_flow()
+ *	Computes hash for a given nss_ipsecmgr_flow_tuple.
+ */
+static inline uint32_t nss_ipsec_xfrm_hash_flow(struct nss_ipsecmgr_flow_tuple *tuple, uint32_t seed, uint16_t size)
+{
+	uint32_t hash;
+
+	BUILD_BUG_ON(!IS_ALIGNED(sizeof(struct nss_ipsecmgr_flow_tuple), sizeof(uint32_t)));
+	hash = nss_ipsec_xfrm_get_hash((uint32_t *)tuple, sizeof(struct nss_ipsecmgr_flow_tuple), seed);
+	return (hash & (size -1));
+}
+
+/*
+ * nss_ipsec_xfrm_init_flow_db()
+ *	Initializes the flow db.
+ */
+static void nss_ipsec_xfrm_init_flow_db(struct nss_ipsec_xfrm_drv *drv)
+{
+	uint32_t i;
+
+	for (i = 0; i < NSS_IPSEC_XFRM_FLOW_DB_MAX; i++) {
+		INIT_LIST_HEAD(&g_ipsec_xfrm.flow_db[i]);
+	}
+}
+
+/*
+ * nss_ipsec_xfrm_flush_flow()
+ *	Flushes the provided list of flows.
+ */
+void nss_ipsec_xfrm_flush_flow(struct list_head *head)
+{
+	struct nss_ipsec_xfrm_flow *flow, *tmp;
+
+	list_for_each_entry_safe(flow, tmp, head, list_entry) {
+		list_del_init(&flow->list_entry);
+		nss_ipsec_xfrm_flow_dealloc(flow);
+	}
+}
+
+/*
+ * nss_ipsec_xfrm_flush_flow_all()
+ *	Flush the flow DB. Caller needs to hold the write lock.
+ */
+void nss_ipsec_xfrm_flush_flow_all(struct nss_ipsec_xfrm_drv *drv)
+{
+	struct list_head free_head;
+	uint32_t i;
+
+	INIT_LIST_HEAD(&free_head);
+
+	/*
+	 * Splice the database and create list of flows to be freed
+	 */
+	write_lock_bh(&drv->lock);
+	for (i = 0; i < NSS_IPSEC_XFRM_FLOW_DB_MAX; i++) {
+		list_splice_init(&drv->flow_db[i], &free_head);
+	}
+
+	write_unlock_bh(&drv->lock);
+
+	nss_ipsec_xfrm_flush_flow(&free_head);
+}
+
+/*
+ * nss_ipsec_xfrm_flush_flow_by_sa()
+ *	Delete flows corrosponding to an xfrm_state. Caller needs to hold the write lock.
+ */
+static void nss_ipsec_xfrm_flush_flow_by_sa(struct nss_ipsec_xfrm_drv *drv, struct nss_ipsec_xfrm_sa *sa)
+{
+	struct list_head *db_head = drv->flow_db;
+	struct nss_ipsec_xfrm_flow *flow, *tmp;
+	struct list_head free_head;
+	uint32_t count;
+
+	INIT_LIST_HEAD(&free_head);
+	write_lock_bh(&drv->lock);
+
+	for (count = NSS_IPSEC_XFRM_FLOW_DB_MAX; count--; db_head++) {
+		list_for_each_entry_safe(flow, tmp, db_head, list_entry) {
+			if (flow->sa == sa) {
+				list_del_init(&flow->list_entry);
+				list_add(&flow->list_entry, &free_head);
+			}
+		}
+	}
+
+	write_unlock_bh(&drv->lock);
+	nss_ipsec_xfrm_flush_flow(&free_head);
+}
+
+/*
+ * nss_ipsec_xfrm_del_flow()
+ *	Delete the specified flow object. Caller needs to hold the write lock.
+ */
+static void nss_ipsec_xfrm_del_flow(struct nss_ipsec_xfrm_drv *drv, struct nss_ipsec_xfrm_flow *flow)
+{
+	write_lock_bh(&drv->lock);
+	list_del_init(&flow->list_entry);
+	write_unlock_bh(&drv->lock);
+
+	nss_ipsec_xfrm_trace("%p: Flow deleted from database\n", flow);
+
+	/*
+	 * Delete any other objects that could be holding reference to the flow object.
+	 * There is no such object for now. So we directly dealloc the flow object.
+	 */
+	nss_ipsec_xfrm_flow_dealloc(flow);
+}
+
+/*
+ * nss_ipsec_xfrm_add_flow()
+ *	Add a flow object to the SA, and insert into flow db. The caller needs to hold the write lock.
+ */
+static void nss_ipsec_xfrm_add_flow(struct nss_ipsec_xfrm_drv *drv, struct nss_ipsec_xfrm_flow *flow)
+{
+	uint32_t hash_idx;
+
+	write_lock_bh(&drv->lock);
+	hash_idx = nss_ipsec_xfrm_hash_flow(&flow->tuple, drv->hash_nonce, NSS_IPSEC_XFRM_FLOW_DB_MAX);
+	list_add(&flow->list_entry, &drv->flow_db[hash_idx]);
+	write_unlock_bh(&drv->lock);
+
+	nss_ipsec_xfrm_trace("%p: Flow added to database (hash_idx:%d)\n", flow, hash_idx);
+}
+
+/*
+ * nss_ipsec_xfrm_ref_flow()
+ *	Get flow and acquire reference to it.
+ *
+ * Note: The caller needs to hold the lock. This function holds the reference to the object
+ */
+static struct nss_ipsec_xfrm_flow *nss_ipsec_xfrm_ref_flow(struct nss_ipsec_xfrm_drv *drv,
+					struct nss_ipsecmgr_flow_tuple *tuple)
+{
+	struct nss_ipsec_xfrm_flow *flow;
+	uint32_t hash_idx;
+
+	hash_idx = nss_ipsec_xfrm_hash_flow(tuple, drv->hash_nonce, NSS_IPSEC_XFRM_FLOW_DB_MAX);
+	nss_ipsec_xfrm_trace("%p: flow hash_idx (%u)", drv, hash_idx);
+
+	read_lock_bh(&drv->lock);
+	list_for_each_entry(flow, &drv->flow_db[hash_idx], list_entry) {
+		if (nss_ipsec_xfrm_flow_match(flow, tuple)) {
+			flow = nss_ipsec_xfrm_flow_ref(flow);
+			read_unlock_bh(&drv->lock);
+			return flow;
+		}
+	}
+
+	read_unlock_bh(&drv->lock);
+
+	return NULL;
+}
+
+/*
+ * nss_ipsec_xfrm_hash_tun()
+ *	Computes hash for a given SIP/DIP pair.
+ */
+static inline uint32_t nss_ipsec_xfrm_hash_tun(const xfrm_address_t *dest_ip, const xfrm_address_t *src_ip,
+		uint32_t seed, uint16_t size)
+{
+	uint32_t hash;
+
+	hash = nss_ipsec_xfrm_get_hash((uint32_t *)dest_ip, 16, seed);
+	hash = nss_ipsec_xfrm_get_hash((uint32_t *)src_ip, 16, hash);
+	return (hash & (size -1));
+}
+
+/*
+ * nss_ipsec_xfrm_init_tun_db()
+ *	Initializes the tunnel db.
+ */
+static void nss_ipsec_xfrm_init_tun_db(struct nss_ipsec_xfrm_drv *drv)
+{
+	uint32_t i;
+
+	for (i = 0; i < NSS_IPSEC_XFRM_TUN_DB_MAX; i++) {
+		INIT_LIST_HEAD(&g_ipsec_xfrm.tun_db[i]);
+	}
+}
+
+/*
+ * nss_ipsec_xfrm_del_tun()
+ *	Remove tunnel from tunnel db.
+ */
+static void nss_ipsec_xfrm_del_tun(struct nss_ipsec_xfrm_drv *drv, struct nss_ipsec_xfrm_tunnel *tun)
+{
+	write_lock_bh(&drv->lock);
+	list_del_init(&tun->list_entry);
+	write_unlock_bh(&drv->lock);
+
+	nss_ipsec_xfrm_trace("%p: Tunnel deleted from database\n", tun);
+	nss_ipsec_xfrm_tunnel_dealloc(tun);
+}
+
+/*
+ * nss_ipsec_xfrm_add_tun()
+ *	Insert tunnel into tunnel db.
+ */
+static void nss_ipsec_xfrm_add_tun(struct nss_ipsec_xfrm_drv *drv, struct nss_ipsec_xfrm_tunnel *tun)
+{
+	uint32_t hash_idx;
+
+	write_lock_bh(&drv->lock);
+	hash_idx = nss_ipsec_xfrm_hash_tun(&tun->remote, &tun->local, drv->hash_nonce, NSS_IPSEC_XFRM_TUN_DB_MAX);
+	list_add(&tun->list_entry, &drv->tun_db[hash_idx]);
+	write_unlock_bh(&drv->lock);
+}
+
+/*
+ * nss_ipsec_xfrm_has_tun()
+ *	Returns true if the given net_dev corrosponds to a ipsec xfrm tunnel.
+ *	The caller needs to hold the read lock.
+ */
+bool nss_ipsec_xfrm_has_tun(struct nss_ipsec_xfrm_drv *drv, struct net_device *net_dev)
+{
+	struct list_head *db_head = drv->tun_db;
+	struct nss_ipsec_xfrm_tunnel *tun, *tmp;
+	bool found = false;
+	uint32_t count;
+
+	read_lock_bh(&drv->lock);
+	for (count = NSS_IPSEC_XFRM_TUN_DB_MAX; count--; db_head++) {
+		list_for_each_entry_safe(tun, tmp, db_head, list_entry) {
+			if (tun->dev == net_dev) {
+				found = true;
+				break;
+			}
+		}
+	}
+
+	read_unlock_bh(&drv->lock);
+	return found;
+}
+
+/*
+ * nss_ipsec_xfrm_ref_tun()
+ *	Get tunnel and acquire reference to it.
+ *
+ * Note: The caller needs to hold the lock. This function holds the reference to the object
+ */
+struct nss_ipsec_xfrm_tunnel *nss_ipsec_xfrm_ref_tun(struct nss_ipsec_xfrm_drv *drv, xfrm_address_t *local,
+				xfrm_address_t *remote, uint16_t family)
+{
+	struct nss_ipsec_xfrm_tunnel *tun;
+	uint32_t hash_idx;
+
+	BUG_ON((family != AF_INET) && (family != AF_INET6));
+
+	hash_idx = nss_ipsec_xfrm_hash_tun(remote, local, drv->hash_nonce, NSS_IPSEC_XFRM_TUN_DB_MAX);
+	nss_ipsec_xfrm_trace("%p: Tunnel add hash_idx %d", drv, hash_idx);
+
+	read_lock_bh(&drv->lock);
+	list_for_each_entry(tun, &drv->tun_db[hash_idx], list_entry) {
+		if (nss_ipsec_xfrm_tunnel_match(tun, remote, local, family)) {
+			tun = nss_ipsec_xfrm_tunnel_ref(tun);
+			read_unlock_bh(&drv->lock);
+			return tun;
+		}
+	}
+
+	read_unlock_bh(&drv->lock);
+	return NULL;
+}
+
+/*
+ * nss_ipsec_xfrm_verify_offload()
+ *	Verify if the XFRM state can be offloaded or not.
+ */
+static bool nss_ipsec_xfrm_verify_offload(struct xfrm_state *x)
+{
+	/*
+	 * We only support Tunnel and Transport Mode ESP
+	 */
+	if ((x->props.mode != XFRM_MODE_TUNNEL) && (x->props.mode != XFRM_MODE_TRANSPORT)) {
+		nss_ipsec_xfrm_warn("%p: xfrm_state offload not allowed: Non-Transport and Non-Tunnel\n", x);
+		return false;
+	}
+
+	/*
+	 * IPv6 transport mode is not supported.
+	 */
+	if ((x->props.family == AF_INET6) && (x->props.mode == XFRM_MODE_TRANSPORT)) {
+		nss_ipsec_xfrm_warn("%p: xfrm_state offload not allowed: Non-Transport and Non-Tunnel\n", x);
+		return false;
+	}
+
+	/*
+	 * Unsupported ESP-over-UDP encap type
+	 */
+	if (x->encap && (x->encap->encap_type != UDP_ENCAP_ESPINUDP)) {
+		nss_ipsec_xfrm_warn("%p: xfrm_state offload not allowed: Non ESP-over-UDP encap\n", x);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_ipsec_xfrm_get_dev_n_type()
+ *	Get ipsecmgr tunnel netdevice and flow type.
+ */
+static struct net_device *nss_ipsec_xfrm_get_dev_n_type(struct net_device *kdev, struct sk_buff *skb, int32_t *type)
+{
+	struct nss_ipsec_xfrm_drv * drv = &g_ipsec_xfrm;
+	uint8_t ip_ver = ip_hdr(skb)->version;
+	struct net_device *dev = NULL;
+	struct xfrm_state *x = NULL;
+
+	nss_ipsec_xfrm_trace("%px", skb);
+
+	BUG_ON((ip_ver != IPVERSION) && (ip_ver != 6));
+
+	/*
+	 * This is a plain text packet undergoing encap.
+	 */
+	x = skb_dst(skb)->xfrm;
+	if (x) {
+		struct nss_ipsec_xfrm_sa *sa = nss_ipsec_xfrm_sa_ref_by_state(x);
+		if (!sa) {
+			nss_ipsec_xfrm_trace("%p: Outbound Plain text packet(%px); not offloaded to NSS\n", sa, skb);
+			return NULL;
+		}
+
+		dev = sa->tun->dev;
+		dev_hold(dev);
+
+		*type = NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_INNER;
+		nss_ipsec_xfrm_trace("%p: Outbound packet(%px) for XFRM encap(%s)\n", sa, skb, dev->name);
+
+		nss_ipsec_xfrm_sa_deref(sa);
+		return dev;
+	}
+
+	/*
+	 * dst is not xfrm. This means packet could be:-
+	 * 1. Outbound encapsulated (skb->iif = ipsectunX)
+	 * 2. Inbound decapsulated (skb->iif = ipsectunX)
+	 * 3. Inbound encapsulated (ECM never sees such a packet)
+	 * 4. None of the above(don't care for us)
+	 */
+	dev = dev_get_by_index(&init_net, skb->skb_iif);
+	if (!dev) {
+		return NULL;
+	}
+
+	/*
+	 * It is an IPsec flow, but is it really bound to a tunnel managed by us.
+	 */
+	if (!nss_ipsec_xfrm_has_tun(drv, dev)) {
+		nss_ipsec_xfrm_trace("%p: IPsec Flow not offloaded to NSS, (%px); skb_iif (%s)\n", drv, skb, dev->name);
+		dev_put(dev);
+		return NULL;
+	}
+
+	/*
+	 * Outbound and encapuslated
+	 */
+	if ((ip_ver == IPVERSION) && (IPCB(skb)->flags & IPSKB_XFRM_TRANSFORMED)) {
+		*type = NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_OUTER;
+	} else if ((ip_ver == 6) && IP6CB(skb)->flags & IP6SKB_XFRM_TRANSFORMED) {
+		*type = NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_OUTER;
+	} else {
+		*type = NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_INNER;
+		BUG_ON(!secpath_exists(skb));
+	}
+
+	nss_ipsec_xfrm_trace("%p: Packet(%px) from ECM ip_ver %d type %d\n", drv, skb, ip_ver, *type);
+
+	return dev;
+}
+
+/*
+ * nss_ipsec_xfrm_sa_tuple2ecm_tuple()
+ * 	Converts nss_ipsecmgr_sa_tuple tuple to ecm_notifier_connection_tuple tuple.
+ */
+static inline void nss_ipsec_xfrm_sa2ecm_tuple(struct nss_ipsecmgr_sa_tuple *sa, struct ecm_notifier_connection_tuple *tuple)
+{
+	tuple->dst_port = sa->dport;
+	tuple->src_port = sa->sport;
+	tuple->ip_ver = sa->ip_version;
+	tuple->protocol = sa->proto_next_hdr;
+
+	if (sa->ip_version == IPVERSION) {
+		tuple->src.in.s_addr = sa->src_ip[0];
+		tuple->dest.in.s_addr = sa->dest_ip[0];
+		return;
+	}
+
+	BUG_ON(sa->ip_version != 6);
+
+	tuple->src.in6.s6_addr32[0] = sa->src_ip[0];
+	tuple->src.in6.s6_addr32[1] = sa->src_ip[1];
+	tuple->src.in6.s6_addr32[2] = sa->src_ip[2];
+	tuple->src.in6.s6_addr32[3] = sa->src_ip[3];
+
+	tuple->dest.in6.s6_addr32[0] = sa->dest_ip[0];
+	tuple->dest.in6.s6_addr32[1] = sa->dest_ip[1];
+	tuple->dest.in6.s6_addr32[2] = sa->dest_ip[2];
+	tuple->dest.in6.s6_addr32[3] = sa->dest_ip[3];
+}
+
+/*
+ * nss_ipsec_xfrm_ecm_conn2flow_tuple()
+ * 	Converts ecm_notifier_connection_data to nss_ipsecmgr_flow_tuple.
+ */
+static void nss_ipsec_xfrm_ecm_conn2tuple(struct ecm_notifier_connection_data *c, struct nss_ipsecmgr_flow_tuple *t,
+					bool is_return)
+{
+	struct in6_addr *sip6, *dip6;
+	struct in_addr *sip, *dip;
+
+	memset(t, 0, sizeof(*t));
+	t->ip_version = c->tuple.ip_ver;
+	t->proto_next_hdr = c->tuple.protocol;
+
+	if (is_return) {
+		sip = &c->tuple.dest.in;
+		dip = &c->tuple.src.in;
+		sip6 = &c->tuple.dest.in6;
+		dip6 = &c->tuple.src.in6;
+		t->sport = c->tuple.dst_port;
+		t->dport = c->tuple.src_port;
+	} else {
+		dip = &c->tuple.dest.in;
+		sip = &c->tuple.src.in;
+		dip6 = &c->tuple.dest.in6;
+		sip6 = &c->tuple.src.in6;
+		t->dport = c->tuple.dst_port;
+		t->sport = c->tuple.src_port;
+	}
+
+	if (t->ip_version == IPVERSION) {
+		t->dest_ip[0] = dip->s_addr;
+		t->src_ip[0] = sip->s_addr;
+		return;
+	}
+
+	BUG_ON(t->ip_version != 6);
+
+	t->dest_ip[0] = dip6->s6_addr32[0];
+	t->dest_ip[1] = dip6->s6_addr32[1];
+	t->dest_ip[2] = dip6->s6_addr32[2];
+	t->dest_ip[3] = dip6->s6_addr32[3];
+
+	t->src_ip[0] = sip6->s6_addr32[0];
+	t->src_ip[1] = sip6->s6_addr32[1];
+	t->src_ip[2] = sip6->s6_addr32[2];
+	t->src_ip[3] = sip6->s6_addr32[3];
+}
+
+
+/*
+ * nss_ipsec_xfrm_ecm_conn_notify()
+ *         Notifier function for ECM connection events.
+ */
+static int nss_ipsec_xfrm_ecm_conn_notify(struct notifier_block *nb, unsigned long event, void *ptr)
+{
+	struct ecm_notifier_connection_data *conn = ptr;
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+	struct nss_ipsecmgr_flow_tuple tuple = {0};
+	struct nss_ipsec_xfrm_flow *flow;
+	bool is_return = false;
+
+	nss_ipsec_xfrm_info("ECM connection event %ld\n", event);
+
+	/*
+	 * We only need to handle REMOVE events
+	 */
+	if (event != ECM_NOTIFIER_ACTION_CONNECTION_REMOVED) {
+		nss_ipsec_xfrm_trace("%px: Unhandled event\n", nb);
+		return NOTIFY_OK;
+	}
+
+	nss_ipsec_xfrm_trace("%px: Conn_tuple: ip_version %d Proto %d sport %d dport %d from_dev %s to_dev %s\n", nb,
+			conn->tuple.ip_ver, conn->tuple.protocol, conn->tuple.src_port, conn->tuple.dst_port,
+			conn->from_dev ? conn->from_dev->name : "", conn->to_dev ? conn->to_dev->name : "");
+	/*
+	 * Connection belongs to outer flow and it will be deleted
+	 * when parent SA gets deref.
+	 */
+	switch (conn->tuple.protocol) {
+	case IPPROTO_ESP:
+		nss_ipsec_xfrm_trace("%px: Connection protocol is ESP, no action required\n", nb);
+		return NOTIFY_OK;
+	case IPPROTO_UDP:
+		if (conn->tuple.src_port == NSS_IPSECMGR_NATT_PORT_DATA) {
+			return NOTIFY_OK;
+		}
+
+		if (conn->tuple.dst_port == NSS_IPSECMGR_NATT_PORT_DATA) {
+			return NOTIFY_OK;
+		}
+
+		break;
+	default:
+		break;
+	}
+
+	/*
+	 * Find the direction of the flow; it is possible that this flow is
+	 * not accelerated through the NSS
+	 */
+	is_return = !!nss_ipsec_xfrm_has_tun(drv, conn->from_dev);
+	if (!is_return && !nss_ipsec_xfrm_has_tun(drv, conn->to_dev)) {
+		return NOTIFY_OK;
+	}
+
+	nss_ipsec_xfrm_ecm_conn2tuple(conn, &tuple, is_return);
+
+	flow = nss_ipsec_xfrm_ref_flow(drv, &tuple);
+	if (!flow) {
+		nss_ipsec_xfrm_err("%p: Flow object doesn't exist for the provided tuple", nb);
+		return false;
+	}
+
+	nss_ipsec_xfrm_del_flow(drv, flow);
+	nss_ipsec_xfrm_flow_deref(flow);
+	return NOTIFY_OK;
+}
+
+#if defined(NSS_L2TPV2_ENABLED)
+/*
+ * nss_ipsec_xfrm_get_encap_ifnum()
+ *»       Get ipsec tunnel NSS inner interface number.
+ */
+static int32_t nss_ipsec_xfrm_get_inner_ifnum(uint32_t *src_ip, uint32_t *dest_ip)
+{
+
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+	struct nss_ipsec_xfrm_tunnel *tun;
+	xfrm_address_t remote = {0};
+	xfrm_address_t local = {0};
+	int32_t if_num;
+
+	nss_ipsec_xfrm_info("%p: src_ip %pI4 %pI4", drv, src_ip, dest_ip);
+	memcpy(&remote, dest_ip, 4);
+	memcpy(&local, src_ip, 4);
+
+	tun = nss_ipsec_xfrm_ref_tun(drv, &local, &remote, AF_INET);
+	if (!tun) {
+		nss_ipsec_xfrm_info("%p: No IPSec tunnel for the given SIP/DIP", drv);
+		return -1;
+	}
+
+	if_num = nss_cmn_get_interface_number_by_dev_and_type(tun->dev, NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_INNER);
+	nss_ipsec_xfrm_info("%p: Tunnel %s Inner ifnum %d", tun, tun->dev->name, if_num);
+
+	nss_ipsec_xfrm_tunnel_deref(tun);
+	return if_num;
+}
+#endif
+
+/*
+ * nss_ipsec_xfrm_state_acquire()
+ *	xfrm km acquire operation function. No-op for the plugin.
+ */
+static int nss_ipsec_xfrm_state_acquire(struct xfrm_state *x, struct xfrm_tmpl *t, struct xfrm_policy *xp)
+{
+	nss_ipsec_xfrm_info("%p: No-Op\n", x);
+	return -1;
+}
+
+/*
+ * nss_ipsec_xfrm_policy_compile()
+ *	xfrm km compile_policy operation function. No-op for the plugin.
+ */
+static struct xfrm_policy *nss_ipsec_xfrm_policy_compile(struct sock *sk, int opt, u8 *data, int len, int *dir)
+{
+	nss_ipsec_xfrm_info("No-Op\n");
+	return NULL;
+}
+
+/*
+ * nss_ipsec_xfrm_policy_notify()
+ *	xfrm km xfrm_policy database change notification function.
+ */
+static int nss_ipsec_xfrm_policy_notify(struct xfrm_policy *xp, int dir, const struct km_event *c)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	if (xp && (xp->type != XFRM_POLICY_TYPE_MAIN)) {
+		return 0;
+	}
+
+	nss_ipsec_xfrm_info("%p: XFRM event %d hard %d\n", xp, c->event, c->data.hard);
+
+	if (c->event == XFRM_MSG_FLUSHPOLICY) {
+		nss_ipsec_xfrm_flush_flow_all(drv);
+	}
+
+        return 0;
+}
+
+/*
+ * nss_ipsec_xfrm_state_notify()
+ *	xfrm km xfrm_state database change notification function.
+ */
+static int nss_ipsec_xfrm_state_notify(struct xfrm_state *x, const struct km_event *c)
+{
+	int refcnt = -1;
+
+	if (x) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		refcnt = atomic_read(&x->refcnt);
+#else
+		refcnt = refcount_read(&x->refcnt);
+#endif
+	}
+
+	nss_ipsec_xfrm_info("%p(%d): event %d hard %d\n", x, refcnt, c->event, c->data.hard);
+	return 0;
+}
+
+/*
+ * nss_ipsec_xfrm_offload_encap()
+ *	Sends an outbound packet to NSS for encapsulation and encryption.
+ */
+static int nss_ipsec_xfrm_offload_encap(struct nss_ipsec_xfrm_sa *sa, struct net *net, struct xfrm_state *x,
+					struct sk_buff *skb, uint16_t family)
+{
+	struct nss_ipsec_xfrm_tunnel *tun = sa->tun;
+	struct nss_ipsecmgr_flow_tuple tuple = {0};
+	struct nss_ipsec_xfrm_drv *drv = sa->drv;
+	struct nss_ipsec_xfrm_flow *flow = NULL;
+	struct net_device *dev = tun->dev;
+	nss_ipsecmgr_status_t status;
+	struct sk_buff *skb2;
+	int err = -EINVAL;
+
+	/*
+	 * Linearization is by-product of skb_copy_expand()
+	 */
+	skb2 = skb_copy_expand(skb, dev->needed_headroom, dev->needed_tailroom, GFP_ATOMIC);
+	if (!skb2) {
+		nss_ipsec_xfrm_err("%px: Failed to offload encap; copy_expand failed\n", skb);
+		XFRM_INC_STATS(net, LINUX_MIB_XFRMOUTERROR);
+		return -ENOMEM;
+	}
+
+	nss_ipsec_xfrm_flow_hdr2tuple(skb2, 0, &tuple);
+
+	/*
+	 * Check if ECM has pushed the rule. If present then push the inner flow rule.
+	 * Enable the IPsec inner flow once ECM has accelerated the outer routing
+	 * flow rule. This will limit the packet rate in encap direction till ECM
+	 * pushes the rule and should minimize the out-of-order issue when ECM
+	 * flow is not present.
+	 */
+	if (!atomic_read(&sa->ecm_accel_outer)) {
+		struct ecm_notifier_connection_tuple ecm_tuple = {0};
+		enum ecm_notifier_connection_state ecm_state;
+
+		nss_ipsec_xfrm_sa2ecm_tuple(&sa->tuple, &ecm_tuple);
+
+		ecm_state = ecm_notifier_connection_state_get(&ecm_tuple);
+		if (ecm_state != ECM_NOTIFIER_CONNECTION_STATE_ACCEL) {
+			goto done;
+		}
+
+		atomic_set(&sa->ecm_accel_outer, 1);
+		nss_ipsec_xfrm_trace("%px/%px: SA %p, Get ecm connection state(%u)\n", skb, skb2, sa, ecm_state);
+	}
+
+	flow = nss_ipsec_xfrm_ref_flow(drv, &tuple);
+	if (flow) {
+		nss_ipsec_xfrm_flow_update(flow, sa);
+		nss_ipsec_xfrm_flow_deref(flow);
+		goto done;
+	}
+
+	/*
+	 * Flow does not exist: Allocate and add a new flow
+	 */
+	flow = nss_ipsec_xfrm_flow_alloc(drv, &tuple, sa);
+	if (!flow) {
+		nss_ipsec_xfrm_err("%px/%px: Failed to allocate new flow object\n", skb, skb2);
+		dev_kfree_skb_any(skb2);
+		return -EINVAL;
+	}
+
+	nss_ipsec_xfrm_add_flow(drv, flow);
+
+done:
+	/*
+	 * Manually compute the checksum.
+	 */
+	if (!skb_is_gso(skb2) && (skb2->ip_summed == CHECKSUM_PARTIAL)) {
+		err = skb_checksum_help(skb2);
+		if (err) {
+			nss_ipsec_xfrm_err("%px/%px: Failed to offload encap; no csum\n", skb, skb2);
+			goto drop;
+		}
+	}
+
+	skb_scrub_packet(skb2, true);
+
+	status = nss_ipsecmgr_sa_tx_inner(sa->tun->dev, &sa->tuple, skb2);
+	if (status != NSS_IPSECMGR_OK) {
+		nss_ipsec_xfrm_err("%px: Failed to offload encap: unable to tx(%px) IPsec manager\n", sa, skb);
+		goto drop;
+	}
+
+	/*
+	 * Success; consume the original skb.
+	 */
+	consume_skb(skb);
+	return 0;
+drop:
+	XFRM_INC_STATS(net, LINUX_MIB_XFRMOUTERROR);
+	dev_kfree_skb_any(skb2);
+	return err;
+}
+
+/*
+ * nss_ipsec_xfrm_offload_decap()
+ *	Sends a inbound packet to NSS for decapsulation and decryption.
+ *	Returns 0 if the packet is queued to NSS.
+ */
+static bool nss_ipsec_xfrm_offload_decap(struct nss_ipsec_xfrm_sa *sa, struct net *net, struct xfrm_state *x,
+				struct sk_buff *skb, uint16_t family, bool natt)
+{
+	struct nss_ipsecmgr_flow_tuple tuple = {0};
+	struct nss_ipsec_xfrm_drv *drv = sa->drv;
+	struct nss_ipsec_xfrm_flow *flow = NULL;
+	nss_ipsecmgr_status_t status;
+	struct iphdr *iph = NULL;
+
+	/*
+	 * In case of ESP-over-UDP, xfrm4_udp_encap_rcv() reduces the iph total length
+	 * by size of the udp header. Undo the same.
+	 */
+	if (natt) {
+		iph = ip_hdr(skb);
+		iph->tot_len = htons(ntohs(iph->tot_len) + sizeof(struct udphdr));
+	}
+
+	/*
+	 * In case of Decap, skb->data points to ESP header or UDP header for NATT.
+	 * Set the skb->data to outer IP header.
+	 */
+	skb_push(skb, skb->data - skb_network_header(skb));
+
+	/*
+	 * Set the transport header
+	 */
+	if (family == AF_INET) {
+		skb_set_transport_header(skb, sizeof(struct iphdr));
+	} else {
+		skb_set_transport_header(skb, sizeof(struct ipv6hdr));
+	}
+
+	/*
+	 * If skb was cloned (likely due to a packet sniffer), Make a copy.
+	 * skb_cow() has check for skb_cloned().
+	 */
+	if (skb_cow(skb, skb_headroom(skb))) {
+		nss_ipsec_xfrm_err("%px: Failed to offload; create writable copy failed: Drop", skb);
+		XFRM_INC_STATS(net, LINUX_MIB_XFRMINERROR);
+		return false;
+	}
+
+	nss_ipsec_xfrm_flow_hdr2tuple(skb, natt, &tuple);
+
+	flow = nss_ipsec_xfrm_ref_flow(drv, &tuple);
+	if (flow) {
+		nss_ipsec_xfrm_flow_update(flow, sa);
+		nss_ipsec_xfrm_flow_deref(flow);
+		goto done;
+	}
+
+	/*
+	 * Flow does not exist: Allocate and add a new flow
+	 */
+	flow = nss_ipsec_xfrm_flow_alloc(drv, &tuple, sa);
+	if (!flow) {
+		nss_ipsec_xfrm_err("%px: Failed to allocate new flow object\n", skb);
+		return false;
+	}
+
+	nss_ipsec_xfrm_add_flow(drv, flow);
+
+done:
+	/*
+	 * We need to release all resources hold by SKB before sending it to NSS.
+	 * Reset the SKB and make it orphan.
+	 */
+	skb_scrub_packet(skb, true);
+
+	/*
+	 * Offload further processing to NSS.
+	 * Note: This can fail if the queue is full
+	 */
+	status = nss_ipsecmgr_sa_tx_outer(sa->tun->dev, &sa->tuple, skb);
+	if (status != NSS_IPSECMGR_OK) {
+		nss_ipsec_xfrm_err("%px: Failed to offload; IPsec manager tx_outer failed\n", sa);
+		XFRM_INC_STATS(net, LINUX_MIB_XFRMINERROR);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_ipsec_xfrm_esp_rcv()
+ * 	Handle a recieved ESP packet.
+ */
+static int nss_ipsec_xfrm_esp_rcv(struct nss_ipsec_xfrm_drv *drv, struct sk_buff *skb, xfrm_address_t *daddr,
+				unsigned int family, bool natt)
+{
+	struct net *net = dev_net(skb->dev);
+	struct nss_ipsec_xfrm_sa *sa = NULL;
+	struct xfrm_state *x;
+	 __be32 seq = 0;
+	 __be32 spi;
+	int err;
+
+	err = xfrm_parse_spi(skb, IPPROTO_ESP, &spi, &seq);
+	if (err) {
+		nss_ipsec_xfrm_err("%px: Failed to handle esp packet; Cannot parse esp hdr: Drop\n", skb);
+		XFRM_INC_STATS(net, LINUX_MIB_XFRMINHDRERROR);
+		goto drop;
+	}
+
+	/*
+	 * If, XFRM state is found then we will proceed with the receive processing of the packet
+	 */
+	x = xfrm_state_lookup(net, skb->mark, daddr, spi, IPPROTO_ESP, family);
+	if (!x) {
+		nss_ipsec_xfrm_err("%px: Failed to handle esp packet; xfrm_state lookup failed: Drop\n", skb);
+		XFRM_INC_STATS(net, LINUX_MIB_XFRMINNOSTATES);
+		goto drop;
+	}
+
+	/*
+	 * Check if the XFRM state is mapped for offload; if not then drop.
+	 * Otherwise, consume the packet for decapsulation
+	 */
+	sa = nss_ipsec_xfrm_sa_ref_by_state(x);
+	if (!sa) {
+		nss_ipsec_xfrm_trace("%px: xfrm_state is not managed by NSS; Drop\n", skb);
+		xfrm_state_put(x);
+		XFRM_INC_STATS(net, LINUX_MIB_XFRMINSTATEINVALID);
+		goto drop;
+	}
+
+	nss_ipsec_xfrm_trace("%p: Inbound packet(%px) for xfrm_state=%p\n", sa, skb, x);
+
+	if (!nss_ipsec_xfrm_offload_decap(sa, net, x, skb, family, natt)) {
+		nss_ipsec_xfrm_err("%p: Failed to decap ESP packet(%px); xfrm_state=%p\n", sa, skb, x);
+		nss_ipsec_xfrm_sa_deref(sa);
+		xfrm_state_put(x);
+		goto drop;
+	}
+
+	nss_ipsec_xfrm_sa_deref(sa);
+	xfrm_state_put(x);
+
+	atomic64_inc(&drv->stats.decap_nss);
+	return 0;
+drop:
+	atomic64_inc(&drv->stats.decap_drop);
+	dev_kfree_skb_any(skb);
+	return 0;
+}
+
+/*
+ * nss_ipsec_xfrm_encap_v4()
+ *	This is called for IPv4 pakcets that are to be transformed.
+ */
+static int nss_ipsec_xfrm_encap_v4(struct net *net, struct sock *sk, struct sk_buff *skb)
+{
+	struct xfrm_state *x = skb_dst(skb)->xfrm;
+	struct nss_ipsec_xfrm_sa *sa;
+	int ret = 0;
+
+#if defined CONFIG_NETFILTER
+	if (!x) {
+		IPCB(skb)->flags |= IPSKB_REROUTED;
+		return dst_output(net, sk, skb);
+	}
+#endif
+	/*
+	 * This skb is going to NSS, hold an additional ref to xfrm_state
+	 */
+	xfrm_state_hold(x);
+
+	/*
+	 * This was already checked in nss_ipsec_xfrm_v6_encap()
+	 */
+	sa = nss_ipsec_xfrm_sa_ref_by_state(x);
+	BUG_ON(!sa);
+
+	ret = nss_ipsec_xfrm_offload_encap(sa, net, x, skb, AF_INET);
+	if (ret < 0) {
+		atomic64_inc(&sa->drv->stats.encap_drop);
+		nss_ipsec_xfrm_sa_deref(sa);
+		xfrm_state_put(x);
+		dev_kfree_skb_any(skb);
+		return ret;
+	}
+
+	atomic64_inc(&sa->drv->stats.encap_nss);
+	nss_ipsec_xfrm_sa_deref(sa);
+	xfrm_state_put(x);
+	return 0;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+/*
+ * nss_ipsec_xfrm_v4_init_flags()
+ *	Initialize xfrm state flags
+ */
+static int nss_ipsec_xfrm_v4_init_flags(struct xfrm_state *x)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", x);
+	return drv->xsa.v4->init_flags(x);
+}
+
+/*
+ * nss_ipsec_xfrm_v4_init_sel()
+ *	Initialize xfrm state selector
+ */
+static void nss_ipsec_xfrm_v4_init_sel(struct xfrm_selector *sel, const struct flowi *fl)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", sel);
+	return drv->xsa.v4->init_tempsel(sel, fl);
+}
+
+/*
+ * nss_ipsec_xfrm_v4_init_param()
+ *	Initialize xfrm state parameters
+ */
+static void nss_ipsec_xfrm_v4_init_param(struct xfrm_state *x, const struct xfrm_tmpl *tmpl,
+		const xfrm_address_t *daddr, const xfrm_address_t *saddr)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", x);
+	return drv->xsa.v4->init_temprop(x, tmpl, daddr, saddr);
+}
+
+/*
+ * nss_ipsec_xfrm_v6_init_sel()
+ *	Initialize xfrm state selector
+ */
+static void nss_ipsec_xfrm_v6_init_sel(struct xfrm_selector *sel, const struct flowi *fl)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", sel);
+	return drv->xsa.v6->init_tempsel(sel, fl);
+}
+
+/*
+ * nss_ipsec_xfrm_v6_init_param()
+ *	Initialize xfrm state parameters
+ */
+static void nss_ipsec_xfrm_v6_init_param(struct xfrm_state *x, const struct xfrm_tmpl *tmpl,
+		const xfrm_address_t *daddr, const xfrm_address_t *saddr)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", x);
+	return drv->xsa.v6->init_temprop(x, tmpl, daddr, saddr);
+}
+
+/*
+ * nss_ipsec_xfrm_v6_sort_tmpl()
+ *	Distribution couting sort for xfrm state template
+ */
+static int nss_ipsec_xfrm_v6_sort_tmpl(struct xfrm_tmpl **dst, struct xfrm_tmpl **src, int n)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", dst);
+	return drv->xsa.v6->tmpl_sort(dst, src, n);
+}
+
+/*
+ * nss_ipsec_xfrm_v6_sort_state()
+ *	Distribution couting sort for xfrm state
+ */
+static int nss_ipsec_xfrm_v6_sort_state(struct xfrm_state **dst, struct xfrm_state **src, int n)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", dst);
+	return drv->xsa.v6->state_sort(dst, src, n);
+}
+#endif
+
+/*
+ * nss_ipsec_xfrm_v4_output()
+ *	Called for IPv4 Plain text packets submitted for IPSec transformation.
+ */
+static int nss_ipsec_xfrm_v4_output(struct net *net, struct sock *sk, struct sk_buff *skb)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+	struct xfrm_state *x = skb_dst(skb)->xfrm;
+	struct nss_ipsec_xfrm_sa *sa = NULL;
+	struct nss_ipsec_xfrm_tunnel *tun;
+	int ret = 0;
+
+	/*
+	 * No xfrm_state associated; Drop
+	 */
+	if (!x) {
+		nss_ipsec_xfrm_warn("%px: Failed to offload; No xfrm_state associated: drop\n", skb);
+		XFRM_INC_STATS(net, LINUX_MIB_XFRMOUTNOSTATES);
+		goto drop;
+	}
+
+	sa = nss_ipsec_xfrm_sa_ref_by_state(x);
+	if (!sa) {
+		nss_ipsec_xfrm_warn("%px: Failed to offload; xfrm_state %p, Flow not offloaded: drop\n", skb, x);
+		XFRM_INC_STATS(net, LINUX_MIB_XFRMOUTSTATEINVALID);
+		goto drop;
+	}
+
+	tun = sa->tun;
+	BUG_ON(!tun);
+
+	/*
+	 * No falling back now. xfrm_state is offloaded to NSS.
+	 */
+	nss_ipsec_xfrm_trace("%px: Outbound packet trapped for encap; xfrm_state %p SA %p\n", skb, x, sa);
+
+	/*
+	 * Call the Post routing hooks.
+	 */
+	ret = NF_HOOK_COND(NFPROTO_IPV4, NF_INET_POST_ROUTING, net, sk, skb, NULL, skb_dst(skb)->dev,
+			nss_ipsec_xfrm_encap_v4, !(IPCB(skb)->flags & IPSKB_REROUTED));
+
+	nss_ipsec_xfrm_sa_deref(sa);
+	return ret;
+
+drop:
+	atomic64_inc(&drv->stats.encap_drop);
+	dev_kfree_skb_any(skb);
+	return -EINVAL;
+}
+
+/*
+ * nss_ipsec_xfrm_v4_output_finish()
+ *	This is called for non-offloaded transformations after the NF_POST routing hooks
+ *	for packets that are to-be transformed with an outer IPv4 header.
+ *	Redirect to the native function.
+ */
+static int nss_ipsec_xfrm_v4_output_finish(struct sock *sk, struct sk_buff *skb)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb);
+	return drv->xsa.v4->output_finish(sk, skb);
+}
+
+/*
+ * nss_ipsec_xfrm_v4_extract_input()
+ *	This is called for non-offloaded transformations, for an inbound transformed packet to
+ *	extract the outer IPv4 header. Redirect to the native function.
+ */
+static int nss_ipsec_xfrm_v4_extract_input(struct xfrm_state *x, struct sk_buff *skb)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb);
+	return drv->xsa.v4->extract_input(x, skb);
+}
+
+/*
+ * nss_ipsec_xfrm_v4_extract_output()
+ *	This is called for non-offloaded transformations, for an outbound to-be
+ *	transformed packet for extracting the inner IPv4 header.
+ *	Redirect to the native function.
+ */
+static int nss_ipsec_xfrm_v4_extract_output(struct xfrm_state *x, struct sk_buff *skb)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb);
+	return drv->xsa.v4->extract_output(x, skb);
+}
+
+/*
+ * nss_ipsec_xfrm_v4_transport_finish()
+ * 	This is called for non-offloaded transformations, for transport mode packets decapsulated
+ * 	with an inner IPv4 header. Redirect to native function
+ */
+static int nss_ipsec_xfrm_v4_transport_finish(struct sk_buff *skb, int async)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb);
+	return drv->xsa.v4->transport_finish(skb, async);
+}
+
+/*
+ * nss_ipsec_xfrm_v4_local_error()
+ * 	This is called for non-offloaded transformations to generate local pmtu errors.
+ * 	Redirect to native function
+ */
+void nss_ipsec_xfrm_v4_local_error(struct sk_buff *skb, u32 mtu)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb);
+	drv->xsa.v4->local_error(skb, mtu);
+
+}
+
+/*
+ * nss_ipsec_xfrm_esp_get_mtu()
+ * 	Get mtu for inner packet.
+ */
+uint32_t nss_ipsec_xfrm_esp_get_mtu(struct xfrm_state *x, int mtu)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+	uint32_t (*fallback_fn)(struct xfrm_state *, int);
+	struct nss_ipsec_xfrm_sa *sa;
+	size_t ip_len;
+
+	if (x->props.family == AF_INET) {
+		ip_len = sizeof(struct iphdr);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		fallback_fn = drv->xsa.v4->type_map[IPPROTO_ESP]->get_mtu;
+#else
+		fallback_fn = drv->xsa.v4->type_esp->get_mtu;
+#endif
+	} else {
+		ip_len = sizeof(struct ipv6hdr);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		fallback_fn = drv->xsa.v6->type_map[IPPROTO_ESP]->get_mtu;
+#else
+		fallback_fn = drv->xsa.v6->type_esp->get_mtu;
+#endif
+	}
+
+	/*
+	 * We are not managing this xfrm_state
+	 * Fallback
+	 */
+	sa = nss_ipsec_xfrm_sa_ref_by_state(x);
+	if (!sa) {
+		nss_ipsec_xfrm_info("%p: xfrm_state is not owned by NSS: Fallback\n", x);
+		goto fallback;
+	}
+
+	/*
+	 * We don't need ip_len for tunnel mode to compute the effective MTU
+	 */
+	if (x->props.mode != XFRM_MODE_TRANSPORT) {
+		ip_len = 0;
+	}
+
+	mtu -= sa->sa_info.hdr_len;
+	mtu -= sa->sa_info.hash_len;
+	mtu -= ip_len;
+
+	mtu = round_down(mtu, sa->sa_info.blk_len);
+	mtu += ip_len;
+	mtu -= 2; /* Trailer length is fixed to 2 bytes */
+
+	nss_ipsec_xfrm_sa_deref(sa);
+
+	nss_ipsec_xfrm_trace("mtu %d", mtu);
+	return mtu;
+
+fallback:
+	if (fallback_fn) {
+		return fallback_fn(x, mtu);
+	}
+
+	nss_ipsec_xfrm_err("%p: Fallback failed", x);
+	return mtu;
+}
+
+/*
+ * nss_ipsec_xfrm_esp_init_state()
+ * 	Initialize IPsec xfrm state of type ESP.
+ */
+static int nss_ipsec_xfrm_esp_init_state(struct xfrm_state *x)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+	struct nss_ipsec_xfrm_tunnel *tun = NULL;
+	struct nss_ipsec_xfrm_sa *sa = NULL;
+	xfrm_address_t remote = {0};
+	xfrm_address_t local = {0};
+	struct net_device *local_dev;
+	bool new_tun = 0;
+	size_t ip_addr_len;
+
+	if (x->props.family == AF_INET) {
+		local_dev = ip_dev_find(&init_net, x->id.daddr.a4);
+		ip_addr_len = sizeof(local.a4);
+	} else {
+		local_dev = ipv6_dev_find(&init_net, &x->id.daddr.in6, 1);
+		ip_addr_len = sizeof(local.a6);
+	}
+
+	/*
+	 * Local device is found for the decapsulation direction;
+	 * Since, we store the tunnel object using the encap direction
+	 * we have to swap the address before the tunnel allocation
+	 */
+	if (local_dev) {
+		memcpy(&local, &x->id.daddr, ip_addr_len);
+		memcpy(&remote, &x->props.saddr, ip_addr_len);
+		dev_put(local_dev);
+	} else {
+		memcpy(&local, &x->props.saddr, ip_addr_len);
+		memcpy(&remote, &x->id.daddr, ip_addr_len);
+	}
+
+	sa = nss_ipsec_xfrm_sa_ref_by_state(x);
+	if (sa) {
+		nss_ipsec_xfrm_warn("%p: xfrm_state is already offloaded %p\n", sa, x);
+		nss_ipsec_xfrm_sa_deref(sa);
+		WARN_ON(1);
+		return -EEXIST;
+	}
+
+	if (!nss_ipsec_xfrm_verify_offload(x)) {
+		nss_ipsec_xfrm_warn("%p: XFRM state offloaded is not allowed\n", x);
+		return -ENOTSUPP;
+
+	}
+
+	tun = nss_ipsec_xfrm_ref_tun(drv, &local, &remote, x->props.family);
+	if (!tun) {
+		nss_ipsec_xfrm_info("%p: Tunnel doesn't exist for this xfrm_state; create one\n", x);
+
+		/*
+		 * We are having the rtnl_lock here(). Hence, we can do the below
+		 * without worying about locking, as there is no parallel entity
+		 * that could create a tunnel.
+		 */
+		tun = nss_ipsec_xfrm_tunnel_alloc(drv, &local, &remote, x->props.family);
+		if (!tun) {
+			nss_ipsec_xfrm_err("%p: Failed to offload xfrm_state; Tunnel alloc failed: Fail\n", x);
+			return -EINVAL;
+		}
+
+		new_tun = true;
+		nss_ipsec_xfrm_tunnel_ref(tun);
+	}
+
+	/*
+	 * Allocate the new SA for the corresponding the XFRM state
+	 * Note: We store the SA inside the XFRM state and it holds a
+	 * reference to our SA object
+	 */
+	sa = nss_ipsec_xfrm_sa_alloc(tun, x);
+	if (!sa) {
+		nss_ipsec_xfrm_err("%p: Failed to offload xfrm_state; SA alloc failed: Fail\n", x);
+		goto error;
+	}
+
+	if (new_tun) {
+		nss_ipsec_xfrm_add_tun(drv, tun);
+	}
+
+	atomic_inc(&tun->num_sa);
+	nss_ipsec_xfrm_tunnel_deref(tun);
+	return 0;
+
+error:
+	if (new_tun) {
+		nss_ipsec_xfrm_tunnel_dealloc(tun);
+	}
+
+	nss_ipsec_xfrm_tunnel_deref(tun);
+	return -EINVAL;
+}
+
+/*
+ * nss_ipsec_xfrm_esp_deinit_state()
+ * 	Destroy IPsec xfrm state of type ESP.
+ */
+static void nss_ipsec_xfrm_esp_deinit_state(struct xfrm_state *x)
+{
+	nss_ipsec_xfrm_trace("%p: xfrm_state destroyed\n", x);
+	nss_ipsec_xfrm_sa_deinit(x);
+	return;
+}
+
+/*
+ * nss_ipsec_xfrm_esp_input()
+ * 	Invoked by stack to handover the packet for decryption.
+ * 	This should not be called for NSS managed ESP xfrm_states.
+ * 	Redirect to the native version.
+ */
+static int nss_ipsec_xfrm_esp_input(struct xfrm_state *x, struct sk_buff *skb)
+{
+	int (*fallback_fn)(struct xfrm_state *, struct sk_buff *);
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	if (x->props.family == AF_INET) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		fallback_fn = drv->xsa.v4->type_map[IPPROTO_ESP]->input;
+#else
+		fallback_fn = drv->xsa.v4->type_esp->input;
+#endif
+	} else {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		fallback_fn = drv->xsa.v6->type_map[IPPROTO_ESP]->input;
+#else
+		fallback_fn = drv->xsa.v6->type_esp->input;
+#endif
+	}
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native stack\n", skb);
+	return fallback_fn(x, skb);
+}
+
+/*
+ * nss_ipsec_xfrm_esp_output()
+ * 	Invoked by stack to handover the packet for encryption,
+ * 	after it has ben encapsulated.
+ * 	This should not be called for NSS managed ESP xfrm_states.
+ * 	Redirect to the native version.
+ */
+static int nss_ipsec_xfrm_esp_output(struct xfrm_state *x, struct sk_buff *skb)
+{
+	int (*fallback_fn)(struct xfrm_state *, struct sk_buff *);
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	if (x->props.family == AF_INET) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		fallback_fn = drv->xsa.v4->type_map[IPPROTO_ESP]->output;
+#else
+		fallback_fn = drv->xsa.v4->type_esp->output;
+#endif
+	} else {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		fallback_fn = drv->xsa.v6->type_map[IPPROTO_ESP]->output;
+#else
+		fallback_fn = drv->xsa.v6->type_esp->output;
+#endif
+	}
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native stack\n", skb);
+	return fallback_fn(x, skb);
+}
+
+/*
+ * nss_ipsec_xfrm_esp4_rcv()
+ * 	Handle a received IPv4 ESP received packet.
+ */
+static int nss_ipsec_xfrm_esp4_rcv(struct sk_buff *skb)
+{
+	struct iphdr *iph = (struct iphdr *)skb_network_header(skb);
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	return nss_ipsec_xfrm_esp_rcv(drv, skb, (xfrm_address_t *)&iph->daddr, AF_INET, false);
+}
+
+/*
+ * nss_ipsec_xfrm_udp_rcv()
+ * 	Handle a received IPv4 ESPinUDP received packet.
+ */
+static int nss_ipsec_xfrm_udp_rcv(struct sk_buff *skb, int nexthdr, __be32 spi, int encap_type)
+{
+	struct iphdr *iph = (struct iphdr *)skb_network_header(skb);
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	return nss_ipsec_xfrm_esp_rcv(drv, skb, (xfrm_address_t *)&iph->daddr, AF_INET, true);
+}
+
+/*
+ * nss_ipsec_xfrm_esp4_rcv_err()
+ * 	Invoked after an ESP packet has been decrypted.
+ * 	This should not be called for NSS managed ESP xfrm_states.
+ * 	Redirect to the native handler.
+ */
+static int nss_ipsec_xfrm_esp4_rcv_err(struct sk_buff *skb, int err)
+{
+	nss_ipsec_xfrm_trace("%px: Redirect to Native ESP handler\n", skb);
+	return 1;
+}
+
+/*
+ * nss_ipsec_xfrm_esp4_err()
+ * 	Invoked for a received ICMP error for ESP.
+ */
+static int nss_ipsec_xfrm_esp4_err(struct sk_buff *skb, u32 info)
+{
+	struct net *net = dev_net(skb->dev);
+	struct nss_ipsec_xfrm_sa *sa;
+	struct ip_esp_hdr *esph;
+	struct xfrm_state *x;
+	struct iphdr *iph;
+
+	nss_ipsec_xfrm_trace("%px:\n", skb);
+
+	iph = (struct iphdr *)skb->data;
+	esph = (struct ip_esp_hdr *) ((uint8_t *)iph + sizeof(*iph));
+
+	x = xfrm_state_lookup(net, skb->mark, (xfrm_address_t *)&iph->daddr, esph->spi, IPPROTO_ESP, AF_INET);
+	if (!x) {
+		nss_ipsec_xfrm_err("%px: xfrm_lookup failed: Done\n", skb);
+		return 0;
+	}
+
+	sa = nss_ipsec_xfrm_sa_ref_by_state(x);
+	if (!sa) {
+		nss_ipsec_xfrm_trace("%px: xfrm_state %p is not owned by NSS: Fallback\n", skb, x);
+		xfrm_state_put(x);
+		return -EINVAL;
+	}
+
+	nss_ipsec_xfrm_sa_deref(sa);
+
+	switch (icmp_hdr(skb)->type) {
+	case ICMP_DEST_UNREACH:
+		if (icmp_hdr(skb)->code != ICMP_FRAG_NEEDED) {
+			xfrm_state_put(x);
+			return 0;
+		}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		ipv4_update_pmtu(skb, net, info, 0, 0, IPPROTO_ESP, 0);
+#else
+		ipv4_update_pmtu(skb, net, info, 0, IPPROTO_ESP);
+#endif
+		break;
+
+	case ICMP_REDIRECT:
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		ipv4_redirect(skb, net, 0, 0, IPPROTO_ESP, 0);
+#else
+		ipv4_redirect(skb, net, 0, IPPROTO_ESP);
+#endif
+		break;
+
+	default:
+		xfrm_state_put(x);
+		return 0;
+	}
+
+	xfrm_state_put(x);
+	return 0;
+}
+
+/*
+ * nss_ipsec_xfrm_encap_v6()
+ *	This is called for IPv6 pakcets that are to be transformed.
+ */
+static int nss_ipsec_xfrm_encap_v6(struct net *net, struct sock *sk, struct sk_buff *skb)
+{
+	struct xfrm_state *x = skb_dst(skb)->xfrm;
+	struct nss_ipsec_xfrm_sa *sa;
+	int ret = 0;
+
+#if defined CONFIG_NETFILTER
+	if (!x) {
+		IP6CB(skb)->flags |= IP6SKB_REROUTED;
+		return dst_output(net, sk, skb);
+	}
+#endif
+	/*
+	 * This skb is going to NSS, hold an additional ref to xfrm_state
+	 */
+	xfrm_state_hold(x);
+
+	/*
+	 * This was already checked in nss_ipsec_xfrm_encap_v4()
+	 */
+	sa = nss_ipsec_xfrm_sa_ref_by_state(x);
+	BUG_ON(!sa);
+
+	ret = nss_ipsec_xfrm_offload_encap(sa, net, x, skb, AF_INET6);
+	if (ret < 0) {
+		atomic64_inc(&sa->drv->stats.encap_drop);
+		nss_ipsec_xfrm_sa_deref(sa);
+		xfrm_state_put(x);
+		dev_kfree_skb_any(skb);
+		return ret;
+	}
+
+	atomic64_inc(&sa->drv->stats.encap_nss);
+	nss_ipsec_xfrm_sa_deref(sa);
+	xfrm_state_put(x);
+	return 0;
+}
+
+/*
+ * nss_ipsec_xfrm_v6_output()
+ *	Called for IPv6 Plain text packets submitted for IPSec transformation.
+ */
+static int nss_ipsec_xfrm_v6_output(struct net *net, struct sock *sk, struct sk_buff *skb)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+	struct xfrm_state *x = skb_dst(skb)->xfrm;
+	struct nss_ipsec_xfrm_sa *sa = NULL;
+	struct nss_ipsec_xfrm_tunnel *tun;
+	int ret = 0;
+
+	/*
+	 * No xfrm_state associated; Drop
+	 */
+	if (!x) {
+		nss_ipsec_xfrm_warn("%px: Failed to offload; No xfrm_state associated: drop\n", skb);
+		XFRM_INC_STATS(net, LINUX_MIB_XFRMOUTNOSTATES);
+		goto drop;
+	}
+
+	sa = nss_ipsec_xfrm_sa_ref_by_state(x);
+	if (!sa) {
+		nss_ipsec_xfrm_warn("%px: Failed to offload; xfrm_state %p, Flow not offloaded: drop\n", skb, x);
+		XFRM_INC_STATS(net, LINUX_MIB_XFRMOUTSTATEINVALID);
+		goto drop;
+	}
+
+	tun = sa->tun;
+	BUG_ON(!tun);
+
+	/*
+	 * No falling back now. xfrm_state is offloaded to NSS.
+	 */
+	nss_ipsec_xfrm_trace("%px: Outbound packet trapped for encap; xfrm_state %p SA %p\n", skb, x, sa);
+
+	/*
+	 * Call the Post routing hooks.
+	 */
+	ret = NF_HOOK_COND(NFPROTO_IPV6, NF_INET_POST_ROUTING, net, sk, skb, NULL, skb_dst(skb)->dev,
+			nss_ipsec_xfrm_encap_v6, !(IP6CB(skb)->flags & IP6SKB_REROUTED));
+
+	nss_ipsec_xfrm_sa_deref(sa);
+	return ret;
+
+drop:
+	atomic64_inc(&drv->stats.encap_drop);
+	dev_kfree_skb_any(skb);
+	return -EINVAL;
+}
+
+/*
+ * nss_ipsec_xfrm_v6_output_finish()
+ *	This is called for non-offloaded transformations after the NF_POST routing hooks
+ *	for packets that are to-be transformed with an outer IPv6 header.
+ *	Redirect to the native function.
+ */
+static int nss_ipsec_xfrm_v6_output_finish(struct sock *sk, struct sk_buff *skb)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb);
+	return drv->xsa.v6->output_finish(sk, skb);
+}
+
+/*
+ * nss_ipsec_xfrm_v6_extract_input()
+ *	This is called for non-offloaded transformations, for an inbound transformed packet to
+ *	extract the outer IPv6 header. Redirect to the native function.
+ */
+static int nss_ipsec_xfrm_v6_extract_input(struct xfrm_state *x, struct sk_buff *skb)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb);
+	return drv->xsa.v6->extract_input(x, skb);
+}
+
+/*
+ * nss_ipsec_xfrm_v6_extract_output()
+ *	This is called for non-offloaded transformations, for an outbound to-be
+ *	transformed packet for extracting the inner IPv6 header.
+ *	Redirect to the native function.
+ */
+static int nss_ipsec_xfrm_v6_extract_output(struct xfrm_state *x, struct sk_buff *skb)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb);
+	return drv->xsa.v6->extract_output(x, skb);
+}
+
+/*
+ * nss_ipsec_xfrm_v6_transport_finish()
+ * 	This is called for non-offloaded transformations, for transport mode packets decapsulated
+ * 	with an inner IPv6 header. Redirect to native function
+ */
+static int nss_ipsec_xfrm_v6_transport_finish(struct sk_buff *skb, int async)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb);
+	return drv->xsa.v6->transport_finish(skb, async);
+}
+
+/*
+ * nss_ipsec_xfrm_v6_local_error()
+ * 	This is called for non-offloaded transformations to generate local pmtu errors.
+ * 	Redirect to native function
+ */
+void nss_ipsec_xfrm_v6_local_error(struct sk_buff *skb, u32 mtu)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native xfrm stack\n", skb);
+	return drv->xsa.v6->local_error(skb, mtu);
+}
+
+/*
+ * nss_ipsec_xfrm_v6_esp_hdr_offset()
+ * 	Invoked by stack for IPv6 transport mode in encap.
+ * 	Redirect to the native version.
+ */
+static  int nss_ipsec_xfrm_v6_esp_hdr_offset(struct xfrm_state *x, struct sk_buff *skb, u8 **prevhdr)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	nss_ipsec_xfrm_trace("%px: Redirect to native esp6 stack\n", skb);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	return drv->xsa.v6->type_map[IPPROTO_ESP]->hdr_offset(x, skb, prevhdr);
+#else
+	return drv->xsa.v6->type_esp->hdr_offset(x, skb, prevhdr);
+#endif
+}
+
+/*
+ * nss_ipsec_xfrm_esp6_rcv()
+ * 	Handle a received IPv6 ESP received packet.
+ */
+static int nss_ipsec_xfrm_esp6_rcv(struct sk_buff *skb)
+{
+	struct ipv6hdr *ip6h = (struct ipv6hdr *)skb_network_header(skb);
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+
+	return nss_ipsec_xfrm_esp_rcv(drv, skb, (xfrm_address_t *)&ip6h->daddr, AF_INET6, false);
+}
+
+/*
+ * nss_ipsec_xfrm_esp6_rcv_err()
+ * 	Invoked after an ESP packet has been decrypted.
+ * 	This should not be called for NSS managed ESP xfrm_states.
+ * 	Redirect to the native handler.
+ */
+static int nss_ipsec_xfrm_esp6_rcv_err(struct sk_buff *skb, int err)
+{
+	nss_ipsec_xfrm_trace("%px: Redirect to Native ESP handler; err(%d)\n", skb, err);
+	return 1;
+}
+
+/*
+ * nss_ipsec_xfrm_esp6_err()
+ * 	Invoked for a received ICMP error for ESP.
+ */
+static int nss_ipsec_xfrm_esp6_err(struct sk_buff *skb, struct inet6_skb_parm *opt, u8 type, u8 code, int offset,
+					__be32 info)
+{
+	const struct ipv6hdr *iph = (const struct ipv6hdr *)skb->data;
+	struct ip_esp_hdr *esph = (struct ip_esp_hdr *)(skb->data + offset);
+	struct net *net = dev_net(skb->dev);
+	struct nss_ipsec_xfrm_sa *sa;
+	struct xfrm_state *x;
+
+	nss_ipsec_xfrm_trace("%px:\n", skb);
+
+	if (type != ICMPV6_PKT_TOOBIG && type != NDISC_REDIRECT) {
+		return 0;
+	}
+
+	x = xfrm_state_lookup(net, skb->mark, (const xfrm_address_t *)&iph->daddr, esph->spi, IPPROTO_ESP, AF_INET6);
+	if (!x) {
+		nss_ipsec_xfrm_err("%px: xfrm_lookup failed: Done\n", skb);
+		return 0;
+	}
+
+	sa = nss_ipsec_xfrm_sa_ref_by_state(x);
+	if (!sa) {
+		nss_ipsec_xfrm_trace("%px: xfrm_state %p is not owned by NSS: Fallback\n", skb, x);
+		xfrm_state_put(x);
+		return -EINVAL;
+	}
+
+	if (type == NDISC_REDIRECT) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		ip6_redirect(skb, net, skb->dev->ifindex, 0);
+#else
+		ip6_redirect(skb, net, skb->dev->ifindex, 0, sock_net_uid(net, NULL));
+#endif
+	} else {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		ip6_update_pmtu(skb, net, info, 0, 0);
+#else
+		ip6_update_pmtu(skb, net, info, 0, 0, sock_net_uid(net, NULL));
+#endif
+	}
+
+	nss_ipsec_xfrm_sa_deref(sa);
+	xfrm_state_put(x);
+	return 0;
+}
+
+/*
+ * nss_ipsec_xfrm_update_stats()
+ *	Update statistics to XFRM stack
+ */
+void nss_ipsec_xfrm_update_stats(struct nss_ipsec_xfrm_drv *drv, struct nss_ipsecmgr_sa_stats *stats)
+{
+	uint16_t family = AF_INET;
+	struct xfrm_state *x;
+
+	if (stats->sa.ip_version == 6) {
+		family = AF_INET6;
+	}
+
+	/*
+	 * Lookup XFRM state by SPI index
+	 */
+	x = xfrm_state_lookup_byspi(&init_net, htonl(stats->sa.spi_index), family);
+	if (!x) {
+		return;
+	}
+
+	spin_lock(&x->lock);
+	x->curlft.packets += stats->pkt_count;
+	x->curlft.bytes += stats->pkt_bytes;
+	x->stats.replay_window += stats->fail_replay_win;
+	x->stats.replay += stats->fail_replay_dup;
+	x->stats.integrity_failed += stats->fail_auth;
+
+	/*
+	 * XXX: Do we need to do anything for overflow of curlft.packets
+	 * and curlft.bytes ?
+	 */
+	xfrm_state_check_expire(x);
+	spin_unlock(&x->lock);
+
+	xfrm_state_put(x);
+}
+
+/*
+ * nss_ipsec_xfrm_state_delete()
+ *	xfrm_state delete notification handler. Deallocate the associated NSS SA.
+ */
+static void nss_ipsec_xfrm_state_delete(struct xfrm_state *x)
+{
+	struct nss_ipsec_xfrm_drv *drv = &g_ipsec_xfrm;
+	struct nss_ipsec_xfrm_tunnel *tun;
+	struct nss_ipsec_xfrm_sa *sa;
+
+	/*
+	 * If we are not managing this xfrm_state, then return
+	 */
+	sa = nss_ipsec_xfrm_sa_ref_by_state(x);
+	if (!sa) {
+		nss_ipsec_xfrm_info("%p: xfrm_state is not owned by NSS: return\n", x);
+		return;
+	}
+
+	tun = sa->tun;
+
+	/*
+	 * First delete any other objects that could be holding reference to the SA object.
+	 * We delete all the flows mapped to this SA.
+	 */
+	nss_ipsec_xfrm_flush_flow_by_sa(drv, sa);
+	nss_ipsec_xfrm_sa_dealloc(sa, x);
+	nss_ipsec_xfrm_sa_deref(sa);
+
+	/*
+	 * We need to release the tunnel when all SA(s) associated with are gone
+	 */
+	if (atomic_dec_and_test(&tun->num_sa)) {
+		nss_ipsec_xfrm_del_tun(drv, tun);
+	}
+
+	return;
+}
+
+/*
+ * nss_ipsec_xfrm_state_event_notify()
+ *	xfrm_state change notification handler.
+ */
+void nss_ipsec_xfrm_state_event_notify(struct xfrm_state *x, enum xfrm_event_type event)
+{
+	nss_ipsec_xfrm_info("%p: xfrm state change event %d\n", x, event);
+
+	switch (event) {
+		case XFRM_EVENT_STATE_ADD:
+			nss_ipsec_xfrm_trace("%p: xfrm state added\n", x);
+			return;
+		case XFRM_EVENT_STATE_DEL:
+			nss_ipsec_xfrm_trace("%p: xfrm state removed\n", x);
+			nss_ipsec_xfrm_state_delete(x);
+			return;
+		default:
+			break;
+	}
+}
+
+static struct ecm_interface_ipsec_callback xfrm_ecm_ipsec_cb =  {
+	.tunnel_get_and_hold = nss_ipsec_xfrm_get_dev_n_type
+};
+
+static struct notifier_block xfrm_ecm_notifier = {
+	.notifier_call = nss_ipsec_xfrm_ecm_conn_notify,
+};
+
+static struct xfrm_event_notifier xfrm_evt_notifier = {
+	.state_notify = nss_ipsec_xfrm_state_event_notify,
+};
+
+#if defined(NSS_L2TPV2_ENABLED)
+static struct l2tpmgr_ipsecmgr_cb xfrm_l2tp =  {
+	.get_ifnum_by_dev = NULL,
+	.get_ifnum_by_ipv4_addr = nss_ipsec_xfrm_get_inner_ifnum,
+};
+#endif
+
+/*
+ * xfrm_mgr template to listen to state and policy notifications.
+ */
+static struct xfrm_mgr nss_ipsec_xfrm_mgr = {
+	.notify         = nss_ipsec_xfrm_state_notify,
+	.acquire        = nss_ipsec_xfrm_state_acquire,
+	.compile_policy = nss_ipsec_xfrm_policy_compile,
+	.new_mapping    = NULL,
+	.notify_policy  = nss_ipsec_xfrm_policy_notify,
+	.migrate        = NULL,
+	.is_alive       = NULL,
+};
+
+/*
+ * IPv4 xfrm_state afinfo object.
+ */
+static struct xfrm_state_afinfo xfrm_v4_afinfo = {
+	.family = AF_INET,
+	.proto = IPPROTO_IPIP,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	.eth_proto = htons(ETH_P_IP),
+	.init_flags = nss_ipsec_xfrm_v4_init_flags,
+	.init_tempsel = nss_ipsec_xfrm_v4_init_sel,
+	.init_temprop = nss_ipsec_xfrm_v4_init_param,
+#endif
+	.output = nss_ipsec_xfrm_v4_output,
+	.output_finish = nss_ipsec_xfrm_v4_output_finish,
+	.extract_input = nss_ipsec_xfrm_v4_extract_input,
+	.extract_output = nss_ipsec_xfrm_v4_extract_output,
+	.transport_finish = nss_ipsec_xfrm_v4_transport_finish,
+	.local_error = nss_ipsec_xfrm_v4_local_error,
+};
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+/*
+ * IPv4 xfrm_mode object
+ */
+struct xfrm_mode xfrm_v4_mode_map[XFRM_MODE_MAX] = {
+	[XFRM_MODE_TRANSPORT] = {
+		.owner = THIS_MODULE,
+		.encap = XFRM_MODE_TRANSPORT,
+	},
+	[XFRM_MODE_TUNNEL] = {
+		.owner = THIS_MODULE,
+		.encap = XFRM_MODE_TUNNEL,
+		.flags = XFRM_MODE_FLAG_TUNNEL,
+	},
+};
+
+/*
+ * IPv6 xfrm_mode object
+ */
+struct xfrm_mode xfrm_v6_mode_map[XFRM_MODE_MAX] = {
+	[XFRM_MODE_ROUTEOPTIMIZATION] = {
+		.owner = THIS_MODULE,
+		.encap = XFRM_MODE_ROUTEOPTIMIZATION,
+	},
+	[XFRM_MODE_TRANSPORT] = {
+		.owner = THIS_MODULE,
+		.encap = XFRM_MODE_TRANSPORT,
+	},
+	[XFRM_MODE_TUNNEL] = {
+		.owner = THIS_MODULE,
+		.encap = XFRM_MODE_TUNNEL,
+		.flags = XFRM_MODE_FLAG_TUNNEL,
+	},
+};
+#endif
+
+/*
+ * IPv4 xfrm_type ESP object.
+ */
+static const struct xfrm_type xfrm_v4_type = {
+	.description = "NSS ESP4",
+	.owner = THIS_MODULE,
+	.proto = IPPROTO_ESP,
+	.flags = XFRM_TYPE_REPLAY_PROT,
+	.init_state = nss_ipsec_xfrm_esp_init_state,
+	.destructor = nss_ipsec_xfrm_esp_deinit_state,
+	.get_mtu = nss_ipsec_xfrm_esp_get_mtu,
+	.input = nss_ipsec_xfrm_esp_input,
+	.output = nss_ipsec_xfrm_esp_output,
+};
+
+/*
+ * xfrm IPv4 ESP proto handler.
+ */
+static struct xfrm4_protocol xfrm4_proto = {
+	.handler = nss_ipsec_xfrm_esp4_rcv,
+	.input_handler = nss_ipsec_xfrm_udp_rcv,
+	.cb_handler = nss_ipsec_xfrm_esp4_rcv_err,
+	.err_handler = nss_ipsec_xfrm_esp4_err,
+	.priority = INT_MAX,
+};
+
+/*
+ * IPv6 xfrm_state afinfo object.
+ */
+static struct xfrm_state_afinfo xfrm_v6_afinfo = {
+	.family = AF_INET6,
+	.proto = IPPROTO_IPV6,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	.eth_proto = htons(ETH_P_IPV6),
+	.init_tempsel = nss_ipsec_xfrm_v6_init_sel,
+	.init_temprop = nss_ipsec_xfrm_v6_init_param,
+	.tmpl_sort = nss_ipsec_xfrm_v6_sort_tmpl,
+	.state_sort = nss_ipsec_xfrm_v6_sort_state,
+#endif
+	.output = nss_ipsec_xfrm_v6_output,
+	.output_finish = nss_ipsec_xfrm_v6_output_finish,
+	.extract_input = nss_ipsec_xfrm_v6_extract_input,
+	.extract_output = nss_ipsec_xfrm_v6_extract_output,
+	.transport_finish = nss_ipsec_xfrm_v6_transport_finish,
+	.local_error = nss_ipsec_xfrm_v6_local_error,
+};
+
+/*
+ * IPv6 xfrm_type ESP object.
+ */
+static const struct xfrm_type xfrm_v6_type = {
+	.description = "NSS ESP6",
+	.owner = THIS_MODULE,
+	.proto = IPPROTO_ESP,
+	.flags = XFRM_TYPE_REPLAY_PROT,
+	.init_state = nss_ipsec_xfrm_esp_init_state,
+	.destructor = nss_ipsec_xfrm_esp_deinit_state,
+	.get_mtu = nss_ipsec_xfrm_esp_get_mtu,
+	.input = nss_ipsec_xfrm_esp_input,
+	.output = nss_ipsec_xfrm_esp_output,
+	.hdr_offset = nss_ipsec_xfrm_v6_esp_hdr_offset,
+};
+
+/*
+ * xfrm IPv6 ESP proto handler.
+ */
+static struct xfrm6_protocol xfrm6_proto = {
+	.handler = nss_ipsec_xfrm_esp6_rcv,
+	.cb_handler = nss_ipsec_xfrm_esp6_rcv_err,
+	.err_handler = nss_ipsec_xfrm_esp6_err,
+	.priority = INT_MAX,
+};
+
+static void nss_ipsec_xfrm_restore_afinfo(struct nss_ipsec_xfrm_drv *drv, uint16_t family)
+{
+	const struct xfrm_type *type_dstopts, *type_routing;
+	const struct xfrm_type *type_ipip, *type_ipv6;
+	const struct xfrm_type *type_ah, *type_comp;
+	struct xfrm_state_afinfo *afinfo;
+	const struct xfrm_type *base;
+
+	/*
+	 * Restore the native afinfo object
+	 */
+	if (family == AF_INET) {
+		base = &xfrm_v4_type;
+		afinfo = drv->xsa.v4;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		xfrm_unregister_mode(&xfrm_v4_mode_map[XFRM_MODE_TUNNEL], AF_INET);
+		xfrm_unregister_mode(&xfrm_v4_mode_map[XFRM_MODE_TRANSPORT], AF_INET);
+#endif
+	} else {
+		base = &xfrm_v6_type;
+		afinfo = drv->xsa.v6;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		xfrm_unregister_mode(&xfrm_v6_mode_map[XFRM_MODE_TUNNEL], AF_INET6);
+		xfrm_unregister_mode(&xfrm_v6_mode_map[XFRM_MODE_TRANSPORT], AF_INET6);
+		xfrm_unregister_mode(&xfrm_v6_mode_map[XFRM_MODE_ROUTEOPTIMIZATION], AF_INET6);
+#endif
+	}
+
+	BUG_ON(!afinfo);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	type_ah = afinfo->type_map[IPPROTO_AH];
+	type_comp = afinfo->type_map[IPPROTO_COMP];
+	type_ipip = afinfo->type_map[IPPROTO_IPIP];
+	type_ipv6 = afinfo->type_map[IPPROTO_IPV6];
+	type_dstopts = afinfo->type_map[IPPROTO_DSTOPTS];
+	type_routing = afinfo->type_map[IPPROTO_ROUTING];
+#else
+	type_ah = afinfo->type_ah;
+	type_comp = afinfo->type_comp;
+	type_ipip = afinfo->type_ipip;
+	type_ipv6 = afinfo->type_ipip6;
+	type_dstopts = afinfo->type_dstopts;
+	type_routing = afinfo->type_routing;
+#endif
+	/*
+	 * Unregister types
+	 */
+	if (type_routing) {
+		xfrm_unregister_type(type_routing, family);
+	}
+
+	if (type_dstopts) {
+		xfrm_unregister_type(type_dstopts, family);
+	}
+
+	if (type_ipv6) {
+		xfrm_unregister_type(type_ipv6, family);
+	}
+
+	if (type_ipip) {
+		xfrm_unregister_type(type_ipip, family);
+	}
+
+	if (type_comp) {
+		xfrm_unregister_type(type_comp, family);
+	}
+
+	if (type_ah) {
+		xfrm_unregister_type(type_ah, family);
+	}
+
+	xfrm_unregister_type(base, family);
+
+	xfrm_state_update_afinfo(family, afinfo);
+}
+
+static void nss_ipsec_xfrm_override_afinfo(struct nss_ipsec_xfrm_drv *drv, uint16_t family)
+{
+	const struct xfrm_type *type_dstopts, *type_routing;
+	const struct xfrm_type *type_ipip, *type_ipv6;
+	const struct xfrm_type *type_ah, *type_comp;
+	struct xfrm_state_afinfo *afinfo;
+	const struct xfrm_type *base;
+
+	/*
+	 * Override ESP type.
+	 */
+	if (family == AF_INET) {
+		base = &xfrm_v4_type;
+		afinfo = drv->xsa.v4 = xfrm_state_update_afinfo(AF_INET, &xfrm_v4_afinfo);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		xfrm_register_mode(&xfrm_v4_mode_map[XFRM_MODE_TRANSPORT], AF_INET);
+		xfrm_register_mode(&xfrm_v4_mode_map[XFRM_MODE_TUNNEL], AF_INET);
+#endif
+	} else {
+		base = &xfrm_v6_type;
+		afinfo = drv->xsa.v6 = xfrm_state_update_afinfo(AF_INET6, &xfrm_v6_afinfo);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		xfrm_register_mode(&xfrm_v6_mode_map[XFRM_MODE_ROUTEOPTIMIZATION], AF_INET6);
+		xfrm_register_mode(&xfrm_v6_mode_map[XFRM_MODE_TRANSPORT], AF_INET6);
+		xfrm_register_mode(&xfrm_v6_mode_map[XFRM_MODE_TUNNEL], AF_INET6);
+#endif
+	}
+
+	BUG_ON(!afinfo);
+
+	xfrm_register_type(base, family);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	type_ah = afinfo->type_map[IPPROTO_AH];
+	type_comp = afinfo->type_map[IPPROTO_COMP];
+	type_ipip = afinfo->type_map[IPPROTO_IPIP];
+	type_ipv6 = afinfo->type_map[IPPROTO_IPV6];
+	type_dstopts = afinfo->type_map[IPPROTO_DSTOPTS];
+	type_routing = afinfo->type_map[IPPROTO_ROUTING];
+#else
+	type_ah = afinfo->type_ah;
+	type_comp = afinfo->type_comp;
+	type_ipip = afinfo->type_ipip;
+	type_ipv6 = afinfo->type_ipip6;
+	type_dstopts = afinfo->type_dstopts;
+	type_routing = afinfo->type_routing;
+#endif
+	/*
+	 * Register types
+	 */
+	if (type_ah) {
+		xfrm_register_type(type_ah, family);
+	}
+
+	if (type_comp) {
+		xfrm_register_type(type_comp, family);
+	}
+
+	if (type_ipip) {
+		xfrm_register_type(type_ipip, family);
+	}
+
+	if (type_ipv6) {
+		xfrm_register_type(type_ipv6, family);
+	}
+
+	if (type_dstopts) {
+		xfrm_register_type(type_dstopts, family);
+	}
+
+	if (type_routing) {
+		xfrm_register_type(type_routing, family);
+	}
+}
+
+/*
+ * nss_ipsec_xfrm_init_module()
+ *	module_init function
+ */
+int __init nss_ipsec_xfrm_init_module(void)
+{
+
+	rwlock_init(&g_ipsec_xfrm.lock);
+
+	nss_ipsec_xfrm_init_tun_db(&g_ipsec_xfrm);
+	nss_ipsec_xfrm_init_flow_db(&g_ipsec_xfrm);
+
+	init_completion(&g_ipsec_xfrm.complete);
+
+	net_get_random_once(&g_ipsec_xfrm.hash_nonce, sizeof(g_ipsec_xfrm.hash_nonce));
+
+	/*
+	 * Listen to xfrm event notifcations
+	 */
+	xfrm_event_register_notifier(&init_net, &xfrm_evt_notifier);
+
+	/*
+	 * Register own esp handlers
+	 */
+	if (xfrm4_protocol_register(&xfrm4_proto, IPPROTO_ESP) < 0) {
+		nss_ipsec_xfrm_info_always("can't add ESP protocol for IPv4\n");
+		return -EAGAIN;
+	}
+
+	if (xfrm6_protocol_register(&xfrm6_proto, IPPROTO_ESP) < 0) {
+		nss_ipsec_xfrm_info_always("can't add ESP protocol for IPv6\n");
+		goto unreg_v4_handler;
+	}
+
+	/*
+	 * Override xfrm_state afinfo
+	 */
+	nss_ipsec_xfrm_override_afinfo(&g_ipsec_xfrm, AF_INET);
+	nss_ipsec_xfrm_override_afinfo(&g_ipsec_xfrm, AF_INET6);
+
+	ecm_interface_ipsec_register_callbacks(&xfrm_ecm_ipsec_cb);
+	ecm_notifier_register_connection_notify(&xfrm_ecm_notifier);
+
+#if defined(NSS_L2TPV2_ENABLED)
+	l2tpmgr_register_ipsecmgr_callback_by_ipaddr(&xfrm_l2tp);
+#endif
+
+	/*
+	 * Register for xfrm events
+	 */
+	xfrm_register_km(&nss_ipsec_xfrm_mgr);
+
+	/*
+	 * Initialize debugfs.
+	 */
+	nss_ipsec_xfrm_debugfs_init(&g_ipsec_xfrm);
+	nss_ipsec_xfrm_info_always("NSS IPSec xfrm plugin module loaded %s\n", NSS_CLIENT_BUILD_ID);
+	return 0;
+
+unreg_v4_handler:
+	xfrm6_protocol_deregister(&xfrm6_proto, IPPROTO_ESP);
+	return -EAGAIN;
+}
+
+/*
+ * nss_ipsec_xfrm_exit_module()
+ *	Unregister callbacks/notifiers and clear all stale data
+ */
+void __exit nss_ipsec_xfrm_exit_module(void)
+{
+	int ret;
+
+	xfrm4_protocol_deregister(&xfrm4_proto, IPPROTO_ESP);
+	xfrm6_protocol_deregister(&xfrm6_proto, IPPROTO_ESP);
+
+	nss_ipsec_xfrm_restore_afinfo(&g_ipsec_xfrm, AF_INET);
+	nss_ipsec_xfrm_restore_afinfo(&g_ipsec_xfrm, AF_INET6);
+
+	ecm_notifier_unregister_connection_notify(&xfrm_ecm_notifier);
+	ecm_interface_ipsec_unregister_callbacks();
+
+#if defined(NSS_L2TPV2_ENABLED)
+	l2tpmgr_unregister_ipsecmgr_callback_by_ipaddr();
+#endif
+	xfrm_unregister_km(&nss_ipsec_xfrm_mgr);
+
+	/*
+	 * Wait till the active tunnel count reaches zero.
+	 */
+	if (atomic_read(&g_ipsec_xfrm.num_tunnels)) {
+		ret = wait_for_completion_timeout(&g_ipsec_xfrm.complete, NSS_IPSEC_XFRM_TUNNEL_FREE_TIMEOUT);
+		WARN_ON(!ret);
+	}
+
+	/*
+	 * Remove debugfs.
+	 */
+	nss_ipsec_xfrm_debugfs_deinit(&g_ipsec_xfrm);
+
+	/*
+	 * Unregister xfrm event notifcations
+	 */
+	xfrm_event_unregister_notifier(&init_net, &xfrm_evt_notifier);
+
+	nss_ipsec_xfrm_info_always("NSS IPSec xfrm plugin module unloaded\n");
+}
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS IPsec XFRM offload glue");
+
+module_init(nss_ipsec_xfrm_init_module);
+module_exit(nss_ipsec_xfrm_exit_module);
diff --git a/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm.h b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm.h
new file mode 100644
index 0000000..96ed6ae
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm.h
@@ -0,0 +1,153 @@
+/* Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_IPSEC_XFRM_H
+#define __NSS_IPSEC_XFRM_H
+
+#define NSS_IPSEC_XFRM_TUN_DB_MAX 128
+#define NSS_IPSEC_XFRM_FLOW_DB_MAX 1024
+
+#define NSS_IPSEC_XFRM_TUNNEL_FREE_TIMEOUT_MSECS 10000
+#define NSS_IPSEC_XFRM_TUNNEL_FREE_TIMEOUT msecs_to_jiffies(NSS_IPSEC_XFRM_TUNNEL_FREE_TIMEOUT_MSECS)
+
+#define NSS_IPSEC_XFRM_DEBUG_LVL_ERROR 1
+#define NSS_IPSEC_XFRM_DEBUG_LVL_WARN 2
+#define NSS_IPSEC_XFRM_DEBUG_LVL_INFO 3
+#define NSS_IPSEC_XFRM_DEBUG_LVL_TRACE 4
+
+#define nss_ipsec_xfrm_info_always(s, ...) pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_ipsec_xfrm_err(s, ...) do {	\
+	if (net_ratelimit()) {	\
+		pr_alert("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+} while (0)
+
+#define nss_ipsec_xfrm_warn(s, ...) do {	\
+	if (net_ratelimit()) {	\
+		pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+} while (0)
+
+#define nss_ipsec_xfrm_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_ipsec_xfrm_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#define nss_ipsec_xfrm_err(s, ...) {	\
+	if (NSS_IPSEC_XFRM_DEBUG_LEVEL > NSS_IPSEC_XFRM_DEBUG_LVL_ERROR) {	\
+		pr_alert("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+#define nss_ipsec_xfrm_warn(s, ...) {	\
+	if (NSS_IPSEC_XFRM_DEBUG_LEVEL > NSS_IPSEC_XFRM_DEBUG_LVL_WARN) {	\
+		pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+#define nss_ipsec_xfrm_info(s, ...) {	\
+	if (NSS_IPSEC_XFRM_DEBUG_LEVEL > NSS_IPSEC_XFRM_DEBUG_LVL_INFO) {	\
+		pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+#define nss_ipsec_xfrm_trace(s, ...) {	\
+	if (NSS_IPSEC_XFRM_DEBUG_LEVEL > NSS_IPSEC_XFRM_DEBUG_LVL_TRACE) {	\
+		pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+
+#endif /* !CONFIG_DYNAMIC_DEBUG */
+
+#define NSS_IPSEC_XFRM_PRINT_PAGES 2
+#define NSS_IPSEC_XFRM_PRINT_BYTES(bytes) ((((bytes) * BITS_PER_BYTE) / 4) + 4)
+#define NSS_IPSEC_XFRM_PRINT_DWORD NSS_IPSEC_XFRM_PRINT_BYTES(8)
+#define NSS_IPSEC_XFRM_PRINT_WORD NSS_IPSEC_XFRM_PRINT_BYTES(4)
+#define NSS_IPSEC_XFRM_PRINT_SHORT NSS_IPSEC_XFRM_PRINT_BYTES(2)
+#define NSS_IPSEC_XFRM_PRINT_BYTE NSS_IPSEC_XFRM_PRINT_BYTES(1)
+#define NSS_IPSEC_XFRM_PRINT_IPADDR (NSS_IPSEC_XFRM_PRINT_WORD * 4)
+#define NSS_IPSEC_XFRM_PRINT_EXTRA 64      /* Bytes */
+
+/*
+ * Statistics dump information
+ */
+struct nss_ipsec_xfrm_print {
+	char *str;              /* Name of variable. */
+	ssize_t var_size;       /* Size of variable in bytes. */
+};
+
+struct nss_ipsec_xfrm_fallback {
+	struct xfrm_state_afinfo *v4;
+	struct xfrm_state_afinfo *v6;
+};
+
+/*
+ * nss_ipsec_xfrm_drv_stats
+ *	NSS IPSec DRV stats.
+ */
+struct nss_ipsec_xfrm_drv_stats {
+	atomic64_t encap_nss;		/* Number of Packets sent(queued) to NSS for encap */
+	atomic64_t encap_drop;		/* Number of Packets dropped that were trapped for encap */
+	atomic64_t decap_nss;		/* Number of Packets queued to NSS for decap */
+	atomic64_t decap_drop;		/* Number of Packets dropped that were trapped for decap */
+	atomic64_t inner_except;	/* Number of inner exceptions that were indicated to stack*/
+	atomic64_t inner_drop; 		/* Number of inner exceptions that were dropped*/
+	atomic64_t outer_except;        /* Number of outer exceptions that were sent out*/
+	atomic64_t outer_drop;          /* Number of outer exceptions that were dropped */
+	atomic64_t tun_alloced;		/* Number of tun objects created */
+	atomic64_t tun_dealloced;	/* Number of tun objects created */
+	atomic64_t tun_freed;		/* Number of tun objects released(freed) */
+	atomic64_t sa_alloced;		/* Number of sa objects created */
+	atomic64_t sa_dealloced;	/* Number of sa objects created */
+	atomic64_t sa_freed;		/* Number of sa objects released(freed) */
+	atomic64_t flow_alloced;	/* Number of flow objects created */
+	atomic64_t flow_dealloced;	/* Number of flow objects created */
+	atomic64_t flow_freed;		/* Number of flow objects deleted */
+};
+
+/*
+ * IPSec xfrm plugin instance
+ */
+struct nss_ipsec_xfrm_drv {
+	struct list_head tun_db[NSS_IPSEC_XFRM_TUN_DB_MAX];	/* Tunnel Hash Database */
+	struct list_head flow_db[NSS_IPSEC_XFRM_FLOW_DB_MAX];	/* Flow Hash Database */
+	struct nss_ipsec_xfrm_drv_stats stats;			/* Statistics */
+	struct nss_ipsec_xfrm_fallback xsa;			/* Pointers to original xfrm_state_afinfo instances */
+	struct completion complete;				/* Completion for num of active tunnels to go zero. */
+	struct dentry *dentry;					/* Debugfs root directory. */
+	size_t stats_len;					/* Size of stats */
+	rwlock_t lock;						/* Lock for DB operations */
+	atomic_t num_tunnels;					/* Number of active tunnels */
+	uint32_t hash_nonce;					/* One time random number */
+};
+
+/*
+ * nss_ipsec_xfrm_get_hash()
+ *	Computes hash code for a given key
+ */
+static inline uint32_t nss_ipsec_xfrm_get_hash(uint32_t *key, uint32_t key_len, uint32_t seed)
+{
+	return jhash2(key, key_len / sizeof(uint32_t), seed);
+
+}
+
+void nss_ipsec_xfrm_update_stats(struct nss_ipsec_xfrm_drv *drv, struct nss_ipsecmgr_sa_stats *stats);
+#endif /* !__NSS_IPSEC_XFRM_H */
diff --git a/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_flow.c b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_flow.c
new file mode 100644
index 0000000..e7eec5c
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_flow.c
@@ -0,0 +1,299 @@
+/* Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/if.h>
+#include <linux/list.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <net/xfrm.h>
+#include <net/protocol.h>
+#include <net/esp.h>
+#include <linux/inetdevice.h>
+#include <net/addrconf.h>
+#include <linux/netfilter.h>
+
+#include <nss_api_if.h>
+#include <nss_ipsec.h>
+#include <nss_ipsecmgr.h>
+
+#include "nss_ipsec_xfrm_tunnel.h"
+#include "nss_ipsec_xfrm_sa.h"
+#include "nss_ipsec_xfrm_flow.h"
+#include "nss_ipsec_xfrm.h"
+
+/*
+ * nss_ipsec_xfrm_flow_final()
+ *	Frees the flow object.
+ */
+static void nss_ipsec_xfrm_flow_final(struct kref *kref)
+{
+	struct nss_ipsec_xfrm_flow *flow = container_of(kref, struct nss_ipsec_xfrm_flow, ref);
+	struct nss_ipsec_xfrm_drv *drv = flow->drv;
+
+	nss_ipsec_xfrm_info("%p:Flow released\n", flow);
+
+	/*
+	 * Release reference to the parent SA.
+	 */
+	if (flow->sa) {
+		nss_ipsec_xfrm_sa_deref(flow->sa);
+		flow->sa = NULL;
+	}
+
+	if (flow->pol) {
+		xfrm_pol_put(flow->pol);
+		flow->pol = NULL;
+	}
+
+	atomic64_inc(&drv->stats.flow_freed);
+	kfree(flow);
+}
+
+/*
+ * nss_ipsec_xfrm_flow_hdr2tuple()
+ *	Parse header and populate the flow tuple
+ */
+void nss_ipsec_xfrm_flow_hdr2tuple(struct sk_buff *skb, bool natt, struct nss_ipsecmgr_flow_tuple *tuple)
+{
+	memset(tuple, 0, sizeof(*tuple));
+
+	if (ip_hdr(skb)->version == IPVERSION) {
+		struct iphdr *iph = ip_hdr(skb);
+
+		tuple->src_ip[0] = ntohl(iph->saddr);
+		tuple->dest_ip[0] = ntohl(iph->daddr);
+		tuple->proto_next_hdr = iph->protocol;
+		tuple->ip_version = IPVERSION;
+	} else {
+		struct ipv6hdr *ip6h = ipv6_hdr(skb);
+
+		tuple->src_ip[0] = ntohl(ip6h->saddr.s6_addr32[0]);
+		tuple->src_ip[1] = ntohl(ip6h->saddr.s6_addr32[1]);
+		tuple->src_ip[2] = ntohl(ip6h->saddr.s6_addr32[2]);
+		tuple->src_ip[3] = ntohl(ip6h->saddr.s6_addr32[3]);
+
+		tuple->dest_ip[0] = ntohl(ip6h->daddr.s6_addr32[0]);
+		tuple->dest_ip[1] = ntohl(ip6h->daddr.s6_addr32[1]);
+		tuple->dest_ip[2] = ntohl(ip6h->daddr.s6_addr32[2]);
+		tuple->dest_ip[3] = ntohl(ip6h->daddr.s6_addr32[3]);
+		tuple->proto_next_hdr = ip6h->nexthdr;
+		tuple->ip_version = 6;
+	}
+
+	switch (tuple->proto_next_hdr) {
+	case IPPROTO_UDP:
+		tuple->sport = ntohs(udp_hdr(skb)->source);
+		tuple->dport = ntohs(udp_hdr(skb)->dest);
+
+		/*
+		 * Check if this a NAT-T outer flow
+		 */
+		if (natt) {
+			struct ip_esp_hdr *esph = (struct ip_esp_hdr *)(udp_hdr(skb) + 1);
+			tuple->spi_index = ntohl(esph->spi);
+		}
+		break;
+
+	case IPPROTO_TCP:
+		tuple->sport = ntohs(tcp_hdr(skb)->source);
+		tuple->dport = ntohs(tcp_hdr(skb)->dest);
+		break;
+
+	case IPPROTO_ESP:
+		tuple->spi_index = ntohl(ip_esp_hdr(skb)->spi);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/*
+ * nss_ipsec_xfrm_flow_match()
+ *	Returns true if the provided flow tuple matches the flow.
+ */
+bool nss_ipsec_xfrm_flow_match(struct nss_ipsec_xfrm_flow *flow, struct nss_ipsecmgr_flow_tuple *s)
+{
+	struct nss_ipsecmgr_flow_tuple *d = &flow->tuple;
+	uint32_t status = 0;
+
+	switch (d->ip_version) {
+		case IPVERSION:
+			status += d->dest_ip[0] ^ s->dest_ip[0];
+			status += d->src_ip[0] ^ s->src_ip[0];
+			status += d->spi_index ^ s->spi_index;
+
+			status += d->sport ^ s->sport;
+			status += d->dport ^ s->dport;
+
+			status += d->ip_version ^ s->ip_version;
+			status += d->proto_next_hdr ^ s->proto_next_hdr;
+			return !status;
+
+		case 6:
+			status += d->dest_ip[0] ^ s->dest_ip[0];
+			status += d->dest_ip[1] ^ s->dest_ip[1];
+			status += d->dest_ip[2] ^ s->dest_ip[2];
+			status += d->dest_ip[3] ^ s->dest_ip[3];
+			status += d->src_ip[0] ^ s->src_ip[0];
+			status += d->src_ip[1] ^ s->src_ip[1];
+			status += d->src_ip[2] ^ s->src_ip[2];
+			status += d->src_ip[3] ^ s->src_ip[3];
+			status += d->spi_index ^ s->spi_index;
+
+			status += d->sport ^ s->sport;
+			status += d->dport ^ s->dport;
+
+			status += d->ip_version ^ s->ip_version;
+			status += d->proto_next_hdr ^ s->proto_next_hdr;
+			return !status;
+	}
+
+	return false;
+}
+
+/*
+ * nss_ipsec_xfrm_flow_deref()
+ *	Put flow ref.
+ */
+void nss_ipsec_xfrm_flow_deref(struct nss_ipsec_xfrm_flow *flow)
+{
+	kref_put(&flow->ref, nss_ipsec_xfrm_flow_final);
+}
+
+/*
+ * nss_ipsec_xfrm_flow_ref()
+ *	Hold flow ref.
+ */
+struct nss_ipsec_xfrm_flow *nss_ipsec_xfrm_flow_ref(struct nss_ipsec_xfrm_flow *flow)
+{
+	kref_get(&flow->ref);
+	return flow;
+}
+
+/*
+ * nss_ipsec_xfrm_flow_update()
+ *	Update Flow if the SA is same then this is duplicate otherwise update the SA.
+ *
+ * Note: The IPsec manager internally takes care of the migration for its flow object
+ */
+bool nss_ipsec_xfrm_flow_update(struct nss_ipsec_xfrm_flow *flow, struct nss_ipsec_xfrm_sa *sa)
+{
+	struct nss_ipsec_xfrm_sa *flow_sa = flow->sa;
+	enum nss_ipsecmgr_status status;
+
+	/*
+	 * The SA is different it means flow is migrating to new SA
+	 */
+	status = nss_ipsecmgr_flow_add(sa->tun->dev, &flow->tuple, &sa->tuple);
+	if ((status != NSS_IPSECMGR_DUPLICATE_FLOW) && (status != NSS_IPSECMGR_OK)) {
+		nss_ipsec_xfrm_err("%p:Failed to add flow to ipsecmgr; status %d, sa %p\n", flow, status, sa);
+		return false;
+	}
+
+	/*
+	 * If the SA is same then the flow is already configured
+	 */
+	if (flow_sa == sa) {
+		return true;
+	}
+
+
+	nss_ipsec_xfrm_info("%p: Flow migrated from SA %p to SA %p\n", flow, flow_sa, sa);
+
+	xchg(&flow->sa, nss_ipsec_xfrm_sa_ref(sa));
+	nss_ipsec_xfrm_sa_deref(flow_sa);
+
+	return true;
+}
+
+/*
+ * nss_ipsec_xfrm_flow_dealloc()
+ * 	Deallocate an existing flow object
+ */
+void nss_ipsec_xfrm_flow_dealloc(struct nss_ipsec_xfrm_flow *flow)
+{
+	struct nss_ipsec_xfrm_drv *drv = flow->drv;
+	struct nss_ipsec_xfrm_tunnel *tun;
+	struct nss_ipsec_xfrm_sa *sa;
+
+	nss_ipsec_xfrm_info("%p", flow);
+
+	atomic64_inc(&drv->stats.flow_dealloced);
+
+	sa = flow->sa;
+	BUG_ON(!sa);
+
+	tun = sa->tun;
+	BUG_ON(!tun);
+
+	/*
+	 * Delete from IPSecmgr; release the reference acquired in alloc
+	 */
+	nss_ipsecmgr_flow_del(tun->dev, &flow->tuple, &sa->tuple);
+	nss_ipsec_xfrm_flow_deref(flow);
+}
+
+/*
+ * nss_ipsec_xfrm_flow_alloc()
+ * 	Allocate a new flow object
+ */
+struct nss_ipsec_xfrm_flow *nss_ipsec_xfrm_flow_alloc(struct nss_ipsec_xfrm_drv *drv,
+							struct nss_ipsecmgr_flow_tuple *tuple,
+							struct nss_ipsec_xfrm_sa *sa)
+{
+	struct nss_ipsec_xfrm_flow *flow;
+	enum nss_ipsecmgr_status status;
+
+	flow = kzalloc(sizeof(struct nss_ipsec_xfrm_flow), GFP_ATOMIC);
+	if (!flow) {
+		nss_ipsec_xfrm_err("Failed to create flow; Out of memory\n");
+		return NULL;
+	}
+
+	flow->drv = drv;
+	memcpy(&flow->tuple, tuple, sizeof(struct nss_ipsecmgr_flow_tuple));
+	kref_init(&flow->ref);
+
+	atomic64_inc(&drv->stats.flow_alloced);
+
+	if (flow->tuple.ip_version == IPVERSION) {
+		nss_ipsec_xfrm_info("New IPv4 flow %p created; sip %pI4h dip %pI4h proto %d sport %d dport %d\n", flow,
+				flow->tuple.src_ip, flow->tuple.dest_ip, flow->tuple.proto_next_hdr,
+				flow->tuple.sport, flow->tuple.dport);
+	} else {
+		nss_ipsec_xfrm_info("New IPv6 flow %p created; sip %pI6h dip %pI6h proto %d sport %d dport %d\n", flow,
+				flow->tuple.src_ip, flow->tuple.dest_ip, flow->tuple.proto_next_hdr,
+				flow->tuple.sport, flow->tuple.dport);
+	}
+
+	flow->sa = nss_ipsec_xfrm_sa_ref(sa);
+
+	status = nss_ipsecmgr_flow_add(sa->tun->dev, &flow->tuple, &sa->tuple);
+	if ((status != NSS_IPSECMGR_DUPLICATE_FLOW) && (status != NSS_IPSECMGR_OK)) {
+		nss_ipsec_xfrm_err("%p:Failed to add flow to ipsecmgr; status %d, sa %p\n", flow, status, sa);
+		goto error;
+	}
+
+	nss_ipsec_xfrm_info("%p:Flow %p added to SA %p\n", drv, flow, sa);
+	return flow;
+
+error:
+	nss_ipsec_xfrm_flow_deref(flow);
+	return NULL;
+}
diff --git a/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_flow.h b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_flow.h
new file mode 100644
index 0000000..92a98b3
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_flow.h
@@ -0,0 +1,44 @@
+/* Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_IPSEC_XFRM_FLOW_H
+#define __NSS_IPSEC_XFRM_FLOW_H
+
+/*
+ * NSS IPSec xfrm Flow obj
+ */
+struct nss_ipsec_xfrm_flow {
+	struct list_head list_entry; 		/* Hash DB Entry */
+	struct nss_ipsec_xfrm_drv *drv; 	/* Pointer to nss_ipsec_xfrm_drv object */
+	struct nss_ipsecmgr_flow_tuple tuple;	/* Cached Parameters for this Flow object*/
+
+	struct kref ref; 			/* Reference count */
+	atomic_t allow_accel;			/* Acceleration is allowed for this flow or not(currently unused) */
+	struct xfrm_policy *pol; 		/* Reference to xfrm stack's policy object */
+	struct nss_ipsec_xfrm_sa *sa; 		/* Reference to the SA object */
+};
+
+void nss_ipsec_xfrm_flow_hdr2tuple(struct sk_buff *skb, bool natt, struct nss_ipsecmgr_flow_tuple *tuple);
+bool nss_ipsec_xfrm_flow_match(struct nss_ipsec_xfrm_flow *flow, struct nss_ipsecmgr_flow_tuple *tuple);
+
+void nss_ipsec_xfrm_flow_deref(struct nss_ipsec_xfrm_flow *flow);
+struct nss_ipsec_xfrm_flow *nss_ipsec_xfrm_flow_ref(struct nss_ipsec_xfrm_flow *flow);
+
+bool nss_ipsec_xfrm_flow_update(struct nss_ipsec_xfrm_flow *flow, struct nss_ipsec_xfrm_sa *new_sa);
+void nss_ipsec_xfrm_flow_dealloc(struct nss_ipsec_xfrm_flow *flow);
+struct nss_ipsec_xfrm_flow *nss_ipsec_xfrm_flow_alloc(struct nss_ipsec_xfrm_drv *ctx,
+							struct nss_ipsecmgr_flow_tuple *tuple,
+							struct nss_ipsec_xfrm_sa *sa);
+#endif /* !__NSS_IPSEC_XFRM_FLOW_H */
diff --git a/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_sa.c b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_sa.c
new file mode 100644
index 0000000..3f4a768
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_sa.c
@@ -0,0 +1,495 @@
+/* Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/if.h>
+#include <linux/list.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <net/xfrm.h>
+#include <net/esp.h>
+#include <net/protocol.h>
+#include <linux/inetdevice.h>
+#include <net/addrconf.h>
+#include <linux/netfilter.h>
+#include <crypto/authenc.h>
+#include <nss_api_if.h>
+#include <nss_ipsec.h>
+#include <nss_ipsecmgr.h>
+#include <ecm_interface_ipsec.h>
+#include <ecm_notifier.h>
+
+#include "nss_ipsec_xfrm_tunnel.h"
+#include "nss_ipsec_xfrm_sa.h"
+#include "nss_ipsec_xfrm_flow.h"
+#include "nss_ipsec_xfrm.h"
+
+/*
+ * XFRM algorithm to IPsec manager algorithm map
+ */
+struct nss_ipsec_xfrm_algo {
+	const char *cipher_name;		/* XFRM Cipher algorithm name */
+	const char *auth_name;		/* XFRM Authentication algorithm name */
+	enum nss_ipsecmgr_algo algo;	/* IPsec manager algorithm number */
+};
+
+/*
+ * Linux crypto algorithm names.
+ */
+static struct nss_ipsec_xfrm_algo xfrm_algo[] = {
+	{.cipher_name = "cbc(aes)", .auth_name = "hmac(sha1)", .algo = NSS_IPSECMGR_ALGO_AES_CBC_SHA1_HMAC},
+	{.cipher_name = "cbc(des3_ede)", .auth_name = "hmac(sha1)", .algo = NSS_IPSECMGR_ALGO_3DES_CBC_SHA1_HMAC},
+	{.cipher_name  = "cbc(aes)", .auth_name = "hmac(md5)", .algo = NSS_IPSECMGR_ALGO_AES_CBC_MD5_HMAC},
+	{.cipher_name = "cbc(des3_ede)", .auth_name = "hmac(md5)", .algo = NSS_IPSECMGR_ALGO_3DES_CBC_MD5_HMAC},
+	{.cipher_name = "rfc4106(gcm(aes))", .auth_name = "rfc4106(gcm(aes))", .algo = NSS_IPSECMGR_ALGO_AES_GCM_GMAC_RFC4106},
+	{.cipher_name = "ecb(cipher_null)", .auth_name = "hmac(sha1)", .algo = NSS_IPSECMGR_ALGO_NULL_CIPHER_SHA1_HMAC},
+	{.cipher_name = "cbc(aes)", .auth_name = "hmac(sha256)", .algo = NSS_IPSECMGR_ALGO_AES_CBC_SHA256_HMAC},
+	{.cipher_name = "cbc(des3_ede)", .auth_name = "hmac(sha256)", .algo = NSS_IPSECMGR_ALGO_3DES_CBC_SHA256_HMAC},
+	{.cipher_name = "ecb(cipher_null)", .auth_name = "hmac(sha256)", .algo = NSS_IPSECMGR_ALGO_NULL_CIPHER_SHA256_HMAC},
+};
+
+/*
+ * nss_ipsec_xfrm_sa_get_algo()
+ *	Get the IPsec manager algorithm from XFRM cipher & authentication names
+ */
+static enum nss_ipsecmgr_algo nss_ipsec_xfrm_sa_get_algo(struct nss_ipsec_xfrm_sa *sa, char *cipher_name, char *auth_name)
+{
+	struct nss_ipsec_xfrm_algo *xalg = xfrm_algo;
+	uint32_t i;
+
+	nss_ipsec_xfrm_trace("%p: get XFRM algorithm name(%s,%s) to IPsec manager algo", sa,
+			cipher_name ? cipher_name : "", auth_name ? auth_name : "");
+
+	for (i = 0; i < ARRAY_SIZE(xfrm_algo); i++, xalg++) {
+		if (cipher_name && strncmp(xalg->cipher_name, cipher_name, strlen(xalg->cipher_name))) {
+			continue;
+		}
+
+		if (auth_name && strncmp(xalg->auth_name, auth_name, strlen(xalg->auth_name))) {
+			continue;
+		}
+
+		return xalg->algo;
+	}
+
+	return NSS_IPSECMGR_ALGO_MAX;
+}
+
+/*
+ * nss_ipsec_xfrm_sa_final()
+ *	Frees the SA object
+ */
+static void nss_ipsec_xfrm_sa_final(struct kref *kref)
+{
+	struct nss_ipsec_xfrm_sa *sa = container_of(kref, struct nss_ipsec_xfrm_sa, ref);
+	struct nss_ipsec_xfrm_tunnel *tun = sa->tun;
+	struct nss_ipsec_xfrm_drv *drv = sa->drv;
+
+	nss_ipsec_xfrm_info("%p: SA freed\n", sa);
+
+	if (tun) {
+		nss_ipsec_xfrm_tunnel_deref(sa->tun);
+		sa->tun = NULL;
+	}
+
+	atomic64_inc(&drv->stats.sa_freed);
+	kfree(sa);
+}
+
+static bool nss_ipsec_xfrm_sa_init_crypto(struct nss_ipsec_xfrm_sa *sa, struct xfrm_state *x)
+{
+	struct nss_ipsecmgr_crypto_keys *nick = &sa->data.cmn.keys;
+	struct nss_ipsecmgr_sa_cmn *nisc = &sa->data.cmn;
+	char *cipher_name, *auth_name;
+
+	if (x->aead) { /* Combined mode cipher/authentication */
+		unsigned int key_len = 0;
+
+		key_len = ALIGN(x->aead->alg_key_len, BITS_PER_BYTE) / BITS_PER_BYTE;
+
+		/* Cipher */
+		cipher_name = x->aead->alg_name;
+		nick->cipher_keylen = key_len - 4; /* Subtract nonce */
+		nick->cipher_key = x->aead->alg_key;
+
+		/* Authentication; No separate auth keys */
+		auth_name = x->aead->alg_name;
+		nisc->icv_len = x->aead->alg_icv_len / BITS_PER_BYTE;
+
+		/* Nonce */
+		nick->nonce_size = 4;
+		nick->nonce = x->aead->alg_key + nick->cipher_keylen;
+	} else if (x->ealg && x->aalg) { /* Authenticated encryption */
+		/* Cipher */
+		cipher_name = x->ealg->alg_name;
+		nick->cipher_keylen = ALIGN(x->ealg->alg_key_len, BITS_PER_BYTE) / BITS_PER_BYTE;
+		nick->cipher_key = x->ealg->alg_key;
+
+		/* Authentication */
+		auth_name = x->aalg->alg_name;
+		nick->auth_keylen = ALIGN(x->aalg->alg_key_len, BITS_PER_BYTE) / BITS_PER_BYTE;
+		nick->auth_key = x->aalg->alg_key;
+		nisc->icv_len =  x->aalg->alg_trunc_len / BITS_PER_BYTE;
+	} else if (x->ealg) { /* Pure encryption */
+		/* Cipher */
+		cipher_name = x->ealg->alg_name;
+		nick->cipher_keylen = ALIGN(x->ealg->alg_key_len, BITS_PER_BYTE) / BITS_PER_BYTE;
+		nick->cipher_key = x->ealg->alg_key;
+
+		/* Authentication */
+		auth_name = NULL;
+		nick->auth_keylen = 0;
+		nick->auth_key = NULL;
+		nisc->icv_len =  0;
+	} else { /* Bypass mode */
+		cipher_name = "NULL";
+		auth_name = "NULL";
+		memset(nick, 0, sizeof(struct nss_ipsecmgr_crypto_keys));
+		nisc->icv_len = 0;
+	}
+
+	nisc->algo = nss_ipsec_xfrm_sa_get_algo(sa, cipher_name, auth_name);
+	if (nisc->algo == NSS_IPSECMGR_ALGO_MAX) {
+		nss_ipsec_xfrm_err("%p: Failed to find algorithm (%s,%s)\n", sa, cipher_name ? cipher_name : "",
+				auth_name ? auth_name : "");
+		memset(nick, 0, sizeof(struct nss_ipsecmgr_crypto_keys));
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_ipsec_xfrm_sa_init_tuple
+ *	Initialize the SA tuple from XFRM state
+ */
+static void nss_ipsec_xfrm_sa_init_tuple(struct nss_ipsec_xfrm_sa *sa, struct xfrm_state *x)
+{
+	struct net_device *local_dev;
+
+	sa->type = NSS_IPSECMGR_SA_TYPE_ENCAP;
+	sa->tuple.spi_index = ntohl(x->id.spi);
+	sa->tuple.proto_next_hdr = IPPROTO_ESP;
+
+	/*
+	* Check if this is ESP-over-UDP SA
+	*/
+	if (x->encap) {
+		sa->tuple.sport = ntohs(x->encap->encap_sport);
+		sa->tuple.dport = ntohs(x->encap->encap_dport);
+		sa->tuple.proto_next_hdr = IPPROTO_UDP;
+	}
+
+	if (x->props.family == AF_INET) {
+		sa->tuple.ip_version = IPVERSION;
+		sa->tuple.src_ip[0] = ntohl(x->props.saddr.a4);
+		sa->tuple.dest_ip[0] = ntohl(x->id.daddr.a4);
+
+		local_dev = ip_dev_find(&init_net, x->id.daddr.a4);
+	} else {
+		sa->tuple.ip_version = 6;
+
+		sa->tuple.src_ip[0] = ntohl(x->props.saddr.a6[0]);
+		sa->tuple.src_ip[1] = ntohl(x->props.saddr.a6[1]);
+		sa->tuple.src_ip[2] = ntohl(x->props.saddr.a6[2]);
+		sa->tuple.src_ip[3] = ntohl(x->props.saddr.a6[3]);
+
+		sa->tuple.dest_ip[0] = ntohl(x->id.daddr.a6[0]);
+		sa->tuple.dest_ip[1] = ntohl(x->id.daddr.a6[1]);
+		sa->tuple.dest_ip[2] = ntohl(x->id.daddr.a6[2]);
+		sa->tuple.dest_ip[3] = ntohl(x->id.daddr.a6[3]);
+
+		local_dev = ipv6_dev_find(&init_net, (struct in6_addr *)x->id.daddr.a6, 1);
+	}
+
+	/*
+	 * Check if the SA is outer or inner and override the type
+	 */
+	if (local_dev) {
+		dev_put(local_dev);
+		sa->type = NSS_IPSECMGR_SA_TYPE_DECAP;
+	}
+}
+
+/*
+ * nss_ipsec_xfrm_sa_deinit()
+ *	Deinitialize the SA.
+ */
+void nss_ipsec_xfrm_sa_deinit(struct xfrm_state *x)
+{
+	nss_ipsec_xfrm_info("%p: flags 0x%x\n", x, x->xflags);
+
+	/*
+	 * If XFRM state was programmed, then deinit
+	 */
+	if (x->xflags & XFRM_STATE_OFFLOAD_NSS) {
+		x->xflags &= ~XFRM_STATE_OFFLOAD_NSS;
+		nss_ipsec_xfrm_sa_deref(x->data);
+		x->data = NULL;
+	}
+}
+
+/*
+ * nss_ipsec_xfrm_sa_init()
+ * 	Initialize common SA parameters befor programming the IPsec manager
+ */
+static void nss_ipsec_xfrm_sa_init(struct nss_ipsec_xfrm_sa *sa, struct xfrm_state *x)
+{
+	struct nss_ipsecmgr_sa_data *sa_data = &sa->data;
+	struct nss_ipsec_xfrm_tunnel *tun = sa->tun;
+
+	nss_ipsec_xfrm_sa_init_tuple(sa, x);
+
+	sa_data->type = sa->type;
+
+	if (sa_data->type == NSS_IPSECMGR_SA_TYPE_ENCAP) {
+		sa_data->encap.ttl_hop_limit = tun->ttl;
+		sa_data->encap.copy_dscp = !(x->props.extra_flags & XFRM_SA_XFLAG_DONT_ENCAP_DSCP);
+		sa_data->encap.copy_df = !(x->props.flags & XFRM_STATE_NOPMTUDISC);
+
+		/*
+		 * TODO: Handle ECN
+		 */
+		nss_ipsec_xfrm_trace("%p: Encap SA xfrm(%p), ttl(%d), dscp(%d), df(%d)\n", sa, x,
+				sa_data->encap.ttl_hop_limit, sa_data->encap.copy_dscp, sa_data->encap.copy_df);
+	} else {
+		uint32_t replay_win = x->props.replay_window / BITS_PER_BYTE;
+
+		sa_data->decap.replay_win = replay_win & (NSS_IPSEC_XFRM_SA_MAX_REPLAY_WIN_SZ - 1);
+		nss_ipsec_xfrm_trace("%p: Decap SA xfrm(%p), replay_win(%u) \n", sa, x, sa_data->decap.replay_win);
+	}
+
+	sa_data->cmn.transport_mode = (x->props.mode == XFRM_MODE_TRANSPORT);
+	sa_data->cmn.enable_esn = !!(x->props.flags & XFRM_STATE_ESN);
+	sa_data->cmn.enable_natt = !!x->encap;
+	sa_data->cmn.skip_trailer = false;
+	sa_data->cmn.crypto_has_keys = true;
+
+	/*
+	 * Bind XFRM state to SA
+	 */
+	x->data = nss_ipsec_xfrm_sa_ref(sa);
+	x->xflags |= XFRM_STATE_OFFLOAD_NSS;
+}
+
+/*
+ * nss_ipsec_xfrm_sa_sp_set()
+ * 	Load skb with sp.
+ */
+bool nss_ipsec_xfrm_sa_sp_set(struct nss_ipsec_xfrm_sa *sa, struct sk_buff *skb)
+{
+	struct sec_path *sp;
+	struct xfrm_state *x;
+
+	/*
+	 * Lookup the XFRM state using SPI index; note that this will hold the state reference
+	 * which needs to be released after the SP usage is over
+	 */
+	x = xfrm_state_lookup_byspi(&init_net, htonl(sa->tuple.spi_index), sa->tun->family);
+	if (!x) {
+		nss_ipsec_xfrm_err("%p: Failed to set SP; no XFRM state found, spi(%u)\n", sa, sa->tuple.spi_index);
+		return false;
+	}
+
+	/*
+	 * Allocate a new SP for the incoming SKB
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+	skb->sp = sp = secpath_dup(NULL);
+#else
+	sp = secpath_set(skb);
+#endif
+	if(!sp) {
+		xfrm_state_put(x);
+		return false;
+	}
+
+	sp->xvec[sp->len++] = x;
+	return true;
+}
+
+/*
+ * nss_ipsec_xfrm_sa_deref()
+ *	Put SA ref.
+ */
+void  nss_ipsec_xfrm_sa_deref(struct nss_ipsec_xfrm_sa *sa)
+{
+	kref_put(&sa->ref, nss_ipsec_xfrm_sa_final);
+}
+
+/*
+ * nss_ipsec_xfrm_sa_ref()
+ *	Hold SA ref.
+ */
+struct nss_ipsec_xfrm_sa *nss_ipsec_xfrm_sa_ref(struct nss_ipsec_xfrm_sa *sa)
+{
+	kref_get(&sa->ref);
+	return sa;
+}
+
+/*
+ * nss_ipsec_xfrm_sa_ref_by_spi()
+ * 	Get NSS xfrm plugin SA object from spi_index and family
+ */
+struct nss_ipsec_xfrm_sa *nss_ipsec_xfrm_sa_ref_by_spi(uint32_t spi_index, uint32_t family)
+{
+	struct nss_ipsec_xfrm_sa * sa;
+	struct xfrm_state *x;
+
+	/*
+	 * Lookup XFRM state by SPI index
+	 */
+	x = xfrm_state_lookup_byspi(&init_net, htonl(spi_index), family);
+	if (!x) {
+		return NULL;
+	}
+
+	sa = nss_ipsec_xfrm_sa_ref_by_state(x);
+	xfrm_state_put(x);
+
+	return sa;
+}
+
+/*
+ * nss_ipsec_xfrm_sa_ref_by_state()
+ *	 Get NSS xfrm plugin SA object from xfrm state.
+ */
+struct nss_ipsec_xfrm_sa *nss_ipsec_xfrm_sa_ref_by_state(struct xfrm_state *x)
+{
+	if (x->xflags & XFRM_STATE_OFFLOAD_NSS) {
+		return nss_ipsec_xfrm_sa_ref(x->data);
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_ipsec_xfrm_sa_dealloc()
+ *	Delete an SA object. Expected to be called when the associated xfrm_state is getting deleted.
+ */
+void nss_ipsec_xfrm_sa_dealloc(struct nss_ipsec_xfrm_sa *sa, struct xfrm_state *x)
+{
+	struct nss_ipsec_xfrm_drv *drv = sa->drv;
+
+	nss_ipsec_xfrm_info("%p: xfrm_state %p", sa, x);
+
+	atomic64_inc(&drv->stats.sa_dealloced);
+
+	/*
+	 * SA should always have an assoicated tunnel.
+	 */
+	BUG_ON(!sa->tun);
+
+	/*
+	 * Delete from ipsecmgr.
+	 */
+	nss_ipsecmgr_sa_del(sa->tun->dev, &sa->tuple);
+
+	/*
+	 * Only switch the value if it same for the current SA
+	 */
+	atomic_cmpxchg(&sa->tun->default_spi, sa->tuple.spi_index, 0);
+
+	/*
+	 * Refcnt was set to 1 when the sa object was created.
+	 * We are releasing the same here.
+	 */
+	nss_ipsec_xfrm_sa_deref(sa);
+}
+
+/*
+ * nss_ipsec_xfrm_sa_alloc()
+ *	Create a new SA object.
+ */
+struct nss_ipsec_xfrm_sa *nss_ipsec_xfrm_sa_alloc(struct nss_ipsec_xfrm_tunnel *tun, struct xfrm_state *x)
+{
+	struct nss_ipsec_xfrm_drv *drv = tun->drv;
+	struct nss_ipsec_xfrm_sa *sa;
+	nss_ipsecmgr_status_t status;
+	uint32_t if_num = 0;
+
+	sa = kzalloc(sizeof(struct nss_ipsec_xfrm_sa), GFP_KERNEL);
+	if (!sa) {
+		nss_ipsec_xfrm_err("%p: Failed to create v4 SA; Out of Memory\n", x);
+		return NULL;
+	}
+
+	atomic64_inc(&drv->stats.sa_alloced);
+
+	sa->drv = drv;
+	sa->tun = nss_ipsec_xfrm_tunnel_ref(tun);
+
+	kref_init(&sa->ref);
+	atomic_set(&sa->ecm_accel_outer, 0);
+
+	/*
+	 * Initialize the SA with common parameters
+	 */
+	nss_ipsec_xfrm_sa_init(sa, x);
+
+	/*
+	 * Derive crypto parameters
+	 */
+	if (!nss_ipsec_xfrm_sa_init_crypto(sa, x)) {
+		nss_ipsec_xfrm_err("%p: Failed to alloc SA; Invalid crypto params\n", sa);
+		goto error;
+	}
+
+	/*
+	 * Add it to the ipsecmgr
+	 */
+	status = nss_ipsecmgr_sa_add_sync(tun->dev, &sa->tuple, &sa->data, &if_num);
+	if ((status != NSS_IPSECMGR_OK) && (status != NSS_IPSECMGR_DUPLICATE_SA)) {
+		nss_ipsec_xfrm_err("%p: Failed to alloc SA; IPsec manager error(%d)\n", sa, status);
+		goto error;
+	}
+
+	/*
+	 * Override the default SPI index if the outer SA was sucessfully programmed
+	 * TODO: This only works if there is only one active outer SA per tunnel. Fix
+	 * the outer exception to store the SA that causes the exception.
+	 */
+	if (sa->type == NSS_IPSECMGR_SA_TYPE_DECAP) {
+		atomic_xchg(&tun->default_spi, sa->tuple.spi_index);
+	}
+
+	/*
+	 * Fetch SA related info from ipsecmgr; this should always succeed as we have
+	 * added a new SA
+	 */
+	status = nss_ipsecmgr_sa_get_info(tun->dev, &sa->tuple, &sa->sa_info);
+	BUG_ON(!status);
+	x->props.header_len = sa->sa_info.hdr_len;
+	x->props.trailer_len = sa->sa_info.trailer_len;
+
+	/*
+	 * Reset all key related references
+	 */
+	memset(&sa->data.cmn.keys, 0, sizeof(struct nss_ipsecmgr_crypto_keys));
+
+	nss_ipsec_xfrm_info("New SA created; src %pI4h dst %pI4h sport %d dport %d proto %d mode %d spi %x type %d\n",
+			sa->tuple.src_ip, sa->tuple.dest_ip, sa->tuple.sport, sa->tuple.dport, sa->tuple.proto_next_hdr,
+			x->props.mode, sa->tuple.spi_index, sa->type);
+
+	return sa;
+error:
+	nss_ipsec_xfrm_sa_deinit(x);
+	nss_ipsec_xfrm_sa_deref(sa);
+	return NULL;
+}
diff --git a/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_sa.h b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_sa.h
new file mode 100644
index 0000000..5a22707
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_sa.h
@@ -0,0 +1,55 @@
+/* Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_IPSEC_XFRM_SA_H
+#define __NSS_IPSEC_XFRM_SA_H
+
+/*
+ * Max replay_window size in bytes.
+ * The max window size suppoted by NSS is actually 48 bytes.
+ * We round it up to the next highest power of 2.
+ */
+#define NSS_IPSEC_XFRM_SA_MAX_REPLAY_WIN_SZ 64
+
+/*
+ * NSS IPSec xfrm SA obj
+ */
+struct nss_ipsec_xfrm_sa {
+	struct nss_ipsecmgr_sa_info sa_info;	/* Cached crypto information for this SA */
+	struct nss_ipsecmgr_sa_tuple tuple;	/* Cached SA tuple for this SA object*/
+	struct nss_ipsecmgr_sa_data data;	/* Cached SA parameters for this SA object */
+	struct nss_ipsec_xfrm_tunnel *tun; 	/* Reference to the parent tun object */
+	struct nss_ipsec_xfrm_drv *drv; 	/* Pointer to nss_ipsec_xfrm_drv */
+	enum nss_ipsecmgr_sa_type type;		/* Encap or decap */
+	atomic_t ecm_accel_outer;		/* Outer flow IPv4 rule is accelerated or not */
+	struct kref ref; 			/* Reference count */
+};
+
+void nss_ipsec_xfrm_sa_deref(struct nss_ipsec_xfrm_sa *sa);
+struct nss_ipsec_xfrm_sa *nss_ipsec_xfrm_sa_ref(struct nss_ipsec_xfrm_sa *sa);
+
+/*
+ * All these API(s) will hold the SA reference; once the usage is over the reference needs to
+ * be dropped
+ */
+struct nss_ipsec_xfrm_sa *nss_ipsec_xfrm_sa_ref_by_state(struct xfrm_state *x);
+struct nss_ipsec_xfrm_sa *nss_ipsec_xfrm_sa_ref_by_spi(uint32_t spi_index, uint32_t family);
+
+bool nss_ipsec_xfrm_sa_sp_set(struct nss_ipsec_xfrm_sa *sa, struct sk_buff *skb);
+
+void nss_ipsec_xfrm_sa_deinit(struct xfrm_state *x);
+void nss_ipsec_xfrm_sa_dealloc(struct nss_ipsec_xfrm_sa *sa, struct xfrm_state *x);
+struct nss_ipsec_xfrm_sa *nss_ipsec_xfrm_sa_alloc(struct nss_ipsec_xfrm_tunnel *tun, struct xfrm_state *x);
+#endif /* !__NSS_IPSEC_XFRM_SA_H */
diff --git a/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_tunnel.c b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_tunnel.c
new file mode 100644
index 0000000..018b2a6
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_tunnel.c
@@ -0,0 +1,371 @@
+/* Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/if.h>
+#include <linux/list.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <net/xfrm.h>
+#include <net/protocol.h>
+#include <linux/inetdevice.h>
+#include <net/addrconf.h>
+#include <linux/netfilter.h>
+
+#include <nss_api_if.h>
+#include <nss_ipsec.h>
+#include <nss_ipsecmgr.h>
+
+#include "nss_ipsec_xfrm_tunnel.h"
+#include "nss_ipsec_xfrm_sa.h"
+#include "nss_ipsec_xfrm_flow.h"
+#include "nss_ipsec_xfrm.h"
+
+/*
+ * nss_ipsec_xfrm_tunnel_free_work()
+ *	Tunnel Free work function.
+ */
+static void nss_ipsec_xfrm_tunnel_free_work(struct work_struct *work)
+{
+	struct nss_ipsec_xfrm_tunnel *tun = container_of(work, struct nss_ipsec_xfrm_tunnel, free_work);
+	struct nss_ipsec_xfrm_drv *drv = tun->drv;
+
+	/*
+	 * There should be no default_outer xfrm_state assoicated,
+	 * with a tunnel that is getting freed.
+	 */
+	BUG_ON(atomic_read(&tun->default_spi));
+	BUG_ON(!tun->dev);
+
+	nss_ipsec_xfrm_info("%p: free tunnel: nss_dev %s", tun, tun->dev->name);
+	nss_ipsecmgr_tunnel_del(tun->dev);
+
+	atomic64_inc(&drv->stats.tun_freed);
+
+	if (atomic_dec_and_test(&drv->num_tunnels)) {
+		complete(&drv->complete);
+	}
+
+	kfree(tun);
+}
+
+/*
+ * nss_ipsec_xfrm_tunnel_final()
+ *	Called when the last held reference to the tunnel is released.
+ */
+static void nss_ipsec_xfrm_tunnel_final(struct kref *kref)
+{
+	struct nss_ipsec_xfrm_tunnel *tun = container_of(kref, struct nss_ipsec_xfrm_tunnel, ref);
+	nss_ipsec_xfrm_trace("%p:Tunnel destroyed (%s) \n", tun, tun->dev->name);
+
+	schedule_work(&tun->free_work);
+}
+
+/*
+ * nss_ipsec_xfrm_tunnel_rx_inner(()
+ *	Inner exception callback
+ */
+static void nss_ipsec_xfrm_tunnel_rx_inner(void *app_data, struct sk_buff *skb)
+{
+	struct nss_ipsec_xfrm_tunnel *tun = app_data;
+	struct nss_ipsec_xfrm_sa *default_sa;
+	struct nss_ipsec_xfrm_drv *drv = tun->drv;
+
+	nss_ipsec_xfrm_trace("%p: Packet(%px) exceptioned after decapsulation; ip_version %d\n", tun, skb, ip_hdr(skb)->version);
+
+	/*
+	 * No secpath should be exisitng with the exception packet.
+	 * XXX Should we add a BUG_ON() here?
+	 */
+	if (secpath_exists(skb)) {
+		nss_ipsec_xfrm_err("%p: Exceptioned packet(%px) already has a SP loaded; dropping\n", tun, skb);
+		goto drop;
+
+	}
+
+	/*
+	 * sec_path is needed for IN/FWD IPSec policy check. sec_path needs the xfrm_state
+	 * that was used to decrypt the packet.
+	 * We feed the secpath with default_outer SA. Note that during rekey transition,
+	 * this might not be the actual SA that was used to decrypt this packet.
+	 * But it should be fine, as the old and new rekey SAs would share the same properties
+	 * and mode.
+	 */
+	default_sa = nss_ipsec_xfrm_sa_ref_by_spi(atomic_read(&tun->default_spi), tun->family);
+	if (!default_sa) {
+		nss_ipsec_xfrm_err("%p: Exceptioned packet(%px) no default_outer SA assoicated; dropping\n", tun, skb);
+		goto drop;
+	}
+
+	/*
+	 * Allocate and setup the SP in SKB
+	 */
+	if (!nss_ipsec_xfrm_sa_sp_set(default_sa, skb)) {
+		nss_ipsec_xfrm_err("%p: Failed to handle exception(%px) after decap; No SP(%p)\n", tun, skb, default_sa);
+		goto err;
+	}
+
+	atomic64_inc(&drv->stats.inner_except);
+	nss_ipsec_xfrm_sa_deref(default_sa);
+
+	netif_receive_skb(skb);
+	return;
+err:
+	nss_ipsec_xfrm_sa_deref(default_sa);
+drop:
+	atomic64_inc(&drv->stats.inner_drop);
+	dev_kfree_skb_any(skb);
+	return;
+}
+
+/*
+ * nss_ipsec_xfrm_tunnel_rx_outer()
+ *	Outer exception callback
+ */
+static void nss_ipsec_xfrm_tunnel_rx_outer(void *app_data, struct sk_buff *skb)
+{
+	int (*local_out)(struct net *, struct sock *, struct sk_buff *);
+	struct nss_ipsec_xfrm_tunnel *tun = app_data;
+	struct nss_ipsec_xfrm_drv *drv = tun->drv;
+	struct dst_entry *dst;
+
+	nss_ipsec_xfrm_trace("%p: Packet(%px) exceptioned after encapsulation; ip_version %d\n", tun, skb, ip_hdr(skb)->version);
+
+	if (ip_hdr(skb)->version == IPVERSION) {
+		struct iphdr *iph = ip_hdr(skb);
+
+		struct rtable *rt = ip_route_output(&init_net, iph->daddr, iph->saddr, 0, 0);
+		if (unlikely(IS_ERR(rt))) {
+			nss_ipsec_xfrm_warn("%px: Failed to handle ipv4 exception after encap; No route\n", skb);
+			goto drop;
+		}
+
+		dst = &rt->dst;
+		local_out = ip_local_out;
+		IPCB(skb)->flags |= IPSKB_XFRM_TRANSFORMED;
+	} else {
+		struct ipv6hdr *ip6h = ipv6_hdr(skb);
+		struct flowi6 fl6;
+
+		memset(&fl6, 0, sizeof(struct flowi6));
+		memcpy(&fl6.daddr, &ip6h->daddr, sizeof(fl6.daddr));
+		memcpy(&fl6.saddr, &ip6h->saddr, sizeof(fl6.saddr));
+
+		dst = ip6_route_output(&init_net, NULL, &fl6);
+		if (unlikely(IS_ERR(dst))) {
+			nss_ipsec_xfrm_warn("%px: Failed to handle ipv6 exception after encap; No route\n", skb);
+			goto drop;
+		}
+
+		local_out = ip6_local_out;
+		IP6CB(skb)->flags |= IP6SKB_XFRM_TRANSFORMED;
+	}
+
+	/*
+	 * Sets the 'dst' entry for SKB and sends the packet out directly to the physical
+	 * device associated with the IPsec tunnel interface.
+	 */
+	skb_dst_set(skb, dst);
+	skb->ip_summed = CHECKSUM_COMPLETE;
+
+	local_out(&init_net, NULL, skb);
+	atomic64_inc(&drv->stats.outer_except);
+	return;
+
+drop:
+	dev_kfree_skb_any(skb);
+	atomic64_inc(&drv->stats.outer_drop);
+	return;
+}
+
+/*
+ * nss_ipsec_xfrm_tunnel_proc_event()
+ *	NSS xfrm event cb registered with ipsecmgr
+ *	Used for syncing per-SA stats.
+ */
+static void nss_ipsec_xfrm_tunnel_proc_event(void *app_data, struct nss_ipsecmgr_event *event)
+{
+	struct nss_ipsec_xfrm_tunnel *tun =  app_data;
+
+	/*
+	 * We only handle stats event for now
+	 */
+	if (event->type != NSS_IPSECMGR_EVENT_SA_STATS) {
+		return;
+	}
+
+	nss_ipsec_xfrm_update_stats(tun->drv, &event->data.stats);
+}
+
+/*
+ * nss_ipsec_xfrm_tunnel_deref()
+ *	Put tunnel ref. Schedules free if the last reference was released.
+ *	Caller needs to hold the write lock, as this could be the last reference
+ *	that is getting put.
+ */
+void nss_ipsec_xfrm_tunnel_deref(struct nss_ipsec_xfrm_tunnel *tun)
+{
+	kref_put(&tun->ref, nss_ipsec_xfrm_tunnel_final);
+}
+
+/*
+ * nss_ipsec_xfrm_tunnel_ref
+ *	Hold tunnel ref.
+ */
+struct nss_ipsec_xfrm_tunnel * nss_ipsec_xfrm_tunnel_ref(struct nss_ipsec_xfrm_tunnel *tun)
+{
+	kref_get(&tun->ref);
+	return tun;
+}
+
+/*
+ * nss_ipsec_xfrm_tunnel_match()
+ *	Returns true if the supplied IP addreses matches the tunnel's
+ *	remote and local addresses
+ */
+bool nss_ipsec_xfrm_tunnel_match(struct nss_ipsec_xfrm_tunnel *tun, xfrm_address_t *l, xfrm_address_t *r, uint16_t family)
+{
+	uint8_t status = 0;
+
+	if (family == AF_INET) {
+		nss_ipsec_xfrm_trace("%p: family %d remote %pI4 local %pI4", tun, family, &r->a4, &l->a4);
+		status += (tun->local.a4 ^ l->a4);
+		status += (tun->remote.a4 ^ r->a4);
+		return !status;
+	}
+
+	nss_ipsec_xfrm_trace( "%p: family %d remote %pI6 local %pI6", tun, family, r->a6, l->a6);
+	status += xfrm6_addr_equal(&tun->local, l);
+	status += xfrm6_addr_equal(&tun->remote, r);
+	return !status;
+}
+
+/*
+ * nss_ipsec_xfrm_tunnel_dealloc()
+ *	Free a tunnel object.
+ */
+void nss_ipsec_xfrm_tunnel_dealloc(struct nss_ipsec_xfrm_tunnel *tun)
+{
+	struct nss_ipsec_xfrm_drv *drv = tun->drv;
+
+	atomic64_inc(&drv->stats.tun_dealloced);
+	nss_ipsec_xfrm_tunnel_deref(tun);
+}
+
+/*
+ * nss_ipsec_xfrm_tunnel_alloc()
+ *	Creates and initializes a new tunnel obj
+ */
+struct nss_ipsec_xfrm_tunnel *nss_ipsec_xfrm_tunnel_alloc(struct nss_ipsec_xfrm_drv *drv, xfrm_address_t *local,
+								xfrm_address_t *remote, uint16_t family)
+{
+	struct nss_ipsecmgr_callback ipsec_cb = {0};
+	struct nss_ipsec_xfrm_tunnel *tun;
+	struct rtable *rt;
+	struct rt6_info *rt6;
+	struct dst_entry *dst;
+	uint8_t ttl_hop_limit;
+	uint16_t overhead;
+	uint32_t mtu;
+
+	switch (family) {
+	case AF_INET:
+		 rt = ip_route_output(&init_net, remote->a4, 0, 0, 0);
+		 if (IS_ERR(rt)) {
+			 nss_ipsec_xfrm_err("%p:Failed to allocate tunnel; No IPv4 dst found\n", drv);
+			 return NULL;
+		 }
+
+		 dst = &rt->dst;
+		 ttl_hop_limit = ip4_dst_hoplimit(dst);
+		 overhead = NSS_IPSEC_XFRM_TUNNEL_V4_MAX_OVERHEAD;
+		 break;
+
+	case AF_INET6:
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		rt6 = rt6_lookup(&init_net, &remote->in6, NULL, 0, 0);
+#else
+		rt6 = rt6_lookup(&init_net, &remote->in6, NULL, 0, 0, 0);
+#endif
+		if (!rt6) {
+			nss_ipsec_xfrm_err("Failed to allocate tunnel; No IPv6 dst found\n");
+			return NULL;
+		}
+
+		dst = &rt6->dst;
+		ttl_hop_limit = ip6_dst_hoplimit(dst);
+		overhead = NSS_IPSEC_XFRM_TUNNEL_V6_MAX_OVERHEAD;
+		break;
+
+	default:
+		nss_ipsec_xfrm_err("%p:Failed to allocate tunnel; bad family type (%u)\n", drv, family);
+		return NULL;
+	}
+
+	mtu = dst_mtu(dst) - overhead;
+	dst_release(dst);
+
+	tun = kzalloc(sizeof(struct nss_ipsec_xfrm_tunnel), GFP_KERNEL);
+	if (!tun) {
+		nss_ipsec_xfrm_err("Failed to create tunnel; Out of memory\n");
+		return NULL;
+	}
+
+	ipsec_cb.except_cb = nss_ipsec_xfrm_tunnel_rx_outer;
+	ipsec_cb.data_cb = nss_ipsec_xfrm_tunnel_rx_inner;
+	ipsec_cb.event_cb = nss_ipsec_xfrm_tunnel_proc_event;
+	ipsec_cb.app_data = tun;
+
+	/*
+	 * Create IPsec manager tunnel netdevice
+	 */
+	tun->dev = nss_ipsecmgr_tunnel_add(&ipsec_cb);
+	if (!tun->dev) {
+		nss_ipsec_xfrm_err("%p: Failed to program tunnel(%p) in IPsec manager\n", drv, tun);
+		kfree(tun);
+		return NULL;
+	}
+
+	tun->ttl = ttl_hop_limit;
+	tun->family = family;
+	tun->drv = drv;
+
+	/*
+	 * Copy the addresses for future comparision
+	 */
+	memcpy(&tun->remote, remote, sizeof(xfrm_address_t));
+	memcpy(&tun->local, local, sizeof(xfrm_address_t));
+
+	/*
+	 * Tunnel reference held; will be released in free or deref
+	 */
+	kref_init(&tun->ref);
+	atomic64_inc(&drv->stats.tun_alloced);
+	atomic_inc(&drv->num_tunnels);
+	INIT_WORK(&tun->free_work, nss_ipsec_xfrm_tunnel_free_work);
+
+	/*
+	 * Update the tunnel MTU for NSS netdevice
+	 */
+	rtnl_lock();
+	dev_set_mtu(tun->dev, mtu);
+	rtnl_unlock();
+
+	nss_ipsec_xfrm_trace("%p: XFRM offload tunnel created\n", tun);
+	return tun;
+}
diff --git a/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_tunnel.h b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_tunnel.h
new file mode 100644
index 0000000..0be258d
--- /dev/null
+++ b/qca-nss-clients/ipsecmgr/v2.0/plugins/xfrm/nss_ipsec_xfrm_tunnel.h
@@ -0,0 +1,62 @@
+/* Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_IPSEC_XFRM_TUNNEL_H
+#define __NSS_IPSEC_XFRM_TUNNEL_H
+
+/*
+ * 20(IPv4 Header) + 8(ESP Header) + 16(Max IV len) + 8(UDP header for NATT tunnels) +
+ * 2(NSS_IPSECMGR_ESP_TRAIL_SZ) + 14(NSS_IPSECMGR_ESP_PAD_SZ) + 16(Max ICV len).
+ */
+#define NSS_IPSEC_XFRM_TUNNEL_V4_MAX_OVERHEAD 84
+
+/*
+ * 40(IPv6 Header) + 8(ESP Header) + 16(Max IV len) + 2(NSS_IPSECMGR_ESP_TRAIL_SZ) +
+ * 14(NSS_IPSECMGR_ESP_PAD_SZ) + 16(Max ICV len).
+ */
+#define NSS_IPSEC_XFRM_TUNNEL_V6_MAX_OVERHEAD 96
+
+/*
+ * Forward Declarations
+ */
+struct nss_ipsec_xfrm_drv;
+struct nss_ipsec_xfrm_sa;
+
+/*
+ * NSS IPSec xfrm Tunnel obj
+ */
+struct nss_ipsec_xfrm_tunnel {
+	struct nss_ipsec_xfrm_drv *drv;		/* Pointer to IPSec xfrm plugin instance */
+	struct work_struct free_work;		/* Tunnel free work */
+	struct list_head list_entry;		/* Hash DB entry */
+	struct net_device *dev;			/* Pointer to corrosponding NSS device */
+
+	xfrm_address_t remote;			/* Remote endpoint Address in networks order */
+	xfrm_address_t local;			/* Local endpoint Address in network order */
+	atomic_t default_spi;			/* spi idx for the default outer SA */
+
+	struct kref ref;			/* Ref Count */
+	uint16_t family;			/* AF_INET or AF_INET6 */
+	atomic_t num_sa;			/* Number of Active SAs */
+	uint8_t ttl;				/* TTL or hop limit for this tunnel */
+};
+
+void nss_ipsec_xfrm_tunnel_deref(struct nss_ipsec_xfrm_tunnel *tun);
+struct nss_ipsec_xfrm_tunnel *nss_ipsec_xfrm_tunnel_ref(struct nss_ipsec_xfrm_tunnel *tun);
+bool nss_ipsec_xfrm_tunnel_match(struct nss_ipsec_xfrm_tunnel *tun, xfrm_address_t *l, xfrm_address_t *r, uint16_t family);
+void nss_ipsec_xfrm_tunnel_dealloc(struct nss_ipsec_xfrm_tunnel *tun);
+struct nss_ipsec_xfrm_tunnel *nss_ipsec_xfrm_tunnel_alloc(struct nss_ipsec_xfrm_drv *ctx, xfrm_address_t *l,
+							xfrm_address_t *r, uint16_t family);
+#endif /* !__NSS_IPSEC_XFRM_TUNNEL_H */
diff --git a/qca-nss-clients/l2tp/l2tpv2/Makefile b/qca-nss-clients/l2tp/l2tpv2/Makefile
new file mode 100644
index 0000000..b6076d3
--- /dev/null
+++ b/qca-nss-clients/l2tp/l2tpv2/Makefile
@@ -0,0 +1,9 @@
+# Makefile for l2tp client
+ccflags-y += -I$(obj)/../../exports -I$(obj)/../..  -I$(obj)/nss_hal/include
+ccflags-y += -DNSS_L2TP_DEBUG_LEVEL=0
+ccflags-y += -Wall -Werror
+ifneq (,$(filter $(CONFIG_L2TP),m y))
+obj-m += qca-nss-l2tpv2.o
+qca-nss-l2tpv2-objs := nss_connmgr_l2tpv2.o nss_l2tpv2_stats.o
+endif
+
diff --git a/qca-nss-clients/l2tp/l2tpv2/nss_connmgr_l2tpv2.c b/qca-nss-clients/l2tp/l2tpv2/nss_connmgr_l2tpv2.c
new file mode 100644
index 0000000..68246f0
--- /dev/null
+++ b/qca-nss-clients/l2tp/l2tpv2/nss_connmgr_l2tpv2.c
@@ -0,0 +1,1077 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2017, 2019-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_connnmgr_l2tpv2.c
+ *
+ * This file is the NSS l2tpv2 tunnel module
+ */
+
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/rcupdate.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <net/ipv6.h>
+#include <linux/rwlock_types.h>
+#include <linux/if_pppox.h>
+#include <linux/hashtable.h>
+#include <linux/inetdevice.h>
+#include <linux/l2tp.h>
+#include <linux/if_arp.h>
+#include <linux/version.h>
+#include <linux/sysctl.h>
+#include <net/route.h>
+#include <linux/refcount.h>
+#include <linux/../../net/l2tp/l2tp_core.h>
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+#include "nss_connmgr_l2tpv2.h"
+#include "nss_l2tpv2_stats.h"
+#include "nss_l2tpmgr.h"
+
+#define L2TP_HDRFLAG_T     0x8000
+#define L2TP_HDRFLAG_L     0x4000
+#define L2TP_HDRFLAG_S     0x0800
+#define L2TP_HDRFLAG_O     0x0200
+#define L2TP_HDRFLAG_P     0x0100
+#define L2TP_HDR_MIN_LEN   6
+#define PPP_HDR_LEN        4
+#define BYTES_PER_SHORT    2
+
+/*
+ * NSS l2tpv2 debug macros
+ */
+#if (NSS_L2TP_DEBUG_LEVEL < 1)
+#define nss_connmgr_l2tpv2_assert(fmt, args...)
+#else
+#define nss_connmgr_l2tpv2_assert(c)  BUG_ON(!(c));
+#endif
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_connmgr_l2tpv2_warning(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_connmgr_l2tpv2_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_connmgr_l2tpv2_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_L2TP_DEBUG_LEVEL < 2)
+#define nss_connmgr_l2tpv2_warning(s, ...)
+#else
+#define nss_connmgr_l2tpv2_warning(s, ...) pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_L2TP_DEBUG_LEVEL < 3)
+#define nss_connmgr_l2tpv2_info(s, ...)
+#else
+#define nss_connmgr_l2tpv2_info(s, ...)   pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_L2TP_DEBUG_LEVEL < 4)
+#define nss_connmgr_l2tpv2_trace(s, ...)
+#else
+#define nss_connmgr_l2tpv2_trace(s, ...)  pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif
+
+#define NUM_L2TP_CHANNELS_IN_PPP_NETDEVICE  1
+#define HASH_BUCKET_SIZE 2  /* ( 2^ HASH_BUCKET_SIZE ) == 4 */
+#define L2TP_SYSCTL_STR_LEN_MAX 2*IFNAMSIZ + 1 /* Size is determined to accomodate two netdevice names and a space in between */
+
+static DEFINE_HASHTABLE(l2tpv2_session_data_hash_table, HASH_BUCKET_SIZE);
+static int ip_ttl_max = 255;
+
+#if defined(NSS_L2TP_IPSEC_BIND_BY_NETDEV)
+static char l2tpoipsec_config[L2TP_SYSCTL_STR_LEN_MAX];
+static struct ctl_table_header *ctl_tbl_hdr; /* l2tpv2 sysctl */
+#endif
+static struct l2tpmgr_ipsecmgr_cb __rcu ipsecmgr_cb;
+
+/*
+ * nss_connmgr_l2tpv2_msg_cb()
+ *	L2TP message callback.
+ */
+static void nss_connmgr_l2tpv2_msg_cb(void *app_data, struct nss_l2tpv2_msg *msg) {
+	struct nss_cmn_msg *ncm = &msg->cm;
+	if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+		nss_connmgr_l2tpv2_warning("Recevied NACK for L2TP message type = %d from NSS\n", ncm->type);
+	}
+
+	nss_connmgr_l2tpv2_trace("Recevied ACK for L2TP message type = %d from NSS\n", ncm->type);
+}
+
+/*
+ * nss_connmgr_l2tpv2_get_session()
+ *	retrieve ppp over l2tpv2 session associated with this netdevice if any
+ *
+ */
+static struct l2tp_session *nss_connmgr_l2tpv2_get_session(struct net_device *dev)
+{
+	struct ppp_channel *ppp_chan[1] = {NULL};
+	int px_proto;
+	struct sock *sk;
+	struct l2tp_session *session = NULL;
+
+	/*
+	 * check whether the interface is of type PPP
+	 */
+	if (dev->type != ARPHRD_PPP || !(dev->flags & IFF_POINTOPOINT)) {
+		nss_connmgr_l2tpv2_info("netdevice is not a PPP tunnel type\n");
+		return NULL;
+	}
+
+	if (ppp_is_multilink(dev)) {
+		nss_connmgr_l2tpv2_info("channel is multilink PPP\n");
+		return NULL;
+	}
+
+	if (ppp_hold_channels(dev, ppp_chan, 1) != 1) {
+		nss_connmgr_l2tpv2_info("hold channel for netdevice failed\n");
+		return NULL;
+	}
+
+	if (!ppp_chan[0]) {
+		nss_connmgr_l2tpv2_info("channel don't have a ppp_channel\n");
+		goto err_nss_connmgr_l2tpv2_get_session_1;
+	}
+
+	px_proto = ppp_channel_get_protocol(ppp_chan[0]);
+	if (px_proto != PX_PROTO_OL2TP) {
+		nss_connmgr_l2tpv2_info("session socket is not of type PX_PROTO_OL2TP\n");
+		goto err_nss_connmgr_l2tpv2_get_session_1;
+	}
+
+	sk = (struct sock *)ppp_chan[0]->private;
+	if (!sk) {
+		nss_connmgr_l2tpv2_info("session socket is NULL\n");
+		goto err_nss_connmgr_l2tpv2_get_session_1;
+	}
+	sock_hold(sk);
+
+	/*
+	 * This is very unlikely, But check the socket is connected state
+	 */
+	if (unlikely(sock_flag(sk, SOCK_DEAD) || !(sk->sk_state & PPPOX_CONNECTED))) {
+		nss_connmgr_l2tpv2_info("l2tpv2 session sock is either dead or not in connected state\n");
+		goto err_nss_connmgr_l2tpv2_get_session_2;
+	}
+
+	session = (struct l2tp_session *)(sk->sk_user_data);
+	if (!session) {
+		nss_connmgr_l2tpv2_info("l2tpv2 session is null\n");
+		goto err_nss_connmgr_l2tpv2_get_session_2;
+	}
+
+	session_hold(session);
+
+err_nss_connmgr_l2tpv2_get_session_2:
+	sock_put(sk);
+
+err_nss_connmgr_l2tpv2_get_session_1:
+	ppp_release_channels(ppp_chan, 1);
+	return session;
+}
+
+/*
+ * nss_connmgr_l2tpv2_get_all_proto_data()
+ *	get all information on ppp, l2tpv2, udp and ip protocol
+ */
+static struct nss_connmgr_l2tpv2_session_data
+*nss_connmgr_l2tpv2_get_all_proto_data(struct net_device *dev,
+				       struct l2tp_session *session)
+{
+	struct nss_connmgr_l2tpv2_session_data *l2tpv2_session_data = NULL;
+	struct l2tp_tunnel *tunnel = NULL;
+	struct inet_sock *inet;
+	struct nss_connmgr_l2tpv2_data *data;
+	struct udp_sock *udp;
+
+	l2tpv2_session_data = kmalloc(sizeof(struct nss_connmgr_l2tpv2_session_data),
+				      GFP_KERNEL);
+	if (!l2tpv2_session_data) {
+		nss_connmgr_l2tpv2_info("failed to allocate l2tpv2_session_data\n");
+		session_put(session);
+		return NULL;
+	}
+
+	tunnel = session->tunnel;
+	if (unlikely(!tunnel)) {
+		nss_connmgr_l2tpv2_info("tunnel is null for session %px\n", session);
+		goto err_nss_connmgr_l2tpv2_get_data_1;
+	}
+	tunnel_hold(tunnel);
+
+	data = &l2tpv2_session_data->data;
+
+	if (tunnel->version != L2TP_V_2)  {
+		nss_connmgr_l2tpv2_info("l2tp version is not 2\n");
+		goto err_nss_connmgr_l2tpv2_get_data_2;
+	}
+
+	if (!tunnel->sock) {
+		nss_connmgr_l2tpv2_info("tunnel sock is NULL\n");
+		goto err_nss_connmgr_l2tpv2_get_data_2;
+	}
+	sock_hold(tunnel->sock);
+
+	/*
+	 * Get Tunnel Info
+	 */
+	data->l2tpv2.tunnel.tunnel_id = tunnel->tunnel_id;
+	data->l2tpv2.tunnel.peer_tunnel_id = tunnel->peer_tunnel_id;
+
+	nss_connmgr_l2tpv2_info("vers=%u tun id=%u peer_id=%u ncap=%u\n",
+	       tunnel->version, tunnel->tunnel_id,
+	       tunnel->peer_tunnel_id,  tunnel->encap);
+	/*
+	 * Get session info
+	 */
+	data->l2tpv2.session.session_id = session->session_id;
+	data->l2tpv2.session.peer_session_id = session->peer_session_id;
+	data->l2tpv2.session.hdr_len = session->hdr_len;
+	data->l2tpv2.session.reorder_timeout = session->reorder_timeout;
+	data->l2tpv2.session.recv_seq = session->recv_seq;
+	data->l2tpv2.session.send_seq = session->send_seq;
+
+	nss_connmgr_l2tpv2_info("sess %u, peer=%u nr=%u ns=%u hdr_len=%u timeout=%x"
+	       " recv_seq=%x send_seq=%x\n",
+	       session->session_id,  session->peer_session_id, session->nr,
+	       session->ns, session->hdr_len,
+	       session->reorder_timeout, session->recv_seq,
+	       session->send_seq);
+
+	/*
+	 * tunnel->sock->sk_no_check/sk_no_check_tx is set to true
+	 * if UDP checksum is not needed for the L2TP socket.
+	 */
+	data->l2tpv2.tunnel.udp_csum = !tunnel->sock->sk_no_check_tx;
+
+	inet = inet_sk(tunnel->sock);
+
+	/*
+	 * UDP header exist ?
+	 */
+	if (tunnel->encap != L2TP_ENCAPTYPE_UDP) {
+		nss_connmgr_l2tpv2_info("encap type is not UDP\n");
+		goto err_nss_connmgr_l2tpv2_get_data_3;
+
+	}
+
+	if (tunnel->sock->sk_protocol != IPPROTO_UDP) {
+		nss_connmgr_l2tpv2_info("Wrong protocol %u\n",
+				       tunnel->sock->sk_protocol);
+		goto err_nss_connmgr_l2tpv2_get_data_3;
+	}
+
+	if (tunnel->sock->sk_state != TCP_ESTABLISHED) {
+		nss_connmgr_l2tpv2_info("Udp socket is not in established" \
+				       " state %u\n", tunnel->sock->sk_state);
+		goto err_nss_connmgr_l2tpv2_get_data_3;
+	}
+
+	udp = udp_sk(tunnel->sock);
+	if (!udp) {
+		nss_connmgr_l2tpv2_info("There is no udp socket !!! ?\n");
+		goto err_nss_connmgr_l2tpv2_get_data_3;
+	}
+
+	data->udp.dport = inet->inet_dport;
+	data->udp.sport = inet->inet_sport;
+
+	nss_connmgr_l2tpv2_info("udp sport=0x%x dport=0x%x\n", ntohs(inet->inet_sport), ntohs(inet->inet_dport));
+
+	/*
+	 * ip data
+	 */
+	if (inet->sk.sk_family == AF_INET) {
+		data->ip.v4.saddr.s_addr = inet->inet_saddr;
+		data->ip.v4.daddr.s_addr = inet->inet_daddr;
+	} else {
+		nss_connmgr_l2tpv2_info("Only Ipv4 protocol supports l2tpv2 packet's outer IP\n");
+		goto err_nss_connmgr_l2tpv2_get_data_3;
+	}
+
+	nss_connmgr_l2tpv2_info("saddr 0x%x daddr = 0x%x\n",  ntohl(inet->inet_saddr), ntohl(inet->inet_daddr));
+
+	/*
+	 * fill in extra data. This can be used to get reference to
+	 * netdevice
+	 */
+	dev_hold(dev);
+	l2tpv2_session_data->dev = dev;
+	strlcpy(session->ifname, dev->name, IFNAMSIZ);
+
+	/*
+	 * There is no need for protecting simultaneous addition &
+	 * deletion of l2tpv2_session_data as all netdev notifier chain
+	 * call back is called  with rtln mutex lock.
+	 */
+	hash_add_rcu(l2tpv2_session_data_hash_table,
+		     &l2tpv2_session_data->hash_list,
+		     dev->ifindex);
+
+	sock_put(tunnel->sock);
+	tunnel_put(tunnel);
+	session_put(session);
+	return l2tpv2_session_data;
+
+err_nss_connmgr_l2tpv2_get_data_3:
+	sock_put(tunnel->sock);
+
+err_nss_connmgr_l2tpv2_get_data_2:
+	tunnel_put(tunnel);
+
+err_nss_connmgr_l2tpv2_get_data_1:
+	kfree(l2tpv2_session_data);
+	session_put(session);
+	return NULL;
+}
+
+/*
+ * nss_connmgr_l2tpv2_exception()
+ *	Exception handler registered to NSS for handling l2tpv2 pkts
+ *
+ */
+static void nss_connmgr_l2tpv2_exception(struct net_device *dev,
+				       struct sk_buff *skb,
+				       __attribute__((unused)) struct napi_struct *napi)
+
+{
+	const struct iphdr *iph_outer, *iph_inner;
+	struct nss_connmgr_l2tpv2_session_data *ptr;
+	uint16_t *l2tp_hdr;
+	uint16_t l2tp_flags;
+	int l2tp_hdr_len = L2TP_HDR_MIN_LEN;
+	__be32 tunnel_local_ip;
+	struct rtable *rt;
+	struct net_device *in_dev;
+
+	/* discard L2 header */
+	skb_pull(skb, sizeof(struct ethhdr));
+	skb_reset_mac_header(skb);
+
+	iph_outer = (const struct iphdr *)skb->data;
+
+	rcu_read_lock();
+	hash_for_each_possible_rcu(l2tpv2_session_data_hash_table, ptr,
+				   hash_list, dev->ifindex) {
+		if (ptr->dev == dev) {
+			tunnel_local_ip = ptr->data.ip.v4.saddr.s_addr;
+			rcu_read_unlock();
+
+			if (iph_outer->version == 4 && iph_outer->saddr == tunnel_local_ip) { /*pkt is encapsulated */
+				skb_pull(skb, sizeof(struct iphdr));
+				skb_pull(skb, sizeof(struct udphdr));
+				l2tp_hdr = (uint16_t *)skb->data;
+				l2tp_flags = ntohs(*l2tp_hdr);
+				if (unlikely(l2tp_flags & L2TP_HDRFLAG_L)) {
+					l2tp_hdr_len += 2;
+				}
+				if (unlikely(l2tp_flags & L2TP_HDRFLAG_S)) {
+					l2tp_hdr_len += 4;
+				}
+				if (unlikely(l2tp_flags & L2TP_HDRFLAG_O)) {
+					uint16_t  offset_pad = ntohs(*(l2tp_hdr + l2tp_hdr_len/BYTES_PER_SHORT));
+					l2tp_hdr_len += 2 + offset_pad;
+				}
+
+				skb_pull(skb, l2tp_hdr_len); /* pull l2tp header */
+				skb_pull(skb, PPP_HDR_LEN);  /* pull ppp header */
+
+				iph_inner = (const struct iphdr *)skb->data;
+				if (iph_inner->version == 4) {
+					skb->protocol = htons(ETH_P_IP);
+				} else if (iph_inner->version == 6) {
+					skb->protocol = htons(ETH_P_IPV6);
+				} else {
+					nss_connmgr_l2tpv2_warning("not able to handle this pkt, so freeing\n");
+					dev_kfree_skb_any(skb);
+					return;
+				}
+				skb_reset_network_header(skb);
+				skb_reset_transport_header(skb);
+				skb->ip_summed = CHECKSUM_NONE;
+				skb->pkt_type = PACKET_HOST;
+				skb->dev = dev;
+
+				/*
+				 * set skb_iif
+				 */
+				rt = ip_route_output(&init_net, iph_inner->saddr, 0, 0, 0);
+				if (unlikely(IS_ERR(rt))) {
+					nss_connmgr_l2tpv2_warning("Martian packets !!!");
+				} else {
+					in_dev = rt->dst.dev;
+					ip_rt_put(rt);
+					if (likely(in_dev)) {
+						skb->skb_iif = in_dev->ifindex;
+					} else {
+						nss_connmgr_l2tpv2_warning("could not find incoming interface\n");
+					}
+				}
+
+				dev_queue_xmit(skb);
+				return;
+
+			} else  { /* pkt is decapsulated */
+				if (iph_outer->version == 4) {
+					skb->protocol = htons(ETH_P_IP);
+				} else if (iph_outer->version == 6) {
+					skb->protocol = htons(ETH_P_IPV6);
+				} else {
+					nss_connmgr_l2tpv2_info("pkt may be a control packet\n");
+				}
+				skb_reset_network_header(skb);
+				skb->pkt_type = PACKET_HOST;
+				skb->skb_iif = dev->ifindex;
+				skb->ip_summed = CHECKSUM_NONE;
+				skb->dev = dev;
+				netif_receive_skb(skb);
+				return;
+			}
+		}
+	}
+	rcu_read_unlock();
+
+	nss_connmgr_l2tpv2_warning("not able to handle this pkt, so freeing\n");
+	dev_kfree_skb_any(skb);
+}
+
+/*
+ * nss_connmgr_l2tpv2_event_receive()
+ *	Event Callback to receive events from NSS
+ */
+static void nss_connmgr_l2tpv2_event_receive(void *if_ctx, struct nss_l2tpv2_msg *tnlmsg)
+{
+	struct net_device *netdev = if_ctx;
+
+	switch (tnlmsg->cm.type) {
+	case NSS_L2TPV2_MSG_SYNC_STATS:
+		nss_l2tpv2_update_dev_stats(netdev, (struct nss_l2tpv2_sync_session_stats_msg *)&tnlmsg->msg.stats);
+		break;
+
+	default:
+		nss_connmgr_l2tpv2_info("Unknown Event from NSS\n");
+		break;
+	}
+}
+
+/*
+ * nss_connmgr_l2tpv2_bind_ipsec_by_ipaddr()
+ * 	Bind L2TP tunnel with IPsec(xfrm) based on IP Address
+ */
+static void nss_connmgr_l2tpv2_bind_ipsec_by_ipaddr(struct nss_ctx_instance *nss_ctx, struct nss_connmgr_l2tpv2_data *l2tpv2_data, uint32_t l2tp_ifnum)
+{
+	struct nss_l2tpv2_msg l2tpv2msg;
+	nss_tx_status_t status;
+	struct nss_l2tpv2_bind_ipsec_if_msg *l2tpv2_bind_ipsec_msg;
+	int32_t ipsec_ifnum;
+	get_ipsec_ifnum_by_ipv4_addr_callback_t ipsec_cb;
+
+	/*
+	 * Check if the L2TP interface is applied over an IPsec (XFRM) interface by querying the IPsec
+	 * client by using the L2TP tunnel IPv4 source/destination addresses.
+	 */
+	rcu_read_lock();
+	ipsec_cb = rcu_dereference(ipsecmgr_cb.get_ifnum_by_ipv4_addr);
+	if (!ipsec_cb) {
+		rcu_read_unlock();
+		nss_connmgr_l2tpv2_info("%px: IPsec get_ifnum_by_ipv4_addr callback is not registered\n", nss_ctx);
+		return;
+	}
+
+	ipsec_ifnum = ipsec_cb(&l2tpv2_data->ip.v4.saddr.s_addr, &l2tpv2_data->ip.v4.daddr.s_addr);
+	rcu_read_unlock();
+
+	if (ipsec_ifnum < 0) {
+		nss_connmgr_l2tpv2_info("%px: Invalid IPsec interface no.(0x%x) based on local & remote IP-address\n", nss_ctx, ipsec_ifnum);
+		return;
+	}
+
+	/*
+	 * For, l2tpoipsec, send the command to bind the l2tp session with the IPsec interface.
+	 */
+	memset(&l2tpv2msg, 0, sizeof(struct nss_l2tpv2_msg));
+	nss_l2tpv2_msg_init(&l2tpv2msg, l2tp_ifnum, NSS_L2TPV2_MSG_BIND_IPSEC_IF,
+			sizeof(struct nss_l2tpv2_bind_ipsec_if_msg), (void *)nss_connmgr_l2tpv2_msg_cb, NULL);
+	l2tpv2_bind_ipsec_msg = &l2tpv2msg.msg.bind_ipsec_if_msg;
+	l2tpv2_bind_ipsec_msg->ipsec_ifnum = ipsec_ifnum;
+
+	status = nss_l2tpv2_tx(nss_ctx, &l2tpv2msg);
+	if (status != NSS_TX_SUCCESS) {
+		/*
+		 * TODO: Add retry logic. Currently it sends a warning message to user.
+		 * In case of bind fails, then we don't bring down L2TP tunnel, instead we give a warning log
+		 * to user, as this introduces a potential risk of not having a per packet check for source
+		 * interface number in firmware.
+		 */
+		nss_connmgr_l2tpv2_warning("%px: L2TPv2 interface binding with IPSec interface(0x%x) failed.\n", nss_ctx, ipsec_ifnum);
+		return;
+	}
+
+	nss_connmgr_l2tpv2_info("%px: L2TPv2 interface is bound to IPsec interface with if_num(0x%x)\n", nss_ctx, ipsec_ifnum);
+}
+
+/*
+ * nss_connmgr_l2tpv2_dev_up()
+ *	pppol2tpv2 interface's up event handler
+ */
+static int nss_connmgr_l2tpv2_dev_up(struct net_device *dev)
+{
+	uint32_t if_number;
+	struct l2tp_session *session = NULL;
+	struct nss_connmgr_l2tpv2_session_data *l2tpv2_session_data = NULL;
+	struct nss_connmgr_l2tpv2_data *data;
+	nss_tx_status_t status;
+	struct nss_ctx_instance *nss_ctx;
+	uint32_t features = 0; /* features denote the skb types supported by this interface */
+	struct nss_l2tpv2_msg  l2tpv2msg;
+	struct nss_l2tpv2_session_create_msg *l2tpv2cfg;
+
+	session = nss_connmgr_l2tpv2_get_session(dev);
+	if (!session) {
+		return NOTIFY_DONE;
+	}
+
+	l2tpv2_session_data = nss_connmgr_l2tpv2_get_all_proto_data(dev, session);
+	if (l2tpv2_session_data  == NULL) {
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Create nss dynamic interface and register
+	 */
+	if_number = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_L2TPV2);
+	if (if_number == -1) {
+		nss_connmgr_l2tpv2_info("Request interface number failed\n");
+		return NOTIFY_DONE;
+	}
+	nss_connmgr_l2tpv2_info("nss_dynamic_interface_alloc_node() sucessful. if_number = %d\n", if_number);
+
+	if (!nss_is_dynamic_interface(if_number)) {
+		nss_connmgr_l2tpv2_warning("Invalid NSS dynamic I/F number %d\n", if_number);
+		return NOTIFY_BAD;
+	}
+
+	/*
+	 * Register l2tpv2  tunnel with NSS
+	 */
+	nss_ctx = nss_register_l2tpv2_if(if_number,
+				       nss_connmgr_l2tpv2_exception,
+				       nss_connmgr_l2tpv2_event_receive,
+				       dev,
+				       features);
+
+	if (!nss_ctx) {
+		status = nss_dynamic_interface_dealloc_node(if_number, NSS_DYNAMIC_INTERFACE_TYPE_L2TPV2);
+		if (status != NSS_TX_SUCCESS) {
+			nss_connmgr_l2tpv2_info("Unable to dealloc the node[%d] in the NSS fw!\n", if_number);
+		}
+		nss_connmgr_l2tpv2_info("nss_register_l2tpv2_if failed\n");
+		return NOTIFY_BAD;
+	}
+	nss_connmgr_l2tpv2_info("%px: nss_register_l2tpv2_if() successful\n", nss_ctx);
+
+	data = &l2tpv2_session_data->data;
+
+	memset(&l2tpv2msg, 0, sizeof(struct nss_l2tpv2_msg));
+	l2tpv2cfg = &l2tpv2msg.msg.session_create_msg;
+	l2tpv2cfg->local_tunnel_id = data->l2tpv2.tunnel.tunnel_id;
+	l2tpv2cfg->peer_tunnel_id = data->l2tpv2.tunnel.peer_tunnel_id;
+	l2tpv2cfg->local_session_id = data->l2tpv2.session.session_id;
+	l2tpv2cfg->peer_session_id = data->l2tpv2.session.peer_session_id;
+	l2tpv2cfg->sip = ntohl(data->ip.v4.saddr.s_addr);
+	l2tpv2cfg->dip = ntohl(data->ip.v4.daddr.s_addr);
+	l2tpv2cfg->reorder_timeout = jiffies_to_msecs(data->l2tpv2.session.reorder_timeout);
+	l2tpv2cfg->sport = ntohs(data->udp.sport);
+	l2tpv2cfg->dport = ntohs(data->udp.dport);
+
+	/*
+	 *  all other fields
+	 */
+	l2tpv2cfg->recv_seq = data->l2tpv2.session.recv_seq;
+	l2tpv2cfg->oip_ttl = ip_ttl_max;
+	l2tpv2cfg->udp_csum = data->l2tpv2.tunnel.udp_csum;
+
+	nss_connmgr_l2tpv2_info("%px: l2tpv2 info\n", nss_ctx);
+	nss_connmgr_l2tpv2_info("%px: tunnel_id %d peer_tunnel_id %d session_id %d peer_session_id %d\n", nss_ctx,
+											l2tpv2cfg->local_tunnel_id,
+											l2tpv2cfg->peer_tunnel_id,
+											l2tpv2cfg->local_session_id,
+											l2tpv2cfg->peer_session_id);
+	nss_connmgr_l2tpv2_info("%px: saddr 0x%x daddr 0x%x sport 0x%x  dport 0x%x\n", nss_ctx,
+									l2tpv2cfg->sip, l2tpv2cfg->dip, l2tpv2cfg->sport, l2tpv2cfg->dport);
+	nss_connmgr_l2tpv2_info("Sending l2tpv2 i/f up command to NSS %px\n", nss_ctx);
+
+	nss_l2tpv2_msg_init(&l2tpv2msg, if_number, NSS_L2TPV2_MSG_SESSION_CREATE, sizeof(struct nss_l2tpv2_session_create_msg), NULL, NULL);
+
+	status = nss_l2tpv2_tx(nss_ctx, &l2tpv2msg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_unregister_l2tpv2_if(if_number);
+		status = nss_dynamic_interface_dealloc_node(if_number, NSS_DYNAMIC_INTERFACE_TYPE_L2TPV2);
+		if (status != NSS_TX_SUCCESS) {
+			nss_connmgr_l2tpv2_warning("%px: Unable to dealloc the node[%d] in the NSS fw!\n", nss_ctx, if_number);
+		}
+		nss_connmgr_l2tpv2_warning("%px: nss l2tp session creation command error %d\n", nss_ctx, status);
+		return NOTIFY_BAD;
+	}
+
+	nss_connmgr_l2tpv2_info("%px: nss_l2tpv2_tx() CREATE successful\n", nss_ctx);
+
+	/*
+	 * Check if we need to bind the L2TP to an IPsec interface. This is required as per RFC3193
+	 */
+	nss_connmgr_l2tpv2_bind_ipsec_by_ipaddr(nss_ctx, data, if_number);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_connmgr_l2tpv2_dev_down()
+ *	pppol2tpv2 interface's down event handler
+ */
+static int nss_connmgr_l2tpv2_dev_down(struct net_device *dev)
+{
+	struct nss_connmgr_l2tpv2_session_data *ptr;
+	struct hlist_node *tmp;
+	struct nss_l2tpv2_msg  l2tpv2msg;
+	struct nss_l2tpv2_session_destroy_msg *l2tpv2cfg;
+	int if_number;
+	nss_tx_status_t status;
+
+	/*
+	 * check whether the interface is of type PPP
+	 */
+	if (dev->type != ARPHRD_PPP || !(dev->flags & IFF_POINTOPOINT)) {
+		nss_connmgr_l2tpv2_info("netdevice is not a l2tpv2/l2tpv3 tunnel type\n");
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Check if l2tpv2 is registered ?
+	 */
+	if_number = nss_cmn_get_interface_number_by_dev(dev);
+	if (if_number < 0) {
+		nss_connmgr_l2tpv2_info("Net device:%px is not registered with nss\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	hash_for_each_possible_safe(l2tpv2_session_data_hash_table, ptr,
+				    tmp, hash_list, dev->ifindex) {
+		if (ptr->dev == dev) {
+			dev_put(dev);
+			hash_del_rcu(&ptr->hash_list);
+			synchronize_rcu();
+
+			memset(&l2tpv2msg, 0, sizeof(struct nss_l2tpv2_msg));
+			l2tpv2cfg = &l2tpv2msg.msg.session_destroy_msg;
+			l2tpv2cfg->local_tunnel_id = ptr->data.l2tpv2.tunnel.tunnel_id;
+			l2tpv2cfg->local_session_id = ptr->data.l2tpv2.session.session_id;
+			kfree(ptr);
+
+			nss_l2tpv2_msg_init(&l2tpv2msg, if_number, NSS_L2TPV2_MSG_SESSION_DESTROY, sizeof(struct nss_l2tpv2_session_destroy_msg), NULL, NULL);
+			status = nss_l2tpv2_tx(nss_l2tpv2_get_context(), &l2tpv2msg);
+			if (status != NSS_TX_SUCCESS) {
+				nss_connmgr_l2tpv2_info("l2tpv2 session destroy command failed, if_number = %d\n", if_number);
+				return NOTIFY_BAD;
+			}
+
+			nss_unregister_l2tpv2_if(if_number);
+			status = nss_dynamic_interface_dealloc_node(if_number, NSS_DYNAMIC_INTERFACE_TYPE_L2TPV2);
+			if (status != NSS_TX_SUCCESS) {
+				nss_connmgr_l2tpv2_info("l2tpv2 dealloc node failure for if_number=%d\n", if_number);
+				return NOTIFY_BAD;
+			}
+			nss_connmgr_l2tpv2_info("deleting l2tpv2session, if_number %d, tunnel_id %d, session_id %d\n",
+									if_number, l2tpv2cfg->local_tunnel_id,  l2tpv2cfg->local_session_id);
+			break;
+		}
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_connmgr_l2tpv2_dev_event()
+ *	Net device notifier for nss l2tpv2 module
+ */
+static int nss_connmgr_l2tpv2_dev_event(struct notifier_block  *nb,
+		unsigned long event, void  *dev)
+{
+	struct net_device *netdev;
+	netdev = netdev_notifier_info_to_dev(dev);
+
+	switch (event) {
+	case NETDEV_UP:
+		return nss_connmgr_l2tpv2_dev_up(netdev);
+
+	case NETDEV_DOWN:
+		return nss_connmgr_l2tpv2_dev_down(netdev);
+
+	default:
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_connmgr_l2tpv2_get_data()
+ *	return 0 on success.
+ */
+int nss_connmgr_l2tpv2_get_data(struct net_device *dev, struct nss_connmgr_l2tpv2_data *data)
+{
+	struct nss_connmgr_l2tpv2_session_data *ptr;
+	if (!data) {
+		nss_connmgr_l2tpv2_info("nss_connmgr_l2tpv2_data ptr is null\n");
+		return -EINVAL;
+	}
+
+	rcu_read_lock();
+	hash_for_each_possible_rcu(l2tpv2_session_data_hash_table, ptr,
+				   hash_list, dev->ifindex) {
+		if (ptr->dev == dev) {
+			memcpy(data, &ptr->data, sizeof(struct nss_connmgr_l2tpv2_data));
+			rcu_read_unlock();
+			return 0;
+		}
+	}
+	rcu_read_unlock();
+
+	return -ENODEV;
+}
+EXPORT_SYMBOL(nss_connmgr_l2tpv2_get_data);
+
+/*
+ * nss_connmgr_l2tpv2_does_connmgr_track()
+ *	return 0 on success.
+ */
+int nss_connmgr_l2tpv2_does_connmgr_track(const struct net_device *dev)
+{
+	struct nss_connmgr_l2tpv2_session_data *ptr;
+
+	rcu_read_lock();
+	hash_for_each_possible_rcu(l2tpv2_session_data_hash_table, ptr,
+				   hash_list, dev->ifindex) {
+		if (ptr->dev == dev) {
+			rcu_read_unlock();
+			return 0;
+		}
+	}
+	rcu_read_unlock();
+
+	return -ENODEV;
+}
+EXPORT_SYMBOL(nss_connmgr_l2tpv2_does_connmgr_track);
+
+/*
+ * l2tpmgr_register_ipsecmgr_callback_by_ipaddr()
+ *	Register IPSecmgr callback.
+ */
+void l2tpmgr_register_ipsecmgr_callback_by_ipaddr(struct l2tpmgr_ipsecmgr_cb *cb)
+{
+	get_ipsec_ifnum_by_ipv4_addr_callback_t ipsec_get_ifnum_by_ipv4_addr;
+
+	rcu_read_lock();
+	ipsec_get_ifnum_by_ipv4_addr = rcu_dereference(ipsecmgr_cb.get_ifnum_by_ipv4_addr);
+	if (ipsec_get_ifnum_by_ipv4_addr) {
+		rcu_read_unlock();
+		nss_connmgr_l2tpv2_info("%px: IPSecmgr Callback get_ifnum_by_ipv4_addr is already registered\n", cb);
+		return;
+	}
+	rcu_read_unlock();
+
+	if (cb->get_ifnum_by_ipv4_addr == NULL) {
+		nss_connmgr_l2tpv2_warning("%px: IPSecmgr Callback get_ifnum_by_ipv4_addr is NULL\n", cb);
+		return;
+	}
+
+	rcu_assign_pointer(ipsecmgr_cb.get_ifnum_by_ipv4_addr, cb->get_ifnum_by_ipv4_addr);
+	synchronize_rcu();
+}
+EXPORT_SYMBOL(l2tpmgr_register_ipsecmgr_callback_by_ipaddr);
+
+/*
+ * l2tpmgr_unregister_ipsecmgr_callback_by_ipaddr
+ *	Unregister callback.
+ */
+void l2tpmgr_unregister_ipsecmgr_callback_by_ipaddr(void)
+{
+	rcu_assign_pointer(ipsecmgr_cb.get_ifnum_by_ipv4_addr, NULL);
+	synchronize_rcu();
+}
+EXPORT_SYMBOL(l2tpmgr_unregister_ipsecmgr_callback_by_ipaddr);
+
+#if defined(NSS_L2TP_IPSEC_BIND_BY_NETDEV)
+/*
+ * l2tpmgr_register_ipsecmgr_callback_by_netdev()
+ *	Register IPSecmgr callback.
+ */
+void l2tpmgr_register_ipsecmgr_callback_by_netdev(struct l2tpmgr_ipsecmgr_cb *cb)
+{
+	get_ipsec_ifnum_by_dev_callback_t ipsec_get_ifnum_by_dev;
+
+	rcu_read_lock();
+	ipsec_get_ifnum_by_dev = rcu_dereference(ipsecmgr_cb.get_ifnum_by_dev);
+	if (ipsec_get_ifnum_by_dev) {
+		rcu_read_unlock();
+		nss_connmgr_l2tpv2_info("%px: IPSecmgr Callback get_ifnum_by_dev is already registered\n", cb);
+		return;
+	}
+	rcu_read_unlock();
+
+	if (cb->get_ifnum_by_dev == NULL) {
+		nss_connmgr_l2tpv2_warning("%px: IPSecmgr Callback get_ifnum_by_dev is NULL\n", cb);
+		return;
+	}
+
+	rcu_assign_pointer(ipsecmgr_cb.get_ifnum_by_dev, cb->get_ifnum_by_dev);
+	synchronize_rcu();
+}
+EXPORT_SYMBOL(l2tpmgr_register_ipsecmgr_callback_by_netdev);
+
+/*
+ * l2tpmgr_unregister_ipsecmgr_callback_by_netdev
+ *	Unregister callback.
+ */
+void l2tpmgr_unregister_ipsecmgr_callback_by_netdev(void)
+{
+	rcu_assign_pointer(ipsecmgr_cb.get_ifnum_by_dev, NULL);
+	synchronize_rcu();
+}
+EXPORT_SYMBOL(l2tpmgr_unregister_ipsecmgr_callback_by_netdev);
+
+/*
+ * nss_connmgr_l2tpv2_proc_handler()
+ *	Read and write handler for sysctl.
+ */
+static int nss_connmgr_l2tpv2_proc_handler(struct ctl_table *ctl,
+					  int write, void __user *buffer,
+					  size_t *lenp, loff_t *ppos)
+{
+	char *l2tp_device_name, *ipsec_device_name;
+	char *input_str = l2tpoipsec_config;
+	int32_t l2tp_ifnum, ipsec_ifnum;
+	struct net_device *l2tpdev, *ipsecdev;
+	nss_tx_status_t status;
+	struct nss_l2tpv2_msg l2tpv2msg;
+	get_ipsec_ifnum_by_dev_callback_t ipsec_cb;
+	struct nss_l2tpv2_bind_ipsec_if_msg *l2tpv2_bind_ipsec_msg;
+	struct nss_ctx_instance *nss_ctx = nss_l2tpv2_get_context();
+	int ret = proc_dostring(ctl, write, buffer, lenp, ppos);
+	struct nss_connmgr_l2tpv2_session_data *ptr;
+
+	if (!write) {
+		nss_connmgr_l2tpv2_info("command to write is echo <l2tp-device-name> <ipsec-device-name> > <filename>\n");
+		return ret;
+	}
+
+	l2tp_device_name = strsep(&input_str, " ");
+	ipsec_device_name = strsep(&input_str, "\0");
+	if (!l2tp_device_name) {
+		nss_connmgr_l2tpv2_info("L2TP device name not found\n");
+		nss_connmgr_l2tpv2_info("command is echo <l2tp-device-name> <ipsec-device-name> > <filename>\n");
+		return -EINVAL;
+	}
+
+	if (!ipsec_device_name) {
+		nss_connmgr_l2tpv2_info("IPsec device name not found\n");
+		nss_connmgr_l2tpv2_info("command is echo <l2tp-device-name> <ipsec-device-name> > <filename>\n");
+		return -EINVAL;
+	}
+
+	l2tpdev = dev_get_by_name(&init_net, l2tp_device_name);
+	if (!l2tpdev) {
+		nss_connmgr_l2tpv2_info("Cannot find the netdevice associated with %s\n", l2tp_device_name);
+		return -EINVAL;
+	}
+
+	rcu_read_lock();
+	hash_for_each_possible_rcu(l2tpv2_session_data_hash_table, ptr,
+				   hash_list, l2tpdev->ifindex) {
+		if (ptr->dev != l2tpdev) {
+			continue;
+		}
+
+		if (ptr->data.l2tpv2.tunnel.udp_csum) {
+			nss_connmgr_l2tpv2_info("Enabling UDP checksum in L2TP packet is not supported for l2tpoipsec flow\n");
+		}
+	}
+	rcu_read_unlock();
+
+	ipsecdev = dev_get_by_name(&init_net, ipsec_device_name);
+	if (!ipsecdev) {
+		nss_connmgr_l2tpv2_info("Cannot find the netdevice associated with %s\n", ipsec_device_name);
+		dev_put(l2tpdev);
+		return -EINVAL;
+	}
+
+	/*
+	 * Get NSS ifnum for L2TP interface.
+	 */
+	l2tp_ifnum = nss_cmn_get_interface_number_by_dev(l2tpdev);
+	if (l2tp_ifnum == -1) {
+		nss_connmgr_l2tpv2_info("Cannot find the NSS interface associated with %s\n", l2tp_device_name);
+		ret = -ENODEV;
+		goto exit;
+	}
+
+	rcu_read_lock();
+	ipsec_cb = rcu_dereference(ipsecmgr_cb.get_ifnum_by_dev);
+	if (!ipsec_cb) {
+		rcu_read_unlock();
+		nss_connmgr_l2tpv2_info("Callback to get IPsec tun device not registered");
+		ret = -EPERM;
+		goto exit;
+	}
+
+	/*
+	 * Get NSS ifnum for IPsec interface.
+	 */
+	ipsec_ifnum = ipsec_cb(ipsecdev);
+	rcu_read_unlock();
+	if (ipsec_ifnum == -1) {
+		nss_connmgr_l2tpv2_info("Cannot find the NSS interface associated with %s\n", ipsec_device_name);
+		ret = -ENODEV;
+		goto exit;
+	}
+
+	/*
+	 * Send the command to bind the l2tp session with the IPsec interface.
+	 */
+	memset(&l2tpv2msg, 0, sizeof(struct nss_l2tpv2_msg));
+	nss_l2tpv2_msg_init(&l2tpv2msg, l2tp_ifnum, NSS_L2TPV2_MSG_BIND_IPSEC_IF, sizeof(struct nss_l2tpv2_bind_ipsec_if_msg), (void *)nss_connmgr_l2tpv2_msg_cb, NULL);
+	l2tpv2_bind_ipsec_msg = &l2tpv2msg.msg.bind_ipsec_if_msg;
+	l2tpv2_bind_ipsec_msg->ipsec_ifnum = ipsec_ifnum;
+	status = nss_l2tpv2_tx(nss_ctx, &l2tpv2msg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_l2tpv2_info("%px IPSec interface bind failed\n", nss_ctx);
+		ret = -EAGAIN;
+	}
+
+exit:
+	dev_put(l2tpdev);
+	dev_put(ipsecdev);
+	return ret;
+}
+
+/*
+ * nss_connmgr_l2tpv2_table
+ */
+static struct ctl_table nss_connmgr_l2tpv2_table[] = {
+	{
+		.procname	= "l2tpoipsec",
+		.data		= &l2tpoipsec_config,
+		.maxlen		= L2TP_SYSCTL_STR_LEN_MAX,
+		.mode		= 0644,
+		.proc_handler	= &nss_connmgr_l2tpv2_proc_handler,
+	},
+	{ }
+};
+
+/*
+ * nss_connmgr_l2tpv2_dir
+ */
+static struct ctl_table nss_connmgr_l2tpv2_dir[] = {
+	{
+		.procname		= "l2tpv2",
+		.mode			= 0555,
+		.child			= nss_connmgr_l2tpv2_table,
+	},
+	{ }
+};
+
+/*
+ * nss_connmgr_l2tpv2_sysroot sysctl root dir
+ */
+static struct ctl_table nss_connmgr_l2tpv2_sysroot[] = {
+	{
+		.procname		= "nss",
+		.mode			= 0555,
+		.child			= nss_connmgr_l2tpv2_dir,
+	},
+	{ }
+};
+#endif
+
+/*
+ * Linux Net device Notifier
+ */
+struct notifier_block nss_connmgr_l2tpv2_notifier = {
+	.notifier_call = nss_connmgr_l2tpv2_dev_event,
+};
+
+/*
+ * nss_connmgr_l2tpv2_init_module()
+ *	Tunnel l2tpv2 module init function
+ */
+int __init nss_connmgr_l2tpv2_init_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+#if defined(NSS_L2TP_IPSEC_BIND_BY_NETDEV)
+	ctl_tbl_hdr = register_sysctl_table(nss_connmgr_l2tpv2_sysroot);
+	if (!ctl_tbl_hdr) {
+		nss_connmgr_l2tpv2_info("Unable to register sysctl table for L2TP conn mgr\n");
+		return -EFAULT;
+	}
+
+#endif
+	/*
+	 * Initialize ipsecmgr callback.
+	 */
+	rcu_assign_pointer(ipsecmgr_cb.get_ifnum_by_dev, NULL);
+	rcu_assign_pointer(ipsecmgr_cb.get_ifnum_by_ipv4_addr, NULL);
+	synchronize_rcu();
+	register_netdevice_notifier(&nss_connmgr_l2tpv2_notifier);
+	return 0;
+}
+
+/*
+ * nss_connmgr_l2tpv2_exit_module
+ *	Tunnel l2tpv2 module exit function
+ */
+void __exit nss_connmgr_l2tpv2_exit_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return;
+	}
+#endif
+	unregister_netdevice_notifier(&nss_connmgr_l2tpv2_notifier);
+}
+
+module_init(nss_connmgr_l2tpv2_init_module);
+module_exit(nss_connmgr_l2tpv2_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS l2tpv2 over ppp offload manager");
diff --git a/qca-nss-clients/l2tp/l2tpv2/nss_connmgr_l2tpv2.h b/qca-nss-clients/l2tp/l2tpv2/nss_connmgr_l2tpv2.h
new file mode 100644
index 0000000..bd3c27a
--- /dev/null
+++ b/qca-nss-clients/l2tp/l2tpv2/nss_connmgr_l2tpv2.h
@@ -0,0 +1,99 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_connnmgr_l2tpv2.h
+ *
+ *Header file implementation of nss_connnmgr_l2tpv2.c
+ */
+
+#ifndef _NSS_CONNMGR_L2TP_V2_H_
+#define _NSS_CONNMGR_L2TP_V2_H_
+
+#include <linux/l2tp.h>
+#include <linux/in.h>
+#include <linux/socket.h>
+#include <linux/types.h>
+#include <linux/version.h>
+
+#define L2TP_V_2 2
+
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 12, 0))
+#define tunnel_hold(tunnel) atomic_inc(&tunnel->ref_count)
+#define tunnel_put(tunnel)  atomic_dec(&tunnel->ref_count)
+#define session_hold(session) atomic_inc(&session->ref_count)
+#define session_put(session)  atomic_dec(&session->ref_count)
+#else
+#define tunnel_hold(tunnel) refcount_inc(&tunnel->ref_count)
+#define tunnel_put(tunnel)  refcount_dec(&tunnel->ref_count)
+#define session_hold(session) refcount_inc(&session->ref_count)
+#define session_put(session)  refcount_dec(&session->ref_count)
+#endif
+
+ /*
+  *		----------------------------------------------------------------------------------
+  *		|		|		|		|		|		 |
+  *		| ip header	| udp header	| l2tpv2 header	|ppp header	| ppp payload    |
+  *		|		|		|		|		|  (IP data gram)|
+  *		|		|		|		|		|		 |
+  *		|---------------------------------------------------------------------------------
+  *             L2TV2 & L2TPV3 over UDP
+  */
+struct session_info {
+	u32 session_id, peer_session_id;	/* local & remote session id */
+	u16 hdr_len;				/* header length */
+	int reorder_timeout;			/* reorder timeout */
+	unsigned send_seq:1;			/* enable tx sequence number ?  */
+	unsigned recv_seq:1;			/* enable rx sequence number ?  */
+};
+
+struct tunnel_info {
+	u32 tunnel_id, peer_tunnel_id;		/* local and remote tunnel id */
+	u8 udp_csum;				/* enable udp checksum ? */
+};
+
+struct udp_info {
+	__be16 dport, sport;
+
+};
+
+struct ip_info {
+		struct {
+			struct in_addr saddr, daddr;
+		} v4;
+};
+
+struct l2tpv2_info {
+	struct tunnel_info tunnel;
+	struct session_info session;
+};
+
+struct nss_connmgr_l2tpv2_data {
+	struct ip_info ip;
+	struct udp_info udp;
+	struct l2tpv2_info l2tpv2;
+};
+
+struct nss_connmgr_l2tpv2_session_data {
+	struct nss_connmgr_l2tpv2_data data;
+	struct net_device *dev;
+	struct hlist_node hash_list;
+};
+
+extern int nss_connmgr_l2tpv2_get_data(struct net_device *dev, struct nss_connmgr_l2tpv2_data *data);
+extern int nss_connmgr_l2tpv2_does_connmgr_track(const struct net_device *dev);
+
+#endif
diff --git a/qca-nss-clients/l2tp/l2tpv2/nss_l2tpv2_stats.c b/qca-nss-clients/l2tp/l2tpv2/nss_l2tpv2_stats.c
new file mode 100644
index 0000000..9d4a37a
--- /dev/null
+++ b/qca-nss-clients/l2tp/l2tpv2/nss_l2tpv2_stats.c
@@ -0,0 +1,170 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_l2tpv2_stats.c
+ *
+ * This file is the NSS l2tpv2 stats handler functions
+ */
+
+#include <linux/types.h>
+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE)
+#include <net/netfilter/nf_flow_table.h>
+#endif
+#include <linux/ppp_channel.h>
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+#include <linux/l2tp.h>
+#include <net/sock.h>
+#include <linux/if_pppox.h>
+#include <linux/ppp_defs.h>
+#include <linux/version.h>
+#include <linux/../../net/l2tp/l2tp_core.h>
+
+#include "nss_connmgr_l2tpv2.h"
+
+/*
+ * NSS l2tpv2 debug macros
+ */
+#if (NSS_L2TP_DEBUG_LEVEL < 1)
+#define nss_l2tpv2_stats_assert(fmt, args...)
+#else
+#define nss_l2tpv2_stats_assert(c)  BUG_ON(!(c));
+#endif
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_l2tpv2_stats_warning(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_l2tpv2_stats_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_l2tpv2_stats_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_L2TP_DEBUG_LEVEL < 2)
+#define nss_l2tpv2_stats_warning(s, ...)
+#else
+#define nss_l2tpv2_stats_warning(s, ...) pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_L2TP_DEBUG_LEVEL < 3)
+#define nss_l2tpv2_stats_info(s, ...)
+#else
+#define nss_l2tpv2_stats_info(s, ...)   pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_L2TP_DEBUG_LEVEL < 4)
+#define nss_l2tpv2_stats_trace(s, ...)
+#else
+#define nss_l2tpv2_stats_trace(s, ...)  pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif
+
+/*
+ * nss_l2tpv2_update_dev_stats()
+ *	Handle stats message for l2tpv2 data messages
+ */
+void nss_l2tpv2_update_dev_stats(struct net_device *dev, struct nss_l2tpv2_sync_session_stats_msg *sync_stats)
+{
+	struct l2tp_tunnel *tunnel;
+	struct l2tp_session *session;
+	struct nss_connmgr_l2tpv2_data data;
+	struct l2tp_stats l2tp_stats;
+	int err;
+
+	if (!dev) {
+		return;
+	}
+
+	dev_hold(dev);
+
+	memset(&l2tp_stats, 0, sizeof(struct l2tp_stats));
+
+	/*
+	 * Get tunnel id
+	 */
+	err = nss_connmgr_l2tpv2_get_data(dev, &data);
+	if (err) {
+		dev_put(dev);
+		return;
+	}
+
+	/*
+	 * Update tunnel & session stats
+	 */
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 12, 0))
+	tunnel = l2tp_tunnel_find(dev_net(dev), data.l2tpv2.tunnel.tunnel_id);
+	if (!tunnel) {
+		dev_put(dev);
+		return;
+	}
+	tunnel_hold(tunnel);
+
+	session = l2tp_session_find(dev_net(dev), tunnel, data.l2tpv2.session.session_id);
+	if (!session) {
+		tunnel_put(tunnel);
+		dev_put(dev);
+		return;
+	}
+	session_hold(session);
+#else
+	tunnel = l2tp_tunnel_get(dev_net(dev), data.l2tpv2.tunnel.tunnel_id);
+	if (!tunnel) {
+		dev_put(dev);
+		return;
+	}
+	session = l2tp_tunnel_get_session(tunnel, data.l2tpv2.session.session_id);
+	if (!session) {
+		tunnel_put(tunnel);
+		dev_put(dev);
+		return;
+	}
+#endif
+
+	atomic_long_set(&l2tp_stats.tx_packets, (long)sync_stats->node_stats.tx_packets);
+	atomic_long_set(&l2tp_stats.tx_bytes, (long)sync_stats->node_stats.tx_bytes);
+	atomic_long_set(&l2tp_stats.tx_errors, (long)sync_stats->tx_errors);
+
+	atomic_long_set(&l2tp_stats.rx_packets, (long)sync_stats->node_stats.rx_packets);
+	atomic_long_set(&l2tp_stats.rx_bytes, (long)sync_stats->node_stats.rx_bytes);
+	atomic_long_set(&l2tp_stats.rx_errors, (long)sync_stats->rx_errors);
+
+	atomic_long_set(&l2tp_stats.rx_seq_discards, (long)sync_stats->rx_seq_discards);
+	atomic_long_set(&l2tp_stats.rx_oos_packets, (long)(sync_stats->rx_oos_packets));
+
+	l2tp_stats_update(tunnel, session, &l2tp_stats);
+
+	session_put(session);
+	tunnel_put(tunnel);
+
+	/*
+	 * Update ppp stats
+	 */
+	ppp_update_stats(dev,
+			 (unsigned long)sync_stats->node_stats.rx_packets,
+			 (unsigned long)sync_stats->node_stats.rx_bytes,
+			 (unsigned long)sync_stats->node_stats.tx_packets,
+			 (unsigned long)sync_stats->node_stats.tx_bytes,
+			 (unsigned long)sync_stats->rx_errors,
+			 (unsigned long)sync_stats->tx_errors,
+			 (unsigned long)nss_cmn_rx_dropped_sum(&sync_stats->node_stats),
+			 (unsigned long)sync_stats->tx_dropped);
+
+	dev_put(dev);
+}
diff --git a/qca-nss-clients/l2tp/l2tpv2/nss_l2tpv2_stats.h b/qca-nss-clients/l2tp/l2tpv2/nss_l2tpv2_stats.h
new file mode 100644
index 0000000..6529184
--- /dev/null
+++ b/qca-nss-clients/l2tp/l2tpv2/nss_l2tpv2_stats.h
@@ -0,0 +1,34 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_l2p_stats.h
+ *
+ * This file is the NSS l2tpv2 stats header file
+ */
+
+#ifndef _NSS_L2TP_V2_STATS_H_
+#define _NSS_L2TP_V2_STATS_H_
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+
+/*
+ * Interface, session and tunnel stats update
+ */
+void nss_l2tpv2_update_dev_stats(struct net_device *dev, struct nss_l2tpv2_sync_session_stats_msg *sync_stats);
+
+#endif
diff --git a/qca-nss-clients/lag/Makefile b/qca-nss-clients/lag/Makefile
new file mode 100644
index 0000000..9286aab
--- /dev/null
+++ b/qca-nss-clients/lag/Makefile
@@ -0,0 +1,15 @@
+# Makefile for the lagmgr client
+
+ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64 ipq60xx ipq60xx_64))
+ccflags-y += -DNSS_LAG_PPE_SUPPORT
+endif
+
+ccflags-y := -I$(obj) -I$(obj)/..
+ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)"
+ccflags-y += -DNSS_LAG_MGR_DEBUG_LEVEL=0
+ccflags-y += -Wall -Werror
+
+obj-m += qca-nss-lag-mgr.o
+qca-nss-lag-mgr-objs := nss_lag.o
+
+obj ?= .
diff --git a/qca-nss-clients/lag/nss_lag.c b/qca-nss-clients/lag/nss_lag.c
new file mode 100644
index 0000000..55230c7
--- /dev/null
+++ b/qca-nss-clients/lag/nss_lag.c
@@ -0,0 +1,380 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_lag.c
+ *	HLOS to NSS LAG Interface manager
+ */
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <net/bonding.h>
+#if defined(NSS_LAG_PPE_SUPPORT)
+#include <nss_vlan_mgr.h>
+#include <fal/fal_trunk.h>
+#endif
+
+#include <nss_api_if.h>
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_lag_warn(s, ...) \
+		pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_lag_info(s, ...) \
+		pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#else /* CONFIG_DYNAMIC_DEBUG */
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_LAG_MGR_DEBUG_LEVEL < 2)
+#define nss_lag_warn(s, ...)
+#else
+#define nss_lag_warn(s, ...) \
+		pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_LAG_MGR_DEBUG_LEVEL < 3)
+#define nss_lag_info(s, ...)
+#else
+#define nss_lag_info(s, ...) \
+		pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+#define NSS_LAG_MAX_BOND_DEVICES 4
+#define NSS_LAG_MAX_PPE_BOND_DEVICES 2
+#define NSS_LAG_MAX_SLAVES_PER_BONDID 16
+#define NSS_LAG_BOND_DEV_STATE_ACTIVE 1
+#define NSS_LAG_BOND_DEV_STATE_INACTIVE 2
+
+/*
+ * LAG manager private structure
+ */
+struct nss_bond_pvt {
+	int32_t bond_dev_state;	/* Active or Inactive */
+	int32_t bondid;		/* Bond ID */
+	uint32_t members;	/* Enslaved devices:
+				 *   bit 0 - eth0,
+				 *   bit1 - eth1 ...
+				 */
+	struct net_device *slaves[NSS_LAG_MAX_SLAVES_PER_BONDID];
+} bond_pvt[NSS_LAG_MAX_BOND_DEVICES];
+
+DEFINE_SPINLOCK(nss_lag_spinlock);
+
+/*
+ * NSS Context for LAG function
+ */
+static void *nss_lag_nss_context;	/* Registration for LAG */
+
+#if defined(NSS_LAG_PPE_SUPPORT)
+/*
+ * nss_lag_update_ppe()
+ *	Update and/or Configure LAG in Hardware when there is change in bonding
+ *	slave's state
+ */
+static int nss_lag_update_ppe(int32_t bondid, int32_t slave_ifnum,
+		enum nss_lag_state_change_ev slave_event)
+{
+	struct nss_bond_pvt *pvt;
+	int32_t enable = 1;
+
+	if (bondid > NSS_LAG_MAX_PPE_BOND_DEVICES) {
+		nss_lag_warn("bondid is wrong: bondid=%d\n", bondid);
+		return -1;
+	}
+
+	if (slave_ifnum > NSS_MAX_PHYSICAL_INTERFACES) {
+		nss_lag_warn("HW LAG Supports only Physical ports: slave=%d\n",
+				slave_ifnum);
+		return -1;
+	}
+
+	spin_lock(&nss_lag_spinlock);
+
+	pvt = &bond_pvt[bondid];
+
+	if (slave_event == NSS_LAG_ENSLAVE)
+		pvt->members |= (1 << (slave_ifnum - 1));
+	else
+		pvt->members &= ~(1 << (slave_ifnum - 1));
+
+	if (pvt->members)
+		pvt->bond_dev_state = NSS_LAG_BOND_DEV_STATE_ACTIVE;
+	else {
+		pvt->bond_dev_state = NSS_LAG_BOND_DEV_STATE_INACTIVE;
+		enable = 0;
+	}
+
+	spin_unlock(&nss_lag_spinlock);
+
+	return fal_trunk_group_set(0, bondid, enable, pvt->members);
+}
+#endif
+
+/*
+ * nss_lag_send_lag_state()
+ *	Send the currnet LAG state of a physical interface that has changed
+ *	state in the bonding driver.
+ */
+static nss_tx_status_t nss_lag_send_lag_state(struct nss_ctx_instance *nss_ctx,
+		int32_t bondid, struct net_device *slave,
+		enum nss_lag_state_change_ev slave_state)
+{
+	int32_t lagid = 0;
+	int32_t slave_ifnum;
+	nss_tx_status_t nss_tx_status;
+
+	nss_lag_info("Send LAG update for: %px (%s)\n", slave, slave->name);
+
+	lagid = bondid + NSS_LAG0_INTERFACE_NUM;
+
+	slave_ifnum = nss_cmn_get_interface_number_by_dev(slave);
+	if (slave_ifnum < 0)
+		return NSS_TX_FAILURE_BAD_PARAM;
+
+	nss_lag_info("slave_state=%d, slave_ifnum=%d, bondid=%d\n",
+			slave_state, slave_ifnum, bondid);
+
+	nss_tx_status = nss_lag_tx_slave_state(lagid, slave_ifnum, slave_state);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_lag_warn("%px: Send LAG update failed, status: %d\n", slave,
+				nss_tx_status);
+		return NSS_TX_FAILURE;
+	}
+	nss_lag_info("%px: Send LAG update success\n", slave);
+
+#if defined(NSS_LAG_PPE_SUPPORT)
+	ret = nss_lag_update_ppe(bondid, slave_ifnum, slave_state);
+	if (ret)
+		nss_lag_warn("%px: Couldn't update PPE: ret =  %d\n",
+				slave, ret);
+#endif
+	return NSS_TX_SUCCESS;
+}
+
+/*
+ * nss_lag_event_cb()
+ *	Handle LAG event from the NSS driver
+ */
+static void nss_lag_event_cb(void *if_ctx, struct nss_lag_msg *msg)
+{
+	/*
+	 * TODO: Figure out if there is anything we need to do here,
+	 * the old CM did nothing..
+	 */
+	switch (msg->cm.type) {
+	default:
+		nss_lag_warn("Unknown LAG event from NSS: %d", msg->cm.type);
+		break;
+	}
+}
+
+/*
+ * nss_lag_update_slave()
+ *	Monitor bonding slaves and send updates to hardware
+ */
+static int nss_lag_update_slave(struct netdev_notifier_info *info)
+{
+	struct net_device *slave_dev = netdev_notifier_info_to_dev(info);
+	struct net_device *bond_dev;
+	int32_t bondid = -1;
+	uint32_t slave_ifnum, i;
+	struct nss_bond_pvt *pvt;
+
+	if (!netif_is_bond_slave(slave_dev))
+		return NOTIFY_DONE;
+
+	/*
+	 * Only care about interfaces known by NSS
+	 */
+	slave_ifnum = nss_cmn_get_interface_number_by_dev(slave_dev);
+	if (slave_ifnum < 0)
+		return NOTIFY_DONE;
+
+	bond_dev = netdev_master_upper_dev_get(slave_dev);
+	if (bond_dev) {
+
+		/* bond_dev is valid when slave is Enslaved */
+
+		nss_lag_info("Interface %s added in LAG ID=%d: %s\n",
+				slave_dev->name, bondid, bond_dev->name);
+
+		/*
+		 * Figure out the aggregation id of this slave
+		 */
+		bondid = bond_get_id(bond_dev);
+		if ((bondid < 0) || (bondid >= NSS_LAG_MAX_BOND_DEVICES)) {
+			nss_lag_warn("Invalid LAG group id 0x%x\n", bondid);
+			return NOTIFY_DONE;
+		}
+
+		spin_lock(&nss_lag_spinlock);
+
+		pvt = &bond_pvt[bondid];
+		pvt->bondid = bondid;
+
+		for (i = 0; i < NSS_LAG_MAX_SLAVES_PER_BONDID; i++) {
+			if (!pvt->slaves[i])
+				break;
+		}
+
+		if (i == NSS_LAG_MAX_SLAVES_PER_BONDID) {
+			spin_unlock(&nss_lag_spinlock);
+			nss_lag_warn("More than max %d slaves are added\n",
+					NSS_LAG_MAX_SLAVES_PER_BONDID);
+			return NOTIFY_DONE;
+		}
+
+		pvt->slaves[i] = slave_dev;
+		spin_unlock(&nss_lag_spinlock);
+
+		if (nss_lag_send_lag_state(nss_lag_nss_context,
+			bondid, slave_dev, NSS_LAG_ENSLAVE)) {
+			nss_lag_warn("Enslave %s dev failed\n",
+					slave_dev->name);
+			return NOTIFY_BAD;
+		}
+
+#if defined(NSS_LAG_PPE_SUPPORT)
+		if (nss_vlan_mgr_add_bond_slave(bond_dev, slave_dev))
+			nss_lag_warn("%px: Adding vlan for %s dev failed\n", slave_dev, slave_dev->name);
+#endif
+		return NOTIFY_DONE;
+	}
+
+	/* Slave is removed from bond */
+	spin_lock(&nss_lag_spinlock);
+	for (i = 0; i < NSS_LAG_MAX_BOND_DEVICES; i++) {
+		int j;
+
+		pvt = &bond_pvt[i];
+		for (j = 0; j < NSS_LAG_MAX_SLAVES_PER_BONDID; j++)
+			if (pvt->slaves[j] == slave_dev) {
+				pvt->slaves[j] = NULL;
+				bondid = pvt->bondid;
+			}
+
+		if (bondid != -1)
+			break;
+	}
+	spin_unlock(&nss_lag_spinlock);
+
+	if (bondid == -1)
+		return NOTIFY_DONE;
+
+	nss_lag_info("Interface %s removed from LAG ID=%d\n",
+			slave_dev->name, bondid);
+
+	if (nss_lag_send_lag_state(nss_lag_nss_context,
+		bondid, slave_dev, NSS_LAG_RELEASE)) {
+		nss_lag_warn("Deslave %s dev failed\n", slave_dev->name);
+		return NOTIFY_BAD;
+	}
+
+#if defined(NSS_LAG_PPE_SUPPORT)
+	if (nss_vlan_mgr_delete_bond_slave(slave_dev))
+		nss_lag_warn("%px: Delete vlan for %s dev failed\n", slave_dev, slave_dev->name);
+#endif
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_lag_netdevice_event()
+ *	Handle events received from network stack
+ */
+static int nss_lag_netdevice_event(struct notifier_block *unused,
+		unsigned long event, void *ptr)
+{
+	switch (event) {
+	case NETDEV_CHANGEUPPER:
+		return nss_lag_update_slave((struct netdev_notifier_info *)ptr);
+	}
+	return NOTIFY_DONE;
+}
+
+/* register netdev notifier callback */
+static struct notifier_block nss_lag_netdevice __read_mostly = {
+	.notifier_call = nss_lag_netdevice_event,
+};
+
+/*
+ * nss_lag_init()
+ *	Initialize NSS LAG client
+ */
+int __init nss_lag_init(void)
+{
+	int ret;
+	/*
+	 * Register Link Aggregation interfaces with NSS driver
+	 * assuming all four LAGs are on same interface.
+	 */
+	nss_lag_nss_context = nss_register_lag_if(NSS_LAG0_INTERFACE_NUM, NULL,
+						nss_lag_event_cb, NULL);
+	if (!nss_lag_nss_context) {
+		nss_lag_info("Failed to register LAG interface with NSS\n");
+		return -1;
+	}
+
+	(void)nss_register_lag_if(NSS_LAG1_INTERFACE_NUM, NULL,
+			nss_lag_event_cb, NULL);
+	(void)nss_register_lag_if(NSS_LAG2_INTERFACE_NUM, NULL,
+			nss_lag_event_cb, NULL);
+	(void)nss_register_lag_if(NSS_LAG3_INTERFACE_NUM, NULL,
+			nss_lag_event_cb, NULL);
+
+	ret = register_netdevice_notifier(&nss_lag_netdevice);
+	if (ret) {
+		nss_lag_warn("Failed to register NETDEV notifier, error=%d\n",
+				ret);
+
+		nss_unregister_lag_if(NSS_LAG0_INTERFACE_NUM);
+		nss_unregister_lag_if(NSS_LAG1_INTERFACE_NUM);
+		nss_unregister_lag_if(NSS_LAG2_INTERFACE_NUM);
+		nss_unregister_lag_if(NSS_LAG3_INTERFACE_NUM);
+	} else
+		nss_lag_info("LAG Manager Installed\n");
+
+	return ret;
+}
+
+/*
+ * nss_lag_exit()
+ *	Cleanup NSS LAG client and exit
+ */
+void __exit nss_lag_exit(void)
+{
+	unregister_netdevice_notifier(&nss_lag_netdevice);
+
+	/*
+	 * Unregister Link Aggregation interfaces with NSS driver
+	 */
+	nss_unregister_lag_if(NSS_LAG0_INTERFACE_NUM);
+	nss_unregister_lag_if(NSS_LAG1_INTERFACE_NUM);
+	nss_unregister_lag_if(NSS_LAG2_INTERFACE_NUM);
+	nss_unregister_lag_if(NSS_LAG3_INTERFACE_NUM);
+
+	nss_lag_info("LAG Manager Removed\n");
+}
+
+module_init(nss_lag_init);
+module_exit(nss_lag_exit);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS LAG Client");
diff --git a/qca-nss-clients/map/map-t/Makefile b/qca-nss-clients/map/map-t/Makefile
new file mode 100644
index 0000000..d7fcd2c
--- /dev/null
+++ b/qca-nss-clients/map/map-t/Makefile
@@ -0,0 +1,7 @@
+# Makefile for map-t client
+ccflags-y += -I$(obj)/../../exports -I$(obj)/../..  -I$(obj)/nss_hal/include
+ccflags-y += -DNSS_MAP_T_DEBUG_LEVEL=0
+ccflags-y += -Wall -Werror
+obj-m += qca-nss-map-t.o
+qca-nss-map-t-objs := nss_connmgr_map_t.o
+
diff --git a/qca-nss-clients/map/map-t/nss_connmgr_map_t.c b/qca-nss-clients/map/map-t/nss_connmgr_map_t.c
new file mode 100644
index 0000000..422f322
--- /dev/null
+++ b/qca-nss-clients/map/map-t/nss_connmgr_map_t.c
@@ -0,0 +1,1218 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_connnmgr_map_t.c
+ *
+ * This file implements NSS map-t client module
+ */
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <net/ipv6.h>
+#include <linux/rwlock_types.h>
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/version.h>
+#include <linux/list_sort.h>
+#include <linux/ipv6.h>
+#include <linux/debugfs.h>
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+#include "nss_connmgr_map_t.h"
+#include <nat46-core.h>
+#include <nat46-netdev.h>
+
+/*
+ * NSS map_t debug macros
+ */
+#if (NSS_MAP_T_DEBUG_LEVEL < 1)
+#define nss_connmgr_map_t_assert(fmt, args...)
+#else
+#define nss_connmgr_map_t_assert(c) BUG_ON(!(c));
+#endif
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_connmgr_map_t_warning(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_connmgr_map_t_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_connmgr_map_t_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_MAP_T_DEBUG_LEVEL < 2)
+#define nss_connmgr_map_t_warning(s, ...)
+#else
+#define nss_connmgr_map_t_warning(s, ...) pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_MAP_T_DEBUG_LEVEL < 3)
+#define nss_connmgr_map_t_info(s, ...)
+#else
+#define nss_connmgr_map_t_info(s, ...) pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_MAP_T_DEBUG_LEVEL < 4)
+#define nss_connmgr_map_t_trace(s, ...)
+#else
+#define nss_connmgr_map_t_trace(s, ...) pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif
+
+/*
+ * Format for header: "netdevice = eth0\n"
+ */
+#define MAP_T_NETDEVICE_SZ (strlen("netdevice = ") + IFNAMSIZ + 1)
+
+/*
+ * Format for a rule: <11 digits decmal> + ": 0x" + <16 hex digits for long long> + newline
+ */
+#define MAP_T_INT_TO_DEC 11
+#define MAP_T_LONG_LONG_TO_HEX 16
+#define MAP_T_RULE_SZ ((MAP_T_INT_TO_DEC) + (MAP_T_LONG_LONG_TO_HEX) + 5)
+
+#define MAP_T_IPV6_CLASS_SHIFT 20
+#define MAP_T_IPV6_CLASS_MASK  0x0FF00000
+
+/*
+ * Max map-t interfaces supported = NSS_MAX_MAP_T_DYNAMIC_INTERFACES
+ */
+static int mapt_interfaces_count;
+
+/*
+ * MAP-T flags.
+ */
+static uint8_t map_t_flags;
+
+/*
+ * client code check for correctness of rule. This debug stats helps in
+ * to see those stats
+ */
+static struct dentry *map_t_debugfs;
+
+/*
+ *      net_device1--------->net_device_2--------->net_device_3
+ *		|		|			|
+ *		|		|			|
+ *		|		|			|
+ *	     rule_set	     rule_set		      rule_set
+ *
+ */
+static LIST_HEAD(list_dev_to_map_t_rules_head);
+
+/*
+ * nss_connmgr_map_t_dump_rules()
+ *	dumps the rule list. Should only call this func from nss_connmgr_map_t_dev_up()
+ *
+ * This function dumps map-t rules read from nat-46 module. This function is
+ * only for debug purpose.
+ */
+static void __maybe_unused nss_connmgr_map_t_dump_rules(struct net_device *dev __maybe_unused, struct nat46_xlate_rulepair *apair __maybe_unused, int count)
+{
+	const char *style_to_string[] __maybe_unused = {"NONE", "MAP", "MAP-0", "RFC6052"};
+	int i = 0;
+
+	if (!apair) {
+		return;
+	}
+
+	for (i = 0; i < count; i++) {
+		nss_connmgr_map_t_info("%px: local.v4 %pI4/%d local.v6 %pI6c/%d local.style %s local.ea-len %d local.psid-offset %d remote.v4 %pI4/%d remote.v6 %pI6c/%d remote.style %s remote.ea-len %d remote.psid-offset %d\n", dev,
+			 &apair->local.v4_pref,
+			 apair->local.v4_pref_len,
+			 &apair->local.v6_pref,
+			 apair->local.v6_pref_len,
+			 style_to_string[apair->local.style],
+			 apair->local.ea_len,
+			 apair->local.psid_offset,
+
+			 &apair->remote.v4_pref,
+			 apair->remote.v4_pref_len,
+			 &apair->remote.v6_pref,
+			 apair->remote.v6_pref_len,
+			 style_to_string[apair->remote.style],
+			 apair->remote.ea_len,
+			 apair->remote.psid_offset);
+
+		apair++;
+	}
+}
+
+/*
+ * nss_connmgr_map_t_dump_list()
+ *	dump sorted list. Should only call this func from nss_connmgr_map_t_dev_up()
+ *
+ * client module will sort map-t rules based on local ipv4 prefix len, remote
+ * ipv4 prefix len, local ipv6 prefix len, remote ipv6 prefix len. This function
+ * can dump those sorted list. This function is only for debug purpose.
+ * We may call this function once sort is done.
+ */
+static void __maybe_unused nss_connmgr_map_t_dump_list(struct net_device *dev __maybe_unused, struct list_head *head)
+{
+	const char *style_to_string[] __maybe_unused = {"NONE", "MAP", "MAP-0", "RFC6052"};
+	struct list_lookup_entry_t *entry;
+	list_for_each_entry(entry, head, list) {
+		struct nat46_xlate_rulepair *apair __maybe_unused = entry->ptr_rule_set;
+		nss_connmgr_map_t_info("%px: local.v4 %pI4/%d local.v6 %pI6c/%d local.style %s local.ea-len %d local.psid-offset %d remote.v4 %pI4/%d remote.v6 %pI6c/%d remote.style %s remote.ea-len %d remote.psid-offset %d\n", dev,
+			&apair->local.v4_pref,
+			apair->local.v4_pref_len,
+			&apair->local.v6_pref,
+			apair->local.v6_pref_len,
+			style_to_string[apair->local.style],
+			apair->local.ea_len,
+			apair->local.psid_offset,
+
+			&apair->remote.v4_pref,
+			apair->remote.v4_pref_len,
+			&apair->remote.v6_pref,
+			apair->remote.v6_pref_len,
+			style_to_string[apair->remote.style],
+			apair->remote.ea_len,
+			apair->remote.psid_offset);
+	}
+}
+
+/*
+ * nss_connmgr_map_t_debugfs_set_rule_status()
+ */
+static void nss_connmgr_map_t_debugfs_set_rule_status(struct net_device *dev, int rule_num, uint64_t status)
+{
+	struct list_dev_to_map_t_rules_entry_t *entry;
+
+	if (rule_num < 1) {
+		return;
+	}
+
+	rule_num--;
+
+	list_for_each_entry(entry, &list_dev_to_map_t_rules_head, list) {
+		if (entry->dev != dev) {
+			continue;
+		}
+		entry->rule_status[rule_num] = status;
+		return;
+	}
+}
+
+/*
+ * nss_connmgr_map_t_free_all()
+ *	Free up all memory allocated for linked list
+ */
+static void nss_connmgr_map_t_free_all(struct net_device *dev)
+{
+	struct list_dev_to_map_t_rules_entry_t *entry, *tmp;
+
+	list_for_each_entry_safe(entry, tmp, &list_dev_to_map_t_rules_head, list) {
+
+		if (entry->dev != dev) {
+			continue;
+		}
+
+		kfree(entry->rule_status);
+
+		list_del(&entry->list);
+		kfree(entry);
+	}
+}
+
+/*
+ * nss_connmgr_map_t_allocate_all()
+ *	allocate all data structures
+ */
+static void nss_connmgr_map_t_allocate_all(struct net_device *dev, struct nat46_xlate_rulepair *rule_pairs, int rule_pair_count)
+{
+	struct list_dev_to_map_t_rules_entry_t *entry;
+
+	entry = (struct list_dev_to_map_t_rules_entry_t *)
+					kmalloc(sizeof(struct list_dev_to_map_t_rules_entry_t), GFP_KERNEL);
+	if (!entry) {
+		nss_connmgr_map_t_warning("%px: Allocation for dev_to_map_t_rules_list_entry failed for netdev = %s\n", dev, dev->name);
+		nss_connmgr_map_t_free_all(dev);
+		return;
+	}
+
+	/*
+	 * Add to map-t netdevice list
+	 */
+	INIT_LIST_HEAD(&entry->list);
+
+	entry->dev = dev;
+	entry->rule_set = rule_pairs;
+
+	list_add(&entry->list, &list_dev_to_map_t_rules_head);
+
+	entry->rule_pair_count = rule_pair_count;
+
+	/*
+	 * allocate memory for rule validation status
+	 */
+	entry->rule_status = kzalloc(sizeof(uint64_t) * rule_pair_count, GFP_KERNEL);
+
+	if (!entry->rule_status) {
+		nss_connmgr_map_t_free_all(dev);
+	}
+
+}
+
+/*
+ * nss_connmgr_mapt_validate_rule_style_mapt()
+ *	Validate map-t style rule
+ */
+static bool nss_connmgr_mapt_validate_rule_style_mapt(struct net_device *dev, struct nat46_xlate_rule *rule, int rule_num,
+						       bool is_local_rule, uint64_t *stats)
+{
+	int psid_len;
+
+	/*
+	 * Validate rule parameters
+	 */
+	if (rule->ea_len < 0 || rule->ea_len > 48) {
+		nss_connmgr_map_t_warning("%px: mapt rule %d is invalid as ea_len < 0 or ea_len > 48\n", dev, rule_num);
+		*stats |= 1 << (is_local_rule ? MAP_T_LOCAL_EA_BITS_LEN_IS_INVALID : MAP_T_REMOTE_EA_BITS_LEN_IS_INVALID);
+		return false;
+	}
+
+	if (rule->v4_pref_len + rule->ea_len > 32) {
+		psid_len = rule->ea_len - (32 - rule->v4_pref_len);
+	} else {
+		psid_len = 0;
+	}
+
+	if (psid_len + rule->psid_offset > 16) {
+		nss_connmgr_map_t_warning("%px: mapt rule %d is invalid as psid offset + psid len > 16\n", dev, rule_num);
+		*stats |= 1 << (is_local_rule ? MAP_T_LOCAL_PSID_LEN_PLUS_PSID_OFFSET_IS_GREATER_THAN_16 : MAP_T_REMOTE_PSID_LEN_PLUS_REMOTE_PSID_OFFSET_IS_GREATER_THAN_16);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_connmgr_mapt_validate_rule_style_rfc6052()
+ *	Validate map-t style rule
+ */
+static bool nss_connmgr_mapt_validate_rule_style_rfc6052(struct net_device *dev, struct nat46_xlate_rule *rule, int rule_num, bool is_local_rule, uint64_t *stats)
+{
+	if (!(rule->v6_pref_len == 32 || rule->v6_pref_len == 40 ||
+	      rule->v6_pref_len == 48 || rule->v6_pref_len == 56 ||
+	      rule->v6_pref_len == 64 || rule->v6_pref_len == 96)) {
+		nss_connmgr_map_t_warning("%px: mapt rule %d is invalid as rfc6052 end user prefix is invalid\n", dev, rule_num);
+		*stats |= 1 << (is_local_rule ? MAP_T_LOCAL_IPV6_PREFIX_LEN_IS_NOT_32_40_48_56_64_OR_96 : MAP_T_REMOTE_IPV6_PREFIX_LEN_IS_NOT_32_40_48_56_64_OR_96);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_connmgr_mapt_check_correctness_of_mapt_rule()
+ *	Check each mapt rule params and validate each field.
+ *
+ * Returns true if all parameters are correct.
+ * As per RFC7599 (map-t rfc), local style should be map-t. Remote style
+ * of FMR must be map-t, but remote syle of DMR is RFC6052.
+ * map-t user space process doesnot really mandates this restriction and
+ * allows style of rule can be anything irrespective of FMR or DMR. So
+ * this check also won't fails on style mismatch.
+ */
+static bool nss_connmgr_mapt_check_correctness_of_mapt_rule(struct net_device *dev, struct nat46_xlate_rulepair *rule_pair, int rule_num, uint64_t *stats)
+{
+	/*
+	 * Validate local rule parameters
+	 */
+	switch (rule_pair->local.style) {
+	case NAT46_XLATE_NONE:
+		break;
+
+	case NAT46_XLATE_MAP:
+		if (!nss_connmgr_mapt_validate_rule_style_mapt(dev, &rule_pair->local, rule_num, true, stats)) {
+			return false;
+		}
+		break;
+
+	case NAT46_XLATE_RFC6052:
+		if (!nss_connmgr_mapt_validate_rule_style_rfc6052(dev, &rule_pair->local, rule_num, true, stats)) {
+			return false;
+		}
+		break;
+
+	default:
+		*stats |= 1 << MAP_T_LOCAL_STYLE_IS_NOT_MAP_T_OR_RFC6052;
+		return false;
+	}
+
+	/*
+	 * Validate remote rule parameters
+	 */
+	switch (rule_pair->remote.style) {
+	case NAT46_XLATE_MAP:
+		if (!nss_connmgr_mapt_validate_rule_style_mapt(dev, &rule_pair->remote, rule_num, false, stats)) {
+			return false;
+		}
+		break;
+
+	case NAT46_XLATE_RFC6052:
+		if (!nss_connmgr_mapt_validate_rule_style_rfc6052(dev, &rule_pair->remote, rule_num, false, stats)) {
+			return false;
+		}
+		break;
+
+	default:
+		*stats |= 1 << MAP_T_REMOTE_STYLE_IS_NOT_MAP_T_OR_RFC6052;
+		return false;
+	}
+
+	return true;
+}
+
+ /*
+ * nss_connmgr_map_t_ipv6_get_tclass()
+ * 	Get traffic class from IPv6 header.
+ */
+static inline uint8_t nss_connmgr_map_t_ipv6_get_tclass(struct ipv6hdr *ip6hdr)
+{
+	uint32_t verclassflow = ntohl(*(uint32_t *)ip6hdr);
+	return  (verclassflow & MAP_T_IPV6_CLASS_MASK) >>
+		 MAP_T_IPV6_CLASS_SHIFT;
+}
+
+/*
+ * nss_connmgr_map_t_ipv6_set_tclass()
+ * 	Set traffic class in IPv6 header.
+ */
+static inline void nss_connmgr_map_t_ipv6_set_tclass(struct ipv6hdr *ip6hdr, uint8_t tclass)
+{
+	uint32_t *ptr = (uint32_t *)ip6hdr;
+	uint32_t verclassflow = ntohl(*ptr);
+
+	verclassflow &= (uint32_t)~MAP_T_IPV6_CLASS_MASK;
+	verclassflow |= (tclass << MAP_T_IPV6_CLASS_SHIFT) & MAP_T_IPV6_CLASS_MASK;
+	*ptr = htonl(verclassflow);
+}
+
+/*
+ * nss_connmgr_map_t_decap_exception()
+ *	Exception handler registered to NSS for handling map_t ipv6 pkts
+ */
+static void nss_connmgr_map_t_decap_exception(struct net_device *dev,
+			struct sk_buff *skb,
+			__attribute__((unused)) struct napi_struct *napi)
+
+{
+	struct iphdr *ip4_hdr;
+	struct ipv6hdr *ip6_hdr;
+	uint32_t v4saddr = 0, v4daddr = 0;
+	struct ipv6hdr ip6_hdr_r;
+	uint8_t next_hdr, hop_limit, tclass, l4_proto;
+	int total_len;
+	uint32_t identifier = 0;
+	bool df_bit = false;
+	uint16_t skip_sz = 0;
+	struct nss_map_t_mdata *mdata;
+
+	mdata = (struct nss_map_t_mdata *)skb->data;
+
+	/* discard meta data header */
+	skb_pull(skb, sizeof(struct nss_map_t_mdata));
+	skb_reset_mac_header(skb);
+
+	skb_reset_network_header(skb);
+
+	ip6_hdr = ipv6_hdr(skb);
+	skb_set_transport_header(skb, sizeof(struct ipv6hdr));
+
+	/*
+	 * IPv4 packet is xlated to ipv6 packet by acceleration engine. But there is no ipv6 rule.
+	 * Call xlate_6_to_4() [ which is exported by nat46.ko ] to find original ipv4 src and ipv4 dest address.
+	 * These function is designed for packets from wan to lan. Since this packet is from lan, need to call
+	 * this function with parameters reversed. ipv6_hdr_r is used for reversing ip addresses.
+	 */
+	memcpy(&ip6_hdr_r.saddr, &ip6_hdr->daddr, sizeof(struct in6_addr));
+	memcpy(&ip6_hdr_r.daddr, &ip6_hdr->saddr, sizeof(struct in6_addr));
+
+	if (unlikely(!xlate_6_to_4(dev, &ip6_hdr_r, ip6_hdr->nexthdr, &v4saddr, &v4daddr))) {  /* packet needs to be xlated v6 to v4 */
+		nss_connmgr_map_t_warning("%px: Martian ipv6 packet !!..free it. (saddr=%pI6c daddr=%pI6c)\n", dev,\
+					  &ip6_hdr->saddr, &ip6_hdr->daddr);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	next_hdr = ip6_hdr->nexthdr;
+	total_len = sizeof(struct iphdr) + ntohs(ip6_hdr->payload_len);
+	hop_limit = ip6_hdr->hop_limit;
+	tclass = nss_connmgr_map_t_ipv6_get_tclass(ip6_hdr);
+
+	if (likely(next_hdr != NEXTHDR_FRAGMENT)) {
+
+		/*
+		 * Set DF bit
+		 */
+		df_bit = !!(mdata->flags & NSS_MAPT_MDATA_FLAG_DF_BIT);
+
+		l4_proto = next_hdr;
+	} else {
+		struct frag_hdr tmp_fh, *fh;
+		const __be32 *fh_addr = skb_header_pointer(skb, sizeof(struct ipv6hdr), sizeof(struct frag_hdr), &tmp_fh);
+		skip_sz = sizeof(struct frag_hdr);
+		if (!fh_addr) {
+			nss_connmgr_map_t_warning("%px: Not able to offset to frag header while v6 -->v4 xlate\n", dev);
+			dev_kfree_skb_any(skb);
+			return;
+		}
+
+		fh = (struct frag_hdr *)fh_addr;
+		identifier = ntohl(fh->identification);
+		l4_proto = fh->nexthdr;
+	}
+
+	skb_pull(skb, sizeof(struct ipv6hdr) + skip_sz - sizeof(struct iphdr));
+	skb_reset_network_header(skb);
+	skb_reset_mac_header(skb);
+
+	ip4_hdr = ip_hdr(skb);
+	memset(ip4_hdr, 0, sizeof(struct iphdr));
+
+	skb_set_transport_header(skb, sizeof(struct iphdr));
+	skb->protocol = htons(ETH_P_IP);
+
+	ip4_hdr->ihl = 5;
+	ip4_hdr->version = 4;
+	ip4_hdr->tot_len = htons(total_len - skip_sz);
+	ip4_hdr->ttl = hop_limit;
+	ip4_hdr->protocol = l4_proto;
+	ip4_hdr->saddr = v4daddr;
+	ip4_hdr->daddr = v4saddr;
+	ip4_hdr->tos = tclass;
+	if (unlikely(df_bit)) {
+		ip4_hdr->frag_off = htons(IP_DF);
+	}
+
+	if (unlikely(identifier)) {
+		ip4_hdr->id = htons(identifier & 0xffff);
+	} else {
+		/*
+		 * Generate the new identifier value and set it
+		 * in the IPv4 Identification field.
+		 */
+		__ip_select_ident(dev_net(dev), ip4_hdr, 1);
+	}
+
+	skb->pkt_type = PACKET_HOST;
+	skb->skb_iif = dev->ifindex;
+	skb->ip_summed = CHECKSUM_NONE;
+	skb->dev = dev;
+
+	nss_connmgr_map_t_trace("%px: ipv6 packet exceptioned after v4 ---> v6 xlate, created original ipv4 packet\n", dev);
+	nss_connmgr_map_t_trace("%px: Calculated ipv4 params: src_addr=0x%x dest_addr=0x%x totallen=%d\n", dev, ip4_hdr->saddr, ip4_hdr->daddr, total_len);
+
+	dev_queue_xmit(skb);
+	return;
+}
+
+/*
+ * nss_connmgr_map_t_encap_exception()
+ *	Exception handler registered to NSS for handling map_t ipv4 pkts
+ * Translates ipv4 packet back to ipv6 and send to nat46 device directly.
+ */
+static void nss_connmgr_map_t_encap_exception(struct net_device *dev,
+			struct sk_buff *skb,
+			__attribute__((unused)) struct napi_struct *napi)
+
+{
+	struct iphdr *ip4_hdr;
+	struct ipv6hdr *ip6_hdr;
+	uint8_t v6saddr[16], v6daddr[16];
+	struct tcphdr *tcph = NULL;
+	struct udphdr *udph = NULL;
+	struct iphdr ip4_hdr_r;
+	__be16 sport, dport;
+	uint8_t nexthdr, hop_limit, tos;
+	int payload_len;
+	bool df_bit = false;
+	uint16_t append_hdr_sz = 0;
+	uint16_t identifier;
+	uint32_t l4_csum, orig_csum;
+	uint16_t csum;
+
+	/*
+	 * Discard L2 header.
+	 */
+	skb_pull(skb, sizeof(struct ethhdr));
+	skb_reset_mac_header(skb);
+	skb_reset_network_header(skb);
+
+	ip4_hdr = ip_hdr(skb);
+	skb_set_transport_header(skb, ip4_hdr->ihl * 4);
+
+	if (ip4_hdr->protocol == IPPROTO_TCP) {
+		tcph = tcp_hdr(skb);
+		l4_csum = tcph->check;
+		sport = tcph->source;
+		dport = tcph->dest;
+	} else if (ip4_hdr->protocol == IPPROTO_UDP) {
+		udph = udp_hdr(skb);
+		orig_csum = l4_csum = udph->check;
+		sport = udph->source;
+		dport = udph->dest;
+	} else {
+		nss_connmgr_map_t_warning("%px: Unsupported protocol, free it up\n", dev);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	/*
+	 * Undo the checksum of the IPv4 source and destinationIPv4 address.
+	 */
+	csum = ip_compute_csum(&ip4_hdr->saddr, 2 * sizeof(ip4_hdr->saddr));
+	l4_csum += ((~csum) & 0xFFFF);
+
+	/*`
+	 * IPv6 packet is xlated to ipv4 packet by acceleration engine. But there is no ipv4 rule.
+	 * Call xlate_4_to_6() [ which is exported by nat46.ko ] to find original ipv6 src and ipv6 dest address.
+	 * These functions is designed for packets from lan to wan. Since this packet is from wan, need to call
+	 * this function with parameters reversed. ipv4_hdr_r is used for reversing ip addresses.
+	 */
+	ip4_hdr_r.daddr = ip4_hdr->saddr;
+	ip4_hdr_r.saddr = ip4_hdr->daddr;
+
+	if (unlikely(!xlate_4_to_6(dev, &ip4_hdr_r, dport, sport, v6saddr, v6daddr))) { /* exception happened after packet got xlated */
+		nss_connmgr_map_t_warning("%px: Martian ipv4 packet !!..free it. (saddr = 0x%x daddr = 0x%x sport = %d dport = %d)\n", dev,\
+					  ip4_hdr->saddr, ip4_hdr->daddr, sport, dport);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	nexthdr = ip4_hdr->protocol;
+	payload_len = ntohs(ip4_hdr->tot_len) - sizeof(struct iphdr);
+	hop_limit = ip4_hdr->ttl;
+	tos = ip4_hdr->tos;
+	identifier = ntohs(ip4_hdr->id);
+
+	if (ip4_hdr->frag_off & htons(IP_DF)) {
+		df_bit = true;
+	}  else if (map_t_flags & MAPT_FLAG_ADD_DUMMY_HDR) {
+		append_hdr_sz = sizeof(struct frag_hdr);
+	}
+
+	if (!pskb_may_pull(skb, sizeof(struct ipv6hdr) + append_hdr_sz - sizeof(struct iphdr))) {
+		nss_connmgr_map_t_warning("%px: Not enough headroom for ipv6 packet...Freeing the packet\n", dev);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	skb_push(skb, sizeof(struct ipv6hdr) + append_hdr_sz - sizeof(struct iphdr));
+	skb_reset_network_header(skb);
+	skb_reset_mac_header(skb);
+
+	skb->protocol = htons(ETH_P_IPV6);
+
+	ip6_hdr = ipv6_hdr(skb);
+	memset(ip6_hdr, 0, sizeof(struct ipv6hdr));
+
+	ip6_hdr->version = 6;
+	ip6_hdr->payload_len = htons(payload_len + append_hdr_sz);
+	ip6_hdr->hop_limit = hop_limit;
+
+	nss_connmgr_map_t_ipv6_set_tclass(ip6_hdr, tos);
+	memcpy(&ip6_hdr->daddr, v6saddr, sizeof(struct in6_addr));
+	memcpy(&ip6_hdr->saddr, v6daddr, sizeof(struct in6_addr));
+
+	if (unlikely(df_bit) || !(map_t_flags & MAPT_FLAG_ADD_DUMMY_HDR))  {
+		ip6_hdr->nexthdr = nexthdr;
+	} else {
+		struct frag_hdr tmp_fh, *fh;
+		const __be32 *fh_addr = skb_header_pointer(skb, sizeof(struct ipv6hdr), sizeof(struct frag_hdr), &tmp_fh);
+		if (!fh_addr) {
+			nss_connmgr_map_t_warning("%px: Not able to offset to frag header\n", dev);
+			dev_kfree_skb_any(skb);
+			return;
+		}
+		fh = (struct frag_hdr *)fh_addr;
+		memset(fh, 0, sizeof(struct frag_hdr));
+		fh->identification = htonl(identifier);
+		fh->nexthdr = nexthdr;
+		ip6_hdr->nexthdr = NEXTHDR_FRAGMENT;
+	}
+
+	skb_set_transport_header(skb, sizeof(struct ipv6hdr) + append_hdr_sz);
+
+	/*
+	 * Add the checksum of the IPv6 source and destination address.
+	 */
+	l4_csum += ip_compute_csum(ip6_hdr->saddr.s6_addr16, 2 * sizeof(ip6_hdr->saddr));
+	/*
+	 * Fold the 32 bits checksum to 16 bits
+	 */
+	l4_csum = (l4_csum & 0x0000FFFF) + (l4_csum >> 16);
+	l4_csum = (l4_csum & 0x0000FFFF) + (l4_csum >> 16);
+
+	if (nexthdr == IPPROTO_TCP) {
+		tcph->check = (uint16_t)l4_csum;
+	} else {
+		udph->check = (orig_csum == 0)? 0:(uint16_t)l4_csum;
+	}
+
+	skb->pkt_type = PACKET_HOST;
+	skb->skb_iif = dev->ifindex;
+	skb->ip_summed = CHECKSUM_NONE;
+	skb->dev = dev;
+
+	nss_connmgr_map_t_trace("%p: ipv4 packet exceptioned after v6 ---> v4 xlate, created original ipv6 packet\n", dev);
+	nss_connmgr_map_t_trace("%p: Calculted ipv6 params: src_addr=%pI6, dest_addr=%pI6, payload_len=%d, checksum=%x\n", dev, v6saddr, v6daddr, payload_len, l4_csum);
+
+	dev_queue_xmit(skb);
+	return;
+}
+
+/*
+ * nss_map_t_update_dev_stats()
+ */
+void nss_map_t_update_dev_stats(struct net_device *dev, struct nss_map_t_sync_stats_msg *sync_stats)
+{
+	if (!dev) {
+		nss_connmgr_map_t_warning("dev is null\n");
+		return;
+	}
+
+	dev_hold(dev);
+
+	nat46_update_stats(dev,
+		sync_stats->node_stats.rx_packets,
+		sync_stats->node_stats.rx_bytes,
+		sync_stats->node_stats.tx_packets,
+		sync_stats->node_stats.tx_bytes,
+		nss_cmn_rx_dropped_sum(&sync_stats->node_stats),
+		sync_stats->tx_dropped);
+
+	dev_put(dev);
+}
+
+/*
+ * nss_connmgr_map_t_event_receive()
+ *	Event Callback to receive events from NSS
+ */
+static void nss_connmgr_map_t_event_receive(void *if_ctx, struct nss_map_t_msg *tnlmsg)
+{
+	struct net_device *netdev = if_ctx;
+
+	switch (tnlmsg->cm.type) {
+	case NSS_MAP_T_MSG_SYNC_STATS:
+		nss_map_t_update_dev_stats(netdev, (struct nss_map_t_sync_stats_msg *)&tnlmsg->msg.stats);
+		break;
+
+	default:
+		nss_connmgr_map_t_info("%px: Unknown Event from NSS\n", netdev);
+		break;
+	}
+}
+
+/*
+ * nss_connmgr_map_t_dev_up()
+ */
+static int nss_connmgr_map_t_dev_up(struct net_device *dev)
+{
+	struct nat46_xlate_rulepair *rule_pairs;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_map_t_msg maptmsg;
+	struct nss_map_t_instance_rule_config_msg *maptcfg;
+	int rule_pair_count = 0;
+	int if_inner, if_outer;
+	nss_tx_status_t status;
+	uint32_t features = 0;
+	int i, j;
+	uint64_t map_t_rule_validation_stats;
+
+	/*
+	 * Get MAP-T interface's information.
+	 */
+	if (!nat46_get_info(dev, &rule_pairs, &rule_pair_count, &map_t_flags)) {
+		nss_connmgr_map_t_warning("%px: Failed to get ruleset on map-t netdevice (%s)\n", dev, dev->name);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Return, if number of  rules configured for the map-t
+	 * interface is < 1 or > 64
+	 */
+
+	if (rule_pair_count < MAP_T_MIN_NUM_RULES_PER_MAP_T_INSTANCE || rule_pair_count > MAP_T_MAX_NUM_RULES_PER_MAP_T_INSTANCE) {
+		nss_connmgr_map_t_warning("%px: No accleration supported if number of rules configured is %d\n", dev, rule_pair_count);
+		return NOTIFY_DONE;
+	}
+
+	if (mapt_interfaces_count == NSS_MAX_MAP_T_DYNAMIC_INTERFACES) {
+		nss_connmgr_map_t_warning("%px: Max number of mapt interfaces supported is %d\n", dev, NSS_MAX_MAP_T_DYNAMIC_INTERFACES);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Create MAP-T inner dynamic interface
+	 */
+	if_inner = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_INNER);
+	if (if_inner < 0) {
+		nss_connmgr_map_t_warning("%px: Request interface number failed\n", dev);
+		return NOTIFY_DONE;
+	}
+	nss_connmgr_map_t_info("%px: encap nss_dynamic_interface_alloc_node() successful. if_number = %d\n", dev, if_inner);
+
+	/*
+	 * Create MAP-T outer dynamic interface
+	 */
+	if_outer = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_OUTER);
+	if (if_outer < 0) {
+		nss_connmgr_map_t_warning("%px: Request interface number failed\n", dev);
+		goto outer_alloc_fail;
+	}
+	nss_connmgr_map_t_info("%px: decap nss_dynamic_interface_alloc_node() successful. if_number = %d\n", dev, if_outer);
+
+	/*
+	 * Register MAP-T encap interface with NSS
+	 */
+	nss_ctx = nss_map_t_register_if(if_inner,
+			NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_INNER,
+			nss_connmgr_map_t_encap_exception,
+			nss_connmgr_map_t_event_receive,
+			dev,
+			features);
+
+	if (!nss_ctx) {
+		nss_connmgr_map_t_warning("%px: encap nss_register_map_t_if failed\n", dev);
+		goto inner_register_fail;
+	}
+	nss_connmgr_map_t_info("%px: encap nss_register_map_t_if() successful. nss_ctx = %px\n", dev, nss_ctx);
+
+	/*
+	 * Register MAP-T decap interface with NSS
+	 */
+	nss_ctx = nss_map_t_register_if(if_outer,
+			NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_OUTER,
+			nss_connmgr_map_t_decap_exception,
+			nss_connmgr_map_t_event_receive,
+			dev,
+			features);
+
+	if (!nss_ctx) {
+		nss_connmgr_map_t_warning("%px: decap nss_register_map_t_if failed\n", dev);
+		goto outer_register_fail;
+	}
+
+	/*
+	 * allocate needed data structures
+	 */
+	nss_connmgr_map_t_allocate_all(dev, rule_pairs, rule_pair_count);
+
+	/*
+	 * Send Rule configuration to acceleration engine.
+	 */
+	for (i = 0; i < rule_pair_count; i++) {
+		map_t_rule_validation_stats = 0;
+
+		memset(&maptmsg, 0, sizeof(struct nss_map_t_msg));
+		maptcfg = &maptmsg.msg.create_msg;
+
+		/*
+		 * These info is used by nss to decide if all rules are
+		 * sent to accleration engine. ie rule_num == rule_pair_count
+		 */
+		maptcfg->rule_num = i + 1;
+		maptcfg->total_rules = rule_pair_count;
+
+		/*
+		 * Set local rule params
+		 */
+		maptcfg->local_map_style = (rule_pairs + i)->local.style;
+
+		for (j = 0; j < 4; j++) {
+			*((uint32_t *)(&maptcfg->local_ipv6_prefix) + j) = ntohl(*((uint32_t *)((rule_pairs + i)->local.v6_pref.s6_addr) + j));
+		}
+		maptcfg->local_ipv6_prefix_len = (rule_pairs + i)->local.v6_pref_len;
+
+		maptcfg->local_ipv4_prefix = ntohl((rule_pairs + i)->local.v4_pref);
+		maptcfg->local_ipv4_prefix_len = (rule_pairs + i)->local.v4_pref_len;
+		maptcfg->local_ea_len = (rule_pairs + i)->local.ea_len;
+		maptcfg->local_psid_offset = (rule_pairs + i)->local.psid_offset;
+
+		maptcfg->valid_rule = 1;
+
+		/*
+		 * Set remote rule params
+		 */
+		maptcfg->remote_map_style = (rule_pairs + i)->remote.style;
+		for (j = 0; j < 4; j++) {
+			*((uint32_t *)(&maptcfg->remote_ipv6_prefix) + j) = ntohl(*((uint32_t *)((rule_pairs + i)->remote.v6_pref.s6_addr) + j));
+		}
+		maptcfg->remote_ipv6_prefix_len = (rule_pairs + i)->remote.v6_pref_len;
+
+		maptcfg->remote_ipv4_prefix = ntohl((rule_pairs + i)->remote.v4_pref);
+		maptcfg->remote_ipv4_prefix_len = (rule_pairs + i)->remote.v4_pref_len;
+		maptcfg->remote_ea_len = (rule_pairs + i)->remote.ea_len;
+		maptcfg->remote_psid_offset = (rule_pairs + i)->remote.psid_offset;
+
+		/*
+		 * check correctness of a map-t rule
+		 */
+		maptcfg->valid_rule = nss_connmgr_mapt_check_correctness_of_mapt_rule(dev, rule_pairs + i, i, &map_t_rule_validation_stats);
+
+		/*
+		 * Debugfs stats file <debug-fs-dir>/map-t helps to figure out
+		 * goodness of a map-t rule. All bits should be 0, if rule is good
+		 * and valid.
+		 */
+		if (unlikely(!maptcfg->valid_rule)) {
+			map_t_rule_validation_stats |= 1 << MAP_T_INVALID_RULE;
+		}
+
+		/*
+		 * set the sibling interface number
+		 */
+		maptcfg->sibling_if = if_outer;
+
+		/*
+		 * set MAP-T flags
+		 */
+		maptcfg->flags = map_t_flags;
+
+		/*
+		 * Send configure message to MAP-T encap interface.
+		 */
+		nss_map_t_msg_init(&maptmsg, if_inner, NSS_MAP_T_MSG_INSTANCE_RULE_CONFIGURE, sizeof(struct nss_map_t_instance_rule_config_msg), NULL, NULL);
+		status = nss_map_t_tx_sync(nss_ctx, &maptmsg);
+		if (status != NSS_TX_SUCCESS) {
+			nss_connmgr_map_t_warning("%px: nss encap MAP-T instance configure command error %d\n", dev, status);
+
+			map_t_rule_validation_stats |= ((uint64_t)(1)) << (64 - MAPT_AE_ERR_CONFIGURE);
+			nss_connmgr_map_t_debugfs_set_rule_status(dev, i + 1, map_t_rule_validation_stats);
+
+			goto config_fail;
+		}
+
+		nss_connmgr_map_t_debugfs_set_rule_status(dev, i + 1, map_t_rule_validation_stats);
+		nss_connmgr_map_t_info("%px: encap nss_map_t_tx() rule #%d configuration successful\n", dev, i + 1);
+
+		/*
+		 * set the sibling interface number
+		 */
+		maptcfg->sibling_if = if_inner;
+
+		/*
+		 * Send configure message to MAP-T decap interface.
+		 */
+		nss_map_t_msg_init(&maptmsg, if_outer, NSS_MAP_T_MSG_INSTANCE_RULE_CONFIGURE, sizeof(struct nss_map_t_instance_rule_config_msg), NULL, NULL);
+		status = nss_map_t_tx_sync(nss_ctx, &maptmsg);
+		if (status != NSS_TX_SUCCESS) {
+			nss_connmgr_map_t_warning("%px: nss decap MAP-T instance configure command error %d\n", dev, status);
+
+			map_t_rule_validation_stats |= ((uint64_t)(1)) << (64 - MAPT_AE_ERR_CONFIGURE);
+			nss_connmgr_map_t_debugfs_set_rule_status(dev, i + 1, map_t_rule_validation_stats);
+
+			goto config_fail;
+		}
+
+		nss_connmgr_map_t_debugfs_set_rule_status(dev, i + 1, map_t_rule_validation_stats);
+		nss_connmgr_map_t_info("%px: decap nss_map_t_tx() rule #%d configuration successful\n", dev, i + 1);
+	}
+
+	/*
+	 * Increment map-t interface count
+	 */
+	mapt_interfaces_count++;
+	nss_connmgr_map_t_info("%px: MAP-T interface count is #%d\n", dev, mapt_interfaces_count);
+
+	return NOTIFY_DONE;
+
+config_fail:
+	nss_connmgr_map_t_free_all(dev);
+	nss_map_t_unregister_if(if_outer);
+outer_register_fail:
+	nss_map_t_unregister_if(if_inner);
+inner_register_fail:
+	status = nss_dynamic_interface_dealloc_node(if_outer, NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_OUTER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_map_t_warning("%px: Unable to dealloc the decap node[%d] in the NSS FW!\n", dev, if_outer);
+	}
+outer_alloc_fail:
+	status = nss_dynamic_interface_dealloc_node(if_inner, NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_INNER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_map_t_warning("%px: Unable to dealloc the encap node[%d] in the NSS FW!\n", dev, if_inner);
+	}
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_connmgr_map_t_dev_down()
+ */
+static int nss_connmgr_map_t_dev_down(struct net_device *dev)
+{
+	int if_inner, if_outer;
+	nss_tx_status_t status;
+	struct nss_map_t_msg maptmsg;
+	struct nss_map_t_instance_rule_deconfig_msg *maptcfg;
+
+	/*
+	 * Check if MAP-T encap interface is registered with NSS
+	 */
+	if_inner = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_INNER);
+	if (if_inner < 0) {
+		nss_connmgr_map_t_warning("%px: MAP-T encap net device is not registered with nss\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Check if MAP-T decap interface is registered with NSS
+	 */
+	if_outer = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_OUTER);
+	if (if_outer < 0) {
+		nss_connmgr_map_t_warning("%px: MAP-T decap net device is not registered with nss\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Free all allocated data structures.
+	 */
+	nss_connmgr_map_t_free_all(dev);
+
+	memset(&maptmsg, 0, sizeof(struct nss_map_t_msg));
+	maptcfg = &maptmsg.msg.destroy_msg;
+	maptcfg->if_number = if_inner;
+
+	/*
+	 * Send deconfigure message to MAP-T encap interface.
+	 */
+	nss_map_t_msg_init(&maptmsg, if_inner, NSS_MAP_T_MSG_INSTANCE_RULE_DECONFIGURE, sizeof(struct nss_map_t_instance_rule_deconfig_msg), NULL, NULL);
+	status = nss_map_t_tx_sync(nss_map_t_get_context(), &maptmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_map_t_warning("%px: map_t encap instance deconfigure command failed, if_number = %d\n", dev, if_inner);
+		return NOTIFY_DONE;
+	}
+
+	memset(&maptmsg, 0, sizeof(struct nss_map_t_msg));
+	maptcfg = &maptmsg.msg.destroy_msg;
+	maptcfg->if_number = if_outer;
+
+	/*
+	 * Send deconfigure message to MAP-T decap interface.
+	 */
+	nss_map_t_msg_init(&maptmsg, if_outer, NSS_MAP_T_MSG_INSTANCE_RULE_DECONFIGURE, sizeof(struct nss_map_t_instance_rule_deconfig_msg), NULL, NULL);
+	status = nss_map_t_tx_sync(nss_map_t_get_context(), &maptmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_map_t_warning("%px: map_t decap instance deconfigure command failed, if_number = %d\n", dev, if_outer);
+		return NOTIFY_DONE;
+	}
+
+	nss_map_t_unregister_if(if_inner);
+	nss_map_t_unregister_if(if_outer);
+
+	status = nss_dynamic_interface_dealloc_node(if_inner, NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_INNER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_map_t_warning("%px: map_t encap dealloc node failure for if_number = %d\n", dev, if_inner);
+		return NOTIFY_DONE;
+	}
+	nss_connmgr_map_t_info("%px: deleted map_t encap instance, if_number = %d\n", dev, if_inner);
+
+	status = nss_dynamic_interface_dealloc_node(if_outer, NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_OUTER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_map_t_warning("%px: map_t decap dealloc node failure for if_number = %d\n", dev, if_outer);
+		return NOTIFY_DONE;
+	}
+	nss_connmgr_map_t_info("%px: deleted map_t decap instance, if_number = %d\n", dev, if_outer);
+
+	/*
+	 * Decrement interface count
+	 */
+	mapt_interfaces_count--;
+	nss_connmgr_map_t_info("%px: MAP-T interface count is #%d\n", dev, mapt_interfaces_count);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_connmgr_map_t_dev_event()
+ *	Net device notifier for nss map_t module
+ */
+static int nss_connmgr_map_t_dev_event(struct notifier_block *nb,
+		unsigned long event, void *dev)
+{
+	struct net_device *netdev;
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 10, 0))
+	netdev = (struct net_device *)dev;
+#else
+	netdev = netdev_notifier_info_to_dev(dev);
+#endif
+
+	/*
+	 * Check for map-t device
+	 */
+	if (!is_map_t_dev(netdev)) {
+		return NOTIFY_DONE;
+	}
+
+	switch (event) {
+	case NETDEV_UP:
+		return nss_connmgr_map_t_dev_up(netdev);
+
+	case NETDEV_DOWN:
+		return nss_connmgr_map_t_dev_down(netdev);
+
+	default:
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * map_t_debugfs_read()
+ *	Read function of <DEBUGFS>/map-t entry
+ *
+ * map-t client code does a map-t rule validation before pushing ae-engine
+ * rules. This helps to easily figure out problems in rules and hence quick
+ * debuggging. <DEBUG-FS-DIR>/map-t has a 64bit value for each rule. All
+ * bits '0' indicate that there is no validation error.
+ */
+static ssize_t map_t_debugfs_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos)
+{
+	struct list_head *list_head_ptr = file->private_data;
+	struct list_dev_to_map_t_rules_entry_t *entry;
+	char *buf;
+	int total_rules = 0;
+	int num_net_devices = 0;
+	int user_copy_len = 0;
+	int err = -EFAULT;
+
+	/*
+	 * Process context should sleep if the netdevice is going down and
+	 * list_head_ptr is being emptied so that 'cat' of this debugfs
+	 * entry won't race in smp
+	 */
+	rtnl_lock();
+
+	/*
+	 * Allocate memory
+	 */
+	list_for_each_entry(entry, list_head_ptr, list) {
+		total_rules += entry->rule_pair_count;
+		num_net_devices++;
+	}
+
+	/*
+	 * Allocate buffer
+	 */
+	buf = kzalloc((MAP_T_NETDEVICE_SZ * num_net_devices) + (MAP_T_RULE_SZ * total_rules) + 1, GFP_KERNEL);
+	if (!buf) {
+		rtnl_unlock();
+		return err;
+	}
+
+	list_for_each_entry(entry, list_head_ptr, list) {
+		int i;
+		int copied_len;
+		copied_len = scnprintf(buf + user_copy_len, MAP_T_NETDEVICE_SZ, "netdevice = %s\n", entry->dev->name);
+		if (unlikely(copied_len == -1)) {
+			kfree(buf);
+			rtnl_unlock();
+			return err;
+		}
+		user_copy_len += copied_len;
+
+		for (i = 0; i < entry->rule_pair_count; i++) {
+
+			copied_len = scnprintf(buf + user_copy_len, MAP_T_RULE_SZ, "%d: 0x%016llx\n",
+					      i + 1, entry->rule_status[i]);
+
+			if (unlikely(copied_len == -1)) {
+				kfree(buf);
+				rtnl_unlock();
+				return err;
+			}
+			user_copy_len += copied_len;
+		}
+	}
+
+	err = simple_read_from_buffer(user_buf, count, ppos, buf, user_copy_len);
+	kfree(buf);
+	rtnl_unlock();
+	return err;
+}
+
+/*
+ * debugfs file ops structure
+ */
+static const struct file_operations map_t_debugfs_fops = {
+	.open = simple_open,
+	.read = map_t_debugfs_read,
+};
+
+/*
+ * Linux Net device Notifier
+ */
+struct notifier_block nss_connmgr_map_t_notifier = {
+	.notifier_call = nss_connmgr_map_t_dev_event,
+};
+
+/*
+ * nss_connmgr_map_t_init_module()
+ *	map_t module init function
+ */
+int __init nss_connmgr_map_t_init_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+
+	map_t_debugfs = debugfs_create_file("map-t", 0444, NULL, &list_dev_to_map_t_rules_head, &map_t_debugfs_fops);
+
+	register_netdevice_notifier(&nss_connmgr_map_t_notifier);
+	return 0;
+}
+
+/*
+ * nss_connmgr_map_t_exit_module
+ *	map_t module exit function
+ */
+void __exit nss_connmgr_map_t_exit_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return;
+	}
+#endif
+
+	if (map_t_debugfs) {
+		debugfs_remove(map_t_debugfs);
+	}
+
+	unregister_netdevice_notifier(&nss_connmgr_map_t_notifier);
+}
+
+module_init(nss_connmgr_map_t_init_module);
+module_exit(nss_connmgr_map_t_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS map_t offload manager");
diff --git a/qca-nss-clients/map/map-t/nss_connmgr_map_t.h b/qca-nss-clients/map/map-t/nss_connmgr_map_t.h
new file mode 100644
index 0000000..6956513
--- /dev/null
+++ b/qca-nss-clients/map/map-t/nss_connmgr_map_t.h
@@ -0,0 +1,84 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_connnmgr_map_t.h
+ *
+ * Header file implementation of nss_connnmgr_map_t.c
+ */
+#ifndef _NSS_CONNMGR_MAP_T_H_
+#define _NSS_CONNMGR_MAP_T_H_
+
+/*
+ * Restrict max number of rules that can be configured for
+ * a MAP-T device
+ */
+#define MAP_T_MAX_NUM_RULES_PER_MAP_T_INSTANCE 64
+#define MAP_T_MIN_NUM_RULES_PER_MAP_T_INSTANCE 1
+
+/*
+ * MAP-T Flag.
+ */
+#define MAPT_FLAG_ADD_DUMMY_HDR 0x01
+
+struct list_dev_to_map_t_rules_entry_t {
+	struct list_head list;					/* list head */
+	struct net_device *dev;					/* net device */
+	struct nat46_xlate_rulepair *rule_set;			/* rule set */
+	uint64_t *rule_status;					/* rule validation status */
+	uint64_t rule_pair_count;				/* number of rules */
+};
+
+struct list_lookup_entry_t {
+	struct list_head list;				/* ipv6 address list */
+	struct nat46_xlate_rulepair *ptr_rule_set;	/* rule set */
+};
+
+struct list_ipv6_address_entry_t {
+	struct in6_addr addr;	/* ipv6 address */
+	u32 prefix_len;		/* prefix length */
+	struct list_head list;	/* list head */
+};
+
+/*
+ * Below enum indicates bits position in <DEBUG-FS>/map-t file. Each bit
+ * reperesent an error of map-t rule. If all bits zero represents goodness
+ * of a map-t rule
+ */
+enum {
+	MAP_T_LOCAL_EA_BITS_LEN_IS_INVALID = 0,
+	MAP_T_LOCAL_PSID_LEN_PLUS_PSID_OFFSET_IS_GREATER_THAN_16,
+	MAP_T_LOCAL_IPV6_PREFIX_LEN_IS_NOT_32_40_48_56_64_OR_96,
+	MAP_T_LOCAL_STYLE_IS_NOT_MAP_T_OR_RFC6052,
+	MAP_T_REMOTE_EA_BITS_LEN_IS_INVALID,
+	MAP_T_REMOTE_PSID_LEN_PLUS_REMOTE_PSID_OFFSET_IS_GREATER_THAN_16,
+	MAP_T_REMOTE_IPV6_PREFIX_LEN_IS_NOT_32_40_48_56_64_OR_96,
+	MAP_T_NO_IPV6_END_USER_PREFIX,
+	MAP_T_REMOTE_STYLE_IS_NOT_MAP_T_OR_RFC6052,
+	MAP_T_INVALID_RULE,
+	MAP_T_RULE_ERROR_MAX,
+};
+
+/*
+ *  AE configure/deconfigure errors
+ */
+enum {
+	MAPT_AE_ERR_CONFIGURE = 1,		/* Error while configuring */
+	MAPT_AE_ERR_DECONFIGURE,		/* Error while deconfiguring */
+	MAPT_AE_ERR_MAX				/* Max error */
+};
+
+#endif
diff --git a/qca-nss-clients/match/Makefile b/qca-nss-clients/match/Makefile
new file mode 100644
index 0000000..5cb9b63
--- /dev/null
+++ b/qca-nss-clients/match/Makefile
@@ -0,0 +1,11 @@
+# Makefile for match
+ccflags-y := -I$(obj)/../exports -I$(obj)/.. \
+	-DNSS_CLIENT_BUILD_ID="$(BUILD_ID)" -DNSS_MATCH_DEBUG_LEVEL=2 -Wall -Werror
+
+obj-m += qca-nss-match.o
+qca-nss-match-objs := nss_match.o
+qca-nss-match-objs += nss_match_cmd.o
+qca-nss-match-objs += nss_match_db.o
+qca-nss-match-objs += nss_match_l2.o
+qca-nss-match-objs += nss_match_stats.o
+qca-nss-match-objs += nss_match_vow.o
diff --git a/qca-nss-clients/match/nss_match.c b/qca-nss-clients/match/nss_match.c
new file mode 100644
index 0000000..36424bc
--- /dev/null
+++ b/qca-nss-clients/match/nss_match.c
@@ -0,0 +1,524 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+/*
+ * nss_match.c
+ */
+
+#include "nss_match_cmd.h"
+#include "nss_match_db.h"
+#include "nss_match_vow.h"
+#include "nss_match_l2.h"
+#include "nss_match_priv.h"
+#include <linux/types.h>
+#include <nss_api_if.h>
+#include <linux/debugfs.h>
+#include <linux/of.h>
+
+/*
+ * nss_match_verify_config_msg()
+ * 	Verify configuration message.
+ */
+static nss_match_status_t nss_match_verify_config_msg(struct nss_match_profile_configure_msg *config_msg)
+{
+	int mask, valid_mask_word;
+	int index, invalid_word_count = 0;
+
+	switch (config_msg->profile_type) {
+	case NSS_MATCH_PROFILE_TYPE_VOW:
+		valid_mask_word = 1;
+		break;
+	case NSS_MATCH_PROFILE_TYPE_L2:
+		valid_mask_word = 4;
+		break;
+	default:
+		nss_match_warn("Invalid profile type: %d.\n", config_msg->profile_type);
+		return NSS_MATCH_ERROR_PROFILE_CONFIG_INVALID;
+	}
+
+	for (mask = 0; mask < NSS_MATCH_MASK_MAX; mask++) {
+		if ((config_msg->valid_mask_flag) & (1 << mask)) {
+			for (index = 0; index < valid_mask_word; index++) {
+				if (!config_msg->maskset[mask][index]) {
+					invalid_word_count++;
+				}
+			}
+
+			/*
+			 * If all words of mask is null.
+			 */
+			if (invalid_word_count == valid_mask_word) {
+				nss_match_warn("Invalid mask for valid_mask_flag: %d\n", config_msg->valid_mask_flag);
+				return NSS_MATCH_ERROR_PROFILE_CONFIG_INVALID;
+			}
+		}
+	}
+
+	return NSS_MATCH_SUCCESS;
+}
+
+/*
+ * nss_match_sync_callback()
+ * 	Sync callback for syncing stats.
+ */
+static void nss_match_sync_callback(void *app_data, struct nss_match_msg *nmm)
+{
+	struct nss_ctx_instance *nss_ctx = nss_match_get_context();
+
+	switch (nmm->cm.type) {
+	case NSS_MATCH_STATS_SYNC:
+		nss_match_stats_table_sync(nss_ctx, &nmm->msg.stats, nmm->cm.interface);
+		return;
+	default:
+		nss_match_warn("%px: Unknown Event from NSS", nmm);
+		return;
+	}
+}
+
+/*
+ * nss_match_rule_delete()
+ * 	User API to delete the match rule.
+ */
+nss_match_status_t nss_match_rule_delete(struct nss_ctx_instance *nss_ctx, uint32_t rule_id, uint32_t table_id)
+{
+	struct nss_match_msg matchm;
+	struct nss_match_rule_info rule;
+	uint32_t profile_type, len;
+	int if_num;
+	enum nss_match_msg_types type;
+	nss_tx_status_t nss_tx_status;
+
+	if ((rule_id == 0) || (rule_id > NSS_MATCH_INSTANCE_RULE_MAX)) {
+		nss_match_warn("%px: rule_id doesnot exist, rule_id = %d", nss_ctx, rule_id);
+		return NSS_MATCH_ERROR_RULE_ID_OUTOFBOUND;
+	}
+
+	if (!nss_match_db_table_validate(table_id)) {
+		nss_match_warn("%px: Invalid table_id %d", nss_ctx, table_id);
+		return NSS_MATCH_ERROR_TABLE_ID_OUTOFBOUND;
+	}
+
+	if_num = nss_match_get_ifnum_by_table_id(table_id);
+	if (if_num < 0) {
+		nss_match_warn("%px: Invalid table_id %d", nss_ctx, table_id);
+		return NSS_MATCH_ERROR_TABLE_ID_OUTOFBOUND;
+	}
+
+	/*
+	 * Read the rule information
+	 */
+	if (!nss_match_db_rule_read(&rule, table_id, rule_id)) {
+		nss_match_warn("%px: rule_id does not exist, rule_id = %d", nss_ctx, rule_id);
+		return NSS_MATCH_ERROR_RULE_ID_OUTOFBOUND;
+	}
+
+	nss_match_db_get_profile_type(table_id, &profile_type);
+
+	switch (profile_type) {
+	case NSS_MATCH_PROFILE_TYPE_VOW:
+		type = NSS_MATCH_DELETE_VOW_RULE_MSG;
+		len = sizeof(struct nss_match_rule_vow_msg);
+		matchm.msg.vow_rule = rule.profile.vow;
+		break;
+	case NSS_MATCH_PROFILE_TYPE_L2:
+		type = NSS_MATCH_DELETE_L2_RULE_MSG;
+		len = sizeof(struct nss_match_rule_l2_msg);
+		matchm.msg.l2_rule = rule.profile.l2;
+		break;
+	default:
+		nss_match_warn("%px: Unknown profile type: %d", nss_ctx, profile_type);
+		return NSS_MATCH_ERROR_UNKNOWN_MSG;
+	}
+
+	nss_match_msg_init(&matchm, if_num, type, len, NULL, NULL);
+
+	nss_tx_status = nss_match_msg_tx_sync(nss_ctx, &matchm);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_match_warn("%px: Sending delete rule failed, rule_id = %d, status = %d", nss_ctx, rule_id, nss_tx_status);
+		return NSS_MATCH_ERROR_RULE_DELETE;
+	}
+
+	nss_match_db_rule_delete(table_id, rule_id);
+	return NSS_MATCH_SUCCESS;
+}
+EXPORT_SYMBOL(nss_match_rule_delete);
+
+/*
+ * nss_match_get_ifnum_by_table_id()
+ *	Returns interface number using table ID.
+ */
+int nss_match_get_ifnum_by_table_id(uint32_t table_id)
+{
+	if (table_id == 0 || table_id > NSS_MATCH_INSTANCE_MAX) {
+		nss_match_warn("Invalid table_id %d.\n", table_id);
+		return -1;
+	}
+
+	return nss_match_db_get_ifnum_by_table_id(table_id);
+}
+EXPORT_SYMBOL(nss_match_get_ifnum_by_table_id);
+
+/*
+ * nss_match_vow_rule_add()
+ * 	User API to add VoW rule.
+ */
+int nss_match_vow_rule_add(struct nss_ctx_instance *nss_ctx, struct nss_match_rule_vow_msg *rule_msg, uint32_t table_id)
+{
+	int rule_id = -1, if_num;
+	struct nss_match_msg nmm;
+	struct nss_match_rule_info rule;
+	enum nss_match_msg_types type = NSS_MATCH_ADD_VOW_RULE_MSG;
+	nss_tx_status_t nss_tx_status;
+
+	if (!nss_match_db_table_validate(table_id)) {
+		nss_match_warn("%px: Invalid table_id %d, table is not configured.\n", nss_ctx, table_id);
+		return rule_id;
+	}
+
+	if_num = nss_match_get_ifnum_by_table_id(table_id);
+	if (if_num < 0) {
+		nss_match_warn("%px: Cannot add the rule, table doesnot exist", nss_ctx);
+		return rule_id;
+	}
+
+	rule.profile.vow = *rule_msg;
+
+	if (nss_match_db_rule_find(&rule, table_id)) {
+		nss_match_warn("%px: Rule exists already. \n", nss_ctx);
+		return -1;
+	}
+
+	rule_id = nss_match_db_generate_rule_id(table_id);
+	if (rule_id <= 0 ) {
+		nss_match_warn("%px: Reached limit, New rule can't be added. \n", nss_ctx);
+		return -1;
+	}
+
+	rule.profile.vow.rule_id = rule_id;
+	nss_match_db_rule_add(&rule, table_id);
+
+	nss_match_msg_init(&nmm, if_num, type, sizeof(struct nss_match_rule_vow_msg), NULL, NULL);
+
+	nmm.msg.vow_rule = rule.profile.vow;
+	nmm.cm.type = type;
+
+	/*
+	 * Send the message to FW to add the VoW rule into the rule table.
+	 */
+	nss_tx_status = nss_match_msg_tx_sync(nss_ctx, &nmm);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_match_warn("%px:add rule failed from NSS, rule_id = %d, nss_tx_status = %d\n",
+				nss_ctx, rule_id, nss_tx_status);
+		nss_match_db_rule_delete(table_id, rule_id);
+		return -1;
+	}
+
+	return rule_id;
+}
+EXPORT_SYMBOL(nss_match_vow_rule_add);
+
+/*
+ * nss_match_l2_rule_add()
+ * 	User API to add rule for L2 profile.
+ */
+int nss_match_l2_rule_add(struct nss_ctx_instance *nss_ctx, struct nss_match_rule_l2_msg *rule_msg, uint32_t table_id)
+{
+	int rule_id = -1, if_num;
+	enum nss_match_msg_types type = NSS_MATCH_ADD_L2_RULE_MSG;
+	struct nss_match_msg nmm;
+	struct nss_match_rule_info rule;
+	nss_tx_status_t nss_tx_status;
+
+	if (!nss_match_db_table_validate(table_id)) {
+		nss_match_warn("%px: Cannot insert rule, table: %d is not configured. \n", nss_ctx, table_id);
+		return -1;
+	}
+
+	if_num = nss_match_get_ifnum_by_table_id(table_id);
+	if (if_num < 0) {
+		nss_match_warn("%px: Cannot add the rule, invalid table ID: %d", nss_ctx, table_id);
+		return rule_id;
+	}
+
+	rule.profile.l2 = *rule_msg;
+
+	if (nss_match_db_rule_find(&rule, table_id)) {
+		nss_match_warn("%px: Rule exists already \n", nss_ctx);
+		return -1;
+	}
+
+	rule_id = nss_match_db_generate_rule_id(table_id);
+	if (rule_id <= 0) {
+		nss_match_warn("%px: New rule can't be added, Reached limit. \n", nss_ctx);
+		return -1;
+	}
+
+	rule.profile.l2.rule_id = rule_id;
+	nss_match_db_rule_add(&rule, table_id);
+
+	nss_match_msg_init(&nmm, if_num, type, sizeof(struct nss_match_rule_l2_msg), NULL, NULL);
+
+	nmm.msg.l2_rule = rule.profile.l2;
+	nmm.cm.type = type;
+
+	/*
+	 * Send the message to FW to add the L2 rule into the rule table.
+	 */
+	nss_tx_status = nss_match_msg_tx_sync(nss_ctx, &nmm);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_match_warn("%px:add rule failed from NSS, rule_id = %d, nss_tx_status = %d\n",
+				nss_ctx, rule_id, nss_tx_status);
+		nss_match_db_rule_delete(table_id, rule_id);
+		return -1;
+	}
+
+	return rule_id;
+}
+EXPORT_SYMBOL(nss_match_l2_rule_add);
+
+/*
+ * nss_match_profile_configure()
+ * 	User API to configure match profile.
+ */
+nss_match_status_t nss_match_profile_configure(struct nss_ctx_instance *nss_ctx, struct nss_match_profile_configure_msg *config_msg, uint32_t table_id)
+{
+	struct nss_match_msg matchm;
+	int32_t if_num;
+	nss_tx_status_t nss_tx_status;
+	nss_match_status_t status;
+
+	status = nss_match_verify_config_msg(config_msg);
+        if (status != NSS_MATCH_SUCCESS) {
+		nss_match_warn("%px: Invalid config message.", nss_ctx);
+		return status;
+	}
+
+	if ((table_id == 0) || (table_id > NSS_MATCH_INSTANCE_MAX)) {
+		nss_match_warn("%px: Cannot configure table, table_id %d is not valid.\n", nss_ctx, table_id);
+		return NSS_MATCH_ERROR_TABLE_ID_OUTOFBOUND;
+	}
+
+	if (nss_match_db_table_validate(table_id)) {
+		nss_match_warn("Table %d is already configured.\n", table_id);
+		return NSS_MATCH_ERROR_TABLE_ID_OUTOFBOUND;
+	}
+
+	if_num = nss_match_get_ifnum_by_table_id(table_id);
+	if (if_num < 0) {
+		nss_match_warn("%px: Invalid table ID: %d, if_num %d", nss_ctx, table_id, if_num);
+		return NSS_MATCH_ERROR_TABLE_ID_OUTOFBOUND;
+	}
+
+	/*
+	 * Configuring the profile will enable sync from NSS. So add the instance into the DB first.
+	 */
+	nss_match_db_profile_type_add(config_msg->profile_type, table_id);
+	nss_match_db_mask_add(config_msg, table_id);
+	nss_match_db_instance_enable(table_id);
+
+	nss_match_msg_init(&matchm, if_num, NSS_MATCH_TABLE_CONFIGURE_MSG,
+			sizeof(struct nss_match_profile_configure_msg), NULL, NULL);
+	matchm.msg.configure_msg = *config_msg;
+
+	nss_tx_status = nss_match_msg_tx_sync(nss_ctx, &matchm);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_match_warn("%px: Profile configuration failed for table_id = %d\n, nss_tx_status = %d\n",
+				nss_ctx, if_num, nss_tx_status);
+		nss_match_db_instance_disable(table_id);
+		return NSS_MATCH_ERROR_INSTANCE_CONFIGURED;
+	}
+
+	return NSS_MATCH_SUCCESS;
+}
+EXPORT_SYMBOL(nss_match_profile_configure);
+
+/*
+ * nss_match_instance_destroy()
+ * 	User API to destroy the match instance.
+ */
+nss_match_status_t nss_match_instance_destroy(uint32_t table_id)
+{
+	nss_tx_status_t status;
+	int if_num;
+
+	if (table_id == 0 || table_id > NSS_MATCH_INSTANCE_MAX) {
+		nss_match_warn("Cannot delete the rule, table = %d, does not exist", table_id);
+		return NSS_MATCH_ERROR_TABLE_ID_OUTOFBOUND;
+	}
+
+	if_num = nss_match_get_ifnum_by_table_id(table_id);
+	if (if_num < 0) {
+		nss_match_warn("Cannot delete the rule, if_num = %d, table = %d, does not exist", if_num, table_id);
+		return NSS_MATCH_ERROR_TABLE_ID_OUTOFBOUND;
+	}
+
+	if (!nss_match_unregister_instance(if_num)) {
+		nss_match_warn("Cannot unregister the instance: %d\n", table_id);
+		return NSS_MATCH_ERROR_TABLE_ID_OUTOFBOUND;
+	}
+
+	/*
+	 * Dealloc the interface first, so that stats syncs are disabled.
+	 */
+	status = nss_dynamic_interface_dealloc_node(if_num, NSS_DYNAMIC_INTERFACE_TYPE_MATCH);
+	if (status != NSS_TX_SUCCESS) {
+		nss_match_warn("Table dealloc node failure for if_num =%d\n", if_num);
+		return NSS_MATCH_ERROR_TABLE_DELETE;
+	}
+
+	nss_match_db_table_destroy(table_id);
+	return NSS_MATCH_SUCCESS;
+}
+EXPORT_SYMBOL(nss_match_instance_destroy);
+
+/*
+ * nss_match_instance_create()
+ * 	User API to create the match instance.
+ */
+int32_t nss_match_instance_create(void)
+{
+	int32_t if_num, table_id;
+	struct nss_ctx_instance *nss_ctx;
+
+	if (nss_match_db_instance_count_get() == NSS_MATCH_INSTANCE_MAX) {
+		nss_match_warn("Match instance limit exceeded.\n");
+		return -1;
+	}
+
+	if_num = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_MATCH);
+	if (if_num < 0) {
+		nss_match_warn("Failed to allocate a node.\n");
+		return if_num;
+	}
+
+	nss_ctx = nss_match_register_instance(if_num, nss_match_sync_callback);
+	if (!nss_ctx) {
+		nss_match_warn("%px, Failed to register node : %d.\n", nss_ctx, if_num);
+		goto dealloc_node;
+	}
+
+	/*
+	 * Create the table entry in the DB.
+	 */
+	table_id = nss_match_db_table_create(if_num);
+	if (table_id < 0) {
+		nss_match_warn("%px: Memory allocation failed for match DB array\n", nss_ctx);
+		goto unregister_node;
+	}
+
+	return table_id;
+
+unregister_node:
+	nss_match_unregister_instance(if_num);
+
+dealloc_node:
+	nss_dynamic_interface_dealloc_node(if_num, NSS_DYNAMIC_INTERFACE_TYPE_MATCH);
+
+	return -1;
+
+}
+EXPORT_SYMBOL(nss_match_instance_create);
+
+static struct dentry *match_config;
+
+/*
+ * nss_match_exit_module()
+ */
+static void __exit nss_match_exit_module(void)
+{
+	int table, status;
+
+	for (table = 1; table <= NSS_MATCH_INSTANCE_MAX; table++) {
+
+		/*
+		 * Skip invalid table ID.
+		 */
+		if (nss_match_get_ifnum_by_table_id(table) < 0) {
+			continue;
+		}
+
+		status = nss_match_instance_destroy(table);
+		if (status != NSS_MATCH_SUCCESS) {
+			nss_match_warn("NSS match client destroy failed for table ID=%d with err=%d \n", table, status);
+		}
+	}
+
+	nss_match_ctl_unregister();
+	debugfs_remove_recursive(match_config);
+	nss_match_info("NSS match client destroyed\n");
+}
+
+/*
+ * nss_match_init_module()
+ */
+static int __init nss_match_init_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+	nss_match_db_init();
+
+	/*
+	 * Register VoW profile ops
+	 */
+	nss_match_vow_init();
+
+	/*
+	 * Register L2 profile ops
+	 */
+	nss_match_l2_init();
+
+	/*
+	 * Register command line interface for match
+	 */
+	if (!nss_match_ctl_register()) {
+		nss_match_warn("Can't create Match directory in procfs");
+		return -1;
+	}
+
+	match_config = debugfs_create_dir("match", NULL);
+
+	if (!match_config) {
+		nss_match_warn("Cannot create MATCH directory");
+		nss_match_ctl_unregister();
+		return -1;
+	}
+
+	/*
+	 * Register stats CLI for match
+	 */
+	if (!nss_match_stats_debugfs_create(match_config)) {
+		nss_match_warn("Cannot create MATCH node stats dentry file");
+		debugfs_remove_recursive(match_config);
+		nss_match_ctl_unregister();
+		return -1;
+	}
+
+	nss_match_info("NSS match client initialized\n");
+	return 0;
+}
+module_init(nss_match_init_module);
+module_exit(nss_match_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS match client");
diff --git a/qca-nss-clients/match/nss_match_cmd.c b/qca-nss-clients/match/nss_match_cmd.c
new file mode 100644
index 0000000..d2e08ac
--- /dev/null
+++ b/qca-nss-clients/match/nss_match_cmd.c
@@ -0,0 +1,746 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+/*
+ * nss_match_cmd.c
+ */
+
+#include <linux/sysctl.h>
+#include <linux/inetdevice.h>
+#include <linux/netdevice.h>
+#include <linux/ctype.h>
+#include "nss_match_db.h"
+#include "nss_match_cmd.h"
+#include <nss_api_if.h>
+#include "nss_match_priv.h"
+
+unsigned char nss_match_data[100] __read_mostly;
+
+/*
+ * nss_match_cmd_instance_config_tx_sync()
+ *	Sends configuration message to NSS
+ */
+static nss_tx_status_t nss_match_cmd_instance_config_tx_sync(struct nss_ctx_instance *nss_ctx,
+						uint32_t if_num, struct nss_match_profile_configure_msg *config_msg)
+{
+	struct nss_match_msg matchm;
+
+	nss_match_msg_init(&matchm, if_num,  NSS_MATCH_TABLE_CONFIGURE_MSG,
+			sizeof(struct nss_match_profile_configure_msg), NULL, NULL);
+	matchm.msg.configure_msg = *config_msg;
+
+	return nss_match_msg_tx_sync(nss_ctx, &matchm);
+}
+
+static int nss_match_cmd_enable_instance(struct nss_match_profile_configure_msg *config_msg, int if_num, uint32_t table_id) {
+
+	nss_tx_status_t nss_tx_status;
+	struct nss_ctx_instance *nss_ctx = nss_match_get_context();
+
+	nss_tx_status = nss_match_cmd_instance_config_tx_sync(nss_ctx, if_num, config_msg);
+	if (nss_tx_status == NSS_TX_SUCCESS) {
+		if (!nss_match_db_instance_enable(table_id)) {
+			nss_match_warn("Failed to enable instance for table_id=%u\n", table_id);
+			return -1;
+		}
+		return 0;
+	}
+	nss_match_warn("%px: Cannot configure/enable the new instance\n", nss_ctx);
+
+	return -1;
+}
+
+/*
+ * nss_match_cmd_parse()
+ *	Returns command type.
+ */
+static nss_match_cmd_t nss_match_cmd_parse(char *cmd)
+{
+	if (cmd == NULL)
+		return NSS_MATCH_UNKNOWN;
+	if (!(strncasecmp(cmd, "createtable", strlen("createtable"))))
+		return NSS_MATCH_CREATE_TABLE;
+	if (!(strncasecmp(cmd, "addmask", strlen("addmask"))))
+		return NSS_MATCH_ADD_MASK;
+	if (!(strncasecmp(cmd, "enable", strlen("enable"))))
+		return NSS_MATCH_ENABLE;
+	if (!(strncasecmp(cmd, "addrule", strlen("addrule"))))
+		return NSS_MATCH_ADD_RULE;
+	if (!(strncasecmp(cmd, "delrule", strlen("delrule"))))
+		return NSS_MATCH_DELETE_RULE;
+	if (!(strncasecmp(cmd, "deltable", strlen("deltable"))))
+		return NSS_MATCH_DESTROY_TABLE;
+
+	return NSS_MATCH_UNKNOWN;
+}
+
+/*
+ * nss_match_cmd_get_profile_type()
+ *	Parse message to create an instance.
+ */
+static enum nss_match_profile_type nss_match_cmd_get_profile_type(char *input_msg)
+{
+	char *token, *param;
+
+	token = strsep(&input_msg, " ");
+	if (!token) {
+		return NSS_MATCH_PROFILE_TYPE_NONE;
+	}
+
+	param = strsep(&token, "=");
+	if (!param || !token) {
+		return NSS_MATCH_PROFILE_TYPE_NONE;
+	}
+
+	if (!(strncasecmp(param, "profile_type", strlen("profile_type")))) {
+		if (!(strncasecmp(token, "vow", strlen("vow")))) {
+			return NSS_MATCH_PROFILE_TYPE_VOW;
+		}
+
+		if (!(strncasecmp(token, "l2", strlen("l2")))) {
+			return NSS_MATCH_PROFILE_TYPE_L2;
+		}
+	}
+
+	return NSS_MATCH_PROFILE_TYPE_NONE;
+}
+
+/*
+ * nss_match_cmd_procfs_config_handler()
+ * 	Handles command input by user to create and configure match instance.
+ */
+static int nss_match_cmd_procfs_config_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	char *command_str, *token, *param, *value;
+	char *input_msg, *input_msg_orig;
+	nss_match_cmd_t command;
+	struct nss_ctx_instance *nss_ctx = nss_match_get_context();
+	size_t count = *lenp;
+	int ret = proc_dostring(ctl, write, buffer, lenp, ppos);
+
+	if (!write) {
+		return ret;
+	}
+
+	input_msg = (char *)kzalloc(count + 1, GFP_KERNEL);
+	if (!input_msg) {
+		nss_match_warn("%px: Dynamic allocation falied while writing input message from file", ctl);
+		return -ENOMEM;
+	}
+
+	input_msg_orig = input_msg;
+	if (copy_from_user(input_msg, buffer, count)) {
+		kfree(input_msg);
+		nss_match_warn("%px: Cannot copy user's entry to kernel memory\n", ctl);
+		return -EFAULT;
+	}
+
+	command_str = strsep(&input_msg, " ");
+	command = nss_match_cmd_parse(command_str);
+
+	switch (command) {
+	case NSS_MATCH_CREATE_TABLE:
+	{
+		int table_id = -1, profile_type = 0;
+
+		profile_type = nss_match_cmd_get_profile_type(input_msg);
+		if (profile_type == NSS_MATCH_PROFILE_TYPE_NONE) {
+			pr_warn("%px: Please provide a valid profile type\n", ctl);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		table_id = nss_match_instance_create();
+		if (table_id <= 0) {
+			pr_warn("%px: Cannot create a new match instance\n", ctl);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		nss_match_db_profile_type_add(profile_type, table_id);
+		pr_warn("%px: New match instance created, table_id = %d\n", ctl, table_id);
+		kfree(input_msg_orig);
+		return count;
+	}
+
+	case NSS_MATCH_ADD_MASK:
+	{
+		uint32_t table_id = 0;
+		struct nss_match_msg input_mask_param = {0};
+
+		token = strsep(&input_msg, " ");
+		param = strsep(&token, "=");
+		value = token;
+		if (!value || !param) {
+			goto fail;
+		}
+
+		if (!strncasecmp(param, "table_id", strlen("table_id"))) {
+			ret = sscanf(value, "%u", &table_id);
+			if (!ret) {
+				pr_warn("%px: Cannot convert to integer. Wrong input!!", ctl);
+				kfree(input_msg_orig);
+				return -EINVAL;
+			}
+		}
+
+		if (table_id == 0 || table_id > NSS_MATCH_INSTANCE_MAX) {
+			pr_warn("%px: Invalid table_id %d", ctl, table_id);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		if (nss_match_db_table_validate(table_id)) {
+			pr_warn("%px: Table is already configured, %d", ctl, table_id);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		if (nss_match_db_parse_cmd(table_id, input_msg, &input_mask_param, NSS_MATCH_ADD_MASK)) {
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		nss_match_db_mask_add(&input_mask_param.msg.configure_msg, table_id);
+		pr_warn("%px: Mask added to instance successfully. %d", ctl, table_id);
+
+		kfree(input_msg_orig);
+		return count;
+	}
+
+	case NSS_MATCH_ENABLE:
+	{
+		uint32_t table_id = 0;
+		struct nss_match_profile_configure_msg config_msg = {0};
+		int if_num = -1;
+
+		token = strsep(&input_msg, " ");
+		param = strsep(&token, "=");
+		value = token;
+		if (!param || !value) {
+			goto fail;
+		}
+
+		if (!strncasecmp(param, "table_id", strlen("table_id"))) {
+			ret = sscanf(value, "%u", &table_id);
+			if (!ret) {
+				pr_warn("%px: Cannot convert to integer. Wrong input!!", ctl);
+				kfree(input_msg_orig);
+				return -EINVAL;
+			}
+		}
+
+		if ((table_id == 0) || (table_id > NSS_MATCH_INSTANCE_MAX)) {
+			pr_warn("%px: Invalid table_id %d", ctl, table_id);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		if (nss_match_db_table_validate(table_id)) {
+			pr_warn("%px: Table is already configured, %d", ctl, table_id);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		if (!nss_match_db_instance_config_get(&config_msg, &if_num, table_id)) {
+			pr_warn("%px: Unable to fetch stored configuration %d", ctl, table_id);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		if (if_num < 0) {
+			nss_match_warn("%px: Incorrect interface number: %d\n", ctl, if_num);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		if (nss_match_cmd_enable_instance(&config_msg, if_num, table_id)) {
+			pr_warn("%px: Failed to enable table %d\n", ctl, table_id);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		pr_warn("%px: Table %d enabled successfully\n", ctl, table_id);
+		kfree(input_msg_orig);
+		return count;
+	}
+
+	case NSS_MATCH_ADD_RULE:
+	{
+		uint32_t profile_type = 0;
+		uint32_t table_id = 0;
+		int rule_id = -1;
+		struct nss_match_msg input_rule_param = {0};
+
+		token = strsep(&input_msg, " ");
+		param = strsep(&token, "=");
+		value = token;
+		if (!param || !value) {
+			goto fail;
+		}
+
+		if (!strncasecmp(param, "table_id", strlen("table_id"))) {
+			ret = sscanf(value, "%u", &table_id);
+			if (!ret) {
+				pr_warn("%px: Cannot convert to integer. Wrong input!!", ctl);
+				kfree(input_msg_orig);
+				return -EINVAL;
+			}
+		}
+
+		if (table_id == 0 || table_id > NSS_MATCH_INSTANCE_MAX) {
+			pr_warn("%px: Invalid table_id: %d", ctl, table_id);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		nss_match_db_get_profile_type(table_id, &profile_type);
+
+		if (nss_match_db_parse_cmd(table_id, input_msg, &input_rule_param, NSS_MATCH_ADD_RULE)) {
+			pr_warn("%px: Wrong input", ctl);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		if (profile_type == NSS_MATCH_PROFILE_TYPE_VOW) {
+			rule_id = nss_match_vow_rule_add(nss_ctx, &input_rule_param.msg.vow_rule, table_id);
+		} else if (profile_type == NSS_MATCH_PROFILE_TYPE_L2) {
+			rule_id = nss_match_l2_rule_add(nss_ctx, &input_rule_param.msg.l2_rule, table_id);
+		}
+
+		if (rule_id < 0) {
+			pr_warn("%px: Failed to add rule into table %d.\n", ctl, table_id);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		pr_warn("%px: Rule added to table %d successfully with rule_id: %d\n", ctl, table_id, rule_id);
+		kfree(input_msg_orig);
+		return count;
+	}
+
+	case NSS_MATCH_DELETE_RULE:
+	{
+		uint32_t table_id = 0;
+		uint16_t rule_id = 0;
+
+		while (input_msg != NULL) {
+			token = strsep(&input_msg, " ");
+			param = strsep(&token, "=");
+			if (!param || !token) {
+				goto fail;
+			}
+
+			/*
+			 * Parsing rule_id and table_id value from the message.
+			 */
+			if (!(strncasecmp(param, "rule_id", strlen("rule_id")))) {
+				if (!sscanf(token, "%hu", &rule_id)) {
+					pr_warn("%px: Cannot convert to integer. Wrong input\n", ctl);
+					kfree(input_msg_orig);
+					return -EINVAL;
+				}
+				continue;
+			}
+
+			if (!strncasecmp(param, "table_id", strlen("table_id"))) {
+				if (!sscanf(token, "%u", &table_id)) {
+					pr_warn("%px: Cannot convert to integer. Wrong input!!", ctl);
+					kfree(input_msg_orig);
+					return -EINVAL;
+				}
+				continue;
+			}
+
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		if (table_id == 0 || table_id > NSS_MATCH_INSTANCE_MAX) {
+			pr_warn("%px: Invalid table_id: %d", ctl, table_id);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		if (rule_id == 0 || rule_id > NSS_MATCH_INSTANCE_RULE_MAX) {
+			pr_warn("%px: Invalid rule_id: %d", ctl, rule_id);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		if (nss_match_rule_delete(nss_ctx, rule_id, table_id)) {
+			pr_warn("%px: Failed to delete rule from table %d.\n", ctl, table_id);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		pr_warn("%px: Rule deleted from table %d successfully\n", ctl, table_id);
+		kfree(input_msg_orig);
+		return count;
+	}
+
+	case NSS_MATCH_DESTROY_TABLE:
+	{
+		uint32_t table_id = 0;
+		char *token, *param;
+		int ret = 0;
+
+		token = strsep(&input_msg, " ");
+		param = strsep(&token, "=");
+		if (!token || !param) {
+			goto fail;
+		}
+
+		if (!(strncasecmp(param, "table_id", strlen("table_id")))) {
+			ret = sscanf(token, "%u", &table_id);
+			if (!ret) {
+				pr_warn("%px: Cannot convert to integer. Wrong input!!", input_msg);
+				kfree(input_msg_orig);
+				return -EINVAL;
+			}
+		}
+
+		if (table_id == 0 || table_id > NSS_MATCH_INSTANCE_MAX) {
+			pr_warn("%px: Invalid table_id: %d", ctl, table_id);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		if (nss_match_instance_destroy(table_id)) {
+			pr_warn("%px: Failed to destroy table %d\n", ctl, table_id);
+			kfree(input_msg_orig);
+			return -EINVAL;
+		}
+
+		pr_warn("%px: Table %d destroyed successfully.\n", ctl, table_id);
+		kfree(input_msg_orig);
+		return count;
+	}
+
+	default:
+	{
+		pr_warn("%px: Input command is not as per syntax, Please enter a valid command", ctl);
+		kfree(input_msg_orig);
+		return -EINVAL;
+	}
+     }
+
+fail:
+	pr_warn("%px: Wrong input, check help. (cat /proc/sys/dev/nss/match/help)", ctl);
+	kfree(input_msg_orig);
+	return ret;
+
+}
+
+/*
+ * nss_match_cmd_procfs_reset_nexthop
+ * 	Reset to default nexthop of an interface
+ */
+static int nss_match_cmd_procfs_reset_nexthop(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct net_device *dev;
+	uint32_t if_num, type = 0;
+	int ret;
+	char *dev_name;
+	char *cmd_buf = nss_match_data;
+	nss_tx_status_t nss_tx_status;
+	struct nss_ctx_instance *nss_ctx = nss_match_get_context();
+	struct nss_ctx_instance *wifi_nss_ctx = nss_wifi_get_context();
+
+	if (!nss_ctx || !wifi_nss_ctx) {
+		pr_warn("%px: NSS Context not found. wifi_nss_ctx: %px. Reset nexthop failed", nss_ctx, wifi_nss_ctx);
+		return -ENOMEM;
+	}
+
+	ret = proc_dostring(ctl, write, buffer, lenp, ppos);
+	if (!write) {
+		pr_warn("%px: Reset nexthop failed.\n", nss_ctx);
+		return ret;
+	}
+
+	/*
+	 * Parse and read the devname from command.
+	 */
+	dev_name = strsep(&cmd_buf, "\0");
+	dev = dev_get_by_name(&init_net, dev_name);
+	if (!dev) {
+		pr_warn("%px: Cannot find the net device: %s. Reset nexthop failed.\n", nss_ctx, dev_name);
+		return -ENODEV;
+	}
+
+	if_num = nss_cmn_get_interface_number_by_dev(dev);
+	if (if_num < 0) {
+		pr_warn("%px: Invalid if_num for interface: %s. Reset nexthop failed.\n", nss_ctx, dev_name);
+		dev_put(dev);
+		return -ENODEV;
+	}
+
+	/*
+	 * Reset Nexthop APIs.
+	 * nss_phys_if_reset_nexthop: Used for physical interfaces.
+	 * nss_if_reset_nexthop: used for VAP interfaces.
+	 */
+	type = nss_dynamic_interface_get_type(wifi_nss_ctx, if_num);
+	if (type == NSS_DYNAMIC_INTERFACE_TYPE_VAP) {
+		nss_tx_status = nss_if_reset_nexthop(wifi_nss_ctx, if_num);
+	} else if (if_num < NSS_MAX_PHYSICAL_INTERFACES) {
+		nss_tx_status = nss_phys_if_reset_nexthop(nss_ctx, if_num);
+	} else {
+		pr_warn("%px: Invalid interface to Reset nexthop. Failed to Reset nexthop on if_num %d.\n",
+				nss_ctx, if_num);
+		dev_put(dev);
+		return -EFAULT;
+	}
+
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		pr_warn("%px: Sending message failed, cannot reset nexthop\n", nss_ctx);
+	}
+
+	dev_put(dev);
+	pr_info("%px: Reset nexthop successful.\n", nss_ctx);
+	return 0;
+}
+
+/*
+ * nss_match_cmd_procfs_set_if_nexthop
+ * 	Set next hop of an interface to a match instance.
+ * 	Only VAP and physical interfaces are supported as of now.
+ */
+static int nss_match_cmd_procfs_set_if_nexthop(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct net_device *dev;
+	uint32_t if_num, type = 0;
+	uint32_t nh_if_num;
+	int table_id;
+	struct nss_ctx_instance *nss_ctx = nss_match_get_context();
+	struct nss_ctx_instance *wifi_nss_ctx = nss_wifi_get_context();
+	char *dev_name, *nexthop_msg;
+	char *cmd_buf = NULL;
+	size_t count = *lenp;
+	nss_tx_status_t nss_tx_status;
+	int ret = proc_dostring(ctl, write, buffer, lenp, ppos);
+
+	if (!write) {
+		return ret;
+	}
+
+	if (!nss_ctx || !wifi_nss_ctx) {
+		pr_warn("%px: NSS Context not found. wifi_nss_ctx: %px. Set nexthop failed", nss_ctx, wifi_nss_ctx);
+		return -ENOMEM;
+	}
+
+	cmd_buf = (char *)kzalloc(count + 1, GFP_KERNEL);
+	nexthop_msg = cmd_buf;
+	if (!cmd_buf) {
+		pr_warn("%px: Cannot allocate buffer to read input", nss_ctx);
+		return -ENOMEM;
+	}
+
+	if (copy_from_user(cmd_buf, buffer, count)) {
+		kfree(nexthop_msg);
+		pr_warn("%px: Cannot copy user's entry to kernel memory\n", nss_ctx);
+		return -EFAULT;
+	}
+
+	dev_name = strsep(&cmd_buf, " ");
+	dev = dev_get_by_name(&init_net, dev_name);
+	if (!dev) {
+		pr_warn("%px: Cannot find the net device\n", nss_ctx);
+		kfree(nexthop_msg);
+		return -ENODEV;
+	}
+
+	if_num = nss_cmn_get_interface_number_by_dev(dev);
+	if (if_num < 0) {
+		pr_warn("%px: Invalid interface number:%d\n", nss_ctx, if_num);
+		kfree(nexthop_msg);
+		dev_put(dev);
+		return -ENODEV;
+	}
+
+	if (isdigit(cmd_buf[0])) {
+		if (!sscanf(cmd_buf, "%u", &nh_if_num)) {
+			pr_warn("%px, Failed to write the nexthop if_num token to integer\n", nss_ctx);
+			kfree(nexthop_msg);
+			dev_put(dev);
+			return -EFAULT;
+		}
+	} else {
+		pr_warn("%px: Invalid nexthop interface number.\n", nss_ctx);
+		kfree(nexthop_msg);
+		dev_put(dev);
+		return -ENODEV;
+	}
+
+	if (nh_if_num < 0) {
+		pr_warn("%px: Invalid nexthop interface number:%d\n", nss_ctx, if_num);
+		kfree(nexthop_msg);
+		dev_put(dev);
+		return -ENODEV;
+	}
+
+	table_id = nss_match_get_table_id_by_ifnum(nh_if_num);
+	if (table_id <= 0 || table_id > NSS_MATCH_INSTANCE_MAX) {
+		pr_warn("Invalid match interface. Failed to set %d as nexthop.\n", nh_if_num);
+		kfree(nexthop_msg);
+		dev_put(dev);
+		return -EFAULT;
+	}
+
+	/*
+	 * Set Nexthop APIs.
+	 * nss_phys_if_set_nexthop: Used for physical interfaces.
+	 * nss_if_set_nexthop: used for VAP interfaces.
+	 */
+	type = nss_dynamic_interface_get_type(wifi_nss_ctx, if_num);
+	if (type == NSS_DYNAMIC_INTERFACE_TYPE_VAP) {
+		nss_tx_status = nss_if_set_nexthop(wifi_nss_ctx, if_num, nh_if_num);
+	} else if (if_num < NSS_MAX_PHYSICAL_INTERFACES) {
+		nss_tx_status = nss_phys_if_set_nexthop(nss_ctx, if_num, nh_if_num);
+	} else {
+		pr_warn("Invalid interface to set nexthop. Failed to set nexthop on if_num %d.\n", if_num);
+		kfree(nexthop_msg);
+		dev_put(dev);
+		return -EFAULT;
+	}
+
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		pr_warn("%px: Sending message failed, cannot change nexthop\n", nss_ctx);
+	}
+
+	kfree(nexthop_msg);
+	dev_put(dev);
+	return ret;
+}
+
+/*
+ * nss_match_cmd_procfs_read_help()
+ * 	Display help for commands.
+ */
+static int nss_match_cmd_procfs_read_help(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+
+	pr_info("\nHelp: (/proc/sys/dev/nss/match/help) \n\
+		1. To create match isntance:\n\
+			echo createtable profile_type=<vow/l2> > config	\n\
+		2. To addmask: \n\
+		a. VoW profile \n\
+			echo addmask table_id=<1..4> mask=<1/2> ifname=<1..ffff> dscp=<1..3f> 802.1p_outer=<1..7> 802.1p_inner=<1..7> > config\n\
+		b. L2 profile \n\
+			echo addmask table_id=<1..4> mask=<1/2> ifname=<1..ffff> smac=<1..ffffffffffff>\
+			dmac=<1..ffffffffffff> ethertype=<1..ffff> > config\n\
+		3. To enable match instance \n\
+			echo enable table_id=1 > config \n\
+		5. Actions:\n\
+			a. action=1 priority=<pri_value>\n\
+			b. action=2 nexthop=<nexthop_ifnum>\n\
+			c. action=3 priority=<pri_value> nexthop=<nexthop_ifnum>\n\
+			d. action=4\n\
+		4. To set nexthop: \n\
+			echo <phy_ifname/VAP name> <match_ifnum> > set_nexthop\n\
+		5. To reset nexthop: \n\
+			echo <dev_name> > reset_nexthop\n");
+	*lenp = 0;
+	return ret;
+}
+
+static struct ctl_table nss_match_table[] = {
+	{
+		.procname		= "config",
+		.data			= &nss_match_data,
+		.maxlen			= sizeof(nss_match_data),
+		.mode			= 0644,
+		.proc_handler		= &nss_match_cmd_procfs_config_handler,
+	},
+	{
+		.procname		= "set_nexthop",
+		.data			= &nss_match_data,
+		.maxlen			= sizeof(nss_match_data),
+		.mode			= 0644,
+		.proc_handler		= &nss_match_cmd_procfs_set_if_nexthop,
+	},
+	{
+		.procname		= "reset_nexthop",
+		.data			= &nss_match_data,
+		.maxlen			= IFNAMSIZ,
+		.mode			= 0644,
+		.proc_handler		= &nss_match_cmd_procfs_reset_nexthop,
+	},
+	{
+		.procname		= "help",
+		.data                   = &nss_match_data,
+		.maxlen                 = sizeof(nss_match_data),
+		.mode			= 0400,
+		.proc_handler		= &nss_match_cmd_procfs_read_help,
+	},
+	{ }
+};
+
+static struct ctl_table nss_match_root_dir[] = {
+	{
+		.procname		= "match",
+		.mode			= 0555,
+		.child			= nss_match_table,
+	},
+	{ }
+};
+
+static struct ctl_table nss_match_nss_root_dir[] = {
+	{
+		.procname		= "nss",
+		.mode			= 0555,
+		.child			= nss_match_root_dir,
+	},
+	{ }
+};
+
+static struct ctl_table nss_match_root[] = {
+	{
+		.procname		= "dev",
+		.mode			= 0555,
+		.child			= nss_match_nss_root_dir,
+	},
+	{ }
+};
+
+static struct ctl_table_header *nss_match_ctl_header;
+
+/*
+ * nss_match_ctl_register
+ * 	Register command line interface for match.
+ */
+bool nss_match_ctl_register(void) {
+	nss_match_ctl_header = register_sysctl_table(nss_match_root);
+	if (!nss_match_ctl_header) {
+		nss_match_warn("Unable to register command line interface.\n");
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_match_ctl_unregister
+ * 	Unregister command line interface for match.
+ */
+void nss_match_ctl_unregister(void) {
+	if (nss_match_ctl_header) {
+		unregister_sysctl_table(nss_match_ctl_header);
+	}
+}
diff --git a/qca-nss-clients/match/nss_match_cmd.h b/qca-nss-clients/match/nss_match_cmd.h
new file mode 100644
index 0000000..6fd8aaf
--- /dev/null
+++ b/qca-nss-clients/match/nss_match_cmd.h
@@ -0,0 +1,42 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ********************************************************************************
+ **/
+
+#ifndef __NSS_MATCH_CMD_H
+#define __NSS_MATCH_CMD_H
+
+#include <linux/types.h>
+#include <linux/sysctl.h>
+#include <linux/debugfs.h>
+
+/*
+ * nss_match_parse_command_type
+ *	Match parse command types.
+ */
+typedef enum nss_match_parse_command_type {
+	NSS_MATCH_UNKNOWN,
+	NSS_MATCH_CREATE_TABLE,
+	NSS_MATCH_ADD_MASK,
+	NSS_MATCH_ENABLE,
+	NSS_MATCH_ADD_RULE,
+	NSS_MATCH_DELETE_RULE,
+	NSS_MATCH_DESTROY_TABLE,
+} nss_match_cmd_t;
+
+void nss_match_ctl_unregister(void);
+bool nss_match_ctl_register(void);
+#endif /* __NSS_MATCH_CMD_H */
diff --git a/qca-nss-clients/match/nss_match_db.c b/qca-nss-clients/match/nss_match_db.c
new file mode 100644
index 0000000..7aa4f04
--- /dev/null
+++ b/qca-nss-clients/match/nss_match_db.c
@@ -0,0 +1,695 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ********************************************************************************
+ **/
+#include "nss_match_db.h"
+#include "nss_match_priv.h"
+#include "nss_match_user.h"
+
+struct nss_match_db match_db; /* Match DB */
+struct match_profile_ops *profile_ops[NSS_MATCH_PROFILE_TYPE_MAX];
+
+/*
+ * nss_match_db_get_instance_by_table_id()
+ *	Get match instance.
+ */
+static struct nss_match_instance *nss_match_db_get_instance_by_table_id(uint32_t table_id)
+{
+	assert_spin_locked(&match_db.db_lock);
+
+	/*
+	 * This assumes table_id is 0 based actual array index.
+	 */
+	if ((table_id >= NSS_MATCH_INSTANCE_MAX) || (!match_db.instance[table_id])) {
+		nss_match_warn("Invalid table index: %d\n", table_id+1);
+		return NULL;
+	}
+
+	return match_db.instance[table_id];
+}
+
+int nss_match_table_count_get(void)
+{
+	int index, count = 0;
+
+	spin_lock_bh(&match_db.db_lock);
+
+	for (index = 0; index < NSS_MATCH_INSTANCE_MAX;	index++) {
+		if ((match_db.instance[index]) && (match_db.instance[index]->is_configured)) {
+			count++;
+		}
+	}
+
+	spin_unlock_bh(&match_db.db_lock);
+	return count;
+}
+
+/*
+ * nss_match_db_stats_get()
+ * 	Get stats value to print.
+ */
+bool nss_match_db_stats_get(uint32_t table_id, struct nss_match_stats *match_stats)
+{
+	struct nss_match_instance *db_instance;
+
+	spin_lock_bh(&match_db.db_lock);
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	memcpy(match_stats, &db_instance->stats, sizeof(struct nss_match_stats));
+	spin_unlock_bh(&match_db.db_lock);
+	return true;
+}
+
+/*
+ * nss_match_db_table_read()
+ * 	Read match table information, including profile information and rules data.
+ */
+size_t nss_match_db_table_read(uint32_t table_id, size_t buflen, char *bufp)
+{
+	struct nss_match_instance *db_instance;
+	size_t wr_len = 0;
+
+	spin_lock_bh(&match_db.db_lock);
+
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return wr_len;
+	}
+
+	wr_len = db_instance->ops->nss_match_table_read(db_instance, buflen, bufp);
+	spin_unlock_bh(&match_db.db_lock);
+	return wr_len;
+}
+
+/*
+ * nss_match_db_generate_rule_id()
+ * 	Generates rule id for match rule.
+ */
+int nss_match_db_generate_rule_id(uint32_t table_id)
+{
+	int rule_id;
+	struct nss_match_instance *db_instance;
+
+	spin_lock_bh(&match_db.db_lock);
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return -1;
+	}
+
+	/*
+	 * Find an unused slot in the rule table.
+	 */
+	for (rule_id = 0; rule_id < NSS_MATCH_INSTANCE_RULE_MAX; rule_id++) {
+		if (db_instance->rules[rule_id].valid_rule) {
+			continue;
+		}
+
+		spin_unlock_bh(&match_db.db_lock);
+		return (rule_id + 1);
+	}
+
+	nss_match_warn("Rule table full with NSS_MATCH_INSTANCE_RULE_MAX:%d entries.\n",
+			NSS_MATCH_INSTANCE_RULE_MAX);
+
+	spin_unlock_bh(&match_db.db_lock);
+	return -1;
+}
+
+/*
+ * nss_match_db_rule_find()
+ * 	Finds if rule exists in db.
+ */
+bool nss_match_db_rule_find(struct nss_match_rule_info *rule, uint32_t table_id)
+{
+	bool result;
+	struct nss_match_instance *db_instance;
+
+	spin_lock_bh(&match_db.db_lock);
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return true;
+	}
+
+	result = db_instance->ops->nss_match_rule_find(db_instance, rule);
+	spin_unlock_bh(&match_db.db_lock);
+	return result;
+}
+
+/*
+ * nss_match_db_rule_add()
+ * 	Adds the match rule in match db.
+ */
+bool nss_match_db_rule_add(struct nss_match_rule_info *rule, uint8_t table_id)
+{
+	struct nss_match_instance *db_instance;
+
+	spin_lock_bh(&match_db.db_lock);
+
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	if (!db_instance->ops->nss_match_rule_add(db_instance, rule)) {
+		nss_match_warn("Unable to add rule to match database.\n");
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	spin_unlock_bh(&match_db.db_lock);
+	return true;
+}
+
+/*
+ * nss_match_db_rule_delete()
+ * 	Deletes the match rule from match db.
+ */
+bool nss_match_db_rule_delete(uint32_t table_id, uint32_t rule_id)
+{
+	struct nss_match_instance *db_instance;
+	int index;
+
+	if (rule_id == 0 || rule_id > NSS_MATCH_INSTANCE_RULE_MAX) {
+		nss_match_warn("Invalid rule ID: %d\n", rule_id);
+		return false;
+	}
+
+	spin_lock_bh(&match_db.db_lock);
+
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	if (!(db_instance->rules[rule_id - 1].valid_rule)) {
+		nss_match_warn("Rule dosn't exist for rule id: %d\n", rule_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	db_instance->rule_count--;
+	db_instance->stats.hit_count[rule_id - 1] = 0;
+
+	for (index = 0; index < NSS_MATCH_MASK_MAX; index++) {
+		db_instance->valid_rule_mask[index][rule_id - 1] = false;
+	}
+	memset(&(db_instance->rules[rule_id - 1]), 0, sizeof(struct nss_match_rule_info));
+
+	spin_unlock_bh(&match_db.db_lock);
+	return true;
+}
+
+/*
+ * nss_match_db_rule_read()
+ * 	Gets the match rule from match db.
+ */
+bool nss_match_db_rule_read(struct nss_match_rule_info *rule, uint32_t table_id, uint16_t rule_id)
+{
+	bool res;
+	struct nss_match_instance *db_instance;
+
+	spin_lock_bh(&match_db.db_lock);
+
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	res = db_instance->ops->nss_match_rule_read(db_instance, rule, rule_id);
+	spin_unlock_bh(&match_db.db_lock);
+	return res;
+}
+
+/*
+ * nss_match_db_parse_cmd()
+ * 	Parses match commands and fills 'rule_msg' accordingly with the information.
+ */
+int nss_match_db_parse_cmd(uint32_t table_id, char *input_msg, struct nss_match_msg *rule_msg, nss_match_cmd_t type)
+{
+	int res;
+	struct nss_match_instance *db_instance;
+
+	spin_lock_bh(&match_db.db_lock);
+
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return -1;
+	}
+
+	spin_unlock_bh(&match_db.db_lock);
+
+	res = db_instance->ops->nss_match_cmd_parse(input_msg, rule_msg, type);
+	return res;
+}
+
+/*
+ * nss_match_db_table_validate()
+ * 	Check if table is configured.
+ */
+bool nss_match_db_table_validate(int table_id)
+{
+	struct nss_match_instance *db_instance;
+
+	spin_lock_bh(&match_db.db_lock);
+
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	if (!db_instance->is_configured) {
+		nss_match_warn("Table is not configured, table_id %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	spin_unlock_bh(&match_db.db_lock);
+	return true;
+}
+
+/*
+ * nss_match_db_get_profile_type()
+ *	Returns the table index and updates profile type.
+ */
+bool nss_match_db_get_profile_type(uint32_t table_id, uint32_t *profile_type)
+{
+	struct nss_match_instance *db_instance;
+
+	spin_lock_bh(&match_db.db_lock);
+
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	*profile_type = db_instance->profile_type;
+
+	spin_unlock_bh(&match_db.db_lock);
+	return true;
+}
+
+/*
+ * nss_match_db_get_ifnum_by_table_id()
+ *	Returns interface number using table ID.
+ */
+int nss_match_db_get_ifnum_by_table_id(uint32_t table_id)
+{
+	int if_num;
+	struct nss_match_instance *db_instance;
+
+	spin_lock_bh(&match_db.db_lock);
+
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return -1;
+	}
+
+	if_num = db_instance->if_num;
+	spin_unlock_bh(&match_db.db_lock);
+	return if_num;
+}
+
+/*
+ * nss_match_get_table_id_by_ifnum()
+ * 	Returns table index using interface number.
+ *
+ */
+int nss_match_get_table_id_by_ifnum(int if_num)
+{
+	int index;
+
+	spin_lock_bh(&match_db.db_lock);
+
+	for (index = 0; index < NSS_MATCH_INSTANCE_MAX; index++) {
+		if (!match_db.instance[index] || match_db.instance[index]->if_num != if_num) {
+			continue;
+		}
+
+		spin_unlock_bh(&match_db.db_lock);
+		return index + 1;
+	}
+
+	spin_unlock_bh(&match_db.db_lock);
+	return -1;
+}
+
+/*
+ * nss_match_db_table_destroy()
+ *	Destroys table information from DB.
+ */
+bool nss_match_db_table_destroy(int table_id)
+{
+	/*
+	 * TODO: Add clear table API.
+	 */
+	struct nss_match_instance *table_info;
+
+	if (table_id <= 0 || table_id > NSS_MATCH_INSTANCE_MAX) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		return false;
+	}
+
+	spin_lock_bh(&match_db.db_lock);
+
+	table_info = match_db.instance[table_id - 1];
+	if (!table_info) {
+		nss_match_warn("Invalid table index: %d, table doesn't exist.\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	match_db.instance_count--;
+	match_db.instance[table_id - 1] = NULL;
+
+	spin_unlock_bh(&match_db.db_lock);
+	kfree(table_info);
+	return true;
+}
+
+/*
+ * nss_match_db_table_create()
+ * 	Create an instance in the DB for the new table.
+ */
+int nss_match_db_table_create(int if_num)
+{
+	int index, table_id = -1;
+	struct nss_match_instance *mi;
+
+	mi = (struct nss_match_instance *) kzalloc(sizeof(struct nss_match_instance), GFP_KERNEL);
+	if (!mi) {
+		nss_match_warn("Unable to allocate memory for new table.\n");
+		return -1;
+	}
+
+	spin_lock_bh(&match_db.db_lock);
+	for (index = 0; index < NSS_MATCH_INSTANCE_MAX; index++) {
+		if (match_db.instance[index]) {
+			continue;
+		}
+
+		match_db.instance[index] = mi;
+		match_db.instance_count++;
+		match_db.instance[index]->profile_type = 0;
+		match_db.instance[index]->maskset[0][0] = 0;
+		match_db.instance[index]->maskset[1][0] = 0;
+		match_db.instance[index]->if_num = if_num;
+		match_db.instance[index]->is_configured = false;
+		match_db.instance[index]->valid_mask_flag = 0;
+		table_id = index + 1;
+		break;
+	}
+
+	spin_unlock_bh(&match_db.db_lock);
+	return table_id;
+}
+
+/*
+ * nss_match_db_profile_type_add()
+ * 	Add profile type to match instance.
+ */
+bool nss_match_db_profile_type_add(uint32_t profile_type, uint8_t table_id)
+{
+	struct nss_match_instance *db_instance;
+
+	spin_lock_bh(&match_db.db_lock);
+
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	db_instance->profile_type = profile_type;
+	db_instance->ops = profile_ops[profile_type];
+	nss_match_info("Added ops %px for profile type: %d", db_instance->ops, profile_type);
+	spin_unlock_bh(&match_db.db_lock);
+	return true;
+}
+
+/*
+ * nss_match_db_mask_add()
+ * 	Add a mask to the profile.
+ */
+bool nss_match_db_mask_add(struct nss_match_profile_configure_msg *config_msg, uint8_t table_id)
+{
+	int valid, index;
+	struct nss_match_instance *db_instance;
+
+	spin_lock_bh(&match_db.db_lock);
+
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	for (valid = 0; valid < NSS_MATCH_MASK_MAX; valid++) {
+		if (config_msg->valid_mask_flag & (1 << valid)) {
+			for (index = 0; index < NSS_MATCH_MASK_WORDS_MAX; index++) {
+				db_instance->maskset[valid][index] = config_msg->maskset[valid][index];
+			}
+		}
+	}
+	db_instance->valid_mask_flag |= config_msg->valid_mask_flag;
+	spin_unlock_bh(&match_db.db_lock);
+	return true;
+}
+
+/*
+ * nss_match_db_instance_config_get()
+ * 	Get the profile config given the table ID.
+ */
+bool nss_match_db_instance_config_get(struct nss_match_profile_configure_msg *config_msg, int *if_num, uint8_t table_id)
+{
+	int valid, index;
+	struct nss_match_instance *db_instance;
+
+	spin_lock_bh(&match_db.db_lock);
+
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	config_msg->profile_type = db_instance->profile_type;
+	if (!(db_instance->valid_mask_flag)) {
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	config_msg->valid_mask_flag = db_instance->valid_mask_flag;
+
+	for (valid = 0; valid < NSS_MATCH_MASK_MAX; valid++) {
+		if (db_instance->valid_mask_flag & (1 << valid)) {
+			for (index = 0; index < NSS_MATCH_MASK_WORDS_MAX; index++) {
+				config_msg->maskset[valid][index] = db_instance->maskset[valid][index];
+			}
+		}
+	}
+
+	*if_num = db_instance->if_num;
+
+	spin_unlock_bh(&match_db.db_lock);
+
+	return true;
+}
+
+/*
+ * nss_match_db_instance_count_get()
+ * 	Get total number of existing match instance.
+ */
+int nss_match_db_instance_count_get(void)
+{
+	int count;
+
+	spin_lock_bh(&match_db.db_lock);
+	count = match_db.instance_count;
+	spin_unlock_bh(&match_db.db_lock);
+
+	return count;
+}
+
+/*
+ * nss_match_db_rule_count_get()
+ * 	Get total number of rule pr instance.
+ */
+int nss_match_db_rule_count_get(uint32_t table_id)
+{
+	int count;
+	struct nss_match_instance *db_instance;
+
+	spin_lock_bh(&match_db.db_lock);
+
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return -1;
+	}
+
+	count = db_instance->rule_count;
+	spin_unlock_bh(&match_db.db_lock);
+	return count;
+}
+
+/*
+ * nss_match_stats_table_sync()
+ *	Debug stats sync for match.
+ */
+void nss_match_stats_table_sync(struct nss_ctx_instance *nss_ctx, struct nss_match_stats_sync *stats_msg, uint16_t if_num)
+{
+	int index, table_id;
+	struct nss_match_instance *db_instance;
+
+	table_id = nss_match_get_table_id_by_ifnum(if_num);
+	if (table_id <= 0 || table_id > NSS_MATCH_INSTANCE_MAX) {
+		nss_match_warn("Invalid table id: %d\n", table_id);
+		return;
+	}
+
+	spin_lock_bh(&match_db.db_lock);
+
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid if_num: %d, table index: %d, failed to get DB instance. \n", if_num, table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return;
+	}
+
+	db_instance->stats.pstats.rx_packets += stats_msg->p_stats.rx_packets;
+	db_instance->stats.pstats.rx_bytes += stats_msg->p_stats.rx_bytes;
+	db_instance->stats.pstats.tx_packets += stats_msg->p_stats.tx_packets;
+	db_instance->stats.pstats.tx_bytes += stats_msg->p_stats.tx_bytes;
+
+	for (index = 0; index < NSS_MAX_NUM_PRI; index++) {
+		db_instance->stats.pstats.rx_dropped[index] += stats_msg->p_stats.rx_dropped[index];
+	}
+
+	for (index = 0; index < NSS_MATCH_INSTANCE_RULE_MAX; index++) {
+		/*
+		 * Avoid sync for invalid rules.
+		 */
+		if (!db_instance->rules[index].valid_rule) {
+			continue;
+		}
+		db_instance->stats.hit_count[index] += stats_msg->hit_count[index];
+	}
+
+	spin_unlock_bh(&match_db.db_lock);
+}
+
+/*
+ * nss_match_db_instance_disable
+ * 	Disable the match instance.
+ */
+bool nss_match_db_instance_disable(uint32_t table_id)
+{
+	struct nss_match_instance *db_instance;
+
+	spin_lock_bh(&match_db.db_lock);
+
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	db_instance->is_configured = false;
+	spin_unlock_bh(&match_db.db_lock);
+
+	return true;
+}
+
+/*
+ * nss_match_db_instance_enable()
+ * 	Enable the match instance.
+ */
+bool nss_match_db_instance_enable(uint32_t table_id)
+{
+	struct nss_match_instance *db_instance;
+
+	spin_lock_bh(&match_db.db_lock);
+
+	db_instance = nss_match_db_get_instance_by_table_id(table_id - 1);
+	if (!db_instance) {
+		nss_match_warn("Invalid table index, failed to get DB instance: %d\n", table_id);
+		spin_unlock_bh(&match_db.db_lock);
+		return false;
+	}
+
+	db_instance->is_configured = true;
+	spin_unlock_bh(&match_db.db_lock);
+
+	return true;
+}
+
+/*
+ * nss_match_profile_ops_register()
+ * 	Registers match ops according to profile type.
+ */
+bool nss_match_profile_ops_register(uint32_t type, struct match_profile_ops *mops)
+{
+	if (type >= NSS_MATCH_PROFILE_TYPE_MAX) {
+		nss_match_warn("Invalid profile type: %d", type);
+		return false;
+	}
+
+	profile_ops[type] = mops;
+	nss_match_info("Match ops added for profile type: %d", type);
+
+	return true;
+}
+
+/*
+ * nss_match_db_init()
+ * 	Initializes DB.
+ */
+void nss_match_db_init(void)
+{
+	match_db.instance_count = 0;
+	spin_lock_init(&match_db.db_lock);
+	nss_match_info("db init successful.\n");
+}
diff --git a/qca-nss-clients/match/nss_match_db.h b/qca-nss-clients/match/nss_match_db.h
new file mode 100644
index 0000000..0429d39
--- /dev/null
+++ b/qca-nss-clients/match/nss_match_db.h
@@ -0,0 +1,112 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ********************************************************************************
+ **/
+
+#ifndef __NSS_MATCH_DB_H
+#define __NSS_MATCH_DB_H
+
+#include "nss_match_stats.h"
+#include "nss_match_cmd.h"
+
+/*
+ * nss_match_rule_info
+ *	Rule information.
+ */
+struct nss_match_rule_info {
+	union {
+		struct nss_match_rule_vow_msg vow;
+		struct nss_match_rule_l2_msg l2;
+	} profile;
+	bool valid_rule;
+};
+
+/*
+ * nss_match_instance
+ *	Match instance information.
+ */
+struct nss_match_instance {
+	struct nss_match_rule_info rules[NSS_MATCH_INSTANCE_RULE_MAX];
+	struct nss_match_stats stats;
+	struct match_profile_ops *ops;
+	uint32_t valid_mask_flag;
+	uint32_t maskset[NSS_MATCH_MASK_MAX][NSS_MATCH_MASK_WORDS_MAX];	/* Maskset. */
+	bool valid_rule_mask[NSS_MATCH_MASK_MAX][NSS_MATCH_INSTANCE_RULE_MAX];
+	uint32_t profile_type;
+	uint32_t if_num;
+	uint16_t rule_count;
+	bool is_configured;
+};
+
+/*
+ * nss_match_db
+ * 	Structure to store all match instance information.
+ */
+struct nss_match_db {
+	struct nss_match_instance *instance[NSS_MATCH_INSTANCE_MAX];		/* Pointer to each match instance database. */
+	spinlock_t db_lock;		/* Spin lock to protect database. */
+	int8_t instance_count;		/* Match instance count. */
+};
+
+/*
+ * match_profile_ops
+ * 	Operations to perform on match db.
+ */
+struct match_profile_ops {
+
+	/* Check if rule exists already in database. */
+	bool (*nss_match_rule_find)(struct nss_match_instance *db_instance, struct nss_match_rule_info *rule);
+
+	/* Add match rule into database. */
+	bool (*nss_match_rule_add)(struct nss_match_instance *db_instance, struct nss_match_rule_info *rule);
+
+	/* Get match rules details from database. */
+	bool (*nss_match_rule_read)(struct nss_match_instance *db_instance, struct nss_match_rule_info *rule, uint16_t rule_id);
+
+	/* Read table details. */
+	size_t (*nss_match_table_read)(struct nss_match_instance *db_instance, size_t buflen, char *bufp);
+
+	/* Parse command line arguements. */
+	int (*nss_match_cmd_parse)(char *input_msg, struct nss_match_msg *rule_msg, nss_match_cmd_t type);
+};
+
+int nss_match_table_count_get(void);
+int nss_match_db_rule_count_get(uint32_t table_id);
+int nss_match_get_table_id_by_ifnum(int if_num);
+bool nss_match_db_table_validate(int table_id);
+bool nss_match_db_get_profile_type(uint32_t table_id, uint32_t *profile_type);
+bool nss_match_db_table_destroy(int table_id);
+int nss_match_db_table_create(int if_num);
+bool nss_match_db_mask_add(struct nss_match_profile_configure_msg *config_msg, uint8_t table_id);
+bool nss_match_db_instance_config_get(struct nss_match_profile_configure_msg *config_msg, int *if_num, uint8_t table_id);
+bool nss_match_db_instance_enable(uint32_t table_id);
+bool nss_match_db_instance_disable(uint32_t table_id);
+int nss_match_db_instance_count_get(void);
+bool nss_match_db_profile_type_add(uint32_t profile_type, uint8_t table_id);
+int nss_match_db_generate_rule_id(uint32_t table_id);
+bool nss_match_db_rule_find(struct nss_match_rule_info *rule, uint32_t table_id);
+bool nss_match_db_rule_add(struct nss_match_rule_info *rule, uint8_t table_id);
+bool nss_match_db_rule_delete(uint32_t table_id, uint32_t rule_id);
+bool nss_match_db_rule_read(struct nss_match_rule_info *rule, uint32_t table_id, uint16_t rule_id);
+int nss_match_db_parse_cmd(uint32_t table_id, char *input_msg, struct nss_match_msg *rule_msg, nss_match_cmd_t type);
+void nss_match_stats_table_sync(struct nss_ctx_instance *nss_ctx, struct nss_match_stats_sync *stats_msg, uint16_t if_num);
+size_t nss_match_db_table_read(uint32_t table_id, size_t buflen, char *bufp);
+bool nss_match_db_stats_get(uint32_t table_id, struct nss_match_stats *match_stats);
+void nss_match_db_init(void);
+bool nss_match_profile_ops_register(uint32_t type, struct match_profile_ops *mops);
+int nss_match_db_get_ifnum_by_table_id(uint32_t table_id);
+
+#endif /* __NSS_MATCH_DB_H */
diff --git a/qca-nss-clients/match/nss_match_l2.c b/qca-nss-clients/match/nss_match_l2.c
new file mode 100644
index 0000000..a415fbc
--- /dev/null
+++ b/qca-nss-clients/match/nss_match_l2.c
@@ -0,0 +1,495 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ********************************************************************************
+ **/
+#include "nss_match_db.h"
+#include "nss_match_priv.h"
+
+#define MATCH_L2_KEY0_IFNUM_SHIFT 0
+#define MATCH_L2_KEY0_DMAC_HW0_SHIFT 16
+#define MATCH_L2_KEY1_DMAC_HW1_SHIFT 0
+#define MATCH_L2_KEY1_DMAC_HW2_SHIFT 16
+#define MATCH_L2_KEY2_SMAC_HW0_SHIFT 0
+#define MATCH_L2_KEY2_SMAC_HW1_SHIFT 16
+#define MATCH_L2_KEY3_SMAC_HW2_SHIFT 0
+#define MATCH_L2_KEY3_ETHERTYPE_SHIFT 16
+
+/*
+ * nss_match_l2_rule_find()
+ *	Check if any slot is available for new entry.
+ */
+static bool nss_match_l2_rule_find(struct nss_match_instance *db_instance, struct nss_match_rule_info *rule)
+{
+	uint16_t index;
+
+	/*
+	 * Check if entry is duplicate.
+	 */
+	for (index = 0; index < NSS_MATCH_INSTANCE_RULE_MAX; index++) {
+		struct nss_match_rule_info rule_info = db_instance->rules[index];
+
+		if (rule_info.valid_rule &&
+			rule_info.profile.l2.if_num == rule->profile.l2.if_num &&
+			rule_info.profile.l2.ethertype == rule->profile.l2.ethertype &&
+			rule_info.profile.l2.smac[0] == htons(rule->profile.l2.smac[0]) &&
+			rule_info.profile.l2.smac[1] == htons(rule->profile.l2.smac[1]) &&
+			rule_info.profile.l2.smac[2] == htons(rule->profile.l2.smac[2]) &&
+			rule_info.profile.l2.dmac[0] == htons(rule->profile.l2.dmac[0]) &&
+			rule_info.profile.l2.dmac[1] == htons(rule->profile.l2.dmac[1]) &&
+			rule_info.profile.l2.dmac[2] == htons(rule->profile.l2.dmac[2]) &&
+			rule_info.profile.l2.mask_id == rule->profile.l2.mask_id) {
+			nss_match_info("Rule matched\n");
+			return true;
+		}
+	}
+
+	return false;
+}
+
+/*
+ * nss_match_l2_db_rule_add()
+ * 	Store L2 rule information.
+ */
+static bool nss_match_l2_db_rule_add(struct nss_match_instance *db_instance, struct nss_match_rule_info *rule)
+{
+	uint8_t rule_id = rule->profile.l2.rule_id;
+	uint8_t mask_id = rule->profile.l2.mask_id;
+
+	if (rule_id == 0 || rule_id > NSS_MATCH_INSTANCE_RULE_MAX) {
+		nss_match_warn("Invalid rule id: %d\n", rule_id);
+		return false;
+	}
+
+	if (db_instance->rules[rule_id - 1].valid_rule) {
+		nss_match_warn("Rule exists for rule id: %d\n", rule_id);
+		return false;
+	}
+
+	db_instance->rules[rule_id - 1].profile.l2.if_num =  rule->profile.l2.if_num;
+	db_instance->rules[rule_id - 1].profile.l2.smac[0] = ntohs(rule->profile.l2.smac[0]);
+	db_instance->rules[rule_id - 1].profile.l2.smac[1] = ntohs(rule->profile.l2.smac[1]);
+	db_instance->rules[rule_id - 1].profile.l2.smac[2] = ntohs(rule->profile.l2.smac[2]);
+	db_instance->rules[rule_id - 1].profile.l2.dmac[0] = ntohs(rule->profile.l2.dmac[0]);
+	db_instance->rules[rule_id - 1].profile.l2.dmac[1] = ntohs(rule->profile.l2.dmac[1]);
+	db_instance->rules[rule_id - 1].profile.l2.dmac[2] = ntohs(rule->profile.l2.dmac[2]);
+	db_instance->rules[rule_id - 1].profile.l2.ethertype = rule->profile.l2.ethertype;
+	db_instance->rules[rule_id - 1].profile.l2.mask_id = mask_id;
+	db_instance->rules[rule_id - 1].profile.l2.action.action_flag = rule->profile.l2.action.action_flag;
+	db_instance->rules[rule_id - 1].profile.l2.action.setprio = rule->profile.l2.action.setprio;
+	db_instance->rules[rule_id - 1].profile.l2.action.forward_ifnum = rule->profile.l2.action.forward_ifnum;
+	db_instance->rules[rule_id - 1].valid_rule = true;
+	db_instance->rules[rule_id - 1].profile.l2.rule_id = rule_id;
+	db_instance->valid_rule_mask[mask_id - 1][rule_id - 1] = true;
+	db_instance->rule_count++;
+
+	return true;
+}
+
+/*
+ * nss_match_l2_rule_read()
+ *	Reads rule parameters by rule id.
+ */
+static bool nss_match_l2_rule_read(struct nss_match_instance *db_instance, struct nss_match_rule_info *rule, uint16_t rule_id)
+{
+	if (!db_instance->rules[rule_id - 1].valid_rule) {
+		nss_match_warn("rule_id does not exist, rule_id = %d", rule_id);
+		return false;
+	}
+
+	rule->profile.l2.if_num = db_instance->rules[rule_id - 1].profile.l2.if_num;
+	rule->profile.l2.smac[0] = htons(db_instance->rules[rule_id - 1].profile.l2.smac[0]);
+	rule->profile.l2.smac[1] = htons(db_instance->rules[rule_id - 1].profile.l2.smac[1]);
+	rule->profile.l2.smac[2] = htons(db_instance->rules[rule_id - 1].profile.l2.smac[2]);
+	rule->profile.l2.dmac[0] = htons(db_instance->rules[rule_id - 1].profile.l2.dmac[0]);
+	rule->profile.l2.dmac[1] = htons(db_instance->rules[rule_id - 1].profile.l2.dmac[1]);
+	rule->profile.l2.dmac[2] = htons(db_instance->rules[rule_id - 1].profile.l2.dmac[2]);
+	rule->profile.l2.ethertype = db_instance->rules[rule_id - 1].profile.l2.ethertype;
+	rule->profile.l2.mask_id = db_instance->rules[rule_id - 1].profile.l2.mask_id;
+	rule->profile.l2.rule_id = db_instance->rules[rule_id - 1].profile.l2.rule_id;
+
+	return true;
+}
+
+/*
+ * nss_match_l2_cmd_parse()
+ *	Parse the L2 command
+ */
+static int nss_match_l2_cmd_parse(char *input_msg, struct nss_match_msg *rule_msg, nss_match_cmd_t type)
+{
+	char *token, *param;
+	struct nss_ctx_instance *nss_ctx = nss_match_get_context();
+	int ret = 0;
+	uint32_t mask_val[4] = {0};
+	uint32_t actions = 0, if_num = 0, setprio = 0, nexthop = 0;
+	uint16_t smac[3] = {0}, dmac[3] = {0}, mask_id = 0, ethertype = 0;
+	uint8_t mac_addr_tmp[6];
+	char tmp[4];
+
+	/*
+	 * Parse User input.
+	 */
+	while (input_msg != NULL) {
+		token = strsep(&input_msg, " ");
+		param = strsep(&token, "=");
+		if (!param || !token) {
+			goto fail;
+		}
+
+		/*
+		 * Parse mask ID of the message.
+		 */
+		if (!(strncasecmp(param, "mask", strlen("mask")))) {
+			if (!sscanf(token, "%hu", &mask_id)) {
+				pr_info("%px: Cannot convert to integer. Wrong input\n", nss_ctx);
+				return -EINVAL;
+			}
+
+			if (mask_id > NSS_MATCH_MASK_MAX) {
+				pr_info("%px: Maskset num %d, exceeds max allowed value %d\n", nss_ctx, mask_id, NSS_MATCH_MASK_MAX);
+				return -EINVAL;
+			}
+
+			continue;
+		}
+
+		/*
+		 * Parse interface name of the message.
+		 */
+		if (!(strncasecmp(param, "ifname", strlen("ifname")))) {
+			struct net_device *dev;
+			if (type == NSS_MATCH_ADD_MASK) {
+				if (!sscanf(token, "%x", &if_num)) {
+					pr_info("%px: Cannot convert to integer. Wrong input\n", nss_ctx);
+					return -EINVAL;
+				}
+
+				continue;
+			}
+
+			if (type == NSS_MATCH_ADD_RULE) {
+				dev = dev_get_by_name(&init_net, token);
+				if (!dev) {
+					pr_info("%px: Cannot find the net device\n", nss_ctx);
+					return -ENODEV;
+				}
+
+				if_num = nss_cmn_get_interface_number_by_dev(dev);
+				dev_put(dev);
+				continue;
+			}
+		}
+
+		/*
+		 * Parse soure mac address of the message.
+		 */
+		if (!(strncasecmp(param, "smac", strlen("smac")))) {
+
+			/*
+			 * Parse the 48bit mask input in hex. For ex, smac=FFFF0000FFFF
+			 */
+			if (type == NSS_MATCH_ADD_MASK) {
+				tmp[0] = token[0];
+				tmp[1] = token[1];
+				tmp[2] = token[2];
+				tmp[3] = token[3];
+				sscanf(tmp, "%hx", &smac[0]);
+
+				tmp[0] = token[4];
+				tmp[1] = token[5];
+				tmp[2] = token[6];
+				tmp[3] = token[7];
+				sscanf(tmp, "%hx", &smac[1]);
+
+				tmp[0] = token[8];
+				tmp[1] = token[9];
+				tmp[2] = token[10];
+				tmp[3] = token[11];
+				sscanf(tmp, "%hx", &smac[2]);
+			}
+
+			/*
+			 * Parse the 6 byte MAC address delimited by ':'. For ex, smac=01:00:25:ff:45:a1
+			 */
+			if (type == NSS_MATCH_ADD_RULE) {
+				sscanf(token, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+		&mac_addr_tmp[0], &mac_addr_tmp[1], &mac_addr_tmp[2], &mac_addr_tmp[3], &mac_addr_tmp[4], &mac_addr_tmp[5]);
+
+				memcpy((uint8_t *)smac, mac_addr_tmp, 6);
+			}
+
+			nss_match_info("%px: src mac %x %x %x ", nss_ctx, smac[0], smac[1], smac[2]);
+			continue;
+		}
+
+		/*
+		 * Parse the destination mac address of the message.
+		 */
+		if (!(strncasecmp(param, "dmac", strlen("dmac")))) {
+
+			/*
+			 * Parse the 48bit mask input in hex. For ex, dmac=FFFF0000FFFF
+			 */
+			if (type == NSS_MATCH_ADD_MASK) {
+
+				tmp[0] = token[0];
+				tmp[1] = token[1];
+				tmp[2] = token[2];
+				tmp[3] = token[3];
+				sscanf(tmp, "%hx", &dmac[0]);
+
+				tmp[0] = token[4];
+				tmp[1] = token[5];
+				tmp[2] = token[6];
+				tmp[3] = token[7];
+				sscanf(tmp, "%hx", &dmac[1]);
+
+				tmp[0] = token[8];
+				tmp[1] = token[9];
+				tmp[2] = token[10];
+				tmp[3] = token[11];
+				sscanf(tmp, "%hx", &dmac[2]);
+			}
+
+			/*
+			 * Parse the 6 byte MAC address delimited by ':'. For ex, dmac=01:00:5e:ff:45:a1
+			 */
+			if (type == NSS_MATCH_ADD_RULE) {
+				sscanf(token, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+		&mac_addr_tmp[0], &mac_addr_tmp[1], &mac_addr_tmp[2], &mac_addr_tmp[3], &mac_addr_tmp[4], &mac_addr_tmp[5]);
+				memcpy((uint8_t *)dmac, mac_addr_tmp, 6);
+			}
+
+			nss_match_info("%px: dest mac %x %x %x ", nss_ctx, dmac[0], dmac[1], dmac[2]);
+			continue;
+		}
+
+		/*
+		 * Parse ethertype of the message.
+		 */
+		if (!(strncasecmp(param, "ethertype", strlen("ethertype")))) {
+			ret = sscanf(token, "%hx", &ethertype);
+			if (!ret) {
+				pr_info("%px: Cannot convert to integer. Wrong input\n", nss_ctx);
+				return -EINVAL;
+			}
+
+			continue;
+		}
+
+		/*
+		 * Parsing action from the message provided by user.
+		 */
+		if (!(strncasecmp(param, "action", strlen("action")))) {
+			if (!sscanf(token, "%u", &actions)) {
+				pr_info("%px: Cannot convert to integer. Wrong input\n", nss_ctx);
+				return -EINVAL;
+			}
+
+			continue;
+		}
+
+		/*
+		 * Parsing priority for action provided by user.
+		 */
+		if (!(strncasecmp(param, "priority", strlen("priority")))) {
+			if (!sscanf(token, "%u", &setprio)) {
+				pr_info("%px: Cannot convert to integer. Wrong input\n", nss_ctx);
+				return -EINVAL;
+			}
+
+			continue;
+		}
+
+		/*
+		 * Parsing nexthop for action provided by user.
+		 */
+		if (!(strncasecmp(param, "nexthop", strlen("nexthop")))) {
+			if (!sscanf(token, "%u", &nexthop)) {
+				pr_info("%px: Cannot convert to integer. Wrong input\n", nss_ctx);
+				return -EINVAL;
+			}
+
+			continue;
+		}
+
+		pr_info("%px: Not a valid input\n", nss_ctx);
+		goto fail;
+	}
+
+	/*
+	 * Verify correctness of field combination.
+	 */
+	switch (type) {
+	case NSS_MATCH_ADD_RULE:
+		if (!mask_id || !actions) {
+			goto fail;
+		}
+
+		switch(actions) {
+		case NSS_MATCH_ACTION_SETPRIO:
+			if (nexthop || !setprio || setprio >= NSS_MAX_NUM_PRI) {
+				goto fail;
+			}
+			break;
+		case NSS_MATCH_ACTION_FORWARD:
+			if (setprio || !nexthop) {
+				goto fail;
+			}
+			break;
+		case NSS_MATCH_ACTION_SETPRIO | NSS_MATCH_ACTION_FORWARD:
+			if (!setprio || !nexthop || setprio >= NSS_MAX_NUM_PRI) {
+				goto fail;
+			}
+			break;
+		case NSS_MATCH_ACTION_DROP:
+			if (setprio || nexthop) {
+				goto fail;
+			}
+			break;
+		default:
+			goto fail;
+		}
+
+		rule_msg->msg.l2_rule.if_num = if_num;
+
+		/*
+		 * Smac, dmac are in host order, these should be converted to network order, before sending to FW.
+		 */
+		rule_msg->msg.l2_rule.smac[0] = htons(smac[0]);
+		rule_msg->msg.l2_rule.smac[1] = htons(smac[1]);
+		rule_msg->msg.l2_rule.smac[2] = htons(smac[2]);
+		rule_msg->msg.l2_rule.dmac[0] = htons(dmac[0]);
+		rule_msg->msg.l2_rule.dmac[1] = htons(dmac[1]);
+		rule_msg->msg.l2_rule.dmac[2] = htons(dmac[2]);
+		rule_msg->msg.l2_rule.ethertype = ethertype;
+		rule_msg->msg.l2_rule.mask_id = mask_id;
+		rule_msg->msg.l2_rule.action.setprio = setprio;
+		rule_msg->msg.l2_rule.action.action_flag = actions;
+		rule_msg->msg.l2_rule.action.forward_ifnum = nexthop;
+		break;
+	case NSS_MATCH_ADD_MASK:
+		if (!mask_id) {
+			pr_info("Missing mandatory field, Mask ID.\n");
+			goto fail;
+		}
+
+		mask_val[0] = (if_num << MATCH_L2_KEY0_IFNUM_SHIFT);
+		mask_val[0] |= (dmac[0] << MATCH_L2_KEY0_DMAC_HW0_SHIFT);
+		mask_val[1] = (dmac[1] << MATCH_L2_KEY1_DMAC_HW1_SHIFT);
+		mask_val[1] |= (dmac[2] << MATCH_L2_KEY1_DMAC_HW2_SHIFT);
+		mask_val[2] = (smac[0] << MATCH_L2_KEY2_SMAC_HW0_SHIFT);
+		mask_val[2] |= (smac[1] << MATCH_L2_KEY2_SMAC_HW1_SHIFT);
+		mask_val[3] = (smac[2] << MATCH_L2_KEY3_SMAC_HW2_SHIFT);
+		mask_val[3] |= (ethertype << MATCH_L2_KEY3_ETHERTYPE_SHIFT);
+
+		rule_msg->msg.configure_msg.maskset[mask_id-1][0] = mask_val[0];
+		rule_msg->msg.configure_msg.maskset[mask_id-1][1] = mask_val[1];
+		rule_msg->msg.configure_msg.maskset[mask_id-1][2] = mask_val[2];
+		rule_msg->msg.configure_msg.maskset[mask_id-1][3] = mask_val[3];
+		rule_msg->msg.configure_msg.valid_mask_flag = mask_id;
+		break;
+	default:
+		pr_info("Invalid parse type: %d", type);
+		goto fail;
+	}
+
+	return 0;
+
+fail:
+	pr_warn("Invalid input, Check help: cat /proc/sys/dev/nss/match/help");
+	return -EINVAL;
+}
+
+/*
+ * nss_match_l2_table_read()
+ * 	Reads stats for l2 profile.
+ */
+static size_t nss_match_l2_table_read(struct nss_match_instance *db_instance, size_t buflen, char *bufp) {
+	int i, j;
+	struct nss_ctx_instance *nss_ctx = nss_match_get_context();
+	struct net_device *net_dev;
+	uint64_t mask_hit_count = 0;
+	size_t size_wr = 0;
+	char *dev_name;
+
+	size_wr += scnprintf(bufp + size_wr, buflen - size_wr, "\nProfile Type = %d\n", db_instance->profile_type);
+
+	for (i = 0; i < NSS_MATCH_MASK_MAX; i++) {
+		if (!(db_instance->valid_mask_flag & (1 << i))) {
+			size_wr += scnprintf(bufp + size_wr, buflen - size_wr, "Mask %d = Invalid\n", i+1);
+			continue;
+		}
+
+		for (j = 0; j < NSS_MATCH_INSTANCE_RULE_MAX; j++) {
+			if (!db_instance->valid_rule_mask[i][j]) {
+				continue;
+			}
+
+			mask_hit_count += db_instance->stats.hit_count[j];
+		}
+
+		size_wr += scnprintf(bufp + size_wr, buflen - size_wr, "Mask %d =%x %x %x %x\t\t Rule hits using mask %d = %llu\n\n",
+				i+1, db_instance->maskset[i][3], db_instance->maskset[i][2], db_instance->maskset[i][1], db_instance->maskset[i][0], i+1, mask_hit_count);
+		mask_hit_count = 0;
+	}
+
+	size_wr += scnprintf(bufp + size_wr, buflen - size_wr, "%8s  %20s  %8s  %8s  %18s  %18s  %10s  %8s  %8s  %9s\n\n",
+		                "rule_id", "hit_count_per_rule", "mask_id", "if_name", "dest_mac_addr", "src_mac_addr", "ethertype", "action", "prio", "nh_ifnum");
+
+	for (j = 0; j < NSS_MATCH_INSTANCE_RULE_MAX; j++) {
+		if (!db_instance->rules[j].valid_rule)
+			continue;
+
+		dev_name = "N/A";
+		net_dev = nss_cmn_get_interface_dev(nss_ctx, db_instance->rules[j].profile.l2.if_num);
+		if (net_dev) {
+			dev_name = net_dev->name;
+		}
+
+		size_wr += scnprintf(bufp + size_wr, buflen - size_wr, "%8d  %20llu  %8d  %8s  %18pM  %18pM  %10hx  %8u  %8d  %9d\n",
+				j + 1,
+				db_instance->stats.hit_count[j],
+				db_instance->rules[j].profile.l2.mask_id,
+				dev_name,
+				&db_instance->rules[j].profile.l2.dmac,
+				&db_instance->rules[j].profile.l2.smac,
+				db_instance->rules[j].profile.l2.ethertype,
+				db_instance->rules[j].profile.l2.action.action_flag,
+				db_instance->rules[j].profile.l2.action.setprio,
+				db_instance->rules[j].profile.l2.action.forward_ifnum);
+	}
+
+	return size_wr;
+}
+
+/*
+ * Match ops for L2 profile.
+ */
+static struct match_profile_ops match_profile_ops_l2 = {
+	nss_match_l2_rule_find,
+	nss_match_l2_db_rule_add,
+	nss_match_l2_rule_read,
+	nss_match_l2_table_read,
+	nss_match_l2_cmd_parse,
+};
+
+void nss_match_l2_init(void) {
+	/*
+	 * Register the L2 profile ops.
+	 */
+	nss_match_profile_ops_register(NSS_MATCH_PROFILE_TYPE_L2, &match_profile_ops_l2);
+	nss_match_info("L2 profile initialization done\n");
+}
diff --git a/qca-nss-clients/match/nss_match_l2.h b/qca-nss-clients/match/nss_match_l2.h
new file mode 100644
index 0000000..40ef8f8
--- /dev/null
+++ b/qca-nss-clients/match/nss_match_l2.h
@@ -0,0 +1,24 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ********************************************************************************
+ **/
+
+#ifndef __NSS_MATCH_L2_H
+#define __NSS_MATCH_L2_H
+
+void nss_match_l2_init(void);
+
+#endif /* __NSS_MATCH_L2_H */
diff --git a/qca-nss-clients/match/nss_match_priv.h b/qca-nss-clients/match/nss_match_priv.h
new file mode 100644
index 0000000..4386696
--- /dev/null
+++ b/qca-nss-clients/match/nss_match_priv.h
@@ -0,0 +1,51 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_match_user.h"
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_match_warn(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_match_info(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_match_trace(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#else /* CONFIG_DYNAMIC_DEBUG */
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_match_DEBUG_LEVEL < 2)
+#define nss_match_warn(s, ...)
+#else
+#define nss_match_warn(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_match_DEBUG_LEVEL < 3)
+#define nss_match_info(s, ...)
+#else
+#define nss_match_info(s, ...)   pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_match_DEBUG_LEVEL < 4)
+#define nss_match_trace(s, ...)
+#else
+#define nss_match_trace(s, ...)  pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+
diff --git a/qca-nss-clients/match/nss_match_stats.c b/qca-nss-clients/match/nss_match_stats.c
new file mode 100644
index 0000000..c8f3a2b
--- /dev/null
+++ b/qca-nss-clients/match/nss_match_stats.c
@@ -0,0 +1,186 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/types.h>
+#include <nss_api_if.h>
+#include <linux/debugfs.h>
+#include "nss_match_db.h"
+#include "nss_match_priv.h"
+
+/*
+ * nss_match_stats_str
+ *	MATCH statistics strings for nss MATCH stats
+ */
+static int8_t *nss_match_stats_str[NSS_MATCH_STATS_INSTANCE_MAX] = {
+	"rx_packets",
+	"rx_bytes",
+	"tx_packets",
+	"tx_bytes",
+	"rx_queue_0_drop",
+	"rx_queue_1_drop",
+	"rx_queue_2_drop",
+	"rx_queue_3_drop",
+};
+
+/*
+ * nss_match_stats_read()
+ *	Read MATCH statistics
+ */
+static ssize_t nss_match_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int instance_count = nss_match_table_count_get();
+	uint32_t max_output_lines = 2 /* header & footer for instance stats */
+					+ instance_count * (NSS_MATCH_STATS_INSTANCE_MAX + 2) /*instance stats */
+					+ 2;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	int id, i;
+	ssize_t bytes_read = 0;
+	struct nss_match_stats match_stats = {0};
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_match_warn("Could not allocate memory for local statistics buffer\n");
+		return 0;
+	}
+
+	/*
+	 * Session stats
+	 */
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nmatch instance stats start:\n\n");
+	for (id = 1; id <= NSS_MATCH_INSTANCE_MAX; id++) {
+		if (!nss_match_db_table_validate(id)) {
+			continue;
+		}
+
+		if (!nss_match_db_stats_get(id, &match_stats)) {
+			nss_match_warn("Could not read stats for table_id = %d\n", id);
+			continue;
+		}
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "Table_id= %d\n\n", id);
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "if_num of match instance = %d\n\n", nss_match_get_ifnum_by_table_id(id));
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%s = %llu\n", nss_match_stats_str[NSS_MATCH_STATS_RX_PACKETS],
+					match_stats.pstats.rx_packets);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%s = %llu\n", nss_match_stats_str[NSS_MATCH_STATS_RX_BYTES],
+					match_stats.pstats.rx_bytes);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%s = %llu\n", nss_match_stats_str[NSS_MATCH_STATS_TX_PACKETS],
+					match_stats.pstats.tx_packets);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%s = %llu\n", nss_match_stats_str[NSS_MATCH_STATS_TX_BYTES],
+					match_stats.pstats.tx_bytes);
+		for (i = 0; i < NSS_MAX_NUM_PRI ; ++i) {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%s = %llu\n",
+					nss_match_stats_str[i + NSS_MATCH_STATS_RX_QUEUE_0_DROP],
+					match_stats.pstats.rx_dropped[i]);
+		}
+
+		for (i = 0; i < NSS_MATCH_INSTANCE_RULE_MAX; ++i) {
+			if (match_stats.hit_count[i] <= 0) {
+				continue;
+			}
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+					"Hit count of rule ID %d = %llu\n", i+1,
+					match_stats.hit_count[i]);
+		}
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+	}
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nMatch instance stats end\n");
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_match_stats_table_read()
+ *	Read match table entry
+ */
+static ssize_t nss_match_stats_table_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	/*
+	 * TODO: Optimize buffer size needed for table information.
+	 */
+	uint32_t max_output_lines = 2 + NSS_MATCH_INSTANCE_MAX * 2		/* for 2 maskset */
+		+ NSS_MATCH_INSTANCE_MAX * NSS_MATCH_INSTANCE_RULE_MAX *(9)	/* for:  4 rule fields + 1 rule_id + 3 action fields + 1 hit count*/
+		+ 2;
+	int i;
+	int if_num;
+	size_t size_wr = 0, buflen = 0;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	ssize_t bytes_read = 0;
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	char *bufp;
+	if (unlikely(lbuf == NULL)) {
+		nss_match_warn("%px: Could not allocate memory for local statistics buffer", fp);
+		return 0;
+	}
+
+	for (i = 1; i <= NSS_MATCH_INSTANCE_MAX; ++i) {
+		if_num = nss_match_get_ifnum_by_table_id(i);
+		if (if_num < 0) {
+			continue;
+		}
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nTable_id =%d\n", i);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "Match if_num = %d\n\n", if_num);
+		bufp = lbuf + size_wr;
+		buflen = size_al - size_wr;
+		size_wr += nss_match_db_table_read(i, buflen, bufp);
+
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_match_stats_show_table_ops
+ */
+static const struct file_operations nss_match_stats_show_table_ops = {
+	.read = nss_match_stats_table_read,
+};
+
+/*
+ * nss_match_stats_ops
+ */
+static const struct file_operations nss_match_stats_ops = {
+	.read = nss_match_stats_read,
+};
+
+/*
+ * nss_match_stats_debugfs_create()
+ *	Create MATCH node statistics debug entry.
+ */
+bool nss_match_stats_debugfs_create(struct dentry *match_config)
+{
+	if (!debugfs_create_file("showtable", 0400, match_config, NULL, &nss_match_stats_show_table_ops)) {
+		nss_match_warn("Cannot create match display dentry file");
+		debugfs_remove_recursive(match_config);
+		return false;
+	}
+
+	if (!debugfs_create_file("stats", 0400, match_config, NULL, &nss_match_stats_ops)) {
+		nss_match_warn("Cannot create MATCH dentry file");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/match/nss_match_stats.h b/qca-nss-clients/match/nss_match_stats.h
new file mode 100644
index 0000000..ce4ed46
--- /dev/null
+++ b/qca-nss-clients/match/nss_match_stats.h
@@ -0,0 +1,72 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ********************************************************************************
+ **/
+
+#ifndef __NSS_MATCH_STATS_H
+#define __NSS_MATCH_STATS_H
+
+#include <nss_api_if.h>
+#include <linux/module.h>
+#include <linux/ctype.h>
+#include <linux/debugfs.h>
+
+#define NSS_STATS_MAX_STR_LENGTH 96
+#define NSS_MATCH_STATS_INSTANCE_MAX NSS_MATCH_STATS_MAX + NSS_MATCH_INSTANCE_RULE_MAX
+
+/*
+ * nss_match_stats_type
+ * 	Match stats types.
+ */
+enum nss_match_stats_type {
+	NSS_MATCH_STATS_RX_PACKETS,
+	NSS_MATCH_STATS_RX_BYTES,
+	NSS_MATCH_STATS_TX_PACKETS,
+	NSS_MATCH_STATS_TX_BYTES,
+	NSS_MATCH_STATS_RX_QUEUE_0_DROP,
+	NSS_MATCH_STATS_RX_QUEUE_1_DROP,
+	NSS_MATCH_STATS_RX_QUEUE_2_DROP,
+	NSS_MATCH_STATS_RX_QUEUE_3_DROP,
+	NSS_MATCH_STATS_MAX
+};
+
+/*
+ * nss_match_db_node_stats
+ *	Common node stats for match.
+ */
+struct nss_match_db_node_stats {
+	uint64_t rx_packets;			/* Number of packets received. */
+	uint64_t rx_bytes;			/* Number of bytes received. */
+	uint64_t tx_packets;			/* Number of packets transmitted. */
+	uint64_t tx_bytes;			/* Number of bytes transmitted. */
+	uint64_t rx_dropped[NSS_MAX_NUM_PRI];	/* Packets dropped on receive due to queue full. */
+};
+
+/*
+ * nss_match_stats
+ *	Match rule stats.
+ */
+struct nss_match_stats {
+	struct nss_match_db_node_stats pstats;
+	uint64_t hit_count[NSS_MATCH_INSTANCE_RULE_MAX];
+};
+
+/*
+ * NSS match statistics APIs
+ */
+extern bool nss_match_stats_debugfs_create(struct dentry *match_config);
+
+#endif /* __NSS_MATCH_STATS_H */
diff --git a/qca-nss-clients/match/nss_match_vow.c b/qca-nss-clients/match/nss_match_vow.c
new file mode 100644
index 0000000..cc395a9
--- /dev/null
+++ b/qca-nss-clients/match/nss_match_vow.c
@@ -0,0 +1,454 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ********************************************************************************
+ **/
+#include "nss_match_db.h"
+#include "nss_match_priv.h"
+
+#define NSS_MATCH_MAX_DSCP 63
+#define NSS_MATCH_MAX_8021P 7
+#define NSS_MATCH_VOW_KEY_IFNUM_SHIFT 0
+#define NSS_MATCH_VOW_KEY_DSCP_SHIFT 16
+#define NSS_MATCH_VOW_KEY_INNER_8021P_SHIFT 22
+#define NSS_MATCH_VOW_KEY_OUTER_8021P_SHIFT 25
+
+/*
+ * nss_match_vow_rule_find()
+ * 	Check if rule exists already.
+ */
+static bool nss_match_vow_rule_find(struct nss_match_instance *db_instance, struct nss_match_rule_info *rule)
+{
+	uint16_t index;
+
+	/*
+	 * Check if entry is present already.
+	 */
+	for (index = 0; index < NSS_MATCH_INSTANCE_RULE_MAX; index++) {
+		struct nss_match_rule_info rule_info = db_instance->rules[index];
+
+		if (rule->valid_rule &&
+				rule_info.profile.vow.if_num == rule->profile.vow.if_num &&
+				rule_info.profile.vow.dscp == rule->profile.vow.dscp &&
+				rule_info.profile.vow.inner_8021p == rule->profile.vow.inner_8021p &&
+				rule_info.profile.vow.outer_8021p == rule->profile.vow.outer_8021p &&
+				rule_info.profile.vow.mask_id == rule->profile.vow.mask_id) {
+			nss_match_info("Rule matched.\n");
+			return true;
+		}
+	}
+
+	return false;
+}
+
+/*
+ * nss_match_vow_db_rule_add()
+ * 	Store VoW rule information.
+ */
+static bool nss_match_vow_db_rule_add(struct nss_match_instance *db_instance, struct nss_match_rule_info *rule)
+{
+	uint8_t rule_id = rule->profile.vow.rule_id;
+	uint8_t mask_id = rule->profile.vow.mask_id;
+
+	if (rule_id == 0 || rule_id > NSS_MATCH_INSTANCE_RULE_MAX) {
+		nss_match_info("Invalid rule id: %d\n", rule_id);
+		return false;
+	}
+
+	if (db_instance->rules[rule_id - 1].valid_rule) {
+		nss_match_info("Rule exists for rule id: %d\n", rule_id);
+		return false;
+	}
+
+	db_instance->rules[rule_id - 1].profile.vow.if_num = rule->profile.vow.if_num;
+	db_instance->rules[rule_id - 1].profile.vow.dscp = rule->profile.vow.dscp;
+	db_instance->rules[rule_id - 1].profile.vow.inner_8021p = rule->profile.vow.inner_8021p;
+	db_instance->rules[rule_id - 1].profile.vow.outer_8021p = rule->profile.vow.outer_8021p;
+	db_instance->rules[rule_id - 1].profile.vow.mask_id = mask_id;
+	db_instance->rules[rule_id - 1].profile.vow.action.action_flag = rule->profile.vow.action.action_flag;
+	db_instance->rules[rule_id - 1].profile.vow.action.setprio = rule->profile.vow.action.setprio;
+	db_instance->rules[rule_id - 1].profile.vow.action.forward_ifnum = rule->profile.vow.action.forward_ifnum;
+	db_instance->rules[rule_id - 1].valid_rule = true;
+	db_instance->rules[rule_id - 1].profile.vow.rule_id = rule_id;
+	db_instance->valid_rule_mask[mask_id - 1][rule_id - 1] = true;
+	db_instance->rule_count++;
+
+	return true;
+}
+
+/*
+ * nss_match_vow_rule_read()
+ *	Reads rule parameters by rule id.
+ */
+static bool nss_match_vow_rule_read(struct nss_match_instance *db_instance, struct nss_match_rule_info *rule, uint16_t rule_id)
+{
+	if (rule_id == 0 || rule_id > NSS_MATCH_INSTANCE_RULE_MAX) {
+		nss_match_info("Invalid rule id: %d\n", rule_id);
+		return false;
+	}
+
+	if (!db_instance->rules[rule_id - 1].valid_rule) {
+		nss_match_info("rule_id doesnot exist, rule_id = %d", rule_id);
+		return false;
+	}
+
+	rule->profile.vow.if_num = db_instance->rules[rule_id - 1].profile.vow.if_num;
+	rule->profile.vow.dscp = db_instance->rules[rule_id - 1].profile.vow.dscp;
+	rule->profile.vow.outer_8021p = db_instance->rules[rule_id - 1].profile.vow.outer_8021p;
+	rule->profile.vow.inner_8021p = db_instance->rules[rule_id - 1].profile.vow.inner_8021p;
+	rule->profile.vow.mask_id = db_instance->rules[rule_id - 1].profile.vow.mask_id;
+	rule->profile.vow.rule_id = db_instance->rules[rule_id - 1].profile.vow.rule_id;
+	return true;
+}
+
+/*
+ * nss_match_vow_cmd_parse()
+ *	Adds new rules to the list
+ */
+static int nss_match_vow_cmd_parse(char *input_msg, struct nss_match_msg *rule_msg, nss_match_cmd_t type)
+{
+	char *token, *param, *value;
+	struct nss_ctx_instance *nss_ctx = nss_match_get_context();
+	int ret = 0;
+	uint32_t actions = 0, if_num = 0, dscp = 0, outer_prio = 0, inner_prio = 0, setprio = 0, nexthop = 0;
+	uint16_t mask_id = 0;
+	uint32_t mask_val = 0;
+
+	/*
+	 * Parse the user input.
+	 */
+	while (input_msg != NULL) {
+		token = strsep(&input_msg, " ");
+		param = strsep(&token, "=");
+		value = token;
+		if (!param || !value) {
+			goto fail;
+		}
+
+		/*
+		 * Parsing mask ID from the message.
+		 */
+		if (!(strncasecmp(param, "mask", strlen("mask")))) {
+			if (!sscanf(value, "%hu", &mask_id)) {
+				pr_info("%px: Cannot convert to integer. Wrong input\n", nss_ctx);
+				return -EINVAL;
+			}
+
+			continue;
+		}
+
+		/*
+		 * Parsing interface name from the message.
+		 */
+		if (!(strncasecmp(param, "ifname", strlen("ifname")))) {
+			struct net_device *dev;
+
+			if (type == NSS_MATCH_ADD_MASK) {
+				if (!sscanf(value, "%x", &if_num)) {
+					pr_info("%px: Cannot convert to integer. Wrong input\n", nss_ctx);
+					return -EINVAL;
+				}
+				continue;
+			}
+
+			if (type == NSS_MATCH_ADD_RULE) {
+				dev = dev_get_by_name(&init_net, value);
+				if (!dev) {
+					pr_info("%px: Cannot find the net device\n", nss_ctx);
+					return -ENODEV;
+				}
+
+				if_num = nss_cmn_get_interface_number_by_dev(dev);
+				dev_put(dev);
+				continue;
+			}
+		}
+
+		/*
+		 * Parsing Dscp value from the message.
+		 */
+		if (!(strncasecmp(param, "dscp", strlen("dscp")))) {
+
+			if (type == NSS_MATCH_ADD_RULE) {
+				ret = sscanf(value, "%u", &dscp);
+			} else if (type == NSS_MATCH_ADD_MASK) {
+				ret = sscanf(value, "%x", &dscp);
+			}
+
+			if (!ret) {
+				pr_info("%px: Cannot convert to integer. Wrong input\n", nss_ctx);
+				return -EINVAL;
+			}
+
+			continue;
+		}
+
+		/*
+		 * Parsing 8021.p inner from the message given by host.
+		 */
+		if (!(strncasecmp(param, "802.1p_inner", strlen("802.1p_inner")))) {
+			if (type == NSS_MATCH_ADD_RULE) {
+				ret = sscanf(value, "%u", &inner_prio);
+			} else if (type == NSS_MATCH_ADD_MASK) {
+				ret = sscanf(value, "%x", &inner_prio);
+			}
+
+			if (!ret) {
+				pr_info("%px: Cannot convert to integer. Wrong input!!\n", nss_ctx);
+				return -EINVAL;
+			}
+
+			continue;
+		}
+
+		/*
+		 * Parsing 8021.p outer from the message given by host.
+		 */
+		if (!(strncasecmp(param, "802.1p_outer", strlen("802.1p_outer")))) {
+
+			if (type == NSS_MATCH_ADD_RULE) {
+				ret = sscanf(value, "%u", &outer_prio);
+			} else if (type == NSS_MATCH_ADD_MASK) {
+				ret = sscanf(value, "%x", &outer_prio);
+			}
+
+			if (!ret) {
+				pr_info("%px: Cannot convert to integer. Wrong input\n", nss_ctx);
+				return -EINVAL;
+			}
+
+			continue;
+		}
+
+		/*
+		 * Parsing action from the message provided by user.
+		 */
+		if (!(strncasecmp(param, "action", strlen("action")))) {
+			if (!sscanf(value, "%u", &actions)) {
+				pr_info("%px: Cannot convert to integer. Wrong input\n", nss_ctx);
+				return -EINVAL;
+			}
+
+			continue;
+		}
+
+		/*
+		 * Parsing priority for action provided by user.
+		 */
+		if (!(strncasecmp(param, "priority", strlen("priority")))) {
+			if (!sscanf(value, "%u", &setprio)) {
+				pr_info("%px: Cannot convert to integer. Wrong input\n", nss_ctx);
+				return -EINVAL;
+			}
+
+			continue;
+		}
+
+		/*
+		 * Parsing nexthop for action provided by user.
+		 */
+		if (!(strncasecmp(param, "nexthop", strlen("nexthop")))) {
+			if (!sscanf(value, "%u", &nexthop)) {
+				pr_info("%px: Cannot convert to integer. Wrong input\n", nss_ctx);
+				return -EINVAL;
+			}
+
+			continue;
+		}
+
+		pr_info("%px: Not a valid input\n", nss_ctx);
+		return -EINVAL;
+	}
+
+	/*
+	 * Validate user input values.
+	 */
+	if (mask_id > NSS_MATCH_MASK_MAX) {
+		pr_info("%px: Maskset num exceeds allowed value: %d\n", nss_ctx, mask_id);
+		return -EINVAL;
+	}
+
+	if (dscp > NSS_MATCH_MAX_DSCP) {
+		pr_info("%px: Dscp value %d cannot go beyond %d\n", nss_ctx, dscp, NSS_MATCH_MAX_DSCP);
+		return -EINVAL;
+	}
+
+	if (inner_prio > NSS_MATCH_MAX_8021P || outer_prio > NSS_MATCH_MAX_8021P) {
+		pr_info("%px: Priority inner:%d outer:%d value cannot go beyond 7.\n", nss_ctx, inner_prio, outer_prio);
+		return -EINVAL;
+	}
+
+	/*
+	 * Verify correctness of field combination.
+	 */
+	switch (type) {
+	case NSS_MATCH_ADD_RULE:
+		if (!mask_id || !actions) {
+			goto fail;
+		}
+
+		switch(actions) {
+		case NSS_MATCH_ACTION_SETPRIO:
+			if (nexthop || !setprio || setprio >= NSS_MAX_NUM_PRI) {
+				goto fail;
+			}
+			break;
+		case NSS_MATCH_ACTION_FORWARD:
+			if (setprio || !nexthop) {
+				goto fail;
+			}
+			break;
+		case NSS_MATCH_ACTION_SETPRIO | NSS_MATCH_ACTION_FORWARD:
+			if (!setprio || !nexthop || setprio >= NSS_MAX_NUM_PRI) {
+				goto fail;
+			}
+			break;
+		case NSS_MATCH_ACTION_DROP:
+			if (setprio || nexthop) {
+				goto fail;
+			}
+			break;
+		default:
+			goto fail;
+		}
+
+		if (!outer_prio && inner_prio) {
+			pr_info("Wrong config for two layer of vlan, inner = %u outer = %u", inner_prio, outer_prio);
+			goto fail;
+		}
+
+		rule_msg->msg.vow_rule.if_num = if_num;
+		rule_msg->msg.vow_rule.dscp = dscp;
+		rule_msg->msg.vow_rule.outer_8021p = outer_prio;
+		rule_msg->msg.vow_rule.inner_8021p = inner_prio;
+		rule_msg->msg.vow_rule.mask_id = mask_id;
+		rule_msg->msg.vow_rule.action.setprio = setprio;
+		rule_msg->msg.vow_rule.action.action_flag = actions;
+		rule_msg->msg.vow_rule.action.forward_ifnum = nexthop;
+		break;
+	case NSS_MATCH_ADD_MASK:
+		if (!mask_id) {
+			pr_info("Missing mandatory field, mask ID.\n");
+			goto fail;
+		}
+
+		mask_val = (if_num << NSS_MATCH_VOW_KEY_IFNUM_SHIFT);
+	 	mask_val |= (dscp << NSS_MATCH_VOW_KEY_DSCP_SHIFT);
+	 	mask_val |= (inner_prio << NSS_MATCH_VOW_KEY_INNER_8021P_SHIFT);
+	 	mask_val |= (outer_prio << NSS_MATCH_VOW_KEY_OUTER_8021P_SHIFT);
+
+		rule_msg->msg.configure_msg.profile_type = NSS_MATCH_PROFILE_TYPE_VOW;
+		rule_msg->msg.configure_msg.maskset[mask_id-1][0] = mask_val;
+		rule_msg->msg.configure_msg.valid_mask_flag = mask_id;
+		break;
+	default:
+		pr_info("Invalid parse type: %d", type);
+		goto fail;
+	}
+
+	return 0;
+
+fail:
+	pr_warn("Invalid input, Check help.(cat /proc/sys/dev/nss/match/help)");
+	return -EINVAL;
+}
+
+/*
+ * nss_match_vow_table_read()
+ * 	Reads stats for VoW profile.
+ */
+static size_t nss_match_vow_table_read(struct nss_match_instance *db_instance, size_t buflen, char *bufp)
+{
+	int i, j;
+	struct nss_ctx_instance *nss_ctx = nss_match_get_context();
+	struct net_device *net_dev;
+	uint64_t mask_hit_count = 0;
+	size_t size_wr = 0;
+	char *dev_name;
+
+	size_wr += scnprintf(bufp + size_wr, buflen - size_wr, "Match if_num = %d\n", db_instance->if_num);
+	size_wr += scnprintf(bufp + size_wr, buflen - size_wr, "Profile Type = %d\n", db_instance->profile_type);
+
+	for (i = 0; i < NSS_MATCH_MASK_MAX; i++) {
+		if (!(db_instance->valid_mask_flag & (1 << i))) {
+			size_wr += scnprintf(bufp + size_wr, buflen - size_wr, "Mask %d = Invalid\n", i+1);
+			continue;
+		}
+
+		for (j = 0; j < NSS_MATCH_INSTANCE_RULE_MAX; j++) {
+			if (!db_instance->valid_rule_mask[i][j]) {
+				continue;
+			}
+
+			mask_hit_count += db_instance->stats.hit_count[j];
+		}
+
+		size_wr += scnprintf(bufp + size_wr, buflen - size_wr, "Mask %d = %x\t Rule hits using mask %d = %llu\n",
+				i+1, db_instance->maskset[i][0], i+1, mask_hit_count);
+		mask_hit_count = 0;
+	}
+
+	size_wr += scnprintf(bufp + size_wr, buflen - size_wr, "%8s %20s  %8s  %8s  %8s  %9s  %8s  %8s  %8s  %9s\n\n",
+		"rule_id", "hit count per rule", "mask_id", "if_name", "dscp", "out_vlan", "in_vlan", "action", "prio", "nh_ifnum");
+
+	for (j = 0; j < NSS_MATCH_INSTANCE_RULE_MAX; j++) {
+		if (!db_instance->rules[j].valid_rule)
+			continue;
+
+		dev_name = "N/A";
+		net_dev = nss_cmn_get_interface_dev(nss_ctx, db_instance->rules[j].profile.vow.if_num);
+		if (net_dev) {
+			dev_name = net_dev->name;
+		}
+
+		size_wr += scnprintf(bufp + size_wr, buflen - size_wr, "%8d %20llu  %8d  %8s  %8d  %8d  %8d  %8u  %8d %8d\n",
+				j+1,
+				db_instance->stats.hit_count[j],
+				db_instance->rules[j].profile.vow.mask_id,
+				dev_name,
+				db_instance->rules[j].profile.vow.dscp,
+				db_instance->rules[j].profile.vow.outer_8021p,
+				db_instance->rules[j].profile.vow.inner_8021p,
+				db_instance->rules[j].profile.vow.action.action_flag,
+				db_instance->rules[j].profile.vow.action.setprio,
+				db_instance->rules[j].profile.vow.action.forward_ifnum);
+	}
+
+	return size_wr;
+}
+
+/*
+ * Match ops for VoW profile.
+ */
+static struct match_profile_ops match_profile_vow_ops = {
+	nss_match_vow_rule_find,
+	nss_match_vow_db_rule_add,
+	nss_match_vow_rule_read,
+	nss_match_vow_table_read,
+	nss_match_vow_cmd_parse,
+};
+
+/*
+ * nss_match_vow_init()
+ * 	Initializes the VoW profile.
+ */
+void nss_match_vow_init(void) {
+
+	/*
+	 * Register the VoW profile ops.
+	 */
+	nss_match_profile_ops_register(NSS_MATCH_PROFILE_TYPE_VOW, &match_profile_vow_ops);
+	nss_match_info("VoW profile initialization done\n");
+}
diff --git a/qca-nss-clients/match/nss_match_vow.h b/qca-nss-clients/match/nss_match_vow.h
new file mode 100644
index 0000000..30f3b4e
--- /dev/null
+++ b/qca-nss-clients/match/nss_match_vow.h
@@ -0,0 +1,23 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ********************************************************************************
+ **/
+
+#ifndef __NSS_MATCH_VOW_H
+#define __NSS_MATCH_VOW_H
+
+void nss_match_vow_init(void);
+#endif /* __NSS_MATCH_VOW_H */
diff --git a/qca-nss-clients/mirror/Makefile b/qca-nss-clients/mirror/Makefile
new file mode 100644
index 0000000..0a30795
--- /dev/null
+++ b/qca-nss-clients/mirror/Makefile
@@ -0,0 +1,11 @@
+# Makefile for NSS MIRROR
+
+ccflags-y += $(NSS_CCFLAGS) -I$(obj)/../../exports
+ccflags-y += -DNSS_MIRROR_DEBUG_LEVEL=2
+ccflags-y += -Wall -Werror
+
+obj-m += qca-nss-mirror.o
+qca-nss-mirror-objs := \
+		  nss_mirror.o \
+		  nss_mirror_ctl.o \
+		  nss_mirror_init.o
diff --git a/qca-nss-clients/mirror/nss_mirror.c b/qca-nss-clients/mirror/nss_mirror.c
new file mode 100644
index 0000000..74095d3
--- /dev/null
+++ b/qca-nss-clients/mirror/nss_mirror.c
@@ -0,0 +1,905 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+
+#include "nss_mirror.h"
+
+#define NSS_MIRROR_NETDEV_NAME "mirror."
+
+/*
+ * Mirror netdevice count for naming convension.
+ */
+static u8 nss_mirror_netdev_count = 0;
+
+/*
+ * Mirror device statistics lock.
+ */
+static DEFINE_SPINLOCK(nss_mirror_stats_lock);
+
+/*
+ * Mirror interface array lock.
+ */
+static DEFINE_SPINLOCK(nss_mirror_arr_lock);
+
+/*
+ * Array of mirror interfaces.
+ */
+static struct net_device *nss_mirror_arr[NSS_MAX_MIRROR_DYNAMIC_INTERFACES];
+
+/*
+ * nss_mirror_arr_del()
+ *	API to delete mirror netdev from mirror array.
+ */
+static void nss_mirror_arr_del(struct net_device *mirror_dev)
+{
+	struct nss_mirror_instance_priv *mirror_priv = netdev_priv(mirror_dev);
+
+	spin_lock(&nss_mirror_arr_lock);
+	nss_mirror_arr[mirror_priv->mirror_arr_index] = NULL;
+	spin_unlock(&nss_mirror_arr_lock);
+}
+
+/*
+ * nss_mirror_arr_add()
+ *	API to add mirror netdev in mirror array.
+ */
+static int nss_mirror_arr_add(struct net_device *dev)
+{
+	uint8_t i;
+
+	spin_lock(&nss_mirror_arr_lock);
+	for (i = 0; i < NSS_MAX_MIRROR_DYNAMIC_INTERFACES; i++) {
+		struct nss_mirror_instance_priv *mirror_priv;
+
+		if (nss_mirror_arr[i] != NULL) {
+			continue;
+		}
+
+		/*
+		 * Add interface in mirror array.
+		 */
+		nss_mirror_arr[i] = dev;
+		mirror_priv = netdev_priv(dev);
+		mirror_priv->mirror_arr_index = i;
+		spin_unlock(&nss_mirror_arr_lock);
+		return 0;
+	}
+	spin_unlock(&nss_mirror_arr_lock);
+	return -1;
+}
+
+/*
+ * nss_mirror_display_info()
+ *	API to display configure information for the given mirror device.
+ */
+void nss_mirror_display_info(struct net_device *mirror_dev)
+{
+	struct nss_mirror_instance_priv *mirror_priv = netdev_priv(mirror_dev);
+
+	pr_info("Mirror interface:%s info:\n", mirror_dev->name);
+
+	pr_info("mirror interface number: %d\n"
+			"mirror configure: mirror size: %d, mirror point: %d, mirror offset: %d\n"
+			"rule config mode: %d\n",
+			 mirror_priv->mirror_instance_if_num, mirror_priv->mirror_size,
+			 mirror_priv->mirror_point, mirror_priv->mirror_offset,
+			 mirror_priv->rule_config_mode);
+}
+
+/*
+ * nss_mirror_display_all_info()
+ *	API to display configure information for all mirror devices.
+ */
+void nss_mirror_display_all_info(void)
+{
+	int i;
+	struct net_device *mirror_dev;
+
+	spin_lock(&nss_mirror_arr_lock);
+	for (i = 0; i < NSS_MAX_MIRROR_DYNAMIC_INTERFACES; i++) {
+
+		if (nss_mirror_arr[i] == NULL) {
+			continue;
+		}
+
+		mirror_dev = nss_mirror_arr[i];
+		nss_mirror_display_info(mirror_dev);
+	}
+	spin_unlock(&nss_mirror_arr_lock);
+}
+
+/*
+ * nss_mirror_netdev_up()
+ *	API to make the net device up.
+ */
+static int nss_mirror_netdev_up(struct net_device *dev)
+{
+	netif_start_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_mirror_netdev_down()
+ *	API to make the net device down.
+ */
+static int nss_mirror_netdev_down(struct net_device *dev)
+{
+	netif_stop_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_mirror_get_stats()
+ *	API to get statistics for mirror interface.
+ */
+static struct rtnl_link_stats64 *nss_mirror_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	struct nss_mirror_instance_priv *mirror_priv;
+
+	if (!stats) {
+		nss_mirror_warn("%px: Invalid stats parameter.\n", dev);
+		return stats;
+	}
+
+	memset(stats, 0, sizeof(struct rtnl_link_stats64));
+
+	spin_lock_bh(&nss_mirror_stats_lock);
+	if (!dev) {
+		spin_unlock_bh(&nss_mirror_stats_lock);
+		nss_mirror_warn("Invalid netdev.\n");
+		return stats;
+	}
+	dev_hold(dev);
+	mirror_priv = netdev_priv(dev);
+	memcpy(stats, &mirror_priv->stats, sizeof(struct rtnl_link_stats64));
+	dev_put(dev);
+	spin_unlock_bh(&nss_mirror_stats_lock);
+
+	return stats;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0))
+/*
+ * nss_mirror_netdev_stats64()
+ *	Netdev ops function to retrieve stats for kernel version < 4.6
+ */
+static struct rtnl_link_stats64 *nss_mirror_netdev_stats64(struct net_device *dev,
+						struct rtnl_link_stats64 *tot)
+{
+	return nss_mirror_get_stats(dev, tot);
+}
+#else
+/*
+ * nss_mirror_netdev_stats64()
+ *	Netdev ops function to retrieve stats
+ */
+static void nss_mirror_netdev_stats64(struct net_device *dev,
+						struct rtnl_link_stats64 *tot)
+{
+	nss_mirror_get_stats(dev, tot);
+}
+#endif
+
+/*
+ * nss_mirror_netdev_ops
+ *	Mirror net device operations.
+ */
+static const struct net_device_ops nss_mirror_netdev_ops = {
+	.ndo_open		= nss_mirror_netdev_up,
+	.ndo_stop		= nss_mirror_netdev_down,
+	.ndo_get_stats64	= nss_mirror_netdev_stats64,
+};
+
+/*
+ * nss_mirror_netdev_setup()
+ *	Setup the mirror net device.
+ */
+static void nss_mirror_netdev_setup(struct net_device *dev)
+{
+	dev->addr_len = 0;
+	dev->flags = IFF_NOARP;
+	dev->features = NETIF_F_FRAGLIST;
+	dev->netdev_ops = &nss_mirror_netdev_ops;
+}
+
+/*
+ * nss_mirror_stats_update()
+ *	API to update mirror interface statistics.
+ */
+static void nss_mirror_stats_update(struct net_device *mirror_dev, struct nss_mirror_stats_sync_msg *stats)
+{
+	struct rtnl_link_stats64 *netdev_stats;
+	struct nss_mirror_instance_priv *mirror_priv;
+	uint64_t dropped = 0;
+
+	spin_lock_bh(&nss_mirror_stats_lock);
+	if (!mirror_dev) {
+		spin_unlock_bh(&nss_mirror_stats_lock);
+		nss_mirror_warn("Invalid mirror interface\n");
+		return;
+	}
+
+	dev_hold(mirror_dev);
+	mirror_priv = netdev_priv(mirror_dev);
+	netdev_stats = &mirror_priv->stats;
+
+	dropped += nss_cmn_rx_dropped_sum(&stats->node_stats);
+
+	/*
+	 * TODO: Currently mirror stat tx_send fail is used by NSS firmware
+	 * even after sending the packet to the host.
+	 * So, at present, this stat cannot be used as drop stats by this API.
+	 * In future, if we need to add this stat too in mirror interface
+	 * drop stats, then NSS firmware should not use this stat after sending
+	 * the packets to the host and should use some new stat for post mirrored
+	 * errors (errors which may occur after sending the packet to the host).
+	 */
+	dropped += stats->mirror_stats.mem_alloc_fail;
+	dropped += stats->mirror_stats.copy_fail;
+
+	/*
+	 * There will not be any tx stats for mirror interface, as mirror interface
+	 * is intented to receive mirrored packets only.
+	 */
+	netdev_stats->rx_packets += stats->mirror_stats.mirror_pkts;
+	netdev_stats->rx_bytes += stats->mirror_stats.mirror_bytes;
+	netdev_stats->rx_dropped += dropped;
+	dev_put(mirror_dev);
+	spin_unlock_bh(&nss_mirror_stats_lock);
+}
+
+/*
+ * nss_mirror_event_cb()
+ *	Event callback.
+ */
+static void nss_mirror_event_cb(void *if_ctx, struct nss_cmn_msg *ncm)
+{
+	struct net_device *netdev = if_ctx;
+	struct nss_mirror_msg *nim = (struct nss_mirror_msg *)ncm;
+
+	switch (ncm->type) {
+	case NSS_MIRROR_MSG_SYNC_STATS:
+		nss_mirror_stats_update(netdev, &nim->msg.stats);
+		break;
+
+       default:
+		nss_mirror_warn("%px: Unknown Event from NSS\n", netdev);
+		break;
+       }
+}
+
+/*
+ * nss_mirror_data_cb()
+ *	Data callback.
+ */
+static void nss_mirror_data_cb(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	if (!skb || !skb->data) {
+		return;
+	}
+
+	dev_hold(netdev);
+
+	/*
+	 * Free the packet if mirror device is not up.
+	 */
+	if (!(netdev->flags & IFF_UP)) {
+		kfree_skb(skb);
+		dev_put(netdev);
+		return;
+	}
+
+	skb->dev = netdev;
+	skb->pkt_type = PACKET_HOST;
+	skb->skb_iif = netdev->ifindex;
+	skb_reset_mac_header(skb);
+	netif_receive_skb(skb);
+
+	dev_put(netdev);
+}
+
+/*
+ * nss_mirror_disable()
+ *	API to send disable message to mirror interface in NSS firmware.
+ */
+int nss_mirror_disable(struct net_device *mirror_dev)
+{
+	struct nss_mirror_msg nmm = {0};
+	struct nss_ctx_instance *nss_ctx;
+	const struct net_device_ops *ops;
+	nss_tx_status_t status;
+	int32_t if_num, ret;
+
+	if (!mirror_dev) {
+		nss_mirror_warn("Invalid input mirror interface\n");
+		return -1;
+	}
+
+	/*
+	 * Fetch the mirror netdevice.
+	 */
+	if ((if_num = nss_cmn_get_interface_number_by_dev_and_type(mirror_dev, NSS_DYNAMIC_INTERFACE_TYPE_MIRROR)) < 0) {
+		nss_mirror_warn("No valid NSS FW interface for %s device\n", mirror_dev->name);
+		return -1;
+	}
+
+	nss_ctx = nss_mirror_get_context();
+	if (!nss_ctx) {
+		nss_mirror_warn("Invalid NSS context\n");
+		return -1;
+	}
+
+	nss_cmn_msg_init(&nmm.cm, if_num, NSS_MIRROR_MSG_DISABLE, 0, NULL, NULL);
+
+	status = nss_mirror_tx_msg_sync(nss_ctx, &nmm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_mirror_warn("Sending disable config to %d mirror interface failed\n", if_num);
+		return -1;
+	}
+
+	/*
+	 * Bring down the mirror netdev.
+	 */
+	ops = mirror_dev->netdev_ops;
+	if (ops->ndo_stop) {
+		ret = ops->ndo_stop(mirror_dev);
+		if (ret) {
+			nss_mirror_warn("%s device stop function failed: %d\n", mirror_dev->name, ret);
+			return -1;
+		}
+		mirror_dev->flags &= ~IFF_UP;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(nss_mirror_disable);
+
+/*
+ * nss_mirror_enable()
+ *	API to send enable message to mirror interface in NSS firmware.
+ */
+int nss_mirror_enable(struct net_device *mirror_dev)
+{
+	struct nss_mirror_msg nmm = {0};
+	struct nss_ctx_instance *nss_ctx;
+	const struct net_device_ops *ops;
+	nss_tx_status_t status;
+	int32_t if_num, ret;
+
+	if (!mirror_dev) {
+		nss_mirror_warn("Invalid input mirror interface\n");
+		return -1;
+	}
+
+	/*
+	 * Verify the mirror netdevice.
+	 */
+	if ((if_num = nss_cmn_get_interface_number_by_dev_and_type(mirror_dev, NSS_DYNAMIC_INTERFACE_TYPE_MIRROR)) < 0) {
+		nss_mirror_warn("No valid NSS FW interface for %s device\n", mirror_dev->name);
+		return -1;
+	}
+
+	nss_ctx = nss_mirror_get_context();
+	if (!nss_ctx) {
+		nss_mirror_warn("Invalid NSS context\n");
+		return -1;
+	}
+
+	nss_cmn_msg_init(&nmm.cm, if_num, NSS_MIRROR_MSG_ENABLE, 0, NULL, NULL);
+
+	status = nss_mirror_tx_msg_sync(nss_ctx, &nmm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_mirror_warn("Sending enable config to %d mirror interface failed\n", if_num);
+		return -1;
+	}
+
+	/*
+	 * Bring up the mirror netdev.
+	 */
+	ops = mirror_dev->netdev_ops;
+	if (ops->ndo_open) {
+		ret = ops->ndo_open(mirror_dev);
+		if (ret) {
+			nss_mirror_warn("%s device open function failed: %d\n", mirror_dev->name, ret);
+			return -1;
+		}
+		mirror_dev->flags |= IFF_UP;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(nss_mirror_enable);
+
+/*
+ * nss_mirror_set_nexthop()
+ *	API to send set nexthop message to mirror interface in NSS firmware.
+ */
+int nss_mirror_set_nexthop(struct net_device *mirror_dev, int32_t mirror_next_hop)
+{
+	struct nss_mirror_msg nmm = {0};
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_mirror_instance_priv *mirror_priv;
+	int32_t mirror_if_num;
+	nss_tx_status_t status;
+
+	if (!mirror_dev) {
+		nss_mirror_warn("Invalid input mirror interface\n");
+		return -1;
+	}
+
+	/*
+	 * Validate the nexthop argument.
+	 */
+	if (mirror_next_hop >= NSS_MAX_NET_INTERFACES) {
+		nss_mirror_warn("Invalid mirror next hop interface:%d\n", mirror_next_hop);
+		return -1;
+	}
+
+	/*
+	 * Fetch the mirror netdevice.
+	 */
+	if ((mirror_if_num = nss_cmn_get_interface_number_by_dev_and_type(mirror_dev, NSS_DYNAMIC_INTERFACE_TYPE_MIRROR)) < 0) {
+		nss_mirror_warn("No valid NSS FW interface for %s device\n", mirror_dev->name);
+		return -1;
+	}
+
+	/*
+	 * Return if the mirror interface is in open state.
+	 */
+	if ((mirror_dev->flags & IFF_UP)) {
+		nss_mirror_warn("%s mirror interface is in open state\n", mirror_dev->name);
+		return -1;
+	}
+
+	mirror_priv = netdev_priv(mirror_dev);
+	if (mirror_priv->rule_config_mode == NSS_MIRROR_MODE_INGRESS_PMC) {
+		nss_mirror_warn("Nexthop already configured for %s mirror device\n", mirror_dev->name);
+		return -1;
+	}
+
+	nss_ctx = nss_mirror_get_context();
+	if (!nss_ctx) {
+		nss_mirror_warn("Invalid NSS context\n");
+		return -1;
+	}
+
+	nss_cmn_msg_init(&nmm.cm, mirror_if_num, NSS_MIRROR_MSG_SET_NEXTHOP, 0, NULL, NULL);
+	nmm.msg.nexthop.if_num = mirror_next_hop;
+
+	status = nss_mirror_tx_msg_sync(nss_ctx, &nmm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_mirror_warn("Sending set nexthop config to %d mirror interface failed"
+				" Nexthop: %d\n", mirror_if_num, mirror_next_hop);
+		return -1;
+	}
+
+	/*
+	 * Update the configure mode in mirror netdev.
+	 */
+	mirror_priv->rule_config_mode = NSS_MIRROR_MODE_INGRESS_PMC;
+
+	return 0;
+}
+EXPORT_SYMBOL(nss_mirror_set_nexthop);
+
+/*
+ * nss_mirror_reset_nexthop()
+ *	API to send reset nexthop message to mirror interface in NSS firmware.
+ */
+int nss_mirror_reset_nexthop(struct net_device *mirror_dev)
+{
+	struct nss_mirror_msg nmm = {0};
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_mirror_instance_priv *mirror_priv;
+	nss_tx_status_t status;
+	int32_t if_num;
+
+	if (!mirror_dev) {
+		nss_mirror_warn("Invalid input mirror interface\n");
+		return -1;
+	}
+
+	/*
+	 * Verify the mirror netdevice.
+	 */
+	if ((if_num = nss_cmn_get_interface_number_by_dev_and_type(mirror_dev, NSS_DYNAMIC_INTERFACE_TYPE_MIRROR)) < 0) {
+		nss_mirror_warn("No valid NSS FW interface for %s device\n", mirror_dev->name);
+		return -1;
+	}
+
+	mirror_priv = netdev_priv(mirror_dev);
+	if (mirror_priv->rule_config_mode != NSS_MIRROR_MODE_INGRESS_PMC) {
+		nss_mirror_warn("Invalid request for %s mirror device\n", mirror_dev->name);
+		return -1;
+	}
+
+	nss_ctx = nss_mirror_get_context();
+	if (!nss_ctx) {
+		nss_mirror_warn("Invalid NSS context\n");
+		return -1;
+	}
+
+	nss_cmn_msg_init(&nmm.cm, if_num, NSS_MIRROR_MSG_RESET_NEXTHOP, 0, NULL, NULL);
+
+	status = nss_mirror_tx_msg_sync(nss_ctx, &nmm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_mirror_warn("Sending reset nexthop config to %d mirror interface failed\n", if_num);
+		return -1;
+	}
+
+	/*
+	 * Reset the mirror configuration.
+	 */
+	mirror_priv->rule_config_mode = NSS_MIRROR_MODE_NONE;
+
+	return 0;
+}
+EXPORT_SYMBOL(nss_mirror_reset_nexthop);
+
+/*
+ * nss_mirror_configure()
+ *	API to send configure message to mirror interface in NSS firmware.
+ */
+int nss_mirror_configure(struct net_device *mirror_dev, enum nss_mirror_pkt_clone_point pkt_clone_point,
+		 uint16_t pkt_clone_size, uint16_t pkt_clone_offset)
+{
+	struct nss_mirror_msg nmm = {0};
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_mirror_instance_priv *mirror_priv;
+	nss_tx_status_t status;
+	int32_t if_num;
+
+	if (!mirror_dev) {
+		nss_mirror_warn("Invalid input mirror interface\n");
+		return -1;
+	}
+
+	/*
+	 * Validate clone point parameter.
+	 */
+	if (!pkt_clone_point || (pkt_clone_point >= NSS_MIRROR_PKT_CLONE_POINT_MAX)) {
+		nss_mirror_warn("Invalid clone point value: %d for device %s\n", pkt_clone_point, mirror_dev->name);
+		return -1;
+	}
+
+	/*
+	 * Fetch the mirror netdevice.
+	 */
+	if ((if_num = nss_cmn_get_interface_number_by_dev_and_type(mirror_dev, NSS_DYNAMIC_INTERFACE_TYPE_MIRROR)) < 0) {
+		nss_mirror_warn("No valid NSS FW interface for %s device\n", mirror_dev->name);
+		return -1;
+	}
+
+	nss_ctx = nss_mirror_get_context();
+	if (!nss_ctx) {
+		nss_mirror_warn("Invalid NSS context\n");
+		return -1;
+	}
+
+	nss_cmn_msg_init(&nmm.cm, if_num, NSS_MIRROR_MSG_CONFIGURE,
+			 sizeof(struct nss_mirror_configure_msg), NULL, NULL);
+	nmm.msg.config.pkt_clone_size = pkt_clone_size;
+	nmm.msg.config.pkt_clone_point = pkt_clone_point;
+	nmm.msg.config.pkt_clone_offset = pkt_clone_offset;
+
+	nss_mirror_trace("pkt_clone_size : %d pkt_clone_point %d pkt_clone_offset %d\n", nmm.msg.config.pkt_clone_size, nmm.msg.config.pkt_clone_point, nmm.msg.config.pkt_clone_offset);
+
+	status = nss_mirror_tx_msg_sync(nss_ctx, &nmm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_mirror_warn("Sending create config to %d mirror interface failed\n", if_num);
+		return -1;
+	}
+
+	/*
+	 * Save the mirror configurations in mirror netdev.
+	 */
+	mirror_priv = netdev_priv(mirror_dev);
+	mirror_priv->mirror_point = pkt_clone_point;
+	mirror_priv->mirror_offset = pkt_clone_offset;
+	mirror_priv->mirror_size = pkt_clone_size;
+
+	return 0;
+}
+EXPORT_SYMBOL(nss_mirror_configure);
+
+/*
+ * nss_mirror_reset_if_nexthop()
+ *	API to send reset nexthop command to NSS firmware.
+ * TODO: Remove this API and its usage and use NSS driver API, once
+ * similar API is added into NSS driver.
+ */
+nss_tx_status_t nss_mirror_reset_if_nexthop(uint32_t if_num)
+{
+	struct nss_if_msg nim;
+	struct nss_ctx_instance *nss_ctx;
+	nss_tx_status_t status;
+
+	/*
+	 * TODO: Use context of the input interface instead of mirror context.
+	 */
+	nss_ctx = nss_mirror_get_context();
+	if (!nss_ctx) {
+		nss_mirror_warn("Invalid NSS context\n");
+		return -1;
+	}
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_IF_RESET_NEXTHOP, 0, NULL, NULL);
+
+	status = nss_if_tx_msg(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_mirror_warn("%px: Failed to send reset nexthop message to %d interface\n", nss_ctx, if_num);
+		return status;
+	}
+
+	nss_mirror_info("%px: Reset nexthop message is sent successfully\n", nss_ctx);
+	return status;
+}
+
+/*
+ * nss_mirror_destroy_if()
+ *	API to un-register and destroy the mirror instance in NSS firmware.
+ */
+static int nss_mirror_destroy_if(struct net_device *mirror_dev)
+{
+	int32_t if_num;
+
+	/*
+	 * Fetch the mirror netdevice.
+	 */
+	if ((if_num = nss_cmn_get_interface_number_by_dev_and_type(mirror_dev, NSS_DYNAMIC_INTERFACE_TYPE_MIRROR)) < 0) {
+		nss_mirror_warn("No valid NSS FW interface for %s device\n", mirror_dev->name);
+		return -1;
+	}
+
+	nss_mirror_unregister_if(if_num);
+	if (nss_dynamic_interface_dealloc_node(if_num, NSS_DYNAMIC_INTERFACE_TYPE_MIRROR)
+			!= NSS_TX_SUCCESS) {
+		nss_mirror_warn("Failed to dealloc mirror interface instance\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_mirror_netdev_destroy()
+ *	API to un-register and free mirror net device.
+ */
+static void nss_mirror_netdev_destroy(struct net_device *mirror_dev)
+{
+	if (!mirror_dev) {
+		nss_mirror_warn("Invalid mirror device pointer\n");
+		return;
+	}
+
+	unregister_netdev(mirror_dev);
+
+	spin_lock_bh(&nss_mirror_stats_lock);
+	free_netdev(mirror_dev);
+	spin_unlock_bh(&nss_mirror_stats_lock);
+}
+
+/*
+ * nss_mirror_destroy()
+ *	API to de-register and delete mirror interface.
+ */
+int nss_mirror_destroy(struct net_device *mirror_dev)
+{
+	if (!mirror_dev) {
+		nss_mirror_warn("Invalid input mirror interface\n");
+		return -1;
+	}
+
+	/*
+	 * Destroy mirror instance in NSS firmware.
+	 */
+	if (nss_mirror_destroy_if(mirror_dev)) {
+		nss_mirror_warn("Error in destroying %s mirror interface from NSS"
+				" firmware\n", mirror_dev->name);
+		return -1;
+	}
+
+	/*
+	 * Remove mirror netdev from mirror array.
+	 */
+	nss_mirror_arr_del(mirror_dev);
+
+	/*
+	 * Destroy the mirror device.
+	 */
+	nss_mirror_netdev_destroy(mirror_dev);
+	return 0;
+}
+EXPORT_SYMBOL(nss_mirror_destroy);
+
+/*
+ * nss_mirror_create_if()
+ *	Create and register mirror instance in NSS.
+ */
+static int32_t nss_mirror_create_if(struct net_device *dev, nss_mirror_data_callback_t data_callback)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_mirror_instance_priv *mirror_priv;
+	int32_t if_num, ret;
+	uint32_t features = 0;
+
+	if_num = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_MIRROR);
+	if (if_num < 0) {
+		nss_mirror_warn("Mirror interface creation failed - alloc node failed\n");
+		return -1;
+	}
+
+	nss_ctx = nss_mirror_register_if(if_num,
+			data_callback,
+			nss_mirror_event_cb,
+			dev,
+			features);
+	if (!nss_ctx) {
+		nss_mirror_warn("%d interface registration failed\n", if_num);
+		ret = nss_dynamic_interface_dealloc_node(if_num, NSS_DYNAMIC_INTERFACE_TYPE_MIRROR);
+		if (ret != NSS_TX_SUCCESS) {
+			nss_mirror_warn("%d interface dealloc failed\n", if_num);
+		}
+		return -1;
+	}
+
+	nss_mirror_trace("Alloc status on %d interface\n", if_num);
+
+	/*
+	 * Save NSS mirror interface number in mirror netdev.
+	 */
+	mirror_priv = netdev_priv(dev);
+	mirror_priv->mirror_instance_if_num = if_num;
+
+	return if_num;
+}
+
+/*
+ * nss_mirror_create()
+ *	API to create and register mirror interface.
+ */
+struct net_device *nss_mirror_create(void)
+{
+	struct net_device *dev;
+	char *devname;
+	int32_t mirror_if_num;
+	int ret;
+
+	devname = vzalloc(strlen(NSS_MIRROR_NETDEV_NAME)+3+1);
+	if (!devname) {
+		nss_mirror_warn("memory allocation failed\n");
+		return NULL;
+	}
+
+	snprintf(devname, strlen(NSS_MIRROR_NETDEV_NAME)+3, "%s%d", NSS_MIRROR_NETDEV_NAME, nss_mirror_netdev_count);
+
+	dev = alloc_netdev(sizeof(struct nss_mirror_instance_priv), devname, NET_NAME_UNKNOWN, nss_mirror_netdev_setup);
+	if (!dev) {
+		nss_mirror_warn("netdev allocation failed\n");
+		vfree(devname);
+		return NULL;
+	}
+
+	mirror_if_num = nss_mirror_create_if(dev, nss_mirror_data_cb);
+	if (mirror_if_num < 0) {
+		nss_mirror_warn("mirror interface instance creation failed\n");
+		free_netdev(dev);
+		vfree(devname);
+		return NULL;
+	}
+
+	ret = register_netdev(dev);
+	if (ret) {
+		nss_mirror_warn("netdev registration failed\n");
+		if (nss_mirror_destroy_if(dev)) {
+			nss_mirror_warn("Error in destroying %s mirror device from"
+					" NSS firmware\n", dev->name);
+		}
+		free_netdev(dev);
+		vfree(devname);
+		return NULL;
+	}
+
+	/*
+	 * Add the mirror netdev to mirror array.
+	 */
+	if (nss_mirror_arr_add(dev)) {
+		nss_mirror_warn("Error in adding %s mirror device in mirror array\n", dev->name);
+		if (nss_mirror_destroy_if(dev)) {
+			nss_mirror_warn("Error in destroying %s mirror device from"
+					" NSS firmware\n", dev->name);
+		}
+		nss_mirror_netdev_destroy(dev);
+		vfree(devname);
+		return NULL;
+	}
+
+	nss_mirror_netdev_count++;
+	return dev;
+}
+EXPORT_SYMBOL(nss_mirror_create);
+
+/*
+ * nss_mirror_deconfigure_mirror()
+ *	API to deconfigure mirror device.
+ */
+int nss_mirror_deconfigure_mirror(struct net_device *mirror_dev)
+{
+	struct nss_mirror_instance_priv *mirror_priv = netdev_priv(mirror_dev);
+
+	if (mirror_priv->rule_config_mode == NSS_MIRROR_MODE_NONE) {
+		return 0;
+	}
+
+	if (mirror_priv->rule_config_mode == NSS_MIRROR_MODE_INGRESS_PMC) {
+		if (nss_mirror_reset_nexthop(mirror_dev)) {
+			nss_mirror_warn("Error in sending reset nexthop config to mirror interface: %d\n",
+					mirror_priv->mirror_instance_if_num);
+			return -1;
+		}
+	}
+
+	/*
+	 * Reset the mirror mode.
+	 */
+	mirror_priv->rule_config_mode = NSS_MIRROR_MODE_NONE;
+	return 0;
+}
+
+/*
+ * nss_mirror_destroy_all()
+ *	API to destroy all the configured mirror devices.
+ */
+int nss_mirror_destroy_all(void)
+{
+	int i;
+
+	for (i = 0; i < NSS_MAX_MIRROR_DYNAMIC_INTERFACES; i++) {
+		struct net_device *mirror_dev;
+
+		spin_lock(&nss_mirror_arr_lock);
+		if (nss_mirror_arr[i] == NULL) {
+			spin_unlock(&nss_mirror_arr_lock);
+			continue;
+		}
+
+		mirror_dev = nss_mirror_arr[i];
+		spin_unlock(&nss_mirror_arr_lock);
+
+		/*
+		 * Deconfigure mirror interface.
+		 */
+		if (nss_mirror_deconfigure_mirror(mirror_dev) < 0) {
+			nss_mirror_warn("Error in deconfiguring mirror interface: %s\n", mirror_dev->name);
+			return -1;
+		}
+
+		if (nss_mirror_destroy(mirror_dev)) {
+			nss_mirror_warn("Error in sending delete config to mirror interface: %s\n", mirror_dev->name);
+			return -1;
+		}
+	}
+	return 0;
+}
diff --git a/qca-nss-clients/mirror/nss_mirror.h b/qca-nss-clients/mirror/nss_mirror.h
new file mode 100644
index 0000000..8f9dc0b
--- /dev/null
+++ b/qca-nss-clients/mirror/nss_mirror.h
@@ -0,0 +1,110 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include <linux/etherdevice.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+
+#if (NSS_MIRROR_DEBUG_LEVEL < 1)
+#define nss_mirror_assert(fmt, args...)
+#else
+#define nss_mirror_assert(c) if (!(c)) { BUG_ON(!(c)); }
+#endif /* NSS_MIRROR_DEBUG_LEVEL */
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_mirror_warn(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_mirror_info(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_mirror_trace(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#else /* CONFIG_DYNAMIC_DEBUG */
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_MIRROR_DEBUG_LEVEL < 2)
+#define nss_mirror_warn(s, ...)
+#else
+#define nss_mirror_warn(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_MIRROR_DEBUG_LEVEL < 3)
+#define nss_mirror_info(s, ...)
+#else
+#define nss_mirror_info(s, ...)   pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_MIRROR_DEBUG_LEVEL < 4)
+#define nss_mirror_trace(s, ...)
+#else
+#define nss_mirror_trace(s, ...)  pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+/*
+ * Mirror configure modes.
+ */
+#define NSS_MIRROR_MODE_NONE 0x0
+#define NSS_MIRROR_MODE_INGRESS_PMC 0x1
+
+/*
+ * nss_mirror_instance_priv
+ *	Private structure of mirror net device.
+ */
+struct nss_mirror_instance_priv {
+	struct rtnl_link_stats64 stats;			/* Netdev stats. */
+	uint32_t mirror_instance_if_num;		/* NSS interface number for this mirror device. */
+	enum nss_mirror_pkt_clone_point mirror_point;	/* Point in the packet to copy from. */
+	uint16_t mirror_size;				/* Number of bytes to copy. */
+	uint16_t mirror_offset;				/* Copy offset. */
+	uint8_t rule_config_mode;			/* Configure mode. */
+	uint8_t mirror_arr_index;			/* Netdev index in mirror array. */
+};
+
+/*
+ * nss_mirror_display_info()
+ *	API to display configure information for the given mirror device.
+ */
+extern void nss_mirror_display_info(struct net_device *mirror_dev);
+
+/*
+ * nss_mirror_display_all_info()
+ *	API to display configure information for all mirror devices.
+ */
+extern void nss_mirror_display_all_info(void);
+
+/*
+ * nss_mirror_reset_if_nexthop()
+ *	API to send reset nexthop command to NSS firmware.
+ * TODO: Remove this API and its usage and use NSS driver API, once
+ * similar API is added into NSS driver.
+ */
+extern nss_tx_status_t nss_mirror_reset_if_nexthop(uint32_t if_num);
+
+/*
+ * nss_mirror_deconfigure_mirror()
+ *	API to deconfigure mirror device.
+ */
+extern int nss_mirror_deconfigure_mirror(struct net_device *mirror_dev);
+
+/*
+ * nss_mirror_destroy_all()
+ *	API to destroy all the configured mirror devices.
+ */
+extern int nss_mirror_destroy_all(void);
diff --git a/qca-nss-clients/mirror/nss_mirror_ctl.c b/qca-nss-clients/mirror/nss_mirror_ctl.c
new file mode 100644
index 0000000..2368a08
--- /dev/null
+++ b/qca-nss-clients/mirror/nss_mirror_ctl.c
@@ -0,0 +1,980 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include <linux/sysctl.h>
+#include <linux/string.h>
+
+#include "nss_mirror_public.h"
+#include "nss_mirror.h"
+
+#define NSS_MIRROR_CONFIG_PARAM_NUM 3
+#define NSS_MIRROR_SET_NEXTHOP_PARAM_NUM 2
+#define NSS_MIRROR_ENABLE_INGRESS_PMC_NUM 2
+
+/*
+ * nss_mirror_ctl_cmd_type
+ *	Mirror command types.
+ */
+enum nss_mirror_ctl_cmd_type {
+	NSS_MIRROR_CMD_UNKNOWN,			/* Unknown command. */
+	NSS_MIRROR_CMD_CREATE,			/* Create command. */
+	NSS_MIRROR_CMD_CONFIGURE,		/* Configure command. */
+	NSS_MIRROR_CMD_SET_NEXTHOP,		/* Set nexthop command. */
+	NSS_MIRROR_CMD_RESET_NEXTHOP,		/* Reset nexthop command. */
+	NSS_MIRROR_CMD_INGRESS_PMC_ENABLE,	/* Ingress promiscuous enable command. */
+	NSS_MIRROR_CMD_INGRESS_PMC_DISABLE,	/* Ingress promiscuous disable command. */
+	NSS_MIRROR_CMD_ENABLE,			/* Enable command. */
+	NSS_MIRROR_CMD_DISABLE,			/* Disable command. */
+	NSS_MIRROR_CMD_DISPLAY,			/* Display command. */
+	NSS_MIRROR_CMD_DESTROY,			/* Destroy command. */
+	NSS_MIRROR_CMD_HELP,			/* Help command. */
+};
+
+/*
+ * Sysctl table header for mirror.
+ */
+static struct ctl_table_header *nss_mirror_ctl_header;
+
+/*
+ * Mirror config data.
+ */
+static unsigned char nss_mirror_config_data[128] __read_mostly;
+
+/*
+ * nss_mirror_ctl_read_nextarg()
+ *	API to read the next argument in the command.
+ */
+static char *nss_mirror_ctl_read_nextarg(char **buf_ptr)
+{
+	if (!buf_ptr || !(*buf_ptr)) {
+		nss_mirror_warn("Read Buf is NULL\n");
+		return NULL;
+	}
+
+	return strsep(buf_ptr, " ");
+}
+
+/*
+ * nss_mirror_ctl_read_value()
+ *	API to read a value of the param in the command.
+ */
+static char *nss_mirror_ctl_read_value(char **buf_ptr, char **value_ptr, char *delim)
+{
+	*value_ptr = nss_mirror_ctl_read_nextarg(buf_ptr);
+
+	if (!(*value_ptr)) {
+		return NULL;
+	}
+
+	return strsep(value_ptr, delim);
+}
+
+/*
+ * nss_mirror_ctl_convert_char_to_u32()
+ *	API to convert character to u32.
+ */
+static int nss_mirror_ctl_convert_char_to_u32(char *buf, uint32_t *arg)
+{
+	int ret;
+
+	/*
+	 * Write the tokens to unsigned integer.
+	 */
+	ret = sscanf(buf, "%u", arg);
+	if (ret != 1) {
+		nss_mirror_warn("Failed to write the %s token to u32\n", buf);
+		return -1;
+	}
+	return 0;
+}
+
+/*
+ * nss_mirror_ctl_convert_char_to_u16()
+ *	API to convert character to u16.
+ */
+static int nss_mirror_ctl_convert_char_to_u16(char *buf, uint16_t *arg)
+{
+	int ret;
+
+	/*
+	 * Write the tokens to unsigned short integer.
+	 */
+	ret = sscanf(buf, "%hu", arg);
+	if (ret != 1) {
+		nss_mirror_warn("Failed to write the %s token to u16\n", buf);
+		return -1;
+	}
+	return 0;
+}
+
+/*
+ * nss_mirror_ctl_get_netdev_by_name()
+ *	API to get netdev from name.
+ *
+ * Note: Caller is expected to release the hold on the dev.
+ */
+static int nss_mirror_ctl_get_netdev_by_name(char *name, struct net_device **dev)
+{
+	char dev_name[IFNAMSIZ] = {0};
+
+	strlcpy(dev_name, name, IFNAMSIZ);
+	if (dev_name[strlen(dev_name) - 1] == '\n') {
+		dev_name[strlen(dev_name) - 1] = '\0';
+	}
+	nss_mirror_info("Device name: %s\n", dev_name);
+	*dev = dev_get_by_name(&init_net, dev_name);
+	if (!*dev) {
+		nss_mirror_warn("Cannot find %s netdevice\n", dev_name);
+		return -1;
+	}
+	return 0;
+}
+
+/*
+ * nss_mirror_ctl_display_help()
+ *	API to display help.
+ */
+static void nss_mirror_ctl_display_help(void)
+{
+	pr_info("Usage: \n"
+		"echo create > <REDIRECT PATH>\n"
+		"echo configure mirrordev=<mirror dev name> [mirror_size=<MIRROR SIZE>]"
+		" [mirror_point=<MIRROR POINT>] [mirror_offset=<MIRROR OFFSET>] > <REDIRECT PATH>\n"
+		"echo enable mirrordev=<mirror dev name> > <REDIRECT PATH>\n"
+		"echo disable mirrordev=<mirror dev name> > <REDIRECT PATH>\n"
+		"echo set_nexthop mirrordev=<mirror dev name> mirror_next_hop=n2h/eth_rx\n > <REDIRECT PATH>"
+		"echo reset_nexthop mirrordev=<mirror dev name> > <REDIRECT PATH>\n"
+		"echo ingress_pmc_enable devname=<eth/ath dev name> mirrordev=<mirror dev name> > <REDIRECT PATH>\n"
+		"echo ingress_pmc_disable devname=<eth/ath dev name> > <REDIRECT PATH>\n"
+		"echo display [mirrordev=<dev name> / all] > <REDIRECT PATH>\n"
+		"echo destroy mirrordev=<mirror dev name> > <REDIRECT PATH>\n"
+		"Where,\n"
+		"\t<REDIRECT PATH> = /proc/sys/dev/nss/mirror/config\n"
+	      );
+}
+
+/*
+ * nss_mirror_ctl_parse_reset_nexthop_cmd()
+ *	API to parse reset nexthop command.
+ */
+static int nss_mirror_ctl_parse_reset_nexthop_cmd(char *buffer)
+{
+	struct net_device *mirror_dev;
+	char *param, *value;
+
+	param = nss_mirror_ctl_read_value(&buffer, &value, "=");
+	if (!param || !value) {
+		return -1;
+	}
+
+	if (strcmp(param, "mirrordev")) {
+		nss_mirror_warn("Invalid param: %s in promiscuous enable cmd\n", value);
+		return -1;
+	}
+
+	if (nss_mirror_ctl_get_netdev_by_name(value, &mirror_dev) < 0) {
+		nss_mirror_warn("Error in getting mirror net device.\n");
+		return -1;
+	}
+
+	if (nss_mirror_reset_nexthop(mirror_dev)) {
+		nss_mirror_warn("Error in sending reset nexthop config to mirror interface: %s\n", mirror_dev->name);
+		dev_put(mirror_dev);
+		return -1;
+	}
+
+	dev_put(mirror_dev);
+	return 0;
+}
+
+/*
+ * nss_mirror_ctl_parse_set_nexthop_cmd()
+ *	API to parse set nexthop command.
+ */
+static int nss_mirror_ctl_parse_set_nexthop_cmd(char *buffer)
+{
+	struct net_device *mirror_dev = NULL;
+	char *param, *value;
+	int32_t nexthop_if_num = -1;
+	uint8_t param_num = NSS_MIRROR_SET_NEXTHOP_PARAM_NUM;
+
+	do {
+		param = nss_mirror_ctl_read_value(&buffer, &value, "=");
+		if (!param || !value) {
+			return -1;
+		}
+
+		if (!strcmp(param, "mirrordev")) {
+			if (nss_mirror_ctl_get_netdev_by_name(value, &mirror_dev) < 0) {
+				nss_mirror_warn("Error in getting mirror net device.\n");
+				return -1;
+			}
+		} else if (!strcmp(param, "mirror_next_hop")) {
+			if (value[strlen(value) - 1] == '\n') {
+				value[strlen(value) - 1] = '\0';
+			}
+			if (!strcmp(value, "eth_rx")) {
+				nexthop_if_num = NSS_ETH_RX_INTERFACE;
+			} else if (!strcmp(value, "n2h")) {
+				nexthop_if_num = NSS_N2H_INTERFACE;
+			} else {
+				if (mirror_dev) {
+					dev_put(mirror_dev);
+				}
+				nss_mirror_warn("Invalid mirror next hop value %s\n", value);
+				return -1;
+			}
+		} else {
+			if (mirror_dev) {
+				dev_put(mirror_dev);
+			}
+			nss_mirror_warn("Invalid param: %s in promiscuous enable cmd\n", value);
+			return -1;
+		}
+	} while (--param_num);
+
+	if (!mirror_dev) {
+		nss_mirror_warn("Mirror device is NULL\n");
+		return -1;
+	}
+
+	if (nexthop_if_num < 0) {
+		nss_mirror_warn("Invalid nexthop interface number\n");
+		dev_put(mirror_dev);
+		return -1;
+	}
+
+	if (nss_mirror_set_nexthop(mirror_dev, nexthop_if_num)) {
+		nss_mirror_warn("Error in sending set nexthop config to mirror interface: %s\n", mirror_dev->name);
+		dev_put(mirror_dev);
+		return -1;
+	}
+
+	dev_put(mirror_dev);
+	return 0;
+}
+
+/*
+ * nss_mirror_ctl_parse_disable_cmd()
+ *	API to parse disable command.
+ */
+static int nss_mirror_ctl_parse_disable_cmd(char *buffer)
+{
+	struct net_device *mirror_dev;
+	char *param, *value;
+
+	param = nss_mirror_ctl_read_value(&buffer, &value, "=");
+	if (!param || !value) {
+		return -1;
+	}
+
+	if (strcmp(param, "mirrordev")) {
+		nss_mirror_warn("Invalid parameter %s in disable cmd\n", param);
+		return -1;
+	}
+
+	if (nss_mirror_ctl_get_netdev_by_name(value, &mirror_dev) < 0) {
+		nss_mirror_warn("Error in getting mirror net device.\n");
+		return -1;
+	}
+
+	if (nss_mirror_disable(mirror_dev)) {
+		nss_mirror_warn("Error in sending disable config to mirror interface: %s\n", mirror_dev->name);
+		dev_put(mirror_dev);
+		return -1;
+	}
+
+	dev_put(mirror_dev);
+	return 0;
+}
+
+/*
+ * nss_mirror_ctl_parse_enable_cmd()
+ *	API to parse enable command.
+ */
+static int nss_mirror_ctl_parse_enable_cmd(char *buffer)
+{
+	struct net_device *mirror_dev;
+	char *param, *value;
+
+	param = nss_mirror_ctl_read_value(&buffer, &value, "=");
+	if (!param || !value) {
+		return -1;
+	}
+
+	if (strcmp(param, "mirrordev")) {
+		nss_mirror_warn("Invalid parameter %s in enable cmd\n", param);
+		return -1;
+	}
+
+	if (nss_mirror_ctl_get_netdev_by_name(value, &mirror_dev) < 0) {
+		nss_mirror_warn("Error in getting mirror net device.\n");
+		return -1;
+	}
+
+	if (nss_mirror_enable(mirror_dev)) {
+		nss_mirror_warn("Error in sending enable config to mirror interface: %s\n", mirror_dev->name);
+		dev_put(mirror_dev);
+		return -1;
+	}
+
+	dev_put(mirror_dev);
+	return 0;
+}
+
+/*
+ * nss_mirror_ctl_parse_display_cmd()
+ *	API to parse display command.
+ */
+static int nss_mirror_ctl_parse_display_cmd(char *buffer)
+{
+	char *param, *value;
+	char dev_name[IFNAMSIZ] = {0};
+	struct net_device *mirror_dev;
+
+	param = nss_mirror_ctl_read_value(&buffer, &value, "=");
+	if (!param || !value) {
+		return -1;
+	}
+
+	if (strcmp(param, "mirrordev")) {
+		nss_mirror_warn("Invalid param %s in mirror display cmd\n", param);
+		return -1;
+	}
+
+	strlcpy(dev_name, value, IFNAMSIZ);
+	if (dev_name[strlen(dev_name) - 1] == '\n') {
+		dev_name[strlen(dev_name) - 1] = '\0';
+	}
+	nss_mirror_info("dev name: %s\n", dev_name);
+
+	if (!strcmp(dev_name, "all")) {
+		nss_mirror_display_all_info();
+		return 0;
+	}
+
+	mirror_dev = dev_get_by_name(&init_net, dev_name);
+	if (!mirror_dev) {
+		nss_mirror_warn("Cannot find the %s netdevice\n", dev_name);
+		return -1;
+	}
+
+	/*
+	 * Verify the mirror netdevice.
+	 */
+	if (nss_cmn_get_interface_number_by_dev_and_type(mirror_dev, NSS_DYNAMIC_INTERFACE_TYPE_MIRROR) < 0) {
+		dev_put(mirror_dev);
+		nss_mirror_warn("No valid NSS FW interface for %s device\n", dev_name);
+		return -1;
+	}
+
+	nss_mirror_display_info(mirror_dev);
+
+	dev_put(mirror_dev);
+	return 0;
+}
+
+/*
+ * nss_mirror_ctl_parse_enable_ingress_pmc_cmd()
+ *	API to parse ingress promiscuous enable command.
+ */
+static int nss_mirror_ctl_parse_enable_ingress_pmc_cmd(char *buffer)
+{
+	char *param, *value;
+	struct nss_ctx_instance *nss_ctx;
+	struct net_device *dev, *mirror_dev = NULL;
+	nss_tx_status_t status;
+	int32_t if_num = -1, type = 0, mirror_if_num = -1;
+	uint8_t param_num = NSS_MIRROR_ENABLE_INGRESS_PMC_NUM;
+
+	do {
+		param = nss_mirror_ctl_read_value(&buffer, &value, "=");
+		if (!param || !value) {
+			return -1;
+		}
+
+		if (!strcmp(param, "devname")) {
+			if (nss_mirror_ctl_get_netdev_by_name(value, &dev) < 0) {
+				nss_mirror_warn("Error in getting devname net device.\n");
+				if (mirror_dev) {
+					dev_put(mirror_dev);
+				}
+				return -1;
+			}
+
+			if ((if_num = nss_cmn_get_interface_number_by_dev(dev)) < 0) {
+				nss_mirror_warn("No valid NSS FW interface for %s device\n", dev->name);
+				if (mirror_dev) {
+					dev_put(mirror_dev);
+				}
+				dev_put(dev);
+				return -1;
+			}
+			dev_put(dev);
+		} else if (!strcmp(param, "mirrordev")) {
+			if (nss_mirror_ctl_get_netdev_by_name(value, &mirror_dev) < 0) {
+				nss_mirror_warn("Error in getting mirror net device.\n");
+				return -1;
+			}
+
+			/*
+			 * Verify the mirror netdevice.
+			 */
+			if ((mirror_if_num = nss_cmn_get_interface_number_by_dev_and_type(mirror_dev, NSS_DYNAMIC_INTERFACE_TYPE_MIRROR)) < 0) {
+				nss_mirror_warn("No valid NSS FW interface for %s device\n", mirror_dev->name);
+				dev_put(mirror_dev);
+				return -1;
+			}
+		} else {
+			if (mirror_dev) {
+				dev_put(mirror_dev);
+			}
+			nss_mirror_warn("Invalid param: %s in promiscuous enable cmd\n", value);
+			return -1;
+		}
+	} while (--param_num);
+
+	if (!mirror_dev) {
+		nss_mirror_warn("Mirror device is NULL\n");
+		return -1;
+	}
+
+	if ((if_num < 0) || (mirror_if_num < 0)) {
+		nss_mirror_warn("Invalid interface number\n");
+		dev_put(mirror_dev);
+		return -1;
+	}
+
+	/*
+	 * Return if the mirror interface is in open state.
+	 */
+	if (mirror_dev->flags & IFF_UP) {
+		nss_mirror_warn("%s mirror interface is in open state\n", mirror_dev->name);
+		dev_put(mirror_dev);
+		return -1;
+	}
+
+	dev_put(mirror_dev);
+
+	nss_ctx = nss_mirror_get_context();
+	if (!nss_ctx) {
+		nss_mirror_warn("Invalid NSS context\n");
+		return -1;
+	}
+
+	type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+
+	if (type == NSS_DYNAMIC_INTERFACE_TYPE_VAP) {
+		status = nss_wifi_vdev_set_next_hop(nss_wifi_get_context(), if_num, mirror_if_num);
+	} else if (if_num < NSS_MAX_PHYSICAL_INTERFACES) {
+		status = nss_phys_if_set_nexthop(nss_ctx, if_num, mirror_if_num);
+	} else {
+		nss_mirror_warn("Invalid nexthop interface:%d type:%d\n", if_num, type);
+		return -1;
+	}
+
+	if (status != NSS_TX_SUCCESS) {
+		nss_mirror_warn("Setting nexthop failed. if_num: %u, nexthop: %u\n", if_num, mirror_if_num);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_mirror_ctl_parse_disable_ingress_pmc_cmd()
+ *	API to parse ingress promiscuous disable command.
+ */
+static int nss_mirror_ctl_parse_disable_ingress_pmc_cmd(char *buffer)
+{
+	char *param, *value;
+	struct nss_ctx_instance *nss_ctx;
+	struct net_device *dev;
+	nss_tx_status_t status;
+	int32_t if_num, type = 0;
+
+	param = nss_mirror_ctl_read_value(&buffer, &value, "=");
+	if (!param || !value) {
+		return -1;
+	}
+
+	if (strcmp(param, "devname")) {
+		nss_mirror_warn("Invalid param: %s in promiscuous enable cmd\n", value);
+		return -1;
+	}
+
+	if (nss_mirror_ctl_get_netdev_by_name(value, &dev) < 0) {
+		nss_mirror_warn("Error in getting devname net device.\n");
+		return -1;
+	}
+
+	if ((if_num = nss_cmn_get_interface_number_by_dev(dev)) < 0) {
+		nss_mirror_warn("No valid NSS FW interface for %s device\n", dev->name);
+		dev_put(dev);
+		return -1;
+	}
+
+	dev_put(dev);
+
+	nss_ctx = nss_mirror_get_context();
+	if (!nss_ctx) {
+		nss_mirror_warn("Invalid NSS context\n");
+		return -1;
+	}
+
+	type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+
+	if (type == NSS_DYNAMIC_INTERFACE_TYPE_VAP) {
+		status = nss_mirror_reset_if_nexthop(if_num);
+	} else if (if_num < NSS_MAX_PHYSICAL_INTERFACES) {
+		status = nss_phys_if_reset_nexthop(nss_ctx, if_num);
+	} else {
+		nss_mirror_warn("Reset nexthop failed for %d interface, type:%d\n", if_num, type);
+		return -1;
+	}
+
+	if (status != NSS_TX_SUCCESS) {
+		nss_mirror_warn("Re-setting nexthop failed for if_num: %u\n", if_num);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_mirror_ctl_parse_destroy_cmd()
+ *	API to parse destroy command.
+ */
+static int nss_mirror_ctl_parse_destroy_cmd(char *buffer)
+{
+	struct net_device *mirror_dev;
+	char *param, *value;
+
+	param = nss_mirror_ctl_read_value(&buffer, &value, "=");
+	if (!param || !value) {
+		return -1;
+	}
+
+	if (strcmp(param, "mirrordev")) {
+		nss_mirror_warn("Invalid param %s in mirror delete command\n", param);
+		return -1;
+	}
+
+	if (nss_mirror_ctl_get_netdev_by_name(value, &mirror_dev) < 0) {
+		nss_mirror_warn("Error in getting mirror net device.\n");
+		return -1;
+	}
+
+	/*
+	 * Deconfigure mirror interface.
+	 */
+	if (nss_mirror_deconfigure_mirror(mirror_dev) < 0) {
+		nss_mirror_warn("Error in deconfiguring mirror interface: %s\n", mirror_dev->name);
+		dev_put(mirror_dev);
+		return -1;
+	}
+
+	dev_put(mirror_dev);
+
+	if (nss_mirror_destroy(mirror_dev)) {
+		nss_mirror_warn("Error in sending delete config to mirror interface: %s\n", mirror_dev->name);
+		dev_put(mirror_dev);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_mirror_ctl_parse_config_param()
+ *	API to parse configure parameters.
+ */
+static int nss_mirror_ctl_parse_config_param(char *buffer, uint16_t *size_ptr,
+		enum nss_mirror_pkt_clone_point *pt_ptr, uint16_t *offset_ptr)
+{
+	uint8_t param_num = NSS_MIRROR_CONFIG_PARAM_NUM;
+	char *param, *value;
+
+	do {
+		param = nss_mirror_ctl_read_value(&buffer, &value, "=");
+
+		/*
+		 * No configure parameter is given. Use the default configure values.
+		 */
+		if (!param || !value) {
+			return 0;
+		}
+
+		if (!strcmp(param, "mirror_size")) {
+			if (nss_mirror_ctl_convert_char_to_u16(value, size_ptr)) {
+				nss_mirror_warn("Not able to parse %s to u16\n", value);
+				return -1;
+			}
+		} else if (!strcmp(param, "mirror_point")) {
+			if (nss_mirror_ctl_convert_char_to_u32(value, pt_ptr)) {
+				nss_mirror_warn("Not able to parse %s to u32\n", value);
+				return -1;
+			}
+		} else if (!strcmp(param, "mirror_offset")) {
+			if (nss_mirror_ctl_convert_char_to_u16(value, offset_ptr)) {
+				nss_mirror_warn("Not able to parse %s to u16\n", value);
+				return -1;
+			}
+		} else {
+			nss_mirror_warn("Invalid param:%s in create cmd\n", param);
+			return -1;
+		}
+	} while (--param_num);
+
+	return 0;
+}
+
+/*
+ * nss_mirror_ctl_parse_configure_cmd()
+ *	API to parse configure command.
+ */
+static int nss_mirror_ctl_parse_configure_cmd(char *buffer)
+{
+	struct net_device *mirror_dev;
+	char *param, *value;
+	enum nss_mirror_pkt_clone_point mirror_point = NSS_MIRROR_PKT_CLONE_POINT_DEFAULT;
+	uint16_t mirror_size = 0;
+	uint16_t mirror_offset = 0;
+
+	param = nss_mirror_ctl_read_value(&buffer, &value, "=");
+	if (!param || !value) {
+		return -1;
+	}
+
+	if (strcmp(param, "mirrordev")) {
+		nss_mirror_warn("Invalid param %s in mirror configure command\n", param);
+		return -1;
+	}
+
+	if (nss_mirror_ctl_get_netdev_by_name(value, &mirror_dev) < 0) {
+		nss_mirror_warn("Error in getting mirror net device.\n");
+		return -1;
+	}
+
+	if (nss_mirror_ctl_parse_config_param(buffer, &mirror_size,
+				&mirror_point, &mirror_offset)) {
+		dev_put(mirror_dev);
+		nss_mirror_warn("Error in parsing mirror configure command\n");
+		return -1;
+	}
+
+	nss_mirror_info("Mirror size: %d, mirror point: %d, mirror offset: %d\n",
+			mirror_size, mirror_point, mirror_offset);
+
+	if (nss_mirror_configure(mirror_dev, mirror_point,
+			mirror_size, mirror_offset)) {
+		nss_mirror_warn("Error in sending config message to %s mirror interface\n", mirror_dev->name);
+		dev_put(mirror_dev);
+		return -1;
+	}
+
+	dev_put(mirror_dev);
+	return 0;
+}
+
+/*
+ * nss_mirror_ctl_parse_cmd()
+ *	API to parse mirror commands.
+ */
+static int32_t nss_mirror_ctl_parse_cmd(char *cmd)
+{
+	if (cmd == NULL) {
+		return NSS_MIRROR_CMD_UNKNOWN;
+	}
+
+	if (!strcmp(cmd, "create")) {
+		return NSS_MIRROR_CMD_CREATE;
+	}
+
+	if (!strcmp(cmd, "configure")) {
+		return NSS_MIRROR_CMD_CONFIGURE;
+	}
+
+	if (!strcmp(cmd, "enable")) {
+		return NSS_MIRROR_CMD_ENABLE;
+	}
+
+	if (!strcmp(cmd, "disable")) {
+		return NSS_MIRROR_CMD_DISABLE;
+	}
+
+	if (!strcmp(cmd, "display")) {
+		return NSS_MIRROR_CMD_DISPLAY;
+	}
+
+	if (!strcmp(cmd, "destroy")) {
+		return NSS_MIRROR_CMD_DESTROY;
+	}
+
+	if (!strcmp(cmd, "set_nexthop")) {
+		return NSS_MIRROR_CMD_SET_NEXTHOP;
+	}
+
+	if (!strcmp(cmd, "reset_nexthop")) {
+		return NSS_MIRROR_CMD_RESET_NEXTHOP;
+	}
+
+	if (!strcmp(cmd, "ingress_pmc_enable")) {
+		return NSS_MIRROR_CMD_INGRESS_PMC_ENABLE;
+	}
+
+	if (!strcmp(cmd, "ingress_pmc_disable")) {
+		return NSS_MIRROR_CMD_INGRESS_PMC_DISABLE;
+	}
+
+	if (!strcmp(cmd, "help")) {
+		return NSS_MIRROR_CMD_HELP;
+	}
+
+	nss_mirror_warn("Invalid string:%s in command\n", cmd);
+	return NSS_MIRROR_CMD_UNKNOWN;
+}
+
+/*
+ * nss_mirror_ctl_config_handler()
+ *	Mirror sysctl config handler.
+ */
+static int nss_mirror_ctl_config_handler(struct ctl_table *ctl, int write,
+		 void __user *buf, size_t *lenp, loff_t *ppos)
+{
+	char *buffer, *pfree;
+	char * nextarg;
+	int command, ret;
+	size_t count = *lenp;
+
+	/*
+	 * Find the string, return an error if not found
+	 */
+	ret = proc_dostring(ctl, write, buf, lenp, ppos);
+	if (ret || !write) {
+		return ret;
+	}
+
+	buffer = vzalloc(count + 1);
+	if (!buffer) {
+		nss_mirror_warn("%px: Dynamic allocation failed for input buffer\n", ctl);
+		return -ENOMEM;
+	}
+
+	pfree = buffer;
+
+	if (copy_from_user(buffer, buf, count)) {
+		vfree(pfree);
+		return -EFAULT;
+	}
+
+	nextarg = nss_mirror_ctl_read_nextarg(&buffer);
+	if (!nextarg) {
+		goto err;
+	}
+
+	if (nextarg[strlen(nextarg) - 1] == '\n') {
+		nextarg[strlen(nextarg) - 1] = '\0';
+	}
+
+	command = nss_mirror_ctl_parse_cmd(nextarg);
+	switch (command) {
+
+	case NSS_MIRROR_CMD_CREATE:
+	{
+		struct net_device *mirror_dev;
+		if (!(mirror_dev = nss_mirror_create())) {
+			nss_mirror_warn("%s Error in create cmd\n", __func__);
+			goto err;
+		}
+		break;
+	}
+
+	case NSS_MIRROR_CMD_CONFIGURE:
+	{
+		if (nss_mirror_ctl_parse_configure_cmd(buffer)) {
+			nss_mirror_warn("Error in parsing configure cmd\n");
+			goto err;
+		}
+		break;
+	}
+
+	case NSS_MIRROR_CMD_SET_NEXTHOP:
+	{
+		if (nss_mirror_ctl_parse_set_nexthop_cmd(buffer)) {
+			nss_mirror_warn("Error in parsing promiscuous rx enable cmd\n");
+			goto err;
+		}
+		break;
+	}
+
+	case NSS_MIRROR_CMD_RESET_NEXTHOP:
+	{
+		if (nss_mirror_ctl_parse_reset_nexthop_cmd(buffer)) {
+			nss_mirror_warn("Error in parsing promiscuous rx disable cmd\n");
+			goto err;
+		}
+		break;
+	}
+
+	case NSS_MIRROR_CMD_INGRESS_PMC_ENABLE:
+	{
+		if (nss_mirror_ctl_parse_enable_ingress_pmc_cmd(buffer)) {
+			nss_mirror_warn("Error in parsing set nexthop cmd\n");
+			goto err;
+		}
+		break;
+	}
+
+	case NSS_MIRROR_CMD_INGRESS_PMC_DISABLE:
+	{
+		if (nss_mirror_ctl_parse_disable_ingress_pmc_cmd(buffer)) {
+			nss_mirror_warn("Error in parsing reset nexthop cmd\n");
+			goto err;
+		}
+		break;
+	}
+
+	case NSS_MIRROR_CMD_DISABLE:
+	{
+		if (nss_mirror_ctl_parse_disable_cmd(buffer)) {
+			nss_mirror_warn("Error in parsing disable cmd\n");
+			goto err;
+		}
+		break;
+	}
+
+	case NSS_MIRROR_CMD_ENABLE:
+	{
+		if (nss_mirror_ctl_parse_enable_cmd(buffer)) {
+			nss_mirror_warn("Error in parsing enable cmd\n");
+			goto err;
+		}
+		break;
+	}
+
+	case NSS_MIRROR_CMD_DISPLAY:
+	{
+		if (nss_mirror_ctl_parse_display_cmd(buffer)) {
+			nss_mirror_warn("Error in parsing display cmd\n");
+			goto err;
+		}
+		break;
+	}
+
+	case NSS_MIRROR_CMD_DESTROY:
+	{
+		if (nss_mirror_ctl_parse_destroy_cmd(buffer)) {
+			nss_mirror_warn("Error in parsing destroy cmd\n");
+			goto err;
+		}
+		break;
+	}
+
+	case NSS_MIRROR_CMD_HELP:
+	{
+		nss_mirror_ctl_display_help();
+		break;
+	}
+
+	default:
+		nss_mirror_warn("Invalid input in command.\n");
+		goto err;
+	}
+
+	vfree(pfree);
+	return ret;
+err:
+	vfree(pfree);
+	return -EINVAL;
+}
+
+/*
+ * nss mirror sysctl table
+ */
+static struct ctl_table nss_mirror_table[] = {
+	{
+		.procname	= "config",
+		.data		= &nss_mirror_config_data,
+		.maxlen		= sizeof(nss_mirror_config_data),
+		.mode		= 0644,
+		.proc_handler	= &nss_mirror_ctl_config_handler,
+	},
+	{ }
+};
+
+/*
+ * nss mirror dir
+ */
+static struct ctl_table nss_mirror_root_dir[] = {
+	{
+		.procname		= "mirror",
+		.mode			= 0555,
+		.child			= nss_mirror_table,
+	},
+	{ }
+};
+
+/*
+ * nss mirror sysctl nss root dir
+ */
+static struct ctl_table nss_mirror_nss_root_dir[] = {
+	{
+		.procname		= "nss",
+		.mode			= 0555,
+		.child			= nss_mirror_root_dir,
+	},
+	{ }
+};
+
+/*
+ * nss mirror sysctl root dir
+ */
+static struct ctl_table nss_mirror_root[] = {
+	{
+		.procname		= "dev",
+		.mode			= 0555,
+		.child			= nss_mirror_nss_root_dir,
+	},
+	{ }
+};
+
+/*
+ * nss_mirror_ctl_register()
+ *	Register command line interface for mirror.
+ */
+int nss_mirror_ctl_register(void)
+{
+	nss_mirror_ctl_header = register_sysctl_table(nss_mirror_root);
+	if (!nss_mirror_ctl_header) {
+		nss_mirror_warn("Creating sysctl directory table header for mirror failed\n");
+		return -1;
+	}
+	return 0;
+}
+
+/*
+ * nss_mirror_ctl_unregister()
+ *	Un-register command line interface for mirror.
+ */
+void nss_mirror_ctl_unregister(void)
+{
+	if (nss_mirror_ctl_header) {
+		unregister_sysctl_table(nss_mirror_ctl_header);
+	}
+}
diff --git a/qca-nss-clients/mirror/nss_mirror_ctl.h b/qca-nss-clients/mirror/nss_mirror_ctl.h
new file mode 100644
index 0000000..0b0c2ec
--- /dev/null
+++ b/qca-nss-clients/mirror/nss_mirror_ctl.h
@@ -0,0 +1,29 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+/*
+ * nss_mirror_ctl_register()
+ *	Register command line interface for mirror.
+ */
+extern int nss_mirror_ctl_register(void);
+
+/*
+ * nss_mirror_ctl_unregister()
+ *	Un-register command line interface for mirror.
+ */
+extern void nss_mirror_ctl_unregister(void);
diff --git a/qca-nss-clients/mirror/nss_mirror_init.c b/qca-nss-clients/mirror/nss_mirror_init.c
new file mode 100644
index 0000000..b918fb7
--- /dev/null
+++ b/qca-nss-clients/mirror/nss_mirror_init.c
@@ -0,0 +1,61 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/module.h>
+
+#include "nss_mirror_ctl.h"
+#include "nss_mirror.h"
+
+/*
+ * nss_mirror_module_init()
+ *	Initialize mirror module.
+ */
+static int __init nss_mirror_module_init(void)
+{
+	int ret = 0;
+
+	ret = nss_mirror_ctl_register();
+	if (ret) {
+		nss_mirror_warn("Mirror ctl registration failed\n");
+		return ret;
+	}
+
+	nss_mirror_info("Mirror module initialized\n");
+	return 0;
+}
+
+/*
+ * nss_mirror_module_exit()
+ *	De-initialize mirror module.
+ */
+static void __exit nss_mirror_module_exit(void)
+{
+	if (nss_mirror_destroy_all() < 0) {
+		nss_mirror_warn("Error in destroying all the configured mirror devices\n");
+	}
+	nss_mirror_ctl_unregister();
+	nss_mirror_info("Mirror module unloaded.\n");
+}
+
+module_init(nss_mirror_module_init);
+module_exit(nss_mirror_module_exit);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS MIRROR Client");
diff --git a/qca-nss-clients/mscs/Makefile b/qca-nss-clients/mscs/Makefile
new file mode 100644
index 0000000..ea88e92
--- /dev/null
+++ b/qca-nss-clients/mscs/Makefile
@@ -0,0 +1,7 @@
+# Makefile for mscs client
+ccflags-y += -I$(obj)/../exports -I$(obj)/..
+ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)"
+ccflags-y += -DNSS_MSCS_DEBUG_LEVEL=2
+ccflags-y += -Wall -Werror
+obj-m += qca-nss-mscs.o
+qca-nss-mscs-objs := nss_mscs.o
diff --git a/qca-nss-clients/mscs/nss_mscs.c b/qca-nss-clients/mscs/nss_mscs.c
new file mode 100644
index 0000000..2f6d286
--- /dev/null
+++ b/qca-nss-clients/mscs/nss_mscs.c
@@ -0,0 +1,142 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+
+#include <qca_mscs_if.h>
+#include <qca_mesh_latency_if.h>
+#include <nss_api_if.h>
+#include <ecm_classifier_mscs_public.h>
+#include <ecm_classifier_emesh_public.h>
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+
+/*
+ * Compile messakes for dynamic enable/disable
+ */
+#define nss_mscs_warning(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_mscs_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_mscs_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_MSCS_DEBUG_LEVEL < 2)
+#define nss_mscs_warning(s, ...)
+#else
+#define nss_mscs_warning(s, ...) pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_MSCS_DEBUG_LEVEL < 3)
+#define nss_mscs_info(s, ...)
+#else
+#define nss_mscs_info(s, ...)   pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_MSCS_DEBUG_LEVEL < 4)
+#define nss_mscs_trace(s, ...)
+#else
+#define nss_mscs_trace(s, ...)  pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif
+
+/*
+ * nss_mscs_ecm
+ * 	Register MSCS client callback with ECM MSCS classifier to support MSCS wifi peer lookup.
+ */
+static struct ecm_classifier_mscs_callbacks nss_mscs_ecm = {
+	    .get_peer_priority = qca_mscs_peer_lookup_n_get_priority,
+};
+
+/*
+ * nss_emesh_ecm
+ * 	Register EMESH client callback with ECM EMSH classifier to update peer mesh latency parameters.
+ */
+static struct ecm_classifier_emesh_callbacks nss_emesh_ecm = {
+	    .update_peer_mesh_latency_params = qca_mesh_latency_update_peer_parameter,
+};
+
+/*
+ * nss_mscs_init_module()
+ *	MSCS clinet module init function
+ */
+int __init nss_mscs_init_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+
+	/*
+	 * MSCS is enabled only on supported platform
+	 */
+	if (!nss_cmn_get_nss_enabled()) {
+		nss_mscs_warning("MSCS client is not compatible with this Platform\n");
+		return -1;
+	}
+
+	if (ecm_classifier_mscs_callback_register(&nss_mscs_ecm)) {
+		nss_mscs_warning("ecm mscs classifier callback registration failed.\n");
+		return -1;
+	}
+
+	if (ecm_classifier_emesh_latency_config_callback_register(&nss_emesh_ecm)) {
+		ecm_classifier_mscs_callback_unregister();
+		nss_mscs_warning("ecm mesh classifier callback registration failed.\n");
+		return -1;
+	}
+
+	nss_mscs_info("NSS MSCS Client loaded: %s\n", NSS_CLIENT_BUILD_ID);
+	return 0;
+
+}
+
+/*
+ * nss_mscs_exit_module()
+ *	MSCS module exit function
+ */
+void __exit nss_mscs_exit_module(void)
+{
+#ifdef CONFIG_OF
+
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return;
+	}
+#endif
+
+	ecm_classifier_mscs_callback_unregister();
+	ecm_classifier_emesh_latency_config_callback_unregister();
+	nss_mscs_info("MSCS Client unloaded\n");
+
+}
+
+module_init(nss_mscs_init_module);
+module_exit(nss_mscs_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS MSCS client module");
diff --git a/qca-nss-clients/netlink/Makefile b/qca-nss-clients/netlink/Makefile
new file mode 100644
index 0000000..bf51ecb
--- /dev/null
+++ b/qca-nss-clients/netlink/Makefile
@@ -0,0 +1,82 @@
+CAPWAP_ENABLED := $(strip $(if $(filter $(capwapmgr), y), 1 , 0))
+IPSEC_ENABLED := $(strip $(if $(filter $(ipsecmgr), y), 1 , 0))
+DTLS_ENABLED := $(strip $(if $(filter $(dtlsmgr), y), 1 , 0))
+
+ccflags-y := -Wall -Werror
+ccflags-y += -I$(obj)/include
+ccflags-y += -I$(obj)/../exports
+ccflags-y += -DNSS_NL_DEBUG_LEVEL=4
+ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)"
+
+ccflags-y += -DCONFIG_NSS_NLIPV4=1
+ccflags-y += -DCONFIG_NSS_NLIPV6=1
+ccflags-y += -DCONFIG_NSS_NLOAM=1
+ccflags-y += -DCONFIG_NSS_NLGRE_REDIR_FAMILY=1
+ccflags-y += -DCONFIG_NSS_NLETHRX=1
+ccflags-y += -DCONFIG_NSS_NLDYNAMIC_INTERFACE=1
+ccflags-y += -DCONFIG_NSS_NLN2H=1
+ccflags-y += -DCONFIG_NSS_NLIPV4_REASM=1
+ccflags-y += -DCONFIG_NSS_NLIPV6_REASM=1
+ccflags-y += -DCONFIG_NSS_NLWIFILI=1
+ccflags-y += -DCONFIG_NSS_NLLSO_RX=1
+ccflags-y += -DCONFIG_NSS_NLMAP_T=1
+ccflags-y += -DCONFIG_NSS_NLPPPOE=1
+ccflags-y += -DCONFIG_NSS_NLL2TPV2=1
+ccflags-y += -DCONFIG_NSS_NLPPTP=1
+ccflags-y += -DCONFIG_NSS_NLCAPWAP=${CAPWAP_ENABLED}
+ccflags-y += -DCONFIG_NSS_NLIPSEC=${IPSEC_ENABLED}
+ccflags-y += -DCONFIG_NSS_NLDTLS=${DTLS_ENABLED}
+ccflags-y += -DCONFIG_NSS_NLUDP_ST=1
+
+qca-nss-netlink-objs := nss_nl.o
+qca-nss-netlink-objs += nss_nlgre_redir_family.o
+qca-nss-netlink-objs += nss_nlgre_redir_cmd.o
+qca-nss-netlink-objs += nss_nlgre_redir_cmn.o
+qca-nss-netlink-objs += nss_nlgre_redir.o
+qca-nss-netlink-objs += nss_nlgre_redir_lag.o
+qca-nss-netlink-objs += nss_nlipv4.o
+qca-nss-netlink-objs += nss_nlipv6.o
+qca-nss-netlink-objs += nss_nloam.o
+qca-nss-netlink-objs += nss_nlethrx.o
+qca-nss-netlink-objs += nss_nldynamic_interface.o
+qca-nss-netlink-objs += nss_nln2h.o
+qca-nss-netlink-objs += nss_nlipv4_reasm.o
+qca-nss-netlink-objs += nss_nlipv6_reasm.o
+qca-nss-netlink-objs += nss_nlwifili.o
+qca-nss-netlink-objs += nss_nllso_rx.o
+qca-nss-netlink-objs += nss_nlmap_t.o
+qca-nss-netlink-objs += nss_nlpppoe.o
+qca-nss-netlink-objs += nss_nll2tpv2.o
+qca-nss-netlink-objs += nss_nlpptp.o
+qca-nss-netlink-objs += nss_nludp_st.o
+
+ifneq (,$(filter $(capwapmgr), y))
+qca-nss-netlink-objs += nss_nlcapwap.o
+endif
+
+ifneq (,$(filter $(dtlsmgr), y))
+qca-nss-netlink-objs += nss_nldtls.o
+endif
+
+ifneq (,$(filter $(ipsecmgr), y))
+qca-nss-netlink-objs += nss_nlipsec.o
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64))
+ccflags-y += -DCONFIG_NSS_NLC2C_TX=1
+ccflags-y += -DCONFIG_NSS_NLC2C_RX=1
+qca-nss-netlink-objs += nss_nlc2c_tx.o
+qca-nss-netlink-objs += nss_nlc2c_rx.o
+else
+ccflags-y += -DCONFIG_NSS_NLC2C_TX=0
+ccflags-y += -DCONFIG_NSS_NLC2C_RX=0
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq60xx ipq60xx_64 ipq807x ipq807x_64))
+ccflags-y += -DCONFIG_NSS_NLEDMA=1
+qca-nss-netlink-objs += nss_nledma.o
+else
+ccflags-y += -DCONFIG_NSS_NLEDMA=0
+endif
+
+obj-m += qca-nss-netlink.o
diff --git a/qca-nss-clients/netlink/include/nss_nl_if.h b/qca-nss-clients/netlink/include/nss_nl_if.h
new file mode 100644
index 0000000..784bb44
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nl_if.h
@@ -0,0 +1,46 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2016, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nl_if.h
+ *	NSS Netlink interface
+ */
+#ifndef __NSS_NL_IF_H
+#define __NSS_NL_IF_H
+
+#define NSS_NL_VER_MINOR 1
+#define NSS_NL_VER_MAJOR 1
+#define NSS_NL_VER_SHIFT 8
+
+#define NSS_NL_VER ((NSS_NL_VER_MAJOR << NSS_NL_VER_SHIFT) | NSS_NL_VER_MINOR)
+
+/**
+ * @brief interface types
+ */
+enum nss_nl_iftype {
+	NSS_NL_IFTYPE_PHYSICAL = 0,
+	NSS_NL_IFTYPE_VLAN,
+	NSS_NL_IFTYPE_PPPOE,
+	NSS_NL_IFTYPE_TUNNEL_IPSEC,
+	NSS_NL_IFTYPE_TUNNEL_GRE,
+	NSS_NL_IFTYPE_TUNNEL_PPTP,
+	NSS_NL_IFTYPE_TUNNEL_TUN6RD,
+	NSS_NL_IFTYPE_MAX
+};
+
+#endif /* __NSS_NL_IF_H */
+
+
diff --git a/qca-nss-clients/netlink/include/nss_nlc2c_rx_if.h b/qca-nss-clients/netlink/include/nss_nlc2c_rx_if.h
new file mode 100644
index 0000000..312d869
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nlc2c_rx_if.h
@@ -0,0 +1,32 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nlc2c_rx_if.h
+ *	NSS Netlink c2c_rx headers
+ */
+#ifndef __NSS_NLC2C_RX_IF_H
+#define __NSS_NLC2C_RX_IF_H
+
+/**
+ * c2c_rx forwarding Family
+ */
+#define NSS_NLC2C_RX_FAMILY "nss_nlc2c_rx"
+#define NSS_NLC2C_RX_MCAST_GRP "nss_nlc2c_rx_mc"
+
+#endif /* __NSS_NLC2C_RX_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nlc2c_tx_if.h b/qca-nss-clients/netlink/include/nss_nlc2c_tx_if.h
new file mode 100644
index 0000000..e5cf381
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nlc2c_tx_if.h
@@ -0,0 +1,32 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nlc2c_tx_if.h
+ *      NSS Netlink c2c_tx headers
+ */
+#ifndef __NSS_NLC2C_TX_IF_H
+#define __NSS_NLC2C_TX_IF_H
+
+/**
+ * c2c_tx forwarding Family
+ */
+#define NSS_NLC2C_TX_FAMILY "nss_nlc2c_tx"
+#define NSS_NLC2C_TX_MCAST_GRP "nss_nlc2c_tx_mc"
+
+#endif /* __NSS_NLC2C_TX_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nlcapwap_if.h b/qca-nss-clients/netlink/include/nss_nlcapwap_if.h
new file mode 100644
index 0000000..e1a00f2
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nlcapwap_if.h
@@ -0,0 +1,183 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015,2018-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nlcapwap_if.h
+ *	NSS Netlink CAPWAP headers
+ */
+#ifndef __NSS_NLCAPWAP_IF_H
+#define __NSS_NLCAPWAP_IF_H
+
+#include <nss_nlcmn_if.h>
+
+/**
+ * Capwap family definitions
+ */
+#define NSS_NLCAPWAP_META_HEADER_SZ 32
+#define NSS_NLCAPWAP_FAMILY "nss_nlcapwap"
+#define NSS_NLCAPWAP_MCAST_GRP "nss_nlcapwap_mc"
+#define NSS_NLCAPWAP_MODE_MAX_SZ 16
+#define NSS_NLCAPWAP_PROTO_MAX_SZ 16
+#define NSS_NLCAPWAP_KEY_SZ 32
+
+/**
+ * @brief Enumeration for all command types.
+ */
+enum nss_nlcapwap_cmd_type {
+	NSS_NLCAPWAP_CMD_TYPE_UNKNOWN,			/**< Unknown command type */
+	NSS_NLCAPWAP_CMD_TYPE_CREATE_TUN,		/**< Creates a tunnel. */
+	NSS_NLCAPWAP_CMD_TYPE_DESTROY_TUN,		/**< Destroys the tunnel created. */
+	NSS_NLCAPWAP_CMD_TYPE_UPDATE_MTU,		/**< Updates the mtu of the path. */
+	NSS_NLCAPWAP_CMD_TYPE_PERF,			/**< Enables or disables performance for capwap. */
+	NSS_NLCAPWAP_CMD_TYPE_DTLS,			/**< Enables or disables dtls for capwap tunnel. */
+	NSS_NLCAPWAP_CMD_TYPE_TX_PACKETS,		/**< Helps in configuring parameters for sending traffic. */
+	NSS_NLCAPWAP_CMD_TYPE_META_HEADER,		/**< Creates a meta header for capwap. */
+	NSS_NLCAPWAP_CMD_TYPE_IP_FLOW,			/**< To add or delete an ip flow for capwap. */
+	NSS_NLCAPWAP_CMD_TYPE_KEEPALIVE,		/**< To enable or disable keepalive for capwap. */
+	NSS_NLCAPWAP_CMD_TYPE_MAX			/**< Max number of commands type. */
+};
+
+/**
+ * @brief Enumeration for ip flow type.
+ */
+enum nss_nlcapwap_ip_flow_mode {
+	NSS_NLCAPWAP_IP_FLOW_MODE_UNKNOWN,		/**< To add ip flow rule */
+	NSS_NLCAPWAP_IP_FLOW_MODE_ADD,			/**< To add ip flow rule */
+	NSS_NLCAPWAP_IP_FLOW_MODE_DEL,			/**< To delelte ip flow rule */
+	NSS_NLCAPWAP_IP_FLOW_MODE_MAX			/**< To delelte ip flow rule */
+};
+
+/**
+ * @brief Parameters for creating tunnel
+ */
+struct nss_nlcapwap_create_tun {
+	struct nss_capwap_rule_msg rule;	/**< Rule to add capwap tunnel */
+	char gmac_ifname[IFNAMSIZ];		/**< WAN interface name */
+	bool inner_trustsec_en;			/**< Inner trustsec is enabled */
+	bool outer_trustsec_en;			/**< Outer trustsec is enabled */
+	bool wireless_qos_en;			/**< Wireless qos is enabled */
+	uint8_t gmac_ifmac[ETH_ALEN];		/**< Mac address of the wan interface */
+	uint8_t bssid[ETH_ALEN];		/**< BSSID of the AP */
+	uint8_t vlan_config;			/**< Vlan is configured */
+	uint8_t pppoe_config;			/**< PPPOE is configured */
+	uint8_t csum_enable;			/**< Udp lite is configured */
+};
+
+/**
+ * @brief parameters useful for destroying the tunnel
+ */
+struct nss_nlcapwap_destroy_tun {
+	uint8_t tun_id;			/**< Tunnel associated with the netdev */
+};
+
+/**
+ * @brief parameters useful for updating the mtu of tunnel
+ */
+struct nss_nlcapwap_update_mtu {
+	struct nss_capwap_path_mtu_msg mtu;	/** Update mtu params */
+	uint8_t tun_id;				/**< Tunnel associated with the netdev */
+};
+
+/**
+ * @brief parameters useful for enabling or disabling dtls
+ */
+struct nss_nlcapwap_dtls {
+	uint32_t flags;				/**< DTLS header flags. */
+	void *app_data;				/**< Opaque data returned in callback. */
+	uint16_t tun_id;			/**< Tunnel for which dtls to be enabled. */
+	bool enable_dtls;			/**< Enables or disables dtls for capwap tunnel. */
+	uint8_t ip_version;			/**< Version of IP address */
+	struct nss_dtlsmgr_encap_config encap;	/**< Encap data. */
+	struct nss_dtlsmgr_decap_config decap;	/**< Decap data. */
+};
+
+/**
+ * @brief parameters useful for enabling or disabling performance
+ */
+struct nss_nlcapwap_perf {
+	bool perf_en;			/**< Enables or disables performance for capwap tunnel */
+};
+
+/**
+ * @brief parameters to send traffic.
+ */
+struct nss_nlcapwap_tx_packets {
+	uint32_t pkt_size;				/**< Packet size */
+	uint32_t num_of_packets;			/**< Number of packets to be transmitted */
+	uint16_t tun_id;				/**< Tunnel used for transmission */
+};
+
+/**
+ * @brief parameters used to add or delete IP flow
+ */
+struct nss_nlcapwap_ip_flow {
+	enum nss_nlcapwap_ip_flow_mode ip_flow_mode;	/**< Add or delete flow */
+	struct nss_capwap_flow_rule_msg flow;		/**< IP flow rule */
+	uint16_t tun_id;				/**< Tunnel for which the flow is added */
+};
+
+/**
+ * @brief parameters used to create meta header
+ */
+struct nss_nlcapwap_meta_header {
+	uint8_t meta_header_blob[NSS_NLCAPWAP_META_HEADER_SZ];	/**< Binary blob of meta header. */
+	uint16_t type;						/**< Type of meta header. */
+	uint16_t tun_id;					/**< Tunnel for which meta header used */
+};
+
+/**
+ * @brief parameters to enable or disable keepalive pkt transmission
+ */
+struct nss_nlcapwap_keepalive {
+	uint16_t tun_id;			/**< Tunnel used for transmission */
+	bool tx_keepalive;			/**< Flag to check for dtls keepalive ON/OFF status */
+};
+
+/**
+ * @brief capwap message
+ */
+struct nss_nlcapwap_rule {
+	struct nss_nlcmn cm;		/**< Common message header */
+
+	/**
+	 * @brief payload of an CAPWAP netlink msg
+	 */
+	union {
+		struct nss_nlcapwap_create_tun create;		/**< Create tunnel */
+		struct nss_nlcapwap_destroy_tun destroy;	/**< Destroy tunnel */
+		struct nss_nlcapwap_dtls dtls;			/**< Enables/creates or disables/destroys dtls tunnel. */
+		struct nss_nlcapwap_perf perf;			/**< Enable or disables performance. */
+		struct nss_nlcapwap_tx_packets tx_packets;	/**< Send traffic from host_to_host or end_to_end*/
+		struct nss_nlcapwap_meta_header meta_header;	/**< Creates meta header */
+		struct nss_nlcapwap_ip_flow ip_flow;		/**< Add or delete ip flow rules */
+		struct nss_nlcapwap_update_mtu update_mtu;	/**< Update mtu of the path */
+		struct nss_nlcapwap_keepalive kalive;		/**< Enable or disable keepalive transmission */
+	} msg;
+};
+
+/**
+ * @brief NETLINK capwap message init
+ * @param rule[IN] NSS NETLINK capwap rule
+ * @param type[IN] capwap cmd type
+ */
+static inline void nss_nlcapwap_rule_init(struct nss_nlcapwap_rule *rule, enum nss_nlcapwap_cmd_type type)
+{
+	nss_nlcmn_set_ver(&rule->cm, NSS_NL_VER);
+	nss_nlcmn_init_cmd(&rule->cm, sizeof(struct nss_nlcapwap_rule), type);
+}
+
+/**@}*/
+#endif /* __NSS_NLCAPWAP_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nlcmn_if.h b/qca-nss-clients/netlink/include/nss_nlcmn_if.h
new file mode 100644
index 0000000..a57eb0f
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nlcmn_if.h
@@ -0,0 +1,179 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015,2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nlcmn_if.h
+ *	NSS Netlink common headers
+ */
+#ifndef __NSS_NLCMN_IF_H
+#define __NSS_NLCMN_IF_H
+
+#define NSS_NLCMN_CB_MAX_SZ 64 /* bytes */
+
+/**
+ * @brief Common message header for each NSS netlink message
+ */
+struct nss_nlcmn {
+	uint32_t version;			/**< message version */
+	uint32_t pid;				/**< process ID for the message */
+	nss_ptr_t sock_data;			/**< socket specific info, used by kernel */
+	uint16_t cmd_len;			/**< command len */
+	uint8_t cmd_type;			/**< command type */
+	uint8_t res;				/**< reserve for future use */
+	int32_t cb_owner;			/**< CB identifier */
+	uint8_t cb_data[NSS_NLCMN_CB_MAX_SZ]; 	/**< user context buffer */
+};
+
+/**
+ * @brief NSS subsystems in alphabetical order for nssinfo tool
+ */
+enum nss_nlcmn_subsys {
+	NSS_NLCMN_SUBSYS_CAPWAP,
+	NSS_NLCMN_SUBSYS_C2C_RX,
+	NSS_NLCMN_SUBSYS_C2C_TX,
+	NSS_NLCMN_SUBSYS_DYNAMIC_INTERFACE,
+	NSS_NLCMN_SUBSYS_EDMA,
+	NSS_NLCMN_SUBSYS_ETHRX,
+	NSS_NLCMN_SUBSYS_IPV4,
+	NSS_NLCMN_SUBSYS_IPV4_REASM,
+	NSS_NLCMN_SUBSYS_IPV6,
+	NSS_NLCMN_SUBSYS_IPV6_REASM,
+	NSS_NLCMN_SUBSYS_L2TPV2,
+	NSS_NLCMN_SUBSYS_LSO_RX,
+	NSS_NLCMN_SUBSYS_MAP_T,
+	NSS_NLCMN_SUBSYS_N2H,
+	NSS_NLCMN_SUBSYS_PPPOE,
+	NSS_NLCMN_SUBSYS_PPTP,
+	NSS_NLCMN_SUBSYS_WIFILI,
+	NSS_NLCMN_SUBSYS_MAX
+};
+
+/**
+ * @brief messages senders must use this to initialize command
+ *
+ * @param cm[IN] common message
+ * @param len[IN] command length
+ * @param cmd[IN] command for the family
+ */
+static inline void nss_nlcmn_init_cmd(struct nss_nlcmn *cm, uint16_t len, uint8_t cmd)
+{
+	cm->cmd_type = cmd;
+	cm->cmd_len = len;
+}
+
+/**
+ * @brief check the version number of the incoming message
+ *
+ * @param cm[IN] common message header
+ *
+ * @return true on version match
+ */
+static inline bool nss_nlcmn_chk_ver(struct nss_nlcmn *cm, uint32_t ver)
+{
+	return cm->version == ver;
+}
+
+/**
+ * @brief set the version number for common message header
+ *
+ * @param cm[IN] common message header
+ * @param ver[IN] version number to apply
+ */
+static inline void nss_nlcmn_set_ver(struct nss_nlcmn *cm, uint32_t ver)
+{
+	cm->version = ver;
+}
+
+/**
+ * @brief get the version number from common message header
+ *
+ * @param cm[IN] common message header
+ *
+ * @return version
+ */
+static inline uint32_t nss_nlcmn_get_ver(struct nss_nlcmn *cm)
+{
+	return cm->version;
+}
+
+/**
+ * @brief get the NSS Family command type
+ *
+ * @param cm[IN] common message
+ *
+ * @return command type
+ */
+static inline uint8_t nss_nlcmn_get_cmd(struct nss_nlcmn *cm)
+{
+	return cm->cmd_type;
+}
+
+/**
+ * @brief get the NSS Family command len
+ *
+ * @param cm[IN] common message
+ *
+ * @return command len
+ */
+static inline uint16_t nss_nlcmn_get_len(struct nss_nlcmn *cm)
+{
+	return cm->cmd_len;
+}
+
+/**
+ * @brief get the callback data
+ *
+ * @param cm[IN] common message
+ * @param cb_owner[IN] callback owner ID
+ *
+ * @return callback data or NULL if the owner doesn't match
+ */
+static inline void *nss_nlcmn_get_cb_data(struct nss_nlcmn *cm, int32_t cb_owner)
+{
+	/*
+	 * if owner doesn't match then the caller is not the owner
+	 */
+	if (cm->cb_owner != cb_owner) {
+		return NULL;
+	}
+
+	return cm->cb_data;
+}
+
+/**
+ * @brief set the callback data ownership
+ *
+ * @param cm[IN] common message
+ * @param cb_owner[IN] callback owner ID
+ */
+static inline void nss_nlcmn_set_cb_owner(struct nss_nlcmn *cm, int32_t cb_owner)
+{
+	cm->cb_owner = cb_owner;
+}
+
+/**
+ * @brief clear the CB ownership (ID) after use
+ *
+ * @param cm[IN] common message
+ */
+static inline void nss_nlcmn_clr_cb_owner(struct nss_nlcmn *cm)
+{
+	nss_nlcmn_set_cb_owner(cm, -1);
+}
+
+#endif /* __NSS_NLCMN_IF_H */
+
+
diff --git a/qca-nss-clients/netlink/include/nss_nldtls_if.h b/qca-nss-clients/netlink/include/nss_nldtls_if.h
new file mode 100644
index 0000000..875e19d
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nldtls_if.h
@@ -0,0 +1,154 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015,2018-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nldtls_if.h
+ *	NSS Netlink Dtls headers
+ */
+#ifndef __NSS_NLDTLS_IF_H
+#define __NSS_NLDTLS_IF_H
+
+#include <nss_nlcmn_if.h>
+
+/**
+ * @brief Dtls definitions
+ */
+#define NSS_NLDTLS_FAMILY "nss_nldtls"
+#define NSS_NLDTLS_MCAST_GRP "nss_nldtls_mc"
+#define NSS_NLDTLS_MODE_MAX_SZ 16
+#define NSS_NLDTLS_PROTO_MAX_SZ 16
+#define NSS_NLDTLS_ENCAP_SIDE 0
+#define NSS_NLDTLS_DECAP_SIDE 1
+#define NSS_NLDTLS_TX_PKTS_MODE_END_TO_END 0
+#define NSS_NLDTLS_TX_PKTS_MODE_HOST_TO_HOST 1
+#define NSS_NLDTLS_CIPHER_KEY_MAX 32
+#define NSS_NLDTLS_AUTH_KEY_MAX 64
+#define NSS_NLDTLS_NONCE_SIZE_MAX 4
+
+/**
+ * @brief Enumeration for all command types.
+ */
+enum nss_nldtls_cmd_type {
+	NSS_NLDTLS_CMD_TYPE_UNKNOWN,			/**< Unknown command type */
+	NSS_NLDTLS_CMD_TYPE_CREATE_TUN,			/**< Creates a tunnel. */
+	NSS_NLDTLS_CMD_TYPE_DESTROY_TUN,		/**< Destroys the tunnel created. */
+	NSS_NLDTLS_CMD_TYPE_UPDATE_CONFIG,		/**< Updates the configuration of the dtls tunnel. */
+	NSS_NLDTLS_CMD_TYPE_TX_PKTS,			/**< Helps in configuring parameters for sending traffic. */
+	NSS_NLDTLS_CMD_TYPE_MAX				/**< Max number of commands type. */
+};
+
+/**
+ * @brief Parameters for crypto keys
+ */
+struct nss_nldtls_crypto_keys {
+	uint8_t cipher[NSS_NLDTLS_CIPHER_KEY_MAX];	/**< Cipher key data */
+	uint8_t auth[NSS_NLDTLS_CIPHER_KEY_MAX];	/**< Cipher key data */
+	uint8_t nonce[NSS_NLDTLS_CIPHER_KEY_MAX];	/**< Cipher key data */
+};
+
+/**
+ * @brief Parameters for encap configuration
+ */
+struct nss_nldtls_encap_config {
+	struct nss_dtlsmgr_encap_config cfg;
+	struct nss_nldtls_crypto_keys keys;
+};
+
+/**
+ * @brief Parameter for decap configuration
+ */
+struct nss_nldtls_decap_config {
+	struct nss_dtlsmgr_decap_config cfg;
+	struct nss_nldtls_crypto_keys keys;
+};
+
+/**
+ * @brief Parameters to create a tunnel.
+ */
+struct nss_nldtls_create_tun {
+	struct nss_nldtls_encap_config encap;	/**< Encap data. */
+	struct nss_nldtls_decap_config decap;	/**< Decap data. */
+	uint32_t flags;				/**< DTLS header flags. */
+	uint32_t from_mtu;			/**< Mtu of incoming interface. */
+	uint32_t to_mtu;			/**< Mtu of outgoing interface. */
+	uint8_t ip_version;			/**< Version of IP address */
+	char gmac_ifname[IFNAMSIZ];		/**< WAN interface name */
+	uint8_t gmac_ifmac[ETH_ALEN];		/**< Mac address of the wan interface */
+	uint8_t dir;				/**< Encap or decap side. */
+};
+
+/**
+ * @brief parameters useful for destroying the tunnel
+ */
+struct nss_nldtls_destroy_tun {
+	char dev_name[IFNAMSIZ];	/**< Device name associated with tunnel */
+};
+
+/**
+ * @brief parameters useful for updating the tunnel configuration
+ */
+struct nss_nldtls_update_config {
+	struct nss_dtlsmgr_config_update config_update;		/**< Update config params */
+	struct nss_nldtls_crypto_keys keys;			/**< Crypto keys. */
+	uint16_t epoch;						/**< Dtls encap epoch. */
+	uint16_t window_sz;					/**< Dtls window size parameter. */
+	char dev_name[IFNAMSIZ];				/**< Device whose config to be updated. */
+	uint8_t dir;						/**< Encap or decap side. */
+};
+
+/**
+ * @brief parameters to send traffic.
+ */
+struct nss_nldtls_tx_pkts {
+	uint32_t num_pkts;		/**< Number of packets to be transmitted */
+	uint32_t seq_num;		/**< starting sequence number */
+	uint16_t pkt_sz;		/**< Size of packet to be transmitted */
+	char dev_name[IFNAMSIZ];	/**< Device used for transmission */
+	uint8_t mode;			/**< Can be end_to_end or host_to_host*/
+	uint8_t ctype;			/**< dtls content type */
+	bool log_en;			/**< Enable or disable wireless info */
+};
+
+/**
+ * @brief dtls message
+ */
+struct nss_nldtls_rule {
+	struct nss_nlcmn cm;		/**< Common message header */
+
+	/**
+	 * @brief payload of an DTLS netlink msg
+	 */
+	union {
+		struct nss_nldtls_create_tun create;			/**< Create tunnel */
+		struct nss_nldtls_destroy_tun destroy;			/**< Destroy tunnel */
+		struct nss_nldtls_tx_pkts tx_pkts;			/**< Send traffic*/
+		struct nss_nldtls_update_config update_config;		/**< Update configuration*/
+	} msg;
+};
+
+/**
+ * @brief NETLINK dtls rule init
+ * @param rule[IN] NSS NETLINK dtls rule
+ * @param type[IN] dtls command type
+ */
+static inline void nss_nldtls_rule_init(struct nss_nldtls_rule *rule, enum nss_nldtls_cmd_type type)
+{
+	nss_nlcmn_set_ver(&rule->cm, NSS_NL_VER);
+	nss_nlcmn_init_cmd(&rule->cm, sizeof(struct nss_nldtls_rule), type);
+}
+
+/**@}*/
+#endif /* __NSS_NLDTLS_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nldynamic_interface_if.h b/qca-nss-clients/netlink/include/nss_nldynamic_interface_if.h
new file mode 100644
index 0000000..52c7491
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nldynamic_interface_if.h
@@ -0,0 +1,32 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nldynamic_interface_if.h
+ *      NSS Netlink dynamic_interface headers
+ */
+#ifndef __NSS_NLDYNAMIC_INTERFACE_IF_H
+#define __NSS_NLDYNAMIC_INTERFACE_IF_H
+
+/**
+ * dynamic interface forwarding Family
+ */
+#define NSS_NLDYNAMIC_INTERFACE_FAMILY "nss_nldyna"
+#define NSS_NLDYNAMIC_INTERFACE_MCAST_GRP "nss_nldyna_mc"
+
+#endif /* __NSS_NLDYNAMIC_INTERFACE_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nledma_if.h b/qca-nss-clients/netlink/include/nss_nledma_if.h
new file mode 100644
index 0000000..604b5de
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nledma_if.h
@@ -0,0 +1,42 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nledma_if.h
+ *      NSS Netlink Edma headers
+ */
+#ifndef __NSS_NLEDMA_IF_H
+#define __NSS_NLEDMA_IF_H
+#include "nss_edma.h"
+
+/**
+ * Edma forwarding Family
+ */
+#define NSS_NLEDMA_FAMILY "nss_nledma"
+#define NSS_NLEDMA_MCAST_GRP "nss_nledma_mc"
+
+/**
+ * @brief Edma stats
+ */
+struct nss_nledma_stats {
+	uint32_t core_id;
+	int port_id;
+	uint64_t cmn_node_stats[NSS_STATS_NODE_MAX];
+};
+
+#endif /* __NSS_NLEDMA_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nlethrx_if.h b/qca-nss-clients/netlink/include/nss_nlethrx_if.h
new file mode 100644
index 0000000..91e2ee9
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nlethrx_if.h
@@ -0,0 +1,33 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nlethrx_if.h
+ *	NSS Netlink eth_rx headers
+ */
+#ifndef __NSS_NLETHRX_IF_H
+#define __NSS_NLETHRX_IF_H
+#include "nss_eth_rx.h"
+
+/**
+ * eth_rx forwarding Family
+ */
+#define NSS_NLETHRX_FAMILY "nss_nlethrx"
+#define NSS_NLETHRX_MCAST_GRP "nss_nlethrx_mc"
+
+#endif /* __NSS_NLETHRX_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nlgre_redir_if.h b/qca-nss-clients/netlink/include/nss_nlgre_redir_if.h
new file mode 100644
index 0000000..95ddc5c
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nlgre_redir_if.h
@@ -0,0 +1,136 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015,2018-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_NLGRE_REDIR_IF_H
+#define __NSS_NLGRE_REDIR_IF_H
+
+#define NSS_NLGRE_REDIR_TUN_TYPE_MAX_SZ 16		/**< Maximum length of tunnel type */
+#define NSS_NLGRE_REDIR_MODE_MAX_SZ 16			/**< Maximum length of mode */
+#define NSS_NLGRE_REDIR_FAMILY "nss_nlgre_redir"	/**< Family */
+#define NSS_NLGRE_REDIR_MCAST_GRP "nss_nlgrerdr_mc"	/**< Multicast group */
+
+/**
+ * @brief Enumeration for all command types.
+ */
+enum nss_nlgre_redir_cmd_type {
+	NSS_NLGRE_REDIR_CMD_TYPE_UNKNOWN,		/**< Unknown command type */
+	NSS_NLGRE_REDIR_CMD_TYPE_CREATE_TUN,		/**< Create tunnel */
+	NSS_NLGRE_REDIR_CMD_TYPE_DESTROY_TUN,		/**< Destroy tunnel */
+	NSS_NLGRE_REDIR_CMD_TYPE_MAP,			/**< Map the vap interface to tunnel id */
+	NSS_NLGRE_REDIR_CMD_TYPE_UNMAP,			/**< Unmap vap and tunnel id */
+	NSS_NLGRE_REDIR_CMD_TYPE_SET_NEXT_HOP,		/**< Set the next hop of inner interface */
+	NSS_NLGRE_REDIR_CMD_TYPE_ADD_HASH,		/**< Add a hash entry*/
+	NSS_NLGRE_REDIR_CMD_TYPE_DEL_HASH,		/**< Delete a hash entry */
+	NSS_NLGRE_REDIR_CMD_TYPE_MAX,			/**< Max number of commands */
+};
+
+/**
+ * @brief Parameters to create a tunnel.
+ */
+struct nss_nlgre_redir_create_tun {
+	uint32_t sip[4];				/**< Src address of tunnel */
+	uint32_t dip[4];				/**< Dest address of tunnel */
+	uint32_t ssip[4];				/**< Src address of second tunnel */
+	uint32_t sdip[4];				/**< Dest address of second tunnel */
+	uint8_t hash_mode;				/**< Indicates how the traffic should be mapped */
+	uint8_t iptype;					/**< IPv4 = 1 and IPV6 = 2 */
+	char mode[NSS_NLGRE_REDIR_MODE_MAX_SZ];		/**< Mode can be sjack or wifi */
+	bool lag_enable;				/**< Indicates whether lag is enabled or not */
+	uint8_t res;					/**< Padding to make size multiple of 4 */
+};
+
+/**
+ * @brief parameters useful for destroying the tunnel
+ */
+struct nss_nlgre_redir_destroy_tun {
+	char netdev[IFNAMSIZ];				/**< Dev to be destroyed */
+};
+
+/**
+ * @brief parameters to create interface map message.
+ */
+struct nss_nlgre_redir_map {
+	uint32_t ipsec_sa_pattern;				/**< Ipsec association parameters */
+	uint16_t rid;						/**< Radio id */
+	uint16_t vid;						/**< Vap id */
+	char vap_nss_if[IFNAMSIZ];				/**< Vap interface name */
+	char tun_type[NSS_NLGRE_REDIR_TUN_TYPE_MAX_SZ];		/**< Tunnel type{tun, dtun, split} */
+};
+
+/**
+ * @brief parameters used to unmap the device
+ */
+struct nss_nlgre_redir_unmap {
+	char vap_nss_if[IFNAMSIZ];			/**< Dev name to be unmapped */
+	uint16_t rid;					/**< Radio id */
+	uint16_t vid;					/**< Vap id */
+	uint8_t res[2];					/**< Reserve for padding purpose */
+};
+
+/**
+ * @brief parameters used to set the next hop
+ */
+struct nss_nlgre_redir_set_next {
+	char dev_name[IFNAMSIZ];			/**< Dev whose next hop to be set */
+	char next_dev_name[IFNAMSIZ];			/**< Dev set as the set next */
+	char mode[NSS_NLGRE_REDIR_MODE_MAX_SZ];		/**< Split or wifi */
+	uint8_t res[2];					/**< Reserve for padding purpose */
+};
+
+/**
+ * @brief parameters to perform hash operations.
+ */
+struct nss_nlgre_redir_hash_ops {
+	uint16_t slave;					/**< Tunnel to which the traffic should be mapped */
+	uint8_t smac[6];				/**< Source mac address */
+	uint8_t dmac[6];				/**< Destination mac address */
+	char mode[NSS_NLGRE_REDIR_MODE_MAX_SZ];    	/**< Sjack or wifi */
+};
+
+/**@}*/
+
+/**
+ * @brief gre_redir message
+ */
+struct nss_nlgre_redir_rule {
+	struct nss_nlcmn cm;				/**< Common message header */
+
+	/**
+	 * @brief payload of an GRE_REDIR netlink msg
+	 */
+	union {
+		struct nss_nlgre_redir_create_tun create;	/**< Create tunnel */
+		struct nss_nlgre_redir_destroy_tun destroy;	/**< Destroy tunnel */
+		struct nss_nlgre_redir_map map;			/**< Map the interface */
+		struct nss_nlgre_redir_unmap unmap;		/**< Unmap the interface */
+		struct nss_nlgre_redir_set_next snext;		/**< Set next hop */
+		struct nss_nlgre_redir_hash_ops hash_ops;	/**< Add and del hash value(s) */
+	} msg;
+};
+
+/**
+ * @brief NETLINK gre_redir message init
+ * @param rule[IN] NSS NETLINK gre_redir message
+ * @param type[IN] gre_redir message type
+ */
+static inline void nss_nlgre_redir_rule_init(struct nss_nlgre_redir_rule *rule, enum nss_nlgre_redir_cmd_type type)
+{
+	nss_nlcmn_set_ver(&rule->cm, NSS_NL_VER);
+	nss_nlcmn_init_cmd(&rule->cm, sizeof(struct nss_nlgre_redir_rule), type);
+}
+
+/**@}*/
+#endif /* __NSS_NLGRE_REDIR_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nlipsec_if.h b/qca-nss-clients/netlink/include/nss_nlipsec_if.h
new file mode 100644
index 0000000..e3d43f4
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nlipsec_if.h
@@ -0,0 +1,98 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015,2018-2019 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_NLIPSEC_IF_H
+#define __NSS_NLIPSEC_IF_H
+
+/**
+ * @addtogroup nss_netlink
+ * @{
+ */
+
+/*
+ * @file nss_nlipsec_if.h
+ *	NSS Netlink IPsec headers
+ */
+
+#define NSS_NLIPSEC_FAMILY "nss_nlipsec"	/**< IPsec family */
+#define NSS_NLIPSEC_MAX_TUNNELS 16		/**< Max tunnels */
+#define NSS_NLIPSEC_MCAST_GRP "nss_nlipsec_mc"
+#define NSS_NLIPSEC_CIPHER_KEY_MAX 32
+#define NSS_NLIPSEC_AUTH_KEY_MAX 64
+#define NSS_NLIPSEC_NONCE_SIZE_MAX 4
+
+/**
+ * @brief ipsec commands types
+ */
+enum nss_nlipsec_cmd {
+	NSS_NLIPSEC_CMD_UNSPEC,				/**< Unspecified cmd. */
+	NSS_NLIPSEC_CMD_ADD_TUNNEL,			/**< Create tunnel. */
+	NSS_NLIPSEC_CMD_DEL_TUNNEL,			/**< Destroy tunnel. */
+	NSS_NLIPSEC_CMD_ADD_SA,				/**< Add Security AssociationA. */
+	NSS_NLIPSEC_CMD_DEL_SA,				/**< Delete Security Association. */
+	NSS_NLIPSEC_CMD_ADD_FLOW,			/**< Add flow. */
+	NSS_NLIPSEC_CMD_DEL_FLOW,			/**< Delete flow. */
+	NSS_NLIPSEC_CMD_MAX
+};
+
+/**
+ * @brief IPsec SA message
+ */
+struct nss_nlipsec_rule_sa {
+	struct nss_ipsecmgr_sa_tuple tuple;		/**< Security Association tuple. */
+	struct nss_ipsecmgr_sa_data data;		/**< Security Association data. */
+	uint8_t cipher_key[NSS_NLIPSEC_CIPHER_KEY_MAX];	/**< Cipher key. */
+	uint8_t auth_key[NSS_NLIPSEC_AUTH_KEY_MAX];	/**< Authentication key. */
+	uint8_t nonce[NSS_NLIPSEC_NONCE_SIZE_MAX];	/**< Nonce. */
+
+};
+
+/**
+ * @brief IPsec flow message
+ */
+struct nss_nlipsec_rule_flow {
+	struct nss_ipsecmgr_flow_tuple tuple;		/**< Flow tuple. */
+	struct nss_ipsecmgr_sa_tuple sa;		/**< Flow data. */
+};
+
+/**
+ * @brief IPsec message
+ */
+struct nss_nlipsec_rule {
+	struct nss_nlcmn cm;				/**< Common message header. */
+	char ifname[IFNAMSIZ];				/**< IPSec interface name. */
+	uint8_t ifnum;					/**< Interface Number. */
+
+	union {
+		struct nss_nlipsec_rule_flow flow;	/**< Flow rule. */
+		struct nss_nlipsec_rule_sa sa;		/**< SA rule. */
+		struct nss_ipsecmgr_event event;	/**< IPsec event. */
+	} rule;
+};
+
+/**
+ * @brief NETLINK IPsec message init
+ *
+ * @param rule[IN] NSS NETLINK IPsec message
+ * @param type[IN] IPsec message type
+ */
+static inline void nss_nlipsec_rule_init(struct nss_nlipsec_rule *rule, enum nss_nlipsec_cmd type)
+{
+	nss_nlcmn_set_ver(&rule->cm, NSS_NL_VER);
+	nss_nlcmn_init_cmd(&rule->cm, sizeof(struct nss_nlipsec_rule), type);
+}
+
+#endif /* __NSS_NLIPSEC_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nlipv4_if.h b/qca-nss-clients/netlink/include/nss_nlipv4_if.h
new file mode 100644
index 0000000..ef9de8e
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nlipv4_if.h
@@ -0,0 +1,63 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2016,2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nlipv4_if.h
+ *	NSS Netlink IPv4 headers
+ */
+#ifndef __NSS_NLIPV4_IF_H
+#define __NSS_NLIPV4_IF_H
+
+/**
+ * IPv4 forwarding Family
+ */
+#define NSS_NLIPV4_FAMILY "nss_nlipv4"
+#define NSS_NLIPV4_MCAST_GRP "nss_nlipv4_mc"
+
+#define NSS_NLIPV4_ARPHRD_IPSEC_TUNNEL_TYPE 0x31
+#define NSS_NLIPV4_VLAN_ID_NOT_CONFIGURED 0xFFF
+#define NSS_NLIPV4_MIN_MTU 576
+#define NSS_NLIPV4_MAX_MTU 65535
+
+/**
+ * @brief IPv4 rule
+ */
+struct nss_nlipv4_rule {
+	struct nss_nlcmn cm;				/**< common message header */
+
+	char flow_ifname[IFNAMSIZ];			/**< ingress interface name */
+	char return_ifname[IFNAMSIZ];			/**< egress interface name */
+
+	enum nss_nl_iftype flow_iftype;			/**< ingress interface type */
+	enum nss_nl_iftype return_iftype;		/**< egress interface type */
+
+	struct nss_ipv4_msg nim;			/**< rule message */
+	struct nss_ipv4_stats_notification stats;	/**< NSS statistics*/
+};
+
+/**
+ * @brief NETLINK IPv4 message init
+ *
+ * @param rule[IN] NSS NETLINK IPv4 rule
+ * @param type[IN] IPv4 message type
+ */
+static inline void nss_nlipv4_rule_init(struct nss_nlipv4_rule *rule, enum nss_ipv4_message_types type)
+{
+	nss_nlcmn_set_ver(&rule->cm, NSS_NL_VER);
+	nss_nlcmn_init_cmd(&rule->cm, sizeof(struct nss_nlipv4_rule), type);
+}
+
+#endif /* __NSS_NLIPV4_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nlipv4_reasm_if.h b/qca-nss-clients/netlink/include/nss_nlipv4_reasm_if.h
new file mode 100644
index 0000000..eae1511
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nlipv4_reasm_if.h
@@ -0,0 +1,32 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nlipv4_reasm_if.h
+ *	NSS Netlink ipv4_reasm headers
+ */
+#ifndef __NSS_NLIPV4_REASM_IF_H
+#define __NSS_NLIPV4_REASM_IF_H
+
+/**
+ * ipv4_reasm forwarding Family
+ */
+#define NSS_NLIPV4_REASM_FAMILY "nss_ipv4_rsm"
+#define NSS_NLIPV4_REASM_MCAST_GRP "ipv4_rsm_mc"
+
+#endif /* __NSS_NLIPV4_REASM_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nlipv6_if.h b/qca-nss-clients/netlink/include/nss_nlipv6_if.h
new file mode 100644
index 0000000..03726ca
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nlipv6_if.h
@@ -0,0 +1,86 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016,2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nlipv6_if.h
+ *	NSS Netlink IPv6 headers
+ */
+#ifndef __NSS_NLIPV6_IF_H
+#define __NSS_NLIPV6_IF_H
+
+/**
+ * IPv6 forwarding Family
+ */
+#define NSS_NLIPV6_FAMILY "nss_nlipv6"
+#define NSS_NLIPV6_MCAST_GRP "nss_nlipv6_mc"
+#define NSS_NLIPV6_ARPHRD_IPSEC_TUNNEL_TYPE 0x31
+#define NSS_NLIPV6_VLAN_ID_NOT_CONFIGURED 0xFFF
+#define NSS_NLIPV6_MIN_MTU 1280
+#define NSS_NLIPV6_MAX_MTU 65535
+
+#define NSS_NLIPV6_ADDR_BITS (sizeof(uint32_t) * 4 * BITS_PER_BYTE)	/* 128 bits */
+#define NSS_NLIPV6_SUBNET_BITS (sizeof(uint32_t) * 4 * BITS_PER_BYTE)	/* 128 bits */
+
+/**
+ * @brief IPv6 rule
+ */
+struct nss_nlipv6_rule {
+	struct nss_nlcmn cm;				/**< common message header */
+
+	char flow_ifname[IFNAMSIZ];			/**< ingress interface name */
+	char return_ifname[IFNAMSIZ];			/**< egress interface name */
+
+	enum nss_nl_iftype flow_iftype;			/**< ingress interface type */
+	enum nss_nl_iftype return_iftype;		/**< egress interface type */
+
+	struct nss_ipv6_msg nim;			/**< rule message */
+	struct nss_ipv6_stats_notification stats;	/**< NSS statistics */
+};
+
+/**
+ * @brief NETLINK IPv6 message init
+ *
+ * @param rule[IN] NSS NETLINK IPv6 rule
+ * @param type[IN] IPv6 message type
+ */
+static inline void nss_nlipv6_rule_init(struct nss_nlipv6_rule *rule, enum nss_ipv6_message_types type)
+{
+	nss_nlcmn_set_ver(&rule->cm, NSS_NL_VER);
+	nss_nlcmn_init_cmd(&rule->cm, sizeof(struct nss_nlipv6_rule), type);
+}
+
+/**
+ * @brief convert ipv6 address to NSS format
+ *
+ * @param rule[IN] IPv6 address
+ */
+static inline void nss_nlipv6_swap_addr(uint32_t *src, uint32_t *dst)
+{
+	uint32_t temp[4];
+
+	if (src == dst) {
+		memcpy(temp, src, sizeof(temp));
+		src = temp;
+	}
+
+	dst[0] = src[3];
+	dst[1] = src[2];
+	dst[2] = src[1];
+	dst[3] = src[0];
+
+}
+
+#endif /* __NSS_NLIPV6_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nlipv6_reasm_if.h b/qca-nss-clients/netlink/include/nss_nlipv6_reasm_if.h
new file mode 100644
index 0000000..5a52d91
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nlipv6_reasm_if.h
@@ -0,0 +1,32 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nlipv6_reasm_if.h
+ *	NSS Netlink ipv6_reasm headers
+ */
+#ifndef __NSS_NLIPV6_REASM_IF_H
+#define __NSS_NLIPV6_REASM_IF_H
+
+/**
+ * ipv6_reasm forwarding Family
+ */
+#define NSS_NLIPV6_REASM_FAMILY "nss_ipv6_rsm"
+#define NSS_NLIPV6_REASM_MCAST_GRP "ipv6_rsm_mc"
+
+#endif /* __NSS_NLIPV6_REASM_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nll2tpv2_if.h b/qca-nss-clients/netlink/include/nss_nll2tpv2_if.h
new file mode 100644
index 0000000..8c005f0
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nll2tpv2_if.h
@@ -0,0 +1,32 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nll2tpv2_if.h
+ *	NSS Netlink l2tpv2 headers
+ */
+#ifndef __NSS_NLL2TPV2_IF_H
+#define __NSS_NLL2TPV2_IF_H
+
+/**
+ * l2tpv2 forwarding Family
+ */
+#define NSS_NLL2TPV2_FAMILY "nss_nll2tpv2"
+#define NSS_NLL2TPV2_MCAST_GRP "nss_nll2tpv2_mc"
+
+#endif /* __NSS_NLL2TPV2_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nllso_rx_if.h b/qca-nss-clients/netlink/include/nss_nllso_rx_if.h
new file mode 100644
index 0000000..627424c
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nllso_rx_if.h
@@ -0,0 +1,32 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nllso_rx_if.h
+ *	NSS Netlink lso_rx headers
+ */
+#ifndef __NSS_NLLSO_RX_IF_H
+#define __NSS_NLLSO_RX_IF_H
+
+/**
+ * lso_rx forwarding Family
+ */
+#define NSS_NLLSO_RX_FAMILY "nss_nllso_rx"
+#define NSS_NLLSO_RX_MCAST_GRP "nss_nllso_rx_mc"
+
+#endif /* __NSS_NLLSO_RX_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nlmap_t_if.h b/qca-nss-clients/netlink/include/nss_nlmap_t_if.h
new file mode 100644
index 0000000..63d7205
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nlmap_t_if.h
@@ -0,0 +1,32 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nlmap_t_if.h
+ *	NSS Netlink map_t headers
+ */
+#ifndef __NSS_NLMAP_T_IF_H
+#define __NSS_NLMAP_T_IF_H
+
+/**
+ * map_t forwarding Family
+ */
+#define NSS_NLMAP_T_FAMILY "nss_nlmap_t"
+#define NSS_NLMAP_T_MCAST_GRP "nss_nlmap_t_mc"
+
+#endif /* __NSS_NLMAP_T_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nln2h_if.h b/qca-nss-clients/netlink/include/nss_nln2h_if.h
new file mode 100644
index 0000000..2c0580a
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nln2h_if.h
@@ -0,0 +1,32 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nln2h_if.h
+ *      NSS Netlink n2h headers
+ */
+#ifndef __NSS_NLN2H_IF_H
+#define __NSS_NLN2H_IF_H
+
+/**
+ * n2h forwarding Family
+ */
+#define NSS_NLN2H_FAMILY "nss_nln2h"
+#define NSS_NLN2H_MCAST_GRP "nss_nln2h_mc"
+
+#endif /* __NSS_NLN2H_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nloam_if.h b/qca-nss-clients/netlink/include/nss_nloam_if.h
new file mode 100644
index 0000000..317b451
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nloam_if.h
@@ -0,0 +1,157 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nloam_if.h
+ *	NSS Netlink OAM headers
+ */
+
+#ifndef __NSS_NLOAM_IF_H
+#define __NSS_NLOAM_IF_H
+
+/*
+ * OAM Family name
+ *	OAM - Operations, Administration and Maintenance Service
+ *	This netlink family is meant for servicing the request from the OAM proxy.
+ */
+#define NSS_NLOAM_FAMILY "nss_nloam"
+#define NSS_NLOAM_MCAST_GRP "nss_nloam_mc"
+
+#define NSS_NLOAM_ABS_TIME_WIDTH 4	/**< words*/
+#define NSS_NLOAM_BIN_DATA_SZ 256
+#define NSS_NLOAM_RESP_ERR_SZ 512
+
+/*
+ * @brief NSS oam command types
+ *
+ * @note These are the command types from oam proxy to nss oam server via oam adapter
+ */
+enum nss_nloam_cmd {
+	NSS_NLOAM_CMD_NONE = 0,			/**< none */
+	NSS_NLOAM_CMD_SET_REQ = 1,		/**< set request to nss */
+	NSS_NLOAM_CMD_GET_REQ = 2,		/**< get request to nss */
+	NSS_NLOAM_CMD_CLR_REQ = 3,		/**< clr request to nss*/
+	NSS_NLOAM_CMD_MAX,			/**< Max command */
+};
+
+/*
+ * @brief NSS oam command types
+ *
+ * @note These are the sub command types from oam proxy to nss oam server for get command
+ */
+enum nss_nloam_get_type {
+	NSS_NLOAM_GET_TYPE_NONE = 0x0,
+	NSS_NLOAM_GET_TYPE_FW_VERSION = 0x20050001,	/**< sub type get fw version */
+	NSS_NLOAM_GET_TYPE_UNKNOWN = 0xFFFFFFFF,	/**< unknown type (-1) */
+};
+
+/*
+ * @brief NSS oam response types
+ *
+ * @note These are the response types from nss oam server to oam proxy server via oam adapter
+ */
+enum nss_nloam_resp_type {
+	NSS_NLOAM_RESP_TYPE_SET = 1,	/**< resp for set request command */
+	NSS_NLOAM_RESP_TYPE_GET = 2,	/**< resp for get reqest command */
+	NSS_NLOAM_RESP_TYPE_MAX,	/**< max response type */
+};
+
+/*
+ * @brief message format for oam get command type
+ *
+ * @note get message format oam proxy to server as per protocol document
+ */
+struct nss_nloam_get_req {
+	uint16_t trans_id;
+	uint16_t batch_sz;
+
+	uint32_t rec_id;
+
+	uint8_t clear_on_read;
+	uint8_t res;
+};
+
+/*
+ * @brief message format for oam get resp
+ *
+ * @note get message format server to oam proxy as per protocol document
+ */
+struct nss_nloam_get_resp {
+	uint16_t trans_id;
+	uint8_t mgmt_res;
+	uint8_t time_source;
+
+	uint32_t abs_time[NSS_NLOAM_ABS_TIME_WIDTH];
+	uint32_t rec_id;
+	uint32_t error_no;
+
+	uint16_t length;
+	uint8_t res[2];
+
+	uint8_t bin[NSS_NLOAM_BIN_DATA_SZ];
+};
+
+/*
+ * @brief message format for oam set command type
+ *
+ * @note set message format from oam proxy to server as per protocol document
+ */
+struct nss_nloam_set_req {
+	uint16_t trans_id;
+	uint8_t mgmt_op_type;
+	uint8_t reg_dwnld_flag;
+
+	uint32_t rec_id;
+
+	uint16_t length;
+	uint8_t apply_action;
+	uint8_t res;
+
+	uint8_t bin[NSS_NLOAM_BIN_DATA_SZ];
+};
+
+/*
+ * @brief message format for oam set resp
+ *
+ * @note set message format server to oam proxy as per protocol document
+ */
+struct nss_nloam_set_resp {
+	uint16_t trans_id;
+	uint16_t apply_action;
+
+	uint32_t error_no;
+
+	uint16_t length;
+	uint8_t mgmt_res;
+	uint8_t res;
+
+	uint8_t error_msg[NSS_NLOAM_RESP_ERR_SZ];	/**< null terminated string */
+};
+
+/*
+ * @brief oam session info
+ */
+struct nss_nloam_rule {
+	struct nss_nlcmn cm;
+	union {
+		struct nss_nloam_set_req set_req;	/**< set request from oam adapter */
+		struct nss_nloam_set_resp set_resp;	/**< set response to oam adapter */
+		struct nss_nloam_get_req get_req;	/**< get request from oam adapter */
+		struct nss_nloam_get_resp get_resp;	/**< get response to oam adapter */
+	} msg;
+};
+
+#endif /* __NSS_OAM_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nlpppoe_if.h b/qca-nss-clients/netlink/include/nss_nlpppoe_if.h
new file mode 100644
index 0000000..73f6d46
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nlpppoe_if.h
@@ -0,0 +1,32 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nlpppoe_if.h
+ *	NSS Netlink pppoe headers
+ */
+#ifndef __NSS_NLPPPOE_IF_H
+#define __NSS_NLPPPOE_IF_H
+
+/**
+ * pppoe forwarding Family
+ */
+#define NSS_NLPPPOE_FAMILY "nss_nlpppoe"
+#define NSS_NLPPPOE_MCAST_GRP "nss_nlpppoe_mc"
+
+#endif /* __NSS_NLPPPOE_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nlpptp_if.h b/qca-nss-clients/netlink/include/nss_nlpptp_if.h
new file mode 100644
index 0000000..338e676
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nlpptp_if.h
@@ -0,0 +1,32 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nlpptp_if.h
+ *	NSS Netlink pptp headers
+ */
+#ifndef __NSS_NLPPTP_IF_H
+#define __NSS_NLPPTP_IF_H
+
+/**
+ * pptp forwarding Family
+ */
+#define NSS_NLPPTP_FAMILY "nss_nlpptp"
+#define NSS_NLPPTP_MCAST_GRP "nss_nlpptp_mc"
+
+#endif /* __NSS_NLPPTP_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nludp_st_if.h b/qca-nss-clients/netlink/include/nss_nludp_st_if.h
new file mode 100755
index 0000000..ede390d
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nludp_st_if.h
@@ -0,0 +1,85 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nludp_st_if.h
+ *	NSS Netlink udp_st headers
+ */
+#ifndef __NSS_NLUDP_ST_IF_H
+#define __NSS_NLUDP_ST_IF_H
+#include "nss_udp_st.h"
+
+#define NSS_NLUDP_ST_MAX_MTU 65535
+
+/**
+ * UDP speed test forwarding Family
+ */
+#define NSS_NLUDP_ST_FAMILY "nss_nludp_st"
+#define NSS_NLUDP_ST_MCAST_GRP "nss_nludp_st_mc"
+
+/**
+ * UDP speed test rule.
+ */
+struct nss_nludp_st_rule {
+        struct nss_nlcmn cm;				/**< Common message header. */
+	char gmac_ifname[IFNAMSIZ];			/**< GMAC interface name. */
+	struct nss_udp_st_msg num;			/**< UDP ST Rule message. */
+};
+
+/**
+ * nss_nludp_st_rule_init
+ *	NETLINK udp_st message init.
+ *
+ * @param[in] rule NSS Netlink UDP speed test rule.
+ * @param[in] type UDP speed test message type.
+ *
+ * @return
+ * None.
+ */
+static inline void nss_nludp_st_rule_init(struct nss_nludp_st_rule *rule, enum nss_udp_st_message_types type)
+{
+	nss_nlcmn_set_ver(&rule->cm, NSS_NL_VER);
+	nss_nlcmn_init_cmd(&rule->cm, sizeof(struct nss_nludp_st_rule), type);
+}
+
+/**
+ * nss_nludp_st_swap_addr_ipv6
+ *	Converts IPv6 address to NSS format.
+ *
+ * @param[in] rule IPv6 address.
+ *
+ * @return
+ * None.
+ */
+static inline void nss_nludp_st_swap_addr_ipv6(uint32_t *src, uint32_t *dst)
+{
+	uint32_t temp[4];
+
+	if (src == dst) {
+		memcpy(temp, src, sizeof(temp));
+		src = temp;
+	}
+
+	dst[0] = src[3];
+	dst[1] = src[2];
+	dst[2] = src[1];
+	dst[3] = src[0];
+
+}
+
+#endif /* __NSS_NLUDP_ST_IF_H */
diff --git a/qca-nss-clients/netlink/include/nss_nlwifili_if.h b/qca-nss-clients/netlink/include/nss_nlwifili_if.h
new file mode 100644
index 0000000..9ba6688
--- /dev/null
+++ b/qca-nss-clients/netlink/include/nss_nlwifili_if.h
@@ -0,0 +1,32 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_nlwifili_if.h
+ *	NSS Netlink wifili headers
+ */
+#ifndef __NSS_NLWIFILI_IF_H
+#define __NSS_NLWIFILI_IF_H
+
+/**
+ * wifili forwarding Family
+ */
+#define NSS_NLWIFILI_FAMILY "nss_nlwifili"
+#define NSS_NLWIFILI_MCAST_GRP "nss_nlwifili_mc"
+
+#endif /* __NSS_NLWIFILI_IF_H */
diff --git a/qca-nss-clients/netlink/nss_nl.c b/qca-nss-clients/netlink/nss_nl.c
new file mode 100644
index 0000000..4642f8e
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nl.c
@@ -0,0 +1,573 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2016,2018-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/if.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/netlink.h>
+#include <linux/of.h>
+#include <linux/types.h>
+#include <linux/version.h>
+#include <net/genetlink.h>
+
+#include <nss_api_if.h>
+#include <nss_capwap.h>
+#include <nss_capwapmgr.h>
+#include <nss_cmn.h>
+#include <nss_ipsecmgr.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcapwap.h"
+#include "nss_nlcapwap_if.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nldtls.h"
+#include "nss_nldtls_if.h"
+#include "nss_nlgre_redir_if.h"
+#include "nss_nlgre_redir_family.h"
+#include "nss_nlipsec.h"
+#include "nss_nlipsec_if.h"
+#include "nss_nlipv4.h"
+#include "nss_nlipv4_if.h"
+#include "nss_nlipv6.h"
+#include "nss_nlipv6_if.h"
+#include "nss_nloam.h"
+#include "nss_nloam_if.h"
+#include "nss_nlethrx.h"
+#include "nss_nlethrx_if.h"
+#include "nss_nledma.h"
+#include "nss_nledma_if.h"
+#include "nss_nlcapwap.h"
+#include "nss_nlcapwap_if.h"
+#include "nss_nldynamic_interface.h"
+#include "nss_nldynamic_interface_if.h"
+#include "nss_nln2h.h"
+#include "nss_nln2h_if.h"
+#include "nss_nlc2c_tx.h"
+#include "nss_nlc2c_tx_if.h"
+#include "nss_nlc2c_rx.h"
+#include "nss_nlc2c_rx_if.h"
+#include "nss_nlipv4_reasm.h"
+#include "nss_nlipv4_reasm_if.h"
+#include "nss_nlipv6_reasm.h"
+#include "nss_nlipv6_reasm_if.h"
+#include "nss_nlwifili.h"
+#include "nss_nlwifili_if.h"
+#include "nss_nllso_rx.h"
+#include "nss_nllso_rx_if.h"
+#include "nss_nlmap_t.h"
+#include "nss_nlmap_t_if.h"
+#include "nss_nlpppoe.h"
+#include "nss_nlpppoe_if.h"
+#include "nss_nll2tpv2.h"
+#include "nss_nll2tpv2_if.h"
+#include "nss_nlpptp.h"
+#include "nss_nlpptp_if.h"
+#include "nss_nludp_st.h"
+#include "nss_nludp_st_if.h"
+
+/*
+ * nss_nl.c
+ *	NSS Netlink manager
+ */
+
+/*
+ * NSS NL family definition
+ */
+struct nss_nl_family {
+	uint8_t *name;		/* name of the family */
+	nss_nl_fn_t entry;	/* entry function of the family */
+	nss_nl_fn_t exit;	/* exit function of the family */
+	bool valid;		/* valid or invalid */
+};
+
+/*
+ * Family handler table
+ */
+static struct nss_nl_family family_handlers[] = {
+	{
+		/*
+		 * NSS_NLIPV4
+		 */
+		.name = NSS_NLIPV4_FAMILY,		/* ipv4 */
+		.entry = NSS_NLIPV4_INIT,		/* init */
+		.exit = NSS_NLIPV4_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLIPV4		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLIPSEC
+		 */
+		.name = NSS_NLIPSEC_FAMILY,		/* ipsec */
+		.entry = NSS_NLIPSEC_INIT,		/* init */
+		.exit = NSS_NLIPSEC_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLIPSEC		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLOAM
+		 */
+		.name = NSS_NLOAM_FAMILY,		/* oam */
+		.entry = NSS_NLOAM_INIT,		/* init */
+		.exit = NSS_NLOAM_EXIT,			/* exit */
+		.valid = CONFIG_NSS_NLOAM		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLIPV6
+		 */
+		.name = NSS_NLIPV6_FAMILY,		/* ipv6 */
+		.entry = NSS_NLIPV6_INIT,		/* init */
+		.exit = NSS_NLIPV6_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLIPV6		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLGRE_REDIR
+		 */
+		.name = NSS_NLGRE_REDIR_FAMILY,		/* gre_redir */
+		.entry = NSS_NLGRE_REDIR_FAMILY_INIT,	/* init */
+		.exit = NSS_NLGRE_REDIR_FAMILY_EXIT,	/* exit */
+		.valid = CONFIG_NSS_NLGRE_REDIR_FAMILY	/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLCAPWAP
+		 */
+		.name = NSS_NLCAPWAP_FAMILY,		/* capwap */
+		.entry = NSS_NLCAPWAP_INIT,		/* init */
+		.exit = NSS_NLCAPWAP_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLCAPWAP		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLDTLS
+		 */
+		.name = NSS_NLDTLS_FAMILY,		/* dtls */
+		.entry = NSS_NLDTLS_INIT,		/* init */
+		.exit = NSS_NLDTLS_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLDTLS		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLETHRX
+		 */
+		.name = NSS_NLETHRX_FAMILY,		/* ethrx */
+		.entry = NSS_NLETHRX_INIT,		/* init */
+		.exit = NSS_NLETHRX_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLETHRX		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLEDMA
+		 */
+		.name = NSS_NLEDMA_FAMILY,		/* edma */
+		.entry = NSS_NLEDMA_INIT,		/* init */
+		.exit = NSS_NLEDMA_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLEDMA		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLDYNAMIC_INTERFACE
+		 */
+		.name = NSS_NLDYNAMIC_INTERFACE_FAMILY,	/* dynamic interface */
+		.entry = NSS_NLDYNAMIC_INTERFACE_INIT,	/* init */
+		.exit = NSS_NLDYNAMIC_INTERFACE_EXIT,	/* exit */
+		.valid = CONFIG_NSS_NLDYNAMIC_INTERFACE	/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLN2H
+		 */
+		.name = NSS_NLN2H_FAMILY,		/* n2h */
+		.entry = NSS_NLN2H_INIT,		/* init */
+		.exit = NSS_NLN2H_EXIT,			/* exit */
+		.valid = CONFIG_NSS_NLN2H		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLC2C_TX
+		 */
+		.name = NSS_NLC2C_TX_FAMILY,		/* c2c_tx */
+		.entry = NSS_NLC2C_TX_INIT,		/* init */
+		.exit = NSS_NLC2C_TX_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLC2C_TX		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLC2C_RX
+		 */
+		.name = NSS_NLC2C_RX_FAMILY,		/* c2c_rx */
+		.entry = NSS_NLC2C_RX_INIT,		/* init */
+		.exit = NSS_NLC2C_RX_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLC2C_RX		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLIPV4_REASM
+		 */
+		.name = NSS_NLIPV4_REASM_FAMILY,	/* ipv4_reasm */
+		.entry = NSS_NLIPV4_REASM_INIT,		/* init */
+		.exit = NSS_NLIPV4_REASM_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLIPV4_REASM	/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLIPV6_REASM
+		 */
+		.name = NSS_NLIPV6_REASM_FAMILY,	/* ipv6_reasm */
+		.entry = NSS_NLIPV6_REASM_INIT,		/* init */
+		.exit = NSS_NLIPV6_REASM_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLIPV6_REASM	/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLWIFILI
+		 */
+		.name = NSS_NLWIFILI_FAMILY,		/* wifili */
+		.entry = NSS_NLWIFILI_INIT,		/* init */
+		.exit = NSS_NLWIFILI_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLWIFILI		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLLSO_RX
+		 */
+		.name = NSS_NLLSO_RX_FAMILY,		/* lso_rx */
+		.entry = NSS_NLLSO_RX_INIT,		/* init */
+		.exit = NSS_NLLSO_RX_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLLSO_RX		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLMAP_T
+		 */
+		.name = NSS_NLMAP_T_FAMILY,		/* map_t */
+		.entry = NSS_NLMAP_T_INIT,		/* init */
+		.exit = NSS_NLMAP_T_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLMAP_T		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLPPPOE
+		 */
+		.name = NSS_NLPPPOE_FAMILY,		/* pppoe */
+		.entry = NSS_NLPPPOE_INIT,		/* init */
+		.exit = NSS_NLPPPOE_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLPPPOE		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLL2TPV2
+		 */
+		.name = NSS_NLL2TPV2_FAMILY,		/* l2tpv2 */
+		.entry = NSS_NLL2TPV2_INIT,		/* init */
+		.exit = NSS_NLL2TPV2_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLL2TPV2		/* 1 or 0 */
+	},
+	{
+		/*
+		 * NSS_NLPPTP
+		 */
+		.name = NSS_NLPPTP_FAMILY,		/* pptp */
+		.entry = NSS_NLPPTP_INIT,		/* init */
+		.exit = NSS_NLPPTP_EXIT,		/* exit */
+		.valid = CONFIG_NSS_NLPPTP		/* 1 or 0 */
+	},
+	{
+                /*
+                 * NSS_NLUDP_ST
+                 */
+                .name = NSS_NLUDP_ST_FAMILY,             /* udp_st */
+                .entry = NSS_NLUDP_ST_INIT,              /* init */
+                .exit = NSS_NLUDP_ST_EXIT,               /* exit */
+                .valid = CONFIG_NSS_NLUDP_ST             /* 1 or 0 */
+        },
+
+};
+
+#define NSS_NL_FAMILY_HANDLER_SZ ARRAY_SIZE(family_handlers)
+
+/*
+ * nss_nl_alloc_msg()
+ *	allocate NETLINK message
+ *
+ * NOTE: this returns the SKB/message
+ */
+struct sk_buff *nss_nl_new_msg(struct genl_family *family, uint8_t cmd)
+{
+	struct sk_buff *skb;
+	struct nss_nlcmn *cm;
+	int len;
+
+	/*
+	 * aligned length
+	 */
+	len = nla_total_size(family->hdrsize);
+
+	/*
+	 * allocate NL message
+	 */
+	skb = genlmsg_new(len, GFP_ATOMIC);
+	if (!skb) {
+		nss_nl_error("%s: unable to allocate notifier SKB\n", family->name);
+		return NULL;
+	}
+
+	/*
+	 * append the generic message header
+	 */
+	cm = genlmsg_put(skb, 0 /*pid*/, 0 /*seq*/, family, 0 /*flags*/, cmd);
+	if (!cm) {
+		nss_nl_error("%s: no space to put generic header\n", family->name);
+		nlmsg_free(skb);
+		return NULL;
+	}
+
+	/*
+	 * Kernel PID=0
+	 */
+	cm->pid = 0;
+
+	return skb;
+}
+
+/*
+ * nss_nl_copy_msg()
+ *	copy a existing NETLINK message into a new one
+ *
+ * NOTE: this returns the new SKB/message
+ */
+struct sk_buff *nss_nl_copy_msg(struct sk_buff *orig)
+{
+	struct sk_buff *copy;
+	struct nss_nlcmn *cm;
+
+	cm = nss_nl_get_data(orig);
+
+	copy = skb_copy(orig, GFP_KERNEL);
+	if (!copy) {
+		nss_nl_error("%d:unable to copy incoming message of len(%d)\n", cm->pid, orig->len);
+		return NULL;
+	}
+
+	return copy;
+}
+
+/*
+ * nss_nl_get_data()
+ *	Returns start of payload data
+ */
+void  *nss_nl_get_data(struct sk_buff *skb)
+{
+	return genlmsg_data(NLMSG_DATA(skb->data));
+}
+
+/*
+ * nss_nl_mcast_event()
+ *	mcast the event to the user listening on the MCAST group ID
+ *
+ * Note: It will free the message buffer if there is no space left to end
+ */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))
+int nss_nl_mcast_event(struct genl_family *family, struct sk_buff *skb)
+{
+	struct nss_nlcmn *cm;
+
+	cm = genlmsg_data(NLMSG_DATA(skb->data));
+
+	/*
+	 * End the message as no more updates are left to happen.
+	 * After this, the message is assunmed to be read-only
+	 */
+	genlmsg_end(skb, cm);
+
+	return genlmsg_multicast(family, skb, cm->pid, 0, GFP_ATOMIC);
+}
+#else
+int nss_nl_mcast_event(struct genl_multicast_group *grp, struct sk_buff *skb)
+{
+	struct nss_nlcmn *cm;
+
+	cm = genlmsg_data(NLMSG_DATA(skb->data));
+
+	/*
+	 * End the message as no more updates are left to happen.
+	 * After this, the message is assunmed to be read-only
+	 */
+	genlmsg_end(skb, cm);
+
+	return genlmsg_multicast(skb, cm->pid, grp->id, GFP_ATOMIC);
+}
+#endif
+
+/*
+ * nss_nl_ucast_resp()
+ *	send the response to the user (PID)
+ *
+ * NOTE: this assumes the socket to be available for reception
+ */
+int nss_nl_ucast_resp(struct sk_buff *skb)
+{
+	struct nss_nlcmn *cm;
+	struct net *net;
+
+	cm = genlmsg_data(NLMSG_DATA(skb->data));
+
+	net = (struct net *)cm->sock_data;
+	cm->sock_data = 0;
+
+	/*
+	 * End the message as no more updates are left to happen
+	 * After this message is assumed to be read-only
+	 */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
+	genlmsg_end(skb, cm);
+#else
+	if (genlmsg_end(skb, cm) < 0) {
+		nss_nl_error("%d: unable to close generic ucast message\n", cm->pid);
+		nlmsg_free(skb);
+		return -ENOMEM;
+	}
+#endif
+
+	return genlmsg_unicast(net, skb, cm->pid);
+}
+
+/*
+ * nss_nl_get_msg()
+ *	verifies and returns the message pointer
+ */
+struct nss_nlcmn *nss_nl_get_msg(struct genl_family *family, struct genl_info *info, uint16_t cmd)
+{
+	struct nss_nlcmn *cm;
+	uint32_t pid;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
+	pid =  info->snd_pid;
+#else
+	pid =  info->snd_portid;
+#endif
+	/*
+	 * validate the common message header version & magic
+	 */
+	cm = info->userhdr;
+	if (nss_nlcmn_chk_ver(cm, family->version) == false) {
+		nss_nl_error("%d, %s: version mismatch (%d)\n", pid, family->name, cm->version);
+		return NULL;
+	}
+
+	/*
+	 * check if the message len arrived matches with expected len
+	 */
+	if (nss_nlcmn_get_len(cm) != family->hdrsize) {
+		nss_nl_error("%d, %s: invalid command len (%d)\n", pid, family->name, nss_nlcmn_get_len(cm));
+		return NULL;
+	}
+
+	cm->pid = pid;
+	cm->sock_data = (nss_ptr_t)genl_info_net(info);
+
+	return cm;
+}
+
+/*
+ * nss_nl_init()
+ *	init module
+ */
+static int __init nss_nl_init(void)
+{
+	struct nss_nl_family *family = NULL;
+	int i = 0;
+
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+	nss_nl_info_always("NSS Netlink manager loaded: %s\n", NSS_CLIENT_BUILD_ID);
+
+	/*
+	 * initialize the handler families, the intention to init the
+	 * families that are marked active
+	 */
+	family = &family_handlers[0];
+
+	for (i = 0; i < NSS_NL_FAMILY_HANDLER_SZ; i++, family++) {
+		/*
+		 * Check if the family exists
+		 */
+		if (!family->valid || !family->entry) {
+			nss_nl_info_always("skipping family:%s\n", family->name);
+			nss_nl_info_always("valid = %d, entry = %d\n", family->valid, !!family->entry);
+			continue;
+		}
+
+		nss_nl_info_always("attaching family:%s\n", family->name);
+
+		family->entry();
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nl_exit()
+ *	deinit module
+ */
+static void __exit nss_nl_exit(void)
+{
+	struct nss_nl_family *family = NULL;
+	int i = 0;
+
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return;
+	}
+#endif
+	nss_nl_info_always("NSS Netlink manager unloaded\n");
+
+	/*
+	 * initialize the handler families
+	 */
+	family = &family_handlers[0];
+
+	for (i = 0; i < NSS_NL_FAMILY_HANDLER_SZ; i++, family++) {
+		/*
+		 * Check if the family exists
+		 */
+		if (!family->valid || !family->exit) {
+			nss_nl_info_always("skipping family:%s\n", family->name);
+			nss_nl_info_always("valid = %d, exit = %d\n", family->valid, !!family->exit);
+			continue;
+		}
+
+		nss_nl_info_always("detaching family:%s\n", family->name);
+
+		family->exit();
+	}
+}
+
+module_init(nss_nl_init);
+module_exit(nss_nl_exit);
+
+MODULE_DESCRIPTION("NSS NETLINK");
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/qca-nss-clients/netlink/nss_nl.h b/qca-nss-clients/netlink/nss_nl.h
new file mode 100644
index 0000000..95300ce
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nl.h
@@ -0,0 +1,135 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015,2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nl.h
+ *	NSS Netlink internal definitions
+ */
+#ifndef __NSS_NL_H
+#define __NSS_NL_H
+
+#define NSS_NL_DEBUG_LVL_ERROR 1
+#define NSS_NL_DEBUG_LVL_WARN 2
+#define NSS_NL_DEBUG_LVL_INFO 3
+#define NSS_NL_DEBUG_LVL_TRACE 4
+
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_nl_error(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_nl_warn(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_nl_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_nl_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_nl_hex_dump_bytes(prefix_str, prefix_type, buf, len)	\
+	dynamic_hex_dump(prefix_str, prefix_type, 16, 1, buf, len, true)
+#else
+/*
+ * Statically compile messages at different levels
+ */
+#define nss_nl_error(s, ...) {	\
+	if (NSS_NL_DEBUG_LEVEL > NSS_NL_DEBUG_LVL_ERROR) {	\
+		pr_alert("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+#define nss_nl_warn(s, ...) {	\
+	if (NSS_NL_DEBUG_LEVEL > NSS_NL_DEBUG_LVL_WARN) {	\
+		pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+#define nss_nl_info(s, ...) {	\
+	if (NSS_NL_DEBUG_LEVEL > NSS_NL_DEBUG_LVL_INFO) {	\
+		pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+#define nss_nl_hex_dump_bytes(prefix_str, prefix_type, buf, len) {	\
+	if (NSS_NL_DEBUG_LEVEL > NSS_NL_DEBUG_LVL_INFO) {	\
+		print_hex_dump_bytes(prefix_str, prefix_type, buf, len);	\
+	}	\
+}
+#define nss_nl_trace(s, ...) {	\
+	if (NSS_NL_DEBUG_LEVEL > NSS_NL_DEBUG_LVL_TRACE) {	\
+		pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+}
+#endif /* !CONFIG_DYNAMIC_DEBUG */
+
+/*
+ * debug message for module init and exit
+ */
+#define nss_nl_info_always(s, ...) printk(KERN_INFO"%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+
+#define NSS_NETLINK_INIT_FAMILY(family, pre_fn, post_fn) {	\
+	.id = GENL_ID_GENERATE,	\
+	.name = NSS_NETLINK_##family##FAMILY,	\
+	.hdrsize = 0,	\
+	.version = NSS_NETLINK_VER,	\
+	.maxattr = NSS_NETLINK_##family##_CMD_MAX,	\
+	.netnsok = true,	\
+	.pre_doit = pre_fn,	\
+	.post_doit = post_fn,	\
+}
+
+#define NSS_NETLINK_INIT_POLICY(cmd, ds) {	\
+	.type = NLA_BINARY,	\
+	.len = sizeof(struct ##ds),	\
+}
+
+
+typedef bool (*nss_nl_fn_t)(void);
+
+/*
+ * *************
+ * Generic API(s)
+ * *************
+ */
+
+/*
+ * Allocate NSS NL message buffer, this returns the message SKB and start of the payload pointer
+ */
+struct sk_buff *nss_nl_new_msg(struct genl_family *family, uint8_t cmd);
+
+/*
+ * Copy NSS NL message buffer into a new SKB
+ */
+struct sk_buff *nss_nl_copy_msg(struct sk_buff *orig);
+
+/*
+ * Get NSS NL message pointer for a given command
+ */
+struct nss_nlcmn *nss_nl_get_msg(struct genl_family *family, struct genl_info *info, uint16_t cmd);
+
+/*
+ * returns the start of NSS_NL payload
+ */
+void *nss_nl_get_data(struct sk_buff *skb);
+
+/*
+ * unicast response to the user
+ */
+int nss_nl_ucast_resp(struct sk_buff *skb);
+
+/*
+ * multicast response to the user
+ */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
+int nss_nl_mcast_event(struct genl_family *family, struct sk_buff *skb);
+#else
+int nss_nl_mcast_event(struct genl_multicast_group *grp, struct sk_buff *skb);
+#endif
+#endif /* __NSS_NL_H */
diff --git a/qca-nss-clients/netlink/nss_nlc2c_rx.c b/qca-nss-clients/netlink/nss_nlc2c_rx.c
new file mode 100644
index 0000000..ab1fc89
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlc2c_rx.c
@@ -0,0 +1,178 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlc2c_rx.c
+ *	NSS Netlink c2c_rx Handler
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/notifier.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nlc2c_rx_if.h"
+#include "nss_c2c_rx.h"
+
+/*
+ * prototypes
+ */
+static int nss_nlc2c_rx_ops_get_stats(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlc2c_rx_process_notify(struct notifier_block *nb,  unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nlc2c_rx_mcgrp[] = {
+	{.name = NSS_NLC2C_RX_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nlc2c_rx_ops[] = {
+	{.cmd = NSS_STATS_EVENT_NOTIFY, .doit = nss_nlc2c_rx_ops_get_stats},
+};
+
+/*
+ * c2c_rx family definition
+ */
+static struct genl_family nss_nlc2c_rx_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,						/* Auto generate ID */
+#endif
+	.name = NSS_NLC2C_RX_FAMILY,					/* family name string */
+	.hdrsize = sizeof(struct nss_c2c_rx_stats_notification),	/* NSS NETLINK c2c_rx stats */
+	.version = NSS_NL_VER,						/* Set it to NSS_NLC2C_RX version */
+	.maxattr = NSS_STATS_EVENT_MAX,					/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nlc2c_rx_ops,
+	.n_ops = ARRAY_SIZE(nss_nlc2c_rx_ops),
+	.mcgrps = nss_nlc2c_rx_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nlc2c_rx_mcgrp)
+};
+
+/*
+ * stats call back handler for c2c_rx from NSS
+ */
+static struct notifier_block nss_c2c_rx_stats_notifier_nb = {
+	.notifier_call = nss_nlc2c_rx_process_notify,
+};
+
+/*
+ * nss_nlc2c_rx_ops_get_stats()
+ *	get stats handler
+ */
+static int nss_nlc2c_rx_ops_get_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+/*
+ * nss_nlc2c_rx_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nlc2c_rx_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct sk_buff *skb;
+	struct nss_c2c_rx_stats_notification *nss_stats, *nl_stats;
+
+	skb = nss_nl_new_msg(&nss_nlc2c_rx_family, NSS_NLCMN_SUBSYS_C2C_RX);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLC2C_RX event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_stats = nss_nl_get_data(skb);
+	nss_stats = (struct nss_c2c_rx_stats_notification *)data;
+	memcpy(nl_stats, nss_stats, sizeof(struct nss_c2c_rx_stats_notification));
+	nss_nl_mcast_event(&nss_nlc2c_rx_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nlc2c_rx_init()
+ *	handler init
+ */
+bool nss_nlc2c_rx_init(void)
+{
+	int error,ret;
+
+	nss_nl_info_always("Init NSS netlink c2c_rx handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nlc2c_rx_family);
+	if (error) {
+		nss_nl_info_always("Error: unable to register c2c_rx family\n");
+		return false;
+	}
+
+	/*
+	 * register device call back handler for c2c_rx from NSS
+	 */
+	ret = nss_c2c_rx_stats_register_notifier(&nss_c2c_rx_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context \n");
+		genl_unregister_family(&nss_nlc2c_rx_family);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nlc2c_rx_exit()
+ *	handler exit
+ */
+bool nss_nlc2c_rx_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink c2c_rx handler\n");
+
+	/*
+	 * Unregister the device callback handler for c2c_rx
+	 */
+	nss_c2c_rx_stats_unregister_notifier(&nss_c2c_rx_stats_notifier_nb);
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nlc2c_rx_family);
+	if (error) {
+		nss_nl_info_always("unable to unregister c2c_rx NETLINK family\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nlc2c_rx.h b/qca-nss-clients/netlink/nss_nlc2c_rx.h
new file mode 100644
index 0000000..0d16921
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlc2c_rx.h
@@ -0,0 +1,37 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlc2c_rx.h
+ *	NSS Netlink c2c_rx API definitions
+ */
+#ifndef __NSS_NLC2C_RX_H
+#define __NSS_NLC2C_RX_H
+
+#if (CONFIG_NSS_NLC2C_RX == 1)
+bool nss_nlc2c_rx_init(void);
+bool nss_nlc2c_rx_exit(void);
+
+#define NSS_NLC2C_RX_INIT nss_nlc2c_rx_init
+#define NSS_NLC2C_RX_EXIT nss_nlc2c_rx_exit
+#else
+#define NSS_NLC2C_RX_INIT 0
+#define NSS_NLC2C_RX_EXIT 0
+#endif /* !CONFIG_NSS_NLC2C_RX */
+
+#endif /* __NSS_NLC2C_RX_H */
diff --git a/qca-nss-clients/netlink/nss_nlc2c_tx.c b/qca-nss-clients/netlink/nss_nlc2c_tx.c
new file mode 100644
index 0000000..ebc0265
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlc2c_tx.c
@@ -0,0 +1,178 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlc2c_tx.c
+ *	NSS Netlink c2c_tx Handler
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/notifier.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nlc2c_tx_if.h"
+#include "nss_c2c_tx.h"
+
+/*
+ * prototypes
+ */
+static int nss_nlc2c_tx_ops_get_stats(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlc2c_tx_process_notify(struct notifier_block *nb,  unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nlc2c_tx_mcgrp[] = {
+	{.name = NSS_NLC2C_TX_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nlc2c_tx_ops[] = {
+	{.cmd = NSS_STATS_EVENT_NOTIFY, .doit = nss_nlc2c_tx_ops_get_stats},
+};
+
+/*
+ * c2c_tx family definition
+ */
+static struct genl_family nss_nlc2c_tx_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,						/* Auto generate ID */
+#endif
+	.name = NSS_NLC2C_TX_FAMILY,					/* family name string */
+	.hdrsize = sizeof(struct nss_c2c_tx_stats_notification),	/* NSS NETLINK c2c_tx stats */
+	.version = NSS_NL_VER,						/* Set it to NSS_NLC2C_TX version */
+	.maxattr = NSS_STATS_EVENT_MAX,					/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nlc2c_tx_ops,
+	.n_ops = ARRAY_SIZE(nss_nlc2c_tx_ops),
+	.mcgrps = nss_nlc2c_tx_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nlc2c_tx_mcgrp)
+};
+
+/*
+ * stats call back handler for c2c_tx from NSS
+ */
+static struct notifier_block nss_c2c_tx_stats_notifier_nb = {
+	.notifier_call = nss_nlc2c_tx_process_notify,
+};
+
+/*
+ * nss_nlc2c_tx_ops_get_stats()
+ *	get stats handler
+ */
+static int nss_nlc2c_tx_ops_get_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+/*
+ * nss_nlc2c_tx_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nlc2c_tx_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct sk_buff *skb;
+	struct nss_c2c_tx_stats_notification *nss_stats, *nl_stats;
+
+	skb = nss_nl_new_msg(&nss_nlc2c_tx_family, NSS_NLCMN_SUBSYS_C2C_TX);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLC2C_TX event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_stats = nss_nl_get_data(skb);
+	nss_stats = (struct nss_c2c_tx_stats_notification *)data;
+	memcpy(nl_stats, nss_stats, sizeof(struct nss_c2c_tx_stats_notification));
+	nss_nl_mcast_event(&nss_nlc2c_tx_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nlc2c_tx_init()
+ *	handler init
+ */
+bool nss_nlc2c_tx_init(void)
+{
+	int error,ret;
+
+	nss_nl_info_always("Init NSS netlink c2c_tx handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nlc2c_tx_family);
+	if (error) {
+		nss_nl_info_always("Error: unable to register c2c_tx family\n");
+		return false;
+	}
+
+	/*
+	 * register device call back handler for c2c_tx from NSS
+	 */
+	ret = nss_c2c_tx_stats_register_notifier(&nss_c2c_tx_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context \n");
+		genl_unregister_family(&nss_nlc2c_tx_family);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nlc2c_tx_exit()
+ *	handler exit
+ */
+bool nss_nlc2c_tx_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink c2c_tx handler\n");
+
+	/*
+	 * Unregister the device callback handler for c2c_tx
+	 */
+	nss_c2c_tx_stats_unregister_notifier(&nss_c2c_tx_stats_notifier_nb);
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nlc2c_tx_family);
+	if (error) {
+		nss_nl_info_always("unable to unregister c2c_tx NETLINK family\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nlc2c_tx.h b/qca-nss-clients/netlink/nss_nlc2c_tx.h
new file mode 100644
index 0000000..cfb6da8
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlc2c_tx.h
@@ -0,0 +1,37 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlc2c_tx.h
+ *	NSS Netlink c2c_tx API definitions
+ */
+#ifndef __NSS_NLC2C_TX_H
+#define __NSS_NLC2C_TX_H
+
+#if (CONFIG_NSS_NLC2C_TX == 1)
+bool nss_nlc2c_tx_init(void);
+bool nss_nlc2c_tx_exit(void);
+
+#define NSS_NLC2C_TX_INIT nss_nlc2c_tx_init
+#define NSS_NLC2C_TX_EXIT nss_nlc2c_tx_exit
+#else
+#define NSS_NLC2C_TX_INIT 0
+#define NSS_NLC2C_TX_EXIT 0
+#endif /* !CONFIG_NSS_NLC2C_TX */
+
+#endif /* __NSS_NLC2C_TX_H */
diff --git a/qca-nss-clients/netlink/nss_nlcapwap.c b/qca-nss-clients/netlink/nss_nlcapwap.c
new file mode 100644
index 0000000..bc7466c
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlcapwap.c
@@ -0,0 +1,1636 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2016,2018-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/debugfs.h>
+#include <linux/if.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/netlink.h>
+#include <linux/types.h>
+#include <linux/version.h>
+#include <linux/workqueue.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_capwap.h>
+#include <nss_capwapmgr.h>
+#include <nss_capwap_user.h>
+#include <nss_cmn.h>
+#include <nss_dtlsmgr.h>
+#include <nss_dtls_cmn.h>
+#include <nss_nlcmn_if.h>
+#include <nss_nl_if.h>
+#include "nss_crypto_defines.h"
+#include "nss_nl.h"
+#include "nss_nlcapwap_if.h"
+#include "nss_nlcapwap.h"
+#include "nss_nlcmn_if.h"
+
+/*
+ * nss_nlcapwap_tunnel_stats
+ *	Keeps track of the netlink capwap stats
+ */
+struct nss_nlcapwap_tunnel_stats {
+	uint32_t ka_seq_fail;
+	uint32_t tx_data_pkts;
+	uint32_t rx_data_pkts;
+	uint32_t tx_ka_pkts;
+	uint32_t rx_ka_pkts;
+};
+
+/*
+ * nss_nlcapwap_tunnel_keepalive
+ *	Parameters needed for keepalive execution
+ */
+struct nss_nlcapwap_tunnel_keepalive {
+	struct delayed_work work;
+	uint32_t tx_seq;
+	uint32_t rx_seq;
+	uint16_t tun_id;
+	atomic_t status;
+};
+
+/*
+ * nss_nlcapwap_tunnel
+ *	Stores the per tunnel data
+ */
+struct nss_nlcapwap_tunnel {
+	struct nss_nlcapwap_tunnel_keepalive kalive;	/* Keepalive parameters */
+	struct nss_nlcapwap_tunnel_stats stats;		/* Per tunnel netlink level stats */
+	struct nss_nlcapwap_meta_header mh;		/* Stores meta header of tunnel */
+};
+
+/*
+ * nss_nlcapwap_global_ctx
+ *	Global context for capwap
+ */
+struct nss_nlcapwap_global_ctx {
+	struct nss_nlcapwap_tunnel tun[NSS_CAPWAPMGR_MAX_TUNNELS];	/* Keepalive params per tunnel */
+	unsigned long tun_bitmap[NSS_NLCAPWAP_MAX_TUNNEL_LONGS];	/* Bitmap to keep track of tunnel status */
+	struct net_device *capwap_dev;	/* CAPWAP global device */
+	struct dentry *dentry;		/* Debug entry to maintain netlink stats */
+	atomic_t enable_perf;		/* Atomic variable to enable and disable perf */
+	rwlock_t lock;			/* Lock variable for synchronization */
+};
+
+/*
+ * nss_nlcapwap_app_hdr
+ *	Custom header needed by sender and receiver
+ */
+struct nss_nlcapwap_app_hdr {
+	uint32_t seq_num;		/* Seq number associated with packet */
+	uint16_t tun_id;		/* Tunnel used for transmission */
+	uint8_t res[2];			/* Reserved for padding */
+};
+
+/*
+ * nss_nlcapwap_hdr
+ *	capwap header used for dtls_keepalive packets
+ */
+struct nss_nlcapwap_hdr {
+	uint8_t preamble;	/* 0=CAPWAP header, 1=CAPWAP DTLS header */
+
+	/*
+	 * 1-byte
+	 */
+	uint8_t rid1:3;
+
+	/*
+	 * rid1: 3 bits of a 5-bit field that contains the Radio ID number for
+	 * this packet, whose value is between one (1) and 31. Given
+	 * that MAC Addresses are not necessarily unique across physical
+	 * radios in a WTP, the Radio Identifier (RID) field is used to
+	 * indicate with which physical radio the message is associated.
+	 */
+	uint8_t hlen:5;
+	/*
+	 * hlen: A 5-bit field containing the length of the CAPWAP transport
+	 * header in 4-byte words (similar to IP header length). This
+	 * length includes the optional headers.
+	 */
+
+	/*
+	 * 1-byte
+	 */
+	uint8_t T:1;		/* Type (1=802.11, 0=Other) */
+	uint8_t wbid:5;
+	/*
+	 * wbid: A 5-bit field that is the wireless binding identifier. The
+	 * identifier will indicate the type of wireless packet associated
+	 * with the radio. The following values are defined:
+	 * 0 - Reserved 1 - IEEE 802.11 2 - Reserved 3 - EPCGlobal [EPCGlobal]
+	 */
+
+	uint8_t rid2:2;		/* 2-bits of radio id -- look at rid1 */
+
+	/*
+	 * 1-byte
+	 */
+	uint8_t flags:3;	/* Not Used */
+	uint8_t K:1;		/* 1=KeepAlive packet 0=Not keepalive packet */
+	uint8_t M:1;		/* 1=MAC address is present, 0=not present */
+	uint8_t W:1;		/* 1=wireless info present, 0=not present */
+	uint8_t L:1;		/* 1=Last fragment, 0=Not the last fragment */
+	uint8_t F:1;		/* 1=Fragmented, 0=Not fragmented */
+
+	uint16_t frag_id;	/* Fragment ID */
+	uint16_t frag_off;	/* 13-bit Offset of the fragment in 8 byte words */
+				/* lower 3 bits are reserved & must be set to 0 */
+} __attribute__((packed));
+
+/*
+ * Global capwap context variable
+ */
+static struct nss_nlcapwap_global_ctx global_ctx;
+
+static int nss_nlcapwap_ops_create_tun(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlcapwap_ops_destroy_tun(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlcapwap_ops_update_mtu(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlcapwap_ops_dtls(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlcapwap_ops_perf(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlcapwap_ops_tx_packets(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlcapwap_ops_meta_header(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlcapwap_ops_ip_flow(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlcapwap_ops_keepalive(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlcapwap_ops_get_stats(struct sk_buff *skb, struct genl_info *info);
+
+/*
+ * nss_nlcapwap_family_mcgrp
+ *	Multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nlcapwap_family_mcgrp[] = {
+	{.name = NSS_NLCAPWAP_MCAST_GRP},
+};
+
+/*
+ * nss_nlcapwap_cmd_ops
+ *	Operation table called by the generic netlink layer based on the command
+ */
+struct genl_ops nss_nlcapwap_cmd_ops[] = {
+	{.cmd = NSS_NLCAPWAP_CMD_TYPE_CREATE_TUN, .doit = nss_nlcapwap_ops_create_tun,},
+	{.cmd = NSS_NLCAPWAP_CMD_TYPE_DESTROY_TUN, .doit = nss_nlcapwap_ops_destroy_tun,},
+	{.cmd = NSS_NLCAPWAP_CMD_TYPE_UPDATE_MTU, .doit = nss_nlcapwap_ops_update_mtu,},
+	{.cmd = NSS_NLCAPWAP_CMD_TYPE_DTLS, .doit = nss_nlcapwap_ops_dtls,},
+	{.cmd = NSS_NLCAPWAP_CMD_TYPE_PERF, .doit = nss_nlcapwap_ops_perf,},
+	{.cmd = NSS_NLCAPWAP_CMD_TYPE_TX_PACKETS, .doit = nss_nlcapwap_ops_tx_packets,},
+	{.cmd = NSS_NLCAPWAP_CMD_TYPE_META_HEADER, .doit = nss_nlcapwap_ops_meta_header,},
+	{.cmd = NSS_NLCAPWAP_CMD_TYPE_IP_FLOW, .doit = nss_nlcapwap_ops_ip_flow,},
+	{.cmd = NSS_NLCAPWAP_CMD_TYPE_KEEPALIVE, .doit = nss_nlcapwap_ops_keepalive,},
+	{.cmd = NSS_STATS_EVENT_NOTIFY, .doit = nss_nlcapwap_ops_get_stats,},
+};
+
+/*
+ * nss_nlcapwap_family
+ *	Capwap family definition
+ */
+struct genl_family nss_nlcapwap_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,				/* Auto generate ID */
+#endif
+	.name = NSS_NLCAPWAP_FAMILY,			/* family name string */
+	.hdrsize = sizeof(struct nss_nlcapwap_rule),	/* NSS NETLINK capwap rule */
+	.version = NSS_NL_VER,				/* Set it to NSS_NL_VER version */
+	.maxattr = NSS_NLCAPWAP_CMD_TYPE_MAX,		/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nlcapwap_cmd_ops,
+	.n_ops = ARRAY_SIZE(nss_nlcapwap_cmd_ops),
+	.mcgrps = nss_nlcapwap_family_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nlcapwap_family_mcgrp)
+};
+
+/*
+ * nss_nlcapwap_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nlcapwap_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct sk_buff *skb;
+	struct nss_capwap_stats_notification *nss_stats, *nl_stats;
+
+	nss_stats = (struct nss_capwap_stats_notification *)data;
+	skb = nss_nl_new_msg(&nss_nlcapwap_family, NSS_NLCMN_SUBSYS_CAPWAP);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLCAPWAP event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_stats = nss_nl_get_data(skb);
+	memcpy(nl_stats, nss_stats, sizeof(struct nss_capwap_stats_notification));
+	nss_nl_mcast_event(&nss_nlcapwap_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * device call back handler for capwap from NSS
+ */
+static struct notifier_block nss_capwap_stats_notifier_nb = {
+	.notifier_call = nss_nlcapwap_process_notify,
+};
+
+/*
+ * nss_nlcapwap_get_tun_by_index()
+ *	Returns the tunnel context based on index passed
+ */
+static struct nss_nlcapwap_tunnel *nss_nlcapwap_get_tun_by_index(int idx)
+{
+	if (idx >= NSS_CAPWAPMGR_MAX_TUNNELS) {
+		nss_nl_error("Index value out of bound: %d\n", idx);
+		return NULL;
+	}
+
+	return test_bit(idx, global_ctx.tun_bitmap) ? &global_ctx.tun[idx] : NULL;
+}
+
+/*
+ * nss_nlcapwap_rx_handler()
+ *	Capwap netdev rx handler
+ */
+static rx_handler_result_t nss_nlcapwapmgr_rx_handler(struct sk_buff **pskb)
+{
+	struct nss_capwap_metaheader *mh;
+	struct nss_nlcapwap_tunnel *tun;
+	struct sk_buff *skb = *pskb;
+	uint32_t matched = 0;
+	uint8_t *data;
+	int len;
+	int i;
+
+	len = skb->len;
+	mh = (struct nss_capwap_metaheader *)skb->data;
+
+	/*
+	 * We need to pull the meta header for the payload start
+	 */
+	if (!atomic_read(&global_ctx.enable_perf)) {
+		data = skb_pull(skb, sizeof(*mh) + sizeof(struct ethhdr));
+		/*
+		 * Test bytes with known pattern
+		 */
+		for (i = 0; i < skb->len; i++, data++) {
+			matched += (*data == NSS_NLCAPWAP_DATA);
+		}
+	}
+
+	nss_nl_info("RX packet for tun(%d), len(%d) matched(%d)\n", mh->tunnel_id, len, matched);
+
+	write_lock_bh(&global_ctx.lock);
+	tun = nss_nlcapwap_get_tun_by_index(mh->tunnel_id);
+	if (!tun) {
+		nss_nl_error("%px: Could not find tunnel associated with index: %d\n", skb, mh->tunnel_id);
+		write_unlock_bh(&global_ctx.lock);
+		goto free;
+	}
+
+	tun->stats.rx_data_pkts++;
+	write_unlock_bh(&global_ctx.lock);
+
+free:
+	dev_kfree_skb_any(skb);
+	return RX_HANDLER_CONSUMED;
+}
+
+/*
+ * nss_nlcapwap_tx_keepalive()
+ *	Handler for sending capwap keepalive frames
+ */
+static int nss_nlcapwap_tx_keepalive(struct nss_nlcapwap_tunnel_keepalive *kp)
+{
+	struct nss_nlcapwap_app_hdr *apph;
+	struct nss_nlcapwap_tunnel *tun;
+	struct net_device *capwap_dev;
+	struct net_device *dtls_dev;
+	struct nss_nlcapwap_hdr *ch;
+	struct sk_buff *skb;
+	size_t align_offset;
+	size_t skb_sz;
+
+	/*
+	 * Check if dtls is enabled for the tunnel
+	 */
+	dtls_dev = nss_capwapmgr_get_dtls_netdev(global_ctx.capwap_dev, kp->tun_id);
+	if (!dtls_dev) {
+		nss_nl_error("%px: DTLS net_device not found for capwap_dev(%s)\n", &kp, capwap_dev->name);
+		return -ENODEV;
+	}
+
+	/*
+	 * Allocate a new skb
+	 */
+	skb_sz = NSS_NLCAPWAP_MAX_HEADROOM + NSS_NLCAPWAP_KALIVE_PAYLOAD_SZ + NSS_NLCAPWAP_MAX_TAILROOM;
+	skb_sz += SMP_CACHE_BYTES;
+
+	skb = dev_alloc_skb(skb_sz);
+	if (!skb) {
+		nss_nl_error("%px: Could not allocate a skb of size(%zu)\n", kp, skb_sz);
+		dev_put(dtls_dev);
+		return -ENOMEM;
+	}
+
+	align_offset = PTR_ALIGN(skb->data, SMP_CACHE_BYTES) - skb->data;
+	skb_reserve(skb, NSS_NLCAPWAP_MAX_HEADROOM + align_offset);
+
+	/*
+	 * Set the queue mapping to highest priority queue
+	 */
+	skb_set_queue_mapping(skb, 1);
+
+	/*
+	 * Initialize the capwap header with zero
+	 */
+	ch = (struct nss_nlcapwap_hdr *)skb_put(skb, sizeof(*ch));
+	memset(ch, 0, sizeof(*ch));
+
+	/*
+	 * Set the keepalive timer bit
+	 */
+	ch->K = 1;
+
+	/*
+	 * Fill the packet data with msg_type and tun_id
+	 */
+	apph = (struct nss_nlcapwap_app_hdr *)skb_put(skb, sizeof(*apph));
+
+	write_lock_bh(&global_ctx.lock);
+	tun = nss_nlcapwap_get_tun_by_index(kp->tun_id);
+	if (!tun) {
+		write_unlock_bh(&global_ctx.lock);
+		nss_nl_error("%px: Could not find tunnel associated with index: %d\n", kp, kp->tun_id);
+		return -ENODEV;
+	}
+
+	apph->tun_id = kp->tun_id;
+	apph->seq_num = kp->tx_seq;
+
+	kp->tx_seq++;
+	tun->stats.tx_ka_pkts++;
+	write_unlock_bh(&global_ctx.lock);
+
+	BUG_ON(!IS_ALIGNED((unsigned long)skb->data, sizeof(uint32_t)));
+
+	if (dtls_dev->netdev_ops->ndo_start_xmit(skb, dtls_dev) != NETDEV_TX_OK) {
+		dev_kfree_skb_any(skb);
+		return -EBUSY;
+	}
+
+	nss_nl_info("%px: Keepalive packet sent\n", dtls_dev);
+	dev_put(dtls_dev);
+	return 0;
+}
+
+/*
+ * nss_nlcapwap_keepalive()
+ *	Sends keepalive packet at regular interval
+ */
+static void nss_nlcapwap_keepalive(struct work_struct *work)
+{
+	struct delayed_work *dwork = (struct delayed_work *)work;
+	struct nss_nlcapwap_tunnel_keepalive *kp = container_of(dwork, struct nss_nlcapwap_tunnel_keepalive, work);
+
+	nss_nlcapwap_tx_keepalive(kp);
+	if (atomic_read(&kp->status)) {
+		   schedule_delayed_work(dwork, NSS_NLCAPWAP_KALIVE_TIMER_MSECS);
+	}
+}
+
+/*
+ * nss_nlcapwap_tun_init()
+ *	Initialize the tunnel
+ */
+static void nss_nlcapwap_tun_init(struct nss_nlcapwap_tunnel *tun, uint16_t tun_id)
+{
+	memset(tun, 0, sizeof(*tun));
+	tun->kalive.tun_id = tun_id;
+	INIT_DELAYED_WORK(&tun->kalive.work, nss_nlcapwap_keepalive);
+}
+
+/*
+ * nss_nlcapwap_tun_deinit()
+ *	Deinitializes the tunnel
+ */
+static void nss_nlcapwap_tun_deinit(struct nss_nlcapwap_tunnel *tun)
+{
+	/*
+	 * Flush the delayed work if its enabled for the tunnel
+	 */
+	if (!atomic_read(&tun->kalive.status)) {
+		return;
+	}
+
+	/*
+	 * De-initialize the keepalive context for tun_id
+	 */
+	atomic_set(&tun->kalive.status, 0);
+	cancel_delayed_work(&tun->kalive.work);
+}
+
+/*
+ * nss_nlcapwap_destroy_tun()
+ *	Destroys tunnel based on tun_id
+ */
+static int nss_nlcapwap_destroy_tun(uint16_t tun_id)
+{
+	struct net_device *capwap_dev;
+	nss_capwapmgr_status_t status;
+
+	/*
+	 * Get the capwap netdev reference
+	 */
+	capwap_dev = global_ctx.capwap_dev;
+	if (!capwap_dev) {
+		nss_nl_error("CAPWAP net_device not found\n");
+		return -ENODEV;
+	}
+
+	status = nss_capwapmgr_disable_tunnel(capwap_dev, tun_id);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_nl_error("Unable to disable the tunnel: %d\n", tun_id);
+		return -EAGAIN;
+	}
+
+	status = nss_capwapmgr_tunnel_destroy(capwap_dev, tun_id);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_nl_error("Unable to destroy the tunnel: %d\n", tun_id);
+		nss_capwapmgr_enable_tunnel(capwap_dev, tun_id);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nlcapwap_data_cb()
+ *	Data callback for capwap
+ */
+static void nss_nlcapwap_data_cb(void *app_data, struct sk_buff *skb)
+{
+	struct nss_nlcapwap_app_hdr *apph;
+	struct nss_dtlsmgr_metadata *mh;
+	struct nss_nlcapwap_tunnel *tun;
+	uint32_t exp_seq;
+	uint32_t tun_id;
+
+	/*
+	 * Move the pointer to start of custom header
+	 */
+	apph = (struct nss_nlcapwap_app_hdr *)skb_pull(skb, sizeof(*mh) + 8);
+	tun_id = apph->tun_id;
+
+	/*
+	 * Aquire lock and check if the seq num in packet is what we expected as rx_seq
+	 */
+	write_lock_bh(&global_ctx.lock);
+	tun = nss_nlcapwap_get_tun_by_index(tun_id);
+	if (!tun) {
+		write_unlock_bh(&global_ctx.lock);
+		nss_nl_error("%px: Could not find tunnel associated with index: %d\n", skb, tun_id);
+		return;
+	}
+
+	/*
+	 * Check if the received sequence number matches with the expected sequence number
+	 */
+	exp_seq = tun->kalive.rx_seq;
+	tun->stats.rx_ka_pkts++;
+	tun->kalive.rx_seq = apph->seq_num + 1;
+	tun->stats.ka_seq_fail += (apph->seq_num != exp_seq);
+	write_unlock_bh(&global_ctx.lock);
+
+	/*
+	 * TODO: If, we have exceeded ka_seq_fail threshold then destroy tunnel
+	 */
+	nss_nl_info("%px: RX DTLS pkt len:%d, tun_id:%d, seq_num:%u\n", skb, skb->len, apph->tun_id, apph->seq_num);
+	dev_kfree_skb_any(skb);
+}
+
+/*
+ * nss_nlcapwap_dtls_configure()
+ *	Common handler for v4 and v6 capwap-dtls configuration
+ */
+static void nss_nlcapwap_dtls_configure(struct nss_dtlsmgr_config *dcfg, struct nss_nlcapwap_rule *nl_rule)
+{
+	uint8_t algo = nl_rule->msg.dtls.encap.crypto.algo;
+
+	dcfg->flags = nl_rule->msg.dtls.flags;
+	dcfg->flags |= NSS_DTLSMGR_HDR_CAPWAP;
+
+	if (algo == NSS_DTLSMGR_ALGO_AES_GCM) {
+		dcfg->flags |= NSS_DTLSMGR_CIPHER_MODE_GCM;
+	}
+
+	/*
+	 * Encap configuration
+	 */
+	dcfg->app_data = NULL;
+	dcfg->notify = NULL;
+	dcfg->data = nss_nlcapwap_data_cb;
+
+	memcpy(&dcfg->encap, &nl_rule->msg.dtls.encap, sizeof(struct nss_dtlsmgr_encap_config));
+	memcpy(&dcfg->decap, &nl_rule->msg.dtls.decap, sizeof(struct nss_dtlsmgr_decap_config));
+}
+
+/*
+ * nss_nlcapwap_create_tun_ipv4_config()
+ *	Configures the common rule for rx and tx.
+ */
+static void nss_nlcapwap_create_tun_ipv4_config(struct nss_nlcapwap_rule *nl_rule,
+		struct nss_capwap_rule_msg *capwap_rule, struct nss_dtlsmgr_config *dtls_ipv4,
+		struct nss_ipv4_create *ipv4)
+{
+	struct net_device *wan_ndev;
+	uint32_t features = 0;
+	uint32_t if_num;
+
+	/*
+	 * Initialize the msgs
+	 */
+	memset(ipv4, 0, sizeof(*ipv4));
+	memset(capwap_rule, 0, sizeof(*capwap_rule));
+
+	/*
+	 * Configure CAPWAP rule
+	 */
+	capwap_rule->encap.path_mtu = htonl(nl_rule->msg.create.rule.encap.path_mtu);
+	capwap_rule->decap.reassembly_timeout = htonl(nl_rule->msg.create.rule.decap.reassembly_timeout);
+	capwap_rule->decap.max_fragments = htonl(nl_rule->msg.create.rule.decap.max_fragments);
+	capwap_rule->decap.max_buffer_size = htonl(nl_rule->msg.create.rule.decap.max_buffer_size);
+	capwap_rule->stats_timer = htonl(nl_rule->msg.create.rule.stats_timer);
+	capwap_rule->l3_proto = NSS_CAPWAP_TUNNEL_IPV4;
+	if (nl_rule->msg.create.rule.which_udp == IPPROTO_UDP) {
+		capwap_rule->which_udp = NSS_CAPWAP_TUNNEL_UDP;
+		ipv4->protocol = IPPROTO_UDP;
+	} else {
+		capwap_rule->which_udp = NSS_CAPWAP_TUNNEL_UDPLite;
+		ipv4->protocol = IPPROTO_UDPLITE;
+	}
+
+	if (nl_rule->msg.create.inner_trustsec_en) {
+		nss_nl_info("Enabling INNER TRUSTSEC in rule\n");
+		features |= NSS_CAPWAPMGR_FEATURE_INNER_TRUSTSEC_ENABLED;
+	}
+
+	if (nl_rule->msg.create.outer_trustsec_en) {
+		nss_nl_info("Enabling OUTER TRUSTSEC in rule\n");
+		features |= NSS_CAPWAPMGR_FEATURE_OUTER_TRUSTSEC_ENABLED;
+	}
+
+	if (nl_rule->msg.create.wireless_qos_en) {
+		nss_nl_info("Enabling WIRELESS QOS\n");
+		features |= NSS_CAPWAPMGR_FEATURE_WIRELESS_QOS_ENABLED;
+	}
+
+	capwap_rule->enabled_features = features;
+
+	/*
+	 * Configure IPv4 rule
+	 */
+	wan_ndev = dev_get_by_name(&init_net, &nl_rule->msg.create.gmac_ifname[0]);
+	if (!wan_ndev) {
+		nss_nl_info("Can't find %s netdev\n", nl_rule->msg.create.gmac_ifname);
+		return;
+	}
+
+	if_num = nss_cmn_get_interface_number_by_dev(wan_ndev);
+	nss_nl_info("CAPWAP on %s, if_num is %d\n", nl_rule->msg.create.gmac_ifname, if_num);
+	ipv4->src_interface_num = if_num;
+	ipv4->dest_interface_num = NSS_NLCAPWAP_WAN_IFNUM;
+	ipv4->from_mtu = wan_ndev->mtu;
+	ipv4->to_mtu = wan_ndev->mtu;
+
+	ipv4->src_ip = nl_rule->msg.create.rule.encap.src_ip.ip.ipv4;
+	ipv4->src_port = nl_rule->msg.create.rule.encap.src_port;
+	ipv4->src_ip_xlate = nl_rule->msg.create.rule.encap.src_ip.ip.ipv4;
+	ipv4->src_port_xlate = nl_rule->msg.create.rule.encap.src_port;
+
+	ipv4->dest_ip = nl_rule->msg.create.rule.encap.dest_ip.ip.ipv4;
+	ipv4->dest_port = nl_rule->msg.create.rule.encap.dest_port;
+	ipv4->dest_ip_xlate = nl_rule->msg.create.rule.encap.dest_ip.ip.ipv4;
+	ipv4->dest_port_xlate = nl_rule->msg.create.rule.encap.dest_port;
+
+	memcpy(ipv4->src_mac, nl_rule->msg.create.gmac_ifmac, sizeof(ipv4->src_mac));
+
+	ipv4->in_vlan_tag[0] = NSS_NLCAPWAP_VLAN_TAG_INVALID;
+	ipv4->in_vlan_tag[1] = NSS_NLCAPWAP_VLAN_TAG_INVALID;
+	ipv4->out_vlan_tag[0] = NSS_NLCAPWAP_VLAN_TAG_INVALID;
+	ipv4->out_vlan_tag[1] = NSS_NLCAPWAP_VLAN_TAG_INVALID;
+	dev_put(wan_ndev);
+}
+
+/*
+ * nss_nlcapwap_create_tun_ipv6_config()
+ *	Configures the common rule for rx and tx.
+ */
+static void nss_nlcapwap_create_tun_ipv6_config(struct nss_nlcapwap_rule *nl_rule,
+		struct nss_capwap_rule_msg *capwap_rule, struct nss_dtlsmgr_config *dtls_ipv6,
+		struct nss_ipv6_create *ipv6)
+{
+	struct net_device *wan_ndev;
+	uint32_t features = 0;
+	uint32_t if_num;
+
+	/*
+	 * Initialize the msgs
+	 */
+	memset(ipv6, 0, sizeof (struct nss_ipv6_create));
+	memset(capwap_rule, 0, sizeof(struct nss_capwap_rule_msg));
+
+	/*
+	 * Configuring capwap rule
+	 */
+	capwap_rule->encap.path_mtu = htonl(nl_rule->msg.create.rule.encap.path_mtu);
+	capwap_rule->decap.reassembly_timeout = htonl(nl_rule->msg.create.rule.decap.reassembly_timeout);
+	capwap_rule->decap.max_fragments = htonl(nl_rule->msg.create.rule.decap.max_fragments);
+	capwap_rule->decap.max_buffer_size = htonl(nl_rule->msg.create.rule.decap.max_buffer_size);
+	capwap_rule->stats_timer = htonl(nl_rule->msg.create.rule.stats_timer);
+	capwap_rule->l3_proto = NSS_CAPWAP_TUNNEL_IPV6;
+
+	if (nl_rule->msg.create.rule.which_udp == IPPROTO_UDP) {
+		capwap_rule->which_udp = NSS_CAPWAP_TUNNEL_UDP;
+		ipv6->protocol = IPPROTO_UDP;
+	} else {
+		capwap_rule->which_udp = NSS_CAPWAP_TUNNEL_UDPLite;
+		ipv6->protocol = IPPROTO_UDPLITE;
+	}
+
+	if (nl_rule->msg.create.inner_trustsec_en) {
+		nss_nl_info("Enabling INNER TRUSTSEC in rule\n");
+		features |= NSS_CAPWAPMGR_FEATURE_INNER_TRUSTSEC_ENABLED;
+	}
+
+	if (nl_rule->msg.create.outer_trustsec_en) {
+		nss_nl_info("Enabling OUTER TRUSTSEC in rule\n");
+		features |= NSS_CAPWAPMGR_FEATURE_OUTER_TRUSTSEC_ENABLED;
+	}
+
+	if (nl_rule->msg.create.wireless_qos_en) {
+		nss_nl_info("Enabling WIRELESS QOS\n");
+		features |= NSS_CAPWAPMGR_FEATURE_WIRELESS_QOS_ENABLED;
+	}
+
+	capwap_rule->enabled_features = features;
+	capwap_rule->outer_sgt_value = nl_rule->msg.create.rule.outer_sgt_value;
+
+	/*
+	 * Configure IPv6 rule
+	 */
+	wan_ndev = dev_get_by_name(&init_net, &nl_rule->msg.create.gmac_ifname[0]);
+	if (!wan_ndev) {
+		nss_nl_info("Can't find %s netdev\n", nl_rule->msg.create.gmac_ifname);
+		return;
+	}
+
+	if_num = nss_cmn_get_interface_number_by_dev(wan_ndev);
+	nss_nl_info("CAPWAP on %s, if_num is %d\n", nl_rule->msg.create.gmac_ifname, if_num);
+	ipv6->src_interface_num = if_num;
+	ipv6->dest_interface_num = NSS_NLCAPWAP_WAN_IFNUM;
+	ipv6->from_mtu = wan_ndev->mtu;
+	ipv6->to_mtu = wan_ndev->mtu;
+	memcpy(ipv6->src_ip, nl_rule->msg.create.rule.encap.src_ip.ip.ipv6, sizeof(ipv6->src_ip));
+	memcpy(ipv6->dest_ip, nl_rule->msg.create.rule.encap.dest_ip.ip.ipv6, sizeof(ipv6->dest_ip));
+	memcpy(&ipv6->src_mac[0], &nl_rule->msg.create.gmac_ifmac[0], sizeof(ipv6->src_mac));
+	ipv6->src_port = nl_rule->msg.create.rule.encap.src_port;
+	ipv6->dest_port = nl_rule->msg.create.rule.encap.dest_port;
+	ipv6->in_vlan_tag[0] = NSS_NLCAPWAP_VLAN_TAG_INVALID;
+	ipv6->in_vlan_tag[1] = NSS_NLCAPWAP_VLAN_TAG_INVALID;
+	ipv6->out_vlan_tag[0] = NSS_NLCAPWAP_VLAN_TAG_INVALID;
+	ipv6->out_vlan_tag[1] = NSS_NLCAPWAP_VLAN_TAG_INVALID;
+	dev_put(wan_ndev);
+}
+
+/*
+ * nss_nlcapwap_ops_create_tun()
+ *	Handler for creating tunnel
+ */
+static int nss_nlcapwap_ops_create_tun(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_capwap_rule_msg capwap_rule;
+	struct nss_dtlsmgr_config dtls_ipv4;
+	struct nss_dtlsmgr_config dtls_ipv6;
+	struct nss_nlcapwap_rule *nl_rule;
+	struct nss_ipv4_create ipv4_rule;
+	struct nss_ipv6_create ipv6_rule;
+	struct nss_nlcapwap_tunnel *tun;
+	struct net_device *capwap_dev;
+	struct nss_nlcmn *nl_cm;
+	uint16_t tun_id;
+	int ret = 0;
+
+	/*
+	 * Get the tunnel_id. We only create a new tunnel if max limit is not exceeded
+	 */
+	write_lock_bh(&global_ctx.lock);
+	tun_id = find_first_zero_bit(global_ctx.tun_bitmap, NSS_CAPWAPMGR_MAX_TUNNELS);
+	if (tun_id >= NSS_CAPWAPMGR_MAX_TUNNELS) {
+		nss_nl_error("All tunnels exhausted(%d), no free tunnel found.\n", tun_id);
+		return -ENOSPC;
+	}
+
+	tun = &global_ctx.tun[tun_id];
+	nss_nlcapwap_tun_init(tun, tun_id);
+
+	set_bit(tun_id, global_ctx.tun_bitmap);
+	write_unlock_bh(&global_ctx.lock);
+
+	/*
+	 * Get the capwap netdev reference
+	 */
+	capwap_dev = global_ctx.capwap_dev;
+	if (!capwap_dev) {
+		nss_nl_error("Failed to find CAPWAP netdevice\n");
+		return -ENODEV;
+	}
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlcapwap_family, info, NSS_NLCAPWAP_CMD_TYPE_CREATE_TUN);
+	if (!nl_cm) {
+		nss_nl_error("Unable to extract create tunnel data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlcapwap_rule, cm);
+
+	/*
+	 * Needed for 802.3 to 802.11 conversion
+	 */
+	memcpy(capwap_rule.bssid, nl_rule->msg.create.rule.bssid, sizeof(capwap_rule.bssid));
+	capwap_rule.outer_sgt_value = nl_rule->msg.create.rule.outer_sgt_value;
+
+	/*
+	 * Create tunnel based on ip version
+	 */
+	if (nl_rule->msg.create.rule.l3_proto == NSS_NLCAPWAP_IP_VERS_4) {
+		nss_nlcapwap_create_tun_ipv4_config(nl_rule, &capwap_rule, &dtls_ipv4, &ipv4_rule);
+		/*
+		 * Create CAPWAP IPv4 tunnel
+		 */
+		ret = nss_capwapmgr_ipv4_tunnel_create(capwap_dev, tun_id, &ipv4_rule, &capwap_rule, &dtls_ipv4);
+		if (ret != 0) {
+			nss_nl_error("Unable to create tunnel(%d), status(%d)\n", tun_id, ret);
+			return -EAGAIN;
+		}
+
+		nss_nl_info("Created IPv4 tunnel: src:%pI4h(%d) dst:%pI4h(%d) p:%d\n\n",
+				&ipv4_rule.src_ip, ipv4_rule.src_port, &ipv4_rule.dest_ip,
+				ipv4_rule.dest_port, ipv4_rule.protocol);
+	} else {
+		nss_nlcapwap_create_tun_ipv6_config(nl_rule, &capwap_rule, &dtls_ipv6, &ipv6_rule);
+		/*
+		 * Create CAPWAP IPv6 tunnel
+		 */
+		ret = nss_capwapmgr_ipv6_tunnel_create(capwap_dev, tun_id, &ipv6_rule, &capwap_rule, &dtls_ipv6);
+		if (ret != 0) {
+			nss_nl_error("Unable to create tunnel: %d\n", tun_id);
+			return -EAGAIN;
+		}
+
+		nss_nl_info("Created IPv6 tunnel: src:%pI6(%d), dst:%pI6(%d), proto:%d\n\n",
+				ipv6_rule.src_ip, ipv6_rule.src_port, ipv6_rule.dest_ip, ipv6_rule.dest_port,
+				ipv6_rule.protocol);
+	}
+
+	nss_capwapmgr_change_version(capwap_dev, tun_id, NSS_CAPWAP_VERSION_V2);
+	nss_capwapmgr_enable_tunnel(capwap_dev, tun_id);
+
+	nss_nl_info("Successfully created tunnel %d\n", tun_id);
+	return 0;
+}
+
+/*
+ * nss_nlcapwap_ops_destroy_tun()
+ *	Handler to destroy tunnel
+ */
+static int nss_nlcapwap_ops_destroy_tun(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nlcapwap_rule *nl_rule;
+	struct nss_nlcapwap_tunnel *tun;
+	struct nss_nlcmn *nl_cm;
+	uint16_t tun_id;
+	int ret;
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlcapwap_family, info, NSS_NLCAPWAP_CMD_TYPE_DESTROY_TUN);
+	if (!nl_cm) {
+		nss_nl_error("Unable to extract destroy tunnel data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlcapwap_rule, cm);
+
+	/*
+	 * Get the tunnel id
+	 */
+	tun_id = nl_rule->msg.destroy.tun_id;
+	if (tun_id >= NSS_CAPWAPMGR_MAX_TUNNELS) {
+		nss_nl_error("Not a valid tunnel_id: %d\n", tun_id);
+		return -ENODEV;
+	}
+
+	write_lock_bh(&global_ctx.lock);
+	tun = nss_nlcapwap_get_tun_by_index(tun_id);
+	if (!tun) {
+		write_unlock_bh(&global_ctx.lock);
+		nss_nl_error("%px: Could not find tunnel associated with index: %d\n", nl_rule, tun_id);
+		return -ENODEV;
+	}
+
+	nss_nlcapwap_tun_deinit(tun);
+	clear_bit(tun_id, global_ctx.tun_bitmap);
+	write_unlock_bh(&global_ctx.lock);
+
+	/*
+	 * Destroy the corresponding tunnel
+	 */
+	ret = nss_nlcapwap_destroy_tun(tun_id);
+	if (ret) {
+		nss_nl_error("Unable to set the tunnel status to 0 for tun: %d\n", tun_id);
+		return -EINVAL;
+	}
+
+	nss_nl_info("Successfully destroyed %d tunnel\n", nl_rule->msg.destroy.tun_id);
+	return 0;
+}
+
+/*
+ * nss_nlcapwap_ops_update_mtu()
+ *	Handler for updating mtu
+ */
+static int nss_nlcapwap_ops_update_mtu(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nlcapwap_rule *nl_rule;
+	struct net_device *capwap_dev;
+	nss_capwapmgr_status_t status;
+	struct nss_nlcmn *nl_cm;
+	uint16_t tun_id;
+	uint32_t mtu;
+
+	/*
+	 * Get the capwap netdev reference
+	 */
+	capwap_dev = global_ctx.capwap_dev;
+	if (!capwap_dev) {
+		nss_nl_error("Failed to find CAPWAP netdevice\n");
+		return -ENODEV;
+	}
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlcapwap_family, info, NSS_NLCAPWAP_CMD_TYPE_UPDATE_MTU);
+	if (!nl_cm) {
+		nss_nl_error("Unable to extract update mtu data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlcapwap_rule, cm);
+
+	/*
+	 * Update the path_mtu of the corresponding tunnel
+	 */
+	tun_id = nl_rule->msg.update_mtu.tun_id;
+	if (tun_id >= NSS_CAPWAPMGR_MAX_TUNNELS) {
+		nss_nl_error("Not a valid tunnel_id: %d\n", tun_id);
+		return -ENODEV;
+	}
+
+	mtu = nl_rule->msg.update_mtu.mtu.path_mtu;
+
+	status = nss_capwapmgr_update_path_mtu(capwap_dev, tun_id, mtu);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_nl_error("Unable to update the mtu of the %d tunnel: %d\n", tun_id, mtu);
+		return -EINVAL;
+	}
+
+	nss_nl_info("Successfully updated the mtu of the %d tunnel.\n", tun_id);
+	return 0;
+}
+
+/*
+ * nss_nlcapwap_ops_dtls()
+ *	Handler for dtls enable or disable command
+ */
+static int nss_nlcapwap_ops_dtls(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_dtlsmgr_config dtls_config;
+	struct nss_nlcapwap_rule *nl_rule;
+	struct net_device *capwap_dev;
+	nss_capwapmgr_status_t status;
+	struct nss_nlcmn *nl_cm;
+	uint16_t tun_id;
+
+	/*
+	 * Get the capwap netdev reference
+	 */
+	capwap_dev = global_ctx.capwap_dev;
+	if (!capwap_dev) {
+		nss_nl_error("Failed to find CAPWAP netdevice\n");
+		return -ENODEV;
+	}
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlcapwap_family, info, NSS_NLCAPWAP_CMD_TYPE_DTLS);
+	if (!nl_cm) {
+		nss_nl_error("Unable to extract dtls data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Disabling dtls for capwap
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlcapwap_rule, cm);
+
+	tun_id = nl_rule->msg.dtls.tun_id;
+	if (tun_id >= NSS_CAPWAPMGR_MAX_TUNNELS) {
+		nss_nl_error("Not a valid tunnel_id: %d\n", tun_id);
+		return -ENODEV;
+	}
+
+	if (!nl_rule->msg.dtls.enable_dtls) {
+		status = nss_capwapmgr_disable_tunnel(capwap_dev, tun_id);
+		if (status != NSS_CAPWAPMGR_SUCCESS) {
+			nss_nl_error("Not able to disable tunnel %d\n", tun_id);
+			return -EBUSY;
+		}
+
+		status = nss_capwapmgr_configure_dtls(capwap_dev, tun_id, 0, NULL);
+		if (status != NSS_CAPWAPMGR_SUCCESS) {
+			nss_nl_error("Not able to disable dtls for tunnel(%d)\n", tun_id);
+			nss_capwapmgr_enable_tunnel(capwap_dev, tun_id);
+			return -EINVAL;
+		}
+
+		status = nss_capwapmgr_enable_tunnel(capwap_dev, tun_id);
+		if (status != NSS_CAPWAPMGR_SUCCESS) {
+			nss_nl_error("Not able to enable tunnel %d\n", tun_id);
+			return -EINVAL;
+		}
+
+		nss_nl_info("Succesfully disabled dtls for capwap tunnel %d\n", tun_id);
+		return 0;
+	}
+
+	nss_nl_info("Enabling DTLS for tunnel %d\n", tun_id);
+
+	/*
+	 * Fill DTLS configuration data
+	 */
+	nss_nlcapwap_dtls_configure(&dtls_config, nl_rule);
+
+	/*
+	 * Enabling dtls for capwap tunnel
+	 */
+	status = nss_capwapmgr_disable_tunnel(capwap_dev, tun_id);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_nl_error("Not able to disable tunnel %d\n", tun_id);
+		return -EBUSY;
+	}
+
+	status = nss_capwapmgr_configure_dtls(capwap_dev, tun_id, 1, &dtls_config);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_nl_error("Not able to enable dtls for tunnel %d\n", tun_id);
+		nss_capwapmgr_enable_tunnel(capwap_dev, tun_id);
+		return -EINVAL;
+	}
+
+	status = nss_capwapmgr_enable_tunnel(capwap_dev, tun_id);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_nl_error("Not able to enable tunnel %d\n", tun_id);
+		return -EINVAL;
+	}
+
+	nss_nl_info("Successfully enabled dtls for the capwap tunnel: %d\n", tun_id);
+	return 0;
+}
+
+/*
+ * nss_nlcapwap_ops_perf()
+ *	Handler for enabling or disabling perf
+ */
+static int nss_nlcapwap_ops_perf(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nlcapwap_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	bool perf_en;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlcapwap_family, info, NSS_NLCAPWAP_CMD_TYPE_PERF);
+	if (!nl_cm) {
+		nss_nl_error("Unable to extract perf parameter.\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlcapwap_rule, cm);
+	perf_en = !!nl_rule->msg.perf.perf_en;
+
+	atomic_set(&global_ctx.enable_perf, perf_en);
+	nss_nl_info("Successfully %s performance\n", perf_en ? "enabled" : "disabled");
+
+	return 0;
+}
+
+/*
+ * nss_nlcapwap_ops_ip_flow()
+ *	Handler for adding or deleting ip flow rule
+ */
+static int nss_nlcapwap_ops_ip_flow(struct sk_buff *skb, struct genl_info *info)
+{
+	nss_capwapmgr_status_t status;
+	struct nss_nlcapwap_rule *nl_rule;
+	struct net_device *capwap_dev;
+	struct nss_nlcmn *nl_cm;
+
+	/*
+	 * Get the capwap netdev reference
+	 */
+	capwap_dev = global_ctx.capwap_dev;
+	if (!capwap_dev) {
+		nss_nl_error("Failed to find CAPWAP netdevice\n");
+		return -ENODEV;
+	}
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlcapwap_family, info, NSS_NLCAPWAP_CMD_TYPE_IP_FLOW);
+	if (!nl_cm) {
+		nss_nl_error("Unable to extract ip flow rule.\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlcapwap_rule, cm);
+
+	/*
+	 * Add flow rule
+	 */
+	if (nl_rule->msg.ip_flow.ip_flow_mode == NSS_NLCAPWAP_IP_FLOW_MODE_ADD) {
+		status = nss_capwapmgr_add_flow_rule(capwap_dev, nl_rule->msg.ip_flow.tun_id,
+				nl_rule->msg.ip_flow.flow.ip_version, nl_rule->msg.ip_flow.flow.protocol,
+				nl_rule->msg.ip_flow.flow.src_ip, nl_rule->msg.ip_flow.flow.dst_ip,
+				nl_rule->msg.ip_flow.flow.src_port, nl_rule->msg.ip_flow.flow.dst_port,
+				nl_rule->msg.ip_flow.flow.flow_id);
+		if (status != NSS_CAPWAPMGR_SUCCESS) {
+			nss_nl_error("Unable to add flow rule\n");
+			return -EAGAIN;
+		}
+
+		nss_nl_info("Succesfully added flow rule for tunnel %d\n",
+				nl_rule->msg.ip_flow.tun_id);
+		return 0;
+	}
+
+	/*
+	 * Delete existing flow rule
+	 */
+	status = nss_capwapmgr_del_flow_rule(capwap_dev, nl_rule->msg.ip_flow.tun_id,
+			nl_rule->msg.ip_flow.flow.ip_version, nl_rule->msg.ip_flow.flow.protocol,
+			nl_rule->msg.ip_flow.flow.src_ip, nl_rule->msg.ip_flow.flow.dst_ip,
+			nl_rule->msg.ip_flow.flow.src_port, nl_rule->msg.ip_flow.flow.dst_port);
+	if (status != NSS_CAPWAPMGR_SUCCESS) {
+		nss_nl_error("Unable to del flow rule\n");
+		return -EAGAIN;
+	}
+
+	nss_nl_info("Succesfully deleted flow rule for tunnel %d\n", nl_rule->msg.ip_flow.tun_id);
+	return 0;
+}
+
+/*
+ * nss_nlcapwap_tx_packets()
+ *	Handler for sending traffic from one DUT to other
+ */
+static int nss_nlcapwap_tx_packets(struct nss_nlcapwap_rule *nl_rule)
+{
+	struct nss_capwap_metaheader *mh;
+	struct nss_nlcapwap_tunnel *tun;
+	struct net_device *capwap_dev;
+	struct sk_buff *skb;
+	size_t align_offset;
+	uint16_t tun_id;
+	uint8_t mh_type;
+	size_t pkt_sz;
+	size_t skb_sz;
+
+	tun_id = nl_rule->msg.tx_packets.tun_id;
+	pkt_sz = nl_rule->msg.tx_packets.pkt_size;
+
+	/*
+	 * Get the capwap netdev reference;
+	 * TODO: We need to add the DTLS needed headroom/tailroom to it
+	 */
+	capwap_dev = global_ctx.capwap_dev;
+	if (!capwap_dev) {
+		nss_nl_error("Failed to find CAPWAP netdevice\n");
+		return -ENODEV;
+	}
+
+	skb_sz = NSS_NLCAPWAP_MAX_HEADROOM + pkt_sz + NSS_NLCAPWAP_MAX_TAILROOM + SMP_CACHE_BYTES;
+
+	skb = dev_alloc_skb(skb_sz);
+	if (!skb) {
+		nss_nl_error("%px: Could not allocate a sk_buff of size(%zu).\n", capwap_dev, skb_sz);
+		return -ENOMEM;
+	}
+
+	/*
+	 * Reserve headroom for tunnel headers CAPWAP/DTLS
+	 */
+	align_offset = PTR_ALIGN(skb->data, SMP_CACHE_BYTES) - skb->data;
+	skb_reserve(skb, NSS_NLCAPWAP_MAX_HEADROOM + align_offset + sizeof(uint16_t));
+
+	write_lock_bh(&global_ctx.lock);
+	tun = nss_nlcapwap_get_tun_by_index(tun_id);
+	if (!tun) {
+		write_unlock_bh(&global_ctx.lock);
+		dev_kfree_skb_any(skb);
+		nss_nl_error("%px: Could not find tunnel associated with index: %d\n", nl_rule, tun_id);
+		return -ENODEV;
+	}
+
+	mh = (struct nss_capwap_metaheader *)skb_put(skb, sizeof(*mh));
+	memcpy(mh, tun->mh.meta_header_blob, NSS_NLCAPWAP_META_HEADER_SZ);
+	mh_type = tun->mh.type;
+	tun->stats.tx_data_pkts++;
+	write_unlock_bh(&global_ctx.lock);
+	pkt_sz -= sizeof(*mh);
+
+	/*
+	 * Set the appropriate ether_type
+	 */
+	if (mh_type == NSS_NLCAPWAP_META_HEADER_TYPE_IPV4_DATA) {
+		/*
+		 * For normal ipv4 data frames.
+		 */
+		struct ethhdr *eh = (struct ethhdr *)skb_put(skb, sizeof(*eh));
+		eh->h_proto = htons(ETH_P_IP);
+		pkt_sz -= sizeof(*eh);
+	} else if (mh_type == NSS_NLCAPWAP_META_HEADER_TYPE_EAPOL) {
+		/*
+		 * EAPOL type frames.
+		 */
+		struct ethhdr *eh = (struct ethhdr *)skb_put(skb, sizeof(*eh));
+		eh->h_proto = htons(ETH_P_PAE);
+		pkt_sz -= sizeof(*eh);
+	} else {
+		/*
+		 * DTLS management type frames.
+		 */
+		uint16_t *data = (uint16_t *)skb_put(skb, sizeof(*data));
+		*data = htons(NSS_CAPWAP_PKT_TYPE_DTLS_ENABLED);
+		pkt_sz -= sizeof(*data);
+	}
+
+	if (!atomic_read(&global_ctx.enable_perf)) {
+		memset(skb_put(skb, pkt_sz), NSS_NLCAPWAP_DATA, pkt_sz);
+	}
+
+	BUG_ON(!IS_ALIGNED((unsigned long)skb->data, sizeof(uint16_t)));
+
+	if (capwap_dev->netdev_ops->ndo_start_xmit(skb, capwap_dev) != NETDEV_TX_OK) {
+		dev_kfree_skb_any(skb);
+		return -EBUSY;
+	}
+
+	nss_nl_info("Tx packet for tun(%d), skb_size(%zu) matched(%zu)\n", mh->tunnel_id, skb_sz, pkt_sz);
+	return 0;
+}
+
+/*
+ * nss_nlcapwap_ops_tx_packets()
+ *	Handler for sending traffic
+ */
+static int nss_nlcapwap_ops_tx_packets(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nlcapwap_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	uint16_t num_pkts;
+	int ret;
+	int i;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlcapwap_family, info, NSS_NLCAPWAP_CMD_TYPE_TX_PACKETS);
+	if (!nl_cm) {
+		nss_nl_error("Unable to extract tx_packets data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlcapwap_rule, cm);
+	num_pkts = nl_rule->msg.tx_packets.num_of_packets;
+
+	for (i = 0; i < num_pkts; i++) {
+		ret = nss_nlcapwap_tx_packets(nl_rule);
+		if (ret < 0) {
+			nss_nl_error("Error in transmission of skb\n");
+			return ret;
+		}
+	}
+
+	nss_nl_info("Traffic transmission successful\n");
+	return 0;
+}
+
+/*
+ * nss_nlcapwap_ops_meta_header()
+ *	Handler for creating meta header
+ */
+static int nss_nlcapwap_ops_meta_header(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nlcapwap_rule *nl_rule;
+	struct nss_nlcapwap_tunnel *tun;
+	struct nss_nlcmn *nl_cm;
+	uint16_t tun_id;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlcapwap_family, info, NSS_NLCAPWAP_CMD_TYPE_META_HEADER);
+	if (!nl_cm) {
+		nss_nl_error("Unable to extract meta header values.\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlcapwap_rule, cm);
+	tun_id = nl_rule->msg.meta_header.tun_id;
+
+	/*
+	 * Set meta header values
+	 */
+	write_lock_bh(&global_ctx.lock);
+	tun = nss_nlcapwap_get_tun_by_index(tun_id);
+	if (!tun) {
+		write_unlock_bh(&global_ctx.lock);
+		nss_nl_error("%px: Could not find tunnel associated with index: %d\n", nl_rule, tun_id);
+		return -EAGAIN;
+	}
+
+	tun->mh = nl_rule->msg.meta_header;
+	write_unlock_bh(&global_ctx.lock);
+	nss_nl_info("Successfully created meta header.\n");
+	return 0;
+}
+
+/*
+ * nss_nlcapwap_ops_get_stats()
+ *	get stats handler
+ */
+static int nss_nlcapwap_ops_get_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+/*
+ * nss_nlcapwap_ops_keepalive()
+ *	Handler for enabling and disabling keepalive flag
+ */
+static int nss_nlcapwap_ops_keepalive(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nlcapwap_rule *nl_rule;
+	struct nss_nlcapwap_tunnel *tun;
+	struct net_device *dtls_dev;
+	struct delayed_work *dwork;
+	struct nss_nlcmn *nl_cm;
+	uint32_t tun_id;
+	bool kalive;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlcapwap_family, info, NSS_NLCAPWAP_CMD_TYPE_KEEPALIVE);
+	if (!nl_cm) {
+		nss_nl_error("Unable to extract meta header values.\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlcapwap_rule, cm);
+
+	/*
+	 * Extract the tun_id
+	 */
+	tun_id = nl_rule->msg.kalive.tun_id;
+	dtls_dev = nss_capwapmgr_get_dtls_netdev(global_ctx.capwap_dev, tun_id);
+	if (!dtls_dev) {
+		nss_nl_error("%px: Failed to find DTLS dev for (%s)\n", &nl_rule, global_ctx.capwap_dev->name);
+		return -ENODEV;
+	}
+
+	/*
+	 * Get the local tunnel object
+	 */
+	write_lock_bh(&global_ctx.lock);
+	tun = nss_nlcapwap_get_tun_by_index(tun_id);
+	if (!tun) {
+		write_unlock_bh(&global_ctx.lock);
+		nss_nl_error("%px: Could not find tunnel associated with index: %d\n", nl_rule, tun_id);
+		dev_put(dtls_dev);
+		return -EAGAIN;
+	}
+
+	dwork = &tun->kalive.work;
+	kalive = nl_rule->msg.kalive.tx_keepalive;
+	atomic_set(&tun->kalive.status, kalive);
+
+	write_unlock_bh(&global_ctx.lock);
+
+	/*
+	 * Check if dtls keepalive packets needs to be sent
+	 */
+	if (kalive) {
+		schedule_delayed_work(dwork, NSS_NLCAPWAP_KALIVE_TIMER_MSECS);
+	} else {
+		flush_delayed_work(dwork);
+	}
+
+	nss_nl_info("%px: keepalive %s for tun(%d)\n", tun, kalive ? "enabled" : "disabled", tun_id);
+	dev_put(dtls_dev);
+	return 0;
+}
+
+/*
+ * nss_nlcapwap_tunnel_stats_read()
+ *	Reads the netlink capwap stats
+ */
+static ssize_t nss_nlcapwap_tunnel_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *f_ppos)
+{
+	struct nss_nlcapwap_tunnel_stats stats = {0};
+	struct nss_nlcapwap_tunnel *tun;
+	uint32_t max_output_lines;
+	ssize_t bytes_read = 0;
+	ssize_t size_wr = 0;
+	ssize_t size_al;
+	char *lbuf;
+	int index;
+
+	/*
+	 * Header and footer for instance stats
+	 */
+	max_output_lines = 4 + (NSS_CAPWAPMGR_MAX_TUNNELS * NSS_NLCAPWAP_STATS_MAX);
+	size_al = NSS_NLCAPWAP_MAX_STR_LEN * max_output_lines;
+
+	lbuf = vzalloc(size_al);
+	if (!lbuf) {
+		nss_nl_error("%px: Could not allocate space for debug entry\n", f_ppos);
+		return 0;
+	}
+
+	/*
+	 * Session stats
+	 */
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nCapwap netlinks stats start:\n\n");
+	for (index = 0; index < NSS_CAPWAPMGR_MAX_TUNNELS; index++) {
+		/*
+		 * Copy the tunnels stats
+		 */
+		read_lock_bh(&global_ctx.lock);
+		tun = nss_nlcapwap_get_tun_by_index(index);
+		if (!tun) {
+			read_unlock_bh(&global_ctx.lock);
+			continue;
+		}
+
+		memcpy(&stats, &tun->stats, sizeof(stats));
+		read_unlock_bh(&global_ctx.lock);
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "----------------------------");
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n%s\t: %d", "Tunnel ID", index);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n%s\t: %d", "tx_data_pkts", stats.tx_data_pkts);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n%s\t: %d", "rx_data_pkts", stats.rx_data_pkts);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n%s\t: %d", "tx_ka_pkts", stats.tx_ka_pkts);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n%s\t: %d", "rx_ka_pkts", stats.rx_ka_pkts);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n%s\t: %d", "ka_seq_fail", stats.ka_seq_fail);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n----------------------------");
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+	}
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nCapwap netlinks stats end.\n\n");
+	bytes_read = simple_read_from_buffer(ubuf, sz, f_ppos, lbuf, size_wr);
+
+	vfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_nlcapwap_stats_ops
+ *	Defines the file operations for nlcapwap dentry
+ */
+static const struct file_operations nss_nlcapwap_stats_ops = {
+	.read = nss_nlcapwap_tunnel_stats_read,
+};
+
+/*
+ * nss_nlcapwap_get_ifnum()
+ *	Get the interface number corresponding to netdev
+ */
+int nss_nlcapwap_get_ifnum(struct net_device *dev, enum nss_dynamic_interface_type type)
+{
+	int ifnum;
+
+	/*
+	 * Get the interface number depending upon the dev and type
+	 */
+	ifnum = nss_cmn_get_interface_number_by_dev_and_type(dev, type);
+	if (ifnum < 0) {
+		nss_nl_error("%px: Failed to find interface number (dev:%s, type:%d)\n",
+				dev, dev->name, type);
+		return -ENODEV;
+	}
+
+	return ifnum;
+}
+
+/*
+ * nss_nlcapwap_init()
+ *	Init handler for capwap
+ */
+bool nss_nlcapwap_init(void)
+{
+	int err;
+
+	nss_nl_info_always("Init NSS netlink capwap handler\n");
+
+	/*
+	 * Initialize atomic variable
+	 */
+	atomic_set(&global_ctx.enable_perf, 0);
+
+	/*
+	 * Register the capwap netdev rx handler
+	 */
+	global_ctx.capwap_dev = nss_capwapmgr_get_netdev();
+	if (!global_ctx.capwap_dev) {
+		nss_nl_info_always("Failed to find the CAPWAP device\n");
+	}
+
+	/*
+	 * Create a debugfs entry for netlink capwap
+	 */
+	global_ctx.dentry = debugfs_create_dir("nlcapwap", NULL);
+	if (!global_ctx.dentry) {
+		nss_nl_info_always("Cannot create nlcapwap directory\n");
+		return false;
+	}
+
+	if (!debugfs_create_file("stats", 0400, global_ctx.dentry, NULL, &nss_nlcapwap_stats_ops)) {
+		nss_nl_info_always("Cannot create nlcapwap dentry file\n");
+		return false;
+	}
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	err = genl_register_family(&nss_nlcapwap_family);
+	if (err) {
+		nss_nl_info_always("Error: %d unable to register capwap family\n", err);
+		goto free;
+	}
+
+	/*
+	 * register device call back handler for capwap from NSS
+	 */
+	err = nss_capwap_stats_register_notifier(&nss_capwap_stats_notifier_nb);
+	if (err) {
+		nss_nl_info_always("Error: %d unable to register capwap stats notifier\n", err);
+		goto free_family;
+	}
+
+	/*
+	 * Register a netdevice rx handler
+	 */
+	rtnl_lock();
+	err = netdev_rx_handler_register(global_ctx.capwap_dev, nss_nlcapwapmgr_rx_handler, NULL);
+	rtnl_unlock();
+
+	if (err < 0) {
+		nss_nl_error("Couldn't register CAPWAP RX handler\n");
+		goto free_notify;
+	}
+
+	/*
+	 * Initialize the global lock
+	 */
+	rwlock_init(&global_ctx.lock);
+	return true;
+
+free_notify:
+	nss_capwap_stats_unregister_notifier(&nss_capwap_stats_notifier_nb);
+free_family:
+	genl_unregister_family(&nss_nlcapwap_family);
+free:
+	debugfs_remove_recursive(global_ctx.dentry);
+	return false;
+}
+
+/*
+ * nss_nlcapwap_exit()
+ *	Exit handler for capwap
+ */
+bool nss_nlcapwap_exit(void)
+{
+	struct nss_nlcapwap_tunnel *tun;
+	int err;
+	int i;
+
+	nss_nl_info_always("Exit NSS netlink capwap handler\n");
+
+	/*
+	 * unregister the ops family so that we don't receive any new requests
+	 */
+	err = genl_unregister_family(&nss_nlcapwap_family);
+	if (err) {
+		nss_nl_info_always("Error: %d unable to unregister capwap NETLINK family\n", err);
+		return false;
+	}
+
+	/*
+	 * Unregister the capwap netdev rx handler
+	 */
+	if (global_ctx.capwap_dev) {
+		rtnl_lock();
+		netdev_rx_handler_unregister(global_ctx.capwap_dev);
+		rtnl_unlock();
+	}
+
+	/*
+	 * Remove the debugfs entry
+	 */
+	debugfs_remove_recursive(global_ctx.dentry);
+
+	/*
+	 * Destroy all the active tunnels
+	 */
+	for (i = 0; i < NSS_CAPWAPMGR_MAX_TUNNELS; i++) {
+		write_lock_bh(&global_ctx.lock);
+		tun = nss_nlcapwap_get_tun_by_index(i);
+		if (!tun) {
+			write_unlock_bh(&global_ctx.lock);
+			continue;
+		}
+
+		nss_nlcapwap_tun_deinit(tun);
+		clear_bit(i, global_ctx.tun_bitmap);
+		write_unlock_bh(&global_ctx.lock);
+
+		/*
+		 * Destroy the corresponding tunnel
+		 */
+		if (!nss_nlcapwap_destroy_tun(i)) {
+			nss_nl_error("Unable to set the tunnel status to 0 for tun: %d\n", i);
+			continue;
+		}
+	}
+
+	/*
+	 * Unregister the device callback handler for capwap
+	 */
+	nss_capwap_stats_unregister_notifier(&nss_capwap_stats_notifier_nb);
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nlcapwap.h b/qca-nss-clients/netlink/nss_nlcapwap.h
new file mode 100644
index 0000000..53c4bf3
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlcapwap.h
@@ -0,0 +1,57 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, 2018-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlcapwap.h
+ *	NSS Netlink Capwap API definitions
+ */
+#ifndef __NSS_NLCAPWAP_H
+#define __NSS_NLCAPWAP_H
+
+#define NSS_NLCAPWAP_IP_VERS_4 4			/* IP version 4 */
+#define NSS_NLCAPWAP_IP_VERS_6 6			/* IP version 6 */
+#define NSS_NLCAPWAP_VLAN_TAG_INVALID 0xFFF		/* Invalid vlan tag */
+#define NSS_NLCAPWAP_WAN_IFNUM 0			/* WAN interface number */
+#define NSS_NLCAPWAP_DATA 0xcc				/* Dummy data */
+#define NSS_NLCAPWAP_KALIVE_PAYLOAD_SZ 64		/* Capwap+Dtls keepalive packet size */
+#define NSS_NLCAPWAP_KALIVE_TIMER_MSECS 1000		/* Capwap+Dtls keepalive timer */
+#define NSS_NLCAPWAP_STATS_MAX 5			/* Maximum number of stats per tunnel */
+#define NSS_NLCAPWAP_MAX_STR_LEN 96			/* Maximum length of stats string */
+#define NSS_NLCAPWAP_MAX_HEADROOM 128	/* Maximum headroom needed */
+#define NSS_NLCAPWAP_MAX_TAILROOM 192	/* Maximum tailroom needed */
+#define NSS_NLCAPWAP_MAX_TUNNEL_LONGS BITS_TO_LONGS(NSS_CAPWAPMGR_MAX_TUNNELS)
+/*
+ * nss_nlcapwap_meta_header_type
+ *	Capwap meta header type
+ */
+enum nss_nlcapwap_meta_header_type {
+	NSS_NLCAPWAP_META_HEADER_TYPE_UNKNOWN = -1,	/* Unknown meta header type */
+	NSS_NLCAPWAP_META_HEADER_TYPE_IPV4_DATA,	/* capwap meta header type ipv4 */
+	NSS_NLCAPWAP_META_HEADER_TYPE_EAPOL,		/* capwap meta header type eapol */
+	NSS_NLCAPWAP_META_HEADER_TYPE_MAX		/* Max meta header type */
+};
+
+#if (CONFIG_NSS_NLCAPWAP == 1)
+bool nss_nlcapwap_init(void);
+bool nss_nlcapwap_exit(void);
+#define NSS_NLCAPWAP_INIT nss_nlcapwap_init
+#define NSS_NLCAPWAP_EXIT nss_nlcapwap_exit
+#else
+#define NSS_NLCAPWAP_INIT 0
+#define NSS_NLCAPWAP_EXIT 0
+#endif /* !CONFIG_NSS_NLCAPWAP */
+
+#endif /* __NSS_NLCAPWAP_H */
diff --git a/qca-nss-clients/netlink/nss_nldtls.c b/qca-nss-clients/netlink/nss_nldtls.c
new file mode 100644
index 0000000..3db69b8
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nldtls.c
@@ -0,0 +1,1223 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2016,2018-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <crypto/internal/skcipher.h>
+#include <linux/debugfs.h>
+#include <linux/etherdevice.h>
+#include <linux/icmp.h>
+#include <linux/inet.h>
+#include <linux/udp.h>
+#include <linux/version.h>
+#include <net/genetlink.h>
+#include <net/ip6_checksum.h>
+#include <net/udp.h>
+#include <nss_api_if.h>
+#include <nss_dtls.h>
+#include <nss_dtlsmgr.h>
+#include <nss_dtls_cmn.h>
+#include <nss_nlcmn_if.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nldtls.h"
+#include "nss_nldtls_if.h"
+
+/*
+ * prototypes
+ */
+static int nss_nldtls_ops_create_tun(struct sk_buff *skb, struct genl_info *info);
+static int nss_nldtls_ops_destroy_tun(struct sk_buff *skb, struct genl_info *info);
+static int nss_nldtls_ops_update_config(struct sk_buff *skb, struct genl_info *info);
+static int nss_nldtls_ops_tx_pkts(struct sk_buff *skb, struct genl_info *info);
+
+/*
+ * Initializing the global variables
+ */
+static struct nss_nldtls_gbl_ctx gbl_ctx = {
+	.lock = __SPIN_LOCK_UNLOCKED(lock),
+	.num_tun = ATOMIC_INIT(0),
+	.dtls_list_head = LIST_HEAD_INIT(gbl_ctx.dtls_list_head),
+	.log_en = false
+};
+
+/*
+ * nss_nldtls_family_mcgrp
+ *	Multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nldtls_family_mcgrp[] = {
+	{.name = NSS_NLDTLS_MCAST_GRP},
+};
+
+/*
+ * nss_nldtls_ops
+ *	Operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nldtls_ops[] = {
+	{.cmd = NSS_NLDTLS_CMD_TYPE_CREATE_TUN, .doit = nss_nldtls_ops_create_tun,},
+	{.cmd = NSS_NLDTLS_CMD_TYPE_DESTROY_TUN, .doit = nss_nldtls_ops_destroy_tun,},
+	{.cmd = NSS_NLDTLS_CMD_TYPE_UPDATE_CONFIG, .doit = nss_nldtls_ops_update_config,},
+	{.cmd = NSS_NLDTLS_CMD_TYPE_TX_PKTS, .doit = nss_nldtls_ops_tx_pkts,},
+};
+
+/*
+ * nss_nldtls_family
+ *	Dtls family definition
+ */
+struct genl_family nss_nldtls_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,				/* Auto generate ID */
+#endif
+	.name = NSS_NLDTLS_FAMILY,			/* family name string */
+	.hdrsize = sizeof(struct nss_nldtls_rule),	/* NSS NETLINK dtls rule */
+	.version = NSS_NL_VER,				/* Set it to NSS_NLDTLS version */
+	.maxattr = NSS_NLDTLS_CMD_TYPE_MAX,		/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nldtls_ops,
+	.n_ops = ARRAY_SIZE(nss_nldtls_ops),
+	.mcgrps = nss_nldtls_family_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nldtls_family_mcgrp)
+};
+
+/*
+ * nss_nldtls_find_tun_ctx()
+ *	Returns the global context object of a tunnel
+ */
+static struct nss_nldtls_tun_ctx *nss_nldtls_find_tun_ctx(struct net_device *dev)
+{
+	struct nss_nldtls_tun_ctx *entry;
+
+	spin_lock(&gbl_ctx.lock);
+	list_for_each_entry(entry, &gbl_ctx.dtls_list_head, list) {
+		if (!strncmp(entry->dev_name, dev->name, IFNAMSIZ)) {
+			spin_unlock(&gbl_ctx.lock);
+			return entry;
+		}
+	}
+
+	spin_unlock(&gbl_ctx.lock);
+	return NULL;
+}
+
+/*
+ * nss_nldtls_dev_rx_handler()
+ *	Common rx handler for all dtls dev
+ */
+static rx_handler_result_t nss_nldtls_dev_rx_handler(struct sk_buff **pskb)
+{
+	static bool first_pkt;
+	unsigned long long duration;
+	struct sk_buff *skb = *pskb;
+	ktime_t delta;
+
+	if (unlikely(!first_pkt)) {
+		gbl_ctx.first_rx_pkt_time = ktime_get();
+		first_pkt = true;
+	}
+
+	gbl_ctx.last_rx_pkt_time = ktime_get();
+	if (unlikely(gbl_ctx.log_en)) {
+		struct net_device *dev;
+
+		delta = ktime_sub(gbl_ctx.last_rx_pkt_time, gbl_ctx.first_rx_pkt_time);
+		duration = (unsigned long long) ktime_to_ns(delta) >> 10;
+		print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, skb->data, 64);
+		dev = dev_get_by_index(&init_net, skb->skb_iif);
+		if (dev) {
+			nss_nl_info("%px: in_dev = %s, out_dev = %s\n", skb, dev->name, skb->dev->name);
+			dev_put(dev);
+		}
+
+		nss_nl_info("%px: DTLS RX (%s) pkt len = %d udp_csum = %s rx_time: %llu\n", skb,
+				skb->dev->name, skb->len, udp_lib_checksum_complete(skb) ?
+				"invalid" : "valid", duration);
+	}
+
+	dev_kfree_skb_any(skb);
+	return RX_HANDLER_CONSUMED;
+}
+
+/*
+ * nss_nldtls_create_ipv4_rule()
+ *	Create a nss entry to accelerate the given IPv4 connection
+ */
+static int nss_nldtls_create_ipv4_rule(struct nss_ipv4_create *unic, uint16_t rule_flags)
+{
+	struct nss_ipv4_rule_create_msg *nircm;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_ipv4_msg nim;
+	nss_tx_status_t status;
+
+	nss_ctx = nss_ipv4_get_mgr();
+	if (!nss_ctx) {
+		nss_nl_info("%px: Couldn't get IPv4 ctx\n", unic);
+		return -1;
+	}
+
+	nss_nl_info("%px: IPv4 rule: src:%pI4h:%d dst:%pI4h:%d p:%d\n",
+	      unic, &unic->src_ip, unic->src_port,
+	      &unic->dest_ip, unic->dest_port, unic->protocol);
+
+	memset(&nim, 0, sizeof (struct nss_ipv4_msg));
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE,
+			  NSS_IPV4_TX_CREATE_RULE_MSG,
+			  sizeof(struct nss_ipv4_rule_create_msg), NULL, NULL);
+
+	nircm = &nim.msg.rule_create;
+	nircm->valid_flags = 0;
+	nircm->rule_flags = 0;
+
+	/*
+	 * Copy over the 5 tuple details.
+	 */
+	nircm->tuple.protocol = (uint8_t)unic->protocol;
+	nircm->tuple.flow_ip = unic->src_ip;
+	nircm->tuple.flow_ident = (uint32_t)unic->src_port;
+	nircm->tuple.return_ip = unic->dest_ip;
+	nircm->tuple.return_ident = (uint32_t)unic->dest_port;
+
+	/*
+	 * Copy over the connection rules and set the CONN_VALID flag
+	 */
+	nircm->conn_rule.flow_interface_num = unic->src_interface_num;
+	nircm->conn_rule.flow_mtu = unic->from_mtu;
+	nircm->conn_rule.flow_ip_xlate = unic->src_ip_xlate;
+	nircm->conn_rule.flow_ident_xlate = (uint32_t)unic->src_port_xlate;
+	memcpy(nircm->conn_rule.flow_mac, unic->src_mac, 6);
+	nircm->conn_rule.return_interface_num = unic->dest_interface_num;
+	nircm->conn_rule.return_mtu = unic->to_mtu;
+	nircm->conn_rule.return_ip_xlate = unic->dest_ip_xlate;
+	nircm->conn_rule.return_ident_xlate = (uint32_t)unic->dest_port_xlate;
+	if ((nircm->tuple.return_ip != nircm->conn_rule.return_ip_xlate) ||
+	    (nircm->tuple.return_ident != nircm->conn_rule.return_ident_xlate))
+		memcpy(nircm->conn_rule.return_mac, unic->dest_mac_xlate, 6);
+	else
+		memcpy(nircm->conn_rule.return_mac, unic->dest_mac, 6);
+
+	/*
+	 * Copy over the DSCP rule parameters
+	 */
+	if (unic->flags & NSS_IPV4_CREATE_FLAG_DSCP_MARKING) {
+		nircm->dscp_rule.flow_dscp = unic->flow_dscp;
+		nircm->dscp_rule.return_dscp = unic->return_dscp;
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_DSCP_MARKING;
+		nircm->valid_flags |= NSS_IPV4_RULE_CREATE_DSCP_MARKING_VALID;
+	}
+
+	nircm->valid_flags |= NSS_IPV4_RULE_CREATE_CONN_VALID;
+
+	/*
+	 * Copy over the pppoe rules and set the PPPOE_VALID flag.
+	 */
+	nircm->pppoe_rule.flow_if_exist = unic->flow_pppoe_if_exist;
+	nircm->pppoe_rule.flow_if_num = unic->flow_pppoe_if_num;
+	nircm->pppoe_rule.return_if_exist = unic->return_pppoe_if_exist;
+	nircm->pppoe_rule.return_if_num = unic->return_pppoe_if_num;
+	nircm->valid_flags |= NSS_IPV4_RULE_CREATE_PPPOE_VALID;
+
+	/*
+	 * Copy over the vlan rules and set the VLAN_VALID flag
+	 */
+	nircm->vlan_primary_rule.ingress_vlan_tag = unic->in_vlan_tag[0];
+	nircm->vlan_primary_rule.egress_vlan_tag = unic->out_vlan_tag[0];
+	nircm->vlan_secondary_rule.ingress_vlan_tag = unic->in_vlan_tag[1];
+	nircm->vlan_secondary_rule.egress_vlan_tag = unic->out_vlan_tag[1];
+	nircm->valid_flags |= NSS_IPV4_RULE_CREATE_VLAN_VALID;
+
+	/*
+	 * Copy over the qos rules and set the QOS_VALID flag
+	 */
+	nircm->qos_rule.flow_qos_tag = unic->flow_qos_tag;
+	nircm->qos_rule.return_qos_tag = unic->return_qos_tag;
+	nircm->valid_flags |= NSS_IPV4_RULE_CREATE_QOS_VALID;
+
+	if (unic->flags & NSS_IPV4_CREATE_FLAG_NO_SEQ_CHECK)
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_NO_SEQ_CHECK;
+
+	if (unic->flags & NSS_IPV4_CREATE_FLAG_BRIDGE_FLOW)
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_BRIDGE_FLOW;
+
+	if (unic->flags & NSS_IPV4_CREATE_FLAG_ROUTED)
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_ROUTED;
+
+	/*
+	 * Set the flag NSS_IPV4_RULE_CREATE_FLAG_ICMP_NO_CME_FLUSH so that
+	 * rule is not flushed when NSS FW receives ICMP errors/packets.
+	 */
+	nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_ICMP_NO_CME_FLUSH;
+
+	/*
+	 * Add any other additional flags which caller has requested.
+	 * For example: update MTU
+	 */
+	nircm->rule_flags |= rule_flags;
+
+	status = nss_ipv4_tx(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_info("%px: Create IPv4 message failed %d\n", nss_ctx, status);
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nldtls_create_ipv6_rule()
+ *	Create a nss entry to accelerate the given IPV6 connection
+ */
+static int nss_nldtls_create_ipv6_rule(struct nss_ipv6_create *unic, uint16_t rule_flags)
+{
+	struct nss_ipv6_rule_create_msg *nircm;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_ipv6_msg nim;
+	nss_tx_status_t status;
+
+	nss_ctx = nss_ipv6_get_mgr();
+	if (!nss_ctx) {
+		nss_nl_info("%px: Couldn't get IPv6 ctx\n", unic);
+		return -1;
+	}
+
+	nss_nl_info("%px: Create IPv6 rule: %pI6:%d %pI6:%d p:%d\n",
+	      unic, unic->src_ip, unic->src_port, unic->dest_ip,
+	      unic->dest_port, unic->protocol);
+
+	memset(&nim, 0, sizeof (struct nss_ipv6_msg));
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE,
+			  NSS_IPV6_TX_CREATE_RULE_MSG,
+			  sizeof(struct nss_ipv6_rule_create_msg), NULL, NULL);
+
+	nircm = &nim.msg.rule_create;
+	nircm->rule_flags = 0;
+	nircm->valid_flags = 0;
+
+	/*
+	 * Copy over the 5 tuple information.
+	 */
+	nircm->tuple.protocol = (uint8_t)unic->protocol;
+	memcpy(nircm->tuple.flow_ip, unic->src_ip, sizeof(nircm->tuple.flow_ip));
+	memcpy(nircm->tuple.return_ip, unic->dest_ip, sizeof(nircm->tuple.return_ip));
+	nircm->tuple.flow_ident = (uint32_t)unic->src_port;
+	nircm->tuple.return_ident = (uint32_t)unic->dest_port;
+
+	/*
+	 * Copy over the connection rules and set CONN_VALID flag
+	 */
+	nircm->conn_rule.flow_interface_num = unic->src_interface_num;
+	nircm->conn_rule.flow_mtu = unic->from_mtu;
+	nircm->conn_rule.return_interface_num = unic->dest_interface_num;
+	nircm->conn_rule.return_mtu = unic->to_mtu;
+	memcpy(nircm->conn_rule.flow_mac, unic->src_mac, 6);
+	memcpy(nircm->conn_rule.return_mac, unic->dest_mac, 6);
+	nircm->valid_flags |= NSS_IPV6_RULE_CREATE_CONN_VALID;
+
+	/*
+	 * Copy over the DSCP rule parameters
+	 */
+	if (unic->flags & NSS_IPV6_CREATE_FLAG_DSCP_MARKING) {
+		nircm->dscp_rule.flow_dscp = unic->flow_dscp;
+		nircm->dscp_rule.return_dscp = unic->return_dscp;
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_DSCP_MARKING;
+		nircm->valid_flags |= NSS_IPV6_RULE_CREATE_DSCP_MARKING_VALID;
+	}
+
+	/*
+	 * Copy over the pppoe rules and set PPPOE_VALID flag
+	 */
+	nircm->pppoe_rule.flow_if_exist = unic->flow_pppoe_if_exist;
+	nircm->pppoe_rule.flow_if_num = unic->flow_pppoe_if_num;
+	nircm->pppoe_rule.return_if_exist = unic->return_pppoe_if_exist;
+	nircm->pppoe_rule.return_if_num = unic->return_pppoe_if_num;
+	nircm->valid_flags |= NSS_IPV6_RULE_CREATE_PPPOE_VALID;
+
+	/*
+	 * Copy over the tcp rules and set TCP_VALID flag
+	 */
+	nircm->tcp_rule.flow_window_scale = unic->flow_window_scale;
+	nircm->tcp_rule.flow_max_window = unic->flow_max_window;
+	nircm->tcp_rule.flow_end = unic->flow_end;
+	nircm->tcp_rule.flow_max_end = unic->flow_max_end;
+	nircm->tcp_rule.return_window_scale = unic->return_window_scale;
+	nircm->tcp_rule.return_max_window = unic->return_max_window;
+	nircm->tcp_rule.return_end = unic->return_end;
+	nircm->tcp_rule.return_max_end = unic->return_max_end;
+	nircm->valid_flags |= NSS_IPV6_RULE_CREATE_TCP_VALID;
+
+	/*
+	 * Copy over the vlan rules and set the VLAN_VALID flag
+	 */
+	nircm->vlan_primary_rule.egress_vlan_tag = unic->out_vlan_tag[0];
+	nircm->vlan_primary_rule.ingress_vlan_tag = unic->in_vlan_tag[0];
+	nircm->vlan_secondary_rule.egress_vlan_tag = unic->out_vlan_tag[1];
+	nircm->vlan_secondary_rule.ingress_vlan_tag = unic->in_vlan_tag[1];
+	nircm->valid_flags |= NSS_IPV6_RULE_CREATE_VLAN_VALID;
+
+	/*
+	 * Copy over the qos rules and set the QOS_VALID flag
+	 */
+	nircm->qos_rule.flow_qos_tag = unic->flow_qos_tag;
+	nircm->qos_rule.return_qos_tag = unic->return_qos_tag;
+	nircm->valid_flags |= NSS_IPV6_RULE_CREATE_QOS_VALID;
+
+	if (unic->flags & NSS_IPV6_CREATE_FLAG_NO_SEQ_CHECK)
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_NO_SEQ_CHECK;
+
+	if (unic->flags & NSS_IPV6_CREATE_FLAG_BRIDGE_FLOW)
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_BRIDGE_FLOW;
+
+	if (unic->flags & NSS_IPV6_CREATE_FLAG_ROUTED)
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_ROUTED;
+
+	/*
+	 * Set the flag NSS_IPV4_RULE_CREATE_FLAG_ICMP_NO_CME_FLUSH so that
+	 * rule is not flushed when NSS FW receives ICMP errors/packets.
+	 */
+	nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_ICMP_NO_CME_FLUSH;
+
+	/*
+	 * Add any other additional flags which caller has requested.
+	 * For example: update MTU
+	 */
+	nircm->rule_flags |= rule_flags;
+
+	status = nss_ipv6_tx(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_info("%px: Create IPv4 message failed %d\n", nss_ctx, status);
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nldtls_data_callback()
+ *	Data callback function for dtls
+ */
+static void nss_nldtls_data_callback(void *app_data, struct sk_buff *skb)
+{
+	struct nss_dtlsmgr_metadata *ndm;
+	struct nss_nldtls_tun_ctx *tun;
+	struct nss_nldtls_stats *stats;
+	struct net_device *dev;
+
+	dev = dev_get_by_index(&init_net, skb->skb_iif);
+	if (!dev) {
+		nss_nl_error("Unable to get net dev for skb_iif %d\n", skb->skb_iif);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	ndm = (struct nss_dtlsmgr_metadata *)skb->data;
+	tun = nss_nldtls_find_tun_ctx(dev);
+	if (!tun) {
+		nss_nl_error("Unable find tunnel ctx for %s\n", dev->name);
+		dev_put(dev);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	stats = &tun->stats[NSS_NLDTLS_CTYPE_TO_IDX(ndm->ctype)];
+	spin_lock(&gbl_ctx.lock);
+	stats->rx_pkts++;
+	stats->rx_bytes += skb->len - sizeof(*ndm);
+	spin_unlock(&gbl_ctx.lock);
+
+	if (unlikely(gbl_ctx.log_en)) {
+		nss_nl_hex_dump_bytes("", DUMP_PREFIX_OFFSET, skb->data, (skb->len > 64) ? 64 : skb->len);
+	}
+
+	nss_nl_trace("%px Received DTLS packet\n", skb);
+	dev_put(dev);
+	dev_kfree_skb_any(skb);
+}
+
+/*
+ * nss_nldtls_create_session()
+ *	Create a DTLS session through dtlsmgr driver API.
+ */
+static struct net_device *nss_nldtls_create_session(struct nss_nldtls_rule *nl_rule)
+{
+	struct nss_nldtls_tun_ctx *dtls_tun_data;
+	struct nss_dtlsmgr_config dcfg;
+	struct nss_dtlsmgr_ctx *ctx;
+	struct net_device *ndev;
+	uint16_t key_len;
+	uint8_t algo;
+	int err;
+
+	if (atomic_read(&gbl_ctx.num_tun) >= NSS_NLDTLS_MAX_TUNNELS) {
+		nss_nl_error("Max number of tunnels exhausted: 32\n");
+		return NULL;
+	}
+
+	memset(&dcfg, 0, sizeof(struct nss_dtlsmgr_config));
+	algo = nl_rule->msg.create.encap.cfg.crypto.algo;
+	dcfg.flags = nl_rule->msg.create.flags | NSS_DTLSMGR_ENCAP_METADATA;
+	if (algo == NSS_DTLSMGR_ALGO_AES_GCM)
+		dcfg.flags |= NSS_DTLSMGR_CIPHER_MODE_GCM;
+
+	dcfg.app_data = NULL;
+	dcfg.notify = NULL;
+	dcfg.data = nss_nldtls_data_callback;
+
+	/*
+	 * Encap configuration
+	 */
+	key_len = nl_rule->msg.create.encap.cfg.crypto.cipher_key.len;
+	if (key_len > NSS_NLDTLS_CIPHER_KEY_MAX) {
+		nss_nl_error("Invalid cipher length: %u\n", key_len);
+		return NULL;
+	}
+
+	key_len = nl_rule->msg.create.encap.cfg.crypto.auth_key.len;
+	if (key_len > NSS_NLDTLS_AUTH_KEY_MAX) {
+		nss_nl_error("Invalid authentication length: %u\n", key_len);
+		return NULL;
+	}
+
+	key_len = nl_rule->msg.create.encap.cfg.crypto.nonce.len;
+	if (key_len > NSS_NLDTLS_NONCE_SIZE_MAX) {
+		nss_nl_error("Invalid nonce length: %u\n", key_len);
+		return NULL;
+	}
+
+	nl_rule->msg.create.encap.cfg.crypto.cipher_key.data = nl_rule->msg.create.encap.keys.cipher;
+	nl_rule->msg.create.encap.cfg.crypto.auth_key.data = nl_rule->msg.create.encap.keys.auth;
+	nl_rule->msg.create.encap.cfg.crypto.nonce.data = nl_rule->msg.create.encap.keys.nonce;
+	memcpy((void *)&dcfg.encap, (void *)&nl_rule->msg.create.encap.cfg, sizeof(struct nss_dtlsmgr_encap_config));
+
+	/*
+	 * Decap configuration
+	 */
+	key_len = nl_rule->msg.create.decap.cfg.crypto.cipher_key.len;
+	if (key_len > NSS_NLDTLS_CIPHER_KEY_MAX) {
+		nss_nl_error("Invalid cipher length: %u\n", key_len);
+		return NULL;
+	}
+
+	key_len = nl_rule->msg.create.decap.cfg.crypto.auth_key.len;
+	if (key_len > NSS_NLDTLS_AUTH_KEY_MAX) {
+		nss_nl_error("Invalid authentication length: %u\n", key_len);
+		return NULL;
+	}
+
+	key_len = nl_rule->msg.create.decap.cfg.crypto.nonce.len;
+	if (key_len > NSS_NLDTLS_NONCE_SIZE_MAX) {
+		nss_nl_error("Invalid nonce length: %u\n", key_len);
+		return NULL;
+	}
+
+	nl_rule->msg.create.decap.cfg.crypto.cipher_key.data = nl_rule->msg.create.decap.keys.cipher;
+	nl_rule->msg.create.decap.cfg.crypto.auth_key.data = nl_rule->msg.create.decap.keys.auth;
+	nl_rule->msg.create.decap.cfg.crypto.nonce.data = nl_rule->msg.create.decap.keys.nonce;
+	memcpy((void *)&dcfg.decap, (void *)&nl_rule->msg.create.decap.cfg, sizeof(struct nss_dtlsmgr_decap_config));
+	dcfg.decap.nexthop_ifnum = NSS_N2H_INTERFACE;
+
+	/*
+	 * Create a dtls session
+	 */
+	ndev = nss_dtlsmgr_session_create(&dcfg);
+	if (!ndev) {
+		nss_nl_error("Failed to create DTLS session\n");
+		return NULL;
+	}
+
+	ctx = netdev_priv(ndev);
+	/*
+	 * Register rx handler for dtls netdev
+	 */
+	rtnl_lock();
+	err = netdev_rx_handler_register(ndev, nss_nldtls_dev_rx_handler, 0);
+	if (err) {
+		rtnl_unlock();
+		nss_dtlsmgr_session_destroy(ndev);
+		nss_nl_error("%px: Failed to register rx handler\n", ctx);
+		return NULL;
+	}
+
+	rtnl_unlock();
+
+	/*
+	 * Prepare data for current tunnel
+	 */
+	dtls_tun_data = (struct nss_nldtls_tun_ctx *)kmalloc(sizeof(*dtls_tun_data), GFP_KERNEL);
+	dtls_tun_data->nl_rule = nl_rule;
+	memcpy(dtls_tun_data->dev_name, ndev->name, IFNAMSIZ);
+	memset(&dtls_tun_data->stats, 0, sizeof(dtls_tun_data->stats));
+
+	/*
+	 * Adding tunnel to global list of tunnels
+	 */
+	spin_lock(&gbl_ctx.lock);
+	list_add_tail(&dtls_tun_data->list, &gbl_ctx.dtls_list_head);
+	spin_unlock(&gbl_ctx.lock);
+
+	nss_nl_info("%px: Succesfully created dtls session.\n", ctx);
+	return ndev;
+}
+
+/*
+ * nss_nldtls_create_ipv4_rule_entry()
+ *	Handler for adding ipv4 rule entry for dtls session
+ */
+static int nss_nldtls_create_ipv4_rule_entry(struct net_device *dtls_dev, struct nss_nldtls_rule *nl_rule)
+{
+	struct nss_ipv4_create ipv4;
+	struct net_device *ndev;
+	uint32_t if_num;
+
+	/*
+	 * Configure IPv4 rule
+	 */
+	memset(&ipv4, 0, sizeof(struct nss_ipv4_create));
+
+	ipv4.from_mtu = nl_rule->msg.create.from_mtu;
+	ipv4.to_mtu = nl_rule->msg.create.to_mtu;
+
+	ndev = dev_get_by_name(&init_net, &nl_rule->msg.create.gmac_ifname[0]);
+	if (ndev == NULL) {
+		nss_nl_error("Can't find %s netdev\n", nl_rule->msg.create.gmac_ifname);
+		return -EINVAL;
+	}
+
+	if_num = nss_cmn_get_interface_number_by_dev(ndev);
+	ipv4.src_interface_num = if_num;
+	ipv4.dest_interface_num = nss_dtlsmgr_get_interface(dtls_dev, NSS_DTLSMGR_INTERFACE_TYPE_OUTER);
+
+	ipv4.src_port = nl_rule->msg.create.encap.cfg.dport;
+	ipv4.src_port_xlate = nl_rule->msg.create.encap.cfg.dport;
+	ipv4.src_ip = nl_rule->msg.create.encap.cfg.dip[0];
+	ipv4.src_ip_xlate = nl_rule->msg.create.encap.cfg.dip[0];
+
+	ipv4.dest_ip = nl_rule->msg.create.encap.cfg.sip[0];
+	ipv4.dest_ip_xlate = nl_rule->msg.create.encap.cfg.sip[0];
+	ipv4.dest_port = nl_rule->msg.create.encap.cfg.sport;
+	ipv4.dest_port_xlate = nl_rule->msg.create.encap.cfg.sport;
+
+	if (nl_rule->msg.create.flags & NSS_DTLSMGR_HDR_UDPLITE)
+		ipv4.protocol = IPPROTO_UDPLITE;
+	else
+		ipv4.protocol = IPPROTO_UDP;
+
+	ipv4.in_vlan_tag[0] = NSS_NLDTLS_VLAN_INVALID;
+	ipv4.out_vlan_tag[0] = NSS_NLDTLS_VLAN_INVALID;
+	ipv4.in_vlan_tag[1] = NSS_NLDTLS_VLAN_INVALID;
+	ipv4.out_vlan_tag[1] = NSS_NLDTLS_VLAN_INVALID;
+
+	memcpy(&ipv4.src_mac[0], &nl_rule->msg.create.gmac_ifmac[0], sizeof(ipv4.src_mac));
+
+	/*
+	 * Create an ipv4 rule entry
+	 */
+	return nss_nldtls_create_ipv4_rule(&ipv4, 0);
+}
+
+/*
+ * nss_nldtls_create_ipv6_rule_entry()
+ *	Handler to add an ipv6 rule entry for dtls session
+ */
+static int nss_nldtls_create_ipv6_rule_entry(struct net_device *dtls_dev, struct nss_nldtls_rule *nl_rule)
+{
+	struct nss_ipv6_create ipv6;
+	struct net_device *ndev;
+	uint32_t if_num;
+
+	/*
+	 * Configure IPv6 rule
+	 */
+	memset(&ipv6, 0, sizeof(struct nss_ipv6_create));
+
+	ipv6.from_mtu = nl_rule->msg.create.from_mtu;
+	ipv6.to_mtu = nl_rule->msg.create.to_mtu;
+
+	ndev = dev_get_by_name(&init_net, &nl_rule->msg.create.gmac_ifname[0]);
+	if (ndev == NULL) {
+		nss_nl_error("Can't find %s netdev\n", nl_rule->msg.create.gmac_ifname);
+		return -EINVAL;
+	}
+
+	if_num = nss_cmn_get_interface_number_by_dev(ndev);
+	ipv6.src_interface_num = if_num;
+	ipv6.dest_interface_num = nss_dtlsmgr_get_interface(dtls_dev, NSS_DTLSMGR_INTERFACE_TYPE_OUTER);
+	ipv6.src_port = nl_rule->msg.create.encap.cfg.dport;
+	ipv6.dest_port = nl_rule->msg.create.encap.cfg.sport;
+
+	/*
+	 * Configure IPv6 rule
+	 */
+	memcpy(ipv6.src_ip, nl_rule->msg.create.encap.cfg.dip, sizeof(ipv6.src_ip));
+	memcpy(ipv6.dest_ip, nl_rule->msg.create.encap.cfg.sip, sizeof(ipv6.dest_ip));
+
+	if (nl_rule->msg.create.flags & NSS_DTLSMGR_HDR_UDPLITE)
+		ipv6.protocol = IPPROTO_UDPLITE;
+	else
+		ipv6.protocol = IPPROTO_UDP;
+
+	ipv6.in_vlan_tag[0] = NSS_NLDTLS_VLAN_INVALID;
+	ipv6.in_vlan_tag[1] = NSS_NLDTLS_VLAN_INVALID;
+	ipv6.out_vlan_tag[1] = NSS_NLDTLS_VLAN_INVALID;
+	ipv6.out_vlan_tag[0] = NSS_NLDTLS_VLAN_INVALID;
+
+	memcpy(&ipv6.src_mac[0], &nl_rule->msg.create.gmac_ifmac[0], sizeof(ipv6.src_mac));
+
+	/*
+	 * Create an ipv6 rule entry
+	 */
+	return nss_nldtls_create_ipv6_rule(&ipv6, 0);
+}
+
+/*
+ * nss_nldtls_destroy_tun()
+ *	Common handler for tunnel destroy
+ */
+static int nss_nldtls_destroy_tun(struct net_device *dev)
+{
+	struct nss_nldtls_tun_ctx *tun;
+
+	tun = nss_nldtls_find_tun_ctx(dev);
+	if (!tun) {
+		nss_nl_error("Unable to find context of the tunnel: %s\n", dev->name);
+		return -EAGAIN;
+	}
+
+	/*
+	 * Delete tunnel node from the list
+	 */
+	list_del_init(&tun->list);
+	kfree(tun);
+
+	/*
+	 * Destroy the dtls session
+	 */
+	if (nss_dtlsmgr_session_destroy(dev)) {
+		nss_nl_error("Unable to destroy the tunnel: %s\n", dev->name);
+		return -EAGAIN;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nldtls_ops_create_tun()
+ *	Handler for creating tunnel
+ */
+static int nss_nldtls_ops_create_tun(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nldtls_rule *nl_rule;
+	struct net_device *dtls_dev;
+	struct nss_nlcmn *nl_cm;
+	int ret = 0;
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nldtls_family, info, NSS_NLDTLS_CMD_TYPE_CREATE_TUN);
+	if (!nl_cm) {
+		nss_nl_error("%px: Unable to extract create tunnel data\n", skb);
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nldtls_rule, cm);
+
+	/*
+	 * Create tunnel based on ip version
+	 */
+	if (nl_rule->msg.create.ip_version == NSS_NLDTLS_IP_VERS_4) {
+		dtls_dev = nss_nldtls_create_session(nl_rule);
+		if (!dtls_dev) {
+			nss_nl_error("%px: Unable to create dtls session for v4\n", skb);
+			return -EINVAL;
+		}
+
+		/*
+		 * Create IPv4 rule entry
+		 */
+		ret = nss_nldtls_create_ipv4_rule_entry(dtls_dev, nl_rule);
+		if (ret < 0) {
+			nss_nldtls_destroy_tun(dtls_dev);
+			nss_nl_error("%px Unable to add a rule entry for ipv4.\n", skb);
+			return -EAGAIN;
+		}
+
+		atomic_inc(&gbl_ctx.num_tun);
+		nss_nl_info("%px: Successfully created ipv4 dtls tunnel\n", skb);
+	} else {
+		dtls_dev = nss_nldtls_create_session(nl_rule);
+		if (!dtls_dev) {
+			nss_nl_error("%px: Unable to create dtls session for v6\n", skb);
+			return -EINVAL;
+		}
+
+		/*
+		 * Create IPv6 rule entry
+		 */
+		ret = nss_nldtls_create_ipv6_rule_entry(dtls_dev, nl_rule);
+		if (ret < 0) {
+			nss_nldtls_destroy_tun(dtls_dev);
+			nss_nl_error("%px: Unable to add a rule entry for ipv6.\n", skb);
+			return -EAGAIN;
+		}
+
+		atomic_inc(&gbl_ctx.num_tun);
+		nss_nl_info("%px: Successfully created ipv6 dtls tunnel\n", skb);
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nldtls_ops_destroy_tun()
+ *	Handler to destroy tunnel
+ */
+static int nss_nldtls_ops_destroy_tun(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nldtls_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	struct net_device *dev;
+	int ret;
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nldtls_family, info, NSS_NLDTLS_CMD_TYPE_DESTROY_TUN);
+	if (!nl_cm) {
+		nss_nl_error("%px: Unable to extract destroy tunnel data\n", skb);
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nldtls_rule, cm);
+
+	dev = dev_get_by_name(&init_net, nl_rule->msg.destroy.dev_name);
+	if (!dev) {
+		nss_nl_error("%px Unable to find dev: %s\n", skb, nl_rule->msg.destroy.dev_name);
+		return -EINVAL;
+	}
+
+	dev_put(dev);
+
+	/*
+	 * Common dtls handler for tunnel destroy
+	 */
+	ret = nss_nldtls_destroy_tun(dev);
+	if (ret < 0) {
+		nss_nl_error("%px Unable to destroy tunnel: %s\n", skb, dev->name);
+		return -EAGAIN;
+	}
+
+	atomic_dec(&gbl_ctx.num_tun);
+	nss_nl_info("%px: Successfully destroyed dtls session: %s\n", skb, nl_rule->msg.destroy.dev_name);
+	return 0;
+}
+
+/*
+ * nss_nldtls_ops_update_config()
+ *	Handler for updating configuration command
+ */
+static int nss_nldtls_ops_update_config(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_dtlsmgr_config_update dcfg;
+	struct nss_nldtls_rule *nl_rule;
+	struct nss_nldtls_tun_ctx *tun;
+	struct nss_dtlsmgr_ctx *ctx;
+	nss_dtlsmgr_status_t status;
+	struct nss_nlcmn *nl_cm;
+	struct net_device *dev;
+	uint16_t key_len;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nldtls_family, info, NSS_NLDTLS_CMD_TYPE_UPDATE_CONFIG);
+	if (!nl_cm) {
+		nss_nl_error("%px: Unable to extract update_config data.\n", skb);
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nldtls_rule, cm);
+
+	dev = dev_get_by_name(&init_net, nl_rule->msg.update_config.dev_name);
+	if (!dev) {
+		nss_nl_error("%px Unable to find dev: %s\n", skb, nl_rule->msg.update_config.dev_name);
+		return -EINVAL;
+	}
+
+	ctx = netdev_priv(dev);
+	tun = nss_nldtls_find_tun_ctx(dev);
+	if (!tun) {
+		nss_nl_error("%px Unable to find context of the tunnel: %s\n", ctx, dev->name);
+		dev_put(dev);
+		return -EAGAIN;
+	}
+
+	/*
+	 * Configure the dtls configuration
+	 */
+	dcfg.crypto.algo = nl_rule->msg.update_config.config_update.crypto.algo;
+	dcfg.crypto.cipher_key.data = nl_rule->msg.update_config.keys.cipher;
+	dcfg.crypto.auth_key.data = nl_rule->msg.update_config.keys.auth;
+	dcfg.crypto.nonce.data = nl_rule->msg.update_config.keys.nonce;
+	key_len = nl_rule->msg.update_config.config_update.crypto.cipher_key.len;
+	if (key_len > NSS_NLDTLS_CIPHER_KEY_MAX) {
+		nss_nl_error("Invalid cipher length: %u\n", key_len);
+		return -EINVAL;
+	}
+
+	dcfg.crypto.cipher_key.len = key_len;
+	key_len = nl_rule->msg.update_config.config_update.crypto.auth_key.len;
+	if (key_len > NSS_NLDTLS_AUTH_KEY_MAX) {
+		nss_nl_error("Invalid authentication length: %u\n", key_len);
+		return -EINVAL;
+	}
+
+	dcfg.crypto.auth_key.len = key_len;
+	key_len = nl_rule->msg.update_config.config_update.crypto.nonce.len;
+	if (key_len > NSS_NLDTLS_NONCE_SIZE_MAX) {
+		nss_nl_error("Invalid nonce length: %u\n", key_len);
+		return -EINVAL;
+	}
+
+	dcfg.crypto.nonce.len = key_len;
+	dcfg.epoch = nl_rule->msg.update_config.config_update.epoch;
+	dcfg.window_size = nl_rule->msg.update_config.config_update.window_size;
+	if (!nl_rule->msg.update_config.dir) {
+		status = nss_dtlsmgr_session_update_encap(dev, &dcfg);
+		if (status != NSS_DTLSMGR_OK) {
+			nss_nl_error("%px Unable to update encap configuration\n", ctx);
+			dev_put(dev);
+			return -EINVAL;
+		}
+
+		nss_nl_info("%px: Successfully update the encap configuration\n", ctx);
+	} else {
+		status = nss_dtlsmgr_session_update_decap(dev, &dcfg);
+		if (status != NSS_DTLSMGR_OK) {
+			nss_nl_error("%px Unable to update decap configuration\n", ctx);
+			dev_put(dev);
+			return -EINVAL;
+		}
+
+		nss_nl_info("%px: Successfully update the decap configuration\n", ctx);
+	}
+
+	/*
+	 * Update the tun data configuration
+	 */
+	tun->nl_rule = nl_rule;
+	dev_put(dev);
+	return 0;
+}
+
+/*
+ * nss_nldtls_alloc_pkt()
+ *	Handler for forming ctype packet
+ */
+static struct sk_buff *nss_nldtls_alloc_pkt(struct nss_nldtls_rule *nl_rule,
+			struct net_device *dev, uint32_t pkt_sz, uint8_t ctype)
+{
+	struct nss_dtlsmgr_metadata *ndm;
+	uint16_t hdr_len, payload_len;
+	struct sk_buff *skb;
+
+	hdr_len = dev->needed_headroom + sizeof(*ndm);
+	payload_len = hdr_len + dev->needed_tailroom + pkt_sz;
+	skb = netdev_alloc_skb(dev, payload_len);
+	if (!skb) {
+		return NULL;
+	}
+
+	skb_reserve(skb, hdr_len);
+
+	/*
+	 * Fill the packet with dummy data
+	 */
+	memset(skb_put(skb, pkt_sz), NSS_NLDTLS_DUMMY_DATA, skb->len);
+
+	ndm = nss_dtlsmgr_metadata_init(skb);
+	nss_dtlsmgr_metadata_set_seq(ndm, nl_rule->msg.tx_pkts.seq_num);
+	nss_dtlsmgr_metadata_set_ctype(ndm, ctype);
+
+	if (unlikely(nl_rule->msg.tx_pkts.log_en)) {
+		nss_nl_info("%px DTLS TX pkt len:%u\n", skb, skb->len);
+	}
+
+	return skb;
+}
+
+/*
+ * nss_nldtls_ops_tx_pkts()
+ *	Handler for sending traffic
+ */
+static int nss_nldtls_ops_tx_pkts(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nldtls_rule *nl_rule;
+	struct nss_nldtls_tun_ctx *tun;
+	struct nss_nldtls_stats *stats;
+	unsigned long long duration;
+	struct nss_nlcmn *nl_cm;
+	struct net_device *dev;
+	struct sk_buff *tx_skb;
+	uint32_t num_pkts;
+	uint32_t pkt_sz;
+	uint32_t count;
+	ktime_t delta;
+	uint8_t ctype;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nldtls_family, info, NSS_NLDTLS_CMD_TYPE_TX_PKTS);
+	if (!nl_cm) {
+		nss_nl_error("%px: Unable to extract tx_pkts data\n", skb);
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nldtls_rule, cm);
+
+	ctype = nl_rule->msg.tx_pkts.ctype;
+	num_pkts = nl_rule->msg.tx_pkts.num_pkts;
+
+	switch (ctype) {
+	case NSS_DTLSMGR_METADATA_CTYPE_CCS:
+		pkt_sz = NSS_NLDTLS_CCS_PKT_SZ;
+		break;
+
+	case NSS_DTLSMGR_METADATA_CTYPE_ALERT:
+		pkt_sz = NSS_NLDTLS_ALERT_PKT_SZ;
+		break;
+
+	case NSS_DTLSMGR_METADATA_CTYPE_HANDSHAKE:
+		pkt_sz = NSS_NLDTLS_HANDSHAKE_PKT_SZ;
+		break;
+
+	case NSS_DTLSMGR_METADATA_CTYPE_APP:
+		pkt_sz = nl_rule->msg.tx_pkts.pkt_sz;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	dev = dev_get_by_name(&init_net, nl_rule->msg.tx_pkts.dev_name);
+	if (!dev) {
+		nss_nl_error("%px Unable to find dev: %s\n", skb, nl_rule->msg.tx_pkts.dev_name);
+		return -EINVAL;
+	}
+
+	tun = nss_nldtls_find_tun_ctx(dev);
+	if (!tun) {
+		nss_nl_error("%px Unable to find context of the tunnel: %s\n", skb, dev->name);
+		dev_put(dev);
+		return -EINVAL;
+	}
+
+	spin_lock(&gbl_ctx.lock);
+	gbl_ctx.log_en = nl_rule->msg.tx_pkts.log_en;
+	spin_unlock(&gbl_ctx.lock);
+
+	gbl_ctx.first_tx_pkt_time = ktime_get();
+
+	for (count = 0; count < num_pkts; count++) {
+		tx_skb = nss_nldtls_alloc_pkt(nl_rule, dev, pkt_sz, ctype);
+		if (!tx_skb) {
+			nss_nl_error("%px Failed to allocate skb\n", dev);
+			break;
+		}
+
+		dev->netdev_ops->ndo_start_xmit(tx_skb, dev);
+	}
+
+	stats = &tun->stats[NSS_NLDTLS_CTYPE_TO_IDX(ctype)];
+	spin_lock(&gbl_ctx.lock);
+	stats->tx_pkts += count;
+	stats->tx_bytes += (count * pkt_sz);
+	spin_unlock(&gbl_ctx.lock);
+	dev_put(dev);
+
+	if (count != num_pkts) {
+		nss_nl_error("%px Error in transmission\n", skb);
+		return -EAGAIN;
+	}
+
+	gbl_ctx.last_tx_pkt_time = ktime_get();
+	delta = ktime_sub(gbl_ctx.last_tx_pkt_time, gbl_ctx.first_tx_pkt_time);
+	duration = (unsigned long long) ktime_to_ns(delta) >> 10;
+	nss_nl_info("%px Packets sent in %llu usecs", dev, duration);
+	nss_nl_info("%px Traffic transmission successful\n", skb);
+	return 0;
+}
+
+/*
+ * nss_nldtls_tunnel_stats_read()
+ *	reads the per tunnel tx and rx packets stats for every ctypes
+ */
+static ssize_t nss_nldtls_tunnel_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *f_ppos)
+{
+	struct nss_nldtls_stats stats[NSS_NLDTLS_CTYPE_MAX];
+	struct nss_nldtls_tun_ctx *entry;
+	uint32_t max_output_lines;
+	char dev_name[IFNAMSIZ];
+	ssize_t bytes_read = 0;
+	ssize_t size_wr = 0;
+	ssize_t size_al;
+	char *lbuf;
+
+	max_output_lines = 2 + (NSS_NLDTLS_MAX_TUNNELS * NSS_NLDTLS_STATS_MAX_ROW);
+	size_al = NSS_NLDTLS_STATS_MAX_STR_LEN * max_output_lines;
+
+	lbuf = vzalloc(size_al);
+
+	if (!lbuf) {
+		nss_nl_error("%px Could not allocate buffer for debug entry\n", f_ppos);
+		return 0;
+	}
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nDTLS netlink ctype stats:\n");
+	list_for_each_entry(entry, &gbl_ctx.dtls_list_head, list) {
+		spin_lock_bh(&gbl_ctx.lock);
+		memcpy(&stats, &entry->stats, sizeof(stats));
+		strlcpy(dev_name, entry->dev_name, IFNAMSIZ);
+		spin_unlock_bh(&gbl_ctx.lock);
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n--------------------------------");
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n%s:\t %s", "dev", dev_name);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n change_cipher_spec");
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "tx_pkts", stats[0].tx_pkts);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "tx_bytes", stats[0].tx_bytes);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "rx_pkts", stats[0].rx_pkts);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "rx_bytes", stats[0].rx_bytes);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n alert");
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "tx_pkts", stats[1].tx_pkts);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "tx_bytes", stats[1].tx_bytes);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "rx_pkts", stats[1].rx_pkts);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "rx_bytes", stats[1].rx_bytes);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n handshake");
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "tx_pkts", stats[2].tx_pkts);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "tx_bytes", stats[2].tx_bytes);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "rx_pkts", stats[2].rx_pkts);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "rx_bytes", stats[2].rx_bytes);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n app_data");
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "tx_pkts", stats[3].tx_pkts);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "tx_bytes", stats[3].tx_bytes);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "rx_pkts", stats[3].rx_pkts);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\t%s:\t %llu", "rx_bytes", stats[3].rx_bytes);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n--------------------------------\n");
+	}
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nDTLS netlink ctype stats end\n\n");
+	bytes_read = simple_read_from_buffer(ubuf, sz, f_ppos, lbuf, size_wr);
+
+	vfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_nldtls_stats_ops()
+ *	file operation handler for dentry
+ */
+static const struct file_operations nss_nldtls_stats_ops = {
+	.read = nss_nldtls_tunnel_stats_read,
+};
+
+/*
+ * nss_nldtls_init()
+ *	Init handler for dtls
+ */
+bool nss_nldtls_init(void)
+{
+	int err;
+
+	nss_nl_info_always("Init NSS netlink dtls handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	err = genl_register_family(&nss_nldtls_family);
+	if (err) {
+		nss_nl_info_always("Error: %d unable to register gre_redir family\n", err);
+		genl_unregister_family(&nss_nldtls_family);
+		return false;
+	}
+
+	/*
+	 * Create a debugfs entry for netlink dtls
+	 */
+	gbl_ctx.dentry = debugfs_create_dir("nldtls", NULL);
+	if (!gbl_ctx.dentry) {
+		nss_nl_info_always("Cannot create nldtls directory\n");
+		goto free_family;
+	}
+
+	if (!debugfs_create_file("stats", 0400, gbl_ctx.dentry, NULL, &nss_nldtls_stats_ops)) {
+		nss_nl_info_always("Cannot create nldtls dentry file\n");
+		goto free_debugfs;
+	}
+
+	return true;
+
+free_debugfs:
+	debugfs_remove_recursive(gbl_ctx.dentry);
+free_family:
+	genl_unregister_family(&nss_nldtls_family);
+
+	return false;
+}
+
+/*
+ * nss_nldtls_exit()
+ *	Exit handler for dtls
+ */
+bool nss_nldtls_exit(void)
+{
+	struct nss_nldtls_tun_ctx *entry, *tmp;
+	struct net_device *dev;
+	int err;
+
+	nss_nl_info_always("Exit NSS netlink dtls handler\n");
+
+	/*
+	 * Destroy all active tunnel before exiting
+	 */
+	list_for_each_entry_safe(entry, tmp, &gbl_ctx.dtls_list_head, list) {
+		dev = dev_get_by_name(&init_net, entry->dev_name);
+		if (dev) {
+			dev_put(dev);
+			nss_nldtls_destroy_tun(dev);
+		}
+	}
+
+	nss_nl_info_always("All active tunnels destroyed\n");
+
+	/*
+	 * unregister the ops family
+	 */
+	err = genl_unregister_family(&nss_nldtls_family);
+	if (err) {
+		nss_nl_info_always("Error: %d unable to unregister dtls NETLINK family\n", err);
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nldtls.h b/qca-nss-clients/netlink/nss_nldtls.h
new file mode 100644
index 0000000..920f557
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nldtls.h
@@ -0,0 +1,89 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015,2018-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nldtls.h
+ *	NSS Netlink Dtls API definitions
+ */
+#ifndef __NSS_NLDTLS_H
+#define __NSS_NLDTLS_H
+
+#define NSS_NLDTLS_SKB_TAILROOM 192
+#define NSS_NLDTLS_IPV4_SESSION 0
+#define NSS_NLDTLS_MAX_TUNNELS 32
+#define NSS_NLDTLS_VLAN_INVALID 0xFFF
+#define NSS_NLDTLS_IP_VERS_4 4
+#define NSS_NLDTLS_DUMMY_DATA 0xcc
+#define NSS_NLDTLS_STATS_MAX_ROW 23
+#define NSS_NLDTLS_STATS_MAX_STR_LEN 35
+
+#define NSS_NLDTLS_CTYPE_MAX 4
+#define NSS_NLDTLS_CTYPE_BASE	NSS_DTLSMGR_METADATA_CTYPE_CCS
+#define NSS_NLDTLS_CTYPE_TO_IDX(ctype)	((ctype) - NSS_NLDTLS_CTYPE_BASE)
+
+#define NSS_NLDTLS_CCS_PKT_SZ 1
+#define NSS_NLDTLS_ALERT_PKT_SZ 2
+#define NSS_NLDTLS_HANDSHAKE_PKT_SZ 56
+
+/*
+ * nss_dtls_stats
+ *	netlink DTLS TX and RX statistics
+ */
+struct nss_nldtls_stats {
+	uint64_t rx_pkts;
+	uint64_t rx_bytes;
+	uint64_t tx_pkts;
+	uint64_t tx_bytes;
+};
+
+/*
+ * nss_nldtls_tun_ctx
+ *	Per dtls tunnel context
+ */
+struct nss_nldtls_tun_ctx {
+	struct list_head list;			/**< List for holding different tunnel info */
+	struct nss_nldtls_rule *nl_rule;	/**< Dtls rule structure */
+	char dev_name[IFNAMSIZ];		/**< Dtls session netdev */
+	struct nss_nldtls_stats stats[NSS_NLDTLS_CTYPE_MAX];
+						/**< Dtls stats */
+};
+
+/*
+ * nss_nldtls_gbl_ctx
+ *	Global context for dtls
+ */
+struct nss_nldtls_gbl_ctx {
+	spinlock_t lock;
+	atomic_t num_tun;
+	struct list_head dtls_list_head;
+	bool log_en;
+	ktime_t first_rx_pkt_time;
+	ktime_t first_tx_pkt_time;
+	ktime_t last_rx_pkt_time;
+	ktime_t last_tx_pkt_time;
+	struct dentry *dentry;
+};
+
+#if (CONFIG_NSS_NLDTLS == 1)
+bool nss_nldtls_init(void);
+bool nss_nldtls_exit(void);
+#define NSS_NLDTLS_INIT nss_nldtls_init
+#define NSS_NLDTLS_EXIT nss_nldtls_exit
+#else
+#define NSS_NLDTLS_INIT 0
+#define NSS_NLDTLS_EXIT 0
+#endif /* !CONFIG_NSS_NLDTLS */
+#endif /* __NSS_NLDTLS_H */
diff --git a/qca-nss-clients/netlink/nss_nldynamic_interface.c b/qca-nss-clients/netlink/nss_nldynamic_interface.c
new file mode 100644
index 0000000..fbd3dd4
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nldynamic_interface.c
@@ -0,0 +1,178 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nldynamic_interface.c
+ *      NSS Netlink dynamic interface Handler
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/notifier.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nldynamic_interface_if.h"
+#include "nss_dynamic_interface.h"
+
+/*
+ * prototypes
+ */
+static int nss_nldynamic_interface_ops_get_stats(struct sk_buff *skb, struct genl_info *info);
+static int nss_nldynamic_interface_process_notify(struct notifier_block *nb, unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nldynamic_interface_mcgrp[] = {
+	{.name = NSS_NLDYNAMIC_INTERFACE_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nldynamic_interface_ops[] = {
+	{.cmd = NSS_STATS_EVENT_NOTIFY, .doit = nss_nldynamic_interface_ops_get_stats},
+};
+
+/*
+ * dynamic interface family definition
+ */
+static struct genl_family nss_nldynamic_interface_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,					/* Auto generate ID */
+#endif
+	.name = NSS_NLDYNAMIC_INTERFACE_FAMILY,			/* family name string */
+	.hdrsize = sizeof(struct nss_dynamic_interface_notification),	/* NSS NETLINK dynamic interface information */
+	.version = NSS_NL_VER,					/* Set it to NSS_NLDYNAMIC_INTERFACE version */
+	.maxattr = NSS_STATS_EVENT_MAX,				/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nldynamic_interface_ops,
+	.n_ops = ARRAY_SIZE(nss_nldynamic_interface_ops),
+	.mcgrps = nss_nldynamic_interface_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nldynamic_interface_mcgrp)
+};
+
+/*
+ * destroy interface call back handler for dynamic interface from NSS
+ */
+static struct notifier_block nss_dynamic_interface_stats_notifier_nb = {
+	.notifier_call = nss_nldynamic_interface_process_notify,
+};
+
+/*
+ * nss_nldynamic_interface_ops_get_stats()
+ *	get stats handler
+ */
+static int nss_nldynamic_interface_ops_get_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+/*
+ * nss_nldynamic_interface_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nldynamic_interface_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct sk_buff *skb;
+	struct nss_dynamic_interface_notification *nss_notification, *nl_notification;
+
+	nss_notification = (struct nss_dynamic_interface_notification *)data;
+	skb = nss_nl_new_msg(&nss_nldynamic_interface_family, NSS_NLCMN_SUBSYS_DYNAMIC_INTERFACE);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLDYNAMIC_INTERFACE event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_notification = nss_nl_get_data(skb);
+	memcpy(nl_notification, nss_notification, sizeof(struct nss_dynamic_interface_notification));
+	nss_nl_mcast_event(&nss_nldynamic_interface_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nldynamic_interface_init()
+ *	handler init
+ */
+bool nss_nldynamic_interface_init(void)
+{
+	int error,ret;
+
+	nss_nl_info_always("Init NSS netlink dynamic_interface handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nldynamic_interface_family);
+	if (error) {
+		nss_nl_info_always("Error: unable to register dynamic_interface family\n");
+		return false;
+	}
+
+	/*
+	 * register device call back handler for dynamic interface from NSS
+	 */
+	ret = nss_dynamic_interface_stats_register_notifier(&nss_dynamic_interface_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context \n");
+		genl_unregister_family(&nss_nldynamic_interface_family);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nldynamic_interface_exit()
+ *	handler exit
+ */
+bool nss_nldynamic_interface_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink dynamic_interface handler\n");
+
+	/*
+	 * Unregister the device callback handler for dynamic interface
+	 */
+	nss_dynamic_interface_stats_unregister_notifier(&nss_dynamic_interface_stats_notifier_nb);
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nldynamic_interface_family);
+	if (error) {
+		nss_nl_info_always("unable to unregister dynamic_interface NETLINK family\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nldynamic_interface.h b/qca-nss-clients/netlink/nss_nldynamic_interface.h
new file mode 100644
index 0000000..10bf740
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nldynamic_interface.h
@@ -0,0 +1,37 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nldynamic_interface.h
+ *      NSS Netlink dynamic_interface API definitions
+ */
+#ifndef __NSS_NLDYNAMIC_INTERFACE_H
+#define __NSS_NLDYNAMIC_INTERFACE_H
+
+bool nss_nldynamic_interface_init(void);
+bool nss_nldynamic_interface_exit(void);
+
+#if defined(CONFIG_NSS_NLDYNAMIC_INTERFACE)
+#define NSS_NLDYNAMIC_INTERFACE_INIT nss_nldynamic_interface_init
+#define NSS_NLDYNAMIC_INTERFACE_EXIT nss_nldynamic_interface_exit
+#else
+#define NSS_NLDYNAMIC_INTERFACE_INIT 0
+#define NSS_NLDYNAMIC_INTERFACE_EXIT 0
+#endif /* !CONFIG_NSS_NLDYNAMIC_INTERFACE */
+
+#endif /* __NSS_NLDYNAMIC_INTERFACE_H */
diff --git a/qca-nss-clients/netlink/nss_nledma.c b/qca-nss-clients/netlink/nss_nledma.c
new file mode 100644
index 0000000..d784c0b
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nledma.c
@@ -0,0 +1,183 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nledma.c
+ *	NSS Netlink Edma Handler
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netlink.h>
+#include <linux/vmalloc.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nledma_if.h"
+#include "nss_edma.h"
+
+/*
+ * prototypes
+ */
+static int nss_nledma_ops_get_stats(struct sk_buff *skb, struct genl_info *info);
+static int nss_nledma_process_notify(struct notifier_block *nb, unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nledma_mcgrp[] = {
+	{.name = NSS_NLEDMA_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nledma_ops[] = {
+	{.cmd = NSS_STATS_EVENT_NOTIFY, .doit = nss_nledma_ops_get_stats,},
+};
+
+/*
+ * Edma family definition
+ */
+static struct genl_family nss_nledma_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,				/* Auto generate ID */
+#endif
+	.name = NSS_NLEDMA_FAMILY,			/* family name string */
+	.hdrsize = sizeof(struct nss_nledma_stats),	/* NSS NETLINK Edma stats */
+	.version = NSS_NL_VER,				/* Set it to NSS_NLEDMA version */
+	.maxattr = NSS_STATS_EVENT_MAX,			/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nledma_ops,
+	.n_ops = ARRAY_SIZE(nss_nledma_ops),
+	.mcgrps = nss_nledma_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nledma_mcgrp)
+};
+
+/*
+ * statistics call back handler for edma from NSS
+ */
+static struct notifier_block nss_edma_stats_notifier_nb = {
+	.notifier_call = nss_nledma_process_notify,
+};
+
+#define NSS_NLEDMA_OPS_SZ ARRAY_SIZE(nss_nledma_ops)
+
+/*
+ * nss_nledma_ops_get_stats()
+ *	get stats handler
+ */
+static int nss_nledma_ops_get_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+/*
+ * nss_nledma_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nledma_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct nss_nledma_stats *stats;
+	struct sk_buff *skb;
+	int id;
+
+	for (id = 0 ; id < NSS_EDMA_NUM_PORTS_MAX; id++) {
+		skb = nss_nl_new_msg(&nss_nledma_family, NSS_NLCMN_SUBSYS_EDMA);
+		if (!skb) {
+			nss_nl_error("unable to allocate NSS_NLEDMA event\n");
+			return NOTIFY_DONE;
+		}
+
+		stats = nss_nl_get_data(skb);
+		nss_edma_get_stats(stats->cmn_node_stats,id);
+		stats->core_id = *(uint32_t *)data;
+		stats->port_id = id;
+		nss_nl_mcast_event(&nss_nledma_family, skb);
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nledma_init()
+ *	handler init
+ */
+bool nss_nledma_init(void)
+{
+	int error, ret;
+
+	nss_nl_info_always("Init NSS netlink Edma handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nledma_family);
+	if (error) {
+		nss_nl_info_always("Error: unable to register Edma family\n");
+		return false;
+	}
+
+	/*
+	 * register device call back handler for edma from NSS
+	 */
+	ret = nss_edma_stats_register_notifier(&nss_edma_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context\n");
+		genl_unregister_family(&nss_nledma_family);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nledma_exit()
+ *	handler exit
+ */
+bool nss_nledma_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink Edma handler\n");
+
+	/*
+	 * Unregister the device callback handler for edma
+	 */
+	nss_edma_stats_unregister_notifier(&nss_edma_stats_notifier_nb);
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nledma_family);
+	if (error) {
+		nss_nl_info_always("unable to unregister Edma NETLINK family\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nledma.h b/qca-nss-clients/netlink/nss_nledma.h
new file mode 100644
index 0000000..746c1ab
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nledma.h
@@ -0,0 +1,37 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nledma.h
+ *      NSS Netlink Edma API definitions
+ */
+#ifndef __NSS_NLEDMA_H
+#define __NSS_NLEDMA_H
+
+#if (CONFIG_NSS_NLEDMA == 1)
+bool nss_nledma_init(void);
+bool nss_nledma_exit(void);
+
+#define NSS_NLEDMA_INIT nss_nledma_init
+#define NSS_NLEDMA_EXIT nss_nledma_exit
+#else
+#define NSS_NLEDMA_INIT 0
+#define NSS_NLEDMA_EXIT 0
+#endif /* !CONFIG_NSS_NLEDMA */
+
+#endif /* __NSS_NLEDMA_H */
diff --git a/qca-nss-clients/netlink/nss_nlethrx.c b/qca-nss-clients/netlink/nss_nlethrx.c
new file mode 100644
index 0000000..e9a5daf
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlethrx.c
@@ -0,0 +1,178 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlethrx.c
+ *	NSS Netlink eth_rx Handler
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nlethrx_if.h"
+#include "nss_eth_rx.h"
+
+/*
+ * prototypes
+ */
+static int nss_nlethrx_ops_get_stats(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlethrx_process_notify(struct notifier_block *nb, unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nlethrx_mcgrp[] = {
+	{.name = NSS_NLETHRX_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nlethrx_ops[] = {
+	{.cmd = NSS_STATS_EVENT_NOTIFY, .doit = nss_nlethrx_ops_get_stats,},
+};
+
+/*
+ * eth_rx family definition
+ */
+static struct genl_family nss_nlethrx_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,						/* Auto generate ID */
+#endif
+	.name = NSS_NLETHRX_FAMILY,					/* family name string */
+	.hdrsize = sizeof(struct nss_eth_rx_stats_notification),	/* NSS NETLINK eth_rx rule */
+	.version = NSS_NL_VER,						/* Set it to NSS_NLETHRX version */
+	.maxattr = NSS_STATS_EVENT_MAX,					/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nlethrx_ops,
+	.n_ops = ARRAY_SIZE(nss_nlethrx_ops),
+	.mcgrps = nss_nlethrx_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nlethrx_mcgrp)
+};
+
+/*
+ * statistics call back handler for eth_rx from NSS
+ */
+static struct notifier_block nss_eth_rx_stats_notifier_nb = {
+	.notifier_call = nss_nlethrx_process_notify,
+};
+
+/*
+ * nss_nlethrx_ops_get_stats()
+ *	get stats handler
+ */
+static int nss_nlethrx_ops_get_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+/*
+ * nss_nlethrx_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nlethrx_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct sk_buff *skb;
+	struct nss_eth_rx_stats_notification *nl_stats, *nss_stats;
+
+	skb = nss_nl_new_msg(&nss_nlethrx_family, NSS_NLCMN_SUBSYS_ETHRX);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLETHRX event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_stats = nss_nl_get_data(skb);
+	nss_stats = (struct nss_eth_rx_stats_notification *)data;
+	memcpy(nl_stats, nss_stats, sizeof(struct nss_eth_rx_stats_notification));
+	nss_nl_mcast_event(&nss_nlethrx_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nlethrx_init()
+ *	handler init
+ */
+bool nss_nlethrx_init(void)
+{
+	int error,ret;
+
+	nss_nl_info_always("Init NSS netlink eth_rx handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nlethrx_family);
+	if (error) {
+		nss_nl_info_always("Error: unable to register eth_rx family\n");
+		return false;
+	}
+
+	/*
+	 * register device call back handler for ethrx from NSS
+	 */
+	ret = nss_eth_rx_stats_register_notifier(&nss_eth_rx_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context \n");
+		genl_unregister_family(&nss_nlethrx_family);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nlethrx_exit()
+ *	handler exit
+ */
+bool nss_nlethrx_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink eth_rx handler\n");
+
+	/*
+	 * Unregister the device callback handler for ethrx
+	 */
+	nss_eth_rx_stats_unregister_notifier(&nss_eth_rx_stats_notifier_nb);
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nlethrx_family);
+	if (error) {
+		nss_nl_info_always("unable to unregister eth_rx NETLINK family\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nlethrx.h b/qca-nss-clients/netlink/nss_nlethrx.h
new file mode 100644
index 0000000..1081034
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlethrx.h
@@ -0,0 +1,37 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlethrx.h
+ *      NSS Netlink eth_rx API definitions
+ */
+#ifndef __NSS_NLETHRX_H
+#define __NSS_NLETHRX_H
+
+bool nss_nlethrx_init(void);
+bool nss_nlethrx_exit(void);
+
+#if defined(CONFIG_NSS_NLETHRX)
+#define NSS_NLETHRX_INIT nss_nlethrx_init
+#define NSS_NLETHRX_EXIT nss_nlethrx_exit
+#else
+#define NSS_NLETHRX_INIT 0
+#define NSS_NLETHRX_EXIT 0
+#endif /* !CONFIG_NSS_NLETHRX */
+
+#endif /* __NSS_NLETHRX_H */
diff --git a/qca-nss-clients/netlink/nss_nlgre_redir.c b/qca-nss-clients/netlink/nss_nlgre_redir.c
new file mode 100644
index 0000000..9ffc93b
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlgre_redir.c
@@ -0,0 +1,173 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2015-2016,2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/etherdevice.h>
+#include <linux/if_ether.h>
+#include <net/genetlink.h>
+#include <nss_api_if.h>
+#include <nss_nl_if.h>
+#include "nss_nlcmn_if.h"
+#include "nss_nl.h"
+#include "nss_nlgre_redir_if.h"
+#include "nss_nlgre_redir_cmn.h"
+#include "nss_nlgre_redir.h"
+
+/*
+ * nss_nlgre_redir_destroy_tun()
+ * 	Destroys the gre_redir tunnel
+ */
+int nss_nlgre_redir_destroy_tun(struct net_device *dev)
+{
+	int ret;
+
+	if (!dev) {
+		nss_nl_error("Dev is NULL\n");
+		return -EINVAL;
+	}
+
+	ret = nss_nlgre_redir_cmn_destroy_tun(dev);
+	if (ret < 0) {
+		nss_nl_error("Could not destroy the tunnel\n");
+		return -EINVAL;
+	}
+
+	nss_nl_info("Successfully destroyed the tunnel\n");
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_create_tun()
+ * 	Creates a gre_redir tunnel
+ */
+int nss_nlgre_redir_create_tun(struct nss_nlgre_redir_create_tun *create_params)
+{
+	struct net_device *dev;
+
+	if (!create_params) {
+		nss_nl_error("create_params is NULL\n");
+		return -EINVAL;
+	}
+
+	dev = nss_nlgre_redir_cmn_create_tun(create_params->sip, create_params->dip, create_params->iptype);
+	if (!dev) {
+		nss_nl_error("Could not create tunnel\n");
+		return -EINVAL;
+	}
+
+	nss_nl_info("Successfully created the tunnel = %s\n", dev->name);
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_map_interface()
+ * 	Maps the nss interface to the tunnel ID
+ */
+int nss_nlgre_redir_map_interface(struct nss_nlgre_redir_map *map_params)
+{
+	struct nss_ctx_instance *nss_ctx;
+	uint32_t nexthop_nssif, vap_nss_if;
+	uint8_t tun_type;
+	int ret;
+
+	if (!map_params) {
+		nss_nl_error("map params is NULL\n");
+		return -EINVAL;
+	}
+
+	nss_ctx = nss_gre_redir_get_context();
+	vap_nss_if = nss_nlgre_redir_cmn_get_dev_ifnum(map_params->vap_nss_if);
+
+	/*
+	 * Get tunnel type from tun_type string
+	 */
+	tun_type = nss_nlgre_redir_cmn_get_tun_type(map_params->tun_type);
+	switch(tun_type) {
+	case NSS_NLGRE_REDIR_TUN_TYPE_DTUN:
+	case NSS_NLGRE_REDIR_TUN_TYPE_TUN:
+		nexthop_nssif = vap_nss_if;
+		break;
+	case NSS_NLGRE_REDIR_TUN_TYPE_SPLIT:
+		nexthop_nssif = NSS_ETH_RX_INTERFACE;
+		break;
+	default:
+		nss_nl_error("%px: not a valid tunnel_type\n", nss_ctx);
+		return -1;
+	}
+
+	/*
+	 * Map the nss interface
+	 */
+	ret = nss_nlgre_redir_cmn_map_interface(nexthop_nssif, 0, map_params);
+	if (ret == -1) {
+		nss_nl_error("%px: Unable to map nss interface\n", nss_ctx);
+		return -1;
+	}
+
+	nss_nl_info("Successfully mapped the nss interface to tunnel ID\n");
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_set_next_hop()
+ * 	Sets the next hop of vap as wifi_offld_inner interface of gre_redir node
+ */
+int nss_nlgre_redir_set_next_hop(struct nss_nlgre_redir_set_next *set_next_params)
+{
+	enum nss_nlgre_redir_cmn_mode_type mode;
+	struct nss_ctx_instance *nss_ctx;
+	struct net_device *next_dev;
+	uint32_t nexthop_ifnum;
+	int ret;
+
+	if (!set_next_params) {
+		nss_nl_error("set next params is NULL\n");
+		return -EINVAL;
+	}
+
+	nss_ctx = nss_gre_redir_get_context();
+	next_dev = dev_get_by_name(&init_net, set_next_params->next_dev_name);
+	if (!next_dev) {
+		nss_nl_error("%px: Unable to get the reference to dev %s\n", nss_ctx, set_next_params->next_dev_name);
+		return -1;
+	}
+
+	dev_put(next_dev);
+	mode = nss_nlgre_redir_cmn_mode_str_to_enum(set_next_params->mode);
+	switch(mode) {
+	case NSS_NLGRE_REDIR_CMN_MODE_TYPE_WIFI:
+		/*
+		 * Gets the wifi_offl_inner_ifnum interface number of gretun[index]
+		 */
+		nexthop_ifnum = nss_nlgre_redir_cmn_get_tun_ifnum(NSS_NLGRE_REDIR_CMN_MODE_TYPE_WIFI, next_dev);
+		break;
+	case NSS_NLGRE_REDIR_CMN_MODE_TYPE_SPLIT:
+		nexthop_ifnum = NSS_ETH_RX_INTERFACE;
+		break;
+	default:
+		nss_nl_error("%px: Unknown set next mode\n", nss_ctx);
+		return -1;
+	}
+
+	ret = nss_nlgre_redir_cmn_set_next_hop(nexthop_ifnum, set_next_params);
+	if (ret == -1) {
+		nss_nl_error("%px: Unable to set the next hop\n", nss_ctx);
+		return -1;
+	}
+
+	nss_nl_info("Successfully set the next hop\n");
+	return 0;
+}
diff --git a/qca-nss-clients/netlink/nss_nlgre_redir.h b/qca-nss-clients/netlink/nss_nlgre_redir.h
new file mode 100644
index 0000000..16ab737
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlgre_redir.h
@@ -0,0 +1,54 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2014-2015,2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#define NSS_NLGRE_REDIR_MODE_MAX_SZ 16		/**< Max size of mode value */
+
+/*
+ * nss_nlgre_redir_tun_type
+ * 	Different tunnel types supported in gre_redir
+ */
+enum nss_nlgre_redir_tun_type {
+	NSS_NLGRE_REDIR_TUN_TYPE_UNKNOWN,		/**< Unknown tunnel type */
+	NSS_NLGRE_REDIR_TUN_TYPE_TUN,			/**< Raw mode 802.11 frames traffic*/
+	NSS_NLGRE_REDIR_TUN_TYPE_DTUN,			/**< For 802.3 frames traffic */
+	NSS_NLGRE_REDIR_TUN_TYPE_SPLIT,			/**< For split mode */
+	NSS_NLGRE_REDIR_TUN_TYPE_MAX			/**< Max number of tun type supported */
+};
+
+/*
+ * nss_nlgre_redir_map_interface()
+ * 	Interface map message.
+ */
+int nss_nlgre_redir_map_interface(struct nss_nlgre_redir_map *map_params);
+
+/*
+ * nss_nlgre_redir_set_next_hop()
+ * 	Sets next hop as gre-redir for wifi.
+ */
+int nss_nlgre_redir_set_next_hop(struct nss_nlgre_redir_set_next *setnext_params);
+
+/*
+ * nss_nlgre_redir_create_tun()
+ * 	Unregisters and deallocs dynamic interfaces.
+ */
+int nss_nlgre_redir_create_tun(struct nss_nlgre_redir_create_tun *create_params);
+
+/*
+ * nss_nlgre_redir_destroy_tun()
+ * 	Destroy tunnel in tunnel mode.
+ */
+int nss_nlgre_redir_destroy_tun(struct net_device *dev);
+
diff --git a/qca-nss-clients/netlink/nss_nlgre_redir_cmd.c b/qca-nss-clients/netlink/nss_nlgre_redir_cmd.c
new file mode 100644
index 0000000..8538267
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlgre_redir_cmd.c
@@ -0,0 +1,518 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2016,2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlgre_redir.c
+ * 	NSS Netlink gre_redir Handler
+ */
+#include <linux/version.h>
+#include <net/genetlink.h>
+#include <nss_api_if.h>
+#include <nss_nlcmn_if.h>
+#include <nss_nl_if.h>
+#include <nss_nlgre_redir_if.h>
+#include "nss_nl.h"
+#include "nss_nlgre_redir.h"
+#include "nss_nlgre_redir_cmd.h"
+#include "nss_nlgre_redir_cmn.h"
+#include "nss_nlgre_redir_lag.h"
+#include "nss_nlipv6_if.h"
+#include "nss_nlipv4_if.h"
+
+/*
+ * To get lock on deploy_mode
+ */
+static DEFINE_SPINLOCK(lock);
+
+/*
+ * Variable to keep track of mode we are operating
+ */
+static enum nss_nlgre_redir_cmd_deploy_mode deploy_mode;
+
+/*
+ * prototypes
+ */
+static int nss_nlgre_redir_cmd_ops_tun_create(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlgre_redir_cmd_ops_tun_destroy(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlgre_redir_cmd_ops_map(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlgre_redir_cmd_ops_unmap(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlgre_redir_cmd_ops_set_next(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlgre_redir_cmd_ops_add_hash(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlgre_redir_cmd_ops_del_hash(struct sk_buff *skb, struct genl_info *info);
+
+/*
+ * nss_nlgre_redir_cmd_mcgrp
+ *	Multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nlgre_redir_family_mcgrp[] = {
+         {.name = NSS_NLGRE_REDIR_MCAST_GRP},
+};
+
+/*
+ * nss_nlgre_redir_ops
+ * 	Operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nlgre_redir_ops[] = {
+	{.cmd = NSS_NLGRE_REDIR_CMD_TYPE_CREATE_TUN, .doit = nss_nlgre_redir_cmd_ops_tun_create,},
+	{.cmd = NSS_NLGRE_REDIR_CMD_TYPE_DESTROY_TUN, .doit = nss_nlgre_redir_cmd_ops_tun_destroy,},
+	{.cmd = NSS_NLGRE_REDIR_CMD_TYPE_MAP, .doit = nss_nlgre_redir_cmd_ops_map,},
+	{.cmd = NSS_NLGRE_REDIR_CMD_TYPE_UNMAP, .doit = nss_nlgre_redir_cmd_ops_unmap,},
+	{.cmd = NSS_NLGRE_REDIR_CMD_TYPE_SET_NEXT_HOP, .doit = nss_nlgre_redir_cmd_ops_set_next,},
+	{.cmd = NSS_NLGRE_REDIR_CMD_TYPE_ADD_HASH, .doit = nss_nlgre_redir_cmd_ops_add_hash,},
+	{.cmd = NSS_NLGRE_REDIR_CMD_TYPE_DEL_HASH, .doit = nss_nlgre_redir_cmd_ops_del_hash,},
+};
+
+/*
+ * nss_nlgre_redir_cmd_family
+ * 	Gre_redir family definition
+ */
+struct genl_family nss_nlgre_redir_cmd_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,				/* Auto generate ID */
+#endif
+	.name = NSS_NLGRE_REDIR_FAMILY,			/* family name string */
+	.hdrsize = sizeof(struct nss_nlgre_redir_rule),	/* NSS NETLINK gre_redir rule */
+	.version = NSS_NL_VER,				/* Set it to NSS_NLGRE_REDIR version */
+	.maxattr = NSS_NLGRE_REDIR_CMD_TYPE_MAX,	/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nlgre_redir_ops,
+	.n_ops = ARRAY_SIZE(nss_nlgre_redir_ops),
+	.mcgrps = nss_nlgre_redir_family_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nlgre_redir_family_mcgrp)
+};
+
+/*
+ * nss_nlgre_redir_cmd_get_deploy_mode()
+ * 	Returns deploy_mode value
+ */
+static inline enum nss_nlgre_redir_cmd_deploy_mode nss_nlgre_redir_cmd_get_deploy_mode(void)
+{
+	enum nss_nlgre_redir_cmd_deploy_mode ret_deploy_mode;
+	spin_lock(&lock);
+	ret_deploy_mode = deploy_mode;
+	spin_unlock(&lock);
+	return ret_deploy_mode;
+}
+
+/*
+ * nss_nlgre_redir_cmd_set_deploy_mode()
+ * 	Sets the value of deploy_mode to parameter passed
+ */
+static inline void nss_nlgre_redir_cmd_set_deploy_mode(enum nss_nlgre_redir_cmd_deploy_mode param_deploy_mode)
+{
+	spin_lock(&lock);
+	deploy_mode = param_deploy_mode;
+	spin_unlock(&lock);
+}
+
+/*
+ * nss_nlgre_redir_cmd_ops_tun_create()
+ * 	Handler for tunnel create
+ */
+static int nss_nlgre_redir_cmd_ops_tun_create(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nlgre_redir_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	int ret = 0;
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlgre_redir_cmd_family, info, NSS_NLGRE_REDIR_CMD_TYPE_CREATE_TUN);
+	if (!nl_cm) {
+		nss_nl_error("Unable to extract create tunnel data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlgre_redir_rule, cm);
+
+	/*
+	 * Create tunnel based on value of lag_enable
+	 */
+	if (!nl_rule->msg.create.lag_enable) {
+		nss_nlgre_redir_cmd_set_deploy_mode(NSS_NLGRE_REDIR_CMD_DEPLOY_MODE_NON_LAG);
+		ret = nss_nlgre_redir_create_tun(&nl_rule->msg.create);
+		if (ret < 0) {
+			nss_nl_error("Unable to create tunnel\n");
+			return -EAGAIN;
+		}
+
+		goto done;
+	}
+
+	/*
+	 * Create a lag tunnel
+	 */
+	nss_nlgre_redir_cmd_set_deploy_mode(NSS_NLGRE_REDIR_CMD_DEPLOY_MODE_LAG);
+	ret = nss_nlgre_redir_lag_create_tun(&nl_rule->msg.create);
+	if (ret < 0) {
+		nss_nl_error("Unable to create lag tunnel\n");
+		return -EAGAIN;
+	}
+done:
+	nss_nl_info("Successfully created tunnel\n");
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_cmd_ops_tun_destroy()
+ * 	Handler to destroy tunnel
+ */
+static int nss_nlgre_redir_cmd_ops_tun_destroy(struct sk_buff *skb, struct genl_info *info)
+{
+	enum nss_nlgre_redir_cmd_deploy_mode deploy_mode;
+	struct nss_nlgre_redir_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	struct net_device *dev;
+	int ret = 0;
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlgre_redir_cmd_family, info, NSS_NLGRE_REDIR_CMD_TYPE_DESTROY_TUN);
+	if (!nl_cm) {
+		nss_nl_error("Unable to extract destroy tunnel data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlgre_redir_rule, cm);
+
+	/*
+	 * Get the dev reference
+	 */
+	dev = dev_get_by_name(&init_net, nl_rule->msg.destroy.netdev);
+	if (!dev) {
+		nss_nl_error("Invalid parameters: %s\n", nl_rule->msg.destroy.netdev);
+		return -ENODEV;
+	}
+
+	dev_put(dev);
+
+	/*
+	 * Destroy the non-lag tunnel
+	 */
+	deploy_mode = nss_nlgre_redir_cmd_get_deploy_mode();
+	if (deploy_mode != NSS_NLGRE_REDIR_CMD_DEPLOY_MODE_LAG) {
+		ret = nss_nlgre_redir_destroy_tun(dev);
+		if (ret < 0) {
+			nss_nl_error("Unable to destroy tunnel: %s\n", nl_rule->msg.destroy.netdev);
+			dev_put(dev);
+			return -EAGAIN;
+		}
+
+		goto done;
+	}
+
+	/*
+	 * Destroy the lag tunnel
+	 */
+	ret = nss_nlgre_redir_lag_destroy_tun(dev);
+	if (ret < 0) {
+		nss_nl_error("Unable to destroy tunnel: %s\n", nl_rule->msg.destroy.netdev);
+		dev_put(dev);
+		return -EAGAIN;
+	}
+
+done:
+	nss_nl_info("Successfully destroyed gretun = %s tunnel\n", nl_rule->msg.destroy.netdev);
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_cmd_ops_map()
+ * 	Handler for map command
+ */
+static int nss_nlgre_redir_cmd_ops_map(struct sk_buff *skb, struct genl_info *info)
+{
+	enum nss_nlgre_redir_cmd_deploy_mode deploy_mode;
+	struct nss_nlgre_redir_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	int ret = 0;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlgre_redir_cmd_family, info, NSS_NLGRE_REDIR_CMD_TYPE_MAP);
+	if (!nl_cm) {
+		nss_nl_error("Unable to extract map interface data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlgre_redir_rule, cm);
+
+	/*
+	 * Map the interface
+	 */
+	deploy_mode = nss_nlgre_redir_cmd_get_deploy_mode();
+	if (deploy_mode != NSS_NLGRE_REDIR_CMD_DEPLOY_MODE_LAG) {
+		ret = nss_nlgre_redir_map_interface(&nl_rule->msg.map);
+		if(ret < 0) {
+			nss_nl_error("Unable to map nss interface\n");
+			return -EAGAIN;
+		}
+
+		goto done;
+	}
+
+	ret = nss_nlgre_redir_lag_map_interface(&nl_rule->msg.map);
+	if (ret < 0) {
+		nss_nl_error("Unable to map nss interface\n");
+		return -EAGAIN;
+	}
+done:
+	nss_nl_info("Successfully mapped nss interface.\n");
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_cmd_ops_unmap()
+ * 	Handler for unmap command
+ */
+static int nss_nlgre_redir_cmd_ops_unmap(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nlgre_redir_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	int ret = 0;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlgre_redir_cmd_family, info, NSS_NLGRE_REDIR_CMD_TYPE_UNMAP);
+	if (!nl_cm) {
+		nss_nl_error("Unable to extract unmap data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlgre_redir_rule, cm);
+
+	/*
+	 * Unmap the interface
+	 */
+	ret = nss_nlgre_redir_cmn_unmap_interface(&nl_rule->msg.unmap);
+	if(ret < 0) {
+		nss_nl_error("Unable to unmap nss interface\n");
+		return -EAGAIN;
+	}
+
+	nss_nl_info("Successfully unmapped the nss interface.\n");
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_cmd_ops_set_next()
+ * 	Handler for set_next command
+ */
+static int nss_nlgre_redir_cmd_ops_set_next(struct sk_buff *skb, struct genl_info *info)
+{
+	enum nss_nlgre_redir_cmd_deploy_mode deploy_mode;
+	struct nss_nlgre_redir_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	int ret = 0;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlgre_redir_cmd_family, info, NSS_NLGRE_REDIR_CMD_TYPE_SET_NEXT_HOP);
+	if (!nl_cm) {
+		nss_nl_error("Unable to extract set_next_hop data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlgre_redir_rule, cm);
+
+	/*
+	 * Set the next hop of ath0 as wifi_offld_inner of gre_redir node
+	 */
+	deploy_mode = nss_nlgre_redir_cmd_get_deploy_mode();
+	if (deploy_mode != NSS_NLGRE_REDIR_CMD_DEPLOY_MODE_LAG) {
+		ret = nss_nlgre_redir_set_next_hop(&nl_rule->msg.snext);
+		if (ret < 0) {
+			nss_nl_error("Unable to set next hop\n");
+			return -EAGAIN;
+		}
+
+		goto done;
+	}
+
+	/*
+	 * Set the next hop of ath0 as lag US node's inner interface
+	 */
+	ret = nss_nlgre_redir_lag_set_next_hop(&nl_rule->msg.snext);
+	if (ret < 0) {
+		nss_nl_error("Unable to set the next hop\n");
+		return -EAGAIN;
+	}
+
+done:
+	nss_nl_info("Successfully set the next hop\n");
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_cmd_ops_add_hash()
+ * 	Handler for adding hash a value
+ */
+static int nss_nlgre_redir_cmd_ops_add_hash(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nlgre_redir_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	int ret;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlgre_redir_cmd_family, info, NSS_NLGRE_REDIR_CMD_TYPE_ADD_HASH);
+	if (!nl_cm) {
+		nss_nl_error("Unable to add a new hash value.\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlgre_redir_rule, cm);
+	ret = nss_nlgre_redir_lag_add_hash(&nl_rule->msg.hash_ops);
+	if(ret < 0) {
+		nss_nl_error("Unable to add hash value.\n");
+		return -EINVAL;
+	}
+
+	nss_nl_info("Successfully added a hash value.\n");
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_cmd_ops_del_hash()
+ * 	Handler for deleting a hash value
+ */
+static int nss_nlgre_redir_cmd_ops_del_hash(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nlgre_redir_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	int ret;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlgre_redir_cmd_family, info, NSS_NLGRE_REDIR_CMD_TYPE_DEL_HASH);
+	if (!nl_cm) {
+		nss_nl_error("Unable to delete the hash value.\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlgre_redir_rule, cm);
+
+	/*
+	 * Delete hash value corresponding to smac and dmac
+	 */
+	ret = nss_nlgre_redir_lag_del_hash(&nl_rule->msg.hash_ops);
+	if(ret < 0) {
+		nss_nl_error("Unable to delete hash value.\n");
+		return -EINVAL;
+	}
+
+	nss_nl_info("Successfully deleted the hash entry.\n");
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_cmd_get_ifnum()
+ * 	Get the interface number corresponding to netdev
+ */
+int nss_nlgre_redir_cmd_get_ifnum(struct net_device *dev, uint8_t proto)
+{
+	enum nss_dynamic_interface_type type;
+	int ifnum;
+
+	switch (proto) {
+	case IPPROTO_TCP:
+	case IPPROTO_UDP:
+	case IPPROTO_UDPLITE:
+		type = NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_OFFL_INNER;
+		break;
+	case IPPROTO_GRE:
+		type = NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_OUTER;
+		break;
+	default:
+		nss_nl_error("Invalid protocol %d\n", proto);
+		return -1;
+	}
+
+	/*
+	 * Get the interface number depending upon the dev and type
+	 */
+	ifnum = nss_cmn_get_interface_number_by_dev_and_type(dev, type);
+	if (ifnum < 0) {
+		nss_nl_error("%px: Failed to find interface number (dev:%s, type:%d)\n", dev, dev->name, type);
+		return -1;
+	}
+
+	return ifnum;
+}
+
+/*
+ * nss_nlgre_redir_cmd_get_mtu()
+ * 	Returns the mtu based on the device passed
+ */
+int nss_nlgre_redir_cmd_get_mtu(struct net_device *dev, uint8_t iptype, int ifnum)
+{
+	enum nss_dynamic_interface_type type;
+	struct nss_ctx_instance *nss_ctx;
+	int mtu = dev->mtu;
+
+	nss_ctx = nss_gre_redir_get_context();
+	type = nss_dynamic_interface_get_type(nss_ctx, ifnum);
+	switch (iptype) {
+	case NSS_GRE_REDIR_IP_HDR_TYPE_IPV4:
+		if (type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_OUTER) {
+			mtu = NSS_NLIPV4_MAX_MTU;
+		} else if (mtu < NSS_NLIPV4_MIN_MTU) {
+			mtu = NSS_NLIPV4_MIN_MTU;
+		}
+
+		break;
+	case NSS_GRE_REDIR_IP_HDR_TYPE_IPV6:
+		if (type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_OUTER) {
+			mtu = NSS_NLIPV6_MAX_MTU;
+		} else if (mtu < NSS_NLIPV6_MIN_MTU) {
+			mtu = NSS_NLIPV6_MIN_MTU;
+		}
+
+		break;
+	}
+
+	return mtu;
+}
diff --git a/qca-nss-clients/netlink/nss_nlgre_redir_cmd.h b/qca-nss-clients/netlink/nss_nlgre_redir_cmd.h
new file mode 100644
index 0000000..e59bcab
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlgre_redir_cmd.h
@@ -0,0 +1,52 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015,2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlgre_redir_cmd.h
+ *	NSS Netlink gre_redir API definitions
+ */
+#ifndef __NSS_NLGRE_REDIR_CMD_H
+#define __NSS_NLGRE_REDIR_CMD_H
+#define NSS_NLGRE_REDIR_CMD_MAX 7
+/*
+ * nss_nlgre_redir_cmd_deploy_mode
+ * 	Gre_redir deployment mode types
+ */
+enum nss_nlgre_redir_cmd_deploy_mode {
+	NSS_NLGRE_REDIR_CMD_DEPLOY_MODE_UNKNOWN,			/**< Invalid mode */
+	NSS_NLGRE_REDIR_CMD_DEPLOY_MODE_NON_LAG,			/**< Basic tunnel mode */
+	NSS_NLGRE_REDIR_CMD_DEPLOY_MODE_LAG,				/**< Lag mode */
+	NSS_NLGRE_REDIR_CMD_DEPLOY_MODE_MAX				/**< Maximum deploy mode */
+};
+
+/*
+ * To keep track of family operations
+ */
+extern struct genl_family nss_nlgre_redir_cmd_family;
+
+/*
+ * nss_nlgre_redir_cmd_get_ifnum()
+ * 	Get the interface number corresponding to netdev
+ */
+int nss_nlgre_redir_cmd_get_ifnum(struct net_device *dev, uint8_t proto);
+
+/*
+ * nss_nlgre_redir_cmd_get_mtu()
+ * 	Returns the mtu based on the device passed
+ */
+int nss_nlgre_redir_cmd_get_mtu(struct net_device *dev, uint8_t iptype, int ifnum);
+
+#endif /* __NSS_NLGRE_REDIR_CMD_H */
diff --git a/qca-nss-clients/netlink/nss_nlgre_redir_cmn.c b/qca-nss-clients/netlink/nss_nlgre_redir_cmn.c
new file mode 100644
index 0000000..2517622
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlgre_redir_cmn.c
@@ -0,0 +1,918 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2015-2016, 2018-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/etherdevice.h>
+#include <linux/if_ether.h>
+#include <net/genetlink.h>
+#include <nss_api_if.h>
+#include <nss_nl_if.h>
+#include "nss_nlcmn_if.h"
+#include "nss_nl.h"
+#include "nss_nlgre_redir_if.h"
+#include "nss_nlgre_redir_cmn.h"
+
+static struct nss_nlgre_redir_cmn_tun_data tun_data[NSS_NLGRE_REDIR_CMN_MAX_TUNNELS];
+static const struct net_device_ops gre_redir_netdev_ops;
+static DEFINE_SPINLOCK(lock);
+
+/*
+ * nss_nlgre_redir_cmn_get_tun_data()
+ * 	Returns the tun_data after checking for lock
+ */
+static struct nss_nlgre_redir_cmn_tun_data nss_nlgre_redir_cmn_get_tun_data(struct net_device *dev)
+{
+	struct nss_nlgre_redir_cmn_tun_data dummy_tun_data = {0};
+	int index;
+
+	spin_lock(&lock);
+	for (index = 0; index < NSS_NLGRE_REDIR_CMN_MAX_TUNNELS; index++) {
+		if (dev != tun_data[index].dev) {
+			continue;
+		}
+
+		spin_unlock(&lock);
+		return tun_data[index];
+	}
+
+	spin_unlock(&lock);
+	return dummy_tun_data;
+}
+
+/*
+ * nss_nlgre_redir_cmn_get_next_free_tun()
+ * 	Returns the next free tunnel available
+ */
+static int nss_nlgre_redir_cmn_get_next_free_tun(void)
+{
+	int index;
+
+	spin_lock(&lock);
+	for (index = 0; index < NSS_NLGRE_REDIR_CMN_MAX_TUNNELS ; index++) {
+		if (!tun_data[index].enable) {
+			spin_unlock(&lock);
+			return index;
+		}
+	}
+
+	spin_unlock(&lock);
+	nss_nl_error("Max tunnel count exceeded: %d\n", index);
+	return -1;
+}
+
+/*
+ * nss_nlgre_redir_cmn_set_tun_data()
+ * 	Set the tun_data value to value passed
+ */
+static bool nss_nlgre_redir_cmn_set_tun_data(struct nss_nlgre_redir_cmn_tun_data *data, int index)
+{
+	if (!data) {
+		nss_nl_error("data is NULL\n");
+		return false;
+	}
+
+	spin_lock(&lock);
+	tun_data[index] = *data;
+	spin_unlock(&lock);
+	return true;
+}
+
+/*
+ * nss_nlgre_redir_cmn_init_tun_data()
+ * 	Initializes the tun_data
+ */
+static void nss_nlgre_redir_cmn_init_tun_data(struct nss_nlgre_redir_cmn_tun_data *tun_data)
+{
+	tun_data->dev = NULL;
+	tun_data->enable = false;
+	tun_data->host_inner_ifnum = -1;
+	tun_data->wifi_offl_inner_ifnum = -1;
+	tun_data->sjack_inner_ifnum = -1;
+	tun_data->outer_ifnum = -1;
+}
+
+/*
+ * nss_nlgre_redir_cmn_deinit_tun_data()
+ *	Deinitialize private data for the given index.
+ */
+static bool nss_nlgre_redir_cmn_deinit_tun_data(struct nss_nlgre_redir_cmn_tun_data *tun_data, int index)
+{
+	struct nss_ctx_instance *nss_ctx;
+
+	nss_ctx = nss_gre_redir_get_context();
+	tun_data->dev = NULL;
+	tun_data->enable = false;
+	tun_data->host_inner_ifnum = -1;
+	tun_data->wifi_offl_inner_ifnum = -1;
+	tun_data->sjack_inner_ifnum = -1;
+	tun_data->outer_ifnum = -1;
+
+	if (!nss_nlgre_redir_cmn_set_tun_data(tun_data, index)) {
+		nss_nl_error("%px: Unable to set tun_data\n", nss_ctx);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nlgre_redir_cmn_host_data_cb()
+ *	Data callback for host offload inner node.
+ */
+static void nss_nlgre_redir_cmn_host_data_cb(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_redir_get_context();
+
+	if (!skb) {
+		nss_nl_trace("%px: SKB is NULL\n", nss_ctx);
+		return;
+	}
+
+	nss_nl_trace("%px: Exception packet on host inner:\n", skb);
+	nss_nlgre_redir_cmn_print_hex_dump(skb);
+	skb->protocol = eth_type_trans(skb, netdev);
+	netif_receive_skb(skb);
+}
+
+/*
+ * nss_nlgre_redir_cmn_wifi_offl_data_cb()
+ *	Data callback for wifi offload inner node.
+ */
+static void nss_nlgre_redir_cmn_wifi_offl_data_cb(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_redir_get_context();
+
+	if (!skb) {
+		nss_nl_warn("%px: SKB is NULL\n", nss_ctx);
+		return;
+	}
+
+	nss_nl_trace("%px: Exception packet on wifi offld inner:\n", skb);
+	nss_nlgre_redir_cmn_print_hex_dump(skb);
+	skb->protocol = eth_type_trans(skb, netdev);
+	netif_receive_skb(skb);
+}
+
+/*
+ * nss_nlgre_redir_cmn_sjack_data_cb
+ *	Data callback for sjack inner node.
+ */
+static void nss_nlgre_redir_cmn_sjack_data_cb(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	nss_nl_trace("%px: Exception packet on sjack inner node:\n", skb);
+	nss_nlgre_redir_cmn_print_hex_dump(skb);
+	dev_kfree_skb(skb);
+}
+
+/*
+ * nss_nlgre_redir_cmn_outer_data_cb()
+ *	Data callback for outer node.
+ */
+static void nss_nlgre_redir_cmn_outer_data_cb(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	nss_nl_trace("%px: Exception packet on outer node:\n", skb);
+	nss_nlgre_redir_cmn_print_hex_dump(skb);
+	dev_kfree_skb(skb);
+}
+
+/*
+ * nss_nlgre_redir_cmn_map_unmap_msg_cb()
+ *	HLOS->NSS message completion callback.
+ */
+static void nss_nlgre_redir_cmn_map_unmap_msg_cb(void *app_data, struct nss_cmn_msg *cmnmsg)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_redir_get_context();
+	nss_nl_info("%px: callback gre_redir tunnel msg from NSS\n", nss_ctx);
+}
+
+/*
+ * nss_nlgre_redir_cmn_interface_alloc_and_register()
+ * 	Allocates nodes and registers callbacks
+ */
+static int nss_nlgre_redir_cmn_interface_alloc_and_register(struct nss_nlgre_redir_cmn_tun_data *tun_data, struct net_device *dev)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_redir_get_context();
+
+	tun_data->host_inner_ifnum = nss_gre_redir_alloc_and_register_node(dev,
+			nss_nlgre_redir_cmn_host_data_cb,
+			NULL, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_HOST_INNER, dev);
+	nss_nl_info("%px: host_inner = %d\n", nss_ctx, tun_data->host_inner_ifnum);
+	if (tun_data->host_inner_ifnum == -1) {
+		nss_nl_error("%px: Unable to allocate and register wifi host inner interface\n", nss_ctx);
+		return -1;
+	}
+
+	tun_data->wifi_offl_inner_ifnum = nss_gre_redir_alloc_and_register_node(dev,
+			nss_nlgre_redir_cmn_wifi_offl_data_cb,
+			NULL, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_OFFL_INNER, dev);
+	nss_nl_info("%px: wifi_inner = %d\n", nss_ctx, tun_data->wifi_offl_inner_ifnum);
+	if (tun_data->wifi_offl_inner_ifnum == -1) {
+		nss_nl_error("%px: Unable to allocate and register wifi offload inner interface\n", nss_ctx);
+		return -1;
+	}
+
+	tun_data->sjack_inner_ifnum = nss_gre_redir_alloc_and_register_node(dev,
+			nss_nlgre_redir_cmn_sjack_data_cb,
+			NULL, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_SJACK_INNER, dev);
+	nss_nl_info("%px: sjack_inner = %d\n", nss_ctx, tun_data->sjack_inner_ifnum);
+	if (tun_data->sjack_inner_ifnum == -1) {
+		nss_nl_error("%px: Unable to allocate and register sjack inner interface\n", nss_ctx);
+		return -1;
+	}
+
+	tun_data->outer_ifnum = nss_gre_redir_alloc_and_register_node(dev,
+			nss_nlgre_redir_cmn_outer_data_cb,
+			NULL, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_OUTER, dev);
+	nss_nl_info("%px: outer = %d\n", nss_ctx, tun_data->outer_ifnum);
+	if (tun_data->outer_ifnum == -1) {
+		nss_nl_error("%px: Unable to allocate and register outer interface\n", nss_ctx);
+		return -1;
+	}
+
+	return 0;
+
+}
+
+/*
+ * nss_nlgre_redir_cmn_open_interface()
+ *	Used when the interface is opened for use.
+ */
+static int nss_nlgre_redir_cmn_open_interface(struct net_device *dev)
+{
+	struct nss_gre_redir_cmn_ndev_priv *priv;
+	priv = netdev_priv(dev);
+	priv->gre_seq = 0;
+	netif_start_queue(dev);
+	netif_carrier_on(dev);
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_cmn_close_interace()
+ *	Used when the interface is closed.
+ */
+static int nss_nlgre_redir_cmn_close_interface(struct net_device *dev)
+{
+	netif_stop_queue (dev);
+	netif_carrier_off(dev);
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_cmn_xmit_data()
+ *	Used when the interface is used for transmit data.
+ */
+static netdev_tx_t nss_nlgre_redir_cmn_xmit_data(struct sk_buff *skb, struct net_device *dev)
+{
+	struct nss_gre_redir_encap_per_pkt_metadata *meta_data_encap = NULL;
+	struct nss_gre_redir_cmn_ndev_priv *priv;
+	uint32_t ifnum, ret = 0;
+	struct nss_ctx_instance *nss_ctx;
+
+	nss_ctx = nss_gre_redir_get_context();
+	priv = netdev_priv(dev);
+	ifnum = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_HOST_INNER);
+
+	/*
+	 * Initializing the start of skb with offset of metadata
+	 */
+	*(skb->head) = NSS_GRE_REDIR_PER_PACKET_METADATA_OFFSET;
+
+	/*
+	 * Configuring gre_redir meta data.
+	 */
+	meta_data_encap = (struct nss_gre_redir_encap_per_pkt_metadata *)(skb->head + NSS_GRE_REDIR_PER_PACKET_METADATA_OFFSET);
+	memset(meta_data_encap, 0, sizeof(struct nss_gre_redir_encap_per_pkt_metadata));
+	meta_data_encap->gre_flags = 0;
+	meta_data_encap->gre_prio = 0;
+	meta_data_encap->gre_seq = ++priv->gre_seq;
+	meta_data_encap->gre_tunnel_id = 10;
+	meta_data_encap->ip_dscp = 0;
+	meta_data_encap->ip_df_override = 0;
+	meta_data_encap->ipsec_pattern = 0;
+
+	nss_ctx = nss_gre_redir_get_context();
+	ret = nss_gre_redir_tx_buf(nss_ctx, skb, ifnum);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_nl_error("%px: Transmit failed and returned with %d\n", nss_ctx, ret);
+		dev_kfree_skb_any(skb);
+	}
+
+	return ret;
+}
+
+/*
+ * nss_nlgre_redir_cmn_stats64_get()
+ *	Used to get link statistics.
+ */
+static struct rtnl_link_stats64 *nss_nlgre_redir_cmn_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	struct nss_gre_redir_tunnel_stats get_stats;
+	bool found = false;
+	int i;
+
+	for (i = 0; i < NSS_GRE_REDIR_MAX_INTERFACES; i++) {
+		if (!nss_gre_redir_stats_get(i, &get_stats)) {
+			continue;
+		}
+
+		if (get_stats.dev != dev) {
+			continue;
+		}
+
+		found = true;
+		break;
+	}
+
+	if (found == false)
+		return NULL;
+
+	stats->tx_bytes   = get_stats.tstats.tx_bytes;
+	stats->tx_packets = get_stats.tstats.tx_packets;
+	stats->rx_bytes   = get_stats.tstats.rx_bytes;
+	stats->rx_packets = get_stats.tstats.rx_packets;
+	for (i = 0;i < ARRAY_SIZE(get_stats.tstats.rx_dropped); i++) {
+		stats->rx_dropped += get_stats.tstats.rx_dropped[i];
+	}
+
+	stats->tx_dropped = get_stats.tstats.tx_dropped;
+
+	return stats;
+}
+
+/*
+ * nss_nlgre_redir_cmn_dev_stats64
+ *	Report packet statistics to linux
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0))
+static struct rtnl_link_stats64 *nss_nlgre_redir_cmn_dev_stats64(struct net_device *dev,
+		struct rtnl_link_stats64 *stats)
+{
+	return nss_nlgre_redir_cmn_get_stats64(dev, stats);
+}
+#else
+static void nss_nlgre_redir_cmn_dev_stats64(struct net_device *dev,
+		struct rtnl_link_stats64 *stats)
+{
+	nss_nlgre_redir_cmn_get_stats64(dev, stats);
+}
+#endif
+
+/*
+ * nss_nlgre_redir_cmn_set_mac_address()
+ * 	Sets the mac address of netdev
+ */
+static int nss_nlgre_redir_cmn_set_mac_address(struct net_device *dev, void *p)
+{
+	struct sockaddr *addr = (struct sockaddr *)p;
+
+	if (!is_valid_ether_addr(addr->sa_data)) {
+		nss_nl_error("%pM: MAC address validation failed\n", addr->sa_data);
+		return -EINVAL;
+	}
+
+	memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_cmn_netdev_destructor()
+ * 	Unregisters and free the net device
+ */
+static void nss_nlgre_redir_cmn_netdev_destructor(struct net_device *dev)
+{
+	nss_nl_info("Gre_redir tunnel device freed %s\n", dev->name);
+	free_netdev(dev);
+}
+
+/*
+ * nss_nlgre_redir_cmn_dev_setup()
+ * 	To setup the netdevice
+ */
+static void nss_nlgre_redir_cmn_dev_setup(struct net_device *dev)
+{
+	ether_setup(dev);
+	dev->needed_headroom = NSS_NLGRE_REDIR_CMN_NEEDED_HEADROOM;
+	dev->netdev_ops = &gre_redir_netdev_ops;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0))
+	dev->destructor = nss_nlgre_redir_cmn_netdev_destructor;
+#else
+	dev->priv_destructor = nss_nlgre_redir_cmn_netdev_destructor;
+#endif
+	eth_hw_addr_random(dev);
+}
+
+/*
+ * net_device_ops
+ *	Netdevice operations.
+ */
+static const struct net_device_ops gre_redir_netdev_ops = {
+	.ndo_open = nss_nlgre_redir_cmn_open_interface,
+	.ndo_stop = nss_nlgre_redir_cmn_close_interface,
+	.ndo_start_xmit = nss_nlgre_redir_cmn_xmit_data,
+	.ndo_get_stats64 = nss_nlgre_redir_cmn_dev_stats64,
+	.ndo_set_mac_address = nss_nlgre_redir_cmn_set_mac_address,
+};
+
+/*
+ * nss_nlgre_redir_cmn_print_hex_dump()
+ *	To print hex dump of packet received
+ */
+void nss_nlgre_redir_cmn_print_hex_dump(struct sk_buff *skb)
+{
+	int16_t dump_sz = (skb->len < NSS_NLGRE_REDIR_PKT_DUMP_SZ) ? skb->len : NSS_NLGRE_REDIR_PKT_DUMP_SZ;
+
+	dump_sz -= NSS_NLGRE_REDIR_PKT_DUMP_OFFSET;
+	if (dump_sz > 0) {
+		/*
+		 * Enable dynamic debug to print
+		 */
+		print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, skb->data, dump_sz);
+		return;
+	}
+
+	nss_nl_warn("Could not print packet skb->len=%d, DUMP_SZ=%d, DUMP_OFFSET=%d\n",
+			skb->len, NSS_NLGRE_REDIR_PKT_DUMP_SZ, NSS_NLGRE_REDIR_PKT_DUMP_OFFSET);
+}
+
+/*
+ * nss_nlgre_redir_cmn_mode_str_to_enum()
+ * 	Returns the type of mode
+ */
+enum nss_nlgre_redir_cmn_mode_type nss_nlgre_redir_cmn_mode_str_to_enum(char *mode)
+{
+	if (!mode)
+		return NSS_NLGRE_REDIR_CMN_MODE_TYPE_UNKNOWN;
+	if (!strncmp(mode, "wifi", NSS_NLGRE_REDIR_MODE_MAX_SZ))
+		return NSS_NLGRE_REDIR_CMN_MODE_TYPE_WIFI;
+	if (!strncmp(mode, "split", NSS_NLGRE_REDIR_MODE_MAX_SZ))
+		return NSS_NLGRE_REDIR_CMN_MODE_TYPE_SPLIT;
+
+	return NSS_NLGRE_REDIR_CMN_MODE_TYPE_UNKNOWN;
+}
+
+/*
+ * nss_nlgre_redir_cmn_get_tun_ifnum()
+ * 	Returns the interface number of the net device
+ */
+int32_t nss_nlgre_redir_cmn_get_tun_ifnum(enum nss_nlgre_redir_cmn_mode_type type, struct net_device *dev)
+{
+	struct nss_nlgre_redir_cmn_tun_data tun_data;
+
+	if (!dev) {
+		nss_nl_error("net_dev is NULL\n");
+		return -1;
+	}
+
+	tun_data = nss_nlgre_redir_cmn_get_tun_data(dev);
+	if (!tun_data.dev) {
+		nss_nl_error("Invalid tun_data: %px\n", tun_data.dev);
+		return -1;
+	}
+
+	switch(type) {
+	case NSS_NLGRE_REDIR_CMN_MODE_TYPE_WIFI:
+		return tun_data.wifi_offl_inner_ifnum;
+	case NSS_NLGRE_REDIR_CMN_MODE_TYPE_SPLIT:
+		return NSS_ETH_RX_INTERFACE;
+	default:
+		nss_nl_error("Wrong mode type: %d\n", type);
+		return -1;
+	}
+
+	return -1;
+}
+
+/*
+ * nss_nlgre_redir_cmn_get_tun_type()
+ * 	Returns the type of tunnel we'll operate in
+ */
+enum nss_nlgre_redir_cmn_tun_type nss_nlgre_redir_cmn_get_tun_type(char *tun_type)
+{
+	if (!tun_type)
+		return NSS_NLGRE_REDIR_CMN_TUN_TYPE_UNKNOWN;
+	if (!strncmp(tun_type, "tun", NSS_NLGRE_REDIR_CMN_TUN_TYPE_MAX_SZ))
+		return NSS_NLGRE_REDIR_CMN_TUN_TYPE_TUN;
+	if (!strncmp(tun_type, "dtun", NSS_NLGRE_REDIR_CMN_TUN_TYPE_MAX_SZ))
+		return NSS_NLGRE_REDIR_CMN_TUN_TYPE_DTUN;
+	if (!strncmp(tun_type, "split", NSS_NLGRE_REDIR_CMN_TUN_TYPE_MAX_SZ))
+		return NSS_NLGRE_REDIR_CMN_TUN_TYPE_SPLIT;
+
+	return NSS_NLGRE_REDIR_CMN_TUN_TYPE_UNKNOWN;
+}
+
+/*
+ * nss_nlgre_redir_cmn_get_tun_data_index()
+ *	Returns index in array of private data.
+ */
+int nss_nlgre_redir_cmn_get_tun_data_index(struct net_device *dev)
+{
+	struct nss_ctx_instance *nss_ctx;
+	uint32_t iter;
+
+	nss_ctx = nss_gre_redir_get_context();
+	if (!dev) {
+		nss_nl_error("%px: Dev is NULL\n", nss_ctx);
+		return -1;
+	}
+
+	spin_lock(&lock);
+	for (iter = 0; iter < NSS_NLGRE_REDIR_CMN_MAX_TUNNELS; iter++) {
+		if (tun_data[iter].dev != dev) {
+			continue;
+		}
+
+		spin_unlock(&lock);
+		return iter;
+	}
+
+	spin_unlock(&lock);
+	return -1;
+}
+
+/*
+ * nss_gre_redir_unregister_and_deallocate()
+ *	Unregisters and deallocates corresponding dev and node.
+ */
+bool nss_nlgre_redir_cmn_unregister_and_deallocate(struct net_device *dev, uint32_t type)
+{
+	nss_tx_status_t status;
+	int ifnum;
+	bool ret;
+
+	ifnum = nss_cmn_get_interface_number_by_dev_and_type(dev, type);
+	if (ifnum == -1) {
+		nss_nl_error("%px: unable to get NSS interface for net device %s of type %d\n", dev, dev->name, type);
+		return false;
+	}
+
+	ret = nss_gre_redir_unregister_if(ifnum);
+	if (!ret) {
+		nss_nl_error("%px: Unable to unregister interface %d\n", dev, ret);
+		return false;
+	}
+
+	status = nss_dynamic_interface_dealloc_node(ifnum, type);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_error("%px: Unable to deallocate node %d\n", dev, status);
+		return false;
+	}
+
+	nss_nl_trace("%s: Sucessfully unregistered and deallocated %d\n", dev->name, ifnum);
+	return true;
+}
+
+/*
+ * nss_nlgre_redir_cmn_interfaces_unregister_and_dealloc
+ * 	Find out the interfaces to be deallocated
+ */
+void nss_nlgre_redir_cmn_interfaces_unregister_and_dealloc(struct nss_nlgre_redir_cmn_tun_data *tun_data)
+{
+	struct nss_ctx_instance *nss_ctx;
+
+	nss_ctx = nss_gre_redir_get_context();
+	if (tun_data->sjack_inner_ifnum != -1) {
+		if(!nss_nlgre_redir_cmn_unregister_and_deallocate(tun_data->dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_HOST_INNER)) {
+			nss_nl_error("%px: Unable to unregister and deallocate node of type %d\n", nss_ctx,
+					NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_HOST_INNER);
+		}
+	}
+
+	if (tun_data->wifi_offl_inner_ifnum != -1) {
+		if (!nss_nlgre_redir_cmn_unregister_and_deallocate(tun_data->dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_OFFL_INNER)) {
+			nss_nl_error("%px: Unable to unregister and deallocate node of type %d\n", nss_ctx,
+					NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_OFFL_INNER);
+		}
+	}
+
+	if (tun_data->host_inner_ifnum != -1) {
+		if (!nss_nlgre_redir_cmn_unregister_and_deallocate(tun_data->dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_SJACK_INNER)) {
+			nss_nl_error("%px: Unable to unregister and deallocate node of type %d\n", nss_ctx,
+					NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_SJACK_INNER);
+		}
+	}
+
+	if (tun_data->outer_ifnum != -1) {
+		if (!nss_nlgre_redir_cmn_unregister_and_deallocate(tun_data->dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_OUTER)) {
+			nss_nl_error("%px: Unable to unregister and deallocate node of type %d\n", nss_ctx,
+					NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_OUTER);
+		}
+	}
+
+	nss_nl_trace("%s: Sucessfully unregistered and deallocated\n", tun_data->dev->name);
+}
+
+/*
+ * nss_nlgre_redir_cmn_destroy_tun()
+ *	Unregisters and deallocs dynamic interfaces.
+ */
+int nss_nlgre_redir_cmn_destroy_tun(struct net_device *dev)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_redir_get_context();
+	struct nss_nlgre_redir_cmn_tun_data tun_data;
+	int index;
+
+	dev_hold(dev);
+	tun_data = nss_nlgre_redir_cmn_get_tun_data(dev);
+	if (!tun_data.dev) {
+		nss_nl_error("%px: Invalid tun data\n", nss_ctx);
+		return -1;
+	}
+
+	index = nss_nlgre_redir_cmn_get_tun_data_index(tun_data.dev);
+	if (index < NSS_NLGRE_REDIR_CMN_MIN_TUNNELS || index >= NSS_NLGRE_REDIR_CMN_MAX_TUNNELS) {
+		nss_nl_error("%px: index out of bound %d\n", nss_ctx, index);
+		return -1;
+	}
+
+	nss_nlgre_redir_cmn_interfaces_unregister_and_dealloc(&tun_data);
+	nss_nlgre_redir_cmn_deinit_tun_data(&tun_data, index);
+	dev_put(dev);
+	unregister_netdev(dev);
+	nss_nl_info("%px: Successfully destroyed gretun = gretun%d tunnel\n", dev, index);
+	return index;
+}
+
+/*
+ * nss_nlgre_redir_cmn_create_tun()
+ *	Allocates netdevice and configures tunnel.
+ */
+struct net_device *nss_nlgre_redir_cmn_create_tun(uint32_t sip[4], uint32_t dip[4], uint8_t iptype)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_redir_get_context();
+	struct nss_gre_redir_outer_configure_msg ngrocm = {0};
+	struct nss_gre_redir_inner_configure_msg ngrm = {0};
+	struct nss_nlgre_redir_cmn_tun_data tun_data;
+	struct nss_gre_redir_cmn_ndev_priv *priv;
+	struct net_device *dev;
+	nss_tx_status_t status;
+	int tun_idx = -1, ret;
+
+	tun_idx = nss_nlgre_redir_cmn_get_next_free_tun();
+	if (tun_idx == -1) {
+		nss_nl_error("Unable to allocate any tunnel\n");
+		return NULL;
+	}
+
+	/*
+	 * Initializes the tun_data
+	 */
+	nss_nlgre_redir_cmn_init_tun_data(&tun_data);
+	dev = alloc_netdev(sizeof(*priv), "gretun%d", NET_NAME_UNKNOWN, nss_nlgre_redir_cmn_dev_setup);
+	if (!dev) {
+		nss_nl_error("Unable to allocate netdev\n");
+		return NULL;
+	}
+
+	if (register_netdev(dev)) {
+		nss_nl_warn("Unable to register netdev %s\n", dev->name);
+		free_netdev(dev);
+		goto fail;
+	}
+
+	/*
+	 * Dynamic interface allocation.
+	 */
+	ret = nss_nlgre_redir_cmn_interface_alloc_and_register(&tun_data, dev);
+	if (ret == -1) {
+		nss_nl_error("%px: Unable to allocate and register gre_redir nodes\n", nss_ctx);
+		unregister_netdev(dev);
+		goto fail;
+	}
+
+	memcpy(ngrm.ip_src_addr, sip, sizeof(ngrm.ip_src_addr));
+	memcpy(ngrm.ip_dest_addr, dip, sizeof(ngrm.ip_dest_addr));
+
+	/*
+	 * TODO: Dynamic assignment of values from userspace
+	 * ip_df_policy value currently hard coded. This needs to be supplied from userspace.
+	 */
+	ngrm.ip_hdr_type = iptype;
+	ngrm.ip_df_policy = 0;
+	ngrm.gre_version = 0;
+	ngrm.ip_ttl = NSS_NLGRE_REDIR_CMN_IP_TTL;
+	ngrm.except_outerif = tun_data.outer_ifnum;
+
+	/*
+	 * TODO: Dynamic assignment of values from userspace
+	 * rps_hint value currently hard coded. This needs to be supplied from userspace.
+	 */
+	ngrocm.ip_hdr_type = iptype;
+	ngrocm.rps_hint = 0;
+	ngrocm.except_hostif = tun_data.host_inner_ifnum;
+	ngrocm.except_offlif = tun_data.wifi_offl_inner_ifnum;
+	ngrocm.except_sjackif = tun_data.sjack_inner_ifnum;
+
+	status = nss_gre_redir_configure_inner_node(tun_data.host_inner_ifnum, &ngrm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_warn("%px: unable to configure host inner node %d\n", nss_ctx, tun_data.host_inner_ifnum);
+		unregister_netdev(dev);
+		goto fail;
+	}
+
+	status = nss_gre_redir_configure_inner_node(tun_data.wifi_offl_inner_ifnum, &ngrm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_warn("%px: unable to configure wifi offload inner node %d\n", nss_ctx, tun_data.host_inner_ifnum);
+		unregister_netdev(dev);
+		goto fail;
+	}
+
+	status = nss_gre_redir_configure_inner_node(tun_data.sjack_inner_ifnum, &ngrm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_warn("%px: unable to configure sjack inner node %d\n", nss_ctx, tun_data.sjack_inner_ifnum);
+		unregister_netdev(dev);
+		goto fail;
+	}
+
+	status = nss_gre_redir_configure_outer_node(tun_data.outer_ifnum, &ngrocm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_warn("%px: unable to configure outer node %d\n", nss_ctx, tun_data.host_inner_ifnum);
+		unregister_netdev(dev);
+		goto fail;
+	}
+
+	tun_data.enable = true;
+	tun_data.dev = dev;
+	if (!nss_nlgre_redir_cmn_set_tun_data(&tun_data, tun_idx)) {
+		nss_nl_error("%px: Unable to set tun data\n", nss_ctx);
+		unregister_netdev(dev);
+		goto fail;
+	}
+
+	return dev;
+fail:
+	nss_nlgre_redir_cmn_interfaces_unregister_and_dealloc(&tun_data);
+	nss_nlgre_redir_cmn_deinit_tun_data(&tun_data, tun_idx);
+	return NULL;
+}
+
+/*
+ * nss_nlgre_redir_cmn_get_dev_ifnum()
+ * 	Returns the interface number by dev and type
+ */
+int32_t nss_nlgre_redir_cmn_get_dev_ifnum(char *dev_name)
+{
+	struct net_device *dev;
+	uint32_t ifnum;
+
+	if (!dev_name) {
+		nss_nl_error("dev_name is NULL\n");
+		return -1;
+	}
+
+	/*
+	 * Get the dev reference
+	 */
+	dev = dev_get_by_name(&init_net, dev_name);
+	if (!dev) {
+		nss_nl_error("Invalid parameter: %s\n", dev_name);
+		return -ENODEV;
+	}
+
+	ifnum = nss_cmn_get_interface_number_by_dev(dev);
+	dev_put(dev);
+	return ifnum;
+}
+
+/*
+ * nss_nlgre_redir_cmn_map_interface()
+ *	Map nss interface to tunnel ID.
+ */
+int nss_nlgre_redir_cmn_map_interface(uint32_t nexthop_nssif, uint16_t lag_en, struct nss_nlgre_redir_map *map_params)
+{
+	struct nss_gre_redir_msg ngrm;
+	struct nss_ctx_instance *nss_ctx;
+	nss_tx_status_t ret;
+	uint32_t vap_nss_if;
+	uint8_t tun_type;
+	uint32_t len;
+
+	len = sizeof(struct nss_gre_redir_msg) - sizeof(struct nss_cmn_msg);
+	nss_ctx = nss_gre_redir_get_context();
+	tun_type = nss_nlgre_redir_cmn_get_tun_type(map_params->tun_type);
+	vap_nss_if = nss_nlgre_redir_cmn_get_dev_ifnum(map_params->vap_nss_if);
+	if ((vap_nss_if >= NSS_DYNAMIC_IF_START+NSS_MAX_DYNAMIC_INTERFACES) || (vap_nss_if < NSS_DYNAMIC_IF_START)) {
+		nss_nl_error("%px: vap_nss_if is out of valid range for vap: %d\n", nss_ctx, vap_nss_if);
+		return -1;
+	}
+
+	if (map_params->rid >= NSS_NLGRE_REDIR_CMN_RADIO_ID_MAX) {
+		nss_nl_error("%px: radio_id is out of valid range for vap: %d\n", nss_ctx, vap_nss_if);
+		return -1;
+	}
+
+	if (map_params->vid >= NSS_NLGRE_REDIR_CMN_VAP_ID_MAX) {
+		nss_nl_error("%px: vap_id is out of valid range for vap: %d\n", nss_ctx, vap_nss_if);
+		return -1;
+	}
+
+	nss_cmn_msg_init(&ngrm.cm, NSS_GRE_REDIR_INTERFACE, NSS_GRE_REDIR_TX_INTERFACE_MAP_MSG,
+			len, nss_nlgre_redir_cmn_map_unmap_msg_cb, NULL);
+
+	ngrm.msg.interface_map.vap_nssif = vap_nss_if;
+	ngrm.msg.interface_map.radio_id = map_params->rid;
+	ngrm.msg.interface_map.vap_id = map_params->vid;
+	ngrm.msg.interface_map.tunnel_type = tun_type;
+	ngrm.msg.interface_map.ipsec_pattern = map_params->ipsec_sa_pattern;
+	ngrm.msg.interface_map.lag_en = lag_en;
+	ngrm.msg.interface_map.nexthop_nssif = nexthop_nssif;
+
+	ret = nss_gre_redir_tx_msg_sync(nss_ctx, &ngrm);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_nl_error("%px: Tx to firmware failed\n", nss_ctx);
+		return -1;
+	}
+
+	nss_nl_info("%px: Successfully transmitted msg to firmware\n", nss_ctx);
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_cmn_unmap_interface()
+ *	Interface unmap message.
+ */
+int nss_nlgre_redir_cmn_unmap_interface(struct nss_nlgre_redir_unmap *unmap_params)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_gre_redir_msg ngrm;
+	uint32_t vap_nss_if, len;
+	nss_tx_status_t ret;
+
+	len = sizeof(struct nss_gre_redir_msg) - sizeof(struct nss_cmn_msg);
+	vap_nss_if = nss_nlgre_redir_cmn_get_dev_ifnum(unmap_params->vap_nss_if);
+	nss_ctx = nss_gre_redir_get_context();
+
+	if ((vap_nss_if >= NSS_DYNAMIC_IF_START+NSS_MAX_DYNAMIC_INTERFACES) || (vap_nss_if < NSS_DYNAMIC_IF_START)) {
+		nss_nl_error("%px: vap_nss_if is out of valid range for vap: %d\n", nss_ctx, vap_nss_if);
+		return -1;
+	}
+
+	if (unmap_params->rid >= NSS_NLGRE_REDIR_CMN_RADIO_ID_MAX) {
+		nss_nl_error("%px: radio_id is out of valid range for vap: %d\n", nss_ctx, vap_nss_if);
+		return -1;
+	}
+
+	if (unmap_params->vid >= NSS_NLGRE_REDIR_CMN_VAP_ID_MAX) {
+		nss_nl_error("%px: vap_id is out of valid range for vap: %d\n", nss_ctx, vap_nss_if);
+		return -1;
+	}
+
+	nss_cmn_msg_init(&ngrm.cm, NSS_GRE_REDIR_INTERFACE, NSS_GRE_REDIR_TX_INTERFACE_UNMAP_MSG,
+			len, nss_nlgre_redir_cmn_map_unmap_msg_cb, NULL);
+	ngrm.msg.interface_unmap.vap_nssif = vap_nss_if;
+	ngrm.msg.interface_unmap.radio_id = unmap_params->rid;
+	ngrm.msg.interface_unmap.vap_id = unmap_params->vid;
+
+	ret = nss_gre_redir_tx_msg_sync(nss_ctx, &ngrm);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_nl_error("%px: Tx to firmware failed\n", nss_ctx);
+		return -1;
+	}
+
+	nss_nl_info("%px: Successfully transmitted msg to firmware\n", nss_ctx);
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_cmn_set_next_hop()
+ *	Sets next hop as gre-redir for wifi.
+ */
+int nss_nlgre_redir_cmn_set_next_hop(uint32_t next_dev_ifnum, struct nss_nlgre_redir_set_next *setnext_params)
+{
+	struct nss_ctx_instance *nss_ctx;
+	nss_tx_status_t ret;
+	int ifnumber;
+	void *ctx;
+
+	nss_ctx = nss_gre_redir_get_context();
+	ifnumber = nss_nlgre_redir_cmn_get_dev_ifnum(setnext_params->dev_name);
+	if (ifnumber == -1) {
+		nss_nl_error("%px: Unable to find NSS interface for net device %s\n", nss_ctx, setnext_params->dev_name);
+		return -1;
+	}
+
+	nss_nl_info("%px: next hop interface number is %d\n", nss_ctx, next_dev_ifnum);
+	ctx = nss_wifi_get_context();
+
+	ret = nss_wifi_vdev_set_next_hop(ctx, ifnumber, next_dev_ifnum);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_nl_error("%px: wifi drv api failed to set next hop\n", nss_ctx);
+		return -1;
+	}
+
+	nss_nl_info("%px: Successfully set the next hop\n", nss_ctx);
+	return 0;
+}
diff --git a/qca-nss-clients/netlink/nss_nlgre_redir_cmn.h b/qca-nss-clients/netlink/nss_nlgre_redir_cmn.h
new file mode 100644
index 0000000..00138b1
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlgre_redir_cmn.h
@@ -0,0 +1,157 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2014-2015,2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * NSS Netlink gre_redir headers
+ */
+#define NSS_NLGRE_REDIR_CMN_NEEDED_HEADROOM 192		/**< Maximum headroom available */
+#define NSS_NLGRE_REDIR_CMN_RADIO_ID_MAX 2		/**< Radio Id max size */
+#define NSS_NLGRE_REDIR_CMN_RADIO_ID_MIN 0		/**< Radio Id min size */
+#define NSS_NLGRE_REDIR_CMN_VAP_ID_MAX 16		/**< Vap Id max size */
+#define NSS_NLGRE_REDIR_CMN_VAP_ID_MIN 0		/**< Vap Id min size */
+#define NSS_NLGRE_REDIR_CMN_MAX_TUNNELS 24		/**< Maximum number of tunnels allowed */
+#define NSS_NLGRE_REDIR_CMN_TUN_TYPE_MAX_SZ 16		/**< Maximum size of tunnel type */
+#define NSS_NLGRE_REDIR_CMN_MAX_SKB_PRINT_LEN 3		/**< Maximum length of skb to print */
+#define NSS_NLGRE_REDIR_CMN_MIN_TUNNELS 0		/**< Mininum number of tunnels required */
+#define NSS_NLGRE_REDIR_CMN_IP_TTL 128			/**< Time to live for IP */
+#define NSS_NLGRE_REDIR_PKT_DUMP_SZ 64			/**< Size of packet to dump */
+#define NSS_NLGRE_REDIR_PKT_DUMP_OFFSET 0		/**< Dump offset */
+
+/*
+ * netdevice private data
+ */
+struct nss_gre_redir_cmn_ndev_priv {
+	uint32_t gre_seq;				/**< Sequence number */
+};
+
+/*
+ * Context need to be maintained globally for GRE redirect tunnel.
+ */
+struct nss_nlgre_redir_cmn_tun_data {
+	struct net_device *dev;				/**< Net device */
+	int32_t host_inner_ifnum;			/**< Interface no. of pnode host inner */
+	int32_t wifi_offl_inner_ifnum;			/**< Interface no. of pnode wifi offld inner */
+	int32_t sjack_inner_ifnum;			/**< Interface no. of pnode sjack inner */
+	int32_t outer_ifnum;				/**< Interface no. of pnode outer */
+	bool enable;					/**< Device is enabled or not */
+};
+
+/*
+ * nss_nlgre_redir_cmn_tun_type
+ * 	Different tunnel types supported in gre_redir
+ */
+enum nss_nlgre_redir_cmn_tun_type {
+	NSS_NLGRE_REDIR_CMN_TUN_TYPE_UNKNOWN,		/**< Unknown tunnel type */
+	NSS_NLGRE_REDIR_CMN_TUN_TYPE_TUN,		/**< Raw mode 802.11 frames traffic*/
+	NSS_NLGRE_REDIR_CMN_TUN_TYPE_DTUN,		/**< For 802.3 frames traffic */
+	NSS_NLGRE_REDIR_CMN_TUN_TYPE_SPLIT,		/**< For split mode */
+	NSS_NLGRE_REDIR_CMN_TUN_TYPE_MAX		/**< Max number of tun type supported */
+};
+
+/*
+ * nss_nlgre_redir_cmn_mode_type
+ * 	Modes available for setting next hop
+ */
+enum nss_nlgre_redir_cmn_mode_type {
+	NSS_NLGRE_REDIR_CMN_MODE_TYPE_UNKNOWN,	/**< Unknown mode type */
+	NSS_NLGRE_REDIR_CMN_MODE_TYPE_WIFI,	/**< ath0 ---> wifi_offld_inner */
+	NSS_NLGRE_REDIR_CMN_MODE_TYPE_SPLIT,	/**< ath0 ---> ETH_RX_INTERFACE */
+	NSS_NLGRE_REDIR_CMN_MODE_TYPE_MAX	/**< Max number of modes supported */
+};
+
+/*
+ * nss_nlgre_redir_cmn_init()
+ * 	Initializes the tun_data
+ */
+void nss_nlgre_redir_cmn_init(void);
+
+/*
+ * nss_nlgre_redir_cmn_get_tun_ifnum()
+ * 	Returns the interface number corresponding to dev
+ */
+int32_t nss_nlgre_redir_cmn_get_tun_ifnum(enum nss_nlgre_redir_cmn_mode_type type, struct net_device *dev);
+/*
+ * nss_nlgre_redir_cmn_mode_str_to_enum()
+ * 	Returns the enum converted value of the string
+ */
+enum nss_nlgre_redir_cmn_mode_type nss_nlgre_redir_cmn_mode_str_to_enum(char *mode);
+
+/*
+ * nss_nlgre_redir_cmn_get_tun_data_index()
+ * 	Returns the interface number of dev
+ */
+int nss_nlgre_redir_cmn_get_tun_data_index(struct net_device *dev);
+
+/*
+ * nss_nlgre_redir_cmn_get_dev_ifnum()
+ * 	Returns the interface number of dev
+ */
+int32_t nss_nlgre_redir_cmn_get_dev_ifnum(char *dev_name);
+
+/*
+ * nss_nlgre_redir_cmn_get_tun_type()
+ * 	Returns the tunnel type
+ */
+enum nss_nlgre_redir_cmn_tun_type nss_nlgre_redir_cmn_get_tun_type(char *tun_type);
+
+/*
+ * nss_gre_redir_cmn_unregister_and_deallocate()
+ * 	Unregisters and deallocates a node.
+ */
+bool nss_nlgre_redir_cmn_unregister_and_deallocate(struct net_device *dev, uint32_t type);
+
+/*
+ * nss_nlgre_redir_cmn_print_hex_dump()
+ *	Prints the initials few bytes of packet
+ */
+void nss_nlgre_redir_cmn_print_hex_dump(struct sk_buff *skb);
+
+/*
+ * nss_nlgre_redir_cmn_create_tun()
+ * 	Creates a gre_redir tunnel
+ */
+struct net_device *nss_nlgre_redir_cmn_create_tun(uint32_t sip[4], uint32_t dip[4], uint8_t iptype);
+
+/*
+ * nss_nlgre_redir_cmn_destroy_tun()
+ * 	Destroys the gre_redir tunnel
+ */
+int nss_nlgre_redir_cmn_destroy_tun(struct net_device *dev);
+
+/*
+ * nss_nlgre_redir_cmn_unmap_interface()
+ * 	Unmaps the nss interface
+ */
+int nss_nlgre_redir_cmn_unmap_interface(struct nss_nlgre_redir_unmap *unmap_params);
+
+/*
+ * nss_nlgre_redir_cmn_map_interface()
+ * 	Unmaps the nss interface
+ */
+int nss_nlgre_redir_cmn_map_interface(uint32_t nexthop_nssif, uint16_t lag_en, struct nss_nlgre_redir_map *map_params);
+
+/*
+ * nss_nlgre_redir_cmn_set_next_hop()
+ * 	Sets the next hop of the nss ath0 interface
+ */
+int nss_nlgre_redir_cmn_set_next_hop(uint32_t next_dev_ifnum, struct nss_nlgre_redir_set_next *set_next_params);
+
+/*
+ * nss_nlgre_redir_cmn_init()
+ *	Initializes tun_data and lock variable.
+ */
+void nss_nlgre_redir_cmn_init(void);
+
diff --git a/qca-nss-clients/netlink/nss_nlgre_redir_family.c b/qca-nss-clients/netlink/nss_nlgre_redir_family.c
new file mode 100644
index 0000000..576f064
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlgre_redir_family.c
@@ -0,0 +1,70 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2016,2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlgre_redir.c
+ * 	NSS Netlink gre_redir Handler
+ */
+#include <linux/version.h>
+#include <net/genetlink.h>
+#include <nss_api_if.h>
+#include <nss_nlcmn_if.h>
+#include <nss_nl_if.h>
+#include <nss_nlgre_redir_if.h>
+#include "nss_nl.h"
+#include "nss_nlgre_redir_cmd.h"
+
+/*
+ * nss_nlgre_redir_family_init()
+ * 	handler init
+ */
+bool nss_nlgre_redir_family_init(void)
+{
+	int err;
+	nss_nl_info_always("Init NSS netlink gre_redir handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	err = genl_register_family(&nss_nlgre_redir_cmd_family);
+	if (err) {
+		nss_nl_info_always("Error: %d unable to register gre_redir family\n", err);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nlgre_redir_family_exit()
+ *	handler exit
+ */
+bool nss_nlgre_redir_family_exit(void)
+{
+	int err;
+	nss_nl_info_always("Exit NSS netlink gre_redir handler\n");
+
+	/*
+	 * unregister the ops family
+	 */
+	err = genl_unregister_family(&nss_nlgre_redir_cmd_family);
+	if (err) {
+		nss_nl_info_always("Error: %d unable to unregister gre_redir NETLINK family\n", err);
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nlgre_redir_family.h b/qca-nss-clients/netlink/nss_nlgre_redir_family.h
new file mode 100644
index 0000000..dbad4e1
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlgre_redir_family.h
@@ -0,0 +1,44 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015,2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlgre_redir_family.h
+ *	NSS Netlink gre_redir API definitions
+ */
+#ifndef __NSS_NLGRE_REDIR_FAMILY_H
+#define __NSS_NLGRE_REDIR_FAMILY_H
+
+/*
+ * nss_nlgre_redir_family_init()
+ * 	To initialize the gre_redir module
+ */
+bool nss_nlgre_redir_family_init(void);
+
+/*
+ * nss_nlgre_redir_family_exit()
+ * 	Exit the gre_redir module
+ */
+bool nss_nlgre_redir_family_exit(void);
+
+#if defined(CONFIG_NSS_NLGRE_REDIR_FAMILY)
+#define NSS_NLGRE_REDIR_FAMILY_INIT nss_nlgre_redir_family_init
+#define NSS_NLGRE_REDIR_FAMILY_EXIT nss_nlgre_redir_family_exit
+#else
+#define NSS_NLGRE_REDIR_FAMILY_INIT 0
+#define NSS_NLGRE_REDIR_FAMILY_EXIT 0
+#endif /* !CONFIG_NSS_NLGRE_REDIR_FAMILY */
+
+#endif /* __NSS_NLGRE_REDIR_FAMILY_H */
diff --git a/qca-nss-clients/netlink/nss_nlgre_redir_lag.c b/qca-nss-clients/netlink/nss_nlgre_redir_lag.c
new file mode 100644
index 0000000..40c8bf0
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlgre_redir_lag.c
@@ -0,0 +1,436 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2015-2016,2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/etherdevice.h>
+#include <linux/if_ether.h>
+#include <net/genetlink.h>
+#include <nss_api_if.h>
+#include <nss_nl_if.h>
+#include "nss_nlcmn_if.h"
+#include "nss_nl.h"
+#include "nss_nlgre_redir_if.h"
+#include "nss_nlgre_redir_cmn.h"
+#include "nss_nlgre_redir_lag.h"
+
+/*
+ * Spin_lock for lag_pvt_data
+ */
+static DEFINE_SPINLOCK(lock);
+
+static struct nss_nlgre_redir_lag_pvt_data lag_pvt_data;
+static const struct net_device_ops dummy_netdev_ops;
+
+/*
+ * nss_nlgre_redir_lag_msg_completion_cb()
+ * 	HLOS->NSS message completion callback.
+ */
+static void nss_nlgre_redir_lag_msg_completion_cb(void *app_data, struct nss_cmn_msg *cmnmsg)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_redir_get_context();
+	nss_nl_info("%px: callback gre_redir tunnel msg from NSS\n", nss_ctx);
+}
+
+/*
+ * nss_nlgre_redir_lag_us_data_cb()
+ *	Exception handler for LAG_US node.
+ */
+static void nss_nlgre_redir_lag_us_data_cb(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	nss_nl_trace("Exception packet on lag_us node:\n");
+	nss_nlgre_redir_cmn_print_hex_dump(skb);
+	dev_kfree_skb_any(skb);
+}
+
+/*
+ * nss_nlgre_redir_lag_ds_data_cb()
+ *	Exception handler for LAG_DS node.
+ */
+static void nss_nlgre_redir_lag_ds_data_cb(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	nss_nl_trace("Exception packet on lag_ds node:\n");
+	nss_nlgre_redir_cmn_print_hex_dump(skb);
+	dev_kfree_skb_any(skb);
+}
+
+/*
+ * nss_nlgre_redir_lag_us_msg_cb()
+ *	GRE LAG upstream  NSS->HLOS message callback.
+ */
+static void nss_nlgre_redir_lag_us_msg_cb(void *app_data, struct nss_cmn_msg *cmnmsg)
+{
+	struct nss_gre_redir_lag_us_msg *tunmsg = (struct nss_gre_redir_lag_us_msg *)cmnmsg;
+	int i;
+
+	if (tunmsg->cm.type != NSS_GRE_REDIR_LAG_US_DB_HASH_NODE_MSG) {
+		return;
+	}
+
+	nss_nl_trace("%px: callback_stats: count = %u index = %u\n", tunmsg,
+			tunmsg->msg.hash_stats.count, tunmsg->msg.hash_stats.db_entry_idx);
+	for (i = 0; i < tunmsg->msg.hash_stats.count; i++) {
+		nss_nl_trace("%px: hits = %llu smac = %pM dmac = %pM\n", tunmsg,
+				tunmsg->msg.hash_stats.hstats[i].hits,
+				&(tunmsg->msg.hash_stats.hstats[i].src_mac),
+				&(tunmsg->msg.hash_stats.hstats[i].dest_mac));
+	}
+}
+
+/*
+ * nss_nlgre_redir_lag_ds_msg_cb()
+ *	GRE LAG upstream  NSS->HLOS message callback.
+ */
+static void nss_nlgre_redir_lag_ds_msg_cb(void *app_data, struct nss_cmn_msg *cmnmsg)
+{
+	struct nss_gre_redir_lag_ds_msg *tunmsg = (struct nss_gre_redir_lag_ds_msg *)cmnmsg;
+
+	if (tunmsg->cm.type != NSS_GRE_REDIR_LAG_DS_STATS_SYNC_MSG) {
+		return;
+	}
+
+	nss_nl_trace("%px: callback_stats: invalid_dest: %u, exception_cnt: %u\n", tunmsg,
+			tunmsg->msg.ds_sync_stats.ds_stats.dst_invalid,
+			tunmsg->msg.ds_sync_stats.ds_stats.exception_cnt);
+
+}
+
+/*
+ * nss_nlgre_redir_lag_get_lag_pvt_data()
+ * 	Return lag_pvt_data after lock checking
+ */
+static struct nss_nlgre_redir_lag_pvt_data nss_nlgre_redir_lag_get_lag_pvt_data(void)
+{
+	struct nss_nlgre_redir_lag_pvt_data ret_lag_pvt_data;
+
+	spin_lock(&lock);
+	ret_lag_pvt_data = lag_pvt_data;
+	spin_unlock(&lock);
+	return ret_lag_pvt_data;
+}
+
+/*
+ * nss_nlgre_redir_lag_set_lag_pvt_data()
+ * 	Return lag_pvt_data after lock checking
+ */
+static void nss_nlgre_redir_lag_set_lag_pvt_data(struct nss_nlgre_redir_lag_pvt_data *data)
+{
+	spin_lock(&lock);
+	lag_pvt_data = *data;
+	spin_unlock(&lock);
+}
+
+/*
+ * nss_nlgre_redir_lag_destroy_tun()
+ *	Destroy tunnel in LAG mode.
+ */
+int nss_nlgre_redir_lag_destroy_tun(struct net_device *dev)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_redir_get_context();
+	struct nss_nlgre_redir_lag_pvt_data lag_pvt_data;
+	uint8_t tun_idx;
+	int ret;
+
+	if (!dev) {
+		nss_nl_error("%px: Dev is null\n", nss_ctx);
+		return -1;
+	}
+
+	dev_hold(dev);
+
+	/*
+	 * Unregister and deallocate the lag US and DS interfaces
+	 */
+	lag_pvt_data = nss_nlgre_redir_lag_get_lag_pvt_data();
+	ret = nss_gre_redir_lag_us_unregister_and_dealloc(lag_pvt_data.inner_ifnum);
+	if (ret) {
+		nss_nl_error("%px: Unable to deallocate node %d\n", dev, lag_pvt_data.inner_ifnum);
+	}
+
+	ret = nss_gre_redir_lag_ds_unregister_and_dealloc(lag_pvt_data.outer_ifnum);
+	if (ret) {
+		nss_nl_error("%px: Unable to deallocate node %d\n", dev, lag_pvt_data.outer_ifnum);
+	}
+
+	for (tun_idx = 0; tun_idx < NSS_NLGRE_REDIR_LAG_SLAVES; tun_idx++) {
+		if (!lag_pvt_data.slaves[tun_idx]) {
+			nss_nl_error("%px: Slave tunnel index out of range\n", nss_ctx);
+			ret = -1;
+			goto done;
+		}
+
+		ret = nss_nlgre_redir_cmn_destroy_tun(lag_pvt_data.slaves[tun_idx]);
+		if (ret == -1) {
+			nss_nl_error("%px: Unable to destroy tunnel associated with slave %d\n", nss_ctx, tun_idx+1);
+			goto done;
+		}
+
+		nss_nl_info("%px: Successfully destroyed slave tunnel %d\n", nss_ctx, tun_idx+1);
+	}
+
+done:
+	/*
+	 * Free the lag dummy dev resources
+	 */
+	dev_put(dev);
+	unregister_netdev(dev);
+	free_netdev(dev);
+	lag_pvt_data.dev = NULL;
+	return ret;
+}
+
+/*
+ * nss_nlgre_redir_lag_create_tun()
+ * 	Cretate GRE redir tunnel in LAG mode.
+ */
+int nss_nlgre_redir_lag_create_tun(struct nss_nlgre_redir_create_tun *create_params)
+{
+	struct nss_nlgre_redir_lag_pvt_data lag_pvt_data;
+	struct nss_gre_redir_lag_us_config_msg config;
+	struct nss_gre_redir_cmn_ndev_priv *gr;
+	struct nss_ctx_instance *nss_ctx;
+	struct net_device *dummy_dev;
+	bool status;
+	int iter;
+
+	nss_ctx = nss_gre_redir_get_context();
+	lag_pvt_data = nss_nlgre_redir_lag_get_lag_pvt_data();
+	lag_pvt_data.slaves[0] = nss_nlgre_redir_cmn_create_tun(create_params->sip, create_params->dip, create_params->iptype);
+	if (!lag_pvt_data.slaves[0]) {
+		nss_nl_error("%px: Unable to create tunnel for %dst slave\n", nss_ctx, 1);
+		goto fail0;
+	}
+
+	lag_pvt_data.slaves[1] = nss_nlgre_redir_cmn_create_tun(create_params->ssip, create_params->sdip, create_params->iptype);
+	if (!lag_pvt_data.slaves[1]) {
+		nss_nl_error("%px: Unable to create tunnel for %dnd slave\n", nss_ctx, 2);
+		goto fail0;
+	}
+
+	dummy_dev = alloc_netdev(sizeof(*gr), "grelag%d", NET_NAME_UNKNOWN, ether_setup);
+	if (!dummy_dev) {
+		nss_nl_error("%px: Unable to allocate net_dev for dummy_dev\n", nss_ctx);
+		goto fail0;
+	}
+
+	dummy_dev->needed_headroom = NSS_NLGRE_REDIR_CMN_NEEDED_HEADROOM;
+	dummy_dev->netdev_ops = &dummy_netdev_ops;
+	lag_pvt_data.inner_ifnum = nss_gre_redir_lag_us_alloc_and_register_node(dummy_dev,
+			nss_nlgre_redir_lag_us_data_cb, nss_nlgre_redir_lag_us_msg_cb, dummy_dev);
+
+	if (lag_pvt_data.inner_ifnum == -1) {
+		nss_nl_error("%px: Unable to allocate or register LAG US dynamic node.\n", nss_ctx);
+		goto fail1;
+	}
+
+	nss_nl_info("%px: LAG US interface number = %d\n", nss_ctx, lag_pvt_data.inner_ifnum);
+	lag_pvt_data.outer_ifnum = nss_gre_redir_lag_ds_alloc_and_register_node(dummy_dev,
+			nss_nlgre_redir_lag_ds_data_cb, nss_nlgre_redir_lag_ds_msg_cb, dummy_dev);
+
+	if (lag_pvt_data.outer_ifnum == -1) {
+		nss_nl_error("%px: Unable to allocate or register LAG DS dynamic node.\n", nss_ctx);
+		goto fail2;
+	}
+
+	nss_nl_info("%px: LAG DS interface number = %d\n", nss_ctx, lag_pvt_data.outer_ifnum);
+
+	config.hash_mode = create_params->hash_mode;
+	config.num_slaves = NSS_NLGRE_REDIR_LAG_SLAVES;
+
+	for (iter = 0; iter < NSS_NLGRE_REDIR_LAG_SLAVES; iter++) {
+		config.if_num[iter] = nss_nlgre_redir_cmn_get_tun_ifnum(NSS_NLGRE_REDIR_CMN_MODE_TYPE_WIFI, lag_pvt_data.slaves[iter]);
+	}
+
+	status = nss_gre_redir_lag_us_configure_node(lag_pvt_data.inner_ifnum, &config);
+	if (!status) {
+		nss_nl_info("%px: Unable to configure LAG US node.\n", nss_ctx);
+		goto fail3;
+	}
+
+	if (register_netdev(dummy_dev)) {
+		nss_nl_error("%px: Unable to register dummy_dev\n", nss_ctx);
+		goto fail3;
+	}
+
+	lag_pvt_data.dev = dummy_dev;
+	nss_nlgre_redir_lag_set_lag_pvt_data(&lag_pvt_data);
+	return 0;
+
+fail3:
+	nss_nlgre_redir_cmn_unregister_and_deallocate(dummy_dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_DS);
+fail2:
+	nss_nlgre_redir_cmn_unregister_and_deallocate(dummy_dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_US);
+fail1:
+	free_netdev(dummy_dev);
+fail0:
+	for (iter = 0; iter < NSS_NLGRE_REDIR_LAG_SLAVES; iter++) {
+		if (!lag_pvt_data.slaves[iter]) {
+			nss_nlgre_redir_cmn_destroy_tun(lag_pvt_data.slaves[iter]);
+			continue;
+		}
+
+		break;
+	}
+
+	return -1;
+}
+
+/*
+ * nss_nlgre_redir_lag_map_interface()
+ * 	Maps the nss interface to tunnel ID
+ */
+int nss_nlgre_redir_lag_map_interface(struct nss_nlgre_redir_map *map_params)
+{
+	struct nss_nlgre_redir_lag_pvt_data lag_pvt_data;
+	struct nss_ctx_instance *nss_ctx;
+	uint32_t nexthop_nssif;
+	int ret;
+
+	nss_ctx = nss_gre_redir_get_context();
+	lag_pvt_data = nss_nlgre_redir_lag_get_lag_pvt_data();
+	nexthop_nssif = lag_pvt_data.outer_ifnum;
+	ret = nss_nlgre_redir_cmn_map_interface(nexthop_nssif, 1, map_params);
+	if (ret == -1) {
+		nss_nl_error("%px: Unable to map nss interface\n", nss_ctx);
+		return -1;
+	}
+
+	nss_nl_info("Successfully mapped the nss interface to tunnel ID\n");
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_lag_set_next_hop()
+ * 	Sets the next hop of ath0 interface as lag US node's interface
+ */
+int nss_nlgre_redir_lag_set_next_hop(struct nss_nlgre_redir_set_next *set_next_params)
+{
+	struct nss_nlgre_redir_lag_pvt_data lag_pvt_data;
+	struct nss_ctx_instance *nss_ctx;
+	uint32_t nexthop_ifnum;
+	int ret;
+
+	nss_ctx = nss_gre_redir_get_context();
+	lag_pvt_data = nss_nlgre_redir_lag_get_lag_pvt_data();
+	nexthop_ifnum = lag_pvt_data.inner_ifnum;
+	ret = nss_nlgre_redir_cmn_set_next_hop(nexthop_ifnum, set_next_params);
+	if (ret == -1) {
+		nss_nl_error("%px: Unable to set the next hop as lag US node's interface\n", nss_ctx);
+		return -1;
+	}
+
+	nss_nl_info("Successfully set the next hop as lag US node's interface\n");
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_lag_add_hash()
+ *	Add hash entry.
+ */
+int nss_nlgre_redir_lag_add_hash(struct nss_nlgre_redir_hash_ops *hash_ops)
+{
+	struct nss_nlgre_redir_lag_pvt_data lag_pvt_data;
+	struct nss_gre_redir_lag_us_msg *nglm;
+	struct nss_ctx_instance *nss_ctx;
+	nss_tx_status_t status;
+	uint32_t len;
+	int i;
+
+	lag_pvt_data = nss_nlgre_redir_lag_get_lag_pvt_data();
+	nss_ctx = nss_gre_redir_lag_us_get_context();
+	if (!nss_ctx) {
+		nss_nl_error("Unable to get nss context\n");
+		return -1;
+	}
+
+	nglm = kmalloc(sizeof(struct nss_gre_redir_lag_us_msg), GFP_KERNEL);
+	if (!nglm) {
+		nss_nl_error("%px: Unable to allocate memory to send add hash msg.\n", nss_ctx);
+		return -1;
+	}
+
+	len = sizeof(struct nss_gre_redir_lag_us_msg) - sizeof(struct nss_cmn_msg);
+	nss_cmn_msg_init(&nglm->cm, lag_pvt_data.inner_ifnum, NSS_GRE_REDIR_LAG_US_ADD_HASH_NODE_MSG, len,
+			nss_nlgre_redir_lag_msg_completion_cb, NULL);
+	memcpy((void *)(nglm->msg.add_hash.src_mac), (void *)hash_ops->smac, sizeof(nglm->msg.add_hash.src_mac));
+	memcpy((void *)(nglm->msg.add_hash.dest_mac), (void *)hash_ops->dmac, sizeof(nglm->msg.add_hash.dest_mac));
+	for (i = 0; i < NSS_NLGRE_REDIR_LAG_SLAVES; i++) {
+		if (hash_ops->slave != i) {
+			continue;
+		}
+
+		nglm->msg.add_hash.if_num = nss_nlgre_redir_cmn_get_tun_ifnum(NSS_NLGRE_REDIR_CMN_MODE_TYPE_WIFI,
+				lag_pvt_data.slaves[i]);
+		break;
+	}
+
+	if (i == NSS_NLGRE_REDIR_LAG_SLAVES || nglm->msg.add_hash.if_num == -1) {
+		nss_nl_error("%px: Invalid value for index, valid slaves: [%s, %s]\n", nss_ctx,
+				lag_pvt_data.slaves[0]->name, lag_pvt_data.slaves[1]->name);
+		return -1;
+	}
+
+	nss_nl_info("smac = %pM dmac = %pM ifnum = %d\n", &(nglm->msg.add_hash.src_mac),
+			&(nglm->msg.add_hash.dest_mac), nglm->msg.add_hash.if_num);
+	status = nss_gre_redir_lag_us_tx_msg_sync(nss_ctx, nglm);
+	kfree(nglm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_error("%px: Unable to add hash entry.\n", nss_ctx);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nlgre_redir_lag_del_hash()
+ *	Delete hash entry.
+ */
+int nss_nlgre_redir_lag_del_hash(struct nss_nlgre_redir_hash_ops *hash_ops)
+{
+	struct nss_nlgre_redir_lag_pvt_data lag_pvt_data;
+	struct nss_gre_redir_lag_us_msg *nglm;
+	struct nss_ctx_instance *nss_ctx;
+	nss_tx_status_t status;
+	uint32_t len;
+
+	lag_pvt_data = nss_nlgre_redir_lag_get_lag_pvt_data();
+	nss_ctx = nss_gre_redir_lag_us_get_context();
+	if (!nss_ctx) {
+		nss_nl_error("Unable to get nss context\n");
+		return -1;
+	}
+
+	nglm = kmalloc(sizeof(struct nss_gre_redir_lag_us_msg), GFP_KERNEL);
+	if (!nglm) {
+		nss_nl_error("%px: Unable to allocate memory to send del hash msg.\n", nss_ctx);
+		return -1;
+	}
+
+	len = sizeof(struct nss_gre_redir_lag_us_msg) - sizeof(struct nss_cmn_msg);
+	nss_cmn_msg_init(&nglm->cm, lag_pvt_data.inner_ifnum, NSS_GRE_REDIR_LAG_US_DEL_HASH_NODE_MSG, len,
+			nss_nlgre_redir_lag_msg_completion_cb, NULL);
+	memcpy((void *)(nglm->msg.del_hash.src_mac), (void *)hash_ops->smac, sizeof(nglm->msg.del_hash.src_mac));
+	memcpy((void *)(nglm->msg.del_hash.dest_mac), (void *)hash_ops->dmac, sizeof(nglm->msg.del_hash.dest_mac));
+	nss_nl_info("smac = %pM dmac = %pM\n", &(nglm->msg.del_hash.src_mac), &(nglm->msg.del_hash.dest_mac));
+	status = nss_gre_redir_lag_us_tx_msg_sync(nss_ctx, nglm);
+	kfree(nglm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_error("%px: Unable to delete hash entry.\n", nss_ctx);
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/qca-nss-clients/netlink/nss_nlgre_redir_lag.h b/qca-nss-clients/netlink/nss_nlgre_redir_lag.h
new file mode 100644
index 0000000..b0b7ee1
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlgre_redir_lag.h
@@ -0,0 +1,65 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2014-2015,2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#define NSS_NLGRE_REDIR_LAG_SLAVES 2		/**< Maximum number of slaves for lag tunnel */
+
+/*
+ * nss_nlgre_redir_lag_pvt_data
+ * 	Context need to be maintained for LAG deployment.
+ */
+struct nss_nlgre_redir_lag_pvt_data {
+	uint32_t inner_ifnum;			/**< Inner ifnum of lag netdev */
+	uint32_t outer_ifnum;			/**< Outer ifnum of lag netdev */
+	struct net_device *slaves[2];		/**< Slave's dev reference*/
+	struct net_device *dev;			/**< Pointer to netdev for lag */
+};
+
+/*
+ * nss_nlgre_redir_lag_create_tun()
+ *	Creates a lag node and configures LAG US/DS dynamic nodes.
+ */
+int nss_nlgre_redir_lag_create_tun(struct nss_nlgre_redir_create_tun *create_params);
+
+/*
+ * nss_nlgre_redir_lag_destroy_tun()
+ * 	Destroys the lag tunnel.
+ */
+int nss_nlgre_redir_lag_destroy_tun(struct net_device *dev);
+
+/*
+ * nss_nlgre_redir_lag_set_next_hop()
+ * 	Sets the next hop as lag US node
+ */
+int nss_nlgre_redir_lag_set_next_hop(struct nss_nlgre_redir_set_next *set_next_params);
+
+/*
+ * nss_nlgre_redir_lag_map_interface()
+ * 	Maps the vap interface to tunnel ID
+ */
+int nss_nlgre_redir_lag_map_interface(struct nss_nlgre_redir_map *map_params);
+
+/*
+ * nss_nlgre_redir_lag_add_hash()
+ * 	Add hash entry.
+ */
+int nss_nlgre_redir_lag_add_hash(struct nss_nlgre_redir_hash_ops *hash_ops);
+
+/*
+ * nss_nlgre_redir_lag_del_hash()
+ * 	Delete hash entry.
+ */
+int nss_nlgre_redir_lag_del_hash(struct nss_nlgre_redir_hash_ops *hash_ops);
+
diff --git a/qca-nss-clients/netlink/nss_nlipsec.c b/qca-nss-clients/netlink/nss_nlipsec.c
new file mode 100644
index 0000000..24ae58d
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlipsec.c
@@ -0,0 +1,748 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2016,2018-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlipsec.c
+ *	NSS Netlink IPsec Handler
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/if.h>
+#include <linux/netlink.h>
+#include <linux/mutex.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_ipsec.h>
+#include <nss_ipsecmgr.h>
+#include <nss_nl_if.h>
+#include <nss_ipsec_cmn.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nlipsec_if.h"
+#include "nss_nlipv6_if.h"
+#include "nss_nlipv4_if.h"
+
+/*
+ * Function prototypes
+ */
+static int nss_nlipsec_op_create_tunnel(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlipsec_op_destroy_tunnel(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlipsec_op_add_sa(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlipsec_op_delete_sa(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlipsec_op_add_flow(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlipsec_op_delete_flow(struct sk_buff *skb, struct genl_info *info);
+
+/*
+ * Hold netdevice references
+ */
+struct nss_nlipsec_ref {
+	struct mutex lock;	/* Mutex for field access */
+	int ifindex;		/* Device interface index */
+	bool valid;		/* Reference is valid or invalid */
+};
+
+/*
+ * Local context for the NSS_NLIPSEC
+ */
+struct nss_nlipsec_ctx {
+	atomic_t tunnels;	/* Number tunnels allocated */
+
+	/*
+	 * This table stores device reference associated
+	 * to the IPsec tunnel that it has created through NETLINK
+	 * thus prohibiting any spurious attempts to delete
+	 * random net_devices from the Linux kernel
+	 */
+	struct nss_nlipsec_ref ref_tbl[NSS_NLIPSEC_MAX_TUNNELS];
+};
+
+/*
+ * Global context
+ */
+static struct nss_nlipsec_ctx gbl_ctx;
+
+/*
+ * Multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nlipsec_mcgrp[] = {
+	{.name = NSS_NLIPSEC_MCAST_GRP},
+};
+
+/*
+ * Operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nlipsec_ops[] = {
+	{ /* Create tunnel */
+		.cmd = NSS_NLIPSEC_CMD_ADD_TUNNEL,
+		.doit = nss_nlipsec_op_create_tunnel,
+	},
+	{ /* Destroy tunnel */
+		.cmd = NSS_NLIPSEC_CMD_DEL_TUNNEL,
+		.doit = nss_nlipsec_op_destroy_tunnel,
+	},
+	{ /* Add Security Association */
+		.cmd = NSS_NLIPSEC_CMD_ADD_SA,
+		.doit = nss_nlipsec_op_add_sa,
+	},
+	{ /* Delete Security Association */
+		.cmd = NSS_NLIPSEC_CMD_DEL_SA,
+		.doit = nss_nlipsec_op_delete_sa,
+	},
+	{ /* Add flow */
+		.cmd = NSS_NLIPSEC_CMD_ADD_FLOW,
+		.doit = nss_nlipsec_op_add_flow,
+	},
+	{ /* Delete flow */
+		.cmd = NSS_NLIPSEC_CMD_DEL_FLOW,
+		.doit = nss_nlipsec_op_delete_flow,
+	},
+};
+
+/*
+ * IPsec family definition
+ */
+static struct genl_family nss_nlipsec_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,			/* Auto generate ID */
+#endif
+	.name = NSS_NLIPSEC_FAMILY,		/* Family name string */
+	.hdrsize = sizeof(struct nss_nlipsec_rule),/* NSS NETLINK IPsec rule */
+	.version = NSS_NL_VER,			/* Set it to NSS_NL version */
+	.maxattr = NSS_NLIPSEC_CMD_MAX,		/* Maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nlipsec_ops,
+	.n_ops = ARRAY_SIZE(nss_nlipsec_ops),
+	.mcgrps = nss_nlipsec_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nlipsec_mcgrp)
+};
+
+/*
+ * nss_nlipsec_add_ref()
+ *	Add reference to the netdevice object
+ */
+static inline void nss_nlipsec_add_ref(struct net_device *dev)
+{
+	struct nss_nlipsec_ref *ref = gbl_ctx.ref_tbl;
+	int i;
+
+	for (i = 0; i < NSS_NLIPSEC_MAX_TUNNELS; i++, ref++) {
+		mutex_lock(&ref->lock); /* lock_ref */
+
+		if (!ref->valid) {
+			ref->ifindex = dev->ifindex;
+			ref->valid = true;
+
+			mutex_unlock(&ref->lock); /* unlock_ref */
+			return;
+		}
+
+		mutex_unlock(&ref->lock); /* unlock_ref */
+	}
+
+	BUG_ON(i == NSS_NLIPSEC_MAX_TUNNELS);
+}
+
+/*
+ * nss_nlipsec_del_ref()
+ *	delete netdevice reference
+ */
+static inline void nss_nlipsec_del_ref(struct nss_nlipsec_ref *ref)
+{
+	mutex_lock(&ref->lock);	/* lock_ref */
+
+	ref->ifindex = -1;
+	ref->valid = false;
+
+	mutex_unlock(&ref->lock); /* unlock_ref */
+}
+
+/*
+ * nss_nlipsec_find_ref()
+ *	find refernce node for the given netdevice
+ */
+struct nss_nlipsec_ref *nss_nlipsec_find_ref(struct net_device *dev)
+{
+	struct nss_nlipsec_ref *ref = gbl_ctx.ref_tbl;
+	int i;
+
+	for (i = 0; i < NSS_NLIPSEC_MAX_TUNNELS; i++, ref++) {
+
+		mutex_lock(&ref->lock); /* lock_ref */
+
+		if (ref->valid && (dev->ifindex == ref->ifindex)) {
+			mutex_unlock(&ref->lock); /* unlock_ref */
+			return ref;
+		}
+
+		mutex_unlock(&ref->lock); /* unlock_ref */
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_nlipsec_process_event()
+ *	Process events from NSS IPsec manager and MCAST it to user
+ */
+static void nss_nlipsec_process_event(void *ctx, struct nss_ipsecmgr_event *ev)
+{
+	struct nss_nlipsec_rule *nl_rule;
+	struct sk_buff *skb;
+
+	/*
+	 * Allocate a new event message
+	 */
+	skb = nss_nl_new_msg(&nss_nlipsec_family, ev->type);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLIPV4 event\n");
+		return;
+	}
+
+	nl_rule = nss_nl_get_data(skb);
+
+	/*
+	 * Initialize the NETLINK common header
+	 */
+	nss_nlipsec_rule_init(nl_rule, ev->type);
+
+	/*
+	 * Copy the contents of the sync message into the NETLINK message
+	 */
+	memcpy(&nl_rule->rule.event, ev, sizeof(struct nss_ipsecmgr_event));
+
+	nss_nl_mcast_event(&nss_nlipsec_family, skb);
+}
+
+/*
+ * nss_nlipsec_get_ifnum()
+ *	Extract dynamic interface number for inner/outer
+ */
+int nss_nlipsec_get_ifnum(struct net_device *dev, uint8_t proto, uint16_t dest_port, uint16_t src_port)
+{
+	enum nss_dynamic_interface_type type;
+	int ifnum;
+
+	/*
+	 * If the flow is outer, then set the IPsec outer interface type else
+	 * set the inner interface type to obtain interface number.
+	 */
+	switch (proto) {
+	case IPPROTO_ESP:
+		type = NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_OUTER;
+		break;
+
+	case IPPROTO_UDP:
+		if (dest_port == NSS_IPSECMGR_NATT_PORT_DATA)
+			type = NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_OUTER;
+		else if (src_port == NSS_IPSECMGR_NATT_PORT_DATA)
+			type = NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_OUTER;
+		else
+			type = NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_INNER;
+
+		break;
+
+	default:
+		type = NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_INNER;
+		break;
+	}
+
+	ifnum = nss_cmn_get_interface_number_by_dev_and_type(dev, type);
+	if (ifnum < 0) {
+		nss_nl_error("%px: Failed to find interface number (dev:%s, type:%d)\n", dev, dev->name, type);
+		return -1;
+	}
+
+	/*
+	 * Interface number with core-id
+	 */
+	return nss_ipsec_cmn_get_ifnum_with_coreid(ifnum);
+}
+
+/*
+ * nss_nlipsec_get_mtu()
+ * 	Provide maximum mtu if it is an outer flow and maintain minimum mtu
+ */
+int nss_nlipsec_get_mtu(struct net_device *dev, uint8_t ip_ver, uint8_t proto, uint16_t dest_port, uint16_t src_port)
+{
+	int mtu = dev->mtu;
+
+	/*
+	 * If, flow device is IPsec tunnel and protocol is ESP or NAT-T (UDP@4500)
+	 * then the operation is Decapsulation. In this we would like to keep the MTU
+	 * at the maximum(65536). This would avoid fragmenting the  packet in NSS before
+	 * delivering it for IPsec decap. Also, if the device mtu is less than the minimum
+	 * mtu, we set it to the minimum mtu.
+	 */
+	switch (ip_ver) {
+	case 4:
+		if (proto == IPPROTO_ESP)
+			mtu = NSS_NLIPV4_MAX_MTU;
+		else if ((proto == IPPROTO_UDP) && (dest_port == NSS_IPSECMGR_NATT_PORT_DATA))
+			mtu = NSS_NLIPV4_MAX_MTU;
+		else if ((proto == IPPROTO_UDP) && (src_port == NSS_IPSECMGR_NATT_PORT_DATA))
+			mtu = NSS_NLIPV4_MAX_MTU;
+		else if (dev->mtu < NSS_NLIPV4_MIN_MTU)
+			mtu = NSS_NLIPV4_MIN_MTU;
+
+		break;
+	case 6:
+		if (proto == IPPROTO_ESP)
+			mtu = NSS_NLIPV6_MAX_MTU;
+		else if (dev->mtu < NSS_NLIPV6_MIN_MTU)
+			mtu = NSS_NLIPV6_MIN_MTU;
+
+		break;
+	}
+
+	return mtu;
+}
+
+/*
+ * nss_nlipsec_op_create_tunnel()
+ *	Add IPsec tunnel
+ */
+static int nss_nlipsec_op_create_tunnel(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nlipsec_rule *nl_rule;
+	struct nss_ipsecmgr_callback cb = {0};
+	struct nss_nlcmn *nl_cm;
+	struct net_device *dev;
+	struct sk_buff *resp;
+	uint32_t pid;
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlipsec_family, info, NSS_NLIPSEC_CMD_ADD_TUNNEL);
+	if (!nl_cm) {
+		nss_nl_error("unable to extract create tunnel data\n");
+		return -EINVAL;
+	}
+
+	pid = nl_cm->pid;
+
+	if (atomic_read(&gbl_ctx.tunnels) == NSS_NLIPSEC_MAX_TUNNELS) {
+		nss_nl_error("%d: max allowed tunnel reached (%d)\n", pid, NSS_NLIPSEC_MAX_TUNNELS);
+		return -EINVAL;
+	}
+
+	/*
+	 * Create a IPsec tunnel device
+	 */
+	cb.app_data = &gbl_ctx;
+	cb.skb_dev = NULL;
+	cb.data_cb = NULL;
+	cb.event_cb = nss_nlipsec_process_event;
+	dev = nss_ipsecmgr_tunnel_add(&cb);
+	if (!dev) {
+		nss_nl_error("%d:unable to add IPsec tunnel\n", pid);
+		return -ENOMEM;
+	}
+
+	/*
+	 * Add an internal reference to the tunnel dev
+	 */
+	atomic_inc(&gbl_ctx.tunnels);
+	nss_nlipsec_add_ref(dev);
+
+	/*
+	 * Response message to caller
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("unable to copy incoming message\n");
+		goto free_dev;
+	}
+
+	/*
+	 * Overload the nl_rule with the new response address
+	 */
+	nl_rule = nss_nl_get_data(resp);
+
+	/*
+	 * Init the command
+	 */
+	nss_nlipsec_rule_init(nl_rule, NSS_NLIPSEC_CMD_ADD_TUNNEL);
+
+	/*
+	 * We need to send the  name to the user; copy
+	 * the tunnel I/F name into the same rule and send it
+	 * as part of the response for the create operation
+	 */
+	strlcpy(nl_rule->ifname, dev->name, IFNAMSIZ);
+
+	/*
+	 * Send to userspace
+	 */
+	nss_nl_ucast_resp(resp);
+
+	return 0;
+
+free_dev:
+	nss_ipsecmgr_tunnel_del(dev);
+	return -ENOMEM;
+}
+
+/*
+ * nss_nlipsec_op_destroy_tunnel()
+ *	Delete an IPsec tunnel
+ */
+static int nss_nlipsec_op_destroy_tunnel(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nlipsec_rule *nl_rule;
+	struct nss_nlipsec_ref *ref;
+	struct nss_nlcmn *nl_cm;
+	struct net_device *dev;
+	uint32_t pid;
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlipsec_family, info, NSS_NLIPSEC_CMD_DEL_TUNNEL);
+	if (!nl_cm) {
+		nss_nl_error("unable to extract destroy tunnel data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlipsec_rule, cm);
+	pid = nl_cm->pid;
+
+	if (atomic_read(&gbl_ctx.tunnels) == 0) {
+		nss_nl_error("%d: no tunnels available for deletion\n", pid);
+		return -EINVAL;
+	}
+	/*
+	 * Get the the Linux net_device object
+	 */
+	dev = dev_get_by_name(&init_net, nl_rule->ifname);
+	if (!dev) {
+		nss_nl_error("%d: unable to find netdevice (%s)\n", pid, nl_rule->ifname);
+		return -EINVAL;
+	}
+
+	/*
+	 * Find if we have the local reference
+	 */
+	ref = nss_nlipsec_find_ref(dev);
+	if (!ref) {
+		nss_nl_error("%d: (%s) was not created through NL_IPSEC\n", pid, dev->name);
+		dev_put(dev);
+		return -EINVAL;
+	}
+
+	nss_nlipsec_del_ref(ref);
+	atomic_dec(&gbl_ctx.tunnels);
+
+	/*
+	 * Down the ref_cnt held by nss_nlipsec_destroy_tunnel
+	 */
+	dev_put(dev);
+
+	/*
+	 * Delete the tunnel device
+	 */
+	nss_ipsecmgr_tunnel_del(dev);
+
+	return 0;
+}
+
+/*
+ * nss_nlipsec_get_rule()
+ *	Extract the rule message
+ */
+static struct nss_nlipsec_rule *nss_nlipsec_get_rule(struct genl_info *info, enum nss_nlipsec_cmd cmd,
+							struct net_device **dev)
+{
+	struct nss_nlipsec_rule *nl_rule;
+	struct nss_nlipsec_ref *ref;
+	struct nss_nlcmn *nl_cm;
+	uint32_t pid;
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlipsec_family, info, cmd);
+	if (!nl_cm) {
+		nss_nl_error("Unable to extract SA data\n");
+		return NULL;
+	}
+
+	nl_rule = container_of(nl_cm, struct nss_nlipsec_rule, cm);
+
+	pid = nl_cm->pid;
+
+	*dev = dev_get_by_name(&init_net, nl_rule->ifname);
+	if (!(*dev)) {
+		nss_nl_error("%d: Unable to find Linux net_device(%s)\n", pid, nl_rule->ifname);
+		return NULL;
+	}
+
+	ref = nss_nlipsec_find_ref(*dev);
+	if (!ref) {
+		nss_nl_error("%d: (%s) was not created through NL_IPSEC", pid, (*dev)->name);
+		dev_put(*dev);
+		return NULL;
+	}
+	return nl_rule;
+}
+
+/*
+ * nss_nlipsec_op_add_sa()
+ *	Add a Security Association for Encapsulation or Decapsulation
+ */
+static int nss_nlipsec_op_add_sa(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_ipsecmgr_sa_data *sa_data;
+	struct nss_nlipsec_rule_sa *sa_rule;
+	struct nss_nlipsec_rule *nl_rule;
+	struct net_device *dev;
+	struct sk_buff *resp;
+	uint32_t pid, if_num;
+	int error = 0;
+
+	nl_rule = nss_nlipsec_get_rule(info, NSS_NLIPSEC_CMD_ADD_SA, &dev);
+	if (!nl_rule) {
+		nss_nl_error("Failed to extract SA data\n");
+		return -EINVAL;
+	}
+
+	pid = nl_rule->cm.pid;
+	nss_nl_error("%d: device(%s)", pid, dev->name);
+
+	/*
+	 * Get the SA rule and data from the message
+	 */
+	sa_rule = &nl_rule->rule.sa;
+	sa_data = &nl_rule->rule.sa.data;
+
+	/*
+	 * Switch to kernel pointers
+	 */
+	sa_data->cmn.keys.cipher_key = sa_rule->cipher_key;
+	sa_data->cmn.keys.auth_key = sa_rule->auth_key;
+	sa_data->cmn.keys.nonce = sa_rule->nonce;
+
+	error = nss_ipsecmgr_sa_add_sync(dev, &sa_rule->tuple, sa_data, &if_num);
+	if (error) {
+		nss_nl_error("%d: Failed to add SA for net device(%s), error:%d\n", pid, nl_rule->ifname, error);
+		goto free_dev;
+	}
+
+	/*
+	 * Response message to caller
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("unable to copy incoming message\n");
+		error = -ENOMEM;
+		goto free_dev;
+	}
+
+	/*
+	 * Overload the nl_rule with the new response address
+	 */
+	nl_rule = nss_nl_get_data(resp);
+
+	/*
+	 * Init the command
+	 */
+	nss_nlipsec_rule_init(nl_rule, NSS_NLIPSEC_CMD_ADD_SA);
+
+	/*
+	 * We need to send the ifnum to the user; copy
+	 * the if_number into the same rule and send it
+	 * as part of the response for the create operation
+	 */
+	nl_rule->ifnum = if_num;
+
+	/*
+	 * Send to userspace
+	 */
+	nss_nl_ucast_resp(resp);
+
+free_dev:
+	/*
+	 *  dev_put for dev_get done on nss_nlipsec_get_rule
+	 */
+	dev_put(dev);
+	return error;
+}
+
+/*
+ * nss_nlipsec_op_delete_sa()
+ *	Delete a Security Association for Encapsulation or Decapsulation
+ */
+static int nss_nlipsec_op_delete_sa(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nlipsec_rule *nl_rule;
+	struct net_device *dev;
+	uint32_t pid;
+
+	nl_rule = nss_nlipsec_get_rule(info, NSS_NLIPSEC_CMD_DEL_SA, &dev);
+	if (!nl_rule) {
+		nss_nl_error("Failed to extract SA data\n");
+		return -EINVAL;
+	}
+
+	pid = nl_rule->cm.pid;
+	nss_nl_error("%d: device(%s)", pid, dev->name);
+
+	nss_ipsecmgr_sa_del(dev, &nl_rule->rule.sa.tuple);
+
+	/*
+	 *  dev_put for dev_get done on nss_nlipsec_get_rule
+	 */
+	dev_put(dev);
+	return 0;
+}
+
+/*
+ * nss_nlipsec_op_add_flow()
+ *	Add a flow
+ */
+static int nss_nlipsec_op_add_flow(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_ipsecmgr_flow_tuple *flow_tuple;
+	struct nss_ipsecmgr_sa_tuple *sa_tuple;
+	struct nss_nlipsec_rule *nl_rule;
+	struct net_device *dev;
+	uint32_t pid;
+	int error = 0;
+
+	nl_rule = nss_nlipsec_get_rule(info, NSS_NLIPSEC_CMD_ADD_FLOW, &dev);
+	if (!nl_rule) {
+		nss_nl_error("Failed to extract SA data\n");
+		return -EINVAL;
+	}
+
+	pid = nl_rule->cm.pid;
+	nss_nl_error("%d: device(%s)", pid, dev->name);
+
+	flow_tuple = &nl_rule->rule.flow.tuple;
+	sa_tuple = &nl_rule->rule.flow.sa;
+
+	error = nss_ipsecmgr_flow_add_sync(dev, flow_tuple, sa_tuple);
+	if (error) {
+		nss_nl_error("%d: Failed to add subnet for net_device(%s)", pid, nl_rule->ifname);
+	}
+
+	/*
+	 *  dev_put for dev_get done on nss_nlipsec_get_rule
+	 */
+	dev_put(dev);
+	return error;
+}
+
+/*
+ * nss_nlipsec_op_delete_flow()
+ *	Delete a flow
+ */
+static int nss_nlipsec_op_delete_flow(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_ipsecmgr_flow_tuple *flow_tuple;
+	struct nss_ipsecmgr_sa_tuple *sa_tuple;
+	struct nss_nlipsec_rule *nl_rule;
+	struct net_device *dev;
+	uint32_t pid;
+	int error = 0;
+
+	nl_rule = nss_nlipsec_get_rule(info, NSS_NLIPSEC_CMD_DEL_FLOW, &dev);
+	if (!nl_rule) {
+		nss_nl_error("Failed to extract SA data\n");
+		return -EINVAL;
+	}
+
+	pid = nl_rule->cm.pid;
+	nss_nl_error("%d: device(%s)", pid, dev->name);
+
+	flow_tuple = &nl_rule->rule.flow.tuple;
+	sa_tuple = &nl_rule->rule.flow.sa;
+
+	nss_ipsecmgr_flow_del(dev, flow_tuple, sa_tuple);
+
+	/*
+	 *  dev_put for dev_get done on nss_nlipsec_get_rule
+	 */
+	dev_put(dev);
+	return error;
+}
+
+/*
+ * nss_nlipsec_init()
+ *	Netlink IPsec handler initialization
+ */
+bool nss_nlipsec_init(void)
+{
+	struct nss_nlipsec_ref *ref = gbl_ctx.ref_tbl;
+	int error;
+	int i;
+
+	nss_nl_info_always("Init NSS netlink IPsec handler\n");
+
+	/*
+	 * Initialize reference table
+	 */
+	for (i = 0; i < NSS_NLIPSEC_MAX_TUNNELS; i++, ref++) {
+		mutex_init(&ref->lock);
+		ref->valid = false;
+		ref->ifindex = -1;
+	}
+
+	/*
+	 * Register with the family
+	 */
+	error = genl_register_family(&nss_nlipsec_family);
+	if (error != 0) {
+		nss_nl_info_always("Error: unable to register IPsec family\n");
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nlipsec_exit()
+ *	Netlink IPsec handler exit
+ */
+bool nss_nlipsec_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink IPsec handler\n");
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nlipsec_family);
+	if (error != 0) {
+		nss_nl_info_always("Unregister IPsec NETLINK family failed\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nlipsec.h b/qca-nss-clients/netlink/nss_nlipsec.h
new file mode 100644
index 0000000..9c8bb51
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlipsec.h
@@ -0,0 +1,66 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014 - 2015, 2019 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlipsec.h
+ *	NSS Netlink IPsec API definitions
+ */
+#ifndef __NSS_NLIPSEC_H
+#define __NSS_NLIPSEC_H
+
+
+
+#if (CONFIG_NSS_NLIPSEC == 1)
+#define NSS_NLIPSEC_INIT nss_nlipsec_init
+#define NSS_NLIPSEC_EXIT nss_nlipsec_exit
+
+bool nss_nlipsec_init(void);
+bool nss_nlipsec_exit(void);
+
+/*
+ * Get dynamic interface number for inner/outer
+ */
+int nss_nlipsec_get_ifnum(struct net_device *dev, uint8_t proto, uint16_t dest_port, uint16_t src_port);
+
+/*
+ * Get mtu for IPsec tunnel
+ */
+int nss_nlipsec_get_mtu(struct net_device *dev, uint8_t ip_ver, uint8_t proto, uint16_t dest_port, uint16_t src_port);
+
+#else
+#define NSS_NLIPSEC_INIT 0
+#define NSS_NLIPSEC_EXIT 0
+
+/*
+ * Stub functions
+ */
+static inline int nss_nlipsec_get_ifnum(struct net_device *dev, uint8_t proto, uint16_t dest_port, uint16_t src_port)
+{
+	nss_nl_error("%p: Unsupported protocol interface number (dev:%s)\n", dev, dev->name);
+	return -1;
+}
+
+/*
+ * Stub functions
+ */
+static inline int nss_nlipsec_get_mtu(struct net_device *dev, uint8_t ip_ver, uint8_t proto, uint16_t dest_port,
+					uint16_t src_port)
+{
+	return dev->mtu;
+}
+
+#endif /* !CONFIG_NSS_NLIPSEC */
+#endif /* __NSS_NLIPSEC_H */
diff --git a/qca-nss-clients/netlink/nss_nlipv4.c b/qca-nss-clients/netlink/nss_nlipv4.c
new file mode 100644
index 0000000..d549427
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlipv4.c
@@ -0,0 +1,1024 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlipv4.c
+ *	NSS Netlink IPv4 Handler
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/version.h>
+#include <linux/if.h>
+#include <linux/in.h>
+#include <linux/netlink.h>
+#include <linux/rcupdate.h>
+#include <linux/etherdevice.h>
+#include <linux/if_addr.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/if_vlan.h>
+#include <linux/completion.h>
+#include <linux/semaphore.h>
+#include <linux/in.h>
+
+#include <net/arp.h>
+#include <net/genetlink.h>
+#include <net/neighbour.h>
+#include <net/net_namespace.h>
+#include <net/route.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_ipsec.h"
+#include "nss_ipsec_cmn.h"
+#include "nss_ipsecmgr.h"
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nlgre_redir_cmd.h"
+#include "nss_nlipsec_if.h"
+#include "nss_nlipsec.h"
+#include "nss_nlipv4_if.h"
+#include "nss_ipv4.h"
+/*
+ * NSS NETLINK IPv4 context
+ */
+struct nss_nlipv4_ctx {
+	void *nss;
+};
+
+/*
+ * prototypes
+ */
+static int nss_nlipv4_ops_create_rule(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlipv4_ops_destroy_rule(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlipv4_process_notify(struct notifier_block *nb, unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nlipv4_mcgrp[] = {
+	{.name = NSS_NLIPV4_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nlipv4_ops[] = {
+	{.cmd = NSS_IPV4_TX_CREATE_RULE_MSG, .doit = nss_nlipv4_ops_create_rule,},	/* rule create */
+	{.cmd = NSS_IPV4_TX_DESTROY_RULE_MSG, .doit = nss_nlipv4_ops_destroy_rule,},	/* rule destroy */
+};
+
+/*
+ * IPv4 family definition
+ */
+static struct genl_family nss_nlipv4_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,				/* Auto generate ID */
+#endif
+	.name = NSS_NLIPV4_FAMILY,			/* family name string */
+	.hdrsize = sizeof(struct nss_nlipv4_rule),	/* NSS NETLINK IPv4 rule */
+	.version = NSS_NL_VER,				/* Set it to NSS_NLIPv4 version */
+	.maxattr = NSS_IPV4_MAX_MSG_TYPES,		/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nlipv4_ops,
+	.n_ops = ARRAY_SIZE(nss_nlipv4_ops),
+	.mcgrps = nss_nlipv4_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nlipv4_mcgrp)
+};
+
+/*
+ * statistics call back handler for ipv4 from NSS
+ */
+static struct notifier_block nss_ipv4_stats_notifier_nb = {
+	.notifier_call = nss_nlipv4_process_notify,
+};
+
+#define NSS_NLIPV4_OPS_SZ ARRAY_SIZE(nss_nlipv4_ops)
+
+static struct nss_nlipv4_ctx gbl_ctx;
+
+/*
+ * nss_nlipv4_get_neigh()
+ * 	Returns neighbour reference for a given IP address
+ */
+static struct neighbour *nss_nlipv4_get_neigh(uint32_t ip_addr)
+{
+	struct neighbour *neigh;
+	struct rtable *rt;
+	struct dst_entry *dst;
+
+	/*
+	 * search for route entry
+	 */
+	rt = ip_route_output(&init_net, ip_addr, 0, 0, 0);
+	if (IS_ERR(rt)) {
+		return NULL;
+	}
+
+	dst = (struct dst_entry *)rt;
+
+	/*
+	 * neighbour lookup using IP address in the route table
+	 */
+	neigh = dst_neigh_lookup(dst, &ip_addr);
+	if (likely(neigh)) {
+		dst_release(dst);
+
+		return neigh;
+	}
+
+	/*
+	 * neighbour lookup using IP address, device in the arp table
+	 */
+	neigh = neigh_lookup(&arp_tbl, &ip_addr, dst->dev);
+	if (likely(neigh)) {
+		dst_release(dst);
+		return neigh;
+	}
+
+	/*
+	 * dst reference count was held during the lookup
+	 */
+	dst_release(dst);
+	return NULL;
+}
+
+/*
+ * nss_nlipv4_mac_addr_get()
+ * 	Return the hardware (MAC) address of the given IPv4 address, if any.
+ *
+ * Returns 0 on success or a negative result on failure.
+ * We look up the rtable entry for the address and,
+ * from its neighbour structure,obtain the hardware address.
+ * This means we will also work if the neighbours are routers too.
+ */
+static int nss_nlipv4_get_macaddr(uint32_t ip_addr, uint8_t mac_addr[])
+{
+	struct neighbour *neigh;
+
+	/*
+	 * handle multicast IP address seperately
+	 */
+	if (ipv4_is_multicast(htonl(ip_addr))) {
+		/*
+		 * fixed
+		 */
+		mac_addr[0] = 0x01;
+		mac_addr[1] = 0x00;
+		mac_addr[2] = 0x5e;
+
+		/*
+		 * from ip_addr
+		 */
+		mac_addr[3] = (htonl(ip_addr) & 0x7f0000) >> 16;
+		mac_addr[4] = (htonl(ip_addr) & 0xff00) >> 8;
+		mac_addr[5] = (htonl(ip_addr) & 0xff);
+
+		return 0;
+	}
+
+	rcu_read_lock();
+
+	/*
+	 * retrieve the neighbour
+	 */
+	neigh = nss_nlipv4_get_neigh(htonl(ip_addr));
+	if (!neigh) {
+		rcu_read_unlock();
+		nss_nl_info("neighbour lookup failed for IP:0x%x\n", htonl(ip_addr));
+		return -ENODEV;
+	}
+
+	rcu_read_unlock();
+
+	if ((neigh->nud_state & NUD_VALID) == 0) {
+		nss_nl_info("neighbour state is invalid for IP:0x%x\n", htonl(ip_addr));
+		goto fail;
+	}
+
+	if (!neigh->dev) {
+		nss_nl_info("neighbour device not found for IP:0x%x\n", htonl(ip_addr));
+		goto fail;
+	}
+
+	if (is_multicast_ether_addr(neigh->ha)) {
+		nss_nl_info( "neighbour MAC address is multicast or broadcast\n");
+		goto fail;
+	}
+
+	ether_addr_copy(mac_addr, neigh->ha);
+	neigh_release(neigh);
+	return 0;
+fail:
+
+	neigh_release(neigh);
+	return -ENODEV;
+}
+
+/*
+ * nss_nlipv4_verify_5tuple()
+ * 	verify and override 5-tuple entries
+ */
+static int nss_nlipv4_verify_5tuple(struct nss_ipv4_5tuple *tuple)
+{
+	bool ident_check = false;
+
+	/*
+	 * protocol, flow ip and return ip  must be provided
+	 */
+	if (!tuple->protocol || !tuple->flow_ip || !tuple->return_ip) {
+		nss_nl_info("Empty protocol or flow_ip or return_ip for 5-tuple\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Validate the port number
+	 */
+	switch (tuple->protocol) {
+	case IPPROTO_UDP:
+	case IPPROTO_TCP:
+	case IPPROTO_SCTP:
+		ident_check = true;
+		break;
+
+	default:
+		if (tuple->flow_ident || tuple->return_ident) {
+			nss_nl_error("Flow ident and return ident must be zero. Flow ident:%d return ident:%d protocol:%d\n",
+					tuple->flow_ident, tuple->return_ident, tuple->protocol);
+			return -EINVAL;
+		}
+		ident_check = false;
+		break;
+	}
+
+	if (ident_check && (!tuple->flow_ident || !tuple->return_ident)) {
+		nss_nl_info("Empty idents flow port:%d return port:%d\n", tuple->flow_ident, tuple->return_ident);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nlipv4_verify_conn_rule()
+ * 	verify and override connection rule entries
+ */
+static int nss_nlipv4_verify_conn_rule(struct nss_ipv4_rule_create_msg *msg, struct net_device *flow_dev,
+					struct net_device *return_dev, enum nss_nl_iftype flow_iftype,
+					enum nss_nl_iftype return_iftype)
+{
+	struct nss_ipv4_connection_rule *conn = &msg->conn_rule;
+	struct nss_ipv4_nexthop *nexthop = &msg->nexthop_rule;
+        struct nss_ipv4_5tuple *tuple = &msg->tuple;
+	const size_t rule_sz = sizeof(struct nss_ipv4_connection_rule);
+	bool valid;
+
+	/*
+	 * Connection rule is not valid ignore rest of the checks
+	 */
+	valid = msg->valid_flags & NSS_IPV4_RULE_CREATE_CONN_VALID;
+	if (!valid) {
+		memset(conn, 0, rule_sz);
+		return -EINVAL;
+	}
+
+	if ((flow_iftype >= NSS_NL_IFTYPE_MAX) || (return_iftype >= NSS_NL_IFTYPE_MAX)) {
+		nss_nl_error("%px: Invalid interface type (flow:%d, return:%d)\n", msg, flow_iftype, return_iftype);
+		return -EINVAL;
+	}
+
+	/*
+	 * Update the flow  & return MAC address
+	 */
+	if (nss_nlipv4_get_macaddr(tuple->flow_ip, (uint8_t *)conn->flow_mac)) {
+		nss_nl_info("Error in Updating the Flow MAC Address \n");
+		return -EINVAL;
+	}
+
+	if (nss_nlipv4_get_macaddr(tuple->return_ip, (uint8_t *)conn->return_mac)) {
+		nss_nl_info("Error in Updating the Return MAC Address \n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Update flow interface number and flow mtu
+	 */
+	switch (flow_iftype) {
+	case NSS_NL_IFTYPE_TUNNEL_IPSEC:
+		conn->flow_interface_num = nss_nlipsec_get_ifnum(flow_dev, tuple->protocol,
+								tuple->return_ident, tuple->flow_ident);
+		if (conn->flow_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get flow interface number (dev:%s, type:%d)\n",
+							flow_dev, flow_dev->name, flow_iftype);
+			return -EINVAL;
+		}
+
+		conn->flow_mtu = nss_nlipsec_get_mtu(flow_dev, 4, tuple->protocol,
+							tuple->return_ident, tuple->flow_ident);
+		break;
+
+	case NSS_NL_IFTYPE_TUNNEL_GRE:
+		/*
+		 * Currently this implementation is only for gre_redir
+		 */
+		conn->flow_interface_num = nss_nlgre_redir_cmd_get_ifnum(flow_dev, tuple->protocol);
+		if (conn->flow_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get flow interface number (dev:%s, type:%d)\n",
+								flow_dev, flow_dev->name, flow_iftype);
+			return -EINVAL;
+		}
+
+		conn->flow_mtu = nss_nlgre_redir_cmd_get_mtu(flow_dev, NSS_GRE_REDIR_IP_HDR_TYPE_IPV4, conn->flow_interface_num);
+		break;
+
+	case NSS_NL_IFTYPE_VLAN:
+		conn->flow_interface_num = nss_cmn_get_interface_number_by_dev(vlan_dev_real_dev(flow_dev));
+		if (conn->flow_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get flow interface number (dev:%s, type:%d)\n",
+					flow_dev, flow_dev->name, flow_iftype);
+			return -EINVAL;
+		}
+
+		conn->flow_mtu = flow_dev->mtu;
+		break;
+
+	case NSS_NL_IFTYPE_PHYSICAL:
+		conn->flow_interface_num = nss_cmn_get_interface_number_by_dev(flow_dev);
+		if (conn->flow_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get flow interface number (dev:%s, type:%d)\n",
+					flow_dev, flow_dev->name, flow_iftype);
+			return -EINVAL;
+		}
+
+		conn->flow_mtu = flow_dev->mtu;
+		break;
+
+	default:
+		nss_nl_error("%px: Unsupported flow interface type (%d)\n", msg, flow_iftype);
+		return -EINVAL;
+	}
+
+	nss_nl_info("%px: dev=%s flow_ifnum:0x%x flow_mtu=%d\n", msg, flow_dev->name,
+			conn->flow_interface_num, conn->flow_mtu);
+	/*
+	 * Update return interface number and return mtu
+	 */
+	switch (return_iftype) {
+	case NSS_NL_IFTYPE_TUNNEL_IPSEC:
+		conn->return_interface_num = nss_nlipsec_get_ifnum(return_dev, tuple->protocol,
+									tuple->return_ident, tuple->flow_ident);
+		if (conn->return_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get return interface number (dev:%s, type:%d)\n",
+					return_dev, return_dev->name, return_iftype);
+			return -EINVAL;
+		}
+
+		conn->return_mtu = nss_nlipsec_get_mtu(return_dev, 4, tuple->protocol,
+							tuple->return_ident, tuple->flow_ident);
+		break;
+
+	case NSS_NL_IFTYPE_TUNNEL_GRE:
+		conn->return_interface_num = nss_nlgre_redir_cmd_get_ifnum(return_dev, tuple->protocol);
+		if (conn->return_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get return interface number (dev:%s, type:%d)\n",
+							return_dev, return_dev->name, return_iftype);
+			return -EINVAL;
+		}
+
+		conn->return_mtu = nss_nlgre_redir_cmd_get_mtu(return_dev, NSS_GRE_REDIR_IP_HDR_TYPE_IPV4, conn->return_interface_num);
+		break;
+
+	case NSS_NL_IFTYPE_VLAN:
+		conn->return_interface_num = nss_cmn_get_interface_number_by_dev(vlan_dev_real_dev(return_dev));
+		if (conn->return_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get return interface number (dev:%s, type:%d)\n",
+					return_dev, return_dev->name, return_iftype);
+			return -EINVAL;
+		}
+
+		conn->return_mtu = return_dev->mtu;
+		break;
+
+	case NSS_NL_IFTYPE_PHYSICAL:
+		conn->return_interface_num = nss_cmn_get_interface_number_by_dev(return_dev);
+		if (conn->return_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get return interface number (dev:%s, type:%d)\n",
+					return_dev, return_dev->name, return_iftype);
+			return -EINVAL;
+		}
+
+		conn->return_mtu = return_dev->mtu;
+		break;
+
+	default:
+		nss_nl_error("%px: Unsupported return interface type (%d)\n", msg, flow_iftype);
+		return -EINVAL;
+	}
+
+	nss_nl_info("%px: dev=%s return_ifnum:0x%x return_mtu=%d\n", msg, return_dev->name,
+			conn->return_interface_num, conn->return_mtu);
+
+	nexthop->flow_nexthop = conn->flow_interface_num;
+	nexthop->return_nexthop = conn->return_interface_num;
+
+	nss_nl_info("flow_nexthop:%d return_nexthop:%d\n", nexthop->flow_nexthop, nexthop->return_nexthop);
+
+	/*
+	 * update flow & return xlate info
+	 */
+	conn->flow_ip_xlate = msg->tuple.flow_ip;
+	conn->flow_ident_xlate = msg->tuple.flow_ident;
+	conn->return_ip_xlate = msg->tuple.return_ip;
+	conn->return_ident_xlate = msg->tuple.return_ident;
+
+	return 0;
+}
+
+/*
+ * nss_nlipv4_verify_tcp_rule()
+ *	verify and override TCP protocol rule entries
+ */
+static int nss_nlipv4_verify_tcp_rule(struct nss_ipv4_rule_create_msg *msg)
+{
+	struct nss_ipv4_protocol_tcp_rule *tcp = &msg->tcp_rule;
+	const size_t rule_sz = sizeof(struct nss_ipv4_protocol_tcp_rule);
+	bool valid;
+
+	valid = msg->valid_flags & NSS_IPV4_RULE_CREATE_TCP_VALID;
+
+	/*
+	 * tcp rule is not valid ignore rest of the checks
+	 */
+	if (!valid){
+		memset(tcp, 0, rule_sz);
+		return 0;
+	}
+
+	/*
+	 * XXX: add addtional checks as required
+	 */
+
+	return 0;
+}
+
+/*
+ * nss_nlipv4_verify_pppoe_rule()
+ * 	verify and override pppoe rule entries
+ */
+static int nss_nlipv4_verify_pppoe_rule(struct nss_ipv4_rule_create_msg *msg)
+{
+	struct nss_ipv4_pppoe_rule *pppoe = &msg->pppoe_rule;
+	const size_t rule_sz = sizeof(struct nss_ipv4_pppoe_rule);
+	bool valid;
+
+	valid = msg->valid_flags & NSS_IPV4_RULE_CREATE_PPPOE_VALID;
+
+	/*
+	 * pppoe rule is not valid ignore rest of the checks
+	 */
+	if (!valid){
+		memset(pppoe, 0, rule_sz);
+		return 0;
+	}
+
+	/*
+	 * XXX: add addtional checks as required
+	 */
+	return 0;
+}
+
+/*
+ * nss_nlipv4_verify_qos_rule()
+ * 	verify and override qos rule entries
+ */
+static int nss_nlipv4_verify_qos_rule(struct nss_ipv4_rule_create_msg *msg)
+{
+	struct nss_ipv4_qos_rule *qos = &msg->qos_rule;
+	const size_t rule_sz = sizeof(struct nss_ipv4_qos_rule);
+	bool valid;
+
+	valid = msg->valid_flags & NSS_IPV4_RULE_CREATE_QOS_VALID;
+
+	/*
+	 * qos rule is not valid ignore rest of the checks
+	 */
+	if (!valid){
+		memset(qos, 0, rule_sz);
+		return 0;
+	}
+
+	/*
+	 * XXX: add addtional checks as required
+	 */
+	return 0;
+}
+
+/*
+ * nss_nlipv4_verify_igs_rule()
+ * 	Verify and override ingress shaping rule entries.
+ */
+static int nss_nlipv4_verify_igs_rule(struct nss_ipv4_rule_create_msg *msg)
+{
+	struct nss_ipv4_igs_rule *igs = &msg->igs_rule;
+	const size_t rule_sz = sizeof(struct nss_ipv4_igs_rule);
+	bool valid;
+
+	valid = msg->valid_flags & NSS_IPV4_RULE_CREATE_IGS_VALID;
+
+	/*
+	 * ingress shaping rule is not valid ignore rest of the checks
+	 */
+	if (!valid) {
+		memset(igs, 0, rule_sz);
+		return 0;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nlipv4_verify_dscp_rule()
+ * 	verify and override dscp rule entries
+ */
+static int nss_nlipv4_verify_dscp_rule(struct nss_ipv4_rule_create_msg *msg)
+{
+	struct nss_ipv4_dscp_rule *dscp = &msg->dscp_rule;
+	const size_t rule_sz = sizeof(struct nss_ipv4_dscp_rule);
+	bool valid;
+
+	valid = msg->valid_flags & NSS_IPV4_RULE_CREATE_DSCP_MARKING_VALID;
+
+	/*
+	 * dscp rule is not valid ignore rest of the checks
+	 */
+	if (!valid){
+		memset(dscp, 0, rule_sz);
+		return 0;
+	}
+
+	/*
+	 * XXX: add addtional checks as required
+	 */
+	return 0;
+}
+
+/*
+ * nss_nlipv4_verify_vlan_rule()
+ * 	verify and override vlan rule entries
+ */
+static int nss_nlipv4_verify_vlan_rule(struct nss_ipv4_rule_create_msg *msg,
+		struct net_device *flow_dev, struct net_device *return_dev)
+{
+	struct nss_ipv4_vlan_rule *vlan_primary = &msg->vlan_primary_rule;
+	struct nss_ipv4_vlan_rule *vlan_secondary = &msg->vlan_secondary_rule;
+	bool flow_vlan = is_vlan_dev(flow_dev);
+	bool return_vlan = is_vlan_dev(return_dev);
+
+	/*
+	 * Fill all with default values.
+	 */
+	vlan_primary->ingress_vlan_tag = NSS_NLIPV4_VLAN_ID_NOT_CONFIGURED;
+	vlan_primary->egress_vlan_tag = NSS_NLIPV4_VLAN_ID_NOT_CONFIGURED;
+
+	vlan_secondary->ingress_vlan_tag = NSS_NLIPV4_VLAN_ID_NOT_CONFIGURED;
+	vlan_secondary->egress_vlan_tag = NSS_NLIPV4_VLAN_ID_NOT_CONFIGURED;
+
+	if (!flow_vlan && !return_vlan)
+		return 0;
+
+	msg->valid_flags |= NSS_IPV4_RULE_CREATE_VLAN_VALID;
+
+	/*
+	 * Add single VLAN
+	 */
+	if (flow_vlan)
+		vlan_primary->ingress_vlan_tag = ETH_P_8021Q << 16 | vlan_dev_vlan_id(flow_dev);
+
+	if (return_vlan)
+		vlan_primary->egress_vlan_tag = ETH_P_8021Q << 16 | vlan_dev_vlan_id(return_dev);
+
+	/*
+	 * XXX: add addtional checks as required
+	 */
+	return 0;
+}
+
+/*
+ * nss_nlipv4_verify_identifier()
+ *	verify and override identifier rule entries
+ */
+static int nss_nlipv4_verify_identifier(struct nss_ipv4_rule_create_msg *msg)
+{
+	struct nss_ipv4_identifier_rule *identifier = &msg->identifier;
+	const size_t rule_sz = sizeof(struct nss_ipv4_identifier_rule);
+	uint16_t valid;
+
+	/*
+	 * if identifier is not valid, set identifier rule to 0
+	 */
+	valid = msg->valid_flags & NSS_IPV4_RULE_CREATE_IDENTIFIER_VALID;
+	if (!valid) {
+		memset(identifier, 0, rule_sz);
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nlipv4_process_notify()
+ * 	process notification messages from NSS
+ */
+static int nss_nlipv4_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct nss_nlipv4_rule *nl_rule;
+	struct sk_buff *skb;
+	struct nss_ipv4_stats_notification *nss_stats;
+
+	skb = nss_nl_new_msg(&nss_nlipv4_family, NSS_NLCMN_SUBSYS_IPV4);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLIPV4 event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_rule = nss_nl_get_data(skb);
+	nss_stats = (struct nss_ipv4_stats_notification *)data;
+	memcpy(&nl_rule->stats, nss_stats, sizeof(struct nss_ipv4_stats_notification));
+	nss_nl_mcast_event(&nss_nlipv4_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nlipv4_resp_create_rule()
+ * 	handle response for create rule
+ */
+static void nss_nlipv4_process_resp(void *app_data, struct nss_ipv4_msg *nim)
+{
+	struct sk_buff *resp = (struct sk_buff *)app_data;
+	struct nss_nlipv4_rule *nl_rule;
+	struct nss_ipv4_msg *nl_nim;
+
+	nl_rule = nss_nl_get_data(resp);
+	nl_nim = &nl_rule->nim;
+
+	/*
+	 * clear NSS common message items that are not useful to uspace
+	 */
+	nim->cm.interface = 0;
+	nim->cm.cb = (nss_ptr_t)NULL;
+	nim->cm.app_data = (nss_ptr_t)NULL;
+
+	/*
+	 * copy the message response data into the NL message buffer. If, FW
+	 * has updated the message then we must updated the same into the NL
+	 * message as the NL message buffer is different from what was sent
+	 * to FW
+	 */
+	memcpy(nl_nim, nim, sizeof(struct nss_ipv4_msg));
+
+	nss_nl_ucast_resp(resp);
+}
+
+/*
+ * nss_nlipv4_ops_create_rule()
+ * 	rule create handler
+ */
+static int nss_nlipv4_ops_create_rule(struct sk_buff *skb, struct genl_info *info)
+{
+	struct net_device *return_dev;
+	struct net_device *flow_dev;
+	struct nss_nlipv4_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	struct nss_ipv4_msg *nim;
+	nss_tx_status_t tx_status;
+	struct sk_buff *resp;
+	uint32_t pid;
+	int error;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlipv4_family, info, NSS_IPV4_TX_CREATE_RULE_MSG);
+	if (!nl_cm) {
+		nss_nl_error("unable to extract rule create data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlipv4_rule, cm);
+	nim = &nl_rule->nim;
+	pid = nl_cm->pid;
+
+	/*
+	 * extract netdevices for flow and return
+	 */
+	flow_dev = dev_get_by_name(&init_net, nl_rule->flow_ifname);
+	if (!flow_dev) {
+		nss_nl_error("%d:flow interface(%s) is not available\n", pid, nl_rule->flow_ifname);
+		return -EINVAL;
+	}
+
+	return_dev = dev_get_by_name(&init_net, nl_rule->return_ifname);
+	if (!return_dev) {
+		dev_put(flow_dev);
+		nss_nl_error("%d:return interface(%s) is not available\n", pid, nl_rule->return_ifname);
+		return -EINVAL;
+	}
+
+	/*
+	 * check 5-tuple
+	 */
+	error = nss_nlipv4_verify_5tuple(&nim->msg.rule_create.tuple);
+	if (error < 0) {
+		nss_nl_error("%d:invalid 5-tuple information passed\n", pid);
+		goto done;
+	}
+
+	nss_nl_info("Checking rule for srcif(%s) src_type(%d) destif(%s) dest_type(%d)\n", nl_rule->flow_ifname,
+			nl_rule->flow_iftype, nl_rule->return_ifname, nl_rule->return_iftype);
+
+	/*
+	 * check connection rule
+	 */
+	error = nss_nlipv4_verify_conn_rule(&nim->msg.rule_create, flow_dev, return_dev,
+						nl_rule->flow_iftype, nl_rule->return_iftype);
+	if (error < 0) {
+		nss_nl_error("%d:invalid conn rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * check tcp protocol rule
+	 */
+	error = nss_nlipv4_verify_tcp_rule(&nim->msg.rule_create);
+	if (error < 0) {
+		nss_nl_error("%d:invalid tcp rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * check pppoe rule
+	 */
+	error = nss_nlipv4_verify_pppoe_rule(&nim->msg.rule_create);
+	if (error < 0) {
+		nss_nl_error("%d:invalid pppoe rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * check qos rule
+	 */
+	error = nss_nlipv4_verify_qos_rule(&nim->msg.rule_create);
+	if (error < 0) {
+		nss_nl_error("%d:invalid qos rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * check ingress shaping rule
+	 */
+	error = nss_nlipv4_verify_igs_rule(&nim->msg.rule_create);
+	if (error < 0) {
+		nss_nl_error("%d:invalid ingress shaping rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * check dscp rule
+	 */
+	error = nss_nlipv4_verify_dscp_rule(&nim->msg.rule_create);
+	if (error < 0) {
+		nss_nl_error("%d:invalid dscp rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * check vlan rule
+	 */
+	error = nss_nlipv4_verify_vlan_rule(&nim->msg.rule_create, flow_dev, return_dev);
+	if (error < 0) {
+		nss_nl_error("%d:invalid vlan rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * check identifier
+	 */
+	error = nss_nlipv4_verify_identifier(&nim->msg.rule_create);
+	if (error < 0) {
+		nss_nl_error("%d:invalid identifier rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("%d:unable to save response data from NL buffer\n", pid);
+		error = -ENOMEM;
+		goto done;
+	}
+
+	/*
+	 * Initialize the common message
+	 */
+	nss_ipv4_msg_init(nim,					/* ipv4 message */
+			NSS_IPV4_RX_INTERFACE,			/* interface number */
+			NSS_IPV4_TX_CREATE_RULE_MSG,		/* rule */
+			sizeof(struct nss_ipv4_rule_create_msg),/* message size */
+			nss_nlipv4_process_resp,		/* response callback */
+			(void *)resp);				/* app context */
+
+	/*
+	 * Push Rule to NSS
+	 */
+	tx_status = nss_ipv4_tx_sync(gbl_ctx.nss, nim);
+
+	/* TODO: Handle the case where firmware has received the response
+	 * and there is a failure in firmware.
+	 */
+	if (tx_status != NSS_TX_SUCCESS) {
+		nss_nl_error("%d:unable to send IPv4 rule create, status(%d)\n", pid, tx_status);
+		error = -EBUSY;
+	}
+
+done:
+	dev_put(flow_dev);
+	dev_put(return_dev);
+
+	return error;
+}
+
+/*
+ * nss_nlipv4_ops_destroy_rule()
+ * 	rule delete handler
+ */
+static int nss_nlipv4_ops_destroy_rule(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nlipv4_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	struct nss_ipv4_msg *nim;
+	nss_tx_status_t tx_status;
+	struct sk_buff *resp;
+	uint32_t pid;
+	int error;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlipv4_family, info, NSS_IPV4_TX_DESTROY_RULE_MSG);
+	if (!nl_cm) {
+		nss_nl_error("unable to extract rule destroy data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlipv4_rule, cm);
+	nim = &nl_rule->nim;
+	pid = nl_cm->pid;
+
+	/*
+	 * check 5-tuple
+	 */
+	error = nss_nlipv4_verify_5tuple(&nim->msg.rule_destroy.tuple);
+	if (error < 0) {
+		nss_nl_error("%d:invalid 5-tuple information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("%d:unable to save response data from NL buffer\n", pid);
+		error = -ENOMEM;
+		goto done;
+	}
+	/*
+	 * Initialize the common message
+	 */
+	nss_ipv4_msg_init(nim,						/* ipv4 message */
+			NSS_IPV4_RX_INTERFACE,				/* interface number */
+			NSS_IPV4_TX_DESTROY_RULE_MSG,			/* rule */
+			sizeof(struct nss_ipv4_rule_destroy_msg),	/* message size */
+			nss_nlipv4_process_resp,			/* response callback */
+			(void *)resp);					/* app context */
+
+	/*
+	 * Push rule to NSS
+	 */
+	tx_status = nss_ipv4_tx_sync(gbl_ctx.nss, nim);
+
+	/* TODO: Handle the case where firmware has received the response
+	 * and there is a failure in firmware.
+	 */
+	if (tx_status != NSS_TX_SUCCESS) {
+		nss_nl_error("%d:unable to send IPv4 rule delete, status(%d)\n", pid, tx_status);
+		return -EBUSY;
+	}
+
+done:
+	return error;
+}
+
+/*
+ * nss_nlipv4_init()
+ * 	handler init
+ */
+bool nss_nlipv4_init(void)
+{
+	int error,ret;
+
+	nss_nl_info_always("Init NSS netlink IPv4 handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nlipv4_family);
+	if (error != 0) {
+		nss_nl_info_always("Error: unable to register IPv4 family\n");
+		return false;
+	}
+
+	/*
+	 * To get NSS context
+	 */
+	gbl_ctx.nss = nss_ipv4_get_mgr();
+	if (!gbl_ctx.nss) {
+		nss_nl_info_always("Error: retreiving the NSS Context \n");
+		goto unreg_family;
+	}
+
+	/*
+	 * register device call back handler for ipv4 from NSS
+	 */
+	ret = nss_ipv4_stats_register_notifier(&nss_ipv4_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context \n");
+		goto unreg_family;
+	}
+
+	return true;
+
+	/*
+	 * undo all registeration
+	 */
+unreg_family:
+	genl_unregister_family(&nss_nlipv4_family);
+
+	return false;
+}
+
+/*
+ * nss_nlipv4_exit()
+ *	handler exit
+ */
+bool nss_nlipv4_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink IPv4 handler\n");
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nlipv4_family);
+	if (error != 0) {
+		nss_nl_info_always("unable to unregister IPv4 NETLINK family\n");
+		return false;
+	}
+
+	/*
+	 * Unregister the device callback handler for ipv4
+	 */
+	nss_ipv4_stats_unregister_notifier(&nss_ipv4_stats_notifier_nb);
+
+	gbl_ctx.nss = NULL;
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nlipv4.h b/qca-nss-clients/netlink/nss_nlipv4.h
new file mode 100644
index 0000000..8195b3d
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlipv4.h
@@ -0,0 +1,35 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014 - 2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlipv4.h
+ *	NSS Netlink IPv4 API definitions
+ */
+#ifndef __NSS_NLIPV4_H
+#define __NSS_NLIPV4_H
+
+bool nss_nlipv4_init(void);
+bool nss_nlipv4_exit(void);
+
+#if defined(CONFIG_NSS_NLIPV4)
+#define NSS_NLIPV4_INIT nss_nlipv4_init
+#define NSS_NLIPV4_EXIT nss_nlipv4_exit
+#else
+#define NSS_NLIPV4_INIT 0
+#define NSS_NLIPV4_EXIT 0
+#endif /* !CONFIG_NSS_NLIPV4 */
+
+#endif /* __NSS_NLIPV4_H */
diff --git a/qca-nss-clients/netlink/nss_nlipv4_reasm.c b/qca-nss-clients/netlink/nss_nlipv4_reasm.c
new file mode 100644
index 0000000..5fe4bc4
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlipv4_reasm.c
@@ -0,0 +1,178 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlipv4_reasm.c
+ *	NSS Netlink ipv4_reasm Handler
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/notifier.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nlipv4_reasm_if.h"
+#include "nss_ipv4_reasm.h"
+
+/*
+ * prototypes
+ */
+static int nss_nlipv4_reasm_ops_get_stats(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlipv4_reasm_process_notify(struct notifier_block *nb,  unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nlipv4_reasm_mcgrp[] = {
+	{.name = NSS_NLIPV4_REASM_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nlipv4_reasm_ops[] = {
+	{.cmd = NSS_STATS_EVENT_NOTIFY, .doit = nss_nlipv4_reasm_ops_get_stats},
+};
+
+/*
+ * ipv4_reasm family definition
+ */
+static struct genl_family nss_nlipv4_reasm_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,						/* Auto generate ID */
+#endif
+	.name = NSS_NLIPV4_REASM_FAMILY,				/* family name string */
+	.hdrsize = sizeof(struct nss_ipv4_reasm_stats_notification),	/* NSS NETLINK ipv4_reasm stats */
+	.version = NSS_NL_VER,						/* Set it to NSS_NLIPV4_REASM version */
+	.maxattr = NSS_STATS_EVENT_MAX,					/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nlipv4_reasm_ops,
+	.n_ops = ARRAY_SIZE(nss_nlipv4_reasm_ops),
+	.mcgrps = nss_nlipv4_reasm_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nlipv4_reasm_mcgrp)
+};
+
+/*
+ * stats call back handler for ipv4_reasm from NSS
+ */
+static struct notifier_block nss_ipv4_reasm_stats_notifier_nb = {
+	.notifier_call = nss_nlipv4_reasm_process_notify,
+};
+
+/*
+ * nss_nlipv4_reasm_ops_get_stats()
+ *	get stats handler
+ */
+static int nss_nlipv4_reasm_ops_get_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+/*
+ * nss_nlipv4_reasm_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nlipv4_reasm_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct sk_buff *skb;
+	struct nss_ipv4_reasm_stats_notification *nss_stats, *nl_stats;
+
+	skb = nss_nl_new_msg(&nss_nlipv4_reasm_family, NSS_NLCMN_SUBSYS_IPV4_REASM);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLIPV4_REASM event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_stats = nss_nl_get_data(skb);
+	nss_stats = (struct nss_ipv4_reasm_stats_notification *)data;
+	memcpy(nl_stats, nss_stats, sizeof(struct nss_ipv4_reasm_stats_notification));
+	nss_nl_mcast_event(&nss_nlipv4_reasm_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nlipv4_reasm_init()
+ *	handler init
+ */
+bool nss_nlipv4_reasm_init(void)
+{
+	int error,ret;
+
+	nss_nl_info_always("Init NSS netlink ipv4_reasm handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nlipv4_reasm_family);
+	if (error) {
+		nss_nl_info_always("Error: unable to register ipv4_reasm family\n");
+		return false;
+	}
+
+	/*
+	 * register device call back handler for ipv4_reasm from NSS
+	 */
+	ret = nss_ipv4_reasm_stats_register_notifier(&nss_ipv4_reasm_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context \n");
+		genl_unregister_family(&nss_nlipv4_reasm_family);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nlipv4_reasm_exit()
+ *	handler exit
+ */
+bool nss_nlipv4_reasm_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink ipv4_reasm handler\n");
+
+	/*
+	 * Unregister the device callback handler for ipv4_reasm
+	 */
+	nss_ipv4_reasm_stats_unregister_notifier(&nss_ipv4_reasm_stats_notifier_nb);
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nlipv4_reasm_family);
+	if (error) {
+		nss_nl_info_always("unable to unregister ipv4_reasm NETLINK family\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nlipv4_reasm.h b/qca-nss-clients/netlink/nss_nlipv4_reasm.h
new file mode 100644
index 0000000..e13b35a
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlipv4_reasm.h
@@ -0,0 +1,37 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlipv4_reasm.h
+ *	NSS Netlink ipv4_reasm API definitions
+ */
+#ifndef __NSS_NLIPV4_REASM_H
+#define __NSS_NLIPV4_REASM_H
+
+bool nss_nlipv4_reasm_init(void);
+bool nss_nlipv4_reasm_exit(void);
+
+#if defined(CONFIG_NSS_NLIPV4_REASM)
+#define NSS_NLIPV4_REASM_INIT nss_nlipv4_reasm_init
+#define NSS_NLIPV4_REASM_EXIT nss_nlipv4_reasm_exit
+#else
+#define NSS_NLIPV4_REASM_INIT 0
+#define NSS_NLIPV4_REASM_EXIT 0
+#endif /* !CONFIG_NSS_NLIPV4_REASM */
+
+#endif /* __NSS_NLIPV4_REASM_H */
diff --git a/qca-nss-clients/netlink/nss_nlipv6.c b/qca-nss-clients/netlink/nss_nlipv6.c
new file mode 100644
index 0000000..b4c7d5b
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlipv6.c
@@ -0,0 +1,1029 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlipv6.c
+ *	NSS Netlink IPv6 Handler
+ */
+
+#include <linux/completion.h>
+#include <linux/etherdevice.h>
+#include <linux/if.h>
+#include <linux/if_addr.h>
+#include <linux/if_vlan.h>
+#include <linux/in.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/netlink.h>
+#include <linux/rcupdate.h>
+#include <linux/semaphore.h>
+#include <linux/types.h>
+#include <linux/version.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <net/addrconf.h>
+#include <net/arp.h>
+#include <net/genetlink.h>
+#include <net/ip6_route.h>
+#include <net/neighbour.h>
+#include <net/net_namespace.h>
+#include <net/route.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_ipsec.h>
+#include <nss_ipsec_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_ipsecmgr.h"
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nlgre_redir_cmd.h"
+#include "nss_nlipsec.h"
+#include "nss_nlipsec_if.h"
+#include "nss_nlipv6.h"
+#include "nss_nlipv6_if.h"
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+#define DST_NEIGH_LOOKUP(dst, ip_addr) dst_neigh_lookup(dst, ip_addr)
+#else
+#define DST_NEIGH_LOOKUP(dst, ip_addr) dst_get_neighbour_noref(dst)
+#endif
+
+/*
+ * NSS NETLINK IPv6 context
+ */
+struct nss_nlipv6_ctx {
+	void *nss;
+};
+
+/*
+ * prototypes
+ */
+
+static int nss_nlipv6_ops_create_rule(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlipv6_ops_destroy_rule(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlipv6_process_notify(struct notifier_block *nb, unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static struct genl_multicast_group nss_nlipv6_mcgrp[] = {
+	{.name = NSS_NLIPV6_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nlipv6_ops[] = {
+	{.cmd = NSS_IPV6_TX_CREATE_RULE_MSG, .doit = nss_nlipv6_ops_create_rule,},	/* rule create */
+	{.cmd = NSS_IPV6_TX_DESTROY_RULE_MSG, .doit = nss_nlipv6_ops_destroy_rule,},	/* rule destroy */
+};
+
+/*
+ * IPV6 family definition
+ */
+static struct genl_family nss_nlipv6_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,				/* Auto generate ID */
+#endif
+	.name = NSS_NLIPV6_FAMILY,			/* family name string */
+	.hdrsize = sizeof(struct nss_nlipv6_rule),	/* NSS NETLINK IPV6 rule */
+	.version = NSS_NL_VER,				/* Set it to NSS_NLIPV6 version */
+	.maxattr = NSS_IPV6_MAX_MSG_TYPES,		/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nlipv6_ops,
+	.n_ops = ARRAY_SIZE(nss_nlipv6_ops),
+	.mcgrps = nss_nlipv6_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nlipv6_mcgrp)
+};
+
+/*
+ * statistics call back handler for ipv6 from NSS
+ */
+static struct notifier_block nss_ipv6_stats_notifier_nb = {
+	.notifier_call = nss_nlipv6_process_notify,
+};
+
+#define NSS_NLIPV6_OPS_SZ ARRAY_SIZE(nss_nlipv6_ops)
+
+static struct nss_nlipv6_ctx gbl_ctx;
+
+/*
+ * nss_nlipv6_get_neigh()
+ * 	Returns neighbour reference for a given IP address
+ */
+static struct neighbour *nss_nlipv6_get_neigh(uint32_t dst_addr[4])
+{
+	struct neighbour *neigh;
+	struct dst_entry *dst;
+	struct rt6_info *rt;
+	struct in6_addr daddr;
+
+	IPV6_ADDR_TO_IN6_ADDR(daddr, dst_addr);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0))
+	rt = rt6_lookup(&init_net, &daddr, NULL, 0, 0);
+#else
+	rt = rt6_lookup(&init_net, &daddr, NULL, 0, NULL, 0);
+#endif
+	if (!rt) {
+		return NULL;
+	}
+
+	dst = (struct dst_entry *)rt;
+
+	/*
+	 * neighbour lookup using IP address in the route table
+	 */
+	neigh = DST_NEIGH_LOOKUP(dst, &daddr);
+	if (likely(neigh)) {
+		neigh_hold(neigh);
+		dst_release(dst);
+
+		return neigh;
+	}
+	dst_release(dst);
+
+	return NULL;
+}
+
+/*
+ * nss_nlipv6_get_addr_hton()
+ * 	Convert the ipv6 address from host order to network order.
+ */
+static inline void nss_nlipv6_get_addr_hton(uint32_t src[4], uint32_t dst[4])
+{
+	nss_nlipv6_swap_addr(src, dst);
+
+	dst[0] = htonl(dst[0]);
+	dst[1] = htonl(dst[1]);
+	dst[2] = htonl(dst[2]);
+	dst[3] = htonl(dst[3]);
+}
+
+/*
+ * nss_nlipv6_mac_addr_get()
+ * 	Return the hardware (MAC) address of the given ipv6 address, if any.
+ *
+ * Returns 0 on success or a negative result on failure.
+ * We look up the rtable entry for the address and,
+ * from its neighbour structure,obtain the hardware address.
+ * This means we will also work if the neighbours are routers too.
+ */
+static int nss_nlipv6_get_macaddr(uint32_t ip_addr[4], uint8_t mac_addr[])
+{
+	struct neighbour *neigh;
+	struct  in6_addr addr;
+
+	nss_nlipv6_get_addr_hton(ip_addr, addr.s6_addr32);
+
+	if (ipv6_addr_is_multicast(&addr)) {
+		/*
+		 * fixed
+		 */
+		mac_addr[0] = 0x33;
+		mac_addr[1] = 0x33;
+
+		/*
+		 * Last word of the IPv6 address.
+		 */
+		memcpy(&mac_addr[2], &addr.s6_addr32[3], sizeof(uint32_t));
+		return 0;
+
+	}
+
+	rcu_read_lock();
+
+	/*
+	 * retrieve the neighbour
+	 */
+	neigh = nss_nlipv6_get_neigh(addr.s6_addr32);
+	if (!neigh) {
+		rcu_read_unlock();
+		nss_nl_info("neighbour lookup failed for %pI6c\n", addr.s6_addr32);
+		return -ENODEV;
+	}
+
+	rcu_read_unlock();
+
+	if ((neigh->nud_state & NUD_VALID) == 0) {
+		nss_nl_info("neighbour state is invalid for %pI6c\n", addr.s6_addr32);
+		goto fail;
+	}
+
+	if (!neigh->dev) {
+		nss_nl_info("neighbour device not found for %pI6c\n", addr.s6_addr32);
+		goto fail;
+	}
+
+	if (is_multicast_ether_addr(neigh->ha)) {
+		nss_nl_info("neighbour MAC address is multicast or broadcast\n");
+		goto fail;
+	}
+
+	ether_addr_copy(mac_addr, neigh->ha);
+	neigh_release(neigh);
+	return 0;
+fail:
+
+	neigh_release(neigh);
+	return -ENODEV;
+}
+
+/*
+ * nss_nlipv6_verify_5tuple()
+ * 	verify and override 5-tuple entries
+ */
+static int nss_nlipv6_verify_5tuple(struct nss_ipv6_5tuple *tuple)
+{
+	/*
+	 * protocol must be provided
+	 */
+	if (!tuple->protocol) {
+		nss_nl_info("Empty protocol for 5-tuple\n");
+		return -EINVAL;
+	}
+
+	if (bitmap_empty((unsigned long *)tuple->flow_ip, NSS_NLIPV6_ADDR_BITS)) {
+		nss_nl_info("Empty flow IP\n");
+		return -EINVAL;
+	}
+
+	if (bitmap_empty((unsigned long *)tuple->return_ip, NSS_NLIPV6_ADDR_BITS)) {
+		nss_nl_info("Empty return IP\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Validate the port number
+	 */
+	switch (tuple->protocol) {
+	case IPPROTO_UDP:
+	case IPPROTO_TCP:
+	case IPPROTO_SCTP:
+		if (!tuple->flow_ident || !tuple->return_ident) {
+			nss_nl_error("Empty flow ident or return ident. flow ident:%d return ident:%d protocol:%d\n",
+					tuple->flow_ident, tuple->return_ident, tuple->protocol);
+			return -EINVAL;
+		}
+		break;
+	default:
+		if (tuple->flow_ident || tuple->return_ident) {
+			nss_nl_error("Flow ident and return ident must be empty. flow ident:%u return ident:%u protocol:%u\n",
+					tuple->flow_ident, tuple->return_ident, tuple->protocol);
+
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nlipv6_verify_conn_rule()
+ * 	verify and override connection rule entries
+ */
+static int nss_nlipv6_verify_conn_rule(struct nss_ipv6_rule_create_msg *msg, struct net_device *flow_dev,
+					struct net_device *return_dev, enum nss_nl_iftype flow_iftype,
+					enum nss_nl_iftype return_iftype)
+{
+	struct nss_ipv6_connection_rule *conn = &msg->conn_rule;
+	struct nss_ipv6_nexthop *nexthop = &msg->nexthop_rule;
+	struct nss_ipv6_5tuple *tuple = &msg->tuple;
+	const size_t rule_sz = sizeof(struct nss_ipv6_connection_rule);
+	bool valid;
+
+	/*
+	 * Connection rule is not valid ignore rest of the checks
+	 */
+	valid = msg->valid_flags & NSS_IPV6_RULE_CREATE_CONN_VALID;
+	if (!valid) {
+		memset(conn, 0, rule_sz);
+		return -EINVAL;
+	}
+
+	if ((flow_iftype >= NSS_NL_IFTYPE_MAX) || (return_iftype >= NSS_NL_IFTYPE_MAX)) {
+		nss_nl_error("%px: Invalid interface type (flow:%d, return:%d)\n", msg, flow_iftype, return_iftype);
+		return -EINVAL;
+	}
+
+	/*
+	 * Update the flow  & return MAC address
+	 */
+	if (nss_nlipv6_get_macaddr(tuple->flow_ip, (uint8_t *)conn->flow_mac)) {
+		nss_nl_info("Error in Updating the Flow MAC Address \n");
+		return -EINVAL;
+	}
+
+	if (nss_nlipv6_get_macaddr(tuple->return_ip, (uint8_t *)conn->return_mac)) {
+		nss_nl_info("Error in Updating the Return MAC Address \n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Update flow interface number and flow mtu
+	 */
+	switch (flow_iftype) {
+	case NSS_NL_IFTYPE_TUNNEL_IPSEC:
+		conn->flow_interface_num = nss_nlipsec_get_ifnum(flow_dev, tuple->protocol,
+								tuple->return_ident, tuple->flow_ident);
+		if (conn->flow_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get flow interface number (dev:%s, type:%d)\n",
+					flow_dev, flow_dev->name, flow_iftype);
+			return -EINVAL;
+		}
+
+		conn->flow_mtu = nss_nlipsec_get_mtu(flow_dev, 6, tuple->protocol,
+							tuple->return_ident, tuple->flow_ident);
+		break;
+
+	case NSS_NL_IFTYPE_TUNNEL_GRE:
+		conn->flow_interface_num = nss_nlgre_redir_cmd_get_ifnum(flow_dev, tuple->protocol);
+		if (conn->flow_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get flow interface number (dev:%s, type:%d)\n",
+			flow_dev, flow_dev->name, flow_iftype);
+			return -EINVAL;
+		}
+
+		conn->flow_mtu = nss_nlgre_redir_cmd_get_mtu(flow_dev, NSS_GRE_REDIR_IP_HDR_TYPE_IPV6, conn->flow_interface_num);
+		break;
+
+	case NSS_NL_IFTYPE_VLAN:
+		conn->flow_interface_num = nss_cmn_get_interface_number_by_dev(vlan_dev_real_dev(flow_dev));
+		if (conn->flow_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get flow interface number (dev:%s, type:%d)\n",
+					flow_dev, flow_dev->name, flow_iftype);
+			return -EINVAL;
+		}
+
+		conn->flow_mtu = flow_dev->mtu;
+		break;
+
+	case NSS_NL_IFTYPE_PHYSICAL:
+		conn->flow_interface_num = nss_cmn_get_interface_number_by_dev(flow_dev);
+		if (conn->flow_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get flow interface number (dev:%s, type:%d)\n",
+					flow_dev, flow_dev->name, flow_iftype);
+			return -EINVAL;
+		}
+
+		conn->flow_mtu = flow_dev->mtu;
+		break;
+
+	default:
+		nss_nl_error("%px: Unsupported flow interface type (%d)\n", msg, flow_iftype);
+		return -EINVAL;
+	}
+
+	nss_nl_info("%px: dev=%s flow_ifnum:0x%x flow_mtu=%d\n", msg, flow_dev->name,
+			conn->flow_interface_num, conn->flow_mtu);
+
+	/*
+	 * Update return interface number and return mtu
+	 */
+	switch (return_iftype) {
+	case NSS_NL_IFTYPE_TUNNEL_IPSEC:
+		conn->return_interface_num = nss_nlipsec_get_ifnum(return_dev, tuple->protocol,
+									tuple->return_ident, tuple->flow_ident);
+		if (conn->return_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get return interface number (dev:%s, type:%d)\n",
+					return_dev, return_dev->name, return_iftype);
+			return -EINVAL;
+		}
+
+		conn->return_mtu = nss_nlipsec_get_mtu(return_dev, 6, tuple->protocol,
+							tuple->return_ident, tuple->flow_ident);
+		break;
+
+	case NSS_NL_IFTYPE_TUNNEL_GRE:
+		conn->return_interface_num = nss_nlgre_redir_cmd_get_ifnum(return_dev, tuple->protocol);
+		if (conn->return_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get return interface number (dev:%s, type:%d)\n",
+			return_dev, return_dev->name, return_iftype);
+			return -EINVAL;
+		}
+
+		conn->return_mtu = nss_nlgre_redir_cmd_get_mtu(return_dev, NSS_GRE_REDIR_IP_HDR_TYPE_IPV6, conn->return_interface_num);
+		break;
+
+	case NSS_NL_IFTYPE_VLAN:
+		conn->return_interface_num = nss_cmn_get_interface_number_by_dev(vlan_dev_real_dev(return_dev));
+		if (conn->return_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get return interface number (dev:%s, type:%d)\n",
+					return_dev, return_dev->name, return_iftype);
+			return -EINVAL;
+		}
+
+		conn->return_mtu = return_dev->mtu;
+		break;
+
+	case NSS_NL_IFTYPE_PHYSICAL:
+		conn->return_interface_num = nss_cmn_get_interface_number_by_dev(return_dev);
+		if (conn->return_interface_num < 0 ) {
+			nss_nl_error("%px: Failed to get return interface number (dev:%s, type:%d)\n",
+					return_dev, return_dev->name, return_iftype);
+			return -EINVAL;
+		}
+
+		conn->return_mtu = return_dev->mtu;
+		break;
+
+	default:
+		nss_nl_error("%px: Unsupported return interface type (%d)\n", msg, flow_iftype);
+		return -EINVAL;
+	}
+
+	nss_nl_info("%px: dev=%s return_ifnum:0x%x return_mtu=%d\n", msg, return_dev->name,
+			conn->return_interface_num, conn->return_mtu);
+
+	nexthop->flow_nexthop = conn->flow_interface_num;
+	nexthop->return_nexthop = conn->return_interface_num;
+
+	nss_nl_info("flow_nexthop:%d return_nexthop:%d\n", nexthop->flow_nexthop, nexthop->return_nexthop);
+
+	return 0;
+}
+
+/*
+ * nss_nlipv6_verify_tcp_rule()
+ * 	verify and override TCP protocol rule entries
+ */
+static int nss_nlipv6_verify_tcp_rule(struct nss_ipv6_rule_create_msg *msg)
+{
+	struct nss_ipv6_protocol_tcp_rule *tcp = &msg->tcp_rule;
+	const size_t rule_sz = sizeof(struct nss_ipv6_protocol_tcp_rule);
+	bool valid;
+
+	/*
+	 * tcp rule is not valid ignore rest of the checks
+	 */
+	valid = msg->valid_flags & NSS_IPV6_RULE_CREATE_TCP_VALID;
+	if (!valid) {
+		memset(tcp, 0, rule_sz);
+		return 0;
+	}
+
+	/*
+	 * XXX: add addtional checks as required
+	 */
+
+	return 0;
+}
+
+/*
+ * nss_nlipv6_verify_pppoe_rule()
+ * 	verify and override pppoe rule entries
+ */
+static int nss_nlipv6_verify_pppoe_rule(struct nss_ipv6_rule_create_msg *msg)
+{
+	struct nss_ipv6_pppoe_rule *pppoe = &msg->pppoe_rule;
+	const size_t rule_sz = sizeof(struct nss_ipv6_pppoe_rule);
+	bool valid;
+
+	/*
+	 * pppoe rule is not valid ignore rest of the checks
+	 */
+	valid = msg->valid_flags & NSS_IPV6_RULE_CREATE_PPPOE_VALID;
+	if (!valid) {
+		memset(pppoe, 0, rule_sz);
+		return 0;
+	}
+
+	/*
+	 * XXX: add addtional checks as required
+	 */
+	return 0;
+}
+
+/*
+ * nss_nlipv6_verify_igs_rule()
+ * 	verify and override ingress shaping rule entries
+ */
+static int nss_nlipv6_verify_igs_rule(struct nss_ipv6_rule_create_msg *msg)
+{
+	struct nss_ipv6_igs_rule *igs = &msg->igs_rule;
+	const size_t rule_sz = sizeof(struct nss_ipv6_igs_rule);
+	bool valid;
+
+	/*
+	 * ingress shaping rule is not valid ignore rest of the checks
+	 */
+	valid = msg->valid_flags & NSS_IPV6_RULE_CREATE_IGS_VALID;
+	if (!valid) {
+		memset(igs, 0, rule_sz);
+		return 0;
+	}
+	return 0;
+}
+
+/*
+ * nss_nlipv6_verify_qos_rule()
+ * 	verify and override qos rule entries
+ */
+static int nss_nlipv6_verify_qos_rule(struct nss_ipv6_rule_create_msg *msg)
+{
+	struct nss_ipv6_qos_rule *qos = &msg->qos_rule;
+	const size_t rule_sz = sizeof(struct nss_ipv6_qos_rule);
+	bool valid;
+
+	/*
+	 * qos rule is not valid ignore rest of the checks
+	 */
+	valid = msg->valid_flags & NSS_IPV6_RULE_CREATE_QOS_VALID;
+	if (!valid) {
+		memset(qos, 0, rule_sz);
+		return 0;
+	}
+
+	/*
+	 * XXX: add addtional checks as required
+	 */
+	return 0;
+}
+
+/*
+ * nss_nlipv6_verify_dscp_rule()
+ * 	verify and override dscp rule entries
+ */
+static int nss_nlipv6_verify_dscp_rule(struct nss_ipv6_rule_create_msg *msg)
+{
+	struct nss_ipv6_dscp_rule *dscp = &msg->dscp_rule;
+	const size_t rule_sz = sizeof(struct nss_ipv6_dscp_rule);
+	bool valid;
+
+	/*
+	 * dscp rule is not valid ignore rest of the checks
+	 */
+	valid = msg->valid_flags & NSS_IPV6_RULE_CREATE_DSCP_MARKING_VALID;
+	if (!valid) {
+		memset(dscp, 0, rule_sz);
+		return 0;
+	}
+
+	/*
+	 * XXX: add addtional checks as required
+	 */
+	return 0;
+}
+
+/*
+ * nss_nlipv6_verify_vlan_rule()
+ * 	verify and override vlan rule entries
+ */
+static int nss_nlipv6_verify_vlan_rule(struct nss_ipv6_rule_create_msg *msg, struct net_device *flow_dev,
+					struct net_device *return_dev)
+{
+	struct nss_ipv6_vlan_rule *vlan_primary = &msg->vlan_primary_rule;
+	struct nss_ipv6_vlan_rule *vlan_secondary = &msg->vlan_secondary_rule;
+	bool flow_vlan = is_vlan_dev(flow_dev);
+	bool return_vlan = is_vlan_dev(return_dev);
+
+	/*
+	 * Fill all with default values.
+	 */
+	vlan_primary->ingress_vlan_tag = NSS_NLIPV6_VLAN_ID_NOT_CONFIGURED;
+	vlan_primary->egress_vlan_tag = NSS_NLIPV6_VLAN_ID_NOT_CONFIGURED;
+
+	vlan_secondary->ingress_vlan_tag = NSS_NLIPV6_VLAN_ID_NOT_CONFIGURED;
+	vlan_secondary->egress_vlan_tag = NSS_NLIPV6_VLAN_ID_NOT_CONFIGURED;
+
+	if (!flow_vlan && !return_vlan)
+		return 0;
+
+	msg->valid_flags |= NSS_IPV6_RULE_CREATE_VLAN_VALID;
+
+	/*
+	 * Add single vlan
+	 */
+	if (flow_vlan)
+		vlan_primary->ingress_vlan_tag = ETH_P_8021Q << 16 | vlan_dev_vlan_id(flow_dev);
+
+	if (return_vlan)
+		vlan_primary->egress_vlan_tag = ETH_P_8021Q << 16 | vlan_dev_vlan_id(return_dev);
+
+	/*
+	 * XXX: add addtional checks as required
+	 */
+	return 0;
+}
+
+/*
+ * nss_nlipv6_verify_identifier()
+ *	verify and override identifier rule entries
+ */
+static int nss_nlipv6_verify_identifier(struct nss_ipv6_rule_create_msg *msg)
+{
+	struct nss_ipv6_identifier_rule *identifier = &msg->identifier;
+	const size_t rule_sz = sizeof(struct nss_ipv6_identifier_rule);
+	uint16_t valid;
+
+	/*
+	 * if identifier is not valid, set identifier rule to 0
+	 */
+	valid = msg->valid_flags & NSS_IPV6_RULE_CREATE_IDENTIFIER_VALID;
+	if (!valid) {
+		memset(identifier, 0, rule_sz);
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nlipv6_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nlipv6_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct nss_nlipv6_rule *nl_rule;
+	struct sk_buff *skb;
+	struct nss_ipv6_stats_notification *nss_stats;
+
+	skb = nss_nl_new_msg(&nss_nlipv6_family, NSS_NLCMN_SUBSYS_IPV6);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLIPV6 event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_rule = nss_nl_get_data(skb);
+	nss_stats = (struct nss_ipv6_stats_notification *)data;
+	memcpy(&nl_rule->stats, nss_stats, sizeof(struct nss_ipv6_stats_notification));
+	nss_nl_mcast_event(&nss_nlipv6_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nlipv6_resp_create_rule()
+ * 	handle response for create rule
+ */
+static void nss_nlipv6_process_resp(void *app_data, struct nss_ipv6_msg *nim)
+{
+	struct sk_buff *resp = (struct sk_buff *)app_data;
+	struct nss_nlipv6_rule *nl_rule;
+	struct nss_ipv6_msg *nl_nim;
+
+	nl_rule = nss_nl_get_data(resp);
+	nl_nim = &nl_rule->nim;
+
+	/*
+	 * copy the message response data into the NL message buffer. If, FW
+	 * has updated the message then we must updated the same into the NL
+	 * message as the NL message buffer is different from what was sent
+	 * to FW
+	 */
+	memcpy(nl_nim, nim, sizeof(struct nss_ipv6_msg));
+
+	nss_nl_ucast_resp(resp);
+}
+
+/*
+ * nss_nlipv6_ops_create_rule()
+ * 	rule create handler
+ */
+static int nss_nlipv6_ops_create_rule(struct sk_buff *skb, struct genl_info *info)
+{
+	struct net_device *return_dev;
+	struct net_device *flow_dev;
+	struct nss_nlipv6_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	struct nss_ipv6_msg *nim;
+	nss_tx_status_t tx_status;
+	struct sk_buff *resp;
+	uint32_t pid;
+	int error;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlipv6_family, info, NSS_IPV6_TX_CREATE_RULE_MSG);
+	if (!nl_cm) {
+		nss_nl_error("unable to extract rule create data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlipv6_rule, cm);
+	nim = &nl_rule->nim;
+	pid = nl_cm->pid;
+
+	/*
+	 * extract netdevices for flow and return
+	 */
+	flow_dev = dev_get_by_name(&init_net, nl_rule->flow_ifname);
+	if (!flow_dev) {
+		nss_nl_error("%d:flow interface is not available for dev=%s\n", pid, nl_rule->flow_ifname);
+		return -EINVAL;
+	}
+
+	return_dev = dev_get_by_name(&init_net, nl_rule->return_ifname);
+	if (!return_dev) {
+		dev_put(flow_dev);
+		nss_nl_error("%d:return interface is not available for dev=%s\n", pid, nl_rule->return_ifname);
+		return -EINVAL;
+	}
+
+	/*
+	 * check 5-tuple
+	 */
+	error = nss_nlipv6_verify_5tuple(&nim->msg.rule_create.tuple);
+	if (error < 0) {
+		nss_nl_error("%d:invalid 5-tuple information passed\n", pid);
+		goto done;
+	}
+
+	nss_nl_info("Checking rule for flowdev=%s flow_type=%d returndev=%s return_type=%d\n",
+			nl_rule->flow_ifname, nl_rule->flow_iftype, nl_rule->return_ifname, nl_rule->return_iftype);
+
+	/*
+	 * check connection rule
+	 */
+	error = nss_nlipv6_verify_conn_rule(&nim->msg.rule_create, flow_dev, return_dev,
+						nl_rule->flow_iftype, nl_rule->return_iftype);
+	if (error < 0) {
+		nss_nl_error("%d:invalid conn rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * check tcp protocol rule
+	 */
+	error = nss_nlipv6_verify_tcp_rule(&nim->msg.rule_create);
+	if (error < 0) {
+		nss_nl_error("%d:invalid tcp rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * check pppoe rule
+	 */
+	error = nss_nlipv6_verify_pppoe_rule(&nim->msg.rule_create);
+	if (error < 0) {
+		nss_nl_error("%d:invalid pppoe rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * check qos rule
+	 */
+	error = nss_nlipv6_verify_qos_rule(&nim->msg.rule_create);
+	if (error < 0) {
+		nss_nl_error("%d:invalid qos rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * check ingress shaping rule
+	 */
+	error = nss_nlipv6_verify_igs_rule(&nim->msg.rule_create);
+	if (error < 0) {
+		nss_nl_error("%d:invalid ingress shaping rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * check dscp rule
+	 */
+	error = nss_nlipv6_verify_dscp_rule(&nim->msg.rule_create);
+	if (error < 0) {
+		nss_nl_error("%d:invalid dscp rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * check vlan rule
+	 */
+	error = nss_nlipv6_verify_vlan_rule(&nim->msg.rule_create, flow_dev, return_dev);
+	if (error < 0) {
+		nss_nl_error("%d:invalid vlan rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * check identifier
+	 */
+	error = nss_nlipv6_verify_identifier(&nim->msg.rule_create);
+	if (error < 0) {
+		nss_nl_error("%d:invalid identifier rule information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("%d:unable to save response data from NL buffer\n", pid);
+		error = -ENOMEM;
+		goto done;
+	}
+
+	/*
+	 * Initialize the common message
+	 */
+	nss_ipv6_msg_init(nim,					/* ipv6 message */
+			NSS_IPV6_RX_INTERFACE,			/* interface number */
+			NSS_IPV6_TX_CREATE_RULE_MSG,		/* rule */
+			sizeof(struct nss_ipv6_rule_create_msg),/* message size */
+			nss_nlipv6_process_resp,		/* response callback */
+			(void *)resp);				/* app context */
+
+	/*
+	 * Conver the IP addresses to NSS format
+	 */
+	nss_nlipv6_swap_addr(nim->msg.rule_create.tuple.flow_ip, nim->msg.rule_create.tuple.flow_ip);
+	nss_nlipv6_swap_addr(nim->msg.rule_create.tuple.return_ip, nim->msg.rule_create.tuple.return_ip);
+
+	/*
+	 * Push Rule to NSS
+	 */
+	tx_status = nss_ipv6_tx_sync(gbl_ctx.nss, nim);
+
+        /* TODO: Handle the case where firmware has received the response
+	 * and there is a failure in firmware.
+	 */
+	if (tx_status != NSS_TX_SUCCESS) {
+		nss_nl_error("%d:unable to send IPV6 rule create, status(%d)\n", pid, tx_status);
+		error = -EBUSY;
+	}
+
+done:
+	dev_put(flow_dev);
+	dev_put(return_dev);
+
+	return error;
+}
+
+/*
+ * nss_nlipv6_ops_destroy_rule()
+ * 	rule delete handler
+ */
+static int nss_nlipv6_ops_destroy_rule(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nlipv6_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	struct nss_ipv6_msg *nim;
+	nss_tx_status_t tx_status;
+	struct sk_buff *resp;
+	uint32_t pid;
+	int error;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nlipv6_family, info, NSS_IPV6_TX_DESTROY_RULE_MSG);
+	if (!nl_cm) {
+		nss_nl_error("unable to extract rule destroy data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nlipv6_rule, cm);
+	nim = &nl_rule->nim;
+	pid = nl_cm->pid;
+
+	/*
+	 * check 5-tuple
+	 */
+	error = nss_nlipv6_verify_5tuple(&nim->msg.rule_destroy.tuple);
+	if (error < 0) {
+		nss_nl_error("%d:invalid 5-tuple information passed\n", pid);
+		goto done;
+	}
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("%d:unable to save response data from NL buffer\n", pid);
+		error = -ENOMEM;
+		goto done;
+	}
+	/*
+	 * Initialize the common message
+	 */
+	nss_ipv6_msg_init(nim,						/* ipv6 message */
+			NSS_IPV6_RX_INTERFACE,				/* interface number */
+			NSS_IPV6_TX_DESTROY_RULE_MSG,			/* rule */
+			sizeof(struct nss_ipv6_rule_destroy_msg),	/* message size */
+			nss_nlipv6_process_resp,			/* response callback */
+			(void *)resp);					/* app context */
+	/*
+	 * Conver the IP addresses to NSS format
+	 */
+	nss_nlipv6_swap_addr(nim->msg.rule_destroy.tuple.flow_ip, nim->msg.rule_destroy.tuple.flow_ip);
+	nss_nlipv6_swap_addr(nim->msg.rule_destroy.tuple.return_ip, nim->msg.rule_destroy.tuple.return_ip);
+
+	/*
+	 * Push rule to NSS
+	 */
+	tx_status = nss_ipv6_tx_sync(gbl_ctx.nss, nim);
+
+        /* TODO: Handle the case where firmware has received the response
+	 * and there is a failure in firmware.
+	 */
+	if (tx_status != NSS_TX_SUCCESS) {
+		nss_nl_error("%d:unable to send IPV6 rule delete, status(%d)\n", pid, tx_status);
+		return -EBUSY;
+	}
+
+done:
+	return error;
+}
+
+/*
+ * nss_nlipv6_init()
+ * 	handler init
+ */
+bool nss_nlipv6_init(void)
+{
+	int error, ret;
+
+	nss_nl_info_always("Init NSS netlink IPV6 handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nlipv6_family);
+	if (error != 0) {
+		nss_nl_info_always("Error: unable to register IPV6 family\n");
+		return false;
+	}
+
+	/*
+	 * To get NSS context
+	 */
+	gbl_ctx.nss = nss_ipv6_get_mgr();
+	if (!gbl_ctx.nss) {
+		nss_nl_info_always("Error: retreiving the NSS Context \n");
+		goto unreg_family;
+	}
+
+	/*
+	 * register device call back handler for ipv6 from NSS
+	 */
+	ret = nss_ipv6_stats_register_notifier(&nss_ipv6_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context \n");
+		goto unreg_family;
+	}
+
+	return true;
+
+	/*
+	 * undo all registeration
+	 */
+unreg_family:
+	genl_unregister_family(&nss_nlipv6_family);
+
+	return false;
+}
+
+/*
+ * nss_nlipv6_exit()
+ *	handler exit
+ */
+bool nss_nlipv6_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink IPV6 handler\n");
+
+	/*
+	 * Unregister the device callback handler for ipv6
+	 */
+	nss_ipv6_stats_unregister_notifier(&nss_ipv6_stats_notifier_nb);
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nlipv6_family);
+	if (error != 0) {
+		nss_nl_info_always("unable to unregister IPV6 NETLINK family\n");
+		return false;
+	}
+
+	gbl_ctx.nss = NULL;
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nlipv6.h b/qca-nss-clients/netlink/nss_nlipv6.h
new file mode 100644
index 0000000..98185f9
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlipv6.h
@@ -0,0 +1,37 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlipv6.h
+ *	NSS Netlink IPv6 API definitions
+ */
+#ifndef __NSS_NLIPV6_H
+#define __NSS_NLIPV6_H
+
+#define NSS_NLIPV6_VLAN_ID_NOT_CONFIGURED 0xFFF    /* Invalid vlan 4095 */
+
+bool nss_nlipv6_init(void);
+bool nss_nlipv6_exit(void);
+
+#if defined(CONFIG_NSS_NLIPV6)
+#define NSS_NLIPV6_INIT nss_nlipv6_init
+#define NSS_NLIPV6_EXIT nss_nlipv6_exit
+#else
+#define NSS_NLIPV6_INIT 0
+#define NSS_NLIPV6_EXIT 0
+#endif /* !CONFIG_NSS_NLIPV6 */
+
+#endif /* __NSS_NLIPV6_H */
diff --git a/qca-nss-clients/netlink/nss_nlipv6_reasm.c b/qca-nss-clients/netlink/nss_nlipv6_reasm.c
new file mode 100644
index 0000000..4182e53
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlipv6_reasm.c
@@ -0,0 +1,178 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlipv6_reasm.c
+ *	NSS Netlink ipv6_reasm Handler
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/notifier.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nlipv6_reasm_if.h"
+#include "nss_ipv6_reasm.h"
+
+/*
+ * prototypes
+ */
+static int nss_nlipv6_reasm_ops_get_stats(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlipv6_reasm_process_notify(struct notifier_block *nb,  unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nlipv6_reasm_mcgrp[] = {
+	{.name = NSS_NLIPV6_REASM_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nlipv6_reasm_ops[] = {
+	{.cmd = NSS_STATS_EVENT_NOTIFY, .doit = nss_nlipv6_reasm_ops_get_stats},
+};
+
+/*
+ * ipv6_reasm family definition
+ */
+static struct genl_family nss_nlipv6_reasm_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,						/* Auto generate ID */
+#endif
+	.name = NSS_NLIPV6_REASM_FAMILY,				/* family name string */
+	.hdrsize = sizeof(struct nss_ipv6_reasm_stats_notification),	/* NSS NETLINK ipv6_reasm stats */
+	.version = NSS_NL_VER,						/* Set it to NSS_NLIPV6_REASM version */
+	.maxattr = NSS_STATS_EVENT_MAX,					/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nlipv6_reasm_ops,
+	.n_ops = ARRAY_SIZE(nss_nlipv6_reasm_ops),
+	.mcgrps = nss_nlipv6_reasm_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nlipv6_reasm_mcgrp)
+};
+
+/*
+ * stats call back handler for ipv6_reasm from NSS
+ */
+static struct notifier_block nss_ipv6_reasm_stats_notifier_nb = {
+	.notifier_call = nss_nlipv6_reasm_process_notify,
+};
+
+/*
+ * nss_nlipv6_reasm_ops_get_stats()
+ *	get stats handler
+ */
+static int nss_nlipv6_reasm_ops_get_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+/*
+ * nss_nlipv6_reasm_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nlipv6_reasm_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct sk_buff *skb;
+	struct nss_ipv6_reasm_stats_notification *nss_stats, *nl_stats;
+
+	skb = nss_nl_new_msg(&nss_nlipv6_reasm_family, NSS_NLCMN_SUBSYS_IPV6_REASM);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLIPV6_REASM event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_stats = nss_nl_get_data(skb);
+	nss_stats = (struct nss_ipv6_reasm_stats_notification *)data;
+	memcpy(nl_stats, nss_stats, sizeof(struct nss_ipv6_reasm_stats_notification));
+	nss_nl_mcast_event(&nss_nlipv6_reasm_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nlipv6_reasm_init()
+ *	handler init
+ */
+bool nss_nlipv6_reasm_init(void)
+{
+	int error,ret;
+
+	nss_nl_info_always("Init NSS netlink ipv6_reasm handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nlipv6_reasm_family);
+	if (error) {
+		nss_nl_info_always("Error: unable to register ipv6_reasm family\n");
+		return false;
+	}
+
+	/*
+	 * register device call back handler for ipv6_reasm from NSS
+	 */
+	ret = nss_ipv6_reasm_stats_register_notifier(&nss_ipv6_reasm_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context\n");
+		genl_unregister_family(&nss_nlipv6_reasm_family);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nlipv6_reasm_exit()
+ *	handler exit
+ */
+bool nss_nlipv6_reasm_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink ipv6_reasm handler\n");
+
+	/*
+	 * Unregister the device callback handler for ipv6_reasm
+	 */
+	nss_ipv6_reasm_stats_unregister_notifier(&nss_ipv6_reasm_stats_notifier_nb);
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nlipv6_reasm_family);
+	if (error) {
+		nss_nl_info_always("unable to unregister ipv6_reasm NETLINK family\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nlipv6_reasm.h b/qca-nss-clients/netlink/nss_nlipv6_reasm.h
new file mode 100644
index 0000000..2337078
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlipv6_reasm.h
@@ -0,0 +1,37 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlipv6_reasm.h
+ *	NSS Netlink ipv6_reasm API definitions
+ */
+#ifndef __NSS_NLIPV6_REASM_H
+#define __NSS_NLIPV6_REASM_H
+
+bool nss_nlipv6_reasm_init(void);
+bool nss_nlipv6_reasm_exit(void);
+
+#if defined(CONFIG_NSS_NLIPV6_REASM)
+#define NSS_NLIPV6_REASM_INIT nss_nlipv6_reasm_init
+#define NSS_NLIPV6_REASM_EXIT nss_nlipv6_reasm_exit
+#else
+#define NSS_NLIPV6_REASM_INIT 0
+#define NSS_NLIPV6_REASM_EXIT 0
+#endif /* !CONFIG_NSS_NLIPV6_REASM */
+
+#endif /* __NSS_NLIPV6_REASM_H */
diff --git a/qca-nss-clients/netlink/nss_nll2tpv2.c b/qca-nss-clients/netlink/nss_nll2tpv2.c
new file mode 100644
index 0000000..711bf74
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nll2tpv2.c
@@ -0,0 +1,179 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nll2tpv2.c
+ *	NSS Netlink l2tpv2 Handler
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/notifier.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nll2tpv2_if.h"
+#include "nss_l2tpv2.h"
+
+/*
+ * prototypes
+ */
+static int nss_nll2tpv2_ops_get_stats(struct sk_buff *skb, struct genl_info *info);
+static int nss_nll2tpv2_process_notify(struct notifier_block *nb, unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nll2tpv2_mcgrp[] = {
+	{.name = NSS_NLL2TPV2_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nll2tpv2_ops[] = {
+	{.cmd = NSS_STATS_EVENT_NOTIFY, .doit = nss_nll2tpv2_ops_get_stats},
+};
+
+/*
+ * l2tpv2 family definition
+ */
+static struct genl_family nss_nll2tpv2_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,						/* Auto generate ID */
+#endif
+	.name = NSS_NLL2TPV2_FAMILY,					/* family name string */
+	.hdrsize = sizeof(struct nss_l2tpv2_stats_notification),	/* NSS NETLINK l2tpv2 stats */
+	.version = NSS_NL_VER,						/* Set it to NSS_NLL2TPV2 version */
+	.maxattr = NSS_STATS_EVENT_MAX,					/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nll2tpv2_ops,
+	.n_ops = ARRAY_SIZE(nss_nll2tpv2_ops),
+	.mcgrps = nss_nll2tpv2_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nll2tpv2_mcgrp)
+};
+
+/*
+ * device call back handler for l2tpv2 from NSS
+ */
+static struct notifier_block nss_l2tpv2_stats_notifier_nb = {
+	.notifier_call = nss_nll2tpv2_process_notify,
+};
+
+/*
+ * nss_nll2tpv2_ops_get_stats()
+ *	get stats handler
+ */
+static int nss_nll2tpv2_ops_get_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+/*
+ * nss_nll2tpv2_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nll2tpv2_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct sk_buff *skb;
+	struct nss_l2tpv2_stats_notification *nss_stats, *nl_stats;
+
+	nss_stats = (struct nss_l2tpv2_stats_notification *)data;
+	skb = nss_nl_new_msg(&nss_nll2tpv2_family, NSS_NLCMN_SUBSYS_L2TPV2);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLL2TPV2 event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_stats = nss_nl_get_data(skb);
+	memcpy(nl_stats, nss_stats, sizeof(struct nss_l2tpv2_stats_notification));
+	nss_nl_mcast_event(&nss_nll2tpv2_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nll2tpv2_init()
+ *	handler init
+ */
+bool nss_nll2tpv2_init(void)
+{
+	int error,ret;
+
+	nss_nl_info_always("Init NSS netlink l2tpv2 handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nll2tpv2_family);
+	if (error) {
+		nss_nl_info_always("Error: unable to register l2tpv2 family\n");
+		return false;
+	}
+
+	/*
+	 * register device call back handler for l2tpv2 from NSS
+	 */
+	ret = nss_l2tpv2_stats_register_notifier(&nss_l2tpv2_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context\n");
+		genl_unregister_family(&nss_nll2tpv2_family);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nll2tpv2_exit()
+ *	handler exit
+ */
+bool nss_nll2tpv2_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink l2tpv2 handler\n");
+
+	/*
+	 * Unregister the device callback handler for l2tpv2
+	 */
+	nss_l2tpv2_stats_unregister_notifier(&nss_l2tpv2_stats_notifier_nb);
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nll2tpv2_family);
+	if (error) {
+		nss_nl_info_always("unable to unregister l2tpv2 NETLINK family\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nll2tpv2.h b/qca-nss-clients/netlink/nss_nll2tpv2.h
new file mode 100644
index 0000000..9862b3a
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nll2tpv2.h
@@ -0,0 +1,37 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nll2tpv2.h
+ *	NSS Netlink l2tpv2 API definitions
+ */
+#ifndef __NSS_NLL2TPV2_H
+#define __NSS_NLL2TPV2_H
+
+bool nss_nll2tpv2_init(void);
+bool nss_nll2tpv2_exit(void);
+
+#if defined(CONFIG_NSS_NLL2TPV2)
+#define NSS_NLL2TPV2_INIT nss_nll2tpv2_init
+#define NSS_NLL2TPV2_EXIT nss_nll2tpv2_exit
+#else
+#define NSS_NLL2TPV2_INIT 0
+#define NSS_NLL2TPV2_EXIT 0
+#endif /* !CONFIG_NSS_NLL2TPV2 */
+
+#endif /* __NSS_NLL2TPV2_H */
diff --git a/qca-nss-clients/netlink/nss_nllso_rx.c b/qca-nss-clients/netlink/nss_nllso_rx.c
new file mode 100644
index 0000000..ccd8c7b
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nllso_rx.c
@@ -0,0 +1,179 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nllso_rx.c
+ *	NSS Netlink lso_rx Handler
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/notifier.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nllso_rx_if.h"
+#include "nss_lso_rx.h"
+
+/*
+ * prototypes
+ */
+static int nss_nllso_rx_ops_get_stats(struct sk_buff *skb, struct genl_info *info);
+static int nss_nllso_rx_process_notify(struct notifier_block *nb, unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nllso_rx_mcgrp[] = {
+	{.name = NSS_NLLSO_RX_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nllso_rx_ops[] = {
+	{.cmd = NSS_STATS_EVENT_NOTIFY, .doit = nss_nllso_rx_ops_get_stats},
+};
+
+/*
+ * lso_rx family definition
+ */
+static struct genl_family nss_nllso_rx_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,						/* Auto generate ID */
+#endif
+	.name = NSS_NLLSO_RX_FAMILY,					/* family name string */
+	.hdrsize = sizeof(struct nss_lso_rx_stats_notification),	/* NSS NETLINK lso_rx stats */
+	.version = NSS_NL_VER,						/* Set it to NSS_NLLSO_RX version */
+	.maxattr = NSS_STATS_EVENT_MAX,					/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nllso_rx_ops,
+	.n_ops = ARRAY_SIZE(nss_nllso_rx_ops),
+	.mcgrps = nss_nllso_rx_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nllso_rx_mcgrp)
+};
+
+/*
+ * device call back handler for lso_rx from NSS
+ */
+static struct notifier_block nss_lso_rx_stats_notifier_nb = {
+	.notifier_call = nss_nllso_rx_process_notify,
+};
+
+/*
+ * nss_nllso_rx_ops_get_stats()
+ *	get stats handler
+ */
+static int nss_nllso_rx_ops_get_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+/*
+ * nss_nllso_rx_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nllso_rx_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct sk_buff *skb;
+	struct nss_lso_rx_stats_notification *nss_stats, *nl_stats;
+
+	nss_stats = (struct nss_lso_rx_stats_notification *)data;
+	skb = nss_nl_new_msg(&nss_nllso_rx_family, NSS_NLCMN_SUBSYS_LSO_RX);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLLSO_RX event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_stats = nss_nl_get_data(skb);
+	memcpy(nl_stats, nss_stats, sizeof(struct nss_lso_rx_stats_notification));
+	nss_nl_mcast_event(&nss_nllso_rx_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nllso_rx_init()
+ *	handler init
+ */
+bool nss_nllso_rx_init(void)
+{
+	int error,ret;
+
+	nss_nl_info_always("Init NSS netlink lso_rx handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nllso_rx_family);
+	if (error) {
+		nss_nl_info_always("Error: unable to register lso_rx family\n");
+		return false;
+	}
+
+	/*
+	 * register device call back handler for lso_rx from NSS
+	 */
+	ret = nss_lso_rx_stats_register_notifier(&nss_lso_rx_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context\n");
+		genl_unregister_family(&nss_nllso_rx_family);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nllso_rx_exit()
+ *	handler exit
+ */
+bool nss_nllso_rx_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink lso_rx handler\n");
+
+	/*
+	 * Unregister the device callback handler for lso_rx
+	 */
+	nss_lso_rx_stats_unregister_notifier(&nss_lso_rx_stats_notifier_nb);
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nllso_rx_family);
+	if (error) {
+		nss_nl_info_always("unable to unregister lso_rx NETLINK family\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nllso_rx.h b/qca-nss-clients/netlink/nss_nllso_rx.h
new file mode 100644
index 0000000..f190e7e
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nllso_rx.h
@@ -0,0 +1,37 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nllso_rx.h
+ *	NSS Netlink lso_rx API definitions
+ */
+#ifndef __NSS_NLLSO_RX_H
+#define __NSS_NLLSO_RX_H
+
+bool nss_nllso_rx_init(void);
+bool nss_nllso_rx_exit(void);
+
+#if defined(CONFIG_NSS_NLLSO_RX)
+#define NSS_NLLSO_RX_INIT nss_nllso_rx_init
+#define NSS_NLLSO_RX_EXIT nss_nllso_rx_exit
+#else
+#define NSS_NLLSO_RX_INIT 0
+#define NSS_NLLSO_RX_EXIT 0
+#endif /* !CONFIG_NSS_NLLSO_RX */
+
+#endif /* __NSS_NLLSO_RX_H */
diff --git a/qca-nss-clients/netlink/nss_nlmap_t.c b/qca-nss-clients/netlink/nss_nlmap_t.c
new file mode 100644
index 0000000..23e8bc5
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlmap_t.c
@@ -0,0 +1,179 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlmap_t.c
+ *      NSS Netlink map_t Handler
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/notifier.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nlmap_t_if.h"
+#include "nss_map_t.h"
+
+/*
+ * prototypes
+ */
+static int nss_nlmap_t_ops_get_stats(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlmap_t_process_notify(struct notifier_block *nb, unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nlmap_t_mcgrp[] = {
+	{.name = NSS_NLMAP_T_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nlmap_t_ops[] = {
+	{.cmd = NSS_STATS_EVENT_NOTIFY, .doit = nss_nlmap_t_ops_get_stats},
+};
+
+/*
+ * map_t family definition
+ */
+static struct genl_family nss_nlmap_t_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,						/* Auto generate ID */
+#endif
+	.name = NSS_NLMAP_T_FAMILY,					/* family name string */
+	.hdrsize = sizeof(struct nss_map_t_stats_notification),		/* NSS NETLINK map_t stats */
+	.version = NSS_NL_VER,						/* Set it to NSS_NLMAP_T version */
+	.maxattr = NSS_STATS_EVENT_MAX,					/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nlmap_t_ops,
+	.n_ops = ARRAY_SIZE(nss_nlmap_t_ops),
+	.mcgrps = nss_nlmap_t_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nlmap_t_mcgrp)
+};
+
+/*
+ * device call back handler for map_t from NSS
+ */
+static struct notifier_block nss_map_t_stats_notifier_nb = {
+	.notifier_call = nss_nlmap_t_process_notify,
+};
+
+/*
+ * nss_nlmap_t_ops_get_stats()
+ *	get stats handler
+ */
+static int nss_nlmap_t_ops_get_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+/*
+ * nss_nlmap_t_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nlmap_t_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct sk_buff *skb;
+	struct nss_map_t_stats_notification *nss_stats, *nl_stats;
+
+	nss_stats = (struct nss_map_t_stats_notification *)data;
+	skb = nss_nl_new_msg(&nss_nlmap_t_family, NSS_NLCMN_SUBSYS_MAP_T);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLMAP_T event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_stats = nss_nl_get_data(skb);
+	memcpy(nl_stats, nss_stats, sizeof(struct nss_map_t_stats_notification));
+	nss_nl_mcast_event(&nss_nlmap_t_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nlmap_t_init()
+ *	handler init
+ */
+bool nss_nlmap_t_init(void)
+{
+	int error,ret;
+
+	nss_nl_info_always("Init NSS netlink map_t handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nlmap_t_family);
+	if (error) {
+		nss_nl_info_always("Error: unable to register map_t family\n");
+		return false;
+	}
+
+	/*
+	 * register device call back handler for map_t from NSS
+	 */
+	ret = nss_map_t_stats_register_notifier(&nss_map_t_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context\n");
+		genl_unregister_family(&nss_nlmap_t_family);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nlmap_t_exit()
+ *	handler exit
+ */
+bool nss_nlmap_t_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink map_t handler\n");
+
+	/*
+	 * Unregister the device callback handler for map_t
+	 */
+	nss_map_t_stats_unregister_notifier(&nss_map_t_stats_notifier_nb);
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nlmap_t_family);
+	if (error) {
+		nss_nl_info_always("unable to unregister map_t NETLINK family\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nlmap_t.h b/qca-nss-clients/netlink/nss_nlmap_t.h
new file mode 100644
index 0000000..1608288
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlmap_t.h
@@ -0,0 +1,37 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlmap_t.h
+ *	NSS Netlink map_t API definitions
+ */
+#ifndef __NSS_NLMAP_T_H
+#define __NSS_NLMAP_T_H
+
+bool nss_nlmap_t_init(void);
+bool nss_nlmap_t_exit(void);
+
+#if defined(CONFIG_NSS_NLMAP_T)
+#define NSS_NLMAP_T_INIT nss_nlmap_t_init
+#define NSS_NLMAP_T_EXIT nss_nlmap_t_exit
+#else
+#define NSS_NLMAP_T_INIT 0
+#define NSS_NLMAP_T_EXIT 0
+#endif /* !CONFIG_NSS_NLMAP_T */
+
+#endif /* __NSS_NLMAP_T_H */
diff --git a/qca-nss-clients/netlink/nss_nln2h.c b/qca-nss-clients/netlink/nss_nln2h.c
new file mode 100644
index 0000000..e56d31f
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nln2h.c
@@ -0,0 +1,178 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nln2h.c
+ *      NSS Netlink n2h Handler
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/notifier.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nln2h_if.h"
+#include "nss_n2h.h"
+
+/*
+ * prototypes
+ */
+static int nss_nln2h_ops_get_stats(struct sk_buff *skb, struct genl_info *info);
+static int nss_nln2h_process_notify(struct notifier_block *nb,  unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nln2h_mcgrp[] = {
+	{.name = NSS_NLN2H_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nln2h_ops[] = {
+	{.cmd = NSS_STATS_EVENT_NOTIFY, .doit = nss_nln2h_ops_get_stats},
+};
+
+/*
+ * n2h family definition
+ */
+static struct genl_family nss_nln2h_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,					/* Auto generate ID */
+#endif
+	.name = NSS_NLN2H_FAMILY,				/* family name string */
+	.hdrsize = sizeof(struct nss_n2h_stats_notification),	/* NSS NETLINK n2h stats */
+	.version = NSS_NL_VER,					/* Set it to NSS_NLN2H version */
+	.maxattr = NSS_STATS_EVENT_MAX,				/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nln2h_ops,
+	.n_ops = ARRAY_SIZE(nss_nln2h_ops),
+	.mcgrps = nss_nln2h_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nln2h_mcgrp)
+};
+
+/*
+ * stats call back handler for n2h from NSS
+ */
+static struct notifier_block nss_n2h_stats_notifier_nb = {
+	.notifier_call = nss_nln2h_process_notify,
+};
+
+/*
+ * nss_nln2h_ops_get_stats()
+ *	get stats handler
+ */
+static int nss_nln2h_ops_get_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+/*
+ * nss_nln2h_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nln2h_process_notify(struct notifier_block *nb,	unsigned long val, void *data)
+{
+	struct sk_buff *skb;
+	struct nss_n2h_stats_notification *nss_stats, *nl_stats;
+
+	skb = nss_nl_new_msg(&nss_nln2h_family, NSS_NLCMN_SUBSYS_N2H);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLN2H event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_stats = nss_nl_get_data(skb);
+	nss_stats = (struct nss_n2h_stats_notification *)data;
+	memcpy(nl_stats, nss_stats, sizeof(struct nss_n2h_stats_notification));
+	nss_nl_mcast_event(&nss_nln2h_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nln2h_init()
+ *	handler init
+ */
+bool nss_nln2h_init(void)
+{
+	int error,ret;
+
+	nss_nl_info_always("Init NSS netlink n2h handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nln2h_family);
+	if (error) {
+		nss_nl_info_always("Error: unable to register n2h family\n");
+		return false;
+	}
+
+	/*
+	 * register device call back handler for n2h from NSS
+	 */
+	ret = nss_n2h_stats_register_notifier(&nss_n2h_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context\n");
+		genl_unregister_family(&nss_nln2h_family);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nln2h_exit()
+ *	handler exit
+ */
+bool nss_nln2h_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink n2h handler\n");
+
+	/*
+	 * Unregister the device callback handler for n2h
+	 */
+	nss_n2h_stats_unregister_notifier(&nss_n2h_stats_notifier_nb);
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nln2h_family);
+	if (error) {
+		nss_nl_info_always("unable to unregister n2h NETLINK family\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nln2h.h b/qca-nss-clients/netlink/nss_nln2h.h
new file mode 100644
index 0000000..2bdaecd
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nln2h.h
@@ -0,0 +1,38 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nln2h.h
+ *      NSS Netlink n2h API definitions
+ */
+#ifndef __NSS_NLN2H_H
+#define __NSS_NLN2H_H
+
+bool nss_nln2h_init(void);
+bool nss_nln2h_exit(void);
+
+#if defined(CONFIG_NSS_NLN2H)
+#define NSS_NLN2H_INIT nss_nln2h_init
+#define NSS_NLN2H_EXIT nss_nln2h_exit
+#else
+#define NSS_NLN2H_INIT 0
+#define NSS_NLN2H_EXIT 0
+#endif /* !CONFIG_NSS_NLN2H */
+
+#endif /* __NSS_NLN2H_H */
+
diff --git a/qca-nss-clients/netlink/nss_nloam.c b/qca-nss-clients/netlink/nss_nloam.c
new file mode 100644
index 0000000..e0eb85e
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nloam.c
@@ -0,0 +1,393 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016,2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nloam.c
+ *	NSS Netlink OAM Handler
+ *
+ * This nss netlink oam module receives request message from
+ * oam adapter and forward it to nss. It also receive responses
+ * from nss and forward it to oam adapter.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+
+#include <net/genetlink.h>
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include <nss_oam.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nloam_if.h"
+
+/*
+ * prototype declaration for functions
+ */
+static int nss_nloam_op_none(struct sk_buff *skb, struct genl_info *info);
+static int nss_nloam_op_get_req(struct sk_buff *skb, struct genl_info *info);
+static void nss_nloam_process_resp(void *app_data, struct nss_oam_msg *nom);
+static int nss_nloam_get_fw_pre_req(void *msg, struct nss_oam_msg *nom);
+static int nss_nloam_get_fw_post_resp(void *msg, struct nss_oam_msg *nom);
+
+/*
+ * global context for nss_nloam
+ */
+struct nss_nloam_ctx {
+	void *nss_ctx;
+};
+
+static struct nss_nloam_ctx global_nloam_ctx;
+
+typedef int (*nss_nloam_msg_cb_t)(void *msg, struct nss_oam_msg *nom);
+
+/*
+ * message map for message type and rec_id
+ */
+struct nss_nloam_msg_map {
+	uint32_t msg_type;
+	int32_t rec_id;
+
+	int8_t cmd_type;
+	int8_t res[3];
+
+	nss_nloam_msg_cb_t pre_req;
+	nss_nloam_msg_cb_t post_resp;
+};
+
+struct nss_nloam_msg_map global_nloam_msg_map[] = {
+	{
+		.msg_type = NSS_OAM_MSG_TYPE_GET_FW_VER,
+		.rec_id = NSS_NLOAM_GET_TYPE_FW_VERSION,
+		.cmd_type = NSS_NLOAM_CMD_GET_REQ,
+		.pre_req = nss_nloam_get_fw_pre_req,
+		.post_resp = nss_nloam_get_fw_post_resp,
+	},
+};
+
+static struct genl_multicast_group nss_nloam_mcgrp[] = {
+	{.name = NSS_NLOAM_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nloam_ops[] = {
+	{.cmd = NSS_NLOAM_CMD_NONE, .doit = nss_nloam_op_none,},
+	{.cmd = NSS_NLOAM_CMD_GET_REQ, .doit = nss_nloam_op_get_req,},
+};
+
+/*
+ * OAM family definition
+ */
+static struct genl_family nss_nloam_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,				/* Auto generate ID */
+#endif
+	.name = NSS_NLOAM_FAMILY,			/* family name string */
+	.hdrsize = sizeof(struct nss_nloam_rule),	/* NLOAM msg size */
+	.version = NSS_NL_VER,				/* nss netlink version */
+	.maxattr = NSS_NLOAM_CMD_MAX,			/* maximum commands supported */
+	.netnsok = false,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nloam_ops,
+	.n_ops = ARRAY_SIZE(nss_nloam_ops),
+	.mcgrps = nss_nloam_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nloam_mcgrp)
+};
+
+#define NSS_NLOAM_OPS_SZ ARRAY_SIZE(nss_nloam_ops)
+#define NSS_NLOAM_PAYLOAD_SZ sizeof(struct nss_oam_msg) - sizeof(struct nss_cmn_msg)
+
+/*
+ * nss_nloam_get_fw_pre_req()
+ *	call back for get firmware version request message.
+ */
+static int nss_nloam_get_fw_pre_req(void *msg, struct nss_oam_msg *nom)
+{
+	struct nss_nloam_get_req *get_req = (struct nss_nloam_get_req *)msg;
+
+	if (get_req->clear_on_read) {
+		nss_nl_error("clear_on_read is invalid for get_fw_version\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nloam_get_fw_post_resp()
+ *	call back for get firmware version response message.
+ */
+static int nss_nloam_get_fw_post_resp(void *msg, struct nss_oam_msg *nom)
+{
+	struct nss_nloam_get_resp *get_resp = (struct nss_nloam_get_resp *)msg;
+	uint32_t error;
+	char *fw_ver;
+
+	fw_ver = nom->msg.fw_ver.string;
+	get_resp->length = strlen(fw_ver);
+
+	/*
+	 * Check the response status from fw.
+	 */
+	if (nom->cm.response == NSS_CMN_RESPONSE_EMSG) {
+		nss_nl_error("response message with error status\n");
+		error = nom->cm.error;
+		goto fail;
+	}
+
+	/*
+	 * Check for max length
+	 */
+	if (get_resp->length >= NSS_OAM_FW_VERSION_LEN) {
+		nss_nl_error("nss fw version exceeds max length\n");
+		error = ENOBUFS;
+		goto fail;
+	}
+
+	strlcpy((char *)get_resp->bin, nom->msg.fw_ver.string, NSS_OAM_FW_VERSION_LEN);
+	get_resp->bin[NSS_OAM_FW_VERSION_LEN - 1] = '\0';
+	get_resp->error_no = 0;
+
+	return 0;
+fail:
+	/*
+	 * As user app expects bin is a null terminated string
+	 * On failure terminating with only '\0' - empty string
+	 */
+	get_resp->bin[0] = '\0';
+	get_resp->error_no = error;
+	return -error;
+}
+
+/*
+ * nss_nloam_find_msg_idx()
+ *	Helper function to find the message of a command from msg_map
+ */
+static struct nss_nloam_msg_map *nss_nloam_find_msg(uint8_t cmd_type, uint32_t rec_id)
+{
+	struct nss_nloam_msg_map *msg;
+	const size_t array_sz = ARRAY_SIZE(global_nloam_msg_map);
+	int i = 0;
+
+	for (i = 0, msg = &global_nloam_msg_map[0]; i < array_sz; i++, msg++) {
+		if ((msg->cmd_type == cmd_type) && (msg->rec_id == rec_id)) {
+			return msg;
+		}
+	}
+	return NULL;
+}
+
+/*
+ * nss_nloam_op_none()
+ *	invalid command handler; ideally nobody should call this
+ */
+static int nss_nloam_op_none(struct sk_buff *skb, struct genl_info *info)
+{
+	nss_nl_error("unable to reply generic message\n");
+	return -ENOENT;
+}
+
+/*
+ * nss_nloam_op_get_req()
+ *	sends the user data to NSS HLOS driver to forward the request to NSS FW
+ */
+static int nss_nloam_op_get_req(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nloam_get_req *get_req;
+	struct nss_nloam_rule *nl_oam;
+	struct nss_nloam_msg_map *msg;
+	nss_tx_status_t tx_status;
+	struct nss_nlcmn *nl_cm;
+	struct nss_oam_msg nom;
+	struct sk_buff *resp;
+	uint32_t error = 0;
+	uint32_t msg_type;
+	uint8_t cmd_type;
+	uint32_t pid;
+
+	/*
+	 * extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nloam_family, info, NSS_NLOAM_CMD_SET_REQ);
+	if (!nl_cm) {
+		nss_nl_error("unable to extract oam req cmd\n");
+		error = -EINVAL;
+		goto error;
+	}
+
+	nl_oam = container_of(nl_cm, struct nss_nloam_rule, cm);
+	pid = nl_cm->pid;
+
+	/*
+	 * Frame message to send nss according to the recieved request
+	 */
+	cmd_type = nss_nlcmn_get_cmd(nl_cm);
+	get_req = &nl_oam->msg.get_req;
+
+	msg = nss_nloam_find_msg(cmd_type, get_req->rec_id);
+	if (!msg) {
+		nss_nl_error("%d: invalid OAM CMD (type - %d, rec - %d)\n", pid, cmd_type, get_req->rec_id);
+		error = -EINVAL;
+		goto error;
+	}
+
+	BUG_ON(!msg->pre_req);
+	error = msg->pre_req(get_req, &nom);
+	if (error) {
+		goto error;
+	}
+
+	msg_type = msg->msg_type;
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("%d: unable to save response data from NL buffer\n", pid);
+		error = -ENOMEM;
+		goto error;
+	}
+
+	/*
+	 * Initialize the common message before sending to NSS
+	 */
+	nss_cmn_msg_init(&nom.cm,				/* common message */
+			NSS_OAM_INTERFACE,			/* oam if number */
+			msg_type,				/* type */
+			NSS_NLOAM_PAYLOAD_SZ,			/* message len */
+			nss_nloam_process_resp, 		/* callback */
+			(void *)resp);				/* app context */
+
+	/*
+	 * Push the Rule to NSS
+	 */
+	tx_status = nss_oam_tx_msg(global_nloam_ctx.nss_ctx, &nom);
+	if (NSS_TX_SUCCESS != tx_status) {
+		nss_nl_error("Error in Pushing the oam message\n");
+		error = -EBUSY;
+		goto free;
+	}
+
+	return 0;
+
+free:
+	dev_kfree_skb_any(resp);
+error:
+	return error;
+}
+
+/*
+ * nss_nloam_process_resp()
+ *	Process the response message for a command sent
+ */
+static void nss_nloam_process_resp(void *app_data, struct nss_oam_msg *nom)
+{
+	struct sk_buff *resp = (struct sk_buff *)app_data;
+	struct nss_nloam_rule *nl_oam_reply;
+	struct nss_nloam_msg_map *msg;
+	uint8_t cmd_type;
+
+	nl_oam_reply = (struct nss_nloam_rule *) nss_nl_get_data(resp);
+
+	cmd_type = nss_nlcmn_get_cmd(&nl_oam_reply->cm);
+	msg = nss_nloam_find_msg(cmd_type, nl_oam_reply->msg.get_req.rec_id);
+
+	if (!msg) {
+		nss_nl_error("invalid message reply for get request: %d\n", cmd_type);
+		return;
+	}
+
+	BUG_ON(!msg->post_resp);
+	msg->post_resp(&nl_oam_reply->msg, nom);
+	nss_nl_ucast_resp(resp);
+}
+
+/*
+ * nss_nloam_process_notify()
+ *	Process the notify message from nss
+ */
+static void nss_nloam_process_notify(void *app_data, struct nss_oam_msg *nom)
+{
+	/*
+	 * As of now there is no notify message expected from nss
+	 */
+	nss_nl_info("handler for nss nloam notify message\n");
+}
+
+/*
+ * nss_nloam_init()
+ *	handler init
+ */
+bool nss_nloam_init(void)
+{
+	int error;
+
+	/*
+	 * register with the family
+	 */
+	error = genl_register_family(&nss_nloam_family);
+	if (error != 0) {
+		nss_nl_info_always("unable to register OAM family\n");
+		return false;
+	}
+
+	/*
+	 * register device call back handler for OAM from NSS
+	 */
+	global_nloam_ctx.nss_ctx = nss_oam_notify_register(nss_nloam_process_notify, NULL);
+	if (!global_nloam_ctx.nss_ctx) {
+		nss_nl_error("Error in retreiving the NSS Context\n");
+		goto unreg_ops;
+	}
+
+	return true;
+
+unreg_ops:
+	genl_unregister_family(&nss_nloam_family);
+
+	return false;
+}
+
+/*
+ * nss_nloam_exit()
+ *	handler exit
+ */
+bool nss_nloam_exit(void)
+{
+	nss_nl_info_always("Uninitiallizing the NSS netlink oam handler\n");
+
+	/*
+	 * Unregister the device callback handler for oam
+	 */
+	nss_oam_notify_unregister();
+
+	/*
+	 * unregister with the family
+	 */
+	genl_unregister_family(&nss_nloam_family);
+
+	global_nloam_ctx.nss_ctx = NULL;
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nloam.h b/qca-nss-clients/netlink/nss_nloam.h
new file mode 100644
index 0000000..3327d05
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nloam.h
@@ -0,0 +1,36 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nloam.h
+ *	NSS Netlink OAM API definitions
+ */
+
+#ifndef __NSS_NLOAM_H
+#define __NSS_NLOAM_H
+
+bool nss_nloam_init(void);
+bool nss_nloam_exit(void);
+
+#if defined(CONFIG_NSS_NLOAM)
+#define NSS_NLOAM_INIT nss_nloam_init
+#define NSS_NLOAM_EXIT nss_nloam_exit
+#else
+#define NSS_NLOAM_INIT 0
+#define NSS_NLOAM_EXIT 0
+#endif /* !CONFIG_NSS_NLOAM */
+
+#endif /* __NSS_NLOAM_H */
diff --git a/qca-nss-clients/netlink/nss_nlpppoe.c b/qca-nss-clients/netlink/nss_nlpppoe.c
new file mode 100644
index 0000000..4cbc93b
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlpppoe.c
@@ -0,0 +1,179 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlpppoe.c
+ *	NSS Netlink pppoe Handler
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/notifier.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nlpppoe_if.h"
+#include "nss_pppoe.h"
+
+/*
+ * prototypes
+ */
+static int nss_nlpppoe_ops_get_stats(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlpppoe_process_notify(struct notifier_block *nb, unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nlpppoe_mcgrp[] = {
+	{.name = NSS_NLPPPOE_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nlpppoe_ops[] = {
+	{.cmd = NSS_STATS_EVENT_NOTIFY, .doit = nss_nlpppoe_ops_get_stats},
+};
+
+/*
+ * pppoe family definition
+ */
+static struct genl_family nss_nlpppoe_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,						/* Auto generate ID */
+#endif
+	.name = NSS_NLPPPOE_FAMILY,					/* family name string */
+	.hdrsize = sizeof(struct nss_pppoe_stats_notification),		/* NSS NETLINK pppoe stats */
+	.version = NSS_NL_VER,						/* Set it to NSS_NLPPPOE version */
+	.maxattr = NSS_STATS_EVENT_MAX,					/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nlpppoe_ops,
+	.n_ops = ARRAY_SIZE(nss_nlpppoe_ops),
+	.mcgrps = nss_nlpppoe_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nlpppoe_mcgrp)
+};
+
+/*
+ * device call back handler for pppoe from NSS
+ */
+static struct notifier_block nss_pppoe_stats_notifier_nb = {
+	.notifier_call = nss_nlpppoe_process_notify,
+};
+
+/*
+ * nss_nlpppoe_ops_get_stats()
+ *	get stats handler
+ */
+static int nss_nlpppoe_ops_get_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+/*
+ * nss_nlpppoe_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nlpppoe_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct sk_buff *skb;
+	struct nss_pppoe_stats_notification *nss_stats, *nl_stats;
+
+	nss_stats = (struct nss_pppoe_stats_notification *)data;
+	skb = nss_nl_new_msg(&nss_nlpppoe_family, NSS_NLCMN_SUBSYS_PPPOE);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLPPPOE event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_stats = nss_nl_get_data(skb);
+	memcpy(nl_stats, nss_stats, sizeof(struct nss_pppoe_stats_notification));
+	nss_nl_mcast_event(&nss_nlpppoe_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nlpppoe_init()
+ *	handler init
+ */
+bool nss_nlpppoe_init(void)
+{
+	int error,ret;
+
+	nss_nl_info_always("Init NSS netlink pppoe handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nlpppoe_family);
+	if (error) {
+		nss_nl_info_always("Error: unable to register pppoe family\n");
+		return false;
+	}
+
+	/*
+	 * register device call back handler for pppoe from NSS
+	 */
+	ret = nss_pppoe_stats_register_notifier(&nss_pppoe_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context\n");
+		genl_unregister_family(&nss_nlpppoe_family);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nlpppoe_exit()
+ *	handler exit
+ */
+bool nss_nlpppoe_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink pppoe handler\n");
+
+	/*
+	 * Unregister the device callback handler for pppoe
+	 */
+	nss_pppoe_stats_unregister_notifier(&nss_pppoe_stats_notifier_nb);
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nlpppoe_family);
+	if (error) {
+		nss_nl_info_always("unable to unregister pppoe NETLINK family\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nlpppoe.h b/qca-nss-clients/netlink/nss_nlpppoe.h
new file mode 100644
index 0000000..9740127
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlpppoe.h
@@ -0,0 +1,37 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlpppoe.h
+ *	NSS Netlink pppoe API definitions
+ */
+#ifndef __NSS_NLPPPOE_H
+#define __NSS_NLPPPOE_H
+
+bool nss_nlpppoe_init(void);
+bool nss_nlpppoe_exit(void);
+
+#if defined(CONFIG_NSS_NLPPPOE)
+#define NSS_NLPPPOE_INIT nss_nlpppoe_init
+#define NSS_NLPPPOE_EXIT nss_nlpppoe_exit
+#else
+#define NSS_NLPPPOE_INIT 0
+#define NSS_NLPPPOE_EXIT 0
+#endif /* !CONFIG_NSS_NLPPPOE */
+
+#endif /* __NSS_NLPPPOE_H */
diff --git a/qca-nss-clients/netlink/nss_nlpptp.c b/qca-nss-clients/netlink/nss_nlpptp.c
new file mode 100644
index 0000000..b142b2a
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlpptp.c
@@ -0,0 +1,179 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlpptp.c
+ *	NSS Netlink pptp Handler
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/notifier.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nlpptp_if.h"
+#include "nss_pptp.h"
+
+/*
+ * prototypes
+ */
+static int nss_nlpptp_ops_get_stats(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlpptp_process_notify(struct notifier_block *nb, unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nlpptp_mcgrp[] = {
+	{.name = NSS_NLPPTP_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nlpptp_ops[] = {
+	{.cmd = NSS_STATS_EVENT_NOTIFY, .doit = nss_nlpptp_ops_get_stats},
+};
+
+/*
+ * pptp family definition
+ */
+static struct genl_family nss_nlpptp_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,						/* Auto generate ID */
+#endif
+	.name = NSS_NLPPTP_FAMILY,					/* family name string */
+	.hdrsize = sizeof(struct nss_pptp_stats_notification),		/* NSS NETLINK pptp stats */
+	.version = NSS_NL_VER,						/* Set it to NSS_NLPPTP version */
+	.maxattr = NSS_STATS_EVENT_MAX,					/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nlpptp_ops,
+	.n_ops = ARRAY_SIZE(nss_nlpptp_ops),
+	.mcgrps = nss_nlpptp_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nlpptp_mcgrp)
+};
+
+/*
+ * device call back handler for pptp from NSS
+ */
+static struct notifier_block nss_pptp_stats_notifier_nb = {
+	.notifier_call = nss_nlpptp_process_notify,
+};
+
+/*
+ * nss_nlpptp_ops_get_stats()
+ *	get stats handler
+ */
+static int nss_nlpptp_ops_get_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+/*
+ * nss_nlpptp_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nlpptp_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct sk_buff *skb;
+	struct nss_pptp_stats_notification *nss_stats, *nl_stats;
+
+	nss_stats = (struct nss_pptp_stats_notification *)data;
+	skb = nss_nl_new_msg(&nss_nlpptp_family, NSS_NLCMN_SUBSYS_PPTP);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLPPTP event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_stats = nss_nl_get_data(skb);
+	memcpy(nl_stats, nss_stats, sizeof(struct nss_pptp_stats_notification));
+	nss_nl_mcast_event(&nss_nlpptp_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nlpptp_init()
+ *	handler init
+ */
+bool nss_nlpptp_init(void)
+{
+	int error,ret;
+
+	nss_nl_info_always("Init NSS netlink pptp handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nlpptp_family);
+	if (error) {
+		nss_nl_info_always("Error: unable to register pptp family\n");
+		return false;
+	}
+
+	/*
+	 * register device call back handler for pptp from NSS
+	 */
+	ret = nss_pptp_stats_register_notifier(&nss_pptp_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context\n");
+		genl_unregister_family(&nss_nlpptp_family);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nlpptp_exit()
+ *	handler exit
+ */
+bool nss_nlpptp_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink pptp handler\n");
+
+	/*
+	 * Unregister the device callback handler for pptp
+	 */
+	nss_pptp_stats_unregister_notifier(&nss_pptp_stats_notifier_nb);
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nlpptp_family);
+	if (error) {
+		nss_nl_info_always("unable to unregister pptp NETLINK family\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nlpptp.h b/qca-nss-clients/netlink/nss_nlpptp.h
new file mode 100644
index 0000000..8215501
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlpptp.h
@@ -0,0 +1,37 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlpptp.h
+ *	NSS Netlink pptp API definitions
+ */
+#ifndef __NSS_NLPPTP_H
+#define __NSS_NLPPTP_H
+
+bool nss_nlpptp_init(void);
+bool nss_nlpptp_exit(void);
+
+#if defined(CONFIG_NSS_NLPPTP)
+#define NSS_NLPPTP_INIT nss_nlpptp_init
+#define NSS_NLPPTP_EXIT nss_nlpptp_exit
+#else
+#define NSS_NLPPTP_INIT 0
+#define NSS_NLPPTP_EXIT 0
+#endif /* !CONFIG_NSS_NLPPTP */
+
+#endif /* __NSS_NLPPTP_H */
diff --git a/qca-nss-clients/netlink/nss_nludp_st.c b/qca-nss-clients/netlink/nss_nludp_st.c
new file mode 100755
index 0000000..a769b3c
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nludp_st.c
@@ -0,0 +1,1268 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nludp_st.c
+ *	NSS Netlink udp_st Handler
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+#include <net/arp.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nludp_st_if.h"
+#include "nss_nludp_st.h"
+
+/*
+ * prototypes
+ */
+static int nss_nludp_st_ops_uncfg_rule(struct sk_buff *skb, struct genl_info *info);
+static int nss_nludp_st_ops_cfg_rule(struct sk_buff *skb, struct genl_info *info);
+static int nss_nludp_st_ops_stop(struct sk_buff *skb, struct genl_info *info);
+static int nss_nludp_st_ops_start(struct sk_buff *skb, struct genl_info *info);
+static int nss_nludp_st_ops_tx_destroy(struct sk_buff *skb, struct genl_info *info);
+static int nss_nludp_st_ops_tx_create(struct sk_buff *skb, struct genl_info *info);
+static int nss_nludp_st_ops_reset_stats(struct sk_buff *skb, struct genl_info *info);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nludp_st_mcgrp[] = {
+	{.name = NSS_NLUDP_ST_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nludp_st_ops[] = {
+	{.cmd = NSS_UDP_ST_CFG_RULE_MSG, .doit = nss_nludp_st_ops_cfg_rule,},
+	{.cmd = NSS_UDP_ST_UNCFG_RULE_MSG, .doit = nss_nludp_st_ops_uncfg_rule,},
+	{.cmd = NSS_UDP_ST_START_MSG, .doit = nss_nludp_st_ops_start,},
+	{.cmd = NSS_UDP_ST_STOP_MSG, .doit = nss_nludp_st_ops_stop,},
+	{.cmd = NSS_UDP_ST_TX_CREATE_MSG, .doit = nss_nludp_st_ops_tx_create,},
+	{.cmd = NSS_UDP_ST_TX_DESTROY_MSG, .doit = nss_nludp_st_ops_tx_destroy,},
+	{.cmd = NSS_UDP_ST_RESET_STATS_MSG, .doit = nss_nludp_st_ops_reset_stats,},
+};
+
+/*
+ * udp_st family definition
+ */
+static struct genl_family nss_nludp_st_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,						/* Auto generate ID */
+#endif
+	.name = NSS_NLUDP_ST_FAMILY,					/* family name string */
+	.hdrsize = sizeof(struct nss_nludp_st_rule),			/* NSS NETLINK udp_st rule */
+	.version = NSS_NL_VER,						/* Set it to NSS_NLudp_st version */
+	.maxattr = NSS_UDP_ST_MAX_MSG_TYPES,				/* Maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nludp_st_ops,
+	.n_ops = ARRAY_SIZE(nss_nludp_st_ops),
+	.mcgrps = nss_nludp_st_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nludp_st_mcgrp)
+};
+
+/*
+ * nss_nludp_st_process_resp()
+ *      handle responses
+ */
+static void nss_nludp_st_process_resp(void *app_data, struct nss_udp_st_msg *num)
+{
+	struct sk_buff *resp = (struct sk_buff *)app_data;
+	struct nss_nludp_st_rule *nl_rule;
+	struct nss_udp_st_msg *nl_num;
+
+	nl_rule = nss_nl_get_data(resp);
+	nl_num = &nl_rule->num;
+
+	/*
+	 * clear NSS common message items that are not useful to uspace
+	 */
+	num->cm.interface = 0;
+	num->cm.cb = (nss_ptr_t)NULL;
+	num->cm.app_data = (nss_ptr_t)NULL;
+
+	/*
+	 * copy the message response data into the NL message buffer. If, FW
+	 * has updated the message then we must updated the same into the NL
+	 * message as the NL message buffer is different from what was sent
+	 * to FW
+	 */
+	memcpy(nl_num, num, sizeof(struct nss_udp_st_msg));
+
+	nss_nl_ucast_resp(resp);
+}
+
+/*
+ * nss_nludp_st_ops_stop
+ *      Stop UDP spedtest
+ */
+static int nss_nludp_st_ops_stop(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nludp_st_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_udp_st_msg num;
+	struct sk_buff *resp;
+	nss_tx_status_t status;
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nludp_st_family, info, NSS_UDP_ST_STOP_MSG);
+	if (!nl_cm) {
+		nss_nl_error("%px: Unable to extract udp_st stop data\n", skb);
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nludp_st_rule, cm);
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("%p:unable to save response data from NL buffer\n", nl_rule);
+		return -ENOMEM;
+	}
+
+	nss_ctx = nss_udp_st_get_mgr();
+	if (!nss_ctx) {
+		nss_nl_info("Couldn't get udp_st ctx\n");
+		return -EPERM;
+	}
+
+
+	memset(&num, 0, sizeof(struct nss_udp_st_msg));
+	nss_udp_st_msg_init(&num,				/* udp_st message */
+			NSS_UDP_ST_INTERFACE,			/* interface number */
+			NSS_UDP_ST_STOP_MSG,			/* rule */
+			sizeof(struct nss_udp_st_stop),	/* message size */
+			nss_nludp_st_process_resp,		/* response callback */
+			(void *)resp);				/* app context */
+
+
+	memcpy(&num.msg.stop, &nl_rule->num.msg.stop, sizeof(struct nss_udp_st_stop));
+
+	status = nss_udp_st_tx_sync(nss_ctx, &num);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_info("%px: Create udp_st message failed %d\n", nss_ctx, status);
+		return -EBADMSG;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nludp_st_ops_start
+ *	Start UDP spedtest
+ */
+static int nss_nludp_st_ops_start(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nludp_st_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_udp_st_msg num;
+	struct sk_buff *resp;
+	uint32_t pid;
+	nss_tx_status_t status;
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nludp_st_family, info, NSS_UDP_ST_START_MSG);
+	if (!nl_cm) {
+		nss_nl_error("%px: Unable to extract udp_st start data\n", skb);
+		return -EINVAL;
+	}
+
+	pid = nl_cm->pid;
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nludp_st_rule, cm);
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("%p:unable to save response data from NL buffer\n", nl_rule);
+		return -ENOMEM;
+	}
+
+	nss_ctx = nss_udp_st_get_mgr();
+	if (!nss_ctx) {
+		nss_nl_info("Couldn't get udp_st ctx\n");
+		return -ENOENT;
+	}
+
+	memset(&num, 0, sizeof(struct nss_udp_st_msg));
+	nss_udp_st_msg_init(&num,				/* udp_st message */
+			NSS_UDP_ST_INTERFACE,			/* interface number */
+			NSS_UDP_ST_START_MSG,			/* rule */
+			sizeof(struct nss_udp_st_start),	/* message size */
+			nss_nludp_st_process_resp,		/* response callback */
+			(void *)resp);				/* app context */
+
+	memcpy(&num.msg.start, &nl_rule->num.msg.start, sizeof(struct nss_udp_st_start));
+
+	status = nss_udp_st_tx_sync(nss_ctx, &num);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_info("%px: Create udp_st message failed %d\n", nss_ctx, status);
+		return -EBADMSG;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nludp_st_ops_reset_stats
+ *	Resets UDP speed test statistics.
+ */
+static int nss_nludp_st_ops_reset_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nludp_st_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_udp_st_msg num;
+	struct sk_buff *resp;
+	uint32_t pid;
+	nss_tx_status_t status;
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nludp_st_family, info, NSS_UDP_ST_RESET_STATS_MSG);
+	if (!nl_cm) {
+		nss_nl_error("%px: Unable to extract udp_st reset stats data\n", skb);
+		return -EINVAL;
+	}
+
+	pid = nl_cm->pid;
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nludp_st_rule, cm);
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("%p:unable to save response data from NL buffer\n", nl_rule);
+		return -ENOMEM;
+	}
+
+	nss_ctx = nss_udp_st_get_mgr();
+	if (!nss_ctx) {
+		nss_nl_info("Couldn't get udp_st ctx\n");
+		return -ENOENT;
+	}
+
+	memset(&num, 0, sizeof(struct nss_udp_st_msg));
+	nss_udp_st_msg_init(&num,				/* udp_st message */
+			NSS_UDP_ST_INTERFACE,			/* interface number */
+			NSS_UDP_ST_RESET_STATS_MSG,		/* UDP ST stats reset */
+			sizeof(struct nss_udp_st_reset_stats),	/* message size */
+			nss_nludp_st_process_resp,		/* response callback */
+			(void *)resp);				/* app context */
+
+	status = nss_udp_st_tx_sync(nss_ctx, &num);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_info("%px: Create udp_st message failed %d\n", nss_ctx, status);
+		return -EBADMSG;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nludp_st_ops_tx_destroy
+ *	Destroys UDP speed test Tx node.
+ */
+static int nss_nludp_st_ops_tx_destroy(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nludp_st_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_udp_st_msg num;
+	struct sk_buff *resp;
+	uint32_t pid;
+	nss_tx_status_t status;
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nludp_st_family, info, NSS_UDP_ST_TX_DESTROY_MSG);
+	if (!nl_cm) {
+		nss_nl_error("%px: Unable to extract udp_st tx destroy data\n", skb);
+		return -EINVAL;
+	}
+
+	pid = nl_cm->pid;
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nludp_st_rule, cm);
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("%p:unable to save response data from NL buffer\n", nl_rule);
+		return -ENOMEM;
+	}
+
+	nss_ctx = nss_udp_st_get_mgr();
+	if (!nss_ctx) {
+		nss_nl_info("Couldn't get udp_st ctx\n");
+		return -ENOENT;
+	}
+
+	memset(&num, 0, sizeof(struct nss_udp_st_msg));
+	nss_udp_st_msg_init(&num,				/* udp_st message */
+			NSS_UDP_ST_INTERFACE,			/* interface number */
+			NSS_UDP_ST_TX_DESTROY_MSG,		/* UDP ST tx destroy */
+			sizeof(struct nss_udp_st_tx_destroy),	/* message size */
+			nss_nludp_st_process_resp,		/* response callback */
+			(void *)resp);				/* app context */
+
+	status = nss_udp_st_tx_sync(nss_ctx, &num);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_info("%px: Create udp_st message failed %d\n", nss_ctx, status);
+		return -EBADMSG;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nludp_st_ops_tx_create
+ *	Creates UDP speed test Tx node.
+ */
+static int nss_nludp_st_ops_tx_create(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nludp_st_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_udp_st_msg num;
+	struct sk_buff *resp;
+	uint32_t pid;
+	nss_tx_status_t status;
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nludp_st_family, info, NSS_UDP_ST_TX_CREATE_MSG);
+	if (!nl_cm) {
+		nss_nl_error("%px: Unable to extract udp_st tx create data\n", skb);
+		return -EINVAL;
+	}
+
+	pid = nl_cm->pid;
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nludp_st_rule, cm);
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("%p:unable to save response data from NL buffer\n", nl_rule);
+		return -ENOMEM;
+	}
+
+	nss_ctx = nss_udp_st_get_mgr();
+	if (!nss_ctx) {
+		nss_nl_info("Couldn't get udp_st ctx\n");
+		return -ENOENT;
+	}
+
+	memset(&num, 0, sizeof(struct nss_udp_st_msg));
+	nss_udp_st_msg_init(&num,				/* udp_st message */
+			NSS_UDP_ST_INTERFACE,			/* interface number */
+			NSS_UDP_ST_TX_CREATE_MSG,		/* UDP ST tx create */
+			sizeof(struct nss_udp_st_tx_create),	/* message size */
+			nss_nludp_st_process_resp,		/* response callback */
+			(void *)resp);				/* app context */
+
+	memcpy(&num.msg.create, &nl_rule->num.msg.create, sizeof(struct nss_udp_st_tx_create));
+
+	status = nss_udp_st_tx_sync(nss_ctx, &num);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_info("%px: Create udp_st message failed %d\n", nss_ctx, status);
+		return -EBADMSG;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nludp_st_get_neigh_ipv4()
+ *	Returns neighbour reference for a given IP address
+ */
+static struct neighbour *nss_nludp_st_get_neigh_ipv4(uint32_t ip_addr)
+{
+	struct neighbour *neigh;
+	struct rtable *rt;
+	struct dst_entry *dst;
+
+	/*
+	 * search for route entry
+	 */
+	rt = ip_route_output(&init_net, ip_addr, 0, 0, 0);
+	if (IS_ERR(rt)) {
+		return NULL;
+	}
+
+	dst = (struct dst_entry *)rt;
+
+	/*
+	 * neighbour lookup using IP address in the route table
+	 */
+	neigh = dst_neigh_lookup(dst, &ip_addr);
+	if (likely(neigh)) {
+		dst_release(dst);
+		return neigh;
+	}
+
+	/*
+	 * neighbour lookup using IP address, device in the arp table
+	 */
+	neigh = neigh_lookup(&arp_tbl, &ip_addr, dst->dev);
+	if (likely(neigh)) {
+		dst_release(dst);
+		return neigh;
+	}
+
+	/*
+	 * dst reference count was held during the lookup
+	 */
+	dst_release(dst);
+	return NULL;
+}
+
+/*
+ * nss_nludp_st_mac_addr_get_ipv4()
+ *	Return the hardware (MAC) address of the given IPv4 address, if any.
+ *
+ * Returns 0 on success or a negative result on failure.
+ * We look up the rtable entry for the address and,
+ * from its neighbour structure,obtain the hardware address.
+ * This means we will also work if the neighbours are routers too.
+ */
+static int nss_nludp_st_get_macaddr_ipv4(uint32_t ip_addr, uint8_t mac_addr[])
+{
+	struct neighbour *neigh;
+
+	/*
+	 * handle multicast IP address seperately
+	 */
+	if (ipv4_is_multicast(htonl(ip_addr))) {
+		/*
+		 * fixed
+		 */
+		mac_addr[0] = 0x01;
+		mac_addr[1] = 0x00;
+		mac_addr[2] = 0x5e;
+
+		/*
+		 * from ip_addr
+		 */
+		mac_addr[3] = (htonl(ip_addr) & 0x7f0000) >> 16;
+		mac_addr[4] = (htonl(ip_addr) & 0xff00) >> 8;
+		mac_addr[5] = (htonl(ip_addr) & 0xff);
+
+		return 0;
+	}
+
+	/*
+	 * retrieve the neighbour
+	 */
+	rcu_read_lock();
+	neigh = nss_nludp_st_get_neigh_ipv4(htonl(ip_addr));
+	if (!neigh) {
+		rcu_read_unlock();
+		nss_nl_info("neighbour lookup failed for IP:0x%x\n", htonl(ip_addr));
+		return -ENODEV;
+	}
+	rcu_read_unlock();
+
+	if ((neigh->nud_state & NUD_VALID) == 0) {
+		nss_nl_info("neighbour state is invalid for IP:0x%x\n", htonl(ip_addr));
+		goto fail;
+	}
+
+	if (!neigh->dev) {
+		nss_nl_info("neighbour device not found for IP:0x%x\n", htonl(ip_addr));
+		goto fail;
+	}
+
+	if (is_multicast_ether_addr(neigh->ha)) {
+		nss_nl_info( "neighbour MAC address is multicast or broadcast\n");
+		goto fail;
+	}
+
+	ether_addr_copy(mac_addr, neigh->ha);
+	neigh_release(neigh);
+	return 0;
+
+fail:
+	neigh_release(neigh);
+	return -ENODEV;
+}
+
+/*
+ * nss_nludp_st_get_neigh_ipv6()
+ *	Returns neighbour reference for a given IP address
+ */
+static struct neighbour *nss_nludp_st_get_neigh_ipv6(uint32_t dst_addr[4])
+{
+	struct neighbour *neigh;
+	struct dst_entry *dst;
+	struct rt6_info *rt;
+	struct in6_addr daddr;
+
+	IPV6_ADDR_TO_IN6_ADDR(daddr, dst_addr);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0))
+	rt = rt6_lookup(&init_net, &daddr, NULL, 0, 0);
+#else
+	rt = rt6_lookup(&init_net, &daddr, NULL, 0, NULL, 0);
+#endif
+	if (!rt) {
+		return NULL;
+	}
+
+	dst = (struct dst_entry *)rt;
+
+	/*
+	 * neighbour lookup using IP address in the route table
+	 */
+	neigh = dst_neigh_lookup(dst, &daddr);
+	if (likely(neigh)) {
+		neigh_hold(neigh);
+		dst_release(dst);
+		return neigh;
+	}
+	dst_release(dst);
+
+	return NULL;
+}
+
+/*
+ * nss_nludp_st_get_addr_hton()
+ *	Convert the ipv6 address from host order to network order.
+ */
+static inline void nss_nludp_st_get_addr_hton(uint32_t src[4], uint32_t dst[4])
+{
+	nss_nludp_st_swap_addr_ipv6(src, dst);
+
+	dst[0] = htonl(dst[0]);
+	dst[1] = htonl(dst[1]);
+	dst[2] = htonl(dst[2]);
+	dst[3] = htonl(dst[3]);
+}
+
+/*
+ * nss_nludp_st_mac_addr_get_ipv6()
+ *	Return the hardware (MAC) address of the given ipv6 address, if any.
+ *
+ * Returns 0 on success or a negative result on failure.
+ * We look up the rtable entry for the address and,
+ * from its neighbour structure,obtain the hardware address.
+ * This means we will also work if the neighbours are routers too.
+ */
+static int nss_nludp_st_get_macaddr_ipv6(uint32_t ip_addr[4], uint8_t mac_addr[])
+{
+	struct neighbour *neigh;
+	struct  in6_addr addr;
+
+	nss_nludp_st_get_addr_hton(ip_addr, addr.s6_addr32);
+
+	if (ipv6_addr_is_multicast(&addr)) {
+		/*
+		 * fixed
+		 */
+		mac_addr[0] = 0x33;
+		mac_addr[1] = 0x33;
+
+		/*
+		 * Last word of the IPv6 address.
+		 */
+		memcpy(&mac_addr[2], &addr.s6_addr32[3], sizeof(uint32_t));
+		return 0;
+	}
+
+	rcu_read_lock();
+
+	/*
+	 * retrieve the neighbour
+	 */
+	neigh = nss_nludp_st_get_neigh_ipv6(addr.s6_addr32);
+	if (!neigh) {
+		rcu_read_unlock();
+		nss_nl_info("neighbour lookup failed for %pI6c\n", addr.s6_addr32);
+		return -ENODEV;
+	}
+
+	rcu_read_unlock();
+
+	if ((neigh->nud_state & NUD_VALID) == 0) {
+		nss_nl_info("neighbour state is invalid for %pI6c\n", addr.s6_addr32);
+		goto fail;
+	}
+
+	if (!neigh->dev) {
+		nss_nl_info("neighbour device not found for %pI6c\n", addr.s6_addr32);
+		goto fail;
+	}
+
+	if (is_multicast_ether_addr(neigh->ha)) {
+		nss_nl_info("neighbour MAC address is multicast or broadcast\n");
+		goto fail;
+	}
+
+	ether_addr_copy(mac_addr, neigh->ha);
+	neigh_release(neigh);
+	return 0;
+fail:
+	neigh_release(neigh);
+	return -ENODEV;
+}
+
+/*
+ * nss_nludp_st_destroy_ipv4_rule()
+ *	Destroy a nss entry to accelerate the given IPV4 connection
+ */
+static int nss_nludp_st_destroy_ipv4_rule(struct sk_buff *skb, struct nss_nludp_st_rule *nl_rule)
+{
+	struct nss_ipv4_rule_destroy_msg *nirdm;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_ipv4_msg nim;
+	struct sk_buff *resp;
+	nss_tx_status_t status;
+
+	nss_ctx = nss_ipv4_get_mgr();
+	if (!nss_ctx) {
+		nss_nl_info("%px: Couldn't get IPv4 ctx\n", nl_rule);
+		return -EPERM;
+	}
+
+	nss_nl_info("%px: IPv4 rule: src:%pI4h:%d dst:%pI4h:%d p:%d\n",
+		nl_rule, &nl_rule->num.msg.uncfg.src_ip.ip.ipv4, nl_rule->num.msg.uncfg.src_port,
+		&nl_rule->num.msg.uncfg.dest_ip.ip.ipv4, nl_rule->num.msg.uncfg.dest_port, IPPROTO_UDP);
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("%p:unable to save response data from NL buffer\n", nl_rule);
+		return -ENOMEM;
+	}
+
+	memset(&nim, 0, sizeof(struct nss_ipv4_msg));
+	nss_ipv4_msg_init(&nim,
+			NSS_IPV4_RX_INTERFACE,
+			NSS_IPV4_TX_DESTROY_RULE_MSG,
+			sizeof(struct nss_ipv4_rule_destroy_msg),
+			NULL,
+			NULL);
+
+	nirdm = &nim.msg.rule_destroy;
+
+	/*
+	 * Copy over the 5 tuple details.
+	 */
+	nirdm->tuple.protocol = (uint8_t)IPPROTO_UDP;
+	nirdm->tuple.flow_ip = nl_rule->num.msg.uncfg.src_ip.ip.ipv4;
+	nirdm->tuple.flow_ident = (uint32_t)nl_rule->num.msg.uncfg.src_port;
+	nirdm->tuple.return_ip = nl_rule->num.msg.uncfg.dest_ip.ip.ipv4;
+	nirdm->tuple.return_ident = (uint32_t)nl_rule->num.msg.uncfg.dest_port;
+
+	status = nss_ipv4_tx(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_info("%px: Destroy IPv4 message failed %d\n", nss_ctx, status);
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nludp_st_create_ipv4_rule()
+ *	Create a nss entry to accelerate the given IPv4 connection
+ */
+static int nss_nludp_st_create_ipv4_rule(struct sk_buff *skb, struct nss_nludp_st_rule *nl_rule)
+{
+	struct nss_ipv4_rule_create_msg *nircm;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_ipv4_msg nim;
+	struct net_device *net_dev;
+	struct nss_ipv4_nexthop *nexthop;
+	struct sk_buff *resp;
+	nss_tx_status_t status;
+
+	nss_ctx = nss_ipv4_get_mgr();
+	if (!nss_ctx) {
+		nss_nl_info("%px: Couldn't get IPv4 ctx\n", nl_rule);
+		return -EPERM;
+	}
+
+	nss_nl_info("%px: IPv4 rule: src:%pI4h:%d dst:%pI4h:%d p:%d\n",
+		nl_rule, &nl_rule->num.msg.cfg.src_ip.ip.ipv4, nl_rule->num.msg.cfg.src_port,
+		&nl_rule->num.msg.cfg.dest_ip.ip.ipv4, nl_rule->num.msg.cfg.dest_port, IPPROTO_UDP);
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("%p:unable to save response data from NL buffer\n", nl_rule);
+		return -ENOMEM;
+	}
+
+	memset(&nim, 0, sizeof(struct nss_ipv4_msg));
+	nss_ipv4_msg_init(&nim,
+			NSS_IPV4_RX_INTERFACE,
+			NSS_IPV4_TX_CREATE_RULE_MSG,
+			sizeof(struct nss_ipv4_rule_create_msg),
+			NULL,
+			NULL);
+
+	nircm = &nim.msg.rule_create;
+	nircm->valid_flags = 0;
+	nircm->rule_flags = 0;
+
+	/*
+	 * Copy over the 5 tuple details.
+	 */
+	nircm->tuple.protocol = (uint8_t)IPPROTO_UDP;
+	nircm->tuple.flow_ip = nl_rule->num.msg.cfg.src_ip.ip.ipv4;
+	nircm->conn_rule.flow_ip_xlate = nl_rule->num.msg.cfg.src_ip.ip.ipv4;
+	nircm->tuple.flow_ident = (uint32_t)nl_rule->num.msg.cfg.src_port;
+	nircm->conn_rule.flow_ident_xlate = (uint32_t)nl_rule->num.msg.cfg.src_port;
+	nircm->tuple.return_ip = nl_rule->num.msg.cfg.dest_ip.ip.ipv4;
+	nircm->conn_rule.return_ip_xlate = nl_rule->num.msg.cfg.dest_ip.ip.ipv4;
+	nircm->tuple.return_ident = (uint32_t)nl_rule->num.msg.cfg.dest_port;
+	nircm->conn_rule.return_ident_xlate = (uint32_t)nl_rule->num.msg.cfg.dest_port;
+
+	/*
+	 * extract netdevice
+	 */
+	net_dev = dev_get_by_name(&init_net, nl_rule->gmac_ifname);
+	if (!net_dev) {
+		nss_nl_error("%p: net device(%s) is not available\n", nl_rule, nl_rule->gmac_ifname);
+		return -EINVAL;
+	}
+
+	/*
+	 * Copy over the connection rules and set the CONN_VALID flag
+	 */
+	nircm->conn_rule.flow_interface_num = NSS_UDP_ST_INTERFACE;
+	memcpy(nircm->conn_rule.flow_mac, net_dev->dev_addr, 6);
+
+	/*
+	 * Set the MTU values of the flows.
+	 */
+	nircm->conn_rule.flow_mtu = NSS_NLUDP_ST_MAX_MTU;
+	nircm->conn_rule.return_mtu = net_dev->mtu;
+
+	/*
+	 * Special case: RAWIP, the destination address does not have MAC Addr.
+	 * So, set it to 0. Also append Core ID if the net device run in a different core.
+	 */
+	if (net_dev->type == ARPHRD_RAWIP) {
+#if !defined(NSS_NETLINK_UDP_ST_NO_RMNET_SUPPORT)
+		nircm->conn_rule.return_interface_num = nss_rmnet_rx_get_ifnum(net_dev);
+		memset(nircm->conn_rule.return_mac, 0, ETH_ALEN);
+#else
+		nss_nl_info("Error. no RAWIP support \n");
+		dev_put(net_dev);
+		return -EINVAL;
+#endif
+	} else {
+		nircm->conn_rule.return_interface_num = nss_cmn_get_interface_number_by_dev(net_dev);
+		if (nss_nludp_st_get_macaddr_ipv4(nircm->tuple.return_ip, (uint8_t *)&nircm->conn_rule.return_mac)) {
+			nss_nl_info("Error in Updating the Return MAC Address \n");
+			dev_put(net_dev);
+			return -EINVAL;
+		}
+	}
+
+	nircm->valid_flags |= NSS_IPV4_RULE_CREATE_CONN_VALID;
+
+	nexthop = &nircm->nexthop_rule;
+	nexthop->flow_nexthop = nircm->conn_rule.flow_interface_num;
+	nexthop->return_nexthop = nircm->conn_rule.return_interface_num;
+
+	nss_nl_info("flow_nexthop:%d return_nexthop:%d\n", nexthop->flow_nexthop, nexthop->return_nexthop);
+
+	status = nss_ipv4_tx(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_info("%px: Create IPv4 message failed %d\n", nss_ctx, status);
+	}
+
+	dev_put(net_dev);
+	return 0;
+}
+
+/*
+ * nss_nludp_st_destroy_ipv6_rule()
+ *	Destroy a nss entry to accelerate the given IPV6 connection
+ */
+static int nss_nludp_st_destroy_ipv6_rule(struct sk_buff *skb, struct nss_nludp_st_rule *nl_rule)
+{
+	struct nss_ipv6_rule_destroy_msg *nirdm;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_ipv6_msg nim;
+	struct sk_buff *resp;
+	nss_tx_status_t status;
+
+	nss_ctx = nss_ipv6_get_mgr();
+	if (!nss_ctx) {
+		nss_nl_info("%px: Couldn't get IPv6 ctx\n", nl_rule);
+		return -EPERM;
+	}
+
+	nss_nl_info("%px: IPv6 rule: src:%pI4h:%d dst:%pI4h:%d p:%d\n",
+		nl_rule, nl_rule->num.msg.uncfg.src_ip.ip.ipv6, nl_rule->num.msg.uncfg.src_port,
+		nl_rule->num.msg.uncfg.dest_ip.ip.ipv6, nl_rule->num.msg.uncfg.dest_port, IPPROTO_UDP);
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("%p:unable to save response data from NL buffer\n", nl_rule);
+		return -ENOMEM;
+	}
+
+	memset(&nim, 0, sizeof(struct nss_ipv6_msg));
+	nss_ipv6_msg_init(&nim,
+			NSS_IPV6_RX_INTERFACE,
+			NSS_IPV6_TX_DESTROY_RULE_MSG,
+			sizeof(struct nss_ipv6_rule_destroy_msg),
+			NULL,
+			NULL);
+
+	nirdm = &nim.msg.rule_destroy;
+
+	/*
+	 * Copy over the 5 tuple details.
+	 */
+	nirdm->tuple.protocol = (uint8_t)IPPROTO_UDP;
+	memcpy(nirdm->tuple.flow_ip, nl_rule->num.msg.uncfg.src_ip.ip.ipv6, sizeof(uint32_t) * 4);
+	nirdm->tuple.flow_ident = (uint32_t)nl_rule->num.msg.uncfg.src_port;
+	memcpy(nirdm->tuple.return_ip, nl_rule->num.msg.uncfg.dest_ip.ip.ipv6, sizeof(uint32_t) * 4);
+	nirdm->tuple.return_ident = (uint32_t)nl_rule->num.msg.uncfg.dest_port;
+
+	status = nss_ipv6_tx(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_info("%px: Destroy IPv6 message failed %d\n", nss_ctx, status);
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_nludp_st_create_ipv6_rule()
+ *	Create a nss entry to accelerate the given IPV6 connection
+ */
+static int nss_nludp_st_create_ipv6_rule(struct sk_buff *skb, struct nss_nludp_st_rule *nl_rule)
+{
+	struct nss_ipv6_rule_create_msg *nircm;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_ipv6_msg nim;
+	struct net_device *net_dev;
+	struct nss_ipv6_nexthop *nexthop;
+	struct sk_buff *resp;
+	nss_tx_status_t status;
+
+	nss_ctx = nss_ipv6_get_mgr();
+	if (!nss_ctx) {
+		nss_nl_info("%px: Couldn't get IPv6 ctx\n", nl_rule);
+		return -EPERM;
+	}
+
+	nss_nl_info("%px: Create IPv6 rule: %pI6:%d %pI6:%d p:%d\n",
+		nl_rule, nl_rule->num.msg.cfg.src_ip.ip.ipv6, nl_rule->num.msg.cfg.src_port,
+		nl_rule->num.msg.cfg.dest_ip.ip.ipv6, nl_rule->num.msg.cfg.dest_port, IPPROTO_UDP);
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("%p:unable to save response data from NL buffer\n", nl_rule);
+		return -ENOMEM;
+	}
+
+	memset(&nim, 0, sizeof(struct nss_ipv6_msg));
+	nss_ipv6_msg_init(&nim,
+			NSS_IPV6_RX_INTERFACE,
+			NSS_IPV6_TX_CREATE_RULE_MSG,
+			sizeof(struct nss_ipv6_rule_create_msg),
+			NULL,
+			NULL);
+
+	nircm = &nim.msg.rule_create;
+	nircm->rule_flags = 0;
+	nircm->valid_flags = 0;
+
+	/*
+	 * Copy over the 5 tuple information.
+	 */
+	nircm->tuple.protocol = (uint8_t)IPPROTO_UDP;
+	memcpy(nircm->tuple.flow_ip, nl_rule->num.msg.cfg.src_ip.ip.ipv6, sizeof(nircm->tuple.flow_ip));
+	memcpy(nircm->tuple.return_ip, nl_rule->num.msg.cfg.dest_ip.ip.ipv6, sizeof(nircm->tuple.return_ip));
+	nircm->tuple.flow_ident = (uint32_t)nl_rule->num.msg.cfg.src_port;
+	nircm->tuple.return_ident = (uint32_t)nl_rule->num.msg.cfg.dest_port;
+
+	/*
+	 * extract netdevice
+	 */
+	net_dev = dev_get_by_name(&init_net, nl_rule->gmac_ifname);
+	if (!net_dev) {
+		nss_nl_error("%p: net device(%s) is not available\n", nl_rule, nl_rule->gmac_ifname);
+		return -EINVAL;
+	}
+
+	/*
+	 * Copy over the connection rules and set CONN_VALID flag
+	 */
+	nircm->conn_rule.flow_interface_num = NSS_UDP_ST_INTERFACE;
+	memcpy(nircm->conn_rule.flow_mac, net_dev->dev_addr, 6);
+
+	/*
+	 * Special case: RAWIP, the destination address does not have MAC Addr.
+	 * So, set it to 0. Also append Core ID if the net device run in a different core.
+	 */
+	if (net_dev->type == ARPHRD_RAWIP) {
+#if !defined(NSS_NETLINK_UDP_ST_NO_RMNET_SUPPORT)
+		nircm->conn_rule.return_interface_num = nss_rmnet_rx_get_ifnum(net_dev);
+		memset(nircm->conn_rule.return_mac, 0, ETH_ALEN);
+#else
+		nss_nl_info("Error. no RAWIP support \n");
+		dev_put(net_dev);
+		return -EINVAL;
+#endif
+	} else {
+		nircm->conn_rule.return_interface_num = nss_cmn_get_interface_number_by_dev(net_dev);
+		if (nss_nludp_st_get_macaddr_ipv6(nircm->tuple.return_ip, (uint8_t *)&nircm->conn_rule.return_mac)) {
+			nss_nl_info("Error in Updating the Return MAC Address \n");
+			dev_put(net_dev);
+			return -EINVAL;
+		}
+	}
+
+	nircm->valid_flags |= NSS_IPV6_RULE_CREATE_CONN_VALID;
+
+	nexthop = &nircm->nexthop_rule;
+	nexthop->flow_nexthop = nircm->conn_rule.flow_interface_num;
+	nexthop->return_nexthop = nircm->conn_rule.return_interface_num;
+
+	nss_nl_info("flow_nexthop:%d return_nexthop:%d\n", nexthop->flow_nexthop, nexthop->return_nexthop);
+
+	status = nss_ipv6_tx(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_info("%px: Create IPv6 message failed %d\n", nss_ctx, status);
+		return -EPERM;
+	}
+
+	dev_put(net_dev);
+	return 0;
+}
+
+/*
+ * nss_nludp_st_uncfg_udp_st_rule()
+ *	Unconfigures the entry from udp_st
+ */
+static int nss_nludp_st_uncfg_udp_st_rule(struct sk_buff *skb, struct nss_udp_st_cfg *uncfg)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_udp_st_msg num;
+	struct sk_buff *resp;
+	nss_tx_status_t status;
+	int ret = 0;
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("unable to save response data from NL buffer\n");
+		return -ENOMEM;
+	}
+
+	nss_ctx = nss_udp_st_get_mgr();
+	if (!nss_ctx) {
+		nss_nl_info("Couldn't get udp_st ctx\n");
+		return -EPERM;
+	}
+
+	memset(&num, 0, sizeof(struct nss_udp_st_msg));
+	nss_udp_st_msg_init(&num, NSS_UDP_ST_INTERFACE,
+				NSS_UDP_ST_UNCFG_RULE_MSG,
+				sizeof(struct nss_udp_st_cfg),
+				nss_nludp_st_process_resp,
+				(void *)resp);
+
+	memcpy(&num.msg.uncfg, uncfg, sizeof(struct nss_udp_st_cfg));
+
+	status = nss_udp_st_tx_sync(nss_ctx, &num);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_info("%px: Create udp_st message failed %d\n", nss_ctx, status);
+		return -EBADMSG;
+	}
+
+	return ret;
+}
+
+/*
+ * nss_nludp_st_cfg_udp_st_rule()
+ *	Configures the entry from udp_st
+ */
+static int nss_nludp_st_cfg_udp_st_rule(struct sk_buff *skb, struct nss_udp_st_cfg *cfg)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_udp_st_msg num;
+	struct sk_buff *resp;
+	nss_tx_status_t status;
+	int ret = 0;
+
+	/*
+	 * copy the NL message for response
+	 */
+	resp = nss_nl_copy_msg(skb);
+	if (!resp) {
+		nss_nl_error("unable to save response data from NL buffer\n");
+		return -ENOMEM;
+	}
+
+	nss_ctx = nss_udp_st_get_mgr();
+	if (!nss_ctx) {
+		nss_nl_info("Couldn't get udp_st ctx\n");
+		return -EPERM;
+	}
+
+	memset(&num, 0, sizeof(struct nss_udp_st_msg));
+	nss_udp_st_msg_init(&num, NSS_UDP_ST_INTERFACE,
+				NSS_UDP_ST_CFG_RULE_MSG,
+				sizeof(struct nss_udp_st_cfg),
+				nss_nludp_st_process_resp,
+				(void *)resp);
+	memcpy(&num.msg.cfg, cfg, sizeof(struct nss_udp_st_cfg));
+
+	status = nss_udp_st_tx_sync(nss_ctx, &num);
+	if (status != NSS_TX_SUCCESS) {
+		nss_nl_info("%px: Create udp_st message failed %d\n", nss_ctx, status);
+		return -EBADMSG;
+	}
+
+	return ret;
+}
+
+/*
+ * nss_nludp_st_ops_uncfg_rule
+ *	Handler for unconfiguring rules
+ */
+static int nss_nludp_st_ops_uncfg_rule(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nludp_st_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	int ret = 0;
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nludp_st_family, info, NSS_UDP_ST_UNCFG_RULE_MSG);
+	if (!nl_cm) {
+		nss_nl_error("%px: Unable to extract unconfigure rule data\n", skb);
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nludp_st_rule, cm);
+
+	/*
+	 * Unconfigure udp_st only for the transmit node.
+	 * It is sent for received node to just get an ACK for this uncfg rule.
+	 */
+	ret = nss_nludp_st_uncfg_udp_st_rule(skb, &nl_rule->num.msg.uncfg);
+	if (ret < 0) {
+		nss_nl_info("%px: Unable to remove a rule entry for udp st\n", skb);
+		return -EBADMSG;
+	}
+
+	/*
+	 * Destroy rule based on ip version
+	 */
+	if (nl_rule->num.msg.uncfg.ip_version == NSS_UDP_ST_FLAG_IPV4) {
+		ret = nss_nludp_st_destroy_ipv4_rule(skb, nl_rule);
+	} else if (nl_rule->num.msg.uncfg.ip_version == NSS_UDP_ST_FLAG_IPV6) {
+		ret = nss_nludp_st_destroy_ipv6_rule(skb, nl_rule);
+	} else {
+		goto fail;
+	}
+
+	if (ret < 0) {
+		nss_nl_error("%px: Unable to delete a rule entry for ipv%d.\n", skb, nl_rule->num.msg.uncfg.ip_version);
+		goto fail;
+	}
+
+	return ret;
+fail:
+	/*
+	 * num.msg.cfg and num.msg.uncfg are of same type, struct nss_udp_st_cfg
+	 */
+	if (nl_rule->num.msg.uncfg.type == NSS_UDP_ST_TEST_TX) {
+		nss_nludp_st_cfg_udp_st_rule(skb, &nl_rule->num.msg.uncfg);
+	}
+	return -EAGAIN;
+}
+
+/*
+ * nss_nludp_st_ops_cfg_rule()
+ *	Handler for configuring rules
+ */
+static int nss_nludp_st_ops_cfg_rule(struct sk_buff *skb, struct genl_info *info)
+{
+	struct nss_nludp_st_rule *nl_rule;
+	struct nss_nlcmn *nl_cm;
+	int ret = 0;
+
+	/*
+	 * Extract the message payload
+	 */
+	nl_cm = nss_nl_get_msg(&nss_nludp_st_family, info, NSS_UDP_ST_CFG_RULE_MSG);
+	if (!nl_cm) {
+		nss_nl_error("%px: Unable to extract configure rule data\n", skb);
+		return -EINVAL;
+	}
+
+	/*
+	 * Message validation required before accepting the configuration
+	 */
+	nl_rule = container_of(nl_cm, struct nss_nludp_st_rule, cm);
+
+	/*
+	 * Configures udp_st only for the transmit node.
+	 * It is sent for received node to just get an ACK for this cfg rule.
+	 */
+	ret = nss_nludp_st_cfg_udp_st_rule(skb, &nl_rule->num.msg.cfg);
+	if (ret < 0) {
+		nss_nl_info("%px: Unable to add a rule entry for udp st\n", skb);
+		return -EBADMSG;
+	}
+
+	/*
+	 * Create rule based on ip version
+	 */
+	if (nl_rule->num.msg.cfg.ip_version == NSS_UDP_ST_FLAG_IPV4) {
+		ret = nss_nludp_st_create_ipv4_rule(skb, nl_rule);
+	} else if (nl_rule->num.msg.cfg.ip_version == NSS_UDP_ST_FLAG_IPV6) {
+		ret = nss_nludp_st_create_ipv6_rule(skb, nl_rule);
+	} else {
+		goto fail;
+	}
+
+	if (ret < 0) {
+		nss_nl_error("%px: Unable to add a rule entry for ipv%d.\n", skb, nl_rule->num.msg.cfg.ip_version);
+		goto fail;
+	}
+
+	return 0;
+fail:
+	/*
+	 * num.msg.cfg and num.msg.uncfg are of same type, struct nss_udp_st_cfg
+	 */
+	if (nl_rule->num.msg.cfg.type == NSS_UDP_ST_TEST_TX) {
+		nss_nludp_st_uncfg_udp_st_rule(skb, &nl_rule->num.msg.cfg);
+	}
+	return -EAGAIN;
+}
+
+/*
+ * nss_nludp_st_exit()
+ *	handler exit
+ */
+bool nss_nludp_st_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink udp_st handler\n");
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nludp_st_family);
+	if (error) {
+		nss_nl_info_always("unable to unregister udp_st NETLINK family\n");
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nludp_st_init()
+ *	handler init
+ */
+bool nss_nludp_st_init(void)
+{
+	int error;
+
+	nss_nl_info_always("Init NSS netlink udp_st handler\n");
+
+	/*
+	 * register Netlink ops with the family
+	 */
+	error = genl_register_family(&nss_nludp_st_family);
+	if (error) {
+		nss_nl_info_always("Error: unable to register udp_st family\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nludp_st.h b/qca-nss-clients/netlink/nss_nludp_st.h
new file mode 100755
index 0000000..b8e7fb2
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nludp_st.h
@@ -0,0 +1,37 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nludp_st.h
+ *      NSS Netlink udp_st API definitions
+ */
+#ifndef __NSS_NLUDP_ST_H
+#define __NSS_NLUDP_ST_H
+
+bool nss_nludp_st_init(void);
+bool nss_nludp_st_exit(void);
+
+#if defined(CONFIG_NSS_NLUDP_ST)
+#define NSS_NLUDP_ST_INIT nss_nludp_st_init
+#define NSS_NLUDP_ST_EXIT nss_nludp_st_exit
+#else
+#define NSS_NLUDP_ST_INIT 0
+#define NSS_NLUDP_ST_EXIT 0
+#endif /* !CONFIG_NSS_NLUDP_ST */
+
+#endif /* __NSS_NLUDP_ST_H */
diff --git a/qca-nss-clients/netlink/nss_nlwifili.c b/qca-nss-clients/netlink/nss_nlwifili.c
new file mode 100644
index 0000000..9c65bd9
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlwifili.c
@@ -0,0 +1,179 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlwifili.c
+ *	NSS Netlink wifili Handler
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/notifier.h>
+
+#include <net/genetlink.h>
+#include <net/sock.h>
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <nss_nl_if.h>
+#include "nss_nl.h"
+#include "nss_nlcmn_if.h"
+#include "nss_nlwifili_if.h"
+#include "nss_wifili_if.h"
+
+/*
+ * prototypes
+ */
+static int nss_nlwifili_ops_get_stats(struct sk_buff *skb, struct genl_info *info);
+static int nss_nlwifili_process_notify(struct notifier_block *nb, unsigned long val, void *data);
+
+/*
+ * multicast group for sending message status & events
+ */
+static const struct genl_multicast_group nss_nlwifili_mcgrp[] = {
+	{.name = NSS_NLWIFILI_MCAST_GRP},
+};
+
+/*
+ * operation table called by the generic netlink layer based on the command
+ */
+static struct genl_ops nss_nlwifili_ops[] = {
+	{.cmd = NSS_STATS_EVENT_NOTIFY, .doit = nss_nlwifili_ops_get_stats},
+};
+
+/*
+ * wifili family definition
+ */
+static struct genl_family nss_nlwifili_family = {
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 9, 0))
+	.id = GENL_ID_GENERATE,						/* Auto generate ID */
+#endif
+	.name = NSS_NLWIFILI_FAMILY,					/* family name string */
+	.hdrsize = sizeof(struct nss_wifili_stats_notification),	/* NSS NETLINK wifili stats */
+	.version = NSS_NL_VER,						/* Set it to NSS_NLWIFILI version */
+	.maxattr = NSS_STATS_EVENT_MAX,					/* maximum commands supported */
+	.netnsok = true,
+	.pre_doit = NULL,
+	.post_doit = NULL,
+	.ops = nss_nlwifili_ops,
+	.n_ops = ARRAY_SIZE(nss_nlwifili_ops),
+	.mcgrps = nss_nlwifili_mcgrp,
+	.n_mcgrps = ARRAY_SIZE(nss_nlwifili_mcgrp)
+};
+
+/*
+ * device call back handler for wifili from NSS
+ */
+static struct notifier_block nss_wifili_stats_notifier_nb = {
+	.notifier_call = nss_nlwifili_process_notify,
+};
+
+/*
+ * nss_nlwifili_ops_get_stats()
+ *	get stats handler
+ */
+static int nss_nlwifili_ops_get_stats(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+/*
+ * nss_nlwifili_process_notify()
+ *	process notification messages from NSS
+ */
+static int nss_nlwifili_process_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+	struct sk_buff *skb;
+	struct nss_wifili_stats_notification *nss_stats, *nl_stats;
+
+	nss_stats = (struct nss_wifili_stats_notification *)data;
+	skb = nss_nl_new_msg(&nss_nlwifili_family, NSS_NLCMN_SUBSYS_WIFILI);
+	if (!skb) {
+		nss_nl_error("unable to allocate NSS_NLWIFILI event\n");
+		return NOTIFY_DONE;
+	}
+
+	nl_stats = nss_nl_get_data(skb);
+	memcpy(nl_stats, nss_stats, sizeof(struct nss_wifili_stats_notification));
+	nss_nl_mcast_event(&nss_nlwifili_family, skb);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_nlwifili_init()
+ *	handler init
+ */
+bool nss_nlwifili_init(void)
+{
+	int error,ret;
+
+	nss_nl_info_always("Init NSS netlink wifili handler\n");
+
+	/*
+	 * register NETLINK ops with the family
+	 */
+	error = genl_register_family(&nss_nlwifili_family);
+	if (error) {
+		nss_nl_info_always("Error: unable to register wifili family\n");
+		return false;
+	}
+
+	/*
+	 * register device call back handler for wifili from NSS
+	 */
+	ret = nss_wifili_stats_register_notifier(&nss_wifili_stats_notifier_nb);
+	if (ret) {
+		nss_nl_info_always("Error: retreiving the NSS Context\n");
+		genl_unregister_family(&nss_nlwifili_family);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_nlwifili_exit()
+ *	handler exit
+ */
+bool nss_nlwifili_exit(void)
+{
+	int error;
+
+	nss_nl_info_always("Exit NSS netlink wifili handler\n");
+
+	/*
+	 * Unregister the device callback handler for wifili
+	 */
+	nss_wifili_stats_unregister_notifier(&nss_wifili_stats_notifier_nb);
+
+	/*
+	 * unregister the ops family
+	 */
+	error = genl_unregister_family(&nss_nlwifili_family);
+	if (error) {
+		nss_nl_info_always("unable to unregister wifili NETLINK family\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/netlink/nss_nlwifili.h b/qca-nss-clients/netlink/nss_nlwifili.h
new file mode 100644
index 0000000..5bb6a9f
--- /dev/null
+++ b/qca-nss-clients/netlink/nss_nlwifili.h
@@ -0,0 +1,37 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_nlwifili.h
+ *      NSS Netlink wifili API definitions
+ */
+#ifndef __NSS_NLWIFILI_H
+#define __NSS_NLWIFILI_H
+
+bool nss_nlwifili_init(void);
+bool nss_nlwifili_exit(void);
+
+#if defined(CONFIG_NSS_NLWIFILI)
+#define NSS_NLWIFILI_INIT nss_nlwifili_init
+#define NSS_NLWIFILI_EXIT nss_nlwifili_exit
+#else
+#define NSS_NLWIFILI_INIT 0
+#define NSS_NLWIFILI_EXIT 0
+#endif /* !CONFIG_NSS_NLWIFILI */
+
+#endif /* __NSS_NLWIFILI_H */
diff --git a/qca-nss-clients/nss_connmgr_tun6rd.c b/qca-nss-clients/nss_connmgr_tun6rd.c
new file mode 100644
index 0000000..ffa6ad4
--- /dev/null
+++ b/qca-nss-clients/nss_connmgr_tun6rd.c
@@ -0,0 +1,501 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, 2016-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_tun6rd.c
+ *
+ * This file is the NSS 6rd tunnel module
+ * ------------------------REVISION HISTORY-----------------------------
+ * Qualcomm Atheros         15/sep/2013              Created
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/of.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <net/ipv6.h>
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3,9,0))
+#include <net/ipip.h>
+#else
+#include <net/ip_tunnels.h>
+#endif
+#include <linux/if_arp.h>
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+
+/*
+ * NSS tun6rd debug macros
+ */
+#if (NSS_TUN6RD_DEBUG_LEVEL < 1)
+#define nss_tun6rd_assert(fmt, args...)
+#else
+#define nss_tun6rd_assert(c) if (!(c)) { BUG_ON(!(c)); }
+#endif
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_tun6rd_warning(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_tun6rd_info(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_tun6rd_trace(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_TUN6RD_DEBUG_LEVEL < 2)
+#define nss_tun6rd_warning(s, ...)
+#else
+#define nss_tun6rd_warning(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_TUN6RD_DEBUG_LEVEL < 3)
+#define nss_tun6rd_info(s, ...)
+#else
+#define nss_tun6rd_info(s, ...)   pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_TUN6RD_DEBUG_LEVEL < 4)
+#define nss_tun6rd_trace(s, ...)
+#else
+#define nss_tun6rd_trace(s, ...)  pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif
+
+/*
+ * 6rd tunnel stats
+ */
+struct nss_tun6rd_stats {
+	uint32_t rx_packets;	/* Number of received packets */
+	uint32_t rx_bytes;	/* Number of received bytes */
+	uint32_t tx_packets;	/* Number of transmitted packets */
+	uint32_t tx_bytes;	/* Number of transmitted bytes */
+};
+
+/*
+ * nss_tun6rd_update_dev_stats
+ *	Update the Dev stats received from NetAp
+ */
+static void nss_tun6rd_update_dev_stats(struct net_device *dev,
+					struct nss_tun6rd_sync_stats_msg *sync_stats)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+	struct pcpu_sw_netstats stats;
+
+	u64_stats_init(&stats.syncp);
+	u64_stats_update_begin(&stats.syncp);
+	stats.rx_packets = sync_stats->node_stats.rx_packets;
+	stats.rx_bytes = sync_stats->node_stats.rx_bytes;
+	stats.tx_packets = sync_stats->node_stats.tx_packets;
+	stats.tx_bytes = sync_stats->node_stats.tx_bytes;
+	u64_stats_update_end(&stats.syncp);
+#else
+	struct nss_tun6rd_stats stats;
+
+	stats.rx_packets = sync_stats->node_stats.rx_packets;
+	stats.rx_bytes = sync_stats->node_stats.rx_bytes;
+	stats.tx_packets = sync_stats->node_stats.tx_packets;
+	stats.tx_bytes = sync_stats->node_stats.tx_bytes;
+#endif
+
+	ipip6_update_offload_stats(dev, (void *)&stats);
+}
+
+/*
+ * nss_tun6rd_event_receive()
+ *	Event Callback to receive events from NSS
+ */
+static void nss_tun6rd_event_receive(void *if_ctx, struct nss_tun6rd_msg *tnlmsg)
+{
+	struct net_device *netdev = if_ctx;
+
+	switch (tnlmsg->cm.type) {
+	case NSS_TUN6RD_RX_STATS_SYNC:
+		nss_tun6rd_update_dev_stats(netdev, (struct nss_tun6rd_sync_stats_msg *)&tnlmsg->msg.stats);
+		break;
+
+	default:
+		nss_tun6rd_info("Unknown Event from NSS\n");
+		break;
+	}
+}
+
+/*
+ * nss_tun6rd_exception()
+ *	Exception handler registered to NSS driver
+ */
+static void nss_tun6rd_exception(struct net_device *dev, struct sk_buff *skb, __attribute__((unused)) struct napi_struct *napi)
+{
+	const struct iphdr *iph;
+
+	skb->dev = dev;
+	nss_tun6rd_info("received - %d bytes name %s ver %x\n",
+			skb->len,dev->name,skb->data[0]);
+
+	iph = (const struct iphdr *)skb->data;
+
+	/*
+	 * Packet after Decap/Encap Did not find the Rule.
+	 */
+	if (iph->version != 4) {
+		skb->protocol = htons(ETH_P_IPV6);
+	} else {
+		if (iph->protocol == IPPROTO_IPV6) {
+			skb_pull(skb, sizeof(struct iphdr));
+			skb->protocol = htons(ETH_P_IPV6);
+			skb_reset_network_header(skb);
+			skb->pkt_type = PACKET_HOST;
+			skb->ip_summed = CHECKSUM_NONE;
+			dev_queue_xmit(skb);
+			return;
+		}
+		skb->protocol = htons(ETH_P_IP);
+	}
+
+	skb_reset_network_header(skb);
+	skb->pkt_type = PACKET_HOST;
+	skb->skb_iif = dev->ifindex;
+	skb->ip_summed = CHECKSUM_NONE;
+	netif_receive_skb(skb);
+}
+
+/*
+ * nss_tun6rd_dev_up()
+ *	6RD Tunnel device i/f up handler
+ */
+static int nss_tun6rd_dev_up(struct net_device *netdev)
+{
+	struct ip_tunnel *tunnel;
+	struct ip_tunnel_6rd_parm *ip6rd;
+	const struct iphdr  *tiph;
+	struct nss_tun6rd_msg msg_tunnel;
+	struct nss_tun6rd_attach_tunnel_msg *cfg_tunnel;
+	int32_t outer_if;
+	int32_t inner_if;
+	nss_tx_status_t status;
+	struct nss_ctx_instance *nss_ctx;
+	uint32_t features = 0; /* features denote the skb types supported by this interface */
+
+	/*
+	 * Validate netdev for ipv6-in-ipv4  Tunnel
+	 */
+	if (netdev->type != ARPHRD_SIT) {
+		return NOTIFY_DONE;
+	}
+
+	tunnel = (struct ip_tunnel *)netdev_priv(netdev);
+	ip6rd =  &tunnel->ip6rd;
+
+	/*
+	 * Valid 6rd Tunnel Check
+	 * 1. 6rd Prefix len should be non zero
+	 * 2. Relay prefix length should not be greater then 32
+	 * 3. To allow for stateless address auto-configuration on the CE LAN side,
+	 *    6rd delegated prefix SHOULD be /64 or shorter.
+	 */
+	if ((ip6rd->prefixlen == 0 )
+			|| (ip6rd->relay_prefixlen > 32)
+			|| (ip6rd->prefixlen
+				+ (32 - ip6rd->relay_prefixlen) > 64)) {
+
+		nss_tun6rd_warning("%px: Invalid 6rd argument prefix len %d relayprefix len %d\n",
+				netdev, ip6rd->prefixlen, ip6rd->relay_prefixlen);
+		return NOTIFY_DONE;
+	}
+
+	nss_tun6rd_info("%px: Valid 6rd Tunnel Prefix %x %x %x %x\n Prefix len %d relay_prefix %d relay_prefixlen %d\n",
+			netdev,
+			ip6rd->prefix.s6_addr32[0],ip6rd->prefix.s6_addr32[1],
+			ip6rd->prefix.s6_addr32[2],ip6rd->prefix.s6_addr32[3],
+			ip6rd->prefixlen, ip6rd->relay_prefix,
+			ip6rd->relay_prefixlen);
+
+	/*
+	 * Find the Tunnel device IP header info
+	 */
+	tiph = &tunnel->parms.iph ;
+	nss_tun6rd_trace("%px: Tunnel Param srcaddr %x daddr %x ttl %d tos %x\n",
+			netdev, tiph->saddr, tiph->daddr, tiph->ttl, tiph->tos);
+
+	if (tiph->saddr == 0) {
+		nss_tun6rd_warning("%px: Tunnel src address not configured %x\n",
+				netdev, tiph->saddr);
+		return NOTIFY_DONE;
+	}
+
+	outer_if = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_OUTER);
+	if (-1 == outer_if) {
+		nss_tun6rd_warning("%px: Request outer interface number failed\n", netdev);
+		goto outer_fail;
+	}
+
+	if (!nss_is_dynamic_interface(outer_if)) {
+		nss_tun6rd_warning("%px: Invalid NSS dynamic I/F number %d\n", netdev, outer_if);
+		goto outer_fail;
+	}
+
+	inner_if = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_INNER);
+	if (-1 == inner_if) {
+		nss_tun6rd_warning("%px: Request inner interface number failed\n", netdev);
+		goto inner_fail;
+	}
+
+	if (!nss_is_dynamic_interface(inner_if)) {
+		nss_tun6rd_warning("%px: Invalid NSS dynamic I/F number %d\n", netdev, inner_if);
+		goto inner_fail;
+	}
+
+	/*
+	 * Register 6rd tunnel's inner interface with NSS
+	 */
+	nss_ctx = nss_register_tun6rd_if(inner_if,
+				NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_INNER,
+				nss_tun6rd_exception,
+				nss_tun6rd_event_receive,
+				netdev,
+				features);
+	if (!nss_ctx) {
+		nss_tun6rd_trace("%px: nss_register_tun6rd_if failed for inner interface\n", netdev);
+		goto register_inner_if_fail;
+	}
+
+	/*
+	 * Register 6rd tunnel's outer interface with NSS
+	 */
+	nss_ctx = nss_register_tun6rd_if(outer_if,
+				NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_OUTER,
+				nss_tun6rd_exception,
+				nss_tun6rd_event_receive,
+				netdev,
+				features);
+	if (!nss_ctx) {
+		nss_tun6rd_trace("%px: nss_register_tun6rd_if failed for outer interface\n", netdev);
+		goto register_outer_if_fail;
+	}
+
+	/*
+	 * Prepare The Tunnel configuration parameter to send to nss
+	 */
+	memset(&msg_tunnel, 0, sizeof(struct nss_tun6rd_msg));
+	cfg_tunnel = &msg_tunnel.msg.tunnel;
+	cfg_tunnel->saddr = ntohl(tiph->saddr);
+	cfg_tunnel->daddr = ntohl(tiph->daddr);
+	cfg_tunnel->ttl = tiph->ttl;
+	cfg_tunnel->tos = tiph->tos;
+	cfg_tunnel->sibling_if_num = outer_if;
+
+	nss_tun6rd_trace("%px: Sending 6rd tunnel i/f up command to NSS %px\n",
+			netdev, nss_ctx);
+
+	/*
+	 * Send 6rd Tunnel UP command to NSS
+	 */
+	nss_tun6rd_msg_init(&msg_tunnel, inner_if, NSS_TUN6RD_ATTACH_PNODE,
+			sizeof(struct nss_tun6rd_attach_tunnel_msg), NULL, NULL);
+
+	status = nss_tun6rd_tx(nss_ctx, &msg_tunnel);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tun6rd_warning("%px: Tunnel up command error %d\n", netdev, status);
+		goto tunnel_up_fail;
+	}
+
+	return NOTIFY_OK;
+
+tunnel_up_fail:
+	nss_unregister_tun6rd_if(outer_if);
+
+register_outer_if_fail:
+	nss_unregister_tun6rd_if(inner_if);
+
+register_inner_if_fail:
+	status = nss_dynamic_interface_dealloc_node(inner_if, NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_INNER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tun6rd_warning("%px: Unable to dealloc the node[%d] in the NSS fw!\n", netdev, inner_if);
+	}
+
+inner_fail:
+	status = nss_dynamic_interface_dealloc_node(outer_if, NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_OUTER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tun6rd_warning("%px: Unable to dealloc the node[%d] in the NSS fw!\n", netdev, outer_if);
+	}
+
+outer_fail:
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_tun6rd_dev_down()
+ *	6RD Tunnel device i/f down handler
+ */
+static int nss_tun6rd_dev_down(struct net_device *netdev)
+{
+	struct ip_tunnel *tunnel;
+	struct ip_tunnel_6rd_parm *ip6rd;
+	int32_t outer_if;
+	int32_t inner_if;
+	nss_tx_status_t status;
+
+	/*
+	 * Validate netdev for ipv6-in-ipv4  Tunnel
+	 */
+	if (netdev->type != ARPHRD_SIT) {
+		return NOTIFY_DONE;
+	}
+
+	tunnel = (struct ip_tunnel *)netdev_priv(netdev);
+	ip6rd =  &tunnel->ip6rd;
+
+	/*
+	 * Valid 6rd Tunnel Check
+	 */
+	if ((ip6rd->prefixlen == 0 )
+			|| (ip6rd->relay_prefixlen > 32 )
+			|| (ip6rd->prefixlen
+				+ (32 - ip6rd->relay_prefixlen) > 64)) {
+
+		nss_tun6rd_warning("%px: Invalid 6rd argument prefix len %d relayprefix len %d\n",
+				netdev, ip6rd->prefixlen, ip6rd->relay_prefixlen);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Check if tunnel 6rd outer is registered ?
+	 */
+	outer_if = nss_cmn_get_interface_number_by_dev_and_type(netdev, NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_OUTER);
+	if (outer_if < 0) {
+		nss_tun6rd_warning("%px: Net device is not registered\n", netdev);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Un-Register 6rd tunnel's outer interface with NSS
+	 */
+	nss_unregister_tun6rd_if(outer_if);
+	status = nss_dynamic_interface_dealloc_node(outer_if, NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_OUTER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tun6rd_warning("%px: Dealloc outer interface failed\n", netdev);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Check if tunnel 6rd inner is registered ?
+	 */
+	inner_if = nss_cmn_get_interface_number_by_dev_and_type(netdev, NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_INNER);
+	if (inner_if < 0) {
+		nss_tun6rd_warning("%px: Net device is not registered\n", netdev);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Un-Register 6rd tunnel's inner interface with NSS
+	 */
+	nss_unregister_tun6rd_if(inner_if);
+	status = nss_dynamic_interface_dealloc_node(inner_if, NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_INNER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tun6rd_warning("%px: Dealloc inner interface failed\n", netdev);
+		return NOTIFY_DONE;
+	}
+
+	return NOTIFY_OK;
+}
+
+/*
+ * nss_tun6rd_dev_event()
+ *	Net device notifier for 6rd module
+ */
+static int nss_tun6rd_dev_event(struct notifier_block  *nb,
+		unsigned long event, void  *dev)
+{
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3,10,0))
+	struct net_device *netdev = (struct net_device *)dev;
+#else
+	struct net_device *netdev = netdev_notifier_info_to_dev(dev);
+#endif
+
+	switch (event) {
+	case NETDEV_UP:
+		nss_tun6rd_trace("NETDEV_UP: event %lu name %s\n", event, netdev->name);
+		return nss_tun6rd_dev_up(netdev);
+
+	case NETDEV_DOWN:
+		nss_tun6rd_trace("NETDEV_DOWN: event %lu name %s\n", event, netdev->name);
+		return nss_tun6rd_dev_down(netdev);
+
+	default:
+		nss_tun6rd_trace("Unhandled notifier event %lu name %s\n",event, netdev->name);
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * Linux Net device Notifier
+ */
+struct notifier_block nss_tun6rd_notifier = {
+	.notifier_call = nss_tun6rd_dev_event,
+};
+
+/*
+ * nss_tun6rd_init_module()
+ *	Tunnel 6rd module init function
+ */
+int __init nss_tun6rd_init_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+	nss_tun6rd_info("module (platform - IPQ806x , %s) loaded\n",
+			NSS_CLIENT_BUILD_ID);
+
+	register_netdevice_notifier(&nss_tun6rd_notifier);
+	nss_tun6rd_trace("Netdev Notifier registered\n");
+
+	return 0;
+}
+
+/*
+ * nss_tun6rd_exit_module()
+ *	Tunnel 6rd module exit function
+ */
+void __exit nss_tun6rd_exit_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return;
+	}
+#endif
+	unregister_netdevice_notifier(&nss_tun6rd_notifier);
+	nss_tun6rd_info("module unloaded\n");
+}
+
+module_init(nss_tun6rd_init_module);
+module_exit(nss_tun6rd_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS tun6rd offload manager");
diff --git a/qca-nss-clients/nss_qdisc/Makefile b/qca-nss-clients/nss_qdisc/Makefile
new file mode 100644
index 0000000..c3895b5
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/Makefile
@@ -0,0 +1,28 @@
+ccflags-y := -I$(obj)/../exports -I$(srctree)/net/bridge -DNSS_QDISC_DEBUG_LEVEL=2
+
+# If NSS_QDISC_PPE_SUPPORT is removed, then remove/disable
+# nss_ppe.o nss_ppe_mc.o from qca-nss-qdisc-objs list.
+ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64 ipq60xx ipq60xx_64))
+ccflags-y += -DNSS_QDISC_PPE_SUPPORT -DNSS_QDISC_BRIDGE_SUPPORT
+endif
+
+ccflags-y += -Wall -Werror
+
+obj-m += qca-nss-qdisc.o
+qca-nss-qdisc-objs := 	nss_qdisc.o \
+			nss_fifo.o \
+			nss_codel.o \
+			nss_tbl.o \
+			nss_prio.o \
+			nss_bf.o \
+			nss_wrr.o \
+			nss_htb.o \
+			nss_blackhole.o \
+			nss_wred.o
+
+ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64 ipq60xx ipq60xx_64))
+qca-nss-qdisc-objs += 	nss_ppe.o \
+			nss_ppe_mc.o
+endif
+
+obj-$(igs)+= igs/
diff --git a/qca-nss-clients/nss_qdisc/igs/Makefile b/qca-nss-clients/nss_qdisc/igs/Makefile
new file mode 100644
index 0000000..19f6972
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/igs/Makefile
@@ -0,0 +1,10 @@
+# Makefile for IGS (Ingress Shaping)
+
+ccflags-y += $(NSS_CCFLAGS) -I$(obj)/../../exports
+ccflags-y += -DNSS_IGS_DEBUG_LEVEL=2
+ccflags-y += -Wall -Werror
+
+obj-m += act_nssmirred.o
+act_nssmirred-objs := \
+		      nss_mirred.o \
+		      nss_ifb.o
diff --git a/qca-nss-clients/nss_qdisc/igs/nss_ifb.c b/qca-nss-clients/nss_qdisc/igs/nss_ifb.c
new file mode 100644
index 0000000..7e20f23
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/igs/nss_ifb.c
@@ -0,0 +1,621 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <net/netfilter/nf_conntrack_dscpremark_ext.h>
+#include "nss_mirred.h"
+#include "nss_igs.h"
+#include "nss_ifb.h"
+
+/*
+ * TODO: Current implementation only supports one IFB interface to be mapped with
+ * any one interface at a time. This has to be changed to support the mapping of
+ * an IFB device to multiple interfaces.
+ */
+static LIST_HEAD(nss_ifb_list);			/* List of IFB and its mapped interface */
+static DEFINE_SPINLOCK(nss_ifb_list_lock);	/* Lock for the ifb list */
+
+/*
+ * nss_ifb_msg_response
+ *	NSS firmware message response structure.
+ */
+static struct nss_ifb_msg_response {
+	struct semaphore sem;
+	wait_queue_head_t wq;
+	enum nss_cmn_response response;
+	bool cond;
+} msg_response;
+
+/*
+ * nss_ifb_igs_ip_pre_routing_hook()
+ *	Copy class-id to Linux CT structure.
+ *
+ * Copy class-id from tc_index field of skb in ingress QoS fields inside
+ * DSCP CT extention structure.
+ */
+unsigned int nss_ifb_igs_ip_pre_routing_hook(void *priv, struct sk_buff *skb,
+		 const struct nf_hook_state *state)
+{
+	struct nf_conn *ct;
+	struct nf_ct_dscpremark_ext *dscpcte;
+	enum ip_conntrack_info ctinfo;
+
+	if (unlikely(!skb))
+		return NF_ACCEPT;
+
+	/*
+	 * Return if ingress qostag value (saved in tc_index field) is 0.
+	 */
+	if (likely(!skb->tc_index))
+		return NF_ACCEPT;
+
+	ct = nf_ct_get(skb, &ctinfo);
+	if (!ct)
+		return NF_ACCEPT;
+
+	spin_lock_bh(&ct->lock);
+	dscpcte = nf_ct_dscpremark_ext_find(ct);
+	if (!dscpcte) {
+		spin_unlock_bh(&ct->lock);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Copy ingress qostag value (saved in tc_index) to ingress
+	 * qostag fields of DSCP CT extension structure.
+	 */
+	if (IP_CT_DIR_ORIGINAL == CTINFO2DIR(ctinfo)) {
+		dscpcte->igs_flow_qos_tag = skb->tc_index;
+	} else {
+		dscpcte->igs_reply_qos_tag = skb->tc_index;
+	}
+	spin_unlock_bh(&ct->lock);
+
+	/*
+	 * Reset the tc_index field as it no longer required.
+	 */
+	skb->tc_index = 0;
+	return NF_ACCEPT;
+}
+
+/*
+ * nss_ifb_list_del()
+ *	API to delete member in ifb list.
+ */
+void nss_ifb_list_del(struct nss_ifb_info *ifb_info)
+{
+	spin_lock_bh(&nss_ifb_list_lock);
+	list_del(&ifb_info->map_list);
+	spin_unlock_bh(&nss_ifb_list_lock);
+}
+
+/*
+ * nss_ifb_list_add()
+ *	API to add member in ifb list.
+ */
+static void nss_ifb_list_add(struct nss_ifb_info *ifb_info)
+{
+	spin_lock_bh(&nss_ifb_list_lock);
+	list_add(&(ifb_info->map_list), &nss_ifb_list);
+	spin_unlock_bh(&nss_ifb_list_lock);
+}
+
+/*
+ * nss_ifb_is_mapped()
+ *	Returns the map status of the given ifb bind structure.
+ */
+bool nss_ifb_is_mapped(struct nss_ifb_info *ifb_info)
+{
+	bool is_mapped;
+
+	spin_lock_bh(&nss_ifb_list_lock);
+	is_mapped = ifb_info->is_mapped;
+	spin_unlock_bh(&nss_ifb_list_lock);
+	return is_mapped;
+}
+
+/*
+ * nss_ifb_config_msg_init()
+ *	Initialize IFB configure interface's message.
+ */
+static void nss_ifb_config_msg_init(struct nss_if_msg *ncm, uint16_t if_num,
+		 uint32_t type,  uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+
+/*
+ * nss_ifb_clear_config_cb()
+ *	CLEAR configure handler for an IFB mapped interface.
+ */
+static void nss_ifb_clear_config_cb(void *app_data, struct nss_if_msg *nim)
+{
+	struct nss_ifb_info *ifb_info = (struct nss_ifb_info *)app_data;
+	bool ret;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_igs_error("Response error: %d\n", nim->cm.response);
+		return;
+	}
+
+	do {
+		ret = spin_trylock_bh(&nss_ifb_list_lock);
+	} while (!ret);
+	ifb_info->is_mapped = false;
+	spin_unlock_bh(&nss_ifb_list_lock);
+}
+
+/*
+ * nss_ifb_async_cb()
+ *	IFB asynchronous handler for an IFB mapped interface.
+ */
+static void nss_ifb_async_cb(void *app_data, struct nss_if_msg *nim)
+{
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_igs_error("Response error: %d\n", nim->cm.response);
+	}
+}
+
+/*
+ * nss_ifb_wake_up_cb()
+ *	IFB wake up handler for an IFB mapped interface.
+ */
+static void nss_ifb_wake_up_cb(void *app_data, struct nss_if_msg *nim)
+{
+	msg_response.response = nim->cm.response;
+	msg_response.cond = 0;
+	wake_up(&msg_response.wq);
+}
+
+/*
+ * nss_ifb_config_msg_fill()
+ *	Fill the IFB configure message.
+ */
+static bool nss_ifb_config_msg_fill(struct nss_if_msg *nim_ptr, struct net_device *dev,
+		int32_t ifb_num, enum nss_ifb_if_config config, void *cb)
+{
+	uint32_t if_src_num;
+
+	if (netif_is_ifb_dev(dev)) {
+		if_src_num = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_IGS);
+		if (if_src_num < 0) {
+			nss_igs_error("invalid IFB device %s\n", dev->name);
+			return -1;
+		}
+	} else {
+		if_src_num = nss_cmn_get_interface_number_by_dev(dev);
+		if (if_src_num < 0) {
+			nss_igs_error("invalid device %s\n", dev->name);
+			return -1;
+		}
+	}
+
+	switch (config) {
+	case NSS_IFB_SET_IGS_NODE:
+		nss_ifb_config_msg_init(nim_ptr, if_src_num, NSS_IF_SET_IGS_NODE,
+			sizeof(struct nss_if_igs_config), nss_ifb_wake_up_cb, cb);
+		nim_ptr->msg.config_igs.igs_num = ifb_num;
+		break;
+	case NSS_IFB_CLEAR_IGS_NODE:
+		nss_ifb_config_msg_init(nim_ptr, if_src_num, NSS_IF_CLEAR_IGS_NODE,
+			sizeof(struct nss_if_igs_config), nss_ifb_clear_config_cb, cb);
+		nim_ptr->msg.config_igs.igs_num = ifb_num;
+		break;
+	case NSS_IFB_SET_NEXTHOP:
+		nss_ifb_config_msg_init(nim_ptr, if_src_num, NSS_IF_SET_NEXTHOP,
+			sizeof(struct nss_if_set_nexthop), nss_ifb_wake_up_cb, cb);
+		nim_ptr->msg.set_nexthop.nexthop = ifb_num;
+		break;
+	case NSS_IFB_RESET_NEXTHOP:
+		nss_ifb_config_msg_init(nim_ptr, if_src_num, NSS_IF_RESET_NEXTHOP,
+			sizeof(struct nss_if_set_nexthop), nss_ifb_async_cb, cb);
+		nim_ptr->msg.set_nexthop.nexthop = ifb_num;
+		break;
+	case NSS_IFB_OPEN:
+		nss_ifb_config_msg_init(nim_ptr, if_src_num, NSS_IF_OPEN,
+			sizeof(struct nss_if_open), nss_ifb_async_cb, cb);
+		/*
+		 * Reset the elements of interface's open configuration.
+		 */
+		memset (&nim_ptr->msg.open, 0, sizeof(struct nss_if_open));
+		break;
+	case NSS_IFB_CLOSE:
+		nss_ifb_config_msg_init(nim_ptr, if_src_num, NSS_IF_CLOSE,
+			sizeof(struct nss_if_close), nss_ifb_async_cb, cb);
+		/*
+		 * Reset the elements of interface's close configuration.
+		 */
+		memset (&nim_ptr->msg.close, 0, sizeof(struct nss_if_close));
+		break;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ifb_config_msg_tx()
+ *	Send IFB configure message to an IFB mapped interface.
+ */
+int32_t nss_ifb_config_msg_tx(struct net_device *dev, int32_t ifb_num,
+		 enum nss_ifb_if_config config, void *cb)
+{
+	struct nss_if_msg nim;
+	int32_t ret;
+
+	if ((ret = nss_ifb_config_msg_fill(&nim, dev, ifb_num, config, cb))) {
+		nss_igs_error("Error in setting up IFB %d config message\n", config);
+		return -1;
+	}
+
+	ret = nss_if_tx_msg(nss_igs_get_context(), &nim);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_igs_error("failed to send config message\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ifb_config_msg_tx_sync()
+ *	Send IFB configure message to an IFB mapped interface and wait for the response.
+ */
+int32_t nss_ifb_config_msg_tx_sync(struct net_device *dev, int32_t ifb_num,
+		 enum nss_ifb_if_config config, void *cb)
+{
+	struct nss_if_msg nim;
+	int32_t ret;
+
+	if ((ret = nss_ifb_config_msg_fill(&nim, dev, ifb_num, config, cb))) {
+		nss_igs_error("Error in setting up IFB %d config message\n", config);
+		return -1;
+	}
+
+	down(&msg_response.sem);
+	ret = nss_if_tx_msg(nss_igs_get_context(), &nim);
+	if (ret != NSS_TX_SUCCESS) {
+		up(&msg_response.sem);
+		nss_igs_error("failed to send config message\n");
+		return -1;
+	}
+
+	msg_response.cond = 1;
+	if (!wait_event_timeout(msg_response.wq, msg_response.cond == 0, NSS_IFB_MSG_TIMEOUT)) {
+		nss_igs_error("config for attach interface msg timeout\n");
+		up(&msg_response.sem);
+		return -1;
+	} else if (msg_response.response != NSS_CMN_RESPONSE_ACK) {
+		up(&msg_response.sem);
+		nss_igs_error("config for attach interface msg return with response: %d\n", msg_response.response);
+		return -1;
+	}
+
+	up(&msg_response.sem);
+	return 0;
+}
+
+/*
+ * nss_ifb_reset_nexthop()
+ *	Send RESET NEXTHOP configure message to an IFB mapped interface.
+ */
+bool nss_ifb_reset_nexthop(struct nss_ifb_info *ifb_info)
+{
+	int32_t if_num;
+
+	spin_lock_bh(&nss_ifb_list_lock);
+	if (!(ifb_info->is_mapped)) {
+		nss_igs_info("%s IFB device mapped flag is not set\n", ifb_info->ifb_dev->name);
+		spin_unlock_bh(&nss_ifb_list_lock);
+		return true;
+	}
+
+	/*
+	 * Send RESET NEXTHOP config message to the mapped interface.
+	 */
+	if_num = nss_cmn_get_interface_number_by_dev_and_type(ifb_info->ifb_dev, NSS_DYNAMIC_INTERFACE_TYPE_IGS);
+	if (if_num < 0) {
+		nss_igs_error("No %s IFB device found in NSS firmware\n", ifb_info->ifb_dev->name);
+	}
+
+	if (nss_ifb_config_msg_tx(ifb_info->map_dev, if_num, NSS_IFB_RESET_NEXTHOP, NULL) < 0) {
+		nss_igs_error("Sending RESET NEXTHOP config to %s dev failed\n", ifb_info->map_dev->name);
+		spin_unlock_bh(&nss_ifb_list_lock);
+		return false;
+	}
+	spin_unlock_bh(&nss_ifb_list_lock);
+	return true;
+}
+
+/*
+ * nss_ifb_down()
+ *	Send interface's DOWN configure message to an IFB interface.
+ */
+bool nss_ifb_down(struct nss_ifb_info *ifb_info)
+{
+	int32_t ifb_num;
+
+	spin_lock_bh(&nss_ifb_list_lock);
+	if (!(ifb_info->is_mapped)) {
+		nss_igs_info("%s IFB device mapped flag is not set\n", ifb_info->ifb_dev->name);
+		spin_unlock_bh(&nss_ifb_list_lock);
+		return true;
+	}
+
+	/*
+	 * Send interface's DOWN config message to an IFB interface.
+	 */
+	ifb_num = nss_cmn_get_interface_number_by_dev_and_type(ifb_info->ifb_dev, NSS_DYNAMIC_INTERFACE_TYPE_IGS);
+	if (ifb_num < 0) {
+		nss_igs_error("No %s IFB device found in NSS FW\n", ifb_info->ifb_dev->name);
+		spin_unlock_bh(&nss_ifb_list_lock);
+		return false;
+	}
+
+	if (nss_ifb_config_msg_tx(ifb_info->ifb_dev, ifb_num, NSS_IFB_CLOSE, ifb_info) < 0) {
+		nss_igs_error("Sending unassign to %s dev failed\n", ifb_info->map_dev->name);
+		spin_unlock_bh(&nss_ifb_list_lock);
+		return false;
+	}
+	spin_unlock_bh(&nss_ifb_list_lock);
+	return true;
+}
+
+/*
+ * nss_ifb_up()
+ *	Send interface's UP configure message to an IFB interface.
+ */
+bool nss_ifb_up(struct nss_ifb_info *ifb_info)
+{
+	int32_t ifb_num;
+
+	spin_lock_bh(&nss_ifb_list_lock);
+	if (!(ifb_info->is_mapped)) {
+		nss_igs_info("%s IFB device mapped flag is not set\n", ifb_info->ifb_dev->name);
+		spin_unlock_bh(&nss_ifb_list_lock);
+		return true;
+	}
+
+	/*
+	 * Send interface's UP config message to an IFB interface.
+	 */
+	ifb_num = nss_cmn_get_interface_number_by_dev_and_type(ifb_info->ifb_dev, NSS_DYNAMIC_INTERFACE_TYPE_IGS);
+	if (ifb_num < 0) {
+		nss_igs_error("No %s IFB device found in NSS FW\n", ifb_info->ifb_dev->name);
+		spin_unlock_bh(&nss_ifb_list_lock);
+		return false;
+	}
+
+	if (nss_ifb_config_msg_tx(ifb_info->ifb_dev, ifb_num, NSS_IFB_OPEN, ifb_info) < 0) {
+		nss_igs_error("Sending unassign to %s dev failed\n", ifb_info->map_dev->name);
+		spin_unlock_bh(&nss_ifb_list_lock);
+		return false;
+	}
+	spin_unlock_bh(&nss_ifb_list_lock);
+	return true;
+}
+
+/*
+ * nss_ifb_clear_igs_node()
+ *	Send CLEAR configure message to an IFB mapped interface.
+ */
+bool nss_ifb_clear_igs_node(struct nss_ifb_info *ifb_info)
+{
+	int32_t if_num;
+
+	spin_lock_bh(&nss_ifb_list_lock);
+	if (!(ifb_info->is_mapped)) {
+		nss_igs_info("%s IFB device mapped flag is not set\n", ifb_info->ifb_dev->name);
+		spin_unlock_bh(&nss_ifb_list_lock);
+		return true;
+	}
+
+	/*
+	 * Send CLEAR config message to the mapped interface.
+	 */
+	if_num = nss_cmn_get_interface_number_by_dev_and_type(ifb_info->ifb_dev, NSS_DYNAMIC_INTERFACE_TYPE_IGS);
+	if (if_num < 0) {
+		nss_igs_error("No %s IFB device found in NSS firmware\n", ifb_info->ifb_dev->name);
+	}
+
+	if (nss_ifb_config_msg_tx(ifb_info->map_dev, if_num, NSS_IFB_CLEAR_IGS_NODE, ifb_info) < 0) {
+		nss_igs_error("Sending unassign to %s dev failed\n", ifb_info->map_dev->name);
+		spin_unlock_bh(&nss_ifb_list_lock);
+		return false;
+	}
+	spin_unlock_bh(&nss_ifb_list_lock);
+	return true;
+}
+
+/*
+ * nss_ifb_init()
+ *	Initialization API.
+ */
+void nss_ifb_init()
+{
+	sema_init(&msg_response.sem, 1);
+	init_waitqueue_head(&msg_response.wq);
+}
+
+/*
+ * nss_ifb_find_map_dev()
+ *	Find and return the IFB mapped netdev in the ifb list.
+ */
+struct nss_ifb_info *nss_ifb_find_map_dev(struct net_device *dev)
+{
+	struct nss_ifb_info *ifb_info;
+
+	spin_lock_bh(&nss_ifb_list_lock);
+	list_for_each_entry(ifb_info, &nss_ifb_list, map_list) {
+		if (ifb_info->map_dev == dev) {
+			spin_unlock_bh(&nss_ifb_list_lock);
+			return ifb_info;
+		}
+	}
+	spin_unlock_bh(&nss_ifb_list_lock);
+	return NULL;
+}
+
+/*
+ * nss_ifb_find_dev()
+ *	Find and return the IFB netdev in the ifb list.
+ */
+struct nss_ifb_info *nss_ifb_find_dev(struct net_device *dev)
+{
+	struct nss_ifb_info *ifb_info;
+
+	spin_lock_bh(&nss_ifb_list_lock);
+	list_for_each_entry(ifb_info, &nss_ifb_list, map_list) {
+		if (ifb_info->ifb_dev == dev) {
+			spin_unlock_bh(&nss_ifb_list_lock);
+			return ifb_info;
+		}
+	}
+	spin_unlock_bh(&nss_ifb_list_lock);
+	return NULL;
+}
+
+/*
+ * nss_ifb_bind()
+ *	API to bind an IFB device with its requested mapped interface.
+ */
+int32_t nss_ifb_bind(struct nss_ifb_info *ifb_info, struct net_device *from_dev,
+		struct net_device *to_dev)
+{
+	if (!ifb_info) {
+		/*
+		 * IFB not present in local LL.
+		 * Add the entry in LL.
+		 */
+		ifb_info = kmalloc(sizeof(*ifb_info), GFP_KERNEL);
+		if (!ifb_info) {
+			nss_igs_error("kmalloc failed\n");
+			return -ENOMEM;
+		}
+		ifb_info->ifb_dev = to_dev;
+		ifb_info->map_dev = from_dev;
+		ifb_info->is_mapped = true;
+		nss_ifb_list_add(ifb_info);
+	} else {
+		/*
+		 * IFB present in local LL and its is_mapped is not set.
+		 * make the ifb_info's is_mapped to true again.
+		 */
+		spin_lock_bh(&nss_ifb_list_lock);
+		ifb_info->map_dev = from_dev;
+		ifb_info->is_mapped = true;
+		spin_unlock_bh(&nss_ifb_list_lock);
+	}
+	return 0;
+}
+
+/*
+ * nss_ifb_update_dev_stats()
+ *	IFB stats function to copy the common stats to the netdevice.
+ */
+static void nss_ifb_update_dev_stats(struct net_device *dev, struct nss_igs_stats_sync_msg *sync_stats)
+{
+	struct pcpu_sw_netstats stats;
+	struct nss_cmn_node_stats *node_stats = &(sync_stats->node_stats);
+
+	if (!dev) {
+		nss_igs_error("Device is NULL\n");
+		return;
+	}
+
+	u64_stats_init(&stats.syncp);
+	u64_stats_update_begin(&stats.syncp);
+
+	/*
+	 * In NSS firmware, the IFB interface's stats are getting updated
+	 * post shaping. Therefore IFB interface's stats should be updated
+	 * with NSS firmware's IFB TX stats only.
+	 */
+	stats.rx_packets = stats.tx_packets = node_stats->tx_packets;
+	stats.rx_bytes = stats.tx_bytes = node_stats->tx_bytes;
+	dev->stats.rx_dropped = dev->stats.tx_dropped += sync_stats->igs_stats.tx_dropped;
+	u64_stats_update_end(&stats.syncp);
+
+	ifb_update_offload_stats(dev, &stats);
+}
+
+/*
+ * nss_ifb_event_cb()
+ *	Event Callback for IFB interface to receive events from NSS firmware.
+ */
+static void nss_ifb_event_cb(void *if_ctx, struct nss_cmn_msg *ncm)
+{
+	struct net_device *netdev = if_ctx;
+	struct nss_igs_msg *nim = (struct nss_igs_msg *)ncm;
+
+	switch (ncm->type) {
+	case NSS_IGS_MSG_SYNC_STATS:
+		nss_ifb_update_dev_stats(netdev, (struct nss_igs_stats_sync_msg *)&nim->msg.stats);
+		break;
+
+	default:
+		nss_igs_error("%px: Unknown Event from NSS\n", netdev);
+		break;
+	}
+}
+
+/*
+ * nss_ifb_delete_if()
+ *	Delete an IFB interface in NSS Firmware.
+ */
+void nss_ifb_delete_if(int32_t if_num)
+{
+	nss_igs_unregister_if(if_num);
+	if (nss_dynamic_interface_dealloc_node(if_num, NSS_DYNAMIC_INTERFACE_TYPE_IGS)
+			 != NSS_TX_SUCCESS) {
+		nss_igs_error("Failed to de-alloc IFB dynamic interface\n");
+	}
+}
+
+/*
+ * nss_ifb_create_if()
+ *	Create an IFB interface in NSS Firmware.
+ */
+int32_t nss_ifb_create_if(struct net_device *dev)
+{
+	int32_t if_num, ret;
+	uint32_t features = 0;
+	struct nss_ctx_instance *nss_ctx;
+
+	if_num = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_IGS);
+	if (if_num < 0) {
+		nss_igs_error("%d interface creation failed\n", if_num);
+		return -1;
+	}
+
+	nss_ctx = nss_igs_register_if(if_num,
+			NSS_DYNAMIC_INTERFACE_TYPE_IGS,
+			nss_ifb_event_cb,
+			dev,
+			features);
+	if (!nss_ctx) {
+		nss_igs_error("%d interface registration failed\n", if_num);
+		goto registration_fail;
+	}
+	return if_num;
+
+registration_fail:
+	ret = nss_dynamic_interface_dealloc_node(if_num, NSS_DYNAMIC_INTERFACE_TYPE_IGS);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_igs_error("%d interface dealloc failed\n", if_num);
+	}
+	return -1;
+}
diff --git a/qca-nss-clients/nss_qdisc/igs/nss_ifb.h b/qca-nss-clients/nss_qdisc/igs/nss_ifb.h
new file mode 100644
index 0000000..e5bd3d6
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/igs/nss_ifb.h
@@ -0,0 +1,138 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#define NSS_IFB_MSG_TIMEOUT (600*HZ)	/* 1 min timeout */
+
+/*
+ * nss_ifb_if_config
+ *	Types of IFB configuration messages.
+ */
+enum nss_ifb_if_config {
+	NSS_IFB_SET_IGS_NODE,
+	NSS_IFB_CLEAR_IGS_NODE,
+	NSS_IFB_SET_NEXTHOP,
+	NSS_IFB_RESET_NEXTHOP,
+	NSS_IFB_OPEN,
+	NSS_IFB_CLOSE,
+};
+
+/*
+ * nss_ifb_info
+ *	IFB and its mapped interface's bind structure.
+ */
+struct nss_ifb_info {
+	struct net_device *ifb_dev;	/* IFB device */
+	struct net_device *map_dev;	/* Device mapped to an IFB device */
+	struct list_head map_list;	/* Internal list */
+	bool is_mapped;			/* Flag to indicate whether mapping is valid or not */
+};
+
+/*
+ * nss_ifb_igs_ip_pre_routing_hook()
+ *	Copy class-id to Linux CT structure.
+ *
+ * Copy class-id from tc_index field of skb in ingress QoS fields inside
+ * DSCP CT extention structure.
+ */
+extern unsigned int nss_ifb_igs_ip_pre_routing_hook(void *priv, struct sk_buff *skb,
+		 const struct nf_hook_state *state);
+
+/*
+ * nss_ifb_list_del()
+ *	API to delete member in ifb list.
+ */
+extern void nss_ifb_list_del(struct nss_ifb_info *ifb_info);
+
+/*
+ * nss_ifb_is_mapped()
+ *	Returns the map status of the given ifb bind structure.
+ */
+extern bool nss_ifb_is_mapped(struct nss_ifb_info *ifb_info);
+
+/*
+ * nss_ifb_config_msg_tx()
+ *	Send IFB configure message to an IFB mapped interface.
+ */
+extern int32_t nss_ifb_config_msg_tx(struct net_device *dev, int32_t ifb_num,
+		 enum nss_ifb_if_config config, void *cb);
+
+/*
+ * nss_ifb_config_msg_tx_sync()
+ *	Send IFB configure message to an IFB mapped interface and wait for the response.
+ */
+extern int32_t nss_ifb_config_msg_tx_sync(struct net_device *dev, int32_t ifb_num,
+		 enum nss_ifb_if_config config, void *cb);
+
+/*
+ * nss_ifb_reset_nexthop()
+ *	Send RESET NEXTHOP configure message to an IFB mapped interface.
+ */
+extern bool nss_ifb_reset_nexthop(struct nss_ifb_info *ifb_info);
+
+/*
+ * nss_ifb_clear_igs_node()
+ *	Send CLEAR configure message to an IFB mapped interface.
+ */
+extern bool nss_ifb_clear_igs_node(struct nss_ifb_info *ifb_info);
+
+/*
+ * nss_ifb_down()
+ *	Send interface's DOWN configure message to an IFB interface.
+ */
+extern bool nss_ifb_down(struct nss_ifb_info *ifb_info);
+
+/*
+ * nss_ifb_up()
+ *	Send interface's UP configure message to an IFB interface.
+ */
+extern bool nss_ifb_up(struct nss_ifb_info *ifb_info);
+
+/*
+ * nss_ifb_init()
+ *	Initialization API.
+ */
+extern void nss_ifb_init(void);
+
+/*
+ * nss_ifb_find_map_dev()
+ *	Find and return the IFB mapped netdev in the ifb list.
+ */
+extern struct nss_ifb_info *nss_ifb_find_map_dev(struct net_device *dev);
+
+/*
+ * nss_ifb_find_dev()
+ *	Find and return the IFB netdev in the ifb list.
+ */
+extern struct nss_ifb_info *nss_ifb_find_dev(struct net_device *dev);
+
+/*
+ * nss_ifb_bind()
+ *	API to bind an IFB device with its requested mapped interface.
+ */
+extern int32_t nss_ifb_bind(struct nss_ifb_info *ifb_info, struct net_device *from_dev,
+		struct net_device *to_dev);
+
+/*
+ * nss_ifb_delete_if()
+ *	Delete an IFB interface in NSS Firmware.
+ */
+extern void nss_ifb_delete_if(int32_t if_num);
+
+/*
+ * nss_ifb_create_if()
+ *	Create an IFB interface in NSS Firmware.
+ */
+extern int32_t nss_ifb_create_if(struct net_device *dev);
diff --git a/qca-nss-clients/nss_qdisc/igs/nss_igs.h b/qca-nss-clients/nss_qdisc/igs/nss_igs.h
new file mode 100644
index 0000000..7e7941f
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/igs/nss_igs.h
@@ -0,0 +1,66 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#define NSS_IGS_DEBUG_LEVEL_ERROR 1
+#define NSS_IGS_DEBUG_LEVEL_WARN 2
+#define NSS_IGS_DEBUG_LEVEL_INFO 3
+#define NSS_IGS_DEBUG_LEVEL_TRACE 4
+
+/*
+ * Debug message for module init and exit
+ */
+#define nss_igs_info_always(s, ...) printk(KERN_INFO"%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+/*
+ * Error and warn message will be enabled by default in Makefile
+ */
+#if (NSS_IGS_DEBUG_LEVEL < NSS_IGS_DEBUG_LEVEL_ERROR)
+#define nss_igs_assert(s, ...)
+#define nss_igs_error(s, ...)
+#else
+#define nss_igs_assert(c, s, ...) { if (!(c)) { pr_emerg("ASSERT: %s:%d:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__); BUG(); } }
+#define nss_igs_error(s, ...) pr_err("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_IGS_DEBUG_LEVEL < NSS_IGS_DEBUG_LEVEL_WARN)
+#define nss_igs_warning(s, ...)
+#else
+#define nss_igs_warning(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_igs_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_igs_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+#else
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_IGS_DEBUG_LEVEL < NSS_IGS_DEBUG_LEVEL_INFO)
+#define nss_igs_info(s, ...)
+#else
+#define nss_igs_info(s, ...) pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_IGS_DEBUG_LEVEL < NSS_IGS_DEBUG_LEVEL_TRACE)
+#define nss_igs_trace(s, ...)
+#else
+#define nss_igs_trace(s, ...) pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif
diff --git a/qca-nss-clients/nss_qdisc/igs/nss_mirred.c b/qca-nss-clients/nss_qdisc/igs/nss_mirred.c
new file mode 100644
index 0000000..5729b08
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/igs/nss_mirred.c
@@ -0,0 +1,769 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <nss_api_if.h>
+#include <nss_cmn.h>
+#include <linux/tc_act/tc_nss_mirred.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include "nss_mirred.h"
+#include "nss_igs.h"
+#include "nss_ifb.h"
+
+static LIST_HEAD(nss_mirred_list);		/* List for all nss mirred actions */
+static DEFINE_SPINLOCK(nss_mirred_list_lock);	/* Lock for the nss mirred list */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0))
+static unsigned int nss_mirred_net_id;		/* NSS mirror net ID */
+static struct tc_action_ops nss_mirred_act_ops;	/* NSS action mirror ops */
+#endif
+
+/*
+ * nss_mirred_release()
+ *	Cleanup the resources for nss mirred action.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+static void nss_mirred_release(struct tc_action *tc_act, int bind)
+#else
+static void nss_mirred_release(struct tc_action *tc_act)
+#endif
+{
+	struct nss_mirred_tcf *act = nss_mirred_get(tc_act);
+	struct net_device *dev = rcu_dereference_protected(act->tcfm_dev, 1);
+	struct nss_ifb_info *ifb_info = nss_ifb_find_dev(dev);
+
+	if (!ifb_info) {
+		nss_igs_error("IFB device %s not found in the linked list \n", dev->name);
+		return;
+	}
+
+	/*
+	 * Send IFB RESET NEXTHOP configure message to the mapped interface.
+	 */
+	if (!nss_ifb_reset_nexthop(ifb_info)) {
+		nss_igs_error("Error in sending IFB RESET NEXTHOP configure message\n");
+	}
+
+	if (!nss_ifb_clear_igs_node(ifb_info)) {
+		nss_igs_error("Error in sending IFB CLEAR configure message\n");
+	}
+
+	/*
+	 * Delete the nss mirred action list.
+	 */
+	spin_lock_bh(&nss_mirred_list_lock);
+	list_del(&act->tcfm_list);
+	spin_unlock_bh(&nss_mirred_list_lock);
+	if (dev) {
+		dev_put(dev);
+	}
+}
+
+/*
+ * nss_mirred_policy
+ *	nss mirred policy structure.
+ */
+static const struct nla_policy nss_mirred_policy[TC_NSS_MIRRED_MAX + 1] = {
+	[TC_NSS_MIRRED_PARMS] = { .len = sizeof(struct tc_nss_mirred) },
+};
+
+/*
+ * nss_mirred_init()
+ *	Initialize the nss mirred action.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+static int nss_mirred_init(struct net *net, struct nlattr *nla,
+			   struct nlattr *est, struct tc_action *tc_act, int ovr,
+			   int bind)
+{
+#else
+static int nss_mirred_init(struct net *net, struct nlattr *nla,
+			   struct nlattr *est, struct tc_action **tc_act, int ovr,
+			   int bind, bool rtnl_held, struct tcf_proto *tp,
+			   struct netlink_ext_ack *extack)
+{
+	struct tc_action_net *tn = net_generic(net, nss_mirred_net_id);
+	u32 index;
+#endif
+	struct nlattr *arr[TC_NSS_MIRRED_MAX + 1];
+	struct tc_nss_mirred *parm;
+	struct nss_mirred_tcf *act;
+	struct net_device *to_dev, *from_dev;
+	struct nss_ifb_info *ifb_info;
+	int32_t ret, ifb_num;
+
+	if (!nla) {
+		return -EINVAL;
+	}
+
+	/*
+	 * Parse and validate the user configurations.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0))
+	ret = nla_parse_nested(arr, TC_NSS_MIRRED_MAX, nla, nss_mirred_policy);
+#else
+	ret = nla_parse_nested_deprecated(arr, TC_NSS_MIRRED_MAX, nla, nss_mirred_policy, extack);
+#endif
+	if (ret < 0) {
+		return ret;
+	}
+	if (!arr[TC_NSS_MIRRED_PARMS]) {
+		return -EINVAL;
+	}
+
+	parm = nla_data(arr[TC_NSS_MIRRED_PARMS]);
+	if (!parm->from_ifindex || !parm->to_ifindex) {
+		nss_igs_error("Invalid ifindex: from_ifindex: %u, to_ifindex: %u\n",
+				parm->from_ifindex, parm->to_ifindex);
+		return -EINVAL;
+	}
+
+	from_dev = __dev_get_by_index(net, parm->from_ifindex);
+	if (!from_dev) {
+		nss_igs_error("No device found for %u ifindex\n", parm->from_ifindex);
+		return -ENODEV;
+	}
+
+	if (nss_cmn_get_interface_number_by_dev(from_dev) < 0) {
+		nss_igs_error("No NSS FW device found for %s\n", from_dev->name);
+		return -ENODEV;
+	}
+
+	if (netif_is_ifb_dev(from_dev)) {
+		nss_igs_error("IFB device %s as from_dev\n", from_dev->name);
+		return -ENODEV;
+	}
+
+	to_dev = __dev_get_by_index(net, parm->to_ifindex);
+	if (!to_dev) {
+		nss_igs_error("No device found for %u ifindex\n", parm->to_ifindex);
+		return -ENODEV;
+	}
+
+	if (!netif_is_ifb_dev(to_dev)) {
+		nss_igs_error("%s is not an IFB device\n", to_dev->name);
+		return -ENODEV;
+	}
+
+	ifb_info = nss_ifb_find_map_dev(from_dev);
+	if (ifb_info) {
+		if (nss_ifb_is_mapped(ifb_info)) {
+			nss_igs_error("%s device is already mapped to the other IFB device\n",
+					from_dev->name);
+			return -EEXIST;
+		}
+	}
+
+	ifb_info = nss_ifb_find_dev(to_dev);
+	if (ifb_info) {
+		if (nss_ifb_is_mapped(ifb_info)) {
+			nss_igs_error("%s IFB device is already mapped to the other device\n",
+					to_dev->name);
+			return -EEXIST;
+		}
+	}
+
+	ifb_num = nss_cmn_get_interface_number_by_dev_and_type(to_dev, NSS_DYNAMIC_INTERFACE_TYPE_IGS);
+	if (ifb_num < 0) {
+		/*
+		 * Create the IFB instance in the NSS firmware.
+		 */
+		ifb_num = nss_ifb_create_if(to_dev);
+		if (ifb_num < 0) {
+			nss_igs_error("failure in IFB creation\n");
+			return -EINVAL;
+		}
+	}
+
+	/*
+	 * Send config message to the interface attached to an IFB interface.
+	 */
+	if (nss_ifb_config_msg_tx_sync(from_dev, ifb_num, NSS_IFB_SET_IGS_NODE, NULL) < 0) {
+		nss_igs_error("Sending config to %s dev failed\n", from_dev->name);
+		return -EINVAL;
+	}
+
+	/*
+	 * Send next hop config message to the interface attached to an IFB interface.
+	 */
+	if (nss_ifb_config_msg_tx_sync(from_dev, ifb_num, NSS_IFB_SET_NEXTHOP, NULL) < 0) {
+		nss_igs_error("Sending next hop config to %s dev failed\n", from_dev->name);
+		return -EINVAL;
+	}
+
+	/*
+	 * Bind an IFB device with its requested mapped interface.
+	 */
+	ret = nss_ifb_bind(ifb_info, from_dev, to_dev);
+	if (ret < 0) {
+		nss_igs_error(" Binding an IFB device failed\n");
+		nss_ifb_delete_if(ifb_num);
+		return ret;
+	}
+
+	/*
+	 * Return error if nss mirred action index is present in the hash.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	if (tcf_hash_check(parm->index, tc_act, bind)) {
+		return -EEXIST;
+	}
+
+	ret = tcf_hash_create(parm->index, est, tc_act, sizeof(*act),
+			bind, true);
+	if (ret) {
+		return ret;
+	}
+
+	act = nss_mirred_get(tc_act);
+#else
+	index = parm->index;
+	ret = tcf_idr_check_alloc(tn, &index, tc_act, bind);
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (ret && bind) {
+		return 0;
+	}
+
+	if (!ret) {
+		ret = tcf_idr_create(tn, index, est, tc_act, &nss_mirred_act_ops,
+				bind, true);
+		if (ret) {
+			tcf_idr_cleanup(tn, index);
+			return ret;
+		}
+	}
+
+	act = nss_mirred_get(*tc_act);
+#endif
+	/*
+	 * Fill up the nss mirred tc parameters to
+	 * its local action structure.
+	 */
+	ASSERT_RTNL();
+	act->tcf_action = parm->action;
+	act->tcfm_from_ifindex = parm->from_ifindex;
+	act->tcfm_to_ifindex = parm->to_ifindex;
+	dev_hold(to_dev);
+	rcu_assign_pointer(act->tcfm_dev, to_dev);
+
+	/*
+	 * Add the new action instance to the nss mirred action list.
+	 */
+	spin_lock_bh(&nss_mirred_list_lock);
+	list_add(&act->tcfm_list, &nss_mirred_list);
+	spin_unlock_bh(&nss_mirred_list_lock);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	tcf_hash_insert(tc_act);
+#endif
+
+	return ACT_P_CREATED;
+}
+
+/*
+ * nss_mirred_act()
+ *	nss mirred action handler.
+ */
+static int nss_mirred_act(struct sk_buff *skb, const struct tc_action *tc_act,
+		      struct tcf_result *res)
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	struct nss_mirred_tcf *act = tc_act->priv;
+#else
+	struct nss_mirred_tcf *act = nss_mirred_get(tc_act);
+#endif
+	struct net_device *dev;
+	struct sk_buff *skb_new;
+	int retval, err;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	u32 skb_tc_at = G_TC_AT(skb->tc_verd);
+
+	/*
+	 * Return if skb is not at ingress.
+	 */
+	if (!(skb_tc_at & AT_INGRESS)) {
+		return TC_ACT_UNSPEC;
+	}
+
+#else
+	if (!skb_at_tc_ingress(skb)) {
+		return TC_ACT_UNSPEC;
+	}
+#endif
+
+	/*
+	 * Update the last use of action.
+	 */
+	tcf_lastuse_update(&act->tcf_tm);
+	bstats_cpu_update(this_cpu_ptr(act->common.cpu_bstats), skb);
+
+	rcu_read_lock();
+	retval = READ_ONCE(act->tcf_action);
+	dev = rcu_dereference(act->tcfm_dev);
+	if (unlikely(!dev)) {
+		nss_igs_error("tc nssmirred: target device is gone\n");
+		goto out;
+	}
+
+	if (unlikely(!(dev->flags & IFF_UP))) {
+		nss_igs_error("tc nssmirred: device %s is down\n", dev->name);
+		goto out;
+	}
+
+	/*
+	 * Redirect the packet to the attached IFB interface
+	 */
+	skb_new = skb_clone(skb, GFP_ATOMIC);
+	if (!skb_new) {
+		goto out;
+	}
+
+	skb_new->skb_iif = skb->dev->ifindex;
+	skb_new->dev = dev;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	skb_new->tc_verd = SET_TC_FROM(skb_new->tc_verd, skb_tc_at);
+	skb_push_rcsum(skb_new, skb->mac_len);
+	skb_sender_cpu_clear(skb_new);
+#else
+	skb_set_redirected(skb_new, skb_new->tc_at_ingress);
+	skb_push_rcsum(skb_new, skb->mac_len);
+#endif
+
+	err = dev_queue_xmit(skb_new);
+	if (!err) {
+		rcu_read_unlock();
+		return retval;
+	}
+out:
+	qstats_overlimit_inc(this_cpu_ptr(act->common.cpu_qstats));
+	retval = TC_ACT_SHOT;
+	rcu_read_unlock();
+	return retval;
+}
+
+/*
+ * nss_mirred_dump()
+ *	Dump the nssmirred action configurations.
+ */
+static int nss_mirred_dump(struct sk_buff *skb, struct tc_action *tc_act, int bind, int ref)
+{
+	struct tcf_t filter;
+	unsigned char *tail = skb_tail_pointer(skb);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	struct nss_mirred_tcf *act = tc_act->priv;
+#else
+	struct nss_mirred_tcf *act = nss_mirred_get(tc_act);
+#endif
+	struct tc_nss_mirred opt = {
+		.index   = act->tcf_index,
+		.action  = act->tcf_action,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		.refcnt  = act->tcf_refcnt - ref,
+		.bindcnt = act->tcf_bindcnt - bind,
+#else
+		.refcnt  = refcount_read(&act->tcf_refcnt) - ref,
+		.bindcnt = atomic_read(&act->tcf_bindcnt) - bind,
+#endif
+		.from_ifindex = act->tcfm_from_ifindex,
+		.to_ifindex = act->tcfm_to_ifindex,
+	};
+
+	if (nla_put(skb, TC_NSS_MIRRED_PARMS, sizeof(opt), &opt)) {
+		goto out;
+	}
+	filter.install = jiffies_to_clock_t(jiffies - act->tcf_tm.install);
+	filter.lastuse = jiffies_to_clock_t(jiffies - act->tcf_tm.lastuse);
+	filter.expires = jiffies_to_clock_t(act->tcf_tm.expires);
+	if (nla_put(skb, TC_NSS_MIRRED_TM, sizeof(filter), &filter)) {
+		goto out;
+	}
+	return skb->len;
+
+out:
+	nlmsg_trim(skb, tail);
+	return -1;
+}
+
+/*
+ * nss_mirred_unregister_event_handler()
+ *	nss mirred un-register event handler.
+ */
+static void nss_mirred_unregister_event_handler(struct net_device *dev)
+{
+	struct nss_ifb_info *ifb_info;
+
+	/*
+	 * IFB interface.
+	 */
+	if (netif_is_ifb_dev(dev)) {
+		ifb_info = nss_ifb_find_dev(dev);
+	} else {
+		/*
+		 * Check if the device is an IFB mapped device.
+		 */
+		ifb_info = nss_ifb_find_map_dev(dev);
+	}
+
+	/*
+	 * Device not present in ifb list.
+	 */
+	if (!ifb_info) {
+		return;
+	}
+
+	/*
+	 * Send IFB RESET NEXTHOP configure message to the mapped interface.
+	 */
+	if (!nss_ifb_reset_nexthop(ifb_info)) {
+		nss_igs_error("Error in sending IFB RESET NEXTHOP configure message\n");
+	}
+
+	/*
+	 * Send IFB CLEAR configure message to the mapped interface.
+	 */
+	if (!nss_ifb_clear_igs_node(ifb_info)) {
+		nss_igs_error("Error in sending IFB CLEAR configure message\n");
+	}
+	if (netif_is_ifb_dev(dev)) {
+		int32_t ifb_num = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_IGS);
+
+		if (ifb_num < 0) {
+			nss_igs_error("Invalid %s IFB device\n", dev->name);
+			return;
+		}
+		nss_ifb_delete_if(ifb_num);
+		nss_ifb_list_del(ifb_info);
+	}
+}
+
+/*
+ * nss_mirred_down_event_handler()
+ *	nss mirred interface's down event handler.
+ */
+static void nss_mirred_down_event_handler(struct net_device *dev)
+{
+	struct nss_ifb_info *ifb_info;
+
+	/*
+	 * IFB interface.
+	 */
+	if (!netif_is_ifb_dev(dev)) {
+		return;
+	}
+
+	ifb_info = nss_ifb_find_dev(dev);
+
+	if (!ifb_info) {
+		return;
+	}
+
+	if (!nss_ifb_down(ifb_info)) {
+		nss_igs_error("Error in sending IFB DOWN configure message\n");
+	}
+}
+
+/*
+ * nss_mirred_up_event_handler()
+ *	nss mirred interface's up event handler.
+ */
+static void nss_mirred_up_event_handler(struct net_device *dev)
+{
+	struct nss_ifb_info *ifb_info;
+
+	/*
+	 * IFB interface.
+	 */
+	if (!netif_is_ifb_dev(dev)) {
+		return;
+	}
+
+	ifb_info = nss_ifb_find_dev(dev);
+
+	if (!ifb_info) {
+		return;
+	}
+
+	if (!nss_ifb_up(ifb_info)) {
+		nss_igs_error("Error in sending IFB UP configure message\n");
+	}
+}
+
+/*
+ * nss_mirred_device_event()
+ *	nssmirred device event callback.
+ */
+static int nss_mirred_device_event(struct notifier_block *unused,
+		unsigned long event, void *ptr)
+{
+	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
+	struct nss_mirred_tcf *act;
+
+	switch (event) {
+	case NETDEV_UNREGISTER:
+		nss_mirred_unregister_event_handler(dev);
+
+		ASSERT_RTNL();
+
+		/*
+		 * Free up the actions instance present in
+		 * the nss mirred list.
+		 */
+		spin_lock_bh(&nss_mirred_list_lock);
+		list_for_each_entry(act, &nss_mirred_list, tcfm_list) {
+			if (rcu_access_pointer(act->tcfm_dev) == dev) {
+				dev_put(dev);
+				RCU_INIT_POINTER(act->tcfm_dev, NULL);
+			}
+		}
+		spin_unlock_bh(&nss_mirred_list_lock);
+		break;
+	case NETDEV_UP:
+		nss_mirred_up_event_handler(dev);
+		break;
+	case NETDEV_DOWN:
+		nss_mirred_down_event_handler(dev);
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0))
+/*
+ * nss_mirred_walker
+ *	nssmirred tcf_action walker
+ */
+static int nss_mirred_walker(struct net *net, struct sk_buff *skb,
+		struct netlink_callback *cb, int type,
+		const struct tc_action_ops *ops,
+		struct netlink_ext_ack *extack)
+{
+	struct tc_action_net *tn = net_generic(net, nss_mirred_net_id);
+
+	return tcf_generic_walker(tn, skb, cb, type, ops, extack);
+}
+
+/*
+ * nss_mirred_search
+ *	nssmirred search idr function.
+ */
+static int nss_mirred_search(struct net *net, struct tc_action **a, u32 index)
+{
+	struct tc_action_net *tn = net_generic(net, nss_mirred_net_id);
+
+	return tcf_idr_search(tn, a, index);
+}
+
+/*
+ * nss_mirred_dev_put
+ *	Release igs dev
+ */
+static void nss_mirred_dev_put(void *priv)
+{
+	struct net_device *dev = priv;
+
+	dev_put(dev);
+}
+
+/*
+ * nss_mirred_device
+ *	Get the igs dev.
+ */
+static struct net_device *nss_mirred_device(const struct tc_action *a, tc_action_priv_destructor *destructor)
+{
+	struct nss_mirred_tcf *m = nss_mirred_get(a);
+	struct net_device *dev;
+
+	rcu_read_lock();
+	dev = rcu_dereference(m->tcfm_dev);
+	if (dev) {
+		dev_hold(dev);
+		*destructor = nss_mirred_dev_put;
+	}
+	rcu_read_unlock();
+
+	return dev;
+}
+#endif
+
+/*
+ * nss_mirred_device_notifier
+ *	nss mirred device notifier structure.
+ */
+static struct notifier_block nss_mirred_device_notifier = {
+	.notifier_call = nss_mirred_device_event,
+};
+
+/*
+ * nss_mirred_act_ops
+ *	Registration structure for nss mirred action.
+ */
+static struct tc_action_ops nss_mirred_act_ops = {
+	.kind		=	"nssmirred",
+	.owner		=	THIS_MODULE,
+	.act		=	nss_mirred_act,
+	.dump		=	nss_mirred_dump,
+	.cleanup	=	nss_mirred_release,
+	.init		=	nss_mirred_init,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	.type		=	TCA_ACT_MIRRED_NSS,
+#else
+	.id		=	TCA_ID_MIRRED_NSS,
+	.walk		=	nss_mirred_walker,
+	.lookup		=	nss_mirred_search,
+	.size           =       sizeof(struct nss_mirred_tcf),
+	.get_dev	=	nss_mirred_device
+#endif
+};
+
+/*
+ * nss_mirred_igs_nf_ops
+ *	Pre-routing hooks into netfilter packet monitoring point.
+ */
+struct nf_hook_ops nss_mirred_igs_nf_ops[] __read_mostly = {
+	/*
+	 * Pre routing hook is used to copy class-id to the ECM rule.
+	 */
+	{
+		.hook		=	nss_ifb_igs_ip_pre_routing_hook,
+		.pf		=	NFPROTO_IPV4,
+		.hooknum	=	NF_INET_PRE_ROUTING,
+		.priority	=	NF_IP_PRI_CONNTRACK + 1,
+	},
+	{
+		.hook		=	nss_ifb_igs_ip_pre_routing_hook,
+		.pf		=	NFPROTO_IPV6,
+		.hooknum	=	NF_INET_PRE_ROUTING,
+		.priority	=	NF_IP_PRI_CONNTRACK + 1,
+	},
+};
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0))
+/*
+ * nss_mirred_init_net
+ *	nssmirred net init function.
+ */
+static __net_init int nss_mirred_init_net(struct net *net)
+{
+	struct tc_action_net *tn = net_generic(net, nss_mirred_net_id);
+	nf_register_net_hooks(net, nss_mirred_igs_nf_ops,
+			ARRAY_SIZE(nss_mirred_igs_nf_ops));
+
+	return tc_action_net_init(net, tn, &nss_mirred_act_ops);
+}
+
+/*
+ * nss_mirred_exit_net
+ *	nssmirred net exit function.
+ */
+static void __net_exit nss_mirred_exit_net(struct net *net)
+{
+	nf_unregister_net_hooks(net, nss_mirred_igs_nf_ops,
+			ARRAY_SIZE(nss_mirred_igs_nf_ops));
+}
+
+/*
+ * nss_mirred_exit_batch_net
+ *	nssmirred exit_batch_net function.
+ */
+static void __net_exit nss_mirred_exit_batch_net(struct list_head *net_list)
+{
+	tc_action_net_exit(net_list, nss_mirred_net_id);
+}
+
+/*
+ * nss_mirred_net_ops
+ *	Per netdevice ops.
+ */
+static struct pernet_operations nss_mirred_net_ops = {
+	.init = nss_mirred_init_net,
+	.exit = nss_mirred_exit_net,
+	.exit_batch = nss_mirred_exit_batch_net,
+	.id   = &nss_mirred_net_id,
+	.size = sizeof(struct tc_action_net),
+};
+#endif
+
+/*
+ * nss_mirred_init_module()
+ *	nssmirred init function.
+ */
+static int __init nss_mirred_init_module(void)
+{
+	int err = register_netdevice_notifier(&nss_mirred_device_notifier);
+	if (err) {
+		return err;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	err = tcf_register_action(&nss_mirred_act_ops, NSS_MIRRED_TAB_MASK);
+	if (err) {
+		unregister_netdevice_notifier(&nss_mirred_device_notifier);
+		return err;
+	}
+
+	err = nf_register_hooks(nss_mirred_igs_nf_ops, ARRAY_SIZE(nss_mirred_igs_nf_ops));
+	if (err < 0) {
+		nss_igs_error("Registering ingress nf hooks failed, ret: %d\n", err);
+		tcf_unregister_action(&nss_mirred_act_ops);
+		unregister_netdevice_notifier(&nss_mirred_device_notifier);
+		return err;
+	}
+#else
+	err = tcf_register_action(&nss_mirred_act_ops, &nss_mirred_net_ops);
+	if (err) {
+		unregister_netdevice_notifier(&nss_mirred_device_notifier);
+		return err;
+	}
+#endif
+
+	/*
+	 * Set the IGS module reference variable.
+	 */
+	nss_igs_module_save(&nss_mirred_act_ops, THIS_MODULE);
+
+	nss_ifb_init();
+	return 0;
+}
+
+/*
+ * nss_mirred_cleanup_module()
+ *	nssmirred exit function.
+ */
+static void __exit nss_mirred_cleanup_module(void)
+{
+	/*
+	 * Reset the IGS module reference variable.
+	 */
+	nss_igs_module_save(&nss_mirred_act_ops, NULL);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	nf_unregister_hooks(nss_mirred_igs_nf_ops, ARRAY_SIZE(nss_mirred_igs_nf_ops));
+
+	/*
+	 * Un-register nss mirred action.
+	 */
+	tcf_unregister_action(&nss_mirred_act_ops);
+#else
+	tcf_unregister_action(&nss_mirred_act_ops, &nss_mirred_net_ops);
+#endif
+	unregister_netdevice_notifier(&nss_mirred_device_notifier);
+}
+
+module_init(nss_mirred_init_module);
+module_exit(nss_mirred_cleanup_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/qca-nss-clients/nss_qdisc/igs/nss_mirred.h b/qca-nss-clients/nss_qdisc/igs/nss_mirred.h
new file mode 100644
index 0000000..3f48f83
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/igs/nss_mirred.h
@@ -0,0 +1,54 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <net/act_api.h>
+
+#define NSS_MIRRED_TAB_MASK 7
+
+/*
+ * nss_mirred_tcf
+ *	nss mirred internal structure.
+ */
+struct nss_mirred_tcf {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	struct tcf_common common;		/* Common filter structure */
+#else
+	struct tc_action common;		/* Common filter structure */
+#endif
+	__u32 tcfm_to_ifindex;			/* Index number of device to which
+						 * traffic will be redirected.
+						 */
+	__u32 tcfm_from_ifindex;		/* Index number of device from which
+						 * traffic will be redirected.
+						 */
+	struct net_device __rcu *tcfm_dev;	/* net device pointer of the device
+						 * to which traffic will be redirected.
+						 */
+	struct list_head tcfm_list;		/* list for the nss mirred action */
+};
+
+/*
+ * To get the pointer of nss mirred action structure from the common
+ * tc_action structure pointer.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+#define nss_mirred_get(a) \
+	container_of(a->priv, struct nss_mirred_tcf, common)
+#else
+#define nss_mirred_get(a) ((struct nss_mirred_tcf *)a)
+#endif
+
diff --git a/qca-nss-clients/nss_qdisc/nss_bf.c b/qca-nss-clients/nss_qdisc/nss_bf.c
new file mode 100644
index 0000000..5bc7d97
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_bf.c
@@ -0,0 +1,918 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2017, 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_qdisc.h"
+
+/*
+ * nss_bf class instance structure
+ */
+struct nss_bf_class_data {
+	struct nss_qdisc nq;			/* Base class used by nss_qdisc */
+	struct Qdisc_class_common cl_common;	/* Common class structure */
+	u32 rate;				/* Allowed bandwidth for this class */
+	u32 burst;				/* Allowed burst for this class */
+	u32 mtu;				/* MTU size of the interface */
+	u32 quantum;				/* Quantum allocation for DRR */
+	struct Qdisc *qdisc;			/* Pointer to child qdisc */
+};
+
+/*
+ * nss_bf qdisc instance structure
+ */
+struct nss_bf_sched_data {
+	struct nss_qdisc nq;			/* Base class used by nss_qdisc */
+	u16 defcls;				/* default class id */
+	struct nss_bf_class_data root;		/* root class */
+	struct Qdisc_class_hash clhash;		/* class hash */
+};
+
+/*
+ * nss_bf_policy structure
+ */
+static struct nla_policy nss_bf_policy[TCA_NSSBF_MAX + 1] = {
+	[TCA_NSSBF_CLASS_PARMS] = { .len = sizeof(struct tc_nssbf_class_qopt) },
+	[TCA_NSSBF_QDISC_PARMS] = { .len = sizeof(struct tc_nssbf_qopt) },
+};
+
+/*
+ * nss_bf_find_class()
+ *	Returns a pointer to class if classid matches with a class under this qdisc.
+ */
+static inline struct nss_bf_class_data *nss_bf_find_class(u32 classid,
+							struct Qdisc *sch)
+{
+	struct nss_bf_sched_data *q = qdisc_priv(sch);
+	struct Qdisc_class_common *clc;
+	clc = qdisc_class_find(&q->clhash, classid);
+	if (clc == NULL) {
+		nss_qdisc_info("Cannot find class with classid %u in qdisc %px hash table %px\n", classid, sch, &q->clhash);
+		return NULL;
+	}
+	return container_of(clc, struct nss_bf_class_data, cl_common);
+}
+
+/*
+ * nss_bf_change_class()
+ *	Configures a new class.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_bf_change_class(struct Qdisc *sch, u32 classid, u32 parentid,
+		  struct nlattr **tca, unsigned long *arg)
+{
+	struct netlink_ext_ack *extack = NULL;
+#else
+static int nss_bf_change_class(struct Qdisc *sch, u32 classid, u32 parentid,
+		  struct nlattr **tca, unsigned long *arg, struct netlink_ext_ack *extack)
+{
+#endif
+	struct nss_bf_sched_data *q = qdisc_priv(sch);
+	struct nss_bf_class_data *cl = (struct nss_bf_class_data *)*arg;
+	struct nlattr *opt = tca[TCA_OPTIONS];
+	struct nlattr *tb[TCA_NSSBF_MAX + 1];
+	struct tc_nssbf_class_qopt *qopt;
+	struct nss_if_msg nim_config;
+	struct net_device *dev = qdisc_dev(sch);
+	unsigned int accel_mode = nss_qdisc_accel_mode_get(&q->nq);
+
+	nss_qdisc_info("Changing bf class %u\n", classid);
+	if (!opt) {
+		return -EINVAL;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_bf_policy, tb, TCA_NSSBF_MAX, TCA_NSSBF_CLASS_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_bf_policy, tb, TCA_NSSBF_MAX, TCA_NSSBF_CLASS_PARMS, extack);
+#endif
+
+	if (!qopt) {
+		return -EINVAL;
+	}
+
+	/*
+	 * If class with a given classid is not found, we allocate a new one
+	 */
+	if (!cl) {
+		struct nss_if_msg nim_attach;
+		nss_qdisc_info("Bf class %u not found. Allocating a new class.\n", classid);
+		cl = kzalloc(sizeof(struct nss_bf_class_data), GFP_KERNEL);
+
+		if (!cl) {
+			nss_qdisc_error("Class allocation failed for classid %u\n", classid);
+			return -EINVAL;
+		}
+
+		nss_qdisc_info("Bf class %u allocated %px\n", classid, cl);
+		cl->cl_common.classid = classid;
+
+		/*
+		 * We make the child qdisc a noop qdisc, and
+		 * set reference count to 1. This is important,
+		 * reference count should not be 0.
+		 */
+		cl->qdisc = &noop_qdisc;
+		nss_qdisc_atomic_set(&cl->nq);
+		*arg = (unsigned long)cl;
+
+		nss_qdisc_info("Adding classid %u to qdisc %px hash queue %px\n", classid, sch, &q->clhash);
+
+		/*
+		 * This is where a class gets initialized. Classes do not have a init function
+		 * that is registered to Linux. Therefore we initialize the NSSBF_GROUP shaper
+		 * here.
+		 */
+		if (nss_qdisc_init(sch, &cl->nq, NSS_SHAPER_NODE_TYPE_BF_GROUP, classid, accel_mode, extack) < 0)
+		{
+			nss_qdisc_error("Nss init for class %u failed\n", classid);
+			kfree(cl);
+			return -EINVAL;
+		}
+
+		/*
+		 * Set qos_tag of parent to which the class needs to be attached to.
+		 */
+		nim_attach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+
+		/*
+		 * Set the child to be this class.
+		 */
+		nim_attach.msg.shaper_configure.config.msg.shaper_node_config.snc.bf_attach.child_qos_tag = cl->nq.qos_tag;
+
+		/*
+		 * Send node_attach command down to the NSS
+		 */
+		if (nss_qdisc_node_attach(&q->nq, &cl->nq, &nim_attach,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_ATTACH) < 0) {
+			nss_qdisc_error("Nss attach for class %u failed\n", classid);
+			nss_qdisc_destroy(&cl->nq);
+			kfree(cl);
+			return -EINVAL;
+		}
+
+		/*
+		 * Add class to hash tree once it is attached in the NSS
+		 */
+		sch_tree_lock(sch);
+		qdisc_class_hash_insert(&q->clhash, &cl->cl_common);
+		sch_tree_unlock(sch);
+
+		/*
+		 * Hash grow should not come within the tree lock
+		 */
+		qdisc_class_hash_grow(sch, &q->clhash);
+
+		/*
+		 * Start the stats polling timer
+		 */
+		nss_qdisc_start_basic_stats_polling(&cl->nq);
+
+		nss_qdisc_info("Class %u successfully allocated\n", classid);
+	}
+
+	sch_tree_lock(sch);
+	cl->rate = qopt->rate;
+	cl->burst = qopt->burst;
+
+	/*
+	 * If MTU and quantum values are not provided, set them to
+	 * the interface's MTU value.
+	 */
+	if (!qopt->mtu) {
+		cl->mtu = psched_mtu(dev);
+		nss_qdisc_info("MTU not provided for bf class on interface %s. "
+				"Setting MTU to %u bytes\n", dev->name, cl->mtu);
+	} else {
+		cl->mtu = qopt->mtu;
+	}
+
+	if (!qopt->quantum) {
+		cl->quantum = psched_mtu(dev);
+		nss_qdisc_info("Quantum value not provided for bf class on interface %s. "
+				"Setting quantum to %u\n", dev->name, cl->quantum);
+	} else {
+		cl->quantum = qopt->quantum;
+	}
+
+	sch_tree_unlock(sch);
+
+	/*
+	 * Fill information that needs to be sent down to the NSS for configuring the
+	 * bf class.
+	 */
+	nim_config.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag;
+	nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.bf_group_param.quantum = cl->quantum;
+	nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.bf_group_param.lap.rate = cl->rate;
+	nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.bf_group_param.lap.burst = cl->burst;
+	nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.bf_group_param.lap.max_size = cl->mtu;
+	nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.bf_group_param.lap.short_circuit = false;
+
+	nss_qdisc_info("Rate = %u Burst = %u MTU = %u Quantum = %u\n", cl->rate, cl->burst, cl->mtu, cl->quantum);
+
+	/*
+	 * Send configure command to the NSS
+	 */
+	if (nss_qdisc_configure(&cl->nq, &nim_config,
+			NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_CHANGE_PARAM) < 0) {
+		nss_qdisc_error("Failed to configure class %u\n", classid);
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("Class %u changed successfully\n", classid);
+	return 0;
+}
+
+/*
+ * nss_bf_destroy_class()
+ *	Detaches all child nodes and destroys the class.
+ */
+static void nss_bf_destroy_class(struct Qdisc *sch, struct nss_bf_class_data *cl)
+{
+	struct nss_bf_sched_data *q = qdisc_priv(sch);
+	struct nss_if_msg nim;
+
+	nss_qdisc_info("Destroying bf class %px from qdisc %px\n", cl, sch);
+
+	/*
+	 * Note, this function gets called even for NSSBF and not just for NSSBF_GROUP.
+	 * If this is BF qdisc then we should not call nss_qdisc_destroy or stop polling
+	 * for stats. These two actions will happen inside nss_bf_destroy(), which is called
+	 * only for the root qdisc.
+	 */
+	if (cl == &q->root) {
+		nss_qdisc_info("We do not destroy bf class %px here since this is "
+				"the qdisc %px\n", cl, sch);
+		return;
+	}
+
+	/*
+	 * We always have to detach our child qdisc in NSS, before destroying it.
+	 */
+	if (cl->qdisc != &noop_qdisc) {
+		struct nss_qdisc *nq_child = qdisc_priv(cl->qdisc);
+		nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag;
+		if (nss_qdisc_node_detach(&cl->nq, nq_child, &nim,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+			nss_qdisc_error("Failed to detach child %x from class %x\n",
+					cl->qdisc->handle, q->nq.qos_tag);
+			return;
+		}
+	}
+
+	/*
+	 * And now we destroy the child.
+	 */
+	 nss_qdisc_put(cl->qdisc);
+
+	/*
+	 * Stop the stats polling timer and free class
+	 */
+	nss_qdisc_stop_basic_stats_polling(&cl->nq);
+
+	/*
+	 * Destroy the shaper in NSS
+	 */
+	nss_qdisc_destroy(&cl->nq);
+
+	/*
+	 * Free class
+	 */
+	kfree(cl);
+}
+
+/*
+ * nss_bf_delete_class()
+ *	Detaches a class from operation, but does not destroy it.
+ */
+static int nss_bf_delete_class(struct Qdisc *sch, unsigned long arg)
+{
+	struct nss_bf_sched_data *q = qdisc_priv(sch);
+	struct nss_bf_class_data *cl = (struct nss_bf_class_data *)arg;
+	struct nss_if_msg nim;
+	int refcnt;
+	struct nss_qdisc *nq_child = (struct nss_qdisc *)qdisc_priv(cl->qdisc);
+
+	/*
+	 * Since all classes are leaf nodes in our case, we dont have to make
+	 * that check.
+	 */
+	if (cl == &q->root)
+		return -EBUSY;
+
+	/*
+	 * The message to NSS should be sent to the parent of this class
+	 */
+	nss_qdisc_info("Detaching bf class: %px\n", cl);
+	nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.bf_detach.child_qos_tag = cl->nq.qos_tag;
+	if (nss_qdisc_node_detach(&q->nq, nq_child, &nim,
+			NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+		return -EINVAL;
+	}
+
+	sch_tree_lock(sch);
+	qdisc_reset(cl->qdisc);
+	qdisc_class_hash_remove(&q->clhash, &cl->cl_common);
+	refcnt = nss_qdisc_atomic_sub_return(&cl->nq);
+	sch_tree_unlock(sch);
+	if (!refcnt) {
+		nss_qdisc_error("Reference count should not be zero for class %px\n", cl);
+	}
+
+	return 0;
+}
+
+/*
+ * nss_bf_graft_class()
+ *	Replaces the qdisc attached to the provided class.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_bf_graft_class(struct Qdisc *sch, unsigned long arg, struct Qdisc *new,
+								 struct Qdisc **old)
+#else
+static int nss_bf_graft_class(struct Qdisc *sch, unsigned long arg, struct Qdisc *new,
+								 struct Qdisc **old, struct netlink_ext_ack *extack)
+#endif
+{
+	struct nss_bf_sched_data *q = qdisc_priv(sch);
+	struct nss_bf_class_data *cl = (struct nss_bf_class_data *)arg;
+	struct nss_if_msg nim_detach;
+	struct nss_if_msg nim_attach;
+	struct nss_qdisc *nq_new = qdisc_priv(new);
+
+	nss_qdisc_info("Grafting class %px\n", sch);
+
+	if (cl == &q->root) {
+		nss_qdisc_error("Can't graft root class %px\n", cl);
+		return -EINVAL;
+	}
+
+	if (new == NULL)
+		new = &noop_qdisc;
+
+	sch_tree_lock(sch);
+	*old = cl->qdisc;
+	sch_tree_unlock(sch);
+
+	/*
+	 * Since we initially attached a noop qdisc as child (in Linux),
+	 * we do not perform a detach in the NSS if its a noop qdisc.
+	 */
+	nss_qdisc_info("Grafting old: %px with new: %px\n", *old, new);
+	if (*old != &noop_qdisc) {
+		struct nss_qdisc *nq_old = (struct nss_qdisc *)qdisc_priv(*old);
+		nss_qdisc_info("Detaching old: %px\n", *old);
+		nim_detach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag;
+		if (nss_qdisc_node_detach(&cl->nq, nq_old, &nim_detach,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+			return -EINVAL;
+		}
+	}
+
+	/*
+	 * If the new qdisc is a noop qdisc, we do not send down an attach command
+	 * to the NSS.
+	 */
+	if (new != &noop_qdisc) {
+		nss_qdisc_info("Attaching new: %px\n", new);
+		nim_attach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag;
+		nim_attach.msg.shaper_configure.config.msg.shaper_node_config.snc.bf_group_attach.child_qos_tag = nq_new->qos_tag;
+		if (nss_qdisc_node_attach(&cl->nq, nq_new, &nim_attach,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_ATTACH) < 0) {
+			return -EINVAL;
+		}
+	}
+
+	/*
+	 * Replaced in NSS, now replace in Linux.
+	 */
+	nss_qdisc_replace(sch, new, &cl->qdisc);
+
+	nss_qdisc_info("Nssbf grafted");
+
+	return 0;
+}
+
+/*
+ * nss_bf_leaf_class()
+ *	Returns pointer to qdisc if leaf class.
+ */
+static struct Qdisc *nss_bf_leaf_class(struct Qdisc *sch, unsigned long arg)
+{
+	struct nss_bf_class_data *cl = (struct nss_bf_class_data *)arg;
+	nss_qdisc_info("bf class leaf %px\n", cl);
+
+	/*
+	 * Since all nss_bf groups are leaf nodes, we can always
+	 * return the attached qdisc.
+	 */
+	return cl->qdisc;
+}
+
+/*
+ * nss_bf_qlen_notify()
+ *	We dont maintain a live set of stats in linux, so this function is not implemented.
+ */
+static void nss_bf_qlen_notify(struct Qdisc *sch, unsigned long arg)
+{
+	nss_qdisc_info("bf qlen notify %px\n", sch);
+	/*
+	 * Gets called when qlen of child changes (Useful for deactivating)
+	 * Not useful for us here.
+	 */
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0))
+/*
+ * nss_bf_get_class()
+ *	Fetches the class pointer if provided the classid.
+ */
+static unsigned long nss_bf_get_class(struct Qdisc *sch, u32 classid)
+{
+	struct nss_bf_class_data *cl = nss_bf_find_class(classid, sch);
+
+	nss_qdisc_info("Get bf class %px - class match = %px\n", sch, cl);
+
+	if (cl != NULL)
+		atomic_add(1, &cl->nq.refcnt);
+
+	return (unsigned long)cl;
+}
+
+/*
+ * nss_bf_put_class()
+ *	Reduces reference count for this class.
+ */
+static void nss_bf_put_class(struct Qdisc *sch, unsigned long arg)
+{
+	struct nss_bf_class_data *cl = (struct nss_bf_class_data *)arg;
+	nss_qdisc_info("bf put class for %px\n", cl);
+
+	/*
+	 * We are safe to destroy the qdisc if the reference count
+	 * goes down to 0.
+	 */
+	if (nss_qdisc_atomic_sub_return(&cl->nq) == 0) {
+		nss_bf_destroy_class(sch, cl);
+	}
+}
+#else
+/*
+ * nss_bf_search_class()
+ *	Fetches the class pointer if provided the classid.
+ */
+static unsigned long nss_bf_search_class(struct Qdisc *sch, u32 classid)
+{
+	struct nss_bf_class_data *cl = nss_bf_find_class(classid, sch);
+
+	nss_qdisc_info("Get bf class %px - class match = %px\n", sch, cl);
+
+	return (unsigned long)cl;
+}
+#endif
+
+/*
+ * nss_bf_dump_class()
+ *	Dumps all configurable parameters pertaining to this class.
+ */
+static int nss_bf_dump_class(struct Qdisc *sch, unsigned long arg, struct sk_buff *skb,
+		struct tcmsg *tcm)
+{
+	struct nss_bf_class_data *cl = (struct nss_bf_class_data *)arg;
+	struct nlattr *opts;
+	struct tc_nssbf_class_qopt qopt;
+
+	nss_qdisc_info("Dumping class %px of Qdisc %px\n", cl, sch);
+
+	qopt.burst = cl->burst;
+	qopt.rate = cl->rate;
+	qopt.mtu = cl->mtu;
+	qopt.quantum = cl->quantum;
+
+	/*
+	 * All bf group nodes are root nodes. i.e. they dont
+	 * have any mode bf groups attached beneath them.
+	 */
+	tcm->tcm_parent = TC_H_ROOT;
+	tcm->tcm_handle = cl->cl_common.classid;
+	tcm->tcm_info = cl->qdisc->handle;
+
+	opts = nss_qdisc_nla_nest_start(skb, TCA_OPTIONS);
+	if (opts == NULL || nla_put(skb, TCA_NSSBF_CLASS_PARMS, sizeof(qopt), &qopt)) {
+		goto nla_put_failure;
+	}
+
+	return nla_nest_end(skb, opts);
+
+nla_put_failure:
+	nla_nest_cancel(skb, opts);
+	return -EMSGSIZE;
+}
+
+/*
+ * nss_bf_dump_class_stats()
+ *	Dumps class statistics.
+ */
+static int nss_bf_dump_class_stats(struct Qdisc *sch, unsigned long arg, struct gnet_dump *d)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)arg;
+
+	if (nss_qdisc_gnet_stats_copy_basic(sch, d, &nq->bstats) < 0 ||
+			nss_qdisc_gnet_stats_copy_queue(d, &nq->qstats) < 0) {
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_bf_walk()
+ *	Used to walk the tree.
+ */
+static void nss_bf_walk(struct Qdisc *sch, struct qdisc_walker *arg)
+{
+	struct nss_bf_sched_data *q = qdisc_priv(sch);
+	struct hlist_node *n __maybe_unused;
+	struct nss_bf_class_data *cl;
+	unsigned int i;
+
+	nss_qdisc_info("In bf walk %px\n", sch);
+	if (arg->stop)
+		return;
+
+	for (i = 0; i < q->clhash.hashsize; i++) {
+		nss_qdisc_hlist_for_each_entry(cl, n, &q->clhash.hash[i],
+				cl_common.hnode) {
+			if (arg->count < arg->skip) {
+				arg->count++;
+				continue;
+			}
+			if (arg->fn(sch, (unsigned long)cl, arg) < 0) {
+				arg->stop = 1;
+				return;
+			}
+			arg->count++;
+		}
+	}
+}
+
+/*
+ * nss_bf_change_qdisc()
+ *	Can be used to configure a nssbf qdisc.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_bf_change_qdisc(struct Qdisc *sch, struct nlattr *opt)
+#else
+static int nss_bf_change_qdisc(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+#endif
+{
+	struct nss_bf_sched_data *q = qdisc_priv(sch);
+	struct nlattr *tb[TCA_NSSBF_MAX + 1];
+	struct tc_nssbf_qopt *qopt;
+
+	/*
+	 * Since nssbf can be created with no arguments, opt might be NULL
+	 * (depending on the kernel version). This is still a valid create
+	 * request.
+	 */
+	if (opt == NULL) {
+
+		/*
+		 * If no parameter is passed, set it to 0 and continue
+		 * creating the qdisc.
+		 */
+		sch_tree_lock(sch);
+		q->defcls = 0;
+		sch_tree_unlock(sch);
+		return 0;
+	}
+
+	/*
+	 * If it is not NULL, parse to get qopt.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_bf_policy, tb, TCA_NSSBF_MAX, TCA_NSSBF_QDISC_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_bf_policy, tb, TCA_NSSBF_MAX, TCA_NSSBF_QDISC_PARMS, extack);
+#endif
+	if (!qopt) {
+		return -EINVAL;
+	}
+
+	sch_tree_lock(sch);
+	q->defcls = qopt->defcls;
+	sch_tree_unlock(sch);
+
+	/*
+	 * This information is unused in the NSS. So we do not send
+	 * a configuration message down.
+	 */
+
+	return 0;
+}
+
+/*
+ * nss_bf_reset_class()
+ *	Resets child qdisc of class to be reset.
+ */
+static void nss_bf_reset_class(struct nss_bf_class_data *cl)
+{
+	nss_qdisc_reset(cl->qdisc);
+	nss_qdisc_info("Nssbf class resetted %px\n", cl->qdisc);
+}
+
+/*
+ * nss_bf_reset_qdisc()
+ *	Resets nssbf qdisc and its classes.
+ */
+static void nss_bf_reset_qdisc(struct Qdisc *sch)
+{
+	struct nss_bf_sched_data *q = qdisc_priv(sch);
+	struct nss_bf_class_data *cl;
+	struct hlist_node *n __maybe_unused;
+	unsigned int i;
+
+	for (i = 0; i < q->clhash.hashsize; i++) {
+		nss_qdisc_hlist_for_each_entry(cl, n, &q->clhash.hash[i], cl_common.hnode)
+			nss_bf_reset_class(cl);
+	}
+
+	nss_qdisc_reset(sch);
+	nss_qdisc_info("Nssbf qdisc resetted %px\n", sch);
+}
+
+/*
+ * nss_bf_destroy_qdisc()
+ *	Call to destroy a nssbf qdisc and its associated classes.
+ */
+static void nss_bf_destroy_qdisc(struct Qdisc *sch)
+{
+	struct nss_bf_sched_data *q = qdisc_priv(sch);
+	struct hlist_node *n __maybe_unused;
+	struct hlist_node *next;
+	struct nss_bf_class_data *cl;
+	struct nss_if_msg nim;
+	unsigned int i;
+
+	/*
+	 * Destroy all the classes before the root qdisc is destroyed.
+	 */
+	for (i = 0; i < q->clhash.hashsize; i++) {
+		nss_qdisc_hlist_for_each_entry_safe(cl, n, next, &q->clhash.hash[i], cl_common.hnode) {
+
+			/*
+			 * If this is the root class, we dont have to destroy it. This will be taken
+			 * care of by the nss_bf_destroy() function.
+			 */
+			if (cl == &q->root) {
+				nss_qdisc_info("We do not detach or destroy bf class %px here since this is "
+						"the qdisc %px\n", cl, sch);
+				continue;
+			}
+
+			/*
+			 * Reduce refcnt by 1 before destroying. This is to
+			 * ensure that polling of stat stops properly.
+			 */
+			 nss_qdisc_atomic_sub(&cl->nq);
+
+			/*
+			 * Detach class before destroying it. We dont check for noop qdisc here
+			 * since we do not attach anu such at init.
+			 */
+			nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+			nim.msg.shaper_configure.config.msg.shaper_node_config.snc.bf_detach.child_qos_tag = cl->nq.qos_tag;
+			if (nss_qdisc_node_detach(&q->nq, &cl->nq, &nim,
+					NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+				nss_qdisc_error("Node detach failed for qdisc %x class %x\n",
+							cl->nq.qos_tag, q->nq.qos_tag);
+				return;
+			}
+
+			/*
+			 * Now we can destroy the class.
+			 */
+			nss_bf_destroy_class(sch, cl);
+		}
+	}
+	qdisc_class_hash_destroy(&q->clhash);
+
+	/*
+	 * Stop the polling of basic stats
+	 */
+	nss_qdisc_stop_basic_stats_polling(&q->nq);
+
+	/*
+	 * Now we can go ahead and destroy the qdisc.
+	 * Note: We dont have to detach ourself from our parent because this
+	 *	 will be taken care of by the graft call.
+	 */
+	nss_qdisc_destroy(&q->nq);
+	nss_qdisc_info("Nssbf destroyed %px\n", sch);
+}
+
+/*
+ * nss_bf_init_qdisc()
+ *	Initializes the nssbf qdisc.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_bf_init_qdisc(struct Qdisc *sch, struct nlattr *opt)
+{
+	struct netlink_ext_ack *extack = NULL;
+#else
+static int nss_bf_init_qdisc(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+{
+#endif
+	struct nss_bf_sched_data *q = qdisc_priv(sch);
+	struct nlattr *tb[TCA_NSSBF_MAX + 1];
+	struct tc_nssbf_qopt *qopt;
+	int err;
+	unsigned int accel_mode;
+
+	nss_qdisc_info("Init bf qdisc %px\n", sch);
+
+	err = qdisc_class_hash_init(&q->clhash);
+	if (err < 0) {
+		return err;
+	}
+
+	q->root.cl_common.classid = sch->handle;
+	q->root.qdisc = &noop_qdisc;
+
+	qdisc_class_hash_insert(&q->clhash, &q->root.cl_common);
+	qdisc_class_hash_grow(sch, &q->clhash);
+
+	/*
+	 * opt is NULL when no parameter is passed by user in TC.
+	 */
+	if (!opt) {
+		accel_mode = TCA_NSS_ACCEL_MODE_NSS_FW;
+	} else {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+		qopt = nss_qdisc_qopt_get(opt, nss_bf_policy, tb, TCA_NSSBF_MAX, TCA_NSSBF_QDISC_PARMS);
+#else
+		qopt = nss_qdisc_qopt_get(opt, nss_bf_policy, tb, TCA_NSSBF_MAX, TCA_NSSBF_QDISC_PARMS, extack);
+#endif
+		if (!qopt) {
+			return -EINVAL;
+		}
+		accel_mode = qopt->accel_mode;
+	}
+
+	/*
+	 * Initialize the NSSBF shaper in NSS
+	 */
+	if (nss_qdisc_init(sch, &q->nq, NSS_SHAPER_NODE_TYPE_BF, 0, accel_mode, extack) < 0) {
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("Nssbf initialized - handle %x parent %x\n", sch->handle, sch->parent);
+
+	/*
+	 * Tune nss_bf parameters.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	if (nss_bf_change_qdisc(sch, opt) < 0) {
+#else
+	if (nss_bf_change_qdisc(sch, opt, extack) < 0) {
+#endif
+		nss_qdisc_destroy(&q->nq);
+		return -EINVAL;
+	}
+
+	/*
+	 * Start the stats polling timer
+	 */
+	nss_qdisc_start_basic_stats_polling(&q->nq);
+
+	return 0;
+}
+
+/*
+ * nss_bf_dump_qdisc()
+ *	Dumps nssbf qdisc's configurable parameters.
+ */
+static int nss_bf_dump_qdisc(struct Qdisc *sch, struct sk_buff *skb)
+{
+	struct nss_bf_sched_data *q = qdisc_priv(sch);
+	struct tc_nssbf_qopt qopt;
+	struct nlattr *opts = NULL;
+
+	nss_qdisc_info("In bf dump qdisc\n");
+	qopt.defcls = q->defcls;
+	qopt.accel_mode = nss_qdisc_accel_mode_get(&q->nq);
+
+	opts = nss_qdisc_nla_nest_start(skb, TCA_OPTIONS);
+	if (!opts || nla_put(skb, TCA_NSSBF_QDISC_PARMS, sizeof(qopt), &qopt)) {
+		goto nla_put_failure;
+	}
+
+	return nla_nest_end(skb, opts);
+
+nla_put_failure:
+	nla_nest_cancel(skb, opts);
+	return -EMSGSIZE;
+}
+
+/*
+ * nss_bf_enqueue()
+ *	Enqueues a skb to nssbf qdisc.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+static int nss_bf_enqueue(struct sk_buff *skb, struct Qdisc *sch)
+#else
+static int nss_bf_enqueue(struct sk_buff *skb, struct Qdisc *sch,
+				struct sk_buff **to_free)
+#endif
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	return nss_qdisc_enqueue(skb, sch);
+#else
+	return nss_qdisc_enqueue(skb, sch, to_free);
+#endif
+}
+
+/*
+ * nss_bf_dequeue()
+ *	Dequeues a skb to nssbf qdisc.
+ */
+static struct sk_buff *nss_bf_dequeue(struct Qdisc *sch)
+{
+	return nss_qdisc_dequeue(sch);
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+/*
+ * nss_bf_drop()
+ *	Drops a single skb from linux queue, if not empty.
+ *
+ * Does not drop packets that are queued in the NSS.
+ */
+static unsigned int nss_bf_drop(struct Qdisc *sch)
+{
+	printk("In bf drop\n");
+	return nss_qdisc_drop(sch);
+}
+#endif
+
+/*
+ * Registration structure for nssbf class
+ */
+const struct Qdisc_class_ops nss_bf_class_ops = {
+	.change		= nss_bf_change_class,
+	.delete		= nss_bf_delete_class,
+	.graft		= nss_bf_graft_class,
+	.leaf		= nss_bf_leaf_class,
+	.qlen_notify	= nss_bf_qlen_notify,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0))
+	.get		= nss_bf_get_class,
+	.put		= nss_bf_put_class,
+#else
+	.find		= nss_bf_search_class,
+#endif
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	.tcf_chain	= nss_qdisc_tcf_chain,
+#else
+	.tcf_block      = nss_qdisc_tcf_block,
+#endif
+	.bind_tcf	= nss_qdisc_tcf_bind,
+	.unbind_tcf	= nss_qdisc_tcf_unbind,
+	.dump		= nss_bf_dump_class,
+	.dump_stats	= nss_bf_dump_class_stats,
+	.walk		= nss_bf_walk
+};
+
+/*
+ * Registration structure for nssbf qdisc
+ */
+struct Qdisc_ops nss_bf_qdisc_ops __read_mostly = {
+	.id		= "nssbf",
+	.init		= nss_bf_init_qdisc,
+	.change		= nss_bf_change_qdisc,
+	.reset		= nss_bf_reset_qdisc,
+	.destroy	= nss_bf_destroy_qdisc,
+	.dump		= nss_bf_dump_qdisc,
+	.enqueue	= nss_bf_enqueue,
+	.dequeue	= nss_bf_dequeue,
+	.peek		= qdisc_peek_dequeued,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	.drop		= nss_bf_drop,
+#endif
+	.cl_ops		= &nss_bf_class_ops,
+	.priv_size	= sizeof(struct nss_bf_sched_data),
+	.owner		= THIS_MODULE
+};
diff --git a/qca-nss-clients/nss_qdisc/nss_bf.h b/qca-nss-clients/nss_qdisc/nss_bf.h
new file mode 100644
index 0000000..d7da15c
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_bf.h
@@ -0,0 +1,17 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern struct Qdisc_ops nss_bf_qdisc_ops;
diff --git a/qca-nss-clients/nss_qdisc/nss_blackhole.c b/qca-nss-clients/nss_qdisc/nss_blackhole.c
new file mode 100644
index 0000000..fb737df
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_blackhole.c
@@ -0,0 +1,301 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, 2016-2017, 2020,  The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_qdisc.h"
+
+/*
+ * nss_blackhole private qdisc structure
+ */
+struct nss_blackhole_sched_data {
+	struct nss_qdisc nq;	/* Common base class for all nss qdiscs */
+	u8 set_default;		/* Flag to set qdisc as default qdisc for enqueue */
+};
+
+/*
+ * nss_blackhole policy structure
+ */
+static struct nla_policy nss_blackhole_policy[TCA_NSSBLACKHOLE_MAX + 1] = {
+	[TCA_NSSBLACKHOLE_PARMS] = { .len = sizeof(struct tc_nssblackhole_qopt) },
+};
+
+/*
+ * nss_blackhole_enqueue()
+ *	Enqueue API for nss blackhole qdisc.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+static int nss_blackhole_enqueue(struct sk_buff *skb, struct Qdisc *sch)
+#else
+static int nss_blackhole_enqueue(struct sk_buff *skb, struct Qdisc *sch,
+				struct sk_buff **to_free)
+#endif
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	return nss_qdisc_enqueue(skb, sch);
+#else
+	return nss_qdisc_enqueue(skb, sch, to_free);
+#endif
+}
+
+/*
+ * nss_blackhole_dequeue()
+ * 	Dequeue API for nss blackhole qdisc.
+ */
+static struct sk_buff *nss_blackhole_dequeue(struct Qdisc *sch)
+{
+	return nss_qdisc_dequeue(sch);
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+/*
+ * nss_blackhole_drop()
+ *	The following function drops a packet from HLOS queue.
+ *
+ * Note, this does not drop packets from queues in the NSS. We do not support that.
+ */
+static unsigned int nss_blackhole_drop(struct Qdisc *sch)
+{
+	nss_qdisc_info("qdisc %x dropping\n", sch->handle);
+	return nss_qdisc_drop(sch);
+}
+#endif
+
+/*
+ * nss_blackhole_reset()
+ *	Resets the nss blackhole qdisc.
+ */
+static void nss_blackhole_reset(struct Qdisc *sch)
+{
+	nss_qdisc_info("qdisc %x resetting\n", sch->handle);
+	nss_qdisc_reset(sch);
+}
+
+/*
+ * nss_blackhole_destroy()
+ *	Destroys the nss blackhole qdisc.
+ */
+static void nss_blackhole_destroy(struct Qdisc *sch)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)qdisc_priv(sch);
+
+	/*
+	 * Stop the polling of basic stats
+	 */
+	nss_qdisc_stop_basic_stats_polling(nq);
+
+	nss_qdisc_info("destroying qdisc %x\n", sch->handle);
+	nss_qdisc_destroy(nq);
+}
+
+/*
+ * nss_blackhole_change()
+ *	Function call used to configure the parameters of the nss blackhole qdisc.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_blackhole_change(struct Qdisc *sch, struct nlattr *opt)
+#else
+static int nss_blackhole_change(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+#endif
+{
+	struct nss_blackhole_sched_data *q;
+	struct nlattr *tb[TCA_NSSBLACKHOLE_MAX + 1];
+	struct tc_nssblackhole_qopt *qopt;
+	struct nss_if_msg nim;
+
+	if (!opt) {
+		return 0;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_blackhole_policy, tb, TCA_NSSBLACKHOLE_MAX, TCA_NSSBLACKHOLE_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_blackhole_policy, tb, TCA_NSSBLACKHOLE_MAX, TCA_NSSBLACKHOLE_PARMS, extack);
+#endif
+	if (!qopt) {
+		return -EINVAL;
+	}
+
+	/*
+	 * Required for basic stats display
+	 */
+	sch->limit = 0;
+
+	q = qdisc_priv(sch);
+	q->set_default = qopt->set_default;
+	nss_qdisc_info("qdisc set_default = %u\n", qopt->set_default);
+
+	/*
+	 * Underneath nss_bloackhole uses a fifo in the NSS. This is why we are sending down a configuration
+	 * message to a fifo node. There are no blackhole shaper in the NSS as yet.
+	 *
+	 * Note: We simply set the limit of fifo to zero to get the blackhole behavior.
+	 */
+	nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.fifo_param.limit = 0;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.fifo_param.drop_mode = NSS_SHAPER_FIFO_DROP_MODE_TAIL;
+	if (nss_qdisc_configure(&q->nq, &nim, NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_CHANGE_PARAM) < 0) {
+		nss_qdisc_error("qdisc %x configuration failed\n", sch->handle);
+		return -EINVAL;
+	}
+
+	/*
+	 * There is nothing we need to do if the qdisc is not
+	 * set as default qdisc.
+	 */
+	if (q->set_default == 0) {
+		return 0;
+	}
+
+	/*
+	 * Set this qdisc to be the default qdisc for enqueuing packets.
+	 */
+	if (nss_qdisc_set_default(&q->nq) < 0) {
+		nss_qdisc_error("qdisc %x set_default failed\n", sch->handle);
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("qdisc %x set as default\n", q->nq.qos_tag);
+	return 0;
+}
+
+/*
+ * nss_blackhole_init()
+ *	Initializes a nss blackhole qdisc.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_blackhole_init(struct Qdisc *sch, struct nlattr *opt)
+{
+	struct netlink_ext_ack *extack = NULL;
+#else
+static int nss_blackhole_init(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+{
+#endif
+	struct nss_qdisc *nq = qdisc_priv(sch);
+	struct nlattr *tb[TCA_NSSBLACKHOLE_MAX + 1];
+	struct tc_nssblackhole_qopt *qopt;
+	unsigned int accel_mode;
+
+	/*
+	 * opt is NULL when no parameter is passed to TC.
+	 */
+	if (!opt) {
+		accel_mode = TCA_NSS_ACCEL_MODE_PPE;
+	} else {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+		qopt = nss_qdisc_qopt_get(opt, nss_blackhole_policy, tb, TCA_NSSBLACKHOLE_MAX, TCA_NSSBLACKHOLE_PARMS);
+#else
+		qopt = nss_qdisc_qopt_get(opt, nss_blackhole_policy, tb, TCA_NSSBLACKHOLE_MAX, TCA_NSSBLACKHOLE_PARMS, extack);
+#endif
+		if (!qopt) {
+			return -EINVAL;
+		}
+		accel_mode = qopt->accel_mode;
+	}
+
+	nss_qdisc_info("qdisc %x initializing\n", sch->handle);
+	nss_blackhole_reset(sch);
+
+	if (nss_qdisc_init(sch, nq, NSS_SHAPER_NODE_TYPE_FIFO, 0, accel_mode, extack) < 0)
+	{
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("qdisc %x initialized with parent %x\n", sch->handle, sch->parent);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	if (nss_blackhole_change(sch, opt) < 0) {
+#else
+	if (nss_blackhole_change(sch, opt, extack) < 0) {
+#endif
+		nss_qdisc_destroy(nq);
+		return -EINVAL;
+	}
+
+	/*
+	 * Start the stats polling timer
+	 */
+	nss_qdisc_start_basic_stats_polling(nq);
+
+	return 0;
+}
+
+/*
+ * nss_blackhole_dump()
+ *	Dumps qdisc parameters for nss blackhole.
+ */
+static int nss_blackhole_dump(struct Qdisc *sch, struct sk_buff *skb)
+{
+	struct nss_blackhole_sched_data *q;
+	struct nlattr *opts = NULL;
+	struct tc_nssblackhole_qopt opt;
+
+	nss_qdisc_info("qdisc %x dumping!\n", sch->handle);
+
+	q = qdisc_priv(sch);
+	if (q == NULL) {
+		return -1;
+	}
+
+	opt.set_default = q->set_default;
+	opt.accel_mode = nss_qdisc_accel_mode_get(&q->nq);
+
+	opts = nss_qdisc_nla_nest_start(skb, TCA_OPTIONS);
+	if (opts == NULL) {
+		goto nla_put_failure;
+	}
+	if (nla_put(skb, TCA_NSSBLACKHOLE_PARMS, sizeof(opt), &opt))
+		goto nla_put_failure;
+
+	return nla_nest_end(skb, opts);
+
+nla_put_failure:
+	nla_nest_cancel(skb, opts);
+	return -EMSGSIZE;
+}
+
+/*
+ * nss_blackhole_peek()
+ *	Peeks the first packet in queue for this qdisc.
+ *
+ * Note: This just peeks at the first packet in what is present in HLOS. This does not
+ * perform an actual peak into the queue in the NSS. Given the async delay between
+ * the processors, there is less use in implementing this function.
+ */
+static struct sk_buff *nss_blackhole_peek(struct Qdisc *sch)
+{
+	nss_qdisc_info("qdisc %x peeked\n", sch->handle);
+	return nss_qdisc_peek(sch);
+}
+
+/*
+ * Registration structure for nss blackhole qdisc
+ */
+struct Qdisc_ops nss_blackhole_qdisc_ops __read_mostly = {
+	.id		=	"nssblackhole",
+	.priv_size	=	sizeof(struct nss_blackhole_sched_data),
+	.enqueue	=	nss_blackhole_enqueue,
+	.dequeue	=	nss_blackhole_dequeue,
+	.peek		=	nss_blackhole_peek,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	.drop		=	nss_blackhole_drop,
+#endif
+	.init		=	nss_blackhole_init,
+	.reset		=	nss_blackhole_reset,
+	.destroy	=	nss_blackhole_destroy,
+	.change		=	nss_blackhole_change,
+	.dump		=	nss_blackhole_dump,
+	.owner		=	THIS_MODULE,
+};
diff --git a/qca-nss-clients/nss_qdisc/nss_blackhole.h b/qca-nss-clients/nss_qdisc/nss_blackhole.h
new file mode 100644
index 0000000..58dce8b
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_blackhole.h
@@ -0,0 +1,17 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern struct Qdisc_ops nss_blackhole_qdisc_ops;
diff --git a/qca-nss-clients/nss_qdisc/nss_codel.c b/qca-nss-clients/nss_qdisc/nss_codel.c
new file mode 100644
index 0000000..226d706
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_codel.c
@@ -0,0 +1,583 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, 2016-2018, 2020,  The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_qdisc.h"
+#include "nss_codel.h"
+
+/*
+ * Default number of flow queues used (in fq_codel) if user doesn't specify a value.
+ */
+#define NSS_CODEL_DEFAULT_FQ_COUNT 1024
+
+/*
+ * Codel stats structure.
+ */
+struct nss_codel_stats_sq {
+	u32 peak_queue_delay;	/* Peak delay experienced by a dequeued packet */
+	u32 peak_drop_delay;	/* Peak delay experienced by a packet that is dropped */
+};
+
+/*
+ * Codel floq queue stats structure.
+ */
+struct nss_codel_stats_fq {
+        u64 ecn_mark_cnt;	/* Number of packets marked with ECN */
+        u64 new_flow_cnt;	/* Total number of new flows seen. */
+	u64 drop_overlimit;	/* Number of overlimit drops */
+	u32 new_flows_len;	/* Current number of new flows */
+	u32 old_flows_len;	/* Current number of old flows */
+	u32 maxpacket;		/* Largest packet seen so far */
+};
+
+/*
+ * Codel instance structure.
+ */
+struct nss_codel_sched_data {
+	struct nss_qdisc nq;	/* Common base class for all nss qdiscs */
+	u32 target;		/* Acceptable value of queue delay */
+	u32 limit;		/* Length of queue */
+	u32 interval;		/* Monitoring interval */
+	u32 flows;		/* Number of flow buckets */
+	u32 quantum;		/* Weight (in bytes) used for DRR of flow buckets */
+	unsigned long flow_queue_mem;
+				/* Pointer to flow queue memory */
+	dma_addr_t dma_mapped_mem ;
+				/* Mapped memory address */
+	u32 flow_queue_sz;	/* Size of a flow queue in firmware (bytes) */
+	u8 ecn;			/* 0 - disable ECN, 1 - enable ECN */
+	u8 set_default;		/* Flag to set qdisc as default qdisc for enqueue */
+	struct nss_codel_stats_sq sq_stats;
+				/* Contains single queue codel stats */
+	struct nss_codel_stats_fq fq_stats;
+				/* Contains flow queue codel stats */
+};
+
+/*
+ * Codel netlink policy structure.
+ */
+static struct nla_policy nss_codel_policy[TCA_NSSCODEL_MAX + 1] = {
+	[TCA_NSSCODEL_PARMS] = { .len = sizeof(struct tc_nsscodel_qopt) },
+};
+
+/*
+ * nss_codel_enqueue()
+ *	Enqueue a packet into nss_codel queue in NSS firmware (bounce).
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+static int nss_codel_enqueue(struct sk_buff *skb, struct Qdisc *sch)
+#else
+static int nss_codel_enqueue(struct sk_buff *skb, struct Qdisc *sch,
+				struct sk_buff **to_free)
+#endif
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	return nss_qdisc_enqueue(skb, sch);
+#else
+	return nss_qdisc_enqueue(skb, sch, to_free);
+#endif
+}
+
+/*
+ * nss_codel_dequeue()
+ *	Dequeue a packet from the bounce complete queue (use when bouncing packets).
+ */
+static struct sk_buff *nss_codel_dequeue(struct Qdisc *sch)
+{
+	return nss_qdisc_dequeue(sch);
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+/*
+ * nss_codel_drop()
+ *	Drops a packet from the bounce complete queue.
+ *
+ * Note: this does not drop packets from the NSS queues.
+ */
+static unsigned int nss_codel_drop(struct Qdisc *sch)
+{
+	return nss_qdisc_drop(sch);
+}
+#endif
+
+/*
+ * nss_codel_reset()
+ *	Resets nss_codel qdisc.
+ */
+static void nss_codel_reset(struct Qdisc *sch)
+{
+	nss_qdisc_info("nss_codel resetting!");
+	nss_qdisc_reset(sch);
+}
+
+/*
+ * nss_codel_flow_queues_free()
+ *	Free memory allocated for the flow queues (used in fq_codel mode).
+ */
+static void nss_codel_flow_queues_free(struct nss_codel_sched_data *q)
+{
+	if (!q->flow_queue_mem) {
+		return;
+	}
+
+	/*
+	 * If DMA mapping was successful, unmap it.
+	 */
+	if (!dma_mapping_error(nss_shaper_get_dev(), q->dma_mapped_mem)) {
+		nss_qdisc_trace("Unmapping flow queue memory\n");
+		dma_unmap_single(nss_shaper_get_dev(), q->dma_mapped_mem, q->flow_queue_sz * q->flows, DMA_FROM_DEVICE);
+	}
+
+	free_pages(q->flow_queue_mem, get_order(q->flow_queue_sz * q->flows));
+	q->flow_queue_mem = 0;
+	q->dma_mapped_mem = (dma_addr_t)0;
+
+	nss_qdisc_trace("Flow queues freed\n");
+}
+
+/*
+ * nss_codel_destroy()
+ *	Destroys the nss_codel qdisc.
+ */
+static void nss_codel_destroy(struct Qdisc *sch)
+{
+	struct nss_codel_sched_data *q = qdisc_priv(sch);
+
+	/*
+	 * Stop the polling of basic stats
+	 */
+	nss_qdisc_stop_basic_stats_polling(&q->nq);
+	nss_qdisc_destroy(&q->nq);
+	nss_codel_flow_queues_free(q);
+	nss_qdisc_info("nss_codel destroyed");
+}
+
+/*
+ * nss_codel_stats_callback()
+ *	Invoked by the nss_qdisc infrastructure on receiving stats update from firmware.
+ */
+static void nss_codel_stats_callback(struct nss_qdisc *nq, struct nss_shaper_node_stats_response *response)
+{
+	struct nss_codel_sched_data *q = (struct nss_codel_sched_data *)nq;
+
+	if (!q->flows) {
+		q->sq_stats.peak_queue_delay = response->per_sn_stats.codel.sq.packet_latency_peak_msec_dequeued;
+		q->sq_stats.peak_drop_delay = response->per_sn_stats.codel.sq.packet_latency_peak_msec_dropped;
+		return;
+	}
+
+	q->fq_stats.new_flows_len = response->per_sn_stats.codel.fq.new_flows_len;
+	q->fq_stats.old_flows_len = response->per_sn_stats.codel.fq.old_flows_len;
+	q->fq_stats.maxpacket = response->per_sn_stats.codel.fq.maxpacket;
+	q->fq_stats.drop_overlimit += response->sn_stats.delta.enqueued_packets_dropped;
+	q->fq_stats.ecn_mark_cnt += response->per_sn_stats.codel.fq.delta.ecn_mark_cnt;
+	q->fq_stats.new_flow_cnt += response->per_sn_stats.codel.fq.delta.new_flow_cnt;
+}
+
+/*
+ * nss_codel_configure_callback()
+ *	Invoked by the nss_qdisc infrastructure on receiving a response for a configure msg.
+ */
+static void nss_codel_configure_callback(struct nss_qdisc *nq, struct nss_shaper_configure *nsc)
+{
+	struct nss_codel_sched_data *q;
+
+	/*
+	 * Currently only care about firmware response for the memory size
+	 * get message. The rest we ignore.
+	 */
+	nss_qdisc_trace("Callback for request %d\n", nsc->request_type);
+	if (nsc->request_type != NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_MEM_REQ) {
+		return;
+	}
+
+	if (nsc->response_type != NSS_SHAPER_RESPONSE_TYPE_SUCCESS) {
+		return;
+	}
+
+	q = (struct nss_codel_sched_data *)nq;
+	q->flow_queue_sz = nsc->msg.shaper_node_config.snc.codel_mem_req.mem_req;
+	nss_qdisc_info("Flow queue size %u bytes\n", q->flow_queue_sz);
+}
+
+/*
+ * nss_codel_mem_sz_get()
+ *	Sends a message to nss_codel queue (in FW) requesting per flow-queue mem size.
+ *
+ * The response for this message will invoke the nss_codel_configure_callback() API.
+ */
+static int nss_codel_mem_sz_get(struct Qdisc *sch, struct tc_nsscodel_qopt *qopt)
+{
+	struct nss_if_msg nim;
+	struct nss_qdisc *nq = qdisc_priv(sch);
+
+	/*
+	 * No memory allocation needed for codel when operating in single
+	 * queue mode. This is needed only for flow-queue mode.
+	 */
+	if (!qopt->flows) {
+		return 0;
+	}
+
+	nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = nq->qos_tag;
+	if (nss_qdisc_configure(nq, &nim,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_MEM_REQ) < 0) {
+		nss_qdisc_warning("Memory size get failed\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_codel_change()
+ *	Used to configure the nss_codel queue in NSS firmware.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_codel_change(struct Qdisc *sch, struct nlattr *opt)
+#else
+static int nss_codel_change(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+#endif
+{
+	struct nss_codel_sched_data *q = qdisc_priv(sch);
+	struct nlattr *tb[TCA_NSSCODEL_MAX + 1];
+	struct tc_nsscodel_qopt *qopt;
+	struct nss_if_msg nim;
+	struct net_device *dev = qdisc_dev(sch);
+	uint32_t order, sz = 0;
+	bool is_fq_codel = (sch->ops == &nss_fq_codel_qdisc_ops);
+	struct nss_shaper_node_config *config;
+	bool free_flow_queue = true;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_codel_policy, tb, TCA_NSSCODEL_MAX, TCA_NSSCODEL_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_codel_policy, tb, TCA_NSSCODEL_MAX, TCA_NSSCODEL_PARMS, extack);
+#endif
+	if (!qopt) {
+		return -EINVAL;
+	}
+
+	if (!qopt->target || !qopt->interval) {
+		nss_qdisc_error("nss_codel requires a non-zero value for target "
+				"and interval\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * If flow queues have already been allocated, then ensure the user does not
+	 * attempt to change the number of flows in a subsequent change command.
+	 */
+	if (q->flow_queue_mem) {
+		if (q->flows != qopt->flows) {
+			nss_qdisc_warning("Change of flow queue count not allowed");
+			return -EINVAL;
+		}
+
+		/*
+		 * Since the flow queue is already allocated, we should not free
+		 * it if this update fails. The expectation is that the queue
+		 * should continue to operate in its current configuration.
+		 */
+		free_flow_queue = false;
+	}
+
+	if (!qopt->limit) {
+		qopt->limit = dev->tx_queue_len ? : 1;
+	}
+
+	q->target = qopt->target;
+	q->limit = qopt->limit;
+	q->interval = qopt->interval;
+	q->quantum = qopt->quantum;
+	q->flows = qopt->flows;
+	q->ecn = qopt->ecn;
+	q->set_default = qopt->set_default;
+
+	/*
+	 * Required for basic stats display
+	 */
+	sch->limit = qopt->limit;
+
+	nss_qdisc_info("Target:%u Limit:%u Interval:%u set_default = %u\n",
+		q->target, q->limit, q->interval, qopt->set_default);
+
+	/*
+	 * Allocate memory for the flow queues if it is nssfq_codel and memory
+	 * has not been allocated previously (i.e. init time).
+	 */
+	if (is_fq_codel && !q->flow_queue_mem) {
+		/*
+		 * Use the default flow queue count if value is not speficied by user.
+		 */
+		if (!q->flows) {
+			q->flows = NSS_CODEL_DEFAULT_FQ_COUNT;
+		}
+
+		sz = q->flow_queue_sz * q->flows;
+		order = get_order(sz);
+
+		nss_qdisc_trace("Allocating %u bytes (%u pages) for flow qeueue\n", sz, 1 << order);
+
+		nss_qdisc_info("Flows:%u Quantum:%u Ecn:%u\n",
+			q->flows, q->quantum, q->ecn);
+
+		q->flow_queue_mem = __get_free_pages(GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO, order);
+		if (!q->flow_queue_mem) {
+			nss_qdisc_warning("Failed to allocated flow queue memory\n");
+			return -ENOMEM;
+		}
+
+		q->dma_mapped_mem = dma_map_single(nss_shaper_get_dev(), (void *)q->flow_queue_mem, sz, DMA_TO_DEVICE);
+		if(unlikely(dma_mapping_error(nss_shaper_get_dev(), q->dma_mapped_mem))) {
+			nss_qdisc_warning("DMA map failed for virtual address = %lu\n", q->flow_queue_mem);
+			nss_codel_flow_queues_free(q);
+			return -ENOMEM;
+		}
+		nss_qdisc_trace("Successfully allocated memory for flow queue\n");
+	}
+
+	/*
+	 * Target and interval time needs to be provided in milliseconds
+	 * (tc provides us the time in mircoseconds and therefore we divide by 1000)
+	 */
+	config = &nim.msg.shaper_configure.config.msg.shaper_node_config;
+	config->snc.codel_param.cap.interval = q->interval / 1000;
+	config->snc.codel_param.cap.target = q->target / 1000;
+	config->qos_tag = q->nq.qos_tag;
+	config->snc.codel_param.qlen_max = q->limit;
+	config->snc.codel_param.cap.mtu = psched_mtu(dev);
+	config->snc.codel_param.quantum = q->quantum;
+	config->snc.codel_param.flows = q->flows;
+	config->snc.codel_param.flows_mem = (uint32_t)q->dma_mapped_mem;
+	config->snc.codel_param.flows_mem_sz = sz;
+	config->snc.codel_param.ecn = q->ecn;
+	nss_qdisc_info("MTU size of interface %s is %u bytes\n",
+			dev->name, config->snc.codel_param.cap.mtu);
+
+	if (nss_qdisc_configure(&q->nq, &nim,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_CHANGE_PARAM) < 0) {
+		goto fail;
+	}
+
+	/*
+	 * There is nothing we need to do if the qdisc is not
+	 * set as default qdisc.
+	 */
+	if (!q->set_default) {
+		return 0;
+	}
+
+	/*
+	 * Set this qdisc to be the default qdisc for enqueuing packets.
+	 */
+	if (nss_qdisc_set_default(&q->nq) < 0) {
+		goto fail;
+	}
+
+	return 0;
+
+fail:
+	if (free_flow_queue) {
+		nss_codel_flow_queues_free(q);
+	}
+
+	return -EINVAL;
+}
+
+/*
+ * nss_codel_init()
+ *	Initializes the nss_codel qdisc.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_codel_init(struct Qdisc *sch, struct nlattr *opt)
+{
+	struct netlink_ext_ack *extack = NULL;
+#else
+static int nss_codel_init(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+{
+#endif
+	struct nss_qdisc *nq = qdisc_priv(sch);
+	struct nlattr *tb[TCA_NSSCODEL_MAX + 1];
+	struct tc_nsscodel_qopt *qopt;
+
+	if (!opt) {
+		return -EINVAL;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_codel_policy, tb, TCA_NSSCODEL_MAX, TCA_NSSCODEL_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_codel_policy, tb, TCA_NSSCODEL_MAX, TCA_NSSCODEL_PARMS, extack);
+#endif
+	if (!qopt) {
+		return -EINVAL;
+	}
+
+	if (qopt->accel_mode != TCA_NSS_ACCEL_MODE_NSS_FW) {
+		nss_qdisc_warning("NSS codel supports only offload mode %d", TCA_NSS_ACCEL_MODE_NSS_FW);
+		return -EINVAL;
+	}
+
+	nss_codel_reset(sch);
+	nss_qdisc_register_configure_callback(nq, nss_codel_configure_callback);
+	nss_qdisc_register_stats_callback(nq, nss_codel_stats_callback);
+
+	if (nss_qdisc_init(sch, nq, NSS_SHAPER_NODE_TYPE_CODEL, 0, qopt->accel_mode, extack) < 0)
+	{
+		return -EINVAL;
+	}
+
+	if (nss_codel_mem_sz_get(sch, qopt) < 0) {
+		return -EINVAL;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	if (nss_codel_change(sch, opt) < 0) {
+#else
+	if (nss_codel_change(sch, opt, extack) < 0) {
+#endif
+		nss_qdisc_destroy(nq);
+		return -EINVAL;
+	}
+
+	/*
+	 * Start the stats polling timer
+	 */
+	nss_qdisc_start_basic_stats_polling(nq);
+
+	return 0;
+}
+
+/*
+ * nss_codel_dump()
+ *	Dumps out the nss_codel configuration parameters.
+ */
+static int nss_codel_dump(struct Qdisc *sch, struct sk_buff *skb)
+{
+	struct nss_codel_sched_data *q;
+	struct nlattr *opts = NULL;
+	struct tc_nsscodel_qopt opt;
+
+	nss_qdisc_info("NssCodel Dumping!");
+
+	q = qdisc_priv(sch);
+	if (q == NULL) {
+		return -1;
+	}
+
+	opt.target = q->target;
+	opt.limit = q->limit;
+	opt.interval = q->interval;
+	opt.set_default = q->set_default;
+	opt.accel_mode = nss_qdisc_accel_mode_get(&q->nq);
+	opt.quantum = q->quantum;
+	opt.flows = q->flows;
+	opt.ecn = q->ecn;
+
+	opts = nss_qdisc_nla_nest_start(skb, TCA_OPTIONS);
+	if (opts == NULL) {
+		goto nla_put_failure;
+	}
+
+	if (nla_put(skb, TCA_NSSCODEL_PARMS, sizeof(opt), &opt)) {
+		goto nla_put_failure;
+	}
+
+	return nla_nest_end(skb, opts);
+
+nla_put_failure:
+	nla_nest_cancel(skb, opts);
+	return -EMSGSIZE;
+}
+
+/*
+ * nss_codel_dump_stats()
+ *	Dumps out the nss_codel statistics.
+ */
+static int nss_codel_dump_stats(struct Qdisc *sch, struct gnet_dump *d)
+{
+	struct nss_codel_sched_data *q = qdisc_priv(sch);
+	struct tc_nssfq_codel_xstats fqcst;
+	struct tc_nsscodel_xstats cst;
+
+	if (!q->flows) {
+		cst.peak_queue_delay = q->sq_stats.peak_queue_delay;
+		cst.peak_drop_delay = q->sq_stats.peak_drop_delay;
+		return gnet_stats_copy_app(d, &cst, sizeof(cst));
+	}
+
+	fqcst.new_flow_count = q->fq_stats.new_flow_cnt;
+	fqcst.new_flows_len = q->fq_stats.new_flows_len;
+	fqcst.old_flows_len = q->fq_stats.old_flows_len;
+	fqcst.ecn_mark = q->fq_stats.ecn_mark_cnt;
+	fqcst.drop_overlimit = q->fq_stats.drop_overlimit;
+	fqcst.maxpacket = q->fq_stats.maxpacket;
+	return gnet_stats_copy_app(d, &fqcst, sizeof(fqcst));
+}
+
+/*
+ * nss_codel_peek()
+ *	Peeks into the first sk_buff in the bounce complete queue.
+ */
+static struct sk_buff *nss_codel_peek(struct Qdisc *sch)
+{
+	nss_qdisc_info("Nsscodel Peeking");
+	return nss_qdisc_peek(sch);
+}
+
+/*
+ * nss_codel ops parameters.
+ */
+struct Qdisc_ops nss_codel_qdisc_ops __read_mostly = {
+	.id		=	"nsscodel",
+	.priv_size	=	sizeof(struct nss_codel_sched_data),
+	.enqueue	=	nss_codel_enqueue,
+	.dequeue	=	nss_codel_dequeue,
+	.peek		=	nss_codel_peek,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	.drop		=	nss_codel_drop,
+#endif
+	.init		=	nss_codel_init,
+	.reset		=	nss_codel_reset,
+	.destroy	=	nss_codel_destroy,
+	.change		=	nss_codel_change,
+	.dump		=	nss_codel_dump,
+	.dump_stats	=	nss_codel_dump_stats,
+	.owner		=	THIS_MODULE,
+};
+
+/*
+ * nss_fq_codel ops parameters.
+ */
+struct Qdisc_ops nss_fq_codel_qdisc_ops __read_mostly = {
+	.id		=	"nssfq_codel",
+	.priv_size	=	sizeof(struct nss_codel_sched_data),
+	.enqueue	=	nss_codel_enqueue,
+	.dequeue	=	nss_codel_dequeue,
+	.peek		=	nss_codel_peek,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	.drop		=	nss_codel_drop,
+#endif
+	.init		=	nss_codel_init,
+	.reset		=	nss_codel_reset,
+	.destroy	=	nss_codel_destroy,
+	.change		=	nss_codel_change,
+	.dump		=	nss_codel_dump,
+	.dump_stats	=	nss_codel_dump_stats,
+	.owner		=	THIS_MODULE,
+};
diff --git a/qca-nss-clients/nss_qdisc/nss_codel.h b/qca-nss-clients/nss_qdisc/nss_codel.h
new file mode 100644
index 0000000..6534f78
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_codel.h
@@ -0,0 +1,18 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, 2018 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern struct Qdisc_ops nss_codel_qdisc_ops;
+extern struct Qdisc_ops nss_fq_codel_qdisc_ops;
diff --git a/qca-nss-clients/nss_qdisc/nss_fifo.c b/qca-nss-clients/nss_qdisc/nss_fifo.c
new file mode 100644
index 0000000..a5d2705
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_fifo.c
@@ -0,0 +1,379 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, 2016-2017, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_qdisc.h"
+#include "nss_fifo.h"
+
+struct nss_fifo_sched_data {
+	struct nss_qdisc nq;	/* Common base class for all nss qdiscs */
+	u32 limit;		/* Queue length in packets */
+				/* TODO: Support for queue length in bytes */
+	u8 set_default;		/* Flag to set qdisc as default qdisc for enqueue */
+	bool is_bfifo;		/* Flag to identify bfifo or pfifo */
+};
+
+static struct nla_policy nss_fifo_policy[TCA_NSSFIFO_MAX + 1] = {
+	[TCA_NSSFIFO_PARMS] = { .len = sizeof(struct tc_nssfifo_qopt) },
+};
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+static int nss_fifo_enqueue(struct sk_buff *skb, struct Qdisc *sch)
+#else
+static int nss_fifo_enqueue(struct sk_buff *skb, struct Qdisc *sch,
+				struct sk_buff **to_free)
+#endif
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	return nss_qdisc_enqueue(skb, sch);
+#else
+	return nss_qdisc_enqueue(skb, sch, to_free);
+#endif
+}
+
+static struct sk_buff *nss_fifo_dequeue(struct Qdisc *sch)
+{
+	return nss_qdisc_dequeue(sch);
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+static unsigned int nss_fifo_drop(struct Qdisc *sch)
+{
+	nss_qdisc_info("nss_fifo dropping");
+	return nss_qdisc_drop(sch);
+}
+#endif
+
+static void nss_fifo_reset(struct Qdisc *sch)
+{
+	nss_qdisc_info("nss_fifo resetting!");
+	nss_qdisc_reset(sch);
+}
+
+static void nss_fifo_destroy(struct Qdisc *sch)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)qdisc_priv(sch);
+
+	/*
+	 * Stop the polling of basic stats
+	 */
+	nss_qdisc_stop_basic_stats_polling(nq);
+
+	nss_qdisc_destroy(nq);
+	nss_qdisc_info("nss_fifo destroyed");
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_fifo_params_validate_and_save(struct Qdisc *sch, struct nlattr *opt)
+#else
+static int nss_fifo_params_validate_and_save(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+#endif
+{
+	struct nlattr *tb[TCA_NSSFIFO_MAX + 1];
+	struct tc_nssfifo_qopt *qopt;
+	struct nss_fifo_sched_data *q = qdisc_priv(sch);
+	bool is_bfifo = (sch->ops == &nss_bfifo_qdisc_ops);
+
+	if (!opt) {
+		return -EINVAL;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_fifo_policy, tb, TCA_NSSFIFO_MAX, TCA_NSSFIFO_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_fifo_policy, tb, TCA_NSSFIFO_MAX, TCA_NSSFIFO_PARMS, extack);
+#endif
+	if (!qopt) {
+		nss_qdisc_warning("Invalid input to fifo %x", sch->handle);
+		return -EINVAL;
+	}
+
+	if (!qopt->limit) {
+		qopt->limit = qdisc_dev(sch)->tx_queue_len ? : 1;
+
+		if (is_bfifo) {
+			qopt->limit *= psched_mtu(qdisc_dev(sch));
+		}
+	}
+
+	/*
+	 * Required for basic stats display
+	 */
+	sch->limit = qopt->limit;
+	q->limit = qopt->limit;
+	q->set_default = qopt->set_default;
+	q->is_bfifo = is_bfifo;
+
+	nss_qdisc_info("limit:%u set_default:%u\n", qopt->limit, qopt->set_default);
+	return 0;
+}
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_fifo_ppe_change(struct Qdisc *sch, struct nlattr *opt)
+#else
+static int nss_fifo_ppe_change(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack)
+#endif
+{
+	struct nss_fifo_sched_data *q = qdisc_priv(sch);
+	struct nss_qdisc *nq = &q->nq;
+	struct nss_ppe_qdisc prev_npq;
+
+	/*
+	 * Save previous configuration for reset purpose.
+	 */
+	if (nq->npq.is_configured) {
+		prev_npq = nq->npq;
+	}
+
+	/*
+	 * In case of bfifo, change the queue limit to number of blocks
+	 * as PPE HW has memory in blocks of 256 bytes.
+	 */
+	if (q->is_bfifo) {
+		nq->npq.q.qlimit = q->limit / NSS_PPE_MEM_BLOCK_SIZE;
+	} else {
+		nq->npq.q.qlimit = q->limit;
+	}
+
+	nq->npq.q.color_en = false;
+	nq->npq.q.red_en = false;
+
+	/*
+	 * Currently multicast queue configuration is based on set_default.
+	 * TODO: Enhance multicast queue configuration on the basis of
+	 * multicast parameter specified in tc commands.
+	 */
+	nq->npq.q.mcast_enable = q->set_default;
+
+	if (nss_ppe_configure(&q->nq, &prev_npq) < 0) {
+		nss_qdisc_warning("nss_fifo %x configuration failed\n", sch->handle);
+		goto fail;
+	}
+
+	return 0;
+
+fail:
+	if (nq->npq.is_configured) {
+		nss_qdisc_warning("nss_fifo %x configuration failed\n", sch->handle);
+		return -EINVAL;
+	}
+
+	/*
+	 * Fallback to nss qdisc if PPE Qdisc configuration failed at init time.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	if (nss_ppe_fallback_to_nss(&q->nq, opt) < 0) {
+#else
+	if (nss_ppe_fallback_to_nss(&q->nq, opt, extack) < 0) {
+#endif
+	nss_qdisc_warning("nss_fifo %x fallback to nss failed\n", sch->handle);
+		return -EINVAL;
+	}
+	return 0;
+}
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_fifo_change(struct Qdisc *sch, struct nlattr *opt)
+#else
+static int nss_fifo_change(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+#endif
+{
+	struct nss_fifo_sched_data *q = qdisc_priv(sch);
+	struct nss_qdisc *nq = &q->nq;
+	struct nss_if_msg nim;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	if (nss_fifo_params_validate_and_save(sch, opt) < 0) {
+#else
+	if (nss_fifo_params_validate_and_save(sch, opt, extack) < 0) {
+#endif
+		nss_qdisc_warning("nss_fifo %px params validate and save failed\n", sch);
+		return -EINVAL;
+	}
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	if (nq->mode == NSS_QDISC_MODE_PPE) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+		if (nss_fifo_ppe_change(sch, opt) < 0) {
+#else
+		if (nss_fifo_ppe_change(sch, opt, extack) < 0) {
+#endif
+			nss_qdisc_warning("nss_fifo %px params validate and save failed\n", sch);
+			return -EINVAL;
+		}
+		return 0;
+	}
+#endif
+
+	nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = nq->qos_tag;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.fifo_param.limit = q->limit;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.fifo_param.drop_mode = NSS_SHAPER_FIFO_DROP_MODE_TAIL;
+	if (nss_qdisc_configure(&q->nq, &nim, NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_CHANGE_PARAM) < 0) {
+		nss_qdisc_error("nss_fifo %px configuration failed\n", sch);
+		return -EINVAL;
+	}
+
+	/*
+	 * There is nothing we need to do if the qdisc is not
+	 * set as default qdisc.
+	 */
+	if (q->set_default == 0) {
+		return 0;
+	}
+
+	/*
+	 * Set this qdisc to be the default qdisc for enqueuing packets.
+	 */
+	if (nss_qdisc_set_default(nq) < 0) {
+		nss_qdisc_error("nss_fifo %px set_default failed\n", sch);
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("nss_fifo queue (qos_tag:%u) set as default\n", nq->qos_tag);
+
+	return 0;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_fifo_init(struct Qdisc *sch, struct nlattr *opt)
+{
+	struct netlink_ext_ack *extack = NULL;
+#else
+static int nss_fifo_init(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+{
+#endif
+	struct nss_qdisc *nq = qdisc_priv(sch);
+	struct nlattr *tb[TCA_NSSFIFO_MAX + 1];
+	struct tc_nssfifo_qopt *qopt;
+
+	if (!opt) {
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("Initializing Fifo - type %d\n", NSS_SHAPER_NODE_TYPE_FIFO);
+	nss_fifo_reset(sch);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_fifo_policy, tb, TCA_NSSFIFO_MAX, TCA_NSSFIFO_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_fifo_policy, tb, TCA_NSSFIFO_MAX, TCA_NSSFIFO_PARMS, extack);
+#endif
+	if (!qopt) {
+		nss_qdisc_warning("Invalid input to fifo %x", sch->handle);
+		return -EINVAL;
+	}
+
+	if (nss_qdisc_init(sch, nq, NSS_SHAPER_NODE_TYPE_FIFO, 0, qopt->accel_mode, extack) < 0)
+	{
+		nss_qdisc_warning("Fifo %x init failed", sch->handle);
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("NSS fifo initialized - handle %x parent %x\n", sch->handle, sch->parent);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	if (nss_fifo_change(sch, opt) < 0) {
+#else
+	if (nss_fifo_change(sch, opt, extack) < 0) {
+#endif
+		nss_qdisc_destroy(nq);
+		return -EINVAL;
+	}
+
+	/*
+	 * Start the stats polling timer
+	 */
+	nss_qdisc_start_basic_stats_polling(nq);
+
+	return 0;
+}
+
+static int nss_fifo_dump(struct Qdisc *sch, struct sk_buff *skb)
+{
+	struct nss_fifo_sched_data *q;
+	struct nlattr *opts = NULL;
+	struct tc_nssfifo_qopt opt;
+
+	nss_qdisc_info("Nssfifo Dumping!");
+
+	q = qdisc_priv(sch);
+	if (q == NULL) {
+		return -1;
+	}
+
+	opt.limit = q->limit;
+	opt.set_default = q->set_default;
+	opt.accel_mode = nss_qdisc_accel_mode_get(&q->nq);
+
+	opts = nss_qdisc_nla_nest_start(skb, TCA_OPTIONS);
+
+	if (opts == NULL) {
+		goto nla_put_failure;
+	}
+
+	if (nla_put(skb, TCA_NSSFIFO_PARMS, sizeof(opt), &opt)) {
+		goto nla_put_failure;
+	}
+
+	return nla_nest_end(skb, opts);
+
+nla_put_failure:
+	nla_nest_cancel(skb, opts);
+	return -EMSGSIZE;
+}
+
+static struct sk_buff *nss_fifo_peek(struct Qdisc *sch)
+{
+	nss_qdisc_info("Nssfifo Peeking");
+	return nss_qdisc_peek(sch);
+}
+
+struct Qdisc_ops nss_pfifo_qdisc_ops __read_mostly = {
+	.id		=	"nsspfifo",
+	.priv_size	=	sizeof(struct nss_fifo_sched_data),
+	.enqueue	=	nss_fifo_enqueue,
+	.dequeue	=	nss_fifo_dequeue,
+	.peek		=	nss_fifo_peek,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	.drop		=	nss_fifo_drop,
+#endif
+	.init		=	nss_fifo_init,
+	.reset		=	nss_fifo_reset,
+	.destroy	=	nss_fifo_destroy,
+	.change		=	nss_fifo_change,
+	.dump		=	nss_fifo_dump,
+	.owner		=	THIS_MODULE,
+};
+
+struct Qdisc_ops nss_bfifo_qdisc_ops __read_mostly = {
+	.id		=	"nssbfifo",
+	.priv_size	=	sizeof(struct nss_fifo_sched_data),
+	.enqueue	=	nss_fifo_enqueue,
+	.dequeue	=	nss_fifo_dequeue,
+	.peek		=	nss_fifo_peek,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	.drop		=	nss_fifo_drop,
+#endif
+	.init		=	nss_fifo_init,
+	.reset		=	nss_fifo_reset,
+	.destroy	=	nss_fifo_destroy,
+	.change		=	nss_fifo_change,
+	.dump		=	nss_fifo_dump,
+	.owner		=	THIS_MODULE,
+};
diff --git a/qca-nss-clients/nss_qdisc/nss_fifo.h b/qca-nss-clients/nss_qdisc/nss_fifo.h
new file mode 100644
index 0000000..3635dfe
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_fifo.h
@@ -0,0 +1,18 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern struct Qdisc_ops nss_pfifo_qdisc_ops;
+extern struct Qdisc_ops nss_bfifo_qdisc_ops;
diff --git a/qca-nss-clients/nss_qdisc/nss_htb.c b/qca-nss-clients/nss_qdisc/nss_htb.c
new file mode 100644
index 0000000..bd9b466
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_htb.c
@@ -0,0 +1,1184 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2017, 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_qdisc.h"
+
+#define NSS_HTB_MAX_PRIORITY 4
+
+/*
+ * nss_htb class parameters
+ */
+struct nss_htb_param {
+	u32 rate;		/* Allowed bandwidth for this class */
+	u32 burst;		/* Allowed burst for this class */
+	u32 crate;		/* Ceil bandwidth for this class */
+	u32 cburst;		/* Ceil burst for this class */
+	u32 quantum;		/* Quantum allocation for DRR */
+	u32 priority;		/* Priority value of this class */
+	u32 overhead;		/* Overhead in bytes to be added for each packet */
+};
+
+/*
+ * nss_htb class instance structure
+ */
+struct nss_htb_class_data {
+	struct nss_qdisc nq;			/* Base class used by nss_qdisc */
+	struct Qdisc_class_common sch_common;	/* Common class structure for scheduler use */
+	struct nss_htb_class_data *parent;	/* Pointer to our parent class */
+	struct Qdisc *qdisc;			/* Child qdisc, used by leaf classes */
+	int children;				/* Count of number of attached child classes */
+	bool is_leaf;				/* True if leaf class */
+	struct nss_htb_param param;		/* Parameters for this class */
+};
+
+/*
+ * nss_htb qdisc instance structure
+ */
+struct nss_htb_sched_data {
+	struct nss_qdisc nq;		/* Base class used by nss_qdisc */
+	u16 r2q;			/* The rate to quantum conversion ratio */
+	struct nss_htb_class_data root;	/* Root class */
+	struct Qdisc_class_hash clhash;	/* Class hash */
+};
+
+/*
+ * nss_htb_policy structure
+ */
+static struct nla_policy nss_htb_policy[TCA_NSSHTB_MAX + 1] = {
+	[TCA_NSSHTB_CLASS_PARMS] = { .len = sizeof(struct tc_nsshtb_class_qopt) },
+	[TCA_NSSHTB_QDISC_PARMS] = { .len = sizeof(struct tc_nsshtb_qopt) },
+};
+
+/*
+ * nss_htb_find_class()
+ *	Returns a pointer to class if classid matches with a class under this qdisc.
+ */
+static inline struct nss_htb_class_data *nss_htb_find_class(u32 classid, struct Qdisc *sch)
+{
+	struct nss_htb_sched_data *q = qdisc_priv(sch);
+	struct Qdisc_class_common *clc;
+	clc = qdisc_class_find(&q->clhash, classid);
+	if (clc == NULL) {
+		nss_qdisc_info("cannot find class with classid %x in qdisc %x hash\n",
+					classid, sch->handle);
+		return NULL;
+	}
+	return container_of(clc, struct nss_htb_class_data, sch_common);
+}
+
+/*
+ * nss_htb_class_params_validate_and_save()
+ *	Validates and saves the qdisc configuration parameters.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_htb_class_params_validate_and_save(struct Qdisc *sch, struct nlattr **tca,
+					struct nss_htb_param *param)
+#else
+static int nss_htb_class_params_validate_and_save(struct Qdisc *sch, struct nlattr **tca,
+					struct nss_htb_param *param, struct netlink_ext_ack *extack)
+#endif
+{
+	struct nlattr *opt = tca[TCA_OPTIONS];
+	struct nlattr *tb[TCA_NSSHTB_MAX + 1];
+	struct tc_nsshtb_class_qopt *qopt;
+	struct nss_htb_sched_data *q = qdisc_priv(sch);
+	struct net_device *dev = qdisc_dev(sch);
+	unsigned int mtu = psched_mtu(dev);
+
+	nss_qdisc_trace("validating parameters for nsshtb class of qdisc:%x\n", sch->handle);
+
+	if (!opt) {
+		nss_qdisc_error("passing null opt for configuring htb class %x\n", sch->handle);
+		return -EINVAL;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_htb_policy, tb, TCA_NSSHTB_MAX, TCA_NSSHTB_CLASS_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_htb_policy, tb, TCA_NSSHTB_MAX, TCA_NSSHTB_CLASS_PARMS, extack);
+#endif
+	if (!qopt) {
+		return -EINVAL;
+	}
+
+	sch_tree_lock(sch);
+	if (qopt->rate && !qopt->burst) {
+		nss_qdisc_error("burst needed if rate is non zero - class %x\n", sch->handle);
+		sch_tree_unlock(sch);
+		return -EINVAL;
+	}
+
+	if (!qopt->crate || !qopt->cburst) {
+		nss_qdisc_error("crate and cburst need to be non zero - class %x\n",
+					sch->handle);
+		sch_tree_unlock(sch);
+		return -EINVAL;
+	}
+
+	if (!(qopt->priority < NSS_HTB_MAX_PRIORITY)) {
+		nss_qdisc_error("priority %u of htb class %x greater than max prio %u",
+					qopt->priority, sch->handle, NSS_HTB_MAX_PRIORITY);
+		sch_tree_unlock(sch);
+		return -EINVAL;
+	}
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	if (q->nq.mode == NSS_QDISC_MODE_PPE) {
+		if ((qopt->quantum % NSS_PPE_DRR_WEIGHT_MAX) != 0) {
+			nss_qdisc_warning("nsshtb (accel_mode %d) requires quantum to be a multiple of 1024\n",
+					nss_qdisc_accel_mode_get(&q->nq));
+			sch_tree_unlock(sch);
+			return -EINVAL;
+		}
+
+		if (qopt->quantum > (NSS_PPE_DRR_WEIGHT_MAX * NSS_PPE_DRR_WEIGHT_MAX)) {
+			nss_qdisc_warning("nsshtb (accel_mode %d) requires quantum not exceeding 1024*1024\n",
+					nss_qdisc_accel_mode_get(&q->nq));
+			sch_tree_unlock(sch);
+			return -EINVAL;
+		}
+	}
+#endif
+
+	memset(param, 0, sizeof(*param));
+	param->rate = qopt->rate;
+	param->burst = qopt->burst;
+	param->crate = qopt->crate;
+	param->cburst = qopt->cburst;
+	param->overhead = qopt->overhead;
+	param->quantum = qopt->quantum;
+	param->priority = qopt->priority;
+
+	/*
+	 * If quantum value is not provided, set it to
+	 * the interface's MTU value.
+	 */
+	if (!param->quantum) {
+		/*
+		 * If quantum was not provided, we have two options.
+		 * One, use r2q and rate to figure out the quantum. Else,
+		 * use the interface's MTU as the value of quantum.
+		 */
+		if (q->r2q && param->rate) {
+			param->quantum = (param->rate / q->r2q) / 8;
+			nss_qdisc_info("quantum not provided for htb class %x on interface %s\n"
+					"Setting quantum to %uB based on r2q %u and rate %uBps\n",
+					sch->handle, dev->name, param->quantum, q->r2q, param->rate / 8);
+		} else {
+			param->quantum = mtu;
+			nss_qdisc_info("quantum value not provided for htb class %x on interface %s\n"
+					"Setting quantum to MTU %uB\n", sch->handle, dev->name, param->quantum);
+		}
+	}
+	sch_tree_unlock(sch);
+
+	return 0;
+}
+
+/*
+ * nss_htb_class_alloc()
+ *	Allocates a new class.
+ */
+static struct nss_htb_class_data *nss_htb_class_alloc(struct Qdisc *sch, struct nss_htb_class_data *parent, u32 classid)
+{
+	struct nss_htb_class_data *cl;
+	nss_qdisc_trace("creating a new htb class of qdisc:%x\n", sch->handle);
+
+	/*
+	 * check for valid classid
+	 */
+	if (!classid || TC_H_MAJ(classid ^ sch->handle) || nss_htb_find_class(classid, sch)) {
+		return NULL;
+	}
+
+	nss_qdisc_trace("htb class %x not found. Allocating a new class.\n", classid);
+	cl = kzalloc(sizeof(struct nss_htb_class_data), GFP_KERNEL);
+
+	if (!cl) {
+		nss_qdisc_error("class allocation failed for classid %x\n", classid);
+		return NULL;
+	}
+
+	nss_qdisc_trace("htb class %x allocated - addr %px\n", classid, cl);
+	cl->parent = parent;
+	cl->sch_common.classid = classid;
+
+	/*
+	 * Set this class as leaf. If a new class is attached as
+	 * child, it will set this value to false during the attach
+	 * process.
+	 */
+	cl->is_leaf = true;
+
+	/*
+	 * We make the child qdisc a noop qdisc, and
+	 * set reference count to 1. This is important,
+	 * reference count should not be 0.
+	 */
+	cl->qdisc = &noop_qdisc;
+	nss_qdisc_atomic_set(&cl->nq);
+
+	return cl;
+}
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+/*
+ * nss_htb_ppe_change_class()
+ *	Configures a class in ppe qdisc
+ */
+static int nss_htb_ppe_change_class(struct Qdisc *sch, struct nss_htb_class_data *cl, struct nss_htb_param *param)
+{
+	struct nss_ppe_qdisc prev_npq;
+
+	/*
+	 * Save the previous scheduler configuration
+	 * for handling failure conditions.
+	 */
+	prev_npq = cl->nq.npq;
+
+	cl->nq.npq.shaper_present = true;
+	cl->nq.npq.shaper.rate = param->rate;
+	cl->nq.npq.shaper.burst = param->burst;
+	cl->nq.npq.shaper.crate = param->crate;
+	cl->nq.npq.shaper.cburst = param->cburst;
+	cl->nq.npq.shaper.overhead = param->overhead;
+	cl->nq.npq.scheduler.drr_weight = nss_ppe_drr_weight_get(param->quantum, NSS_PPE_DRR_UNIT_BYTE);
+	cl->nq.npq.scheduler.drr_unit = NSS_PPE_DRR_UNIT_BYTE;
+	cl->nq.npq.scheduler.priority = param->priority;
+
+	/*
+	 * Change the configuration in SSDK
+	 */
+	if (nss_ppe_configure(&cl->nq, &prev_npq) != 0)  {
+		nss_qdisc_warning("nss_htb %x SSDK scheduler configuration failed\n", sch->handle);
+		return -EINVAL;
+	}
+
+	cl->param = *param;
+	return 0;
+}
+#endif
+
+/*
+ * nss_htb_change_class()
+ *	Configures a new class.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_htb_change_class(struct Qdisc *sch, u32 classid, u32 parentid,
+		  struct nlattr **tca, unsigned long *arg)
+{
+	struct netlink_ext_ack *extack = NULL;
+#else
+static int nss_htb_change_class(struct Qdisc *sch, u32 classid, u32 parentid,
+		  struct nlattr **tca, unsigned long *arg, struct netlink_ext_ack *extack)
+{
+#endif
+	struct nss_htb_sched_data *q = qdisc_priv(sch);
+	struct nss_htb_class_data *cl = (struct nss_htb_class_data *)*arg;
+	struct nss_htb_class_data *parent;
+	struct nss_qdisc *nq_parent;
+	struct nss_htb_param param;
+	struct nss_if_msg nim_config;
+	struct net_device *dev = qdisc_dev(sch);
+	unsigned int mtu = psched_mtu(dev);
+	unsigned int accel_mode = nss_qdisc_accel_mode_get(&q->nq);
+	bool new_init = false;
+
+	nss_qdisc_trace("configuring htb class %x of qdisc %x\n", classid, sch->handle);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	if (nss_htb_class_params_validate_and_save(sch, tca, &param) < 0) {
+#else
+	if (nss_htb_class_params_validate_and_save(sch, tca, &param, extack) < 0) {
+#endif
+		nss_qdisc_warning("validation of configuration parameters for htb class %x failed\n",
+					sch->handle);
+		return -EINVAL;
+	}
+
+	parent = (parentid == TC_H_ROOT) ? NULL : nss_htb_find_class(parentid, sch);
+
+	/*
+	 * The parent could be the htb qdisc, or a class. We set nq_parent pointer
+	 * accordingly.
+	 */
+	if (parent) {
+		nq_parent = &parent->nq;
+	} else {
+		nq_parent = &q->nq;
+	}
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	if (cl && (cl->nq.mode == NSS_QDISC_MODE_PPE)) {
+		if (nss_htb_ppe_change_class(sch, cl, &param) < 0) {
+			nss_qdisc_warning("nss_htb %x SSDK scheduler configuration failed\n", sch->handle);
+			return -EINVAL;
+		}
+		return 0;
+	}
+#endif
+
+	/*
+	 * If class with a given classid is not found, we allocate a new one
+	 */
+	if (!cl) {
+		struct nss_if_msg nim_attach;
+		cl = nss_htb_class_alloc(sch, parent, classid);
+
+		if (!cl) {
+			nss_qdisc_warning("class allocation failed for classid %x\n", classid);
+			goto failure;
+		}
+
+		*arg = (unsigned long)cl;
+		new_init = true;
+		nss_qdisc_trace("adding class %x to qdisc %x\n", classid, sch->handle);
+
+		/*
+		 * This is where a class gets initialized. Classes do not have a init function
+		 * that is registered to Linux. Therefore we initialize the NSSHTB_GROUP shaper
+		 * here.
+		 */
+		cl->nq.parent = nq_parent;
+		if (nss_qdisc_init(sch, &cl->nq, NSS_SHAPER_NODE_TYPE_HTB_GROUP, classid, accel_mode, extack) < 0)
+		{
+			nss_qdisc_error("nss_init for htb class %x failed\n", classid);
+			goto failure;
+		}
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+		if (cl->nq.mode == NSS_QDISC_MODE_PPE) {
+			if (nss_htb_ppe_change_class(sch, cl, &param) < 0) {
+				nss_qdisc_warning("nss_htb %x SSDK scheduler configuration failed\n", sch->handle);
+				nss_qdisc_destroy(&cl->nq);
+				goto failure;
+			}
+		}
+#endif
+
+		/*
+		 * Set qos_tag of parent to which the class needs to e attached to.
+		 * Set the child to be this class.
+		 * Send node_attach command down to the NSS
+		 */
+		nim_attach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = nq_parent->qos_tag;
+
+		if (cl->nq.mode == NSS_QDISC_MODE_NSS) {
+			nim_attach.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_attach.child_qos_tag = cl->nq.qos_tag;
+		}
+
+		if (nss_qdisc_node_attach(nq_parent, &cl->nq, &nim_attach,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_ATTACH) < 0) {
+			nss_qdisc_error("nss_attach for class %x failed\n", classid);
+			nss_qdisc_destroy(&cl->nq);
+			goto failure;
+		}
+
+		/*
+		 * We have successfully attached ourselves in the NSS. We can therefore
+		 * add this class to qdisc hash tree, and increment parent's child count
+		 * (if parent exists)
+		 */
+		sch_tree_lock(sch);
+		qdisc_class_hash_insert(&q->clhash, &cl->sch_common);
+		if (parent) {
+			parent->children++;
+
+			/*
+			 * Parent can no longer be leaf. Set flag to false.
+			 */
+			parent->is_leaf = false;
+		}
+		sch_tree_unlock(sch);
+
+		/*
+		 * Hash grow should not come within the tree lock
+		 */
+		qdisc_class_hash_grow(sch, &q->clhash);
+
+		/*
+		 * Start the stats polling timer
+		 */
+		nss_qdisc_start_basic_stats_polling(&cl->nq);
+
+		nss_qdisc_trace("class %x successfully allocated and initialized\n", classid);
+	}
+
+	/*
+	 * Fill information that needs to be sent down to the NSS for configuring the
+	 * htb class.
+	 */
+	cl->param = param;
+	if (cl->nq.mode == NSS_QDISC_MODE_NSS) {
+		nim_config.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag;
+		nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_param.quantum = cl->param.quantum;
+		nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_param.priority = cl->param.priority;
+		nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_param.overhead = cl->param.overhead;
+		nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_param.rate_police.rate = cl->param.rate;
+		nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_param.rate_police.burst = cl->param.burst;
+		nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_param.rate_police.max_size = mtu;
+		nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_param.rate_police.short_circuit = false;
+		nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_param.rate_ceil.rate = cl->param.crate;
+		nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_param.rate_ceil.burst = cl->param.cburst;
+		nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_param.rate_ceil.max_size = mtu;
+		nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_param.rate_ceil.short_circuit = false;
+
+		nss_qdisc_info("htb class %x - rate = %ubps burst = %ubytes crate = %ubps cburst = %ubytes MTU = %ubytes "
+				"quantum = %ubytes priority = %u\n", classid, cl->param.rate, cl->param.burst, cl->param.crate,
+				cl->param.cburst, mtu, cl->param.quantum, cl->param.priority);
+
+		/*
+		 * Send configure command to the NSS
+		 */
+		if (nss_qdisc_configure(&cl->nq, &nim_config,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_CHANGE_PARAM) < 0) {
+			nss_qdisc_error("failed to send configure message for htb class %x\n", classid);
+
+			if (!new_init) {
+				return -EINVAL;
+			}
+
+			nss_qdisc_destroy(&cl->nq);
+			goto failure;
+		}
+	}
+
+	nss_qdisc_info("htb class %x configured successfully\n", classid);
+	return 0;
+
+failure:
+	if (cl) {
+		kfree(cl);
+	}
+	return -EINVAL;
+}
+
+/*
+ * nss_htb_destroy_class()
+ *	Detaches all child nodes and destroys the class.
+ */
+static void nss_htb_destroy_class(struct Qdisc *sch, struct nss_htb_class_data *cl)
+{
+	struct nss_htb_sched_data *q __maybe_unused = qdisc_priv(sch);
+	struct nss_if_msg nim;
+	struct nss_qdisc *nq_child;
+
+	nss_qdisc_trace("destroying htb class %x from qdisc %x\n", cl->nq.qos_tag, sch->handle);
+
+	/*
+	 * We always have to detach the child qdisc, before destroying it.
+	 */
+	if (cl->qdisc != &noop_qdisc) {
+		nq_child = qdisc_priv(cl->qdisc);
+		nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag;
+
+		if (cl->nq.mode == NSS_QDISC_MODE_NSS) {
+			nim.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_detach.child_qos_tag = nq_child->qos_tag;
+		}
+
+		if (nss_qdisc_node_detach(&cl->nq, nq_child, &nim,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+			nss_qdisc_error("failed to detach child %x from class %x\n",
+					cl->qdisc->handle, q->nq.qos_tag);
+			return;
+		}
+	}
+
+	/*
+	 * And now we destroy the child.
+	 */
+	 nss_qdisc_put(cl->qdisc);
+
+	/*
+	 * Stop the stats polling timer and free class
+	 */
+	nss_qdisc_stop_basic_stats_polling(&cl->nq);
+
+	/*
+	 * Destroy the shaper in NSS
+	 */
+	nss_qdisc_destroy(&cl->nq);
+
+	/*
+	 * Free class
+	 */
+	kfree(cl);
+}
+
+/*
+ * nss_htb_delete_class()
+ *	Detaches a class from operation, but does not destroy it.
+ */
+static int nss_htb_delete_class(struct Qdisc *sch, unsigned long arg)
+{
+	struct nss_htb_sched_data *q = qdisc_priv(sch);
+	struct nss_htb_class_data *cl = (struct nss_htb_class_data *)arg;
+	struct nss_if_msg nim;
+	int refcnt;
+
+	/*
+	 * If the class still has child nodes, then we do not
+	 * support deleting it.
+	 */
+	if (cl->children) {
+		return -EBUSY;
+	}
+
+	/*
+	 * Check if we are root class or not (parent pointer is NULL for a root class)
+	 */
+	if (cl->parent) {
+
+		/*
+		 * The htb class to be detached has a parent class (i.e. not the root class),
+		 * so we need to send a detach msg to its parent class.
+		 */
+		nss_qdisc_info("detaching from parent htb class %x ", cl->parent->nq.qos_tag);
+		nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->parent->nq.qos_tag;
+		nim.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_detach.child_qos_tag = cl->nq.qos_tag;
+		if (nss_qdisc_node_detach(&q->nq, &cl->nq, &nim, NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+			return -EINVAL;
+		}
+	} else {
+		/*
+		 * The message to NSS should be sent to the parent of this class
+		 */
+		nss_qdisc_info("detaching from parent htb qdisc %x", q->nq.qos_tag);
+		nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+		if (nss_qdisc_node_detach(&q->nq, &cl->nq, &nim, NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+			return -EINVAL;
+		}
+	}
+
+	sch_tree_lock(sch);
+	qdisc_reset(cl->qdisc);
+	qdisc_class_hash_remove(&q->clhash, &cl->sch_common);
+
+	/*
+	 * If we are root class, we dont have to update our parent.
+	 * We simply deduct refcnt and return.
+	 */
+	if (!cl->parent) {
+		refcnt = nss_qdisc_atomic_sub_return(&cl->nq);
+		sch_tree_unlock(sch);
+		return 0;
+	}
+
+	/*
+	 * We are not root class. Therefore we reduce the children count
+	 * for our parent and also update its 'is_leaf' status.
+	 */
+	cl->parent->children--;
+	if (!cl->parent->children) {
+		cl->parent->is_leaf = true;
+	}
+
+	/*
+	 * Decrement refcnt and return
+	 */
+	refcnt = nss_qdisc_atomic_sub_return(&cl->nq);
+	sch_tree_unlock(sch);
+
+	return 0;
+}
+
+/*
+ * nss_htb_graft_class()
+ *	Replaces the qdisc attached to the provided class.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_htb_graft_class(struct Qdisc *sch, unsigned long arg, struct Qdisc *new, struct Qdisc **old)
+#else
+static int nss_htb_graft_class(struct Qdisc *sch, unsigned long arg, struct Qdisc *new, struct Qdisc **old,
+				struct netlink_ext_ack *extack)
+#endif
+{
+	struct nss_htb_class_data *cl = (struct nss_htb_class_data *)arg;
+	struct nss_if_msg nim_detach;
+	struct nss_if_msg nim_attach;
+	struct nss_qdisc *nq_new = qdisc_priv(new);
+	struct nss_qdisc *nq_old;
+
+	nss_qdisc_trace("grafting htb class %x\n", cl->nq.qos_tag);
+
+	if (new == NULL) {
+		new = &noop_qdisc;
+	}
+
+	sch_tree_lock(sch);
+	*old = cl->qdisc;
+	sch_tree_unlock(sch);
+
+	/*
+	 * Since we initially attached a noop qdisc as child (in Linux),
+	 * we do not perform a detach in the NSS if its a noop qdisc.
+	 */
+	nss_qdisc_info("grafting old: %x with new: %x\n", (*old)->handle, new->handle);
+	if (*old != &noop_qdisc) {
+		nss_qdisc_trace("detaching old: %x\n", (*old)->handle);
+		nq_old = qdisc_priv(*old);
+		nim_detach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag;
+		nim_detach.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_detach.child_qos_tag = nq_old->qos_tag;
+		if (nss_qdisc_node_detach(&cl->nq, nq_old, &nim_detach,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+			nss_qdisc_warning("detach of old qdisc %x failed\n", (*old)->handle);
+			return -EINVAL;
+		}
+	}
+
+	/*
+	 * If the new qdisc is a noop qdisc, we do not send down an attach command
+	 * to the NSS.
+	 */
+	if (new != &noop_qdisc) {
+		nss_qdisc_trace("attaching new: %x\n", new->handle);
+		nim_attach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag;
+		nim_attach.msg.shaper_configure.config.msg.shaper_node_config.snc.htb_group_attach.child_qos_tag = nq_new->qos_tag;
+		if (nss_qdisc_node_attach(&cl->nq, nq_new, &nim_attach,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_ATTACH) < 0) {
+			nss_qdisc_error("attach of new qdisc %x failed\n", new->handle);
+			return -EINVAL;
+		}
+	}
+
+	/*
+	 * Replaced in NSS, now replace in Linux.
+	 */
+	nss_qdisc_replace(sch, new, &cl->qdisc);
+
+	return 0;
+}
+
+/*
+ * nss_htb_leaf_class()
+ *	Returns pointer to qdisc if leaf class.
+ */
+static struct Qdisc *nss_htb_leaf_class(struct Qdisc *sch, unsigned long arg)
+{
+	struct nss_htb_class_data *cl = (struct nss_htb_class_data *)arg;
+	nss_qdisc_trace("htb class %x is leaf %d\n", cl->nq.qos_tag, cl->is_leaf);
+
+	/*
+	 * Return qdisc pointer if this is level 0 class
+	 */
+	return cl->is_leaf ? cl->qdisc : NULL;
+}
+
+/*
+ * nss_htb_qlen_notify()
+ *	We dont maintain a live set of stats in linux, so this function is not implemented.
+ */
+static void nss_htb_qlen_notify(struct Qdisc *sch, unsigned long arg)
+{
+	nss_qdisc_trace("qlen notify called for htb qdisc %x\n", sch->handle);
+
+	/*
+	 * Gets called when qlen of child changes (Useful for deactivating)
+	 * Not useful for us here.
+	 */
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0))
+/*
+ * nss_htb_get_class()
+ *	Fetches the class pointer if provided the classid.
+ */
+static unsigned long nss_htb_get_class(struct Qdisc *sch, u32 classid)
+{
+	struct nss_htb_class_data *cl = nss_htb_find_class(classid, sch);
+
+	if (cl != NULL) {
+		nss_qdisc_trace("fetched htb class %x from qdisc %x\n",
+				cl->nq.qos_tag, sch->handle);
+		atomic_add(1, &cl->nq.refcnt);
+	}
+
+	return (unsigned long)cl;
+}
+
+/*
+ * nss_htb_put_class()
+ *	Reduces reference count for this class.
+ */
+static void nss_htb_put_class(struct Qdisc *sch, unsigned long arg)
+{
+	struct nss_htb_class_data *cl = (struct nss_htb_class_data *)arg;
+	nss_qdisc_trace("executing put on htb class %x in qdisc %x\n",
+			cl->nq.qos_tag, sch->handle);
+
+	/*
+	 * We are safe to destroy the qdisc if the reference count
+	 * goes down to 0.
+	 */
+	if (nss_qdisc_atomic_sub_return(&cl->nq) == 0) {
+		nss_htb_destroy_class(sch, cl);
+	}
+}
+#else
+/*
+ * nss_htb_search_class()
+ *	Fetches the class pointer if provided the classid.
+ */
+static unsigned long nss_htb_search_class(struct Qdisc *sch, u32 classid)
+{
+	struct nss_htb_class_data *cl = nss_htb_find_class(classid, sch);
+
+	return (unsigned long)cl;
+}
+#endif
+
+/*
+ * nss_htb_dump_class()
+ *	Dumps all configurable parameters pertaining to this class.
+ */
+static int nss_htb_dump_class(struct Qdisc *sch, unsigned long arg, struct sk_buff *skb, struct tcmsg *tcm)
+{
+	struct nss_htb_class_data *cl = (struct nss_htb_class_data *)arg;
+	struct nlattr *opts;
+	struct tc_nsshtb_class_qopt qopt;
+
+	nss_qdisc_trace("dumping htb class %x of qdisc %x\n", cl->nq.qos_tag, sch->handle);
+
+	qopt.burst = cl->param.burst;
+	qopt.rate = cl->param.rate;
+	qopt.crate = cl->param.crate;
+	qopt.cburst = cl->param.cburst;
+	qopt.overhead = cl->param.overhead;
+	qopt.quantum = cl->param.quantum;
+	qopt.priority = cl->param.priority;
+
+	/*
+	 * All htb group nodes are root nodes. i.e. they dont
+	 * have any mode htb groups attached beneath them.
+	 */
+	tcm->tcm_parent = TC_H_ROOT;
+	tcm->tcm_handle = cl->sch_common.classid;
+	tcm->tcm_info = cl->qdisc->handle;
+
+	opts = nss_qdisc_nla_nest_start(skb, TCA_OPTIONS);
+	if (opts == NULL || nla_put(skb, TCA_NSSHTB_CLASS_PARMS, sizeof(qopt), &qopt)) {
+		goto nla_put_failure;
+	}
+
+	return nla_nest_end(skb, opts);
+
+nla_put_failure:
+	nla_nest_cancel(skb, opts);
+	nss_qdisc_error("htb class %x dumo failed\n", cl->nq.qos_tag);
+	return -EMSGSIZE;
+}
+
+/*
+ * nss_htb_dump_class_stats()
+ *	Dumps class statistics.
+ */
+static int nss_htb_dump_class_stats(struct Qdisc *sch, unsigned long arg, struct gnet_dump *d)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)arg;
+
+	if (nss_qdisc_gnet_stats_copy_basic(sch, d, &nq->bstats) < 0 ||
+			nss_qdisc_gnet_stats_copy_queue(d, &nq->qstats) < 0) {
+		nss_qdisc_error("htb class %x stats dump failed\n", nq->qos_tag);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_htb_walk()
+ *	Used to walk the tree.
+ */
+static void nss_htb_walk(struct Qdisc *sch, struct qdisc_walker *arg)
+{
+	struct nss_htb_sched_data *q = qdisc_priv(sch);
+	struct hlist_node *n __maybe_unused;
+	struct nss_htb_class_data *cl;
+	unsigned int i;
+
+	nss_qdisc_trace("walking htb qdisc %x\n", sch->handle);
+
+	if (arg->stop)
+		return;
+
+	for (i = 0; i < q->clhash.hashsize; i++) {
+		nss_qdisc_hlist_for_each_entry(cl, n, &q->clhash.hash[i],
+				sch_common.hnode) {
+			if (arg->count < arg->skip) {
+				arg->count++;
+				continue;
+			}
+			if (arg->fn(sch, (unsigned long)cl, arg) < 0) {
+				arg->stop = 1;
+				return;
+			}
+			arg->count++;
+		}
+	}
+}
+
+/*
+ * nss_htb_change_qdisc()
+ *	Can be used to configure a htb qdisc.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_htb_change_qdisc(struct Qdisc *sch, struct nlattr *opt)
+#else
+static int nss_htb_change_qdisc(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+#endif
+{
+	struct nss_htb_sched_data *q = qdisc_priv(sch);
+	struct nlattr *tb[TCA_NSSHTB_MAX + 1];
+	struct tc_nsshtb_qopt *qopt;
+
+	/*
+	 * Since nsshtb can be created with no arguments, opt might be NULL
+	 * (depending on the kernel version). This is still a valid create
+	 * request.
+	 */
+	if (opt == NULL) {
+
+		/*
+		 * If no parameter is passed, set it to 0 and continue
+		 * creating the qdisc.
+		 */
+		sch_tree_lock(sch);
+		q->r2q = 0;
+		sch_tree_unlock(sch);
+		return 0;
+	}
+
+	/*
+	 * If it is not NULL, parse to get qopt.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_htb_policy, tb, TCA_NSSHTB_MAX, TCA_NSSHTB_QDISC_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_htb_policy, tb, TCA_NSSHTB_MAX, TCA_NSSHTB_QDISC_PARMS, extack);
+#endif
+	if (!qopt) {
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("Setting r2q:%u", qopt->r2q);
+
+	sch_tree_lock(sch);
+	q->r2q = qopt->r2q;
+	sch_tree_unlock(sch);
+
+	/*
+	 * The r2q parameter is not needed in the firmware. So we do not
+	 * send down a configuration message.
+	 */
+
+	return 0;
+}
+
+/*
+ * nss_htb_reset_class()
+ *	Resets child qdisc of class to be reset.
+ */
+static void nss_htb_reset_class(struct nss_htb_class_data *cl)
+{
+	nss_qdisc_reset(cl->qdisc);
+	nss_qdisc_trace("htb class %x reset\n", cl->nq.qos_tag);
+}
+
+/*
+ * nss_htb_reset_qdisc()
+ *	Resets htb qdisc and its classes.
+ */
+static void nss_htb_reset_qdisc(struct Qdisc *sch)
+{
+	struct nss_htb_sched_data *q = qdisc_priv(sch);
+	struct nss_htb_class_data *cl;
+	struct hlist_node *n __maybe_unused;
+	unsigned int i;
+
+	for (i = 0; i < q->clhash.hashsize; i++) {
+		nss_qdisc_hlist_for_each_entry(cl, n, &q->clhash.hash[i], sch_common.hnode)
+			nss_htb_reset_class(cl);
+	}
+
+	nss_qdisc_reset(sch);
+	nss_qdisc_trace("nss htb qdisc %x reset\n", sch->handle);
+}
+
+/*
+ * nss_htb_destroy_qdisc()
+ *	Call to destroy a htb qdisc and its associated classes.
+ */
+static void nss_htb_destroy_qdisc(struct Qdisc *sch)
+{
+	struct nss_htb_sched_data *q = qdisc_priv(sch);
+	struct hlist_node *n __maybe_unused;
+	struct hlist_node *next;
+	struct nss_htb_class_data *cl;
+	unsigned int i = 0;
+
+	/*
+	 * Destroy all the child classes before the parent is destroyed.
+	 */
+	while (q->clhash.hashelems) {
+		nss_qdisc_hlist_for_each_entry_safe(cl, n, next, &q->clhash.hash[i], sch_common.hnode) {
+
+			if (cl->children) {
+				continue;
+			}
+
+			/*
+			 * Reduce refcnt by 1 before destroying. This is to
+			 * ensure that polling of stat stops properly.
+			 */
+			 nss_qdisc_atomic_sub(&cl->nq);
+
+			/*
+			 * We are not root class. Therefore we reduce the children count
+			 * for our parent.
+			 */
+			sch_tree_lock(sch);
+			if (cl->parent) {
+				cl->parent->children--;
+			}
+			qdisc_class_hash_remove(&q->clhash, &cl->sch_common);
+			sch_tree_unlock(sch);
+
+			/*
+			 * Now we can destroy the class.
+			 */
+			nss_htb_destroy_class(sch, cl);
+		}
+		i++;
+
+		/*
+		 * In the first iteration, all the leaf nodes will be removed.
+		 * Now the intermediate nodes (one above the leaf nodes) are
+		 * leaf nodes. So, to delete the entire tree level wise,
+		 * wrap around the index.
+		 */
+		if (i == q->clhash.hashsize) {
+			i = 0;
+		}
+	}
+	qdisc_class_hash_destroy(&q->clhash);
+
+	/*
+	 * Stop the polling of basic stats
+	 */
+	nss_qdisc_stop_basic_stats_polling(&q->nq);
+
+	/*
+	 * Now we can go ahead and destroy the qdisc.
+	 * Note: We dont have to detach ourself from our parent because this
+	 *	 will be taken care of by the graft call.
+	 */
+	nss_qdisc_destroy(&q->nq);
+	nss_qdisc_info("htb qdisc %x destroyed\n", sch->handle);
+}
+
+/*
+ * nss_htb_init_qdisc()
+ *	Initializes the htb qdisc.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_htb_init_qdisc(struct Qdisc *sch, struct nlattr *opt)
+{
+	struct netlink_ext_ack *extack = NULL;
+#else
+static int nss_htb_init_qdisc(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+{
+#endif
+	struct nss_htb_sched_data *q = qdisc_priv(sch);
+	struct nlattr *tb[TCA_NSSHTB_MAX + 1];
+	struct tc_nsshtb_qopt *qopt;
+	int err;
+	unsigned int accel_mode;
+	unsigned int r2q = 0;
+
+	nss_qdisc_trace("initializing htb qdisc %x\n", sch->handle);
+
+	err = qdisc_class_hash_init(&q->clhash);
+	if (err < 0) {
+		nss_qdisc_error("hash init failed for htb qdisc %x", sch->handle);
+		return err;
+	}
+
+	if (!opt) {
+		accel_mode = TCA_NSS_ACCEL_MODE_PPE;
+	} else {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+		qopt = nss_qdisc_qopt_get(opt, nss_htb_policy, tb, TCA_NSSHTB_MAX, TCA_NSSHTB_QDISC_PARMS);
+#else
+		qopt = nss_qdisc_qopt_get(opt, nss_htb_policy, tb, TCA_NSSHTB_MAX, TCA_NSSHTB_QDISC_PARMS, extack);
+#endif
+		if (!qopt) {
+			return -EINVAL;
+		}
+		accel_mode = qopt->accel_mode;
+		r2q = qopt->r2q;
+	}
+
+	nss_qdisc_info("r2q = %u accel_mode = %u\n", r2q, accel_mode);
+
+	/*
+	 * Initialize the NSSHTB shaper in NSS
+	 */
+	if (nss_qdisc_init(sch, &q->nq, NSS_SHAPER_NODE_TYPE_HTB, 0, accel_mode, extack) < 0) {
+		nss_qdisc_error("failed to initialize htb qdisc %x in nss", sch->handle);
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("htb qdisc initialized with handle %x\n", sch->handle);
+
+	/*
+	 * Tune HTB parameters
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	if (nss_htb_change_qdisc(sch, opt) < 0) {
+#else
+	if (nss_htb_change_qdisc(sch, opt, extack) < 0) {
+#endif
+		nss_qdisc_destroy(&q->nq);
+		return -EINVAL;
+	}
+
+	/*
+	 * Start the stats polling timer
+	 */
+	nss_qdisc_start_basic_stats_polling(&q->nq);
+
+	return 0;
+}
+
+/*
+ * nss_htb_dump_qdisc()
+ *	Dumps htb qdisc's configurable parameters.
+ */
+static int nss_htb_dump_qdisc(struct Qdisc *sch, struct sk_buff *skb)
+{
+	struct nss_htb_sched_data *q = qdisc_priv(sch);
+	struct nlattr *opts = NULL;
+	struct tc_nsshtb_qopt qopt;
+
+	nss_qdisc_trace("dumping htb qdisc %x\n", sch->handle);
+
+	qopt.r2q = q->r2q;
+	qopt.accel_mode = nss_qdisc_accel_mode_get(&q->nq);
+
+	nss_qdisc_info("r2q = %u accel_mode = %u", qopt.r2q, qopt.accel_mode);
+
+	opts = nss_qdisc_nla_nest_start(skb, TCA_OPTIONS);
+	if (!opts || nla_put(skb, TCA_NSSHTB_QDISC_PARMS, sizeof(qopt), &qopt)) {
+		goto nla_put_failure;
+	}
+
+	return nla_nest_end(skb, opts);
+
+ nla_put_failure:
+	nla_nest_cancel(skb, opts);
+	return -EMSGSIZE;
+}
+
+/*
+ * nss_htb_enqueue()
+ *	Enqueues a skb to htb qdisc.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+static int nss_htb_enqueue(struct sk_buff *skb, struct Qdisc *sch)
+#else
+static int nss_htb_enqueue(struct sk_buff *skb, struct Qdisc *sch,
+				struct sk_buff **to_free)
+#endif
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	return nss_qdisc_enqueue(skb, sch);
+#else
+	return nss_qdisc_enqueue(skb, sch, to_free);
+#endif
+}
+
+/*
+ * nss_htb_dequeue()
+ *	Dequeues a skb from htb qdisc.
+ */
+static struct sk_buff *nss_htb_dequeue(struct Qdisc *sch)
+{
+	return nss_qdisc_dequeue(sch);
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+/*
+ * nss_htb_drop()
+ *	Drops a single skb from linux queue, if not empty.
+ *
+ * Does not drop packets that are queued in the NSS.
+ */
+static unsigned int nss_htb_drop(struct Qdisc *sch)
+{
+	nss_qdisc_trace("drop called on htb qdisc %x\n", sch->handle);
+	return nss_qdisc_drop(sch);
+}
+#endif
+
+/*
+ * Registration structure for htb class
+ */
+const struct Qdisc_class_ops nss_htb_class_ops = {
+	.change		= nss_htb_change_class,
+	.delete		= nss_htb_delete_class,
+	.graft		= nss_htb_graft_class,
+	.leaf		= nss_htb_leaf_class,
+	.qlen_notify	= nss_htb_qlen_notify,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0))
+	.get		= nss_htb_get_class,
+	.put		= nss_htb_put_class,
+#else
+	.find		=	nss_htb_search_class,
+#endif
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	.tcf_chain	= nss_qdisc_tcf_chain,
+#else
+	.tcf_block	= nss_qdisc_tcf_block,
+#endif
+	.bind_tcf	= nss_qdisc_tcf_bind,
+	.unbind_tcf	= nss_qdisc_tcf_unbind,
+	.dump		= nss_htb_dump_class,
+	.dump_stats	= nss_htb_dump_class_stats,
+	.walk		= nss_htb_walk
+};
+
+/*
+ * Registration structure for htb qdisc
+ */
+struct Qdisc_ops nss_htb_qdisc_ops __read_mostly = {
+	.id		= "nsshtb",
+	.init		= nss_htb_init_qdisc,
+	.change		= nss_htb_change_qdisc,
+	.reset		= nss_htb_reset_qdisc,
+	.destroy	= nss_htb_destroy_qdisc,
+	.dump		= nss_htb_dump_qdisc,
+	.enqueue	= nss_htb_enqueue,
+	.dequeue	= nss_htb_dequeue,
+	.peek		= qdisc_peek_dequeued,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	.drop		= nss_htb_drop,
+#endif
+	.cl_ops		= &nss_htb_class_ops,
+	.priv_size	= sizeof(struct nss_htb_sched_data),
+	.owner		= THIS_MODULE
+};
diff --git a/qca-nss-clients/nss_qdisc/nss_htb.h b/qca-nss-clients/nss_qdisc/nss_htb.h
new file mode 100644
index 0000000..5f9cbbd
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_htb.h
@@ -0,0 +1,17 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern struct Qdisc_ops nss_htb_qdisc_ops;
diff --git a/qca-nss-clients/nss_qdisc/nss_ppe.c b/qca-nss-clients/nss_qdisc/nss_ppe.c
new file mode 100644
index 0000000..cd793d1
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_ppe.c
@@ -0,0 +1,2372 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_qdisc.h"
+#include "nss_wred.h"
+
+/*
+ * HW scaling factor
+ *
+ * Change this value to 100 if testing on RUMI.
+ * Frequency of RUMI is 100 times slower.
+ */
+#define NSS_PPE_HW_FREQ_SCALING	1
+
+/*
+ * Max Resources per port
+ *
+ * Currently, we are using only one multicast queue.
+ * In case of Loopback port, the resources are reserved
+ * for qdisc functionality.
+ */
+#define NSS_PPE_MCAST_QUEUE_MAX		1
+
+#define NSS_PPE_LOOPBACK_L0_SP_MAX		1
+#define NSS_PPE_LOOPBACK_L0_CDRR_MAX		16
+#define NSS_PPE_LOOPBACK_L0_EDRR_MAX		16
+#define NSS_PPE_LOOPBACK_QUEUE_MAX		16
+#define NSS_PPE_LOOPBACK_MCAST_QUEUE_MAX	1
+
+#define NSS_PPE_LOOPBACK_L0_SP_BASE		35
+#define NSS_PPE_LOOPBACK_L0_CDRR_BASE		32
+#define NSS_PPE_LOOPBACK_L0_EDRR_BASE		32
+#define NSS_PPE_LOOPBACK_QUEUE_BASE		128
+#define NSS_PPE_LOOPBACK_MCAST_QUEUE_BASE	256
+
+#define NSS_PPE_PRIORITY_MAX		7
+#define NSS_PPE_PORT_MAX		8
+
+/*
+ * Max number of PRIO bands supported based on level.
+ */
+#define NSS_PPE_PORT_LEVEL_PRIO_BANDS_MAX	4
+#define NSS_PPE_FLOW_LEVEL_PRIO_BANDS_MAX	8
+
+static struct nss_ppe_port ppe_qdisc_port[NSS_PPE_PORT_MAX];
+
+/*
+ * nss_ppe_loobback_l1_conf_set()
+ *	Sets default L1 queue scheduler in SSDK for port 0.
+ */
+static int nss_ppe_loobback_l1_conf_set(void)
+{
+	fal_qos_scheduler_cfg_t l1cfg;
+
+	/*
+	 * Set Level 1 Configuration
+	 */
+	memset(&l1cfg, 0, sizeof(l1cfg));
+	l1cfg.sp_id = 0;
+	l1cfg.c_pri = 0;
+	l1cfg.e_pri = 0;
+	l1cfg.c_drr_id = 0;
+	l1cfg.e_drr_id = 0;
+	l1cfg.c_drr_wt = 1;
+	l1cfg.e_drr_wt = 1;
+
+	nss_qdisc_trace("SSDK level1 configuration: Port:0, l0spid:%d, c_drrid:%d, c_pri:%d, c_drr_wt:%d, e_drrid:%d, e_pri:%d, e_drr_wt:%d, l1spid:%d\n",
+			NSS_PPE_LOOPBACK_L0_SP_BASE, l1cfg.c_drr_id, l1cfg.c_pri, l1cfg.c_drr_wt, l1cfg.e_drr_id, l1cfg.e_pri, l1cfg.e_drr_wt, l1cfg.sp_id);
+	if (fal_queue_scheduler_set(0, NSS_PPE_LOOPBACK_L0_SP_BASE, NSS_PPE_FLOW_LEVEL - 1, 0, &l1cfg) != 0) {
+		nss_qdisc_error("SSDK level1 queue scheduler configuration failed\n");
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("SSDK L1 configuration successful\n");
+	return 0;
+}
+
+/*
+ * nss_ppe_res_entries_free()
+ *	Free all the resource for a given port.
+ */
+static void nss_ppe_res_entries_free(uint32_t port, nss_ppe_res_type_t type)
+{
+	struct nss_ppe_res *res;
+	struct nss_ppe_res *head = NULL;
+	struct nss_ppe_port *ppe_port = &ppe_qdisc_port[port];
+
+	spin_lock_bh(&ppe_port->lock);
+	head = ppe_port->res_free[type];
+	while (head) {
+		res = head;
+		head = head->next;
+		kfree(res);
+	}
+
+	ppe_port->res_free[type] = NULL;
+	spin_unlock_bh(&ppe_port->lock);
+
+	nss_qdisc_info("port:%d, type:%d\n", port, type);
+}
+
+/*
+ * nss_ppe_res_entries_alloc()
+ *	Allocates all the resources for a given port.
+ */
+static struct nss_ppe_res *nss_ppe_res_entries_alloc(uint32_t port, nss_ppe_res_type_t type)
+{
+	struct nss_ppe_res *res = NULL;
+	struct nss_ppe_res *next = NULL;
+	uint32_t i;
+	struct nss_ppe_port *ppe_port = &ppe_qdisc_port[port];
+	uint32_t max = ppe_port->max[type];
+
+	spin_lock_bh(&ppe_port->lock);
+	for (i = max; i > 0; i--) {
+		res = kzalloc(sizeof(struct nss_ppe_res), GFP_KERNEL);
+		if (!res) {
+			nss_qdisc_error("Free queue list allocation failed for port %u\n", port);
+			goto fail;
+		}
+
+		res->offset = i - 1;
+		res->type = type;
+		res->next = next;
+		next = res;
+
+	}
+	spin_unlock_bh(&ppe_port->lock);
+
+	nss_qdisc_trace("port:%d, type:%d\n", port, type);
+	return res;
+
+fail:
+	while (next) {
+		res = next;
+		next = next->next;
+		kfree(res);
+	}
+	spin_unlock_bh(&ppe_port->lock);
+	return NULL;
+}
+
+/*
+ * nss_ppe_sub_type_is_queue()
+ *	Returns true is qdisc is of type queue.
+ */
+static bool nss_ppe_sub_type_is_queue(struct nss_ppe_qdisc *npq)
+{
+	if (npq->sub_type < NSS_SHAPER_CONFIG_PPE_SN_SCH_MAX) {
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_ppe_max_get()
+ *	Returns maximum number of the particular resource for a given port.
+ */
+static uint32_t nss_ppe_max_get(uint32_t port, nss_ppe_res_type_t type)
+{
+	uint32_t max = 0;
+	struct nss_ppe_port *ppe_port = &ppe_qdisc_port[port];
+
+	spin_lock_bh(&ppe_port->lock);
+	max = ppe_port->max[type];
+	spin_unlock_bh(&ppe_port->lock);
+
+	nss_qdisc_info("port:%d, type:%d, max:%d\n", port, type, max);
+	return max;
+}
+
+/*
+ * nss_ppe_port_res_free()
+ *	Free resources allocated to PPE ports
+ */
+int nss_ppe_port_res_free(void)
+{
+	uint32_t i, j;
+	nss_qdisc_info("nss_ppe_port_res_free");
+
+	for (i = 0; i < NSS_PPE_PORT_MAX - 1; i++) {
+		for (j = 0; j < NSS_PPE_MAX_RES_TYPE; j++) {
+			nss_ppe_res_entries_free(i, j);
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ppe_port_res_alloc()
+ *	Allocates per port resources
+ *
+ *	TODO: Replace the MAX with the configuration from device tree.
+ */
+int nss_ppe_port_res_alloc(void)
+{
+	int j, type;
+	fal_portscheduler_resource_t cfg;
+	int i = 0;
+	nss_qdisc_info("nss_ppe_port_res_alloc");
+
+	memset(&ppe_qdisc_port, 0, sizeof(struct nss_ppe_port) * NSS_PPE_PORT_MAX);
+
+	nss_qdisc_info("Resource allocation for loopback port %u\n", i);
+
+	/*
+	 * Initialize lock
+	 */
+	spin_lock_init(&ppe_qdisc_port[i].lock);
+
+	/*
+	 * Loopback port configuration
+	 * Loopback port requires only L0 resources.
+	 */
+	ppe_qdisc_port[i].max[NSS_PPE_UCAST_QUEUE] = NSS_PPE_LOOPBACK_QUEUE_MAX;
+	ppe_qdisc_port[i].base[NSS_PPE_UCAST_QUEUE] = NSS_PPE_LOOPBACK_QUEUE_BASE;
+
+	ppe_qdisc_port[i].max[NSS_PPE_MCAST_QUEUE] = NSS_PPE_LOOPBACK_MCAST_QUEUE_MAX;
+	ppe_qdisc_port[i].base[NSS_PPE_MCAST_QUEUE] = NSS_PPE_LOOPBACK_MCAST_QUEUE_BASE;
+
+	ppe_qdisc_port[i].max[NSS_PPE_L0_CDRR] = NSS_PPE_LOOPBACK_L0_CDRR_MAX;
+	ppe_qdisc_port[i].base[NSS_PPE_L0_CDRR] = NSS_PPE_LOOPBACK_L0_CDRR_BASE;
+
+	ppe_qdisc_port[i].max[NSS_PPE_L0_EDRR] = NSS_PPE_LOOPBACK_L0_EDRR_MAX;
+	ppe_qdisc_port[i].base[NSS_PPE_L0_EDRR] = NSS_PPE_LOOPBACK_L0_EDRR_BASE;
+
+	ppe_qdisc_port[i].max[NSS_PPE_L0_SP] = NSS_PPE_LOOPBACK_L0_SP_MAX;
+	ppe_qdisc_port[i].base[NSS_PPE_L0_SP] = NSS_PPE_LOOPBACK_L0_SP_BASE;
+
+	for (type = 0; type <= NSS_PPE_L0_SP; type++) {
+		ppe_qdisc_port[i].res_free[type] = nss_ppe_res_entries_alloc(i, type);
+		if (!ppe_qdisc_port[i].res_free[type]) {
+			nss_qdisc_error("Resource list allocation failed for port:%u type:%u\n", i, type);
+			goto failure;
+		}
+	}
+
+	/*
+	 * Allocate resources for GMAC switch ports.
+	 */
+	for (i = 1; i < NSS_PPE_PORT_MAX - 1; i++) {
+		nss_qdisc_info("Resource allocation for port %u\n", i);
+
+		/*
+		 * Initialize locks
+		 */
+		spin_lock_init(&ppe_qdisc_port[i].lock);
+
+		/*
+		 * Resource configuration
+		 */
+		memset(&cfg, 0, sizeof(cfg));
+
+		if (fal_port_scheduler_resource_get(0, i, &cfg) != 0) {
+			nss_qdisc_error("Fetching of port scheduler resource information failed\n");
+			goto failure;
+		}
+
+		ppe_qdisc_port[i].max[NSS_PPE_UCAST_QUEUE] = cfg.ucastq_num;
+		ppe_qdisc_port[i].base[NSS_PPE_UCAST_QUEUE] = cfg.ucastq_start;
+
+		/*
+		 * Even though we reserve more mcast queues in the device tree, we only use 1 in qdiscs.
+		 */
+		ppe_qdisc_port[i].max[NSS_PPE_MCAST_QUEUE] = NSS_PPE_MCAST_QUEUE_MAX;
+		ppe_qdisc_port[i].base[NSS_PPE_MCAST_QUEUE] = cfg.mcastq_start;
+
+		ppe_qdisc_port[i].max[NSS_PPE_L0_CDRR] = cfg.l0cdrr_num;
+		ppe_qdisc_port[i].base[NSS_PPE_L0_CDRR] = cfg.l0cdrr_start;
+
+		ppe_qdisc_port[i].max[NSS_PPE_L0_EDRR] = cfg.l0edrr_num;
+		ppe_qdisc_port[i].base[NSS_PPE_L0_EDRR] = cfg.l0edrr_start;
+
+		ppe_qdisc_port[i].max[NSS_PPE_L0_SP] = cfg.l0sp_num;
+		ppe_qdisc_port[i].base[NSS_PPE_L0_SP] = cfg.l0sp_start;
+
+		ppe_qdisc_port[i].max[NSS_PPE_L1_CDRR] = cfg.l1cdrr_num;
+		ppe_qdisc_port[i].base[NSS_PPE_L1_CDRR] = cfg.l1cdrr_start;
+
+		ppe_qdisc_port[i].max[NSS_PPE_L1_EDRR] = cfg.l1edrr_num;
+		ppe_qdisc_port[i].base[NSS_PPE_L1_EDRR] = cfg.l1edrr_start;
+
+		for (type = 0; type < NSS_PPE_MAX_RES_TYPE; type++) {
+			ppe_qdisc_port[i].res_free[type] = nss_ppe_res_entries_alloc(i, type);
+			if (!ppe_qdisc_port[i].res_free[type]) {
+				nss_qdisc_error("Resource list allocation failed for port:%u type:%u\n", i, type);
+				goto failure;
+			}
+		}
+	}
+
+	/*
+	 * Set default level 1 configuration for loopback port.
+	 */
+	if (nss_ppe_loobback_l1_conf_set() != 0) {
+		nss_qdisc_error("Failed default level 1 configuration for brige port\n");
+		goto failure;
+	}
+	return 0;
+
+failure:
+	/*
+	 * In case we have successfully allocated resources for all the ports
+	 * and failure occurs while setting default level 1 configuration
+	 * for loobpack port, then decrement the counter to deallocate resources.
+	 */
+	if (i == (NSS_PPE_PORT_MAX - 1)) {
+		i--;
+	}
+
+	while (i >= 0) {
+		for (j = 0; j < NSS_PPE_MAX_RES_TYPE; j++) {
+			nss_ppe_res_entries_free(i, j);
+		}
+		i--;
+	}
+	return -EINVAL;
+}
+
+/*
+ * nss_ppe_queue_disable()
+ *	Disables a queue in SSDK.
+ */
+static void nss_ppe_queue_disable(struct nss_qdisc *nq)
+{
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	if (!npq->q.ucast_valid) {
+		return;
+	}
+
+	/*
+	 * Disable queue enqueue, dequeue and flush the queue.
+	 */
+	fal_qm_enqueue_ctrl_set(0, npq->q.ucast_qid, false);
+	fal_scheduler_dequeue_ctrl_set(0, npq->q.ucast_qid, false);
+	fal_queue_flush(0, port_num, npq->q.ucast_qid);
+
+	nss_qdisc_info("Disable SSDK level0 queue scheduler successful\n");
+}
+
+/*
+ * nss_ppe_queue_enable()
+ *	Enables a queue in SSDK.
+ */
+static void nss_ppe_queue_enable(struct nss_qdisc *nq)
+{
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	if (!npq->q.ucast_valid) {
+		return;
+	}
+
+	/*
+	 * Enable queue enqueue and dequeue.
+	 */
+	fal_qm_enqueue_ctrl_set(0, npq->q.ucast_qid, true);
+	fal_scheduler_dequeue_ctrl_set(0, npq->q.ucast_qid, true);
+
+	nss_qdisc_info("Enable SSDK level0 queue scheduler successful\n");
+}
+
+/*
+ * nss_ppe_l1_res_free()
+ *	Frees Level 1 scheduler resources.
+ */
+static int nss_ppe_l1_res_free(struct nss_qdisc *nq)
+{
+	uint32_t offset;
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	if (!npq->l1_valid) {
+		return 0;
+	}
+
+	/*
+	 * Loopback will have one level less than the max shaper levels.
+	 * L1 scheduler was configured at init time, so resources were allocated.
+	 */
+	if (nq->needs_ppe_loopback) {
+		offset = npq->l0spid - nss_ppe_base_get(port_num, NSS_PPE_L0_SP);
+		if (nss_ppe_res_free(port_num, offset, NSS_PPE_L0_SP) != 0) {
+			nss_qdisc_error("Used res:%d not found for port:%d, type:%d\n", npq->l0spid, port_num, NSS_PPE_L0_SP);
+			return -EINVAL;
+		}
+
+		npq->l0spid = 0;
+		npq->l1_valid = false;
+		nss_qdisc_trace("loopback resource freed\n");
+		return 0;
+	}
+
+	/*
+	 * Free Level 1 DRR resource
+	 */
+	offset = npq->l1c_drrid - nss_ppe_base_get(port_num, NSS_PPE_L1_CDRR);
+	if (nss_ppe_res_free(port_num, offset, NSS_PPE_L1_CDRR) != 0) {
+		nss_qdisc_error("Used res:%d not found for port:%d, type:%d \n", npq->l1c_drrid, port_num, NSS_PPE_L1_CDRR);
+		return -EINVAL;
+	}
+
+	offset = npq->l1e_drrid - nss_ppe_base_get(port_num, NSS_PPE_L1_EDRR);
+	if (nss_ppe_res_free(port_num, offset, NSS_PPE_L1_EDRR) != 0) {
+		nss_qdisc_error("Used res:%d not found for port:%d, type:%d \n", npq->l1e_drrid, port_num, NSS_PPE_L1_EDRR);
+		return -EINVAL;
+	}
+
+	/*
+	 * Free Level 0 SP resource
+	 */
+	offset = npq->l0spid - nss_ppe_base_get(port_num, NSS_PPE_L0_SP);
+	if (nss_ppe_res_free(port_num, offset, NSS_PPE_L0_SP) != 0) {
+		nss_qdisc_error("Used res:%d not found for port:%d, type:%d \n", npq->l0spid, port_num, NSS_PPE_L0_SP);
+		return -EINVAL;
+	}
+
+	/*
+	 * Reset Res id values in qdisc
+	 */
+	npq->l0spid = 0;
+	npq->l1c_drrid = 0;
+	npq->l1e_drrid = 0;
+	npq->l1_valid = false;
+
+	nss_qdisc_info("SSDK level1 queue scheduler configuration successful\n");
+	return 0;
+}
+
+/*
+ * nss_ppe_l1_res_alloc()
+ *	Allocates Level 1 scheduler resources
+ */
+static int nss_ppe_l1_res_alloc(struct nss_qdisc *nq)
+{
+	struct nss_ppe_res *l1c_drr = NULL;
+	struct nss_ppe_res *l1e_drr = NULL;
+	struct nss_ppe_res *l0sp = NULL;
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	/*
+	 * Get Level 0 SP resource
+	 */
+	l0sp = nss_ppe_res_alloc(port_num, NSS_PPE_L0_SP);
+	if (!l0sp) {
+		nss_qdisc_warning("Free res not found for port:%d, type:%d \n", port_num, NSS_PPE_L0_SP);
+		goto fail;
+	}
+
+	/*
+	 * Loopback has no dedicated L1 schedulers. L0 SP is the only resource we
+	 * need to allocate.
+	 */
+	if (nq->needs_ppe_loopback) {
+		npq->l0spid = nss_ppe_base_get(port_num, NSS_PPE_L0_SP) + l0sp->offset;
+		npq->l1_valid = true;
+		nss_qdisc_info("Level1 scheduler resource allocation successful\n");
+		return 0;
+	}
+
+	/*
+	 * Get Level 1 DRR resource
+	 */
+	l1c_drr = nss_ppe_res_alloc(port_num, NSS_PPE_L1_CDRR);
+	if (!l1c_drr) {
+		nss_qdisc_warning("Free res not found for port:%d, type:%d \n", port_num, NSS_PPE_L1_CDRR);
+		goto fail;
+	}
+
+	l1e_drr = nss_ppe_res_alloc(port_num, NSS_PPE_L1_EDRR);
+	if (!l1e_drr) {
+		nss_qdisc_warning("Free res not found for port:%d, type:%d \n", port_num, NSS_PPE_L1_EDRR);
+		goto fail;
+	}
+
+	/*
+	 * Set Res id values in qdisc
+	 */
+	npq->q.ucast_qid = 0;
+	npq->q.mcast_qid = 0;
+	npq->q.ucast_valid = false;
+	npq->l1_valid = true;
+	npq->l0c_drrid = 0;
+	npq->l0e_drrid = 0;
+	npq->l0spid = nss_ppe_base_get(port_num, NSS_PPE_L0_SP) + l0sp->offset;
+	npq->l1c_drrid = nss_ppe_base_get(port_num, NSS_PPE_L1_CDRR) + l1c_drr->offset;
+	npq->l1e_drrid = nss_ppe_base_get(port_num, NSS_PPE_L1_EDRR) + l1e_drr->offset;
+
+	nss_qdisc_info("Level1 scheduler resource allocation successful\n");
+	return 0;
+
+fail:
+	if (l0sp) {
+		nss_ppe_res_free(port_num, l0sp->offset, NSS_PPE_L0_SP);
+	}
+
+	if (l1e_drr) {
+		nss_ppe_res_free(port_num, l1e_drr->offset, NSS_PPE_L1_EDRR);
+	}
+
+	if (l1c_drr) {
+		nss_ppe_res_free(port_num, l1c_drr->offset, NSS_PPE_L1_CDRR);
+	}
+	return -EINVAL;
+}
+
+/*
+ * nss_ppe_all_queue_disable()
+ *	Disables all queues corresponding to a port in SSDK.
+ */
+static void nss_ppe_all_queue_disable(uint32_t port_num)
+{
+	uint32_t qid = nss_ppe_base_get(port_num, NSS_PPE_UCAST_QUEUE);
+	uint32_t mcast_qid = nss_ppe_base_get(port_num, NSS_PPE_MCAST_QUEUE);
+	uint32_t offset;
+
+	/*
+	 * Disable queue enqueue, dequeue and flush the queue.
+	 */
+	for (offset = 0; offset < nss_ppe_max_get(port_num, NSS_PPE_UCAST_QUEUE); offset++) {
+		fal_qm_enqueue_ctrl_set(0, qid + offset, false);
+		fal_scheduler_dequeue_ctrl_set(0, qid + offset, false);
+		fal_queue_flush(0, port_num, qid + offset);
+	}
+
+	for (offset = 0; offset < nss_ppe_max_get(port_num, NSS_PPE_MCAST_QUEUE); offset++) {
+		fal_qm_enqueue_ctrl_set(0, mcast_qid + offset, false);
+		fal_scheduler_dequeue_ctrl_set(0, mcast_qid + offset, false);
+		fal_queue_flush(0, port_num, mcast_qid + offset);
+	}
+
+	nss_qdisc_info("Disable SSDK level0 queue scheduler successful\n");
+}
+
+/*
+ * nss_ppe_all_queue_enable()
+ *	Enables all level L0 queues corresponding to a port in SSDK.
+ */
+static void nss_ppe_all_queue_enable(uint32_t port_num)
+{
+	uint32_t qid = nss_ppe_base_get(port_num, NSS_PPE_UCAST_QUEUE);
+	uint32_t mcast_qid = nss_ppe_base_get(port_num, NSS_PPE_MCAST_QUEUE);
+	uint32_t offset;
+
+	/*
+	 * Enable queue enqueue and dequeue.
+	 */
+	for (offset = 0; offset < nss_ppe_max_get(port_num, NSS_PPE_UCAST_QUEUE); offset++) {
+		fal_qm_enqueue_ctrl_set(0, qid + offset, true);
+		fal_scheduler_dequeue_ctrl_set(0, qid + offset, true);
+	}
+
+	for (offset = 0; offset < nss_ppe_max_get(port_num, NSS_PPE_MCAST_QUEUE); offset++) {
+		fal_qm_enqueue_ctrl_set(0, mcast_qid + offset, true);
+		fal_scheduler_dequeue_ctrl_set(0, mcast_qid + offset, true);
+	}
+
+	nss_qdisc_info("Enable SSDK level0 queue scheduler successful\n");
+}
+
+/*
+ * nss_ppe_l1_queue_scheduler_configure()
+ *	Configures Level 1 queue scheduler in SSDK.
+ */
+static int nss_ppe_l1_queue_scheduler_configure(struct nss_qdisc *nq)
+{
+	fal_qos_scheduler_cfg_t l1cfg;
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	if (npq->scheduler.drr_weight >= NSS_PPE_DRR_WEIGHT_MAX) {
+		nss_qdisc_warning("DRR weight:%d should be less than 1024\n", npq->scheduler.drr_weight);
+		return -EINVAL;
+	}
+
+	/*
+	 * Disable all queues and set Level 1 SSDK configuration
+	 * We need to disable and flush the queues before
+	 * changing scheduler's sp_id/drr_id/priority.
+	 */
+	nss_ppe_all_queue_disable(port_num);
+
+	memset(&l1cfg, 0, sizeof(l1cfg));
+	l1cfg.sp_id = port_num;
+
+	l1cfg.c_drr_wt = npq->scheduler.drr_weight ? npq->scheduler.drr_weight : 1;
+	l1cfg.c_drr_unit = npq->scheduler.drr_unit;
+	l1cfg.e_drr_wt = npq->scheduler.drr_weight ? npq->scheduler.drr_weight : 1;
+	l1cfg.e_drr_unit = npq->scheduler.drr_unit;
+	l1cfg.c_pri = NSS_PPE_PRIORITY_MAX - npq->scheduler.priority;
+	l1cfg.e_pri = NSS_PPE_PRIORITY_MAX - npq->scheduler.priority;
+	l1cfg.c_drr_id = npq->l1c_drrid;
+	l1cfg.e_drr_id = npq->l1e_drrid;
+	l1cfg.drr_frame_mode = NSS_PPE_FRAME_CRC;
+
+	nss_qdisc_trace("SSDK level1 configuration: Port:%d, l0spid:%d, c_drrid:%d, c_pri:%d, c_drr_wt:%d, e_drrid:%d, e_pri:%d, e_drr_wt:%d, l1spid:%d\n",
+			port_num, npq->l0spid, l1cfg.c_drr_id, l1cfg.c_pri, l1cfg.c_drr_wt, l1cfg.e_drr_id, l1cfg.e_pri, l1cfg.e_drr_wt, l1cfg.sp_id);
+	if (fal_queue_scheduler_set(0, npq->l0spid, NSS_PPE_FLOW_LEVEL - 1, port_num, &l1cfg) != 0) {
+		nss_qdisc_error("SSDK level1 queue scheduler configuration failed\n");
+		nss_ppe_all_queue_enable(port_num);
+		return -EINVAL;
+	}
+
+	nss_ppe_all_queue_enable(port_num);
+
+	nss_qdisc_info("SSDK level1 queue scheduler configuration successful\n");
+	return 0;
+}
+
+/*
+ * nss_ppe_l1_queue_scheduler_set()
+ *	Configures Level 1 queue scheduler in SSDK.
+ */
+static int nss_ppe_l1_queue_scheduler_set(struct nss_qdisc *nq)
+{
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	/*
+	 * Loopback will have one level less than the max shaper levels.
+	 * L1 scheduler was configured at init time, so no need to allocate resources.
+	 */
+	if (nq->needs_ppe_loopback) {
+		/*
+		 * Allocate resource if we have not already done so.
+		 */
+		if (!npq->l1_valid && nss_ppe_l1_res_alloc(nq) != 0) {
+			nss_qdisc_warning("SSDK level1 queue scheduler configuration failed\n");
+			return -EINVAL;
+		}
+
+		nss_qdisc_info("Allocated spid:%d expected:%d\n", npq->l0spid, NSS_PPE_LOOPBACK_L0_SP_BASE);
+
+		/*
+		 * L0 SP is the only resource we allocate in loopback, and that
+		 * does not require additional configuration. The next level of
+		 * C/E DRR will attach to the right priority slot.
+		 *
+		 * We simply return.
+		 */
+		nss_qdisc_info("SSDK level1 queue scheduler configuration successful\n");
+		return 0;
+	}
+
+	/*
+	 * Allocate resources if we have not already done so.
+	 */
+	if (!npq->l1_valid && nss_ppe_l1_res_alloc(nq) != 0) {
+		nss_qdisc_warning("SSDK level1 queue scheduler configuration failed\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Set Level 1 configuration
+	 */
+	if (nss_ppe_l1_queue_scheduler_configure(nq) != 0) {
+		nss_qdisc_error("SSDK level1 queue scheduler configuration failed\n");
+		nss_ppe_l1_res_free(nq);
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("SSDK level1 queue scheduler configuration successful\n");
+	return 0;
+}
+
+/*
+ * nss_ppe_l0_res_free()
+ *	Frees level0 scheduler resources.
+ */
+static int nss_ppe_l0_res_free(struct nss_qdisc *nq)
+{
+	uint32_t offset;
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	if (!npq->l0_valid) {
+		return 0;
+	}
+
+	/*
+	 * Free Level 0 DRR resource
+	 */
+	offset = npq->l0c_drrid - nss_ppe_base_get(port_num, NSS_PPE_L0_CDRR);
+	if (nss_ppe_res_free(port_num, offset, NSS_PPE_L0_CDRR) != 0) {
+		nss_qdisc_error("Used res:%d not found for port:%d, type:%d \n", npq->l0c_drrid, port_num, NSS_PPE_L0_CDRR);
+		return -EINVAL;
+	}
+
+	offset = npq->l0e_drrid - nss_ppe_base_get(port_num, NSS_PPE_L0_EDRR);
+	if (nss_ppe_res_free(port_num, offset, NSS_PPE_L0_EDRR) != 0) {
+		nss_qdisc_error("Used res:%d not found for port:%d, type:%d \n", npq->l0e_drrid, port_num, NSS_PPE_L0_EDRR);
+		return -EINVAL;
+	}
+
+	/*
+	 * Free Level 0 queue resource
+	 */
+	offset = npq->q.ucast_qid - nss_ppe_base_get(port_num, NSS_PPE_UCAST_QUEUE);
+	if (nss_ppe_res_free(port_num, offset, NSS_PPE_UCAST_QUEUE) != 0) {
+		nss_qdisc_error("Used res:%d not found for port:%d, type:%d \n", npq->q.ucast_qid, port_num, NSS_PPE_UCAST_QUEUE);
+		return -EINVAL;
+	}
+
+	/*
+	 * Reset Res id values in qdisc
+	 */
+	npq->q.ucast_qid = 0;
+	npq->q.mcast_qid = 0;
+	npq->q.mcast_valid = false;
+	npq->q.ucast_valid = false;
+	npq->l0c_drrid = 0;
+	npq->l0e_drrid = 0;
+	npq->l0_valid = false;
+
+	nss_qdisc_info("Level0 scheduler resource de-allocation successful\n");
+	return 0;
+}
+
+/*
+ * nss_ppe_l0_queue_scheduler_deconfigure()
+ *	De-configures Level 0 queue scheduler configuration in SSDK.
+ */
+static int nss_ppe_l0_queue_scheduler_deconfigure(struct nss_qdisc *nq)
+{
+	fal_qos_scheduler_cfg_t l0cfg;
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	nss_ppe_all_queue_disable(port_num);
+
+	/*
+	 * Reset Level 0 configuration
+	 */
+	memset(&l0cfg, 0, sizeof(l0cfg));
+	l0cfg.sp_id = npq->l0spid;
+	l0cfg.c_drr_wt = 0;
+	l0cfg.e_drr_wt = 0;
+	l0cfg.c_drr_id = npq->l0c_drrid;
+	l0cfg.e_drr_id = npq->l0e_drrid;
+
+	nss_qdisc_trace("SSDK level0 configuration: Port:%d, ucast_qid:%d, c_drrid:%d, c_pri:%d, c_drr_wt:%d, e_drrid:%d, e_pri:%d, e_drr_wt:%d, l0spid:%d\n",
+			port_num, npq->q.ucast_qid, l0cfg.c_drr_id, l0cfg.c_pri, l0cfg.c_drr_wt, l0cfg.e_drr_id, l0cfg.e_pri, l0cfg.e_drr_wt, l0cfg.sp_id);
+	if (fal_queue_scheduler_set(0, npq->q.ucast_qid, NSS_PPE_QUEUE_LEVEL - 1, port_num, &l0cfg) != 0) {
+		nss_qdisc_error("SSDK level0 queue scheduler configuration failed\n");
+		nss_ppe_all_queue_enable(port_num);
+		return -EINVAL;
+	}
+
+	nss_ppe_all_queue_enable(port_num);
+
+	nss_qdisc_info("SSDK level0 queue scheduler configuration successful\n");
+	return 0;
+}
+
+/*
+ * nss_ppe_l0_queue_scheduler_reset()
+ *	Resets Level 0 queue scheduler configuration in SSDK.
+ */
+static int nss_ppe_l0_queue_scheduler_reset(struct nss_qdisc *nq)
+{
+	if (nss_ppe_l0_queue_scheduler_deconfigure(nq) != 0) {
+		nss_qdisc_error("SSDK level0 queue scheduler configuration failed\n");
+		return -EINVAL;
+	}
+
+	if (nss_ppe_l0_res_free(nq) != 0) {
+		nss_qdisc_error("Level0 scheduler resources de-allocation failed\n");
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("SSDK level0 queue scheduler configuration successful\n");
+	return 0;
+}
+
+/*
+ * nss_ppe_l0_res_alloc()
+ *	Allocates level 0 resources.
+ */
+static int nss_ppe_l0_res_alloc(struct nss_qdisc *nq)
+{
+	struct nss_ppe_res *l0c_drr = NULL;
+	struct nss_ppe_res *l0e_drr = NULL;
+	struct nss_ppe_res *q = NULL;
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	/*
+	 * Get Level 0 DRR Resource
+	 */
+	l0c_drr = nss_ppe_res_alloc(port_num, NSS_PPE_L0_CDRR);
+	if (!l0c_drr) {
+		nss_qdisc_warning("Free res not found for port:%d, type:%d \n", port_num, NSS_PPE_L0_CDRR);
+		goto fail;
+	}
+
+	l0e_drr = nss_ppe_res_alloc(port_num, NSS_PPE_L0_EDRR);
+	if (!l0e_drr) {
+		nss_qdisc_warning("Free res not found for port:%d, type:%d \n", port_num, NSS_PPE_L0_EDRR);
+		goto fail;
+	}
+
+	/*
+	 * Get Level 0 queue Resource
+	 */
+	q = nss_ppe_res_alloc(port_num, NSS_PPE_UCAST_QUEUE);
+	if (!q) {
+		nss_qdisc_warning("Free res not found for port:%d, type:%d \n", port_num, NSS_PPE_UCAST_QUEUE);
+		goto fail;
+	}
+
+	/*
+	 * Set res id values in qdisc
+	 */
+	npq->q.ucast_qid = nss_ppe_base_get(port_num, NSS_PPE_UCAST_QUEUE) + q->offset;
+	npq->q.ucast_valid = true;
+	npq->l0_valid = true;
+	npq->l0c_drrid = nss_ppe_base_get(port_num, NSS_PPE_L0_CDRR) + l0c_drr->offset;
+	npq->l0e_drrid = nss_ppe_base_get(port_num, NSS_PPE_L0_EDRR) + l0e_drr->offset;
+	npq->q.mcast_qid = 0;
+
+	/*
+	 * If a qdisc or class is attached at queue level,
+	 * we need to set the L0 SP Id from the parent qdisc
+	 * to make connection between L0 and L1 resources.
+	 */
+	if (npq->level == NSS_PPE_QUEUE_LEVEL) {
+		npq->l0spid = nq->parent->npq.l0spid;
+	}
+
+	nss_qdisc_info("Level0 scheduler resource allocation successful\n");
+	return 0;
+
+fail:
+	if (q) {
+		nss_ppe_res_free(port_num, q->offset, NSS_PPE_UCAST_QUEUE);
+	}
+
+	if (l0c_drr) {
+		nss_ppe_res_free(port_num, l0c_drr->offset, NSS_PPE_L0_CDRR);
+	}
+
+	if (l0e_drr) {
+		nss_ppe_res_free(port_num, l0e_drr->offset, NSS_PPE_L0_EDRR);
+	}
+	return -EINVAL;
+}
+
+/*
+ * nss_ppe_l0_queue_scheduler_configure()
+ *	Configures a level 0 queue scheduler in SSDK.
+ */
+static int nss_ppe_l0_queue_scheduler_configure(struct nss_qdisc *nq)
+{
+	fal_qos_scheduler_cfg_t l0cfg;
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	if (npq->scheduler.drr_weight >= NSS_PPE_DRR_WEIGHT_MAX) {
+		nss_qdisc_warning("DRR weight:%d should be less than 1024\n", npq->scheduler.drr_weight);
+		return -EINVAL;
+	}
+
+	/*
+	 * Disable all queues and set Level 0 SSDK configuration
+	 * We need to disable and flush the queues before
+	 * changing scheduler's sp_id/drr_id/priority.
+	 */
+	nss_ppe_all_queue_disable(port_num);
+
+	memset(&l0cfg, 0, sizeof(l0cfg));
+	l0cfg.sp_id = npq->l0spid;
+	l0cfg.c_drr_wt = npq->scheduler.drr_weight ? npq->scheduler.drr_weight : 1;
+	l0cfg.c_drr_unit = npq->scheduler.drr_unit;
+	l0cfg.e_drr_wt = npq->scheduler.drr_weight ? npq->scheduler.drr_weight : 1;
+	l0cfg.e_drr_unit = npq->scheduler.drr_unit;
+	l0cfg.c_pri = NSS_PPE_PRIORITY_MAX - npq->scheduler.priority;
+	l0cfg.e_pri = NSS_PPE_PRIORITY_MAX - npq->scheduler.priority;
+	l0cfg.c_drr_id = npq->l0c_drrid;
+	l0cfg.e_drr_id = npq->l0e_drrid;
+	l0cfg.drr_frame_mode = NSS_PPE_FRAME_CRC;
+
+	nss_qdisc_trace("SSDK level0 configuration: Port:%d, ucast_qid:%d, c_drrid:%d, c_pri:%d, c_drr_wt:%d, e_drrid:%d, e_pri:%d, e_drr_wt:%d, l0spid:%d\n",
+			port_num, npq->q.ucast_qid, l0cfg.c_drr_id, l0cfg.c_pri, l0cfg.c_drr_wt, l0cfg.e_drr_id, l0cfg.e_pri, l0cfg.e_drr_wt, l0cfg.sp_id);
+	if (fal_queue_scheduler_set(0, npq->q.ucast_qid, NSS_PPE_QUEUE_LEVEL - 1, port_num, &l0cfg) != 0) {
+		nss_qdisc_error("SSDK level0 queue scheduler configuration failed\n");
+		nss_ppe_all_queue_enable(port_num);
+		return -EINVAL;
+	}
+
+	/*
+	 * This function is called at the time of queue qdisc allocation at all
+	 * levels and class allocation at NSS_PPE_QUEUE_LEVEL.
+	 * Also invoked at time of change class at NSS_PPE_QUEUE_LEVEL and
+	 * NSS_PPE_SUB_QUEUE_LEVEL levels. But, mcast will be valid only in
+	 * case queue is attached at NSS_PPE_SUB_QUEUE_LEVEL and change class
+	 * is invoked at NSS_PPE_QUEUE_LEVEL level.
+	 * Other scenarios catering to mcast queue are handled in separate mcast APIs.
+	 */
+	if (npq->q.mcast_qid) {
+		nss_qdisc_trace("SSDK level0 configuration: Port:%d, mcast_qid:%d, c_drrid:%d, c_pri:%d, c_drr_wt:%d, e_drrid:%d, e_pri:%d, e_drr_wt:%d, l0spid:%d\n",
+				port_num, npq->q.mcast_qid, l0cfg.c_drr_id, l0cfg.c_pri, l0cfg.c_drr_wt, l0cfg.e_drr_id, l0cfg.e_pri, l0cfg.e_drr_wt, l0cfg.sp_id);
+		if (fal_queue_scheduler_set(0, npq->q.mcast_qid, NSS_PPE_QUEUE_LEVEL - 1, port_num, &l0cfg) != 0) {
+			nss_qdisc_error("SSDK level0 multicast queue scheduler configuration failed\n");
+			nss_ppe_all_queue_enable(port_num);
+			return -EINVAL;
+		}
+	}
+
+	nss_ppe_all_queue_enable(port_num);
+
+	nss_qdisc_info("SSDK level0 queue scheduler configuration successful\n");
+	return 0;
+}
+
+/*
+ * nss_ppe_l0_queue_scheduler_set()
+ *	Configures a level 0 queue scheduler in SSDK.
+ */
+static int nss_ppe_l0_queue_scheduler_set(struct nss_qdisc *nq)
+{
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	/*
+	 * Allocate resources only if scheduler is not valid
+	 */
+	if (!npq->l0_valid) {
+		/*
+		 * Allocate Level 0 resources
+		 */
+		if (nss_ppe_l0_res_alloc(nq) != 0) {
+			nss_qdisc_warning("SSDK level0 queue scheduler configuration failed\n");
+			return -EINVAL;
+		}
+	}
+
+	/*
+	 * Set Level 0 configuration
+	 */
+	if (nss_ppe_l0_queue_scheduler_configure(nq) != 0) {
+		nss_qdisc_error("SSDK level0 queue scheduler configuration failed\n");
+		nss_ppe_l0_res_free(nq);
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("SSDK level0 queue scheduler configuration successful\n");
+	return 0;
+}
+
+/*
+ * nss_ppe_port_shaper_reset()
+ *	Resets a port shaper in SSDK.
+ */
+static int nss_ppe_port_shaper_reset(struct nss_qdisc *nq)
+{
+	fal_shaper_config_t cfg;
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+
+	memset(&cfg, 0, sizeof(cfg));
+	nss_qdisc_trace("SSDK port shaper reset : Port:%d\n", port_num);
+	if (fal_port_shaper_set(0, port_num, &cfg) != 0) {
+		nss_qdisc_error("SSDK port shaper configuration failed for port:%d\n", port_num);
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("SSDK port shaper configuration successful for port:%d\n", port_num);
+	return 0;
+}
+
+/*
+ * nss_ppe_port_shaper_set()
+ *	Configures a port shaper in SSDK.
+ */
+static int nss_ppe_port_shaper_set(struct nss_qdisc *nq)
+{
+	fal_shaper_token_number_t token;
+	fal_shaper_config_t cfg;
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	/*
+	 * Set port shaper token number
+	 */
+	memset(&token, 0, sizeof(token));
+	token.c_token_number = NSS_PPE_TOKEN_MAX;
+	token.e_token_number = NSS_PPE_TOKEN_MAX;
+
+	nss_qdisc_trace("SSDK port token set : Port:%d, c_token_number:%x, e_token_number:%x\n",
+		port_num, token.c_token_number, token.e_token_number);
+	if (fal_port_shaper_token_number_set(0, port_num, &token) != 0) {
+		nss_qdisc_error("SSDK port shaper token configuration failed for port:%d\n", port_num);
+		return -EINVAL;
+	}
+
+	/*
+	 * Set port shaper configuration
+	 * Note: SSDK API requires burst in bytes/sec
+	 * while rate in kbits/sec.
+	 */
+	memset(&cfg, 0, sizeof(cfg));
+	cfg.couple_en = 0;
+	cfg.meter_unit = 0;
+	cfg.c_shaper_en = 1;
+	cfg.cbs = npq->shaper.cburst;
+	cfg.cir = (npq->shaper.crate / 1000) * 8;
+	cfg.shaper_frame_mode = NSS_PPE_FRAME_CRC;
+
+	/*
+	 * Take HW scaling into consideration
+	 */
+	cfg.cir = cfg.cir * NSS_PPE_HW_FREQ_SCALING;
+
+	nss_qdisc_trace("SSDK port shaper configuration: Port:%u, couple_en:%u, meter_unit:%u, c_shaper_en:%u, cbs:%u, cir:%u, ebs:%u, eir:%u, shaper_frame_mode:%u\n",
+			port_num, cfg.couple_en, cfg.meter_unit, cfg.c_shaper_en, cfg.cbs, cfg.cir, cfg.ebs, cfg.eir, cfg.shaper_frame_mode);
+	if (fal_port_shaper_set(0, port_num, &cfg) != 0) {
+		nss_qdisc_error("SSDK port shaper configuration failed for port:%d\n", port_num);
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("SSDK port shaper configuration successful for port:%d\n", port_num);
+	return 0;
+}
+
+/*
+ * nss_ppe_flow_shaper_reset()
+ *	Resets a flow shaper in SSDK.
+ */
+static int nss_ppe_flow_shaper_reset(struct nss_qdisc *nq)
+{
+	fal_shaper_config_t cfg;
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	/*
+	 * Reset flow shaper configuration
+	 */
+	memset(&cfg, 0, sizeof(cfg));
+	nss_qdisc_trace("SSDK flow shaper reset : l0spid:%d\n", npq->l0spid);
+	if (fal_flow_shaper_set(0, npq->l0spid, &cfg) != 0) {
+		nss_qdisc_error("SSDK flow shaper configuration failed for port:%d, l0spid:%d\n",
+			port_num, npq->l0spid);
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("SSDK flow shaper configuration successful for port:%d\n", port_num);
+	return 0;
+}
+
+/*
+ * nss_ppe_flow_shaper_set()
+ *	Configures a flow shaper in SSDK.
+ */
+static int nss_ppe_flow_shaper_set(struct nss_qdisc *nq)
+{
+	fal_shaper_token_number_t token;
+	fal_shaper_config_t cfg;
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	/*
+	 * Set flow shaper token number
+	 */
+	memset(&token, 0, sizeof(token));
+	token.c_token_number = NSS_PPE_TOKEN_MAX;
+	token.e_token_number = NSS_PPE_TOKEN_MAX;
+
+	nss_qdisc_trace("SSDK flow token set : l0spid:%d, c_token_number:%x, e_token_number:%x\n",
+		npq->l0spid, token.c_token_number, token.e_token_number);
+	if (fal_flow_shaper_token_number_set(0, npq->l0spid, &token) != 0) {
+		nss_qdisc_error("SSDK flow shaper token configuration failed for port:%d, l0spid:%d\n",
+			port_num, npq->l0spid);
+		return -EINVAL;
+	}
+
+	/*
+	 * Set flow shaper token configuration
+	 * Note: SSDK API requires burst in bytes/sec
+	 * while rate in kbits/sec.
+	 */
+	cfg.couple_en = 0;
+	cfg.meter_unit = 0;
+	cfg.c_shaper_en = 1;
+	cfg.cbs = npq->shaper.burst;
+	cfg.cir = (npq->shaper.rate / 1000) * 8;
+	cfg.e_shaper_en = 1;
+	cfg.ebs = npq->shaper.cburst;
+	cfg.eir = ((npq->shaper.crate / 1000) * 8) - cfg.cir;
+	cfg.shaper_frame_mode = NSS_PPE_FRAME_CRC;
+
+	/*
+	 * Take HW scaling into consideration
+	 */
+	cfg.cir = cfg.cir * NSS_PPE_HW_FREQ_SCALING;
+	cfg.eir = cfg.eir * NSS_PPE_HW_FREQ_SCALING;
+
+	nss_qdisc_trace("SSDK flow shaper configuration: l0spid:%u, couple_en:%u, meter_unit:%u, c_shaper_en:%u, cbs:%u, cir:%u, ebs:%u, eir:%u, shaper_frame_mode:%u\n",
+		npq->l0spid, cfg.couple_en, cfg.meter_unit, cfg.c_shaper_en, cfg.cbs, cfg.cir, cfg.ebs, cfg.eir, cfg.shaper_frame_mode);
+	if (fal_flow_shaper_set(0, npq->l0spid, &cfg) != 0) {
+		nss_qdisc_error("SSDK flow shaper configuration failed for port:%d, l0spid:%d\n",
+			port_num, npq->l0spid);
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("SSDK flow shaper configuration successful for port:%d\n", port_num);
+	return 0;
+}
+
+/*
+ * nss_ppe_queue_shaper_reset()
+ *	Resets a queue shaper in SSDK.
+ */
+static int nss_ppe_queue_shaper_reset(struct nss_qdisc *nq)
+{
+	fal_shaper_config_t cfg;
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	/*
+	 * Reset queue shaper configuration
+	 */
+	memset(&cfg, 0, sizeof(cfg));
+	nss_qdisc_trace("SSDK queue shaper reset : ucast_qid:%d\n", npq->q.ucast_qid);
+	if (fal_queue_shaper_set(0, npq->q.ucast_qid, &cfg) != 0) {
+		nss_qdisc_error("SSDK queue shaper configuration failed for port:%d, ucast_qid:%d\n",
+			port_num, npq->q.ucast_qid);
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("SSDK queue shaper configuration successful for port:%d\n",
+		port_num);
+	return 0;
+}
+
+/*
+ * nss_ppe_queue_shaper_set()
+ *	Configures a queue shaper in SSDK.
+ */
+static int nss_ppe_queue_shaper_set(struct nss_qdisc *nq)
+{
+	fal_shaper_token_number_t token;
+	fal_shaper_config_t cfg;
+	uint32_t port_num __maybe_unused = nss_ppe_port_num_get(nq);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	/*
+	 * Set queue shaper token number
+	 */
+	memset(&token, 0, sizeof(token));
+	token.c_token_number = NSS_PPE_TOKEN_MAX;
+	token.e_token_number = NSS_PPE_TOKEN_MAX;
+
+	nss_qdisc_trace("SSDK queue token set : ucast_qid:%d, c_token_number:%x, e_token_number:%x\n",
+		npq->q.ucast_qid, token.c_token_number, token.e_token_number);
+	if (fal_queue_shaper_token_number_set(0, npq->q.ucast_qid, &token) != 0) {
+		nss_qdisc_error("SSDK queue shaper token configuration failed\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Set queue shaper confguration
+	 * Note: SSDK API requires burst in bytes/sec
+	 * while rate in kbits/sec.
+	 */
+	cfg.couple_en = 0;
+	cfg.meter_unit = 0;
+	cfg.c_shaper_en = 1;
+	cfg.cbs = npq->shaper.burst;
+	cfg.cir = (npq->shaper.rate / 1000) * 8;
+	cfg.e_shaper_en = 1;
+	cfg.ebs = npq->shaper.cburst;
+	cfg.eir = ((npq->shaper.crate / 1000) * 8) - cfg.cir;
+	cfg.shaper_frame_mode = NSS_PPE_FRAME_CRC;
+
+	/*
+	 * Take HW scaling into consideration
+	 */
+	cfg.cir = cfg.cir * NSS_PPE_HW_FREQ_SCALING;
+	cfg.eir = cfg.eir * NSS_PPE_HW_FREQ_SCALING;
+
+	nss_qdisc_trace("SSDK queue shaper configuration: ucast_qid:%u, couple_en:%u, meter_unit:%u, c_shaper_en:%u, cbs:%u, cir:%u, ebs:%u, eir:%u, shaper_frame_mode:%u\n",
+		npq->q.ucast_qid, cfg.couple_en, cfg.meter_unit, cfg.c_shaper_en, cfg.cbs, cfg.cir, cfg.ebs, cfg.eir, cfg.shaper_frame_mode);
+	if (fal_queue_shaper_set(0, npq->q.ucast_qid, &cfg) != 0) {
+		nss_qdisc_error("SSDK queue shaper configuration failed\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * This function is called at the time of class allocation and change at
+	 * NSS_PPE_QUEUE_LEVEL. But, mcast will be valid only in case queue
+	 * is attached at NSS_PPE_SUB_QUEUE_LEVEL and change class is invoked
+	 * at NSS_PPE_QUEUE_LEVEL level.
+	 * Other scenarios catering to mcast queue are handled in separate mcast APIs.
+	 */
+	if (npq->q.mcast_qid) {
+		nss_qdisc_trace("SSDK multicast queue shaper configuration: mcast_qid:%u, couple_en:%u, meter_unit:%u, c_shaper_en:%u, cbs:%u, cir:%u, ebs:%u, eir:%u, shaper_frame_mode:%u\n",
+			npq->q.mcast_qid, cfg.couple_en, cfg.meter_unit, cfg.c_shaper_en, cfg.cbs, cfg.cir, cfg.ebs, cfg.eir, cfg.shaper_frame_mode);
+		if (fal_queue_shaper_set(0, npq->q.mcast_qid, &cfg) != 0) {
+			nss_qdisc_error("SSDK multicast queue shaper configuration failed\n");
+			return -EINVAL;
+		}
+	}
+
+	nss_qdisc_info("SSDK queue shaper configuration successful for port:%d\n", port_num);
+	return 0;
+}
+
+/*
+ * nss_ppe_max_level_get()
+ *	Returns the max configuration level for the given prot.
+ */
+static int nss_ppe_max_level_get(struct nss_qdisc *nq)
+{
+	int level = NSS_PPE_MAX_LEVEL;
+
+	/*
+	 * Loopback uses one level.
+	 */
+	if (nq->needs_ppe_loopback) {
+		level = level - 1;
+	}
+
+	nss_qdisc_info("level:%d\n", level);
+	return level;
+}
+
+/*
+ * nss_ppe_attach_free()
+ *	Attaches a resource to free list.
+ */
+static void nss_ppe_attach_free(uint32_t port, struct nss_ppe_res *res)
+{
+	struct nss_ppe_port *ppe_port = &ppe_qdisc_port[port];
+
+	spin_lock_bh(&ppe_port->lock);
+	res->next = ppe_port->res_free[res->type];
+	ppe_port->res_free[res->type] = res;
+	spin_unlock_bh(&ppe_port->lock);
+
+	nss_qdisc_info("port:%d, type:%d, res:%px\n", port, res->type, res);
+	return;
+}
+
+/*
+ * nss_ppe_base_get()
+ *	Returns base of the particular resource for a given port.
+ */
+uint32_t nss_ppe_base_get(uint32_t port, nss_ppe_res_type_t type)
+{
+	uint32_t base = 0;
+	struct nss_ppe_port *ppe_port = &ppe_qdisc_port[port];
+
+	spin_lock_bh(&ppe_port->lock);
+	base = ppe_port->base[type];
+	spin_unlock_bh(&ppe_port->lock);
+
+	nss_qdisc_info("port:%d, type:%d, base:%d\n", port, type, base);
+	return base;
+}
+
+/*
+ * nss_ppe_res_free()
+ *	Frees the allocated resource and attach it to free list.
+ */
+int nss_ppe_res_free(uint32_t port, uint32_t offset, nss_ppe_res_type_t type)
+{
+	struct nss_ppe_res *temp = NULL;
+	struct nss_ppe_res *res = NULL;
+	struct nss_ppe_port *ppe_port = &ppe_qdisc_port[port];
+
+	if (type >= NSS_PPE_MAX_RES_TYPE) {
+		nss_qdisc_assert(false, "Resource type:%d not valid for port:%d", type, port);
+		return -1;
+	}
+
+	spin_lock_bh(&ppe_port->lock);
+	res = ppe_port->res_used[type];
+	if (res->offset == offset) {
+		ppe_port->res_used[type] = res->next;
+		res->next = NULL;
+		spin_unlock_bh(&ppe_port->lock);
+		goto success;
+	}
+
+	temp = res;
+	res = res->next;
+
+	while (res) {
+		if (res->offset == offset) {
+			temp->next = res->next;
+			res->next = NULL;
+			break;
+		} else {
+			temp = res;
+			res = res->next;
+		}
+	}
+	spin_unlock_bh(&ppe_port->lock);
+
+	if (!res) {
+		nss_qdisc_assert(false, "Resource:%d type:%d not found for port:%d", offset, type, port);
+		return -1;
+	}
+
+success:
+	nss_ppe_attach_free(port, res);
+	nss_qdisc_info("port:%d, type:%d, res:%px\n", port, type, res);
+	return 0;
+}
+
+/*
+ * nss_ppe_res_alloc()
+ *	Allocates free resource for a given port.
+ */
+struct nss_ppe_res *nss_ppe_res_alloc(uint32_t port, nss_ppe_res_type_t type)
+{
+	struct nss_ppe_res *res = NULL;
+	struct nss_ppe_port *ppe_port = &ppe_qdisc_port[port];
+
+	/*
+	 * Detach the resource from free list
+	 * and attach to used list.
+	 */
+	spin_lock_bh(&ppe_port->lock);
+	res = ppe_port->res_free[type];
+	if (res) {
+		ppe_port->res_free[type] = res->next;
+		res->next = ppe_port->res_used[type];
+		ppe_port->res_used[type] = res;
+	}
+	spin_unlock_bh(&ppe_port->lock);
+
+	nss_qdisc_info("port:%d, type:%d, res:%px\n", port, type, res);
+	return res;
+}
+
+/*
+ * nss_ppe_default_conf_set()
+ *	Sets default queue scheduler in SSDK.
+ */
+static int nss_ppe_default_conf_set(uint32_t port_num)
+{
+	fal_qos_scheduler_cfg_t l0cfg;
+	fal_ac_obj_t obj;
+	fal_ac_ctrl_t cfg;
+	uint32_t l0spid;
+	uint32_t ucast_qid;
+	uint32_t mcast_qid;
+
+	/*
+	 * Disable all queues and set SSDK configuration
+	 * We need to disable and flush the queues before
+	 * reseting to the default configuration.
+	 */
+	nss_ppe_all_queue_disable(port_num);
+
+	/*
+	 * No resources were allocated for Port 0 (Loopback port).
+	 * L1 scheduler was configured at init time.
+	 */
+	if (port_num == 0) {
+		l0spid = NSS_PPE_LOOPBACK_L0_SP_BASE;
+		goto conf;
+	}
+
+	/*
+	 * Invoke SSDK API to reset the default configuration for a given port.
+	 */
+	if (fal_port_scheduler_cfg_reset(0, port_num) != 0) {
+		nss_qdisc_error("SSDK reset default queue configuration failed\n");
+		nss_ppe_all_queue_enable(port_num);
+		return -EINVAL;
+	}
+
+	nss_ppe_all_queue_enable(port_num);
+
+	nss_qdisc_info("SSDK queue configuration successful\n");
+	return 0;
+
+conf:
+	/*
+	 * Reset Level 0 Configuration
+	 * We are not using SSDK reset API for port 0 as
+	 * only 16 queues from this port are used for QoS.
+	 */
+	memset(&l0cfg, 0, sizeof(l0cfg));
+	l0cfg.sp_id = l0spid;
+	l0cfg.c_pri = NSS_PPE_PRIORITY_MAX;
+	l0cfg.e_pri = NSS_PPE_PRIORITY_MAX;
+	l0cfg.c_drr_wt = 1;
+	l0cfg.e_drr_wt = 1;
+	l0cfg.c_drr_id = nss_ppe_base_get(port_num, NSS_PPE_L0_CDRR);
+	l0cfg.e_drr_id = nss_ppe_base_get(port_num, NSS_PPE_L0_EDRR);
+	ucast_qid = nss_ppe_base_get(port_num, NSS_PPE_UCAST_QUEUE);
+	mcast_qid = nss_ppe_base_get(port_num, NSS_PPE_MCAST_QUEUE);
+
+	nss_qdisc_trace("SSDK level0 configuration: Port:%d, ucast_qid:%d, c_drrid:%d, c_pri:%d, c_drr_wt:%d, e_drrid:%d, e_pri:%d, e_drr_wt:%d, l0spid:%d\n",
+			port_num, ucast_qid, l0cfg.c_drr_id, l0cfg.c_pri, l0cfg.c_drr_wt, l0cfg.e_drr_id, l0cfg.e_pri, l0cfg.e_drr_wt, l0cfg.sp_id);
+	if (fal_queue_scheduler_set(0, ucast_qid, NSS_PPE_QUEUE_LEVEL - 1, port_num, &l0cfg) != 0) {
+		nss_qdisc_error("SSDK level0 queue scheduler configuration failed\n");
+		nss_ppe_all_queue_enable(port_num);
+		return -EINVAL;
+	}
+
+	nss_qdisc_trace("SSDK level0 configuration: Port:%d, mcast_qid:%d, c_drrid:%d, c_pri:%d, c_drr_wt:%d, e_drrid:%d, e_pri:%d, e_drr_wt:%d, l0spid:%d\n",
+			port_num, mcast_qid, l0cfg.c_drr_id, l0cfg.c_pri, l0cfg.c_drr_wt, l0cfg.e_drr_id, l0cfg.e_pri, l0cfg.e_drr_wt, l0cfg.sp_id);
+	if (fal_queue_scheduler_set(0, mcast_qid, NSS_PPE_QUEUE_LEVEL - 1, port_num, &l0cfg) != 0) {
+		nss_qdisc_error("SSDK level0 queue scheduler configuration failed\n");
+		nss_ppe_all_queue_enable(port_num);
+		return -EINVAL;
+	}
+
+	memset(&obj, 0, sizeof(obj));
+	obj.obj_id = ucast_qid;
+	fal_ac_prealloc_buffer_set(0, &obj, 0);
+	obj.obj_id = mcast_qid;
+	fal_ac_prealloc_buffer_set(0, &obj, 0);
+
+	/*
+	 * Disable force drop.
+	 * Setting ac_fc_en as 0 means queue will
+	 * honor flow control.
+	 */
+	memset(&cfg, 0, sizeof(cfg));
+	obj.obj_id = ucast_qid;
+	cfg.ac_en = 1;
+	nss_qdisc_trace("SSDK queue flow control set: ucast_qid:%d, enable:%d\n", ucast_qid, cfg.ac_fc_en);
+	if (fal_ac_ctrl_set(0, &obj, &cfg) != 0) {
+		nss_qdisc_error("SSDK queue flow control set failed\n");
+		nss_ppe_all_queue_enable(port_num);
+		return -EINVAL;
+	}
+
+	nss_ppe_all_queue_enable(port_num);
+
+	nss_qdisc_info("SSDK queue configuration successful\n");
+	return 0;
+}
+
+/*
+ * nss_ppe_queue_limit_set()
+ *	Sets queue size in SSDK.
+ */
+static int nss_ppe_queue_limit_set(struct nss_qdisc *nq)
+{
+	fal_ac_obj_t obj;
+	fal_ac_static_threshold_t cfg;
+	fal_ac_ctrl_t ctrl_cfg;
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	if (!npq->q.ucast_valid) {
+		return 0;
+	}
+
+	/*
+	 * Unicast queue configuration.
+	 */
+	memset(&obj, 0, sizeof(obj));
+	obj.obj_id = npq->q.ucast_qid;
+
+	nss_qdisc_trace("SSDK queue buffer set: ucast_qid:%d, qlimit:%d\n", npq->q.ucast_qid, npq->q.qlimit);
+	if (fal_ac_prealloc_buffer_set(0, &obj, npq->q.qlimit) != 0) {
+		nss_qdisc_error("SSDK queue configuration failed\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Enable force drop for PPE qdisc.
+	 * When set to 1, the flow control will be overriden
+	 * for that queue and packets drop gets enabled.
+	 */
+	memset(&ctrl_cfg, 0, sizeof(ctrl_cfg));
+	ctrl_cfg.ac_en = 1;
+	if (nq->mode == NSS_QDISC_MODE_PPE) {
+		ctrl_cfg.ac_fc_en = 1;
+	}
+
+	nss_qdisc_trace("SSDK queue flow control set: ucast_qid:%d, enable:%d\n", npq->q.ucast_qid, ctrl_cfg.ac_fc_en);
+	if (fal_ac_ctrl_set(0, &obj, &ctrl_cfg) != 0) {
+		nss_qdisc_error("SSDK queue flow control set failed\n");
+		return -EINVAL;
+	}
+
+	memset(&cfg, 0, sizeof(cfg));
+	cfg.wred_enable = npq->q.red_en;
+	cfg.green_max = npq->q.max_th[NSS_PPE_COLOR_GREEN];
+	cfg.green_min_off = npq->q.min_th[NSS_PPE_COLOR_GREEN];
+	nss_qdisc_trace("SSDK queue ac threshold set: ucast_qid:%d, wred_enable:%d, green_max:%d, green_min_off:%d\n",
+		npq->q.ucast_qid, cfg.wred_enable, cfg.green_max, cfg.green_min_off);
+	if (fal_ac_static_threshold_set(0, &obj, &cfg) != 0) {
+		nss_qdisc_error("SSDK queue configuration failed\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Multicast queue configuration.
+	 */
+	if (npq->q.mcast_valid) {
+		obj.obj_id = npq->q.mcast_qid;
+
+		nss_qdisc_trace("SSDK multicast queue buffer set: mcast_qid:%d, qlimit:%d\n", npq->q.mcast_qid, npq->q.qlimit);
+		if (fal_ac_prealloc_buffer_set(0, &obj, npq->q.qlimit) != 0) {
+			nss_qdisc_error("SSDK multicast queue configuration failed\n");
+			return -EINVAL;
+		}
+
+		nss_qdisc_trace("SSDK multicast queue ac threshold set: mcast_qid:%d, wred_enable:%d, green_max:%d, green_min_off:%d\n",
+			npq->q.mcast_qid, cfg.wred_enable, cfg.green_max, cfg.green_min_off);
+		if (fal_ac_static_threshold_set(0, &obj, &cfg) != 0) {
+			nss_qdisc_error("SSDK multicast queue configuration failed\n");
+			return -EINVAL;
+		}
+	}
+
+	nss_qdisc_info("SSDK queue configuration successful\n");
+	return 0;
+}
+
+/*
+ * nss_ppe_scheduler_reset()
+ *	Resets a configured scheduler in SSDK.
+ */
+static int nss_ppe_scheduler_reset(struct nss_qdisc *nq)
+{
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	if ((!npq->l0_valid) && (!npq->l1_valid)) {
+		return 0;
+	}
+
+	if (npq->level == NSS_PPE_PORT_LEVEL) {
+		if (!nss_ppe_sub_type_is_queue(npq)) {
+			nss_qdisc_info("SSDK reset scheduler successful\n");
+			return 0;
+		}
+
+		if (nss_ppe_l0_queue_scheduler_reset(nq) != 0) {
+			nss_qdisc_warning("SSDK Level0 queue scheduler reset failed\n");
+			return -EINVAL;
+		}
+
+		if (nss_ppe_l1_res_free(nq) != 0) {
+			nss_qdisc_warning("SSDK Level1 queue scheduler reset failed\n");
+			return -EINVAL;
+		}
+
+		nss_qdisc_info("SSDK reset scheduler successful\n");
+		return 0;
+	}
+
+	if (npq->level == NSS_PPE_FLOW_LEVEL) {
+
+		/*
+		 * We have allocated L0 resources if this qdisc is of type queue or
+		 * this is an hybrid (NSS) qdisc that is attached to PPE qdisc.
+		 */
+		if ((nss_ppe_sub_type_is_queue(npq)) || (nq->mode == NSS_QDISC_MODE_NSS)) {
+			if (nss_ppe_l0_queue_scheduler_reset(nq) < 0) {
+				nss_qdisc_warning("SSDK Level0 configuration for attach of new qdisc failed\n");
+				return -EINVAL;
+			}
+		}
+
+		if (nss_ppe_l1_res_free(nq) != 0) {
+			nss_qdisc_warning("SSDK Level1 queue scheduler reset failed\n");
+			return -EINVAL;
+		}
+	} else if (npq->level == NSS_PPE_QUEUE_LEVEL) {
+		if (nss_ppe_l0_queue_scheduler_reset(nq) != 0) {
+			nss_qdisc_warning("SSDK Level0 queue scheduler reset failed\n");
+			return -EINVAL;
+		}
+	} else {
+
+		/*
+		 * When a classful qdisc say HTB is configured with max levels of hierarchy,
+		 * and then if a qdisc say FIFO is attached at the last level, we will have all
+		 * the resources allocated and we just need to enable/disable the queue.
+		 */
+		nss_ppe_queue_disable(nq);
+	}
+
+	nss_qdisc_info("SSDK reset scheduler successful\n");
+	return 0;
+}
+
+/*
+ * nss_ppe_scheduler_set()
+ *	Configures a scheduler in SSDK.
+ */
+static int nss_ppe_scheduler_set(struct nss_qdisc *nq)
+{
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	if (npq->level == NSS_PPE_PORT_LEVEL) {
+
+		/*
+		 * Only L1 SP can be allocated at port level if qdisc is not of type queue.
+		 * Since L1 SP is equal to port number, we don't explicitly allocate it.
+		 */
+		if (!nss_ppe_sub_type_is_queue(npq)) {
+			nss_qdisc_info("SSDK scheduler configuration successful\n");
+			return 0;
+		}
+
+		/*
+		 * Set queue schedulers for queue qdiscs attached at port level.
+		 */
+		if (nss_ppe_l1_queue_scheduler_set(nq) < 0) {
+			nss_qdisc_warning("SSDK Level1 configuration failed\n");
+			return -EINVAL;
+		}
+
+		if (nss_ppe_l0_queue_scheduler_set(nq) < 0) {
+			nss_ppe_l1_res_free(nq);
+			nss_qdisc_warning("SSDK Level0 configuration failed\n");
+			return -EINVAL;
+		}
+
+		nss_qdisc_info("SSDK scheduler configuration successful\n");
+		return 0;
+	}
+
+	if (npq->level == NSS_PPE_FLOW_LEVEL) {
+		if (nss_ppe_l1_queue_scheduler_set(nq) < 0) {
+			nss_qdisc_warning("SSDK Level1 configuration failed\n");
+			return -EINVAL;
+		}
+
+		/*
+		 * We need to allocate L0 resources as well if qdisc is of type queue or
+		 * we are attaching a hybrid (NSS) qdisc to PPE qdisc.
+		 */
+		if ((nss_ppe_sub_type_is_queue(npq)) || (nq->mode == NSS_QDISC_MODE_NSS)) {
+			if (nss_ppe_l0_queue_scheduler_set(nq) < 0) {
+				nss_qdisc_warning("SSDK Level0 configuration failed\n");
+				return -EINVAL;
+			}
+		}
+	} else if (npq->level == NSS_PPE_QUEUE_LEVEL) {
+
+		/*
+		 * This case is invoked when a Qdisc/class is attached/changed
+		 * at queue level. If a class is attached at queue level, we
+		 * disable the queue until a qdisc is attached. but if it is
+		 * invoked at change configuration time, we just set the schedulers.
+		 */
+		if (nss_ppe_l0_queue_scheduler_set(nq) < 0) {
+			nss_qdisc_warning("SSDK Level0 configuration failed\n");
+			return -EINVAL;
+		}
+
+		if ((!npq->is_configured) && (!nss_ppe_sub_type_is_queue(npq))) {
+			nss_ppe_queue_disable(nq);
+		}
+	} else {
+		/*
+		 * When a classful qdisc say HTB is configured with max levels of hierarchy,
+		 * and then if a qdisc say FIFO is attached at the last level, we will have all
+		 * the resources allocated and we just need to enable/disable the queue.
+		 */
+		nss_ppe_queue_enable(nq);
+	}
+
+	nss_qdisc_info("SSDK scheduler configuration successful\n");
+	return 0;
+}
+
+/*
+ * nss_ppe_shaper_reset()
+ *	Resets a configured shaper in SSDK.
+ */
+static int nss_ppe_shaper_reset(struct nss_qdisc *nq)
+{
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	if (!npq->shaper_present) {
+		return 0;
+	}
+
+	if (npq->level == NSS_PPE_PORT_LEVEL) {
+		if (nss_ppe_port_shaper_reset(nq) != 0) {
+				nss_qdisc_warning("Reset Port shaper failed\n");
+			return -EINVAL;
+		}
+		nss_qdisc_info("SSDK reset shaper successful\n");
+		return 0;
+	}
+
+	if (npq->level == NSS_PPE_FLOW_LEVEL) {
+		if (nss_ppe_flow_shaper_reset(nq) != 0) {
+			nss_qdisc_warning("Reset Flow shaper failed\n");
+			return -EINVAL;
+		}
+		nss_qdisc_info("SSDK reset shaper successful\n");
+		return 0;
+	}
+
+	if (npq->level == NSS_PPE_QUEUE_LEVEL) {
+		if (nss_ppe_queue_shaper_reset(nq) != 0) {
+			nss_qdisc_warning("Reset Queue shaper failed\n");
+			return -EINVAL;
+		}
+	}
+
+	npq->shaper_present = false;
+
+	nss_qdisc_info("SSDK reset shaper successful\n");
+	return 0;
+}
+
+/*
+ * nss_ppe_shaper_set()
+ *	Configures a shaper in SSDK.
+ */
+static int nss_ppe_shaper_set(struct nss_qdisc *nq)
+{
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	if (!npq->shaper_present) {
+		return 0;
+	}
+
+	if (npq->level == NSS_PPE_PORT_LEVEL) {
+		if (nss_ppe_port_shaper_set(nq) != 0) {
+			nss_qdisc_warning("Port shaper configuration failed\n");
+			return -EINVAL;
+		}
+		nss_qdisc_info("SSDK set shaper successful\n");
+		return 0;
+	}
+
+	if (npq->level == NSS_PPE_FLOW_LEVEL) {
+		if (nss_ppe_flow_shaper_set(nq) != 0) {
+			nss_qdisc_warning("Port shaper configuration failed\n");
+			return -EINVAL;
+		}
+		nss_qdisc_info("SSDK set shaper successful\n");
+		return 0;
+	}
+
+	if (npq->level == NSS_PPE_QUEUE_LEVEL) {
+		if (nss_ppe_queue_shaper_set(nq) != 0) {
+			nss_qdisc_warning("Queue shaper configuration failed\n");
+			return -EINVAL;
+		}
+	}
+
+	nss_qdisc_info("SSDK set shaper successful\n");
+	return 0;
+}
+
+/*
+ * nss_ppe_set_parent()
+ *	Sets the parent of given qdisc.
+ */
+int nss_ppe_set_parent(struct Qdisc *sch, struct nss_qdisc *nq, uint32_t parent)
+{
+	struct net_device *dev = qdisc_dev(sch);
+	struct nss_qdisc *parent_nq = NULL;
+	struct Qdisc *parent_qdisc = NULL;
+	unsigned long parent_class = 0;
+
+	/*
+	 * PPE Qdisc cannot be attached to NSS Qdisc.
+	 */
+	if (parent != TC_H_ROOT) {
+		parent_qdisc = qdisc_lookup(dev, TC_H_MAJ(parent));
+		parent_nq = qdisc_priv(parent_qdisc);
+	} else if (nq->is_class) {
+		parent_nq = qdisc_priv(nq->qdisc);
+	}
+
+	if ((parent_nq) && (parent_nq->mode == NSS_QDISC_MODE_NSS)) {
+		nss_qdisc_info("HW qdisc/class %px cannot be attached to nss qdisc/class\n", nq->qdisc);
+		return NSS_PPE_QDISC_PARENT_NOT_PPE;
+	}
+
+	/*
+	 * Set the parent if current Qdisc is not a class.
+	 * For class, parent is set before invoking nss_qdisc_init in respective qdisc files.
+	 */
+	if ((parent_nq) && (!nq->is_class)) {
+		nq->parent = parent_nq;
+
+		/*
+		 * If parent is a class.
+		 *
+		 * Though PRIO is classless but PRIO bands are treated as classes by Qdisc
+		 * infrastructure i.e TC_H_MIN(parent) is true for PRIO band.
+		 * But, we donot allocate any resources for PRIO bands separately so in
+		 * case of any qdisc attached to PRIO band, the parent is set as PRIO qdisc itself.
+		 * And the below class check is applicable only for the classful qdiscs.
+		 */
+		if ((parent_nq) && (parent_nq->npq.sub_type != NSS_SHAPER_CONFIG_PPE_SN_TYPE_PRIO) && (TC_H_MIN(parent))) {
+			if (!parent_qdisc) {
+				nss_qdisc_info("HW qdisc/class %px cannot be attached to non-existing class %x\n", nq->qdisc, parent);
+				return NSS_PPE_QDISC_PARENT_NOT_EXISTING;
+			}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0))
+			parent_class = parent_qdisc->ops->cl_ops->get(parent_qdisc, parent);
+#else
+			parent_class = parent_qdisc->ops->cl_ops->find(parent_qdisc, parent);
+#endif
+			if (!parent_class) {
+				nq->parent = NULL;
+				nss_qdisc_info("HW qdisc/class %px cannot be attached to non-existing class %x\n", nq->qdisc, parent);
+				return NSS_PPE_QDISC_PARENT_NOT_EXISTING;
+
+			}
+
+			nq->parent = (struct nss_qdisc *)parent_class;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0))
+			parent_qdisc->ops->cl_ops->put(parent_qdisc, parent_class);
+#endif
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ppe_get_max_prio_bands()
+ *	Returns the number of PRIO bands supported based on qdisc level.
+ */
+int nss_ppe_get_max_prio_bands(struct nss_qdisc *nq)
+{
+	nss_ppe_level_t level = nq->npq.level;
+
+	switch (level) {
+	case NSS_PPE_PORT_LEVEL:
+		return NSS_PPE_PORT_LEVEL_PRIO_BANDS_MAX;
+
+	case NSS_PPE_FLOW_LEVEL:
+		return NSS_PPE_FLOW_LEVEL_PRIO_BANDS_MAX;
+
+	default:
+		nss_qdisc_warning("HW Qdisc not supported at this level\n");
+		return 0;
+	}
+}
+
+/*
+ * nss_ppe_is_depth_valid()
+ *	Checks the depth of Qdisc tree.
+ */
+static int nss_ppe_is_depth_valid(struct nss_qdisc *nq)
+{
+	enum nss_shaper_config_ppe_sn_type sub_type = nq->npq.sub_type;
+	nss_ppe_level_t valid_level;
+	nss_qdisc_trace("level:%d\n", nq->npq.level);
+
+	switch (sub_type) {
+	case NSS_SHAPER_CONFIG_PPE_SN_TYPE_FIFO:
+	case NSS_SHAPER_CONFIG_PPE_SN_TYPE_RED:
+		valid_level = NSS_PPE_SUB_QUEUE_LEVEL;
+		break;
+
+	case NSS_SHAPER_CONFIG_PPE_SN_TYPE_HTB:
+	case NSS_SHAPER_CONFIG_PPE_SN_TYPE_WRR:
+	case NSS_SHAPER_CONFIG_PPE_SN_TYPE_PRIO:
+		valid_level = NSS_PPE_FLOW_LEVEL;
+		break;
+
+	case NSS_SHAPER_CONFIG_PPE_SN_TYPE_HTB_GROUP:
+	case NSS_SHAPER_CONFIG_PPE_SN_TYPE_TBL:
+	case NSS_SHAPER_CONFIG_PPE_SN_TYPE_WRR_GROUP:
+		valid_level = NSS_PPE_QUEUE_LEVEL;
+		break;
+
+	default:
+		nss_qdisc_warning("HW Qdisc not supported\n");
+		return false;
+	}
+
+	if (nq->npq.level < valid_level) {
+		nss_qdisc_warning("sub_type:%d not supported at level:%d\n", sub_type, nq->npq.level);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_ppe_drr_weight_get()
+ *	Returns the DRR weight corresponding to quantum.
+ */
+int nss_ppe_drr_weight_get(uint32_t quantum, nss_ppe_drr_unit_t drr_unit)
+{
+	switch (drr_unit) {
+	case NSS_PPE_DRR_UNIT_BYTE:
+		if (quantum < NSS_PPE_DRR_WEIGHT_MAX) {
+			return 1;
+		} else {
+			return quantum / NSS_PPE_DRR_WEIGHT_MAX;
+		}
+
+	case NSS_PPE_DRR_UNIT_PACKET:
+		return quantum;
+
+	default:
+		nss_qdisc_warning("DRR unit %d not supported\n", drr_unit);
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ppe_port_num_get()
+ *	Returns the port number.
+ */
+int nss_ppe_port_num_get(struct nss_qdisc *nq)
+{
+	int port_num = 0;
+
+	/*
+	 * Fetch port number based on interface type.
+	 * TODO: Change this when API from DP is available
+	 */
+	if (!nq->needs_ppe_loopback) {
+		port_num = nq->nss_interface_number;
+	}
+
+	nss_qdisc_info("port:%d\n", port_num);
+	return port_num;
+}
+
+/*
+ * nss_ppe_all_queue_enable_hybrid()
+ *	Enables PPE queues when NSS queuing Qdiscs are attached in the hieracrchy.
+ */
+void nss_ppe_all_queue_enable_hybrid(struct nss_qdisc *nq)
+{
+	struct nss_qdisc *nq_root = qdisc_priv(qdisc_root(nq->qdisc));
+
+	if (!nq_root->hybrid_configured) {
+		return;
+	}
+
+	/*
+	 * In case of hybrid mode, we disable the PPE queues until
+	 * queueing Qdisc is attached in the hierarchy.
+	 */
+	if((nq->type == NSS_SHAPER_NODE_TYPE_CODEL)
+		|| (nq->type == NSS_SHAPER_NODE_TYPE_FIFO)
+		|| (nq->type == NSS_SHAPER_NODE_TYPE_BF)
+		|| (nq->type == NSS_SHAPER_NODE_TYPE_WRED)) {
+		uint32_t port_num = nss_ppe_port_num_get(nq);
+		nss_ppe_all_queue_enable(port_num);
+		nss_qdisc_info("Queues in hybrid mode enabled successfully for Qdisc %px (type %d)\n", nq, nq->type);
+	}
+}
+
+/*
+ * nss_ppe_node_detach()
+ *	Configuration function that helps detach a child shaper node from a parent.
+ */
+int nss_ppe_node_detach(struct nss_qdisc *nq, struct nss_qdisc *nq_child)
+{
+	struct nss_qdisc *nq_root = qdisc_priv(qdisc_root(nq->qdisc));
+
+	/*
+	 * If child qdisc is of type NSS, reset the hybrid mode and
+	 * hybrid_configured flag.
+	 */
+	if (nq_child->mode != NSS_QDISC_MODE_PPE) {
+		if (nss_qdisc_set_hybrid_mode(nq_child, NSS_QDISC_HYBRID_MODE_DISABLE, 0) < 0) {
+			nss_qdisc_warning("detach of old qdisc %px failed\n", nq_child->qdisc);
+			return -EINVAL;
+		}
+
+		nq_root->hybrid_configured = false;
+	}
+
+	nss_ppe_destroy(nq_child);
+
+	nss_qdisc_info("Qdisc:%px, node:%px\n", nq, nq_child);
+	return 0;
+}
+
+/*
+ * nss_ppe_node_attach()
+ *	Configuration function that helps attach a child shaper node to a parent.
+ */
+int nss_ppe_node_attach(struct nss_qdisc *nq, struct nss_qdisc *nq_child)
+{
+	struct net_device *dev = qdisc_dev(nq_child->qdisc);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+	struct nss_ppe_qdisc *npq_child = &nq_child->npq;
+	int ucast_qbase = nss_ppe_base_get(nss_ppe_port_num_get(nq), NSS_PPE_UCAST_QUEUE);
+	struct nss_qdisc *nq_root = qdisc_priv(qdisc_root(nq->qdisc));
+
+	/*
+	 * Configuration is not required if child node is a class.
+	 */
+	if (nq_child->is_class)  {
+		return 0;
+	}
+
+	/*
+	 * In case of chile attached to PRIO qdisc, scheduler configuration is
+	 * required to set the priority of child qdisc in SSDK.
+	 */
+	if (nq->npq.sub_type == NSS_SHAPER_CONFIG_PPE_SN_TYPE_PRIO) {
+		if (nss_ppe_scheduler_set(nq_child) != 0)  {
+			nss_qdisc_warning("SSDK scheduler configuration failed\n");
+			return -EINVAL;
+		}
+	}
+
+	if (nq_child->mode == NSS_QDISC_MODE_PPE) {
+		return 0;
+	}
+
+	/*
+	 * Return error in case NSS Qdisc is attached to loopback.
+	 */
+	if (nq->needs_ppe_loopback) {
+		nss_qdisc_warning("NSS Qdisc cannot be attached to PPE Qdisc on loopback interface.\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Return error if hybrid QoS is already configured on the port.
+	 */
+	if (nq_root->hybrid_configured) {
+		nss_qdisc_warning("More than one NSS qdisc cannot be attached to PPE qdsic.\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * If new qdisc is not of type PPE, then configure a simple fifo
+	 * queue in HW. This is where packets coming from the Adv QoS
+	 * portion of the tree will get enqueued to.
+	 */
+	nq_child->parent = nq;
+	npq_child->level = npq->level - 1;
+
+	if (npq_child->level == NSS_PPE_SUB_QUEUE_LEVEL) {
+		npq_child->q.ucast_valid = npq->q.ucast_valid;
+		npq_child->q.ucast_qid = npq->q.ucast_qid;
+	}
+
+	npq->q.qlimit = dev->tx_queue_len ? : 1;
+	if (nss_ppe_scheduler_set(nq_child) < 0) {
+		nss_qdisc_warning("SSDK scheduler configuration failed\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Program PPE queue parameters
+	 */
+	if (nss_ppe_queue_limit_set(nq_child) < 0) {
+		nss_qdisc_warning("SSDK queue configuration failed\n");
+		nss_ppe_mcast_queue_reset(nq_child);
+		nss_ppe_scheduler_reset(nq_child);
+		return -EINVAL;
+	}
+
+	if (nss_qdisc_set_hybrid_mode(nq_child, NSS_QDISC_HYBRID_MODE_ENABLE, npq_child->q.ucast_qid - ucast_qbase) < 0) {
+		nss_qdisc_warning("nss qdisc configuration failed\n");
+		nss_ppe_mcast_queue_reset(nq_child);
+		nss_ppe_scheduler_reset(nq_child);
+		return -EINVAL;
+	}
+
+	nq_root->hybrid_configured = true;
+
+	nss_qdisc_info("Qdisc:%px, node:%px\n", nq, nq_child);
+	return 0;
+}
+
+/*
+ * nss_ppe_configure()
+ *	Configures the SSDK schedulers and NSS shapers.
+ */
+int nss_ppe_configure(struct nss_qdisc *nq, struct nss_ppe_qdisc *prev_npq)
+{
+	struct nss_if_msg nim;
+	int ucast_qbase = nss_ppe_base_get(nss_ppe_port_num_get(nq), NSS_PPE_UCAST_QUEUE);
+	int mcast_qbase = nss_ppe_base_get(nss_ppe_port_num_get(nq), NSS_PPE_MCAST_QUEUE);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+	/*
+	 * Change the configuration in SSDK
+	 */
+	if (nss_ppe_scheduler_set(nq) != 0)  {
+		nss_qdisc_warning("SSDK scheduler configuration failed\n");
+		goto fail;
+	}
+
+	if (nss_ppe_shaper_set(nq) != 0)  {
+		nss_qdisc_warning("SSDK shaper configuration failed\n");
+		goto fail;
+	}
+
+	/*
+	 * NSS configuration is not needed if Qdisc is not of queue type
+	 * because firmware proxy nodes don't care about scheduler parameters.
+	 */
+	if (!nss_ppe_sub_type_is_queue(npq)) {
+		nq->npq.is_configured = true;
+		return 0;
+	}
+
+	if (nss_ppe_mcast_queue_set(nq) < 0) {
+		nss_qdisc_warning("SSDK multicast queueue configuration failed\n");
+		goto fail;
+	}
+
+	/*
+	 * Program PPE queue parameters
+	 */
+	if (nss_ppe_queue_limit_set(nq) < 0) {
+		nss_qdisc_warning("SSDK queue configuration failed\n");
+		goto fail;
+	}
+
+	memset(&nim, 0, sizeof(struct nss_if_msg));
+	nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = nq->qos_tag;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.ppe_sn_param.type = npq->sub_type;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.ppe_sn_param.limit = npq->q.qlimit;
+
+	if (npq->q.ucast_valid) {
+		nim.msg.shaper_configure.config.msg.shaper_node_config.snc.ppe_sn_param.ucast_base = ucast_qbase;
+		nim.msg.shaper_configure.config.msg.shaper_node_config.snc.ppe_sn_param.ucast_offset = npq->q.ucast_qid - ucast_qbase;
+	}
+
+	if (npq->q.mcast_valid) {
+		nim.msg.shaper_configure.config.msg.shaper_node_config.snc.ppe_sn_param.mcast_base = mcast_qbase;
+		nim.msg.shaper_configure.config.msg.shaper_node_config.snc.ppe_sn_param.mcast_offset = npq->q.mcast_qid - mcast_qbase;
+	}
+
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.ppe_sn_param.port = nss_ppe_port_num_get(nq);
+
+	if (nss_qdisc_configure(nq, &nim, NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_CHANGE_PARAM) < 0) {
+		nss_qdisc_warning("Qdisc configuration failed\n");
+		goto fail;
+	}
+
+	/*
+	 * There is nothing we need to do if the qdisc is not
+	 * set as default qdisc.
+	 * TODO: Currently multicast is associated with set_default configuration.
+	 * Once multicast will have its own confuration parameter, move this code to
+	 * respective qdisc.
+	 */
+	if ((npq->q.mcast_enable) && (nss_qdisc_set_default(nq) < 0)) {
+		nss_qdisc_error("set_default failed\n");
+		goto fail;
+	}
+
+	nq->npq.is_configured = true;
+
+	nss_qdisc_info("Qdisc configured successfully\n");
+	return 0;
+
+fail:
+	if (!nq->npq.is_configured) {
+		return -EINVAL;
+	}
+
+	if (nq->is_class) {
+		return -EINVAL;
+	}
+
+	/*
+	 * Restore to previous configuration if exists.
+	 * In case set_default is toggled and we have allocated/deallocated the
+	 * mcast resources during change configuration, we need to restore them
+	 * to old configuration by again deallocating/allocating them.
+	 */
+	if ((npq->q.mcast_enable != prev_npq->q.mcast_enable)
+		&& (npq->q.mcast_valid != prev_npq->q.mcast_valid)) {
+		prev_npq->q.mcast_valid = npq->q.mcast_valid;
+		prev_npq->q.mcast_qid = npq->q.mcast_qid;
+	}
+
+	memcpy(npq, prev_npq, sizeof(struct nss_ppe_qdisc));
+	nss_ppe_queue_limit_set(nq);
+	nss_ppe_mcast_queue_set(nq);
+
+	nss_ppe_shaper_set(nq);
+	nss_ppe_scheduler_set(nq);
+
+	return -EINVAL;
+}
+
+/*
+ * nss_ppe_fallback_to_nss()
+ *	Calls the initialization of NSS Qdisc when PPE initialization fails.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+int nss_ppe_fallback_to_nss(struct nss_qdisc *nq, struct nlattr *opt)
+#else
+int nss_ppe_fallback_to_nss(struct nss_qdisc *nq, struct nlattr *opt, struct netlink_ext_ack *extack)
+#endif
+{
+	nss_qdisc_destroy(nq);
+
+	memset(&nq->npq, 0, sizeof(struct nss_ppe_qdisc));
+	nq->ppe_init_failed = true;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	if (nq->qdisc->ops->init(nq->qdisc, opt) < 0) {
+#else
+	if (nq->qdisc->ops->init(nq->qdisc, opt, extack) < 0) {
+#endif
+			nss_qdisc_warning("Fallback to NSS Qdisc failed.\n");
+			return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ppe_destroy()
+ *	Destroys NSS PPE Qdisc.
+ */
+void nss_ppe_destroy(struct nss_qdisc *nq)
+{
+	nss_ppe_mcast_queue_reset(nq);
+	nss_ppe_shaper_reset(nq);
+	nss_ppe_scheduler_reset(nq);
+
+	if (nq->is_root) {
+		nss_ppe_default_conf_set(nss_ppe_port_num_get(nq));
+	}
+}
+
+/*
+ * nss_ppe_init()
+ *	Initializes NSS Qdisc and sets the level of this qdisc.
+ */
+int nss_ppe_init(struct Qdisc *sch, struct nss_qdisc *nq, nss_shaper_node_type_t type)
+{
+	bool is_red;
+	bool alloc_scheduler = true;
+	struct net_device *dev = qdisc_dev(sch);
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+
+	/*
+	 * HW qdisc is supported only on physical and loopbaack ports.
+	 */
+	if (port_num >= NSS_PPE_PORT_MAX) {
+		nss_qdisc_info("HW qdisc not supported on port %d\n", port_num);
+		return -1;
+	}
+
+	memset(&nq->npq, 0, sizeof(struct nss_ppe_qdisc));
+
+	switch (type) {
+	case NSS_SHAPER_NODE_TYPE_FIFO:
+		nq->npq.sub_type = NSS_SHAPER_CONFIG_PPE_SN_TYPE_FIFO;
+		break;
+
+	case NSS_SHAPER_NODE_TYPE_WRED:
+		is_red = sch->ops == &nss_red_qdisc_ops;
+		if (!is_red) {
+			nss_qdisc_info("HW WRED qdisc not supported %x\n", sch->handle);
+			return -1;
+		} else {
+			nq->npq.sub_type = NSS_SHAPER_CONFIG_PPE_SN_TYPE_RED;
+		}
+		break;
+
+	case NSS_SHAPER_NODE_TYPE_HTB:
+
+		/*
+		 * Currently we only allow one ppehtb qdisc and
+		 * that should be at the root.
+		 */
+		if (sch->parent != TC_H_ROOT) {
+			nss_qdisc_info("HW HTB qdisc needs to be root %x\n", sch->handle);
+			return -1;
+		}
+
+		nq->npq.sub_type = NSS_SHAPER_CONFIG_PPE_SN_TYPE_HTB;
+		alloc_scheduler = false;
+		break;
+
+	case NSS_SHAPER_NODE_TYPE_HTB_GROUP:
+		nq->npq.sub_type = NSS_SHAPER_CONFIG_PPE_SN_TYPE_HTB_GROUP;
+		break;
+
+	case NSS_SHAPER_NODE_TYPE_TBL:
+		nq->npq.sub_type = NSS_SHAPER_CONFIG_PPE_SN_TYPE_TBL;
+		break;
+
+	case NSS_SHAPER_NODE_TYPE_WRR:
+		nq->npq.sub_type = NSS_SHAPER_CONFIG_PPE_SN_TYPE_WRR;
+		break;
+
+	case NSS_SHAPER_NODE_TYPE_WRR_GROUP:
+		nq->npq.sub_type = NSS_SHAPER_CONFIG_PPE_SN_TYPE_WRR_GROUP;
+		break;
+
+	case NSS_SHAPER_NODE_TYPE_PRIO:
+		nq->npq.sub_type = NSS_SHAPER_CONFIG_PPE_SN_TYPE_PRIO;
+		break;
+
+	default:
+		nss_qdisc_warning("HW Qdisc not supported\n");
+		return -1;
+	}
+
+	nq->npq.q.qlimit = dev->tx_queue_len ? : 1;
+	nq->npq.scheduler.priority = NSS_PPE_PRIORITY_MAX;
+
+	if (nq->is_root) {
+		nq->npq.level = nss_ppe_max_level_get(nq) - 1;
+	} else {
+		if (!nq->parent) {
+			nss_qdisc_warning("Qdisc is not root and has no parent\n");
+			return -1;
+		}
+
+		/*
+		 * First HTB class has a same level as HTB qdisc.
+		 * While all other qdiscs and classes wil be at one level less than the parent level.
+		 * This is because all other scheduler qdisc (such as TBL, WRR, etc) have some logic
+		 * in qdisc that needs resource allocation in PPE. HTB qdisc on the other hand does
+		 * nothing useful and thus we don't allocate any resource".
+		 */
+		nss_qdisc_trace("Qdisc parent = %px, handle=%x\n", nq->parent,  nq->parent->qos_tag);
+		if ((nq->parent->npq.sub_type == NSS_SHAPER_CONFIG_PPE_SN_TYPE_HTB)) {
+			nq->npq.level = nq->parent->npq.level;
+		} else {
+			nq->npq.level = nq->parent->npq.level - 1;
+		}
+
+		if (!nss_ppe_is_depth_valid(nq)) {
+			nss_qdisc_warning("tree is too deep\n");
+			memset(&nq->npq, 0, sizeof(struct nss_ppe_qdisc));
+			return -1;
+		}
+	}
+
+	nq->mode = NSS_QDISC_MODE_PPE;
+	if (alloc_scheduler) {
+		if (nss_ppe_scheduler_set(nq) < 0) {
+			nss_qdisc_warning("%px SSDK scheduler configuration failed\n", sch);
+			memset(&nq->npq, 0, sizeof(struct nss_ppe_qdisc));
+			nq->mode = NSS_QDISC_MODE_NSS;
+			return -1;
+		}
+	}
+
+	if (nq->npq.level == NSS_PPE_SUB_QUEUE_LEVEL) {
+		nq->npq.q = nq->parent->npq.q;
+	}
+
+	nq->type = NSS_SHAPER_NODE_TYPE_PPE_SN;
+
+	nss_qdisc_info("Qdisc initialization successful\n");
+	return 0;
+}
diff --git a/qca-nss-clients/nss_qdisc/nss_ppe.h b/qca-nss-clients/nss_qdisc/nss_ppe.h
new file mode 100644
index 0000000..fc4e088
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_ppe.h
@@ -0,0 +1,288 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <fal_qm.h>
+#include <fal_qos.h>
+#include <fal_shaper.h>
+#include <nss_api_if.h>
+
+/*
+ * Queues in PPE are assigned blocks of memory (not packets)
+ * Each block is 256B in size.
+ */
+#define NSS_PPE_MEM_BLOCK_SIZE 256
+
+/*
+ * Token number is assigned the max value so as to
+ * avoid the packet loss at the start of shaper process.
+ */
+#define NSS_PPE_TOKEN_MAX		0x3fffffff
+
+#define NSS_PPE_DRR_WEIGHT_MAX		1024
+
+/*
+ * Error codes
+ */
+#define NSS_PPE_QDISC_PARENT_NOT_PPE -1
+#define NSS_PPE_QDISC_PARENT_NOT_EXISTING -2
+
+struct nss_qdisc;
+
+/*
+ * Quantum unit.
+ */
+enum nss_ppe_drr_unit {
+	NSS_PPE_DRR_UNIT_BYTE,
+	NSS_PPE_DRR_UNIT_PACKET,
+};
+typedef enum nss_ppe_drr_unit nss_ppe_drr_unit_t;
+
+/*
+ * Frame mode.
+ */
+enum nss_ppe_frame_mode {
+	NSS_PPE_IPG_PREAMBLE_FRAME_CRC,	/* IPG + Preamble + Frame + CRC */
+	NSS_PPE_FRAME_CRC,		/* Frame + CRC */
+	NSS_PPE_L3_EXCLUDE_CRC,		/* after Ethernet type exclude CRC*/
+};
+
+/*
+ * Shaper/Scheduler levels.
+ */
+enum nss_ppe_level {
+	NSS_PPE_SUB_QUEUE_LEVEL,
+	NSS_PPE_QUEUE_LEVEL,
+	NSS_PPE_FLOW_LEVEL,
+	NSS_PPE_PORT_LEVEL,
+	NSS_PPE_MAX_LEVEL,
+};
+typedef enum nss_ppe_level nss_ppe_level_t;
+
+/*
+ * Resource type.
+ */
+enum nss_ppe_res_type {
+	NSS_PPE_UCAST_QUEUE,
+	NSS_PPE_MCAST_QUEUE,
+	NSS_PPE_L0_CDRR,
+	NSS_PPE_L0_EDRR,
+	NSS_PPE_L0_SP,
+	NSS_PPE_L1_CDRR,
+	NSS_PPE_L1_EDRR,
+	NSS_PPE_MAX_RES_TYPE,
+};
+typedef enum nss_ppe_res_type nss_ppe_res_type_t;
+
+/*
+ * Supported colors
+ */
+enum nss_ppe_color_types {
+	NSS_PPE_COLOR_GREEN,
+	NSS_PPE_COLOR_YELLOW,
+	NSS_PPE_COLOR_RED,
+	NSS_PPE_COLOR_MAX,
+};
+
+/*
+ * Resource Structure.
+ */
+struct nss_ppe_res {
+	nss_ppe_res_type_t type;	/* resource type */
+	uint32_t offset;		/* Resource offset */
+	struct nss_ppe_res *next; /* Pointer to next resource */
+};
+
+/*
+ * nss_ppe_port structure
+ */
+struct nss_ppe_port {
+	uint32_t base[NSS_PPE_MAX_RES_TYPE];	/* Base Id */
+	uint32_t max[NSS_PPE_MAX_RES_TYPE];	/* Max resources */
+	struct nss_ppe_res *res_used[NSS_PPE_MAX_RES_TYPE];	/* Used res list */
+	struct nss_ppe_res *res_free[NSS_PPE_MAX_RES_TYPE];	/* Free res list */
+
+	spinlock_t lock;				/* Lock to protect the port structure */
+};
+
+/*
+ * nss_ppe_queue structure
+ */
+struct nss_ppe_queue {
+	uint32_t ucast_qid;			/* Unicast Queue ID */
+	uint32_t mcast_qid;			/* Multicast Queue ID */
+	uint32_t qlimit;			/* Queue limit */
+	uint32_t min_th[NSS_PPE_COLOR_MAX];	/* Min threshold */
+	uint32_t max_th[NSS_PPE_COLOR_MAX];	/* Max threshold */
+	bool color_en;				/* Enable color mode */
+	bool red_en;				/* Enable red algorithm */
+	bool ucast_valid;			/* Queue ID valid */
+	bool mcast_valid;			/* Multicast configuration valid */
+	bool mcast_enable;			/* Multicast configuration enabled? */
+};
+
+/*
+ * nss_ppe_shaper structure
+ */
+struct nss_ppe_shaper {
+	uint32_t rate;		/* Allowed bandwidth */
+	uint32_t burst;		/* Allowed burst */
+	uint32_t crate;		/* Ceil bandwidth */
+	uint32_t cburst;	/* Ceil burst */
+	uint32_t overhead;	/* Overhead in bytes to be added for each packet */
+};
+
+/*
+ * nss_ppe_scheduler structure
+ */
+struct nss_ppe_scheduler {
+	uint32_t drr_weight;	/* DRR weight */
+	nss_ppe_drr_unit_t drr_unit;
+				/* DRR unit*/
+	uint32_t priority;	/* Priority value */
+};
+
+/*
+ * nss_ppe structure
+ */
+struct nss_ppe_qdisc {
+	enum nss_shaper_config_ppe_sn_type sub_type;	/* Type of PPE Qdisc */
+				/* PPE Qdisc type */
+	struct nss_ppe_queue q;	/* PPE queue related parameters */
+	struct nss_ppe_shaper shaper;	/* PPE shaper parameters */
+	struct nss_ppe_scheduler scheduler;	/* PPE scheduler parameters */
+	nss_ppe_level_t level;	/* Level at which qdisc is configured */
+	uint32_t l0spid;	/* Level 0 SP Id configured in SSDK */
+	uint32_t l0c_drrid;	/* Level 0 c_drr Id configured in SSDK */
+	uint32_t l0e_drrid;	/* Level 0 e_drr Id configured in SSDK */
+	uint32_t l1c_drrid;	/* Level 1 c_drr Id configured in SSDK */
+	uint32_t l1e_drrid;	/* Level 1 e_drr Id configured in SSDK */
+	bool l1_valid;		/* Level 1 scheduler resources valid */
+	bool l0_valid;		/* Level 0 scheduler resources valid */
+	bool shaper_present;	/* Shaper parameters present? */
+	bool is_configured;	/* Qdisc already configured or not */
+};
+
+/*
+ * nss_ppe_base_get()
+ *	Returns base of the particular resource for a given port.
+ */
+extern uint32_t nss_ppe_base_get(uint32_t port, nss_ppe_res_type_t type);
+
+/*
+ * nss_ppe_port_res_free()
+ *	Free resources allocated to PPE ports
+ */
+extern int nss_ppe_port_res_free(void);
+
+/*
+ * nss_ppe_res_alloc()
+ *	Allocates free resource for a given port.
+ */
+extern struct nss_ppe_res *nss_ppe_res_alloc(uint32_t port, nss_ppe_res_type_t type);
+
+/*
+ * nss_ppe_res_free()
+ *	Frees the allocated resource and attach it to free list.
+ */
+extern int nss_ppe_res_free(uint32_t port, uint32_t offset, nss_ppe_res_type_t type);
+
+/*
+ * nss_ppe_port_res_alloc()
+ *	Allocates per port resources
+ */
+extern int nss_ppe_port_res_alloc(void);
+
+/*
+ * nss_ppe_mcast_queue_reset()
+ *	Deconfigures and deallocates a multicast queue in SSDK.
+ */
+extern int nss_ppe_mcast_queue_reset(struct nss_qdisc *nq);
+
+/*
+ * nss_ppe_mcast_queue_set()
+ *	Allocates and configures a multicast queue in SSDK.
+ */
+extern int nss_ppe_mcast_queue_set(struct nss_qdisc *nq);
+
+/*
+ * nss_ppe_drr_weight_get()
+ *	Returns the DRR weight corresponding to quantum.
+ */
+extern int nss_ppe_drr_weight_get(uint32_t quantum, nss_ppe_drr_unit_t drr_unit);
+
+/*
+ * nss_ppe_port_num_get()
+ *	Returns the port number.
+ */
+extern int nss_ppe_port_num_get(struct nss_qdisc *nq);
+
+/*
+ * nss_ppe_set_parent()
+ *	Sets the parent of given qdisc.
+ */
+extern int nss_ppe_set_parent(struct Qdisc *sch, struct nss_qdisc *nq, uint32_t parent);
+
+/*
+ * nss_ppe_get_max_prio_bands()
+ *	Returns the number of PRIO bands supported based on qdisc level.
+ */
+extern int nss_ppe_get_max_prio_bands(struct nss_qdisc *nq);
+
+/*
+ * nss_ppe_all_queue_enable_hybrid()
+ *	Enables PPE queues when NSS queuing Qdiscs are attached in the hieracrchy.
+ */
+extern void nss_ppe_all_queue_enable_hybrid(struct nss_qdisc *nq);
+
+/*
+ * nss_ppe_node_detach()
+ *	Configuration function that helps detach a child shaper node from a parent.
+ */
+extern int nss_ppe_node_detach(struct nss_qdisc *nq, struct nss_qdisc *nq_child);
+
+/*
+ * nss_ppe_node_attach()
+ *	Configuration function that helps attach a child shaper node to a parent.
+ */
+extern int nss_ppe_node_attach(struct nss_qdisc *nq, struct nss_qdisc *nq_child);
+
+/*
+ * nss_ppe_node_attach()
+ *	Configures the SSDK schedulers and NSS shapers.
+ */
+extern int nss_ppe_configure(struct nss_qdisc *nq, struct nss_ppe_qdisc *prev_npq);
+
+/*
+ * nss_ppe_fallback_to_nss()
+ *	Calls the initialization of NSS Qdisc when PPE initialization fails.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+extern int nss_ppe_fallback_to_nss(struct nss_qdisc *nq, struct nlattr *opt);
+#else
+extern int nss_ppe_fallback_to_nss(struct nss_qdisc *nq, struct nlattr *opt, struct netlink_ext_ack *extack);
+#endif
+
+/*
+ * nss_ppe_destroy()
+ *	Destroys the qdisc.
+ */
+extern void nss_ppe_destroy(struct nss_qdisc *nq);
+
+/*
+ * nss_ppe_init()
+ *	Initializes NSS Qdisc and sets the level of this qdisc.
+ */
+extern int nss_ppe_init(struct Qdisc *sch, struct nss_qdisc *nq, nss_shaper_node_type_t type);
diff --git a/qca-nss-clients/nss_qdisc/nss_ppe_mc.c b/qca-nss-clients/nss_qdisc/nss_ppe_mc.c
new file mode 100644
index 0000000..b4ff822
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_ppe_mc.c
@@ -0,0 +1,167 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_qdisc.h"
+
+/*
+ * nss_ppe_mcast_queue_reset()
+ *	Deconfigures and deallocates a multicast queue in SSDK.
+ */
+int nss_ppe_mcast_queue_reset(struct nss_qdisc *nq)
+{
+	fal_shaper_config_t cfg;
+	uint32_t offset;
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+	struct nss_ppe_qdisc *npq = &nq->npq;
+
+
+	if (!npq->q.mcast_valid) {
+		return 0;
+	}
+
+	fal_qm_enqueue_ctrl_set(0, npq->q.mcast_qid, false);
+	fal_scheduler_dequeue_ctrl_set(0, npq->q.mcast_qid, false);
+	fal_queue_flush(0, port_num, npq->q.mcast_qid);
+
+	/*
+	 * In case, multicast queue is attached to a classful qdisc at
+	 * its maximum depth, then reset the multicast queue ID in parent qdisc
+	 * and reset queue shaper.
+	 */
+	if (npq->level == NSS_PPE_SUB_QUEUE_LEVEL) {
+		nq->parent->npq.q.mcast_qid = 0;
+		memset(&cfg, 0, sizeof(cfg));
+		nss_qdisc_trace("SSDK multicast queue shaper reset : mcast_qid:%d\n", npq->q.mcast_qid);
+		if (fal_queue_shaper_set(0, npq->q.mcast_qid, &cfg) != 0) {
+			nss_qdisc_error("SSDK multicast queue shaper configuration failed for port:%d, mcast_qid:%d\n",
+				port_num, npq->q.mcast_qid);
+			return -EINVAL;
+		}
+	}
+
+	/*
+	 * Free Level 0 multicast queue resource
+	 */
+	offset = npq->q.mcast_qid - nss_ppe_base_get(port_num, NSS_PPE_MCAST_QUEUE);
+	if (nss_ppe_res_free(port_num, offset, NSS_PPE_MCAST_QUEUE) != 0) {
+		nss_qdisc_error("Used res:%d not found for port:%d, type:%d \n", npq->q.mcast_qid, port_num, NSS_PPE_MCAST_QUEUE);
+		return -EINVAL;
+	}
+
+	npq->q.mcast_qid = 0;
+	npq->q.mcast_valid = false;
+
+	nss_qdisc_info("SSDK multicast queue reset successful for port:%d\n", port_num);
+	return 0;
+}
+
+/*
+ * nss_ppe_mcast_queue_set()
+ *	Allocates and configures a multicast queue in SSDK.
+ */
+int nss_ppe_mcast_queue_set(struct nss_qdisc *nq)
+{
+	fal_qos_scheduler_cfg_t l0cfg;
+	fal_shaper_token_number_t token;
+	fal_shaper_config_t cfg;
+	struct nss_ppe_qdisc *npq = &nq->npq;
+	struct nss_ppe_res *mcast_q = NULL;
+	uint32_t port_num = nss_ppe_port_num_get(nq);
+
+	/*
+	 * If multicast queue configuartion is not enabled,
+	 * it could be possible that queue's multicast configuration
+	 * has changed from enabled to disabled.
+	 * So, we need to reset it.
+	 */
+	 if (!npq->q.mcast_enable) {
+		nss_ppe_mcast_queue_reset(nq);
+		return 0;
+	 }
+
+	/*
+	 * If multicast queue configuartion is enabled,
+	 * and we have a valid mcast queue, then nothing to do.
+	 */
+	if (npq->q.mcast_valid) {
+		return 0;
+	}
+
+	/*
+	 * Get Level 0 multicast queue Resource
+	 */
+	mcast_q = nss_ppe_res_alloc(port_num, NSS_PPE_MCAST_QUEUE);
+	if (!mcast_q) {
+		nss_qdisc_warning("Free res not found for port:%d, type:%d \n", port_num, NSS_PPE_MCAST_QUEUE);
+		return -EINVAL;
+	}
+	npq->q.mcast_qid = nss_ppe_base_get(port_num, NSS_PPE_MCAST_QUEUE) + mcast_q->offset;
+	npq->q.mcast_valid = true;
+
+	nss_qdisc_trace("SSDK level0 configuration get: ucast_qid:%d\n", npq->q.ucast_qid);
+	if (fal_queue_scheduler_get(0, npq->q.ucast_qid, NSS_PPE_QUEUE_LEVEL - 1, &port_num, &l0cfg) != 0) {
+		nss_qdisc_error("SSDK level0 unicast queue scheduler configuration fetch failed\n");
+		goto fail;
+	}
+
+	nss_qdisc_trace("SSDK level0 configuration: Port:%d, mcast_qid:%d, c_drrid:%d, c_pri:%d, c_drr_wt:%d, e_drrid:%d, e_pri:%d, e_drr_wt:%d, l0spid:%d\n",
+			port_num, npq->q.mcast_qid, l0cfg.c_drr_id, l0cfg.c_pri, l0cfg.c_drr_wt, l0cfg.e_drr_id, l0cfg.e_pri, l0cfg.e_drr_wt, l0cfg.sp_id);
+	if (fal_queue_scheduler_set(0, npq->q.mcast_qid, NSS_PPE_QUEUE_LEVEL - 1, port_num, &l0cfg) != 0) {
+		nss_qdisc_error("SSDK level0 multicast queue scheduler configuration failed\n");
+		goto fail;
+	}
+
+	/*
+	 * In case, multicast queue is attached at NSS_PPE_SUB_QUEUE_LEVEL level,
+	 * set queue shaper for multicast queue.
+	 */
+	if (npq->level == NSS_PPE_SUB_QUEUE_LEVEL) {
+		memset(&token, 0, sizeof(token));
+		token.c_token_number = NSS_PPE_TOKEN_MAX;
+		token.e_token_number = NSS_PPE_TOKEN_MAX;
+
+		nss_qdisc_trace("SSDK multicast queue token set : mcast_qid:%d, c_token_number:%x, e_token_number:%x\n",
+			npq->q.mcast_qid, token.c_token_number, token.e_token_number);
+		if (fal_queue_shaper_token_number_set(0, npq->q.mcast_qid, &token) != 0) {
+			nss_qdisc_error("SSDK multicast queue shaper token configuration failed\n");
+			goto fail;
+		}
+
+		if (fal_queue_shaper_get(0, npq->q.ucast_qid, &cfg) != 0) {
+			nss_qdisc_error("SSDK queue shaper configuration fetch failed\n");
+			goto fail;
+		}
+
+		nss_qdisc_trace("SSDK multicast queue shaper configuration: mcast_qid:%d, couple_en:%d, meter_unit:%d, c_shaper_en:%d, cbs:%d, cir:%d, ebs:%d, eir:%d, shaper_frame_mode:%d\n",
+			npq->q.mcast_qid, cfg.couple_en, cfg.meter_unit, cfg.c_shaper_en, cfg.cbs, cfg.cir, cfg.ebs, cfg.eir, cfg.shaper_frame_mode);
+		if (fal_queue_shaper_set(0, npq->q.mcast_qid, &cfg) != 0) {
+			nss_qdisc_error("SSDK multicast queue shaper configuration failed\n");
+			goto fail;
+		}
+	}
+
+	fal_qm_enqueue_ctrl_set(0, npq->q.mcast_qid, true);
+	fal_scheduler_dequeue_ctrl_set(0, npq->q.mcast_qid, true);
+
+	nss_qdisc_info("SSDK multicast queue configuration successful for port:%d\n", port_num);
+	return 0;
+
+fail:
+	nss_ppe_res_free(port_num, mcast_q->offset, NSS_PPE_MCAST_QUEUE);
+	npq->q.mcast_qid = 0;
+	npq->q.mcast_valid = 0;
+	return -EINVAL;
+}
\ No newline at end of file
diff --git a/qca-nss-clients/nss_qdisc/nss_prio.c b/qca-nss-clients/nss_qdisc/nss_prio.c
new file mode 100644
index 0000000..6b44ba9
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_prio.c
@@ -0,0 +1,568 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2017, 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_qdisc.h"
+
+/*
+ * nssprio qdisc instance structure
+ */
+struct nss_prio_sched_data {
+	struct nss_qdisc nq;	/* Common base class for all nss qdiscs */
+	int bands;		/* Number of priority bands to use */
+	struct Qdisc *queues[TCA_NSSPRIO_MAX_BANDS];
+				/* Array of child qdisc holder */
+};
+
+/*
+ * nssprio policy structure
+ */
+static struct nla_policy nss_prio_policy[TCA_NSSPRIO_MAX + 1] = {
+	[TCA_NSSPRIO_PARMS] = { .len = sizeof(struct tc_nssprio_qopt) },
+};
+
+/*
+ * nss_prio_enqueue()
+ *	Enqueues a skb to nssprio qdisc.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+static int nss_prio_enqueue(struct sk_buff *skb, struct Qdisc *sch)
+#else
+static int nss_prio_enqueue(struct sk_buff *skb, struct Qdisc *sch,
+				struct sk_buff **to_free)
+#endif
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	return nss_qdisc_enqueue(skb, sch);
+#else
+	return nss_qdisc_enqueue(skb, sch, to_free);
+#endif
+}
+
+/*
+ * nss_prio_dequeue()
+ *	Dequeues a skb to nssprio qdisc.
+ */
+static struct sk_buff *nss_prio_dequeue(struct Qdisc *sch)
+{
+	return nss_qdisc_dequeue(sch);
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+/*
+ * nss_prio_drop()
+ *	Drops a single skb from linux queue, if not empty.
+ *
+ * Does not drop packets that are queued in the NSS.
+ */
+static unsigned int nss_prio_drop(struct Qdisc *sch)
+{
+	return nss_qdisc_drop(sch);
+}
+#endif
+
+/*
+ * nss_prio_peek()
+ *	Peeks the first packet in queue for this qdisc.
+ */
+static struct sk_buff *nss_prio_peek(struct Qdisc *sch)
+{
+	return nss_qdisc_peek(sch);
+}
+
+/*
+ * nss_prio_reset()
+ *	Reset the nssprio qdisc
+ */
+static void nss_prio_reset(struct Qdisc *sch)
+{
+	return nss_qdisc_reset(sch);
+}
+
+/*
+ * nss_prio_destroy()
+ *	Destroy the nssprio qdisc
+ */
+static void nss_prio_destroy(struct Qdisc *sch)
+{
+	struct nss_prio_sched_data *q = qdisc_priv(sch);
+	struct nss_if_msg nim;
+	int i;
+
+	nss_qdisc_info("Destroying prio");
+
+	/*
+	 * Destroy all attached child nodes before destroying prio
+	 */
+	for (i = 0; i < q->bands; i++) {
+
+		/*
+		 * We always detach the shaper in NSS before destroying it.
+		 * It is very important to check for noop qdisc since those dont
+		 * exist in the NSS.
+		 */
+		if (q->queues[i] != &noop_qdisc) {
+			struct nss_qdisc *nq_child = qdisc_priv(q->queues[i]);
+			nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+			nim.msg.shaper_configure.config.msg.shaper_node_config.snc.prio_detach.priority = i;
+			if (nss_qdisc_node_detach(&q->nq, nq_child, &nim,
+					NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+				nss_qdisc_error("Failed to detach child in band %d from prio %x\n",
+							i, q->nq.qos_tag);
+				return;
+			}
+		}
+
+		/*
+		 * We can now destroy it
+		 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0))
+		qdisc_destroy(q->queues[i]);
+#else
+		qdisc_put(q->queues[i]);
+#endif
+	}
+
+	/*
+	 * Stop the polling of basic stats
+	 */
+	nss_qdisc_stop_basic_stats_polling(&q->nq);
+
+	/*
+	 * Destroy the qdisc in NSS
+	 */
+	nss_qdisc_destroy(&q->nq);
+}
+
+/*
+ * nss_prio_get_max_bands()
+ *	Function call to get max bamds supported
+ */
+static int nss_prio_get_max_bands(struct Qdisc *sch)
+{
+	struct nss_prio_sched_data *q = qdisc_priv(sch);
+	q = qdisc_priv(sch);
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	if (q->nq.mode == NSS_QDISC_MODE_PPE) {
+		return nss_ppe_get_max_prio_bands(&q->nq);
+	}
+#endif
+
+	if (q->nq.mode == NSS_QDISC_MODE_NSS) {
+		return TCA_NSSPRIO_MAX_BANDS;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_prio_change()
+ *	Function call to configure the nssprio parameters
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_prio_change(struct Qdisc *sch, struct nlattr *opt)
+#else
+static int nss_prio_change(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+#endif
+{
+	struct nlattr *tb[TCA_NSSPRIO_MAX + 1];
+	struct nss_prio_sched_data *q;
+	struct tc_nssprio_qopt *qopt;
+
+	q = qdisc_priv(sch);
+
+	/*
+	 * Since nssprio can be created with no arguments, opt might be NULL
+	 * (depending on the kernel version). This is still a valid create
+	 * request.
+	 */
+	if (!opt) {
+
+		/*
+		 * If no parameter is passed, set it to the default value.
+		 */
+		sch_tree_lock(sch);
+		q->bands = TCA_NSSPRIO_MAX_BANDS;
+		sch_tree_unlock(sch);
+		return 0;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_prio_policy, tb, TCA_NSSPRIO_MAX, TCA_NSSPRIO_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_prio_policy, tb, TCA_NSSPRIO_MAX, TCA_NSSPRIO_PARMS, extack);
+#endif
+	if (!qopt) {
+		return -EINVAL;
+	}
+
+	if (qopt->bands > nss_prio_get_max_bands(sch)) {
+		nss_qdisc_warning("nssprio (accel_mode %d) requires max bands to be %d\n",
+				nss_qdisc_accel_mode_get(&q->nq), nss_prio_get_max_bands(sch));
+		return -EINVAL;
+	}
+
+	sch_tree_lock(sch);
+	q->bands = qopt->bands;
+	sch_tree_unlock(sch);
+	nss_qdisc_info("Bands = %u\n", qopt->bands);
+
+	/*
+	 * We do not pass on this information to NSS since
+	 * it not required for operation of prio. This parameter
+	 * is needed only for the proxy operation.
+	 */
+
+	return 0;
+}
+
+/*
+ * nss_prio_init()
+ *	Initializes the nssprio qdisc
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_prio_init(struct Qdisc *sch, struct nlattr *opt)
+{
+	struct netlink_ext_ack *extack = NULL;
+#else
+static int nss_prio_init(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+{
+#endif
+	struct nss_prio_sched_data *q = qdisc_priv(sch);
+	struct nlattr *tb[TCA_NSSPRIO_MAX + 1];
+	struct tc_nssprio_qopt *qopt;
+	int i;
+	unsigned int accel_mode;
+
+	for (i = 0; i < TCA_NSSPRIO_MAX_BANDS; i++) {
+		q->queues[i] = &noop_qdisc;
+	}
+
+	if (!opt) {
+		accel_mode = TCA_NSS_ACCEL_MODE_PPE;
+	} else {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+		qopt = nss_qdisc_qopt_get(opt, nss_prio_policy, tb, TCA_NSSPRIO_MAX, TCA_NSSPRIO_PARMS);
+#else
+		qopt = nss_qdisc_qopt_get(opt, nss_prio_policy, tb, TCA_NSSPRIO_MAX, TCA_NSSPRIO_PARMS, extack);
+#endif
+		if (!qopt) {
+			return -EINVAL;
+		}
+		accel_mode = qopt->accel_mode;
+	}
+
+	if (nss_qdisc_init(sch, &q->nq, NSS_SHAPER_NODE_TYPE_PRIO, 0, accel_mode, extack) < 0)
+	{
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("Nssprio initialized - handle %x parent %x\n",
+			sch->handle, sch->parent);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	if (nss_prio_change(sch, opt) < 0) {
+#else
+	if (nss_prio_change(sch, opt, extack) < 0) {
+#endif
+		nss_qdisc_destroy(&q->nq);
+		return -EINVAL;
+	}
+
+	/*
+	 * Start the stats polling timer
+	 */
+	nss_qdisc_start_basic_stats_polling(&q->nq);
+	return 0;
+}
+
+/*
+ * nss_prio_dump()
+ *	Dump the parameters of nssprio
+ */
+static int nss_prio_dump(struct Qdisc *sch, struct sk_buff *skb)
+{
+	struct nss_prio_sched_data *q = qdisc_priv(sch);
+	struct nlattr *opts = NULL;
+	struct tc_nssprio_qopt qopt;
+
+	nss_qdisc_info("Nssprio dumping");
+	qopt.bands = q->bands;
+	qopt.accel_mode = nss_qdisc_accel_mode_get(&q->nq);
+
+	opts = nss_qdisc_nla_nest_start(skb, TCA_OPTIONS);
+	if (opts == NULL || nla_put(skb, TCA_NSSPRIO_PARMS, sizeof(qopt), &qopt)) {
+		goto nla_put_failure;
+	}
+
+	return nla_nest_end(skb, opts);
+
+nla_put_failure:
+	nla_nest_cancel(skb, opts);
+	return -EMSGSIZE;
+}
+
+/*
+ * nss_prio_graft()
+ *	Replaces existing child qdisc with the new qdisc that is passed.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_prio_graft(struct Qdisc *sch, unsigned long arg,
+				struct Qdisc *new, struct Qdisc **old)
+#else
+static int nss_prio_graft(struct Qdisc *sch, unsigned long arg,
+				struct Qdisc *new, struct Qdisc **old,
+				struct netlink_ext_ack *extack)
+#endif
+{
+	struct nss_prio_sched_data *q = qdisc_priv(sch);
+	struct nss_qdisc *nq_new = qdisc_priv(new);
+	uint32_t band = (uint32_t)(arg - 1);
+	struct nss_if_msg nim_attach;
+	struct nss_if_msg nim_detach;
+
+	nss_qdisc_info("Grafting band %u, available bands %u\n", band, q->bands);
+
+	if (new == NULL)
+		new = &noop_qdisc;
+
+	if (band > q->bands)
+		return -EINVAL;
+
+	sch_tree_lock(sch);
+	*old = q->queues[band];
+	sch_tree_unlock(sch);
+
+	nss_qdisc_info("Grafting old: %px with new: %px\n", *old, new);
+	if (*old != &noop_qdisc) {
+		struct nss_qdisc *nq_old = qdisc_priv(*old);
+		nss_qdisc_info("Detaching old: %px\n", *old);
+		nim_detach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+
+		if (q->nq.mode == NSS_QDISC_MODE_NSS) {
+			nim_detach.msg.shaper_configure.config.msg.shaper_node_config.snc.prio_detach.priority = band;
+		}
+
+		if (nss_qdisc_node_detach(&q->nq, nq_old, &nim_detach,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+			return -EINVAL;
+		}
+	}
+
+	if (new != &noop_qdisc) {
+		nss_qdisc_info("Attaching new child with qos tag: %x, priority: %u to "
+				"qos_tag: %x\n", nq_new->qos_tag, band, q->nq.qos_tag);
+		nim_attach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+		nim_attach.msg.shaper_configure.config.msg.shaper_node_config.snc.prio_attach.child_qos_tag = nq_new->qos_tag;
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+		if (q->nq.mode == NSS_QDISC_MODE_PPE) {
+			nq_new->npq.scheduler.priority = band;
+		}
+#endif
+
+		if (q->nq.mode == NSS_QDISC_MODE_NSS) {
+			nim_attach.msg.shaper_configure.config.msg.shaper_node_config.snc.prio_attach.priority = band;
+		}
+
+		if (nss_qdisc_node_attach(&q->nq, nq_new, &nim_attach,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_ATTACH) < 0) {
+			return -EINVAL;
+		}
+	}
+
+	/*
+	 * Replaced in NSS, now replace in Linux.
+	 */
+	nss_qdisc_replace(sch, new, &q->queues[band]);
+
+	nss_qdisc_info("Nssprio grafted");
+
+	return 0;
+}
+
+/*
+ * nss_prio_leaf_class()
+ *	Returns pointer to qdisc if leaf class.
+ */
+static struct Qdisc *nss_prio_leaf(struct Qdisc *sch, unsigned long arg)
+{
+	struct nss_prio_sched_data *q = qdisc_priv(sch);
+	uint32_t band = (uint32_t)(arg - 1);
+
+	nss_qdisc_info("Nssprio returns leaf\n");
+
+	if (band > q->bands)
+		return NULL;
+
+	return q->queues[band];
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0))
+/*
+ * nss_prio_get()
+ *	Returns the band if provided the classid.
+ */
+static unsigned long nss_prio_get(struct Qdisc *sch, u32 classid)
+{
+	struct nss_prio_sched_data *q = qdisc_priv(sch);
+	unsigned long band = TC_H_MIN(classid);
+
+	nss_qdisc_info("Inside get. Handle - %x Classid - %x Band %lu Available band %u\n", sch->handle, classid, band, q->bands);
+
+	if (band > q->bands)
+		return 0;
+
+	return band;
+}
+
+/*
+ * nss_prio_put()
+ *	Unused API.
+ */
+static void nss_prio_put(struct Qdisc *sch, unsigned long arg)
+{
+	nss_qdisc_info("Inside prio put\n");
+}
+#else
+/*
+ * nss_prio_search()
+ *	Returns the band if provided the classid.
+ */
+static unsigned long nss_prio_search(struct Qdisc *sch, u32 classid)
+{
+	struct nss_prio_sched_data *q = qdisc_priv(sch);
+	unsigned long band = TC_H_MIN(classid);
+
+	nss_qdisc_info("Inside get. Handle - %x Classid - %x Band %lu Available band %u\n", sch->handle, classid, band, q->bands);
+
+	if (band > q->bands)
+		return 0;
+
+	return band;
+}
+#endif
+
+/*
+ * nss_prio_walk()
+ *	Walks the priority band.
+ */
+static void nss_prio_walk(struct Qdisc *sch, struct qdisc_walker *arg)
+{
+	struct nss_prio_sched_data *q = qdisc_priv(sch);
+	int i;
+
+	if (arg->stop)
+		return;
+
+	for (i = 0; i < q->bands; i++) {
+		if (arg->count < arg->skip) {
+			arg->count++;
+			continue;
+		}
+		if (arg->fn(sch, i + 1, arg) < 0) {
+			arg->stop = 1;
+			break;
+		}
+		arg->count++;
+	}
+	nss_qdisc_info("Nssprio walk called\n");
+}
+
+/*
+ * nss_prio_dump_class()
+ * 	Dumps all configurable parameters pertaining to this class.
+ */
+static int nss_prio_dump_class(struct Qdisc *sch, unsigned long cl,
+			     struct sk_buff *skb, struct tcmsg *tcm)
+{
+	struct nss_prio_sched_data *q = qdisc_priv(sch);
+
+	tcm->tcm_handle |= TC_H_MIN(cl);
+	tcm->tcm_info = q->queues[cl - 1]->handle;
+
+	nss_qdisc_info("Nssprio dumping class\n");
+	return 0;
+}
+
+/*
+ * nss_prio_dump_class_stats()
+ *	Dumps class statistics.
+ */
+static int nss_prio_dump_class_stats(struct Qdisc *sch, unsigned long cl,
+			     	    struct gnet_dump *d)
+{
+	struct nss_prio_sched_data *q = qdisc_priv(sch);
+	struct Qdisc *cl_q;
+
+	cl_q = q->queues[cl - 1];
+	cl_q->qstats.qlen = cl_q->q.qlen;
+
+	if (nss_qdisc_gnet_stats_copy_basic(sch, d, &cl_q->bstats) < 0 ||
+			nss_qdisc_gnet_stats_copy_queue(d, &cl_q->qstats) < 0)
+		return -1;
+
+	nss_qdisc_info("Nssprio dumping class stats\n");
+	return 0;
+}
+
+/*
+ * Registration structure for nssprio class
+ */
+const struct Qdisc_class_ops nss_prio_class_ops = {
+	.graft		=	nss_prio_graft,
+	.leaf		=	nss_prio_leaf,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0))
+	.get		=	nss_prio_get,
+	.put		=	nss_prio_put,
+#else
+	.find       =   nss_prio_search,
+#endif
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	.tcf_chain	=	nss_qdisc_tcf_chain,
+#else
+	.tcf_block	=	nss_qdisc_tcf_block,
+#endif
+	.bind_tcf	=	nss_qdisc_tcf_bind,
+	.unbind_tcf	=	nss_qdisc_tcf_unbind,
+	.walk		=	nss_prio_walk,
+	.dump		=	nss_prio_dump_class,
+	.dump_stats	=	nss_prio_dump_class_stats,
+};
+
+/*
+ * Registration structure for nssprio qdisc
+ */
+struct Qdisc_ops nss_prio_qdisc_ops __read_mostly = {
+	.next		=	NULL,
+	.id		=	"nssprio",
+	.priv_size	=	sizeof(struct nss_prio_sched_data),
+	.cl_ops		=	&nss_prio_class_ops,
+	.enqueue	=	nss_prio_enqueue,
+	.dequeue	=	nss_prio_dequeue,
+	.peek		=	nss_prio_peek,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	.drop		=	nss_prio_drop,
+#endif
+	.init		=	nss_prio_init,
+	.reset		=	nss_prio_reset,
+	.destroy	=	nss_prio_destroy,
+	.change		=	nss_prio_change,
+	.dump		=	nss_prio_dump,
+	.owner		=	THIS_MODULE,
+};
diff --git a/qca-nss-clients/nss_qdisc/nss_prio.h b/qca-nss-clients/nss_qdisc/nss_prio.h
new file mode 100644
index 0000000..2833a81
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_prio.h
@@ -0,0 +1,17 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern struct Qdisc_ops nss_prio_qdisc_ops;
diff --git a/qca-nss-clients/nss_qdisc/nss_qdisc.c b/qca-nss-clients/nss_qdisc/nss_qdisc.c
new file mode 100644
index 0000000..25fab67
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_qdisc.c
@@ -0,0 +1,3104 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <nss_api_if.h>
+#include "nss_qdisc.h"
+#include "nss_fifo.h"
+#include "nss_codel.h"
+#include "nss_tbl.h"
+#include "nss_prio.h"
+#include "nss_bf.h"
+#include "nss_wrr.h"
+#include "nss_wfq.h"
+#include "nss_htb.h"
+#include "nss_blackhole.h"
+#include "nss_wred.h"
+
+void *nss_qdisc_ctx;			/* Shaping context for nss_qdisc */
+
+#define NSS_QDISC_COMMAND_TIMEOUT (10*HZ) /* We set 10sec to be the command */
+					   /* timeout value for messages */
+
+/*
+ * Defines related to root hash maintenance
+ */
+#define NSS_QDISC_ROOT_HASH_SIZE 4
+#define NSS_QDISC_ROOT_HASH_MASK (NSS_QDISC_ROOT_HASH_SIZE - 1)
+
+/*
+ * nss_qdisc_interface_is_virtual()
+ *	Return true if it is redirect or bridge interface.
+ */
+bool nss_qdisc_interface_is_virtual(struct nss_ctx_instance *nss_ctx, int32_t if_num)
+{
+	/*
+	 * If there is no bridge client, then bridge gets represented
+	 * as a redirect interface. So this check is sufficient.
+	 */
+	bool is_virtual = nss_cmn_interface_is_redirect(nss_ctx, if_num) || nss_igs_verify_if_num(if_num);
+
+#if defined(NSS_QDISC_BRIDGE_SUPPORT)
+	is_virtual = is_virtual || nss_bridge_verify_if_num(if_num);
+#endif
+	return is_virtual;
+}
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+/*
+ * nss_qdisc_ppe_init()
+ *	Initializes a shaper in PPE.
+ */
+static int nss_qdisc_ppe_init(struct Qdisc *sch, struct nss_qdisc *nq, nss_shaper_node_type_t type, uint32_t parent)
+{
+	int status = 0;
+
+	/*
+	 * Fallback to NSS Qdisc if PPE Qdisc configuration failed.
+	 */
+	if (nq->ppe_init_failed) {
+		nss_qdisc_info("Qdisc %px (type %d) HW Qdisc initialization already tried, creating NSS Qdisc\n",
+			nq->qdisc, nq->type);
+		return 0;
+	}
+
+	/*
+	 * Bridge and IFB needs PPE looback port shapers.
+	 */
+	if (nq->is_bridge || nss_igs_verify_if_num(nq->nss_interface_number)) {
+		nss_qdisc_info("Qdisc %px (type %d) init qdisc: %px, needs PPE loopback port\n",
+			nq->qdisc, nq->type, nq->qdisc);
+		nq->needs_ppe_loopback = true;
+	} else {
+		nss_qdisc_info("Qdisc %px (type %d) init qdisc: %px, does not need PPE loopback port\n",
+			nq->qdisc, nq->type, nq->qdisc);
+		nq->needs_ppe_loopback = false;
+	}
+
+	/*
+	 * Set the parent of PPE qdisc.
+	 */
+	status = nss_ppe_set_parent(sch, nq, parent);
+	if (status == NSS_PPE_QDISC_PARENT_NOT_EXISTING) {
+		nss_qdisc_info("HW qdisc/class %x cannot be attached to non-existing parent %x\n", nq->qos_tag, parent);
+		return -1;
+	} else if (status == NSS_PPE_QDISC_PARENT_NOT_PPE) {
+		nss_qdisc_info("HW qdisc/class %x cannot be attached to NSS qdisc/class %x\n", nq->qos_tag, parent);
+		return 0;
+	}
+
+	if (nss_ppe_init(sch, nq, type) < 0) {
+			/*
+			 * Class creation failures in PPE cannot use fallback to NSS-FW
+			 * because classes under a qdisc usually share resources and that
+			 * cannot happen across two data planes.
+			 * Therefore fallback only applies to qdiscs.
+			 */
+			if (nq->is_class) {
+			nss_qdisc_error("Qdisc %px (type %d) initializing HW class failed", nq->qdisc, nq->type);
+			return -1;
+		}
+		nss_qdisc_info("Qdisc %px (type %d) initializing HW Qdisc failed, initializing NSS Qdisc \n",
+			nq->qdisc, nq->type);
+	} else {
+		nss_qdisc_info("Qdisc %px (type %d) successfully created in PPE\n", nq->qdisc, nq->type);
+	}
+
+	return 0;
+}
+#endif
+
+/*
+ * nss_qdisc_msg_init()
+ *      Initialize the qdisc specific message
+ */
+static void nss_qdisc_msg_init(struct nss_if_msg *nim, uint16_t if_num, uint32_t msg_type, uint32_t len,
+				nss_if_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&nim->cm, if_num, msg_type, len, (void*)cb, app_data);
+}
+
+/*
+ * nss_qdisc_get_interface_msg()
+ *	Returns the correct message that needs to be sent down to the NSS interface.
+ */
+static inline int nss_qdisc_get_interface_msg(bool is_bridge, uint32_t msg_type)
+{
+	/*
+	 * We re-assign the message based on whether this is for the I shaper
+	 * or the B shaper. The is_bridge flag tells if we are on a bridge interface.
+	 */
+	if (is_bridge) {
+		switch(msg_type) {
+		case NSS_QDISC_IF_SHAPER_ASSIGN:
+			return NSS_IF_BSHAPER_ASSIGN;
+		case NSS_QDISC_IF_SHAPER_UNASSIGN:
+			return NSS_IF_BSHAPER_UNASSIGN;
+		case NSS_QDISC_IF_SHAPER_CONFIG:
+			return NSS_IF_BSHAPER_CONFIG;
+		default:
+			nss_qdisc_info("Unknown message type for a bridge - type %d", msg_type);
+			return -1;
+		}
+	} else {
+		switch(msg_type) {
+		case NSS_QDISC_IF_SHAPER_ASSIGN:
+			return NSS_IF_ISHAPER_ASSIGN;
+		case NSS_QDISC_IF_SHAPER_UNASSIGN:
+			return NSS_IF_ISHAPER_UNASSIGN;
+		case NSS_QDISC_IF_SHAPER_CONFIG:
+			return NSS_IF_ISHAPER_CONFIG;
+		default:
+			nss_qdisc_info("Unknown message type for an interface - type %d", msg_type);
+			return -1;
+		}
+	}
+}
+
+/*
+ * nss_qdisc_attach_bshaper_callback()
+ *	Call back funtion for bridge shaper attach to an interface.
+ */
+static void nss_qdisc_attach_bshaper_callback(void *app_data, struct nss_if_msg *nim)
+{
+	struct Qdisc *sch = (struct Qdisc *)app_data;
+	struct nss_qdisc *nq = qdisc_priv(sch);
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_qdisc_warning("B-shaper attach FAILED - response: %d\n",
+				nim->cm.error);
+		atomic_set(&nq->state, NSS_QDISC_STATE_FAILED_RESPONSE);
+		wake_up(&nq->wait_queue);
+		return;
+	}
+
+	nss_qdisc_info("B-shaper attach SUCCESS\n");
+	atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+	wake_up(&nq->wait_queue);
+}
+
+/*
+ * nss_qdisc_attach_bridge()
+ *	Attaches a given bridge shaper to a given interface (Different from shaper_assign)
+ */
+static int nss_qdisc_attach_bshaper(struct Qdisc *sch, uint32_t if_num)
+{
+	struct nss_if_msg nim;
+	struct nss_qdisc *nq = (struct nss_qdisc *)qdisc_priv(sch);
+	int32_t state, rc;
+
+	nss_qdisc_info("Attaching B-shaper %u to interface %u\n",
+			nq->shaper_id, if_num);
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_READY) {
+		nss_qdisc_warning("qdisc %px (type %d) is not ready: State - %d\n",
+				sch, nq->type, state);
+		return -1;
+	}
+
+	/*
+	 * Set shaper node state to IDLE
+	 */
+	atomic_set(&nq->state, NSS_QDISC_STATE_IDLE);
+
+	/*
+	 * Populate the message and send it down
+	 */
+	nss_qdisc_msg_init(&nim, if_num, NSS_IF_BSHAPER_ASSIGN,
+				sizeof(struct nss_if_shaper_assign),
+				nss_qdisc_attach_bshaper_callback,
+				sch);
+	/*
+	 * Assign the ID of the Bshaper that needs to be assigned to the interface recognized
+	 * by if_num.
+	 */
+	nim.msg.shaper_assign.shaper_id = nq->shaper_id;
+	rc = nss_if_tx_msg(nq->nss_shaping_ctx, &nim);
+
+	if (rc != NSS_TX_SUCCESS) {
+		nss_qdisc_warning("Failed to send bshaper (id: %u) attach for "
+				"interface(if_num: %u)\n", nq->shaper_id, if_num);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	/*
+	 * Wait until cleanup operation is complete at which point the state
+	 * shall become non-idle.
+	 */
+	if (!wait_event_timeout(nq->wait_queue, atomic_read(&nq->state) != NSS_QDISC_STATE_IDLE,
+				NSS_QDISC_COMMAND_TIMEOUT)) {
+		nss_qdisc_error("bshaper attach command for %x on interface %u timedout!\n",
+					nq->qos_tag, if_num);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_READY) {
+		nss_qdisc_error("Failed to attach B-shaper %u to interface %u - state: %d\n",
+				nq->shaper_id, if_num, state);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	nss_qdisc_info("Attach of B-shaper %u to interface %u is complete\n",
+			nq->shaper_id, if_num);
+	return 0;
+}
+
+/*
+ * nss_qdisc_detach_bshaper_callback()
+ *	Call back function for bridge shaper detach
+ */
+static void nss_qdisc_detach_bshaper_callback(void *app_data, struct nss_if_msg *nim)
+{
+	struct Qdisc *sch = (struct Qdisc *)app_data;
+	struct nss_qdisc *nq = qdisc_priv(sch);
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_qdisc_error("B-shaper detach FAILED - response: %d\n",
+				nim->cm.error);
+		atomic_set(&nq->state, NSS_QDISC_STATE_FAILED_RESPONSE);
+		wake_up(&nq->wait_queue);
+		return;
+	}
+
+	nss_qdisc_info("B-shaper detach SUCCESS\n");
+	atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+	wake_up(&nq->wait_queue);
+}
+
+/*
+ * nss_qdisc_detach_bridge()
+ *	Detaches a given bridge shaper from a given interface (different from shaper unassign)
+ */
+static int nss_qdisc_detach_bshaper(struct Qdisc *sch, uint32_t if_num)
+{
+	struct nss_if_msg nim;
+	struct nss_qdisc *nq = (struct nss_qdisc *)qdisc_priv(sch);
+	int32_t state, rc;
+
+	nss_qdisc_info("Detaching B-shaper %u from interface %u\n",
+			nq->shaper_id, if_num);
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_READY) {
+		nss_qdisc_warning("qdisc %px (type %d) is not ready: %d\n",
+				sch, nq->type, state);
+		return -1;
+	}
+
+	/*
+	 * Set shaper node state to IDLE
+	 */
+	atomic_set(&nq->state, NSS_QDISC_STATE_IDLE);
+
+	/*
+	 * Create and send shaper unassign message to the NSS interface
+	 */
+	nss_qdisc_msg_init(&nim, if_num, NSS_IF_BSHAPER_UNASSIGN,
+				sizeof(struct nss_if_shaper_unassign),
+				nss_qdisc_detach_bshaper_callback,
+				sch);
+	nim.msg.shaper_unassign.shaper_id = nq->shaper_id;
+	rc = nss_if_tx_msg(nq->nss_shaping_ctx, &nim);
+
+	if (rc != NSS_TX_SUCCESS) {
+		nss_qdisc_warning("Failed to send B-shaper (id: %u) detach "
+			"for interface(if_num: %u)\n", nq->shaper_id, if_num);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	/*
+	 * Wait until cleanup operation is complete at which point the state
+	 * shall become non-idle.
+	 */
+	if (!wait_event_timeout(nq->wait_queue, atomic_read(&nq->state) != NSS_QDISC_STATE_IDLE,
+				NSS_QDISC_COMMAND_TIMEOUT)) {
+		nss_qdisc_error("bshaper detach command for %x on interface %u timedout!\n",
+					nq->qos_tag, if_num);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_READY) {
+		nss_qdisc_error("Failed to detach B-shaper %u from interface %u - state %d\n",
+				nq->shaper_id, if_num, state);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	nss_qdisc_info("Detach of B-shaper %u to interface %u is complete.",
+			nq->shaper_id, if_num);
+
+	return 0;
+}
+
+/*
+ * nss_qdisc_refresh_bshaper_assignment()
+ *	Performs assign on unassign of bshaper for interfaces on the bridge.
+ */
+static int nss_qdisc_refresh_bshaper_assignment(struct Qdisc *br_qdisc,
+					enum nss_qdisc_bshaper_tasks task)
+{
+	struct net_device *dev;
+	struct net_device *br_dev = qdisc_dev(br_qdisc);
+	struct nss_qdisc *nq;
+	struct nss_qdisc_bridge_update br_update;
+	int i;
+
+	if ((br_qdisc->parent != TC_H_ROOT) && (br_qdisc->parent != TC_H_UNSPEC)) {
+		nss_qdisc_error("Qdisc not root qdisc for the bridge interface: "
+				"Handle - %x", br_qdisc->parent);
+		return -1;
+	}
+
+	nq = qdisc_priv(br_qdisc);
+
+	/*
+	 * Initialize the bridge update srtucture.
+	 */
+	br_update.port_list_count = 0;
+	br_update.unassign_count = 0;
+
+	read_lock(&dev_base_lock);
+	dev = first_net_device(&init_net);
+
+	while(dev) {
+		struct net_bridge_port *br_port;
+		int nss_if_num;
+
+		nss_qdisc_info("Scanning device %s", dev->name);
+
+		rcu_read_lock();
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
+		br_port = br_port_get_rcu(dev);
+#else
+		br_port = rcu_dereference(dev->br_port);
+#endif
+
+		if (!br_port || !br_port->br) {
+			rcu_read_unlock();
+			goto nextdev;
+		}
+
+		/*
+		 * Dont care if this device is not on the
+		 * bridge that is of concern.
+		 */
+		if (br_port->br->dev != br_dev) {
+			rcu_read_unlock();
+			goto nextdev;
+		}
+
+		rcu_read_unlock();
+
+		/*
+		 * If the interface is known to NSS then we will have to shape it.
+		 * Irrespective of whether it has an interface qdisc or not.
+		 */
+		nss_if_num = nss_cmn_get_interface_number(nq->nss_shaping_ctx, dev);
+		if (nss_if_num < 0) {
+			goto nextdev;
+		}
+
+		nss_qdisc_info("Will be linking/unlinking %s to/from bridge %s\n",
+						dev->name, br_dev->name);
+		br_update.port_list[br_update.port_list_count++] = nss_if_num;
+nextdev:
+		dev = next_net_device(dev);
+	}
+	read_unlock(&dev_base_lock);
+
+	nss_qdisc_info("List count %d\n", br_update.port_list_count);
+
+	if (task == NSS_QDISC_SCAN_AND_ASSIGN_BSHAPER) {
+		/*
+		 * Loop through the ports and assign them with B-shapers.
+		 */
+		for (i = 0; i < br_update.port_list_count; i++) {
+			if (nss_qdisc_attach_bshaper(br_qdisc, br_update.port_list[i]) >= 0) {
+				nss_qdisc_info("Interface %u added to bridge %s\n",
+					br_update.port_list[i], br_dev->name);
+				continue;
+			}
+			nss_qdisc_error("Unable to attach bshaper with shaper-id: %u, "
+				"to interface if_num: %d\n", nq->shaper_id,
+				br_update.port_list[i]);
+			br_update.unassign_count = i;
+			break;
+		}
+		nss_qdisc_info("Unassign count %d\n", br_update.unassign_count);
+		if (br_update.unassign_count == 0) {
+			return 0;
+		}
+
+		/*
+		 * In case of a failure, unassign the B-shapers that were assigned above
+		 */
+		for (i = 0; i < br_update.unassign_count; i++) {
+			if (nss_qdisc_detach_bshaper(br_qdisc, br_update.port_list[i]) >= 0) {
+				continue;
+			}
+			nss_qdisc_error("Unable to detach bshaper with shaper-id: %u, "
+				"from interface if_num: %d\n", nq->shaper_id,
+				br_update.port_list[i]);
+		}
+
+		nss_qdisc_info("Failed to link interfaces to bridge\n");
+		return -1;
+	} else if (task == NSS_QDISC_SCAN_AND_UNASSIGN_BSHAPER) {
+		/*
+		 * Loop through the ports and assign them with B-shapers.
+		 */
+		for (i = 0; i < br_update.port_list_count; i++) {
+			if (nss_qdisc_detach_bshaper(br_qdisc, br_update.port_list[i]) >= 0) {
+				nss_qdisc_info("Interface %u removed from bridge %s\n",
+					br_update.port_list[i], br_dev->name);
+				continue;
+			}
+			nss_qdisc_error("Unable to detach bshaper with shaper-id: %u, "
+				"from interface if_num: %d\n", nq->shaper_id,
+				br_update.port_list[i]);
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * nss_qdisc_root_cleanup_final()
+ *	Performs final cleanup of a root shaper node after all other
+ *	shaper node cleanup is complete.
+ */
+static void nss_qdisc_root_cleanup_final(struct nss_qdisc *nq)
+{
+	nss_qdisc_info("Root qdisc %px (type %d) final cleanup\n",
+				nq->qdisc, nq->type);
+
+	/*
+	 * If we are a bridge then we have to unregister for bridge bouncing
+	 * AND destroy the virtual interface that provides bridge shaping.
+	 */
+	if (nq->is_bridge) {
+		/*
+		 * Unregister for bouncing to the NSS for bridge shaping
+		 */
+		nss_qdisc_info("Unregister for bridge bouncing: %px\n",
+				nq->bounce_context);
+		nss_shaper_unregister_shaper_bounce_bridge(nq->nss_interface_number);
+
+		/*
+		 * Unregister the virtual interface we use to act as shaper
+		 * for bridge shaping.
+		 */
+		nss_qdisc_info("Release root bridge virtual interface: %px\n",
+				nq->virt_if_ctx);
+	}
+
+	/*
+	 * If we are a virual interface other than a bridge then we simply
+	 * unregister for interface bouncing and not care about deleting the
+	 * interface.
+	 */
+	if (nq->is_virtual && !nq->is_bridge) {
+		/*
+		 * Unregister for interface bouncing of packets
+		 */
+		nss_qdisc_info("Unregister for interface bouncing: %px\n",
+				nq->bounce_context);
+		nss_shaper_unregister_shaper_bounce_interface(nq->nss_interface_number);
+	}
+
+	/*
+	 * Finally unregister for shaping
+	 */
+	nss_qdisc_info("Unregister for shaping\n");
+	nss_shaper_unregister_shaping(nq->nss_shaping_ctx);
+
+	/*
+	 * Now set our final state and wake up the caller
+	 */
+	atomic_set(&nq->state, nq->pending_final_state);
+	wake_up(&nq->wait_queue);
+}
+
+/*
+ * nss_qdisc_root_cleanup_shaper_unassign_callback()
+ *	Invoked on the response to a shaper unassign config command issued
+ */
+static void nss_qdisc_root_cleanup_shaper_unassign_callback(void *app_data,
+							struct nss_if_msg *nim)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)app_data;
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_qdisc_error("Root qdisc %px (type %d) shaper unsassign FAILED\n", nq->qdisc, nq->type);
+		atomic_set(&nq->state, NSS_QDISC_STATE_UNASSIGN_SHAPER_FAIL);
+		wake_up(&nq->wait_queue);
+		return;
+	}
+
+	nss_qdisc_root_cleanup_final(nq);
+}
+
+/*
+ * nss_qdisc_root_cleanup_shaper_unassign()
+ *	Issue command to unassign the shaper
+ */
+static void nss_qdisc_root_cleanup_shaper_unassign(struct nss_qdisc *nq)
+{
+	struct nss_if_msg nim;
+	nss_tx_status_t rc;
+	int msg_type;
+
+	nss_qdisc_info("Root qdisc %px (type %d): shaper unassign: %d\n",
+			nq->qdisc, nq->type, nq->shaper_id);
+
+	msg_type = nss_qdisc_get_interface_msg(nq->is_bridge, NSS_QDISC_IF_SHAPER_UNASSIGN);
+	nss_qdisc_msg_init(&nim, nq->nss_interface_number, msg_type,
+			sizeof(struct nss_if_shaper_unassign),
+			nss_qdisc_root_cleanup_shaper_unassign_callback,
+			nq);
+	nim.msg.shaper_unassign.shaper_id = nq->shaper_id;
+	rc = nss_if_tx_msg(nq->nss_shaping_ctx, &nim);
+
+	if (rc == NSS_TX_SUCCESS) {
+		/*
+		 * Tx successful, simply return.
+		 */
+		return;
+	}
+
+	nss_qdisc_error("Root qdisc %px (type %d): unassign command send failed: "
+		"%d, shaper id: %d\n", nq->qdisc, nq->type, rc, nq->shaper_id);
+
+	atomic_set(&nq->state, NSS_QDISC_STATE_UNASSIGN_SHAPER_SEND_FAIL);
+	wake_up(&nq->wait_queue);
+}
+
+/*
+ * nss_qdisc_root_cleanup_free_node_callback()
+ *	Invoked on the response to freeing a shaper node
+ */
+static void nss_qdisc_root_cleanup_free_node_callback(void *app_data,
+						struct nss_if_msg *nim)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)app_data;
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_qdisc_error("Root qdisc %px (type %d) free FAILED response "
+					"type: %d\n", nq->qdisc, nq->type,
+					nim->msg.shaper_configure.config.response_type);
+		atomic_set(&nq->state, NSS_QDISC_STATE_NODE_FREE_FAIL);
+		wake_up(&nq->wait_queue);
+		return;
+	}
+
+	nss_qdisc_info("Root qdisc %px (type %d) free SUCCESS - response "
+			"type: %d\n", nq->qdisc, nq->type,
+			nim->msg.shaper_configure.config.response_type);
+
+	nss_qdisc_root_cleanup_shaper_unassign(nq);
+}
+
+/*
+ * nss_qdisc_root_cleanup_free_node()
+ *	Free the shaper node, issue command to do so.
+ */
+static void nss_qdisc_root_cleanup_free_node(struct nss_qdisc *nq)
+{
+	struct nss_if_msg nim;
+	nss_tx_status_t rc;
+	int msg_type;
+
+	nss_qdisc_info("Root qdisc %px (type %d): freeing shaper node\n",
+			nq->qdisc, nq->type);
+
+	/*
+	 * Construct and send the shaper configure message down to the NSS interface
+	 */
+	msg_type = nss_qdisc_get_interface_msg(nq->is_bridge, NSS_QDISC_IF_SHAPER_CONFIG);
+	nss_qdisc_msg_init(&nim, nq->nss_interface_number, msg_type,
+				sizeof(struct nss_if_shaper_configure),
+				nss_qdisc_root_cleanup_free_node_callback,
+				nq);
+	nim.msg.shaper_configure.config.request_type = NSS_SHAPER_CONFIG_TYPE_FREE_SHAPER_NODE;
+	nim.msg.shaper_configure.config.msg.free_shaper_node.qos_tag = nq->qos_tag;
+	rc = nss_if_tx_msg(nq->nss_shaping_ctx, &nim);
+
+	if (rc == NSS_TX_SUCCESS) {
+		/*
+		 * Tx successful, simply return.
+		 */
+		return;
+	}
+
+	nss_qdisc_error("Qdisc %px (type %d): free command send "
+		"failed: %d, qos tag: %x\n", nq->qdisc, nq->type,
+		rc, nq->qos_tag);
+
+	atomic_set(&nq->state, NSS_QDISC_STATE_NODE_FREE_SEND_FAIL);
+	wake_up(&nq->wait_queue);
+}
+
+/*
+ * nss_qdisc_root_init_root_assign_callback()
+ *	Invoked on the response to assigning shaper node as root
+ */
+static void nss_qdisc_root_init_root_assign_callback(void *app_data,
+						struct nss_if_msg *nim)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)app_data;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_qdisc_warning("Root assign FAILED for qdisc %px (type %d), "
+			"response type: %d\n", nq->qdisc, nq->type,
+			nim->msg.shaper_configure.config.response_type);
+		nq->pending_final_state = NSS_QDISC_STATE_ROOT_SET_FAIL;
+		nss_qdisc_root_cleanup_free_node(nq);
+		return;
+	}
+
+	nss_qdisc_info("Qdisc %px (type %d): set as root is done. Response - %d"
+			, nq->qdisc, nq->type, nim->msg.shaper_configure.config.response_type);
+	atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+	wake_up(&nq->wait_queue);
+}
+
+/*
+ * nss_qdisc_root_init_alloc_node_callback()
+ *	Invoked on the response to creating a shaper node as root
+ */
+static void nss_qdisc_root_init_alloc_node_callback(void *app_data,
+						struct nss_if_msg *nim)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)app_data;
+	nss_tx_status_t rc;
+	int msg_type;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_qdisc_info("Qdisc %px (type %d) root alloc node FAILED "
+			"response type: %d\n", nq->qdisc, nq->type,
+			nim->msg.shaper_configure.config.response_type);
+
+		nq->pending_final_state = NSS_QDISC_STATE_NODE_ALLOC_FAIL;
+
+		/*
+		 * No shaper node created, cleanup from unsassigning the shaper
+		 */
+		nss_qdisc_root_cleanup_shaper_unassign(nq);
+		return;
+	}
+
+	nss_qdisc_info("Qdisc %px (type %d), shaper node alloc success: %u\n",
+				nq->qdisc, nq->type, nq->shaper_id);
+
+	/*
+	 * Create and send shaper configure message to the NSS interface
+	 */
+	msg_type = nss_qdisc_get_interface_msg(nq->is_bridge, NSS_QDISC_IF_SHAPER_CONFIG);
+	nss_qdisc_msg_init(nim, nq->nss_interface_number, msg_type,
+				sizeof(struct nss_if_shaper_configure),
+				nss_qdisc_root_init_root_assign_callback,
+				nq);
+	nim->msg.shaper_configure.config.request_type = NSS_SHAPER_CONFIG_TYPE_SET_ROOT;
+	nim->msg.shaper_configure.config.msg.set_root_node.qos_tag = nq->qos_tag;
+	rc = nss_if_tx_msg(nq->nss_shaping_ctx, nim);
+
+	if (rc == NSS_TX_SUCCESS) {
+		return;
+	}
+
+	nss_qdisc_warning("Root assign send command failed: %d\n",
+			rc);
+
+	nq->pending_final_state = NSS_QDISC_STATE_ROOT_SET_SEND_FAIL;
+	nss_qdisc_root_cleanup_free_node(nq);
+}
+
+/*
+ * nss_qdisc_root_init_shaper_assign_callback()
+ *	Invoked on the response to a shaper assign config command issued
+ */
+static void nss_qdisc_root_init_shaper_assign_callback(void *app_data,
+						struct nss_if_msg *nim)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)app_data;
+	nss_tx_status_t rc;
+	int msg_type;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_qdisc_warning("Qdisc %x (type %d): shaper assign failed - phys_if response type: %d\n",
+			nq->qos_tag, nq->type, nim->cm.error);
+		/*
+		 * Unable to assign a shaper, perform cleanup from final stage
+		 */
+		nq->pending_final_state = NSS_QDISC_STATE_SHAPER_ASSIGN_FAILED;
+		nss_qdisc_root_cleanup_final(nq);
+		return;
+	}
+
+	if (nim->cm.type != NSS_IF_ISHAPER_ASSIGN && nim->cm.type != NSS_IF_BSHAPER_ASSIGN) {
+		nss_qdisc_error("Qdisc %x (type %d): shaper assign callback received garbage: %d\n",
+			nq->qos_tag, nq->type, nim->cm.type);
+		return;
+	}
+
+	nss_qdisc_info("Qdisc %x (type %d): shaper assign callback received sane message: %d\n",
+		nq->qos_tag, nq->type, nim->cm.type);
+
+	/*
+	 * Shaper has been allocated and assigned
+	 */
+	nq->shaper_id = nim->msg.shaper_assign.new_shaper_id;
+	nss_qdisc_info("Qdisc %px (type %d), shaper assigned: %u\n",
+				nq->qdisc, nq->type, nq->shaper_id);
+
+	/*
+	 * Create and send the shaper configure message to the NSS interface
+	 */
+	msg_type = nss_qdisc_get_interface_msg(nq->is_bridge, NSS_QDISC_IF_SHAPER_CONFIG);
+	nss_qdisc_msg_init(nim, nq->nss_interface_number, msg_type, sizeof(struct nss_if_shaper_configure),
+				nss_qdisc_root_init_alloc_node_callback,
+				nq);
+	nim->msg.shaper_configure.config.request_type = NSS_SHAPER_CONFIG_TYPE_ALLOC_SHAPER_NODE;
+	nim->msg.shaper_configure.config.msg.alloc_shaper_node.node_type = nq->type;
+	nim->msg.shaper_configure.config.msg.alloc_shaper_node.qos_tag = nq->qos_tag;
+	rc = nss_if_tx_msg(nq->nss_shaping_ctx, nim);
+
+	if (rc == NSS_TX_SUCCESS) {
+		return;
+	}
+
+	/*
+	 * Unable to send alloc node command, cleanup from unassigning the shaper
+	 */
+	nss_qdisc_warning("Qdisc %px (type %d) create command failed: %d\n",
+			nq->qdisc, nq->type, rc);
+
+	nq->pending_final_state = NSS_QDISC_STATE_NODE_ALLOC_SEND_FAIL;
+	nss_qdisc_root_cleanup_shaper_unassign(nq);
+}
+
+/*
+ * nss_qdisc_child_cleanup_final()
+ *	Perform final cleanup of a shaper node after all shaper node
+ *	cleanup is complete.
+ */
+static void nss_qdisc_child_cleanup_final(struct nss_qdisc *nq)
+{
+	nss_qdisc_info("Final cleanup type %d: %px\n",
+			nq->type, nq->qdisc);
+
+	/*
+	 * Finally unregister for shaping
+	 */
+	nss_qdisc_info("Unregister for shaping\n");
+	nss_shaper_unregister_shaping(nq->nss_shaping_ctx);
+
+	/*
+	 * Now set our final state
+	 */
+	atomic_set(&nq->state, nq->pending_final_state);
+	wake_up(&nq->wait_queue);
+}
+
+/*
+ * nss_qdisc_child_cleanup_free_node_callback()
+ *	Invoked on the response to freeing a child shaper node
+ */
+static void nss_qdisc_child_cleanup_free_node_callback(void *app_data,
+						struct nss_if_msg *nim)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)app_data;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_qdisc_error("Qdisc %px (type %d qos_tag %x): child free FAILED response type: %d\n",
+			nq->qdisc, nq->type, nq->qos_tag, nim->msg.shaper_configure.config.response_type);
+		atomic_set(&nq->state, NSS_QDISC_STATE_NODE_FREE_FAIL);
+		wake_up(&nq->wait_queue);
+		return;
+	}
+
+	nss_qdisc_info("Qdisc %px (type %d): child shaper node "
+			"free complete\n", nq->qdisc, nq->type);
+
+	/*
+	 * Perform final cleanup
+	 */
+	nss_qdisc_child_cleanup_final(nq);
+}
+
+/*
+ * nss_qdisc_child_cleanup_free_node()
+ *	Free the child shaper node, issue command to do so.
+ */
+static void nss_qdisc_child_cleanup_free_node(struct nss_qdisc *nq)
+{
+	struct nss_if_msg nim;
+	nss_tx_status_t rc;
+	int msg_type;
+
+	nss_qdisc_info("Qdisc %px (type %d qos_tag %x): free shaper node command\n",
+			nq->qdisc, nq->type, nq->qos_tag);
+
+	/*
+	 * Create and send the shaper configure message to the NSS interface
+	 */
+	msg_type = nss_qdisc_get_interface_msg(nq->is_bridge, NSS_QDISC_IF_SHAPER_CONFIG);
+	nss_qdisc_msg_init(&nim, nq->nss_interface_number, msg_type, sizeof(struct nss_if_shaper_configure),
+				nss_qdisc_child_cleanup_free_node_callback,
+				nq);
+	nim.msg.shaper_configure.config.request_type = NSS_SHAPER_CONFIG_TYPE_FREE_SHAPER_NODE;
+	nim.msg.shaper_configure.config.msg.free_shaper_node.qos_tag = nq->qos_tag;
+	rc = nss_if_tx_msg(nq->nss_shaping_ctx, &nim);
+
+	if (rc == NSS_TX_SUCCESS) {
+		return;
+	}
+
+	nss_qdisc_error("Qdisc %px (type %d): child free node command send "
+			"failed: %d, qos tag: %x\n", nq->qdisc, nq->type,
+			rc, nq->qos_tag);
+
+	atomic_set(&nq->state, NSS_QDISC_STATE_NODE_FREE_SEND_FAIL);
+	wake_up(&nq->wait_queue);
+}
+
+/*
+ * nss_qdisc_child_init_alloc_node_callback()
+ *	Invoked on the response to creating a child shaper node
+ */
+static void nss_qdisc_child_init_alloc_node_callback(void *app_data, struct nss_if_msg *nim)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)app_data;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_qdisc_error("Qdisc %px (type %d): child alloc node FAILED, response "
+			"type: %d\n", nq->qdisc, nq->type, nim->msg.shaper_configure.config.response_type);
+		/*
+		 * Cleanup from final stage
+		 */
+		nq->pending_final_state = NSS_QDISC_STATE_NODE_ALLOC_FAIL_CHILD;
+		nss_qdisc_child_cleanup_final(nq);
+		return;
+	}
+
+	/*
+	 * Shaper node has been allocated
+	 */
+	nss_qdisc_info("Qdisc %px (type %d): shaper node successfully "
+			"created as a child node\n", nq->qdisc, nq->type);
+
+	atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+	wake_up(&nq->wait_queue);
+}
+
+/*
+ * nss_qdisc_add_to_tail_protected()
+ *	Adds to list while holding the qdisc lock.
+ */
+static inline void nss_qdisc_add_to_tail_protected(struct sk_buff *skb, struct Qdisc *sch)
+{
+	struct nss_qdisc *nq = qdisc_priv(sch);
+
+	/*
+	 * Since packets can come back from the NSS at any time (in case of bounce),
+	 * enqueue's and dequeue's can cause corruption, if not done within locks.
+	 */
+	spin_lock_bh(&nq->bounce_protection_lock);
+
+	/*
+	 * We do not use the qdisc_enqueue_tail() API here in order
+	 * to prevent stats from getting updated by the API.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	__skb_queue_tail(&sch->q, skb);
+#else
+	__qdisc_enqueue_tail(skb, &sch->q);
+#endif
+
+	spin_unlock_bh(&nq->bounce_protection_lock);
+};
+
+/*
+ * nss_qdisc_add_to_tail()
+ *	Adds to list without holding any locks.
+ */
+static inline void nss_qdisc_add_to_tail(struct sk_buff *skb, struct Qdisc *sch)
+{
+	/*
+	 * We do not use the qdisc_enqueue_tail() API here in order
+	 * to prevent stats from getting updated by the API.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	__skb_queue_tail(&sch->q, skb);
+#else
+	__qdisc_enqueue_tail(skb, &sch->q);
+#endif
+};
+
+/*
+ * nss_qdisc_remove_from_tail_protected()
+ *	Removes from list while holding the qdisc lock.
+ */
+static inline struct sk_buff *nss_qdisc_remove_from_tail_protected(struct Qdisc *sch)
+{
+	struct nss_qdisc *nq = qdisc_priv(sch);
+	struct sk_buff *skb;
+
+	/*
+	 * Since packets can come back from the NSS at any time (in case of bounce),
+	 * enqueue's and dequeue's can cause corruption, if not done within locks.
+	 */
+	spin_lock_bh(&nq->bounce_protection_lock);
+
+	/*
+	 * We use __skb_dequeue() to ensure that
+	 * stats don't get updated twice.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0))
+	skb = __skb_dequeue(&sch->q);
+#else
+	skb = __qdisc_dequeue_head(&sch->q);
+#endif
+	spin_unlock_bh(&nq->bounce_protection_lock);
+	return skb;
+};
+
+/*
+ * nss_qdisc_remove_to_tail_protected()
+ *	Removes from list without holding any locks.
+ */
+static inline struct sk_buff *nss_qdisc_remove_from_tail(struct Qdisc *sch)
+{
+	/*
+	 * We use __skb_dequeue() to ensure that
+	 * stats don't get updated twice.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0))
+	return __skb_dequeue(&sch->q);
+#else
+	return __qdisc_dequeue_head(&sch->q);
+#endif
+};
+
+/*
+ * nss_qdisc_bounce_callback()
+ *	Enqueues packets bounced back from NSS firmware.
+ */
+static void nss_qdisc_bounce_callback(void *app_data, struct sk_buff *skb)
+{
+	struct Qdisc *sch = (struct Qdisc *)app_data;
+
+	/*
+	 * Enqueue the packet for transmit and schedule a dequeue
+	 * This enqueue has to be protected in order to avoid corruption.
+	 */
+	nss_qdisc_add_to_tail_protected(skb, sch);
+	__netif_schedule(sch);
+}
+
+/*
+ * nss_qdisc_mark_and_schedule()
+ *	Mark the classid in packet and enqueue it.
+ */
+static void nss_qdisc_mark_and_schedule(void *app_data, struct sk_buff *skb)
+{
+	struct Qdisc *sch = (struct Qdisc *)app_data;
+	uint16_t temp = TC_H_MAJ(skb->priority) >> 16;
+
+	/*
+	 * Restore the priority field of skb to its value before bouncing.
+	 * Before bounce, we saved the priority value to tc_index field.
+	 *
+	 * Save the qostag of shaped packet to tc_index field.
+	 */
+	skb->priority = (skb->tc_index << 16) | TC_H_MIN(skb->priority);
+	skb->tc_index = temp;
+
+	/*
+	 * Enqueue the packet for transmit and schedule a dequeue
+	 * This enqueue has to be protected in order to avoid corruption.
+	 */
+	nss_qdisc_add_to_tail_protected(skb, sch);
+	__netif_schedule(sch);
+}
+
+/*
+ * nss_qdisc_replace()
+ *	Used to replace old qdisc with a new qdisc.
+ */
+struct Qdisc *nss_qdisc_replace(struct Qdisc *sch, struct Qdisc *new,
+					  struct Qdisc **pold)
+{
+	/*
+	 * The qdisc_replace() API is originally introduced in kernel version 4.6,
+	 * however this has been back ported to the 4.4. kernal used in QSDK.
+	 */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
+	return qdisc_replace(sch, new, pold);
+#else
+	struct Qdisc *old;
+
+	sch_tree_lock(sch);
+	old = *pold;
+	*pold = new;
+	if (old != NULL) {
+		qdisc_tree_decrease_qlen(old, old->q.qlen);
+		qdisc_reset(old);
+	}
+	sch_tree_unlock(sch);
+
+	return old;
+#endif
+}
+
+/*
+ * nss_qdisc_qopt_get()
+ *	Extracts qopt from opt.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+void *nss_qdisc_qopt_get(struct nlattr *opt, struct nla_policy *policy,
+				struct nlattr *tb[], uint32_t tca_max, uint32_t tca_params)
+#else
+void *nss_qdisc_qopt_get(struct nlattr *opt, struct nla_policy *policy,
+				struct nlattr *tb[], uint32_t tca_max, uint32_t tca_params, struct netlink_ext_ack *extack)
+#endif
+{
+	int err;
+
+	if (!opt) {
+		return NULL;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	err = nla_parse_nested(tb, tca_max, opt, policy);
+#else
+	err = nla_parse_nested_deprecated(tb, tca_max, opt, policy, extack);
+#endif
+
+	if (err < 0)
+		return NULL;
+
+	if (tb[tca_params] == NULL)
+		return NULL;
+
+	return nla_data(tb[tca_params]);
+}
+
+/*
+ * nss_qdisc_mode_get()
+ *	Returns the operating mode of nss_qdisc, 0 = nss-fw, 1 = ppe.
+ */
+uint8_t nss_qdisc_accel_mode_get(struct nss_qdisc *nq)
+{
+	if (nq->mode == NSS_QDISC_MODE_PPE) {
+		return TCA_NSS_ACCEL_MODE_PPE;
+	}
+
+	return TCA_NSS_ACCEL_MODE_NSS_FW;
+}
+
+/*
+ * nss_qdisc_peek()
+ *	Called to peek at the head of an nss qdisc
+ */
+struct sk_buff *nss_qdisc_peek(struct Qdisc *sch)
+{
+	struct nss_qdisc *nq = qdisc_priv(sch);
+	struct sk_buff *skb;
+
+	if (!nq->is_virtual) {
+		skb = qdisc_peek_head(sch);
+	} else {
+		spin_lock_bh(&nq->bounce_protection_lock);
+		skb = qdisc_peek_head(sch);
+		spin_unlock_bh(&nq->bounce_protection_lock);
+	}
+
+	return skb;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+/*
+ * nss_qdisc_drop()
+ *	Called to drop the packet at the head of queue
+ */
+unsigned int nss_qdisc_drop(struct Qdisc *sch)
+{
+	struct nss_qdisc *nq = qdisc_priv(sch);
+	unsigned int ret;
+
+	if (!nq->is_virtual) {
+		ret = __qdisc_queue_drop_head(sch, &sch->q);
+	} else {
+		spin_lock_bh(&nq->bounce_protection_lock);
+		/*
+		 * This function is safe to call within locks
+		 */
+		ret = __qdisc_queue_drop_head(sch, &sch->q);
+		spin_unlock_bh(&nq->bounce_protection_lock);
+	}
+
+	return ret;
+}
+#endif
+
+/*
+ * nss_qdisc_reset()
+ *	Called when a qdisc is reset
+ */
+void nss_qdisc_reset(struct Qdisc *sch)
+{
+	struct nss_qdisc *nq = qdisc_priv(sch);
+
+	nss_qdisc_info("Qdisc %px (type %d) resetting\n",
+			sch, nq->type);
+
+	/*
+	 * Delete all packets pending in the output queue and reset stats
+	 */
+	if (!nq->is_virtual) {
+		qdisc_reset_queue(sch);
+	} else {
+		spin_lock_bh(&nq->bounce_protection_lock);
+		/*
+		 * This function is safe to call within locks
+		 */
+		qdisc_reset_queue(sch);
+		spin_unlock_bh(&nq->bounce_protection_lock);
+	}
+
+	nss_qdisc_info("Qdisc %px (type %d) reset complete\n",
+			sch, nq->type);
+}
+
+/*
+ * nss_qdisc_iterate_fl()
+ *	Iterate the filter list over the qdisc.
+ *
+ * Return 1, if the packet need not to be processed further, otherwise, return 0.
+ */
+static bool nss_qdisc_iterate_fl(struct sk_buff *skb, struct Qdisc *sch)
+{
+	struct nss_qdisc *nq = qdisc_priv(sch);
+	struct tcf_proto *tcf;
+	struct tcf_result res;
+	int status;
+
+	if (!(tcf = rcu_dereference_bh(nq->filter_list))) {
+		return 0;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	status = tc_classify(skb, tcf, &res, false);
+#else
+	status = tcf_classify(skb, tcf, &res, false);
+#endif
+	if ((status == TC_ACT_STOLEN) || (status == TC_ACT_QUEUED)) {
+		return 1;
+	}
+
+	/*
+	 * Check the tc filter's action result.
+	 * Save the higher 16-bits of skb's priority field in tc_index
+	 * and update it with the class-id to be used for ingress shaping
+	 * by NSS firmware.
+	 */
+	if (status != TC_ACT_UNSPEC) {
+		skb->tc_index = TC_H_MAJ(skb->priority) >> 16;
+		skb->priority = TC_H_MAKE(res.classid, skb->priority);
+	}
+	return 0;
+}
+
+/*
+ * nss_qdisc_enqueue()
+ *	Generic enqueue call for enqueuing packets into NSS for shaping
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+extern int nss_qdisc_enqueue(struct sk_buff *skb, struct Qdisc *sch)
+#else
+extern int nss_qdisc_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free)
+#endif
+{
+	struct nss_qdisc *nq = qdisc_priv(sch);
+	nss_tx_status_t status;
+
+	/*
+	 * If we are not the root qdisc then we should not be getting packets!!
+	 */
+	if (unlikely(!nq->is_root)) {
+		nss_qdisc_error("Qdisc %px (type %d): unexpected packet "
+			"for child qdisc - skb: %px\n", sch, nq->type, skb);
+		nss_qdisc_add_to_tail(skb, sch);
+		__netif_schedule(sch);
+		return NET_XMIT_SUCCESS;
+	}
+
+	/*
+	 * Packet enueued in linux for transmit.
+	 *
+	 * What we do here depends upon whether we are a bridge or not. If not a
+	 * bridge then it depends on if we are a physical or virtual interface
+	 * The decision we are trying to reach is whether to bounce a packet to
+	 * the NSS to be shaped or not.
+	 *
+	 * is_bridge		is_virtual	Meaning
+	 * ---------------------------------------------------------------------------
+	 * false		false		Physical interface in NSS
+	 *
+	 * Action: Simply allow the packet to be dequeued. The packet will be
+	 * shaped by the interface shaper in the NSS by the usual transmit path.
+	 *
+	 *
+	 * false		true		Physical interface in Linux.
+	 * 					NSS still responsible for shaping
+	 *
+	 * Action: Bounce the packet to the NSS virtual interface that represents
+	 * this Linux physical interface for INTERFACE shaping. When the packet is
+	 * returned from being shaped we allow it to be dequeued for transmit.
+	 *
+	 * true			n/a		Logical Linux interface.
+	 *					Root qdisc created a virtual interface
+	 *					to represent it in the NSS for shaping
+	 *					purposes.
+	 *
+	 * Action: Bounce the packet to the NSS virtual interface (for BRIDGE shaping)
+	 * the bridge root qdisc created for it. When the packet is returned from being
+	 * shaped we allow it to be dequeued for transmit.
+	 */
+
+	/*
+	 * Iterate over the filters attached to the qdisc.
+	 */
+	if (nss_qdisc_iterate_fl(skb, sch)) {
+		kfree_skb(skb);
+		return NET_XMIT_SUCCESS;
+	}
+
+	/*
+	 * Skip the shaping of already shaped packets.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	if (skb->tc_verd & TC_NCLS_NSS) {
+		skb->tc_verd = CLR_TC_NCLS_NSS(skb->tc_verd);
+		nss_qdisc_mark_and_schedule(nq->qdisc, skb);
+		return NET_XMIT_SUCCESS;
+	}
+#else
+	if (skb_skip_tc_classify_offload(skb)) {
+		nss_qdisc_mark_and_schedule(nq->qdisc, skb);
+		return NET_XMIT_SUCCESS;
+	}
+#endif
+
+	if (!nq->is_virtual) {
+		/*
+		 * TX to an NSS physical - the shaping will occur as part of normal
+		 * transmit path.
+		 */
+		nss_qdisc_add_to_tail(skb, sch);
+		__netif_schedule(sch);
+		return NET_XMIT_SUCCESS;
+	}
+
+	if (nq->is_bridge) {
+		/*
+		 * TX to a bridge, this is to be shaped by the b shaper on the virtual interface created
+		 * to represent the bridge interface.
+		 */
+		status = nss_shaper_bounce_bridge_packet(nq->bounce_context, nq->nss_interface_number, skb);
+		if (likely(status == NSS_TX_SUCCESS)) {
+			return NET_XMIT_SUCCESS;
+		}
+
+		nss_qdisc_trace("Qdisc %px (type %d): failed to bounce for bridge %d, skb: %px\n",
+					sch, nq->type, nq->nss_interface_number, skb);
+		goto enqueue_drop;
+	}
+
+	/*
+	 * TX to a physical Linux (NSS virtual).  Bounce packet to NSS for
+	 * interface shaping.
+	 */
+	status = nss_shaper_bounce_interface_packet(nq->bounce_context,
+							nq->nss_interface_number, skb);
+	if (likely(status == NSS_TX_SUCCESS)) {
+		return NET_XMIT_SUCCESS;
+	}
+
+	/*
+	 * We failed to bounce the packet for shaping on a virtual interface
+	 */
+	nss_qdisc_trace("Qdisc %px (type %d): failed to bounce for "
+		"interface: %d, skb: %px\n", sch, nq->type,
+		nq->nss_interface_number, skb);
+
+enqueue_drop:
+	/*
+	 * We were unable to transmit the packet for bridge shaping.
+	 * We therefore drop it.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	kfree_skb(skb);
+
+	spin_lock_bh(&nq->lock);
+	sch->qstats.drops++;
+	spin_unlock_bh(&nq->lock);
+#else
+	qdisc_drop(skb, sch, to_free);
+#endif
+	return NET_XMIT_DROP;
+}
+
+/*
+ * nss_qdisc_dequeue()
+ *	Generic dequeue call for dequeuing bounced packets.
+ */
+inline struct sk_buff *nss_qdisc_dequeue(struct Qdisc *sch)
+{
+	struct nss_qdisc *nq = qdisc_priv(sch);
+
+	/*
+	 * We use the protected dequeue API if the interface involves bounce.
+	 * That is, a bridge or a virtual interface. Else, we use the unprotected
+	 * API.
+	 */
+	if (nq->is_virtual) {
+		return nss_qdisc_remove_from_tail_protected(sch);
+	} else {
+		return nss_qdisc_remove_from_tail(sch);
+	}
+}
+
+/*
+ * nss_qdisc_set_hybrid_mode_callback()
+ *	The callback function for a shaper node set hybrid mode
+ */
+static void nss_qdisc_set_hybrid_mode_callback(void *app_data,
+					struct nss_if_msg *nim)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)app_data;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_qdisc_error("Qdisc %px (type %d): shaper node set default FAILED, response type: %d\n",
+			nq->qdisc, nq->type, nim->msg.shaper_configure.config.response_type);
+		atomic_set(&nq->state, NSS_QDISC_STATE_FAILED_RESPONSE);
+		wake_up(&nq->wait_queue);
+		return;
+	}
+
+	nss_qdisc_info("Qdisc %px (type %d): attach complete\n", nq->qdisc, nq->type);
+	atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+	wake_up(&nq->wait_queue);
+}
+
+/*
+ * nss_qdisc_set_hybrid_mode()
+ *	Configuration function that enables/disables hybrid mode
+ */
+int nss_qdisc_set_hybrid_mode(struct nss_qdisc *nq, enum nss_qdisc_hybrid_mode mode, uint32_t offset)
+{
+	int32_t state, rc;
+	int msg_type;
+	struct nss_if_msg nim;
+
+	nss_qdisc_info("Setting qdisc %px (type %d) as hybrid mode\n",
+			nq->qdisc, nq->type);
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_READY) {
+		nss_qdisc_warning("Qdisc %px (type %d): qdisc state not ready: %d\n",
+				nq->qdisc, nq->type, state);
+		return -1;
+	}
+
+	/*
+	 * Set shaper node state to IDLE
+	 */
+	atomic_set(&nq->state, NSS_QDISC_STATE_IDLE);
+
+	/*
+	 * Create the shaper configure message and send it down to the NSS interface
+	 */
+	msg_type = nss_qdisc_get_interface_msg(nq->is_bridge, NSS_QDISC_IF_SHAPER_CONFIG);
+	nss_qdisc_msg_init(&nim, nq->nss_interface_number, msg_type, sizeof(struct nss_if_shaper_configure),
+				nss_qdisc_set_hybrid_mode_callback,
+				nq);
+
+	if (mode == NSS_QDISC_HYBRID_MODE_ENABLE) {
+		nim.msg.shaper_configure.config.request_type = NSS_SHAPER_CONFIG_TYPE_HYBRID_MODE_ENABLE;
+		nim.msg.shaper_configure.config.msg.set_hybrid_mode.offset = offset;
+	} else {
+		nim.msg.shaper_configure.config.request_type = NSS_SHAPER_CONFIG_TYPE_HYBRID_MODE_DISABLE;
+	}
+
+	rc = nss_if_tx_msg(nq->nss_shaping_ctx, &nim);
+
+	if (rc != NSS_TX_SUCCESS) {
+		nss_qdisc_warning("Failed to send set hybrid mode message for "
+					"qdisc type %d\n", nq->type);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	/*
+	 * Wait until cleanup operation is complete at which point the state
+	 * shall become non-idle.
+	 */
+	if (!wait_event_timeout(nq->wait_queue, atomic_read(&nq->state) != NSS_QDISC_STATE_IDLE,
+				NSS_QDISC_COMMAND_TIMEOUT)) {
+		nss_qdisc_error("set_hybrid_mode for qdisc %x timedout!\n", nq->qos_tag);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_READY) {
+		nss_qdisc_error("Qdisc %px (type %d): failed to set hybrid mode "
+			"State: %d\n", nq->qdisc, nq->type, state);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	nss_qdisc_info("Qdisc %px (type %d): shaper node set hybrid mode complete\n",
+			nq->qdisc, nq->type);
+	return 0;
+}
+
+/*
+ * nss_qdisc_set_default_callback()
+ *	The callback function for a shaper node set default
+ */
+static void nss_qdisc_set_default_callback(void *app_data,
+					struct nss_if_msg *nim)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)app_data;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_qdisc_error("Qdisc %px (type %d): shaper node set default FAILED, response type: %d\n",
+			nq->qdisc, nq->type, nim->msg.shaper_configure.config.response_type);
+		atomic_set(&nq->state, NSS_QDISC_STATE_FAILED_RESPONSE);
+		wake_up(&nq->wait_queue);
+		return;
+	}
+
+	nss_qdisc_info("Qdisc %px (type %d): attach complete\n", nq->qdisc, nq->type);
+	atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+	wake_up(&nq->wait_queue);
+}
+
+/*
+ * nss_qdisc_node_set_default()
+ *	Configuration function that sets shaper node as default for packet enqueue
+ */
+int nss_qdisc_set_default(struct nss_qdisc *nq)
+{
+	int32_t state, rc;
+	int msg_type;
+	struct nss_if_msg nim;
+
+	nss_qdisc_info("Setting qdisc %px (type %d) as default\n",
+			nq->qdisc, nq->type);
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_READY) {
+		nss_qdisc_warning("Qdisc %px (type %d): qdisc state not ready: %d\n",
+				nq->qdisc, nq->type, state);
+		return -1;
+	}
+
+	/*
+	 * Set shaper node state to IDLE
+	 */
+	atomic_set(&nq->state, NSS_QDISC_STATE_IDLE);
+
+	/*
+	 * Create the shaper configure message and send it down to the NSS interface
+	 */
+	msg_type = nss_qdisc_get_interface_msg(nq->is_bridge, NSS_QDISC_IF_SHAPER_CONFIG);
+	nss_qdisc_msg_init(&nim, nq->nss_interface_number, msg_type, sizeof(struct nss_if_shaper_configure),
+				nss_qdisc_set_default_callback,
+				nq);
+	nim.msg.shaper_configure.config.request_type = NSS_SHAPER_CONFIG_TYPE_SET_DEFAULT;
+	nim.msg.shaper_configure.config.msg.set_default_node.qos_tag = nq->qos_tag;
+	rc = nss_if_tx_msg(nq->nss_shaping_ctx, &nim);
+
+	if (rc != NSS_TX_SUCCESS) {
+		nss_qdisc_warning("Failed to send set default message for "
+					"qdisc type %d\n", nq->type);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	/*
+	 * Wait until cleanup operation is complete at which point the state
+	 * shall become non-idle.
+	 */
+	if (!wait_event_timeout(nq->wait_queue, atomic_read(&nq->state) != NSS_QDISC_STATE_IDLE,
+				NSS_QDISC_COMMAND_TIMEOUT)) {
+		nss_qdisc_error("set_default for qdisc %x timedout!\n", nq->qos_tag);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_READY) {
+		nss_qdisc_error("Qdisc %px (type %d): failed to default "
+			"State: %d\n", nq->qdisc, nq->type, state);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	nss_qdisc_info("Qdisc %px (type %d): shaper node default complete\n",
+			nq->qdisc, nq->type);
+	return 0;
+}
+
+/*
+ * nss_qdisc_node_attach_callback()
+ *	The callback function for a shaper node attach message
+ */
+static void nss_qdisc_node_attach_callback(void *app_data,
+					struct nss_if_msg *nim)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)app_data;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_qdisc_info("Qdisc %px (type %d) shaper node attach FAILED - response "
+			"type: %d\n", nq->qdisc, nq->type,
+			nim->msg.shaper_configure.config.response_type);
+		atomic_set(&nq->state, NSS_QDISC_STATE_FAILED_RESPONSE);
+		wake_up(&nq->wait_queue);
+		return;
+	}
+
+	nss_qdisc_info("qdisc type %d: %px, attach complete\n",
+			nq->type, nq->qdisc);
+
+	atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+	wake_up(&nq->wait_queue);
+}
+
+/*
+ * nss_qdisc_node_attach()
+ *	Configuration function that helps attach a child shaper node to a parent.
+ */
+int nss_qdisc_node_attach(struct nss_qdisc *nq, struct nss_qdisc *nq_child,
+			struct nss_if_msg *nim, int32_t attach_type)
+{
+	int32_t state, rc;
+	int msg_type;
+
+	nss_qdisc_info("Qdisc %px (type %d) attaching\n",
+			nq->qdisc, nq->type);
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	if (nq->mode == NSS_QDISC_MODE_PPE) {
+		if (nss_ppe_node_attach(nq, nq_child) < 0) {
+			nss_qdisc_warning("attach of new qdisc %px failed\n", nq_child->qdisc);
+			return -EINVAL;
+
+		}
+		nim->msg.shaper_configure.config.msg.shaper_node_config.snc.ppe_sn_attach.child_qos_tag = nq_child->qos_tag;
+	}
+#endif
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_READY) {
+		nss_qdisc_warning("Qdisc %px (type %d): not ready, state: %d\n",
+				nq->qdisc, nq->type, state);
+		return -1;
+	}
+
+	/*
+	 * Set shaper node state to IDLE
+	 */
+	atomic_set(&nq->state, NSS_QDISC_STATE_IDLE);
+
+	/*
+	 * Create the shaper configure message and send it down to the NSS interface
+	 */
+	msg_type = nss_qdisc_get_interface_msg(nq->is_bridge, NSS_QDISC_IF_SHAPER_CONFIG);
+	nss_qdisc_msg_init(nim, nq->nss_interface_number, msg_type, sizeof(struct nss_if_shaper_configure),
+				nss_qdisc_node_attach_callback,
+				nq);
+	nim->msg.shaper_configure.config.request_type = attach_type;
+	rc = nss_if_tx_msg(nq->nss_shaping_ctx, nim);
+
+	if (rc != NSS_TX_SUCCESS) {
+		nss_qdisc_warning("Failed to send configure message for "
+					"qdisc type %d\n", nq->type);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	/*
+	 * Wait until cleanup operation is complete at which point the state
+	 * shall become non-idle.
+	 */
+	if (!wait_event_timeout(nq->wait_queue, atomic_read(&nq->state) != NSS_QDISC_STATE_IDLE,
+				NSS_QDISC_COMMAND_TIMEOUT)) {
+		nss_qdisc_error("attach for qdisc %x timedout!\n", nq->qos_tag);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_READY) {
+		nss_qdisc_error("Qdisc %px (type %d) failed to attach child "
+			"node, State: %d\n", nq->qdisc, nq->type, state);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	/*
+	 * Save the parent node (helps in debugging)
+	 */
+	spin_lock_bh(&nq_child->lock);
+	nq_child->parent = nq;
+	spin_unlock_bh(&nq_child->lock);
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	/*
+	 * In case of hybrid mode, enable PPE queues when NSS queuing
+	 * Qdiscs are attached in the hierarchy.
+	 */
+	nss_ppe_all_queue_enable_hybrid(nq_child);
+#endif
+
+	nss_qdisc_info("Qdisc %px (type %d): shaper node attach complete\n",
+			nq->qdisc, nq->type);
+	return 0;
+}
+
+/*
+ * nss_qdisc_node_detach_callback()
+ *	The callback function for a shaper node detach message
+ */
+static void nss_qdisc_node_detach_callback(void *app_data,
+					struct nss_if_msg *nim)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)app_data;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_qdisc_info("Qdisc %px (type %d): shaper node detach FAILED - response "
+			"type: %d\n", nq->qdisc, nq->type,
+			nim->msg.shaper_configure.config.response_type);
+		atomic_set(&nq->state, NSS_QDISC_STATE_FAILED_RESPONSE);
+		wake_up(&nq->wait_queue);
+		return;
+	}
+
+	nss_qdisc_info("Qdisc %px (type %d): detach complete\n",
+			nq->qdisc, nq->type);
+
+	atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+	wake_up(&nq->wait_queue);
+}
+
+/*
+ * nss_qdisc_node_detach()
+ *	Configuration function that helps detach a child shaper node to a parent.
+ */
+int nss_qdisc_node_detach(struct nss_qdisc *nq, struct nss_qdisc *nq_child,
+	struct nss_if_msg *nim, int32_t detach_type)
+{
+	int32_t state, rc, msg_type;
+
+	nss_qdisc_info("Qdisc %px (type %d) detaching\n",
+			nq->qdisc, nq->type);
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	if (nq->mode == NSS_QDISC_MODE_PPE) {
+		if (nss_ppe_node_detach(nq, nq_child) < 0) {
+			nss_qdisc_warning("detach of old qdisc %px failed\n", nq_child->qdisc);
+			return -1;
+		}
+		nim->msg.shaper_configure.config.msg.shaper_node_config.snc.ppe_sn_detach.child_qos_tag = nq_child->qos_tag;
+	}
+#endif
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_READY) {
+		nss_qdisc_warning("Qdisc %px (type %d): not ready, state: %d\n",
+				nq->qdisc, nq->type, state);
+		return -1;
+	}
+
+	/*
+	 * Set shaper node state to IDLE
+	 */
+	atomic_set(&nq->state, NSS_QDISC_STATE_IDLE);
+
+	/*
+	 * Create and send the shaper configure message to the NSS interface
+	 */
+	msg_type = nss_qdisc_get_interface_msg(nq->is_bridge, NSS_QDISC_IF_SHAPER_CONFIG);
+	nss_qdisc_msg_init(nim, nq->nss_interface_number, msg_type, sizeof(struct nss_if_shaper_configure),
+				nss_qdisc_node_detach_callback,
+				nq);
+	nim->msg.shaper_configure.config.request_type = detach_type;
+	rc = nss_if_tx_msg(nq->nss_shaping_ctx, nim);
+
+	if (rc != NSS_TX_SUCCESS) {
+		nss_qdisc_warning("Qdisc %px (type %d): Failed to send configure "
+					"message.", nq->qdisc, nq->type);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	/*
+	 * Wait until cleanup operation is complete at which point the state
+	 * shall become non-idle.
+	 */
+	if (!wait_event_timeout(nq->wait_queue, atomic_read(&nq->state) != NSS_QDISC_STATE_IDLE,
+				NSS_QDISC_COMMAND_TIMEOUT)) {
+		nss_qdisc_error("detach for qdisc %x timedout!\n", nq->qos_tag);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_READY) {
+		nss_qdisc_error("Qdisc %px (type %d): failed to detach child node, "
+				"State: %d\n", nq->qdisc, nq->type, state);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	spin_lock_bh(&nq_child->lock);
+	nq_child->parent = NULL;
+	spin_unlock_bh(&nq_child->lock);
+
+	nss_qdisc_info("Qdisc %px (type %d): shaper node detach complete\n",
+			nq->qdisc, nq->type);
+	return 0;
+}
+
+/*
+ * nss_qdisc_configure_callback()
+ *	The call back function for a shaper node configure message
+ */
+static void nss_qdisc_configure_callback(void *app_data,
+				struct nss_if_msg *nim)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)app_data;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_qdisc_info("Qdisc %px (type %d): shaper node configure FAILED "
+			"response type: %d\n", nq->qdisc, nq->type,
+			nim->msg.shaper_configure.config.response_type);
+		atomic_set(&nq->state, NSS_QDISC_STATE_FAILED_RESPONSE);
+		wake_up(&nq->wait_queue);
+		return;
+	}
+
+	/*
+	 * Shapers that need to look at responses for a configure message register
+	 * for a configure callback. This needs to be invoked.
+	 */
+	if (nq->config_cb) {
+		nq->config_cb(nq, &nim->msg.shaper_configure.config);
+	}
+
+	nss_qdisc_info("Qdisc %px (type %d): configuration complete\n",
+			nq->qdisc, nq->type);
+	atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+	wake_up(&nq->wait_queue);
+}
+
+/*
+ * nss_qdisc_configure()
+ *	Configuration function that aids in tuning of queuing parameters.
+ */
+int nss_qdisc_configure(struct nss_qdisc *nq,
+	struct nss_if_msg *nim, int32_t config_type)
+{
+	int32_t state, rc;
+	int msg_type;
+
+	nss_qdisc_info("Qdisc %px (type %d) configuring\n", nq->qdisc, nq->type);
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_READY) {
+		nss_qdisc_warning("Qdisc %px (type %d): not ready for configure, "
+				"state : %d\n", nq->qdisc, nq->type, state);
+		return -1;
+	}
+
+	/*
+	 * Set shaper node state to IDLE
+	 */
+	atomic_set(&nq->state, NSS_QDISC_STATE_IDLE);
+
+	/*
+	 * Create and send the shaper configure message to the NSS interface
+	 */
+	msg_type = nss_qdisc_get_interface_msg(nq->is_bridge, NSS_QDISC_IF_SHAPER_CONFIG);
+	nss_qdisc_msg_init(nim, nq->nss_interface_number, msg_type, sizeof(struct nss_if_shaper_configure),
+				nss_qdisc_configure_callback,
+				nq);
+	nim->msg.shaper_configure.config.request_type = config_type;
+	rc = nss_if_tx_msg(nq->nss_shaping_ctx, nim);
+
+	if (rc != NSS_TX_SUCCESS) {
+		nss_qdisc_warning("Qdisc %px (type %d): Failed to send configure "
+			"message\n", nq->qdisc, nq->type);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	/*
+	 * Wait until cleanup operation is complete at which point the state
+	 * shall become non-idle.
+	 */
+	if (!wait_event_timeout(nq->wait_queue, atomic_read(&nq->state) != NSS_QDISC_STATE_IDLE,
+				NSS_QDISC_COMMAND_TIMEOUT)) {
+		nss_qdisc_error("configure for qdisc %x timedout!\n", nq->qos_tag);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_READY) {
+		nss_qdisc_error("Qdisc %px (type %d): failed to configure shaper "
+			"node: State: %d\n", nq->qdisc, nq->type, state);
+		atomic_set(&nq->state, NSS_QDISC_STATE_READY);
+		return -1;
+	}
+
+	nss_qdisc_info("Qdisc %px (type %d): shaper node configure complete\n",
+			nq->qdisc, nq->type);
+	return 0;
+}
+
+/*
+ * nss_qdisc_register_configure_callback()
+ *	Register shaper configure callback, which gets invoked on receiving a response.
+ */
+void nss_qdisc_register_configure_callback(struct nss_qdisc *nq, nss_qdisc_configure_callback_t cb)
+{
+	nss_qdisc_assert(!nq->config_cb, "Qdisc %px: config callback already registered", nq);
+	nq->config_cb = cb;
+}
+
+/*
+ * nss_qdisc_register_stats_callback()
+ *	Register shaper stats callback, which gets invoked on receiving a stats response.
+ */
+void nss_qdisc_register_stats_callback(struct nss_qdisc *nq, nss_qdisc_stats_callback_t cb)
+{
+	nss_qdisc_assert(!nq->stats_cb, "Qdisc %px: config callback already registered", nq);
+	nq->stats_cb = cb;
+}
+
+/*
+ * nss_qdisc_destroy()
+ *	Destroys a shaper in NSS, and the sequence is based on the position of
+ *	this qdisc (child or root) and the interface to which it is attached to.
+ */
+void nss_qdisc_destroy(struct nss_qdisc *nq)
+{
+	int32_t state;
+	nss_tx_status_t cmd_status;
+
+	nss_qdisc_info("Qdisc %px (type %d) destroy\n",
+			nq->qdisc, nq->type);
+
+	/*
+	 * Destroy any attached filter over qdisc.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	tcf_destroy_chain(&nq->filter_list);
+#else
+	tcf_block_put(nq->block);
+#endif
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	if (nq->mode == NSS_QDISC_MODE_PPE) {
+		nss_ppe_destroy(nq);
+	}
+#endif
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_READY) {
+		nss_qdisc_warning("Qdisc %px (type %d): destroy not ready, "
+				"state: %d\n", nq->qdisc, nq->type, state);
+		return;
+	}
+
+	/*
+	 * How we begin to tidy up depends on whether we are root or child
+	 */
+	nq->pending_final_state = NSS_QDISC_STATE_IDLE;
+	if (!nq->is_root) {
+		nss_qdisc_child_cleanup_free_node(nq);
+	} else {
+
+		/*
+		 * If this is root on a bridge interface, then unassign
+		 * the bshaper from all the attached interfaces.
+		 */
+		if (nq->is_bridge) {
+			nss_qdisc_info("Qdisc %px (type %d): is root on bridge. Need to "
+				"unassign bshapers from its interfaces\n", nq->qdisc, nq->type);
+			nss_qdisc_refresh_bshaper_assignment(nq->qdisc, NSS_QDISC_SCAN_AND_UNASSIGN_BSHAPER);
+		}
+
+		/*
+		 * Begin by freeing the root shaper node
+		 */
+		nss_qdisc_root_cleanup_free_node(nq);
+
+		/*
+		 * In case of IGS interface, release the reference of the IGS module.
+		 */
+		if (nss_igs_verify_if_num(nq->nss_interface_number)) {
+			nss_igs_module_put();
+		}
+	}
+
+	/*
+	 * Wait until cleanup operation is complete at which point the state
+	 * shall become idle.
+	 */
+	if (!wait_event_timeout(nq->wait_queue, atomic_read(&nq->state) == NSS_QDISC_STATE_IDLE,
+				NSS_QDISC_COMMAND_TIMEOUT)) {
+		nss_qdisc_error("destroy command for %x timedout!\n", nq->qos_tag);
+	}
+
+	state = atomic_read(&nq->state);
+	if (state != NSS_QDISC_STATE_IDLE) {
+		nss_qdisc_error("clean up for nss qdisc %x failed with "
+					"status %d\n", nq->qos_tag, state);
+	}
+
+	if (nq->destroy_virtual_interface) {
+		/*
+		 * We are using the sync API here since qdisc operations
+		 * in Linux are expected to operate synchronously.
+		 */
+		cmd_status = nss_virt_if_destroy_sync(nq->virt_if_ctx);
+		if (cmd_status != NSS_TX_SUCCESS) {
+			nss_qdisc_error("Qdisc %px virtual interface %px destroy failed: %d\n",
+						nq->qdisc, nq->virt_if_ctx, cmd_status);
+		}
+		nq->virt_if_ctx = NULL;
+	}
+
+	nss_qdisc_info("Qdisc %px (type %d): destroy complete\n",
+			nq->qdisc, nq->type);
+}
+
+/*
+ * __nss_qdisc_init()
+ *	Initializes a shaper in NSS, based on the position of this qdisc (child or root)
+ *	and if its a normal interface or a bridge interface.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+int __nss_qdisc_init(struct Qdisc *sch, struct nss_qdisc *nq, nss_shaper_node_type_t type, uint32_t classid, uint32_t accel_mode)
+{
+#else
+int __nss_qdisc_init(struct Qdisc *sch, struct nss_qdisc *nq, nss_shaper_node_type_t type, uint32_t classid, uint32_t accel_mode,
+		struct netlink_ext_ack *extack)
+{
+	int err;
+#endif
+	struct Qdisc *root;
+	u32 parent;
+	nss_tx_status_t rc;
+	struct net_device *dev;
+	int32_t state;
+	struct nss_if_msg nim;
+	int msg_type;
+	nss_tx_status_t cmd_status;
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	bool mode_ppe = false;
+#endif
+	bool igs_put = false;
+	if (accel_mode >= TCA_NSS_ACCEL_MODE_MAX) {
+		nss_qdisc_warning("Qdisc %px (type %d) accel_mode:%u should be < %u\n",
+					sch, nq->type, accel_mode, TCA_NSS_ACCEL_MODE_MAX);
+		return -1;
+	}
+
+	/*
+	 * Initialize locks
+	 */
+	spin_lock_init(&nq->bounce_protection_lock);
+	spin_lock_init(&nq->lock);
+
+	/*
+	 * Initialize the wait queue
+	 */
+	init_waitqueue_head(&nq->wait_queue);
+
+	/*
+	 * Add NSS flag to the qdisc
+	 */
+	sch->flags |= TCQ_F_NSS;
+
+	/*
+	 * Record our qdisc, mode and type in the private region for handy use
+	 */
+	nq->qdisc = sch;
+	nq->type = type;
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	/*
+	 * Record user's prefered mode input.
+	 */
+	if (accel_mode == TCA_NSS_ACCEL_MODE_PPE) {
+		mode_ppe = true;
+	}
+#endif
+
+	/*
+	 * We set mode to NSS as default, but if we are successful in creating
+	 * qdisc in PPE, then we will get changed to NSS_QDISC_MODE_PPE.
+	 */
+	nq->mode = NSS_QDISC_MODE_NSS;
+
+	/*
+	 * We dont have to destroy a virtual interface unless
+	 * we are the ones who created it. So set it to false
+	 * by default.
+	 */
+	nq->destroy_virtual_interface = false;
+
+	/*
+	 * Set shaper node state to IDLE
+	 */
+	atomic_set(&nq->state, NSS_QDISC_STATE_IDLE);
+
+	/*
+	 * Initialize filter list.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	RCU_INIT_POINTER(nq->filter_list, NULL);
+#endif
+	/*
+	 * If we are a class, then classid is used as the qos tag.
+	 * Else the qdisc handle will be used as the qos tag.
+	 */
+	if (classid) {
+		nq->qos_tag = classid;
+		nq->is_class = true;
+	} else {
+		nq->qos_tag = (uint32_t)sch->handle;
+		nq->is_class = false;
+	}
+
+	parent = sch->parent;
+
+	/*
+	 * If our parent is TC_H_ROOT and we are not a class, then we are the root qdisc.
+	 * Note, classes might have its qdisc as root, however we should not set is_root to
+	 * true for classes. This is the reason why we check for classid.
+	 */
+	if ((sch->parent == TC_H_ROOT) && (!nq->is_class)) {
+		nss_qdisc_info("Qdisc %px (type %d) is root\n", nq->qdisc, nq->type);
+		nq->is_root = true;
+		root = sch;
+	} else {
+		nss_qdisc_info("Qdisc %px (type %d) not root\n", nq->qdisc, nq->type);
+		nq->is_root = false;
+		root = qdisc_root(sch);
+	}
+
+	/*
+	 * Get the net device as it will tell us if we are on a bridge,
+	 * or on a net device that is represented by a virtual NSS interface (e.g. WIFI)
+	 */
+	dev = qdisc_dev(sch);
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0))
+	/*
+	 * Currently filter addition is only supported over IFB interfaces.
+	 * Therefore, perform tcf block allocation (which is used for storing
+	 * filter list) only if the input net device is an IFB device.
+	 */
+	if (netif_is_ifb_dev(dev)) {
+		err = tcf_block_get(&nq->block, &nq->filter_list, sch, extack);
+		if (err) {
+			nss_qdisc_error("%px: Unable to initialize tcf_block\n", &nq->block);
+			return -1;
+		}
+	} else {
+		RCU_INIT_POINTER(nq->filter_list, NULL);
+		nq->block = NULL;
+	}
+#endif
+
+	nss_qdisc_info("Qdisc %px (type %d) init dev: %px\n", nq->qdisc, nq->type, dev);
+
+	/*
+	 * Determine if dev is a bridge or not as this determines if we
+	 * interract with an I or B shaper.
+	 */
+	if (dev->priv_flags & IFF_EBRIDGE) {
+		nss_qdisc_info("Qdisc %px (type %d) init qdisc: %px, is bridge\n",
+			nq->qdisc, nq->type, nq->qdisc);
+		nq->is_bridge = true;
+	} else {
+		nss_qdisc_info("Qdisc %px (type %d) init qdisc: %px, not bridge\n",
+			nq->qdisc, nq->type, nq->qdisc);
+		nq->is_bridge = false;
+	}
+
+	nss_qdisc_info("Qdisc %px (type %d) init root: %px, qos tag: %x, "
+		"parent: %x rootid: %s owner: %px\n", nq->qdisc, nq->type, root,
+		nq->qos_tag, parent, root->ops->id, root->ops->owner);
+
+	/*
+	 * The root must be of PPE or nss type.
+	 * This is to prevent mixing NSS and PPE qdisc with linux qdisc.
+	 */
+	if ((parent != TC_H_ROOT) && (root->ops->owner != THIS_MODULE)) {
+		nss_qdisc_warning("NSS qdisc %px (type %d) used along with non-nss qdiscs,"
+			" or the interface is currently down", nq->qdisc, nq->type);
+	}
+
+	/*
+	 * Register for NSS shaping
+	 */
+	nq->nss_shaping_ctx = nss_shaper_register_shaping();
+	if (!nq->nss_shaping_ctx) {
+		nss_qdisc_error("no shaping context returned for type %d\n",
+				nq->type);
+		atomic_set(&nq->state, NSS_QDISC_STATE_INIT_FAILED);
+		goto init_fail;
+	}
+
+	/*
+	 * If we are not the root qdisc then we have a simple enough job to do
+	 */
+	if (!nq->is_root) {
+		struct nss_if_msg nim_alloc;
+
+		nss_qdisc_info("Qdisc %px (type %d) initializing non-root qdisc\n",
+				nq->qdisc, nq->type);
+
+		/*
+		 * The device we are operational on MUST be recognised as an NSS interface.
+		 * NOTE: We do NOT support non-NSS known interfaces in this implementation.
+		 * NOTE: This will still work where the dev is registered as virtual, in which case
+		 * nss_interface_number shall indicate a virtual NSS interface.
+		 */
+		nq->nss_interface_number = nss_cmn_get_interface_number(nq->nss_shaping_ctx, dev);
+		if (nq->nss_interface_number < 0) {
+			nss_qdisc_error("Qdisc %px (type %d) net device unknown to "
+				"nss driver %s\n", nq->qdisc, nq->type, dev->name);
+			nss_shaper_unregister_shaping(nq->nss_shaping_ctx);
+			atomic_set(&nq->state, NSS_QDISC_STATE_INIT_FAILED);
+			goto init_fail;
+		}
+
+		/*
+		 * Set the virtual flag
+		 */
+		nq->is_virtual = nss_qdisc_interface_is_virtual(nq->nss_shaping_ctx, nq->nss_interface_number);
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+		/*
+		 * Try initializing PPE Qdisc first.
+		 */
+		if (mode_ppe && nss_qdisc_ppe_init(sch, nq, type, parent) < 0) {
+			nss_qdisc_error("Qdisc %px (type %d) init failed", nq->qdisc, nq->type);
+			nss_shaper_unregister_shaping(nq->nss_shaping_ctx);
+			atomic_set(&nq->state, NSS_QDISC_STATE_INIT_FAILED);
+			goto init_fail;
+		}
+#endif
+
+		/*
+		 * Create a shaper node for requested type.
+		 * Essentially all we need to do is create the shaper node.
+		 */
+		nss_qdisc_info("Qdisc %px (type %d) non-root (child) create\n",
+				nq->qdisc, nq->type);
+
+		/*
+		 * Create and send the shaper configure message to the interface
+		 */
+		msg_type = nss_qdisc_get_interface_msg(nq->is_bridge, NSS_QDISC_IF_SHAPER_CONFIG);
+		nss_qdisc_msg_init(&nim_alloc, nq->nss_interface_number, msg_type, sizeof(struct nss_if_shaper_configure),
+					nss_qdisc_child_init_alloc_node_callback,
+					nq);
+		nim_alloc.msg.shaper_configure.config.request_type = NSS_SHAPER_CONFIG_TYPE_ALLOC_SHAPER_NODE;
+		nim_alloc.msg.shaper_configure.config.msg.alloc_shaper_node.node_type = nq->type;
+		nim_alloc.msg.shaper_configure.config.msg.alloc_shaper_node.qos_tag = nq->qos_tag;
+		rc = nss_if_tx_msg(nq->nss_shaping_ctx, &nim_alloc);
+
+		if (rc != NSS_TX_SUCCESS) {
+			nss_qdisc_error("Qdisc %px (type %d) create command "
+				"failed: %d\n", nq->qdisc, nq->type, rc);
+			nq->pending_final_state = NSS_QDISC_STATE_CHILD_ALLOC_SEND_FAIL;
+			nss_qdisc_child_cleanup_final(nq);
+			goto init_fail;
+		}
+
+		/*
+		 * Wait until init operation is complete.
+		 */
+		if (!wait_event_timeout(nq->wait_queue, atomic_read(&nq->state) != NSS_QDISC_STATE_IDLE,
+					NSS_QDISC_COMMAND_TIMEOUT)) {
+			nss_qdisc_error("init for qdisc %x timedout!\n", nq->qos_tag);
+			return -1;
+		}
+
+		state = atomic_read(&nq->state);
+		nss_qdisc_info("Qdisc %px (type %d): initialised with state: %d\n",
+					nq->qdisc, nq->type, state);
+
+		/*
+		 * If state is positive, return success
+		 */
+		if (state > 0) {
+			return 0;
+		}
+
+		goto init_fail;
+	}
+
+	/*
+	 * Root qdisc has a lot of work to do. It is responsible for setting up
+	 * the shaper and creating the root and default shaper nodes. Also, when
+	 * operating on a bridge, a virtual NSS interface is created to represent
+	 * bridge shaping. Further, when operating on a bridge, we monitor for
+	 * bridge port changes and assign B shapers to the interfaces of the ports.
+	 */
+	nss_qdisc_info("init qdisc type %d : %px, ROOT\n", nq->type, nq->qdisc);
+
+	/*
+	 * Detect if we are operating on a bridge or interface
+	 */
+	if (nq->is_bridge) {
+		nss_qdisc_info("Qdisc %px (type %d): initializing root qdisc on bridge\n",
+			nq->qdisc, nq->type);
+
+		/*
+		 * Since we are a root qdisc on this bridge, we have to create a
+		 * virtual interface to represent this bridge in the NSS (if is does
+		 * not already exist). This will allow us to bounce packets to the
+		 * NSS for bridge shaping.
+		 */
+		nq->nss_interface_number = nss_cmn_get_interface_number(nq->nss_shaping_ctx, dev);
+		if (nq->nss_interface_number < 0) {
+
+			/*
+			 * Case where bridge interface is not already represented
+			 * in the firmware (by clients such as bridge_mgr).
+			 */
+			nq->virt_if_ctx = nss_virt_if_create_sync(dev);
+			if (!nq->virt_if_ctx) {
+				nss_qdisc_error("Qdisc %px (type %d): cannot create virtual interface\n",
+					nq->qdisc, nq->type);
+				nss_shaper_unregister_shaping(nq->nss_shaping_ctx);
+				atomic_set(&nq->state, NSS_QDISC_STATE_INIT_FAILED);
+				goto init_fail;
+			}
+			nss_qdisc_info("Qdisc %px (type %d): virtual interface registered in NSS: %px\n",
+				nq->qdisc, nq->type, nq->virt_if_ctx);
+
+			/*
+			 * We are the one who have created the virtual interface, so we
+			 * must ensure it is destroyed whenever we are done.
+			 */
+			nq->destroy_virtual_interface = true;
+
+			/*
+			 * Save the virtual interface number
+			 */
+			nq->nss_interface_number = nss_virt_if_get_interface_num(nq->virt_if_ctx);
+			nss_qdisc_info("Qdisc %px (type %d) virtual interface number: %d\n",
+					nq->qdisc, nq->type, nq->nss_interface_number);
+		}
+
+		nq->is_virtual = nss_qdisc_interface_is_virtual(nq->nss_shaping_ctx, nq->nss_interface_number);
+
+		/*
+		 * The root qdisc will get packets enqueued to it, so it must
+		 * register for bridge bouncing as it will be responsible for
+		 * bouncing packets to the NSS for bridge shaping.
+		 */
+		if (!nss_igs_verify_if_num(nq->nss_interface_number)) {
+			nq->bounce_context = nss_shaper_register_shaper_bounce_bridge(nq->nss_interface_number,
+					nss_qdisc_bounce_callback, nq->qdisc, THIS_MODULE);
+		} else {
+			nss_qdisc_error("Since %d is an IFB device, it cannot"
+					" register for bridge bouncing\n", nq->nss_interface_number);
+			nss_shaper_unregister_shaping(nq->nss_shaping_ctx);
+			atomic_set(&nq->state, NSS_QDISC_STATE_INIT_FAILED);
+			goto init_fail;
+		}
+
+		if (!nq->bounce_context) {
+			nss_qdisc_error("Qdisc %px (type %d): is root but cannot register "
+					"for bridge bouncing\n", nq->qdisc, nq->type);
+			nss_shaper_unregister_shaping(nq->nss_shaping_ctx);
+			atomic_set(&nq->state, NSS_QDISC_STATE_INIT_FAILED);
+			goto init_fail;
+		}
+
+	} else {
+		nss_qdisc_info("Qdisc %px (type %d): is interface\n", nq->qdisc, nq->type);
+
+		/*
+		 * The device we are operational on MUST be recognised as an NSS interface.
+		 * NOTE: We do NOT support non-NSS known interfaces in this basic implementation.
+		 * NOTE: This will still work where the dev is registered as virtual, in which case
+		 * nss_interface_number shall indicate a virtual NSS interface.
+		 */
+		nq->nss_interface_number = nss_cmn_get_interface_number(nq->nss_shaping_ctx, dev);
+		if (nq->nss_interface_number < 0) {
+			nss_qdisc_error("Qdisc %px (type %d): interface unknown to nss driver %s\n",
+					nq->qdisc, nq->type, dev->name);
+			nss_shaper_unregister_shaping(nq->nss_shaping_ctx);
+			atomic_set(&nq->state, NSS_QDISC_STATE_INIT_FAILED);
+			goto init_fail;
+		}
+
+		/*
+		 * Is the interface virtual or not?
+		 * NOTE: If this interface is virtual then we have to bounce packets to it for shaping
+		 */
+		nq->is_virtual = nss_qdisc_interface_is_virtual(nq->nss_shaping_ctx, nq->nss_interface_number);
+		if (!nq->is_virtual) {
+			nss_qdisc_info("Qdisc %px (type %d): interface %u is physical\n",
+					nq->qdisc, nq->type, nq->nss_interface_number);
+		} else {
+			nss_qdisc_info("Qdisc %px (type %d): interface %u is virtual\n",
+					nq->qdisc, nq->type, nq->nss_interface_number);
+
+			/*
+			 * Register for interface bounce shaping.
+			 */
+			if (!nss_igs_verify_if_num(nq->nss_interface_number)) {
+				nq->bounce_context = nss_shaper_register_shaper_bounce_interface(nq->nss_interface_number,
+						nss_qdisc_bounce_callback, nq->qdisc, THIS_MODULE);
+			} else {
+
+				/*
+				 * In case of IGS interface, take the reference of IGS module.
+				 */
+				if (!nss_igs_module_get()) {
+					nss_qdisc_error("Module reference failed for IGS interface %d"
+							" , Qdisc %px (type %d)\n", nq->nss_interface_number,
+							nq->qdisc, nq->type);
+					nss_shaper_unregister_shaping(nq->nss_shaping_ctx);
+					atomic_set(&nq->state, NSS_QDISC_STATE_INIT_FAILED);
+					goto init_fail;
+				}
+
+				/*
+				 * Set the flag to indicate the IGS module reference get is successful.
+				 * This flag will be used to decrement the IGS module reference in case
+				 * of any error conditions.
+				 */
+				igs_put = true;
+				nq->bounce_context = nss_shaper_register_shaper_bounce_interface(nq->nss_interface_number,
+						nss_qdisc_mark_and_schedule, nq->qdisc, THIS_MODULE);
+			}
+
+			if (!nq->bounce_context) {
+				nss_qdisc_error("Qdisc %px (type %d): is root but failed "
+				"to register for interface bouncing\n", nq->qdisc, nq->type);
+				nss_shaper_unregister_shaping(nq->nss_shaping_ctx);
+				atomic_set(&nq->state, NSS_QDISC_STATE_INIT_FAILED);
+				goto init_fail;
+			}
+		}
+	}
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	/*
+	 * Try initializing PPE Qdisc first.
+	 */
+	if (mode_ppe && nss_qdisc_ppe_init(sch, nq, type, parent) < 0) {
+		nss_qdisc_error("Qdisc %px (type %d) init failed", nq->qdisc, nq->type);
+		nss_shaper_unregister_shaping(nq->nss_shaping_ctx);
+		atomic_set(&nq->state, NSS_QDISC_STATE_INIT_FAILED);
+		goto init_fail;
+	}
+#endif
+
+	/*
+	 * Create and send the shaper assign message to the NSS interface
+	 */
+	msg_type = nss_qdisc_get_interface_msg(nq->is_bridge, NSS_QDISC_IF_SHAPER_ASSIGN);
+	nss_qdisc_msg_init(&nim, nq->nss_interface_number, msg_type, sizeof(struct nss_if_shaper_assign),
+				nss_qdisc_root_init_shaper_assign_callback,
+				nq);
+	nim.msg.shaper_assign.shaper_id = 0;	/* Any free shaper will do */
+	rc = nss_if_tx_msg(nq->nss_shaping_ctx, &nim);
+
+	if (rc != NSS_TX_SUCCESS) {
+		nss_qdisc_error("shaper assign command failed: %d\n", rc);
+		nq->pending_final_state = NSS_QDISC_STATE_ASSIGN_SHAPER_SEND_FAIL;
+		nss_qdisc_root_cleanup_final(nq);
+		goto init_fail;
+	}
+
+	/*
+	 * Wait until init operation is complete.
+	 */
+	if (!wait_event_timeout(nq->wait_queue, atomic_read(&nq->state) != NSS_QDISC_STATE_IDLE,
+				NSS_QDISC_COMMAND_TIMEOUT)) {
+		/*
+		 * Decrement the IGS module reference.
+		 */
+		if (igs_put) {
+			nss_igs_module_put();
+		}
+	nss_qdisc_error("init for qdisc %x timedout!\n", nq->qos_tag);
+		return -1;
+	}
+
+	state = atomic_read(&nq->state);
+	nss_qdisc_info("Qdisc %px (type %d): is initialised with state: %d\n",
+			nq->qdisc, nq->type, state);
+
+	if (state > 0) {
+
+		/*
+		 * Return if this is not a root qdisc on a bridge interface.
+		 */
+		if (!nq->is_root || !nq->is_bridge) {
+			return 0;
+		}
+
+		nss_qdisc_info("This is a bridge interface. Linking bridge ...\n");
+		/*
+		 * This is a root qdisc added to a bridge interface. Now we go ahead
+		 * and add this B-shaper to interfaces known to the NSS
+		 */
+		if (nss_qdisc_refresh_bshaper_assignment(nq->qdisc, NSS_QDISC_SCAN_AND_ASSIGN_BSHAPER) < 0) {
+			nss_qdisc_destroy(nq);
+			nss_qdisc_error("bridge linking failed\n");
+
+			/*
+			 * We do not go to init_fail since nss_qdisc_destroy()
+			 * will take care of deleting the virtual interface.
+			 */
+			return -1;
+		}
+		nss_qdisc_info("Bridge linking complete\n");
+		return 0;
+	}
+
+init_fail:
+
+	/*
+	 * Decrement the IGS module reference.
+	 */
+	if (igs_put) {
+		nss_igs_module_put();
+	}
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	if (nq->mode == NSS_QDISC_MODE_PPE) {
+		nss_ppe_destroy(nq);
+	}
+#endif
+
+	/*
+	 * Destroy any virtual interfaces created by us before returning a failure.
+	 */
+	if (nq->destroy_virtual_interface) {
+		/*
+		 * We are using the sync API here since qdisc operations
+		 * in Linux are expected to operate synchronously.
+		 */
+		cmd_status = nss_virt_if_destroy_sync(nq->virt_if_ctx);
+		if (cmd_status != NSS_TX_SUCCESS) {
+			nss_qdisc_error("Qdisc %px virtual interface %px destroy failed: %d\n",
+						nq->qdisc, nq->virt_if_ctx, cmd_status);
+		}
+		nq->virt_if_ctx = NULL;
+	}
+
+	return -1;
+}
+
+/*
+ * nss_qdisc_init()
+ *	Initialize nss qdisc based on position of the qdisc
+ */
+int nss_qdisc_init(struct Qdisc *sch, struct nss_qdisc *nq, nss_shaper_node_type_t type, uint32_t classid,
+		uint32_t accel_mode, void *extack)
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	return __nss_qdisc_init(sch, nq, type, classid, accel_mode);
+#else
+	return __nss_qdisc_init(sch, nq, type, classid, accel_mode, extack);
+#endif
+}
+
+/*
+ * nss_qdisc_basic_stats_callback()
+ *	Invoked after getting basic stats
+ */
+static void nss_qdisc_basic_stats_callback(void *app_data,
+				struct nss_if_msg *nim)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)app_data;
+	struct Qdisc *qdisc = nq->qdisc;
+	struct gnet_stats_basic_packed *bstats;
+	struct gnet_stats_queue *qstats;
+	struct nss_shaper_node_stats_response *response;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	atomic_t *refcnt;
+#else
+	refcount_t *refcnt;
+#endif
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_qdisc_warning("Qdisc %px (type %d): Receive stats FAILED - "
+			"response: type: %d\n", qdisc, nq->type,
+			nim->msg.shaper_configure.config.response_type);
+		atomic_sub(1, &nq->pending_stat_requests);
+		wake_up(&nq->wait_queue);
+		return;
+	}
+
+	response = &nim->msg.shaper_configure.config.msg.shaper_node_stats_get.response;
+
+	/*
+	 * Get the right stats pointers based on whether it is a class
+	 * or a qdisc.
+	 */
+	if (nq->is_class) {
+		bstats = &nq->bstats;
+		qstats = &nq->qstats;
+		refcnt = &nq->refcnt;
+	} else {
+		bstats = &qdisc->bstats;
+		qstats = &qdisc->qstats;
+		refcnt = &qdisc->refcnt;
+		qdisc->q.qlen = response->sn_stats.qlen_packets;
+	}
+
+	/*
+	 * Update qdisc->bstats
+	 */
+	spin_lock_bh(&nq->lock);
+	bstats->bytes += (__u64)response->sn_stats.delta.dequeued_bytes;
+	bstats->packets += response->sn_stats.delta.dequeued_packets;
+
+	/*
+	 * Update qdisc->qstats
+	 */
+	qstats->backlog = response->sn_stats.qlen_bytes;
+
+	qstats->drops += (response->sn_stats.delta.enqueued_packets_dropped +
+				response->sn_stats.delta.dequeued_packets_dropped);
+
+	/*
+	 * Update qdisc->qstats
+	 */
+	qstats->qlen = response->sn_stats.qlen_packets;
+	qstats->requeues = 0;
+	qstats->overlimits += response->sn_stats.delta.queue_overrun;
+	spin_unlock_bh(&nq->lock);
+
+	/*
+	 * Shapers that maintain additional unique statistics will process them
+	 * via a registered callback. So invoke if its been registered.
+	 */
+	if (nq->stats_cb) {
+		nq->stats_cb(nq, response);
+	}
+
+	/*
+	 * All access to nq fields below do not need lock protection. They
+	 * do not get manipulated on different thread contexts.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	if (atomic_read(refcnt) == 0) {
+#else
+	if (refcount_read(refcnt) == 0) {
+#endif
+		atomic_sub(1, &nq->pending_stat_requests);
+		wake_up(&nq->wait_queue);
+		return;
+	}
+
+	/*
+	 * Requests for stats again, after 1 sec.
+	 */
+	nq->stats_get_timer.expires += HZ;
+	if (nq->stats_get_timer.expires <= jiffies) {
+		nss_qdisc_info("losing time %lu, jiffies = %lu\n",
+				nq->stats_get_timer.expires, jiffies);
+		nq->stats_get_timer.expires = jiffies + HZ;
+	}
+	add_timer(&nq->stats_get_timer);
+}
+
+/*
+ * nss_qdisc_get_stats_timer_callback()
+ *	Invoked periodically to get updated stats
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0))
+static void nss_qdisc_get_stats_timer_callback(unsigned long int data)
+#else
+static void nss_qdisc_get_stats_timer_callback(struct timer_list *tm)
+#endif
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0))
+	struct nss_qdisc *nq = (struct nss_qdisc *)data;
+#else
+	struct nss_qdisc *nq = from_timer(nq, tm, stats_get_timer);
+#endif
+
+	nss_tx_status_t rc;
+	struct nss_if_msg nim;
+	int msg_type;
+
+	/*
+	 * Create and send the shaper configure message to the NSS interface
+	 */
+	msg_type = nss_qdisc_get_interface_msg(nq->is_bridge, NSS_QDISC_IF_SHAPER_CONFIG);
+	nss_qdisc_msg_init(&nim, nq->nss_interface_number, msg_type, sizeof(struct nss_if_shaper_configure),
+				nss_qdisc_basic_stats_callback,
+				nq);
+	nim.msg.shaper_configure.config.request_type = NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_BASIC_STATS_GET;
+	nim.msg.shaper_configure.config.msg.shaper_node_stats_get.qos_tag = nq->qos_tag;
+	rc = nss_if_tx_msg(nq->nss_shaping_ctx, &nim);
+
+	/*
+	 * Check if we failed to send the stats request to NSS.
+	 */
+	if (rc != NSS_TX_SUCCESS) {
+		nss_qdisc_info("%px: stats fetch request dropped, causing "
+				"delay in stats fetch\n", nq->qdisc);
+
+		/*
+		 * Schedule the timer once again for re-trying. Since this is a
+		 * re-try we schedule it 100ms from now, instead of a whole second.
+		 */
+		nq->stats_get_timer.expires = jiffies + HZ/10;
+		add_timer(&nq->stats_get_timer);
+	}
+}
+
+/*
+ * nss_qdisc_start_basic_stats_polling()
+ *	Call to initiate the stats polling timer
+ */
+void nss_qdisc_start_basic_stats_polling(struct nss_qdisc *nq)
+{
+	/*
+	 * In case the stats polling timer is already
+	 * initiated, return. This can happen only when
+	 * there is a fallback from PPE to NSS qdisc.
+	 */
+	if (atomic_read(&nq->pending_stat_requests)) {
+		return;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0))
+	init_timer(&nq->stats_get_timer);
+	nq->stats_get_timer.function = nss_qdisc_get_stats_timer_callback;
+	nq->stats_get_timer.data = (unsigned long)nq;
+#else
+	timer_setup(&nq->stats_get_timer, nss_qdisc_get_stats_timer_callback, 0);
+#endif
+
+	nq->stats_get_timer.expires = jiffies + HZ;
+	atomic_set(&nq->pending_stat_requests, 1);
+	add_timer(&nq->stats_get_timer);
+}
+
+/*
+ * nss_qdisc_stop_basic_stats_polling()
+ *	Call to stop polling of basic stats
+ */
+void nss_qdisc_stop_basic_stats_polling(struct nss_qdisc *nq)
+{
+	/*
+	 * If the timer was active, then delete timer and return.
+	 */
+	if (del_timer(&nq->stats_get_timer) > 0) {
+		/*
+		 * The timer was still active (counting down) when it was deleted.
+		 * Therefore we are sure that there are no pending stats request
+		 * for which we need to wait for. We can therefore return.
+		 */
+		return;
+	}
+
+	/*
+	 * The timer has already fired, which means we have a pending stat response.
+	 * We will have to wait until we have received the pending response.
+	 */
+	if (!wait_event_timeout(nq->wait_queue, atomic_read(&nq->pending_stat_requests) == 0,
+				NSS_QDISC_COMMAND_TIMEOUT)) {
+		nss_qdisc_error("Stats request command for %x timedout!\n", nq->qos_tag);
+	}
+}
+
+/*
+ * nss_qdisc_gnet_stats_copy_basic()
+ *  Wrapper around gnet_stats_copy_basic()
+ */
+int nss_qdisc_gnet_stats_copy_basic(struct Qdisc *sch, struct gnet_dump *d,
+				struct gnet_stats_basic_packed *b)
+{
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 18, 0))
+	return gnet_stats_copy_basic(d, b);
+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	return gnet_stats_copy_basic(d, NULL, b);
+#else
+	return gnet_stats_copy_basic(qdisc_root_sleeping_running(sch), d, NULL, b);
+#endif
+}
+
+/*
+ * nss_qdisc_gnet_stats_copy_queue()
+ *  Wrapper around gnet_stats_copy_queue()
+ */
+int nss_qdisc_gnet_stats_copy_queue(struct gnet_dump *d,
+					struct gnet_stats_queue *q)
+{
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 18, 0))
+	return gnet_stats_copy_queue(d, q);
+#else
+	return gnet_stats_copy_queue(d, NULL, q, q->qlen);
+#endif
+}
+
+/*
+ * nss_qdisc_if_event_cb()
+ *	Callback function that is registered to listen to events on net_device.
+ */
+static int nss_qdisc_if_event_cb(struct notifier_block *unused,
+					unsigned long event, void *ptr)
+{
+	struct net_device *dev;
+	struct net_device *br;
+	struct Qdisc *br_qdisc;
+	int if_num, br_num;
+	struct nss_qdisc *nq;
+
+	dev = nss_qdisc_get_dev(ptr);
+	if (!dev) {
+		nss_qdisc_warning("Received event %lu on NULL interface\n", event);
+		return NOTIFY_DONE;
+	}
+
+	switch (event) {
+	case NETDEV_BR_JOIN:
+	case NETDEV_BR_LEAVE:
+		nss_qdisc_info("Received NETDEV_BR_JOIN/NETDEV_BR_LEAVE on interface %s\n",
+				dev->name);
+		br = nss_qdisc_get_dev_master(dev);
+		if_num = nss_cmn_get_interface_number(nss_qdisc_ctx, dev);
+
+		if (br == NULL || !(br->priv_flags & IFF_EBRIDGE)) {
+			nss_qdisc_error("Sensed bridge activity on interface %s "
+				"that is not on any bridge\n", dev->name);
+			break;
+		}
+
+		br_num = nss_cmn_get_interface_number(nss_qdisc_ctx, br);
+		br_qdisc = br->qdisc;
+		/*
+		 * Ensure the interfaces involved are known to NSS.
+		 */
+		if (if_num < 0 || br_num < 0) {
+			nss_qdisc_info("No action taken since if_num is %d for %s "
+					"and br_num is %d for bridge %s\n", if_num,
+					dev->name, br_num, br->name);
+			break;
+		}
+
+		/*
+		 * Ensure we have nss qdisc configured on the bridge
+		 */
+		if (!(br_qdisc->flags & TCQ_F_NSS)) {
+			nss_qdisc_info("NSS qdisc is not configured on %s interface, "
+					"qdisc id: %s", br->name, br_qdisc->ops->id);
+			break;
+		}
+
+		nq = (struct nss_qdisc *)qdisc_priv(br_qdisc);
+
+		/*
+		 * Call attach or detach according as per event type.
+		 */
+		if (event == NETDEV_BR_JOIN) {
+			nss_qdisc_info("Instructing interface %s to attach to bridge(%s) "
+					"shaping\n", dev->name, br->name);
+			nss_qdisc_attach_bshaper(br_qdisc, if_num);
+		} else if (event == NETDEV_BR_LEAVE) {
+			nss_qdisc_info("Instructing interface %s to detach from bridge(%s) "
+					"shaping\n",dev->name, br->name);
+			nss_qdisc_detach_bshaper(br_qdisc, if_num);
+		}
+
+		break;
+	default:
+		nss_qdisc_info("Received NETDEV_DEFAULT on interface %s\n", dev->name);
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+/*
+ * nss_qdisc_tcf_chain()
+ *	Return the filter list of qdisc.
+ */
+struct tcf_proto __rcu **nss_qdisc_tcf_chain(struct Qdisc *sch, unsigned long arg)
+{
+	struct nss_qdisc *nq = qdisc_priv(sch);
+
+	/*
+	 * Currently filter addition is only supported over IFB interfaces.
+	 */
+	if (!nss_igs_verify_if_num(nq->nss_interface_number)) {
+		nss_qdisc_error("%d is not an ifb interface. Filter addition is only"
+				" supported for IFB interfaces.", nq->nss_interface_number);
+		return NULL;
+	}
+
+	/*
+	 * Currently, support is available only for tc filter iterations
+	 * at root qdisc.
+	 */
+	if (nq->is_root) {
+		return &(nq->filter_list);
+	}
+
+	return NULL;
+}
+#else
+/*
+ * nss_qdisc_tcf_block()
+ *	Return the block containing chain of qdisc.
+ */
+struct tcf_block *nss_qdisc_tcf_block(struct Qdisc *sch, unsigned long cl, struct netlink_ext_ack *extack)
+{
+	struct nss_qdisc *nq = qdisc_priv(sch);
+
+	/*
+	 * Currently, support is available only for tc filter iterations
+	 * at root qdisc.
+	 */
+	if (nq->is_root) {
+		return nq->block;
+	}
+
+	return NULL;
+}
+#endif
+
+/*
+ * nss_qdisc_tcf_bind()
+ *	Bind the filter to the qdisc.
+ *
+ * This is an empty callback, because, currently, tc filter iteration support
+ * is not present at class of a qdisc.
+ */
+unsigned long nss_qdisc_tcf_bind(struct Qdisc *sch, unsigned long parent, u32 classid)
+{
+	return (unsigned long)NULL;
+}
+
+/*
+ * nss_qdisc_tcf_unbind()
+ *	Unbind the filter from the qdisc.
+ *
+ * This is an empty callback, because, currently, tc filter iteration support
+ * is not present at class of a qdisc.
+ */
+void nss_qdisc_tcf_unbind(struct Qdisc *sch, unsigned long arg)
+{
+	return;
+}
+
+static struct notifier_block nss_qdisc_device_notifier = {
+		.notifier_call = nss_qdisc_if_event_cb };
+
+/*
+ * TODO: Get the bridge related code out into nss_qdisc_bridge.c
+ * Get the stats into nss_qdisc_stats.c
+ *
+ */
+
+/* ================== Module registration ================= */
+
+static int __init nss_qdisc_module_init(void)
+{
+	int ret;
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+	nss_qdisc_info("Module initializing\n");
+	nss_qdisc_ctx = nss_shaper_register_shaping();
+
+	ret = register_qdisc(&nss_pfifo_qdisc_ops);
+	if (ret != 0)
+		return ret;
+	nss_qdisc_info("nsspfifo registered\n");
+
+	ret = register_qdisc(&nss_bfifo_qdisc_ops);
+	if (ret != 0)
+		return ret;
+	nss_qdisc_info("nssbfifo registered\n");
+
+	ret = register_qdisc(&nss_codel_qdisc_ops);
+	if (ret != 0)
+		return ret;
+	nss_qdisc_info("nsscodel registered\n");
+
+	ret = register_qdisc(&nss_fq_codel_qdisc_ops);
+	if (ret != 0)
+		return ret;
+	nss_qdisc_info("nssfq_codel registered\n");
+
+	ret = register_qdisc(&nss_tbl_qdisc_ops);
+	if (ret != 0)
+		return ret;
+	nss_qdisc_info("nsstbl registered\n");
+
+	ret = register_qdisc(&nss_prio_qdisc_ops);
+	if (ret != 0)
+		return ret;
+	nss_qdisc_info("nssprio registered\n");
+
+	ret = register_qdisc(&nss_bf_qdisc_ops);
+	if (ret != 0)
+		return ret;
+	nss_qdisc_info("nssbf registered\n");
+
+	ret = register_qdisc(&nss_wrr_qdisc_ops);
+	if (ret != 0)
+		return ret;
+	nss_qdisc_info("nsswrr registered\n");
+
+	ret = register_qdisc(&nss_wfq_qdisc_ops);
+	if (ret != 0)
+		return ret;
+	nss_qdisc_info("nsswfq registered\n");
+
+	ret = register_qdisc(&nss_htb_qdisc_ops);
+	if (ret != 0)
+		return ret;
+	nss_qdisc_info("nsshtb registered\n");
+
+	ret = register_qdisc(&nss_blackhole_qdisc_ops);
+	if (ret != 0)
+		return ret;
+	nss_qdisc_info("nssblackhole registered\n");
+
+	ret = register_qdisc(&nss_red_qdisc_ops);
+	if (ret != 0)
+		return ret;
+	nss_qdisc_info("nssred registered\n");
+
+	ret = register_qdisc(&nss_wred_qdisc_ops);
+	if (ret != 0)
+		return ret;
+	nss_qdisc_info("nsswred registered\n");
+
+	ret = register_netdevice_notifier(&nss_qdisc_device_notifier);
+	if (ret != 0)
+		return ret;
+	nss_qdisc_info("nss qdisc device notifiers registered\n");
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	nss_ppe_port_res_alloc();
+	nss_qdisc_info("nss ppe qdsic configured");
+#endif
+
+	return 0;
+}
+
+static void __exit nss_qdisc_module_exit(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return;
+	}
+#endif
+
+	unregister_qdisc(&nss_pfifo_qdisc_ops);
+	nss_qdisc_info("nsspfifo unregistered\n");
+
+	unregister_qdisc(&nss_bfifo_qdisc_ops);
+	nss_qdisc_info("nssbfifo unregistered\n");
+
+	unregister_qdisc(&nss_codel_qdisc_ops);
+	nss_qdisc_info("nsscodel unregistered\n");
+
+	unregister_qdisc(&nss_fq_codel_qdisc_ops);
+	nss_qdisc_info("nssfq_codel unregistered\n");
+
+	unregister_qdisc(&nss_tbl_qdisc_ops);
+	nss_qdisc_info("nsstbl unregistered\n");
+
+	unregister_qdisc(&nss_prio_qdisc_ops);
+	nss_qdisc_info("nssprio unregistered\n");
+
+	unregister_qdisc(&nss_bf_qdisc_ops);
+	nss_qdisc_info("nssbf unregistered\n");
+
+	unregister_qdisc(&nss_wrr_qdisc_ops);
+	nss_qdisc_info("nsswrr unregistered\n");
+
+	unregister_qdisc(&nss_wfq_qdisc_ops);
+	nss_qdisc_info("nsswfq unregistered\n");
+
+	unregister_qdisc(&nss_htb_qdisc_ops);
+	nss_qdisc_info("nsshtb unregistered\n");
+
+	unregister_qdisc(&nss_blackhole_qdisc_ops);
+	nss_qdisc_info("nssblackhole unregistered\n");
+
+	unregister_qdisc(&nss_red_qdisc_ops);
+	nss_qdisc_info("nssred unregistered\n");
+
+	unregister_qdisc(&nss_wred_qdisc_ops);
+	nss_qdisc_info("nsswred unregistered\n");
+
+	unregister_netdevice_notifier(&nss_qdisc_device_notifier);
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	nss_ppe_port_res_free();
+	nss_qdisc_info("nss_ppe_port_res_free\n");
+#endif
+}
+
+module_init(nss_qdisc_module_init)
+module_exit(nss_qdisc_module_exit)
+
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/qca-nss-clients/nss_qdisc/nss_qdisc.h b/qca-nss-clients/nss_qdisc/nss_qdisc.h
new file mode 100644
index 0000000..3b7381c
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_qdisc.h
@@ -0,0 +1,488 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, 2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/skbuff.h>
+#include <net/pkt_sched.h>
+#include <net/pkt_cls.h>
+#include <net/inet_ecn.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <linux/if_bridge.h>
+#include <linux/list.h>
+#include <linux/version.h>
+#include <br_private.h>
+#include <nss_api_if.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0))
+#include <linux/netlink.h>
+#endif
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+#include "nss_ppe.h"
+#endif
+
+#define NSS_QDISC_DEBUG_LEVEL_ERROR 1
+#define NSS_QDISC_DEBUG_LEVEL_WARN 2
+#define NSS_QDISC_DEBUG_LEVEL_INFO 3
+#define NSS_QDISC_DEBUG_LEVEL_TRACE 4
+
+/*
+ * Debug message for module init and exit
+ */
+#define nss_qdisc_info_always(s, ...) printk(KERN_INFO"%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+/*
+ * Error and warn message will be enabled by default in Makefile
+ */
+#if (NSS_QDISC_DEBUG_LEVEL < NSS_QDISC_DEBUG_LEVEL_ERROR)
+#define nss_qdisc_assert(s, ...)
+#define nss_qdisc_error(s, ...)
+#else
+#define nss_qdisc_assert(c, s, ...) { if (!(c)) { pr_emerg("ASSERT: %s:%d:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__); BUG(); } }
+#define nss_qdisc_error(s, ...) pr_err("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_QDISC_DEBUG_LEVEL < NSS_QDISC_DEBUG_LEVEL_WARN)
+#define nss_qdisc_warning(s, ...)
+#else
+#define nss_qdisc_warning(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_qdisc_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_qdisc_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+#else
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_QDISC_DEBUG_LEVEL < NSS_QDISC_DEBUG_LEVEL_INFO)
+#define nss_qdisc_info(s, ...)
+#else
+#define nss_qdisc_info(s, ...) pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_QDISC_DEBUG_LEVEL < NSS_QDISC_DEBUG_LEVEL_TRACE)
+#define nss_qdisc_trace(s, ...)
+#else
+#define nss_qdisc_trace(s, ...) pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif
+
+/*
+ * State values
+ */
+#define NSS_QDISC_STATE_IDLE 0
+#define NSS_QDISC_STATE_READY 1
+
+#define NSS_QDISC_STATE_INIT_FAILED -1
+#define NSS_QDISC_STATE_ASSIGN_SHAPER_SEND_FAIL -2
+#define NSS_QDISC_STATE_SHAPER_ASSIGN_FAILED -3
+#define NSS_QDISC_STATE_NODE_ALLOC_SEND_FAIL -4
+#define NSS_QDISC_STATE_NODE_ALLOC_FAIL -5
+#define NSS_QDISC_STATE_ROOT_SET_SEND_FAIL -6
+#define NSS_QDISC_STATE_ROOT_SET_FAIL -7
+#define NSS_QDISC_STATE_DEFAULT_SET_SEND_FAIL -8
+#define NSS_QDISC_STATE_DEFAULT_SET_FAIL -9
+#define NSS_QDISC_STATE_CHILD_ALLOC_SEND_FAIL -10
+#define NSS_QDISC_STATE_NODE_ALLOC_FAIL_CHILD -11
+#define NSS_QDISC_STATE_FAILED_RESPONSE -12
+#define NSS_QDISC_STATE_UNASSIGN_SHAPER_SEND_FAIL -13
+#define NSS_QDISC_STATE_UNASSIGN_SHAPER_FAIL -14
+#define NSS_QDISC_STATE_NODE_FREE_FAIL -15
+#define NSS_QDISC_STATE_NODE_FREE_SEND_FAIL -16
+
+#define NSS_QDISC_BRIDGE_PORT_MAX 100
+
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3,8,0))
+#define nss_qdisc_hlist_for_each_entry(tpos, pos, head, member) hlist_for_each_entry(tpos, pos, head, member)
+#define nss_qdisc_hlist_for_each_entry_safe(tpos, pos, n, head, member) hlist_for_each_entry_safe(tpos, pos, n, head, member)
+#define nss_qdisc_get_dev_master(dev) (dev->master)
+#define nss_qdisc_get_dev(ptr) (struct net_device *)ptr
+#else
+#define nss_qdisc_hlist_for_each_entry(tpos, pos, head, member) hlist_for_each_entry(tpos, head, member)
+#define nss_qdisc_hlist_for_each_entry_safe(tpos, pos, n, head, member) hlist_for_each_entry_safe(tpos, n, head, member)
+#define nss_qdisc_get_dev_master(dev) netdev_master_upper_dev_get(dev)
+#define nss_qdisc_get_dev(ptr) netdev_notifier_info_to_dev(ptr)
+#endif
+
+/*
+ * Mode of Qdisc/class
+ * These are defined as Magic numbers to avoid false positives
+ */
+#define NSS_QDISC_MODE_NSS 0x6243
+#define NSS_QDISC_MODE_PPE 0x6245
+
+struct nss_qdisc;
+
+typedef void (*nss_qdisc_stats_callback_t)(struct nss_qdisc *nq, struct nss_shaper_node_stats_response *response);
+typedef void (*nss_qdisc_configure_callback_t)(struct nss_qdisc *nq, struct nss_shaper_configure *response);
+
+struct nss_qdisc {
+	struct Qdisc *qdisc;			/* Handy pointer back to containing qdisc */
+	struct nss_qdisc *parent;		/* Pointer to parent nss qdisc */
+	void *nss_shaping_ctx;			/* NSS context for general operations */
+	int32_t nss_interface_number;		/* NSS Interface number we are shaping on */
+	nss_shaper_node_type_t type;		/* Type of shaper node */
+	bool is_class;				/* True if this represents a class and not a qdisc */
+	bool is_root;				/* True if root qdisc on a net device */
+	bool is_bridge;				/* True when qdisc is a bridge */
+	bool is_virtual;			/* True when the device is represented as a virtual in
+						 * the NSS e.g. perhaps operating on a wifi interface
+						 * or bridge.
+						 */
+	bool needs_ppe_loopback;		/* True when qdisc is on bridge or igs */
+	bool destroy_virtual_interface;		/* Set if the interface is first registered in NSS by
+						 * us. This means it needs to be un-regisreted when the
+						 * module goes down.
+						 */
+	atomic_t state;				/* < 0: Signal that qdisc has 'failed'. 0
+						 * indicates 'pending' setup.  > 0 is READY.
+						 * NOTE: volatile AND atomic - this is polled
+						 * AND is used for syncronisation.
+						 */
+	uint32_t shaper_id;			/* Used when is_root. Child qdiscs use this
+						 * information to know what shaper under
+						 * which to create shaper nodes
+						 */
+	uint32_t qos_tag;			/* QoS tag of this node */
+	volatile int32_t pending_final_state;	/* Used to let the callback cycle know what
+						 * state to set the qdisc in on successful
+						 * completion.
+						 */
+	struct nss_virt_if_handle *virt_if_ctx;	/* Context provided by the NSS driver for
+						 * new interfaces that are registered.
+						 */
+	void *bounce_context;			/* Context for bounce registration. Bounce
+						 * enables packets to be sent to NSS for
+						 * shaping purposes, and is returned to
+						 * Linux for transmit.
+						 */
+	spinlock_t bounce_protection_lock;	/* Lock to protect the enqueue and dequeue
+						 * operation on skb lists triggeret by bounce
+						 * callbacks.
+						 */
+	nss_qdisc_stats_callback_t stats_cb;
+						/* Stats update callback function for qdisc specific
+						 * stats update.
+						 */
+	nss_qdisc_configure_callback_t config_cb;
+						/* Shaper configure callback for reading shaper specific
+						 * responses (e.g. memory size).
+						 */
+	struct gnet_stats_basic_packed bstats;	/* Basic class statistics */
+	struct gnet_stats_queue qstats;		/* Qstats for use by classes */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	atomic_t refcnt;			/* Reference count for class use */
+#else
+	refcount_t refcnt;			/* Reference count for class use */
+#endif
+	struct timer_list stats_get_timer;	/* Timer used to poll for stats */
+	atomic_t pending_stat_requests;		/* Number of pending stats responses */
+	wait_queue_head_t wait_queue;		/* Wait queue used to wait on responses from the NSS */
+	spinlock_t lock;			/* Lock to protect the nss qdisc structure */
+	uint16_t mode;				/* Mode of Qdisc/class */
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	struct nss_ppe_qdisc npq;		/* PPE Qdisc */
+	bool ppe_init_failed;			/* Flag is set if PPE initialization fails */
+	bool hybrid_configured;			/* Flag is set only in root qdisc when first NSS Qdisc
+						 * is attached to PPE qdisc in the tree.
+						 */
+#endif
+	struct tcf_proto __rcu *filter_list;	/* Filter list */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0))
+	struct tcf_block *block;
+#endif
+};
+
+/*
+ * nss_qdisc bridge update structure
+ */
+struct nss_qdisc_bridge_update {
+	int port_list[NSS_QDISC_BRIDGE_PORT_MAX];
+	int port_list_count;
+	int unassign_count;
+};
+
+/*
+ * Task types for bridge scanner.
+ */
+enum nss_qdisc_bshaper_tasks {
+	NSS_QDISC_SCAN_AND_ASSIGN_BSHAPER,
+	NSS_QDISC_SCAN_AND_UNASSIGN_BSHAPER,
+};
+
+/*
+ * Types of messages sent down to NSS interfaces
+ */
+enum nss_qdisc_interface_msgs {
+	NSS_QDISC_IF_SHAPER_ASSIGN,
+	NSS_QDISC_IF_SHAPER_UNASSIGN,
+	NSS_QDISC_IF_SHAPER_CONFIG,
+};
+
+/*
+ * Types of mode for hybrid configuration.
+ */
+enum nss_qdisc_hybrid_mode {
+	NSS_QDISC_HYBRID_MODE_DISABLE,
+	NSS_QDISC_HYBRID_MODE_ENABLE,
+};
+
+/*
+ * nss_qdisc_nla_nest_start()
+ *	Returns the container attribute
+ */
+static inline struct nlattr * nss_qdisc_nla_nest_start(struct sk_buff *skb, int attrtype)
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	return nla_nest_start(skb, TCA_OPTIONS);
+#else
+	return nla_nest_start_noflag(skb, TCA_OPTIONS);
+#endif
+}
+
+/*
+ * nss_qdisc_atomic_sub()
+ *	Atomically decrements the ref count by 1
+ */
+static inline void nss_qdisc_atomic_sub(struct nss_qdisc *nq)
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	atomic_sub(1, &nq->refcnt);
+#else
+	atomic_sub(1, &nq->refcnt.refs);
+#endif
+}
+
+/*
+ * nss_qdisc_atomic_sub_return()
+ *	Atomically decrements the ref count by 1 and return ref count
+ */
+static inline int nss_qdisc_atomic_sub_return(struct nss_qdisc *nq)
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	return atomic_sub_return(1, &nq->refcnt);
+#else
+	return atomic_sub_return(1, &nq->refcnt.refs);
+#endif
+}
+
+/*
+ * nss_qdisc_atomic_set()
+ *	Atomically sets the ref count by 1
+ */
+static inline void nss_qdisc_atomic_set(struct nss_qdisc *nq)
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	atomic_set(&nq->refcnt, 1);
+#else
+	refcount_set(&nq->refcnt, 1);
+#endif
+}
+
+/*
+ * nss_qdisc_put()
+ *	Destroy the qdisc
+ */
+static inline void nss_qdisc_put(struct Qdisc *sch)
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0))
+	qdisc_destroy(sch);
+#else
+	qdisc_put(sch);
+#endif
+}
+
+/*
+ * nss_qdisc_qopt_get()
+ *	Extracts qopt from opt.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+extern void *nss_qdisc_qopt_get(struct nlattr *opt, struct nla_policy *policy,
+				struct nlattr *tb[], uint32_t tca_max, uint32_t tca_params);
+#else
+extern void *nss_qdisc_qopt_get(struct nlattr *opt, struct nla_policy *policy,
+				struct nlattr *tb[], uint32_t tca_max, uint32_t tca_params, struct netlink_ext_ack *extack);
+#endif
+
+/*
+ * nss_qdisc_mode_get()
+ *	Returns the operating mode of nss_qdisc, 0 = nss-fw, 1 = ppe.
+ */
+extern uint8_t nss_qdisc_accel_mode_get(struct nss_qdisc *nq);
+
+/*
+ * nss_qdisc_peek()
+ *	Called to peek at the head of an nss qdisc
+ */
+extern struct sk_buff *nss_qdisc_peek(struct Qdisc *sch);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+/*
+ * nss_qdisc_drop()
+ *	Called to drop the packet at the head of queue
+ */
+extern unsigned int nss_qdisc_drop(struct Qdisc *sch);
+#endif
+
+/*
+ * nss_qdisc_reset()
+ *	Called when a qdisc is reset
+ */
+extern void nss_qdisc_reset(struct Qdisc *sch);
+
+/*
+ * nss_qdisc_enqueue()
+ *	Generic enqueue call for enqueuing packets into NSS for shaping
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+extern int nss_qdisc_enqueue(struct sk_buff *skb, struct Qdisc *sch);
+#else
+extern int nss_qdisc_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free);
+#endif
+
+/*
+ * nss_qdisc_dequeue()
+ *	Generic dequeue call for dequeuing bounced packets.
+ */
+extern struct sk_buff *nss_qdisc_dequeue(struct Qdisc *sch);
+
+/*
+ * nss_qdisc_set_hybrid_mode()
+ *	Configuration function that enables/disables hybrid mode
+ */
+extern int nss_qdisc_set_hybrid_mode(struct nss_qdisc *nq, enum nss_qdisc_hybrid_mode mode, uint32_t offset);
+
+/*
+ * nss_qdisc_node_set_default()
+ *	Configuration function that sets shaper node as default for packet enqueue
+ */
+extern int nss_qdisc_set_default(struct nss_qdisc *nq);
+
+/*
+ * nss_qdisc_node_attach()
+ *	Configuration function that helps attach a child shaper node to a parent.
+ */
+extern int nss_qdisc_node_attach(struct nss_qdisc *nq, struct nss_qdisc *nq_child,
+					struct nss_if_msg *nim, int32_t attach_type);
+
+/*
+ * nss_qdisc_node_detach()
+ *	Configuration function that helps detach a child shaper node to a parent.
+ */
+extern int nss_qdisc_node_detach(struct nss_qdisc *nq, struct nss_qdisc *nq_child,
+					struct nss_if_msg *nim, int32_t detach_type);
+
+/*
+ * nss_qdisc_configure()
+ *	Configuration function that aids in tuning of queuing parameters.
+ */
+extern int nss_qdisc_configure(struct nss_qdisc *nq,
+	struct nss_if_msg *nim, int32_t config_type);
+
+
+/*
+ * nss_qdisc_register_configure_callback()
+ *	Register shaper configure callback, which gets invoked on receiving a response.
+ */
+extern void nss_qdisc_register_configure_callback(struct nss_qdisc *nq, nss_qdisc_configure_callback_t cb);
+
+/*
+ * nss_qdisc_register_stats_callback()
+ *	Register shaper stats callback, which gets invoked on receiving a stats response.
+ */
+extern void nss_qdisc_register_stats_callback(struct nss_qdisc *nq, nss_qdisc_stats_callback_t cb);
+
+/*
+ * nss_qdisc_destroy()
+ *	Destroys a shaper in NSS, and the sequence is based on the position of
+ *	this qdisc (child or root) and the interface to which it is attached to.
+ */
+extern void nss_qdisc_destroy(struct nss_qdisc *nq);
+
+/*
+ * nss_qdisc_init()
+ *	Initializes a shaper in NSS, based on the position of this qdisc (child or root)
+ *	and if its a normal interface or a bridge interface.
+ */
+extern int nss_qdisc_init(struct Qdisc *sch, struct nss_qdisc *nq, nss_shaper_node_type_t type, uint32_t classid, uint32_t accel_mode,
+		void *extack);
+
+/*
+ * nss_qdisc_start_basic_stats_polling()
+ *	Call to initiate the stats polling timer
+ */
+extern void nss_qdisc_start_basic_stats_polling(struct nss_qdisc *nq);
+
+/*
+ * nss_qdisc_stop_basic_stats_polling()
+ *	Call to stop polling of basic stats
+ */
+extern void nss_qdisc_stop_basic_stats_polling(struct nss_qdisc *nq);
+
+/*
+ * nss_qdisc_gnet_stats_copy_basic()
+ *  Wrapper around gnet_stats_copy_basic()
+ */
+extern int nss_qdisc_gnet_stats_copy_basic(struct Qdisc *sch,
+				struct gnet_dump *d, struct gnet_stats_basic_packed *b);
+
+/*
+ * nss_qdisc_gnet_stats_copy_queue()
+ *  Wrapper around gnet_stats_copy_queue()
+ */
+extern int nss_qdisc_gnet_stats_copy_queue(struct gnet_dump *d,
+				struct gnet_stats_queue *q);
+
+/*
+ * nss_qdisc_replace()
+ *	Used to replace old qdisc with a new one
+ */
+extern struct Qdisc *nss_qdisc_replace(struct Qdisc *sch, struct Qdisc *new,
+					struct Qdisc **pold);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+/*
+ * nss_qdisc_tcf_chain()
+ *	Return the filter list of qdisc.
+ */
+extern struct tcf_proto __rcu **nss_qdisc_tcf_chain(struct Qdisc *sch, unsigned long arg);
+#else
+/*
+ * nss_qdisc_tcf_block()
+ *	Return the block containing chain of qdisc.
+ */
+extern struct tcf_block *nss_qdisc_tcf_block(struct Qdisc *sch, unsigned long cl, struct netlink_ext_ack *extack);
+#endif
+
+/*
+ * nss_qdisc_tcf_bind()
+ *	Bind the filter to the qdisc.
+ */
+extern unsigned long nss_qdisc_tcf_bind(struct Qdisc *sch, unsigned long parent, u32 classid);
+
+/*
+ * nss_qdisc_tcf_unbind()
+ *	Unbind the filter from the qdisc.
+ */
+extern void nss_qdisc_tcf_unbind(struct Qdisc *sch, unsigned long arg);
diff --git a/qca-nss-clients/nss_qdisc/nss_tbl.c b/qca-nss-clients/nss_qdisc/nss_tbl.c
new file mode 100644
index 0000000..ddca81b
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_tbl.c
@@ -0,0 +1,465 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2017, 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_qdisc.h"
+
+struct nss_tbl_sched_data {
+	struct nss_qdisc nq;	/* Common base class for all nss qdiscs */
+	u32 rate;		/* Limiting rate of TBL */
+	u32 peakrate;		/* Maximum rate to control bursts */
+	u32 burst;		/* Maximum allowed burst size */
+	u32 mtu;		/* MTU of the interface attached to */
+	struct Qdisc *qdisc;	/* Qdisc to which it is attached to */
+};
+
+static struct nla_policy nss_tbl_policy[TCA_NSSTBL_MAX + 1] = {
+	[TCA_NSSTBL_PARMS] = { .len = sizeof(struct tc_nsstbl_qopt) },
+};
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+static int nss_tbl_enqueue(struct sk_buff *skb, struct Qdisc *sch)
+#else
+static int nss_tbl_enqueue(struct sk_buff *skb, struct Qdisc *sch,
+				struct sk_buff **to_free)
+#endif
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	return nss_qdisc_enqueue(skb, sch);
+#else
+	return nss_qdisc_enqueue(skb, sch, to_free);
+#endif
+}
+
+static struct sk_buff *nss_tbl_dequeue(struct Qdisc *sch)
+{
+	return nss_qdisc_dequeue(sch);
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+static unsigned int nss_tbl_drop(struct Qdisc *sch)
+{
+	return nss_qdisc_drop(sch);
+}
+#endif
+
+static struct sk_buff *nss_tbl_peek(struct Qdisc *sch)
+{
+	return nss_qdisc_peek(sch);
+}
+
+static void nss_tbl_reset(struct Qdisc *sch)
+{
+	nss_qdisc_reset(sch);
+}
+
+static void nss_tbl_destroy(struct Qdisc *sch)
+{
+	struct nss_tbl_sched_data *q = qdisc_priv(sch);
+	struct nss_qdisc *nq_child = (struct nss_qdisc *)qdisc_priv(q->qdisc);
+	struct nss_if_msg nim;
+
+	/*
+	 * We must always detach our child node in NSS before destroying it.
+	 * Also, we make sure we dont send down the command for noop qdiscs.
+	 */
+	if (q->qdisc != &noop_qdisc) {
+		nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+		if (nss_qdisc_node_detach(&q->nq, nq_child, &nim,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+			nss_qdisc_error("Failed to detach child %x from nss_tbl %x\n",
+					q->qdisc->handle, q->nq.qos_tag);
+			return;
+		}
+	}
+
+	/*
+	 * Now we can destroy our child qdisc
+	 */
+	 nss_qdisc_put(q->qdisc);
+
+	/*
+	 * Stop the polling of basic stats and destroy qdisc.
+	 */
+	nss_qdisc_stop_basic_stats_polling(&q->nq);
+	nss_qdisc_destroy(&q->nq);
+}
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_tbl_ppe_change(struct Qdisc *sch, struct nlattr *opt)
+#else
+static int nss_tbl_ppe_change(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack)
+#endif
+{
+	struct nss_tbl_sched_data *q = qdisc_priv(sch);
+	struct nss_qdisc *nq = &q->nq;
+	struct nss_ppe_qdisc prev_npq;
+
+	/*
+	 * Save previous configuration for reset purpose
+	 */
+	if (nq->npq.is_configured) {
+		prev_npq = nq->npq;
+	}
+
+	nq->npq.shaper_present = true;
+	nq->npq.shaper.rate = q->rate;
+	nq->npq.shaper.burst = q->burst;
+	nq->npq.shaper.crate = q->rate;
+	nq->npq.shaper.cburst = q->burst;
+	nq->npq.shaper.overhead = 0;
+
+	if (nss_ppe_configure(nq, &prev_npq) != 0) {
+		nss_qdisc_warning("nss_tbl %x SSDK scheduler configuration failed\n", sch->handle);
+		goto fail;
+	}
+
+	return 0;
+
+fail:
+	if (nq->npq.is_configured) {
+		nss_qdisc_warning("nss_tbl %x SSDK scheduler configuration failed\n", sch->handle);
+		return -EINVAL;
+	}
+
+	/*
+	 * PPE qdisc config failed, try to initialize in NSS.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	if (nss_ppe_fallback_to_nss(nq, opt)) {
+#else
+	if (nss_ppe_fallback_to_nss(nq, opt, extack)) {
+#endif
+	nss_qdisc_warning("nss_tbl %x fallback to nss failed\n", sch->handle);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_tbl_change(struct Qdisc *sch, struct nlattr *opt)
+#else
+static int nss_tbl_change(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+#endif
+{
+	struct nss_tbl_sched_data *q = qdisc_priv(sch);
+	struct nlattr *tb[TCA_NSSTBL_MAX + 1];
+	struct tc_nsstbl_qopt *qopt;
+	struct nss_if_msg nim;
+	struct net_device *dev = qdisc_dev(sch);
+
+	if (!opt) {
+		return -EINVAL;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_tbl_policy, tb, TCA_NSSTBL_MAX, TCA_NSSTBL_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_tbl_policy, tb, TCA_NSSTBL_MAX, TCA_NSSTBL_PARMS, extack);
+#endif
+	if (!qopt) {
+		return -EINVAL;
+	}
+
+	/*
+	 * Set MTU if it wasn't specified explicitely
+	 */
+	if (!qopt->mtu) {
+		qopt->mtu = psched_mtu(dev);
+		nss_qdisc_info("MTU not provided for nss_tbl. Setting it to %s's default %u bytes\n", dev->name, qopt->mtu);
+	}
+
+	/*
+	 * Burst size cannot be less than MTU
+	 */
+	if (qopt->burst < qopt->mtu) {
+		nss_qdisc_error("Burst size: %u is less than the specified MTU: %u\n", qopt->burst, qopt->mtu);
+		return -EINVAL;
+	}
+
+	/*
+	 * Rate can be zero. Therefore we dont do a check on it.
+	 */
+	q->rate = qopt->rate;
+	nss_qdisc_info("Rate = %u", qopt->rate);
+	q->burst = qopt->burst;
+	nss_qdisc_info("Burst = %u", qopt->burst);
+	q->mtu = qopt->mtu;
+	nss_qdisc_info("MTU = %u", qopt->mtu);
+	q->peakrate = qopt->peakrate;
+	nss_qdisc_info("Peak Rate = %u", qopt->peakrate);
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	if (q->nq.mode == NSS_QDISC_MODE_PPE) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+		if (nss_tbl_ppe_change(sch, opt) < 0) {
+#else
+		if (nss_tbl_ppe_change(sch, opt, extack) < 0) {
+#endif
+			nss_qdisc_warning("nss_tbl %x SSDK scheduler config failed\n", sch->handle);
+			return -EINVAL;
+		}
+		return 0;
+	}
+#endif
+
+	nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.tbl_param.lap_cir.rate = q->rate;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.tbl_param.lap_cir.burst = q->burst;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.tbl_param.lap_cir.max_size = q->mtu;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.tbl_param.lap_cir.short_circuit = false;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.tbl_param.lap_pir.rate = q->peakrate;
+
+	/*
+	 * It is important to set these two parameters to be the same as MTU.
+	 * This ensures bursts from CIR dont go above the specified peakrate.
+	 */
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.tbl_param.lap_pir.burst = q->mtu;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.tbl_param.lap_pir.max_size = q->mtu;
+
+	/*
+	 * We can short circuit peakrate limiter if it is not being configured.
+	 */
+	if (q->peakrate) {
+		nim.msg.shaper_configure.config.msg.shaper_node_config.snc.tbl_param.lap_pir.short_circuit = false;
+	} else {
+		nim.msg.shaper_configure.config.msg.shaper_node_config.snc.tbl_param.lap_pir.short_circuit = true;
+	}
+
+	if (nss_qdisc_configure(&q->nq, &nim, NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_CHANGE_PARAM) < 0) {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_tbl_init(struct Qdisc *sch, struct nlattr *opt)
+{
+	struct netlink_ext_ack *extack = NULL;
+#else
+static int nss_tbl_init(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+{
+#endif
+	struct nss_tbl_sched_data *q = qdisc_priv(sch);
+	struct nlattr *tb[TCA_NSSTBL_MAX + 1];
+	struct tc_nsstbl_qopt *qopt;
+
+	if (!opt) {
+		return -EINVAL;
+	}
+
+	q->qdisc = &noop_qdisc;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_tbl_policy, tb, TCA_NSSTBL_MAX, TCA_NSSTBL_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_tbl_policy, tb, TCA_NSSTBL_MAX, TCA_NSSTBL_PARMS, extack);
+#endif
+	if (!qopt) {
+		return -EINVAL;
+	}
+
+	if (nss_qdisc_init(sch, &q->nq, NSS_SHAPER_NODE_TYPE_TBL, 0, qopt->accel_mode, extack) < 0)
+	{
+		return -EINVAL;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	if (nss_tbl_change(sch, opt) < 0) {
+#else
+	if (nss_tbl_change(sch, opt, extack) < 0) {
+#endif
+		nss_qdisc_info("Failed to configure tbl\n");
+		nss_qdisc_destroy(&q->nq);
+		return -EINVAL;
+	}
+
+	/*
+	 * Start the stats polling timer
+	 */
+	nss_qdisc_start_basic_stats_polling(&q->nq);
+
+	return 0;
+}
+
+static int nss_tbl_dump(struct Qdisc *sch, struct sk_buff *skb)
+{
+	struct nss_tbl_sched_data *q = qdisc_priv(sch);
+	struct nlattr *opts = NULL;
+	struct tc_nsstbl_qopt opt;
+
+	opt.rate = q->rate;
+	opt.peakrate = q->peakrate;
+	opt.burst = q->burst;
+	opt.mtu = q->mtu;
+	opt.accel_mode = nss_qdisc_accel_mode_get(&q->nq);
+
+	nss_qdisc_info("Nsstbl dumping");
+
+	opts = nss_qdisc_nla_nest_start(skb, TCA_OPTIONS);
+	if (opts == NULL || nla_put(skb, TCA_NSSTBL_PARMS, sizeof(opt), &opt)) {
+		goto nla_put_failure;
+	}
+
+	return nla_nest_end(skb, opts);
+
+nla_put_failure:
+	nla_nest_cancel(skb, opts);
+	return -EMSGSIZE;
+}
+
+static int nss_tbl_dump_class(struct Qdisc *sch, unsigned long cl,
+			     struct sk_buff *skb, struct tcmsg *tcm)
+{
+	struct nss_tbl_sched_data *q = qdisc_priv(sch);
+	nss_qdisc_info("Nsstbl dumping class");
+
+	tcm->tcm_handle |= TC_H_MIN(1);
+	tcm->tcm_info = q->qdisc->handle;
+
+	return 0;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_tbl_graft(struct Qdisc *sch, unsigned long arg, struct Qdisc *new,
+			struct Qdisc **old)
+#else
+static int nss_tbl_graft(struct Qdisc *sch, unsigned long arg, struct Qdisc *new,
+			struct Qdisc **old, struct netlink_ext_ack *extack)
+#endif
+{
+	struct nss_tbl_sched_data *q = qdisc_priv(sch);
+	struct nss_qdisc *nq_new = (struct nss_qdisc *)qdisc_priv(new);
+	struct nss_if_msg nim_attach;
+	struct nss_if_msg nim_detach;
+
+	if (new == NULL)
+		new = &noop_qdisc;
+
+	sch_tree_lock(sch);
+	*old = q->qdisc;
+	sch_tree_unlock(sch);
+
+	nss_qdisc_info("Grafting old: %px with new: %px\n", *old, new);
+	if (*old != &noop_qdisc) {
+		struct nss_qdisc *nq_old = (struct nss_qdisc *)qdisc_priv(*old);
+		nss_qdisc_info("Detaching old: %px\n", *old);
+		nim_detach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+		if (nss_qdisc_node_detach(&q->nq, nq_old, &nim_detach,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+			return -EINVAL;
+		}
+	}
+
+	if (new != &noop_qdisc) {
+		nss_qdisc_info("Attaching new: %px\n", new);
+		nim_attach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+		nim_attach.msg.shaper_configure.config.msg.shaper_node_config.snc.tbl_attach.child_qos_tag = nq_new->qos_tag;
+		if (nss_qdisc_node_attach(&q->nq, nq_new, &nim_attach,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_ATTACH) < 0) {
+			return -EINVAL;
+		}
+	}
+
+	/*
+	 * Replaced in NSS, now replace in Linux.
+	 */
+	nss_qdisc_replace(sch, new, &q->qdisc);
+
+	nss_qdisc_info("Nsstbl grafted");
+
+	return 0;
+}
+
+static struct Qdisc *nss_tbl_leaf(struct Qdisc *sch, unsigned long arg)
+{
+	struct nss_tbl_sched_data *q = qdisc_priv(sch);
+	nss_qdisc_info("Nsstbl returns leaf");
+	return q->qdisc;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0))
+static unsigned long nss_tbl_get(struct Qdisc *sch, u32 classid)
+{
+	return 1;
+}
+
+static void nss_tbl_put(struct Qdisc *sch, unsigned long arg)
+{
+}
+#else
+static unsigned long nss_tbl_search(struct Qdisc *sch, u32 classid)
+{
+	return 1;
+}
+#endif
+
+static void nss_tbl_walk(struct Qdisc *sch, struct qdisc_walker *walker)
+{
+	nss_qdisc_info("Nsstbl walk called");
+	if (!walker->stop) {
+		if (walker->count >= walker->skip)
+			if (walker->fn(sch, 1, walker) < 0) {
+				walker->stop = 1;
+				return;
+			}
+		walker->count++;
+	}
+}
+
+const struct Qdisc_class_ops nss_tbl_class_ops = {
+	.graft		=	nss_tbl_graft,
+	.leaf		=	nss_tbl_leaf,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0))
+	.get		=	nss_tbl_get,
+	.put		=	nss_tbl_put,
+#else
+	.find       =   nss_tbl_search,
+#endif
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	.tcf_chain	=	nss_qdisc_tcf_chain,
+#else
+	.tcf_block	=	nss_qdisc_tcf_block,
+#endif
+	.bind_tcf	=	nss_qdisc_tcf_bind,
+	.unbind_tcf	=	nss_qdisc_tcf_unbind,
+	.walk		=	nss_tbl_walk,
+	.dump		=	nss_tbl_dump_class,
+};
+
+struct Qdisc_ops nss_tbl_qdisc_ops __read_mostly = {
+	.next		=	NULL,
+	.id		=	"nsstbl",
+	.priv_size	=	sizeof(struct nss_tbl_sched_data),
+	.cl_ops		=	&nss_tbl_class_ops,
+	.enqueue	=	nss_tbl_enqueue,
+	.dequeue	=	nss_tbl_dequeue,
+	.peek		=	nss_tbl_peek,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	.drop		=	nss_tbl_drop,
+#endif
+	.init		=	nss_tbl_init,
+	.reset		=	nss_tbl_reset,
+	.destroy	=	nss_tbl_destroy,
+	.change		=	nss_tbl_change,
+	.dump		=	nss_tbl_dump,
+	.owner		=	THIS_MODULE,
+};
diff --git a/qca-nss-clients/nss_qdisc/nss_tbl.h b/qca-nss-clients/nss_qdisc/nss_tbl.h
new file mode 100644
index 0000000..d9a9c33
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_tbl.h
@@ -0,0 +1,17 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern struct Qdisc_ops nss_tbl_qdisc_ops;
diff --git a/qca-nss-clients/nss_qdisc/nss_wfq.h b/qca-nss-clients/nss_qdisc/nss_wfq.h
new file mode 100644
index 0000000..27b8550
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_wfq.h
@@ -0,0 +1,17 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern struct Qdisc_ops nss_wfq_qdisc_ops;
diff --git a/qca-nss-clients/nss_qdisc/nss_wred.c b/qca-nss-clients/nss_qdisc/nss_wred.c
new file mode 100644
index 0000000..c301f99
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_wred.c
@@ -0,0 +1,488 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2017, 2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_qdisc.h"
+
+#define NSS_WRED_SUPPORT_TRAFFIC_CLASS 6
+#define NSS_WRED_MAX_TRAFFIC_CLASS NSS_WRED_SUPPORT_TRAFFIC_CLASS+1
+
+/*
+ * nsswred traffic class structure
+ */
+struct nss_wred_traffic_class {
+	u32 limit;			/* Queue length */
+	u32 weight_mode_value;		/* Weight mode value */
+	struct tc_red_alg_parameter rap;/* Parameters for RED alg */
+};
+
+/*
+ * nsswred private qdisc structure
+ */
+struct nss_wred_sched_data {
+	struct nss_qdisc nq;	/* Common base class for all nss qdiscs */
+	u32 traffic_classes;	/* # of traffic classs in this wred*/
+	u32 def_traffic_class;	/* Default traffic class if no match */
+	enum tc_nsswred_weight_modes weight_mode;
+				/* Weight mode */
+	struct nss_wred_traffic_class nwtc[NSS_WRED_MAX_TRAFFIC_CLASS];
+				/* Parameters for each traffic class */
+	u8 ecn;			/* Mark ECN or drop pkt */
+	u8 weighted;		/* This is a wred or red */
+	u8 set_default;		/* Flag to set qdisc as default qdisc for enqueue */
+};
+
+/*
+ * nsswred policy structure
+ */
+static struct nla_policy nss_wred_policy[TCA_NSSWRED_MAX + 1] = {
+	[TCA_NSSWRED_PARMS] = { .len = sizeof(struct tc_nsswred_qopt) },
+};
+
+/*
+ * nss_wred_enqueue()
+ *	Enqueue API for nsswred qdisc
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+static int nss_wred_enqueue(struct sk_buff *skb, struct Qdisc *sch)
+#else
+static int nss_wred_enqueue(struct sk_buff *skb, struct Qdisc *sch,
+				struct sk_buff **to_free)
+#endif
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	return nss_qdisc_enqueue(skb, sch);
+#else
+	return nss_qdisc_enqueue(skb, sch, to_free);
+#endif
+}
+
+/*
+ * nss_wred_dequeue()
+ *	Dequeue API for nsswred qdisc
+ */
+static struct sk_buff *nss_wred_dequeue(struct Qdisc *sch)
+{
+	return nss_qdisc_dequeue(sch);
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+/*
+ * nss_wred_drop()
+ *	Drops a packet from HLOS queue.
+ */
+static unsigned int nss_wred_drop(struct Qdisc *sch)
+{
+	nss_qdisc_info("nsswred dropping");
+	return nss_qdisc_drop(sch);
+}
+#endif
+
+/*
+ * nss_wred_reset()
+ *	Reset the nsswred qdisc
+ */
+static void nss_wred_reset(struct Qdisc *sch)
+{
+	nss_qdisc_info("nsswred resetting!");
+	nss_qdisc_reset(sch);
+}
+
+/*
+ * nss_wred_destroy()
+ *	Destroy the nsswred qdisc
+ */
+static void nss_wred_destroy(struct Qdisc *sch)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)qdisc_priv(sch);
+
+	/*
+	 * Stop the polling of basic stats
+	 */
+	nss_qdisc_stop_basic_stats_polling(nq);
+
+	nss_qdisc_destroy(nq);
+	nss_qdisc_info("nsswred destroyed");
+}
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+/*
+ * nss_wred_ppe_change()
+ *	Function call to configure the nssred parameters for ppe qdisc.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_wred_ppe_change(struct Qdisc *sch, struct nlattr *opt)
+#else
+static int nss_wred_ppe_change(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack)
+#endif
+{
+	struct nss_wred_sched_data *q = qdisc_priv(sch);
+	struct nss_qdisc *nq = &q->nq;
+	struct nss_ppe_qdisc prev_npq;
+
+	/*
+	 * Save previous configuration for reset purpose.
+	 */
+	if (nq->npq.is_configured) {
+		prev_npq = nq->npq;
+	}
+
+	/*
+	 * PPE operates in terms of memory blocks, and each block
+	 * is NSS_PPE_MEM_BLOCK_SIZE bytes in size. Therefore we divide the
+	 * input parameters which are in bytes by NSS_PPE_MEM_BLOCK_SIZE to get
+	 * the number of memory blocks to assign.
+	 */
+	nq->npq.q.red_en = true;
+	nq->npq.q.color_en = false;
+	nq->npq.q.qlimit = q->nwtc[0].limit / NSS_PPE_MEM_BLOCK_SIZE;
+	nq->npq.q.min_th[NSS_PPE_COLOR_GREEN] = q->nwtc[0].rap.min / NSS_PPE_MEM_BLOCK_SIZE;
+	nq->npq.q.max_th[NSS_PPE_COLOR_GREEN] = q->nwtc[0].rap.max / NSS_PPE_MEM_BLOCK_SIZE;
+
+	/*
+	 * Currently multicast queue configuration is based on set_default.
+	 * TODO: Enhance multicast queue configuration on the basis of
+	 * multicast parameter specified in tc commands.
+	 */
+	nq->npq.q.mcast_enable = q->set_default;
+
+	if (nss_ppe_configure(&q->nq, &prev_npq) < 0) {
+		nss_qdisc_warning("nss_wred %x configuration failed\n", sch->handle);
+		goto fail;
+	}
+
+	return 0;
+
+fail:
+	if (nq->npq.is_configured) {
+		nss_qdisc_warning("nss_wred %x configuration failed\n", sch->handle);
+		return -EINVAL;
+	}
+
+	/*
+	 * Fallback to nss qdisc if PPE Qdisc configuration failed at init time.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	if (nss_ppe_fallback_to_nss(&q->nq, opt) < 0) {
+#else
+	if (nss_ppe_fallback_to_nss(&q->nq, opt, extack) < 0) {
+#endif
+	nss_qdisc_warning("nss_wred %x fallback to nss failed\n", sch->handle);
+		return -EINVAL;
+	}
+	return 0;
+}
+#endif
+
+/*
+ * nss_wred_change()
+ *	Function call to configure the nsswred parameters
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_wred_change(struct Qdisc *sch, struct nlattr *opt)
+#else
+static int nss_wred_change(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+#endif
+{
+	struct nss_wred_sched_data *q = qdisc_priv(sch);
+	struct nlattr *tb[TCA_NSSWRED_MAX + 1];
+	struct tc_nsswred_qopt *qopt;
+	struct nss_if_msg nim;
+
+	if (!opt) {
+		return -EINVAL;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_wred_policy, tb, TCA_NSSWRED_MAX, TCA_NSSWRED_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_wred_policy, tb, TCA_NSSWRED_MAX, TCA_NSSWRED_PARMS, extack);
+#endif
+	if (!qopt) {
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("nsswred %x traffic_classes:%d def_traffic_class: %d Weight_Mode:%d ECN:%d\n",
+			sch->handle, qopt->traffic_classes, qopt->def_traffic_class, qopt->weight_mode, qopt->ecn);
+
+	if (qopt->traffic_classes) {
+		/*
+		 * This is a wred setup command, do checks again because parameters might not come from tc utility
+		 */
+		if (qopt->traffic_classes > NSS_WRED_SUPPORT_TRAFFIC_CLASS) {
+			nss_qdisc_error("nsswred %x traffic classes should not exceeds %d\n", sch->handle, NSS_WRED_SUPPORT_TRAFFIC_CLASS);
+			return -EINVAL;
+		}
+		if (qopt->def_traffic_class < 1 || qopt->def_traffic_class > qopt->traffic_classes) {
+			nss_qdisc_error("nsswred %x invalid default traffic\n", sch->handle);
+			return -EINVAL;
+		}
+		if (qopt->weight_mode >= TC_NSSWRED_WEIGHT_MODES) {
+			nss_qdisc_error("nsswred %x invalid weight_mode\n", sch->handle);
+			return -EINVAL;
+		}
+		q->traffic_classes = qopt->traffic_classes ;
+		q->def_traffic_class = qopt->def_traffic_class;
+		q->weight_mode = qopt->weight_mode;
+		q->ecn = qopt->ecn;
+		q->weighted = 1;
+	} else {
+		if (qopt->traffic_id) {
+			/*
+			 * This is a wred traffic class command
+			 */
+			if (!q->traffic_classes) {
+				nss_qdisc_error("nsswred %x not setup yet, can't accept traffic class configuration\n", sch->handle);
+				return -EINVAL;
+			}
+			if (!qopt->limit || !qopt->rap.min || !qopt->rap.max || !qopt->weight_mode_value || !qopt->rap.exp_weight_factor) {
+				nss_qdisc_error("nsswred %x Requires RED algorithm parameters and weight_mode_value\n", sch->handle);
+				return -EINVAL;
+			}
+		} else {
+			/*
+			 * This is a red setup command
+			 */
+			if (!qopt->limit || !qopt->rap.exp_weight_factor) {
+				nss_qdisc_error("nsswred %x Requires RED algorithm parameters\n", sch->handle);
+				return -EINVAL;
+			}
+			/*
+			 * If min/max does not specify, calculated it
+			 */
+			if (!qopt->rap.max) {
+				qopt->rap.max = qopt->rap.min ? qopt->rap.min * 3 : qopt->limit / 4;
+			}
+			if (!qopt->rap.min) {
+				qopt->rap.min = qopt->rap.max / 3;
+			}
+			q->ecn = qopt->ecn;
+		}
+		q->nwtc[qopt->traffic_id].limit = qopt->limit;
+		q->nwtc[qopt->traffic_id].weight_mode_value = qopt->weight_mode_value;
+		q->nwtc[qopt->traffic_id].rap.min = qopt->rap.min;
+		q->nwtc[qopt->traffic_id].rap.max = qopt->rap.max;
+		q->nwtc[qopt->traffic_id].rap.probability = qopt->rap.probability;
+		q->nwtc[qopt->traffic_id].rap.exp_weight_factor = qopt->rap.exp_weight_factor;
+	}
+	q->set_default = qopt->set_default;
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	if (q->nq.mode == NSS_QDISC_MODE_PPE) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+		if (nss_wred_ppe_change(sch, opt) < 0) {
+#else
+		if (nss_wred_ppe_change(sch, opt, extack) < 0) {
+#endif
+			nss_qdisc_warning("nss_wred %px params validate and save failed\n", sch);
+			return -EINVAL;
+		}
+		return 0;
+	}
+#endif
+
+	nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.limit = qopt->limit;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.weight_mode = qopt->weight_mode;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.weight_mode_value = qopt->weight_mode_value;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.rap.min = qopt->rap.min;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.rap.max = qopt->rap.max;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.rap.probability = qopt->rap.probability;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.rap.exp_weight_factor = qopt->rap.exp_weight_factor;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.traffic_classes = qopt->traffic_classes;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.ecn = qopt->ecn;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.def_traffic_class = qopt->def_traffic_class;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wred_param.traffic_id = qopt->traffic_id;
+
+	if (nss_qdisc_configure(&q->nq, &nim, NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_CHANGE_PARAM) < 0) {
+		nss_qdisc_error("nsswred %x configuration failed\n", sch->handle);
+		return -EINVAL;
+	}
+
+	if (q->set_default == 0)
+		return 0;
+
+	/*
+	 * Set this qdisc to be the default qdisc for enqueuing packets.
+	 */
+	if (nss_qdisc_set_default(&q->nq) < 0) {
+		nss_qdisc_error("nsswred %x set_default failed\n", sch->handle);
+		return -EINVAL;
+	}
+	nss_qdisc_info("nsswred queue (qos_tag:%u) set as default\n", q->nq.qos_tag);
+
+	return 0;
+}
+
+/*
+ * nss_wred_init()
+ *	Init the nsswred qdisc
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_wred_init(struct Qdisc *sch, struct nlattr *opt)
+{
+	struct netlink_ext_ack *extack = NULL;
+#else
+static int nss_wred_init(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+{
+#endif
+	struct nss_qdisc *nq = qdisc_priv(sch);
+	struct nlattr *tb[TCA_NSSWRED_MAX + 1];
+	struct tc_nsswred_qopt *qopt;
+
+	if (opt == NULL) {
+		return -EINVAL;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_wred_policy, tb, TCA_NSSWRED_MAX, TCA_NSSWRED_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_wred_policy, tb, TCA_NSSWRED_MAX, TCA_NSSWRED_PARMS, extack);
+#endif
+	if (!qopt) {
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("Initializing Wred - type %d\n", NSS_SHAPER_NODE_TYPE_WRED);
+	nss_wred_reset(sch);
+
+	if (nss_qdisc_init(sch, nq, NSS_SHAPER_NODE_TYPE_WRED, 0, qopt->accel_mode, extack) < 0)
+	{
+		return -EINVAL;
+	}
+
+	nss_qdisc_info("NSS wred initialized - handle %x parent %x\n", sch->handle, sch->parent);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	if (nss_wred_change(sch, opt) < 0) {
+#else
+	if (nss_wred_change(sch, opt, extack) < 0) {
+#endif
+		nss_qdisc_destroy(nq);
+		return -EINVAL;
+	}
+
+	/*
+	 * Start the stats polling timer
+	 */
+	nss_qdisc_start_basic_stats_polling(nq);
+
+	return 0;
+}
+
+/*
+ * nss_wred_dump()
+ *	Dump the parameters of nsswred to tc
+ */
+static int nss_wred_dump(struct Qdisc *sch, struct sk_buff *skb)
+{
+	struct nss_wred_sched_data *q;
+	struct nlattr *opts = NULL;
+	struct tc_nsswred_qopt opt;
+	int i;
+	nss_qdisc_info("Nsswred Dumping!");
+
+	q = qdisc_priv(sch);
+	if (q == NULL) {
+		return -1;
+	}
+
+	if (q->weighted) {
+		opt.traffic_classes = q->traffic_classes;
+		opt.def_traffic_class = q->def_traffic_class;
+		opt.ecn = q->ecn;
+		opt.weight_mode = q->weight_mode;
+		for (i = 0 ; i < q->traffic_classes; i++) {
+			opt.tntc[i].limit = q->nwtc[i+1].limit;
+			opt.tntc[i].weight_mode_value = q->nwtc[i+1].weight_mode_value;
+			opt.tntc[i].rap.exp_weight_factor = q->nwtc[i+1].rap.exp_weight_factor;
+			opt.tntc[i].rap.min = q->nwtc[i+1].rap.min;
+			opt.tntc[i].rap.max = q->nwtc[i+1].rap.max;
+			opt.tntc[i].rap.probability = q->nwtc[i+1].rap.probability;
+		}
+	} else {
+		opt.ecn = q->ecn;
+		opt.limit = q->nwtc[0].limit;
+		opt.rap.min = q->nwtc[0].rap.min;
+		opt.rap.max = q->nwtc[0].rap.max;
+		opt.rap.exp_weight_factor = q->nwtc[0].rap.exp_weight_factor;
+		opt.rap.probability = q->nwtc[0].rap.probability;
+	}
+
+	opt.set_default = q->set_default;
+	opt.accel_mode = nss_qdisc_accel_mode_get(&q->nq);
+
+	opts = nss_qdisc_nla_nest_start(skb, TCA_OPTIONS);
+	if (opts == NULL || nla_put(skb, TCA_NSSWRED_PARMS, sizeof(opt), &opt)) {
+		goto nla_put_failure;
+	}
+
+	return nla_nest_end(skb, opts);
+
+nla_put_failure:
+	nla_nest_cancel(skb, opts);
+	return -EMSGSIZE;
+}
+
+/*
+ * nss_wred_peek()
+ *	Peeks the first packet in queue for this qdisc
+ */
+static struct sk_buff *nss_wred_peek(struct Qdisc *sch)
+{
+	nss_qdisc_info("Nsswred Peeking");
+	return nss_qdisc_peek(sch);
+}
+
+/*
+ * Registration structure for nss_red qdisc
+ */
+struct Qdisc_ops nss_red_qdisc_ops __read_mostly = {
+	.id		=	"nssred",
+	.priv_size	=	sizeof(struct nss_wred_sched_data),
+	.enqueue	=	nss_wred_enqueue,
+	.dequeue	=	nss_wred_dequeue,
+	.peek		=	nss_wred_peek,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	.drop		=	nss_wred_drop,
+#endif
+	.init		=	nss_wred_init,
+	.reset		=	nss_wred_reset,
+	.destroy	=	nss_wred_destroy,
+	.change		=	nss_wred_change,
+	.dump		=	nss_wred_dump,
+	.owner		=	THIS_MODULE,
+};
+
+/*
+ * Registration structure for nss_wred qdisc
+ */
+struct Qdisc_ops nss_wred_qdisc_ops __read_mostly = {
+	.id		=	"nsswred",
+	.priv_size	=	sizeof(struct nss_wred_sched_data),
+	.enqueue	=	nss_wred_enqueue,
+	.dequeue	=	nss_wred_dequeue,
+	.peek		=	nss_wred_peek,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	.drop		=	nss_wred_drop,
+#endif
+	.init		=	nss_wred_init,
+	.reset		=	nss_wred_reset,
+	.destroy	=	nss_wred_destroy,
+	.change		=	nss_wred_change,
+	.dump		=	nss_wred_dump,
+	.owner		=	THIS_MODULE,
+};
diff --git a/qca-nss-clients/nss_qdisc/nss_wred.h b/qca-nss-clients/nss_qdisc/nss_wred.h
new file mode 100644
index 0000000..1666400
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_wred.h
@@ -0,0 +1,18 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern struct Qdisc_ops nss_red_qdisc_ops;
+extern struct Qdisc_ops nss_wred_qdisc_ops;
diff --git a/qca-nss-clients/nss_qdisc/nss_wrr.c b/qca-nss-clients/nss_qdisc/nss_wrr.c
new file mode 100644
index 0000000..e6df8f7
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_wrr.c
@@ -0,0 +1,987 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2017, 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_qdisc.h"
+#include "nss_wrr.h"
+
+struct nss_wrr_class_data {
+	struct nss_qdisc nq;		/* Base class used by nss_qdisc */
+	struct Qdisc_class_common cl_common;	/* Common class structure */
+	u32 quantum;				/* Quantum allocation for DRR */
+	struct Qdisc *qdisc;			/* Pointer to child qdisc */
+};
+
+struct nss_wrr_sched_data {
+	struct nss_qdisc nq;		/* Base class used by nss_qdisc */
+	struct nss_wrr_class_data root;	/* Root class */
+	struct Qdisc_class_hash clhash;	/* Class hash */
+};
+
+static struct nla_policy nss_wrr_policy[TCA_NSSWRR_MAX + 1] = {
+	[TCA_NSSWRR_CLASS_PARMS] = { .len = sizeof(struct tc_nsswrr_class_qopt) },
+	[TCA_NSSWRR_QDISC_PARMS] = { .len = sizeof(struct tc_nsswrr_qopt) },
+};
+
+static inline struct nss_wrr_class_data *nss_wrr_find_class(u32 classid,
+							struct Qdisc *sch)
+{
+	struct nss_wrr_sched_data *q = qdisc_priv(sch);
+	struct Qdisc_class_common *clc;
+	clc = qdisc_class_find(&q->clhash, classid);
+	if (clc == NULL) {
+		nss_qdisc_info("Cannot find class with classid %u in qdisc %px hash table %px\n", classid, sch, &q->clhash);
+		return NULL;
+	}
+	return container_of(clc, struct nss_wrr_class_data, cl_common);
+}
+
+static void nss_wrr_destroy_class(struct Qdisc *sch, struct nss_wrr_class_data *cl)
+{
+	struct nss_wrr_sched_data *q = qdisc_priv(sch);
+	struct nss_if_msg nim;
+
+	nss_qdisc_info("Destroying nss_wrr class %px from qdisc %px\n", cl, sch);
+
+	/*
+	 * Note, this function gets called even for NSSWRR and not just for NSSWRR_GROUP.
+	 * If this is wrr qdisc then we should not call nss_qdisc_destroy or stop polling
+	 * for stats. These two actions will happen inside nss_wrr_destroy(), which is called
+	 * only for the root qdisc.
+	 */
+	if (cl == &q->root) {
+		nss_qdisc_info("We do not destroy nss_wrr class %px here since this is "
+				"the qdisc %px\n", cl, sch);
+		return;
+	}
+
+	/*
+	 * We always have to detach our child qdisc in NSS, before destroying it.
+	 */
+	if (cl->qdisc != &noop_qdisc) {
+		struct nss_qdisc *nq_child = qdisc_priv(cl->qdisc);
+		nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag;
+		if (nss_qdisc_node_detach(&cl->nq, nq_child, &nim,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+			nss_qdisc_error("Failed to detach child %x from class %x\n",
+					cl->qdisc->handle, q->nq.qos_tag);
+			return;
+		}
+	}
+
+	/*
+	 * And now we destroy the child.
+	 */
+	 nss_qdisc_put(cl->qdisc);
+
+	/*
+	 * Stop the stats polling timer and free class
+	 */
+	nss_qdisc_stop_basic_stats_polling(&cl->nq);
+
+	/*
+	 * Destroy the shaper in NSS
+	 */
+	nss_qdisc_destroy(&cl->nq);
+
+	/*
+	 * Free class
+	 */
+	kfree(cl);
+}
+
+/*
+ * nss_wrr_class_params_validate_and_save()
+ *	Validates and saves the class configuration parameters.
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_wrr_class_params_validate_and_save(struct Qdisc *sch, struct nlattr **tca,
+					uint32_t *quantum)
+#else
+static int nss_wrr_class_params_validate_and_save(struct Qdisc *sch, struct nlattr **tca,
+					uint32_t *quantum, struct netlink_ext_ack *extack)
+#endif
+{
+	struct nlattr *tb[TCA_NSSWRR_MAX + 1];
+	struct nlattr *opt = tca[TCA_OPTIONS];
+	struct tc_nsswrr_class_qopt *qopt;
+	struct net_device *dev = qdisc_dev(sch);
+	bool is_wrr = (sch->ops == &nss_wrr_qdisc_ops);
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	struct nss_wrr_sched_data *q = qdisc_priv(sch);
+#endif
+
+	nss_qdisc_trace("validating parameters for nsswrr class of qdisc:%x\n", sch->handle);
+
+	if (!opt) {
+		return -EINVAL;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_wrr_policy, tb, TCA_NSSWRR_MAX, TCA_NSSWRR_CLASS_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_wrr_policy, tb, TCA_NSSWRR_MAX, TCA_NSSWRR_CLASS_PARMS, extack);
+#endif
+	if (!qopt) {
+		return -EINVAL;
+	}
+
+	sch_tree_lock(sch);
+
+	/*
+	 * If the value of quantum is not provided default it based on the type
+	 * of operation (i.e. wrr or wfq)
+	 */
+	*quantum = qopt->quantum;
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	if (is_wrr) {
+		if ((qopt->quantum >= NSS_PPE_DRR_WEIGHT_MAX)) {
+			nss_qdisc_warning("quantum %u of nss_wrr class of qdisc %x should be a less than 1024\n",
+					qopt->quantum, sch->handle);
+			sch_tree_unlock(sch);
+			return -EINVAL;
+		}
+	} else if (q->nq.mode == NSS_QDISC_MODE_PPE) {
+		if ((qopt->quantum % NSS_PPE_DRR_WEIGHT_MAX) != 0) {
+			nss_qdisc_warning("nss_wfq (accel_mode %d) requires quantum to be a multiple of 1024\n",
+					nss_qdisc_accel_mode_get(&q->nq));
+			sch_tree_unlock(sch);
+			return -EINVAL;
+		}
+
+		if (qopt->quantum > (NSS_PPE_DRR_WEIGHT_MAX * NSS_PPE_DRR_WEIGHT_MAX)) {
+			nss_qdisc_warning("nss_wfq (accel_mode %d) requires quantum not exceeding 1024*1024\n",
+					nss_qdisc_accel_mode_get(&q->nq));
+			sch_tree_unlock(sch);
+			return -EINVAL;
+		}
+	}
+#endif
+
+	if (!*quantum) {
+		if (is_wrr) {
+			*quantum = 1;
+			nss_qdisc_info("Quantum value not provided for nss_wrr class on interface %s. "
+					"Setting quantum to %up\n", dev->name, *quantum);
+		} else {
+			*quantum = psched_mtu(dev);
+			nss_qdisc_info("Quantum value not provided for nss_wfq class on interface %s. "
+					"Setting quantum to %ubytes\n", dev->name, *quantum);
+		}
+	}
+
+	sch_tree_unlock(sch);
+
+	return 0;
+}
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+/*
+ * nss_wrr_ppe_change_class()
+ *	Configures a class in ppe qdisc
+ */
+static int nss_wrr_ppe_change_class(struct Qdisc *sch, struct nss_wrr_class_data *cl, uint32_t quantum)
+{
+	struct nss_ppe_qdisc prev_npq;
+	bool is_wrr = (sch->ops == &nss_wrr_qdisc_ops);
+
+	/*
+	 * Save the previous scheduler configuration
+	 * for handling failure conditions.
+	 */
+	prev_npq = cl->nq.npq;
+
+	/*
+	 * Quantum is specified in bytes for WFQ while it is in packets for WRR.
+	 */
+	if (is_wrr) {
+		cl->nq.npq.scheduler.drr_weight = nss_ppe_drr_weight_get(quantum, NSS_PPE_DRR_UNIT_PACKET);
+		cl->nq.npq.scheduler.drr_unit = NSS_PPE_DRR_UNIT_PACKET;
+	} else {
+		cl->nq.npq.scheduler.drr_weight = nss_ppe_drr_weight_get(quantum, NSS_PPE_DRR_UNIT_BYTE);
+		cl->nq.npq.scheduler.drr_unit = NSS_PPE_DRR_UNIT_BYTE;
+	}
+
+	/*
+	 * Change the configuration in SSDK
+	 */
+	if (nss_ppe_configure(&cl->nq, &prev_npq) != 0)  {
+		nss_qdisc_warning("nss_wrr %x SSDK scheduler configuration failed\n", sch->handle);
+		return -EINVAL;
+	}
+
+	cl->quantum = quantum;
+	return 0;
+}
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_wrr_change_class(struct Qdisc *sch, u32 classid, u32 parentid,
+		  struct nlattr **tca, unsigned long *arg)
+{
+	struct netlink_ext_ack *extack = NULL;
+#else
+static int nss_wrr_change_class(struct Qdisc *sch, u32 classid, u32 parentid,
+		  struct nlattr **tca, unsigned long *arg, struct netlink_ext_ack *extack)
+{
+#endif
+	struct nss_wrr_sched_data *q = qdisc_priv(sch);
+	struct nss_wrr_class_data *cl = (struct nss_wrr_class_data *)*arg;
+	struct nss_if_msg nim_config;
+	bool new_init = false;
+	uint32_t quantum;
+	unsigned int accel_mode = nss_qdisc_accel_mode_get(&q->nq);
+
+	nss_qdisc_info("Changing nss_wrr class %u\n", classid);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	if (nss_wrr_class_params_validate_and_save(sch, tca, &quantum) < 0) {
+#else
+	if (nss_wrr_class_params_validate_and_save(sch, tca, &quantum, extack) < 0) {
+#endif
+		nss_qdisc_warning("validation of configuration parameters for wrr class %x failed\n",
+					sch->handle);
+		return -EINVAL;
+	}
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+	if (cl && (cl->nq.mode == NSS_QDISC_MODE_PPE)) {
+		if (nss_wrr_ppe_change_class(sch, cl, quantum) < 0) {
+			nss_qdisc_warning("nss_htb %x SSDK scheduler configuration failed\n", sch->handle);
+			return -EINVAL;
+		}
+		return 0;
+	}
+#endif
+
+	/*
+	 * If class with a given classid is not found, we allocate a new one
+	 */
+	if (!cl) {
+
+		struct nss_if_msg nim_attach;
+
+		/*
+		 * The class does not already exist, we are newly initializing it.
+		 */
+		new_init = true;
+
+		nss_qdisc_info("Nss_wrr class %u not found. Allocating a new class.\n", classid);
+		cl = kzalloc(sizeof(struct nss_wrr_class_data), GFP_KERNEL);
+
+		if (!cl) {
+			nss_qdisc_error("Class allocation failed for classid %u\n", classid);
+			return -EINVAL;
+		}
+
+		nss_qdisc_info("NSS_wrr class %u allocated %px\n", classid, cl);
+		cl->cl_common.classid = classid;
+
+		/*
+		 * We make the child qdisc a noop qdisc, and
+		 * set reference count to 1. This is important,
+		 * reference count should not be 0.
+		 */
+		cl->qdisc = &noop_qdisc;
+		nss_qdisc_atomic_set(&cl->nq);
+		*arg = (unsigned long)cl;
+
+		nss_qdisc_info("Adding classid %u to qdisc %px hash queue %px\n", classid, sch, &q->clhash);
+
+		/*
+		 * This is where a class gets initialized. Classes do not have a init function
+		 * that is registered to Linux. Therefore we initialize the NSSWRR_GROUP shaper
+		 * here.
+		 */
+		cl->nq.parent = &q->nq;
+		if (nss_qdisc_init(sch, &cl->nq, NSS_SHAPER_NODE_TYPE_WRR_GROUP, classid, accel_mode, extack) < 0)
+		{
+			nss_qdisc_error("Nss init for class %u failed\n", classid);
+			return -EINVAL;
+		}
+
+#if defined(NSS_QDISC_PPE_SUPPORT)
+		if (cl->nq.mode == NSS_QDISC_MODE_PPE) {
+			if (nss_wrr_ppe_change_class(sch, cl, quantum) < 0) {
+				nss_qdisc_warning("nss_htb %x SSDK scheduler configuration failed\n", sch->handle);
+				nss_qdisc_destroy(&cl->nq);
+				goto failure;
+			}
+		}
+#endif
+		/*
+		 * Set qos_tag of parent to which the class needs to be attached to.
+		 * Set the child to be this class.
+		 * Send node_attach command down to the NSS.
+		 */
+		nim_attach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+
+		if (cl->nq.mode == NSS_QDISC_MODE_NSS) {
+			nim_attach.msg.shaper_configure.config.msg.shaper_node_config.snc.wrr_attach.child_qos_tag = cl->nq.qos_tag;
+		}
+
+		if (nss_qdisc_node_attach(&q->nq, &cl->nq, &nim_attach,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_ATTACH) < 0) {
+			nss_qdisc_error("Nss attach for class %u failed\n", classid);
+			nss_qdisc_destroy(&cl->nq);
+			goto failure;
+		}
+
+		/*
+		 * Add class to hash tree once it is attached in the NSS
+		 */
+		sch_tree_lock(sch);
+		qdisc_class_hash_insert(&q->clhash, &cl->cl_common);
+		sch_tree_unlock(sch);
+
+		/*
+		 * Hash grow should not come within the tree lock
+		 */
+		qdisc_class_hash_grow(sch, &q->clhash);
+
+		/*
+		 * Start the stats polling timer
+		 */
+		nss_qdisc_start_basic_stats_polling(&cl->nq);
+
+		nss_qdisc_info("Class %u successfully allocated\n", classid);
+	}
+
+	cl->quantum = quantum;
+
+	/*
+	 * Fill information that needs to be sent down to the NSS for configuring the
+	 * wrr class.
+	 */
+	if (cl->nq.mode == NSS_QDISC_MODE_NSS) {
+		nim_config.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag;
+		nim_config.msg.shaper_configure.config.msg.shaper_node_config.snc.wrr_group_param.quantum = cl->quantum;
+
+		nss_qdisc_info("Quantum = %u\n", cl->quantum);
+
+		/*
+		 * Send configure command to the NSS
+		 */
+		if (nss_qdisc_configure(&cl->nq, &nim_config,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_CHANGE_PARAM) < 0) {
+			nss_qdisc_error("Failed to configure class %x\n", classid);
+
+			/*
+			 * We dont have to destroy the class if this was just a
+			 * change command.
+			 */
+			if (!new_init) {
+				return -EINVAL;
+			}
+
+			/*
+			 * Else, we have failed in the NSS and we will have to
+			 * destroy the class
+			 */
+			nss_qdisc_destroy(&cl->nq);
+			goto failure;
+		}
+	}
+
+	nss_qdisc_info("Class %x changed successfully\n", classid);
+	return 0;
+
+failure:
+	if (cl) {
+		kfree(cl);
+	}
+	return -EINVAL;
+}
+
+static int nss_wrr_delete_class(struct Qdisc *sch, unsigned long arg)
+{
+	struct nss_wrr_sched_data *q = qdisc_priv(sch);
+	struct nss_wrr_class_data *cl = (struct nss_wrr_class_data *)arg;
+	struct nss_if_msg nim;
+	int refcnt;
+
+	/*
+	 * Since all classes are leaf nodes in our case, we dont have to make
+	 * that check.
+	 */
+	if (cl == &q->root)
+		return -EBUSY;
+
+	/*
+	 * The message to NSS should be sent to the parent of this class
+	 */
+	nss_qdisc_info("Detaching nss_wrr class: %px\n", cl);
+	nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+	nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wrr_detach.child_qos_tag = cl->nq.qos_tag;
+	if (nss_qdisc_node_detach(&q->nq, &cl->nq, &nim,
+			NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+		return -EINVAL;
+	}
+
+	sch_tree_lock(sch);
+	qdisc_reset(cl->qdisc);
+	qdisc_class_hash_remove(&q->clhash, &cl->cl_common);
+
+	refcnt = nss_qdisc_atomic_sub_return(&cl->nq);
+
+	sch_tree_unlock(sch);
+	if (!refcnt) {
+		nss_qdisc_error("Reference count should not be zero for class %px\n", cl);
+	}
+
+	return 0;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_wrr_graft_class(struct Qdisc *sch, unsigned long arg, struct Qdisc *new,
+								 struct Qdisc **old)
+#else
+static int nss_wrr_graft_class(struct Qdisc *sch, unsigned long arg, struct Qdisc *new,
+								 struct Qdisc **old, struct netlink_ext_ack *extack)
+#endif
+{
+	struct nss_wrr_sched_data *q = qdisc_priv(sch);
+	struct nss_wrr_class_data *cl = (struct nss_wrr_class_data *)arg;
+	struct nss_if_msg nim_detach;
+	struct nss_if_msg nim_attach;
+	struct nss_qdisc *nq_new = qdisc_priv(new);
+
+	nss_qdisc_info("Grafting class %px\n", sch);
+
+	if (cl == &q->root) {
+		nss_qdisc_error("Can't graft root class %px\n", cl);
+		return -EINVAL;
+	}
+
+	if (new == NULL)
+		new = &noop_qdisc;
+
+	sch_tree_lock(sch);
+	*old = cl->qdisc;
+	sch_tree_unlock(sch);
+
+	/*
+	 * Since we initially attached a noop qdisc as child (in Linux),
+	 * we do not perform a detach in the NSS if its a noop qdisc.
+	 */
+	nss_qdisc_info("Grafting old: %px with new: %px\n", *old, new);
+	if (*old != &noop_qdisc) {
+		struct nss_qdisc *nq_child = qdisc_priv(*old);
+		nss_qdisc_info("Detaching old: %px\n", *old);
+		nim_detach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag;
+		if (nss_qdisc_node_detach(&cl->nq, nq_child, &nim_detach,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+			return -EINVAL;
+		}
+	}
+
+	/*
+	 * If the new qdisc is a noop qdisc, we do not send down an attach command
+	 * to the NSS.
+	 */
+	if (new != &noop_qdisc) {
+		nss_qdisc_info("Attaching new: %px\n", new);
+		nim_attach.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = cl->nq.qos_tag;
+		nim_attach.msg.shaper_configure.config.msg.shaper_node_config.snc.wrr_group_attach.child_qos_tag = nq_new->qos_tag;
+		if (nss_qdisc_node_attach(&cl->nq, nq_new, &nim_attach,
+				NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_ATTACH) < 0) {
+			return -EINVAL;
+		}
+	}
+
+	/*
+	 * Replaced in NSS, now replace in Linux.
+	 */
+	nss_qdisc_replace(sch, new, &cl->qdisc);
+
+	nss_qdisc_info("Nsswrr grafted");
+
+	return 0;
+}
+
+static struct Qdisc *nss_wrr_leaf_class(struct Qdisc *sch, unsigned long arg)
+{
+	struct nss_wrr_class_data *cl = (struct nss_wrr_class_data *)arg;
+	nss_qdisc_info("nss_wrr class leaf %px\n", cl);
+
+	/*
+	 * Since all nss_wrr groups are leaf nodes, we can always
+	 * return the attached qdisc.
+	 */
+	return cl->qdisc;
+}
+
+static void nss_wrr_qlen_notify(struct Qdisc *sch, unsigned long arg)
+{
+	nss_qdisc_info("nss_wrr qlen notify %px\n", sch);
+	/*
+	 * Gets called when qlen of child changes (Useful for deactivating)
+	 * Not useful for us here.
+	 */
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0))
+static unsigned long nss_wrr_get_class(struct Qdisc *sch, u32 classid)
+{
+	struct nss_wrr_class_data *cl = nss_wrr_find_class(classid, sch);
+
+	nss_qdisc_info("Get nss_wrr class %px - class match = %px\n", sch, cl);
+
+	if (cl != NULL) {
+		atomic_add(1, &cl->nq.refcnt);
+	}
+
+	return (unsigned long)cl;
+}
+
+static void nss_wrr_put_class(struct Qdisc *sch, unsigned long arg)
+{
+	struct nss_wrr_class_data *cl = (struct nss_wrr_class_data *)arg;
+	nss_qdisc_info("nss_wrr put class for %px\n", cl);
+
+	/*
+	 * We are safe to destroy the qdisc if the reference count
+	 * goes down to 0.
+	 */
+	if (nss_qdisc_atomic_sub_return(&cl->nq) == 0) {
+		nss_wrr_destroy_class(sch, cl);
+	}
+}
+#else
+static unsigned long nss_wrr_search_class(struct Qdisc *sch, u32 classid)
+{
+	struct nss_wrr_class_data *cl = nss_wrr_find_class(classid, sch);
+
+	nss_qdisc_info("Get nss_wrr class %px - class match = %px\n", sch, cl);
+
+	if (cl != NULL) {
+		atomic_add(1, &cl->nq.refcnt.refs);
+	}
+
+	return (unsigned long)cl;
+}
+#endif
+
+static int nss_wrr_dump_class(struct Qdisc *sch, unsigned long arg, struct sk_buff *skb,
+		struct tcmsg *tcm)
+{
+	struct nss_wrr_class_data *cl = (struct nss_wrr_class_data *)arg;
+	struct nlattr *opts;
+	struct tc_nsswrr_class_qopt qopt;
+
+	nss_qdisc_info("Dumping class %px of Qdisc %x\n", cl, sch->handle);
+
+	qopt.quantum = cl->quantum;
+
+	/*
+	 * All bf group nodes are root nodes. i.e. they dont
+	 * have any mode bf groups attached beneath them.
+	 */
+	tcm->tcm_parent = TC_H_ROOT;
+	tcm->tcm_handle = cl->cl_common.classid;
+	tcm->tcm_info = cl->qdisc->handle;
+
+	opts = nss_qdisc_nla_nest_start(skb, TCA_OPTIONS);
+	if (opts == NULL || nla_put(skb, TCA_NSSWRR_CLASS_PARMS, sizeof(qopt), &qopt)) {
+		goto nla_put_failure;
+	}
+	return nla_nest_end(skb, opts);
+
+nla_put_failure:
+	nla_nest_cancel(skb, opts);
+	return -EMSGSIZE;
+}
+
+static int nss_wrr_dump_class_stats(struct Qdisc *sch, unsigned long arg, struct gnet_dump *d)
+{
+	struct nss_qdisc *nq = (struct nss_qdisc *)arg;
+
+	if (nss_qdisc_gnet_stats_copy_basic(sch, d, &nq->bstats) < 0 ||
+			nss_qdisc_gnet_stats_copy_queue(d, &nq->qstats) < 0) {
+		return -1;
+	}
+
+	return 0;
+}
+
+static void nss_wrr_walk(struct Qdisc *sch, struct qdisc_walker *arg)
+{
+	struct nss_wrr_sched_data *q = qdisc_priv(sch);
+	struct hlist_node *n __maybe_unused;
+	struct nss_wrr_class_data *cl;
+	unsigned int i;
+
+	nss_qdisc_info("In nss_wrr walk %px\n", sch);
+	if (arg->stop)
+		return;
+
+	for (i = 0; i < q->clhash.hashsize; i++) {
+		nss_qdisc_hlist_for_each_entry(cl, n, &q->clhash.hash[i],
+				cl_common.hnode) {
+			if (arg->count < arg->skip) {
+				arg->count++;
+				continue;
+			}
+			if (arg->fn(sch, (unsigned long)cl, arg) < 0) {
+				arg->stop = 1;
+				return;
+			}
+			arg->count++;
+		}
+	}
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_wrr_init_qdisc(struct Qdisc *sch, struct nlattr *opt)
+{
+	struct netlink_ext_ack *extack = NULL;
+#else
+static int nss_wrr_init_qdisc(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+{
+#endif
+	struct nss_wrr_sched_data *q = qdisc_priv(sch);
+	struct nlattr *tb[TCA_NSSWRR_MAX + 1];
+	int err;
+	struct nss_if_msg nim;
+	struct tc_nsswrr_qopt *qopt;
+
+	nss_qdisc_info("Init nss_wrr qdisc %px\n", sch);
+
+	err = qdisc_class_hash_init(&q->clhash);
+	if (err < 0) {
+		return err;
+	}
+
+	q->root.cl_common.classid = sch->handle;
+	q->root.qdisc = &noop_qdisc;
+
+	qdisc_class_hash_insert(&q->clhash, &q->root.cl_common);
+	qdisc_class_hash_grow(sch, &q->clhash);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_wrr_policy, tb, TCA_NSSWRR_MAX, TCA_NSSWRR_QDISC_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_wrr_policy, tb, TCA_NSSWRR_MAX, TCA_NSSWRR_QDISC_PARMS, extack);
+#endif
+	if (!qopt) {
+		nss_qdisc_warning("Failed to parse input");
+		return -EINVAL;
+	}
+
+	/*
+	 * Initialize the NSSWRR shaper in NSS
+	 */
+	if (nss_qdisc_init(sch, &q->nq, NSS_SHAPER_NODE_TYPE_WRR, 0, qopt->accel_mode, extack) < 0) {
+		nss_qdisc_warning("Failed init nss_wrr qdisc");
+		return -EINVAL;
+	}
+
+	if (q->nq.mode == NSS_QDISC_MODE_NSS) {
+		/*
+		 * Configure the qdisc to operate in one of the two modes
+		 */
+		nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+		if (strncmp(sch->ops->id, "nsswrr", 6) == 0) {
+			nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wrr_param.operation_mode = NSS_SHAPER_WRR_MODE_ROUND_ROBIN;
+		} else if (strncmp(sch->ops->id, "nsswfq", 6) == 0) {
+			nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wrr_param.operation_mode = NSS_SHAPER_WRR_MODE_FAIR_QUEUEING;
+		} else {
+			nss_qdisc_error("Unknow qdisc association");
+			nss_qdisc_destroy(&q->nq);
+			return -EINVAL;
+		}
+
+		/*
+		 * Send configure command to the NSS
+		 */
+		if (nss_qdisc_configure(&q->nq, &nim, NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_CHANGE_PARAM) < 0) {
+			nss_qdisc_warning("Failed to configure nss_wrr qdisc %x\n", q->nq.qos_tag);
+			nss_qdisc_destroy(&q->nq);
+			return -EINVAL;
+		}
+	}
+
+	nss_qdisc_info("Nsswrr initialized - handle %x parent %x\n", sch->handle, sch->parent);
+
+	/*
+	 * Start the stats polling timer
+	 */
+	nss_qdisc_start_basic_stats_polling(&q->nq);
+
+	return 0;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+static int nss_wrr_change_qdisc(struct Qdisc *sch, struct nlattr *opt)
+#else
+static int nss_wrr_change_qdisc(struct Qdisc *sch, struct nlattr *opt,
+				struct netlink_ext_ack *extack)
+#endif
+{
+	struct nlattr *tb[TCA_NSSWRR_MAX + 1];
+	struct nss_wrr_sched_data *q;
+	struct tc_nsswrr_qopt *qopt;
+
+	q = qdisc_priv(sch);
+
+	if (opt == NULL) {
+		return -EINVAL;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+	qopt = nss_qdisc_qopt_get(opt, nss_wrr_policy, tb, TCA_NSSWRR_MAX, TCA_NSSWRR_QDISC_PARMS);
+#else
+	qopt = nss_qdisc_qopt_get(opt, nss_wrr_policy, tb, TCA_NSSWRR_MAX, TCA_NSSWRR_QDISC_PARMS, extack);
+#endif
+	if (!qopt) {
+		return -EINVAL;
+	}
+
+	/*
+	 * WRR has no qdisc parameters that can be changed.
+	 */
+
+	return 0;
+}
+
+static void nss_wrr_reset_class(struct nss_wrr_class_data *cl)
+{
+	nss_qdisc_reset(cl->qdisc);
+	nss_qdisc_info("Nsswrr class resetted %px\n", cl->qdisc);
+}
+
+static void nss_wrr_reset_qdisc(struct Qdisc *sch)
+{
+	struct nss_wrr_sched_data *q = qdisc_priv(sch);
+	struct nss_wrr_class_data *cl;
+	struct hlist_node *n __maybe_unused;
+	unsigned int i;
+
+	for (i = 0; i < q->clhash.hashsize; i++) {
+		nss_qdisc_hlist_for_each_entry(cl, n, &q->clhash.hash[i], cl_common.hnode)
+		nss_wrr_reset_class(cl);
+	}
+
+	nss_qdisc_reset(sch);
+	nss_qdisc_info("Nsswrr qdisc resetted %px\n", sch);
+}
+
+static void nss_wrr_destroy_qdisc(struct Qdisc *sch)
+{
+	struct nss_wrr_sched_data *q = qdisc_priv(sch);
+	struct hlist_node *n __maybe_unused;
+	struct hlist_node *next;
+	struct nss_wrr_class_data *cl;
+	struct nss_if_msg nim;
+	unsigned int i;
+
+	/*
+	 * Destroy all the classes before the root qdisc is destroyed.
+	 */
+	for (i = 0; i < q->clhash.hashsize; i++) {
+		nss_qdisc_hlist_for_each_entry_safe(cl, n, next, &q->clhash.hash[i], cl_common.hnode) {
+
+			/*
+			 * If this is the root class, we dont have to destroy it. This will be taken
+			 * care of by the nss_wrr_destroy() function.
+			 */
+			if (cl == &q->root) {
+				nss_qdisc_info("We do not detach or destroy nss_wrr class %px here since this is "
+						"the qdisc %px\n", cl, sch);
+				continue;
+			}
+
+			/*
+			 * Reduce refcnt by 1 before destroying. This is to
+			 * ensure that polling of stat stops properly.
+			 */
+			 nss_qdisc_atomic_sub(&cl->nq);
+
+			/*
+			 * Detach class before destroying it. We dont check for noop qdisc here
+			 * since we do not attach anu such at init.
+			 */
+			nim.msg.shaper_configure.config.msg.shaper_node_config.qos_tag = q->nq.qos_tag;
+			nim.msg.shaper_configure.config.msg.shaper_node_config.snc.wrr_detach.child_qos_tag = cl->nq.qos_tag;
+			if (nss_qdisc_node_detach(&q->nq, &cl->nq, &nim, NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH) < 0) {
+				nss_qdisc_error("Node detach failed for qdisc %x class %x\n",
+							cl->nq.qos_tag, q->nq.qos_tag);
+				return;
+			}
+
+			/*
+			 * Now we can destroy the class.
+			 */
+			nss_wrr_destroy_class(sch, cl);
+		}
+	}
+	qdisc_class_hash_destroy(&q->clhash);
+
+	/*
+	 * Stop the polling of basic stats
+	 */
+	nss_qdisc_stop_basic_stats_polling(&q->nq);
+
+	/*
+	 * Now we can go ahead and destroy the qdisc.
+	 * Note: We dont have to detach ourself from our parent because this
+	 *	 will be taken care of by the graft call.
+	 */
+	nss_qdisc_destroy(&q->nq);
+	nss_qdisc_info("Nsswrr destroyed %px\n", sch);
+}
+
+static int nss_wrr_dump_qdisc(struct Qdisc *sch, struct sk_buff *skb)
+{
+	struct nss_wrr_sched_data *q;
+	struct nlattr *opts = NULL;
+	struct tc_nsswrr_qopt opt;
+
+	nss_qdisc_info("Nsswrr Dumping!");
+
+	q = qdisc_priv(sch);
+	if (q == NULL) {
+		return -1;
+	}
+
+	opt.accel_mode = nss_qdisc_accel_mode_get(&q->nq);
+
+	opts = nss_qdisc_nla_nest_start(skb, TCA_OPTIONS);
+	if (opts == NULL) {
+		goto nla_put_failure;
+	}
+	if (nla_put(skb, TCA_NSSWRR_QDISC_PARMS, sizeof(opt), &opt)) {
+		goto nla_put_failure;
+	}
+
+	return nla_nest_end(skb, opts);
+
+nla_put_failure:
+	nla_nest_cancel(skb, opts);
+	return -EMSGSIZE;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+static int nss_wrr_enqueue(struct sk_buff *skb, struct Qdisc *sch)
+#else
+static int nss_wrr_enqueue(struct sk_buff *skb, struct Qdisc *sch,
+				struct sk_buff **to_free)
+#endif
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	return nss_qdisc_enqueue(skb, sch);
+#else
+	return nss_qdisc_enqueue(skb, sch, to_free);
+#endif
+}
+
+static struct sk_buff *nss_wrr_dequeue(struct Qdisc *sch)
+{
+	return nss_qdisc_dequeue(sch);
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+static unsigned int nss_wrr_drop(struct Qdisc *sch)
+{
+	nss_qdisc_info("Nsswrr drop\n");
+	return nss_qdisc_drop(sch);
+}
+#endif
+
+const struct Qdisc_class_ops nss_wrr_class_ops = {
+	.change		= nss_wrr_change_class,
+	.delete		= nss_wrr_delete_class,
+	.graft		= nss_wrr_graft_class,
+	.leaf		= nss_wrr_leaf_class,
+	.qlen_notify	= nss_wrr_qlen_notify,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0))
+	.get		= nss_wrr_get_class,
+	.put		= nss_wrr_put_class,
+#else
+	.find       = nss_wrr_search_class,
+#endif
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	.tcf_chain	= nss_qdisc_tcf_chain,
+#else
+	.tcf_block	= nss_qdisc_tcf_block,
+#endif
+	.bind_tcf	= nss_qdisc_tcf_bind,
+	.unbind_tcf	= nss_qdisc_tcf_unbind,
+	.dump		= nss_wrr_dump_class,
+	.dump_stats	= nss_wrr_dump_class_stats,
+	.walk		= nss_wrr_walk
+};
+
+struct Qdisc_ops nss_wrr_qdisc_ops __read_mostly = {
+	.id		= "nsswrr",
+	.init		= nss_wrr_init_qdisc,
+	.change		= nss_wrr_change_qdisc,
+	.reset		= nss_wrr_reset_qdisc,
+	.destroy	= nss_wrr_destroy_qdisc,
+	.dump		= nss_wrr_dump_qdisc,
+	.enqueue	= nss_wrr_enqueue,
+	.dequeue	= nss_wrr_dequeue,
+	.peek		= qdisc_peek_dequeued,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	.drop		= nss_wrr_drop,
+#endif
+	.cl_ops		= &nss_wrr_class_ops,
+	.priv_size	= sizeof(struct nss_wrr_sched_data),
+	.owner		= THIS_MODULE
+};
+
+const struct Qdisc_class_ops nss_wfq_class_ops = {
+	.change		= nss_wrr_change_class,
+	.delete		= nss_wrr_delete_class,
+	.graft		= nss_wrr_graft_class,
+	.leaf		= nss_wrr_leaf_class,
+	.qlen_notify	= nss_wrr_qlen_notify,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0))
+	.get		= nss_wrr_get_class,
+	.put		= nss_wrr_put_class,
+#else
+	.find       = nss_wrr_search_class,
+#endif
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	.tcf_chain	= nss_qdisc_tcf_chain,
+#else
+	.tcf_block	= nss_qdisc_tcf_block,
+#endif
+	.bind_tcf	= nss_qdisc_tcf_bind,
+	.unbind_tcf	= nss_qdisc_tcf_unbind,
+	.dump		= nss_wrr_dump_class,
+	.dump_stats	= nss_wrr_dump_class_stats,
+	.walk		= nss_wrr_walk
+};
+
+struct Qdisc_ops nss_wfq_qdisc_ops __read_mostly = {
+	.id		= "nsswfq",
+	.init		= nss_wrr_init_qdisc,
+	.change		= nss_wrr_change_qdisc,
+	.reset		= nss_wrr_reset_qdisc,
+	.destroy	= nss_wrr_destroy_qdisc,
+	.dump		= nss_wrr_dump_qdisc,
+	.enqueue	= nss_wrr_enqueue,
+	.dequeue	= nss_wrr_dequeue,
+	.peek		= qdisc_peek_dequeued,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+	.drop		= nss_wrr_drop,
+#endif
+	.cl_ops		= &nss_wrr_class_ops,
+	.priv_size	= sizeof(struct nss_wrr_sched_data),
+	.owner		= THIS_MODULE
+};
diff --git a/qca-nss-clients/nss_qdisc/nss_wrr.h b/qca-nss-clients/nss_qdisc/nss_wrr.h
new file mode 100644
index 0000000..7ef5d93
--- /dev/null
+++ b/qca-nss-clients/nss_qdisc/nss_wrr.h
@@ -0,0 +1,17 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern struct Qdisc_ops nss_wrr_qdisc_ops;
diff --git a/qca-nss-clients/openvpn/Makefile b/qca-nss-clients/openvpn/Makefile
new file mode 100644
index 0000000..122085d
--- /dev/null
+++ b/qca-nss-clients/openvpn/Makefile
@@ -0,0 +1,4 @@
+# Makefile for the ovpnmgr client
+
+obj-y += src/
+obj-y += plugins/
diff --git a/qca-nss-clients/openvpn/plugins/Makefile b/qca-nss-clients/openvpn/plugins/Makefile
new file mode 100644
index 0000000..ae03882
--- /dev/null
+++ b/qca-nss-clients/openvpn/plugins/Makefile
@@ -0,0 +1,13 @@
+
+# Makefile for the ovpn plugins
+
+ccflags-y := $(NSS_CCFLAGS) -I$(obj) -I$(obj)/../../exports -I$(obj)/include -I$(obj)/../src -I$(STAGING_DIR)/usr/include/qca-nss-ecm
+
+ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)"
+ccflags-y += -DNSS_OVPNMGR_DEBUG_LEVEL=0
+ccflags-y += -DNSS_OVPN_LINK_DEBUG_LEVEL=0
+ccflags-y += -Wall -Werror
+
+obj-m += qca-nss-ovpn-link.o
+qca-nss-ovpn-link-objs := nss_ovpn_link.o
+obj ?= .
diff --git a/qca-nss-clients/openvpn/plugins/nss_ovpn_link.c b/qca-nss-clients/openvpn/plugins/nss_ovpn_link.c
new file mode 100644
index 0000000..e4495b3
--- /dev/null
+++ b/qca-nss-clients/openvpn/plugins/nss_ovpn_link.c
@@ -0,0 +1,176 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ovpn_link.c
+ *	Interface between NSS OVPN manager and ECM.
+ */
+#include <linux/module.h>
+#include <linux/ip.h>
+#include <net/ip.h>
+#include <linux/ipv6.h>
+#include <linux/ipv6.h>
+#include <linux/netdevice.h>
+#include <linux/crypto.h>
+
+#include <nss_api_if.h>
+#include <nss_qvpn.h>
+#include <nss_ovpnmgr.h>
+#include <ecm_interface_ovpn.h>
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_ovpn_link_info(s, ...) \
+		pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_ovpn_link_warn(s, ...) \
+		pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#else /* CONFIG_DYNAMIC_DEBUG */
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_OVPN_LINK_DEBUG_LEVEL < 1)
+#define nss_ovpn_link_info(s, ...)
+#else
+#define nss_ovpn_link_info(s, ...) \
+		pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_OVPN_LINK_DEBUG_LEVEL < 2)
+#define nss_ovpn_link_warn(s, ...)
+#else
+#define nss_ovpn_link_warn(s, ...) \
+		pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+/*
+ * nss_ovpn_link_update_route()
+ *	Update OVPN tunnel route.
+ */
+static void nss_ovpn_link_update_route(struct net_device *tun_dev, uint32_t *from_addr, uint32_t *to_addr, int version)
+{
+	BUG_ON(!tun_dev);
+
+	nss_ovpnmgr_tun_route_update(tun_dev->ifindex, from_addr, to_addr, version);
+}
+
+/*
+ * nss_ovpn_link_get_ifnum()
+ *	Return NSS ifnum from OVPN manager.
+ */
+static int nss_ovpn_link_get_ifnum(struct net_device *dev, struct sk_buff *skb, struct net_device **tun_dev)
+{
+	struct nss_ovpnmgr_route_tuple rt={0};
+	struct ipv6hdr *ipv6;
+	uint32_t ifnum;
+
+	/*
+	 * skb start with L3 header
+	 */
+	if ((skb->protocol != htons(ETH_P_IP)) && (skb->protocol != htons(ETH_P_IPV6))) {
+		nss_ovpn_link_warn("%px: Protocol=%x is not supported\n", dev, skb->protocol);
+		return -1;
+	}
+
+	if (ip_hdr(skb)->version == IPVERSION) {	/* IPv4 Packet */
+		rt.ip_addr[0] = ip_hdr(skb)->saddr;
+		rt.ip_version = IPVERSION;
+
+		*tun_dev = nss_ovpnmgr_app_find_tun(dev, &rt, &ifnum);
+		if (*tun_dev) {
+			return (int)ifnum;
+		}
+
+		rt.ip_addr[0] = ip_hdr(skb)->daddr;
+
+		*tun_dev = nss_ovpnmgr_app_find_tun(dev, &rt, &ifnum);
+		if (*tun_dev) {
+			return (int)ifnum;
+		}
+
+		nss_ovpn_link_warn("%px: Failed to find tunnel device.\n", dev);
+		return -ENOENT;
+	}
+
+	/* IPv6 Packet */
+	ipv6 = ipv6_hdr(skb);
+
+	memcpy(&rt.ip_addr[0], &ipv6->saddr, sizeof(ipv6->saddr));
+	rt.ip_version = 6;
+
+	*tun_dev = nss_ovpnmgr_app_find_tun(dev, &rt, &ifnum);
+	if (*tun_dev) {
+		return (int)ifnum;
+	}
+
+	memcpy(&rt.ip_addr[0], &ipv6->daddr, sizeof(ipv6->daddr));
+
+	*tun_dev = nss_ovpnmgr_app_find_tun(dev, &rt, &ifnum);
+	if (*tun_dev) {
+		return (int)ifnum;
+	}
+
+	nss_ovpn_link_warn("%px: Failed to find tunnel device.\n", dev);
+	return -ENOENT;
+}
+
+/*
+ * nss_ovpn_ecm
+ *	Register Front End interface with ECM to support OVPN offload.
+ */
+static struct ecm_interface_ovpn nss_ovpn_ecm = {
+	.ovpn_update_route = nss_ovpn_link_update_route,
+	.ovpn_get_ifnum = nss_ovpn_link_get_ifnum
+};
+
+/*
+ * nss_ovpn_link_init()
+ *	Initialize NSS OVPN Manager
+ */
+int __init nss_ovpn_link_init(void)
+{
+	if (!nss_cmn_get_nss_enabled()) {
+		nss_ovpn_link_warn("OVPN Manager is not compatible with this Platform\n");
+		return -1;
+	}
+
+	if (ecm_interface_ovpn_register(&nss_ovpn_ecm)) {
+		nss_ovpn_link_warn("ecm fe registration failed.\n");
+		return -1;
+	}
+
+	nss_ovpn_link_info("NSS OVPN Link loaded: %s\n", NSS_CLIENT_BUILD_ID);
+
+	return 0;
+}
+
+/*
+ * nss_ovpn_link_exit()
+ *	Cleanup NSS OVPN Manager and exit
+ */
+void __exit nss_ovpn_link_exit(void)
+{
+	ecm_interface_ovpn_unregister();
+	nss_ovpn_link_info("OVPN Link unloaded\n");
+}
+
+module_init(nss_ovpn_link_init);
+module_exit(nss_ovpn_link_exit);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS OVPN");
diff --git a/qca-nss-clients/openvpn/plugins/nss_ovpn_sk.c b/qca-nss-clients/openvpn/plugins/nss_ovpn_sk.c
new file mode 100644
index 0000000..3db9fec
--- /dev/null
+++ b/qca-nss-clients/openvpn/plugins/nss_ovpn_sk.c
@@ -0,0 +1,917 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ovpn_sk.c
+ *	Socket implementation for OVPN.
+ */
+
+#include <linux/version.h>
+#include <linux/net.h>
+#include <linux/socket.h>
+#include <net/sock.h>
+#include <net/udp_tunnel.h>
+#include <linux/crypto.h>
+#include <linux/inetdevice.h>
+
+#include <nss_api_if.h>
+#include <nss_qvpn.h>
+#include "nss_ovpn_sk.h"
+#include "nss_ovpnmgr.h"
+#include "nss_ovpn_sk_priv.h"
+
+static struct proto nss_ovpn_sk_proto __read_mostly = {
+	.name = "OVPN",
+	.owner = THIS_MODULE,
+	.obj_size = sizeof(struct nss_ovpn_sk_pinfo),
+};
+
+/*
+ * nss_ovpn_sk_route_info_copy()
+ *	Copy route info passed from application.
+ */
+static inline void nss_ovpn_sk_route_info_copy(struct nss_ovpnmgr_route_tuple *route, struct nss_ovpn_sk_route_info *route_info)
+{
+	route->ip_version = route_info->ip_version;
+	memcpy(route->ip_addr, route_info->ip_network, sizeof(route_info->ip_network));
+}
+
+/*
+ * nss_ovpn_sk_route_state_get()
+ *	Get route status from OVPN manager.
+ */
+static int nss_ovpn_sk_route_state_get(struct socket *sock, unsigned long argp)
+{
+	struct nss_ovpn_sk_route_info route_info;
+	struct nss_ovpnmgr_route_tuple route;
+	struct nss_ovpn_sk_pinfo *pinfo = (struct nss_ovpn_sk_pinfo *)sock->sk;
+
+	if (!pinfo->dev) {
+		nss_ovpn_sk_warn("%px: Application is not registered\n", sock);
+		return -EINVAL;
+	}
+
+	if (copy_from_user(&route_info, (void *)argp, sizeof(route_info))) {
+		nss_ovpn_sk_warn("%px: Failed to copy route information\n", sock);
+		return -EFAULT;
+	}
+
+	nss_ovpn_sk_route_info_copy(&route, &route_info);
+	return nss_ovpnmgr_route_is_active(route_info.tunnel_id, &route);
+}
+
+/*
+ * nss_ovpn_sk_stats_get()
+ *	Get tunnel statistics.
+ */
+static int nss_ovpn_sk_stats_get(struct socket *sock, unsigned long argp)
+{
+	struct nss_ovpn_sk_tun_stats tun_stats;
+	struct nss_ovpnmgr_tun_stats stats;
+	struct nss_ovpn_sk_pinfo *pinfo = (struct nss_ovpn_sk_pinfo *)sock->sk;
+	int ret;
+
+	if (!pinfo->dev) {
+		nss_ovpn_sk_warn("%px: Application is not registered\n", sock);
+		return -EINVAL;
+	}
+
+	if (copy_from_user(&tun_stats, (void *)argp, sizeof(tun_stats))) {
+		nss_ovpn_sk_warn("%px: Failed to copy tunnel statistics\n", sock);
+		return -EFAULT;
+	}
+
+	ret = nss_ovpnmgr_tun_stats_get(tun_stats.tunnel_id, &stats);
+	if (ret) {
+		nss_ovpn_sk_warn("%px: Failed to get statistics for tunnel_id = %u\n", sock, tun_stats.tunnel_id);
+		return ret;
+	}
+
+	tun_stats.tun_read_bytes  = stats.tun_read_bytes;
+	tun_stats.tun_write_bytes = stats.tun_write_bytes;
+	tun_stats.link_read_bytes = stats.link_read_bytes;
+	tun_stats.link_read_bytes_auth = stats.link_read_bytes_auth;
+	tun_stats.link_write_bytes = stats.link_write_bytes;
+
+	if (copy_to_user((void *)argp, &tun_stats, sizeof(tun_stats))) {
+		nss_ovpn_sk_warn("%px: Failed to copy statistics\n", sock);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ovpn_sk_crypto_key_del()
+ *	Delete crypto key.
+ */
+static int nss_ovpn_sk_crypto_key_del(struct socket *sock, unsigned long argp)
+{
+	struct nss_ovpn_sk_crypto_session crypto_session;
+	struct nss_ovpn_sk_pinfo *pinfo = (struct nss_ovpn_sk_pinfo *)sock->sk;
+
+	if (!pinfo->dev) {
+		nss_ovpn_sk_warn("%px: Application is not registered\n", sock);
+		return -EINVAL;
+	}
+
+	if (copy_from_user(&crypto_session, (void *)argp, sizeof(crypto_session))) {
+		nss_ovpn_sk_warn("%px: Failed to copy crypto session\n", sock);
+		return -EFAULT;
+	}
+
+	return nss_ovpnmgr_crypto_key_del(crypto_session.tunnel_id);
+}
+
+/*
+ * nss_ovpn_sk_crypto_key_add()
+ *	Add crypto key.
+ */
+static int nss_ovpn_sk_crypto_key_add(struct socket *sock, unsigned long argp)
+{
+	struct nss_ovpn_sk_crypto_session crypto_info;
+	struct nss_ovpnmgr_crypto_config crypto_cfg;
+	struct nss_ovpn_sk_pinfo *pinfo = (struct nss_ovpn_sk_pinfo *)sock->sk;
+
+	if (!pinfo->dev) {
+		nss_ovpn_sk_warn("%px: Application is not registered\n", sock);
+		return -EINVAL;
+	}
+
+	if (copy_from_user(&crypto_info, (void *)argp, sizeof(crypto_info))) {
+		nss_ovpn_sk_warn("%px: Failed to copy crypto key\n", sock);
+		return -EFAULT;
+	}
+
+	crypto_cfg.algo = crypto_info.config.algo;
+	crypto_cfg.encrypt.cipher_keylen = crypto_info.config.cipher_key_size;
+	crypto_cfg.encrypt.hmac_keylen = crypto_info.config.hmac_key_size;
+	crypto_cfg.decrypt.cipher_keylen = crypto_info.config.cipher_key_size;
+	crypto_cfg.decrypt.hmac_keylen = crypto_info.config.hmac_key_size;
+
+	memcpy(&crypto_cfg.encrypt, &crypto_info.encrypt, sizeof(crypto_info.encrypt));
+	memcpy(&crypto_cfg.decrypt, &crypto_info.decrypt, sizeof(crypto_info.decrypt));
+
+	nss_ovpn_sk_info("%px: Crypto Add: tunnel_id = %u, key_id = %d\n", sock, crypto_info.tunnel_id, crypto_info.key_id);
+	return nss_ovpnmgr_crypto_key_add(crypto_info.tunnel_id, crypto_info.key_id, &crypto_cfg);
+}
+
+/*
+ * nss_ovpn_sk_route_del()
+ *	Delete route from tunnel.
+ */
+static int nss_ovpn_sk_route_del(struct socket *sock, unsigned long argp)
+{
+	struct nss_ovpn_sk_route_info route_info;
+	struct nss_ovpnmgr_route_tuple route;
+	struct nss_ovpn_sk_pinfo *pinfo = (struct nss_ovpn_sk_pinfo *)sock->sk;
+
+	if (!pinfo->dev) {
+		nss_ovpn_sk_warn("%px: Application is not registered\n", sock);
+		return -EINVAL;
+	}
+
+	if (copy_from_user(&route_info, (void *)argp, sizeof(route_info))) {
+		nss_ovpn_sk_warn("%px: Failed to copy route information\n", sock);
+		return -EFAULT;
+	}
+
+	nss_ovpn_sk_route_info_copy(&route, &route_info);
+	return nss_ovpnmgr_route_del(route_info.tunnel_id, &route);
+}
+
+/*
+ * nss_ovpn_sk_route_add()
+ *	Add route for the tunnel.
+ */
+static int nss_ovpn_sk_route_add(struct socket *sock, unsigned long argp)
+{
+	struct nss_ovpn_sk_route_info route_info;
+	struct nss_ovpnmgr_route_tuple route;
+	struct nss_ovpn_sk_pinfo *pinfo = (struct nss_ovpn_sk_pinfo *)sock->sk;
+
+	if (!pinfo->dev) {
+		nss_ovpn_sk_warn("%px: Application is not registered\n", sock);
+		return -EINVAL;
+	}
+
+	if (copy_from_user(&route_info, (void *)argp, sizeof(route_info))) {
+		nss_ovpn_sk_warn("%px: Failed to copy route information\n", sock);
+		return -EFAULT;
+	}
+
+	nss_ovpn_sk_route_info_copy(&route, &route_info);
+	return nss_ovpnmgr_route_add(route_info.tunnel_id, &route);
+}
+
+/*
+ * nss_ovpn_sk_update_ipv4_tuple()
+ *	Update ipv4 tuple with hop_limit and source IP if needed.
+ */
+static int nss_ovpn_sk_update_ipv4_tuple(struct nss_ovpn_sk_pinfo *pinfo, struct nss_ovpn_sk_tunnel *tun_data)
+{
+	struct rtable *rt;
+
+	rt = ip_route_output(dev_net(pinfo->dev), tun_data->tun_hdr.dst_ip[0], 0, 0, 0);
+	if (unlikely(IS_ERR(rt))) {
+		nss_ovpn_sk_warn("%px: Failed to find IPv4 route.\n", pinfo);
+		return -EINVAL;
+	}
+
+	if (!tun_data->tun_hdr.src_ip[0]) {
+		__be32 addr;
+
+		nss_ovpn_sk_info("%px: Source IP address is 0, find it\n", pinfo);
+		/*
+		 * Get Source IP address for given dst_ip.
+		 */
+		addr = inet_select_addr(rt->dst.dev, tun_data->tun_hdr.dst_ip[0], RT_SCOPE_LINK);
+		if (!addr) {
+			nss_ovpn_sk_warn("%px: Failed to find source IPv4 address.\n", pinfo);
+			return -EINVAL;
+		}
+
+		tun_data->tun_hdr.src_ip[0] = addr;
+	}
+
+	/*
+	 * Get TTL.
+	 */
+	tun_data->tun_hdr.hop_limit = ip4_dst_hoplimit(&rt->dst);
+	return 0;
+}
+
+/*
+ * nss_ovpn_sk_update_ipv6_tuple()
+ *	Update ipv6 tuple with hop_limit and source IP if needed.
+ */
+static int nss_ovpn_sk_update_ipv6_tuple(struct nss_ovpn_sk_pinfo *pinfo, struct nss_ovpn_sk_tunnel *tun_data)
+{
+	struct dst_entry *dst;
+	struct rt6_info *rt6;
+	int addr_type;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0))
+	rt6 = rt6_lookup(dev_net(pinfo->dev), (struct in6_addr *)tun_data->tun_hdr.dst_ip, NULL, 0, 0);
+#else
+	rt6 = rt6_lookup(dev_net(pinfo->dev), (struct in6_addr *)tun_data->tun_hdr.dst_ip, NULL, 0, 0, 0);
+#endif
+
+	if (!rt6) {
+		nss_ovpn_sk_warn("%px: Failed to find IPv6 route.\n", pinfo);
+		return -EINVAL;
+	}
+
+	dst = &rt6->dst;
+	/*
+	 * Find Source IP address if application did not provide.
+	 */
+	addr_type = ipv6_addr_type((struct in6_addr *)&tun_data->tun_hdr.src_ip);
+	if (addr_type == IPV6_ADDR_ANY) {
+		int ret;
+
+		ret = ipv6_dev_get_saddr(dev_net(pinfo->dev), ip6_dst_idev(dst)->dev,
+				(struct in6_addr *)tun_data->tun_hdr.dst_ip, 0,
+				(struct in6_addr *)tun_data->tun_hdr.src_ip);
+		if (ret) {
+			nss_ovpn_sk_warn("%px: Failed to find source IPv6 address: %d\n", pinfo, ret);
+			return -EINVAL;
+		}
+	}
+
+	tun_data->tun_hdr.hop_limit = ip6_dst_hoplimit(dst);
+	return 0;
+}
+
+/*
+ * nss_ovpn_sk_tun_del()
+ *	Delete tunnel.
+ */
+static int nss_ovpn_sk_tun_del(struct socket *sock, unsigned long argp)
+{
+	uint32_t tunnel_id;
+	struct nss_ovpn_sk_pinfo *pinfo = (struct nss_ovpn_sk_pinfo *)sock->sk;
+
+	if (!pinfo->dev) {
+		nss_ovpn_sk_warn("%px: Application is not registered\n", sock);
+		return -EINVAL;
+	}
+
+	if (copy_from_user(&tunnel_id, (void *)argp, sizeof(tunnel_id))) {
+		nss_ovpn_sk_warn("%px: Failed to copy tunnel id\n", sock);
+		return -EFAULT;
+	}
+
+	return nss_ovpnmgr_tun_del(tunnel_id);
+}
+
+/*
+ * nss_ovpn_sk_tun_add()
+ *	Add tunnel.
+ */
+static int nss_ovpn_sk_tun_add(struct socket *sock, unsigned long argp)
+{
+	struct nss_ovpn_sk_pinfo *pinfo = (struct nss_ovpn_sk_pinfo *)sock->sk;
+	struct nss_ovpnmgr_crypto_config crypto_cfg;
+	struct nss_ovpnmgr_tun_config tun_cfg;
+	struct nss_ovpnmgr_tun_tuple tun_hdr;
+	struct nss_ovpn_sk_tunnel tun_data;
+	struct net_device *tun_dev;
+	uint32_t tunnel_id;
+	int err;
+
+	if (!pinfo->dev) {
+		nss_ovpn_sk_warn("%px: Application is not registered\n", sock);
+		return -EINVAL;
+	}
+
+	if (copy_from_user(&tun_data, (void *)argp, sizeof(tun_data))) {
+		nss_ovpn_sk_warn("%px: Failed to copy application data\n", sock);
+		return -EFAULT;
+	}
+
+	tun_cfg.flags = tun_data.ovpn.flags;
+	tun_cfg.peer_id = tun_data.ovpn.peer_id;
+
+	/*
+	 * Update TTL and if necessary source IP address.
+	 */
+	if (tun_data.ovpn.flags & NSS_OVPN_SK_OVPN_HDR_FLAG_IPv6) {
+		err = nss_ovpn_sk_update_ipv6_tuple(pinfo, &tun_data);
+	} else {
+		err = nss_ovpn_sk_update_ipv4_tuple(pinfo, &tun_data);
+	}
+
+	if (err)
+		return err;
+
+	memcpy(&tun_hdr.src_ip[0], &tun_data.tun_hdr.src_ip[0], sizeof(tun_data.tun_hdr.src_ip));
+	memcpy(&tun_hdr.dst_ip[0], &tun_data.tun_hdr.dst_ip[0], sizeof(tun_data.tun_hdr.dst_ip));
+	tun_hdr.src_port = tun_data.tun_hdr.src_port;
+	tun_hdr.dst_port = tun_data.tun_hdr.dst_port;
+	tun_hdr.hop_limit = tun_data.tun_hdr.hop_limit;
+
+	crypto_cfg.algo = tun_data.crypto.config.algo;
+	crypto_cfg.encrypt.cipher_keylen = tun_data.crypto.config.cipher_key_size;
+	crypto_cfg.encrypt.hmac_keylen = tun_data.crypto.config.hmac_key_size;
+	crypto_cfg.decrypt.cipher_keylen = tun_data.crypto.config.cipher_key_size;
+	crypto_cfg.decrypt.hmac_keylen = tun_data.crypto.config.hmac_key_size;
+
+	memcpy(&crypto_cfg.encrypt.cipher_key, &tun_data.crypto.encrypt.cipher_key, tun_data.crypto.config.cipher_key_size);
+	memcpy(&crypto_cfg.encrypt.hmac_key, &tun_data.crypto.encrypt.hmac_key, tun_data.crypto.config.hmac_key_size);
+	memcpy(&crypto_cfg.decrypt.cipher_key, &tun_data.crypto.decrypt.cipher_key, tun_data.crypto.config.cipher_key_size);
+	memcpy(&crypto_cfg.decrypt.hmac_key, &tun_data.crypto.decrypt.hmac_key, tun_data.crypto.config.hmac_key_size);
+
+	/*
+	 * Add new tunnel.
+	 */
+	tunnel_id = nss_ovpnmgr_tun_add(pinfo->dev, &tun_hdr, &tun_cfg, &crypto_cfg);
+	if (!tunnel_id) {
+		nss_ovpn_sk_warn("%px: Failed to add tunnel for application:%u\n", sock, pinfo->pid);
+		return -EINVAL;
+	}
+
+	if (crypto_cfg.algo != NSS_OVPNMGR_ALGO_NULL_CIPHER_NULL_AUTH) {
+		/*
+		 * Add crypto key.
+		 */
+		err = nss_ovpnmgr_crypto_key_add(tunnel_id, tun_data.crypto.key_id, &crypto_cfg);
+		if (err) {
+			nss_ovpn_sk_warn("%px: crypto key add failed for tunnel_id = %u\n", sock, tunnel_id);
+			nss_ovpnmgr_tun_del(tunnel_id);
+			return -EFAULT;
+		}
+	}
+
+	/*
+	 * Bring up tunnel netdev.
+	 */
+	tun_dev = dev_get_by_index(&init_net, tunnel_id);
+	if (unlikely(!tun_dev)) {
+		nss_ovpn_sk_warn("%px: tun_dev is not found: tunnel_id = %u\n", sock, tunnel_id);
+		nss_ovpnmgr_tun_del(tunnel_id);
+		return -EFAULT;
+	}
+
+	dev_put(tun_dev);
+	/*
+	 * Bring up tunnel device.
+	 */
+	rtnl_lock();
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+	err = dev_open(tun_dev);
+#else
+	err = dev_open(tun_dev, NULL);
+#endif
+	rtnl_unlock();
+
+	if (err) {
+		nss_ovpn_sk_warn("%px: tun_dev is not found: tunnel_id = %u\n", sock, tunnel_id);
+		nss_ovpnmgr_tun_del(tunnel_id);
+		return -EFAULT;
+	}
+
+	/*
+	 * Copy tunnel_id to application memory.
+	 */
+	tun_data.ovpn.tunnel_id = tunnel_id;
+
+	if (copy_to_user((void *)argp, &tun_data, sizeof(tun_data))) {
+		nss_ovpn_sk_warn("%px: Failed to copy tunnel information to application\n", sock);
+		nss_ovpnmgr_tun_del(tunnel_id);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ovpn_sk_app_dereg()
+ *	Deregister application.
+ */
+static int nss_ovpn_sk_app_dereg(struct socket *sock, unsigned long argp)
+{
+	struct nss_ovpn_sk_pinfo *pinfo = (struct nss_ovpn_sk_pinfo *)sock->sk;
+	int ret;
+
+	if (!pinfo->dev) {
+		nss_ovpn_sk_warn("%px: Application is not registered\n", sock);
+		return -EINVAL;
+	}
+
+	nss_ovpn_sk_info("%px: Deregistering app with pid=%u\n", sock, pinfo->pid);
+	ret = nss_ovpnmgr_app_del(pinfo->dev);
+	if (!ret)
+		pinfo->pid = 0;
+
+	/*
+	 * pinfo->dev was held during application registration.
+	 * Since application is closing the socket. release the hold.
+	 */
+	if (pinfo->dev) {
+		dev_put(pinfo->dev);
+		pinfo->dev = NULL;
+	}
+
+	return  ret;
+}
+
+/*
+ * nss_ovpn_sk_app_reg()
+ *	Register application.
+ */
+static int nss_ovpn_sk_app_reg(struct socket *sock, unsigned long argp)
+{
+	struct nss_ovpn_sk_pinfo *pinfo = (struct nss_ovpn_sk_pinfo *)sock->sk;
+	struct nss_ovpn_sk_app_inst app;
+	int ret;
+
+	if (copy_from_user(&app, (void *)argp, sizeof(app))) {
+		nss_ovpn_sk_warn("%px: Failed to copy application data\n", sock);
+		return -EFAULT;
+	}
+	nss_ovpn_sk_info("%px: pid = %u, tun_fd = %d, udp_fd = %d\n", sock, app.pid, app.tun_fd, app.udp_fd);
+
+	pinfo->dev = dev_get_by_name(&init_net, app.tun_dev);
+	if (!pinfo->dev) {
+		nss_ovpn_sk_warn("%px: Couldn't find tun/tap dev=%s\n", sock, app.tun_dev);
+		return -EFAULT;
+	}
+
+	ret = nss_ovpnmgr_app_add(pinfo->dev, app.app_mode, (void *)sock);
+	if (ret) {
+		nss_ovpn_sk_warn("%px: Failed to register application, pid=%u\n", sock, app.pid);
+		dev_put(pinfo->dev);
+		return ret;
+	}
+
+	/*
+	 * Initialize socket private data.
+	 * this will be used in rest of the socket functionality
+	 */
+	pinfo->pid = app.pid;
+	pinfo->tun_fd = app.tun_fd;
+	pinfo->udp_fd = app.udp_fd;
+
+	/*
+	 * Do not release pinfo->dev here.  It will be used
+	 * by socket layer as long as the application is registered.
+	 */
+	return 0;
+}
+
+/*
+ * nss_ovpn_sk_release()
+ *	Release socket.
+ */
+int nss_ovpn_sk_release(struct socket *sock)
+{
+	struct nss_ovpn_sk_pinfo *pinfo = (struct nss_ovpn_sk_pinfo *)sock->sk;
+
+	nss_ovpn_sk_info("%px: Releasing socket\n", sock);
+	if (pinfo->pid && nss_ovpnmgr_app_del(pinfo->dev)) {
+		nss_ovpn_sk_info("%px: Failed to delete App\n", sock);
+	}
+
+	/*
+	 * pinfo->dev was held during application registration.
+	 * Since application is closing the socket. release the hold.
+	 */
+	if (pinfo->dev) {
+		dev_put(pinfo->dev);
+		pinfo->dev = NULL;
+	}
+
+	if (sock->sk)
+		sock_put(sock->sk);
+
+	return 0;
+}
+
+/*
+ * nss_ovpn_sk_sendmsg()
+ *	Receive packet from application.
+ */
+static int nss_ovpn_sk_sendmsg(struct socket *sock, struct msghdr *msg, size_t len)
+{
+	struct nss_ovpn_sk_pkt_info *pkt_info_data;
+	struct nss_ovpnmgr_metadata mdata;
+	struct nss_ovpn_sk_pinfo *pinfo = (struct nss_ovpn_sk_pinfo *)sock->sk;
+	struct sk_buff *skb = NULL;
+	struct cmsghdr *cmsg;
+	size_t total_len = iov_iter_count(&msg->msg_iter);
+	uint8_t *data;
+	int outer_hdr_offset = 0;
+
+	if (!pinfo->dev) {
+		nss_ovpn_sk_warn("%px: Application is not registered\n", sock);
+		return -EINVAL;
+	}
+
+	/*
+	 * Packet received from application has two parts:
+	 *	1. Control message provides details of the packet.
+	 *	2. Packet content.
+	 * Extract control message into pkt_info.
+	 */
+	cmsg = CMSG_FIRSTHDR(msg);
+	if (!cmsg) {
+		nss_ovpn_sk_warn("%px: Control message is invalid\n", sock);
+		return -EINVAL;
+	}
+
+	if (!CMSG_OK(msg, cmsg)) {
+		nss_ovpn_sk_warn("%px: Incorrect message format\n", sock);
+		return -EINVAL;
+	}
+
+	if (cmsg->cmsg_len < CMSG_LEN(sizeof(*pkt_info_data))) {
+		nss_ovpn_sk_warn("%px: Incorrect message length\n", sock);
+		return -EINVAL;
+	}
+
+	pkt_info_data = (struct nss_ovpn_sk_pkt_info *)CMSG_DATA(cmsg);
+	if (!pkt_info_data) {
+		nss_ovpn_sk_warn("%px: Cannot send this packet, there is no msg_control\n", sock);
+		return -EFAULT;
+	}
+
+	if (pkt_info_data->flags & NSS_OVPN_SK_PKT_INFO_FLAG_DIR_DECAP) {
+		if (pkt_info_data->flags & NSS_OVPN_SK_PKT_INFO_FLAG_PKT_TYPE_IPV6) {
+			outer_hdr_offset = sizeof(struct ipv6hdr) + sizeof(struct udphdr);
+			nss_ovpn_sk_info("%px: Decrypt: IPv6 + UDP\n", sock);
+		} else {
+			outer_hdr_offset = sizeof(struct iphdr) + sizeof(struct udphdr);
+			nss_ovpn_sk_info("%px: Decrypt: IPv4 + UDP\n", sock);
+		}
+	} else {
+		/*
+		 * Encapsulation requires headroom + tailroom.
+		 */
+		outer_hdr_offset = NSS_OVPNMGR_TUN_HEADROOM + NSS_OVPNMGR_TUN_TAILROOM;
+	}
+
+	skb = dev_alloc_skb(total_len + outer_hdr_offset);
+	if (unlikely(!skb)) {
+		nss_ovpn_sk_warn("%px: Couldn't allocation skb\n", sock);
+		return -ENOBUFS;
+	}
+
+	if (pkt_info_data->flags & NSS_OVPN_SK_PKT_INFO_FLAG_DIR_DECAP) {
+		data = skb_put(skb, total_len + outer_hdr_offset);
+		data += outer_hdr_offset;
+	} else {
+		skb_reserve(skb, NSS_OVPNMGR_TUN_HEADROOM);
+		data = skb_put(skb, total_len);
+	}
+
+	if (copy_from_iter(data, total_len, &msg->msg_iter) != total_len) {
+		nss_ovpn_sk_info("%px: skb copy conversion failed\n", sock);
+		dev_kfree_skb_any(skb);
+		return -EFAULT;
+	}
+
+	mdata.tunnel_id = pkt_info_data->tunnel_id;
+	mdata.flags = pkt_info_data->flags;
+
+	if (nss_ovpnmgr_tun_tx(mdata.tunnel_id, &mdata, skb)) {
+		nss_ovpn_sk_info("%px: Packet offload failed.\n", sock);
+		dev_kfree_skb_any(skb);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ovpn_sk_recvmsg()
+ *	Send packet to application.
+ */
+static int nss_ovpn_sk_recvmsg(struct socket *sock, struct msghdr *msg, size_t size, int flags)
+{
+	struct nss_ovpn_sk_pkt_info *pkt_info_data, pkt_data;
+	struct nss_ovpnmgr_metadata pkt_info;
+	int copied, ret;
+	struct sk_buff *skb;
+	struct cmsghdr *cmsg, k_cmsg;
+	struct sock *sk = sock->sk;
+
+	if (flags & ~(MSG_PEEK | MSG_DONTWAIT | MSG_TRUNC | MSG_CMSG_COMPAT)) {
+		nss_ovpn_sk_info("%px: Cannot send this packet to app, there is no msg_control\n", sock);
+		return -EINVAL;
+	}
+
+	/*
+	 * Packet received from application has two parts:
+	 *	1. Control message provides details of the packet.
+	 *	2. Packet content.
+	 * Extract control message into pkt_info.
+	 */
+	cmsg = CMSG_FIRSTHDR(msg);
+	if (!cmsg) {
+		nss_ovpn_sk_warn("%px: Control message is invalid\n", sock);
+		return -EINVAL;
+	}
+
+	if (copy_from_user(&k_cmsg, cmsg, sizeof(struct cmsghdr))) {
+		nss_ovpn_sk_warn("Copy from user failed\n");
+		return -EINVAL;
+	}
+
+	cmsg = &k_cmsg;
+
+	if (!CMSG_OK(msg, cmsg)) {
+		nss_ovpn_sk_warn("%px: Incorrect message format\n", sock);
+		return -EINVAL;
+	}
+
+	if (cmsg->cmsg_len < CMSG_LEN(sizeof(*pkt_info_data))) {
+		nss_ovpn_sk_warn("%px: Incorrect message length\n", sock);
+		return -EINVAL;
+	}
+
+	pkt_info_data = (struct nss_ovpn_sk_pkt_info *)CMSG_DATA(cmsg);
+	if (!pkt_info_data) {
+		nss_ovpn_sk_warn("%px: Cannot send this packet to app, there is no msg_control.\n", sock);
+		return -EINVAL;
+	}
+
+	skb = skb_recv_datagram(sk, flags, MSG_DONTWAIT, &ret);
+	if (!skb) {
+		nss_ovpn_sk_warn("%px: There are no packets in the queue.\n", sock);
+		return -ENOBUFS;
+	}
+
+	/*
+	 * Control informatoin of packet is copied in skb->cb by OVPN manager.
+	 * Send control information to application.
+	 */
+	memcpy(&pkt_info, skb->cb, sizeof(pkt_info));
+
+	pkt_data.tunnel_id = pkt_info.tunnel_id;
+	pkt_data.flags = pkt_info.flags;
+
+	if (copy_to_user(pkt_info_data, &pkt_data, sizeof(pkt_data))) {
+		nss_ovpn_sk_warn("Copy from user failed\n");
+		return -EINVAL;
+	}
+
+	put_cmsg(msg, SOL_IP, IP_PKTINFO, sizeof(*pkt_info_data), pkt_info_data);
+
+	copied = skb->len;
+	if (copied > size) {
+		msg->msg_flags |= MSG_TRUNC;
+		copied = size;
+	}
+
+	skb_reset_transport_header(skb);
+	ret = skb_copy_datagram_msg(skb, 0, msg, copied);
+	if (ret) {
+		nss_ovpn_sk_warn("%px: Packet copy to user failed\n", sock);
+		skb_free_datagram(sk, skb);
+		return ret;
+	}
+
+	ret = (flags & MSG_TRUNC) ? skb->len : copied;
+	nss_ovpn_sk_info("%px: Message copied with packet length=%d\n", sock, ret);
+	return ret;
+}
+
+/*
+ * nss_ovpn_sk_ioctl()
+ *	Ioctl interface.
+ */
+static int nss_ovpn_sk_ioctl(struct socket *sock, unsigned int cmd, unsigned long argp)
+{
+	switch (cmd) {
+	case NSS_OVPN_SK_SIOC_APP_REG:
+		return nss_ovpn_sk_app_reg(sock, argp);
+	case NSS_OVPN_SK_SIOC_APP_DEREG:
+		return nss_ovpn_sk_app_dereg(sock, argp);
+	case NSS_OVPN_SK_SIOC_TUN_ADD:
+		return nss_ovpn_sk_tun_add(sock, argp);
+	case NSS_OVPN_SK_SIOC_TUN_DEL:
+		return nss_ovpn_sk_tun_del(sock, argp);
+	case NSS_OVPN_SK_SIOC_ROUTE_ADD:
+		return nss_ovpn_sk_route_add(sock, argp);
+	case NSS_OVPN_SK_SIOC_ROUTE_DEL:
+		return nss_ovpn_sk_route_del(sock, argp);
+	case NSS_OVPN_SK_SIOC_ROUTE_STATE_GET:
+		return nss_ovpn_sk_route_state_get(sock, argp);
+	case NSS_OVPN_SK_SIOC_CRYPTO_KEY_ADD:
+		return nss_ovpn_sk_crypto_key_add(sock, argp);
+	case NSS_OVPN_SK_SIOC_CRYPTO_KEY_DEL:
+		return nss_ovpn_sk_crypto_key_del(sock, argp);
+	case NSS_OVPN_SK_SIOC_STATS_GET:
+		return nss_ovpn_sk_stats_get(sock, argp);
+	}
+
+	nss_ovpn_sk_warn("%px: Invalid ioctl command: %u\n", sock, cmd);
+	return -ENOIOCTLCMD;
+}
+
+static const struct proto_ops nss_ovpn_sk_proto_ops = {
+	.family = PF_OVPN,
+	.owner = THIS_MODULE,
+
+	.connect = sock_no_connect,
+	.socketpair = sock_no_socketpair,
+	.getname = sock_no_getname,
+	.ioctl = nss_ovpn_sk_ioctl,
+	.listen = sock_no_listen,
+	.shutdown = sock_no_shutdown,
+	.getsockopt = sock_no_getsockopt,
+	.mmap = sock_no_mmap,
+	.sendpage = sock_no_sendpage,
+	.sendmsg = nss_ovpn_sk_sendmsg,
+	.recvmsg = nss_ovpn_sk_recvmsg,
+	.poll = datagram_poll,
+	.bind = sock_no_bind,
+	.release = nss_ovpn_sk_release,
+	.setsockopt = sock_no_setsockopt,
+	.accept = sock_no_accept,
+};
+
+/*
+ * nss_ovpn_sk_create()
+ *	Create OVPN socket.
+ */
+static int nss_ovpn_sk_create(struct net *net, struct socket *sock, int protocol, int kern)
+{
+	struct nss_ovpn_sk_pinfo *pinfo;
+	struct sock *sk;
+
+	nss_ovpn_sk_info("%px: protocol = %d, sock->type = %d\n", sock, protocol, sock->type);
+
+	if (sock->type != SOCK_DGRAM) {
+		nss_ovpn_sk_warn("%px: Only SOCK_DGRAM socket is supported\n", sock);
+		return -ESOCKTNOSUPPORT;
+	}
+
+	/*
+	 * For now we don't have any protocol defined.
+	 * We could define different protocols and generalize
+	 * this implementation.
+	 */
+	if (protocol) {
+		nss_ovpn_sk_warn("%px: Protocol specific socket is not implemented.\n", sock);
+		return -EPROTONOSUPPORT;
+	}
+
+	sk = sk_alloc(net, PF_OVPN, GFP_KERNEL, &nss_ovpn_sk_proto, kern);
+	if (!sk) {
+		nss_ovpn_sk_warn("%px: sock instance allocation failed.\n", sock);
+		return -ENOMEM;
+	}
+
+	pinfo =  (struct nss_ovpn_sk_pinfo *)sk;
+	pinfo->pid = 0;
+	pinfo->tun_fd = 0;
+	pinfo->tun_sock = NULL;
+	pinfo->udp_fd = 0;
+
+	sock->ops = &nss_ovpn_sk_proto_ops;
+	sock_init_data(sock, sk);
+
+	sk->sk_family = PF_OVPN;
+	sk->sk_destruct = NULL;
+
+	nss_ovpn_sk_info("Socket created successfully\n");
+	return 0;
+}
+
+static const struct net_proto_family nss_ovpn_sk_family = {
+	.family = PF_OVPN,
+	.create = nss_ovpn_sk_create,
+	.owner = THIS_MODULE,
+};
+
+/*
+ * nss_ovpn_sk_send()
+ *	Enqueue packet to socket queue.
+ */
+int nss_ovpn_sk_send(struct sk_buff *skb, void *app_data)
+{
+	struct socket *sock = app_data;
+	struct sock *sk;
+
+	if (!app_data) {
+		nss_ovpn_sk_warn("%px: app_data is NULL\n", skb);
+		return -1;
+	}
+
+	if (unlikely(skb_orphan_frags(skb, GFP_ATOMIC))) {
+		return -1;
+	}
+
+	sk = sock->sk;
+
+	/*
+	 * Orphan the skb - required as we might hang on to it
+	 * for indefinite time.
+	 */
+	skb_orphan(skb);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	nf_reset(skb);
+#else
+	nf_reset_ct(skb);
+#endif
+
+	/* Enqueue packet */
+	if (sock_queue_rcv_skb(sk, skb) < 0) {
+		return -1;
+	}
+
+	nss_ovpn_sk_info("%px: Packet enqueued into socket queue\n", skb);
+
+	return 0;
+}
+
+/*
+ * nss_ovpn_sk_init()
+ *	Register OVPN socket family.
+ */
+int nss_ovpn_sk_init(void)
+{
+	int ret = proto_register(&nss_ovpn_sk_proto, 0);
+
+	if (ret) {
+		nss_ovpn_sk_warn("Failed to register OVPN socket protocol\n");
+		return ret;
+	}
+
+	ret = sock_register(&nss_ovpn_sk_family);
+	if (ret) {
+		nss_ovpn_sk_warn("Failed to register OVPN socket family\n");
+		proto_unregister(&nss_ovpn_sk_proto);
+		return ret;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ovpn_sk_cleanup()
+ *	De-register OVPN socket family.
+ */
+void nss_ovpn_sk_cleanup(void)
+{
+	sock_unregister(PF_OVPN);
+	proto_unregister(&nss_ovpn_sk_proto);
+}
+
+MODULE_ALIAS_NETPROTO(AF_OVPN);
diff --git a/qca-nss-clients/openvpn/plugins/nss_ovpn_sk_priv.h b/qca-nss-clients/openvpn/plugins/nss_ovpn_sk_priv.h
new file mode 100644
index 0000000..da1208e
--- /dev/null
+++ b/qca-nss-clients/openvpn/plugins/nss_ovpn_sk_priv.h
@@ -0,0 +1,68 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ovpnmgr_sk_priv.h
+ */
+#ifndef __NSS_OVPNMGR_SOCKET__H
+#define __NSS_OVPNMGR_SOCKET__H
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_ovpn_sk_warn(s, ...) \
+		pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_ovpn_sk_info(s, ...) \
+		pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_ovpn_sk_trace(s, ...) \
+		pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#else /* CONFIG_DYNAMIC_DEBUG */
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_OVPNMGR_DEBUG_LEVEL < 2)
+#define nss_ovpn_sk_warn(s, ...)
+#else
+#define nss_ovpn_sk_warn(s, ...) \
+		pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_OVPNMGR_DEBUG_LEVEL < 3)
+#define nss_ovpn_sk_info(s, ...)
+#else
+#define nss_ovpn_sk_info(s, ...) \
+		pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+/*
+ * nss_ovpn_sk_pinfo
+ */
+struct nss_ovpn_sk_pinfo {
+	struct sock sk;		/* Sock instance (struct sock must be the first member). */
+	pid_t pid;		/* PID of application which has created socket. */
+	int32_t tun_fd;		/* TUN/TAP character device file descriptor. */
+	int32_t udp_fd;		/* UDP socket file descriptor. */
+	struct socket *tun_sock;/* Socket instance. */
+	struct net_device *dev;	/* TUN/TAP netdevice. */
+};
+
+int nss_ovpn_sk_init(void);
+int nss_ovpn_sk_send(struct sk_buff *skb, void *app_data);
+void nss_ovpn_sk_cleanup(void);
+
+#endif /* __NSS_OVPNMGR_SOCKET__H */
diff --git a/qca-nss-clients/openvpn/src/Makefile b/qca-nss-clients/openvpn/src/Makefile
new file mode 100644
index 0000000..defe84d
--- /dev/null
+++ b/qca-nss-clients/openvpn/src/Makefile
@@ -0,0 +1,12 @@
+# Makefile for the ovpnmgr client
+
+ccflags-y := $(NSS_CCFLAGS) -I$(obj) -I$(obj)/../../exports -I$(obj)/include -I$(obj)/../plugins
+ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)"
+ccflags-y += -DNSS_OVPNMGR_DEBUG_LEVEL=0 -DNSS_OVPNMGR_DEBUG_ENABLE_PKT_DUMP=0
+ccflags-y += -Wall -Werror
+
+obj-m += qca-nss-ovpn-mgr.o
+qca-nss-ovpn-mgr-objs := nss_ovpnmgr.o nss_ovpnmgr_app.o nss_ovpnmgr_tun.o nss_ovpnmgr_crypto.o \
+			 nss_ovpnmgr_route.o nss_ovpnmgr_debugfs.o \
+			 ../plugins/nss_ovpn_sk.o
+obj ?= .
diff --git a/qca-nss-clients/openvpn/src/nss_ovpnmgr.c b/qca-nss-clients/openvpn/src/nss_ovpnmgr.c
new file mode 100644
index 0000000..17b8f03
--- /dev/null
+++ b/qca-nss-clients/openvpn/src/nss_ovpnmgr.c
@@ -0,0 +1,179 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ovpnmgr.c
+ */
+#include <linux/module.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/crypto.h>
+#include <linux/if_tun.h>
+
+#include <nss_api_if.h>
+#include <nss_qvpn.h>
+#include "nss_ovpnmgr.h"
+#include "nss_ovpnmgr_crypto.h"
+#include "nss_ovpnmgr_app.h"
+#include "nss_ovpnmgr_tun.h"
+#include "nss_ovpnmgr_debugfs.h"
+#include "nss_ovpnmgr_priv.h"
+#include "nss_ovpnmgr_route.h"
+#include "nss_ovpn_sk_priv.h"
+
+/*
+ * OVPN manager context structure
+ */
+struct nss_ovpnmgr_context ovpnmgr_ctx;
+
+/*
+ * nss_ovpnmgr_netdevice_event()
+ *	OpenVPN manager netdevice notifications.
+ */
+static int nss_ovpnmgr_netdevice_event(struct notifier_block *unused,
+					unsigned long event, void *ptr)
+{
+	struct netdev_notifier_info *info = ptr;
+	struct net_device *app_dev = netdev_notifier_info_to_dev(info);
+	struct nss_ovpnmgr_tun *tun, *n;
+	struct nss_ovpnmgr_app *app;
+	struct net_device *nss_dev;
+
+	/*
+	 * Do not process any event other than UP and DOWN
+	 */
+	if ((event != NETDEV_UP) && (event != NETDEV_DOWN)) {
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * We should process notification only for TUN/TAP device
+	 */
+	if (!(app_dev->priv_flags_ext & IFF_EXT_TUN_TAP)) {
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Find the application for the net_device triggering notification
+	 */
+	read_lock_bh(&ovpnmgr_ctx.lock);
+
+	app = nss_ovpnmgr_app_find(app_dev);
+	if (unlikely(!app)) {
+		read_unlock_bh(&ovpnmgr_ctx.lock);
+		nss_ovpnmgr_warn("%px: Application is not registered: app_dev = %s\n", app_dev, app_dev->name);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Listen to application netdevice UP and DOWN event. If UP event is triggered
+	 * then bring all NSS device attached to application device UP. If down event is triggered
+	 * then bring down all NSS device attached to application device DOWN. This will make ECM
+	 * flush(DOWN)/add(UP) flow rules in the system.
+	 *
+	 * Iterate through all NSS device registered and change their state to UP
+	 */
+	list_for_each_entry_safe(tun, n, &app->tun_list, list) {
+		nss_dev = __dev_get_by_index(&init_net, tun->tunnel_id);
+		if (unlikely(!nss_dev)) {
+			nss_ovpnmgr_warn("%px: Couldn't find tunnel: tunnel_id = %u\n\n", tun, tun->tunnel_id);
+			continue;
+		}
+
+		/*
+		 * dev_open and dev_close can sleep; hence calling it in non atomic context.
+		 */
+		read_unlock_bh(&ovpnmgr_ctx.lock);
+		if (event == NETDEV_UP) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+			dev_open(nss_dev);
+#else
+			dev_open(nss_dev, NULL);
+#endif
+
+		} else {
+			dev_close(nss_dev);
+		}
+
+		read_lock_bh(&ovpnmgr_ctx.lock);
+	}
+
+	read_unlock_bh(&ovpnmgr_ctx.lock);
+
+	/*
+	 * Notify done for all the events we don't care
+	 */
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_ovpnmgr_netdevice_nb
+ *	OpenVPN Netdevice notification callback
+ */
+static struct notifier_block nss_ovpnmgr_netdevice_nb __read_mostly = {
+	.notifier_call = nss_ovpnmgr_netdevice_event,
+};
+
+/*
+ * nss_ovpnmgr_init()
+ *	Initialize NSS OVPN Manager
+ */
+int __init nss_ovpnmgr_init(void)
+{
+	if (!nss_cmn_get_nss_enabled()) {
+		nss_ovpnmgr_warn("OVPN Manager is not compatible with this platform\n");
+		return -1;
+	}
+
+	rwlock_init(&ovpnmgr_ctx.lock);
+	INIT_LIST_HEAD(&ovpnmgr_ctx.app_list);
+
+	if (nss_ovpn_sk_init()) {
+		nss_ovpnmgr_warn("Failed to initialize socket interface\n");
+		return -1;
+	}
+
+	if (nss_ovpnmgr_debugfs_init()) {
+		nss_ovpnmgr_warn("Debugfs Initialization failed\n");
+		nss_ovpn_sk_cleanup();
+		return -1;
+	}
+
+	tun_register_offload_stats_callback(nss_ovpnmgr_tun_get_stats);
+	register_netdevice_notifier(&nss_ovpnmgr_netdevice_nb);
+	nss_ovpnmgr_info("OVPN Init successful\n");
+	return 0;
+}
+
+/*
+ * nss_ovpnmgr_exit()
+ *	Cleanup NSS OVPN Manager and exit
+ */
+void __exit nss_ovpnmgr_exit(void)
+{
+	unregister_netdevice_notifier(&nss_ovpnmgr_netdevice_nb);
+	nss_ovpnmgr_debugfs_cleanup();
+	nss_ovpn_sk_cleanup();
+	tun_unregister_offload_stats_callback();
+	nss_ovpnmgr_info("OVPN Manager Removed\n");
+}
+
+module_init(nss_ovpnmgr_init);
+module_exit(nss_ovpnmgr_exit);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS OVPN Manager");
diff --git a/qca-nss-clients/openvpn/src/nss_ovpnmgr_app.c b/qca-nss-clients/openvpn/src/nss_ovpnmgr_app.c
new file mode 100644
index 0000000..9a2556a
--- /dev/null
+++ b/qca-nss-clients/openvpn/src/nss_ovpnmgr_app.c
@@ -0,0 +1,302 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ovpnmgr_app.c
+ */
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/if_tun.h>
+#include <linux/ip.h>
+#include <net/ip.h>
+#include <net/udp.h>
+#include <net/ip6_checksum.h>
+#include <linux/ipv6.h>
+#include <linux/crypto.h>
+
+#include <nss_api_if.h>
+#include <nss_qvpn.h>
+#include "nss_ovpnmgr.h"
+#include "nss_ovpnmgr_crypto.h"
+#include "nss_ovpnmgr_tun.h"
+#include "nss_ovpnmgr_app.h"
+#include "nss_ovpnmgr_debugfs.h"
+#include "nss_ovpnmgr_priv.h"
+#include "nss_ovpnmgr_route.h"
+#include "nss_ovpn_sk_priv.h"
+
+/*
+ * nss_ovpnmgr_app_find_dev()
+ *	Returns net_device on which route tuple is routed
+ */
+static struct net_device *nss_ovpnmgr_app_find_dev(struct nss_ovpnmgr_route_tuple *rt)
+{
+	struct net_device *dev;
+	struct rt6_info *rt6;
+	struct rtable *rt4;
+
+	if (rt->ip_version == IPVERSION) {
+		rt4 = ip_route_output(&init_net, rt->ip_addr[0], 0, 0, 0);
+		if (IS_ERR(rt4)) {
+			return NULL;
+		}
+
+		dev = rt4->dst.dev;
+		ip_rt_put(rt4);
+
+		return dev;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0))
+	rt6 = rt6_lookup(&init_net, (const struct in6_addr *)rt->ip_addr, NULL, 0, 0);
+#else
+	rt6 = rt6_lookup(&init_net, (const struct in6_addr *)rt->ip_addr, NULL, 0, 0, 0);
+#endif
+
+	if (!rt6) {
+		return NULL;
+	}
+
+	dev = rt6->dst.dev;
+	ip6_rt_put(rt6);
+
+	return dev;
+}
+
+/*
+ * nss_ovpnmgr_app_find_tun()
+ *	Returns NSS ifnum.
+ */
+struct net_device *nss_ovpnmgr_app_find_tun(struct net_device *app_dev, struct nss_ovpnmgr_route_tuple *rt, uint32_t *ifnum)
+{
+	struct nss_ovpnmgr_app *app;
+	struct nss_ovpnmgr_tun *tun;
+	struct net_device *dev = NULL;
+	uint32_t tun_ifnum = NSS_MAX_NET_INTERFACES;
+	ssize_t addr_size;
+
+	addr_size = (rt->ip_version == IPVERSION) ? sizeof(rt->ip_addr[0]) : sizeof(rt->ip_addr);
+
+	read_lock_bh(&ovpnmgr_ctx.lock);
+
+	app = nss_ovpnmgr_app_find(app_dev);
+	if (!app) {
+		read_unlock_bh(&ovpnmgr_ctx.lock);
+		nss_ovpnmgr_warn("%px: Application is not registered, app_dev=%s\n", app_dev, app_dev->name);
+		return NULL;
+	}
+
+	/*
+	 * Check if application device is in UP state. If it is UP then only
+	 * allow ECM to push flow rules. This logic will make sure that openvpn
+	 * flows are not accelerated when tunnel device is down
+	 */
+	if (!(app->dev->flags & IFF_UP)) {
+		read_unlock_bh(&ovpnmgr_ctx.lock);
+		nss_ovpnmgr_warn("%px: Application device not up, app_dev=%s\n", app->dev, app->dev->name);
+		return NULL;
+	}
+
+	if (app->mode == NSS_OVPNMGR_APP_MODE_CLIENT) {
+		/*
+		 * There are no routes in client mode.
+		 */
+
+		list_for_each_entry(tun, &app->tun_list, list) {
+
+			dev = nss_ovpnmgr_app_find_dev(rt);
+			/*
+			 * If routed interface is tun/tap return inner interface.
+			 */
+			if (dev == app->dev) {
+				nss_ovpnmgr_info("%px: Found dev = %s\n", app, dev->name);
+				tun_ifnum = tun->inner.ifnum;
+				dev = tun->dev;
+				goto done;
+			}
+
+			/*
+			 * Check if rt->ip_addr matches tunnel IP.
+			 */
+			if (!memcmp(rt->ip_addr, &tun->tun_hdr.src_ip, addr_size)) {
+				nss_ovpnmgr_info("%px: Encapsulated packet.\n", app);
+				tun_ifnum = tun->outer.ifnum;
+				dev = tun->dev;
+				goto done;
+			}
+		}
+		read_unlock_bh(&ovpnmgr_ctx.lock);
+		return NULL;
+	}
+
+	list_for_each_entry(tun, &app->tun_list, list) {
+		struct nss_ovpnmgr_route *route;
+
+		route = nss_ovpnmgr_route_find(&tun->route_list, rt);
+		if (route) {
+			tun_ifnum = tun->inner.ifnum;
+			dev = tun->dev;
+			goto done;
+		}
+
+		/*
+		 * Check if rt->ip_addr matches tunnel IP.
+		 */
+		if (!memcmp(rt->ip_addr, &tun->tun_hdr.src_ip, addr_size)) {
+			tun_ifnum = tun->outer.ifnum;
+			dev = tun->dev;
+			goto done;
+		}
+	}
+done:
+	read_unlock_bh(&ovpnmgr_ctx.lock);
+	*ifnum = tun_ifnum;
+	return dev;
+}
+EXPORT_SYMBOL(nss_ovpnmgr_app_find_tun);
+
+/*
+ * nss_ovpnmgr_app_forward()
+ *	Send packet to Host
+ */
+void nss_ovpnmgr_app_forward(struct nss_ovpnmgr_app *app, struct nss_ovpnmgr_tun *tun, struct sk_buff *skb)
+{
+	struct nss_ovpnmgr_metadata *metadata = (struct nss_ovpnmgr_metadata *)skb->cb;
+
+	BUILD_BUG_ON(sizeof(skb->cb) < sizeof(struct nss_ovpnmgr_metadata));
+
+	metadata->flags = NSS_OVPNMGR_METADATA_FLAG_PKT_DECAP | NSS_OVPNMGR_METADATA_FLAG_PKT_TYPE_CTRL;
+	metadata->tunnel_id = tun->tunnel_id;
+
+	if (nss_ovpn_sk_send(skb, app->app_data)) {
+		nss_ovpnmgr_warn("%px: failed to send packet to OVPN application.\n", tun);
+		tun->inner.stats.host_pkt_drop++;
+		dev_kfree_skb_any(skb);
+	}
+}
+
+/*
+ * nss_ovpnmgr_app_find()
+ *	Find OVPN application instance.
+ */
+struct nss_ovpnmgr_app *nss_ovpnmgr_app_find(struct net_device *dev)
+{
+	struct nss_ovpnmgr_app *app;
+
+	list_for_each_entry(app, &ovpnmgr_ctx.app_list, list) {
+		if (app->dev == dev) {
+			return app;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_ovpnmgr_app_del()
+ *	Delete OpenVPN application.
+ */
+int nss_ovpnmgr_app_del(struct net_device *app_dev)
+{
+	struct nss_ovpnmgr_app *app;
+	struct nss_ovpnmgr_tun *tun, *n;
+
+	write_lock_bh(&ovpnmgr_ctx.lock);
+
+	app = nss_ovpnmgr_app_find(app_dev);
+	if (!app) {
+		write_unlock_bh(&ovpnmgr_ctx.lock);
+		nss_ovpnmgr_warn("%px: Application is not registered: app_dev = %s\n", app_dev, app_dev->name);
+		return -ENODEV;
+	}
+
+	list_del(&app->list);
+	write_unlock_bh(&ovpnmgr_ctx.lock);
+
+	nss_ovpnmgr_info("%px: Uninitializing application instance\n", app);
+
+	/*
+	 * Application is removed from list.
+	 * Check if there are any tunnels.
+	 * Delete all the tunnels from NSS FW and free.
+	 */
+	list_for_each_entry_safe(tun, n, &app->tun_list, list) {
+		nss_ovpnmgr_tun_del(tun->tunnel_id);
+	}
+
+	dev_put(app_dev);
+	nss_ovpnmgr_debugfs_remove(app->dentry);
+
+	kfree(app);
+	return 0;
+}
+EXPORT_SYMBOL(nss_ovpnmgr_app_del);
+
+/*
+ * nss_ovpnmgr_app_add()
+ *	Add OpenVPN application.
+ */
+int nss_ovpnmgr_app_add(struct net_device *app_dev, enum nss_ovpnmgr_app_mode mode, void *app_data)
+{
+	struct nss_ovpnmgr_app *app;
+
+	BUG_ON(!app_dev);
+
+	nss_ovpnmgr_info("Adding new APP :tun_dev=%s:", app_dev->name);
+
+	app = kzalloc(sizeof(*app), GFP_KERNEL);
+	if (!app) {
+		nss_ovpnmgr_warn("Failed to allocate memory for app\n");
+		return -ENOMEM;
+	}
+
+	INIT_LIST_HEAD(&app->tun_list);
+	INIT_LIST_HEAD(&app->list);
+	/*
+	 * Hold tun/tap netdev and release when deleting application.
+	 */
+	dev_hold(app_dev);
+
+	/*
+	 * Initialize application instance.
+	 */
+	app->mode = mode;
+	app->dev = app_dev;
+	app->app_data = app_data;
+	nss_ovpnmgr_debugfs_create(app);
+
+	write_lock_bh(&ovpnmgr_ctx.lock);
+	/*
+	 * Check if the application is already registered.
+	 */
+	if (nss_ovpnmgr_app_find(app_dev)) {
+		write_unlock_bh(&ovpnmgr_ctx.lock);
+		nss_ovpnmgr_info("%px: Application is already registered: app_dev=%s\n", app_dev, app_dev->name);
+		dev_put(app_dev);
+		nss_ovpnmgr_debugfs_remove(app->dentry);
+		kfree(app);
+		return -EEXIST;
+	}
+
+	list_add(&app->list, &ovpnmgr_ctx.app_list);
+	write_unlock_bh(&ovpnmgr_ctx.lock);
+
+	nss_ovpnmgr_info("%px: Application is registered successfully\n", app);
+	return 0;
+}
+EXPORT_SYMBOL(nss_ovpnmgr_app_add);
diff --git a/qca-nss-clients/openvpn/src/nss_ovpnmgr_app.h b/qca-nss-clients/openvpn/src/nss_ovpnmgr_app.h
new file mode 100644
index 0000000..50555a7
--- /dev/null
+++ b/qca-nss-clients/openvpn/src/nss_ovpnmgr_app.h
@@ -0,0 +1,39 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ovpnmgr_app.h
+ */
+#ifndef __NSS_OVPNMGR_APP__H
+#define __NSS_OVPNMGR_APP__H
+
+struct nss_ovpnmgr_tun;
+
+/*
+ * nss_ovpnmgr_app
+ */
+struct nss_ovpnmgr_app {
+	struct list_head list;		/* List node to add into list of application. */
+	struct list_head tun_list;	/* List head to maintain OVPN Tunnels. */
+	enum nss_ovpnmgr_app_mode mode;	/* Application mode - server/client. */
+	struct net_device *dev;		/* TUN/TAP netdevice. */
+	void *app_data;			/* Application data. */
+	struct dentry *dentry;		/* Debugfs entry for OVPN Tunnels created by the application. */
+};
+
+struct nss_ovpnmgr_app *nss_ovpnmgr_app_find(struct net_device *app_dev);
+void nss_ovpnmgr_app_forward(struct nss_ovpnmgr_app *app, struct nss_ovpnmgr_tun *tun, struct sk_buff *skb);
+#endif /* __NSS_OVPNMGR_APP__H */
diff --git a/qca-nss-clients/openvpn/src/nss_ovpnmgr_crypto.c b/qca-nss-clients/openvpn/src/nss_ovpnmgr_crypto.c
new file mode 100644
index 0000000..c953d4d
--- /dev/null
+++ b/qca-nss-clients/openvpn/src/nss_ovpnmgr_crypto.c
@@ -0,0 +1,534 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ovpnmgr_crypto.c
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/if.h>
+#include <linux/crypto.h>
+#include <crypto/algapi.h>
+#include <crypto/aead.h>
+#include <crypto/skcipher.h>
+#include <crypto/aes.h>
+#include <crypto/authenc.h>
+#include <crypto/des.h>
+#include <crypto/sha.h>
+#include <crypto/hash.h>
+
+#include <nss_api_if.h>
+#include <nss_cryptoapi.h>
+#include <nss_qvpn.h>
+#include "nss_ovpnmgr.h"
+#include "nss_ovpnmgr_crypto.h"
+#include "nss_ovpnmgr_tun.h"
+#include "nss_ovpnmgr_app.h"
+#include "nss_ovpnmgr_debugfs.h"
+#include "nss_ovpnmgr_priv.h"
+#include "nss_ovpnmgr_route.h"
+
+/*
+ * Linux aead crypto algorithm names.
+ */
+static const char *nss_ovpnmgr_crypto_algo_name[NSS_OVPNMGR_ALGO_MAX] = {
+	"authenc(hmac(sha1),cbc(aes))",
+	"authenc(hmac(sha256),cbc(aes))",
+	"authenc(hmac(sha1),cbc(des3_ede))",
+	"authenc(hmac(sha256),cbc(des3_ede))",
+	"hmac(sha1)",
+	"hmac(sha256)",
+	"cbc(aes)",
+	"cbc(des3_ede)",
+};
+
+/*
+ * nss_ovpnmgr_config_crypto_key_add()
+ *	Add crypto key.
+ */
+static int nss_ovpnmgr_config_crypto_key_add(struct nss_ovpnmgr_tun_ctx *tun_ctx, struct nss_ovpnmgr_tun *tun)
+{
+	enum nss_qvpn_error_type resp;
+	struct nss_qvpn_msg nqm;
+	struct nss_qvpn_crypto_key_add_msg *key = &nqm.msg.key_add;
+	struct nss_qvpn_crypto_key_activate_msg *key_activate = &nqm.msg.key_activate;
+	nss_tx_status_t status;
+	uint32_t session_id;
+
+	key->crypto_idx = tun_ctx->active.crypto_idx;
+
+	if (tun->tun_cfg.flags & NSS_OVPNMGR_HDR_FLAG_DATA_V2) {
+		session_id = NSS_OVPNMGR_TUN_DATA_V2 << NSS_OVPNMGR_TUN_OPCODE_SHIFT;
+		session_id |= tun_ctx->active.key_id << NSS_OVPNMGR_TUN_KEY_ID_SHIFT;
+		session_id |= tun->tun_cfg.peer_id & NSS_OVPNMGR_TUN_PEER_ID_MASK;
+		session_id = htonl(session_id);
+	} else {
+		session_id = NSS_OVPNMGR_TUN_DATA_V1 << NSS_OVPNMGR_TUN_OPCODE_SHIFT;
+		session_id |= tun_ctx->active.key_id;
+	}
+
+	memcpy(key->session_id, &session_id, sizeof(session_id));
+
+	nss_ovpnmgr_info("%px: Active key: session=%d, key_id=%d, crypto_blk_size = %d, hmac_len = %d, iv_len = %d\n",
+			tun_ctx, tun_ctx->active.crypto_idx, tun_ctx->active.key_id,
+			tun_ctx->active.blk_len, tun_ctx->active.hash_len, tun_ctx->active.iv_len);
+
+	status = nss_qvpn_tx_msg_sync(tun_ctx->nss_ctx,  &nqm, tun_ctx->ifnum, NSS_QVPN_MSG_TYPE_CRYPTO_KEY_ADD,
+					sizeof(*key), &resp);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ovpnmgr_warn("%px: failed to add crypto key, resp = %d, status = %d\n", tun_ctx, resp, status);
+		return status == NSS_TX_FAILURE_QUEUE ? -EBUSY : -EINVAL;
+	}
+
+	/* Send key activate message. */
+	memset(&nqm, 0, sizeof(nqm));
+	key_activate->crypto_idx = tun_ctx->active.crypto_idx;
+	memcpy(key_activate->vpn_hdr_head, &session_id, sizeof(session_id));
+
+	status = nss_qvpn_tx_msg_sync(tun_ctx->nss_ctx,  &nqm, tun_ctx->ifnum, NSS_QVPN_MSG_TYPE_CRYPTO_KEY_ACTIVATE,
+					sizeof(*key_activate), &resp);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ovpnmgr_warn("%px: failed to activate crypto key, resp = %d, status = %d\n", tun_ctx, resp, status);
+		return status == NSS_TX_FAILURE_QUEUE ? -EBUSY : -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ovpnmgr_config_crypto_key_del()
+ *	Delete crypto key.
+ */
+static int nss_ovpnmgr_config_crypto_key_del(struct nss_ovpnmgr_tun_ctx *tun_ctx)
+{
+	enum nss_qvpn_error_type resp;
+	struct nss_qvpn_msg nqm;
+	nss_tx_status_t status;
+
+	/* Send key deactivate message. */
+	nqm.msg.key_del.crypto_idx = tun_ctx->expiring.crypto_idx;
+
+	nss_ovpnmgr_info("%px: Expiring key: session=%d, key_id=%d, crypto_blk_size = %d, hmac_len = %d, iv_len = %d\n",
+			tun_ctx, tun_ctx->expiring.crypto_idx, tun_ctx->expiring.key_id,
+			tun_ctx->expiring.blk_len, tun_ctx->expiring.hash_len, tun_ctx->expiring.iv_len);
+
+	status = nss_qvpn_tx_msg_sync(tun_ctx->nss_ctx,  &nqm, tun_ctx->ifnum, NSS_QVPN_MSG_TYPE_CRYPTO_KEY_DEACTIVATE,
+			sizeof(nqm.msg.key_del), &resp);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ovpnmgr_warn("%px: failed to deactivate crypto key, resp = %d, status = %d\n", tun_ctx, resp, status);
+		return status == NSS_TX_FAILURE_QUEUE ? -EBUSY : -EINVAL;
+	}
+
+	status = nss_qvpn_tx_msg_sync(tun_ctx->nss_ctx,  &nqm, tun_ctx->ifnum, NSS_QVPN_MSG_TYPE_CRYPTO_KEY_DEL,
+			sizeof(nqm.msg.key_del), &resp);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ovpnmgr_warn("%px: failed to delete crypto key, resp = %d, status = %d\n", tun_ctx, resp, status);
+		return status == NSS_TX_FAILURE_QUEUE ? -EBUSY : -EINVAL;
+	}
+	return 0;
+}
+
+/*
+ * nss_ovpnmgr_crypto_ctx_alloc_aead()
+ *	Creates AEAD crypto context.
+ */
+static int nss_ovpnmgr_crypto_ctx_alloc_aead(struct nss_ovpnmgr_crypto_ctx *ctx,
+					struct nss_ovpnmgr_crypto_config *params,
+					struct nss_ovpnmgr_crypto_key *key)
+{
+	struct crypto_authenc_key_param *key_param;
+	enum nss_ovpnmgr_algo algo = params->algo;
+	struct rtattr *rta;
+	uint32_t session, keylen;
+	char *keys, *p;
+	int res;
+
+	nss_ovpnmgr_info("%px: Registering AEAD alg %s\n", ctx, nss_ovpnmgr_crypto_algo_name[algo]);
+
+	ctx->tfm.aead = crypto_alloc_aead(nss_ovpnmgr_crypto_algo_name[algo], 0, 0);
+	if (IS_ERR(ctx->tfm.aead)) {
+		res = PTR_ERR(ctx->tfm.aead);
+		nss_ovpnmgr_warn("%px: failed to allocate crypto aead context, res=%d\n", ctx, res);
+		return -ENOENT;
+	}
+
+	/*
+	 * Construct keys
+	 */
+	keylen = RTA_SPACE(sizeof(*key_param));
+	keylen += key->cipher_keylen;
+	keylen += key->hmac_keylen;
+
+	keys = vzalloc(keylen);
+	if (!keys) {
+		nss_ovpnmgr_warn("%px: failed to allocate key memory", ctx);
+		crypto_free_aead(ctx->tfm.aead);
+		return -ENOMEM;
+	}
+
+	p = keys;
+	rta = (void *)p;
+	rta->rta_type = CRYPTO_AUTHENC_KEYA_PARAM;
+	rta->rta_len = RTA_LENGTH(sizeof(*key_param));
+	key_param = RTA_DATA(rta);
+	p += RTA_SPACE(sizeof(*key_param));
+
+	/*
+	 * Copy authentication key
+	 */
+	memcpy(p, key->hmac_key, key->hmac_keylen);
+	p += key->hmac_keylen;
+
+	/*
+	 * Copy cipher Key
+	 */
+	key_param->enckeylen = cpu_to_be32(key->cipher_keylen);
+	memcpy(p, key->cipher_key, key->cipher_keylen);
+
+	res = crypto_aead_setkey(ctx->tfm.aead, keys, keylen);
+	if (res) {
+		nss_ovpnmgr_warn("%px: failed to configure keys, res=%d\n", ctx, res);
+		vfree(keys);
+		crypto_free_aead(ctx->tfm.aead);
+		return -EKEYREJECTED;
+	}
+
+	nss_cryptoapi_aead_ctx2session(ctx->tfm.aead, &session);
+
+	ctx->crypto_type = NSS_OVPNMGR_CRYPTO_TYPE_AEAD;
+	ctx->blk_len = (uint8_t)crypto_aead_blocksize(ctx->tfm.aead);
+	ctx->hash_len = (uint8_t)crypto_aead_authsize(ctx->tfm.aead);
+	ctx->iv_len = (uint8_t)crypto_aead_ivsize(ctx->tfm.aead);
+	ctx->crypto_idx = (uint16_t)session;
+
+	nss_ovpnmgr_info("%px: blk_len=%u, hash_len=%u, iv_len=%u, session=%d\n",
+			ctx, ctx->blk_len, ctx->hash_len, ctx->iv_len, session);
+
+	vfree(keys);
+	return 0;
+}
+
+/*
+ * nss_ovpnmgr_crypto_ctx_alloc_ablk()
+ *	Creates ABLK crypto context.
+ */
+static int nss_ovpnmgr_crypto_ctx_alloc_ablk(struct nss_ovpnmgr_crypto_ctx *ctx,
+		struct nss_ovpnmgr_crypto_config *params,
+		struct nss_ovpnmgr_crypto_key *key)
+{
+	struct crypto_skcipher *skcipher;
+	enum nss_ovpnmgr_algo algo = params->algo;
+	uint32_t session;
+	int res;
+
+	nss_ovpnmgr_info("%px: Registering ABLK alg %s\n", ctx, nss_ovpnmgr_crypto_algo_name[algo]);
+
+	skcipher = crypto_alloc_skcipher(nss_ovpnmgr_crypto_algo_name[algo], 0, 0);
+	if (IS_ERR(skcipher)) {
+		res = PTR_ERR(skcipher);
+		nss_ovpnmgr_warn("%px: failed to allocate crypto aead context, res = %d\n", ctx, res);
+		return -ENOENT;
+	}
+
+	res = crypto_skcipher_setkey(skcipher, key->cipher_key, key->cipher_keylen);
+	if (res) {
+		nss_ovpnmgr_warn("%px: failed to set skcipher key, res=%d", ctx, res);
+		crypto_free_skcipher(skcipher);
+		return -EKEYREJECTED;
+	}
+
+	nss_cryptoapi_skcipher_ctx2session(skcipher, &session);
+
+	ctx->crypto_type = NSS_OVPNMGR_CRYPTO_TYPE_ABLK;
+	ctx->blk_len = (uint8_t)crypto_skcipher_blocksize(skcipher);
+	ctx->iv_len = (uint8_t)crypto_skcipher_ivsize(skcipher);
+	ctx->tfm.skcipher = skcipher;
+	ctx->crypto_idx = (uint16_t)session;
+
+	nss_ovpnmgr_info("%px: skcipher Registered: blk_len=%u, iv_len=%u, session=%u\n",
+			ctx, ctx->blk_len, ctx->iv_len, session);
+	return 0;
+}
+
+/*
+ * nss_ovpnmgr_crypto_ctx_alloc_ahash()
+ *	Creates ABLK crypto context.
+ */
+static int nss_ovpnmgr_crypto_ctx_alloc_ahash(struct nss_ovpnmgr_crypto_ctx *ctx,
+		struct nss_ovpnmgr_crypto_config *params,
+		struct nss_ovpnmgr_crypto_key *key)
+{
+	enum nss_ovpnmgr_algo algo = params->algo;
+	struct crypto_ahash *ahash;
+	uint32_t session;
+	int res;
+
+	nss_ovpnmgr_info("%px: Registering AHASH alg %s\n", ctx, nss_ovpnmgr_crypto_algo_name[algo]);
+
+	ahash = crypto_alloc_ahash(nss_ovpnmgr_crypto_algo_name[algo], 0, 0);
+	if (IS_ERR(ahash)) {
+		res = PTR_ERR(ahash);
+		nss_ovpnmgr_warn("%px: failed to allocate ahash context, res = %d", ctx, res);
+		return -ENOENT;
+	}
+
+	res = crypto_ahash_setkey(ahash, key->hmac_key, key->hmac_keylen);
+	if (res) {
+		nss_ovpnmgr_warn("%px: failed to set ahash key, res=%d", ctx, res);
+		crypto_free_ahash(ahash);
+		return -EKEYREJECTED;
+	}
+
+	nss_cryptoapi_ahash_ctx2session(ahash, &session);
+
+	ctx->crypto_type = NSS_OVPNMGR_CRYPTO_TYPE_AHASH;
+	ctx->tfm.ahash = ahash;
+	ctx->hash_len = crypto_ahash_digestsize(ahash);
+	ctx->crypto_idx = (uint16_t)session;
+
+	nss_ovpnmgr_info("%px: AHASH Registered: hash_len=%u, session=%u\n", ctx, ctx->hash_len, session);
+	return 0;
+}
+
+/*
+ * nss_ovpnmgr_crypto_ctx_free()
+ *	Unregisters crypto context.
+ */
+void nss_ovpnmgr_crypto_ctx_free(struct nss_ovpnmgr_crypto_ctx *ctx)
+{
+	switch (ctx->crypto_type) {
+	case NSS_OVPNMGR_CRYPTO_TYPE_AEAD:
+		crypto_free_aead(ctx->tfm.aead);
+		ctx->tfm.aead = NULL;
+		break;
+	case NSS_OVPNMGR_CRYPTO_TYPE_ABLK:
+		crypto_free_skcipher(ctx->tfm.skcipher);
+		ctx->tfm.skcipher = NULL;
+		break;
+	case NSS_OVPNMGR_CRYPTO_TYPE_AHASH:
+		crypto_free_ahash(ctx->tfm.ahash);
+		ctx->tfm.ahash = NULL;
+		break;
+	}
+}
+
+/*
+ * nss_ovpnmgr_crypto_ctx_alloc()
+ *	Registers crypto context based on crypto_type.
+ */
+int nss_ovpnmgr_crypto_ctx_alloc(struct nss_ovpnmgr_crypto_ctx *ctx,
+				struct nss_ovpnmgr_crypto_config *params,
+				struct nss_ovpnmgr_crypto_key *key)
+{
+	switch (params->algo) {
+	/* AEAD */
+	case NSS_OVPNMGR_ALGO_AES_CBC_SHA1_HMAC:
+	case NSS_OVPNMGR_ALGO_AES_CBC_SHA256_HMAC:
+	case NSS_OVPNMGR_ALGO_3DES_CBC_SHA1_HMAC:
+	case NSS_OVPNMGR_ALGO_3DES_CBC_SHA256_HMAC:
+		return nss_ovpnmgr_crypto_ctx_alloc_aead(ctx, params, key);
+	/* AHASH */
+	case NSS_OVPNMGR_ALGO_NULL_CIPHER_SHA1_HMAC:
+	case NSS_OVPNMGR_ALGO_NULL_CIPHER_SHA256_HMAC:
+		return nss_ovpnmgr_crypto_ctx_alloc_ahash(ctx, params, key);
+	/* ABLK */
+	case NSS_OVPNMGR_ALGO_AES_CBC_NULL_AUTH:
+	case NSS_OVPNMGR_ALGO_3DES_CBC_NULL_AUTH:
+		return nss_ovpnmgr_crypto_ctx_alloc_ablk(ctx, params, key);
+	case NSS_OVPNMGR_ALGO_NULL_CIPHER_NULL_AUTH:
+		nss_ovpnmgr_info("%px: Cipher is none. Auth is none\n", ctx);
+		ctx->tfm.aead = NULL;
+		ctx->crypto_idx = U16_MAX;
+		break;
+	default:
+		nss_ovpnmgr_info("%px: Crypto algorithm is invalid. algo=%d\n", ctx, params->algo);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ovpnmgr_crypto_key_del()
+ *	Delete crypto keys.
+ */
+int nss_ovpnmgr_crypto_key_del(uint32_t tunnel_id)
+{
+	struct nss_ovpnmgr_crypto_ctx *ctx_inner;
+	struct nss_ovpnmgr_crypto_ctx *ctx_outer;
+	struct nss_ovpnmgr_tun *tun;
+	struct net_device *tun_dev;
+
+	tun_dev = dev_get_by_index(&init_net, tunnel_id);
+	if (!tun_dev) {
+		nss_ovpnmgr_warn("Couldn't find tunnel: tunnel_id = %u\n\n", tunnel_id);
+		return -EINVAL;
+	}
+
+	tun = netdev_priv(tun_dev);
+
+	write_lock_bh(&ovpnmgr_ctx.lock);
+	ctx_inner = &tun->inner.expiring;
+	if (!ctx_inner->tfm.aead) {
+		/*
+		 * Expiring key is not valid, return.
+		 */
+		write_unlock_bh(&ovpnmgr_ctx.lock);
+		dev_put(tun_dev);
+		return -EINVAL;
+	}
+
+	ctx_outer = &tun->outer.expiring;
+	if (unlikely(!ctx_outer->tfm.aead)) {
+		/*
+		 * Expiring key is not valid, return.
+		 */
+		write_unlock_bh(&ovpnmgr_ctx.lock);
+		dev_put(tun_dev);
+		return -EINVAL;
+	}
+
+	write_unlock_bh(&ovpnmgr_ctx.lock);
+
+	/*
+	 * When crypto key delete request is received, it is always
+	 * expiring key that is deleted.  Active key is deleted only during
+	 * tunnel delete request.
+	 */
+
+	/*
+	 * Deregister Encryption
+	 */
+	nss_ovpnmgr_crypto_ctx_free(ctx_inner);
+
+	/* Send Crypto Key delete message to NSS firmware. */
+	if (nss_ovpnmgr_config_crypto_key_del(&tun->inner)) {
+		nss_ovpnmgr_warn("%px: Failed to update crypto key\n", ctx_inner);
+	}
+
+	/* Deregister Decryption */
+	nss_ovpnmgr_crypto_ctx_free(ctx_outer);
+
+	/* Send Crypto Key delete message to NSS firmware. */
+	if (nss_ovpnmgr_config_crypto_key_del(&tun->outer)) {
+		nss_ovpnmgr_warn("%px: Failed to update crypto key\n", ctx_outer);
+	}
+
+	dev_put(tun_dev);
+	return 0;
+}
+EXPORT_SYMBOL(nss_ovpnmgr_crypto_key_del);
+
+/*
+ * nss_ovpnmgr_crypto_key_add()
+ *	Add crypto key.
+ */
+int nss_ovpnmgr_crypto_key_add(uint32_t tunnel_id, uint8_t key_id, struct nss_ovpnmgr_crypto_config *cfg)
+{
+	struct nss_ovpnmgr_crypto_ctx encrypt;
+	struct nss_ovpnmgr_crypto_ctx decrypt;
+	struct nss_ovpnmgr_tun *tun;
+	struct net_device *tun_dev;
+	int ret;
+
+	tun_dev = dev_get_by_index(&init_net, tunnel_id);
+	if (!tun_dev) {
+		nss_ovpnmgr_warn("Couldn't find tunnel: tunnel_id = %u\n\n", tunnel_id);
+		return -EINVAL;
+	}
+
+	tun = netdev_priv(tun_dev);
+
+	/*
+	 * Check if crypto keys are negotiated during rekey.
+	 * Otherwise crypto context is allocated when tunnel is added
+	 */
+	if (key_id) {
+		/* Register Encryption */
+		ret = nss_ovpnmgr_crypto_ctx_alloc(&encrypt, cfg, &cfg->encrypt);
+		if (ret) {
+			nss_ovpnmgr_warn("%px: Failed to register Encryption session\n", tun);
+			dev_put(tun_dev);
+			return ret;
+		}
+
+		/* Register Decryption */
+		ret = nss_ovpnmgr_crypto_ctx_alloc(&decrypt, cfg, &cfg->decrypt);
+		if (ret) {
+			/* Deregister Encryption here */
+			nss_ovpnmgr_warn("%px: Failed to register Decryption session\n", tun);
+			goto free_encrypt;
+		}
+
+		encrypt.key_id = key_id;
+		decrypt.key_id = key_id;
+
+		read_lock_bh(&ovpnmgr_ctx.lock);
+		/* copy old active key into expiring key */
+		memcpy(&tun->inner.expiring, &tun->inner.active, sizeof(tun->inner.active));
+		memcpy(&tun->outer.expiring, &tun->outer.active, sizeof(tun->outer.active));
+
+		/* copy the new key as active key */
+		memcpy(&tun->inner.active, &encrypt, sizeof(encrypt));
+		memcpy(&tun->outer.active, &decrypt, sizeof(decrypt));
+		read_unlock_bh(&ovpnmgr_ctx.lock);
+	} else {
+		/*
+		 * Initial crypto context is created during tunnel configuration.
+		 * copy crypto context for processing.
+		 * We will explicitly reset expiring key to 0.
+		 */
+		read_lock_bh(&ovpnmgr_ctx.lock);
+		memset(&tun->inner.expiring, 0, sizeof(tun->inner.expiring));
+		memset(&tun->outer.expiring, 0, sizeof(tun->outer.expiring));
+
+		memcpy(&encrypt, &tun->inner.active, sizeof(encrypt));
+		memcpy(&decrypt, &tun->outer.active, sizeof(decrypt));
+		read_unlock_bh(&ovpnmgr_ctx.lock);
+	}
+
+	/*
+	 * Send crypto key addition command to inner node.
+	 */
+	if (nss_ovpnmgr_config_crypto_key_add(&tun->inner, tun)) {
+		nss_ovpnmgr_warn("%px: Failed to update inner crypto key\n", tun);
+		ret = -EIO;
+		goto free_decrypt;
+	}
+
+	/*
+	 * Send crypto key addition command to outer node.
+	 */
+	if (nss_ovpnmgr_config_crypto_key_add(&tun->outer, tun)) {
+		nss_ovpnmgr_warn("%px: Failed to update outer crypto key\n", tun);
+		ret = -EIO;
+		goto free_decrypt;
+	}
+
+	dev_put(tun_dev);
+	return 0;
+
+free_decrypt:
+	nss_ovpnmgr_crypto_ctx_free(&decrypt);
+
+free_encrypt:
+	nss_ovpnmgr_crypto_ctx_free(&encrypt);
+
+	dev_put(tun_dev);
+	return ret;
+}
+EXPORT_SYMBOL(nss_ovpnmgr_crypto_key_add);
diff --git a/qca-nss-clients/openvpn/src/nss_ovpnmgr_crypto.h b/qca-nss-clients/openvpn/src/nss_ovpnmgr_crypto.h
new file mode 100644
index 0000000..953e31c
--- /dev/null
+++ b/qca-nss-clients/openvpn/src/nss_ovpnmgr_crypto.h
@@ -0,0 +1,64 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ovpnmgr_crypto.h
+ */
+#ifndef __NSS_OVPNMGR_CRYPTO__H
+#define __NSS_OVPNMGR_CRYPTO__H
+
+#define NSS_OVPNMGR_CRYPTO_INVALID_KEY_ID 0xff
+
+/*
+ * Crypto key types.
+ */
+enum nss_ovpnmgr_crypto_key_type {
+	NSS_OVPNMGR_CRYPTO_KEY_TYPE_INITIAL,	/* Initial key which becomes active during tunnel addition. */
+	NSS_OVPNMGR_CRYPTO_KEY_TYPE_CURRENT,	/* Current key. */
+	NSS_OVPNMGR_CRYPTO_KEY_TYPE_EXPIRING	/* Key about to expire. */
+};
+
+/*
+ * NSS OVPN manager supported crypto algorithms
+ */
+enum nss_ovpnmgr_crypto_type {
+	NSS_OVPNMGR_CRYPTO_TYPE_AEAD = 1,	/* Crypto type AEAD */
+	NSS_OVPNMGR_CRYPTO_TYPE_ABLK,		/* Crypto type ABLK */
+	NSS_OVPNMGR_CRYPTO_TYPE_AHASH		/* Crypto type AHASH */
+};
+
+/*
+ * nss_ovpnmgr_crypto_ctx
+ */
+struct nss_ovpnmgr_crypto_ctx {
+	uint8_t blk_len;				/* Cipher block length. */
+	uint8_t hash_len;				/* Hash length. */
+	uint8_t iv_len;					/* IV length. */
+	uint8_t key_id;					/* Crypto key id. */
+	uint16_t crypto_idx;				/* Crypto Session Index. */
+
+	enum nss_ovpnmgr_crypto_type crypto_type;	/* Crypto type. */
+	union {
+		struct crypto_aead *aead;		/* Cipher + Hash */
+		struct crypto_skcipher *skcipher;	/* Cipher Only */
+		struct crypto_ahash *ahash;		/* Hash Only */
+	} tfm;
+};
+
+int nss_ovpnmgr_crypto_ctx_alloc(struct nss_ovpnmgr_crypto_ctx *ctx,
+		struct nss_ovpnmgr_crypto_config *cfg, struct nss_ovpnmgr_crypto_key *key);
+void nss_ovpnmgr_crypto_ctx_free(struct nss_ovpnmgr_crypto_ctx *crypto_ctx);
+#endif /* __NSS_OVPNMGR_CRYPTO__H */
diff --git a/qca-nss-clients/openvpn/src/nss_ovpnmgr_debugfs.c b/qca-nss-clients/openvpn/src/nss_ovpnmgr_debugfs.c
new file mode 100644
index 0000000..04e76c2
--- /dev/null
+++ b/qca-nss-clients/openvpn/src/nss_ovpnmgr_debugfs.c
@@ -0,0 +1,220 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ovpnmgr_debugfs.c
+ *	Debugfs implementation for OVPN.
+ */
+#include <linux/debugfs.h>
+#include <linux/crypto.h>
+#include <linux/list.h>
+#include <linux/proc_fs.h>
+
+#include <nss_api_if.h>
+#include <nss_qvpn.h>
+#include "nss_ovpnmgr.h"
+#include "nss_ovpnmgr_crypto.h"
+#include "nss_ovpnmgr_tun.h"
+#include "nss_ovpnmgr_app.h"
+#include "nss_ovpnmgr_debugfs.h"
+#include "nss_ovpnmgr_priv.h"
+#include "nss_ovpnmgr_route.h"
+
+/*
+ * nss_ovpnmgr_debugfs_tun_info_show()
+ */
+static void nss_ovpnmgr_debugfs_tun_info_show(struct nss_ovpnmgr_tun *tun, struct seq_file *m)
+{
+	int i;
+
+	seq_printf(m, "\tTunnel ID: %u\n", tun->tunnel_id);
+	seq_printf(m, "\t\tNetdev: %s\n", tun->dev->name);
+	seq_printf(m, "\t\tEncap ifnum: %u\n", tun->inner.ifnum);
+	seq_printf(m, "\t\tDecap ifnum: %u\n", tun->outer.ifnum);
+	seq_printf(m, "\t\tOVPN Flags: %x\n", tun->tun_cfg.flags);
+
+	if (tun->tun_cfg.flags & NSS_OVPNMGR_HDR_FLAG_IPV6) {
+		seq_printf(m, "\t\tSrc IP: %pI6c\n", &tun->tun_hdr.src_ip[0]);
+		seq_printf(m, "\t\tDst IP: %pI6c\n", &tun->tun_hdr.dst_ip[0]);
+	} else {
+		seq_printf(m, "\t\tSrc IP: %pI4n\n", &tun->tun_hdr.src_ip[0]);
+		seq_printf(m, "\t\tDst IP: %pI4n\n", &tun->tun_hdr.dst_ip[0]);
+	}
+
+	if (!(tun->tun_cfg.flags & NSS_OVPNMGR_HDR_FLAG_L4_PROTO_TCP)) {
+		seq_printf(m, "\t\tL4 Protocol: UDP\n");
+	}
+
+	seq_printf(m, "\t\tSrc Port: %u\n", ntohs(tun->tun_hdr.src_port));
+	seq_printf(m, "\t\tDst Port: %u\n", ntohs(tun->tun_hdr.dst_port));
+	seq_printf(m, "\t\tCrypto Session: (Inner)\n");
+	seq_printf(m, "\t\t\tActive: \n");
+	seq_printf(m, "\t\t\t\tIndex: %u\n", tun->inner.active.crypto_idx);
+	seq_printf(m, "\t\t\t\tKeyId: %u\n", tun->inner.active.key_id);
+	seq_printf(m, "\t\t\tExpiring: \n");
+	seq_printf(m, "\t\t\t\tIndex: %u\n", tun->inner.expiring.crypto_idx);
+	seq_printf(m, "\t\t\t\tKeyId: %u\n", tun->inner.expiring.key_id);
+	seq_printf(m, "\t\tCrypto Session: (Outer)\n");
+	seq_printf(m, "\t\t\tActive: \n");
+	seq_printf(m, "\t\t\t\tIndex: %u\n", tun->outer.active.crypto_idx);
+	seq_printf(m, "\t\t\t\tKeyId: %u\n", tun->outer.active.key_id);
+	seq_printf(m, "\t\t\tExpiring: \n");
+	seq_printf(m, "\t\t\t\tIndex: %u\n", tun->outer.expiring.crypto_idx);
+	seq_printf(m, "\t\t\t\tKeyId: %u\n", tun->outer.expiring.key_id);
+
+	seq_puts(m, "\tStatistics:\n\t\tEncap:\n");
+
+	seq_printf(m, "\t\t\trx_packets: %llu\n", tun->inner.stats.rx_packets);
+	seq_printf(m, "\t\t\trx_bytes: %llu\n", tun->inner.stats.rx_bytes);
+	seq_printf(m, "\t\t\ttx_packets: %llu\n", tun->inner.stats.tx_packets);
+	seq_printf(m, "\t\t\ttx_bytes: %llu\n", tun->inner.stats.tx_bytes);
+
+	for (i = 0 ; i < NSS_MAX_NUM_PRI; i++) {
+		seq_printf(m, "\t\t\trx_queue_%d_dropped: %llu\n", i, tun->inner.stats.rx_dropped[i]);
+	}
+
+	for (i = 0; i < NSS_CRYPTO_CMN_RESP_ERROR_MAX; i++) {
+		seq_printf(m, "\t\t\tfail_crypto[%d]: %llu\n", i, tun->inner.stats.fail_crypto[i]);
+	}
+
+	for (i = 0; i < NSS_QVPN_PKT_DROP_EVENT_MAX; i++) {
+		seq_printf(m, "\t\t\tfail_offload[%d]: %llu\n", i, tun->inner.stats.fail_offload[i]);
+	}
+
+	seq_printf(m, "\t\t\thost_pkt_drops: %llu\n", tun->inner.stats.host_pkt_drop);
+
+	for (i = 0; i < NSS_QVPN_EXCEPTION_EVENT_MAX; i++) {
+		seq_printf(m, "\t\t\texception[%d]: %llu\n", i, tun->inner.stats.exception[i]);
+	}
+
+	seq_puts(m, "\t\tDecap:\n");
+
+	seq_printf(m, "\t\t\trx_packets: %llu\n", tun->outer.stats.rx_packets);
+	seq_printf(m, "\t\t\trx_bytes: %llu\n", tun->outer.stats.rx_bytes);
+	seq_printf(m, "\t\t\ttx_packets: %llu\n", tun->outer.stats.tx_packets);
+	seq_printf(m, "\t\t\ttx_bytes: %llu\n", tun->outer.stats.tx_bytes);
+
+	for (i = 0 ; i < NSS_MAX_NUM_PRI; i++) {
+		seq_printf(m, "\t\t\trx_queue_%d_dropped: %llu\n", i, tun->outer.stats.rx_dropped[i]);
+	}
+
+	for (i = 0; i < NSS_CRYPTO_CMN_RESP_ERROR_MAX; i++) {
+		seq_printf(m, "\t\t\tfail_crypto[%d]: %llu\n", i, tun->outer.stats.fail_crypto[i]);
+	}
+
+	for (i = 0; i < NSS_QVPN_PKT_DROP_EVENT_MAX; i++) {
+		seq_printf(m, "\t\t\tfail_offload[%d]: %llu\n", i, tun->outer.stats.fail_offload[i]);
+	}
+
+	seq_printf(m, "\t\t\thost_pkt_drops: %llu\n", tun->outer.stats.host_pkt_drop);
+
+	for (i = 0; i < NSS_QVPN_EXCEPTION_EVENT_MAX; i++) {
+		seq_printf(m, "\t\t\texception[%d]: %llu\n", i, tun->outer.stats.exception[i]);
+	}
+
+	seq_putc(m, '\n');
+}
+
+/*
+ * nss_ovpnmgr_debugfs_tun_list_show()
+ */
+static int nss_ovpnmgr_debugfs_tun_list_show(struct seq_file *m, void *p)
+{
+	struct nss_ovpnmgr_app *app = m->private;
+	struct nss_ovpnmgr_tun *tun;
+
+	read_lock_bh(&ovpnmgr_ctx.lock);
+
+	list_for_each_entry(tun, &app->tun_list, list) {
+		nss_ovpnmgr_debugfs_tun_info_show(tun, m);
+	}
+
+	read_unlock_bh(&ovpnmgr_ctx.lock);
+	return 0;
+}
+
+/*
+ * nss_ovpnmgr_debugfs_tun_list_open()
+ */
+static int nss_ovpnmgr_debugfs_tun_list_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, nss_ovpnmgr_debugfs_tun_list_show, inode->i_private);
+}
+
+/*
+ * tun file operation structure instance
+ */
+static const struct file_operations tun_list_op = {
+	.open = nss_ovpnmgr_debugfs_tun_list_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = seq_release
+};
+
+/*
+ * nss_ovpnmgr_debugfs_init()
+ *	Initialize the debugfs tree.
+ */
+int nss_ovpnmgr_debugfs_init(void)
+{
+	/*
+	 * initialize debugfs.
+	 */
+	ovpnmgr_ctx.dentry = debugfs_create_dir("qca-nss-ovpnmgr", NULL);
+	if (!ovpnmgr_ctx.dentry) {
+		nss_ovpnmgr_warn("Creating debug directory failed\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ovpnmgr_debugfs_create()
+ *	Create debufs file for registered OVPN application.
+ */
+void nss_ovpnmgr_debugfs_create(struct nss_ovpnmgr_app *app)
+{
+	char dentry_name[NSS_OVPNMGR_DEBUGFS_MAX_NAME_SIZE];
+
+	scnprintf(dentry_name, sizeof(dentry_name), "ovpn_app_%s", app->dev->name);
+
+	/*
+	 * Create debugfs entries for SA, flow and subnet
+	 */
+	app->dentry = debugfs_create_file(dentry_name, S_IRUGO, ovpnmgr_ctx.dentry, app, &tun_list_op);
+	if (!app->dentry) {
+		nss_ovpnmgr_warn("Debugfs file creation failed for tun\n");
+	}
+}
+
+/*
+ * nss_ovpnmgr_debugfs_remove()
+ *	Remove debufs file for registered OVPN application.
+ */
+void nss_ovpnmgr_debugfs_remove(struct dentry *dentry)
+{
+	debugfs_remove(dentry);
+}
+
+/*
+ * nss_ovpnmgr_debugfs_cleanup()
+ *	Cleanup the debugfs tree.
+ */
+void nss_ovpnmgr_debugfs_cleanup(void)
+{
+	debugfs_remove_recursive(ovpnmgr_ctx.dentry);
+}
diff --git a/qca-nss-clients/openvpn/src/nss_ovpnmgr_debugfs.h b/qca-nss-clients/openvpn/src/nss_ovpnmgr_debugfs.h
new file mode 100644
index 0000000..695405b
--- /dev/null
+++ b/qca-nss-clients/openvpn/src/nss_ovpnmgr_debugfs.h
@@ -0,0 +1,29 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ovpnmgr_debugfs.h
+ */
+#ifndef __NSS_OVPNMGR_DEBUGFS__H
+#define __NSS_OVPNMGR_DEBUGFS__H
+
+#define NSS_OVPNMGR_DEBUGFS_MAX_NAME_SIZE 30
+
+int nss_ovpnmgr_debugfs_init(void);
+void nss_ovpnmgr_debugfs_create(struct nss_ovpnmgr_app *app);
+void nss_ovpnmgr_debugfs_remove(struct dentry *app_dentry);
+void nss_ovpnmgr_debugfs_cleanup(void);
+#endif /* __NSS_OVPNMGR_DEBUGFS__H */
diff --git a/qca-nss-clients/openvpn/src/nss_ovpnmgr_priv.h b/qca-nss-clients/openvpn/src/nss_ovpnmgr_priv.h
new file mode 100644
index 0000000..12b06fa
--- /dev/null
+++ b/qca-nss-clients/openvpn/src/nss_ovpnmgr_priv.h
@@ -0,0 +1,81 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ovpnmgr_priv.h
+ */
+#ifndef __NSS_OVPNMGR_PRIV__H
+#define __NSS_OVPNMGR_PRIV__H
+
+#define NSS_OVPNMGR_DEBUG_LVL_ERROR 1		/* Turn on debug for an error. */
+#define NSS_OVPNMGR_DEBUG_LVL_WARN 2		/* Turn on debug for a warning. */
+#define NSS_OVPNMGR_DEBUG_LVL_INFO 3		/* Turn on debug for information. */
+#define NSS_OVPNMGR_DEBUG_LVL_TRACE 4		/* Turn on debug for trace. */
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_ovpnmgr_error(s, ...) do { \
+	if (net_ratelimit()) {  \
+		pr_alert("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);  \
+	} \
+} while (0)
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_ovpnmgr_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_ovpnmgr_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_ovpnmgr_warn(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+#else
+/*
+ * Statically compile messages at different levels
+ */
+#define nss_ovpnmgr_info(s, ...) {     \
+	if (NSS_OVPNMGR_DEBUG_LEVEL > NSS_OVPNMGR_DEBUG_LVL_INFO) {   \
+		pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__); \
+	} \
+}
+#define nss_ovpnmgr_trace(s, ...) {    \
+	if (NSS_OVPNMGR_DEBUG_LEVEL > NSS_OVPNMGR_DEBUG_LVL_TRACE) {  \
+		pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);   \
+	} \
+}
+#define nss_ovpnmgr_warn(s, ...) {    \
+	if (NSS_OVPNMGR_DEBUG_LEVEL > NSS_OVPNMGR_DEBUG_LVL_WARN) {  \
+		pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);   \
+	} \
+}
+#endif /* !CONFIG_DYNAMIC_DEBUG */
+
+/*
+ * OVPN manager context structure
+ */
+extern struct nss_ovpnmgr_context ovpnmgr_ctx;
+
+/*
+ * nss_ovpnmgr_context
+ *	OVPN manager context structure
+ */
+struct nss_ovpnmgr_context {
+	struct dentry *dentry;		/* Debugfs entry for OVPN Tunnels. */
+	struct list_head app_list;	/* List of OVPN application instances */
+	rwlock_t lock;			/* Lock to protect Application List */
+};
+
+#endif /* __NSS_OVPNMGR_PRIV__H */
diff --git a/qca-nss-clients/openvpn/src/nss_ovpnmgr_route.c b/qca-nss-clients/openvpn/src/nss_ovpnmgr_route.c
new file mode 100644
index 0000000..09ae181
--- /dev/null
+++ b/qca-nss-clients/openvpn/src/nss_ovpnmgr_route.c
@@ -0,0 +1,235 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ovpnmgr_route.c
+ */
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/if_tun.h>
+#include <linux/ip.h>
+#include <net/ip.h>
+#include <net/udp.h>
+#include <net/ip6_checksum.h>
+#include <linux/ipv6.h>
+#include <linux/crypto.h>
+#include <crypto/algapi.h>
+#include <crypto/aead.h>
+#include <crypto/skcipher.h>
+#include <crypto/aes.h>
+#include <crypto/authenc.h>
+#include <crypto/des.h>
+#include <crypto/sha.h>
+#include <crypto/hash.h>
+
+#include <nss_api_if.h>
+#include <nss_cryptoapi.h>
+#include <nss_qvpn.h>
+#include <nss_ovpnmgr.h>
+#include "nss_ovpnmgr_crypto.h"
+#include "nss_ovpnmgr_tun.h"
+#include "nss_ovpnmgr_app.h"
+#include "nss_ovpnmgr_debugfs.h"
+#include "nss_ovpnmgr_priv.h"
+#include "nss_ovpnmgr_route.h"
+
+/*
+ * nss_ovpnmgr_route_find()
+ *	Return route for the given tunnel and address
+ */
+struct nss_ovpnmgr_route *nss_ovpnmgr_route_find(struct list_head *rt_list, struct nss_ovpnmgr_route_tuple *rt)
+{
+	struct nss_ovpnmgr_route *route;
+
+	list_for_each_entry(route, rt_list, list) {
+		if (route->rt.ip_version != rt->ip_version) {
+			continue;
+		}
+
+		if (!memcmp(route->rt.ip_addr, rt->ip_addr, sizeof(rt->ip_addr))) {
+			return route;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_ovpnmgr_route_set_active()
+ *	Update OVPN tunnel route.
+ */
+int nss_ovpnmgr_route_set_active(struct list_head *rt_list, struct nss_ovpnmgr_route_tuple *rt)
+{
+	struct nss_ovpnmgr_route *route;
+
+	/*
+	 * This API should be called under lock.
+	 */
+	lockdep_assert_held(&ovpnmgr_ctx.lock);
+
+	/*
+	 * Search for route entry with from_addr.
+	 */
+	route = nss_ovpnmgr_route_find(rt_list, rt);
+	if (!route) {
+		nss_ovpnmgr_warn("%px: Route %x:%x:%x:%x not found\n", rt_list, rt->ip_addr[0],
+				rt->ip_addr[1], rt->ip_addr[2], rt->ip_addr[3]);
+		return -EINVAL;
+	}
+
+	route->in_use++;
+	return 0;
+}
+
+/*
+ * nss_ovpnmgr_route_is_active()
+ *	Get route state.
+ */
+bool nss_ovpnmgr_route_is_active(uint32_t tunnel_id, struct nss_ovpnmgr_route_tuple *rt)
+{
+	struct nss_ovpnmgr_route *route;
+	struct net_device *tun_dev;
+	struct nss_ovpnmgr_tun *tun;
+
+	tun_dev = dev_get_by_index(&init_net, tunnel_id);
+	if (!tun_dev) {
+		nss_ovpnmgr_warn("Couldn't find tunnel: tunnel_id = %u\n", tunnel_id);
+		return false;
+	}
+
+	tun = netdev_priv(tun_dev);
+
+	read_lock_bh(&ovpnmgr_ctx.lock);
+
+	route = nss_ovpnmgr_route_find(&tun->route_list, rt);
+	if (!route) {
+		/*
+		 * Route is not found.
+		 */
+		read_unlock_bh(&ovpnmgr_ctx.lock);
+		dev_put(tun_dev);
+		return false;
+	}
+
+	/*
+	 * in_use is updated when packets hit flow entries in firmware are active
+	 */
+	if (route->in_use) {
+		route->in_use = 0;
+		read_unlock_bh(&ovpnmgr_ctx.lock);
+		nss_ovpnmgr_info("%px: Route is active, don't delete\n", tun);
+		dev_put(tun_dev);
+		return true;
+	}
+
+	read_unlock_bh(&ovpnmgr_ctx.lock);
+
+	dev_put(tun_dev);
+	return false;
+}
+EXPORT_SYMBOL(nss_ovpnmgr_route_is_active);
+
+/*
+ * nss_ovpnmgr_route_del()
+ *	Delete route from the tunnel.
+ */
+int nss_ovpnmgr_route_del(uint32_t tunnel_id, struct nss_ovpnmgr_route_tuple *rt)
+{
+	struct nss_ovpnmgr_route *route;
+	struct net_device *tun_dev;
+	struct nss_ovpnmgr_tun *tun;
+
+	tun_dev = dev_get_by_index(&init_net, tunnel_id);
+	if (!tun_dev) {
+		nss_ovpnmgr_warn("Couldn't find tunnel: tunnel_id = %u\n\n", tunnel_id);
+		return -ENODEV;
+	}
+
+	tun = netdev_priv(tun_dev);
+	write_lock_bh(&ovpnmgr_ctx.lock);
+
+	route = nss_ovpnmgr_route_find(&tun->route_list, rt);
+	if (!route) {
+		/*
+		 * Route is not found.
+		 */
+		write_unlock_bh(&ovpnmgr_ctx.lock);
+		dev_put(tun_dev);
+		return -EINVAL;
+	}
+
+	nss_ovpnmgr_info("%px: Deleting route on tunnel id:%d\n", route, tunnel_id);
+
+	list_del(&route->list);
+	write_unlock_bh(&ovpnmgr_ctx.lock);
+
+	kfree(route);
+	dev_put(tun_dev);
+	return 0;
+}
+EXPORT_SYMBOL(nss_ovpnmgr_route_del);
+
+/*
+ * nss_ovpnmgr_route_add()
+ *	Add new route for the given tunnel
+ */
+int nss_ovpnmgr_route_add(uint32_t tunnel_id, struct nss_ovpnmgr_route_tuple *rt)
+{
+	struct nss_ovpnmgr_route *route;
+	struct net_device *tun_dev;
+	struct nss_ovpnmgr_tun *tun;
+
+	tun_dev = dev_get_by_index(&init_net, tunnel_id);
+	if (!tun_dev) {
+		nss_ovpnmgr_warn("Couldn't find tunnel: tunnel_id = %u\n\n", tunnel_id);
+		return -ENODEV;
+	}
+
+	tun = netdev_priv(tun_dev);
+
+	/*
+	 * Check if route is available.
+	 */
+	route = nss_ovpnmgr_route_find(&tun->route_list, rt);
+	if (route) {
+		nss_ovpnmgr_warn("%px: Route is available\n", tun);
+		dev_put(tun_dev);
+		return -EEXIST;
+	}
+
+	route = kzalloc(sizeof(*route), GFP_KERNEL);
+	if (!route) {
+		nss_ovpnmgr_warn("%px: Couldn't allocate memory for new route\n", tun);
+		dev_put(tun_dev);
+		return -ENOMEM;
+	}
+
+	memcpy(&route->rt, rt, sizeof(*rt));
+	nss_ovpnmgr_info("%px: version = %d, IP = %x:%x:%x:%x\n", tun,
+			route->rt.ip_version, route->rt.ip_addr[0],
+			route->rt.ip_addr[1], route->rt.ip_addr[2],
+			route->rt.ip_addr[3]);
+
+	write_lock_bh(&ovpnmgr_ctx.lock);
+	list_add(&route->list, &tun->route_list);
+	write_unlock_bh(&ovpnmgr_ctx.lock);
+
+	dev_put(tun_dev);
+	return 0;
+}
+EXPORT_SYMBOL(nss_ovpnmgr_route_add);
diff --git a/qca-nss-clients/openvpn/src/nss_ovpnmgr_route.h b/qca-nss-clients/openvpn/src/nss_ovpnmgr_route.h
new file mode 100644
index 0000000..6ca8e48
--- /dev/null
+++ b/qca-nss-clients/openvpn/src/nss_ovpnmgr_route.h
@@ -0,0 +1,34 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ovpnmgr_route.h
+ */
+#ifndef __NSS_OVPNMGR_ROUTE__H
+#define __NSS_OVPNMGR_ROUTE__H
+
+/*
+ * nss_ovpnmgr_route
+ */
+struct nss_ovpnmgr_route {
+	struct list_head list;			/* List of Routes configured in this tunnel. */
+	struct nss_ovpnmgr_route_tuple rt;	/* Route tuple. */
+	uint32_t in_use;			/* Increments when ecm stats update updated from NSS FW */
+};
+
+struct nss_ovpnmgr_route *nss_ovpnmgr_route_find(struct list_head *rt_list, struct nss_ovpnmgr_route_tuple *rt);
+int nss_ovpnmgr_route_set_active(struct list_head *rt_list, struct nss_ovpnmgr_route_tuple *rt);
+#endif /* __NSS_OVPNMGR_ROUTE__H */
diff --git a/qca-nss-clients/openvpn/src/nss_ovpnmgr_tun.c b/qca-nss-clients/openvpn/src/nss_ovpnmgr_tun.c
new file mode 100644
index 0000000..2d6ecb4
--- /dev/null
+++ b/qca-nss-clients/openvpn/src/nss_ovpnmgr_tun.c
@@ -0,0 +1,1301 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ovpnmgr_tun.c
+ */
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/if_tun.h>
+#include <linux/ip.h>
+#include <net/ip.h>
+#include <net/udp.h>
+#include <net/ip6_checksum.h>
+#include <linux/ipv6.h>
+#include <linux/crypto.h>
+
+#include <nss_api_if.h>
+#include <nss_qvpn.h>
+#include "nss_ovpnmgr.h"
+#include "nss_ovpnmgr_crypto.h"
+#include "nss_ovpnmgr_tun.h"
+#include "nss_ovpnmgr_app.h"
+#include "nss_ovpnmgr_debugfs.h"
+#include "nss_ovpnmgr_priv.h"
+#include "nss_ovpnmgr_route.h"
+
+#if NSS_OVPNMGR_DEBUG_ENABLE_PKT_DUMP
+/*
+ * nss_ovpnmgr_tun_pkt_dump()
+ *	Dump packet.
+ */
+static void nss_ovpnmgr_tun_pkt_dump(struct sk_buff *skb, char *hdr, uint16_t offset, uint16_t len)
+{
+	nss_ovpnmgr_info("%s:\n", hdr);
+	print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, skb->data + offset, len);
+}
+#define NSS_OVPNMGR_TUN_PKT_DUMP(skb, hdr, offset, len) nss_ovpnmgr_tun_pkt_dump(skb, hdr, offset, len)
+#else
+#define NSS_OVPNMGR_TUN_PKT_DUMP(skb, hdr, offset, len)
+#endif
+
+/*
+ * nss_ovpnmgr_tun_ipv4_forward()
+ *	Transmit IPv4 encapsulated packet exceptioned from NSS.
+ */
+static void nss_ovpnmgr_tun_ipv4_forward(struct nss_ovpnmgr_tun *tun, struct sk_buff *skb)
+{
+	struct nss_ovpnmgr_app *app = tun->app;
+	struct udphdr *udph;
+	struct rtable *rt;
+	struct iphdr *iph;
+
+	skb->protocol = htons(ETH_P_IP);
+	skb_reset_network_header(skb);
+	iph = ip_hdr(skb);
+
+	rt = ip_route_output(dev_net(app->dev), iph->daddr, iph->saddr, 0, 0);
+	if (unlikely(IS_ERR(rt))) {
+		nss_ovpnmgr_warn("%px: Failed to find IPv4 route.\n", skb);
+		tun->outer.stats.host_pkt_drop++;
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	/*
+	 * Reset skb->dst.
+	 */
+	skb_dst_drop(skb);
+	skb_dst_set(skb, &rt->dst);
+	/*
+	 * Set packet type as host generated and set skb->dev to tun/tap device.
+	 */
+	skb->pkt_type = PACKET_HOST;
+	skb->dev = app->dev;
+
+	/*
+	 * Check IPv4 header length.
+	 */
+	if (ip_hdrlen(skb) != sizeof(*iph)) {
+		nss_ovpnmgr_warn("%px: IPv4 header length is incorrect.\n", skb);
+		tun->outer.stats.host_pkt_drop++;
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	/*
+	 * Set transport header.
+	 */
+	skb_set_transport_header(skb, ip_hdrlen(skb));
+	skb->skb_iif = app->dev->ifindex;
+
+	if (iph->protocol != IPPROTO_UDP) {
+		nss_ovpnmgr_warn("%px: Encapuslation protocol is not UDP.\n", skb);
+		tun->outer.stats.host_pkt_drop++;
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	udph = udp_hdr(skb);
+	udp_set_csum(0, skb, iph->saddr, iph->daddr, ntohs(udph->len));
+	ip_local_out(&init_net, NULL, skb);
+}
+
+/*
+ * nss_ovpnmgr_tun_ipv6_forward()
+ *	Transmit IPv6 encapsulated packet exceptioned from NSS.
+ */
+static void nss_ovpnmgr_tun_ipv6_forward(struct nss_ovpnmgr_tun *tun, struct sk_buff *skb)
+{
+	struct nss_ovpnmgr_app *app = tun->app;
+	struct rt6_info *rt6;
+	struct ipv6hdr *ip6h;
+
+	skb_reset_network_header(skb);
+	skb->protocol = htons(ETH_P_IPV6);
+	ip6h = ipv6_hdr(skb);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0))
+	rt6 = rt6_lookup(dev_net(app->dev), &ip6h->daddr, &ip6h->saddr, 0, 0);
+#else
+	rt6 = rt6_lookup(dev_net(app->dev), &ip6h->daddr, &ip6h->saddr, 0, 0, 0);
+#endif
+	if (!rt6) {
+		nss_ovpnmgr_warn("%px: Failed to find IPv6 route.\n", skb);
+		tun->outer.stats.host_pkt_drop++;
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	/*
+	 * Reset skb->dst.
+	 */
+	skb_dst_drop(skb);
+	skb_dst_set(skb, &rt6->dst);
+
+	/*
+	 * Set packet type as host generated and set skb->dev to tun/tap device.
+	 */
+	skb->pkt_type = PACKET_HOST;
+	skb->dev = app->dev;
+
+	/*
+	 * Set transport header.
+	 */
+	skb_set_transport_header(skb, sizeof(*ip6h));
+	skb->skb_iif = app->dev->ifindex;
+
+	if (ip6h->nexthdr != IPPROTO_UDP) {
+		nss_ovpnmgr_warn("%px: Encapuslation protocol is not UDP.\n", skb);
+		tun->outer.stats.host_pkt_drop++;
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	skb->ip_summed = CHECKSUM_PARTIAL;
+	ip6_local_out(&init_net, NULL, skb);
+}
+
+/*
+ * nss_ovpnmgr_tun_rx_outer()
+ *	Handles encapsulated packets received from NSS firmware
+ */
+static void nss_ovpnmgr_tun_rx_outer(struct net_device *dev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	struct nss_ovpnmgr_tun *tun = netdev_priv(dev);
+
+	skb_reset_network_header(skb);
+
+	switch (ip_hdr(skb)->version) {
+	case IPVERSION:
+		/*
+		 * Dump ip_hdr(20) + udp_hdr(8) + ovpn_hdr(4)
+		 */
+		NSS_OVPNMGR_TUN_PKT_DUMP(skb, "IPv4 packet from NSS(Outer)", 0, 32);
+		nss_ovpnmgr_tun_ipv4_forward(tun, skb);
+		break;
+	case 6:
+		/*
+		 * Dump ipv6_hdr(40) + udp_hdr(8) + ovpn_hdr(4)
+		 */
+		NSS_OVPNMGR_TUN_PKT_DUMP(skb, "IPv6 packet from NSS(Outer)", 0, 52);
+		nss_ovpnmgr_tun_ipv6_forward(tun, skb);
+		break;
+	default:
+		/*
+		 * Dump initial 20 bytes to analyze junk packet.
+		 */
+		NSS_OVPNMGR_TUN_PKT_DUMP(skb, "Junk packet from NSS(Outer)", 0, 20);
+		tun->outer.stats.host_pkt_drop++;
+		dev_kfree_skb_any(skb);
+	}
+}
+
+/*
+ * nss_ovpnmgr_tun_rx_inner()
+ *	Handles decapsulated packets received from NSS firmware
+ */
+static void nss_ovpnmgr_tun_rx_inner(struct net_device *dev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	struct nss_ovpnmgr_tun *tun = netdev_priv(dev);
+	struct nss_ovpnmgr_app *app = tun->app;
+
+	skb_reset_mac_header(skb);
+	skb_reset_network_header(skb);
+	skb_reset_transport_header(skb);
+
+	switch (ip_hdr(skb)->version) {
+	case IPVERSION:
+		/*
+		 * Dump ip_hdr(20) + transport header(8)
+		 */
+		NSS_OVPNMGR_TUN_PKT_DUMP(skb, "IPv4 packet from NSS(Inner)", 0, 28);
+		skb->protocol = htons(ETH_P_IP);
+		break;
+	case 6:
+		/*
+		 * Dump ipv6_hdr(40) + transport header(8)
+		 */
+		NSS_OVPNMGR_TUN_PKT_DUMP(skb, "IPv6 packet from NSS(Inner)", 0, 48);
+		skb->protocol = htons(ETH_P_IPV6);
+		break;
+	default:
+		/*
+		 * Dump maximum control packet size(28)
+		 */
+		NSS_OVPNMGR_TUN_PKT_DUMP(skb, "OCC/PING(OVPN) packet from NSS(Inner)", 0, 28);
+		nss_ovpnmgr_app_forward(app, tun, skb);
+		return;
+	}
+
+	skb->ip_summed = CHECKSUM_NONE;
+	skb->pkt_type = PACKET_HOST;
+	skb->dev = app->dev;
+	skb->skb_iif = app->dev->ifindex;
+	netif_receive_skb(skb);
+}
+
+/*
+ * nss_ovpnmgr_tun_stats_update()
+ *	Update statistics.
+ */
+static void nss_ovpnmgr_tun_stats_update(struct nss_ovpnmgr_tun *tun, struct rtnl_link_stats64 *stats)
+{
+	struct nss_ovpnmgr_tun_ctx_stats *inner_stats, *outer_stats;
+	int i;
+
+	/*
+	 * This API is called under lock.
+	 */
+
+	inner_stats = &tun->inner.stats;
+	outer_stats = &tun->outer.stats;
+
+	stats->rx_packets += inner_stats->rx_packets;
+	stats->rx_bytes += inner_stats->rx_bytes;
+	stats->tx_packets += outer_stats->tx_packets;
+	stats->tx_bytes += outer_stats->tx_bytes;
+
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		stats->rx_dropped += inner_stats->rx_dropped[i];
+		stats->tx_dropped += outer_stats->rx_dropped[i];
+	}
+
+	for (i = 1; i < NSS_CRYPTO_CMN_RESP_ERROR_MAX; i++) {
+		stats->rx_dropped += inner_stats->fail_crypto[i];
+		stats->tx_dropped += outer_stats->fail_crypto[i];
+	}
+
+	for (i = 0; i < NSS_QVPN_PKT_DROP_EVENT_MAX; i++) {
+		stats->rx_dropped += inner_stats->fail_offload[i];
+		stats->tx_dropped += outer_stats->fail_offload[i];
+	}
+}
+
+/*
+ * nss_ovpnmgr_tun_update_node_stats()
+ *	Update node statistics.
+ */
+static void nss_ovpnmgr_tun_update_node_stats(struct nss_ovpnmgr_tun *tun, struct nss_qvpn_stats_sync_msg *stats, bool inner)
+{
+	struct nss_ovpnmgr_tun_stats *tun_stats = &tun->stats;
+
+	if (inner) {
+		tun_stats->tun_read_bytes += stats->node_stats.rx_bytes;
+		tun_stats->link_write_bytes += stats->node_stats.tx_bytes;
+	} else {
+		tun_stats->link_read_bytes += stats->node_stats.rx_bytes;
+		tun_stats->tun_write_bytes += stats->node_stats.tx_bytes;
+		tun_stats->link_read_bytes_auth += stats->node_stats.tx_bytes;
+		tun_stats->link_read_bytes_auth += stats->exception_event[NSS_QVPN_EXCEPTION_EVENT_RX_DATA_PKT];
+	}
+}
+
+/*
+ * nss_ovpnmgr_tun_event_inner()
+ *	Handles events/messages from NSS firmware
+ */
+static void nss_ovpnmgr_tun_event_inner(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_ovpnmgr_tun_ctx_stats *ctx_stats;
+	struct nss_ovpnmgr_tun *tun = app_data;
+	struct nss_qvpn_msg *nom = (struct nss_qvpn_msg *)ncm;
+	struct nss_qvpn_stats_sync_msg *stats = &nom->msg.stats;
+	struct nss_ovpnmgr_app *app = tun->app;
+	struct net_device *dev;
+	int i;
+
+	if (nom->cm.type != NSS_QVPN_MSG_TYPE_SYNC_STATS) {
+		nss_ovpnmgr_warn("%px: Unsupported event received from NSS: %d\n", tun, nom->cm.type);
+		return;
+	}
+
+	write_lock(&ovpnmgr_ctx.lock);
+
+	ctx_stats = &tun->inner.stats;
+
+	ctx_stats->rx_packets += stats->node_stats.rx_packets;
+	ctx_stats->rx_bytes += stats->node_stats.rx_bytes;
+
+	ctx_stats->tx_packets += stats->node_stats.tx_packets;
+	ctx_stats->tx_bytes += stats->node_stats.tx_bytes;
+
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		ctx_stats->rx_dropped[i] += stats->node_stats.rx_dropped[i];
+	}
+
+	for (i = 0; i < NSS_CRYPTO_CMN_RESP_ERROR_MAX; i++) {
+		ctx_stats->fail_crypto[i] += stats->crypto_resp_error[i];
+	}
+
+	for (i = 0; i < NSS_QVPN_PKT_DROP_EVENT_MAX; i++) {
+		ctx_stats->fail_offload[i] += stats->pkt_drop_event[i];
+	}
+
+	for (i = 0 ; i < NSS_QVPN_EXCEPTION_EVENT_MAX; i++) {
+		ctx_stats->exception[i] += stats->exception_event[i];
+	}
+
+	dev = app->dev;
+	nss_ovpnmgr_tun_update_node_stats(tun, stats, true);
+
+	write_unlock(&ovpnmgr_ctx.lock);
+}
+
+/*
+ * nss_ovpnmgr_tun_event_outer()
+ *	Handles events/messages from NSS firmware
+ */
+static void nss_ovpnmgr_tun_event_outer(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_ovpnmgr_tun_ctx_stats *ctx_stats;
+	struct nss_ovpnmgr_tun *tun = app_data;
+	struct nss_qvpn_msg *nom = (struct nss_qvpn_msg *)ncm;
+	struct nss_qvpn_stats_sync_msg *stats = &nom->msg.stats;
+	struct nss_ovpnmgr_app *app = tun->app;
+	struct net_device *dev;
+	int i;
+
+	if (nom->cm.type != NSS_QVPN_MSG_TYPE_SYNC_STATS) {
+		nss_ovpnmgr_warn("%px: Unsupported event received from NSS: %d\n", tun, nom->cm.type);
+		return;
+	}
+
+	write_lock(&ovpnmgr_ctx.lock);
+
+	ctx_stats = &tun->outer.stats;
+
+	ctx_stats->rx_packets += stats->node_stats.rx_packets;
+	ctx_stats->rx_bytes += stats->node_stats.rx_bytes;
+
+	ctx_stats->tx_packets += stats->node_stats.tx_packets;
+	ctx_stats->tx_bytes += stats->node_stats.tx_bytes;
+
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		ctx_stats->rx_dropped[i] += stats->node_stats.rx_dropped[i];
+	}
+
+	for (i = 0; i < NSS_CRYPTO_CMN_RESP_ERROR_MAX; i++) {
+		ctx_stats->fail_crypto[i] += stats->crypto_resp_error[i];
+	}
+
+	for (i = 0; i < NSS_QVPN_PKT_DROP_EVENT_MAX; i++) {
+		ctx_stats->fail_offload[i] += stats->pkt_drop_event[i];
+	}
+
+	for (i = 0 ; i < NSS_QVPN_EXCEPTION_EVENT_MAX; i++) {
+		ctx_stats->exception[i] += stats->exception_event[i];
+	}
+
+	dev = app->dev;
+	nss_ovpnmgr_tun_update_node_stats(tun, stats, false);
+
+	write_unlock(&ovpnmgr_ctx.lock);
+}
+
+/*
+ * nss_ovpnmgr_tun_ctx_deinit()
+ *	De-initialize tunnel node.
+ */
+static int nss_ovpnmgr_tun_ctx_deinit(struct nss_ovpnmgr_tun_ctx *ctx)
+{
+	nss_qvpn_unregister_if(ctx->ifnum);
+
+	if (nss_dynamic_interface_dealloc_node(ctx->ifnum, ctx->di_type) != NSS_TX_SUCCESS) {
+		nss_ovpnmgr_warn("%px: failed to dealloc OVPN inner DI\n", ctx);
+	}
+
+	/* Unregister Encryption */
+	nss_ovpnmgr_crypto_ctx_free(&ctx->active);
+	nss_ovpnmgr_crypto_ctx_free(&ctx->expiring);
+
+	return 0;
+}
+
+/*
+ * nss_ovpnmgr_tun_deconfig()
+ *	Deconfigure inner tunnel node.
+ */
+static int nss_ovpnmgr_tun_deconfig(struct nss_ovpnmgr_tun_ctx *ctx, struct nss_ovpnmgr_tun *tun)
+{
+	struct nss_qvpn_msg nom;
+	struct nss_qvpn_tunnel_config_msg *msg = &nom.msg.tunnel_config;
+	enum nss_qvpn_error_type resp;
+	nss_tx_status_t status;
+
+	/*
+	 * TODO: Need to add support to retry if the failure is due to queueu full.
+	 */
+	status = nss_qvpn_tx_msg_sync(tun->nss_ctx, &nom, ctx->ifnum, NSS_QVPN_MSG_TYPE_TUNNEL_DECONFIGURE,
+			sizeof(*msg), &resp);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ovpnmgr_warn("%px: failed to configure outer interface, resp=%d, status = %d\n", tun, resp, status);
+		return status == NSS_TX_FAILURE_QUEUE ? -EBUSY : -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * ovpnmgr_dev_ops
+ */
+static const struct net_device_ops ovpnmgr_dev_ops = {
+	/*
+	 * ovpn netdev is created for transmitting control packets in data channel
+	 * to application. No addtional functionality is implemented.
+	 */
+};
+
+/*
+ * nss_ovpnmgr_tun_free()
+ *	Delete OVPN tunnel.
+ */
+static void nss_ovpnmgr_tun_free(struct net_device *dev)
+{
+	struct nss_ovpnmgr_tun *tun = netdev_priv(dev);
+
+	nss_ovpnmgr_tun_deconfig(&tun->inner, tun);
+	nss_ovpnmgr_tun_deconfig(&tun->outer, tun);
+	nss_ovpnmgr_tun_ctx_deinit(&tun->inner);
+	nss_ovpnmgr_tun_ctx_deinit(&tun->outer);
+	free_netdev(dev);
+}
+
+/*
+ * nss_ovpnmgr_tun_dev_setup()
+ *	Setup function for dummy netdevice.
+ */
+static void nss_ovpnmgr_tun_dev_setup(struct net_device *dev)
+{
+	dev->needed_headroom = NSS_OVPNMGR_TUN_HEADROOM;
+	dev->needed_tailroom = NSS_OVPNMGR_TUN_TAILROOM;
+
+	dev->header_ops = NULL;
+	dev->netdev_ops = &ovpnmgr_dev_ops;
+	dev->ethtool_ops = NULL;
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 11, 8))
+	dev->destructor = nss_ovpnmgr_tun_free;
+#else
+	dev->priv_destructor = nss_ovpnmgr_tun_free;
+#endif
+}
+
+/*
+ * nss_ovpnmgr_tun_alloc()
+ *	Allocte an OVPN tunnel instance.
+ */
+static struct nss_ovpnmgr_tun *nss_ovpnmgr_tun_alloc(void)
+{
+	struct nss_ovpnmgr_tun *tun;
+	struct net_device *dev;
+
+	dev = alloc_netdev(sizeof(*tun), NSS_OVPNMGR_TUN_NAME, NET_NAME_ENUM, nss_ovpnmgr_tun_dev_setup);
+	if (!dev) {
+		nss_ovpnmgr_warn("unable to allocate ovpn netdev\n");
+		return NULL;
+	}
+
+	tun = netdev_priv(dev);
+	tun->dev = dev;
+
+	INIT_LIST_HEAD(&tun->list);
+	INIT_LIST_HEAD(&tun->route_list);
+
+	tun->nss_ctx = nss_qvpn_get_context();
+	if (unlikely(!tun->nss_ctx)) {
+		nss_ovpnmgr_warn("%px: Failed to get NSS OVPN context.\n", tun);
+		return NULL;
+	}
+
+	tun->inner.nss_ctx = tun->outer.nss_ctx = tun->nss_ctx;
+	return tun;
+}
+
+/*
+ * nss_ovpnmgr_tun_init_qvpn_config()
+ *	Initialize QVPN configuration data structure.
+ */
+static void nss_ovpnmgr_tun_init_qvpn_config(struct nss_ovpnmgr_tun *tun, struct nss_qvpn_tunnel_config_msg *qvpn_cfg)
+{
+	memset(qvpn_cfg, 0, sizeof(*qvpn_cfg));
+
+	if (tun->tun_cfg.flags & NSS_OVPNMGR_HDR_FLAG_IPV6) {
+		nss_ovpnmgr_ipv6_addr_ntohl(qvpn_cfg->hdr_cfg.dst_ip, tun->tun_hdr.dst_ip);
+		nss_ovpnmgr_ipv6_addr_ntohl(qvpn_cfg->hdr_cfg.src_ip, tun->tun_hdr.src_ip);
+		qvpn_cfg->hdr_cfg.hdr_flags = NSS_QVPN_HDR_FLAG_IPV6;
+	} else {
+		qvpn_cfg->hdr_cfg.src_ip[0] = ntohl(tun->tun_hdr.src_ip[0]);
+		qvpn_cfg->hdr_cfg.dst_ip[0] = ntohl(tun->tun_hdr.dst_ip[0]);
+	}
+
+	qvpn_cfg->hdr_cfg.src_port = ntohs(tun->tun_hdr.src_port);
+	qvpn_cfg->hdr_cfg.dst_port = ntohs(tun->tun_hdr.dst_port);
+	qvpn_cfg->hdr_cfg.hop_limit = tun->tun_hdr.hop_limit;
+	qvpn_cfg->hdr_cfg.hdr_flags |= NSS_QVPN_HDR_FLAG_L4_UDP;
+	qvpn_cfg->hdr_cfg.seqnum_size = 4;
+	qvpn_cfg->hdr_cfg.anti_replay_alg = NSS_QVPN_ANTI_REPLAY_ALG_REPLAY_WINDOW;
+	qvpn_cfg->hdr_cfg.session_id_offset = 0;
+	qvpn_cfg->hdr_cfg.session_id_size = 1;
+	qvpn_cfg->hdr_cfg.vpn_hdr_head_offset = 0;
+	qvpn_cfg->hdr_cfg.vpn_hdr_tail_size = 0;
+}
+
+/*
+ * nss_ovpnmgr_tun_inner_config()
+ *	Configure inner tunnel node.
+ */
+static int nss_ovpnmgr_tun_inner_config(struct nss_ovpnmgr_tun *tun)
+{
+	struct nss_qvpn_msg nom;
+	struct nss_qvpn_tunnel_config_msg *qvpn_cfg = &nom.msg.tunnel_config;
+	enum nss_qvpn_error_type resp;
+	nss_tx_status_t status;
+	int32_t total_cmds = 1;
+
+	nss_ovpnmgr_tun_init_qvpn_config(tun, qvpn_cfg);
+
+	qvpn_cfg->sibling_if = tun->outer.ifnum;
+
+	/*
+	 * QVPN commands for OVPN encapsulation.
+	 *	NSS_QVPN_CMDS_TYPE_ADD_VPN_HDR, NSS_QVPN_CMDS_TYPE_ANTI_REPLAY,
+	 *	NSS_QVPN_CMDS_TYPE_ENCRYPT, NSS_QVPN_CMDS_TYPE_ADD_L3_L4_HDR
+	 */
+	qvpn_cfg->cmd[0] = NSS_QVPN_CMDS_TYPE_ADD_VPN_HDR;
+
+	if (!(tun->tun_cfg.flags & NSS_OVPNMGR_HDR_FLAG_NO_REPLAY)) {
+		qvpn_cfg->cmd[total_cmds++] = NSS_QVPN_CMDS_TYPE_ANTI_REPLAY;
+	}
+
+	if (tun->inner.active.crypto_idx != U16_MAX) {
+		qvpn_cfg->cmd[total_cmds++] = NSS_QVPN_CMDS_TYPE_ENCRYPT;
+		qvpn_cfg->cmd_profile = NSS_QVPN_PROFILE_CRYPTO_ENCAP;
+	} else {
+		qvpn_cfg->cmd_profile = NSS_QVPN_PROFILE_ENCAP;
+	}
+
+	qvpn_cfg->cmd[total_cmds++] = NSS_QVPN_CMDS_TYPE_ADD_L3_L4_HDR;
+	qvpn_cfg->total_cmds = total_cmds;
+
+	/*
+	 * Crypto configuration.
+	 */
+	qvpn_cfg->crypto_key.crypto_idx = tun->inner.active.crypto_idx;
+
+	if (tun->tun_cfg.flags & NSS_OVPNMGR_HDR_FLAG_DATA_V2) {
+		uint32_t *session_id = (uint32_t *)qvpn_cfg->hdr_cfg.vpn_hdr_head;
+
+		*session_id = htonl((NSS_OVPNMGR_TUN_DATA_V2 << NSS_OVPNMGR_TUN_OPCODE_SHIFT) |
+					(tun->inner.active.key_id << NSS_OVPNMGR_TUN_KEY_ID_SHIFT) |
+					(tun->tun_cfg.peer_id & 0xFFFFFF));
+		/*
+		 * [op+kid|peer-id|HMAC Len|IV|SNO|Inner Packet]
+		 * [1|3|20-32|16-24-32]
+		 */
+		qvpn_cfg->crypto_cfg.hmac_offset = 4;
+		qvpn_cfg->hdr_cfg.vpn_hdr_head_size = 4;
+	} else {
+		uint32_t *session_id = (uint32_t *)qvpn_cfg->hdr_cfg.vpn_hdr_head;
+
+		*session_id = htonl((NSS_OVPNMGR_TUN_DATA_V1 << NSS_OVPNMGR_TUN_OPCODE_SHIFT) |
+					(tun->inner.active.key_id << NSS_OVPNMGR_TUN_KEY_ID_SHIFT));
+		/*
+		 * [op+kid|HMAC Len|IV|SNO|Inner Packet]
+		 * [1|20-32|16-24-32]
+		 */
+		qvpn_cfg->crypto_cfg.hmac_offset = 1;
+		qvpn_cfg->hdr_cfg.vpn_hdr_head_size = 1;
+	}
+
+	memcpy(qvpn_cfg->crypto_key.session_id, qvpn_cfg->hdr_cfg.vpn_hdr_head, 1);
+	qvpn_cfg->crypto_cfg.hmac_len = tun->inner.active.hash_len;
+	qvpn_cfg->crypto_cfg.iv_len = tun->inner.active.iv_len;
+
+	qvpn_cfg->hdr_cfg.vpn_hdr_head_size += qvpn_cfg->crypto_cfg.hmac_len + qvpn_cfg->crypto_cfg.iv_len +
+						qvpn_cfg->hdr_cfg.seqnum_size;
+	qvpn_cfg->crypto_cfg.iv_offset = qvpn_cfg->crypto_cfg.hmac_offset + qvpn_cfg->crypto_cfg.hmac_len;
+	qvpn_cfg->crypto_cfg.auth_offset = qvpn_cfg->crypto_cfg.iv_offset;
+	qvpn_cfg->crypto_cfg.cipher_op_offset = qvpn_cfg->crypto_cfg.iv_offset + qvpn_cfg->crypto_cfg.iv_len;
+	qvpn_cfg->crypto_cfg.cipher_blk_size = tun->outer.active.blk_len;
+
+	qvpn_cfg->hdr_cfg.seqnum_offset = qvpn_cfg->crypto_cfg.iv_offset + qvpn_cfg->crypto_cfg.iv_len;
+
+	switch (tun->inner.active.crypto_type) {
+	case NSS_OVPNMGR_CRYPTO_TYPE_AEAD:
+		qvpn_cfg->crypto_cfg.crypto_mode = NSS_QVPN_CRYPTO_MODE_ENC_AUTH;
+		qvpn_cfg->crypto_cfg.iv_type = NSS_QVPN_IV_TYPE_DYNAMIC_RAND;
+		qvpn_cfg->crypto_cfg.pad_type = NSS_QVPN_PAD_TYPE_PKCS7;
+		break;
+	case NSS_OVPNMGR_CRYPTO_TYPE_ABLK:
+		qvpn_cfg->crypto_cfg.crypto_mode = NSS_QVPN_CRYPTO_MODE_ENC;
+		qvpn_cfg->crypto_cfg.iv_type = NSS_QVPN_IV_TYPE_DYNAMIC_RAND;
+		qvpn_cfg->crypto_cfg.pad_type = NSS_QVPN_PAD_TYPE_PKCS7;
+		break;
+	case NSS_OVPNMGR_CRYPTO_TYPE_AHASH:
+		qvpn_cfg->crypto_cfg.crypto_mode = NSS_QVPN_CRYPTO_MODE_AUTH;
+		qvpn_cfg->crypto_cfg.iv_type = NSS_QVPN_IV_TYPE_NONE;
+		qvpn_cfg->crypto_cfg.pad_type = NSS_QVPN_PAD_TYPE_NONE;
+		break;
+	default:
+		qvpn_cfg->crypto_cfg.crypto_mode = NSS_QVPN_CRYPTO_MODE_NONE;
+		qvpn_cfg->crypto_cfg.iv_type = NSS_QVPN_IV_TYPE_NONE;
+		qvpn_cfg->crypto_cfg.pad_type = NSS_QVPN_PAD_TYPE_NONE;
+	}
+
+	status = nss_qvpn_tx_msg_sync(tun->nss_ctx,  &nom, tun->inner.ifnum, NSS_QVPN_MSG_TYPE_TUNNEL_CONFIGURE,
+					sizeof(*qvpn_cfg), &resp);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ovpnmgr_warn("%px: failed to configure inner interface, resp = %d, status = %d\n", tun, resp, status);
+		return status == NSS_TX_FAILURE_QUEUE ? -EBUSY : -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ovpnmgr_tun_outer_config()
+ *	Configure outer tunnel node.
+ */
+static int nss_ovpnmgr_tun_outer_config(struct nss_ovpnmgr_tun *tun)
+{
+	struct nss_qvpn_msg nom;
+	struct nss_qvpn_tunnel_config_msg *qvpn_cfg = &nom.msg.tunnel_config;
+	enum nss_qvpn_error_type resp;
+	nss_tx_status_t status;
+	int32_t total_cmds = 0;
+
+	nss_ovpnmgr_tun_init_qvpn_config(tun, qvpn_cfg);
+
+	qvpn_cfg->sibling_if = tun->inner.ifnum;
+
+	/*
+	 * QVPN commands for OVPN encapsulation.
+	 *	NSS_QVPN_CMDS_TYPE_DECRYPT, NSS_QVPN_CMDS_TYPE_ANTI_REPLAY,
+	 *	NSS_QVPN_CMDS_TYPE_REMOVE_L3_L4_HDR, NSS_QVPN_CMDS_TYPE_REMOVE_VPN_HDR
+	 */
+
+	if (tun->outer.active.crypto_idx != U16_MAX) {
+		qvpn_cfg->cmd[total_cmds++] = NSS_QVPN_CMDS_TYPE_DECRYPT;
+		qvpn_cfg->cmd_profile = NSS_QVPN_PROFILE_CRYPTO_DECAP;
+	} else {
+		qvpn_cfg->cmd_profile = NSS_QVPN_PROFILE_DECAP;
+	}
+
+	if (!(tun->tun_cfg.flags & NSS_OVPNMGR_HDR_FLAG_NO_REPLAY)) {
+		qvpn_cfg->cmd[total_cmds++] = NSS_QVPN_CMDS_TYPE_ANTI_REPLAY;
+	}
+
+	qvpn_cfg->cmd[total_cmds++] = NSS_QVPN_CMDS_TYPE_REMOVE_L3_L4_HDR;
+	qvpn_cfg->cmd[total_cmds++] = NSS_QVPN_CMDS_TYPE_REMOVE_VPN_HDR;
+	qvpn_cfg->total_cmds = total_cmds;
+
+	/*
+	 * Crypto configuration.
+	 */
+	qvpn_cfg->crypto_key.crypto_idx = tun->outer.active.crypto_idx;
+
+	if (tun->tun_cfg.flags & NSS_OVPNMGR_HDR_FLAG_PEER_DATA_V2) {
+		uint32_t *session_id = (uint32_t *)qvpn_cfg->hdr_cfg.vpn_hdr_head;
+
+		nss_ovpnmgr_info("Peer transmits V2 data packets\n");
+
+		*session_id = htonl((NSS_OVPNMGR_TUN_DATA_V2 << NSS_OVPNMGR_TUN_OPCODE_SHIFT) |
+					(tun->inner.active.key_id << NSS_OVPNMGR_TUN_KEY_ID_SHIFT) |
+					(tun->tun_cfg.peer_id & 0xFFFFFF));
+		/*
+		 * [op+kid|peer-id|HMAC Len|IV|SNO|Inner Packet]
+		 * [1|3|20-32|16-24-32]
+		 */
+		qvpn_cfg->crypto_cfg.hmac_offset = 4;
+		qvpn_cfg->hdr_cfg.vpn_hdr_head_size = 4;
+	} else {
+		uint32_t *session_id = (uint32_t *)qvpn_cfg->hdr_cfg.vpn_hdr_head;
+
+		*session_id = htonl((NSS_OVPNMGR_TUN_DATA_V1 << NSS_OVPNMGR_TUN_OPCODE_SHIFT) |
+					(tun->inner.active.key_id << NSS_OVPNMGR_TUN_KEY_ID_SHIFT));
+		/*
+		 * [op+kid|HMAC Len|IV|SNO|Inner Packet]
+		 * [1|20-32|16-24-32]
+		 */
+		qvpn_cfg->crypto_cfg.hmac_offset = 1;
+		qvpn_cfg->hdr_cfg.vpn_hdr_head_size = 1;
+	}
+
+	memcpy(qvpn_cfg->crypto_key.session_id, qvpn_cfg->hdr_cfg.vpn_hdr_head, 1);
+
+	qvpn_cfg->crypto_cfg.hmac_len = tun->outer.active.hash_len;
+	qvpn_cfg->crypto_cfg.iv_len = tun->outer.active.iv_len;
+
+	qvpn_cfg->hdr_cfg.vpn_hdr_head_size += qvpn_cfg->crypto_cfg.hmac_len + qvpn_cfg->crypto_cfg.iv_len +
+						qvpn_cfg->hdr_cfg.seqnum_size;
+	qvpn_cfg->crypto_cfg.iv_offset = qvpn_cfg->crypto_cfg.hmac_offset + qvpn_cfg->crypto_cfg.hmac_len;
+	qvpn_cfg->crypto_cfg.auth_offset = qvpn_cfg->crypto_cfg.iv_offset;
+	qvpn_cfg->crypto_cfg.cipher_op_offset = qvpn_cfg->crypto_cfg.iv_offset + qvpn_cfg->crypto_cfg.iv_len;
+	qvpn_cfg->crypto_cfg.cipher_blk_size = tun->outer.active.blk_len;
+
+	switch (tun->outer.active.crypto_type) {
+	case NSS_OVPNMGR_CRYPTO_TYPE_AEAD:
+		qvpn_cfg->crypto_cfg.crypto_mode = NSS_QVPN_CRYPTO_MODE_AUTH_DEC;
+		qvpn_cfg->crypto_cfg.iv_type = NSS_QVPN_IV_TYPE_DYNAMIC_RAND;
+		qvpn_cfg->crypto_cfg.pad_type = NSS_QVPN_PAD_TYPE_PKCS7;
+		break;
+	case NSS_OVPNMGR_CRYPTO_TYPE_ABLK:
+		qvpn_cfg->crypto_cfg.crypto_mode = NSS_QVPN_CRYPTO_MODE_DEC;
+		qvpn_cfg->crypto_cfg.iv_type = NSS_QVPN_IV_TYPE_DYNAMIC_RAND;
+		qvpn_cfg->crypto_cfg.pad_type = NSS_QVPN_PAD_TYPE_PKCS7;
+		break;
+	case NSS_OVPNMGR_CRYPTO_TYPE_AHASH:
+		qvpn_cfg->crypto_cfg.crypto_mode = NSS_QVPN_CRYPTO_MODE_AUTH;
+		qvpn_cfg->crypto_cfg.iv_type = NSS_QVPN_IV_TYPE_NONE;
+		qvpn_cfg->crypto_cfg.pad_type = NSS_QVPN_PAD_TYPE_NONE;
+		break;
+	default:
+		qvpn_cfg->crypto_cfg.crypto_mode = NSS_QVPN_CRYPTO_MODE_NONE;
+		qvpn_cfg->crypto_cfg.iv_type = NSS_QVPN_IV_TYPE_NONE;
+		qvpn_cfg->crypto_cfg.pad_type = NSS_QVPN_PAD_TYPE_NONE;
+	}
+
+	status = nss_qvpn_tx_msg_sync(tun->nss_ctx, &nom, tun->outer.ifnum, NSS_QVPN_MSG_TYPE_TUNNEL_CONFIGURE,
+					sizeof(*qvpn_cfg), &resp);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ovpnmgr_warn("%px: failed to configure outer interface, resp = %d, status = %d\n", tun, resp, status);
+		return status == NSS_TX_FAILURE_QUEUE ? -EBUSY : -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ovpnmgr_tun_ctx_inner_init()
+ *	Initialize inner tunnel context.
+ */
+static int nss_ovpnmgr_tun_ctx_inner_init(struct nss_ovpnmgr_tun *tun,
+		struct nss_ovpnmgr_crypto_config *crypto_cfg)
+{
+	int ret;
+
+	/*
+	 * Register Encryption.
+	 */
+	if (nss_ovpnmgr_crypto_ctx_alloc(&tun->inner.active, crypto_cfg, &crypto_cfg->encrypt)) {
+		nss_ovpnmgr_error("%px: Failed to register Encryption session\n", tun);
+		return -EINVAL;
+	}
+
+	/* Send message to NSS FW */
+	tun->inner.di_type = NSS_DYNAMIC_INTERFACE_TYPE_QVPN_INNER;
+	tun->inner.ifnum = nss_dynamic_interface_alloc_node(tun->inner.di_type);
+	if (tun->inner.ifnum < 0) {
+		nss_ovpnmgr_error("%px: Failed to alloc OVPN inner dynamic interface\n", tun);
+		ret = -ENXIO;
+		goto free_crypto;
+	}
+
+	if (!nss_qvpn_register_if(tun->inner.ifnum, nss_ovpnmgr_tun_rx_inner,
+				nss_ovpnmgr_tun_event_inner, tun->dev, 0, tun)) {
+		nss_ovpnmgr_warn("%px: Failed to register OVPN inner interface %d\n", tun, tun->inner.ifnum);
+		ret = -EIO;
+		goto free_ifnum;
+	}
+
+	return 0;
+
+free_ifnum:
+	if (nss_dynamic_interface_dealloc_node(tun->inner.ifnum, tun->inner.di_type)) {
+		nss_ovpnmgr_warn("%px: Failed to dealloc inner DI.\n", tun);
+	}
+
+free_crypto:
+	/* Unregister Encryption */
+	nss_ovpnmgr_crypto_ctx_free(&tun->inner.active);
+	return ret;
+}
+
+/*
+ * nss_ovpnmgr_tun_ctx_outer_init()
+ *	Initialize outer tunnel context.
+ */
+static int nss_ovpnmgr_tun_ctx_outer_init(struct nss_ovpnmgr_tun *tun, struct nss_ovpnmgr_crypto_config *crypto_cfg)
+{
+	int ret;
+
+	/*
+	 * Register Encryption.
+	 */
+	if (nss_ovpnmgr_crypto_ctx_alloc(&tun->outer.active, crypto_cfg, &crypto_cfg->decrypt)) {
+		nss_ovpnmgr_error("%px: Failed to register Encryption session\n", tun);
+		return -EINVAL;
+	}
+
+	/* Send message to NSS FW */
+	tun->outer.di_type = NSS_DYNAMIC_INTERFACE_TYPE_QVPN_OUTER;
+	tun->outer.ifnum = nss_dynamic_interface_alloc_node(tun->outer.di_type);
+	if (tun->outer.ifnum < 0) {
+		nss_ovpnmgr_error("%px: Failed to alloc OVPN outer dynamic interface\n", tun);
+		ret = -ENXIO;
+		goto free_crypto;
+	}
+
+	if (!nss_qvpn_register_if(tun->outer.ifnum, nss_ovpnmgr_tun_rx_outer, nss_ovpnmgr_tun_event_outer,
+				tun->dev, 0, tun)) {
+		nss_ovpnmgr_warn("%px: Failed to register OVPN outer interface %d\n", tun, tun->outer.ifnum);
+		ret = -EIO;
+		goto free_ifnum;
+	}
+
+	return 0;
+
+free_ifnum:
+	if (nss_dynamic_interface_dealloc_node(tun->outer.ifnum, tun->outer.di_type)) {
+		nss_ovpnmgr_warn("%px: Failed to dealloc outer dynamic node.\n", tun);
+	}
+
+free_crypto:
+	/* Unregister Decryption */
+	nss_ovpnmgr_crypto_ctx_free(&tun->outer.active);
+	return ret;
+}
+
+/*
+ * nss_ovpnmgr_tun_config_verify()
+ *	Verify tunnel configuration.
+ */
+static int nss_ovpnmgr_tun_config_verify(struct nss_ovpnmgr_tun_tuple *tun_hdr, struct nss_ovpnmgr_tun_config *tun_cfg)
+{
+	if (tun_cfg->flags & NSS_OVPNMGR_HDR_FLAG_L4_PROTO_TCP) {
+		nss_ovpnmgr_warn("%px: OVPN data channel offload over TCP is not supported\n", tun_hdr);
+		return -EINVAL;
+	}
+
+	if (tun_cfg->flags & NSS_OVPNMGR_HDR_FLAG_FRAG) {
+		nss_ovpnmgr_warn("%px: Fragmentation specified by OVPN protocol is not supported\n", tun_hdr);
+		return -EINVAL;
+	}
+
+	if (tun_cfg->flags & NSS_OVPNMGR_HDR_FLAG_PID_LONG_FMT) {
+		nss_ovpnmgr_warn("%px: PID Long format is not supported\n", tun_hdr);
+		return -EINVAL;
+	}
+
+	if (tun_cfg->flags & NSS_OVPNMGR_HDR_FLAG_SHARED_KEY) {
+		nss_ovpnmgr_warn("%px: Crypto shared key is not supported\n", tun_hdr);
+		return -EINVAL;
+	}
+
+	if (tun_cfg->flags & NSS_OVPNMGR_HDR_FLAG_COPY_TOS) {
+		nss_ovpnmgr_warn("%px: Copy TOS is not supported\n", tun_hdr);
+		return -EINVAL;
+	}
+
+	if (!tun_hdr->dst_ip[0] || !tun_hdr->src_ip[0] || !tun_hdr->src_port || !tun_hdr->dst_port) {
+		nss_ovpnmgr_warn("%px: IP/UDP Tunnel parameters are invalid.\n", tun_hdr);
+		return -EINVAL;
+	}
+
+	if (!tun_hdr->hop_limit) {
+		nss_ovpnmgr_warn("%px: Invalid hop_limit.\n", tun_hdr);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+/*
+ * nss_ovpnmgr_tun_config_dump()
+ *	Dump configuration details.
+ */
+static void nss_ovpnmgr_tun_config_dump(struct net_device *app_dev, struct nss_ovpnmgr_tun_tuple *tun_hdr,
+			struct nss_ovpnmgr_tun_config *tun_cfg, struct nss_ovpnmgr_crypto_config *crypto_cfg)
+{
+	nss_ovpnmgr_info("%px: app_dev = %s\n", app_dev, app_dev->name);
+	nss_ovpnmgr_info("flags = %x, peer_id = %u\n", tun_cfg->flags, tun_cfg->peer_id);
+
+	if (tun_cfg->flags & NSS_OVPNMGR_HDR_FLAG_IPV6) {
+		nss_ovpnmgr_info("Remote tunnel IP = %pI6c\n", tun_hdr->dst_ip);
+		nss_ovpnmgr_info("local tunnel IP = %pI6c\n", tun_hdr->src_ip);
+		nss_ovpnmgr_info("local tunnel Port = %d\n", tun_hdr->src_port);
+		nss_ovpnmgr_info("remote tunnel Port = %d\n", tun_hdr->dst_port);
+	} else {
+		nss_ovpnmgr_info("Remote tunnel IP = %pI4\n", &tun_hdr->dst_ip[0]);
+		nss_ovpnmgr_info("local tunnel IP = %pI4\n", &tun_hdr->src_ip[0]);
+		nss_ovpnmgr_info("local tunnel Port = %d\n", tun_hdr->src_port);
+		nss_ovpnmgr_info("remote tunnel Port = %d\n", tun_hdr->dst_port);
+	}
+	nss_ovpnmgr_info("hop_limit = %d\n", tun_hdr->hop_limit);
+	nss_ovpnmgr_info("Crypto: algo = %d, cipher_keylen = %d, hmac_keylen = %d\n",
+			crypto_cfg->algo, crypto_cfg->encrypt.cipher_keylen,
+			crypto_cfg->encrypt.hmac_keylen);
+}
+
+/*
+ * nss_ovpnmgr_tun_get_stats()
+ *	Update offload tunnel statistics
+ */
+void nss_ovpnmgr_tun_get_stats(struct net_device *app_dev, struct rtnl_link_stats64 *stats)
+{
+	struct nss_ovpnmgr_app *app;
+	struct nss_ovpnmgr_tun *tun;
+
+	write_lock_bh(&ovpnmgr_ctx.lock);
+
+	app = nss_ovpnmgr_app_find(app_dev);
+	if (!app) {
+		write_unlock_bh(&ovpnmgr_ctx.lock);
+		return;
+	}
+
+	/*
+	 * Get per tunnel statistics.
+	 */
+	list_for_each_entry(tun, &app->tun_list, list) {
+		nss_ovpnmgr_tun_stats_update(tun, stats);
+	}
+
+	write_unlock_bh(&ovpnmgr_ctx.lock);
+}
+
+/*
+ * nss_ovpnmgr_tun_route_update()
+ *	Update route state
+ */
+void nss_ovpnmgr_tun_route_update(uint32_t tunnel_id, uint32_t *from_addr, uint32_t *to_addr, int version)
+{
+	struct nss_ovpnmgr_route_tuple rt;
+	struct nss_ovpnmgr_tun *tun;
+	struct net_device *tun_dev;
+	int addr_size;
+
+	tun_dev = dev_get_by_index(&init_net, tunnel_id);
+	if (!tun_dev) {
+		nss_ovpnmgr_warn("Couldn't find tunnel with tunnel_id = %d\n", tunnel_id);
+		return;
+	}
+
+	tun = netdev_priv(tun_dev);
+
+	addr_size = version == IPVERSION ? sizeof(rt.ip_addr[0]) : sizeof(rt.ip_addr);
+
+	memset(&rt, 0, sizeof(rt));
+
+	rt.ip_version = version;
+	memcpy(rt.ip_addr, from_addr, addr_size);
+
+	write_lock_bh(&ovpnmgr_ctx.lock);
+	/*
+	 * Set route active for from_addr.
+	 */
+	if (!nss_ovpnmgr_route_set_active(&tun->route_list, &rt)) {
+		goto done;
+	}
+
+	/*
+	 * Route is not found for from_addr, set route active for to_addr.
+	 */
+	memcpy(rt.ip_addr, to_addr, addr_size);
+
+	nss_ovpnmgr_route_set_active(&tun->route_list, &rt);
+done:
+	write_unlock_bh(&ovpnmgr_ctx.lock);
+	dev_put(tun_dev);
+}
+EXPORT_SYMBOL(nss_ovpnmgr_tun_route_update);
+
+/*
+ * nss_ovpnmgr_tun_stats_get()
+ *	Get statistics of tunnel
+ */
+int nss_ovpnmgr_tun_stats_get(uint32_t tunnel_id, struct nss_ovpnmgr_tun_stats *stats)
+{
+	struct nss_ovpnmgr_tun *tun;
+	struct net_device *tun_dev;
+
+	tun_dev = dev_get_by_index(&init_net, tunnel_id);
+	if (!tun_dev) {
+		nss_ovpnmgr_warn("Couldn't find tunnel with tunnel_id = %d\n", tunnel_id);
+		return -EINVAL;
+	}
+
+	tun = netdev_priv(tun_dev);
+
+	write_lock_bh(&ovpnmgr_ctx.lock);
+	stats->tun_read_bytes  = tun->stats.tun_read_bytes;
+	stats->tun_write_bytes = tun->stats.tun_write_bytes;
+	stats->link_read_bytes = tun->stats.link_read_bytes;
+	stats->link_read_bytes_auth = tun->stats.link_read_bytes_auth;
+	stats->link_write_bytes = tun->stats.link_write_bytes;
+	memset(&tun->stats, 0, sizeof(tun->stats));
+	write_unlock_bh(&ovpnmgr_ctx.lock);
+
+	dev_put(tun_dev);
+	return 0;
+}
+EXPORT_SYMBOL(nss_ovpnmgr_tun_stats_get);
+
+/*
+ * nss_ovpnmgr_tun_tx()
+ *	Transmit packet to NSS firmware for encapsulation/decapsulation.
+ */
+int nss_ovpnmgr_tun_tx(uint32_t tunnel_id, struct nss_ovpnmgr_metadata *mdata, struct sk_buff *skb)
+{
+	struct nss_ovpnmgr_tun_ctx_stats *stats;
+	struct nss_ovpnmgr_tun *tun;
+	struct net_device *tun_dev;
+	nss_tx_status_t status;
+	bool expand_skb = false;
+	uint32_t ifnum;
+	uint16_t nhead;
+	uint16_t ntail;
+	int err;
+
+	tun_dev = dev_get_by_index(&init_net, tunnel_id);
+	if (!tun_dev) {
+		nss_ovpnmgr_warn("%px: Couldn't find tunnel with tunnel_id = %d\n", skb, mdata->tunnel_id);
+		return -EINVAL;
+	}
+
+	tun = netdev_priv(tun_dev);
+	nss_ovpnmgr_info("%px: metadata flags (0x%x)\n", tun, mdata->flags);
+
+	nhead = tun_dev->needed_headroom;
+	ntail = tun_dev->needed_tailroom;
+
+	read_lock_bh(&ovpnmgr_ctx.lock);
+	if (mdata->flags & NSS_OVPNMGR_METADATA_FLAG_PKT_DECAP) {
+		ifnum = tun->outer.ifnum;
+		stats = &tun->outer.stats;
+	} else {
+		ifnum = tun->inner.ifnum;
+		stats = &tun->inner.stats;
+	}
+	read_unlock_bh(&ovpnmgr_ctx.lock);
+
+	/*
+	 * Check if skb is shared
+	 */
+	if (unlikely(skb_shared(skb))) {
+		skb = skb_unshare(skb, in_atomic() ? GFP_ATOMIC : GFP_KERNEL);
+		if (!skb) {
+			nss_ovpnmgr_trace("%px: unable to expand skb, dev = %s\n", tun, tun_dev->name);
+			err = -ENOSPC;
+			goto free;
+		}
+	}
+
+	if (skb_cloned(skb) || (skb_headroom(skb) < nhead) || (skb_tailroom(skb) < ntail)) {
+		expand_skb = true;
+	}
+
+	if (expand_skb && pskb_expand_head(skb, nhead, ntail, in_atomic() ? GFP_ATOMIC : GFP_KERNEL)) {
+		nss_ovpnmgr_trace("%px: unable to expand skb, dev = %s\n", tun, tun_dev->name);
+		err = -ENOMEM;
+		goto free;
+	}
+
+	/*
+	 * Dump IPv4/v6 header (40) + transport header (8) + ovpn header (4)
+	 */
+	NSS_OVPNMGR_TUN_PKT_DUMP(skb, "Pkt to NSS", 0, 52);
+
+	status = nss_qvpn_tx_buf(tun->nss_ctx, ifnum, skb);
+	if (status != NSS_TX_SUCCESS) {
+		nss_ovpnmgr_trace("%px: Packet offload failed, status = %d\n", tun, status);
+		err = (status == NSS_TX_FAILURE_QUEUE) ? -EBUSY : -EINVAL;
+		goto free;
+	}
+
+	dev_put(tun_dev);
+	return 0;
+free:
+	write_lock_bh(&ovpnmgr_ctx.lock);
+	stats->host_pkt_drop++;
+	write_unlock_bh(&ovpnmgr_ctx.lock);
+
+	dev_put(tun_dev);
+	return err;
+}
+EXPORT_SYMBOL(nss_ovpnmgr_tun_tx);
+
+/*
+ * nss_ovpnmgr_tun_del()
+ *	Delete tunnel.
+ */
+int nss_ovpnmgr_tun_del(uint32_t tunnel_id)
+{
+	struct nss_ovpnmgr_route *route, *n;
+	struct nss_ovpnmgr_tun *tun;
+	struct net_device *tun_dev;
+
+	tun_dev = dev_get_by_index(&init_net, tunnel_id);
+	if (!tun_dev) {
+		nss_ovpnmgr_warn("Couldn't find tunnel: tunnel_id = %u\n\n", tunnel_id);
+		return -EINVAL;
+	}
+
+	tun = netdev_priv(tun_dev);
+
+	nss_ovpnmgr_info("%px: Deleting Tunnel, tunnel_id = %d\n", tun, tun->tunnel_id);
+
+	write_lock_bh(&ovpnmgr_ctx.lock);
+	/*
+	 * Delete Routes from the tunnel.
+	 */
+	list_for_each_entry_safe(route, n, &tun->route_list, list) {
+		list_del(&route->list);
+		kfree(route);
+	}
+
+	/*
+	 * Remove this tunnel from tunnel list.
+	 */
+	list_del(&tun->list);
+	write_unlock_bh(&ovpnmgr_ctx.lock);
+
+	/*
+	 * Release tun_dev before freeing tunnel.
+	 */
+	dev_put(tun_dev);
+	/*
+	 * Unregister ovpn netdevice.
+	 */
+	rtnl_is_locked() ? unregister_netdevice(tun_dev) : unregister_netdev(tun_dev);
+	return 0;
+}
+EXPORT_SYMBOL(nss_ovpnmgr_tun_del);
+
+/*
+ * nss_ovpnmgr_tun_add()
+ *	Add new tunnel.
+ */
+uint32_t nss_ovpnmgr_tun_add(struct net_device *app_dev,
+			struct nss_ovpnmgr_tun_tuple *tun_hdr,
+			struct nss_ovpnmgr_tun_config *tun_cfg,
+			struct nss_ovpnmgr_crypto_config *crypto_cfg)
+{
+	struct nss_ovpnmgr_app *app;
+	struct nss_ovpnmgr_tun *tun;
+	struct net_device *tun_dev;
+	int status;
+
+	nss_ovpnmgr_tun_config_dump(app_dev, tun_hdr, tun_cfg, crypto_cfg);
+
+	/*
+	 * Veryify tunnel configuration parameters.
+	 */
+	status = nss_ovpnmgr_tun_config_verify(tun_hdr, tun_cfg);
+	if (status < 0) {
+		nss_ovpnmgr_warn("%px: Tunnel configuration parameters are invalid, status=%d.\n", app_dev, status);
+		return 0;
+	}
+
+	read_lock_bh(&ovpnmgr_ctx.lock);
+	app = nss_ovpnmgr_app_find(app_dev);
+	if (!app) {
+		read_unlock_bh(&ovpnmgr_ctx.lock);
+		nss_ovpnmgr_warn("%px: Couldn't find app for app_dev=%s\n", app_dev, app_dev->name);
+		return 0;
+	}
+
+	/*
+	 * Hold the device until we add the tunnel.
+	 */
+	dev_hold(app_dev);
+	read_unlock_bh(&ovpnmgr_ctx.lock);
+
+	tun = nss_ovpnmgr_tun_alloc();
+	if (!tun) {
+		nss_ovpnmgr_warn("%px: Tunnel allocation failed.\n", app);
+		dev_put(app_dev);
+		return 0;
+	}
+
+	tun_dev = tun->dev;
+
+	/*
+	 * Copy tunnel header parameters.
+	 */
+	memcpy(&tun->tun_hdr, tun_hdr, sizeof(*tun_hdr));
+	tun->tun_cfg.flags = tun_cfg->flags;
+
+	/*
+	 * Initialize tunnel inner context.
+	 */
+	if (nss_ovpnmgr_tun_ctx_inner_init(tun, crypto_cfg)) {
+		nss_ovpnmgr_error("%px: Failed to initialize inner context.\n", app);
+		goto free_tun;
+	}
+
+	/*
+	 * Initialize tunnel outer context.
+	 */
+	if (nss_ovpnmgr_tun_ctx_outer_init(tun, crypto_cfg)) {
+		nss_ovpnmgr_error("%px: Failed to initialize outer context.\n", app);
+		goto free_inner;
+	}
+
+	/*
+	 * Configure inner node.
+	 */
+	if (nss_ovpnmgr_tun_inner_config(tun)) {
+		nss_ovpnmgr_warn("%px: inner node tunnel configuration failed\n", tun);
+		goto free_outer;
+	}
+
+	/*
+	 * Configure outer node.
+	 */
+	if (nss_ovpnmgr_tun_outer_config(tun)) {
+		nss_ovpnmgr_warn("%px: Outer node tunnel configuration failed\n", tun);
+		goto free_inner_config;
+	}
+
+	/*
+	 * Register netdev.
+	 */
+	status = rtnl_is_locked() ? register_netdevice(tun_dev) : register_netdev(tun_dev);
+	if (status < 0) {
+		nss_ovpnmgr_warn("register net dev failed :%s\n", tun_dev->name);
+		goto free_outer_config;
+	}
+
+	/*
+	 * Assign ifindex as tunnel_id as it is unique.
+	 */
+	tun->tunnel_id = tun_dev->ifindex;
+	tun->app = app;
+
+	write_lock_bh(&ovpnmgr_ctx.lock);
+	list_add(&tun->list, &app->tun_list);
+	write_unlock_bh(&ovpnmgr_ctx.lock);
+
+	dev_put(app_dev);
+	return tun->tunnel_id;
+
+free_outer_config:
+	nss_ovpnmgr_tun_deconfig(&tun->outer, tun);
+free_inner_config:
+	nss_ovpnmgr_tun_deconfig(&tun->inner, tun);
+free_outer:
+	nss_ovpnmgr_tun_ctx_deinit(&tun->outer);
+free_inner:
+	nss_ovpnmgr_tun_ctx_deinit(&tun->inner);
+free_tun:
+	free_netdev(tun_dev);
+	dev_put(app_dev);
+
+	return 0;
+}
+EXPORT_SYMBOL(nss_ovpnmgr_tun_add);
diff --git a/qca-nss-clients/openvpn/src/nss_ovpnmgr_tun.h b/qca-nss-clients/openvpn/src/nss_ovpnmgr_tun.h
new file mode 100644
index 0000000..a28b21a
--- /dev/null
+++ b/qca-nss-clients/openvpn/src/nss_ovpnmgr_tun.h
@@ -0,0 +1,82 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ovpnmgr_tun.h
+ */
+#ifndef _NSS_OVPNMGR_TUN_H
+#define _NSS_OVPNMGR_TUN_H
+
+#define NSS_OVPNMGR_TUN_NAME "ovpn%d"
+
+/*
+ * nss_ovpnmgr_tun_ctx_stats
+ *	Tunnel statistics received from NSS firmware.
+ */
+struct nss_ovpnmgr_tun_ctx_stats {
+	uint64_t exception[NSS_QVPN_EXCEPTION_EVENT_MAX];	/* Exception statistics. */
+	uint64_t fail_crypto[NSS_CRYPTO_CMN_RESP_ERROR_MAX];	/* Crypto response errors. */
+	uint64_t fail_offload[NSS_QVPN_PKT_DROP_EVENT_MAX];	/* Packets drop events.*/
+	uint64_t rx_dropped[NSS_MAX_NUM_PRI];			/* Packets dropped on receive due to queue full. */
+	uint64_t rx_packets;					/* Number of packets received. */
+	uint64_t rx_bytes;					/* Number of bytes received. */
+	uint64_t tx_packets;					/* Number of packets transmitted. */
+	uint64_t tx_bytes;					/* Number of bytes transmitted. */
+	uint64_t host_pkt_drop;					/* Packet drops in host. */
+};
+
+/*
+ * nss_ovpnmgr_tun_ctx
+ *	Tunnel context.
+ */
+struct nss_ovpnmgr_tun_ctx {
+	struct nss_ctx_instance *nss_ctx;	/* OVPN nss context. */
+	struct nss_ovpnmgr_crypto_ctx active;	/* Crypto context for active key. */
+	struct nss_ovpnmgr_crypto_ctx expiring;	/* Crypto context for expiring key. */
+	struct nss_ovpnmgr_tun_ctx_stats stats;	/* Tunnel statistics. */
+	int32_t ifnum;				/* Dynamic interface for OVPN encapsulation. */
+	uint32_t di_type;			/* Dynamic interface type. */
+};
+
+/*
+ * nss_ovpnmgr_tun
+ *	Tunnel instance.
+ */
+struct nss_ovpnmgr_tun {
+	struct list_head list;					/* List of OVPN Tunnels created by the application. */
+	struct nss_ovpnmgr_app *app;				/* Application reference. */
+	struct nss_ovpnmgr_tun_tuple tun_hdr;			/* OVPN tunnel header parameters. */
+	struct nss_ovpnmgr_tun_config tun_cfg;			/* OVPN tunnel header parameters. */
+	struct nss_ovpnmgr_tun_ctx inner;			/* Inner tunnel context. */
+	struct nss_ovpnmgr_tun_ctx outer;			/* Outer tunnel context. */
+	struct nss_qvpn_hdr_configure_msg ovpn_hdr;		/* OVPN header for QVPN configuration. */
+	struct nss_ctx_instance *nss_ctx;			/* OVPN NSS context. */
+	struct nss_ovpnmgr_tun_stats stats;			/* OVPN tunnel statistics. */
+	struct list_head route_list;				/* List of Routes configured in this tunnel. */
+	uint32_t tunnel_id;					/* Tunnel id assigned during tunnel addition. */
+	struct net_device *dev;					/* Tunnel netdev. */
+};
+
+static inline void nss_ovpnmgr_ipv6_addr_ntohl(uint32_t *host, uint32_t *net)
+{
+	host[0] = ntohl(net[0]);
+	host[1] = ntohl(net[1]);
+	host[2] = ntohl(net[2]);
+	host[3] = ntohl(net[3]);
+}
+
+void nss_ovpnmgr_tun_get_stats(struct net_device *app_dev, struct rtnl_link_stats64 *stats);
+#endif /* _NSS_OVPNMGR_TUN_H */
diff --git a/qca-nss-clients/portifmgr/Makefile b/qca-nss-clients/portifmgr/Makefile
new file mode 100644
index 0000000..47a3fac
--- /dev/null
+++ b/qca-nss-clients/portifmgr/Makefile
@@ -0,0 +1,14 @@
+ccflags-y := -I$(obj)/../exports -I$(obj)/..  -I$(obj)/nss_hal/include
+ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)"
+
+#
+# If you want to build qca-nss-portifmgr with QCA Ref design AP148 support
+# set NSS_PORTIFMGR_REF_AP148
+#     ccflags-y += -DNSS_PORTIFMGR_REF_AP148
+# Otherwise qca-nss-portifmgr will only provide APIs for creating interfaces
+
+obj-m += qca-nss-portifmgr.o
+qca-nss-portifmgr-objs := nss_portifmgr.o
+
+ccflags-y += -DNSS_PORTIFMGR_DEBUG_LEVEL=2 #-DNSS_PORTIFMGR_REF_AP148
+ccflags-y += -Wall -Werror
diff --git a/qca-nss-clients/portifmgr/nss_portifmgr.c b/qca-nss-clients/portifmgr/nss_portifmgr.c
new file mode 100644
index 0000000..80a6277
--- /dev/null
+++ b/qca-nss-clients/portifmgr/nss_portifmgr.c
@@ -0,0 +1,440 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2016, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_portifmgr.c
+ *	NSS to HLOS Port Interface manager
+ */
+#include <linux/module.h>
+#include <linux/etherdevice.h>
+#include <linux/if_arp.h>
+#include <linux/rtnetlink.h>
+#include <nss_api_if.h>
+#include <nss_gmac_api_if.h>
+
+#include <nss_portifmgr.h>
+
+#define NSS_PORTIFMGR_EXTRA_HEADER_SIZE	4
+
+/*
+ * Features enabled for portifmgr, note we are not able to enable HW_CSUM
+ * related features because GMAC HW can't do checksum offloading when
+ * proprietary header inserted
+ */
+#define NSS_PORTIFMGR_SUPPORTED_FEATURES (NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_FRAGLIST)
+
+#if (NSS_PORTIFMGR_DEBUG_LEVEL < 1)
+#define nss_portifmgr_assert(fmt, args...)
+#else
+#define nss_portifmgr_assert(c) BUG_ON(!(c))
+#endif /* NSS_PORTIFMGR_DEBUG_LEVEL */
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_portifmgr_warn(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_portifmgr_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_portifmgr_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#else /* CONFIG_DYNAMIC_DEBUG */
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_PORTIFMGR_DEBUG_LEVEL < 2)
+#define nss_portifmgr_warn(s, ...)
+#else
+#define nss_portifmgr_warn(s, ...) pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_PORTIFMGR_DEBUG_LEVEL < 3)
+#define nss_portifmgr_info(s, ...)
+#else
+#define nss_portifmgr_info(s, ...)   pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_PORTIFMGR_DEBUG_LEVEL < 4)
+#define nss_portifmgr_trace(s, ...)
+#else
+#define nss_portifmgr_trace(s, ...)  pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+#ifdef NSS_PORTIFMGR_REF_AP148
+/*
+ * This holds all the netdev created on the switch ports
+ */
+struct net_device *ndev_list[NSS_PORTID_MAX_SWITCH_PORT];
+#endif
+
+/*
+ * nss_portifmgr_receive_pkt()
+ *	Receives a pkt from NSS
+ */
+static void nss_portifmgr_receive_pkt(struct net_device *dev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	struct nss_portifmgr_priv *priv;
+
+	/* SKB NETIF START */
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+
+	skb->dev = dev;
+	skb->protocol = eth_type_trans(skb, dev);
+
+	nss_portifmgr_trace("%s: Rx on if_num %d, packet len %d, CSUM %d\n",
+			__func__, priv->if_num, skb->len, skb->ip_summed);
+
+	(void)netif_receive_skb(skb);
+	/* SKB NETIF END */
+	dev_put(dev);
+}
+
+/*
+ * nss_portifmgr_open()
+ *	Netdev's open call.
+ */
+static int nss_portifmgr_open(struct net_device *dev)
+{
+	struct nss_portifmgr_priv *priv = (struct nss_portifmgr_priv *)netdev_priv(dev);
+
+	if (!priv->nss_ctx) {
+		nss_portifmgr_warn("%px: %s registration to NSS not completed yet\n", dev, dev->name);
+		return -EAGAIN;
+	}
+	netif_start_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_portifmgr_close()
+ *	Netdev's close call.
+ */
+static int nss_portifmgr_close(struct net_device *dev)
+{
+	netif_stop_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_portifmgr_start_xmit()
+ *	Transmit skb to NSS FW over portid if_num.
+ */
+static netdev_tx_t nss_portifmgr_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+
+	struct net_device_stats *stats = &dev->stats;
+	struct nss_portifmgr_priv *priv;
+	const unsigned char *dest = skb->data;
+	struct sk_buff *tx_skb = skb;
+	nss_tx_status_t status;
+
+	priv = netdev_priv(dev);
+
+	/*
+	 * Drop if trying to xmit when registration to NSS is not completed yet.
+	 */
+	if (!priv->nss_ctx) {
+		nss_portifmgr_warn("%px: sending without ctx: if_num %d port_id %d\n",
+					dev, priv->port_id, priv->if_num);
+		goto drop;
+	}
+
+	if (skb_headroom(skb) < NSS_PORTIFMGR_EXTRA_HEADER_SIZE) {
+		nss_portifmgr_warn("%px: headroom not enough skb: %px\n", dev, skb);
+		goto drop;
+	}
+
+	/*
+	 * For a multicast/broadcast skb, linux is trying to send the same
+	 * skb->data to all interfaces. But we are going to add port header
+	 * inside the eth_header. The 2nd interface will get a skb that eth_hdr
+	 * is already have a portid header. We need to make a copy to avoid this
+	 */
+	if (!is_unicast_ether_addr(dest)) {
+		tx_skb = skb_copy(skb, GFP_KERNEL);
+		kfree_skb(skb);
+		if (!tx_skb) {
+			nss_portifmgr_warn("%px: failed to copy skb\n", dev);
+			stats->tx_dropped++;
+			return NETDEV_TX_OK;
+		}
+	}
+
+	status = nss_portid_if_tx_data(priv->nss_ctx, tx_skb, priv->if_num);
+	if (likely(status == NSS_TX_SUCCESS)) {
+		return NETDEV_TX_OK;
+	}
+	nss_portifmgr_warn("%px: portid interface failed to xmit the packet : %d\n",
+								dev, status);
+
+drop:
+	kfree_skb(tx_skb);
+	stats->tx_dropped++;
+	return NETDEV_TX_OK;
+}
+
+/*
+ * nss_portifmgr_get_stats()
+ *	Netdev get stats function to get port stats
+ */
+static struct rtnl_link_stats64 *nss_portifmgr_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	struct nss_portifmgr_priv *priv = (struct nss_portifmgr_priv *)netdev_priv(dev);
+	BUG_ON(priv == NULL);
+
+	nss_portid_get_stats(priv->if_num, stats);
+	return stats;
+}
+
+/*
+ * nss_portifmgr_change_mtu()
+ *	Netdev change mtu function
+ */
+int nss_portifmgr_change_mtu(struct net_device *dev, int new_mtu)
+{
+	struct nss_portifmgr_priv *priv = (struct nss_portifmgr_priv *)netdev_priv(dev);
+
+	if ((new_mtu + NSS_PORTIFMGR_EXTRA_HEADER_SIZE) > priv->real_dev->mtu) {
+		return -ERANGE;
+	}
+
+	dev->mtu = new_mtu;
+	return 0;
+}
+
+/*
+ * nss_portifmgr_netdev_ops
+ *	Netdev operations.
+ */
+static const struct net_device_ops nss_portifmgr_netdev_ops = {
+	.ndo_open		= nss_portifmgr_open,
+	.ndo_stop		= nss_portifmgr_close,
+	.ndo_start_xmit		= nss_portifmgr_start_xmit,
+	.ndo_set_mac_address	= eth_mac_addr,
+	.ndo_change_mtu		= nss_portifmgr_change_mtu,
+	.ndo_get_stats64	= nss_portifmgr_get_stats,
+};
+
+/*
+ * nss_portifmgr_create_if()
+ *	API to create netdev and dynamic interfaces that mapped to switch port and gmac
+ */
+struct net_device *nss_portifmgr_create_if(int port_id, int gmac_id, const char *name)
+{
+	struct net_device *ndev, *real_dev;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_portifmgr_priv *priv;
+	int err, if_num;
+	nss_tx_status_t status;
+
+	real_dev = nss_gmac_get_netdev_by_macid(gmac_id);
+	if (!real_dev) {
+		nss_portifmgr_warn("Underlying gmac%d netdevice does not exist!\n", gmac_id);
+		return NULL;
+	}
+
+	ndev = alloc_etherdev(sizeof(struct nss_portifmgr_priv));
+	if (!ndev) {
+		nss_portifmgr_warn("Error allocating netdev\n");
+		return NULL;
+	}
+
+	/*
+	 * Setup net_device
+	 */
+	ndev->netdev_ops = &nss_portifmgr_netdev_ops;
+	ndev->needed_headroom = NSS_PORTIFMGR_EXTRA_HEADER_SIZE;
+	ndev->features |= NSS_PORTIFMGR_SUPPORTED_FEATURES;
+	ndev->hw_features |= NSS_PORTIFMGR_SUPPORTED_FEATURES;
+	ndev->vlan_features |= NSS_PORTIFMGR_SUPPORTED_FEATURES;
+	ndev->wanted_features |= NSS_PORTIFMGR_SUPPORTED_FEATURES;
+	ndev->mtu = real_dev->mtu - NSS_PORTIFMGR_EXTRA_HEADER_SIZE;
+	strlcpy(ndev->name, name, IFNAMSIZ);
+
+	/*
+	 * Setup temp mac address, this can be changed with ifconfig later
+	 */
+	memcpy(ndev->dev_addr, "\x00\x03\x7f\x11\x22\x00", ETH_ALEN);
+	ndev->dev_addr[5] = 0x10 + port_id;
+
+	err = register_netdev(ndev);
+	if (err) {
+		nss_portifmgr_warn("Register_netdev() fail with error :%d\n", err);
+		free_netdev(ndev);
+		return NULL;
+	}
+
+	if_num = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_PORTID);
+	if (if_num < 0) {
+		nss_portifmgr_warn("Dynamic interface alloc failed\n");
+		goto fail;
+	}
+
+	/*
+	 * Register port interface with NSS
+	 */
+	nss_ctx = nss_portid_register_port_if(if_num, port_id, ndev, nss_portifmgr_receive_pkt);
+	if (!nss_ctx) {
+		goto fail2;
+	}
+
+	/*
+	 * Fill in information in the netdev priv structure
+	 */
+	priv = netdev_priv(ndev);
+	priv->nss_ctx = nss_ctx;
+	priv->real_dev = real_dev;
+	priv->if_num = if_num;
+	priv->port_id = port_id;
+
+	/*
+	 * Send msg to configure port in NSS FW
+	 */
+	status = nss_portid_tx_configure_port_if_msg(nss_ctx, if_num, port_id, gmac_id);
+	if (status == NSS_TX_SUCCESS) {
+		dev_hold(real_dev);
+		return ndev;
+	}
+
+	/*
+	 * Failure handling
+	 */
+	nss_portid_unregister_port_if(if_num);
+fail2:
+	(void)nss_dynamic_interface_dealloc_node(if_num, NSS_DYNAMIC_INTERFACE_TYPE_PORTID);
+
+fail:
+	unregister_netdev(ndev);
+	free_netdev(ndev);
+	return NULL;
+}
+EXPORT_SYMBOL(nss_portifmgr_create_if);
+
+/*
+ * nss_portifmgr_destroy_if()
+ *	API to destroy netdev and the dynamic interfaces associated with it
+ */
+void nss_portifmgr_destroy_if(struct net_device *ndev)
+{
+	struct nss_portifmgr_priv *priv = netdev_priv(ndev);
+	nss_tx_status_t status;
+
+	/*
+	 * Release ref for the real gmac net_device
+	 */
+	dev_put(priv->real_dev);
+
+	/*
+	 * Unconfigure port
+	 */
+	status = nss_portid_tx_unconfigure_port_if_msg(priv->nss_ctx, priv->if_num, priv->port_id);
+	if (status != NSS_TX_SUCCESS) {
+		nss_portifmgr_warn("%px: destroy if_num %d failed\n", priv->nss_ctx, priv->if_num);
+	}
+
+	/*
+	 * Unregister from NSS
+	 */
+	nss_portid_unregister_port_if(priv->if_num);
+
+	/*
+	 * Release dynamic interface
+	 */
+	(void)nss_dynamic_interface_dealloc_node(priv->if_num, NSS_DYNAMIC_INTERFACE_TYPE_PORTID);
+
+	/*
+	 * Unregister net_device
+	 */
+	rtnl_is_locked() ? unregister_netdevice(ndev) : unregister_netdev(ndev);
+}
+EXPORT_SYMBOL(nss_portifmgr_destroy_if);
+
+#ifdef NSS_PORTIFMGR_REF_AP148
+/*
+ * nss_portifmgr_create_interfaces_ap148()
+ *	Sample function to create port interfaces on AP148 ref design
+ */
+void nss_portifmgr_create_interfaces_ap148(void)
+{
+	int i = 0;
+	ndev_list[i] = nss_portifmgr_create_if(1, 2, "lan%d");
+	if (!ndev_list[i]) {
+		nss_portifmgr_warn("Creating lan0 interface on port 1 failed\n");
+		return;
+	}
+
+	ndev_list[++i] = nss_portifmgr_create_if(2, 2, "lan%d");
+	if (!ndev_list[i]) {
+		nss_portifmgr_warn("Creating lan1 interface on port 2 failed\n");
+		return;
+	}
+
+	ndev_list[++i] = nss_portifmgr_create_if(3, 2, "lan%d");
+	if (!ndev_list[i]) {
+		nss_portifmgr_warn("Creating lan2 interface on port 3 failed\n");
+		return;
+	}
+}
+
+/*
+ * nss_portifmgr_destroy_all_interfaces()
+ *	Destroy all the created interfaces
+ */
+void nss_portifmgr_destroy_all_interfaces(void)
+{
+	int i;
+
+	for (i = 0; i < NSS_PORTID_MAX_SWITCH_PORT; i++) {
+		if (ndev_list[i]) {
+			nss_portifmgr_destroy_if(ndev_list[i]);
+			ndev_list[i] = NULL;
+		}
+	}
+}
+#endif
+
+/*
+ * nss_portifmgr_init_module()
+ *	portifmgr module init function
+ */
+int __init nss_portifmgr_init_module(void)
+{
+	pr_info("module (platform - IPQ806x , Build %s) loaded\n",
+			 NSS_CLIENT_BUILD_ID);
+
+#ifdef NSS_PORTIFMGR_REF_AP148
+	nss_portifmgr_create_interfaces_ap148();
+#endif
+	return 0;
+}
+
+/*
+ * nss_portifmgr_exit_module()
+ *	portifmgr module exit function
+ */
+void __exit nss_portifmgr_exit_module(void)
+{
+#ifdef NSS_PORTIFMGR_REF_AP148
+	nss_portifmgr_destroy_all_interfaces();
+#endif
+	pr_info("module unloaded\n");
+}
+
+module_init(nss_portifmgr_init_module);
+module_exit(nss_portifmgr_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS port interface manager");
diff --git a/qca-nss-clients/portifmgr/nss_portifmgr.h b/qca-nss-clients/portifmgr/nss_portifmgr.h
new file mode 100644
index 0000000..aa1b5b9
--- /dev/null
+++ b/qca-nss-clients/portifmgr/nss_portifmgr.h
@@ -0,0 +1,54 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_portifmgr.h
+ *	Port interface manager for NSS
+ */
+#ifndef __NSS_PORTIFMGR_H
+#define __NSS_PORTIFMGR_H
+
+/*
+ * portid interface net_device private structure
+ */
+struct nss_portifmgr_priv {
+	struct nss_ctx_instance *nss_ctx;	/**< Pointer to NSS context */
+	struct net_device *real_dev;		/**< Pointer to the real gmac net_device */
+	int if_num;				/**< Interface number */
+	int port_id;				/**< Switch port id */
+};
+
+/**
+ * @brief Create a net_device on a switch port
+ *
+ * @param port_id mapped port id
+ * @param gmac_id mapped gmac id
+ * @param name net_device name
+ *
+ * @return created net_device
+ */
+extern struct net_device *nss_portifmgr_create_if(int port_id, int gmac_id, const char *name);
+
+/**
+ * @brief Destroy a port interface net_device
+ *
+ * @param ndev net_device to be destroyed
+ *
+ * @return none
+ */
+extern void nss_portifmgr_destroy_if(struct net_device *ndev);
+#endif /* __NSS_PORTIFMGR_H */
+
diff --git a/qca-nss-clients/pppoe/Makefile b/qca-nss-clients/pppoe/Makefile
new file mode 100644
index 0000000..3ee05b7
--- /dev/null
+++ b/qca-nss-clients/pppoe/Makefile
@@ -0,0 +1,10 @@
+# Makefile for pppoe client
+ccflags-y += -I$(obj)/../exports -I$(obj)/..  -I$(obj)/nss_hal/include
+ccflags-y += -DNSS_PPPOE_DEBUG_LEVEL=0
+ccflags-y += -Wall -Werror
+obj-m += qca-nss-pppoe.o
+qca-nss-pppoe-objs := nss_connmgr_pppoe.o
+
+ifneq (,$(filter $(CONFIG_BONDING),y m))
+ccflags-y += -DBONDING_SUPPORT
+endif
diff --git a/qca-nss-clients/pppoe/nss_connmgr_pppoe.c b/qca-nss-clients/pppoe/nss_connmgr_pppoe.c
new file mode 100755
index 0000000..00bc794
--- /dev/null
+++ b/qca-nss-clients/pppoe/nss_connmgr_pppoe.c
@@ -0,0 +1,441 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/rwlock_types.h>
+#include <linux/hashtable.h>
+#include <linux/inetdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/ip.h>
+#include <net/ipv6.h>
+#include <linux/if_arp.h>
+#include <net/route.h>
+#include <linux/if_pppox.h>
+#include <net/ip.h>
+#include <linux/if_bridge.h>
+#include <net/bonding.h>
+#ifdef CONFIG_OF
+#include <linux/of.h>
+#endif
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+#include "nss_connmgr_pppoe.h"
+
+#define HASH_BUCKET_SIZE 2  /* ( 2^ HASH_BUCKET_SIZE ) == 4 */
+
+static DEFINE_HASHTABLE(pppoe_session_table, HASH_BUCKET_SIZE);
+
+/*
+ * nss_connmgr_pppoe_get_session()
+ *	Retrieve pppoe session associated with this netdevice if any
+ */
+static int nss_connmgr_pppoe_get_session(struct net_device *dev,  struct pppoe_opt *addressing)
+{
+	struct ppp_channel *channel[1] = {NULL};
+	int px_proto;
+	int ppp_ch_count;
+
+	if (ppp_is_multilink(dev)) {
+		nss_connmgr_pppoe_warn("%px: channel is multilink PPP\n", dev);
+		return -1;
+	}
+
+	ppp_ch_count = ppp_hold_channels(dev, channel, 1);
+	nss_connmgr_pppoe_info("%px: PPP hold channel ret %d\n", dev, ppp_ch_count);
+	if (ppp_ch_count != 1) {
+		nss_connmgr_pppoe_warn("%px: hold channel for netdevice failed\n", dev);
+		return -1;
+	}
+
+	px_proto = ppp_channel_get_protocol(channel[0]);
+	if (px_proto != PX_PROTO_OE) {
+		nss_connmgr_pppoe_warn("%px: session socket is not of type PX_PROTO_OE\n", dev);
+		ppp_release_channels(channel, 1);
+		return -1;
+	}
+
+	if (pppoe_channel_addressing_get(channel[0], addressing)) {
+		nss_connmgr_pppoe_warn("%px: failed to get addressing information\n", dev);
+		ppp_release_channels(channel, 1);
+		return -1;
+	}
+
+	dev_put(addressing->dev);
+	ppp_release_channels(channel, 1);
+	return 0;
+}
+
+/*
+ * nss_connmgr_add_pppoe_session()
+ *	Add PPPoE session entry into Hash table
+ */
+static struct nss_connmgr_pppoe_session_entry *nss_connmgr_add_pppoe_session(struct net_device *dev, struct pppoe_opt *opt)
+
+{
+	struct nss_connmgr_pppoe_session_entry *entry = NULL;
+	struct nss_connmgr_pppoe_session_info *info;
+
+	entry = kmalloc(sizeof(struct nss_connmgr_pppoe_session_entry),
+				      GFP_KERNEL);
+	if (!entry) {
+		nss_connmgr_pppoe_warn("%px: failed to allocate pppoe session entry\n", dev);
+		return NULL;
+	}
+
+	info = &entry->info;
+
+	/*
+	 * Get session info
+	 */
+	info->session_id = (uint16_t)ntohs((uint16_t)opt->pa.sid);
+	ether_addr_copy(info->server_mac, opt->pa.remote);
+	ether_addr_copy(info->local_mac, opt->dev->dev_addr);
+
+	nss_connmgr_pppoe_info("%px: Added PPPoE session with session_id=%u server_mac=%pM local_mac %pM\n",
+			       dev, info->session_id, info->server_mac, info->local_mac);
+
+	entry->dev = dev;
+
+	/*
+	 * There is no need for protecting simultaneous addition &
+	 * deletion of pppoe sesion entry as the PPP notifier chain
+	 * call back is called with mutex lock.
+	 */
+	hash_add_rcu(pppoe_session_table,
+		&entry->hash_list,
+		dev->ifindex);
+
+	return entry;
+}
+
+/*
+ * nss_connmgr_pppoe_disconnect()
+ *	pppoe interface's disconnect event handler
+ */
+static int nss_connmgr_pppoe_disconnect(struct net_device *dev)
+{
+	struct nss_connmgr_pppoe_session_entry *entry;
+	struct nss_connmgr_pppoe_session_entry *found = NULL;
+	struct hlist_node *temp;
+	struct nss_pppoe_msg npm;
+	struct nss_pppoe_destroy_msg *npm_destroy;
+	nss_tx_status_t status;
+	int if_number;
+
+	/*
+	 * check whether the interface is of type PPP
+	 */
+	if (dev->type != ARPHRD_PPP || !(dev->flags & IFF_POINTOPOINT)) {
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Check if pppoe is registered ?
+	 */
+	if_number = nss_cmn_get_interface_number_by_dev(dev);
+	if (if_number < 0) {
+		nss_connmgr_pppoe_warn("%px: Net device is not registered with nss\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	hash_for_each_possible_safe(pppoe_session_table, entry,
+				     temp, hash_list, dev->ifindex) {
+		if (entry->dev != dev) {
+			continue;
+		}
+		/*
+		 * In the hash list, there must be only one entry match with this net device.
+		 */
+		found = entry;
+		break;
+	}
+
+	if (!found) {
+		nss_connmgr_pppoe_warn("%px: PPPoE session is not found for device: %s\n", dev, dev->name);
+		return NOTIFY_DONE;
+	}
+
+	hash_del_rcu(&entry->hash_list);
+	synchronize_rcu();
+
+	memset(&npm, 0, sizeof(struct nss_pppoe_msg));
+	npm_destroy = &npm.msg.destroy;
+	npm_destroy->session_id = entry->info.session_id;
+	ether_addr_copy(npm_destroy->server_mac, entry->info.server_mac);
+	ether_addr_copy(npm_destroy->local_mac, entry->info.local_mac);
+
+	nss_pppoe_msg_init(&npm, if_number, NSS_PPPOE_MSG_SESSION_DESTROY, sizeof(struct nss_pppoe_destroy_msg), NULL, NULL);
+	status = nss_pppoe_tx_msg_sync(nss_pppoe_get_context(), &npm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pppoe_warn("%px: pppoe session destroy command failed, if_number = %d\n", dev, if_number);
+		goto done;
+	}
+	nss_unregister_pppoe_session_if(if_number);
+	status = nss_dynamic_interface_dealloc_node(if_number, NSS_DYNAMIC_INTERFACE_TYPE_PPPOE);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pppoe_warn("%px: pppoe dealloc node failure for if_number=%d\n", dev, if_number);
+	} else {
+		nss_connmgr_pppoe_info("%px: PPPoE session is destroyed with if_number %d, session_id %d, server_mac %pM, local_mac %pM\n",
+				       dev, if_number, entry->info.session_id,
+				       entry->info.server_mac, entry->info.local_mac);
+	}
+done:
+	kfree(entry);
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_connmgr_pppoe_connect()
+ *	pppoe interface's connect event handler
+ */
+static int nss_connmgr_pppoe_connect(struct net_device *dev)
+{
+	struct pppoe_opt opt;
+	struct nss_connmgr_pppoe_session_entry *entry = NULL;
+	struct nss_connmgr_pppoe_session_info *info;
+	nss_tx_status_t status;
+	struct nss_ctx_instance *nss_ctx;
+	uint32_t features = 0;
+	int32_t if_number;
+	struct nss_pppoe_msg npm;
+	struct nss_pppoe_create_msg *npm_create;
+	int ret;
+
+	/*
+	 * check whether the interface is of type PPP
+	 */
+	if (dev->type != ARPHRD_PPP || !(dev->flags & IFF_POINTOPOINT)) {
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Check if pppoe is already registered.
+	 */
+	if_number = nss_cmn_get_interface_number_by_dev(dev);
+	if (if_number >= 0) {
+		nss_connmgr_pppoe_warn("%px: Net device is already registered with nss\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	ret = nss_connmgr_pppoe_get_session(dev, &opt);
+	if (ret < 0) {
+		nss_connmgr_pppoe_warn("%px: Unable to get pppoe session from the netdev\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Create nss dynamic interface and register
+	 */
+	if_number = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_PPPOE);
+	if (if_number == -1) {
+		nss_connmgr_pppoe_warn("%px: Request interface number failed\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	if (!nss_is_dynamic_interface(if_number)) {
+		nss_connmgr_pppoe_warn("%px: Invalid NSS dynamic I/F number %d\n", dev, if_number);
+		goto connect_fail1;
+	}
+
+	nss_connmgr_pppoe_info("%px: PPPoE dynamic interface allocation is successful with if_number %d\n", dev, if_number);
+
+	entry = nss_connmgr_add_pppoe_session(dev, &opt);
+	if (!entry) {
+		nss_connmgr_pppoe_warn("%px: PPPoE session add failed %d\n", dev, if_number);
+		goto connect_fail1;
+	}
+
+	/*
+	 * Register pppoe  tunnel with NSS
+	 */
+	nss_ctx = nss_register_pppoe_session_if(if_number,
+				       NULL,
+				       dev,
+				       features,
+				       entry);
+	if (!nss_ctx) {
+		nss_connmgr_pppoe_warn("%px: nss_register_pppoe_session_if failed\n", dev);
+		goto connect_fail2;
+	}
+
+	nss_connmgr_pppoe_info("%px: PPPoE session interface registration is successful\n", nss_ctx);
+
+	memset(&npm, 0, sizeof(struct nss_pppoe_msg));
+	npm_create = &npm.msg.create;
+	info = &entry->info;
+	npm_create->session_id = info->session_id;
+
+	/*
+	 * PPPoE connection could be on a bridge device like br-wan or on bond device like bond0.
+	 * So, check if the opt device is bridge or bond.
+	 */
+	if (netif_is_bond_master(opt.dev)) {
+		int32_t bondid = -1;
+#if defined(BONDING_SUPPORT)
+		bondid = bond_get_id(opt.dev);
+#endif
+		if (bondid < 0) {
+			nss_connmgr_pppoe_warn("%px: Invalid LAG group id 0x%x\n", dev, bondid);
+			goto connect_fail3;
+		}
+		npm_create->base_if_num = bondid + NSS_LAG0_INTERFACE_NUM;
+	} else if (opt.dev->priv_flags & IFF_EBRIDGE) {
+		/*
+		 * Device is bridge. We need to get the actual physical port.
+		 * Searching this physical port in the fdb database with the server mac
+		 * address of the session.
+		 */
+		struct net_device *port = br_port_dev_get(opt.dev, info->server_mac, NULL, 0);
+		if (!port) {
+			nss_connmgr_pppoe_warn("%px: Unable to get the bridge port device from the bridge interface: %s\n",
+						dev, opt.dev->name);
+			goto connect_fail3;
+		}
+
+		/*
+		 * Get the interface number of the base interface.
+		 */
+		npm_create->base_if_num = nss_cmn_get_interface_number_by_dev(port);
+		nss_connmgr_pppoe_info("local_mac: %pM server_mac: %pM opt.dev: %s base_if: %d\n",
+					info->local_mac, info->server_mac, opt.dev->name, npm_create->base_if_num);
+		/*
+		 * Release the port which was held by the br_port_dev_get() call.
+		 */
+		dev_put(port);
+	} else {
+		/*
+		 * PPPoE sessions can be created over either a physical or virtual interface. They may not be
+		 * created over a LAG or bridge interface. This interface is the base interface which will be used
+		 * for HW next_hop. On SoCs, which do not have HW acceleration, this interface number is not used
+		 * and -1 is returned.
+		 */
+		npm_create->base_if_num = nss_cmn_get_interface_number_by_dev(opt.dev);
+	}
+
+	ether_addr_copy(npm_create->server_mac, info->server_mac);
+	ether_addr_copy(npm_create->local_mac, info->local_mac);
+	npm_create->mtu = dev->mtu;
+
+	nss_connmgr_pppoe_info("%px: pppoe info\n", dev);
+	nss_connmgr_pppoe_info("%px: session_id %d server_mac %pM local_mac %pM base_if %s (%d)\n",
+			       dev, npm_create->session_id,
+			       npm_create->server_mac, npm_create->local_mac, opt.dev->name, npm_create->base_if_num);
+	nss_connmgr_pppoe_info("%px: Sending pppoe session create command to NSS\n", dev);
+
+	nss_pppoe_msg_init(&npm, if_number, NSS_PPPOE_MSG_SESSION_CREATE, sizeof(struct nss_pppoe_create_msg), NULL, NULL);
+
+	status = nss_pppoe_tx_msg_sync(nss_ctx, &npm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pppoe_warn("%px: nss pppoe session creation command error %d\n", dev, status);
+		goto connect_fail3;
+	}
+	nss_connmgr_pppoe_info("%px: PPPoE session creation is successful\n", dev);
+
+	return NOTIFY_DONE;
+
+connect_fail3:
+	nss_unregister_pppoe_session_if(if_number);
+
+connect_fail2:
+	hash_del_rcu(&entry->hash_list);
+	synchronize_rcu();
+	kfree(entry);
+
+connect_fail1:
+	status = nss_dynamic_interface_dealloc_node(if_number, NSS_DYNAMIC_INTERFACE_TYPE_PPPOE);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pppoe_warn("%px: Unable to dealloc the node[%d] in the NSS fw!\n", dev, if_number);
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_connmgr_pppoe_channel_notifier_handler()
+ *	PPPoE channel notifier handler.
+ */
+static int nss_connmgr_pppoe_channel_notifier_handler(struct notifier_block *nb,
+							unsigned long event,
+							void *arg)
+{
+	struct net_device *dev = (struct net_device *)arg;
+
+	switch (event) {
+	case PPP_CHANNEL_CONNECT:
+		return nss_connmgr_pppoe_connect(dev);
+	case PPP_CHANNEL_DISCONNECT:
+		return nss_connmgr_pppoe_disconnect(dev);
+	default:
+		nss_connmgr_pppoe_info("%px: Unhandled channel event: %lu\n", dev, event);
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+struct notifier_block nss_connmgr_pppoe_channel_notifier_nb = {
+        .notifier_call = nss_connmgr_pppoe_channel_notifier_handler,
+};
+
+/*
+ * nss_connmgr_pppoe_exit_module
+ *	pppoe module exit function
+ */
+void __exit nss_connmgr_pppoe_exit_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return;
+	}
+#endif
+
+	/*
+	 * Unregister the module from the PPP channel events.
+	 */
+	ppp_channel_connection_unregister_notify(&nss_connmgr_pppoe_channel_notifier_nb);
+}
+
+/*
+ * nss_connmgr_pppoe_init_module()
+ *	pppoe module init function
+ */
+int __init nss_connmgr_pppoe_init_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+	/*
+	 * Register the module to the PPP channel events.
+	 */
+	ppp_channel_connection_register_notify(&nss_connmgr_pppoe_channel_notifier_nb);
+	return 0;
+}
+
+module_init(nss_connmgr_pppoe_init_module);
+module_exit(nss_connmgr_pppoe_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS pppoe offload manager");
diff --git a/qca-nss-clients/pppoe/nss_connmgr_pppoe.h b/qca-nss-clients/pppoe/nss_connmgr_pppoe.h
new file mode 100644
index 0000000..eed16f8
--- /dev/null
+++ b/qca-nss-clients/pppoe/nss_connmgr_pppoe.h
@@ -0,0 +1,87 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_connnmgr_pppoe.h
+ *	NSS PPPOE client definitions
+ */
+
+#ifndef _NSS_CONNMGR_PPPOE_H_
+#define _NSS_CONNMGR_PPPOE_H_
+/*
+ * Debug macros
+ */
+#if (NSS_PPPOE_DEBUG_LEVEL < 1)
+#define nss_connmgr_pppoe_assert(fmt, args...)
+#else
+#define nss_connmgr_pppoe_assert(c) BUG_ON(!(c))
+#endif
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_connmgr_pppoe_warn(s, ...) pr_debug("%s[%d]:" s, __func__, \
+					  __LINE__, ##__VA_ARGS__)
+#define nss_connmgr_pppoe_info(s, ...) pr_debug("%s[%d]:" s, __func__, \
+					  __LINE__, ##__VA_ARGS__)
+#define nss_connmgr_pppoe_trace(s, ...) pr_debug("%s[%d]:" s, __func__, \
+					   __LINE__, ##__VA_ARGS__)
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_PPPOE_DEBUG_LEVEL < 2)
+#define nss_connmgr_pppoe_warn(s, ...)
+#else
+#define nss_connmgr_pppoe_warn(s, ...) pr_warn("%s[%d]:" s, __func__, \
+					 __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_PPPOE_DEBUG_LEVEL < 3)
+#define nss_connmgr_pppoe_info(s, ...)
+#else
+#define nss_connmgr_pppoe_info(s, ...) pr_notice("%s[%d]:" s, __func__, \
+					   __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_PPPOE_DEBUG_LEVEL < 4)
+#define nss_connmgr_pppoe_trace(s, ...)
+#else
+#define nss_connmgr_pppoe_trace(s, ...)  pr_info("%s[%d]:" s, __func__, \
+					   __LINE__, ##__VA_ARGS__)
+#endif
+#endif
+
+/*
+ * Structure for PPPOE client driver session info
+ */
+struct nss_connmgr_pppoe_session_info {
+	uint32_t session_id;
+	uint8_t server_mac[ETH_ALEN];
+	uint8_t local_mac[ETH_ALEN];
+};
+
+/*
+ * Structure for PPPOE session entry into HASH table
+ */
+struct nss_connmgr_pppoe_session_entry {
+	struct nss_connmgr_pppoe_session_info info;
+	struct net_device *dev;
+	struct hlist_node hash_list;
+};
+#endif
diff --git a/qca-nss-clients/pptp/Makefile b/qca-nss-clients/pptp/Makefile
new file mode 100644
index 0000000..cf5dd62
--- /dev/null
+++ b/qca-nss-clients/pptp/Makefile
@@ -0,0 +1,6 @@
+# Makefile for pptp client
+ccflags-y += -I$(obj)/../exports -I$(obj)/..  -I$(obj)/nss_hal/include
+ccflags-y += -DNSS_PPTP_DEBUG_LEVEL=0
+ccflags-y += -Wall -Werror
+obj-m += qca-nss-pptp.o
+qca-nss-pptp-objs := nss_connmgr_pptp.o
diff --git a/qca-nss-clients/pptp/nss_connmgr_pptp.c b/qca-nss-clients/pptp/nss_connmgr_pptp.c
new file mode 100644
index 0000000..80805c4
--- /dev/null
+++ b/qca-nss-clients/pptp/nss_connmgr_pptp.c
@@ -0,0 +1,889 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/rwlock_types.h>
+#include <linux/hashtable.h>
+#include <linux/inetdevice.h>
+#include <linux/ip.h>
+#include <net/ipv6.h>
+#include <linux/if_arp.h>
+#include <net/route.h>
+#include <linux/if_pppox.h>
+#include <net/ip.h>
+
+#ifdef CONFIG_OF
+#include <linux/of.h>
+#endif
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+#include "nss_connmgr_pptp.h"
+
+#define PPP_HDR_LEN        4
+
+/*
+ * NSS pptp debug macros
+ */
+#if (NSS_PPTP_DEBUG_LEVEL < 1)
+#define nss_connmgr_pptp_assert(fmt, args...)
+#else
+#define nss_connmgr_pptp_assert(c) if (!(c)) { BUG_ON(!(c)); }
+#endif
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_connmgr_pptp_warning(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_connmgr_pptp_info(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_connmgr_pptp_trace(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_PPTP_DEBUG_LEVEL < 2)
+#define nss_connmgr_pptp_warning(s, ...)
+#else
+#define nss_connmgr_pptp_warning(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_PPTP_DEBUG_LEVEL < 3)
+#define nss_connmgr_pptp_info(s, ...)
+#else
+#define nss_connmgr_pptp_info(s, ...)   pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_PPTP_DEBUG_LEVEL < 4)
+#define nss_connmgr_pptp_trace(s, ...)
+#else
+#define nss_connmgr_pptp_trace(s, ...)  pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif
+
+#define NUM_PPTP_CHANNELS_IN_PPP_NETDEVICE  1
+#define HASH_BUCKET_SIZE 2  /* ( 2^ HASH_BUCKET_SIZE ) == 4 */
+
+static DEFINE_HASHTABLE(pptp_session_table, HASH_BUCKET_SIZE);
+
+/*
+ * nss_connmgr_pptp_client_xmit()
+ * 	PPTP GRE seq/ack offload callback handler. Sends SKB to NSS firmware.
+ * 	Note: RCU lock is already held by caller.
+ */
+static int nss_connmgr_pptp_client_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct nss_connmgr_pptp_session_entry *session_info;
+	struct nss_ctx_instance *nss_pptp_ctx;
+	nss_tx_status_t status;
+	int host_inner_if;;
+
+	/*
+	 * Check if pptp host inner I/F is registered ?
+	 */
+	host_inner_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_PPTP_HOST_INNER);
+	if (host_inner_if < 0) {
+		nss_connmgr_pptp_warning("%px: Net device is not registered\n", dev);
+		return -1;
+	}
+
+	nss_pptp_ctx = nss_pptp_get_context();
+	if (!nss_pptp_ctx) {
+		nss_connmgr_pptp_warning("%px: NSS PPTP context not found for if_number %d\n", dev, host_inner_if);
+		return -1;
+	}
+
+	hash_for_each_possible_rcu(pptp_session_table, session_info,
+				    hash_list, dev->ifindex) {
+		if (session_info->dev != dev) {
+			continue;
+		}
+
+		status = nss_pptp_tx_buf(nss_pptp_ctx, host_inner_if, skb);
+		if (status == NSS_TX_SUCCESS) {
+			/*
+			 * Found a match for a session and successfully posted
+			 * packet to firmware. Retrun success.
+			 */
+			nss_connmgr_pptp_info("%px: NSS FW tx success if_number %d\n", dev, host_inner_if);
+			return 0;
+		}
+
+		nss_connmgr_pptp_info("%px: NSS FW tx failed if_number %d\n", dev, host_inner_if);
+		return -1;
+	}
+
+	/* Return error, Could not find a match for session */
+	return -1;
+}
+
+/*
+ * nss_connmgr_pptp_get_session()
+ *	Retrieve pptp session associated with this netdevice if any
+ */
+static int nss_connmgr_pptp_get_session(struct net_device *dev, struct pptp_opt *opt)
+{
+	struct ppp_channel *channel[1] = {NULL};
+	int px_proto;
+	int ppp_ch_count;
+
+	/*
+	 * check whether the interface is of type PPP
+	 */
+	if (dev->type != ARPHRD_PPP || !(dev->priv_flags_ext & IFF_EXT_PPP_PPTP)) {
+		nss_connmgr_pptp_info("%px: netdevice is not a PPP tunnel type\n", dev);
+		return -1;
+	}
+
+	if (ppp_is_multilink(dev)) {
+		nss_connmgr_pptp_warning("%px: channel is multilink PPP\n", dev);
+		return -1;
+	}
+
+	if (ppp_is_cp_enabled(dev)) {
+		nss_connmgr_pptp_warning("%px: rx or tx compression is enabled for PPP\n", dev);
+		return -1;
+	}
+
+	ppp_ch_count = ppp_hold_channels(dev, channel, 1);
+	nss_connmgr_pptp_info("%px: PPP hold channel ret %d\n", dev, ppp_ch_count);
+	if (ppp_ch_count != 1) {
+		nss_connmgr_pptp_warning("%px: hold channel for netdevice failed\n", dev);
+		return -1;
+	}
+
+	if (!channel[0]) {
+		nss_connmgr_pptp_warning("%px: channel don't have a ppp_channel\n", dev);
+		return -1;
+	}
+
+	px_proto = ppp_channel_get_protocol(channel[0]);
+	if (px_proto != PX_PROTO_PPTP) {
+		nss_connmgr_pptp_warning("%px: session socket is not of type PX_PROTO_PPTP\n", dev);
+		ppp_release_channels(channel, 1);
+		return -1;
+	}
+
+	pptp_channel_addressing_get(opt, channel[0]);
+
+	ppp_release_channels(channel, 1);
+	return 0;
+}
+
+/*
+ * nss_connmgr_add_pptp_session()
+ *	Add PPTP session entry into Hash table
+ */
+static struct nss_connmgr_pptp_session_entry *nss_connmgr_add_pptp_session(struct net_device *dev, struct pptp_opt *session)
+
+{
+	struct nss_connmgr_pptp_session_entry *pptp_session_data = NULL;
+	struct nss_connmgr_pptp_session_info *data;
+	struct net_device *physical_dev;
+
+	pptp_session_data = kmalloc(sizeof(struct nss_connmgr_pptp_session_entry),
+				      GFP_KERNEL);
+	if (!pptp_session_data) {
+		nss_connmgr_pptp_warning("%px: failed to allocate pptp_session_data\n", dev);
+		return NULL;
+	}
+
+	data = &pptp_session_data->data;
+
+	/*
+	 * Get session info
+	 */
+	data->src_call = session->src_addr.call_id;
+	data->dst_call = session->dst_addr.call_id;
+	data->src_ip = session->src_addr.sin_addr.s_addr;
+	data->dst_ip = session->dst_addr.sin_addr.s_addr;
+
+	nss_connmgr_pptp_info("%px: src_call_id=%u peer_call_id=%u\n", dev, data->src_call, data->dst_call);
+
+	/*
+	 * This netdev hold will be released when netdev
+	 * down event arrives and session goes down.
+	 */
+	dev_hold(dev);
+	pptp_session_data->dev = dev;
+
+	/*
+	 * Note: ip_dev_find does a hold on the physical device,
+	 * which is released when PPTP session goes down
+	 */
+	physical_dev = ip_dev_find(&init_net, data->src_ip);
+	if (!physical_dev) {
+		nss_connmgr_pptp_warning("%px: couldn't find a phycal dev %s\n", dev, dev->name);
+		dev_put(dev);
+		kfree(pptp_session_data);
+		return NULL;
+	}
+
+	pptp_session_data->phy_dev = physical_dev;
+
+	/*
+	 * There is no need for protecting simultaneous addition &
+	 * deletion of pptp_session_data as all netdev notifier chain
+	 * call back is called with rtln mutex lock.
+	 */
+	hash_add_rcu(pptp_session_table,
+		&pptp_session_data->hash_list,
+		dev->ifindex);
+
+	return pptp_session_data;
+}
+
+/*
+ * nss_connmgr_pptp_event_receive()
+ *	Event Callback to receive events from NSS
+ */
+static void nss_connmgr_pptp_event_receive(void *if_ctx, struct nss_pptp_msg *tnlmsg)
+{
+	struct nss_connmgr_pptp_session_entry *session_info = (struct nss_connmgr_pptp_session_entry *)if_ctx;
+	struct net_device *netdev = session_info->dev;
+	struct nss_pptp_sync_session_stats_msg *sync_stats;
+	uint32_t if_type;
+
+	switch (tnlmsg->cm.type) {
+	case NSS_PPTP_MSG_SYNC_STATS:
+		if (!netdev) {
+			return;
+		}
+
+		nss_connmgr_pptp_info("%px: Update PPP stats for PPTP netdev %px\n", session_info, netdev);
+		sync_stats = (struct nss_pptp_sync_session_stats_msg *)&tnlmsg->msg.stats;
+		dev_hold(netdev);
+
+		if_type = nss_dynamic_interface_get_type(nss_pptp_get_context(), tnlmsg->cm.interface);
+
+		if (if_type == NSS_DYNAMIC_INTERFACE_TYPE_PPTP_OUTER) {
+			ppp_update_stats(netdev,
+				 (unsigned long)sync_stats->node_stats.rx_packets,
+				 (unsigned long)sync_stats->node_stats.rx_bytes,
+				 0, 0, 0, 0, 0, 0);
+		} else {
+
+			ppp_update_stats(netdev, 0, 0,
+				 (unsigned long)sync_stats->node_stats.tx_packets,
+				 (unsigned long)sync_stats->node_stats.tx_bytes,
+				  0, 0, 0, 0);
+		}
+
+		dev_put(netdev);
+		break;
+
+	default:
+		nss_connmgr_pptp_warning("%px: Unknown Event from NSS\n", session_info);
+		break;
+	}
+}
+
+/*
+ * nss_connmgr_pptp_decap_exception()
+ *	Exception handler registered to NSS for handling pptp pkts
+ */
+static void nss_connmgr_pptp_decap_exception(struct net_device *dev,
+				       struct sk_buff *skb,
+				       __attribute__((unused)) struct napi_struct *napi)
+
+{
+	struct iphdr *iph_outer;
+	struct nss_connmgr_pptp_session_entry *session_info;
+	struct flowi4 fl4;
+	struct nss_pptp_gre_hdr *gre_hdr;
+	__be32 tunnel_local_ip;
+	__be32 tunnel_peer_ip;
+	struct rtable *rt;
+
+	/* discard L2 header */
+	skb_pull(skb, sizeof(struct ethhdr));
+	skb_reset_mac_header(skb);
+
+	iph_outer = (struct iphdr *)skb->data;
+
+	rcu_read_lock();
+	hash_for_each_possible_rcu(pptp_session_table, session_info,
+				   hash_list, dev->ifindex) {
+		if (session_info->dev != dev) {
+			continue;
+		}
+
+		tunnel_local_ip = session_info->data.src_ip;
+		tunnel_peer_ip = session_info->data.dst_ip;
+		rcu_read_unlock();
+		if ((iph_outer->version == 4) && (iph_outer->protocol == IPPROTO_GRE) &&
+			(iph_outer->saddr == tunnel_local_ip) && (iph_outer->daddr == tunnel_peer_ip)) { /*pkt is encapsulated */
+
+			/*
+			 * Pull the outer IP header and confirm the packet is a PPTP GRE Packet
+			 */
+			skb_pull(skb, sizeof(struct iphdr));
+			gre_hdr = (struct nss_pptp_gre_hdr *)skb->data;
+			if ((ntohs(gre_hdr->protocol) != NSS_PPTP_GRE_PROTO) &&
+				(gre_hdr->flags_ver == NSS_PPTP_GRE_VER)) {
+				nss_connmgr_pptp_warning("%px, Not PPTP_GRE_PROTO, so freeing\n", dev);
+				dev_kfree_skb_any(skb);
+				return;
+			}
+
+			skb_push(skb, sizeof(struct iphdr));
+
+			/*
+			 * This is a PPTP encapsulated packet that has been exceptioned to host from NSS.
+			 * We can send it directly to the physical device
+			 */
+			rt = ip_route_output_ports(&init_net, &fl4, NULL, tunnel_peer_ip,
+					tunnel_local_ip, 0, 0, IPPROTO_GRE, RT_TOS(0), 0);
+			if (unlikely(IS_ERR(rt))) {
+				nss_connmgr_pptp_warning("%px: Martian packets, drop\n", dev);
+				nss_connmgr_pptp_warning("%px: No route or out dev, drop packet...\n", dev);
+				dev_kfree_skb_any(skb);
+				return;
+			}
+
+			if (likely(rt->dst.dev)) {
+				nss_connmgr_pptp_info("%px: dst route dev is %s\n", session_info, rt->dst.dev->name);
+			} else {
+				nss_connmgr_pptp_warning("%px: No out dev, drop packet...\n", dev);
+				dev_kfree_skb_any(skb);
+			}
+
+			/*
+			 * Sets the 'dst' entry for SKB, reset the IP and Transport
+			 * Header and sends the packet out directly to the physical
+			 * device associated with the PPTP tunnel interface.
+			 */
+			skb->dev = dev;
+			skb_dst_drop(skb);
+			skb_dst_set(skb, &rt->dst);
+			skb->ip_summed = CHECKSUM_COMPLETE;
+
+			skb_reset_network_header(skb);
+			skb_set_transport_header(skb, iph_outer->ihl*4);
+			skb->skb_iif = dev->ifindex;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
+			ip_local_out(skb);
+#else
+			ip_local_out(&init_net, skb->sk, skb);
+#endif
+			return;
+		}
+	}
+	rcu_read_unlock();
+	nss_connmgr_pptp_warning("%px: unable to find session for PPTP exception packet from %s, so freeing\n", dev, dev->name);
+	dev_kfree_skb_any(skb);
+}
+
+/*
+ * nss_connmgr_pptp_encap_exception()
+ *	Exception handler registered to NSS for handling pptp pkts
+ */
+static void nss_connmgr_pptp_encap_exception(struct net_device *dev,
+				       struct sk_buff *skb,
+				       __attribute__((unused)) struct napi_struct *napi)
+
+{
+	struct iphdr *iph_outer;
+	struct nss_connmgr_pptp_session_entry *session_info;
+	__be32 tunnel_local_ip;
+	__be32 tunnel_peer_ip;
+
+	/* discard L2 header */
+	skb_pull(skb, sizeof(struct ethhdr));
+	skb_reset_mac_header(skb);
+
+	iph_outer = (struct iphdr *)skb->data;
+
+	rcu_read_lock();
+	hash_for_each_possible_rcu(pptp_session_table, session_info,
+				   hash_list, dev->ifindex) {
+		if (session_info->dev != dev) {
+			continue;
+		}
+
+		tunnel_local_ip = session_info->data.src_ip;
+		tunnel_peer_ip = session_info->data.dst_ip;
+		rcu_read_unlock();
+
+		if (iph_outer->version == 4) {
+			skb->protocol = htons(ETH_P_IP);
+		} else if (iph_outer->version == 6) {
+			skb->protocol = htons(ETH_P_IPV6);
+		} else {
+			nss_connmgr_pptp_info("%px: pkt may be a control packet\n", dev);
+		}
+
+		skb_reset_network_header(skb);
+		skb->pkt_type = PACKET_HOST;
+		skb->skb_iif = dev->ifindex;
+		skb->ip_summed = CHECKSUM_NONE;
+		skb->dev = dev;
+		nss_connmgr_pptp_info("%px: send decapsulated packet through network stack", dev);
+		netif_receive_skb(skb);
+		return;
+	}
+	rcu_read_unlock();
+	nss_connmgr_pptp_warning("%px: unable to find session for PPTP exception packet from %s, so freeing\n", dev, dev->name);
+	dev_kfree_skb_any(skb);
+}
+
+/*
+ * nss_connmgr_pptp_dev_up()
+ *	pppopptp interface's up event handler
+ */
+static int nss_connmgr_pptp_dev_up(struct net_device *dev)
+{
+	struct pptp_opt opt;
+	struct nss_connmgr_pptp_session_entry *session_info = NULL;
+	struct nss_connmgr_pptp_session_info *data;
+	nss_tx_status_t status;
+	struct nss_ctx_instance *nss_ctx;
+	uint32_t features = 0;
+	int32_t inner_if, outer_if, host_inner_if;
+	struct nss_pptp_msg  pptpmsg;
+	struct nss_pptp_session_configure_msg *pptpcfg;
+	int ret;
+
+	ret = nss_connmgr_pptp_get_session(dev, &opt);
+	if (ret < 0) {
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Create nss dynamic interface and register
+	 */
+	inner_if = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_PPTP_INNER);
+	if (inner_if < 0) {
+		nss_connmgr_pptp_warning("%px: Request inner interface number failed\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	if (!nss_is_dynamic_interface(inner_if)) {
+		nss_connmgr_pptp_warning("%px: Invalid NSS dynamic I/F number %d\n", dev, inner_if);
+		goto inner_fail;
+	}
+
+	outer_if = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_PPTP_OUTER);
+	if (outer_if < 0) {
+		nss_connmgr_pptp_warning("%px: Request outer interface number failed\n", dev);
+		goto inner_fail;
+	}
+
+	if (!nss_is_dynamic_interface(outer_if)) {
+		nss_connmgr_pptp_warning("%px: Invalid NSS dynamic I/F number %d\n", dev, outer_if);
+		goto outer_fail;
+	}
+
+	host_inner_if = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_PPTP_HOST_INNER);
+	if (host_inner_if < 0) {
+		nss_connmgr_pptp_warning("%px: Request host inner interface number failed\n", dev);
+		goto outer_fail;
+	}
+
+	if (!nss_is_dynamic_interface(host_inner_if)) {
+		nss_connmgr_pptp_warning("%px: Invalid NSS dynamic I/F number %d\n", dev, host_inner_if);
+		goto host_inner_fail;
+	}
+
+	session_info = nss_connmgr_add_pptp_session(dev, &opt);
+	if (!session_info) {
+		nss_connmgr_pptp_warning("%px: PPTP session add failed\n", dev);
+		goto host_inner_fail;
+	}
+
+	/*
+	 * Register pptp tunnel inner interface with NSS
+	 */
+	nss_ctx = nss_register_pptp_if(inner_if,
+				NSS_DYNAMIC_INTERFACE_TYPE_PPTP_INNER,
+				nss_connmgr_pptp_encap_exception,
+				nss_connmgr_pptp_event_receive,
+				dev,
+				features,
+				session_info);
+
+	if (!nss_ctx) {
+		nss_connmgr_pptp_warning("%px: nss_register_pptp_if failed for inner\n", dev);
+		goto register_inner_if_fail;
+	}
+
+	nss_connmgr_pptp_info("%px: inner interface registration successful\n", nss_ctx);
+
+	/*
+	 * Register pptp tunnel outer interface with NSS
+	 */
+	nss_ctx = nss_register_pptp_if(outer_if,
+				NSS_DYNAMIC_INTERFACE_TYPE_PPTP_OUTER,
+				nss_connmgr_pptp_decap_exception,
+				nss_connmgr_pptp_event_receive,
+				dev,
+				features,
+				session_info);
+
+	if (!nss_ctx) {
+		nss_connmgr_pptp_warning("%px: nss_register_pptp_if failed for outer\n", dev);
+		goto register_outer_if_fail;
+	}
+
+	nss_connmgr_pptp_info("%px: outer interface registration successful\n", nss_ctx);
+
+	/*
+	 * Register pptp tunnel inner interface with NSS
+	 */
+	nss_ctx = nss_register_pptp_if(host_inner_if,
+				NSS_DYNAMIC_INTERFACE_TYPE_PPTP_HOST_INNER,
+				nss_connmgr_pptp_encap_exception,
+				nss_connmgr_pptp_event_receive,
+				dev,
+				features,
+				session_info);
+
+	if (!nss_ctx) {
+		nss_connmgr_pptp_warning("%px: nss_register_pptp_if failed for host inner\n", dev);
+		goto register_host_inner_if_fail;
+	}
+
+	nss_connmgr_pptp_info("%px: host inner interface registration successful\n", nss_ctx);
+
+	/*
+	 * Initialize and configure inner I/F.
+	 */
+	data = &session_info->data;
+
+	memset(&pptpmsg, 0, sizeof(struct nss_pptp_msg));
+	pptpcfg = &pptpmsg.msg.session_configure_msg;
+
+	/*
+	 * The call id is already in host byte order,
+	 * therefore no need to do ntohs() for call id.
+	 */
+	pptpcfg->src_call_id = data->src_call;
+	pptpcfg->dst_call_id = data->dst_call;
+
+	/*
+	 * Convert IP addresses from nework byte order
+	 * to host byte order before posting to firmware.
+	 */
+	pptpcfg->sip = ntohl(data->src_ip);
+	pptpcfg->dip = ntohl(data->dst_ip);
+
+	/*
+	 * Populate the sibling interfaces.
+	 */
+	pptpcfg->sibling_ifnum_pri = outer_if;
+	pptpcfg->sibling_ifnum_aux = host_inner_if;
+
+	nss_connmgr_pptp_info("%px: pptp info\n", dev);
+	nss_connmgr_pptp_info("%px: local_call_id %d peer_call_id %d\n", dev,
+									pptpcfg->src_call_id,
+									pptpcfg->dst_call_id);
+	nss_connmgr_pptp_info("%px: saddr 0x%x daddr 0x%x \n", dev, pptpcfg->sip, pptpcfg->dip);
+
+	nss_pptp_msg_init(&pptpmsg, inner_if, NSS_PPTP_MSG_SESSION_CONFIGURE, sizeof(struct nss_pptp_session_configure_msg), NULL, NULL);
+
+	status = nss_pptp_tx_msg_sync(nss_ctx, &pptpmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pptp_warning("%px: nss pptp session creation command error %d\n", dev, status);
+		goto tx_msg_fail;
+	}
+	nss_connmgr_pptp_info("%px: nss_pptp_tx() successful for inner\n", dev);
+
+	/*
+	 * Initialize and configure outer I/F.
+	 */
+	pptpcfg->sibling_ifnum_pri = inner_if;
+	pptpcfg->sibling_ifnum_aux = host_inner_if;
+
+	nss_pptp_msg_init(&pptpmsg, outer_if, NSS_PPTP_MSG_SESSION_CONFIGURE, sizeof(struct nss_pptp_session_configure_msg), NULL, NULL);
+
+	status = nss_pptp_tx_msg_sync(nss_ctx, &pptpmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pptp_warning("%px: nss pptp session creation command error %d\n", dev, status);
+		goto tx_msg_fail;
+	}
+	nss_connmgr_pptp_info("%px: nss_pptp_tx() successful for outer\n", dev);
+
+	/*
+	 * Initialize and configure host inner I/F.
+	 */
+	pptpcfg->sibling_ifnum_pri = outer_if;
+	pptpcfg->sibling_ifnum_aux = inner_if;
+
+	nss_pptp_msg_init(&pptpmsg, host_inner_if, NSS_PPTP_MSG_SESSION_CONFIGURE, sizeof(struct nss_pptp_session_configure_msg), NULL, NULL);
+
+	status = nss_pptp_tx_msg_sync(nss_ctx, &pptpmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pptp_warning("%px: nss pptp session creation command error %d\n", dev, status);
+		goto tx_msg_fail;
+	}
+	nss_connmgr_pptp_info("%px: nss_pptp_tx() successful for host inner\n", dev);
+
+	/*
+	 * Enable the offload mode for Linux PPTP kernel driver. After this
+	 * all PPTP GRE packets will go through the NSS FW.
+	 */
+	pptp_session_enable_offload_mode(data->dst_call, data->dst_ip);
+
+	return NOTIFY_DONE;
+
+tx_msg_fail:
+	nss_unregister_pptp_if(host_inner_if);
+register_host_inner_if_fail:
+	nss_unregister_pptp_if(outer_if);
+register_outer_if_fail:
+	nss_unregister_pptp_if(inner_if);
+register_inner_if_fail:
+		dev_put(dev); /* We are accessing dev later */
+		dev_put(session_info->phy_dev);
+		hash_del_rcu(&session_info->hash_list);
+		synchronize_rcu();
+		kfree(session_info);
+host_inner_fail:
+	status = nss_dynamic_interface_dealloc_node(host_inner_if, NSS_DYNAMIC_INTERFACE_TYPE_PPTP_HOST_INNER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pptp_warning("%px: Unable to dealloc the node[%d] in the NSS fw!\n", dev, host_inner_if);
+	}
+outer_fail:
+	status = nss_dynamic_interface_dealloc_node(inner_if, NSS_DYNAMIC_INTERFACE_TYPE_PPTP_OUTER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pptp_warning("%px: Unable to dealloc the node[%d] in the NSS fw!\n", dev, outer_if);
+	}
+inner_fail:
+	status = nss_dynamic_interface_dealloc_node(inner_if, NSS_DYNAMIC_INTERFACE_TYPE_PPTP_INNER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pptp_warning("%px: Unable to dealloc the node[%d] in the NSS fw!\n", dev, inner_if);
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_connmgr_pptp_dev_down()
+ *	pptp interface's down event handler
+ */
+static int nss_connmgr_pptp_dev_down(struct net_device *dev)
+{
+	struct nss_connmgr_pptp_session_entry *session_info;
+	struct nss_connmgr_pptp_session_entry *session_found = NULL;
+	struct hlist_node *tmp;
+
+	struct nss_pptp_msg pptpmsg;
+	struct nss_pptp_session_deconfigure_msg *pptpcfg;
+	nss_tx_status_t status;
+	int32_t inner_if, outer_if, host_inner_if;
+
+	/*
+	 * check whether the interface is of type PPP
+	 */
+	if (dev->type != ARPHRD_PPP || !(dev->priv_flags_ext & IFF_EXT_PPP_PPTP)) {
+		nss_connmgr_pptp_info("%px: netdevice is not a pptp tunnel type\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Check if pptp inner I/F is registered ?
+	 */
+	inner_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_PPTP_INNER);
+	if (inner_if < 0) {
+		nss_connmgr_pptp_warning("%px: outer I/F is not registered\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Check if pptp outer I/F is registered ?
+	 */
+	outer_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_PPTP_OUTER);
+	if (outer_if < 0) {
+		nss_connmgr_pptp_warning("%px: inner I/F is not registered\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Check if pptp host inner I/F is registered ?
+	 */
+	host_inner_if = nss_cmn_get_interface_number_by_dev_and_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_PPTP_HOST_INNER);
+	if (host_inner_if < 0) {
+		nss_connmgr_pptp_warning("%px: Net device is not registered\n", dev);
+		return NOTIFY_DONE;
+	}
+
+	hash_for_each_possible_safe(pptp_session_table, session_info,
+				    tmp, hash_list, dev->ifindex) {
+		if (session_info->dev != dev) {
+			continue;
+		}
+
+		session_found = session_info;
+		break;
+	}
+
+	if (!session_found) {
+		nss_connmgr_pptp_warning("%px: pptp session is not found for this device", dev);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Disable the pptp offload mode. This will allow all PPTP GRE packets
+	 * to go through linux PPTP kernel module.
+	 */
+	pptp_session_disable_offload_mode(session_info->data.dst_call, session_info->data.dst_ip);
+	dev_put(dev);
+	dev_put(session_info->phy_dev);
+	hash_del_rcu(&session_info->hash_list);
+	synchronize_rcu();
+
+	memset(&pptpmsg, 0, sizeof(struct nss_pptp_msg));
+	pptpcfg = &pptpmsg.msg.session_deconfigure_msg;
+	pptpcfg->src_call_id = session_info->data.src_call;
+
+	/*
+	 * Deconfigure all I/Fs.
+	 */
+	nss_pptp_msg_init(&pptpmsg, inner_if, NSS_PPTP_MSG_SESSION_DECONFIGURE, sizeof(struct nss_pptp_session_deconfigure_msg), NULL, NULL);
+	status = nss_pptp_tx_msg_sync(nss_pptp_get_context(), &pptpmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pptp_warning("%px: pptp session destroy command failed, if_number = %d\n", dev, inner_if);
+		goto fail;
+	}
+
+	nss_pptp_msg_init(&pptpmsg, outer_if, NSS_PPTP_MSG_SESSION_DECONFIGURE, sizeof(struct nss_pptp_session_deconfigure_msg), NULL, NULL);
+	status = nss_pptp_tx_msg_sync(nss_pptp_get_context(), &pptpmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pptp_warning("%px: pptp session destroy command failed, if_number = %d\n", dev, outer_if);
+		goto fail;
+	}
+
+	nss_pptp_msg_init(&pptpmsg, host_inner_if, NSS_PPTP_MSG_SESSION_DECONFIGURE, sizeof(struct nss_pptp_session_deconfigure_msg), NULL, NULL);
+	status = nss_pptp_tx_msg_sync(nss_pptp_get_context(), &pptpmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pptp_warning("%px: pptp session destroy command failed, if_number = %d\n", dev, host_inner_if);
+		goto fail;
+	}
+
+	/*
+	 * Unregister all the I/Fs.
+	 */
+	nss_unregister_pptp_if(inner_if);
+	nss_unregister_pptp_if(outer_if);
+	nss_unregister_pptp_if(host_inner_if);
+
+	/*
+	 * Dealloc all the I/Fs.
+	 */
+	status = nss_dynamic_interface_dealloc_node(inner_if, NSS_DYNAMIC_INTERFACE_TYPE_PPTP_INNER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pptp_warning("%px: pptp dealloc node failure for inner if_number=%d\n", dev, inner_if);
+		goto fail;
+	}
+
+	status = nss_dynamic_interface_dealloc_node(outer_if, NSS_DYNAMIC_INTERFACE_TYPE_PPTP_OUTER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pptp_warning("%px: pptp dealloc node failure for outer if_number=%d\n", dev, outer_if);
+		goto fail;
+	}
+
+	status = nss_dynamic_interface_dealloc_node(host_inner_if, NSS_DYNAMIC_INTERFACE_TYPE_PPTP_HOST_INNER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_connmgr_pptp_warning("%px: pptp dealloc node failure for host inner if_number=%d\n", dev, host_inner_if);
+		goto fail;
+	}
+
+	nss_connmgr_pptp_info("%px: deleting pptpsession, if_number %d, local_call_id %d, peer_call_id %d\n", dev,
+					dev->ifindex, session_info->data.src_call,  session_info->data.dst_call);
+
+fail:
+	kfree(session_info);
+	return NOTIFY_DONE;
+
+}
+
+/*
+ * nss_connmgr_pptp_dev_event()
+ *	Net device notifier for nss pptp module
+ */
+static int nss_connmgr_pptp_dev_event(struct notifier_block  *nb,
+		unsigned long event, void  *dev)
+{
+	struct net_device *netdev = netdev_notifier_info_to_dev(dev);
+
+	switch (event) {
+	case NETDEV_UP:
+		nss_connmgr_pptp_info("%px: netdevice '%s' UP event\n", netdev, netdev->name);
+		return nss_connmgr_pptp_dev_up(netdev);
+
+	case NETDEV_DOWN:
+		nss_connmgr_pptp_info("%px: netdevice '%s' Down event\n", netdev, netdev->name);
+		return nss_connmgr_pptp_dev_down(netdev);
+
+	default:
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * Linux Net device Notifier
+ */
+struct notifier_block nss_connmgr_pptp_notifier = {
+	.notifier_call = nss_connmgr_pptp_dev_event,
+};
+
+/*
+ * nss_connmgr_pptp_init_module()
+ *	Tunnel pptp module init function
+ */
+int __init nss_connmgr_pptp_init_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+	register_netdevice_notifier(&nss_connmgr_pptp_notifier);
+	pptp_register_gre_seq_offload_callback(nss_connmgr_pptp_client_xmit);
+	return 0;
+}
+
+/*
+ * nss_connmgr_pptp_exit_module
+ *	Tunnel pptp module exit function
+ */
+void __exit nss_connmgr_pptp_exit_module(void)
+{
+	pptp_unregister_gre_seq_offload_callback();
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return;
+	}
+#endif
+	unregister_netdevice_notifier(&nss_connmgr_pptp_notifier);
+}
+
+module_init(nss_connmgr_pptp_init_module);
+module_exit(nss_connmgr_pptp_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS pptp offload manager");
diff --git a/qca-nss-clients/pptp/nss_connmgr_pptp.h b/qca-nss-clients/pptp/nss_connmgr_pptp.h
new file mode 100644
index 0000000..deb00a3
--- /dev/null
+++ b/qca-nss-clients/pptp/nss_connmgr_pptp.h
@@ -0,0 +1,73 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_connnmgr_pptp.h
+ *	NSS PPTP client definitions
+ */
+
+#ifndef _NSS_CONNMGR_PPTP_H_
+#define _NSS_CONNMGR_PPTP_H_
+
+ /*
+  *		------------------------------------------------------------------
+  *		|		|		|		|		 |
+  *		| ip header	| GRE header	|ppp header	| ppp payload    |
+  *		|		|		|		|  (IP data gram)|
+  *		|		|		|		|		 |
+  *		|-----------------------------------------------------------------
+  *             PPTP over GRE
+  */
+
+#define NSS_PPTP_GRE_PROTO	0x880B
+#define NSS_PPTP_GRE_VER	0x1
+#define NSS_PPTP_GRE_HAS_ACK	0x80
+#define NSS_PPTP_GRE_HAS_SEQ	0x10
+
+/*
+ * GRE Header Structure
+ */
+struct nss_pptp_gre_hdr {
+	uint8_t  flags;
+	uint8_t  flags_ver;
+	uint16_t protocol;
+	uint16_t payload_len;
+	uint16_t call_id;
+	uint32_t seq;
+	uint32_t ack;
+};
+
+/*
+ * Structure for PPTP client driver session info
+ */
+struct nss_connmgr_pptp_session_info {
+	uint32_t src_call;
+	uint32_t dst_call;
+	uint32_t src_ip;
+	uint32_t dst_ip;
+};
+
+/*
+ * Structure for PPTP session entry into HASH table
+ */
+struct nss_connmgr_pptp_session_entry {
+	struct nss_connmgr_pptp_session_info data;
+	struct net_device *dev;
+	struct net_device *phy_dev;
+	struct hlist_node hash_list;
+};
+
+#endif
diff --git a/qca-nss-clients/profiler/Makefile b/qca-nss-clients/profiler/Makefile
new file mode 100644
index 0000000..e58e737
--- /dev/null
+++ b/qca-nss-clients/profiler/Makefile
@@ -0,0 +1,7 @@
+ccflags-y := -I$(obj) -I$(obj)/.. -I$(obj)/../exports -DNSS_DEBUG_LEVEL=0 #-DPROFILE_DEBUG
+ccflags-y += -Wall -Werror
+
+obj-m += qca-nss-profile-drv.o
+qca-nss-profile-drv-objs := profile.o
+
+ccflags-y += $(NSS_CCFLAGS)
diff --git a/qca-nss-clients/profiler/profile.c b/qca-nss-clients/profiler/profile.c
new file mode 100755
index 0000000..67418f6
--- /dev/null
+++ b/qca-nss-clients/profiler/profile.c
@@ -0,0 +1,1387 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014,2016,2018, 2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * qsdk/qca/src/qca-nss-drv/profiler/profile.c
+ *
+ *   Implementation for NetAP Profiler
+ */
+
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/export.h>
+#include <linux/module.h>
+#include <linux/seq_file.h>
+#include <linux/proc_fs.h>
+#include <linux/mm.h>
+#include <linux/mmzone.h>
+#include <linux/fs.h>
+#include <linux/page-flags.h>
+#include <linux/sched.h>
+#include <asm/uaccess.h>
+#include <asm/page.h>
+#include <asm/thread_info.h>
+#include <linux/ctype.h>
+#include <nss_api_if.h>
+
+#include "profilenode.h"
+#include "profpkt.h"
+
+/*
+ * This is the driver for the NetAP Core profiler. The system interface to the driver is
+ *	profile_register_performance_counter(), defined in <asm/profile.>
+ *	a set of proc files (proc/profile/<*>), used by the profiler daemon
+ *
+ * communication between the profiler components is described in a set of header files.
+ * There are multiple versions of these files that must be kept synchronized:
+ *	in nss/source/pkg/profile
+ *	in tools/profiler
+ *	in qsdk/qca/src/qca-nss-drv/profiler
+ *
+ * profilesample.h specifies the sample format used by pkg/profile, profile driver, and ip3kprof (two versions)
+ * profilenode.h specifies the driver node communication between NetAP and the profile driver. (two versions)
+ * profpkt.h specifies the network packet format between the profile driver, profile daemon, and ip3kprof (two versions)
+ *
+ *
+ * NSS profile sampler:
+ *	pkg/profile/src/profile.c
+ *	pkg/profile/include/profilenode.h
+ *	pkg/profile/include/profilesample.h
+ *
+ * profile driver: this code
+ *	qsdk/qca/src/qca-nss-drv/profiler
+ *
+ * profilerd: the user daemon that sends data to the tool
+ *	qsdk/qca/feeds/qca/utils/profilerd
+ *
+ * ubicom32-prof: the Windows tool
+ *	tools/profiler/src/(many files)
+ *
+ */
+
+#ifdef	PROFILE_DEBUG
+#define	profileDebug(s, ...) pr_debug("%s[%d]: " s, __func__, __LINE__, ##__VA_ARGS__)
+#define	profileInfo(s, ...) pr_info("%s[%d]: " s, __func__, __LINE__, ##__VA_ARGS__)
+#else
+#define	profileDebug(s, ...)
+#define	profileInfo(s, ...)
+#endif
+
+#define	profileWarn(s, ...) pr_warn("%s[%d]: " s, __func__, __LINE__, ##__VA_ARGS__)
+
+static void profiler_handle_reply(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm);
+
+/*
+ * LINUX and Ultra counters must all fit in one packet
+ */
+#define PROFILE_LINUX_MAX_COUNTERS 40
+#define PROFILE_STS_EVENT_COUNTERS 8
+#define PROFILE_STS_EVENT_THREAD_BITS 5
+
+static int profile_num_counters = 0;
+static volatile unsigned int *profile_counter[PROFILE_LINUX_MAX_COUNTERS];
+static char profile_name[PROFILE_LINUX_MAX_COUNTERS][PROFILE_COUNTER_NAME_LENGTH];
+
+/*
+ * internal function to check if @name has been registered before
+ * return the found index, or -1 otherwise
+ */
+static int __profile_find_entry(char *name)
+{
+	int i;
+
+	for (i = 0; i < profile_num_counters; i++) {
+		if (!strncasecmp(name, profile_name[i], PROFILE_COUNTER_NAME_LENGTH)) {
+			return i;
+		}
+	}
+	return -1;
+}
+
+/*
+ * profile_register_performance_counter - register @counter into profile tracking list by key @name
+ * @counter: pointer of the counter variable
+ * @name: identifier of this counter
+ *
+ * Returns zero if total entries exceeding PROFILE_LINUX_MAX_COUNTERS
+ * non-zero otherwise.
+ *
+ * Each @name gives unique entry for @counter, by allocating a new array slot or just use existing one.
+ * No need of de-registration API, since a loadable module's new insmod, will replace the
+ * @counter's * new address at the same profile_counter[] slot.
+ */
+int profile_register_performance_counter(volatile unsigned int *counter, char *name)
+{
+	int i;
+
+	if (profile_num_counters >= PROFILE_LINUX_MAX_COUNTERS) {
+		return 0;
+	}
+
+	i = __profile_find_entry(name);
+	if (i < 0) {
+		i = profile_num_counters++;
+	}
+
+	profile_counter[i] = counter;
+	strlcpy(profile_name[i], name, PROFILE_COUNTER_NAME_LENGTH);
+	profile_name[i][PROFILE_COUNTER_NAME_LENGTH - 1] = 0;
+
+	return 1;
+}
+
+/*
+ * profile_make_data_packet
+ *	Make a packet full of sample data
+ */
+static int profile_make_data_packet(char *buf, int blen, struct profile_io *pn)
+{
+	int sp_samples = 0;	/* separated samples if any */
+	int ns;		/* number of samples requested */
+	struct profile_header ph;
+	struct nss_profile_sample_ctrl *psc_hd = &pn->pnc.pn2h->psc_header;
+
+	if (blen < sizeof(ph) + sizeof(struct nss_profile_sample)) {
+		return -EINVAL;
+	}
+
+	profileInfo("%px stat %x cnt %d %px\n", pn->pnc.pn2h, pn->pnc.pn2h->mh.md_type, psc_hd->ps_count, pn->ccl);
+
+	if (pn->pnc.pn2h->mh.md_type == PINGPONG_EMPTY || psc_hd->ps_count < 1) {
+		struct nss_profile_n2h_sample_buf *nsb;
+		ns = (pn->ccl_read + 1) & (CCL_SIZE-1);
+		nsb = pn->ccl + ns;
+		if (ns == pn->ccl_write || nsb->mh.md_type != PINGPONG_FULL) {
+			profileInfo("waiting more data %x %px : ns %d rd %d wr %d\n", nsb->mh.md_type, nsb, ns, pn->ccl_read, pn->ccl_write);
+			return -EAGAIN;
+		}
+		pn->ccl_read = ns;
+		profileInfo("sp %px => %px rd %d %px\n", pn->pnc.samples, nsb->samples, ns, nsb);
+		psc_hd = &nsb->psc_header;
+		pn->pnc.pn2h = nsb;
+		pn->pnc.samples = nsb->samples;
+		pn->pnc.cur = 0;
+	}
+	pn->pnc.pn2h->mh.md_type = PINGPONG_INUSE;
+
+	/*
+	 * fill in the packet header
+	 */
+	memset(&ph, 0, sizeof(ph));
+	ph.pph.magic = htons(PROF_MAGIC + PROFILE_VERSION);
+	ph.pph.header_size = sizeof(ph);
+	ph.pph.profile_instructions = 0;
+	ph.pph.clock_freq = pn->pnc.un.cpu_freq;
+	ph.pph.ddr_freq = pn->pnc.un.ddr_freq;
+	ph.pph.cpu_id = pn->pnc.un.cpu_id;
+	ph.pph.seq_num = htonl(pn->profile_sequence_num);
+	ph.pph.sample_stack_words = NSS_PROFILE_STACK_WORDS;
+
+	ns = (blen - sizeof(ph)) / sizeof(struct nss_profile_sample);
+	profileInfo("%X: blen %d ns = %d psc_hd count %d ssets %d phs %zu pss %zu\n",
+		pn->profile_sequence_num, blen, ns, psc_hd->ps_count,
+		psc_hd->ex_hd.sample_sets, sizeof(ph), sizeof(struct nss_profile_sample));
+	if (ns > psc_hd->ps_count)
+		ns = psc_hd->ps_count;
+	if (ns == 0) {
+		printk("NS should not be 0: rlen %d hd cnt %d\n", blen, psc_hd->ps_count);
+		return 0;
+	}
+
+	/*
+	 * if buf cannot hold all samples, then samples must be separated by set.
+	 */
+	if (ns < psc_hd->ps_count) {
+		ph.exh.sets_map = psc_hd->ex_hd.sets_map;	/* save for separating sets */
+		do {
+			sp_samples += psc_hd->ex_hd.sets_map & 0x0F;
+			psc_hd->ex_hd.sets_map >>= 4;	/* remove the last set */
+			psc_hd->ex_hd.sample_sets--;
+			ph.exh.sample_sets++;		/* save for restore later */
+		} while ((psc_hd->ps_count - sp_samples) > ns);
+		ns = psc_hd->ps_count - sp_samples;
+	}
+	ph.pph.sample_count = ns;
+	if (copy_to_user(buf, &ph.pph, sizeof(ph.pph)) != 0) {
+		return -EFAULT;
+	}
+	buf += sizeof(ph.pph);
+
+	/*
+	 * ph.exh is unused dummy; and psc_hd->ex_hd is used directly to avoid double mem copy
+	 */
+	if (copy_to_user(buf, &psc_hd->ex_hd, sizeof(psc_hd->ex_hd)) != 0) {
+		return -EFAULT;
+	}
+	buf += sizeof(psc_hd->ex_hd);
+
+	blen = ns * sizeof(struct nss_profile_sample);
+	profileDebug("-profile_make_data_packet %px slen %d cur %d dcped %zd + %zd\n",
+		pn->pnc.samples, blen, pn->pnc.cur, sizeof(ph.pph), sizeof(psc_hd->ex_hd));
+	if (copy_to_user(buf, &pn->pnc.samples[pn->pnc.cur], blen) != 0) {
+		return -EFAULT;
+	}
+	pn->pnc.cur += ns;
+	psc_hd->ps_count -= ns;
+	if (psc_hd->ps_count < 1)
+		pn->pnc.pn2h->mh.md_type = PINGPONG_EMPTY;
+
+	/*
+	 * restore left over sample counts; 0s for no one
+	 */
+	if (sp_samples) {
+		profileDebug("%d sps %d %d: sets %d : %d map %x <> %x\n", psc_hd->ps_count, ns, sp_samples, psc_hd->ex_hd.sample_sets, ph.exh.sample_sets, psc_hd->ex_hd.sets_map, ph.exh.sets_map);
+		psc_hd->ex_hd.sample_sets = ph.exh.sample_sets;
+		psc_hd->ex_hd.sets_map = ph.exh.sets_map;
+	}
+
+	pn->profile_sequence_num++;
+	blen += sizeof(ph);
+	profileDebug("+profile_make_data_packet %d phd len %zd nsp %px rd %d cnt %d\n", blen, sizeof(ph), pn->pnc.pn2h, pn->ccl_read, psc_hd->ps_count);
+	return blen;
+}
+
+static void *profiler_get_dma(struct nss_ctx_instance *nss_ctx, struct profile_io *pn)
+{
+	struct nss_profile_sdma_producer *dma;
+	void *kaddr = nss_profiler_alloc_dma(nss_ctx, &dma);
+	pn->pnc.un.sram_start = dma->desc_ring;
+	return kaddr;
+}
+
+/*
+ * This is no longer needed due to NetAP and Linux use different CPUs, and profile is NetAP only.
+ * All related code will be removed after corresponging code in visual tool is corrected; otherwise
+ * visual tool will mis-behave
+ */
+struct profile_counter profile_builtin_stats[] =
+{
+	{
+	"Free memory(KB)", 0
+	},
+	{
+	"Max free Block(KB)", 0
+	}
+};
+
+/*
+ * profile_make_stats_packet
+ *	make a packet full of performance counters (software)
+ */
+static int profile_make_stats_packet(char *buf, int bytes, struct profile_io *pn)
+{
+	static char prof_pkt[NSS_PROFILE_MAX_PACKET_SIZE];
+
+	char *ptr;
+	int n;
+	struct profile_counter *counter_ptr;
+	struct profile_header_counters *hdr = (struct profile_header_counters *)prof_pkt;
+	struct nss_profile_sample_ctrl *psc_hd = &pn->pnc.pn2h->psc_header;
+
+	if (bytes > NSS_PROFILE_MAX_PACKET_SIZE) {
+		bytes = NSS_PROFILE_MAX_PACKET_SIZE;
+	}
+	n = sizeof(profile_builtin_stats) + (pn->pnc.un.num_counters + profile_num_counters) * sizeof(*counter_ptr);
+
+	if ((bytes - sizeof(hdr)) < n) {
+		profileWarn("room too small %d for cnts %d\n", bytes, n);
+		return 0;
+	}
+
+	hdr->magic = htons(PROF_MAGIC_COUNTERS);
+	hdr->ultra_count = htons(pn->pnc.un.num_counters);
+	hdr->linux_count = htonl(profile_num_counters + sizeof(profile_builtin_stats) / sizeof(*counter_ptr));
+	hdr->ultra_sample_time = psc_hd->ex_hd.clocks;
+	hdr->linux_sample_time = psc_hd->ex_hd.clocks; /* QSDK has no time func */
+
+	n = pn->pnc.un.num_counters;	/* copy NSS counters */
+	n *= sizeof(pn->pnc.un.counters[0]);
+	ptr = (char*) (hdr + 1);
+	memcpy(ptr, (void *)(pn->pnc.un.counters), n);
+	ptr += n;
+
+	counter_ptr = (struct profile_counter *)ptr;
+	for (n = 0; n < profile_num_counters; ++n) {
+		counter_ptr->value = htonl(*profile_counter[n]);
+		strlcpy(counter_ptr->name, profile_name[n],
+			PROFILE_COUNTER_NAME_LENGTH);
+		counter_ptr++;
+	}
+	ptr = (char*)counter_ptr;
+
+	/*
+	 * built in statistics
+	profile_get_memory_stats(&total_free, &max_free);
+	 */
+	profile_builtin_stats[0].value = 0;
+	profile_builtin_stats[1].value = 0;
+	memcpy(ptr, (void *)profile_builtin_stats, sizeof(profile_builtin_stats));
+	ptr += sizeof(profile_builtin_stats);
+
+	n = ptr - prof_pkt;
+	if (copy_to_user(buf, prof_pkt, n) != 0) {
+		return -EFAULT;
+	}
+	return n;
+}
+
+/*
+ * space for all memory blocks so we can hold locks for short time when walking tables
+ */
+static struct profile_io *node[NSS_MAX_CORES];
+
+/*
+ * profile_open
+ *	open function of system call
+ */
+static int profile_open(struct inode *inode, struct file *filp)
+{
+	int	n;
+	struct profile_io *pn;
+
+	if (filp->private_data)
+		profileWarn("%s: %px\n", filp->f_path.dentry->d_iname, filp->private_data);
+
+	n = filp->f_path.dentry->d_iname[strlen(filp->f_path.dentry->d_iname) - 1] - '0';
+	if (n < 0 || n >= NSS_MAX_CORES)
+		n = 0;
+	pn = node[n];
+	if (!pn) {
+		return -ENOENT;
+	}
+
+	profileInfo("_open: mode %x flag %x\n", filp->f_mode, filp->f_flags);
+	if (!pn->pnc.enabled && nss_get_state(pn->ctx) == NSS_STATE_INITIALIZED) {
+		/*
+		 * sw_ksp_ptr is used as event flag. NULL means normal I/O
+		 */
+		pn->sw_ksp_ptr = NULL;
+		pn->pnc.enabled = 1;
+		pn->profile_first_packet = 1;
+
+		/*
+		 * If profiler is opened in read only mode, it is done by START_MSG
+		 * via debug interface (IF), which reads NSS-FW all registered NSS
+		 * variables.
+		 * Do not start engine (no sampling required) for debug IF.
+		 */
+		if (FMODE_READ & filp->f_mode) {
+			nss_tx_status_t ret;
+
+			pn->pnc.un.hd_magic = NSS_PROFILE_HD_MAGIC | NSS_PROFILER_START_MSG;
+			ret = nss_profiler_if_tx_buf(pn->ctx, &pn->pnc.un,
+				sizeof(pn->pnc.un), profiler_handle_reply, pn);
+			profileInfo("%s: %d -- %px: ccl %px sp %px\n", __func__, ret,
+				pn, pn->ccl, pn->pnc.samples);
+		}
+		filp->private_data = pn;
+		return 0;
+	}
+
+	profileWarn("profile ena %d nss stat %x\n", pn->pnc.enabled,
+			nss_get_state(pn->ctx));
+	return -EBUSY;
+}
+
+/*
+ * profile_read
+ *	read syscall
+ *
+ * return a udp packet ready to send to the profiler tool
+ * when there are no packets left to make, return 0
+ */
+static ssize_t profile_read(struct file *filp, char *buf, size_t count, loff_t *f_pos)
+{
+	int result = 0;
+	int slen = 0;
+	struct profile_io *pn = (struct profile_io *)filp->private_data;
+	if (!pn) {
+		return -ENOENT;
+	}
+
+	if (!pn->pnc.enabled) {
+		return -EPERM;
+	}
+	if (pn->sw_ksp_ptr) {
+		struct debug_box *db = (struct debug_box *) pn->sw_ksp_ptr;
+
+		if ((void*)db != (void*)pn) {
+			profileWarn("%px: hwe data not ready %px\n", pn, db);
+			return -EAGAIN;
+		}
+
+		profileWarn("dbda %px: %x %x %x %x %x\n", db->data,
+			db->data[0], db->data[2], db->data[4], db->data[6], db->data[7]);
+
+		slen = (PROFILE_STS_EVENT_COUNTERS + 1) * sizeof(db->data[0]);
+		if (copy_to_user(buf, db->data, slen))
+			return -EFAULT;
+		profileInfo("%px: sw_ksp_ptr %px slen %d\n", pn, pn->sw_ksp_ptr, slen);
+		return	slen;
+	}
+
+	if (!pn->pnc.samples) {
+		profileWarn("DEBUG %px: NULL samples\n", pn);
+		return -ENOMEM;
+	}
+
+	if (pn->profile_first_packet) {
+		result = profile_make_stats_packet(buf, count, pn);
+		pn->profile_first_packet = 0;
+		profileInfo("%d profile_make_stats_packet %zd\n", result, count);
+
+#ifdef	PROFILE_SEP_STAT
+		/*
+		 * currectly, stat and sample data are combined in one pkt for efficient;
+		 * but this is harder to debug and required remote tool to handle
+		 * packet in all-in-one method instead of individual handler.
+		 */
+		return result;
+#endif
+	}
+
+	if (result > 0) {
+		buf += result;
+		count -= result;
+		slen = result;
+	}
+	result = profile_make_data_packet(buf, count, pn);
+	if (result == 0) {
+		pn->profile_first_packet = 1;
+	}
+	profileInfo("%d: profile_make_data_packet %zd %d\n", result, count, slen);
+
+	profileInfo("%d: read\n", pn->pnc.enabled);
+	if (pn->pnc.enabled < 0) {
+		nss_tx_status_t ret;
+		pn->pnc.enabled = 1;
+		pn->pnc.un.hd_magic = NSS_PROFILE_HD_MAGIC | NSS_PROFILER_START_MSG;
+		ret = nss_profiler_if_tx_buf(pn->ctx, &pn->pnc.un, sizeof(pn->pnc.un),
+						profiler_handle_reply, pn);
+		profileWarn("%s: restart %d -- %px: ccl %px sp %px\n", __func__,
+				ret, pn, pn->ccl, pn->pnc.samples);
+	}
+
+	return result + slen;
+}
+
+/*
+ * profile_release
+ *	the close syscall paired with profiler_open
+ */
+static int profile_release(struct inode *inode, struct file *filp)
+{
+	struct profile_io *pn = (struct profile_io *)filp->private_data;
+	if (!pn) {
+		return -ENOENT;
+	}
+
+	if (pn->pnc.enabled) {
+		nss_tx_status_t ret;
+		pn->sw_ksp_ptr = NULL;
+		pn->pnc.enabled = 0;
+		pn->pnc.un.hd_magic = NSS_PROFILE_HD_MAGIC | NSS_PROFILER_STOP_MSG;
+		ret = nss_profiler_if_tx_buf(pn->ctx, &pn->pnc.un,
+				sizeof(pn->pnc.un), profiler_handle_reply, pn);
+		profileInfo("%s: %px %d\n", __func__, pn, ret);
+		return 0;
+	}
+	profileWarn("%s: attempt closing non-open dev %px\n", __func__, pn);
+	pn->profile_first_packet = 1;
+	return -EBADF;
+}
+
+#ifndef	__aarch64__
+/*
+ * counter_rate_by_uint32
+ *	helper function for handling 64-bit calculation in 32-bit mode
+ *
+ * 32-bit kernel does not have 64-bit div function;
+ * to avoid overflow and underflow, use if branch
+ * to overcome this problem: slower bur more accurate.
+ */
+static void counter_rate_by_uint32(struct nss_profile_common *pnc)
+{
+	static uint32_t prev_cnts[32];
+	static uint32_t last_uclk;
+	uint32_t mclk, uclk, ubi32_freq;
+	int n = pnc->un.num_counters;
+
+	ubi32_freq = htonl(pnc->un.cpu_freq) / 1000000;
+	uclk = pnc->un.rate - last_uclk;
+	last_uclk = pnc->un.rate;
+	printk("%d nss counters:	clk dif %u freq %u\n", n, uclk, ubi32_freq);
+
+	/*
+	 * exactly 4G? make it maximum
+	 */
+	if (!uclk)
+		uclk--;
+	while (n--) {
+		uint32_t v_dif;
+		uint32_t v = ntohl(pnc->un.counters[n].value);
+		uint32_t pv = prev_cnts[n];
+
+		prev_cnts[n] = v;
+		v_dif = v - pv;
+
+		/*
+		 * threshold	= MAX_UINT32 / MAX_Ubi32CPU_CLK (MHz)
+		 * if counter diff is less then this threshold,
+		 * 32-bit calculation can be directly applied w/o o/u flow;
+		 * otherwise, tick diff (uclk) adjust needs to be done before
+		 * calculating the rate to avoid over/under flow.
+		 */
+		if (v_dif < (UINT_MAX / ubi32_freq)) {
+			v_dif = (v_dif * ubi32_freq) / (uclk / 1000000);
+		} else {
+			/*
+			 * assume fast polling is 200ms, @ 500MHz, the minimum
+			 * uclk value is 0.5M * 200 = 10M, so reduce by 1M
+			 * it will still have value in 10, not zero (0).
+			 * in 2.3GHz and 1 sec interval, the residual is 2300.
+			 * The maximum polling interval is 2 sec for 2.3GHz,
+			 * and 3 sec for 1.7GHz.
+			 */
+			if (uclk > 1000000) {
+				mclk = uclk / 1000000;
+				v_dif = (v_dif / mclk) * ubi32_freq;
+			} else {
+				mclk = uclk / 1000;
+				v_dif = (v_dif / mclk) * ubi32_freq * 1000;
+			}
+		}
+		printk("%-32s 0x%08X	%10u :	%u/s\n",
+			pnc->un.counters[n].name, v, v, v_dif);
+	}
+}
+#endif
+
+/*
+ * profiler_handle_counter_event_reply()
+ *	get reply from firmware for current FW stat event counter configurations
+ *
+ * Based on firmware CPU clock (cpu_freq), calculate the counter change rate in
+ * second and print both counter value and its rate.
+ */
+static void profiler_handle_counter_event_reply(struct nss_ctx_instance *nss_ctx,
+						struct nss_cmn_msg *ncm)
+{
+	struct profile_io *pio = (struct profile_io *) ncm->app_data;
+	struct nss_profile_common *pnc = &pio->pnc;
+
+#ifndef __aarch64__
+	counter_rate_by_uint32(pnc);
+#else
+	static uint32_t prev_cnts[32];
+	static uint32_t last_uclk;
+	uint32_t ubi32_freq;
+	uint32_t uclk;
+	int n = pnc->un.num_counters;
+
+	ubi32_freq = htonl(pnc->un.cpu_freq);
+	uclk = pnc->un.rate - last_uclk;
+	last_uclk = pnc->un.rate;
+	printk("%d nss counters:	clk dif %u freq %u\n", n, uclk, ubi32_freq);
+	while (n--) {
+		uint32_t v = ntohl(pnc->un.counters[n].value);
+		uint32_t pv = prev_cnts[n];
+
+		prev_cnts[n] = v;
+
+		printk("%-32s 0x%08X	%10u :	%llu/s\n",
+			pnc->un.counters[n].name, v, v,
+			(uint64_t)(v - pv) * ubi32_freq / uclk);
+	}
+#endif
+}
+
+/*
+ * parseDbgCmd()
+ *	process debugging command(s).
+ *
+ * Currently supported command:
+ *	"=show-nss-counter"	display all values of nss variables registered
+ *				by profile_register_performance_counter(&v, name)
+ */
+#define	SHOW_COUNTER_CMD "show-nss-counter"
+static int parseDbgCmd(const char *buf, size_t count,
+			struct debug_box *db, struct profile_io *pio)
+{
+	int result;
+
+	if (strncmp(buf, SHOW_COUNTER_CMD, min(sizeof(SHOW_COUNTER_CMD)-1, count))) {
+		printk(KERN_ERR "%s: unsupported cmd %s %zu\n",
+			__func__, buf, strlen(buf));
+		return -EINVAL;
+	}
+
+	db->hd_magic = NSS_PROFILE_HD_MAGIC | NSS_PROFILER_COUNTERS_MSG;
+	result = nss_profiler_if_tx_buf(pio->ctx, &pio->pnc.un,
+					sizeof(pio->pnc.un),
+					profiler_handle_counter_event_reply, pio);
+	profileInfo("%s: %d\n", __func__, result);
+	return result == NSS_TX_SUCCESS ? count : -EFAULT;
+}
+
+/*
+ * profiler_handle_stat_event_reply()
+ *	print current FW stat event counter configurations
+ */
+static void profiler_handle_stat_event_reply(struct nss_ctx_instance *nss_ctx,
+						struct nss_cmn_msg *ncm)
+{
+	struct profile_io *pio = (struct profile_io *) ncm->app_data;
+	struct debug_box *pdb = (struct debug_box *) &pio->pnc;
+	struct debug_box *db = (struct debug_box *) &ncm[1];
+	int i, thrds;
+
+	for (i = 0; i < db->dlen; i++)
+		printk("stat counter %d: %x\n", i, db->data[i]);
+
+	thrds = db->data[i];
+	i = (1 << PROFILE_STS_EVENT_THREAD_BITS) - 1;
+	profileInfo("%d: event end mark %x, ThrA %d ThrB %d\n",
+		ncm->len, thrds, (thrds & i) + 1,
+		((thrds >> PROFILE_STS_EVENT_THREAD_BITS) & i) + 1);
+
+	/*
+	 * save data for read()
+	 */
+	memcpy(pdb->data, db->data, (db->dlen + 1) * sizeof(db->data[0]));
+	pio->sw_ksp_ptr = (uint32_t *)pdb;
+}
+
+/*
+ * parse_sys_stat_event_req()
+ *	process FW stat events request: event#1 index#1 event#2 index#2 ...
+ */
+static int parse_sys_stat_event_req(const char *buf, size_t count,
+				struct debug_box *db, struct profile_io *pio)
+{
+	char *cp;
+	int result;
+
+	printk("%zd cmd buf %s\n", count, buf);
+	if (count < 19) /* minimum data for sys_stat_event request */
+		return	-EINVAL;
+
+	if (strncmp(buf, "get-sys-stat-events", 19) == 0) {
+		db->hd_magic = NSS_PROFILE_HD_MAGIC | NSS_PROFILER_GET_SYS_STAT_EVENT;
+		result = nss_profiler_if_tx_buf(pio->ctx, &pio->pnc.un,
+					sizeof(pio->pnc.un),
+					profiler_handle_stat_event_reply, pio);
+		profileInfo("get_sys_stat_events: %d\n", result);
+		return	result == NSS_TX_SUCCESS ? count : -EFAULT;
+	}
+
+	if (strncmp(buf, "set-sys-stat-events", 19)) {
+		printk("unknow event: %s\n", buf);
+		return	-EINVAL;
+	}
+
+	db->dlen = sizeof(pio->pnc.un);
+	memset(db->data, 0, PROFILE_STS_EVENT_COUNTERS * sizeof(db->data[0]));
+
+	cp = strchr(buf, ' ');
+	if (!cp) {
+		printk("no enough paramters %s\n", buf);
+		return	-EINVAL;
+	}
+
+	do {
+		unsigned long idx;
+		int event, e5x;
+		char *kstrp;
+
+		while (isspace(*cp))
+			cp++;
+		kstrp = strchr(cp, ' ');
+		if (!kstrp) {
+			printk(KERN_ERR "%px missing index %px %s\n", buf, cp, cp);
+			return	-EINVAL;
+		}
+		kstrp[0] = 0;
+
+		/*
+		 * kstrtoul bugs:
+		 *	it does not use white space for delimiter.
+		 *	it cannot use base 0, thus base 10 only.
+		 */
+		event = kstrtoul(cp, 10, &idx);
+		if (event) {
+			printk(KERN_ERR "kstrtoul %d: %s\n", event, cp);
+			return -EINVAL;
+		}
+		event = idx;
+
+		/*
+		 * Processing thread specific events, which requires hex values.
+		 * Because kstrtoul cannot use base 0, it makes this task harder
+		 * in user space. Users need to convert hex value to decimal, then
+		 * pass them in userland command event-counter.
+		 */
+		e5x = event >> 16;
+		if (e5x) {
+			if ((event & 0x1FF) < 50) {
+				printk(KERN_INFO "thr ID (%d) ignored for event %d\n",
+					e5x, event & 0x1FF);
+			} else if (e5x > 12) {
+				if ((e5x >>= 5) > 12) {
+					printk(KERN_INFO "tID %d too big [1..12]\n", e5x);
+					return	-E2BIG;
+				}
+			}
+		}
+
+		cp = kstrp + 1;
+		while (isspace(*cp))
+			cp++;
+		kstrp = strchr(cp, ' ');
+		if (kstrp) {
+			kstrp[0] = 0;
+			kstrp++;
+		}
+
+		if (kstrtoul(cp, 10, &idx) || idx < 0 || idx > 7) {
+			printk(KERN_ERR "bad index %ld [0..7]\n", idx);
+			return	-ERANGE;
+		}
+		printk(KERN_INFO "%px: e %d i %ld\n", db, event, idx);
+		db->data[idx] = event;
+		cp = kstrp;
+	} while (cp);
+	db->hd_magic = NSS_PROFILE_HD_MAGIC | NSS_PROFILER_SET_SYS_STAT_EVENT;
+	result = nss_profiler_if_tx_buf(pio->ctx, &pio->pnc.un, sizeof(pio->pnc.un),
+				profiler_handle_stat_event_reply, pio);
+	profileInfo("%px: %zd send cmd %x to FW ret %d\n",
+			db, count, db->hd_magic, result);
+	return	count;
+}
+
+/*
+ * parseDbgData()
+ *	parsing debug requests: base_address [options] cmd length
+ *
+ * cmd is either read or write
+ * option is one of mio, moveio, h [heap security verify], etc.
+ */
+static int parseDbgData(const char *buf, size_t count, struct debug_box *db)
+{
+	char *cp;
+	int n;
+
+	printk("%px %px: buf (%s) cnt %zd\n", db, buf, buf, count);
+	if (sscanf(buf, "%x", (uint32_t *)&db->base_addr) != 1) {
+		printk("%s: cannot get base addr\n", __func__);
+		return	-EINVAL;
+	}
+
+	cp = strchr(buf, ' ');
+	if (!cp) {
+noea:		printk("%s: no enough arguments\n", __func__);
+		return -EFAULT;
+	}
+
+	while (isspace(*cp)) cp++;
+	if (!strncmp(cp, "mio", 3) || !strncmp(cp, "moveio", 6)) {
+		printk("%px: cp (%s)\n", cp, cp);
+		cp = strchr(cp, ' ');
+		if (!cp) {
+			goto noea;
+		}
+		db->opts |= DEBUG_OPT_MOVEIO;
+	}
+
+	while (isspace(*cp)) cp++;
+	printk("base addr %X -- %s", db->base_addr, cp);
+
+	if (!strncmp(cp, "read", 4)) {
+		cp = strchr(cp, ' ');
+		if (cp) {
+			while (isspace(*cp)) cp++;
+			sscanf(cp, "%x", &db->dlen);
+		}
+		return 0;
+	}
+
+	n = 0;
+	do {
+		while (isspace(*cp)) cp++;
+		if (sscanf(cp, "%x", db->data+n) != 1) {
+			printk("n %d : %s\n", n, cp);
+			break;
+		}
+		printk("write %x to off %zx\n", db->data[n], n * sizeof(db->data[0]));
+		n++;
+		cp = strchr(cp, ' ');
+	} while (cp && n < MAX_DB_WR);
+	return n;
+}
+
+/*
+ * debug_if_show
+ *	display memory content read from Phy addr
+ */
+static void debug_if_show(struct debug_box *db, int buf_len)
+{
+	int i;
+
+	for (i=0; i < db->dlen; i++) {
+		if ((i & 3) == 0)
+			printk("\n%zX: ", db->base_addr + i * sizeof(db->base_addr));
+		printk("%9x", db->data[i]);
+	}
+	printk("\ndumped %d (extra 1) blen %d\n", db->dlen, buf_len);
+}
+
+/*
+ * profiler_handle_debug_reply
+ *	show debug message we requested from NSS
+ */
+static void profiler_handle_debug_reply(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm)
+{
+	debug_if_show((struct debug_box*)&ncm[1], ncm->len);
+}
+
+/*
+ * debug_if
+ *	a generic Krait <--> NSS debug interface
+ */
+static ssize_t debug_if(struct file *filp,
+			const char __user *ubuf, size_t count, loff_t *f_pos)
+{
+	char *buf;
+	int result;
+	struct debug_box *db;
+	struct profile_io *pio = (struct profile_io *)filp->private_data;
+
+	if (!pio) {
+		return -ENOENT;
+	}
+
+	if (!pio->pnc.enabled) {
+		return -EPERM;
+	}
+
+	buf = kmalloc(count, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	if (copy_from_user(buf, ubuf, count)) {
+		kfree(buf);
+		printk(KERN_ERR "copy_from_user\n");
+		return -EIO;
+	}
+	buf[count-1] = 0;
+
+	db = (struct debug_box *) &pio->pnc;
+	db->dlen = db->opts = 0;
+
+	/*
+	 * process possible commands
+	 */
+	if (buf[0] == '=') {
+		result = parseDbgCmd(buf+1, count, db, pio);
+		kfree(buf);
+		return result;
+	}
+
+	/*
+	 * process stat_event request: display/change
+	 */
+	if (!isdigit(buf[0])) {
+		result = parse_sys_stat_event_req(buf, count, db, pio);
+		kfree(buf);
+
+		if ((result > 0) && (filp->f_flags & O_RDWR)) {
+			/*
+			 * set flag so event-counter can read the data from FW
+			 */
+			pio->sw_ksp_ptr = db->data;
+		}
+		return	result;
+	}
+
+	/*
+	 * process memory I/O for debug
+	 */
+	result = parseDbgData(buf, count, db);
+	kfree(buf);
+	if (result < 0) {
+		return	result;
+	}
+
+	if (!result) {
+		db->hd_magic = NSS_PROFILE_HD_MAGIC | NSS_PROFILER_DEBUG_RD_MSG;
+	} else {
+		db->hd_magic = NSS_PROFILE_HD_MAGIC | NSS_PROFILER_DEBUG_WR_MSG;
+		db->dlen = result;
+	}
+	result = nss_profiler_if_tx_buf(pio->ctx, &pio->pnc.un,
+			sizeof(pio->pnc.un), profiler_handle_debug_reply, pio);
+	printk("dbg res %d dlen = %d opt %x\n", result, db->dlen, db->opts);
+	return	count;
+}
+
+static const struct file_operations profile_fops = {
+	.open		= profile_open,
+	.read		= profile_read,
+	.release	= profile_release,
+	.write		= debug_if,
+};
+
+/*
+ * showing sample status on Linux console
+ */
+static int profile_rate_show(struct seq_file *m, void *v)
+{
+	struct profile_io *pn = node[0];
+	if (pn) {
+		struct nss_profile_sample_ctrl *psc_hd = &pn->pnc.pn2h->psc_header;
+		seq_printf(m, "%d samples per second.  %d ultra, %d linux virtual counters.  %d dropped samples.  %d queued of %d max sampels.  %d sent packets.\n",
+			pn->pnc.un.rate, pn->pnc.un.num_counters, profile_num_counters, psc_hd->ps_dropped, psc_hd->ps_count, psc_hd->ps_max_samples, pn->profile_sequence_num);
+	} else {
+		seq_printf(m, "Profiler is not initialized.\n");
+	}
+	return 0;
+}
+
+static int profile_rate_open(struct inode *inode, struct file *filp)
+{
+	return single_open(filp, profile_rate_show, NULL);
+}
+
+static ssize_t profile_rate_write(struct file *filp, const char *buf, size_t len, loff_t *off)
+{
+	*off = 0;
+	return 0;
+}
+
+static const struct file_operations profile_rate_fops = {
+	.open		= profile_rate_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+	.write		= profile_rate_write,
+};
+
+/*
+ * hexdump
+ *	hex dump for debug
+ */
+static void kxdump(void *buf, int len, const char *who)
+{
+	int32_t *ip = (int32_t *) buf;
+	int lns = len >> 5;	/* 32-B each line */
+	if (lns > 8)
+		lns = 8;
+	printk("%px: kxdump %s: len %d\n", buf, who, len);
+	do {
+		printk("%x %x %x %x %x %x %x %x\n", ip[0], ip[1], ip[2], ip[3], ip[4], ip[5], ip[6], ip[7]);
+		ip += 8;
+	} while (lns--);
+}
+
+/*
+ * profiler_magic_verify
+ *	check magic # and detect Endian.
+ *
+ * negtive return means failure.
+ * return 1 means need to ntoh swap.
+ */
+static int profiler_magic_verify(struct nss_profile_sample_ctrl *psc_hd, int buf_len)
+{
+	int swap = 0;
+	if ((psc_hd->psc_magic & NSS_PROFILE_HD_MMASK) != NSS_PROFILE_HD_MAGIC) {
+		if ((psc_hd->psc_magic & NSS_PROFILE_HD_MMASK_REV) != NSS_PROFILE_HD_MAGIC_REV) {
+			kxdump(psc_hd, buf_len, "bad profile packet");
+			printk("bad profile HD magic 0x%x : %d\n",
+				psc_hd->psc_magic, buf_len);
+			return -1;
+		}
+		profileDebug("Profile data in different Endian type %x\n", psc_hd->psc_magic);
+		swap = 1;
+		psc_hd->psc_magic = ntohl(psc_hd->psc_magic);
+	}
+	return swap;
+}
+
+/*
+ * profile_handle_nss_data
+ *	process profile sample data from NSS
+ */
+static void profile_handle_nss_data(void *arg, struct nss_profiler_msg *npm)
+{
+	int buf_len = npm->cm.len;
+	void *buf = &npm->payload;
+	struct profile_io *pn;
+	struct nss_profile_n2h_sample_buf *nsb;
+	struct nss_profile_sample_ctrl *psc_hd = (struct nss_profile_sample_ctrl *)buf;
+	int	ret, wr;
+	int	swap = 0;	/* only for header and info data, not samples */
+
+	if (buf_len < (sizeof(struct nss_profile_session) - sizeof(struct profile_counter) * (PROFILE_MAX_APP_COUNTERS))) {
+		profileWarn("%px: profile data packet is too small to be useful %d %x psc_hd %px\n",
+			npm, buf_len, npm->cm.interface, psc_hd);
+		return;
+	}
+
+	swap = profiler_magic_verify(psc_hd, buf_len);
+	if (swap < 0) {
+		return;
+	}
+
+	pn = (struct profile_io *)arg;
+	profileDebug("PN %px CM msg %d len %d\n", pn, npm->cm.type, buf_len);
+	profileInfo("%s: dlen %d swap %d cmd %x - %d\n", __func__, buf_len, swap, npm->cm.type, (pn->ccl_read - pn->ccl_write) & (CCL_SIZE-1));
+	//kxdump(buf, buf_len, "process profile packet");
+
+	if (npm->cm.type == NSS_PROFILER_FIXED_INFO_MSG) {
+		struct nss_profile_session *pTx = (struct nss_profile_session *)buf;
+		if (swap) {
+			pn->pnc.un.rate = ntohl(pTx->rate);
+			pn->pnc.un.cpu_id = ntohl(pTx->cpu_id);
+			pn->pnc.un.cpu_freq = ntohl(pTx->cpu_freq);
+			pn->pnc.un.ddr_freq = ntohl(pTx->ddr_freq);
+			pn->pnc.un.num_counters = pTx->num_counters;
+		} else {
+			pn->pnc.un = *pTx;
+		}
+		memcpy(pn->pnc.un.counters, pTx->counters, pn->pnc.un.num_counters * sizeof(pn->pnc.un.counters[0]));
+		pn->profile_first_packet = 1;
+		return;
+	}
+
+	wr = (pn->ccl_write + 1) & (CCL_SIZE-1);
+	nsb = pn->ccl + wr;
+	swap = (pn->ccl_read - wr) & (CCL_SIZE-1);	/* PROFILER_FLOWCTRL */
+	if (nsb->mh.md_type != PINGPONG_EMPTY || (swap && swap < 5)) {
+		if (pn->pnc.enabled > 0) {
+			pn->pnc.enabled = -1;
+			pn->pnc.un.hd_magic = NSS_PROFILE_HD_MAGIC | NSS_PROFILER_STOP_MSG;
+			ret = nss_profiler_if_tx_buf(pn->ctx,
+					&pn->pnc.un, sizeof(pn->pnc.un),
+					profiler_handle_reply, pn);
+			profileWarn("%d temp stop sampling engine %d\n", swap, ret);
+		}
+		if (swap < 3) {
+			profileWarn("w%px.%d: %d no room for new profile samples r%px.%d\n", nsb, wr, swap, pn->ccl+pn->ccl_read, pn->ccl_read);
+			return;	/* -EMSGSIZE */
+		}
+	}
+	pn->ccl_write = wr;
+
+	/*
+	 * sampling data -- hdr NBO swap is done at NSS side via SWAPB.
+	 */
+	memcpy(&nsb->psc_header, buf, buf_len); /* pn->pnc.pn2h->psc_header = *psc_hd; maybe faster, but take more memory */
+
+	nsb->mh.md_type = PINGPONG_FULL;
+
+	/*
+	 * ask for perf_counters (software counters) update every 32 samples
+	 */
+	if (!wr) {
+		pn->pnc.un.hd_magic = NSS_PROFILE_HD_MAGIC | NSS_PROFILER_COUNTERS_MSG;
+		ret = nss_profiler_if_tx_buf(pn->ctx, &pn->pnc.un,
+				sizeof(pn->pnc.un), profiler_handle_reply, pn);
+		if (ret == NSS_TX_FAILURE)
+			printk("req counters Cmd failed %d %d\n", ret, wr);
+	}
+	profileInfo("filled %px %px wr %d\n", nsb, nsb->samples, pn->ccl_write);
+}
+
+/*
+ * profiler_dma_handler
+ *	Handle DMA interrupt, and map DMA to N2H to minimize changes
+ * in profile_handle_nss_data.
+ */
+static void profiler_dma_handler(void *arg)
+{
+	int cri, idx, widx;
+	struct nss_profiler_msg *npm;
+	struct nss_profile_sdma_consumer *cbc;
+	struct nss_profile_sdma_producer *dma;
+	struct profile_io *pn = (struct profile_io *)arg;
+	struct nss_profile_sdma_ctrl *ctrl = nss_profile_dma_get_ctrl(pn->ctx);
+
+	if (!ctrl) {
+		profileWarn("%px: cannot get dma ctrl block\n", pn->ctx);
+		return;
+	}
+
+	dma = ctrl->producer;
+	cbc = ctrl->consumer;
+	cri = ctrl->cur_ring;
+	idx = ctrl->cidx[cri];
+	widx = ctrl->pidx[cri];
+
+	if (idx == widx) {
+		profileInfo("%px: dma[%d]%d %px sz %d no more profile data %px (%zd)\n",
+			ctrl, cri, idx, dma, dma->buf_size,
+			cbc->ring.kp + idx * dma->buf_size, sizeof(*ctrl));
+		return;
+	}
+
+	do {
+		npm = cbc->ring.kp + idx * dma->buf_size;
+
+		dmac_inv_range(npm, &npm->payload);
+		dsb(sy);
+
+		dmac_inv_range(&npm->payload, (void *)&npm->payload + npm->cm.len);
+		dsb(sy);
+
+		profile_handle_nss_data(pn, npm);
+		idx = (idx + 1) & (dma->num_bufs - 1);
+	} while (idx != widx);
+
+	ctrl->cidx[cri] = idx;
+	profileInfo("flush %px %px r %d w %d(%d)\n", cbc, cbc->ring.kp, idx, widx, ctrl->pidx[cri]);
+	dmac_clean_range(ctrl->cidx + cri, ctrl->cidx + cri + 1);
+	dsb(sy);
+}
+
+/*
+ * profiler_handle_reply
+ *	process N2H reply for message we sent to NSS
+ */
+static void profiler_handle_reply(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm)
+{
+	switch (ncm->response) {
+	default:
+		if (ncm->error == PROFILE_ERROR_NO_DMA) {
+			struct nss_profile_sdma_consumer *cbc;
+			struct nss_profile_sdma_ctrl *ctrl;
+			struct profile_io *pn = node[0];
+
+			if (!pn || pn->ctx != nss_ctx) {
+				pn = node[1];
+				if (!pn || pn->ctx != nss_ctx)
+					return;
+			}
+
+			ctrl = nss_profile_dma_get_ctrl(nss_ctx);
+			if (!ctrl) {
+				profileWarn("%px: profiler can't get DMA\n", nss_ctx);
+				return;
+			}
+
+			cbc = ctrl->consumer;
+			cbc->ring.kp = profiler_get_dma(nss_ctx, pn);
+			if (cbc->ring.kp) {
+				pn->pnc.un.hd_magic = NSS_PROFILE_HD_MAGIC | NSS_PROFILER_START_MSG;
+				if (nss_profiler_if_tx_buf(pn->ctx, &pn->pnc.un,
+					sizeof(pn->pnc.un), profiler_handle_reply, pn)
+						== NSS_TX_SUCCESS)
+					return;
+			}
+		}
+
+		profileWarn("%px: profiler had error response %d\n", nss_ctx, ncm->response);
+		/*
+		 * fail through -- no plan to do anything yet
+		 */
+	case NSS_CMN_RESPONSE_ACK:
+		return;
+	}
+}
+
+/*
+ * profile_prepare_dma()
+ *	Allocate DMA for profile if no DMA allocated; then register
+ * callback to handle interrupt for reading samples.
+ */
+static bool profile_prepare_dma(struct profile_io *node)
+{
+	struct nss_profile_sdma_ctrl *ctrl = nss_profile_dma_get_ctrl(node->ctx);
+
+	if (!ctrl)
+		return 0;
+
+	if (!ctrl->consumer[0].ring.kp)
+		ctrl->consumer[0].ring.kp = profiler_get_dma(node->ctx, node);
+
+	/*
+	 * register_noncd_cb will not fail since (!ctrl) has been checked above.
+	 * The ctrl is allocated in driver side, so even in impossible event to
+	 * cause register_noncd_cb failed, no need to release dma since calling
+	 * this function will not allocate another DMA if a DMA alerady exists.
+	 */
+	return (bool)nss_profile_dma_register_cb(node->ctx, 0, profiler_dma_handler, (void*)node);
+}
+
+/*
+ * profile_init
+ *	initialize basic profile data structure
+ */
+static void profile_init(struct profile_io *node)
+{
+	int n;
+
+	memset(&node->pnc, 0, sizeof(node->pnc));
+	node->ccl_read = 0;
+	node->ccl_write = -1;
+	node->pnc.pn2h = node->ccl;
+	node->pnc.samples = node->ccl->samples;
+
+	for (n = 0; n < CCL_SIZE; n++) {
+		node->ccl[n].mh.md_type = PINGPONG_EMPTY;
+		node->ccl[n].psc_header.ps_count = 0;
+	}
+
+	/*
+	 * sw_ksp is an array of pointers to struct thread_info,
+	 * the current task executing for each linux virtual processor
+	node->sw_ksp_ptr = sw_ksp;
+	 */
+	node->sw_ksp_ptr = NULL;
+	/*
+	 * Old profile info: unused by now
+	 * node->task_offset = offsetof(struct thread_info, task);
+	 * node->pid_offset = offsetof(struct task_struct, tgid);
+	 */
+}
+
+static struct proc_dir_entry *pdir;
+
+/*
+ * netap_profile_release_resource
+ *	init_module cannot call exit_MODULE, so use this wrapper
+ */
+void netap_profile_release_resource(void)
+{
+	if (pdir) {
+		remove_proc_entry("rate", pdir);
+		remove_proc_entry("data", pdir);
+		remove_proc_entry("data1", pdir);
+		proc_remove(pdir);
+		pdir = NULL;
+	}
+
+	if (node[0]->ctx) {
+		nss_profile_dma_deregister_cb(node[0]->ctx, 0);
+		if (node[1] && node[1]->ctx) {
+			nss_profile_dma_deregister_cb(node[1]->ctx, 0);
+			nss_profiler_release_dma(node[1]->ctx);
+			/*
+			 * node[1] memory is part of node[0] allocation; same as the ccl.
+			 */
+			node[1] = NULL;
+		}
+		nss_profiler_release_dma(node[0]->ctx);
+	}
+	kfree(node[0]->ccl);
+	kfree(node[0]);
+	node[0] = NULL;
+}
+
+/*
+ * netap_profile_init_module
+ *	kernel module entry
+ */
+int __init netap_profile_init_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+	/*
+	 * we need N nodes, not one node + N ctx, for N cores
+	 */
+	node[0] = kmalloc(sizeof(*node[0]) * NSS_MAX_CORES, GFP_KERNEL);
+	if (!node[0]) {
+		profileWarn("Profiler CTRL kmalloc failed.\n");
+		return -ENOMEM;
+	}
+
+	node[0]->ccl = kmalloc(sizeof(*node[0]->ccl) * CCL_SIZE * NSS_MAX_CORES, GFP_KERNEL);
+	if (!node[0]->ccl) {
+		profileWarn("Profiler n2h_sample_buf kmalloc failed.\n");
+		kfree(node[0]);
+		node[0] = NULL;
+		return -ENOMEM;
+	}
+
+	/*
+	 * connect to the file system
+	 */
+	pdir = proc_mkdir("profile", NULL);
+	if (!pdir ||
+	    !proc_create("data", 0, pdir, &profile_fops) ||
+	    !proc_create("data1", 0, pdir, &profile_fops) ||
+	    !proc_create("rate", 0, pdir, &profile_rate_fops)) {
+		netap_profile_release_resource();
+		return -ENOMEM;
+	}
+
+	profile_init(node[0]);
+
+	/*
+	 * attatch the device callback to N2H channel for CPU 0
+	 */
+	node[0]->ctx = nss_profiler_notify_register(NSS_CORE_0, profile_handle_nss_data, node[0]);
+	if (!node[0]->ctx) {
+		netap_profile_release_resource();
+		return -ENXIO;
+	}
+	profile_prepare_dma(node[0]);
+
+#if NSS_MAX_CORES > 1
+	node[1] = node[0] + 1;
+	node[1]->ccl = node[0]->ccl + CCL_SIZE;
+
+	profile_init(node[1]);
+	node[1]->ctx = nss_profiler_notify_register(NSS_CORE_1, profile_handle_nss_data, node[1]);
+	profile_prepare_dma(node[1]);
+
+	profile_register_performance_counter(&node[1]->profile_sequence_num, "Profile1 DRV data packets");
+#endif
+
+	profile_register_performance_counter(&node[0]->profile_sequence_num, "Profile0 DRV data packets");
+	return 0;
+}
+
+/*
+ * netap_profile_exit_module
+ *	kernel module exit
+ */
+void __exit netap_profile_exit_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return;
+	}
+#endif
+	nss_profiler_notify_unregister(NSS_CORE_0);
+#if NSS_MAX_CORES > 1
+	nss_profiler_notify_unregister(NSS_CORE_1);
+#endif
+	netap_profile_release_resource();
+}
+
+module_init(netap_profile_init_module);
+module_exit(netap_profile_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/qca-nss-clients/profiler/profilenode.h b/qca-nss-clients/profiler/profilenode.h
new file mode 100644
index 0000000..9cae122
--- /dev/null
+++ b/qca-nss-clients/profiler/profilenode.h
@@ -0,0 +1,150 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, 2018 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss profile node.h
+ *	device node for the profiler, for communicating between FW and GUI via host
+ */
+
+#include "profilesample.h"
+
+#define	NSS_PROFILE_HD_MAGIC		0x4F525000	/* 0 + "PRO" */
+#define	NSS_PROFILE_HD_MAGIC_REV	0x0050524F	/* different endian */
+#define	NSS_PROFILE_HD_MMASK		0xFFFFFF00	/* 1st byte is Rx/Tx cmd */
+#define	NSS_PROFILE_HD_MMASK_REV	0x00FFFFFF
+
+struct nss_profile_sample_ctrl {
+	uint32_t psc_magic;	/* MAGIC + cmd for packet and endianess check */
+
+	/*
+	 * controlling data need to be sent to and used by upper layer (HLOS).
+	 */
+	uint16_t ps_count;	/* number of valid samples */
+	uint16_t ps_max_samples; /* how many samples can be in the samples array */
+	uint32_t ps_dropped;	/* how many samples did the profiler drop due to buffer overruns */
+
+	/*
+	 * info data -- sent to remote profiler tool (need swap)
+	 */
+	struct profile_ext_header ex_hd;
+
+};
+
+/*
+ * # of sample buffers in pbuf payload
+ */
+#ifndef	PBUF_PAYLOAD_SIZE
+#define	PBUF_PAYLOAD_SIZE	1792	/* for HLOS driver: must sync with pbuf_public */
+typedef enum meta_types {
+	PINGPONG_EMPTY,
+	PINGPONG_FULL,
+	PINGPONG_INUSE,
+} flowctrl_t;
+#else
+typedef enum pnode_c2h_metadata_types	flowctrl_t;	/* for NSS driver */
+#endif
+
+#define	MAX_SAMPLES_PER_PBUF	((PBUF_PAYLOAD_SIZE - sizeof(struct nss_profile_sample_ctrl)) / sizeof(struct nss_profile_sample))
+
+struct n2h_meta_header {
+	flowctrl_t md_type;	/* N2H (NSS) and receiver (HLOS) flow control (meta type) */
+	uint32_t d_len;		/* total data length start from psc_header */
+};
+
+struct nss_profile_session {	/* use for per session start */
+	uint32_t hd_magic;	/* common ovarlay in all headers */
+	uint8_t	num_counters;	/* # performance (app) counters registered (changeable) */
+	uint8_t	unused1B;
+	uint8_t nc_sts_sel_thrA;
+	uint8_t nc_sts_sel_thrB;
+	uint32_t ocm_size;
+	uint32_t sram_start;
+
+	uint32_t rate;		/* sampling rate */
+	uint32_t cpu_id;	/* chip_id register */
+	uint32_t cpu_freq;	/* chip clock */
+	uint32_t ddr_freq;	/* DDR MEM speed */
+	struct profile_counter counters[PROFILE_MAX_APP_COUNTERS];
+};
+
+struct nss_profile_n2h_sample_buf {
+	struct n2h_meta_header	mh;
+
+	struct nss_profile_sample_ctrl	psc_header;	/* per sample period */
+	struct nss_profile_sample	samples[MAX_SAMPLES_PER_PBUF];	/* per thread samples - for NSS send */
+};
+
+struct nss_profile_common {
+	struct nss_profile_session un;
+	/*
+	 * changable data sent everything pbuf
+	 */
+	struct nss_profile_n2h_sample_buf *pn2h; /* sampling ctrl for this sample period */
+	struct nss_profile_sample *samples;	/* samples array was allocated by the linux driver */
+					/* now NSS points it to pbuf + pn2h header */
+	uint16_t	cur;		/* pos where driver take (read) samples */
+	int16_t		enabled;	/* Is the profiler enabled to take samples? */
+};
+
+/*
+ * Each buffer holds 4-7 sets (sample intrs) of samples, by average 5 sets per buffer
+ * at 10ms sample clock; 1s sleep in profilerd requires kernel to have 1000 / 10 / 5 = 20
+ * buffers to store one 1s samples. For higher sampling rate, either kernel needs more
+ * buffers or profilerd needs less sleep time, but both needs to make match.
+ */
+#define	CCL_SIZE	32
+
+struct profile_io {
+	struct nss_profile_common	pnc;
+
+	/*
+	 * control fields - HLOS
+	 */
+	void	*ctx;		// nss_ctx for Linux driver
+	int	profile_first_packet;
+	int	profile_sequence_num;
+
+	/*
+	 * circular buffers for psc_header/samples
+	 */
+	struct nss_profile_n2h_sample_buf *ccl;
+	int	ccl_read;
+	int	ccl_write;
+
+	/*
+	 * data from HLOS -- used to generate sample->pid in ULTRA -- no longer needed in NSS
+	 * uint32_t task_offset; offset in bytes in thread_info to task_struct pointer
+	 * uint32_t pid_offset;	offset in bytes in task_struct to the PID
+	 */
+	uint32_t *sw_ksp_ptr;	// pointer to array (per hardware thread) of pointers to struct thread_info
+};
+
+/*
+ * Krait <--> NSS debug mechanism. It lays over on nss_profile_n2h_sample_buf.samples (ccl->samples)
+ */
+#define	MAX_DB_WR	28	// profile_session has 31 4B words data (32W total with hd_magic) and
+#define	MAX_DB_RD	30	// common has two more ptrs
+struct debug_box {		// this overlays with profile_common (RD) or profile_session (WR)
+	uint32_t hd_magic;	// cmd + MAGIC for packet and endianess check
+
+	uint32_t opts;
+	int32_t base_addr;	/* Ubi32 is 32-bit */
+	int32_t	dlen;		// in 4B words
+	uint32_t data[MAX_DB_RD];
+};
+
+#define	DEBUG_OPT_BCTRL	1		// basic CTRL
+#define	DEBUG_OPT_MOVEIO	(1<<1)	// force to use moveio in case new OCP range is added
diff --git a/qca-nss-clients/profiler/profilesample.h b/qca-nss-clients/profiler/profilesample.h
new file mode 100644
index 0000000..c352628
--- /dev/null
+++ b/qca-nss-clients/profiler/profilesample.h
@@ -0,0 +1,90 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, 2018 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * profilesample.h
+ *	Sample format for profiling
+ */
+
+#ifndef	_NSS_PROFILE_SAMPLE_H_
+#define	_NSS_PROFILE_SAMPLE_H_
+
+#define NSS_PROFILE_STACK_WORDS 4
+
+/*
+ * Each sample is for an enabled thread, not including the profiling thread.
+ * HRT thread sampling is optional.
+ * Sampled threads may be active or inactive.  Samples are included in thread number
+ * order, so each sample interval has a set of samples starting with one from thread 0
+ *
+ * Samples include bits indicating if this thread is blocked
+ */
+#define NSS_PROFILE_I_BLOCKED_BIT 5
+#define NSS_PROFILE_I_BLOCKED (1 << NSS_PROFILE_I_BLOCKED_BIT)
+#define NSS_PROFILE_D_BLOCKED_BIT 4
+#define NSS_PROFILE_D_BLOCKED (1 << NSS_PROFILE_D_BLOCKED_BIT)
+#define NSS_PROFILE_BTB_SHIFT 6
+
+struct nss_profile_sample {
+	uint32_t pc;		/* PC value */
+	uint32_t pid;		/* pid for the current process, or 0 if NOMMU or unmapped space */
+	uint16_t active;	/* threads are active - for accurate counting */
+	uint16_t d_blocked;	/* threads are blocked due to D cache misses : may be removed */
+	uint16_t i_blocked;	/* threads are blocked due to I cache misses */
+	uint8_t cond_codes;	/* for branch prediction */
+	uint8_t thread;		/* 4-bit thread number */
+	uint32_t a_reg;		/* source An if PC points to a calli.  Otherwise a5 contents for parent of leaf function */
+	uint32_t parent[NSS_PROFILE_STACK_WORDS];
+				/* return addresses from stack, to find the caller */
+};
+
+
+/*
+ * packet size for profile communication = MSS - tcp/ip headers
+ */
+#define NSS_PROFILE_MAX_PACKET_SIZE 1440
+
+#define NSS_PROFILE_MAX_COUNTERS ((NSS_PROFILE_MAX_PACKET_SIZE - sizeof(struct profile_header_counters)) / (PROFILE_COUNTER_NAME_LENGTH + 4))
+
+struct profile_counter {
+	char name[PROFILE_COUNTER_NAME_LENGTH];
+	uint32_t value;
+};
+
+/*
+ * NSS HW counters and CPU threads
+ */
+#define NSS_HW_COUNTERS 8
+#define	NSS_CPU_THREADS	12
+
+/*
+ * sampling period info cross all modules -- use extended struct to avoid copy
+ */
+struct profile_ext_header {
+	uint16_t d_blocked;	/* threads are blocked due to D cache misses */
+	uint16_t i_blocked;	/* threads are blocked due to I cache misses */
+	uint16_t high;		/* threads were enabled high priority -- unused */
+	uint16_t enabled_threads;	/* threads were enabled at the last sample time */
+	uint16_t hrt;		/* HRT threads */
+	uint8_t profiler_tid;	/* thread running the profile sampler */
+	uint8_t sample_sets;	/* typical 5-8 sets, and may be 9 - see design doc for details */
+	uint32_t sets_map;	/* a set map uses a nibble, 8 maps and 9th is derived */
+	uint32_t clocks;		/* system clock timer at last sample */
+	uint32_t inst_count[NSS_CPU_THREADS]; /* sampled instruction counts at most recent sample */
+	uint32_t stats[NSS_HW_COUNTERS]; /* contents of the cache statistics counters */
+};
+
+#endif	/* _NSS_PROFILE_SAMPLE_H_ */
diff --git a/qca-nss-clients/profiler/profpkt.h b/qca-nss-clients/profiler/profpkt.h
new file mode 100644
index 0000000..331afec
--- /dev/null
+++ b/qca-nss-clients/profiler/profpkt.h
@@ -0,0 +1,142 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * profpkt.h
+ *      profile packet header to communicate with the profiler display tool
+ *
+ * IMPORTANT!  There is a parallel verison of this file for both linux driver and profiler display tool
+ *
+ * Both this file and profilesample.h file must be placed
+ * in dirver/.../nss (for linux driver)	and as well as	in tools/profiler/include directories
+ *	(for profilerd.c of profilerd and profile.cpp:1600::on_packet of profile tool).
+ *
+ *   Ubi32 CPU Profiler packet formats for communication between the linux proc driver and the profiler display tool
+ */
+
+#include "profilesample.h"	// common definitions
+
+#define PROFILE_PORT 51080
+#define PROFILE_CONTROL_PORT 51081
+#define PROFILE_POSIX_NAME_LENGTH 32
+
+/*
+ * profile UDP packet format for communicating between ip3k and host
+ *
+ * every packet starts with a header, followed by samples.
+ * samples are only taken for non-hrt threads that are
+ * active
+ */
+#define PROF_MAGIC 0x3ea0
+#define PROF_MAGIC_COUNTERS 0x9ea0
+#define PROF_MAGIC_MAPS 0xaea0
+
+/*
+ * Versions (31 max):
+ * 1 to 4 were before 6.0 release,  development versions
+ * 5 was forward compatible version, shipped with 6.0 and 6.1
+ * 6 adds heap packets, and clock_freq to header, shipped with 6.2
+ * 7 adds a sequence numbers to check for dropped packets, shipped with 6.3.5
+ * 8 adds mqueue timing information, shipped with 6.3.5
+ * 9 adds sdram heap size information, shipped with 6.4
+ * 10 adds heapmem heap callers and long latency stack traces.  shipped with 6.4
+ * 11 adds support for Mars (IP5K).  shipped with 6.10
+ * 12 adds more support for Mars.  Shipped with 7.0
+ * 13 adds per sample latency measurement.  Shipped with 7.2
+ * 14 changes the heap format and adds a string packet.  Shipped with 7.4
+ * 15 adds dsr stats and posix.  shipped with 7.6
+ * 16 corrects maximum packet count for Ares.  ships with 7.9
+ * 17 adds a5 register value to sample
+ * 18 adds counter support and removes unused header fields
+ * 19 adds PID support for MMU profiling
+ * 20 changes the protocol for transmitting map PID maps automatically
+ * 21 adds support for multiple possible parents, configurable
+ */
+
+#define PROFILE_VERSION 21
+
+
+/*
+ * Each packet starts with a profile_header, then sample_count samples;
+ * samples are gprof samples of pc, the return address, condition codes, and active threads.
+ * For performance concern, the field sequence may be reordered to match profilenode to reduce
+ * a memory copy.
+ */
+struct profile_pkg_header {		// in network byte order !
+	uint16_t magic;			/* magic number and version */
+	uint8_t header_size;		/* number of bytes in profile header */
+	uint8_t sample_count;		/* number of samples in the packet */
+	uint8_t nc_sts_tselA;		/* thr 1 statistics requst to FW */
+	uint8_t nc_sts_tselB;		/* thr 2 requst to FW */
+	uint8_t spare1B;
+	uint8_t sample_stack_words;	/* number of stack words in the sample */
+	uint32_t seq_num;		/* to detect dropped profiler packets */
+	uint32_t profile_instructions;	/* instructions executed by profiler mainline */
+
+	uint32_t unused_overlay;	//  untouched fields below in Linux -- to reduce memcpy
+	uint32_t cpu_id;		/* CHIP_ID register contents */
+	uint32_t clock_freq;		/* clock frequency (Hz) of system being analyzed */
+	uint32_t ddr_freq;		/* DDR clock frequency */
+};
+
+struct profile_header {		// in network byte order !
+	struct profile_pkg_header pph;
+	struct profile_ext_header exh;
+};
+
+struct profile_header_counters {
+	uint16_t magic;
+	uint16_t ultra_count;		// how many ultra counters follow this
+	uint32_t ultra_sample_time;	// in chip clocks
+	uint32_t linux_count;		// how many linux counters follow this
+	uint32_t linux_sample_time;
+};
+
+/*
+ * send memory maps from linux to profiler tool
+ */
+
+struct profile_header_maps {
+	uint16_t magic;			/* magic number and last packet bit */
+	uint16_t count;
+	uint32_t page_shift;
+};
+
+#define PROFILE_MAP_NUM_TYPES 16
+
+/* size field is pages.  True size in bytes is (1 << PAGE_SHIFT) * size */
+#define PROFILE_MAP_TYPE_FREE 0
+#define PROFILE_MAP_TYPE_SMALL 1
+#define PROFILE_MAP_TYPE_FS 2
+#define PROFILE_MAP_TYPE_UNKNOWN_USED 4
+#define PROFILE_MAP_TYPE_TEXT 5
+#define PROFILE_MAP_TYPE_STACK 6
+#define PROFILE_MAP_TYPE_APP_DATA 7
+#define PROFILE_MAP_TYPE_ASHMEM 8
+#define PROFILE_MAP_TYPE_READ_SHARED 9
+#define PROFILE_MAP_TYPE_CACHE 10
+#define PROFILE_MAP_TYPE_VMA_WASTE 11
+#define PROFILE_MAP_RESERVED 15
+
+#define PROFILE_MAP_TYPE_SHIFT 12
+#define PROFILE_MAP_SIZE_MASK 0xfff
+
+struct profile_map {
+	uint16_t start;		/* start page number of segment, relative to start of OCM (Max 256 MB on IP7K or 1 GB on IP8K, plus 256 KB OCM) */
+	uint16_t type_size;	/* type (4 bits) of the segment and size (12 bits) in pages. A size of 0 means 4K pages */
+};
+
+#define PROFILE_MAX_MAPS (PROFILE_MAX_PACKET_SIZE - sizeof(struct profile_header_maps)) / sizeof(struct profile_map)
diff --git a/qca-nss-clients/pvxlanmgr/Makefile b/qca-nss-clients/pvxlanmgr/Makefile
new file mode 100644
index 0000000..aa7829a
--- /dev/null
+++ b/qca-nss-clients/pvxlanmgr/Makefile
@@ -0,0 +1,6 @@
+ccflags-y := -I$(obj)/../exports -I$(obj)/..  -I$(obj)/nss_hal/include \
+	-DNSS_CLIENT_BUILD_ID="$(BUILD_ID)" -DNSS_PVXLANMGR_DEBUG_LEVEL=2 -Wall -Werror
+
+obj-m += qca-nss-pvxlanmgr.o
+qca-nss-pvxlanmgr-objs := nss_pvxlanmgr.o
+qca-nss-pvxlanmgr-objs += nss_pvxlanmgr_tunnel.o
diff --git a/qca-nss-clients/pvxlanmgr/nss_pvxlanmgr.c b/qca-nss-clients/pvxlanmgr/nss_pvxlanmgr.c
new file mode 100644
index 0000000..e1d749f
--- /dev/null
+++ b/qca-nss-clients/pvxlanmgr/nss_pvxlanmgr.c
@@ -0,0 +1,677 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_pvxlanmgr.c
+ *	NSS to HLOS Pvxlan manager
+ */
+#include "nss_pvxlanmgr_priv.h"
+
+/*
+ * nss_pvxlanmgr_stats_update()
+ *	Update the netdev stats
+ */
+static void nss_pvxlanmgr_stats_update(void *app_data, struct nss_pvxlan_msg *msg)
+{
+	struct net_device *dev = (struct net_device *)app_data;
+	struct nss_pvxlanmgr_priv *priv;
+	struct nss_pvxlan_stats_msg *stats;
+	struct rtnl_link_stats64 *netdev_stats;
+	struct nss_cmn_msg *ncm;
+	uint32_t i, if_num;
+	uint64_t dropped = 0;
+
+	ncm = (struct nss_cmn_msg *)msg;
+	if_num = ncm->interface;
+
+	stats = &msg->msg.stats;
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+	netdev_stats = &priv->stats;
+
+	/*
+	 * Only look at the tx_packets/tx_bytes for both host_inner/outer interfaces.
+	 * rx_bytes/rx_packets are increased when the packet is received by the node.
+	 * Therefore, it includes both transmitted/dropped packets. tx_bytes/tx_packets
+	 * reflect successfully transmitted packets.
+	 */
+	if (if_num == priv->if_num_host_inner) {
+		netdev_stats->tx_packets += stats->node_stats.tx_packets;
+		for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+			dropped += stats->node_stats.rx_dropped[i];
+		}
+		dropped += stats->mac_db_lookup_failed;
+		dropped += stats->udp_encap_lookup_failed;
+		netdev_stats->tx_bytes += stats->node_stats.tx_bytes;
+		dropped += stats->dropped_hroom;
+		dropped += stats->dropped_ver_mis;
+		dropped += stats->dropped_zero_sized_packet;
+		dropped += stats->dropped_next_node_queue_full;
+		netdev_stats->tx_dropped += dropped;
+		dev_put(dev);
+		return;
+	}
+
+	netdev_stats->rx_packets += stats->node_stats.tx_packets;
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		dropped += stats->node_stats.rx_dropped[i];
+	}
+	dropped += stats->dropped_malformed;
+	dropped += stats->dropped_next_node_queue_full;
+	dropped += stats->dropped_pbuf_alloc_failed;
+	dropped += stats->dropped_linear_failed;
+
+	netdev_stats->rx_bytes += stats->node_stats.tx_bytes;
+	netdev_stats->rx_dropped += dropped;
+	dev_put(dev);
+}
+
+/*
+ * nss_pvxlanmgr_start_xmit()
+ *	Transmit's skb to NSS FW over PVxLAN if_num.
+ *
+ * Please make sure to leave headroom of NSS_PVXLAN_HEADROOM with every
+ * packet so that NSS can encap eth,vlan,ip,udp,pvxlan headers.
+ * Also, skb->len must include size of metaheader. Essentially skb->len is
+ * size of PVxLAN Payload and metaheader.
+ */
+static netdev_tx_t nss_pvxlanmgr_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct net_device_stats *stats = &dev->stats;
+	struct nss_pvxlanmgr_priv *priv;
+	uint32_t if_num_host_inner;
+	nss_tx_status_t status;
+	int32_t extra_head = skb_headroom(skb) - dev->needed_headroom;
+
+	priv = netdev_priv(dev);
+
+	if (unlikely(extra_head < 0)) {
+		nss_pvxlanmgr_warn("%px: skb ( %px ) does not have enough headroom\n", dev, skb);
+		kfree_skb(skb);
+		stats->tx_dropped++;
+		return NETDEV_TX_OK;
+	}
+
+	if_num_host_inner = priv->if_num_host_inner;
+	if (unlikely(if_num_host_inner == 0)) {
+		nss_pvxlanmgr_warn("%px: (PVXLAN packet) if_num in the tunnel not set pre->if_num_host_inner %d\n", dev,
+				priv->if_num_host_inner);
+		kfree_skb(skb);
+		stats->tx_dropped++;
+		return NETDEV_TX_OK;
+	}
+
+	status = nss_pvxlan_tx_buf(priv->pvxlan_ctx, skb, if_num_host_inner);
+	if (unlikely(status != NSS_TX_SUCCESS)) {
+		if (status == NSS_TX_FAILURE_QUEUE) {
+			nss_pvxlanmgr_warn("%px: netdev :%px queue is full", dev, dev);
+			if (!netif_queue_stopped(dev)) {
+				netif_stop_queue(dev);
+			}
+			nss_pvxlanmgr_warn("%px: (PVxLAN packet) Failed to xmit the packet because of the tx failure : %d\n", dev, status);
+			return NETDEV_TX_BUSY;
+		}
+
+		nss_pvxlanmgr_warn("%px: (PVxLAN packet) Failed to xmit the packet because of non-tx failure reason : %d\n", dev, status);
+		kfree_skb(skb);
+		stats->tx_dropped++;
+	}
+
+	return NETDEV_TX_OK;
+}
+
+/*
+ * nss_pvxlanmgr_receive_pkt()
+ *	Receives a pkt from NSS
+ */
+static void nss_pvxlanmgr_receive_pkt(struct net_device *dev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	/*
+	 * SKB NETIF START
+	 */
+	dev_hold(dev);
+	skb->dev = dev;
+	skb->pkt_type = PACKET_OTHERHOST;
+	skb->skb_iif = dev->ifindex;
+	skb_reset_mac_header(skb);
+	skb_reset_network_header(skb);
+	skb_reset_transport_header(skb);
+	netif_receive_skb(skb);
+
+	/*
+	 * SKB NETIF END
+	 */
+	dev_put(dev);
+
+}
+
+/*
+ * nss_pvxlanmgr_get_tunnel_stats()
+ *	Netdev get stats function to get tunnel stats
+ */
+static struct rtnl_link_stats64 *nss_pvxlanmgr_get_tunnel_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	struct nss_pvxlanmgr_priv *priv;
+
+	if (!stats) {
+		nss_pvxlanmgr_warn("%px: invalid rtnl structure\n", dev);
+		return stats;
+	}
+
+	dev_hold(dev);
+
+	/*
+	 * Netdev seems to be incrementing rx_dropped because we don't give IP header.
+	 * So reset it as it's of no use for us.
+	 */
+	atomic_long_set(&dev->rx_dropped, 0);
+	priv = netdev_priv(dev);
+	memset(stats, 0, sizeof(struct rtnl_link_stats64));
+	memcpy(stats, &priv->stats, sizeof(struct rtnl_link_stats64));
+	dev_put(dev);
+
+	return stats;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0))
+/*
+ * nss_pvxlanmgr_dev_tunnel_stats()
+ *	Netdev ops function to retrieve stats for kernel version < 4.6
+ */
+static struct rtnl_link_stats64 *nss_pvxlanmgr_dev_tunnel_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	return nss_pvxlanmgr_get_tunnel_stats(dev, stats);
+}
+#else
+/*
+ * nss_pvxlanmgr_dev_tunnel_stats()
+ *	Netdev ops function to retrieve stats for kernel version > 4.6
+ */
+static void nss_pvxlanmgr_dev_tunnel_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	nss_pvxlanmgr_get_tunnel_stats(dev, stats);
+}
+#endif
+
+/*
+ * nss_pvxlanmgr_unregister_with_nss()
+ *	Internal function to unregister with NSS FW
+ */
+static void nss_pvxlanmgr_unregister_with_nss(uint32_t if_num)
+{
+	nss_pvxlanmgr_trace("%d: unregister with NSS FW\n", if_num);
+	nss_pvxlan_unregister(if_num);
+}
+
+/*
+ * nss_pvxlanmgr_register_with_nss()
+ *	Internal function to register with NSS FW.
+ */
+static nss_pvxlanmgr_status_t nss_pvxlanmgr_register_with_nss(uint32_t if_num, struct net_device *dev)
+{
+	struct nss_ctx_instance *ctx;
+
+	/*
+	 * features denote the skb_types supported
+	 */
+	uint32_t features = 0;
+
+	ctx = nss_pvxlan_register(if_num, nss_pvxlanmgr_receive_pkt, nss_pvxlanmgr_stats_update, dev, features);
+	if (!ctx) {
+		nss_pvxlanmgr_warn("%px: %d: nss_pvxlanmgr_data_register failed\n", dev, if_num);
+		return NSS_PVXLANMGR_FAILURE;
+	}
+	return NSS_PVXLANMGR_SUCCESS;
+}
+
+/*
+ * nss_pvxlanmgr_open()
+ *	Netdev's open call.
+ */
+static int nss_pvxlanmgr_open(struct net_device *dev)
+{
+	netif_start_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_pvxlanmgr_close()
+ *	Netdev's close call.
+ */
+static int nss_pvxlanmgr_close(struct net_device *dev)
+{
+	netif_stop_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_pvxlanmgr_decongestion_callback()
+ *	Wakeup netif queue if we were stopped by start_xmit
+ */
+static void nss_pvxlanmgr_decongestion_callback(void *arg)
+{
+	struct net_device *dev = arg;
+
+	/*
+	 * TODO: Add a check whether tunnel is disabled or not before waking it up.
+	 */
+	if (netif_queue_stopped(dev)) {
+		netif_wake_queue(dev);
+	}
+}
+
+/*
+ * nss_pvxlanmgr_netdev_ops
+ *	Netdev operations.
+ */
+static const struct net_device_ops nss_pvxlanmgr_netdev_ops = {
+	.ndo_open		= nss_pvxlanmgr_open,
+	.ndo_stop		= nss_pvxlanmgr_close,
+	.ndo_start_xmit		= nss_pvxlanmgr_start_xmit,
+	.ndo_set_mac_address	= eth_mac_addr,
+	.ndo_get_stats64	= nss_pvxlanmgr_dev_tunnel_stats,
+};
+
+/*
+ * nss_pvxlanmgr_dummy_netdev_setup()
+ *	Netdev setup function.
+ */
+static void nss_pvxlanmgr_dummy_netdev_setup(struct net_device *dev)
+{
+	dev->addr_len = ETH_ALEN;
+	dev->mtu = ETH_DATA_LEN;
+	dev->needed_headroom = NSS_PVXLAN_HEADROOM;
+	dev->type = ARPHRD_VOID;
+	dev->ethtool_ops = NULL;
+	dev->header_ops = NULL;
+	dev->netdev_ops = &nss_pvxlanmgr_netdev_ops;
+
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 11, 8))
+	dev->destructor = NULL;
+#else
+	dev->priv_destructor = NULL;
+#endif
+
+	memcpy(dev->dev_addr, "\x00\x00\x00\x00\x00\x00", dev->addr_len);
+	memset(dev->broadcast, 0xff, dev->addr_len);
+	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
+}
+
+/*
+ * nss_pvxlanmgr_netdev_down()
+ *	NSS Pvxlan Tunnel device i/f up handler
+ */
+static int nss_pvxlanmgr_netdev_down(struct net_device *netdev)
+{
+	nss_pvxlanmgr_netdev_disable(netdev);
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_pvxlanmgr_netdev_up()
+ *	NSS PVxLAN Tunnel device i/f up handler
+ */
+static int nss_pvxlanmgr_netdev_up(struct net_device *netdev)
+{
+	nss_pvxlanmgr_netdev_enable(netdev);
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_pvxlanmgr_netdev_event()
+ *	Netdevice notifier for NSS PVxLAN manager module
+ */
+static int nss_pvxlanmgr_netdev_event(struct notifier_block  *nb, unsigned long event, void  *dev)
+{
+	struct net_device *netdev = (struct net_device *)dev;
+
+	if (strstr(netdev->name, NSS_PVXLANMGR_NETDEV_NAME) == NULL) {
+		return NOTIFY_DONE;
+	}
+
+	switch (event) {
+	case NETDEV_UP:
+		nss_pvxlanmgr_trace("%px: NETDEV_UP: event %lu name %s\n", netdev, event, netdev->name);
+		return nss_pvxlanmgr_netdev_up(netdev);
+
+	case NETDEV_DOWN:
+		nss_pvxlanmgr_trace("%px: NETDEV_DOWN: event %lu name %s\n", netdev, event, netdev->name);
+		return nss_pvxlanmgr_netdev_down(netdev);
+
+	default:
+		nss_pvxlanmgr_trace("%px: Unhandled notifier event %lu name %s\n", netdev, event, netdev->name);
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * Linux Net device Notifier
+ */
+static struct notifier_block nss_pvxlanmgr_netdev_notifier = {
+	.notifier_call = nss_pvxlanmgr_netdev_event,
+};
+
+/*
+ * nss_pvxlanmgr_get_if_num_outer()
+ *	Get the if_num outer for the netdevice.
+ */
+uint32_t nss_pvxlanmgr_get_if_num_outer(struct net_device *dev)
+{
+	struct nss_pvxlanmgr_priv *priv;
+	priv = netdev_priv(dev);
+
+	return priv->if_num_outer;
+}
+EXPORT_SYMBOL(nss_pvxlanmgr_get_if_num_outer);
+
+/*
+ * nss_pvxlanmgr_get_if_num_host_inner()
+ *	Get the host inner interface number for the netdevice.
+ */
+uint32_t nss_pvxlanmgr_get_if_num_host_inner(struct net_device *dev)
+{
+	struct nss_pvxlanmgr_priv *priv;
+	priv = netdev_priv(dev);
+
+	return priv->if_num_host_inner;
+}
+EXPORT_SYMBOL(nss_pvxlanmgr_get_if_num_host_inner);
+
+/*
+ * nss_pvxlanmgr_netdev_disable()
+ *	API for disabling a data tunnel
+ */
+nss_pvxlanmgr_status_t nss_pvxlanmgr_netdev_disable(struct net_device *dev)
+{
+	struct nss_pvxlanmgr_priv *priv;
+	nss_tx_status_t ret;
+
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+	nss_pvxlanmgr_info("%px: tunnel disable is being called\n", dev);
+	ret = nss_pvxlanmgr_tunnel_tx_msg_disable(priv->pvxlan_ctx, priv->if_num_host_inner);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: Tunnel disable failed: %d\n", dev, ret);
+		dev_put(dev);
+		return ret;
+	}
+
+	ret = nss_pvxlanmgr_tunnel_tx_msg_disable(priv->pvxlan_ctx, priv->if_num_outer);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: Tunnel disable failed: %d\n", dev, ret);
+		nss_pvxlanmgr_tunnel_tx_msg_enable(priv->pvxlan_ctx, priv->if_num_host_inner, priv->if_num_outer);
+		dev_put(dev);
+		return ret;
+	}
+
+	dev_put(dev);
+	return ret;
+}
+EXPORT_SYMBOL(nss_pvxlanmgr_netdev_disable);
+
+/*
+ * nss_pvxlanmgr_netdev_enable()
+ *	API for enabling a data tunnel
+ */
+nss_pvxlanmgr_status_t nss_pvxlanmgr_netdev_enable(struct net_device *dev)
+{
+	struct nss_pvxlanmgr_priv *priv;
+	nss_tx_status_t ret;
+
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+	nss_pvxlanmgr_info("%px: tunnel enable is being called\n", dev);
+	ret = nss_pvxlanmgr_tunnel_tx_msg_enable(priv->pvxlan_ctx, priv->if_num_host_inner, priv->if_num_outer);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: Tunnel enable failed: %d\n", dev, ret);
+		dev_put(dev);
+		return ret;
+	}
+
+	ret = nss_pvxlanmgr_tunnel_tx_msg_enable(priv->pvxlan_ctx, priv->if_num_outer, priv->if_num_host_inner);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: Tunnel enable failed: %d\n", dev, ret);
+		nss_pvxlanmgr_tunnel_tx_msg_disable(priv->pvxlan_ctx, priv->if_num_host_inner);
+		dev_put(dev);
+		return ret;
+	}
+
+	dev_put(dev);
+	return ret;
+}
+EXPORT_SYMBOL(nss_pvxlanmgr_netdev_enable);
+
+/*
+ * nss_pvxlanmgr_netdev_destroy()
+ *	API for destroying a netdevice.
+ *
+ * The PVxLAN tunnel must be destroyed first before netdevice.
+ * Even though unregistrations fail during this process, we can't stop and return.
+ * That will cause a resource to never be freed. Therefore, we print warning if any
+ * of the unregistration fails but continue to free the resources.
+ */
+nss_pvxlanmgr_status_t nss_pvxlanmgr_netdev_destroy(struct net_device *dev)
+{
+	struct nss_pvxlanmgr_priv *priv;
+	uint32_t if_num_host_inner, if_num_outer, i;
+	nss_tx_status_t nss_status;
+	struct nss_pvxlanmgr_tunnel *t;
+
+	priv = netdev_priv(dev);
+	if_num_host_inner = priv->if_num_host_inner;
+	if_num_outer = priv->if_num_outer;
+
+	if (nss_cmn_unregister_queue_decongestion(priv->pvxlan_ctx, nss_pvxlanmgr_decongestion_callback) != NSS_CB_UNREGISTER_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: failed to unregister decongestion callback\n", dev);
+	}
+
+	/*
+	 * Delete all tunnels associated with this net_device.
+	 */
+	for (i = 0; i < NSS_PVXLANMGR_MAX_TUNNELS; i++) {
+		t = nss_pvxlanmgr_tunnel_get(dev, i);
+		if (t) {
+			nss_pvxlanmgr_warn("%px: tunnel %d: exist during the destruction\n", dev, i);
+			nss_pvxlanmgr_tunnel_destroy(dev, i);
+		}
+	}
+
+	/*
+	 * Deallocate dynamic interface
+	 */
+	nss_pvxlanmgr_unregister_with_nss(if_num_host_inner);
+	nss_status = nss_dynamic_interface_dealloc_node(if_num_host_inner, NSS_DYNAMIC_INTERFACE_TYPE_PVXLAN_HOST_INNER);
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: Dealloc of dynamic interface failed: %d\n",
+			dev, if_num_host_inner);
+	}
+
+	/*
+	 * Deallocate dynamic interface
+	 */
+	nss_pvxlanmgr_unregister_with_nss(if_num_outer);
+	nss_status = nss_dynamic_interface_dealloc_node(if_num_outer, NSS_DYNAMIC_INTERFACE_TYPE_PVXLAN_OUTER);
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: Dealloc of dynamic interface failed for tunnel: %d\n",
+			dev, if_num_outer);
+	}
+
+	unregister_netdev(dev);
+	priv = netdev_priv(dev);
+
+	kfree(priv->tunnel);
+	free_netdev(dev);
+	return NSS_PVXLANMGR_SUCCESS;
+}
+EXPORT_SYMBOL(nss_pvxlanmgr_netdev_destroy);
+
+/*
+ * nss_pvxlanmgr_netdev_create()
+ *	API to create a Pvxlan netdev
+ */
+struct net_device *nss_pvxlanmgr_netdev_create()
+{
+	struct nss_pvxlanmgr_priv *priv;
+	struct net_device *dev;
+	int32_t pvxlan_if_num_host_inner, pvxlan_if_num_outer;
+	int err;
+
+	dev = alloc_netdev(sizeof(struct nss_pvxlanmgr_priv),
+					"nsspvxlan%d", NET_NAME_ENUM, nss_pvxlanmgr_dummy_netdev_setup);
+	if (!dev) {
+		nss_pvxlanmgr_warn("Error allocating netdev\n");
+		return NULL;
+	}
+
+	priv = netdev_priv(dev);
+	priv->pvxlan_ctx = nss_pvxlan_get_ctx();
+	if (!priv->pvxlan_ctx) {
+		nss_pvxlanmgr_warn("%px: failed to find pvxlan context\n", dev);
+		goto fail1;
+	}
+
+	priv->ipv4_ctx = nss_ipv4_get_mgr();
+	if (!priv->ipv4_ctx) {
+		nss_pvxlanmgr_warn("%px: failed to find IPv4 context\n", dev);
+		goto fail1;
+	}
+
+	priv->ipv6_ctx = nss_ipv6_get_mgr();
+	if (!priv->ipv6_ctx) {
+		nss_pvxlanmgr_warn("%px: failed to find IPv6 context\n", dev);
+		goto fail1;
+	}
+
+	priv->tunnel = kzalloc(sizeof(struct nss_pvxlanmgr_tunnel) * NSS_PVXLANMGR_MAX_TUNNELS, GFP_ATOMIC);
+	if (!priv->tunnel) {
+		nss_pvxlanmgr_warn("%px: failed to allocate tunnel memory\n", dev);
+		goto fail1;
+	}
+
+	if (nss_cmn_register_queue_decongestion(priv->pvxlan_ctx, nss_pvxlanmgr_decongestion_callback, dev) != NSS_CB_REGISTER_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: failed to register decongestion callback\n", dev);
+		goto fail2;
+	}
+
+	pvxlan_if_num_host_inner = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_PVXLAN_HOST_INNER);
+	if (pvxlan_if_num_host_inner < 0) {
+		nss_pvxlanmgr_warn("%px: di returned error : %d\n", dev, pvxlan_if_num_host_inner);
+		goto fail3;
+	}
+
+	if (nss_pvxlanmgr_register_with_nss(pvxlan_if_num_host_inner, dev) != NSS_PVXLANMGR_SUCCESS) {
+		nss_pvxlanmgr_warn("%d: NSS PVXLAN register with NSS failed", pvxlan_if_num_host_inner);
+		goto fail4;
+	}
+
+	pvxlan_if_num_outer = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_PVXLAN_OUTER);
+	if (pvxlan_if_num_outer < 0) {
+		nss_pvxlanmgr_warn("%px: di returned error : %d\n", dev, pvxlan_if_num_outer);
+		goto fail5;
+	}
+
+	if (nss_pvxlanmgr_register_with_nss(pvxlan_if_num_outer, dev) != NSS_PVXLANMGR_SUCCESS) {
+		nss_pvxlanmgr_warn("%d: NSS PVXLAN register with NSS failed", pvxlan_if_num_outer);
+		goto fail6;
+	}
+
+	err = register_netdev(dev);
+	if (err) {
+		nss_pvxlanmgr_warn("register_netdev() fail with error :%d\n", err);
+		goto fail7;
+	}
+
+	priv->if_num_host_inner = pvxlan_if_num_host_inner;
+	priv->if_num_outer = pvxlan_if_num_outer;
+
+	return dev;
+
+fail7:
+	nss_pvxlanmgr_unregister_with_nss(pvxlan_if_num_outer);
+fail6:
+	nss_dynamic_interface_dealloc_node(pvxlan_if_num_outer, NSS_DYNAMIC_INTERFACE_TYPE_PVXLAN_OUTER);
+fail5:
+	nss_pvxlanmgr_unregister_with_nss(pvxlan_if_num_host_inner);
+fail4:
+	nss_dynamic_interface_dealloc_node(pvxlan_if_num_host_inner, NSS_DYNAMIC_INTERFACE_TYPE_PVXLAN_HOST_INNER);
+fail3:
+	nss_cmn_unregister_queue_decongestion(priv->pvxlan_ctx, nss_pvxlanmgr_decongestion_callback);
+fail2:
+	kfree(priv->tunnel);
+fail1:
+	free_netdev(dev);
+	return NULL;
+}
+EXPORT_SYMBOL(nss_pvxlanmgr_netdev_create);
+
+/*
+ * nss_pvxlanmgr_exit_module()
+ *	Tunnel Pvxlan module exit function
+ */
+void __exit nss_pvxlanmgr_exit_module(void)
+{
+	int ret;
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return;
+	}
+#endif
+
+	ret = unregister_netdevice_notifier(&nss_pvxlanmgr_netdev_notifier);
+	if (!ret) {
+		nss_pvxlanmgr_warn("failed to unregister netdevice notifier: error %d\n", ret);
+	}
+
+	nss_pvxlanmgr_info("module unloaded\n");
+}
+
+/*
+ * nss_pvxlanmgr_init_module()
+ *	Tunnel Pvxlan module init function
+ */
+int __init nss_pvxlanmgr_init_module(void)
+{
+	int ret;
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+
+	nss_pvxlanmgr_info("module %s loaded\n",
+			   NSS_CLIENT_BUILD_ID);
+
+	ret = register_netdevice_notifier(&nss_pvxlanmgr_netdev_notifier);
+	if (!ret) {
+		nss_pvxlanmgr_warn("failed to register netdevice notifier: error %d/n", ret);
+	}
+
+	return ret;
+}
+
+module_init(nss_pvxlanmgr_init_module);
+module_exit(nss_pvxlanmgr_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS Pvxlan manager");
diff --git a/qca-nss-clients/pvxlanmgr/nss_pvxlanmgr_priv.h b/qca-nss-clients/pvxlanmgr/nss_pvxlanmgr_priv.h
new file mode 100644
index 0000000..7c1fb79
--- /dev/null
+++ b/qca-nss-clients/pvxlanmgr/nss_pvxlanmgr_priv.h
@@ -0,0 +1,105 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_pvxlanmgr_priv.h
+ *	Pvxlan manager private defines
+ */
+#include <linux/types.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/version.h>
+#include <nss_api_if.h>
+#include <linux/in.h>
+#include <linux/etherdevice.h>
+#include <nss_cmn.h>
+#include <nss_pvxlan.h>
+#include <nss_pvxlanmgr.h>
+
+#define NSS_PVXLANMGR_NETDEV_NAME "nsspvxlan"
+
+#if (NSS_PVXLANMGR_DEBUG_LEVEL < 1)
+#define nss_pvxlanmgr_assert(fmt, args...)
+#else
+#define nss_pvxlanmgr_assert(c) if (!(c)) { BUG_ON(!(c)); }
+#endif /* NSS_PVXLANMGR_DEBUG_LEVEL */
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_pvxlanmgr_warn(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_pvxlanmgr_info(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_pvxlanmgr_trace(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#else /* CONFIG_DYNAMIC_DEBUG */
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_PVXLANMGR_DEBUG_LEVEL < 2)
+#define nss_pvxlanmgr_warn(s, ...)
+#else
+#define nss_pvxlanmgr_warn(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_PVXLANMGR_DEBUG_LEVEL < 3)
+#define nss_pvxlanmgr_info(s, ...)
+#else
+#define nss_pvxlanmgr_info(s, ...)   pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_PVXLANMGR_DEBUG_LEVEL < 4)
+#define nss_pvxlanmgr_trace(s, ...)
+#else
+#define nss_pvxlanmgr_trace(s, ...)  pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+/*
+ * Mapping table from tunnel-id to rule.
+ */
+struct nss_pvxlanmgr_tunnel {
+	uint32_t tunnel_state;			/* Tunnel state. */
+	union {
+		struct nss_ipv4_rule_create_msg v4;	/* IPv4 rule structure. */
+		struct nss_ipv6_rule_create_msg v6;	/* IPv6 rule struture. */
+	} ip_rule;
+	struct nss_pvxlan_rule_msg pvxlan_rule;	/* Copy of PVXLAN rule. */
+};
+
+/*
+ * Private structure to store information needed by a nss_pvxlan net_device
+ */
+struct nss_pvxlanmgr_priv {
+	struct nss_ctx_instance *pvxlan_ctx;	/* Pointer to NSS PVxLAN context. */
+	struct nss_ctx_instance *ipv4_ctx;	/* Pointer to NSS IPv4 context. */
+	struct nss_ctx_instance *ipv6_ctx;	/* Pointer to NSS IPv6 context. */
+	struct nss_pvxlanmgr_tunnel *tunnel;	/* Pointer to tunnel data. */
+	struct nss_pvxlanmgr_response *resp;	/* Response housekeeping. */
+	struct rtnl_link_stats64 stats;		/* NetDev stats. */
+	uint32_t if_num_host_inner;		/* Pvxlan inner interface number in NSS. */
+	uint32_t if_num_outer;			/* Pvxlan outer interface number in NSS. */
+};
+
+/*
+ * Returns tunnel structure pointer from tunnel_id.
+ */
+struct nss_pvxlanmgr_tunnel *nss_pvxlanmgr_tunnel_get(struct net_device *dev, uint32_t tunnel_id);
+
+nss_tx_status_t nss_pvxlanmgr_tunnel_tx_msg_disable(struct nss_ctx_instance *ctx, uint32_t if_num);
+
+nss_tx_status_t nss_pvxlanmgr_tunnel_tx_msg_enable(struct nss_ctx_instance *ctx,
+						uint32_t if_num, uint32_t sibling_if_num);
diff --git a/qca-nss-clients/pvxlanmgr/nss_pvxlanmgr_tunnel.c b/qca-nss-clients/pvxlanmgr/nss_pvxlanmgr_tunnel.c
new file mode 100644
index 0000000..07b64c1
--- /dev/null
+++ b/qca-nss-clients/pvxlanmgr/nss_pvxlanmgr_tunnel.c
@@ -0,0 +1,620 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include "nss_pvxlanmgr_priv.h"
+
+/*
+ * nss_pvxlanmgr_tunnel_tx_msg()
+ *	Transmit PVXLAN tunnel operation messages.
+ */
+static nss_tx_status_t nss_pvxlanmgr_tunnel_tx_msg(struct nss_ctx_instance *ctx, struct nss_pvxlan_msg * msg,
+		uint32_t if_num, nss_pvxlan_msg_type_t cmd, uint32_t len)
+{
+
+	/*
+	 * Send PVXLAN data tunnel command to NSS
+	 */
+	nss_pvxlan_msg_init(msg, if_num, cmd, len, NULL, NULL);
+	return nss_pvxlan_tx_msg_sync(ctx, msg);
+}
+
+/*
+ * nss_pvxlanmgr_tunnel_tx_msg_mac_del()
+ *	PvxLAN tunnel transmit mac delete messages.
+ */
+static inline nss_pvxlanmgr_status_t nss_pvxlanmgr_tunnel_tx_msg_mac_del(struct net_device *dev, uint32_t tunnel_id,
+						uint8_t *mac_addr)
+{
+	struct nss_pvxlanmgr_priv *priv;
+	struct nss_pvxlan_msg pvxlanmsg;
+	struct nss_pvxlan_mac_msg *ncfrm;
+	struct nss_pvxlanmgr_tunnel *t;
+	nss_tx_status_t status;
+
+	t = nss_pvxlanmgr_tunnel_get(dev, tunnel_id);
+	if (!t) {
+		nss_pvxlanmgr_warn("%px: can't find tunnel: %d\n", dev, tunnel_id);
+		return NSS_PVXLANMGR_FAILURE_BAD_PARAM;
+	}
+
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+
+	memset(&pvxlanmsg, 0, sizeof(struct nss_pvxlan_msg));
+
+	/*
+	 * Set MAC rule message
+	 */
+	ncfrm = &pvxlanmsg.msg.mac_del;
+	ncfrm->tunnel_id = tunnel_id;
+	memcpy(ncfrm->mac_addr, mac_addr, ETH_ALEN);
+
+	status = nss_pvxlanmgr_tunnel_tx_msg(priv->pvxlan_ctx, &pvxlanmsg, priv->if_num_host_inner, NSS_PVXLAN_MSG_TYPE_MAC_DEL, sizeof(struct nss_pvxlan_mac_msg));
+	if (status != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: ctx: MAC delete failed %d\n", dev, status);
+	}
+
+	dev_put(dev);
+	return status;
+}
+
+/*
+ * nss_pvxlanmgr_tunnel_tx_msg_mac_add()
+ *	PvxLAN tunnel transmit mac add messages.
+ */
+static inline nss_pvxlanmgr_status_t nss_pvxlanmgr_tunnel_tx_msg_mac_add(struct net_device *dev, uint32_t tunnel_id,
+						uint8_t *mac_addr, struct nss_pvxlanmgr_vxlan_hdr *pvxch)
+{
+	struct nss_pvxlanmgr_priv *priv;
+	struct nss_pvxlan_msg pvxlanmsg;
+	struct nss_pvxlan_mac_msg *ncfrm;
+	struct nss_pvxlanmgr_tunnel *t;
+	nss_tx_status_t status;
+
+	t = nss_pvxlanmgr_tunnel_get(dev, tunnel_id);
+	if (!t) {
+		nss_pvxlanmgr_warn("%px: can't find tunnel: %d\n", dev, tunnel_id);
+		return NSS_PVXLANMGR_FAILURE_BAD_PARAM;
+	}
+
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+
+	memset(&pvxlanmsg, 0, sizeof(struct nss_pvxlan_msg));
+
+	/*
+	 * Set MAC rule message
+	 */
+	ncfrm = &pvxlanmsg.msg.mac_add;
+	ncfrm->flags = pvxch->flags;
+	ncfrm->vnet_id = pvxch->vnet_id;
+	ncfrm->policy_id = pvxch->gpid;
+	ncfrm->tunnel_id = tunnel_id;
+	memcpy(ncfrm->mac_addr, mac_addr, ETH_ALEN);
+
+	status = nss_pvxlanmgr_tunnel_tx_msg(priv->pvxlan_ctx, &pvxlanmsg, priv->if_num_host_inner, NSS_PVXLAN_MSG_TYPE_MAC_ADD, sizeof(struct nss_pvxlan_mac_msg));
+	if (status != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: ctx: MAC addition failed %d\n", dev, status);
+	}
+
+	dev_put(dev);
+	return status;
+}
+
+/*
+ * nss_pvxlanmgr_pvxlan_rule_destroy()
+ *	Internal function to destroy a PVxLAN rule
+ */
+static nss_pvxlanmgr_status_t nss_pvxlanmgr_tunnel_pvxlan_rule_destroy(struct nss_ctx_instance *ctx, uint32_t if_num,
+			 struct nss_pvxlan_rule_msg *msg)
+{
+	struct nss_pvxlan_msg pvxlanmsg;
+	nss_tx_status_t status;
+
+	nss_pvxlanmgr_info("%px: ctx: PVxLAN Rule src_port: 0x%d dest_port:0x%d\n", ctx,
+	    msg->encap.src_port, msg->encap.dest_port);
+
+	/*
+	 * Prepare the tunnel configuration parameter to send to NSS FW
+	 */
+	memset(&pvxlanmsg, 0, sizeof(struct nss_pvxlan_msg));
+	pvxlanmsg.msg.rule_uncfg = *msg;
+
+	/*
+	 * Send PVxLAN tunnel create command to NSS
+	 */
+	status = nss_pvxlanmgr_tunnel_tx_msg(ctx, &pvxlanmsg, if_num, NSS_PVXLAN_MSG_TYPE_TUNNEL_DESTROY_RULE, sizeof(struct nss_pvxlan_rule_msg));
+	if (status != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: ctx: create encap data tunnel error %d\n", ctx, status);
+		return status;
+	}
+
+	return NSS_PVXLANMGR_SUCCESS;
+}
+
+/*
+ * nss_pvxlanmgr_pvxlan_rule_create()
+ *	Internal function to create a PVxLAN rule
+ */
+static nss_pvxlanmgr_status_t nss_pvxlanmgr_tunnel_pvxlan_rule_create(struct nss_ctx_instance *ctx, uint32_t if_num,
+			 struct nss_pvxlan_rule_msg *msg)
+{
+	struct nss_pvxlan_msg pvxlanmsg;
+	nss_tx_status_t status;
+
+	nss_pvxlanmgr_info("%px: ctx: PVxLAN Rule src_port: 0x%d dest_port:0x%d\n", ctx,
+	    msg->encap.src_port, msg->encap.dest_port);
+
+	/*
+	 * Prepare the tunnel configuration parameter to send to NSS FW
+	 */
+	memset(&pvxlanmsg, 0, sizeof(struct nss_pvxlan_msg));
+	pvxlanmsg.msg.rule_cfg = *msg;
+
+	/*
+	 * Send PVxLAN tunnel create command to NSS
+	 */
+	status = nss_pvxlanmgr_tunnel_tx_msg(ctx, &pvxlanmsg, if_num, NSS_PVXLAN_MSG_TYPE_TUNNEL_CREATE_RULE, sizeof(struct nss_pvxlan_rule_msg));
+	if (status != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: ctx: create encap data tunnel error %d\n", ctx, status);
+		return status;
+	}
+
+	return NSS_PVXLANMGR_SUCCESS;
+}
+
+/*
+ * nss_pvxlanmgr_tunnel_destroy_ipv4_rule()
+ *	Destroy a given connection in the NSS
+ */
+static nss_tx_status_t nss_pvxlanmgr_tunnel_destroy_ipv4_rule(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_5tuple *ni5t)
+{
+	struct nss_ipv4_msg nim;
+	nss_tx_status_t status;
+
+	nss_pvxlanmgr_info("%px: ctx: Destroy IPv4: %pI4h :%u, %pI4h :%u, p: %d\n", nss_ctx,
+		&ni5t->flow_ip, ni5t->flow_ident, &ni5t->return_ip, ni5t->return_ident, ni5t->protocol);
+
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_DESTROY_RULE_MSG,
+			sizeof(struct nss_ipv4_rule_destroy_msg), NULL, NULL);
+
+	nim.msg.rule_destroy.tuple = *ni5t;
+	status = nss_ipv4_tx_sync(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: Destroy IPv4 message failed %d\n", nss_ctx, status);
+	}
+
+	return status;
+}
+
+/*
+ * nss_pvxlanmgr_tunnel_destroy_ipv6_rule()
+ *	Destroy a given connection in the NSS
+ */
+static nss_tx_status_t nss_pvxlanmgr_tunnel_destroy_ipv6_rule(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_5tuple *ni5t)
+{
+	struct nss_ipv6_msg nim;
+	nss_tx_status_t status;
+
+	nss_pvxlanmgr_info("%px: ctx: Destroy IPv6: %pI6:%u, %pI6:%u, p: %d\n", nss_ctx,
+		ni5t->flow_ip, ni5t->flow_ident, ni5t->return_ip, ni5t->return_ident, ni5t->protocol);
+
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_DESTROY_RULE_MSG,
+			sizeof(struct nss_ipv6_rule_destroy_msg), NULL, NULL);
+
+	nim.msg.rule_destroy.tuple = *ni5t;
+	status = nss_ipv6_tx_sync(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: Destroy IPv6 message failed %d\n", nss_ctx, status);
+	}
+	return status;
+}
+
+/*
+ * nss_pvxlanmgr_tunnel_create_ipv4_rule()
+ *	Create a given connection in the NSS
+ */
+static nss_tx_status_t nss_pvxlanmgr_tunnel_create_ipv4_rule(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_rule_create_msg *nircm)
+{
+	struct nss_ipv4_msg nim;
+	nss_tx_status_t status;
+
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_CREATE_RULE_MSG,
+			sizeof(struct nss_ipv4_rule_create_msg), NULL, NULL);
+
+	nim.msg.rule_create = *nircm;
+	status = nss_ipv4_tx_sync(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: Create IPv4 message failed %d\n", nss_ctx, status);
+	}
+
+	return status;
+}
+
+/*
+ * nss_pvxlanmgr_tunnel_create_ipv6_rule()
+ *	Create a given connection in the NSS
+ */
+static nss_tx_status_t nss_pvxlanmgr_tunnel_create_ipv6_rule(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_rule_create_msg *nircm)
+{
+	struct nss_ipv6_msg nim;
+	nss_tx_status_t status;
+
+	memset(&nim, 0, sizeof (struct nss_ipv6_msg));
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_CREATE_RULE_MSG,
+			sizeof(struct nss_ipv6_rule_create_msg), NULL, NULL);
+
+	nim.msg.rule_create = *nircm;
+	status = nss_ipv6_tx_sync(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: Create IPv6 message failed %d\n", nss_ctx, status);
+	}
+
+	return status;
+}
+
+/*
+ * nss_pvxlanmgr_tunnel_get()
+ *	Common function to verify tunnel_id and returns pointer to tunnel.
+ */
+struct nss_pvxlanmgr_tunnel *nss_pvxlanmgr_tunnel_get(struct net_device *dev, uint32_t tunnel_id)
+{
+	struct nss_pvxlanmgr_priv *priv;
+	struct nss_pvxlanmgr_tunnel *t;
+
+	if (!dev) {
+		nss_pvxlanmgr_warn("Invalid net_device\n");
+		return NULL;
+	}
+
+	if (tunnel_id >= NSS_PVXLANMGR_MAX_TUNNELS) {
+		nss_pvxlanmgr_warn("%px: tunnel_id: %d out of range (%d)\n", dev, tunnel_id, NSS_PVXLANMGR_MAX_TUNNELS);
+		return NULL;
+	}
+
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+	t = &priv->tunnel[tunnel_id];
+	if (!(t->tunnel_state & NSS_PVXLANMGR_TUNNEL_STATE_CONFIGURED)) {
+		dev_put(dev);
+		return NULL;
+	}
+
+	dev_put(dev);
+	return t;
+}
+
+/*
+ * nss_pvxlanmgr_tunnel_mac_remove()
+ *	Send a pvxlan remove mac message to NSS core.
+ */
+nss_pvxlanmgr_status_t nss_pvxlanmgr_tunnel_mac_remove(struct net_device *dev, uint32_t tunnel_id, uint8_t *mac_addr)
+{
+	return nss_pvxlanmgr_tunnel_tx_msg_mac_del(dev, tunnel_id, mac_addr);
+}
+EXPORT_SYMBOL(nss_pvxlanmgr_tunnel_mac_remove);
+
+/*
+ * nss_pvxlanmgr_tunnel_mac_add()
+ *	Send a pvxlan add mac message to NSS core.
+ */
+nss_pvxlanmgr_status_t nss_pvxlanmgr_tunnel_mac_add(struct net_device *dev, uint32_t tunnel_id, uint8_t *mac_addr, struct nss_pvxlanmgr_vxlan_hdr *pvxch)
+{
+	return nss_pvxlanmgr_tunnel_tx_msg_mac_add(dev, tunnel_id, mac_addr, pvxch);
+}
+EXPORT_SYMBOL(nss_pvxlanmgr_tunnel_mac_add);
+
+/*
+ * nss_pvxlanmgr_tunnel_tx_msg_disable()
+ *	PVxLAN tunnel transmit disable messages.
+ */
+nss_tx_status_t nss_pvxlanmgr_tunnel_tx_msg_disable(struct nss_ctx_instance *ctx, uint32_t if_num)
+{
+	struct nss_pvxlan_msg pvxlanmsg;
+	nss_tx_status_t status;
+
+	/*
+	 * Prepare the tunnel configuration parameter to send to NSS FW
+	 */
+	memset(&pvxlanmsg, 0, sizeof(struct nss_pvxlan_msg));
+
+	status = nss_pvxlanmgr_tunnel_tx_msg(ctx, &pvxlanmsg, if_num, NSS_PVXLAN_MSG_TYPE_TUNNEL_DISABLE, 0);
+	if (status != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: ctx: Tunnel disable error : %d\n", ctx, status);
+	}
+
+	return status;
+}
+
+/*
+ * nss_pvxlanmgr_tunnel_tx_msg_enable()
+ *	PVxLAN tunnel transmit enable messages.
+ */
+nss_tx_status_t nss_pvxlanmgr_tunnel_tx_msg_enable(struct nss_ctx_instance *ctx,
+					uint32_t if_num, uint32_t sibling_if_num)
+{
+	struct nss_pvxlan_msg pvxlanmsg;
+	nss_tx_status_t status;
+
+	/*
+	 * Prepare the tunnel configuration parameter to send to NSS FW
+	 */
+	memset(&pvxlanmsg, 0, sizeof(struct nss_pvxlan_msg));
+	pvxlanmsg.msg.enable.sibling_if_num = sibling_if_num;
+
+	status = nss_pvxlanmgr_tunnel_tx_msg(ctx, &pvxlanmsg, if_num, NSS_PVXLAN_MSG_TYPE_TUNNEL_ENABLE, sizeof(struct nss_pvxlan_tunnel_state_msg));
+
+	if (status != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: ctx: Tunnel enable error : %d\n", ctx, status);
+	}
+
+	return status;
+}
+
+/*
+ * nss_pvxlanmgr_tunnel_destroy()
+ *	API for destroying a tunnel. All mac rules associated with this tunnel must be removed first.
+ */
+nss_pvxlanmgr_status_t nss_pvxlanmgr_tunnel_destroy(struct net_device *dev, uint32_t tunnel_id)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_pvxlanmgr_priv *priv;
+	struct nss_pvxlanmgr_tunnel *t;
+	nss_tx_status_t nss_status = NSS_TX_SUCCESS;
+	uint32_t if_num_host_inner, if_num_outer;
+	struct nss_pvxlan_rule_msg *pvxlan_rule;
+	nss_pvxlanmgr_status_t status;
+
+	t = nss_pvxlanmgr_tunnel_get(dev, tunnel_id);
+	if (!t) {
+		nss_pvxlanmgr_warn("%px: tunnel %d: wrong argument for tunnel destroy\n", dev, tunnel_id);
+		return NSS_PVXLANMGR_FAILURE_BAD_PARAM;
+	}
+
+	if (!(t->tunnel_state & NSS_PVXLANMGR_TUNNEL_STATE_CONFIGURED)) {
+		nss_pvxlanmgr_warn("%px: tunnel %d is not configured yet\n", dev, tunnel_id);
+		return NSS_PVXLANMGR_FAILURE_TUNNEL_NOT_CREATED;
+	}
+
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+	if_num_host_inner = priv->if_num_host_inner;
+	if_num_outer = priv->if_num_outer;
+	nss_pvxlanmgr_info("%px: tunnel destroy is being called for tunnel %d and tunnel %d\n", dev, if_num_host_inner, if_num_outer);
+
+	pvxlan_rule = &t->pvxlan_rule;
+	status = nss_pvxlanmgr_tunnel_pvxlan_rule_destroy(priv->pvxlan_ctx, if_num_host_inner, pvxlan_rule);
+	if (status != NSS_PVXLANMGR_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: %d: PVXLAN rule destroy failed with status: %d\n", dev, if_num_host_inner, status);
+		dev_put(dev);
+		return NSS_PVXLANMGR_FAILURE_PVXLAN_RULE;
+	}
+
+	if (t->pvxlan_rule.flags & NSS_PVXLAN_TUNNEL_IPV4) {
+		nss_ctx = priv->ipv4_ctx;
+		nss_status = nss_pvxlanmgr_tunnel_destroy_ipv4_rule(nss_ctx, &t->ip_rule.v4.tuple);
+	} else {
+		nss_ctx = priv->ipv6_ctx;
+		nss_status = nss_pvxlanmgr_tunnel_destroy_ipv6_rule(nss_ctx, &t->ip_rule.v6.tuple);
+	}
+
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_tunnel_pvxlan_rule_create(priv->pvxlan_ctx, if_num_host_inner, pvxlan_rule);
+		nss_pvxlanmgr_warn("%px: Unconfigure IP rule failed for tunnel: %d\n",
+			dev, tunnel_id);
+		dev_put(dev);
+		return NSS_PVXLANMGR_FAILURE_IP_DESTROY_RULE;
+	}
+
+	t->tunnel_state &= ~NSS_PVXLANMGR_TUNNEL_STATE_CONFIGURED;
+
+	nss_pvxlanmgr_info("%px: Tunnel %d is completely destroyed\n", dev, tunnel_id);
+	dev_put(dev);
+	return NSS_PVXLANMGR_SUCCESS;
+}
+EXPORT_SYMBOL(nss_pvxlanmgr_tunnel_destroy);
+
+/*
+ * nss_pvxlanmgr_tunnel_ipv4_create()
+ *	Common handling for creating IPv4 tunnel
+ */
+nss_pvxlanmgr_status_t nss_pvxlanmgr_tunnel_ipv4_create(struct net_device *dev, uint32_t tunnel_id,
+							struct nss_ipv4_rule_create_msg *nircm, uint32_t pvxlan_src_port)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_pvxlanmgr_priv *priv;
+	struct nss_pvxlanmgr_tunnel *t;
+	struct nss_pvxlan_rule_msg pvxlan_rule;
+	nss_pvxlanmgr_status_t status = NSS_PVXLANMGR_SUCCESS;
+	uint32_t if_num_host_inner, if_num_outer;
+	uint16_t flags = 0;
+	nss_tx_status_t nss_status = NSS_TX_SUCCESS;
+
+	if (tunnel_id >= NSS_PVXLANMGR_MAX_TUNNELS) {
+		nss_pvxlanmgr_warn("%px: invalid tunnel_id: %d max: NSS_PVXLANMGR_MAX_TUNNELS\n", dev, tunnel_id);
+		return NSS_PVXLANMGR_FAILURE_BAD_PARAM;
+	}
+
+	if (!(nircm->tuple.protocol == IPPROTO_UDP)) {
+		nss_pvxlanmgr_warn("%px: tunnel %d: wrong argument for protocol: %u\n", dev, tunnel_id, nircm->tuple.protocol);
+		return NSS_PVXLANMGR_FAILURE_BAD_PARAM;
+	}
+
+	t = nss_pvxlanmgr_tunnel_get(dev, tunnel_id);
+	if (t) {
+		nss_pvxlanmgr_warn("%px: tunnel: %d already created\n", dev, tunnel_id);
+		return NSS_PVXLANMGR_FAILURE_TUNNEL_EXISTS;
+	}
+
+	/*
+	 * Copy over the IP rule information to PVxLAN rule for encap side.
+	 * This will avoid any confusions because IP rule direction is ingress from WAN and
+	 * PVxLAN encap rule direction is egress to the WAN port.
+	 * pvxlan_src port for encapsulation is provided separately.
+	 * So, use that one rather than the one in the IP rule.
+	 */
+	pvxlan_rule.encap.src_port = pvxlan_src_port;
+	pvxlan_rule.encap.src.ip.ipv4 = nircm->tuple.return_ip;
+
+	pvxlan_rule.encap.dest_port = nircm->tuple.flow_ident;
+	pvxlan_rule.encap.dest.ip.ipv4 = nircm->tuple.flow_ip;
+	pvxlan_rule.tunnel_id = tunnel_id;
+	pvxlan_rule.rps = -1;
+	flags |= NSS_PVXLAN_TUNNEL_IPV4;
+	flags |= NSS_PVXLAN_TUNNEL_UDP;
+	pvxlan_rule.flags = flags;
+
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+	if_num_host_inner = priv->if_num_host_inner;
+	if_num_outer = priv->if_num_outer;
+
+	status = nss_pvxlanmgr_tunnel_pvxlan_rule_create(priv->pvxlan_ctx, if_num_host_inner, &pvxlan_rule);
+	nss_pvxlanmgr_info("%px: dynamic interface if_num is :%d and pvxlan tunnel status:%d\n", dev, if_num_host_inner, status);
+	if (status != NSS_PVXLANMGR_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: %d: PVXLAN rule create failed with status: %d\n", dev, if_num_host_inner, status);
+		dev_put(dev);
+		return NSS_PVXLANMGR_FAILURE_PVXLAN_RULE;
+	}
+
+	nss_ctx = priv->ipv4_ctx;
+	nss_status = nss_pvxlanmgr_tunnel_create_ipv4_rule(nss_ctx, nircm);
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_tunnel_pvxlan_rule_destroy(priv->pvxlan_ctx, if_num_host_inner, &pvxlan_rule);
+		nss_pvxlanmgr_warn("%px: %d: IPv4 rule create failed with status: %d\n", dev, if_num_host_inner, nss_status);
+		dev_put(dev);
+		return NSS_PVXLANMGR_FAILURE_IP_RULE;
+	}
+
+	t = &priv->tunnel[tunnel_id];
+
+	nss_pvxlanmgr_info("%px: Pvxlan Tunnel create done tunnel_id:%d (%px) IPv4: %pI4h :%u, %pI4h :%u, p: %d\n", dev,
+			tunnel_id, t, &nircm->tuple.flow_ip, nircm->tuple.flow_ident, &nircm->tuple.return_ip,
+			nircm->tuple.return_ident, nircm->tuple.protocol);
+
+	memcpy(&t->ip_rule.v4, nircm, sizeof(struct nss_ipv4_rule_create_msg));
+	memcpy(&t->pvxlan_rule, &pvxlan_rule, sizeof(struct nss_pvxlan_rule_msg));
+
+	/*
+	 * Make it globally visible inside the netdev.
+	 */
+	t->tunnel_state |= NSS_PVXLANMGR_TUNNEL_STATE_CONFIGURED;
+
+	dev_put(dev);
+	return status;
+}
+EXPORT_SYMBOL(nss_pvxlanmgr_tunnel_ipv4_create);
+
+/*
+ * nss_pvxlanmgr_tunnel_ipv6_create()
+ *	Common handling for creating IPv6 tunnel
+ */
+nss_pvxlanmgr_status_t nss_pvxlanmgr_tunnel_ipv6_create(struct net_device *dev, uint32_t tunnel_id,
+							struct nss_ipv6_rule_create_msg *nircm, uint32_t pvxlan_src_port)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_pvxlanmgr_priv *priv;
+	struct nss_pvxlanmgr_tunnel *t;
+	struct nss_pvxlan_rule_msg pvxlan_rule;
+	nss_pvxlanmgr_status_t status = NSS_PVXLANMGR_SUCCESS;
+	uint32_t if_num_host_inner, if_num_outer;
+	uint16_t flags = 0;
+	nss_tx_status_t nss_status = NSS_TX_SUCCESS;
+
+	if (tunnel_id >= NSS_PVXLANMGR_MAX_TUNNELS) {
+		nss_pvxlanmgr_warn("%px: invalid tunnel_id: %d max: NSS_PVXLANMGR_MAX_TUNNELS\n", dev, tunnel_id);
+		return NSS_PVXLANMGR_FAILURE_BAD_PARAM;
+	}
+
+	if (!(nircm->tuple.protocol == IPPROTO_UDP ||
+		nircm->tuple.protocol == IPPROTO_UDPLITE)) {
+		nss_pvxlanmgr_warn("%px: tunnel %d: wrong argument for protocol %u\n", dev, tunnel_id, nircm->tuple.protocol);
+		return NSS_PVXLANMGR_FAILURE_BAD_PARAM;
+	}
+
+	t = nss_pvxlanmgr_tunnel_get(dev, tunnel_id);
+	if (t) {
+		nss_pvxlanmgr_warn("%px: tunnel: %d already created\n", dev, tunnel_id);
+		return NSS_PVXLANMGR_FAILURE_TUNNEL_EXISTS;
+	}
+
+	/*
+	 * Copy over the IP rule information to PVxLAN rule for encap side.
+	 * This will avoid any confusions because IP rule direction is ingress from WAN and
+	 * PVxLAN encap rule direction is egress to the WAN port.
+	 *
+	 * pvxlan_src port is provided separately. So, use that one rather than the one in the IP rule.
+	 */
+	pvxlan_rule.encap.src_port = pvxlan_src_port;
+	pvxlan_rule.encap.src.ip.ipv6[0] = nircm->tuple.return_ip[0];
+	pvxlan_rule.encap.src.ip.ipv6[1] = nircm->tuple.return_ip[1];
+	pvxlan_rule.encap.src.ip.ipv6[2] = nircm->tuple.return_ip[2];
+	pvxlan_rule.encap.src.ip.ipv6[3] = nircm->tuple.return_ip[3];
+
+	pvxlan_rule.encap.dest_port = nircm->tuple.flow_ident;
+	pvxlan_rule.encap.dest.ip.ipv6[0] = nircm->tuple.flow_ip[0];
+	pvxlan_rule.encap.dest.ip.ipv6[1] = nircm->tuple.flow_ip[1];
+	pvxlan_rule.encap.dest.ip.ipv6[2] = nircm->tuple.flow_ip[2];
+	pvxlan_rule.encap.dest.ip.ipv6[3] = nircm->tuple.flow_ip[3];
+	pvxlan_rule.tunnel_id = tunnel_id;
+	pvxlan_rule.rps = -1;
+	flags |= NSS_PVXLAN_TUNNEL_IPV6;
+
+	if (nircm->tuple.protocol == IPPROTO_UDP) {
+		flags |= NSS_PVXLAN_TUNNEL_UDP;
+	} else {
+		flags |= NSS_PVXLAN_TUNNEL_UDPLite;
+		flags |= NSS_PVXLAN_TUNNEL_ENCAP_UDPLITE_HDR_CSUM;
+	}
+	pvxlan_rule.flags = flags;
+
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+	if_num_host_inner = priv->if_num_host_inner;
+	if_num_outer = priv->if_num_outer;
+
+	status = nss_pvxlanmgr_tunnel_pvxlan_rule_create(priv->pvxlan_ctx, if_num_host_inner, &pvxlan_rule);
+	nss_pvxlanmgr_info("%px: dynamic interface if_num is :%d and pvxlan tunnel status:%d\n", dev, if_num_host_inner, status);
+	if (status != NSS_PVXLANMGR_SUCCESS) {
+		nss_pvxlanmgr_warn("%px: %d: PVXLAN rule create failed with status: %d\n", dev, if_num_host_inner, status);
+		dev_put(dev);
+		return NSS_PVXLANMGR_FAILURE_PVXLAN_RULE;
+	}
+
+	nss_ctx = priv->ipv6_ctx;
+	nss_status = nss_pvxlanmgr_tunnel_create_ipv6_rule(nss_ctx, nircm);
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_pvxlanmgr_tunnel_pvxlan_rule_destroy(priv->pvxlan_ctx, if_num_host_inner, &pvxlan_rule);
+		nss_pvxlanmgr_warn("%px: %d: IPv6 rule create failed with status: %d\n", dev, if_num_host_inner, nss_status);
+		dev_put(dev);
+		return NSS_PVXLANMGR_FAILURE_IP_RULE;
+	}
+
+	t = &priv->tunnel[tunnel_id];
+
+	nss_pvxlanmgr_info("%px: Pvxlan Tunnel create done tunnel_id:%d (%px)\n", dev, tunnel_id, t);
+
+	memcpy(&t->ip_rule.v6, nircm, sizeof(struct nss_ipv6_rule_create_msg));
+	memcpy(&t->pvxlan_rule, &pvxlan_rule, sizeof(struct nss_pvxlan_rule_msg));
+
+	/*
+	 * Make it globally visible inside the netdev.
+	 */
+	t->tunnel_state |= NSS_PVXLANMGR_TUNNEL_STATE_CONFIGURED;
+
+	dev_put(dev);
+	return status;
+}
+EXPORT_SYMBOL(nss_pvxlanmgr_tunnel_ipv6_create);
diff --git a/qca-nss-clients/tls/Makefile b/qca-nss-clients/tls/Makefile
new file mode 100644
index 0000000..53f9d60
--- /dev/null
+++ b/qca-nss-clients/tls/Makefile
@@ -0,0 +1,14 @@
+# Makefile for TLS manager
+
+ccflags-y += $(NSS_CCFLAGS) -I$(obj)/../../exports
+#ccflags-y += -DNSS_TLSMGR_DEBUG_DUMP
+ccflags-y += -DNSS_TLSMGR_DEBUG_LEVEL=3
+ccflags-y += -DNSS_TLSMGR_BUILD_ID=\"'Build_ID - $(shell date +'%m/%d/%y, %H:%M:%S') SoC=$(SoC)'\"
+ccflags-y += -Wall -Werror
+
+obj-m += qca-nss-tlsmgr.o
+qca-nss-tlsmgr-objs += nss_tlsmgr.o
+qca-nss-tlsmgr-objs += nss_tlsmgr_buf.o
+qca-nss-tlsmgr-objs += nss_tlsmgr_crypto.o
+qca-nss-tlsmgr-objs += nss_tlsmgr_ctx.o
+qca-nss-tlsmgr-objs += nss_tlsmgr_tun.o
diff --git a/qca-nss-clients/tls/nss_tlsmgr.c b/qca-nss-clients/tls/nss_tlsmgr.c
new file mode 100644
index 0000000..27ddd13
--- /dev/null
+++ b/qca-nss-clients/tls/nss_tlsmgr.c
@@ -0,0 +1,283 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+/*
+ * nss_tlsmgr.c
+ *	NSS TLS Manager
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/if_arp.h>
+#include <linux/atomic.h>
+#include <linux/debugfs.h>
+
+#include <nss_api_if.h>
+
+#include <nss_tls.h>
+#include "nss_tlsmgr_priv.h"
+
+/*
+ * Global TLS context
+ */
+struct nss_tlsmgr *tlsmgr_drv;
+
+/*
+ * nss_tlsmgr_add_node_stats()
+ *	Creates entries for node statistics
+ *
+ * Node statistics
+ */
+static const struct nss_tlsmgr_print tlsmgr_print_node_stats[] = {
+	{"\tfail_ctx_alloc", NSS_TLSMGR_PRINT_DWORD},
+	{"\tfail_ctx_free", NSS_TLSMGR_PRINT_DWORD},
+	{"\tfail_pbuf_stats", NSS_TLSMGR_PRINT_DWORD},
+};
+
+/*
+ * nss_tlsmgr_stats_size()
+ *	Calculate size of NODE stats
+ */
+static ssize_t nss_tlsmgr_stats_size(void)
+{
+	const struct nss_tlsmgr_print *prn = tlsmgr_print_node_stats;
+	ssize_t len = NSS_TLSMGR_PRINT_EXTRA;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(tlsmgr_print_node_stats); i++, prn++)
+		len += strlen(prn->str) + prn->var_size;
+
+	return len;
+}
+
+/*
+ * nss_tlsmgr_print()
+ *	Print context statistics
+ */
+static ssize_t nss_tlsmgr_print(char *buf)
+{
+	const struct nss_tlsmgr_print *prn = tlsmgr_print_node_stats;
+	ssize_t max_len = tlsmgr_drv->print_len;
+	uint32_t *stats_word = (uint32_t *)&tlsmgr_drv->stats;
+	ssize_t len;
+	int i;
+
+	/*
+	 * This expects a strict order as per the stats structure
+	 */
+	len = snprintf(buf, max_len, "---- NODE -----\n");
+	len += snprintf(buf + len, max_len - len, "stats: {\n");
+
+	for (i = 0; i < ARRAY_SIZE(tlsmgr_print_node_stats); i++, prn++)
+		len += snprintf(buf + len, max_len - len, "%s: %u\n", prn->str, *stats_word++);
+
+	len += snprintf(buf + len, max_len - len, "}\n");
+
+	return len;
+}
+
+/*
+ * nss_tlsmgr_read()
+ *	Read NODE info
+ */
+static ssize_t nss_tlsmgr_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	struct nss_tlsmgr_ctx *ctx = fp->private_data;
+	ssize_t print_len = tlsmgr_drv->stats_len;
+	ssize_t len = 0;
+	char *buf;
+
+	buf = vzalloc(print_len);
+	if (!buf) {
+		nss_tlsmgr_warn("%px: failed to allocate print buffer (req:%zd)", ctx, print_len);
+		return 0;
+	}
+
+	/*
+	 * Walk the context reference tree and retrieve stats
+	 */
+	len = nss_tlsmgr_print(buf);
+
+	len = simple_read_from_buffer(ubuf, sz, ppos, buf, len);
+	vfree(buf);
+
+	return len;
+}
+
+/*
+ * file operation structure instance
+ */
+const struct file_operations tlsmgr_file_ops = {
+	.open = simple_open,
+	.llseek = default_llseek,
+	.read = nss_tlsmgr_read,
+};
+
+/*
+ * nss_tlsmgr_node_config_done()
+ *	Check and set the configured flag if the TLS firmware package is successfully configured.
+ */
+static void nss_tlsmgr_node_config_done(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_tlsmgr *drv = app_data;
+
+	nss_tlsmgr_info("%px: configure node(%u) response(%d) error(%d)\n", drv,
+			 ncm->interface, ncm->response, ncm->error);
+
+	if ((ncm->response == NSS_CMN_RESPONSE_ACK) || (ncm->error == NSS_TLS_ERROR_ALREADY_CONFIGURE)) {
+		   atomic_set(&drv->is_configured, true);
+	}
+}
+
+/*
+ * nss_tlsmgr_node_config()
+ *	Send a configure message to the TLS firmware package.
+ */
+static void nss_tlsmgr_node_config(struct nss_tlsmgr *drv)
+{
+	struct nss_tls_msg ntcm = {0};
+	nss_tx_status_t nss_status;
+
+	/*
+	 * Send TLS node configure message to NSS
+	 */
+	nss_tls_msg_init(&ntcm, NSS_TLS_INTERFACE, NSS_TLS_MSG_TYPE_NODE_CONFIG, 0, nss_tlsmgr_node_config_done, drv);
+
+	nss_status = nss_tls_tx_msg(drv->nss_ctx, &ntcm);
+	if (nss_status != NSS_TX_SUCCESS) {
+		nss_tlsmgr_warn("%px: unable to send node configure \n", drv);
+		return;
+	}
+}
+
+/*
+ * nss_tlsmgr_rx_event()
+ *	Handle the response notification from the firmware.
+ */
+static void nss_tlsmgr_rx_event(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_tlsmgr *drv = app_data;
+	struct nss_tls_msg *ntcm = (struct nss_tls_msg *)ncm;
+
+	nss_tlsmgr_trace("%px: received Node stats sync:%u\n", drv, ncm->interface);
+
+	WARN_ON(ncm->interface != NSS_TLS_INTERFACE);
+
+	/*
+	 * The firmware TLS should not configure its DMA rings till it
+	 * knows that the HW is fully configured by host crypto driver.
+	 * Since, the firmware boots independent of the host. There is no
+	 * guarantee that the DMA will be ready for configuration when the
+	 * firmware is configuring itself. Thus our approach is to notify
+	 * the firmware to setup its DMA after the host is ready. Here we
+	 * use a simple approach of module load order where the TLS Manager
+	 * loads after the crypto driver. The expectation is that the crypto
+	 * driver would configure the HW correctly and other modules dependent
+	 * upon it would get the chance to load. Once, the configuration is
+	 * done for TLS when would like to avoid further configuration of the
+	 * DMA.
+	 */
+	if (!atomic_read(&drv->is_configured)) {
+		nss_tlsmgr_node_config(drv);
+		return;
+	}
+
+	switch (ncm->type) {
+        case NSS_TLS_MSG_TYPE_NODE_SYNC: {
+		struct nss_tls_node_stats *sync = &ntcm->msg.node_stats;
+		uint64_t *node_stats = (uint64_t *)&drv->stats;
+		uint32_t *msg_stats = (uint32_t *)sync;
+		int num;
+
+		write_lock(&drv->lock);
+		for (num = 0; num < sizeof(drv->stats)/sizeof(*node_stats); num++) {
+			node_stats[num] += msg_stats[num];
+		}
+
+		write_unlock(&drv->lock);
+		break;
+	}
+
+	default:
+		nss_tlsmgr_info("%px: unhandled tls message type(%u)", drv, ntcm->cm.type);
+		break;
+	}
+}
+
+/*
+ * nss_tlsmgr_init_module()
+ *	Initialize the TLS manager module.
+ */
+int __init nss_tlsmgr_init_module(void)
+{
+	tlsmgr_drv = vzalloc(sizeof(*tlsmgr_drv));
+	if (!tlsmgr_drv) {
+		nss_tlsmgr_warn("Failed to allocate TLS manager context");
+		return -1;
+	}
+
+	atomic_set(&tlsmgr_drv->is_configured, false);
+
+	nss_tlsmgr_trace("registering for base interface(%u)", NSS_TLS_INTERFACE);
+
+	tlsmgr_drv->nss_ctx = nss_tls_notify_register(NSS_TLS_INTERFACE, nss_tlsmgr_rx_event, tlsmgr_drv);
+	if (unlikely(!tlsmgr_drv->nss_ctx)) {
+		nss_tlsmgr_warn("%px: TLS NSS context instance is NULL", tlsmgr_drv);
+		return -ENODEV;
+	}
+
+	tlsmgr_drv->dentry = debugfs_create_dir("qca-nss-tlsmgr", NULL);
+	if (unlikely(!tlsmgr_drv->dentry)) {
+		nss_tlsmgr_warn("Failed to create debugfs directory");
+		return -ENOENT;
+	}
+
+	rwlock_init(&tlsmgr_drv->lock);
+
+	debugfs_create_file("node", S_IRUGO, tlsmgr_drv->dentry, NULL, &tlsmgr_file_ops);
+	tlsmgr_drv->stats_len = tlsmgr_drv->print_len = nss_tlsmgr_stats_size();
+
+	nss_tlsmgr_info_always("qca-nss-tlsmgr module loaded (%s)\n", NSS_TLSMGR_BUILD_ID);
+	return 0;
+}
+
+/*
+ * nss_tlsmgr_exit_module()
+ *	Remove the TLS manager module.
+ */
+void __exit nss_tlsmgr_exit_module(void)
+{
+	debugfs_remove_recursive(tlsmgr_drv->dentry);
+	nss_tls_notify_unregister(NSS_TLS_INTERFACE);
+	atomic_set(&tlsmgr_drv->is_configured, false);
+
+	/*
+	 * Free the tlsmgr ctx
+	 */
+	vfree(tlsmgr_drv);
+	tlsmgr_drv = NULL;
+
+	nss_tlsmgr_info_always("tls manger is unloaded");
+}
+
+module_init(nss_tlsmgr_init_module);
+module_exit(nss_tlsmgr_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS TLS manager");
diff --git a/qca-nss-clients/tls/nss_tlsmgr_buf.c b/qca-nss-clients/tls/nss_tlsmgr_buf.c
new file mode 100644
index 0000000..35b33f2
--- /dev/null
+++ b/qca-nss-clients/tls/nss_tlsmgr_buf.c
@@ -0,0 +1,401 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+/*
+ * nss_tlsmgr_buf.c
+ *	NSS TLS Manager buffer
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/tlshdr.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/crypto.h>
+#include <linux/debugfs.h>
+#include <linux/rtnetlink.h>
+#include <net/ipv6.h>
+#include <linux/if_arp.h>
+#include <linux/etherdevice.h>
+#include <linux/atomic.h>
+#include <asm/cmpxchg.h>
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+
+#include <nss_tls.h>
+#include <nss_tlsmgr.h>
+#include "nss_tlsmgr_ctx.h"
+#include "nss_tlsmgr_crypto.h"
+#include "nss_tlsmgr_buf.h"
+#include "nss_tlsmgr_mdata.h"
+#include "nss_tlsmgr_tun.h"
+#include "nss_tlsmgr_priv.h"
+
+#define NSS_TLSMGR_REC_MAX_SIZE	(sizeof(struct nss_tlsmgr_rec) * NSS_TLSMGR_MDATA_REC_MAX)
+
+/*
+ * nss_tlsmgr_buf_get_rec_start()
+ *	Get record start
+ */
+struct nss_tlsmgr_rec *nss_tlsmgr_buf_get_rec_start(struct nss_tlsmgr_buf *buf)
+{
+	return (struct nss_tlsmgr_rec *)((uint8_t *)buf + sizeof(*buf));
+}
+
+/*
+ * nss_tlsmgr_buf_set_rec()
+ *	Reserve space for a record in a buffer.
+ */
+struct nss_tlsmgr_rec *nss_tlsmgr_buf_set_rec(struct nss_tlsmgr_buf *buf, uint8_t in_segs, uint8_t out_segs)
+{
+	struct nss_tlsmgr_rec *rec;
+	uint16_t cnt;
+
+	if ((in_segs > NSS_TLSMGR_FRAG_MAX) || (out_segs > NSS_TLSMGR_FRAG_MAX)) {
+		nss_tlsmgr_warn("%px: Unsupported fragment count: in_segs(%d) out_segs(%d)", buf, in_segs, out_segs);
+		return NULL;
+	}
+
+	BUG_ON(buf->magic != NSS_TLSMGR_BUF_MAGIC);
+
+	if (buf->rec_cnt >= NSS_TLSMGR_MDATA_REC_MAX) {
+		nss_tlsmgr_warn("%px: Maximum record count reached(%d)", buf, buf->rec_cnt);
+		return NULL;
+	}
+
+	cnt = buf->rec_cnt;
+	buf->rec_cnt++;
+
+	rec = nss_tlsmgr_buf_get_rec_start(buf);
+	rec = rec + cnt;
+
+	sg_init_table(rec->in, in_segs);
+	sg_init_table(rec->out, out_segs);
+
+	return rec;
+}
+EXPORT_SYMBOL(nss_tlsmgr_buf_set_rec);
+
+/*
+ * nss_tlsmgr_buf_get_rec()
+ *	Get a record for the given record index.
+ */
+struct nss_tlsmgr_rec *nss_tlsmgr_buf_get_rec(struct nss_tlsmgr_buf *buf, uint8_t rec_idx)
+{
+	BUG_ON(buf->magic != NSS_TLSMGR_BUF_MAGIC);
+
+	if (rec_idx > NSS_TLSMGR_MDATA_REC_MAX) {
+		nss_tlsmgr_warn("%px: Invalid record index(%d)", buf, rec_idx);
+		return NULL;
+	}
+
+	return nss_tlsmgr_buf_get_rec_start(buf) + rec_idx;
+}
+EXPORT_SYMBOL(nss_tlsmgr_buf_get_rec);
+
+/*
+ * nss_tlsmgr_buf_rx()
+ *	Transform done completion API
+ */
+void nss_tlsmgr_buf_rx(struct nss_tlsmgr_buf *buf, nss_tlsmgr_status_t status)
+{
+	BUG_ON(buf->magic != NSS_TLSMGR_BUF_MAGIC);
+
+	/*
+	 * Invoke user registered callback
+	 */
+	if (buf->cb) {
+		buf->cb(buf->app_data, buf, status);
+	}
+}
+
+/*
+ * nss_tlsmgr_buf_encap()
+ *	Encapsulation API() for TLS records
+ */
+nss_tlsmgr_status_t nss_tlsmgr_buf_encap(struct nss_tlsmgr_buf *buf, nss_tlsmgr_data_callback_t cb, void *app_data)
+{
+	struct nss_tlsmgr_tun *tun = buf->tun;
+	struct net_device *dev = tun->dev;
+	struct nss_tlsmgr_ctx *ctx;
+	struct sk_buff *skb;
+	struct nss_tlsmgr_rec *rec;
+	uint8_t *mdata_start;
+
+	BUG_ON(buf->magic != NSS_TLSMGR_BUF_MAGIC);
+
+	if (unlikely(!cb)) {
+		nss_tlsmgr_error("%px: no user callback registered\n", buf);
+		return NSS_TLSMGR_FAIL_QUEUE_FULL;
+	}
+
+	if (!(dev->flags & IFF_RUNNING)) {
+		return NSS_TLSMGR_FAIL_QUEUE_FULL;
+	}
+
+	/*
+	 * Fill User callback and application data in buffer
+	 */
+	buf->cb = cb;
+	buf->app_data = app_data;
+
+	rec = nss_tlsmgr_buf_get_rec_start(buf);
+
+	mdata_start = (uint8_t *)(rec + buf->rec_cnt);
+	mdata_start = PTR_ALIGN(mdata_start, SMP_CACHE_BYTES);
+
+	/*
+	 * At this point the buf is removed from the active data, only
+	 * metadata is left.
+	 */
+	skb = buf->skb;
+	skb_pull(skb, mdata_start - skb->data);
+
+	ctx = &tun->ctx_enc;
+
+	return nss_tlsmgr_ctx_tx(ctx, skb, rec);
+}
+EXPORT_SYMBOL(nss_tlsmgr_buf_encap);
+
+/*
+ * nss_tlsmgr_buf_decap()
+ *	Decapsulation API() for TLS records
+ */
+nss_tlsmgr_status_t nss_tlsmgr_buf_decap(struct nss_tlsmgr_buf *buf, nss_tlsmgr_data_callback_t cb, void *app_data)
+{
+	struct nss_tlsmgr_tun *tun = buf->tun;
+	struct nss_tlsmgr_ctx *ctx;
+	struct sk_buff *skb;
+	struct nss_tlsmgr_rec *rec;
+	uint8_t *mdata_start;
+
+	BUG_ON(buf->magic != NSS_TLSMGR_BUF_MAGIC);
+
+	if (unlikely(!cb)) {
+		nss_tlsmgr_error("%px: no user callback registered\n", buf);
+		return NSS_TLSMGR_FAIL_QUEUE_FULL;
+	}
+
+	if (!(tun->dev->flags & IFF_RUNNING)) {
+		return NSS_TLSMGR_FAIL_QUEUE_FULL;
+	}
+
+	/*
+	 * Fill User callback and application data in buffer
+	 */
+	buf->cb = cb;
+	buf->app_data = app_data;
+
+	rec = nss_tlsmgr_buf_get_rec_start(buf);
+
+	mdata_start = (uint8_t *)(rec + buf->rec_cnt);
+	mdata_start = PTR_ALIGN(mdata_start, SMP_CACHE_BYTES);
+
+	/*
+	 * At this point the buf is removed from the active data, only
+	 * metadata is left.
+	 */
+	skb = buf->skb;
+	skb_pull(skb, mdata_start - skb->data);
+
+	ctx = &tun->ctx_dec;
+
+	return nss_tlsmgr_ctx_tx(ctx, skb, rec);
+}
+EXPORT_SYMBOL(nss_tlsmgr_buf_decap);
+
+/*
+ * nss_tlsmgr_buf_decap_skb2recs()
+ *	Create recs from SKB
+ */
+nss_tlsmgr_status_t nss_tlsmgr_buf_decap_skb2recs(struct sk_buff *skb, struct nss_tlsmgr_buf *buf)
+{
+	struct nss_tlsmgr_rec *rec;
+	uint16_t tls_len, version;
+	struct tlshdr *hdr;
+	int payload_len;
+	uint8_t *data;
+
+	if (skb_linearize(skb) < 0) {
+		nss_tlsmgr_warn("%px: Failed to linearize SKB", skb);
+		return NSS_TLSMGR_FAIL_LINEARIZE;
+	}
+
+	payload_len = skb->len;
+	data = skb->data;
+
+	/*
+	 * Packet will be of the form
+	 * TLS_HDR1 APP_DATA1 TLS_HDR2 APP_DATA2...
+	 * Here we will parse the header and check for the application data length for that
+	 * record and prepare TLS record.
+	 */
+	do {
+		hdr = (struct tlshdr *)data;
+		tls_len = ntohs(hdr->len) + sizeof(*hdr);
+		payload_len = payload_len - tls_len;
+		version = ntohs(hdr->version);
+
+		/*
+		 * Check if this payload is malformed or not
+		 */
+		if (payload_len < 0) {
+			nss_tlsmgr_warn("%px: Payload length shorter than record length (%d)", skb, tls_len);
+			return NSS_TLSMGR_FAIL_REC_LEN;
+		}
+
+		/*
+		 * Check if the type is supported for offload, note we only decode data and CCS.
+		 * Other types are skipped in processing
+		 */
+		if ((hdr->type != TLSHDR_REC_TYPE_DATA) && (hdr->type != TLSHDR_REC_TYPE_CCS)) {
+			nss_tlsmgr_warn("%px: Skipping TLS type (%d)", buf, hdr->type);
+			continue;
+		}
+
+		/*
+		 * Ideally, it should not receive 1.0 version packet. This check is needed for
+		 * decapsulation side
+		 */
+		if ((version != TLSHDR_VERSION_1_1) && (version != TLSHDR_VERSION_1_2)) {
+			nss_tlsmgr_warn("%px: bad TLS version (0x%x)", buf, version);
+			return NSS_TLSMGR_FAIL_REC_VERSION;
+		}
+
+		/*
+		 * Decapsulation is only supported in non-SG mode.
+		 */
+		rec = nss_tlsmgr_buf_set_rec(buf, 1, 1);
+		if (unlikely(!rec)) {
+			nss_tlsmgr_warn("%px: Error setting record", buf);
+			return NSS_TLSMGR_FAIL_REC_RANGE;
+		}
+
+		rec->rec_type = hdr->type;
+		sg_set_buf(&rec->in[0], data, tls_len);
+		sg_set_buf(&rec->out[0], data, tls_len);
+		data += tls_len;
+	} while(payload_len);
+
+	nss_tlsmgr_info("%px: SKB decoded to recs(%d) of size( %d)", skb, buf->rec_cnt, skb->len);
+	return NSS_TLSMGR_OK;
+}
+EXPORT_SYMBOL(nss_tlsmgr_buf_decap_skb2recs);
+
+/*
+ * nss_tlsmgr_buf_get_priv()
+ *	Get User private data from buffer.
+ */
+void *nss_tlsmgr_buf_get_priv(struct nss_tlsmgr_buf *buf)
+{
+	return buf->priv;
+}
+EXPORT_SYMBOL(nss_tlsmgr_buf_get_priv);
+
+/*
+ * nss_tlsmgr_buf_get_rec_cnt()
+ *	Total number of records in a buffer.
+ */
+uint8_t nss_tlsmgr_buf_get_rec_cnt(struct nss_tlsmgr_buf *buf)
+{
+	return buf->rec_cnt;
+}
+EXPORT_SYMBOL(nss_tlsmgr_buf_get_rec_cnt);
+
+/*
+ * nss_tlsmgr_buf2skb()
+ *	Buffer to SKB conversion.
+ */
+struct sk_buff *nss_tlsmgr_buf2skb(struct nss_tlsmgr_buf *buf)
+{
+	return buf->skb;
+}
+EXPORT_SYMBOL(nss_tlsmgr_buf2skb);
+
+/*
+ * nss_tlsmgr_skb2buf()
+ *	SKB to buffer conversion.
+ */
+struct nss_tlsmgr_buf *nss_tlsmgr_skb2buf(struct sk_buff *skb)
+{
+	return (struct nss_tlsmgr_buf *)skb->head;
+}
+EXPORT_SYMBOL(nss_tlsmgr_skb2buf);
+
+/*
+ * nss_tlsmgr_buf_alloc()
+ *	TLS buffer allocation API()
+ */
+struct nss_tlsmgr_buf *nss_tlsmgr_buf_alloc(struct net_device *dev, void *priv)
+{
+	struct nss_tlsmgr_tun *tun = netdev_priv(dev);
+	struct nss_tlsmgr_buf *buf;
+	struct sk_buff *skb;
+	size_t size;
+
+	/*
+	 * The metadata start needs to be aligned to the Cache line boundary
+	 */
+	size = sizeof(*buf) + (sizeof(struct nss_tlsmgr_rec) * NSS_TLSMGR_MDATA_REC_MAX);
+	size += sizeof(struct nss_tlsmgr_mdata) + SMP_CACHE_BYTES;
+
+	size = ALIGN(size, SMP_CACHE_BYTES);
+
+	/*
+	 * Allocate SKB for TLS buffer
+	 */
+	skb = netdev_alloc_skb(dev, size);
+	if (unlikely(!skb)) {
+		nss_tlsmgr_warn("%px:unable to allocate SKB\n", priv);
+		return NULL;
+	}
+
+	/*
+	 * The buf structure must start from head; hence reset the
+	 * data back to head
+	 */
+	skb_push(skb, skb_headroom(skb));
+	skb_trim(skb, 0);
+
+	buf = (struct nss_tlsmgr_buf *)skb_put(skb, size);
+	memset(buf, 0, skb->len);
+	buf->tun = tun;
+	buf->skb = skb;
+	buf->priv = priv;
+	buf->magic = NSS_TLSMGR_BUF_MAGIC;
+
+	nss_tlsmgr_trace("%px: allocated buffer of size(%zu)", skb, size);
+	return buf;
+}
+EXPORT_SYMBOL(nss_tlsmgr_buf_alloc);
+
+/*
+ * nss_tlsmgr_buf_free()
+ *	TLS buffer free API()
+ */
+void nss_tlsmgr_buf_free(struct nss_tlsmgr_buf *buf)
+{
+	/*
+	 * Free the SKB
+	 */
+	dev_kfree_skb_any(buf->skb);
+}
+EXPORT_SYMBOL(nss_tlsmgr_buf_free);
diff --git a/qca-nss-clients/tls/nss_tlsmgr_buf.h b/qca-nss-clients/tls/nss_tlsmgr_buf.h
new file mode 100644
index 0000000..9d508fc
--- /dev/null
+++ b/qca-nss-clients/tls/nss_tlsmgr_buf.h
@@ -0,0 +1,46 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+/*
+ * nss_tlsmgr_buf.h
+ */
+
+#ifndef __NSS_TLSMGR_BUF_H_
+#define __NSS_TLSMGR_BUF_H_
+
+#define NSS_TLSMGR_BUF_MAGIC 0x884e
+
+/**
+ * NSS tls manager buffer stucture
+ */
+struct nss_tlsmgr_buf {
+	struct sk_buff *skb;		/**< SKB container pointer. */
+	struct nss_tlsmgr_tun *tun;	/**< Pointer to TLS tunnel. */
+	void *priv; 			/**< Per buffer private data pointer. */
+	void *app_data;			/**< Callback application data. */
+	nss_tlsmgr_data_callback_t cb;	/**< Callback routine. */
+	uint16_t rec_cnt;		/**< Number of records available in buffer. */
+	uint16_t magic;			/**< Magic number protection. */
+	struct nss_tlsmgr_rec rec[];	/**< Records starts after buffer. */
+};
+
+void nss_tlsmgr_buf_rx(struct nss_tlsmgr_buf *buf, nss_tlsmgr_status_t status);
+
+struct nss_tlsmgr_rec *nss_tlsmgr_buf_get_rec_start(struct nss_tlsmgr_buf *buf);
+
+#endif /* !__NSS_TLSMGR_BUF_H_ */
diff --git a/qca-nss-clients/tls/nss_tlsmgr_crypto.c b/qca-nss-clients/tls/nss_tlsmgr_crypto.c
new file mode 100644
index 0000000..1a8b0fe
--- /dev/null
+++ b/qca-nss-clients/tls/nss_tlsmgr_crypto.c
@@ -0,0 +1,372 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+/*
+ * nss_tlsmgr_crypto.c
+ *	NSS TLS Manager crypto object
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/tlshdr.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/crypto.h>
+#include <linux/debugfs.h>
+#include <linux/rtnetlink.h>
+#include <net/ipv6.h>
+#include <linux/if_arp.h>
+#include <linux/etherdevice.h>
+#include <linux/atomic.h>
+
+#include <crypto/algapi.h>
+#include <crypto/aead.h>
+#include <crypto/aes.h>
+#include <crypto/authenc.h>
+#include <crypto/des.h>
+#include <crypto/sha.h>
+#include <crypto/skcipher.h>
+#include <crypto/hash.h>
+#include <crypto/internal/hash.h>
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+
+#include <nss_cryptoapi.h>
+#include <nss_tls.h>
+#include <nss_tlsmgr.h>
+
+#include "nss_tlsmgr_ctx.h"
+#include "nss_tlsmgr_crypto.h"
+#include "nss_tlsmgr_tun.h"
+#include "nss_tlsmgr_priv.h"
+
+#define NSS_TLSMGR_KEY_PARAM_SIZE RTA_SPACE(sizeof(struct crypto_authenc_key_param))
+
+static struct nss_tlsmgr_algo_info tlsmgr_algo_info[NSS_TLSMGR_ALGO_MAX] = {
+	{"cipher_null", NSS_TLSMGR_KEY_PARAM_SIZE},
+	{"hmac(sha1)", NSS_TLSMGR_KEY_PARAM_SIZE},
+	{"hmac(sha256)", NSS_TLSMGR_KEY_PARAM_SIZE},
+	{"authenc(hmac(sha1),cbc(aes))", NSS_TLSMGR_KEY_PARAM_SIZE},
+	{"authenc(hmac(sha256),cbc(aes))", NSS_TLSMGR_KEY_PARAM_SIZE},
+	{"authenc(hmac(sha1),cbc(des3_ede))", NSS_TLSMGR_KEY_PARAM_SIZE},
+	{"authenc(hmac(sha256),cbc(des3_ede))", NSS_TLSMGR_KEY_PARAM_SIZE},
+};
+
+/*
+ * nss_tlsmgr_crypto_free()
+ *	Free the Crypto context.
+ */
+void nss_tlsmgr_crypto_free(struct nss_tlsmgr_crypto *ntc)
+{
+	if (ntc->aead)
+		crypto_free_aead(ntc->aead);
+
+	if (ntc->ahash)
+		crypto_free_ahash(ntc->ahash);
+
+	vfree(ntc);
+}
+
+/*
+ * nss_tlsmgr_crypto_alloc()
+ *	Allocate crypto node and configure crypto
+ */
+struct nss_tlsmgr_crypto *nss_tlsmgr_crypto_alloc(struct nss_tlsmgr_config *cfg)
+{
+	struct crypto_authenc_key_param *key_param;
+	struct nss_tlsmgr_algo_info *info;
+	struct nss_tlsmgr_crypto *ntc;
+	struct rtattr *rta;
+	char *keys, *p;
+	uint16_t keylen;
+
+	ntc = vzalloc(sizeof(*ntc));
+	if (!ntc) {
+		nss_tlsmgr_warn("failed to allocate crypto data\n");
+		return NULL;
+	}
+
+	INIT_LIST_HEAD(&ntc->list);
+
+	nss_tlsmgr_trace("algo:%d cipher_keylen:%d auth_keylen:%d nonce_len:%d\n",
+				cfg->algo, cfg->cipher_key.len, cfg->auth_key.len, cfg->nonce.len);
+
+	info = &tlsmgr_algo_info[cfg->algo];
+
+	switch (cfg->algo) {
+	case NSS_TLSMGR_ALGO_AES_CBC_SHA1_HMAC:
+	case NSS_TLSMGR_ALGO_AES_CBC_SHA256_HMAC:
+	case NSS_TLSMGR_ALGO_3DES_CBC_SHA1_HMAC:
+	case NSS_TLSMGR_ALGO_3DES_CBC_SHA256_HMAC:
+		ntc->aead = crypto_alloc_aead(info->name, 0, 0);
+		if (IS_ERR(ntc->aead)) {
+			nss_tlsmgr_warn("failed to allocate crypto aead context for algorithm(%d)\n", cfg->algo);
+			vfree(ntc);
+			return NULL;
+		}
+
+		/*
+		 * Construct keys
+		 */
+		keylen = info->rta_key_sz;
+		keylen += cfg->cipher_key.len;
+		keylen += cfg->auth_key.len;
+		keylen += cfg->nonce.len;
+
+		keys = vzalloc(keylen);
+		if (!keys) {
+			nss_tlsmgr_warn("failed to allocate key memory\n");
+			crypto_free_aead(ntc->aead);
+			vfree(ntc);
+			return NULL;
+		}
+
+		p = keys;
+		rta = (void *)p;
+		rta->rta_type = CRYPTO_AUTHENC_KEYA_PARAM;
+		rta->rta_len = RTA_LENGTH(sizeof(*key_param));
+		key_param = RTA_DATA(rta);
+		p += RTA_SPACE(sizeof(*key_param));
+
+		/*
+		 * Copy authentication key
+		 */
+		memcpy(p, cfg->auth_key.data, cfg->auth_key.len);
+		p += cfg->auth_key.len;
+
+		/*
+		 * Copy cipher Key
+		 */
+		key_param->enckeylen = cpu_to_be32(cfg->cipher_key.len);
+		memcpy(p, cfg->cipher_key.data, cfg->cipher_key.len);
+
+		if (crypto_aead_setkey(ntc->aead, keys, keylen)) {
+			nss_tlsmgr_warn("failed to configure keys");
+			crypto_free_aead(ntc->aead);
+			vfree(keys);
+			vfree(ntc);
+			return NULL;
+		}
+
+		nss_cryptoapi_aead_ctx2session(ntc->aead, &ntc->crypto_idx);
+		ntc->aead = NULL;
+		vfree(keys);
+		break;
+
+	case NSS_TLSMGR_ALGO_NULL_SHA1_HMAC:
+	case NSS_TLSMGR_ALGO_NULL_SHA256_HMAC:
+		ntc->ahash = crypto_alloc_ahash(info->name, 0, 0);
+		if (IS_ERR(ntc->ahash)) {
+			nss_tlsmgr_warn("%px: failed to allocate crypto ahash context\n", ntc);
+			vfree(ntc);
+			return NULL;
+		}
+
+		if (crypto_ahash_setkey(ntc->ahash, cfg->auth_key.data, cfg->auth_key.len)) {
+			nss_tlsmgr_warn("%px: failed to configure keys\n", ntc);
+			crypto_free_ahash(ntc->ahash);
+			vfree(ntc);
+			return NULL;
+		}
+
+		nss_cryptoapi_ahash_ctx2session(ntc->ahash, &ntc->crypto_idx);
+		ntc->ahash = NULL;
+		break;
+
+	default:
+		nss_tlsmgr_warn("%px: invalid crypto algorithm(%d)\n", ntc, cfg->algo);
+		vfree(ntc);
+		return NULL;
+	}
+
+	nss_tlsmgr_trace("crypto_aead allocated\n");
+	return ntc;
+}
+
+/*
+ * nss_tlsmgr_crypto_update_null()
+ *	Update the NULL crypto keys.
+ *
+ * This is used to create a dummy crypto session when TLS tunnel is created.
+ * This session will be in the active list until user do a crypto update/CCS.
+ * Once CCS is triggered by the user, then this dummy session will be removed
+ * from the list and this new crypto updates will become the new active session.
+ */
+nss_tlsmgr_status_t nss_tlsmgr_crypto_update_null(struct net_device *dev, struct nss_tlsmgr_ctx *ctx)
+{
+        enum nss_tls_msg_type msg_type = NSS_TLS_MSG_TYPE_CIPHER_UPDATE;
+	struct nss_tlsmgr_tun *tun = netdev_priv(dev);
+	struct nss_tls_cipher_update *ntcu;
+	struct nss_tlsmgr_crypto *crypto;
+	struct nss_tlsmgr_config cfg;
+	struct nss_tls_msg ntm;
+	nss_tx_status_t status;
+
+	memset(&cfg, 0, sizeof(struct nss_tlsmgr_config));
+	cfg.algo = NSS_TLSMGR_ALGO_NULL_SHA1_HMAC;
+	cfg.hdr_ver = TLSHDR_VERSION_1_2;
+
+	/*
+	 * Create a dummy crypto session for the first CCS operation
+	 */
+	crypto = nss_tlsmgr_crypto_alloc(&cfg);
+	if (!crypto) {
+		nss_tlsmgr_crypto_free(crypto);
+		nss_tlsmgr_warn("%px: unable to update encap context data", ctx);
+		return NSS_TLSMGR_FAIL_NOMEM;
+	}
+
+	memset(&ntm, 0, sizeof(struct nss_tls_msg));
+
+	ntcu = &ntm.msg.cipher_update;
+	ntcu->crypto_idx = crypto->crypto_idx;
+	ntcu->ver = cfg.hdr_ver;
+	ntcu->skip = 1;
+
+	status = nss_tls_tx_msg_sync(ctx->nss_ctx, ctx->ifnum, msg_type, sizeof(*ntcu), &ntm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tlsmgr_warn("%px: Failed to configure decap, status:%d, error:%d", ctx, status, ntm.cm.error);
+		return false;
+	}
+
+	/*
+	 * Add crypto to context active list
+	 */
+	write_lock(&tun->lock);
+	list_add_tail(&crypto->list, &ctx->crypto_active);
+	write_unlock(&tun->lock);
+
+	nss_tlsmgr_trace("%px: NULL context(0x%x) update done", ctx, ctx->ifnum & ((1 << NSS_CORE_ID_SHIFT) - 1));
+
+	return NSS_TLSMGR_OK;
+}
+
+/*
+ * nss_tlsmgr_crypto_update_encap()
+ *	Update the encapsulation crypto keys.
+ */
+nss_tlsmgr_status_t nss_tlsmgr_crypto_update_encap(struct net_device *dev, struct nss_tlsmgr_config *cfg)
+{
+        enum nss_tls_msg_type msg_type = NSS_TLS_MSG_TYPE_CIPHER_UPDATE;
+	struct nss_tlsmgr_tun *tun = netdev_priv(dev);
+	struct nss_tlsmgr_ctx *ctx = &tun->ctx_enc;
+	struct nss_tls_cipher_update *ntcu;
+	struct nss_tlsmgr_crypto *crypto;
+	struct nss_tls_msg ntm;
+	nss_tx_status_t status;
+
+	if ((cfg->hdr_ver != TLSHDR_VERSION_1_1) && (cfg->hdr_ver != TLSHDR_VERSION_1_2)) {
+		nss_tlsmgr_warn("%px: Invalid TLS header version: %d", ctx, cfg->hdr_ver);
+		return NSS_TLSMGR_FAIL_REC_VERSION;
+	}
+
+	if (cfg->algo >= ARRAY_SIZE(tlsmgr_algo_info)) {
+		nss_tlsmgr_warn("invalid crypto algorithm\n");
+		return -EINVAL;
+	}
+
+	crypto = nss_tlsmgr_crypto_alloc(cfg);
+	if (!crypto) {
+		nss_tlsmgr_warn("%px: unable to update encap context data", ctx);
+		return NSS_TLSMGR_FAIL_NOMEM;
+	}
+
+	memset(&ntm, 0, sizeof(struct nss_tls_msg));
+
+	ntcu = &ntm.msg.cipher_update;
+	ntcu->crypto_idx = crypto->crypto_idx;
+	ntcu->ver = cfg->hdr_ver;
+
+	status = nss_tls_tx_msg_sync(ctx->nss_ctx, ctx->ifnum, msg_type, sizeof(*ntcu), &ntm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tlsmgr_crypto_free(crypto);
+		nss_tlsmgr_warn("%px: Failed to configure encap, status:%d, error:%d", ctx, status, ntm.cm.error);
+		return NSS_TLSMGR_FAIL_MESSAGE;
+	}
+
+	/*
+	 * Add crypto to context active list
+	 */
+	write_lock(&tun->lock);
+	list_add_tail(&crypto->list, &ctx->crypto_active);
+	write_unlock(&tun->lock);
+
+	nss_tlsmgr_trace("%px: encap context(0x%x) update done", ctx, ctx->ifnum & ((1 << NSS_CORE_ID_SHIFT) - 1));
+
+	return NSS_TLSMGR_OK;
+}
+EXPORT_SYMBOL(nss_tlsmgr_crypto_update_encap);
+
+/*
+ * nss_tlsmgr_crypto_update_decap()
+ *	Update the decapsulation crypto keys.
+ */
+nss_tlsmgr_status_t nss_tlsmgr_crypto_update_decap(struct net_device *dev, struct nss_tlsmgr_config *cfg)
+{
+        enum nss_tls_msg_type msg_type = NSS_TLS_MSG_TYPE_CIPHER_UPDATE;
+	struct nss_tlsmgr_tun *tun = netdev_priv(dev);
+	struct nss_tlsmgr_ctx *ctx = &tun->ctx_dec;
+	struct nss_tls_cipher_update *ntcu;
+	struct nss_tlsmgr_crypto *crypto;
+	struct nss_tls_msg ntm;
+	nss_tx_status_t status;
+
+	if ((cfg->hdr_ver != TLSHDR_VERSION_1_1) && (cfg->hdr_ver != TLSHDR_VERSION_1_2)) {
+		nss_tlsmgr_warn("%px: Invalid TLS header version: %d", ctx, cfg->hdr_ver);
+		return NSS_TLSMGR_FAIL_REC_VERSION;
+	}
+
+	if (cfg->algo >= ARRAY_SIZE(tlsmgr_algo_info)) {
+		nss_tlsmgr_warn("invalid crypto algorithm\n");
+		return -EINVAL;
+	}
+
+	crypto = nss_tlsmgr_crypto_alloc(cfg);
+	if (!crypto) {
+		nss_tlsmgr_warn("%px: unable to update decap context data", ctx);
+		return NSS_TLSMGR_FAIL_NOMEM;
+	}
+
+	memset(&ntm, 0, sizeof(struct nss_tls_msg));
+
+	ntcu = &ntm.msg.cipher_update;
+	ntcu->crypto_idx = crypto->crypto_idx;
+	ntcu->ver = cfg->hdr_ver;
+
+	status = nss_tls_tx_msg_sync(ctx->nss_ctx, ctx->ifnum, msg_type, sizeof(*ntcu), &ntm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tlsmgr_crypto_free(crypto);
+		nss_tlsmgr_warn("%px: Failed to configure decap, status:%d, error:%d", ctx, status, ntm.cm.error);
+		return false;
+	}
+
+	/*
+	 * Add crypto to context active list
+	 */
+	write_lock(&tun->lock);
+	list_add_tail(&crypto->list, &ctx->crypto_active);
+	write_unlock(&tun->lock);
+
+	nss_tlsmgr_trace("%px: decap context(0x%x) update done", ctx, ctx->ifnum & ((1 << NSS_CORE_ID_SHIFT) - 1));
+
+	return NSS_TLSMGR_OK;
+}
+EXPORT_SYMBOL(nss_tlsmgr_crypto_update_decap);
diff --git a/qca-nss-clients/tls/nss_tlsmgr_crypto.h b/qca-nss-clients/tls/nss_tlsmgr_crypto.h
new file mode 100644
index 0000000..2c522d9
--- /dev/null
+++ b/qca-nss-clients/tls/nss_tlsmgr_crypto.h
@@ -0,0 +1,49 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+/*
+ * nss_tlsmgr_crypto.h
+ */
+
+#ifndef __NSS_TLSMGR_CRYPTO_H_
+#define __NSS_TLSMGR_CRYPTO_H_
+
+/*
+ * TLS algorithm information
+ */
+struct nss_tlsmgr_algo_info {
+	char *name;				/* Linux crypto algorithm string. */
+	uint32_t rta_key_sz;			/* RTA key attribute size. */
+};
+
+/*
+ * TLS crypto configuration data; this data structure will be maintained
+ * as a list in actual context data. This data structure will hold aead
+ * context and crypto index to be used for a particular context.
+ */
+struct nss_tlsmgr_crypto {
+	struct list_head list;                  /* List of crypto data. */
+	struct crypto_aead *aead;               /* Linux AEAD context. */
+	struct crypto_ahash *ahash;		/* Linux crypto AHASH context */
+	uint32_t crypto_idx;			/* List head */
+};
+
+nss_tlsmgr_status_t nss_tlsmgr_crypto_update_null(struct net_device *dev, struct nss_tlsmgr_ctx *ctx);
+struct nss_tlsmgr_crypto *nss_tlsmgr_crypto_alloc(struct nss_tlsmgr_config *cfg);
+void nss_tlsmgr_crypto_free(struct nss_tlsmgr_crypto *crypto);
+#endif /* !__NSS_TLSMGR_CRYPTO_H_ */
diff --git a/qca-nss-clients/tls/nss_tlsmgr_ctx.c b/qca-nss-clients/tls/nss_tlsmgr_ctx.c
new file mode 100644
index 0000000..2fd5d03
--- /dev/null
+++ b/qca-nss-clients/tls/nss_tlsmgr_ctx.c
@@ -0,0 +1,685 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+/*
+ * nss_tlsmgr_ctx.c
+ *	NSS TLS Manager context
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/tlshdr.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/debugfs.h>
+#include <linux/rtnetlink.h>
+#include <net/ipv6.h>
+#include <linux/if_arp.h>
+#include <linux/etherdevice.h>
+#include <linux/atomic.h>
+#include <linux/delay.h>
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+
+#include <nss_tls.h>
+#include <nss_tlsmgr.h>
+#include "nss_tlsmgr_buf.h"
+#include "nss_tlsmgr_ctx.h"
+#include "nss_tlsmgr_crypto.h"
+#include "nss_tlsmgr_mdata.h"
+#include "nss_tlsmgr_tun.h"
+#include "nss_tlsmgr_priv.h"
+
+/*
+ * Context Host statistics print info
+ */
+static const struct nss_tlsmgr_print tlsmgr_print_ctx_host_stats[] = {
+	{"\ttx_packets", NSS_TLSMGR_PRINT_DWORD},
+	{"\ttx_bytes", NSS_TLSMGR_PRINT_DWORD},
+	{"\ttx_error", NSS_TLSMGR_PRINT_DWORD},
+	{"\trx_packets", NSS_TLSMGR_PRINT_DWORD},
+	{"\trx_bytes", NSS_TLSMGR_PRINT_DWORD},
+	{"\trx_error", NSS_TLSMGR_PRINT_DWORD},
+};
+
+/*
+ * Context statistics print info
+ */
+static const struct nss_tlsmgr_print tlsmgr_print_ctx_fw_stats[] = {
+	{"\trx_packets", NSS_TLSMGR_PRINT_DWORD},
+	{"\trx_bytes", NSS_TLSMGR_PRINT_DWORD},
+	{"\ttx_packets", NSS_TLSMGR_PRINT_DWORD},
+	{"\ttx_bytes", NSS_TLSMGR_PRINT_DWORD},
+	{"\trx_dropped[0]", NSS_TLSMGR_PRINT_DWORD},
+	{"\trx_dropped[1]", NSS_TLSMGR_PRINT_DWORD},
+	{"\trx_dropped[2]", NSS_TLSMGR_PRINT_DWORD},
+	{"\trx_dropped[3]", NSS_TLSMGR_PRINT_DWORD},
+
+	{"\tsingle_rec", NSS_TLSMGR_PRINT_DWORD},
+	{"\tmulti_rec", NSS_TLSMGR_PRINT_DWORD},
+	{"\ttx_inval_reqs", NSS_TLSMGR_PRINT_DWORD},
+	{"\trx_ccs_rec", NSS_TLSMGR_PRINT_DWORD},
+	{"\tfail_ccs", NSS_TLSMGR_PRINT_DWORD},
+	{"\teth_node_deactive", NSS_TLSMGR_PRINT_DWORD},
+	{"\tcrypto_alloc_success", NSS_TLSMGR_PRINT_DWORD},
+	{"\tcrypto_free_req", NSS_TLSMGR_PRINT_DWORD},
+	{"\tcrypto_free_success", NSS_TLSMGR_PRINT_DWORD},
+	{"\tfail_crypto_alloc", NSS_TLSMGR_PRINT_DWORD},
+	{"\tfail_crypto_lookup", NSS_TLSMGR_PRINT_DWORD},
+	{"\tfail_req_alloc", NSS_TLSMGR_PRINT_DWORD},
+	{"\tfail_pbuf_stats", NSS_TLSMGR_PRINT_DWORD},
+	{"\tfail_ctx_active", NSS_TLSMGR_PRINT_DWORD},
+
+	{"\thw_len_error", NSS_TLSMGR_PRINT_DWORD},
+	{"\thw_token_error", NSS_TLSMGR_PRINT_DWORD},
+	{"\thw_bypass_error", NSS_TLSMGR_PRINT_DWORD},
+	{"\thw_crypto_error", NSS_TLSMGR_PRINT_DWORD},
+	{"\thw_hash_error", NSS_TLSMGR_PRINT_DWORD},
+	{"\thw_config_error", NSS_TLSMGR_PRINT_DWORD},
+	{"\thw_algo_error", NSS_TLSMGR_PRINT_DWORD},
+	{"\thw_hash_ovf_error", NSS_TLSMGR_PRINT_DWORD},
+	{"\thw_auth_error", NSS_TLSMGR_PRINT_DWORD},
+	{"\thw_pad_verify_error", NSS_TLSMGR_PRINT_DWORD},
+	{"\thw_timeout_error", NSS_TLSMGR_PRINT_DWORD},
+
+	{"\tno_desc_in", NSS_TLSMGR_PRINT_DWORD},
+	{"\tno_desc_out", NSS_TLSMGR_PRINT_DWORD},
+	{"\tno_reqs", NSS_TLSMGR_PRINT_DWORD},
+};
+
+#ifdef NSS_TLSMGR_DEBUG_DUMP
+/*
+ * nss_tlsmgr_ctx_dump_mdata()
+ *	Dump metadata
+ */
+static void nss_tlsmgr_ctx_dump_mdata(struct nss_tlsmgr_mdata *mdata)
+{
+	int i;
+
+	nss_tlsmgr_trace("mdata_ver (%x) mdata_rec_cnt (%x) in_frag_cnt (%x) out_frag_cnt (%x) flags (%x)\n",
+			mdata->ver, mdata->rec_cnt, mdata->in_frag_cnt, mdata->out_frag_cnt, mdata->flags);
+
+	for (i = 0; i < 4; i++) {
+		nss_tlsmgr_trace("rec_len (%x) rec_type (%x) in_frags (%x) out_frags (%x)\n",
+			mdata->rec[i].rec_len, mdata->rec[i].rec_type, mdata->rec[i].in_frags, mdata->rec[i].out_frags);
+	}
+}
+
+#define NSS_TLSMGR_DUMP_MDATA(mdata) nss_tlsmgr_ctx_dump_mdata(mdata);
+#else
+#define NSS_TLSMGR_DUMP_MDATA(mdata)
+#endif
+
+/*
+ * nss_tlsmgr_ctx_stats_size()
+ *	Calculate size of context stats
+ */
+static ssize_t nss_tlsmgr_ctx_stats_size(void)
+{
+	const struct nss_tlsmgr_print *prn = tlsmgr_print_ctx_fw_stats;
+	ssize_t len = NSS_TLSMGR_CTX_PRINT_EXTRA;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(tlsmgr_print_ctx_fw_stats); i++, prn++)
+		len += strlen(prn->str) + prn->var_size;
+
+	prn = tlsmgr_print_ctx_host_stats;
+
+	len += NSS_TLSMGR_CTX_PRINT_EXTRA;
+
+	for (i = 0; i < ARRAY_SIZE(tlsmgr_print_ctx_host_stats); i++, prn++)
+		len += strlen(prn->str) + prn->var_size;
+
+	return len;
+}
+
+/*
+ * nss_tlsmgr_ctx_print()
+ *	Print context statistics
+ */
+static ssize_t nss_tlsmgr_ctx_print(struct nss_tlsmgr_ctx *ctx, char *buf)
+{
+	const struct nss_tlsmgr_print *prn = tlsmgr_print_ctx_fw_stats;
+	ssize_t max_len = ctx->print_len;
+	uint64_t *stats_dword = (uint64_t *)&ctx->fw_stats;
+	ssize_t len;
+	int i;
+
+	/*
+	 * This expects a strict order as per the stats structure
+	 */
+	len = snprintf(buf, max_len, "---- Context -----\n");
+	len += snprintf(buf + len, max_len - len, "stats: {\n");
+
+	for (i = 0; i < ARRAY_SIZE(tlsmgr_print_ctx_fw_stats); i++, prn++)
+		len += snprintf(buf + len, max_len - len, "%s: %llu\n", prn->str, *stats_dword++);
+
+	len += snprintf(buf + len, max_len - len, "}\n");
+
+	stats_dword = (uint64_t *)&ctx->host_stats;
+
+	len += snprintf(buf + len, max_len - len, "Host stats: {\n");
+	prn = tlsmgr_print_ctx_host_stats;
+
+	for (i = 0; i < ARRAY_SIZE(tlsmgr_print_ctx_host_stats); i++, prn++)
+		len += snprintf(buf + len, max_len - len, "%s: %llu\n", prn->str, *stats_dword++);
+
+	len += snprintf(buf + len, max_len - len, "}\n");
+
+	return len;
+}
+
+/*
+ * nss_tlsmgr_ctx_map_frag()
+ *	map fragments
+ */
+static inline uint16_t nss_tlsmgr_ctx_map_frag(struct nss_tlsmgr_ctx *ctx, struct scatterlist *sg,
+					struct nss_tlsmgr_mdata_frag *frag, uint8_t *frag_cnt)
+{
+	struct scatterlist *cur = sg;
+	uint16_t frag_len = 0;
+	uint8_t frag_count;
+	int i = 0;
+
+	frag_count = dma_map_sg(ctx->nss_dev, sg, sg_nents(sg), DMA_TO_DEVICE);
+	for_each_sg(sg, cur, frag_count, i) {
+		frag[i].len = sg_dma_len(cur);
+		frag[i].addr = sg_dma_address(cur);
+		frag_len += frag[i].len;
+	}
+
+	frag[0].flags |= NSS_TLSMGR_MDATA_FRAG_FLAG_FIRST;
+	frag[frag_count - 1].flags |= NSS_TLSMGR_MDATA_FRAG_FLAG_LAST;
+
+	*frag_cnt = frag_count;
+	return frag_len;
+}
+
+/*
+ * nss_tlsmgr_ctx_unmap_frag()
+ *	Unmap fragments
+ */
+static inline void nss_tlsmgr_ctx_unmap_frag(struct nss_tlsmgr_ctx *ctx, struct nss_tlsmgr_mdata_frag *frag_ptr, uint8_t frag_cnt)
+{
+	uint8_t frag_idx;
+
+	for (frag_idx = 0; frag_idx < frag_cnt; frag_ptr++, frag_idx++) {
+		dma_unmap_single(ctx->nss_dev, frag_ptr->addr, frag_ptr->len, DMA_BIDIRECTIONAL);
+	}
+}
+
+/*
+ * nss_tlsmgr_ctx_read_stats()
+ *	Read context info
+ */
+ssize_t nss_tlsmgr_ctx_read_stats(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	struct nss_tlsmgr_ctx *ctx = fp->private_data;
+	struct nss_tlsmgr_tun *tun = netdev_priv(ctx->dev);
+	ssize_t print_len = ctx->print_len;
+	ssize_t len = 0;
+	char *buf;
+
+	buf = vzalloc(print_len);
+	if (!buf) {
+		nss_tlsmgr_warn("%px: failed to allocate print buffer (req:%zd)", ctx, print_len);
+		return 0;
+	}
+
+	/*
+	 * Walk the context reference tree and retrieve stats
+	 */
+	read_lock_bh(&tun->lock);
+	len = nss_tlsmgr_ctx_print(ctx, buf);
+	read_unlock_bh(&tun->lock);
+
+	len = simple_read_from_buffer(ubuf, sz, ppos, buf, len);
+	vfree(buf);
+
+	return len;
+}
+
+/*
+ * nss_tlsmgr_ctx_rx_stats()
+ *	Asynchronous event for reception of stats
+ */
+void nss_tlsmgr_ctx_rx_stats(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_tls_msg *ntcm = (struct nss_tls_msg *)ncm;
+	struct nss_tlsmgr_ctx *ctx = app_data;
+	struct nss_tlsmgr_tun *tun = netdev_priv(ctx->dev);
+
+	switch (ncm->type) {
+        case NSS_TLS_MSG_TYPE_CTX_SYNC: {
+		struct nss_tls_ctx_stats *sync = &ntcm->msg.stats;
+		uint64_t *fw_stats = (uint64_t *)&ctx->fw_stats;
+		uint32_t *msg_stats = (uint32_t *)sync;
+		int num;
+
+		write_lock(&tun->lock);
+		for (num = 0; num < sizeof(ctx->fw_stats)/sizeof(*fw_stats); num++) {
+			fw_stats[num] += msg_stats[num];
+		}
+
+		write_unlock(&tun->lock);
+		break;
+	}
+
+	default:
+		nss_tlsmgr_info("%px: unhandled tls message type(%u)", ctx, ntcm->cm.type);
+		break;
+	}
+}
+
+/*
+ * nss_tlsmgr_ctx_stats_copy()
+ *	Read context stats into Linux device stats
+ */
+void nss_tlsmgr_ctx_stats_copy(struct nss_tlsmgr_ctx *ctx, struct rtnl_link_stats64 *dev_stats)
+{
+	struct nss_tlsmgr_pkt_stats *stats = &ctx->host_stats;
+	uint64_t *packets, *bytes, *error;
+
+	switch (ctx->di_type) {
+	case NSS_DYNAMIC_INTERFACE_TYPE_TLS_INNER:
+		packets = &dev_stats->tx_packets;
+		bytes = &dev_stats->tx_bytes;
+		error = &dev_stats->rx_errors;
+		break;
+
+	case NSS_DYNAMIC_INTERFACE_TYPE_TLS_OUTER:
+		packets = &dev_stats->rx_packets;
+		bytes = &dev_stats->rx_bytes;
+		error = &dev_stats->rx_errors;
+		break;
+
+	default:
+		return;
+	}
+
+	*packets += stats->rx_packets;
+	*bytes += stats->rx_bytes;
+	*error += stats->rx_errors;
+}
+
+/*
+ * nss_tlsmgr_ctx_rx_inner()
+ *	Process inner from NSS
+ */
+void nss_tlsmgr_ctx_rx_inner(struct net_device *dev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	struct nss_tlsmgr_mdata *mdata = (struct nss_tlsmgr_mdata *)skb->data;
+	struct nss_tlsmgr_mdata_rec *rec_mdata = nss_tlsmgr_mdata_get_rec(mdata, 0);
+	struct nss_tlsmgr_buf *buf = (struct nss_tlsmgr_buf *)skb->head;
+	struct nss_tlsmgr_rec *rec = nss_tlsmgr_buf_get_rec_start(buf);
+	struct nss_tlsmgr_tun *tun = netdev_priv(dev);
+	struct nss_tlsmgr_ctx *ctx = &tun->ctx_enc;
+	struct nss_tlsmgr_mdata_frag *frag_ptr;
+	struct nss_tlsmgr_crypto *crypto;
+	nss_tlsmgr_status_t status;
+	uint8_t frag_cnt;
+	int rec_idx;
+
+	ctx->host_stats.rx_packets++;
+	atomic_dec(&tun->pkt_pending);
+
+	BUG_ON(nss_tlsmgr_mdata_get_magic(mdata) != NSS_TLSMGR_MDATA_MAGIC);
+	BUG_ON(nss_tlsmgr_mdata_get_ver(mdata) != NSS_TLSMGR_MDATA_VER);
+	BUG_ON(nss_tlsmgr_mdata_get_rec_cnt(mdata) > NSS_TLSMGR_MDATA_REC_MAX);
+
+	for (rec_idx = 0; rec_idx < mdata->rec_cnt; rec_idx++, rec_mdata++, rec++) {
+		frag_ptr = nss_tlsmgr_mdata_rec_get_in_frag(rec_mdata);
+		frag_cnt = nss_tlsmgr_mdata_rec_get_in_frags(rec_mdata);
+		nss_tlsmgr_ctx_unmap_frag(ctx, frag_ptr, frag_cnt);
+
+		frag_ptr = nss_tlsmgr_mdata_rec_get_out_frag(rec_mdata);
+		frag_cnt = nss_tlsmgr_mdata_rec_get_out_frags(rec_mdata);
+		nss_tlsmgr_ctx_unmap_frag(ctx, frag_ptr, frag_cnt);
+
+		rec->error = rec_mdata->error;
+	}
+
+	/*
+	 * Peek into crypto active list and schedule detach and free
+	 */
+	if (mdata->flags & NSS_TLSMGR_MDATA_FLAG_CCS) {
+		/*
+		 * Detach from head of an active list and attach to tail of inactive list
+		 * and schedule a delayed free.
+		 */
+		write_lock(&tun->lock);
+		crypto = list_first_entry_or_null(&ctx->crypto_active, struct nss_tlsmgr_crypto, list);
+		if (crypto) {
+			list_del(&crypto->list);
+			list_add_tail(&crypto->list, &tun->free_list);
+		}
+
+		write_unlock(&tun->lock);
+
+		schedule_work(&tun->free_work);
+	}
+
+	if (unlikely(mdata->flags & NSS_TLSMGR_MDATA_FLAG_ERROR)) {
+		status = NSS_TLSMGR_FAIL_TRANSFORM;
+		ctx->host_stats.rx_errors++;
+	}
+
+	nss_tlsmgr_buf_rx(buf, status);
+}
+
+/*
+ * nss_tlsmgr_ctx_rx_outer()
+ *	Process outer from NSS
+ */
+void nss_tlsmgr_ctx_rx_outer(struct net_device *dev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	struct nss_tlsmgr_mdata *mdata = (struct nss_tlsmgr_mdata *)skb->data;
+	struct nss_tlsmgr_mdata_rec *rec_mdata = nss_tlsmgr_mdata_get_rec(mdata, 0);
+	struct nss_tlsmgr_tun *tun = netdev_priv(dev);
+	nss_tlsmgr_status_t status = NSS_TLSMGR_OK;
+	struct nss_tlsmgr_buf *buf = (struct nss_tlsmgr_buf *)skb->head;
+	struct nss_tlsmgr_rec *rec = nss_tlsmgr_buf_get_rec_start(buf);
+	struct nss_tlsmgr_ctx *ctx = &tun->ctx_dec;
+	struct nss_tlsmgr_mdata_frag *frag_ptr;
+	struct nss_tlsmgr_crypto *crypto;
+	uint8_t frag_cnt;
+	int rec_idx;
+
+	BUG_ON(nss_tlsmgr_mdata_get_magic(mdata) != NSS_TLSMGR_MDATA_MAGIC);
+	BUG_ON(nss_tlsmgr_mdata_get_ver(mdata) != NSS_TLSMGR_MDATA_VER);
+	BUG_ON(nss_tlsmgr_mdata_get_rec_cnt(mdata) > NSS_TLSMGR_MDATA_REC_MAX);
+
+	ctx->host_stats.rx_packets++;
+	atomic_dec(&tun->pkt_pending);
+
+	for (rec_idx = 0; rec_idx < mdata->rec_cnt; rec_idx++, rec_mdata++, rec++) {
+		frag_ptr = nss_tlsmgr_mdata_rec_get_in_frag(rec_mdata);
+		frag_cnt = nss_tlsmgr_mdata_rec_get_in_frags(rec_mdata);
+		nss_tlsmgr_ctx_unmap_frag(ctx, frag_ptr, frag_cnt);
+
+		frag_ptr = nss_tlsmgr_mdata_rec_get_out_frag(rec_mdata);
+		frag_cnt = nss_tlsmgr_mdata_rec_get_out_frags(rec_mdata);
+		nss_tlsmgr_ctx_unmap_frag(ctx, frag_ptr, frag_cnt);
+
+		rec->error = rec_mdata->error;
+	}
+
+	/*
+	 * Peek into crypto active list and schedule detach and free
+	 */
+	if (mdata->flags & NSS_TLSMGR_MDATA_FLAG_CCS) {
+		/*
+		 * Detach from head of an active list and attach to tail of inactive list
+		 * and schedule a delayed free.
+		 */
+		write_lock(&tun->lock);
+		crypto = list_first_entry_or_null(&ctx->crypto_active, struct nss_tlsmgr_crypto, list);
+		if (crypto) {
+			list_del(&crypto->list);
+			list_add_tail(&crypto->list, &tun->free_list);
+		}
+
+		write_unlock(&tun->lock);
+
+		schedule_work(&tun->free_work);
+	}
+
+	/*
+	 * check if there is any error reported in mdata.
+	 */
+	if (unlikely(mdata->flags & NSS_TLSMGR_MDATA_FLAG_ERROR)) {
+		status = NSS_TLSMGR_FAIL_TRANSFORM;
+		ctx->host_stats.rx_errors++;
+	}
+
+	nss_tlsmgr_buf_rx(buf, status);
+}
+
+/*
+ * nss_tlsmgr_ctx_fill_mdata()
+ *	Prepare metadata records and fragments
+ */
+static void nss_tlsmgr_ctx_fill_mdata(struct nss_tlsmgr_ctx *ctx, struct nss_tlsmgr_rec *rec,
+					uint8_t *data, uint8_t rec_cnt)
+{
+	struct nss_tlsmgr_mdata *mdata = (struct nss_tlsmgr_mdata *)data;
+	struct nss_tlsmgr_mdata_rec *rec_mdata = nss_tlsmgr_mdata_get_rec(mdata, 0);
+	struct nss_tlsmgr_mdata_frag *infrag_ptr, *outfrag_ptr;
+	uint8_t rec_idx;
+
+	mdata->ver = NSS_TLSMGR_MDATA_VER;
+	mdata->rec_cnt = rec_cnt;
+	mdata->magic = NSS_TLSMGR_MDATA_MAGIC;
+
+	for (rec_idx = 0; rec_idx < mdata->rec_cnt; rec++, rec_mdata++, rec_idx++) {
+		rec_mdata->rec_type = rec->rec_type;
+
+		if (unlikely(rec->rec_type == NSS_TLSMGR_REC_TYPE_CCS))
+			mdata->flags |= NSS_TLSMGR_MDATA_FLAG_CCS;
+
+		infrag_ptr = nss_tlsmgr_mdata_rec_get_in_frag(rec_mdata);
+		outfrag_ptr = nss_tlsmgr_mdata_rec_get_out_frag(rec_mdata);
+		rec_mdata->rec_len = nss_tlsmgr_ctx_map_frag(ctx, rec->in, infrag_ptr, &rec_mdata->in_frags);
+		nss_tlsmgr_ctx_map_frag(ctx, rec->out, outfrag_ptr, &rec_mdata->out_frags);
+
+		mdata->in_frag_cnt += rec_mdata->in_frags;
+		mdata->out_frag_cnt += rec_mdata->out_frags;
+	}
+
+	NSS_TLSMGR_DUMP_MDATA(mdata);
+}
+
+/*
+ * nss_tlsmgr_ctx_tx()
+ *	Transmit API
+ */
+nss_tlsmgr_status_t nss_tlsmgr_ctx_tx(struct nss_tlsmgr_ctx *ctx, struct sk_buff *skb, struct nss_tlsmgr_rec *rec)
+{
+	struct nss_tlsmgr_buf *buf = (struct nss_tlsmgr_buf *)skb->head;
+	struct net_device *dev = ctx->dev;
+	struct nss_tlsmgr_tun *tun = netdev_priv(dev);
+	nss_tx_status_t status;
+
+	nss_tlsmgr_ctx_fill_mdata(ctx, rec, skb->data, buf->rec_cnt);
+
+	nss_tlsmgr_trace("%px: Enqueueing buffer to ctx with interface num(%d)", ctx, ctx->ifnum);
+	status = nss_tls_tx_buf(skb, ctx->ifnum, ctx->nss_ctx);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tlsmgr_warn("%px: Buffer transmission to NSS FW failed, status=%d", buf, status);
+		ctx->host_stats.tx_error++;
+
+		/*
+		 * Reset Device state to be only UP and not RUNNING
+		 */
+		dev->flags &= ~IFF_RUNNING;
+		mod_timer(&tun->decongest.timer, jiffies + tun->decongest.ticks);
+		return (status == NSS_TX_FAILURE_QUEUE) ? NSS_TLSMGR_FAIL_QUEUE_FULL : NSS_TLSMGR_FAIL;
+	}
+
+	ctx->host_stats.tx_packets++;
+
+	atomic_inc(&buf->tun->pkt_pending);
+	return NSS_TLSMGR_OK;
+}
+
+/*
+ * nss_tlsmgr_ctx_deconfig()
+ *	Deconfigure TLS context
+ */
+void nss_tlsmgr_ctx_deconfig(struct nss_tlsmgr_ctx *ctx)
+{
+	struct nss_tlsmgr_tun *tun = netdev_priv(ctx->dev);
+
+	nss_tls_unregister_if(ctx->ifnum);
+	nss_dynamic_interface_dealloc_node(ctx->ifnum, ctx->di_type);
+
+	/*
+	 * Move all active crypto sessions to free list and schedule
+	 * the free work function
+	 */
+	write_lock_bh(&tun->lock);
+	list_splice_tail_init(&ctx->crypto_active, &tun->free_list);
+	write_unlock_bh(&tun->lock);
+
+	schedule_work(&tun->free_work);
+}
+EXPORT_SYMBOL(nss_tlsmgr_ctx_deconfig);
+
+/*
+ * nss_tlsmgr_ctx_config_inner()
+ *	Create TLS Encapsulation context
+ */
+int nss_tlsmgr_ctx_config_inner(struct nss_tlsmgr_ctx *ctx, struct net_device *dev)
+{
+	enum nss_tls_msg_type msg_type = NSS_TLS_MSG_TYPE_CTX_CONFIG;
+	struct nss_tls_ctx_config *ctx_msg;
+	struct nss_tls_msg ntcm;
+	nss_tx_status_t status;
+	int32_t ifnum;
+
+	INIT_LIST_HEAD(&ctx->crypto_active);
+
+	ifnum = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_TLS_INNER);
+	if (ifnum < 0) {
+		nss_tlsmgr_warn("%px: failed to allocate encap dynamic interface(%u)", tlsmgr_drv, ifnum);
+		return -EINVAL;
+	}
+
+	ctx->di_type = NSS_DYNAMIC_INTERFACE_TYPE_TLS_INNER;
+	ctx->ifnum = ifnum;
+	ctx->dev = dev;
+	ctx->print_len = nss_tlsmgr_ctx_stats_size();
+
+	/*
+	 * Register NSS TLS Encap I/F
+	 */
+	ctx->nss_ctx = nss_tls_register_if(ctx->ifnum, nss_tlsmgr_ctx_rx_inner,
+					nss_tlsmgr_ctx_rx_stats, ctx->dev,
+					0, ctx->di_type, (void *)ctx);
+	if (!ctx->nss_ctx) {
+		nss_tlsmgr_warn("%px: NSS register interface(%u) failed", ctx, ctx->ifnum);
+		goto fail_register;
+	}
+
+	ctx->nss_dev = nss_tls_get_dev(ctx->nss_ctx);
+
+	memset(&ctx->fw_stats, 0, sizeof(ctx->fw_stats));
+	memset(&ntcm, 0, sizeof(struct nss_tls_msg));
+
+	ctx_msg = &ntcm.msg.ctx_cfg;
+	ctx_msg->except_ifnum = ifnum;
+
+	status = nss_tls_tx_msg_sync(ctx->nss_ctx, ctx->ifnum, msg_type, sizeof(*ctx_msg), &ntcm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tlsmgr_warn("%px: Failed to configure the context (ctx_type:%u),(tx_status:%d),(error:%x)",
+				ctx, ctx->di_type, status, ntcm.cm.error);
+		goto fail_msg;
+	}
+
+	/*
+	 * This is needed because the NSS firmware can have
+	 * different requirements for headroom and tailroom
+	 * based on chipsets. Hence, load the value supported
+	 * by NSS.
+	 */
+	dev->needed_headroom = ctx_msg->headroom;
+	dev->needed_tailroom = ctx_msg->tailroom;
+
+	/*
+	 * Allocate dummy crypto context in active list
+	 */
+	nss_tlsmgr_crypto_update_null(dev, ctx);
+
+	return 0;
+
+fail_msg:
+	nss_tls_unregister_if(ctx->ifnum);
+fail_register:
+	nss_dynamic_interface_dealloc_node(ifnum, NSS_DYNAMIC_INTERFACE_TYPE_TLS_INNER);
+	return -EINVAL;
+}
+EXPORT_SYMBOL(nss_tlsmgr_ctx_config_inner);
+
+/*
+ * nss_tlsmgr_ctx_config_outer()
+ *	Create TLS Decapsulation context
+ */
+int nss_tlsmgr_ctx_config_outer(struct nss_tlsmgr_ctx *ctx, struct net_device *dev)
+{
+	enum nss_tls_msg_type msg_type = NSS_TLS_MSG_TYPE_CTX_CONFIG;
+	struct nss_tls_ctx_config *ctx_msg;
+	struct nss_tls_msg ntcm;
+	nss_tx_status_t status;
+	int32_t ifnum;
+
+	INIT_LIST_HEAD(&ctx->crypto_active);
+
+	ifnum = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_TLS_OUTER);
+	if (ifnum < 0) {
+		nss_tlsmgr_warn("%px: failed to allocate decap dynamic interface(%u)", tlsmgr_drv, ifnum);
+		return -EINVAL;
+	}
+
+	ctx->di_type = NSS_DYNAMIC_INTERFACE_TYPE_TLS_OUTER;
+	ctx->ifnum = ifnum;
+	ctx->dev = dev;
+	ctx->print_len = nss_tlsmgr_ctx_stats_size();
+
+	/*
+	 * Register NSS TLS Decap I/F
+	 */
+	ctx->nss_ctx = nss_tls_register_if(ctx->ifnum, nss_tlsmgr_ctx_rx_outer,
+					nss_tlsmgr_ctx_rx_stats, ctx->dev,
+					0, ctx->di_type, (void *)ctx);
+	if (!ctx->nss_ctx) {
+		nss_tlsmgr_warn("%px: NSS register interface(%u) failed", ctx, ctx->ifnum);
+		goto fail_register;
+	}
+
+	ctx->nss_dev = nss_tls_get_dev(ctx->nss_ctx);
+
+	memset(&ctx->fw_stats, 0, sizeof(ctx->fw_stats));
+	memset(&ntcm, 0, sizeof(struct nss_tls_msg));
+
+	ctx_msg = &ntcm.msg.ctx_cfg;
+	ctx_msg->except_ifnum = ifnum;
+
+	status = nss_tls_tx_msg_sync(ctx->nss_ctx, ctx->ifnum, msg_type, sizeof(*ctx_msg), &ntcm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tlsmgr_warn("%px: Failed to configure the context (ctx_type:%u),(tx_status:%d),(error:%x)",
+				ctx, ctx->di_type, status, ntcm.cm.error);
+		goto fail_msg;
+	}
+
+	/*
+	 * Allocate dummy crypto context in active list
+	 */
+	nss_tlsmgr_crypto_update_null(dev, ctx);
+
+	return 0;
+
+fail_msg:
+	nss_tls_unregister_if(ctx->ifnum);
+fail_register:
+	nss_dynamic_interface_dealloc_node(ifnum, NSS_DYNAMIC_INTERFACE_TYPE_TLS_INNER);
+	return -EINVAL;
+}
+EXPORT_SYMBOL(nss_tlsmgr_ctx_config_outer);
diff --git a/qca-nss-clients/tls/nss_tlsmgr_ctx.h b/qca-nss-clients/tls/nss_tlsmgr_ctx.h
new file mode 100644
index 0000000..ff49a42
--- /dev/null
+++ b/qca-nss-clients/tls/nss_tlsmgr_ctx.h
@@ -0,0 +1,102 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+/*
+ * nss_tlsmgr_ctx.h
+ */
+
+#ifndef __NSS_TLSMGR_CTX_H_
+#define __NSS_TLSMGR_CTX_H_
+
+#define NSS_TLSMGR_CTX_PRINT_EXTRA 64	/* Bytes */
+
+/*
+ * Context statistics
+ */
+struct nss_tlsmgr_ctx_fw_stats {
+	/* Packet counters */
+	uint64_t rx_packets;                    /* Number of packets received. */
+	uint64_t rx_bytes;                      /* Number of bytes received. */
+	uint64_t tx_packets;                    /* Number of packets transmitted. */
+	uint64_t tx_bytes;                      /* Number of bytes transmitted. */
+	uint64_t rx_dropped[NSS_MAX_NUM_PRI];   /* Packets dropped on receive due to queue full. */
+
+	uint64_t single_rec;			/**< Number of Tx single record datagrams. */
+	uint64_t multi_rec;			/**< Number of multiple Tx record datagrams. */
+	uint64_t tx_inval_reqs;			/**< Number of Tx invalidation successfully requested. */
+	uint64_t rx_ccs_rec;			/**< Number of change cipher spec records received. */
+	uint64_t fail_ccs;			/**< Failed to switch to new crypto. */
+	uint64_t eth_node_deactive;		/**< Ethernet node deactivated as no crypto available. */
+	uint64_t crypto_alloc_success;		/**< Number of crypto allocation. */
+	uint64_t crypto_free_req;		/**< Number of crypto free request. */
+	uint64_t crypto_free_success;		/**< Number of crypto free success. */
+	uint64_t fail_crypto_alloc;		/**< Number of crypto allocation failed. */
+	uint64_t fail_crypto_lookup;		/**< Failed to find acive crypto session. */
+	uint64_t fail_req_alloc;		/**< Failuer to allocate request memory pool.  */
+	uint64_t fail_pbuf_stats;		/**< Failure in pbuf allocation for statistics. */
+	uint64_t fail_ctx_active;		/**< Failure in enqueue due to inactive context. */
+
+	/*
+	 * Dont change the order below
+	 */
+	uint64_t hw_len_error;			/**< Length error. */
+	uint64_t hw_token_error;		/**< Token error, unknown token command/instruction. */
+	uint64_t hw_bypass_error;		/**< Token contains too much bypass data. */
+	uint64_t hw_crypto_error;		/**< Cryptograhic block size error. */
+	uint64_t hw_hash_error;			/**< Hash block size error. */
+	uint64_t hw_config_error;		/**< Invalid command/algorithm/mode/combination. */
+	uint64_t hw_algo_error;			/**< Unsupported algorithm. */
+	uint64_t hw_hash_ovf_error;		/**< Hash input overflow. */
+	uint64_t hw_auth_error;         	/**< Hash input overflow. */
+	uint64_t hw_pad_verify_error;		/**< Pad verification error. */
+	uint64_t hw_timeout_error;              /**< Data timed-out. */
+
+	/*
+	 * Performance statistics
+	 */
+	uint64_t no_desc_in;			/**< Ingress DMA descriptor not available. */
+	uint64_t no_desc_out;			/**< Egress DMA descriptor not available. */
+	uint64_t no_reqs;			/**< Not enough requests available for records. */
+};
+
+/*
+ * TLS context
+ */
+struct nss_tlsmgr_ctx {
+	struct net_device *dev;				/* Tunnel device. */
+	struct device *nss_dev;				/* NSS device. */
+	struct dentry *dentry;  			/* Debugfs directory for ctx statistics. */
+	struct nss_ctx_instance *nss_ctx;		/* NSS context handle. */
+	struct list_head crypto_active;			/* List of active TLS record(s). */
+
+	struct nss_tlsmgr_ctx_fw_stats fw_stats;	/* Context FW Statistics. */
+	struct nss_tlsmgr_pkt_stats host_stats; 	/* Host statistics. */
+	ssize_t print_len;				/* Print buffer lenght. */
+
+	uint32_t ifnum;         			/* NSS interface number. */
+	uint32_t di_type;       			/* Dynamic interface type. */
+};
+
+nss_tlsmgr_status_t nss_tlsmgr_ctx_tx(struct nss_tlsmgr_ctx *ctx, struct sk_buff *skb, struct nss_tlsmgr_rec *rec);
+extern int nss_tlsmgr_ctx_config_inner(struct nss_tlsmgr_ctx *ctx, struct net_device *dev);
+extern int nss_tlsmgr_ctx_config_outer(struct nss_tlsmgr_ctx *ctx, struct net_device *dev);
+extern void nss_tlsmgr_ctx_deconfig(struct nss_tlsmgr_ctx *ctx);
+extern void nss_tlsmgr_ctx_stats_copy(struct nss_tlsmgr_ctx *ctx, struct rtnl_link_stats64 *dev_stats);
+
+ssize_t nss_tlsmgr_ctx_read_stats(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos);
+#endif /* !__NSS_TLSMGR_CTX_H_ */
diff --git a/qca-nss-clients/tls/nss_tlsmgr_mdata.h b/qca-nss-clients/tls/nss_tlsmgr_mdata.h
new file mode 100644
index 0000000..40a5e2d
--- /dev/null
+++ b/qca-nss-clients/tls/nss_tlsmgr_mdata.h
@@ -0,0 +1,204 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+/**
+ * @file nss_tlsmgr_mdata.h
+ *	NSS TLS common metadata definitions.
+ */
+
+#ifndef _NSS_TLSMGR_MDATA_H_
+#define _NSS_TLSMGR_MDATA_H_
+
+#define NSS_TLSMGR_MDATA_VER  0x01  /**< Metadata version. */
+#define NSS_TLSMGR_MDATA_MAGIC  0x8e8f  /**< Metadata magic. */
+
+#define NSS_TLSMGR_MDATA_FRAG_MAX 4
+#define NSS_TLSMGR_MDATA_REC_MAX 4
+#define NSS_TLSMGR_MAX_IN_FRAGS (NSS_TLSMGR_MDATA_REC_MAX * NSS_TLSMGR_MDATA_FRAG_MAX)  /**< Maximum input fragments. */
+#define NSS_TLSMGR_MAX_OUT_FRAGS (NSS_TLSMGR_MDATA_REC_MAX * NSS_TLSMGR_MDATA_FRAG_MAX)	/**< Maximum output fragments. */
+
+#define NSS_TLSMGR_MDATA_FLAG_CCS 0x1
+#define NSS_TLSMGR_MDATA_FLAG_ERROR 0x2
+
+#define NSS_TLSMGR_MDATA_FRAG_FLAG_FIRST 0x1
+#define NSS_TLSMGR_MDATA_FRAG_FLAG_LAST 0x2
+
+/**
+ * nss_tlsmgr_mdata_frag
+ *	TLS fragment information.
+ */
+struct nss_tlsmgr_mdata_frag {
+	uint32_t addr;		/**< Adress of data fragment. */
+	uint16_t len;		/**< Length of data fragment. */
+	uint16_t flags;		/**< Reserved. */
+};
+
+/**
+ * nss_tlsmgr_mdata_rec
+ *	TLS record information.
+ */
+struct nss_tlsmgr_mdata_rec {
+	uint16_t rec_len;					/**< Length of payload in this record. */
+	uint8_t rec_type;					/**< Type of record. */
+	uint8_t error; 						/* Transform error codes */
+	uint8_t in_frags;					/**< Number of input fragments. */
+	uint8_t out_frags;					/**< Number of output fragments. */
+	uint8_t res[2]; 					/**< Reserved. */
+	struct nss_tlsmgr_mdata_frag in[NSS_TLSMGR_MDATA_FRAG_MAX];	/**< Input fragments. */
+	struct nss_tlsmgr_mdata_frag out[NSS_TLSMGR_MDATA_FRAG_MAX];	/**< Output fragments. */
+};
+
+/**
+ * nss_tlsmgr_mdata
+ *	TLS metadata.
+ */
+struct nss_tlsmgr_mdata {
+	uint8_t  ver;		/**< Metadata version. */
+	uint8_t rec_cnt;	/**< Total number of records. */
+	uint8_t in_frag_cnt;	/**< Total number of input fragments. */
+	uint8_t out_frag_cnt;	/**< Total number of output fragments. */
+	uint32_t flags;		/**< Transformation flags. */
+	uint8_t res[2];		/**< Reserved. */
+	uint16_t magic;         /**< Meta data magic. */
+	struct nss_tlsmgr_mdata_rec rec[NSS_TLSMGR_MDATA_REC_MAX];	/**< Records structure. */
+};
+
+/*
+ * nss_tlsmgr_mdata_get_ver()
+ *	Get TLS metadata Version.
+ */
+static inline uint8_t nss_tlsmgr_mdata_get_ver(struct nss_tlsmgr_mdata *ntm)
+{
+	return ntm->ver;
+}
+
+/*
+ * nss_tlsmgr_mdata_get_magic()
+ *	Get TLS metadata Magic.
+ */
+static inline uint16_t nss_tlsmgr_mdata_get_magic(struct nss_tlsmgr_mdata *ntm)
+{
+	return ntm->magic;
+}
+
+/*
+ * nss_tlsmgr_mdata_get_rec_cnt()
+ *	Get TLS metadata record count.
+ */
+static inline uint8_t nss_tlsmgr_mdata_get_rec_cnt(struct nss_tlsmgr_mdata *ntm)
+{
+	return ntm->rec_cnt;
+}
+
+/*
+ * nss_tlsmgr_mdata_get_rec()
+ *	Get start of record.
+ */
+static inline struct nss_tlsmgr_mdata_rec *nss_tlsmgr_mdata_get_rec(struct nss_tlsmgr_mdata *ntm, uint8_t idx)
+{
+	return &ntm->rec[idx];
+}
+
+/*
+ * nss_tlsmgr_mdata_get_rec_len()
+ *	Get record length.
+ */
+static inline uint16_t nss_tlsmgr_mdata_rec_get_rec_len(struct nss_tlsmgr_mdata_rec *ntmr)
+{
+	return ntmr->rec_len;
+}
+
+/*
+ * nss_tlsmgr_mdata_get_rec_type()
+ *	Get record type.
+ */
+static inline uint8_t nss_tlsmgr_mdata_rec_get_rec_type(struct nss_tlsmgr_mdata_rec *ntmr)
+{
+	return ntmr->rec_type;
+}
+
+/*
+ * nss_tlsmgr_mdata_rec_get_error()
+ *	Get error status from metadata.
+ */
+static inline uint8_t nss_tlsmgr_mdata_rec_get_error(struct nss_tlsmgr_mdata_rec *ntmr)
+{
+	return ntmr->error;
+}
+
+/*
+ * nss_tlsmgr_mdata_rec_get_in_frags()
+ *	Get total number of input fragments.
+ */
+static inline uint8_t nss_tlsmgr_mdata_rec_get_in_frags(struct nss_tlsmgr_mdata_rec *ntmr)
+{
+	return ntmr->in_frags;
+}
+
+/*
+ * nss_tlsmgr_mdata_rec_get_out_frags()
+ *	Get total number of output fragments.
+ */
+static inline uint8_t nss_tlsmgr_mdata_rec_get_out_frags(struct nss_tlsmgr_mdata_rec *ntmr)
+{
+	return ntmr->out_frags;
+}
+
+/*
+ * nss_tlsmgr_mdata_rec_get_in_frag()
+ *	Get start of input fragment.
+ */
+static inline struct nss_tlsmgr_mdata_frag *nss_tlsmgr_mdata_rec_get_in_frag(struct nss_tlsmgr_mdata_rec *ntmr)
+{
+	return ntmr->in;
+}
+
+/*
+ * nss_tlsmgr_mdata_rec_get_out_frag()
+	int error;
+ *	Get start of output fragment.
+ */
+static inline struct nss_tlsmgr_mdata_frag *nss_tlsmgr_mdata_rec_get_out_frag(struct nss_tlsmgr_mdata_rec *ntmr)
+{
+	return ntmr->out;
+}
+
+/*
+ * nss_tlsmgr_mdata_rec_verify_idx()
+ *	Check if record index is out of range.
+ */
+static inline bool nss_tlsmgr_mdata_rec_verify_idx(uint8_t idx)
+{
+	return idx > NSS_TLSMGR_MDATA_REC_MAX;
+}
+
+/*
+ * nss_tlsmgr_mdata_frag_is_overflow()
+ *	Check if fragment index is out of range.
+ */
+static inline bool nss_tlsmgr_mdata_frag_verify_count(uint8_t frag_cnt)
+{
+	return frag_cnt > NSS_TLSMGR_MDATA_FRAG_MAX;
+}
+
+/**
+ * @}
+ */
+#endif /* _NSS_TLSMGR_MDATA_H_ */
+
+
diff --git a/qca-nss-clients/tls/nss_tlsmgr_priv.h b/qca-nss-clients/tls/nss_tlsmgr_priv.h
new file mode 100644
index 0000000..6acf291
--- /dev/null
+++ b/qca-nss-clients/tls/nss_tlsmgr_priv.h
@@ -0,0 +1,96 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+/*
+ * nss_tlsmgr_priv.h
+ */
+
+#ifndef __NSS_TLSMGR_PRIV_H_
+#define __NSS_TLSMGR_PRIV_H_
+
+#define NSS_TLSMGR_DEBUG_LEVEL_ERROR 1
+#define NSS_TLSMGR_DEBUG_LEVEL_WARN 2
+#define NSS_TLSMGR_DEBUG_LEVEL_INFO 3
+#define NSS_TLSMGR_DEBUG_LEVEL_TRACE 4
+
+#define nss_tlsmgr_info_always(s, ...) pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__)
+
+#define nss_tlsmgr_error(s, ...) do {	\
+	if (net_ratelimit()) {	\
+		pr_alert("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+} while (0)
+
+#define nss_tlsmgr_warn(s, ...) do {	\
+	if (net_ratelimit()) {	\
+		pr_warn("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__);	\
+	}	\
+} while (0)
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_tlsmgr_info(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__)
+#define nss_tlsmgr_trace(s, ...) pr_debug("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__)
+#else
+
+#define nss_tlsmgr_info(s, ...) {	\
+	if (NSS_TLSMGR_DEBUG_LEVEL > NSS_TLSMGR_DEBUG_LEVEL_WARN)	\
+		pr_notice("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__)	\
+}
+
+#define nss_tlsmgr_trace(s, ...) {	\
+	if (NSS_TLSMGR_DEBUG_LEVEL > NSS_TLSMGR_DEBUG_LEVEL_INFO)	\
+		pr_info("%s[%d]:" s "\n", __func__, __LINE__, ##__VA_ARGS__)	\
+}
+
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+#define NSS_TLSMGR_PRINT_PAGES 2
+#define NSS_TLSMGR_PRINT_BYTES(bytes) ((((bytes) * BITS_PER_BYTE) / 4) + 4)
+#define NSS_TLSMGR_PRINT_DWORD NSS_TLSMGR_PRINT_BYTES(8)
+#define NSS_TLSMGR_PRINT_WORD NSS_TLSMGR_PRINT_BYTES(4)
+#define NSS_TLSMGR_PRINT_SHORT NSS_TLSMGR_PRINT_BYTES(2)
+#define NSS_TLSMGR_PRINT_BYTE NSS_TLSMGR_PRINT_BYTES(1)
+#define NSS_TLSMGR_PRINT_IPADDR (NSS_TLSMGR_PRINT_WORD * 4)
+#define NSS_TLSMGR_PRINT_EXTRA 64      /* Bytes */
+
+/*
+ * Statistics dump information
+ */
+struct nss_tlsmgr_print {
+	char *str;              /* Name of variable. */
+	ssize_t var_size;       /* Size of variable in bytes. */
+};
+
+/*
+ * TLS manager data
+ */
+struct nss_tlsmgr {
+	atomic_t is_configured;			/* Firmware is configured. */
+	rwlock_t lock;				/* Tunnel lock. */
+
+	ssize_t print_len;			/* Print buffer length. */
+	ssize_t stats_len;			/* Statistics length. */
+
+	struct dentry *dentry;			/* Debugfs root directory. */
+	struct nss_tls_node_stats stats;	/* Node statistics. */
+	struct nss_ctx_instance *nss_ctx;	/* NSS data/message handle. */
+};
+
+extern struct nss_tlsmgr *tlsmgr_drv;
+
+#endif /* !__NSS_TLSMGR_PRIV_H_ */
diff --git a/qca-nss-clients/tls/nss_tlsmgr_tun.c b/qca-nss-clients/tls/nss_tlsmgr_tun.c
new file mode 100644
index 0000000..0e4eb1c
--- /dev/null
+++ b/qca-nss-clients/tls/nss_tlsmgr_tun.c
@@ -0,0 +1,468 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+/*
+ * nss_tlsmgr_tun.c
+ *	NSS TLS Manager tunnel onbject
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/debugfs.h>
+#include <linux/rtnetlink.h>
+#include <net/ipv6.h>
+#include <linux/if_arp.h>
+#include <linux/etherdevice.h>
+#include <linux/atomic.h>
+#include <linux/tlshdr.h>
+#include <crypto/aes.h>
+#include <crypto/sha.h>
+
+#include <nss_api_if.h>
+#include <nss_dynamic_interface.h>
+
+#include <nss_tls.h>
+#include <nss_tlsmgr.h>
+#include "nss_tlsmgr_priv.h"
+#include "nss_tlsmgr_ctx.h"
+#include "nss_tlsmgr_crypto.h"
+#include "nss_tlsmgr_tun.h"
+
+/*
+ * nss_tlsmgr_tun_get_headroom()
+ *	Get headroom required for encapsulation.
+ */
+uint16_t nss_tlsmgr_tun_get_headroom(struct net_device *dev)
+{
+	return dev->needed_headroom;
+}
+EXPORT_SYMBOL(nss_tlsmgr_tun_get_headroom);
+
+/*
+ * nss_tlsmgr_tun_get_tailroom()
+ *	Get tailroom required for encapsulation.
+ */
+uint16_t nss_tlsmgr_tun_get_tailroom(struct net_device *dev)
+{
+	return dev->needed_tailroom;
+}
+EXPORT_SYMBOL(nss_tlsmgr_tun_get_tailroom);
+
+/*
+ * nss_tlsmgr_tun_tx()
+ *	Transmit packet to TLS node in NSS firmware.
+ */
+static netdev_tx_t nss_tlsmgr_tun_tx(struct sk_buff *skb, struct net_device *dev)
+{
+	nss_tlsmgr_warn("%px: TLS device xmit function invoked", dev);
+	dev_kfree_skb_any(skb);
+	return NETDEV_TX_OK;
+}
+
+/*
+ * nss_tlsmgr_tun_close()
+ *	Stop packet transmission on the TLS network device.
+ */
+static int nss_tlsmgr_tun_close(struct net_device *dev)
+{
+	netif_stop_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_tlsmgr_tun_open()
+ *	Start processing packets on the TLS network device.
+ */
+static int nss_tlsmgr_tun_open(struct net_device *dev)
+{
+	netif_start_queue(dev);
+	return 0;
+}
+
+/*
+ * nss_tlsmgr_tun_stats64()
+ *	TLS manager tunnel device
+ */
+static struct rtnl_link_stats64 *nss_tlsmgr_get_tun_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	struct nss_tlsmgr_tun *tun = netdev_priv(dev);
+
+	memset(stats, 0, sizeof(*stats));
+
+	read_lock_bh(&tun->lock);
+	nss_tlsmgr_ctx_stats_copy(&tun->ctx_enc, stats);
+	nss_tlsmgr_ctx_stats_copy(&tun->ctx_dec, stats);
+	read_unlock_bh(&tun->lock);
+
+	return stats;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0))
+/*
+ * nss_tlsmgr_tun_stats64()
+ * 	Netdev ops function to retrieve stats for kernel version < 4.6
+ */
+static struct rtnl_link_stats64 *nss_tlsmgr_tun_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	return nss_tlsmgr_get_tun_stats64(dev, stats);
+}
+#else
+/*
+ * nss_tlsmgr_tun_stats64()
+ * 	Netdev ops function to retrieve stats for kernel version >= 4.6
+ */
+static void nss_tlsmgr_tun_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
+{
+	nss_tlsmgr_get_tun_stats64(dev, stats);
+}
+#endif
+
+/*
+ * nss_tlsmgr_tun_change_mtu()
+ *	Change MTU size of TLS context device.
+ */
+static int32_t nss_tlsmgr_tun_change_mtu(struct net_device *dev, int32_t mtu)
+{
+	/*
+	 * TODO: Send a ETH_NODE message to firmware for updating the MTU
+	 */
+	dev->mtu = mtu;
+	return 0;
+}
+
+/*
+ * TLS netdev ops
+ */
+static const struct net_device_ops nss_tlsmgr_tun_ops = {
+	.ndo_start_xmit = nss_tlsmgr_tun_tx,
+	.ndo_open = nss_tlsmgr_tun_open,
+	.ndo_stop = nss_tlsmgr_tun_close,
+	.ndo_get_stats64 = nss_tlsmgr_tun_stats64,
+	.ndo_change_mtu = nss_tlsmgr_tun_change_mtu,
+};
+
+/*
+ * nss_tlsmgr_tun_setup()
+ *	setup the TLS tunnel
+ */
+static void nss_tlsmgr_tun_setup(struct net_device *dev)
+{
+	dev->addr_len = ETH_ALEN;
+	dev->mtu = ETH_DATA_LEN;
+	dev->hard_header_len = 0;
+
+	dev->type = ARPHRD_TUNNEL;
+	dev->ethtool_ops = NULL;
+	dev->header_ops = NULL;
+
+	dev->netdev_ops = &nss_tlsmgr_tun_ops;
+
+	/*
+	 * Get the MAC address from the ethernet device
+	 */
+	random_ether_addr(dev->dev_addr);
+
+	memset(dev->broadcast, 0xff, dev->addr_len);
+	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
+}
+
+/*
+ * nss_tlsmgr_tun_delayed_free()
+ *	Delayed worker function to free TLS session.
+ */
+static void nss_tlsmgr_tun_free_work(struct work_struct *work)
+{
+	struct nss_tlsmgr_tun *tun = container_of(work, struct nss_tlsmgr_tun, free_work);
+	struct nss_tlsmgr_crypto *cur, *tmp;
+	struct list_head tmp_head;
+
+	write_lock_bh(&tun->lock);
+	INIT_LIST_HEAD(&tmp_head);
+	list_splice_tail_init(&tun->free_list, &tmp_head);
+	write_unlock_bh(&tun->lock);
+
+	list_for_each_entry_safe(cur, tmp, &tmp_head, list) {
+		list_del(&cur->list);
+		nss_tlsmgr_crypto_free(cur);
+	}
+
+	read_lock_bh(&tun->lock);
+	if (!list_empty(&tun->free_list))
+		schedule_work(&tun->free_work);
+	read_unlock_bh(&tun->lock);
+}
+
+
+/*
+ * nss_tlsmgr_notify_event()
+ *	TLS manager notification timer handler
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0))
+static void nss_tlsmgr_notify_event(unsigned long data)
+#else
+static void nss_tlsmgr_notify_event(struct timer_list *tm)
+#endif
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0))
+	struct nss_tlsmgr_tun *tun = (struct nss_tlsmgr_tun *)data;
+#else
+	struct nss_tlsmgr_tun *tun = from_timer(tun, tm, notify.timer);
+#endif
+	nss_tlsmgr_notify_callback_t cb;
+	struct nss_tlsmgr_stats stats;
+	void *app_data;
+
+	read_lock_bh(&tun->lock);
+	stats.encap = tun->ctx_enc.host_stats;
+	stats.decap = tun->ctx_dec.host_stats;
+	cb = tun->notify.cb;
+	app_data = tun->notify.app_data;
+	read_unlock_bh(&tun->lock);
+
+	if (cb) {
+		cb(app_data, tun->dev, &stats);
+		mod_timer(&tun->notify.timer, jiffies + tun->notify.ticks);
+	}
+}
+
+/*
+ * nss_tlsmgr_notify_decongestion()
+ *	TLS manager decongestion notification
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0))
+static void nss_tlsmgr_notify_decongestion(unsigned long data)
+#else
+static void nss_tlsmgr_notify_decongestion(struct timer_list *tm)
+#endif
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0))
+	struct nss_tlsmgr_tun *tun = (struct nss_tlsmgr_tun *)data;
+#else
+	struct nss_tlsmgr_tun *tun = from_timer(tun, tm, notify.timer);
+#endif
+	nss_tlsmgr_decongest_callback_t cb;
+	void *app_data;
+
+	if (atomic_read(&tun->pkt_pending)) {
+		mod_timer(&tun->decongest.timer, jiffies + tun->decongest.ticks);
+		return;
+	}
+
+	BUG_ON(tun->dev->flags & IFF_RUNNING);
+
+	read_lock_bh(&tun->lock);
+	cb = tun->decongest.cb;
+	app_data = tun->decongest.app_data;
+	read_unlock_bh(&tun->lock);
+
+	/*
+	 * Mark device as RUNNING again before notifying the application
+	 * to start transmitting again
+	 */
+	tun->dev->flags |= IFF_RUNNING;
+
+	if (cb) {
+		cb(app_data, tun->dev);
+	}
+}
+
+/*
+ * nss_tlsmgr_register_notify()
+ *	TLS Manager notification register
+ */
+bool nss_tlsmgr_register_notify(struct net_device *dev, nss_tlsmgr_notify_callback_t cb,
+					void *app_data, uint32_t msecs)
+{
+	struct nss_tlsmgr_tun *tun = netdev_priv(dev);
+
+	if (!cb || !msecs) {
+		nss_tlsmgr_warn("%px: NULL notification parameters %px %d\n", tun, cb, msecs);
+		return false;
+	};
+
+	write_lock_bh(&tun->lock);
+	tun->notify.ticks = msecs_to_jiffies(msecs);
+	tun->notify.app_data = app_data;
+	tun->notify.cb = cb;
+	write_unlock_bh(&tun->lock);
+
+	mod_timer(&tun->notify.timer, jiffies + tun->notify.ticks);
+	return true;
+}
+EXPORT_SYMBOL(nss_tlsmgr_register_notify);
+
+/*
+ * nss_tlsmgr_unregister_notify()
+ *	TLS Manager notification unregister
+ */
+void nss_tlsmgr_unregister_notify(struct net_device *dev)
+{
+	struct nss_tlsmgr_tun *tun = netdev_priv(dev);
+
+	write_lock_bh(&tun->lock);
+	tun->notify.app_data = NULL;
+	tun->notify.cb = NULL;
+	tun->notify.ticks = 0;
+	write_unlock_bh(&tun->lock);
+
+	BUG_ON(in_atomic());
+	del_timer_sync(&tun->notify.timer);
+}
+
+/*
+ * file operation structure instance
+ */
+const struct file_operations tlsmgr_ctx_file_ops = {
+	.open = simple_open,
+	.llseek = default_llseek,
+	.read = nss_tlsmgr_ctx_read_stats,
+};
+
+/*
+ * nss_tlsmgr_tun_add()
+ *	Create TLS tunnel device and dynamic interface
+ */
+struct net_device *nss_tlsmgr_tun_add(nss_tlsmgr_decongest_callback_t cb, void *app_data)
+{
+	struct nss_tlsmgr_tun *tun;
+	struct net_device *dev;
+	int error;
+
+	if (!atomic_read(&tlsmgr_drv->is_configured)) {
+		nss_tlsmgr_warn("%px: tls firmware not ready", tlsmgr_drv);
+		return NULL;
+	}
+
+	dev = alloc_netdev(sizeof(*tun), "tls%d", NET_NAME_ENUM, nss_tlsmgr_tun_setup);
+	if (!dev) {
+		nss_tlsmgr_warn("%px: unable to allocate tls device", tun);
+		return NULL;
+	}
+
+	tun = netdev_priv(dev);
+	tun->dev = dev;
+	rwlock_init(&tun->lock);
+
+	error = nss_tlsmgr_ctx_config_inner(&tun->ctx_enc, dev);
+	if (error < 0) {
+		nss_tlsmgr_warn("%px: unable to create encap context, error(%d)", tun, error);
+		goto free_dev;
+	}
+
+	error = nss_tlsmgr_ctx_config_outer(&tun->ctx_dec, dev);
+	if (error < 0) {
+		nss_tlsmgr_warn("%px: unable to create decap context, error(%d)", tun, error);
+		goto deconfig_inner;
+	}
+
+	error = rtnl_is_locked() ? register_netdevice(dev) : register_netdev(dev);
+	if (error < 0) {
+		nss_tlsmgr_warn("%px: unable register net_device(%s)", tun, dev->name);
+		goto deconfig_outer;
+	}
+
+	nss_tlsmgr_trace("%px: tls tunnel(%s) created, encap(%u), decap(%u)",
+			  tun, dev->name, tun->ctx_enc.ifnum, tun->ctx_dec.ifnum);
+
+	/*
+	 * Initialize tunnel decongestion
+	 */
+	tun->decongest.ticks = msecs_to_jiffies(NSS_TLSMGR_TUN_DECONGEST_TICKS);
+	tun->decongest.app_data = app_data;
+	tun->decongest.cb = cb;
+
+	/*
+	 * Initialize Event notification and Decongestion timer
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0))
+	init_timer(&tun->notify.timer);
+	tun->notify.timer.function = nss_tlsmgr_notify_event;
+	tun->notify.timer.data = (unsigned long)tun;
+
+	init_timer(&tun->decongest.timer);
+	tun->decongest.timer.function = nss_tlsmgr_notify_decongestion;
+	tun->decongest.timer.data = (unsigned long)tun;
+#else
+	timer_setup(&tun->notify.timer, nss_tlsmgr_notify_event, 0);
+	timer_setup(&tun->decongest.timer, nss_tlsmgr_notify_decongestion, 0);
+#endif
+
+	INIT_LIST_HEAD(&tun->free_list);
+	INIT_WORK(&tun->free_work, nss_tlsmgr_tun_free_work);
+
+	/*
+	 * Create debugfs entry for tunnel and its child context(s)
+	 */
+	tun->dentry = debugfs_create_dir(dev->name, tlsmgr_drv->dentry);
+	if (tun->dentry) {
+		debugfs_create_file("inner", S_IRUGO, tun->dentry, &tun->ctx_enc, &tlsmgr_ctx_file_ops);
+		debugfs_create_file("outer", S_IRUGO, tun->dentry, &tun->ctx_dec, &tlsmgr_ctx_file_ops);
+	}
+
+	/*
+	 * Mark device as UP and Running
+	 */
+	dev->flags = IFF_UP | IFF_RUNNING;
+
+	return dev;
+
+deconfig_outer:
+	nss_tlsmgr_ctx_deconfig(&tun->ctx_dec);
+
+deconfig_inner:
+	nss_tlsmgr_ctx_deconfig(&tun->ctx_enc);
+
+free_dev:
+	free_netdev(dev);
+	return NULL;
+}
+EXPORT_SYMBOL(nss_tlsmgr_tun_add);
+
+/*
+ * nss_tlsmgr_tun_del()
+ *	Delete TLS tunnel
+ */
+void nss_tlsmgr_tun_del(struct net_device *dev)
+{
+	struct nss_tlsmgr_tun *tun = netdev_priv(dev);
+
+	nss_tlsmgr_trace("%px: destroying encap(%u) and decap(%u) context",
+			  tun, tun->ctx_enc.ifnum, tun->ctx_dec.ifnum);
+
+	debugfs_remove_recursive(tun->dentry);
+
+	nss_tlsmgr_unregister_notify(dev);
+
+	del_timer_sync(&tun->decongest.timer);
+	tun->decongest.app_data = NULL;
+	tun->decongest.cb = NULL;
+	tun->decongest.ticks = 0;
+
+	nss_tlsmgr_ctx_deconfig(&tun->ctx_enc);
+	nss_tlsmgr_ctx_deconfig(&tun->ctx_dec);
+
+	schedule_work(&tun->free_work);
+	flush_work(&tun->free_work);
+
+	rtnl_is_locked() ? unregister_netdevice(dev) : unregister_netdev(dev);
+}
+EXPORT_SYMBOL(nss_tlsmgr_tun_del);
diff --git a/qca-nss-clients/tls/nss_tlsmgr_tun.h b/qca-nss-clients/tls/nss_tlsmgr_tun.h
new file mode 100644
index 0000000..5d2c159
--- /dev/null
+++ b/qca-nss-clients/tls/nss_tlsmgr_tun.h
@@ -0,0 +1,70 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+/*
+ * nss_tlsmgr_tun.h
+ */
+
+#ifndef __NSS_TLSMGR_TUN_H_
+#define __NSS_TLSMGR_TUN_H_
+
+#define NSS_TLSMGR_MAX_HDR_SZ \
+	(sizeof(struct ipv6hdr) + sizeof(struct tcphdr) + sizeof(struct tlshdr) + AES_BLOCK_SIZE)
+#define NSS_TLSMGR_MAX_TRAILER_SZ (AES_BLOCK_SIZE + SHA256_DIGEST_SIZE + 1)
+#define NSS_TLSMGR_MAX_HEADROOM NSS_TLSMGR_MAX_HDR_SZ
+#define NSS_TLSMGR_MAX_TAILROOM NSS_TLSMGR_MAX_TRAILER_SZ
+
+#define NSS_TLSMGR_TUN_DECONGEST_TICKS 100
+
+/*
+ * Tunnel Event notification
+ */
+struct nss_tlsmgr_notify {
+	nss_tlsmgr_notify_callback_t cb; 	/* Callback function */
+	struct timer_list timer; 		/* Timer for invoking the callback */
+	unsigned long ticks; 			/* User programmed time interval */
+	void *app_data; 			/* Callback context */
+};
+
+/*
+ * Decongestion Event notification
+ */
+struct nss_tlsmgr_decongest {
+	nss_tlsmgr_decongest_callback_t cb;	/* Callback function */
+	struct timer_list timer; 		/* Timer for invoking the callback */
+	unsigned long ticks; 			/* User programmed time interval */
+	void *app_data; 			/* Callback context */
+};
+
+/*
+ * TLS tunnel object
+ */
+struct nss_tlsmgr_tun  {
+	struct net_device *dev;   			/* Tunnel netdevice. */
+	rwlock_t lock;					/* Tunnel lock. */
+	atomic_t pkt_pending;				/* Packets not retured to host. */
+	struct dentry *dentry;    			/* Debugfs directory for tunnel stats. */
+	struct list_head free_list;			/* List of inactive TLS record(s). */
+	struct work_struct free_work;			/* Work scheduled for deletion. */
+	struct nss_tlsmgr_notify notify; 		/* Period notification to user */
+	struct nss_tlsmgr_decongest decongest;		/* Decongestion notification to user */
+	struct nss_tlsmgr_ctx ctx_enc;     		/* Encapsulation context. */
+	struct nss_tlsmgr_ctx ctx_dec;			/* Decapsulation context. */
+};
+
+#endif /* !__NSS_TLSMGR_TUN_H_ */
diff --git a/qca-nss-clients/tunipip6/Makefile b/qca-nss-clients/tunipip6/Makefile
new file mode 100644
index 0000000..5f3a8e0
--- /dev/null
+++ b/qca-nss-clients/tunipip6/Makefile
@@ -0,0 +1,10 @@
+# Makefile for tunipip6 client
+ccflags-y += -I$(obj)/../exports -I$(obj)/..
+ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)"
+ccflags-y += -DNSS_TUNIPIP6_DEBUG_LEVEL=0
+ccflags-y += -Wall -Werror
+obj-m += qca-nss-tunipip6.o
+qca-nss-tunipip6-objs := nss_connmgr_tunipip6.o nss_connmgr_tunipip6_sysctl.o nss_connmgr_tunipip6_stats.o
+ifneq ($(findstring 4.4, $(KERNELVERSION)),)
+ccflags-y += -DDRAFT03_SUPPORT
+endif
diff --git a/qca-nss-clients/tunipip6/nss_connmgr_tunipip6.c b/qca-nss-clients/tunipip6/nss_connmgr_tunipip6.c
new file mode 100644
index 0000000..0a03a7d
--- /dev/null
+++ b/qca-nss-clients/tunipip6/nss_connmgr_tunipip6.c
@@ -0,0 +1,1183 @@
+ /*
+ **************************************************************************
+ * Copyright (c) 2014, 2017-2018, 2020 The Linux Foundation. All rights reserved.
+
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+#include <net/ip.h>
+#include <net/ipv6.h>
+#include <linux/if.h>
+#include <net/ip_tunnels.h>
+#include <net/ip6_tunnel.h>
+#include <nss_api_if.h>
+#include "nss_connmgr_tunipip6.h"
+#include "nss_connmgr_tunipip6_sysctl.h"
+#include "nss_connmgr_tunipip6_priv.h"
+
+#define NSS_TUNIPIP6_MAX_FMR 255	/* Maximum number of forward mapping rule (FMR). */
+
+/*
+ * Frag Id update is disabled by default
+ */
+bool frag_id_update = false;
+/*
+ * Creating custom ipip6 interface is disabled by default.
+ */
+static bool enable_custom;
+module_param(enable_custom, bool, 0);
+
+/*
+ * tunipip6 global context.
+ */
+struct nss_tunipip6_context tunipip6_ctx;
+
+/*
+ * nss_tunipip6_alloc_instance()
+ * 	Allocate tunipip6 interface instance.
+ */
+static struct nss_tunipip6_instance *nss_tunipip6_alloc_instance(struct net_device *dev,
+					int inner_ifnum,
+					int outer_ifnum)
+{
+	struct nss_tunipip6_instance*ntii;
+
+	ntii = vzalloc(sizeof(*ntii));
+	if (!ntii) {
+		nss_tunipip6_warning("%px: Not able to allocate tunipip6 instance\n", dev);
+		return NULL;
+	}
+
+	ntii->dev = dev;
+
+	/*
+	 * Create statistics dentry.
+	 */
+	if (!nss_tunipip6_stats_dentry_create(ntii)) {
+		vfree(ntii);
+		nss_tunipip6_warning("%px: Not able to create tunipip6 statistics dentry\n", dev);
+		return NULL;
+	}
+
+	INIT_LIST_HEAD(&ntii->list);
+	ntii->inner_ifnum = inner_ifnum;
+	ntii->outer_ifnum = outer_ifnum;
+	dev_hold(dev);
+	return ntii;
+}
+
+/*
+ * nss_tunipip6_free_instance()
+ * 	Delete the tunipip6 interface instance from the list and free it.
+ *
+ * Note: tunnel list lock is expected to be held by the caller.
+ */
+static void nss_tunipip6_free_instance(struct nss_tunipip6_instance *ntii)
+{
+	if (!list_empty(&ntii->list)) {
+		list_del(&ntii->list);
+	}
+
+	vfree(ntii);
+}
+
+/*
+ * nss_tunipip6_find_instance()
+ * 	Find tunipip6 interface instance from list.
+ *
+ * Note: tunnel list lock is expected to be held by the caller.
+ */
+struct nss_tunipip6_instance *nss_tunipip6_find_instance(struct net_device *dev)
+{
+	struct nss_tunipip6_instance *ntii;
+
+	/*
+	 * Check if dev instance is in the list
+	 */
+	list_for_each_entry(ntii, &tunipip6_ctx.dev_list, list) {
+		if (ntii->dev == dev) {
+			return ntii;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_tunipip6_find_and_free_instance()
+ * 	Find and free the tunipip6 instance.
+ */
+static enum nss_connmgr_tunipip6_err_codes nss_tunipip6_find_and_free_instance(struct net_device *netdev)
+{
+	struct dentry *dentry;
+	struct nss_tunipip6_instance *ntii;
+
+	spin_lock_bh(&tunipip6_ctx.lock);
+	ntii = nss_tunipip6_find_instance(netdev);
+	if (!ntii) {
+		spin_unlock_bh(&tunipip6_ctx.lock);
+		nss_tunipip6_warning("%px: Not able to find tunipip6 instance for dev:%s\n", netdev, netdev->name);
+		return NSS_CONNMGR_TUNIPIP6_CONTEXT_FAILURE;
+	}
+
+	dentry = ntii->dentry;
+	nss_tunipip6_free_instance(ntii);
+	spin_unlock_bh(&tunipip6_ctx.lock);
+	debugfs_remove(dentry);
+	dev_put(netdev);
+	return NSS_CONNMGR_TUNIPIP6_SUCCESS;
+}
+
+/*
+ * nss_tunipip6_encap_exception()
+ *	Exception handler registered to NSS driver.
+ *
+ * This function is called when no rule is found for successful encapsulation.
+ */
+static void nss_tunipip6_encap_exception(struct net_device *dev, struct sk_buff *skb, __attribute__((unused)) struct napi_struct *napi)
+{
+	const struct net_device_ops *ops = dev->netdev_ops;
+	struct netdev_queue *queue;
+	struct iphdr *iph;
+	struct rtable *rt;
+	int cpu;
+
+	if (unlikely(!pskb_may_pull(skb, sizeof(struct iphdr)))) {
+		nss_tunipip6_warning("%px: skb: %px, pskb_may_pull failed to linearize iphdr, packet does not have a proper IPv4 header.", dev, skb);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	skb_reset_network_header(skb);
+
+	iph = ip_hdr(skb);
+	nss_tunipip6_assert(iph->version == IPVERSION);
+
+	nss_tunipip6_info("%px: received - %d bytes name %s ver %x\n",
+			skb, skb->len, dev->name, iph->version);
+
+	rt = ip_route_output(&init_net, iph->daddr, 0, 0, 0);
+	if (unlikely(IS_ERR(rt))) {
+		nss_tunipip6_info("%px: Failed to find IPv4 route for dest %pI4 src %pI4\n", skb, &iph->daddr, &iph->saddr);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	nss_tunipip6_trace("%px: Route look up successful for dest_ip: %pI4 src_ip: %pI4 dest dev:%s\n",
+			skb, &iph->daddr, &iph->saddr, rt->dst.dev->name);
+
+	/*
+	 * Send decap direction packets to stack using netif_receive_skb
+	 * NOTE: if tunnel to tunnel traffic is enabled, then this might fail.
+	 */
+	if (rt->dst.dev->type != ARPHRD_TUNNEL6) {
+		skb->dev = dev;
+		skb->protocol = htons(ETH_P_IP);
+		skb->pkt_type = PACKET_HOST;
+		skb->skb_iif = dev->ifindex;
+		skb->ip_summed = CHECKSUM_NONE;
+		ip_rt_put(rt);
+		netif_receive_skb(skb);
+		return;
+	}
+
+	/*
+	 * Send encap direction packets to tunnel xmit using ndo_start_xmit
+	 */
+	skb_dst_drop(skb);
+	skb_dst_set(skb, &rt->dst);
+
+	/*
+	 * Set ignore df bit to fragment the packet in kernel.
+	 */
+	if (!(iph->frag_off & htons(IP_DF))) {
+		skb->ignore_df = true;
+	}
+
+	skb->protocol = htons(ETH_P_IP);
+	skb->pkt_type = PACKET_HOST;
+	skb->skb_iif = dev->ifindex;
+	skb->dev = dev;
+	skb->ip_summed = CHECKSUM_NONE;
+
+	/*
+	 * This is needed to acquire HARD_TX_LOCK.
+	 */
+	cpu = smp_processor_id();
+	queue = skb_get_tx_queue(dev, skb);
+
+	nss_tunipip6_trace("%px: skb queue mapping: %d, cpu: %d", skb, skb_get_queue_mapping(skb), cpu);
+
+	/*
+	 * Take HARD_TX_LOCK to be in sync with the kernel.
+	 */
+	HARD_TX_LOCK(dev, queue, cpu);
+
+	/*
+	 * Check if queue is alive
+	 */
+	if (unlikely(netif_xmit_frozen_or_stopped(queue))) {
+		HARD_TX_UNLOCK(dev, queue);
+		nss_tunipip6_trace("%px: Dropping the packet, as queue: %px is not alive", skb, queue);
+		skb_dst_drop(skb);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+	ops->ndo_start_xmit(skb, dev);
+	HARD_TX_UNLOCK(dev, queue);
+}
+
+/*
+ * nss_tunipip6_decap_exception()
+ *	Exception handler registered to NSS driver.
+ *
+ * Exception handler registered to NSS for handling tunipip6 ipv6 pkts.
+ */
+static void nss_tunipip6_decap_exception(struct net_device *dev, struct sk_buff *skb, __attribute__((unused)) struct napi_struct *napi)
+{
+	const struct net_device_ops *ops = dev->netdev_ops;
+	struct netdev_queue *queue;
+	struct iphdr *iph;
+	struct rtable *rt;
+	int cpu;
+	int8_t ver = skb->data[0] >> 4;
+
+	nss_tunipip6_trace("%px: received - %d bytes name %s ver %x\n",
+			dev, skb->len, dev->name, ver);
+
+	nss_tunipip6_assert(ver == 6);
+
+	if (unlikely(!pskb_may_pull(skb, sizeof(struct ipv6hdr)))) {
+		nss_tunipip6_warning("%px: pskb_may_pull failed to pull ipv6 header", dev);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	skb_pull(skb, sizeof(struct ipv6hdr));
+
+	if (unlikely(!pskb_may_pull(skb, sizeof(struct iphdr)))) {
+		nss_tunipip6_warning("%px: pskb_may_pull failed to linearize iphdr, packet does not have a proper IPv4 header.", dev);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	skb_reset_network_header(skb);
+
+	iph = ip_hdr(skb);
+	nss_tunipip6_assert(iph->version == 4);
+
+	rt = ip_route_output(&init_net, iph->daddr, 0, 0, 0);
+	if (unlikely(IS_ERR(rt))) {
+		nss_tunipip6_info("%px: Failed to find IPv4 route for %pI4\n", skb, &iph->daddr);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	nss_tunipip6_trace("%px: Route look up successful for dest_ip: %pI4 src_ip: %pI4\n",
+			skb, &iph->daddr, &iph->saddr);
+
+	skb_dst_drop(skb);
+	skb_dst_set(skb, &rt->dst);
+
+	skb_reset_transport_header(skb);
+
+	/*
+	 * Set ignore df bit to fragment the packet in kernel.
+	 */
+	if (!(iph->frag_off & htons(IP_DF))) {
+		skb->ignore_df = true;
+	}
+
+	skb->protocol = htons(ETH_P_IP);
+	skb->pkt_type = PACKET_HOST;
+	skb->skb_iif = dev->ifindex;
+	skb->dev = dev;
+	skb->ip_summed = CHECKSUM_NONE;
+
+	/*
+	 * This is needed to acquire HARD_TX_LOCK.
+	 */
+	cpu = smp_processor_id();
+	queue = skb_get_tx_queue(dev, skb);
+
+	nss_tunipip6_trace("%px: skb queue mapping: %d, cpu: %d", skb, skb_get_queue_mapping(skb), cpu);
+
+	/*
+	 * Take HARD_TX_LOCK to be in sync with the kernel.
+	 */
+	HARD_TX_LOCK(dev, queue, cpu);
+
+	/*
+	 * Check if queue is alive
+	 */
+	if (unlikely(netif_xmit_frozen_or_stopped(queue))) {
+		HARD_TX_UNLOCK(dev, queue);
+		nss_tunipip6_trace("%px: Dropping the packet, as queue: %px is not alive", skb, queue);
+		skb_dst_drop(skb);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+	ops->ndo_start_xmit(skb, dev);
+	HARD_TX_UNLOCK(dev, queue);
+}
+
+/*
+ *  nss_tunipip6_update_dev_stats
+ *	Update the Dev stats received from NSS
+ */
+static void nss_tunipip6_update_dev_stats(struct net_device *dev,
+					struct nss_tunipip6_msg *tnlmsg)
+{
+	struct pcpu_sw_netstats stats;
+	enum nss_dynamic_interface_type interface_type;
+	struct nss_tunipip6_stats_sync_msg *sync_stats = (struct nss_tunipip6_stats_sync_msg *)&tnlmsg->msg.stats;
+
+	interface_type = nss_dynamic_interface_get_type(nss_tunipip6_get_context(), tnlmsg->cm.interface);
+
+	memset(&stats, 0, sizeof(stats));
+	if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER) {
+		stats.tx_packets = sync_stats->node_stats.tx_packets;
+		stats.tx_bytes = sync_stats->node_stats.tx_bytes;
+	} else if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_OUTER) {
+		stats.rx_packets = sync_stats->node_stats.rx_packets;
+		stats.rx_bytes = sync_stats->node_stats.rx_bytes;
+	} else {
+		nss_tunipip6_warning("%px: Invalid interface type received from NSS\n", dev);
+		return;
+	}
+
+	dev->stats.rx_dropped += nss_cmn_rx_dropped_sum(&sync_stats->node_stats);
+
+	/* TODO: Update rx_dropped stats in ip6_update_offload_stats() */
+	ip6_update_offload_stats(dev, (void *)&stats);
+}
+
+/*
+ * nss_tunipip6_event_receive()
+ *	Event Callback to receive events from NSS.
+ */
+void nss_tunipip6_event_receive(void *if_ctx, struct nss_tunipip6_msg *tnlmsg)
+{
+	struct net_device *netdev = NULL;
+
+	netdev = (struct net_device *)if_ctx;
+
+	switch (tnlmsg->cm.type) {
+	case NSS_TUNIPIP6_STATS_SYNC:
+		/*
+		 * Update netdevice statistics.
+		 */
+		nss_tunipip6_update_dev_stats(netdev, tnlmsg);
+
+		/*
+		 * Update NSS statistics for tunipip6.
+		 */
+		nss_tunipip6_stats_sync(netdev, tnlmsg);
+		break;
+
+	default:
+		nss_tunipip6_info("%px: Unknown Event from NSS\n", netdev);
+		break;
+	}
+}
+
+/*
+ * _nss_tunipip6_dyn_interface_destroy()
+ * 	Destroy NSS dynamic interface.
+ */
+enum nss_connmgr_tunipip6_err_codes _nss_tunipip6_dyn_interface_destroy(struct net_device *netdev)
+{
+	int inner_ifnum, outer_ifnum;
+	nss_tx_status_t status;
+
+	/*
+	 * Check if tunnel ipip6 is registered ?
+	 */
+	inner_ifnum = nss_cmn_get_interface_number_by_dev_and_type(netdev, NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER);
+	if (inner_ifnum < 0) {
+		nss_tunipip6_warning("%px: Net device is not registered with nss inner node\n", netdev);
+		return NSS_CONNMGR_TUNIPIP6_NO_DEV;
+	}
+
+	status = nss_dynamic_interface_dealloc_node(inner_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tunipip6_warning("%px: Dealloc inneer node failure\n", netdev);
+		return NSS_CONNMGR_TUNIPIP6_TUN_DESTROY_FAILURE;
+	}
+
+	/*
+	 * Un-Register IPIP6 tunnel with NSS
+	 */
+	nss_unregister_tunipip6_if(inner_ifnum);
+
+	outer_ifnum = nss_cmn_get_interface_number_by_dev_and_type(netdev, NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_OUTER);
+	if (outer_ifnum < 0) {
+		nss_tunipip6_warning("%px: Net device is not registered with nss outer node\n", netdev);
+		return NSS_CONNMGR_TUNIPIP6_NO_DEV;
+	}
+
+	status = nss_dynamic_interface_dealloc_node(outer_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_OUTER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tunipip6_warning("%px: Dealloc outer node failure\n", netdev);
+		return NSS_CONNMGR_TUNIPIP6_TUN_DESTROY_FAILURE;
+	}
+
+	/*
+	 * Un-Register IPIP6 tunnel with NSS
+	 */
+	nss_unregister_tunipip6_if(outer_ifnum);
+
+	return NSS_CONNMGR_TUNIPIP6_SUCCESS;
+}
+
+/*
+ * nss_tunipip6_dev_parse_param()
+ *	IPIP6 standard Tunnel device i/f up handler
+ */
+static void nss_tunipip6_dev_parse_param(struct net_device *netdev, struct nss_connmgr_tunipip6_tunnel_cfg *tnlcfg)
+{
+	struct ip6_tnl *tunnel;
+	struct flowi6 *fl6;
+
+	tunnel = (struct ip6_tnl *)netdev_priv(netdev);
+
+	/*
+	 * Find the Tunnel device flow information
+	 */
+	fl6 = &tunnel->fl.u.ip6;
+
+	nss_tunipip6_trace("%px: Tunnel param saddr: %pI6 daddr: %pI6\n", netdev, fl6->saddr.s6_addr32, fl6->daddr.s6_addr32);
+	nss_tunipip6_trace("%px: Hop limit %d\n", netdev, tunnel->parms.hop_limit);
+	nss_tunipip6_trace("%px: Tunnel param flag %x  fl6.flowlabel %x\n", netdev,  tunnel->parms.flags, fl6->flowlabel);
+	nss_tunipip6_trace("%px: Tunnel frag id update is %d\n", netdev, frag_id_update);
+
+	/*
+	 * Prepare The Tunnel configuration parameter to send to nss
+	 */
+	tnlcfg->saddr[0] = ntohl(fl6->saddr.s6_addr32[0]);
+	tnlcfg->saddr[1] = ntohl(fl6->saddr.s6_addr32[1]);
+	tnlcfg->saddr[2] = ntohl(fl6->saddr.s6_addr32[2]);
+	tnlcfg->saddr[3] = ntohl(fl6->saddr.s6_addr32[3]);
+	tnlcfg->daddr[0] = ntohl(fl6->daddr.s6_addr32[0]);
+	tnlcfg->daddr[1] = ntohl(fl6->daddr.s6_addr32[1]);
+	tnlcfg->daddr[2] = ntohl(fl6->daddr.s6_addr32[2]);
+	tnlcfg->daddr[3] = ntohl(fl6->daddr.s6_addr32[3]);
+	tnlcfg->hop_limit = tunnel->parms.hop_limit;
+	tnlcfg->flags = ntohl(tunnel->parms.flags);
+	tnlcfg->ttl_inherit = false;
+	tnlcfg->tos_inherit = true;
+	tnlcfg->frag_id_update = frag_id_update;
+	tnlcfg->fmr_max = NSS_TUNIPIP6_MAX_FMR;
+	/*
+	 * Flow Label In kernel is stored in big endian format.
+	 */
+	tnlcfg->flowlabel = fl6->flowlabel;
+
+	/*
+	 * The tunnel_type for ds-lite and map-e should be same.
+	 */
+	tnlcfg->tunnel_type = NSS_CONNMGR_TUNIPIP6_TUNNEL_MAPE;
+
+#if IS_ENABLED(CONFIG_MAP_E_SUPPORT)
+#ifdef DRAFT03_SUPPORT
+	/*
+	 * Set "tunnel_type" based on draft03.
+	 */
+	if (tunnel->parms.draft03) {
+		tnlcfg->tunnel_type = NSS_CONNMGR_TUNIPIP6_TUNNEL_MAPE_DRAFT03;
+	}
+#endif
+#endif
+}
+
+#if IS_ENABLED(CONFIG_MAP_E_SUPPORT)
+/*
+ * nss_connmgr_tunipip6_configure_fmr()
+ * 	Add FMR in NSS (if present).
+ */
+static void nss_connmgr_tunipip6_configure_fmr(struct net_device *netdev)
+{
+	struct ip6_tnl *tunnel;
+	struct __ip6_tnl_fmr *fmr;
+	uint32_t fmr_number = 0;
+	enum nss_connmgr_tunipip6_err_codes status;
+	struct nss_connmgr_tunipip6_maprule_cfg mrcfg = {0};
+
+	tunnel = (struct ip6_tnl *)netdev_priv(netdev);
+
+	/*
+	 * Configure FMR table up to NSS_TUNIPIP6_MAX_FMR, the rest will be forwarded to BR
+	 */
+	for (fmr = tunnel->parms.fmrs; fmr && fmr_number < NSS_TUNIPIP6_MAX_FMR; fmr = fmr->next, fmr_number++) {
+		/*
+		 * Prepare "rulecfg"
+		 */
+		mrcfg.rule_type = NSS_CONNMGR_TUNIPIP6_RULE_FMR;
+		mrcfg.ipv6_prefix[0] = ntohl(fmr->ip6_prefix.s6_addr32[0]);
+		mrcfg.ipv6_prefix[1] = ntohl(fmr->ip6_prefix.s6_addr32[1]);
+		mrcfg.ipv6_prefix[2] = ntohl(fmr->ip6_prefix.s6_addr32[2]);
+		mrcfg.ipv6_prefix[3] = ntohl(fmr->ip6_prefix.s6_addr32[3]);
+		mrcfg.ipv4_prefix = ntohl(fmr->ip4_prefix.s_addr);
+		mrcfg.ipv6_prefix_len = fmr->ip6_prefix_len;
+		mrcfg.ipv4_prefix_len = fmr->ip4_prefix_len;
+		mrcfg.ea_len = fmr->ea_len;
+		mrcfg.psid_offset = fmr->offset;
+
+		/*
+		 * Call add maprule API.
+		 */
+		status = nss_connmgr_tunipip6_add_maprule(netdev, &mrcfg);
+		if (status != NSS_CONNMGR_TUNIPIP6_SUCCESS) {
+			nss_tunipip6_trace("%px: Not able to add FMR rule. IPv6 Prefix: %pI6 IPv6 Prefix Lenght: %d\n"
+					"IPv4 Prefix: %pI6 IPv4 Prefix Lenght: %d EA Length: %d PSID Offset: %d\n",
+					netdev, mrcfg.ipv6_prefix, mrcfg.ipv6_prefix_len,&mrcfg.ipv4_prefix,
+					mrcfg.ipv4_prefix_len, mrcfg.ea_len, mrcfg.psid_offset);
+		}
+	}
+}
+#endif
+
+/*
+ * nss_connmgr_tunipip6_create_interface()
+ * 	Exported API to create and configure NSS nodes.
+ */
+enum nss_connmgr_tunipip6_err_codes nss_connmgr_tunipip6_create_interface(struct net_device *netdev, struct nss_connmgr_tunipip6_tunnel_cfg *tnlcfg)
+{
+	struct nss_tunipip6_msg tnlmsg;
+	struct nss_tunipip6_create_msg *tnlcreate;
+	struct nss_ctx_instance *nss_ctx;
+	int inner_ifnum, outer_ifnum;
+	uint32_t features = 0;
+	nss_tx_status_t status;
+	struct nss_tunipip6_instance *ntii;
+
+#if IS_ENABLED(CONFIG_MAP_E_SUPPORT)
+#ifndef DRAFT03_SUPPORT
+	if ((tnlcfg->tunnel_type == NSS_CONNMGR_TUNIPIP6_TUNNEL_4RD) ||
+		tnlcfg->tunnel_type == NSS_CONNMGR_TUNIPIP6_TUNNEL_MAPE_DRAFT03) {
+		nss_tunipip6_warning("Draftf03 is not supported\n");
+		return NSS_CONNMGR_TUNIPIP6_TUN_CREATE_FAILURE;
+	}
+#endif
+#endif
+	/*
+	 * For standard tunnel, netdev and tnlcfg validation is done
+	 * inside nss_tunipip6_dev_parse_param().
+	 */
+	if (!enable_custom) {
+		goto configure_tunnel;
+	}
+
+	if (!netdev || !tnlcfg) {
+		nss_tunipip6_warning("Invalid parametes passed\n");
+		return NSS_CONNMGR_TUNIPIP6_INVALID_PARAM;
+	}
+
+	/*
+	 * Validate netdev for ipv6-in-ipv4  Tunnel
+	 */
+	if (netdev->type != ARPHRD_TUNNEL6) {
+		nss_tunipip6_warning("%px: Invalid netdevice type: %d\n", netdev, netdev->type);
+		return NSS_CONNMGR_TUNIPIP6_NETDEV_TYPE_FAILURE;
+	}
+
+configure_tunnel:
+	if ((tnlcfg->tunnel_type != NSS_CONNMGR_TUNIPIP6_TUNNEL_4RD) &&
+		(tnlcfg->tunnel_type != NSS_CONNMGR_TUNIPIP6_TUNNEL_MAPE) &&
+		(tnlcfg->tunnel_type != NSS_CONNMGR_TUNIPIP6_TUNNEL_MAPE_DRAFT03)) {
+		nss_tunipip6_warning("%px: Invalid tunnel type: %d\n", netdev, tnlcfg->tunnel_type);
+		return NSS_CONNMGR_TUNIPIP6_TUN_NONE;
+	}
+
+	/*
+	 * Prepare The Tunnel configuration parameter to send to nss
+	 */
+	memset(&tnlmsg, 0, sizeof(struct nss_tunipip6_msg));
+	tnlcreate = &tnlmsg.msg.tunipip6_create;
+
+	tnlcreate->saddr[0] = tnlcfg->saddr[0];
+	tnlcreate->saddr[1] = tnlcfg->saddr[1];
+	tnlcreate->saddr[2] = tnlcfg->saddr[2];
+	tnlcreate->saddr[3] = tnlcfg->saddr[3];
+	tnlcreate->daddr[0] = tnlcfg->daddr[0];
+	tnlcreate->daddr[1] = tnlcfg->daddr[1];
+	tnlcreate->daddr[2] = tnlcfg->daddr[2];
+	tnlcreate->daddr[3] = tnlcfg->daddr[3];
+	tnlcreate->hop_limit = tnlcfg->hop_limit;
+	tnlcreate->flags = tnlcfg->flags;
+	tnlcreate->flowlabel = tnlcfg->flowlabel;
+	tnlcreate->ttl_inherit = tnlcfg->ttl_inherit;
+	tnlcreate->tos_inherit = tnlcfg->tos_inherit;
+	tnlcreate->frag_id_update = tnlcfg->frag_id_update;
+	tnlcreate->fmr_max = tnlcfg->fmr_max;
+
+	/*
+	 * Set "draft03" based on "tunnel_type". draft03 should be
+	 * set to 0 for MAPE.
+	 */
+	if ((tnlcfg->tunnel_type == NSS_CONNMGR_TUNIPIP6_TUNNEL_4RD) ||
+			(tnlcfg->tunnel_type == NSS_CONNMGR_TUNIPIP6_TUNNEL_MAPE_DRAFT03)) {
+		tnlcreate->draft03 = 1;
+	}
+
+	inner_ifnum = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER);
+	if (inner_ifnum < 0) {
+		nss_tunipip6_warning("%px: Request interface number failed\n", netdev);
+		goto inner_alloc_fail;
+	}
+
+	outer_ifnum = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_OUTER);
+	if (outer_ifnum < 0) {
+		nss_tunipip6_warning("%px: Request interface number failed\n", netdev);
+		goto outer_alloc_fail;
+	}
+
+	/*
+	 * Register ipip6 tunnel with NSS
+	 */
+	nss_ctx = nss_register_tunipip6_if(inner_ifnum,
+					NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER,
+					nss_tunipip6_encap_exception,
+					nss_tunipip6_event_receive,
+					netdev,
+					features);
+	if (!nss_ctx) {
+		nss_tunipip6_warning("%px: nss_register_tunipip6_if Failed\n", netdev);
+		goto inner_reg_fail;
+	}
+
+	nss_ctx = nss_register_tunipip6_if(outer_ifnum,
+					NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_OUTER,
+					nss_tunipip6_decap_exception,
+					nss_tunipip6_event_receive,
+					netdev,
+					features);
+	if (!nss_ctx) {
+		nss_tunipip6_warning("%px: nss_register_tunipip6_if Failed\n", netdev);
+		goto outer_reg_fail;
+	}
+
+	nss_tunipip6_trace("%px: nss_register_tunipip6_if Success\n", netdev);
+
+	/*
+	 * Updating sibling_if_num for encap interface.
+	 */
+	tnlcreate->sibling_if_num = outer_ifnum;
+
+	nss_tunipip6_trace("%px: Tunnel Param srcaddr %x:%x:%x:%x  daddr %x:%x:%x:%x\n", netdev,
+			tnlcreate->saddr[0], tnlcreate->saddr[1],
+			tnlcreate->saddr[2], tnlcreate->saddr[3],
+			tnlcreate->daddr[0], tnlcreate->daddr[1],
+			tnlcreate->daddr[2], tnlcreate->daddr[3]);
+
+	/*
+	 * Send configure message to encap interface.
+	 */
+	nss_tunipip6_msg_init(&tnlmsg, inner_ifnum, NSS_TUNIPIP6_TX_ENCAP_IF_CREATE,
+			sizeof(struct nss_tunipip6_create_msg), NULL, NULL);
+
+	nss_tunipip6_trace("%px: Sending IPIP6 tunnel i/f up command to NSS %px\n", netdev, nss_ctx);
+	status = nss_tunipip6_tx_sync(nss_ctx, &tnlmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tunipip6_warning("%px: Tunnel up command error %d\n", netdev, status);
+		goto context_alloc_fail;
+	}
+
+	/*
+	 * Updating sibling_if_num for decap interface.
+	 */
+	tnlcreate->sibling_if_num = inner_ifnum;
+
+	/*
+	 * Send configure message to decap interface.
+	 */
+	nss_tunipip6_msg_init(&tnlmsg, outer_ifnum, NSS_TUNIPIP6_TX_DECAP_IF_CREATE,
+			sizeof(struct nss_tunipip6_create_msg), NULL, NULL);
+
+	nss_tunipip6_trace("%px: Sending IPIP6 tunnel i/f up command to NSS %px\n", netdev, nss_ctx);
+	status = nss_tunipip6_tx_sync(nss_ctx, &tnlmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tunipip6_warning("%px: Tunnel up command error %d\n", netdev, status);
+		goto context_alloc_fail;
+	}
+
+	/*
+	 * Initialize tunipip6 instance.
+	 */
+	ntii = nss_tunipip6_alloc_instance(netdev, inner_ifnum, outer_ifnum);
+	if (!ntii) {
+		nss_tunipip6_warning("%px: Not able to create tunipip6 instance\n", netdev);
+		goto context_alloc_fail;
+	}
+
+	/*
+	 * Add the new tunipip6 instance to the global list.
+	 */
+	spin_lock_bh(&tunipip6_ctx.lock);
+	list_add(&ntii->list, &tunipip6_ctx.dev_list);
+	spin_unlock_bh(&tunipip6_ctx.lock);
+
+	return NSS_CONNMGR_TUNIPIP6_SUCCESS;
+
+context_alloc_fail:
+	nss_unregister_tunipip6_if(outer_ifnum);
+outer_reg_fail:
+	nss_unregister_tunipip6_if(inner_ifnum);
+inner_reg_fail:
+	status = nss_dynamic_interface_dealloc_node(outer_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_OUTER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tunipip6_warning("%px: Unable to dealloc the node[%d] in the NSS fw!\n", netdev, outer_ifnum);
+	}
+outer_alloc_fail:
+	status = nss_dynamic_interface_dealloc_node(inner_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tunipip6_warning("%px: Unable to dealloc the node[%d] in the NSS fw!\n", netdev, inner_ifnum);
+	}
+inner_alloc_fail:
+
+	return NSS_CONNMGR_TUNIPIP6_TUN_CREATE_FAILURE;
+}
+EXPORT_SYMBOL(nss_connmgr_tunipip6_create_interface);
+
+/*
+ * nss_connmgr_tunipip6_destroy_interface()
+ * 	Exported API to destroy NSS dynamic interface.
+ */
+enum nss_connmgr_tunipip6_err_codes nss_connmgr_tunipip6_destroy_interface(struct net_device *netdev)
+{
+	enum nss_connmgr_tunipip6_err_codes ret;
+
+	/*
+	 * Validate netdev for ipv6-in-ipv4  Tunnel
+	 */
+	if (netdev->type != ARPHRD_TUNNEL6) {
+		return NSS_CONNMGR_TUNIPIP6_NETDEV_TYPE_FAILURE;
+	}
+
+	/*
+	 * Destroy tunipip6 NSS context.
+	 */
+	ret = _nss_tunipip6_dyn_interface_destroy(netdev);
+	if (ret != NSS_CONNMGR_TUNIPIP6_SUCCESS) {
+		nss_tunipip6_warning("%px: Not able to destroy NSS context. Err: %d\n", netdev, ret);
+		return ret;
+	}
+
+	/*
+	 * Find and free the tunipip6 instance.
+	 */
+	ret = nss_tunipip6_find_and_free_instance(netdev);
+	return ret;
+}
+EXPORT_SYMBOL(nss_connmgr_tunipip6_destroy_interface);
+
+/*
+ * nss_connmgr_tunipip6_add_maprule()
+ * 	Add new BMR/FMR entry.
+ */
+enum nss_connmgr_tunipip6_err_codes nss_connmgr_tunipip6_add_maprule(struct net_device *netdev, struct nss_connmgr_tunipip6_maprule_cfg *rulecfg)
+{
+	struct nss_tunipip6_msg tnlmsg;
+	struct nss_tunipip6_map_rule *rule_add;
+	struct nss_ctx_instance *nss_ctx;
+	nss_tx_status_t status;
+	int inner_ifnum;
+	int msg_type;
+
+	if (!netdev || !rulecfg) {
+		return NSS_CONNMGR_TUNIPIP6_INVALID_PARAM;
+	}
+
+	inner_ifnum = nss_cmn_get_interface_number_by_dev_and_type(netdev, NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER);
+	if (inner_ifnum < 0) {
+		nss_tunipip6_warning("%px: Invalid inner interface number: %d\n", netdev, inner_ifnum);
+		return NSS_CONNMGR_TUNIPIP6_NO_DEV;
+	}
+
+	switch (rulecfg->rule_type) {
+	case NSS_CONNMGR_TUNIPIP6_RULE_BMR:
+		msg_type = NSS_TUNIPIP6_BMR_RULE_ADD;
+		break;
+	case NSS_CONNMGR_TUNIPIP6_RULE_FMR:
+		msg_type = NSS_TUNIPIP6_FMR_RULE_ADD;
+		break;
+	default:
+		nss_tunipip6_warning("%p: Invalid rule type: %d", netdev, rulecfg->rule_type);
+		return NSS_CONNMGR_TUNIPIP6_INVALID_RULE_TYPE;
+	}
+
+	/*
+	 * Prepare the mapping rule parameter to send to nss
+	 */
+	memset(&tnlmsg, 0, sizeof(struct nss_tunipip6_msg));
+	rule_add = &tnlmsg.msg.map_rule;
+
+	rule_add->ip6_prefix[0] = rulecfg->ipv6_prefix[0];
+	rule_add->ip6_prefix[1] = rulecfg->ipv6_prefix[1];
+	rule_add->ip6_prefix[2] = rulecfg->ipv6_prefix[2];
+	rule_add->ip6_prefix[3] = rulecfg->ipv6_prefix[3];
+	rule_add->ip6_prefix_len = rulecfg->ipv6_prefix_len;
+
+	rule_add->ip4_prefix = rulecfg->ipv4_prefix;
+	rule_add->ip4_prefix_len = rulecfg->ipv4_prefix_len;
+
+	rule_add->ip6_suffix[0] = rulecfg->ipv6_suffix[0];
+	rule_add->ip6_suffix[1] = rulecfg->ipv6_suffix[1];
+	rule_add->ip6_suffix[2] = rulecfg->ipv6_suffix[2];
+	rule_add->ip6_suffix[3] = rulecfg->ipv6_suffix[3];
+	rule_add->ip6_suffix_len = rulecfg->ipv6_suffix_len;
+
+	rule_add->ea_len = rulecfg->ea_len;
+	rule_add->psid_offset = rulecfg->psid_offset;
+
+	/*
+	 * Send maprule add message to encap interface.
+	 */
+	nss_tunipip6_msg_init(&tnlmsg, inner_ifnum, msg_type,
+			sizeof(struct nss_tunipip6_map_rule), NULL, NULL);
+
+	nss_ctx = nss_tunipip6_get_context();
+	nss_tunipip6_trace("%px: Sending IPIP6 tunnel maprule, message type %d add command to NSS %p\n", netdev, msg_type, nss_ctx);
+	status = nss_tunipip6_tx_sync(nss_ctx, &tnlmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tunipip6_warning("%px: Tunnel maprule add command error %d\n", netdev, status);
+		return NSS_CONNMGR_TUNIPIP6_MAPRULE_ADD_FAILURE;
+	}
+
+	return NSS_CONNMGR_TUNIPIP6_SUCCESS;
+}
+EXPORT_SYMBOL(nss_connmgr_tunipip6_add_maprule);
+
+/*
+ * nss_connmgr_tunipip6_del_maprule()
+ * 	Delete existing BMR/FMR entry.
+ */
+enum nss_connmgr_tunipip6_err_codes nss_connmgr_tunipip6_del_maprule(struct net_device *netdev, struct nss_connmgr_tunipip6_maprule_cfg *rulecfg)
+{
+	struct nss_tunipip6_msg tnlmsg;
+	struct nss_tunipip6_map_rule *map_rule;
+	struct nss_ctx_instance *nss_ctx;
+	nss_tx_status_t status;
+	int inner_ifnum;
+	int msg_type;
+
+	if (!netdev || !rulecfg) {
+		return NSS_CONNMGR_TUNIPIP6_INVALID_PARAM;
+	}
+
+	inner_ifnum = nss_cmn_get_interface_number_by_dev_and_type(netdev, NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER);
+	if (inner_ifnum < 0) {
+		nss_tunipip6_warning("%px: Invalid inner interface number: %d\n", netdev, inner_ifnum);
+		return NSS_CONNMGR_TUNIPIP6_NO_DEV;
+	}
+
+	/*
+	 * Intialize tunnel message.
+	 */
+	memset(&tnlmsg, 0, sizeof(struct nss_tunipip6_msg));
+
+	/*
+	 * To delete BMR, only delete message is needed.
+	 */
+	switch (rulecfg->rule_type) {
+	case NSS_CONNMGR_TUNIPIP6_RULE_BMR:
+		msg_type = NSS_TUNIPIP6_BMR_RULE_DEL;
+
+		/*
+		 * To delete BMR, only delete message is needed.
+		 */
+		goto del_bmr;
+	case NSS_CONNMGR_TUNIPIP6_RULE_FMR:
+		msg_type = NSS_TUNIPIP6_FMR_RULE_DEL;
+		break;
+	default:
+		nss_tunipip6_warning("%p: Invalid rule type: %d", netdev, rulecfg->rule_type);
+		return NSS_CONNMGR_TUNIPIP6_INVALID_RULE_TYPE;
+	}
+
+	/*
+	 * Prepare the maprule rule parameter to send to NSS
+	 */
+	map_rule = &tnlmsg.msg.map_rule;
+	map_rule->ip6_prefix[0] = rulecfg->ipv6_prefix[0];
+	map_rule->ip6_prefix[1] = rulecfg->ipv6_prefix[1];
+	map_rule->ip6_prefix[2] = rulecfg->ipv6_prefix[2];
+	map_rule->ip6_prefix[3] = rulecfg->ipv6_prefix[3];
+	map_rule->ip6_prefix_len = rulecfg->ipv6_prefix_len;
+
+	map_rule->ip4_prefix = rulecfg->ipv4_prefix;
+	map_rule->ip4_prefix_len = rulecfg->ipv4_prefix_len;
+
+	map_rule->ip6_suffix[0] = rulecfg->ipv6_suffix[0];
+	map_rule->ip6_suffix[1] = rulecfg->ipv6_suffix[1];
+	map_rule->ip6_suffix[2] = rulecfg->ipv6_suffix[2];
+	map_rule->ip6_suffix[3] = rulecfg->ipv6_suffix[3];
+	map_rule->ip6_suffix_len = rulecfg->ipv6_suffix_len;
+
+	map_rule->ea_len = rulecfg->ea_len;
+	map_rule->psid_offset = rulecfg->psid_offset;
+
+del_bmr:
+	/*
+	 * Send map rule delete message to encap interface.
+	 */
+	nss_tunipip6_msg_init(&tnlmsg, inner_ifnum, msg_type,
+			sizeof(struct nss_tunipip6_map_rule), NULL, NULL);
+	nss_ctx = nss_tunipip6_get_context();
+	nss_tunipip6_trace("%px: Sending IPIP6 tunnel maprule, message type %d delete command to NSS %p\n", netdev, msg_type, nss_ctx);
+	status = nss_tunipip6_tx_sync(nss_ctx, &tnlmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tunipip6_warning("%px: Tunnel maprule delete command error %d\n", netdev, status);
+		return NSS_CONNMGR_TUNIPIP6_MAPRULE_DEL_FAILURE;
+	}
+
+	return NSS_CONNMGR_TUNIPIP6_SUCCESS;
+}
+EXPORT_SYMBOL(nss_connmgr_tunipip6_del_maprule);
+
+/*
+ * nss_connmgr_tunipip6_flush_fmr_rule()
+ * 	Flush existing FMR entry.
+ */
+enum nss_connmgr_tunipip6_err_codes nss_connmgr_tunipip6_flush_fmr_rule(struct net_device *netdev)
+{
+	struct nss_tunipip6_msg tnlmsg;
+	struct nss_ctx_instance *nss_ctx;
+	nss_tx_status_t status;
+	int inner_ifnum;
+
+	if (!netdev) {
+		return NSS_CONNMGR_TUNIPIP6_INVALID_PARAM;
+	}
+
+	/*
+	 * Send fmr rule flush message to encap interface.
+	 */
+	inner_ifnum = nss_cmn_get_interface_number_by_dev_and_type(netdev, NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER);
+	if (inner_ifnum < 0) {
+		nss_tunipip6_warning("%px: Invalid inner interface number: %d\n", netdev, inner_ifnum);
+		return NSS_CONNMGR_TUNIPIP6_NO_DEV;
+	}
+
+	nss_tunipip6_msg_init(&tnlmsg, inner_ifnum, NSS_TUNIPIP6_FMR_RULE_FLUSH,
+			0, NULL, NULL);
+
+	nss_ctx = nss_tunipip6_get_context();
+	nss_tunipip6_trace("%px: Sending IPIP6 tunnel FMR rule flush command to NSS %p\n", netdev, nss_ctx);
+	status = nss_tunipip6_tx_sync(nss_ctx, &tnlmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_tunipip6_warning("%px: FMR rule flush command error %d\n", netdev, status);
+		return NSS_CONNMGR_TUNIPIP6_FMR_RULE_FLUSH_FAILURE;
+	}
+
+	return NSS_CONNMGR_TUNIPIP6_SUCCESS;
+}
+EXPORT_SYMBOL(nss_connmgr_tunipip6_flush_fmr_rule);
+
+/*
+ * nss_tunipip6_dev_event()
+ *	Net device notifier for ipip6 module
+ */
+static int nss_tunipip6_dev_event(struct notifier_block  *nb,
+		unsigned long event, void  *dev)
+{
+	struct net_device *netdev = netdev_notifier_info_to_dev(dev);
+	struct nss_connmgr_tunipip6_tunnel_cfg tnlcfg = {0};
+
+	/*
+	 * Validate netdev for ipv6-in-ipv4  Tunnel
+	 */
+	if (netdev->type != ARPHRD_TUNNEL6 ) {
+		return NOTIFY_DONE;;
+	}
+
+	switch (event) {
+	case NETDEV_UP:
+		nss_tunipip6_trace("%px: NETDEV_UP :event %lu name %s\n", netdev, event, netdev->name);
+
+		/*
+		 * Create NSS interface for standard tunnel. The creation of the tunnel
+		 * is a three step process.
+		 * 1.	'tnlcfg' is populated from the netdev parameters.
+		 * 2.	Create API is called to create NSS encap and decap nodes.
+		 * 3.	Configure FMR rules(if present) in NSS encap node.
+		 */
+		nss_tunipip6_dev_parse_param(netdev, &tnlcfg);
+		if (nss_connmgr_tunipip6_create_interface(netdev, &tnlcfg) != NSS_CONNMGR_TUNIPIP6_SUCCESS) {
+			nss_tunipip6_trace("%px: Not able to create tunnel for dev: %s\n", netdev, netdev->name);
+			return NOTIFY_DONE;
+		}
+#if IS_ENABLED(CONFIG_MAP_E_SUPPORT)
+		nss_connmgr_tunipip6_configure_fmr(netdev);
+#endif
+		break;
+
+	case NETDEV_DOWN:
+		nss_tunipip6_trace("%px: NETDEV_DOWN :event %lu name %s\n", netdev, event, netdev->name);
+		nss_connmgr_tunipip6_destroy_interface(netdev);
+		break;
+
+	default:
+		nss_tunipip6_trace("%px: Unhandled notifier dev %s event %x\n", netdev, netdev->name, (int)event);
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_tunipip6_destroy_interface_all()
+ * 	Destroy NSS interfaces and free instance for all tunipip6 interfaces.
+ */
+static void nss_tunipip6_destroy_interface_all(void)
+{
+	struct net_device *netdev;
+	struct dentry *dentry;
+	struct nss_tunipip6_instance *ntii;
+
+	spin_lock_bh(&tunipip6_ctx.lock);
+	ntii = list_first_entry_or_null(&tunipip6_ctx.dev_list, struct nss_tunipip6_instance, list);
+	do {
+		if (!ntii) {
+			spin_unlock_bh(&tunipip6_ctx.lock);
+			return;
+		}
+
+		netdev = ntii->dev;
+		dentry = ntii->dentry;
+		nss_tunipip6_free_instance(ntii);
+		spin_unlock_bh(&tunipip6_ctx.lock);
+
+		dev_put(netdev);
+		debugfs_remove(dentry);
+		_nss_tunipip6_dyn_interface_destroy(netdev);
+
+		spin_lock_bh(&tunipip6_ctx.lock);
+		ntii = list_first_entry_or_null(&tunipip6_ctx.dev_list, struct nss_tunipip6_instance, list);
+	} while (ntii);
+	spin_unlock_bh(&tunipip6_ctx.lock);
+}
+
+/*
+ * Linux Net device Notifier
+ */
+struct notifier_block nss_tunipip6_notifier = {
+	.notifier_call = nss_tunipip6_dev_event,
+};
+
+/*
+ * nss_tunipip6_init_module()
+ *	Tunnel ipip6 module init function
+ */
+int __init nss_tunipip6_init_module(void)
+{
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return 0;
+	}
+#endif
+	nss_tunipip6_info("module (platform - IPQ806x , %s) loaded\n",
+			  NSS_CLIENT_BUILD_ID);
+
+	/*
+	 * Initialize lock and dev list.
+	 */
+	INIT_LIST_HEAD(&tunipip6_ctx.dev_list);
+	spin_lock_init(&tunipip6_ctx.lock);
+
+	/*
+	 * Create the debugfs directory for statistics.
+	 */
+	if (!nss_tunipip6_stats_dentry_init()) {
+		nss_tunipip6_trace("Failed to initialize debugfs\n");
+		return -1;
+	}
+
+	/*
+	 * Do not register net device notification for
+	 * custom tunnel. Net device notification is used only
+	 * for standard tunnel.
+	 */
+	if (!enable_custom) {
+		register_netdevice_notifier(&nss_tunipip6_notifier);
+		nss_tunipip6_trace("Netdev Notifier registerd\n");
+	}
+
+	/*
+	 * Register sysctl to add/delete/flush mapping rules.
+	 */
+	nss_tunipip6_sysctl_register();
+	nss_tunipip6_trace("Sysctl registerd\n");
+
+	return 0;
+}
+
+/*
+ * nss_tunipip6_exit_module()
+ *	Tunnel ipip6 module exit function
+ */
+void __exit nss_tunipip6_exit_module(void)
+{
+#ifdef CONFIG_OF
+
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		return;
+	}
+#endif
+
+	/*
+	 * Free Host and NSS tunipip6 instances.
+	 */
+	nss_tunipip6_destroy_interface_all();
+
+	/*
+	 * De-initialize debugfs.
+	 */
+	nss_tunipip6_stats_dentry_deinit();
+
+	/*
+	 * Unregister net device notification for standard tunnel.
+	 */
+	if (!enable_custom) {
+		unregister_netdevice_notifier(&nss_tunipip6_notifier);
+		nss_tunipip6_trace("Netdev Notifier unregisterd\n");
+	}
+
+	/*
+	 * Unregister sysctl.
+	 */
+	nss_tunipip6_sysctl_unregister();
+	nss_tunipip6_trace("Sysctl unregisterd\n");
+
+	nss_tunipip6_info("module unloaded\n");
+}
+
+module_init(nss_tunipip6_init_module);
+module_exit(nss_tunipip6_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS tunipip6 offload manager");
diff --git a/qca-nss-clients/tunipip6/nss_connmgr_tunipip6_priv.h b/qca-nss-clients/tunipip6/nss_connmgr_tunipip6_priv.h
new file mode 100644
index 0000000..3893038
--- /dev/null
+++ b/qca-nss-clients/tunipip6/nss_connmgr_tunipip6_priv.h
@@ -0,0 +1,94 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_CONNMGR_TUNIPIP6_PRIV_H_
+#define __NSS_CONNMGR_TUNIPIP6_PRIV_H_
+
+#include "nss_connmgr_tunipip6_stats.h"
+#include <linux/debugfs.h>
+
+/*
+ * tunipip6 context
+ */
+extern struct nss_tunipip6_context tunipip6_ctx;
+
+/*
+ * NSS tunipip6 debug macros
+ */
+#if (NSS_TUNIPIP6_DEBUG_LEVEL < 1)
+#define nss_tunipip6_assert(fmt, args...)
+#else
+#define nss_tunipip6_assert(c) if (!(c)) { BUG_ON(!(c)); }
+#endif
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_tunipip6_warning(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_tunipip6_info(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_tunipip6_trace(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#else /* CONFIG_DYNAMIC_DEBUG */
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_TUNIPIP6_DEBUG_LEVEL < 2)
+#define nss_tunipip6_warning(s, ...)
+#else
+#define nss_tunipip6_warning(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_TUNIPIP6_DEBUG_LEVEL < 3)
+#define nss_tunipip6_info(s, ...)
+#else
+#define nss_tunipip6_info(s, ...)   pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_TUNIPIP6_DEBUG_LEVEL < 4)
+#define nss_tunipip6_trace(s, ...)
+#else
+#define nss_tunipip6_trace(s, ...)  pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+extern struct nss_tunipip6_context tunipip6_ctx;
+
+/*
+ * tunipip6 global context structure.
+ */
+struct nss_tunipip6_context {
+	struct list_head dev_list;		/* List of tunipip6 interface instances */
+	struct dentry *tunipip6_dentry_dir;	/* tunipip6 debugfs directory entry */
+	spinlock_t lock;			/* Lock to protect list. */
+};
+
+/*
+ * tunipip6 interface instance structure.
+ */
+struct nss_tunipip6_instance {
+	struct list_head list;			/* List of tunipip6 interface instance */
+	struct net_device *dev;			/* tunipip6 netdevice */
+	struct dentry *dentry;			/* debugfs entry for this tunnel device */
+	struct nss_tunipip6_stats stats;	/* tunipip6 statistics */
+	uint32_t inner_ifnum;			/* tunipip6 inner dynamic interface */
+	uint32_t outer_ifnum;			/* tunipip6 outer dynamic interface */
+};
+
+struct nss_tunipip6_instance *nss_tunipip6_find_instance(struct net_device *dev);
+
+#endif /* __NSS_CONNMGR_TUNIPIP6_PRIV_H_ */
diff --git a/qca-nss-clients/tunipip6/nss_connmgr_tunipip6_stats.c b/qca-nss-clients/tunipip6/nss_connmgr_tunipip6_stats.c
new file mode 100644
index 0000000..c45255e
--- /dev/null
+++ b/qca-nss-clients/tunipip6/nss_connmgr_tunipip6_stats.c
@@ -0,0 +1,226 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <nss_api_if.h>
+#include "nss_connmgr_tunipip6_priv.h"
+
+/*
+ * nss_tunipip6_stats_str
+ *	tunipip6 statistics strings for NSS tunnel stats
+ */
+static int8_t *nss_tunipip6_stats_str[NSS_TUNIPIP6_STATS_MAX] = {
+	"rx pkts",
+	"rx bytes",
+	"tx pkts",
+	"tx bytes",
+	"rx queue 0 dropped",
+	"rx queue 1 dropped",
+	"rx queue 2 dropped",
+	"rx queue 3 dropped",
+	"encap low headroom",
+	"encap unhandled_protocol",
+	"encap enqueue fail",
+	"encap tunnel exist",
+	"encap total fmr_count",
+	"encap fmr add count",
+	"encap fmr del count",
+	"encap fmr flush count",
+	"encap fmr update_count",
+	"encap fmr add_fail count",
+	"encap fmr del_fail count",
+	"encap error no fmr",
+	"encap bmr add count",
+	"encap bmr del count",
+	"encap error bmr exist",
+	"encap error no bmr",
+	"decap enqueue fail",
+};
+
+/*
+ * nss_tunipip6_stats_show()
+ *	Read tunipip6 tunnel statistics
+ */
+static int nss_tunipip6_stats_show(struct seq_file *m, void __attribute__((unused))*p)
+{
+	int i;
+	struct nss_tunipip6_instance *tun_inst;
+	struct nss_tunipip6_stats *tunipip6_tunnel_stats;
+
+	tun_inst = vzalloc(sizeof(struct nss_tunipip6_instance));
+	if (!tun_inst) {
+		nss_tunipip6_warning("Failed to allocate memory for tun_inst\n");
+		return -ENOMEM;
+	}
+
+	tunipip6_tunnel_stats = vzalloc(sizeof(struct nss_tunipip6_stats));
+	if (!tunipip6_tunnel_stats) {
+		nss_tunipip6_warning("Failed to allocate memory for tunipip6_tunnel_stats\n");
+		vfree(tun_inst);
+		return -ENOMEM;
+	}
+
+	/*
+	 * Copy the tunnel and stats information from the tunnel instance.
+	 */
+	spin_lock_bh(&tunipip6_ctx.lock);
+	memcpy(tun_inst, m->private, sizeof(struct nss_tunipip6_instance));
+	memcpy(tunipip6_tunnel_stats, &tun_inst->stats, sizeof(struct nss_tunipip6_stats));
+	spin_unlock_bh(&tunipip6_ctx.lock);
+
+	seq_printf(m, "\n\tInner ifnum %u stats:\n", tun_inst->inner_ifnum);
+	for (i = 0; i < NSS_TUNIPIP6_STATS_MAX; i++) {
+		seq_printf(m, "\t\t%s = %llu\n",
+				nss_tunipip6_stats_str[i],
+				tunipip6_tunnel_stats->inner_stats[i]);
+	}
+
+	seq_printf(m, "\n\tOuter ifnum %u stats:\n", tun_inst->outer_ifnum);
+	for (i = 0; i < NSS_TUNIPIP6_STATS_MAX; i++) {
+		seq_printf(m, "\t\t%s = %llu\n",
+				nss_tunipip6_stats_str[i],
+				tunipip6_tunnel_stats->outer_stats[i]);
+	}
+
+	seq_printf(m, "\n%s tunnel stats end\n\n", tun_inst->dev->name);
+	vfree(tun_inst);
+	vfree(tunipip6_tunnel_stats);
+	return 0;
+}
+
+/*
+ * nss_tunipip6_stats_open()
+ */
+static int nss_tunipip6_stats_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, nss_tunipip6_stats_show, inode->i_private);
+}
+
+/*
+ * nss_tunipip6_stats_update()
+ *	Update inner or outer node statistics
+ */
+static void nss_tunipip6_stats_update(uint64_t *stats, struct nss_tunipip6_stats_sync_msg *stats_msg)
+{
+	uint32_t i, *src;
+	uint64_t *dest = stats;
+
+	src = &stats_msg->node_stats.rx_packets;
+	for (i = NSS_TUNIPIP6_STATS_RX_PKTS; i < NSS_TUNIPIP6_STATS_MAX; i++, src++, dest++) {
+		*dest += *src;
+	}
+}
+
+/*
+ * nss_tunipip6_stats_sync()
+ *	Sync function for tunipip6 statistics
+ */
+void nss_tunipip6_stats_sync(struct net_device *dev, struct nss_tunipip6_msg *ntm)
+{
+	uint32_t ifnum = ntm->cm.interface;
+	struct nss_tunipip6_stats_sync_msg *stats = &ntm->msg.stats;
+	struct nss_tunipip6_instance *ntii;
+	struct nss_tunipip6_stats *s;
+
+	spin_lock_bh(&tunipip6_ctx.lock);
+	ntii = nss_tunipip6_find_instance(dev);
+	if (!ntii) {
+		spin_unlock_bh(&tunipip6_ctx.lock);
+		nss_tunipip6_warning("%px: Not able to find context for device: %s\n", dev, dev->name);
+		return;
+	}
+
+	s = &ntii->stats;
+	if (ntii->inner_ifnum == ifnum) {
+		nss_tunipip6_stats_update(s->inner_stats, stats);
+		s->inner_stats[NSS_TUNIPIP6_STATS_CONFIG_ENCAP_TOTAL_FMR] = stats->tun_stats.encap.cfg.total_fmr;
+	} else if (ntii->outer_ifnum == ifnum) {
+		nss_tunipip6_stats_update(s->outer_stats, stats);
+	} else {
+		nss_tunipip6_warning("%px: Netdev=%s invalid interface number. Interface No: %u\n", dev, dev->name, ifnum);
+	}
+
+	spin_unlock_bh(&tunipip6_ctx.lock);
+}
+
+/*
+ * nss_tunipip6_stats_ops
+ *	File operations for tunipip6 tunnel stats
+ */
+static const struct file_operations nss_tunipip6_stats_ops = { \
+	.open = nss_tunipip6_stats_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = seq_release
+};
+
+/*
+ * nss_tunipip6_stats_dentry_destroy()
+ *	Remove debufs file for given tunnel.
+ */
+void nss_tunipip6_stats_dentry_destroy(struct nss_tunipip6_instance *tun_inst)
+{
+	debugfs_remove(tun_inst->dentry);
+}
+
+/*
+ * nss_tunipip6_stats_dentry_create()
+ *	Create dentry for a given tunnel.
+ */
+bool nss_tunipip6_stats_dentry_create(struct nss_tunipip6_instance *tun_inst)
+{
+	char dentry_name[IFNAMSIZ];
+
+	scnprintf(dentry_name, sizeof(dentry_name), "%s", tun_inst->dev->name);
+	tun_inst->dentry = debugfs_create_file(dentry_name, S_IRUGO,
+			tunipip6_ctx.tunipip6_dentry_dir, tun_inst, &nss_tunipip6_stats_ops);
+	if (!tun_inst->dentry) {
+		nss_tunipip6_warning("Debugfs file creation failed for tun %s\n", tun_inst->dev->name);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_tunipip6_stats_dentry_deinit()
+ *	Cleanup the debugfs tree.
+ */
+void nss_tunipip6_stats_dentry_deinit(void)
+{
+	if (tunipip6_ctx.tunipip6_dentry_dir) {
+		debugfs_remove_recursive(tunipip6_ctx.tunipip6_dentry_dir);
+	}
+}
+
+/*
+ * nss_tunipip6_stats_dentry_init()
+ *	Create tunipip6 tunnel statistics debugfs entry.
+ */
+bool nss_tunipip6_stats_dentry_init(void)
+{
+	/*
+	 * Initialize debugfs directory.
+	 */
+	tunipip6_ctx.tunipip6_dentry_dir = debugfs_create_dir("qca-nss-tunipip6", NULL);
+	if (!tunipip6_ctx.tunipip6_dentry_dir) {
+		nss_tunipip6_warning("Failed to create debug entry for subsystem: qca-nss-tunipip6\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-clients/tunipip6/nss_connmgr_tunipip6_stats.h b/qca-nss-clients/tunipip6/nss_connmgr_tunipip6_stats.h
new file mode 100644
index 0000000..bbe7311
--- /dev/null
+++ b/qca-nss-clients/tunipip6/nss_connmgr_tunipip6_stats.h
@@ -0,0 +1,73 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef _NSS_CONNMGR_TUNIPIP6_STATS_H_
+#define _NSS_CONNMGR_TUNIPIP6_STATS_H_
+
+struct nss_tunipip6_instance;
+
+/*
+ * tunipip6 statistic counters
+ */
+enum nss_tunipip6_stats_type {
+	NSS_TUNIPIP6_STATS_RX_PKTS,
+	NSS_TUNIPIP6_STATS_RX_BYTES,
+	NSS_TUNIPIP6_STATS_TX_PKTS,
+	NSS_TUNIPIP6_STATS_TX_BYTES,
+	NSS_TUNIPIP6_STATS_RX_QUEUE_0_DROPPED,
+	NSS_TUNIPIP6_STATS_RX_QUEUE_1_DROPPED,
+	NSS_TUNIPIP6_STATS_RX_QUEUE_2_DROPPED,
+	NSS_TUNIPIP6_STATS_RX_QUEUE_3_DROPPED,
+	NSS_TUNIPIP6_STATS_EXCEP_ENCAP_LOW_HEADROOM,
+	NSS_TUNIPIP6_STATS_EXCEP_ENCAP_UNHANDLED_PROTOCOL,
+	NSS_TUNIPIP6_STATS_DROP_ENCAP_ENQUEUE_FAIL,
+	NSS_TUNIPIP6_STATS_CONFIG_ERR_TUNNEL,
+	NSS_TUNIPIP6_STATS_CONFIG_ENCAP_TOTAL_FMR,
+	NSS_TUNIPIP6_STATS_CONFIG_ENCAP_FMR_ADD,
+	NSS_TUNIPIP6_STATS_CONFIG_ENCAP_FMR_DEL,
+	NSS_TUNIPIP6_STATS_CONFIG_ENCAP_FMR_FLUSH,
+	NSS_TUNIPIP6_STATS_CONFIG_ENCAP_FMR_UPDATE,
+	NSS_TUNIPIP6_STATS_CONFIG_ENCAP_FMR_ADD_FAIL,
+	NSS_TUNIPIP6_STATS_CONFIG_ENCAP_FMR_DEL_FAIL,
+	NSS_TUNIPIP6_STATS_CONFIG_ENCAP_ERR_NO_FMR,
+	NSS_TUNIPIP6_STATS_CONFIG_ENCAP_BMR_ADD,
+	NSS_TUNIPIP6_STATS_CONFIG_ENCAP_BMR_DEL,
+	NSS_TUNIPIP6_STATS_CONFIG_ENCAP_ERR_BMR_EXIST,
+	NSS_TUNIPIP6_STATS_CONFIG_ENCAP_ERR_NO_BMR,
+	NSS_TUNIPIP6_STATS_DROP_DECAP_ENQUEUE_FAIL,
+	NSS_TUNIPIP6_STATS_MAX,
+};
+
+/*
+ * tunipip6 statistics
+ */
+struct nss_tunipip6_stats {
+	uint64_t inner_stats[NSS_TUNIPIP6_STATS_MAX];
+	uint64_t outer_stats[NSS_TUNIPIP6_STATS_MAX];
+};
+
+/*
+ * tunipip6 statistics API
+ */
+extern void nss_tunipip6_stats_sync(struct net_device *dev, struct nss_tunipip6_msg *ntm);
+extern void nss_tunipip6_stats_dentry_deinit(void);
+extern bool nss_tunipip6_stats_dentry_init(void);
+extern void nss_tunipip6_stats_dentry_destroy(struct nss_tunipip6_instance *tun_inst);
+extern bool nss_tunipip6_stats_dentry_create(struct nss_tunipip6_instance *tun_inst);
+
+#endif /* _NSS_CONNMGR_TUNIPIP6_STATS_H_ */
diff --git a/qca-nss-clients/tunipip6/nss_connmgr_tunipip6_sysctl.c b/qca-nss-clients/tunipip6/nss_connmgr_tunipip6_sysctl.c
new file mode 100644
index 0000000..3632d62
--- /dev/null
+++ b/qca-nss-clients/tunipip6/nss_connmgr_tunipip6_sysctl.c
@@ -0,0 +1,502 @@
+ /*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/of.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <net/ipv6.h>
+#include <net/ip_tunnels.h>
+#include <net/ip6_tunnel.h>
+#include <linux/if_arp.h>
+#include <nss_api_if.h>
+#include <linux/sysctl.h>
+#include <linux/printk.h>
+#include <linux/inet.h>
+#include "nss_connmgr_tunipip6.h"
+
+#define MAX_PROC_SIZE 1024
+#define MAX_DATA_LEN 500
+#define MAX_IPV4_PREFIX_LEN 32
+#define MAX_IPV6_PREFIX_LEN 128
+#define MAX_PSID_OFFSET_LEN 15
+#define NETDEV_STR_LEN 30
+#define PREFIX_STR_LEN 100
+
+extern bool frag_id_update;
+
+unsigned char nss_tunipip6_data[MAX_DATA_LEN] __read_mostly;
+enum nss_tunipip6_sysctl_mode {
+	NSS_TUNIPIP6_SYSCTL_ADD_MAPRULE,
+	NSS_TUNIPIP6_SYSCTL_DEL_MAPRULE,
+	NSS_TUNIPIP6_SYSCTL_FLUSH_FMR_RULE,
+	NSS_TUNIPIP6_SYSCTL_FRAG_ID,
+};
+
+
+static int nss_tunipip6_data_parser(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos, enum nss_tunipip6_sysctl_mode mode)
+{
+	char dev_name[NETDEV_STR_LEN] = {0}, ipv6_prefix_str[PREFIX_STR_LEN] = {0}, ipv6_suffix_str[PREFIX_STR_LEN] = {0}, ipv4_prefix_str[PREFIX_STR_LEN] = {0};
+	uint32_t ipv6_prefix[4], ipv6_prefix_len, ipv6_suffix[4], ipv6_suffix_len, ipv4_prefix, ipv4_prefix_len, ea_len, psid_offset;
+	int rule_type = 0, frag_id = 0;
+	bool ipv6_prefix_valid = false, ipv6_prefix_len_valid = false, ipv6_suffix_valid = false;
+	bool ipv4_prefix_valid = false, ipv4_prefix_len_valid = false, ipv6_suffix_len_valid = false;
+	bool rule_type_valid = false, ea_len_valid = false, psid_offset_valid = false, netdev_valid = false;
+	struct nss_connmgr_tunipip6_maprule_cfg mrcfg = {0};
+	char *buf;
+	enum nss_connmgr_tunipip6_err_codes status;
+	struct net_device *dev = NULL;
+	char *pfree;
+	char *token;
+	int ret;
+	int count;
+
+        if (!write) {
+                return -EINVAL;
+        }
+
+	buf = kzalloc(MAX_PROC_SIZE, GFP_KERNEL);
+	if (!buf) {
+		return -ENOMEM;
+	}
+	pfree = buf;
+	count = *lenp;
+	if (count > MAX_PROC_SIZE) {
+		count = MAX_PROC_SIZE;
+	}
+
+	if (copy_from_user(buf, buffer, count)) {
+		kfree(pfree);
+		return -EFAULT;
+	}
+
+	while (buf) {
+		char *param, *value;
+		token = strsep(&buf, " \n");
+		if (token[0] == 0) {
+			continue;
+		}
+
+		param = strsep(&token, "=");
+		value = token;
+
+		if (!value || !param) {
+			kfree(pfree);
+			goto fail;
+		}
+
+		/*
+		 * Parse netdev and FMR parameters.
+		 */
+
+		if (!strcmp(param, "netdev")) {
+			strlcpy(dev_name, value, 30);
+			dev = dev_get_by_name(&init_net, dev_name);
+			if (!dev) {
+				kfree(pfree);
+				goto fail;
+			}
+			netdev_valid = true;
+			continue;
+		}
+
+		if (!strcmp(param, "rule_type")) {
+			if (!sscanf(value, "%u", &rule_type)) {
+				kfree(pfree);
+				goto fail;
+			}
+
+			if ((rule_type !=NSS_CONNMGR_TUNIPIP6_RULE_BMR) &&
+				       (rule_type != NSS_CONNMGR_TUNIPIP6_RULE_FMR)) {
+				kfree(pfree);
+				goto fail;
+			}
+			rule_type_valid = true;
+			continue;
+		}
+
+		if (!strcmp(param, "frag_id_update")) {
+			if (!sscanf(value, "%u", &frag_id)) {
+				kfree(pfree);
+				goto fail;
+			}
+
+			if (frag_id != 0 && frag_id != 1) {
+				kfree(pfree);
+				goto fail;
+			}
+			continue;
+		}
+
+		if (!strcmp(param, "ipv4_prefix")) {
+			strlcpy(ipv4_prefix_str, value, 30);
+			ret = in4_pton(ipv4_prefix_str, -1, (uint8_t *)&ipv4_prefix, -1, NULL);
+			if (ret != 1) {
+				kfree(pfree);
+				goto fail;
+			}
+			ipv4_prefix_valid = true;
+			continue;
+		}
+
+		if (!strcmp(param, "ipv4_prefix_len")) {
+			if (!sscanf(value, "%u", &ipv4_prefix_len)) {
+				kfree(pfree);
+				goto fail;
+			}
+
+			if (ipv4_prefix_len > MAX_IPV4_PREFIX_LEN) {
+				kfree(pfree);
+				goto fail;
+			}
+
+			ipv4_prefix_len_valid = true;
+			continue;
+		}
+
+		if (!strcmp(param, "ipv6_prefix")) {
+			strlcpy(ipv6_prefix_str, value, 100);
+			ret = in6_pton(ipv6_prefix_str, -1, (uint8_t *)&ipv6_prefix, -1, NULL);
+			if (ret != 1) {
+				kfree(pfree);
+				goto fail;
+			}
+			ipv6_prefix_valid = true;
+			continue;
+		}
+
+		if (!strcmp(param, "ipv6_prefix_len")) {
+			if (!sscanf(value, "%u", &ipv6_prefix_len)) {
+				kfree(pfree);
+				goto fail;
+			}
+
+			if (ipv6_prefix_len > MAX_IPV6_PREFIX_LEN) {
+				kfree(pfree);
+				goto fail;
+			}
+
+			ipv6_prefix_len_valid = true;
+			continue;
+		}
+
+		if (!strcmp(param, "ipv6_suffix")) {
+			strlcpy(ipv6_suffix_str, value, 100);
+			ret = in6_pton(ipv6_suffix_str, -1, (uint8_t *)&ipv6_suffix, -1, NULL);
+			if (ret != 1) {
+				kfree(pfree);
+				goto fail;
+			}
+			ipv6_suffix_valid = true;
+			continue;
+		}
+
+		if (!strcmp(param, "ipv6_suffix_len")) {
+			if (!sscanf(value, "%u", &ipv6_suffix_len)) {
+				kfree(pfree);
+				goto fail;
+			}
+
+			if (ipv6_suffix_len > MAX_IPV6_PREFIX_LEN) {
+				kfree(pfree);
+				goto fail;
+			}
+
+			ipv6_suffix_len_valid = true;
+			continue;
+		}
+
+		if (!strcmp(param, "ea_len")) {
+			if (!sscanf(value, "%u", &ea_len)) {
+				kfree(pfree);
+				goto fail;
+			}
+
+			ea_len_valid = true;
+			continue;
+		}
+
+		if (!strcmp(param, "psid_offset")) {
+			if (!sscanf(value, "%u", &psid_offset)) {
+				kfree(pfree);
+				goto fail;
+			}
+
+			if (psid_offset> MAX_PSID_OFFSET_LEN) {
+				kfree(pfree);
+				goto fail;
+			}
+
+			psid_offset_valid = true;
+			continue;
+		}
+	}
+
+	kfree(pfree);
+
+	/*
+	 * Netdev param is not needed only for frag_id command
+	 */
+	if (!netdev_valid && mode != NSS_TUNIPIP6_SYSCTL_FRAG_ID) {
+		goto fail;
+	}
+
+	switch(mode) {
+	case NSS_TUNIPIP6_SYSCTL_DEL_MAPRULE:
+		if (!rule_type_valid ) {
+			goto fail;
+		}
+
+		/*
+		 * BMR delete will follow this and FMR delete will fall through.
+		 */
+		if (rule_type == NSS_CONNMGR_TUNIPIP6_RULE_BMR) {
+			if ((ipv6_prefix_valid || ipv6_prefix_len_valid || ipv6_suffix_valid ||
+				ipv4_prefix_valid || ipv4_prefix_len_valid || ea_len_valid ||
+				psid_offset_valid)) {
+				goto fail;
+			}
+
+			mrcfg.rule_type = rule_type;
+			status = nss_connmgr_tunipip6_del_maprule(dev, &mrcfg);
+			if (status == NSS_CONNMGR_TUNIPIP6_SUCCESS) {
+				pr_info("Map Rule delete success for netdev: %s\n", dev->name);
+			} else {
+				pr_info("Map Rule delete failure for netdev: %s\n", dev->name);
+			}
+			break;
+		}
+#if __has_attribute(__fallthrough__)
+	__attribute__((__fallthrough__));
+#endif
+	case NSS_TUNIPIP6_SYSCTL_ADD_MAPRULE:
+		if (!(rule_type_valid && ipv6_prefix_valid && ipv6_prefix_len_valid && ipv6_suffix_valid &&
+			ipv4_prefix_valid && ipv4_prefix_len_valid && ea_len_valid &&
+			psid_offset_valid)) {
+			goto fail;
+		}
+
+		mrcfg.rule_type = rule_type;
+		mrcfg.ipv6_prefix[0] = ntohl(ipv6_prefix[0]);
+		mrcfg.ipv6_prefix[1] = ntohl(ipv6_prefix[1]);
+		mrcfg.ipv6_prefix[2] = ntohl(ipv6_prefix[2]);
+		mrcfg.ipv6_prefix[3] = ntohl(ipv6_prefix[3]);
+		mrcfg.ipv6_prefix_len = ipv6_prefix_len;
+
+		mrcfg.ipv4_prefix = ntohl(ipv4_prefix);
+		mrcfg.ipv4_prefix_len = ipv4_prefix_len;
+
+		mrcfg.ipv6_suffix[0] = ntohl(ipv6_suffix[0]);
+		mrcfg.ipv6_suffix[1] = ntohl(ipv6_suffix[1]);
+		mrcfg.ipv6_suffix[2] = ntohl(ipv6_suffix[2]);
+		mrcfg.ipv6_suffix[3] = ntohl(ipv6_suffix[3]);
+		mrcfg.ipv6_suffix_len = ipv6_suffix_len;
+
+		mrcfg.ea_len = ea_len;
+		mrcfg.psid_offset = psid_offset;
+
+		if (mode == NSS_TUNIPIP6_SYSCTL_ADD_MAPRULE) {
+			status = nss_connmgr_tunipip6_add_maprule(dev, &mrcfg);
+			if (status == NSS_CONNMGR_TUNIPIP6_SUCCESS) {
+				pr_info("Map Rule create success for netdev: %s\n", dev->name);
+			} else {
+				pr_info("Map Rule create failure for netdev: %s\n", dev->name);
+			}
+		} else {
+			status = nss_connmgr_tunipip6_del_maprule(dev, &mrcfg);
+			if (status == NSS_CONNMGR_TUNIPIP6_SUCCESS) {
+				pr_info("Map Rule delete success for netdev: %s\n", dev->name);
+			} else {
+				pr_info("Map Rule delete failure for netdev: %s\n", dev->name);
+			}
+		}
+		break;
+
+	case NSS_TUNIPIP6_SYSCTL_FLUSH_FMR_RULE:
+		status = nss_connmgr_tunipip6_flush_fmr_rule(dev);
+		if (status == NSS_CONNMGR_TUNIPIP6_SUCCESS) {
+			pr_info("Map Rule flush success for netdev: %s\n", dev->name);
+		} else {
+			pr_info("Map Rule flush failed for netdev: %s\n", dev->name);
+		}
+		break;
+
+	case NSS_TUNIPIP6_SYSCTL_FRAG_ID:
+		if ((netdev_valid || rule_type_valid || ipv6_prefix_valid || ipv6_prefix_len_valid || ipv6_suffix_valid ||
+				ipv4_prefix_valid || ipv4_prefix_len_valid || ea_len_valid ||
+				psid_offset_valid)) {
+				goto fail;
+		}
+
+		if (frag_id) {
+			frag_id_update = true;
+			pr_info("Frag Id enabled for all tunnels.\n");
+		} else {
+			frag_id_update = false;
+			pr_info("Frag Id disabled for all tunnels.\n");
+		}
+		return 0;
+	}
+
+	dev_put(dev);
+	return 0;
+
+fail:
+	if (dev) {
+		dev_put(dev);
+	}
+
+	pr_info("Wrong input, check help. (cat /proc/sys/dev/nss/ipip6/help)\n");
+	return 0;
+}
+
+static int nss_tunipip6_cmd_procfs_add_maprule(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	return nss_tunipip6_data_parser(ctl, write, buffer, lenp, ppos, NSS_TUNIPIP6_SYSCTL_ADD_MAPRULE);
+}
+
+static int nss_tunipip6_cmd_procfs_del_maprule(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	return nss_tunipip6_data_parser(ctl, write, buffer, lenp, ppos, NSS_TUNIPIP6_SYSCTL_DEL_MAPRULE);
+}
+
+static int nss_tunipip6_cmd_procfs_flush_fmr_rule(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	return nss_tunipip6_data_parser(ctl, write, buffer, lenp, ppos, NSS_TUNIPIP6_SYSCTL_FLUSH_FMR_RULE);
+}
+
+static int nss_tunipip6_cmd_procfs_enable_frag_id(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	return nss_tunipip6_data_parser(ctl, write, buffer, lenp, ppos, NSS_TUNIPIP6_SYSCTL_FRAG_ID);
+}
+
+static int nss_tunipip6_cmd_procfs_read_help(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+
+	pr_info("\nHelp: (/proc/sys/dev/nss/ipip6/help) \n\
+			1. To add maprule(rule_type=1(BMR)/2(FMR)):\n\
+			echo dev=<map-mape/MAP-E netdevice> rule_type=<1/2> ipv6_prefix=<XXXX::XXXX> ipv6_prefix_len=<XX> ipv4_prefix=<X.X.X.X> ipv4_prefix_len=<XX> \n\
+			ipv6_suffix=<XXXX::XXXX> ipv6_sufffix_len=<XX> ea_len=<XX> psid_offset=<XX> > add_map_rule \n\
+			2. a. To delete maprule(FMR):\n\
+			echo dev=<map-mape/MAP-E netdevice> rule_type=<2> ipv6_prefix=<XXXX::XXXX> ipv6_prefix_len=<XX> ipv4_prefix=<X.X.X.X> ipv4_prefix_len=<XX> \n\
+			ipv6_suffix=<XXXX::XXXX> ipv6_sufffix_len=<XX> ea_len=<XX> psid_offset=<XX> > remove_map_rule \n\
+			b. To delete maprule(BMR):\n\
+			echo dev=<map-mape/MAP-E netdevice> rule_type=<1> > remove_map_rule\n\
+			3. To flush FMR entries:\n\
+			echo dev=<map-mape/MAP-E netdevice> > flush_fmr_rule\n");
+	pr_info("\t\t\t4. To enable/disable frag id: \n\
+			echo frag_id_update=<0/1> > frag_id \n\
+			=====end of help=====\n");
+	*lenp = 0;
+	return ret;
+}
+
+static struct ctl_table nss_tunipip6_table[] = {
+	{
+		.procname		= "add_map_rule",
+		.data			= &nss_tunipip6_data,
+		.maxlen			= sizeof(nss_tunipip6_data),
+		.mode			= 0644,
+		.proc_handler		= &nss_tunipip6_cmd_procfs_add_maprule,
+	},
+	{
+		.procname		= "remove_map_rule",
+		.data			= &nss_tunipip6_data,
+		.maxlen			= sizeof(nss_tunipip6_data),
+		.mode			= 0644,
+		.proc_handler		= &nss_tunipip6_cmd_procfs_del_maprule,
+	},
+	{
+		.procname		= "flush_fmr_rule",
+		.data			= &nss_tunipip6_data,
+		.maxlen			= sizeof(nss_tunipip6_data),
+		.mode			= 0644,
+		.proc_handler		= &nss_tunipip6_cmd_procfs_flush_fmr_rule,
+	},
+	{
+		.procname               = "frag_id",
+		.data                   = &nss_tunipip6_data,
+		.maxlen                 = sizeof(nss_tunipip6_data),
+		.mode                   = 0644,
+		.proc_handler           = &nss_tunipip6_cmd_procfs_enable_frag_id,
+	},
+	{
+		.procname		= "help",
+		.data			= &nss_tunipip6_data,
+		.maxlen			= sizeof(nss_tunipip6_data),
+		.mode			= 0400,
+		.proc_handler		= &nss_tunipip6_cmd_procfs_read_help,
+	},
+	{ }
+};
+
+static struct ctl_table nss_tunipip6_root_dir[] = {
+	{
+		.procname		= "ipip6",
+		.mode			= 0555,
+		.child			= nss_tunipip6_table,
+	},
+	{ }
+};
+
+static struct ctl_table nss_tunipip6_nss_root_dir[] = {
+	{
+		.procname		= "nss",
+		.mode			= 0555,
+		.child			= nss_tunipip6_root_dir,
+	},
+	{ }
+};
+
+static struct ctl_table nss_tunipip6_root[] = {
+	{
+		.procname		= "dev",
+		.mode			= 0555,
+		.child			= nss_tunipip6_nss_root_dir,
+	},
+	{ }
+};
+
+static struct ctl_table_header *nss_tunipip6_ctl_header;
+
+/*
+ * nss_tunipip6_sysctl_register()
+ * 	Register command line interface for tunipip6.
+ */
+bool nss_tunipip6_sysctl_register(void) {
+	nss_tunipip6_ctl_header = register_sysctl_table(nss_tunipip6_root);
+	if (!nss_tunipip6_ctl_header) {
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_tunipip6_sysctl_unregister()
+ * 	Unregister command line interface for tunipip6.
+ */
+void nss_tunipip6_sysctl_unregister(void) {
+	if (nss_tunipip6_ctl_header) {
+		unregister_sysctl_table(nss_tunipip6_ctl_header);
+	}
+}
diff --git a/qca-nss-clients/tunipip6/nss_connmgr_tunipip6_sysctl.h b/qca-nss-clients/tunipip6/nss_connmgr_tunipip6_sysctl.h
new file mode 100644
index 0000000..eb82bd4
--- /dev/null
+++ b/qca-nss-clients/tunipip6/nss_connmgr_tunipip6_sysctl.h
@@ -0,0 +1,24 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef _NSS_CONNMGR_TUNIPIP6_SYSCTL_
+#define _NSS_CONNMGR_TUNIPIP6_SYSCTL_
+
+bool nss_tunipip6_sysctl_register(void);
+void nss_tunipip6_sysctl_unregister(void);
+#endif
diff --git a/qca-nss-clients/vlan/Makefile b/qca-nss-clients/vlan/Makefile
new file mode 100644
index 0000000..7882c47
--- /dev/null
+++ b/qca-nss-clients/vlan/Makefile
@@ -0,0 +1,16 @@
+ccflags-y := -I$(obj)/../exports -I$(obj)/..  -I$(obj)/nss_hal/include
+ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)"
+
+obj-m += qca-nss-vlan.o
+qca-nss-vlan-objs := nss_vlan_mgr.o
+
+ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64 ipq60xx ipq60xx_64))
+ccflags-y += -DNSS_VLAN_MGR_PPE_SUPPORT
+endif
+
+ccflags-y += -DNSS_VLAN_MGR_DEBUG_LEVEL=0
+ccflags-y += -Wall -Werror
+
+ifneq (,$(filter $(CONFIG_BONDING),y m))
+ccflags-y += -DBONDING_SUPPORT
+endif
diff --git a/qca-nss-clients/vlan/nss_vlan_mgr.c b/qca-nss-clients/vlan/nss_vlan_mgr.c
new file mode 100644
index 0000000..6329e95
--- /dev/null
+++ b/qca-nss-clients/vlan/nss_vlan_mgr.c
@@ -0,0 +1,1940 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_vlan_mgr.c
+ *	NSS to HLOS vlan Interface manager
+ */
+#include <linux/etherdevice.h>
+#include <linux/if_vlan.h>
+#include <linux/proc_fs.h>
+#include <linux/sysctl.h>
+#include <linux/module.h>
+#include <net/bonding.h>
+#include <nss_api_if.h>
+#ifdef NSS_VLAN_MGR_PPE_SUPPORT
+#include <ref/ref_vsi.h>
+#include <fal/fal_portvlan.h>
+#include <fal/fal_stp.h>
+#endif
+
+#if (NSS_VLAN_MGR_DEBUG_LEVEL < 1)
+#define nss_vlan_mgr_assert(fmt, args...)
+#else
+#define nss_vlan_mgr_assert(c) BUG_ON(!(c))
+#endif /* NSS_VLAN_MGR_DEBUG_LEVEL */
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_vlan_mgr_warn(s, ...) \
+		pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_vlan_mgr_info(s, ...) \
+		pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define nss_vlan_mgr_trace(s, ...) \
+		pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#else /* CONFIG_DYNAMIC_DEBUG */
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_VLAN_MGR_DEBUG_LEVEL < 2)
+#define nss_vlan_mgr_warn(s, ...)
+#else
+#define nss_vlan_mgr_warn(s, ...) \
+		pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_VLAN_MGR_DEBUG_LEVEL < 3)
+#define nss_vlan_mgr_info(s, ...)
+#else
+#define nss_vlan_mgr_info(s, ...) \
+		pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_VLAN_MGR_DEBUG_LEVEL < 4)
+#define nss_vlan_mgr_trace(s, ...)
+#else
+#define nss_vlan_mgr_trace(s, ...) \
+		pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+#define NSS_VLAN_PHY_PORT_MIN 1
+#define NSS_VLAN_PHY_PORT_MAX 6
+#define NSS_VLAN_PHY_PORT_NUM 8
+#define NSS_VLAN_PHY_PORT_CHK(n) ((n) >= NSS_VLAN_PHY_PORT_MIN && (n) <= NSS_VLAN_PHY_PORT_MAX)
+#define NSS_VLAN_MGR_TAG_CNT(v) ((v->parent) ? NSS_VLAN_TYPE_DOUBLE : NSS_VLAN_TYPE_SINGLE)
+#define NSS_VLAN_TPID_SHIFT 16
+#define NSS_VLAN_PORT_ROLE_CHANGED 1
+
+#define NSS_VLAN_MGR_SWITCH_ID 0
+#define NSS_VLAN_MGR_STP_ID 0
+
+/*
+ * vlan client context
+ */
+struct nss_vlan_mgr_context {
+	int ctpid;				/* Customer TPID */
+	int stpid;				/* Service TPID */
+	int port_role[NSS_VLAN_PHY_PORT_NUM];	/* Role of physical ports */
+	struct list_head list;			/* List of vlan private instance */
+	spinlock_t lock;			/* Lock to protect vlan private instance */
+	struct ctl_table_header *sys_hdr;	/* "/pro/sys/nss/vlan_client" directory */
+} vlan_mgr_ctx;
+
+/*
+ * vlan manager private structure
+ */
+struct nss_vlan_pvt {
+	struct list_head list;			/* list head */
+	struct nss_vlan_pvt *parent;		/* parent vlan instance */
+	uint32_t nss_if;			/* nss interface number of this vlan device */
+
+	/*
+	 * Fields for Linux information
+	 */
+	int ifindex;				/* netdev ifindex */
+	int32_t port[NSS_VLAN_PHY_PORT_MAX];	/* real physical port of this vlan */
+	int32_t bond_ifnum;			/* bond interface number, if vlan is created over bond */
+	uint32_t vid;				/* vid info */
+	uint32_t tpid;				/* tpid info */
+	uint32_t mtu;				/* mtu info */
+	uint8_t dev_addr[ETH_ALEN];		/* mac address */
+
+#ifdef NSS_VLAN_MGR_PPE_SUPPORT
+	/*
+	 * Fields for PPE information
+	 */
+	uint32_t ppe_vsi;			/* VLAN VSI info */
+	uint32_t bridge_vsi;			/* Bridge's VSI when vlan is a member of a bridge */
+	uint32_t ppe_cvid;			/* ppe_cvid info */
+	uint32_t ppe_svid;			/* ppe_svid info */
+	fal_vlan_trans_adv_rule_t eg_xlt_rule;	/* VLAN Translation Rule */
+	fal_vlan_trans_adv_action_t eg_xlt_action;	/* VLAN Translation Action */
+#endif
+	int refs;				/* reference count */
+};
+
+/*
+ * nss_vlan_mgr_instance_find_and_ref()
+ */
+static struct nss_vlan_pvt *nss_vlan_mgr_instance_find_and_ref(
+						struct net_device *dev)
+{
+	struct nss_vlan_pvt *v;
+
+	if (!is_vlan_dev(dev)) {
+		return NULL;
+	}
+
+	spin_lock(&vlan_mgr_ctx.lock);
+	list_for_each_entry(v, &vlan_mgr_ctx.list, list) {
+		if (v->ifindex == dev->ifindex) {
+			v->refs++;
+			spin_unlock(&vlan_mgr_ctx.lock);
+			return v;
+		}
+	}
+	spin_unlock(&vlan_mgr_ctx.lock);
+
+	return NULL;
+}
+
+/*
+ * nss_vlan_mgr_instance_deref()
+ */
+static void nss_vlan_mgr_instance_deref(struct nss_vlan_pvt *v)
+{
+	spin_lock(&vlan_mgr_ctx.lock);
+	BUG_ON(!(--v->refs));
+	spin_unlock(&vlan_mgr_ctx.lock);
+}
+
+#ifdef NSS_VLAN_MGR_PPE_SUPPORT
+/*
+ * nss_vlan_mgr_calculate_new_port_role()
+ *	check if we can change this port to edge port
+ */
+static bool nss_vlan_mgr_calculate_new_port_role(int32_t port,
+						int32_t portindex)
+{
+	struct nss_vlan_pvt *vif;
+	bool to_edge_port = true;
+
+	if (vlan_mgr_ctx.port_role[port] == FAL_QINQ_EDGE_PORT)
+		return false;
+
+	if (vlan_mgr_ctx.ctpid != vlan_mgr_ctx.stpid)
+		return false;
+
+	/*
+	 * If no other double VLAN interface on the same physcial port,
+	 * we set physical port as edge port
+	 */
+	spin_lock(&vlan_mgr_ctx.lock);
+	list_for_each_entry(vif, &vlan_mgr_ctx.list, list) {
+		if ((vif->port[portindex] == port) && (vif->parent)) {
+			to_edge_port = false;
+			break;
+		}
+	}
+	spin_unlock(&vlan_mgr_ctx.lock);
+
+	if (to_edge_port) {
+		fal_port_qinq_role_t mode;
+
+		mode.mask = FAL_PORT_QINQ_ROLE_INGRESS_EN | FAL_PORT_QINQ_ROLE_EGRESS_EN;
+		mode.ingress_port_role = FAL_QINQ_EDGE_PORT;
+		mode.egress_port_role = FAL_QINQ_EDGE_PORT;
+
+		if (fal_port_qinq_mode_set(NSS_VLAN_MGR_SWITCH_ID, port, &mode)) {
+			nss_vlan_mgr_warn("failed to set %d as edge port\n", port);
+			return false;
+		}
+
+		vlan_mgr_ctx.port_role[port] = FAL_QINQ_EDGE_PORT;
+	}
+
+	return to_edge_port;
+}
+
+/*
+ * nss_vlan_mgr_port_role_update()
+ *	Update physical port role between EDGE and CORE.
+ */
+static void nss_vlan_mgr_port_role_update(struct nss_vlan_pvt *vif,
+					uint32_t new_ppe_cvid,
+					uint32_t new_ppe_svid,
+					uint32_t port_id)
+{
+	int rc;
+
+	/*
+	 * Delete old ingress vlan translation rule
+	 */
+	rc = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, port_id, vif->ppe_svid, vif->ppe_cvid, PPE_VSI_INVALID);
+	if (rc != SW_OK) {
+		nss_vlan_mgr_warn("Failed to delete old ingress vlan translation rule of port %d, error: %d\n", port_id, rc);
+		return;
+	}
+
+	/*
+	 * Delete old egress vlan translation rule
+	 */
+	rc = fal_port_vlan_trans_adv_del(NSS_VLAN_MGR_SWITCH_ID, port_id,
+			FAL_PORT_VLAN_EGRESS,
+			&vif->eg_xlt_rule, &vif->eg_xlt_action);
+	if (rc != SW_OK) {
+		nss_vlan_mgr_warn("Failed to delete old egress vlan translation of port %d, error: %d\n", port_id, rc);
+		return;
+	}
+
+	/*
+	 * Update ppe_civd and ppe_svid
+	 */
+	vif->ppe_cvid = new_ppe_cvid;
+	vif->ppe_svid = new_ppe_svid;
+
+	/*
+	 * Add new ingress vlan translation rule
+	 */
+	rc = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, port_id, vif->ppe_svid,
+				vif->ppe_cvid,
+				(vif->bridge_vsi ? vif->bridge_vsi : vif->ppe_vsi));
+	if (rc != SW_OK) {
+		nss_vlan_mgr_warn("Failed to update ingress vlan translation of port %d, error: %d\n", port_id, rc);
+		return;
+	}
+
+	/*
+	 * Add new egress vlan translation rule
+	 */
+	vif->eg_xlt_action.cvid_xlt_cmd = (vif->ppe_cvid == FAL_VLAN_INVALID) ? 0 : FAL_VID_XLT_CMD_ADDORREPLACE;
+	vif->eg_xlt_action.cvid_xlt = (vif->ppe_cvid == FAL_VLAN_INVALID) ? 0 : vif->ppe_cvid;
+	vif->eg_xlt_action.svid_xlt_cmd = (vif->ppe_svid == FAL_VLAN_INVALID) ? 0 : FAL_VID_XLT_CMD_ADDORREPLACE;
+	vif->eg_xlt_action.svid_xlt = (vif->ppe_svid == FAL_VLAN_INVALID) ? 0 : vif->ppe_svid;
+
+	rc = fal_port_vlan_trans_adv_add(NSS_VLAN_MGR_SWITCH_ID, port_id,
+			FAL_PORT_VLAN_EGRESS, &vif->eg_xlt_rule, &vif->eg_xlt_action);
+	if (rc != SW_OK)
+		nss_vlan_mgr_warn("Failed to update egress vlan translation of port: %d. error: %d\n", port_id, rc);
+}
+
+/*
+ * nss_vlan_mgr_port_role_over_bond_update()
+ *	Update port role for bond slaves.
+ */
+static void nss_vlan_mgr_port_role_over_bond_update(struct nss_vlan_pvt *vif,
+					uint32_t new_ppe_cvid,
+					uint32_t new_ppe_svid)
+{
+	int i;
+	fal_vid_xlt_cmd_t old_cvid_xlt_cmd, old_svid_xlt_cmd;
+	uint32_t old_cvid_xlt, old_svid_xlt;
+
+	vif->eg_xlt_rule.port_bitmap = 0;
+
+	/*
+	 * For vlan over bond, the vif->eg_xlt_action will be modified while
+	 * updating the first slave. Hence we need to store the old vif->eg_xlt_action
+	 * and pass the same to modify the existing entry for the other ports/slaves. After
+	 * modification of all ports we should update vif->eg_xlt_action with the
+	 * new value which is passed to ssdk.
+	 */
+	old_cvid_xlt_cmd = vif->eg_xlt_action.cvid_xlt_cmd;
+	old_cvid_xlt = vif->eg_xlt_action.cvid_xlt;
+	old_svid_xlt_cmd = vif->eg_xlt_action.svid_xlt_cmd;
+	old_svid_xlt = vif->eg_xlt_action.svid_xlt;
+	for (i = 0; i < NSS_VLAN_PHY_PORT_MAX; i++) {
+		if (!vif->port[i])
+			continue;
+		vif->eg_xlt_rule.port_bitmap |= (1 << vif->port[i]);
+		nss_vlan_mgr_port_role_update(vif, new_ppe_cvid, new_ppe_svid, vif->port[i]);
+
+		/*
+		 * Update vif->eg_xlt_action with old value to modify the entry
+		 * for next port/slave
+		 */
+		vif->eg_xlt_action.cvid_xlt_cmd = old_cvid_xlt_cmd;
+		vif->eg_xlt_action.cvid_xlt = old_cvid_xlt;
+		vif->eg_xlt_action.svid_xlt_cmd = old_svid_xlt_cmd;
+		vif->eg_xlt_action.svid_xlt = old_svid_xlt;
+	}
+
+	/*
+	 * All ports/slaves are updated now, reset the vif->eg_xlt_action
+	 * with the value that is passed to ssdk.
+	 */
+	vif->eg_xlt_action.cvid_xlt_cmd = (vif->ppe_cvid == FAL_VLAN_INVALID) ? 0 : FAL_VID_XLT_CMD_ADDORREPLACE;
+	vif->eg_xlt_action.cvid_xlt = (vif->ppe_cvid == FAL_VLAN_INVALID) ? 0 : vif->ppe_cvid;
+	vif->eg_xlt_action.svid_xlt_cmd = (vif->ppe_svid == FAL_VLAN_INVALID) ? 0 : FAL_VID_XLT_CMD_ADDORREPLACE;
+	vif->eg_xlt_action.svid_xlt = (vif->ppe_svid == FAL_VLAN_INVALID) ? 0 : vif->ppe_svid;
+}
+
+/*
+ * nss_vlan_mgr_port_role_event()
+ *	Decide port role updation for bond or physical device
+ */
+static void nss_vlan_mgr_port_role_event(int32_t port, int portindex)
+{
+	struct nss_vlan_pvt *vif;
+	bool vlan_over_bond = false;
+
+	if (vlan_mgr_ctx.ctpid != vlan_mgr_ctx.stpid)
+		return;
+
+	spin_lock(&vlan_mgr_ctx.lock);
+	list_for_each_entry(vif, &vlan_mgr_ctx.list, list) {
+		if ((vif->port[portindex] == port) && (!vif->parent)) {
+			vlan_over_bond = vif->bond_ifnum ? true : false;
+			if ((vlan_mgr_ctx.port_role[port] == FAL_QINQ_EDGE_PORT) &&
+			    (vif->vid != vif->ppe_cvid)) {
+				if (!vlan_over_bond)
+					nss_vlan_mgr_port_role_update(vif, vif->vid, PPE_VSI_INVALID, vif->port[0]);
+				else
+					nss_vlan_mgr_port_role_over_bond_update(vif, vif->vid, PPE_VSI_INVALID);
+			}
+
+			if ((vlan_mgr_ctx.port_role[port] == FAL_QINQ_CORE_PORT) &&
+			    (vif->vid != vif->ppe_svid)) {
+				if (!vlan_over_bond)
+					nss_vlan_mgr_port_role_update(vif, PPE_VSI_INVALID, vif->vid, vif->port[0]);
+				else
+					nss_vlan_mgr_port_role_over_bond_update(vif, PPE_VSI_INVALID, vif->vid);
+			}
+		}
+	}
+	spin_unlock(&vlan_mgr_ctx.lock);
+}
+
+/*
+ * nss_vlan_mgr_bond_configure_ppe()
+ *	Configure PPE for bond device
+ */
+static int nss_vlan_mgr_bond_configure_ppe(struct nss_vlan_pvt *v, struct net_device *bond_dev)
+{
+	uint32_t vsi;
+	int ret = 0;
+	struct net_device *slave;
+	int32_t port;
+	int vlan_mgr_bond_port_role = -1;
+
+	if (ppe_vsi_alloc(NSS_VLAN_MGR_SWITCH_ID, &vsi)) {
+		nss_vlan_mgr_warn("%s: failed to allocate VSI for bond vlan device", bond_dev->name);
+		return -1;
+	}
+
+	if (nss_vlan_tx_vsi_attach_msg(v->nss_if, vsi) != NSS_TX_SUCCESS) {
+		nss_vlan_mgr_warn("%s: failed to attach VSI to bond vlan interface\n", bond_dev->name);
+		goto free_vsi;
+	}
+
+	/*
+	 * Set vlan_mgr_bond_port_role and check
+	 * if all the bond slaves are physical ports
+	 */
+	rcu_read_lock();
+	for_each_netdev_in_bond_rcu(bond_dev, slave) {
+		port = nss_cmn_get_interface_number_by_dev(slave);
+		if (!NSS_VLAN_PHY_PORT_CHK(port)) {
+			rcu_read_unlock();
+			nss_vlan_mgr_warn("%s: %d is not valid physical port\n", slave->name, port);
+			goto free_vsi;
+		}
+
+		/*
+		 * vlan_mgr_bond_port_role is same for all the slaves in the bond group
+		 */
+		if (vlan_mgr_bond_port_role == -1) {
+			vlan_mgr_bond_port_role = vlan_mgr_ctx.port_role[port];
+		}
+	}
+	rcu_read_unlock();
+
+	/*
+	 * In case the bond interface has no slaves, we do not want to proceed further
+	 */
+	if (vlan_mgr_bond_port_role == -1) {
+		goto free_vsi;
+	}
+
+	/*
+	 * Calculate ppe cvid and svid
+	 */
+	if (NSS_VLAN_MGR_TAG_CNT(v) == NSS_VLAN_TYPE_DOUBLE) {
+		v->ppe_cvid = v->vid;
+		v->ppe_svid = v->parent->vid;
+	} else {
+		if (((vlan_mgr_ctx.ctpid != vlan_mgr_ctx.stpid) && (v->tpid == vlan_mgr_ctx.ctpid)) ||
+				((vlan_mgr_ctx.ctpid == vlan_mgr_ctx.stpid) &&
+				 (vlan_mgr_bond_port_role == FAL_QINQ_EDGE_PORT))) {
+			v->ppe_cvid = v->vid;
+			v->ppe_svid = FAL_VLAN_INVALID;
+		} else {
+			v->ppe_cvid = FAL_VLAN_INVALID;
+			v->ppe_svid = v->vid;
+		}
+	}
+
+	/*
+	 * Add ingress vlan translation rule
+	 */
+	rcu_read_lock();
+	for_each_netdev_in_bond_rcu(bond_dev, slave) {
+		port = nss_cmn_get_interface_number_by_dev(slave);
+		ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1], v->ppe_svid, v->ppe_cvid, vsi);
+		if (ret != SW_OK) {
+			rcu_read_unlock();
+			nss_vlan_mgr_warn("bond:%s -> slave:%s: failed to set ingress vlan translation, error: %d\n", bond_dev->name, slave->name, ret);
+			goto detach_vsi;
+		}
+	}
+	rcu_read_unlock();
+
+	/*
+	 * Add egress vlan translation rule
+	 */
+	memset(&v->eg_xlt_rule, 0, sizeof(v->eg_xlt_rule));
+	memset(&v->eg_xlt_action, 0, sizeof(v->eg_xlt_action));
+
+	/*
+	 * Fields for match
+	 */
+	v->eg_xlt_rule.vsi_valid = true;	/* Use vsi as search key*/
+	v->eg_xlt_rule.vsi_enable = true;	/* Use vsi as search key*/
+	v->eg_xlt_rule.vsi = vsi;		/* Use vsi as search key*/
+	v->eg_xlt_rule.s_tagged = 0x7;		/* Accept tagged/untagged/priority tagged svlan */
+	v->eg_xlt_rule.c_tagged = 0x7;		/* Accept tagged/untagged/priority tagged cvlan */
+
+	/*
+	 * Fields for action
+	 */
+	v->eg_xlt_action.cvid_xlt_cmd = (v->ppe_cvid == FAL_VLAN_INVALID) ? 0 : FAL_VID_XLT_CMD_ADDORREPLACE;
+	v->eg_xlt_action.cvid_xlt = (v->ppe_cvid == FAL_VLAN_INVALID) ? 0 : v->ppe_cvid;
+	v->eg_xlt_action.svid_xlt_cmd = (v->ppe_svid == FAL_VLAN_INVALID) ? 0 : FAL_VID_XLT_CMD_ADDORREPLACE;
+	v->eg_xlt_action.svid_xlt = (v->ppe_svid == FAL_VLAN_INVALID) ? 0 : v->ppe_svid;
+
+	rcu_read_lock();
+	for_each_netdev_in_bond_rcu(bond_dev, slave) {
+		port = nss_cmn_get_interface_number_by_dev(slave);
+		v->eg_xlt_rule.port_bitmap |= (1 << v->port[port - 1]);
+		ret = fal_port_vlan_trans_adv_add(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1],
+				FAL_PORT_VLAN_EGRESS, &v->eg_xlt_rule, &v->eg_xlt_action);
+		if (ret != SW_OK) {
+			rcu_read_unlock();
+			nss_vlan_mgr_warn("bond:%s -> slave:%s: failed to set egress vlan translation. error:%d\n", bond_dev->name, slave->name, ret);
+			goto delete_ingress_rule;
+		}
+	}
+	rcu_read_unlock();
+
+	/*
+	 * Update vlan port role
+	 */
+	if ((v->ppe_svid != FAL_VLAN_INVALID) && (vlan_mgr_bond_port_role != FAL_QINQ_CORE_PORT)) {
+		rcu_read_lock();
+		for_each_netdev_in_bond_rcu(bond_dev, slave) {
+			fal_port_qinq_role_t mode;
+			port = nss_cmn_get_interface_number_by_dev(slave);
+
+			/*
+			 * If double tag, we should set physical port as core port
+			 */
+			vlan_mgr_ctx.port_role[port] = FAL_QINQ_CORE_PORT;
+
+			/*
+			 * Update port role in PPE
+			 */
+			mode.mask = FAL_PORT_QINQ_ROLE_INGRESS_EN | FAL_PORT_QINQ_ROLE_EGRESS_EN;
+			mode.ingress_port_role = FAL_QINQ_CORE_PORT;
+			mode.egress_port_role = FAL_QINQ_CORE_PORT;
+
+			if (fal_port_qinq_mode_set(NSS_VLAN_MGR_SWITCH_ID, port, &mode)) {
+				rcu_read_unlock();
+				nss_vlan_mgr_warn("bond:%s -> slave:%s: failed to set %d as core port\n", bond_dev->name, slave->name, port);
+				goto delete_egress_rule;
+			}
+		}
+		rcu_read_unlock();
+		ret = NSS_VLAN_PORT_ROLE_CHANGED;
+	}
+
+	v->ppe_vsi = vsi;
+	return ret;
+
+delete_egress_rule:
+	rcu_read_lock();
+	for_each_netdev_in_bond_rcu(bond_dev, slave) {
+		port = nss_cmn_get_interface_number_by_dev(slave);
+		ret = fal_port_vlan_trans_adv_del(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1],
+				FAL_PORT_VLAN_EGRESS,
+				&v->eg_xlt_rule, &v->eg_xlt_action);
+		if (ret != SW_OK) {
+			nss_vlan_mgr_warn("%px: Failed to delete egress translation rule for port:%d, error: %d\n", v, v->port[port - 1], ret);
+		}
+	}
+	rcu_read_unlock();
+
+delete_ingress_rule:
+	rcu_read_lock();
+	for_each_netdev_in_bond_rcu(bond_dev, slave) {
+		port = nss_cmn_get_interface_number_by_dev(slave);
+		ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1], v->ppe_svid, v->ppe_cvid, PPE_VSI_INVALID);
+		if (ret != SW_OK) {
+			nss_vlan_mgr_warn("%px: Failed to delete ingress translation rule for port:%d, error: %d\n", v, v->port[port - 1], ret);
+		}
+	}
+	rcu_read_unlock();
+
+detach_vsi:
+	if (nss_vlan_tx_vsi_detach_msg(v->nss_if, vsi)) {
+		nss_vlan_mgr_warn("%px: Failed to detach vsi %d\n", v, vsi);
+	}
+
+free_vsi:
+	if (ppe_vsi_free(NSS_VLAN_MGR_SWITCH_ID, vsi)) {
+		nss_vlan_mgr_warn("%px: Failed to free VLAN VSI\n", v);
+	}
+
+	return -1;
+}
+/*
+ * nss_vlan_mgr_configure_ppe()
+ *	Configure PPE for physical devices
+ */
+static int nss_vlan_mgr_configure_ppe(struct nss_vlan_pvt *v, struct net_device *dev)
+{
+	uint32_t vsi;
+	int ret = 0;
+
+	if (ppe_vsi_alloc(NSS_VLAN_MGR_SWITCH_ID, &vsi)) {
+		nss_vlan_mgr_warn("%s: failed to allocate VSI for vlan device", dev->name);
+		return -1;
+	}
+
+	if (nss_vlan_tx_vsi_attach_msg(v->nss_if, vsi) != NSS_TX_SUCCESS) {
+		nss_vlan_mgr_warn("%s: failed to attach VSI to vlan interface\n", dev->name);
+		goto free_vsi;
+	}
+
+	/*
+	 * Calculate ppe cvid and svid
+	 */
+	if (NSS_VLAN_MGR_TAG_CNT(v) == NSS_VLAN_TYPE_DOUBLE) {
+		v->ppe_cvid = v->vid;
+		v->ppe_svid = v->parent->vid;
+	} else {
+		if (((vlan_mgr_ctx.ctpid != vlan_mgr_ctx.stpid) && (v->tpid == vlan_mgr_ctx.ctpid)) ||
+		    ((vlan_mgr_ctx.ctpid == vlan_mgr_ctx.stpid) &&
+		     (vlan_mgr_ctx.port_role[v->port[0]] == FAL_QINQ_EDGE_PORT))) {
+			v->ppe_cvid = v->vid;
+			v->ppe_svid = FAL_VLAN_INVALID;
+		} else {
+			v->ppe_cvid = FAL_VLAN_INVALID;
+			v->ppe_svid = v->vid;
+		}
+	}
+
+	/*
+	 * Add ingress vlan translation rule
+	 */
+	ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[0], v->ppe_svid, v->ppe_cvid, vsi);
+	if (ret != SW_OK) {
+		nss_vlan_mgr_warn("%s: failed to set ingress vlan translation, error: %d\n", dev->name, ret);
+		goto detach_vsi;
+	}
+
+	/*
+	 * Add egress vlan translation rule
+	 */
+	memset(&v->eg_xlt_rule, 0, sizeof(v->eg_xlt_rule));
+	memset(&v->eg_xlt_action, 0, sizeof(v->eg_xlt_action));
+
+	/*
+	 * Fields for match
+	 */
+	v->eg_xlt_rule.vsi_valid = true;	/* Use vsi as search key*/
+	v->eg_xlt_rule.vsi_enable = true;	/* Use vsi as search key*/
+	v->eg_xlt_rule.vsi = vsi;		/* Use vsi as search key*/
+	v->eg_xlt_rule.s_tagged = 0x7;		/* Accept tagged/untagged/priority tagged svlan */
+	v->eg_xlt_rule.c_tagged = 0x7;		/* Accept tagged/untagged/priority tagged cvlan */
+	v->eg_xlt_rule.port_bitmap = (1 << v->port[0]); /* Use port as search key*/
+
+	/*
+	 * Fields for action
+	 */
+	v->eg_xlt_action.cvid_xlt_cmd = (v->ppe_cvid == FAL_VLAN_INVALID) ? 0 : FAL_VID_XLT_CMD_ADDORREPLACE;
+	v->eg_xlt_action.cvid_xlt = (v->ppe_cvid == FAL_VLAN_INVALID) ? 0 : v->ppe_cvid;
+	v->eg_xlt_action.svid_xlt_cmd = (v->ppe_svid == FAL_VLAN_INVALID) ? 0 : FAL_VID_XLT_CMD_ADDORREPLACE;
+	v->eg_xlt_action.svid_xlt = (v->ppe_svid == FAL_VLAN_INVALID) ? 0 : v->ppe_svid;
+
+	ret = fal_port_vlan_trans_adv_add(NSS_VLAN_MGR_SWITCH_ID, v->port[0],
+				FAL_PORT_VLAN_EGRESS, &v->eg_xlt_rule,
+				&v->eg_xlt_action);
+	if (ret != SW_OK) {
+		nss_vlan_mgr_warn("%s: failed to set egress vlan translation\n", dev->name);
+		goto delete_ingress_rule;
+	}
+
+	if ((v->ppe_svid != FAL_VLAN_INVALID) && (vlan_mgr_ctx.port_role[v->port[0]] != FAL_QINQ_CORE_PORT)) {
+		fal_port_qinq_role_t mode;
+
+		/*
+		 * If double tag, we should set physical port as core port
+		 */
+		vlan_mgr_ctx.port_role[v->port[0]] = FAL_QINQ_CORE_PORT;
+
+		/*
+		 * Update port role in PPE
+		 */
+		mode.mask = FAL_PORT_QINQ_ROLE_INGRESS_EN | FAL_PORT_QINQ_ROLE_EGRESS_EN;
+		mode.ingress_port_role = FAL_QINQ_CORE_PORT;
+		mode.egress_port_role = FAL_QINQ_CORE_PORT;
+
+		if (fal_port_qinq_mode_set(NSS_VLAN_MGR_SWITCH_ID, v->port[0], &mode)) {
+			nss_vlan_mgr_warn("%s: failed to set %d as core port\n", dev->name, v->port[0]);
+			goto delete_egress_rule;
+		}
+		ret = NSS_VLAN_PORT_ROLE_CHANGED;
+	}
+
+	v->ppe_vsi = vsi;
+	return ret;
+
+delete_egress_rule:
+	ret = fal_port_vlan_trans_adv_del(NSS_VLAN_MGR_SWITCH_ID, v->port[0],
+				FAL_PORT_VLAN_EGRESS,
+				&v->eg_xlt_rule, &v->eg_xlt_action);
+	if (ret != SW_OK) {
+		nss_vlan_mgr_warn("%px: Failed to delete egress translation rule, error: %d\n", v, ret);
+	}
+
+delete_ingress_rule:
+	ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[0], v->ppe_svid, v->ppe_cvid, PPE_VSI_INVALID);
+	if (ret != SW_OK) {
+		nss_vlan_mgr_warn("%px: Failed to delete ingress translation rule, error: %d\n", v, ret);
+	}
+
+detach_vsi:
+	if (nss_vlan_tx_vsi_detach_msg(v->nss_if, vsi)) {
+		nss_vlan_mgr_warn("%px: Failed to detach vsi %d\n", v, vsi);
+	}
+
+free_vsi:
+	if (ppe_vsi_free(NSS_VLAN_MGR_SWITCH_ID, vsi)) {
+		nss_vlan_mgr_warn("%px: Failed to free VLAN VSI\n", v);
+	}
+
+	return -1;
+}
+#endif
+
+/*
+ * nss_vlan_mgr_create_instance()
+ *	Create vlan instance
+ */
+static struct nss_vlan_pvt *nss_vlan_mgr_create_instance(
+						struct net_device *dev)
+{
+	struct nss_vlan_pvt *v;
+	struct vlan_dev_priv *vlan;
+	struct net_device *real_dev;
+	struct net_device *slave;
+	int32_t port, bondid = -1;
+
+	if (!is_vlan_dev(dev)) {
+		return NULL;
+	}
+
+	v = kzalloc(sizeof(*v), GFP_KERNEL);
+	if (!v) {
+		return NULL;
+	}
+
+	INIT_LIST_HEAD(&v->list);
+
+	vlan = vlan_dev_priv(dev);
+	real_dev = vlan->real_dev;
+	v->vid = vlan->vlan_id;
+	v->tpid = ntohs(vlan->vlan_proto);
+
+	/*
+	 * Check if the vlan has any parent.
+	 *
+	 * 1. While adding eth0.10/bond0.10, the real_dev will become
+	 * eth0/bond0. In this case, v->parent should be NULL and respective
+	 * port numbers will be assigned to v->port.
+	 *
+	 * 2. While adding eth0.10.20/bond0.10.20, the real_dev will
+	 * become eth0.10/bond0.10, so v->parent should be valid. But v->parent->parent
+	 * should be NULL, as explained above. In this case, we need to copy the
+	 * v->parent->port numbers to v->ports as the double vlan is created
+	 * on the same physical port(s).
+	 *
+	 * 3. We ignore the remaining case as we support only 2 valn tags.
+	 */
+	v->parent = nss_vlan_mgr_instance_find_and_ref(real_dev);
+	if (!v->parent) {
+		if (!netif_is_bond_master(real_dev)) {
+			v->port[0] = nss_cmn_get_interface_number_by_dev(real_dev);
+			if (!NSS_VLAN_PHY_PORT_CHK(v->port[0])) {
+				nss_vlan_mgr_warn("%s: %d is not valid physical port\n", real_dev->name, v->port[0]);
+				kfree(v);
+				return NULL;
+			}
+		} else {
+#if defined(BONDING_SUPPORT)
+			bondid = bond_get_id(real_dev);
+#endif
+			if (bondid < 0) {
+				nss_vlan_mgr_warn("%px: Invalid LAG group id 0x%x\n", v, bondid);
+				kfree(v);
+				return NULL;
+			}
+			rcu_read_lock();
+			for_each_netdev_in_bond_rcu(real_dev, slave) {
+				port = nss_cmn_get_interface_number_by_dev(slave);
+				if (!NSS_VLAN_PHY_PORT_CHK(port)) {
+					rcu_read_unlock();
+					nss_vlan_mgr_warn("%s: %d is not valid physical port\n", slave->name, port);
+					kfree(v);
+					return NULL;
+				}
+				v->port[port - 1] = port;
+			}
+			rcu_read_unlock();
+			v->bond_ifnum = bondid + NSS_LAG0_INTERFACE_NUM;
+		}
+	} else if (!v->parent->parent) {
+		if (is_vlan_dev(real_dev)) {
+			vlan = vlan_dev_priv(real_dev);
+			real_dev = vlan->real_dev;
+		}
+		if (!netif_is_bond_master(real_dev)) {
+			v->port[0] = v->parent->port[0];
+		} else {
+			rcu_read_lock();
+			for_each_netdev_in_bond_rcu(real_dev, slave) {
+				port = nss_cmn_get_interface_number_by_dev(slave);
+				if (!NSS_VLAN_PHY_PORT_CHK(port)) {
+					rcu_read_unlock();
+					nss_vlan_mgr_warn("%s: %d is not valid physical port\n", slave->name, port);
+					kfree(v);
+					return NULL;
+				}
+				v->port[port - 1] = v->parent->port[port - 1];
+			}
+			rcu_read_unlock();
+			v->bond_ifnum = v->parent->bond_ifnum;
+		}
+	} else {
+		nss_vlan_mgr_warn("%s: don't support more than 2 vlans\n", dev->name);
+		nss_vlan_mgr_instance_deref(v->parent);
+		kfree(v);
+		return NULL;
+	}
+
+	/*
+	 * Check if TPID is permited
+	 */
+	if ((NSS_VLAN_MGR_TAG_CNT(v) == NSS_VLAN_TYPE_DOUBLE) &&
+	    ((v->tpid != vlan_mgr_ctx.ctpid) || (v->parent->tpid != vlan_mgr_ctx.stpid))) {
+		nss_vlan_mgr_warn("%s: double tag: tpid %04x not match global tpid(%04x, %04x)\n", dev->name, v->tpid, vlan_mgr_ctx.ctpid,
+				vlan_mgr_ctx.stpid);
+		nss_vlan_mgr_instance_deref(v->parent);
+		kfree(v);
+		return NULL;
+	}
+
+	if ((NSS_VLAN_MGR_TAG_CNT(v) == NSS_VLAN_TYPE_SINGLE) &&
+	    ((v->tpid != vlan_mgr_ctx.ctpid) && (v->tpid != vlan_mgr_ctx.stpid))) {
+		nss_vlan_mgr_warn("%s: single tag: tpid %04x not match global tpid(%04x, %04x)\n", dev->name, v->tpid, vlan_mgr_ctx.ctpid, vlan_mgr_ctx.stpid);
+		kfree(v);
+		return NULL;
+	}
+
+	v->mtu = dev->mtu;
+	ether_addr_copy(v->dev_addr, dev->dev_addr);
+	v->ifindex = dev->ifindex;
+	v->refs = 1;
+
+	return v;
+}
+
+/*
+ * nss_vlan_mgr_instance_free()
+ *	Destroy vlan instance
+ */
+static void nss_vlan_mgr_instance_free(struct nss_vlan_pvt *v)
+{
+	int32_t i;
+	int ret = 0;
+
+	spin_lock(&vlan_mgr_ctx.lock);
+	BUG_ON(--v->refs);
+	if (!list_empty(&v->list)) {
+		list_del(&v->list);
+	}
+	spin_unlock(&vlan_mgr_ctx.lock);
+
+#ifdef NSS_VLAN_MGR_PPE_SUPPORT
+	if (v->ppe_vsi) {
+		/*
+		 * Detach VSI
+		 */
+		if (nss_vlan_tx_vsi_detach_msg(v->nss_if, v->ppe_vsi)) {
+			nss_vlan_mgr_warn("%px: Failed to detach vsi %d\n", v, v->ppe_vsi);
+		}
+
+		/*
+		 * Delete ingress vlan translation rule
+		 */
+		for (i = 0; i < NSS_VLAN_PHY_PORT_MAX; i++) {
+			if (!v->port[i])
+				continue;
+			ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[i], v->ppe_svid, v->ppe_cvid, PPE_VSI_INVALID);
+			if (ret != SW_OK)
+				nss_vlan_mgr_warn("%px: Failed to delete old ingress translation rule, error: %d\n", v, ret);
+		}
+
+		/*
+		 * Delete egress vlan translation rule
+		 */
+		v->eg_xlt_rule.port_bitmap = 0;
+		for (i = 0; i < NSS_VLAN_PHY_PORT_MAX; i++) {
+			if (!v->port[i])
+				continue;
+			v->eg_xlt_rule.port_bitmap |= (1 << v->port[i]);
+			ret = fal_port_vlan_trans_adv_del(NSS_VLAN_MGR_SWITCH_ID, v->port[i],
+						FAL_PORT_VLAN_EGRESS,
+						&v->eg_xlt_rule, &v->eg_xlt_action);
+			if (ret != SW_OK) {
+				nss_vlan_mgr_warn("%px: Failed to delete vlan translation rule, error:%d\n", v, ret);
+			}
+		}
+
+		/*
+		 * Free PPE VSI
+		 */
+		if (ppe_vsi_free(NSS_VLAN_MGR_SWITCH_ID, v->ppe_vsi)) {
+			nss_vlan_mgr_warn("%px: Failed to free VLAN VSI\n", v);
+		}
+	}
+
+	/*
+	 * Need to change the physical port role. While adding
+	 * eth0.10.20/bond0.10.20, the role of the physical port(s) changed
+	 * from EDGE to CORE. So, while removing eth0.10.20/bond0.10.20, the
+	 * role of the physical port(s) should be changed from CORE to EDGE.
+	 */
+	for (i = 0; i < NSS_VLAN_PHY_PORT_MAX; i++) {
+		if (v->port[i]) {
+			if (nss_vlan_mgr_calculate_new_port_role(v->port[i], i)) {
+				nss_vlan_mgr_port_role_event(v->port[i], i);
+			}
+		}
+	}
+#endif
+
+	if (v->nss_if) {
+		nss_unregister_vlan_if(v->nss_if);
+		if (nss_dynamic_interface_dealloc_node(v->nss_if, NSS_DYNAMIC_INTERFACE_TYPE_VLAN) != NSS_TX_SUCCESS)
+			nss_vlan_mgr_warn("%px: Failed to dealloc vlan dynamic interface\n", v);
+	}
+
+	if (v->parent)
+		nss_vlan_mgr_instance_deref(v->parent);
+
+	kfree(v);
+}
+
+/*
+ * nss_vlan_mgr_changemtu_event()
+ */
+static int nss_vlan_mgr_changemtu_event(struct netdev_notifier_info *info)
+{
+	struct net_device *dev = netdev_notifier_info_to_dev(info);
+	struct nss_vlan_pvt *v_pvt = nss_vlan_mgr_instance_find_and_ref(dev);
+
+	if (!v_pvt)
+		return NOTIFY_DONE;
+
+	spin_lock(&vlan_mgr_ctx.lock);
+	if (v_pvt->mtu == dev->mtu) {
+		spin_unlock(&vlan_mgr_ctx.lock);
+		nss_vlan_mgr_instance_deref(v_pvt);
+		return NOTIFY_DONE;
+	}
+	spin_unlock(&vlan_mgr_ctx.lock);
+
+	if (nss_vlan_tx_set_mtu_msg(v_pvt->nss_if, dev->mtu) != NSS_TX_SUCCESS) {
+		nss_vlan_mgr_warn("%s: Failed to send change MTU(%d) message to NSS\n", dev->name, dev->mtu);
+		nss_vlan_mgr_instance_deref(v_pvt);
+		return NOTIFY_BAD;
+	}
+
+	spin_lock(&vlan_mgr_ctx.lock);
+	v_pvt->mtu = dev->mtu;
+	spin_unlock(&vlan_mgr_ctx.lock);
+	nss_vlan_mgr_trace("%s: MTU changed to %d, NSS updated\n", dev->name, dev->mtu);
+	nss_vlan_mgr_instance_deref(v_pvt);
+	return NOTIFY_DONE;
+}
+
+/*
+ * int nss_vlan_mgr_changeaddr_event()
+ */
+static int nss_vlan_mgr_changeaddr_event(struct netdev_notifier_info *info)
+{
+	struct net_device *dev = netdev_notifier_info_to_dev(info);
+	struct nss_vlan_pvt *v_pvt = nss_vlan_mgr_instance_find_and_ref(dev);
+
+	if (!v_pvt)
+		return NOTIFY_DONE;
+
+	spin_lock(&vlan_mgr_ctx.lock);
+	if (!memcmp(v_pvt->dev_addr, dev->dev_addr, ETH_ALEN)) {
+		spin_unlock(&vlan_mgr_ctx.lock);
+		nss_vlan_mgr_instance_deref(v_pvt);
+		return NOTIFY_DONE;
+	}
+	spin_unlock(&vlan_mgr_ctx.lock);
+
+	if (nss_vlan_tx_set_mac_addr_msg(v_pvt->nss_if, dev->dev_addr) != NSS_TX_SUCCESS) {
+		nss_vlan_mgr_warn("%s: Failed to send change MAC address message to NSS\n", dev->name);
+		nss_vlan_mgr_instance_deref(v_pvt);
+		return NOTIFY_BAD;
+	}
+
+	spin_lock(&vlan_mgr_ctx.lock);
+	ether_addr_copy(v_pvt->dev_addr, dev->dev_addr);
+	spin_unlock(&vlan_mgr_ctx.lock);
+	nss_vlan_mgr_trace("%s: MAC changed to %pM, updated NSS\n", dev->name, dev->dev_addr);
+	nss_vlan_mgr_instance_deref(v_pvt);
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_vlan_mgr_register_event()
+ */
+static int nss_vlan_mgr_register_event(struct netdev_notifier_info *info)
+{
+	struct net_device *dev = netdev_notifier_info_to_dev(info);
+	struct nss_vlan_pvt *v;
+	int if_num;
+#ifdef NSS_VLAN_MGR_PPE_SUPPORT
+	int ret;
+#endif
+	uint32_t vlan_tag;
+	struct net_device *slave;
+	int32_t port, port_if;
+	struct vlan_dev_priv *vlan;
+	struct net_device *real_dev;
+	bool is_bond_master = false;
+
+	v = nss_vlan_mgr_create_instance(dev);
+	if (!v)
+		return NOTIFY_DONE;
+
+	if_num = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_VLAN);
+	if (if_num < 0) {
+		nss_vlan_mgr_warn("%s: failed to alloc NSS dynamic interface\n", dev->name);
+		nss_vlan_mgr_instance_free(v);
+		return NOTIFY_DONE;
+	}
+
+	if (!nss_register_vlan_if(if_num, NULL, dev, 0, v)) {
+		nss_vlan_mgr_warn("%s: failed to register NSS dynamic interface", dev->name);
+		if (nss_dynamic_interface_dealloc_node(if_num, NSS_DYNAMIC_INTERFACE_TYPE_VLAN) != NSS_TX_SUCCESS)
+			nss_vlan_mgr_warn("%px: Failed to dealloc vlan dynamic interface\n", v);
+		nss_vlan_mgr_instance_free(v);
+		return NOTIFY_DONE;
+	}
+	v->nss_if = if_num;
+
+	vlan = vlan_dev_priv(dev);
+	real_dev = vlan->real_dev;
+	if (is_vlan_dev(real_dev)) {
+		vlan = vlan_dev_priv(real_dev);
+		real_dev = vlan->real_dev;
+	}
+	is_bond_master = netif_is_bond_master(real_dev);
+
+#ifdef NSS_VLAN_MGR_PPE_SUPPORT
+	if (!is_bond_master)
+		ret = nss_vlan_mgr_configure_ppe(v, dev);
+	else
+		ret = nss_vlan_mgr_bond_configure_ppe(v, real_dev);
+
+	if (ret < 0) {
+		nss_vlan_mgr_instance_free(v);
+		return NOTIFY_DONE;
+	}
+#endif
+
+	if (nss_vlan_tx_set_mac_addr_msg(v->nss_if, v->dev_addr) != NSS_TX_SUCCESS) {
+		nss_vlan_mgr_warn("%s: failed to set mac_addr msg\n", dev->name);
+		nss_vlan_mgr_instance_free(v);
+		return NOTIFY_DONE;
+	}
+
+	if (nss_vlan_tx_set_mtu_msg(v->nss_if, v->mtu) != NSS_TX_SUCCESS) {
+		nss_vlan_mgr_warn("%s: failed to set mtu msg\n", dev->name);
+		nss_vlan_mgr_instance_free(v);
+		return NOTIFY_DONE;
+	}
+
+	vlan_tag = (v->tpid << NSS_VLAN_TPID_SHIFT | v->vid);
+	port_if = is_bond_master ? v->bond_ifnum : v->port[0];
+	if (nss_vlan_tx_add_tag_msg(v->nss_if, vlan_tag,
+				(v->parent ? v->parent->nss_if : port_if),
+				port_if) != NSS_TX_SUCCESS) {
+		nss_vlan_mgr_warn("%s: failed to add vlan in nss\n", dev->name);
+		nss_vlan_mgr_instance_free(v);
+		return NOTIFY_DONE;
+	}
+
+	spin_lock(&vlan_mgr_ctx.lock);
+	list_add(&v->list, &vlan_mgr_ctx.list);
+	spin_unlock(&vlan_mgr_ctx.lock);
+
+#ifdef NSS_VLAN_MGR_PPE_SUPPORT
+	if (ret == NSS_VLAN_PORT_ROLE_CHANGED) {
+		if (!is_bond_master) {
+			nss_vlan_mgr_port_role_event(v->port[0], 0);
+		} else {
+			rcu_read_lock();
+			for_each_netdev_in_bond_rcu(real_dev, slave) {
+				port = nss_cmn_get_interface_number_by_dev(slave);
+				if (!NSS_VLAN_PHY_PORT_CHK(port)) {
+					rcu_read_unlock();
+					nss_vlan_mgr_warn("%s: %d is not valid physical port\n", slave->name, port);
+					return NOTIFY_DONE;
+				}
+				nss_vlan_mgr_port_role_event(v->port[port - 1], port-1);
+				break;
+			}
+			rcu_read_unlock();
+		}
+	}
+#endif
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_vlan_mgr_unregister_event()
+ */
+static int nss_vlan_mgr_unregister_event(struct netdev_notifier_info *info)
+{
+	struct net_device *dev = netdev_notifier_info_to_dev(info);
+	struct nss_vlan_pvt *v = nss_vlan_mgr_instance_find_and_ref(dev);
+
+	/*
+	 * Do we have it on record?
+	 */
+	if (!v)
+		return NOTIFY_DONE;
+
+	nss_vlan_mgr_trace("Vlan %s unregsitered. Freeing NSS dynamic interface %d\n", dev->name, v->nss_if);
+
+	/*
+	 * Release reference got by "nss_vlan_mgr_instance_find_and_ref"
+	 */
+	nss_vlan_mgr_instance_deref(v);
+
+	/*
+	 * Free instance
+	 */
+	nss_vlan_mgr_instance_free(v);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_vlan_mgr_netdevice_event()
+ */
+static int nss_vlan_mgr_netdevice_event(struct notifier_block *unused,
+				unsigned long event, void *ptr)
+{
+	struct netdev_notifier_info *info = (struct netdev_notifier_info *)ptr;
+
+	switch (event) {
+	case NETDEV_CHANGEADDR:
+		return nss_vlan_mgr_changeaddr_event(info);
+	case NETDEV_CHANGEMTU:
+		return nss_vlan_mgr_changemtu_event(info);
+	case NETDEV_REGISTER:
+		return nss_vlan_mgr_register_event(info);
+	case NETDEV_UNREGISTER:
+		return nss_vlan_mgr_unregister_event(info);
+	}
+
+	/*
+	 * Notify done for all the events we don't care
+	 */
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block nss_vlan_mgr_netdevice_nb __read_mostly = {
+	.notifier_call = nss_vlan_mgr_netdevice_event,
+};
+
+/*
+ * nss_vlan_mgr_get_real_dev()
+ *	Get real dev for vlan interface
+ */
+struct net_device *nss_vlan_mgr_get_real_dev(struct net_device *dev)
+{
+	struct vlan_dev_priv *vlan;
+
+	if (!dev)
+		return NULL;
+
+	vlan = vlan_dev_priv(dev);
+	return vlan->real_dev;
+}
+EXPORT_SYMBOL(nss_vlan_mgr_get_real_dev);
+
+#ifdef NSS_VLAN_MGR_PPE_SUPPORT
+/*
+ * nss_vlan_mgr_port_vsi_update()
+ * 	Update vlan port with the new vsi value
+ */
+static int nss_vlan_mgr_port_vsi_update(struct nss_vlan_pvt *v, uint32_t new_vsi)
+{
+	int ret;
+	uint32_t old_vsi;
+
+	/*
+	 * Delete old ingress vlan translation rule
+	 */
+	ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[0], v->ppe_svid, v->ppe_cvid, PPE_VSI_INVALID);
+	if (ret != SW_OK) {
+		nss_vlan_mgr_warn("%px: Failed to delete old ingress translation rule for port: %d, error: %d\n", v, v->port[0], ret);
+		return -1;
+	}
+
+	/*
+	 * Delete old egress vlan translation rule
+	 */
+	ret = fal_port_vlan_trans_adv_del(NSS_VLAN_MGR_SWITCH_ID, v->port[0],
+			FAL_PORT_VLAN_EGRESS, &v->eg_xlt_rule, &v->eg_xlt_action);
+	if (ret != SW_OK) {
+		nss_vlan_mgr_warn("%px: failed to delete egress vlan translation while joining bridge for port: %d, error: %d\n", v, v->port[0], ret);
+		return -1;
+	}
+
+	/*
+	 * Add new ingress vlan translation rule to use new VSI
+	 */
+	ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[0], v->ppe_svid, v->ppe_cvid, new_vsi);
+	if (ret != SW_OK) {
+		nss_vlan_mgr_warn("%px: failed to change ingress vlan translation while joining bridge for port: %d, error: %d\n", v, v->port[0], ret);
+		return -1;
+	}
+
+	/*
+	 * Add new egress vlan translation rule to use new VSI
+	 */
+	old_vsi = v->eg_xlt_rule.vsi;
+	v->eg_xlt_rule.vsi = new_vsi;
+	ret = fal_port_vlan_trans_adv_add(NSS_VLAN_MGR_SWITCH_ID, v->port[0],
+			FAL_PORT_VLAN_EGRESS, &v->eg_xlt_rule, &v->eg_xlt_action);
+	if (ret != SW_OK) {
+		nss_vlan_mgr_warn("%px: failed to change egress vlan translation while joining bridge for port: %d. error:%d\n", v, v->port[0], ret);
+		v->eg_xlt_rule.vsi = old_vsi;
+		return -1;
+	}
+	return 0;
+}
+
+/*
+ * nss_vlan_mgr_over_bond_port_vsi_update()
+ * 	Update bond slaves with the new vsi value
+ */
+static int nss_vlan_mgr_over_bond_port_vsi_update(struct net_device *real_dev, struct nss_vlan_pvt *v, uint32_t new_vsi)
+{
+	int port, ret;
+	uint32_t old_vsi;
+	struct net_device *slave;
+
+	v->eg_xlt_rule.port_bitmap = 0;
+	old_vsi = v->eg_xlt_rule.vsi;
+
+	rcu_read_lock();
+	for_each_netdev_in_bond_rcu(real_dev, slave) {
+		port = nss_cmn_get_interface_number_by_dev(slave);
+		if (!NSS_VLAN_PHY_PORT_CHK(port)) {
+			rcu_read_unlock();
+			nss_vlan_mgr_warn("%px: bond: %s, slave is not a physical interface\n", v, real_dev->name);
+			return -1;
+		}
+		v->eg_xlt_rule.port_bitmap |= (1 << v->port[port - 1]);
+
+		/*
+		 * Delete old ingress vlan translation rule
+		 */
+		ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1], v->ppe_svid, v->ppe_cvid, PPE_VSI_INVALID);
+		if (ret != SW_OK) {
+			rcu_read_unlock();
+			nss_vlan_mgr_warn("%px: Failed to delete old ingress translation rule for port: %d\n, error: %d", v, v->port[port - 1], ret);
+			return -1;
+		}
+
+		/*
+		 * Delete old egress vlan translation rule
+		 */
+		ret = fal_port_vlan_trans_adv_del(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1],
+				FAL_PORT_VLAN_EGRESS, &v->eg_xlt_rule, &v->eg_xlt_action);
+		if (ret != SW_OK) {
+			rcu_read_unlock();
+			nss_vlan_mgr_warn("%px: failed to delete egress vlan translation while joining bridge for port: %d, error:%d\n", v, v->port[port - 1], ret);
+			return -1;
+		}
+
+		/*
+		 * Add new ingress vlan translation rule to use bridge VSI
+		 */
+		ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1], v->ppe_svid, v->ppe_cvid, new_vsi);
+		if (ret != SW_OK) {
+			rcu_read_unlock();
+			nss_vlan_mgr_warn("%px: failed to change ingress vlan translation while joining bridge for port: %d, error: %d\n", v, v->port[port - 1], ret);
+			return -1;
+		}
+
+		/*
+		 * Add new egress vlan translation rule to use bridge VSI
+		 */
+		v->eg_xlt_rule.vsi = new_vsi;
+		ret = fal_port_vlan_trans_adv_add(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1],
+				FAL_PORT_VLAN_EGRESS, &v->eg_xlt_rule, &v->eg_xlt_action);
+		if (ret != SW_OK) {
+			rcu_read_unlock();
+			nss_vlan_mgr_warn("%px: failed to change egress vlan translation while joining bridge for port: %d. error:%d\n", v, v->port[port - 1], ret);
+			return -1;
+		}
+		v->eg_xlt_rule.vsi = old_vsi;
+	}
+	rcu_read_unlock();
+
+	v->eg_xlt_rule.vsi = new_vsi;
+	return 0;
+}
+
+/*
+ * nss_vlan_mgr_over_bond_join_bridge()
+ *	Join bond interface to bridge
+ */
+static int nss_vlan_mgr_over_bond_join_bridge(struct net_device *real_dev, struct nss_vlan_pvt *v, uint32_t bridge_vsi)
+{
+	int ret;
+	uint32_t vlan_vsi;
+
+	vlan_vsi = v->eg_xlt_rule.vsi;
+	ret = nss_vlan_mgr_over_bond_port_vsi_update(real_dev, v, bridge_vsi);
+	if (ret) {
+		nss_vlan_mgr_warn("%px: failed to update bond slaves with the bridge vsi: %d\n", v, bridge_vsi);
+		goto return_with_error;
+	}
+
+	v->bridge_vsi = bridge_vsi;
+	return 0;
+
+return_with_error:
+	ret = nss_vlan_mgr_over_bond_port_vsi_update(real_dev, v, vlan_vsi);
+	if (ret) {
+		nss_vlan_mgr_warn("%px: failed to update bond slaves with the vlan vsi: %d\n", v, vlan_vsi);
+	}
+	return -1;
+}
+
+/*
+ * nss_vlan_mgr_over_bond_leave_bridge()
+ *	Leave bond interface from bridge
+ */
+static int nss_vlan_mgr_over_bond_leave_bridge(struct net_device *real_dev, struct nss_vlan_pvt *v)
+{
+	int port, ret;
+	struct net_device *slave;
+	uint32_t bridge_vsi;
+
+	bridge_vsi = v->eg_xlt_rule.vsi;
+	ret = nss_vlan_mgr_over_bond_port_vsi_update(real_dev, v, v->ppe_vsi);
+	if (ret) {
+		nss_vlan_mgr_warn("%px: failed to update bond slaves with the vlan vsi: %d\n", v, v->ppe_vsi);
+		goto return_with_error;
+	}
+	v->bridge_vsi = 0;
+
+	rcu_read_lock();
+	for_each_netdev_in_bond_rcu(real_dev, slave) {
+		port = nss_cmn_get_interface_number_by_dev(slave);
+		if (!NSS_VLAN_PHY_PORT_CHK(port)) {
+			rcu_read_unlock();
+			nss_vlan_mgr_warn("%s: %d is not valid physical port\n", slave->name, port);
+			goto return_with_error;
+		}
+
+		/*
+		 * Set port STP state to forwarding after bond interfaces leave bridge
+		 */
+		fal_stp_port_state_set(NSS_VLAN_MGR_SWITCH_ID, NSS_VLAN_MGR_STP_ID,
+				v->port[port - 1], FAL_STP_FORWARDING);
+	}
+	rcu_read_unlock();
+	return 0;
+
+return_with_error:
+	ret = nss_vlan_mgr_over_bond_port_vsi_update(real_dev, v, bridge_vsi);
+	if (ret) {
+		nss_vlan_mgr_warn("%px: failed to update bond slaves with the bridge vsi: %d\n", v, bridge_vsi);
+	}
+	return -1;
+
+}
+#endif
+
+/*
+ * nss_vlan_mgr_join_bridge()
+ *	update ingress and egress vlan translation rule to use bridge VSI
+ */
+int nss_vlan_mgr_join_bridge(struct net_device *dev, uint32_t bridge_vsi)
+{
+	struct nss_vlan_pvt *v = nss_vlan_mgr_instance_find_and_ref(dev);
+	struct net_device *real_dev;
+	int ret;
+
+	if (!v)
+		return 0;
+
+#ifdef NSS_VLAN_MGR_PPE_SUPPORT
+	if ((v->bridge_vsi == bridge_vsi) || v->bridge_vsi) {
+		nss_vlan_mgr_warn("%s is already in bridge VSI %d, can't change to %d\n", dev->name, v->bridge_vsi, bridge_vsi);
+		nss_vlan_mgr_instance_deref(v);
+		return 0;
+	}
+
+	/*
+	 * If real_dev is bond_master, update for all slaves
+	 */
+	real_dev = nss_vlan_mgr_get_real_dev(dev);
+	if (real_dev && is_vlan_dev(real_dev)) {
+		real_dev = nss_vlan_mgr_get_real_dev(real_dev);
+	}
+	if (real_dev == NULL) {
+		nss_vlan_mgr_warn("%px: real dev for the vlan: %s is NULL\n", v, dev->name);
+		nss_vlan_mgr_instance_deref(v);
+		return -1;
+	}
+
+	/*
+	 * Check if real_dev is bond master
+	 */
+	if (netif_is_bond_master(real_dev)) {
+		ret = nss_vlan_mgr_over_bond_join_bridge(real_dev, v, bridge_vsi);
+		nss_vlan_mgr_instance_deref(v);
+		if (ret) {
+			nss_vlan_mgr_warn("%px: Bond master: %s failed to join bridge\n", v, real_dev->name);
+			return -1;
+		}
+		return 0;
+	}
+
+	/*
+	 * real_dev is not bond but a physical device
+	 */
+	ret = nss_vlan_mgr_port_vsi_update(v, bridge_vsi);
+	if (ret) {
+		nss_vlan_mgr_warn("%px: failed to join bridge %s\n", v, real_dev->name);
+	} else {
+		v->bridge_vsi = bridge_vsi;
+	}
+#endif
+	nss_vlan_mgr_instance_deref(v);
+	return 0;
+}
+EXPORT_SYMBOL(nss_vlan_mgr_join_bridge);
+
+/*
+ * nss_vlan_mgr_leave_bridge()
+ *	update ingress and egress vlan translation rule to restore vlan VSI
+ */
+int nss_vlan_mgr_leave_bridge(struct net_device *dev, uint32_t bridge_vsi)
+{
+	struct nss_vlan_pvt *v = nss_vlan_mgr_instance_find_and_ref(dev);
+	struct net_device *real_dev;
+	int ret;
+
+	if (!v)
+		return 0;
+
+#ifdef NSS_VLAN_MGR_PPE_SUPPORT
+	if (v->bridge_vsi != bridge_vsi) {
+		nss_vlan_mgr_warn("%s is not in bridge VSI %d, ignore\n", dev->name, bridge_vsi);
+		nss_vlan_mgr_instance_deref(v);
+		return 0;
+	}
+
+	/*
+	 * If real_dev is bond_master, update for all slaves
+	 */
+	real_dev = nss_vlan_mgr_get_real_dev(dev);
+	if (real_dev && is_vlan_dev(real_dev)) {
+		real_dev = nss_vlan_mgr_get_real_dev(real_dev);
+	}
+
+	if (!real_dev) {
+		nss_vlan_mgr_warn("%px: real dev for the vlan: %s is NULL\n", v, dev->name);
+		nss_vlan_mgr_instance_deref(v);
+		return -1;
+	}
+
+	/*
+	 * Check if real_dev is bond master
+	 */
+	if (netif_is_bond_master(real_dev)) {
+		ret = nss_vlan_mgr_over_bond_leave_bridge(real_dev, v);
+		nss_vlan_mgr_instance_deref(v);
+		if (ret) {
+			nss_vlan_mgr_warn("%px: Bond master: %s failed to leave bridge\n", v, real_dev->name);
+			return -1;
+		}
+		return 0;
+	}
+
+	/*
+	 * real_dev is not bond but a physical device
+	 */
+	ret = nss_vlan_mgr_port_vsi_update(v, v->ppe_vsi);
+	if (ret) {
+		nss_vlan_mgr_warn("%px: failed to leave bridge %s\n", v, real_dev->name);
+		nss_vlan_mgr_instance_deref(v);
+		return -1;
+	}
+	v->bridge_vsi = 0;
+
+	/*
+	 * Set port STP state to forwarding after vlan interface leaves bridge
+	 */
+	fal_stp_port_state_set(NSS_VLAN_MGR_SWITCH_ID, NSS_VLAN_MGR_STP_ID,
+					v->port[0], FAL_STP_FORWARDING);
+#endif
+	nss_vlan_mgr_instance_deref(v);
+	return 0;
+}
+EXPORT_SYMBOL(nss_vlan_mgr_leave_bridge);
+
+#ifdef NSS_VLAN_MGR_PPE_SUPPORT
+/*
+ * int nss_vlan_mgr_update_ppe_tpid()
+ */
+static int nss_vlan_mgr_update_ppe_tpid(void)
+{
+	fal_tpid_t tpid;
+
+	tpid.mask = FAL_TPID_CTAG_EN | FAL_TPID_STAG_EN;
+	tpid.ctpid = vlan_mgr_ctx.ctpid;
+	tpid.stpid = vlan_mgr_ctx.stpid;
+
+	if (fal_ingress_tpid_set(NSS_VLAN_MGR_SWITCH_ID, &tpid) || fal_egress_tpid_set(NSS_VLAN_MGR_SWITCH_ID, &tpid)) {
+		nss_vlan_mgr_warn("failed to set ctpid %d stpid %d\n", tpid.ctpid, tpid.stpid);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_vlan_mgr_tpid_proc_handler()
+ *	Sets customer TPID and service TPID
+ */
+static int nss_vlan_mgr_tpid_proc_handler(struct ctl_table *ctl,
+					  int write, void __user *buffer,
+					  size_t *lenp, loff_t *ppos)
+{
+	int ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (write)
+		nss_vlan_mgr_update_ppe_tpid();
+
+	return ret;
+}
+
+/*
+ * nss_vlan sysctl table
+ */
+static struct ctl_table nss_vlan_table[] = {
+	{
+		.procname	= "ctpid",
+		.data		= &vlan_mgr_ctx.ctpid,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_vlan_mgr_tpid_proc_handler,
+	},
+	{
+		.procname	= "stpid",
+		.data		= &vlan_mgr_ctx.stpid,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_vlan_mgr_tpid_proc_handler,
+	},
+	{ }
+};
+
+/*
+ * nss_vlan sysctl dir
+ */
+static struct ctl_table nss_vlan_dir[] = {
+	{
+		.procname		= "vlan_client",
+		.mode			= 0555,
+		.child			= nss_vlan_table,
+	},
+	{ }
+};
+
+/*
+ * nss_vlan systel root dir
+ */
+static struct ctl_table nss_vlan_root_dir[] = {
+	{
+		.procname		= "nss",
+		.mode			= 0555,
+		.child			= nss_vlan_dir,
+	},
+	{ }
+};
+
+/*
+ * nss_vlan_mgr_add_bond_slave()
+ *	Add new slave port to bond_vlan
+ */
+int nss_vlan_mgr_add_bond_slave(struct net_device *bond_dev,
+			struct net_device *slave_dev)
+{
+	struct nss_vlan_pvt *v;
+	int32_t bond_ifnum, vsi = 0, port, bondid = -1;
+	int ret;
+
+#if defined(BONDING_SUPPORT)
+	bondid = bond_get_id(bond_dev);
+#endif
+	if (bondid < 0) {
+		nss_vlan_mgr_warn("%s: Invalid LAG group id 0x%x\n", bond_dev->name, bondid);
+		return -1;
+	}
+	bond_ifnum = bondid + NSS_LAG0_INTERFACE_NUM;
+
+	/*
+	 * find all the vlan_pvt structure which has parent bond_dev
+	 */
+	spin_lock(&vlan_mgr_ctx.lock);
+	list_for_each_entry(v, &vlan_mgr_ctx.list, list) {
+		if (v->bond_ifnum != bond_ifnum)
+			continue;
+
+		/*
+		 * Add Ingress and Egress vlan_vsi
+		 */
+		port = nss_cmn_get_interface_number_by_dev(slave_dev);
+		if (!NSS_VLAN_PHY_PORT_CHK(port)) {
+			spin_unlock(&vlan_mgr_ctx.lock);
+			nss_vlan_mgr_warn("%s: %d is not valid physical port\n", slave_dev->name, port);
+			return -1;
+		}
+		v->port[port - 1] = port;
+
+		/*
+		 * Set correct vsi for the bond slave
+		 */
+		vsi = v->bridge_vsi ? v->bridge_vsi : v->ppe_vsi;
+
+		/*
+		 * Add ingress vlan tranlation table
+		 */
+		ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1], v->ppe_svid, v->ppe_cvid, vsi);
+		if (ret != SW_OK) {
+			spin_unlock(&vlan_mgr_ctx.lock);
+			nss_vlan_mgr_warn("bond: %s -> slave: %s: failed to set ingress vlan translation, error: %d\n", bond_dev->name, slave_dev->name, ret);
+			return -1;
+		}
+
+		/*
+		 * Add egress vlan tranlation table
+		 */
+		v->eg_xlt_rule.port_bitmap |= (1 << v->port[port - 1]);
+		ret = fal_port_vlan_trans_adv_add(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1],
+					FAL_PORT_VLAN_EGRESS,
+					&v->eg_xlt_rule,
+					&v->eg_xlt_action);
+		if (ret != SW_OK) {
+			spin_unlock(&vlan_mgr_ctx.lock);
+			nss_vlan_mgr_warn("bond:%s -> slave:%s failed to set egress vlan translation. error: %d\n", bond_dev->name, slave_dev->name, ret);
+			goto delete_ingress_rule;
+		}
+
+		/*
+		 * Update port role
+		 */
+		if ((v->ppe_svid != FAL_VLAN_INVALID) &&
+				(vlan_mgr_ctx.port_role[v->port[port - 1]] != FAL_QINQ_CORE_PORT)) {
+			fal_port_qinq_role_t mode;
+
+			/*
+			 * If double tag, we should set physical port as core port
+			 */
+			vlan_mgr_ctx.port_role[v->port[port - 1]] = FAL_QINQ_CORE_PORT;
+
+			/*
+			 * Update port role in PPE
+			 */
+			mode.mask = FAL_PORT_QINQ_ROLE_INGRESS_EN | FAL_PORT_QINQ_ROLE_EGRESS_EN;
+			mode.ingress_port_role = FAL_QINQ_CORE_PORT;
+			mode.egress_port_role = FAL_QINQ_CORE_PORT;
+			if (fal_port_qinq_mode_set(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1], &mode)) {
+				spin_unlock(&vlan_mgr_ctx.lock);
+				nss_vlan_mgr_warn("bond:%s -> slave:%s failed to set %d as core port\n",
+						bond_dev->name, slave_dev->name,
+						v->port[port - 1]);
+				goto delete_egress_rule;
+			}
+		}
+	}
+	spin_unlock(&vlan_mgr_ctx.lock);
+	return 0;
+
+delete_egress_rule:
+	ret = fal_port_vlan_trans_adv_del(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1],
+				FAL_PORT_VLAN_EGRESS,
+				&v->eg_xlt_rule, &v->eg_xlt_action);
+	if (ret != SW_OK) {
+		nss_vlan_mgr_warn("%px: Failed to delete egress translation rule, error: %d\n", v, ret);
+	}
+delete_ingress_rule:
+	ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1], v->ppe_svid, v->ppe_cvid, PPE_VSI_INVALID);
+	if (ret != SW_OK) {
+		nss_vlan_mgr_warn("%px: Failed to delete ingress translation rule, error: %d\n", v, ret);
+	}
+
+	return -1;
+}
+EXPORT_SYMBOL(nss_vlan_mgr_add_bond_slave);
+
+/*
+ * nss_vlan_mgr_delete_bond_slave()
+ *	Delete new slave port from bond_vlan
+ */
+int nss_vlan_mgr_delete_bond_slave(struct net_device *slave_dev)
+{
+	struct nss_vlan_pvt *v;
+	uint32_t port;
+	fal_port_qinq_role_t mode;
+	int ret;
+
+	/*
+	 * Find port id for the slave
+	 */
+	port = nss_cmn_get_interface_number_by_dev(slave_dev);
+	if (!NSS_VLAN_PHY_PORT_CHK(port)) {
+		spin_unlock(&vlan_mgr_ctx.lock);
+		nss_vlan_mgr_warn("%s: %d is not valid physical port\n", slave_dev->name, port);
+		return -1;
+	}
+
+	spin_lock(&vlan_mgr_ctx.lock);
+	list_for_each_entry(v, &vlan_mgr_ctx.list, list) {
+		if (v->port[port - 1] != port)
+			continue;
+
+		/*
+		 * Delete ingress vlan tranlation table
+		 */
+		ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1], v->ppe_svid, v->ppe_cvid, PPE_VSI_INVALID);
+		if (ret != SW_OK) {
+			spin_unlock(&vlan_mgr_ctx.lock);
+			nss_vlan_mgr_warn("%px: Failed to delete old ingress translation rule, error: %d\n", v, ret);
+			return -1;
+		}
+
+		/*
+		 * Delete egress vlan tranlation table
+		 */
+		ret = fal_port_vlan_trans_adv_del(NSS_VLAN_MGR_SWITCH_ID, v->port[port - 1],
+				FAL_PORT_VLAN_EGRESS,
+				&v->eg_xlt_rule, &v->eg_xlt_action);
+		if (ret != SW_OK) {
+			spin_unlock(&vlan_mgr_ctx.lock);
+			nss_vlan_mgr_warn("%px: Failed to delete vlan translation rule, error: %d\n", v, ret);
+			return -1;
+		}
+		v->eg_xlt_rule.port_bitmap = v->eg_xlt_rule.port_bitmap ^ (1 << port);
+
+		/*
+		 * Change port role to edge
+		 */
+		mode.mask = FAL_PORT_QINQ_ROLE_INGRESS_EN | FAL_PORT_QINQ_ROLE_EGRESS_EN;
+		mode.ingress_port_role = FAL_QINQ_EDGE_PORT;
+		mode.egress_port_role = FAL_QINQ_EDGE_PORT;
+		if (fal_port_qinq_mode_set(NSS_VLAN_MGR_SWITCH_ID, port, &mode)) {
+			spin_unlock(&vlan_mgr_ctx.lock);
+			nss_vlan_mgr_warn("failed to set %d as edge port\n", port);
+			return -1;
+		}
+		vlan_mgr_ctx.port_role[port] = FAL_QINQ_EDGE_PORT;
+
+		/*
+		 * Set vlan port
+		 */
+		v->port[port - 1] = 0;
+	}
+	spin_unlock(&vlan_mgr_ctx.lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(nss_vlan_mgr_delete_bond_slave);
+
+/*
+ * nss_vlan_mgr_add_vlan_rule()
+ *	Add VLAN translation rule in PPE
+ */
+void nss_vlan_mgr_add_vlan_rule(struct net_device *dev, int bridge_vsi, int vid)
+{
+	fal_vlan_trans_adv_rule_t eg_xlt_rule;
+	fal_vlan_trans_adv_action_t eg_xlt_action;
+	int port_id;
+	int ret;
+
+	port_id = nss_cmn_get_interface_number_by_dev(dev);
+	if (!NSS_VLAN_PHY_PORT_CHK(port_id)) {
+		nss_vlan_mgr_warn("%px: %s:%d is not valid physical port\n", dev, dev->name, port_id);
+		return;
+	}
+
+	/*
+	 * Add new ingress vlan translation rule to use bridge VSI
+	 */
+	ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, port_id, FAL_VLAN_INVALID, vid, bridge_vsi);
+	if (ret != SW_OK) {
+		nss_vlan_mgr_warn("%px: failed to change ingress vlan translation for port: %d, error: %d\n",
+				dev, port_id, ret);
+		return;
+	}
+
+	/*
+	 * Add egress vlan translation rule
+	 */
+	memset(&eg_xlt_rule, 0, sizeof(eg_xlt_rule));
+	memset(&eg_xlt_action, 0, sizeof(eg_xlt_action));
+
+	/*
+	 * Fields for match
+	 */
+	eg_xlt_rule.vsi_valid = true;	/* Use vsi as search key */
+	eg_xlt_rule.vsi_enable = true;	/* Use vsi as search key */
+	eg_xlt_rule.vsi = bridge_vsi;	/* Use vsi as search key */
+	eg_xlt_rule.s_tagged = 0x7;	/* Accept tagged/untagged/priority tagged svlan */
+	eg_xlt_rule.c_tagged = 0x7;	/* Accept tagged/untagged/priority tagged cvlan */
+	eg_xlt_rule.port_bitmap = (1 << port_id); /* Use port as search key */
+
+	/*
+	 * Fields for action
+	 */
+	eg_xlt_action.cvid_xlt_cmd = FAL_VID_XLT_CMD_ADDORREPLACE;
+	eg_xlt_action.cvid_xlt = vid;
+
+	ret = fal_port_vlan_trans_adv_add(NSS_VLAN_MGR_SWITCH_ID, port_id,
+				FAL_PORT_VLAN_EGRESS, &eg_xlt_rule,
+				&eg_xlt_action);
+	if (ret != SW_OK) {
+		nss_vlan_mgr_warn("%px: Failed to update egress vlan(%x) translation rule for port: %d, error: %d\n",
+				dev, vid, port_id, ret);
+		/*
+		 * Delete ingress vlan translation rule
+		 */
+		if (ret != SW_ALREADY_EXIST) {
+			ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, port_id, FAL_VLAN_INVALID, vid, PPE_VSI_INVALID);
+		}
+
+		return;
+	}
+
+	nss_vlan_mgr_info("%px: Added egress vlan(%x) translation rule for port: %d\n", dev, vid, port_id);
+}
+EXPORT_SYMBOL(nss_vlan_mgr_add_vlan_rule);
+
+/*
+ * nss_vlan_mgr_del_vlan_rule()
+ *	Delete VLAN translation rule in PPE
+ */
+void nss_vlan_mgr_del_vlan_rule(struct net_device *dev, int bridge_vsi, int vid)
+{
+	fal_vlan_trans_adv_rule_t eg_xlt_rule;	/* VLAN Translation Rule */
+	fal_vlan_trans_adv_action_t eg_xlt_action;	/* VLAN Translation Action */
+	int port_id;
+	int ret;
+
+	port_id = nss_cmn_get_interface_number_by_dev(dev);
+	if (!NSS_VLAN_PHY_PORT_CHK(port_id)) {
+		nss_vlan_mgr_warn("%px: %s:%d is not valid physical port\n", dev, dev->name, port_id);
+		return;
+	}
+
+	/*
+	 * Delete ingress vlan translation rule
+	 */
+	ret = ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, port_id, FAL_VLAN_INVALID, vid, PPE_VSI_INVALID);
+	if (ret != SW_OK) {
+		nss_vlan_mgr_warn("%px: failed to delete ingress vlan translation for port: %d, error: %d\n", dev, port_id, ret);
+		return;
+	}
+
+	/*
+	 * Delete egress vlan translation rule
+	 */
+	memset(&eg_xlt_rule, 0, sizeof(eg_xlt_rule));
+	memset(&eg_xlt_action, 0, sizeof(eg_xlt_action));
+
+	/*
+	 * Fields for match
+	 */
+	eg_xlt_rule.vsi_valid = true;	/* Use vsi as search key */
+	eg_xlt_rule.vsi_enable = true;	/* Use vsi as search key */
+	eg_xlt_rule.vsi = bridge_vsi;	/* Use vsi as search key */
+	eg_xlt_rule.s_tagged = 0x7;	/* Accept tagged/untagged/priority tagged svlan */
+	eg_xlt_rule.c_tagged = 0x7;	/* Accept tagged/untagged/priority tagged cvlan */
+	eg_xlt_rule.port_bitmap = (1 << port_id); /* Use port as search key */
+
+	/*
+	 * Fields for action
+	 */
+	eg_xlt_action.cvid_xlt_cmd = FAL_VID_XLT_CMD_ADDORREPLACE;
+	eg_xlt_action.cvid_xlt = vid;
+
+	/*
+	 * Delete old egress vlan translation rule
+	 */
+	ret = fal_port_vlan_trans_adv_del(NSS_VLAN_MGR_SWITCH_ID, port_id,
+				FAL_PORT_VLAN_EGRESS, &eg_xlt_rule,
+				&eg_xlt_action);
+	if (ret != SW_OK) {
+		nss_vlan_mgr_warn("%px: Failed to update egress vlan translation of port: %d. error: %d\n", dev, port_id, ret);
+		ppe_port_vlan_vsi_set(NSS_VLAN_MGR_SWITCH_ID, port_id, FAL_VLAN_INVALID, vid, bridge_vsi);
+		return;
+	}
+
+	nss_vlan_mgr_info("%px: deleted egress vlan(%x) translation rule for port: %d\n", dev, vid, port_id);
+}
+EXPORT_SYMBOL(nss_vlan_mgr_del_vlan_rule);
+#endif
+
+/*
+ * nss_vlan_mgr_init_module()
+ *	vlan_mgr module init function
+ */
+int __init nss_vlan_mgr_init_module(void)
+{
+#ifdef NSS_VLAN_MGR_PPE_SUPPORT
+	int idx;
+#endif
+
+	INIT_LIST_HEAD(&vlan_mgr_ctx.list);
+	spin_lock_init(&vlan_mgr_ctx.lock);
+
+	vlan_mgr_ctx.ctpid = ETH_P_8021Q;
+	vlan_mgr_ctx.stpid = ETH_P_8021Q;
+
+#ifdef NSS_VLAN_MGR_PPE_SUPPORT
+	vlan_mgr_ctx.sys_hdr = register_sysctl_table(nss_vlan_root_dir);
+	if (!vlan_mgr_ctx.sys_hdr) {
+		nss_vlan_mgr_warn("Unabled to register sysctl table for vlan manager\n");
+		return -EFAULT;
+	}
+
+	if (nss_vlan_mgr_update_ppe_tpid()) {
+		unregister_sysctl_table(vlan_mgr_ctx.sys_hdr);
+		return -EFAULT;
+	}
+
+	for (idx = 0; idx < NSS_VLAN_PHY_PORT_NUM; idx++) {
+		vlan_mgr_ctx.port_role[idx] = FAL_QINQ_EDGE_PORT;
+	}
+#endif
+	register_netdevice_notifier(&nss_vlan_mgr_netdevice_nb);
+
+	nss_vlan_mgr_info("Module (Build %s) loaded\n", NSS_CLIENT_BUILD_ID);
+	return 0;
+}
+
+/*
+ * nss_vlan_mgr_exit_module()
+ *	vlan_mgr module exit function
+ */
+void __exit nss_vlan_mgr_exit_module(void)
+{
+	unregister_netdevice_notifier(&nss_vlan_mgr_netdevice_nb);
+
+#ifdef NSS_VLAN_MGR_PPE_SUPPORT
+	if (vlan_mgr_ctx.sys_hdr)
+		unregister_sysctl_table(vlan_mgr_ctx.sys_hdr);
+#endif
+	nss_vlan_mgr_info("Module unloaded\n");
+}
+
+module_init(nss_vlan_mgr_init_module);
+module_exit(nss_vlan_mgr_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS vlan manager");
diff --git a/qca-nss-clients/vxlanmgr/Makefile b/qca-nss-clients/vxlanmgr/Makefile
new file mode 100644
index 0000000..7410642
--- /dev/null
+++ b/qca-nss-clients/vxlanmgr/Makefile
@@ -0,0 +1,9 @@
+ccflags-y += -I$(obj)/../exports -I$(obj)/.. -I$(obj)/nss_hal/include
+ccflags-y += -DNSS_CLIENT_BUILD_ID="$(BUILD_ID)"
+ccflags-y += -DNSS_VXLANMGR_DEBUG_LEVEL=2
+ccflags-y += -Wall -Werror
+
+obj-m += qca-nss-vxlanmgr.o
+qca-nss-vxlanmgr-objs := nss_vxlanmgr.o
+qca-nss-vxlanmgr-objs += nss_vxlanmgr_tunnel.o
+qca-nss-vxlanmgr-objs += nss_vxlanmgr_tun_stats.o
diff --git a/qca-nss-clients/vxlanmgr/nss_vxlanmgr.c b/qca-nss-clients/vxlanmgr/nss_vxlanmgr.c
new file mode 100644
index 0000000..df8261c
--- /dev/null
+++ b/qca-nss-clients/vxlanmgr/nss_vxlanmgr.c
@@ -0,0 +1,147 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_vxlanmgr.c
+ *	NSS to HLOS VxLAN manager
+ */
+
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/of.h>
+#include <net/vxlan.h>
+#include <nss_api_if.h>
+#include "nss_vxlanmgr.h"
+#include "nss_vxlanmgr_tun_stats.h"
+
+/*
+ * VxLAN context
+ */
+struct nss_vxlanmgr_ctx vxlan_ctx;
+
+/*
+ * nss_vxlanmgr_netdev_event()
+ *	Netdevice notifier for NSS VxLAN manager module
+ */
+static int nss_vxlanmgr_netdev_event(struct notifier_block *nb, unsigned long event, void *dev)
+{
+	struct net_device *netdev = netdev_notifier_info_to_dev(dev);
+
+	if (!netif_is_vxlan(netdev)) {
+		/*
+		 * Return if it's not a vxlan netdev
+		 */
+		return NOTIFY_DONE;
+	}
+
+	switch (event) {
+	case NETDEV_DOWN:
+		nss_vxlanmgr_trace("%px: NETDEV_DOWN: event %lu name %s\n", netdev, event, netdev->name);
+		return nss_vxlanmgr_tunnel_deconfig(netdev);
+	case NETDEV_UP:
+		nss_vxlanmgr_trace("%px: NETDEV_UP: event %lu name %s\n", netdev, event, netdev->name);
+		return nss_vxlanmgr_tunnel_config(netdev);
+	case NETDEV_UNREGISTER:
+		nss_vxlanmgr_trace("%px: NETDEV_UNREGISTER: event %lu name %s\n", netdev, event, netdev->name);
+		return nss_vxlanmgr_tunnel_destroy(netdev);
+	case NETDEV_REGISTER:
+		nss_vxlanmgr_trace("%px: NETDEV_REGISTER: event %lu name %s\n", netdev, event, netdev->name);
+		return nss_vxlanmgr_tunnel_create(netdev);
+	default:
+		nss_vxlanmgr_trace("%px: Unhandled notifier event %lu name %s\n", netdev, event, netdev->name);
+	}
+	return NOTIFY_DONE;
+}
+
+/*
+ * Linux Net device Notifier
+ */
+static struct notifier_block nss_vxlanmgr_netdev_notifier = {
+	.notifier_call = nss_vxlanmgr_netdev_event,
+};
+
+/*
+ * nss_vxlanmgr_exit_module()
+ *	Tunnel vxlan module exit function
+ */
+void __exit nss_vxlanmgr_exit_module(void)
+{
+	int ret;
+	struct nss_vxlanmgr_tun_ctx *tun_ctx, *temp;
+
+	/*
+	 * Check if there are any tunnels.
+	 * Delete all the tunnels from NSS FW and free.
+	 */
+	list_for_each_entry_safe(tun_ctx, temp, &vxlan_ctx.list, head) {
+		/*
+		 * Send deconfigure and destroy message to FW.
+		 */
+		nss_vxlanmgr_trace("Removing tunnel %s\n", tun_ctx->dev->name);
+		nss_vxlanmgr_tunnel_deconfig(tun_ctx->dev);
+		nss_vxlanmgr_tunnel_destroy(tun_ctx->dev);
+	}
+
+	nss_vxlanmgr_tun_stats_dentry_deinit();
+	ret = unregister_netdevice_notifier(&nss_vxlanmgr_netdev_notifier);
+	if (ret) {
+		nss_vxlanmgr_warn("failed to unregister netdevice notifier: error %d\n", ret);
+		return;
+	}
+
+	nss_vxlanmgr_info("module unloaded\n");
+}
+
+/*
+ * nss_vxlanmgr_init_module()
+ *	Tunnel vxlan module init function
+ */
+int __init nss_vxlanmgr_init_module(void)
+{
+	int ret;
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		nss_vxlanmgr_warn("nss-common not found.\n");
+		return -1;
+	}
+
+	INIT_LIST_HEAD(&vxlan_ctx.list);
+	vxlan_ctx.nss_ctx = nss_vxlan_get_ctx();
+	spin_lock_init(&vxlan_ctx.tun_lock);
+
+	if (!nss_vxlanmgr_tun_stats_dentry_init()) {
+		nss_vxlanmgr_warn("Failed to create debugfs entry\n");
+		return -1;
+	}
+
+	ret = register_netdevice_notifier(&nss_vxlanmgr_netdev_notifier);
+	if (ret) {
+		nss_vxlanmgr_tun_stats_dentry_deinit();
+		nss_vxlanmgr_warn("Failed to register netdevice notifier: error %d\n", ret);
+		return -1;
+	}
+
+	nss_vxlanmgr_info("Module %s loaded\n", NSS_CLIENT_BUILD_ID);
+	return 0;
+}
+
+module_init(nss_vxlanmgr_init_module);
+module_exit(nss_vxlanmgr_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS VxLAN manager");
diff --git a/qca-nss-clients/vxlanmgr/nss_vxlanmgr.h b/qca-nss-clients/vxlanmgr/nss_vxlanmgr.h
new file mode 100644
index 0000000..bb39119
--- /dev/null
+++ b/qca-nss-clients/vxlanmgr/nss_vxlanmgr.h
@@ -0,0 +1,85 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_vxlanmgr.h
+ *	VxLAN manager header
+ */
+#ifndef __NSS_VXLANMGR_H
+#define __NSS_VXLANMGR_H
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_vxlanmgr_warn(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_vxlanmgr_info(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_vxlanmgr_trace(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#else /* CONFIG_DYNAMIC_DEBUG */
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_VXLANMGR_DEBUG_LEVEL < 2)
+#define nss_vxlanmgr_warn(s, ...)
+#else
+#define nss_vxlanmgr_warn(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_VXLANMGR_DEBUG_LEVEL < 3)
+#define nss_vxlanmgr_info(s, ...)
+#else
+#define nss_vxlanmgr_info(s, ...)   pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_VXLANMGR_DEBUG_LEVEL < 4)
+#define nss_vxlanmgr_trace(s, ...)
+#else
+#define nss_vxlanmgr_trace(s, ...)  pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+struct nss_vxlanmgr_ctx {
+	struct list_head list;			/* vxlanmgr context list head */
+	struct dentry *dentry;			/* debugfs entry for qca-nss-vxlanmgr */
+	struct nss_ctx_instance *nss_ctx;	/* nss context for vxlan tunnel */
+	uint32_t tun_count;			/* active vxlan tunnel count */
+	spinlock_t tun_lock;			/* spinlock */
+};
+
+struct nss_vxlanmgr_tun_ctx {
+	struct list_head head;			/* tunnel context list entry */
+	struct net_device *dev;			/* tunnel netdevice pointer */
+	struct dentry *dentry;			/* per tunnel debugfs entry */
+	struct nss_vxlanmgr_ctx *vxlan_ctx;	/* pointer to vxlanmgr context */
+	struct nss_vxlanmgr_tun_stats *stats;	/* tunnel statistics structure */
+	uint32_t inner_ifnum;			/* inner node interface number */
+	uint32_t outer_ifnum;			/* outer node interface number */
+	uint32_t vni;				/* vnet identifier */
+	uint16_t tunnel_flags;			/* vxlan tunnel flags */
+	uint16_t flow_label;			/* flowlabel */
+	uint16_t src_port_min;			/* minimum source port */
+	uint16_t src_port_max;			/* maximum source port*/
+	uint16_t dest_port;			/* destination port */
+	uint8_t tos;				/* tos value */
+	uint8_t ttl;				/* time to live */
+};
+
+extern int nss_vxlanmgr_tunnel_create(struct net_device *dev);
+extern int nss_vxlanmgr_tunnel_destroy(struct net_device *dev);
+extern int nss_vxlanmgr_tunnel_config(struct net_device *dev);
+extern int nss_vxlanmgr_tunnel_deconfig(struct net_device *dev);
+
+#endif /* __NSS_VXLANMGR_H */
diff --git a/qca-nss-clients/vxlanmgr/nss_vxlanmgr_tun_stats.c b/qca-nss-clients/vxlanmgr/nss_vxlanmgr_tun_stats.c
new file mode 100644
index 0000000..38847b0
--- /dev/null
+++ b/qca-nss-clients/vxlanmgr/nss_vxlanmgr_tun_stats.c
@@ -0,0 +1,322 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/debugfs.h>
+#include <linux/etherdevice.h>
+#include <linux/netdevice.h>
+#include <nss_api_if.h>
+#include "nss_vxlanmgr.h"
+#include "nss_vxlanmgr_tun_stats.h"
+
+/*
+ * VxLAN context
+ */
+extern struct nss_vxlanmgr_ctx vxlan_ctx;
+
+/*
+ * nss_vxlanmgr_tun_stats_str
+ *	Vxlan statistics strings for nss tunnel stats
+ */
+static int8_t *nss_vxlanmgr_tun_stats_str[NSS_VXLANMGR_TUN_STATS_TYPE_MAX] = {
+	"rx_pkts",
+	"rx_bytes",
+	"tx_pkts",
+	"tx_bytes",
+	"rx_queue_0_dropped",
+	"rx_queue_1_dropped",
+	"rx_queue_2_dropped",
+	"rx_queue_3_dropped",
+	"Except MAC DB look up failed",
+	"Except Insufficient Headroom",
+	"Except MAC moved",
+	"Except No Policy ID",
+	"Except Extra flags",
+	"Except VNI Look-up failed",
+	"Dropped packet malformed",
+	"Dropped next node queue is full",
+	"Except Inner hash calculation failed",
+};
+
+/*
+ * nss_vxlanmgr_tun_stats_show()
+ *	Read Vxlan Tunnel statistics
+ */
+static int nss_vxlanmgr_tun_stats_show(struct seq_file *m, void __attribute__((unused))*p)
+{
+	int i;
+	struct nss_vxlanmgr_tun_ctx *tun_ctx;
+	struct nss_vxlanmgr_tun_stats *vxlan_tunnel_stats;
+
+	tun_ctx = kzalloc(sizeof(struct nss_vxlanmgr_tun_ctx), GFP_KERNEL);
+	if (!tun_ctx) {
+		nss_vxlanmgr_warn("Failed to allocate memory for tun_ctx\n");
+		return -ENOMEM;
+	}
+
+	vxlan_tunnel_stats = kzalloc(sizeof(struct nss_vxlanmgr_tun_stats), GFP_KERNEL);
+	if (!vxlan_tunnel_stats) {
+		nss_vxlanmgr_warn("Failed to allocate memory for vxlan_tunnel_stats\n");
+		kfree(tun_ctx);
+		return -ENOMEM;
+	}
+
+	spin_lock_bh(&vxlan_ctx.tun_lock);
+	memcpy(tun_ctx, m->private, sizeof(struct nss_vxlanmgr_tun_ctx));
+	memcpy(vxlan_tunnel_stats, tun_ctx->stats, sizeof(struct nss_vxlanmgr_tun_stats));
+	spin_unlock_bh(&vxlan_ctx.tun_lock);
+
+	/*
+	 * Tunnel stats
+	 */
+	seq_printf(m, "\n%s tunnel stats start:\n", tun_ctx->dev->name);
+
+	seq_printf(m, "\t%s configuration:\n", tun_ctx->dev->name);
+	seq_printf(m, "\t\tvni = %u\n", tun_ctx->vni);
+	seq_printf(m, "\t\ttunnel_flags = %x\n", tun_ctx->tunnel_flags);
+	seq_printf(m, "\t\tflow_label = %u\n", tun_ctx->flow_label);
+	seq_printf(m, "\t\tsrc_port_min = %u\n", tun_ctx->src_port_min);
+	seq_printf(m, "\t\tsrc_port_max = %u\n", tun_ctx->src_port_max);
+	seq_printf(m, "\t\tdest_port = %u\n", ntohs(tun_ctx->dest_port));
+	seq_printf(m, "\t\ttos = %u\n", tun_ctx->tos);
+	seq_printf(m, "\t\tttl = %u\n", tun_ctx->ttl);
+
+	seq_printf(m, "\n\tInner ifnum %u stats:\n", tun_ctx->inner_ifnum);
+	for (i = 0; i < NSS_VXLANMGR_TUN_STATS_TYPE_MAX; i++) {
+		seq_printf(m, "\t\t%s = %llu\n",
+				nss_vxlanmgr_tun_stats_str[i],
+				vxlan_tunnel_stats->inner_stats[i]);
+	}
+
+	seq_printf(m, "\n\tOuter ifnum %u stats:\n", tun_ctx->outer_ifnum);
+	for (i = 0; i < NSS_VXLANMGR_TUN_STATS_TYPE_MAX; i++) {
+		seq_printf(m, "\t\t%s = %llu\n",
+				nss_vxlanmgr_tun_stats_str[i],
+				vxlan_tunnel_stats->outer_stats[i]);
+	}
+
+	seq_printf(m, "\n\tMAC DB stats:\n");
+	for (i = 0; i < NSS_VXLAN_MACDB_ENTRIES_MAX; i++) {
+		if (!vxlan_tunnel_stats->mac_stats[i][0]) {
+			continue;
+		}
+		seq_printf(m, "\t\t%pM = %llu\n",
+				&vxlan_tunnel_stats->mac_stats[i][0],
+				vxlan_tunnel_stats->mac_stats[i][1]);
+	}
+	seq_printf(m, "\n\tPackets dropped at host: %llu\n",
+				vxlan_tunnel_stats->host_packet_drop);
+
+	seq_printf(m, "\n%s tunnel stats end\n\n", tun_ctx->dev->name);
+	kfree(tun_ctx);
+	kfree(vxlan_tunnel_stats);
+	return 0;
+}
+
+/*
+ * nss_vxlanmgr_tun_stats_open()
+ */
+static int nss_vxlanmgr_tun_stats_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, nss_vxlanmgr_tun_stats_show, inode->i_private);
+}
+
+/*
+ * nss_vxlanmgr_tun_stats_update()
+ *	Update inner and outer node statistics
+ */
+void nss_vxlanmgr_tun_stats_update(uint64_t *stats, struct nss_vxlan_stats_msg *stats_msg)
+{
+	uint32_t i;
+
+	stats[NSS_VXLANMGR_TUN_STATS_TYPE_RX_PKTS] += stats_msg->node_stats.rx_packets;
+	stats[NSS_VXLANMGR_TUN_STATS_TYPE_RX_BYTES] += stats_msg->node_stats.rx_bytes;
+	stats[NSS_VXLANMGR_TUN_STATS_TYPE_TX_PKTS] += stats_msg->node_stats.tx_packets;
+	stats[NSS_VXLANMGR_TUN_STATS_TYPE_TX_BYTES] += stats_msg->node_stats.tx_bytes;
+
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		stats[NSS_VXLANMGR_TUN_STATS_TYPE_RX_QUEUE_0_DROPPED + i] += stats_msg->node_stats.rx_dropped[i];
+	}
+
+	stats[NSS_VXLANMGR_TUN_STATS_TYPE_MAC_DB_LOOKUP_FAILED] +=
+		stats_msg->except_mac_db_lookup_failed;
+	stats[NSS_VXLANMGR_TUN_STATS_TYPE_EXCEPT_HEADROOM_INSUFFICIENT] +=
+		stats_msg->except_low_hroom;
+	stats[NSS_VXLANMGR_TUN_STATS_TYPE_EXCEPT_MAC_MOVE] +=
+		stats_msg->except_mac_move;
+	stats[NSS_VXLANMGR_TUN_STATS_TYPE_EXCEPT_NO_POLICY_ID] +=
+		stats_msg->except_no_policy_id;
+	stats[NSS_VXLANMGR_TUN_STATS_TYPE_EXCEPT_EXTRA_FLAGS] +=
+		stats_msg->except_extra_vxlan_hdr_flags;
+	stats[NSS_VXLANMGR_TUN_STATS_TYPE_EXCEPT_VNI_LOOKUP_FAILED] +=
+		stats_msg->except_vni_lookup_failed;
+	stats[NSS_VXLANMGR_TUN_STATS_TYPE_DROP_MALFORMED] +=
+		stats_msg->dropped_malformed;
+	stats[NSS_VXLANMGR_TUN_STATS_TYPE_DROP_NEXT_NODE_QUEUE_FULL] +=
+		stats_msg->dropped_next_node_queue_full;
+	stats[NSS_VXLANMGR_TUN_STATS_TYPE_EXCEPT_INNER_HASH] +=
+		stats_msg->except_inner_hash;
+}
+
+/*
+ * nss_vxlanmgr_tun_macdb_stats_sync()
+ *	Sync function for vxlan fdb entries
+ */
+void nss_vxlanmgr_tun_macdb_stats_sync(struct nss_vxlanmgr_tun_ctx *tun_ctx, struct nss_vxlan_msg *nvm)
+{
+	struct nss_vxlan_macdb_stats_msg *db_stats;
+	struct nss_vxlanmgr_tun_stats *s = tun_ctx->stats;
+	uint16_t i, j, nentries;
+
+	db_stats = &nvm->msg.db_stats;
+	nentries = db_stats->cnt;
+
+	dev_hold(tun_ctx->dev);
+
+	if (nentries > NSS_VXLAN_MACDB_ENTRIES_PER_MSG) {
+		nss_vxlanmgr_warn("%px: No more than 20 entries allowed per message.\n", tun_ctx->dev);
+		dev_put(tun_ctx->dev);
+		return;
+	}
+
+	for (j = 0; j < nentries; j++) {
+		if (!db_stats->entry[j].hits) {
+			continue;
+		}
+		for (i = 0; i < NSS_VXLAN_MACDB_ENTRIES_MAX; i++) {
+			if (ether_addr_equal((uint8_t *)&s->mac_stats[i][0],
+						(uint8_t *)db_stats->entry[j].mac)) {
+				s->mac_stats[i][1] += db_stats->entry[j].hits;
+				break;
+			}
+		}
+	}
+	dev_put(tun_ctx->dev);
+}
+
+/*
+ * nss_vxlanmgr_tun_stats_sync()
+ *	Sync function for vxlan statistics
+ */
+void nss_vxlanmgr_tun_stats_sync(struct nss_vxlanmgr_tun_ctx *tun_ctx, struct nss_vxlan_msg *nvm)
+{
+	uint32_t ifnum = nvm->cm.interface;
+	struct nss_vxlan_stats_msg *stats = &nvm->msg.stats;
+	struct nss_vxlanmgr_tun_stats *s = tun_ctx->stats;
+
+	if (tun_ctx->inner_ifnum == ifnum) {
+		nss_vxlanmgr_tun_stats_update(s->inner_stats, stats);
+	} else if (tun_ctx->outer_ifnum == ifnum) {
+		nss_vxlanmgr_tun_stats_update(s->outer_stats, stats);
+	} else {
+		nss_vxlanmgr_warn("Invalid interface number\n");
+	}
+}
+
+/*
+ * nss_vxlanmgr_tun_stats_ops
+ *	File operations for VxLAN tunnel stats
+ */
+static const struct file_operations nss_vxlanmgr_tun_stats_ops = { \
+	.open = nss_vxlanmgr_tun_stats_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = seq_release
+};
+
+/*
+ * nss_vxlanmgr_tun_stats_deinit()
+ *	Remove the stats entry for the given interface number.
+ */
+void nss_vxlanmgr_tun_stats_deinit(struct nss_vxlanmgr_tun_ctx *tun_ctx)
+{
+	struct nss_vxlanmgr_tun_stats *stats_stats = tun_ctx->stats;
+
+	spin_lock_bh(&vxlan_ctx.tun_lock);
+	kfree(stats_stats);
+	tun_ctx->stats = NULL;
+	spin_unlock_bh(&vxlan_ctx.tun_lock);
+}
+
+/*
+ * nss_vxlanmgr_tun_stats_init()
+ *	Alloc and initialize tunnel debug stats.
+ */
+bool nss_vxlanmgr_tun_stats_init(struct nss_vxlanmgr_tun_ctx *tun_ctx)
+{
+	struct nss_vxlanmgr_tun_stats *stats_stats;
+
+	stats_stats = kzalloc(sizeof(struct nss_vxlanmgr_tun_stats), GFP_ATOMIC);
+	if (!stats_stats) {
+		nss_vxlanmgr_warn("Failed to allocate memory for stats_stats\n");
+		return false;
+	}
+
+	tun_ctx->stats = stats_stats;
+	return true;
+}
+
+/*
+ * nss_vxlanmgr_tun_stats_dentry_remove()
+ *	Remove debufs file for given tunnel context.
+ */
+void nss_vxlanmgr_tun_stats_dentry_remove(struct nss_vxlanmgr_tun_ctx *tun_ctx)
+{
+	debugfs_remove(tun_ctx->dentry);
+}
+
+/*
+ * nss_vxlanmgr_tun_stats_dentry_create()
+ *	Create dentry for a given tunnel.
+ */
+bool nss_vxlanmgr_tun_stats_dentry_create(struct nss_vxlanmgr_tun_ctx *tun_ctx)
+{
+	char dentry_name[IFNAMSIZ];
+
+	scnprintf(dentry_name, sizeof(dentry_name), "%s", tun_ctx->dev->name);
+	tun_ctx->dentry = debugfs_create_file(dentry_name, S_IRUGO,
+			tun_ctx->vxlan_ctx->dentry, tun_ctx, &nss_vxlanmgr_tun_stats_ops);
+	if (!tun_ctx->dentry) {
+		nss_vxlanmgr_warn("Debugfs file creation failed for tun %s\n", tun_ctx->dev->name);
+		return false;
+	}
+	return true;
+}
+
+/*
+ * nss_vxlanmgr_tun_stats_dentry_deinit()
+ *	Cleanup the debugfs tree.
+ */
+void nss_vxlanmgr_tun_stats_dentry_deinit()
+{
+	debugfs_remove_recursive(vxlan_ctx.dentry);
+}
+
+/*
+ * nss_vxlanmgr_tun_stats_dentry_init()
+ *	Create VxLAN tunnel statistics debugfs entry.
+ */
+bool nss_vxlanmgr_tun_stats_dentry_init()
+{
+	/*
+	 * initialize debugfs.
+	 */
+	vxlan_ctx.dentry = debugfs_create_dir("qca-nss-vxlanmgr", NULL);
+	if (!vxlan_ctx.dentry) {
+		nss_vxlanmgr_warn("Creating debug directory failed\n");
+		return false;
+	}
+	return true;
+}
diff --git a/qca-nss-clients/vxlanmgr/nss_vxlanmgr_tun_stats.h b/qca-nss-clients/vxlanmgr/nss_vxlanmgr_tun_stats.h
new file mode 100644
index 0000000..0be5194
--- /dev/null
+++ b/qca-nss-clients/vxlanmgr/nss_vxlanmgr_tun_stats.h
@@ -0,0 +1,66 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2019, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_VXLANMGR_TUN_STATS_H
+#define __NSS_VXLANMGR_TUN_STATS_H
+
+/*
+ * VxLAN statistic counters
+ */
+enum nss_vxlanmgr_tun_stats_type {
+	NSS_VXLANMGR_TUN_STATS_TYPE_RX_PKTS,
+	NSS_VXLANMGR_TUN_STATS_TYPE_RX_BYTES,
+	NSS_VXLANMGR_TUN_STATS_TYPE_TX_PKTS,
+	NSS_VXLANMGR_TUN_STATS_TYPE_TX_BYTES,
+	NSS_VXLANMGR_TUN_STATS_TYPE_RX_QUEUE_0_DROPPED,
+	NSS_VXLANMGR_TUN_STATS_TYPE_RX_QUEUE_1_DROPPED,
+	NSS_VXLANMGR_TUN_STATS_TYPE_RX_QUEUE_2_DROPPED,
+	NSS_VXLANMGR_TUN_STATS_TYPE_RX_QUEUE_3_DROPPED,
+	NSS_VXLANMGR_TUN_STATS_TYPE_MAC_DB_LOOKUP_FAILED,
+	NSS_VXLANMGR_TUN_STATS_TYPE_EXCEPT_HEADROOM_INSUFFICIENT,
+	NSS_VXLANMGR_TUN_STATS_TYPE_EXCEPT_MAC_MOVE,
+	NSS_VXLANMGR_TUN_STATS_TYPE_EXCEPT_NO_POLICY_ID,
+	NSS_VXLANMGR_TUN_STATS_TYPE_EXCEPT_EXTRA_FLAGS,
+	NSS_VXLANMGR_TUN_STATS_TYPE_EXCEPT_VNI_LOOKUP_FAILED,
+	NSS_VXLANMGR_TUN_STATS_TYPE_DROP_MALFORMED,
+	NSS_VXLANMGR_TUN_STATS_TYPE_DROP_NEXT_NODE_QUEUE_FULL,
+	NSS_VXLANMGR_TUN_STATS_TYPE_EXCEPT_INNER_HASH,
+	NSS_VXLANMGR_TUN_STATS_TYPE_MAX,
+};
+
+/*
+ * VxLAN tunnel statistics
+ */
+struct nss_vxlanmgr_tun_stats {
+	uint64_t inner_stats[NSS_VXLANMGR_TUN_STATS_TYPE_MAX];
+	uint64_t outer_stats[NSS_VXLANMGR_TUN_STATS_TYPE_MAX];
+	uint64_t host_packet_drop;
+	uint64_t mac_stats[NSS_VXLAN_MACDB_ENTRIES_MAX][2];
+};
+
+/*
+ * VxLAN statistics APIs
+ */
+extern void nss_vxlanmgr_tun_macdb_stats_sync(struct nss_vxlanmgr_tun_ctx *tun_ctx, struct nss_vxlan_msg *nvm);
+extern void nss_vxlanmgr_tun_stats_sync(struct nss_vxlanmgr_tun_ctx *tun_ctx, struct nss_vxlan_msg *nvm);
+extern void nss_vxlanmgr_tun_stats_deinit(struct nss_vxlanmgr_tun_ctx *tun_ctx);
+extern bool nss_vxlanmgr_tun_stats_init(struct nss_vxlanmgr_tun_ctx *tun_ctx);
+extern void nss_vxlanmgr_tun_stats_dentry_deinit(void);
+extern bool nss_vxlanmgr_tun_stats_dentry_init(void);
+extern void nss_vxlanmgr_tun_stats_dentry_remove(struct nss_vxlanmgr_tun_ctx *tun_ctx);
+extern bool nss_vxlanmgr_tun_stats_dentry_create(struct nss_vxlanmgr_tun_ctx *tun_ctx);
+
+#endif /* __NSS_VXLANMGR_TUN_STATS_H */
diff --git a/qca-nss-clients/vxlanmgr/nss_vxlanmgr_tunnel.c b/qca-nss-clients/vxlanmgr/nss_vxlanmgr_tunnel.c
new file mode 100644
index 0000000..fc99d4d
--- /dev/null
+++ b/qca-nss-clients/vxlanmgr/nss_vxlanmgr_tunnel.c
@@ -0,0 +1,1104 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/if_ether.h>
+#include <linux/in.h>
+#include <linux/ip.h>
+#include <linux/netdevice.h>
+#include <linux/skbuff.h>
+#include <linux/version.h>
+#include <net/addrconf.h>
+#include <net/dst.h>
+#include <net/flow.h>
+#include <net/ipv6.h>
+#include <net/route.h>
+#include <net/vxlan.h>
+#include <nss_api_if.h>
+#include "nss_vxlanmgr.h"
+#include "nss_vxlanmgr_tun_stats.h"
+
+/*
+ * VxLAN context
+ */
+extern struct nss_vxlanmgr_ctx vxlan_ctx;
+
+/*
+ * nss_vxlanmgr_tunnel_ctx_dev_get()
+ *	Find VxLAN tunnel context using netdev.
+ *	Context lock must be held before calling this API.
+ */
+struct nss_vxlanmgr_tun_ctx *nss_vxlanmgr_tunnel_ctx_dev_get(struct net_device *dev)
+{
+	struct nss_vxlanmgr_tun_ctx *tun_ctx;
+
+	list_for_each_entry(tun_ctx, &vxlan_ctx.list, head) {
+		if (tun_ctx->dev == dev) {
+			return tun_ctx;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * nss_vxlanmgr_tunnel_tx_msg()
+ *	Transmit VxLAN tunnel operation messages asynchronously.
+ */
+static nss_tx_status_t nss_vxlanmgr_tunnel_tx_msg(struct nss_ctx_instance *ctx,
+						  struct nss_vxlan_msg *msg,
+						  uint32_t if_num,
+						  enum nss_vxlan_msg_type type,
+						  uint32_t len)
+{
+	nss_vxlan_msg_init(msg, if_num, type, len, NULL, NULL);
+	return nss_vxlan_tx_msg(ctx, msg);
+}
+
+/*
+ * nss_vxlanmgr_tunnel_tx_msg_sync()
+ *	Transmit VxLAN tunnel operation messages.
+ */
+static nss_tx_status_t nss_vxlanmgr_tunnel_tx_msg_sync(struct nss_ctx_instance *ctx,
+							struct nss_vxlan_msg *msg,
+							uint32_t if_num,
+							enum nss_vxlan_msg_type type,
+							uint32_t len)
+{
+	nss_vxlan_msg_init(msg, if_num, type, len, NULL, NULL);
+	return nss_vxlan_tx_msg_sync(ctx, msg);
+}
+
+/*
+ * nss_vxlanmgr_tunnel_flags_parse()
+ *	Function to parse vxlan flags.
+ */
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 5, 7))
+static uint16_t nss_vxlanmgr_tunnel_flags_parse(struct vxlan_dev *priv)
+{
+	uint16_t flags = 0;
+	uint32_t priv_flags = priv->flags;
+
+	if (priv_flags & VXLAN_F_RSC)
+		return flags;
+	if (priv_flags & VXLAN_F_GBP)
+		flags |= NSS_VXLAN_RULE_FLAG_GBP_ENABLED;
+
+	if (priv_flags & VXLAN_F_IPV6) {
+		flags |= NSS_VXLAN_RULE_FLAG_IPV6;
+		if (!(priv_flags & VXLAN_F_UDP_ZERO_CSUM6_TX))
+			flags |= NSS_VXLAN_RULE_FLAG_ENCAP_L4_CSUM_REQUIRED;
+	} else {
+		flags |= NSS_VXLAN_RULE_FLAG_IPV4;
+		if (priv_flags & VXLAN_F_UDP_CSUM)
+			flags |= NSS_VXLAN_RULE_FLAG_ENCAP_L4_CSUM_REQUIRED;
+	}
+
+	if (priv->cfg.tos == 1)
+		flags |= NSS_VXLAN_RULE_FLAG_INHERIT_TOS;
+
+	return (flags | NSS_VXLAN_RULE_FLAG_UDP);
+}
+#else
+static uint16_t nss_vxlanmgr_tunnel_flags_parse(struct vxlan_dev *priv)
+{
+	uint16_t flags = 0;
+	struct vxlan_config *cfg = &priv->cfg;
+	uint32_t priv_flags = cfg->flags;
+
+	if (priv_flags & VXLAN_F_RSC)
+		return flags;
+	if (priv_flags & VXLAN_F_GPE)
+		return flags;
+	if (priv_flags & VXLAN_F_GBP)
+		flags |= NSS_VXLAN_RULE_FLAG_GBP_ENABLED;
+
+	if (priv_flags & VXLAN_F_IPV6) {
+		flags |= NSS_VXLAN_RULE_FLAG_IPV6;
+		if (!(priv_flags & VXLAN_F_UDP_ZERO_CSUM6_TX))
+			flags |= NSS_VXLAN_RULE_FLAG_ENCAP_L4_CSUM_REQUIRED;
+	} else {
+		flags |= NSS_VXLAN_RULE_FLAG_IPV4;
+		if (!(priv_flags & VXLAN_F_UDP_ZERO_CSUM_TX))
+			flags |= NSS_VXLAN_RULE_FLAG_ENCAP_L4_CSUM_REQUIRED;
+	}
+
+	if (cfg->tos == 1)
+		flags |= NSS_VXLAN_RULE_FLAG_INHERIT_TOS;
+
+	return (flags | NSS_VXLAN_RULE_FLAG_UDP);
+}
+#endif
+
+/*
+ * nss_vxlanmgr_tunnel_fill_src_ip()
+ *	Return src_ip using route lookup.
+ */
+static bool nss_vxlanmgr_tunnel_fill_src_ip(struct vxlan_dev *vxlan,
+						union vxlan_addr *src_ip,
+						union vxlan_addr *rem_ip,
+						sa_family_t sa_family,
+						uint32_t *new_src_ip)
+{
+	struct flowi4 fl4;
+	struct flowi6 fl6;
+	struct rtable *rt = NULL;
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 5, 7))
+	struct dst_entry *dst = NULL;
+	int err;
+#else
+	const struct in6_addr *final_dst = NULL;
+	struct dst_entry *dentry;
+#endif
+
+	/*
+	 * IPv4
+	 */
+	if (sa_family == AF_INET) {
+		if (src_ip->sin.sin_addr.s_addr == htonl(INADDR_ANY)) {
+			/*
+			 * Lookup
+			 */
+			memset(&fl4, 0, sizeof(fl4));
+			fl4.flowi4_proto = IPPROTO_UDP;
+			fl4.daddr = rem_ip->sin.sin_addr.s_addr;
+			fl4.saddr = src_ip->sin.sin_addr.s_addr;
+
+			rt = ip_route_output_key(vxlan->net, &fl4);
+			if (IS_ERR(rt)) {
+				nss_vxlanmgr_warn("No route available.\n");
+				return false;
+			}
+			new_src_ip[0] = fl4.saddr;
+			return true;
+		}
+		new_src_ip[0] = src_ip->sin.sin_addr.s_addr;
+		return true;
+	}
+
+	/*
+	 * IPv6
+	 */
+	if (ipv6_addr_any(&src_ip->sin6.sin6_addr)) {
+		/*
+		 * Lookup
+		 */
+		memset(&fl6, 0, sizeof(fl6));
+		fl6.flowi6_proto = IPPROTO_UDP;
+		fl6.daddr = rem_ip->sin6.sin6_addr;
+		fl6.saddr = src_ip->sin6.sin6_addr;
+
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 5, 7))
+		err = ipv6_stub->ipv6_dst_lookup(vxlan->net,
+				vxlan->vn6_sock->sock->sk, &dst, &fl6);
+		if (err < 0) {
+#else
+		dentry = ipv6_stub->ipv6_dst_lookup_flow(vxlan->net,
+				vxlan->vn6_sock->sock->sk, &fl6, final_dst);
+		if (!dentry) {
+#endif
+			nss_vxlanmgr_warn("No route, drop packet.\n");
+			return false;
+		}
+		memcpy(new_src_ip, &fl6.saddr, sizeof(struct in6_addr));
+		return true;
+	}
+	memcpy(new_src_ip, &src_ip->sin6.sin6_addr, sizeof(struct in6_addr));
+	return true;
+}
+
+/*
+ * nss_vxlanmgr_tunnel_mac_del()
+ *	VxLAN tunnel mac delete messages.
+ */
+static nss_tx_status_t nss_vxlanmgr_tunnel_mac_del(struct nss_vxlanmgr_tun_ctx *tun_ctx,
+						   struct vxlan_fdb_event *vfe)
+{
+	struct net_device *dev;
+	struct nss_vxlan_mac_msg *mac_del_msg;
+	struct nss_vxlan_msg vxlanmsg;
+	struct vxlan_config *cfg;
+	struct vxlan_dev *priv;
+	union vxlan_addr *remote_ip, *src_ip;
+	uint32_t i, inner_ifnum;
+	nss_tx_status_t status = NSS_TX_FAILURE;
+
+	dev = vfe->dev;
+	dev_hold(dev);
+
+	spin_lock_bh(&vxlan_ctx.tun_lock);
+	inner_ifnum = tun_ctx->inner_ifnum;
+	spin_unlock_bh(&vxlan_ctx.tun_lock);
+
+	/*
+	 * Only non-zero mac entries should be sent to NSS.
+	 */
+	if (is_zero_ether_addr(vfe->eth_addr)) {
+		nss_vxlanmgr_trace("Only non-zero mac entries should be sent to NSS.\n");
+		goto done;
+	}
+
+	memset(&vxlanmsg, 0, sizeof(struct nss_vxlan_msg));
+	priv = netdev_priv(dev);
+
+	/*
+	 * Set MAC rule message
+	 */
+	mac_del_msg = &vxlanmsg.msg.mac_del;
+	mac_del_msg->vni = vxlan_get_vni(priv);
+	ether_addr_copy((uint8_t *)mac_del_msg->mac_addr, (uint8_t *)vfe->eth_addr);
+
+	cfg = &priv->cfg;
+	src_ip = &cfg->saddr;
+	remote_ip = &vfe->rdst->remote_ip;
+
+	if (remote_ip->sa.sa_family == AF_INET){
+		if (remote_ip->sin.sin_addr.s_addr == htonl(INADDR_ANY)) {
+			nss_vxlanmgr_warn("%px: MAC deletion failed for unknown remote\n", dev);
+			goto done;
+		}
+		memcpy(&mac_del_msg->encap.dest_ip, &remote_ip->sin.sin_addr, sizeof(struct in_addr));
+		memcpy(&mac_del_msg->encap.src_ip, &src_ip->sin.sin_addr, sizeof(struct in_addr));
+	} else {
+		if (ipv6_addr_any(&remote_ip->sin6.sin6_addr)) {
+			nss_vxlanmgr_warn("%px: MAC deletion failed for unknown remote\n", dev);
+			goto done;
+		}
+		memcpy(&mac_del_msg->encap.dest_ip, &remote_ip->sin6.sin6_addr, sizeof(struct in6_addr));
+		memcpy(&mac_del_msg->encap.src_ip, &src_ip->sin6.sin6_addr, sizeof(struct in6_addr));
+	}
+
+	/*
+	 * Send MAC del message asynchronously as it is called by chain
+	 * notifier in atomic context from the vxlan driver.
+	 */
+	status = nss_vxlanmgr_tunnel_tx_msg(vxlan_ctx.nss_ctx,
+						&vxlanmsg,
+						inner_ifnum,
+						NSS_VXLAN_MSG_TYPE_MAC_DEL,
+						sizeof(struct nss_vxlan_mac_msg));
+	if (status != NSS_TX_SUCCESS) {
+		nss_vxlanmgr_warn("%px: MAC deletion failed %d\n", dev, status);
+	}
+
+	spin_lock_bh(&vxlan_ctx.tun_lock);
+	for (i = 0; i < NSS_VXLAN_MACDB_ENTRIES_MAX; i++) {
+		if (ether_addr_equal((uint8_t *)&tun_ctx->stats->mac_stats[i][0], (uint8_t *)vfe->eth_addr)) {
+			tun_ctx->stats->mac_stats[i][0] = 0;
+			tun_ctx->stats->mac_stats[i][1] = 0;
+			break;
+		}
+	}
+	spin_unlock_bh(&vxlan_ctx.tun_lock);
+
+done:
+	dev_put(dev);
+	return status;
+}
+
+/*
+ * nss_vxlanmgr_tunnel_mac_add()
+ *	VxLAN tunnel mac add messages.
+ */
+static nss_tx_status_t nss_vxlanmgr_tunnel_mac_add(struct nss_vxlanmgr_tun_ctx *tun_ctx,
+						   struct vxlan_fdb_event *vfe)
+{
+	struct net_device *dev;
+	struct nss_vxlan_mac_msg *mac_add_msg;
+	struct nss_vxlan_msg vxlanmsg;
+	struct vxlan_config *cfg;
+	struct vxlan_dev *priv;
+	union vxlan_addr *remote_ip, *src_ip;
+	uint32_t i, inner_ifnum;
+	uint32_t new_src_ip[4] = {0};
+	nss_tx_status_t status = NSS_TX_FAILURE;
+
+	dev = vfe->dev;
+	dev_hold(dev);
+
+	spin_lock_bh(&vxlan_ctx.tun_lock);
+	inner_ifnum = tun_ctx->inner_ifnum;
+	spin_unlock_bh(&vxlan_ctx.tun_lock);
+
+	/*
+	 * Only non-zero mac entries should be sent to NSS.
+	 */
+	if (is_zero_ether_addr(vfe->eth_addr)) {
+		nss_vxlanmgr_trace("Only non-zero mac entries should be sent to NSS.\n");
+		goto done;
+	}
+
+	memset(&vxlanmsg, 0, sizeof(struct nss_vxlan_msg));
+	priv = netdev_priv(dev);
+
+	/*
+	 * Set MAC rule message
+	 */
+	mac_add_msg = &vxlanmsg.msg.mac_add;
+	mac_add_msg->vni = vxlan_get_vni(priv);
+	ether_addr_copy((uint8_t *)mac_add_msg->mac_addr, (uint8_t *)vfe->eth_addr);
+
+	cfg = &priv->cfg;
+	src_ip = &cfg->saddr;
+	remote_ip = &vfe->rdst->remote_ip;
+
+	if (remote_ip->sa.sa_family == AF_INET){
+		if (remote_ip->sin.sin_addr.s_addr == htonl(INADDR_ANY)) {
+			nss_vxlanmgr_warn("%px: MAC addition failed for unknown remote\n", dev);
+			goto done;
+		}
+		memcpy(&mac_add_msg->encap.dest_ip[0], &remote_ip->sin.sin_addr, sizeof(struct in_addr));
+		if (!nss_vxlanmgr_tunnel_fill_src_ip(priv, src_ip, remote_ip, AF_INET, new_src_ip)) {
+			nss_vxlanmgr_warn("%px: MAC addition failed for unknown source\n", dev);
+			goto done;
+		}
+		mac_add_msg->encap.src_ip[0] = new_src_ip[0];
+	} else {
+		if (ipv6_addr_any(&remote_ip->sin6.sin6_addr)) {
+			nss_vxlanmgr_warn("%px: MAC addition failed for unknown remote\n", dev);
+			goto done;
+		}
+		memcpy(mac_add_msg->encap.dest_ip, &remote_ip->sin6.sin6_addr, sizeof(struct in6_addr));
+		if (!nss_vxlanmgr_tunnel_fill_src_ip(priv, src_ip, remote_ip, AF_INET6, new_src_ip)) {
+			nss_vxlanmgr_warn("%px: MAC addition failed for unknown source\n", dev);
+			goto done;
+		}
+		memcpy(mac_add_msg->encap.src_ip, new_src_ip, sizeof(struct in6_addr));
+	}
+
+	/*
+	 * Send MAC add message asynchronously as it is called by chain
+	 * notifier in atomic context from the vxlan driver.
+	 */
+	status = nss_vxlanmgr_tunnel_tx_msg(vxlan_ctx.nss_ctx,
+						&vxlanmsg,
+						inner_ifnum,
+						NSS_VXLAN_MSG_TYPE_MAC_ADD,
+						sizeof(struct nss_vxlan_mac_msg));
+	if (status != NSS_TX_SUCCESS) {
+		nss_vxlanmgr_warn("%px: MAC addition failed %d\n", dev, status);
+		goto done;
+	}
+
+	spin_lock_bh(&vxlan_ctx.tun_lock);
+	for (i = 0; i < NSS_VXLAN_MACDB_ENTRIES_MAX; i++) {
+		if (!tun_ctx->stats->mac_stats[i][0]) {
+			ether_addr_copy((uint8_t *)&tun_ctx->stats->mac_stats[i][0],
+					(uint8_t *)vfe->eth_addr);
+			break;
+		}
+	}
+	spin_unlock_bh(&vxlan_ctx.tun_lock);
+
+done:
+	dev_put(dev);
+	return status;
+}
+
+/*
+ * nss_vxlanmgr_tunnel_fdb_event()
+ *	Event handler for VxLAN fdb updates
+ */
+static int nss_vxlanmgr_tunnel_fdb_event(struct notifier_block *nb, unsigned long event, void *data)
+{
+	struct vxlan_fdb_event *vfe;
+	struct nss_vxlanmgr_tun_ctx *tun_ctx;
+
+	vfe = (struct vxlan_fdb_event *)data;
+	spin_lock_bh(&vxlan_ctx.tun_lock);
+	tun_ctx = nss_vxlanmgr_tunnel_ctx_dev_get(vfe->dev);
+	if (!tun_ctx) {
+		spin_unlock_bh(&vxlan_ctx.tun_lock);
+		nss_vxlanmgr_warn("%px: Invalid tunnel context\n", vfe->dev);
+		return NOTIFY_DONE;
+	}
+	spin_unlock_bh(&vxlan_ctx.tun_lock);
+
+	switch(event) {
+	case RTM_DELNEIGH:
+		nss_vxlanmgr_tunnel_mac_del(tun_ctx, vfe);
+		break;
+	case RTM_NEWNEIGH:
+		nss_vxlanmgr_tunnel_mac_add(tun_ctx, vfe);
+		break;
+	default:
+		nss_vxlanmgr_warn("%lu: Unknown FDB event received.\n", event);
+	}
+	return NOTIFY_DONE;
+}
+
+/*
+ * Notifier to receive fdb events from VxLAN
+ */
+static struct notifier_block nss_vxlanmgr_tunnel_fdb_notifier = {
+	.notifier_call = nss_vxlanmgr_tunnel_fdb_event,
+};
+
+/*
+ * nss_vxlanmgr_tunnel_inner_stats()
+ *	Update vxlan netdev stats with inner node stats
+ */
+static void nss_vxlanmgr_tunnel_inner_stats(struct nss_vxlanmgr_tun_ctx *tun_ctx, struct nss_vxlan_msg *nvm)
+{
+	struct nss_vxlan_stats_msg *stats;
+	struct pcpu_sw_netstats *tstats;
+	struct net_device *dev;
+	struct net_device_stats *netdev_stats;
+	uint32_t i;
+	uint64_t dropped = 0;
+
+	stats = &nvm->msg.stats;
+	dev = tun_ctx->dev;
+
+	dev_hold(dev);
+	netdev_stats = (struct net_device_stats *)&dev->stats;
+
+	/*
+	 * Only look at the tx_packets/tx_bytes for both host_inner/outer interfaces.
+	 * rx_bytes/rx_packets are increased when the packet is received by the node.
+	 * Therefore, it includes both transmitted/dropped packets. tx_bytes/tx_packets
+	 * reflect successfully transmitted packets.
+	 */
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		dropped += stats->node_stats.rx_dropped[i];
+	}
+
+	tstats = this_cpu_ptr(dev->tstats);
+	u64_stats_update_begin(&tstats->syncp);
+	tstats->tx_packets += stats->node_stats.tx_packets;
+	tstats->tx_bytes += stats->node_stats.tx_bytes;
+	u64_stats_update_end(&tstats->syncp);
+	netdev_stats->tx_dropped += dropped;
+	dev_put(dev);
+}
+
+/*
+ * nss_vxlanmgr_tunnel_outer_stats()
+ *	Update vxlan netdev stats with outer node stats
+ */
+static void nss_vxlanmgr_tunnel_outer_stats(struct nss_vxlanmgr_tun_ctx *tun_ctx, struct nss_vxlan_msg *nvm)
+{
+	struct nss_vxlan_stats_msg *stats;
+	struct pcpu_sw_netstats *tstats;
+	struct net_device *dev;
+	struct net_device_stats *netdev_stats;
+	uint32_t i;
+	uint64_t dropped = 0;
+
+	stats = &nvm->msg.stats;
+	dev = tun_ctx->dev;
+
+	dev_hold(dev);
+	netdev_stats = (struct net_device_stats *)&dev->stats;
+
+	/*
+	 * Only look at the tx_packets/tx_bytes for both host_inner/outer interfaces.
+	 * rx_bytes/rx_packets are increased when the packet is received by the node.
+	 * Therefore, it includes both transmitted/dropped packets. tx_bytes/tx_packets
+	 * reflect successfully transmitted packets.
+	 */
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		dropped += stats->node_stats.rx_dropped[i];
+	}
+
+	tstats = this_cpu_ptr(dev->tstats);
+	u64_stats_update_begin(&tstats->syncp);
+	tstats->rx_packets += stats->node_stats.tx_packets;
+	tstats->rx_bytes += stats->node_stats.tx_bytes;
+	u64_stats_update_end(&tstats->syncp);
+	netdev_stats->rx_dropped += dropped;
+	dev_put(dev);
+}
+
+/*
+ * nss_vxlanmgr_tunnel_fdb_update()
+ *	Update vxlan fdb entries
+ */
+static void nss_vxlanmgr_tunnel_fdb_update(struct nss_vxlanmgr_tun_ctx *tun_ctx, struct nss_vxlan_msg *nvm)
+{
+	uint8_t *mac;
+	uint16_t i, nentries;
+	struct vxlan_dev *priv;
+	struct nss_vxlan_macdb_stats_msg *db_stats;
+
+	db_stats = &nvm->msg.db_stats;
+	nentries = db_stats->cnt;
+	priv = netdev_priv(tun_ctx->dev);
+
+	dev_hold(tun_ctx->dev);
+
+	if (nentries > NSS_VXLAN_MACDB_ENTRIES_PER_MSG) {
+		nss_vxlanmgr_warn("%px: No more than 20 entries allowed per message.\n", tun_ctx->dev);
+		dev_put(tun_ctx->dev);
+		return;
+	}
+
+	for (i = 0; i < nentries; i++) {
+		if (likely(db_stats->entry[i].hits)) {
+			mac = (uint8_t *)db_stats->entry[i].mac;
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 5, 7))
+			vxlan_fdb_update_mac(priv, mac);
+#else
+			vxlan_fdb_update_mac(priv, mac, tun_ctx->vni);
+#endif
+		}
+	}
+	dev_put(tun_ctx->dev);
+}
+
+/*
+ * nss_vxlanmgr_tunnel_inner_notifier()
+ *	Notifier for vxlan tunnel encap node
+ */
+static void nss_vxlanmgr_tunnel_inner_notifier(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct net_device *dev = (struct net_device *)app_data;
+	struct nss_vxlanmgr_tun_ctx *tun_ctx;
+	struct nss_vxlan_msg *nvm;
+
+	if (!ncm) {
+	    nss_vxlanmgr_info("%px: NULL msg received.\n", dev);
+	    return;
+	}
+
+	spin_lock_bh(&vxlan_ctx.tun_lock);
+	tun_ctx = nss_vxlanmgr_tunnel_ctx_dev_get(dev);
+	if (!tun_ctx) {
+		spin_unlock_bh(&vxlan_ctx.tun_lock);
+		nss_vxlanmgr_warn("%px: Invalid tunnel context\n", dev);
+		return;
+	}
+
+	nvm = (struct nss_vxlan_msg *)ncm;
+	switch (nvm->cm.type) {
+	case NSS_VXLAN_MSG_TYPE_STATS_SYNC:
+		nss_vxlanmgr_tunnel_inner_stats(tun_ctx, nvm);
+		nss_vxlanmgr_tun_stats_sync(tun_ctx, nvm);
+		break;
+	case NSS_VXLAN_MSG_TYPE_MACDB_STATS:
+		nss_vxlanmgr_tunnel_fdb_update(tun_ctx, nvm);
+		nss_vxlanmgr_tun_macdb_stats_sync(tun_ctx, nvm);
+		break;
+	default:
+		spin_unlock_bh(&vxlan_ctx.tun_lock);
+		nss_vxlanmgr_info("%px: Unknown Event from NSS", dev);
+		return;
+	}
+	spin_unlock_bh(&vxlan_ctx.tun_lock);
+}
+
+/*
+ * nss_vxlanmgr_tunnel_outer_notifier()
+ *	Notifier for vxlan tunnel decap node
+ */
+static void nss_vxlanmgr_tunnel_outer_notifier(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct net_device *dev = (struct net_device *)app_data;
+	struct nss_vxlanmgr_tun_ctx *tun_ctx;
+	struct nss_vxlan_msg *nvm;
+
+	if (!ncm) {
+	    nss_vxlanmgr_info("%px: NULL msg received.\n", dev);
+	    return;
+	}
+
+	spin_lock_bh(&vxlan_ctx.tun_lock);
+	tun_ctx = nss_vxlanmgr_tunnel_ctx_dev_get(dev);
+	if (!tun_ctx) {
+		spin_unlock_bh(&vxlan_ctx.tun_lock);
+		nss_vxlanmgr_warn("%px: Invalid tunnel context\n", dev);
+		return;
+	}
+
+	nvm = (struct nss_vxlan_msg *)ncm;
+	switch (nvm->cm.type) {
+	case NSS_VXLAN_MSG_TYPE_STATS_SYNC:
+		nss_vxlanmgr_tunnel_outer_stats(tun_ctx, nvm);
+		nss_vxlanmgr_tun_stats_sync(tun_ctx, nvm);
+		break;
+	default:
+		spin_unlock_bh(&vxlan_ctx.tun_lock);
+		nss_vxlanmgr_info("%px: Unknown Event from NSS", dev);
+		return;
+	}
+	spin_unlock_bh(&vxlan_ctx.tun_lock);
+}
+
+/*
+ * nss_vxlanmgr_tunnel_inner_recv()
+ *	Receives a pkt from NSS
+ */
+static void nss_vxlanmgr_tunnel_inner_recv(struct net_device *dev, struct sk_buff *skb,
+		__attribute__((unused)) struct napi_struct *napi)
+{
+	dev_hold(dev);
+	nss_vxlanmgr_info("%px: (vxlan packet) Exception packet received.\n", dev);
+
+	/*
+	 * These are decapped and exceptioned packets.
+	 */
+	skb->protocol = eth_type_trans(skb, dev);
+	netif_receive_skb(skb);
+	dev_put(dev);
+	return;
+}
+
+/*
+ * nss_vxlanmgr_tunnel_outer_recv()
+ *	Receives a pkt from NSS
+ */
+static void nss_vxlanmgr_tunnel_outer_recv(struct net_device *dev, struct sk_buff *skb,
+		__attribute__((unused)) struct napi_struct *napi)
+{
+	struct iphdr *iph;
+	size_t l3_hdr_size;
+	struct nss_vxlanmgr_tun_ctx *tun_ctx;
+
+	nss_vxlanmgr_info("%px: (vxlan packet) Exception packet received.\n", dev);
+
+	spin_lock_bh(&vxlan_ctx.tun_lock);
+	tun_ctx = nss_vxlanmgr_tunnel_ctx_dev_get(dev);
+	if (!tun_ctx) {
+		spin_unlock_bh(&vxlan_ctx.tun_lock);
+		nss_vxlanmgr_warn("%px: Invalid tunnel context\n", dev);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	iph = (struct iphdr *)skb->data;
+	switch (iph->version) {
+	case 4:
+		l3_hdr_size = sizeof(struct iphdr);
+		skb->protocol = htons(ETH_P_IP);
+		break;
+	case 6:
+		l3_hdr_size = sizeof(struct ipv6hdr);
+		skb->protocol = htons(ETH_P_IPV6);
+		break;
+	default:
+		tun_ctx->stats->host_packet_drop++;
+		spin_unlock_bh(&vxlan_ctx.tun_lock);
+		nss_vxlanmgr_trace("%px: Skb received with unknown IP version: %d.\n", dev, iph->version);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	/*
+	 * VxLAN encapsulated packet exceptioned, remove the encapsulation
+	 * and transmit on VxLAN interface.
+	 */
+	if (unlikely(!pskb_may_pull(skb, (l3_hdr_size + sizeof(struct udphdr)
+							+ sizeof(struct vxlanhdr))))) {
+		tun_ctx->stats->host_packet_drop++;
+		spin_unlock_bh(&vxlan_ctx.tun_lock);
+		nss_vxlanmgr_trace("%px: pskb_may_pull failed for skb:%px\n", dev, skb);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	skb_pull(skb, (l3_hdr_size + sizeof(struct udphdr) + sizeof(struct vxlanhdr)));
+
+	/*
+	 * Inner ethernet payload.
+	 */
+	if (unlikely(!pskb_may_pull(skb, sizeof(struct ethhdr)))) {
+		tun_ctx->stats->host_packet_drop++;
+		spin_unlock_bh(&vxlan_ctx.tun_lock);
+		nss_vxlanmgr_trace("%px: pskb_may_pull failed for skb:%px\n", dev, skb);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+
+	spin_unlock_bh(&vxlan_ctx.tun_lock);
+	skb->dev = dev;
+	skb_reset_mac_header(skb);
+	skb_reset_network_header(skb);
+	skb_reset_transport_header(skb);
+	skb_reset_mac_len(skb);
+	dev_queue_xmit(skb);
+}
+
+/*
+ * nss_vxlanmgr_tunnel_deconfig()
+ *	Function to send dynamic interface disable message
+ */
+int nss_vxlanmgr_tunnel_deconfig(struct net_device *dev)
+{
+	struct nss_vxlanmgr_tun_ctx *tun_ctx;
+	uint32_t inner_ifnum, outer_ifnum;
+	struct nss_vxlan_msg vxlanmsg;
+	nss_tx_status_t ret;
+
+	dev_hold(dev);
+
+	spin_lock_bh(&vxlan_ctx.tun_lock);
+	tun_ctx = nss_vxlanmgr_tunnel_ctx_dev_get(dev);
+	if (!tun_ctx) {
+		spin_unlock_bh(&vxlan_ctx.tun_lock);
+		nss_vxlanmgr_warn("%px: Invalid tunnel context\n", dev);
+		goto done;
+	}
+
+	inner_ifnum = tun_ctx->inner_ifnum;
+	outer_ifnum = tun_ctx->outer_ifnum;
+	spin_unlock_bh(&vxlan_ctx.tun_lock);
+
+	memset(&vxlanmsg, 0, sizeof(struct nss_vxlan_msg));
+
+	ret = nss_vxlanmgr_tunnel_tx_msg_sync(vxlan_ctx.nss_ctx,
+						&vxlanmsg,
+						inner_ifnum,
+						NSS_VXLAN_MSG_TYPE_TUN_DISABLE, 0);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_vxlanmgr_warn("%px: Sending configuration to inner interface failed: %d\n", dev, ret);
+		goto done;
+	}
+
+	ret = nss_vxlanmgr_tunnel_tx_msg_sync(vxlan_ctx.nss_ctx,
+						&vxlanmsg,
+						outer_ifnum,
+						NSS_VXLAN_MSG_TYPE_TUN_DISABLE, 0);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_vxlanmgr_warn("%px: Sending configuration to outer interface failed: %d\n", dev, ret);
+	}
+
+done:
+	dev_put(dev);
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_vxlanmgr_tunnel_config()
+ *	Function to send dynamic interface enable message
+ */
+int nss_vxlanmgr_tunnel_config(struct net_device *dev)
+{
+	uint32_t inner_ifnum, outer_ifnum;
+	struct nss_vxlanmgr_tun_ctx *tun_ctx;
+	struct nss_vxlan_msg vxlanmsg;
+	nss_tx_status_t ret;
+
+	dev_hold(dev);
+
+	spin_lock_bh(&vxlan_ctx.tun_lock);
+	tun_ctx = nss_vxlanmgr_tunnel_ctx_dev_get(dev);
+	if (!tun_ctx) {
+		spin_unlock_bh(&vxlan_ctx.tun_lock);
+		nss_vxlanmgr_warn("%px: Invalid tunnel context\n", dev);
+		goto done;
+	}
+
+	inner_ifnum = tun_ctx->inner_ifnum;
+	outer_ifnum = tun_ctx->outer_ifnum;
+	spin_unlock_bh(&vxlan_ctx.tun_lock);
+
+	memset(&vxlanmsg, 0, sizeof(struct nss_vxlan_msg));
+
+	ret = nss_vxlanmgr_tunnel_tx_msg_sync(vxlan_ctx.nss_ctx,
+						&vxlanmsg,
+						inner_ifnum,
+						NSS_VXLAN_MSG_TYPE_TUN_ENABLE, 0);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_vxlanmgr_warn("%px: Sending configuration to inner interface failed: %d\n", dev, ret);
+		goto done;
+	}
+
+	ret = nss_vxlanmgr_tunnel_tx_msg_sync(vxlan_ctx.nss_ctx,
+						&vxlanmsg,
+						outer_ifnum,
+						NSS_VXLAN_MSG_TYPE_TUN_ENABLE, 0);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_vxlanmgr_warn("%px: Sending configuration to outer interface failed: %d\n", dev, ret);
+		/*
+		 * Disable inner node.
+		 */
+		nss_vxlanmgr_tunnel_tx_msg_sync(vxlan_ctx.nss_ctx,
+						&vxlanmsg,
+						inner_ifnum,
+						NSS_VXLAN_MSG_TYPE_TUN_DISABLE, 0);
+	}
+
+done:
+	dev_put(dev);
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_vxlanmgr_tunnel_destroy()
+ *	Function to unregister and destroy dynamic interfaces.
+ */
+int nss_vxlanmgr_tunnel_destroy(struct net_device *dev)
+{
+	uint32_t inner_ifnum, outer_ifnum;
+	struct nss_vxlanmgr_tun_ctx *tun_ctx;
+	struct nss_vxlan_msg vxlanmsg;
+	nss_tx_status_t ret;
+
+	dev_hold(dev);
+
+	spin_lock_bh(&vxlan_ctx.tun_lock);
+	if (!vxlan_ctx.tun_count) {
+		spin_unlock_bh(&vxlan_ctx.tun_lock);
+		nss_vxlanmgr_warn("%px: No more tunnels to destroy.\n", dev);
+		goto done;
+	}
+
+	tun_ctx = nss_vxlanmgr_tunnel_ctx_dev_get(dev);
+	if (!tun_ctx) {
+		spin_unlock_bh(&vxlan_ctx.tun_lock);
+		nss_vxlanmgr_warn("%px: Invalid tunnel context\n", dev);
+		goto done;
+	}
+
+	inner_ifnum = tun_ctx->inner_ifnum;
+	outer_ifnum = tun_ctx->outer_ifnum;
+
+	/*
+	 * Remove tunnel from global list.
+	 */
+	list_del(&tun_ctx->head);
+
+	/*
+	 * Decrement interface count.
+	 */
+	vxlan_ctx.tun_count--;
+	spin_unlock_bh(&vxlan_ctx.tun_lock);
+
+	nss_vxlanmgr_tun_stats_deinit(tun_ctx);
+	nss_vxlanmgr_tun_stats_dentry_remove(tun_ctx);
+	kfree(tun_ctx);
+
+	if (!vxlan_ctx.tun_count) {
+		/*
+		 * Unregister fdb notifier chain if
+		 * all vxlan tunnels are destroyed.
+		 */
+		vxlan_fdb_unregister_notify(&nss_vxlanmgr_tunnel_fdb_notifier);
+	}
+	nss_vxlanmgr_info("%px: VxLAN interface count is #%d\n", dev, vxlan_ctx.tun_count);
+
+	memset(&vxlanmsg, 0, sizeof(struct nss_vxlan_msg));
+	ret = nss_vxlanmgr_tunnel_tx_msg_sync(vxlan_ctx.nss_ctx,
+						&vxlanmsg,
+						inner_ifnum,
+						NSS_VXLAN_MSG_TYPE_TUN_UNCONFIGURE, 0);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_vxlanmgr_warn("%px: Sending configuration to inner interface failed: %d\n", dev, ret);
+	}
+
+	if (!nss_vxlan_unregister_if(inner_ifnum)) {
+		nss_vxlanmgr_warn("%px: Inner interface not found\n", dev);
+	}
+	ret = nss_dynamic_interface_dealloc_node(inner_ifnum,
+						NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_INNER);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_vxlanmgr_warn("%px: Failed to dealloc inner: %d\n", dev, ret);
+	}
+
+	ret = nss_vxlanmgr_tunnel_tx_msg_sync(vxlan_ctx.nss_ctx,
+						&vxlanmsg,
+						outer_ifnum,
+						NSS_VXLAN_MSG_TYPE_TUN_UNCONFIGURE, 0);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_vxlanmgr_warn("%px: Sending configuration to outer interface failed: %d\n", dev, ret);
+	}
+
+	if (!nss_vxlan_unregister_if(outer_ifnum)) {
+		nss_vxlanmgr_warn("%px: Outer interface not found\n", dev);
+	}
+	ret = nss_dynamic_interface_dealloc_node(outer_ifnum,
+						NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_OUTER);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_vxlanmgr_warn("%px: Failed to dealloc outer: %d\n", dev, ret);
+	}
+
+done:
+	dev_put(dev);
+	return NOTIFY_DONE;
+}
+
+/*
+ * nss_vxlanmgr_tunnel_create()
+ *	Function to create and register dynamic interfaces.
+ */
+int nss_vxlanmgr_tunnel_create(struct net_device *dev)
+{
+	struct vxlan_dev *priv;
+	struct nss_vxlan_msg vxlanmsg;
+	struct nss_vxlanmgr_tun_ctx *tun_ctx;
+	struct nss_vxlan_rule_msg *vxlan_cfg;
+	struct nss_ctx_instance *nss_ctx;
+	uint32_t inner_ifnum, outer_ifnum;
+	uint16_t parse_flags;
+	nss_tx_status_t ret;
+
+	spin_lock_bh(&vxlan_ctx.tun_lock);
+	if (vxlan_ctx.tun_count == NSS_VXLAN_MAX_TUNNELS) {
+		spin_unlock_bh(&vxlan_ctx.tun_lock);
+		nss_vxlanmgr_warn("%px: Max number of vxlan interfaces supported is %d\n", dev, NSS_VXLAN_MAX_TUNNELS);
+		return NOTIFY_DONE;
+	}
+	spin_unlock_bh(&vxlan_ctx.tun_lock);
+
+	dev_hold(dev);
+	priv = netdev_priv(dev);
+	parse_flags = nss_vxlanmgr_tunnel_flags_parse(priv);
+
+	/*
+	 * Check if the tunnel is supported.
+	 */
+	if (!parse_flags) {
+		nss_vxlanmgr_warn("%px: Tunnel offload not supported\n", dev);
+		goto ctx_alloc_fail;
+	}
+
+	tun_ctx = kzalloc(sizeof(struct nss_vxlanmgr_tun_ctx), GFP_ATOMIC);
+	if (!tun_ctx) {
+		nss_vxlanmgr_warn("Failed to allocate memory for tun_ctx\n");
+		goto ctx_alloc_fail;
+	}
+	tun_ctx->dev = dev;
+	tun_ctx->vxlan_ctx = &vxlan_ctx;
+	INIT_LIST_HEAD(&tun_ctx->head);
+
+	inner_ifnum = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_INNER);
+	if (inner_ifnum < 0) {
+		nss_vxlanmgr_warn("%px: Inner interface allocation failed.\n", dev);
+		goto inner_alloc_fail;
+	}
+	tun_ctx->inner_ifnum = inner_ifnum;
+
+	outer_ifnum = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_OUTER);
+	if (outer_ifnum < 0) {
+		nss_vxlanmgr_warn("%px: Outer interface allocation failed.\n", dev);
+		goto outer_alloc_fail;
+	}
+	tun_ctx->outer_ifnum = outer_ifnum;
+
+	/*
+	 * Register vxlan tunnel with NSS
+	 */
+	nss_ctx = nss_vxlan_register_if(inner_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_INNER,
+					nss_vxlanmgr_tunnel_inner_recv,
+					nss_vxlanmgr_tunnel_inner_notifier, dev, 0);
+	if (!nss_ctx) {
+		nss_vxlanmgr_warn("%px: Failed to register inner iface\n", dev);
+		goto inner_reg_fail;
+	}
+
+	nss_ctx = nss_vxlan_register_if(outer_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_OUTER,
+					nss_vxlanmgr_tunnel_outer_recv,
+					nss_vxlanmgr_tunnel_outer_notifier, dev, 0);
+	if (!nss_ctx) {
+		nss_vxlanmgr_warn("%px: Failed to register outer iface\n", dev);
+		goto outer_reg_fail;
+	}
+
+	nss_vxlanmgr_trace("%px: Successfully registered inner and outer iface for VxLAN\n", dev);
+
+	memset(&vxlanmsg, 0, sizeof(struct nss_vxlan_msg));
+	vxlan_cfg = &vxlanmsg.msg.vxlan_create;
+
+	vxlan_cfg->vni = vxlan_get_vni(priv);
+	vxlan_cfg->tunnel_flags = parse_flags;
+	vxlan_cfg->src_port_min = priv->cfg.port_min;
+	vxlan_cfg->src_port_max = priv->cfg.port_max;
+	vxlan_cfg->dest_port = priv->cfg.dst_port;
+	vxlan_cfg->tos = priv->cfg.tos;
+	vxlan_cfg->ttl = (priv->cfg.ttl ? priv->cfg.ttl : IPDEFTTL);
+
+	vxlan_cfg->sibling_if_num = outer_ifnum;
+	ret = nss_vxlanmgr_tunnel_tx_msg_sync(vxlan_ctx.nss_ctx,
+						&vxlanmsg,
+						inner_ifnum,
+						NSS_VXLAN_MSG_TYPE_TUN_CONFIGURE,
+						sizeof(struct nss_vxlan_rule_msg));
+	if (ret != NSS_TX_SUCCESS) {
+		nss_vxlanmgr_warn("%px: Sending configuration to inner interface failed: %d\n", dev, ret);
+		goto config_fail;
+	}
+
+	vxlan_cfg->sibling_if_num = inner_ifnum;
+	ret = nss_vxlanmgr_tunnel_tx_msg_sync(vxlan_ctx.nss_ctx,
+						&vxlanmsg,
+						outer_ifnum,
+						NSS_VXLAN_MSG_TYPE_TUN_CONFIGURE,
+						sizeof(struct nss_vxlan_rule_msg));
+	if (ret != NSS_TX_SUCCESS) {
+		nss_vxlanmgr_warn("%px: Sending configuration to outer interface failed: %d\n", dev, ret);
+		goto config_fail;
+	}
+
+	if (!nss_vxlanmgr_tun_stats_dentry_create(tun_ctx)) {
+		nss_vxlanmgr_warn("%px: Tun stats dentry init failed\n", vxlan_ctx.nss_ctx);
+		goto config_fail;
+	}
+
+	if (!nss_vxlanmgr_tun_stats_init(tun_ctx)) {
+		nss_vxlanmgr_warn("%px: Tun stats init failed\n", vxlan_ctx.nss_ctx);
+		goto config_fail;
+	}
+
+	tun_ctx->vni = vxlan_cfg->vni;
+	tun_ctx->tunnel_flags = vxlan_cfg->tunnel_flags;
+	tun_ctx->flow_label = vxlan_cfg->flow_label;
+	tun_ctx->src_port_min = vxlan_cfg->src_port_min;
+	tun_ctx->src_port_max = vxlan_cfg->src_port_max;
+	tun_ctx->dest_port = vxlan_cfg->dest_port;
+	tun_ctx->tos = vxlan_cfg->tos;
+	tun_ctx->ttl = vxlan_cfg->ttl;
+
+	spin_lock_bh(&vxlan_ctx.tun_lock);
+	/*
+	 * Add tunnel to global list.
+	 */
+	list_add(&tun_ctx->head, &vxlan_ctx.list);
+
+	if (!vxlan_ctx.tun_count) {
+		/*
+		 * Register with fdb notifier chain
+		 * when first tunnel is created.
+		 */
+		vxlan_fdb_register_notify(&nss_vxlanmgr_tunnel_fdb_notifier);
+	}
+
+	/*
+	 * Increment vxlan tunnel interface count
+	 */
+	vxlan_ctx.tun_count++;
+	spin_unlock_bh(&vxlan_ctx.tun_lock);
+	nss_vxlanmgr_info("%px: VxLAN interface count is #%d\n", dev, vxlan_ctx.tun_count);
+
+	dev_put(dev);
+	return NOTIFY_DONE;
+
+config_fail:
+	nss_vxlan_unregister_if(outer_ifnum);
+outer_reg_fail:
+	nss_vxlan_unregister_if(inner_ifnum);
+inner_reg_fail:
+	ret = nss_dynamic_interface_dealloc_node(outer_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_OUTER);
+	if (ret != NSS_TX_SUCCESS)
+		nss_vxlanmgr_warn("%px: Outer interface dealloc failed: %d\n", dev, ret);
+outer_alloc_fail:
+	ret = nss_dynamic_interface_dealloc_node(inner_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_INNER);
+	if (ret != NSS_TX_SUCCESS)
+		nss_vxlanmgr_warn("%px: Inner interface dealloc failed: %d\n", dev, ret);
+inner_alloc_fail:
+	kfree(tun_ctx);
+ctx_alloc_fail:
+	dev_put(dev);
+	return NOTIFY_DONE;
+}
diff --git a/qca-nss-clients/wifi_meshmgr/Makefile b/qca-nss-clients/wifi_meshmgr/Makefile
new file mode 100644
index 0000000..d64f51e
--- /dev/null
+++ b/qca-nss-clients/wifi_meshmgr/Makefile
@@ -0,0 +1,8 @@
+ccflags-y += -I$(obj)/../exports -I$(obj)/.. -I$(obj)/nss_hal/include
+ccflags-y += -I$(obj)/../../qca-nss-drv/exports
+ccflags-y += -DNSS_CLIENT_BUILD_ID=\"Build\"
+ccflags-y += -DNSS_WIFI_MESHMGR_DEBUG_LEVEL=4
+ccflags-y += -Werror
+
+obj-m += qca-nss-wifi-meshmgr.o
+qca-nss-wifi-meshmgr-objs := nss_wifi_meshmgr.o
diff --git a/qca-nss-clients/wifi_meshmgr/nss_wifi_mesh_priv.h b/qca-nss-clients/wifi_meshmgr/nss_wifi_mesh_priv.h
new file mode 100644
index 0000000..66bf3dd
--- /dev/null
+++ b/qca-nss-clients/wifi_meshmgr/nss_wifi_mesh_priv.h
@@ -0,0 +1,83 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_wifi_mesh_priv.h
+ *	Mesh manager header
+ */
+#ifndef __NSS_WIFI_MESH_PRIV_H_
+#define __NSS_WIFI_MESH_PRIV_H_
+
+#define NSS_WIFI_MESH_MAX 16
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define nss_wifi_meshmgr_warn(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_wifi_meshmgr_info(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_wifi_meshmgr_trace(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#else /* CONFIG_DYNAMIC_DEBUG */
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_WIFI_MESHMGR_DEBUG_LEVEL < 2)
+#define nss_wifi_meshmgr_warn(s, ...)
+#else
+#define nss_wifi_meshmgr_warn(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_WIFI_MESHMGR_DEBUG_LEVEL < 3)
+#define nss_wifi_meshmgr_info(s, ...)
+#else
+#define nss_wifi_meshmgr_info(s, ...)   pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_WIFI_MESHMGR_DEBUG_LEVEL < 4)
+#define nss_wifi_meshmgr_trace(s, ...)
+#else
+#define nss_wifi_meshmgr_trace(s, ...)  pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+/*
+ * nss_wifi_meshmgr_mesh_ctx
+ *	Mesh context per interface.
+ */
+struct nss_wifi_meshmgr_mesh_ctx {
+	struct net_device *dev;			/* Netdevice pointer */
+	atomic_t ref;				/* Atomic reference count */
+	int32_t encap_ifnum;			/* Encap interface number */
+	int32_t decap_ifnum;			/* Decap interface number */
+	struct semaphore sem;			/* Semaphore for message synchronization */
+	struct completion complete;		/* Per context complete */
+	nss_tx_status_t response;		/* Response type */
+};
+
+/*
+ * nss_wifi_meshmgr_ctx
+ *	Global mesh context.
+ */
+struct nss_wifi_meshmgr_ctx {
+	struct nss_ctx_instance *nss_ctx;	/* Nss context for mesh */
+	uint32_t mesh_count;			/* Active mesh count */
+	spinlock_t ref_lock;			/* Spinlock */
+	struct nss_wifi_meshmgr_mesh_ctx *mesh_ctx[NSS_WIFI_MESH_MAX];
+						/* Mesh handle table */
+};
+#endif /* __NSS_WIFI_MESH_PRIV_H_ */
diff --git a/qca-nss-clients/wifi_meshmgr/nss_wifi_meshmgr.c b/qca-nss-clients/wifi_meshmgr/nss_wifi_meshmgr.c
new file mode 100644
index 0000000..c67cadf
--- /dev/null
+++ b/qca-nss-clients/wifi_meshmgr/nss_wifi_meshmgr.c
@@ -0,0 +1,2001 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_wifi_meshmgr.c
+ *	NSS to HLOS WiFi-Mesh manager
+ */
+
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/of.h>
+#include <nss_api_if.h>
+#include <nss_wifi_meshmgr.h>
+#include "nss_wifi_mesh_priv.h"
+
+/*
+ * WiFi-Mesh context
+ */
+static struct nss_wifi_meshmgr_ctx wmgr_ctx;
+
+/*
+ * nss_wifi_meshmgr_verify_if_num()
+ *	Verify interface number.
+ */
+static bool nss_wifi_meshmgr_verify_if_num(int32_t if_num, enum nss_dynamic_interface_type di_type)
+{
+	return (nss_is_dynamic_interface(if_num) &&
+		(nss_dynamic_interface_get_type(wmgr_ctx.nss_ctx, if_num) == di_type));
+}
+
+/*
+ * nss_wifi_meshmgr_tx_msg()
+ *	WiFi-Mesh message send API
+ */
+static nss_wifi_meshmgr_status_t nss_wifi_meshmgr_tx_msg(struct nss_wifi_mesh_msg *msg)
+{
+	return nss_wifi_mesh_tx_msg(wmgr_ctx.nss_ctx, msg);
+}
+
+/*
+ * nss_wifi_meshmgr_ctx_insert()
+ *	Insert the mesh context into global table
+ */
+static int32_t nss_wifi_meshmgr_ctx_insert(struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx)
+{
+	int32_t i, idx = -1;
+	struct net_device *dev;
+
+	assert_spin_locked(&wmgr_ctx.ref_lock);
+
+	/*
+	 * Check if the context already exist for the same netdev.
+	 */
+	for (i = 0; i < NSS_WIFI_MESH_MAX; i++) {
+		if (!wmgr_ctx.mesh_ctx[i]) {
+			idx = i;
+			continue;
+		}
+
+		dev = (wmgr_ctx.mesh_ctx[i])->dev;
+		if (dev == wmesh_ctx->dev) {
+			nss_wifi_meshmgr_warn("%px: The mesh context already exist for dev:%s",
+						&wmgr_ctx, wmesh_ctx->dev->name);
+			return -1;
+		}
+	}
+
+	if (idx == -1) {
+		return idx;
+	}
+
+	wmgr_ctx.mesh_ctx[idx] = wmesh_ctx;
+	return idx;
+}
+
+/*
+ * nss_wifi_meshmgr_ctx_remove()
+ *	Remove the mesh context from global table
+ */
+static void nss_wifi_meshmgr_ctx_remove(struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx)
+{
+	int32_t i;
+
+	assert_spin_locked(&wmgr_ctx.ref_lock);
+
+	for (i = 0; i < NSS_WIFI_MESH_MAX; i++) {
+		if (wmgr_ctx.mesh_ctx[i] != wmesh_ctx) {
+			continue;
+		}
+
+		wmgr_ctx.mesh_ctx[i] = NULL;
+		return;
+	}
+}
+
+/*
+ * nss_wifi_meshmgr_cleanup()
+ *	Clean up the mesh context.
+ */
+static void nss_wifi_meshmgr_cleanup(struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx)
+{
+	int32_t encap_ifnum, decap_ifnum;
+	nss_wifi_meshmgr_status_t nss_status;
+
+	nss_wifi_meshmgr_trace("%px: Mesh handle cleanup called for: %s\n", &wmgr_ctx, wmesh_ctx->dev->name);
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+	decap_ifnum = wmesh_ctx->decap_ifnum;
+
+	/*
+	 * Unregister and dealloc decap DI.
+	 */
+	nss_unregister_wifi_mesh_if(decap_ifnum);
+	nss_status = nss_dynamic_interface_dealloc_node(decap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Failed to dealloc decap: %d\n", &wmgr_ctx, nss_status);
+	}
+
+	/*
+	 * Unregister and dealloc encap DI.
+	 */
+	nss_unregister_wifi_mesh_if(encap_ifnum);
+	nss_status = nss_dynamic_interface_dealloc_node(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Failed to dealloc encap: %d\n", &wmgr_ctx, nss_status);
+	}
+
+	dev_put(wmesh_ctx->dev);
+	kfree(wmesh_ctx);
+}
+
+/*
+ * nss_wifi_meshmgr_ref_dec()
+ *	Find and decrement the reference counter.
+ */
+static void nss_wifi_meshmgr_ref_dec(struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx)
+{
+	if (atomic_dec_and_test(&wmesh_ctx->ref)) {
+		nss_wifi_meshmgr_cleanup(wmesh_ctx);
+	}
+}
+
+/*
+ * nss_wifi_meshmgr_find_and_ref_inc()
+ *	Find and inreae the reference counter.
+ */
+static struct nss_wifi_meshmgr_mesh_ctx *nss_wifi_meshmgr_find_and_ref_inc(nss_wifi_mesh_handle_t mesh_handle)
+{
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+
+	if ((mesh_handle < 0) || (mesh_handle >= NSS_WIFI_MESH_MAX)) {
+		nss_wifi_meshmgr_warn("%px: Invalid mesh handle: %d\n", &wmgr_ctx, mesh_handle);
+		return NULL;
+	}
+
+	spin_lock_bh(&wmgr_ctx.ref_lock);
+	wmesh_ctx = wmgr_ctx.mesh_ctx[mesh_handle];
+	if (wmesh_ctx && atomic_inc_and_test(&wmesh_ctx->ref)) {
+		BUG_ON(1);
+	}
+	spin_unlock_bh(&wmgr_ctx.ref_lock);
+	return wmesh_ctx;
+}
+
+/*
+ * nss_wifi_meshmgr_remap_error()
+ *	Remap the error code.
+ */
+static nss_wifi_meshmgr_status_t nss_wifi_meshmgr_remap_error(enum nss_wifi_mesh_error_types error)
+{
+	switch (error) {
+	case NSS_WIFI_MESH_ERROR_UNKNOWN_MSG:
+		return NSS_WIFI_MESHMGR_FAILURE_UNKNOWN_MSG;
+	case NSS_WIFI_MESH_ERROR_TTL_CONFIG:
+		return NSS_WIFI_MESHMGR_FAILURE_TTL_CONFIG;
+	case NSS_WIFI_MESH_ERROR_REFRESH_TIME_CONFIG:
+		return NSS_WIFI_MESHMGR_FAILURE_REFRESH_TIME_CONFIG;
+	case NSS_WIFI_MESH_ERROR_MPP_LEARNING_MODE_CONFIG:
+		return NSS_WIFI_MESHMGR_FAILURE_MPP_LEARNING_MODE_CONFIG;
+	case NSS_WIFI_MESH_ERROR_PATH_ADD_MAX_RADIO_CNT:
+		return NSS_WIFI_MESHMGR_FAILURE_PATH_ADD_MAX_RADIO_CNT;
+	case NSS_WIFI_MESH_ERROR_PATH_ADD_INVALID_INTERFACE_NUM:
+		return NSS_WIFI_MESHMGR_FAILURE_PATH_ADD_INVALID_INTERFACE_NUM;
+	case NSS_WIFI_MESH_ERROR_PATH_ADD_INTERFACE_NUM_NOT_FOUND:
+		return NSS_WIFI_MESHMGR_FAILURE_PATH_ADD_INTERFACE_NUM_NOT_FOUND;
+	case NSS_WIFI_MESH_ERROR_PATH_TABLE_FULL:
+		return NSS_WIFI_MESHMGR_FAILURE_PATH_TABLE_FULL;
+	case NSS_WIFI_MESH_ERROR_PATH_ALLOC_FAIL:
+		return NSS_WIFI_MESHMGR_FAILURE_PATH_ALLOC_FAIL;
+	case NSS_WIFI_MESH_ERROR_PATH_INSERT_FAIL:
+		return NSS_WIFI_MESHMGR_FAILURE_PATH_INSERT_FAIL;
+	case NSS_WIFI_MESH_ERROR_PATH_NOT_FOUND:
+		return NSS_WIFI_MESHMGR_FAILURE_PATH_NOT_FOUND;
+	case NSS_WIFI_MESH_ERROR_PATH_UNHASHED:
+		return NSS_WIFI_MESHMGR_FAILURE_PATH_UNHASHED;
+	case NSS_WIFI_MESH_ERROR_PATH_DELETE_FAIL:
+		return NSS_WIFI_MESHMGR_FAILURE_PATH_DELETE_FAIL;
+	case NSS_WIFI_MESH_ERROR_PROXY_PATH_NOT_FOUND:
+		return NSS_WIFI_MESHMGR_FAILURE_PROXY_PATH_NOT_FOUND;
+	case NSS_WIFI_MESH_ERROR_PROXY_PATH_UNHASHED:
+		return NSS_WIFI_MESHMGR_FAILURE_PROXY_PATH_UNHASHED;
+	case NSS_WIFI_MESH_ERROR_PROXY_PATH_DELETE_FAIL:
+		return NSS_WIFI_MESHMGR_FAILURE_PROXY_PATH_DELETE_FAIL;
+	case NSS_WIFI_MESH_ERROR_PROXY_PATH_EXISTS:
+		return NSS_WIFI_MESHMGR_FAILURE_PROXY_PATH_EXISTS;
+	case NSS_WIFI_MESH_ERROR_PROXY_PATH_ALLOC_FAIL:
+		return NSS_WIFI_MESHMGR_FAILURE_PROXY_PATH_ALLOC_FAIL;
+	case NSS_WIFI_MESH_ERROR_PROXY_PATH_INSERT_FAIL:
+		return NSS_WIFI_MESHMGR_FAILURE_PROXY_PATH_INSERT_FAIL;
+	case NSS_WIFI_MESH_ERROR_PROXY_PATH_TABLE_FULL:
+		return NSS_WIFI_MESHMGR_FAILURE_PROXY_PATH_TABLE_FULL;
+	case NSS_WIFI_MESH_ERROR_PB_ALLOC_FAIL:
+		return NSS_WIFI_MESHMGR_FAILURE_PB_ALLOC_FAIL;
+	case NSS_WIFI_MESH_ERROR_ENQUEUE_TO_HOST_FAIL:
+		return NSS_WIFI_MESHMGR_FAILURE_ENQUEUE_TO_HOST_FAIL;
+	case NSS_WIFI_MESH_ERROR_ENABLE_INTERFACE_FAIL:
+		return NSS_WIFI_MESHMGR_FAILURE_ENABLE_INTERFACE_FAIL;
+	case NSS_WIFI_MESH_ERROR_DISABLE_INTERFACE_FAIL:
+		return NSS_WIFI_MESHMGR_FAILURE_DISABLE_INTERFACE_FAIL;
+	case NSS_WIFI_MESH_ERROR_INVALID_EXCEPTION_NUM:
+		return NSS_WIFI_MESHMGR_FAILURE_INVALID_EXCEPTION_NUM;
+	case NSS_WIFI_MESH_ERROR_ONESHOT_ALREADY_ATTACHED:
+		return NSS_WIFI_MESHMGR_FAILURE_ONESHOT_ALREADY_ATTACHED;
+	default:
+		return NSS_WIFI_MESHMGR_FAILURE;
+	};
+}
+
+/*
+ * nss_wifi_meshmgr_tx_msg_cb()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_wifi_meshmgr_tx_msg_cb(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx = (struct nss_wifi_meshmgr_mesh_ctx *)app_data;
+	uint32_t error_code = ncm->error;
+
+	/*
+	 * FIXME: The wmesh_ctx can be invalid if the memory goes away with the caller being timedout.
+	 */
+	wmesh_ctx->response = NSS_WIFI_MESHMGR_SUCCESS;
+	if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+		nss_wifi_meshmgr_warn("%px: WiFi-Mesh error response %d error_code: %u\n", &wmgr_ctx, ncm->response, error_code);
+		wmesh_ctx->response = nss_wifi_meshmgr_remap_error(error_code);
+	}
+
+	complete(&wmesh_ctx->complete);
+}
+
+ /*
+ * nss_wifi_meshmgr_tx_msg_sync()
+ *     Transmit a WiFi mesh message to NSS firmware synchronously.
+ */
+static nss_wifi_meshmgr_status_t nss_wifi_meshmgr_tx_msg_sync(struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx, struct nss_wifi_mesh_msg *wmesh_msg)
+{
+	nss_wifi_meshmgr_status_t status;
+	int ret;
+
+	down(&wmesh_ctx->sem);
+	status = nss_wifi_meshmgr_tx_msg(wmesh_msg);
+	if (status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh tx sync msg failed: %d\n", &wmgr_ctx, status);
+		up(&wmesh_ctx->sem);
+		return status;
+	}
+
+	/*
+	 * Wait for the acknowledgement.
+	 */
+	ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT));
+	if (!ret) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx);
+		wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT;
+	}
+
+	status = wmesh_ctx->response;
+	up(&wmesh_ctx->sem);
+	return status;
+}
+
+/*
+ * nss_wifi_meshmgr_tx_buf()
+ *	Send packets to mesh I/F
+ */
+nss_wifi_meshmgr_status_t nss_wifi_meshmgr_tx_buf(nss_wifi_mesh_handle_t mesh_handle, struct sk_buff *os_buf)
+{
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	int32_t encap_ifnum;
+	nss_wifi_meshmgr_status_t nss_status;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+
+	/*
+	 * Verify the encap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, encap_ifnum);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	nss_status = nss_wifi_mesh_tx_buf(wmgr_ctx.nss_ctx, os_buf, encap_ifnum);
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_tx_buf);
+
+/*
+ * nss_wifi_meshmgr_if_down()
+ *	Make the NSS interface down synchronously.
+ */
+nss_wifi_meshmgr_status_t nss_wifi_meshmgr_if_down(nss_wifi_mesh_handle_t mesh_handle)
+{
+	struct nss_wifi_mesh_msg wmesh_msg;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	nss_wifi_meshmgr_status_t nss_status;
+	int32_t encap_ifnum, decap_ifnum;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+	decap_ifnum = wmesh_ctx->decap_ifnum;
+
+	/*
+	 * Verify the I/F encap and decap number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER) ||
+		nss_wifi_meshmgr_verify_if_num(decap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER))) {
+		nss_wifi_meshmgr_warn("%px: Interface verification failed\n", &wmgr_ctx);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	/*
+	 * Initialize the encap I/F down message.
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nss_wifi_mesh_msg_init(&wmesh_msg, encap_ifnum, NSS_IF_CLOSE,
+			sizeof(struct nss_if_close), nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+
+	/*
+	 * Send the I/F down message to the encap I/F.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg_sync(wmesh_ctx, &wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh link encap I/F down failed: %d.\n", &wmgr_ctx, nss_status);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return nss_status;
+	}
+
+	/*
+	 * Initialize the decap I/F down message.
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nss_wifi_mesh_msg_init(&wmesh_msg, decap_ifnum, NSS_IF_CLOSE,
+			sizeof(struct nss_if_close), nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+
+	/*
+	 * Send the I/F down message to the decap I/F.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg_sync(wmesh_ctx, &wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh link decap I/F down failed: %d.\n", &wmgr_ctx, nss_status);
+	}
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_if_down);
+
+/*
+ * nss_wifi_meshmgr_if_up()
+ *	Make the NSS interface up synchronously.
+ */
+nss_wifi_meshmgr_status_t nss_wifi_meshmgr_if_up(nss_wifi_mesh_handle_t mesh_handle)
+{
+	struct nss_wifi_mesh_msg wmesh_msg;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	nss_wifi_meshmgr_status_t nss_status;
+	int32_t encap_ifnum, decap_ifnum;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+	decap_ifnum = wmesh_ctx->decap_ifnum;
+
+	/*
+	 * Verify the I/F encap and decap number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER) ||
+		nss_wifi_meshmgr_verify_if_num(decap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER))) {
+		nss_wifi_meshmgr_warn("%px: Interface verification failed\n", &wmgr_ctx);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	/*
+	 * Initialize the encap I/F up message.
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nss_wifi_mesh_msg_init(&wmesh_msg, encap_ifnum, NSS_IF_OPEN,
+			sizeof(struct nss_if_open), nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+
+	/*
+	 * Send the I/F up message to the encap I/F.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg_sync(wmesh_ctx, &wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh link encap I/F up failed: %d.\n", &wmgr_ctx, nss_status);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return nss_status;
+	}
+
+	/*
+	 * Initialize the I/F decap up message.
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nss_wifi_mesh_msg_init(&wmesh_msg, decap_ifnum, NSS_IF_OPEN,
+			sizeof(struct nss_if_open), nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+
+	/*
+	 * Send the I/F up message to the decap interface.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg_sync(wmesh_ctx, &wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh link decap I/F up failed: %d.\n", &wmgr_ctx, nss_status);
+	}
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_if_up);
+
+/*
+ * nss_wifi_meshmgr_dump_mesh_path()
+ *	Dump mesh path table request asynchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_dump_mesh_path(nss_wifi_mesh_handle_t mesh_handle, nss_wifi_mesh_msg_callback_t msg_cb, void *app_data)
+{
+	struct nss_wifi_mesh_msg wmesh_msg;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	nss_wifi_meshmgr_status_t nss_status;
+	int32_t encap_ifnum;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+
+	/*
+	 * Verify the encap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, encap_ifnum);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	/*
+	 * Initialize the path dump request message.
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nss_wifi_mesh_msg_init(&wmesh_msg, encap_ifnum, NSS_WIFI_MESH_MSG_PATH_TABLE_DUMP,
+			sizeof(struct nss_wifi_mesh_path_table_dump), msg_cb, app_data);
+
+	/*
+	 * Send the path dump request mesage to the NSS asynchronously.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg(&wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh dump mesh path failed: %d.\n", &wmgr_ctx, nss_status);
+	}
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_dump_mesh_path);
+
+/*
+ * nss_wifi_meshmgr_dump_mesh_path_sync()
+ *	Dump mesh path table request synchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_dump_mesh_path_sync(nss_wifi_mesh_handle_t mesh_handle)
+{
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	nss_wifi_meshmgr_status_t nss_status;
+	int32_t ret;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	/*
+	 * Send the path dump request mesage to the NSS synchronously.
+	 */
+	down(&wmesh_ctx->sem);
+	nss_status = nss_wifi_meshmgr_dump_mesh_path(mesh_handle, nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh path dump msg failed: %d.\n", &wmgr_ctx, nss_status);
+		up(&wmesh_ctx->sem);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return nss_status;
+	}
+
+	/*
+	 * Wait for the acknowledgement
+	 */
+	ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT));
+	if (!ret) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx);
+		wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT;
+	}
+
+	nss_status = wmesh_ctx->response;
+	up(&wmesh_ctx->sem);
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_dump_mesh_path_sync);
+
+/*
+ * nss_wifi_meshmgr_dump_mesh_proxy_path()
+ *	Dump mesh proxy path table request asynchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_dump_mesh_proxy_path(nss_wifi_mesh_handle_t mesh_handle, nss_wifi_mesh_msg_callback_t msg_cb, void *app_data)
+{
+	struct nss_wifi_mesh_msg wmesh_msg;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	nss_wifi_meshmgr_status_t nss_status;
+	int32_t encap_ifnum;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+
+	/*
+	 * Verify the encap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, encap_ifnum);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	/*
+	 * Initialize the proxy path table message.
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nss_wifi_mesh_msg_init(&wmesh_msg, encap_ifnum, NSS_WIFI_MESH_MSG_PROXY_PATH_TABLE_DUMP,
+			sizeof(struct nss_wifi_mesh_proxy_path_table_dump), msg_cb, app_data);
+
+	/*
+	 * Send the proxy path dump message to NSS asynchronously.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg(&wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh link vap proxy path dump failed: %d.\n", &wmgr_ctx, nss_status);
+	}
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_dump_mesh_proxy_path);
+
+/*
+ * nss_wifi_meshmgr_dump_mesh_path_sync()
+ *	Dump mesh proxy path table request synchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_dump_mesh_proxy_path_sync(nss_wifi_mesh_handle_t mesh_handle)
+{
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	nss_wifi_meshmgr_status_t nss_status;
+	int32_t ret;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	/*
+	 * Send the path dump request to the NSS synchronously.
+	 */
+	down(&wmesh_ctx->sem);
+	nss_status = nss_wifi_meshmgr_dump_mesh_proxy_path(mesh_handle, nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh proxy path dump msg failed: %d.\n", &wmgr_ctx, nss_status);
+		up(&wmesh_ctx->sem);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return nss_status;
+	}
+
+	/*
+	 * Wait for the acknowledgement
+	 */
+	ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT));
+	if (!ret) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx);
+		wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT;
+	}
+
+	nss_status = wmesh_ctx->response;
+	up(&wmesh_ctx->sem);
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_dump_mesh_proxy_path_sync);
+
+/*
+ * nss_wifi_meshmgr_assoc_link_vap()
+ *	Associate the link interface to the mesh I/F asynchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_assoc_link_vap(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_assoc_link_vap *wmalv,
+				nss_wifi_mesh_msg_callback_t msg_cb, void *app_data)
+{
+	struct nss_wifi_vdev_msg *wifivdevmsg;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	struct nss_wifi_vdev_set_next_hop_msg *next_hop_msg = NULL;
+	int32_t decap_ifnum, link_ifnum;
+	nss_wifi_meshmgr_status_t nss_status;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	wifivdevmsg = kzalloc(sizeof(*wifivdevmsg), GFP_ATOMIC);
+	if (!wifivdevmsg) {
+		nss_wifi_meshmgr_warn("%px: Failed to allocate message memmory", &wmgr_ctx);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	decap_ifnum = wmesh_ctx->decap_ifnum;
+
+	/*
+	 * Verify the decap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(decap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, decap_ifnum);
+		kfree(wifivdevmsg);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+
+	link_ifnum = wmalv->link_vap_id;
+
+	/*
+	 * Verify the link VAP I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(link_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_VAP))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, link_ifnum);
+		kfree(wifivdevmsg);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+
+	next_hop_msg = &wifivdevmsg->msg.next_hop;
+	next_hop_msg->ifnumber = decap_ifnum;
+	nss_cmn_msg_init(&wifivdevmsg->cm, link_ifnum, NSS_WIFI_VDEV_SET_NEXT_HOP, sizeof(*next_hop_msg),
+				msg_cb, app_data);
+
+	/*
+	 * Send the link vap mesage to the NSS synchronously.
+	 */
+	nss_status = nss_wifi_vdev_tx_msg(wmgr_ctx.nss_ctx, wifivdevmsg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh link vap association failed: %d.\n", &wmgr_ctx, nss_status);
+	}
+
+	kfree(wifivdevmsg);
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_assoc_link_vap);
+
+/*
+ * nss_wifi_meshmgr_assoc_link_vap_sync()
+ *	Associate the link VAP to the mesh I/F synchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_assoc_link_vap_sync(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_assoc_link_vap *wmalv)
+{
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	nss_wifi_meshmgr_status_t nss_status;
+	int32_t ret;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	/*
+	 * Send the link vap mesage to the NSS synchronously.
+	 */
+	down(&wmesh_ctx->sem);
+	nss_status = nss_wifi_meshmgr_assoc_link_vap(mesh_handle, wmalv, nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh link vap association failed: %d.\n", &wmgr_ctx, nss_status);
+		up(&wmesh_ctx->sem);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return nss_status;
+	}
+
+	/*
+	 * Wait for the acknowledgement
+	 */
+	ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT));
+	if (!ret) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx);
+		wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT;
+	}
+
+	nss_status = wmesh_ctx->response;
+	up(&wmesh_ctx->sem);
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_assoc_link_vap_sync);
+
+/*
+ * nss_wifi_meshmgr_mesh_config_update()
+ *	Update mesh configuration message asynchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_config_update(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_config_msg *wmcum,
+				    nss_wifi_mesh_msg_callback_t msg_cb, void *app_data)
+{
+	struct nss_wifi_mesh_msg wmesh_msg;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	struct nss_wifi_mesh_config_msg *nwmcum;
+	int32_t encap_ifnum, decap_ifnum;
+	nss_wifi_meshmgr_status_t nss_status;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+	decap_ifnum = wmesh_ctx->decap_ifnum;
+
+	/*
+	 * Verify the encap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER))) {
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, encap_ifnum);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	/*
+	 * Verify the decap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(decap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER))) {
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, decap_ifnum);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	/*
+	 * Initialize the mesh configuration messsage.
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nwmcum = &wmesh_msg.msg.mesh_config;
+	memcpy(nwmcum, wmcum, sizeof(*nwmcum));
+	nss_wifi_mesh_msg_init(&wmesh_msg, encap_ifnum, NSS_WIFI_MESH_MSG_INTERFACE_CONFIGURE,
+			sizeof(*nwmcum), msg_cb, app_data);
+
+	/*
+	 * Send the configuration message to encap I/F.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg(&wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh configuration message failed: %d.\n", &wmgr_ctx, nss_status);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return nss_status;
+	}
+
+	/*
+	 * Initialize the mesh configuration messsage.
+	 */
+	nss_wifi_mesh_msg_init(&wmesh_msg, decap_ifnum, NSS_WIFI_MESH_MSG_INTERFACE_CONFIGURE,
+			sizeof(*nwmcum), msg_cb, app_data);
+
+	/*
+	 * Send the configuration message decap I/F.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg(&wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh configuration message failed: %d.\n", &wmgr_ctx, nss_status);
+	}
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_config_update);
+
+/*
+ * nss_wifi_meshmgr_mesh_config_update_sync()
+ *	Update mesh configuration message synchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_config_update_sync(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_config_msg *wmcum)
+{
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	nss_wifi_meshmgr_status_t nss_status;
+	int32_t ret;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	/*
+	 * Send the message to NSS synchronously.
+	 */
+	down(&wmesh_ctx->sem);
+	nss_status = nss_wifi_meshmgr_mesh_config_update(mesh_handle, wmcum, nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh proxy path update failed: %d.\n", &wmgr_ctx, nss_status);
+		up(&wmesh_ctx->sem);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return nss_status;
+	}
+
+	/*
+	 * Wait for the acknowledgement
+	 */
+	ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT));
+	if (!ret) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx);
+		wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT;
+	}
+
+	nss_status = wmesh_ctx->response;
+	up(&wmesh_ctx->sem);
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_config_update_sync);
+
+/*
+ * nss_wifi_meshmgr_mesh_proxy_path_delete()
+ *	Delete the mesh proxy path asynchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_proxy_path_delete(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_proxy_path_del_msg *wmppdm,
+					nss_wifi_mesh_msg_callback_t msg_cb, void *app_data)
+{
+	struct nss_wifi_mesh_msg wmesh_msg;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	struct nss_wifi_mesh_proxy_path_del_msg *nwmppdm;
+	int32_t encap_ifnum;
+	nss_wifi_meshmgr_status_t nss_status;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+
+	/*
+	 * Verify the encap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, encap_ifnum);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	/*
+	 * Initialize the message.
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nwmppdm = &wmesh_msg.msg.proxy_del_msg;
+	memcpy(nwmppdm, wmppdm, sizeof(*nwmppdm));
+	nss_wifi_mesh_msg_init(&wmesh_msg, encap_ifnum, NSS_WIFI_MESH_MSG_PROXY_PATH_DELETE,
+			sizeof(*nwmppdm), msg_cb, app_data);
+
+	/*
+	 * Send the message to NSS asynchronously.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg(&wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh proxy path delete failed: %d.\n", &wmgr_ctx, nss_status);
+	}
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_proxy_path_delete);
+
+/*
+ * nss_wifi_meshmgr_mesh_proxy_path_delete_sync()
+ *	Delete the mesh proxy path synchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_proxy_path_delete_sync(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_proxy_path_del_msg *wmppdm)
+{
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	nss_wifi_meshmgr_status_t nss_status;
+	int32_t ret;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	/*
+	 * Send the message to NSS synchronously.
+	 */
+	down(&wmesh_ctx->sem);
+	nss_status = nss_wifi_meshmgr_mesh_proxy_path_delete(mesh_handle, wmppdm, nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh proxy path delete failed: %d.\n", &wmgr_ctx, nss_status);
+		up(&wmesh_ctx->sem);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return nss_status;
+	}
+
+	/*
+	 * Wait for the acknowledgement
+	 */
+	ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT));
+	if (!ret) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx);
+		wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT;
+	}
+
+	nss_status = wmesh_ctx->response;
+	up(&wmesh_ctx->sem);
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_proxy_path_delete_sync);
+
+/*
+ * nss_wifi_meshmgr_mesh_proxy_path_update()
+ *	Mesh prpxy path update message asynchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_proxy_path_update(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_proxy_path_update_msg *wmppum,
+					nss_wifi_mesh_msg_callback_t msg_cb, void *app_data)
+{
+	struct nss_wifi_mesh_msg wmesh_msg;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	struct nss_wifi_mesh_proxy_path_update_msg *nwmppum;
+	int32_t encap_ifnum;
+	nss_wifi_meshmgr_status_t nss_status;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+
+	/*
+	 * Verify the encap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, encap_ifnum);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	/*
+	 * Initialize the message.
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nwmppum = &wmesh_msg.msg.proxy_update_msg;
+	memcpy(nwmppum, wmppum, sizeof(*nwmppum));
+	nss_wifi_mesh_msg_init(&wmesh_msg, encap_ifnum, NSS_WIFI_MESH_MSG_PROXY_PATH_UPDATE,
+			sizeof(*nwmppum), msg_cb, app_data);
+
+	/*
+	 * Send the message to NSS asynchronously
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg(&wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh proxy path update failed: %d.\n", &wmgr_ctx, nss_status);
+	}
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_proxy_path_update);
+
+/*
+ * nss_wifi_meshmgr_mesh_proxy_path_update_sync()
+ *	Send proxy update message synchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_proxy_path_update_sync(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_proxy_path_update_msg *wmppum)
+{
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	nss_wifi_meshmgr_status_t nss_status;
+	int32_t ret;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	/*
+	 * Send the message to NSS synchronously.
+	 */
+	down(&wmesh_ctx->sem);
+	nss_status = nss_wifi_meshmgr_mesh_proxy_path_update(mesh_handle, wmppum, nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh proxy path update failed: %d.\n", &wmgr_ctx, nss_status);
+		up(&wmesh_ctx->sem);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return nss_status;
+	}
+
+	/*
+	 * Wait for the acknowledgement
+	 */
+	ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT));
+	if (!ret) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx);
+		wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT;
+	}
+
+	nss_status = wmesh_ctx->response;
+	up(&wmesh_ctx->sem);
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_proxy_path_update_sync);
+
+/*
+ * nss_wifi_meshmgr_mesh_proxy_path_add()
+ *	Send mesh proxy add message asynchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_proxy_path_add(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_proxy_path_add_msg *wmppam,
+				     nss_wifi_mesh_msg_callback_t msg_cb, void *app_data)
+{
+	struct nss_wifi_mesh_msg wmesh_msg;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	struct nss_wifi_mesh_proxy_path_add_msg *nwmppam;
+	int32_t encap_ifnum;
+	nss_wifi_meshmgr_status_t nss_status;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+
+	/*
+	 * Verify the encap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, encap_ifnum);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	/*
+	 * Initialize the message
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nwmppam = &wmesh_msg.msg.proxy_add_msg;
+	memcpy(nwmppam, wmppam, sizeof(*nwmppam));
+	nss_wifi_mesh_msg_init(&wmesh_msg, encap_ifnum, NSS_WIFI_MESH_MSG_PROXY_PATH_ADD,
+			sizeof(*nwmppam), msg_cb, app_data);
+
+	/*
+	 * Send the message to NSS asynchronously.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg(&wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh proxy path add  failed: %d.\n", &wmgr_ctx, nss_status);
+	}
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_proxy_path_add);
+
+/*
+ * nss_wifi_meshmgr_mesh_proxy_path_add_sync()
+ *	Send mesh proxy add message synchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_proxy_path_add_sync(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_proxy_path_add_msg *wmppam)
+{
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	int32_t ret;
+	nss_wifi_meshmgr_status_t nss_status;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	/*
+	 * Send the message to NSS synchronously.
+	 */
+	down(&wmesh_ctx->sem);
+	nss_status = nss_wifi_meshmgr_mesh_proxy_path_add(mesh_handle, wmppam, nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh proxy path add failed: %d.\n", &wmgr_ctx, nss_status);
+		up(&wmesh_ctx->sem);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return nss_status;
+	}
+
+	/*
+	 * Wait for the acknowledgement
+	 */
+	ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT));
+	if (!ret) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx);
+		wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT;
+	}
+
+	nss_status = wmesh_ctx->response;
+	up(&wmesh_ctx->sem);
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_proxy_path_add_sync);
+
+/*
+ * nss_wifi_meshmgr_mesh_path_delete()
+ *	Send the mesh path delete message asynchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_path_delete(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_mpath_del_msg *wmpdm,
+				  nss_wifi_mesh_msg_callback_t msg_cb, void *app_data)
+{
+	struct nss_wifi_mesh_msg wmesh_msg;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	struct nss_wifi_mesh_mpath_del_msg *nwmpdm;
+	int32_t encap_ifnum;
+	nss_wifi_meshmgr_status_t nss_status;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+
+	/*
+	 * Verify the encap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, encap_ifnum);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	/*
+	 * Initialize the message.
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nwmpdm = &wmesh_msg.msg.mpath_del;
+	memcpy(nwmpdm, wmpdm, sizeof(*nwmpdm));
+	nss_wifi_mesh_msg_init(&wmesh_msg, encap_ifnum, NSS_WIFI_MESH_MSG_MPATH_DELETE,
+			sizeof(*nwmpdm), msg_cb, app_data);
+
+	/*
+	 * Send the message to NSS asynchronously.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg(&wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh path delete failed: %d.\n", &wmgr_ctx, nss_status);
+	}
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_path_delete);
+
+/*
+ * nss_wifi_meshmgr_mesh_path_delete_sync()
+ *	Send the mesh path delete message synchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_path_delete_sync(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_mpath_del_msg *wmpdm)
+{
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	int32_t ret;
+	nss_wifi_meshmgr_status_t nss_status;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	/*
+	 * Send the message to NSS synchronously.
+	 */
+	down(&wmesh_ctx->sem);
+	nss_status = nss_wifi_meshmgr_mesh_path_delete(mesh_handle, wmpdm, nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh path delete failed: %d.\n", &wmgr_ctx, nss_status);
+		up(&wmesh_ctx->sem);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return nss_status;
+	}
+
+	/*
+	 * Wait for the acknowledgement
+	 */
+	ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT));
+	if (!ret) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx);
+		wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT;
+	}
+
+	nss_status = wmesh_ctx->response;
+	up(&wmesh_ctx->sem);
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_path_delete_sync);
+
+/*
+ * nss_wifi_meshmgr_mesh_path_add()
+ *	Mesh path add message asynchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_path_add(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_mpath_add_msg *wmpam,
+			       nss_wifi_mesh_msg_callback_t msg_cb, void *app_data)
+{
+	struct nss_wifi_mesh_msg wmesh_msg;
+	struct nss_wifi_mesh_mpath_add_msg *nwmpam;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	int32_t encap_ifnum;
+	nss_wifi_meshmgr_status_t nss_status;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+
+	/*
+	 * Verify the encap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, encap_ifnum);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	/*
+	 * Initialize the message.
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nwmpam = &wmesh_msg.msg.mpath_add;
+	memcpy(nwmpam, wmpam, sizeof(*nwmpam));
+	nss_wifi_mesh_msg_init(&wmesh_msg, encap_ifnum, NSS_WIFI_MESH_MSG_MPATH_ADD,
+			sizeof(*nwmpam), msg_cb, app_data);
+
+	/*
+	 * Send the message to NSS asynchronously.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg(&wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh path addition failed: %d.\n", &wmgr_ctx, nss_status);
+	}
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_path_add);
+
+/*
+ * nss_wifi_meshmgr_mesh_path_add_sync()
+ *	Mesh path add message synchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_path_add_sync(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_mpath_add_msg *wmpam)
+{
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	int32_t ret;
+	nss_wifi_meshmgr_status_t nss_status;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	/*
+	 * Send the message to NSS synchronously.
+	 */
+	down(&wmesh_ctx->sem);
+	nss_status = nss_wifi_meshmgr_mesh_path_add(mesh_handle, wmpam, nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh path addition failed: %d.\n", &wmgr_ctx, nss_status);
+		up(&wmesh_ctx->sem);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return nss_status;
+	}
+
+	/*
+	 * Wait for the acknowledgement
+	 */
+	ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT));
+	if (!ret) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx);
+		wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT;
+	}
+
+	nss_status = wmesh_ctx->response;
+	up(&wmesh_ctx->sem);
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_path_add_sync);
+
+/*
+ * nss_wifi_meshmgr_mpath_update()
+ *	Send mesh path update message asynchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_path_update(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_mpath_update_msg *wmpum,
+				  nss_wifi_mesh_msg_callback_t msg_cb, void *app_data)
+{
+	struct nss_wifi_mesh_msg wmesh_msg;
+	struct nss_wifi_mesh_mpath_update_msg *nwmpum;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	int32_t encap_ifnum;
+	nss_wifi_meshmgr_status_t nss_status;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+
+	/*
+	 * Verify the encap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, encap_ifnum);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	/*
+	 * Initialize the mesh path update message.
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nwmpum = &wmesh_msg.msg.mpath_update;
+	memcpy(nwmpum, wmpum, sizeof(*nwmpum));
+	nss_wifi_mesh_msg_init(&wmesh_msg, encap_ifnum, NSS_WIFI_MESH_MSG_MPATH_UPDATE,
+			sizeof(*nwmpum), msg_cb, app_data);
+
+	/*
+	 * Send the message to NSS asynchronously.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg(&wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh MPath update failed: %d.\n", &wmgr_ctx, nss_status);
+	}
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_path_update);
+
+/*
+ * nss_wifi_meshmgr_mpath_update_sync()
+ *	Send mesh path update message sychronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_path_update_sync(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_mpath_update_msg *wmpum)
+{
+	nss_wifi_meshmgr_status_t nss_status;
+	int32_t ret;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	/*
+	 * Send the message to NSS synchronously.
+	 */
+	down(&wmesh_ctx->sem);
+	nss_status = nss_wifi_meshmgr_mesh_path_update(mesh_handle, wmpum, nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh MPath update failed: %d.\n", &wmgr_ctx, nss_status);
+		up(&wmesh_ctx->sem);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return nss_status;
+	}
+
+	/*
+	 * Wait for the acknowledgement
+	 */
+	ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT));
+	if (!ret) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx);
+		wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT;
+	}
+
+	nss_status = wmesh_ctx->response;
+	up(&wmesh_ctx->sem);
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_path_update_sync);
+
+/*
+ * nss_wifi_meshmgr_mesh_path_exception()
+ *	Mesh path exception msg asynchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_path_exception(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_exception_flag_msg *wmefm,
+			       nss_wifi_mesh_msg_callback_t msg_cb, void *app_data)
+{
+	struct nss_wifi_mesh_msg wmesh_msg;
+	struct nss_wifi_mesh_exception_flag_msg *nwmefm;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	int32_t encap_ifnum;
+	nss_wifi_meshmgr_status_t nss_status;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+
+	/*
+	 * Verify the encap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, encap_ifnum);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	/*
+	 * Initialize the message.
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nwmefm = &wmesh_msg.msg.exception_msg;
+	memcpy(nwmefm, wmefm, sizeof(*nwmefm));
+	nss_wifi_mesh_msg_init(&wmesh_msg, encap_ifnum, NSS_WIFI_MESH_MSG_EXCEPTION_FLAG,
+			sizeof(*nwmefm), msg_cb, app_data);
+
+	/*
+	 * Send the message to NSS asynchronously.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg(&wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh path exception message failed: %d.\n", &wmgr_ctx, nss_status);
+	}
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_path_exception);
+
+/*
+ * nss_wifi_meshmgr_mesh_path_exception_sync()
+ *	Send mesh path exception message sychronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_mesh_path_exception_sync(nss_wifi_mesh_handle_t mesh_handle,struct nss_wifi_mesh_exception_flag_msg *wmefm)
+{
+	nss_wifi_meshmgr_status_t nss_status;
+	int32_t ret;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	/*
+	 * Send the message to NSS synchronously.
+	 */
+	down(&wmesh_ctx->sem);
+	nss_status = nss_wifi_meshmgr_mesh_path_exception(mesh_handle, wmefm, nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh path exception message failed: %d.\n", &wmgr_ctx, nss_status);
+		up(&wmesh_ctx->sem);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return nss_status;
+	}
+
+	/*
+	 * Wait for the acknowledgement
+	 */
+	ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT));
+	if (!ret) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx);
+		wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT;
+	}
+
+	nss_status = wmesh_ctx->response;
+	up(&wmesh_ctx->sem);
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_mesh_path_exception_sync);
+
+/*
+ * nss_wifi_meshmgr_config_mesh_exception()
+ *	Configure mesh exception asynchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_config_mesh_exception(nss_wifi_mesh_handle_t mesh_handle, struct nss_wifi_mesh_rate_limit_config *wmrlc,
+			       nss_wifi_mesh_msg_callback_t msg_cb, void *app_data)
+{
+	struct nss_wifi_mesh_msg wmesh_msg;
+	struct nss_wifi_mesh_rate_limit_config *nwmrlc;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+	int32_t encap_ifnum, decap_ifnum, ifnum;
+	nss_wifi_meshmgr_status_t nss_status;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+
+	/*
+	 * Verify the encap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, encap_ifnum);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	decap_ifnum = wmesh_ctx->decap_ifnum;
+
+	/*
+	 * Verify the decap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(decap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, decap_ifnum);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	switch(wmrlc->exception_num) {
+	case NSS_WIFI_MESH_DS_MESH_PATH_NOT_FOUND:
+		ifnum = encap_ifnum;
+		break;
+
+	case NSS_WIFI_MESH_US_MESH_PROXY_NOT_FOUND:
+		ifnum = decap_ifnum;
+		break;
+
+	case NSS_WIFI_MESH_US_MESH_PATH_NOT_FOUND:
+		ifnum = decap_ifnum;
+		break;
+	}
+
+	/*
+	 * Initialize the message.
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nwmrlc = &wmesh_msg.msg.exc_cfg;
+	memcpy(nwmrlc, wmrlc, sizeof(*nwmrlc));
+	nss_wifi_mesh_msg_init(&wmesh_msg, ifnum, NSS_WIFI_MESH_CONFIG_EXCEPTION,
+			sizeof(*nwmrlc), msg_cb, app_data);
+
+	/*
+	 * Send the message to NSS asynchronously.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg(&wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh config exception message failed: %d.\n", &wmgr_ctx, nss_status);
+	}
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_config_mesh_exception);
+
+/*
+ * nss_wifi_meshmgr_config_mesh_exception_sync()
+ *	Configure mesh exception synchronously.
+ */
+nss_wifi_meshmgr_status_t
+nss_wifi_meshmgr_config_mesh_exception_sync(nss_wifi_mesh_handle_t mesh_handle,struct nss_wifi_mesh_rate_limit_config *wmrlc)
+{
+	nss_wifi_meshmgr_status_t nss_status;
+	int32_t ret;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_NULL_MESH_CTX;
+	}
+
+	/*
+	 * Send the message to NSS synchronously.
+	 */
+	down(&wmesh_ctx->sem);
+	nss_status = nss_wifi_meshmgr_config_mesh_exception(mesh_handle, wmrlc, nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Mesh config exception message failed: %d.\n", &wmgr_ctx, nss_status);
+		up(&wmesh_ctx->sem);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return nss_status;
+	}
+
+	/*
+	 * Wait for the acknowledgement
+	 */
+	ret = wait_for_completion_timeout(&wmesh_ctx->complete, msecs_to_jiffies(NSS_WIFI_MESH_TX_TIMEOUT));
+	if (!ret) {
+		nss_wifi_meshmgr_warn("%px: WiFi mesh msg tx failed due to timeout\n", &wmgr_ctx);
+		wmesh_ctx->response = NSS_WIFI_MESHMGR_FAILURE_SYNC_TIMEOUT;
+	}
+
+	nss_status = wmesh_ctx->response;
+	up(&wmesh_ctx->sem);
+
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_config_mesh_exception_sync);
+
+/*
+ * nss_wifi_meshmgr_if_destroy_sync()
+ *	Function to unregister and destroy dynamic interfaces synchronously.
+ */
+nss_wifi_meshmgr_status_t nss_wifi_meshmgr_if_destroy_sync(nss_wifi_mesh_handle_t mesh_handle)
+{
+	int32_t encap_ifnum, decap_ifnum;
+	nss_wifi_meshmgr_status_t nss_status;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+
+	wmesh_ctx = nss_wifi_meshmgr_find_and_ref_inc(mesh_handle);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Mesh context is null\n", &wmgr_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE_BAD_PARAM;
+	}
+
+	encap_ifnum = wmesh_ctx->encap_ifnum;
+	decap_ifnum = wmesh_ctx->decap_ifnum;
+
+	/*
+	 * Verify the encap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, encap_ifnum);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	/*
+	 * Verify the decap I/F number against it types.
+	 */
+	if (!(nss_wifi_meshmgr_verify_if_num(decap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER))) {
+		nss_wifi_meshmgr_warn("%px: I/F num: 0x%x verification failed\n", &wmgr_ctx, decap_ifnum);
+		nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+		return NSS_WIFI_MESHMGR_FAILURE;
+	}
+
+	/*
+	 * Send the I/F down message to NSS.
+	 */
+	nss_status = nss_wifi_meshmgr_if_down(mesh_handle);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Sending mesh I/F down to NSS failed: %d\n", &wmgr_ctx, nss_status);
+	}
+
+	/*
+	 * Remove mesh context from the table.
+	 */
+	spin_lock_bh(&wmgr_ctx.ref_lock);
+	nss_wifi_meshmgr_ctx_remove(wmesh_ctx);
+	wmgr_ctx.mesh_count--;
+	spin_unlock_bh(&wmgr_ctx.ref_lock);
+
+	/*
+	 * Release the reference taken during alloc.
+	 */
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+
+	/*
+	 * Release the reference for the find taken at the beginning of the function.
+	 */
+	nss_wifi_meshmgr_ref_dec(wmesh_ctx);
+	return nss_status;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_if_destroy_sync);
+
+/*
+ * nss_wifi_meshmgr_if_create_sync()
+ *	Create and register dynamic interface synchronously.
+ *
+ * Note: Synchronous create message, callbacks are used for driver registration not message handling.
+ */
+nss_wifi_mesh_handle_t nss_wifi_meshmgr_if_create_sync(struct net_device *dev, struct nss_wifi_mesh_config_msg *wmcm,
+						       nss_wifi_mesh_data_callback_t data_cb,
+						       nss_wifi_mesh_ext_data_callback_t ext_data_cb,
+						       nss_wifi_mesh_msg_callback_t event_cb)
+{
+	struct nss_wifi_mesh_msg wmesh_msg;
+	struct nss_wifi_mesh_config_msg *nwmcm;
+	int32_t encap_ifnum, decap_ifnum;
+	uint32_t features = 0;
+	nss_wifi_mesh_handle_t mesh_handle;
+	nss_wifi_meshmgr_status_t nss_status;
+	struct nss_wifi_meshmgr_mesh_ctx *wmesh_ctx;
+
+	spin_lock_bh(&wmgr_ctx.ref_lock);
+	if (wmgr_ctx.mesh_count == NSS_WIFI_MESH_MAX) {
+		nss_wifi_meshmgr_warn("%px: Reached maxed number of mesh interface\n", dev);
+		spin_unlock_bh(&wmgr_ctx.ref_lock);
+		return -1;
+	}
+
+	wmgr_ctx.mesh_count++;
+	spin_unlock_bh(&wmgr_ctx.ref_lock);
+
+	dev_hold(dev);
+	wmesh_ctx = kzalloc(sizeof(*wmesh_ctx), GFP_ATOMIC);
+	if (!wmesh_ctx) {
+		nss_wifi_meshmgr_warn("%px: Failed to allocate memory for mesh context\n", dev);
+		goto ctx_alloc_fail;
+	}
+
+	wmesh_ctx->dev = dev;
+	sema_init(&wmesh_ctx->sem, 1);
+	init_completion(&wmesh_ctx->complete);
+
+	/*
+	 * Alloc the encap dynamic interface node.
+	 */
+	encap_ifnum = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER);
+	if (encap_ifnum < 0) {
+		nss_wifi_meshmgr_warn("%px: Encap allocation failed.\n", dev);
+		goto encap_alloc_fail;
+	}
+
+	if (nss_register_wifi_mesh_if(encap_ifnum, data_cb, ext_data_cb, event_cb,
+					NSS_WIFI_MESH_DP_INNER, dev, features) != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Encap registration failed.\n", dev);
+		goto encap_reg_fail;
+	}
+
+	/*
+	 * Allocate and register decap interface.
+	 */
+	decap_ifnum = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER);
+	if (decap_ifnum < 0) {
+		nss_wifi_meshmgr_warn("%px: Decap allocation failed.\n", dev);
+		goto decap_alloc_fail;
+	}
+
+
+	if (nss_register_wifi_mesh_if(decap_ifnum, data_cb, ext_data_cb, event_cb,
+					NSS_WIFI_MESH_DP_OUTER, dev, features) != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Decap registration failed.\n", dev);
+		goto decap_reg_fail;
+	}
+
+	wmesh_ctx->encap_ifnum = encap_ifnum;
+	wmesh_ctx->decap_ifnum = decap_ifnum;
+
+	nss_wifi_meshmgr_trace("%px: Successfully registered encap and decap iface for Mesh\n", dev);
+
+	/*
+	 * Initialize the encap configuration message.
+	 */
+	memset(&wmesh_msg, 0, sizeof(struct nss_wifi_mesh_msg));
+	nwmcm = &wmesh_msg.msg.mesh_config;
+	nwmcm->ttl = wmcm->ttl;
+	nwmcm->mesh_path_refresh_time = wmcm->mesh_path_refresh_time;
+	nwmcm->mpp_learning_mode = wmcm->mpp_learning_mode;
+	nwmcm->config_flags = wmcm->config_flags | NSS_WIFI_MESH_CONFIG_FLAG_SIBLING_IF_NUM_VALID;
+	nwmcm->sibling_ifnum = decap_ifnum;
+
+	ether_addr_copy(nwmcm->local_mac_addr, wmcm->local_mac_addr);
+	nss_wifi_mesh_msg_init(&wmesh_msg, encap_ifnum, NSS_WIFI_MESH_MSG_INTERFACE_CONFIGURE,
+			sizeof(*nwmcm), nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+
+	/*
+	 * Send the encap configuration message.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg_sync(wmesh_ctx, &wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Encap configuration message failed: %d.\n", dev, nss_status);
+		goto config_failed;
+	}
+
+	/*
+	 * Initialize the decap configuration message.
+	 */
+	nwmcm->sibling_ifnum = encap_ifnum;
+	nwmcm->block_mesh_forwarding = wmcm->block_mesh_forwarding;
+	nss_wifi_mesh_msg_init(&wmesh_msg, decap_ifnum, NSS_WIFI_MESH_MSG_INTERFACE_CONFIGURE,
+			       sizeof(*nwmcm), nss_wifi_meshmgr_tx_msg_cb, wmesh_ctx);
+
+	/*
+	 * Send the decap configuration message.
+	 */
+	nss_status = nss_wifi_meshmgr_tx_msg_sync(wmesh_ctx, &wmesh_msg);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Decap configuration message failed: %d.\n", dev, nss_status);
+		goto config_failed;
+	}
+
+	/*
+	 * Take the self reference on the mesh context.
+	 */
+	atomic_set(&wmesh_ctx->ref, 1);
+
+	/*
+	 * Add the Mesh context to the mesh manager's list.
+	 */
+	spin_lock_bh(&wmgr_ctx.ref_lock);
+	mesh_handle = nss_wifi_meshmgr_ctx_insert(wmesh_ctx);
+	if (mesh_handle < 0) {
+		spin_unlock_bh(&wmgr_ctx.ref_lock);
+		nss_wifi_meshmgr_warn("%px: Insertion for mesh context failed", &wmgr_ctx);
+		goto config_failed;
+	}
+
+	spin_unlock_bh(&wmgr_ctx.ref_lock);
+
+	nss_wifi_meshmgr_trace("%px: WiFi Mesh interface count:%d.\n", dev, wmgr_ctx.mesh_count);
+	return mesh_handle;
+
+config_failed:
+	nss_unregister_wifi_mesh_if(decap_ifnum);
+decap_reg_fail:
+	nss_dynamic_interface_dealloc_node(decap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Decap interface dealloc failed: %d\n", dev, nss_status);
+	}
+decap_alloc_fail:
+	nss_unregister_wifi_mesh_if(encap_ifnum);
+encap_reg_fail:
+	nss_dynamic_interface_dealloc_node(encap_ifnum, NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER);
+	if (nss_status != NSS_WIFI_MESHMGR_SUCCESS) {
+		nss_wifi_meshmgr_warn("%px: Encap interface dealloc failed: %d\n", dev, nss_status);
+	}
+encap_alloc_fail:
+	kfree(wmesh_ctx);
+ctx_alloc_fail:
+	spin_lock_bh(&wmgr_ctx.ref_lock);
+	wmgr_ctx.mesh_count--;
+	spin_unlock_bh(&wmgr_ctx.ref_lock);
+	dev_put(dev);
+	return -1;
+}
+EXPORT_SYMBOL(nss_wifi_meshmgr_if_create_sync);
+
+/*
+ * nss_wifi_meshmgr_exit_module()
+ *	WiFi-Mesh module exit function
+ */
+static void __exit nss_wifi_meshmgr_exit_module(void)
+{
+	int32_t i;
+
+	/*
+	 * Check if there are any mesh I/F. Delete all the mesh I/F from NSS FW and free.
+	 */
+	for (i = 0; i < NSS_WIFI_MESH_MAX; i++) {
+		if (nss_wifi_meshmgr_if_destroy_sync(i) != NSS_WIFI_MESHMGR_SUCCESS) {
+			nss_wifi_meshmgr_warn("%px Destroy failed or context does not exist", &wmgr_ctx);
+		}
+	}
+	nss_wifi_meshmgr_info("Module %s unloaded\n", NSS_CLIENT_BUILD_ID);
+}
+
+/*
+ * nss_wifi_meshmgr_init_module()
+ *	Wi-Fi mesh manager module init function
+ */
+static int __init nss_wifi_meshmgr_init_module(void)
+{
+	struct nss_ctx_instance *nss_ctx;
+	int32_t idx;
+
+#ifdef CONFIG_OF
+	/*
+	 * If the node is not compatible, don't do anything.
+	 */
+	if (!of_find_node_by_name(NULL, "nss-common")) {
+		nss_wifi_meshmgr_warn("NSS common not found.\n");
+		return -1;
+	}
+#endif
+
+	nss_ctx = nss_wifi_mesh_get_context();
+	if (!nss_ctx) {
+		nss_wifi_meshmgr_warn("NSS SoC context is NULL.\n");
+		return -1;
+	}
+
+	wmgr_ctx.nss_ctx = nss_ctx;
+	for (idx = 0; idx < NSS_WIFI_MESH_MAX; idx++) {
+		wmgr_ctx.mesh_ctx[idx] = NULL;
+	}
+
+	wmgr_ctx.mesh_count = 0;
+	spin_lock_init(&wmgr_ctx.ref_lock);
+
+	nss_wifi_meshmgr_info("Module %s loaded\n", NSS_CLIENT_BUILD_ID);
+	return 0;
+}
+
+module_init(nss_wifi_meshmgr_init_module);
+module_exit(nss_wifi_meshmgr_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS WiFi-Mesh manager");
diff --git a/qca-nss-dp/.gitignore b/qca-nss-dp/.gitignore
new file mode 100644
index 0000000..644cc16
--- /dev/null
+++ b/qca-nss-dp/.gitignore
@@ -0,0 +1,15 @@
+
+# Ignore general build intermediate files
+*.o
+*.cmd
+*.ko
+*.mod.*
+*.mod
+Module.symvers
+modules.order
+/.tmp_versions/
+built-in.a
+exports/nss_dp_arch.h
+
+# don't ignore .gitignore itself
+!.gitignore
diff --git a/qca-nss-dp/Makefile b/qca-nss-dp/Makefile
new file mode 100644
index 0000000..157342b
--- /dev/null
+++ b/qca-nss-dp/Makefile
@@ -0,0 +1,72 @@
+###################################################
+# Makefile for the NSS data plane driver
+###################################################
+
+obj ?= .
+
+obj-m += qca-nss-dp.o
+
+qca-nss-dp-objs += nss_dp_attach.o \
+		   nss_dp_ethtools.o \
+		   nss_dp_main.o \
+		   hal/soc_ops/$(SoC)/nss_$(SoC).o
+
+NSS_DP_INCLUDE = -I$(obj)/include -I$(obj)/exports -I$(obj)/hal/include \
+		 -I$(obj)/hal/dp_ops/include
+
+ifeq ($(SoC),$(filter $(SoC),ipq807x ipq60xx))
+qca-nss-dp-objs += hal/dp_ops/edma_dp/edma_v1/edma_cfg.o \
+		   hal/dp_ops/edma_dp/edma_v1/edma_data_plane.o \
+		   hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.o \
+		   hal/gmac_ops/qcom/qcom_if.o \
+		   hal/gmac_ops/syn/xgmac/syn_if.o
+NSS_DP_INCLUDE += -I$(obj)/hal/dp_ops/edma_dp/edma_v1/include
+ccflags-y += -DNSS_DP_PPE_SUPPORT
+ifneq ($(CONFIG_NET_SWITCHDEV),)
+qca-nss-dp-objs += nss_dp_switchdev.o
+ccflags-y += -DNSS_DP_PPE_SWITCHDEV
+endif
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq807x))
+ccflags-y += -DNSS_DP_IPQ807X -DNSS_DP_EDMA_TX_SMALL_PKT_WAR
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq60xx))
+ccflags-y += -DNSS_DP_IPQ60XX
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq50xx))
+qca-nss-dp-objs += hal/dp_ops/syn_gmac_dp/syn_dp_cfg_rx.o  \
+		   hal/dp_ops/syn_gmac_dp/syn_dp_cfg_tx.o \
+		   hal/dp_ops/syn_gmac_dp/syn_dp_rx.o \
+		   hal/dp_ops/syn_gmac_dp/syn_dp_tx.o \
+		   hal/dp_ops/syn_gmac_dp/syn_dp.o \
+		   hal/gmac_ops/syn/gmac/syn_if.o
+NSS_DP_INCLUDE += -I$(obj)/hal/dp_ops/syn_gmac_dp/include
+ccflags-y += -DNSS_DP_IPQ50XX
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq95xx))
+qca-nss-dp-objs += hal/dp_ops/edma_dp/edma_v2/edma.o \
+		   hal/dp_ops/edma_dp/edma_v2/edma_cfg_rx.o \
+		   hal/dp_ops/edma_dp/edma_v2/edma_cfg_tx.o \
+		   hal/dp_ops/edma_dp/edma_v2/edma_debugfs.o \
+		   hal/dp_ops/edma_dp/edma_v2/edma_dp.o \
+		   hal/dp_ops/edma_dp/edma_v2/edma_misc.o \
+		   hal/dp_ops/edma_dp/edma_v2/edma_rx.o \
+		   hal/dp_ops/edma_dp/edma_v2/edma_tx.o \
+		   hal/gmac_ops/qcom/qcom_if.o \
+		   hal/gmac_ops/syn/xgmac/syn_if.o
+NSS_DP_INCLUDE += -I$(obj)/hal/dp_ops/edma_dp/edma_v2
+NSS_DP_INCLUDE += -I$(obj)/hal/dp_ops/edma_dp/edma_v2/include
+ccflags-y += -DNSS_DP_IPQ95XX -DNSS_DP_PPE_SUPPORT
+ifneq ($(CONFIG_NET_SWITCHDEV),)
+qca-nss-dp-objs += nss_dp_switchdev.o
+ccflags-y += -DNSS_DP_PPE_SWITCHDEV
+endif
+endif
+
+ccflags-y += $(NSS_DP_INCLUDE)
+ccflags-y += -Wall -Werror
+ccflags-y += -DEDMA_DEBUG_LEVEL=2
diff --git a/qca-nss-dp/build.sh b/qca-nss-dp/build.sh
new file mode 100755
index 0000000..026f25b
--- /dev/null
+++ b/qca-nss-dp/build.sh
@@ -0,0 +1,104 @@
+#!/bin/bash
+
+set -e
+set -o errtrace
+trap 'echo Fatal error: script $0 aborting at line $LINENO, command \"$BASH_COMMAND\" returned $?; exit 1' ERR
+
+PRODUCT_LIST="sirocco"
+
+NUM_JOBS=$(grep -c processor /proc/cpuinfo)
+
+MODULE_NAME="qca-nss-dp"
+###################################################
+# Setup build toollchain
+###################################################
+sdk_top_dir=$(readlink -e $(dirname $0)/..)
+TOP_DIR=$(readlink -e ${sdk_top_dir}/..)
+
+#export ARCH and build related envs.
+source ${TOP_DIR}/sdk/build_scripts/setup_env.sh
+
+kernel_path=$(readlink -e ${sdk_top_dir}/../kernel)
+qca_ssdk_include_path=$(readlink -e ${sdk_top_dir}/qca-ssdk/include)
+qca_ssdk_common_path=$(readlink -e ${sdk_top_dir}/qca-ssdk/include/common)
+qca_ssdk_sal_path=$(readlink -e ${sdk_top_dir}/qca-ssdk/include/sal/os)
+qca_ssdk_sal_linux_path=$(readlink -e ${sdk_top_dir}/qca-ssdk/include/sal/os/linux)
+qca_ssdk_dependency=$(readlink -e ${sdk_top_dir}/qca-ssdk)
+soc_type=ipq50xx
+
+extra_cflags="-I${qca_ssdk_include_path} -I${qca_ssdk_common_path} -I${qca_ssdk_sal_path} -I${qca_ssdk_sal_linux_path}"
+
+##################################################
+# Build Kernel Module
+##################################################
+function BuildKModule() {
+    # make kernel module
+    echo "Build ${MODULE_NAME}"
+    ln -f  hal/soc_ops/${soc_type}/nss_${soc_type}.h  exports/nss_dp_arch.h
+    ${CROSS_MAKE} -C ${kernel_path} M=${sdk_top_dir}/${MODULE_NAME} SoC=${soc_type} EXTRA_CFLAGS="${extra_cflags}" KBUILD_EXTRA_SYMBOLS=${qca_ssdk_dependency}/Module.symvers V=1
+}
+
+##################################################
+# Build & Install
+##################################################
+function BuildAndInstall() {
+    local product=$1
+    local eureka_src_path=$(readlink -e $2)
+    if [ -z ${eureka_src_path} ]; then
+      echo "eureka_src_path doesn't exist"
+      exit 1
+    fi
+
+    # clean previous build
+    find . -name "*.o" -delete
+    find . -name "*.cmd" -delete
+    find . -name "*.ko" -delete
+    find . -name "*.mod.*" -delete
+    find . -name "*.mod" -delete
+    find . -name Module.symvers -delete
+
+    # build module
+    BuildKModule
+
+    # install module
+    echo "Install ${MODULE_NAME}.ko"
+    local module_target_dir="$(GetModulePath ${eureka_src_path} ${product})"
+    mkdir -p ${module_target_dir}
+    cp -f ${MODULE_NAME}.ko ${module_target_dir}/.
+}
+
+function Usage() {
+    cat << EOF
+Usage:
+    $0 <product> <eureka_src_path>
+    Valid products: ${PRODUCT_LIST}
+EOF
+}
+
+function IsProductValid() {
+  local product
+  local ret=1
+
+  for product in ${PRODUCT_LIST}; do
+    if [ "${product}" == "$1" ]; then
+      ret=0
+      break
+    fi
+  done
+
+  return ${ret}
+}
+
+#########################
+####### Main Entry ######
+#########################
+if (( $# < 2 )); then
+  Usage
+else
+  if IsProductValid $1; then
+    BuildAndInstall $1 $2
+  else
+    echo "$1 is a invalid product"
+    Usage
+  fi
+fi
diff --git a/qca-nss-dp/exports/nss_dp_api_if.h b/qca-nss-dp/exports/nss_dp_api_if.h
new file mode 100644
index 0000000..c3f0cda
--- /dev/null
+++ b/qca-nss-dp/exports/nss_dp_api_if.h
@@ -0,0 +1,246 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_dp_api_if.h
+ *	nss-dp exported structures/apis.
+ *
+ * This file declares all the public interfaces
+ * for NSS data-plane driver.
+ */
+
+#ifndef __NSS_DP_API_IF_H
+#define __NSS_DP_API_IF_H
+
+#include "nss_dp_arch.h"
+
+/**
+ * @addtogroup nss_dp_subsystem
+ * @{
+ */
+
+/*
+ * NSS DP status
+ */
+#define NSS_DP_SUCCESS	0
+#define NSS_DP_FAILURE	-1
+
+/*
+ * NSS DP platform specific defines
+ */
+#define NSS_DP_START_IFNUM	NSS_DP_HAL_START_IFNUM
+			/**< First GMAC interface number (0/1) depending on SoC. */
+#define NSS_DP_MAX_INTERFACES	(NSS_DP_HAL_MAX_PORTS + NSS_DP_START_IFNUM)
+			/**< Last interface index for the SoC, to be used by qca-nss-drv. */
+#define NSS_DP_INVALID_INTERFACE -1
+
+/*
+ * NSS PTP service code
+ */
+#define NSS_PTP_EVENT_SERVICE_CODE	0x9
+
+/**
+ * nss_dp_data_plane_ctx
+ *	Data plane context base class.
+ */
+struct nss_dp_data_plane_ctx {
+	struct net_device *dev;
+};
+
+/**
+ * nss_dp_gmac_stats
+ *	The per-GMAC statistics structure.
+ */
+struct nss_dp_gmac_stats {
+	struct nss_dp_hal_gmac_stats stats;
+};
+
+/**
+ * nss_dp_data_plane_ops
+ *	Per data-plane ops structure.
+ *
+ * Default would be slowpath and can be overridden by nss-drv
+ */
+struct nss_dp_data_plane_ops {
+	int (*init)(struct nss_dp_data_plane_ctx *dpc);
+	int (*open)(struct nss_dp_data_plane_ctx *dpc, uint32_t tx_desc_ring,
+		    uint32_t rx_desc_ring, uint32_t mode);
+	int (*close)(struct nss_dp_data_plane_ctx *dpc);
+	int (*link_state)(struct nss_dp_data_plane_ctx *dpc,
+			  uint32_t link_state);
+	int (*mac_addr)(struct nss_dp_data_plane_ctx *dpc, uint8_t *addr);
+	int (*change_mtu)(struct nss_dp_data_plane_ctx *dpc, uint32_t mtu);
+	netdev_tx_t (*xmit)(struct nss_dp_data_plane_ctx *dpc, struct sk_buff *os_buf);
+	void (*set_features)(struct nss_dp_data_plane_ctx *dpc);
+	int (*pause_on_off)(struct nss_dp_data_plane_ctx *dpc,
+			    uint32_t pause_on);
+	int (*vsi_assign)(struct nss_dp_data_plane_ctx *dpc, uint32_t vsi);
+	int (*vsi_unassign)(struct nss_dp_data_plane_ctx *dpc, uint32_t vsi);
+	int (*rx_flow_steer)(struct nss_dp_data_plane_ctx *dpc, struct sk_buff *skb,
+				uint32_t cpu, bool is_add);
+	void (*get_stats)(struct nss_dp_data_plane_ctx *dpc, struct nss_dp_gmac_stats *stats);
+	int (*deinit)(struct nss_dp_data_plane_ctx *dpc);
+};
+
+/**
+ * nss_dp_receive
+ *	Called by overlay drivers to deliver packets to nss-dp.
+ *
+ * @datatypes
+ * net_device
+ * sk_buff
+ * napi_struct
+ *
+ * @param[in] netdev Pointer to netdev structure on which packet is received.
+ * @param[in] skb Pointer to the received packet.
+ * @param[in] napi Pointer to napi context.
+ */
+void nss_dp_receive(struct net_device *netdev, struct sk_buff *skb,
+						struct napi_struct *napi);
+
+/**
+ * nss_dp_is_in_open_state
+ *	Returns if a data plane is opened or not.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] netdev Pointer to netdev structure.
+ *
+ * @return
+ * bool
+ */
+bool nss_dp_is_in_open_state(struct net_device *netdev);
+
+/**
+ * nss_dp_override_data_palne
+ *	API to allow overlay drivers to override the data plane.
+ *
+ * @datatypes
+ * net_device
+ * nss_dp_data_plane_ops
+ * nss_dp_data_plane_ctx
+ *
+ * @param[in] netdev Pointer to netdev structure.
+ * @param[in] dp_ops Pointer to respective data plane ops structure.
+ * @param[in] dpc Pointer to data plane context.
+ *
+ * @return
+ * int
+ */
+int nss_dp_override_data_plane(struct net_device *netdev,
+			       struct nss_dp_data_plane_ops *dp_ops,
+			       struct nss_dp_data_plane_ctx *dpc);
+
+/**
+ * nss_dp_start_data_plane
+ *	Dataplane API to inform netdev when it is ready to start.
+ *
+ * @datatypes
+ * net_device
+ * nss_dp_data_plane_ctx
+ *
+ * @param[in] netdev Pointer to netdev structure.
+ * @param[in] dpc Pointer to data plane context.
+ */
+void nss_dp_start_data_plane(struct net_device *netdev,
+			     struct nss_dp_data_plane_ctx *dpc);
+
+/**
+ * nss_dp_restore_data_plane
+ *	Called by overlay drivers to detach itself from nss-dp.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] netdev Pointer to netdev structure.
+ */
+void nss_dp_restore_data_plane(struct net_device *netdev);
+
+/**
+ * nss_dp_get_netdev_by_nss_if_num
+ *	Returns the net device of the corresponding id if it exists.
+ *
+ * @datatypes
+ * int
+ *
+ * @param[in] interface ID of the physical mac port.
+ *
+ * @return
+ * Pointer to netdev structure.
+ */
+struct net_device *nss_dp_get_netdev_by_nss_if_num(int if_num);
+
+/**
+ * nss_phy_tstamp_rx_buf
+ *	Receive timestamp packet.
+ *
+ * @datatypes
+ * sk_buff
+ *
+ * @param[in] app_data Pointer to the application context of the message.
+ * @param[in] skb Pointer to the packet.
+ */
+void nss_phy_tstamp_rx_buf(void *app_data, struct sk_buff *skb);
+
+/**
+ * nss_phy_tstamp_tx_buf
+ *	Transmit timestamp packet
+ *
+ * @datatypes
+ * net_device
+ * sk_buff
+ *
+ * @param[in] net_device Pointer to netdev structure.
+ * @param[in] skb Pointer to the packet.
+ */
+void nss_phy_tstamp_tx_buf(struct net_device *ndev, struct sk_buff *skb);
+
+/**
+ * nss_dp_is_netdev_physical
+ *	Returns true if the net device is physical, false otherwise..
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] net_device pointer to netdev structure.
+ *
+ * @return
+ * true if interface is physical, false otherwise.
+ */
+bool nss_dp_is_netdev_physical(struct net_device *netdev);
+
+/**
+ * nss_dp_get_port_num
+ *	Returns the port number for the physical interface.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] net_device pointer to netdev structure.
+ *
+ * @return
+ * port number correspond to this net_device.
+ */
+int32_t nss_dp_get_port_num(struct net_device *netdev);
+
+/**
+ *@}
+ */
+
+#endif	/** __NSS_DP_API_IF_H */
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c
new file mode 100644
index 0000000..fbd315a
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c
@@ -0,0 +1,968 @@
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include <linux/interrupt.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/debugfs.h>
+#include <linux/reset.h>
+
+#include "edma_regs.h"
+#include "edma_data_plane.h"
+#include "nss_dp_dev.h"
+
+#define EDMA_HW_RESET_ID "edma_rst"
+
+/*
+ * edma_cleanup_rxfill_ring_res()
+ *	Cleanup resources for one RxFill ring
+ */
+static void edma_cleanup_rxfill_ring_res(struct edma_hw *ehw,
+				struct edma_rxfill_ring *rxfill_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+	struct sk_buff *skb;
+	uint16_t cons_idx, curr_idx;
+	struct edma_rxfill_desc *rxfill_desc;
+	uint32_t reg_data = 0;
+	struct edma_rx_preheader *rxph = NULL;
+	int store_idx;
+
+	/*
+	 * Read RXFILL ring producer index
+	 */
+	reg_data = edma_reg_read(EDMA_REG_RXFILL_PROD_IDX(rxfill_ring->id));
+	curr_idx = reg_data & EDMA_RXFILL_PROD_IDX_MASK;
+
+	/*
+	 * Read RXFILL ring consumer index
+	 */
+	reg_data = edma_reg_read(EDMA_REG_RXFILL_CONS_IDX(rxfill_ring->id));
+	cons_idx = reg_data & EDMA_RXFILL_CONS_IDX_MASK;
+
+	while (curr_idx != cons_idx) {
+		/*
+		 * Get RXFILL descriptor
+		 */
+		rxfill_desc = EDMA_RXFILL_DESC(rxfill_ring, cons_idx);
+
+		/*
+		 * Get Rx preheader
+		 */
+		rxph = (struct edma_rx_preheader *)
+			phys_to_virt(rxfill_desc->buffer_addr);
+
+		dma_unmap_single(&pdev->dev, rxfill_desc->buffer_addr,
+					ehw->rx_alloc_size, DMA_FROM_DEVICE);
+
+		/*
+		 * Get sk_buff and free it
+		 */
+		store_idx = rxph->opaque;
+		skb = ehw->rx_skb_store[store_idx];
+		ehw->rx_skb_store[store_idx] = NULL;
+		dev_kfree_skb_any(skb);
+		cons_idx++;
+		if (cons_idx == rxfill_ring->count)
+			cons_idx = 0;
+	}
+
+	/*
+	 * Free RXFILL ring descriptors
+	 */
+	dma_free_coherent(&pdev->dev,
+				(sizeof(struct edma_rxfill_desc)
+				* rxfill_ring->count),
+				rxfill_ring->desc, rxfill_ring->dma);
+}
+
+/*
+ * edma_setup_rxfill_ring_res()
+ *	Setup resources for one RxFill ring
+ */
+static int edma_setup_rxfill_ring_res(struct edma_hw *ehw,
+				struct edma_rxfill_ring *rxfill_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+
+	/*
+	 * Allocate RxFill ring descriptors
+	 */
+	rxfill_ring->desc = dma_alloc_coherent(&pdev->dev,
+				(sizeof(struct edma_rxfill_desc)
+				* rxfill_ring->count),
+				&rxfill_ring->dma, GFP_KERNEL);
+	if (!rxfill_ring->desc) {
+		pr_warn("Descriptor alloc for RXFILL ring %u failed\n",
+				rxfill_ring->id);
+		return -ENOMEM;
+	}
+
+	spin_lock_init(&rxfill_ring->lock);
+	return 0;
+}
+
+/*
+ * edma_setup_rxdesc_ring_res()
+ *	Setup resources for one RxDesc ring
+ */
+static int edma_setup_rxdesc_ring_res(struct edma_hw *ehw,
+				struct edma_rxdesc_ring *rxdesc_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+
+	/*
+	 * Allocate RxDesc ring descriptors
+	 */
+	rxdesc_ring->desc = dma_alloc_coherent(&pdev->dev,
+				(sizeof(struct edma_rxdesc_desc)
+				* rxdesc_ring->count),
+				&rxdesc_ring->dma, GFP_KERNEL);
+	if (!rxdesc_ring->desc) {
+		pr_warn("Descriptor alloc for RXDESC ring %u failed\n",
+				rxdesc_ring->id);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+/*
+ * edma_cleanup_rxdesc_ring_res()
+ *	Cleanup resources for RxDesc ring
+ */
+static void edma_cleanup_rxdesc_ring_res(struct edma_hw *ehw,
+				struct edma_rxdesc_ring *rxdesc_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+	struct sk_buff *skb;
+	struct edma_rxdesc_desc *rxdesc_desc;
+	struct edma_rx_preheader *rxph = NULL;
+	uint16_t prod_idx = 0;
+	uint16_t cons_idx = 0;
+	int store_idx;
+
+	cons_idx = edma_reg_read(EDMA_REG_RXDESC_CONS_IDX(rxdesc_ring->id))
+					& EDMA_RXDESC_CONS_IDX_MASK;
+
+	prod_idx = edma_reg_read(EDMA_REG_RXDESC_PROD_IDX(rxdesc_ring->id))
+					& EDMA_RXDESC_PROD_IDX_MASK;
+
+	/*
+	 * Free any buffers assigned to any descriptors
+	 */
+	while (cons_idx != prod_idx) {
+		rxdesc_desc = EDMA_RXDESC_DESC(rxdesc_ring, cons_idx);
+
+		rxph = (struct edma_rx_preheader *)
+			phys_to_virt(rxdesc_desc->buffer_addr);
+
+		dma_unmap_single(&pdev->dev, rxdesc_desc->buffer_addr,
+					ehw->rx_alloc_size, DMA_FROM_DEVICE);
+		store_idx = rxph->opaque;
+		skb = ehw->rx_skb_store[store_idx];
+		ehw->rx_skb_store[store_idx] = NULL;
+		dev_kfree_skb_any(skb);
+
+		/*
+		 * Update consumer index
+		 */
+		if (++cons_idx == rxdesc_ring->count)
+			cons_idx = 0;
+	}
+
+	/*
+	 * Free RXDESC ring descriptors
+	 */
+	dma_free_coherent(&pdev->dev,
+				(sizeof(struct edma_rxdesc_desc)
+				* rxdesc_ring->count),
+				rxdesc_ring->desc, rxdesc_ring->dma);
+}
+
+/*
+ * edma_cleanup_txcmpl_ring_res()
+ *	Cleanup resources for one TxCmpl ring
+ */
+static void edma_cleanup_txcmpl_ring_res(struct edma_hw *ehw,
+				struct edma_txcmpl_ring *txcmpl_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+
+	/*
+	 * Free any buffers assigned to any descriptors
+	 */
+	edma_clean_tx(ehw, txcmpl_ring);
+
+	/*
+	 * Free TxCmpl ring descriptors
+	 */
+	dma_free_coherent(&pdev->dev,
+				(sizeof(struct edma_txcmpl_desc)
+				* txcmpl_ring->count),
+				txcmpl_ring->desc, txcmpl_ring->dma);
+}
+
+/*
+ * edma_setup_txcmpl_ring_res()
+ *	Setup resources for one TxCmpl ring
+ */
+static int edma_setup_txcmpl_ring_res(struct edma_hw *ehw,
+				struct edma_txcmpl_ring *txcmpl_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+
+	/*
+	 * Allocate TxCmpl ring descriptors
+	 */
+	txcmpl_ring->desc = dma_alloc_coherent(&pdev->dev,
+					(sizeof(struct edma_txcmpl_desc)
+					* txcmpl_ring->count),
+					&txcmpl_ring->dma, GFP_KERNEL);
+
+	if (!txcmpl_ring->desc) {
+		pr_warn("Descriptor alloc for TXCMPL ring %u failed\n",
+				txcmpl_ring->id);
+
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+/*
+ * edma_cleanup_txdesc_ring_res()
+ *	Cleanup resources for one TxDesc ring
+ */
+static void edma_cleanup_txdesc_ring_res(struct edma_hw *ehw,
+				struct edma_txdesc_ring *txdesc_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+	struct sk_buff *skb = NULL;
+	struct edma_txdesc_desc *txdesc = NULL;
+	uint16_t prod_idx, cons_idx;
+	size_t buf_len;
+	uint32_t data;
+	int store_idx;
+
+	/*
+	 * Free any buffers assigned to any descriptors
+	 */
+	data = edma_reg_read(EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id));
+	prod_idx = data & EDMA_TXDESC_PROD_IDX_MASK;
+
+	data = edma_reg_read(EDMA_REG_TXDESC_CONS_IDX(txdesc_ring->id));
+	cons_idx = data & EDMA_TXDESC_CONS_IDX_MASK;
+
+	while (cons_idx != prod_idx) {
+		txdesc = EDMA_TXDESC_DESC(txdesc_ring, cons_idx);
+		store_idx = txdesc->buffer_addr;
+		skb = ehw->tx_skb_store[store_idx];
+		ehw->tx_skb_store[store_idx] = NULL;
+
+		buf_len = (txdesc->word1 & EDMA_TXDESC_DATA_LENGTH_MASK) >>
+				EDMA_TXDESC_DATA_LENGTH_SHIFT;
+
+		dma_unmap_single(&pdev->dev, (dma_addr_t)skb->data,
+				buf_len + EDMA_TX_PREHDR_SIZE, DMA_TO_DEVICE);
+
+		dev_kfree_skb_any(skb);
+		cons_idx = (cons_idx + 1) & (txdesc_ring->count - 1);
+		cons_idx++;
+		if (cons_idx == txdesc_ring->count)
+			cons_idx = 0;
+
+	}
+
+	/*
+	 * Free Tx ring descriptors
+	 */
+	dma_free_coherent(&pdev->dev,
+			  (sizeof(struct edma_txdesc_desc)
+			   * txdesc_ring->count),
+			   txdesc_ring->desc, txdesc_ring->dma);
+
+}
+
+/*
+ * edma_setup_txdesc_ring_res()
+ *	Setup resources for one TxDesc ring
+ */
+static int edma_setup_txdesc_ring_res(struct edma_hw *ehw,
+				struct edma_txdesc_ring *txdesc_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+
+	/*
+	 * Allocate Tx ring descriptors
+	 */
+	txdesc_ring->desc = dma_alloc_coherent(&pdev->dev,
+					(sizeof(struct edma_txdesc_desc)
+					* txdesc_ring->count),
+					&txdesc_ring->dma, GFP_KERNEL);
+	if (!txdesc_ring->desc) {
+		pr_warn("Descriptor alloc for TXDESC ring %u failed\n",
+				txdesc_ring->id);
+		return -ENOMEM;
+	}
+
+	spin_lock_init(&txdesc_ring->tx_lock);
+
+	return 0;
+}
+
+/*
+ * edma_setup_ring_resources()
+ *	Allocate/setup resources for EDMA rings
+ */
+static int edma_setup_ring_resources(struct edma_hw *ehw)
+{
+	struct edma_txcmpl_ring *txcmpl_ring = NULL;
+	struct edma_txdesc_ring *txdesc_ring = NULL;
+	struct edma_rxfill_ring *rxfill_ring = NULL;
+	struct edma_rxdesc_ring *rxdesc_ring = NULL;
+	int i;
+	int ret;
+	int index;
+
+	/*
+	 * Allocate TxDesc ring descriptors
+	 */
+	for (i = 0; i < ehw->txdesc_rings; i++) {
+		txdesc_ring = &ehw->txdesc_ring[i];
+		txdesc_ring->count = EDMA_RING_SIZE;
+		txdesc_ring->id = ehw->txdesc_ring_start + i;
+
+		ret = edma_setup_txdesc_ring_res(ehw, txdesc_ring);
+		if (ret != 0) {
+			while (i-- >= 0)
+				edma_cleanup_txdesc_ring_res(ehw,
+					&ehw->txdesc_ring[i]);
+
+			return -ENOMEM;
+
+		}
+	}
+
+	/*
+	 * Allocate TxCmpl ring descriptors
+	 */
+	for (i = 0; i < ehw->txcmpl_rings; i++) {
+		txcmpl_ring = &ehw->txcmpl_ring[i];
+		txcmpl_ring->count = EDMA_RING_SIZE;
+		txcmpl_ring->id = ehw->txcmpl_ring_start + i;
+
+		ret = edma_setup_txcmpl_ring_res(ehw, txcmpl_ring);
+
+		if (ret != 0) {
+			while (i-- >= 0)
+				edma_cleanup_txcmpl_ring_res(ehw,
+						&ehw->txcmpl_ring[i]);
+
+			goto txcmpl_mem_alloc_fail;
+		}
+	}
+
+	/*
+	 * Allocate Rx fill ring descriptors
+	 */
+	for (i = 0; i < ehw->rxfill_rings; i++) {
+		rxfill_ring = &ehw->rxfill_ring[i];
+		rxfill_ring->count = EDMA_RING_SIZE;
+		rxfill_ring->id = ehw->rxfill_ring_start + i;
+
+		ret = edma_setup_rxfill_ring_res(ehw, rxfill_ring);
+		if (ret != 0) {
+			while (--i >= 0)
+				edma_cleanup_rxfill_ring_res(ehw,
+					&ehw->rxfill_ring[i]);
+
+			goto rxfill_mem_alloc_fail;
+		}
+	}
+
+	/*
+	 * Allocate RxDesc ring descriptors
+	 */
+	for (i = 0; i < ehw->rxdesc_rings; i++) {
+		rxdesc_ring = &ehw->rxdesc_ring[i];
+		rxdesc_ring->count = EDMA_RING_SIZE;
+		rxdesc_ring->id = ehw->rxdesc_ring_start + i;
+
+		/*
+		 * Create a mapping between RX Desc ring and Rx fill ring.
+		 * Number of fill rings are lesser than the descriptor rings
+		 * Share the fill rings across descriptor rings.
+		 */
+
+		index = ehw->rxfill_ring_start + (i % ehw->rxfill_rings);
+		rxdesc_ring->rxfill =
+			&ehw->rxfill_ring[index - ehw->rxfill_ring_start];
+
+		ret = edma_setup_rxdesc_ring_res(ehw, rxdesc_ring);
+		if (ret != 0) {
+			while (--i >= 0)
+				edma_cleanup_rxdesc_ring_res(ehw,
+						&ehw->rxdesc_ring[i]);
+
+			goto rxdesc_mem_alloc_fail;
+		}
+	}
+
+	return 0;
+
+rxdesc_mem_alloc_fail:
+	for (i = 0; i < ehw->rxfill_rings; i++)
+		edma_cleanup_rxfill_ring_res(ehw, &ehw->rxfill_ring[i]);
+
+rxfill_mem_alloc_fail:
+	for (i = 0; i < ehw->txcmpl_rings; i++)
+		edma_cleanup_txcmpl_ring_res(ehw, &ehw->txcmpl_ring[i]);
+
+txcmpl_mem_alloc_fail:
+	for (i = 0; i < ehw->txdesc_rings; i++)
+		edma_cleanup_txdesc_ring_res(ehw, &ehw->txdesc_ring[i]);
+
+	return -ENOMEM;
+}
+
+/*
+ * edma_free_rings()
+ *	Free EDMA software rings
+ */
+static void edma_free_rings(struct edma_hw *ehw)
+{
+	kfree(ehw->rxfill_ring);
+	kfree(ehw->rxdesc_ring);
+	kfree(ehw->txdesc_ring);
+	kfree(ehw->txcmpl_ring);
+}
+
+/*
+ * edma_alloc_rings()
+ *	Allocate EDMA software rings
+ */
+static int edma_alloc_rings(struct edma_hw *ehw)
+{
+	ehw->rxfill_ring = kzalloc((sizeof(struct edma_rxfill_ring) *
+				ehw->rxfill_rings), GFP_KERNEL);
+	if (!ehw->rxfill_ring)
+		return -ENOMEM;
+
+	ehw->rxdesc_ring = kzalloc((sizeof(struct edma_rxdesc_ring) *
+				ehw->rxdesc_rings), GFP_KERNEL);
+	if (!ehw->rxdesc_ring)
+		goto rxdesc_ring_alloc_fail;
+
+	ehw->txdesc_ring = kzalloc((sizeof(struct edma_txdesc_ring) *
+				ehw->txdesc_rings), GFP_KERNEL);
+	if (!ehw->txdesc_ring)
+		goto txdesc_ring_alloc_fail;
+
+	ehw->txcmpl_ring = kzalloc((sizeof(struct edma_txcmpl_ring) *
+				ehw->txcmpl_rings), GFP_KERNEL);
+	if (!ehw->txcmpl_ring)
+		goto txcmpl_ring_alloc_fail;
+
+	pr_info("Num rings - TxDesc:%u (%u-%u) TxCmpl:%u (%u-%u)\n",
+			ehw->txdesc_rings, ehw->txdesc_ring_start,
+			(ehw->txdesc_ring_start + ehw->txdesc_rings - 1),
+			ehw->txcmpl_rings, ehw->txcmpl_ring_start,
+			(ehw->txcmpl_ring_start + ehw->txcmpl_rings - 1));
+
+	pr_info("RxDesc:%u (%u-%u) RxFill:%u (%u-%u)\n",
+		ehw->rxdesc_rings, ehw->rxdesc_ring_start,
+		(ehw->rxdesc_ring_start + ehw->rxdesc_rings - 1),
+		ehw->rxfill_rings, ehw->rxfill_ring_start,
+		(ehw->rxfill_ring_start + ehw->rxfill_rings - 1));
+
+	return 0;
+txcmpl_ring_alloc_fail:
+	kfree(ehw->txdesc_ring);
+txdesc_ring_alloc_fail:
+	kfree(ehw->rxdesc_ring);
+rxdesc_ring_alloc_fail:
+	kfree(ehw->rxfill_ring);
+	return -ENOMEM;
+}
+
+/*
+ * edma_cleanup_rings()
+ *	Cleanup EDMA rings
+ */
+void edma_cleanup_rings(struct edma_hw *ehw)
+{
+	int i;
+
+	/*
+	 * Free any buffers assigned to any descriptors
+	 */
+	for (i = 0; i < ehw->txdesc_rings; i++)
+		edma_cleanup_txdesc_ring_res(ehw, &ehw->txdesc_ring[i]);
+
+	/*
+	 * Free Tx completion descriptors
+	 */
+	for (i = 0; i < ehw->txcmpl_rings; i++)
+		edma_cleanup_txcmpl_ring_res(ehw, &ehw->txcmpl_ring[i]);
+
+	/*
+	 * Free Rx fill ring descriptors
+	 */
+	for (i = 0; i < ehw->rxfill_rings; i++)
+		edma_cleanup_rxfill_ring_res(ehw, &ehw->rxfill_ring[i]);
+
+	/*
+	 * Free Rx completion ring descriptors
+	 */
+	for (i = 0; i < ehw->rxdesc_rings; i++)
+		edma_cleanup_rxdesc_ring_res(ehw, &ehw->rxdesc_ring[i]);
+
+	edma_free_rings(ehw);
+}
+
+/*
+ * edma_init_rings()
+ *	Initialize EDMA rings
+ */
+static int edma_init_rings(struct edma_hw *ehw)
+{
+	int ret = 0;
+
+	ret = edma_alloc_rings(ehw);
+	if (ret)
+		return ret;
+
+	ret = edma_setup_ring_resources(ehw);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/*
+ * edma_configure_txdesc_ring()
+ *	Configure one TxDesc ring
+ */
+static void edma_configure_txdesc_ring(struct edma_hw *ehw,
+					struct edma_txdesc_ring *txdesc_ring)
+{
+	uint32_t data = 0;
+	uint16_t hw_cons_idx = 0;
+
+	/*
+	 * Configure TXDESC ring
+	 */
+	edma_reg_write(EDMA_REG_TXDESC_BA(txdesc_ring->id),
+			(uint32_t)(txdesc_ring->dma &
+			EDMA_RING_DMA_MASK));
+
+	edma_reg_write(EDMA_REG_TXDESC_RING_SIZE(txdesc_ring->id),
+			(uint32_t)(txdesc_ring->count &
+			EDMA_TXDESC_RING_SIZE_MASK));
+
+	data = edma_reg_read(EDMA_REG_TXDESC_CONS_IDX(txdesc_ring->id));
+	data &= ~(EDMA_TXDESC_CONS_IDX_MASK);
+	hw_cons_idx = data;
+
+	data = edma_reg_read(EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id));
+	data &= ~(EDMA_TXDESC_PROD_IDX_MASK);
+	data |= hw_cons_idx & EDMA_TXDESC_PROD_IDX_MASK;
+	edma_reg_write(EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id), data);
+}
+
+/*
+ * edma_configure_txcmpl_ring()
+ *	Configure one TxCmpl ring
+ */
+static void edma_configure_txcmpl_ring(struct edma_hw *ehw,
+					struct edma_txcmpl_ring *txcmpl_ring)
+{
+	uint32_t tx_mod_timer;
+
+	/*
+	 * Configure TxCmpl ring base address
+	 */
+	edma_reg_write(EDMA_REG_TXCMPL_BA(txcmpl_ring->id),
+			(uint32_t)(txcmpl_ring->dma & EDMA_RING_DMA_MASK));
+	edma_reg_write(EDMA_REG_TXCMPL_RING_SIZE(txcmpl_ring->id),
+			(uint32_t)(txcmpl_ring->count
+			& EDMA_TXDESC_RING_SIZE_MASK));
+
+	/*
+	 * Set TxCmpl ret mode to opaque
+	 */
+	edma_reg_write(EDMA_REG_TXCMPL_CTRL(txcmpl_ring->id),
+			EDMA_TXCMPL_RETMODE_OPAQUE);
+
+	tx_mod_timer = (EDMA_TX_MOD_TIMER & EDMA_TX_MOD_TIMER_INIT_MASK)
+			<< EDMA_TX_MOD_TIMER_INIT_SHIFT;
+	edma_reg_write(EDMA_REG_TX_MOD_TIMER(txcmpl_ring->id),
+				tx_mod_timer);
+
+	edma_reg_write(EDMA_REG_TX_INT_CTRL(txcmpl_ring->id), 0x2);
+}
+
+/*
+ * edma_configure_rxdesc_ring()
+ *	Configure one RxDesc ring
+ */
+static void edma_configure_rxdesc_ring(struct edma_hw *ehw,
+					struct edma_rxdesc_ring *rxdesc_ring)
+{
+	uint32_t data;
+
+	edma_reg_write(EDMA_REG_RXDESC_BA(rxdesc_ring->id),
+			(uint32_t)(rxdesc_ring->dma & 0xffffffff));
+
+	data = rxdesc_ring->count & EDMA_RXDESC_RING_SIZE_MASK;
+	data |= (ehw->rx_payload_offset & EDMA_RXDESC_PL_OFFSET_MASK)
+		 << EDMA_RXDESC_PL_OFFSET_SHIFT;
+	edma_reg_write(EDMA_REG_RXDESC_RING_SIZE(rxdesc_ring->id), data);
+
+	data = (EDMA_RX_MOD_TIMER_INIT & EDMA_RX_MOD_TIMER_INIT_MASK)
+			<< EDMA_RX_MOD_TIMER_INIT_SHIFT;
+	edma_reg_write(EDMA_REG_RX_MOD_TIMER(rxdesc_ring->id), data);
+
+	/*
+	 * Enable ring. Set ret mode to 'opaque'.
+	 */
+	edma_reg_write(EDMA_REG_RX_INT_CTRL(rxdesc_ring->id), 0x2);
+}
+
+/*
+ * edma_configure_rxfill_ring()
+ *	Configure one RxFill ring
+ */
+static void edma_configure_rxfill_ring(struct edma_hw *ehw,
+					struct edma_rxfill_ring *rxfill_ring)
+{
+	uint32_t data = 0;
+
+	edma_reg_write(EDMA_REG_RXFILL_BA(rxfill_ring->id),
+			(uint32_t)(rxfill_ring->dma & EDMA_RING_DMA_MASK));
+
+	data = rxfill_ring->count & EDMA_RXFILL_RING_SIZE_MASK;
+	edma_reg_write(EDMA_REG_RXFILL_RING_SIZE(rxfill_ring->id), data);
+
+	/*
+	 * Alloc Rx buffers
+	 */
+	edma_alloc_rx_buffer(ehw, rxfill_ring);
+}
+
+/*
+ * edma_configure_rings()
+ *	Configure EDMA rings
+ */
+static void edma_configure_rings(struct edma_hw *ehw)
+{
+	int i = 0;
+
+	/*
+	 * Initialize the store
+	 */
+	for (i = 0; i < EDMA_RING_SIZE; i++) {
+		ehw->tx_skb_store[i] = NULL;
+		ehw->rx_skb_store[i] = NULL;
+	}
+
+	/*
+	 * Configure TXDESC ring
+	 */
+	for (i = 0; i < ehw->txdesc_rings; i++)
+		edma_configure_txdesc_ring(ehw, &ehw->txdesc_ring[i]);
+
+	/*
+	 * Configure TXCMPL ring
+	 */
+	for (i = 0; i < ehw->txcmpl_rings; i++)
+		edma_configure_txcmpl_ring(ehw, &ehw->txcmpl_ring[i]);
+
+	/*
+	 * Configure RXFILL rings
+	 */
+	for (i = 0; i < ehw->rxfill_rings; i++)
+		edma_configure_rxfill_ring(ehw, &ehw->rxfill_ring[i]);
+
+	/*
+	 * Configure RXDESC ring
+	 */
+	for (i = 0; i < ehw->rxdesc_rings; i++)
+		edma_configure_rxdesc_ring(ehw, &ehw->rxdesc_ring[i]);
+}
+
+/*
+ * edma_hw_reset()
+ *	Reset EDMA Hardware during initialization
+ */
+int edma_hw_reset(struct edma_hw *ehw)
+{
+	struct reset_control *rst;
+	struct platform_device *pdev = ehw->pdev;
+
+	rst = devm_reset_control_get(&pdev->dev, EDMA_HW_RESET_ID);
+	if (IS_ERR(rst)) {
+		pr_warn("DTS Node: %s does not exist\n", EDMA_HW_RESET_ID);
+		return -EINVAL;
+	}
+
+	reset_control_assert(rst);
+	udelay(100);
+
+	reset_control_deassert(rst);
+	udelay(100);
+
+	pr_info("EDMA HW Reset completed succesfully\n");
+
+	return 0;
+}
+
+/*
+ * edma_hw_init()
+ *	EDMA hw init
+ */
+int edma_hw_init(struct edma_hw *ehw)
+{
+	int ret = 0;
+	int desc_index;
+	uint32_t i, data, reg = 0;
+	struct edma_rxdesc_ring *rxdesc_ring = NULL;
+
+	data = edma_reg_read(EDMA_REG_MAS_CTRL);
+	pr_info("EDMA ver %d hw init\n", data);
+
+	/*
+	 * Setup private data structure
+	 */
+	ehw->misc_intr_mask = 0x0;
+	ehw->rxfill_intr_mask = EDMA_RXFILL_INT_MASK;
+	ehw->rxdesc_intr_mask = EDMA_RXDESC_INT_MASK_PKT_INT;
+	ehw->txcmpl_intr_mask = EDMA_TX_INT_MASK_PKT_INT |
+				EDMA_TX_INT_MASK_UGT_INT;
+	ehw->rx_payload_offset = EDMA_RX_PREHDR_SIZE;
+	ehw->active = 0;
+	ehw->edma_initialized = false;
+	ehw->rx_alloc_size = dp_global_ctx.rx_buf_size;
+
+	/* Reset EDMA */
+	ret = edma_hw_reset(ehw);
+	if (ret)
+		return ret;
+
+	/*
+	 * Disable interrupts
+	 */
+	for (i = 0; i < EDMA_MAX_TXCMPL_RINGS; i++)
+		edma_reg_write(EDMA_REG_TX_INT_MASK(i), 0);
+
+	for (i = 0; i < EDMA_MAX_RXFILL_RINGS; i++)
+		edma_reg_write(EDMA_REG_RXFILL_INT_MASK(i), 0);
+
+	for (i = 0; i < EDMA_MAX_RXDESC_RINGS; i++)
+		edma_reg_write(EDMA_REG_RX_INT_CTRL(i), 0);
+
+	/*
+	 * Disable Rx rings
+	 */
+	for (i = 0; i < EDMA_MAX_RXDESC_RINGS; i++) {
+		data = edma_reg_read(EDMA_REG_RXDESC_CTRL(i));
+		data &= ~EDMA_RXDESC_RX_EN;
+		edma_reg_write(EDMA_REG_RXDESC_CTRL(i), data);
+	}
+
+	/*
+	 * Disable RxFill Rings
+	 */
+	for (i = 0; i < EDMA_MAX_RXFILL_RINGS; i++) {
+		data = edma_reg_read(EDMA_REG_RXFILL_RING_EN(i));
+		data &= ~EDMA_RXFILL_RING_EN;
+		edma_reg_write(EDMA_REG_RXFILL_RING_EN(i), data);
+	}
+
+	/*
+	 * Disable Tx rings
+	 */
+	for (desc_index = 0; desc_index < EDMA_MAX_TXDESC_RINGS; desc_index++) {
+		data = edma_reg_read(EDMA_REG_TXDESC_CTRL(desc_index));
+		data &= ~EDMA_TXDESC_TX_EN;
+		edma_reg_write(EDMA_REG_TXDESC_CTRL(desc_index), data);
+	}
+
+#if defined(NSS_DP_IPQ807X)
+	/*
+	 * Clear the TXDESC2CMPL_MAP_xx reg before setting up
+	 * the mapping. This register holds TXDESC to TXFILL ring
+	 * mapping.
+	 */
+	edma_reg_write(EDMA_REG_TXDESC2CMPL_MAP_0, 0);
+	edma_reg_write(EDMA_REG_TXDESC2CMPL_MAP_1, 0);
+	edma_reg_write(EDMA_REG_TXDESC2CMPL_MAP_2, 0);
+	desc_index = ehw->txcmpl_ring_start;
+
+	/*
+	 * 3 registers to hold the completion mapping for total 24
+	 * TX desc rings (0-9,10-19 and rest). In each entry 3 bits hold
+	 * the mapping for a particular TX desc ring.
+	 */
+	for (i = ehw->txdesc_ring_start;
+		i < ehw->txdesc_ring_end; i++) {
+		if (i >= 0 && i <= 9)
+			reg = EDMA_REG_TXDESC2CMPL_MAP_0;
+		else if (i >= 10 && i <= 19)
+			reg = EDMA_REG_TXDESC2CMPL_MAP_1;
+		else
+			reg = EDMA_REG_TXDESC2CMPL_MAP_2;
+
+		pr_debug("Configure TXDESC:%u to use TXCMPL:%u\n",
+				i, desc_index);
+
+		data = edma_reg_read(reg);
+		data |= (desc_index & 0x7) << ((i % 10) * 3);
+		edma_reg_write(reg, data);
+
+		desc_index++;
+		if (desc_index == ehw->txcmpl_ring_end)
+				desc_index = ehw->txcmpl_ring_start;
+	}
+#endif
+
+	/*
+	 * Set PPE QID to EDMA Rx ring mapping.
+	 * When coming up use only queue 0.
+	 * HOST EDMA rings. FW EDMA comes up and overwrites as required.
+	 * Each entry can hold mapping for 8 PPE queues and entry size is
+	 * 4 bytes
+	 */
+	desc_index = ehw->rxdesc_ring_start;
+	data = 0;
+	data |= (desc_index & 0xF);
+	edma_reg_write(EDMA_QID2RID_TABLE_MEM(0), data);
+	pr_debug("Configure QID2RID reg:0x%x to 0x%x\n", reg, data);
+
+	ret = edma_init_rings(ehw);
+	if (ret)
+		return ret;
+
+	edma_configure_rings(ehw);
+
+	/*
+	 * Set RXDESC2FILL_MAP_xx reg.
+	 * There are two registers RXDESC2FILL_0 and RXDESC2FILL_1
+	 * 3 bits holds the rx fill ring mapping for each of the
+	 * rx descriptor ring.
+	 */
+	edma_reg_write(EDMA_REG_RXDESC2FILL_MAP_0, 0);
+	edma_reg_write(EDMA_REG_RXDESC2FILL_MAP_1, 0);
+	for (i = ehw->rxdesc_ring_start;
+			i < ehw->rxdesc_ring_end; i++) {
+		if ((i >= 0) && (i <= 9))
+			reg = EDMA_REG_RXDESC2FILL_MAP_0;
+		else
+			reg = EDMA_REG_RXDESC2FILL_MAP_1;
+
+		rxdesc_ring = &ehw->rxdesc_ring[i - ehw->rxdesc_ring_start];
+
+		pr_debug("Configure RXDESC:%u to use RXFILL:%u\n",
+				rxdesc_ring->id, rxdesc_ring->rxfill->id);
+
+		data = edma_reg_read(reg);
+		data |= (rxdesc_ring->rxfill->id & 0x7) << ((i % 10) * 3);
+		edma_reg_write(reg, data);
+	}
+
+	reg = EDMA_REG_RXDESC2FILL_MAP_0;
+	pr_debug("EDMA_REG_RXDESC2FILL_MAP_0: 0x%x\n", edma_reg_read(reg));
+	reg = EDMA_REG_RXDESC2FILL_MAP_1;
+	pr_debug("EDMA_REG_RXDESC2FILL_MAP_1: 0x%x\n", edma_reg_read(reg));
+
+#if defined(NSS_DP_IPQ807X)
+	reg = EDMA_REG_TXDESC2CMPL_MAP_0;
+	pr_debug("EDMA_REG_TXDESC2CMPL_MAP_0: 0x%x\n", edma_reg_read(reg));
+	reg = EDMA_REG_TXDESC2CMPL_MAP_1;
+	pr_debug("EDMA_REG_TXDESC2CMPL_MAP_1: 0x%x\n", edma_reg_read(reg));
+	reg = EDMA_REG_TXDESC2CMPL_MAP_2;
+	pr_debug("EDMA_REG_TXDESC2CMPL_MAP_2: 0x%x\n", edma_reg_read(reg));
+#endif
+
+	/*
+	 * Configure DMA request priority, DMA read burst length,
+	 * and AXI write size.
+	 */
+	data = EDMA_DMAR_BURST_LEN_SET(EDMA_BURST_LEN_ENABLE)
+		| EDMA_DMAR_REQ_PRI_SET(0)
+		| EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SET(31)
+		| EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SET(7)
+		| EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SET(7);
+	edma_reg_write(EDMA_REG_DMAR_CTRL, data);
+#if defined(NSS_DP_IPQ60XX)
+	data = edma_reg_read(EDMA_REG_AXIW_CTRL);
+	data |= EDMA_AXIW_MAX_WR_SIZE_EN;
+	edma_reg_write(EDMA_REG_AXIW_CTRL, data);
+#endif
+
+	/*
+	 * Misc error mask
+	 */
+	data = EDMA_MISC_AXI_RD_ERR_MASK_EN |
+		EDMA_MISC_AXI_WR_ERR_MASK_EN |
+		EDMA_MISC_RX_DESC_FIFO_FULL_MASK_EN |
+		EDMA_MISC_RX_ERR_BUF_SIZE_MASK_EN |
+		EDMA_MISC_TX_SRAM_FULL_MASK_EN |
+		EDMA_MISC_TX_CMPL_BUF_FULL_MASK_EN |
+		EDMA_MISC_DATA_LEN_ERR_MASK_EN;
+#if defined(NSS_DP_IPQ807X)
+	data |= EDMA_MISC_PKT_LEN_LA_64K_MASK_EN |
+		 EDMA_MISC_PKT_LEN_LE_40_MASK_EN;
+#else
+	data |= EDMA_MISC_TX_TIMEOUT_MASK_EN;
+#endif
+	edma_reg_write(EDMA_REG_MISC_INT_MASK, data);
+
+	/*
+	 * Global EDMA enable and padding enable
+	 */
+	data = EDMA_PORT_PAD_EN | EDMA_PORT_EDMA_EN;
+	edma_reg_write(EDMA_REG_PORT_CTRL, data);
+
+	/*
+	 * Enable Rx rings
+	 */
+	for (i = ehw->rxdesc_ring_start; i < ehw->rxdesc_ring_end; i++) {
+		data = edma_reg_read(EDMA_REG_RXDESC_CTRL(i));
+		data |= EDMA_RXDESC_RX_EN;
+		edma_reg_write(EDMA_REG_RXDESC_CTRL(i), data);
+	}
+
+	for (i = ehw->rxfill_ring_start; i < ehw->rxfill_ring_end; i++) {
+		data = edma_reg_read(EDMA_REG_RXFILL_RING_EN(i));
+		data |= EDMA_RXFILL_RING_EN;
+		edma_reg_write(EDMA_REG_RXFILL_RING_EN(i), data);
+	}
+
+	/*
+	 * Enable Tx rings
+	 */
+	for (i = ehw->txdesc_ring_start; i < ehw->txdesc_ring_end; i++) {
+		data = edma_reg_read(EDMA_REG_TXDESC_CTRL(i));
+		data |= EDMA_TXDESC_TX_EN;
+		edma_reg_write(EDMA_REG_TXDESC_CTRL(i), data);
+	}
+
+	ehw->edma_initialized = true;
+
+	return 0;
+}
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c
new file mode 100644
index 0000000..56c780f
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c
@@ -0,0 +1,899 @@
+/*
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/debugfs.h>
+#include <linux/netdevice.h>
+#include <fal/fal_vsi.h>
+#include "edma_data_plane.h"
+#include "edma_regs.h"
+#include "nss_dp_api_if.h"
+#include "nss_dp_dev.h"
+
+/*
+ * EDMA hardware instance
+ */
+struct edma_hw edma_hw;
+
+/*
+ * edma_reg_read()
+ *	Read EDMA register
+ */
+uint32_t edma_reg_read(uint32_t reg_off)
+{
+	return hal_read_reg(edma_hw.reg_base, reg_off);
+}
+
+/*
+ * edma_reg_write()
+ *	Write EDMA register
+ */
+void edma_reg_write(uint32_t reg_off, uint32_t val)
+{
+	hal_write_reg(edma_hw.reg_base, reg_off, val);
+}
+
+/*
+ * edma_disable_interrupts()
+ *	Disable EDMA RX/TX interrupt masks.
+ */
+static void edma_disable_interrupts(void)
+{
+	struct edma_rxdesc_ring *rxdesc_ring = NULL;
+	struct edma_rxfill_ring *rxfill_ring = NULL;
+	struct edma_txcmpl_ring *txcmpl_ring = NULL;
+	int i;
+
+	for (i = 0; i < edma_hw.rxdesc_rings; i++) {
+		rxdesc_ring = &edma_hw.rxdesc_ring[i];
+		edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id),
+			       EDMA_MASK_INT_CLEAR);
+	}
+
+	for (i = 0; i < edma_hw.txcmpl_rings; i++) {
+		txcmpl_ring = &edma_hw.txcmpl_ring[i];
+		edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id),
+			       EDMA_MASK_INT_CLEAR);
+	}
+
+	for (i = 0; i < edma_hw.rxfill_rings; i++) {
+		rxfill_ring = &edma_hw.rxfill_ring[i];
+		edma_reg_write(EDMA_REG_RXFILL_INT_MASK(rxfill_ring->id),
+			       EDMA_MASK_INT_CLEAR);
+	}
+
+	/*
+	 * Clear MISC interrupt mask.
+	 */
+	edma_reg_write(EDMA_REG_MISC_INT_MASK, EDMA_MASK_INT_CLEAR);
+}
+
+/*
+ * edma_enable_interrupts()
+ *	Enable RX/TX EDMA interrupt masks.
+ */
+static void edma_enable_interrupts(void)
+{
+	struct edma_rxdesc_ring *rxdesc_ring = NULL;
+	struct edma_rxfill_ring *rxfill_ring = NULL;
+	struct edma_txcmpl_ring *txcmpl_ring = NULL;
+	int i;
+
+	for (i = 0; i < edma_hw.rxfill_rings; i++) {
+		rxfill_ring = &edma_hw.rxfill_ring[i];
+		edma_reg_write(EDMA_REG_RXFILL_INT_MASK(rxfill_ring->id),
+				edma_hw.rxfill_intr_mask);
+	}
+
+	for (i = 0; i < edma_hw.txcmpl_rings; i++) {
+		txcmpl_ring = &edma_hw.txcmpl_ring[i];
+		edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id),
+				edma_hw.txcmpl_intr_mask);
+	}
+
+	for (i = 0; i < edma_hw.rxdesc_rings; i++) {
+		rxdesc_ring = &edma_hw.rxdesc_ring[i];
+		edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id),
+				edma_hw.rxdesc_intr_mask);
+	}
+
+	/*
+	 * Enable MISC interrupt mask.
+	 */
+	edma_reg_write(EDMA_REG_MISC_INT_MASK, edma_hw.misc_intr_mask);
+}
+
+/*
+ * edma_disable_port()
+ * 	EDMA disable port
+ */
+static void edma_disable_port(void)
+{
+	edma_reg_write(EDMA_REG_PORT_CTRL, EDMA_DISABLE);
+}
+
+/*
+ * edma_of_get_pdata()
+ *	Read the device tree details for EDMA
+ */
+static int edma_of_get_pdata(struct resource *edma_res)
+{
+	/*
+	 * Find EDMA node in device tree
+	 */
+	edma_hw.device_node = of_find_node_by_name(NULL,
+				EDMA_DEVICE_NODE_NAME);
+	if (!edma_hw.device_node) {
+		pr_warn("EDMA device tree node (%s) not found\n",
+				EDMA_DEVICE_NODE_NAME);
+		return -EINVAL;
+	}
+
+	/*
+	 * Get EDMA device node
+	 */
+	edma_hw.pdev = of_find_device_by_node(edma_hw.device_node);
+	if (!edma_hw.pdev) {
+		pr_warn("Platform device for node %px(%s) not found\n",
+				edma_hw.device_node,
+				(edma_hw.device_node)->name);
+		return -EINVAL;
+	}
+
+	/*
+	 * Get EDMA register resource
+	 */
+	if (of_address_to_resource(edma_hw.device_node, 0, edma_res) != 0) {
+		pr_warn("Unable to get register address for edma device: "
+			  EDMA_DEVICE_NODE_NAME"\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Get id of first TXDESC ring
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,txdesc-ring-start",
+				      &edma_hw.txdesc_ring_start) != 0) {
+		pr_warn("Read error 1st TXDESC ring (txdesc_ring_start)\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Get number of TXDESC rings
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,txdesc-rings",
+				 &edma_hw.txdesc_rings) != 0) {
+		pr_warn("Unable to read number of txdesc rings.\n");
+		return -EINVAL;
+	}
+	edma_hw.txdesc_ring_end = edma_hw.txdesc_ring_start +
+					edma_hw.txdesc_rings;
+
+	/*
+	 * Get id of first TXCMPL ring
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,txcmpl-ring-start",
+				&edma_hw.txcmpl_ring_start) != 0) {
+		pr_warn("Read error 1st TXCMPL ring (txcmpl_ring_start)\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Get number of TXCMPL rings
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,txcmpl-rings",
+				&edma_hw.txcmpl_rings) != 0) {
+		pr_warn("Unable to read number of txcmpl rings.\n");
+		return -EINVAL;
+	}
+	edma_hw.txcmpl_ring_end = edma_hw.txcmpl_ring_start +
+					edma_hw.txcmpl_rings;
+
+	/*
+	 * Get id of first RXFILL ring
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,rxfill-ring-start",
+				      &edma_hw.rxfill_ring_start) != 0) {
+		pr_warn("Read error 1st RXFILL ring (rxfill-ring-start)\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Get number of RXFILL rings
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,rxfill-rings",
+					&edma_hw.rxfill_rings) != 0) {
+		pr_warn("Unable to read number of rxfill rings.\n");
+		return -EINVAL;
+	}
+	edma_hw.rxfill_ring_end = edma_hw.rxfill_ring_start +
+					edma_hw.rxfill_rings;
+
+	/*
+	 * Get id of first RXDESC ring
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,rxdesc-ring-start",
+				      &edma_hw.rxdesc_ring_start) != 0) {
+		pr_warn("Read error 1st RXDESC ring (rxdesc-ring-start)\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Get number of RXDESC rings
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,rxdesc-rings",
+					&edma_hw.rxdesc_rings) != 0) {
+		pr_warn("Unable to read number of rxdesc rings.\n");
+		return -EINVAL;
+	}
+	edma_hw.rxdesc_ring_end = edma_hw.rxdesc_ring_start +
+					edma_hw.rxdesc_rings;
+
+	return 0;
+}
+
+/*
+ * edma_init()
+ *	EDMA init
+ */
+int edma_init(void)
+{
+	int ret = 0;
+	struct resource res_edma;
+
+	/*
+	 * Get all the DTS data needed
+	 */
+	if (edma_of_get_pdata(&res_edma) < 0) {
+		pr_warn("Unable to get EDMA DTS data.\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Request memory region for EDMA registers
+	 */
+	edma_hw.reg_resource = request_mem_region(res_edma.start,
+				resource_size(&res_edma),
+				EDMA_DEVICE_NODE_NAME);
+	if (!edma_hw.reg_resource) {
+		pr_warn("Unable to request EDMA register memory.\n");
+		return -EFAULT;
+	}
+
+	/*
+	 * Remap register resource
+	 */
+	edma_hw.reg_base = ioremap_nocache((edma_hw.reg_resource)->start,
+				resource_size(edma_hw.reg_resource));
+	if (!edma_hw.reg_base) {
+		pr_warn("Unable to remap EDMA register memory.\n");
+		ret = -EFAULT;
+		goto edma_init_remap_fail;
+	}
+
+	if (edma_hw_init(&edma_hw) != 0) {
+		ret = -EFAULT;
+		goto edma_init_hw_init_fail;
+	}
+
+	platform_set_drvdata(edma_hw.pdev, (void *)&edma_hw);
+
+	edma_hw.napi_added = 0;
+
+	return 0;
+
+edma_init_hw_init_fail:
+	iounmap(edma_hw.reg_base);
+
+edma_init_remap_fail:
+	release_mem_region((edma_hw.reg_resource)->start,
+			   resource_size(edma_hw.reg_resource));
+	return ret;
+}
+
+/*
+ * edma_cleanup()
+ *	EDMA cleanup
+ */
+void edma_cleanup(bool is_dp_override)
+{
+	int i;
+	struct edma_txcmpl_ring *txcmpl_ring = NULL;
+	struct edma_rxdesc_ring *rxdesc_ring = NULL;
+
+	/*
+	 * The cleanup can happen from data plane override
+	 * or from module_exit, we want to cleanup only once
+	 */
+	if (!edma_hw.edma_initialized) {
+		/*
+		 * Disable EDMA only at module exit time, since NSS firmware
+		 * depends on this setting.
+		 */
+		if (!is_dp_override) {
+			edma_disable_port();
+		}
+		return;
+	}
+
+	/*
+	 * Disable Rx rings used by this driver
+	 */
+	for (i = edma_hw.rxdesc_ring_start; i < edma_hw.rxdesc_ring_end; i++)
+		edma_reg_write(EDMA_REG_RXDESC_CTRL(i), EDMA_RING_DISABLE);
+
+	/*
+	 * Disable Tx rings used by this driver
+	 */
+	for (i = edma_hw.txdesc_ring_start; i < edma_hw.txdesc_ring_end; i++) {
+		txcmpl_ring = &edma_hw.txcmpl_ring[i];
+		edma_reg_write(EDMA_REG_TXDESC_CTRL(i),
+				EDMA_RING_DISABLE);
+	}
+
+	/*
+	 * Disable RxFill Rings used by this driver
+	 */
+	for (i = edma_hw.rxfill_ring_start; i < edma_hw.rxfill_ring_end; i++)
+		edma_reg_write(EDMA_REG_RXFILL_RING_EN(i), EDMA_RING_DISABLE);
+
+	/*
+	 * Clear interrupt mask
+	 */
+	for (i = 0; i < edma_hw.rxdesc_rings; i++) {
+		rxdesc_ring = &edma_hw.rxdesc_ring[i];
+		edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id),
+			       EDMA_MASK_INT_CLEAR);
+	}
+
+	for (i = 0; i < edma_hw.txcmpl_rings; i++) {
+		txcmpl_ring = &edma_hw.txcmpl_ring[i];
+		edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id),
+			       EDMA_MASK_INT_CLEAR);
+	}
+
+	edma_reg_write(EDMA_REG_MISC_INT_MASK, EDMA_MASK_INT_CLEAR);
+
+	/*
+	 * Remove interrupt handlers and NAPI
+	 */
+	if (edma_hw.napi_added) {
+		/*
+		 * Free IRQ for TXCMPL rings
+		 */
+		for (i = 0; i < edma_hw.txcmpl_rings; i++) {
+			synchronize_irq(edma_hw.txcmpl_intr[i]);
+			free_irq(edma_hw.txcmpl_intr[i],
+					(void *)(edma_hw.pdev));
+		}
+
+		/*
+		 * Free IRQ for RXFILL rings
+		 */
+		for (i = 0; i < edma_hw.rxfill_rings; i++) {
+			synchronize_irq(edma_hw.rxfill_intr[i]);
+			free_irq(edma_hw.rxfill_intr[i],
+					(void *)(edma_hw.pdev));
+		}
+
+		/*
+		 * Free IRQ for RXDESC rings
+		 */
+		for (i = 0; i < edma_hw.rxdesc_rings; i++) {
+			synchronize_irq(edma_hw.rxdesc_intr[i]);
+			free_irq(edma_hw.rxdesc_intr[i],
+					(void *)(edma_hw.pdev));
+		}
+
+		/*
+		 * Free Misc IRQ
+		 */
+		synchronize_irq(edma_hw.misc_intr);
+		free_irq(edma_hw.misc_intr, (void *)(edma_hw.pdev));
+
+		netif_napi_del(&edma_hw.napi);
+		edma_hw.napi_added = 0;
+	}
+
+	/*
+	 * Disable EDMA only at module exit time, since NSS firmware
+	 * depends on this setting.
+	 */
+	if (!is_dp_override) {
+		edma_disable_port();
+	}
+
+	/*
+	 * cleanup rings and free
+	 */
+	edma_cleanup_rings(&edma_hw);
+	iounmap(edma_hw.reg_base);
+	release_mem_region((edma_hw.reg_resource)->start,
+			   resource_size(edma_hw.reg_resource));
+
+	/*
+	 * Mark initialize false, so that we do not
+	 * try to cleanup again
+	 */
+	edma_hw.edma_initialized = false;
+}
+
+/*
+ * nss_dp_edma_if_open()
+ *	Do slow path data plane open
+ */
+static int edma_if_open(struct nss_dp_data_plane_ctx *dpc,
+			uint32_t tx_desc_ring, uint32_t rx_desc_ring,
+			uint32_t mode)
+{
+	if (!dpc->dev)
+		return NSS_DP_FAILURE;
+
+	/*
+	 * Enable NAPI
+	 */
+	if (edma_hw.active++ != 0)
+		return NSS_DP_SUCCESS;
+
+	napi_enable(&edma_hw.napi);
+
+	/*
+	 * Enable the interrupt masks.
+	 */
+	edma_enable_interrupts();
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_if_close()
+ *	Do slow path data plane close
+ */
+static int edma_if_close(struct nss_dp_data_plane_ctx *dpc)
+{
+	if (--edma_hw.active != 0)
+		return NSS_DP_SUCCESS;
+
+	/*
+	 * Disable the interrupt masks.
+	 */
+	edma_disable_interrupts();
+
+	/*
+	 * Disable NAPI
+	 */
+	napi_disable(&edma_hw.napi);
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_if_link_state()
+ */
+static int edma_if_link_state(struct nss_dp_data_plane_ctx *dpc,
+			      uint32_t link_state)
+{
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_if_mac_addr()
+ */
+static int edma_if_mac_addr(struct nss_dp_data_plane_ctx *dpc, uint8_t *addr)
+{
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_if_change_mtu()
+ */
+static int edma_if_change_mtu(struct nss_dp_data_plane_ctx *dpc, uint32_t mtu)
+{
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_if_xmit()
+ *	Transmit a packet using EDMA
+ */
+static netdev_tx_t edma_if_xmit(struct nss_dp_data_plane_ctx *dpc,
+				struct sk_buff *skb)
+{
+	struct net_device *netdev = dpc->dev;
+	int ret;
+	uint32_t tx_ring, skbq, nhead, ntail;
+	bool expand_skb = false;
+
+	if (skb->len < ETH_HLEN) {
+		netdev_dbg(netdev, "skb->len < ETH_HLEN\n");
+		goto drop;
+	}
+
+	/*
+	 * Select a Tx ring
+	 */
+	skbq = skb_get_queue_mapping(skb);
+	tx_ring = 0;
+	if ((edma_hw.txdesc_rings > 1) && (skbq > 0))
+		tx_ring = edma_hw.txdesc_rings % skbq;
+
+	/*
+	 * Check for non-linear skb
+	 */
+	if (skb_is_nonlinear(skb)) {
+		netdev_dbg(netdev, "cannot Tx non-linear skb:%px\n", skb);
+		goto drop;
+	}
+
+	/*
+	 * Check for headroom/tailroom and clone
+	 */
+	nhead = netdev->needed_headroom;
+	ntail = netdev->needed_tailroom;
+
+	if (skb_cloned(skb) ||
+		(skb_headroom(skb) < nhead) ||
+		(skb_headroom(skb) < ntail)) {
+		expand_skb = true;
+	}
+
+	/*
+	 * Expand the skb. This also unclones a cloned skb.
+	 */
+	if (expand_skb && pskb_expand_head(skb, nhead, ntail, GFP_ATOMIC)) {
+		netdev_dbg(netdev, "cannot expand skb:%px\n", skb);
+		goto drop;
+	}
+
+	/*
+	 * Transmit the packet
+	 */
+	ret = edma_ring_xmit(&edma_hw, netdev, skb,
+			&edma_hw.txdesc_ring[tx_ring]);
+	if (ret == EDMA_TX_OK)
+		return NETDEV_TX_OK;
+
+	/*
+	 * Not enough descriptors. Stop netdev Tx queue.
+	 */
+	if (ret == EDMA_TX_DESC) {
+		netif_stop_queue(netdev);
+		return NETDEV_TX_BUSY;
+	}
+
+drop:
+	dev_kfree_skb_any(skb);
+	netdev->stats.tx_dropped++;
+
+	return NETDEV_TX_OK;
+}
+
+/*
+ * edma_if_set_features()
+ *	Set the supported net_device features
+ */
+static void edma_if_set_features(struct nss_dp_data_plane_ctx *dpc)
+{
+	/*
+	 * TODO - add flags to support HIGHMEM/cksum offload VLAN
+	 * the features are enabled.
+	 */
+}
+
+/* TODO - check if this is needed */
+/*
+ * edma_if_pause_on_off()
+ *	Set pause frames on or off
+ *
+ * No need to send a message if we defaulted to slow path.
+ */
+static int edma_if_pause_on_off(struct nss_dp_data_plane_ctx *dpc,
+				uint32_t pause_on)
+{
+	return NSS_DP_SUCCESS;
+}
+
+#ifdef CONFIG_RFS_ACCEL
+/*
+ * edma_if_rx_flow_steer()
+ *	Flow steer of the data plane
+ *
+ * Initial receive flow steering function for data plane operation.
+ */
+static int edma_if_rx_flow_steer(struct nss_dp_data_plane_ctx *dpc, struct sk_buff *skb,
+					uint32_t cpu, bool is_add)
+{
+	return NSS_DP_SUCCESS;
+}
+#endif
+
+/*
+ * edma_if_deinit()
+ *	Free edma resources
+ */
+static int edma_if_deinit(struct nss_dp_data_plane_ctx *dpc)
+{
+	/*
+	 * Free up resources used by EDMA if all the
+	 * interfaces have been overridden
+	 * */
+	if (edma_hw.dp_override_cnt == EDMA_MAX_GMACS - 1) {
+		edma_cleanup(true);
+	} else {
+		edma_hw.dp_override_cnt++;
+	}
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_irq_init()
+ *	Initialize interrupt handlers for the driver
+ */
+static int edma_irq_init(void)
+{
+	int err;
+	uint32_t entry_num, i;
+
+	/*
+	 * Get TXCMPL rings IRQ numbers
+	 */
+	entry_num = 0;
+	for (i = 0; i < edma_hw.txcmpl_rings; i++, entry_num++) {
+		edma_hw.txcmpl_intr[i] =
+			platform_get_irq(edma_hw.pdev, entry_num);
+		if (edma_hw.txcmpl_intr[i] < 0) {
+			pr_warn("%s: txcmpl_intr[%u] irq get failed\n",
+					(edma_hw.device_node)->name, i);
+			return -1;
+		}
+
+		pr_debug("%s: txcmpl_intr[%u] = %u\n",
+				 (edma_hw.device_node)->name,
+				 i, edma_hw.txcmpl_intr[i]);
+	}
+
+	/*
+	 * Get RXFILL rings IRQ numbers
+	 */
+	for (i = 0; i < edma_hw.rxfill_rings; i++, entry_num++) {
+		edma_hw.rxfill_intr[i] =
+			platform_get_irq(edma_hw.pdev, entry_num);
+		if (edma_hw.rxfill_intr[i] < 0) {
+			pr_warn("%s: rxfill_intr[%u] irq get failed\n",
+					(edma_hw.device_node)->name, i);
+			return -1;
+		}
+
+		pr_debug("%s: rxfill_intr[%u] = %u\n",
+				 (edma_hw.device_node)->name,
+				 i, edma_hw.rxfill_intr[i]);
+	}
+
+	/*
+	 * Get RXDESC rings IRQ numbers
+	 *
+	 */
+	for (i = 0; i < edma_hw.rxdesc_rings; i++, entry_num++) {
+		edma_hw.rxdesc_intr[i] =
+			platform_get_irq(edma_hw.pdev, entry_num);
+		if (edma_hw.rxdesc_intr[i] < 0) {
+			pr_warn("%s: rxdesc_intr[%u] irq get failed\n",
+					(edma_hw.device_node)->name, i);
+			return -1;
+		}
+
+		pr_debug("%s: rxdesc_intr[%u] = %u\n",
+				 (edma_hw.device_node)->name,
+				 i, edma_hw.rxdesc_intr[i]);
+	}
+
+	/*
+	 * Get misc IRQ number
+	 */
+	edma_hw.misc_intr = platform_get_irq(edma_hw.pdev, entry_num);
+	pr_debug("%s: misc IRQ:%u\n",
+			  (edma_hw.device_node)->name,
+			  edma_hw.misc_intr);
+
+	/*
+	 * Request IRQ for TXCMPL rings
+	 */
+	for (i = 0; i < edma_hw.txcmpl_rings; i++) {
+		err = request_irq(edma_hw.txcmpl_intr[i],
+				  edma_handle_irq, IRQF_SHARED,
+				  "edma_txcmpl", (void *)edma_hw.pdev);
+		if (err) {
+			pr_debug("TXCMPL ring IRQ:%d request failed\n",
+					edma_hw.txcmpl_intr[i]);
+			return -1;
+
+		}
+	}
+
+	/*
+	 * Request IRQ for RXFILL rings
+	 */
+	for (i = 0; i < edma_hw.rxfill_rings; i++) {
+		err = request_irq(edma_hw.rxfill_intr[i],
+				  edma_handle_irq, IRQF_SHARED,
+				  "edma_rxfill", (void *)edma_hw.pdev);
+		if (err) {
+			pr_debug("RXFILL ring IRQ:%d request failed\n",
+					edma_hw.rxfill_intr[i]);
+			goto rx_fill_ring_intr_req_fail;
+		}
+	}
+
+	/*
+	 * Request IRQ for RXDESC rings
+	 */
+	for (i = 0; i < edma_hw.rxdesc_rings; i++) {
+		err = request_irq(edma_hw.rxdesc_intr[i],
+				  edma_handle_irq, IRQF_SHARED,
+				  "edma_rxdesc", (void *)edma_hw.pdev);
+		if (err) {
+			pr_debug("RXDESC ring IRQ:%d request failed\n",
+					edma_hw.rxdesc_intr[i]);
+			goto rx_desc_ring_intr_req_fail;
+		}
+	}
+
+	/*
+	 * Request Misc IRQ
+	 */
+	err = request_irq(edma_hw.misc_intr, edma_handle_misc_irq,
+			  IRQF_SHARED, "edma_misc",
+			  (void *)edma_hw.pdev);
+	if (err) {
+		pr_debug("MISC IRQ:%d request failed\n",
+				edma_hw.misc_intr);
+		goto misc_intr_req_fail;
+	}
+
+	return 0;
+
+misc_intr_req_fail:
+
+	/*
+	 * Free IRQ for RXDESC rings
+	 */
+	for (i = 0; i < edma_hw.rxdesc_rings; i++) {
+		synchronize_irq(edma_hw.rxdesc_intr[i]);
+		free_irq(edma_hw.rxdesc_intr[i],
+				(void *)&(edma_hw.pdev)->dev);
+	}
+
+rx_desc_ring_intr_req_fail:
+
+	/*
+	 * Free IRQ for RXFILL rings
+	 */
+	for (i = 0; i < edma_hw.rxfill_rings; i++) {
+		synchronize_irq(edma_hw.rxfill_intr[i]);
+		free_irq(edma_hw.rxfill_intr[i],
+				(void *)&(edma_hw.pdev)->dev);
+	}
+
+rx_fill_ring_intr_req_fail:
+
+	/*
+	 * Free IRQ for TXCMPL rings
+	 */
+	for (i = 0; i < edma_hw.txcmpl_rings; i++) {
+
+		synchronize_irq(edma_hw.txcmpl_intr[i]);
+		free_irq(edma_hw.txcmpl_intr[i],
+				(void *)&(edma_hw.pdev)->dev);
+	}
+
+	return -1;
+}
+
+/*
+ * edma_register_netdevice()
+ *	Register netdevice with EDMA
+ */
+static int edma_register_netdevice(struct net_device *netdev, uint32_t macid)
+{
+	if (!netdev) {
+		pr_info("nss_dp_edma: Invalid netdev pointer %px\n", netdev);
+		return -EINVAL;
+	}
+
+	if ((macid < EDMA_START_GMACS) || (macid > EDMA_MAX_GMACS)) {
+		netdev_dbg(netdev, "nss_dp_edma: Invalid macid(%d) for %s\n",
+			macid, netdev->name);
+		return -EINVAL;
+	}
+
+	netdev_info(netdev, "nss_dp_edma: Registering netdev %s(qcom-id:%d) with EDMA\n",
+		netdev->name, macid);
+
+	/*
+	 * We expect 'macid' to correspond to ports numbers on
+	 * IPQ807x. These begin from '1' and hence we subtract
+	 * one when using it as an array index.
+	 */
+	edma_hw.netdev_arr[macid - 1] = netdev;
+
+	/*
+	 * NAPI add
+	 */
+	if (!edma_hw.napi_added) {
+		netif_napi_add(netdev, &edma_hw.napi, edma_napi,
+				EDMA_NAPI_WORK);
+		/*
+		 * Register the interrupt handlers and enable interrupts
+		 */
+		if (edma_irq_init() < 0)
+			return -EINVAL;
+
+		edma_hw.napi_added = 1;
+	}
+
+	return 0;
+}
+
+/*
+ * edma_if_init()
+ */
+static int edma_if_init(struct nss_dp_data_plane_ctx *dpc)
+{
+
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *dp_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	int ret = 0;
+
+	/*
+	 * Register the netdev
+	 */
+	ret = edma_register_netdevice(netdev, dp_dev->macid);
+	if (ret) {
+		netdev_dbg(netdev,
+				"Error registering netdevice with EDMA %s\n",
+				netdev->name);
+		return NSS_DP_FAILURE;
+	}
+
+	/*
+	 * Headroom needed for Tx preheader
+	 */
+	netdev->needed_headroom += EDMA_TX_PREHDR_SIZE;
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * nss_dp_edma_ops
+ */
+struct nss_dp_data_plane_ops nss_dp_edma_ops = {
+	.init		= edma_if_init,
+	.open		= edma_if_open,
+	.close		= edma_if_close,
+	.link_state	= edma_if_link_state,
+	.mac_addr	= edma_if_mac_addr,
+	.change_mtu	= edma_if_change_mtu,
+	.xmit		= edma_if_xmit,
+	.set_features	= edma_if_set_features,
+	.pause_on_off	= edma_if_pause_on_off,
+#ifdef CONFIG_RFS_ACCEL
+	.rx_flow_steer	= edma_if_rx_flow_steer,
+#endif
+	.deinit		= edma_if_deinit,
+};
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h
new file mode 100644
index 0000000..0921e96
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h
@@ -0,0 +1,287 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016, 2018-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+*/
+
+#ifndef __NSS_DP_EDMA_DATAPLANE__
+#define __NSS_DP_EDMA_DATAPLANE__
+
+#include <linux/netdevice.h>
+#include <nss_dp_arch.h>
+
+#define EDMA_DEVICE_NODE_NAME		"edma"
+#define EDMA_RX_PREHDR_SIZE		(sizeof(struct edma_rx_preheader))
+#define EDMA_TX_PREHDR_SIZE		(sizeof(struct edma_tx_preheader))
+#define EDMA_RING_SIZE			128
+#define EDMA_NAPI_WORK			100
+#define EDMA_START_GMACS		NSS_DP_HAL_START_IFNUM
+#define EDMA_MAX_GMACS			NSS_DP_HAL_MAX_PORTS
+#define EDMA_TX_PKT_MIN_SIZE		33	/* IPQ807x EDMA needs a minimum packet size of 33 bytes */
+#if defined(NSS_DP_IPQ60XX)
+#define EDMA_MAX_TXCMPL_RINGS		24	/* Max TxCmpl rings */
+#else
+#define EDMA_MAX_TXCMPL_RINGS		8	/* Max TxCmpl rings */
+#endif
+#define EDMA_MAX_RXDESC_RINGS		16	/* Max RxDesc rings */
+#define EDMA_MAX_RXFILL_RINGS		8	/* Max RxFill rings */
+#define EDMA_MAX_TXDESC_RINGS		24	/* Max TxDesc rings */
+#define EDMA_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
+#define EDMA_RXFILL_DESC(R, i) EDMA_GET_DESC(R, i, struct edma_rxfill_desc)
+#define EDMA_RXDESC_DESC(R, i) EDMA_GET_DESC(R, i, struct edma_rxdesc_desc)
+#define EDMA_TXDESC_DESC(R, i) EDMA_GET_DESC(R, i, struct edma_txdesc_desc)
+#define EDMA_RXPH_SRC_INFO_TYPE_GET(rxph)	(((rxph)->src_info >> 8) & 0xf0)
+#define EDMA_RXPH_SERVICE_CODE_GET(rxph)	(((rxph)->rx_pre4) & 0xff)
+
+/*
+ * Tx descriptor
+ */
+struct edma_txdesc_desc {
+	uint32_t buffer_addr;
+		/* buffer address */
+	uint32_t word1;
+		/* more bit, TSO, preheader, pool, offset and length */
+};
+
+/*
+ * TxCmpl descriptor
+ */
+struct edma_txcmpl_desc {
+	uint32_t buffer_addr;	/* buffer address/opaque */
+	uint32_t status;	/* status */
+};
+
+/*
+ * Rx descriptor
+ */
+struct edma_rxdesc_desc {
+	uint32_t buffer_addr;	/* buffer address */
+	uint32_t status;	/* status */
+};
+
+/*
+ * RxFill descriptor
+ */
+struct edma_rxfill_desc {
+	uint32_t buffer_addr;	/* Buffer address */
+	uint32_t word1;		/* opaque_ind and buffer size */
+};
+
+/*
+ * Tx descriptor ring
+ */
+struct edma_txdesc_ring {
+	uint32_t id;			/* TXDESC ring number */
+	void *desc;			/* descriptor ring virtual address */
+	dma_addr_t dma;			/* descriptor ring physical address */
+	spinlock_t tx_lock;		/* Tx ring lock */
+	uint16_t count;			/* number of descriptors */
+};
+
+/*
+ * TxCmpl ring
+ */
+struct edma_txcmpl_ring {
+	uint32_t id;			/* TXCMPL ring number */
+	void *desc;			/* descriptor ring virtual address */
+	dma_addr_t dma;			/* descriptor ring physical address */
+	uint16_t count;			/* number of descriptors in the ring */
+};
+
+/*
+ * RxFill ring
+ */
+struct edma_rxfill_ring {
+	uint32_t id;			/* RXFILL ring number */
+	void *desc;			/* descriptor ring virtual address */
+	dma_addr_t dma;			/* descriptor ring physical address */
+	spinlock_t lock;		/* Rx ring lock */
+	uint16_t count;			/* number of descriptors in the ring */
+};
+
+/*
+ * RxDesc ring
+ */
+struct edma_rxdesc_ring {
+	uint32_t id;			/* RXDESC ring number */
+	struct edma_rxfill_ring *rxfill;	/* RXFILL ring used */
+	void *desc;			/* descriptor ring virtual address */
+	dma_addr_t dma;			/* descriptor ring physical address */
+	uint16_t count;			/* number of descriptors in the ring */
+};
+
+/*
+ * EDMA Tx Preheader
+ */
+struct edma_tx_preheader {
+	uint32_t opaque;   /* Opaque, contains skb pointer */
+	uint16_t src_info; /* Src information */
+	uint16_t dst_info; /* Dest information */
+	uint32_t tx_pre2;  /* SVLAN & CVLAN flag, drop prec, hash value */
+	uint32_t tx_pre3;  /* STAG, CTAG */
+	uint32_t tx_pre4;  /* CPU code, L3 & L4 offset, service code */
+	uint32_t tx_pre5;  /* IP addr index, ACL index */
+	uint32_t tx_pre6;  /* IP payload checksum, copy2cpu, timestamp, dscp */
+	uint32_t tx_pre7;  /* Timestamp, QoS TAG */
+};
+
+/*
+ * EDMA Rx Preheader
+ */
+struct edma_rx_preheader {
+	uint32_t opaque;
+		/* Opaque, contains skb pointer*/
+	uint16_t src_info;
+		/* Src information */
+	uint16_t dst_info;
+		/* Dest information */
+	uint32_t rx_pre2;
+		/* SVLAN & CVLAN flag, drop prec, hash value */
+	uint32_t rx_pre3;
+		/* STAG, CTAG */
+	uint32_t rx_pre4;
+		/* CPU code, L3 & L4 offset, service code */
+	uint32_t rx_pre5;
+		/* IP addr index, ACL index */
+	uint32_t rx_pre6;
+		/* IP payload checksum, copy2cpu, timestamp, dscp */
+	uint32_t rx_pre7;
+		/* Timestamp, QoS TAG */
+};
+
+enum edma_tx {
+	EDMA_TX_OK = 0,		/* Tx success */
+	EDMA_TX_DESC = 1,	/* Not enough descriptors */
+	EDMA_TX_FAIL = 2,	/* Tx failure */
+};
+
+/*
+ * EDMA private data structure
+ */
+struct edma_hw {
+	struct napi_struct napi;
+			/* napi structure */
+	struct net_device *netdev_arr[EDMA_MAX_GMACS];
+			/* netdev for each gmac port */
+	struct device_node *device_node;
+			/* Device tree node */
+	struct platform_device *pdev;
+			/* Platform device */
+	void __iomem *reg_base;
+			/* Base register address */
+	struct resource *reg_resource;
+			/* Memory resource */
+	uint16_t rx_payload_offset;
+			/* start of the payload offset */
+	uint32_t flags;
+			/* internal flags */
+	int active;
+			/* status */
+	int napi_added;
+			/* flag to indicate napi add status */
+
+	/*
+	 * Debugfs entries
+	 */
+	struct dentry *edma_dentry;
+	struct dentry *txdesc_dentry;
+	struct dentry *txcmpl_dentry;
+	struct dentry *rxdesc_dentry;
+
+	/*
+	 * Store for tx and rx skbs
+	 */
+	struct sk_buff *rx_skb_store[EDMA_RING_SIZE];
+	struct sk_buff *tx_skb_store[EDMA_RING_SIZE];
+
+	struct edma_rxfill_ring *rxfill_ring;
+			/* Rx Fill Ring, SW is producer */
+	struct edma_rxdesc_ring *rxdesc_ring;
+			/* Rx Descriptor Ring, SW is consumer */
+	struct edma_txdesc_ring *txdesc_ring;
+			/* Tx Descriptor Ring, SW is producer */
+	struct edma_txcmpl_ring *txcmpl_ring;
+			/* Tx Completion Ring, SW is consumer */
+
+	uint32_t txdesc_rings;
+			/* Number of TxDesc rings */
+	uint32_t txdesc_ring_start;
+			/* Id of first TXDESC ring */
+	uint32_t txdesc_ring_end;
+			/* Id of the last TXDESC ring */
+	uint32_t txcmpl_rings;
+			/* Number of TxCmpl rings */
+	uint32_t txcmpl_ring_start;
+			/* Id of first TXCMPL ring */
+	uint32_t txcmpl_ring_end;
+			/* Id of last TXCMPL ring */
+	uint32_t rxfill_rings;
+			/* Number of RxFill rings */
+	uint32_t rxfill_ring_start;
+			/* Id of first RxFill ring */
+	uint32_t rxfill_ring_end;
+			/* Id of last RxFill ring */
+	uint32_t rxdesc_rings;
+			/* Number of RxDesc rings */
+	uint32_t rxdesc_ring_start;
+			/* Id of first RxDesc ring */
+	uint32_t rxdesc_ring_end;
+			/* Id of last RxDesc ring */
+	uint32_t txcmpl_intr[EDMA_MAX_TXCMPL_RINGS];
+			/* TxCmpl ring IRQ numbers */
+	uint32_t rxfill_intr[EDMA_MAX_RXFILL_RINGS];
+			/* Rx fill ring IRQ numbers */
+	uint32_t rxdesc_intr[EDMA_MAX_RXDESC_RINGS];
+			/* Rx desc ring IRQ numbers */
+	uint32_t misc_intr;
+			/* Misc IRQ number */
+
+	uint32_t tx_intr_mask;
+			/* Tx interrupt mask */
+	uint32_t rxfill_intr_mask;
+			/* Rx fill ring interrupt mask */
+	uint32_t rxdesc_intr_mask;
+			/* Rx Desc ring interrupt mask */
+	uint32_t txcmpl_intr_mask;
+			/* Tx Cmpl ring interrupt mask */
+	uint32_t misc_intr_mask;
+			/* misc interrupt interrupt mask */
+	uint32_t dp_override_cnt;
+			/* number of interfaces overriden */
+	bool edma_initialized;
+			/* flag to check initialization status */
+	uint32_t rx_alloc_size;
+			/* Buffer size to allocate */
+};
+
+extern struct edma_hw edma_hw;
+
+uint32_t edma_reg_read(uint32_t reg_off);
+void edma_reg_write(uint32_t reg_off, uint32_t val);
+
+int edma_alloc_rx_buffer(struct edma_hw *ehw,
+		struct edma_rxfill_ring *rxfill_ring);
+enum edma_tx edma_ring_xmit(struct edma_hw *ehw,
+			    struct net_device *netdev,
+			    struct sk_buff *skb,
+			    struct edma_txdesc_ring *txdesc_ring);
+uint32_t edma_clean_tx(struct edma_hw *ehw,
+			struct edma_txcmpl_ring *txcmpl_ring);
+irqreturn_t edma_handle_irq(int irq, void *ctx);
+irqreturn_t edma_handle_misc_irq(int irq, void *ctx);
+int edma_napi(struct napi_struct *napi, int budget);
+void edma_cleanup_rings(struct edma_hw *ehw);
+int edma_hw_init(struct edma_hw *ehw);
+#endif /* __NSS_DP_EDMA_DATAPLANE__ */
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/edma_regs.h b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/edma_regs.h
new file mode 100644
index 0000000..e724cc7
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/edma_regs.h
@@ -0,0 +1,454 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016,2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+*/
+
+#ifndef __EDMA_REGS__
+#define __EDMA_REGS__
+
+/*
+ * IPQ807x EDMA register offsets
+ */
+#define EDMA_REG_MAS_CTRL		0x0
+#define EDMA_REG_PORT_CTRL		0x4
+#define EDMA_REG_VLAN_CTRL		0x8
+#define EDMA_REG_RXDESC2FILL_MAP_0	0x18
+#define EDMA_REG_RXDESC2FILL_MAP_1	0x1c
+#define EDMA_REG_TXQ_CTRL		0x20
+#define EDMA_REG_TXQ_CTRL_2		0x24
+#define EDMA_REG_TXQ_FC_0		0x28
+#define EDMA_REG_TXQ_FC_1		0x30
+#define EDMA_REG_TXQ_FC_2		0x34
+#define EDMA_REG_TXQ_FC_3		0x38
+#define EDMA_REG_RXQ_CTRL		0x3c
+#define EDMA_REG_RX_TX_FULL_QID		0x40
+#define EDMA_REG_RXQ_FC_THRE		0x44
+#define EDMA_REG_DMAR_CTRL		0x48
+#define EDMA_REG_AXIR_CTRL		0x4c
+#define EDMA_REG_AXIW_CTRL		0x50
+#define EDMA_REG_MIN_MSS		0x54
+#define EDMA_REG_LOOPBACK_CTRL		0x58
+#define EDMA_REG_MISC_INT_STAT		0x5c
+#define EDMA_REG_MISC_INT_MASK		0x60
+#define EDMA_REG_DBG_CTRL		0x64
+#define EDMA_REG_DBG_DATA		0x68
+#define EDMA_REG_TXDESC_BA(n)		(0x1000 + (0x1000 * n))
+#define EDMA_REG_TXDESC_PROD_IDX(n)	(0x1004 + (0x1000 * n))
+#define EDMA_REG_TXDESC_CONS_IDX(n)	(0x1008 + (0x1000 * n))
+#define EDMA_REG_TXDESC_RING_SIZE(n)	(0x100c + (0x1000 * n))
+#define EDMA_REG_TXDESC_CTRL(n)		(0x1010 + (0x1000 * n))
+#if defined(NSS_DP_IPQ807X)
+#define EDMA_REG_TXDESC2CMPL_MAP_0	0xc
+#define EDMA_REG_TXDESC2CMPL_MAP_1	0x10
+#define EDMA_REG_TXDESC2CMPL_MAP_2	0x14
+#define EDMA_REG_TXCMPL_BASE		0x19000
+#define EDMA_REG_TX_BASE		0x21000
+#else
+#define EDMA_REG_TXCMPL_BASE		0x79000
+#define EDMA_REG_TX_BASE		0x91000
+#endif
+#define EDMA_REG_TXCMPL_BA_OFFSET		0x00000
+#define EDMA_REG_TXCMPL_PROD_IDX_OFFSET		0x00004
+#define EDMA_REG_TXCMPL_CONS_IDX_OFFSET		0x00008
+#define EDMA_REG_TXCMPL_RING_SIZE_OFFSET	0x0000c
+#define EDMA_REG_TXCMPL_UGT_THRE_OFFSET		0x00010
+#define EDMA_REG_TXCMPL_CTRL_OFFSET		0x00014
+#define EDMA_REG_TXCMPL_BPC_OFFSET		0x00018
+#define EDMA_REG_TX_INT_STAT_OFFSET		0x00000
+#define EDMA_REG_TX_INT_MASK_OFFSET		0x00004
+#define EDMA_REG_TX_MOD_TIMER_OFFSET		0x00008
+#define EDMA_REG_TX_INT_CTRL_OFFSET		0x0000c
+#define EDMA_REG_TXCMPL_BA(n)		(EDMA_REG_TXCMPL_BASE + EDMA_REG_TXCMPL_BA_OFFSET + (0x1000 * n))
+#define EDMA_REG_TXCMPL_PROD_IDX(n)	(EDMA_REG_TXCMPL_BASE + EDMA_REG_TXCMPL_PROD_IDX_OFFSET + (0x1000 * n))
+#define EDMA_REG_TXCMPL_CONS_IDX(n)	(EDMA_REG_TXCMPL_BASE + EDMA_REG_TXCMPL_CONS_IDX_OFFSET + (0x1000 * n))
+#define EDMA_REG_TXCMPL_RING_SIZE(n)	(EDMA_REG_TXCMPL_BASE + EDMA_REG_TXCMPL_RING_SIZE_OFFSET + (0x1000 * n))
+#define EDMA_REG_TXCMPL_UGT_THRE(n)	(EDMA_REG_TXCMPL_BASE + EDMA_REG_TXCMPL_UGT_THRE_OFFSET + (0x1000 * n))
+#define EDMA_REG_TXCMPL_CTRL(n)		(EDMA_REG_TXCMPL_BASE + EDMA_REG_TXCMPL_CTRL_OFFSET + (0x1000 * n))
+#define EDMA_REG_TXCMPL_BPC(n)		(EDMA_REG_TXCMPL_BASE + EDMA_REG_TXCMPL_BPC_OFFSET + (0x1000 * n))
+#define EDMA_REG_TX_INT_STAT(n)		(EDMA_REG_TX_BASE + EDMA_REG_TX_INT_STAT_OFFSET + (0x1000 * n))
+#define EDMA_REG_TX_INT_MASK(n)		(EDMA_REG_TX_BASE + EDMA_REG_TX_INT_MASK_OFFSET + (0x1000 * n))
+#define EDMA_REG_TX_MOD_TIMER(n)	(EDMA_REG_TX_BASE + EDMA_REG_TX_MOD_TIMER_OFFSET + (0x1000 * n))
+#define EDMA_REG_TX_INT_CTRL(n)		(EDMA_REG_TX_BASE + EDMA_REG_TX_INT_CTRL_OFFSET + (0x1000 * n))
+#define EDMA_REG_RXFILL_BA(n)		(0x29000 + (0x1000 * n))
+#define EDMA_REG_RXFILL_PROD_IDX(n)	(0x29004 + (0x1000 * n))
+#define EDMA_REG_RXFILL_CONS_IDX(n)	(0x29008 + (0x1000 * n))
+#define EDMA_REG_RXFILL_RING_SIZE(n)	(0x2900c + (0x1000 * n))
+#define EDMA_REG_RXFILL_BUFFER1_SIZE(n)	(0x29010 + (0x1000 * n))
+#define EDMA_REG_RXFILL_FC_THRE(n)	(0x29014 + (0x1000 * n))
+#define EDMA_REG_RXFILL_UGT_THRE(n)	(0x29018 + (0x1000 * n))
+#define EDMA_REG_RXFILL_RING_EN(n)	(0x2901c + (0x1000 * n))
+#define EDMA_REG_RXFILL_DISABLE(n)	(0x29020 + (0x1000 * n))
+#define EDMA_REG_RXFILL_DISABLE_DONE(n)	(0x29024 + (0x1000 * n))
+#define EDMA_REG_RXFILL_INT_STAT(n)	(0x31000 + (0x1000 * n))
+#define EDMA_REG_RXFILL_INT_MASK(n)	(0x31004 + (0x1000 * n))
+#define EDMA_REG_RXDESC_BA(n)		(0x39000 + (0x1000 * n))
+#define EDMA_REG_RXDESC_PROD_IDX(n)	(0x39004 + (0x1000 * n))
+#define EDMA_REG_RXDESC_CONS_IDX(n)	(0x39008 + (0x1000 * n))
+#define EDMA_REG_RXDESC_RING_SIZE(n)	(0x3900c + (0x1000 * n))
+#define EDMA_REG_RXDESC_FC_THRE(n)	(0x39010 + (0x1000 * n))
+#define EDMA_REG_RXDESC_UGT_THRE(n)	(0x39014 + (0x1000 * n))
+#define EDMA_REG_RXDESC_CTRL(n)		(0x39018 + (0x1000 * n))
+#define EDMA_REG_RXDESC_BPC(n)		(0x3901c + (0x1000 * n))
+#define EDMA_REG_RXDESC_INT_STAT(n)	(0x49000 + (0x1000 * n))
+#define EDMA_REG_RXDESC_INT_MASK(n)	(0x49004 + (0x1000 * n))
+#define EDMA_REG_RX_MOD_TIMER(n)	(0x49008 + (0x1000 * n))
+#define EDMA_REG_RX_INT_CTRL(n)		(0x4900c + (0x1000 * n))
+#define EDMA_QID2RID_TABLE_MEM(q)	(0x5a000 + (0x4 * q))
+#define EDMA_REG_RXRING_PC(n)		(0x5A200 + (0x10 * n))
+#define EDMA_REG_RXRING_BC_0(n)		(0x5A204 + (0x10 * n))
+#define EDMA_REG_RXRING_BC_1(n)		(0x5A208 + (0x10 * n))
+#define EDMA_REG_TXRING_PC(n)		(0x74000 + (0x10 * n))
+#define EDMA_REG_TXRING_BC_0(n)		(0x74004 + (0x10 * n))
+#define EDMA_REG_TXRING_BC_1(n)		(0x74008 + (0x10 * n))
+
+/*
+ * EDMA_REG_PORT_CTRL register
+ */
+#define EDMA_PORT_PAD_EN		0x1
+#define EDMA_PORT_EDMA_EN		0x2
+
+/*
+ * EDMA_REG_TXQ_CTRL register
+ */
+#define EDMA_TXDESC_PF_THRE_MASK		0xf
+#define EDMA_TXDESC_PF_THRE_SHIFT		0
+#define EDMA_TXCMPL_WB_THRE_MASK		0xf
+#define EDMA_TXCMPL_WB_THRE_SHIFT		4
+#define EDMA_TXDESC_PKT_SRAM_THRE_MASK		0xff
+#define EDMA_TXDESC_PKT_SRAM_THRE_SHIFT		8
+#define EDMA_TXCMPL_WB_TIMER_MASK		0xffff
+#define EDMA_TXCMPL_WB_TIMER_SHIFT		16
+
+/*
+ * EDMA_REG_RXQ_CTRL register
+ */
+#define EDMA_RXFILL_PF_THRE_MASK		0xf
+#define EDMA_RXFILL_PF_THRE_SHIFT		0
+#define EDMA_RXDESC_WB_THRE_MASK		0xf
+#define EDMA_RXDESC_WB_THRE_SHIFT		4
+#define EDMA_RXDESC_WB_TIMER_MASK		0xffff
+#define EDMA_RXDESC_WB_TIMER_SHIFT		16
+
+/*
+ * EDMA_REG_RX_TX_FULL_QID register
+ */
+#define EDMA_RX_DESC_FULL_QID_MASK		0xff
+#define EDMA_RX_DESC_FULL_QID_SHIFT		0
+#define EDMA_TX_CMPL_BUF_FULL_QID_MASK		0xff
+#define EDMA_TX_CMPL_BUF_FULL_QID_SHIFT		8
+#define EDMA_TX_SRAM_FULL_QID_MASK		0x1f
+#define EDMA_TX_SRAM_FULL_QID_SHIFT		16
+
+/*
+ * EDMA_REG_RXQ_FC_THRE reister
+ */
+#define EDMA_RXFILL_FIFO_XOFF_THRE_MASK		0x1f
+#define EDMA_RXFILL_FIFO_XOFF_THRE_SHIFT	0
+#define EDMA_DESC_FIFO_XOFF_THRE_MASK		0x3f
+#define EDMA_DESC_FIFO_XOFF_THRE_SHIFT		16
+
+/*
+ * EDMA_REG_DMAR_CTRL register
+ */
+#define EDMA_DMAR_REQ_PRI_MASK			0x7
+#define EDMA_DMAR_REQ_PRI_SHIFT			0
+#define EDMA_DMAR_BURST_LEN_MASK		0x1
+#define EDMA_DMAR_BURST_LEN_SHIFT		3
+#define EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK	0x1f
+#define EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SHIFT	4
+#define EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK	0x7
+#define EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SHIFT	9
+#define EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK	0x7
+#define EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SHIFT	12
+
+#define EDMA_DMAR_REQ_PRI_SET(x)        	(((x) & EDMA_DMAR_REQ_PRI_MASK) << EDMA_DMAR_REQ_PRI_SHIFT)
+#define EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SET(x) (((x) & EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK) << EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SHIFT)
+#define EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SET(x) (((x) & EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK) << EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SHIFT)
+#define EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SET(x) (((x) & EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK) << EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SHIFT)
+#define EDMA_DMAR_BURST_LEN_SET(x)		(((x) & EDMA_DMAR_BURST_LEN_MASK) << EDMA_DMAR_BURST_LEN_SHIFT)
+
+/*
+ * Enable 128 byte EDMA burts for IPQ60xx
+ */
+#if defined(NSS_DP_IPQ60XX)
+#define EDMA_BURST_LEN_ENABLE		1
+#else
+#define EDMA_BURST_LEN_ENABLE		0
+#endif
+
+/*
+ * EDMA_REG_AXIW_CTRL_REG
+ */
+#define EDMA_AXIW_MAX_WR_SIZE_EN		0x400
+
+/*
+ * EDMA DISABLE
+ */
+#define EDMA_DISABLE				0
+
+/*
+ * EDMA_REG_TXDESC_PROD_IDX register
+ */
+#define EDMA_TXDESC_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXDESC_CONS_IDX register
+ */
+#define EDMA_TXDESC_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXDESC_RING_SIZE register
+ */
+#define EDMA_TXDESC_RING_SIZE_MASK		0xffff
+
+/*
+ * EDMA_REG_TXDESC_CTRL register
+ */
+#define EDMA_TXDESC_ARB_GRP_ID_MASK		0x3
+#define EDMA_TXDESC_ARB_GRP_ID_SHIFT		4
+#define EDMA_TXDESC_FC_GRP_ID_MASK		0x7
+#define EDMA_TXDESC_FC_GRP_ID_SHIFT		1
+#define EDMA_TXDESC_TX_EN			0x1
+
+/*
+ * EDMA_REG_TXCMPL_PROD_IDX register
+ */
+#define EDMA_TXCMPL_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXCMPL_CONS_IDX register
+ */
+#define EDMA_TXCMPL_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXCMPL_RING_SIZE register
+ */
+#define EDMA_TXCMPL_RING_SIZE_MASK		0xffff
+
+/*
+ * EDMA_REG_TXCMPL_UGT_THRE register
+ */
+#define EDMA_TXCMPL_LOW_THRE_MASK		0xffff
+#define EDMA_TXCMPL_LOW_THRE_SHIFT		0
+#define EDMA_TXCMPL_FC_THRE_MASK		0x3f
+#define EDMA_TXCMPL_FC_THRE_SHIFT		16
+
+/*
+ * EDMA_REG_TXCMPL_CTRL register
+ */
+#define EDMA_TXCMPL_RET_MODE_BUFF_ADDR		0x0
+#define EDMA_TXCMPL_RET_MODE_OPAQUE		0x1
+
+/*
+ * EDMA_REG_TX_MOD_TIMER register
+ */
+#define EDMA_TX_MOD_TIMER_INIT_MASK		0xffff
+#define EDMA_TX_MOD_TIMER_INIT_SHIFT		0
+
+/*
+ * EDMA_REG_TX_INT_CTRL register
+ */
+#define EDMA_TX_INT_MASK			0x3
+
+/*
+ * EDMA_REG_RXFILL_PROD_IDX register
+ */
+#define EDMA_RXFILL_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXFILL_CONS_IDX register
+ */
+#define EDMA_RXFILL_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXFILL_RING_SIZE register
+ */
+#define EDMA_RXFILL_RING_SIZE_MASK		0xffff
+#define EDMA_RXFILL_BUF_SIZE_MASK		0x3fff
+#define EDMA_RXFILL_BUF_SIZE_SHIFT		16
+
+/*
+ * EDMA_REG_RXFILL_FC_THRE register
+ */
+#define EDMA_RXFILL_FC_XON_THRE_MASK		0x7ff
+#define EDMA_RXFILL_FC_XON_THRE_SHIFT		12
+#define EDMA_RXFILL_FC_XOFF_THRE_MASK		0x7ff
+#define EDMA_RXFILL_FC_XOFF_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXFILL_UGT_THRE register
+ */
+#define EDMA_RXFILL_LOW_THRE_MASK		0xffff
+#define EDMA_RXFILL_LOW_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXFILL_RING_EN register
+ */
+#define EDMA_RXFILL_RING_EN			0x1
+
+/*
+ * EDMA_REG_RXFILL_INT_MASK register
+ */
+#define EDMA_RXFILL_INT_MASK			0x1
+
+/*
+ * EDMA_REG_RXDESC_PROD_IDX register
+ */
+#define EDMA_RXDESC_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXDESC_CONS_IDX register
+ */
+#define EDMA_RXDESC_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXDESC_RING_SIZE register
+ */
+#define EDMA_RXDESC_RING_SIZE_MASK		0xffff
+#define EDMA_RXDESC_PL_OFFSET_MASK		0x1ff
+#define EDMA_RXDESC_PL_OFFSET_SHIFT		16
+
+/*
+ * EDMA_REG_RXDESC_FC_THRE register
+ */
+#define EDMA_RXDESC_FC_XON_THRE_MASK		0x7ff
+#define EDMA_RXDESC_FC_XON_THRE_SHIFT		12
+#define EDMA_RXDESC_FC_XOFF_THRE_MASK		0x7ff
+#define EDMA_RXDESC_FC_XOFF_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXDESC_UGT_THRE register
+ */
+#define EDMA_RXDESC_LOW_THRE_MASK		0xffff
+#define EDMA_RXDESC_LOW_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXDESC_CTRL register
+ */
+#define EDMA_RXDESC_STAG_REMOVE_EN		0x8
+#define EDMA_RXDESC_CTAG_REMOVE_EN		0x4
+#define EDMA_RXDESC_QDISC_EN			0x2
+#define EDMA_RXDESC_RX_EN			0x1
+
+/*
+ * EDMA_REG_TX_INT_MASK register
+ */
+#define EDMA_TX_INT_MASK_PKT_INT		0x1
+#define EDMA_TX_INT_MASK_UGT_INT		0x2
+
+/*
+ * EDMA_REG_RXDESC_INT_STAT register
+ */
+#define EDMA_RXDESC_INT_STAT_PKT_INT		0x1
+#define EDMA_RXDESC_INT_STAT_UGT_INT		0x2
+
+/*
+ * EDMA_REG_RXDESC_INT_MASK register
+ */
+#define EDMA_RXDESC_INT_MASK_PKT_INT		0x1
+#define EDMA_RXDESC_INT_MASK_TIMER_INT_DIS	0x2
+
+#define EDMA_MASK_INT_DISABLE			0x0
+#define EDMA_MASK_INT_CLEAR			0x0
+
+/*
+ * EDMA_REG_RX_MOD_TIMER register
+ */
+#define EDMA_RX_MOD_TIMER_INIT_MASK		0xffff
+#define EDMA_RX_MOD_TIMER_INIT_SHIFT		0
+
+/*
+ * EDMA QID2RID register sizes
+ */
+#define EDMA_QID2RID_DEPTH			0x40
+#define EDMA_QID2RID_QUEUES_PER_ENTRY		8
+
+/*
+ * TXDESC shift values
+ */
+#define EDMA_TXDESC_MORE_SHIFT			31
+#define EDMA_TXDESC_TSO_EN_SHIFT		30
+#define EDMA_TXDESC_PREHEADER_SHIFT		29
+#define EDMA_TXDESC_POOL_ID_SHIFT		24
+#define EDMA_TXDESC_POOL_ID_MASK		0x1f
+#define EDMA_TXDESC_DATA_OFFSET_SHIFT		16
+#define EDMA_TXDESC_DATA_OFFSET_MASK		0xff
+#define EDMA_TXDESC_DATA_LENGTH_SHIFT		0
+#define EDMA_TXDESC_DATA_LENGTH_MASK		0xffff
+
+#define EDMA_PREHDR_DSTINFO_PORTID_IND		0x20
+#define EDMA_PREHDR_PORTNUM_BITS		0x0fff
+#define EDMA_RING_DMA_MASK			0xffffffff
+/*
+ * RXDESC shift values
+ */
+#define EDMA_RXDESC_RX_RXFILL_CNT_MASK		0x000f
+#define EDMA_RXDESC_RX_RXFILL_CNT_SHIFT		16
+
+#define EDMA_RXDESC_PKT_SIZE_MASK		0x3fff
+#define EDMA_RXDESC_PKT_SIZE_SHIFT		0
+
+#define EDMA_RXDESC_RXD_VALID_MASK		0x1
+#define EDMA_RXDESC_RXD_VALID_SHIFT		31
+
+#define EDMA_RXDESC_PACKET_LEN_MASK		0x3fff
+#define EDMA_RXDESC_RING_INT_STATUS_MASK	0x3
+
+#define EDMA_RING_DISABLE			0
+#define EDMA_TXCMPL_RING_INT_STATUS_MASK	0x3
+#define EDMA_TXCMPL_RETMODE_OPAQUE		0x0
+#define EDMA_RXFILL_RING_INT_STATUS_MASK	0x1
+
+/*
+ * TODO tune the timer and threshold values
+ */
+#define EDMA_RXFILL_FIFO_XOFF_THRE		0x3
+#define EDMA_RXFILL_PF_THRE			0x3
+#define EDMA_RXDESC_WB_THRE			0x0
+#define EDMA_RXDESC_WB_TIMER			0x2
+
+#define EDMA_RXDESC_XON_THRE			50
+#define EDMA_RXDESC_XOFF_THRE			30
+#define EDMA_RXDESC_LOW_THRE			0
+#define EDMA_RX_MOD_TIMER_INIT			1000
+
+#define EDMA_TXDESC_PF_THRE			0x3
+#define EDMA_TXCMPL_WB_THRE			0X0
+#define EDMA_TXDESC_PKT_SRAM_THRE		0x20
+#define EDMA_TXCMPL_WB_TIMER			0x2
+
+#define EDMA_TX_MOD_TIMER			150
+
+/*
+ * EDMA misc error mask
+ */
+#define EDMA_MISC_AXI_RD_ERR_MASK_EN		0x1
+#define EDMA_MISC_AXI_WR_ERR_MASK_EN		0x2
+#define EDMA_MISC_RX_DESC_FIFO_FULL_MASK_EN	0x4
+#define EDMA_MISC_RX_ERR_BUF_SIZE_MASK_EN	0x8
+#define EDMA_MISC_TX_SRAM_FULL_MASK_EN		0x10
+#define EDMA_MISC_TX_CMPL_BUF_FULL_MASK_EN	0x20
+
+#if defined(NSS_DP_IPQ807X)
+#define EDMA_MISC_PKT_LEN_LA_64K_MASK_EN	0x40
+#define EDMA_MISC_PKT_LEN_LE_40_MASK_EN		0x80
+#define EDMA_MISC_DATA_LEN_ERR_MASK_EN		0x100
+#else
+#define EDMA_MISC_DATA_LEN_ERR_MASK_EN		0x40
+#define EDMA_MISC_TX_TIMEOUT_MASK_EN		0x80
+#endif
+
+#endif /*  __EDMA_REGS__ */
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c
new file mode 100644
index 0000000..42961fa
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c
@@ -0,0 +1,796 @@
+/*
+ * Copyright (c) 2016-2018, 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/debugfs.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include "edma_data_plane.h"
+#include "edma_regs.h"
+#include "nss_dp_dev.h"
+
+/*
+ * edma_alloc_rx_buffer()
+ *	Alloc Rx buffers for one RxFill ring
+ */
+int edma_alloc_rx_buffer(struct edma_hw *ehw,
+		struct edma_rxfill_ring *rxfill_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+	struct sk_buff *skb;
+	uint16_t num_alloc = 0;
+	uint16_t cons, next, counter;
+	struct edma_rxfill_desc *rxfill_desc;
+	uint32_t reg_data = 0;
+	uint32_t store_index = 0;
+	uint32_t alloc_size = ehw->rx_alloc_size;
+	struct edma_rx_preheader *rxph = NULL;
+
+	/*
+	 * Read RXFILL ring producer index
+	 */
+	reg_data = edma_reg_read(EDMA_REG_RXFILL_PROD_IDX(rxfill_ring->id));
+	next = reg_data & EDMA_RXFILL_PROD_IDX_MASK & (rxfill_ring->count - 1);
+
+	/*
+	 * Read RXFILL ring consumer index
+	 */
+	reg_data = edma_reg_read(EDMA_REG_RXFILL_CONS_IDX(rxfill_ring->id));
+	cons = reg_data & EDMA_RXFILL_CONS_IDX_MASK;
+
+	while (1) {
+		counter = next;
+		if (++counter == rxfill_ring->count)
+			counter = 0;
+
+		if (counter == cons)
+			break;
+
+		/*
+		 * Allocate buffer
+		 */
+		skb = dev_alloc_skb(alloc_size);
+		if (unlikely(!skb))
+			break;
+
+		/*
+		 * Get RXFILL descriptor
+		 */
+		rxfill_desc = EDMA_RXFILL_DESC(rxfill_ring, next);
+
+		/*
+		 * Make room for Rx preheader
+		 */
+		rxph = (struct edma_rx_preheader *)
+			skb_push(skb, EDMA_RX_PREHDR_SIZE);
+
+		/*
+		 * Store the skb in the rx store
+		 */
+		store_index = next;
+		if (ehw->rx_skb_store[store_index] != NULL) {
+			dev_kfree_skb_any(skb);
+			break;
+		}
+		ehw->rx_skb_store[store_index] = skb;
+		memcpy((uint8_t *)&rxph->opaque, (uint8_t *)&store_index, 4);
+		/*
+		 * Save buffer size in RXFILL descriptor
+		 */
+		rxfill_desc->word1 = cpu_to_le32(alloc_size
+					& EDMA_RXFILL_BUF_SIZE_MASK);
+
+		/*
+		 * Map Rx buffer for DMA
+		 */
+		rxfill_desc->buffer_addr = cpu_to_le32(dma_map_single(
+						&pdev->dev,
+						skb->data,
+						alloc_size,
+						DMA_FROM_DEVICE));
+
+		if (!rxfill_desc->buffer_addr) {
+			dev_kfree_skb_any(skb);
+			ehw->rx_skb_store[store_index] = NULL;
+			break;
+		}
+
+		num_alloc++;
+		next = counter;
+	}
+
+	if (num_alloc) {
+		/*
+		 * Update RXFILL ring producer index
+		 */
+		reg_data = next & EDMA_RXFILL_PROD_IDX_MASK;
+
+		/*
+		 * make sure the producer index updated before
+		 * updating the hardware
+		 */
+		wmb();
+
+		edma_reg_write(EDMA_REG_RXFILL_PROD_IDX(rxfill_ring->id),
+				reg_data);
+	}
+
+	return num_alloc;
+}
+
+/*
+ * edma_clean_tx()
+ *	Reap Tx descriptors
+ */
+uint32_t edma_clean_tx(struct edma_hw *ehw,
+			struct edma_txcmpl_ring *txcmpl_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+	struct edma_txcmpl_desc *txcmpl = NULL;
+	uint16_t prod_idx = 0;
+	uint16_t cons_idx = 0;
+	uint32_t data = 0;
+	uint32_t txcmpl_consumed = 0;
+	struct sk_buff *skb;
+	uint32_t len;
+	int store_index;
+	dma_addr_t daddr;
+
+	/*
+	 * Get TXCMPL ring producer index
+	 */
+	data = edma_reg_read(EDMA_REG_TXCMPL_PROD_IDX(txcmpl_ring->id));
+	prod_idx = data & EDMA_TXCMPL_PROD_IDX_MASK;
+
+	/*
+	 * Get TXCMPL ring consumer index
+	 */
+	data = edma_reg_read(EDMA_REG_TXCMPL_CONS_IDX(txcmpl_ring->id));
+	cons_idx = data & EDMA_TXCMPL_CONS_IDX_MASK;
+
+	while (cons_idx != prod_idx) {
+		txcmpl = &(((struct edma_txcmpl_desc *)
+					(txcmpl_ring->desc))[cons_idx]);
+
+		/*
+		 * skb for this is stored in tx store and
+		 * tx header contains the index in the field
+		 * buffer address (opaque) of txcmpl
+		 */
+		store_index = txcmpl->buffer_addr;
+		skb = ehw->tx_skb_store[store_index];
+		ehw->tx_skb_store[store_index] = NULL;
+
+		if (unlikely(!skb)) {
+			pr_warn("Invalid skb: cons_idx:%u prod_idx:%u status %x\n",
+				  cons_idx, prod_idx, txcmpl->status);
+			goto next_txcmpl_desc;
+		}
+
+		len = skb_headlen(skb);
+		daddr = (dma_addr_t)virt_to_phys(skb->data);
+
+		pr_debug("skb:%px cons_idx:%d prod_idx:%d word1:0x%x\n",
+			   skb, cons_idx, prod_idx, txcmpl->status);
+
+		dma_unmap_single(&pdev->dev, daddr,
+				 len, DMA_TO_DEVICE);
+		dev_kfree_skb_any(skb);
+
+next_txcmpl_desc:
+		if (++cons_idx == txcmpl_ring->count)
+			cons_idx = 0;
+
+		txcmpl_consumed++;
+	}
+
+	if (txcmpl_consumed == 0)
+		return 0;
+
+	pr_debug("TXCMPL:%u txcmpl_consumed:%u prod_idx:%u cons_idx:%u\n",
+			txcmpl_ring->id, txcmpl_consumed, prod_idx, cons_idx);
+
+	/*
+	 * Update TXCMPL ring consumer index
+	 */
+	wmb();
+	edma_reg_write(EDMA_REG_TXCMPL_CONS_IDX(txcmpl_ring->id), cons_idx);
+
+	return txcmpl_consumed;
+}
+
+/*
+ * nss_phy_tstamp_rx_buf()
+ *	Receive timestamp packet
+ */
+void nss_phy_tstamp_rx_buf(__attribute__((unused))void *app_data, struct sk_buff *skb)
+{
+	struct net_device *ndev = skb->dev;
+
+	/*
+	 * The PTP_CLASS_ value 0 is passed to phy driver, which will be
+	 * set to the correct PTP class value by calling ptp_classify_raw
+	 * in drv->rxtstamp function.
+	 */
+	if (ndev && ndev->phydev && ndev->phydev->drv &&
+			ndev->phydev->drv->rxtstamp)
+		if(ndev->phydev->drv->rxtstamp(ndev->phydev, skb, 0))
+			return;
+
+	netif_receive_skb(skb);
+}
+EXPORT_SYMBOL(nss_phy_tstamp_rx_buf);
+
+/*
+ * nss_phy_tstamp_tx_buf()
+ *	Transmit timestamp packet
+ */
+void nss_phy_tstamp_tx_buf(struct net_device *ndev, struct sk_buff *skb)
+{
+	/*
+	 * Function drv->txtstamp will create a clone of skb if necessary,
+	 * the PTP_CLASS_ value 0 is passed to phy driver, which will be
+	 * set to the correct PTP class value by calling ptp_classify_raw
+	 * in the drv->txtstamp function.
+	 */
+	if (ndev && ndev->phydev && ndev->phydev->drv &&
+			ndev->phydev->drv->txtstamp)
+		ndev->phydev->drv->txtstamp(ndev->phydev, skb, 0);
+}
+EXPORT_SYMBOL(nss_phy_tstamp_tx_buf);
+
+/*
+ * edma_clean_rx()
+ *	Reap Rx descriptors
+ */
+static uint32_t edma_clean_rx(struct edma_hw *ehw,
+				int work_to_do,
+				struct edma_rxdesc_ring *rxdesc_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+	struct net_device *ndev;
+	struct sk_buff *skb = NULL;
+	struct edma_rxdesc_desc *rxdesc_desc;
+	struct edma_rx_preheader *rxph = NULL;
+	uint16_t prod_idx = 0;
+	int src_port_num = 0;
+	int pkt_length = 0;
+	uint16_t cons_idx = 0;
+	uint32_t work_done = 0;
+	int store_index;
+
+	/*
+	 * Read Rx ring consumer index
+	 */
+	cons_idx = edma_reg_read(EDMA_REG_RXDESC_CONS_IDX(rxdesc_ring->id))
+				& EDMA_RXDESC_CONS_IDX_MASK;
+
+	while (1) {
+		/*
+		 * Read Rx ring producer index
+		 */
+		prod_idx = edma_reg_read(
+			EDMA_REG_RXDESC_PROD_IDX(rxdesc_ring->id))
+			& EDMA_RXDESC_PROD_IDX_MASK;
+
+		if (cons_idx == prod_idx)
+			break;
+
+		if (work_done >= work_to_do)
+			break;
+
+		rxdesc_desc = EDMA_RXDESC_DESC(rxdesc_ring, cons_idx);
+
+		/*
+		 * Get Rx preheader
+		 */
+		rxph = (struct edma_rx_preheader *)
+			phys_to_virt(rxdesc_desc->buffer_addr);
+
+		/*
+		 * DMA unmap Rx buffer
+		 */
+		dma_unmap_single(&pdev->dev,
+				 rxdesc_desc->buffer_addr,
+				 ehw->rx_alloc_size,
+				 DMA_FROM_DEVICE);
+
+		store_index = rxph->opaque;
+		skb = ehw->rx_skb_store[store_index];
+		ehw->rx_skb_store[store_index] = NULL;
+		if (unlikely(!skb)) {
+			pr_warn("WARN: empty skb reference in rx_store:%d\n",
+					cons_idx);
+			goto next_rx_desc;
+		}
+
+		/*
+		 * Check src_info from Rx preheader
+		 */
+		if (EDMA_RXPH_SRC_INFO_TYPE_GET(rxph) ==
+				EDMA_PREHDR_DSTINFO_PORTID_IND) {
+			src_port_num = rxph->src_info &
+				EDMA_PREHDR_PORTNUM_BITS;
+		} else {
+			pr_warn("WARN: src_info_type:0x%x. Drop skb:%px\n",
+				  EDMA_RXPH_SRC_INFO_TYPE_GET(rxph), skb);
+			dev_kfree_skb_any(skb);
+			goto next_rx_desc;
+		}
+
+		/*
+		 * Get packet length
+		 */
+		pkt_length = rxdesc_desc->status & EDMA_RXDESC_PACKET_LEN_MASK;
+
+		if (unlikely((src_port_num < EDMA_START_GMACS) ||
+			(src_port_num > EDMA_MAX_GMACS))) {
+			pr_warn("WARN: Port number error :%d. Drop skb:%px\n",
+					src_port_num, skb);
+			dev_kfree_skb_any(skb);
+			goto next_rx_desc;
+		}
+
+		/*
+		 * Get netdev for this port using the source port
+		 * number as index into the netdev array. We need to
+		 * subtract one since the indices start form '0' and
+		 * port numbers start from '1'.
+		 */
+		ndev = ehw->netdev_arr[src_port_num - 1];
+		if (unlikely(!ndev)) {
+			pr_warn("WARN: netdev Null src_info_type:0x%x. Drop skb:%px\n",
+					src_port_num, skb);
+			dev_kfree_skb_any(skb);
+			goto next_rx_desc;
+		}
+
+		if (unlikely(!netif_running(ndev))) {
+			dev_kfree_skb_any(skb);
+			goto next_rx_desc;
+		}
+
+		/*
+		 * Remove Rx preheader
+		 */
+		skb_pull(skb, EDMA_RX_PREHDR_SIZE);
+
+		/*
+		 * Update skb fields and indicate packet to stack
+		 */
+		skb->dev = ndev;
+		skb->skb_iif = ndev->ifindex;
+		skb_put(skb, pkt_length);
+		skb->protocol = eth_type_trans(skb, skb->dev);
+#ifdef NSS_DP_PPE_SWITCHDEV
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+		skb->offload_fwd_mark = ndev->offload_fwd_mark;
+#else
+		/*
+		 * TODO: Implement ndo_get_devlink_port()
+		 */
+		 skb->offload_fwd_mark = 0;
+#endif
+		pr_debug("skb:%px ring_idx:%u pktlen:%d proto:0x%x mark:%u\n",
+			   skb, cons_idx, pkt_length, skb->protocol,
+			   skb->offload_fwd_mark);
+#else
+		pr_debug("skb:%px ring_idx:%u pktlen:%d proto:0x%x\n",
+			   skb, cons_idx, pkt_length, skb->protocol);
+#endif
+		/*
+		 * Deliver the ptp packet to phy driver for RX timestamping
+		 */
+		if (unlikely(EDMA_RXPH_SERVICE_CODE_GET(rxph) ==
+					NSS_PTP_EVENT_SERVICE_CODE))
+			nss_phy_tstamp_rx_buf(ndev, skb);
+		else
+			netif_receive_skb(skb);
+
+next_rx_desc:
+		/*
+		 * Update consumer index
+		 */
+		if (++cons_idx == rxdesc_ring->count)
+			cons_idx = 0;
+
+		/*
+		 * Update work done
+		 */
+		work_done++;
+	}
+
+	edma_alloc_rx_buffer(ehw, rxdesc_ring->rxfill);
+
+	/*
+	 * make sure the consumer index is updated
+	 * before updating the hardware
+	 */
+	wmb();
+	edma_reg_write(EDMA_REG_RXDESC_CONS_IDX(rxdesc_ring->id), cons_idx);
+	return work_done;
+}
+
+/*
+ * edma_napi()
+ *	EDMA NAPI handler
+ */
+int edma_napi(struct napi_struct *napi, int budget)
+{
+	struct edma_hw *ehw = container_of(napi, struct edma_hw, napi);
+	struct edma_txcmpl_ring *txcmpl_ring = NULL;
+	struct edma_rxdesc_ring *rxdesc_ring = NULL;
+	struct edma_rxfill_ring *rxfill_ring = NULL;
+
+	struct net_device *ndev;
+	int work_done = 0;
+	int i;
+
+	for (i = 0; i < ehw->rxdesc_rings; i++) {
+		rxdesc_ring = &ehw->rxdesc_ring[i];
+		work_done += edma_clean_rx(ehw, budget, rxdesc_ring);
+	}
+
+	for (i = 0; i < ehw->txcmpl_rings; i++) {
+		txcmpl_ring = &ehw->txcmpl_ring[i];
+		work_done += edma_clean_tx(ehw, txcmpl_ring);
+	}
+
+	for (i = 0; i < ehw->rxfill_rings; i++) {
+		rxfill_ring = &ehw->rxfill_ring[i];
+		work_done += edma_alloc_rx_buffer(ehw, rxfill_ring);
+	}
+
+	/*
+	 * Resume netdev Tx queue
+	 */
+	/*
+	 * TODO works currently since we have a single queue.
+	 * Need to make sure we have support in place when there is
+	 * support for multiple queues
+	 */
+	for (i = 0; i < EDMA_MAX_GMACS; i++) {
+		ndev = ehw->netdev_arr[i];
+		if (!ndev)
+			continue;
+
+		if (netif_queue_stopped(ndev) && netif_carrier_ok(ndev))
+			netif_start_queue(ndev);
+	}
+
+	/*
+	 * TODO - rework and fix the budget control
+	 */
+	if (work_done < budget) {
+		/*
+		 * TODO per core NAPI
+		 */
+		napi_complete(napi);
+
+		/*
+		 * Set RXDESC ring interrupt mask
+		 */
+		for (i = 0; i < ehw->rxdesc_rings; i++) {
+			rxdesc_ring = &ehw->rxdesc_ring[i];
+			edma_reg_write(
+				EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id),
+				ehw->rxdesc_intr_mask);
+		}
+
+		/*
+		 * Set TXCMPL ring interrupt mask
+		 */
+		for (i = 0; i < ehw->txcmpl_rings; i++) {
+			txcmpl_ring = &ehw->txcmpl_ring[i];
+			edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id),
+					ehw->txcmpl_intr_mask);
+		}
+
+		/*
+		 * Set RXFILL ring interrupt mask
+		 */
+		for (i = 0; i < ehw->rxfill_rings; i++) {
+			rxfill_ring = &ehw->rxfill_ring[i];
+			edma_reg_write(EDMA_REG_RXFILL_INT_MASK(
+						rxfill_ring->id),
+						edma_hw.rxfill_intr_mask);
+		}
+	}
+	return work_done;
+}
+
+/*
+ * edma_ring_xmit()
+ *	Transmit a packet using an EDMA ring
+ */
+enum edma_tx edma_ring_xmit(struct edma_hw *ehw,
+			    struct net_device *netdev,
+			    struct sk_buff *skb,
+			    struct edma_txdesc_ring *txdesc_ring)
+{
+	struct nss_dp_dev *dp_dev = netdev_priv(netdev);
+	struct edma_txdesc_desc *txdesc = NULL;
+	uint16_t buf_len;
+	uint16_t hw_next_to_use, hw_next_to_clean, chk_idx;
+	uint32_t data;
+	uint32_t store_index = 0;
+	struct edma_tx_preheader *txph = NULL;
+
+	/*
+	 * TODO - revisit locking
+	 */
+	spin_lock_bh(&txdesc_ring->tx_lock);
+
+	/*
+	 * Read TXDESC ring producer index
+	 */
+	data = edma_reg_read(EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id));
+	hw_next_to_use = data & EDMA_TXDESC_PROD_IDX_MASK;
+
+	/*
+	 * Read TXDESC ring consumer index
+	 */
+	/*
+	 * TODO - read to local variable to optimize uncached access
+	 */
+	data = edma_reg_read(EDMA_REG_TXDESC_CONS_IDX(txdesc_ring->id));
+	hw_next_to_clean = data & EDMA_TXDESC_CONS_IDX_MASK;
+
+	/*
+	 * Check for available Tx descriptor
+	 */
+	chk_idx = (hw_next_to_use + 1) & (txdesc_ring->count-1);
+
+	if (chk_idx == hw_next_to_clean) {
+		spin_unlock_bh(&txdesc_ring->tx_lock);
+		return EDMA_TX_DESC;
+	}
+
+#if defined(NSS_DP_EDMA_TX_SMALL_PKT_WAR)
+	/*
+	 * IPQ807x EDMA hardware can't process the packet if the packet size is
+	 * less than EDMA_TX_PKT_MIN_SIZE (33 Byte). So, if the packet size
+	 * is indeed less than EDMA_TX_PKT_MIN_SIZE, perform padding
+	 * (if possible), otherwise drop the packet.
+	 * Using skb_padto() API for padding the packet. This API will drop
+	 * the packet if the padding is not possible.
+	 */
+	if (unlikely(skb->len < EDMA_TX_PKT_MIN_SIZE)) {
+		if (skb_padto(skb, EDMA_TX_PKT_MIN_SIZE)) {
+			netdev_dbg(netdev, "padding couldn't happen, skb is freed.\n");
+			netdev->stats.tx_dropped++;
+			spin_unlock_bh(&txdesc_ring->tx_lock);
+			return EDMA_TX_OK;
+		}
+		skb->len = EDMA_TX_PKT_MIN_SIZE;
+	}
+#endif
+
+	buf_len = skb_headlen(skb);
+
+	/*
+	 * Deliver the ptp packet to phy driver for TX timestamping
+	 */
+	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
+		nss_phy_tstamp_tx_buf(netdev, skb);
+
+	/*
+	 * Make room for Tx preheader
+	 */
+	txph = (struct edma_tx_preheader *)skb_push(skb,
+			EDMA_TX_PREHDR_SIZE);
+	memset((void *)txph, 0, EDMA_TX_PREHDR_SIZE);
+
+	/*
+	 * Populate Tx preheader dst info, port id is macid in dp_dev
+	 */
+	txph->dst_info = (EDMA_PREHDR_DSTINFO_PORTID_IND << 8) |
+			(dp_dev->macid & 0x0fff);
+
+	/*
+	 * Store the skb in tx_store
+	 */
+	store_index = hw_next_to_use & (txdesc_ring->count - 1);
+	if (unlikely(ehw->tx_skb_store[store_index] != NULL)) {
+		spin_unlock_bh(&txdesc_ring->tx_lock);
+		return EDMA_TX_DESC;
+	}
+
+	ehw->tx_skb_store[store_index] = skb;
+	memcpy(skb->data, &store_index, 4);
+
+	/*
+	 * Get Tx descriptor
+	 */
+	txdesc = EDMA_TXDESC_DESC(txdesc_ring, hw_next_to_use);
+	memset(txdesc, 0, sizeof(struct edma_txdesc_desc));
+
+	/*
+	 * Map buffer to DMA address
+	 */
+	txdesc->buffer_addr = cpu_to_le32(dma_map_single(&(ehw->pdev)->dev,
+				       skb->data,
+				       buf_len + EDMA_TX_PREHDR_SIZE,
+				       DMA_TO_DEVICE));
+	if (!txdesc->buffer_addr) {
+		/*
+		 * DMA map failed for this address. Drop it
+		 * and make sure does not got to stack again
+		 */
+		dev_kfree_skb_any(skb);
+
+		ehw->tx_skb_store[store_index] = NULL;
+		spin_unlock_bh(&txdesc_ring->tx_lock);
+		return EDMA_TX_OK;
+	}
+
+	/*
+	 * Populate Tx descriptor
+	 */
+	txdesc->word1 |= (1 << EDMA_TXDESC_PREHEADER_SHIFT)
+			| ((EDMA_TX_PREHDR_SIZE & EDMA_TXDESC_DATA_OFFSET_MASK)
+			   << EDMA_TXDESC_DATA_OFFSET_SHIFT);
+	txdesc->word1 |= ((buf_len & EDMA_TXDESC_DATA_LENGTH_MASK)
+			<< EDMA_TXDESC_DATA_LENGTH_SHIFT);
+
+	netdev_dbg(netdev, "skb:%px tx_ring:%u proto:0x%x\n",
+			skb, txdesc_ring->id, ntohs(skb->protocol));
+	netdev_dbg(netdev, "port:%u prod_idx:%u cons_idx:%u\n",
+			dp_dev->macid, hw_next_to_use, hw_next_to_clean);
+
+	/*
+	 * Update producer index
+	 */
+	hw_next_to_use = (hw_next_to_use + 1) & (txdesc_ring->count - 1);
+
+	/*
+	 * make sure the hw_next_to_use is updated before the
+	 * write to hardware
+	 */
+	wmb();
+
+	edma_reg_write(EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id),
+		       hw_next_to_use & EDMA_TXDESC_PROD_IDX_MASK);
+	spin_unlock_bh(&txdesc_ring->tx_lock);
+	return EDMA_TX_OK;
+}
+
+/*
+ * edma_handle_misc_irq()
+ *	Process IRQ
+ */
+irqreturn_t edma_handle_misc_irq(int irq, void *ctx)
+{
+	uint32_t misc_intr_status = 0;
+	uint32_t reg_data = 0;
+	struct edma_hw *ehw = NULL;
+	struct platform_device *pdev = (struct platform_device *)ctx;
+
+	ehw = platform_get_drvdata(pdev);
+
+	/*
+	 * Read Misc intr status
+	 */
+	reg_data = edma_reg_read(EDMA_REG_MISC_INT_STAT);
+	misc_intr_status = reg_data & ehw->misc_intr_mask;
+
+	/*
+	 * TODO - error logging
+	 */
+	if (misc_intr_status == 0)
+		return IRQ_NONE;
+	else
+		edma_reg_write(EDMA_REG_MISC_INT_MASK, EDMA_MASK_INT_DISABLE);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * edma_handle_irq()
+ *	Process IRQ and schedule napi
+ */
+irqreturn_t edma_handle_irq(int irq, void *ctx)
+{
+	uint32_t reg_data = 0;
+	uint32_t rxdesc_intr_status = 0;
+	uint32_t txcmpl_intr_status = 0;
+	uint32_t rxfill_intr_status = 0;
+	int i;
+	struct edma_txcmpl_ring *txcmpl_ring = NULL;
+	struct edma_rxdesc_ring *rxdesc_ring = NULL;
+	struct edma_rxfill_ring *rxfill_ring = NULL;
+	struct edma_hw *ehw = NULL;
+	struct platform_device *pdev = (struct platform_device *)ctx;
+
+	ehw = platform_get_drvdata(pdev);
+	if (!ehw) {
+		pr_info("Unable to retrieve platrofm data");
+		return IRQ_HANDLED;
+	}
+
+	/*
+	 * Read RxDesc intr status
+	 */
+	for (i = 0; i < ehw->rxdesc_rings; i++) {
+		rxdesc_ring = &ehw->rxdesc_ring[i];
+		reg_data = edma_reg_read(
+				EDMA_REG_RXDESC_INT_STAT(rxdesc_ring->id));
+		rxdesc_intr_status |= reg_data &
+				EDMA_RXDESC_RING_INT_STATUS_MASK;
+
+		/*
+		 * Disable RxDesc intr
+		 */
+		edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id),
+			       EDMA_MASK_INT_DISABLE);
+	}
+
+	/*
+	 * Read TxCmpl intr status
+	 */
+	for (i = 0; i < ehw->txcmpl_rings; i++) {
+		txcmpl_ring = &ehw->txcmpl_ring[i];
+		reg_data = edma_reg_read(
+				EDMA_REG_TX_INT_STAT(txcmpl_ring->id));
+		txcmpl_intr_status |= reg_data &
+				EDMA_TXCMPL_RING_INT_STATUS_MASK;
+
+		/*
+		 * Disable TxCmpl intr
+		 */
+		edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id),
+				EDMA_MASK_INT_DISABLE);
+	}
+
+	/*
+	 * Read RxFill intr status
+	 */
+	for (i = 0; i < ehw->rxfill_rings; i++) {
+		rxfill_ring = &ehw->rxfill_ring[i];
+		reg_data = edma_reg_read(
+				EDMA_REG_RXFILL_INT_STAT(rxfill_ring->id));
+		rxfill_intr_status |= reg_data &
+				EDMA_RXFILL_RING_INT_STATUS_MASK;
+
+		/*
+		 * Disable RxFill intr
+		 */
+		edma_reg_write(EDMA_REG_RXFILL_INT_MASK(rxfill_ring->id),
+			       EDMA_MASK_INT_DISABLE);
+
+	}
+
+	if ((rxdesc_intr_status == 0) && (txcmpl_intr_status == 0) &&
+			(rxfill_intr_status == 0))
+		return IRQ_NONE;
+
+	for (i = 0; i < ehw->rxdesc_rings; i++) {
+		rxdesc_ring = &ehw->rxdesc_ring[i];
+		edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id),
+			       EDMA_MASK_INT_DISABLE);
+	}
+
+	/*
+	 *TODO - per core NAPI
+	 */
+	if (rxdesc_intr_status || txcmpl_intr_status || rxfill_intr_status)
+		if (likely(napi_schedule_prep(&ehw->napi)))
+			__napi_schedule(&ehw->napi);
+
+	return IRQ_HANDLED;
+}
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/include/nss_dp_hal_info.h b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/include/nss_dp_hal_info.h
new file mode 100644
index 0000000..f0a4ecb
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v1/include/nss_dp_hal_info.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_HAL_INFO_H__
+#define __NSS_DP_HAL_INFO_H__
+
+/*
+ * nss_dp_hal_info
+ *	Data plane specific information wrapper
+ */
+struct nss_dp_hal_info {
+};
+
+#endif	/* __NSS_DP_HAL_INFO_H__ */
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma.c b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma.c
new file mode 100644
index 0000000..d14abd0
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma.c
@@ -0,0 +1,1357 @@
+/*
+ * Copyright (c) 2021-2022, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/debugfs.h>
+#include <linux/interrupt.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/irq.h>
+#include <linux/reset.h>
+#include <fal/fal_qm.h>
+#include <fal/fal_rss_hash.h>
+#include <fal/fal_servcode.h>
+#include <linux/clk.h>
+#include "edma.h"
+#include "edma_cfg_tx.h"
+#include "edma_cfg_rx.h"
+#include "edma_regs.h"
+#include "edma_debug.h"
+#include "edma_debugfs.h"
+
+/*
+ * EDMA hardware instance
+ */
+struct edma_gbl_ctx edma_gbl_ctx;
+
+static char edma_txcmpl_irq_name[EDMA_MAX_TXCMPL_RINGS][EDMA_IRQ_NAME_SIZE];
+static char edma_rxdesc_irq_name[EDMA_MAX_RXDESC_RINGS][EDMA_IRQ_NAME_SIZE];
+
+/*
+ * edma_disable_interrupts()
+ *	Disable EDMA RX/TX interrupt masks.
+ */
+void edma_disable_interrupts(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	for (i = 0; i < egc->num_rxdesc_rings; i++) {
+		struct edma_rxdesc_ring *rxdesc_ring =
+				&egc->rxdesc_rings[i];
+		edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->ring_id),
+				EDMA_MASK_INT_CLEAR);
+	}
+
+	for (i = 0; i < egc->num_txcmpl_rings; i++) {
+		struct edma_txcmpl_ring *txcmpl_ring =
+				&egc->txcmpl_rings[i];
+		edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id),
+				EDMA_MASK_INT_CLEAR);
+	}
+
+	/*
+	 * Clear MISC interrupt mask.
+	 */
+	edma_reg_write(EDMA_REG_MISC_INT_MASK, EDMA_MASK_INT_CLEAR);
+}
+
+/*
+ * edma_enable_interrupts()
+ *	Enable RX/TX EDMA interrupt masks.
+ */
+void edma_enable_interrupts(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	for (i = 0; i < egc->num_rxdesc_rings; i++) {
+		struct edma_rxdesc_ring *rxdesc_ring =
+				&egc->rxdesc_rings[i];
+		edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->ring_id),
+				egc->rxdesc_intr_mask);
+	}
+
+	for (i = 0; i < egc->num_txcmpl_rings; i++) {
+		struct edma_txcmpl_ring *txcmpl_ring =
+				&egc->txcmpl_rings[i];
+		edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id),
+				egc->txcmpl_intr_mask);
+	}
+
+	/*
+	 * Enable MISC interrupt mask.
+	 */
+	edma_reg_write(EDMA_REG_MISC_INT_MASK, egc->misc_intr_mask);
+}
+
+/*
+ * edma_disable_port()
+ *	EDMA disable port
+ */
+static void edma_disable_port(void)
+{
+	edma_reg_write(EDMA_REG_PORT_CTRL, EDMA_DISABLE);
+}
+
+/*
+ * edma_cfg_sc_bypass
+ *	Set service code to disable PPE processing
+ *
+ * TODO: Use PPE APIs when they are available.
+ */
+static sw_error_t edma_cfg_sc_bypass(struct edma_gbl_ctx *egc)
+{
+	sw_error_t ret;
+	fal_servcode_config_t entry = {0};
+	entry.bypass_bitmap[0] = ~((1 << FAKE_MAC_HEADER_BYP)
+					| (1 << SERVICE_CODE_BYP)
+					| (1 << FAKE_L2_PROTO_BYP));
+	entry.bypass_bitmap[1] = ~(1 << ACL_POST_ROUTING_CHECK_BYP);
+
+	ret = fal_servcode_config_set(0, EDMA_SC_BYPASS, &entry);
+	if (ret < 0) {
+		edma_err("%px: Error in configuring service code %d\n", egc, ret);
+	}
+
+	return ret;
+}
+
+/*
+ * edma_cleanup()
+ *	EDMA cleanup
+ */
+void edma_cleanup(bool is_dp_override)
+{
+	/*
+	 * The cleanup can happen from data plane override
+	 * or from module_exit, we want to cleanup only once
+	 *
+	 * On cleanup, disable EDMA only at module exit time, since
+	 * NSS firmware depends on this setting.
+	 */
+	if (!edma_gbl_ctx.edma_initialized) {
+		if (!is_dp_override) {
+			edma_disable_port();
+		}
+		return;
+	}
+
+	if (edma_gbl_ctx.ctl_table_hdr) {
+		unregister_sysctl_table(edma_gbl_ctx.ctl_table_hdr);
+		edma_gbl_ctx.ctl_table_hdr = NULL;
+	}
+
+	/*
+	 * TODO: Check with HW team about the state of in-flight
+	 * packets when the descriptor rings are disabled.
+	 */
+	edma_cfg_tx_rings_disable(&edma_gbl_ctx);
+	edma_cfg_rx_rings_disable(&edma_gbl_ctx);
+
+	edma_disable_interrupts(&edma_gbl_ctx);
+
+	/*
+	 * Remove interrupt handlers and NAPI
+	 */
+	if (edma_gbl_ctx.napi_added) {
+		uint32_t i;
+
+		/*
+		 * Free IRQ for TXCMPL rings
+		 */
+		for (i = 0; i < edma_gbl_ctx.num_txcmpl_rings; i++) {
+			synchronize_irq(edma_gbl_ctx.txcmpl_intr[i]);
+
+			free_irq(edma_gbl_ctx.txcmpl_intr[i],
+					(void *)&(edma_gbl_ctx.txcmpl_rings[i]));
+		}
+
+		/*
+		 * Free IRQ for RXDESC rings
+		 */
+		for (i = 0; i < edma_gbl_ctx.num_rxdesc_rings; i++) {
+			synchronize_irq(edma_gbl_ctx.rxdesc_intr[i]);
+			free_irq(edma_gbl_ctx.rxdesc_intr[i],
+					(void *)&(edma_gbl_ctx.rxdesc_rings[i]));
+		}
+
+		/*
+		 * Free Misc IRQ
+		 */
+		synchronize_irq(edma_gbl_ctx.misc_intr);
+		free_irq(edma_gbl_ctx.misc_intr, (void *)(edma_gbl_ctx.pdev));
+
+		edma_cfg_rx_napi_delete(&edma_gbl_ctx);
+		edma_cfg_tx_napi_delete(&edma_gbl_ctx);
+		edma_gbl_ctx.napi_added = false;
+	}
+
+	/*
+	 * Disable EDMA only at module exit time, since NSS firmware
+	 * depends on this setting.
+	 */
+	if (!is_dp_override) {
+		edma_disable_port();
+	}
+
+	/*
+	 * cleanup rings and free
+	 */
+	edma_cfg_tx_rings_cleanup(&edma_gbl_ctx);
+	edma_cfg_rx_rings_cleanup(&edma_gbl_ctx);
+
+	iounmap(edma_gbl_ctx.reg_base);
+	release_mem_region((edma_gbl_ctx.reg_resource)->start,
+			resource_size(edma_gbl_ctx.reg_resource));
+
+	/*
+	 * Clean the debugfs entries for the EDMA
+	 */
+	edma_debugfs_exit();
+
+	/*
+	 * Mark initialize false, so that we do not
+	 * try to cleanup again
+	 */
+	edma_gbl_ctx.edma_initialized = false;
+}
+
+/*
+ * edma_validate_desc_map()
+ *	Validate descriptor maps received from the dtsi
+ */
+static bool edma_validate_desc_map(void)
+{
+	uint32_t i, j, desc_bitmap = 0;
+	int32_t txdesc_port_arr[EDMA_MAX_TXDESC_RINGS] = {0};
+
+	for (i = 0; i < EDMA_TX_RING_PER_CORE_MAX; i++) {
+		for_each_possible_cpu(j) {
+			int32_t desc_num = edma_gbl_ctx.tx_map[i][j];
+			if (desc_num < 0) {
+				continue;
+			}
+
+			if (desc_num >= EDMA_MAX_TXDESC_RINGS) {
+				edma_err("desc number (%d) at tx_map[%d][%d] greater"
+						" than the max txdesc ring count\n",
+						 desc_num, i, j);
+				return false;
+			}
+
+			/*
+			 * Check if the user is trying to map the same descriptor
+			 * for multiple ports.
+			 * If that is the case, then return failure.
+			 */
+			if (desc_bitmap & (1 << desc_num)) {
+				if (txdesc_port_arr[desc_num] == i) {
+					continue;
+				} else {
+					edma_err("desc number (%d) already in use by other"
+						       " port (%d)\n", desc_num,
+						       txdesc_port_arr[desc_num]);
+					return false;
+				}
+			}
+
+			desc_bitmap |= (1 << desc_num);
+			txdesc_port_arr[desc_num] = i;
+		}
+	}
+
+	desc_bitmap = 0;
+
+	for_each_possible_cpu(i) {
+		int32_t desc_num = edma_gbl_ctx.rxdesc_ring_map[0][i];
+		if (desc_num < 0) {
+			continue;
+		}
+
+		if (desc_num >= EDMA_MAX_RXDESC_RINGS) {
+			edma_err("desc number (%d) at rxdesc_map[%d][%d] is greater than"
+				       " the max rxdesc rings allowed\n",
+				       desc_num, 0, i);
+			return false;
+		}
+
+		if (desc_bitmap & (1 << desc_num)) {
+			edma_err("desc num (%d) already present in the rexdesc ring map\n",
+					desc_num);
+			return false;
+		}
+
+		desc_bitmap |= (1 << desc_num);
+	}
+
+	return true;
+}
+
+/*
+ * edma_of_get_pdata()
+ *	Read the device tree details for EDMA
+ */
+static int edma_of_get_pdata(struct resource *edma_res)
+{
+	int ret;
+	uint32_t i, j;
+
+	/*
+	 * Find EDMA node in device tree
+	 */
+	edma_gbl_ctx.device_node = of_find_node_by_name(NULL,
+				EDMA_DEVICE_NODE_NAME);
+	if (!edma_gbl_ctx.device_node) {
+		edma_err("EDMA device tree node (%s) not found\n",
+				EDMA_DEVICE_NODE_NAME);
+		return -EINVAL;
+	}
+
+	/*
+	 * Get EDMA device node
+	 */
+	edma_gbl_ctx.pdev = of_find_device_by_node(edma_gbl_ctx.device_node);
+	if (!edma_gbl_ctx.pdev) {
+		edma_err("Platform device for node %px(%s) not found\n",
+				edma_gbl_ctx.device_node,
+				(edma_gbl_ctx.device_node)->name);
+		return -EINVAL;
+	}
+
+	/*
+	 * Get EDMA register resource
+	 */
+	if (of_address_to_resource(edma_gbl_ctx.device_node, 0, edma_res) != 0) {
+		edma_err("Unable to get register address for edma device: "
+			  EDMA_DEVICE_NODE_NAME"\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Get id of first TXDESC ring
+	 */
+	if (of_property_read_u32(edma_gbl_ctx.device_node, "qcom,txdesc-ring-start",
+				&edma_gbl_ctx.txdesc_ring_start) != 0) {
+		edma_err("Read error 1st TXDESC ring (txdesc_ring_start)\n");
+		return -EINVAL;
+	}
+
+	if (edma_gbl_ctx.txdesc_ring_start >= EDMA_MAX_TXDESC_RINGS) {
+		edma_err("Incorrect txdesc-ring-start value (%d) received as input\n",
+				edma_gbl_ctx.txdesc_ring_start);
+		return -EINVAL;
+	}
+	edma_debug("txdesc ring start: %d\n", edma_gbl_ctx.txdesc_ring_start);
+
+	/*
+	 * Get number of TXDESC rings
+	 */
+	if (of_property_read_u32(edma_gbl_ctx.device_node, "qcom,txdesc-rings",
+				&edma_gbl_ctx.num_txdesc_rings) != 0) {
+		edma_err("Unable to read number of txdesc rings.\n");
+		return -EINVAL;
+	}
+
+	if (edma_gbl_ctx.num_txdesc_rings > EDMA_MAX_TXDESC_RINGS) {
+		edma_err("Invalid txdesc-rings value (%d) received as input\n",
+				edma_gbl_ctx.num_txdesc_rings);
+		return -EINVAL;
+	}
+
+	edma_gbl_ctx.txdesc_ring_end = edma_gbl_ctx.txdesc_ring_start +
+					edma_gbl_ctx.num_txdesc_rings;
+	if (edma_gbl_ctx.txdesc_ring_end > EDMA_MAX_TXDESC_RINGS) {
+		edma_err("Invalid Txdesc ring configuration: txdesc-ring-start (%d)"
+				" and txdesc-rings (%d)\n",
+				edma_gbl_ctx.txdesc_ring_start,
+				edma_gbl_ctx.num_txdesc_rings);
+		return -EINVAL;
+	}
+	edma_debug("txdesc rings count: %d, txdesc ring end: %d\n",
+			edma_gbl_ctx.num_txdesc_rings, edma_gbl_ctx.txdesc_ring_end);
+
+	/*
+	 * Get id of first TXCMPL ring
+	 */
+	if (of_property_read_u32(edma_gbl_ctx.device_node, "qcom,txcmpl-ring-start",
+				&edma_gbl_ctx.txcmpl_ring_start) != 0) {
+		edma_err("Read error 1st TXCMPL ring (txcmpl_ring_start)\n");
+		return -EINVAL;
+	}
+
+	if (edma_gbl_ctx.txcmpl_ring_start >= EDMA_MAX_TXCMPL_RINGS) {
+		edma_err("Incorrect txcmpl-ring-start value (%d) received as input\n",
+				edma_gbl_ctx.txcmpl_ring_start);
+		return -EINVAL;
+	}
+	edma_debug("txcmpl ring start: %d\n", edma_gbl_ctx.txcmpl_ring_start);
+
+	/*
+	 * Get number of TXCMPL rings
+	 */
+	if (of_property_read_u32(edma_gbl_ctx.device_node, "qcom,txcmpl-rings",
+				&edma_gbl_ctx.num_txcmpl_rings) != 0) {
+		edma_err("Unable to read number of txcmpl rings.\n");
+		return -EINVAL;
+	}
+
+	if (edma_gbl_ctx.num_txcmpl_rings > EDMA_MAX_TXCMPL_RINGS) {
+		edma_err("Invalid txcmpl-rings value (%d) received as input\n",
+				edma_gbl_ctx.num_txcmpl_rings);
+		return -EINVAL;
+	}
+
+	edma_gbl_ctx.txcmpl_ring_end = edma_gbl_ctx.txcmpl_ring_start +
+					edma_gbl_ctx.num_txcmpl_rings;
+	if (edma_gbl_ctx.txcmpl_ring_end > EDMA_MAX_TXCMPL_RINGS) {
+		edma_err("Invalid Txcmpl ring configuration: txcmpl-ring-start (%d)"
+				" and txcmpl-rings (%d)\n",
+				edma_gbl_ctx.txcmpl_ring_start,
+				edma_gbl_ctx.num_txcmpl_rings);
+		return -EINVAL;
+	}
+	edma_debug("txcmpl rings count: %d, txcmpl ring end: %d\n",
+			edma_gbl_ctx.num_txcmpl_rings, edma_gbl_ctx.txcmpl_ring_end);
+
+	/*
+	 * Get id of first RXFILL ring
+	 */
+	if (of_property_read_u32(edma_gbl_ctx.device_node, "qcom,rxfill-ring-start",
+				&edma_gbl_ctx.rxfill_ring_start) != 0) {
+		edma_err("Read error 1st RXFILL ring (rxfill-ring-start)\n");
+		return -EINVAL;
+	}
+
+	if (edma_gbl_ctx.rxfill_ring_start >= EDMA_MAX_RXFILL_RINGS) {
+		edma_err("Incorrect rxfill-ring-start value (%d) received as input\n",
+				edma_gbl_ctx.rxfill_ring_start);
+		return -EINVAL;
+	}
+	edma_debug("rxfill ring start: %d\n", edma_gbl_ctx.rxfill_ring_start);
+
+	/*
+	 * Get number of RXFILL rings
+	 */
+	if (of_property_read_u32(edma_gbl_ctx.device_node, "qcom,rxfill-rings",
+					&edma_gbl_ctx.num_rxfill_rings) != 0) {
+		edma_err("Unable to read number of rxfill rings.\n");
+		return -EINVAL;
+	}
+
+	if (edma_gbl_ctx.num_rxfill_rings > EDMA_MAX_RXFILL_RINGS) {
+		edma_err("Invalid rxfill-rings value (%d) received as input\n",
+				edma_gbl_ctx.num_rxfill_rings);
+		return -EINVAL;
+	}
+
+	edma_gbl_ctx.rxfill_ring_end = edma_gbl_ctx.rxfill_ring_start +
+					edma_gbl_ctx.num_rxfill_rings;
+	if (edma_gbl_ctx.rxfill_ring_end > EDMA_MAX_RXFILL_RINGS) {
+		edma_err("Invalid Rxfill ring configuration: rxfill-ring-start (%d)"
+				" and rxfill-rings (%d)\n",
+				edma_gbl_ctx.rxfill_ring_start,
+				edma_gbl_ctx.num_rxfill_rings);
+		return -EINVAL;
+	}
+	edma_debug("rxfill rings count: %d, rxfill ring end: %d\n",
+			edma_gbl_ctx.num_rxfill_rings, edma_gbl_ctx.rxfill_ring_end);
+
+	/*
+	 * Get page_mode of RXFILL rings
+	 * TODO: Move this setting to DP common node
+	 */
+#if !defined(NSS_DP_MEM_PROFILE_LOW) && !defined(NSS_DP_MEM_PROFILE_MEDIUM)
+	of_property_read_u32(edma_gbl_ctx.device_node, "qcom,rx-page-mode",
+					&edma_gbl_ctx.rx_page_mode);
+#endif
+
+	/*
+	 * Get id of first RXDESC ring
+	 */
+	if (of_property_read_u32(edma_gbl_ctx.device_node, "qcom,rxdesc-ring-start",
+				&edma_gbl_ctx.rxdesc_ring_start) != 0) {
+		edma_err("Read error 1st RXDESC ring (rxdesc-ring-start)\n");
+		return -EINVAL;
+	}
+
+	if (edma_gbl_ctx.rxdesc_ring_start >= EDMA_MAX_RXDESC_RINGS) {
+		edma_err("Incorrect rxdesc-ring-start value (%d) received as input\n",
+				edma_gbl_ctx.rxdesc_ring_start);
+		return -EINVAL;
+	}
+	edma_debug("rxdesc ring start: %d\n", edma_gbl_ctx.rxdesc_ring_start);
+
+	/*
+	 * Get number of RXDESC rings
+	 */
+	if (of_property_read_u32(edma_gbl_ctx.device_node, "qcom,rxdesc-rings",
+					&edma_gbl_ctx.num_rxdesc_rings) != 0) {
+		edma_err("Unable to read number of rxdesc rings.\n");
+		return -EINVAL;
+	}
+
+	if (edma_gbl_ctx.num_rxdesc_rings > EDMA_MAX_RXDESC_RINGS) {
+		edma_err("Invalid rxdesc-rings value (%d) received as input\n",
+				edma_gbl_ctx.num_rxdesc_rings);
+		return -EINVAL;
+	}
+
+	edma_gbl_ctx.rxdesc_ring_end = edma_gbl_ctx.rxdesc_ring_start +
+					edma_gbl_ctx.num_rxdesc_rings;
+	if (edma_gbl_ctx.rxdesc_ring_end > EDMA_MAX_RXDESC_RINGS) {
+		edma_err("Invalid Rxdesc ring configuration: rxdesc-ring-start (%d)"
+				" and rxdesc-rings (%d)\n",
+				edma_gbl_ctx.rxdesc_ring_start,
+				edma_gbl_ctx.num_rxdesc_rings);
+		return -EINVAL;
+	}
+	edma_debug("rxdesc rings count: %d, rxdesc ring end: %d\n",
+			edma_gbl_ctx.num_rxdesc_rings, edma_gbl_ctx.rxdesc_ring_end);
+
+	/*
+	 * Get Tx Map priority level
+	 */
+	if (of_property_read_u32(edma_gbl_ctx.device_node, "qcom,tx-map-priority-level",
+					&edma_gbl_ctx.tx_priority_level) != 0) {
+		edma_err("Unable to read Tx map priority level.\n");
+		return -EINVAL;
+	}
+
+	if (edma_gbl_ctx.tx_priority_level > EDMA_TX_MAX_PRIORITY_LEVEL) {
+		edma_err("Invalid tx priority value (%d), maximum possible"
+				" priority value is %u\n", edma_gbl_ctx.tx_priority_level,
+				EDMA_TX_MAX_PRIORITY_LEVEL);
+		return -EINVAL;
+	}
+	edma_debug("tx map priority level: %d\n", edma_gbl_ctx.tx_priority_level);
+
+	/*
+	 * Get Rx Map priority level
+	 */
+	if (of_property_read_u32(edma_gbl_ctx.device_node,
+					"qcom,rx-map-priority-level",
+					&edma_gbl_ctx.rx_priority_level) != 0) {
+		edma_err("Unable to read Rx map priority level.\n");
+		return -EINVAL;
+	}
+
+	if (edma_gbl_ctx.rx_priority_level > EDMA_RX_MAX_PRIORITY_LEVEL) {
+		edma_err("Invalid tx priority value (%d), maximum possible"
+				" priority value is %u\n",
+				edma_gbl_ctx.rx_priority_level,
+				EDMA_RX_MAX_PRIORITY_LEVEL);
+		return -EINVAL;
+	}
+	edma_debug("rx map priority level: %d\n",
+				edma_gbl_ctx.rx_priority_level);
+
+	/*
+	 * Get TXDESC Map
+	 */
+	ret = of_property_read_u32_array(edma_gbl_ctx.device_node,
+			"qcom,txdesc-map",
+			(int32_t *)edma_gbl_ctx.tx_map,
+			(EDMA_MAX_GMACS * EDMA_TX_MAX_PRIORITY_LEVEL * NR_CPUS));
+	if (ret) {
+		edma_err("Unable to read Tx map array. ret: %d\n", ret);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < EDMA_TX_RING_PER_CORE_MAX; i++) {
+		for_each_possible_cpu(j) {
+			edma_debug("txmap[%d][%d] = %d\n", i, j,
+					edma_gbl_ctx.tx_map[i][j]);
+		}
+	}
+
+	/*
+	 * Get TXDESC flow control Group ID Map
+	 */
+	ret = of_property_read_u32_array(edma_gbl_ctx.device_node,
+			"qcom,txdesc-fc-grp-map",
+			(int32_t *)edma_gbl_ctx.tx_fc_grp_map, EDMA_MAX_GMACS);
+	if (ret) {
+		edma_err("Unable to read TxDesc-Fc-Grp map array. \
+			ret: %d\n", ret);
+		return -EINVAL;
+	}
+
+	/*
+	 * Get RXDESC Map
+	 */
+	ret = of_property_read_u32_array(edma_gbl_ctx.device_node,
+			"qcom,rxdesc-map",
+			(int32_t *)edma_gbl_ctx.rxdesc_ring_map,
+			(EDMA_RXDESC_RING_PER_CORE_MAX * NR_CPUS));
+	if (ret) {
+		edma_err("Unable to read Rx ring map array. Return: %d\n", ret);
+		return -EINVAL;
+	}
+
+	for_each_possible_cpu(i) {
+		edma_debug("rxdesc_ring_map[%d] = %d\n", i,
+				edma_gbl_ctx.rxdesc_ring_map[0][i]);
+	}
+
+	return 0;
+}
+
+/*
+ * edma_alloc_rings()
+ *	Allocate and initialize EDMA rings
+ */
+static int edma_alloc_rings(struct edma_gbl_ctx *egc)
+{
+	if (edma_cfg_tx_rings_alloc(egc)) {
+		edma_err("Error in allocating tx rings\n");
+		return -ENOMEM;
+	}
+
+	if (edma_cfg_rx_rings_alloc(egc)) {
+		edma_err("Error in allocating rx rings\n");
+		goto rx_rings_alloc_fail;
+	}
+
+	return 0;
+
+rx_rings_alloc_fail:
+	edma_cfg_tx_rings_cleanup(egc);
+	return -ENOMEM;
+}
+
+/*
+ * edma_hw_reset()
+ *	Reset EDMA Hardware during initialization
+ */
+static int edma_hw_reset(struct edma_gbl_ctx *egc)
+{
+	struct reset_control *edma_hw_rst;
+	struct platform_device *pdev = egc->pdev;
+
+	edma_hw_rst = devm_reset_control_get(&pdev->dev, EDMA_HW_RESET_ID);
+	if (IS_ERR(edma_hw_rst)) {
+		edma_err("DTS Node: %s does not exist\n", EDMA_HW_RESET_ID);
+		return -EINVAL;
+	}
+
+	reset_control_assert(edma_hw_rst);
+	udelay(100);
+
+	reset_control_deassert(edma_hw_rst);
+	udelay(100);
+
+	edma_info("EDMA HW Reset completed succesfully\n");
+
+	return 0;
+}
+
+/*
+ * edma_init_ring_maps()
+ *	API to initialize TX/RX ring maps in the global context
+ */
+static void edma_init_ring_maps(void)
+{
+	uint32_t i, j;
+
+	for (i = 0; i < EDMA_MAX_TXDESC_RINGS; i++) {
+		edma_gbl_ctx.tx_to_txcmpl_map[i] = -1;
+	}
+
+	for (i = 0; i < EDMA_TX_RING_PER_CORE_MAX; i++) {
+		for_each_possible_cpu(j) {
+			edma_gbl_ctx.tx_map[i][j] = -1;
+		}
+	}
+
+	for (i = 0; i < EDMA_TXCMPL_RING_PER_CORE_MAX; i++) {
+		for_each_possible_cpu(j) {
+			edma_gbl_ctx.txcmpl_map[i][j] = -1;
+		}
+	}
+
+	for (i = 0; i < EDMA_MAX_GMACS; i++) {
+		edma_gbl_ctx.tx_fc_grp_map[i] = -1;
+	}
+}
+
+/*
+ * edma_configure_rps_hash_map()
+ *	Configure RPS hash map
+ *
+ * Map all possible hash values to queues used by the EDMA
+ * Rx rings in a round robin fashion. These queues are expected
+ * to be mapped to different Rx rings which are assigned to different
+ * cores using IRQ affinity configuration.
+ *
+ * TODO: Move hash map configuration to PPE driver.
+ */
+static void edma_configure_rps_hash_map(struct edma_gbl_ctx *egc)
+{
+	uint32_t hash, q_off = 0;
+	fal_rss_hash_config_t hash_cfg = {0};
+	sw_error_t error;
+
+	/*
+	 * Initialize the store
+	 */
+	for (hash = 0; hash < EDMA_RSS_HASH_MAX; hash++) {
+		fal_ucast_hash_map_set(0, EDMA_PORT_PROFILE_ID, hash, q_off);
+		edma_info("profile_id: %u, hash: %u, q_off: %u\n", EDMA_PORT_PROFILE_ID, hash, q_off);
+
+		q_off += EDMA_PORT_QUEUE_PER_CORE;
+		q_off %= EDMA_PORT_QUEUE_NUM;
+	}
+
+	/*
+	 * Configure initial seed and mask for hash.
+	 *
+	 * NOTE: In the event when the following RPS hash
+	 * configuration fails, all the traffic will go to
+	 * the Rx descriptor ring mapped to QID 0.
+	 */
+	hash_cfg.hash_seed = PPE_HASH_SEED_DEFAULT;
+	hash_cfg.hash_mask = PPE_HASH_MASK;
+	hash_cfg.hash_sip_mix[0] = PPE_HASH_MIX_V4_SIP;
+	hash_cfg.hash_dip_mix[0] = PPE_HASH_MIX_V4_DIP;
+	hash_cfg.hash_protocol_mix = PPE_HASH_MIX_V4_PROTO;
+	hash_cfg.hash_dport_mix = PPE_HASH_MIX_V4_DPORT;
+	hash_cfg.hash_sport_mix = PPE_HASH_MIX_V4_SPORT;
+
+	hash_cfg.hash_fin_inner[0] = (PPE_HASH_FIN_INNER_OUTER_0 & 0x1f);
+	hash_cfg.hash_fin_outer[0] = ((PPE_HASH_FIN_INNER_OUTER_0 >> 5) & 0x1f);
+	hash_cfg.hash_fin_inner[1] = (PPE_HASH_FIN_INNER_OUTER_1 & 0x1f);
+	hash_cfg.hash_fin_outer[1] = ((PPE_HASH_FIN_INNER_OUTER_1 >> 5) & 0x1f);
+	hash_cfg.hash_fin_inner[2] = (PPE_HASH_FIN_INNER_OUTER_2 & 0x1f);
+	hash_cfg.hash_fin_outer[2] = ((PPE_HASH_FIN_INNER_OUTER_2 >> 5) & 0x1f);
+	hash_cfg.hash_fin_inner[3] = (PPE_HASH_FIN_INNER_OUTER_3 & 0x1f);
+	hash_cfg.hash_fin_outer[3] = ((PPE_HASH_FIN_INNER_OUTER_3 >> 5) & 0x1f);
+	hash_cfg.hash_fin_inner[4] = (PPE_HASH_FIN_INNER_OUTER_4 & 0x1f);
+	hash_cfg.hash_fin_outer[4] = ((PPE_HASH_FIN_INNER_OUTER_4 >> 5) & 0x1f);
+
+	/*
+	 * Configure IPv4 RSS hash seed initialization
+	 */
+	error = fal_rss_hash_config_set(0, FAL_RSS_HASH_IPV4ONLY, &hash_cfg);
+	if (error != SW_OK) {
+		edma_err("IPv4 RSS hash initialization failed. ret: %d\n", error);
+	}
+
+	hash_cfg.hash_sip_mix[0] = PPE_HASH_SIPV6_MIX_0;
+	hash_cfg.hash_dip_mix[0] = PPE_HASH_DIPV6_MIX_0;
+	hash_cfg.hash_sip_mix[1] = PPE_HASH_SIPV6_MIX_1;
+	hash_cfg.hash_dip_mix[1] = PPE_HASH_DIPV6_MIX_1;
+	hash_cfg.hash_sip_mix[2] = PPE_HASH_SIPV6_MIX_2;
+	hash_cfg.hash_dip_mix[2] = PPE_HASH_DIPV6_MIX_2;
+	hash_cfg.hash_sip_mix[3] = PPE_HASH_SIPV6_MIX_3;
+	hash_cfg.hash_dip_mix[3] = PPE_HASH_DIPV6_MIX_3;
+
+	/*
+	 * Configure IPv6 RSS hash seed initialization
+	 */
+	error = fal_rss_hash_config_set(0, FAL_RSS_HASH_IPV6ONLY, &hash_cfg);
+	if (error != SW_OK) {
+		edma_err("IPv6 RSS hash initialization failed. ret: %d\n", error);
+	}
+}
+
+/*
+ * edma_hw_init()
+ *	EDMA hardware initialization
+ */
+static int edma_hw_init(struct edma_gbl_ctx *egc)
+{
+	int ret = 0;
+	uint32_t data;
+
+	data = edma_reg_read(EDMA_REG_MAS_CTRL);
+	edma_info("EDMA ver %d hw init\n", data);
+
+	/*
+	 * Setup private data structure
+	 */
+	egc->rxfill_intr_mask = EDMA_RXFILL_INT_MASK;
+	egc->rxdesc_intr_mask = EDMA_RXDESC_INT_MASK_PKT_INT;
+	egc->txcmpl_intr_mask = EDMA_TX_INT_MASK_PKT_INT;
+	egc->edma_initialized = false;
+	atomic_set(&egc->active_port_count, 0);
+
+	/*
+	 * Reset EDMA
+	 */
+	ret = edma_hw_reset(egc);
+	if (ret) {
+		edma_err("Error in resetting the hardware. ret: %d\n", ret);
+		return ret;
+	}
+
+	ret = (int)edma_cfg_sc_bypass(egc);
+	if (ret) {
+		edma_err("Error in configuring service code: %d\n", ret);
+		return ret;
+	}
+
+	/*
+	 * Set EDMA global page mode and jumbo MRU
+	 */
+	edma_cfg_rx_page_mode_and_jumbo(egc);
+
+	ret = edma_alloc_rings(egc);
+	if (ret) {
+		edma_err("Error in initializaing the rings. ret: %d\n", ret);
+		return ret;
+	}
+
+	/*
+	 * Disable interrupts
+	 */
+	edma_disable_interrupts(egc);
+
+	edma_cfg_rx_rings_disable(egc);
+	edma_cfg_tx_rings_disable(egc);
+
+	edma_cfg_tx_mapping(egc);
+	edma_cfg_rx_mapping(egc);
+
+	edma_cfg_tx_rings(egc);
+	edma_cfg_rx_rings(egc);
+
+	/*
+	 * Configure DMA request priority, DMA read burst length,
+	 * and AXI write size.
+	 */
+	data = EDMA_DMAR_BURST_LEN_SET(EDMA_BURST_LEN_ENABLE)
+		| EDMA_DMAR_REQ_PRI_SET(0)
+		| EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SET(31)
+		| EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SET(7)
+		| EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SET(7);
+	edma_reg_write(EDMA_REG_DMAR_CTRL, data);
+
+	/*
+	 * Misc error mask
+	 */
+	data = EDMA_MISC_AXI_RD_ERR_MASK |
+		EDMA_MISC_AXI_WR_ERR_MASK |
+		EDMA_MISC_RX_DESC_FIFO_FULL_MASK |
+		EDMA_MISC_RX_ERR_BUF_SIZE_MASK |
+		EDMA_MISC_TX_SRAM_FULL_MASK |
+		EDMA_MISC_TX_CMPL_BUF_FULL_MASK |
+		EDMA_MISC_DATA_LEN_ERR_MASK;
+	data |= EDMA_MISC_TX_TIMEOUT_MASK;
+	egc->misc_intr_mask = data;
+
+	edma_cfg_rx_rings_enable(egc);
+	edma_cfg_tx_rings_enable(egc);
+
+	/*
+	 * Global EDMA enable and padding enable
+	 */
+	data = EDMA_PORT_PAD_EN | EDMA_PORT_EDMA_EN;
+	edma_reg_write(EDMA_REG_PORT_CTRL, data);
+
+	/*
+	 * Initialize RPS hash map table
+	 */
+	edma_configure_rps_hash_map(egc);
+
+	egc->edma_initialized = true;
+
+	return 0;
+}
+
+/*
+ * edma_clock_set_and_enable()
+ *	API to set and enable the EDMA common clocks
+ */
+static int32_t edma_clock_set_and_enable(struct device *dev, const char *id, unsigned long rate)
+{
+	struct clk *clk = NULL;
+	int err;
+
+	clk = devm_clk_get(dev, id);
+	if (IS_ERR(clk)) {
+		edma_err("%px: Error in getting the %s clock\n", dev, id);
+		return -1;
+	}
+
+	if (rate) {
+		err = clk_set_rate(clk, rate);
+		if (err) {
+			edma_err("%px: Error in setting %s clock frequency\n", dev, id);
+			return -1;
+		}
+	}
+
+	err = clk_prepare_enable(clk);
+	if (err) {
+		edma_err("%px: Error in enabling %s clock\n", dev, id);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * edma_configure_clocks()
+ *	API to configure EDMA common clocks
+ */
+static int32_t edma_configure_clocks(void)
+{
+	struct platform_device *pdev = edma_gbl_ctx.pdev;
+	int32_t err;
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_CSR_CLK, EDMA_CSR_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_CSR_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_NSSNOC_CSR_CLK, EDMA_NSSNOC_CSR_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_NSSNOC_CSR_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_IMEM_QSB_CLK,
+					EDMA_IMEM_QSB_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_IMEM_QSB_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_NSSNOC_IMEM_QSB_CLK,
+					EDMA_NSSNOC_IMEM_QSB_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_NSSNOC_IMEM_QSB_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_IMEM_AHB_CLK,
+					EDMA_IMEM_AHB_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_IMEM_AHB_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_NSSNOC_IMEM_AHB_CLK,
+					EDMA_NSSNOC_IMEM_AHB_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_NSSNOC_IMEM_AHB_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_MEM_NOC_NSSNOC_CLK,
+					EDMA_MEM_NOC_NSSNOC_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_MEM_NOC_NSSNOC_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_TBU_CLK,
+					EDMA_TBU_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_TBU_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_TS_CLK, EDMA_TS_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_TS_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_NSSCC_CLK, EDMA_NSSCC_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_NSSCC_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_NSSCFG_CLK, EDMA_NSSCFG_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_NSSCFG_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_NSSCNOC_ATB_CLK,
+					EDMA_NSSCNOC_ATB_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_NSSCNOC_ATB_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_NSSNOC_MEM_NOC_1_CLK,
+					EDMA_NSSNOC_MEM_NOC_1_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_NSSNOC_MEM_NOC_1_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_NSSNOC_MEMNOC_CLK,
+					EDMA_NSSNOC_MEMNOC_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_NSSNOC_MEMNOC_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_NSSNOC_NSSCC_CLK,
+					EDMA_NSSNOC_NSSCC_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_NSSNOC_NSSCC_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_NSSNOC_PCNOC_1_CLK,
+					EDMA_NSSNOC_PCNOC_1_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_NSSNOC_PCNOC_1_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_NSSNOC_QOSGEN_REF_CLK,
+					EDMA_NSSNOC_QOSGEN_REF_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_NSSNOC_QOSGEN_REF_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_NSSNOC_SNOC_1_CLK,
+					EDMA_NSSNOC_SNOC_1_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_NSSNOC_SNOC_1_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_NSSNOC_SNOC_CLK,
+					EDMA_NSSNOC_SNOC_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_NSSNOC_SNOC_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_NSSNOC_TIMEOUT_REF_CLK,
+					EDMA_NSSNOC_TIMEOUT_REF_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_NSSNOC_TIMEOUT_REF_CLK);
+		return -1;
+	}
+
+	err = edma_clock_set_and_enable(&pdev->dev, EDMA_NSSNOC_XO_DCD_CLK,
+					EDMA_NSSNOC_XO_DCD_CLK_FREQ);
+	if (err) {
+		edma_err("Error in enabling %s clock\n", EDMA_NSSNOC_XO_DCD_CLK);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * edma_rx_flow_control_table
+ *	EDMA Rx flow control sysctl table
+ */
+static struct ctl_table edma_rx_flow_control_table[] = {
+	{
+		.procname	=	"rx_fc_enable",
+		.data		=	&edma_cfg_rx_fc_enable,
+		.maxlen		=	sizeof(int),
+		.mode		=	0644,
+		.proc_handler	=	edma_cfg_rx_fc_enable_handler
+	},
+	{}
+};
+
+/*
+ * edma_main
+ *	EDMA main directory
+ */
+static struct ctl_table edma_main[] = {
+	{
+		.procname	=	"edma",
+		.mode		=	0555,
+		.child		=	edma_rx_flow_control_table,
+	},
+	{}
+};
+
+/*
+ * edma_root
+ *	EDMA root directory
+ */
+static struct ctl_table edma_root[] = {
+	{
+		.procname	=	"net",
+		.mode		=	0555,
+		.child		=	edma_main,
+	},
+	{}
+};
+
+/*
+ * edma_init()
+ *	EDMA init
+ */
+int edma_init(void)
+{
+	int ret = 0;
+	struct resource res_edma;
+
+	/*
+	 * Check the EDMA state
+	 */
+	if (likely(edma_gbl_ctx.edma_initialized)) {
+		edma_debug("EDMA is already initialized");
+		return 0;
+	}
+
+	edma_init_ring_maps();
+
+	/*
+	 * Get all the DTS data needed
+	 */
+	if (edma_of_get_pdata(&res_edma) < 0) {
+		edma_err("Unable to get EDMA DTS data.\n");
+		return -EINVAL;
+	}
+
+	if (!edma_validate_desc_map()) {
+		edma_err("Incorrect desc map received\n");
+		return -EINVAL;
+	}
+
+	edma_gbl_ctx.ctl_table_hdr = register_sysctl_table(edma_root);
+	if (!edma_gbl_ctx.ctl_table_hdr) {
+		edma_err("sysctl table configuration failed");
+		return -EINVAL;
+	}
+
+	/*
+	 * Request memory region for EDMA registers
+	 */
+	edma_gbl_ctx.reg_resource = request_mem_region(res_edma.start,
+				resource_size(&res_edma),
+				EDMA_DEVICE_NODE_NAME);
+	if (!edma_gbl_ctx.reg_resource) {
+		edma_err("Unable to request EDMA register memory.\n");
+		unregister_sysctl_table(edma_gbl_ctx.ctl_table_hdr);
+		edma_gbl_ctx.ctl_table_hdr = NULL;
+		return -EFAULT;
+	}
+
+	/*
+	 * Remap register resource
+	 */
+	edma_gbl_ctx.reg_base = ioremap_nocache((edma_gbl_ctx.reg_resource)->start,
+				resource_size(edma_gbl_ctx.reg_resource));
+	if (!edma_gbl_ctx.reg_base) {
+		edma_err("Unable to remap EDMA register memory.\n");
+		ret = -EFAULT;
+		goto edma_init_remap_fail;
+	}
+
+	/*
+	 * Initialize EDMA debugfs entry
+	 */
+	ret = edma_debugfs_init();
+	if (ret < 0) {
+		edma_err("Error in EDMA debugfs init API. ret: %d\n", ret);
+		ret = -EINVAL;
+		goto edma_debugfs_init_fail;
+	}
+
+	/*
+	 * Configure the EDMA common clocks
+	 */
+	ret = edma_configure_clocks();
+	if (ret) {
+		edma_err("Error in configuring the common EDMA clocks\n");
+		ret = -EFAULT;
+		goto edma_hw_init_fail;
+	}
+
+	edma_info("EDMA common clocks are configured\n");
+
+	if (edma_hw_init(&edma_gbl_ctx) != 0) {
+		edma_err("Error in edma initialization\n");
+		ret = -EFAULT;
+		goto edma_hw_init_fail;
+	}
+
+	/*
+	 * We add NAPIs and register IRQs at the time of the first netdev open
+	 */
+	edma_gbl_ctx.napi_added = false;
+
+	return 0;
+
+edma_hw_init_fail:
+	edma_debugfs_exit();
+
+edma_debugfs_init_fail:
+	iounmap(edma_gbl_ctx.reg_base);
+
+edma_init_remap_fail:
+	release_mem_region((edma_gbl_ctx.reg_resource)->start,
+			resource_size(edma_gbl_ctx.reg_resource));
+	unregister_sysctl_table(edma_gbl_ctx.ctl_table_hdr);
+	edma_gbl_ctx.ctl_table_hdr = NULL;
+	return ret;
+}
+
+/*
+ * edma_irq_init()
+ *	Initialize interrupt handlers for the driver
+ */
+int edma_irq_init(void)
+{
+	int err;
+	uint32_t entry_num, i;
+
+	/*
+	 * Get TXCMPL rings IRQ numbers
+	 */
+	entry_num = 0;
+	for (i = 0; i < edma_gbl_ctx.num_txcmpl_rings; i++, entry_num++) {
+		edma_gbl_ctx.txcmpl_intr[i] =
+			platform_get_irq(edma_gbl_ctx.pdev, entry_num);
+		if (edma_gbl_ctx.txcmpl_intr[i] < 0) {
+			edma_err("%s: txcmpl_intr[%u] irq get failed\n",
+					(edma_gbl_ctx.device_node)->name, i);
+			return -1;
+		}
+
+		edma_debug("%s: txcmpl_intr[%u] = %u\n",
+				 (edma_gbl_ctx.device_node)->name,
+				 i, edma_gbl_ctx.txcmpl_intr[i]);
+	}
+
+	/*
+	 * Get RXDESC rings IRQ numbers
+	 *
+	 */
+	for (i = 0; i < edma_gbl_ctx.num_rxdesc_rings; i++, entry_num++) {
+		edma_gbl_ctx.rxdesc_intr[i] =
+			platform_get_irq(edma_gbl_ctx.pdev, entry_num);
+		if (edma_gbl_ctx.rxdesc_intr[i] < 0) {
+			edma_err("%s: rxdesc_intr[%u] irq get failed\n",
+					(edma_gbl_ctx.device_node)->name, i);
+			return -1;
+		}
+
+		edma_debug("%s: rxdesc_intr[%u] = %u\n",
+				 (edma_gbl_ctx.device_node)->name,
+				 i, edma_gbl_ctx.rxdesc_intr[i]);
+	}
+
+	/*
+	 * Get misc IRQ number
+	 */
+	edma_gbl_ctx.misc_intr = platform_get_irq(edma_gbl_ctx.pdev, entry_num);
+	if (edma_gbl_ctx.misc_intr < 0) {
+		edma_err("%s: misc_intr irq get failed\n", (edma_gbl_ctx.device_node)->name);
+		return -1;
+	}
+
+	edma_debug("%s: misc IRQ:%u\n", (edma_gbl_ctx.device_node)->name,
+						edma_gbl_ctx.misc_intr);
+
+
+	/*
+	 * Request IRQ for Tx complete rings
+	 */
+	for (i = 0; i < edma_gbl_ctx.num_txcmpl_rings; i++) {
+		snprintf(edma_txcmpl_irq_name[i], 32, "edma_txcmpl_%d", edma_gbl_ctx.txcmpl_ring_start + i);
+
+		irq_set_status_flags(edma_gbl_ctx.txcmpl_intr[i], IRQ_DISABLE_UNLAZY);
+
+		err = request_irq(edma_gbl_ctx.txcmpl_intr[i],
+				edma_tx_handle_irq, IRQF_SHARED,
+				edma_txcmpl_irq_name[i],
+				(void *)&(edma_gbl_ctx.txcmpl_rings[i]));
+		if (err) {
+			edma_err("TXCMPL ring IRQ:%d request %d failed\n",
+					edma_gbl_ctx.txcmpl_intr[i], i);
+			return -1;
+
+		}
+
+		edma_debug("TXCMPL ring(%d) IRQ:%d request success(%s)\n",
+					edma_gbl_ctx.txcmpl_ring_start + i,
+					edma_gbl_ctx.txcmpl_intr[i],
+					edma_txcmpl_irq_name[i]);
+	}
+
+	/*
+	 * Request IRQ for RXDESC rings
+	 */
+	for (i = 0; i < edma_gbl_ctx.num_rxdesc_rings; i++) {
+		snprintf(edma_rxdesc_irq_name[i], 20, "edma_rxdesc_%d", edma_gbl_ctx.rxdesc_ring_start + i);
+
+		irq_set_status_flags(edma_gbl_ctx.rxdesc_intr[i], IRQ_DISABLE_UNLAZY);
+
+		err = request_irq(edma_gbl_ctx.rxdesc_intr[i],
+				edma_rx_handle_irq, IRQF_SHARED,
+				edma_rxdesc_irq_name[i],
+				(void *)&(edma_gbl_ctx.rxdesc_rings[i]));
+		if (err) {
+			edma_err("RXDESC ring IRQ:%d request failed\n",
+					edma_gbl_ctx.rxdesc_intr[i]);
+			goto rx_desc_ring_intr_req_fail;
+		}
+
+		edma_debug("RXDESC ring(%d) IRQ:%d request success(%s)\n",
+					edma_gbl_ctx.rxdesc_ring_start + i,
+					edma_gbl_ctx.rxdesc_intr[i],
+					edma_rxdesc_irq_name[i]);
+	}
+
+	/*
+	 * Request Misc IRQ
+	 */
+	err = request_irq(edma_gbl_ctx.misc_intr, edma_misc_handle_irq,
+						IRQF_SHARED, "edma_misc",
+						(void *)edma_gbl_ctx.pdev);
+	if (err) {
+		edma_err("MISC IRQ:%d request failed\n",
+				edma_gbl_ctx.misc_intr);
+		goto misc_intr_req_fail;
+	}
+
+	return 0;
+
+misc_intr_req_fail:
+	/*
+	 * Free IRQ for RXDESC rings
+	 */
+	for (i = 0; i < edma_gbl_ctx.num_rxdesc_rings; i++) {
+		synchronize_irq(edma_gbl_ctx.rxdesc_intr[i]);
+
+		free_irq(edma_gbl_ctx.rxdesc_intr[i],
+				(void *)&(edma_gbl_ctx.rxdesc_rings[i]));
+	}
+
+rx_desc_ring_intr_req_fail:
+	/*
+	 * Free IRQ for TXCMPL rings
+	 */
+	for (i = 0; i < edma_gbl_ctx.num_txcmpl_rings; i++) {
+
+		synchronize_irq(edma_gbl_ctx.txcmpl_intr[i]);
+		free_irq(edma_gbl_ctx.txcmpl_intr[i],
+				(void *)&(edma_gbl_ctx.txcmpl_rings[i]));
+	}
+
+	return -1;
+}
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma.h b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma.h
new file mode 100644
index 0000000..2e1cb6b
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma.h
@@ -0,0 +1,304 @@
+/*
+ * Copyright (c) 2021-2022, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __EDMA_H__
+#define __EDMA_H__
+
+#include <linux/netdevice.h>
+#include <nss_dp_arch.h>
+#include <nss_dp_api_if.h>
+#include <nss_dp_hal_if.h>
+#include "edma_rx.h"
+#include "edma_tx.h"
+
+/*
+ * The driver uses kernel DMA constructs that assume an architecture
+ * where the view of physical addresses is consistent between SoC and
+ * IO device(EDMA).
+ * Note that this may not be compatible for platforms where this
+ * assumption is not true, for example IO devices with IOMMU support.
+ */
+#if defined(CONFIG_ARM_SMMU) || \
+	defined(CONFIG_IOMMU_SUPPORT)
+#error "Build Error: Platform is enabled with IOMMU/SMMU support."
+#endif
+
+#define EDMA_HW_RESET_ID		"edma_rst"
+#define EDMA_DEVICE_NODE_NAME		"edma"
+#define EDMA_START_GMACS		NSS_DP_HAL_START_IFNUM
+#define EDMA_MAX_GMACS			NSS_DP_HAL_MAX_PORTS
+#define EDMA_IRQ_NAME_SIZE		32
+#define EDMA_SC_BYPASS			1
+#define EDMA_NETDEV_FEATURES		NETIF_F_FRAGLIST \
+					| NETIF_F_SG \
+					| NETIF_F_RXCSUM \
+					| NETIF_F_HW_CSUM \
+					| NETIF_F_TSO \
+					| NETIF_F_TSO6;
+
+#define EDMA_SWITCH_DEV_ID	0
+#define EDMA_PPE_QUEUE_LEVEL	0
+#define EDMA_BITS_IN_WORD	32
+
+/*
+ * Bitmap for ring to PPE queue's mapping.
+ *
+ * A bitmap for 300 PPE queues requires 10 32bit integers
+ */
+#define EDMA_RING_MAPPED_QUEUE_BM_WORD_COUNT	10
+
+/*
+ * EDMA clock frequency: 352 MHZ
+ * So, one clock cycle = (1/352) micro seconds
+ *
+ * One timer unit is 128 clock cycles.
+ *
+ * So, therefore the microsecond to timer unit calculation is:
+ * Timer unit	= time in microseconds / (one clock cycle in microsecond * cycles in 1 timer unit)
+ * 		= ('x' microsecond * 352 / 128)
+ */
+#define EDMA_CLK_FREQ		352
+#define CYCLE_PER_TIMER_UNIT	128
+#define MICROSEC_TO_TIMER_UNIT(x)	(((x) * EDMA_CLK_FREQ) / CYCLE_PER_TIMER_UNIT)
+
+/*
+ * EDMA common clocks
+ */
+#define EDMA_CSR_CLK			"nss-csr-clk"
+#define EDMA_NSSNOC_CSR_CLK		"nss-nssnoc-csr-clk"
+#define EDMA_IMEM_QSB_CLK		"nss-imem-qsb-clk"
+#define EDMA_NSSNOC_IMEM_QSB_CLK	"nss-nssnoc-imem-qsb-clk"
+#define EDMA_IMEM_AHB_CLK		"nss-imem-ahb-clk"
+#define EDMA_NSSNOC_IMEM_AHB_CLK	"nss-nssnoc-imem-ahb-clk"
+#define EDMA_MEM_NOC_NSSNOC_CLK		"nss-mem-noc-nssnoc-clk"
+#define EDMA_TBU_CLK			"nss-tbu-clk"
+#define EDMA_TS_CLK			"nss-ts-clk"
+#define EDMA_NSSCC_CLK			"nss-nsscc-clk"
+#define EDMA_NSSCFG_CLK			"nss-nsscfg-clk"
+#define EDMA_NSSCNOC_ATB_CLK		"nss-nsscnoc-atb-clk"
+#define EDMA_NSSNOC_MEM_NOC_1_CLK	"nss-nssnoc-mem-noc-1-clk"
+#define EDMA_NSSNOC_MEMNOC_CLK		"nss-nssnoc-memnoc-clk"
+#define EDMA_NSSNOC_NSSCC_CLK		"nss-nssnoc-nsscc-clk"
+#define EDMA_NSSNOC_PCNOC_1_CLK		"nss-nssnoc-pcnoc-1-clk"
+#define EDMA_NSSNOC_QOSGEN_REF_CLK	"nss-nssnoc-qosgen-ref-clk"
+#define EDMA_NSSNOC_SNOC_1_CLK		"nss-nssnoc-snoc-1-clk"
+#define EDMA_NSSNOC_SNOC_CLK		"nss-nssnoc-snoc-clk"
+#define EDMA_NSSNOC_TIMEOUT_REF_CLK	"nss-nssnoc-timeout-ref-clk"
+#define EDMA_NSSNOC_XO_DCD_CLK		"nss-nssnoc-xo-dcd-clk"
+
+/*
+ * EDMA common clock's frequencies
+ */
+#define EDMA_CSR_CLK_FREQ			100000000
+#define EDMA_NSSNOC_CSR_CLK_FREQ		100000000
+#define EDMA_IMEM_QSB_CLK_FREQ			353000000
+#define EDMA_NSSNOC_IMEM_QSB_CLK_FREQ		353000000
+#define EDMA_IMEM_AHB_CLK_FREQ			100000000
+#define EDMA_NSSNOC_IMEM_AHB_CLK_FREQ		100000000
+#define EDMA_MEM_NOC_NSSNOC_CLK_FREQ		533333333
+#define EDMA_TBU_CLK_FREQ			533333333
+#define EDMA_TS_CLK_FREQ			24000000
+#define EDMA_NSSCC_CLK_FREQ			100000000
+#define EDMA_NSSCFG_CLK_FREQ			100000000
+#define EDMA_NSSCNOC_ATB_CLK_FREQ		240000000
+#define EDMA_NSSNOC_MEM_NOC_1_CLK_FREQ		533333333
+#define EDMA_NSSNOC_MEMNOC_CLK_FREQ		533333333
+#define EDMA_NSSNOC_NSSCC_CLK_FREQ		100000000
+#define EDMA_NSSNOC_PCNOC_1_CLK_FREQ		100000000
+#define EDMA_NSSNOC_QOSGEN_REF_CLK_FREQ		6000000
+#define EDMA_NSSNOC_SNOC_1_CLK_FREQ		342857143
+#define EDMA_NSSNOC_SNOC_CLK_FREQ		342857143
+#define EDMA_NSSNOC_TIMEOUT_REF_CLK_FREQ	6000000
+#define EDMA_NSSNOC_XO_DCD_CLK_FREQ		24000000
+
+#define EDMA_DESC_AVAIL_COUNT(head, tail, max) (((head) - (tail)) + (max)) & ((max) - 1)
+
+/*
+ * EDMA MISC status get macros
+ */
+#define EDMA_MISC_AXI_RD_ERR_STATUS_GET(x)	((x) & EDMA_MISC_AXI_RD_ERR_MASK)
+#define EDMA_MISC_AXI_WR_ERR_STATUS_GET(x)	(((x) & EDMA_MISC_AXI_WR_ERR_MASK) >> 1)
+#define EDMA_MISC_RX_DESC_FIFO_FULL_STATUS_GET(x)	(((x) & EDMA_MISC_RX_DESC_FIFO_FULL_MASK) >> 2)
+#define EDMA_MISC_RX_ERR_BUF_SIZE_STATUS_GET(x)		(((x) & EDMA_MISC_RX_ERR_BUF_SIZE_MASK) >> 3)
+#define EDMA_MISC_TX_SRAM_FULL_STATUS_GET(x)		(((x) & EDMA_MISC_TX_SRAM_FULL_MASK) >> 4)
+#define EDMA_MISC_TX_CMPL_BUF_FULL_STATUS_GET(x)		(((x) & EDMA_MISC_TX_CMPL_BUF_FULL_MASK) >> 5)
+#define EDMA_MISC_DATA_LEN_ERR_STATUS_GET(x)		(((x) & EDMA_MISC_DATA_LEN_ERR_MASK) >> 6)
+#define EDMA_MISC_TX_TIMEOUT_STATUS_GET(x)		(((x) & EDMA_MISC_TX_TIMEOUT_MASK) >> 7)
+
+/*
+ * edma_misc_stats
+ *	EDMA miscellaneous stats
+ */
+struct edma_misc_stats {
+	uint64_t edma_misc_axi_read_err;		/* AXI read error */
+	uint64_t edma_misc_axi_write_err;		/* AXI write error */
+	uint64_t edma_misc_rx_desc_fifo_full;		/* Rx descriptor FIFO full error */
+	uint64_t edma_misc_rx_buf_size_err;		/* Rx buffer size too small error */
+	uint64_t edma_misc_tx_sram_full;		/* Tx packet SRAM buffer full error */
+	uint64_t edma_misc_tx_data_len_err;		/* Tx data length error */
+	uint64_t edma_misc_tx_timeout;			/* Tx timeout error */
+	uint64_t edma_misc_tx_cmpl_buf_full;		/* Tx completion buffer full error */
+	struct u64_stats_sync syncp;			/* Synchronization pointer */
+};
+
+/*
+ * edma_pcpu_stats
+ *	EDMA per cpu stats data structure
+ */
+struct edma_pcpu_stats {
+	struct edma_rx_stats __percpu *rx_stats;
+			/* Per CPU Rx statistics */
+	struct edma_tx_stats __percpu *tx_stats;
+			/* Per CPU Tx statistics */
+};
+
+/*
+ * EDMA private data structure
+ */
+struct edma_gbl_ctx {
+	struct net_device *netdev_arr[EDMA_MAX_GMACS];
+			/* Net device for each GMAC port */
+	struct device_node *device_node;
+			/* Device tree node */
+	struct platform_device *pdev;
+			/* Platform device */
+	void __iomem *reg_base;
+			/* EDMA base register mapped address */
+	struct resource *reg_resource;
+			/* Memory resource */
+	atomic_t active_port_count;
+			/* Count of active number of ports */
+	bool napi_added;
+			/* NAPI flag */
+
+	struct ctl_table_header *ctl_table_hdr;
+			/* sysctl table entry */
+
+	struct edma_rxfill_ring *rxfill_rings;
+			/* Rx Fill Rings, SW is producer */
+	struct edma_rxdesc_ring *rxdesc_rings;
+			/* Rx Descriptor Rings, SW is consumer */
+	struct edma_txdesc_ring *txdesc_rings;
+			/* Tx Descriptor Ring, SW is producer */
+	struct edma_txcmpl_ring *txcmpl_rings;
+			/* Tx complete Ring, SW is consumer */
+
+	uint32_t rxfill_ring_map[EDMA_RXFILL_RING_PER_CORE_MAX][NR_CPUS];
+			/* Rx Fill ring per-core mapping from device tree */
+	uint32_t rxdesc_ring_map[EDMA_RXDESC_RING_PER_CORE_MAX][NR_CPUS];
+			/* Rx Descriptor ring per-core mapping from device tree */
+	uint32_t (*rxdesc_ring_to_queue_bm)[EDMA_RING_MAPPED_QUEUE_BM_WORD_COUNT];
+			/* Bitmap of mapped PPE queue ids of the Rx descriptor rings */
+	int32_t tx_to_txcmpl_map[EDMA_MAX_TXDESC_RINGS];
+			/* Tx ring to Tx complete ring mapping */
+	int32_t tx_map[EDMA_TX_RING_PER_CORE_MAX][NR_CPUS];
+			/* Per core Tx ring to core mapping */
+	int32_t tx_fc_grp_map[EDMA_MAX_GMACS];
+			/* Per GMAC TxDesc ring to flow control group mapping */
+	int32_t txcmpl_map[EDMA_TXCMPL_RING_PER_CORE_MAX][NR_CPUS];
+			/* Tx complete ring to core mapping */
+
+	struct dentry *root_dentry;	/* Root debugfs entry */
+	struct dentry *stats_dentry;	/* Statistics debugfs entry */
+
+	struct edma_misc_stats __percpu *misc_stats;
+			/* Per CPU miscellaneous statistics */
+
+	uint32_t tx_priority_level;
+			/* Tx priority level per port */
+	uint32_t rx_priority_level;
+			/* Rx priority level per core */
+	uint32_t num_txdesc_rings;
+			/* Number of TxDesc rings */
+	uint32_t txdesc_ring_start;
+			/* Id of first TXDESC ring */
+	uint32_t txdesc_ring_end;
+			/* Id of the last TXDESC ring */
+	uint32_t num_txcmpl_rings;
+			/* Number of TxCmpl rings */
+	uint32_t txcmpl_ring_start;
+			/* Id of first TXCMPL ring */
+	uint32_t txcmpl_ring_end;
+			/* Id of last TXCMPL ring */
+	uint32_t num_rxfill_rings;
+			/* Number of RxFill rings */
+	uint32_t rxfill_ring_start;
+			/* Id of first RxFill ring */
+	uint32_t rxfill_ring_end;
+			/* Id of last RxFill ring */
+	uint32_t num_rxdesc_rings;
+			/* Number of RxDesc rings */
+	uint32_t rxdesc_ring_start;
+			/* Id of first RxDesc ring */
+	uint32_t rxdesc_ring_end;
+			/* Id of last RxDesc ring */
+	uint32_t txcmpl_intr[EDMA_MAX_TXCMPL_RINGS];
+			/* TxCmpl ring IRQ numbers */
+	uint32_t rxfill_intr[EDMA_MAX_RXFILL_RINGS];
+			/* Rx fill ring IRQ numbers */
+	uint32_t rxdesc_intr[EDMA_MAX_RXDESC_RINGS];
+			/* Rx desc ring IRQ numbers */
+	uint32_t misc_intr;
+			/* Misc IRQ number */
+
+	uint32_t rxfill_intr_mask;
+			/* Rx fill ring interrupt mask */
+	uint32_t rxdesc_intr_mask;
+			/* Rx Desc ring interrupt mask */
+	uint32_t txcmpl_intr_mask;
+			/* Tx Cmpl ring interrupt mask */
+	uint32_t misc_intr_mask;
+			/* Misc interrupt interrupt mask */
+	uint32_t dp_override_cnt;
+			/* Number of interfaces overriden */
+	uint32_t rx_page_mode;
+			/* Page mode enabled or disabled */
+	uint32_t rx_jumbo_mru;
+			/* Jumbo MRU value */
+	bool edma_initialized;
+			/* Flag to check initialization status */
+};
+
+extern struct edma_gbl_ctx edma_gbl_ctx;
+
+int edma_irq_init(void);
+irqreturn_t edma_misc_handle_irq(int irq, void *ctx);
+int32_t edma_misc_stats_alloc(void);
+void edma_misc_stats_free(void);
+void edma_enable_interrupts(struct edma_gbl_ctx *egc);
+void edma_disable_interrupts(struct edma_gbl_ctx *egc);
+
+/*
+ * edma_reg_read()
+ *	Read EDMA register
+ */
+static inline uint32_t edma_reg_read(uint32_t reg_off)
+{
+	return hal_read_reg(edma_gbl_ctx.reg_base, reg_off);
+}
+
+/*
+ * edma_reg_write()
+ *	Write EDMA register
+ */
+static inline void edma_reg_write(uint32_t reg_off, uint32_t val)
+{
+	hal_write_reg(edma_gbl_ctx.reg_base, reg_off, val);
+}
+
+#endif	/* __EDMA_H__ */
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_cfg_rx.c b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_cfg_rx.c
new file mode 100644
index 0000000..f370362
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_cfg_rx.c
@@ -0,0 +1,1163 @@
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/debugfs.h>
+#include <linux/interrupt.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/reset.h>
+#include <fal/fal_qos.h>
+#include <fal/fal_qm.h>
+#include "edma.h"
+#include "edma_cfg_rx.h"
+#include "edma_regs.h"
+#include "edma_debug.h"
+#include "nss_dp_dev.h"
+
+uint32_t edma_cfg_rx_fc_enable = EDMA_RX_FC_ENABLE;
+
+/*
+ * edma_cfg_rx_fill_ring_cleanup()
+ *	Cleanup resources for one RxFill ring
+ *
+ * API expects ring to be disabled by caller
+ */
+static void edma_cfg_rx_fill_ring_cleanup(struct edma_gbl_ctx *egc,
+				struct edma_rxfill_ring *rxfill_ring)
+{
+	uint16_t cons_idx, curr_idx;
+	uint32_t reg_data;
+
+	/*
+	 * Get RXFILL ring producer index
+	 */
+	curr_idx = rxfill_ring->prod_idx & EDMA_RXFILL_PROD_IDX_MASK;
+
+	/*
+	 * Get RXFILL ring consumer index
+	 */
+	reg_data = edma_reg_read(EDMA_REG_RXFILL_CONS_IDX(rxfill_ring->ring_id));
+	cons_idx = reg_data & EDMA_RXFILL_CONS_IDX_MASK;
+
+	while (curr_idx != cons_idx) {
+		struct sk_buff *skb;
+		struct edma_rxfill_desc *rxfill_desc;
+
+		/*
+		 * Get RXFILL descriptor
+		 */
+		rxfill_desc = EDMA_RXFILL_DESC(rxfill_ring, cons_idx);
+
+		cons_idx = (cons_idx + 1) & EDMA_RX_RING_SIZE_MASK;
+
+		/*
+		 * Get skb from opaque
+		 */
+		skb = (struct sk_buff *)EDMA_RXFILL_OPAQUE_GET(rxfill_desc);
+		if (unlikely(!skb)) {
+			edma_warn("Empty skb reference at index:%d\n",
+					cons_idx);
+			continue;
+		}
+		dev_kfree_skb_any(skb);
+	}
+
+	/*
+	 * Free RXFILL ring descriptors
+	 */
+	kfree(rxfill_ring->desc);
+	rxfill_ring->desc = NULL;
+	rxfill_ring->dma = (dma_addr_t)0;
+}
+
+/*
+ * edma_cfg_rx_fill_ring_setup()
+ *	Setup resources for one RxFill ring
+ */
+static int edma_cfg_rx_fill_ring_setup(struct edma_rxfill_ring *rxfill_ring)
+{
+	/*
+	 * Allocate RxFill ring descriptors
+	 */
+	rxfill_ring->desc = kmalloc((sizeof(struct edma_rxfill_desc) * rxfill_ring->count) +
+				SMP_CACHE_BYTES,  GFP_KERNEL | __GFP_ZERO);
+	if (!rxfill_ring->desc) {
+		edma_err("Descriptor alloc for RXFILL ring %u failed\n",
+							rxfill_ring->ring_id);
+		return -ENOMEM;
+	}
+
+	rxfill_ring->dma = (dma_addr_t)virt_to_phys(rxfill_ring->desc);
+
+	return 0;
+}
+
+/*
+ * edma_cfg_rx_desc_ring_setup()
+ *	Setup resources for one RxDesc ring
+ */
+static int edma_cfg_rx_desc_ring_setup(struct edma_rxdesc_ring *rxdesc_ring)
+{
+	/*
+	 * Allocate RxDesc ring descriptors
+	 */
+	rxdesc_ring->pdesc = kmalloc((sizeof(struct edma_rxdesc_desc) *  rxdesc_ring->count) +
+				SMP_CACHE_BYTES,  GFP_KERNEL | __GFP_ZERO);
+	if (!rxdesc_ring->pdesc) {
+		edma_err("Descriptor alloc for RXDESC ring %u failed\n",
+							rxdesc_ring->ring_id);
+		return -ENOMEM;
+	}
+
+	rxdesc_ring->pdma = (dma_addr_t)virt_to_phys(rxdesc_ring->pdesc);
+
+	/*
+	 * Allocate secondary RxDesc ring descriptors
+	 */
+	rxdesc_ring->sdesc = kmalloc((sizeof(struct edma_rxdesc_sec_desc) *  rxdesc_ring->count) +
+				SMP_CACHE_BYTES,  GFP_KERNEL | __GFP_ZERO);
+	if (!rxdesc_ring->sdesc) {
+		edma_err("Descriptor alloc for secondary RX ring %u failed\n",
+							rxdesc_ring->ring_id);
+		kfree(rxdesc_ring->pdesc);
+		rxdesc_ring->pdesc = NULL;
+		rxdesc_ring->pdma = (dma_addr_t)0;
+		return -ENOMEM;
+	}
+
+	rxdesc_ring->sdma = (dma_addr_t)virt_to_phys(rxdesc_ring->sdesc);
+
+	return 0;
+}
+
+/*
+ * edma_cfg_rx_desc_ring_cleanup()
+ *	Cleanup resources for RxDesc ring
+ *
+ * API expects ring to be disabled by caller
+ */
+static void edma_cfg_rx_desc_ring_cleanup(struct edma_gbl_ctx *egc,
+				struct edma_rxdesc_ring *rxdesc_ring)
+{
+	uint16_t prod_idx, cons_idx;
+
+	/*
+	 * Get Rxdesc consumer & producer indices
+	 */
+	cons_idx = rxdesc_ring->cons_idx & EDMA_RXDESC_CONS_IDX_MASK;
+
+	prod_idx = edma_reg_read(EDMA_REG_RXDESC_PROD_IDX(rxdesc_ring->ring_id))
+					& EDMA_RXDESC_PROD_IDX_MASK;
+
+	/*
+	 * Free any buffers assigned to any descriptors
+	 */
+	while (cons_idx != prod_idx) {
+		struct sk_buff *skb;
+		struct edma_rxdesc_desc *rxdesc_desc =
+			EDMA_RXDESC_PRI_DESC(rxdesc_ring, cons_idx);
+
+		/*
+		 * Update consumer index
+		 */
+		cons_idx = (cons_idx + 1) & EDMA_RX_RING_SIZE_MASK;
+
+		/*
+		 * Get opaque from RXDESC
+		 */
+		skb = (struct sk_buff *)EDMA_RXDESC_OPAQUE_GET(rxdesc_desc);
+		if (unlikely(!skb)) {
+			edma_warn("Empty skb reference at index:%d\n",
+								cons_idx);
+			continue;
+		}
+		dev_kfree_skb_any(skb);
+	}
+
+	/*
+	 * Free RXDESC ring descriptors
+	 */
+	kfree(rxdesc_ring->pdesc);
+	rxdesc_ring->pdesc = NULL;
+	rxdesc_ring->pdma = (dma_addr_t)0;
+
+	/*
+	 * TODO:
+	 * Free any buffers assigned to any secondary ring descriptors
+	 */
+	kfree(rxdesc_ring->sdesc);
+	rxdesc_ring->sdesc = NULL;
+	rxdesc_ring->sdma = (dma_addr_t)0;
+}
+
+/*
+ * edma_cfg_rx_desc_rings_reset_queue_mapping()
+ *	API to reset Rx descriptor rings to PPE queues mapping
+ */
+static int32_t edma_cfg_rx_desc_rings_reset_queue_mapping(void)
+{
+	fal_queue_bmp_t queue_bmp = {0};
+	int32_t i;
+
+	for (i = 0; i < EDMA_MAX_RXDESC_RINGS; i++) {
+		if (fal_edma_ring_queue_map_set(EDMA_SWITCH_DEV_ID, i, &queue_bmp) != SW_OK) {
+			edma_err("Error in unmapping rxdesc ring %d to PPE queue mapping to"
+					" disable its backpressure configuration\n", i);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * edma_cfg_rx_desc_ring_reset_queue_priority()
+ *	API to reset the priority for PPE queues mapped to Rx rings
+ */
+static int32_t edma_cfg_rx_desc_ring_reset_queue_priority(struct edma_gbl_ctx *egc,
+				uint32_t rxdesc_ring_idx)
+{
+	fal_qos_scheduler_cfg_t qsch;
+	uint32_t i, queue_id, bit_set, port_id, cur_queue_word;
+
+	for (i = 0; i < EDMA_RING_MAPPED_QUEUE_BM_WORD_COUNT; i++) {
+		cur_queue_word = egc->rxdesc_ring_to_queue_bm[rxdesc_ring_idx][i];
+		if (cur_queue_word == 0) {
+			continue;
+		}
+
+		do {
+			bit_set = ffs((uint32_t)cur_queue_word);
+			queue_id = (((i * EDMA_BITS_IN_WORD) + bit_set) - 1);
+			memset(&qsch, 0, sizeof(fal_qos_scheduler_cfg_t));
+			if (fal_queue_scheduler_get(EDMA_SWITCH_DEV_ID, queue_id,
+						EDMA_PPE_QUEUE_LEVEL, &port_id, &qsch) != SW_OK) {
+				edma_err("Error in getting %u queue's priority information\n", queue_id);
+				return -1;
+			}
+
+			/*
+			 * Configure the default queue priority.
+			 * In IPQ95xx, currently single queue is being mapped to the
+			 * single Rx descriptor ring and each ring will be processed
+			 * on the separate core. Therefore assigning same priority to
+			 * all these mapped queues.
+			 */
+			qsch.e_pri = EDMA_RX_DEFAULT_QUEUE_PRI;
+			qsch.c_pri = EDMA_RX_DEFAULT_QUEUE_PRI;
+			if (fal_queue_scheduler_set(EDMA_SWITCH_DEV_ID, queue_id,
+						EDMA_PPE_QUEUE_LEVEL, port_id, &qsch) != SW_OK) {
+				edma_err("Error in resetting %u queue's priority\n", queue_id);
+				return -1;
+			}
+
+			cur_queue_word &= ~(1 << (bit_set - 1));
+		} while (cur_queue_word);
+	}
+
+	return 0;
+}
+
+/*
+ * edma_cfg_rx_desc_ring_reset_queue_config()
+ *	API to reset the Rx descriptor rings configurations
+ */
+static int32_t edma_cfg_rx_desc_ring_reset_queue_config(struct edma_gbl_ctx *egc)
+{
+	int32_t i;
+
+	/*
+	 * Unmap Rxdesc ring to PPE queue mapping to reset its backpressure configuration
+	 */
+	if (edma_cfg_rx_desc_rings_reset_queue_mapping()) {
+		edma_err("Error in resetting Rx desc ring backpressure configurations\n");
+		return -1;
+	}
+
+	/*
+	 * Reset the priority for PPE queues mapped to Rx rings
+	 */
+	for (i = 0; i < egc->num_rxdesc_rings; i++) {
+		if(edma_cfg_rx_desc_ring_reset_queue_priority(egc, i)) {
+			edma_err("Error in resetting ring:%d queue's priority\n",
+					 i + egc->rxdesc_ring_start);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * edma_cfg_rx_desc_ring_to_queue_mapping()
+ *	API to map Rx descriptor rings to PPE queue for backpressure
+ */
+static void edma_cfg_rx_desc_ring_to_queue_mapping(uint32_t enable)
+{
+	uint32_t i, j;
+	sw_error_t ret;
+	fal_queue_bmp_t queue_bmp = {0};
+
+	/*
+	 * Rxdesc ring to PPE queue mapping
+	 */
+	for (i = 0; i < edma_gbl_ctx.num_rxdesc_rings; i++) {
+		struct edma_rxdesc_ring *rxdesc_ring;
+
+		rxdesc_ring = &edma_gbl_ctx.rxdesc_rings[i];
+		if (enable) {
+			memcpy(queue_bmp.bmp, edma_gbl_ctx.rxdesc_ring_to_queue_bm[i],
+					sizeof(uint32_t) * EDMA_RING_MAPPED_QUEUE_BM_WORD_COUNT);
+		}
+
+		ret = fal_edma_ring_queue_map_set(0, rxdesc_ring->ring_id, &queue_bmp);
+		if (ret != SW_OK) {
+			edma_err("Error in configuring Rx ring to PPE queue mapping."
+					" ret: %d, id: %d, queue: %d\n",
+					ret, rxdesc_ring->ring_id, queue_bmp.bmp[0]);
+			if (edma_cfg_rx_desc_rings_reset_queue_mapping()) {
+				edma_err("Error in resetting Rx desc ring backpressure configurations\n");
+			}
+			return;
+		}
+
+		edma_info("Rx desc ring %d to PPE queue mapping for backpressure:\n",
+				rxdesc_ring->ring_id);
+		for (j = 0; j < EDMA_RING_MAPPED_QUEUE_BM_WORD_COUNT; j++) {
+			edma_info("\tPPE queue bitmap[%d]: %0x\n", j, queue_bmp.bmp[j]);
+		}
+	}
+}
+
+/*
+ * edma_cfg_rx_fill_ring_flow_control()
+ *	Configure Rx fill ring flow control configuration
+ */
+static void edma_cfg_rx_fill_ring_flow_control(uint32_t threshold_xoff, uint32_t threshold_xon)
+{
+	uint32_t data, i;
+
+	data = (threshold_xoff & EDMA_RXFILL_FC_XOFF_THRE_MASK) << EDMA_RXFILL_FC_XOFF_THRE_SHIFT;
+	data |= ((threshold_xon & EDMA_RXFILL_FC_XON_THRE_MASK) << EDMA_RXFILL_FC_XON_THRE_SHIFT);
+
+	for (i = 0; i < edma_gbl_ctx.num_rxfill_rings; i++) {
+		struct edma_rxfill_ring *rxfill_ring;
+
+		rxfill_ring = &edma_gbl_ctx.rxfill_rings[i];
+		edma_reg_write(EDMA_REG_RXFILL_FC_THRE(rxfill_ring->ring_id), data);
+	}
+}
+
+/*
+ * edma_cfg_rx_desc_ring_flow_control()
+ *	Configure Rx descriptor ring flow control configuration
+ */
+static void edma_cfg_rx_desc_ring_flow_control(uint32_t threshold_xoff, uint32_t threshold_xon)
+{
+	uint32_t data, i;
+
+	data = (threshold_xoff & EDMA_RXDESC_FC_XOFF_THRE_MASK) << EDMA_RXDESC_FC_XOFF_THRE_SHIFT;
+	data |= ((threshold_xon & EDMA_RXDESC_FC_XON_THRE_MASK) << EDMA_RXDESC_FC_XON_THRE_SHIFT);
+	for (i = 0; i < edma_gbl_ctx.num_rxdesc_rings; i++) {
+		struct edma_rxdesc_ring *rxdesc_ring;
+
+		rxdesc_ring = &edma_gbl_ctx.rxdesc_rings[i];
+		edma_reg_write(EDMA_REG_RXDESC_FC_THRE(rxdesc_ring->ring_id), data);
+	}
+}
+
+/*
+ * edma_cfg_rx_mapped_queue_ac_fc_configure()
+ *	API to configure Rx descriptor mapped queue's AC FC threshold
+ *
+ * This will enable queue tail drop on the PPE queues mapped to Rx rings.
+ */
+static int32_t edma_cfg_rx_mapped_queue_ac_fc_configure(uint16_t threshold,
+				uint32_t enable)
+{
+	uint32_t i, j, cur_queue_word, bit_set, queue_id;
+	fal_ac_dynamic_threshold_t cfg;
+	fal_ac_obj_t obj;
+	fal_ac_ctrl_t ac_ctrl;
+	bool is_enable = (enable ? true: false);
+
+	for (i = 0; i < edma_gbl_ctx.num_rxdesc_rings; i++) {
+		struct edma_rxdesc_ring *rxdesc_ring;
+
+		rxdesc_ring = &edma_gbl_ctx.rxdesc_rings[i];
+
+		for (j = 0; j < EDMA_RING_MAPPED_QUEUE_BM_WORD_COUNT; j++) {
+			cur_queue_word = edma_gbl_ctx.rxdesc_ring_to_queue_bm[i][j];
+			if (cur_queue_word == 0) {
+				continue;
+			}
+
+			do {
+				bit_set = ffs((uint32_t)cur_queue_word);
+				queue_id = (((j * EDMA_BITS_IN_WORD) + bit_set) - 1);
+
+				/*
+				 * Configure the mapped queues AC FC configuration threshold
+				 */
+				memset(&cfg, 0, sizeof(fal_ac_dynamic_threshold_t));
+				if (fal_ac_dynamic_threshold_get(EDMA_SWITCH_DEV_ID,
+					queue_id, &cfg) != SW_OK) {
+					edma_err("Error in getting %d queue's AC FC threshold\n",
+							queue_id);
+					return -1;
+				}
+
+				/*
+				 * TODO:
+				 * Check if the threshold configuration can be done
+				 * once the time of initialization and then later the AC
+				 * FC configuration can be enabled/disabled from this API
+				 * or not.
+				 */
+				cfg.ceiling = threshold;
+				if (fal_ac_dynamic_threshold_set(EDMA_SWITCH_DEV_ID,
+						queue_id, &cfg) != SW_OK) {
+					edma_err("Error in configuring queue(%d) threshold"
+							" value:%d\n", queue_id, threshold);
+					return -1;
+				}
+
+				/*
+				 * Enable/disable the state of mapped queues AC FC configuration
+				 */
+				memset(&obj, 0, sizeof(fal_ac_obj_t));
+				memset(&ac_ctrl, 0, sizeof(fal_ac_ctrl_t));
+				obj.type = FAL_AC_QUEUE;
+				obj.obj_id = queue_id;
+				if (fal_ac_ctrl_get(EDMA_SWITCH_DEV_ID, &obj, &ac_ctrl) != SW_OK) {
+					edma_err("Error in getting %d queue's AC configuration\n",
+							obj.obj_id);
+					return -1;
+				}
+
+				ac_ctrl.ac_fc_en = is_enable;
+				if (fal_ac_ctrl_set(EDMA_SWITCH_DEV_ID, &obj, &ac_ctrl) != SW_OK) {
+					edma_err("Error in changing queue's ac_fc state:%d"
+							" for queue:%d", is_enable, obj.obj_id);
+					return -1;
+				}
+
+				cur_queue_word &= ~(1 << (bit_set - 1));
+			} while (cur_queue_word);
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * edma_cfg_rx_desc_ring_configure()
+ *	Configure one RxDesc ring in EDMA HW
+ */
+static void edma_cfg_rx_desc_ring_configure(struct edma_rxdesc_ring *rxdesc_ring)
+{
+	uint32_t data;
+
+	edma_reg_write(EDMA_REG_RXDESC_BA(rxdesc_ring->ring_id),
+			(uint32_t)(rxdesc_ring->pdma & EDMA_RXDESC_BA_MASK));
+
+	edma_reg_write(EDMA_REG_RXDESC_PREHEADER_BA(rxdesc_ring->ring_id),
+			(uint32_t)(rxdesc_ring->sdma & EDMA_RXDESC_PREHEADER_BA_MASK));
+
+	data = rxdesc_ring->count & EDMA_RXDESC_RING_SIZE_MASK;
+	data |= (EDMA_RXDESC_PL_DEFAULT_VALUE & EDMA_RXDESC_PL_OFFSET_MASK)
+		 << EDMA_RXDESC_PL_OFFSET_SHIFT;
+	edma_reg_write(EDMA_REG_RXDESC_RING_SIZE(rxdesc_ring->ring_id), data);
+
+	/*
+	 * Validate mitigation timer value
+	 */
+	if ((nss_dp_rx_mitigation_timer < EDMA_RX_MITIGATION_TIMER_MIN) ||
+			(nss_dp_rx_mitigation_timer > EDMA_RX_MITIGATION_TIMER_MAX)) {
+		edma_err("Invalid Rx mitigation timer configured:%d for ring:%d."
+				" Using the default timer value:%d\n",
+				nss_dp_rx_mitigation_timer, rxdesc_ring->ring_id,
+				NSS_DP_RX_MITIGATION_TIMER_DEF);
+		nss_dp_rx_mitigation_timer = NSS_DP_RX_MITIGATION_TIMER_DEF;
+	}
+
+	/*
+	 * Validate mitigation packet count value
+	 */
+	if ((nss_dp_rx_mitigation_pkt_cnt < EDMA_RX_MITIGATION_PKT_CNT_MIN) ||
+			(nss_dp_rx_mitigation_pkt_cnt > EDMA_RX_MITIGATION_PKT_CNT_MAX)) {
+		edma_err("Invalid Rx mitigation packet count configured:%d for ring:%d."
+				" Using the default packet counter value:%d\n",
+				nss_dp_rx_mitigation_timer, rxdesc_ring->ring_id,
+				NSS_DP_RX_MITIGATION_PKT_CNT_DEF);
+		nss_dp_rx_mitigation_pkt_cnt = NSS_DP_RX_MITIGATION_PKT_CNT_DEF;
+	}
+
+	/*
+	 * Configure the Mitigation timer
+	 */
+	data = MICROSEC_TO_TIMER_UNIT(nss_dp_rx_mitigation_timer);
+	data = ((data & EDMA_RX_MOD_TIMER_INIT_MASK)
+			<< EDMA_RX_MOD_TIMER_INIT_SHIFT);
+	edma_info("EDMA Rx mitigation timer value: %d\n", data);
+	edma_reg_write(EDMA_REG_RX_MOD_TIMER(rxdesc_ring->ring_id), data);
+
+	/*
+	 * Configure the Mitigation packet count
+	 */
+	data = (nss_dp_rx_mitigation_pkt_cnt & EDMA_RXDESC_LOW_THRE_MASK)
+			<< EDMA_RXDESC_LOW_THRE_SHIFT;
+	edma_info("EDMA Rx mitigation packet count value: %d\n", data);
+	edma_reg_write(EDMA_REG_RXDESC_UGT_THRE(rxdesc_ring->ring_id), data);
+
+	/*
+	 * Enable ring. Set ret mode to 'opaque'.
+	 */
+	edma_reg_write(EDMA_REG_RX_INT_CTRL(rxdesc_ring->ring_id), EDMA_RX_NE_INT_EN);
+}
+
+/*
+ * edma_cfg_rx_fill_ring_configure()
+ *	Configure one RxFill ring in EDMA HW
+ */
+static void edma_cfg_rx_fill_ring_configure(struct edma_rxfill_ring *rxfill_ring)
+{
+	uint32_t ring_sz;
+
+	edma_reg_write(EDMA_REG_RXFILL_BA(rxfill_ring->ring_id),
+			(uint32_t)(rxfill_ring->dma & EDMA_RING_DMA_MASK));
+
+	ring_sz = rxfill_ring->count & EDMA_RXFILL_RING_SIZE_MASK;
+	edma_reg_write(EDMA_REG_RXFILL_RING_SIZE(rxfill_ring->ring_id), ring_sz);
+
+	/*
+	 * Alloc Rx buffers
+	 */
+	edma_rx_alloc_buffer(rxfill_ring, rxfill_ring->count - 1);
+}
+
+/*
+ * edma_cfg_rx_qid_to_rx_desc_ring_mapping()
+ *	Configure PPE queue id to Rx ring mapping
+ */
+static void edma_cfg_rx_qid_to_rx_desc_ring_mapping(struct edma_gbl_ctx *egc)
+{
+	uint32_t desc_index, i;
+	uint32_t reg_index, data;
+
+	/*
+	 * Set PPE QID to EDMA Rx ring mapping.
+	 * Each entry can hold mapping for 4 PPE queues and
+	 * entry size is 4 bytes.
+	 */
+	desc_index = (egc->rxdesc_ring_start & EDMA_RX_RING_ID_MASK);
+
+	for (i = EDMA_PORT_QUEUE_START;
+		i <= EDMA_PORT_QUEUE_END;
+			i += EDMA_QID2RID_NUM_PER_REG) {
+		reg_index = i/EDMA_QID2RID_NUM_PER_REG;
+		data = EDMA_RX_RING_ID_QUEUE0_SET(desc_index) |
+			EDMA_RX_RING_ID_QUEUE1_SET(desc_index + 1) |
+			EDMA_RX_RING_ID_QUEUE2_SET(desc_index + 2) |
+			EDMA_RX_RING_ID_QUEUE3_SET(desc_index + 3);
+
+		edma_reg_write(EDMA_QID2RID_TABLE_MEM(reg_index), data);
+		desc_index += EDMA_QID2RID_NUM_PER_REG;
+
+		edma_debug("Configure QID2RID(%d) reg:0x%x to 0x%x\n",
+				i, EDMA_QID2RID_TABLE_MEM(reg_index), data);
+	}
+
+	/*
+	 * Map PPE multicast queues to the first Rx ring.
+	 */
+	desc_index = (egc->rxdesc_ring_start & EDMA_RX_RING_ID_MASK);
+	for (i = EDMA_CPU_PORT_MC_QID_MIN;
+		i <= EDMA_CPU_PORT_MC_QID_MAX;
+			i += EDMA_QID2RID_NUM_PER_REG) {
+		reg_index = i/EDMA_QID2RID_NUM_PER_REG;
+		data = EDMA_RX_RING_ID_QUEUE0_SET(desc_index) |
+			EDMA_RX_RING_ID_QUEUE1_SET(desc_index) |
+			EDMA_RX_RING_ID_QUEUE2_SET(desc_index) |
+			EDMA_RX_RING_ID_QUEUE3_SET(desc_index);
+
+		edma_reg_write(EDMA_QID2RID_TABLE_MEM(reg_index), data);
+
+		edma_debug("Configure QID2RID(%d) reg:0x%x to 0x%x\n",
+				i, EDMA_QID2RID_TABLE_MEM(reg_index), data);
+	}
+}
+
+/*
+ * edma_cfg_rx_rings_to_rx_fill_mapping()
+ *	Configure Rx rings to Rx fill mapping
+ */
+static void edma_cfg_rx_rings_to_rx_fill_mapping(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	/*
+	 * Set RXDESC2FILL_MAP_xx reg.
+	 * 3 registers hold the Rxfill mapping for total 24 Rxdesc rings.
+	 * 3 bits holds the rx fill ring mapping for each of the
+	 * rx descriptor ring.
+	 */
+	edma_reg_write(EDMA_REG_RXDESC2FILL_MAP_0, 0);
+	edma_reg_write(EDMA_REG_RXDESC2FILL_MAP_1, 0);
+	edma_reg_write(EDMA_REG_RXDESC2FILL_MAP_2, 0);
+
+	for (i = 0; i < egc->num_rxdesc_rings; i++) {
+		uint32_t data, reg, ring_id;
+		struct edma_rxdesc_ring *rxdesc_ring = &egc->rxdesc_rings[i];
+
+		ring_id = rxdesc_ring->ring_id;
+		if ((ring_id >= 0) && (ring_id <= 9)) {
+			reg = EDMA_REG_RXDESC2FILL_MAP_0;
+		} else if ((ring_id >= 10) && (ring_id <= 19)) {
+			reg = EDMA_REG_RXDESC2FILL_MAP_1;
+		} else {
+			reg = EDMA_REG_RXDESC2FILL_MAP_2;
+		}
+
+		edma_debug("Configure RXDESC:%u to use RXFILL:%u\n",
+						ring_id,
+						rxdesc_ring->rxfill->ring_id);
+
+		/*
+		 * Set the Rx fill ring number in the
+		 * mapping register.
+		 */
+		data = edma_reg_read(reg);
+		data |= (rxdesc_ring->rxfill->ring_id &
+				EDMA_RXDESC2FILL_MAP_RXDESC_MASK) <<
+				((ring_id % 10) * 3);
+		edma_reg_write(reg, data);
+	}
+
+	edma_debug("EDMA_REG_RXDESC2FILL_MAP_0: 0x%x\n", edma_reg_read(EDMA_REG_RXDESC2FILL_MAP_0));
+	edma_debug("EDMA_REG_RXDESC2FILL_MAP_1: 0x%x\n", edma_reg_read(EDMA_REG_RXDESC2FILL_MAP_1));
+	edma_debug("EDMA_REG_RXDESC2FILL_MAP_2: 0x%x\n", edma_reg_read(EDMA_REG_RXDESC2FILL_MAP_2));
+}
+
+/*
+ * edma_cfg_rx_rings_enable()
+ *	API to enable Rx and Rxfill rings
+ */
+void edma_cfg_rx_rings_enable(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	/*
+	 * Enable Rx rings
+	 */
+	for (i = egc->rxdesc_ring_start; i < egc->rxdesc_ring_end; i++) {
+		uint32_t data;
+
+		data = edma_reg_read(EDMA_REG_RXDESC_CTRL(i));
+		data |= EDMA_RXDESC_RX_EN;
+		edma_reg_write(EDMA_REG_RXDESC_CTRL(i), data);
+	}
+
+	for (i = egc->rxfill_ring_start; i < egc->rxfill_ring_end; i++) {
+		uint32_t data;
+
+		data = edma_reg_read(EDMA_REG_RXFILL_RING_EN(i));
+		data |= EDMA_RXFILL_RING_EN;
+		edma_reg_write(EDMA_REG_RXFILL_RING_EN(i), data);
+	}
+}
+
+/*
+ * edma_cfg_rx_rings_disable()
+ *	API to disable Rx and Rxfill rings
+ */
+void edma_cfg_rx_rings_disable(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	/*
+	 * Disable Rx rings
+	 */
+	for (i = 0; i < egc->num_rxdesc_rings; i++) {
+		uint32_t data;
+		struct edma_rxdesc_ring *rxdesc_ring = NULL;
+
+		rxdesc_ring = &egc->rxdesc_rings[i];
+		data = edma_reg_read(EDMA_REG_RXDESC_CTRL(rxdesc_ring->ring_id));
+		data &= ~EDMA_RXDESC_RX_EN;
+		edma_reg_write(EDMA_REG_RXDESC_CTRL(rxdesc_ring->ring_id), data);
+	}
+
+	/*
+	 * Disable RxFill Rings
+	 */
+	for (i = 0; i < egc->num_rxfill_rings; i++) {
+		uint32_t data;
+		struct edma_rxfill_ring *rxfill_ring = NULL;
+
+		rxfill_ring = &egc->rxfill_rings[i];
+		data = edma_reg_read(EDMA_REG_RXFILL_RING_EN(rxfill_ring->ring_id));
+		data &= ~EDMA_RXFILL_RING_EN;
+		edma_reg_write(EDMA_REG_RXFILL_RING_EN(rxfill_ring->ring_id), data);
+	}
+}
+
+/*
+ * edma_cfg_rx_mapping()
+ *	API to setup RX ring mapping
+ */
+void edma_cfg_rx_mapping(struct edma_gbl_ctx *egc)
+{
+	edma_cfg_rx_qid_to_rx_desc_ring_mapping(egc);
+	edma_cfg_rx_rings_to_rx_fill_mapping(egc);
+}
+
+/*
+ * edma_cfg_rx_rings_setup()
+ *	Allocate/setup resources for EDMA rings
+ */
+static int edma_cfg_rx_rings_setup(struct edma_gbl_ctx *egc)
+{
+	uint32_t queue_id = EDMA_PORT_QUEUE_START;
+	int32_t i, alloc_size, buf_len;
+
+	/*
+	 * Set buffer allocation size
+	 */
+	if (egc->rx_jumbo_mru) {
+		alloc_size = egc->rx_jumbo_mru + EDMA_RX_SKB_HEADROOM + NET_IP_ALIGN;
+		buf_len = alloc_size - EDMA_RX_SKB_HEADROOM - NET_IP_ALIGN;
+	} else if (egc->rx_page_mode) {
+		alloc_size = EDMA_RX_PAGE_MODE_SKB_SIZE + EDMA_RX_SKB_HEADROOM + NET_IP_ALIGN;
+		buf_len = PAGE_SIZE;
+	} else {
+		alloc_size = dp_global_ctx.rx_buf_size;
+		buf_len = alloc_size - EDMA_RX_SKB_HEADROOM - NET_IP_ALIGN;
+	}
+
+	edma_debug("EDMA ctx:%px rx_ring alloc_size=%d, buf_len=%d\n", egc, alloc_size, buf_len);
+
+	/*
+	 * Allocate Rx fill ring descriptors
+	 */
+	for (i = 0; i < egc->num_rxfill_rings; i++) {
+		int32_t ret;
+		struct edma_rxfill_ring *rxfill_ring = NULL;
+
+		rxfill_ring = &egc->rxfill_rings[i];
+		rxfill_ring->count = EDMA_RX_RING_SIZE;
+		rxfill_ring->ring_id = egc->rxfill_ring_start + i;
+		rxfill_ring->alloc_size = alloc_size;
+		rxfill_ring->buf_len = buf_len;
+		rxfill_ring->page_mode = egc->rx_page_mode;
+
+		ret = edma_cfg_rx_fill_ring_setup(rxfill_ring);
+		if (ret != 0) {
+			edma_err("Error in setting up %d rxfill ring. ret: %d",
+					 rxfill_ring->ring_id, ret);
+			while (--i >= 0) {
+				edma_cfg_rx_fill_ring_cleanup(egc,
+					&egc->rxfill_rings[i]);
+			}
+
+			return -ENOMEM;
+		}
+	}
+
+	/*
+	 * Allocate RxDesc ring descriptors
+	 */
+	for (i = 0; i < egc->num_rxdesc_rings; i++) {
+		uint32_t index, word_idx, bit_idx;
+		int32_t ret;
+		struct edma_rxdesc_ring *rxdesc_ring = NULL;
+
+		rxdesc_ring = &egc->rxdesc_rings[i];
+		rxdesc_ring->count = EDMA_RX_RING_SIZE;
+		rxdesc_ring->ring_id = egc->rxdesc_ring_start + i;
+
+		if (queue_id > EDMA_PORT_QUEUE_END) {
+			edma_err("Invalid queue_id: %d\n", queue_id);
+			while (--i >= 0) {
+				edma_cfg_rx_desc_ring_cleanup(egc, &egc->rxdesc_rings[i]);
+			}
+
+			goto rxdesc_mem_alloc_fail;
+		}
+
+		/*
+		 * MAP Rx descriptor ring to PPE queues.
+		 *
+		 * TODO:
+		 * Currently one Rx descriptor ring can get mapped to only
+		 * single PPE queue. Multiple queues getting mapped to the
+		 * single Rx descriptor ring is not yet supported.
+		 * In future, we can support this by getting the Rx descriptor
+		 * ring to queue mapping from the dtsi.
+		 */
+		word_idx = (queue_id / (EDMA_BITS_IN_WORD - 1));
+		bit_idx = (queue_id % EDMA_BITS_IN_WORD);
+		egc->rxdesc_ring_to_queue_bm[i][word_idx] = 1 << bit_idx;
+		queue_id++;
+
+		/*
+		 * Create a mapping between RX Desc ring and Rx fill ring.
+		 * Number of fill rings are lesser than the descriptor rings
+		 * Share the fill rings across descriptor rings.
+		 */
+		index = egc->rxfill_ring_start + (i % egc->num_rxfill_rings);
+		rxdesc_ring->rxfill = &egc->rxfill_rings[index - egc->rxfill_ring_start];
+
+		ret = edma_cfg_rx_desc_ring_setup(rxdesc_ring);
+		if (ret != 0) {
+			edma_err("Error in setting up %d rxdesc ring. ret: %d",
+					 rxdesc_ring->ring_id, ret);
+			while (--i >= 0) {
+				edma_cfg_rx_desc_ring_cleanup(egc, &egc->rxdesc_rings[i]);
+			}
+
+			goto rxdesc_mem_alloc_fail;
+		}
+	}
+
+	return 0;
+
+rxdesc_mem_alloc_fail:
+	for (i = 0; i < egc->num_rxfill_rings; i++) {
+		edma_cfg_rx_fill_ring_cleanup(egc, &egc->rxfill_rings[i]);
+	}
+
+	return -ENOMEM;
+}
+
+/*
+ * edma_cfg_rx_page_mode_and_jumbo()
+ *	Configure EDMA Rx rings page mode and jumbo MRU
+ */
+void edma_cfg_rx_page_mode_and_jumbo(struct edma_gbl_ctx *egc)
+{
+	/*
+	 * Over-ride EDMA global page mode if specified in module param
+	 */
+	if (dp_global_ctx.overwrite_mode) {
+		edma_debug("Page mode is overwritten: %d\n", dp_global_ctx.page_mode);
+		egc->rx_page_mode = dp_global_ctx.page_mode;
+	}
+
+	if (dp_global_ctx.jumbo_mru) {
+		egc->rx_page_mode = false;
+		egc->rx_jumbo_mru = dp_global_ctx.jumbo_mru;
+		edma_debug("Jumbo mru is enabled: %d\n", egc->rx_jumbo_mru);
+	}
+}
+
+/*
+ * edma_cfg_rx_rings_alloc()
+ *	Allocate EDMA Rx rings
+ */
+int32_t edma_cfg_rx_rings_alloc(struct edma_gbl_ctx *egc)
+{
+	egc->rxfill_rings = kzalloc((sizeof(struct edma_rxfill_ring) *
+				egc->num_rxfill_rings), GFP_KERNEL);
+	if (!egc->rxfill_rings) {
+		edma_err("Error in allocating rxfill ring\n");
+		return -ENOMEM;
+	}
+
+	egc->rxdesc_rings = kzalloc((sizeof(struct edma_rxdesc_ring) *
+				egc->num_rxdesc_rings), GFP_KERNEL);
+	if (!egc->rxdesc_rings) {
+		edma_err("Error in allocating rxdesc ring\n");
+		goto rxdesc_ring_alloc_fail;
+	}
+
+	edma_info("RxDesc:%u (%u-%u) RxFill:%u (%u-%u)\n",
+		egc->num_rxdesc_rings, egc->rxdesc_ring_start,
+		(egc->rxdesc_ring_start + egc->num_rxdesc_rings - 1),
+		egc->num_rxfill_rings, egc->rxfill_ring_start,
+		(egc->rxfill_ring_start + egc->num_rxfill_rings - 1));
+
+	egc->rxdesc_ring_to_queue_bm = kzalloc(egc->num_rxdesc_rings * sizeof(uint32_t) * \
+			 EDMA_RING_MAPPED_QUEUE_BM_WORD_COUNT, GFP_KERNEL);
+	if (!egc->rxdesc_ring_to_queue_bm) {
+		edma_err("Error in allocating mapped queue area for Rxdesc rings\n");
+		goto rx_rings_mapped_queue_alloc_failed;
+	}
+
+	if (edma_cfg_rx_rings_setup(egc)) {
+		edma_err("Error in setting up rx rings\n");
+		goto rx_rings_setup_fail;
+	}
+
+	/*
+	 * Reset Rx descriptor ring mapped queue's configurations
+	 */
+	if (edma_cfg_rx_desc_ring_reset_queue_config(egc)) {
+		edma_err("Error in resetting the Rx descriptor rings configurations\n");
+		edma_cfg_rx_rings_cleanup(egc);
+		return -EINVAL;
+	}
+
+	return 0;
+
+rx_rings_setup_fail:
+	kfree(egc->rxdesc_ring_to_queue_bm);
+	egc->rxdesc_ring_to_queue_bm = NULL;
+rx_rings_mapped_queue_alloc_failed:
+	kfree(egc->rxdesc_rings);
+	egc->rxdesc_rings = NULL;
+rxdesc_ring_alloc_fail:
+	kfree(egc->rxfill_rings);
+	egc->rxfill_rings = NULL;
+	return -ENOMEM;
+}
+
+/*
+ * edma_cfg_rx_rings_cleanup()
+ *	Cleanup EDMA rings
+ */
+void edma_cfg_rx_rings_cleanup(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	/*
+	 * Free Rx fill ring descriptors
+	 */
+	for (i = 0; i < egc->num_rxfill_rings; i++) {
+		edma_cfg_rx_fill_ring_cleanup(egc, &egc->rxfill_rings[i]);
+	}
+
+	/*
+	 * Free Rx completion ring descriptors
+	 */
+	for (i = 0; i < egc->num_rxdesc_rings; i++) {
+		edma_cfg_rx_desc_ring_cleanup(egc, &egc->rxdesc_rings[i]);
+	}
+
+	kfree(egc->rxfill_rings);
+	kfree(egc->rxdesc_rings);
+	egc->rxfill_rings = NULL;
+	egc->rxdesc_rings = NULL;
+
+	if (egc->rxdesc_ring_to_queue_bm) {
+		kfree(egc->rxdesc_ring_to_queue_bm);
+		egc->rxdesc_ring_to_queue_bm = NULL;
+	}
+}
+
+/*
+ * edma_cfg_rx_rings()
+ *	Configure EDMA rings
+ */
+void edma_cfg_rx_rings(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	/*
+	 * Configure RXFILL rings
+	 */
+	for (i = 0; i < egc->num_rxfill_rings; i++) {
+		edma_cfg_rx_fill_ring_configure(&egc->rxfill_rings[i]);
+	}
+
+	/*
+	 * Configure RXDESC ring
+	 */
+	for (i = 0; i < egc->num_rxdesc_rings; i++) {
+		edma_cfg_rx_desc_ring_configure(&egc->rxdesc_rings[i]);
+	}
+}
+
+/*
+ * edma_cfg_rx_napi_disable()
+ *	Disable RX NAPI
+ */
+void edma_cfg_rx_napi_disable(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	for (i = 0; i < egc->num_rxdesc_rings; i++) {
+		struct edma_rxdesc_ring *rxdesc_ring;
+
+		rxdesc_ring = &egc->rxdesc_rings[i];
+
+		if (!rxdesc_ring->napi_added) {
+			continue;
+		}
+
+		napi_disable(&rxdesc_ring->napi);
+	}
+}
+
+/*
+ * edma_cfg_rx_napi_enable()
+ *	Enable RX NAPI
+ */
+void edma_cfg_rx_napi_enable(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	for (i = 0; i < egc->num_rxdesc_rings; i++) {
+		struct edma_rxdesc_ring *rxdesc_ring;
+
+		rxdesc_ring = &egc->rxdesc_rings[i];
+
+		if (!rxdesc_ring->napi_added) {
+			continue;
+		}
+
+		napi_enable(&rxdesc_ring->napi);
+	}
+}
+
+/*
+ * edma_cfg_rx_napi_delete()
+ *	Delete RX NAPI
+ */
+void edma_cfg_rx_napi_delete(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	for (i = 0; i < egc->num_rxdesc_rings; i++) {
+		struct edma_rxdesc_ring *rxdesc_ring;
+
+		rxdesc_ring = &egc->rxdesc_rings[i];
+
+		if (!rxdesc_ring->napi_added) {
+			continue;
+		}
+
+		netif_napi_del(&rxdesc_ring->napi);
+		rxdesc_ring->napi_added = false;
+	}
+}
+
+/*
+ * edma_cfg_rx_napi_add()
+ *	RX NAPI add API
+ */
+void edma_cfg_rx_napi_add(struct edma_gbl_ctx *egc, struct net_device *netdev)
+{
+	uint32_t i;
+
+	if ((nss_dp_rx_napi_budget < EDMA_RX_NAPI_WORK_MIN) ||
+		(nss_dp_rx_napi_budget > EDMA_RX_NAPI_WORK_MAX)) {
+		edma_err("Incorrect Rx NAPI budget: %d, setting to default: %d",
+			nss_dp_rx_napi_budget, NSS_DP_HAL_RX_NAPI_BUDGET);
+		nss_dp_rx_napi_budget = NSS_DP_HAL_RX_NAPI_BUDGET;
+	}
+
+	for (i = 0; i < egc->num_rxdesc_rings; i++) {
+		struct edma_rxdesc_ring *rxdesc_ring = &egc->rxdesc_rings[i];
+		netif_napi_add(netdev, &rxdesc_ring->napi,
+				edma_rx_napi_poll, nss_dp_rx_napi_budget);
+		rxdesc_ring->napi_added = true;
+	}
+}
+
+/*
+ * edma_cfg_rx_fc_enable_handler()
+ *	API to enable/disable Rx rings flow control configurations
+ *
+ * The Rx flow control has the X-OFF and the X-ON threshold values.
+ * Whenever the free Rx ring descriptor count falls below the X-OFF value, the
+ * ring level flow control will kick in and the mapped PPE queues will be backpressured.
+ * Similarly, whenever the free Rx ring descriptor count crosses the X-ON value,
+ * the ring level flow control will be disabled.
+ */
+int edma_cfg_rx_fc_enable_handler(struct ctl_table *table, int write,
+		void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret;
+
+	ret = proc_dointvec(table, write, buffer, lenp, ppos);
+
+	if (!write) {
+		return ret;
+	}
+
+	if (edma_cfg_rx_fc_enable) {
+		/*
+		 * Validate flow control X-OFF and X-ON configurations
+		 */
+		if ((nss_dp_rx_fc_xoff < EDMA_RX_FC_XOFF_THRE_MIN) ||
+				(nss_dp_rx_fc_xoff > EDMA_RX_RING_SIZE)) {
+			edma_err("Incorrect Rx Xoff flow control value: %d. Setting\n"
+					" it to default value: %d", nss_dp_rx_fc_xoff,
+					NSS_DP_RX_FC_XOFF_DEF);
+			nss_dp_rx_fc_xoff = NSS_DP_RX_FC_XOFF_DEF;
+		}
+		if ((nss_dp_rx_fc_xon < EDMA_RX_FC_XON_THRE_MIN) ||
+				(nss_dp_rx_fc_xon > EDMA_RX_RING_SIZE) ||
+				(nss_dp_rx_fc_xon < nss_dp_rx_fc_xoff)) {
+			edma_err("Incorrect Rx Xon flow control value: %d. Setting\n"
+					" it to default value: %d", nss_dp_rx_fc_xon,
+					NSS_DP_RX_FC_XON_DEF);
+			nss_dp_rx_fc_xon = NSS_DP_RX_FC_XON_DEF;
+		}
+
+		/*
+		 * Configure Rx flow control configurations
+		 */
+		edma_cfg_rx_desc_ring_flow_control(nss_dp_rx_fc_xoff, nss_dp_rx_fc_xon);
+		edma_cfg_rx_fill_ring_flow_control(nss_dp_rx_fc_xoff, nss_dp_rx_fc_xon);
+		edma_cfg_rx_desc_ring_to_queue_mapping(edma_cfg_rx_fc_enable);
+
+		/*
+		 * Validate queue's AC FC threshold configuration value
+		 */
+		if ((nss_dp_rx_ac_fc_threshold < EDMA_RX_AC_FC_THRE_MIN) ||
+				(nss_dp_rx_ac_fc_threshold > EDMA_RX_AC_FC_THRE_MAX)) {
+			edma_err("Incorrect AC FC threshold value: %d. Setting"
+					" it to default value: %d", nss_dp_rx_ac_fc_threshold,
+					NSS_DP_RX_AC_FC_THRES_DEF);
+			nss_dp_rx_ac_fc_threshold = NSS_DP_RX_AC_FC_THRES_DEF;
+		}
+
+		/*
+		 * Configure queue tail drop by enabling and configuring the
+		 * AC FC threshold for mapped PPE queues of the Rx descriptor rings
+		 */
+		edma_cfg_rx_mapped_queue_ac_fc_configure(nss_dp_rx_ac_fc_threshold,
+					edma_cfg_rx_fc_enable);
+	} else {
+		/*
+		 * De-configure Rx flow control configurations:
+		 *
+		 * 1. Reset  the Rx descriptor and Rx fill rings flow control
+		 * configurations with original X-OFF and X-ON threshold values.
+		 * 2. Reset the backpressure configuration by un-mapping the Rx
+		 * descriptor rings with any mapped PPE queues
+		 */
+		edma_cfg_rx_desc_ring_flow_control(0, 0);
+		edma_cfg_rx_fill_ring_flow_control(0, 0);
+		edma_cfg_rx_desc_ring_to_queue_mapping(edma_cfg_rx_fc_enable);
+
+		/*
+		 * De-configure mapped queues queue tail drop configurations:
+		 *
+		 * Reset the threshold configuration and disable the Rx descriptor's
+		 * mapped queues AC FC configurataion.
+		 */
+		edma_cfg_rx_mapped_queue_ac_fc_configure(EDMA_RX_AC_FC_THRE_ORIG,
+					edma_cfg_rx_fc_enable);
+	}
+
+	return ret;
+}
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_cfg_rx.h b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_cfg_rx.h
new file mode 100644
index 0000000..d4f6b2f
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_cfg_rx.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __EDMA_CFG_RX_H__
+#define __EDMA_CFG_RX_H__
+
+#define EDMA_RX_NAPI_WORK_MIN		16
+#define EDMA_RX_NAPI_WORK_MAX		512
+#define EDMA_RX_PAGE_MODE_SKB_SIZE	256	/* SKB payload size used in page mode */
+#define EDMA_RX_DEFAULT_QUEUE_PRI	0
+#define EDMA_RX_FC_ENABLE		0	/* RX flow control default state */
+#define EDMA_RX_FC_XOFF_THRE_MIN	0	/* Rx flow control minimum X-OFF value */
+#define EDMA_RX_FC_XON_THRE_MIN		0	/* Rx flow control mininum X-ON value */
+#define EDMA_RX_AC_FC_THRE_ORIG		0x190	/* Rx AC flow control original threshold */
+#define EDMA_RX_AC_FC_THRE_MIN		0	/* Rx AC flow control minimum threshold */
+#define EDMA_RX_AC_FC_THRE_MAX		0x7ff	/* Rx AC flow control maximum threshold.
+						   AC FC threshold value is 11 bits long */
+
+#define EDMA_RX_MITIGATION_TIMER_MIN	0	/* Rx mitigation timer's minimum value in microseconds */
+#define EDMA_RX_MITIGATION_TIMER_MAX	1000	/* Rx mitigation timer's maximum value in microseconds */
+#define EDMA_RX_MITIGATION_PKT_CNT_MIN	0	/* Rx mitigation packet count's minimum value */
+#define EDMA_RX_MITIGATION_PKT_CNT_MAX	256	/* Rx mitigation packet count's maximum value */
+
+extern uint32_t edma_cfg_rx_fc_enable;
+
+void edma_cfg_rx_rings(struct edma_gbl_ctx *egc);
+int32_t edma_cfg_rx_rings_alloc(struct edma_gbl_ctx *egc);
+void edma_cfg_rx_rings_cleanup(struct edma_gbl_ctx *egc);
+void edma_cfg_rx_napi_disable(struct edma_gbl_ctx *egc);
+void edma_cfg_rx_napi_enable(struct edma_gbl_ctx *egc);
+void edma_cfg_rx_napi_delete(struct edma_gbl_ctx *egc);
+void edma_cfg_rx_napi_add(struct edma_gbl_ctx *egc, struct net_device *netdev);
+void edma_cfg_rx_mapping(struct edma_gbl_ctx *egc);
+void edma_cfg_rx_rings_enable(struct edma_gbl_ctx *egc);
+void edma_cfg_rx_rings_disable(struct edma_gbl_ctx *egc);
+int edma_cfg_rx_fc_enable_handler(struct ctl_table *table, int write,
+		void __user *buffer, size_t *lenp, loff_t *ppos);
+void edma_cfg_rx_page_mode_and_jumbo(struct edma_gbl_ctx *egc);
+#endif	/* __EDMA_CFG_RX_H__ */
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_cfg_tx.c b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_cfg_tx.c
new file mode 100644
index 0000000..ba86666
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_cfg_tx.c
@@ -0,0 +1,678 @@
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/debugfs.h>
+#include <linux/interrupt.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/reset.h>
+#include <nss_dp_dev.h>
+#include "edma.h"
+#include "edma_cfg_tx.h"
+#include "edma_regs.h"
+#include "edma_debug.h"
+
+/*
+ * edma_cfg_tx_cmpl_ring_cleanup()
+ *	Cleanup resources for one TxCmpl ring
+ */
+static void edma_cfg_tx_cmpl_ring_cleanup(struct edma_gbl_ctx *egc,
+				struct edma_txcmpl_ring *txcmpl_ring)
+{
+	/*
+	 * Free any buffers assigned to any descriptors
+	 */
+	edma_tx_complete(EDMA_TX_RING_SIZE - 1, txcmpl_ring);
+
+	/*
+	 * Free TxCmpl ring descriptors
+	 */
+	kfree(txcmpl_ring->desc);
+	txcmpl_ring->desc = NULL;
+	txcmpl_ring->dma = (dma_addr_t)0;
+}
+
+/*
+ * edma_cfg_tx_cmpl_ring_setup()
+ *	Setup resources for one TxCmpl ring
+ */
+static int edma_cfg_tx_cmpl_ring_setup(struct edma_txcmpl_ring *txcmpl_ring)
+{
+	txcmpl_ring->desc = kmalloc((sizeof(struct edma_txcmpl_desc) *  txcmpl_ring->count) +
+				SMP_CACHE_BYTES,  GFP_KERNEL | __GFP_ZERO);
+	if (!txcmpl_ring->desc) {
+		edma_err("Descriptor alloc for TXCMPL ring %u failed\n",
+				txcmpl_ring->id);
+		return -ENOMEM;
+	}
+
+	txcmpl_ring->dma = (dma_addr_t)virt_to_phys(txcmpl_ring->desc);
+
+	return 0;
+}
+
+/*
+ * edma_cfg_tx_desc_ring_cleanup()
+ *	Cleanup resources for one TxDesc ring
+ *
+ * This API expects ring to be disabled by caller
+ */
+static void edma_cfg_tx_desc_ring_cleanup(struct edma_gbl_ctx *egc,
+				struct edma_txdesc_ring *txdesc_ring)
+{
+	struct sk_buff *skb = NULL;
+	struct edma_pri_txdesc *txdesc = NULL;
+	uint32_t prod_idx, cons_idx, data;
+
+	/*
+	 * Free any buffers assigned to any descriptors
+	 */
+	data = edma_reg_read(EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id));
+	prod_idx = data & EDMA_TXDESC_PROD_IDX_MASK;
+
+	data = edma_reg_read(EDMA_REG_TXDESC_CONS_IDX(txdesc_ring->id));
+	cons_idx = data & EDMA_TXDESC_CONS_IDX_MASK;
+
+	/*
+	 * Walk active list, obtain skb from descriptor and free it
+	 */
+	while (cons_idx != prod_idx) {
+		txdesc = EDMA_TXDESC_PRI_DESC(txdesc_ring, cons_idx);
+		skb = (struct sk_buff *)EDMA_TXDESC_OPAQUE_GET(txdesc);
+		dev_kfree_skb_any(skb);
+
+		cons_idx = ((cons_idx + 1) & EDMA_TX_RING_SIZE_MASK);
+	}
+
+	/*
+	 * Free Tx ring descriptors
+	 */
+	kfree(txdesc_ring->pdesc);
+	txdesc_ring->pdesc = NULL;
+	txdesc_ring->pdma = (dma_addr_t)0;
+
+	/*
+	 * TODO:
+	 * Free any buffers assigned to any secondary descriptors
+	 */
+	kfree(txdesc_ring->sdesc);
+	txdesc_ring->sdesc = NULL;
+	txdesc_ring->sdma = (dma_addr_t)0;
+}
+
+/*
+ * edma_cfg_tx_desc_ring_setup()
+ *	Setup resources for one TxDesc ring
+ */
+static int edma_cfg_tx_desc_ring_setup(struct edma_txdesc_ring *txdesc_ring)
+{
+	/*
+	 * Allocate Tx ring descriptors
+	 */
+	txdesc_ring->pdesc = kmalloc((sizeof(struct edma_pri_txdesc) *  txdesc_ring->count) +
+				SMP_CACHE_BYTES,  GFP_KERNEL | __GFP_ZERO);
+	if (!txdesc_ring->pdesc) {
+		edma_err("Descriptor alloc for TXDESC ring %u failed\n",
+				txdesc_ring->id);
+		return -ENOMEM;
+	}
+
+	txdesc_ring->pdma = (dma_addr_t)virt_to_phys(txdesc_ring->pdesc);
+
+	/*
+	 * Allocate sencondary Tx ring descriptors
+	 */
+	txdesc_ring->sdesc = kmalloc((sizeof(struct edma_sec_txdesc) *  txdesc_ring->count) +
+				SMP_CACHE_BYTES,  GFP_KERNEL | __GFP_ZERO);
+	if (!txdesc_ring->sdesc) {
+		edma_err("Descriptor alloc for secondary TXDESC ring %u failed\n",
+				txdesc_ring->id);
+		kfree(txdesc_ring->pdesc);
+		txdesc_ring->pdesc = NULL;
+		txdesc_ring->pdma = (dma_addr_t)0;
+		return -ENOMEM;
+	}
+
+	txdesc_ring->sdma = (dma_addr_t)virt_to_phys(txdesc_ring->sdesc);
+
+	return 0;
+}
+
+/*
+ * edma_cfg_tx_desc_ring_configure()
+ *	Configure one TxDesc ring in EDMA HW
+ */
+static void edma_cfg_tx_desc_ring_configure(struct edma_txdesc_ring *txdesc_ring)
+{
+	/*
+	 * Configure TXDESC ring
+	 */
+	edma_reg_write(EDMA_REG_TXDESC_BA(txdesc_ring->id),
+			(uint32_t)(txdesc_ring->pdma &
+			EDMA_RING_DMA_MASK));
+
+	edma_reg_write(EDMA_REG_TXDESC_BA2(txdesc_ring->id),
+			(uint32_t)(txdesc_ring->sdma &
+			EDMA_RING_DMA_MASK));
+
+	edma_reg_write(EDMA_REG_TXDESC_RING_SIZE(txdesc_ring->id),
+			(uint32_t)(txdesc_ring->count &
+			EDMA_TXDESC_RING_SIZE_MASK));
+
+	edma_reg_write(EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id),
+			(uint32_t)EDMA_TX_INITIAL_PROD_IDX);
+
+	/*
+	 * Configure group ID for flow control for this Tx ring
+	 */
+	edma_reg_write(EDMA_REG_TXDESC_CTRL(txdesc_ring->id),
+			EDMA_TXDESC_CTRL_FC_GRP_ID_SET(txdesc_ring->fc_grp_id));
+}
+
+/*
+ * edma_cfg_tx_cmpl_ring_configure()
+ *	Configure one TxCmpl ring in EDMA HW
+ */
+static void edma_cfg_tx_cmpl_ring_configure(struct edma_txcmpl_ring *txcmpl_ring)
+{
+	uint32_t data;
+
+	/*
+	 * Configure TxCmpl ring base address
+	 */
+	edma_reg_write(EDMA_REG_TXCMPL_BA(txcmpl_ring->id),
+			(uint32_t)(txcmpl_ring->dma & EDMA_RING_DMA_MASK));
+	edma_reg_write(EDMA_REG_TXCMPL_RING_SIZE(txcmpl_ring->id),
+			(uint32_t)(txcmpl_ring->count
+			& EDMA_TXDESC_RING_SIZE_MASK));
+
+	/*
+	 * Set TxCmpl ret mode to opaque
+	 */
+	edma_reg_write(EDMA_REG_TXCMPL_CTRL(txcmpl_ring->id),
+			EDMA_TXCMPL_RETMODE_OPAQUE);
+
+	/*
+	 * Validate mitigation timer value
+	 */
+	if ((nss_dp_tx_mitigation_timer < EDMA_TX_MITIGATION_TIMER_MIN) ||
+			(nss_dp_tx_mitigation_timer > EDMA_TX_MITIGATION_TIMER_MAX)) {
+		edma_err("Invalid Tx mitigation timer configured:%d for ring:%d."
+				" Using the default timer value:%d\n",
+				nss_dp_tx_mitigation_timer, txcmpl_ring->id,
+				NSS_DP_TX_MITIGATION_TIMER_DEF);
+		nss_dp_tx_mitigation_timer = NSS_DP_TX_MITIGATION_TIMER_DEF;
+	}
+
+	/*
+	 * Validate mitigation packet count value
+	 */
+	if ((nss_dp_tx_mitigation_pkt_cnt < EDMA_TX_MITIGATION_PKT_CNT_MIN) ||
+			(nss_dp_tx_mitigation_pkt_cnt > EDMA_TX_MITIGATION_PKT_CNT_MAX)) {
+		edma_err("Invalid Tx mitigation packet count configured:%d for ring:%d."
+				" Using the default packet counter value:%d\n",
+				nss_dp_tx_mitigation_timer, txcmpl_ring->id,
+				NSS_DP_TX_MITIGATION_PKT_CNT_DEF);
+		nss_dp_tx_mitigation_pkt_cnt = NSS_DP_TX_MITIGATION_PKT_CNT_DEF;
+	}
+
+	/*
+	 * Configure the Mitigation timer
+	 */
+	data = MICROSEC_TO_TIMER_UNIT(nss_dp_tx_mitigation_timer);
+	data = ((data & EDMA_TX_MOD_TIMER_INIT_MASK)
+			<< EDMA_TX_MOD_TIMER_INIT_SHIFT);
+	edma_info("EDMA Tx mitigation timer value: %d\n", data);
+	edma_reg_write(EDMA_REG_TX_MOD_TIMER(txcmpl_ring->id), data);
+
+	/*
+	 * Configure the Mitigation packet count
+	 */
+	data = (nss_dp_tx_mitigation_pkt_cnt & EDMA_TXCMPL_LOW_THRE_MASK)
+			<< EDMA_TXCMPL_LOW_THRE_SHIFT;
+	edma_info("EDMA Tx mitigation packet count value: %d\n", data);
+	edma_reg_write(EDMA_REG_TXCMPL_UGT_THRE(txcmpl_ring->id), data);
+
+	edma_reg_write(EDMA_REG_TX_INT_CTRL(txcmpl_ring->id), EDMA_TX_NE_INT_EN);
+}
+
+/*
+ * edma_cfg_tx_cmpl_mapping_fill()
+ *	API to fill tx complete ring mapping per core
+ */
+static void edma_cfg_tx_cmpl_mapping_fill(struct edma_gbl_ctx *egc)
+{
+	uint32_t i, j;
+
+	for (i = 0; i < EDMA_TX_RING_PER_CORE_MAX; i++) {
+		for_each_possible_cpu(j) {
+			int32_t txdesc_id = egc->tx_map[i][j];
+			if (txdesc_id < 0) {
+				continue;
+			}
+
+			egc->txcmpl_map[i][j] =
+					egc->tx_to_txcmpl_map[txdesc_id];
+			edma_debug("txcmpl_map[i][j]: %d\n",
+					egc->txcmpl_map[i][j]);
+		}
+	}
+}
+
+/*
+ * edma_cfg_tx_fill_per_port_tx_map()
+ *	API to fill per-port Tx ring mapping in net device private area.
+ */
+void edma_cfg_tx_fill_per_port_tx_map(struct net_device *netdev, uint32_t macid)
+{
+	uint32_t i;
+
+	for_each_possible_cpu(i) {
+		struct nss_dp_dev *dp_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+		struct edma_txdesc_ring *txdesc_ring;
+		uint32_t txdesc_ring_id;
+		uint32_t txdesc_start = edma_gbl_ctx.txdesc_ring_start;
+
+		txdesc_ring_id = edma_gbl_ctx.tx_map[macid - 1][i];
+		txdesc_ring = &edma_gbl_ctx.txdesc_rings[txdesc_ring_id - txdesc_start];
+		dp_dev->dp_info.txr_map[0][i] = txdesc_ring;
+	}
+}
+
+/*
+ * edma_cfg_tx_rings_enable()
+ *	API to enable TX rings
+ */
+void edma_cfg_tx_rings_enable(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	/*
+	 * Enable Tx rings
+	 */
+	for (i = 0; i < egc->num_txdesc_rings; i++) {
+		uint32_t data;
+		struct edma_txdesc_ring *txdesc_ring = &egc->txdesc_rings[i];
+
+		data = edma_reg_read(EDMA_REG_TXDESC_CTRL(txdesc_ring->id));
+		data |= EDMA_TXDESC_CTRL_TXEN_SET(EDMA_TXDESC_TX_ENABLE);
+		edma_reg_write(EDMA_REG_TXDESC_CTRL(txdesc_ring->id), data);
+	}
+}
+
+/*
+ * edma_cfg_tx_rings_disable()
+ *	API to disable TX rings
+ */
+void edma_cfg_tx_rings_disable(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	/*
+	 * Disable Tx rings
+	 */
+	for (i = 0; i < egc->num_txdesc_rings; i++) {
+		struct edma_txdesc_ring *txdesc_ring = NULL;
+		uint32_t data;
+
+		txdesc_ring = &egc->txdesc_rings[i];
+		data = edma_reg_read(EDMA_REG_TXDESC_CTRL(txdesc_ring->id));
+		data &= ~EDMA_TXDESC_TX_ENABLE;
+		edma_reg_write(EDMA_REG_TXDESC_CTRL(txdesc_ring->id), data);
+	}
+}
+
+/*
+ * edma_cfg_tx_mapping()
+ *	API to map TX to TX complete rings
+ */
+void edma_cfg_tx_mapping(struct edma_gbl_ctx *egc)
+{
+	uint32_t desc_index, i;
+
+	/*
+	 * Clear the TXDESC2CMPL_MAP_xx reg before setting up
+	 * the mapping. This register holds TXDESC to TXFILL ring
+	 * mapping.
+	 */
+	edma_reg_write(EDMA_REG_TXDESC2CMPL_MAP_0, 0);
+	edma_reg_write(EDMA_REG_TXDESC2CMPL_MAP_1, 0);
+	edma_reg_write(EDMA_REG_TXDESC2CMPL_MAP_2, 0);
+	edma_reg_write(EDMA_REG_TXDESC2CMPL_MAP_3, 0);
+	edma_reg_write(EDMA_REG_TXDESC2CMPL_MAP_4, 0);
+	edma_reg_write(EDMA_REG_TXDESC2CMPL_MAP_5, 0);
+	desc_index = egc->txcmpl_ring_start;
+
+	/*
+	 * 6 registers to hold the completion mapping for total 32
+	 * TX desc rings (0-5, 6-11, 12-17, 18-23, 24-29 and rest).
+	 * In each entry 5 bits hold the mapping for a particular TX desc ring.
+	 */
+	for (i = egc->txdesc_ring_start; i < egc->txdesc_ring_end; i++) {
+		uint32_t reg, data;
+
+		if ((i >= 0) && (i <= 5)) {
+			reg = EDMA_REG_TXDESC2CMPL_MAP_0;
+		} else if ((i >= 6) && (i <= 11)) {
+			reg = EDMA_REG_TXDESC2CMPL_MAP_1;
+		} else if ((i >= 12) && (i <= 17)) {
+			reg = EDMA_REG_TXDESC2CMPL_MAP_2;
+		} else if ((i >= 18) && (i <= 23)) {
+			reg = EDMA_REG_TXDESC2CMPL_MAP_3;
+		} else if ((i >= 24) && (i <= 29)) {
+			reg = EDMA_REG_TXDESC2CMPL_MAP_4;
+		} else {
+			reg = EDMA_REG_TXDESC2CMPL_MAP_5;
+		}
+
+		edma_debug("Configure TXDESC:%u to use TXCMPL:%u\n", i, desc_index);
+
+		/*
+		 * Set the Tx complete descriptor ring number in the mapping register.
+		 * E.g. If (txcmpl ring)desc_index = 31, (txdesc ring)i = 28.
+		 * 	reg = EDMA_REG_TXDESC2CMPL_MAP_4
+		 * 	data |= (desc_index & 0x1F) << ((i % 6) * 5);
+		 * 	data |= (0x1F << 20); -
+		 * 	This sets 11111 at 20th bit of register EDMA_REG_TXDESC2CMPL_MAP_4
+		 */
+		data = edma_reg_read(reg);
+		data |= (desc_index & EDMA_TXDESC2CMPL_MAP_TXDESC_MASK) << ((i % 6) * 5);
+		edma_reg_write(reg, data);
+
+		egc->tx_to_txcmpl_map[i] = desc_index;
+
+		desc_index++;
+		if (desc_index == egc->txcmpl_ring_end) {
+			desc_index = egc->txcmpl_ring_start;
+		}
+	}
+
+	edma_debug("EDMA_REG_TXDESC2CMPL_MAP_0: 0x%x\n", edma_reg_read(EDMA_REG_TXDESC2CMPL_MAP_0));
+	edma_debug("EDMA_REG_TXDESC2CMPL_MAP_1: 0x%x\n", edma_reg_read(EDMA_REG_TXDESC2CMPL_MAP_1));
+	edma_debug("EDMA_REG_TXDESC2CMPL_MAP_2: 0x%x\n", edma_reg_read(EDMA_REG_TXDESC2CMPL_MAP_2));
+	edma_debug("EDMA_REG_TXDESC2CMPL_MAP_3: 0x%x\n", edma_reg_read(EDMA_REG_TXDESC2CMPL_MAP_3));
+	edma_debug("EDMA_REG_TXDESC2CMPL_MAP_4: 0x%x\n", edma_reg_read(EDMA_REG_TXDESC2CMPL_MAP_4));
+	edma_debug("EDMA_REG_TXDESC2CMPL_MAP_5: 0x%x\n", edma_reg_read(EDMA_REG_TXDESC2CMPL_MAP_5));
+}
+
+/*
+ * edma_cfg_tx_rings_setup()
+ *	Allocate/setup resources for EDMA rings
+ */
+static int edma_cfg_tx_rings_setup(struct edma_gbl_ctx *egc)
+{
+	uint32_t i, j = 0;
+
+	/*
+	 * Set Txdesc flow control group id
+	 */
+	for (i = 0; i < EDMA_TX_RING_PER_CORE_MAX; i++) {
+		for_each_possible_cpu(j) {
+			struct edma_txdesc_ring *txdesc_ring = NULL;
+			uint32_t txdesc_idx = egc->tx_map[i][j]
+						- egc->txdesc_ring_start;
+
+			txdesc_ring = &egc->txdesc_rings[txdesc_idx];
+			txdesc_ring->fc_grp_id = egc->tx_fc_grp_map[i];
+		}
+	}
+
+	/*
+	 * Allocate TxDesc ring descriptors
+	 */
+	for (i = 0; i < egc->num_txdesc_rings; i++) {
+		struct edma_txdesc_ring *txdesc_ring = NULL;
+		int32_t ret;
+
+		txdesc_ring = &egc->txdesc_rings[i];
+		txdesc_ring->count = EDMA_TX_RING_SIZE;
+		txdesc_ring->id = egc->txdesc_ring_start + i;
+
+		ret = edma_cfg_tx_desc_ring_setup(txdesc_ring);
+		if (ret != 0) {
+			edma_err("Error in setting up %d txdesc ring. ret: %d",
+					 txdesc_ring->id, ret);
+			while (i-- >= 0) {
+				edma_cfg_tx_desc_ring_cleanup(egc,
+					&egc->txdesc_rings[i]);
+			}
+
+			return -ENOMEM;
+		}
+	}
+
+	/*
+	 * Allocate TxCmpl ring descriptors
+	 */
+	for (i = 0; i < egc->num_txcmpl_rings; i++) {
+		struct edma_txcmpl_ring *txcmpl_ring = NULL;
+		int32_t ret;
+
+		txcmpl_ring = &egc->txcmpl_rings[i];
+		txcmpl_ring->count = EDMA_TX_RING_SIZE;
+		txcmpl_ring->id = egc->txcmpl_ring_start + i;
+
+		ret = edma_cfg_tx_cmpl_ring_setup(txcmpl_ring);
+		if (ret != 0) {
+			edma_err("Error in setting up %d txcmpl ring. ret: %d",
+					 txcmpl_ring->id, ret);
+			while (i-- >= 0) {
+				edma_cfg_tx_cmpl_ring_cleanup(egc,
+						&egc->txcmpl_rings[i]);
+			}
+
+			goto txcmpl_mem_alloc_fail;
+		}
+	}
+
+	edma_cfg_tx_cmpl_mapping_fill(egc);
+
+	return 0;
+
+txcmpl_mem_alloc_fail:
+	for (i = 0; i < egc->num_txdesc_rings; i++)
+		edma_cfg_tx_desc_ring_cleanup(egc, &egc->txdesc_rings[i]);
+
+	return -ENOMEM;
+}
+
+/*
+ * edma_cfg_tx_rings_alloc()
+ *	Allocate EDMA Tx rings
+ */
+int32_t edma_cfg_tx_rings_alloc(struct edma_gbl_ctx *egc)
+{
+	egc->txdesc_rings = kzalloc((sizeof(struct edma_txdesc_ring) *
+				egc->num_txdesc_rings), GFP_KERNEL);
+	if (!egc->txdesc_rings) {
+		edma_err("Error in allocating txdesc ring\n");
+		return -ENOMEM;
+	}
+
+	egc->txcmpl_rings = kzalloc((sizeof(struct edma_txcmpl_ring) *
+				egc->num_txcmpl_rings), GFP_KERNEL);
+	if (!egc->txcmpl_rings) {
+		edma_err("Error in allocating txcmpl ring\n");
+		goto txcmpl_ring_alloc_fail;
+	}
+
+	edma_info("Num rings - TxDesc:%u (%u-%u) TxCmpl:%u (%u-%u)\n",
+			egc->num_txdesc_rings, egc->txdesc_ring_start,
+			(egc->txdesc_ring_start + egc->num_txdesc_rings - 1),
+			egc->num_txcmpl_rings, egc->txcmpl_ring_start,
+			(egc->txcmpl_ring_start + egc->num_txcmpl_rings - 1));
+
+	if (edma_cfg_tx_rings_setup(egc)) {
+		edma_err("Error in setting up tx rings\n");
+		goto tx_rings_setup_fail;
+	}
+
+	return 0;
+
+tx_rings_setup_fail:
+	kfree(egc->txcmpl_rings);
+	egc->txcmpl_rings = NULL;
+txcmpl_ring_alloc_fail:
+	kfree(egc->txdesc_rings);
+	egc->txdesc_rings = NULL;
+	return -ENOMEM;
+}
+
+/*
+ * edma_cfg_tx_rings_cleanup()
+ *	Cleanup EDMA rings
+ */
+void edma_cfg_tx_rings_cleanup(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	/*
+	 * Free any buffers assigned to any descriptors
+	 */
+	for (i = 0; i < egc->num_txdesc_rings; i++) {
+		edma_cfg_tx_desc_ring_cleanup(egc, &egc->txdesc_rings[i]);
+	}
+
+	/*
+	 * Free Tx completion descriptors
+	 */
+	for (i = 0; i < egc->num_txcmpl_rings; i++) {
+		edma_cfg_tx_cmpl_ring_cleanup(egc, &egc->txcmpl_rings[i]);
+	}
+
+	kfree(egc->txdesc_rings);
+	kfree(egc->txcmpl_rings);
+	egc->txdesc_rings = NULL;
+	egc->txcmpl_rings = NULL;
+}
+
+/*
+ * edma_cfg_tx_rings()
+ *	Configure EDMA rings
+ */
+void edma_cfg_tx_rings(struct edma_gbl_ctx *egc)
+{
+	uint32_t i = 0;
+
+	/*
+	 * Configure TXDESC ring
+	 */
+	for (i = 0; i < egc->num_txdesc_rings; i++) {
+		edma_cfg_tx_desc_ring_configure(&egc->txdesc_rings[i]);
+	}
+
+	/*
+	 * Configure TXCMPL ring
+	 */
+	for (i = 0; i < egc->num_txcmpl_rings; i++) {
+		edma_cfg_tx_cmpl_ring_configure(&egc->txcmpl_rings[i]);
+	}
+}
+
+/*
+ * edma_cfg_tx_napi_enable()
+ *	Enable Tx NAPI
+ */
+void edma_cfg_tx_napi_enable(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	for (i = 0; i < egc->num_txcmpl_rings; i++) {
+		struct edma_txcmpl_ring *txcmpl_ring;
+
+		txcmpl_ring = &egc->txcmpl_rings[i];
+
+		if (!txcmpl_ring->napi_added) {
+			continue;
+		}
+
+		/*
+		 * TODO:
+		 * Enable NAPI separately for each port at the time of DP open
+		 */
+		napi_enable(&txcmpl_ring->napi);
+	}
+}
+
+/*
+ * edma_cfg_tx_napi_disable()
+ *	Disable Tx NAPI
+ */
+void edma_cfg_tx_napi_disable(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	for (i = 0; i < egc->num_txcmpl_rings; i++) {
+		struct edma_txcmpl_ring *txcmpl_ring;
+
+		txcmpl_ring = &egc->txcmpl_rings[i];
+
+		if (!txcmpl_ring->napi_added) {
+			continue;
+		}
+
+		napi_disable(&txcmpl_ring->napi);
+	}
+}
+
+/*
+ * edma_cfg_tx_napi_delete()
+ *	Delete Tx NAPI
+ */
+void edma_cfg_tx_napi_delete(struct edma_gbl_ctx *egc)
+{
+	uint32_t i;
+
+	for (i = 0; i < egc->num_txcmpl_rings; i++) {
+		struct edma_txcmpl_ring *txcmpl_ring;
+
+		txcmpl_ring = &egc->txcmpl_rings[i];
+
+		if (!txcmpl_ring->napi_added) {
+			continue;
+		}
+
+		netif_napi_del(&txcmpl_ring->napi);
+		txcmpl_ring->napi_added = false;
+	}
+}
+
+/*
+ * edma_cfg_tx_napi_add()
+ *	TX NAPI add API
+ */
+void edma_cfg_tx_napi_add(struct edma_gbl_ctx *egc, struct net_device *netdev)
+{
+	uint32_t i;
+
+	if ((nss_dp_tx_napi_budget < EDMA_TX_NAPI_WORK_MIN) ||
+		(nss_dp_tx_napi_budget > EDMA_TX_NAPI_WORK_MAX)) {
+		edma_err("Incorrect Tx NAPI budget: %d, setting to default: %d",
+				nss_dp_tx_napi_budget, NSS_DP_HAL_TX_NAPI_BUDGET);
+		nss_dp_tx_napi_budget = NSS_DP_HAL_TX_NAPI_BUDGET;
+	}
+
+	for (i = 0; i < egc->num_txcmpl_rings; i++) {
+		struct edma_txcmpl_ring *txcmpl_ring = &egc->txcmpl_rings[i];
+
+		netif_napi_add(netdev, &txcmpl_ring->napi,
+				edma_tx_napi_poll, nss_dp_tx_napi_budget);
+		txcmpl_ring->napi_added = true;
+	}
+}
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_cfg_tx.h b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_cfg_tx.h
new file mode 100644
index 0000000..cf94f7f
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_cfg_tx.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __EDMA_CFG_TX_H__
+#define __EDMA_CFG_TX_H__
+
+#define EDMA_TX_NAPI_WORK_MIN   16
+#define EDMA_TX_NAPI_WORK_MAX	512
+
+#define EDMA_TX_MITIGATION_TIMER_MIN	0	/* Tx mitigation timer's minimum value in microseconds */
+#define EDMA_TX_MITIGATION_TIMER_MAX	1000	/* Tx mitigation timer's maximum value in microseconds */
+#define EDMA_TX_MITIGATION_PKT_CNT_MIN	0	/* Tx mitigation packet count's minimum value */
+#define EDMA_TX_MITIGATION_PKT_CNT_MAX	256	/* Tx mitigation packet count's maximum value */
+
+void edma_cfg_tx_rings(struct edma_gbl_ctx *egc);
+int32_t edma_cfg_tx_rings_alloc(struct edma_gbl_ctx *egc);
+void edma_cfg_tx_rings_cleanup(struct edma_gbl_ctx *egc);
+void edma_cfg_tx_napi_enable(struct edma_gbl_ctx *egc);
+void edma_cfg_tx_napi_disable(struct edma_gbl_ctx *egc);
+void edma_cfg_tx_napi_delete(struct edma_gbl_ctx *egc);
+void edma_cfg_tx_napi_add(struct edma_gbl_ctx *egc, struct net_device *netdev);
+void edma_cfg_tx_mapping(struct edma_gbl_ctx *egc);
+void edma_cfg_tx_rings_enable(struct edma_gbl_ctx *egc);
+void edma_cfg_tx_rings_disable(struct edma_gbl_ctx *egc);
+void edma_cfg_tx_fill_per_port_tx_map(struct net_device *netdev, uint32_t macid);
+#endif	/* __EDMA_CFG_TX_H__ */
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_debug.h b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_debug.h
new file mode 100644
index 0000000..79435b6
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_debug.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __EDMA_DEBUG_H__
+#define __EDMA_DEBUG_H__
+
+#if (EDMA_DEBUG_LEVEL < 1)
+#define edma_err(s, ...)
+#else
+#define edma_err(s, ...) pr_err("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (EDMA_DEBUG_LEVEL < 2)
+#define edma_warn(s, ...)
+#else
+#define edma_warn(s, ...) pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (EDMA_DEBUG_LEVEL < 3)
+#define edma_info(s, ...)
+#else
+#define edma_info(s, ...) pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (EDMA_DEBUG_LEVEL < 4)
+#define edma_debug(s, ...)
+#else
+#if defined(CONFIG_DYNAMIC_DEBUG)
+#define edma_debug(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#else
+#define edma_debug(s, ...) printk(KERN_DEBUG"%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif
+
+#endif	/*__EDMA_DEBUG_H__ */
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_debugfs.c b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_debugfs.c
new file mode 100644
index 0000000..6b52351
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_debugfs.c
@@ -0,0 +1,431 @@
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/debugfs.h>
+#include "edma.h"
+#include "edma_debug.h"
+#include "edma_debugfs.h"
+
+/*
+ * edma_debugfs_print_banner()
+ *	API to print the banner for a node
+ */
+static void edma_debugfs_print_banner(struct seq_file *m, char *node)
+{
+	uint32_t banner_char_len, i;
+
+	for (i = 0; i < EDMA_STATS_BANNER_MAX_LEN; i++) {
+		seq_printf(m, "_");
+	}
+
+	banner_char_len = (EDMA_STATS_BANNER_MAX_LEN - (strlen(node) + 2)) / 2;
+
+	seq_printf(m, "\n\n");
+
+	for (i = 0; i < banner_char_len; i++) {
+		seq_printf(m, "<");
+	}
+
+	seq_printf(m, " %s ", node);
+
+	for (i = 0; i < banner_char_len; i++) {
+		seq_printf(m, ">");
+	}
+	seq_printf(m, "\n");
+
+	for (i = 0; i < EDMA_STATS_BANNER_MAX_LEN; i++) {
+		seq_printf(m, "_");
+	}
+
+	seq_printf(m, "\n\n");
+}
+
+/*
+ * edma_debugfs_rx_rings_stats_show()
+ *	EDMA debugfs rx rings stats show API
+ */
+static int edma_debugfs_rx_rings_stats_show(struct seq_file *m, void __attribute__((unused))*p)
+{
+	struct edma_rx_fill_stats *rx_fill_stats;
+	struct edma_rx_desc_stats *rx_desc_stats;
+	struct edma_gbl_ctx *egc = &edma_gbl_ctx;
+	uint32_t rx_fill_start_id = egc->rxfill_ring_start;
+	uint32_t rx_desc_start_id = egc->rxdesc_ring_start;
+	uint32_t i;
+	unsigned int start;
+
+	rx_fill_stats = kzalloc(egc->num_rxfill_rings * sizeof(struct edma_rx_fill_stats),
+				 GFP_KERNEL);
+	if (!rx_fill_stats) {
+		edma_err("Error in allocating the Rx fill stats buffer\n");
+		return -ENOMEM;
+	}
+
+	rx_desc_stats = kzalloc(egc->num_rxdesc_rings * sizeof(struct edma_rx_desc_stats),
+				 GFP_KERNEL);
+	if (!rx_desc_stats) {
+		edma_err("Error in allocating the Rx descriptor stats buffer\n");
+		kfree(rx_fill_stats);
+		return -ENOMEM;
+	}
+
+	/*
+	 * Get stats for Rx fill rings
+	 */
+	for (i = 0; i < egc->num_rxfill_rings; i++) {
+		struct edma_rxfill_ring *rxfill_ring;
+		struct edma_rx_fill_stats *stats;
+
+		rxfill_ring = &egc->rxfill_rings[i];
+		stats = &rxfill_ring->rx_fill_stats;
+		do {
+			start = u64_stats_fetch_begin_irq(&stats->syncp);
+			rx_fill_stats[i].alloc_failed = stats->alloc_failed;
+			rx_fill_stats[i].page_alloc_failed = stats->page_alloc_failed;
+		} while (u64_stats_fetch_retry_irq(&stats->syncp, start));
+	}
+
+	/*
+	 * Get stats for Rx Desc rings
+	 */
+	for (i = 0; i < edma_gbl_ctx.num_rxdesc_rings; i++) {
+		struct edma_rxdesc_ring *rxdesc_ring;
+		struct edma_rx_desc_stats *stats;
+
+		rxdesc_ring = &egc->rxdesc_rings[i];
+		stats = &rxdesc_ring->rx_desc_stats;
+		do {
+			start = u64_stats_fetch_begin_irq(&stats->syncp);
+			rx_desc_stats[i].src_port_inval = stats->src_port_inval;
+			rx_desc_stats[i].src_port_inval_type = stats->src_port_inval_type;
+			rx_desc_stats[i].src_port_inval_netdev = stats->src_port_inval_netdev;
+		} while (u64_stats_fetch_retry_irq(&stats->syncp, start));
+	}
+
+	edma_debugfs_print_banner(m, EDMA_RX_RING_STATS_NODE_NAME);
+
+	seq_printf(m, "\n#EDMA RX descriptor rings stats:\n\n");
+	for (i = 0; i < edma_gbl_ctx.num_rxdesc_rings; i++) {
+		seq_printf(m, "\t\tEDMA RX descriptor %d ring stats:\n", i + rx_desc_start_id);
+		seq_printf(m, "\t\t rxdesc[%d]:src_port_inval = %llu\n",
+				i + rx_desc_start_id, rx_desc_stats[i].src_port_inval);
+		seq_printf(m, "\t\t rxdesc[%d]:src_port_inval_type = %llu\n",
+				i + rx_desc_start_id, rx_desc_stats[i].src_port_inval_type);
+		seq_printf(m, "\t\t rxdesc[%d]:src_port_inval_netdev = %llu\n",
+				i + rx_desc_start_id,
+				rx_desc_stats[i].src_port_inval_netdev);
+		seq_printf(m, "\n");
+	}
+
+	seq_printf(m, "\n#EDMA RX fill rings stats:\n\n");
+	for (i = 0; i < edma_gbl_ctx.num_rxfill_rings; i++) {
+		seq_printf(m, "\t\tEDMA RX fill %d ring stats:\n", i + rx_fill_start_id);
+		seq_printf(m, "\t\t rxfill[%d]:alloc_failed = %llu\n",
+				i + rx_fill_start_id, rx_fill_stats[i].alloc_failed);
+		seq_printf(m, "\t\t rxfill[%d]:page_alloc_failed = %llu\n",
+				i + rx_fill_start_id, rx_fill_stats[i].page_alloc_failed);
+		seq_printf(m, "\n");
+	}
+
+	kfree(rx_fill_stats);
+	kfree(rx_desc_stats);
+	return 0;
+}
+
+/*
+ * edma_debugfs_tx_rings_stats_show()
+ *	EDMA debugfs Tx rings stats show API
+ */
+static int edma_debugfs_tx_rings_stats_show(struct seq_file *m, void __attribute__((unused))*p)
+{
+	struct edma_tx_cmpl_stats *tx_cmpl_stats;
+	struct edma_tx_desc_stats *tx_desc_stats;
+	struct edma_gbl_ctx *egc = &edma_gbl_ctx;
+	uint32_t tx_cmpl_start_id = egc->txcmpl_ring_start;
+	uint32_t tx_desc_start_id = egc->txdesc_ring_start;
+	uint32_t i;
+	unsigned int start;
+
+	tx_cmpl_stats = kzalloc(egc->num_txcmpl_rings * sizeof(struct edma_tx_cmpl_stats), GFP_KERNEL);
+	if (!tx_cmpl_stats) {
+		edma_err("Error in allocating the Tx complete stats buffer\n");
+		return -ENOMEM;
+	}
+
+	tx_desc_stats = kzalloc(egc->num_txdesc_rings * sizeof(struct edma_tx_desc_stats), GFP_KERNEL);
+	if (!tx_desc_stats) {
+		edma_err("Error in allocating the Tx descriptor stats buffer\n");
+		kfree(tx_cmpl_stats);
+		return -ENOMEM;
+	}
+
+	/*
+	 * Get stats for Tx desc rings
+	 */
+	for (i = 0; i < egc->num_txdesc_rings; i++) {
+		struct edma_txdesc_ring *txdesc_ring;
+		struct edma_tx_desc_stats *stats;
+
+		txdesc_ring = &egc->txdesc_rings[i];
+		stats = &txdesc_ring->tx_desc_stats;
+		do {
+			start = u64_stats_fetch_begin_irq(&stats->syncp);
+			tx_desc_stats[i].no_desc_avail = stats->no_desc_avail;
+		} while (u64_stats_fetch_retry_irq(&stats->syncp, start));
+	}
+
+	/*
+	 * Get stats for Tx Complete rings
+	 */
+	for (i = 0; i < egc->num_txcmpl_rings; i++) {
+		struct edma_txcmpl_ring *txcmpl_ring;
+		struct edma_tx_cmpl_stats *stats;
+
+		txcmpl_ring = &egc->txcmpl_rings[i];
+		stats = &txcmpl_ring->tx_cmpl_stats;
+		do {
+			start = u64_stats_fetch_begin_irq(&stats->syncp);
+			tx_cmpl_stats[i].invalid_buffer = stats->invalid_buffer;
+			tx_cmpl_stats[i].errors = stats->errors;
+			tx_cmpl_stats[i].desc_with_more_bit = stats->desc_with_more_bit;
+			tx_cmpl_stats[i].no_pending_desc = stats->no_pending_desc;
+		} while (u64_stats_fetch_retry_irq(&stats->syncp, start));
+	}
+
+	edma_debugfs_print_banner(m, EDMA_TX_RING_STATS_NODE_NAME);
+
+	seq_printf(m, "\n#EDMA TX complete rings stats:\n\n");
+	for (i = 0; i < edma_gbl_ctx.num_txcmpl_rings; i++) {
+		seq_printf(m, "\t\tEDMA TX complete %d ring stats:\n", i + tx_cmpl_start_id);
+		seq_printf(m, "\t\t txcmpl[%d]:invalid_buffer = %llu\n",
+				i + tx_cmpl_start_id, tx_cmpl_stats[i].invalid_buffer);
+		seq_printf(m, "\t\t txcmpl[%d]:errors = %llu\n",
+				i + tx_cmpl_start_id, tx_cmpl_stats[i].errors);
+		seq_printf(m, "\t\t txcmpl[%d]:desc_with_more_bit = %llu\n",
+				i + tx_cmpl_start_id, tx_cmpl_stats[i].desc_with_more_bit);
+		seq_printf(m, "\t\t txcmpl[%d]:no_pending_desc = %llu\n",
+				i + tx_cmpl_start_id, tx_cmpl_stats[i].no_pending_desc);
+		seq_printf(m, "\n");
+	}
+
+	seq_printf(m, "\n#EDMA TX descriptor rings stats:\n\n");
+	for (i = 0; i < edma_gbl_ctx.num_txdesc_rings; i++) {
+		seq_printf(m, "\t\tEDMA TX descriptor %d ring stats:\n", i + tx_desc_start_id);
+		seq_printf(m, "\t\t txdesc[%d]:no_desc_avail = %llu\n",
+				i + tx_desc_start_id, tx_desc_stats[i].no_desc_avail);
+		seq_printf(m, "\n");
+	}
+
+	kfree(tx_cmpl_stats);
+	kfree(tx_desc_stats);
+	return 0;
+}
+
+/*
+ * edma_debugfs_misc_stats_show()
+ *	EDMA debugfs miscellaneous stats show API
+ */
+static int edma_debugfs_misc_stats_show(struct seq_file *m, void __attribute__((unused))*p)
+{
+	struct edma_misc_stats *misc_stats, *pcpu_misc_stats;
+	uint32_t cpu;
+	unsigned int start;
+
+	misc_stats = kzalloc(sizeof(struct edma_misc_stats), GFP_KERNEL);
+	if (!misc_stats) {
+		edma_err("Error in allocating the miscellaneous stats buffer\n");
+		return -ENOMEM;
+	}
+
+	/*
+	 * Get percpu EDMA miscellaneous stats
+	 */
+	for_each_possible_cpu(cpu) {
+		pcpu_misc_stats = per_cpu_ptr(edma_gbl_ctx.misc_stats, cpu);
+		do {
+			start = u64_stats_fetch_begin_irq(&pcpu_misc_stats->syncp);
+			misc_stats->edma_misc_axi_read_err +=
+				pcpu_misc_stats->edma_misc_axi_read_err;
+			misc_stats->edma_misc_axi_write_err +=
+				pcpu_misc_stats->edma_misc_axi_write_err;
+			misc_stats->edma_misc_rx_desc_fifo_full +=
+				pcpu_misc_stats->edma_misc_rx_desc_fifo_full;
+			misc_stats->edma_misc_rx_buf_size_err +=
+				pcpu_misc_stats->edma_misc_rx_buf_size_err;
+			misc_stats->edma_misc_tx_sram_full +=
+				pcpu_misc_stats->edma_misc_tx_sram_full;
+			misc_stats->edma_misc_tx_data_len_err +=
+				pcpu_misc_stats->edma_misc_tx_data_len_err;
+			misc_stats->edma_misc_tx_timeout +=
+				pcpu_misc_stats->edma_misc_tx_timeout;
+			misc_stats->edma_misc_tx_cmpl_buf_full +=
+				pcpu_misc_stats->edma_misc_tx_cmpl_buf_full;
+		} while (u64_stats_fetch_retry_irq(&pcpu_misc_stats->syncp, start));
+	}
+
+	edma_debugfs_print_banner(m, EDMA_MISC_STATS_NODE_NAME);
+
+	seq_printf(m, "\n#EDMA miscellaneous stats:\n\n");
+	seq_printf(m, "\t\t miscellaneous axi read error = %llu\n",
+			misc_stats->edma_misc_axi_read_err);
+	seq_printf(m, "\t\t miscellaneous axi write error = %llu\n",
+			misc_stats->edma_misc_axi_write_err);
+	seq_printf(m, "\t\t miscellaneous Rx descriptor fifo full = %llu\n",
+			misc_stats->edma_misc_rx_desc_fifo_full);
+	seq_printf(m, "\t\t miscellaneous Rx buffer size error = %llu\n",
+			misc_stats->edma_misc_rx_buf_size_err);
+	seq_printf(m, "\t\t miscellaneous Tx SRAM full = %llu\n",
+			misc_stats->edma_misc_tx_sram_full);
+	seq_printf(m, "\t\t miscellaneous Tx data length error = %llu\n",
+			misc_stats->edma_misc_tx_data_len_err);
+	seq_printf(m, "\t\t miscellaneous Tx timeout = %llu\n",
+			misc_stats->edma_misc_tx_timeout);
+	seq_printf(m, "\t\t miscellaneous Tx completion buffer full = %llu\n",
+			misc_stats->edma_misc_tx_cmpl_buf_full);
+
+	kfree(misc_stats);
+	return 0;
+}
+
+/*
+ * edma_debugs_rx_rings_stats_open()
+ *	EDMA debugfs Rx rings open callback API
+ */
+static int edma_debugs_rx_rings_stats_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, edma_debugfs_rx_rings_stats_show, inode->i_private);
+}
+
+/*
+ * edma_debugfs_rx_rings_file_ops
+ *	File operations for EDMA Rx rings stats
+ */
+const struct file_operations edma_debugfs_rx_rings_file_ops = {
+	.open = edma_debugs_rx_rings_stats_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = seq_release
+};
+
+/*
+ * edma_debugs_tx_rings_stats_open()
+ *	EDMA debugfs Tx rings open callback API
+ */
+static int edma_debugs_tx_rings_stats_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, edma_debugfs_tx_rings_stats_show, inode->i_private);
+}
+
+/*
+ * edma_debugfs_tx_rings_file_ops
+ *	File operations for EDMA Tx rings stats
+ */
+const struct file_operations edma_debugfs_tx_rings_file_ops = {
+	.open = edma_debugs_tx_rings_stats_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = seq_release
+};
+
+/*
+ * edma_debugs_misc_stats_open()
+ *	EDMA debugfs miscellaneous stats open callback API
+ */
+static int edma_debugs_misc_stats_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, edma_debugfs_misc_stats_show, inode->i_private);
+}
+
+/*
+ * edma_debugfs_misc_file_ops
+ *	File operations for EDMA miscellaneous stats
+ */
+const struct file_operations edma_debugfs_misc_file_ops = {
+	.open = edma_debugs_misc_stats_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = seq_release
+};
+
+/*
+ * edma_debugfs_init()
+ *	EDMA debugfs init API
+ */
+int edma_debugfs_init(void)
+{
+	edma_gbl_ctx.root_dentry = debugfs_create_dir("qca-nss-dp", NULL);
+	if (!edma_gbl_ctx.root_dentry) {
+		edma_err("Unable to create debugfs qca-nss-dp directory in debugfs\n");
+		return -1;
+	}
+
+	edma_gbl_ctx.stats_dentry = debugfs_create_dir("stats", edma_gbl_ctx.root_dentry);
+	if (!edma_gbl_ctx.stats_dentry) {
+		edma_err("Unable to create debugfs stats directory in debugfs\n");
+		goto debugfs_dir_failed;
+	}
+
+	if (!debugfs_create_file("rx_ring_stats", S_IRUGO, edma_gbl_ctx.stats_dentry,
+			NULL, &edma_debugfs_rx_rings_file_ops)) {
+		edma_err("Unable to create Rx rings statistics file entry in debugfs\n");
+		goto debugfs_dir_failed;
+	}
+
+	if (!debugfs_create_file("tx_ring_stats", S_IRUGO, edma_gbl_ctx.stats_dentry,
+			NULL, &edma_debugfs_tx_rings_file_ops)) {
+		edma_err("Unable to create Tx rings statistics file entry in debugfs\n");
+		goto debugfs_dir_failed;
+	}
+
+	/*
+	 * Allocate memory for EDMA miscellaneous stats
+	 */
+	if (edma_misc_stats_alloc() < 0) {
+		edma_err("Unable to allocate miscellaneous percpu stats\n");
+		goto debugfs_dir_failed;
+	}
+
+	if (!debugfs_create_file("misc_stats", S_IRUGO, edma_gbl_ctx.stats_dentry,
+			NULL, &edma_debugfs_misc_file_ops)) {
+		edma_err("Unable to create EDMA miscellaneous statistics file entry in debugfs\n");
+		goto debugfs_dir_failed;
+	}
+
+	return 0;
+
+debugfs_dir_failed:
+	debugfs_remove_recursive(edma_gbl_ctx.root_dentry);
+	edma_gbl_ctx.root_dentry = NULL;
+	edma_gbl_ctx.stats_dentry = NULL;
+	return -1;
+}
+
+/*
+ * edma_debugfs_exit()
+ *	EDMA debugfs exit API
+ */
+void edma_debugfs_exit(void)
+{
+	/*
+	 * Free EDMA miscellaneous stats memory
+	 */
+	edma_misc_stats_free();
+
+	if (edma_gbl_ctx.root_dentry) {
+		debugfs_remove_recursive(edma_gbl_ctx.root_dentry);
+		edma_gbl_ctx.root_dentry = NULL;
+		edma_gbl_ctx.stats_dentry = NULL;
+	}
+}
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_debugfs.h b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_debugfs.h
new file mode 100644
index 0000000..a3b9cea
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_debugfs.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __EDMA_DEBUGFS_H__
+#define __EDMA_DEBUGFS_H__
+
+#define EDMA_STATS_BANNER_MAX_LEN	80
+#define EDMA_RX_RING_STATS_NODE_NAME	"EDMA_RX"
+#define EDMA_TX_RING_STATS_NODE_NAME	"EDMA_TX"
+#define EDMA_MISC_STATS_NODE_NAME	"EDMA_MISC"
+
+int edma_debugfs_init(void);
+void edma_debugfs_exit(void);
+
+#endif	// __EDMA_DEBUGFS_H__
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_dp.c b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_dp.c
new file mode 100644
index 0000000..a60db87
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_dp.c
@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <fal/fal_vsi.h>
+#include "edma.h"
+#include "edma_cfg_tx.h"
+#include "edma_cfg_rx.h"
+#include "edma_debug.h"
+#include "nss_dp_api_if.h"
+#include "nss_dp_dev.h"
+
+/*
+ * edma_dp_open()
+ *	Do slow path data plane open
+ */
+static int edma_dp_open(struct nss_dp_data_plane_ctx *dpc,
+			uint32_t tx_desc_ring, uint32_t rx_desc_ring,
+			uint32_t mode)
+{
+	if (!dpc->dev) {
+		return NSS_DP_FAILURE;
+	}
+
+	/*
+	 * Enable NAPI
+	 */
+	if (atomic_read(&edma_gbl_ctx.active_port_count) != 0) {
+		atomic_inc(&edma_gbl_ctx.active_port_count);
+		return NSS_DP_SUCCESS;
+	}
+	atomic_inc(&edma_gbl_ctx.active_port_count);
+
+	/*
+	 * TODO:
+	 * Enable interrupts and NAPI only for the Tx-cmpl rings mapped to this port
+	 */
+	edma_cfg_tx_napi_enable(&edma_gbl_ctx);
+	edma_cfg_rx_napi_enable(&edma_gbl_ctx);
+
+	/*
+	 * Enable the interrupt masks.
+	 */
+	edma_enable_interrupts(&edma_gbl_ctx);
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_dp_close()
+ *	Do slow path data plane close
+ */
+static int edma_dp_close(struct nss_dp_data_plane_ctx *dpc)
+{
+	if (!atomic_dec_and_test(&edma_gbl_ctx.active_port_count)) {
+		return NSS_DP_SUCCESS;
+	}
+
+	/*
+	 * Disable the interrupt masks.
+	 */
+	edma_disable_interrupts(&edma_gbl_ctx);
+
+	/*
+	 * TODO:
+	 *  Disable interrupts and NAPI only for the Tx-cmpl rings mapped to this port
+	 */
+	edma_cfg_rx_napi_disable(&edma_gbl_ctx);
+	edma_cfg_tx_napi_disable(&edma_gbl_ctx);
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_dp_link_state()
+ *	EDMA data plane link state API
+ */
+static int edma_dp_link_state(struct nss_dp_data_plane_ctx *dpc,
+						uint32_t link_state)
+{
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_dp_mac_addr()
+ *	EDMA data plane MAC address change API
+ */
+static int edma_dp_mac_addr(struct nss_dp_data_plane_ctx *dpc, uint8_t *addr)
+{
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_dp_change_mtu()
+ *	EDMA data plane MTU change API
+ */
+static int edma_dp_change_mtu(struct nss_dp_data_plane_ctx *dpc, uint32_t mtu)
+{
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_dp_xmit()
+ *	Transmit a packet using EDMA
+ */
+static netdev_tx_t edma_dp_xmit(struct nss_dp_data_plane_ctx *dpc,
+				struct sk_buff *skb)
+{
+	struct net_device *netdev = dpc->dev;
+	struct edma_txdesc_ring *txdesc_ring;
+	struct edma_pcpu_stats *pcpu_stats;
+	struct edma_tx_stats *stats;
+	struct nss_dp_dev *dp_dev;
+	uint32_t skbq;
+	int ret;
+
+	/*
+	 * Select a TX ring
+	 */
+	skbq = (skb_get_queue_mapping(skb) & (NR_CPUS - 1));
+
+	dp_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	txdesc_ring = (struct edma_txdesc_ring *)dp_dev->dp_info.txr_map[0][skbq];
+
+	pcpu_stats = &dp_dev->dp_info.pcpu_stats;
+	stats = this_cpu_ptr(pcpu_stats->tx_stats);
+
+	/*
+	 * Transmit the packet
+	 */
+	ret = edma_tx_ring_xmit(netdev, skb, txdesc_ring, stats);
+	if (likely(ret == EDMA_TX_OK)) {
+		return NETDEV_TX_OK;
+	}
+
+	dev_kfree_skb_any(skb);
+	u64_stats_update_begin(&stats->syncp);
+	++stats->tx_drops;
+	u64_stats_update_end(&stats->syncp);
+
+	return NETDEV_TX_OK;
+}
+
+/*
+ * edma_dp_set_features()
+ *	Set the supported net_device features
+ */
+static void edma_dp_set_features(struct nss_dp_data_plane_ctx *dpc)
+{
+	struct net_device *netdev = dpc->dev;
+
+	netdev->features |= EDMA_NETDEV_FEATURES;
+	netdev->hw_features |= EDMA_NETDEV_FEATURES;
+	netdev->vlan_features |= EDMA_NETDEV_FEATURES;
+	netdev->wanted_features |= EDMA_NETDEV_FEATURES;
+}
+
+/* TODO - check if this is needed */
+/*
+ * edma_dp_pause_on_off()
+ *	Set pause frames on or off
+ *
+ * No need to send a message if we defaulted to slow path.
+ */
+static int edma_dp_pause_on_off(struct nss_dp_data_plane_ctx *dpc,
+				uint32_t pause_on)
+{
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_dp_get_ndo_stats
+ *	Get EDMA data plane stats
+ */
+static void edma_dp_get_ndo_stats(struct nss_dp_data_plane_ctx *dpc,
+					struct nss_dp_gmac_stats *stats)
+{
+	struct nss_dp_dev *dp_dev = netdev_priv(dpc->dev);
+	struct nss_dp_hal_info *dp_info = &dp_dev->dp_info;
+	struct edma_rx_stats *pcpu_rx_stats;
+	struct edma_tx_stats *pcpu_tx_stats;
+	int i;
+
+	memset(&stats->stats, 0, sizeof(struct nss_dp_hal_gmac_stats));
+
+	for_each_possible_cpu(i) {
+		struct edma_rx_stats rxp;
+		struct edma_tx_stats txp;
+		unsigned int start;
+		pcpu_rx_stats = per_cpu_ptr(dp_info->pcpu_stats.rx_stats, i);
+
+		do {
+			start = u64_stats_fetch_begin_irq(&pcpu_rx_stats->syncp);
+			memcpy(&rxp, pcpu_rx_stats, sizeof(*pcpu_rx_stats));
+		} while (u64_stats_fetch_retry_irq(&pcpu_rx_stats->syncp, start));
+
+		stats->stats.rx_packets += rxp.rx_pkts;
+		stats->stats.rx_bytes += rxp.rx_bytes;
+		stats->stats.rx_dropped += rxp.rx_drops;
+		stats->stats.rx_nr_frag_packets += rxp.rx_nr_frag_pkts;
+		stats->stats.rx_fraglist_packets += rxp.rx_fraglist_pkts;
+		stats->stats.rx_nr_frag_headroom_err += rxp.rx_nr_frag_headroom_err;
+
+		pcpu_tx_stats = per_cpu_ptr(dp_info->pcpu_stats.tx_stats, i);
+
+		do {
+			start = u64_stats_fetch_begin_irq(&pcpu_tx_stats->syncp);
+			memcpy(&txp, pcpu_tx_stats, sizeof(*pcpu_tx_stats));
+		} while (u64_stats_fetch_retry_irq(&pcpu_tx_stats->syncp, start));
+
+		stats->stats.tx_packets += txp.tx_pkts;
+		stats->stats.tx_bytes += txp.tx_bytes;
+		stats->stats.tx_dropped += txp.tx_drops;
+		stats->stats.tx_nr_frag_packets += txp.tx_nr_frag_pkts;
+		stats->stats.tx_fraglist_packets += txp.tx_fraglist_pkts;
+		stats->stats.tx_fraglist_with_nr_frags_packets += txp.tx_fraglist_with_nr_frags_pkts;
+		stats->stats.tx_tso_packets += txp.tx_tso_pkts;
+	}
+}
+
+#ifdef CONFIG_RFS_ACCEL
+/*
+ * edma_dp_rx_flow_steer()
+ *	Flow steer of the data plane
+ *
+ * Initial receive flow steering function for data plane operation.
+ */
+static int edma_dp_rx_flow_steer(struct nss_dp_data_plane_ctx *dpc, struct sk_buff *skb,
+					uint32_t cpu, bool is_add)
+{
+	return NSS_DP_SUCCESS;
+}
+#endif
+
+/*
+ * edma_dp_deinit()
+ *	Free edma resources
+ */
+static int edma_dp_deinit(struct nss_dp_data_plane_ctx *dpc)
+{
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *dp_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	free_percpu(dp_dev->dp_info.pcpu_stats.rx_stats);
+	free_percpu(dp_dev->dp_info.pcpu_stats.tx_stats);
+
+	/*
+	 * Free up resources used by EDMA if all the
+	 * interfaces have been overridden
+	 * */
+	if (edma_gbl_ctx.dp_override_cnt == EDMA_MAX_GMACS - 1) {
+		edma_cleanup(true);
+	} else {
+		edma_gbl_ctx.dp_override_cnt++;
+	}
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_dp_configure()
+ *	API to configure data plane
+ */
+static int edma_dp_configure(struct net_device *netdev, uint32_t macid)
+{
+	if (!netdev) {
+		edma_err("nss_dp_edma: Invalid netdev pointer %px\n", netdev);
+		return -EINVAL;
+	}
+
+	if ((macid < EDMA_START_GMACS) || (macid > EDMA_MAX_GMACS)) {
+		edma_err("nss_dp_edma: Invalid macid(%d) for %s\n",
+			macid, netdev->name);
+		return -EINVAL;
+	}
+
+	edma_info("nss_dp_edma: Registering netdev %s(qcom-id:%d) with EDMA\n",
+		netdev->name, macid);
+
+	/*
+	 * We expect 'macid' to correspond to ports numbers on
+	 * IPQ95xx. These begin from '1' and hence we subtract
+	 * one when using it as an array index.
+	 */
+	edma_gbl_ctx.netdev_arr[macid - 1] = netdev;
+
+	edma_cfg_tx_fill_per_port_tx_map(netdev, macid);
+
+	if (edma_gbl_ctx.napi_added) {
+		return 0;
+	}
+
+	/*
+	 * TX/RX NAPI addition
+	 */
+	edma_cfg_rx_napi_add(&edma_gbl_ctx, netdev);
+	edma_cfg_tx_napi_add(&edma_gbl_ctx, netdev);
+
+	/*
+	 * Register the interrupt handlers
+	 */
+	if (edma_irq_init() < 0) {
+		edma_cfg_rx_napi_delete(&edma_gbl_ctx);
+		edma_cfg_tx_napi_delete(&edma_gbl_ctx);
+		return -EINVAL;
+	}
+
+	edma_gbl_ctx.napi_added = true;
+	return 0;
+}
+
+/*
+ * edma_dp_init()
+ *	EDMA data plane init function
+ */
+static int edma_dp_init(struct nss_dp_data_plane_ctx *dpc)
+{
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *dp_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	int ret = 0;
+
+	/*
+	 * Allocate per-cpu stats memory
+	 */
+	dp_dev->dp_info.pcpu_stats.rx_stats =
+		netdev_alloc_pcpu_stats(struct edma_rx_stats);
+	if (!dp_dev->dp_info.pcpu_stats.rx_stats) {
+		netdev_err(netdev, "Percpu EDMA Rx stats alloc failed for %s\n",
+				netdev->name);
+		return NSS_DP_FAILURE;
+	}
+
+	dp_dev->dp_info.pcpu_stats.tx_stats =
+		netdev_alloc_pcpu_stats(struct edma_tx_stats);
+	if (!dp_dev->dp_info.pcpu_stats.tx_stats) {
+		netdev_err(netdev, "Percpu EDMA Tx stats alloc failed for %s\n",
+				netdev->name);
+		free_percpu(dp_dev->dp_info.pcpu_stats.rx_stats);
+		return NSS_DP_FAILURE;
+	}
+
+	/*
+	 * Configure the data plane
+	 */
+	ret = edma_dp_configure(netdev, dp_dev->macid);
+	if (ret) {
+		netdev_dbg(netdev, "Error configuring the data plane %s\n",
+				netdev->name);
+		free_percpu(dp_dev->dp_info.pcpu_stats.rx_stats);
+		free_percpu(dp_dev->dp_info.pcpu_stats.tx_stats);
+		return NSS_DP_FAILURE;
+	}
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * nss_dp_edma_ops
+ *	EDMA data plane operations
+ */
+struct nss_dp_data_plane_ops nss_dp_edma_ops = {
+	.init		= edma_dp_init,
+	.open		= edma_dp_open,
+	.close		= edma_dp_close,
+	.link_state	= edma_dp_link_state,
+	.mac_addr	= edma_dp_mac_addr,
+	.change_mtu	= edma_dp_change_mtu,
+	.xmit		= edma_dp_xmit,
+	.set_features	= edma_dp_set_features,
+	.pause_on_off	= edma_dp_pause_on_off,
+	.get_stats	= edma_dp_get_ndo_stats,
+#ifdef CONFIG_RFS_ACCEL
+	.rx_flow_steer	= edma_dp_rx_flow_steer,
+#endif
+	.deinit		= edma_dp_deinit,
+};
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_misc.c b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_misc.c
new file mode 100644
index 0000000..675a0f9
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_misc.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/debugfs.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include "edma.h"
+#include "edma_regs.h"
+#include "edma_debug.h"
+
+/*
+ * edma_misc_stats_alloc()
+ *	API to allocate memory for per-CPU miscellaneous stats
+ */
+int32_t edma_misc_stats_alloc()
+{
+	uint32_t i;
+
+	edma_gbl_ctx.misc_stats = alloc_percpu(struct edma_misc_stats);
+	if (!edma_gbl_ctx.misc_stats) {
+		edma_err("Unable to allocate miscellaneous percpu stats\n");
+		return -ENOMEM;
+	}
+
+	for_each_possible_cpu(i) {
+		struct edma_misc_stats *stats;
+
+		stats = per_cpu_ptr(edma_gbl_ctx.misc_stats, i);
+		u64_stats_init(&stats->syncp);
+	}
+
+	return 0;
+}
+
+/*
+ * edma_misc_stats_free()
+ *	API to free memory of per-CPU miscellaneous stats
+ */
+void edma_misc_stats_free()
+{
+	if (edma_gbl_ctx.misc_stats) {
+		free_percpu(edma_gbl_ctx.misc_stats);
+		edma_gbl_ctx.misc_stats = NULL;
+	}
+}
+
+/*
+ * edma_misc_handle_irq()
+ *	Process miscellaneous interrupts from EDMA
+ */
+irqreturn_t edma_misc_handle_irq(int irq, void *ctx)
+{
+	uint32_t misc_intr_status, reg_data;
+	struct edma_gbl_ctx *egc = &edma_gbl_ctx;
+	struct edma_misc_stats *stats = this_cpu_ptr(edma_gbl_ctx.misc_stats);
+
+	/*
+	 * Read Misc intr status
+	 */
+	reg_data = edma_reg_read(EDMA_REG_MISC_INT_STAT);
+	misc_intr_status = reg_data & egc->misc_intr_mask;
+
+	edma_debug("Received misc irq %d, status: %d\n", irq, misc_intr_status);
+
+	if (EDMA_MISC_AXI_RD_ERR_STATUS_GET(misc_intr_status)) {
+		edma_err("MISC AXI read error received\n");
+		u64_stats_update_begin(&stats->syncp);
+		++stats->edma_misc_axi_read_err;
+		u64_stats_update_end(&stats->syncp);
+	}
+
+	if (EDMA_MISC_AXI_WR_ERR_STATUS_GET(misc_intr_status)) {
+		edma_err("MISC AXI write error received\n");
+		u64_stats_update_begin(&stats->syncp);
+		++stats->edma_misc_axi_write_err;
+		u64_stats_update_end(&stats->syncp);
+	}
+
+	if (EDMA_MISC_RX_DESC_FIFO_FULL_STATUS_GET(misc_intr_status)) {
+		if (net_ratelimit()) {
+			edma_err("MISC Rx descriptor fifo full error received\n");
+		}
+		u64_stats_update_begin(&stats->syncp);
+		++stats->edma_misc_rx_desc_fifo_full;
+		u64_stats_update_end(&stats->syncp);
+	}
+
+	if (EDMA_MISC_RX_ERR_BUF_SIZE_STATUS_GET(misc_intr_status)) {
+		if (net_ratelimit()) {
+			edma_err("MISC Rx buffer size error received\n");
+		}
+		u64_stats_update_begin(&stats->syncp);
+		++stats->edma_misc_rx_buf_size_err;
+		u64_stats_update_end(&stats->syncp);
+	}
+
+	if (EDMA_MISC_TX_SRAM_FULL_STATUS_GET(misc_intr_status)) {
+		if (net_ratelimit()) {
+			edma_err("MISC Tx SRAM full error received\n");
+		}
+		u64_stats_update_begin(&stats->syncp);
+		++stats->edma_misc_tx_sram_full;
+		u64_stats_update_end(&stats->syncp);
+	}
+
+	if (EDMA_MISC_TX_CMPL_BUF_FULL_STATUS_GET(misc_intr_status)) {
+		if (net_ratelimit()) {
+			edma_err("MISC Tx complete buffer full error received\n");
+		}
+		u64_stats_update_begin(&stats->syncp);
+		++stats->edma_misc_tx_cmpl_buf_full;
+		u64_stats_update_end(&stats->syncp);
+	}
+
+	if (EDMA_MISC_DATA_LEN_ERR_STATUS_GET(misc_intr_status)) {
+		if (net_ratelimit()) {
+			edma_err("MISC data length error received\n");
+		}
+		u64_stats_update_begin(&stats->syncp);
+		++stats->edma_misc_tx_data_len_err;
+		u64_stats_update_end(&stats->syncp);
+	}
+
+	if (EDMA_MISC_TX_TIMEOUT_STATUS_GET(misc_intr_status)) {
+		if (net_ratelimit()) {
+			edma_err("MISC Tx timeout error received\n");
+		}
+		u64_stats_update_begin(&stats->syncp);
+		++stats->edma_misc_tx_timeout;
+		u64_stats_update_end(&stats->syncp);
+	}
+
+	return IRQ_HANDLED;
+}
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_regs.h b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_regs.h
new file mode 100644
index 0000000..38743bf
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_regs.h
@@ -0,0 +1,539 @@
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __EDMA_REGS__
+#define __EDMA_REGS__
+
+#define EDMA_GENMASK(end, start)	(uint32_t)((((uint64_t)1 << ((end) - (start) + 1)) - 1) << (start))
+
+/*
+ * EDMA register offsets
+ */
+#define EDMA_REG_MAS_CTRL		0x0
+#define EDMA_REG_PORT_CTRL		0x4
+#define EDMA_REG_VLAN_CTRL		0x8
+#define EDMA_REG_RXDESC2FILL_MAP_0	0x14
+#define EDMA_REG_RXDESC2FILL_MAP_1	0x18
+#define EDMA_REG_RXDESC2FILL_MAP_2	0x1c
+#define EDMA_REG_TXQ_CTRL		0x20
+#define EDMA_REG_TXQ_CTRL_2		0x24
+#define EDMA_REG_TXQ_FC_0		0x28
+#define EDMA_REG_TXQ_FC_1		0x30
+#define EDMA_REG_TXQ_FC_2		0x34
+#define EDMA_REG_TXQ_FC_3		0x38
+#define EDMA_REG_RXQ_CTRL		0x3c
+#define EDMA_REG_MISC_ERR_QID		0x40
+#define EDMA_REG_RXQ_FC_THRE		0x44
+#define EDMA_REG_DMAR_CTRL		0x48
+#define EDMA_REG_AXIR_CTRL		0x4c
+#define EDMA_REG_AXIW_CTRL		0x50
+#define EDMA_REG_MIN_MSS		0x54
+#define EDMA_REG_LOOPBACK_CTRL		0x58
+#define EDMA_REG_MISC_INT_STAT		0x5c
+#define EDMA_REG_MISC_INT_MASK		0x60
+#define EDMA_REG_DBG_CTRL		0x64
+#define EDMA_REG_DBG_DATA		0x68
+#define EDMA_REG_TX_TIMEOUT_THRESH	0x6c
+#define EDMA_REG_REQ0_FIFO_THRESH	0x80
+#define EDMA_REG_WB_OS_THRESH		0x84
+#define EDMA_REG_MISC_ERR_QID_REG2	0x88
+#define EDMA_REG_TXDESC2CMPL_MAP_0	0x8c
+#define EDMA_REG_TXDESC2CMPL_MAP_1	0x90
+#define EDMA_REG_TXDESC2CMPL_MAP_2	0x94
+#define EDMA_REG_TXDESC2CMPL_MAP_3	0x98
+#define EDMA_REG_TXDESC2CMPL_MAP_4	0x9c
+#define EDMA_REG_TXDESC2CMPL_MAP_5	0xa0
+
+#define EDMA_REG_TXDESC_BA(n)		(0x1000 + (0x1000 * (n)))
+#define EDMA_REG_TXDESC_PROD_IDX(n)	(0x1004 + (0x1000 * (n)))
+#define EDMA_REG_TXDESC_CONS_IDX(n)	(0x1008 + (0x1000 * (n)))
+#define EDMA_REG_TXDESC_RING_SIZE(n)	(0x100c + (0x1000 * (n)))
+#define EDMA_REG_TXDESC_CTRL(n)		(0x1010 + (0x1000 * (n)))
+#define EDMA_REG_TXDESC_BA2(n)		(0x1014 + (0x1000 * (n)))
+
+#define EDMA_REG_RXFILL_BA(n)		(0x29000 + (0x1000 * (n)))
+#define EDMA_REG_RXFILL_PROD_IDX(n)	(0x29004 + (0x1000 * (n)))
+#define EDMA_REG_RXFILL_CONS_IDX(n)	(0x29008 + (0x1000 * (n)))
+#define EDMA_REG_RXFILL_RING_SIZE(n)	(0x2900c + (0x1000 * (n)))
+#define EDMA_REG_RXFILL_BUFFER1_SIZE(n)	(0x29010 + (0x1000 * (n)))
+#define EDMA_REG_RXFILL_FC_THRE(n)	(0x29014 + (0x1000 * (n)))
+#define EDMA_REG_RXFILL_UGT_THRE(n)	(0x29018 + (0x1000 * (n)))
+#define EDMA_REG_RXFILL_RING_EN(n)	(0x2901c + (0x1000 * (n)))
+#define EDMA_REG_RXFILL_DISABLE(n)	(0x29020 + (0x1000 * (n)))
+#define EDMA_REG_RXFILL_DISABLE_DONE(n)	(0x29024 + (0x1000 * (n)))
+#define EDMA_REG_RXFILL_INT_STAT(n)	(0x31000 + (0x1000 * (n)))
+#define EDMA_REG_RXFILL_INT_MASK(n)	(0x31004 + (0x1000 * (n)))
+
+#define EDMA_REG_RXDESC_BA(n)		(0x39000 + (0x1000 * (n)))
+#define EDMA_REG_RXDESC_PROD_IDX(n)	(0x39004 + (0x1000 * (n)))
+#define EDMA_REG_RXDESC_CONS_IDX(n)	(0x39008 + (0x1000 * (n)))
+#define EDMA_REG_RXDESC_RING_SIZE(n)	(0x3900c + (0x1000 * (n)))
+#define EDMA_REG_RXDESC_FC_THRE(n)	(0x39010 + (0x1000 * (n)))
+#define EDMA_REG_RXDESC_UGT_THRE(n)	(0x39014 + (0x1000 * (n)))
+#define EDMA_REG_RXDESC_CTRL(n)		(0x39018 + (0x1000 * (n)))
+#define EDMA_REG_RXDESC_BPC(n)		(0x3901c + (0x1000 * (n)))
+#define EDMA_REG_RXDESC_DISABLE(n)	(0x39020 + (0x1000 * (n)))
+#define EDMA_REG_RXDESC_DISABLE_DONE(n)	(0x39024 + (0x1000 * (n)))
+#define EDMA_REG_RXDESC_PREHEADER_BA(n)	(0x39028 + (0x1000 * (n)))
+#define EDMA_REG_RXDESC_INT_STAT(n)	(0x59000 + (0x1000 * (n)))
+#define EDMA_REG_RXDESC_INT_MASK(n)	(0x59004 + (0x1000 * (n)))
+
+#define EDMA_REG_RX_MOD_TIMER(n)	(0x59008 + (0x1000 * (n)))
+#define EDMA_REG_RX_INT_CTRL(n)		(0x5900c + (0x1000 * (n)))
+
+#define EDMA_REG_TXCMPL_BA(n)		(0x79000 + (0x1000 * (n)))
+#define EDMA_REG_TXCMPL_PROD_IDX(n)	(0x79004 + (0x1000 * (n)))
+#define EDMA_REG_TXCMPL_CONS_IDX(n)	(0x79008 + (0x1000 * (n)))
+#define EDMA_REG_TXCMPL_RING_SIZE(n)	(0x7900c + (0x1000 * (n)))
+#define EDMA_REG_TXCMPL_UGT_THRE(n)	(0x79010 + (0x1000 * (n)))
+#define EDMA_REG_TXCMPL_CTRL(n)		(0x79014 + (0x1000 * (n)))
+#define EDMA_REG_TXCMPL_BPC(n)		(0x79018 + (0x1000 * (n)))
+
+#define EDMA_REG_TX_INT_STAT(n)		(0x99000 + (0x1000 * (n)))
+#define EDMA_REG_TX_INT_MASK(n)		(0x99004 + (0x1000 * (n)))
+#define EDMA_REG_TX_MOD_TIMER(n)	(0x99008 + (0x1000 * (n)))
+#define EDMA_REG_TX_INT_CTRL(n)		(0x9900c + (0x1000 * (n)))
+
+/*
+ * QID to RID Table
+ */
+#define EDMA_QID2RID_TABLE_MEM(q)	(0xb9000 + (0x4 * (q)))
+
+/*
+ * EDMA QID2RID configuration
+ *
+ * TODO: Get port queue ids from dtsi
+ */
+#define EDMA_PORT_QUEUE_START		0
+#define EDMA_PORT_QUEUE_END		3
+#define EDMA_PORT_QUEUE_NUM		((EDMA_PORT_QUEUE_END) - (EDMA_PORT_QUEUE_START) + 1)
+#define EDMA_PORT_QUEUE_PER_CORE	((EDMA_PORT_QUEUE_NUM)/(CONFIG_NR_CPUS))
+#define EDMA_CPU_PORT_MC_QID_MIN	256
+#define EDMA_CPU_PORT_MC_QID_MAX	271
+#define EDMA_QID2RID_NUM_PER_REG	4
+#define EDMA_RSS_HASH_MAX		256
+#define EDMA_PORT_PROFILE_ID		0
+
+#define EDMA_RX_RING_ID_QUEUE0_SHIFT	0
+#define EDMA_RX_RING_ID_QUEUE0_MASK	EDMA_GENMASK(7, 0)
+#define EDMA_RX_RING_ID_QUEUE0_GET(x)	(((x) & EDMA_RX_RING_ID_QUEUE0_MASK) >> EDMA_RX_RING_ID_QUEUE0_SHIFT)
+#define EDMA_RX_RING_ID_QUEUE0_SET(x)	(((x) << EDMA_RX_RING_ID_QUEUE0_SHIFT) & EDMA_RX_RING_ID_QUEUE0_MASK)
+
+#define EDMA_RX_RING_ID_QUEUE1_SHIFT	8
+#define EDMA_RX_RING_ID_QUEUE1_MASK	EDMA_GENMASK(15, 8)
+#define EDMA_RX_RING_ID_QUEUE1_GET(x)	(((x) & EDMA_RX_RING_ID_QUEUE1_MASK) >> EDMA_RX_RING_ID_QUEUE1_SHIFT)
+#define EDMA_RX_RING_ID_QUEUE1_SET(x)	(((x) << EDMA_RX_RING_ID_QUEUE1_SHIFT) & EDMA_RX_RING_ID_QUEUE1_MASK)
+
+#define EDMA_RX_RING_ID_QUEUE2_SHIFT	16
+#define EDMA_RX_RING_ID_QUEUE2_MASK	EDMA_GENMASK(23, 16)
+#define EDMA_RX_RING_ID_QUEUE2_GET(x)	(((x) & EDMA_RX_RING_ID_QUEUE2_MASK) >> EDMA_RX_RING_ID_QUEUE2_SHIFT)
+#define EDMA_RX_RING_ID_QUEUE2_SET(x)	(((x) << EDMA_RX_RING_ID_QUEUE2_SHIFT) & EDMA_RX_RING_ID_QUEUE2_MASK)
+
+#define EDMA_RX_RING_ID_QUEUE3_SHIFT	24
+#define EDMA_RX_RING_ID_QUEUE3_MASK	EDMA_GENMASK(31, 24)
+#define EDMA_RX_RING_ID_QUEUE3_GET(x)	(((x) & EDMA_RX_RING_ID_QUEUE3_MASK) >> EDMA_RX_RING_ID_QUEUE3_SHIFT)
+#define EDMA_RX_RING_ID_QUEUE3_SET(x)	(((x) << EDMA_RX_RING_ID_QUEUE3_SHIFT) & EDMA_RX_RING_ID_QUEUE3_MASK)
+
+/*
+ * PPE Hash seed and mask for configuring RPS hash map table
+ */
+#define PPE_HASH_SEED_DEFAULT		0xabbcdefa
+#define PPE_HASH_MASK			0xfff
+#define PPE_HASH_MIX_V4_SIP		0x13
+#define PPE_HASH_MIX_V4_DIP		0xb
+#define PPE_HASH_MIX_V4_PROTO		0x13
+#define PPE_HASH_MIX_V4_DPORT		0xb
+#define PPE_HASH_MIX_V4_SPORT		0x13
+
+#define PPE_HASH_FIN_INNER_OUTER_0	0x205
+#define PPE_HASH_FIN_INNER_OUTER_1	0x264
+#define PPE_HASH_FIN_INNER_OUTER_2	0x227
+#define PPE_HASH_FIN_INNER_OUTER_3	0x245
+#define PPE_HASH_FIN_INNER_OUTER_4	0x201
+
+#define PPE_HASH_SIPV6_MIX_0		0x13
+#define PPE_HASH_SIPV6_MIX_1		0xb
+#define PPE_HASH_SIPV6_MIX_2		0x13
+#define PPE_HASH_SIPV6_MIX_3		0xb
+#define PPE_HASH_DIPV6_MIX_0		0x13
+#define PPE_HASH_DIPV6_MIX_1		0xb
+#define PPE_HASH_DIPV6_MIX_2		0x13
+#define PPE_HASH_DIPV6_MIX_3		0xb
+
+/*
+ * EDMA_REG_PORT_CTRL register
+ */
+#define EDMA_PORT_PAD_EN			0x1
+#define EDMA_PORT_EDMA_EN			0x2
+
+/*
+ * EDMA_REG_TXQ_CTRL register
+ */
+#define EDMA_TXDESC_PF_THRE_MASK		0xf
+#define EDMA_TXDESC_PF_THRE_SHIFT		0
+#define EDMA_TXCMPL_WB_THRE_MASK		0xf
+#define EDMA_TXCMPL_WB_THRE_SHIFT		4
+#define EDMA_TXDESC_PKT_SRAM_THRE_MASK		0xff
+#define EDMA_TXDESC_PKT_SRAM_THRE_SHIFT		8
+#define EDMA_TXCMPL_WB_TIMER_MASK		0xffff
+#define EDMA_TXCMPL_WB_TIMER_SHIFT		16
+
+/*
+ * EDMA_REG_RXQ_CTRL register
+ */
+#define EDMA_RXFILL_PF_THRE_MASK		0xf
+#define EDMA_RXFILL_PF_THRE_SHIFT		0
+#define EDMA_RXDESC_WB_THRE_MASK		0xf
+#define EDMA_RXDESC_WB_THRE_SHIFT		4
+#define EDMA_RXDESC_WB_TIMER_MASK		0xffff
+#define EDMA_RXDESC_WB_TIMER_SHIFT		16
+
+/*
+ * EDMA_REG_RX_TX_FULL_QID register
+ */
+#define EDMA_RX_DESC_FULL_QID_MASK		0xff
+#define EDMA_RX_DESC_FULL_QID_SHIFT		0
+#define EDMA_TX_CMPL_BUF_FULL_QID_MASK		0xff
+#define EDMA_TX_CMPL_BUF_FULL_QID_SHIFT		8
+#define EDMA_TX_SRAM_FULL_QID_MASK		0x1f
+#define EDMA_TX_SRAM_FULL_QID_SHIFT		16
+
+/*
+ * EDMA_REG_RXQ_FC_THRE reister
+ */
+#define EDMA_RXFILL_FIFO_XOFF_THRE_MASK		0x1f
+#define EDMA_RXFILL_FIFO_XOFF_THRE_SHIFT	0
+#define EDMA_DESC_FIFO_XOFF_THRE_MASK		0x3f
+#define EDMA_DESC_FIFO_XOFF_THRE_SHIFT		16
+
+/*
+ * EDMA_REG_DMAR_CTRL register
+ */
+#define EDMA_DMAR_REQ_PRI_MASK			0x7
+#define EDMA_DMAR_REQ_PRI_SHIFT			0
+#define EDMA_DMAR_BURST_LEN_MASK		0x1
+#define EDMA_DMAR_BURST_LEN_SHIFT		3
+#define EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK	0x1f
+#define EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SHIFT	4
+#define EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK	0x7
+#define EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SHIFT	9
+#define EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK	0x7
+#define EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SHIFT	12
+
+#define EDMA_DMAR_REQ_PRI_SET(x)		(((x) & EDMA_DMAR_REQ_PRI_MASK) \
+						<< EDMA_DMAR_REQ_PRI_SHIFT)
+#define EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SET(x)	(((x) & EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK) \
+						<< EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SHIFT)
+#define EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SET(x)	(((x) & EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK) \
+						<< EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SHIFT)
+#define EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SET(x)	(((x) & EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK) \
+						<< EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SHIFT)
+#define EDMA_DMAR_BURST_LEN_SET(x)		(((x) & EDMA_DMAR_BURST_LEN_MASK) \
+						<< EDMA_DMAR_BURST_LEN_SHIFT)
+
+#define EDMA_BURST_LEN_ENABLE		0
+
+/*
+ * EDMA RXDESC base address mask
+ */
+#define EDMA_RXDESC_BA_MASK			0xffffffff
+
+/*
+ * EDMA RXDESC pre-header base address mask
+ */
+#define EDMA_RXDESC_PREHEADER_BA_MASK		0xffffffff
+
+/*
+ * EDMA_REG_AXIW_CTRL_REG
+ */
+#define EDMA_AXIW_MAX_WR_SIZE_EN		0x400
+
+/*
+ * EDMA DISABLE
+ */
+#define EDMA_DISABLE				0
+
+/*
+ * EDMA_REG_TXDESC_PROD_IDX register
+ */
+#define EDMA_TXDESC_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXDESC_CONS_IDX register
+ */
+#define EDMA_TXDESC_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXDESC_RING_SIZE register
+ */
+#define EDMA_TXDESC_RING_SIZE_MASK		0xffff
+
+/*
+ * EDMA_REG_TXDESC_CTRL register
+ */
+#define EDMA_TXDESC_TX_ENABLE			0x1
+
+#define EDMA_TXDESC_CTRL_TXEN_SHIFT		0
+#define EDMA_TXDESC_CTRL_TXEN_MASK		EDMA_GENMASK(0, 0)
+#define EDMA_TXDESC_CTRL_TXEN_GET(x)		(((x) & EDMA_TXDESC_CTRL_TXEN_MASK) >> EDMA_TXDESC_CTRL_TXEN_SHIFT)
+#define EDMA_TXDESC_CTRL_TXEN_SET(x)		(((x) << EDMA_TXDESC_CTRL_TXEN_SHIFT) & EDMA_TXDESC_CTRL_TXEN_MASK)
+
+#define EDMA_TXDESC_CTRL_FC_GRP_ID_SHIFT	1
+#define EDMA_TXDESC_CTRL_FC_GRP_ID_MASK		EDMA_GENMASK(3, 1)
+#define EDMA_TXDESC_CTRL_FC_GRP_ID_GET(x)	(((x) & EDMA_TXDESC_CTRL_FC_GRP_ID_MASK) >> EDMA_TXDESC_CTRL_FC_GRP_ID_SHIFT)
+#define EDMA_TXDESC_CTRL_FC_GRP_ID_SET(x)	(((x) << EDMA_TXDESC_CTRL_FC_GRP_ID_SHIFT) & EDMA_TXDESC_CTRL_FC_GRP_ID_MASK)
+
+#define EDMA_TXDESC_CTRL_ARB_GRP_ID_SHIFT	4
+#define EDMA_TXDESC_CTRL_ARB_GRP_ID_MASK	EDMA_GENMASK(5, 4)
+#define EDMA_TXDESC_CTRL_ARB_GRP_ID_GET(x)	(((x) & EDMA_TXDESC_CTRL_ARB_GRP_ID_MASK) >> EDMA_TXDESC_CTRL_ARB_GRP_ID_SHIFT)
+#define EDMA_TXDESC_CTRL_ARB_GRP_ID_SET(x)	(((x) << EDMA_TXDESC_CTRL_ARB_GRP_ID_SHIFT) & EDMA_TXDESC_CTRL_ARB_GRP_ID_MASK)
+
+/*
+ * EDMA_REG_TXCMPL_PROD_IDX register
+ */
+#define EDMA_TXCMPL_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXCMPL_CONS_IDX register
+ */
+#define EDMA_TXCMPL_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXCMPL_RING_SIZE register
+ */
+#define EDMA_TXCMPL_RING_SIZE_MASK		0xffff
+
+/*
+ * EDMA_REG_TXCMPL_UGT_THRE register
+ */
+#define EDMA_TXCMPL_LOW_THRE_MASK		0xffff
+#define EDMA_TXCMPL_LOW_THRE_SHIFT		0
+#define EDMA_TXCMPL_FC_THRE_MASK		0x3f
+#define EDMA_TXCMPL_FC_THRE_SHIFT		16
+
+/*
+ * EDMA_REG_TXCMPL_CTRL register
+ */
+#define EDMA_TXCMPL_RET_MODE_BUFF_ADDR		0x0
+#define EDMA_TXCMPL_RET_MODE_OPAQUE		0x1
+
+/*
+ * EDMA_REG_TX_MOD_TIMER register
+ */
+#define EDMA_TX_MOD_TIMER_INIT_MASK		0xffff
+#define EDMA_TX_MOD_TIMER_INIT_SHIFT		0
+
+/*
+ * EDMA_REG_TX_INT_CTRL register
+ */
+#define EDMA_TX_INT_MASK			0x3
+
+/*
+ * EDMA_REG_RXFILL_PROD_IDX register
+ */
+#define EDMA_RXFILL_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXFILL_CONS_IDX register
+ */
+#define EDMA_RXFILL_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXFILL_RING_SIZE register
+ */
+#define EDMA_RXFILL_RING_SIZE_MASK		0xffff
+
+/*
+ * EDMA_REG_RXFILL_FC_THRE register
+ */
+#define EDMA_RXFILL_FC_XON_THRE_MASK		0x7ff
+#define EDMA_RXFILL_FC_XON_THRE_SHIFT		12
+#define EDMA_RXFILL_FC_XOFF_THRE_MASK		0x7ff
+#define EDMA_RXFILL_FC_XOFF_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXFILL_UGT_THRE register
+ */
+#define EDMA_RXFILL_LOW_THRE_MASK		0xffff
+#define EDMA_RXFILL_LOW_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXFILL_RING_EN register
+ */
+#define EDMA_RXFILL_RING_EN			0x1
+
+/*
+ * EDMA_REG_RXFILL_INT_MASK register
+ */
+#define EDMA_RXFILL_INT_MASK			0x1
+
+/*
+ * EDMA_REG_RXDESC_PROD_IDX register
+ */
+#define EDMA_RXDESC_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXDESC_CONS_IDX register
+ */
+#define EDMA_RXDESC_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXDESC_RING_SIZE register
+ */
+#define EDMA_RXDESC_RING_SIZE_MASK		0xffff
+#define EDMA_RXDESC_PL_OFFSET_MASK		0x1ff
+#define EDMA_RXDESC_PL_OFFSET_SHIFT		16
+#define EDMA_RXDESC_PL_DEFAULT_VALUE		0
+
+/*
+ * EDMA_REG_RXDESC_FC_THRE register
+ */
+#define EDMA_RXDESC_FC_XON_THRE_MASK		0x7ff
+#define EDMA_RXDESC_FC_XON_THRE_SHIFT		12
+#define EDMA_RXDESC_FC_XOFF_THRE_MASK		0x7ff
+#define EDMA_RXDESC_FC_XOFF_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXDESC_UGT_THRE register
+ */
+#define EDMA_RXDESC_LOW_THRE_MASK		0xffff
+#define EDMA_RXDESC_LOW_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXDESC_CTRL register
+ */
+#define EDMA_RXDESC_STAG_REMOVE_EN		0x8
+#define EDMA_RXDESC_CTAG_REMOVE_EN		0x4
+#define EDMA_RXDESC_QDISC_EN			0x2
+#define EDMA_RXDESC_RX_EN			0x1
+
+/*
+ * EDMA_REG_TX_INT_MASK register
+ */
+#define EDMA_TX_INT_MASK_PKT_INT		0x1
+#define EDMA_TX_INT_MASK_UGT_INT		0x2
+
+/*
+ * EDMA_REG_RXDESC_INT_STAT register
+ */
+#define EDMA_RXDESC_INT_STAT_PKT_INT		0x1
+#define EDMA_RXDESC_INT_STAT_UGT_INT		0x2
+
+/*
+ * EDMA_REG_RXDESC_INT_MASK register
+ */
+#define EDMA_RXDESC_INT_MASK_PKT_INT		0x1
+#define EDMA_RXDESC_INT_MASK_TIMER_INT_DIS	0x2
+
+#define EDMA_MASK_INT_DISABLE			0x0
+#define EDMA_MASK_INT_CLEAR			0x0
+
+/*
+ * EDMA_REG_RX_MOD_TIMER register
+ */
+#define EDMA_RX_MOD_TIMER_INIT_MASK		0xffff
+#define EDMA_RX_MOD_TIMER_INIT_SHIFT		0
+
+/*
+ * EDMA QID2RID register sizes
+ */
+#define EDMA_QID2RID_DEPTH			0x40
+#define EDMA_QID2RID_QUEUES_PER_ENTRY		8
+
+/*
+ * TXDESC shift values
+ */
+#define EDMA_TXDESC_MORE_SHIFT			31
+#define EDMA_TXDESC_TSO_EN_SHIFT		30
+#define EDMA_TXDESC_PREHEADER_SHIFT		29
+#define EDMA_TXDESC_POOL_ID_SHIFT		24
+#define EDMA_TXDESC_POOL_ID_MASK		0x1f
+#define EDMA_TXDESC_DATA_OFFSET_SHIFT		16
+#define EDMA_TXDESC_DATA_OFFSET_MASK		0xff
+#define EDMA_TXDESC_DATA_LENGTH_SHIFT		0
+#define EDMA_TXDESC_DATA_LENGTH_MASK		0x1ffff
+
+#define EDMA_RING_DMA_MASK			0xffffffff
+
+/*
+ * RXDESC shift values
+ */
+#define EDMA_RXDESC_RX_RXFILL_CNT_MASK		0x000f
+#define EDMA_RXDESC_RX_RXFILL_CNT_SHIFT		16
+
+#define EDMA_RXDESC_PKT_SIZE_MASK		0x3fff
+#define EDMA_RXDESC_PKT_SIZE_SHIFT		0
+
+#define EDMA_RXDESC_RXD_VALID_MASK		0x1
+#define EDMA_RXDESC_RXD_VALID_SHIFT		31
+
+#define EDMA_RXDESC_RING_INT_STATUS_MASK	0x3
+
+#define EDMA_RING_DISABLE			0
+#define EDMA_TXCMPL_RING_INT_STATUS_MASK	0x3
+#define EDMA_TXCMPL_RETMODE_OPAQUE		0x0
+#define EDMA_RXFILL_RING_INT_STATUS_MASK	0x1
+
+/*
+ * TODO tune the timer and threshold values
+ */
+#define EDMA_RXFILL_FIFO_XOFF_THRE		0x3
+#define EDMA_RXFILL_PF_THRE			0x3
+#define EDMA_RXDESC_WB_THRE			0x0
+#define EDMA_RXDESC_WB_TIMER			0x2
+
+#define EDMA_RXDESC_XON_THRE			50
+#define EDMA_RXDESC_XOFF_THRE			30
+#define EDMA_RXDESC_LOW_THRE			0
+#define EDMA_RX_MOD_TIMER_INIT			1000
+#define EDMA_RX_NE_INT_EN			0x2
+
+#define EDMA_TXDESC_PF_THRE			0x3
+#define EDMA_TXCMPL_WB_THRE			0X0
+#define EDMA_TXDESC_PKT_SRAM_THRE		0x20
+#define EDMA_TXCMPL_WB_TIMER			0x2
+
+#define EDMA_TX_MOD_TIMER			150
+
+#define EDMA_TX_INITIAL_PROD_IDX		0x0
+#define EDMA_TX_NE_INT_EN			0x2
+
+/*
+ * EDMA misc error mask
+ */
+#define EDMA_MISC_AXI_RD_ERR_MASK		0x1
+#define EDMA_MISC_AXI_WR_ERR_MASK		0x2
+#define EDMA_MISC_RX_DESC_FIFO_FULL_MASK	0x4
+#define EDMA_MISC_RX_ERR_BUF_SIZE_MASK		0x8
+#define EDMA_MISC_TX_SRAM_FULL_MASK		0x10
+#define EDMA_MISC_TX_CMPL_BUF_FULL_MASK		0x20
+
+#define EDMA_MISC_DATA_LEN_ERR_MASK		0x40
+#define EDMA_MISC_TX_TIMEOUT_MASK		0x80
+
+/*
+ * EDMA txdesc2cmpl map
+ */
+#define EDMA_TXDESC2CMPL_MAP_TXDESC_MASK	0x1F
+
+/*
+ * EDMA rxdesc2fill map
+ */
+#define EDMA_RXDESC2FILL_MAP_RXDESC_MASK	0x7
+
+#endif	/* __EDMA_REGS__ */
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_rx.c b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_rx.c
new file mode 100644
index 0000000..4c3cc71
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_rx.c
@@ -0,0 +1,705 @@
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <asm/cacheflush.h>
+#include <linux/version.h>
+#include <linux/netdevice.h>
+#include "edma.h"
+#include "edma_debug.h"
+#include "edma_regs.h"
+#include "nss_dp_dev.h"
+
+/*
+ * edma_rx_alloc_buffer()
+ *	Alloc Rx buffers for one RxFill ring
+ */
+int edma_rx_alloc_buffer(struct edma_rxfill_ring *rxfill_ring, int alloc_count)
+{
+	struct edma_rxfill_desc *rxfill_desc;
+	struct edma_rx_fill_stats *rxfill_stats = &rxfill_ring->rx_fill_stats;
+	uint16_t prod_idx, start_idx;
+	uint16_t num_alloc = 0;
+	uint32_t rx_alloc_size = rxfill_ring->alloc_size;
+	uint32_t buf_len = rxfill_ring->buf_len;
+	bool page_mode = rxfill_ring->page_mode;
+
+	/*
+	 * Get RXFILL ring producer index
+	 */
+	prod_idx = rxfill_ring->prod_idx;
+	start_idx = prod_idx;
+
+	while (likely(alloc_count--)) {
+		void *page_addr = NULL;
+		struct page *pg;
+		struct sk_buff *skb;
+		dma_addr_t buff_addr;
+
+		/*
+		 * Allocate buffer
+		 */
+		skb = dev_alloc_skb(rx_alloc_size);
+		if (unlikely(!skb)) {
+			u64_stats_update_begin(&rxfill_stats->syncp);
+			++rxfill_stats->alloc_failed;
+			u64_stats_update_end(&rxfill_stats->syncp);
+			break;
+		}
+
+		/*
+		 * Reserve headroom
+		 */
+		skb_reserve(skb, EDMA_RX_SKB_HEADROOM + NET_IP_ALIGN);
+
+		/*
+		 * Map Rx buffer for DMA
+		 */
+		if (likely(!page_mode)) {
+			buff_addr = (dma_addr_t)virt_to_phys(skb->data);
+		} else {
+			pg = alloc_page(GFP_ATOMIC);
+			if (unlikely(!pg)) {
+				u64_stats_update_begin(&rxfill_stats->syncp);
+				++rxfill_stats->page_alloc_failed;
+				u64_stats_update_end(&rxfill_stats->syncp);
+				dev_kfree_skb_any(skb);
+				edma_debug("edma_gbl_ctx:%px Unable to allocate page", &edma_gbl_ctx);
+				break;
+			}
+
+			/*
+			 * Get virtual address of allocated page
+			 */
+			page_addr = page_address(pg);
+			buff_addr = (dma_addr_t)virt_to_phys(page_addr);
+			skb_fill_page_desc(skb, 0, pg, 0, PAGE_SIZE);
+			dmac_inv_range_no_dsb(page_addr, (page_addr + PAGE_SIZE));
+		}
+
+		/*
+		 * Get RXFILL descriptor
+		 */
+		rxfill_desc = EDMA_RXFILL_DESC(rxfill_ring, prod_idx);
+
+		EDMA_RXFILL_BUFFER_ADDR_SET(rxfill_desc, buff_addr);
+
+		/*
+		 * Store skb in opaque
+		 */
+		EDMA_RXFILL_OPAQUE_LO_SET(rxfill_desc, skb);
+#ifdef __LP64__
+		EDMA_RXFILL_OPAQUE_HI_SET(rxfill_desc, skb);
+#endif
+
+		/*
+		 * Save buffer size in RXFILL descriptor
+		 */
+		EDMA_RXFILL_PACKET_LEN_SET(
+			rxfill_desc,
+			cpu_to_le32((uint32_t)
+			(buf_len)
+			& EDMA_RXFILL_BUF_SIZE_MASK));
+
+		/*
+		 * Invalidate skb->data
+		 */
+		dmac_inv_range_no_dsb((void *)skb->data,
+				(void *)(skb->data + rx_alloc_size -
+					EDMA_RX_SKB_HEADROOM -
+					NET_IP_ALIGN));
+		prod_idx = (prod_idx + 1) & EDMA_RX_RING_SIZE_MASK;
+		num_alloc++;
+	}
+
+	if (likely(num_alloc)) {
+		uint16_t end_idx =
+			(start_idx + num_alloc) & EDMA_RX_RING_SIZE_MASK;
+
+		rxfill_desc = EDMA_RXFILL_DESC(rxfill_ring, start_idx);
+
+		/*
+		 * Write-back all the cached descriptors
+		 * that are processed.
+		 */
+		if (end_idx > start_idx) {
+			dmac_clean_range_no_dsb((void *)rxfill_desc,
+					(void *)(rxfill_desc + num_alloc));
+		} else {
+			dmac_clean_range_no_dsb((void *)rxfill_ring->desc,
+					(void *)(rxfill_ring->desc + end_idx));
+			dmac_clean_range_no_dsb((void *)rxfill_desc,
+					(void *)(rxfill_ring->desc +
+							EDMA_RX_RING_SIZE));
+		}
+
+		/*
+		 * Make sure the information written to the descriptors
+		 * is updated before writing to the hardware.
+		 */
+		dsb(st);
+
+		edma_reg_write(EDMA_REG_RXFILL_PROD_IDX(rxfill_ring->ring_id),
+								prod_idx);
+		rxfill_ring->prod_idx = prod_idx;
+	}
+
+	return num_alloc;
+}
+
+/*
+ * edma_rx_checksum_verify()
+ *	Update hw checksum status into skb
+ */
+static inline void edma_rx_checksum_verify(struct edma_rxdesc_desc *rxdesc_desc,
+							struct sk_buff* skb)
+{
+	uint8_t pid = EDMA_RXDESC_PID_GET(rxdesc_desc);
+
+	skb_checksum_none_assert(skb);
+
+	if (likely(EDMA_RX_PID_IS_IPV4(pid))) {
+		if (likely(EDMA_RXDESC_L3CSUM_STATUS_GET(rxdesc_desc))
+			&& likely(EDMA_RXDESC_L4CSUM_STATUS_GET(rxdesc_desc))) {
+			skb->ip_summed = CHECKSUM_UNNECESSARY;
+		}
+	} else if (likely(EDMA_RX_PID_IS_IPV6(pid))) {
+		if (likely(EDMA_RXDESC_L4CSUM_STATUS_GET(rxdesc_desc))) {
+			skb->ip_summed = CHECKSUM_UNNECESSARY;
+		}
+	}
+}
+
+/*
+ * edma_rx_handle_scatter_frames()
+ *	Handle scattered packets in Rx direction
+ *
+ * This function should free the SKB in case of failure.
+ */
+static void edma_rx_handle_scatter_frames(struct edma_gbl_ctx *egc,
+		struct edma_rxdesc_ring *rxdesc_ring,
+		struct edma_rxdesc_desc *rxdesc_desc,
+		struct sk_buff *skb)
+{
+	struct nss_dp_dev *dp_dev;
+	struct edma_pcpu_stats *pcpu_stats;
+	struct edma_rx_stats *rx_stats;
+	struct sk_buff *rxdesc_ring_head;
+	struct net_device *dev;
+	uint32_t pkt_length;
+	skb_frag_t *frag = NULL;
+	bool page_mode = rxdesc_ring->rxfill->page_mode;
+
+	/*
+	 * Get packet length
+	 */
+	pkt_length = EDMA_RXDESC_PACKET_LEN_GET(rxdesc_desc);
+	edma_debug("edma_gbl_ctx:%px skb:%px fragment pkt_length:%u\n", egc, skb, pkt_length);
+
+	/*
+	 * For fraglist case
+	 */
+	if (likely(!page_mode)) {
+
+		/*
+		 * Invalidate the buffer received from the HW
+		 */
+		dmac_inv_range((void *)skb->data,
+				(void *)(skb->data + pkt_length));
+
+		if (!(rxdesc_ring->head)) {
+			skb_put(skb, pkt_length);
+			rxdesc_ring->head = skb;
+			rxdesc_ring->last = NULL;
+			return;
+		}
+
+		/*
+		 * If head is present and got next desc.
+		 * Append it to the fraglist of head if this is second frame
+		 * If not second frame append to tail
+		 */
+		skb_put(skb, pkt_length);
+		if (!skb_has_frag_list(rxdesc_ring->head)) {
+			skb_shinfo(rxdesc_ring->head)->frag_list = skb;
+		} else {
+			rxdesc_ring->last->next = skb;
+		}
+
+		rxdesc_ring->last = skb;
+		rxdesc_ring->last->next = NULL;
+		rxdesc_ring->head->len += pkt_length;
+		rxdesc_ring->head->data_len += pkt_length;
+		rxdesc_ring->head->truesize += skb->truesize;
+
+		goto process_last_scatter;
+	}
+
+	/*
+	 * Manage fragments for page mode
+	 */
+	frag = &skb_shinfo(skb)->frags[0];
+	dmac_inv_range((void *)skb_frag_page(frag), (void *)(skb_frag_page(frag) + pkt_length));
+
+	if (!(rxdesc_ring->head)) {
+		skb->len = pkt_length;
+		skb->data_len = pkt_length;
+		skb->truesize = SKB_TRUESIZE(PAGE_SIZE);
+		rxdesc_ring->head = skb;
+		rxdesc_ring->last = NULL;
+		return;
+	}
+
+	/*
+	 * Append current frag at correct index as nr_frag of parent
+	 */
+	skb_add_rx_frag(rxdesc_ring->head, skb_shinfo(rxdesc_ring->head)->nr_frags,
+			skb_frag_page(frag), 0, pkt_length, PAGE_SIZE);
+	skb_shinfo(skb)->nr_frags = 0;
+
+	/*
+	 * Free the SKB after we have appended its frag page to the head skb
+	 */
+	dev_kfree_skb_any(skb);
+
+process_last_scatter:
+
+	/*
+	 * If there are more segments for this packet,
+	 * then we have nothing to do. Otherwise process
+	 * last segment and send packet to stack
+	 */
+	rxdesc_ring_head = rxdesc_ring->head;
+	dev = rxdesc_ring_head->dev;
+
+	if (EDMA_RXDESC_MORE_BIT_GET(rxdesc_desc)) {
+		return;
+	}
+
+	/*
+	 * Check Rx checksum offload status.
+	 */
+	if (likely(dev->features & NETIF_F_RXCSUM)) {
+		edma_rx_checksum_verify(rxdesc_desc, rxdesc_ring_head);
+	}
+
+	/*
+	 * Get stats for the netdevice
+	 */
+	dp_dev = netdev_priv(dev);
+	pcpu_stats = &dp_dev->dp_info.pcpu_stats;
+	rx_stats = this_cpu_ptr(pcpu_stats->rx_stats);
+
+	if (unlikely(page_mode)) {
+		if (unlikely(!pskb_may_pull(rxdesc_ring_head, ETH_HLEN))) {
+			/*
+			 * Discard the SKB that we have been building,
+			 * in addition to the SKB linked to current descriptor.
+			 */
+			dev_kfree_skb_any(rxdesc_ring_head);
+			rxdesc_ring->head = NULL;
+			rxdesc_ring->last = NULL;
+
+			u64_stats_update_begin(&rx_stats->syncp);
+			rx_stats->rx_nr_frag_headroom_err++;
+			u64_stats_update_end(&rx_stats->syncp);
+
+			return;
+		}
+	}
+
+	/*
+	 * TODO: Do a batched update of the stats per netdevice.
+	 */
+	u64_stats_update_begin(&rx_stats->syncp);
+	rx_stats->rx_pkts++;
+	rx_stats->rx_bytes += rxdesc_ring_head->len;
+	rx_stats->rx_nr_frag_pkts += (uint64_t)page_mode;
+	rx_stats->rx_fraglist_pkts += (uint64_t)(!page_mode);
+	u64_stats_update_end(&rx_stats->syncp);
+
+	rxdesc_ring_head->protocol = eth_type_trans(rxdesc_ring_head, dev);
+
+	edma_debug("edma_gbl_ctx:%px skb:%px Jumbo pkt_length:%u\n", egc, rxdesc_ring_head, rxdesc_ring_head->len);
+
+	/*
+	 * Send packet up the stack
+	 */
+#if defined(NSS_DP_ENABLE_NAPI_GRO)
+	napi_gro_receive(&rxdesc_ring->napi, rxdesc_ring_head);
+#else
+	netif_receive_skb(rxdesc_ring_head);
+#endif
+
+	rxdesc_ring->head = NULL;
+	rxdesc_ring->last = NULL;
+}
+
+/*
+ * edma_rx_handle_linear_packets()
+ *	Handle linear packets
+ */
+static inline bool edma_rx_handle_linear_packets(struct edma_gbl_ctx *egc,
+		struct edma_rxdesc_ring *rxdesc_ring,
+		struct edma_rxdesc_desc *rxdesc_desc,
+		struct sk_buff *skb)
+{
+	struct nss_dp_dev *dp_dev;
+	struct edma_pcpu_stats *pcpu_stats;
+	struct edma_rx_stats *rx_stats;
+	uint32_t pkt_length;
+	skb_frag_t *frag = NULL;
+	bool page_mode = rxdesc_ring->rxfill->page_mode;
+
+	/*
+	 * Get stats for the netdevice
+	 */
+	dp_dev = netdev_priv(skb->dev);
+	pcpu_stats = &dp_dev->dp_info.pcpu_stats;
+	rx_stats = this_cpu_ptr(pcpu_stats->rx_stats);
+
+	/*
+	 * Check Rx checksum offload status.
+	 */
+	if (likely(skb->dev->features & NETIF_F_RXCSUM)) {
+		edma_rx_checksum_verify(rxdesc_desc, skb);
+	}
+
+	/*
+	 * Get packet length
+	 */
+	pkt_length = EDMA_RXDESC_PACKET_LEN_GET(rxdesc_desc);
+
+	if (likely(!page_mode)) {
+
+		/*
+		 * Invalidate the buffer received from the HW
+		 */
+		dmac_inv_range((void *)skb->data,
+				(void *)(skb->data + pkt_length));
+
+		skb_put(skb, pkt_length);
+		skb->protocol = eth_type_trans(skb, skb->dev);
+		goto send_to_stack;
+	}
+
+	/*
+	 * Handle linear packet in page mode
+	 */
+	frag = &skb_shinfo(skb)->frags[0];
+	dmac_inv_range((void *)skb_frag_page(frag),
+			(void *)(skb_frag_page(frag) + pkt_length));
+	skb_add_rx_frag(skb, 0, skb_frag_page(frag), 0, pkt_length, PAGE_SIZE);
+
+	/*
+	 * Pull ethernet header into SKB data area for header processing
+	 */
+	if (unlikely(!pskb_may_pull(skb, ETH_HLEN))) {
+		u64_stats_update_begin(&rx_stats->syncp);
+		rx_stats->rx_nr_frag_headroom_err++;
+		u64_stats_update_end(&rx_stats->syncp);
+		return false;
+	}
+
+	skb->protocol = eth_type_trans(skb, skb->dev);
+
+send_to_stack:
+
+	/*
+	 * TODO: Do a batched update of the stats per netdevice.
+	 */
+	u64_stats_update_begin(&rx_stats->syncp);
+	rx_stats->rx_pkts++;
+	rx_stats->rx_bytes += pkt_length;
+	rx_stats->rx_nr_frag_pkts += (uint64_t)page_mode;
+	u64_stats_update_end(&rx_stats->syncp);
+
+	edma_debug("edma_gbl_ctx:%px, skb:%px pkt_length:%u\n",
+			egc, skb, skb->len);
+
+	/*
+	 * Send packet upto network stack
+	 */
+#if defined(NSS_DP_ENABLE_NAPI_GRO)
+	napi_gro_receive(&rxdesc_ring->napi, skb);
+#else
+	netif_receive_skb(skb);
+#endif
+
+	return true;
+}
+
+/*
+ * edma_rx_reap()
+ *	Reap Rx descriptors
+ */
+static uint32_t edma_rx_reap(struct edma_gbl_ctx *egc, int budget,
+				struct edma_rxdesc_ring *rxdesc_ring)
+{
+	struct edma_rxdesc_desc *rxdesc_desc;
+	struct edma_rx_desc_stats *rxdesc_stats = &rxdesc_ring->rx_desc_stats;
+	uint32_t work_to_do, work_done = 0;
+	uint32_t work_leftover;
+	uint16_t prod_idx, cons_idx, end_idx;
+
+	/*
+	 * Get Rx ring producer and consumer indices
+	 */
+	cons_idx = rxdesc_ring->cons_idx;
+
+	if (likely(rxdesc_ring->work_leftover > EDMA_RX_MAX_PROCESS)) {
+		work_to_do = rxdesc_ring->work_leftover;
+	} else {
+		prod_idx =
+			edma_reg_read(EDMA_REG_RXDESC_PROD_IDX(rxdesc_ring->ring_id)) &
+			EDMA_RXDESC_PROD_IDX_MASK;
+		work_to_do = EDMA_DESC_AVAIL_COUNT(prod_idx,
+				cons_idx, EDMA_RX_RING_SIZE);
+		rxdesc_ring->work_leftover = work_to_do;
+	}
+
+	if (work_to_do > budget) {
+		work_to_do = budget;
+	}
+	rxdesc_ring->work_leftover -= work_to_do;
+
+	end_idx = (cons_idx + work_to_do) & EDMA_RX_RING_SIZE_MASK;
+
+	rxdesc_desc = EDMA_RXDESC_PRI_DESC(rxdesc_ring, cons_idx);
+
+	/*
+	 * Invalidate all the cached descriptors
+	 * that'll be processed.
+	 */
+	if (end_idx > cons_idx) {
+		dmac_inv_range_no_dsb((void *)rxdesc_desc,
+			(void *)(rxdesc_desc + work_to_do));
+	} else {
+		dmac_inv_range_no_dsb((void *)rxdesc_ring->pdesc,
+			(void *)(rxdesc_ring->pdesc + end_idx));
+		dmac_inv_range_no_dsb((void *)rxdesc_desc,
+			(void *)(rxdesc_ring->pdesc + EDMA_RX_RING_SIZE));
+	}
+
+	dsb(st);
+
+	work_leftover = work_to_do & (EDMA_RX_MAX_PROCESS - 1);
+	while (likely(work_to_do--)) {
+		struct net_device *ndev;
+		struct sk_buff *skb;
+		uint32_t src_port_num;
+
+		/*
+		 * Get opaque from RXDESC
+		 */
+		skb = (struct sk_buff *)EDMA_RXDESC_OPAQUE_GET(rxdesc_desc);
+
+		/*
+		 * Handle linear packets or initial segments first
+		 */
+		if (likely(!(rxdesc_ring->head))) {
+			/*
+			 * Check src_info
+			 */
+			src_port_num = EDMA_RXDESC_SRC_INFO_GET(rxdesc_desc);
+			if (likely((src_port_num & EDMA_RXDESC_SRCINFO_TYPE_MASK)
+					== EDMA_RXDESC_SRCINFO_TYPE_PORTID)) {
+				src_port_num &= EDMA_RXDESC_PORTNUM_BITS;
+			} else {
+				edma_warn("Src_info_type:0x%x. Drop skb:%px\n",
+						(src_port_num &
+						EDMA_RXDESC_SRCINFO_TYPE_MASK),
+						skb);
+				u64_stats_update_begin(&rxdesc_stats->syncp);
+				++rxdesc_stats->src_port_inval_type;
+				u64_stats_update_end(&rxdesc_stats->syncp);
+				dev_kfree_skb_any(skb);
+				goto next_rx_desc;
+			}
+
+			if (unlikely((src_port_num < NSS_DP_START_IFNUM) ||
+					(src_port_num > NSS_DP_HAL_MAX_PORTS))) {
+				edma_warn("Port number error :%d. \
+						Drop skb:%px\n",
+						src_port_num, skb);
+				u64_stats_update_begin(&rxdesc_stats->syncp);
+				++rxdesc_stats->src_port_inval;
+				u64_stats_update_end(&rxdesc_stats->syncp);
+				dev_kfree_skb_any(skb);
+				goto next_rx_desc;
+			}
+
+			/*
+			 * Get netdev for this port using the source port
+			 * number as index into the netdev array. We need to
+			 * subtract one since the indices start form '0' and
+			 * port numbers start from '1'.
+			 */
+			ndev = egc->netdev_arr[src_port_num - 1];
+			if (unlikely(!ndev)) {
+				edma_warn("Netdev Null src_info_type:0x%x. \
+						Drop skb:%px\n",
+						src_port_num, skb);
+				u64_stats_update_begin(&rxdesc_stats->syncp);
+				++rxdesc_stats->src_port_inval_netdev;
+				u64_stats_update_end(&rxdesc_stats->syncp);
+				dev_kfree_skb_any(skb);
+				goto next_rx_desc;
+			}
+
+			/*
+			 * Update skb fields for head skb
+			 */
+			skb->dev = ndev;
+			skb->skb_iif = ndev->ifindex;
+
+#ifdef CONFIG_NET_SWITCHDEV
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+			skb->offload_fwd_mark = ndev->offload_fwd_mark;
+#else
+			/*
+			 * TODO: Implement ndo_get_devlink_port()
+			 */
+			skb->offload_fwd_mark = 0;
+#endif
+			edma_debug("edma_gbl_ctx:%px skb:%px ring_idx:%u proto:0x%x mark:%u\n",
+					egc, skb, cons_idx, skb->protocol,
+					skb->offload_fwd_mark);
+#else
+			edma_debug("edma_gbl_ctx:%px skb:%px ring_idx:%u proto:0x%x\n",
+					egc, skb, cons_idx,  skb->protocol);
+#endif
+
+			/*
+			 * Handle linear packets
+			 */
+			if (likely(!EDMA_RXDESC_MORE_BIT_GET(rxdesc_desc))) {
+				if (unlikely(!edma_rx_handle_linear_packets(egc, rxdesc_ring, rxdesc_desc, skb))) {
+					dev_kfree_skb_any(skb);
+				}
+
+				goto next_rx_desc;
+			}
+		}
+
+		/*
+		 * Handle scatter frame processing for first/middle/last segments
+		 */
+		edma_rx_handle_scatter_frames(egc, rxdesc_ring, rxdesc_desc, skb);
+
+next_rx_desc:
+		/*
+		 * Update consumer index
+		 */
+		cons_idx = (cons_idx + 1) & EDMA_RX_RING_SIZE_MASK;
+
+		rxdesc_desc = EDMA_RXDESC_PRI_DESC(rxdesc_ring, cons_idx);
+
+		/*
+		 * Update work done
+		 */
+		work_done++;
+
+		/*
+		 * Check if we can refill EDMA_RX_MAX_PROCESS worth buffers,
+		 * if yes, refill and update index before continuing.
+		 */
+		if (unlikely(!(work_done & (EDMA_RX_MAX_PROCESS - 1)))) {
+			edma_reg_write(
+					EDMA_REG_RXDESC_CONS_IDX(rxdesc_ring->ring_id),
+					cons_idx);
+			rxdesc_ring->cons_idx = cons_idx;
+			edma_rx_alloc_buffer(rxdesc_ring->rxfill,
+					EDMA_RX_MAX_PROCESS);
+		}
+	}
+
+	/*
+	 * Check if we need to refill and update
+	 * index for any buffers before exit.
+	 */
+	if (unlikely(work_leftover)) {
+		edma_reg_write(EDMA_REG_RXDESC_CONS_IDX(rxdesc_ring->ring_id),
+				cons_idx);
+		rxdesc_ring->cons_idx = cons_idx;
+		edma_rx_alloc_buffer(rxdesc_ring->rxfill, work_leftover);
+	}
+
+	return work_done;
+}
+
+/*
+ * edma_rx_napi_poll()
+ *	EDMA RX NAPI handler
+ */
+int edma_rx_napi_poll(struct napi_struct *napi, int budget)
+{
+	struct edma_rxdesc_ring *rxdesc_ring = (struct edma_rxdesc_ring *)napi;
+	struct edma_gbl_ctx *egc = &edma_gbl_ctx;
+	int32_t work_done = 0;
+	uint32_t status;
+
+	do {
+		work_done += edma_rx_reap(egc, budget - work_done, rxdesc_ring);
+		if (likely(work_done >= budget)) {
+			return work_done;
+		}
+
+		/*
+		 * Check if there are more packets to process
+		 */
+		status = EDMA_RXDESC_RING_INT_STATUS_MASK &
+			edma_reg_read(
+				EDMA_REG_RXDESC_INT_STAT(rxdesc_ring->ring_id));
+	} while (likely(status));
+
+	/*
+	 * No more packets to process. Finish NAPI processing.
+	 */
+	napi_complete(napi);
+
+	/*
+	 * Set RXDESC ring interrupt mask
+	 */
+	edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->ring_id),
+						egc->rxdesc_intr_mask);
+
+	return work_done;
+}
+
+/*
+ * edma_rx_handle_irq()
+ *	Process RX IRQ and schedule napi
+ */
+irqreturn_t edma_rx_handle_irq(int irq, void *ctx)
+{
+	struct edma_rxdesc_ring *rxdesc_ring = (struct edma_rxdesc_ring *)ctx;
+
+	edma_debug("irq: irq=%d rxdesc_ring_id=%u\n", irq, rxdesc_ring->ring_id);
+
+	if (likely(napi_schedule_prep(&rxdesc_ring->napi))) {
+
+		/*
+		 * Disable RxDesc interrupt
+		 */
+		edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->ring_id),
+							EDMA_MASK_INT_DISABLE);
+		__napi_schedule(&rxdesc_ring->napi);
+	}
+
+	return IRQ_HANDLED;
+}
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_rx.h b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_rx.h
new file mode 100644
index 0000000..61a1aae
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_rx.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __EDMA_RX_H__
+#define __EDMA_RX_H__
+
+#define EDMA_RXFILL_RING_PER_CORE_MAX	1
+#define EDMA_RXDESC_RING_PER_CORE_MAX	1
+
+#define EDMA_RX_MAX_PROCESS		32	/* Max Rx processing without
+						   replenishing RxFill ring */
+#define EDMA_RX_SKB_HEADROOM		128
+
+#define EDMA_GET_DESC(R, i, type)	(&(((type *)((R)->desc))[(i)]))
+#define EDMA_GET_PDESC(R, i, type)	(&(((type *)((R)->pdesc))[(i)]))
+#define EDMA_GET_SDESC(R, i, type)	(&(((type *)((R)->sdesc))[(i)]))
+#define EDMA_RXFILL_DESC(R, i)		EDMA_GET_DESC(R, i, struct edma_rxfill_desc)
+#define EDMA_RXDESC_PRI_DESC(R, i)	EDMA_GET_PDESC(R, i, struct edma_rxdesc_desc)
+#define EDMA_RXDESC_SEC_DESC(R, i)	EDMA_GET_SDESC(R, i, struct edma_rxdesc_sec_desc)
+
+#define EDMA_RX_RING_SIZE		256
+#define EDMA_RX_RING_SIZE_MASK		(EDMA_RX_RING_SIZE - 1)
+#define EDMA_RX_RING_ID_MASK		0x1F
+#define EDMA_MAX_RXDESC_RINGS		24	/* Max RxDesc rings */
+#define EDMA_MAX_RXFILL_RINGS		8	/* Max RxFill rings */
+#define EDMA_RX_MAX_PRIORITY_LEVEL	1
+
+#define EDMA_RX_PID_IPV4_MAX		0x3
+#define EDMA_RX_PID_IPV6		0x4
+#define EDMA_RX_PID_IS_IPV4(pid)	(!((pid) & (~EDMA_RX_PID_IPV4_MAX)))
+#define EDMA_RX_PID_IS_IPV6(pid)	(!(!((pid) & EDMA_RX_PID_IPV6)))
+
+#define EDMA_RXDESC_BUFFER_ADDR_GET(desc)	((uint32_t)((desc)->word0))
+#define EDMA_RXDESC_OPAQUE_GET(desc)		((uintptr_t)((uint64_t)((desc)->word2) | \
+						((uint64_t)((desc)->word3) << 0x20)))
+#define EDMA_RXDESC_SRCINFO_TYPE_PORTID		0x2000
+#define EDMA_RXDESC_SRCINFO_TYPE_SHIFT		8
+#define EDMA_RXDESC_SRCINFO_TYPE_MASK		0xF000
+#define EDMA_RXDESC_L3CSUM_STATUS_MASK		0x2000
+#define EDMA_RXDESC_L4CSUM_STATUS_MASK		0x1000
+#define EDMA_RXDESC_PORTNUM_BITS		0x0FFF
+
+#define EDMA_RXDESC_PACKET_LEN_MASK		0x3FFFF
+#define EDMA_RXDESC_PACKET_LEN_GET(desc)	(((desc)->word5) & \
+						EDMA_RXDESC_PACKET_LEN_MASK)
+#define EDMA_RXDESC_MORE_BIT_MASK		0x40000000
+#define EDMA_RXDESC_MORE_BIT_GET(desc)		(((desc)->word1) & \
+						EDMA_RXDESC_MORE_BIT_MASK)
+#define EDMA_RXDESC_SRC_INFO_GET(desc)		(((desc)->word4) & 0xFFFF)
+#define EDMA_RXDESC_L3CSUM_STATUS_GET(desc)	(((desc)->word6) & \
+						EDMA_RXDESC_L3CSUM_STATUS_MASK)
+#define EDMA_RXDESC_L4CSUM_STATUS_GET(desc)	(((desc)->word6) & \
+						EDMA_RXDESC_L4CSUM_STATUS_MASK)
+#define EDMA_RXDESC_SERVICE_CODE_GET(desc)	(((desc)->word7) & 0x1FF)
+#define EDMA_RXDESC_PID_GET(desc)		(((desc)->word7) & 0x7000) >> 0x0C
+
+#define EDMA_RXFILL_BUF_SIZE_MASK		0xFFFF
+#define EDMA_RXFILL_BUF_SIZE_SHIFT		16
+#define EDMA_RXFILL_OPAQUE_LO_SET(desc, ptr)	(((desc)->word2) = (uint32_t)(uintptr_t)(ptr))
+#define EDMA_RXFILL_OPAQUE_HI_SET(desc, ptr)	(((desc)->word3) = (uint32_t)((uint64_t)(ptr) >> 0x20))
+#define EDMA_RXFILL_OPAQUE_GET(desc)		((uintptr_t)((uint64_t)((desc)->word2) | \
+						((uint64_t)((desc)->word3) << 0x20)))
+#define EDMA_RXFILL_PACKET_LEN_SET(desc, len)	(((desc)->word1) = (uint32_t)\
+						((((uint32_t)len) << \
+						EDMA_RXFILL_BUF_SIZE_SHIFT) & 0xFFFF0000))
+#define EDMA_RXFILL_BUFFER_ADDR_SET(desc, addr)	(((desc)->word0) = (uint32_t)(addr))
+
+/*
+ * edma_rx_stats
+ *	EDMA RX per cpu stats
+ */
+struct edma_rx_stats {
+	uint64_t rx_pkts;
+	uint64_t rx_bytes;
+	uint64_t rx_drops;
+	uint64_t rx_nr_frag_pkts;
+	uint64_t rx_fraglist_pkts;
+	uint64_t rx_nr_frag_headroom_err;
+	struct u64_stats_sync syncp;
+};
+
+/*
+ * edma_rx_desc_stats
+ *	RX descriptor ring stats data structure
+ */
+struct edma_rx_desc_stats {
+	uint64_t src_port_inval;		/* Invalid source port number */
+	uint64_t src_port_inval_type;		/* Source type is not PORT ID */
+	uint64_t src_port_inval_netdev;		/* Invalid net device for the source port */
+	struct u64_stats_sync syncp;		/* Synchronization pointer */
+};
+
+/*
+ * edma_rx_fill_stats
+ *	Rx fill descriptor ring stats data structure
+ */
+struct edma_rx_fill_stats {
+	uint64_t alloc_failed;			/* Buffer allocation failure count */
+	uint64_t page_alloc_failed;		/* Page allocation failure count for page mode */
+	struct u64_stats_sync syncp;		/* Synchronization pointer */
+};
+
+/*
+ * Rx descriptor
+ */
+struct edma_rxdesc_desc {
+	uint32_t word0;		/* Contains buffer address */
+	uint32_t word1;		/* Contains more bit, priority bit, service code */
+	uint32_t word2;		/* Contains opaque */
+	uint32_t word3;		/* Contains opaque high bits */
+	uint32_t word4;		/* Contains destination and source information */
+	uint32_t word5;		/* Contains WiFi QoS, data length */
+	uint32_t word6;		/* Contains hash value, check sum status */
+	uint32_t word7;		/* Contains DSCP, packet offsets */
+};
+
+/*
+ * Rx secondary descriptor
+ */
+struct edma_rxdesc_sec_desc {
+	uint32_t word0;		/* Contains timestamp */
+	uint32_t word1;		/* Contains secondary checksum status */
+	uint32_t word2;		/* Contains QoS tag */
+	uint32_t word3;		/* Contains flow index details */
+	uint32_t word4;		/* Contains secondary packet offsets */
+	uint32_t word5;		/* Contains multicast bit, checksum */
+	uint32_t word6;		/* Contains SVLAN, CVLAN */
+	uint32_t word7;		/* Contains secondary SVLAN, CVLAN */
+};
+
+/*
+ * RxFill descriptor
+ */
+struct edma_rxfill_desc {
+	uint32_t word0;		/* Contains buffer address */
+	uint32_t word1;		/* Contains buffer size */
+	uint32_t word2;		/* Contains opaque */
+	uint32_t word3;		/* Contains opaque high bits */
+};
+
+/*
+ * RxFill ring
+ */
+struct edma_rxfill_ring {
+	uint32_t ring_id;		/* RXFILL ring number */
+	uint32_t count;			/* number of descriptors in the ring */
+	uint32_t prod_idx;		/* Ring producer index */
+	uint32_t alloc_size;		/* Buffer size to allocate */
+	struct edma_rxfill_desc *desc;	/* descriptor ring virtual address */
+	dma_addr_t dma;			/* descriptor ring physical address */
+	uint32_t buf_len;		/* Buffer length for rxfill descriptor */
+	bool page_mode;			/* Page mode for Rx processing */
+	struct edma_rx_fill_stats rx_fill_stats;
+					/* Rx fill ring statistics */
+};
+
+/*
+ * RxDesc ring
+ */
+struct edma_rxdesc_ring {
+	struct napi_struct napi;	/* Napi structure */
+	uint32_t ring_id;		/* RXDESC ring number */
+	uint32_t count;			/* number of descriptors in the ring */
+	uint32_t work_leftover;		/* Leftover descriptors to be processed */
+	uint32_t cons_idx;		/* Ring consumer index */
+	struct edma_rxdesc_desc *pdesc;
+					/* Primary descriptor ring virtual address */
+	struct edma_rxdesc_sec_desc *sdesc;
+					/* Secondary descriptor ring virtual address */
+	struct edma_rx_desc_stats rx_desc_stats;
+					/* Rx descriptor ring statistics */
+	struct edma_rxfill_ring *rxfill;
+					/* RXFILL ring used */
+	bool napi_added;		/* Flag to indicate NAPI add status */
+	dma_addr_t pdma;		/* Primary descriptor ring physical address */
+	dma_addr_t sdma;		/* Secondary descriptor ring physical address */
+	struct sk_buff *head;		/* Head of the skb list in case of scatter-gather frame */
+	struct sk_buff *last;		/* Last skb of the skb list in case of scatter-gather frame */
+};
+
+irqreturn_t edma_rx_handle_irq(int irq, void *ctx);
+int edma_rx_alloc_buffer(struct edma_rxfill_ring *rxfill_ring, int alloc_count);
+int edma_rx_napi_poll(struct napi_struct *napi, int budget);
+
+#endif	/* __EDMA_RX_H__ */
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_tx.c b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_tx.c
new file mode 100644
index 0000000..be48096
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_tx.c
@@ -0,0 +1,614 @@
+/*
+ * Copyright (c) 2021-2022, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/version.h>
+#include <linux/interrupt.h>
+#include <linux/phy.h>
+#include <linux/netdevice.h>
+#include <linux/debugfs.h>
+#include <asm/cacheflush.h>
+
+#include "nss_dp_dev.h"
+#include "edma_regs.h"
+#include "edma_debug.h"
+#include "edma.h"
+
+/*
+ * edma_tx_complete()
+ *	Reap Tx descriptors
+ */
+uint32_t edma_tx_complete(uint32_t work_to_do, struct edma_txcmpl_ring *txcmpl_ring)
+{
+	struct edma_txcmpl_desc *txcmpl;
+	struct edma_tx_cmpl_stats *txcmpl_stats = &txcmpl_ring->tx_cmpl_stats;
+	uint32_t prod_idx;
+	uint32_t cons_idx;
+	uint32_t data;
+	struct sk_buff *skb;
+	uint32_t txcmpl_errors;
+	uint32_t avail, count;
+	uint32_t end_idx;
+	uint32_t more_bit = 0;
+
+	cons_idx = txcmpl_ring->cons_idx;
+
+	if (likely(txcmpl_ring->avail_pkt >= work_to_do)) {
+		avail = work_to_do;
+	} else {
+
+		/*
+		 * Get TXCMPL ring producer index
+		 */
+		data = edma_reg_read(EDMA_REG_TXCMPL_PROD_IDX(txcmpl_ring->id));
+		prod_idx = data & EDMA_TXCMPL_PROD_IDX_MASK;
+
+		avail = EDMA_DESC_AVAIL_COUNT(prod_idx, cons_idx, EDMA_TX_RING_SIZE);
+		txcmpl_ring->avail_pkt = avail;
+
+		if (unlikely(!avail)) {
+			edma_debug("No available descriptors are pending for %d txcmpl ring\n",
+					txcmpl_ring->id);
+			u64_stats_update_begin(&txcmpl_stats->syncp);
+			++txcmpl_stats->no_pending_desc;
+			u64_stats_update_end(&txcmpl_stats->syncp);
+			return 0;
+		}
+
+		avail = min(avail, work_to_do);
+	}
+
+	count = avail;
+
+	end_idx = (cons_idx + avail) & EDMA_TX_RING_SIZE_MASK;
+	txcmpl = EDMA_TXCMPL_DESC(txcmpl_ring, cons_idx);
+
+	if (end_idx > cons_idx) {
+		dmac_inv_range_no_dsb((void *)txcmpl, txcmpl + avail);
+	} else {
+		dmac_inv_range_no_dsb(txcmpl_ring->desc, txcmpl_ring->desc + end_idx);
+		dmac_inv_range_no_dsb((void *)txcmpl, txcmpl_ring->desc + EDMA_TX_RING_SIZE);
+	}
+
+	dsb(st);
+
+	/*
+	 * TODO:
+	 * Instead of freeing the skb, it might be better to save and use
+	 * for Rxfill.
+	 */
+	while (likely(avail--)) {
+
+		/*
+		 * The last descriptor holds the SKB pointer for scattered frames.
+		 * So skip the descriptors with more bit set.
+		 */
+		more_bit = EDMA_TXCMPL_MORE_BIT_GET(txcmpl);
+		if (unlikely(more_bit)) {
+			u64_stats_update_begin(&txcmpl_stats->syncp);
+			++txcmpl_stats->desc_with_more_bit;
+			u64_stats_update_end(&txcmpl_stats->syncp);
+			cons_idx = ((cons_idx + 1) & EDMA_TX_RING_SIZE_MASK);
+			txcmpl = EDMA_TXCMPL_DESC(txcmpl_ring, cons_idx);
+			continue;
+		}
+
+		/*
+		 * Find and free the skb for Tx completion
+		 */
+		skb = (struct sk_buff *)EDMA_TXCMPL_OPAQUE_GET(txcmpl);
+		if (unlikely(!skb)) {
+			edma_warn("Invalid skb: cons_idx:%u prod_idx:%u word2:%x word3:%x\n",
+					cons_idx, prod_idx, txcmpl->word2, txcmpl->word3);
+			u64_stats_update_begin(&txcmpl_stats->syncp);
+			++txcmpl_stats->invalid_buffer;
+			u64_stats_update_end(&txcmpl_stats->syncp);
+		} else {
+			edma_debug("skb:%px, skb->len %d, skb->data_len %d, cons_idx:%d prod_idx:%d word2:0x%x word3:0x%x\n",
+					skb, skb->len, skb->data_len, cons_idx, prod_idx, txcmpl->word2, txcmpl->word3);
+
+			txcmpl_errors = EDMA_TXCOMP_RING_ERROR_GET(txcmpl->word3);
+			if (unlikely(txcmpl_errors)) {
+				edma_err("Error 0x%0x observed in tx complete %d ring\n",
+						txcmpl_errors, txcmpl_ring->id);
+				u64_stats_update_begin(&txcmpl_stats->syncp);
+				++txcmpl_stats->errors;
+				u64_stats_update_end(&txcmpl_stats->syncp);
+			}
+
+			dev_kfree_skb_any(skb);
+		}
+
+		cons_idx = ((cons_idx + 1) & EDMA_TX_RING_SIZE_MASK);
+		txcmpl = EDMA_TXCMPL_DESC(txcmpl_ring, cons_idx);
+	}
+
+	txcmpl_ring->cons_idx = cons_idx;
+	txcmpl_ring->avail_pkt -= count;
+
+	edma_debug("TXCMPL:%u count:%u prod_idx:%u cons_idx:%u\n",
+			txcmpl_ring->id, count, prod_idx, cons_idx);
+	edma_reg_write(EDMA_REG_TXCMPL_CONS_IDX(txcmpl_ring->id), cons_idx);
+
+	return count;
+}
+
+/*
+ * edma_tx_napi_poll()
+ *	EDMA TX NAPI handler
+ */
+int edma_tx_napi_poll(struct napi_struct *napi, int budget)
+{
+	struct edma_txcmpl_ring *txcmpl_ring = (struct edma_txcmpl_ring *)napi;
+	struct edma_gbl_ctx *egc = &edma_gbl_ctx;
+	uint32_t txcmpl_intr_status;
+	int work_done = 0;
+	uint32_t reg_data;
+
+	do {
+		work_done += edma_tx_complete(budget - work_done, txcmpl_ring);
+		if (work_done >= budget) {
+			return work_done;
+		}
+
+		reg_data = edma_reg_read(EDMA_REG_TX_INT_STAT(txcmpl_ring->id));
+		txcmpl_intr_status = reg_data & EDMA_TXCMPL_RING_INT_STATUS_MASK;
+	} while (txcmpl_intr_status);
+
+	/*
+	 * No more packets to process. Finish NAPI processing.
+	 */
+	napi_complete(napi);
+
+	/*
+	 * Set TXCMPL ring interrupt mask
+	 */
+	edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id),
+			egc->txcmpl_intr_mask);
+
+	return work_done;
+}
+
+/*
+ * edma_tx_handle_irq()
+ *	Process TX IRQ and schedule napi
+ */
+irqreturn_t edma_tx_handle_irq(int irq, void *ctx)
+{
+	struct edma_txcmpl_ring *txcmpl_ring = (struct edma_txcmpl_ring *)ctx;
+
+	edma_debug("irq: irq=%d txcmpl_ring_id=%u\n", irq, txcmpl_ring->id);
+	if (likely(napi_schedule_prep(&txcmpl_ring->napi))) {
+		/*
+		 * Disable TxCmpl intr
+		 */
+		edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id),
+				EDMA_MASK_INT_DISABLE);
+		__napi_schedule(&txcmpl_ring->napi);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * edma_tx_desc_init()
+ *	Initializes the Tx descriptor
+ */
+static inline void edma_tx_desc_init(struct edma_pri_txdesc *txdesc)
+{
+	memset(txdesc, 0, sizeof(struct edma_pri_txdesc));
+}
+
+/*
+ * edma_tx_skb_nr_frags()
+ *	Process Tx for skb with nr_frags
+ */
+static uint32_t edma_tx_skb_nr_frags(struct edma_txdesc_ring *txdesc_ring, struct edma_pri_txdesc **txdesc,
+		struct sk_buff *skb, uint32_t *hw_next_to_use)
+{
+	uint8_t i = 0;
+	uint32_t nr_frags = 0, buf_len = 0, num_descs = 0, start_idx = 0, end_idx = 0;
+	struct edma_pri_txdesc *txd = *txdesc;
+
+	/*
+	 * Hold onto the index mapped to *txdesc.
+	 * This will be the index previous to that of current *hw_next_to_use
+	 */
+	start_idx = (((*hw_next_to_use) + EDMA_TX_RING_SIZE_MASK) & EDMA_TX_RING_SIZE_MASK);
+
+	/*
+	 * Handle if the skb has nr_frags
+	 */
+	nr_frags = skb_shinfo(skb)->nr_frags;
+	num_descs = nr_frags;
+	i = 0;
+	while (nr_frags--) {
+		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+		buf_len = skb_frag_size(frag);
+
+		/*
+		 * Setting the MORE bit on the previous Tx descriptor.
+		 * Note: We will flush this descriptor as well later.
+		 */
+		EDMA_TXDESC_MORE_BIT_SET(txd, 1);
+
+		txd = EDMA_TXDESC_PRI_DESC(txdesc_ring, *hw_next_to_use);
+		edma_tx_desc_init(txd);
+		txd->word0 = (dma_addr_t)virt_to_phys(skb_frag_address(frag));
+		dmac_clean_range_no_dsb((void *)skb_frag_address(frag),
+				(void *)(skb_frag_address(frag) + buf_len));
+
+		EDMA_TXDESC_DATA_LEN_SET(txd, buf_len);
+
+		*hw_next_to_use = ((*hw_next_to_use + 1) & EDMA_TX_RING_SIZE_MASK);
+		i++;
+	}
+
+	/*
+	 * This will be the index previous to that of current *hw_next_to_use
+	 */
+	end_idx = (((*hw_next_to_use) + EDMA_TX_RING_SIZE_MASK) & EDMA_TX_RING_SIZE_MASK);
+
+	/*
+	 * Need to flush from initial *txdesc to accomodate for MORE bit change.
+	 * Need to flush all the descriptors but last-one that we filled as well.
+	 */
+	if (end_idx > start_idx) {
+		dmac_clean_range_no_dsb((void *)(*txdesc),
+				((*txdesc) + num_descs));
+	} else {
+		dmac_clean_range_no_dsb(txdesc_ring->pdesc,
+				txdesc_ring->pdesc + end_idx);
+		dmac_clean_range_no_dsb((void *)(*txdesc),
+				txdesc_ring->pdesc + EDMA_TX_RING_SIZE);
+	}
+
+	*txdesc = txd;
+	return num_descs;
+}
+
+/*
+ * edma_tx_skb_first_desc()
+ *	Process the Tx for the first descriptor required for skb
+ */
+static struct edma_pri_txdesc *edma_tx_skb_first_desc(struct nss_dp_dev *dp_dev, struct edma_txdesc_ring *txdesc_ring,
+					struct sk_buff *skb, uint32_t *hw_next_to_use, struct edma_tx_stats *stats)
+{
+	uint32_t buf_len = 0, mss = 0;
+	struct edma_pri_txdesc *txd = NULL;
+
+	/*
+	 * Get the packet length
+	 */
+	buf_len = skb_headlen(skb);
+
+	txd = EDMA_TXDESC_PRI_DESC(txdesc_ring, *hw_next_to_use);
+
+	edma_tx_desc_init(txd);
+
+	/*
+	 * Set the data pointer as the buffer address in the descriptor.
+	 */
+	txd->word0 = (dma_addr_t)virt_to_phys(skb->data);
+	dmac_clean_range_no_dsb((void *)skb->data, (void *)(skb->data + buf_len));
+
+	EDMA_TXDESC_SERVICE_CODE_SET(txd, EDMA_SC_BYPASS);
+
+	/*
+	 * Offload L3/L4 checksum computation
+	 */
+	if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
+		EDMA_TXDESC_ADV_OFFLOAD_SET(txd);
+		EDMA_TXDESC_IP_CSUM_SET(txd);
+		EDMA_TXDESC_L4_CSUM_SET(txd);
+	}
+
+	/*
+	 * Check if the packet needs TSO
+	 */
+	if (unlikely(skb_is_gso(skb))) {
+		if ((skb_shinfo(skb)->gso_type == SKB_GSO_TCPV4) ||
+				(skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6)){
+			mss = skb_shinfo(skb)->gso_size;
+			EDMA_TXDESC_TSO_ENABLE_SET(txd, 1);
+			EDMA_TXDESC_MSS_SET(txd, mss);
+
+			/*
+			 * Update tso stats
+			 */
+			u64_stats_update_begin(&stats->syncp);
+			stats->tx_tso_pkts++;
+			u64_stats_update_end(&stats->syncp);
+		}
+	}
+
+	/*
+	 * Set packet length in the descriptor
+	 */
+	EDMA_TXDESC_DATA_LEN_SET(txd, buf_len);
+
+	/*
+	 * Set destination information in the descriptor
+	 */
+	EDMA_DST_INFO_SET(txd, dp_dev->macid);
+
+	*hw_next_to_use = (*hw_next_to_use + 1) & EDMA_TX_RING_SIZE_MASK;
+
+	return txd;
+}
+
+/*
+ * edma_tx_skb_sg_fill_desc()
+ * 	API to fill SG skb into Tx descriptor. Handles both nr_frags and fraglist cases.
+ */
+static uint32_t edma_tx_skb_sg_fill_desc(struct nss_dp_dev *dp_dev, struct edma_txdesc_ring *txdesc_ring,
+		struct edma_pri_txdesc **txdesc, struct sk_buff *skb, uint32_t *hw_next_to_use,
+		struct edma_tx_stats *stats)
+{
+	uint32_t buf_len = 0, num_descs = 0;
+	struct sk_buff *iter_skb = NULL;
+	uint32_t num_sg_frag_list = 0;
+	struct edma_pri_txdesc *txd = *txdesc;
+
+	/*
+	 * Process head skb
+	 */
+	txd = edma_tx_skb_first_desc(dp_dev, txdesc_ring, skb, hw_next_to_use, stats);
+	num_descs++;
+
+	/*
+	 * Process skb with nr_frags
+	 */
+	if (unlikely(skb_shinfo(skb)->nr_frags)) {
+		num_descs += edma_tx_skb_nr_frags(txdesc_ring, &txd, skb, hw_next_to_use);
+		u64_stats_update_begin(&stats->syncp);
+		stats->tx_nr_frag_pkts++;
+		u64_stats_update_end(&stats->syncp);
+	}
+
+	if (unlikely(skb_has_frag_list(skb))) {
+		struct edma_pri_txdesc *start_desc = NULL;
+		uint32_t start_idx = 0, end_idx = 0;
+
+		/*
+		 * Hold onto the index mapped to txd.
+		 * This will be the index previous to that of current *hw_next_to_use
+		 */
+		start_idx = (((*hw_next_to_use) + EDMA_TX_RING_SIZE_MASK) & EDMA_TX_RING_SIZE_MASK);
+		start_desc = txd;
+
+		/*
+		 * Walk through all fraglist skbs
+		 */
+		skb_walk_frags(skb, iter_skb) {
+			uint32_t num_nr_frag = 0;
+
+			buf_len = skb_headlen(iter_skb);
+
+			/*
+			 * We make sure to flush this descriptor later
+			 */
+			EDMA_TXDESC_MORE_BIT_SET(txd, 1);
+
+			txd = EDMA_TXDESC_PRI_DESC(txdesc_ring, *hw_next_to_use);
+			edma_tx_desc_init(txd);
+			txd->word0 = (dma_addr_t)virt_to_phys(iter_skb->data);
+			dmac_clean_range_no_dsb((void *)iter_skb->data,
+					(void *)(iter_skb->data + buf_len));
+
+			EDMA_TXDESC_DATA_LEN_SET(txd, buf_len);
+
+			*hw_next_to_use = (*hw_next_to_use + 1) & EDMA_TX_RING_SIZE_MASK;
+			num_descs += 1;
+			num_sg_frag_list += 1;
+
+			/*
+			 * skb fraglist skb can have nr_frags
+			 */
+			if (unlikely(skb_shinfo(iter_skb)->nr_frags)) {
+				num_nr_frag = edma_tx_skb_nr_frags(txdesc_ring, &txd, iter_skb, hw_next_to_use);
+				num_descs += num_nr_frag;
+				num_sg_frag_list += num_nr_frag;
+
+				/*
+				 * Update fraglist with nr_frag stats
+				 */
+				u64_stats_update_begin(&stats->syncp);
+				stats->tx_fraglist_with_nr_frags_pkts++;
+				u64_stats_update_end(&stats->syncp);
+			}
+		}
+
+		/*
+		 * This will be the index previous to
+		 * that of current *hw_next_to_use
+		 */
+		end_idx = (((*hw_next_to_use) + EDMA_TX_RING_SIZE_MASK) &
+					EDMA_TX_RING_SIZE_MASK);
+
+		/*
+		 * Need to flush from initial txd to accomodate for MORE bit change.
+		 * Need to flush all the descriptors but last-one that we filled as well.
+		 * This may result double flush if fraglist iter_skb has nr_frags which is rare.
+		 */
+		if (end_idx > start_idx) {
+			dmac_clean_range_no_dsb((void *)(start_desc),
+					((start_desc) + num_sg_frag_list));
+		} else {
+			dmac_clean_range_no_dsb(txdesc_ring->pdesc,
+					txdesc_ring->pdesc + end_idx);
+			dmac_clean_range_no_dsb((void *)(start_desc),
+					txdesc_ring->pdesc + EDMA_TX_RING_SIZE);
+		}
+
+		/*
+		 * Update frag_list stats
+		 */
+		u64_stats_update_begin(&stats->syncp);
+		stats->tx_fraglist_pkts++;
+		u64_stats_update_end(&stats->syncp);
+	}
+
+	edma_debug("skb:%px num_descs_filled: %u, nr_frags %u frag_list fragments %u\n",
+			skb, num_descs, skb_shinfo(skb)->nr_frags, num_sg_frag_list);
+
+	*txdesc = txd;
+	return num_descs;
+}
+
+/*
+ * edma_tx_num_descs_for_sg()
+ *	Calculates number of descriptors needed for SG
+ */
+static uint32_t edma_tx_num_descs_for_sg(struct sk_buff *skb)
+{
+	uint32_t nr_frags_first = 0, num_tx_desc_needed = 0;
+
+	/*
+	 * Check if we have enough Tx descriptors for SG
+	 */
+	if (unlikely(skb_shinfo(skb)->nr_frags)) {
+		nr_frags_first = skb_shinfo(skb)->nr_frags;
+		BUG_ON(nr_frags_first > MAX_SKB_FRAGS);
+		num_tx_desc_needed += nr_frags_first;
+	}
+
+	/*
+	 * Walk through fraglist skbs making a note of nr_frags
+	 * One Tx desc for fraglist skb. Fraglist skb may have further nr_frags.
+	 */
+	if (unlikely(skb_has_frag_list(skb))) {
+		struct sk_buff *iter_skb;
+		skb_walk_frags(skb, iter_skb) {
+			uint32_t nr_frags = skb_shinfo(iter_skb)->nr_frags;
+			BUG_ON(nr_frags > MAX_SKB_FRAGS);
+			num_tx_desc_needed += (1 + nr_frags);
+		}
+	}
+
+	return num_tx_desc_needed;
+}
+
+/*
+ * edma_tx_avail_desc()
+ *	Get available Tx descriptors
+ */
+static uint32_t edma_tx_avail_desc(struct edma_txdesc_ring *txdesc_ring, uint32_t hw_next_to_use)
+{
+	uint32_t data = 0, avail = 0, hw_next_to_clean = 0;
+
+	data = edma_reg_read(EDMA_REG_TXDESC_CONS_IDX(txdesc_ring->id));
+	hw_next_to_clean = data & EDMA_TXDESC_CONS_IDX_MASK;
+
+	avail = EDMA_DESC_AVAIL_COUNT(hw_next_to_clean - 1, hw_next_to_use, EDMA_TX_RING_SIZE);
+
+	return avail;
+}
+
+/*
+ * edma_tx_ring_xmit()
+ *	API to transmit a packet.
+ */
+enum edma_tx edma_tx_ring_xmit(struct net_device *netdev, struct sk_buff *skb,
+				struct edma_txdesc_ring *txdesc_ring,
+				struct edma_tx_stats *stats)
+{
+	struct nss_dp_dev *dp_dev = netdev_priv(netdev);
+	struct edma_tx_desc_stats *txdesc_stats = &txdesc_ring->tx_desc_stats;
+	uint32_t hw_next_to_use = 0;
+	uint32_t num_tx_desc_needed = 0, num_desc_filled = 0;
+	struct edma_pri_txdesc *txdesc = NULL;
+
+	hw_next_to_use = txdesc_ring->prod_idx;
+
+	if (unlikely(!(txdesc_ring->avail_desc)))  {
+		txdesc_ring->avail_desc = edma_tx_avail_desc(txdesc_ring, hw_next_to_use);
+		if (unlikely(!txdesc_ring->avail_desc)) {
+			edma_debug("No available descriptors are present at %d ring\n",
+					txdesc_ring->id);
+
+			u64_stats_update_begin(&txdesc_stats->syncp);
+			++txdesc_stats->no_desc_avail;
+			u64_stats_update_end(&txdesc_stats->syncp);
+			return EDMA_TX_FAIL_NO_DESC;
+		}
+	}
+
+	/*
+	 * Process head skb for linear skb
+	 * Process head skb + nr_frags + fraglist for non linear skb
+	 */
+	if (likely(!skb_is_nonlinear(skb))) {
+		txdesc = edma_tx_skb_first_desc(dp_dev, txdesc_ring, skb, &hw_next_to_use, stats);
+		num_desc_filled++;
+	} else {
+		num_tx_desc_needed += 1;
+		num_tx_desc_needed += edma_tx_num_descs_for_sg(skb);
+
+		if (unlikely(num_tx_desc_needed > txdesc_ring->avail_desc)) {
+			txdesc_ring->avail_desc = edma_tx_avail_desc(txdesc_ring, hw_next_to_use);
+			if (num_tx_desc_needed > txdesc_ring->avail_desc) {
+				u64_stats_update_begin(&txdesc_stats->syncp);
+				++txdesc_stats->no_desc_avail;
+				u64_stats_update_end(&txdesc_stats->syncp);
+				edma_debug("Not enough available descriptors are present at %d ring for SG packet. Needed %d, currently available %d\n",
+					txdesc_ring->id, num_tx_desc_needed, txdesc_ring->avail_desc);
+				return EDMA_TX_FAIL_NO_DESC;
+			}
+		}
+
+		num_desc_filled = edma_tx_skb_sg_fill_desc(dp_dev, txdesc_ring, &txdesc, skb, &hw_next_to_use, stats);
+	}
+
+	/*
+	 * Set the skb pointer to the descriptor's opaque field/s
+	 * on the last descriptor of the packet/SG packet.
+	 */
+	EDMA_TXDESC_OPAQUE_SET(txdesc, skb);
+
+	/*
+	 * Flush the last descriptor.
+	 */
+	dmac_clean_range_no_dsb(txdesc, txdesc + 1);
+
+	/*
+	 * Update producer index
+	 */
+	txdesc_ring->prod_idx = hw_next_to_use & EDMA_TXDESC_PROD_IDX_MASK;
+	txdesc_ring->avail_desc -= num_desc_filled;
+
+	edma_debug("%s: skb:%px tx_ring:%u proto:0x%x skb->len:%d\n"
+			" port:%u prod_idx:%u ip_summed:0x%x\n",
+			netdev->name, skb, txdesc_ring->id, ntohs(skb->protocol),
+			skb->len, dp_dev->macid, hw_next_to_use, skb->ip_summed);
+
+	/*
+	 * Make sure the information written to the descriptors
+	 * is updated before writing to the hardware.
+	 */
+	dsb(st);
+
+	edma_reg_write(EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id),
+			txdesc_ring->prod_idx);
+
+	u64_stats_update_begin(&stats->syncp);
+	stats->tx_pkts++;
+	stats->tx_bytes += skb->len;
+	u64_stats_update_end(&stats->syncp);
+
+	return EDMA_TX_OK;
+}
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_tx.h b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_tx.h
new file mode 100644
index 0000000..10a3869
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/edma_tx.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2021-2022, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __EDMA_TX_H__
+#define __EDMA_TX_H__
+
+#define EDMA_GET_DESC(R, i, type)	(&(((type *)((R)->desc))[(i)]))
+#define EDMA_GET_PDESC(R, i, type)	(&(((type *)((R)->pdesc))[(i)]))
+#define EDMA_GET_SDESC(R, i, type)	(&(((type *)((R)->sdesc))[(i)]))
+#define EDMA_TXCMPL_DESC(R, i)		EDMA_GET_DESC(R, i, struct edma_txcmpl_desc)
+#define EDMA_TXDESC_PRI_DESC(R, i)	EDMA_GET_PDESC(R, i, struct edma_pri_txdesc)
+#define EDMA_TXDESC_SEC_DESC(R, i)	EDMA_GET_SDESC(R, i, struct edma_sec_txdesc)
+
+#define EDMA_MAX_TXCMPL_RINGS		32	/* Max TxCmpl rings */
+#define EDMA_MAX_TXDESC_RINGS		32	/* Max TxDesc rings */
+#define EDMA_TXCMPL_RING_PER_CORE_MAX	6
+#define EDMA_TX_MAX_PRIORITY_LEVEL	1
+
+#define EDMA_TX_RING_SIZE		256
+#define EDMA_TX_RING_SIZE_MASK		(EDMA_TX_RING_SIZE - 1)
+
+#define EDMA_TX_RING_PER_CORE_MAX	(EDMA_TX_MAX_PRIORITY_LEVEL * EDMA_MAX_GMACS)
+
+#define EDMA_DST_PORT_TYPE		2
+#define EDMA_DST_PORT_TYPE_SHIFT	28
+#define EDMA_DST_PORT_TYPE_MASK		(0xf << EDMA_DST_PORT_TYPE_SHIFT)
+#define EDMA_DST_PORT_ID_SHIFT		16
+#define EDMA_DST_PORT_ID_MASK		(0xfff << EDMA_DST_PORT_ID_SHIFT)
+
+#define EDMA_DST_PORT_TYPE_SET(x)	(((x) << EDMA_DST_PORT_TYPE_SHIFT) & EDMA_DST_PORT_TYPE_MASK)
+#define EDMA_DST_PORT_ID_SET(x)		(((x) << EDMA_DST_PORT_ID_SHIFT) & EDMA_DST_PORT_ID_MASK)
+#define EDMA_DST_INFO_SET(desc, x)	((desc)->word4 |= (EDMA_DST_PORT_TYPE_SET(EDMA_DST_PORT_TYPE) | EDMA_DST_PORT_ID_SET(x)))
+#define EDMA_TXDESC_TSO_ENABLE_SHIFT		24
+#define EDMA_TXDESC_TSO_ENABLE_MASK		0x1000000
+#define EDMA_TXDESC_TSO_ENABLE_SET(desc, x)	((desc)->word5 |= (((x) << EDMA_TXDESC_TSO_ENABLE_SHIFT) & EDMA_TXDESC_TSO_ENABLE_MASK))
+#define EDMA_TXDESC_MSS_SHIFT			16
+#define EDMA_TXDESC_MSS_MASK			0xFFFF0000
+#define EDMA_TXDESC_MSS_SET(desc, x)		((desc)->word6 |= (((x) << EDMA_TXDESC_MSS_SHIFT) & EDMA_TXDESC_MSS_MASK))
+#define EDMA_TXDESC_MORE_BIT_MASK	0x40000000
+#define EDMA_TXDESC_MORE_BIT_SHIFT	30
+#define EDMA_TXDESC_MORE_BIT_SET(desc, x)	((desc)->word1 |= (((x) << EDMA_TXDESC_MORE_BIT_SHIFT) & EDMA_TXDESC_MORE_BIT_MASK))
+
+#define EDMA_TXDESC_ADV_OFFSET_BIT	31
+#define EDMA_TXDESC_ADV_OFFLOAD_SET(desc)	((desc)->word5 |= (1 << EDMA_TXDESC_ADV_OFFSET_BIT))
+#define EDMA_TXDESC_IP_CSUM_BIT		25
+#define EDMA_TXDESC_IP_CSUM_SET(desc)		((desc)->word5 |= (1 << EDMA_TXDESC_IP_CSUM_BIT))
+
+#define EDMA_TXDESC_L4_CSUM_SET_SHIFT	26
+#define EDMA_TXDESC_L4_CSUM_SET_MASK	(0x3 << EDMA_TXDESC_L4_CSUM_SET_SHIFT)
+#define EDMA_TXDESC_L4_CSUM_SET(desc)	((desc)->word5 |= ((1 << EDMA_TXDESC_L4_CSUM_SET_SHIFT) & EDMA_TXDESC_L4_CSUM_SET_MASK))
+
+#define EDMA_TXDESC_DATA_LEN_SET(desc, x)	((desc)->word5 |= ((x) & 0x1ffff))
+#define EDMA_TXDESC_SERVICE_CODE_SHIFT	16
+#define EDMA_TXDESC_SERVICE_CODE_MASK	(0x1FF << EDMA_TXDESC_SERVICE_CODE_SHIFT)
+#define EDMA_TXDESC_SERVICE_CODE_SET(desc, x)	((desc)->word1 |= (((x) << EDMA_TXDESC_SERVICE_CODE_SHIFT) & EDMA_TXDESC_SERVICE_CODE_MASK))
+#ifdef __LP64__
+#define EDMA_TXDESC_OPAQUE_GET(desc)		(((uint64_t)(desc)->word3 << 32) | (desc)->word2)
+#define EDMA_TXCMPL_OPAQUE_GET(desc)		(((uint64_t)(desc)->word1 << 32) | (desc)->word0)
+#define EDMA_TXDESC_OPAQUE_LO_SET(desc, ptr)	((desc)->word2 = (uint32_t)(uintptr_t)ptr)
+#define EDMA_TXDESC_OPAQUE_HI_SET(desc, ptr)	((desc)->word3 = (uint32_t)((uint64_t)ptr >> 32))
+#define EDMA_TXDESC_OPAQUE_SET(desc, ptr)	do {	\
+	EDMA_TXDESC_OPAQUE_LO_SET(desc, ptr);		\
+	EDMA_TXDESC_OPAQUE_HI_SET(desc, ptr);		\
+} while (0)
+#else
+#define EDMA_TXCMPL_OPAQUE_GET(desc)		((desc)->word0)
+#define EDMA_TXDESC_OPAQUE_GET(desc)		((desc)->word2)
+#define EDMA_TXDESC_OPAQUE_LO_SET(desc, ptr)	((desc)->word2 = (uint32_t)(uintptr_t)ptr)
+#define EDMA_TXDESC_OPAQUE_SET(desc, ptr)	EDMA_TXDESC_OPAQUE_LO_SET(desc, ptr)
+#endif
+#define EDMA_TXCMPL_MORE_BIT_MASK		0x40000000
+#define EDMA_TXCMPL_MORE_BIT_GET(desc)		((desc)->word2 & EDMA_TXCMPL_MORE_BIT_MASK)
+
+#define EDMA_TXCOMP_RING_ERROR_MASK	0x7fffff
+#define EDMA_TXCOMP_RING_ERROR_GET(x)	((x) & EDMA_TXCOMP_RING_ERROR_MASK)
+
+/*
+ * edma_tx
+ *	List of return values of the TX API.
+ */
+enum edma_tx {
+	EDMA_TX_OK = 0,			/* Tx success */
+	EDMA_TX_FAIL_NO_DESC = 1,	/* Not enough descriptors */
+	EDMA_TX_FAIL = 2,		/* Tx failure */
+};
+
+/*
+ * edma_tx_stats
+ *	EDMA TX per cpu stats
+ */
+struct edma_tx_stats {
+	uint64_t tx_pkts;
+	uint64_t tx_bytes;
+	uint64_t tx_drops;
+	uint64_t tx_nr_frag_pkts;
+	uint64_t tx_fraglist_pkts;
+	uint64_t tx_fraglist_with_nr_frags_pkts;
+	uint64_t tx_tso_pkts;
+	struct u64_stats_sync syncp;
+};
+
+/*
+ * edma_tx_cmpl_stats
+ *	EDMA TX complete ring statistics structure
+ */
+struct edma_tx_cmpl_stats {
+	uint64_t invalid_buffer;		/* Invalid buffer address received */
+	uint64_t errors;			/* Other Tx complete descriptor errors indicated by the hardware */
+	uint64_t desc_with_more_bit;		/* Packet's segment transmit count */
+	uint64_t no_pending_desc;		/* No descriptor is pending for processing */
+	struct u64_stats_sync syncp;		/* Synchronization pointer */
+};
+
+/*
+ * edma_tx_desc_stats
+ * 	EDMA Tx descriptor ring statistics structure
+ */
+struct edma_tx_desc_stats {
+	uint64_t no_desc_avail;			/* No descriptor available to transmit */
+	struct u64_stats_sync syncp;		/* Synchronization pointer */
+};
+
+/*
+ * edma_pri_tx_desc
+ *	EDMA primary TX descriptor.
+ */
+struct edma_pri_txdesc {
+	uint32_t word0;		/* Low 32-bit of buffer address */
+	uint32_t word1;		/* Buffer recycling, PTP tag flag, PRI valid flag */
+	uint32_t word2;		/* Low 32-bit of opaque value */
+	uint32_t word3;		/* High 32-bit of opaque value */
+	uint32_t word4;		/* Source/Destination port info */
+	uint32_t word5;		/* VLAN offload, csum_mode, ip_csum_en, tso_en, data length */
+	uint32_t word6;		/* MSS/hash_value/PTP tag, data offset */
+	uint32_t word7;		/* L4/L3 offset, PROT type, L2 type, CVLAN/SVLAN tag, service code */
+};
+
+/*
+ * edma_sec_txdesc
+ *	EDMA secondary TX descriptor.
+ */
+struct edma_sec_txdesc {
+	uint32_t word0;		/* Reserved */
+	uint32_t word1;		/* Custom csum offset, payload offset, TTL/NAT action */
+	uint32_t word2;		/* NAPT translated port, DSCP value, TTL value */
+	uint32_t word3;		/* Flow index value and valid flag */
+	uint32_t word4;		/* Reserved */
+	uint32_t word5;		/* Reserved */
+	uint32_t word6;		/* CVLAN/SVLAN command */
+	uint32_t word7;		/* CVLAN/SVLAN tag value */
+};
+
+/*
+ * edma_txcmpl_desc
+ *	EDMA TX complete descriptor.
+ */
+struct edma_txcmpl_desc {
+	uint32_t word0;		/* Low 32-bit opaque value */
+	uint32_t word1;		/* High 32-bit opaque value */
+	uint32_t word2;		/* More fragment, transmit ring id, pool id */
+	uint32_t word3;		/* Error indications */
+};
+
+/*
+ * edma_txdesc_ring
+ *	EDMA TX descriptor ring.
+ */
+struct edma_txdesc_ring {
+	uint32_t prod_idx;		/* Producer index */
+	uint32_t avail_desc;		/* Number of available descriptor to process */
+	uint32_t id;			/* TXDESC ring number */
+	struct edma_pri_txdesc *pdesc;	/* Primary descriptor ring virtual address */
+	dma_addr_t pdma;		/* Primary descriptor ring physical address */
+	struct edma_sec_txdesc *sdesc;	/* Secondary descriptor ring virtual address */
+	struct edma_tx_desc_stats tx_desc_stats;
+					/* Tx descriptor ring statistics */
+	dma_addr_t sdma;		/* Secondary descriptor ring physical address */
+	uint32_t count;			/* Number of descriptors */
+	uint8_t fc_grp_id;		/* Flow control group ID */
+};
+
+/*
+ * edma_txcmpl_ring
+ *	EDMA TX complete ring.
+ */
+struct edma_txcmpl_ring {
+	struct napi_struct napi;	/* NAPI structure */
+	uint32_t cons_idx;		/* Consumer index */
+	uint32_t avail_pkt;		/* Number of available packets to process */
+	struct edma_txcmpl_desc *desc;	/* Descriptor ring virtual address */
+	uint32_t id;			/* TXCMPL ring number */
+	struct edma_tx_cmpl_stats tx_cmpl_stats;
+					/* Tx complete ring statistics */
+	dma_addr_t dma;			/* Descriptor ring physical address */
+	uint32_t count;			/* Number of descriptors in the ring */
+	bool napi_added;		/* Flag to indicate NAPI add status */
+};
+
+enum edma_tx edma_tx_ring_xmit(struct net_device *netdev, struct sk_buff *skb,
+				struct edma_txdesc_ring *txdesc_ring,
+				struct edma_tx_stats *stats);
+uint32_t edma_tx_complete(uint32_t work_to_do,
+				struct edma_txcmpl_ring *txcmpl_ring);
+irqreturn_t edma_tx_handle_irq(int irq, void *ctx);
+int edma_tx_napi_poll(struct napi_struct *napi, int budget);
+
+#endif	/* __EDMA_TX_H__ */
diff --git a/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/include/nss_dp_hal_info.h b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/include/nss_dp_hal_info.h
new file mode 100644
index 0000000..684c782
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/edma_dp/edma_v2/include/nss_dp_hal_info.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_HAL_INFO_H__
+#define __NSS_DP_HAL_INFO_H__
+
+#include <edma.h>
+
+/*
+ * nss_dp_hal_info
+ *	Data plane specific information wrapper
+ */
+struct nss_dp_hal_info {
+	struct edma_txdesc_ring *txr_map[EDMA_TX_MAX_PRIORITY_LEVEL][NR_CPUS];
+				/* Per CPU Tx descriptor ring map */
+	struct edma_pcpu_stats pcpu_stats;
+				/* Per CPU netdev statistics */
+};
+
+#endif	/* __NSS_DP_HAL_INFO_H__ */
diff --git a/qca-nss-dp/hal/dp_ops/syn_gmac_dp/include/nss_dp_hal_info.h b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/include/nss_dp_hal_info.h
new file mode 100644
index 0000000..24cb86e
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/include/nss_dp_hal_info.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_HAL_INFO_H__
+#define __NSS_DP_HAL_INFO_H__
+
+#include "../syn_dp.h"
+
+/*
+ * nss_dp_hal_info
+ *	Data plane specific information wrapper
+ */
+struct nss_dp_hal_info {
+	struct syn_dp_info syn_info;
+};
+
+#endif	/* __NSS_DP_HAL_INFO_H__ */
diff --git a/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dma_desc.h b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dma_desc.h
new file mode 100644
index 0000000..c5787d9
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dma_desc.h
@@ -0,0 +1,400 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __SYN_DMA_DESC__
+#define __SYN_DMA_DESC__
+
+/**********************************************************
+ * DMA Engine descriptors
+ **********************************************************/
+/*
+******Enhanced Descritpor structure to support 8K buffer per buffer *******
+
+dma_rx_base_addr = 0x000C,	CSR3 - Receive Descriptor list base address
+dma_rx_base_addr is the pointer to the first Rx Descriptors.
+The Descriptor format in Little endian with a 32 bit Data bus is as shown below.
+
+Similarly
+dma_tx_base_addr     = 0x0010,  CSR4 - Transmit Descriptor list base address
+dma_tx_base_addr is the pointer to the first Tx Descriptors.
+The Descriptor format in Little endian with a 32 bit Data bus is as shown below.
+	-------------------------------------------------------------------------
+ RDES0	|OWN (31)|								|
+	-------------------------------------------------------------------------
+ RDES1	| Ctrl | Res | Byte Count Buffer 2 | Ctrl | Res | Byte Count Buffer 1	|
+	-------------------------------------------------------------------------
+ RDES2	|	Buffer 1 Address						|
+	-------------------------------------------------------------------------
+ RDES3	|	Buffer 2 Address / Next Descriptor Address			|
+	-------------------------------------------------------------------------
+ RDES4	|	Extended Status							|
+	-------------------------------------------------------------------------
+ RDES5	|	Reserved							|
+	-------------------------------------------------------------------------
+ RDES6	|	Receive Timestamp Low						|
+	-------------------------------------------------------------------------
+ RDES7	|	Receive Timestamp High						|
+	-------------------------------------------------------------------------
+
+	------------------------------------------------------------------------
+ TDES0	|OWN (31)| Ctrl | Res | Ctrl | Res | Status				|
+	------------------------------------------------------------------------
+ TDES1	| Res | Byte Count Buffer 2 | Res |	Byte Count Buffer 1		|
+	------------------------------------------------------------------------
+ TDES2	|	Buffer 1 Address						|
+	------------------------------------------------------------------------
+ TDES3	|	Buffer 2 Address / Next Descriptor Address			|
+	------------------------------------------------------------------------
+ TDES4	|	Reserved							|
+	------------------------------------------------------------------------
+ TDES5	|	Reserved							|
+	------------------------------------------------------------------------
+ TDES6	|	Transmit Timestamp Low						|
+	------------------------------------------------------------------------
+ TDES7	|	Transmit Timestamp Higher					|
+	------------------------------------------------------------------------
+*/
+
+/*
+ * syn_dma_desc_mode
+ *	GMAC DMA descriptors mode
+ */
+enum syn_dma_desc_mode {
+	RINGMODE = 0x00000001,
+	CHAINMODE = 0x00000002,
+};
+
+/*
+ * syn_dma_desc_status
+ *	status word of DMA descriptor
+ */
+enum syn_dma_desc_status {
+	DESC_OWN_BY_DMA = 0x80000000,		/* (OWN)Descriptor is
+						   owned by DMA engine */
+	DESC_RX_DA_FILTER_FAIL = 0x40000000,	/* (AFM)Rx - DA Filter
+						   Fail for the rx frame */
+	DESC_RX_FRAME_LENGTH_MASK = 0x3FFF0000,	/* (FL)Receive descriptor
+						   frame length */
+	DESC_RX_FRAME_LENGTH_SHIFT = 16,
+	DESC_RX_ERROR = 0x00008000,		/* (ES)Error summary bit
+						   - OR of the  following bits:
+						   DE || OE || IPC || GF || LC  || RWT
+						   || RE || CE */
+	DESC_RX_TRUNCATED = 0x00004000,		/* (DE)Rx - no more descriptors
+						   for receive frame */
+	DESC_SA_FILTER_FAIL = 0x00002000,	/* (SAF)Rx - SA Filter Fail for
+						   the received frame */
+	DESC_RX_LENGTH_ERROR = 0x00001000,	/* (LE)Rx - frm size not
+						   matching with len field */
+	DESC_RX_OVERFLOW = 0x00000800,		/* (OE)Rx - frm was damaged due
+						   to buffer overflow */
+	DESC_RX_VLAN_TAG = 0x00000400,		/* (VLAN)Rx - received frame
+						   is a VLAN frame */
+	DESC_RX_FIRST = 0x00000200,		/* (FS)Rx - first
+						   descriptor of the frame */
+	DESC_RX_LAST = 0x00000100,		/* (LS)Rx - last
+						   descriptor of the frame */
+	DESC_RX_LONG_FRAME = 0x00000080,	/* (Giant Frame)Rx - frame is
+						   longer than 1518/1522 */
+	DESC_RX_COLLISION = 0x00000040,		/* (LC)Rx - late collision
+						   occurred during reception */
+	DESC_RX_FRAME_ETHER = 0x00000020,	/* (FT)Rx - Frame type - Ether,
+						   otherwise 802.3 */
+	DESC_RX_WATCHDOG = 0x00000010,		/* (RWT)Rx - watchdog timer
+						   expired during reception */
+	DESC_RX_MII_ERROR = 0x00000008,		/* (RE)Rx - error reported
+						   by MII interface */
+	DESC_RX_DRIBBLING = 0x00000004,		/* (DE)Rx - frame contains non
+						   int multiple of 8 bits */
+	DESC_RX_CRC = 0x00000002,		/* (CE)Rx - CRC error */
+	DESC_RX_EXT_STS = 0x00000001,		/* Extended Status Available
+						   in RDES4 */
+	DESC_TX_ERROR = 0x00008000,		/* (ES)Error summary Bits */
+	DESC_TX_INT_ENABLE = 0x40000000,	/* (IC)Tx - interrupt on
+						   completion */
+	DESC_TX_LAST = 0x20000000,		/* (LS)Tx - Last segment of the
+						   frame */
+	DESC_TX_FIRST = 0x10000000,		/* (FS)Tx - First segment of the
+						   frame */
+	DESC_TX_DISABLE_CRC = 0x08000000,	/* (DC)Tx - Add CRC disabled
+						   (first segment only) */
+	DESC_TX_DISABLE_PADD = 0x04000000,	/* (DP)disable padding,
+						   added by - reyaz */
+	DESC_TX_CIS_MASK = 0x00c00000,		/* Tx checksum offloading
+						   control mask */
+	DESC_TX_CIS_BYPASS = 0x00000000,	/* Checksum bypass */
+	DESC_TX_CIS_IPV4_HDR_CS = 0x00400000,	/* IPv4 header checksum */
+	DESC_TX_CIS_TCP_ONLY_CS = 0x00800000,	/* TCP/UDP/ICMP checksum.
+						   Pseudo header  checksum
+						   is assumed to be present */
+	DESC_TX_CIS_TCP_PSEUDO_CS = 0x00c00000,	/* TCP/UDP/ICMP checksum fully
+						   in hardware  including
+						   pseudo header */
+	DESC_TX_DESC_END_OF_RING = 0x00200000,	/* (TER)End of descriptor ring */
+	DESC_TX_DESC_CHAIN = 0x00100000,	/* (TCH)Second buffer address
+						   is chain address */
+	DESC_RX_CHK_BIT0 = 0x00000001,		/* Rx Payload Checksum Error */
+	DESC_RX_CHK_BIT7 = 0x00000080,		/* (IPC CS ERROR)Rx - Ipv4
+						   header checksum error */
+	DESC_RX_CHK_BIT5 = 0x00000020,		/* (FT)Rx - Frame type - Ether,
+						   otherwise 802.3 */
+	DESC_RX_TS_AVAIL = 0x00000080,		/* Time stamp available */
+	DESC_RX_FRAME_TYPE = 0x00000020,	/* (FT)Rx - Frame type - Ether,
+						   otherwise 802.3 */
+	DESC_TX_IPV4_CHK_ERROR = 0x00010000,	/* (IHE) Tx Ip header error */
+	DESC_TX_TIMEOUT = 0x00004000,		/* (JT)Tx - Transmit
+						   jabber timeout */
+	DESC_TX_FRAME_FLUSHED = 0x00002000,	/* (FF)Tx - DMA/MTL flushed
+						   the frame  due to SW flush */
+	DESC_TX_PAY_CHK_ERROR = 0x00001000,	/* (PCE) Tx Payload checksum
+						   Error */
+	DESC_TX_LOST_CARRIER = 0x00000800,	/* (LC)Tx - carrier lost
+						   during tramsmission */
+	DESC_TX_NO_CARRIER = 0x00000400,	/* (NC)Tx - no carrier signal
+						   from the tranceiver */
+	DESC_TX_LATE_COLLISION = 0x00000200,	/* (LC)Tx - transmission aborted
+						   due to collision */
+	DESC_TX_EXC_COLLISIONS = 0x00000100,	/* (EC)Tx - transmission aborted
+						   after 16 collisions */
+	DESC_TX_VLAN_FRAME = 0x00000080,	/* (VF)Tx - VLAN-type frame */
+	DESC_TX_COLL_MASK = 0x00000078,		/* (CC)Tx - Collision count */
+	DESC_TX_COLL_SHIFT = 3,
+	DESC_TX_EXC_DEFERRAL = 0x00000004,	/* (ED)Tx - excessive deferral */
+	DESC_TX_UNDERFLOW = 0x00000002,		/* (UF)Tx - late data arrival
+						   from the memory */
+	DESC_TX_DEFERRED = 0x00000001,		/* (DB)Tx - frame
+						   transmision deferred */
+
+	/*
+	 * This explains the RDES1/TDES1 bits layout
+	 *             ------------------------------------------------------
+	 * RDES1/TDES1 | Control Bits | Byte Count Buf 2 | Byte Count Buf 1 |
+	 *             ------------------------------------------------------
+	 */
+
+	/* dma_descriptor_length */	/* length word of DMA descriptor */
+	DESC_RX_DIS_INT_COMPL = 0x80000000,	/* (Disable Rx int on completion) */
+	DESC_RX_DESC_END_OF_RING = 0x00008000,	/* (RER)End of descriptor ring */
+	DESC_RX_DESC_CHAIN = 0x00004000,	/* (RCH)Second buffer address
+						    is chain address */
+	DESC_SIZE2_MASK = 0x1FFF0000,		/* (RBS2/TBS2) Buffer 2 size */
+	DESC_SIZE2_SHIFT = 16,
+	DESC_SIZE1_MASK = 0x00001FFF,		/* (RBS1/TBS1) Buffer 1 size */
+	DESC_SIZE1_SHIFT = 0,
+
+	/*
+	 * This explains the RDES4 Extended Status bits layout
+	 *              --------------------------------------------------------
+	 *   RDES4      |                 Extended Status                      |
+	 *              --------------------------------------------------------
+	 */
+	DESC_RX_TS_DROPPED = 0x00004000,	/* PTP snapshot available */
+	DESC_RX_PTP_VER = 0x00002000,		/* When set indicates IEEE1584
+						   Version 2 (else Ver1) */
+	DESC_RX_PTP_FRAME_TYPE = 0x00001000,	/* PTP frame type Indicates PTP
+						   sent over ethernet */
+	DESC_RX_PTP_MESSAGE_TYPE = 0x00000F00,	/* Message Type */
+	DESC_RX_PTP_NO = 0x00000000,		/* 0000 => No PTP message rcvd */
+	DESC_RX_PTP_SYNC = 0x00000100,		/* 0001 => Sync (all clock
+						   types) received */
+	DESC_RX_PTP_FOLLOW_UP = 0x00000200,	/* 0010 => Follow_Up (all clock
+						   types) received */
+	DESC_RX_PTP_DELAY_REQ = 0x00000300,	/* 0011 => Delay_Req (all clock
+						   types) received */
+	DESC_RX_PTP_DELAY_RESP = 0x00000400,	/* 0100 => Delay_Resp (all clock
+						   types) received */
+	DESC_RX_PTP_PDELAY_REQ = 0x00000500,	/* 0101 => Pdelay_Req (in P
+						   to P tras clk)  or Announce
+						   in Ord and Bound clk */
+	DESC_RX_PTP_PDELAY_RESP = 0x00000600,	/* 0110 => Pdealy_Resp(in P to
+						   P trans clk) or Management in
+						   Ord and Bound clk */
+	DESC_RX_PTP_PDELAY_RESP_FP = 0x00000700,/* 0111 => Pdelay_Resp_Follow_Up
+						   (in P to P trans clk) or
+						   Signaling in Ord and Bound
+						   clk */
+	DESC_RX_PTP_IPV6 = 0x00000080,		/* Received Packet is in IPV6 */
+	DESC_RX_PTP_IPV4 = 0x00000040,		/* Received Packet is in IPV4 */
+	DESC_RX_CHK_SUM_BYPASS = 0x00000020,	/* When set indicates checksum
+						   offload engine is bypassed */
+	DESC_RX_IP_PAYLOAD_ERROR = 0x00000010,	/* When set indicates 16bit IP
+						   payload CS is in error */
+	DESC_RX_IP_HEADER_ERROR = 0x00000008,	/* When set indicates 16bit IPV4
+						   hdr CS is err or IP datagram
+						   version is not consistent
+						   with Ethernet type value */
+	DESC_RX_IP_PAYLOAD_TYPE = 0x00000007,	/* Indicate the type of payload
+						   encapsulated in IPdatagram
+						   processed by COE (Rx) */
+	DESC_RX_IP_PAYLOAD_UNKNOWN = 0x00000000,/* Unknown or didnot process
+						   IP payload */
+	DESC_RX_IP_PAYLOAD_UDP = 0x00000001,	/* UDP */
+	DESC_RX_IP_PAYLOAD_TCP = 0x00000002,	/* TCP */
+	DESC_RX_IP_PAYLOAD_ICMP = 0x00000003,	/* ICMP */
+};
+
+/*
+ * dma_desc_rx
+ *	Rx DMA Descriptor Structure
+ *
+ * Enhanced descriptor format for receive.
+ */
+struct dma_desc_rx {
+	uint32_t status;	/* Status */
+	uint32_t length;	/* Buffer 1  and Buffer 2 length */
+	uint32_t buffer1;	/* Network Buffer 1 pointer (DMA-able) */
+	uint32_t buffer2;	/* Network Buffer 2 pointer (DMA-able) */
+	/* This data below is used only by driver */
+	uint32_t extstatus;	/* Extended status of a Rx Descriptor */
+	uint32_t reserved1;	/* Reserved word */
+	uint32_t timestamplow;	/* Lower 32 bits of the 64
+				   bit timestamp value */
+	uint32_t timestamphigh;	/* Higher 32 bits of the 64
+					   bit timestamp value */
+	uint32_t padding[8];	/* Pad 32 byte to align to 64B cacheline size */
+};
+
+/*
+ * dma_desc_tx
+ *	Tx DMA Descriptor Structure
+ *
+ * Enhanced descriptor format for transmit.
+ */
+struct dma_desc_tx {
+	uint32_t status;	/* Status */
+	uint32_t length;	/* Buffer 1  and Buffer 2 length */
+	uint32_t buffer1;	/* Network Buffer 1 pointer (DMA-able) */
+	uint32_t buffer2;	/* Network Buffer 2 pointer (DMA-able) */
+	uint32_t reserved1;	/* Reserved word */
+	uint32_t reserved2;	/* Reserved word */
+	uint32_t timestamplow;	/* Lower 32 bits of the 64
+				   bit timestamp value */
+	uint32_t timestamphigh;	/* Higher 32 bits of the 64
+					   bit timestamp value */
+	uint32_t padding[8];	/* Pad 32 byte to align to 64B cacheline size */
+};
+
+/*
+ * syn_dp_gmac_tx_checksum_offload_tcp_pseudo()
+ *	The checksum offload engine is enabled to do complete checksum computation.
+ */
+static inline void syn_dp_gmac_tx_checksum_offload_tcp_pseudo(struct dma_desc_tx *desc)
+{
+	desc->status = ((desc->status & (~DESC_TX_CIS_MASK)) | DESC_TX_CIS_TCP_PSEUDO_CS);
+}
+
+/*
+ * syn_dp_gmac_tx_desc_init_ring()
+ *	Initialize the tx descriptors for ring mode operation.
+ */
+static inline void syn_dp_gmac_tx_desc_init_ring(struct dma_desc_tx *desc, uint32_t no_of_desc)
+{
+	struct dma_desc_tx *last_desc = desc + no_of_desc - 1;
+	memset(desc, 0, no_of_desc * sizeof(struct dma_desc_tx));
+	last_desc->status = DESC_TX_DESC_END_OF_RING;
+}
+
+/*
+ * syn_dp_gmac_rx_desc_init_ring()
+ *	Initialize the rx descriptors for ring mode operation.
+ */
+static inline void syn_dp_gmac_rx_desc_init_ring(struct dma_desc_rx *desc, uint32_t no_of_desc)
+{
+	struct dma_desc_rx *last_desc = desc + no_of_desc - 1;
+	memset(desc, 0, no_of_desc * sizeof(struct dma_desc_rx));
+	last_desc->length = DESC_RX_DESC_END_OF_RING;
+}
+
+/*
+ * syn_dp_gmac_is_rx_desc_linear_and_valid()
+ *	Checks whether the rx descriptor is linear and valid.
+ */
+static inline bool syn_dp_gmac_is_rx_desc_linear_and_valid(uint32_t status, uint32_t extstatus)
+{
+	return (((status & (DESC_RX_ERROR | DESC_RX_FIRST | DESC_RX_LAST)) == (DESC_RX_FIRST | DESC_RX_LAST)) &&
+		!(extstatus & (DESC_RX_IP_HEADER_ERROR | DESC_RX_IP_PAYLOAD_ERROR)));
+}
+
+/*
+ * syn_dp_gmac_is_rx_desc_valid()
+ * 	Check if Rx descriptor is valid with no error.
+ */
+static inline bool syn_dp_gmac_is_rx_desc_valid(uint32_t status, uint32_t extstatus)
+{
+	return (!(status & DESC_RX_ERROR) && !(extstatus & (DESC_RX_IP_HEADER_ERROR | DESC_RX_IP_PAYLOAD_ERROR)));
+}
+
+/*
+ * syn_dp_gmac_get_rx_desc_frame_length()
+ *	Returns the byte length of received frame including CRC.
+ */
+static inline uint32_t syn_dp_gmac_get_rx_desc_frame_length(uint32_t status)
+{
+	return (status & DESC_RX_FRAME_LENGTH_MASK) >> DESC_RX_FRAME_LENGTH_SHIFT;
+}
+
+/*
+ * syn_dp_gmac_is_rx_desc_owned_by_dma()
+ *	Checks whether the Rx descriptor is owned by DMA.
+ */
+static inline bool syn_dp_gmac_is_rx_desc_owned_by_dma(uint32_t status)
+{
+	return (status & DESC_OWN_BY_DMA) == DESC_OWN_BY_DMA;
+}
+
+/*
+ * syn_dp_gmac_is_tx_desc_owned_by_dma()
+ *	Checks whether the Tx descriptor is owned by DMA.
+ */
+static inline bool syn_dp_gmac_is_tx_desc_owned_by_dma(uint32_t status)
+{
+	return (status & DESC_OWN_BY_DMA) == DESC_OWN_BY_DMA;
+}
+
+/*
+ * syn_dp_gmac_is_rx_desc_empty()
+ *	Checks whether the descriptor is empty.
+ */
+static inline bool syn_dp_gmac_is_rx_desc_empty(struct dma_desc_rx *desc)
+{
+	/*
+	 * If length of both buffer1 & buffer2 are zero then desc is empty
+	 */
+	return (desc->length & DESC_SIZE1_MASK) == 0;
+}
+
+/*
+ * syn_dp_gmac_is_tx_desc_empty()
+ *	Checks whether the descriptor is empty.
+ */
+static inline bool syn_dp_gmac_is_tx_desc_empty(struct dma_desc_tx *desc)
+{
+	/*
+	 * If length of both buffer1 & buffer2 are zero then desc is empty
+	 */
+	return (desc->length & DESC_SIZE1_MASK) == 0;
+}
+
+/*
+ * syn_dp_gmac_get_tx_collision_count()
+ *	Gives the transmission collision count.
+ */
+static inline uint32_t syn_dp_gmac_get_tx_collision_count(uint32_t status)
+{
+	return (status & DESC_TX_COLL_MASK) >> DESC_TX_COLL_SHIFT;
+}
+
+#endif /*  __SYN_DMA_DESC__ */
diff --git a/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dma_reg.h b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dma_reg.h
new file mode 100644
index 0000000..79345a7
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dma_reg.h
@@ -0,0 +1,588 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __SYN_DMA_REG_H__
+#define __SYN_DMA_REG_H__
+
+/*
+ * DMA Register offset
+ */
+#define SYN_DMA_BUS_MODE				0x1000
+#define SYN_DMA_TX_POLL_DEMAND				0x1004
+#define SYN_DMA_RX_POLL_DEMAND				0x1008
+#define SYN_DMA_RX_DESCRIPTOR_LIST_ADDRESS		0x100C
+#define SYN_DMA_TX_DESCRIPTOR_LIST_ADDRESS		0x1010
+#define SYN_DMA_STATUS					0x1014
+#define SYN_DMA_OPERATION_MODE				0x1018
+#define SYN_DMA_INT_ENABLE				0x101C
+#define SYN_DMA_MISSED_FRAME_AND_BUFF_OVERFLOW_COUNTER	0x1020
+#define SYN_DMA_RX_INTERRUPT_WATCHDOG_TIMER		0x1024
+#define SYN_DMA_AXI_BUS_MODE				0x1028
+#define SYN_DMA_AHB_OR_AXI_STATUS			0x102C
+#define SYN_DMA_CURRENT_HOST_TX_DESCRIPTOR		0x1048
+#define SYN_DMA_CURRENT_HOST_RX_DESCRIPTOR		0x104C
+#define SYN_DMA_CURRENT_HOST_TX_BUFFER_ADDRESS		0x1050
+#define SYN_DMA_CURRENT_HOST_RX_BUFFER_ADDRESS		0x1054
+
+/*
+ * SYN_DMA_BUS_MODE = 0x0000,		CSR0 - Bus Mode
+ */
+enum syn_dma_bus_mode_reg {
+	SYN_DMA_FIXED_BURST_ENABLE = 0x00010000,	/* (FB)Fixed Burst SINGLE, INCR4,
+							   INCR8 or INCR16 */
+	SYN_DMA_FIXED_BURST_DISABLE = 0x00000000,	/* SINGLE, INCR */
+	SYN_DMA_TX_PRIORITY_RATIO11 = 0x00000000,	/* (PR)TX:RX DMA priority ratio 1:1 */
+	SYN_DMA_TX_PRIORITY_RATIO21 = 0x00004000,	/* (PR)TX:RX DMA priority ratio 2:1 */
+	SYN_DMA_TX_PRIORITY_RATIO31 = 0x00008000,	/* (PR)TX:RX DMA priority ratio 3:1 */
+	SYN_DMA_TX_PRIORITY_RATIO41 = 0x0000C000,	/* (PR)TX:RX DMA priority ratio 4:1 */
+	SYN_DMA_ADDRESS_ALIGNED_BEATS = 0x02000000,	/* Address Aligned beats */
+	SYN_DMA_BURST_LENGTHX8 = 0x01000000,		/* When set mutiplies the PBL by 8 */
+	SYN_DMA_BURST_LENGTH256 = 0x01002000,		/* (dma_burst_lengthx8 |
+							   dma_burst_length32) = 256 */
+	SYN_DMA_BURST_LENGTH128 = 0x01001000,		/* (dma_burst_lengthx8 |
+							   dma_burst_length16) = 128 */
+	SYN_DMA_BURST_LENGTH64 = 0x01000800,		/* (dma_burst_lengthx8 |
+							   dma_burst_length8) = 64 */
+	/* (PBL) programmable burst length */
+	SYN_DMA_BURST_LENGTH32 = 0x00002000,		/* Dma burst length = 32 */
+	SYN_DMA_BURST_LENGTH16 = 0x00001000,		/* Dma burst length = 16 */
+	SYN_DMA_BURST_LENGTH8 = 0x00000800,		/* Dma burst length = 8 */
+	SYN_DMA_BURST_LENGTH4 = 0x00000400,		/* Dma burst length = 4 */
+	SYN_DMA_BURST_LENGTH2 = 0x00000200,		/* Dma burst length = 2 */
+	SYN_DMA_BURST_LENGTH1 = 0x00000100,		/* Dma burst length = 1 */
+	SYN_DMA_BURST_LENGTH0 = 0x00000000,		/* Dma burst length = 0 */
+
+	SYN_DMA_DESCRIPTOR8_WORDS = 0x00000080,		/* Enh Descriptor works  1=>
+							   8 word descriptor */
+	SYN_DMA_DESCRIPTOR4_WORDS = 0x00000000,		/* Enh Descriptor works  0=>
+							   4 word descriptor */
+	SYN_DMA_DESCRIPTOR_SKIP16 = 0x00000040,		/* (DSL)Descriptor skip length (no.of dwords) */
+	SYN_DMA_DESCRIPTOR_SKIP8 = 0x00000020,		/* between two unchained descriptors */
+	SYN_DMA_DESCRIPTOR_SKIP4 = 0x00000010,
+	SYN_DMA_DESCRIPTOR_SKIP2 = 0x00000008,
+	SYN_DMA_DESCRIPTOR_SKIP1 = 0x00000004,
+	SYN_DMA_DESCRIPTOR_SKIP0 = 0x00000000,
+	SYN_DMA_ARBIT_RR = 0x00000000,			/* (DA) DMA RR arbitration */
+	SYN_DMA_ARBIT_PR = 0x00000002,			/* Rx has priority over Tx */
+	SYN_DMA_RESET_ON = 0x00000001,			/* (SWR)Software Reset DMA engine */
+	SYN_DMA_RESET_OFF = 0x00000000,
+};
+
+/*
+ * SYN_DMA_STATUS = 0x0014,		CSR5 - Dma status Register
+ */
+enum syn_dma_status_reg {
+	SYN_DMA_GMAC_PMT_INTR = 0x10000000,		/* (GPI)Gmac subsystem interrupt */
+	SYN_DMA_GMAC_MMC_INTR = 0x08000000,		/* (GMI)Gmac MMC subsystem interrupt */
+	SYN_DMA_GMAC_LINE_INTF_INTR = 0x04000000,	/* Line interface interrupt */
+	SYN_DMA_ERROR_BIT2 = 0x02000000,		/* (EB)Error bits 0-data buffer, 1-desc access */
+	SYN_DMA_ERROR_BIT1 = 0x01000000,		/* (EB)Error bits 0-write trnsf, 1-read transfer */
+	SYN_DMA_ERROR_BIT0 = 0x00800000,		/* (EB)Error bits 0-Rx DMA, 1-Tx DMA */
+	SYN_DMA_TX_STATE = 0x00700000,			/* (TS)Transmit process state */
+	SYN_DMA_TX_STOPPED = 0x00000000,		/* Stopped - Reset or Stop Tx Command issued */
+	SYN_DMA_TX_FETCHING = 0x00100000,		/* Running - fetching the Tx descriptor */
+	SYN_DMA_TX_WAITING = 0x00200000,		/* Running - waiting for status */
+	SYN_DMA_TX_READING = 0x00300000,		/* Running - reading the data from host memory */
+	SYN_DMA_TX_SUSPENDED = 0x00600000,		/* Suspended - Tx Descriptor unavailabe */
+	SYN_DMA_TX_CLOSING = 0x00700000,		/* Running - closing Rx descriptor */
+	SYN_DMA_RX_STATE = 0x000E0000,			/* (RS)Receive process state */
+	SYN_DMA_RX_STOPPED = 0x00000000,		/* Stopped - Reset or Stop Rx Command issued */
+	SYN_DMA_RX_FETCHING = 0x00020000,		/* Running - fetching the Rx descriptor */
+	SYN_DMA_RX_WAITING = 0x00060000,		/* Running - waiting for packet */
+	SYN_DMA_RX_SUSPENDED = 0x00080000,		/* Suspended - Rx Descriptor unavailable */
+	SYN_DMA_RX_CLOSING = 0x000A0000,		/* Running - closing descriptor */
+	SYN_DMA_RX_QUEUING = 0x000E0000,		/* Running - queuing the receive frame into host memory */
+	SYN_DMA_INT_NORMAL = 0x00010000,		/* (NIS)Normal interrupt summary */
+	SYN_DMA_INT_ABNORMAL = 0x00008000,		/* (AIS)Abnormal interrupt summary */
+	SYN_DMA_INT_EARLY_RX = 0x00004000,		/* Early receive interrupt (Normal) */
+	SYN_DMA_INT_BUS_ERROR = 0x00002000,		/* Fatal bus error (Abnormal) */
+	SYN_DMA_INT_EARLY_TX = 0x00000400,		/* Early transmit interrupt (Abnormal) */
+	SYN_DMA_INT_RX_WDOG_TO = 0x00000200,		/* Receive Watchdog Timeout (Abnormal) */
+	SYN_DMA_INT_RX_STOPPED = 0x00000100,		/* Receive process stopped (Abnormal) */
+	SYN_DMA_INT_RX_NO_BUFFER = 0x00000080,		/* RX buffer unavailable (Abnormal) */
+	SYN_DMA_INT_RX_COMPLETED = 0x00000040,		/* Completion of frame RX (Normal) */
+	SYN_DMA_INT_TX_UNDERFLOW = 0x00000020,		/* Transmit underflow (Abnormal) */
+	SYN_DMA_INT_RCV_OVERFLOW = 0x00000010,		/* RX Buffer overflow interrupt */
+	SYN_DMA_INT_TX_JABBER_TO = 0x00000008,		/* TX Jabber Timeout (Abnormal) */
+	SYN_DMA_INT_TX_NO_BUFFER = 0x00000004,		/* TX buffer unavailable (Normal) */
+	SYN_DMA_INT_TX_STOPPED = 0x00000002,		/* TX process stopped (Abnormal) */
+	SYN_DMA_INT_TX_COMPLETED = 0x00000001,		/* Transmit completed (Normal) */
+};
+
+/*
+ * SYN_DMA_OPERATION_MODE = 0x0018,		CSR6 - Dma Operation Mode Register
+ */
+enum syn_dma_operation_mode_reg {
+	SYN_DMA_DISABLE_DROP_TCP_CS = 0x04000000,	/* (DT) Dis. drop. of tcp/ip
+							   CS error frames */
+	SYN_DMA_RX_STORE_AND_FORWARD = 0x02000000,	/* Rx (SF)Store and forward */
+	SYN_DMA_RX_FRAME_FLUSH = 0x01000000,		/* Disable Receive Frame Flush */
+	SYN_DMA_TX_STORE_AND_FORWARD = 0x00200000,	/* Tx (SF)Store and forward */
+	SYN_DMA_FLUSH_TX_FIFO = 0x00100000,		/* (FTF)Tx FIFO controller
+							   is reset to default */
+	SYN_DMA_TX_THRESH_CTRL = 0x0001C000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo */
+	SYN_DMA_TX_THRESH_CTRL16 = 0x0001C000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 16 */
+	SYN_DMA_TX_THRESH_CTRL24 = 0x00018000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 24 */
+	SYN_DMA_TX_THRESH_CTRL32 = 0x00014000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 32 */
+	SYN_DMA_TX_THRESH_CTRL40 = 0x00010000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 40 */
+	SYN_DMA_TX_THRESH_CTRL256 = 0x0000c000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 256 */
+	SYN_DMA_TX_THRESH_CTRL192 = 0x00008000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 192 */
+	SYN_DMA_TX_THRESH_CTRL128 = 0x00004000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 128 */
+	SYN_DMA_TX_THRESH_CTRL64 = 0x00000000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 64 */
+	SYN_DMA_TX_START = 0x00002000,			/* (ST)Start/Stop transmission */
+	SYN_DMA_RX_FLOW_CTRL_DEACT = 0x00401800,	/* (RFD)Rx flow control
+							   deact. Threshold */
+	SYN_DMA_RX_FLOW_CTRL_DEACT1K = 0x00000000,	/* (RFD)Rx flow control
+							   deact. Threshold (1kbytes) */
+	SYN_DMA_RX_FLOW_CTRL_DEACT2K = 0x00000800,	/* (RFD)Rx flow control
+							   deact. Threshold (2kbytes) */
+	SYN_DMA_RX_FLOW_CTRL_DEACT3K = 0x00001000,	/* (RFD)Rx flow control
+							   deact. Threshold (3kbytes) */
+	SYN_DMA_RX_FLOW_CTRL_DEACT4K = 0x00001800,	/* (RFD)Rx flow control
+							   deact. Threshold (4kbytes) */
+	SYN_DMA_RX_FLOW_CTRL_DEACT5K = 0x00400000,	/* (RFD)Rx flow control
+							   deact. Threshold (4kbytes) */
+	SYN_DMA_RX_FLOW_CTRL_DEACT6K = 0x00400800,	/* (RFD)Rx flow control
+							   deact. Threshold (4kbytes) */
+	SYN_DMA_RX_FLOW_CTRL_DEACT7K = 0x00401000,	/* (RFD)Rx flow control
+							   deact. Threshold (4kbytes) */
+	SYN_DMA_RX_FLOW_CTRL_ACT = 0x00800600,		/* (RFA)Rx flow control
+							   Act. Threshold */
+	SYN_DMA_RX_FLOW_CTRL_ACT1K = 0x00000000,	/* (RFA)Rx flow control
+							   Act. Threshold (1kbytes) */
+	SYN_DMA_RX_FLOW_CTRL_ACT2K = 0x00000200,	/* (RFA)Rx flow control
+							   Act. Threshold (2kbytes) */
+	SYN_DMA_RX_FLOW_CTRL_ACT3K = 0x00000400,	/* (RFA)Rx flow control
+							   Act. Threshold (3kbytes) */
+	SYN_DMA_RX_FLOW_CTRL_ACT4K = 0x00000600,	/* (RFA)Rx flow control
+							   Act. Threshold (4kbytes) */
+	SYN_DMA_RX_FLOW_CTRL_ACT5K = 0x00800000,	/* (RFA)Rx flow control
+							   Act. Threshold (5kbytes) */
+	SYN_DMA_RX_FLOW_CTRL_ACT6K = 0x00800200,	/* (RFA)Rx flow control
+							   Act. Threshold (6kbytes) */
+	SYN_DMA_RX_FLOW_CTRL_ACT7K = 0x00800400,	/* (RFA)Rx flow control
+							   Act. Threshold (7kbytes) */
+	SYN_DMA_RX_THRESH_CTRL = 0x00000018,		/* (RTC)Controls thre
+							   Thresh of MTL rx Fifo */
+	SYN_DMA_RX_THRESH_CTRL64 = 0x00000000,		/* (RTC)Controls thre
+							   Thresh of MTL tx Fifo 64 */
+	SYN_DMA_RX_THRESH_CTRL32 = 0x00000008,		/* (RTC)Controls thre
+							   Thresh of MTL tx Fifo 32 */
+	SYN_DMA_RX_THRESH_CTRL96 = 0x00000010,		/* (RTC)Controls thre
+							   Thresh of MTL tx Fifo 96 */
+	SYN_DMA_RX_THRESH_CTRL128 = 0x00000018,		/* (RTC)Controls thre
+							   Thresh of MTL tx Fifo 128 */
+	SYN_DMA_EN_HW_FLOW_CTRL = 0x00000100,		/* (EFC)Enable HW flow control */
+	SYN_DMA_DIS_HW_FLOW_CTRL = 0x00000000,		/* Disable HW flow control */
+	SYN_DMA_FWD_ERROR_FRAMES = 0x00000080,		/* (FEF)Forward error frames */
+	SYN_DMA_FWD_UNDER_SZ_FRAMES = 0x00000040,	/* (FUF)Forward undersize
+							   frames */
+	SYN_DMA_TX_SECOND_FRAME = 0x00000004,		/* (OSF)Operate on 2nd frame */
+	SYN_DMA_RX_START = 0x00000002,			/* (SR)Start/Stop reception */
+};
+
+/*
+ * SYN_DMA_INT_ENABLE = 0x101C,		CSR7 - Interrupt enable Register Layout
+ */
+enum syn_dma_interrupt_reg {
+	SYN_DMA_IE_NORMAL = SYN_DMA_INT_NORMAL,		/* Normal interrupt enable */
+	SYN_DMA_IE_ABNORMAL = SYN_DMA_INT_ABNORMAL,	/* Abnormal interrupt enable */
+	SYN_DMA_IE_EARLY_RX = SYN_DMA_INT_EARLY_RX,	/* Early RX interrupt enable */
+	SYN_DMA_IE_BUS_ERROR = SYN_DMA_INT_BUS_ERROR,	/* Fatal bus error enable */
+	SYN_DMA_IE_EARLY_TX = SYN_DMA_INT_EARLY_TX,	/* Early TX interrupt enable */
+	SYN_DMA_IE_RX_WDOG_TO = SYN_DMA_INT_RX_WDOG_TO,	/* RX Watchdog Timeout enable */
+	SYN_DMA_IE_RX_STOPPED = SYN_DMA_INT_RX_STOPPED,	/* RX process stopped enable */
+	SYN_DMA_IE_RX_NO_BUFFER = SYN_DMA_INT_RX_NO_BUFFER,
+							/* Receive buffer unavailable enable */
+	SYN_DMA_IE_RX_COMPLETED = SYN_DMA_INT_RX_COMPLETED,
+							/* Completion of frame reception enable */
+	SYN_DMA_IE_TX_UNDERFLOW = SYN_DMA_INT_TX_UNDERFLOW,
+							/* TX underflow enable */
+	SYN_DMA_IE_RX_OVERFLOW = SYN_DMA_INT_RCV_OVERFLOW,
+							/* RX Buffer overflow interrupt */
+	SYN_DMA_IE_TX_JABBER_TO = SYN_DMA_INT_TX_JABBER_TO,
+							/* TX Jabber Timeout enable */
+	SYN_DMA_IE_TX_NO_BUFFER = SYN_DMA_INT_TX_NO_BUFFER,
+							/* TX buffer unavailable enable */
+	SYN_DMA_IE_TX_STOPPED = SYN_DMA_INT_TX_STOPPED,
+							/* TX process stopped enable */
+	SYN_DMA_IE_TX_COMPLETED = SYN_DMA_INT_TX_COMPLETED,
+							/* TX completed enable */
+};
+
+/*
+ * SYN_DMA_AXI_BUS_MODE = 0x1028
+ */
+enum syn_dma_axi_bus_mode_reg {
+	SYN_DMA_EN_LPI = 0x80000000,
+	SYN_DMA_LPI_XIT_FRM = 0x40000000,
+	SYN_DMA_WR_OSR_NUM_REQS16 = 0x00F00000,
+	SYN_DMA_WR_OSR_NUM_REQS8 = 0x00700000,
+	SYN_DMA_WR_OSR_NUM_REQS4 = 0x00300000,
+	SYN_DMA_WR_OSR_NUM_REQS2 = 0x00100000,
+	SYN_DMA_WR_OSR_NUM_REQS1 = 0x00000000,
+	SYN_DMA_RD_OSR_NUM_REQS16 = 0x000F0000,
+	SYN_DMA_RD_OSR_NUM_REQS8 = 0x00070000,
+	SYN_DMA_RD_OSR_NUM_REQS4 = 0x00030000,
+	SYN_DMA_RD_OSR_NUM_REQS2 = 0x00010000,
+	SYN_DMA_RD_OSR_NUM_REQS1 = 0x00000000,
+	SYN_DMA_ONEKBBE = 0x00002000,
+	SYN_DMA_AXI_AAL = 0x00001000,
+	SYN_DMA_AXI_BLEN256 = 0x00000080,
+	SYN_DMA_AXI_BLEN128 = 0x00000040,
+	SYN_DMA_AXI_BLEN64 = 0x00000020,
+	SYN_DMA_AXI_BLEN32 = 0x00000010,
+	SYN_DMA_AXI_BLEN16 = 0x00000008,
+	SYN_DMA_AXI_BLEN8 = 0x00000004,
+	SYN_DMA_AXI_BLEN4 = 0x00000002,
+	SYN_DMA_UNDEFINED = 0x00000001,
+};
+
+/*
+ * SYN_DMA_MISSED_FRAME_AND_BUFF_OVERFLOW_COUNTER = 0x1020
+ */
+enum syn_dma_missed_and_buffer_overflow_cnt_reg {
+	SYN_DMA_FIFO_OVERFLOW_SHIFT = 17,
+	SYN_DMA_FIFO_OVERFLOW_MASK = 0x7FF,
+	SYN_DMA_RX_MISSED_MASK = 0xFFFF,
+};
+
+/*
+ * Values to initialize DMA registers
+ */
+enum syn_dma_init_values {
+	SYN_DMA_INT_ERROR_MASK = SYN_DMA_INT_BUS_ERROR,		/* Error */
+	SYN_DMA_INT_RX_ABN_MASK = SYN_DMA_INT_RX_NO_BUFFER,	/* RX abnormal intr */
+	SYN_DMA_INT_RX_NORM_MASK = SYN_DMA_INT_RX_COMPLETED,	/* RXnormal intr */
+	SYN_DMA_INT_RX_STOPPED_MASK = SYN_DMA_INT_RX_STOPPED,	/* RXstopped */
+	SYN_DMA_INT_TX_ABN_MASK = SYN_DMA_INT_TX_UNDERFLOW,	/* TX abnormal intr */
+	SYN_DMA_INT_TX_NORM_MASK = SYN_DMA_INT_TX_COMPLETED,	/* TX normal intr */
+	SYN_DMA_INT_TX_STOPPED_MASK = SYN_DMA_INT_TX_STOPPED,	/* TX stopped */
+
+	SYN_DMA_BUS_MODE_INIT = SYN_DMA_FIXED_BURST_ENABLE | SYN_DMA_BURST_LENGTH8
+		| SYN_DMA_DESCRIPTOR_SKIP2 | SYN_DMA_RESET_OFF,
+
+	SYN_DMA_BUS_MODE_VAL_CLSIZE_64B = SYN_DMA_BURST_LENGTH32
+		| SYN_DMA_BURST_LENGTHX8 | SYN_DMA_DESCRIPTOR_SKIP4
+		| SYN_DMA_DESCRIPTOR8_WORDS | SYN_DMA_ARBIT_PR | SYN_DMA_ADDRESS_ALIGNED_BEATS,
+
+	SYN_DMA_OMR = SYN_DMA_TX_STORE_AND_FORWARD | SYN_DMA_RX_STORE_AND_FORWARD
+		| SYN_DMA_RX_THRESH_CTRL128 | SYN_DMA_TX_SECOND_FRAME,
+
+	SYN_DMA_INT_EN = SYN_DMA_INT_NORMAL
+		| SYN_DMA_INT_ABNORMAL | SYN_DMA_INT_BUS_ERROR
+		| SYN_DMA_INT_RX_NO_BUFFER | SYN_DMA_INT_RX_COMPLETED
+		| SYN_DMA_INT_RX_STOPPED | SYN_DMA_INT_TX_UNDERFLOW
+		| SYN_DMA_INT_TX_COMPLETED | SYN_DMA_INT_TX_STOPPED,
+
+	SYN_DMA_RX_INT_EN = SYN_DMA_INT_RX_NO_BUFFER | SYN_DMA_INT_RX_COMPLETED
+		| SYN_DMA_INT_RX_STOPPED,
+
+	SYN_DMA_TX_INT_EN = SYN_DMA_INT_TX_UNDERFLOW
+		| SYN_DMA_INT_TX_COMPLETED | SYN_DMA_INT_TX_STOPPED,
+
+	SYN_DMA_INT_DISABLE = 0,
+
+	SYN_DMA_AXI_BUS_MODE_VAL = SYN_DMA_AXI_BLEN16 | SYN_DMA_RD_OSR_NUM_REQS8
+		| SYN_DMA_WR_OSR_NUM_REQS8,
+
+	SYN_DMA_BUS_MODE_VAL_CLSIZE_32B = SYN_DMA_BURST_LENGTH32
+		| SYN_DMA_BURST_LENGTHX8 | SYN_DMA_DESCRIPTOR_SKIP0
+		| SYN_DMA_DESCRIPTOR8_WORDS | SYN_DMA_ARBIT_PR | SYN_DMA_ADDRESS_ALIGNED_BEATS,
+
+};
+
+/*
+ * syn_dma_bus_mode_init_clsize_64byte()
+ *	Function to program DMA bus mode register to access cached descriptors.
+ */
+static inline void syn_dma_bus_mode_init_clsize_64byte(void __iomem *mac_base)
+{
+	hal_write_reg(mac_base, SYN_DMA_BUS_MODE, SYN_DMA_BUS_MODE_VAL_CLSIZE_64B);
+}
+
+/*
+ * syn_dma_bus_mode_init_clsize_32byte()
+ *	Function to program DMA bus mode register to access uncached descriptors..
+ */
+static inline void syn_dma_bus_mode_init_clsize_32byte(void __iomem *mac_base)
+{
+	hal_write_reg(mac_base, SYN_DMA_BUS_MODE, SYN_DMA_BUS_MODE_VAL_CLSIZE_32B);
+}
+
+/*
+ * syn_dma_axi_bus_mode_init()
+ *	Function to program DMA AXI bus mode register.
+ */
+static inline void syn_dma_axi_bus_mode_init(void __iomem *mac_base)
+{
+	hal_write_reg(mac_base, SYN_DMA_AXI_BUS_MODE, SYN_DMA_AXI_BUS_MODE_VAL);
+}
+
+/*
+ * syn_dma_operation_mode_init()
+ *	Function to program DMA Operation Mode register.
+ */
+static inline void syn_dma_operation_mode_init(void __iomem *mac_base)
+{
+	hal_write_reg(mac_base, SYN_DMA_OPERATION_MODE, SYN_DMA_OMR);
+}
+
+/*
+ * syn_dma_init()
+ *	Initialize settings for GMAC DMA and AXI bus.
+ */
+static inline void syn_dma_init(void __iomem *mac_base)
+{
+	syn_dma_bus_mode_init_clsize_64byte(mac_base);
+	syn_dma_axi_bus_mode_init(mac_base);
+	syn_dma_operation_mode_init(mac_base);
+}
+
+/*
+ * syn_rx_tcpip_chksum_drop_enable()
+ *	Instruct the DMA to drop the packets that fail TCP/IP checksum.
+ *
+ * This is to instruct the receive DMA engine to drop the recevied
+ * packet if they fails the tcp/ip checksum in hardware. Valid only when
+ * full checksum offloading is enabled(type-2).
+ */
+static inline void syn_rx_tcpip_chksum_drop_enable(void __iomem *mac_base)
+{
+	uint32_t data;
+
+	data = ~(SYN_DMA_DISABLE_DROP_TCP_CS) & hal_read_reg(mac_base, SYN_DMA_OPERATION_MODE);
+	hal_write_reg(mac_base, SYN_DMA_OPERATION_MODE, data);
+}
+
+/*
+ * syn_init_rx_desc_base()
+ *	Programs the Rx Dma base address with the starting address of the descriptor ring or chain.
+ */
+static inline void syn_init_rx_desc_base(void __iomem *mac_base, uint32_t desc_dma)
+{
+	hal_write_reg(mac_base, SYN_DMA_RX_DESCRIPTOR_LIST_ADDRESS, desc_dma);
+}
+
+/*
+ * syn_init_tx_desc_base()
+ *	Programs the Tx Dma base address with the starting address of the descriptor ring or chain.
+ */
+static inline void syn_init_tx_desc_base(void __iomem *mac_base, uint32_t desc_dma)
+{
+	hal_write_reg(mac_base, SYN_DMA_TX_DESCRIPTOR_LIST_ADDRESS, desc_dma);
+}
+
+/*
+ * syn_enable_dma_tx()
+ *	Enable Rx GMAC operation
+ */
+static inline void syn_enable_dma_tx(void __iomem *mac_base)
+{
+	uint32_t data;
+
+	data = hal_read_reg(mac_base, SYN_DMA_OPERATION_MODE);
+	data |= SYN_DMA_TX_START;
+	hal_write_reg(mac_base, SYN_DMA_OPERATION_MODE, data);
+}
+
+/*
+ * syn_disable_dma_tx()
+ *	Disable Rx GMAC operation
+ */
+static inline void syn_disable_dma_tx(void __iomem *mac_base)
+{
+	uint32_t data;
+
+	data = hal_read_reg(mac_base, SYN_DMA_OPERATION_MODE);
+	data &= ~SYN_DMA_TX_START;
+	hal_write_reg(mac_base, SYN_DMA_OPERATION_MODE, data);
+}
+
+/*
+ * syn_enable_dma_rx()
+ *	Enable Rx GMAC operation
+ */
+static inline void syn_enable_dma_rx(void __iomem *mac_base)
+{
+	uint32_t data;
+
+	data = hal_read_reg(mac_base, SYN_DMA_OPERATION_MODE);
+	data |= SYN_DMA_RX_START;
+	hal_write_reg(mac_base, SYN_DMA_OPERATION_MODE, data);
+}
+
+/*
+ * syn_disable_dma_rx()
+ *	Disable Rx GMAC operation
+ */
+static inline void syn_disable_dma_rx(void __iomem *mac_base)
+{
+	uint32_t data;
+
+	data = hal_read_reg(mac_base, SYN_DMA_OPERATION_MODE);
+	data &= ~SYN_DMA_RX_START;
+	hal_write_reg(mac_base, SYN_DMA_OPERATION_MODE, data);
+}
+
+/*
+ * syn_enable_tx_dma_interrupt()
+ *	Enables Rx DMA interrupts.
+ */
+static inline void syn_enable_tx_dma_interrupt(void __iomem *mac_base)
+{
+	uint32_t data;
+
+	data = SYN_DMA_INT_TX_COMPLETED | hal_read_relaxed_reg(mac_base, SYN_DMA_INT_ENABLE);
+	hal_write_relaxed_reg(mac_base, SYN_DMA_INT_ENABLE, data);
+}
+
+/*
+ * syn_enable_rx_dma_interrupt()
+ *	Enables Rx DMA interrupts.
+ */
+static inline void syn_enable_rx_dma_interrupt(void __iomem *mac_base)
+{
+	uint32_t data;
+
+	data = SYN_DMA_INT_RX_COMPLETED | hal_read_relaxed_reg(mac_base, SYN_DMA_INT_ENABLE);
+	hal_write_relaxed_reg(mac_base, SYN_DMA_INT_ENABLE, data);
+}
+
+/*
+ * syn_enable_dma_interrupt()
+ *	Enables all DMA interrupts.
+ */
+static inline void syn_enable_dma_interrupt(void __iomem *mac_base)
+{
+	hal_write_relaxed_reg(mac_base, SYN_DMA_INT_ENABLE, (SYN_DMA_INT_NORMAL | SYN_DMA_INT_RX_COMPLETED | SYN_DMA_INT_TX_COMPLETED));
+}
+
+/*
+ * syn_disable_rx_dma_interrupt()
+ *	Disables Rx DMA interrupts.
+ */
+static inline void syn_disable_rx_dma_interrupt(void __iomem *mac_base)
+{
+	uint32_t data;
+
+	data = (~SYN_DMA_INT_RX_COMPLETED) & hal_read_relaxed_reg(mac_base, SYN_DMA_INT_ENABLE);
+	hal_write_relaxed_reg(mac_base, SYN_DMA_INT_ENABLE, data);
+}
+
+/*
+ * syn_disable_tx_dma_interrupt()
+ *	Disables Tx DMA interrupts.
+ */
+static inline void syn_disable_tx_dma_interrupt(void __iomem *mac_base)
+{
+	uint32_t data;
+
+	data = (~SYN_DMA_INT_TX_COMPLETED) & hal_read_relaxed_reg(mac_base, SYN_DMA_INT_ENABLE);
+	hal_write_relaxed_reg(mac_base, SYN_DMA_INT_ENABLE, data);
+}
+
+/*
+ * syn_disable_dma_interrupt()
+ *	Disables all DMA interrupts.
+ */
+static inline void syn_disable_dma_interrupt(void __iomem *mac_base)
+{
+	hal_write_relaxed_reg(mac_base, SYN_DMA_INT_ENABLE, SYN_DMA_INT_DISABLE);
+}
+
+/*
+ * syn_resume_dma_tx()
+ *	Resumes the DMA Transmission.
+ */
+static inline void syn_resume_dma_tx(void __iomem *mac_base)
+{
+	hal_write_relaxed_reg(mac_base, SYN_DMA_TX_POLL_DEMAND, 0);
+}
+
+/*
+ * syn_resume_dma_rx()
+ *	Resumes the DMA Receive.
+ */
+static inline void syn_resume_dma_rx(void __iomem *mac_base)
+{
+	hal_write_relaxed_reg(mac_base, SYN_DMA_RX_POLL_DEMAND, 0);
+}
+
+/*
+ * syn_clear_tx_dma_status()
+ *	Clear all pending Tx dma interrupts.
+ */
+static inline void syn_clear_tx_dma_status(void __iomem *mac_base)
+{
+	hal_write_relaxed_reg(mac_base, SYN_DMA_STATUS, (SYN_DMA_INT_NORMAL | SYN_DMA_INT_TX_COMPLETED));
+}
+
+/*
+ * syn_clear_rx_dma_status()
+ *	Clear all pending Rx dma interrupts.
+ */
+static inline void syn_clear_rx_dma_status(void __iomem *mac_base)
+{
+	hal_write_relaxed_reg(mac_base, SYN_DMA_STATUS, (SYN_DMA_INT_NORMAL | SYN_DMA_INT_RX_COMPLETED));
+}
+
+/*
+ * syn_clear_dma_status()
+ *	Clear all the pending dma interrupts.
+ */
+static inline void syn_clear_dma_status(void __iomem *mac_base)
+{
+	uint32_t data;
+
+	data = hal_read_relaxed_reg(mac_base, SYN_DMA_STATUS);
+	hal_write_relaxed_reg(mac_base, SYN_DMA_STATUS, data);
+}
+
+/*
+ * syn_get_rx_missed()
+ *	Get Rx missed errors
+ */
+static inline uint32_t syn_get_rx_missed(void __iomem *mac_base)
+{
+	uint32_t missed_frame_buff_overflow;
+
+	missed_frame_buff_overflow = hal_read_reg(mac_base, SYN_DMA_MISSED_FRAME_AND_BUFF_OVERFLOW_COUNTER);
+	return missed_frame_buff_overflow & SYN_DMA_RX_MISSED_MASK;
+}
+
+/*
+ * syn_get_fifo_overflows()
+ *	Get FIFO overflows
+ */
+static inline uint32_t syn_get_fifo_overflows(void __iomem *mac_base)
+{
+	uint32_t missed_frame_buff_overflow;
+
+	missed_frame_buff_overflow = hal_read_reg(mac_base, SYN_DMA_MISSED_FRAME_AND_BUFF_OVERFLOW_COUNTER);
+	return (missed_frame_buff_overflow >> SYN_DMA_FIFO_OVERFLOW_SHIFT) & SYN_DMA_FIFO_OVERFLOW_MASK;
+}
+
+#endif	// __SYN_DMA_REG_H__
diff --git a/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp.c b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp.c
new file mode 100644
index 0000000..4996653
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp.c
@@ -0,0 +1,453 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <nss_dp_dev.h>
+#include <linux/irq.h>
+#include "syn_dma_reg.h"
+
+/*
+ * syn_dp_napi_poll_rx()
+ *	Scheduled by napi to process RX.
+ */
+static int syn_dp_napi_poll_rx(struct napi_struct *napi, int budget)
+{
+	int work_done, pending_refill;
+	struct syn_dp_info_rx *rx_info = (struct syn_dp_info_rx *)napi;
+	void __iomem *mac_base = rx_info->mac_base;
+
+	work_done = syn_dp_rx(rx_info, budget);
+	if (likely(!rx_info->page_mode)) {
+		pending_refill = syn_dp_rx_refill(rx_info);
+	} else {
+		pending_refill = syn_dp_rx_refill_page_mode(rx_info);
+	}
+
+	/*
+	 * Schedule the rx napi again if refill is not completely done
+	 */
+	if (unlikely(pending_refill)) {
+		work_done = budget;
+	}
+
+	if (unlikely(work_done < budget)) {
+		napi_complete(napi);
+		syn_enable_rx_dma_interrupt(mac_base);
+	}
+
+	return work_done;
+}
+
+/*
+ * syn_dp_napi_poll_tx()
+ *	Scheduled by napi to process TX.
+ */
+static int syn_dp_napi_poll_tx(struct napi_struct *napi, int budget)
+{
+	struct syn_dp_info_tx *tx_info = (struct syn_dp_info_tx *)napi;
+	void __iomem *mac_base = tx_info->mac_base;
+	int work_done;
+
+	work_done = syn_dp_tx_complete(tx_info, budget);
+
+	if (unlikely(work_done < budget)) {
+		napi_complete(napi);
+		syn_enable_tx_dma_interrupt(mac_base);
+	}
+
+	return work_done;
+}
+
+/*
+ * syn_dp_handle_irq()
+ *	Process IRQ and schedule napi
+ */
+static irqreturn_t syn_dp_handle_irq(int irq, void *ctx)
+{
+	uint32_t status;
+	struct syn_dp_info *dp_info = (struct syn_dp_info *)ctx;
+	void __iomem *mac_base = dp_info->mac_base;
+
+	status = hal_read_relaxed_reg(mac_base, SYN_DMA_STATUS);
+
+	/*
+	 * We need to clear all interrupts other than RX and TX complete.
+	 * RX and TX complete interrupts should be cleared while scheduling Rx/Tx napi.
+	 */
+	hal_write_relaxed_reg(mac_base,
+			SYN_DMA_STATUS,
+			(status & (~(SYN_DMA_INT_TX_COMPLETED |
+			SYN_DMA_INT_RX_COMPLETED))));
+
+	/*
+	 * Schedule Rx napi if Rx complete interrupt is triggered.
+	 */
+	if (status & SYN_DMA_INT_RX_COMPLETED) {
+		syn_clear_rx_dma_status(mac_base);
+		syn_disable_rx_dma_interrupt(mac_base);
+		napi_schedule(&dp_info->dp_info_rx.napi_rx);
+	}
+
+	/*
+	 * Schedule Tx napi if Tx complete interrupt is triggered.
+	 */
+	if (status & SYN_DMA_INT_TX_COMPLETED) {
+		syn_clear_tx_dma_status(mac_base);
+		syn_disable_tx_dma_interrupt(mac_base);
+		napi_schedule(&dp_info->dp_info_tx.napi_tx);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * syn_dp_if_init()
+ *	Initialize the GMAC data plane operations
+ */
+static int syn_dp_if_init(struct nss_dp_data_plane_ctx *dpc)
+{
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *gmac_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	void __iomem *mac_base = gmac_dev->gmac_hal_ctx->mac_base;
+	uint32_t macid = gmac_dev->macid;
+	struct syn_dp_info *dev_info = &gmac_dev->dp_info.syn_info;
+	struct syn_dp_info_rx *rx_info = &dev_info->dp_info_rx;
+	struct syn_dp_info_tx *tx_info = &dev_info->dp_info_tx;
+	int err;
+
+	if (!netdev) {
+		netdev_err(netdev, "nss_dp_gmac: Invalid netdev pointer %px\n", netdev);
+		return NSS_DP_FAILURE;
+	}
+
+	/*
+	 * Initialize DMA operations.
+	 */
+	syn_dma_init(mac_base);
+
+	/*
+	 * If RX checksum is enabled, then configure DMA drop of the packet
+	 * if error in encapsulated ethernet payload.
+	 */
+	if (test_bit(__NSS_DP_RXCSUM, &gmac_dev->flags)) {
+		syn_rx_tcpip_chksum_drop_enable(mac_base);
+	}
+
+	dev_info->mac_base = rx_info->mac_base = tx_info->mac_base = mac_base;
+	rx_info->netdev = tx_info->netdev = netdev;
+	rx_info->dev = tx_info->dev = &gmac_dev->pdev->dev;
+	netdev_info(netdev, "nss_dp_gmac: Registering netdev %s(qcom-id:%d) with GMAC, mac_base: 0x%px\n", netdev->name, macid, mac_base);
+
+	/*
+	 * Forcing the kernel to use 32-bit DMA addressing
+	 */
+	dma_set_coherent_mask(&gmac_dev->pdev->dev, DMA_BIT_MASK(32));
+
+	/*
+	 * Initialize Rx buffer mode setting and skb allocation length
+	 * based on (page vs fraglist/jumbo-mru).
+	 */
+	rx_info->alloc_buf_len = dp_global_ctx.rx_buf_size;
+	rx_info->page_mode = gmac_dev->rx_page_mode;
+	if (rx_info->page_mode) {
+		rx_info->alloc_buf_len = (SYN_DP_PAGE_MODE_SKB_SIZE + SYN_DP_SKB_HEADROOM + NET_IP_ALIGN);
+	}
+
+	if (gmac_dev->rx_jumbo_mru) {
+		rx_info->alloc_buf_len = (gmac_dev->rx_jumbo_mru + NET_IP_ALIGN);
+	}
+
+	/*
+	 * Initialize the Rx ring
+	 */
+	if (syn_dp_cfg_rx_setup_rings(dev_info)) {
+		netdev_err(netdev, "nss_dp_gmac: Error initializing GMAC Rx rings %px\n", netdev);
+		return NSS_DP_FAILURE;
+	}
+
+	/*
+	 * Initialize the Tx ring
+	 */
+	if (syn_dp_cfg_tx_setup_rings(dev_info)) {
+		syn_dp_cfg_rx_cleanup_rings(dev_info);
+		netdev_err(netdev, "nss_dp_gmac: Error initializing GMAC Tx rings %px\n", netdev);
+		return NSS_DP_FAILURE;
+	}
+
+	if (!dev_info->napi_added) {
+		netif_napi_add(netdev, &rx_info->napi_rx, syn_dp_napi_poll_rx, SYN_DP_NAPI_BUDGET_RX);
+		netif_napi_add(netdev, &tx_info->napi_tx, syn_dp_napi_poll_tx, SYN_DP_NAPI_BUDGET_TX);
+
+		/*
+		 * Requesting irq. Set IRQ_DISABLE_UNLAZY flag, this flag
+		 * can be used for devices which cannot disable the interrupt
+		 * at the device level under certain circumstances
+		 * and have to use disable_irq[_nosync] instead.
+		 */
+		netdev->irq = platform_get_irq(gmac_dev->pdev, 0);
+		irq_set_status_flags(netdev->irq, IRQ_DISABLE_UNLAZY);
+		err = request_irq(netdev->irq, syn_dp_handle_irq, 0, "nss-dp-gmac", &gmac_dev->dp_info.syn_info);
+		if (unlikely(err)) {
+			netif_napi_del(&rx_info->napi_rx);
+			netif_napi_del(&tx_info->napi_tx);
+			syn_dp_cfg_rx_cleanup_rings(dev_info);
+			syn_dp_cfg_tx_cleanup_rings(dev_info);
+			netdev_err(netdev, "err_code:%d, Mac %d IRQ %d request failed\n", err,
+					gmac_dev->macid, netdev->irq);
+			return NSS_DP_FAILURE;
+		}
+
+		gmac_dev->drv_flags |= NSS_DP_PRIV_FLAG(IRQ_REQUESTED);
+		dev_info->napi_added = 1;
+	}
+
+	netdev_dbg(netdev,"Synopsys GMAC dataplane initialized\n");
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_if_open()
+ *	Open the GMAC data plane operations
+ */
+static int syn_dp_if_open(struct nss_dp_data_plane_ctx *dpc, uint32_t tx_desc_ring,
+					uint32_t rx_desc_ring, uint32_t mode)
+{
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *gmac_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	void __iomem *mac_base = gmac_dev->gmac_hal_ctx->mac_base;
+	struct nss_dp_hal_info *dp_info = &gmac_dev->dp_info;
+
+	napi_enable(&dp_info->syn_info.dp_info_rx.napi_rx);
+	napi_enable(&dp_info->syn_info.dp_info_tx.napi_tx);
+
+	syn_enable_dma_tx(mac_base);
+	syn_enable_dma_rx(mac_base);
+
+	syn_enable_dma_interrupt(mac_base);
+
+	netdev_dbg(netdev, "Synopsys GMAC dataplane opened\n");
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_if_close()
+ *	Close the GMAC data plane operations
+ */
+static int syn_dp_if_close(struct nss_dp_data_plane_ctx *dpc)
+{
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *gmac_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	void __iomem *mac_base = gmac_dev->gmac_hal_ctx->mac_base;
+	struct nss_dp_hal_info *dp_info = &gmac_dev->dp_info;
+
+	syn_disable_dma_interrupt(mac_base);
+
+	syn_disable_dma_rx(mac_base);
+	syn_disable_dma_tx(mac_base);
+
+	napi_disable(&dp_info->syn_info.dp_info_rx.napi_rx);
+	napi_disable(&dp_info->syn_info.dp_info_tx.napi_tx);
+
+	netdev_dbg(netdev, "Synopsys GMAC dataplane closed\n");
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_if_link_state()
+ *	Change of link state for the dataplane
+ */
+static int syn_dp_if_link_state(struct nss_dp_data_plane_ctx *dpc, uint32_t link_state)
+{
+	struct net_device *netdev = dpc->dev;
+
+	if (link_state) {
+		netdev_dbg(netdev, "Data plane link up\n");
+	} else {
+		netdev_dbg(netdev, "Data plane link down\n");
+	}
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_if_mac_addr()
+ */
+static int syn_dp_if_mac_addr(struct nss_dp_data_plane_ctx *dpc, uint8_t *addr)
+{
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_if_change_mtu()
+ */
+static int syn_dp_if_change_mtu(struct nss_dp_data_plane_ctx *dpc, uint32_t mtu)
+{
+	/*
+	 * TODO: Work on MTU fix along with register update for frame length
+	 */
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_if_set_features()
+ *	Set the supported net_device features
+ */
+static void syn_dp_if_set_features(struct nss_dp_data_plane_ctx *dpc)
+{
+	struct net_device *netdev = dpc->dev;
+
+	netdev->features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM | NETIF_F_FRAGLIST | NETIF_F_SG;
+	netdev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM | NETIF_F_FRAGLIST | NETIF_F_SG;
+	netdev->vlan_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM | NETIF_F_FRAGLIST | NETIF_F_SG;
+	netdev->wanted_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM | NETIF_F_FRAGLIST | NETIF_F_SG;
+}
+
+/*
+ * syn_dp_if_xmit()
+ *	Dataplane method to transmit the packet
+ */
+static netdev_tx_t syn_dp_if_xmit(struct nss_dp_data_plane_ctx *dpc, struct sk_buff *skb)
+{
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *gmac_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	struct syn_dp_info_tx *tx_info = &gmac_dev->dp_info.syn_info.dp_info_tx;
+	uint16_t ret;
+
+	ret = syn_dp_tx(tx_info, skb);
+	if (likely(!ret)) {
+		return NETDEV_TX_OK;
+	}
+
+	dp_global_ctx.tx_requeue_stop = 1;
+
+	/*
+	 * Handle the scenario when descriptors are not enough.
+	 * Only one DMA channel is supported to assume queue 0.
+	 */
+	if (likely(ret == NETDEV_TX_BUSY)) {
+		/*
+		 * Stop the queue if the queue stop is not disabled and return
+		 * NETDEV_TX_BUSY. Packet will be requeued or dropped by the caller.
+		 * Queue will be re-enabled from Tx Complete.
+		 */
+		if (likely(!dp_global_ctx.tx_requeue_stop)) {
+			netdev_dbg(netdev, "Stopping tx queue due to lack of tx descriptors");
+			atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_packets_requeued);
+			netif_stop_queue(netdev);
+			return NETDEV_TX_BUSY;
+		}
+	}
+
+	netdev_dbg(netdev, "Drop packet due to no Tx descriptor or invalid pkt");
+	atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_dropped);
+	dev_kfree_skb_any(skb);
+	return NETDEV_TX_OK;
+}
+
+/*
+ * syn_dp_if_pause_on_off()
+ */
+static int syn_dp_if_pause_on_off(struct nss_dp_data_plane_ctx *dpc, uint32_t pause_on)
+{
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_if_get_stats
+ *	Get Synopsys GMAC data plane stats
+ */
+static void syn_dp_if_get_stats(struct nss_dp_data_plane_ctx *dpc,
+				struct nss_dp_gmac_stats *stats)
+{
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *gmac_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	struct nss_dp_hal_info *hal_info = &gmac_dev->dp_info;
+
+	netdev_dbg(netdev, "GETTING stats: rx_packets:%llu rx_bytes:%llu",
+			hal_info->syn_info.dp_info_rx.rx_stats.rx_packets,
+			hal_info->syn_info.dp_info_rx.rx_stats.rx_bytes);
+
+	/*
+	 * TODO: Convert to per-cpu stats and use seqcount based update/read
+	 */
+	memcpy(&stats->stats.rx_stats, &hal_info->syn_info.dp_info_rx.rx_stats, sizeof(struct nss_dp_hal_gmac_stats_rx));
+	memcpy(&stats->stats.tx_stats, &hal_info->syn_info.dp_info_tx.tx_stats, sizeof(struct nss_dp_hal_gmac_stats_tx));
+}
+
+/*
+ * syn_dp_if_deinit()
+ *	Free all the Synopsys GMAC resources
+ */
+static int syn_dp_if_deinit(struct nss_dp_data_plane_ctx *dpc)
+{
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *gmac_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	struct nss_dp_hal_info *dp_info = &gmac_dev->dp_info;
+	struct syn_dp_info *dev_info = &dp_info->syn_info;
+
+	if (dev_info->napi_added) {
+
+		/*
+		 * Remove interrupt handlers and NAPI
+		 */
+		if (gmac_dev->drv_flags & NSS_DP_PRIV_FLAG(IRQ_REQUESTED)) {
+			netdev_dbg(netdev, "Freeing IRQ %d for Mac %d\n", netdev->irq, gmac_dev->macid);
+			synchronize_irq(netdev->irq);
+			free_irq(netdev->irq, dev_info);
+			gmac_dev->drv_flags &= ~NSS_DP_PRIV_FLAG(IRQ_REQUESTED);
+		}
+
+		netif_napi_del(&dev_info->dp_info_rx.napi_rx);
+		netif_napi_del(&dev_info->dp_info_tx.napi_tx);
+		dev_info->napi_added = 0;
+	}
+
+	/*
+	 * Cleanup and free the rings
+	 */
+	syn_dp_cfg_rx_cleanup_rings(dev_info);
+	syn_dp_cfg_tx_cleanup_rings(dev_info);
+
+	/*
+	 * Restore the DMA settings to avoid padding the descriptors
+	 * to 64B. This is needed for NSS offload mode.
+	 */
+	syn_dma_bus_mode_init_clsize_32byte(dev_info->mac_base);
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * nss_dp_gmac_ops
+ *	Data plane operations for Synopsys GMAC
+ */
+struct nss_dp_data_plane_ops nss_dp_gmac_ops = {
+	.init		= syn_dp_if_init,
+	.open		= syn_dp_if_open,
+	.close		= syn_dp_if_close,
+	.link_state	= syn_dp_if_link_state,
+	.mac_addr	= syn_dp_if_mac_addr,
+	.change_mtu	= syn_dp_if_change_mtu,
+	.xmit		= syn_dp_if_xmit,
+	.set_features	= syn_dp_if_set_features,
+	.pause_on_off	= syn_dp_if_pause_on_off,
+	.get_stats	= syn_dp_if_get_stats,
+	.deinit		= syn_dp_if_deinit,
+};
diff --git a/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp.h b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp.h
new file mode 100644
index 0000000..7c1b81b
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_SYN_DP__
+#define __NSS_DP_SYN_DP__
+
+#include "syn_dma_desc.h"
+#include "syn_dp_rx.h"
+#include "syn_dp_tx.h"
+
+/*
+ * The driver uses kernel DMA constructs that assume an architecture
+ * where the view of physical addresses is consistent between SoC and
+ * IO device(SynopsysGMAC).
+ * Note that this may not be compatible for platforms where this
+ * assumption is not true, for example IO devices with IOMMU support.
+ */
+#if defined(CONFIG_ARM_SMMU) || \
+	defined(CONFIG_IOMMU_SUPPORT)
+#error "Build Error: Platform is enabled with IOMMU/SMMU support."
+#endif
+
+#define SYN_DP_MINI_JUMBO_FRAME_MTU	1978
+#define SYN_DP_MAX_DESC_BUFF_LEN	0x1FFF	/* Max size of buffer that can be programed into one field of desc */
+#define SYN_DP_SKB_ALLOC_SIZE		(SYN_DP_MINI_JUMBO_FRAME_MTU + NET_IP_ALIGN)
+#define SYN_DP_SKB_HEADROOM		128
+#define SYN_DP_PAGE_MODE_SKB_SIZE	256	/* SKB head buffer size for page mode */
+#define SYN_DP_QUEUE_INDEX		0	/* Only one Tx DMA channel 0 enabled */
+
+/*
+ * syn_dp_info
+ *	Synopysys GMAC Dataplane information
+ */
+struct syn_dp_info {
+	struct syn_dp_info_rx dp_info_rx;
+	struct syn_dp_info_tx dp_info_tx;
+	void __iomem *mac_base;
+	dma_addr_t rx_desc_dma_addr;
+	dma_addr_t tx_desc_dma_addr;
+	int napi_added;
+};
+
+/*
+ * GMAC TX/Rx APIs
+ */
+int syn_dp_cfg_rx_setup_rings(struct syn_dp_info *dev_info);
+void syn_dp_cfg_rx_cleanup_rings(struct syn_dp_info *dev_info);
+int syn_dp_cfg_tx_setup_rings(struct syn_dp_info *dev_info);
+void syn_dp_cfg_tx_cleanup_rings(struct syn_dp_info *dev_info);
+
+int syn_dp_rx(struct syn_dp_info_rx *rx_info, int budget);
+int syn_dp_rx_refill(struct syn_dp_info_rx *rx_info);
+int syn_dp_rx_refill_page_mode(struct syn_dp_info_rx *rx_info);
+int syn_dp_tx(struct syn_dp_info_tx *tx_info, struct sk_buff *skb);
+int syn_dp_tx_complete(struct syn_dp_info_tx *tx_info, int budget);
+
+#endif /*  __NSS_DP_SYN_DP__ */
diff --git a/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_cfg_rx.c b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_cfg_rx.c
new file mode 100644
index 0000000..52048d3
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_cfg_rx.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <nss_dp_dev.h>
+#include "syn_dma_reg.h"
+
+/*
+ * syn_dp_cfg_rx_setup_desc_queue
+ *	This sets up the receive Descriptor queue in ring mode.
+ */
+static int syn_dp_cfg_rx_setup_desc_queue(struct syn_dp_info *dev_info)
+{
+	struct syn_dp_info_rx *rx_info = &dev_info->dp_info_rx;
+	struct dma_desc_rx *first_desc = NULL;
+	struct net_device *netdev = rx_info->netdev;
+
+	netdev_dbg(netdev, "Total size of memory required for Rx Descriptors in Ring Mode = %u\n", (uint32_t)((sizeof(struct dma_desc_rx) * SYN_DP_RX_DESC_SIZE)));
+
+	/*
+	 * Allocate cacheable descriptors for Rx
+	 */
+	first_desc = kzalloc(sizeof(struct dma_desc_rx) * SYN_DP_RX_DESC_SIZE, GFP_KERNEL);
+	if (!first_desc) {
+		netdev_dbg(netdev, "Error in Rx Descriptor Memory allocation in Ring mode\n");
+		return -ENOMEM;
+	}
+
+	dev_info->rx_desc_dma_addr = (dma_addr_t)virt_to_phys(first_desc);
+	rx_info->rx_desc = first_desc;
+	syn_dp_gmac_rx_desc_init_ring(rx_info->rx_desc, SYN_DP_RX_DESC_SIZE);
+
+	rx_info->rx_refill_idx = 0;
+	rx_info->rx_idx = 0;
+	rx_info->busy_rx_desc_cnt = 0;
+
+	netdev_dbg(netdev, "Rx Descriptors in Ring Mode: No. of descriptors = %d base = 0x%px dma = 0x%px\n",
+			SYN_DP_RX_DESC_SIZE, first_desc, (void *)dev_info->rx_desc_dma_addr);
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_cfg_rx_setup_rings
+ *	Perform initial setup of Rx rings
+ */
+int syn_dp_cfg_rx_setup_rings(struct syn_dp_info *dev_info)
+{
+	int err;
+
+	err = syn_dp_cfg_rx_setup_desc_queue(dev_info);
+	if (err) {
+		netdev_dbg(dev_info->dp_info_rx.netdev, "nss_dp_gmac: rx descriptor setup unsuccessfull, err code: %d", err);
+		return NSS_DP_FAILURE;
+	}
+
+	if (likely(!dev_info->dp_info_rx.page_mode)) {
+		syn_dp_rx_refill(&dev_info->dp_info_rx);
+	} else {
+		syn_dp_rx_refill_page_mode(&dev_info->dp_info_rx);
+	}
+	syn_init_rx_desc_base(dev_info->mac_base, dev_info->rx_desc_dma_addr);
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_cfg_rx_cleanup_rings
+ *	Cleanup Synopsys GMAC Rx rings
+ */
+void syn_dp_cfg_rx_cleanup_rings(struct syn_dp_info *dev_info)
+{
+	struct syn_dp_info_rx *rx_info = &dev_info->dp_info_rx;
+	uint32_t rx_skb_index;
+	struct dma_desc_rx *rxdesc;
+	int i;
+	struct sk_buff *skb;
+
+	/*
+	 * Rx Ring cleaning
+	 * We are assuming that the NAPI poll was already completed.
+	 * No need of a lock here since the NAPI and interrupts have been disabled now
+	 */
+	rx_skb_index = rx_info->rx_idx;
+	for (i = 0; i < rx_info->busy_rx_desc_cnt; i++) {
+		rx_skb_index = (rx_skb_index + i) & SYN_DP_RX_DESC_MAX_INDEX;
+		rxdesc = rx_info->rx_desc;
+		skb = rx_info->rx_buf_pool[rx_skb_index].skb;
+		if (unlikely(skb != NULL)) {
+			dev_kfree_skb_any(skb);
+			rx_info->rx_buf_pool[rx_skb_index].skb = NULL;
+		}
+	}
+
+	kfree(rx_info->rx_desc);
+	rx_info->rx_desc = NULL;
+	dev_info->rx_desc_dma_addr = (dma_addr_t)0;
+}
diff --git a/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_cfg_tx.c b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_cfg_tx.c
new file mode 100644
index 0000000..bf5e19a
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_cfg_tx.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <nss_dp_dev.h>
+#include "syn_dma_reg.h"
+
+/*
+ * syn_dp_cfg_tx_setup_desc_queue
+ *	This sets up the transmit Descriptor queue in ring mode.
+ */
+static int syn_dp_cfg_tx_setup_desc_queue(struct syn_dp_info *dev_info)
+{
+	struct syn_dp_info_tx *tx_info = &dev_info->dp_info_tx;
+	struct net_device *netdev = tx_info->netdev;
+	struct dma_desc_tx *first_desc = NULL;
+	dma_addr_t dma_addr;
+
+	netdev_dbg(netdev, "Total size of memory required for Tx Descriptors in Ring Mode = %u\n", (uint32_t)((sizeof(struct dma_desc_tx) * SYN_DP_TX_DESC_SIZE)));
+
+	first_desc = dma_alloc_coherent(tx_info->dev, sizeof(struct dma_desc_tx) * SYN_DP_TX_DESC_SIZE, &dma_addr, GFP_KERNEL);
+	if (!first_desc) {
+		netdev_dbg(netdev, "Error in Tx Descriptors memory allocation\n");
+		return -ENOMEM;
+	}
+
+	tx_info->tx_desc = first_desc;
+	dev_info->tx_desc_dma_addr = dma_addr;
+	netdev_dbg(netdev, "Tx Descriptors in Ring Mode: No. of descriptors = %d base = 0x%px dma = 0x%px\n"
+			, SYN_DP_TX_DESC_SIZE, first_desc, (void *)dma_addr);
+
+	syn_dp_gmac_tx_desc_init_ring(tx_info->tx_desc, SYN_DP_TX_DESC_SIZE);
+
+	tx_info->tx_comp_idx = 0;
+	tx_info->tx_idx = 0;
+	tx_info->busy_tx_desc_cnt = 0;
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_cfg_tx_setup_rings
+ *	Perform initial setup of Tx rings
+ */
+int syn_dp_cfg_tx_setup_rings(struct syn_dp_info *dev_info)
+{
+	int err;
+
+	err = syn_dp_cfg_tx_setup_desc_queue(dev_info);
+	if (err) {
+		netdev_dbg(dev_info->dp_info_tx.netdev, "nss_dp_gmac: tx descriptor setup unsuccessfull, err code: %d", err);
+		return NSS_DP_FAILURE;
+	}
+
+	syn_init_tx_desc_base(dev_info->mac_base, dev_info->tx_desc_dma_addr);
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_cfg_tx_cleanup_rings
+ *	Cleanup Synopsys GMAC Tx rings
+ */
+void syn_dp_cfg_tx_cleanup_rings(struct syn_dp_info *dev_info)
+{
+	struct syn_dp_info_tx *tx_info = &dev_info->dp_info_tx;
+	uint32_t tx_skb_index;
+	struct dma_desc_tx *txdesc;
+	int i;
+	struct sk_buff *skb;
+	uint32_t busy_tx_desc_cnt = atomic_read((atomic_t *)&tx_info->busy_tx_desc_cnt);
+
+	/*
+	 * Tx Ring cleaning
+	 */
+	tx_skb_index = syn_dp_tx_comp_index_get(tx_info);
+	for (i = 0; i < busy_tx_desc_cnt; i++) {
+		tx_skb_index = syn_dp_tx_inc_index(tx_skb_index, i);
+		txdesc = tx_info->tx_desc;
+
+		skb = tx_info->tx_buf_pool[tx_skb_index].skb;
+		if (unlikely(skb != NULL)) {
+			dev_kfree_skb_any(skb);
+			tx_info->tx_buf_pool[tx_skb_index].skb = NULL;
+		}
+	}
+
+	dma_free_coherent(tx_info->dev, (sizeof(struct dma_desc_tx) * SYN_DP_TX_DESC_SIZE),
+				tx_info->tx_desc, dev_info->tx_desc_dma_addr);
+}
diff --git a/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_rx.c b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_rx.c
new file mode 100644
index 0000000..529c77e
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_rx.c
@@ -0,0 +1,643 @@
+/*
+ * Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <asm/cacheflush.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include <linux/debugfs.h>
+
+#include <nss_dp_dev.h>
+#include "syn_dma_reg.h"
+
+/*
+ * syn_dp_rx_reset_one_desc()
+ *	Reset the descriptor after Rx is over.
+ */
+static inline void syn_dp_rx_reset_one_desc(struct dma_desc_rx *rx_desc)
+{
+	rx_desc->status = 0;
+	rx_desc->length &= DESC_RX_DESC_END_OF_RING;
+	rx_desc->buffer1 = 0;
+	rx_desc->buffer2 = 0;
+	rx_desc->extstatus = 0;
+}
+
+/*
+ * syn_dp_rx_refill_one_desc()
+ *	Prepares the descriptor to receive packets.
+ */
+static inline void syn_dp_rx_refill_one_desc(struct dma_desc_rx *rx_desc,
+					uint32_t buffer1, uint32_t length1)
+{
+#ifdef SYN_DP_DEBUG
+	BUG_ON(!syn_dp_gmac_is_rx_desc_empty(rx_desc));
+	BUG_ON(syn_dp_gmac_is_rx_desc_owned_by_dma(rx_desc->status));
+#endif
+
+	if (likely(length1 <= SYN_DP_MAX_DESC_BUFF_LEN)) {
+		rx_desc->length |= ((length1 << DESC_SIZE1_SHIFT) & DESC_SIZE1_MASK);
+		rx_desc->buffer2 = 0;
+	} else {
+		rx_desc->length |= (SYN_DP_MAX_DESC_BUFF_LEN << DESC_SIZE1_SHIFT) & DESC_SIZE1_MASK;
+		rx_desc->length |= ((length1 - SYN_DP_MAX_DESC_BUFF_LEN) << DESC_SIZE2_SHIFT) & DESC_SIZE2_MASK;
+
+		/*
+		 * Program second buffer address if using two buffers.
+		 */
+		rx_desc->buffer2 = buffer1 + SYN_DP_MAX_DESC_BUFF_LEN;
+	}
+
+	rx_desc->buffer1 = buffer1;
+	rx_desc->status = DESC_OWN_BY_DMA;
+}
+
+/*
+ * syn_dp_rx_inval_and_flush()
+ * 	Flush and invalidate the Rx descriptors
+ */
+static inline void syn_dp_rx_inval_and_flush(struct syn_dp_info_rx *rx_info, uint32_t start, uint32_t end)
+{
+	/*
+	 * Batched flush and invalidation of the rx descriptors
+	 */
+	if (end > start) {
+		dmac_flush_range_no_dsb((void *)&rx_info->rx_desc[start], (void *)&rx_info->rx_desc[end] + sizeof(struct dma_desc_rx));
+	} else {
+		dmac_flush_range_no_dsb((void *)&rx_info->rx_desc[start], (void *)&rx_info->rx_desc[SYN_DP_RX_DESC_MAX_INDEX] + sizeof(struct dma_desc_rx));
+		dmac_flush_range_no_dsb((void *)&rx_info->rx_desc[0], (void *)&rx_info->rx_desc[end] + sizeof(struct dma_desc_rx));
+	}
+
+	dsb(st);
+}
+
+/*
+ * syn_dp_rx_refill_page_mode()
+ *	Refill the RX descrptor for page mode
+ */
+int syn_dp_rx_refill_page_mode(struct syn_dp_info_rx *rx_info)
+{
+	int refill_cnt, empty_count;
+	struct net_device *netdev = rx_info->netdev;
+	int i;
+	dma_addr_t dma_addr;
+	struct dma_desc_rx *rx_desc;
+	struct sk_buff *skb;
+	uint32_t rx_refill_idx;
+	uint32_t start, end;
+	struct page *pg;
+	void *page_addr;
+	empty_count = refill_cnt =  SYN_DP_RX_DESC_SIZE - atomic_read((atomic_t *)&rx_info->busy_rx_desc_cnt);
+	start = rx_info->rx_refill_idx;
+	end = syn_dp_rx_inc_index(start, empty_count);
+
+	for (i = 0; i < empty_count; i++) {
+		skb = __netdev_alloc_skb(netdev, rx_info->alloc_buf_len, GFP_ATOMIC);
+		if (unlikely(!skb)) {
+			netdev_dbg(netdev, "Unable to allocate skb for page_mode");
+			atomic64_inc((atomic64_t *)&rx_info->rx_stats.rx_skb_alloc_errors);
+			break;
+		}
+
+		skb_reserve(skb, SYN_DP_SKB_HEADROOM + NET_IP_ALIGN);
+
+		pg = alloc_page(GFP_ATOMIC);
+		if (unlikely(!pg)) {
+			dev_kfree_skb_any(skb);
+			netdev_dbg(netdev, "Unable to allocate page");
+			atomic64_inc((atomic64_t *)&rx_info->rx_stats.rx_skb_alloc_errors);
+			break;
+		}
+
+		/*
+		 * Get virtual address of allocated page.
+		 */
+		page_addr = page_address(pg);
+		dma_addr = (dma_addr_t)virt_to_phys(page_addr);
+
+		skb_fill_page_desc(skb, 0, pg, 0, PAGE_SIZE);
+
+		dmac_inv_range_no_dsb(page_addr, (page_addr + PAGE_SIZE));
+		rx_refill_idx = rx_info->rx_refill_idx;
+		rx_desc = rx_info->rx_desc + rx_refill_idx;
+
+		/*
+		 * Set Rx descriptor variables
+		 */
+		syn_dp_rx_refill_one_desc(rx_desc, dma_addr, PAGE_SIZE);
+		rx_info->rx_buf_pool[rx_refill_idx].skb = skb;
+		rx_info->rx_buf_pool[rx_refill_idx].map_addr_virt = (size_t)(page_addr);
+
+		rx_info->rx_refill_idx = syn_dp_rx_inc_index(rx_refill_idx, 1);
+		atomic_inc((atomic_t *)&rx_info->busy_rx_desc_cnt);
+	}
+
+	syn_dp_rx_inval_and_flush(rx_info, start, end);
+	syn_resume_dma_rx(rx_info->mac_base);
+	return refill_cnt - i;
+}
+
+/*
+ * syn_dp_rx_refill()
+ *	Refill the RX descrptor
+ */
+int syn_dp_rx_refill(struct syn_dp_info_rx *rx_info)
+{
+	int refill_cnt, empty_count;
+	struct net_device *netdev = rx_info->netdev;
+	int i;
+	dma_addr_t dma_addr;
+	struct dma_desc_rx *rx_desc;
+	struct sk_buff *skb;
+	uint32_t rx_refill_idx;
+	uint32_t start, end, inval_len;
+	empty_count = refill_cnt = SYN_DP_RX_DESC_SIZE - atomic_read((atomic_t *)&rx_info->busy_rx_desc_cnt);
+	start = rx_info->rx_refill_idx;
+	end = syn_dp_rx_inc_index(start, empty_count);
+	inval_len = rx_info->alloc_buf_len - SYN_DP_SKB_HEADROOM - NET_IP_ALIGN;
+
+	for (i = 0; i < empty_count; i++) {
+		skb = __netdev_alloc_skb(netdev, rx_info->alloc_buf_len, GFP_ATOMIC);
+		if (unlikely(!skb)) {
+			netdev_dbg(netdev, "Unable to allocate skb, will try next time\n");
+			atomic64_inc((atomic64_t *)&rx_info->rx_stats.rx_skb_alloc_errors);
+			break;
+		}
+
+		skb_reserve(skb, SYN_DP_SKB_HEADROOM + NET_IP_ALIGN);
+
+		dma_addr = (dma_addr_t)virt_to_phys(skb->data);
+		dmac_inv_range_no_dsb((void *)skb->data, (void *)(skb->data + inval_len));
+		rx_refill_idx = rx_info->rx_refill_idx;
+		rx_desc = rx_info->rx_desc + rx_refill_idx;
+
+		/*
+		 * Set Rx descriptor variables
+		 */
+		syn_dp_rx_refill_one_desc(rx_desc, dma_addr, inval_len);
+		rx_info->rx_buf_pool[rx_refill_idx].skb = skb;
+		rx_info->rx_buf_pool[rx_refill_idx].map_addr_virt = (size_t)(skb->data);
+
+		rx_info->rx_refill_idx = syn_dp_rx_inc_index(rx_refill_idx, 1);
+		atomic_inc((atomic_t *)&rx_info->busy_rx_desc_cnt);
+	}
+
+	syn_dp_rx_inval_and_flush(rx_info, start, end);
+	syn_resume_dma_rx(rx_info->mac_base);
+	return refill_cnt - i;
+}
+
+/*
+ * syn_dp_handle_jumbo_packets
+ * 	Process received scattered packets
+ */
+static bool syn_dp_handle_jumbo_packets(struct syn_dp_info_rx *rx_info, struct sk_buff *rx_skb, uint32_t status)
+{
+	int frame_length, temp_len;
+	skb_frag_t *frag;
+
+	frame_length = syn_dp_gmac_get_rx_desc_frame_length(status);
+
+	if (likely(!rx_info->page_mode)) {
+
+		/*
+		 * For fraglist case.
+		 */
+		if ((status & DESC_RX_FIRST) == DESC_RX_FIRST) {
+			/*
+			 * This descriptor is 1st part of frame, make it as head.
+			 */
+			skb_put(rx_skb, frame_length);
+
+			rx_info->head = rx_skb;
+			rx_info->tail = NULL;
+			rx_info->prev_len = frame_length;
+			return true;
+		}
+
+		/*
+		 * If head is not present, which means broken frame.
+		 */
+		if (unlikely(!rx_info->head)) {
+			netdev_err(rx_info->netdev, "Broken frame received for jumbo packet (non page mode)");
+			return false;
+		}
+
+		/*
+		 * Frame length of current skb contains length of previous one also.
+		 * Drop the Skb if wrong length received.
+		 */
+		if (unlikely(frame_length <= rx_info->prev_len)) {
+			netdev_err(rx_info->netdev, "Incorrect frame length received for jumbo packet (non page mode)");
+			return false;
+		}
+
+		temp_len = frame_length - rx_info->prev_len;
+		skb_put(rx_skb, temp_len);
+
+		/*
+		 * If head is present and got next desc.
+		 * Append it to the fraglist of head if this is 2nd frame.
+		 * If not 2nd frame, append to tail.
+		 */
+		if (!skb_shinfo(rx_info->head)->frag_list) {
+			skb_shinfo(rx_info->head)->frag_list = rx_skb;
+		} else {
+			rx_info->tail->next = rx_skb;
+		}
+
+		rx_info->tail = rx_skb;
+		rx_info->tail->next = NULL;
+
+		rx_info->head->data_len += rx_skb->len;
+		rx_info->head->len += rx_skb->len;
+		rx_info->head->truesize += rx_skb->truesize;
+
+		rx_info->prev_len = frame_length;
+		return true;
+	}
+
+	/*
+	 * Page mode processing.
+	 */
+	if ((status & DESC_RX_FIRST) == DESC_RX_FIRST) {
+		/*
+		 * 1st desc of frame, initialize it as head.
+		 */
+		rx_skb->len = frame_length;
+		rx_skb->data_len = frame_length;
+		rx_skb->truesize = PAGE_SIZE;
+		rx_info->head = rx_skb;
+
+		/*
+		 * Store length as next desc will have accumulated number of bytes
+		 * that have been transferred for the current frame.
+		 */
+		rx_info->prev_len = frame_length;
+		return true;
+	}
+
+	if (unlikely(!rx_info->head)) {
+		netdev_err(rx_info->netdev, "Broken frame received for jumbo packet (page mode)");
+		return false;
+	}
+
+	/*
+	 * Frame length of current skb contains length of previous one also.
+	 * Drop the Skb if wrong length received.
+	 */
+	if (unlikely(frame_length <= rx_info->prev_len)) {
+		netdev_err(rx_info->netdev, "Incorrect frame length received for jumbo packet (page mode)");
+		return false;
+	}
+
+	temp_len = frame_length - rx_info->prev_len;
+
+	frag = &skb_shinfo(rx_skb)->frags[0];
+
+	/*
+	 * Append current frag at correct index as nr_frag of parent skb.
+	 */
+	skb_fill_page_desc(rx_info->head,  skb_shinfo(rx_info->head)->nr_frags, skb_frag_page(frag), 0, temp_len);
+	rx_info->head->len += temp_len;
+	rx_info->head->data_len += temp_len;
+	rx_info->head->truesize += PAGE_SIZE;
+
+	rx_info->prev_len = frame_length;
+	skb_shinfo(rx_skb)->nr_frags = 0;
+
+	/*
+	 * Discard this skb since it's fragment has been appended to the head skb's frag array.
+	 */
+	dev_kfree_skb_any(rx_skb);
+	return true;
+}
+
+/*
+ * syn_dp_rx_process_drop()
+ * 	Process Rx error packets
+ */
+static inline void syn_dp_rx_process_drop(struct syn_dp_info_rx *rx_info, uint32_t status,
+					  struct sk_buff *rx_skb, bool is_sg)
+{
+	/*
+	 * Drop the packet if we encounter error in middle of S/G or
+	 * if head skb is not present.
+	 */
+	if (unlikely(is_sg)) {
+		if (likely(rx_info->head)) {
+			dev_kfree_skb_any(rx_info->head);
+			rx_info->head = NULL;
+			rx_info->tail = NULL;
+		}
+		atomic64_inc((atomic64_t *)&rx_info->rx_stats.rx_scatter_errors);
+		rx_info->prev_len = 0;
+	}
+
+	/*
+	 * Invalid packets received, free the skb
+	 */
+	dev_kfree_skb_any(rx_skb);
+	atomic64_inc((atomic64_t *)&rx_info->rx_stats.rx_errors);
+
+	(status & DESC_RX_COLLISION) ? atomic64_inc((atomic64_t *)&rx_info->rx_stats.rx_late_collision_errors) : NULL;
+	(status & DESC_RX_DRIBBLING) ? atomic64_inc((atomic64_t *)&rx_info->rx_stats.rx_dribble_bit_errors) : NULL;
+	(status & DESC_RX_LENGTH_ERROR) ? atomic64_inc((atomic64_t *)&rx_info->rx_stats.rx_length_errors) : NULL;
+	(status & DESC_RX_CRC) ? atomic64_inc((atomic64_t *)&rx_info->rx_stats.rx_crc_errors) : NULL;
+	(status & DESC_RX_OVERFLOW) ? atomic64_inc((atomic64_t *)&rx_info->rx_stats.rx_overflow_errors) : NULL;
+	(status & DESC_RX_IP_HEADER_ERROR) ? atomic64_inc((atomic64_t *)&rx_info->rx_stats.rx_ip_header_errors) : NULL;
+	(status & DESC_RX_IP_PAYLOAD_ERROR) ? atomic64_inc((atomic64_t *)&rx_info->rx_stats.rx_ip_payload_errors) : NULL;
+}
+
+/*
+ * syn_dp_rx()
+ *	Process RX packets
+ */
+int syn_dp_rx(struct syn_dp_info_rx *rx_info, int budget)
+{
+	struct dma_desc_rx *rx_desc = NULL;
+	int frame_length, busy, rx_idx, rx_next_idx;
+	uint32_t status, extstatus;
+	struct sk_buff *rx_skb;
+	struct net_device *netdev = rx_info->netdev;
+	uint32_t rx_packets = 0, rx_bytes = 0;
+	uint32_t start, end;
+	struct syn_dp_rx_buf *rx_buf;
+	struct dma_desc_rx *rx_desc_next = NULL;
+	uint8_t *next_skb_ptr;
+	skb_frag_t *frag = NULL;
+	bool is_gro_enabled = netdev->features & NETIF_F_GRO;
+
+	busy = atomic_read((atomic_t *)&rx_info->busy_rx_desc_cnt);
+	if (unlikely(!busy)) {
+		/*
+		 * No desc are held by GMAC DMA, we are done
+		 */
+		atomic64_inc((atomic64_t *)&rx_info->rx_stats.rx_no_buffer_errors);
+		return 0;
+	}
+
+	if (likely(busy > budget)) {
+		busy = budget;
+	}
+
+	start = rx_info->rx_idx;
+	rx_desc = rx_info->rx_desc + start;
+
+	/*
+	 * Invalidate all the descriptors we can read in one go.
+	 * This could mean we re invalidating more than what we could
+	 * have got from hardware, but that should be ok.
+	 *
+	 * It is expected that speculative prefetches are disabled while
+	 * this code is executing.
+	 */
+	end = syn_dp_rx_inc_index(rx_info->rx_idx, busy);
+	if (end > start) {
+		dmac_inv_range_no_dsb((void *)&rx_info->rx_desc[start], (void *)&rx_info->rx_desc[end] + sizeof(struct dma_desc_rx));
+	} else {
+		dmac_inv_range_no_dsb((void *)&rx_info->rx_desc[start], (void *)&rx_info->rx_desc[SYN_DP_RX_DESC_MAX_INDEX] + sizeof(struct dma_desc_rx));
+		dmac_inv_range_no_dsb((void *)&rx_info->rx_desc[0], (void *)&rx_info->rx_desc[end] + sizeof(struct dma_desc_rx));
+	}
+
+	dsb(st);
+
+	do {
+		status = rx_desc->status;
+		if (unlikely(syn_dp_gmac_is_rx_desc_owned_by_dma(status))) {
+
+			/*
+			 * Rx descriptor still hold by GMAC DMA, so we are done.
+			 * Before we return, invalidation needs to be done
+			 * for prefetch of next data.
+			 */
+			break;
+		}
+
+		/*
+		 * Prefetch a cacheline (64B) packet header data of current SKB.
+		 */
+		rx_idx = rx_info->rx_idx;
+		rx_buf = &rx_info->rx_buf_pool[rx_idx];
+
+		/*
+		 * Re-Invalidate the buffer before read since
+		 * speculative prefetch by CPU may have occurred.
+		 */
+		frame_length = syn_dp_gmac_get_rx_desc_frame_length(status);
+		dmac_inv_range((void *)rx_buf->map_addr_virt,
+			(void *)(((uint8_t *)rx_buf->map_addr_virt) + frame_length));
+		prefetch((void *)rx_buf->map_addr_virt);
+
+		rx_next_idx = syn_dp_rx_inc_index(rx_idx, 1);
+		rx_desc_next = rx_info->rx_desc + rx_next_idx;
+
+		/*
+		 * Prefetch the next descriptor, assuming the next descriptor is available
+		 * for us to read.
+		 */
+		prefetch(rx_desc_next);
+
+		rx_skb = rx_buf->skb;
+		next_skb_ptr = (uint8_t *)rx_info->rx_buf_pool[rx_next_idx].skb;
+		extstatus = rx_desc->extstatus;
+
+		/*
+		 * Firstly check for linear packets without errors.
+		 */
+		if (likely(syn_dp_gmac_is_rx_desc_linear_and_valid(status, extstatus))) {
+			/*
+			 * We have a pkt to process get the frame length
+			 */
+			if (likely(!rx_info->page_mode)) {
+				/*
+				 * Valid packet, collect stats
+				 */
+				rx_packets++;
+				rx_bytes += frame_length;
+
+				skb_put(rx_skb, frame_length);
+				if (likely(!(extstatus & DESC_RX_CHK_SUM_BYPASS))) {
+					rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
+				}
+
+				/*
+				 * Size of sk_buff is 184B, which requires 3 cache lines
+				 * in ARM core (Each cache line is of size 64B). napi_gro_receive
+				 * and skb_put are majorly using variables from sk_buff structure
+				 * which falls on either first or third cache lines. So, prefetching
+				 * first and third cache line provides better performance.
+				 */
+				if (likely(next_skb_ptr)) {
+					prefetch(next_skb_ptr + SYN_DP_RX_SKB_CACHE_LINE1);
+					prefetch(next_skb_ptr + SYN_DP_RX_SKB_CACHE_LINE3);
+				}
+
+				/*
+				 * Type_trans and deliver to linux
+				 */
+				rx_skb->protocol = eth_type_trans(rx_skb, netdev);
+
+				/*
+				 * Deliver the packet to linux
+				 */
+				if (is_gro_enabled) {
+					napi_gro_receive(&rx_info->napi_rx, rx_skb);
+				} else {
+					netif_receive_skb(rx_skb);
+				}
+
+				goto next_desc;
+			}
+
+			/*
+			 * Process packet when page_mode is enabled.
+			 */
+			frag = &skb_shinfo(rx_skb)->frags[0];
+
+			rx_skb->len = frame_length;
+			rx_skb->data_len = frame_length;
+			rx_skb->truesize = PAGE_SIZE;
+
+			skb_fill_page_desc(rx_skb, 0, skb_frag_page(frag), 0, frame_length);
+
+			/*
+			 * Move ethernet header data to skb data area.
+			 */
+			if (unlikely(!pskb_may_pull(rx_skb, ETH_HLEN))) {
+				dev_kfree_skb_any(rx_skb);
+				atomic64_inc((atomic64_t *)&rx_info->rx_stats.rx_errors);
+
+				/*
+				 * TODO: Error counter for this case.
+				 */
+				goto next_desc;
+			}
+
+			rx_skb->protocol = eth_type_trans(rx_skb, netdev);
+			if (likely(!(extstatus & DESC_RX_CHK_SUM_BYPASS))) {
+				rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
+			}
+
+			/*
+			 * Collect statistics.
+			 */
+			rx_packets++;
+			rx_bytes += frame_length;
+
+			if (likely(next_skb_ptr)) {
+				prefetch(next_skb_ptr + SYN_DP_RX_SKB_CACHE_LINE1);
+				prefetch(next_skb_ptr + SYN_DP_RX_SKB_CACHE_LINE3);
+			}
+
+			if (is_gro_enabled) {
+				napi_gro_receive(&rx_info->napi_rx, rx_skb);
+			} else {
+				netif_receive_skb(rx_skb);
+			}
+
+			goto next_desc;
+		}
+
+		/*
+		 * Packet is scattered between multiple descriptors.
+		 */
+		if (likely(syn_dp_gmac_is_rx_desc_valid(status, extstatus))) {
+			uint32_t rx_scatter_packets = 0, rx_scatter_bytes = 0;
+
+			if (unlikely(!syn_dp_handle_jumbo_packets(rx_info, rx_skb, status))) {
+				syn_dp_rx_process_drop(rx_info, status, rx_skb, true);
+				goto next_desc;
+			}
+
+			if ((status & DESC_RX_LAST) != DESC_RX_LAST) {
+				goto next_desc;
+			}
+
+			/*
+			 * Send packet to upper stack only for last descriptor.
+			 */
+			if (unlikely(rx_info->page_mode)) {
+				if (unlikely(!pskb_may_pull(rx_info->head, ETH_HLEN))) {
+					/*
+					 * Discard the SKB that we have been building,
+					 * in addition to the SKB linked to current descriptor.
+					 */
+					syn_dp_rx_process_drop(rx_info, status, rx_skb, true);
+					goto next_desc;
+				}
+			}
+
+			rx_info->head->protocol = eth_type_trans(rx_info->head, netdev);
+			if (likely(!(extstatus & DESC_RX_CHK_SUM_BYPASS))) {
+				rx_info->head->ip_summed = CHECKSUM_UNNECESSARY;
+			}
+
+			rx_info->prev_len = 0;
+			rx_info->tail = NULL;
+
+			rx_scatter_packets++;
+			rx_packets++;
+
+			rx_scatter_bytes += rx_info->head->len;
+			rx_bytes += rx_info->head->len;
+
+			atomic64_add(rx_scatter_packets, (atomic64_t *)&rx_info->rx_stats.rx_scatter_packets);
+			atomic64_add(rx_scatter_bytes, (atomic64_t *)&rx_info->rx_stats.rx_scatter_bytes);
+
+			if (likely(next_skb_ptr)) {
+				prefetch(next_skb_ptr + SYN_DP_RX_SKB_CACHE_LINE1);
+				prefetch(next_skb_ptr + SYN_DP_RX_SKB_CACHE_LINE3);
+			}
+
+			if (is_gro_enabled) {
+				napi_gro_receive(&rx_info->napi_rx, rx_info->head);
+			} else {
+				netif_receive_skb(rx_info->head);
+			}
+
+			rx_info->head = NULL;
+			goto next_desc;
+		}
+
+		/*
+		 * This is a linear packet with error, drop it.
+		 */
+		syn_dp_rx_process_drop(rx_info, status, rx_skb, false);
+next_desc:
+
+		/*
+		 * Reset Rx descriptor and update rx_info information
+		 */
+		syn_dp_rx_reset_one_desc(rx_desc);
+		rx_info->rx_buf_pool[rx_idx].skb = NULL;
+		rx_info->rx_buf_pool[rx_idx].map_addr_virt = 0;
+		rx_info->rx_idx = syn_dp_rx_inc_index(rx_idx, 1);
+		atomic_dec((atomic_t *)&rx_info->busy_rx_desc_cnt);
+		busy--;
+		rx_desc = rx_desc_next;
+	} while (likely(busy > 0));
+
+	/*
+	 * Increment total rx packets and byte count.
+	 */
+	atomic64_add(rx_packets, (atomic64_t *)&rx_info->rx_stats.rx_packets);
+	atomic64_add(rx_bytes, (atomic64_t *)&rx_info->rx_stats.rx_bytes);
+
+	return budget - busy;
+}
diff --git a/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_rx.h b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_rx.h
new file mode 100644
index 0000000..8f0105e
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_rx.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_SYN_DP_RX__
+#define __NSS_DP_SYN_DP_RX__
+
+#define SYN_DP_NAPI_BUDGET_RX		64
+#define SYN_DP_RX_DESC_SIZE		2048	/* Rx Descriptors needed in the descriptor pool/queue */
+#define SYN_DP_RX_DESC_MAX_INDEX	(SYN_DP_RX_DESC_SIZE - 1)
+
+/*
+ * Size of sk_buff is 184B, which requires 3 cache lines
+ * in ARM core (Each cache line is of size 64B). napi_gro_receive
+ * and skb_put are majorly using variables from sk_buff structure
+ * which falls on either first or third cache lines. So, prefetching
+ * first and third cache line provides better performance.
+ */
+#define SYN_DP_RX_SKB_CACHE_LINE1	64
+#define SYN_DP_RX_SKB_CACHE_LINE3	128
+
+/*
+ * syn_dp_rx_buf
+ */
+struct syn_dp_rx_buf {
+	struct sk_buff *skb;	/* Buffer pointer populated to Rx/Tx dma desc */
+	size_t map_addr_virt;	/* Virtual address of buffer populated to Rx/Tx dma desc */
+};
+
+/*
+ * syn_dp_info_rx
+ */
+struct syn_dp_info_rx {
+	struct napi_struct napi_rx;	/* Rx NAPI */
+	void __iomem *mac_base;		/* MAC base for register read/write */
+	struct dma_desc_rx *rx_desc;	/* start address of RX descriptors ring or
+					   chain, this is used by the driver */
+	uint32_t busy_rx_desc_cnt;	/* Number of Rx Descriptors owned by
+					   DMA at any given time */
+	uint32_t rx_refill_idx;		/* index of the rx descriptor owned by DMA */
+	uint32_t rx_idx;		/* index of the rx descriptor next available with driver */
+	struct syn_dp_rx_buf rx_buf_pool[SYN_DP_RX_DESC_SIZE];
+					/* Rx skb pool helping RX DMA descriptors */
+	struct nss_dp_hal_gmac_stats_rx rx_stats;
+					/* GMAC driver Rx statistics */
+	struct net_device *netdev;	/* Net-device corresponding to the GMAC */
+	struct device *dev;		/* Platform device corresponding to the GMAC */
+	struct sk_buff *head;		/* Head of the skb list in case of Scatter-Gather frame */
+	struct sk_buff *tail;		/* Tail of the skb list in case of Scatter-Gather frame */
+	bool page_mode;			/* page_mode: true for nr_frag and false for fraglist */
+	uint32_t alloc_buf_len;		/* Skb alloc length, depends based on page/fraglist mode */
+	uint32_t prev_len;		/* Stores frame_length of previous descriptor */
+};
+
+/*
+ * syn_dp_rx_inc_index()
+ * 	Increment Rx descriptor index
+ */
+static inline int syn_dp_rx_inc_index(uint32_t index, uint32_t inc)
+{
+	return ((index + inc) & SYN_DP_RX_DESC_MAX_INDEX);
+}
+
+#endif /*  __NSS_DP_SYN_DP_RX__ */
diff --git a/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_tx.c b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_tx.c
new file mode 100644
index 0000000..0c367b0
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_tx.c
@@ -0,0 +1,587 @@
+/*
+ * Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/netdevice.h>
+#include <nss_dp_dev.h>
+#include <asm/cacheflush.h>
+#include "syn_dma_reg.h"
+
+/*
+ * syn_dp_tx_error_cnt()
+ *	Set the error counters.
+ */
+static inline void syn_dp_tx_error_cnt(struct syn_dp_info_tx *tx_info, uint32_t status)
+{
+	atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_errors);
+	(status & DESC_TX_TIMEOUT) ? atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_jabber_timeout_errors) : 0;
+	(status & DESC_TX_FRAME_FLUSHED) ? atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_frame_flushed_errors) : 0;
+	(status & DESC_TX_LOST_CARRIER) ? atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_loss_of_carrier_errors) : 0;
+	(status & DESC_TX_NO_CARRIER) ? atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_no_carrier_errors) : 0;
+	(status & DESC_TX_LATE_COLLISION) ? atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_late_collision_errors) : 0;
+	(status & DESC_TX_EXC_COLLISIONS) ? atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_excessive_collision_errors) : 0;
+	(status & DESC_TX_EXC_DEFERRAL) ? atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_excessive_deferral_errors) : 0;
+	(status & DESC_TX_UNDERFLOW) ? atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_underflow_errors) : 0;
+	(status & DESC_TX_IPV4_CHK_ERROR) ? atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_ip_header_errors) : 0;
+	(status & DESC_TX_PAY_CHK_ERROR) ? atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_ip_payload_errors) : 0;
+}
+
+/*
+ * syn_dp_tx_clear_buf_entry()
+ *	Clear the Tx info after Tx is over.
+ */
+static inline void syn_dp_tx_clear_buf_entry(struct syn_dp_info_tx *tx_info, uint32_t tx_skb_index)
+{
+	tx_info->tx_buf_pool[tx_skb_index].len = 0;
+	tx_info->tx_buf_pool[tx_skb_index].skb = NULL;
+	tx_info->tx_buf_pool[tx_skb_index].shinfo_addr_virt = 0;
+}
+
+/*
+ * syn_dp_tx_set_desc_sg()
+ *	Populate the tx desc structure with the buffer address for SG packets
+ */
+static inline struct dma_desc_tx *syn_dp_tx_set_desc_sg(struct syn_dp_info_tx *tx_info,
+					   uint32_t buffer, unsigned int length, uint32_t status)
+{
+	uint32_t tx_idx = tx_info->tx_idx;
+	struct dma_desc_tx *txdesc = tx_info->tx_desc + tx_idx;
+
+#ifdef SYN_DP_DEBUG
+	BUG_ON(atomic_read((atomic_t *)&tx_info->busy_tx_desc_cnt) > SYN_DP_TX_DESC_SIZE);
+	BUG_ON(txdesc != (tx_info->tx_desc + tx_idx));
+	BUG_ON(!syn_dp_gmac_is_tx_desc_empty(txdesc));
+	BUG_ON(syn_dp_gmac_is_tx_desc_owned_by_dma(txdesc));
+#endif
+
+	if (likely(length <= SYN_DP_MAX_DESC_BUFF_LEN)) {
+		txdesc->length  = ((length << DESC_SIZE1_SHIFT) & DESC_SIZE1_MASK);
+		txdesc->buffer2 = 0;
+	} else {
+		txdesc->length  = (SYN_DP_MAX_DESC_BUFF_LEN << DESC_SIZE1_SHIFT) & DESC_SIZE1_MASK;
+		txdesc->length |= ((length - SYN_DP_MAX_DESC_BUFF_LEN) << DESC_SIZE2_SHIFT) & DESC_SIZE2_MASK;
+		txdesc->buffer2 = buffer + SYN_DP_MAX_DESC_BUFF_LEN;
+	}
+
+	txdesc->buffer1 = buffer;
+
+	txdesc->status = (status | ((tx_idx == (SYN_DP_TX_DESC_SIZE - 1)) ? DESC_TX_DESC_END_OF_RING : 0));
+
+	tx_info->tx_idx = syn_dp_tx_inc_index(tx_idx, 1);
+	return txdesc;
+}
+
+/*
+ * syn_dp_tx_process_nr_frags()
+ *	Process nr frags for the SG packets
+ */
+static inline struct dma_desc_tx *syn_dp_tx_process_nr_frags(struct syn_dp_info_tx *tx_info,
+				struct sk_buff *skb, uint32_t *total_length, uint32_t nr_frags)
+{
+	struct dma_desc_tx *tx_desc;
+	dma_addr_t dma_addr;
+	unsigned int length, i = 0;
+
+	do {
+		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i++];
+		void *frag_addr = skb_frag_address(frag);
+		length = skb_frag_size(frag);
+
+#ifdef SYN_DP_DEBUG
+		BUG_ON(!length);
+#endif
+
+		dma_addr = (dma_addr_t)virt_to_phys(frag_addr);
+
+		dmac_clean_range_no_dsb(frag_addr, frag_addr + length);
+
+		*total_length += length;
+		tx_desc = syn_dp_tx_set_desc_sg(tx_info, dma_addr, length, DESC_OWN_BY_DMA);
+	} while ( i < nr_frags);
+
+	return tx_desc;
+}
+
+/*
+ * syn_dp_tx_nr_frags()
+ *	TX routine for Synopsys GMAC SG packets with nr frags
+ */
+int syn_dp_tx_nr_frags(struct syn_dp_info_tx *tx_info, struct sk_buff *skb)
+{
+	dma_addr_t dma_addr;
+	unsigned int length = skb_headlen(skb);
+	struct dma_desc_tx *first_desc, *tx_desc;
+	unsigned int desc_needed = 0, total_len = 0;
+	unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
+	uint32_t last_idx;
+
+#ifdef SYN_DP_DEBUG
+	BUG_ON(nr_frags > MAX_SKB_FRAGS);
+	BUG_ON(!length);
+#endif
+
+	/*
+	 * Total descriptor needed will be sum of number of nr_frags and head skb.
+	 */
+	desc_needed = 1 + nr_frags;
+
+	/*
+	 * If we don't have enough tx descriptor for this pkt, return busy.
+	 */
+	if (unlikely((SYN_DP_TX_DESC_SIZE - atomic_read((atomic_t *)&tx_info->busy_tx_desc_cnt)) < desc_needed)) {
+		atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_desc_not_avail);
+		netdev_dbg(tx_info->netdev, "Not enough descriptors available %d", desc_needed);
+		return NETDEV_TX_BUSY;
+	}
+
+	/*
+	 * Flush the dma for non-paged skb data
+	 */
+	dma_addr = (dma_addr_t)virt_to_phys(skb->data);
+	dmac_clean_range_no_dsb((void *)skb->data, (void *)(skb->data + length));
+
+	total_len = length;
+
+	/*
+	 * Fill the non paged data (skb->data) in the first descriptor.
+	 * We defer setting the desc_own_by_dma for first fragment until
+	 * all the descriptors for this frame are ready.
+	 */
+	first_desc = syn_dp_tx_set_desc_sg(tx_info, dma_addr, length, DESC_TX_FIRST);
+
+	/*
+	 * Fill other fragments which are part of nr_frags in the remaining descriptors
+	 * and returns the last descriptor.
+	 */
+	tx_desc = syn_dp_tx_process_nr_frags(tx_info, skb, &total_len, nr_frags);
+
+	/*
+	 * Save the tx index of the last descriptor of the segment
+	 */
+	last_idx = ((tx_info->tx_idx - 1) & SYN_DP_TX_DESC_MAX_INDEX);
+
+
+	/*
+	 * Fill the buffer pool in the last segment of the fragment only
+	 * instead of filling in all the descriptors for the fragments
+	 */
+	tx_info->tx_buf_pool[last_idx].skb = skb;
+	tx_info->tx_buf_pool[last_idx].len = total_len;
+	tx_info->tx_buf_pool[last_idx].shinfo_addr_virt = (size_t)skb->end;
+
+	/*
+	 * For the last fragment, Enable the interrupt and set LS bit
+	 */
+	tx_desc->status |= (DESC_TX_LAST | DESC_TX_INT_ENABLE);
+
+	/*
+	 * Ensure all write completed before setting own by dma bit so when gmac
+	 * HW takeover this descriptor, all the fields are filled correctly
+	 */
+	wmb();
+
+	/*
+	 * We've now written all of the descriptors in our scatter-gather list
+	 * and need to write the "OWN" bit of the first one to mark the chain
+	 * as available to the DMA engine. Also, add checksum calculation bit
+	 * for the first descriptor if needed
+	 */
+	first_desc->status |= (DESC_OWN_BY_DMA | ((skb->ip_summed == CHECKSUM_PARTIAL) ? DESC_TX_CIS_TCP_PSEUDO_CS : 0));
+
+	atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_nr_frags_pkts);
+	atomic_add(desc_needed, (atomic_t *)&tx_info->busy_tx_desc_cnt);
+	syn_resume_dma_tx(tx_info->mac_base);
+
+	return 0;
+}
+
+/*
+ * syn_dp_tx_frag_list()
+ *	TX routine for Synopsys GMAC SG packets with frag lists
+ */
+int syn_dp_tx_frag_list(struct syn_dp_info_tx *tx_info, struct sk_buff *skb)
+{
+	dma_addr_t dma_addr;
+	struct sk_buff *iter_skb;
+	struct dma_desc_tx *first_desc, *tx_desc;
+	unsigned int length = skb_headlen(skb);
+	unsigned int desc_needed = 1, total_len = 0;
+	unsigned int nr_frags = skb_shinfo(skb)->nr_frags, fraglist_nr_frags = 0;
+	uint32_t last_idx;
+
+	/*
+	 * When skb is fragmented, count the number of descriptors needed
+	 */
+	if (unlikely(nr_frags)) {
+#ifdef SYN_DP_DEBUG
+		BUG_ON(nr_frags > MAX_SKB_FRAGS);
+		BUG_ON(!length);
+#endif
+		desc_needed += nr_frags;
+	}
+
+	/*
+	 * Walk through fraglist skbs, also making note of nr_frags
+	 */
+	skb_walk_frags(skb, iter_skb) {
+		fraglist_nr_frags = skb_shinfo(iter_skb)->nr_frags;
+
+#ifdef SYN_DP_DEBUG
+		/* It is unlikely below check hits, BUG_ON */
+		BUG_ON(fraglist_nr_frags > MAX_SKB_FRAGS);
+#endif
+		/* One descriptor for skb->data and more for nr_frags */
+		desc_needed +=  (1 + fraglist_nr_frags);
+	}
+
+	/*
+	 * If we don't have enough tx descriptor for this pkt, return busy.
+	 */
+	if (unlikely((SYN_DP_TX_DESC_SIZE - atomic_read((atomic_t *)&tx_info->busy_tx_desc_cnt)) < desc_needed)) {
+		atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_desc_not_avail);
+		netdev_dbg(tx_info->netdev, "Not enough descriptors available %d", desc_needed);
+		return NETDEV_TX_BUSY;
+	}
+
+	dma_addr = (dma_addr_t)virt_to_phys(skb->data);
+
+	/*
+	 * Flush the data area of the head skb
+	 */
+	dmac_clean_range_no_dsb((void *)skb->data, (void *)(skb->data + length));
+
+	total_len = length;
+
+	/*
+	 * Fill the first skb of the frag list chain in the first descriptor
+	 * We defer setting the desc_own_by_dma bit for first fragment until
+	 * all the descriptors for this frame are ready.
+	 */
+	first_desc = syn_dp_tx_set_desc_sg(tx_info, dma_addr, length, DESC_TX_FIRST);
+
+	/*
+	 * Fill other fragments which are part of nr_frags in the remaining descriptors
+	 * and returns the last descriptor.
+	 */
+	if (unlikely(nr_frags)) {
+		tx_desc = syn_dp_tx_process_nr_frags(tx_info, skb, &total_len, nr_frags);
+	}
+
+	/*
+	 * Walk through fraglist skbs, also making note of nr_frags and filling it in descriptors
+	 */
+	skb_walk_frags(skb, iter_skb) {
+		length = skb_headlen(iter_skb);
+
+#ifdef SYN_DP_DEBUG
+		BUG_ON(!length);
+#endif
+
+		dma_addr = (dma_addr_t)virt_to_phys(iter_skb->data);
+
+		dmac_clean_range_no_dsb((void *)iter_skb->data, (void *)(iter_skb->data + length));
+
+		total_len += length;
+
+		/*
+		 * Fill the non paged data skb->data.
+		 */
+		tx_desc = syn_dp_tx_set_desc_sg(tx_info, dma_addr, length, DESC_OWN_BY_DMA);
+
+		/*
+		 * Check if nr_frags is available for the skb. If so, fill the
+		 * fragments in the descriptors else, continue
+		 */
+		fraglist_nr_frags = skb_shinfo(iter_skb)->nr_frags;
+
+		/*
+		 * Fill other fragments which are part of nr_frags in the remaining descriptors
+		 * and returns the last descriptor.
+		 */
+		if (unlikely(fraglist_nr_frags)) {
+			tx_desc = syn_dp_tx_process_nr_frags(tx_info, iter_skb, &total_len, fraglist_nr_frags);
+		}
+	}
+
+	/*
+	 * Save the tx index of the last descriptor of the segment
+	 */
+	last_idx = ((tx_info->tx_idx - 1) & SYN_DP_TX_DESC_MAX_INDEX);
+
+
+	/*
+	 * Fill the buffer pool in the last segment of the fragment only
+	 * instead of filling in all the descriptors for the fragments
+	 */
+	tx_info->tx_buf_pool[last_idx].skb = skb;
+	tx_info->tx_buf_pool[last_idx].len = total_len;
+	tx_info->tx_buf_pool[last_idx].shinfo_addr_virt = (size_t)skb->end;
+
+	/*
+	 * For the last fragment, Enable the interrupt and set LS bit
+	 */
+	tx_desc->status |= (DESC_TX_LAST | DESC_TX_INT_ENABLE);
+
+	/*
+	 * Ensure all write completed before setting own by dma bit so when gmac
+	 * HW takeover this descriptor, all the fields are filled correctly
+	 */
+	wmb();
+
+	/*
+	 * We've now written all of the descriptors in our scatter-gather list
+	 * and need to write the "OWN" bit of the first one to mark the chain
+	 * as available to the DMA engine. Also, add checksum calculation
+	 * bit in the first descriptor if needed.
+	 */
+	first_desc->status |= (DESC_OWN_BY_DMA | ((skb->ip_summed == CHECKSUM_PARTIAL) ? DESC_TX_CIS_TCP_PSEUDO_CS : 0));
+
+	atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_fraglist_pkts);
+	atomic_add(desc_needed, (atomic_t *)&tx_info->busy_tx_desc_cnt);
+	syn_resume_dma_tx(tx_info->mac_base);
+
+	return 0;
+}
+
+/*
+ * syn_dp_tx_set_desc()
+ *	Populate the tx desc structure with the buffer address.
+ */
+static inline void syn_dp_tx_set_desc(struct syn_dp_info_tx *tx_info,
+					   uint32_t buffer, struct sk_buff *skb, uint32_t offload_needed,
+					   uint32_t status)
+{
+	uint32_t tx_idx = tx_info->tx_idx;
+	struct dma_desc_tx *txdesc = tx_info->tx_desc + tx_idx;
+	unsigned int length = skb->len;
+
+#ifdef SYN_DP_DEBUG
+	BUG_ON(atomic_read((atomic_t *)&tx_info->busy_tx_desc_cnt) > SYN_DP_TX_DESC_SIZE);
+	BUG_ON(txdesc != (tx_info->tx_desc + tx_idx));
+	BUG_ON(!syn_dp_gmac_is_tx_desc_empty(txdesc));
+	BUG_ON(syn_dp_gmac_is_tx_desc_owned_by_dma(txdesc));
+#endif
+
+	if (likely(length <= SYN_DP_MAX_DESC_BUFF_LEN)) {
+		txdesc->length = ((length << DESC_SIZE1_SHIFT) & DESC_SIZE1_MASK);
+		txdesc->buffer2 = 0;
+	} else {
+		txdesc->length = (SYN_DP_MAX_DESC_BUFF_LEN << DESC_SIZE1_SHIFT) & DESC_SIZE1_MASK;
+		txdesc->length |= ((length - SYN_DP_MAX_DESC_BUFF_LEN) << DESC_SIZE2_SHIFT) & DESC_SIZE2_MASK;
+		txdesc->buffer2 = buffer + SYN_DP_MAX_DESC_BUFF_LEN;
+	}
+
+	txdesc->buffer1 = buffer;
+
+	tx_info->tx_buf_pool[tx_idx].skb = skb;
+	tx_info->tx_buf_pool[tx_idx].len = length;
+	tx_info->tx_buf_pool[tx_idx].shinfo_addr_virt = (size_t)skb->end;
+
+	/*
+	 * Ensure all write completed before setting own by dma bit so when gmac
+	 * HW takeover this descriptor, all the fields are filled correctly
+	 */
+	wmb();
+
+	txdesc->status = (status | ((offload_needed) ? DESC_TX_CIS_TCP_PSEUDO_CS : 0) | ((tx_idx == (SYN_DP_TX_DESC_SIZE - 1)) ? DESC_TX_DESC_END_OF_RING : 0));
+
+	tx_info->tx_idx = syn_dp_tx_inc_index(tx_idx, 1);
+}
+
+/*
+ * syn_dp_tx_complete()
+ *	Xmit complete, clear descriptor and free the skb
+ */
+int syn_dp_tx_complete(struct syn_dp_info_tx *tx_info, int budget)
+{
+	int busy;
+	uint32_t status;
+	struct dma_desc_tx *desc = NULL;
+	struct sk_buff *skb;
+	uint32_t tx_skb_index, len;
+	uint32_t tx_packets = 0, total_len = 0;
+	uint32_t count = 0;
+	uint32_t free_idx;
+	struct syn_dp_tx_buf *tx_buf;
+	struct netdev_queue *nq;
+
+	busy = atomic_read((atomic_t *)&tx_info->busy_tx_desc_cnt);
+
+	if (unlikely(!busy)) {
+
+		/*
+		 * No descriptors are held by GMAC DMA, we are done
+		 */
+		netdev_dbg(tx_info->netdev, "No descriptors held by DMA");
+		return 0;
+	}
+
+	if (likely(busy > budget)) {
+		busy = budget;
+	}
+
+	tx_skb_index = syn_dp_tx_comp_index_get(tx_info);
+	do {
+		desc = syn_dp_tx_comp_desc_get(tx_info);
+		status = desc->status;
+		if (unlikely(syn_dp_gmac_is_tx_desc_owned_by_dma(status))) {
+
+			/*
+			 * Descriptor still held by gmac dma, so we are done.
+			 */
+			break;
+		}
+
+
+		if (likely(status & DESC_TX_LAST)) {
+			tx_skb_index = syn_dp_tx_comp_index_get(tx_info);
+			tx_buf = &tx_info->tx_buf_pool[tx_skb_index];
+			skb = tx_info->skb_free_list[count] = tx_buf->skb;
+			len = tx_buf->len;
+
+#ifdef SYN_DP_DEBUG
+			BUG_ON(!skb);
+#endif
+
+			tx_info->shinfo_addr_virt[count++] = tx_buf->shinfo_addr_virt;
+			syn_dp_tx_clear_buf_entry(tx_info, tx_skb_index);
+
+			if (likely(!(status & DESC_TX_ERROR))) {
+
+				/*
+				 * No error, record tx pkts/bytes and collision.
+				 */
+				tx_packets++;
+				total_len += len;
+			}
+		}
+
+		if (unlikely(status & DESC_TX_ERROR)) {
+			/*
+			 * Some error happened, collect error statistics.
+			 */
+			syn_dp_tx_error_cnt(tx_info, status);
+		}
+
+		tx_info->tx_comp_idx = syn_dp_tx_inc_index(tx_info->tx_comp_idx, 1);
+
+		/*
+		 * Busy is used to count the workdone with assigned budget.
+		 */
+		atomic_dec((atomic_t *)&tx_info->busy_tx_desc_cnt);
+	} while (--busy);
+
+	/*
+	 * Prefetching the shinfo area before releasing to skb recycler gives benefit
+	 * in performance.
+	 * All the completed skb's shinfo are prefetched and skb's are freed in batch.
+	 */
+	for (free_idx = 0; free_idx < count; free_idx++) {
+		if (likely((free_idx + 1) < count)) {
+			prefetch((void *)tx_info->shinfo_addr_virt[free_idx+1]);
+		}
+		dev_kfree_skb_any(tx_info->skb_free_list[free_idx]);
+		tx_info->skb_free_list[free_idx] = NULL;
+		tx_info->shinfo_addr_virt[free_idx] = 0;
+	}
+
+	atomic64_add(tx_packets, (atomic64_t *)&tx_info->tx_stats.tx_packets);
+	atomic64_add(total_len, (atomic64_t *)&tx_info->tx_stats.tx_bytes);
+
+	nq = netdev_get_tx_queue(tx_info->netdev, SYN_DP_QUEUE_INDEX);
+
+	/*
+	 * Wake up queue if stopped earlier due to lack of descriptors
+	 */
+	if (unlikely(netif_tx_queue_stopped(nq)) && netif_carrier_ok(tx_info->netdev)) {
+		netif_wake_queue(tx_info->netdev);
+	}
+
+	return budget - busy;
+}
+
+/*
+ * syn_dp_tx_sg()
+ *	Tx routine for Synopsys GMAC scatter gather packets
+ */
+int syn_dp_tx_sg(struct syn_dp_info_tx *tx_info, struct sk_buff *skb)
+{
+	struct net_device *netdev = tx_info->netdev;
+	bool has_frag_list;
+	unsigned int nr_frags;
+
+	has_frag_list = skb_has_frag_list(skb);
+	nr_frags = skb_shinfo(skb)->nr_frags;
+
+	/*
+	 * Handle SG for below skb types.
+	 * 1. skb has fraglist
+	 * 2. skb has fraglist and any of the fragments can have nr_frags
+	 */
+	if (has_frag_list) {
+		return syn_dp_tx_frag_list(tx_info, skb);
+	}
+
+	/*
+	 * Handle SG for nr_frags
+	 */
+	if (nr_frags) {
+		return syn_dp_tx_nr_frags(tx_info, skb);
+	}
+
+	netdev_dbg(netdev, "Not a valid non-linear packet");
+	return -1;
+}
+
+/*
+ * syn_dp_tx()
+ *	TX routine for Synopsys GMAC
+ */
+int syn_dp_tx(struct syn_dp_info_tx *tx_info, struct sk_buff *skb)
+{
+	struct net_device *netdev = tx_info->netdev;
+	dma_addr_t dma_addr;
+
+	/*
+	 * Check if it's a Scatter Gather packet
+	 */
+	if (unlikely(skb_is_nonlinear(skb))) {
+		return syn_dp_tx_sg(tx_info, skb);
+	}
+
+	/*
+	 * Linear skb processing
+	 */
+	if (unlikely((SYN_DP_TX_DESC_SIZE - atomic_read((atomic_t *)&tx_info->busy_tx_desc_cnt)) < 1)) {
+		atomic64_inc((atomic64_t *)&tx_info->tx_stats.tx_desc_not_avail);
+		netdev_dbg(netdev, "Not enough descriptors available");
+		return NETDEV_TX_BUSY;
+	}
+
+	dma_addr = (dma_addr_t)virt_to_phys(skb->data);
+
+	dmac_clean_range_no_dsb((void *)skb->data, (void *)(skb->data + skb->len));
+
+	/*
+	 * Queue packet to the GMAC rings
+	 */
+	syn_dp_tx_set_desc(tx_info, dma_addr, skb, (skb->ip_summed == CHECKSUM_PARTIAL),
+			(DESC_TX_LAST | DESC_TX_FIRST | DESC_TX_INT_ENABLE | DESC_OWN_BY_DMA));
+
+	syn_resume_dma_tx(tx_info->mac_base);
+	atomic_inc((atomic_t *)&tx_info->busy_tx_desc_cnt);
+	return 0;
+}
diff --git a/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_tx.h b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_tx.h
new file mode 100644
index 0000000..6a5b88a
--- /dev/null
+++ b/qca-nss-dp/hal/dp_ops/syn_gmac_dp/syn_dp_tx.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_SYN_DP_TX__
+#define __NSS_DP_SYN_DP_TX__
+
+#define SYN_DP_NAPI_BUDGET_TX		64
+#define SYN_DP_TX_DESC_SIZE		8192	/* Tx Descriptors needed in the descriptor pool/queue */
+#define SYN_DP_TX_DESC_MAX_INDEX	(SYN_DP_TX_DESC_SIZE - 1)
+#define SYN_DP_TX_INVALID_DESC_INDEX	SYN_DP_TX_DESC_SIZE
+
+/*
+ * syn_dp_tx_buf
+ */
+struct syn_dp_tx_buf {
+	struct sk_buff *skb;	/* Buffer pointer populated to Tx dma desc */
+	uint32_t len;		/* Length of the buffer provided to descriptor */
+	size_t shinfo_addr_virt;	/* Buffer address to prefetch the shinfo
+						during Tx complete*/
+};
+
+/*
+ * syn_dp_info_tx
+ */
+struct syn_dp_info_tx {
+	struct napi_struct napi_tx;	/* Tx NAPI */
+	void __iomem *mac_base;		/* MAC base for register read/write */
+	struct dma_desc_tx *tx_desc;	/* start address of TX descriptors ring or
+						chain, this is used by the driver */
+	uint32_t busy_tx_desc_cnt;	/* Number of Tx Descriptors owned by
+						DMA at any given time */
+	uint32_t tx_comp_idx;		/* index of the tx descriptor owned by DMA */
+	uint32_t tx_idx;		/* index of the tx descriptor next available with driver */
+	struct syn_dp_tx_buf tx_buf_pool[SYN_DP_TX_DESC_SIZE];
+					/* Tx skb pool helping TX DMA descriptors */
+	struct nss_dp_hal_gmac_stats_tx tx_stats;
+					/* GMAC driver Tx statistics */
+	struct net_device *netdev;	/* Net-device corresponding to the GMAC */
+	struct device *dev;		/* Platform device corresponding to the GMAC */
+	struct sk_buff *skb_free_list[SYN_DP_NAPI_BUDGET_TX];
+					/* Array to hold SKBs before free during Tx completion */
+	size_t shinfo_addr_virt[SYN_DP_NAPI_BUDGET_TX];
+					/* Array to hold SKB end pointer to be
+						prefetched during Tx completion */
+};
+
+/*
+ * syn_dp_tx_inc_index()
+ * 	Increment Tx descriptor index
+ */
+static inline uint32_t syn_dp_tx_inc_index(uint32_t index, uint32_t inc)
+{
+	return ((index + inc) & SYN_DP_TX_DESC_MAX_INDEX);
+}
+
+/*
+ * syn_dp_tx_comp_desc_get()
+ * 	Get the Tx completed descriptor
+ */
+static inline struct dma_desc_tx *syn_dp_tx_comp_desc_get(struct syn_dp_info_tx *tx_info)
+{
+	return tx_info->tx_desc + tx_info->tx_comp_idx;
+}
+
+/*
+ * syn_dp_tx_comp_index_get()
+ * 	Get the Tx completion index
+ */
+static inline uint32_t syn_dp_tx_comp_index_get(struct syn_dp_info_tx *tx_info)
+{
+	return tx_info->tx_comp_idx;
+}
+
+#endif /*  __NSS_DP_SYN_DP_TX__ */
diff --git a/qca-nss-dp/hal/gmac_ops/qcom/qcom_dev.h b/qca-nss-dp/hal/gmac_ops/qcom/qcom_dev.h
new file mode 100644
index 0000000..b5a7320
--- /dev/null
+++ b/qca-nss-dp/hal/gmac_ops/qcom/qcom_dev.h
@@ -0,0 +1,697 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017,2020-2021 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF0
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __QCOM_DEV_H__
+#define __QCOM_DEV_H__
+
+#include <nss_dp_hal_if.h>
+#include "qcom_reg.h"
+#include <fal/fal_mib.h>
+#include <fal/fal_port_ctrl.h>
+
+/*
+ * Subclass for base nss_gmac_haldev
+ */
+struct qcom_hal_dev {
+	struct nss_gmac_hal_dev nghd;	/* Base class */
+	fal_mib_counter_t stats;	/* Stats structure */
+};
+/*
+ * qcom_set_rx_flow_ctrl()
+ */
+static inline void qcom_set_rx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_ENABLE, QCOM_RX_FLOW_ENABLE);
+}
+
+/*
+ * qcom_clear_rx_flow_ctrl()
+ */
+static inline void qcom_clear_rx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_ENABLE, QCOM_RX_FLOW_ENABLE);
+}
+
+/*
+ * qcom_set_tx_flow_ctrl()
+ */
+static inline void qcom_set_tx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_ENABLE, QCOM_TX_FLOW_ENABLE);
+}
+
+/*
+ * qcom_clear_tx_flow_ctrl()
+ */
+static inline void qcom_clear_tx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_ENABLE, QCOM_TX_FLOW_ENABLE);
+}
+
+/*
+ * qcom_clear_mac_ctrl0()
+ */
+static inline void qcom_clear_mac_ctrl0(struct nss_gmac_hal_dev *nghd)
+{
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_CTRL0, 0);
+}
+
+/*
+ * qcom_rx_enable()
+ */
+static inline void qcom_rx_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_ENABLE, QCOM_RX_MAC_ENABLE);
+}
+
+/*
+ * qcom_rx_disable()
+ *	Disable the reception of frames on GMII/MII.
+ *	GMAC receive state machine is disabled after completion of reception of
+ *	current frame.
+ */
+static inline void qcom_rx_disable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_ENABLE, QCOM_RX_MAC_ENABLE);
+}
+
+/*
+ * qcom_tx_enable()
+ */
+static inline void qcom_tx_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_ENABLE, QCOM_TX_MAC_ENABLE);
+}
+
+/*
+ * qcom_tx_disable()
+ *	Disable the transmission of frames on GMII/MII.
+ *	GMAC transmit state machine is disabled after completion of
+ *	transmission of current frame.
+ */
+static inline void qcom_tx_disable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_ENABLE, QCOM_TX_MAC_ENABLE);
+}
+
+/*
+ * qcom_set_full_duplex()
+ */
+static inline void qcom_set_full_duplex(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_ENABLE, QCOM_DUPLEX);
+}
+
+/*
+ * qcom_set_half_duplex()
+ */
+static inline void qcom_set_half_duplex(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_ENABLE, QCOM_DUPLEX);
+}
+
+/*
+ * qcom_set_ipgt()
+ */
+static inline void qcom_set_ipgt(struct nss_gmac_hal_dev *nghd, uint32_t ipgt)
+{
+	uint32_t data;
+
+	data = hal_read_relaxed_reg(nghd->mac_base, QCOM_MAC_CTRL0);
+	data &= ~QCOM_IPGT_POS;
+	ipgt = ipgt << QCOM_IPGT_LSB;
+	data |= ipgt;
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_CTRL0, data);
+}
+
+/*
+ * qcom_set_ipgr()
+ */
+static inline void qcom_set_ipgr(struct nss_gmac_hal_dev *nghd, uint32_t ipgr)
+{
+	uint32_t data;
+
+	data = hal_read_relaxed_reg(nghd->mac_base, QCOM_MAC_CTRL0);
+	data &= ~QCOM_IPGR2_POS;
+	ipgr = ipgr << QCOM_IPGR2_LSB;
+	data |= ipgr;
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_CTRL0, data);
+}
+
+/*
+ * qcom_set_half_thdf_ctrl()
+ */
+static inline void qcom_set_half_thdf_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL0, QCOM_HALF_THDF_CTRL);
+}
+
+/*
+ * qcom_reset_half_thdf_ctrl()
+ */
+static inline void qcom_reset_half_thdf_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL0, QCOM_HALF_THDF_CTRL);
+}
+
+/*
+ * qcom_set_frame_len_chk()
+ */
+static inline void qcom_set_frame_len_chk(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL0, QCOM_FLCHK);
+}
+
+/*
+ * qcom_reset_frame_len_chk()
+ */
+static inline void qcom_reset_frame_len_chk(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL0, QCOM_FLCHK);
+}
+
+/*
+ * qcom_set_abebe()
+ */
+static inline void qcom_set_abebe(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL0, QCOM_ABEBE);
+}
+
+/*
+ * qcom_reset_abebe()
+ */
+static inline void qcom_reset_abebe(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL0, QCOM_ABEBE);
+}
+
+/*
+ * qcom_set_amaxe()
+ */
+static inline void qcom_set_amaxe(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL0, QCOM_AMAXE);
+}
+
+/*
+ * qcom_reset_amaxe()
+ */
+static inline void qcom_reset_amaxe(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL0, QCOM_AMAXE);
+}
+
+/*
+ * qcom_set_bpnb()
+ */
+static inline void qcom_set_bpnb(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL0, QCOM_BPNB);
+}
+
+/*
+ * qcom_reset_bpnb()
+ */
+static inline void qcom_reset_bpnb(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL0, QCOM_BPNB);
+}
+
+/*
+ * qcom_set_nobo()
+ */
+static inline void qcom_set_nobo(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL0, QCOM_NOBO);
+}
+
+/*
+ * qcom_reset_nobo()
+ */
+static inline void qcom_reset_nobo(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL0, QCOM_NOBO);
+}
+
+/*
+ * qcom_set_drbnib_rxok()
+ */
+static inline void qcom_set_drbnib_rxok(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL0, QCOM_DRBNIB_RXOK);
+}
+
+/*
+ * qcom_reset_drbnib_rxok()
+ */
+static inline void qcom_reset_drbnib_rxok(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL0, QCOM_DRBNIB_RXOK);
+}
+
+/*
+ * qcom_set_jam_ipg()
+ */
+static inline void qcom_set_jam_ipg(struct nss_gmac_hal_dev *nghd,
+							uint32_t jam_ipg)
+{
+	uint32_t data;
+
+	data = hal_read_relaxed_reg(nghd->mac_base, QCOM_MAC_CTRL1);
+	data &= ~QCOM_JAM_IPG_POS;
+	jam_ipg = jam_ipg << QCOM_JAM_IPG_LSB;
+	data |= jam_ipg;
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_CTRL1, data);
+}
+
+/*
+ * qcom_set_ctrl1_test_pause()
+ */
+static inline void qcom_set_ctrl1_test_pause(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_TPAUSE);
+}
+
+/*
+ * qcom_reset_ctrl1_test_pause()
+ */
+static inline void qcom_reset_ctrl1_test_pause(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_TPAUSE);
+}
+
+/*
+ * qcom_reset_ctrl1_test_pause()
+ */
+static inline void qcom_set_tctl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_TCTL);
+}
+
+/*
+ * qcom_reset_tctl()
+ */
+static inline void qcom_reset_tctl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_TCTL);
+}
+
+/*
+ * qcom_set_sstct()
+ */
+static inline void qcom_set_sstct(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_SSTCT);
+}
+
+/*
+ * qcom_reset_sstct()
+ */
+static inline void qcom_reset_sstct(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_SSTCT);
+}
+
+/*
+ * qcom_set_simr()
+ */
+static inline void qcom_set_simr(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_SIMR);
+}
+
+/*
+ * qcom_reset_simr()
+ */
+static inline void qcom_reset_simr(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_SIMR);
+}
+
+/*
+ * qcom_set_retry()
+ */
+static inline void qcom_set_retry(struct nss_gmac_hal_dev *nghd, uint32_t retry)
+{
+	uint32_t data;
+
+	data = hal_read_relaxed_reg(nghd->mac_base, QCOM_MAC_CTRL1);
+	data &= ~QCOM_RETRY_POS;
+	retry = retry << QCOM_RETRY_LSB;
+	data |= retry;
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_CTRL1, data);
+}
+
+/*
+ * qcom_set_prlen()
+ */
+static inline void qcom_set_prlen(struct nss_gmac_hal_dev *nghd, uint32_t prlen)
+{
+	uint32_t data;
+
+	data = hal_read_relaxed_reg(nghd->mac_base, QCOM_MAC_CTRL1);
+	data &= ~QCOM_PRLEN_POS;
+	prlen = prlen << QCOM_PRLEN_LSB;
+	data |= prlen;
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_CTRL1, data);
+}
+
+/*
+ * qcom_set_ppad()
+ */
+static inline void qcom_set_ppad(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_PPAD);
+}
+
+/*
+ * qcom_reset_ppad()
+ */
+static inline void qcom_reset_ppad(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_PPAD);
+}
+
+/*
+ * qcom_set_povr()
+ */
+static inline void qcom_set_povr(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_POVR);
+}
+
+/*
+ * qcom_reset_povr()
+ */
+static inline void qcom_reset_povr(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_POVR);
+}
+
+/*
+ * qcom_set_phug()
+ */
+static inline void qcom_set_phug(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_PHUG);
+}
+
+/*
+ * qcom_reset_phug()
+ */
+static inline void qcom_reset_phug(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_PHUG);
+}
+
+/*
+ * qcom_set_mbof()
+ */
+static inline void qcom_set_mbof(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_MBOF);
+}
+
+/*
+ * qcom_reset_mbof()
+ */
+static inline void qcom_reset_mbof(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_MBOF);
+}
+
+/*
+ * qcom_set_lcol()
+ */
+static inline void qcom_set_lcol(struct nss_gmac_hal_dev *nghd, uint32_t lcol)
+{
+	uint32_t data;
+
+	data = hal_read_relaxed_reg(nghd->mac_base, QCOM_MAC_CTRL1);
+	data &= ~QCOM_LCOL_POS;
+	lcol = lcol << QCOM_LCOL_LSB;
+	data |= lcol;
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_CTRL1, data);
+}
+
+/*
+ * qcom_set_long_jam()
+ */
+static inline void qcom_set_long_jam(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_LONG_JAM);
+}
+
+/*
+ * qcom_reset_long_jam()
+ */
+static inline void qcom_reset_long_jam(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL1, QCOM_LONG_JAM);
+}
+
+/*
+ * qcom_set_ipg_dec_len()
+ */
+static inline void qcom_set_ipg_dec_len(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL2, QCOM_IPG_DEC_LEN);
+}
+
+/*
+ * qcom_reset_ipg_dec_len()
+ */
+static inline void qcom_reset_ipg_dec_len(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL2, QCOM_IPG_DEC_LEN);
+}
+
+/*
+ * qcom_set_ctrl2_test_pause()
+ */
+static inline void qcom_set_ctrl2_test_pause(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL2, QCOM_TEST_PAUSE);
+}
+
+/*
+ * qcom_reset_ctrl2_test_pause()
+ */
+static inline void qcom_reset_ctrl2_test_pause(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL2, QCOM_TEST_PAUSE);
+}
+
+/*
+ * qcom_set_mac_loopback()
+ */
+static inline void qcom_set_mac_loopback(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL2, QCOM_MAC_LOOPBACK);
+}
+
+/*
+ * qcom_reset_mac_loopback()
+ */
+static inline void qcom_reset_mac_loopback(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL2, QCOM_MAC_LOOPBACK);
+}
+
+/*
+ * qcom_set_ipg_dec()
+ */
+static inline void qcom_set_ipg_dec(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL2, QCOM_IPG_DEC);
+}
+
+/*
+ * qcom_reset_ipg_dec()
+ */
+static inline void qcom_reset_ipg_dec(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL2, QCOM_IPG_DEC);
+}
+
+/*
+ * qcom_set_crs_sel()
+ */
+static inline void qcom_set_crs_sel(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL2, QCOM_SRS_SEL);
+}
+
+/*
+ * qcom_reset_crs_sel()
+ */
+static inline void qcom_reset_crs_sel(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL2, QCOM_SRS_SEL);
+}
+
+/*
+ * qcom_set_crc_rsv()
+ */
+static inline void qcom_set_crc_rsv(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_CTRL2, QCOM_CRC_RSV);
+}
+
+/*
+ * qcom_reset_crc_rsv()
+ */
+static inline void qcom_reset_crc_rsv(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_CTRL2, QCOM_CRC_RSV);
+}
+
+/*
+ * qcom_set_ipgr1()
+ */
+static inline void qcom_set_ipgr1(struct nss_gmac_hal_dev *nghd, uint32_t ipgr1)
+{
+	uint32_t data;
+
+	data = hal_read_relaxed_reg(nghd->mac_base, QCOM_MAC_DBG_CTRL);
+	data &= ~QCOM_DBG_IPGR1_POS;
+	ipgr1 = ipgr1 << QCOM_DBG_IPGR1_LSB;
+	data |= ipgr1;
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_DBG_CTRL, data);
+}
+
+/*
+ * qcom_set_hihg_ipg()
+ */
+static inline void qcom_set_hihg_ipg(struct nss_gmac_hal_dev *nghd,
+			uint32_t hihg_ipg)
+{
+	uint32_t data;
+
+	data = hal_read_relaxed_reg(nghd->mac_base, QCOM_MAC_DBG_CTRL);
+	data &= ~QCOM_DBG_HIHG_IPG_POS;
+	data |= hihg_ipg << QCOM_DBG_HIHG_IPG_LSB;
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_DBG_CTRL, data);
+}
+
+/*
+ * qcom_set_mac_ipg_ctrl()
+ */
+static inline void qcom_set_mac_ipg_ctrl(struct nss_gmac_hal_dev *nghd,
+			uint32_t mac_ipg_ctrl)
+{
+	uint32_t data;
+
+	data = hal_read_relaxed_reg(nghd->mac_base, QCOM_MAC_DBG_CTRL);
+	data &= ~QCOM_DBG_MAC_IPG_CTRL_POS;
+	data |= mac_ipg_ctrl << QCOM_DBG_MAC_IPG_CTRL_LSB;
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_DBG_CTRL, data);
+}
+
+/*
+ * qcom_set_mac_len_ctrl()
+ */
+static inline void qcom_set_mac_len_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_DBG_CTRL, QCOM_DBG_MAC_LEN_CTRL);
+}
+
+/*
+ * qcom_reset_mac_len_ctrl()
+ */
+static inline void qcom_reset_mac_len_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_DBG_CTRL, QCOM_DBG_MAC_LEN_CTRL);
+}
+
+/*
+ * qcom_set_edxsdfr_transmit()
+ */
+static inline void qcom_set_edxsdfr_transmit(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_DBG_CTRL, QCOM_DBG_EDxSDFR_TRANS);
+}
+
+/*
+ * qcom_reset_edxsdfr_transmit()
+ */
+static inline void qcom_reset_edxsdfr_transmit(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, QCOM_MAC_DBG_CTRL, QCOM_DBG_EDxSDFR_TRANS);
+}
+
+/*
+ * qcom_set_mac_dbg_addr()
+ */
+static inline void qcom_set_mac_dbg_addr(struct nss_gmac_hal_dev *nghd,
+						uint8_t mac_dbg_addr)
+{
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_DBG_ADDR, mac_dbg_addr);
+}
+
+/*
+ * qcom_set_mac_dbg_data()
+ */
+static inline void qcom_set_mac_dbg_data(struct nss_gmac_hal_dev *nghd,
+						uint32_t mac_dbg_data)
+{
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_DBG_DATA, mac_dbg_data);
+}
+
+/*
+ * qcom_set_mac_jumbosize()
+ */
+static inline void qcom_set_mac_jumbosize(struct nss_gmac_hal_dev *nghd,
+						uint16_t mac_jumbo_size)
+{
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_JMB_SIZE, mac_jumbo_size);
+}
+
+/*
+ * qcom_clear_mib_ctrl()
+ */
+static inline void qcom_clear_mib_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_MIB_CTRL, 0);
+}
+
+/*
+ * qcom_set_mib_ctrl()
+ */
+static inline void qcom_set_mib_ctrl(struct nss_gmac_hal_dev *nghd,
+						int mib_settings)
+{
+	hal_set_reg_bits(nghd->mac_base, QCOM_MAC_MIB_CTRL,
+			mib_settings);
+}
+
+/*
+ * qcom_get_stats()
+ */
+static int qcom_get_stats(struct nss_gmac_hal_dev *nghd)
+{
+	struct qcom_hal_dev *qhd = (struct qcom_hal_dev *)nghd;
+	fal_mib_counter_t *stats = &(qhd->stats);
+
+	if (fal_mib_counter_get(0, nghd->mac_id, stats) < 0)
+		return -1;
+
+	return 0;
+}
+#endif /* __QCOM_DEV_H__ */
diff --git a/qca-nss-dp/hal/gmac_ops/qcom/qcom_if.c b/qca-nss-dp/hal/gmac_ops/qcom/qcom_if.c
new file mode 100644
index 0000000..214ec15
--- /dev/null
+++ b/qca-nss-dp/hal/gmac_ops/qcom/qcom_if.c
@@ -0,0 +1,521 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/delay.h>
+#include <linux/ethtool.h>
+#include <linux/vmalloc.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <nss_dp_dev.h>
+#include "qcom_dev.h"
+
+#define QCOM_STAT(m)		offsetof(struct nss_dp_hal_gmac_stats, m)
+#define QCOM_MIB_STAT(m)	offsetof(fal_mib_counter_t, m)
+
+/*
+ * Ethtool stats pointer structure
+ */
+struct qcom_ethtool_stats {
+	uint8_t stat_string[ETH_GSTRING_LEN];
+	uint32_t stat_offset;
+};
+
+/*
+ * Array of strings describing data plane statistics
+ */
+static const struct qcom_ethtool_stats qcom_gstrings_stats[] = {
+#if defined(NSS_DP_IPQ95XX)
+	/*
+	 * Per GMAC DMA driver statistics are
+	 * supported today only for IPQ95xx.
+	 */
+	{"rx_bytes", QCOM_STAT(rx_bytes)},
+	{"rx_packets", QCOM_STAT(rx_packets)},
+	{"rx_dropped", QCOM_STAT(rx_dropped)},
+	{"rx_fraglist_packets", QCOM_STAT(rx_fraglist_packets)},
+	{"rx_nr_frag_packets", QCOM_STAT(rx_nr_frag_packets)},
+	{"rx_nr_frag_headroom_err", QCOM_STAT(rx_nr_frag_headroom_err)},
+	{"tx_bytes", QCOM_STAT(tx_bytes)},
+	{"tx_packets", QCOM_STAT(tx_packets)},
+	{"tx_dropped", QCOM_STAT(tx_dropped)},
+	{"tx_nr_frag_packets", QCOM_STAT(tx_nr_frag_packets)},
+	{"tx_fraglist_packets", QCOM_STAT(tx_fraglist_packets)},
+	{"tx_fraglist_nr_frags_packets", QCOM_STAT(tx_fraglist_with_nr_frags_packets)},
+	{"tx_tso_packets", QCOM_STAT(tx_tso_packets)},
+#endif
+};
+
+/*
+ * Array of strings describing mib statistics
+ */
+static const struct qcom_ethtool_stats qcom_gstrings_mib_stats[] = {
+	{"rx_broadcast", QCOM_MIB_STAT(RxBroad)},
+	{"rx_pause", QCOM_MIB_STAT(RxPause)},
+	{"rx_unicast", QCOM_MIB_STAT(RxUniCast)},
+	{"rx_multicast", QCOM_MIB_STAT(RxMulti)},
+	{"rx_fcserr", QCOM_MIB_STAT(RxFcsErr)},
+	{"rx_alignerr", QCOM_MIB_STAT(RxAllignErr)},
+	{"rx_runt", QCOM_MIB_STAT(RxRunt)},
+	{"rx_frag", QCOM_MIB_STAT(RxFragment)},
+	{"rx_jmbfcserr", QCOM_MIB_STAT(RxJumboFcsErr)},
+	{"rx_jmbalignerr", QCOM_MIB_STAT(RxJumboAligenErr)},
+	{"rx_pkt64", QCOM_MIB_STAT(Rx64Byte)},
+	{"rx_pkt65to127", QCOM_MIB_STAT(Rx128Byte)},
+	{"rx_pkt128to255", QCOM_MIB_STAT(Rx256Byte)},
+	{"rx_pkt256to511", QCOM_MIB_STAT(Rx512Byte)},
+	{"rx_pkt512to1023", QCOM_MIB_STAT(Rx1024Byte)},
+	{"rx_pkt1024to1518", QCOM_MIB_STAT(Rx1518Byte)},
+	{"rx_pkt1519tox", QCOM_MIB_STAT(RxMaxByte)},
+	{"rx_toolong", QCOM_MIB_STAT(RxTooLong)},
+	{"rx_pktgoodbyte", QCOM_MIB_STAT(RxGoodByte)},
+	{"rx_pktbadbyte", QCOM_MIB_STAT(RxBadByte)},
+	{"rx_overflow", QCOM_MIB_STAT(RxOverFlow)},
+	{"tx_broadcast", QCOM_MIB_STAT(TxBroad)},
+	{"tx_pause", QCOM_MIB_STAT(TxPause)},
+	{"tx_multicast", QCOM_MIB_STAT(TxMulti)},
+	{"tx_underrun", QCOM_MIB_STAT(TxUnderRun)},
+	{"tx_pkt64", QCOM_MIB_STAT(Tx64Byte)},
+	{"tx_pkt65to127", QCOM_MIB_STAT(Tx128Byte)},
+	{"tx_pkt128to255", QCOM_MIB_STAT(Tx256Byte)},
+	{"tx_pkt256to511", QCOM_MIB_STAT(Tx512Byte)},
+	{"tx_pkt512to1023", QCOM_MIB_STAT(Tx1024Byte)},
+	{"tx_pkt1024to1518", QCOM_MIB_STAT(Tx1518Byte)},
+	{"tx_pkt1519tox", QCOM_MIB_STAT(TxMaxByte)},
+	{"tx_oversize", QCOM_MIB_STAT(TxOverSize)},
+	{"tx_pktbyte_h", QCOM_MIB_STAT(TxByte)},
+	{"tx_collisions", QCOM_MIB_STAT(TxCollision)},
+	{"tx_abortcol", QCOM_MIB_STAT(TxAbortCol)},
+	{"tx_multicol", QCOM_MIB_STAT(TxMultiCol)},
+	{"tx_singlecol", QCOM_MIB_STAT(TxSingalCol)},
+	{"tx_exesdeffer", QCOM_MIB_STAT(TxExcDefer)},
+	{"tx_deffer", QCOM_MIB_STAT(TxDefer)},
+	{"tx_latecol", QCOM_MIB_STAT(TxLateCol)},
+	{"tx_unicast", QCOM_MIB_STAT(TxUniCast)},
+};
+
+/*
+ * Array of strings describing private flag names
+ */
+static const char * const qcom_strings_priv_flags[] = {
+	"linkpoll",
+	"tstamp",
+	"tsmode",
+};
+
+#define QCOM_STATS_LEN		ARRAY_SIZE(qcom_gstrings_stats)
+#define QCOM_MIB_STATS_LEN	ARRAY_SIZE(qcom_gstrings_mib_stats)
+#define QCOM_PRIV_FLAGS_LEN	ARRAY_SIZE(qcom_strings_priv_flags)
+
+/*
+ * qcom_rx_flow_control()
+ */
+static void qcom_rx_flow_control(struct nss_gmac_hal_dev *nghd, bool enabled)
+{
+	if (enabled)
+		qcom_set_rx_flow_ctrl(nghd);
+	else
+		qcom_clear_rx_flow_ctrl(nghd);
+}
+
+/*
+ * qcom_tx_flow_control()
+ */
+static void qcom_tx_flow_control(struct nss_gmac_hal_dev *nghd, bool enabled)
+{
+	if (enabled)
+		qcom_set_tx_flow_ctrl(nghd);
+	else
+		qcom_clear_tx_flow_ctrl(nghd);
+}
+
+/*
+ * qcom_get_mib_stats()
+ */
+static int32_t qcom_get_mib_stats(struct nss_gmac_hal_dev *nghd)
+{
+	if (qcom_get_stats(nghd))
+		return -1;
+
+	return 0;
+}
+
+/*
+ * qcom_set_maxframe()
+ */
+static int32_t qcom_set_maxframe(struct nss_gmac_hal_dev *nghd,
+				 uint32_t maxframe)
+{
+	/*
+	 * TODO: In override mode, the NPU configures
+	 * the max frame size into HW, so we do not
+	 * need to do configure the HW here. When we
+	 * need to support changing max frame size for
+	 * host mode DMA driver for IPQ807x/IPQ60xx,
+	 * we would need to call fal_port_max_frame_size_set()
+	 * here by differentiating between override mode and host mode.
+	 */
+	return 0;
+}
+
+/*
+ * qcom_get_maxframe()
+ */
+static int32_t qcom_get_maxframe(struct nss_gmac_hal_dev *nghd)
+{
+	int ret;
+	uint32_t mtu;
+
+	ret = fal_port_max_frame_size_get(0, nghd->mac_id, &mtu);
+
+	if (!ret)
+		return mtu;
+
+	return ret;
+}
+
+/*
+ * qcom_get_netdev_stats()
+ */
+static int32_t qcom_get_netdev_stats(struct nss_gmac_hal_dev *nghd,
+		struct rtnl_link_stats64 *stats)
+{
+	struct qcom_hal_dev *qhd = (struct qcom_hal_dev *)nghd;
+	fal_mib_counter_t *hal_stats = &(qhd->stats);
+
+	if (qcom_get_mib_stats(nghd))
+		return -1;
+
+	stats->rx_packets = hal_stats->RxUniCast + hal_stats->RxBroad
+				+ hal_stats->RxMulti;
+	stats->tx_packets = hal_stats->TxUniCast + hal_stats->TxBroad
+				+ hal_stats->TxMulti;
+	stats->rx_bytes = hal_stats->RxGoodByte;
+	stats->tx_bytes = hal_stats->TxByte;
+
+	/* RX errors */
+	stats->rx_crc_errors = hal_stats->RxFcsErr + hal_stats->RxJumboFcsErr;
+	stats->rx_frame_errors = hal_stats->RxAllignErr +
+				 hal_stats->RxJumboAligenErr;
+	stats->rx_fifo_errors = hal_stats->RxRunt;
+	stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors +
+			   stats->rx_fifo_errors;
+
+	stats->rx_dropped = hal_stats->RxTooLong + stats->rx_errors;
+
+	/* TX errors */
+	stats->tx_fifo_errors = hal_stats->TxUnderRun;
+	stats->tx_aborted_errors = hal_stats->TxAbortCol;
+	stats->tx_errors = stats->tx_fifo_errors + stats->tx_aborted_errors;
+
+	stats->collisions = hal_stats->TxCollision;
+	stats->multicast = hal_stats->RxMulti;
+
+	return 0;
+}
+
+/*
+ * qcom_get_strset_count()
+ *	Get string set count for ethtool operations
+ */
+int32_t qcom_get_strset_count(struct nss_gmac_hal_dev *nghd, int32_t sset)
+{
+	struct net_device *netdev = nghd->netdev;
+
+	switch (sset) {
+	case ETH_SS_STATS:
+		return (QCOM_STATS_LEN + QCOM_MIB_STATS_LEN);
+	case ETH_SS_PRIV_FLAGS:
+		return QCOM_PRIV_FLAGS_LEN;
+	}
+
+	netdev_dbg(netdev, "%s: Invalid string set\n", __func__);
+	return -EPERM;
+}
+
+/*
+ * qcom_get_strings()
+ *	Get strings
+ */
+int32_t qcom_get_strings(struct nss_gmac_hal_dev *nghd, int32_t sset,
+						uint8_t *data)
+{
+	struct net_device *netdev = nghd->netdev;
+	int i;
+
+	switch (sset) {
+	case ETH_SS_STATS:
+		for (i = 0; i < QCOM_STATS_LEN; i++) {
+			memcpy(data, qcom_gstrings_stats[i].stat_string,
+				strlen(qcom_gstrings_stats[i].stat_string));
+			data += ETH_GSTRING_LEN;
+		}
+
+		for (i = 0; i < QCOM_MIB_STATS_LEN; i++) {
+			memcpy(data, qcom_gstrings_mib_stats[i].stat_string,
+				strlen(qcom_gstrings_mib_stats[i].stat_string));
+			data += ETH_GSTRING_LEN;
+		}
+		break;
+
+	case ETH_SS_PRIV_FLAGS:
+		for (i = 0; i < QCOM_PRIV_FLAGS_LEN; i++) {
+			memcpy(data, qcom_strings_priv_flags[i],
+				strlen(qcom_strings_priv_flags[i]));
+			data += ETH_GSTRING_LEN;
+		}
+		break;
+
+	default:
+		netdev_dbg(netdev, "%s: Invalid string set\n", __func__);
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+/*
+ * qcom_get_eth_stats()
+ */
+static int32_t qcom_get_eth_stats(struct nss_gmac_hal_dev *nghd, uint64_t *data, struct nss_dp_gmac_stats *stats)
+{
+	struct qcom_hal_dev *qhd = (struct qcom_hal_dev *)nghd;
+	fal_mib_counter_t *mib_stats = &(qhd->stats);
+	uint8_t *p;
+	int i, i_mib;
+
+	/*
+	 * Populate data plane statistics.
+	 */
+	for (i = 0; i < QCOM_STATS_LEN; i++) {
+		p = ((uint8_t *)(stats)
+			+ qcom_gstrings_stats[i].stat_offset);
+		data[i] = *(uint64_t *)p;
+	}
+
+	/*
+	 * Get MIB statistics
+	 */
+	if (qcom_get_mib_stats(nghd)) {
+		return -1;
+	}
+
+	/*
+	 * Populate MIB statistics
+	 */
+	for (i_mib = 0; i_mib < QCOM_MIB_STATS_LEN; i_mib++) {
+		p = (uint8_t *)mib_stats
+			+ qcom_gstrings_mib_stats[i_mib].stat_offset;
+		i = QCOM_STATS_LEN + i_mib;
+		data[i] = *(uint32_t *)p;
+	}
+
+	return 0;
+}
+
+/*
+ * qcom_send_pause_frame()
+ */
+static void qcom_send_pause_frame(struct nss_gmac_hal_dev *nghd)
+{
+	qcom_set_ctrl2_test_pause(nghd);
+}
+
+/*
+ * qcom_stop_pause_frame()
+ */
+static void qcom_stop_pause_frame(struct nss_gmac_hal_dev *nghd)
+{
+	qcom_reset_ctrl2_test_pause(nghd);
+}
+
+/*
+ * qcom_start()
+ */
+static int32_t qcom_start(struct nss_gmac_hal_dev *nghd)
+{
+	qcom_set_full_duplex(nghd);
+
+	qcom_tx_enable(nghd);
+	qcom_rx_enable(nghd);
+
+	netdev_dbg(nghd->netdev, "%s: mac_base:0x%px mac_enable:0x%x\n",
+			__func__, nghd->mac_base,
+			hal_read_relaxed_reg(nghd->mac_base, QCOM_MAC_ENABLE));
+
+	return 0;
+}
+
+/*
+ * qcom_stop()
+ */
+static int32_t qcom_stop(struct nss_gmac_hal_dev *nghd)
+{
+	qcom_tx_disable(nghd);
+	qcom_rx_disable(nghd);
+
+	netdev_dbg(nghd->netdev, "%s: mac_base:0x%px mac_enable:0x%x\n",
+			__func__, nghd->mac_base,
+			hal_read_relaxed_reg(nghd->mac_base, QCOM_MAC_ENABLE));
+	return 0;
+}
+
+/*
+ * qcom_init()
+ */
+static void *qcom_init(struct nss_gmac_hal_platform_data *gmacpdata)
+{
+	struct qcom_hal_dev *qhd = NULL;
+	struct net_device *ndev = NULL;
+	struct nss_dp_dev *dp_priv = NULL;
+	struct resource *res;
+
+	ndev = gmacpdata->netdev;
+	dp_priv = netdev_priv(ndev);
+
+	res = platform_get_resource(dp_priv->pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		netdev_dbg(ndev, "Resource get failed.\n");
+		return NULL;
+	}
+
+	qhd = (struct qcom_hal_dev *)devm_kzalloc(&dp_priv->pdev->dev,
+				sizeof(struct qcom_hal_dev), GFP_KERNEL);
+	if (!qhd) {
+		netdev_dbg(ndev, "kzalloc failed. Returning...\n");
+		return NULL;
+	}
+
+	qhd->nghd.mac_reg_len = resource_size(res);
+	qhd->nghd.memres = devm_request_mem_region(&dp_priv->pdev->dev,
+							res->start,
+							resource_size(res),
+							ndev->name);
+	if (!qhd->nghd.memres) {
+		netdev_dbg(ndev, "Request mem region failed. Returning.\n");
+		devm_kfree(&dp_priv->pdev->dev, qhd);
+		return NULL;
+	}
+
+	/* Save netdev context in QCOM HAL context */
+	qhd->nghd.netdev = gmacpdata->netdev;
+	qhd->nghd.mac_id = gmacpdata->macid;
+
+	/* Populate the mac base addresses */
+	qhd->nghd.mac_base = devm_ioremap_nocache(&dp_priv->pdev->dev,
+						res->start, resource_size(res));
+	if (!qhd->nghd.mac_base) {
+		netdev_dbg(ndev, "ioremap fail.\n");
+		devm_release_mem_region(&dp_priv->pdev->dev,
+				qhd->nghd.memres->start,
+				qhd->nghd.mac_reg_len);
+		devm_kfree(&dp_priv->pdev->dev, qhd);
+		return NULL;
+	}
+
+	spin_lock_init(&qhd->nghd.slock);
+
+	netdev_dbg(ndev, "ioremap OK.Size 0x%x Ndev base 0x%lx macbase 0x%px\n",
+			gmacpdata->reg_len,
+			ndev->base_addr,
+			qhd->nghd.mac_base);
+
+	/* Reset MIB Stats */
+	if (fal_mib_port_flush_counters(0, qhd->nghd.mac_id)) {
+		netdev_dbg(ndev, "MIB stats Reset fail.\n");
+	}
+
+	return (struct nss_gmac_hal_dev *)qhd;
+}
+
+/*
+ * qcom_get_mac_address()
+ */
+static void qcom_get_mac_address(struct nss_gmac_hal_dev *nghd,
+				 uint8_t *macaddr)
+{
+	uint32_t data = hal_read_relaxed_reg(nghd->mac_base, QCOM_MAC_ADDR0);
+	macaddr[5] = (data >> 8) & 0xff;
+	macaddr[4] = (data) & 0xff;
+
+	data = hal_read_relaxed_reg(nghd->mac_base, QCOM_MAC_ADDR1);
+	macaddr[0] = (data >> 24) & 0xff;
+	macaddr[1] = (data >> 16) & 0xff;
+	macaddr[2] = (data >> 8) & 0xff;
+	macaddr[3] = (data) & 0xff;
+}
+
+/*
+ * qcom_set_mac_address()
+ */
+static void qcom_set_mac_address(struct nss_gmac_hal_dev *nghd,
+				uint8_t *macaddr)
+{
+	uint32_t data = (macaddr[5] << 8) | macaddr[4];
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_ADDR0, data);
+	data = (macaddr[0] << 24) | (macaddr[1] << 16)
+		| (macaddr[2] << 8) | macaddr[3];
+	hal_write_relaxed_reg(nghd->mac_base, QCOM_MAC_ADDR1, data);
+}
+
+/*
+ * qcom_exit()
+ */
+static void qcom_exit(struct nss_gmac_hal_dev *nghd)
+{
+	struct nss_dp_dev *dp_priv = NULL;
+	struct qcom_hal_dev *qhd = (struct qcom_hal_dev *)nghd;
+
+	netdev_dbg(nghd->netdev, "Freeing up dev memory.\n");
+
+	dp_priv = netdev_priv(nghd->netdev);
+	devm_iounmap(&dp_priv->pdev->dev,
+			(void *)nghd->mac_base);
+	devm_release_mem_region(&dp_priv->pdev->dev,
+			(nghd->memres)->start,
+			nghd->mac_reg_len);
+
+	nghd->memres = NULL;
+	nghd->mac_base = NULL;
+
+	devm_kfree(&dp_priv->pdev->dev, qhd);
+}
+
+/*
+ * MAC hal_ops base structure
+ */
+struct nss_gmac_hal_ops qcom_gmac_ops = {
+	.init = &qcom_init,
+	.start = &qcom_start,
+	.stop = &qcom_stop,
+	.exit = &qcom_exit,
+	.setmacaddr = &qcom_set_mac_address,
+	.getmacaddr = &qcom_get_mac_address,
+	.rxflowcontrol = &qcom_rx_flow_control,
+	.txflowcontrol = &qcom_tx_flow_control,
+	.getstats = &qcom_get_mib_stats,
+	.setmaxframe = &qcom_set_maxframe,
+	.getmaxframe = &qcom_get_maxframe,
+	.getndostats = &qcom_get_netdev_stats,
+	.getssetcount = &qcom_get_strset_count,
+	.getstrings = &qcom_get_strings,
+	.getethtoolstats = &qcom_get_eth_stats,
+	.sendpause = &qcom_send_pause_frame,
+	.stoppause = &qcom_stop_pause_frame,
+};
diff --git a/qca-nss-dp/hal/gmac_ops/qcom/qcom_reg.h b/qca-nss-dp/hal/gmac_ops/qcom/qcom_reg.h
new file mode 100644
index 0000000..9210c2a
--- /dev/null
+++ b/qca-nss-dp/hal/gmac_ops/qcom/qcom_reg.h
@@ -0,0 +1,156 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016,2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF0
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __QCOM_REG_H__
+#define __QCOM_REG_H__
+
+/* Register Offsets */
+/* Offsets of GMAC config and status registers within NSS_GMAC_QCOM_MAC_BASE */
+#define QCOM_MAC_ENABLE		0x0000
+#define QCOM_MAC_SPEED		0x0004
+#define QCOM_MAC_ADDR0		0x0008
+#define QCOM_MAC_ADDR1		0x000c
+#define QCOM_MAC_CTRL0		0x0010
+#define QCOM_MAC_CTRL1		0x0014
+#define QCOM_MAC_CTRL2		0x0018
+#define QCOM_MAC_DBG_CTRL	0x001c
+#define QCOM_MAC_DBG_ADDR	0x0020
+#define QCOM_MAC_DBG_DATA	0x0024
+#define QCOM_MAC_JMB_SIZE	0x0030
+#define QCOM_MAC_MIB_CTRL	0x0034
+
+/* RX stats */
+#define QCOM_RXBROAD		0x0040
+#define QCOM_RXPAUSE		0x0044
+#define QCOM_RXMULTI		0x0048
+#define QCOM_RXFCSERR		0x004c
+#define QCOM_RXALIGNERR		0x0050
+#define QCOM_RXRUNT		0x0054
+#define QCOM_RXFRAG		0x0058
+#define QCOM_RXJMBFCSERR	0x005c
+#define QCOM_RXJMBALIGNERR	0x0060
+#define QCOM_RXPKT64		0x0064
+#define QCOM_RXPKT65TO127	0x0068
+#define QCOM_RXPKT128TO255	0x006c
+#define QCOM_RXPKT256TO511	0x0070
+#define QCOM_RXPKT512TO1023	0x0074
+#define QCOM_RXPKT1024TO1518	0x0078
+#define QCOM_RXPKT1519TOX	0x007c
+#define QCOM_RXPKTTOOLONG	0x0080
+#define QCOM_RXPKTGOODBYTE_L	0x0084
+#define QCOM_RXPKTGOODBYTE_H	0x0088
+#define QCOM_RXPKTBADBYTE_L	0x008c
+#define QCOM_RXPKTBADBYTE_H	0x0090
+#define QCOM_RXUNI		0x0094
+
+/* TX stats */
+#define QCOM_TXBROAD		0x00a0
+#define QCOM_TXPAUSE		0x00a4
+#define QCOM_TXMULTI		0x00a8
+#define QCOM_TXUNDERUN		0x00aC
+#define QCOM_TXPKT64		0x00b0
+#define QCOM_TXPKT65TO127	0x00b4
+#define QCOM_TXPKT128TO255	0x00b8
+#define QCOM_TXPKT256TO511	0x00bc
+#define QCOM_TXPKT512TO1023	0x00c0
+#define QCOM_TXPKT1024TO1518	0x00c4
+#define QCOM_TXPKT1519TOX	0x00c8
+#define QCOM_TXPKTBYTE_L	0x00cc
+#define QCOM_TXPKTBYTE_H	0x00d0
+#define QCOM_TXCOLLISIONS	0x00d4
+#define QCOM_TXABORTCOL		0x00d8
+#define QCOM_TXMULTICOL		0x00dc
+#define QCOM_TXSINGLECOL	0x00e0
+#define QCOM_TXEXCESSIVEDEFER	0x00e4
+#define QCOM_TXDEFER		0x00e8
+#define QCOM_TXLATECOL		0x00ec
+#define QCOM_TXUNI		0x00f0
+
+/* Bit Masks */
+/* GMAC BITs */
+#define QCOM_RX_MAC_ENABLE	1
+#define QCOM_TX_MAC_ENABLE	0x2
+#define QCOM_DUPLEX		0x10
+#define QCOM_RX_FLOW_ENABLE	0x20
+#define QCOM_TX_FLOW_ENABLE	0x40
+
+#define QCOM_MAC_SPEED_10	0
+#define QCOM_MAC_SPEED_100	1
+#define QCOM_MAC_SPEED_1000	2
+
+/* MAC CTRL0 */
+#define QCOM_IPGT_POS		0x0000007f
+#define QCOM_IPGT_LSB		0
+#define QCOM_IPGR2_POS		0x00007f00
+#define QCOM_IPGR2_LSB		8
+#define QCOM_HALF_THDF_CTRL	0x8000
+#define QCOM_HUGE_RECV		0x10000
+#define QCOM_HUGE_TRANS		0x20000
+#define QCOM_FLCHK		0x40000
+#define QCOM_ABEBE		0x80000
+#define QCOM_AMAXE		0x10000000
+#define QCOM_BPNB		0x20000000
+#define QCOM_NOBO		0x40000000
+#define QCOM_DRBNIB_RXOK	0x80000000
+
+/* MAC CTRL1 */
+#define QCOM_JAM_IPG_POS	0x0000000f
+#define QCOM_JAM_IPG_LSB	0
+#define QCOM_TPAUSE		0x10
+#define QCOM_TCTL		0x20
+#define QCOM_SSTCT		0x40
+#define QCOM_SIMR		0x80
+#define QCOM_RETRY_POS		0x00000f00
+#define QCOM_RETRY_LSB		8
+#define QCOM_PRLEN_POS		0x0000f000
+#define QCOM_PRLEN_LSB		8
+#define QCOM_PPAD		0x10000
+#define QCOM_POVR		0x20000
+#define QCOM_PHUG		0x40000
+#define QCOM_MBOF		0x80000
+#define QCOM_LCOL_POS		0x0ff00000
+#define QCOM_LCOL_LSB		20
+#define QCOM_LONG_JAM		0x10000000
+
+/* MAC CTRL2 */
+#define QCOM_IPG_DEC_LEN	0x2
+#define QCOM_TEST_PAUSE		0x4
+#define QCOM_MAC_LPI_TX_IDLE	0x8
+#define QCOM_MAC_LOOPBACK	0x10
+#define QCOM_IPG_DEC		0x20
+#define QCOM_SRS_SEL		0x40
+#define QCOM_CRC_RSV		0x80
+#define QCOM_MAXFR_POS		0x003fff00
+#define QCOM_MAXFR_LSB		8
+
+/* MAC DEBUG_CTRL */
+#define QCOM_DBG_IPGR1_POS	0x0000007f
+#define QCOM_DBG_IPGR1_LSB	0
+#define QCOM_DBG_HIHG_IPG_POS	0x0000ff00
+#define QCOM_DBG_HIHG_IPG_LSB	8
+#define QCOM_DBG_MAC_IPG_CTRL_POS	0x0000ff00
+#define QCOM_DBG_MAC_IPG_CTRL_LSB	20
+#define QCOM_DBG_MAC_LEN_CTRL	0x40000000
+#define QCOM_DBG_EDxSDFR_TRANS	0x80000000
+
+/* MAC MIB-CTRL*/
+#define QCOM_MIB_ENABLE		1
+#define QCOM_MIB_RESET		0x2
+#define QCOM_MIB_RD_CLR		0x4
+
+#endif /*__QCOM_REG_H__*/
diff --git a/qca-nss-dp/hal/gmac_ops/syn/gmac/syn_dev.h b/qca-nss-dp/hal/gmac_ops/syn/gmac/syn_dev.h
new file mode 100644
index 0000000..588ee96
--- /dev/null
+++ b/qca-nss-dp/hal/gmac_ops/syn/gmac/syn_dev.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __SYN_DEV_H__
+#define __SYN_DEV_H__
+
+#include <nss_dp_dev.h>
+#include <fal/fal_mib.h>
+#include <fal/fal_port_ctrl.h>
+
+/*
+ * Synopsys GMAC supports a maximum frame size of 16383 bytes.
+ * So, the max MTU value is maximum frame size excluding
+ * Ethernet header size (14B), FCS (4B) and 2x VLANs (8B).
+ */
+#define SYN_HAL_MAX_MTU_SIZE		16357
+
+/*
+ * SSDK API internally takes care of adding size of
+ * 2xVLANs (8B) when configuring the MTU value.
+ * So, the max L2 overhead does not consider 2xVLANs.
+ */
+#define SYN_HAL_MTU_L2_OVERHEAD		(ETH_HLEN + ETH_FCS_LEN)
+
+/*
+ * GCC_SNOC_GMAC_AXI_CLOCK
+ */
+#define SYN_GMAC_SNOC_GMAC_AXI_CLK	"nss-snoc-gmac-axi-clk"
+
+/*
+ * Subclass for base nss_gmac_hal_dev
+ */
+struct syn_hal_dev {
+	struct nss_gmac_hal_dev nghd;	/* Base class */
+	struct nss_dp_gmac_stats stats;	/* Stats structure */
+};
+
+#endif /*__SYN_DEV_H__*/
diff --git a/qca-nss-dp/hal/gmac_ops/syn/gmac/syn_if.c b/qca-nss-dp/hal/gmac_ops/syn/gmac/syn_if.c
new file mode 100644
index 0000000..c045194
--- /dev/null
+++ b/qca-nss-dp/hal/gmac_ops/syn/gmac/syn_if.c
@@ -0,0 +1,891 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <fal/fal_mib.h>
+#include <fal/fal_port_ctrl.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/ethtool.h>
+#include <linux/vmalloc.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <nss_dp_arch.h>
+#include "syn_dev.h"
+#include "syn_mac_reg.h"
+
+#define SYN_STAT(m)	offsetof(struct nss_dp_hal_gmac_stats, m)
+#define SYN_MIB_STAT(m)	offsetof(fal_mib_counter_t, m)
+#define HW_ERR_SIZE	sizeof(uint64_t)
+
+/*
+ * Array to store ethtool statistics
+ */
+struct syn_ethtool_stats {
+	uint8_t stat_string[ETH_GSTRING_LEN];
+	uint64_t stat_offset;
+};
+
+/*
+ * Array of strings describing statistics
+ */
+static const struct syn_ethtool_stats syn_gstrings_stats[] = {
+	{"rx_bytes", SYN_STAT(rx_stats.rx_bytes)},
+	{"rx_packets", SYN_STAT(rx_stats.rx_packets)},
+	{"rx_errors", SYN_STAT(rx_stats.rx_errors)},
+	{"rx_missed", SYN_STAT(rx_stats.rx_missed)},
+	{"rx_descriptor_errors", SYN_STAT(rx_stats.rx_descriptor_errors)},
+	{"rx_late_collision_errors", SYN_STAT(rx_stats.rx_late_collision_errors)},
+	{"rx_dribble_bit_errors", SYN_STAT(rx_stats.rx_dribble_bit_errors)},
+	{"rx_length_errors", SYN_STAT(rx_stats.rx_length_errors)},
+	{"rx_ip_header_errors", SYN_STAT(rx_stats.rx_ip_header_errors)},
+	{"rx_ip_payload_errors", SYN_STAT(rx_stats.rx_ip_payload_errors)},
+	{"rx_no_buffer_errors", SYN_STAT(rx_stats.rx_no_buffer_errors)},
+	{"rx_transport_csum_bypassed", SYN_STAT(rx_stats.rx_transport_csum_bypassed)},
+	{"rx_fifo_overflows", SYN_STAT(rx_stats.rx_fifo_overflows)},
+	{"rx_overflow_errors", SYN_STAT(rx_stats.rx_overflow_errors)},
+	{"rx_crc_errors", SYN_STAT(rx_stats.rx_crc_errors)},
+	{"rx_scatter_bytes", SYN_STAT(rx_stats.rx_scatter_bytes)},
+	{"rx_scatter_packets", SYN_STAT(rx_stats.rx_scatter_packets)},
+	{"rx_scatter_errors", SYN_STAT(rx_stats.rx_scatter_errors)},
+	{"tx_bytes", SYN_STAT(tx_stats.tx_bytes)},
+	{"tx_packets", SYN_STAT(tx_stats.tx_packets)},
+	{"tx_collisions", SYN_STAT(tx_stats.tx_collisions)},
+	{"tx_errors", SYN_STAT(tx_stats.tx_errors)},
+	{"tx_jabber_timeout_errors", SYN_STAT(tx_stats.tx_jabber_timeout_errors)},
+	{"tx_frame_flushed_errors", SYN_STAT(tx_stats.tx_frame_flushed_errors)},
+	{"tx_loss_of_carrier_errors", SYN_STAT(tx_stats.tx_loss_of_carrier_errors)},
+	{"tx_no_carrier_errors", SYN_STAT(tx_stats.tx_no_carrier_errors)},
+	{"tx_late_collision_errors", SYN_STAT(tx_stats.tx_late_collision_errors)},
+	{"tx_excessive_collision_errors", SYN_STAT(tx_stats.tx_excessive_collision_errors)},
+	{"tx_excessive_deferral_errors", SYN_STAT(tx_stats.tx_excessive_deferral_errors)},
+	{"tx_underflow_errors", SYN_STAT(tx_stats.tx_underflow_errors)},
+	{"tx_ip_header_errors", SYN_STAT(tx_stats.tx_ip_header_errors)},
+	{"tx_ip_payload_errors", SYN_STAT(tx_stats.tx_ip_payload_errors)},
+	{"tx_dropped", SYN_STAT(tx_stats.tx_dropped)},
+	{"tx_ts_create_errors", SYN_STAT(tx_stats.tx_ts_create_errors)},
+	{"tx_desc_not_avail", SYN_STAT(tx_stats.tx_desc_not_avail)},
+	{"tx_pkts_requeued", SYN_STAT(tx_stats.tx_packets_requeued)},
+	{"tx_nr_frags_pkts", SYN_STAT(tx_stats.tx_nr_frags_pkts)},
+	{"tx_fraglist_pkts", SYN_STAT(tx_stats.tx_fraglist_pkts)},
+	{"pmt_interrupts", SYN_STAT(hw_errs[0])},
+	{"mmc_interrupts", SYN_STAT(hw_errs[0]) + (1 * HW_ERR_SIZE)},
+	{"line_interface_interrupts", SYN_STAT(hw_errs[0]) + (2 * HW_ERR_SIZE)},
+	{"fatal_bus_error_interrupts", SYN_STAT(hw_errs[0]) + (3 * HW_ERR_SIZE)},
+	{"rx_buffer_unavailable_interrupts", SYN_STAT(hw_errs[0]) + (4 * HW_ERR_SIZE)},
+	{"rx_process_stopped_interrupts", SYN_STAT(hw_errs[0]) + (5 * HW_ERR_SIZE)},
+	{"tx_underflow_interrupts", SYN_STAT(hw_errs[0]) + (6 * HW_ERR_SIZE)},
+	{"rx_overflow_interrupts", SYN_STAT(hw_errs[0]) + (7 * HW_ERR_SIZE)},
+	{"tx_jabber_timeout_interrutps", SYN_STAT(hw_errs[0]) + (8 * HW_ERR_SIZE)},
+	{"tx_process_stopped_interrutps", SYN_STAT(hw_errs[0]) + (9 * HW_ERR_SIZE)},
+};
+
+/*
+ * Array of strings describing statistics
+ */
+static const struct syn_ethtool_stats syn_gstrings_mib_stats[] = {
+	{"rx_broadcast", SYN_MIB_STAT(RxBroad)},
+	{"rx_pause", SYN_MIB_STAT(RxPause)},
+	{"rx_multicast", SYN_MIB_STAT(RxMulti)},
+	{"rx_fcserr", SYN_MIB_STAT(RxFcsErr)},
+	{"rx_alignerr", SYN_MIB_STAT(RxAllignErr)},
+	{"rx_runt", SYN_MIB_STAT(RxRunt)},
+	{"rx_frag", SYN_MIB_STAT(RxFragment)},
+	{"rx_pkt64", SYN_MIB_STAT(Rx64Byte)},
+	{"rx_pkt65to127", SYN_MIB_STAT(Rx128Byte)},
+	{"rx_pkt128to255", SYN_MIB_STAT(Rx256Byte)},
+	{"rx_pkt256to511", SYN_MIB_STAT(Rx512Byte)},
+	{"rx_pkt512to1023", SYN_MIB_STAT(Rx1024Byte)},
+	{"rx_pkt1024to1518", SYN_MIB_STAT(Rx1518Byte)},
+	{"rx_pkt1519tox", SYN_MIB_STAT(RxMaxByte)},
+	{"rx_toolong", SYN_MIB_STAT(RxTooLong)},
+	{"rx_pktgoodbyte", SYN_MIB_STAT(RxGoodByte)},
+	{"rx_pktbadbyte", SYN_MIB_STAT(RxBadByte)},
+	{"rx_overflow", SYN_MIB_STAT(RxOverFlow)},
+	{"filtered", SYN_MIB_STAT(Filtered)},
+	{"tx_broadcast", SYN_MIB_STAT(TxBroad)},
+	{"tx_pause", SYN_MIB_STAT(TxPause)},
+	{"tx_multicast", SYN_MIB_STAT(TxMulti)},
+	{"tx_underrun", SYN_MIB_STAT(TxUnderRun)},
+	{"tx_pkt64", SYN_MIB_STAT(Tx64Byte)},
+	{"tx_pkt65to127", SYN_MIB_STAT(Tx128Byte)},
+	{"tx_pkt128to255", SYN_MIB_STAT(Tx256Byte)},
+	{"tx_pkt256to511", SYN_MIB_STAT(Tx512Byte)},
+	{"tx_pkt512to1023", SYN_MIB_STAT(Tx1024Byte)},
+	{"tx_pkt1024to1518", SYN_MIB_STAT(Tx1518Byte)},
+	{"tx_pkt1519tox", SYN_MIB_STAT(TxMaxByte)},
+	{"tx_oversize", SYN_MIB_STAT(TxOverSize)},
+	{"tx_pktbyte_h", SYN_MIB_STAT(TxByte)},
+	{"tx_collisions", SYN_MIB_STAT(TxCollision)},
+	{"tx_abortcol", SYN_MIB_STAT(TxAbortCol)},
+	{"tx_multicol", SYN_MIB_STAT(TxMultiCol)},
+	{"tx_singlecol", SYN_MIB_STAT(TxSingalCol)},
+	{"tx_exesdeffer", SYN_MIB_STAT(TxExcDefer)},
+	{"tx_deffer", SYN_MIB_STAT(TxDefer)},
+	{"tx_latecol", SYN_MIB_STAT(TxLateCol)},
+	{"rx_unicast", SYN_MIB_STAT(RxUniCast)},
+	{"tx_unicast", SYN_MIB_STAT(TxUniCast)},
+	{"rx_jumbofcserr", SYN_MIB_STAT(RxJumboFcsErr)},
+	{"rx_jumboalignerr", SYN_MIB_STAT(RxJumboAligenErr)},
+	{"rx_14to63", SYN_MIB_STAT(Rx14To63)},
+	{"rx_toolongbyte", SYN_MIB_STAT(RxTooLongByte)},
+	{"rx_runtbyte", SYN_MIB_STAT(RxRuntByte)},
+};
+
+#define SYN_STATS_LEN	ARRAY_SIZE(syn_gstrings_stats)
+#define SYN_STATS_MIB_STATS_LEN	ARRAY_SIZE(syn_gstrings_mib_stats)
+
+/*
+ * syn_enable_mac_cst()
+ *	Enable stripping of MAC padding/FCS
+ */
+static void syn_enable_mac_cst(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_CONFIGURATION, SYN_MAC_CST_ENABLE);
+}
+
+/*
+ * syn_disable_mac_cst()
+ *	Disable stripping of MAC padding/FCS
+ */
+static void syn_disable_mac_cst(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, SYN_MAC_CONFIGURATION, SYN_MAC_CST_DISABLE);
+}
+
+/*
+ * syn_set_rx_flow_ctrl()
+ */
+static void syn_set_rx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_FLOW_CONTROL,
+			SYN_MAC_FC_RX_FLOW_CONTROL);
+}
+
+/*
+ * syn_clear_rx_flow_ctrl()
+ */
+static void syn_clear_rx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, SYN_MAC_FLOW_CONTROL,
+			SYN_MAC_FC_RX_FLOW_CONTROL);
+
+}
+
+/*
+ * syn_set_tx_flow_ctrl()
+ */
+static void syn_set_tx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_FLOW_CONTROL,
+			SYN_MAC_FC_TX_FLOW_CONTROL);
+}
+
+/*
+ * syn_send_tx_pause_frame()
+ */
+static void syn_send_tx_pause_frame(struct nss_gmac_hal_dev *nghd)
+{
+	syn_set_tx_flow_ctrl(nghd);
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_FLOW_CONTROL,
+			SYN_MAC_FC_SEND_PAUSE_FRAME);
+}
+
+/*
+ * syn_clear_tx_flow_ctrl()
+ */
+static void syn_clear_tx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, SYN_MAC_FLOW_CONTROL,
+			SYN_MAC_FC_TX_FLOW_CONTROL);
+}
+
+/*
+ * syn_rx_enable()
+ */
+static void syn_rx_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_CONFIGURATION, SYN_MAC_RX);
+}
+
+/*
+ * syn_tx_enable()
+ */
+static void syn_tx_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_CONFIGURATION, SYN_MAC_TX);
+}
+
+/*
+ * syn_rx_disable()
+ */
+static void syn_rx_disable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, SYN_MAC_CONFIGURATION, SYN_MAC_RX);
+}
+
+/*
+ * syn_tx_disable()
+ */
+static void syn_tx_disable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, SYN_MAC_CONFIGURATION, SYN_MAC_TX);
+}
+
+/************Ip checksum offloading APIs*************/
+
+/*
+ * syn_enable_rx_chksum_offload()
+ *	Enable IPv4 header and IPv4/IPv6 TCP/UDP checksum calculation by GMAC.
+ */
+static void syn_enable_rx_chksum_offload(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base,
+			      SYN_MAC_CONFIGURATION, SYN_MAC_RX_IPC_OFFLOAD);
+}
+
+/*
+ * syn_disable_rx_chksum_offload()
+ *	Disable the IP checksum offloading in receive path.
+ */
+static void syn_disable_rx_chksum_offload(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base,
+				SYN_MAC_CONFIGURATION, SYN_MAC_RX_IPC_OFFLOAD);
+}
+
+/*******************Ip checksum offloading APIs**********************/
+
+/*
+ * syn_ipc_offload_init()
+ *	Initialize IPC Checksum offloading.
+ */
+static void syn_ipc_offload_init(struct nss_gmac_hal_dev *nghd)
+{
+	struct nss_dp_dev *dp_priv;
+	dp_priv = netdev_priv(nghd->netdev);
+
+	if (test_bit(__NSS_DP_RXCSUM, &dp_priv->flags)) {
+		/*
+		 * Enable the offload engine in the receive path
+		 */
+		syn_enable_rx_chksum_offload(nghd);
+		netdev_dbg(nghd->netdev, "%s: enable Rx checksum\n", __func__);
+	} else {
+		syn_disable_rx_chksum_offload(nghd);
+		netdev_dbg(nghd->netdev, "%s: disable Rx checksum\n", __func__);
+	}
+}
+
+/*
+ * syn_disable_mac_interrupt()
+ *	Disable all the interrupts.
+ */
+static void syn_disable_mac_interrupt(struct nss_gmac_hal_dev *nghd)
+{
+	hal_write_relaxed_reg(nghd->mac_base, SYN_INTERRUPT_MASK, 0xffffffff);
+}
+
+/*
+ * syn_disable_mmc_tx_interrupt()
+ *	Disable the MMC Tx interrupt.
+ *
+ * The MMC tx interrupts are masked out as per the mask specified.
+ */
+static void syn_disable_mmc_tx_interrupt(struct nss_gmac_hal_dev *nghd,
+						uint32_t mask)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MMC_TX_INTERRUPT_MASK, mask);
+}
+
+/*
+ * syn_disable_mmc_rx_interrupt()
+ *	Disable the MMC Rx interrupt.
+ *
+ * The MMC rx interrupts are masked out as per the mask specified.
+ */
+static void syn_disable_mmc_rx_interrupt(struct nss_gmac_hal_dev *nghd,
+						uint32_t mask)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MMC_RX_INTERRUPT_MASK, mask);
+}
+
+/*
+ * syn_disable_mmc_ipc_rx_interrupt()
+ *	Disable the MMC ipc rx checksum offload interrupt.
+ *
+ * The MMC ipc rx checksum offload interrupts are masked out as
+ * per the mask specified.
+ */
+static void syn_disable_mmc_ipc_rx_interrupt(struct nss_gmac_hal_dev *nghd,
+					   uint32_t mask)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MMC_IPC_RX_INTR_MASK, mask);
+}
+
+/*
+ * syn_disable_interrupt_all()
+ *	Disable all the interrupts.
+ */
+static void syn_disable_interrupt_all(struct nss_gmac_hal_dev *nghd)
+{
+	syn_disable_mac_interrupt(nghd);
+	syn_disable_mmc_tx_interrupt(nghd, 0xFFFFFFFF);
+	syn_disable_mmc_rx_interrupt(nghd, 0xFFFFFFFF);
+	syn_disable_mmc_ipc_rx_interrupt(nghd, 0xFFFFFFFF);
+}
+
+/*
+ * syn_broadcast_enable()
+ *	Enables Broadcast frames.
+ *
+ * When enabled Address filtering module passes all incoming broadcast frames.
+ */
+static void syn_broadcast_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, SYN_MAC_FRAME_FILTER, SYN_MAC_BROADCAST);
+}
+
+/*
+ * syn_multicast_enable()
+ *	Enables Multicast frames.
+ *
+ * When enabled all multicast frames are passed.
+ */
+static void syn_multicast_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_FRAME_FILTER, SYN_MAC_MULTICAST_FILTER);
+}
+
+/*
+ * syn_promisc_enable()
+ *	Enables promiscous mode.
+ *
+ * When enabled Address filter modules pass all incoming frames
+ * regardless of their Destination and source addresses.
+ */
+static void syn_promisc_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_FRAME_FILTER,
+				SYN_MAC_PROMISCUOUS_MODE_ON);
+}
+
+/*
+ * syn_rx_flow_control()
+ */
+static void syn_rx_flow_control(struct nss_gmac_hal_dev *nghd,
+							bool enabled)
+{
+	BUG_ON(nghd == NULL);
+
+	if (enabled) {
+		syn_set_rx_flow_ctrl(nghd);
+	} else {
+		syn_clear_rx_flow_ctrl(nghd);
+	}
+}
+
+/*
+ * syn_tx_flow_control()
+ */
+static void syn_tx_flow_control(struct nss_gmac_hal_dev *nghd,
+							bool enabled)
+{
+	BUG_ON(nghd == NULL);
+
+	if (enabled) {
+		syn_set_tx_flow_ctrl(nghd);
+	} else {
+		syn_clear_tx_flow_ctrl(nghd);
+	}
+}
+
+/*
+ * syn_get_max_frame_size()
+ */
+static int32_t syn_get_max_frame_size(struct nss_gmac_hal_dev *nghd)
+{
+	int ret;
+	uint32_t mtu;
+
+	BUG_ON(nghd == NULL);
+
+	ret = fal_port_max_frame_size_get(0, nghd->mac_id, &mtu);
+
+	if (!ret) {
+		return mtu;
+	}
+
+	return ret;
+}
+
+/*
+ * syn_set_max_frame_size()
+ */
+static int32_t syn_set_max_frame_size(struct nss_gmac_hal_dev *nghd,
+							uint32_t val)
+{
+	uint16_t frame_sz;
+	BUG_ON(nghd == NULL);
+
+	if (val > SYN_HAL_MAX_MTU_SIZE) {
+		netdev_warn(nghd->netdev, "Maximum allowed MTU: %d\n",
+							SYN_HAL_MAX_MTU_SIZE);
+		return -1;
+	}
+
+	frame_sz = val + SYN_HAL_MTU_L2_OVERHEAD;
+	return fal_port_max_frame_size_set(0, nghd->mac_id, frame_sz);
+}
+
+/*
+ * syn_get_mib_stats()
+ */
+int syn_get_mib_stats(struct nss_gmac_hal_dev *nghd, fal_mib_counter_t *stats)
+{
+	if (fal_mib_counter_get(0, nghd->mac_id, stats) < 0) {
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * syn_get_netdev_stats()
+ */
+static int32_t syn_get_netdev_stats(struct nss_gmac_hal_dev *nghd,
+		struct rtnl_link_stats64 *stats)
+{
+	fal_mib_counter_t hal_stats;
+
+	BUG_ON(nghd == NULL);
+
+	memset(&hal_stats, 0, sizeof(fal_mib_counter_t));
+	if (syn_get_mib_stats(nghd, &hal_stats)) {
+		return -1;
+	}
+
+	stats->rx_packets = hal_stats.RxUniCast + hal_stats.RxBroad
+				+ hal_stats.RxMulti;
+	stats->tx_packets = hal_stats.TxUniCast + hal_stats.TxBroad
+				+ hal_stats.TxMulti;
+	stats->rx_bytes = hal_stats.RxGoodByte;
+	stats->tx_bytes = hal_stats.TxByte;
+	stats->collisions = hal_stats.TxCollision;
+	stats->multicast = hal_stats.RxMulti;
+
+	/*
+	 * RX errors
+	 */
+	stats->rx_crc_errors = hal_stats.RxFcsErr + hal_stats.RxJumboFcsErr;
+	stats->rx_frame_errors = hal_stats.RxAllignErr +
+				 hal_stats.RxJumboAligenErr + hal_stats.RxRunt;
+	stats->rx_fifo_errors = hal_stats.RxOverFlow;
+	stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors +
+			   stats->rx_fifo_errors;
+
+	stats->rx_dropped = hal_stats.RxTooLong + stats->rx_errors;
+
+	/*
+	 * TX errors
+	 */
+	stats->tx_fifo_errors = hal_stats.TxUnderRun + hal_stats.RxOverFlow;
+	stats->tx_aborted_errors = hal_stats.TxAbortCol;
+	stats->tx_errors = stats->tx_fifo_errors + stats->tx_aborted_errors;
+
+	return 0;
+}
+
+/*
+ * syn_get_eth_stats()
+ */
+static int32_t syn_get_eth_stats(struct nss_gmac_hal_dev *nghd,
+					uint64_t *data,
+					struct nss_dp_gmac_stats *stats)
+{
+	int i, i_mib;
+	fal_mib_counter_t mib_stats;
+	uint8_t *p = NULL;
+
+	BUG_ON(nghd == NULL);
+
+	/*
+	 * Populate data plane statistics.
+	 */
+	for (i = 0; i < SYN_STATS_LEN; i++) {
+		p = ((uint8_t *)(stats) + syn_gstrings_stats[i].stat_offset);
+		data[i] = *(uint64_t *)p;
+	}
+
+	/*
+	 * Get MIB statistics
+	 */
+	memset(&mib_stats, 0, sizeof(fal_mib_counter_t));
+	if (syn_get_mib_stats(nghd, &mib_stats)) {
+		return -1;
+	}
+
+	/*
+	 * Populate MIB statistics
+	 */
+	for (i_mib = 0; i_mib < SYN_STATS_MIB_STATS_LEN; i_mib++) {
+		p = ((uint8_t *)(&mib_stats) +
+				syn_gstrings_mib_stats[i_mib].stat_offset);
+		i = SYN_STATS_LEN + i_mib;
+		data[i] = *(uint64_t *)p;
+	}
+
+	return 0;
+}
+
+/*
+ * syn_get_strset_count()
+ */
+static int32_t syn_get_strset_count(struct nss_gmac_hal_dev *nghd,
+					int32_t sset)
+{
+	struct net_device *netdev;
+
+	BUG_ON(nghd == NULL);
+
+	netdev = nghd->netdev;
+
+	switch (sset) {
+	case ETH_SS_STATS:
+		return (SYN_STATS_LEN + SYN_STATS_MIB_STATS_LEN);
+	}
+
+	netdev_dbg(netdev, "%s: Invalid string set\n", __func__);
+	return -EPERM;
+}
+
+/*
+ * syn_get_strings()
+ */
+static int32_t syn_get_strings(struct nss_gmac_hal_dev *nghd,
+					int32_t stringset, uint8_t *data)
+{
+	struct net_device *netdev;
+	int i;
+
+	BUG_ON(nghd == NULL);
+
+	netdev = nghd->netdev;
+
+	switch (stringset) {
+	case ETH_SS_STATS:
+		for (i = 0; i < SYN_STATS_LEN; i++) {
+			memcpy(data, syn_gstrings_stats[i].stat_string,
+					ETH_GSTRING_LEN);
+			data += ETH_GSTRING_LEN;
+		}
+
+		for (i = 0; i < SYN_STATS_MIB_STATS_LEN; i++) {
+			memcpy(data, syn_gstrings_mib_stats[i].stat_string,
+					ETH_GSTRING_LEN);
+			data += ETH_GSTRING_LEN;
+		}
+
+		break;
+
+	default:
+		netdev_dbg(netdev, "%s: Invalid string set\n", __func__);
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+/*
+ * syn_send_pause_frame()
+ */
+static void syn_send_pause_frame(struct nss_gmac_hal_dev *nghd)
+{
+	BUG_ON(nghd == NULL);
+
+	syn_send_tx_pause_frame(nghd);
+}
+
+/*
+ * syn_set_mac_address()
+ */
+static void syn_set_mac_address(struct nss_gmac_hal_dev *nghd,
+							uint8_t *macaddr)
+{
+	uint32_t data;
+
+	BUG_ON(nghd == NULL);
+
+	if (!macaddr) {
+		netdev_warn(nghd->netdev, "macaddr is not valid.\n");
+		return;
+	}
+
+	data = (macaddr[5] << 8) | macaddr[4] | SYN_MAC_ADDR_HIGH_AE;
+	hal_write_relaxed_reg(nghd->mac_base, SYN_MAC_ADDR0_HIGH, data);
+	data = (macaddr[3] << 24) | (macaddr[2] << 16) | (macaddr[1] << 8)
+		| macaddr[0];
+	hal_write_relaxed_reg(nghd->mac_base, SYN_MAC_ADDR0_LOW, data);
+}
+
+/*
+ * syn_get_mac_address()
+ */
+static void syn_get_mac_address(struct nss_gmac_hal_dev *nghd,
+							uint8_t *macaddr)
+{
+	uint32_t data;
+
+	BUG_ON(nghd == NULL);
+
+	if (!macaddr) {
+		netdev_warn(nghd->netdev, "macaddr is not valid.\n");
+		return;
+	}
+
+	data = hal_read_relaxed_reg(nghd->mac_base, SYN_MAC_ADDR0_HIGH);
+	macaddr[5] = (data >> 8) & 0xff;
+	macaddr[4] = (data) & 0xff;
+
+	data = hal_read_relaxed_reg(nghd->mac_base, SYN_MAC_ADDR0_LOW);
+	macaddr[3] = (data >> 24) & 0xff;
+	macaddr[2] = (data >> 16) & 0xff;
+	macaddr[1] = (data >> 8) & 0xff;
+	macaddr[0] = (data) & 0xff;
+}
+
+/*
+ * syn_gmac_clk_enable
+ *	Function to enable GCC_SNOC_GMAC_AXI_CLK.
+ *
+ * These clocks are required for GMAC operations.
+ */
+static void syn_gmac_clk_enable(struct nss_gmac_hal_dev *nghd)
+{
+	struct net_device *ndev = nghd->netdev;
+	struct nss_dp_dev *dp_priv = netdev_priv(ndev);
+	struct platform_device *pdev = dp_priv->pdev;
+	struct device *dev = &pdev->dev;
+	struct clk *gmac_clk = NULL;
+	int err;
+
+	gmac_clk = devm_clk_get(dev, SYN_GMAC_SNOC_GMAC_AXI_CLK);
+	if (IS_ERR(gmac_clk)) {
+		pr_err("%s: cannot get clock: %s\n", __func__,
+						SYN_GMAC_SNOC_GMAC_AXI_CLK);
+		return;
+	}
+
+	err = clk_prepare_enable(gmac_clk);
+	if (err) {
+		pr_err("%s: cannot enable clock: %s, err: %d\n", __func__,
+						SYN_GMAC_SNOC_GMAC_AXI_CLK, err);
+		return;
+	}
+}
+
+/*
+ * syn_start()
+ */
+static int32_t syn_start(struct nss_gmac_hal_dev *nghd)
+{
+	struct nss_dp_dev *dp_dev;
+
+	BUG_ON(nghd == NULL);
+
+	syn_tx_enable(nghd);
+	syn_rx_enable(nghd);
+	dp_dev = (struct nss_dp_dev *)netdev_priv(nghd->netdev);
+
+	/*
+	 * TODO: Enable MAC CST stripping for NSS mode as well. We need
+	 * NSS change for that.
+	 */
+	if (!(dp_dev->drv_flags & NSS_DP_PRIV_FLAG(INIT_OVERRIDE))) {
+		syn_enable_mac_cst(nghd);
+	}
+
+	netdev_dbg(nghd->netdev, "%s: mac_base:0x%px MAC Config:0x%x\n",
+		__func__, nghd->mac_base,
+		hal_read_relaxed_reg(nghd->mac_base, SYN_MAC_CONFIGURATION));
+
+	return 0;
+}
+
+/*
+ * syn_stop()
+ */
+static int32_t syn_stop(struct nss_gmac_hal_dev *nghd)
+{
+	struct nss_dp_dev *dp_dev;
+
+	BUG_ON(nghd == NULL);
+
+	syn_tx_disable(nghd);
+	syn_rx_disable(nghd);
+	dp_dev = (struct nss_dp_dev *)netdev_priv(nghd->netdev);
+
+	/*
+	 * TODO: Disable MAC CST stripping for NSS mode as well. We need
+	 * NSS change for that.
+	 */
+	if (!(dp_dev->drv_flags & NSS_DP_PRIV_FLAG(INIT_OVERRIDE))) {
+		syn_disable_mac_cst(nghd);
+	}
+
+
+	netdev_dbg(nghd->netdev, "%s: mac_base:0x%px MAC Config:0x%x\n",
+		__func__, nghd->mac_base,
+		hal_read_relaxed_reg(nghd->mac_base, SYN_MAC_CONFIGURATION));
+
+	return 0;
+}
+
+/*
+ * syn_init()
+ */
+static void *syn_init(struct nss_gmac_hal_platform_data *gmacpdata)
+{
+	struct syn_hal_dev *shd = NULL;
+	struct net_device *ndev = NULL;
+	struct nss_dp_dev *dp_priv = NULL;
+	struct resource *res;
+
+	ndev = gmacpdata->netdev;
+	dp_priv = netdev_priv(ndev);
+
+	res = platform_get_resource(dp_priv->pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		netdev_dbg(ndev, "Resource get failed.\n");
+		return NULL;
+	}
+
+	shd = (struct syn_hal_dev *)devm_kzalloc(&dp_priv->pdev->dev,
+					sizeof(struct syn_hal_dev),
+					GFP_KERNEL);
+	if (!shd) {
+		netdev_dbg(ndev, "kzalloc failed. Returning...\n");
+		return NULL;
+	}
+
+	shd->nghd.mac_reg_len = resource_size(res);
+	shd->nghd.memres = devm_request_mem_region(&dp_priv->pdev->dev,
+							res->start,
+							resource_size(res),
+							ndev->name);
+	if (!shd->nghd.memres) {
+		netdev_dbg(ndev, "Request mem region failed. Returning.\n");
+		devm_kfree(&dp_priv->pdev->dev, shd);
+		return NULL;
+	}
+
+	/*
+	 * Save netdev context in syn HAL context
+	 */
+	shd->nghd.netdev = gmacpdata->netdev;
+	shd->nghd.mac_id = gmacpdata->macid;
+	shd->nghd.duplex_mode = DUPLEX_FULL;
+
+	set_bit(__NSS_DP_RXCSUM, &dp_priv->flags);
+
+	/*
+	 * Populate the mac base addresses
+	 */
+	shd->nghd.mac_base =
+		devm_ioremap_nocache(&dp_priv->pdev->dev, res->start,
+							resource_size(res));
+	if (!shd->nghd.mac_base) {
+		netdev_dbg(ndev, "ioremap fail.\n");
+		devm_release_mem_region(&dp_priv->pdev->dev,
+				shd->nghd.memres->start,
+				shd->nghd.mac_reg_len);
+		devm_kfree(&dp_priv->pdev->dev, shd);
+		return NULL;
+	}
+
+	spin_lock_init(&shd->nghd.slock);
+
+	netdev_dbg(ndev, "ioremap OK.Size 0x%x Ndev base 0x%lx macbase 0x%px\n",
+			gmacpdata->reg_len,
+			ndev->base_addr,
+			shd->nghd.mac_base);
+
+	syn_disable_interrupt_all(&shd->nghd);
+
+	/*
+	 * Enable SoC specific GMAC clocks.
+	 */
+	syn_gmac_clk_enable(&shd->nghd);
+
+	syn_ipc_offload_init(&shd->nghd);
+	syn_promisc_enable(&shd->nghd);
+	syn_broadcast_enable(&shd->nghd);
+	syn_multicast_enable(&shd->nghd);
+
+	/*
+	 * Reset MIB Stats
+	 */
+	if (fal_mib_port_flush_counters(0, shd->nghd.mac_id)) {
+		netdev_dbg(ndev, "MIB stats Reset fail.\n");
+	}
+
+	return (struct nss_gmac_hal_dev *)shd;
+}
+
+/*
+ * syn_exit()
+ */
+static void syn_exit(struct nss_gmac_hal_dev *nghd)
+{
+	struct nss_dp_dev *dp_priv = NULL;
+	struct syn_hal_dev *shd = (struct syn_hal_dev *)nghd;
+
+	netdev_dbg(nghd->netdev, "Freeing up dev memory.\n");
+
+	dp_priv = netdev_priv(nghd->netdev);
+	devm_iounmap(&dp_priv->pdev->dev,
+			(void *)nghd->mac_base);
+	devm_release_mem_region(&dp_priv->pdev->dev,
+			(nghd->memres)->start,
+			nghd->mac_reg_len);
+
+	nghd->memres = NULL;
+	nghd->mac_base = NULL;
+
+	devm_kfree(&dp_priv->pdev->dev, shd);
+}
+
+/*
+ * MAC hal_ops base structure
+ */
+struct nss_gmac_hal_ops syn_gmac_ops = {
+	.init = &syn_init,
+	.start =  &syn_start,
+	.stop = &syn_stop,
+	.exit = &syn_exit,
+	.setmacaddr = &syn_set_mac_address,
+	.getmacaddr = &syn_get_mac_address,
+	.rxflowcontrol = &syn_rx_flow_control,
+	.txflowcontrol = &syn_tx_flow_control,
+	.setmaxframe = &syn_set_max_frame_size,
+	.getmaxframe = &syn_get_max_frame_size,
+	.getndostats = &syn_get_netdev_stats,
+	.getssetcount = &syn_get_strset_count,
+	.getstrings = &syn_get_strings,
+	.getethtoolstats = &syn_get_eth_stats,
+	.sendpause = &syn_send_pause_frame,
+};
diff --git a/qca-nss-dp/hal/gmac_ops/syn/gmac/syn_mac_reg.h b/qca-nss-dp/hal/gmac_ops/syn/gmac/syn_mac_reg.h
new file mode 100644
index 0000000..5de97db
--- /dev/null
+++ b/qca-nss-dp/hal/gmac_ops/syn/gmac/syn_mac_reg.h
@@ -0,0 +1,232 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __SYN_MAC_REG_H__
+#define __SYN_MAC_REG_H__
+
+/*
+ * MAC register offset
+ */
+#define SYN_MAC_CONFIGURATION				0x0000
+#define SYN_MAC_FRAME_FILTER				0x0004
+#define SYN_MAC_FLOW_CONTROL				0x0018
+#define SYN_VLAN_TAG					0x001C
+#define SYN_VERSION					0x0020
+#define SYN_DEBUG					0x0024
+#define SYN_REMOTE_WAKE_UP_FRAME_FILTER			0x0028
+#define SYN_PMT_CONTROL_STATUS				0x002C
+#define SYN_LPI_CONTROL_STATUS				0x0030
+#define SYN_LPI_TIMERS_CONTROL				0x0034
+#define SYN_INTERRUPT_STATUS				0x0038
+#define SYN_INTERRUPT_MASK				0x003C
+
+/*
+ * MAC address register offset
+ */
+#define SYN_MAC_ADDR0_HIGH				0x0040
+#define SYN_MAC_ADDR0_LOW				0x0044
+#define SYN_MAC_ADDR1_HIGH				0x0048
+#define SYN_MAC_ADDR1_LOW				0x004C
+#define SYN_MAC_ADDR2_HIGH				0x0050
+#define SYN_MAC_ADDR2_LOW				0x0054
+#define SYN_MAC_ADDR3_HIGH				0x0058
+#define SYN_MAC_ADDR3_LOW				0x005C
+#define SYN_MAC_ADDR4_HIGH				0x0060
+#define SYN_MAC_ADDR4_LOW				0x0064
+
+/*
+ * Watchdog timeout register
+ */
+#define SYN_WDOG_TIMEOUT				0x00DC
+
+/*
+ * Mac Management Counters (MMC) register offset
+ */
+#define SYN_MMC_CONTROL					0x0100
+#define SYN_MMC_RX_INTERRUPT				0x0104
+#define SYN_MMC_TX_INTERRUPT				0x0108
+#define SYN_MMC_RX_INTERRUPT_MASK			0x010C
+#define SYN_MMC_TX_INTERRUPT_MASK			0x0110
+#define SYN_MMC_IPC_RX_INTR_MASK			0x0200
+
+/*
+ * Optional HW feature register
+ */
+#define SYN_HW_FEATURE					0x1058
+
+/*
+ * Register Bit Definitions
+ */
+
+/*
+ * SYN_MAC_CONFIGURATION = 0x0000,	MAC config Register Layout
+ */
+enum syn_mac_config_reg {
+	SYN_MAC_TWOKPE = 0x08000000,			/* Support for 2K packets */
+	SYN_MAC_TWOKPE_ENABLE = 0x08000000,
+	SYN_MAC_TWOKPE_DISABLE = 0x00000000,
+	SYN_MAC_CST = 0x02000000,			/* (CST) CRC Stripping for Type Frames */
+	SYN_MAC_CST_ENABLE = 0x02000000,
+	SYN_MAC_CST_DISABLE = 0x02000000,
+	SYN_MAC_TC = 0x01000000,			/* (TC) Transmit configuration */
+	SYN_MAC_WATCHDOG = 0x00800000,
+	SYN_MAC_WATCHDOG_ENABLE = 0x00000000,		/* Enable watchdog timer */
+	SYN_MAC_WATCHDOG_DISABLE = 0x00800000,		/* (WD)Disable watchdog timer on Rx */
+	SYN_MAC_JABBER = 0x00400000,
+	SYN_MAC_JABBER_ENABLE = 0x00000000,		/* Enable jabber timer */
+	SYN_MAC_JABBER_DISABLE = 0x00400000,		/* (JD)Disable jabber timer on Tx */
+	SYN_MAC_FRAME_BURST = 0x00200000,
+	SYN_MAC_FRAME_BURST_ENABLE = 0x00200000,	/* (BE)Enable frame bursting
+							   during Tx */
+	SYN_MAC_FRAME_BURST_DISABLE = 0x00000000,	/* Disable frame bursting */
+	SYN_MAC_JUMBO_FRAME = 0x00100000,
+	SYN_MAC_JUMBO_FRAME_ENABLE = 0x00100000,	/* (JE)Enable jumbo frame for Rx */
+	SYN_MAC_JUMBO_FRAME_DISABLE = 0x00000000,	/* Disable jumbo frame */
+	SYN_MAC_INTER_FRAME_GAP7 = 0x000E0000,		/* (IFG) Config7 - 40bit times */
+	SYN_MAC_INTER_FRAME_GAP6 = 0x000C0000,		/* (IFG) Config6 - 48bit times */
+	SYN_MAC_INTER_FRAME_GAP5 = 0x000A0000,		/* (IFG) Config5 - 56bit times */
+	SYN_MAC_INTER_FRAME_GAP4 = 0x00080000,		/* (IFG) Config4 - 64bit times */
+	SYN_MAC_INTER_FRAME_GAP3 = 0x00060000,		/* (IFG) Config3 - 72bit times */
+	SYN_MAC_INTER_FRAME_GAP2 = 0x00040000,		/* (IFG) Config2 - 80bit times */
+	SYN_MAC_INTER_FRAME_GAP1 = 0x00020000,		/* (IFG) Config1 - 88bit times */
+	SYN_MAC_INTER_FRAME_GAP0 = 0x00000000,		/* (IFG) Config0 - 96bit times */
+	SYN_MAC_DISABLE_CRS = 0x00010000,		/* (DCRS) Disable Carrier Sense During Transmission */
+	SYN_MAC_MII_GMII = 0x00008000,
+	SYN_MAC_SELECT_MII = 0x00008000,		/* (PS)Port Select-MII mode */
+	SYN_MAC_SELECT_GMII = 0x00000000,		/* GMII mode */
+	SYN_MAC_FE_SPEED100 = 0x00004000,		/* (FES)Fast Ethernet speed 100Mbps */
+	SYN_MAC_FE_SPEED = 0x00004000,			/* (FES)Fast Ethernet speed 100Mbps */
+	SYN_MAC_FE_SPEED10 = 0x00000000,		/* (FES)Fast Ethernet speed 10Mbps */
+	SYN_MAC_RX_OWN = 0x00002000,
+	SYN_MAC_DISABLE_RX_OWN = 0x00002000,		/* (DO)Disable receive own packets */
+	SYN_MAC_ENABLE_RX_OWN = 0x00000000,		/* Enable receive own packets */
+	SYN_MAC_LOOPBACK = 0x00001000,
+	SYN_MAC_LOOPBACK_ON = 0x00001000,		/* (LM)Loopback mode for GMII/MII */
+	SYN_MAC_LOOPBACK_OFF = 0x00000000,		/* Normal mode */
+	SYN_MAC_DUPLEX = 0x00000800,
+	SYN_MAC_FULL_DUPLEX = 0x00000800,		/* (DM)Full duplex mode */
+	SYN_MAC_HALF_DUPLEX = 0x00000000,		/* Half duplex mode */
+	SYN_MAC_RX_IPC_OFFLOAD = 0x00000400,		/* IPC checksum offload */
+	SYN_MAC_RX_IPC_OFFLOAD_ENABLE = 0x00000400,
+	SYN_MAC_RX_IPC_OFFLOAD_DISABLE = 0x00000000,
+	SYN_MAC_RETRY = 0x00000200,
+	SYN_MAC_RETRY_DISABLE = 0x00000200,		/* (DR)Disable Retry */
+	SYN_MAC_RETRY_ENABLE = 0x00000000,		/* Enable retransmission as per BL */
+	SYN_MAC_LINK_UP = 0x00000100,			/* (LUD)Link UP */
+	SYN_MAC_LINK_DOWN = 0x00000100,			/* Link Down */
+	SYN_MAC_PAD_CRC_STRIP = 0x00000080,
+	SYN_MAC_PAD_CRC_STRIP_ENABLE = 0x00000080,	/* (ACS) Automatic Pad/Crc strip enable */
+	SYN_MAC_PAD_CRC_STRIP_DISABLE = 0x00000000,	/* Automatic Pad/Crc stripping disable */
+	SYN_MAC_BACKOFF_LIMIT = 0x00000060,
+	SYN_MAC_BACKOFF_LIMIT3 = 0x00000060,		/* (BL)Back-off limit in HD mode */
+	SYN_MAC_BACKOFF_LIMIT2 = 0x00000040,
+	SYN_MAC_BACKOFF_LIMIT1 = 0x00000020,
+	SYN_MAC_BACKOFF_LIMIT0 = 0x00000000,
+	SYN_MAC_DEFERRAL_CHECK = 0x00000010,
+	SYN_MAC_DEFERRAL_CHECK_ENABLE = 0x00000010,	/* (DC)Deferral check enable in HD mode */
+	SYN_MAC_DEFERRAL_CHECK_DISABLE = 0x00000000,	/* Deferral check disable */
+	SYN_MAC_TX = 0x00000008,
+	SYN_MAC_TX_ENABLE = 0x00000008,			/* (TE)Transmitter enable */
+	SYN_MAC_TX_DISABLE = 0x00000000,		/* Transmitter disable */
+	SYN_MAC_RX = 0x00000004,
+	SYN_MAC_RX_ENABLE = 0x00000004,			/* (RE)Receiver enable */
+	SYN_MAC_RX_DISABLE = 0x00000000,		/* Receiver disable */
+	SYN_MAC_PRELEN_RESERVED = 0x00000003,		/* Preamble Length for Transmit Frames */
+	SYN_MAC_PRELEN_3B = 0x00000002,
+	SYN_MAC_PRELEN_5B = 0x00000001,
+	SYN_MAC_PRELEN_7B = 0x00000000,
+};
+
+/*
+ * SYN_MAC_FRAME_FILTER = 0x0004,	Mac frame filtering controls Register
+ */
+enum syn_mac_frame_filter_reg {
+	SYN_MAC_FILTER = 0x80000000,
+	SYN_MAC_FILTER_OFF = 0x80000000,		/* (RA)Receive all incoming packets */
+	SYN_MAC_FILTER_ON = 0x00000000,			/* Receive filtered pkts only */
+	SYN_MAC_HASH_PERFECT_FILTER = 0x00000400,	/* Hash or Perfect Filter enable */
+	SYN_MAC_SRC_ADDR_FILTER = 0x00000200,
+	SYN_MAC_SRC_ADDR_FILTER_ENABLE = 0x00000200,	/* (SAF)Source Address Filter enable */
+	SYN_MAC_SRC_ADDR_FILTER_DISABLE = 0x00000000,
+	SYN_MAC_SRC_INVA_ADDR_FILTER = 0x00000100,
+	SYN_MAC_SRC_INV_ADDR_FILTER_EN = 0x00000100,	/* (SAIF)Inv Src Addr Filter enable */
+	SYN_MAC_SRC_INV_ADDR_FILTER_DIS = 0x00000000,
+	SYN_MAC_PASS_CONTROL = 0x000000C0,
+	SYN_MAC_PASS_CONTROL3 = 0x000000C0,		/* (PCF)Forwards ctrl frames that pass AF */
+	SYN_MAC_PASS_CONTROL2 = 0x00000080,		/* Forwards all control frames
+							   even if they fail the AF */
+	SYN_MAC_PASS_CONTROL1 = 0x00000040,		/* Forwards all control frames except
+							   PAUSE control frames to application
+							   even if they fail the AF */
+	SYN_MAC_PASS_CONTROL0 = 0x00000000,		/* Don't pass control frames */
+	SYN_MAC_BROADCAST = 0x00000020,
+	SYN_MAC_BROADCAST_DISABLE = 0x00000020,		/* (DBF)Disable Rx of broadcast frames */
+	SYN_MAC_BROADCAST_ENABLE = 0x00000000,		/* Enable broadcast frames */
+	SYN_MAC_MULTICAST_FILTER = 0x00000010,
+	SYN_MAC_MULTICAST_FILTER_OFF = 0x00000010,	/* (PM) Pass all multicast packets */
+	SYN_MAC_MULTICAST_FILTER_ON = 0x00000000,	/* Pass filtered multicast packets */
+	SYN_MAC_DEST_ADDR_FILTER = 0x00000008,
+	SYN_MAC_DEST_ADDR_FILTER_INV = 0x00000008,	/* (DAIF)Inverse filtering for DA */
+	SYN_MAC_DEST_ADDR_FILTER_NOR = 0x00000000,	/* Normal filtering for DA */
+	SYN_MAC_MCAST_HASH_FILTER = 0x00000004,
+	SYN_MAC_MCAST_HASH_FILTER_ON = 0x00000004,	/* (HMC)perfom multicast hash filtering */
+	SYN_MAC_MCAST_HASH_FILTER_OFF = 0x00000000,	/* perfect filtering only */
+	SYN_MAC_UCAST_HASH_FILTER = 0x00000002,
+	SYN_MAC_UCAST_HASH_FILTER_ON = 0x00000002,	/* (HUC)Unicast Hash filtering only */
+	SYN_MAC_UCAST_HASH_FILTER_OFF = 0x00000000,	/* perfect filtering only */
+	SYN_MAC_PROMISCUOUS_MODE = 0x00000001,
+	SYN_MAC_PROMISCUOUS_MODE_ON = 0x00000001,	/* Receive all frames */
+	SYN_MAC_PROMISCUOUS_MODE_OFF = 0x00000000,	/* Receive filtered packets only */
+};
+
+/*
+ * SYN_MAC_FLOW_CONTROL = 0x0018,	Flow control Register Layout
+ */
+enum syn_mac_flow_control_reg {
+	SYN_MAC_FC_PAUSE_TIME_MASK = 0xFFFF0000,	/* (PT) PAUSE TIME field
+							   in the control frame */
+	SYN_MAC_FC_PAUSE_TIME_SHIFT = 16,
+	SYN_MAC_FC_PAUSE_LOW_THRESH = 0x00000030,
+	SYN_MAC_FC_PAUSE_LOW_THRESH3 = 0x00000030,	/* (PLT)thresh for pause
+							   tmr 256 slot time */
+	SYN_MAC_FC_PAUSE_LOW_THRESH2 = 0x00000020,	/* 144 slot time */
+	SYN_MAC_FC_PAUSE_LOW_THRESH1 = 0x00000010,	/* 28 slot time */
+	SYN_MAC_FC_PAUSE_LOW_THRESH0 = 0x00000000,	/* 4 slot time */
+	SYN_MAC_FC_UNICAST_PAUSE_FRAME = 0x00000008,
+	SYN_MAC_FC_UNICAST_PAUSE_FRAME_ON = 0x00000008,	/* (UP)Detect pause frame
+							   with unicast addr. */
+	SYN_MAC_FC_UNICAST_PAUSE_FRAME_OFF = 0x00000000,/* Detect only pause frame
+							   with multicast addr. */
+	SYN_MAC_FC_RX_FLOW_CONTROL = 0x00000004,
+	SYN_MAC_FC_RX_FLOW_CONTROL_ENABLE = 0x00000004,	/* (RFE)Enable Rx flow control */
+	SYN_MAC_FC_RX_FLOW_CONTROL_DISABLE = 0x00000000,/* Disable Rx flow control */
+	SYN_MAC_FC_TX_FLOW_CONTROL = 0x00000002,
+	SYN_MAC_FC_TX_FLOW_CONTROL_ENABLE = 0x00000002,	/* (TFE)Enable Tx flow control */
+	SYN_MAC_FC_TX_FLOW_CONTROL_DISABLE = 0x00000000,/* Disable flow control */
+	SYN_MAC_FC_FLOW_CONTROL_BACK_PRESSURE = 0x00000001,
+	SYN_MAC_FC_SEND_PAUSE_FRAME = 0x00000001,	/* (FCB/PBA)send pause frm/Apply
+							   back pressure */
+};
+
+/*
+ * SYN_MAC_ADDR_HIGH Register
+ */
+enum syn_mac_addr_high {
+	SYN_MAC_ADDR_HIGH_AE = 0x80000000,
+};
+
+#endif /*__SYN_MAC_REG_H__*/
diff --git a/qca-nss-dp/hal/gmac_ops/syn/xgmac/syn_dev.h b/qca-nss-dp/hal/gmac_ops/syn/xgmac/syn_dev.h
new file mode 100644
index 0000000..18b2edd
--- /dev/null
+++ b/qca-nss-dp/hal/gmac_ops/syn/xgmac/syn_dev.h
@@ -0,0 +1,186 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016,2020-2021 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF0
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __SYN_DEV_H__
+#define __SYN_DEV_H__
+
+#include "syn_reg.h"
+#include <fal/fal_mib.h>
+#include <fal/fal_port_ctrl.h>
+
+/*
+ * Subclass for base nss_gmac_haldev
+ */
+struct syn_hal_dev {
+	struct nss_gmac_hal_dev nghd;	/* Base class */
+};
+
+/*
+ * syn_set_rx_flow_ctrl()
+ */
+static inline void syn_set_rx_flow_ctrl(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_RX_FLOW_CTL,
+			SYN_MAC_RX_FLOW_ENABLE);
+}
+
+/*
+ * syn_clear_rx_flow_ctrl()
+ */
+static inline void syn_clear_rx_flow_ctrl(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, SYN_MAC_RX_FLOW_CTL,
+			SYN_MAC_RX_FLOW_ENABLE);
+}
+
+/*
+ * syn_set_tx_flow_ctrl()
+ */
+static inline void syn_set_tx_flow_ctrl(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_Q0_TX_FLOW_CTL,
+			SYN_MAC_TX_FLOW_ENABLE);
+}
+
+/*
+ * syn_send_tx_pause_frame()
+ */
+static inline void syn_send_tx_pause_frame(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_Q0_TX_FLOW_CTL,
+			SYN_MAC_TX_FLOW_ENABLE);
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_Q0_TX_FLOW_CTL,
+			SYN_MAC_TX_PAUSE_SEND);
+}
+
+/*
+ * syn_clear_tx_flow_ctrl()
+ */
+static inline void syn_clear_tx_flow_ctrl(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, SYN_MAC_Q0_TX_FLOW_CTL,
+			SYN_MAC_TX_FLOW_ENABLE);
+}
+
+/*
+ * syn_clear_mac_ctrl()
+ */
+static inline void syn_clear_mac_ctrl(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_write_relaxed_reg(nghd->mac_base, SYN_MAC_TX_CONFIG, 0);
+	hal_write_relaxed_reg(nghd->mac_base, SYN_MAC_RX_CONFIG, 0);
+}
+
+/*
+ * syn_rx_enable()
+ */
+static inline void syn_rx_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_RX_CONFIG, SYN_MAC_RX_ENABLE);
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_PACKET_FILTER, SYN_MAC_RX_ENABLE);
+}
+
+/*
+ * syn_rx_disable()
+ */
+static inline void syn_rx_disable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, SYN_MAC_RX_CONFIG, SYN_MAC_RX_ENABLE);
+}
+
+/*
+ * syn_tx_enable()
+ */
+static inline void syn_tx_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_TX_CONFIG, SYN_MAC_TX_ENABLE);
+}
+
+/*
+ * syn_tx_disable()
+ */
+static inline void syn_tx_disable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, SYN_MAC_TX_CONFIG,
+			SYN_MAC_TX_ENABLE);
+}
+
+/*
+ * syn_set_mmc_stats()
+ */
+static inline void syn_set_mmc_stats(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_MMC_CTL,
+			SYN_MAC_MMC_RSTONRD);
+}
+
+/*
+ * syn_rx_jumbo_frame_enable()
+ */
+static inline void syn_rx_jumbo_frame_enable(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd->mac_base, SYN_MAC_RX_CONFIG,
+			SYN_MAC_JUMBO_FRAME_ENABLE);
+}
+
+/*
+ * syn_rx_jumbo_frame_disable()
+ */
+static inline void syn_rx_jumbo_frame_disable(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd->mac_base, SYN_MAC_RX_CONFIG,
+			SYN_MAC_JUMBO_FRAME_ENABLE);
+}
+
+/*
+ * syn_set_full_duplex()
+ */
+static inline void syn_set_full_duplex(
+		struct nss_gmac_hal_dev *nghd)
+{
+	/* TBD */
+	return;
+}
+
+/*
+ * syn_set_half_duplex()
+ */
+static inline void syn_set_half_duplex(
+		struct nss_gmac_hal_dev *nghd)
+{
+	/* TBD */
+	return;
+}
+
+static int syn_get_xmib_stats(struct nss_gmac_hal_dev *nghd, fal_xgmib_info_t *stats)
+{
+	if (fal_get_xgmib_info(0, nghd->mac_id, stats)) {
+		return -1;
+	}
+
+	return 0;
+}
+#endif /*__SYN_DEV_H__*/
diff --git a/qca-nss-dp/hal/gmac_ops/syn/xgmac/syn_if.c b/qca-nss-dp/hal/gmac_ops/syn/xgmac/syn_if.c
new file mode 100644
index 0000000..ab833b0
--- /dev/null
+++ b/qca-nss-dp/hal/gmac_ops/syn/xgmac/syn_if.c
@@ -0,0 +1,541 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/delay.h>
+#include <linux/ethtool.h>
+#include <linux/vmalloc.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <nss_dp_dev.h>
+#include "syn_dev.h"
+
+#define SYN_STAT(m)		offsetof(struct nss_dp_hal_gmac_stats, m)
+#define SYN_XMIB_STAT(m)	offsetof(fal_xgmib_info_t, m)
+
+struct syn_ethtool_stats {
+	uint8_t stat_string[ETH_GSTRING_LEN];
+	uint64_t stat_offset;
+};
+
+/*
+ * Array of strings describing data plane statistics
+ */
+static const struct syn_ethtool_stats syn_gstrings_stats[] = {
+#if defined(NSS_DP_IPQ95XX)
+	/*
+	 * Per GMAC DMA driver statistics are
+	 * supported today only for IPQ95xx.
+	 */
+	{"rx_bytes", SYN_STAT(rx_bytes)},
+	{"rx_packets", SYN_STAT(rx_packets)},
+	{"rx_dropped", SYN_STAT(rx_dropped)},
+	{"rx_fraglist_packets", SYN_STAT(rx_fraglist_packets)},
+	{"rx_nr_frag_packets", SYN_STAT(rx_nr_frag_packets)},
+	{"rx_nr_frag_headroom_err", SYN_STAT(rx_nr_frag_headroom_err)},
+	{"tx_bytes", SYN_STAT(tx_bytes)},
+	{"tx_packets", SYN_STAT(tx_packets)},
+	{"tx_dropped", SYN_STAT(tx_dropped)},
+	{"tx_nr_frag_packets", SYN_STAT(tx_nr_frag_packets)},
+	{"tx_fraglist_packets", SYN_STAT(tx_fraglist_packets)},
+	{"tx_fraglist_nr_frags_packets", SYN_STAT(tx_fraglist_with_nr_frags_packets)},
+	{"tx_tso_packets", SYN_STAT(tx_tso_packets)},
+#endif
+};
+
+/*
+ * Array of strings describing xmib statistics
+ */
+static const struct syn_ethtool_stats syn_gstrings_xmib_stats[] = {
+	{"rx_frame", SYN_XMIB_STAT(RxFrame)},
+	{"rx_bytes", SYN_XMIB_STAT(RxByte)},
+	{"rx_bytes_g", SYN_XMIB_STAT(RxByteGood)},
+	{"rx_broadcast", SYN_XMIB_STAT(RxBroadGood)},
+	{"rx_multicast", SYN_XMIB_STAT(RxMultiGood)},
+	{"rx_crc_err", SYN_XMIB_STAT(RxFcsErr)},
+	{"rx_runt_err", SYN_XMIB_STAT(RxRuntErr)},
+	{"rx_jabber_err", SYN_XMIB_STAT(RxJabberError)},
+	{"rx_undersize", SYN_XMIB_STAT(RxUndersizeGood)},
+	{"rx_oversize", SYN_XMIB_STAT(RxOversizeGood)},
+	{"rx_pkt64", SYN_XMIB_STAT(Rx64Byte)},
+	{"rx_pkt65to127", SYN_XMIB_STAT(Rx128Byte)},
+	{"rx_pkt128to255", SYN_XMIB_STAT(Rx256Byte)},
+	{"rx_pkt256to511", SYN_XMIB_STAT(Rx512Byte)},
+	{"rx_pkt512to1023", SYN_XMIB_STAT(Rx1024Byte)},
+	{"rx_pkt1024tomax", SYN_XMIB_STAT(RxMaxByte)},
+	{"rx_unicast", SYN_XMIB_STAT(RxUnicastGood)},
+	{"rx_len_err", SYN_XMIB_STAT(RxLengthError)},
+	{"rx_outofrange_err_ctr", SYN_XMIB_STAT(RxOutOfRangeError)},
+	{"rx_pause", SYN_XMIB_STAT(RxPause)},
+	{"rx_fifo_overflow", SYN_XMIB_STAT(RxOverFlow)},
+	{"rx_vlan", SYN_XMIB_STAT(RxVLANFrameGoodBad)},
+	{"rx_wdog", SYN_XMIB_STAT(RxWatchDogError)},
+	{"rx_lpi_usec_ctr", SYN_XMIB_STAT(RxLPIUsec)},
+	{"rx_lpi_tran_ctr", SYN_XMIB_STAT(RxLPITran)},
+	{"rx_drop_frame_ctr", SYN_XMIB_STAT(RxDropFrameGoodBad)},
+	{"rx_drop_byte_ctr", SYN_XMIB_STAT(RxDropByteGoodBad)},
+	{"tx_bytes", SYN_XMIB_STAT(TxByte)},
+	{"tx_frame", SYN_XMIB_STAT(TxFrame)},
+	{"tx_broadcast", SYN_XMIB_STAT(TxBroadGood)},
+	{"tx_broadcast_gb", SYN_XMIB_STAT(TxBroad)},
+	{"tx_multicast", SYN_XMIB_STAT(TxMultiGood)},
+	{"tx_multicast_gb", SYN_XMIB_STAT(TxMulti)},
+	{"tx_pkt64", SYN_XMIB_STAT(Tx64Byte)},
+	{"tx_pkt65to127", SYN_XMIB_STAT(Tx128Byte)},
+	{"tx_pkt128to255", SYN_XMIB_STAT(Tx256Byte)},
+	{"tx_pkt256to511", SYN_XMIB_STAT(Tx512Byte)},
+	{"tx_pkt512to1023", SYN_XMIB_STAT(Tx1024Byte)},
+	{"tx_pkt1024tomax", SYN_XMIB_STAT(TxMaxByte)},
+	{"tx_unicast", SYN_XMIB_STAT(TxUnicast)},
+	{"tx_underflow_err", SYN_XMIB_STAT(TxUnderFlowError)},
+	{"tx_bytes_g", SYN_XMIB_STAT(TxByteGood)},
+	{"tx_frame_g", SYN_XMIB_STAT(TxFrameGood)},
+	{"tx_pause", SYN_XMIB_STAT(TxPause)},
+	{"tx_vlan", SYN_XMIB_STAT(TxVLANFrameGood)},
+	{"tx_lpi_usec_ctr", SYN_XMIB_STAT(TxLPIUsec)},
+	{"tx_lpi_tran_ctr", SYN_XMIB_STAT(TxLPITran)},
+};
+
+/*
+ * Array of strings describing private flag names
+ */
+static const char *const syn_strings_priv_flags[] = {
+	"test",
+};
+
+#define SYN_STATS_LEN		ARRAY_SIZE(syn_gstrings_stats)
+#define SYN_MIB_STATS_LEN	ARRAY_SIZE(syn_gstrings_xmib_stats)
+#define SYN_PRIV_FLAGS_LEN	ARRAY_SIZE(syn_strings_priv_flags)
+
+/*
+ * syn_rx_flow_control()
+ */
+static void syn_rx_flow_control(struct nss_gmac_hal_dev *nghd,
+				     bool enabled)
+{
+	BUG_ON(nghd == NULL);
+
+	if (enabled)
+		syn_set_rx_flow_ctrl(nghd);
+	else
+		syn_clear_rx_flow_ctrl(nghd);
+}
+
+/*
+ * syn_tx_flow_control()
+ */
+static void syn_tx_flow_control(struct nss_gmac_hal_dev *nghd,
+				     bool enabled)
+{
+	BUG_ON(nghd == NULL);
+
+	if (enabled)
+		syn_set_tx_flow_ctrl(nghd);
+	else
+		syn_clear_tx_flow_ctrl(nghd);
+}
+
+/*
+ * syn_get_max_frame_size()
+ */
+static int32_t syn_get_max_frame_size(struct nss_gmac_hal_dev *nghd)
+{
+	int ret;
+	uint32_t mtu;
+
+	ret = fal_port_max_frame_size_get(0, nghd->mac_id, &mtu);
+
+	if (!ret)
+		return mtu;
+
+	return ret;
+}
+
+/*
+ * syn_set_max_frame_size()
+ */
+static int32_t syn_set_max_frame_size(struct nss_gmac_hal_dev *nghd,
+					uint32_t val)
+{
+	/*
+	 * TODO: In override mode, the NPU configures
+	 * the max frame size into HW, so we do not
+	 * need to do configure the HW here. When we
+	 * need to support changing max frame size for
+	 * host mode DMA driver for IPQ807x/IPQ60xx,
+	 * we would need to call fal_port_max_frame_size_set()
+	 * here by differentiating between override mode and host mode.
+	 */
+	return 0;
+}
+
+/*
+ * syn_get_netdev_stats()
+ */
+static int syn_get_netdev_stats(struct nss_gmac_hal_dev *nghd,
+		struct rtnl_link_stats64 *stats)
+{
+	fal_xgmib_info_t hal_stats;
+
+	BUG_ON(nghd == NULL);
+
+	memset(&hal_stats, 0, sizeof(fal_xgmib_info_t));
+	if (syn_get_xmib_stats(nghd, &hal_stats)) {
+		return -1;
+	}
+
+	stats->rx_packets = hal_stats.RxUnicastGood
+		+ hal_stats.RxBroadGood + hal_stats.RxMultiGood;
+	stats->tx_packets = hal_stats.TxUnicast
+		+ hal_stats.TxBroadGood + hal_stats.TxMultiGood;
+	stats->rx_bytes = hal_stats.RxByte;
+	stats->tx_bytes = hal_stats.TxByte;
+	stats->multicast = hal_stats.RxMultiGood;
+
+	/*
+	 * Rx error
+	 */
+	stats->rx_crc_errors = hal_stats.RxFcsErr;
+	stats->rx_frame_errors = hal_stats.RxRuntErr;
+	stats->rx_fifo_errors = hal_stats.RxOverFlow;
+	stats->rx_length_errors = hal_stats.RxLengthError;
+	stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors
+		+ stats->rx_fifo_errors + stats->rx_length_errors;
+	stats->rx_dropped = hal_stats.RxDropFrameGoodBad + stats->rx_errors;
+
+	/*
+	 * Tx error
+	 */
+	stats->tx_fifo_errors = hal_stats.TxUnderFlowError + hal_stats.RxOverFlow;
+	stats->tx_errors = stats->tx_fifo_errors;
+
+	return 0;
+}
+
+/*
+ * syn_get_eth_stats()
+ */
+static int32_t syn_get_eth_stats(struct nss_gmac_hal_dev *nghd,
+				   uint64_t *data, struct nss_dp_gmac_stats *stats)
+{
+	fal_xgmib_info_t mib_stats;
+	uint8_t *p = NULL;
+	int i, i_mib;
+
+	BUG_ON(nghd == NULL);
+
+	/*
+	 * Populate data plane statistics.
+	 */
+	for (i = 0; i < SYN_STATS_LEN; i++) {
+		p = ((uint8_t *)(stats) + syn_gstrings_stats[i].stat_offset);
+		data[i] = *(uint64_t *)p;
+	}
+
+	/*
+	 * Get MIB statistics
+	 */
+	memset(&mib_stats, 0, sizeof(fal_xgmib_info_t));
+	if (syn_get_xmib_stats(nghd, &mib_stats)) {
+		return -1;
+	}
+
+	/*
+	 * Populate MIB statistics
+	 */
+	for (i_mib = 0; i_mib < SYN_MIB_STATS_LEN; i_mib++) {
+		p = ((uint8_t *)(&mib_stats) +
+			syn_gstrings_xmib_stats[i_mib].stat_offset);
+		i = SYN_STATS_LEN + i_mib;
+		data[i] = *(uint32_t *)p;
+	}
+
+	return 0;
+}
+
+/*
+ * syn_get_strset_count()
+ */
+static int32_t syn_get_strset_count(struct nss_gmac_hal_dev *nghd,
+					 int32_t sset)
+{
+	struct net_device *netdev;
+
+	BUG_ON(nghd == NULL);
+
+	netdev = nghd->netdev;
+
+	switch (sset) {
+	case ETH_SS_STATS:
+		return (SYN_STATS_LEN + SYN_MIB_STATS_LEN);
+
+	case ETH_SS_PRIV_FLAGS:
+		return SYN_PRIV_FLAGS_LEN;
+	}
+
+	netdev_dbg(netdev, "%s: Invalid string set\n", __func__);
+	return -EPERM;
+}
+
+/*
+ * syn_get_strings()
+ */
+static int32_t syn_get_strings(struct nss_gmac_hal_dev *nghd,
+				    int32_t stringset, uint8_t *data)
+{
+	struct net_device *netdev;
+	int i;
+
+	BUG_ON(nghd == NULL);
+
+	netdev = nghd->netdev;
+
+	switch (stringset) {
+	case ETH_SS_STATS:
+		for (i = 0; i < SYN_STATS_LEN; i++) {
+			memcpy(data, syn_gstrings_stats[i].stat_string,
+				strlen(syn_gstrings_stats[i].stat_string));
+			data += ETH_GSTRING_LEN;
+		}
+
+		for (i = 0; i < SYN_MIB_STATS_LEN; i++) {
+			memcpy(data, syn_gstrings_xmib_stats[i].stat_string,
+				strlen(syn_gstrings_xmib_stats[i].stat_string));
+			data += ETH_GSTRING_LEN;
+		}
+
+		break;
+
+	case ETH_SS_PRIV_FLAGS:
+		for (i = 0; i < SYN_PRIV_FLAGS_LEN; i++) {
+			memcpy(data, syn_strings_priv_flags[i],
+				strlen(syn_strings_priv_flags[i]));
+			data += ETH_GSTRING_LEN;
+		}
+
+		break;
+
+	default:
+		netdev_dbg(netdev, "%s: Invalid string set\n", __func__);
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+/*
+ * syn_send_pause_frame()
+ */
+static void syn_send_pause_frame(struct nss_gmac_hal_dev *nghd)
+{
+	BUG_ON(nghd == NULL);
+
+	syn_send_tx_pause_frame(nghd);
+}
+
+/*
+ * syn_start
+ */
+static int32_t syn_start(struct nss_gmac_hal_dev *nghd)
+{
+	BUG_ON(nghd == NULL);
+
+	syn_tx_enable(nghd);
+	syn_rx_enable(nghd);
+	syn_set_full_duplex(nghd);
+
+	netdev_dbg(nghd->netdev,
+			"%s: mac_base:0x%px tx_enable:0x%x rx_enable:0x%x\n",
+			__func__,
+			nghd->mac_base,
+			hal_read_relaxed_reg(nghd->mac_base,
+				SYN_MAC_TX_CONFIG),
+			hal_read_relaxed_reg(nghd->mac_base,
+				SYN_MAC_RX_CONFIG));
+
+	return 0;
+}
+
+/*
+ * syn_stop
+ */
+static int32_t syn_stop(struct nss_gmac_hal_dev *nghd)
+{
+	BUG_ON(nghd == NULL);
+
+	syn_tx_disable(nghd);
+	syn_rx_disable(nghd);
+
+	netdev_dbg(nghd->netdev, "%s: Stopping mac_base:0x%px\n", __func__,
+		   nghd->mac_base);
+
+	return 0;
+}
+
+/*
+ * syn_init()
+ */
+static void *syn_init(struct nss_gmac_hal_platform_data *gmacpdata)
+{
+	struct syn_hal_dev *shd = NULL;
+	struct net_device *ndev = NULL;
+	struct nss_dp_dev *dp_priv = NULL;
+	struct resource *res;
+
+	ndev = gmacpdata->netdev;
+	dp_priv = netdev_priv(ndev);
+
+	res = platform_get_resource(dp_priv->pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		netdev_dbg(ndev, "Resource get failed.\n");
+		return NULL;
+	}
+
+	shd = (struct syn_hal_dev *)devm_kzalloc(&dp_priv->pdev->dev,
+					sizeof(struct syn_hal_dev),
+					GFP_KERNEL);
+	if (!shd) {
+		netdev_dbg(ndev, "kzalloc failed. Returning...\n");
+		return NULL;
+	}
+
+	shd->nghd.mac_reg_len = resource_size(res);
+	shd->nghd.memres = devm_request_mem_region(&dp_priv->pdev->dev,
+							res->start,
+							resource_size(res),
+							ndev->name);
+	if (!shd->nghd.memres) {
+		netdev_dbg(ndev, "Request mem region failed. Returning.\n");
+		devm_kfree(&dp_priv->pdev->dev, shd);
+		return NULL;
+	}
+
+	/* Save netdev context in syn HAL context */
+	shd->nghd.netdev = gmacpdata->netdev;
+	shd->nghd.mac_id = gmacpdata->macid;
+
+	/* Populate the mac base addresses */
+	shd->nghd.mac_base =
+		devm_ioremap_nocache(&dp_priv->pdev->dev, res->start,
+				     resource_size(res));
+	if (!shd->nghd.mac_base) {
+		netdev_dbg(ndev, "ioremap fail.\n");
+		devm_release_mem_region(&dp_priv->pdev->dev,
+				shd->nghd.memres->start,
+				shd->nghd.mac_reg_len);
+		devm_kfree(&dp_priv->pdev->dev, shd);
+		return NULL;
+	}
+
+	spin_lock_init(&shd->nghd.slock);
+
+	netdev_info(ndev, "ioremap OK.Size 0x%x Ndev base 0x%lx macbase 0x%px\n",
+			gmacpdata->reg_len,
+			ndev->base_addr,
+			shd->nghd.mac_base);
+
+	/* Reset MIB Stats */
+	if (fal_mib_port_flush_counters(0, shd->nghd.mac_id)) {
+		netdev_dbg(ndev, "MIB stats Reset fail.\n");
+	}
+
+	return (struct nss_gmac_hal_dev *)shd;
+}
+
+/*
+ * syn_set_mac_address()
+ */
+static void syn_set_mac_address(struct nss_gmac_hal_dev *nghd,
+				     uint8_t *macaddr)
+{
+	uint32_t data;
+
+	BUG_ON(nghd == NULL);
+
+	data = (macaddr[5] << 8) | macaddr[4] | SYN_MAC_ADDR_RSVD_BIT;
+	hal_write_relaxed_reg(nghd->mac_base, SYN_MAC_ADDR0_HIGH, data);
+	data = (macaddr[3] << 24) | (macaddr[2] << 16) | (macaddr[1] << 8)
+		| macaddr[0];
+	hal_write_relaxed_reg(nghd->mac_base, SYN_MAC_ADDR0_LOW, data);
+}
+
+/*
+ * syn_get_mac_address()
+ */
+static void syn_get_mac_address(struct nss_gmac_hal_dev *nghd,
+				     uint8_t *macaddr)
+{
+	uint32_t data;
+
+	BUG_ON(nghd == NULL);
+
+	data = hal_read_relaxed_reg(nghd->mac_base, SYN_MAC_ADDR0_HIGH);
+	macaddr[5] = (data >> 8) & 0xff;
+	macaddr[4] = (data) & 0xff;
+
+	data = hal_read_relaxed_reg(nghd->mac_base, SYN_MAC_ADDR0_LOW);
+	macaddr[3] = (data >> 24) & 0xff;
+	macaddr[2] = (data >> 16) & 0xff;
+	macaddr[1] = (data >> 8) & 0xff;
+	macaddr[0] = (data) & 0xff;
+}
+
+/*
+ * syn_exit()
+ */
+static void syn_exit(struct nss_gmac_hal_dev *nghd)
+{
+	struct nss_dp_dev *dp_priv = NULL;
+	struct syn_hal_dev *shd = (struct syn_hal_dev *)nghd;
+
+	netdev_dbg(nghd->netdev, "Freeing up dev memory.\n");
+
+	dp_priv = netdev_priv(nghd->netdev);
+	devm_iounmap(&dp_priv->pdev->dev,
+			(void *)nghd->mac_base);
+	devm_release_mem_region(&dp_priv->pdev->dev,
+			(nghd->memres)->start,
+			nghd->mac_reg_len);
+
+	nghd->memres = NULL;
+	nghd->mac_base = NULL;
+
+	devm_kfree(&dp_priv->pdev->dev, shd);
+}
+
+/*
+ * MAC hal_ops base structure
+ */
+struct nss_gmac_hal_ops syn_gmac_ops = {
+	.init = &syn_init,
+	.start = &syn_start,
+	.stop = &syn_stop,
+	.exit = &syn_exit,
+	.setmacaddr = &syn_set_mac_address,
+	.getmacaddr = &syn_get_mac_address,
+	.rxflowcontrol = &syn_rx_flow_control,
+	.txflowcontrol = &syn_tx_flow_control,
+	.setmaxframe = &syn_set_max_frame_size,
+	.getmaxframe = &syn_get_max_frame_size,
+	.getndostats = &syn_get_netdev_stats,
+	.getssetcount = &syn_get_strset_count,
+	.getstrings = &syn_get_strings,
+	.getethtoolstats = &syn_get_eth_stats,
+	.sendpause = &syn_send_pause_frame,
+};
diff --git a/qca-nss-dp/hal/gmac_ops/syn/xgmac/syn_reg.h b/qca-nss-dp/hal/gmac_ops/syn/xgmac/syn_reg.h
new file mode 100644
index 0000000..f76fce1
--- /dev/null
+++ b/qca-nss-dp/hal/gmac_ops/syn/xgmac/syn_reg.h
@@ -0,0 +1,255 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016,2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF0
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __SYN_REG_H__
+#define __SYN_REG_H__
+
+/*
+ *
+ MAC Register Offset
+ *
+ */
+#define SYN_MAC_TX_CONFIG		0x0000
+#define SYN_MAC_RX_CONFIG		0x0004
+#define SYN_MAC_PACKET_FILTER		0x0008
+#define SYN_MAC_WDOG_TIMEOUT		0x000c
+#define SYN_MAC_HASH_TBL_REG0		0x0010
+#define SYN_MAC_VLAN_TAG		0x0050
+#define SYN_MAC_VLAN_HASH_TBL		0x0058
+#define SYN_MAC_VLAN_INCL		0x0060
+#define SYN_MAC_INNER_VLAN_INCL		0x0064
+#define SYN_MAC_RX_ETH_TYP_MATCH	0x006c
+#define SYN_MAC_Q0_TX_FLOW_CTL		0x0070
+#define SYN_MAC_Q1_TX_FLOW_CTL		0x0074
+#define SYN_MAC_Q2_TX_FLOW_CTL		0x0078
+#define SYN_MAC_Q3_TX_FLOW_CTL		0x007c
+#define SYN_MAC_Q4_TX_FLOW_CTL		0x0080
+#define SYN_MAC_Q5_TX_FLOW_CTL		0x0084
+#define SYN_MAC_Q6_TX_FLOW_CTL		0x0088
+#define SYN_MAC_Q7_TX_FLOW_CTL		0x008c
+#define SYN_MAC_RX_FLOW_CTL		0x0090
+#define SYN_MAC_RXQ_CTL0		0x00a0
+#define SYN_MAC_RXQ_CTL1		0x00a4
+#define SYN_MAC_RXQ_CTL2		0x00a8
+#define SYN_MAC_RXQ_CTL3		0x00ac
+#define SYN_MAC_INT_STATUS		0x00b0
+#define SYN_MAC_INT_ENABLE		0x00b4
+#define SYN_MAC_TX_RX_STATUS		0x00b8
+#define SYN_MAC_PMT_CTL_STATUS		0x00c0
+#define SYN_MAC_RWK_PACKET_FILTER	0x00c4
+#define SYN_MAC_LPI_CTL_STATUS		0x00d0
+#define SYN_MAC_LPI_TIMER_STATUS	0x00d4
+#define SYN_MAC_VERSION			0x0110
+#define SYN_MAC_DEBUG			0x0114
+#define SYN_MAC_FW_FEATURE0		0x011c
+#define SYN_MAC_FW_FEATURE1		0x0120
+#define SYN_MAC_FW_FEATURE2		0x0124
+#define SYN_MAC_GPIO_CTL		0x0278
+#define SYN_MAC_GPIO_STATUS		0x027c
+#define SYN_MAC_ADDR0_HIGH		0x0300
+#define SYN_MAC_ADDR0_LOW		0x0304
+#define SYN_MAC_ADDR1_HIGH		0x0308
+#define SYN_MAC_ADDR1_LOW		0x030c
+#define SYN_MAC_TS_CTL			0x0d00
+#define SYN_MAC_SUB_SEC_INCR		0x0d04
+#define SYN_MAC_SYS_TIME_SECS		0x0d08
+#define SYN_MAC_SYS_TIME_NSECS		0x0d0c
+#define SYN_MAC_SYS_TIME_SECS_UPDATE	0x0d10
+#define SYN_MAC_SYS_TIME_NSECS_UPDATE	0x0d14
+#define SYN_MAC_TS_ADDEND		0x0d18
+#define SYN_MAC_TS_STATUS		0x0d20
+#define SYN_MAC_TX_TS_STATUS_NSECS	0x0d30
+#define SYN_MAC_TX_TS_STATUS_SECS	0x0d34
+#define SYN_MAC_PPS_CTL			0x0d70
+#define SYN_MAC_MMC_CTL			0x0800
+#define SYN_MAC_MMC_RX_INT		0x0804
+#define SYN_MAC_MMC_TX_INT		0x0808
+#define SYN_MAC_MMC_RX_INT_EN		0x080c
+#define SYN_MAC_MMC_TX_INT_EN		0x0810
+
+/* MAC TX MMC Counters */
+#define SYN_MAC_MMC_TX_BCAST_LO		0x0824
+#define SYN_MAC_MMC_TX_BCAST_HI		0x0828
+#define SYN_MAC_MMC_TX_FRAME_LO		0x0894
+#define SYN_MAC_MMC_TX_FRAME_HI		0x0898
+#define SYN_MAC_MMC_TX_MCAST_LO		0x082c
+#define SYN_MAC_MMC_TX_MCAST_HI		0x0830
+#define SYN_MAC_MMC_TX_PKT64_LO		0x0834
+#define SYN_MAC_MMC_TX_PKT64_HI		0x0838
+#define SYN_MAC_MMC_TX_PKT65TO127_LO	0x083c
+#define SYN_MAC_MMC_TX_PKT65TO127_HI	0x0840
+#define SYN_MAC_MMC_TX_PKT128TO255_LO	0x0844
+#define SYN_MAC_MMC_TX_PKT128TO255_HI	0x0848
+#define SYN_MAC_MMC_TX_PKT256TO511_LO	0x084c
+#define SYN_MAC_MMC_TX_PKT256TO511_HI	0x0850
+#define SYN_MAC_MMC_TX_PKT512TO1023_LO	0x0854
+#define SYN_MAC_MMC_TX_PKT512TO1023_HI	0x0858
+#define SYN_MAC_MMC_TX_PKT1024TOMAX_LO	0x085c
+#define SYN_MAC_MMC_TX_PKT1024TOMAX_HI	0x0860
+#define SYN_MAC_MMC_TX_UNICAST_LO	0x0864
+#define SYN_MAC_MMC_TX_UNICAST_HI	0x0868
+#define SYN_MAC_MMC_TX_MCAST_GB_LO	0x086c
+#define SYN_MAC_MMC_TX_MCAST_GB_HI	0x0870
+#define SYN_MAC_MMC_TX_BCAST_GB_LO	0x0874
+#define SYN_MAC_MMC_TX_BCAST_GB_HI	0x0878
+#define SYN_MAC_MMC_TX_UNDERFLOW_ERR_LO	0x087c
+#define SYN_MAC_MMC_TX_UNDERFLOW_ERR_HI	0x0880
+#define SYN_MAC_MMC_TX_BYTES_LO		0x0884
+#define SYN_MAC_MMC_TX_BYTES_HI		0x0888
+#define SYN_MAC_MMC_TX_PAUSE_FRAME_LO	0x0894
+#define SYN_MAC_MMC_TX_PAUSE_FRAME_HI	0x0898
+#define SYN_MAC_MMC_TX_VLAN_LO		0x089c
+#define SYN_MAC_MMC_TX_VLAN_HI		0x08a0
+#define SYN_MAC_MMC_TX_LPI_USEC_CTR_LO	0x08a4
+#define SYN_MAC_MMC_TX_LPI_USEC_CTR_HI	0x08a8
+
+/* MAC RX MMC Counters */
+#define SYN_MAC_MMC_RX_FRAME_LO		0x0900
+#define SYN_MAC_MMC_RX_FRAME_HI		0x0904
+#define SYN_MAC_MMC_RX_BYTES_LO		0x0910
+#define SYN_MAC_MMC_RX_BYTES_HI		0x0914
+#define SYN_MAC_MMC_RX_BCAST_LO		0x0918
+#define SYN_MAC_MMC_RX_BCAST_HI		0x091c
+#define SYN_MAC_MMC_RX_MCAST_LO		0x0920
+#define SYN_MAC_MMC_RX_MCAST_HI		0x0924
+#define SYN_MAC_MMC_RX_CRC_ERR_LO	0x0928
+#define SYN_MAC_MMC_RX_CRC_ERR_HI	0x092c
+#define SYN_MAC_MMC_RX_RUNT_ERR		0x0930
+#define SYN_MAC_MMC_RX_JABBER_ERR	0x0934
+#define SYN_MAC_MMC_RX_UNDERSIZE	0x0938
+#define SYN_MAC_MMC_RX_OVERSIZE		0x093c
+#define SYN_MAC_MMC_RX_PKT64_LO		0x0940
+#define SYN_MAC_MMC_RX_PKT64_HI		0x0944
+#define SYN_MAC_MMC_RX_PKT65TO127_LO	0x0948
+#define SYN_MAC_MMC_RX_PKT65TO127_HI	0x094c
+#define SYN_MAC_MMC_RX_PKT128TO255_LO	0x0950
+#define SYN_MAC_MMC_RX_PKT128TO255_HI	0x0954
+#define SYN_MAC_MMC_RX_PKT256TO511_LO	0x0958
+#define SYN_MAC_MMC_RX_PKT256TO511_HI	0x095c
+#define SYN_MAC_MMC_RX_PKT512TO1023_LO	0x0960
+#define SYN_MAC_MMC_RX_PKT512TO1023_HI	0x0964
+#define SYN_MAC_MMC_RX_PKT1024TOMAX_LO	0x0968
+#define SYN_MAC_MMC_RX_PKT1024TOMAX_HI	0x096c
+#define SYN_MAC_MMC_RX_UNICAST_LO	0x0970
+#define SYN_MAC_MMC_RX_UNICAST_HI	0x0974
+#define SYN_MAC_MMC_RX_LEN_ERR_LO	0x0978
+#define SYN_MAC_MMC_RX_LEN_ERR_HI	0x097c
+#define SYN_MAC_MMC_RX_PAUSE_FRAME_LO	0x0988
+#define SYN_MAC_MMC_RX_PAUSE_FRAME_HI	0x098c
+#define SYN_MAC_MMC_RX_FIFO_OVERFLOW_LO	0x0990
+#define SYN_MAC_MMC_RX_FIFO_OVERFLOW_HI	0x0994
+#define SYN_MAC_MMC_RX_VLAN_FRAME_LO	0x0998
+#define SYN_MAC_MMC_RX_VLAN_FRAME_HI	0x099c
+#define SYN_MAC_MMC_RX_LPI_USEC_CTR_LO	0x09a4
+#define SYN_MAC_MMC_RX_LPI_USEC_CTR_HI	0x09a8
+#define SYN_MAC_MMC_RX_DISCARD_FRAME_LO	0x09ac
+#define SYN_MAC_MMC_RX_DISCARD_FRAME_HI	0x09b0
+
+/* MAC Register Bit Definitions*/
+
+/* SYN_MAC_Q0_TX_FLOW_CTL Bit definitions */
+#define SYN_MAC_TX_PAUSE_SEND		0x00000001
+#define SYN_MAC_TX_FLOW_ENABLE		0x00000002
+#define SYN_MAC_TX_PAUSE_LOW_THRESHOLD	0x00000070
+#define SYN_MAC_ADDR_RSVD_BIT		0x80000000
+
+/* SYN_MAC_RX_FLOW_CTL Bit definitions */
+#define SYN_MAC_RX_FLOW_ENABLE		0x00000001
+
+/* SYN_MAC_TX_CONFIG Bit definitions */
+#define SYN_MAC_TX_ENABLE		0x00000001
+#define SYN_MAC_TX_SPEED_SELECT		0x60000000
+
+/* SYN_MAC_RX_CONFIG Bit definitions */
+#define SYN_MAC_RX_ENABLE		0x00000001
+#define SYN_MAC_JUMBO_FRAME_ENABLE	0x00000100
+
+#define SYN_MAC_SPEED_10G		0x0
+#define SYN_MAC_SPEED_2_5G		0x2
+#define SYN_MAC_SPEED_1G		0x3
+#define SYN_MAC_SPEED_BITPOS		29
+#define SYN_MAC_SPEED_BITMASK		0x3
+
+#define SYN_MAC_DEFAULT_MAX_FRAME_SIZE	1518
+#define SYN_MAC_MAX_FRAME_SIZE_BITPOS	16
+#define SYN_MAC_MAX_FRAME_SIZE_BITMASK	0x3fff
+
+/* SYN_MAC_MMC_CTL Bit definitions */
+#define  SYN_MAC_MMC_RSTONRD		0x00000004
+
+/*
+ *
+ MTL Register Offset
+ *
+ */
+#define SYN_MTL_OPER_MODE		0x1000
+#define SYN_MTL_DEBUG_CTL		0x1008
+#define SYN_MTL_DEBUG_STATUS		0x100c
+#define SYN_MTL_DEBUG_DATA		0x1010
+#define SYN_MTL_INT_STATUS		0x1020
+#define SYN_MTL_RXQ_DMA_MAP0		0x1030
+#define SYN_MTL_RXQ_DMA_MAP1		0x1034
+#define SYN_MTL_RXQ_DMA_MAP2		0x1038
+#define SYN_MTL_TC_PRIO_MAP0		0x1040
+#define SYN_MTL_TC_PRIO_MAP1		0x1044
+#define SYN_MTL_TXQ0_OPER_MODE		0x1100
+#define SYN_MTL_TXQ0_UNDERFLOW		0x1104
+#define SYN_MTL_TXQ0_DEBUG		0x1108
+#define SYN_MTL_TC0_ETS_CTL		0x1110
+#define SYN_MTL_TC0_ETS_STATUS		0x1114
+#define SYN_MTL_TC0_QUANTUM_WEIGHT	0x1118
+#define SYN_MTL_RXQ0_DEBUG		0x1148
+#define SYN_MTL_RXQ0_CTL		0x114c
+#define SYN_MTL_RXQ0_FLOW_CTL		0x1150
+#define SYN_MTL_Q0_INT_ENABLE		0x1170
+#define SYN_MTL_Q0_INT_STATUS		0x1174
+
+/* MTL Register Bit definitions */
+
+/*
+ *
+ DMA Register Offset
+ *
+ */
+#define SYN_DMA_MODE			0x3000
+#define SYN_DMA_SYSBUS_MODE		0x3004
+#define SYN_DMA_INT_STATUS		0x3008
+#define SYN_DMA_AXI_TX_AR_ACE_CTL	0x3010
+#define SYN_DMA_AXI_RX_AW_ACE_CTL	0x3018
+#define SYN_DMA_AXI_TXRX_AWAR_ACE_CTL	0x301c
+#define SYN_DMA_DEBUG_STATUS0		0x3020
+#define SYN_DMA_DEBUG_STATUS1		0x3024
+#define SYN_DMA_TX_EDMA_CTL		0x3040
+#define SYN_DMA_RX_EDMA_CTL		0x3044
+#define SYN_DMA_CH0_CTL			0x3100
+#define SYN_DMA_CH0_TX_CTL		0x3104
+#define SYN_DMA_CH0_RX_CTL		0x3108
+#define SYN_DMA_CH0_TXDESC_LIST_HADDR	0x3110
+#define SYN_DMA_CH0_TXDESC_LIST_LADDR	0x3114
+#define SYN_DMA_CH0_RXDESC_LIST_HADDR	0x3118
+#define SYN_DMA_CH0_RXDESC_LIST_LADDR	0x311c
+#define SYN_DMA_CH0_TXDESC_TAIL_LPTR	0x3124
+#define SYN_DMA_CH0_RXDESC_TAIL_LPTR	0x312c
+#define SYN_DMA_CH0_TXDESC_RING_LEN	0x3130
+#define SYN_DMA_CH0_RXDESC_RING_LEN	0x3134
+#define SYN_DMA_INT_ENABLE		0x3138
+#define SYN_DMA_RX_INT_WDOG_TIMER	0x313c
+
+/* DMA Register Bit definitions */
+
+#endif /*__SYN_REG_H__*/
diff --git a/qca-nss-dp/hal/include/nss_dp_hal.h b/qca-nss-dp/hal/include/nss_dp_hal.h
new file mode 100644
index 0000000..22e83d8
--- /dev/null
+++ b/qca-nss-dp/hal/include/nss_dp_hal.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_HAL_H__
+#define __NSS_DP_HAL_H__
+
+#include "nss_dp_dev.h"
+
+/*
+ * nss_dp_hal_get_gmac_ops()
+ *	Returns gmac hal ops based on the GMAC type.
+ */
+static inline struct nss_gmac_hal_ops *nss_dp_hal_get_gmac_ops(uint32_t gmac_type)
+{
+	return dp_global_ctx.gmac_hal_ops[gmac_type];
+}
+
+/*
+ * nss_dp_hal_set_gmac_ops()
+ *	Sets dp global gmac hal ops based on the GMAC type.
+ */
+static inline void nss_dp_hal_set_gmac_ops(struct nss_gmac_hal_ops *hal_ops, uint32_t gmac_type)
+{
+	dp_global_ctx.gmac_hal_ops[gmac_type] = hal_ops;
+}
+
+/*
+ * HAL functions implemented by SoC specific source files.
+ */
+extern struct nss_dp_data_plane_ops *nss_dp_hal_get_data_plane_ops(void);
+extern bool nss_dp_hal_init(void);
+extern void nss_dp_hal_cleanup(void);
+
+#endif	/* __NSS_DP_HAL_H__ */
diff --git a/qca-nss-dp/hal/include/nss_dp_hal_if.h b/qca-nss-dp/hal/include/nss_dp_hal_if.h
new file mode 100644
index 0000000..a021d13
--- /dev/null
+++ b/qca-nss-dp/hal/include/nss_dp_hal_if.h
@@ -0,0 +1,174 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017,2020-2021 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF0
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_DP_HAL_IF_H__
+#define __NSS_DP_HAL_IF_H__
+
+#include <linux/ioport.h>
+#include <linux/netdevice.h>
+#include <uapi/linux/if_link.h>
+
+enum nss_gmac_hal_device_type {
+	GMAC_HAL_TYPE_QCOM = 0,	/* 1G GMAC type */
+	GMAC_HAL_TYPE_SYN_XGMAC,/* Synopsys XGMAC type */
+	GMAC_HAL_TYPE_SYN_GMAC,	/* Synopsys 1G GMAC type */
+	GMAC_HAL_TYPE_MAX
+};
+
+/*
+ * nss_gmac_hal_platform_data
+ */
+struct nss_gmac_hal_platform_data {
+	struct net_device *netdev; /* Net device */
+	uint32_t reg_len;	/* Register space length */
+	uint32_t mactype;	/* MAC chip type */
+	uint32_t macid;		/* MAC sequence id on the Chip */
+};
+
+/*
+ * NSS GMAC HAL device data
+ */
+struct nss_gmac_hal_dev {
+	void __iomem *mac_base;	/* Base address of MAC registers	*/
+	uint32_t version;	/* GMAC Revision version		*/
+	uint32_t drv_flags;	/* Driver specific feature flags	*/
+
+	/*
+	 * Phy related stuff
+	 */
+	uint32_t link_state;	/* Link status as reported by the Phy	*/
+	uint32_t duplex_mode;	/* Duplex mode of the Phy		*/
+	uint32_t speed;		/* Speed of the Phy			*/
+	uint32_t loop_back_mode;/* Loopback status of the Phy		*/
+	uint32_t phy_mii_type;	/* RGMII/SGMII/XSGMII			*/
+
+	struct net_device *netdev;
+	struct resource *memres;
+	uint32_t mac_reg_len;	/* MAC Register block length		*/
+	uint32_t mac_id;	/* MAC sequence id on the Chip */
+	spinlock_t slock;	/* lock to protect concurrent reg access */
+};
+
+/*
+ * nss_gmac_hal_ops
+ */
+struct nss_gmac_hal_ops {
+	void* (*init)(struct nss_gmac_hal_platform_data *);
+	void (*exit)(struct nss_gmac_hal_dev *);
+	int32_t (*start)(struct nss_gmac_hal_dev *);
+	int32_t (*stop)(struct nss_gmac_hal_dev *);
+	void (*setmacaddr)(struct nss_gmac_hal_dev *, uint8_t *);
+	void (*getmacaddr)(struct nss_gmac_hal_dev *, uint8_t *);
+	void (*promisc)(struct nss_gmac_hal_dev *, bool enabled);
+	void (*multicast)(struct nss_gmac_hal_dev *, bool enabled);
+	void (*broadcast)(struct nss_gmac_hal_dev *, bool enabled);
+	void (*rxcsumoffload)(struct nss_gmac_hal_dev *, bool enabled);
+	void (*txcsumoffload)(struct nss_gmac_hal_dev *, bool enabled);
+	void (*rxflowcontrol)(struct nss_gmac_hal_dev *, bool enabled);
+	void (*txflowcontrol)(struct nss_gmac_hal_dev *, bool enabled);
+	int32_t (*getstats)(struct nss_gmac_hal_dev *);
+	int32_t (*setmaxframe)(struct nss_gmac_hal_dev *, uint32_t);
+	int32_t (*getmaxframe)(struct nss_gmac_hal_dev *);
+	int32_t (*getndostats)(struct nss_gmac_hal_dev *,
+			    struct rtnl_link_stats64 *);
+	void (*sendpause)(struct nss_gmac_hal_dev *);
+	void (*stoppause)(struct nss_gmac_hal_dev *);
+	int32_t (*getssetcount)(struct nss_gmac_hal_dev *, int32_t);
+	int32_t (*getstrings)(struct nss_gmac_hal_dev *, int32_t, uint8_t *);
+	int32_t (*getethtoolstats)(struct nss_gmac_hal_dev *, uint64_t *, struct nss_dp_gmac_stats *);
+};
+
+extern struct nss_gmac_hal_ops qcom_gmac_ops;
+extern struct nss_gmac_hal_ops syn_gmac_ops;
+
+/**********************************************************
+ * Common functions
+ **********************************************************/
+/*
+ * hal_read_reg()
+ */
+static inline uint32_t hal_read_reg(void __iomem *regbase, uint32_t regoffset)
+{
+	return (uint32_t)readl(regbase + regoffset);
+}
+
+/*
+ * hal_write_reg()
+ */
+static inline void hal_write_reg(void __iomem *regbase, uint32_t regoffset,
+								uint32_t val)
+{
+	writel(val, regbase + regoffset);
+}
+
+/*
+ * hal_read_relaxed_reg()
+ */
+static inline uint32_t hal_read_relaxed_reg(void __iomem *regbase,
+							uint32_t regoffset)
+{
+	return readl_relaxed(regbase + regoffset);
+}
+
+/*
+ * hal_write_relaxed_reg()
+ */
+static inline void hal_write_relaxed_reg(void __iomem *regbase,
+						uint32_t regoffset,
+						uint32_t regdata)
+{
+	writel_relaxed(regdata, regbase + regoffset);
+}
+
+/*
+ * hal_set_reg_bits()
+ */
+static inline void hal_set_reg_bits(void __iomem *regbase,
+				    uint32_t regoffset,
+				    uint32_t bitpos)
+{
+	uint32_t data;
+
+	data = bitpos | hal_read_relaxed_reg(regbase, regoffset);
+	hal_write_relaxed_reg(regbase, regoffset, data);
+}
+
+/*
+ * hal_clear_reg_bits()
+ */
+static inline void hal_clear_reg_bits(void __iomem *regbase,
+				      uint32_t regoffset,
+				      uint32_t bitpos)
+{
+	uint32_t data;
+
+	data = ~bitpos & hal_read_relaxed_reg(regbase, regoffset);
+	hal_write_relaxed_reg(regbase, regoffset, data);
+}
+
+/*
+ * hal_check_reg_bits()
+ */
+static inline bool hal_check_reg_bits(void __iomem *regbase,
+				      uint32_t regoffset,
+				      uint32_t bitpos)
+{
+	return (bitpos & hal_read_relaxed_reg(regbase, regoffset)) != 0;
+}
+
+#endif /* __NSS_DP_HAL_IF_H__ */
diff --git a/qca-nss-dp/hal/soc_ops/ipq50xx/nss_ipq50xx.c b/qca-nss-dp/hal/soc_ops/ipq50xx/nss_ipq50xx.c
new file mode 100644
index 0000000..f4975e9
--- /dev/null
+++ b/qca-nss-dp/hal/soc_ops/ipq50xx/nss_ipq50xx.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/of.h>
+#include <linux/ioport.h>
+#include <linux/qcom_scm.h>
+#include "nss_dp_hal.h"
+
+/*
+ * nss_dp_hal_tcsr_base_get()
+ *	Reads TCSR base address from DTS
+ */
+static uint32_t nss_dp_hal_tcsr_base_get(void)
+{
+	uint32_t tcsr_base_addr = 0;
+	struct device_node *dp_cmn;
+
+	/*
+	 * Get reference to NSS dp common device node
+	 */
+	dp_cmn = of_find_node_by_name(NULL, "nss-dp-common");
+	if (!dp_cmn) {
+		pr_info("%s: NSS DP common node not found\n", __func__);
+		return 0;
+	}
+
+	if (of_property_read_u32(dp_cmn, "qcom,tcsr-base", &tcsr_base_addr)) {
+		pr_err("%s: error reading TCSR base\n", __func__);
+	}
+	of_node_put(dp_cmn);
+
+	return tcsr_base_addr;
+}
+
+/*
+ * nss_dp_hal_tcsr_set()
+ *	Sets the TCSR axi cache override register
+ */
+static void nss_dp_hal_tcsr_set(void)
+{
+	void __iomem *tcsr_addr = NULL;
+	uint32_t tcsr_base;
+	int err;
+
+	tcsr_base = nss_dp_hal_tcsr_base_get();
+	if (!tcsr_base) {
+		pr_err("%s: Unable to get TCSR base address\n", __func__);
+		return;
+	}
+
+	/*
+	 * Check if Trust Zone is enabled in the system.
+	 * If yes, we need to go through SCM API call to program TCSR register.
+	 * If TZ is not enabled, we can write to the register directly.
+	 */
+	if (qcom_scm_is_available()) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		err = qcom_scm_tcsr_reg_write((tcsr_base + TCSR_GMAC_AXI_CACHE_OVERRIDE_OFFSET),
+						TCSR_GMAC_AXI_CACHE_OVERRIDE_VALUE);
+#else
+		err = qti_scm_tcsr_reg_write((tcsr_base + TCSR_GMAC_AXI_CACHE_OVERRIDE_OFFSET),
+						TCSR_GMAC_AXI_CACHE_OVERRIDE_VALUE);
+#endif
+		if (err) {
+			pr_err("%s: SCM TCSR write error: %d\n", __func__, err);
+		}
+	} else {
+		tcsr_addr = ioremap_nocache((tcsr_base + TCSR_GMAC_AXI_CACHE_OVERRIDE_OFFSET),
+						TCSR_GMAC_AXI_CACHE_OVERRIDE_REG_SIZE);
+		if (!tcsr_addr) {
+			pr_err("%s: ioremap failed\n", __func__);
+			return;
+		}
+		writel(TCSR_GMAC_AXI_CACHE_OVERRIDE_VALUE, tcsr_addr);
+		iounmap(tcsr_addr);
+	}
+}
+
+/*
+ * nss_dp_hal_get_data_plane_ops()
+ *	Return the data plane ops for registered data plane.
+ */
+struct nss_dp_data_plane_ops *nss_dp_hal_get_data_plane_ops(void)
+{
+	return &nss_dp_gmac_ops;
+}
+
+/*
+ * nss_dp_hal_init()
+ *	Sets the gmac ops based on the GMAC type.
+ */
+bool nss_dp_hal_init(void)
+{
+	/*
+	 * Bail out on not supported platform
+	 */
+	if (!of_machine_is_compatible("qcom,ipq5018")) {
+		return false;
+	}
+
+	nss_dp_hal_set_gmac_ops(&syn_gmac_ops, GMAC_HAL_TYPE_SYN_GMAC);
+
+	/*
+	 * Program the global GMAC AXI Cache override register
+	 * for optimized AXI DMA operation.
+	 */
+	nss_dp_hal_tcsr_set();
+	return true;
+}
+
+/*
+ * nss_dp_hal_cleanup()
+ *	Sets the gmac ops to NULL.
+ */
+void nss_dp_hal_cleanup(void)
+{
+	nss_dp_hal_set_gmac_ops(NULL, GMAC_HAL_TYPE_SYN_GMAC);
+}
diff --git a/qca-nss-dp/hal/soc_ops/ipq50xx/nss_ipq50xx.h b/qca-nss-dp/hal/soc_ops/ipq50xx/nss_ipq50xx.h
new file mode 100644
index 0000000..2cf0042
--- /dev/null
+++ b/qca-nss-dp/hal/soc_ops/ipq50xx/nss_ipq50xx.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_ARCH_H__
+#define __NSS_DP_ARCH_H__
+
+#define NSS_DP_HAL_MAX_PORTS			2
+#define NSS_DP_HAL_START_IFNUM			0
+
+/*
+ * Number of TX/RX queue supported
+ */
+#define NSS_DP_QUEUE_NUM			1
+
+/*
+ * TX/RX NAPI budget
+ */
+#define NSS_DP_HAL_RX_NAPI_BUDGET		32
+#define NSS_DP_HAL_TX_NAPI_BUDGET		32
+
+/*
+ * TCSR_GMAC_AXI_CACHE_OVERRIDE register size
+ */
+#define TCSR_GMAC_AXI_CACHE_OVERRIDE_REG_SIZE	4
+
+/*
+ * TCSR_GMAC_AXI_CACHE_OVERRIDE Register offset
+ */
+#define TCSR_GMAC_AXI_CACHE_OVERRIDE_OFFSET	0x6224
+
+/*
+ * Value for TCSR_GMAC_AXI_CACHE_OVERRIDE register
+ */
+#define TCSR_GMAC_AXI_CACHE_OVERRIDE_VALUE	0x05050505
+
+/**
+ * nss_dp_hal_gmac_stats_rx
+ *	Per-GMAC Rx statistics
+ */
+struct nss_dp_hal_gmac_stats_rx {
+	uint64_t rx_bytes;		/**< Number of RX bytes */
+	uint64_t rx_packets;		/**< Number of RX packets */
+	uint64_t rx_errors;		/**< Number of RX errors */
+	uint64_t rx_missed;		/**< Number of RX packets missed by the DMA */
+	uint64_t rx_descriptor_errors;	/**< Number of RX descriptor errors */
+	uint64_t rx_late_collision_errors;
+					/**< Number of RX late collision errors */
+	uint64_t rx_dribble_bit_errors;	/**< Number of RX dribble bit errors */
+	uint64_t rx_length_errors;	/**< Number of RX length errors */
+	uint64_t rx_ip_header_errors;	/**< Number of RX IP header errors read from rxdec */
+	uint64_t rx_ip_payload_errors;	/**< Number of RX IP payload errors */
+	uint64_t rx_no_buffer_errors;	/**< Number of RX no-buffer errors */
+	uint64_t rx_transport_csum_bypassed;
+					/**< Number of RX packets where the transport checksum was bypassed */
+	uint64_t rx_fifo_overflows;	/**< Number of RX FIFO overflows signalled by the DMA */
+	uint64_t rx_overflow_errors;	/**< Number of Rx Overflow errors received from Rx descriptors */
+	uint64_t rx_crc_errors;		/**< Number of Rx CRC errors */
+	uint64_t rx_skb_alloc_errors;	/**< Number of Rx skb alocation errors */
+	uint64_t rx_scatter_packets;	/**< Number of received scattered frames successful */
+	uint64_t rx_scatter_bytes;	/**< Number of bytes received for scattered frames */
+	uint64_t rx_scatter_errors;	/**< Number of RX scatter errors */
+};
+
+/**
+ * nss_dp_hal_gmac_stats_tx
+ *	Per-GMAC Tx statistics
+ */
+struct nss_dp_hal_gmac_stats_tx {
+	uint64_t tx_bytes;		/**< Number of TX bytes */
+	uint64_t tx_packets;		/**< Number of TX packets */
+	uint64_t tx_collisions;		/**< Number of TX collisions */
+	uint64_t tx_errors;		/**< Number of TX errors */
+	uint64_t tx_jabber_timeout_errors;
+					/**< Number of TX jabber timeout errors */
+	uint64_t tx_frame_flushed_errors;
+					/**< Number of TX frame flushed errors */
+	uint64_t tx_loss_of_carrier_errors;
+					/**< Number of TX loss of carrier errors */
+	uint64_t tx_no_carrier_errors;	/**< Number of TX no carrier errors */
+	uint64_t tx_late_collision_errors;
+					/**< Number of TX late collision errors */
+	uint64_t tx_excessive_collision_errors;
+					/**< Number of TX excessive collision errors */
+	uint64_t tx_excessive_deferral_errors;
+					/**< Number of TX excessive deferral errors */
+	uint64_t tx_underflow_errors;	/**< Number of TX underflow errors */
+	uint64_t tx_ip_header_errors;	/**< Number of TX IP header errors */
+	uint64_t tx_ip_payload_errors;	/**< Number of TX IP payload errors */
+	uint64_t tx_dropped;		/**< Number of TX dropped packets */
+	uint64_t tx_ts_create_errors;	/**< Number of tx timestamp creation errors */
+	uint64_t tx_desc_not_avail;	/**< TX descriptor unavailable */
+	uint64_t tx_nr_frags_pkts;	/**< Number of Tx scatter packets with nr_frags */
+	uint64_t tx_fraglist_pkts;	/**< Number of Tx scatter packets with frag_list */
+	uint64_t tx_packets_requeued;	/**< Number of Tx packets requeued */
+};
+
+/**
+ * nss_dp_hal_gmac_stats
+ *	The per-GMAC statistics structure.
+ */
+struct nss_dp_hal_gmac_stats {
+	struct nss_dp_hal_gmac_stats_rx rx_stats;
+					/**< GMAC Rx statistics */
+	struct nss_dp_hal_gmac_stats_tx tx_stats;
+					/**< GMAC Tx statistics */
+	uint64_t hw_errs[10];		/**< GMAC DMA error counters */
+};
+
+extern struct nss_dp_data_plane_ops nss_dp_gmac_ops;
+
+#endif /* __NSS_DP_ARCH_H__ */
diff --git a/qca-nss-dp/hal/soc_ops/ipq60xx/nss_ipq60xx.c b/qca-nss-dp/hal/soc_ops/ipq60xx/nss_ipq60xx.c
new file mode 100644
index 0000000..80906a4
--- /dev/null
+++ b/qca-nss-dp/hal/soc_ops/ipq60xx/nss_ipq60xx.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/of.h>
+#include <nss_dp_arch.h>
+#include "nss_dp_hal.h"
+
+/*
+ * nss_dp_hal_get_data_plane_ops()
+ *	Return the data plane ops for registered data plane.
+ */
+struct nss_dp_data_plane_ops *nss_dp_hal_get_data_plane_ops(void)
+{
+	return &nss_dp_edma_ops;
+}
+
+/*
+ * nss_dp_hal_init()
+ *	Initialize EDMA and set gmac ops.
+ */
+bool nss_dp_hal_init(void)
+{
+	/*
+	 * Bail out on not supported platform
+	 */
+	if (!of_machine_is_compatible("qcom,ipq6018")) {
+		return false;
+	}
+
+	if (edma_init()) {
+		return false;
+	}
+
+	nss_dp_hal_set_gmac_ops(&qcom_gmac_ops, GMAC_HAL_TYPE_QCOM);
+	nss_dp_hal_set_gmac_ops(&syn_gmac_ops, GMAC_HAL_TYPE_SYN_XGMAC);
+
+	return true;
+}
+
+/*
+ * nss_dp_hal_cleanup()
+ *	Cleanup EDMA and set gmac ops to NULL.
+ */
+void nss_dp_hal_cleanup(void)
+{
+	nss_dp_hal_set_gmac_ops(NULL, GMAC_HAL_TYPE_QCOM);
+	nss_dp_hal_set_gmac_ops(NULL, GMAC_HAL_TYPE_SYN_XGMAC);
+	edma_cleanup(false);
+}
diff --git a/qca-nss-dp/hal/soc_ops/ipq60xx/nss_ipq60xx.h b/qca-nss-dp/hal/soc_ops/ipq60xx/nss_ipq60xx.h
new file mode 100644
index 0000000..bb67ec2
--- /dev/null
+++ b/qca-nss-dp/hal/soc_ops/ipq60xx/nss_ipq60xx.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_ARCH_H__
+#define __NSS_DP_ARCH_H__
+
+#define NSS_DP_HAL_MAX_PORTS		5
+#define NSS_DP_HAL_CPU_NUM		4
+#define NSS_DP_HAL_START_IFNUM		1
+#define NSS_DP_PREHEADER_SIZE		32
+
+/*
+ * Number of TX/RX queue supported
+ */
+#define NSS_DP_QUEUE_NUM		4
+
+/*
+ * TX/RX NAPI budget
+ */
+#define NSS_DP_HAL_RX_NAPI_BUDGET	32
+#define NSS_DP_HAL_TX_NAPI_BUDGET	32
+
+/**
+ * nss_dp_hal_gmac_stats
+ *	The per-GMAC statistics structure.
+ */
+struct nss_dp_hal_gmac_stats {
+};
+
+extern int edma_init(void);
+extern void edma_cleanup(bool is_dp_override);
+extern struct nss_dp_data_plane_ops nss_dp_edma_ops;
+
+#endif /* __NSS_DP_ARCH_H__ */
diff --git a/qca-nss-dp/hal/soc_ops/ipq807x/nss_ipq807x.c b/qca-nss-dp/hal/soc_ops/ipq807x/nss_ipq807x.c
new file mode 100644
index 0000000..3a3e6b6
--- /dev/null
+++ b/qca-nss-dp/hal/soc_ops/ipq807x/nss_ipq807x.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/of.h>
+#include <nss_dp_arch.h>
+#include "nss_dp_hal.h"
+
+/*
+ * nss_dp_hal_get_data_plane_ops()
+ *	Return the data plane ops for registered data plane.
+ */
+struct nss_dp_data_plane_ops *nss_dp_hal_get_data_plane_ops(void)
+{
+	return &nss_dp_edma_ops;
+}
+
+/*
+ * nss_dp_hal_init()
+ *	Initialize EDMA and set gmac ops.
+ */
+bool nss_dp_hal_init(void)
+{
+	/*
+	 * Bail out on not supported platform
+	 */
+	if (!of_machine_is_compatible("qcom,ipq807x") &&
+			!of_machine_is_compatible("qcom,ipq8074")) {
+		return false;
+	}
+
+	if (edma_init()) {
+		return false;
+	}
+
+	nss_dp_hal_set_gmac_ops(&qcom_gmac_ops, GMAC_HAL_TYPE_QCOM);
+	nss_dp_hal_set_gmac_ops(&syn_gmac_ops, GMAC_HAL_TYPE_SYN_XGMAC);
+
+	return true;
+}
+
+/*
+ * nss_dp_hal_cleanup()
+ *	Cleanup EDMA and set gmac ops to NULL.
+ */
+void nss_dp_hal_cleanup(void)
+{
+	nss_dp_hal_set_gmac_ops(NULL, GMAC_HAL_TYPE_QCOM);
+	nss_dp_hal_set_gmac_ops(NULL, GMAC_HAL_TYPE_SYN_XGMAC);
+	edma_cleanup(false);
+}
diff --git a/qca-nss-dp/hal/soc_ops/ipq807x/nss_ipq807x.h b/qca-nss-dp/hal/soc_ops/ipq807x/nss_ipq807x.h
new file mode 100644
index 0000000..8eed489
--- /dev/null
+++ b/qca-nss-dp/hal/soc_ops/ipq807x/nss_ipq807x.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_ARCH_H__
+#define __NSS_DP_ARCH_H__
+
+#define NSS_DP_HAL_MAX_PORTS		6
+#define NSS_DP_HAL_CPU_NUM		4
+#define NSS_DP_HAL_START_IFNUM		1
+#define NSS_DP_PREHEADER_SIZE		32
+
+/*
+ * Number of TX/RX queue supported
+ */
+#define NSS_DP_QUEUE_NUM		4
+
+/*
+ * TX/RX NAPI budget
+ */
+#define NSS_DP_HAL_RX_NAPI_BUDGET	32
+#define NSS_DP_HAL_TX_NAPI_BUDGET	32
+
+/**
+ * nss_dp_hal_gmac_stats
+ *	The per-GMAC statistics structure.
+ */
+struct nss_dp_hal_gmac_stats {
+};
+
+extern int edma_init(void);
+extern void edma_cleanup(bool is_dp_override);
+extern struct nss_dp_data_plane_ops nss_dp_edma_ops;
+
+#endif /* __NSS_DP_ARCH_H__ */
diff --git a/qca-nss-dp/hal/soc_ops/ipq95xx/nss_ipq95xx.c b/qca-nss-dp/hal/soc_ops/ipq95xx/nss_ipq95xx.c
new file mode 100644
index 0000000..9192e00
--- /dev/null
+++ b/qca-nss-dp/hal/soc_ops/ipq95xx/nss_ipq95xx.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/of.h>
+#include <nss_dp_arch.h>
+#include "nss_dp_hal.h"
+
+/*
+ * nss_dp_hal_get_data_plane_ops()
+ *	Return the data plane ops for registered data plane.
+ */
+struct nss_dp_data_plane_ops *nss_dp_hal_get_data_plane_ops(void)
+{
+	return &nss_dp_edma_ops;
+}
+
+/*
+ * nss_dp_hal_init()
+ *	Initialize EDMA and set gmac ops.
+ */
+bool nss_dp_hal_init(void)
+{
+	/*
+	 * Bail out on not supported platform
+	 */
+	if (!of_machine_is_compatible("qcom,ipq9574")) {
+		return false;
+	}
+
+	if (edma_init()) {
+		return false;
+	}
+
+	nss_dp_hal_set_gmac_ops(&qcom_gmac_ops, GMAC_HAL_TYPE_QCOM);
+	nss_dp_hal_set_gmac_ops(&syn_gmac_ops, GMAC_HAL_TYPE_SYN_XGMAC);
+
+	return true;
+}
+
+/*
+ * nss_dp_hal_cleanup()
+ *	Cleanup EDMA and set gmac ops to NULL.
+ */
+void nss_dp_hal_cleanup(void)
+{
+	nss_dp_hal_set_gmac_ops(NULL, GMAC_HAL_TYPE_QCOM);
+	nss_dp_hal_set_gmac_ops(NULL, GMAC_HAL_TYPE_SYN_XGMAC);
+	edma_cleanup(false);
+}
diff --git a/qca-nss-dp/hal/soc_ops/ipq95xx/nss_ipq95xx.h b/qca-nss-dp/hal/soc_ops/ipq95xx/nss_ipq95xx.h
new file mode 100644
index 0000000..e431c9d
--- /dev/null
+++ b/qca-nss-dp/hal/soc_ops/ipq95xx/nss_ipq95xx.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_ARCH_H__
+#define __NSS_DP_ARCH_H__
+
+#define NSS_DP_HAL_MAX_PORTS		6
+#define NSS_DP_HAL_CPU_NUM		4
+#define NSS_DP_HAL_START_IFNUM		1
+
+/*
+ * Number of TX/RX queue supported
+ */
+#define NSS_DP_QUEUE_NUM		4
+
+/*
+ * TX/RX NAPI budget
+ */
+#define NSS_DP_HAL_RX_NAPI_BUDGET	32
+#define NSS_DP_HAL_TX_NAPI_BUDGET	32
+
+/**
+ * nss_dp_hal_gmac_stats
+ *	The per-GMAC statistics structure.
+ */
+struct nss_dp_hal_gmac_stats {
+	uint64_t rx_packets;		/**< Number of RX packets */
+	uint64_t rx_bytes;		/**< Number of RX bytes */
+	uint64_t rx_dropped;		/**< Number of RX dropped packets */
+	uint64_t rx_fraglist_packets;	/**< Number of RX fraglist packets */
+	uint64_t rx_nr_frag_packets;	/**< Number of RX nr fragment packets */
+	uint64_t rx_nr_frag_headroom_err;
+			/**< Number of RX nr fragment packets with headroom error */
+	uint64_t tx_packets;		/**< Number of TX packets */
+	uint64_t tx_bytes;		/**< Number of TX bytes */
+	uint64_t tx_dropped;		/**< Number of TX dropped packets */
+	uint64_t tx_nr_frag_packets;	/**< Number of TX nr fragment packets */
+	uint64_t tx_fraglist_packets;	/**< Number of TX fraglist packets */
+	uint64_t tx_fraglist_with_nr_frags_packets;	/**< Number of TX fraglist packets with nr fragments */
+	uint64_t tx_tso_packets;	/**< Number of TX TCP segmentation offload packets */
+};
+
+extern int edma_init(void);
+extern void edma_cleanup(bool is_dp_override);
+extern struct nss_dp_data_plane_ops nss_dp_edma_ops;
+
+#endif /* __NSS_DP_ARCH_H__ */
diff --git a/qca-nss-dp/include/nss_dp_dev.h b/qca-nss-dp/include/nss_dp_dev.h
new file mode 100644
index 0000000..2669639
--- /dev/null
+++ b/qca-nss-dp/include/nss_dp_dev.h
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_DEV_H__
+#define __NSS_DP_DEV_H__
+
+#include <linux/etherdevice.h>
+#include <linux/netdevice.h>
+#include <linux/platform_device.h>
+#include <linux/switch.h>
+#include <linux/version.h>
+
+#include "nss_dp_api_if.h"
+#include "nss_dp_hal_if.h"
+#include "nss_dp_hal_info.h"
+
+#define NSS_DP_ACL_DEV_ID 0
+
+/*
+ * Rx buffer allocation size as per memory profile
+ */
+#if (defined(NSS_DP_MEM_PROFILE_LOW) || defined(NSS_DP_MEM_PROFILE_MEDIUM)) && !defined(__LP64__)
+#define NSS_DP_RX_BUFFER_SIZE		1856
+#else
+#define NSS_DP_RX_BUFFER_SIZE		1984
+#endif
+
+#if defined(NSS_DP_IPQ95XX)
+/*
+ * Rx rings flow control threshold values
+ *
+ * The Rx flow control has the X-OFF and the X-ON threshold values.
+ * Whenever the free Rx ring descriptor count falls below the X-OFF value, the
+ * ring level flow control will kick in and the mapped PPE queues will be backpressured.
+ * Similarly, whenever the free Rx ring descriptor count crosses the X-ON value,
+ * the ring level flow control will be disabled.
+ */
+#define NSS_DP_RX_FC_XOFF_DEF		16
+#define NSS_DP_RX_FC_XON_DEF		32
+
+/*
+ * Rx ring's mapped AC FC threshold value.
+ *
+ * This value is picked by running four uni-UDPv4 traffic which are mapped
+ * to 4 different rings (and hence processed by 4 different cores) and then
+ * increase one flow's rate to more than what the core can process and observe
+ * whether this congestion in one flow is influencing other flows or not.
+ * Below is the maximum threshold value which is invoking the congestion's queue
+ * tail drop and hence not trigerring the Rx port's back-pressure.
+ */
+#define NSS_DP_RX_AC_FC_THRES_DEF	0x104
+
+/*
+ * Tx/Rx Mitigation values
+ *
+ * Packet count indicates number of packets received or transmitted after which
+ * the interrupt is triggered. Stale timer (in microseconds) indicates time after
+ * which interrupt is triggered in case number of packets have not been accumulated.
+ *
+ * These values are picked by running the single large packet uni-UDPv4 traffic
+ * at moderate speed and observing the CPU utilization for the flow's processing
+ * core.
+ * Below values gave the best combination of the idle CPU percentage left for the
+ * above mentioned scenario and the minimum impact of the single and multi core
+ * small packet's PPS numbers.
+ */
+#define NSS_DP_TX_MITIGATION_TIMER_DEF		250
+#define NSS_DP_TX_MITIGATION_PKT_CNT_DEF	16
+#define NSS_DP_RX_MITIGATION_TIMER_DEF		250
+#define NSS_DP_RX_MITIGATION_PKT_CNT_DEF	16
+#endif
+
+struct nss_dp_global_ctx;
+
+/*
+ * nss data plane device structure
+ */
+struct nss_dp_dev {
+	uint32_t macid;			/* Sequence# of Mac on the platform */
+	uint32_t vsi;			/* vsi number */
+	unsigned long flags;		/* Status flags */
+	unsigned long drv_flags;	/* Driver specific feature flags */
+
+	/* Phy related stuff */
+	struct phy_device *phydev;	/* Phy device */
+	struct mii_bus *miibus;		/* MII bus */
+	uint32_t phy_mii_type;		/* RGMII/SGMII/QSGMII */
+	uint32_t phy_mdio_addr;		/* Mdio address */
+	bool link_poll;			/* Link polling enable? */
+	uint32_t forced_speed;		/* Forced speed? */
+	uint32_t forced_duplex;		/* Forced duplex? */
+	uint32_t link_state;		/* Current link state */
+	uint32_t pause;			/* Current flow control settings */
+
+	struct net_device *netdev;
+	struct platform_device *pdev;
+	struct napi_struct napi;
+
+	struct nss_dp_data_plane_ctx *dpc;
+					/* context when NSS owns GMACs */
+	struct nss_dp_data_plane_ops *data_plane_ops;
+					/* ops for each data plane */
+	struct nss_dp_global_ctx *ctx;	/* Global NSS DP context */
+	struct nss_gmac_hal_dev *gmac_hal_ctx;
+					/* context of gmac hal */
+	struct nss_gmac_hal_ops *gmac_hal_ops;
+					/* GMAC HAL OPS */
+	struct nss_dp_hal_info dp_info;
+					/* SoC specific data plane information */
+
+	/* switchdev related attributes */
+#ifdef NSS_DP_PPE_SWITCHDEV
+	u8 stp_state;			/* STP state of this physical port */
+	unsigned long brport_flags;	/* bridge port flags */
+#endif
+	uint32_t rx_page_mode;		/* page mode for Rx processing */
+	uint32_t rx_jumbo_mru;		/* Jumbo mru value for Rx processing */
+};
+
+/*
+ * nss data plane global context
+ */
+struct nss_dp_global_ctx {
+	struct nss_dp_dev *nss_dp[NSS_DP_HAL_MAX_PORTS];
+	struct nss_gmac_hal_ops *gmac_hal_ops[GMAC_HAL_TYPE_MAX];
+					/* GMAC HAL OPS */
+	bool common_init_done;		/* Flag to hold common init state */
+	uint8_t slowproto_acl_bm;	/* Port bitmap to allow slow protocol packets */
+	uint32_t rx_buf_size;		/* Buffer size to allocate */
+	uint32_t jumbo_mru;			/* Jumbo mru value for Rx processing */
+	bool overwrite_mode;		/* Overwrite mode for Rx processing */
+	bool page_mode;				/* Page mode for Rx processing */
+	bool tx_requeue_stop;		/* Disable queue stop for Tx processing */
+};
+
+/* Global data */
+extern struct nss_dp_global_ctx dp_global_ctx;
+extern struct nss_dp_data_plane_ctx dp_global_data_plane_ctx[NSS_DP_HAL_MAX_PORTS];
+extern int nss_dp_rx_napi_budget;
+extern int nss_dp_tx_napi_budget;
+
+#if defined(NSS_DP_IPQ95XX)
+extern int nss_dp_rx_fc_xon;
+extern int nss_dp_rx_fc_xoff;
+extern int nss_dp_rx_ac_fc_threshold;
+extern int nss_dp_tx_mitigation_timer;
+extern int nss_dp_tx_mitigation_pkt_cnt;
+extern int nss_dp_rx_mitigation_timer;
+extern int nss_dp_rx_mitigation_pkt_cnt;
+#endif
+
+/*
+ * nss data plane link state
+ */
+enum nss_dp_link_state {
+	__NSS_DP_LINK_UP,	/* Indicate link is UP */
+	__NSS_DP_LINK_DOWN	/* Indicate link is down */
+};
+
+/*
+ * nss data plane status
+ */
+enum nss_dp_state {
+	__NSS_DP_UP,		/* set to indicate the interface is UP	*/
+	__NSS_DP_RXCSUM,	/* Rx checksum enabled			*/
+	__NSS_DP_AUTONEG,	/* Autonegotiation Enabled		*/
+	__NSS_DP_LINKPOLL,	/* Poll link status			*/
+};
+
+/*
+ * nss data plane private flags
+ */
+enum nss_dp_priv_flags {
+	__NSS_DP_PRIV_FLAG_INIT_DONE,
+	__NSS_DP_PRIV_FLAG_IRQ_REQUESTED,
+	__NSS_DP_PRIV_FLAG_INIT_OVERRIDE,
+	__NSS_DP_PRIV_FLAG_MAX,
+};
+#define NSS_DP_PRIV_FLAG(x)	(1 << __NSS_DP_PRIV_FLAG_ ## x)
+
+/*
+ * nss_dp_set_ethtool_ops()
+ */
+void nss_dp_set_ethtool_ops(struct net_device *netdev);
+
+/*
+ * nss data plane switchdev helpers
+ */
+#ifdef NSS_DP_PPE_SWITCHDEV
+void nss_dp_switchdev_setup(struct net_device *dev);
+bool nss_dp_is_phy_dev(struct net_device *dev);
+#endif
+
+#endif	/* __NSS_DP_DEV_H__ */
diff --git a/qca-nss-dp/nss_dp_attach.c b/qca-nss-dp/nss_dp_attach.c
new file mode 100644
index 0000000..c667b26
--- /dev/null
+++ b/qca-nss-dp/nss_dp_attach.c
@@ -0,0 +1,203 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2019-2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include "nss_dp_hal.h"
+
+/*
+ * nss_dp_reset_netdev_features()
+ *	Resets the netdev features
+ */
+static inline void nss_dp_reset_netdev_features(struct net_device *netdev)
+{
+	netdev->features = 0;
+	netdev->hw_features = 0;
+	netdev->vlan_features = 0;
+	netdev->wanted_features = 0;
+}
+
+/*
+ * nss_dp_receive()
+ *	Called by overlay drivers to deliver packets to nss-dp
+ */
+void nss_dp_receive(struct net_device *netdev, struct sk_buff *skb,
+					       struct napi_struct *napi)
+{
+	struct nss_dp_dev *dp_dev = netdev_priv(netdev);
+
+	skb->dev = netdev;
+	skb->protocol = eth_type_trans(skb, netdev);
+	netdev_dbg(netdev, "Rx on port%d, packet len %d, CSUM %d\n",
+			dp_dev->macid, skb->len, skb->ip_summed);
+
+#ifdef NSS_DP_PPE_SWITCHDEV
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+	skb->offload_fwd_mark = netdev->offload_fwd_mark;
+#else
+	/*
+	 * TODO: Implement ndo_get_devlink_port()
+	 */
+	skb->offload_fwd_mark = 0;
+#endif
+#endif
+
+	napi_gro_receive(napi, skb);
+}
+EXPORT_SYMBOL(nss_dp_receive);
+
+/*
+ * nss_dp_is_in_open_state()
+ *	Return if a data plane is opened or not
+ */
+bool nss_dp_is_in_open_state(struct net_device *netdev)
+{
+	struct nss_dp_dev *dp_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	if (test_bit(__NSS_DP_UP, &dp_dev->flags))
+		return true;
+	return false;
+}
+EXPORT_SYMBOL(nss_dp_is_in_open_state);
+
+/*
+ * nss_dp_override_data_plane()
+ *	API to allow overlay drivers to override the data plane
+ */
+int nss_dp_override_data_plane(struct net_device *netdev,
+				struct nss_dp_data_plane_ops *dp_ops,
+				struct nss_dp_data_plane_ctx *dpc)
+{
+	struct nss_dp_dev *dp_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	if (!dp_ops->open || !dp_ops->close || !dp_ops->link_state
+		|| !dp_ops->mac_addr || !dp_ops->change_mtu || !dp_ops->xmit
+		|| !dp_ops->set_features || !dp_ops->pause_on_off || !dp_ops->deinit) {
+		netdev_dbg(netdev, "All the op functions must be present, reject this registeration\n");
+		return NSS_DP_FAILURE;
+	}
+
+	/*
+	 * If this data plane is up, close the netdev to force TX/RX stop, and
+	 * also reset the features
+	 */
+	if (test_bit(__NSS_DP_UP, &dp_dev->flags)) {
+		netdev->netdev_ops->ndo_stop(netdev);
+		nss_dp_reset_netdev_features(netdev);
+	}
+
+	/*
+	 * Free up the resources used by the data plane
+	 */
+	if (dp_dev->drv_flags & NSS_DP_PRIV_FLAG(INIT_DONE)) {
+		if (dp_dev->data_plane_ops->deinit(dpc)) {
+			netdev_dbg(netdev, "Data plane de-init failed\n");
+			return -ENOMEM;
+		}
+
+		dp_dev->drv_flags &= ~NSS_DP_PRIV_FLAG(INIT_DONE);
+	}
+
+	/*
+	 * Override the data_plane_ctx, data_plane_ops
+	 */
+	dp_dev->drv_flags |= NSS_DP_PRIV_FLAG(INIT_OVERRIDE);
+	dp_dev->dpc = dpc;
+	dp_dev->data_plane_ops = dp_ops;
+
+	/*
+	 * Initialize the updated data plane
+	 */
+	if (dp_dev->data_plane_ops->init(dpc)) {
+		netdev_dbg(netdev, "Data Plane init failed\n");
+		return -EFAULT;
+	}
+	dp_dev->drv_flags |= NSS_DP_PRIV_FLAG(INIT_DONE);
+
+	return NSS_DP_SUCCESS;
+}
+EXPORT_SYMBOL(nss_dp_override_data_plane);
+
+/*
+ * nss_dp_start_data_plane()
+ *	Data plane to inform netdev it is ready to start
+ */
+void nss_dp_start_data_plane(struct net_device *netdev,
+			     struct nss_dp_data_plane_ctx *dpc)
+{
+	struct nss_dp_dev *dp_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	if (test_bit(__NSS_DP_UP, &dp_dev->flags)) {
+		netdev_dbg(netdev, "This netdev already up, something is wrong\n");
+		return;
+	}
+
+	if (dp_dev->dpc != dpc) {
+		netdev_dbg(netdev, "Cookie %px does not match, reject\n", dpc);
+		return;
+	}
+
+	netdev->netdev_ops->ndo_open(dp_dev->netdev);
+}
+EXPORT_SYMBOL(nss_dp_start_data_plane);
+
+/*
+ * nss_dp_restore_data_plane()
+ *	Called by overlay drivers to detach itself from nss-dp
+ */
+void nss_dp_restore_data_plane(struct net_device *netdev)
+{
+	struct nss_dp_dev *dp_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	/*
+	 * If this data plane is up, close the netdev to force TX/RX stop, and
+	 * also reset the features
+	 */
+	if (test_bit(__NSS_DP_UP, &dp_dev->flags)) {
+		netdev->netdev_ops->ndo_stop(netdev);
+		nss_dp_reset_netdev_features(netdev);
+	}
+
+	dp_dev->data_plane_ops = nss_dp_hal_get_data_plane_ops();
+	dp_dev->dpc = &dp_global_data_plane_ctx[dp_dev->macid - NSS_DP_START_IFNUM];
+
+	/*
+	 * TODO: Re-initialize EDMA dataplane
+	 */
+}
+EXPORT_SYMBOL(nss_dp_restore_data_plane);
+
+/*
+ * nss_dp_get_netdev_by_nss_if_num()
+ *	return the net device of the corrsponding id if exist
+ */
+struct net_device *nss_dp_get_netdev_by_nss_if_num(int if_num)
+{
+	struct nss_dp_dev *dp_dev;
+
+	if ((if_num > NSS_DP_HAL_MAX_PORTS) || (if_num < NSS_DP_START_IFNUM)) {
+		pr_err("Invalid if_num %d\n", if_num);
+		return NULL;
+	}
+
+	dp_dev = dp_global_ctx.nss_dp[if_num - NSS_DP_START_IFNUM];
+	if (!dp_dev)
+		return NULL;
+	return dp_dev->netdev;
+}
+EXPORT_SYMBOL(nss_dp_get_netdev_by_nss_if_num);
diff --git a/qca-nss-dp/nss_dp_ethtools.c b/qca-nss-dp/nss_dp_ethtools.c
new file mode 100644
index 0000000..a614641
--- /dev/null
+++ b/qca-nss-dp/nss_dp_ethtools.c
@@ -0,0 +1,391 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/ethtool.h>
+#include <linux/phy.h>
+#include <linux/mii.h>
+#include "nss_dp_dev.h"
+#include "fal/fal_port_ctrl.h"
+
+/*
+ * nss_dp_get_ethtool_stats()
+ */
+static void nss_dp_get_ethtool_stats(struct net_device *netdev,
+				struct ethtool_stats *stats, uint64_t *data)
+{
+	struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+	struct nss_dp_gmac_stats dp_stats;
+
+	/*
+	 * Get the DMA Driver statistics from the data plane if available
+	 */
+	memset(&dp_stats, 0, sizeof(struct nss_dp_gmac_stats));
+	if (dp_priv->data_plane_ops->get_stats) {
+		dp_priv->data_plane_ops->get_stats(dp_priv->dpc, &dp_stats);
+	}
+
+	/*
+	 * Get and print the GMAC MIB statistics along with the
+	 * DMA driver statistics.
+	 */
+	dp_priv->gmac_hal_ops->getethtoolstats(dp_priv->gmac_hal_ctx, data, &dp_stats);
+}
+
+/*
+ * nss_dp_get_strset_count()
+ */
+static int32_t nss_dp_get_strset_count(struct net_device *netdev, int32_t sset)
+{
+	struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	return dp_priv->gmac_hal_ops->getssetcount(dp_priv->gmac_hal_ctx, sset);
+}
+
+/*
+ * nss_dp_get_strings()
+ */
+static void nss_dp_get_strings(struct net_device *netdev, uint32_t stringset,
+			uint8_t *data)
+{
+	struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	dp_priv->gmac_hal_ops->getstrings(dp_priv->gmac_hal_ctx, stringset,
+					  data);
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+/*
+ * nss_dp_get_settings()
+ */
+static int32_t nss_dp_get_settings(struct net_device *netdev,
+				   struct ethtool_cmd *cmd)
+{
+	struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	/*
+	 * If there is a PHY attached, get the status from Kernel helper
+	 */
+	if (dp_priv->phydev)
+		return phy_ethtool_gset(dp_priv->phydev, cmd);
+
+	return -EIO;
+}
+
+/*
+ * nss_dp_set_settings()
+ */
+static int32_t nss_dp_set_settings(struct net_device *netdev,
+				  struct ethtool_cmd *cmd)
+{
+	struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	if (!dp_priv->phydev)
+		return -EIO;
+
+	return phy_ethtool_sset(dp_priv->phydev, cmd);
+}
+#endif
+
+/*
+ * nss_dp_get_pauseparam()
+ */
+static void nss_dp_get_pauseparam(struct net_device *netdev,
+				     struct ethtool_pauseparam *pause)
+{
+	struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	pause->rx_pause = dp_priv->pause & FLOW_CTRL_RX ? 1 : 0;
+	pause->tx_pause = dp_priv->pause & FLOW_CTRL_TX ? 1 : 0;
+	pause->autoneg = AUTONEG_ENABLE;
+}
+
+/*
+ * nss_dp_set_pauseparam()
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+static int32_t nss_dp_set_pauseparam(struct net_device *netdev,
+				     struct ethtool_pauseparam *pause)
+{
+         struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+
+         /* set flow control settings */
+         dp_priv->pause = 0;
+         if (pause->rx_pause)
+                 dp_priv->pause |= FLOW_CTRL_RX;
+
+         if (pause->tx_pause)
+                 dp_priv->pause |= FLOW_CTRL_TX;
+
+         if (!dp_priv->phydev)
+                 return 0;
+
+         /* Update flow control advertisment */
+         dp_priv->phydev->advertising &=
+                                 ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
+
+         if (pause->rx_pause)
+                 dp_priv->phydev->advertising |=
+                                 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
+
+         if (pause->tx_pause)
+                 dp_priv->phydev->advertising |= ADVERTISED_Asym_Pause;
+
+         genphy_config_aneg(dp_priv->phydev);
+
+         return 0;
+}
+#else
+static int32_t nss_dp_set_pauseparam(struct net_device *netdev,
+				     struct ethtool_pauseparam *pause)
+{
+	struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising) = { 0, };
+
+	/* set flow control settings */
+	dp_priv->pause = 0;
+	if (pause->rx_pause)
+		dp_priv->pause |= FLOW_CTRL_RX;
+
+	if (pause->tx_pause)
+		dp_priv->pause |= FLOW_CTRL_TX;
+
+	if (!dp_priv->phydev)
+		return 0;
+
+	/* Update flow control advertisment */
+	linkmode_copy(advertising, dp_priv->phydev->advertising);
+
+	linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertising);
+	linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertising);
+
+	if (pause->rx_pause) {
+		linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertising);
+		linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertising);
+	}
+
+	if (pause->tx_pause)
+		linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertising);
+
+	linkmode_copy(dp_priv->phydev->advertising, advertising);
+	genphy_config_aneg(dp_priv->phydev);
+
+	return 0;
+}
+#endif
+
+/*
+ * nss_dp_fal_to_ethtool_linkmode_xlate()
+ *	Translate linkmode from FAL type to ethtool type.
+ */
+static inline void nss_dp_fal_to_ethtool_linkmode_xlate(uint32_t *xlate_to, uint32_t *xlate_from)
+{
+	uint32_t pos;
+
+	while (*xlate_from) {
+		pos = ffs(*xlate_from);
+		switch (1 << (pos - 1)) {
+		case FAL_PHY_EEE_10BASE_T:
+			*xlate_to |= SUPPORTED_10baseT_Full;
+			break;
+
+		case FAL_PHY_EEE_100BASE_T:
+			*xlate_to |= SUPPORTED_100baseT_Full;
+			break;
+
+		case FAL_PHY_EEE_1000BASE_T:
+			*xlate_to |= SUPPORTED_1000baseT_Full;
+			break;
+
+		case FAL_PHY_EEE_2500BASE_T:
+			*xlate_to |= SUPPORTED_2500baseX_Full;
+			break;
+
+		case FAL_PHY_EEE_5000BASE_T:
+			/*
+			 * Ethtool does not support enumeration for 5G.
+			 */
+			break;
+
+		case FAL_PHY_EEE_10000BASE_T:
+			*xlate_to |= SUPPORTED_10000baseT_Full;
+			break;
+		}
+
+		*xlate_from &= (~(1 << (pos - 1)));
+	}
+}
+
+/*
+ * nss_dp_get_eee()
+ *	Get EEE settings.
+ */
+static int32_t nss_dp_get_eee(struct net_device *netdev, struct ethtool_eee *eee)
+{
+	struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+	fal_port_eee_cfg_t port_eee_cfg;
+	uint32_t port_id;
+	sw_error_t ret;
+
+	memset(&port_eee_cfg, 0, sizeof(fal_port_eee_cfg_t));
+	port_id = dp_priv->macid;
+	ret = fal_port_interface_eee_cfg_get(NSS_DP_ACL_DEV_ID, port_id, &port_eee_cfg);
+	if (ret != SW_OK) {
+		netdev_dbg(netdev, "Could not fetch EEE settings err = %d\n", ret);
+		return -EIO;
+	}
+
+	/*
+	 * Translate the FAL linkmode types to ethtool linkmode types.
+	 */
+	nss_dp_fal_to_ethtool_linkmode_xlate(&eee->supported, &port_eee_cfg.capability);
+	nss_dp_fal_to_ethtool_linkmode_xlate(&eee->advertised, &port_eee_cfg.advertisement);
+	nss_dp_fal_to_ethtool_linkmode_xlate(&eee->lp_advertised, &port_eee_cfg.link_partner_advertisement);
+	eee->eee_enabled = port_eee_cfg.enable;
+	eee->eee_active = port_eee_cfg.eee_status;
+	eee->tx_lpi_enabled = port_eee_cfg.lpi_tx_enable;
+	eee->tx_lpi_timer = port_eee_cfg.lpi_sleep_timer;
+
+	return 0;
+}
+
+/*
+ * nss_dp_set_eee()
+ *	Set EEE settings.
+ */
+static int32_t nss_dp_set_eee(struct net_device *netdev, struct ethtool_eee *eee)
+{
+	struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+	fal_port_eee_cfg_t port_eee_cfg, port_eee_cur_cfg;
+	uint32_t port_id, pos;
+	sw_error_t ret;
+
+	memset(&port_eee_cfg, 0, sizeof(fal_port_eee_cfg_t));
+	memset(&port_eee_cur_cfg, 0, sizeof(fal_port_eee_cfg_t));
+	port_id = dp_priv->macid;
+
+	/*
+	 * Get current EEE configuration.
+	 */
+	ret = fal_port_interface_eee_cfg_get(NSS_DP_ACL_DEV_ID, port_id, &port_eee_cur_cfg);
+	if (ret != SW_OK) {
+		netdev_dbg(netdev, "Could not fetch EEE settings err = %d\n", ret);
+		return -EIO;
+	}
+
+	port_eee_cfg.enable = eee->eee_enabled;
+
+	/*
+	 * Translate the ethtool speed types to FAL speed types.
+	 */
+	while (eee->advertised) {
+		pos = ffs(eee->advertised);
+		switch (1 << (pos - 1)) {
+		case ADVERTISED_10baseT_Full:
+			if (port_eee_cur_cfg.capability & FAL_PHY_EEE_10BASE_T) {
+				port_eee_cfg.advertisement |= FAL_PHY_EEE_10BASE_T;
+				break;
+			}
+
+			netdev_dbg(netdev, "Advertised value 10baseT_Full is not supported\n");
+			return -EIO;
+
+		case ADVERTISED_100baseT_Full:
+			if (port_eee_cur_cfg.capability & FAL_PHY_EEE_100BASE_T) {
+				port_eee_cfg.advertisement |= FAL_PHY_EEE_100BASE_T;
+				break;
+			}
+
+			netdev_dbg(netdev, "Advertised value 100baseT_Full is not supported\n");
+			return -EIO;
+
+		case ADVERTISED_1000baseT_Full:
+			if (port_eee_cur_cfg.capability & FAL_PHY_EEE_1000BASE_T) {
+				port_eee_cfg.advertisement |= FAL_PHY_EEE_1000BASE_T;
+				break;
+			}
+
+			netdev_dbg(netdev, "Advertised value 1000baseT_Full is not supported\n");
+			return -EIO;
+
+		case ADVERTISED_2500baseX_Full:
+			if (port_eee_cur_cfg.capability & FAL_PHY_EEE_2500BASE_T) {
+				port_eee_cfg.advertisement |= FAL_PHY_EEE_2500BASE_T;
+				break;
+			}
+
+			netdev_dbg(netdev, "Advertised value 2500baseX_Full is not supported\n");
+			return -EIO;
+
+		case ADVERTISED_10000baseT_Full:
+			if (port_eee_cur_cfg.capability & FAL_PHY_EEE_10000BASE_T) {
+				port_eee_cfg.advertisement |= FAL_PHY_EEE_10000BASE_T;
+				break;
+			}
+
+			netdev_dbg(netdev, "Advertised value 10000baseT_Full is not supported\n");
+			return -EIO;
+
+		default:
+			netdev_dbg(netdev, "Advertised value is not supported\n");
+			return -EIO;
+		}
+
+		eee->advertised &= (~(1 << (pos - 1)));
+	}
+
+	port_eee_cfg.lpi_tx_enable = eee->tx_lpi_enabled;
+	port_eee_cfg.lpi_sleep_timer = eee->tx_lpi_timer;
+	ret = fal_port_interface_eee_cfg_set(NSS_DP_ACL_DEV_ID, port_id, &port_eee_cfg);
+	if (ret != SW_OK) {
+		netdev_dbg(netdev, "Could not configure EEE err = %d\n", ret);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/*
+ * Ethtool operations
+ */
+struct ethtool_ops nss_dp_ethtool_ops = {
+	.get_strings = &nss_dp_get_strings,
+	.get_sset_count = &nss_dp_get_strset_count,
+	.get_ethtool_stats = &nss_dp_get_ethtool_stats,
+	.get_link = &ethtool_op_get_link,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+	.get_settings = &nss_dp_get_settings,
+	.set_settings = &nss_dp_set_settings,
+#else
+	.get_link_ksettings = phy_ethtool_get_link_ksettings,
+	.set_link_ksettings = phy_ethtool_set_link_ksettings,
+#endif
+	.get_pauseparam = &nss_dp_get_pauseparam,
+	.set_pauseparam = &nss_dp_set_pauseparam,
+	.get_eee = &nss_dp_get_eee,
+	.set_eee = &nss_dp_set_eee,
+};
+
+/*
+ * nss_dp_set_ethtool_ops()
+ *	Set ethtool operations
+ */
+void nss_dp_set_ethtool_ops(struct net_device *netdev)
+{
+	netdev->ethtool_ops = &nss_dp_ethtool_ops;
+}
diff --git a/qca-nss-dp/nss_dp_main.c b/qca-nss-dp/nss_dp_main.c
new file mode 100644
index 0000000..f728c93
--- /dev/null
+++ b/qca-nss-dp/nss_dp_main.c
@@ -0,0 +1,1067 @@
+/*
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/of_mdio.h>
+#include <linux/phy.h>
+#if defined(NSS_DP_PPE_SUPPORT)
+#include <fal/fal_vsi.h>
+#include <ref/ref_vsi.h>
+#endif
+#include <net/switchdev.h>
+
+#include "nss_dp_hal.h"
+
+/*
+ * Number of TX/RX queue supported
+ */
+#define NSS_DP_NETDEV_TX_QUEUE_NUM NSS_DP_QUEUE_NUM
+#define NSS_DP_NETDEV_RX_QUEUE_NUM NSS_DP_QUEUE_NUM
+
+/* ipq40xx_mdio_data */
+struct ipq40xx_mdio_data {
+	struct mii_bus *mii_bus;
+	void __iomem *membase;
+	int phy_irq[PHY_MAX_ADDR];
+};
+
+/* Global data */
+struct nss_dp_global_ctx dp_global_ctx;
+struct nss_dp_data_plane_ctx dp_global_data_plane_ctx[NSS_DP_HAL_MAX_PORTS];
+
+/* Module params */
+static int page_mode;
+module_param(page_mode, int, 0);
+MODULE_PARM_DESC(page_mode, "enable page mode");
+
+static int overwrite_mode;
+module_param(overwrite_mode, int, 0);
+MODULE_PARM_DESC(overwrite_mode, "overwrite default page_mode setting");
+
+int jumbo_mru;
+module_param(jumbo_mru, int, 0);
+MODULE_PARM_DESC(jumbo_mru, "jumbo mode");
+
+int tx_requeue_stop;
+module_param(tx_requeue_stop, int, 0);
+MODULE_PARM_DESC(tx_requeue_stop, "disable tx requeue function");
+
+int nss_dp_rx_napi_budget = NSS_DP_HAL_RX_NAPI_BUDGET;
+module_param(nss_dp_rx_napi_budget, int, S_IRUGO);
+MODULE_PARM_DESC(nss_dp_rx_napi_budget, "Rx NAPI budget");
+
+int nss_dp_tx_napi_budget = NSS_DP_HAL_TX_NAPI_BUDGET;
+module_param(nss_dp_tx_napi_budget, int, S_IRUGO);
+MODULE_PARM_DESC(nss_dp_tx_napi_budget, "Tx NAPI budget");
+
+#if defined(NSS_DP_IPQ95XX)
+int nss_dp_rx_fc_xoff = NSS_DP_RX_FC_XOFF_DEF;
+module_param(nss_dp_rx_fc_xoff, int, S_IRUGO);
+MODULE_PARM_DESC(nss_dp_rx_fc_xoff, "Rx ring's flow control XOFF threshold value");
+
+int nss_dp_rx_fc_xon = NSS_DP_RX_FC_XON_DEF;
+module_param(nss_dp_rx_fc_xon, int, S_IRUGO);
+MODULE_PARM_DESC(nss_dp_rx_fc_xon, "Rx ring's flow control XON threshold value");
+
+int nss_dp_rx_ac_fc_threshold = NSS_DP_RX_AC_FC_THRES_DEF;
+module_param(nss_dp_rx_ac_fc_threshold, int, S_IRUGO);
+MODULE_PARM_DESC(nss_dp_rx_ac_fc_threshold, "Rx ring's mapped PPE queue's FC threshold value");
+
+int nss_dp_tx_mitigation_timer = NSS_DP_TX_MITIGATION_TIMER_DEF;
+module_param(nss_dp_tx_mitigation_timer, int, S_IRUGO);
+MODULE_PARM_DESC(nss_dp_tx_mitigation_timer, "Tx mitigation timer value in microseconds");
+
+int nss_dp_tx_mitigation_pkt_cnt = NSS_DP_TX_MITIGATION_PKT_CNT_DEF;
+module_param(nss_dp_tx_mitigation_pkt_cnt, int, S_IRUGO);
+MODULE_PARM_DESC(nss_dp_tx_mitigation_pkt_cnt, "Tx mitigation packet count value");
+
+int nss_dp_rx_mitigation_timer = NSS_DP_RX_MITIGATION_TIMER_DEF;
+module_param(nss_dp_rx_mitigation_timer, int, S_IRUGO);
+MODULE_PARM_DESC(nss_dp_rx_mitigation_timer, "Rx mitigation timer value in microseconds");
+
+int nss_dp_rx_mitigation_pkt_cnt = NSS_DP_RX_MITIGATION_PKT_CNT_DEF;
+module_param(nss_dp_rx_mitigation_pkt_cnt, int, S_IRUGO);
+MODULE_PARM_DESC(nss_dp_rx_mitigation_pkt_cnt, "Rx mitigation packet count value");
+#endif
+
+/*
+ * nss_dp_do_ioctl()
+ */
+static int32_t nss_dp_do_ioctl(struct net_device *netdev, struct ifreq *ifr,
+						   int32_t cmd)
+{
+	int ret = -EINVAL;
+	struct nss_dp_dev *dp_priv;
+
+	if (!netdev || !ifr)
+		return ret;
+
+	dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	if (dp_priv->phydev)
+		return phy_mii_ioctl(dp_priv->phydev, ifr, cmd);
+
+	return ret;
+}
+
+/*
+ * nss_dp_change_mtu()
+ */
+static int32_t nss_dp_change_mtu(struct net_device *netdev, int32_t newmtu)
+{
+	int ret = -EINVAL;
+	struct nss_dp_dev *dp_priv;
+
+	if (!netdev)
+		return ret;
+
+	dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	/*
+	 * Check if data plane init has been done
+	 */
+	if (!(dp_priv->drv_flags & NSS_DP_PRIV_FLAG(INIT_DONE))) {
+		return ret;
+	}
+
+	/*
+	 * Configure the new MTU value to underlying HW.
+	 */
+	if (dp_priv->gmac_hal_ops->setmaxframe(dp_priv->gmac_hal_ctx, newmtu)) {
+		netdev_dbg(netdev, "GMAC MTU change failed: %d\n", newmtu);
+		return ret;
+	}
+
+	/*
+	 * Let the underlying data plane decide if the newmtu is applicable.
+	 */
+	if (dp_priv->data_plane_ops->change_mtu(dp_priv->dpc, newmtu)) {
+		netdev_dbg(netdev, "Data plane change mtu failed: %d\n",
+								newmtu);
+		dp_priv->gmac_hal_ops->setmaxframe(dp_priv->gmac_hal_ctx,
+								netdev->mtu);
+		return ret;
+	}
+
+	netdev->mtu = newmtu;
+	return 0;
+}
+
+/*
+ * nss_dp_set_mac_address()
+ */
+static int32_t nss_dp_set_mac_address(struct net_device *netdev, void *macaddr)
+{
+	struct nss_dp_dev *dp_priv;
+	struct sockaddr *addr = (struct sockaddr *)macaddr;
+	int ret = 0;
+
+	if (!netdev)
+		return -EINVAL;
+
+	dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	/*
+	 * Check if data plane init has been done
+	 */
+	if (!(dp_priv->drv_flags & NSS_DP_PRIV_FLAG(INIT_DONE))) {
+		return -EINVAL;
+	}
+
+	netdev_dbg(netdev, "AddrFamily: %d, %0x:%0x:%0x:%0x:%0x:%0x\n",
+			addr->sa_family, addr->sa_data[0], addr->sa_data[1],
+			addr->sa_data[2], addr->sa_data[3], addr->sa_data[4],
+			addr->sa_data[5]);
+
+	ret = eth_prepare_mac_addr_change(netdev, macaddr);
+	if (ret)
+		return ret;
+
+	if (dp_priv->data_plane_ops->mac_addr(dp_priv->dpc, macaddr)) {
+		netdev_dbg(netdev, "Data plane set MAC address failed\n");
+		return -EAGAIN;
+	}
+
+	eth_commit_mac_addr_change(netdev, macaddr);
+
+	dp_priv->gmac_hal_ops->setmacaddr(dp_priv->gmac_hal_ctx,
+			(uint8_t *)addr->sa_data);
+
+	return 0;
+}
+
+/*
+ * nss_dp_get_stats64()
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+static struct rtnl_link_stats64 *nss_dp_get_stats64(struct net_device *netdev,
+					     struct rtnl_link_stats64 *stats)
+{
+	struct nss_dp_dev *dp_priv;
+
+	if (!netdev)
+		return stats;
+
+	dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	/*
+	 * Get the GMAC MIB statistics
+	 */
+	dp_priv->gmac_hal_ops->getndostats(dp_priv->gmac_hal_ctx, stats);
+	return stats;
+}
+#else
+static void nss_dp_get_stats64(struct net_device *netdev,
+					     struct rtnl_link_stats64 *stats)
+{
+	struct nss_dp_dev *dp_priv;
+
+	if (!netdev)
+		return;
+
+	dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	/*
+	 * Get the GMAC MIB statistics
+	 */
+	dp_priv->gmac_hal_ops->getndostats(dp_priv->gmac_hal_ctx, stats);
+}
+#endif
+
+/*
+ * nss_dp_xmit()
+ */
+static netdev_tx_t nss_dp_xmit(struct sk_buff *skb, struct net_device *netdev)
+{
+	struct nss_dp_dev *dp_priv;
+
+	if (!skb || !netdev)
+		return NETDEV_TX_OK;
+
+	dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+	netdev_dbg(netdev, "Tx packet, len %d\n", skb->len);
+
+	return dp_priv->data_plane_ops->xmit(dp_priv->dpc, skb);
+}
+
+/*
+ * nss_dp_close()
+ */
+static int nss_dp_close(struct net_device *netdev)
+{
+	struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	if (!dp_priv)
+		return -EINVAL;
+
+	netif_stop_queue(netdev);
+	netif_carrier_off(netdev);
+
+	/* Notify data plane link is going down */
+	if (dp_priv->data_plane_ops->link_state(dp_priv->dpc, 0)) {
+		netdev_dbg(netdev, "Data plane set link failed\n");
+		return -EAGAIN;
+	}
+
+	if (dp_priv->phydev)
+		phy_stop(dp_priv->phydev);
+	dp_priv->link_state = __NSS_DP_LINK_DOWN;
+
+#if defined(NSS_DP_PPE_SUPPORT)
+	/*
+	 * Notify data plane to unassign VSI.
+	 * This is applicable only for dataplane override mode,
+	 * where NPU is expected to manage VSI assigns/un-assigns for ports.
+	 */
+	if (dp_priv->data_plane_ops->vsi_unassign) {
+		if (dp_priv->data_plane_ops->vsi_unassign(dp_priv->dpc,
+							dp_priv->vsi)) {
+			netdev_err(netdev, "Data plane vsi unassign failed\n");
+			return -EAGAIN;
+		}
+	}
+#endif
+
+	/*
+	 * Notify GMAC to stop
+	 */
+	if (dp_priv->gmac_hal_ops->stop(dp_priv->gmac_hal_ctx)) {
+		netdev_dbg(netdev, "GMAC stop failed\n");
+		return -EAGAIN;
+	}
+
+	/*
+	 * Notify data plane to close
+	 */
+	if (dp_priv->data_plane_ops->close(dp_priv->dpc)) {
+		netdev_dbg(netdev, "Data plane close failed\n");
+		return -EAGAIN;
+	}
+
+	clear_bit(__NSS_DP_UP, &dp_priv->flags);
+
+	return 0;
+}
+
+/*
+ * nss_dp_open()
+ */
+static int nss_dp_open(struct net_device *netdev)
+{
+	struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+
+	if (!dp_priv)
+		return -EINVAL;
+
+	netif_carrier_off(netdev);
+
+	/*
+	 * Call data plane init if it has not been done yet
+	 */
+	if (!(dp_priv->drv_flags & NSS_DP_PRIV_FLAG(INIT_DONE))) {
+		if (dp_priv->data_plane_ops->init(dp_priv->dpc)) {
+			netdev_dbg(netdev, "Data plane init failed\n");
+			return -ENOMEM;
+		}
+
+		dp_priv->drv_flags |= NSS_DP_PRIV_FLAG(INIT_DONE);
+	}
+
+	/*
+	 * Inform the Linux Networking stack about the hardware capability of
+	 * checksum offloading and other features. Each data_plane is
+	 * responsible to maintain the feature set it supports
+	 */
+	dp_priv->data_plane_ops->set_features(dp_priv->dpc);
+
+	set_bit(__NSS_DP_UP, &dp_priv->flags);
+
+#if defined(NSS_DP_PPE_SUPPORT)
+	/*
+	 * Notify data plane to assign VSI if required.
+	 * This is applicable only for dataplane override mode,
+	 * where NPU is expected to manage VSI assigns/un-assigns
+	 * based on port status and network configuration.
+	 */
+	if (dp_priv->data_plane_ops->vsi_assign) {
+		if (dp_priv->data_plane_ops->vsi_assign(dp_priv->dpc,
+							dp_priv->vsi)) {
+			netdev_err(netdev, "Data plane vsi assign failed\n");
+			return -EAGAIN;
+		}
+	}
+#endif
+
+	if (dp_priv->data_plane_ops->mac_addr(dp_priv->dpc, netdev->dev_addr)) {
+		netdev_dbg(netdev, "Data plane set MAC address failed\n");
+		return -EAGAIN;
+	}
+
+	if (dp_priv->data_plane_ops->change_mtu(dp_priv->dpc, netdev->mtu)) {
+		netdev_dbg(netdev, "Data plane change mtu failed\n");
+		return -EAGAIN;
+	}
+
+	if (dp_priv->data_plane_ops->open(dp_priv->dpc, 0, 0, 0)) {
+		netdev_dbg(netdev, "Data plane open failed\n");
+		return -EAGAIN;
+	}
+
+	/*
+	 * Notify GMAC to start receive/transmit
+	 */
+	if (dp_priv->gmac_hal_ops->start(dp_priv->gmac_hal_ctx)) {
+		netdev_dbg(netdev, "GMAC start failed\n");
+		return -EAGAIN;
+	}
+
+	netif_start_queue(netdev);
+
+	if (!dp_priv->link_poll) {
+		/* Notify data plane link is up */
+		if (dp_priv->data_plane_ops->link_state(dp_priv->dpc, 1)) {
+			netdev_dbg(netdev, "Data plane set link failed\n");
+			return -EAGAIN;
+		}
+		dp_priv->link_state = __NSS_DP_LINK_UP;
+		netif_carrier_on(netdev);
+	} else {
+		dp_priv->link_state = __NSS_DP_LINK_DOWN;
+		phy_start(dp_priv->phydev);
+		phy_start_aneg(dp_priv->phydev);
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_RFS_ACCEL
+/*
+ * nss_dp_rx_flow_steer()
+ *	Steer the flow rule to NSS
+ */
+static int nss_dp_rx_flow_steer(struct net_device *netdev, const struct sk_buff *_skb,
+				uint16_t rxq, uint32_t flow)
+{
+	struct nss_dp_dev *dp_priv;
+	struct netdev_rx_queue *rxqueue;
+	struct rps_sock_flow_table *sock_flow_table;
+	struct rps_dev_flow_table *flow_table;
+	struct rps_dev_flow *rxflow;
+	struct sk_buff *skb = (struct sk_buff *)_skb;
+	uint16_t index;
+	uint32_t hash;
+	uint32_t rfscpu;
+	uint32_t rxcpu;
+
+	if (!netdev)
+		return -EINVAL;
+
+	dp_priv = (struct nss_dp_dev *)netdev_priv(netdev);
+	if (!dp_priv)
+		return -EINVAL;
+
+	rxqueue = netdev->_rx;
+
+	if (skb_rx_queue_recorded(skb)) {
+		index = skb_get_rx_queue(skb);
+		rxqueue += index;
+	}
+
+	flow_table = rcu_dereference(rxqueue->rps_flow_table);
+	if (!flow_table) {
+		netdev_dbg(netdev, "RX queue RPS flow table not found\n");
+		return -EINVAL;
+	}
+
+	hash = skb_get_hash(skb);
+	rxflow = &flow_table->flows[hash & flow_table->mask];
+	rxcpu = (uint32_t)rxflow->cpu;
+
+	sock_flow_table = rcu_dereference(rps_sock_flow_table);
+	if (!sock_flow_table) {
+		netdev_dbg(netdev, "Global RPS flow table not found\n");
+		return -EINVAL;
+	}
+
+	rfscpu = sock_flow_table->ents[hash & sock_flow_table->mask];
+	rfscpu &= rps_cpu_mask;
+
+	if (rxcpu == rfscpu)
+		return 0;
+
+	/*
+	 * check rx_flow_steer is defined in data plane ops
+	 */
+	if (!dp_priv->data_plane_ops->rx_flow_steer) {
+		netdev_dbg(netdev, "Data plane ops not defined for flow steer\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Delete the old flow rule
+	 */
+	if (dp_priv->data_plane_ops->rx_flow_steer(dp_priv->dpc, skb, rxcpu, false)) {
+		netdev_dbg(netdev, "Data plane delete flow rule failed\n");
+		return -EAGAIN;
+	}
+
+	/*
+	 * Add the new flow rule
+	 */
+	if (dp_priv->data_plane_ops->rx_flow_steer(dp_priv->dpc, skb, rfscpu, true)) {
+		netdev_dbg(netdev, "Data plane add flow rule failed\n");
+		return -EAGAIN;
+	}
+
+	return 0;
+}
+#endif
+
+/*
+ * nss_dp_select_queue()
+ *	Select tx queue
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+static u16 __attribute__((unused)) nss_dp_select_queue(struct net_device *netdev, struct sk_buff *skb,
+				void *accel_priv, select_queue_fallback_t fallback)
+#else
+static u16 __attribute__((unused)) nss_dp_select_queue(struct net_device *netdev, struct sk_buff *skb,
+				struct net_device *sb_dev)
+#endif
+{
+	int cpu = get_cpu();
+	put_cpu();
+
+	/*
+	 * The number of queue is matching the number of CPUs so get_cpu will
+	 * always match a valid queue
+	 */
+	return cpu;
+}
+
+/*
+ * Netdevice operations
+ */
+static const struct net_device_ops nss_dp_netdev_ops = {
+	.ndo_open = nss_dp_open,
+	.ndo_stop = nss_dp_close,
+	.ndo_start_xmit = nss_dp_xmit,
+	.ndo_get_stats64 = nss_dp_get_stats64,
+	.ndo_set_mac_address = nss_dp_set_mac_address,
+	.ndo_validate_addr = eth_validate_addr,
+	.ndo_change_mtu = nss_dp_change_mtu,
+	.ndo_do_ioctl = nss_dp_do_ioctl,
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+	.ndo_bridge_setlink = switchdev_port_bridge_setlink,
+	.ndo_bridge_getlink = switchdev_port_bridge_getlink,
+	.ndo_bridge_dellink = switchdev_port_bridge_dellink,
+#endif
+#ifndef NSS_DP_IPQ50XX
+	.ndo_select_queue = nss_dp_select_queue,
+#endif
+
+#ifdef CONFIG_RFS_ACCEL
+	.ndo_rx_flow_steer = nss_dp_rx_flow_steer,
+#endif
+};
+
+/*
+ * nss_dp_of_get_pdata()
+ */
+static int32_t nss_dp_of_get_pdata(struct device_node *np,
+				   struct net_device *netdev,
+				   struct nss_gmac_hal_platform_data *hal_pdata)
+{
+	uint8_t *maddr;
+	struct nss_dp_dev *dp_priv;
+	struct resource memres_devtree = {0};
+
+	dp_priv = netdev_priv(netdev);
+
+	if (of_property_read_u32(np, "qcom,id", &dp_priv->macid)) {
+		pr_err("%s: error reading id\n", np->name);
+		return -EFAULT;
+	}
+
+	/*
+	 * change interface 1 name to wan0
+	 * change interface 2 name to lan0
+	 */
+	if (dp_priv->macid == 1) {
+		strcpy(netdev->name, "wan0");
+	} else if (dp_priv->macid == 2) {
+		strcpy(netdev->name, "lan0");
+	}
+
+	if (dp_priv->macid > NSS_DP_HAL_MAX_PORTS || !dp_priv->macid) {
+		pr_err("%s: invalid macid %d\n", np->name, dp_priv->macid);
+		return -EFAULT;
+	}
+
+	if (of_property_read_u32(np, "qcom,mactype", &hal_pdata->mactype)) {
+		pr_err("%s: error reading mactype\n", np->name);
+		return -EFAULT;
+	}
+
+	if (of_address_to_resource(np, 0, &memres_devtree) != 0)
+		return -EFAULT;
+
+	netdev->base_addr = memres_devtree.start;
+	hal_pdata->reg_len = resource_size(&memres_devtree);
+	hal_pdata->netdev = netdev;
+	hal_pdata->macid = dp_priv->macid;
+
+	dp_priv->phy_mii_type = of_get_phy_mode(np);
+	dp_priv->link_poll = of_property_read_bool(np, "qcom,link-poll");
+	if (of_property_read_u32(np, "qcom,phy-mdio-addr",
+		&dp_priv->phy_mdio_addr) && dp_priv->link_poll) {
+		pr_err("%s: mdio addr required if link polling is enabled\n",
+				np->name);
+		return -EFAULT;
+	}
+
+	of_property_read_u32(np, "qcom,forced-speed", &dp_priv->forced_speed);
+	of_property_read_u32(np, "qcom,forced-duplex", &dp_priv->forced_duplex);
+
+	maddr = (uint8_t *)of_get_mac_address(np);
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 4, 0))
+	if (IS_ERR((void *)maddr)) {
+		maddr = NULL;
+	}
+#endif
+
+	if (maddr && is_valid_ether_addr(maddr)) {
+		ether_addr_copy(netdev->dev_addr, maddr);
+	} else {
+		random_ether_addr(netdev->dev_addr);
+		pr_info("GMAC%d(%px) Invalid MAC@ - using %pM\n", dp_priv->macid,
+						dp_priv, netdev->dev_addr);
+	}
+#if !defined(NSS_DP_MEM_PROFILE_LOW) && !defined(NSS_DP_MEM_PROFILE_MEDIUM)
+	of_property_read_u32(np, "qcom,rx-page-mode", &dp_priv->rx_page_mode);
+	if (overwrite_mode) {
+		pr_info("Page mode is overwritten: %d\n", page_mode);
+		dp_priv->rx_page_mode = page_mode;
+	}
+
+	if (jumbo_mru) {
+		dp_priv->rx_page_mode = false;
+		dp_priv->rx_jumbo_mru = jumbo_mru;
+		pr_info("Jumbo mru is enabled: %d\n", dp_priv->rx_jumbo_mru);
+	}
+#else
+	if (overwrite_mode || page_mode || jumbo_mru) {
+		pr_err("Low memory profiles does not support page mode/jumbo mru\n");
+		return -EFAULT;
+	}
+#endif
+
+	return 0;
+}
+
+/*
+ * nss_dp_mdio_attach()
+ */
+static struct mii_bus *nss_dp_mdio_attach(struct platform_device *pdev)
+{
+	struct device_node *mdio_node;
+	struct platform_device *mdio_plat;
+	struct ipq40xx_mdio_data *mdio_data;
+
+	/*
+	 * Find mii_bus using "mdio-bus" handle.
+	 */
+	mdio_node = of_parse_phandle(pdev->dev.of_node, "mdio-bus", 0);
+	if (mdio_node) {
+		return of_mdio_find_bus(mdio_node);
+	}
+
+	mdio_node = of_find_compatible_node(NULL, NULL, "qcom,qca-mdio");
+	if (!mdio_node) {
+		mdio_node = of_find_compatible_node(NULL, NULL,
+							"qcom,ipq40xx-mdio");
+		if (!mdio_node) {
+			dev_err(&pdev->dev, "cannot find mdio node by phandle\n");
+			return NULL;
+		}
+	}
+
+	mdio_plat = of_find_device_by_node(mdio_node);
+	if (!mdio_plat) {
+		dev_err(&pdev->dev, "cannot find platform device from mdio node\n");
+		of_node_put(mdio_node);
+		return NULL;
+	}
+
+	mdio_data = dev_get_drvdata(&mdio_plat->dev);
+	if (!mdio_data) {
+		dev_err(&pdev->dev, "cannot get mii bus reference from device data\n");
+		of_node_put(mdio_node);
+		return NULL;
+	}
+
+	return mdio_data->mii_bus;
+}
+
+#ifdef NSS_DP_PPE_SWITCHDEV
+/*
+ * nss_dp_is_phy_dev()
+ *	Check if it is dp device
+ */
+bool nss_dp_is_phy_dev(struct net_device *dev)
+{
+	return (dev->netdev_ops == &nss_dp_netdev_ops);
+}
+#endif
+
+/*
+ * nss_dp_adjust_link()
+ */
+void nss_dp_adjust_link(struct net_device *netdev)
+{
+	struct nss_dp_dev *dp_priv = netdev_priv(netdev);
+	int current_state = dp_priv->link_state;
+
+	if (!test_bit(__NSS_DP_UP, &dp_priv->flags))
+		return;
+
+	if (dp_priv->phydev->link && (current_state == __NSS_DP_LINK_UP))
+		return;
+
+	if (!dp_priv->phydev->link && (current_state == __NSS_DP_LINK_DOWN))
+		return;
+
+	if (current_state == __NSS_DP_LINK_DOWN) {
+		netdev_info(netdev, "PHY Link up speed: %d\n",
+						dp_priv->phydev->speed);
+		if (dp_priv->data_plane_ops->link_state(dp_priv->dpc, 1)) {
+			netdev_dbg(netdev, "Data plane set link up failed\n");
+			return;
+		}
+		dp_priv->link_state = __NSS_DP_LINK_UP;
+		netif_carrier_on(netdev);
+	} else {
+		netdev_info(netdev, "PHY Link is down\n");
+		if (dp_priv->data_plane_ops->link_state(dp_priv->dpc, 0)) {
+			netdev_dbg(netdev, "Data plane set link down failed\n");
+			return;
+		}
+		dp_priv->link_state = __NSS_DP_LINK_DOWN;
+		netif_carrier_off(netdev);
+	}
+}
+
+/*
+ * nss_dp_probe()
+ */
+static int32_t nss_dp_probe(struct platform_device *pdev)
+{
+	struct net_device *netdev;
+	struct nss_dp_dev *dp_priv;
+	struct device_node *np = pdev->dev.of_node;
+	struct nss_gmac_hal_platform_data gmac_hal_pdata;
+	int32_t ret = 0;
+	uint8_t phy_id[MII_BUS_ID_SIZE + 3];
+#if defined(NSS_DP_PPE_SUPPORT)
+	uint32_t vsi_id;
+	fal_port_t port_id;
+#endif
+
+	/* TODO: See if we need to do some SoC level common init */
+
+	netdev = alloc_etherdev_mqs(sizeof(struct nss_dp_dev),
+			NSS_DP_NETDEV_TX_QUEUE_NUM, NSS_DP_NETDEV_RX_QUEUE_NUM);
+	if (!netdev) {
+		pr_info("alloc_etherdev() failed\n");
+		return -ENOMEM;
+	}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0))
+	/* max_mtu is set to 1500 in ether_setup() */
+	netdev->max_mtu = ETH_MAX_MTU;
+#endif
+
+	dp_priv = netdev_priv(netdev);
+	memset((void *)dp_priv, 0, sizeof(struct nss_dp_dev));
+
+	dp_priv->pdev = pdev;
+	dp_priv->netdev = netdev;
+	netdev->watchdog_timeo = 5 * HZ;
+	netdev->netdev_ops = &nss_dp_netdev_ops;
+	nss_dp_set_ethtool_ops(netdev);
+#ifdef NSS_DP_PPE_SWITCHDEV
+	nss_dp_switchdev_setup(netdev);
+#endif
+
+	ret = nss_dp_of_get_pdata(np, netdev, &gmac_hal_pdata);
+	if (ret != 0) {
+		goto fail;
+	}
+
+	/* Use data plane ops as per the configured SoC */
+	dp_priv->data_plane_ops = nss_dp_hal_get_data_plane_ops();
+	if (!dp_priv->data_plane_ops) {
+		netdev_dbg(netdev, "Dataplane ops not found.\n");
+		goto fail;
+	}
+
+	dp_priv->dpc = &dp_global_data_plane_ctx[dp_priv->macid-1];
+	dp_priv->dpc->dev = netdev;
+	dp_priv->ctx = &dp_global_ctx;
+
+	/* TODO:locks init */
+
+	/*
+	 * HAL's init function will return the pointer to the HAL context
+	 * (private to hal), which dp will store in its data structures.
+	 * The subsequent hal_ops calls expect the DP to pass the HAL
+	 * context pointer as an argument
+	 */
+	dp_priv->gmac_hal_ops = nss_dp_hal_get_gmac_ops(gmac_hal_pdata.mactype);
+	if (!dp_priv->gmac_hal_ops) {
+		netdev_dbg(netdev, "Unsupported Mac type: %d\n", gmac_hal_pdata.mactype);
+		goto fail;
+	}
+
+	dp_priv->gmac_hal_ctx = dp_priv->gmac_hal_ops->init(&gmac_hal_pdata);
+	if (!(dp_priv->gmac_hal_ctx)) {
+		netdev_dbg(netdev, "GMAC hal init failed\n");
+		goto fail;
+	}
+
+	if (dp_priv->data_plane_ops->init(dp_priv->dpc)) {
+		netdev_dbg(netdev, "Data plane init failed\n");
+		goto data_plane_init_fail;
+	}
+
+	dp_priv->drv_flags |= NSS_DP_PRIV_FLAG(INIT_DONE);
+
+	if (dp_priv->link_poll) {
+		dp_priv->miibus = nss_dp_mdio_attach(pdev);
+		if (!dp_priv->miibus) {
+			netdev_dbg(netdev, "failed to find miibus\n");
+			goto phy_setup_fail;
+		}
+		snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
+				dp_priv->miibus->id, dp_priv->phy_mdio_addr);
+
+		SET_NETDEV_DEV(netdev, &pdev->dev);
+
+		dp_priv->phydev = phy_connect(netdev, phy_id,
+				&nss_dp_adjust_link,
+				dp_priv->phy_mii_type);
+		if (IS_ERR(dp_priv->phydev)) {
+			netdev_dbg(netdev, "failed to connect to phy device\n");
+			goto phy_setup_fail;
+		}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+		dp_priv->phydev->advertising |=
+			(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
+		dp_priv->phydev->supported |=
+			(SUPPORTED_Pause | SUPPORTED_Asym_Pause);
+#else
+		linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, dp_priv->phydev->advertising);
+		linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, dp_priv->phydev->advertising);
+
+		linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, dp_priv->phydev->supported);
+		linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, dp_priv->phydev->supported);
+#endif
+	}
+
+#if defined(NSS_DP_PPE_SUPPORT)
+	/* Get port's default VSI */
+	port_id = dp_priv->macid;
+	if (ppe_port_vsi_get(0, port_id, &vsi_id)) {
+		netdev_dbg(netdev, "failed to get port's default VSI\n");
+		goto phy_setup_fail;
+	}
+
+	dp_priv->vsi = vsi_id;
+
+	/*
+	 * Assign the VSI to the port.
+	 */
+	if (fal_port_vsi_set(0, port_id, vsi_id) < 0) {
+		netdev_dbg(netdev, "Data plane vsi assign failed\n");
+		goto phy_setup_fail;
+	}
+#endif
+
+	/* TODO: Features: CSUM, tx/rx offload... configure */
+
+	/* Register the network interface */
+	ret = register_netdev(netdev);
+	if (ret) {
+		netdev_dbg(netdev, "Error registering netdevice %s\n",
+								netdev->name);
+		goto phy_setup_fail;
+	}
+
+	dp_global_ctx.nss_dp[dp_priv->macid - 1] = dp_priv;
+	dp_global_ctx.slowproto_acl_bm = 0;
+
+	netdev_dbg(netdev, "Init NSS DP GMAC%d (base = 0x%lx)\n", dp_priv->macid, netdev->base_addr);
+
+	return 0;
+
+phy_setup_fail:
+	dp_priv->data_plane_ops->deinit(dp_priv->dpc);
+data_plane_init_fail:
+	dp_priv->gmac_hal_ops->exit(dp_priv->gmac_hal_ctx);
+fail:
+	free_netdev(netdev);
+	return -EFAULT;
+}
+
+/*
+ * nss_dp_remove()
+ */
+static int nss_dp_remove(struct platform_device *pdev)
+{
+	uint32_t i;
+	struct nss_dp_dev *dp_priv;
+	struct nss_gmac_hal_ops *hal_ops;
+	struct nss_dp_data_plane_ops *dp_ops;
+
+	for (i = 0; i < NSS_DP_HAL_MAX_PORTS; i++) {
+		dp_priv = dp_global_ctx.nss_dp[i];
+		if (!dp_priv)
+			continue;
+
+		dp_ops = dp_priv->data_plane_ops;
+		hal_ops = dp_priv->gmac_hal_ops;
+
+		if (dp_priv->phydev)
+			phy_disconnect(dp_priv->phydev);
+
+#if defined(NSS_DP_PPE_SUPPORT)
+		/*
+		 * Unassign the port's VSI.
+		 */
+		fal_port_vsi_set(0, dp_priv->macid, 0xFFFF);
+#endif
+		hal_ops->exit(dp_priv->gmac_hal_ctx);
+		dp_ops->deinit(dp_priv->dpc);
+		unregister_netdev(dp_priv->netdev);
+		free_netdev(dp_priv->netdev);
+		dp_global_ctx.nss_dp[i] = NULL;
+	}
+
+	return 0;
+}
+
+static struct of_device_id nss_dp_dt_ids[] = {
+	{ .compatible = "qcom,nss-dp" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, nss_dp_dt_ids);
+
+static struct platform_driver nss_dp_drv = {
+	.probe = nss_dp_probe,
+	.remove = nss_dp_remove,
+	.driver = {
+		   .name = "nss-dp",
+		   .owner = THIS_MODULE,
+		   .of_match_table = of_match_ptr(nss_dp_dt_ids),
+		  },
+};
+
+/*
+ * nss_dp_is_netdev_physical()
+ *	Check the given net device is in DP
+ */
+bool nss_dp_is_netdev_physical(struct net_device *netdev)
+{
+	uint32_t i;
+	struct nss_dp_dev *dp_priv;
+
+	for (i = 0; i < NSS_DP_HAL_MAX_PORTS; i++) {
+		dp_priv = dp_global_ctx.nss_dp[i];
+		if (!dp_priv) {
+			continue;
+		}
+
+		if (dp_priv->netdev == netdev) {
+			return true;
+		}
+	}
+
+	return false;
+}
+EXPORT_SYMBOL(nss_dp_is_netdev_physical);
+
+/*
+ * nss_dp_get_port_num()
+ *	Return port number for the given netdevice
+ */
+int32_t nss_dp_get_port_num(struct net_device *netdev)
+{
+	struct nss_dp_dev *dp_priv;
+
+	if (!nss_dp_is_netdev_physical(netdev)) {
+		return NSS_DP_INVALID_INTERFACE;
+	}
+
+	dp_priv = netdev_priv(netdev);
+	return dp_priv->macid;
+}
+EXPORT_SYMBOL(nss_dp_get_port_num);
+
+/*
+ * nss_dp_init()
+ */
+int __init nss_dp_init(void)
+{
+	int ret;
+
+	dp_global_ctx.common_init_done = false;
+
+	/*
+	 * Get the buffer size to allocate
+	 */
+	dp_global_ctx.rx_buf_size = NSS_DP_RX_BUFFER_SIZE;
+
+	/*
+	 * Get the module params.
+	 * We do not support page_mode or jumbo_mru on low memory profiles.
+	 */
+	dp_global_ctx.tx_requeue_stop = false;
+	if (tx_requeue_stop != 0) {
+		dp_global_ctx.tx_requeue_stop = true;
+	}
+#if !defined(NSS_DP_MEM_PROFILE_LOW) && !defined(NSS_DP_MEM_PROFILE_MEDIUM)
+	dp_global_ctx.overwrite_mode = overwrite_mode;
+	dp_global_ctx.page_mode = page_mode;
+	dp_global_ctx.jumbo_mru = jumbo_mru;
+#else
+	if ((overwrite_mode && page_mode) || jumbo_mru) {
+		pr_err("Low memory profiles does not support page mode/jumbo mru\n");
+	}
+#endif
+
+	/*
+	 * Check platform compatibility and
+	 * set GMAC and data_plane ops.
+	 */
+	if (!nss_dp_hal_init()) {
+		pr_err("DP hal init failed.\n");
+		return -EFAULT;
+	}
+
+	ret = platform_driver_register(&nss_dp_drv);
+	if (ret)
+		pr_info("NSS DP platform drv register failed\n");
+
+	dp_global_ctx.common_init_done = true;
+	pr_info("**********************************************************\n");
+	pr_info("* NSS Data Plane driver\n");
+	pr_info("**********************************************************\n");
+
+	return ret;
+}
+
+/*
+ * nss_dp_exit()
+ */
+void __exit nss_dp_exit(void)
+{
+	/*
+	 * TODO Move this to soc_ops
+	 */
+	if (dp_global_ctx.common_init_done) {
+		nss_dp_hal_cleanup();
+		dp_global_ctx.common_init_done = false;
+	}
+
+	platform_driver_unregister(&nss_dp_drv);
+}
+
+module_init(nss_dp_init);
+module_exit(nss_dp_exit);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("NSS Data Plane Network Driver");
diff --git a/qca-nss-dp/nss_dp_switchdev.c b/qca-nss-dp/nss_dp_switchdev.c
new file mode 100644
index 0000000..842b843
--- /dev/null
+++ b/qca-nss-dp/nss_dp_switchdev.c
@@ -0,0 +1,367 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/if_bridge.h>
+#include <linux/if_vlan.h>
+#include <linux/version.h>
+#include <net/switchdev.h>
+
+#include "nss_dp_dev.h"
+#include "fal/fal_stp.h"
+#include "fal/fal_ctrlpkt.h"
+
+#define NSS_DP_SWITCH_ID		0
+#define NSS_DP_SW_ETHTYPE_PID		0 /* PPE ethtype profile ID for slow protocols */
+#define ETH_P_NONE			0
+
+/*
+ * nss_dp_set_slow_proto_filter()
+ * 	Enable/Disable filter to allow Ethernet slow-protocol
+ */
+static void nss_dp_set_slow_proto_filter(struct nss_dp_dev *dp_priv, bool filter_enable)
+{
+	sw_error_t ret = 0;
+	fal_ctrlpkt_profile_t profile;
+	fal_ctrlpkt_action_t action;
+
+	memset(&profile, 0, sizeof(profile));
+
+	/*
+	 * Action is redirect cpu
+	 */
+	action.action = FAL_MAC_RDT_TO_CPU;
+	action.sg_bypass = A_FALSE;
+
+	/*
+	 * Bypass stp
+	 */
+	action.in_stp_bypass = A_TRUE;
+	action.in_vlan_fltr_bypass = A_FALSE;
+	action.l2_filter_bypass = A_FALSE;
+	profile.action = action;
+	profile.ethtype_profile_bitmap = 0x1;
+
+	/*
+	 * Set port map
+	 */
+	profile.port_map = (1 << dp_priv->macid);
+	if (filter_enable) {
+		ret = fal_mgmtctrl_ctrlpkt_profile_add(NSS_DP_SWITCH_ID, &profile);
+		if (ret != SW_OK) {
+			netdev_dbg(dp_priv->netdev, "failed to add profile for port_map: 0x%x, ret: %d\n", profile.port_map, ret);
+			return;
+		}
+
+		/*
+		 * Enable filter to allow ethernet slow-protocol,
+		 * if this is the first port being disabled by STP
+		 */
+		if (!dp_priv->ctx->slowproto_acl_bm) {
+			ret = fal_mgmtctrl_ethtype_profile_set(NSS_DP_SWITCH_ID, NSS_DP_SW_ETHTYPE_PID, ETH_P_SLOW);
+			if (ret != SW_OK) {
+				netdev_dbg(dp_priv->netdev, "failed to set ethertype profile: 0x%x, ret: %d\n", ETH_P_SLOW, ret);
+				ret = fal_mgmtctrl_ctrlpkt_profile_del(NSS_DP_SWITCH_ID, &profile);
+				if (ret != SW_OK) {
+					netdev_dbg(dp_priv->netdev, "failed to delete profile for port_map: 0x%x, ret: %d\n", profile.port_map, ret);
+				}
+				return;
+			}
+		}
+
+		/*
+		 * Add port to port bitmap
+		 */
+		dp_priv->ctx->slowproto_acl_bm = dp_priv->ctx->slowproto_acl_bm | (1 << dp_priv->macid);
+	} else {
+
+		ret = fal_mgmtctrl_ctrlpkt_profile_del(NSS_DP_SWITCH_ID, &profile);
+		if (ret != SW_OK) {
+			netdev_dbg(dp_priv->netdev, "failed to delete profile for port_map: 0x%x, ret: %d\n", profile.port_map, ret);
+			return;
+		}
+
+		/*
+		 * Delete port from port bitmap
+		 */
+		dp_priv->ctx->slowproto_acl_bm = dp_priv->ctx->slowproto_acl_bm & (~(1 << dp_priv->macid));
+
+		/*
+		 * If all ports are in STP-enabled state, then we do not need
+		 * the filter to allow ethernet slow protocol packets
+		 */
+		if (!dp_priv->ctx->slowproto_acl_bm) {
+			ret = fal_mgmtctrl_ethtype_profile_set(NSS_DP_SWITCH_ID, NSS_DP_SW_ETHTYPE_PID, ETH_P_NONE);
+			if (ret != SW_OK) {
+				netdev_dbg(dp_priv->netdev, "failed to reset ethertype profile: 0x%x ret: %d\n", ETH_P_NONE, ret);
+			}
+		}
+	}
+}
+
+/*
+ * nss_dp_stp_state_set()
+ *	Set bridge port STP state to the port of NSS data plane.
+ */
+static int nss_dp_stp_state_set(struct nss_dp_dev *dp_priv, u8 state)
+{
+	sw_error_t err;
+	fal_stp_state_t stp_state;
+
+	switch (state) {
+	case BR_STATE_DISABLED:
+		stp_state = FAL_STP_DISABLED;
+
+		/*
+		 * Dynamic bond interfaces which are bridge slaves need to receive
+		 * ethernet slow protocol packets for LACP protocol even in STP
+		 * disabled state
+		 */
+		nss_dp_set_slow_proto_filter(dp_priv, true);
+		break;
+	case BR_STATE_LISTENING:
+		stp_state = FAL_STP_LISTENING;
+		break;
+	case BR_STATE_BLOCKING:
+		stp_state = FAL_STP_BLOCKING;
+		break;
+	case BR_STATE_LEARNING:
+		stp_state = FAL_STP_LEARNING;
+		break;
+	case BR_STATE_FORWARDING:
+		stp_state = FAL_STP_FORWARDING;
+
+		/*
+		 * Remove the filter for allowing ethernet slow protocol packets
+		 * for bond interfaces
+		 */
+		nss_dp_set_slow_proto_filter(dp_priv, false);
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+
+	err = fal_stp_port_state_set(NSS_DP_SWITCH_ID, 0, dp_priv->macid,
+				     stp_state);
+	if (err) {
+		netdev_dbg(dp_priv->netdev, "failed to set ftp state\n");
+
+		/*
+		 * Restore the slow proto filters
+		 */
+		if (state == BR_STATE_DISABLED)
+			nss_dp_set_slow_proto_filter(dp_priv, false);
+		else if (state == BR_STATE_FORWARDING)
+			nss_dp_set_slow_proto_filter(dp_priv, true);
+
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+/*
+ * nss_dp_attr_get()
+ *	Get port information to update switchdev attribute for NSS data plane.
+ */
+static int nss_dp_attr_get(struct net_device *dev, struct switchdev_attr *attr)
+{
+	struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(dev);
+
+	switch (attr->id) {
+	case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
+		attr->u.ppid.id_len = 1;
+		attr->u.ppid.id[0] = NSS_DP_SWITCH_ID;
+		break;
+
+	case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS:
+		attr->u.brport_flags = dp_priv->brport_flags;
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_dp_attr_set()
+ *	Get switchdev attribute and set to the device of NSS data plane.
+ */
+static int nss_dp_attr_set(struct net_device *dev,
+				const struct switchdev_attr *attr,
+				struct switchdev_trans *trans)
+{
+	struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(dev);
+	struct net_device *upper_dev;
+	struct vlan_dev_priv *vlan;
+	struct list_head *iter;
+	uint32_t stp_state = attr->u.stp_state;
+
+	if (switchdev_trans_ph_prepare(trans))
+		return 0;
+
+	switch (attr->id) {
+	case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS:
+		dp_priv->brport_flags = attr->u.brport_flags;
+		netdev_dbg(dev, "set brport_flags %lu\n", attr->u.brport_flags);
+		return 0;
+	case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
+		/*
+		 * The stp state is not changed to FAL_STP_DISABLED if
+		 * the net_device (dev) has any vlan configured. Otherwise
+		 * traffic on other vlan(s) will not work.
+		 *
+		 * Note: STP for VLANs is not supported by PPE.
+		 */
+		if ((stp_state == BR_STATE_DISABLED) ||
+			(stp_state == BR_STATE_BLOCKING)) {
+			rcu_read_lock();
+			netdev_for_each_upper_dev_rcu(dev, upper_dev, iter) {
+				if (!is_vlan_dev(upper_dev))
+					continue;
+
+				vlan = vlan_dev_priv(upper_dev);
+				if (vlan->real_dev == dev) {
+					rcu_read_unlock();
+					netdev_dbg(dev, "Do not update stp state to: %u since vlan id: %d is configured on netdevice: %s\n",
+							stp_state, vlan->vlan_id, vlan->real_dev->name);
+					return 0;
+				}
+			}
+
+			rcu_read_unlock();
+		}
+
+		return nss_dp_stp_state_set(dp_priv, stp_state);
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+/*
+ * nss_dp_switchdev_ops
+ *	Switchdev operations of NSS data plane.
+ */
+static const struct switchdev_ops nss_dp_switchdev_ops = {
+	.switchdev_port_attr_get	= nss_dp_attr_get,
+	.switchdev_port_attr_set	= nss_dp_attr_set,
+};
+
+/*
+ * nss_dp_switchdev_setup()
+ *	Set up NSS data plane switchdev operations.
+ */
+void nss_dp_switchdev_setup(struct net_device *dev)
+{
+	dev->switchdev_ops = &nss_dp_switchdev_ops;
+	switchdev_port_fwd_mark_set(dev, NULL, false);
+}
+#else
+
+/*
+ * nss_dp_port_attr_set()
+ *	Sets attributes
+ */
+static int nss_dp_port_attr_set(struct net_device *dev,
+				const struct switchdev_attr *attr,
+				struct switchdev_trans *trans)
+{
+	struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(dev);
+
+	if (switchdev_trans_ph_prepare(trans))
+		return 0;
+
+	switch (attr->id) {
+	case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS:
+		dp_priv->brport_flags = attr->u.brport_flags;
+		netdev_dbg(dev, "set brport_flags %lu\n", attr->u.brport_flags);
+		return 0;
+	case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
+		return nss_dp_stp_state_set(dp_priv, attr->u.stp_state);
+	default:
+		return -EOPNOTSUPP;
+	}
+
+}
+
+/*
+ * nss_dp_switchdev_port_attr_set_event()
+ *	Attribute set event
+ */
+static int nss_dp_switchdev_port_attr_set_event(struct net_device *netdev,
+		struct switchdev_notifier_port_attr_info *port_attr_info)
+{
+	int err;
+
+	err = nss_dp_port_attr_set(netdev, port_attr_info->attr,
+				   port_attr_info->trans);
+
+	port_attr_info->handled = true;
+	return notifier_from_errno(err);
+}
+
+/*
+ * nss_dp_switchdev_event()
+ *	Switch dev event on netdevice
+ */
+static int nss_dp_switchdev_event(struct notifier_block *unused,
+				  unsigned long event, void *ptr)
+{
+	struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
+
+	/*
+	 * Handle switchdev event only for physical devices
+	 */
+	if (!nss_dp_is_phy_dev(dev)) {
+		return NOTIFY_DONE;
+	}
+
+	if (event == SWITCHDEV_PORT_ATTR_SET)
+		nss_dp_switchdev_port_attr_set_event(dev, ptr);
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block nss_dp_switchdev_notifier = {
+	.notifier_call = nss_dp_switchdev_event,
+};
+
+static bool switch_init_done;
+
+/*
+ * nss_dp_switchdev_setup()
+ *	Setup switch dev
+ */
+void nss_dp_switchdev_setup(struct net_device *dev)
+{
+	int err;
+
+	if (switch_init_done) {
+		return;
+	}
+
+	err = register_switchdev_blocking_notifier(&nss_dp_switchdev_notifier);
+	if (err) {
+		netdev_dbg(dev, "%px:Failed to register switchdev notifier\n", dev);
+	}
+
+	switch_init_done = true;
+
+}
+#endif
diff --git a/qca-nss-drv/.gitignore b/qca-nss-drv/.gitignore
new file mode 100644
index 0000000..cb831ad
--- /dev/null
+++ b/qca-nss-drv/.gitignore
@@ -0,0 +1,14 @@
+
+# Ignore general build intermediate files
+*.o
+*.cmd
+*.ko
+*.mod.*
+*.mod
+Module.symvers
+modules.order
+/.tmp_versions/
+built-in.a
+
+# don't ignore .gitignore itself
+!.gitignore
diff --git a/qca-nss-drv/Makefile b/qca-nss-drv/Makefile
new file mode 100644
index 0000000..74b9c4b
--- /dev/null
+++ b/qca-nss-drv/Makefile
@@ -0,0 +1,537 @@
+# ###################################################
+# # Makefile for the NSS driver
+# ###################################################
+
+obj-m += qca-nss-drv.o
+
+#
+# List the files that belong to the driver in alphabetical order.
+#
+qca-nss-drv-objs := \
+			nss_cmn.o \
+			nss_core.o \
+			nss_coredump.o \
+			nss_drv_stats.o \
+			nss_drv_strings.o \
+			nss_dynamic_interface.o \
+			nss_dynamic_interface_log.o \
+			nss_dynamic_interface_stats.o \
+			nss_eth_rx.o \
+			nss_eth_rx_stats.o \
+			nss_eth_rx_strings.o \
+			nss_gmac_stats.o \
+			nss_if.o \
+			nss_if_log.o \
+			nss_init.o \
+			nss_ipv4.o \
+			nss_ipv4_stats.o \
+			nss_ipv4_strings.o \
+			nss_ipv4_log.o \
+			nss_log.o \
+			nss_lso_rx.o \
+			nss_lso_rx_stats.o \
+			nss_lso_rx_strings.o \
+			nss_meminfo.o \
+			nss_n2h.o \
+			nss_n2h_stats.o \
+			nss_n2h_strings.o \
+			nss_phys_if.o \
+			nss_pm.o \
+			nss_profiler.o \
+			nss_project.o \
+			nss_pppoe.o \
+			nss_pppoe_log.o \
+			nss_pppoe_stats.o \
+			nss_pppoe_strings.o \
+			nss_rps.o \
+			nss_stats.o \
+			nss_strings.o \
+			nss_tx_msg_sync.o \
+			nss_unaligned.o \
+			nss_unaligned_log.o \
+			nss_unaligned_stats.o \
+			nss_virt_if.o \
+			nss_virt_if_stats.o \
+			nss_vlan.o \
+			nss_vlan_log.o \
+			nss_wifi.o \
+			nss_wifi_log.o \
+			nss_wifi_stats.o \
+			nss_wifi_vdev.o \
+			nss_wifili.o \
+			nss_wifili_log.o \
+			nss_wifili_stats.o \
+			nss_wifili_strings.o \
+			nss_wifi_mac_db.o
+
+# Base NSS data plane/HAL support
+qca-nss-drv-objs += nss_data_plane/nss_data_plane_common.o
+qca-nss-drv-objs += nss_hal/nss_hal.o
+
+ifneq "$(NSS_DRV_BRIDGE_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_BRIDGE_ENABLE
+qca-nss-drv-objs += \
+		    nss_bridge.o \
+		    nss_bridge_log.o
+endif
+
+ifneq "$(NSS_DRV_WIFI_EXT_VDEV_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_WIFI_EXT_VDEV_ENABLE
+qca-nss-drv-objs += \
+		    nss_wifi_ext_vdev.o \
+		    nss_wifi_ext_vdev_stats.o \
+		    nss_wifi_ext_vdev_log.o
+endif
+
+ifneq "$(NSS_DRV_WIFI_MESH_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_WIFI_MESH_ENABLE
+qca-nss-drv-objs += \
+		    nss_wifi_mesh.o \
+		    nss_wifi_mesh_log.o \
+		    nss_wifi_mesh_stats.o \
+		    nss_wifi_mesh_strings.o
+endif
+
+ifneq "$(NSS_DRV_IPV4_REASM_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_IPV4_REASM_ENABLE
+qca-nss-drv-objs += \
+		    nss_ipv4_reasm.o \
+		    nss_ipv4_reasm_stats.o \
+		    nss_ipv4_reasm_strings.o
+endif
+
+ifneq "$(NSS_DRV_L2TP_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_L2TP_ENABLE
+qca-nss-drv-objs += \
+		   nss_l2tpv2.o \
+		   nss_l2tpv2_log.o \
+		   nss_l2tpv2_stats.o \
+		   nss_l2tpv2_strings.o
+endif
+
+ifneq "$(NSS_DRV_LAG_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_LAG_ENABLE
+qca-nss-drv-objs += \
+		   nss_lag.o \
+		   nss_lag_log.o
+endif
+
+ifneq "$(NSS_DRV_PVXLAN_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_PVXLAN_ENABLE
+qca-nss-drv-objs += \
+			 nss_pvxlan.o \
+			 nss_pvxlan_log.o \
+			 nss_pvxlan_stats.o
+endif
+
+ifneq "$(NSS_DRV_IPV6_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_IPV6_ENABLE
+qca-nss-drv-objs += \
+			nss_ipv6.o \
+			nss_ipv6_stats.o \
+			nss_ipv6_strings.o \
+			nss_ipv6_log.o
+ifneq "$(NSS_DRV_IPV6_REASM_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_IPV6_REASM_ENABLE
+qca-nss-drv-objs += \
+		    nss_ipv6_reasm.o \
+		    nss_ipv6_reasm_stats.o \
+		    nss_ipv6_reasm_strings.o
+endif
+endif
+
+ifneq "$(NSS_DRV_TSTAMP_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_TSTAMP_ENABLE
+qca-nss-drv-objs += \
+			 nss_tstamp.o \
+			 nss_tstamp_stats.o
+endif
+
+ifneq "$(NSS_DRV_GRE_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_GRE_ENABLE
+qca-nss-drv-objs += \
+			 nss_gre.o \
+			 nss_gre_log.o \
+			 nss_gre_stats.o \
+			 nss_gre_strings.o
+endif
+
+ifneq "$(NSS_DRV_GRE_REDIR_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_GRE_REDIR_ENABLE
+qca-nss-drv-objs += \
+			 nss_gre_redir.o \
+			 nss_gre_redir_log.o \
+			 nss_gre_redir_lag_ds.o \
+			 nss_gre_redir_lag_ds_log.o \
+			 nss_gre_redir_lag_ds_stats.o \
+			 nss_gre_redir_lag_ds_strings.o \
+			 nss_gre_redir_lag_us.o \
+			 nss_gre_redir_lag_us_log.o \
+			 nss_gre_redir_lag_us_stats.o \
+			 nss_gre_redir_lag_us_strings.o \
+			 nss_gre_redir_stats.o \
+			 nss_gre_redir_strings.o \
+			 nss_gre_redir_mark.o \
+			 nss_gre_redir_mark_log.o \
+			 nss_gre_redir_mark_stats.o \
+			 nss_gre_redir_mark_strings.o
+endif
+
+ifneq "$(NSS_DRV_GRE_TUNNEL_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_GRE_TUNNEL_ENABLE
+qca-nss-drv-objs += \
+			 nss_gre_tunnel.o \
+			 nss_gre_tunnel_log.o \
+			 nss_gre_tunnel_stats.o \
+			 nss_gre_tunnel_strings.o
+endif
+
+ifneq "$(NSS_DRV_CAPWAP_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_CAPWAP_ENABLE
+qca-nss-drv-objs += \
+			 nss_capwap.o \
+			 nss_capwap_log.o \
+			 nss_capwap_stats.o \
+			 nss_capwap_strings.o
+endif
+
+ifneq "$(NSS_DRV_MAPT_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_MAPT_ENABLE
+qca-nss-drv-objs += \
+			 nss_map_t.o \
+			 nss_map_t_log.o \
+			 nss_map_t_stats.o \
+			 nss_map_t_strings.o
+endif
+
+ifneq "$(NSS_DRV_PPTP_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_PPTP_ENABLE
+qca-nss-drv-objs += \
+			 nss_pptp.o \
+			 nss_pptp_log.o \
+			 nss_pptp_stats.o \
+			 nss_pptp_strings.o
+endif
+
+ifneq "$(NSS_DRV_SHAPER_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_SHAPER_ENABLE
+qca-nss-drv-objs += \
+			 nss_shaper.o
+endif
+
+ifneq "$(NSS_DRV_SJACK_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_SJACK_ENABLE
+qca-nss-drv-objs += \
+			 nss_sjack.o \
+			 nss_sjack_log.o \
+			 nss_sjack_stats.o
+endif
+
+ifneq "$(NSS_DRV_TUN6RD_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_TUN6RD_ENABLE
+qca-nss-drv-objs += \
+			 nss_tun6rd.o \
+			 nss_tun6rd_log.o
+endif
+
+ifneq "$(NSS_DRV_TRUSTSEC_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_TRUSTSEC_ENABLE
+qca-nss-drv-objs += \
+			 nss_trustsec_tx.o \
+			 nss_trustsec_tx_log.o \
+			 nss_trustsec_tx_stats.o
+endif
+
+ifneq "$(NSS_DRV_TUNIPIP6_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_TUNIPIP6_ENABLE
+qca-nss-drv-objs += \
+			 nss_tunipip6.o \
+			 nss_tunipip6_log.o \
+			 nss_tunipip6_stats.o
+endif
+
+ifneq "$(NSS_DRV_QRFS_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_QRFS_ENABLE
+qca-nss-drv-objs += \
+			 nss_qrfs.o \
+			 nss_qrfs_log.o \
+			 nss_qrfs_stats.o
+endif
+
+ifneq "$(NSS_DRV_RMNET_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_RMNET_ENABLE
+qca-nss-drv-objs += \
+			 nss_rmnet_rx.o \
+			 nss_rmnet_rx_stats.o
+endif
+
+ifneq "$(NSS_DRV_PORTID_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_PORTID_ENABLE
+qca-nss-drv-objs += \
+			 nss_portid.o \
+			 nss_portid_log.o \
+			 nss_portid_stats.o
+endif
+
+ifneq "$(NSS_DRV_IGS_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_IGS_ENABLE
+qca-nss-drv-objs += \
+			 nss_igs.o \
+			 nss_igs_stats.o
+endif
+
+ifneq "$(NSS_DRV_OAM_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_OAM_ENABLE
+qca-nss-drv-objs += \
+			 nss_oam.o \
+			 nss_oam_log.o
+endif
+
+ifneq "$(NSS_DRV_CLMAP_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_CLMAP_ENABLE
+qca-nss-drv-objs += \
+			 nss_clmap.o \
+			 nss_clmap_log.o \
+			 nss_clmap_stats.o \
+			 nss_clmap_strings.o
+endif
+
+
+ifneq "$(NSS_DRV_VXLAN_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_VXLAN_ENABLE
+qca-nss-drv-objs += \
+			 nss_vxlan.o \
+			 nss_vxlan_log.o \
+			 nss_vxlan_stats.o
+endif
+
+ifneq "$(NSS_DRV_MATCH_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_MATCH_ENABLE
+qca-nss-drv-objs += \
+			nss_match.o \
+			nss_match_log.o \
+			nss_match_stats.o \
+			nss_match_strings.o
+endif
+
+ifneq "$(NSS_DRV_MIRROR_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_MIRROR_ENABLE
+qca-nss-drv-objs += \
+			nss_mirror.o \
+			nss_mirror_log.o \
+			nss_mirror_stats.o \
+			nss_mirror_strings.o
+endif
+
+ifneq "$(NSS_DRV_UDP_ST_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_UDP_ST_ENABLE
+qca-nss-drv-objs += \
+			nss_udp_st.o \
+			nss_udp_st_log.o \
+			nss_udp_st_stats.o \
+			nss_udp_st_strings.o
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq806x))
+qca-nss-drv-objs += nss_data_plane/nss_data_plane_gmac.o \
+		    nss_hal/ipq806x/nss_hal_pvt.o
+
+ifneq "$(NSS_DRV_C2C_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_C2C_ENABLE
+qca-nss-drv-objs += \
+			 nss_c2c_tx.o \
+			 nss_c2c_tx_log.o \
+			 nss_c2c_tx_stats.o \
+			 nss_c2c_tx_strings.o \
+			 nss_c2c_rx.o \
+			 nss_c2c_rx_stats.o \
+			 nss_c2c_rx_strings.o
+endif
+ifneq "$(NSS_DRV_IPSEC_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_IPSEC_ENABLE
+qca-nss-drv-objs += \
+		    nss_ipsec_log.o \
+		    nss_ipsec.o
+endif
+
+ifneq "$(NSS_DRV_CRYPTO_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_CRYPTO_ENABLE
+qca-nss-drv-objs += \
+		    nss_crypto.o \
+		    nss_crypto_log.o
+endif
+
+ifneq "$(NSS_DRV_DTLS_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_DTLS_ENABLE
+qca-nss-drv-objs += \
+		    nss_dtls.o \
+		    nss_dtls_log.o \
+		    nss_dtls_stats.o
+endif
+ccflags-y += -I$(obj)/nss_hal/ipq806x -DNSS_HAL_IPQ806X_SUPPORT
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq60xx ipq60xx_64 ipq807x ipq807x_64))
+qca-nss-drv-objs += nss_data_plane/nss_data_plane.o \
+					nss_edma.o \
+					nss_edma_stats.o \
+					nss_edma_strings.o \
+					nss_ppe.o \
+					nss_ppe_log.o \
+					nss_ppe_stats.o \
+					nss_ppe_strings.o \
+					nss_ppe_vp.o \
+					nss_ppe_vp_log.o \
+					nss_ppe_vp_stats.o
+
+ccflags-y += -DNSS_DRV_PPE_ENABLE
+ccflags-y += -DNSS_DRV_EDMA_ENABLE
+
+ifneq "$(NSS_DRV_IPSEC_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_IPSEC_ENABLE
+qca-nss-drv-objs += \
+		    nss_ipsec_cmn_log.o \
+		    nss_ipsec_cmn.o \
+		    nss_ipsec_cmn_stats.o \
+		    nss_ipsec_cmn_strings.o
+endif
+
+ifneq "$(NSS_DRV_CRYPTO_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_CRYPTO_ENABLE
+ccflags-y += -DNSS_DRV_DMA_ENABLE
+
+qca-nss-drv-objs += \
+		    nss_crypto_cmn.o \
+		    nss_crypto_cmn_log.o \
+		    nss_crypto_cmn_stats.o \
+		    nss_crypto_cmn_strings.o \
+		    nss_dma.o \
+		    nss_dma_log.o \
+		    nss_dma_stats.o \
+		    nss_dma_strings.o
+endif
+
+ifneq "$(NSS_DRV_DTLS_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_DTLS_ENABLE
+qca-nss-drv-objs += \
+		    nss_dtls_cmn.o \
+		    nss_dtls_cmn_log.o \
+		    nss_dtls_cmn_stats.o \
+		    nss_dtls_cmn_strings.o
+endif
+
+ifneq "$(NSS_DRV_QVPN_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_QVPN_ENABLE
+qca-nss-drv-objs += \
+	     nss_qvpn.o \
+	     nss_qvpn_log.o \
+	     nss_qvpn_stats.o \
+	     nss_qvpn_strings.o
+endif
+ifneq "$(NSS_DRV_TLS_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_TLS_ENABLE
+qca-nss-drv-objs += \
+		     nss_tls.o \
+		     nss_tls_log.o \
+		     nss_tls_stats.o \
+		     nss_tls_strings.o
+endif
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64))
+qca-nss-drv-objs += nss_hal/ipq807x/nss_hal_pvt.o \
+		    nss_data_plane/hal/nss_ipq807x.o
+ifneq "$(NSS_DRV_C2C_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_C2C_ENABLE
+qca-nss-drv-objs += \
+			 nss_c2c_tx.o \
+			 nss_c2c_tx_log.o \
+			 nss_c2c_tx_stats.o \
+			 nss_c2c_tx_strings.o \
+			 nss_c2c_rx.o \
+			 nss_c2c_rx_stats.o \
+			 nss_c2c_rx_strings.o
+endif
+ccflags-y += -I$(obj)/nss_hal/ipq807x -DNSS_HAL_IPQ807x_SUPPORT -DNSS_MULTI_H2N_DATA_RING_SUPPORT
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq60xx ipq60xx_64))
+qca-nss-drv-objs += nss_hal/ipq60xx/nss_hal_pvt.o \
+		    nss_data_plane/hal/nss_ipq60xx.o
+ccflags-y += -I$(obj)/nss_hal/ipq60xx -DNSS_HAL_IPQ60XX_SUPPORT -DNSS_MULTI_H2N_DATA_RING_SUPPORT
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq50xx ipq50xx_64))
+qca-nss-drv-objs += nss_data_plane/nss_data_plane.o \
+		    nss_hal/ipq50xx/nss_hal_pvt.o \
+		    nss_data_plane/hal/nss_ipq50xx.o
+
+ifneq "$(NSS_DRV_IPSEC_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_IPSEC_ENABLE
+qca-nss-drv-objs += \
+		    nss_ipsec_cmn_log.o \
+		    nss_ipsec_cmn.o \
+		    nss_ipsec_cmn_stats.o \
+		    nss_ipsec_cmn_strings.o
+endif
+
+ifneq "$(NSS_DRV_CRYPTO_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_CRYPTO_ENABLE
+qca-nss-drv-objs += \
+		    nss_crypto_cmn.o \
+		    nss_crypto_cmn_log.o \
+		    nss_crypto_cmn_stats.o \
+		    nss_crypto_cmn_strings.o
+endif
+
+ifneq "$(NSS_DRV_DTLS_ENABLE)" "n"
+ccflags-y += -DNSS_DRV_DTLS_ENABLE
+qca-nss-drv-objs += \
+		    nss_dtls_cmn.o \
+		    nss_dtls_cmn_log.o \
+		    nss_dtls_cmn_stats.o \
+		    nss_dtls_cmn_strings.o
+endif
+ccflags-y += -I$(obj)/nss_hal/ipq50xx -DNSS_HAL_IPQ50XX_SUPPORT -DNSS_MULTI_H2N_DATA_RING_SUPPORT
+endif
+
+ccflags-y += -I$(obj)/nss_hal/include -I$(obj)/nss_data_plane/include -I$(obj)/exports -DNSS_DEBUG_LEVEL=0 -DNSS_PKT_STATS_ENABLED=1
+ccflags-y += -I$(obj)/nss_data_plane/hal/include
+ccflags-y += -DNSS_PM_DEBUG_LEVEL=0 -DNSS_SKB_REUSE_SUPPORT=1
+ccflags-y += -Werror
+
+KERNELVERSION := $(word 1, $(subst ., ,$(KERNELVERSION))).$(word 2, $(subst ., ,$(KERNELVERSION)))
+
+ifneq ($(findstring 3.4, $(KERNELVERSION)),)
+NSS_CCFLAGS = -DNSS_DT_SUPPORT=0 -DNSS_FW_DBG_SUPPORT=1 -DNSS_PM_SUPPORT=1
+else
+NSS_CCFLAGS = -DNSS_DT_SUPPORT=1 -DNSS_FW_DBG_SUPPORT=0 -DNSS_PM_SUPPORT=0
+
+ccflags-y += -I$(obj)
+endif
+
+# Fabric scaling is supported in 3.14 and 4.4 only
+ifneq ($(findstring 3.14, $(KERNELVERSION)),)
+NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=1
+else ifneq ($(findstring 4.4, $(KERNELVERSION)),)
+NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=1
+else
+NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=0
+endif
+
+# Disable Frequency scaling
+ifeq "$(NSS_FREQ_SCALE_DISABLE)" "y"
+ccflags-y += -DNSS_FREQ_SCALE_SUPPORT=0
+else
+qca-nss-drv-objs += \
+			nss_freq.o \
+			nss_freq_log.o \
+			nss_freq_stats.o
+ccflags-y += -DNSS_FREQ_SCALE_SUPPORT=1
+endif
+
+ccflags-y += $(NSS_CCFLAGS)
+
+export NSS_CCFLAGS
+
+obj ?= .
diff --git a/qca-nss-drv/Makefile.fsm b/qca-nss-drv/Makefile.fsm
new file mode 100644
index 0000000..93ca007
--- /dev/null
+++ b/qca-nss-drv/Makefile.fsm
@@ -0,0 +1,123 @@
+# ###################################################
+# # Makefile for the NSS driver
+# ###################################################
+obj-m += qca-nss-drv.o
+
+#
+# List the files that belong to the driver in alphabetical order.
+#
+qca-nss-drv-objs := \
+			nss_bridge.o \
+			nss_bridge_log.o \
+			nss_capwap.o \
+			nss_capwap_log.o \
+			nss_capwap_stats.o \
+			nss_cmn.o \
+			nss_core.o \
+			nss_coredump.o \
+			nss_crypto.o \
+			nss_crypto_log.o \
+			nss_dtls.o \
+			nss_dtls_log.o \
+			nss_dtls_stats.o \
+			nss_dynamic_interface.o \
+			nss_dynamic_interface_log.o \
+			nss_edma.o \
+			nss_edma_stats.o \
+			nss_eth_rx.o \
+			nss_eth_rx_stats.o \
+			nss_gre.o \
+			nss_gre_log.o \
+			nss_gre_stats.o \
+			nss_gre_redir.o \
+			nss_gre_redir_log.o \
+			nss_gre_redir_stats.o \
+			nss_gre_tunnel.o \
+			nss_gre_tunnel_log.o \
+			nss_gre_tunnel_stats.o \
+			nss_if.o \
+                        nss_if_log.o \
+			nss_init.o \
+			nss_ipsec.o \
+			nss_ipsec_log.o \
+			nss_ipv4.o \
+			nss_ipv4_stats.o \
+			nss_ipv4_log.o \
+			nss_ipv4_reasm.o \
+			nss_ipv4_reasm_stats.o \
+			nss_ipv6.o \
+			nss_ipv6_stats.o \
+			nss_ipv6_log.o \
+			nss_ipv6_reasm.o \
+			nss_ipv6_reasm_stats.o \
+			nss_l2tpv2.o \
+			nss_l2tpv2_log.o \
+			nss_l2tpv2_stats.o \
+			nss_lag.o \
+			nss_lag_log.o \
+			nss_log.o \
+			nss_lso_rx.o \
+			nss_lso_rx_stats.o \
+			nss_map_t.o \
+			nss_map_t_log.o \
+			nss_map_t_stats.o \
+			nss_n2h.o \
+			nss_n2h_stats.o \
+			nss_oam.o \
+			nss_oam_log.o \
+			nss_phys_if.o \
+			nss_pm.o \
+			nss_profiler.o \
+			nss_portid.o \
+			nss_portid_log.o \
+			nss_portid_stats.o \
+			nss_ppe.o \
+			nss_ppe_log.o \
+			nss_ppe_stats.o \
+			nss_pppoe.o \
+			nss_pppoe_log.o \
+			nss_pppoe_stats.o \
+			nss_pptp.o \
+			nss_pptp_log.o \
+			nss_pptp_stats.o \
+			nss_rps.o \
+			nss_shaper.o \
+			nss_sjack.o \
+			nss_sjack_log.o \
+			nss_sjack_stats.o \
+			nss_stats.o \
+			nss_tstamp.o \
+			nss_tstamp_stats.o \
+			nss_tun6rd.o \
+			nss_tun6rd_log.o \
+			nss_trustsec_tx.o \
+			nss_trustsec_tx_log.o \
+			nss_trustsec_tx_stats.o \
+			nss_tunipip6.o \
+			nss_tunipip6_log.o \
+			nss_unaligned.o \
+			nss_unaligned_log.o \
+			nss_unaligned_stats.o \
+			nss_virt_if.o \
+			nss_virt_if_stats.o \
+			nss_vlan.o \
+			nss_vlan_log.o \
+			nss_wifi.o \
+			nss_wifi_log.o \
+			nss_wifi_stats.o \
+			nss_wifi_if.o \
+			nss_wifi_if_stats.o \
+			nss_wifi_vdev.o
+
+qca-nss-drv-objs += nss_hal/nss_hal.o
+qca-nss-drv-objs += nss_hal/fsm9010/nss_hal_pvt.o
+qca-nss-drv-objs += nss_data_plane/nss_data_plane_common.o
+qca-nss-drv-objs += nss_data_plane/nss_data_plane_gmac.o
+
+ccflags-y += -I$(obj)/nss_hal/include
+ccflags-y += -I$(obj)/nss_data_plane/include
+ccflags-y += -I$(obj)/exports
+ccflags-y += -I$(obj)/nss_hal/fsm9010 -DNSS_HAL_FSM9010_SUPPORT
+ccflags-y += -DNSS_DEBUG_LEVEL=0 -DNSS_PKT_STATS_ENABLED=1
+ccflags-y += -DNSS_DT_SUPPORT=1 -DNSS_PM_SUPPORT=0 -DNSS_FW_DBG_SUPPORT=0 -DNSS_SKB_REUSE_SUPPORT=0
+ccflags-y += -DNSS_PPP_SUPPORT=0 -DNSS_FREQ_SCALE_SUPPORT=0 -DNSS_FABRIC_SCALING_SUPPORT=0
diff --git a/qca-nss-drv/build.sh b/qca-nss-drv/build.sh
new file mode 100755
index 0000000..9afc226
--- /dev/null
+++ b/qca-nss-drv/build.sh
@@ -0,0 +1,104 @@
+#!/bin/bash
+
+set -e
+set -o errtrace
+trap 'echo Fatal error: script $0 aborting at line $LINENO, command \"$BASH_COMMAND\" returned $?; exit 1' ERR
+
+PRODUCT_LIST="sirocco"
+
+NUM_JOBS=$(grep -c processor /proc/cpuinfo)
+
+MODULE_NAME="qca-nss-drv"
+###################################################
+# Setup build toollchain
+###################################################
+sdk_top_dir=$(readlink -e $(dirname $0)/..)
+TOP_DIR=$(readlink -e ${sdk_top_dir}/..)
+
+#export ARCH and build related envs.
+source ${TOP_DIR}/sdk/build_scripts/setup_env.sh
+
+kernel_path=$(readlink -e ${sdk_top_dir}/../kernel)
+qca_ssdk_include_path=$(readlink -e ${sdk_top_dir}/qca-ssdk/include)
+qca_ssdk_common_path=$(readlink -e ${sdk_top_dir}/qca-ssdk/include/common)
+qca_ssdk_sal_path=$(readlink -e ${sdk_top_dir}/qca-ssdk/include/sal/os)
+qca_ssdk_sal_linux_path=$(readlink -e ${sdk_top_dir}/qca-ssdk/include/sal/os/linux)
+qca_nss_dp_path=$(readlink -e ${sdk_top_dir}/qca-nss-dp/exports)
+qca_nss_dp_dependency=$(readlink -e ${sdk_top_dir}/qca-nss-dp)
+soc_type=ipq50xx
+
+extra_cflags="-I${qca_ssdk_include_path} -I${qca_ssdk_common_path} -I${qca_ssdk_sal_path} -I${qca_ssdk_sal_linux_path} -I${qca_nss_dp_path}"
+
+##################################################
+# Build Kernel Module
+##################################################
+function BuildKModule() {
+    # make kernel module
+    echo "Build ${MODULE_NAME}"
+    ${CROSS_MAKE} -C ${kernel_path} M=${sdk_top_dir}/${MODULE_NAME} SoC=${soc_type} EXTRA_CFLAGS="${extra_cflags}" KBUILD_EXTRA_SYMBOLS=${qca_nss_dp_dependency}/Module.symvers V=1
+}
+
+##################################################
+# Build & Install
+##################################################
+function BuildAndInstall() {
+    local product=$1
+    local eureka_src_path=$(readlink -e $2)
+    if [ -z ${eureka_src_path} ]; then
+      echo "eureka_src_path doesn't exist"
+      exit 1
+    fi
+
+    # clean previous build
+    find . -name "*.o" -delete
+    find . -name "*.cmd" -delete
+    find . -name "*.ko" -delete
+    find . -name "*.mod.*" -delete
+    find . -name "*.mod" -delete
+    find . -name Module.symvers -delete
+
+    # build module
+    BuildKModule
+
+    # install module
+    echo "Install ${MODULE_NAME}.ko"
+    local module_target_dir="$(GetModulePath ${eureka_src_path} ${product})"
+    mkdir -p ${module_target_dir}
+    cp -f ${MODULE_NAME}.ko ${module_target_dir}/.
+}
+
+function Usage() {
+    cat << EOF
+Usage:
+    $0 <product> <eureka_src_path>
+    Valid products: ${PRODUCT_LIST}
+EOF
+}
+
+function IsProductValid() {
+  local product
+  local ret=1
+
+  for product in ${PRODUCT_LIST}; do
+    if [ "${product}" == "$1" ]; then
+      ret=0
+      break
+    fi
+  done
+
+  return ${ret}
+}
+
+#########################
+####### Main Entry ######
+#########################
+if (( $# < 2 )); then
+  Usage
+else
+  if IsProductValid $1; then
+    BuildAndInstall $1 $2
+  else
+    echo "$1 is a invalid product"
+    Usage
+  fi
+fi
diff --git a/qca-nss-drv/exports/arch/nss_fsm9010.h b/qca-nss-drv/exports/arch/nss_fsm9010.h
new file mode 100644
index 0000000..7e47290
--- /dev/null
+++ b/qca-nss-drv/exports/arch/nss_fsm9010.h
@@ -0,0 +1,43 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_fsm9010.h
+ *	Architecture dependent parameters.
+ */
+#ifndef __NSS_FSM9010_H
+#define __NSS_FSM9010_H
+
+/**
+ * @addtogroup nss_arch_macros_fsm9010
+ * @{
+ */
+
+#define NSS_MAX_NUM_PRI 1		/**< Maximum number of priority queues in NSS. */
+#define NSS_HOST_CORES 4		/**< Number of host cores. */
+
+#define NSS_N2H_RING_COUNT 3		/**< Number of N2H rings. */
+#define NSS_H2N_RING_COUNT 4		/**< Number of H2N rings. */
+#define NSS_RING_SIZE	128		/**< Ring size. */
+
+#define NSS_IMEM_START 0xE4000000	/**< NSS IMEM start address. */
+#define NSS_IMEM_SIZE  0x10000		/**< NSS IMEM size. */
+
+/**
+ * @}
+ */
+
+#endif /** __NSS_FSM9010_H */
diff --git a/qca-nss-drv/exports/arch/nss_ipq40xx.h b/qca-nss-drv/exports/arch/nss_ipq40xx.h
new file mode 100644
index 0000000..d6d3351
--- /dev/null
+++ b/qca-nss-drv/exports/arch/nss_ipq40xx.h
@@ -0,0 +1,43 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipq40xx.h
+ *	Architecture dependent parameters.
+ */
+#ifndef __NSS_IPQ40XX_H
+#define __NSS_IPQ40XX_H
+
+/**
+ * @addtogroup nss_arch_macros_ipq40xx
+ * @{
+ */
+
+#define NSS_MAX_NUM_PRI 1		/**< Maximum number of priority queues in NSS. */
+#define NSS_HOST_CORES 4		/**< Number of host cores. */
+
+#define NSS_N2H_RING_COUNT 0		/**< Number of N2H rings. */
+#define NSS_H2N_RING_COUNT 0		/**< Number of H2N rings. */
+#define NSS_RING_SIZE	128		/**< Ring size. */
+
+#define NSS_IMEM_START	0x39000000	/**< NSS IMEM start address. */
+#define NSS_IMEM_SIZE	0x10000		/**< NSS IMEM size per core. */
+
+/**
+ * @}
+ */
+
+#endif /** __NSS_IPQ40XX_H */
diff --git a/qca-nss-drv/exports/arch/nss_ipq50xx.h b/qca-nss-drv/exports/arch/nss_ipq50xx.h
new file mode 100644
index 0000000..e83649f
--- /dev/null
+++ b/qca-nss-drv/exports/arch/nss_ipq50xx.h
@@ -0,0 +1,40 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipq50xx.h
+ *	Architecture dependent parameters.
+ */
+#ifndef __NSS_IPQ50XX_H
+#define __NSS_IPQ50XX_H
+
+/**
+ * @addtogroup nss_arch_macros_ipq50xx
+ * @{
+ */
+
+#define NSS_MAX_NUM_PRI 4		/**< Maximum number of priority queues in NSS. */
+#define NSS_HOST_CORES 2		/**< Number of host cores. */
+
+#define NSS_N2H_RING_COUNT 3		/**< Number of N2H rings. */
+#define NSS_H2N_RING_COUNT 7		/**< Number of H2N rings. */
+#define NSS_RING_SIZE	128		/**< Ring size. */
+
+/**
+ * @}
+ */
+
+#endif /** __NSS_IPQ50XX_H */
diff --git a/qca-nss-drv/exports/arch/nss_ipq50xx_64.h b/qca-nss-drv/exports/arch/nss_ipq50xx_64.h
new file mode 100644
index 0000000..b756c5a
--- /dev/null
+++ b/qca-nss-drv/exports/arch/nss_ipq50xx_64.h
@@ -0,0 +1,40 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipq50xx_64.h
+ *	Architecture dependent parameters.
+ */
+#ifndef __NSS_IPQ50XX_64_H
+#define __NSS_IPQ50XX_64_H
+
+/**
+ * @addtogroup nss_arch_macros_ipq50xx_64
+ * @{
+ */
+
+#define NSS_MAX_NUM_PRI 4		/**< Maximum number of priority queues in NSS. */
+#define NSS_HOST_CORES 2		/**< Number of host cores. */
+
+#define NSS_N2H_RING_COUNT 3		/**< Number of N2H rings. */
+#define NSS_H2N_RING_COUNT 7		/**< Number of H2N rings. */
+#define NSS_RING_SIZE	128		/**< Ring size. */
+
+/**
+ * @}
+ */
+
+#endif /** __NSS_IPQ50XX_64_H */
diff --git a/qca-nss-drv/exports/arch/nss_ipq60xx.h b/qca-nss-drv/exports/arch/nss_ipq60xx.h
new file mode 100644
index 0000000..bc0396a
--- /dev/null
+++ b/qca-nss-drv/exports/arch/nss_ipq60xx.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipq60xx.h
+ *	Architecture dependent parameters.
+ */
+#ifndef __NSS_IPQ60XX_H
+#define __NSS_IPQ60XX_H
+
+/**
+ * @addtogroup nss_arch_macros_ipq60xx
+ * @{
+ */
+
+#define NSS_MAX_NUM_PRI 4		/**< Maximum number of priority queues in NSS. */
+#define NSS_HOST_CORES 4		/**< Number of host cores. */
+#define NSS_PPE_SUPPORTED		/**< PPE supported flag. */
+
+#define NSS_N2H_RING_COUNT 5		/**< Number of N2H rings. */
+#define NSS_H2N_RING_COUNT 11		/**< Number of H2N rings. */
+#define NSS_RING_SIZE	128		/**< Ring size. */
+
+/**
+ * @}
+ */
+
+#endif /** __NSS_IPQ60XX_H */
diff --git a/qca-nss-drv/exports/arch/nss_ipq60xx_64.h b/qca-nss-drv/exports/arch/nss_ipq60xx_64.h
new file mode 100644
index 0000000..a0e5e9e
--- /dev/null
+++ b/qca-nss-drv/exports/arch/nss_ipq60xx_64.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipq60xx_64.h
+ *	Architecture dependent parameters.
+ */
+#ifndef __NSS_IPQ60XX_64_H
+#define __NSS_IPQ60XX_64_H
+
+/**
+ * @addtogroup nss_arch_macros_ipq60xx_64
+ * @{
+ */
+
+#define NSS_MAX_NUM_PRI 4		/**< Maximum number of priority queues in NSS. */
+#define NSS_HOST_CORES 4		/**< Number of host cores. */
+#define NSS_PPE_SUPPORTED		/**< PPE supported flag. */
+
+#define NSS_N2H_RING_COUNT 5		/**< Number of N2H rings. */
+#define NSS_H2N_RING_COUNT 11		/**< Number of H2N rings. */
+#define NSS_RING_SIZE	128		/**< Ring size. */
+
+/**
+ * @}
+ */
+
+#endif /** __NSS_IPQ60XX_64_H */
diff --git a/qca-nss-drv/exports/arch/nss_ipq806x.h b/qca-nss-drv/exports/arch/nss_ipq806x.h
new file mode 100644
index 0000000..216f950
--- /dev/null
+++ b/qca-nss-drv/exports/arch/nss_ipq806x.h
@@ -0,0 +1,43 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipq806x.h
+ *	Architecture dependent parameters.
+ */
+#ifndef __NSS_IPQ806X_H
+#define __NSS_IPQ806X_H
+
+/**
+ * @addtogroup nss_arch_macros_ipq806x
+ * @{
+ */
+
+#define NSS_MAX_NUM_PRI 4		/**< Maximum number of priority queues in NSS. */
+#define NSS_HOST_CORES 2		/**< Number of host cores. */
+
+#define NSS_N2H_RING_COUNT 3		/**< Number of N2H rings. */
+#define NSS_H2N_RING_COUNT 4		/**< Number of H2N rings. */
+#define NSS_RING_SIZE	128		/**< Ring size. */
+
+#define NSS_IMEM_START	0x39000000	/**< NSS IMEM start address. */
+#define NSS_IMEM_SIZE	0x10000		/**< NSS IMEM size per core. */
+
+/**
+ * @}
+ */
+
+#endif /** __NSS_IPQ806X_H */
diff --git a/qca-nss-drv/exports/arch/nss_ipq807x.h b/qca-nss-drv/exports/arch/nss_ipq807x.h
new file mode 100644
index 0000000..c8fc26d
--- /dev/null
+++ b/qca-nss-drv/exports/arch/nss_ipq807x.h
@@ -0,0 +1,44 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipq807x.h
+ *	Architecture dependent parameters.
+ */
+#ifndef __NSS_IPQ807X_H
+#define __NSS_IPQ807X_H
+
+/**
+ * @addtogroup nss_arch_macros_ipq807x
+ * @{
+ */
+
+#define NSS_MAX_NUM_PRI 4		/**< Maximum number of priority queues in NSS. */
+#define NSS_HOST_CORES 4		/**< Number of host cores. */
+#define NSS_PPE_SUPPORTED		/**< PPE supported flag. */
+
+#define NSS_N2H_RING_COUNT 5		/**< Number of N2H rings. */
+#define NSS_H2N_RING_COUNT 11		/**< Number of H2N rings. */
+#define NSS_RING_SIZE	128		/**< Ring size. */
+
+#define NSS_IMEM_START	0x38000000	/**< NSS IMEM start address. */
+#define NSS_IMEM_SIZE	0x30000		/**< NSS IMEM size per core. */
+
+/**
+ * @}
+ */
+
+#endif /** __NSS_IPQ807X_H */
diff --git a/qca-nss-drv/exports/arch/nss_ipq807x_64.h b/qca-nss-drv/exports/arch/nss_ipq807x_64.h
new file mode 100644
index 0000000..fec7aa5
--- /dev/null
+++ b/qca-nss-drv/exports/arch/nss_ipq807x_64.h
@@ -0,0 +1,44 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipq807x_64.h
+ *	Architecture dependent parameters.
+ */
+#ifndef __NSS_IPQ807x_64_H
+#define __NSS_IPQ807x_64_H
+
+/**
+ * @addtogroup nss_arch_macros_ipq807x_64
+ * @{
+ */
+
+#define NSS_MAX_NUM_PRI 4		/**< Maximum number of priority queues in NSS. */
+#define NSS_HOST_CORES 4		/**< Number of host cores. */
+#define NSS_PPE_SUPPORTED		/**< PPE supported flag. */
+
+#define NSS_N2H_RING_COUNT 5		/**< Number of N2H rings. */
+#define NSS_H2N_RING_COUNT 11		/**< Number of H2N rings. */
+#define NSS_RING_SIZE	128		/**< Ring size. */
+
+#define NSS_IMEM_START	0x38000000	/**< NSS IMEM start address. */
+#define NSS_IMEM_SIZE	0x30000		/**< NSS IMEM size per core. */
+
+/**
+ * @}
+ */
+
+#endif /** __NSS_IPQ807x_64_H */
diff --git a/qca-nss-drv/exports/nss_api_if.h b/qca-nss-drv/exports/nss_api_if.h
new file mode 100644
index 0000000..ddf6b7c
--- /dev/null
+++ b/qca-nss-drv/exports/nss_api_if.h
@@ -0,0 +1,319 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_api_if.h
+ *	NSS driver APIs and Declarations.
+ *
+ * This file declares all the public interfaces for NSS driver.
+ */
+
+#ifndef __NSS_API_IF_H
+#define __NSS_API_IF_H
+
+#ifdef __KERNEL__ /* only kernel will use. */
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+#include <linux/if_ether.h>
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+#include "nss_arch.h"
+#include "nss_def.h"
+#include "nss_cmn.h"
+#include "nss_tun6rd.h"
+#include "nss_l2tpv2.h"
+#include "nss_pptp.h"
+#include "nss_map_t.h"
+#include "nss_tunipip6.h"
+#include "nss_lag.h"
+#include "nss_stats_public.h"
+#include "nss_ipv4.h"
+#include "nss_ipv6.h"
+#include "nss_shaper.h"
+#include "nss_if.h"
+#include "nss_phy_if.h"
+#include "nss_virt_if.h"
+#include "nss_pppoe.h"
+#include "nss_crypto.h"
+#include "nss_crypto_cmn.h"
+#include "nss_dma.h"
+
+#include "nss_profiler.h"
+#include "nss_dynamic_interface.h"
+#include "nss_ipsec.h"
+#include "nss_ipsec_cmn.h"
+#include "nss_gre.h"
+#include "nss_gre_redir.h"
+#include "nss_gre_redir_lag.h"
+#include "nss_gre_tunnel.h"
+#include "nss_sjack.h"
+#include "nss_capwap.h"
+#include "nss_wifi.h"
+#include "nss_wifi_vdev.h"
+#include "nss_n2h.h"
+#include "nss_rps.h"
+#include "nss_portid.h"
+#include "nss_oam.h"
+#include "nss_dtls.h"
+#include "nss_dtls_cmn.h"
+#include "nss_tls.h"
+#include "nss_edma.h"
+#include "nss_bridge.h"
+#include "nss_ppe.h"
+#include "nss_trustsec_tx.h"
+#include "nss_vlan.h"
+#include "nss_igs.h"
+#include "nss_mirror.h"
+#include "nss_wifili_if.h"
+#include "nss_project.h"
+#include "nss_qrfs.h"
+#include "nss_c2c_tx.h"
+#include "nss_qvpn.h"
+#include "nss_unaligned.h"
+#include "nss_pvxlan.h"
+#include "nss_vxlan.h"
+#include "nss_pm.h"
+#include "nss_freq.h"
+#include "nss_tstamp.h"
+#include "nss_gre_redir_mark.h"
+#include "nss_clmap.h"
+#include "nss_rmnet_rx.h"
+#include "nss_match.h"
+#include "nss_eth_rx.h"
+#include "nss_c2c_rx.h"
+#include "nss_ipv6_reasm.h"
+#include "nss_ipv4_reasm.h"
+#include "nss_lso_rx.h"
+#include "nss_wifi_mac_db_if.h"
+#include "nss_wifi_ext_vdev_if.h"
+#include "nss_wifili_if.h"
+#include "nss_ppe_vp.h"
+#include "nss_wifi_mesh.h"
+#include "nss_udp_st.h"
+#endif
+
+#endif /*__KERNEL__ */
+
+/**
+ * @addtogroup nss_driver_subsystem
+ * @{
+ */
+
+#define NSS_MAX_CORES 2		/**< Maximum number of core interfaces. */
+
+#define NSS_MAX_DEVICE_INTERFACES (NSS_MAX_PHYSICAL_INTERFACES + NSS_MAX_VIRTUAL_INTERFACES + NSS_MAX_TUNNEL_INTERFACES + NSS_MAX_DYNAMIC_INTERFACES)
+		/**< Maximum number of device interfaces. */
+
+#define NSS_MAX_NET_INTERFACES (NSS_MAX_DEVICE_INTERFACES + NSS_MAX_SPECIAL_INTERFACES)
+		/**< Maximum number of network interfaces. */
+
+#define NSS_MAX_PHYSICAL_INTERFACES 8	/**< Maximum number of physical interfaces. */
+#define NSS_MAX_VIRTUAL_INTERFACES 16	/**< Maximum number of virtual interfaces. */
+#define NSS_MAX_TUNNEL_INTERFACES 4	/**< Maximum number of tunnel interfaces. */
+#define NSS_MAX_SPECIAL_INTERFACES 69	/**< Maximum number of special interfaces. */
+#define NSS_MAX_WIFI_RADIO_INTERFACES 3	/**< Maximum number of radio interfaces. */
+
+/*
+ * Start of individual interface groups
+ */
+#define NSS_PHYSICAL_IF_START 0
+		/**< Beginning of the physical interfaces. */
+
+#define NSS_VIRTUAL_IF_START (NSS_PHYSICAL_IF_START + NSS_MAX_PHYSICAL_INTERFACES)
+		/**< Beginning of the virtual interfaces. */
+
+#define NSS_TUNNEL_IF_START (NSS_VIRTUAL_IF_START + NSS_MAX_VIRTUAL_INTERFACES)
+		/**< Beginning of the tunnel interfaces. */
+
+#define NSS_DYNAMIC_IF_START (NSS_TUNNEL_IF_START + NSS_MAX_TUNNEL_INTERFACES)
+		/**< Beginning of the dynamic interfaces. */
+
+#define NSS_SPECIAL_IF_START (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES)
+		/**< Beginning of the special interfaces. */
+
+/*
+ * Tunnel interface numbers
+ */
+#define NSS_IPSEC_ENCAP_IF_NUMBER (NSS_TUNNEL_IF_START + 0)
+		/**< Tunnel interface number for IPsec encapsulation interfaces. */
+#define NSS_IPSEC_DECAP_IF_NUMBER (NSS_TUNNEL_IF_START + 1)
+		/**< Tunnel interface number for IPsec decapsulation interfaces. */
+#define NSS_TUN6RD_INTERFACE (NSS_TUNNEL_IF_START + 2)
+		/**< Tunnel interface number for TUN6RD interfaces. */
+#define NSS_TUNIPIP6_INTERFACE (NSS_TUNNEL_IF_START + 3)
+		/**< Tunnel interface number for TUNIPIP6 interfaces. */
+
+/*
+ * Special interface numbers
+ */
+#define NSS_N2H_INTERFACE (NSS_SPECIAL_IF_START + 0)
+		/**< Special interface number for N2H. */
+#define NSS_ETH_RX_INTERFACE (NSS_SPECIAL_IF_START + 2)
+		/**< Special interface number for Ethernet Rx. */
+#define NSS_PPPOE_INTERFACE (NSS_SPECIAL_IF_START + 3)
+		/**< Special interface number for PPPoE. */
+#define NSS_IPV4_RX_INTERFACE (NSS_SPECIAL_IF_START + 5)
+		/**< Special interface number for IPv4. */
+#define NSS_IPV6_RX_INTERFACE (NSS_SPECIAL_IF_START + 7)
+		/**< Special interface number for IPv6. */
+#define NSS_PROFILER_INTERFACE (NSS_SPECIAL_IF_START + 8)
+		/**< Special interface number for profile. */
+#define NSS_CRYPTO_INTERFACE (NSS_SPECIAL_IF_START + 9)
+		/**< Special interface number for crypto CE5. */
+#define NSS_DTLS_INTERFACE (NSS_SPECIAL_IF_START + 10)
+		/**< Special interface number for DTLS. */
+#define NSS_CRYPTO_CMN_INTERFACE (NSS_SPECIAL_IF_START + 11)
+		/**< Special interface number for crypto common. */
+#define NSS_C2C_TX_INTERFACE (NSS_SPECIAL_IF_START + 12)
+		/**< Virtual interface number for core-to-core transmissions. */
+#define NSS_C2C_RX_INTERFACE (NSS_SPECIAL_IF_START + 13)
+		/**< Virtual interface number for core-to-core reception. */
+#define NSS_IPSEC_CMN_INTERFACE (NSS_SPECIAL_IF_START + 18)
+		/**< Virtual interface number for IPSec rule. */
+#define NSS_COREFREQ_INTERFACE (NSS_SPECIAL_IF_START + 19)
+		/**< Virtual interface number for core frequency. */
+#define NSS_DYNAMIC_INTERFACE (NSS_SPECIAL_IF_START + 20)
+		/**< Special interface number for dynamic interfaces. */
+#define NSS_GRE_REDIR_INTERFACE (NSS_SPECIAL_IF_START + 21)
+		/**< Special interface number for GRE redirect base interfaces. */
+#define NSS_LSO_RX_INTERFACE (NSS_SPECIAL_IF_START + 22)
+		/**< Special interface number for LSO. */
+#define NSS_SJACK_INTERFACE (NSS_SPECIAL_IF_START + 23)
+		/**< Special interface number for GRE REDIR base interfaces. */
+#define NSS_IPV4_REASM_INTERFACE (NSS_SPECIAL_IF_START + 24)
+		/**< Special interface number for IPv4 reassembly interfaces. */
+#define NSS_DEBUG_INTERFACE (NSS_SPECIAL_IF_START + 25)
+		/**< Special interface number for debug. */
+#define NSS_WIFI_INTERFACE0 (NSS_SPECIAL_IF_START + 26)
+		/**< Special interface number for Wi-Fi radio 0. */
+#define NSS_WIFI_INTERFACE1 (NSS_SPECIAL_IF_START + 27)
+		/**< Special interface number for Wi-Fi radio 1. */
+#define NSS_WIFI_INTERFACE2 (NSS_SPECIAL_IF_START + 28)
+		/**< Special interface number for Wi-Fi radio 2. */
+#define NSS_IPV6_REASM_INTERFACE (NSS_SPECIAL_IF_START + 29)
+		/**< Special interface number for IPv6 reassembly. */
+#define NSS_LAG0_INTERFACE_NUM (NSS_SPECIAL_IF_START + 30)
+		/**< Special interface number for LAG0. */
+#define NSS_LAG1_INTERFACE_NUM (NSS_SPECIAL_IF_START + 31)
+		/**< Special interface number for LAG1. */
+#define NSS_LAG2_INTERFACE_NUM (NSS_SPECIAL_IF_START + 32)
+		/**< Special interface number for LAG2. */
+#define NSS_LAG3_INTERFACE_NUM (NSS_SPECIAL_IF_START + 33)
+		/**< Special interface number for LAG3. */
+#define NSS_L2TPV2_INTERFACE (NSS_SPECIAL_IF_START + 34)
+		/**< Special interface number for L2TPv2 UDP encapsulation. */
+#define NSS_PPTP_INTERFACE (NSS_SPECIAL_IF_START + 36)
+		/**< Special interface number for PPTP-to-decapsulation. */
+#define NSS_PORTID_INTERFACE (NSS_SPECIAL_IF_START + 37)
+		/**< Special interface number for port ID. */
+#define NSS_OAM_INTERFACE (NSS_SPECIAL_IF_START + 38)
+		/**< Special interface number for OAM. */
+#define NSS_MAP_T_INTERFACE (NSS_SPECIAL_IF_START + 39)
+		/**< Special interface number for MAP-T. */
+#define NSS_PPE_INTERFACE (NSS_SPECIAL_IF_START + 40)
+		/**< Special interface number for PPE. */
+#define NSS_EDMA_INTERFACE (NSS_SPECIAL_IF_START + 41)
+		/**< Special interface number for EDMA. */
+#define NSS_GRE_TUNNEL_INTERFACE (NSS_SPECIAL_IF_START + 42)
+		/**< Special interface number for NSS GRE tunnel. */
+#define NSS_TRUSTSEC_TX_INTERFACE (NSS_SPECIAL_IF_START + 43)
+		/**< Special interface number for TrustSec Tx. */
+#define NSS_VAP_INTERFACE (NSS_SPECIAL_IF_START + 44)
+		/**< Special interface number for NSS Wi-Fi VAPs base interfaces. */
+#define NSS_VLAN_INTERFACE (NSS_SPECIAL_IF_START + 45)
+		/**< Special interface number for VLAN. */
+#define NSS_GRE_INTERFACE (NSS_SPECIAL_IF_START + 46)
+		/**< Special interface number for GRE. */
+#define NSS_WIFILI_INTERNAL_INTERFACE (NSS_SPECIAL_IF_START + 47)
+		/**< Special interface number for wifili internal instance. */
+#define NSS_PROJECT_INTERFACE (NSS_SPECIAL_IF_START + 48)
+		/**< Special interface number for project node. */
+#define NSS_PBUF_MGR_FREE_INTERFACE (NSS_SPECIAL_IF_START + 49)
+		/**< Special interface number for PBUF_MGR_FREE node. */
+#define NSS_REDIR_RX_INTERFACE (NSS_SPECIAL_IF_START + 50)
+		/**< Special interface number for 802.3 redirect node. */
+#define NSS_QRFS_INTERFACE (NSS_SPECIAL_IF_START + 51)
+		/**< Special interface number for QRFS. */
+#define NSS_GRE_REDIR_LAG_INTERFACE (NSS_SPECIAL_IF_START + 52)
+		/**< Special interface number for GRE redirect link aggregation interface. */
+#define NSS_UNALIGNED_INTERFACE (NSS_SPECIAL_IF_START + 53)
+		/**< Special interface number for unaligned handler. */
+#define NSS_TSTAMP_TX_INTERFACE (NSS_SPECIAL_IF_START + 54)
+		/**< Special interface number for timestamp transmit. */
+#define NSS_TSTAMP_RX_INTERFACE (NSS_SPECIAL_IF_START + 55)
+		/**< Special interface number for timestamp receive. */
+#define NSS_GRE_REDIR_MARK_INTERFACE (NSS_SPECIAL_IF_START + 56)
+		/**< Special interface number for GRE redirect mark. */
+#define NSS_VXLAN_INTERFACE (NSS_SPECIAL_IF_START + 57)
+		/**< Special interface number for VxLAN handler. */
+#define NSS_RMNET_RX_INTERFACE (NSS_SPECIAL_IF_START + 58)
+		/**< Special interface number for remote wireless wide area network receive handler. */
+#define NSS_WIFILI_EXTERNAL_INTERFACE0 (NSS_SPECIAL_IF_START + 59)
+		/**< Special interface number for first external radio instance. */
+#define NSS_WIFILI_EXTERNAL_INTERFACE1 (NSS_SPECIAL_IF_START + 60)
+		/**< Special interface number for second external radio instance. */
+#define NSS_TLS_INTERFACE (NSS_SPECIAL_IF_START + 61)
+		/**< Special interface number for TLS. */
+#define NSS_PPE_VP_INTERFACE (NSS_SPECIAL_IF_START + 62)
+		/**< Special interface number for the virtual port (62, 63, 64) interface. */
+#define NSS_WIFI_MAC_DB_INTERFACE (NSS_SPECIAL_IF_START + 65)
+		/**< Special interface number for the Wi-Fi MAC database. */
+#define NSS_DMA_INTERFACE (NSS_SPECIAL_IF_START + 66)
+		/**< Special interface number for the DMA interface. */
+#define NSS_WIFI_EXT_VDEV_INTERFACE (NSS_SPECIAL_IF_START + 67)
+		/**< Special interface number for the Wi-Fi extended virtual interface. */
+#define NSS_UDP_ST_INTERFACE (NSS_SPECIAL_IF_START + 68)
+		/**< Special interface number for the UDP speed test interface. */
+
+#ifdef __KERNEL__ /* only kernel will use. */
+
+/*
+ * General utilities
+ */
+
+/**
+ * General callback function for all interface messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_if_rx_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * nss_get_state
+ *	Gets the NSS state.
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ *
+ * @return
+ * NSS state.
+ */
+extern nss_state_t nss_get_state(void *nss_ctx);
+
+#endif /*__KERNEL__ */
+
+/*
+ * Once Everything is arranged correctly, will be placed at top
+ */
+
+/**
+ *@}
+ */
+
+#endif /** __NSS_API_IF_H */
diff --git a/qca-nss-drv/exports/nss_arch.h b/qca-nss-drv/exports/nss_arch.h
new file mode 100644
index 0000000..e83649f
--- /dev/null
+++ b/qca-nss-drv/exports/nss_arch.h
@@ -0,0 +1,40 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipq50xx.h
+ *	Architecture dependent parameters.
+ */
+#ifndef __NSS_IPQ50XX_H
+#define __NSS_IPQ50XX_H
+
+/**
+ * @addtogroup nss_arch_macros_ipq50xx
+ * @{
+ */
+
+#define NSS_MAX_NUM_PRI 4		/**< Maximum number of priority queues in NSS. */
+#define NSS_HOST_CORES 2		/**< Number of host cores. */
+
+#define NSS_N2H_RING_COUNT 3		/**< Number of N2H rings. */
+#define NSS_H2N_RING_COUNT 7		/**< Number of H2N rings. */
+#define NSS_RING_SIZE	128		/**< Ring size. */
+
+/**
+ * @}
+ */
+
+#endif /** __NSS_IPQ50XX_H */
diff --git a/qca-nss-drv/exports/nss_bridge.h b/qca-nss-drv/exports/nss_bridge.h
new file mode 100644
index 0000000..7836969
--- /dev/null
+++ b/qca-nss-drv/exports/nss_bridge.h
@@ -0,0 +1,362 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2018,2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_bridge.h
+ *	NSS Bridge interface definitions.
+ */
+
+#ifndef __NSS_BRIDGE_H
+#define __NSS_BRIDGE_H
+
+/**
+ * @addtogroup nss_bridge_subsystem
+ * @{
+ */
+
+/**
+ * nss_bridge_msg_types
+ *	Message types for the NSS bridge.
+ */
+enum nss_bridge_msg_types {
+	NSS_BRIDGE_MSG_JOIN = NSS_IF_MAX_MSG_TYPES + 1,
+	NSS_BRIDGE_MSG_LEAVE,
+	NSS_BRIDGE_MSG_SET_FDB_LEARN,
+	NSS_BRIDGE_MSG_TYPE_MAX,
+};
+
+/**
+ * nss_bridge_error_types
+ *	Error types for the NSS bridge.
+ */
+enum nss_bridge_error_types {
+	NSS_BRIDGE_ERROR_UNKNOWN_MSG = NSS_IF_ERROR_TYPE_MAX + 1,
+	NSS_BRIDGE_ERROR_TYPE_MAX,
+};
+
+/**
+ * nss_bridge_fdb_learn_mode
+ *	FDB learning mode for the NSS bridge.
+ */
+enum nss_bridge_fdb_learn_mode {
+	NSS_BRIDGE_FDB_LEARN_ENABLE,
+	NSS_BRIDGE_FDB_LEARN_DISABLE,
+	NSS_BRIDGE_FDB_LEARN_MODE_MAX,
+};
+
+/**
+ * nss_bridge_join_msg
+ *	Information for joining the bridge.
+ */
+struct nss_bridge_join_msg {
+	uint32_t if_num;	/**< NSS interface to add to a bridge. */
+};
+
+/**
+ * nss_bridge_leave_msg
+ *	Information for leaving the bridge.
+ */
+struct nss_bridge_leave_msg {
+	uint32_t if_num;	/**< NSS interface to remove from a bridge. */
+};
+
+/**
+ * nss_bridge_set_fdb_learn_msg
+ *	Information for FDB learning status on bridge interface.
+ */
+struct nss_bridge_set_fdb_learn_msg {
+	uint32_t mode;		/**< FDB learning mode of bridge interface. */
+};
+
+/**
+ * nss_bridge_msg
+ *	Data for sending and receiving bridge interface messages.
+ */
+struct nss_bridge_msg {
+	struct nss_cmn_msg cm;	/**< Common message header. */
+
+	/**
+	 * Payload of a bridge interface message.
+	 */
+	union {
+		union nss_if_msgs if_msg;
+				/**< NSS interface base message. */
+		struct nss_bridge_join_msg br_join;
+				/**< Join the bridge. */
+		struct nss_bridge_leave_msg br_leave;
+				/**< Leave the bridge. */
+		struct nss_bridge_set_fdb_learn_msg fdb_learn;
+				/**< FDB learning status of bridge. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * nss_bridge_verify_if_num
+ *	Verifies if the interface is type bridge.
+ *
+ * @param[in] if_num  Interface number to be verified.
+ *
+ * @return
+ * True if if_num is of type bridge.
+ */
+bool nss_bridge_verify_if_num(uint32_t if_num);
+
+/**
+ * nss_bridge_tx_msg
+ *	Sends bridge messages to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_bridge_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_bridge_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_bridge_msg *msg);
+
+/**
+ * nss_bridge_tx_msg_sync
+ *	Sends bridge messages synchronously to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_bridge_msg
+ *
+ * @param[in]     nss_ctx  Pointer to the NSS context.
+ * @param[in,out] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_bridge_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_bridge_msg *msg);
+
+/**
+ * nss_bridge_msg_init
+ *	Initializes a bridge message.
+ *
+ * @datatypes
+ * nss_bridge_msg
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    Interface number
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+void nss_bridge_msg_init(struct nss_bridge_msg *ncm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data);
+
+/**
+ * nss_bridge_get_context
+ *	Gets the bridge context used in nss_bridge_tx.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_bridge_get_context(void);
+
+/**
+ * Callback function for receiving bridge data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_bridge_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for receiving bridge messages.
+ *
+ * @datatypes
+ * nss_bridge_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_bridge_msg_callback_t)(void *app_data, struct nss_bridge_msg *msg);
+
+/**
+ * nss_bridge_register
+ *	Registers the bridge interface with the NSS for sending and receiving
+ *	messages.
+ *
+ * @param[in] if_num          NSS interface number.
+ * @param[in] netdev          Pointer to the associated network device.
+ * @param[in] bridge_data_cb  Callback for the bridge data.
+ * @param[in] bridge_msg_cb   Callback for the bridge message.
+ * @param[in] features        Data socket buffer types supported by this interface.
+ * @param[in] app_data        Pointer to the application context of the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_bridge_register(uint32_t if_num, struct net_device *netdev, nss_bridge_callback_t bridge_data_cb, nss_bridge_msg_callback_t bridge_msg_cb, uint32_t features, void *app_data);
+
+/**
+ * nss_bridge_unregister
+ *	Deregisters the bridge interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ */
+void nss_bridge_unregister(uint32_t if_num);
+
+/**
+ * nss_bridge_notify_register
+ *	Registers a notifier callback for bridge messages with the NSS.
+ *
+ * @datatypes
+ * nss_bridge_msg_callback_t
+ *
+ * @param[in] cb        Callback function for the message.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_bridge_notify_register(nss_bridge_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_bridge_notify_unregister
+ *	Deregisters a bridge message notifier callback from the NSS.
+ *
+ * @return
+ * None.
+ */
+void nss_bridge_notify_unregister(void);
+
+/**
+ * nss_bridge_tx_set_mtu_msg
+ *	Sends a message to the bridge to set the MTU.
+ *
+ * @param[in] bridge_if_num  Interface number of the bridge.
+ * @param[in] mtu            MTU value to set.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_bridge_tx_set_mtu_msg(uint32_t bridge_if_num, uint32_t mtu);
+
+/**
+ * nss_bridge_tx_set_mac_addr_msg
+ *	Sends a message to the bridge to set the MAC address.
+ *
+ * @param[in] bridge_if_num  Interface number of the bridge.
+ * @param[in] addr           Pointer to the MAC address.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_bridge_tx_set_mac_addr_msg(uint32_t bridge_if_num, uint8_t *addr);
+
+/**
+ * nss_bridge_tx_join_msg
+ *	Sends the bridge a message to join with a slave interface.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] bridge_if_num  Interface number of the bridge.
+ * @param[in] netdev         Pointer to the associated network device (the
+ *                           slave interface).
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_bridge_tx_join_msg(uint32_t bridge_if_num, struct net_device *netdev);
+
+/**
+ * nss_bridge_tx_leave_msg
+ *	Sends the bridge a message that the slave interface is leaving the bridge.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] bridge_if_num  Interface number of the bridge.
+ * @param[in] netdev         Pointer to the associated network device (the
+ *                           slave interface).
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_bridge_tx_leave_msg(uint32_t bridge_if_num, struct net_device *netdev);
+
+/**
+ * nss_bridge_tx_vsi_assign_msg
+ *	Sends the bridge a message to assign a VSI.
+ *
+ * @param[in] if_num  Interface number of the bridge.
+ * @param[in] vsi     VSI to assign.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_bridge_tx_vsi_assign_msg(uint32_t if_num, uint32_t vsi);
+
+/**
+ * nss_bridge_tx_vsi_unassign_msg
+ *	Sends the bridge a message to unassign a VSI.
+ *
+ * @param[in] if_num  Interface number of the bridge.
+ * @param[in] vsi     VSI to unassign.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_bridge_tx_vsi_unassign_msg(uint32_t if_num, uint32_t vsi);
+
+/**
+ * nss_bridge_tx_set_fdb_learn_msg
+ *	Sends a message to notify NSS about FDB learning enable/disable event.
+ *
+ * @datatypes
+ * nss_bridge_fdb_learn_mode
+ *
+ * @param[in] bridge_if_num  Interface number of the bridge.
+ * @param[in] fdb_learn      FDB learning disable/enable.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_bridge_tx_set_fdb_learn_msg(uint32_t bridge_if_num, enum nss_bridge_fdb_learn_mode fdb_learn);
+
+/**
+ * nss_bridge_init
+ *	Initializes the bridge.
+ *
+ * @return
+ * None.
+ */
+void nss_bridge_init(void);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_BRIDGE_H */
diff --git a/qca-nss-drv/exports/nss_c2c_rx.h b/qca-nss-drv/exports/nss_c2c_rx.h
new file mode 100644
index 0000000..c7db3a0
--- /dev/null
+++ b/qca-nss-drv/exports/nss_c2c_rx.h
@@ -0,0 +1,86 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_c2c_rx.h
+ *	NSS core-to-core reception interface definitions.
+ */
+
+#ifndef __NSS_C2C_RX_H
+#define __NSS_C2C_RX_H
+
+/**
+ * @addtogroup nss_c2c_rx_subsystem
+ * @{
+ */
+
+/**
+ * nss_c2c_rx_stats_types
+ *	Core-to-core reception node statistics.
+ */
+enum nss_c2c_rx_stats_types {
+	NSS_C2C_RX_STATS_PBUF_SIMPLE = NSS_STATS_NODE_MAX,
+						/**< Number of received simple pbufs. */
+	NSS_C2C_RX_STATS_PBUF_SG,		/**< Number of scatter-gather pbufs received. */
+	NSS_C2C_RX_STATS_PBUF_RETURNING,	/**< Number of returning scatter-gather pbufs. */
+	NSS_C2C_RX_STATS_INVAL_DEST,		/**< Number of pbuf enqueue failures because destination is invalid. */
+	NSS_C2C_RX_STATS_MAX,			/**< Maximum message type. */
+};
+
+/**
+ * nss_c2c_rx_stats_notification
+ *	Core-to-core reception statistics structure.
+ */
+struct nss_c2c_rx_stats_notification {
+	uint32_t core_id;			/**< Core ID. */
+	uint64_t stats[NSS_C2C_RX_STATS_MAX];	/**< Core-to-core reception statistics. */
+};
+
+#ifdef __KERNEL__ /* only kernel will use. */
+/**
+ * nss_c2c_rx_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_c2c_rx_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_c2c_rx_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_c2c_rx_stats_unregister_notifier(struct notifier_block *nb);
+#endif /*__KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_C2C_RX_H */
diff --git a/qca-nss-drv/exports/nss_c2c_tx.h b/qca-nss-drv/exports/nss_c2c_tx.h
new file mode 100644
index 0000000..b7ef0e3
--- /dev/null
+++ b/qca-nss-drv/exports/nss_c2c_tx.h
@@ -0,0 +1,308 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_c2c_tx.h
+ *	NSS core-to-core transmission interface definitions.
+ */
+
+#ifndef __NSS_C2C_TX_H
+#define __NSS_C2C_TX_H
+
+/**
+ * @addtogroup nss_c2c_tx_subsystem
+ * @{
+ */
+
+/**
+ * nss_c2c_tx_msg_type
+ *	Supported message types.
+ */
+enum nss_c2c_tx_msg_type {
+	NSS_C2C_TX_MSG_TYPE_STATS,		/**< Statistics synchronization. */
+	NSS_C2C_TX_MSG_TYPE_TX_MAP,		/**< Open engine synchronization. */
+	NSS_C2C_TX_MSG_TYPE_PERFORMANCE_TEST,	/**< Performance test. */
+	NSS_C2C_TX_MSG_TYPE_MAX			/**< Maximum message type. */
+};
+
+/**
+ * nss_c2c_tx_msg_error
+ *	Message error types.
+ */
+enum nss_c2c_tx_msg_error {
+	NSS_C2C_TX_MSG_ERROR_NONE,		/**< No error. */
+	NSS_C2C_TX_MSG_ERROR_INVAL_OP,		/**< Invalid operation. */
+	NSS_C2C_TX_MSG_ERROR_INVALID_TEST_ID,	/**< Invalid test ID. */
+	NSS_C2C_TX_MSG_ERROR_MAX		/**< Maximum error type. */
+};
+
+/**
+ * nss_c2c_tx_test_type
+ *	Supported core-to core transmission tests.
+ */
+enum nss_c2c_tx_test_type {
+	NSS_C2C_TX_TEST_TYPE_SIMPLE = 1,
+			/**< Tests the performance of simple pbufs. */
+	NSS_C2C_TX_TEST_TYPE_SG_CHAIN,
+			/**< Tests the performance of scatter-gather chain pbufs. */
+	NSS_C2C_TX_TEST_TYPE_SG_REF,
+			/**< Tests the performance of scatter-gather pbuf that has references. */
+	NSS_C2C_TX_TEST_TYPE_SG_REFED,
+			/**< Tests the performance of referenced pbuf. */
+	NSS_C2C_TX_TEST_TYPE_MAX
+			/**< Maximum message type. */
+};
+
+/**
+ * nss_c2c_tx_stats_types
+ *	Core-to-core transmission node statistics.
+ */
+enum nss_c2c_tx_stats_types {
+	NSS_C2C_TX_STATS_PBUF_SIMPLE = NSS_STATS_NODE_MAX,
+						/**< Number of received simple pbufs. */
+	NSS_C2C_TX_STATS_PBUF_SG,		/**< Number of scatter-gather pbufs received. */
+	NSS_C2C_TX_STATS_PBUF_RETURNING,	/**< Number of returning scatter-gather pbufs. */
+	NSS_C2C_TX_STATS_MAX,			/**< Maximum message type. */
+};
+
+/**
+ * nss_c2c_tx_stats_notification
+ *	Core-to-core transmission statistics structure.
+ */
+struct nss_c2c_tx_stats_notification {
+	uint32_t core_id;			/**< Core ID. */
+	uint64_t stats[NSS_C2C_TX_STATS_MAX];	/**< Core-to-core transmission statistics. */
+};
+
+#ifdef __KERNEL__ /* only kernel will use. */
+/**
+ * nss_c2c_tx_map
+ *	Core-to-core transmission queue address and interrupt address.
+ */
+struct nss_c2c_tx_map {
+	uint32_t tx_map;		/**< Peer core core-to-core receiver queue start address. */
+	uint32_t c2c_intr_addr;		/**< Peer core core-to-core interrupt register address. */
+};
+
+/**
+ * nss_c2c_tx_stats
+ *	The NSS core-to-core transmission node statistics structure.
+ */
+struct nss_c2c_tx_stats {
+	struct nss_cmn_node_stats node_stats;
+					/**< Common node statistics for core-to-core transmissions. */
+	uint32_t pbuf_simple;		/**< Number of received simple pbuf. */
+	uint32_t pbuf_sg;		/**< Number of scattered/gathered pbuf received. */
+	uint32_t pbuf_returning;	/**< Number of returning scattered/gathered pbuf. */
+};
+
+/**
+ * nss_c2c_tx_test
+ *	Start performance test for the given test ID.
+ */
+struct nss_c2c_tx_test {
+	uint32_t test_id;		/**< ID of the core-to-core communication test. */
+};
+
+/**
+ * nss_c2c_tx_msg
+ *	Message structure to send/receive core-to-core transmission commands.
+ */
+struct nss_c2c_tx_msg {
+	struct nss_cmn_msg cm;			/**< Common message header. */
+
+	/**
+	 * Payload of a NSS core-to-core transmission rule or statistics message.
+	 */
+	union {
+		struct nss_c2c_tx_map map;	/**< Core-to-core transmissions memory map. */
+		struct nss_c2c_tx_stats stats;	/**< Core-to-core transmissions statistics. */
+		struct nss_c2c_tx_test test;	/**< Core-to-core performance test. */
+	} msg;					/**< Message payload. */
+};
+
+/**
+ * nss_c2c_tx_register_handler
+ *	Registers the core-to-core transmissions message handler.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ *
+ * @return
+ * None.
+ */
+void nss_c2c_tx_register_handler(struct nss_ctx_instance *nss_ctx);
+
+/**
+ * Callback function for receiving core-to-core transmissions messages.
+ *
+ * @datatypes
+ * nss_c2c_tx_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_c2c_tx_msg_callback_t)(void *app_data, struct nss_c2c_tx_msg *msg);
+
+/**
+ * nss_c2c_tx_tx_msg
+ *	Transmits a core-to-core transmissions message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_c2c_tx_msg
+ *
+ * @param[in] nss_ctx   Pointer to the NSS context.
+ * @param[in] nctm      Pointer to the message data.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+extern nss_tx_status_t nss_c2c_tx_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_c2c_tx_msg *nctm);
+
+/**
+ * nss_c2c_tx_msg_init
+ *	Initializes core-to-core transmissions messages.
+ *
+ * @datatypes
+ * nss_c2c_tx_msg \n
+ * nss_c2c_tx_msg_callback_t
+ *
+ * @param[in]     nct       Pointer to the NSS interface message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_c2c_tx_msg_init(struct nss_c2c_tx_msg *nct, uint16_t if_num, uint32_t type, uint32_t len,
+			nss_c2c_tx_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_c2c_tx_notify_register
+ *	Registers a notifier callback for core-to-core transmission messages with the NSS.
+ *
+ * @datatypes
+ * nss_c2c_tx_msg_callback_t
+ *
+ * @param[in] core      NSS core number index to the notifier callback table.
+ * @param[in] cb        Callback function for the message.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_c2c_tx_notify_register(int core, nss_c2c_tx_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_c2c_tx_notify_unregister
+ *	Deregisters a core-to-core transmission message notifier callback from the NSS.
+ *
+ * @param[in] core NSS core number index to the notifier callback table.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The notifier callback must have been previously registered.
+ */
+void nss_c2c_tx_notify_unregister(int core);
+
+/**
+ * nss_c2c_tx_msg_cfg_map
+ *	Sends core-to-core transmissions map to NSS
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ *
+ * @param[in] nss_ctx   Pointer to the NSS context.
+ * @param[in] tx_map    Peer core core-to-core receiver queue start address.
+ * @param[in] c2c_addr  Peer core core-to-core interrupt register address.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+extern nss_tx_status_t nss_c2c_tx_msg_cfg_map(struct nss_ctx_instance *nss_ctx, uint32_t tx_map, uint32_t c2c_addr);
+
+/**
+ * nss_c2c_tx_register_sysctl
+ *     Registers the core-to-core transmission sysctl entries to the sysctl tree.
+ *
+ * @return
+ * None.
+ */
+extern void nss_c2c_tx_register_sysctl(void);
+
+/**
+ * nss_c2c_tx_unregister_sysctl
+ *     Deregisters the core-to-core transmission sysctl entries from the sysctl tree.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The system control must have been previously registered.
+ */
+extern void nss_c2c_tx_unregister_sysctl(void);
+
+/**
+ * nss_c2c_tx_init
+ *	Initializes the core-to-core transmission.
+ *
+ * @return
+ * None.
+ */
+void nss_c2c_tx_init(void);
+
+/**
+ * nss_c2c_tx_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_c2c_tx_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_c2c_tx_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_c2c_tx_stats_unregister_notifier(struct notifier_block *nb);
+#endif /*__KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_C2C_TX_H */
diff --git a/qca-nss-drv/exports/nss_capwap.h b/qca-nss-drv/exports/nss_capwap.h
new file mode 100644
index 0000000..4be88fb
--- /dev/null
+++ b/qca-nss-drv/exports/nss_capwap.h
@@ -0,0 +1,659 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_capwap.h
+ *	NSS CAPWAP interface definitions.
+ */
+
+#ifndef __NSS_CAPWAP_H
+#define __NSS_CAPWAP_H
+
+/**
+ * @addtogroup nss_capwap_subsystem
+ * @{
+ */
+
+/**
+ * Size of the headroom required for CAPWAP packets.
+ */
+#define NSS_CAPWAP_HEADROOM 256
+
+/**
+ * nss_capwap_stats_encap_types
+ *	CAPWAP encapsulation statistics.
+ */
+enum nss_capwap_stats_encap_types {
+	NSS_CAPWAP_STATS_ENCAP_TX_PKTS,
+	NSS_CAPWAP_STATS_ENCAP_TX_BYTES,
+	NSS_CAPWAP_STATS_ENCAP_TX_SEGMENTS,
+	NSS_CAPWAP_STATS_ENCAP_TX_DROP_SG_REF,
+	NSS_CAPWAP_STATS_ENCAP_TX_DROP_VER_MISMATCH,
+	NSS_CAPWAP_STATS_ENCAP_TX_DROP_UNALIGN,
+	NSS_CAPWAP_STATS_ENCAP_TX_DROP_HEADER_ROOM,
+	NSS_CAPWAP_STATS_ENCAP_TX_DROP_DTLS,
+	NSS_CAPWAP_STATS_ENCAP_TX_DROP_NWIRELESS,
+	NSS_CAPWAP_STATS_ENCAP_TX_DROP_QUEUE_FULL,
+	NSS_CAPWAP_STATS_ENCAP_TX_DROP_MEM_FAIL,
+	NSS_CAPWAP_STATS_ENCAP_FAST_MEM,
+	NSS_CAPWAP_STATS_ENCAP_MAX
+};
+
+/**
+ * nss_capwap_stats_decap_types
+ *	CAPWAP decapsulation statistics.
+ */
+enum nss_capwap_stats_decap_types {
+	NSS_CAPWAP_STATS_DECAP_RX_PKTS,
+	NSS_CAPWAP_STATS_DECAP_RX_BYTES,
+	NSS_CAPWAP_STATS_DECAP_RX_DTLS_PKTS,
+	NSS_CAPWAP_STATS_DECAP_RX_SEGMENTS,
+	NSS_CAPWAP_STATS_DECAP_RX_DROP,
+	NSS_CAPWAP_STATS_DECAP_RX_DROP_OVERSIZE,
+	NSS_CAPWAP_STATS_DECAP_RX_DROP_FRAG_TIMEOUT,
+	NSS_CAPWAP_STATS_DECAP_RX_DROP_DUP_FRAG,
+	NSS_CAPWAP_STATS_DECAP_RX_DROP_FRAG_GAP,
+	NSS_CAPWAP_STATS_DECAP_RX_DROP_QUEUE_FULL,
+	NSS_CAPWAP_STATS_DECAP_RX_DROP_N2H_QUEUE_FULL,
+	NSS_CAPWAP_STATS_DECAP_RX_DROP_MEM_FAIL,
+	NSS_CAPWAP_STATS_DECAP_RX_DROP_CHECKSUM,
+	NSS_CAPWAP_STATS_DECAP_RX_MALFORMED,
+	NSS_CAPWAP_STATS_DECAP_FAST_MEM,
+	NSS_CAPWAP_STATS_DECAP_MAX
+};
+
+/**
+ * nss_capwap_msg_type
+ *	CAPWAP message types.
+ */
+typedef enum nss_capwap_msg_type {
+	NSS_CAPWAP_MSG_TYPE_NONE,
+	NSS_CAPWAP_MSG_TYPE_CFG_RULE,
+	NSS_CAPWAP_MSG_TYPE_UNCFG_RULE,
+	NSS_CAPWAP_MSG_TYPE_ENABLE_TUNNEL,
+	NSS_CAPWAP_MSG_TYPE_DISABLE_TUNNEL,
+	NSS_CAPWAP_MSG_TYPE_UPDATE_PATH_MTU,
+	NSS_CAPWAP_MSG_TYPE_SYNC_STATS,
+	NSS_CAPWAP_MSG_TYPE_VERSION,		/**< Default is version 1. */
+	NSS_CAPWAP_MSG_TYPE_DTLS,
+	NSS_CAPWAP_MSG_TYPE_FLOW_RULE_ADD,
+	NSS_CAPWAP_MSG_TYPE_FLOW_RULE_DEL,
+	NSS_CAPWAP_MSG_TYPE_MAX,
+} nss_capwap_msg_type_t;
+
+/**
+ * nss_capwap_msg_response
+ *	Error types for CAPWAP responses to messages from the host.
+ */
+typedef enum nss_capwap_msg_response {
+	NSS_CAPWAP_ERROR_MSG_INVALID_REASSEMBLY_TIMEOUT,
+	NSS_CAPWAP_ERROR_MSG_INVALID_PATH_MTU,
+	NSS_CAPWAP_ERROR_MSG_INVALID_MAX_FRAGMENT,
+	NSS_CAPWAP_ERROR_MSG_INVALID_BUFFER_SIZE,
+	NSS_CAPWAP_ERROR_MSG_INVALID_L3_PROTO,
+	NSS_CAPWAP_ERROR_MSG_INVALID_UDP_PROTO,
+	NSS_CAPWAP_ERROR_MSG_INVALID_VERSION,
+	NSS_CAPWAP_ERROR_MSG_TUNNEL_DISABLED,
+	NSS_CAPWAP_ERROR_MSG_TUNNEL_ENABLED,
+	NSS_CAPWAP_ERROR_MSG_TUNNEL_NOT_CFG,
+	NSS_CAPWAP_ERROR_MSG_INVALID_IP_NODE,
+	NSS_CAPWAP_ERROR_MSG_INVALID_TYPE_FLAG,
+	NSS_CAPWAP_ERROR_MSG_INVALID_DTLS_CFG,
+	NSS_CAPWAP_ERROR_MSG_FLOW_TABLE_FULL,
+	NSS_CAPWAP_ERROR_MSG_FLOW_EXIST,
+	NSS_CAPWAP_ERROR_MSG_FLOW_NOT_EXIST,
+	NSS_CAPWAP_ERROR_MSG_MAX,
+} nss_capwap_msg_response_t;
+
+/**
+ * nss_capwap_stats_msg
+ *	Per-tunnel statistics messages from the NSS firmware.
+ */
+struct nss_capwap_stats_msg {
+	struct nss_cmn_node_stats pnode_stats;	/**< Common firmware statistics. */
+	uint32_t dtls_pkts;		/**< Number of DTLS packets flowing through. */
+
+	/*
+	 * Rx/decap stats
+	 */
+	uint32_t rx_dup_frag;		/**< Number of duplicate fragments. */
+	uint32_t rx_segments;		/**< Number of segments or fragments. */
+
+	/**
+	 * Packets dropped because they are larger than the payload size.
+	 */
+	uint32_t rx_oversize_drops;
+
+	uint32_t rx_frag_timeout_drops;
+			/**< Packets dropped because of a reassembly timeout. */
+	uint32_t rx_n2h_drops;
+			/**< Packets dropped because of error in packet processing. */
+	uint32_t rx_n2h_queue_full_drops;
+			/**< Packets dropped because the NSS-to-host queue is full. */
+	uint32_t rx_csum_drops;
+			/**< Packets dropped because of a checksum mismatch. */
+	uint32_t rx_malformed;
+			/**< Packets dropped because of a malformed packet. */
+	uint32_t rx_mem_failure_drops;
+			/**< Packets dropped because of a memory failure. */
+	uint32_t rx_frag_gap_drops;
+			/**< Packets dropped because of a non-sequential fragment offset. */
+
+	/*
+	 * Tx/encap stats
+	 */
+	uint32_t tx_segments;		/**< Number of segments or fragments. */
+	uint32_t tx_queue_full_drops;	/**< Packets dropped because of a full queue. */
+	uint32_t tx_mem_failure_drops;
+			/**< Packets dropped because of a memory failure. */
+	uint32_t tx_dropped_sg_ref;
+			/**< Packets dropped because of a scatter-gather reference. */
+	uint32_t tx_dropped_ver_mis;
+			/**< Packets dropped because of a version mismatch. */
+	uint32_t Reserved;
+			/**< Reserved. */
+	uint32_t tx_dropped_hroom;
+			/**< Packets dropped because of insufficent headroom. */
+	uint32_t tx_dropped_dtls;
+			/**< Packets dropped because of a DTLS packet. */
+	uint32_t tx_dropped_nwireless;
+			/**< Packets dropped because the nwireless field information is wrong. */
+
+	uint32_t fast_mem;
+			/**< Set to 1 when tunnel is operating in fast memory. */
+};
+
+/**
+ * nss_capwap_ip
+ *	IP versions.
+ */
+struct nss_capwap_ip {
+	/**
+	 * Union of IPv4 and IPv6 IP addresses.
+	 */
+	union {
+		uint32_t ipv4;		/**< IPv4 address. */
+		uint32_t ipv6[4];	/**< IPv6 address. */
+	} ip;		/**< Union of IPv4 and IPv6 IP addresses. */
+};
+
+/**
+ * nss_capwap_encap_rule
+ *	Encapsulation information for a CAPWAP tunnel.
+ */
+struct nss_capwap_encap_rule {
+	struct  nss_capwap_ip src_ip;	/**< Source IP. */
+	uint32_t src_port;		/**< Source port. */
+	struct nss_capwap_ip dest_ip;	/**< Destination IP. */
+	uint32_t dest_port;		/**< Destination port. */
+	uint32_t path_mtu;		/**< MTU on the path. */
+};
+
+/**
+ * nss_capwap_decap_rule
+ *	Decapsulation information for a CAPWAP tunnel.
+ */
+struct nss_capwap_decap_rule {
+	uint32_t reassembly_timeout;	/**< Timeout in milliseconds. */
+	uint32_t max_fragments;		/**< Maximum number of fragments expected. */
+	uint32_t max_buffer_size;	/**< Maximum size of the payload buffer. */
+};
+
+/**
+ * nss_capwap_rule_msg
+ *	CAPWAP rule message.
+ *
+ * The same rule structure applies for both encapsulation and decapsulation
+ * in a tunnel.
+ */
+struct nss_capwap_rule_msg {
+	struct nss_capwap_encap_rule encap;	/**< Encapsulation portion of the rule. */
+	struct nss_capwap_decap_rule decap;	/**< Decapsulation portion of the rule. */
+	uint32_t stats_timer;	/**< Statistics interval timer in milliseconds. */
+
+	/**
+	 * Core to choose for receiving packets.
+	 *
+	 * Set to -1 for the NSS firmware to decide.
+	 */
+	int8_t rps;
+
+	uint8_t type_flags;		/**< VLAN or PPPOE is configured. */
+	uint8_t l3_proto;
+			/**< Prototype is NSS_CAPWAP_TUNNEL_IPV4 or NSS_CAPWAP_TUNNEL_IPV6. */
+	uint8_t which_udp;		/**< Tunnel uses the UDP or UDPLite protocol. */
+	uint32_t mtu_adjust;	/**< MTU is reserved for a DTLS process. */
+	uint32_t gmac_ifnum;	/**< Outgoing physical interface. */
+	uint32_t enabled_features;
+			/**< Tunnel enabled features bit flag. */
+
+	/*
+	 * Parameters for each features
+	 */
+	uint32_t dtls_inner_if_num;	/**< Interface number of the associated DTLS node. */
+	uint8_t bssid[ETH_ALEN];	/**< BSSID value. */
+	uint16_t outer_sgt_value;
+			/**< Security Group Tag value configured for this tunnel. */
+};
+
+/**
+ * nss_capwap_version_msg
+ *	Message to set the CAPWAP version.
+ */
+struct nss_capwap_version_msg {
+	uint32_t version;	/**< CAPWAP protocol version. */
+};
+
+/**
+ * nss_capwap_path_mtu_msg
+ *	Message information for the path MTU.
+ */
+struct nss_capwap_path_mtu_msg {
+	uint32_t path_mtu;	/**< Path MTU value between the controller and access point. */
+};
+
+/**
+ * nss_capwap_dtls_msg
+ *	DTLS message information.
+ */
+struct nss_capwap_dtls_msg {
+	uint32_t enable;			/**< Enable or disable DTLS. */
+	uint32_t dtls_inner_if_num;	/**< Interface number of the associated DTLS. */
+	uint32_t mtu_adjust;		/**< MTU adjustment reported by the DTLS node. */
+	uint32_t reserved;			/**< Reserved field for future use. */
+};
+
+/**
+ * nss_capwap_flow_rule_msg
+ *	CAPWAP flow rule message structure.
+ */
+struct nss_capwap_flow_rule_msg {
+	/*
+	 * 5-tuple info.
+	 */
+	uint16_t ip_version;            /**< IP version. */
+	uint16_t protocol;              /**< Layer 4 protocol. */
+	uint16_t src_port;		/**< Source port. */
+	uint16_t dst_port;		/**< Destination port. */
+	uint32_t src_ip[4];		/**< Source IP address. */
+	uint32_t dst_ip[4];		/**< Destination IP address. */
+
+	/*
+	 * Flow attributes.
+	 */
+	uint32_t flow_id;		/**< Flow identification. */
+};
+
+/**
+ * nss_capwap_enable_tunnel_msg
+ *	Structure to update sibling interface number.
+ */
+struct nss_capwap_enable_tunnel_msg {
+	uint32_t sibling_if_num; /**< Sibling interface number. */
+};
+
+/**
+ * nss_capwap_msg
+ *	Data for sending and receiving CAPWAP messages.
+ */
+struct nss_capwap_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a CAPWAP common message.
+	 */
+	union {
+		struct nss_capwap_rule_msg rule;
+				/**< Rule information. */
+		struct nss_capwap_path_mtu_msg mtu;
+				/**< New MTU information. */
+		struct nss_capwap_stats_msg stats;
+				/**< CAPWAP statistics. */
+		struct nss_capwap_version_msg version;
+				/**< CAPWAP version to use. */
+		struct nss_capwap_dtls_msg dtls;
+				/**< DTLS configuration. */
+		struct nss_capwap_flow_rule_msg flow_rule_add;
+				/**< Flow rule add message. */
+		struct nss_capwap_flow_rule_msg flow_rule_del;
+				/**< Flow rule delete message. */
+		struct nss_capwap_enable_tunnel_msg enable_tunnel;
+				/**< Enable tunnel message. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * nss_capwap_pn_stats
+ *	Pnode statistics (64-bit version).
+ */
+struct nss_capwap_pn_stats {
+	uint64_t rx_packets;		/**< Number of packets received. */
+	uint64_t rx_bytes;		/**< Number of bytes received. */
+	uint64_t rx_dropped;		/**< Number of dropped Rx packets. */
+	uint64_t tx_packets;		/**< Number of packets transmitted. */
+	uint64_t tx_bytes;		/**< Number of bytes transmitted. */
+};
+
+/**
+ * nss_capwap_tunnel_stats
+ *	Per-tunnel statistics seen by the HLOS.
+ */
+struct nss_capwap_tunnel_stats {
+	struct nss_capwap_pn_stats pnode_stats;	/**< Common firmware statistics. */
+	uint64_t dtls_pkts;		/**< Number of DTLS packets flowing through. */
+
+	/*
+	 * Rx/decap stats
+	 */
+	uint64_t rx_dup_frag;		/**< Number of duplicate fragments. */
+	uint64_t rx_segments;		/**< Number of segments or fragments. */
+
+	/**
+	 * Packets dropped because they are larger than the payload size.
+	 */
+	uint64_t rx_oversize_drops;
+
+	uint64_t rx_frag_timeout_drops;
+			/**< Packets dropped because of a reassembly timeout. */
+	uint64_t rx_n2h_drops;
+			/**< Packets dropped because of error in processing the packet. */
+	uint64_t rx_n2h_queue_full_drops;
+			/**< Packets dropped because the NSS-to-host queue is full. */
+	uint64_t rx_csum_drops;
+			/**< Packets dropped because of a checksum mismatch. */
+	uint64_t rx_malformed;
+			/**< Packets dropped because of a malformed packet. */
+	uint64_t rx_mem_failure_drops;
+			/**< Packets dropped because of a memory failure. */
+	uint64_t rx_frag_gap_drops;
+			/**< Packets dropped because of a non-sequential fragment offset. */
+
+	/*
+	 * Tx/encap stats
+	 */
+	uint64_t tx_dropped_inner;	/**<Packets dropped due to inflow queue full. */
+	uint64_t tx_segments;		/**< Number of segments or fragments. */
+	uint64_t tx_queue_full_drops;
+			/**< Packets dropped because the queue is full. */
+	uint64_t tx_mem_failure_drops;
+			/**< Packets dropped because of a memory failure. */
+
+	uint64_t tx_dropped_sg_ref;
+			/**< Packets dropped because of a scatter-gather reference. */
+	uint64_t tx_dropped_ver_mis;
+			/**< Packets dropped because of a version mismatch. */
+	uint64_t Reserved;
+			/**< Reserved. */
+	uint64_t tx_dropped_hroom;
+			/**< Packets dropped because of insufficent headroom. */
+	uint64_t tx_dropped_dtls;
+			/**< Packets dropped because of a DTLS packet. */
+	uint64_t tx_dropped_nwireless;
+			/**< Packets dropped because the nwireless field information is wrong. */
+
+	uint32_t fast_mem;
+			/**< Set to 1 when tunnel is operating in fast memory. */
+};
+
+/**
+ * nss_capwap_stats_notification
+ *	CAPWAP statistics structure.
+ */
+struct nss_capwap_stats_notification {
+	uint32_t core_id;			/**< Core ID. */
+	uint32_t if_num;			/**< Interface number. */
+	struct nss_capwap_tunnel_stats stats;	/**< Per-tunnel statistics. */
+};
+
+#ifdef __KERNEL__ /* only kernel will use. */
+
+/**
+ * Callback function for receiving CAPWAP tunnel data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_capwap_buf_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for receiving CAPWAP tunnel messages.
+ *
+ * @datatypes
+ * nss_capwap_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_capwap_msg_callback_t)(void *app_data, struct nss_capwap_msg *msg);
+
+/**
+ * nss_capwap_data_register
+ *	Registers the CAPWAP tunnel interface with the NSS for sending and
+ *	receiving tunnel messages.
+ *
+ * @datatypes
+ * nss_capwap_buf_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num           NSS interface number.
+ * @param[in] capwap_callback  Callback for the CAPWAP tunnel data.
+ * @param[in] netdev           Pointer to the associated network device.
+ * @param[in] features         Data socket buffer types supported by this interface.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_capwap_data_register(uint32_t if_num, nss_capwap_buf_callback_t capwap_callback, struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_capwap_tx_msg
+ *	Sends CAPWAP tunnel messages to the NSS.
+ *
+ * Do not call this function from a softirq or interrupt because it
+ * might sleep if the NSS firmware is busy serving another host thread.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_capwap_msg
+ *
+ * @param[in]     nss_ctx  Pointer to the NSS context.
+ * @param[in,out] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_capwap_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_capwap_msg *msg);
+
+/**
+ * nss_capwap_tx_buf
+ *	Sends a CAPWAP tunnel data buffer to the NSS interface.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] os_buf   Pointer to the OS data buffer.
+ * @param[in] if_num   NSS interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_capwap_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, uint32_t if_num);
+
+/**
+ * nss_capwap_data_unregister
+ *	Deregisters the CAPWAP tunnel interface from the NSS interface.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * TRUE or FALSE
+ *
+ * @dependencies
+ * The tunnel interface must have been previously registered.
+ */
+extern bool nss_capwap_data_unregister(uint32_t if_num);
+
+/**
+ * nss_capwap_notify_register
+ *	Registers an event callback handler with the HLOS driver.
+ *
+ * @datatypes
+ * nss_capwap_msg_callback_t
+ *
+ * @param[in] if_num    NSS interface number.
+ * @param[in] cb        Callback function for the message.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_capwap_notify_register(uint32_t if_num, nss_capwap_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_capwap_notify_unregister
+ *	Deregisters a message notifier from the HLOS driver.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] ctx     Pointer to the context of the HLOS driver.
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The message notifier must have been previously registered.
+ */
+extern nss_tx_status_t nss_capwap_notify_unregister(struct nss_ctx_instance *ctx, uint32_t if_num);
+
+/**
+ * nss_capwap_get_ctx
+ *	Gets the NSS context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_capwap_get_ctx(void);
+
+/**
+ * nss_capwap_ifnum_with_core_id
+ *	Gets the CAPWAP interface number with the core ID.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * Interface number with the core ID.
+ */
+extern int nss_capwap_ifnum_with_core_id(int if_num);
+
+/**
+ * nss_capwap_get_max_buf_size
+ *	Gets the NSS maximum buffer size.
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ *
+ * @return
+ * Maximum buffer size of this NSS core.
+ */
+extern uint32_t nss_capwap_get_max_buf_size(struct nss_ctx_instance *nss_ctx);
+
+/**
+ * nss_capwap_get_stats
+ *	Gets per-tunnel statistics.
+ *
+ * @datatypes
+ * nss_capwap_tunnel_stats
+ *
+ * @param[in]  if_num  NSS interface number.
+ * @param[out] stats   Pointer to the CAPWAP tunnel statistics.
+ *
+ * @return
+ * TRUE or FALSE.
+ */
+extern bool nss_capwap_get_stats(uint32_t if_num, struct nss_capwap_tunnel_stats *stats);
+
+/**
+ * nss_capwap_init
+ *	Initializes the CAPWAP interface.
+ *
+ * @return
+ * None.
+ */
+extern void nss_capwap_init(void);
+
+/**
+ * nss_capwap_msg_init
+ *	Initializes a CAPWAP message.
+ *
+ * @datatypes
+ * nss_capwap_msg \n
+ * nss_capwap_msg_callback_t
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_capwap_msg_init(struct nss_capwap_msg *ncm, uint16_t if_num, uint32_t type, uint32_t len,
+								nss_capwap_msg_callback_t cb, void *app_data);
+/**
+ * nss_capwap_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_capwap_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_capwap_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_capwap_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * @}
+ */
+
+#endif /* __KERNEL__ */
+#endif /* __NSS_CAPWAP_H */
diff --git a/qca-nss-drv/exports/nss_clmap.h b/qca-nss-drv/exports/nss_clmap.h
new file mode 100644
index 0000000..ce2bfe6
--- /dev/null
+++ b/qca-nss-drv/exports/nss_clmap.h
@@ -0,0 +1,390 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_clmap.h
+ *	NSS client map interface definitions.
+ */
+
+#ifndef __NSS_CLMAP_H
+#define __NSS_CLMAP_H
+
+ /**
+  * @addtogroup nss_clmap_subsystem
+  * @{
+  */
+
+/**
+ * Maximum number of supported client map interface.
+ */
+#define NSS_CLMAP_MAX_INTERFACES 1
+
+/**
+ * nss_clmap_msg_type
+ *	Client map message types.
+ */
+typedef enum nss_clmap_msg_type {
+	NSS_CLMAP_MSG_TYPE_SYNC_STATS,		/**< Statistics synchronization message. */
+	NSS_CLMAP_MSG_TYPE_INTERFACE_ENABLE,	/**< Enable the interface. */
+	NSS_CLMAP_MSG_TYPE_INTERFACE_DISABLE,	/**< Disable the interface. */
+	NSS_CLMAP_MSG_TYPE_MAC_ADD,		/**< Add MAC rule to the database. */
+	NSS_CLMAP_MSG_TYPE_MAC_DEL,		/**< Remove MAC rule from the database. */
+	NSS_CLMAP_MSG_TYPE_MAC_FLUSH,		/**< Flush all the MAC rules for a tunnel. */
+	NSS_CLMAP_MSG_TYPE_MAX,			/**< Maximum message type. */
+} nss_clmap_msg_type_t;
+
+/**
+ * nss_clmap_error_types
+ *	Error types for client map responses to messages from the host.
+ */
+typedef enum nss_clmap_error_types {
+	NSS_CLMAP_ERROR_UNKNOWN_TYPE = 1,	/**< Unknown type error. */
+	NSS_CLMAP_ERROR_INTERFACE_DISABLED,	/**< Interface is already disabled. */
+	NSS_CLMAP_ERROR_INTERFACE_ENABLED,	/**< Interface is already enabled. */
+	NSS_CLMAP_ERROR_INVALID_VLAN,		/**< Invalid VLAN. */
+	NSS_CLMAP_ERROR_INVALID_TUNNEL,		/**< Invalid tunnel. */
+	NSS_CLMAP_ERROR_MAC_TABLE_FULL,		/**< MAC table is full. */
+	NSS_CLMAP_ERROR_MAC_EXIST,		/**< MAC does already exist in the table. */
+	NSS_CLMAP_ERROR_MAC_NOT_EXIST,		/**< MAC does not exist in the table. */
+	NSS_CLMAP_ERROR_MAC_ENTRY_UNHASHED,	/**< MAC entry is not hashed in table. */
+	NSS_CLMAP_ERROR_MAC_ENTRY_INSERT_FAILED,
+						/**< Insertion into MAC table failed. */
+	NSS_CLMAP_ERROR_MAC_ENTRY_ALLOC_FAILED,	/**< MAC entry allocation failed. */
+	NSS_CLMAP_ERROR_MAC_ENTRY_DELETE_FAILED,/**< MAC entry deletion failed. */
+	NSS_CLMAP_ERROR_MAX,			/**< Maximum error type. */
+} nss_clmap_error_t;
+
+/**
+ * nss_clmap_interface_type
+ *	Client map NSS interface type.
+ */
+enum nss_clmap_interface_type {
+	NSS_CLMAP_INTERFACE_TYPE_US,
+	NSS_CLMAP_INTERFACE_TYPE_DS,
+	NSS_CLMAP_INTERFACE_TYPE_MAX
+};
+
+/**
+ * nss_clmap_stats_type
+ *	Client map statistic counters.
+ */
+enum nss_clmap_stats_type {
+	NSS_CLMAP_INTERFACE_STATS_RX_PKTS,			/**< Number of packets received. */
+	NSS_CLMAP_INTERFACE_STATS_RX_BYTES,			/**< Number of bytes received. */
+	NSS_CLMAP_INTERFACE_STATS_TX_PKTS,			/**< Number of packets transmitted. */
+	NSS_CLMAP_INTERFACE_STATS_TX_BYTES,			/**< Number of bytes transmitted. */
+	NSS_CLMAP_INTERFACE_STATS_RX_QUEUE_0_DROPPED,		/**< Dropped receive packets 0. */
+	NSS_CLMAP_INTERFACE_STATS_RX_QUEUE_1_DROPPED,		/**< Dropped receive packets 1. */
+	NSS_CLMAP_INTERFACE_STATS_RX_QUEUE_2_DROPPED,		/**< Dropped receive packets 2. */
+	NSS_CLMAP_INTERFACE_STATS_RX_QUEUE_3_DROPPED,		/**< Dropped receive packets 3. */
+	NSS_CLMAP_INTERFACE_STATS_DROPPED_MACDB_LOOKUP_FAILED,	/**< Dropped due to MAC database look up failed. */
+	NSS_CLMAP_INTERFACE_STATS_DROPPED_INVALID_PACKET_SIZE,	/**< Dropped due to invalid size packets. */
+	NSS_CLMAP_INTERFACE_STATS_DROPPED_LOW_HEADROOM,		/**< Dropped due to insufficent headroom. */
+	NSS_CLMAP_INTERFACE_STATS_DROPPED_NEXT_NODE_QUEUE_FULL,	/**< Dropped due to next node queue full. */
+	NSS_CLMAP_INTERFACE_STATS_DROPPED_PBUF_ALLOC_FAILED,	/**< Dropped due to buffer allocation failure. */
+	NSS_CLMAP_INTERFACE_STATS_DROPPED_LINEAR_FAILED,	/**< Dropped due to linear copy failure. */
+	NSS_CLMAP_INTERFACE_STATS_SHARED_PACKET_CNT,		/**< Shared packet count. */
+	NSS_CLMAP_INTERFACE_STATS_ETHERNET_FRAME_ERROR,		/**< Ethernet frame error count. */
+	NSS_CLMAP_INTERFACE_STATS_MACDB_CREATE_REQUESTS_CNT,	/**< MAC database create requests count. */
+	NSS_CLMAP_INTERFACE_STATS_MACDB_CREATE_MAC_EXISTS_CNT,	/**< MAC database create failures, MAC exist count. */
+	NSS_CLMAP_INTERFACE_STATS_MACDB_CREATE_MAC_TABLE_FULL_CNT,
+								/**< MAC database create failures, MAC database full count. */
+	NSS_CLMAP_INTERFACE_STATS_MACDB_DESTROY_REQUESTS_CNT,	/**< MAC database destroy requests count. */
+	NSS_CLMAP_INTERFACE_STATS_MACDB_DESTROY_MAC_NOT_FOUND_CNT,
+								/**< MAC database destroy failures, MAC not found count. */
+	NSS_CLMAP_INTERFACE_STATS_MACDB_DESTROY_MAC_UNHASHED_CNT,
+								/**< MAC database destroy failures, MAC unhashed count. */
+	NSS_CLMAP_INTERFACE_STATS_MACDB_FLUSH_REQUESTS_CNT,	/**< MAC database flush requests count. */
+	NSS_CLMAP_INTERFACE_STATS_MAX,				/**< Maximum statistics type. */
+};
+
+/**
+ * nss_clmap_stats_msg
+ *	Per-interface statistics messages from the NSS firmware.
+ */
+struct nss_clmap_stats_msg {
+	struct nss_cmn_node_stats node_stats;		/**< Common firmware statistics. */
+	uint32_t dropped_macdb_lookup_failed;		/**< Dropped due to MAC database look up failed. */
+	uint32_t dropped_invalid_packet_size;		/**< Dropped due to invalid size packets. */
+	uint32_t dropped_low_hroom;			/**< Dropped due to insufficent headroom. */
+	uint32_t dropped_next_node_queue_full;		/**< Dropped due to next node queue full. */
+	uint32_t dropped_pbuf_alloc_failed;		/**< Dropped due to buffer allocation failure. */
+	uint32_t dropped_linear_failed;			/**< Dropped due to linear copy failure. */
+	uint32_t shared_packet_count;			/**< Shared packet count. */
+	uint32_t ethernet_frame_error;			/**< Ethernet frame error count. */
+	uint32_t macdb_create_requests;			/**< MAC database create requests count. */
+	uint32_t macdb_create_mac_exists;		/**< MAC database create failures, MAC exist count. */
+	uint32_t macdb_create_table_full;		/**< MAC database create failures, MAC database full count. */
+	uint32_t macdb_destroy_requests;		/**< MAC database destroy requests count. */
+	uint32_t macdb_destroy_mac_notfound;		/**< MAC database destroy failures, MAC not found count. */
+	uint32_t macdb_destroy_mac_unhashed;		/**< MAC database destroy failures, MAC unhashed count. */
+	uint32_t macdb_flush_requests;			/**< MAC database flush requests count. */
+};
+
+/**
+ * nss_clmap_mac_msg
+ *	Client map MAC message structure.
+ */
+struct nss_clmap_mac_msg {
+	uint32_t vlan_id;			/**< VLAN ID. */
+	uint32_t nexthop_ifnum;			/**< Next hop interface number. */
+	uint32_t needed_headroom;			/**< Headroom to be added. */
+	uint16_t mac_addr[3];			/**< MAC address. */
+	uint8_t flags;				/**< Flags that carry metadata information. */
+	uint8_t reserved;			/**< Reserved. */
+};
+
+/**
+ * nss_clmap_flush_mac_msg
+ *	CLient flush map MAC message structure.
+ */
+struct nss_clmap_flush_mac_msg {
+	uint32_t nexthop_ifnum;			/**< Next hop interface number. */
+};
+
+/**
+ * nss_clmap_stats_notification
+ *	Client map transmission statistics structure.
+ */
+struct nss_clmap_stats_notification {
+	uint64_t stats_ctx[NSS_CLMAP_INTERFACE_STATS_MAX];	/**< Context transmission statistics. */
+	uint32_t core_id;					/**< Core ID. */
+	uint32_t if_num;					/**< Interface number. */
+};
+
+/**
+ * nss_clmap_msg
+ *	Data for sending and receiving client map messages.
+ */
+struct nss_clmap_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a client map common message.
+	 */
+	union {
+		struct nss_clmap_stats_msg stats;
+				/**< Client map statistics. */
+		struct nss_clmap_mac_msg mac_add;
+				/**< MAC rule add message. */
+		struct nss_clmap_mac_msg mac_del;
+				/**< MAC rule delete message. */
+		struct nss_clmap_flush_mac_msg mac_flush;
+				/**< MAC rule flush message. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving client map data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_clmap_buf_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for receiving client map messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_clmap_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * nss_clmap_tx_msg
+ *	Sends client map messages to the NSS.
+ *
+ * Do not call this function from a softirq or interrupt because it
+ * might sleep if the NSS firmware is busy serving another host thread.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_clmap_msg
+ *
+ * @param[in]     nss_ctx  Pointer to the NSS context.
+ * @param[in,out] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_clmap_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_clmap_msg *msg);
+
+/**
+ * nss_clmap_tx_msg_sync
+ *	Sends client map messages to the NSS.
+ *
+ * Do not call this function from a softirq or interrupt because it
+ * might sleep if the NSS firmware is busy serving another host thread.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_clmap_msg
+ *
+ * @param[in]     nss_ctx  Pointer to the NSS context.
+ * @param[in,out] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_clmap_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_clmap_msg *msg);
+
+/**
+ * nss_clmap_tx_buf
+ *	Sends a client map data buffer to the NSS interface.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] buf   Pointer to the data buffer.
+ * @param[in] if_num   NSS interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_clmap_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *buf, uint32_t if_num);
+
+/**
+ * nss_clmap_unregister
+ *	Deregisters the client map interface from the NSS interface.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * TRUE or FALSE
+ *
+ * @dependencies
+ * The interface must have been previously registered.
+ */
+extern bool nss_clmap_unregister(uint32_t if_num);
+
+/**
+ * nss_clmap_register
+ *	Registers the client map interface with the NSS for sending and
+ *	receiving interface messages.
+ *
+ * @datatypes
+ * nss_clmap_msg_callback_t \n
+ * nss_clmap_buf_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num                    NSS interface number.
+ * @param[in] dynamic_interface_type    NSS interface type.
+ * @param[in] data_cb                   Data callback for the client map data.
+ * @param[in] notify_cb                 Notify callback for the client map data.
+ * @param[in] netdev                    Pointer to the associated network device.
+ * @param[in] features                  Data socket buffer types supported by this interface.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_clmap_register(uint32_t if_num, uint32_t dynamic_interface_type,
+			nss_clmap_buf_callback_t data_cb, nss_clmap_msg_callback_t notify_cb,
+			struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_clmap_get_ctx
+ *	Get the NSS context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_clmap_get_ctx(void);
+
+/**
+ * nss_clmap_ifnum_with_core_id
+ *	Gets the client map interface number with the core ID.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * Interface number with the core ID.
+ */
+extern int nss_clmap_ifnum_with_core_id(int if_num);
+
+/**
+ * nss_clmap_init
+ *	Initializes the client map interface.
+ *
+ * @return
+ * None.
+ */
+extern void nss_clmap_init(void);
+
+/**
+ * nss_clmap_msg_init
+ *	Initializes a client map message.
+ *
+ * @datatypes
+ * nss_clmap_msg \n
+ * nss_clmap_msg_callback_t
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_clmap_msg_init(struct nss_clmap_msg *ncm, uint16_t if_num, uint32_t type, uint32_t len,
+								nss_clmap_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_clmap_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_clmap_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * nss_clmap_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_clmap_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_CLMAP_H */
diff --git a/qca-nss-drv/exports/nss_cmn.h b/qca-nss-drv/exports/nss_cmn.h
new file mode 100644
index 0000000..6e5c41e
--- /dev/null
+++ b/qca-nss-drv/exports/nss_cmn.h
@@ -0,0 +1,478 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, 2016-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_cmn.h
+ *	NSS Common Message Structure and APIs
+ */
+
+#ifndef __NSS_CMN_H
+#define __NSS_CMN_H
+
+/**
+ * @addtogroup nss_common_subsystem
+ * @{
+ */
+
+/**
+ * Interface Number 1 Valid 7 Core 8 Type 16 Index
+ */
+typedef int32_t nss_if_num_t;
+#define NSS_IF_IS_TYPE_DYNAMIC(if_num)		(if_num != -1)
+#define NSS_IF_IS_VALID(if_num)		(if_num < NSS_MAX_NET_INTERFACES)
+
+/**
+ * @struct nss_ctx_instance
+ *	Forward declaration for structure that contains instance data for each
+ *	NSS core. Contents of structure are private to the NSS driver.
+ */
+struct nss_ctx_instance;
+
+/*
+ * The first 8 bits of an interfaces number is representing the core_id,
+ * 0 means local core.
+ */
+
+#define NSS_CORE_ID_SHIFT 24		/**< Number of bits to shift a core local interface number. */
+
+/**
+ * Macro that appends the core identifier to an interface number.
+ */
+#define NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, interface) ((interface) | ((nss_ctx->id + 1) << NSS_CORE_ID_SHIFT))
+
+/**
+ * Macro to obtain a core local interface number.
+ */
+#define NSS_INTERFACE_NUM_GET(interface) ((interface) & 0xffffff)
+
+/**
+ * Macro to obtain an interface core number.
+ */
+#define NSS_INTERFACE_NUM_GET_COREID(interface) ((interface >> NSS_CORE_ID_SHIFT) & 0xff)
+
+/*
+ * Common enumerations.
+ */
+
+/**
+ * nss_tx_status_t
+ *	Tx command failure results.
+ *
+ * Types starting with NSS_TX_FAILURE_SYNC_ are only used by synchronous messages.
+ */
+typedef enum {
+	NSS_TX_SUCCESS = 0,
+	NSS_TX_FAILURE,
+	NSS_TX_FAILURE_QUEUE,
+	NSS_TX_FAILURE_NOT_READY,
+	NSS_TX_FAILURE_TOO_LARGE,
+	NSS_TX_FAILURE_TOO_SHORT,
+	NSS_TX_FAILURE_NOT_SUPPORTED,
+	NSS_TX_FAILURE_BAD_PARAM,
+	NSS_TX_FAILURE_NOT_ENABLED,
+	NSS_TX_FAILURE_SYNC_BAD_PARAM,
+	NSS_TX_FAILURE_SYNC_TIMEOUT,
+	NSS_TX_FAILURE_SYNC_FW_ERR,
+	NSS_TX_FAILURE_MAX,
+} nss_tx_status_t;
+
+/**
+ * nss_state_t
+ *	Initialization states.
+ */
+typedef enum {
+	NSS_STATE_UNINITIALIZED = 0,
+	NSS_STATE_INITIALIZED
+} nss_state_t;
+
+/**
+ * nss_core_id_t
+ *	NSS core IDs.
+ */
+typedef enum {
+	NSS_CORE_0 = 0,
+	NSS_CORE_1,
+	NSS_CORE_MAX
+} nss_core_id_t;
+
+/**
+ * nss_cb_register_status_t
+ *	Callback registration states.
+ */
+typedef enum {
+	NSS_CB_REGISTER_SUCCESS = 0,
+	NSS_CB_REGISTER_FAILED,
+} nss_cb_register_status_t;
+
+/**
+ * nss_cb_unregister_status_t
+ *	Callback deregistration states.
+ */
+typedef enum {
+	NSS_CB_UNREGISTER_SUCCESS = 0,
+	NSS_CB_UNREGISTER_FAILED,
+} nss_cb_unregister_status_t;
+
+/**
+ * nss_cmn_response
+ *	Responses for a common message.
+ */
+enum nss_cmn_response {
+	NSS_CMN_RESPONSE_ACK,
+	NSS_CMN_RESPONSE_EVERSION,
+	NSS_CMN_RESPONSE_EINTERFACE,
+	NSS_CMN_RESPONSE_ELENGTH,
+	NSS_CMN_RESPONSE_EMSG,
+	NSS_CMN_RESPONSE_NOTIFY,
+	NSS_CMN_RESPONSE_LAST
+};
+
+/**
+ * Array of log messages for common NSS responses.
+ */
+extern int8_t *nss_cmn_response_str[NSS_CMN_RESPONSE_LAST];
+
+/**
+ * nss_cmn_msg
+ *	Common message information.
+ */
+struct nss_cmn_msg {
+	uint16_t version;	/**< Version ID for the main message format. */
+	uint16_t len;		/**< Length of the message, excluding the header. */
+	uint32_t interface;	/**< Primary key for all messages. */
+	enum nss_cmn_response response;
+			/**< Primary response. All messages must specify one of these responses. */
+
+	uint32_t type;	/**< Decentralized request number used to match response numbers. */
+	uint32_t error;	/**< Decentralized specific error message (response == EMSG). */
+
+	/**
+	 * Padding used to start the callback from a 64-bit boundary. This field can be reused.
+	 */
+	uint32_t reserved;
+
+	nss_ptr_t cb;		/**< Contains the callback pointer. */
+#ifndef __LP64__
+	uint32_t padding1;	/**< Padding used to fit 64 bits. Do not reuse. */
+#endif
+	nss_ptr_t app_data;	/**< Contains the application data. */
+#ifndef __LP64__
+	uint32_t padding2;	/**< Padding used to fit 64 bits. Do not reuse. */
+#endif
+};
+
+/**
+ * nss_cmn_node_stats
+ *	Common per-node statistics.
+ */
+struct nss_cmn_node_stats {
+	uint32_t rx_packets;			/**< Number of packets received. */
+	uint32_t rx_bytes;			/**< Number of bytes received. */
+	uint32_t tx_packets;			/**< Number of packets transmitted. */
+	uint32_t tx_bytes;			/**< Number of bytes transmitted. */
+	uint32_t rx_dropped[NSS_MAX_NUM_PRI];	/**< Packets dropped on receive due to queue full. */
+};
+
+/**
+ * nss_cmn_get_msg_len
+ *	Gets the message length of a host-to-NSS message.
+ *
+ * @datatypes
+ * nss_cmn_get_msg_len
+ *
+ * @param[in] ncm  Pointer to the common message.
+ *
+ * @return
+ * Length of the message specified in the argument to this function.
+ */
+static inline uint32_t nss_cmn_get_msg_len(struct nss_cmn_msg *ncm)
+{
+	return ncm->len + sizeof(struct nss_cmn_msg);
+}
+
+#ifdef __KERNEL__ /* only for kernel to use. */
+
+/**
+ * nss_cmn_msg_init
+ *	Initializes the common area of an asynchronous host-to-NSS message.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in,out] ncm       Pointer to the common message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Pointer to the callback function.
+ * @param[in]     app_data  Pointer to the application context for this message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_cmn_msg_init(struct nss_cmn_msg *ncm, uint32_t if_num, uint32_t type, uint32_t len,
+	void *cb, void *app_data);
+
+/**
+ * nss_cmn_msg_sync_init
+ *	Initializes the common message of a synchronous host-to-NSS message.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in,out] ncm     Pointer to the common message.
+ * @param[in]     if_num  NSS interface number.
+ * @param[in]     type    Type of message.
+ * @param[in]     len     Size of the payload.
+ *
+ * @return
+ * None.
+ */
+extern void nss_cmn_msg_sync_init(struct nss_cmn_msg *ncm, uint32_t if_num, uint32_t type,  uint32_t len);
+
+/**
+ * nss_cmn_get_interface_number
+ *	Gets the interface number.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * net_device
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] dev      Pointer to the OS network device pointer.
+ *
+ * @return
+ * Interface number.
+ */
+extern int32_t nss_cmn_get_interface_number(struct nss_ctx_instance *nss_ctx, struct net_device *dev);
+
+/**
+ * nss_cmn_get_interface_number_by_dev
+ *	Gets the interface number of a device.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] dev  Pointer to the OS network device pointer.
+ *
+ * @return
+ * Interface number, or -1 on failure.
+ */
+extern int32_t nss_cmn_get_interface_number_by_dev(struct net_device *dev);
+
+/**
+ * nss_cmn_get_interface_number_by_dev_and_type
+ *	Gets the interface number by a device and its type.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] dev   Pointer to the OS network device pointer.
+ * @param[in] type  Type of this interface.
+ *
+ * @return
+ * Interface number, or -1 on failure.
+ */
+extern int32_t nss_cmn_get_interface_number_by_dev_and_type(struct net_device *dev, uint32_t type);
+
+/**
+ * nss_cmn_interface_is_redirect
+ *	Determines if the interface number is a redirect interface.
+ *
+ * @param[in] nss_ctx        Pointer to the NSS context.
+ * @param[in] interface_num  NSS interface number.
+ *
+ * @return
+ * TRUE if the number is a redirect interface. Otherwise FALSE.
+ */
+extern bool nss_cmn_interface_is_redirect(struct nss_ctx_instance *nss_ctx, int32_t interface_num);
+
+/**
+ * nss_cmn_append_core_id
+ * 	Append core ID on NSS interface number.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx   Pointer to the NSS context.
+ * @param[in] if_num    NSS interface number.
+ *
+ * @return
+ * Interface number with core ID.
+ */
+extern int nss_cmn_append_core_id(struct nss_ctx_instance *nss_ctx, int if_num);
+
+/**
+ * nss_cmn_get_interface_dev
+ *	Gets an interface device pointer.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] if_num   NSS interface number.
+ *
+ * @return
+ * Interface device pointer.
+ */
+extern struct net_device *nss_cmn_get_interface_dev(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+
+/**
+ * nss_cmn_get_state
+ *	Obtains the NSS state.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ *
+ * @return
+ * NSS state that indicates whether the NSS core is initialized. For possible values, see nss_state_t.
+ */
+extern nss_state_t nss_cmn_get_state(struct nss_ctx_instance *nss_ctx);
+
+/**
+ * Callback function for queue decongestion messages.
+ *
+ * @param[in] app_data  Pointer to the application context for this message.
+ */
+typedef void (*nss_cmn_queue_decongestion_callback_t)(void *app_data);
+
+/**
+ * nss_cmn_register_queue_decongestion
+ *	Registers a queue for a decongestion event.
+ *
+ * The callback function is called with the spinlock held. The function should avoid deadlocks
+ * caused by attempting to acquire multiple spinlocks.
+
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_cmn_queue_decongestion_callback_t
+ *
+ * @param[in,out] nss_ctx         Pointer to the NSS context.
+ * @param[in]     event_callback  Callback for the message.
+ * @param[in]     app_data        Pointer to the application context to be returned in the
+ *                                callback.
+ *
+ * @return
+ * #NSS_CB_REGISTER_SUCCESS if registration is successful.
+ * @par
+ * Otherwise, #NSS_CB_REGISTER_FAILED.
+ */
+extern nss_cb_register_status_t nss_cmn_register_queue_decongestion(struct nss_ctx_instance *nss_ctx, nss_cmn_queue_decongestion_callback_t event_callback, void *app_data);
+
+/**
+ * nss_cmn_unregister_queue_decongestion
+ *	Deregisters a queue from receiving a decongestion event.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_cmn_queue_decongestion_callback_t
+ *
+ * @param[in,out] nss_ctx         Pointer to the NSS context.
+ * @param[in]     event_callback  Callback for the message.
+ *
+ * @return
+ * #NSS_CB_REGISTER_SUCCESS if registration is successful.
+ * @par
+ * Otherwise, #NSS_CB_REGISTER_FAILED.
+ *
+ * @dependencies
+ * The callback function must have been previously registered.
+ */
+extern nss_cb_unregister_status_t nss_cmn_unregister_queue_decongestion(struct nss_ctx_instance *nss_ctx, nss_cmn_queue_decongestion_callback_t event_callback);
+
+/**
+ * Callback function for packets with service code.
+ *
+ * @param[in] app_data  Pointer to the application context for this message.
+ * @param[in] nbuf      Pointer to the socket buffer.
+ */
+typedef void (*nss_cmn_service_code_callback_t)(void *app_data, struct sk_buff *nbuf);
+
+/**
+ * nss_cmn_register_service_code
+ *	Registers a callback for a service code.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_cmn_service_code_callback_t
+ *
+ * @param[in,out] nss_ctx         Pointer to the NSS context.
+ * @param[in]     cb              Callback for the message.
+ * @param[in]     service_code    Service code found attached to the packet.
+ * @param[in]     app_data        Pointer to the application context to be returned in the
+ *                                callback.
+ *
+ * @return
+ * #NSS_CB_REGISTER_SUCCESS if registration is successful.
+ * @par
+ * Otherwise, #NSS_CB_REGISTER_FAILED.
+ */
+extern nss_cb_register_status_t nss_cmn_register_service_code(struct nss_ctx_instance *nss_ctx, nss_cmn_service_code_callback_t cb, uint8_t service_code, void *app_data);
+
+/**
+ * nss_cmn_unregister_service_code
+ *	Deregisters a callback for the given service code.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_cmn_service_code_callback_t
+ *
+ * @param[in,out] nss_ctx         Pointer to the NSS context.
+ * @param[in]     cb              Callback for the message.
+ * @param[in]     service_code    Service code found attached to the packet.
+ *
+ * @return
+ * #NSS_CB_REGISTER_SUCCESS if registration is successful.
+ * @par
+ * Otherwise, #NSS_CB_REGISTER_FAILED.
+ *
+ * @dependencies
+ * The callback function must have been previously registered.
+ */
+extern nss_cb_unregister_status_t nss_cmn_unregister_service_code(struct nss_ctx_instance *nss_ctx, nss_cmn_service_code_callback_t cb, uint8_t service_code);
+
+/**
+ * nss_cmn_get_nss_enabled
+ *	Checks whether the NSS mode is supported on the platform.
+ *
+ * @return
+ * TRUE if NSS is supported. \n
+ * Otherwise, FALSE.
+ */
+extern bool nss_cmn_get_nss_enabled(void);
+
+/**
+ * nss_cmn_rx_dropped_sum
+ *	Sums dropped packet count of all NSS pnode queues.
+ *
+ * @datatypes
+ * nss_cmn_node_stats \n
+ *
+ * @param[in] node_stats  Pointer to node statistics.
+ *
+ * @return
+ * Total dropped packets count.
+ */
+extern uint32_t nss_cmn_rx_dropped_sum(struct nss_cmn_node_stats *node_stats);
+
+#endif /* __KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_CMN_MSG_H */
diff --git a/qca-nss-drv/exports/nss_crypto.h b/qca-nss-drv/exports/nss_crypto.h
new file mode 100644
index 0000000..5ef514d
--- /dev/null
+++ b/qca-nss-drv/exports/nss_crypto.h
@@ -0,0 +1,392 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_crypto.h
+ *	NSS Crypto interface definitions.
+ */
+
+#ifndef __NSS_CRYPTO_H
+#define __NSS_CRYPTO_H
+
+/**
+ * @addtogroup nss_crypto_subsystem
+ * @{
+ */
+
+#define NSS_CRYPTO_MAX_IDXS 64		/**< Maximum number of supported sessions. */
+#define NSS_CRYPTO_MAX_ENGINES 4	/**< Maximum number of engines available. */
+#define NSS_CRYPTO_BAM_PP 2		/**< Bus Access Manager pipe pairs. */
+
+/**
+ * nss_crypto_hash
+ *	Hash sizes supported by the hardware.
+ */
+enum nss_crypto_hash {
+	NSS_CRYPTO_HASH_SHA96 = 12,
+	NSS_CRYPTO_HASH_SHA128 = 16,
+	NSS_CRYPTO_HASH_SHA160 = 20,
+	NSS_CRYPTO_HASH_SHA256 = 32
+};
+
+/**
+ * nss_crypto_cipher
+ *	Cipher algorithms.
+ */
+enum nss_crypto_cipher {
+	NSS_CRYPTO_CIPHER_NONE = 0,
+	NSS_CRYPTO_CIPHER_AES_CBC,	/**< AES, and CBC for 128-bit and 256-bit key sizes. */
+	NSS_CRYPTO_CIPHER_DES,		/**< DES, and CBC for 64-bit key size. */
+	NSS_CRYPTO_CIPHER_NULL,		/**< NULL and CBC. */
+	NSS_CRYPTO_CIPHER_AES_CTR,	/**< AES, and CTR for 128-bit and 256-bit key sizes. */
+	NSS_CRYPTO_CIPHER_MAX
+};
+
+/**
+ * nss_crypto_auth
+ *	Authentication algorithms.
+ */
+enum nss_crypto_auth {
+	NSS_CRYPTO_AUTH_NONE = 0,
+	NSS_CRYPTO_AUTH_SHA1_HMAC,
+	NSS_CRYPTO_AUTH_SHA256_HMAC,
+	NSS_CRYPTO_AUTH_NULL,
+	NSS_CRYPTO_AUTH_MAX
+};
+
+/**
+ * nss_crypto_msg_type
+ *	Synchronization types.
+ */
+enum nss_crypto_msg_type {
+	NSS_CRYPTO_MSG_TYPE_NONE = 0,
+	NSS_CRYPTO_MSG_TYPE_OPEN_ENG = 1,
+	NSS_CRYPTO_MSG_TYPE_CLOSE_ENG = 2,
+	NSS_CRYPTO_MSG_TYPE_UPDATE_SESSION = 3,
+	NSS_CRYPTO_MSG_TYPE_STATS = 4,
+	NSS_CRYPTO_MSG_TYPE_MAX
+};
+
+/**
+ * nss_crypto_msg_error
+ *	Response types.
+ */
+enum nss_crypto_msg_error {
+	NSS_CRYPTO_MSG_ERROR_NONE = 0,
+	NSS_CRYPTO_MSG_ERROR_INVAL_ENG = 1,
+	NSS_CRYPTO_MSG_ERROR_UNSUPP_OP = 2,
+	NSS_CRYPTO_MSG_ERROR_INVAL_OP = 3,
+	NSS_CRYPTO_MSG_ERROR_INVAL_IDX_RANGE = 4,
+	NSS_CRYPTO_MSG_ERROR_IDX_ALLOC_FAIL = 5,
+	NSS_CRYPTO_MSG_ERROR_MAX
+};
+
+/**
+ * nss_crypto_session_state
+ *	Session states.
+ */
+enum nss_crypto_session_state {
+	NSS_CRYPTO_SESSION_STATE_NONE = 0,
+	NSS_CRYPTO_SESSION_STATE_ACTIVE = 1,
+	NSS_CRYPTO_SESSION_STATE_FREE = 2
+};
+
+/**
+ * nss_crypto_buf_origin
+ *	Origins of the crypto session.
+ */
+enum nss_crypto_buf_origin {
+	NSS_CRYPTO_BUF_ORIGIN_HOST = 0x001,
+	NSS_CRYPTO_BUF_ORIGIN_NSS = 0x0002,
+};
+
+/**
+ * nss_crypto_idx
+ *	Crypto session index information.
+ */
+struct nss_crypto_idx {
+	uint16_t pp_num;		/**< Pipe pair index. */
+	uint16_t cmd_len;		/**< Command block length to program. */
+	uint32_t cblk_paddr;		/**< Physical address of the command block. */
+};
+
+/**
+ * nss_crypto_config_eng
+ *	Engine configuration information for opening the engine from the host.
+ *
+ * This structure is called to initialize the crypto NSS engine-specific data
+ * structures. Ideally, the host can send a single probe for all engines, but
+ * the current implementation relies on probes per engine.
+ */
+struct nss_crypto_config_eng {
+	uint32_t eng_id;		/**< Engine number to open. */
+	uint32_t bam_pbase;		/**< BAM base address (physical). */
+	uint32_t crypto_pbase;		/**< Crypto base address (physical). */
+	uint32_t desc_paddr[NSS_CRYPTO_BAM_PP];
+					/**< Pipe description address (physical). */
+	struct nss_crypto_idx idx[NSS_CRYPTO_MAX_IDXS];
+					/**< Allocated session indices. */
+};
+
+/**
+ * nss_crypto_config_session
+ *	Session-related state configuration.
+ */
+struct nss_crypto_config_session {
+	uint32_t idx;		/**< Session index on which the state is reset. */
+	uint32_t state;		/**< Index state of the session. */
+	uint32_t iv_len;	/**< Length of the initialization vector. */
+};
+
+/**
+ * nss_crypto_stats
+ *	Crypto statistics.
+ */
+struct nss_crypto_stats {
+	uint32_t queued;	/**< Number of frames waiting to be processed. */
+	uint32_t completed;	/**< Number of frames processed. */
+	uint32_t dropped;	/**< Number of frames dropped or not processed. */
+};
+
+/**
+ * nss_crypto_sync_stats
+ *	Statistics synchronized to the host.
+ */
+struct nss_crypto_sync_stats {
+	struct nss_crypto_stats eng_stats[NSS_CRYPTO_MAX_ENGINES];
+			/**< Tx or Rx statistics captured per crypto engine. */
+	struct nss_crypto_stats idx_stats[NSS_CRYPTO_MAX_IDXS];
+			/**< Tx or Rx statistics captured per session. */
+	struct nss_crypto_stats total;
+			/**< Total statistics captured in and out of the engine. */
+};
+
+/**
+ * nss_crypto_msg
+ *	Data for sending and receiving crypto messages.
+ */
+struct nss_crypto_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a crypto message.
+	 */
+	union {
+		struct nss_crypto_config_eng eng;
+				/**< Opens an engine. */
+		struct nss_crypto_config_session session;
+				/**< Resets the statistics. */
+		struct nss_crypto_sync_stats stats;
+				/**< Synchronized statistics for crypto. */
+	} msg;			/**< Message payload. */
+};
+
+#ifdef __KERNEL__  /* only kernel will use. */
+
+/**
+ * Message notification callback.
+ *
+ * @datatypes
+ * nss_crypto_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_crypto_msg_callback_t)(void *app_data, struct nss_crypto_msg *msg);
+
+/**
+ * Data callback.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_crypto_buf_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Power management event callback.
+ *
+ * @param[in] app_data    Pointer to the application context of the message.
+ * @param[in] turbo       Turbo mode event.
+ * @param[in] auto_scale  Specifies the auto scaling of the NSS clock frequency.
+ *
+ * @return
+ * TRUE if crypto is scaled to turbo.
+ */
+typedef bool (*nss_crypto_pm_event_callback_t)(void *app_data, bool turbo, bool auto_scale);
+
+/**
+ * nss_crypto_tx_msg
+ *	Sends a crypto message.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_crypto_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context of the HLOS driver.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * None.
+ */
+extern nss_tx_status_t nss_crypto_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_crypto_msg *msg);
+
+/**
+ * nss_crypto_tx_buf
+ *	Sends a crypto data packet.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context of the HLOS driver
+ * @param[in] if_num   NSS interface number.
+ * @param[in] skb      Pointer to the data socket buffer.
+ *
+ * @return
+ * None.
+ */
+extern nss_tx_status_t nss_crypto_tx_buf(struct nss_ctx_instance *nss_ctx, uint32_t if_num, struct sk_buff *skb);
+
+/**
+ * nss_crypto_notify_register
+ *	Registers an event callback handler with the HLOS driver.
+ *
+ * @datatypes
+ * nss_crypto_msg_callback_t
+ *
+ * @param[in] cb        Callback function for the message.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern struct nss_ctx_instance *nss_crypto_notify_register(nss_crypto_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_crypto_data_register
+ *	Registers a data callback handler with the HLOS driver.
+ *
+ * @datatypes
+ * nss_crypto_buf_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num    NSS interface number.
+ * @param[in] cb        Callback function for the data.
+ * @param[in] netdev    Pointer to the network device.
+ * @param[in] features  Data socket buffer types supported by this interface.
+ *
+ * @return
+ * None.
+ */
+extern struct nss_ctx_instance *nss_crypto_data_register(uint32_t if_num, nss_crypto_buf_callback_t cb,
+		struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_crypto_pm_notify_register
+ *	Registers a power management event callback handler with the HLOS driver.
+ *
+ * @datatypes
+ * nss_crypto_pm_event_callback_t
+ *
+ * @param[in] cb        Callback function for the message.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_crypto_pm_notify_register(nss_crypto_pm_event_callback_t cb, void *app_data);
+
+/**
+ * nss_crypto_notify_unregister
+ *	Deregisters an event callback handler notifier from the HLOS driver.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in,out] ctx  Pointer to the context of the HLOS driver.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The event callback handler must have been previously registered.
+ */
+extern void nss_crypto_notify_unregister(struct nss_ctx_instance *ctx);
+
+/**
+ * nss_crypto_data_unregister
+ *	Deregisters a data callback handler from the HLOS driver.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in,out] ctx     Pointer to the context of the HLOS driver.
+ * @param[in]     if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The callback handler must have been previously registered.
+ */
+extern void nss_crypto_data_unregister(struct nss_ctx_instance *ctx, uint32_t if_num);
+
+/**
+ * nss_crypto_pm_notify_unregister
+ *	Deregisters a power management event callback handler from the HLOS driver.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The callback handler must have been previously registered.
+ */
+extern void nss_crypto_pm_notify_unregister(void);
+
+/**
+ * nss_crypto_msg_init
+ *	Initializes a crypto-specific message.
+ *
+ * @datatypes
+ * nss_crypto_msg \n
+ * nss_crypto_msg_callback_t
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_crypto_msg_init(struct nss_crypto_msg *ncm, uint16_t if_num, uint32_t type, uint32_t len,
+								nss_crypto_msg_callback_t cb, void *app_data);
+
+#endif /*__KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_CRYPTO_H */
diff --git a/qca-nss-drv/exports/nss_crypto_cmn.h b/qca-nss-drv/exports/nss_crypto_cmn.h
new file mode 100644
index 0000000..61b97f1
--- /dev/null
+++ b/qca-nss-drv/exports/nss_crypto_cmn.h
@@ -0,0 +1,460 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_crypto_cmn.h
+ *	NSS Crypto common interface definitions.
+ */
+#ifndef __NSS_CRYPTO_CMN_H
+#define __NSS_CRYPTO_CMN_H
+
+/**
+ * @addtogroup nss_crypto_subsystem
+ * @{
+ */
+
+/*
+ * Context message related array sizes
+ */
+#define NSS_CRYPTO_CMN_CTX_SPARE 4 /**< Context spare words size. */
+#define NSS_CRYPTO_CMN_VER_WORDS 4 /**< Firmware version words size.*/
+#define NSS_CRYPTO_CIPHER_KEYLEN_MAX 32 /**< Maximum cipher keysize. */
+#define NSS_CRYPTO_AUTH_KEYLEN_MAX 128 /**< Maximum authorization keysize. */
+#define NSS_CRYPTO_NONCE_SIZE_MAX 4 /**< Maximum authorization keysize. */
+
+/**
+ * nss_crypto_cmn_algo
+ *	List of crypto algorithms supported.
+ */
+enum nss_crypto_cmn_algo {
+	NSS_CRYPTO_CMN_ALGO_NULL,			/**< NULL transform. */
+	NSS_CRYPTO_CMN_ALGO_3DES_CBC,			/**< Asynchronous block cipher. */
+	NSS_CRYPTO_CMN_ALGO_AES128_CBC,			/**< Asynchronous block cipher. */
+	NSS_CRYPTO_CMN_ALGO_AES192_CBC,			/**< Asynchronous block cipher. */
+	NSS_CRYPTO_CMN_ALGO_AES256_CBC,			/**< Asynchronous block cipher. */
+	NSS_CRYPTO_CMN_ALGO_AES128_CTR,			/**< Asynchronous block cipher. */
+	NSS_CRYPTO_CMN_ALGO_AES192_CTR,			/**< Asynchronous block cipher. */
+	NSS_CRYPTO_CMN_ALGO_AES256_CTR,			/**< Asynchronous block cipher. */
+	NSS_CRYPTO_CMN_ALGO_AES128_ECB,			/**< Asynchronous block cipher. */
+	NSS_CRYPTO_CMN_ALGO_AES192_ECB,			/**< Asynchronous block cipher. */
+	NSS_CRYPTO_CMN_ALGO_AES256_ECB,			/**< Asynchronous block cipher. */
+	NSS_CRYPTO_CMN_ALGO_AES128_GCM,			/**< Asynchronous block cipher. */
+	NSS_CRYPTO_CMN_ALGO_AES192_GCM,			/**< Asynchronous block cipher. */
+	NSS_CRYPTO_CMN_ALGO_AES256_GCM,			/**< Asynchronous block cipher. */
+	NSS_CRYPTO_CMN_ALGO_MD5_HASH,			/**< Asynchronous digest. */
+	NSS_CRYPTO_CMN_ALGO_SHA160_HASH,		/**< Asynchronous digest. */
+	NSS_CRYPTO_CMN_ALGO_SHA224_HASH,		/**< Asynchronous digest. */
+	NSS_CRYPTO_CMN_ALGO_SHA256_HASH,		/**< Asynchronous digest. */
+	NSS_CRYPTO_CMN_ALGO_SHA384_HASH,		/**< Asynchronous digest. */
+	NSS_CRYPTO_CMN_ALGO_SHA512_HASH,		/**< Asynchronous digest. */
+	NSS_CRYPTO_CMN_ALGO_MD5_HMAC,			/**< Asynchronous digest. */
+	NSS_CRYPTO_CMN_ALGO_SHA160_HMAC,		/**< Asynchronous digest. */
+	NSS_CRYPTO_CMN_ALGO_SHA224_HMAC,		/**< Asynchronous digest. */
+	NSS_CRYPTO_CMN_ALGO_SHA256_HMAC,		/**< Asynchronous digest. */
+	NSS_CRYPTO_CMN_ALGO_SHA384_HMAC,		/**< Asynchronous digest. */
+	NSS_CRYPTO_CMN_ALGO_SHA512_HMAC,		/**< Asynchronous digest. */
+	NSS_CRYPTO_CMN_ALGO_AES128_GMAC,		/**< Asynchronous digest. */
+	NSS_CRYPTO_CMN_ALGO_AES192_GMAC,		/**< Asynchronous digest. */
+	NSS_CRYPTO_CMN_ALGO_AES256_GMAC,		/**< Asynchronous digest. */
+	NSS_CRYPTO_CMN_ALGO_AES128_GCM_GMAC,		/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES128_CBC_MD5_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES128_CBC_SHA160_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES128_CBC_SHA256_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES128_CBC_SHA384_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES128_CBC_SHA512_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES192_GCM_GMAC,		/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES192_CBC_MD5_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES192_CBC_SHA160_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES192_CBC_SHA256_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES192_CBC_SHA384_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES192_CBC_SHA512_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES256_GCM_GMAC,		/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES256_CBC_MD5_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES256_CBC_SHA160_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES256_CBC_SHA256_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES256_CBC_SHA384_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES256_CBC_SHA512_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES128_CTR_MD5_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES128_CTR_SHA160_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES128_CTR_SHA256_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES128_CTR_SHA384_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES128_CTR_SHA512_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES192_CTR_MD5_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES192_CTR_SHA160_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES192_CTR_SHA256_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES192_CTR_SHA384_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES192_CTR_SHA512_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES256_CTR_MD5_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES256_CTR_SHA160_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES256_CTR_SHA256_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES256_CTR_SHA384_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_AES256_CTR_SHA512_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_3DES_CBC_MD5_HMAC,		/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_3DES_CBC_SHA160_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_3DES_CBC_SHA256_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_3DES_CBC_SHA384_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_3DES_CBC_SHA512_HMAC,	/**< AEAD transform. */
+	NSS_CRYPTO_CMN_ALGO_MAX
+};
+
+/**
+ * nss_crypto_cmn_resp_error
+ *	Response errors from crypto hardware
+ */
+enum nss_crypto_cmn_resp_error {
+	NSS_CRYPTO_CMN_RESP_ERROR_NONE = 0,			/**< No error. */
+	NSS_CRYPTO_CMN_RESP_ERROR_HDR_VERSION,		/**< Header version mismatch. */
+	NSS_CRYPTO_CMN_RESP_ERROR_CTX_RANGE,		/**< Crypto index out-of-range. */
+	NSS_CRYPTO_CMN_RESP_ERROR_CTX_NOUSE,		/**< Crypto index is freed. */
+	NSS_CRYPTO_CMN_RESP_ERROR_DATA_EMPTY,		/**< Crypto data is empty. */
+	NSS_CRYPTO_CMN_RESP_ERROR_DATA_LEN,			/**< Crypto data length. */
+	NSS_CRYPTO_CMN_RESP_ERROR_DATA_TIMEOUT,		/**< Data timeout from hardware. */
+	NSS_CRYPTO_CMN_RESP_ERROR_CIPHER_ALGO,		/**< Cipher algorithm is not supported. */
+	NSS_CRYPTO_CMN_RESP_ERROR_CIPHER_MODE,		/**< Cipher mode is not supported. */
+	NSS_CRYPTO_CMN_RESP_ERROR_CIPHER_BLK_LEN,	/**< Cipher block length is not aligned. */
+	NSS_CRYPTO_CMN_RESP_ERROR_HASH_CHECK,		/**< Hash check failed. */
+	NSS_CRYPTO_CMN_RESP_ERROR_HASH_NOSPACE,		/**< No space to write hash. */
+	NSS_CRYPTO_CMN_RESP_ERROR_HW_STATUS,		/**< More errors in hardware status. */
+	NSS_CRYPTO_CMN_RESP_ERROR_MAX
+};
+
+/**
+ * nss_crypto_cmn_msg_type
+ *	Message types supported.
+ */
+enum nss_crypto_cmn_msg_type {
+	NSS_CRYPTO_CMN_MSG_TYPE_NONE = 0,		/**< Invalid message. */
+	NSS_CRYPTO_CMN_MSG_TYPE_SETUP_NODE,		/**< Initialize node. */
+	NSS_CRYPTO_CMN_MSG_TYPE_SETUP_ENG,		/**< Initialize engine. */
+	NSS_CRYPTO_CMN_MSG_TYPE_SETUP_DMA,		/**< Initialize DMA pair. */
+	NSS_CRYPTO_CMN_MSG_TYPE_SETUP_CTX,		/**< Update context information. */
+	NSS_CRYPTO_CMN_MSG_TYPE_CLEAR_CTX,		/**< Clear context information. */
+	NSS_CRYPTO_CMN_MSG_TYPE_VERIFY_CTX,		/**< Verify if context is active. */
+	NSS_CRYPTO_CMN_MSG_TYPE_SYNC_NODE_STATS,	/**< Synchronous node statistics. */
+	NSS_CRYPTO_CMN_MSG_TYPE_SYNC_ENG_STATS,		/**< Synchronous engine statistics. */
+	NSS_CRYPTO_CMN_MSG_TYPE_SYNC_CTX_STATS,		/**< Synchronous context statistics. */
+	NSS_CRYPTO_CMN_MSG_TYPE_MAX
+};
+
+/**
+ * nss_crypto_cmn_msg_error
+ *	Message error types supported.
+ */
+enum nss_crypto_cmn_msg_error {
+	NSS_CRYPTO_CMN_MSG_ERROR_NONE = 0,
+	NSS_CRYPTO_CMN_MSG_ERROR_HDR_VERSION_NOSUPP,	/**< Common header version not supported. */
+	NSS_CRYPTO_CMN_MSG_ERROR_NODE_CTX_RANGE,	/**< Context index out-of-range for node. */
+	NSS_CRYPTO_CMN_MSG_ERROR_DMA_MASK,		/**< DMA mask is out-of-range. */
+	NSS_CRYPTO_CMN_MSG_ERROR_DMA_POW2,		/**< DMA count is not a power-of-two. */
+	NSS_CRYPTO_CMN_MSG_ERROR_DMA_MAX_TOKEN,		/**< DMA count exceeds token count. */
+	NSS_CRYPTO_CMN_MSG_ERROR_DMA_TOKEN_ALLOC,	/**< Failed to allocate token. */
+	NSS_CRYPTO_CMN_MSG_ERROR_CTX_RANGE,		/**< Context index out-of-range. */
+	NSS_CRYPTO_CMN_MSG_ERROR_CTX_INUSE,		/**< Context has references. */
+	NSS_CRYPTO_CMN_MSG_ERROR_CTX_WORDS,		/**< Context size is bad. */
+	NSS_CRYPTO_CMN_MSG_ERROR_CTX_ALGO,		/**< Context algorithm is bad. */
+	NSS_CRYPTO_CMN_MSG_ERROR_CTX_ALLOC,		/**< Context alloc failed. */
+	NSS_CRYPTO_CMN_MSG_ERROR_CTX_NOUSE,		/**< Context has no references. */
+	NSS_CRYPTO_CMN_MSG_ERROR_CTX_FLAGS,		/**< Invalid context flags. */
+	NSS_CRYPTO_CMN_MSG_ERROR_MAX
+};
+
+/**
+ * nss_crypto_cmn_ctx_flags
+ *	Context message specific flags.
+ */
+enum nss_crypto_cmn_ctx_flags {
+	NSS_CRYPTO_CMN_CTX_FLAGS_NONE = 0,		/**< Invalid flags. */
+	NSS_CRYPTO_CMN_CTX_FLAGS_SEC_OFFSET = 0x01,	/**< Secure offset is valid. */
+	NSS_CRYPTO_CMN_CTX_FLAGS_SPARE0 = 0x02,		/**< Spare word-0 valid. */
+	NSS_CRYPTO_CMN_CTX_FLAGS_SPARE1 = 0x04,		/**< Spare word-1 valid. */
+	NSS_CRYPTO_CMN_CTX_FLAGS_SPARE2 = 0x08,		/**< Spare word-2 valid. */
+	NSS_CRYPTO_CMN_CTX_FLAGS_SPARE3 = 0x10,		/**< Spare word-3 valid. */
+	NSS_CRYPTO_CMN_CTX_FLAGS_MAX
+};
+
+/**
+ * nss_crypto_cmn_node
+ *	Node message for setting up the crypto node.
+ *
+ * Note: Upon boot this is the first message sent by Host to NSS crypto.
+ *	- It notifies the maximum number of crypto context.
+ *	- It notifies the maximum number of DMA rings.
+ *	- It returns the maximum size of crypto context record.
+ */
+struct nss_crypto_cmn_node {
+	uint32_t max_dma_rings;		/**< Maximum DMA rings supported. */
+	uint32_t max_ctx;		/**< Maximum contexts. */
+	uint32_t max_ctx_size;		/**< Maximum context size. */
+};
+
+/**
+ * nss_crypto_cmn_engine
+ *	Engine message for setting up the instance of crypto engine.
+ *
+ * Note: This is sent after 'node' message for each engine to
+ *	- Get valid DMA pairs supported by firmware.
+ *	- Get maximum request/token count available in firmware.
+ */
+struct nss_crypto_cmn_engine {
+	uint32_t fw_ver[NSS_CRYPTO_CMN_VER_WORDS];	/**< Firmware version. */
+	uint32_t dma_mask;				/**< Max DMA rings. */
+	uint32_t req_count;				/**< Token count. */
+};
+
+/**
+ * nss_crypto_cmn_dma
+ *	DMA message for setting up each DMA pair per engine.
+ */
+struct nss_crypto_cmn_dma {
+	uint16_t pair_id;		/**< DMA pair ID. */
+};
+
+/**
+ * nss_crypto_cmn_ctx
+ *	Context message for setting up a crypto context in firmware.
+ */
+struct nss_crypto_cmn_ctx {
+	uint32_t spare[NSS_CRYPTO_CMN_CTX_SPARE];	/**< Context spare words. */
+	uint16_t index;					/**< Crypto index. */
+	uint16_t sec_offset;				/**< Secure offset for copying keys. */
+
+	uint8_t cipher_key[NSS_CRYPTO_CIPHER_KEYLEN_MAX];	/**< Array containing cipher keys. */
+	uint8_t auth_key[NSS_CRYPTO_AUTH_KEYLEN_MAX];	/**< Array containing authorization keys. */
+	uint8_t nonce[NSS_CRYPTO_NONCE_SIZE_MAX];		/**< Nonce value. */
+
+	uint16_t auth_keylen;				/**< Authorization key length. */
+	uint8_t res[2];					/**< Reserved. */
+
+	enum nss_crypto_cmn_algo algo;			/**< Crypto algorithm. */
+	enum nss_crypto_cmn_ctx_flags flags;		/**< Context specific flags. */
+};
+
+/**
+ * nss_crypto_cmn_stats
+ *	Statistics message applicable for node/engine/context.
+ */
+struct nss_crypto_cmn_stats {
+	struct nss_cmn_node_stats nstats;	/**< Common node statistics. */
+	uint32_t fail_version;			/**< Version mismatch failures. */
+	uint32_t fail_ctx;			/**< Context related failures. */
+	uint32_t fail_dma;			/**< DMA descriptor full. */
+};
+
+/**
+ * nss_crypto_cmn_msg
+ *	Crypto common configuration message.
+ */
+struct nss_crypto_cmn_msg {
+	struct nss_cmn_msg cm;				/**< Common header. */
+	uint32_t seq_num;				/**< Sequence number for messages. */
+	uint32_t uid;					/**< Unique ID to identify engine and context. */
+
+	union {
+		struct nss_crypto_cmn_node node;	/**< Node message. */
+		struct nss_crypto_cmn_engine eng;	/**< Engine message. */
+		struct nss_crypto_cmn_dma dma;		/**< DMA message. */
+		struct nss_crypto_cmn_ctx ctx;		/**< Context message. */
+		struct nss_crypto_cmn_stats stats;	/**< Statistics message. */
+	} msg;
+};
+
+#ifdef __KERNEL__  /* only kernel will use */
+
+/**
+ * Callback function for receiving crypto transformation upon completion.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Networking device registered for callback.
+ * @param[in] skb     Packet buffer.
+ * @param[in] napi    NAPI pointer for Linux NAPI handling.
+ *
+ * @return
+ * None.
+ */
+typedef void (*nss_crypto_cmn_buf_callback_t)(struct net_device *netdev, struct sk_buff *skb,
+						struct napi_struct *napi);
+
+/**
+ * Callback function for receiving crypto_cmn messages.
+ *
+ * @datatypes
+ * nss_crypto_cmn_msg
+ *
+ * @param[in] app_data  Context of the callback user.
+ * @param[in] msg       Crypto common message.
+ *
+ * @return
+ * None.
+ */
+typedef void (*nss_crypto_cmn_msg_callback_t)(void *app_data, struct nss_crypto_cmn_msg *msg);
+
+/**
+ * nss_crypto_cmn_tx_buf
+ *	Send crypto payload to firmware for transformation.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  NSS context per NSS core.
+ * @param[in] if_num   Crypto interface to send the buffer.
+ * @param[in] skb      Crypto payload.
+ *
+ * @return
+ * Status of the TX operation.
+ */
+extern nss_tx_status_t nss_crypto_cmn_tx_buf(struct nss_ctx_instance *nss_ctx, uint32_t if_num, struct sk_buff *skb);
+
+/**
+ * nss_crypto_cmn_tx_msg
+ *	Send crypto message to firmware for configuration.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_crypto_cmn_msg
+ *
+ * @param[in] nss_ctx]  NSS context per NSS core.
+ * @param[in] msg       Control message.
+ *
+ * @return
+ * Status of the TX operation.
+ */
+extern nss_tx_status_t nss_crypto_cmn_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_crypto_cmn_msg *msg);
+
+/**
+ * nss_crypto_cmn_tx_msg
+ *	Send crypto message to firmware for configuration synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_crypto_cmn_msg
+ *
+ * @param[in]     nss_ctx  NSS context per NSS core.
+ * @param[in,out] msg      Crypto message, response data is copied.
+ *
+ * @return
+ * Status of the TX operation.
+ *
+ * @note
+ * Response data for the  message is copied into the 'msg'.
+ * The caller should read the content of the 'msg' to find out errors.
+ * The caller needs to invoke this from a non-atomic context.
+ */
+extern nss_tx_status_t nss_crypto_cmn_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_crypto_cmn_msg *msg);
+
+/**
+ * nss_crypto_cmn_notify_register
+ *	Register a event callback handler with NSS driver
+ *
+ * @datatypes
+ * nss_crypto_cmn_msg_callback_t
+ *
+ * @param[in] cb        Event callback function.
+ * @param[in] app_data  Context of the callback user.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_crypto_cmn_notify_register(nss_crypto_cmn_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_crypto_cmn_notify_unregister
+ *	De-register the event callback handler with NSS driver.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] ctx  Pointer to the NSS context per NSS core.
+ *
+ * @return
+ * None.
+ */
+extern void nss_crypto_cmn_notify_unregister(struct nss_ctx_instance *ctx);
+
+/**
+ * nss_crypto_cmn_data_register
+ *	Crypto data register.
+ *
+ * @datatypes
+ * nss_crypto_cmn_buf_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num    Interface number.
+ * @param[in] cb        Callback function.
+ * @param[in] netdev    Net device.
+ * @param[in] features  Features supported.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_crypto_cmn_data_register(uint32_t if_num,
+						nss_crypto_cmn_buf_callback_t cb,
+						struct net_device *netdev,
+						uint32_t features);
+
+/**
+ * nss_crypto_cmn_data_unregister
+ *	Crypto data de-register.
+ *
+ * @param[in] ctx     NSS context per NSS core.
+ * @param[in] if_num  Interface number.
+ *
+ * @return
+ * None.
+ */
+extern void nss_crypto_cmn_data_unregister(struct nss_ctx_instance *ctx, uint32_t if_num);
+
+/**
+ * nss_crypto_cmn_get_context
+ *	Get the per NSS core context enabled for crypto.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_crypto_cmn_get_context(void);
+
+/**
+ * nss_crypto_cmn_msg_init
+ *	Crypto common message initialization.
+ *
+ * @datatypes
+ * nss_crypto_cmn_msg \n
+ * nss_crypto_cmn_msg_callback_t
+ *
+ * @param[in] ncm       Crypto common message.
+ * @param[in] if_num    Interface number.
+ * @param[in] type      Message type.
+ * @param[in] len       Common message length.
+ * @param[in] cb        Callback function.
+ * @param[in] app_data  Appllication data.
+ *
+ * @return
+ * None.
+ */
+extern void nss_crypto_cmn_msg_init(struct nss_crypto_cmn_msg *ncm, uint16_t if_num,
+				uint32_t type, uint32_t len, nss_crypto_cmn_msg_callback_t cb,
+				void *app_data);
+
+#endif /*__KERNEL__ */
+
+/**
+ * @}
+ */
+#endif
diff --git a/qca-nss-drv/exports/nss_def.h b/qca-nss-drv/exports/nss_def.h
new file mode 100644
index 0000000..9bfab79
--- /dev/null
+++ b/qca-nss-drv/exports/nss_def.h
@@ -0,0 +1,57 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_def.h
+ *	NSS definitions
+ */
+
+#ifndef __NSS_DEF_H
+#define __NSS_DEF_H
+
+/**
+ * @addtogroup nss_common_subsystem
+ * @{
+ */
+
+#define NSS_ETH_NORMAL_FRAME_MTU 1500		/**< MTU of a normal frame.*/
+#define NSS_ETH_MINI_JUMBO_FRAME_MTU 1978	/**< MTU of a mini-jumbo frame. */
+#define NSS_ETH_FULL_JUMBO_FRAME_MTU 9600	/**< MTU of a full jumbo frame. */
+
+/**
+ * Number of ingress or egress VLANS supported in a connection entry.
+ */
+#define MAX_VLAN_DEPTH 2
+
+/**
+ * Number of egress interfaces supported in a multicast connection entry.
+ */
+#define NSS_MC_IF_MAX 16
+
+/**
+ * Real pointer size of the system.
+ */
+#ifdef __LP64__
+typedef uint64_t nss_ptr_t;
+#else
+typedef uint32_t nss_ptr_t;
+#endif
+
+/**
+ * @}
+ */
+
+#endif /** __NSS_DEF_H */
diff --git a/qca-nss-drv/exports/nss_dma.h b/qca-nss-drv/exports/nss_dma.h
new file mode 100755
index 0000000..d0aaa01
--- /dev/null
+++ b/qca-nss-drv/exports/nss_dma.h
@@ -0,0 +1,333 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+/**
+ * @file nss_dma.h
+ *	NSS DMA for linearization and split interface definitions.
+ */
+
+#ifndef __NSS_DMA_H
+#define __NSS_DMA_H
+
+/**
+ * @addtogroup nss_dma_subsystem
+ * @{
+ */
+
+/**
+ * nss_dma_msg_type
+ *	Supported message types.
+ */
+enum nss_dma_msg_type {
+	NSS_DMA_MSG_TYPE_NONE,			/**< Invalid message type. */
+	NSS_DMA_MSG_TYPE_CONFIGURE,		/**< Configure DMA. */
+	NSS_DMA_MSG_TYPE_SYNC_STATS,		/**< Statistics synchronization. */
+	NSS_DMA_MSG_TYPE_TEST_PERF,		/**< Performance test. */
+	NSS_DMA_MSG_TYPE_MAX			/**< Maximum message type. */
+};
+
+/**
+ * nss_dma_msg_error
+ *	Message error types.
+ */
+enum nss_dma_msg_error {
+	NSS_DMA_MSG_ERROR_NONE,			/**< No error. */
+	NSS_DMA_MSG_ERROR_HW_INIT,		/**< Invalid operation. */
+	NSS_DMA_MSG_ERROR_UNHANDLED,		/**< Invalid test ID. */
+	NSS_DMA_MSG_ERROR_TEST,			/**< Performance test failed. */
+	NSS_DMA_MSG_ERROR_MAX			/**< Maximum error type. */
+};
+
+/**
+ * nss_dma_stats_types
+ *	DMA node statistics.
+ */
+enum nss_dma_stats_types {
+	NSS_DMA_STATS_NO_REQ = NSS_STATS_NODE_MAX,
+					/**< Request descriptor not available. */
+	NSS_DMA_STATS_NO_DESC,		/**< DMA descriptors not available. */
+	NSS_DMA_STATS_NEXTHOP,		/**< Failed to retrive next hop. */
+	NSS_DMA_STATS_FAIL_NEXTHOP_QUEUE,
+					/**< Failed to queue next hop. */
+	NSS_DMA_STATS_FAIL_LINEAR_SZ,	/**< Failed to get memory for linearization. */
+	NSS_DMA_STATS_FAIL_LINEAR_ALLOC,/**< Failed to allocate buffer for linearization. */
+	NSS_DMA_STATS_FAIL_LINEAR_NO_SG,/**< Skip linearization due to non-SG packet. */
+	NSS_DMA_STATS_FAIL_SPLIT_SZ,	/**< Failed to spliting buffer into multiple buffers. */
+	NSS_DMA_STATS_FAIL_SPLIT_ALLOC,	/**< Failed to allocate buffer for split. */
+	NSS_DMA_STATS_FAIL_SYNC_ALLOC,	/**< Failed to allocate buffer for sending statistics. */
+	NSS_DMA_STATS_FAIL_CTX_ACTIVE,	/**< Failed to queue as the node is not active. */
+	NSS_DMA_STATS_FAIL_HW_E0,	/**< Failed to process in hardware, error code E0. */
+	NSS_DMA_STATS_FAIL_HW_E1,	/**< Failed to process in hardware, error code E1. */
+	NSS_DMA_STATS_FAIL_HW_E2,	/**< Failed to process in hardware, error code E2. */
+	NSS_DMA_STATS_FAIL_HW_E3,	/**< Failed to process in hardware, error code E3. */
+	NSS_DMA_STATS_FAIL_HW_E4,	/**< Failed to process in hardware, error code E4. */
+	NSS_DMA_STATS_FAIL_HW_E5,	/**< Failed to process in hardware, error code E5. */
+	NSS_DMA_STATS_FAIL_HW_E6,	/**< Failed to process in hardware, error code E6. */
+	NSS_DMA_STATS_FAIL_HW_E7,	/**< Failed to process in hardware, error code E7. */
+	NSS_DMA_STATS_FAIL_HW_E8,	/**< Failed to process in hardware, error code E8. */
+	NSS_DMA_STATS_FAIL_HW_E9,	/**< Failed to process in hardware, error code E9. */
+	NSS_DMA_STATS_FAIL_HW_E10,	/**< Failed to process in hardware, error code E10. */
+	NSS_DMA_STATS_FAIL_HW_E11,	/**< Failed to process in hardware, error code E11. */
+	NSS_DMA_STATS_FAIL_HW_E12,	/**< Failed to process in hardware, error code E12. */
+	NSS_DMA_STATS_FAIL_HW_E13,	/**< Failed to process in hardware, error code E13. */
+	NSS_DMA_STATS_FAIL_HW_E14,	/**< Failed to process in hardware, error code E14. */
+	NSS_DMA_STATS_FAIL_HW_E15,	/**< Failed to process in hardware, error code E15. */
+	NSS_DMA_STATS_MAX,		/**< Maximum message type. */
+};
+
+/**
+ * nss_dma_test_type
+ *	DMA Test types.
+ */
+enum nss_dma_test_type {
+	NSS_DMA_TEST_TYPE_DEFAULT = 0,		/**< Test default segment size. */
+	NSS_DMA_TEST_TYPE_SWEEP,		/**< Test sweep segment size. */
+	NSS_DMA_TEST_TYPE_LARGE,		/**< Test large segment size. */
+	NSS_DMA_TEST_TYPE_VERIFY,		/**< Verify contents at receive processing. */
+	NSS_DMA_TEST_TYPE_MAX			/**< Maximum test type. */
+};
+
+/**
+ * nss_dma_stats_notification
+ *	DMA transmission statistics structure.
+ */
+struct nss_dma_stats_notification {
+	uint64_t stats_ctx[NSS_DMA_STATS_MAX];		/**< Context transmission statistics. */
+	uint32_t core_id;				/**< Core ID. */
+};
+
+#ifdef __KERNEL__ /* only kernel will use. */
+/*
+ * Maximum number of HW specific statistics
+ */
+#define NSS_DMA_HW_ERROR_MAX 16
+
+/*
+ * Test configuration flags
+ */
+#define NSS_DMA_TEST_FLAGS_LINEARIZE 0x01	/**< Linearize test. */
+#define NSS_DMA_TEST_FLAGS_SPLIT 0x02		/**< Split test. */
+
+/**
+ * nss_dma_test_cfg
+ *	Test configuration.
+ */
+struct nss_dma_test_cfg {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics for DMA interface. */
+	uint32_t flags;				/**< Test configuration flags. */
+	uint32_t time_delta;			/**< Difference between start and end. */
+	uint16_t packet_count;			/**< Number of packets to send. */
+	uint16_t type;				/**< Type of test to run. */
+};
+
+/**
+ * nss_dma_stats
+ *	DMA statistics.
+ */
+struct nss_dma_stats {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics for DMA interface. */
+	uint32_t no_req;			/**< Request descriptor not available. */
+	uint32_t no_desc;			/**< DMA descriptors not available. */
+	uint32_t fail_nexthop;			/**< Failed to retrive next hop. */
+	uint32_t fail_nexthop_queue;		/**< Failed to queue next hop. */
+	uint32_t fail_linear_sz;		/**< Failed to get memory for linearization. */
+	uint32_t fail_linear_alloc;		/**< Failed to allocate buffer for linearization. */
+	uint32_t fail_linear_no_sg;		/**< Skip linearization due to non-SG packet. */
+	uint32_t fail_split_sz;			/**< Failed to spliting buffer into multiple buffers. */
+	uint32_t fail_split_alloc;		/**< Failed to allocate buffer for split. */
+	uint32_t fail_sync_alloc;		/**< Failed to allocate buffer for sending statistics. */
+	uint32_t fail_ctx_active;		/**< Failed to queue as the node is not active. */
+	uint32_t fail_hw[NSS_DMA_HW_ERROR_MAX]; /**< Hardware failures. */
+};
+
+/**
+ * nss_dma_msg
+ *	Message structure for configuring the DMA interface.
+ */
+struct nss_dma_msg {
+	struct nss_cmn_msg cm;			/**< Common message header. */
+
+	/**
+	 * Payload of a NSS core-to-core transmission rule or statistics message.
+	 */
+	union {
+		struct nss_dma_test_cfg test_cfg;
+						/**< DMA test configuration. */
+		struct nss_dma_stats stats;	/**< DMA interface statistics. */
+	} msg;					/**< Message payload. */
+};
+
+/**
+ * nss_dma_register_handler
+ *	Registers the DMA message handler.
+ *
+ * @return
+ * None.
+ */
+void nss_dma_register_handler(void);
+
+/**
+ * Callback function for receiving DMA messages.
+ *
+ * @datatypes
+ * nss_c2c_tx_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_dma_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * nss_dma_tx_msg
+ *	Transmits a DMA message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_dma_msg
+ *
+ * @param[in] nss_ctx   Pointer to the NSS context.
+ * @param[in] ndm      Pointer to the message data.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+extern nss_tx_status_t nss_dma_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_dma_msg *ndm);
+
+/**
+ * nss_dma_msg_init
+ *	Initializes DMA messages.
+ *
+ * @datatypes
+ * nss_dma_msg \n
+ * nss_dma_msg_callback_t
+ *
+ * @param[in]     ndm       Pointer to the NSS interface message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_dma_msg_init(struct nss_dma_msg *ndm, uint16_t if_num, uint32_t type, uint32_t len,
+			nss_dma_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_dma_notify_register
+ *	Registers a notifier callback for DMA messages with the NSS.
+ *
+ * @datatypes
+ * nss_dma_msg_callback_t
+ *
+ * @param[in] core      NSS core number index to the notifier callback table.
+ * @param[in] cb        Callback function for the message.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_dma_notify_register(int core, nss_dma_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_dma_notify_unregister
+ *	Deregisters a DMA message notifier callback from the NSS.
+ *
+ * @param[in] core  NSS core number index to the notifier callback table.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The notifier callback must have been previously registered.
+ */
+void nss_dma_notify_unregister(int core);
+
+/**
+ * nss_dma_register_sysctl
+ *     Registers the DMA interface to Linux system control tree.
+ *
+ * @return
+ * None.
+ */
+extern void nss_dma_register_sysctl(void);
+
+/**
+ * nss_dma_unregister_sysctl
+ *     Deregisters the DMA interface from Linux system control tree.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The system control must have been previously registered.
+ */
+extern void nss_dma_unregister_sysctl(void);
+
+/**
+ * nss_dma_init
+ *	Initializes the DMA interface.
+ *
+ * @return
+ * None.
+ */
+void nss_dma_init(void);
+
+/**
+ * nss_dma_get_context
+ *	Get the per NSS core context enabled for DMA.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_dma_get_context(void);
+
+/**
+ * nss_dma_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_dma_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * nss_dma_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_dma_stats_register_notifier(struct notifier_block *nb);
+#endif /*__KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_C2C_TX_H */
diff --git a/qca-nss-drv/exports/nss_dtls.h b/qca-nss-drv/exports/nss_dtls.h
new file mode 100644
index 0000000..d237bfd
--- /dev/null
+++ b/qca-nss-drv/exports/nss_dtls.h
@@ -0,0 +1,335 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_dtls.h
+ *	NSS DTLS interface definitions.
+ */
+
+#ifndef _NSS_DTLS_H_
+#define _NSS_DTLS_H_
+
+/**
+ * @addtogroup nss_dtls_subsystem
+ * @{
+ */
+
+#define NSS_MAX_DTLS_SESSIONS 8		/**< Maximum number of supported DTLS sessions. */
+
+/**
+ * nss_dtls_metadata_types
+ *	Message types for DTLS requests and responses.
+ */
+enum nss_dtls_metadata_types {
+	NSS_DTLS_MSG_SESSION_CONFIGURE,
+	NSS_DTLS_MSG_SESSION_DESTROY,
+	NSS_DTLS_MSG_SESSION_STATS,
+	NSS_DTLS_MSG_REKEY_ENCAP_CIPHER_UPDATE,
+	NSS_DTLS_MSG_REKEY_ENCAP_CIPHER_SWITCH,
+	NSS_DTLS_MSG_REKEY_DECAP_CIPHER_UPDATE,
+	NSS_DTLS_MSG_REKEY_DECAP_CIPHER_SWITCH,
+	NSS_DTLS_MSG_MAX
+};
+
+/**
+ * nss_dtls_error_response_types
+ *	Error types for DTLS responses.
+ */
+enum nss_dtls_error_response_types {
+	NSS_DTLS_ERR_UNKNOWN_MSG = 1,
+	NSS_DTLS_ERR_INVALID_APP_IF = 2,
+	NSS_DTLS_ERR_INVALID_CPARAM = 3,
+	NSS_DTLS_ERR_INVALID_VER = 4,
+	NSS_DTLS_ERR_NOMEM = 5,
+	NSS_DTLS_ERR_MAX,
+};
+
+/**
+ * nss_dtls_session_stats
+ *	DTLS session statistics.
+ */
+struct nss_dtls_session_stats {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics. */
+	uint32_t tx_auth_done;		/**< Tx authentication is done. */
+	uint32_t rx_auth_done;		/**< Rx authentication is successful. */
+	uint32_t tx_cipher_done;	/**< Tx cipher is complete. */
+	uint32_t rx_cipher_done;	/**< Rx cipher is complete. */
+	uint32_t tx_cbuf_alloc_fail;	/**< Tx crypto buffer allocation failure. */
+	uint32_t rx_cbuf_alloc_fail;	/**< Rx crypto buffer allocation failure. */
+	uint32_t tx_cenqueue_fail;	/**< Tx enqueue-to-crypto failure. */
+	uint32_t rx_cenqueue_fail;	/**< Rx enqueue-to-crypto failure. */
+	uint32_t tx_dropped_hroom;
+			/**< Tx packets dropped because of insufficent headroom. */
+	uint32_t tx_dropped_troom;
+			/**< Tx packets dropped because of insufficent tailroom. */
+	uint32_t tx_forward_enqueue_fail;
+			/**< Tx enqueue failed to forward a node after encapsulation. */
+	uint32_t rx_forward_enqueue_fail;
+			/**< Rx enqueue failed to receive a node after decapsulation. */
+	uint32_t rx_invalid_version;	/**< Rx invalid DTLS version. */
+	uint32_t rx_invalid_epoch;	/**< Rx invalid DTLS epoch. */
+	uint32_t rx_malformed;		/**< Rx malformed DTLS record. */
+	uint32_t rx_cipher_fail;	/**< Rx cipher failure. */
+	uint32_t rx_auth_fail;		/**< Rx authentication failure. */
+	uint32_t rx_capwap_classify_fail;	/**< Rx CAPWAP classification failure. */
+	uint32_t rx_single_rec_dgram;	/**< Rx single record datagrams processed. */
+	uint32_t rx_multi_rec_dgram;	/**< Rx multi-record datagrams processed. */
+	uint32_t rx_replay_fail;	/**< Rx anti-replay failures. */
+	uint32_t rx_replay_duplicate;
+			/**< Rx anti-replay failed because of a duplicate record. */
+	uint32_t rx_replay_out_of_window;
+			/**< Rx anti-replay failed because of an out-of-window record. */
+	uint32_t outflow_queue_full;
+			/**< Tx packets dropped because the encapsulation queue is full. */
+	uint32_t decap_queue_full;
+			/**< Rx packets dropped because the decapsulation queue is full. */
+	uint32_t pbuf_alloc_fail;
+			/**< Packets dropped because of a buffer allocation failure. */
+	uint32_t pbuf_copy_fail;
+			/**< Packets dropped because of a buffer copy failure. */
+	uint16_t epoch;		/**< Current epoch. */
+	uint16_t tx_seq_high;	/**< Upper 16 bits of the current sequence number. */
+	uint32_t tx_seq_low;	/**< Lower 32 bits of the current sequence number. */
+};
+
+/**
+ * nss_dtls_session_cipher_update
+ *	Information for a cipher update message in a DTLS session.
+ */
+struct nss_dtls_session_cipher_update {
+	uint32_t crypto_idx;	/**< Crypto index for encapsulation. */
+	uint32_t hash_len;	/**< Authentication hash length for encapsulation. */
+	uint32_t iv_len;	/**< Crypto IV length for encapsulation. */
+	uint32_t cipher_algo;	/**< Encapsulation cipher. */
+	uint32_t auth_algo;	/**< Encapsulation authentication algorithm. */
+	uint16_t epoch;		/**< Epoch indicator. */
+	uint16_t reserved;	/**< Reserved for message alignment.*/
+};
+
+/**
+ * nss_dtls_session_configure
+ *	Configuration message for a DTLS session.
+ */
+struct nss_dtls_session_configure {
+	uint32_t ver;			/**< DTLS version. */
+	uint32_t flags;			/**< DTLS flags. */
+	uint32_t crypto_idx_encap;	/**< Crypto index for encapsulation. */
+	uint32_t crypto_idx_decap;	/**< Crypto index for decapsulation. */
+	uint32_t iv_len_encap;		/**< Crypto IV length for encapsulation. */
+	uint32_t iv_len_decap;		/**< Crypto IV length for decapsulation. */
+	uint32_t hash_len_encap;
+			/**< Authentication hash length for encapsulation. */
+	uint32_t hash_len_decap;
+			/**< Authentication hash length for decapsulation. */
+	uint32_t cipher_algo_encap;	/**< Cipher algorithm for encapsulation. */
+	uint32_t auth_algo_encap;	/**< Authentication algorithm encapsulation. */
+	uint32_t cipher_algo_decap;	/**< Cipher algorithm for decapsulation. */
+	uint32_t auth_algo_decap;	/**< Authentication algorithm decapsulation. */
+	uint32_t nss_app_if;
+			/**< Interface of the node that receives decapsulated packets. */
+	uint16_t sport;			/**< Source UDP/UDPLite port. */
+	uint16_t dport;			/**< Destination UDP/UDPLite port. */
+	uint32_t sip[4];		/**< Source IPv4/IPv6 address. */
+	uint32_t dip[4];		/**< Destination IPv4/IPv6 address. */
+	uint16_t window_size;		/**< Anti-replay window size. */
+	uint16_t epoch;			/**< Epoch indicator. */
+	uint8_t oip_ttl;		/**< Maximum outer IP time-to-live value. */
+	uint8_t reserved1;		/**< Reserved for message alignment. */
+	uint16_t reserved2;		/**< Reserved for message alignment. */
+};
+
+/**
+ * nss_dtls_msg
+ *	Data for sending and receiving DTLS messages.
+ */
+struct nss_dtls_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a DTLS message.
+	 */
+	union {
+		struct nss_dtls_session_configure cfg;
+				/**< Session configuration. */
+		struct nss_dtls_session_cipher_update cipher_update;
+				/**< Cipher update information. */
+		struct nss_dtls_session_stats stats;
+				/**< Session statistics. */
+	} msg;			/**< Message payload for DTLS session messages exchanged with NSS core. */
+};
+
+/**
+ * nss_dtls_tx_buf
+ *	Sends a DTLS data packet to the NSS.
+ *
+ * @datatypes
+ * sk_buff \n
+ * nss_ctx_instance
+ *
+ * @param[in]     os_buf   Pointer to the OS data buffer.
+ * @param[in]     if_num   NSS interface number.
+ * @param[in]     nss_ctx  Pointer to the NSS core context.
+ *
+ * @return
+ * Status of Tx buffer forwarded to NSS for DTLS operation.
+ */
+nss_tx_status_t nss_dtls_tx_buf(struct sk_buff *os_buf, uint32_t if_num,
+				struct nss_ctx_instance *nss_ctx);
+
+/**
+ * nss_dtls_tx_msg
+ *	Sends DTLS messages.
+ *
+ * @param[in]     nss_ctx  Pointer to the NSS core context.
+ * @param[in,out] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_dtls_tx_msg(struct nss_ctx_instance *nss_ctx,
+				       struct nss_dtls_msg *msg);
+
+/**
+ * nss_dtls_tx_msg_sync
+ *	Sends DTLS messages synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_dtls_msg
+ *
+ * @param[in]     nss_ctx  Pointer to the NSS context.
+ * @param[in,out] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_dtls_tx_msg_sync(struct nss_ctx_instance *nss_ctx,
+					    struct nss_dtls_msg *msg);
+
+/**
+ * Callback function for receiving DTLS messages.
+ *
+ * @datatypes
+ * nss_dtls_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_dtls_msg_callback_t)(void *app_data,
+					struct nss_dtls_msg *msg);
+
+/**
+ * Callback function for receiving DTLS session data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_dtls_data_callback_t)(struct net_device *netdev,
+					struct sk_buff *skb,
+					struct napi_struct *napi);
+
+/**
+ * nss_dtls_register_if
+ *	Registers a DTLS session interface with the NSS for sending and receiving
+ *	messages.
+ *
+ * @datatypes
+ * nss_dtls_data_callback_t \n
+ * nss_dtls_msg_callback_t
+ *
+ * @param[in] if_num        NSS interface number.
+ * @param[in] cb            Callback function for the message.
+ * @param[in] msg_callback  Callback for DTLS tunnel message.
+ * @param[in] netdev        Pointer to the associated network device.
+ * @param[in] features      Data socket buffer types supported by this interface.
+ * @param[in] app_ctx       Pointer to the application context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_dtls_register_if(uint32_t if_num,
+							nss_dtls_data_callback_t cb,
+							nss_dtls_msg_callback_t msg_callback,
+							struct net_device *netdev,
+							uint32_t features,
+							void *app_ctx);
+
+/**
+ * nss_dtls_unregister_if
+ *	Deregisters a DTLS session interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The DTLS session interface must have been previously registered.
+ */
+extern void nss_dtls_unregister_if(uint32_t if_num);
+
+/**
+ * nss_dtls_msg_init
+ *	Initializes a DTLS message.
+ *
+ * @datatypes
+ * nss_dtls_msg
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Pointer to the message callback.
+ * @param[in]     app_data  Pointer to the application context.
+ *
+ * @return
+ * None.
+ */
+extern void nss_dtls_msg_init(struct nss_dtls_msg *ncm, uint16_t if_num,
+				uint32_t type, uint32_t len, void *cb,
+				void *app_data);
+
+/**
+ * nss_dtls_get_context
+ *	Gets the NSS core context for the DTLS session.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_dtls_get_context(void);
+
+/**
+ * nss_dtls_get_ifnum_with_coreid
+ *	Gets the DTLS interface number with a core ID.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * Interface number with the core ID.
+ */
+extern int32_t nss_dtls_get_ifnum_with_coreid(int32_t if_num);
+
+/**
+ * @}
+ */
+
+#endif /* _NSS_DTLS_H_. */
diff --git a/qca-nss-drv/exports/nss_dtls_cmn.h b/qca-nss-drv/exports/nss_dtls_cmn.h
new file mode 100644
index 0000000..78b1663
--- /dev/null
+++ b/qca-nss-drv/exports/nss_dtls_cmn.h
@@ -0,0 +1,512 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_dtls_cmn.h
+ *	NSS DTLS common interface definitions, supports inner/outer interface split.
+ */
+
+#ifndef _NSS_DTLS_CMN_H_
+#define _NSS_DTLS_CMN_H_
+
+/**
+ * @addtogroup nss_dtls_subsystem
+ * @{
+ */
+
+#define NSS_DTLS_CMN_CTX_HDR_IPV6 0x0001		/**< DTLS with IPv6. */
+#define NSS_DTLS_CMN_CTX_HDR_UDPLITE 0x0002		/**< DTLS with UDPLite. */
+#define NSS_DTLS_CMN_CTX_HDR_CAPWAP 0x0004		/**< DTLS with CAPWAP. */
+#define NSS_DTLS_CMN_CTX_CIPHER_MODE_GCM 0x0008		/**< DTLS with GCM cipher mode. */
+#define NSS_DTLS_CMN_CTX_ENCAP_UDPLITE_CSUM 0x10000	/**< Checksum only UDPLite header. */
+#define NSS_DTLS_CMN_CTX_ENCAP_METADATA 0x20000		/**< Valid metadata in encapsulation direction. */
+#define NSS_DTLS_CMN_CTX_DECAP_ACCEPT_ALL 0x40000	/**< Exception all error packets to host. */
+
+#define NSS_DTLS_CMN_CLE_MAX 32				/**< Max classification error. */
+
+/**
+ * nss_dtls_cmn_metadata_types
+ *	Message types for DTLS requests and responses.
+ */
+enum nss_dtls_cmn_msg_type {
+	NSS_DTLS_CMN_MSG_TYPE_CONFIGURE_NODE,	/**< Configure DTLS firmware node. */
+	NSS_DTLS_CMN_MSG_TYPE_CONFIGURE_HDR,	/**< Configure the base context parameter. */
+	NSS_DTLS_CMN_MSG_TYPE_CONFIGURE_DTLS,	/**< Configure DTLS parameters. */
+	NSS_DTLS_CMN_MSG_TYPE_SWITCH_DTLS,	/**< Switch to new DTLS transform. */
+	NSS_DTLS_CMN_MSG_TYPE_DECONFIGURE,	/**< Deconfigure context. */
+	NSS_DTLS_CMN_MSG_TYPE_SYNC_STATS,	/**< Synchronize statistics. */
+	NSS_DTLS_CMN_MSG_TYPE_NODE_STATS,	/**< Node statistics. */
+	NSS_DTLS_CMN_MSG_MAX
+};
+
+/**
+ * nss_dtls_cmn_error_response_types
+ *	Error types for DTLS responses.
+ */
+enum nss_dtls_cmn_error {
+	NSS_DTLS_CMN_ERROR_NONE = 0,
+	NSS_DTLS_CMN_ERROR_UNKNOWN_MSG,
+	NSS_DTLS_CMN_ERROR_INVALID_DESTIF,
+	NSS_DTLS_CMN_ERROR_INVALID_SRCIF,
+	NSS_DTLS_CMN_ERROR_INVALID_CRYPTO,
+	NSS_DTLS_CMN_ERROR_INVALID_VER,
+	NSS_DTLS_CMN_ERROR_INVALID_CTX_TYPE,
+	NSS_DTLS_CMN_ERROR_INVALID_CTX_WORDS,
+	NSS_DTLS_CMN_ERROR_FAIL_ALLOC_HWCTX,
+	NSS_DTLS_CMN_ERROR_FAIL_COPY_CTX,
+	NSS_DTLS_CMN_ERROR_FAIL_SWITCH_HWCTX,
+	NSS_DTLS_CMN_ERROR_ALREADY_CONFIGURED,
+	NSS_DTLS_CMN_ERROR_FAIL_NOMEM,
+	NSS_DTLS_CMN_ERROR_FAIL_COPY_NONCE,
+	NSS_DTLS_CMN_ERROR_MAX,
+};
+
+/**
+ * nss_dtls_cmn_ctx_stats_types
+ *	DTLS common context statistics types.
+ */
+enum nss_dtls_cmn_ctx_stats_types {
+	NSS_DTLS_CMN_STATS_RX_SINGLE_REC = NSS_STATS_NODE_MAX,
+						/**< Received single DTLS record datagrams. */
+	NSS_DTLS_CMN_STATS_RX_MULTI_REC,	/**< Received multiple DTLS record datagrams. */
+	NSS_DTLS_CMN_STATS_FAIL_CRYPTO_RESOURCE,/**< Failure in crypto resource allocation. */
+	NSS_DTLS_CMN_STATS_FAIL_CRYPTO_ENQUEUE,	/**< Failure due to full queue in crypto or hardware. */
+	NSS_DTLS_CMN_STATS_FAIL_HEADROOM,	/**< Failure in headroom check. */
+	NSS_DTLS_CMN_STATS_FAIL_TAILROOM,	/**< Failure in tailroom check. */
+	NSS_DTLS_CMN_STATS_FAIL_VER,		/**< Failure in DTLS version check. */
+	NSS_DTLS_CMN_STATS_FAIL_EPOCH,		/**< Failure in DTLS epoch check. */
+	NSS_DTLS_CMN_STATS_FAIL_DTLS_RECORD,	/**< Failure in reading DTLS record. */
+	NSS_DTLS_CMN_STATS_FAIL_CAPWAP,		/**< Failure in CAPWAP classification. */
+	NSS_DTLS_CMN_STATS_FAIL_REPLAY,		/**< Failure in anti-replay check. */
+	NSS_DTLS_CMN_STATS_FAIL_REPLAY_DUP,	/**< Failure in anti-replay; duplicate records. */
+	NSS_DTLS_CMN_STATS_FAIL_REPLAY_WIN,	/**< Failure in anti-replay; packet outside the window. */
+	NSS_DTLS_CMN_STATS_FAIL_QUEUE,		/**< Failure due to full queue in DTLS. */
+	NSS_DTLS_CMN_STATS_FAIL_QUEUE_NEXTHOP,	/**< Failure due to full queue in next hop. */
+	NSS_DTLS_CMN_STATS_FAIL_PBUF_ALLOC,	/**< Failure in pbuf allocation. */
+	NSS_DTLS_CMN_STATS_FAIL_PBUF_LINEAR,	/**< Failure in pbuf linearization. */
+	NSS_DTLS_CMN_STATS_FAIL_PBUF_STATS,	/**< Failure in pbuf allocation for statistics. */
+	NSS_DTLS_CMN_STATS_FAIL_PBUF_ALIGN,	/**< Failure in pbuf alignment. */
+	NSS_DTLS_CMN_STATS_FAIL_CTX_ACTIVE,	/**< Failure in enqueue due to inactive context. */
+	NSS_DTLS_CMN_STATS_FAIL_HWCTX_ACTIVE,	/**< Failure in enqueue due to inactive hardware context. */
+	NSS_DTLS_CMN_STATS_FAIL_CIPHER,		/**< Failure in decrypting the data. */
+	NSS_DTLS_CMN_STATS_FAIL_AUTH,		/**< Failure in authenticating the data. */
+	NSS_DTLS_CMN_STATS_FAIL_SEQ_OVF,	/**< Failure due to sequence number overflow. */
+	NSS_DTLS_CMN_STATS_FAIL_BLK_LEN,	/**< Failure in decapsulation due to bad cipher length. */
+	NSS_DTLS_CMN_STATS_FAIL_HASH_LEN,	/**< Failure in decapsulation due to bad hash length. */
+	NSS_DTLS_CMN_STATS_LEN_ERROR,		/**< Length error. */
+	NSS_DTLS_CMN_STATS_TOKEN_ERROR,		/**< Token error, unknown token command or instruction. */
+	NSS_DTLS_CMN_STATS_BYPASS_ERROR,	/**< Token contains too much bypass data. */
+	NSS_DTLS_CMN_STATS_CONFIG_ERROR,	/**< Invalid command, algorithm, or mode combination. */
+	NSS_DTLS_CMN_STATS_ALGO_ERROR,		/**< Unsupported algorithm. */
+	NSS_DTLS_CMN_STATS_HASH_OVF_ERROR,	/**< Hash input overflow. */
+	NSS_DTLS_CMN_STATS_TTL_ERROR,		/**< TTL or HOP-Limit underflow. */
+	NSS_DTLS_CMN_STATS_CSUM_ERROR,		/**< Checksum error. */
+	NSS_DTLS_CMN_STATS_TIMEOUT_ERROR,	/**< Data timed out. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_0,		/**< Classification failure 0. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_1,		/**< Classification failure 1. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_2,		/**< Classification failure 2. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_3,		/**< Classification failure 3. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_4,		/**< Classification failure 4. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_5,		/**< Classification failure 5. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_6,		/**< Classification failure 6. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_7,		/**< Classification failure 7. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_8,		/**< Classification failure 8. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_9,		/**< Classification failure 9. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_10,	/**< Classification failure 10. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_11,	/**< Classification failure 11. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_12,	/**< Classification failure 12. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_13,	/**< Classification failure 13. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_14,	/**< Classification failure 14. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_15,	/**< Classification failure 15. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_16,	/**< Classification failure 16. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_17,	/**< Classification failure 17. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_18,	/**< Classification failure 18. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_19,	/**< Classification failure 19. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_20,	/**< Classification failure 20. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_21,	/**< Classification failure 21. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_22,	/**< Classification failure 22. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_23,	/**< Classification failure 23. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_24,	/**< Classification failure 24. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_25,	/**< Classification failure 25. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_26,	/**< Classification failure 26. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_27,	/**< Classification failure 27. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_28,	/**< Classification failure 28. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_29,	/**< Classification failure 29. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_30,	/**< Classification failure 30. */
+	NSS_DTLS_CMN_STATS_CLE_ERROR_31,	/**< Classification failure 31. */
+	NSS_DTLS_CMN_STATS_SEQ_LOW,		/**< Lower 32 bits of current transmit sequence number. */
+	NSS_DTLS_CMN_STATS_SEQ_HIGH,		/**< Upper 16 bits of current transmit sequence number. */
+	NSS_DTLS_CMN_STATS_EPOCH,		/**< Current epoch value. */
+	NSS_DTLS_CMN_CTX_STATS_MAX,		/**< Maximum message type. */
+};
+
+/**
+ * nss_dtls_cmn_node_stats
+ * 	DTLS node statistics.
+ */
+struct nss_dtls_cmn_node_stats {
+	uint32_t fail_ctx_alloc;	/**< Failure in allocating a context. */
+	uint32_t fail_ctx_free;		/**< Failure in freeing up the context. */
+	uint32_t fail_pbuf_stats;	/**< Failure in pbuf allocation for statistics. */
+};
+
+/**
+ * nss_dtls_cmn_hw_stats
+ * 	DTLS hardware statistics.
+ */
+struct nss_dtls_cmn_hw_stats {
+	uint32_t len_error;             /**< Length error. */
+	uint32_t token_error;           /**< Token error, unknown token command/instruction. */
+	uint32_t bypass_error;          /**< Token contains too much bypass data. */
+	uint32_t config_error;          /**< Invalid command/algorithm/mode/combination. */
+	uint32_t algo_error;            /**< Unsupported algorithm. */
+	uint32_t hash_ovf_error;        /**< Hash input overflow. */
+	uint32_t ttl_error;             /**< TTL or HOP-Limit underflow. */
+	uint32_t csum_error;            /**< Checksum error. */
+	uint32_t timeout_error;         /**< Data timed-out. */
+};
+
+/**
+ * nss_dtls_cmn_ctx_stats
+ *	DTLS session statistics.
+ */
+struct nss_dtls_cmn_ctx_stats {
+	struct nss_cmn_node_stats pkt;		/**< Common node statistics. */
+	uint32_t rx_single_rec;			/**< Received single DTLS record datagrams. */
+	uint32_t rx_multi_rec;			/**< Received multiple DTLS record datagrams. */
+	uint32_t fail_crypto_resource;		/**< Failure in allocation of crypto resource. */
+	uint32_t fail_crypto_enqueue;		/**< Failure due to queue full in crypto or hardware. */
+	uint32_t fail_headroom;			/**< Failure in headroom check. */
+	uint32_t fail_tailroom;			/**< Failure in tailroom check. */
+	uint32_t fail_ver;			/**< Failure in DTLS version check. */
+	uint32_t fail_epoch;			/**< Failure in DTLS epoch check. */
+	uint32_t fail_dtls_record;		/**< Failure in reading DTLS record. */
+	uint32_t fail_capwap;			/**< Failure in CAPWAP classification. */
+	uint32_t fail_replay;			/**< Failure in anti-replay check. */
+	uint32_t fail_replay_dup;		/**< Failure in anti-replay; duplicate records. */
+	uint32_t fail_replay_win;		/**< Failure in anti-replay; packet outside the window. */
+	uint32_t fail_queue;			/**< Failure due to queue full in DTLS. */
+	uint32_t fail_queue_nexthop;		/**< Failure due to queue full in next_hop. */
+	uint32_t fail_pbuf_alloc;		/**< Failure in pbuf allocation. */
+	uint32_t fail_pbuf_linear;		/**< Failure in pbuf linearization. */
+	uint32_t fail_pbuf_stats;		/**< Failure in pbuf allocation for statistics. */
+	uint32_t fail_pbuf_align;		/**< Failure in pbuf alignment. */
+	uint32_t fail_ctx_active;		/**< Failure in enqueue due to inactive context. */
+	uint32_t fail_hwctx_active;		/**< Failure in enqueue due to inactive hardware context. */
+	uint32_t fail_cipher;			/**< Failure in decrypting the data. */
+	uint32_t fail_auth;			/**< Failure in authenticating the data. */
+	uint32_t fail_seq_ovf;			/**< Failure due to sequence number overflow. */
+	uint32_t fail_blk_len;			/**< Failure in decapsulation due to bad cipher block length. */
+	uint32_t fail_hash_len;			/**< Failure in decapsulation due to bad hash block length. */
+
+	struct nss_dtls_cmn_hw_stats fail_hw;	/**< Hardware failure statistics. */
+
+	uint32_t fail_cle[NSS_DTLS_CMN_CLE_MAX];/**< Classification errors. */
+
+	uint32_t seq_low;			/**< Lower 32 bits of current Tx sequence number. */
+	uint32_t seq_high;			/**< Upper 16 bits of current Tx sequence number. */
+
+	uint16_t epoch;				/**< Current epoch value. */
+	uint8_t res1[2];			/**< Reserved for future use. */
+
+	uint8_t res2[16];			/**< Reserved for future use. */
+};
+
+/**
+ * nss_dtls_cmn_ctx_config_hdr
+ *	Parameters for outer header transform.
+ */
+struct nss_dtls_cmn_ctx_config_hdr {
+	uint32_t flags;		/**< Context flags. */
+	uint32_t dest_ifnum;	/**< Destination interface for packets. */
+	uint32_t src_ifnum;	/**< Source interface of packets. */
+	uint32_t sip[4];	/**< Source IPv4/v6 address. */
+	uint32_t dip[4];	/**< Destination IPv4/v6 address. */
+
+	uint16_t sport;		/**< Source UDP/UDPLite port. */
+	uint16_t dport;		/**< Destination UDP/UDPLite port. */
+
+	uint8_t hop_limit_ttl;	/**< IP header TTL field. */
+	uint8_t dscp;		/**< DSCP value. */
+	uint8_t dscp_copy; 	/**< Copy DSCP value. */
+	uint8_t df;		/**< Do not fragment DTLS over IPv4. */
+};
+
+/**
+ * nss_dtls_cmn_ctx_config_dtls
+ *	Parameters for DTLS transform.
+ */
+struct nss_dtls_cmn_ctx_config_dtls {
+	uint32_t ver;		/**< Version (enum dtls_cmn_ver). */
+	uint32_t crypto_idx;	/**< Crypto index for cipher context. */
+
+	uint16_t window_size;	/**< Anti-replay window size. */
+	uint16_t epoch;		/**< Initial epoch value. */
+
+	uint8_t iv_len;		/**< Crypto IV length for encapsulation. */
+	uint8_t hash_len;	/**< Auth hash length for encapsulation. */
+	uint8_t blk_len;	/**< Cipher block length. */
+	uint8_t res1;		/**< Reserved for alignment. */
+};
+
+/**
+ * nss_dtls_cmn_stats_notification
+ *	DTLS common transmission statistics structure.
+ */
+struct nss_dtls_cmn_stats_notification {
+	uint64_t stats_ctx[NSS_DTLS_CMN_CTX_STATS_MAX];		/**< Context transmission statistics. */
+	uint32_t core_id;					/**< Core ID. */
+	uint32_t if_num;					/**< Interface number. */
+};
+
+/**
+ * nss_dtls_cmn_msg
+ *	Data for sending and receiving DTLS messages.
+ */
+struct nss_dtls_cmn_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a DTLS message.
+	 */
+	union {
+		struct nss_dtls_cmn_ctx_config_hdr hdr_cfg;	/**< Session configuration. */
+		struct nss_dtls_cmn_ctx_config_dtls dtls_cfg;	/**< Cipher update information. */
+		struct nss_dtls_cmn_ctx_stats stats;		/**< Session statistics. */
+		struct nss_dtls_cmn_node_stats node_stats;	/**< Node statistics. */
+	} msg;			/**< Message payload for DTLS session messages exchanged with NSS core. */
+};
+
+#ifdef __KERNEL__ /* only for kernel use. */
+/**
+ * Callback function for receiving DTLS messages.
+ *
+ * @datatypes
+ * nss_dtls_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_dtls_cmn_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * Callback function for receiving DTLS session data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_dtls_cmn_data_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_dtls_cmn_tx_buf
+ *	Sends a DTLS data packet to the NSS.
+ *
+ * @datatypes
+ * sk_buff \n
+ * nss_ctx_instance
+ *
+ * @param[in]     os_buf   Pointer to the OS data buffer.
+ * @param[in]     if_num   NSS interface number.
+ * @param[in]     nss_ctx  Pointer to the NSS core context.
+ *
+ * @return
+ * Status of Tx buffer forwarded to NSS for DTLS operation.
+ */
+nss_tx_status_t nss_dtls_cmn_tx_buf(struct sk_buff *os_buf, uint32_t if_num, struct nss_ctx_instance *nss_ctx);
+
+/**
+ * nss_dtls_cmn_tx_msg
+ *	Sends DTLS messages.
+ *
+ * @param[in]     nss_ctx  Pointer to the NSS core context.
+ * @param[in,out] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_dtls_cmn_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_dtls_cmn_msg *msg);
+
+/**
+ * nss_dtls_cmn_tx_msg_sync
+ *	Sends DTLS messages synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_dtls_cmn_msg_type \n
+ * nss_dtls_cmn_msg \n
+ * nss_dtls_cmn_error
+ *
+ * @param[in]     nss_ctx  Pointer to the NSS context.
+ * @param[in]     if_num   NSS interface number.
+ * @param[in]     type     Type of message.
+ * @param[in]     len      Size of the payload.
+ * @param[in]     ndcm     Pointer to the message data.
+ * @param[in,out] resp     Response for the configuration.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_dtls_cmn_tx_msg_sync(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+						enum nss_dtls_cmn_msg_type type, uint16_t len,
+						struct nss_dtls_cmn_msg *ndcm, enum nss_dtls_cmn_error *resp);
+
+/**
+ * nss_dtls_cmn_unregister_if
+ *	Deregisters a DTLS session interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The DTLS session interface must have been previously registered.
+ */
+extern void nss_dtls_cmn_unregister_if(uint32_t if_num);
+
+/**
+ * nss_dtls_cmn_register_if
+ *	Registers a DTLS session interface with the NSS for sending and receiving
+ *	messages.
+ *
+ * @datatypes
+ * nss_dtls_cmn_data_callback_t \n
+ * nss_dtls_cmn_msg_callback_t
+ *
+ * @param[in] if_num    NSS interface number.
+ * @param[in] data_cb   Callback function for the message.
+ * @param[in] msg_cb    Callback for DTLS tunnel message.
+ * @param[in] netdev    Pointer to the associated network device.
+ * @param[in] features  Data socket buffer types supported by this interface.
+ * @param[in] type      Type of message.
+ * @param[in] app_ctx   Pointer to the application context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_dtls_cmn_register_if(uint32_t if_num,
+							 nss_dtls_cmn_data_callback_t data_cb,
+							 nss_dtls_cmn_msg_callback_t msg_cb,
+							 struct net_device *netdev,
+							 uint32_t features,
+							 uint32_t type,
+							 void *app_ctx);
+
+/**
+ * nss_dtls_cmn_notify_unregister
+ *	Deregisters an event callback.
+ *
+ * @param[in] ifnum  NSS interface number.
+ *
+ * @return
+ * None.
+ */
+extern void nss_dtls_cmn_notify_unregister(uint32_t ifnum);
+
+/**
+ * nss_dtls_cmn_notify_register
+ *	Registers an event callback to handle notification from DTLS firmware package.
+ *
+ * @param[in] ifnum     NSS interface number.
+ * @param[in] ev_cb     Callback for DTLS tunnel message.
+ * @param[in] app_data  Pointer to the application context.
+ *
+ * @return
+ * Pointer to NSS core context.
+ */
+extern struct nss_ctx_instance *nss_dtls_cmn_notify_register(uint32_t ifnum, nss_dtls_cmn_msg_callback_t ev_cb,
+							     void *app_data);
+
+/**
+ * nss_dtls_cmn_msg_init
+ *	Initializes a DTLS message.
+ *
+ * @datatypes
+ * nss_dtls_cmn_msg
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Pointer to the message callback.
+ * @param[in]     app_data  Pointer to the application context.
+ *
+ * @return
+ * None.
+ */
+extern void nss_dtls_cmn_msg_init(struct nss_dtls_cmn_msg *ncm, uint32_t if_num, uint32_t type, uint32_t len, void *cb,
+				void *app_data);
+
+/**
+ * nss_dtls_cmn_get_context
+ *	Gets the NSS core context for the DTLS session.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_dtls_cmn_get_context(void);
+
+/**
+ * nss_dtls_cmn_get_ifnum
+ *	Gets the DTLS interface number with a core ID.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * Interface number with the core ID.
+ */
+extern int32_t nss_dtls_cmn_get_ifnum(int32_t if_num);
+
+/**
+ * nss_dtls_cmn_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_dtls_cmn_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * nss_dtls_cmn_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_dtls_cmn_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * @}
+ */
+
+#endif /* __KERNEL__ */
+#endif /* _NSS_DTLS_CMN_H_. */
diff --git a/qca-nss-drv/exports/nss_dynamic_interface.h b/qca-nss-drv/exports/nss_dynamic_interface.h
new file mode 100644
index 0000000..7595af1
--- /dev/null
+++ b/qca-nss-drv/exports/nss_dynamic_interface.h
@@ -0,0 +1,343 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_dynamic_interface.h
+ *	NSS Dynamic interface definitions.
+ */
+
+#ifndef __NSS_DYNAMIC_INTERFACE_H
+#define __NSS_DYNAMIC_INTERFACE_H
+
+/**
+ * @addtogroup nss_dynamic_interface_subsystem
+ * @{
+ */
+
+#define NSS_MAX_DYNAMIC_INTERFACES 128	/**< Maximum number of dynamic interfaces. */
+
+/**
+ * nss_dynamic_interface_type
+ *	Dynamic interface types.
+ *
+ * @note
+ * Every time a new dynamic interface type is added to an enumeration in the following list,
+ * a corresponding type name string should be added in the dynamic interface type string array.
+ */
+enum nss_dynamic_interface_type {
+	NSS_DYNAMIC_INTERFACE_TYPE_NONE,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR,
+	NSS_DYNAMIC_INTERFACE_TYPE_RESERVED_5,
+	NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_RESERVED,
+	NSS_DYNAMIC_INTERFACE_TYPE_VAP,
+	NSS_DYNAMIC_INTERFACE_TYPE_RESERVED_0,
+	NSS_DYNAMIC_INTERFACE_TYPE_PPPOE,
+	NSS_DYNAMIC_INTERFACE_TYPE_VIRTIF_DEPRECATED,
+	NSS_DYNAMIC_INTERFACE_TYPE_L2TPV2,
+	NSS_DYNAMIC_INTERFACE_TYPE_RESERVED_4,
+	NSS_DYNAMIC_INTERFACE_TYPE_PORTID,
+	NSS_DYNAMIC_INTERFACE_TYPE_DTLS,
+	NSS_DYNAMIC_INTERFACE_TYPE_QVPN_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_QVPN_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_BRIDGE,
+	NSS_DYNAMIC_INTERFACE_TYPE_VLAN,
+	NSS_DYNAMIC_INTERFACE_TYPE_RESERVED_3,
+	NSS_DYNAMIC_INTERFACE_TYPE_WIFILI_INTERNAL,
+	NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_HOST_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_OFFL_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_SJACK_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INLINE_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INLINE_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_N2H,
+	NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_H2N,
+	NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_US,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_DS,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INNER_EXCEPTION,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_EXCEPTION_US,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_EXCEPTION_DS,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_PPTP_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_PPTP_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_PPTP_HOST_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_MDATA_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_MDATA_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_REDIRECT,
+	NSS_DYNAMIC_INTERFACE_TYPE_PVXLAN_HOST_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_PVXLAN_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_IGS,
+	NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US,
+	NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_DS,
+	NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_MATCH,
+	NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_N2H,
+	NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_H2N,
+	NSS_DYNAMIC_INTERFACE_TYPE_WIFILI_EXTERNAL0,
+	NSS_DYNAMIC_INTERFACE_TYPE_WIFILI_EXTERNAL1,
+	NSS_DYNAMIC_INTERFACE_TYPE_TLS_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_TLS_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_MIRROR,
+	NSS_DYNAMIC_INTERFACE_TYPE_WIFI_EXT_VDEV_WDS,
+	NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_HOST_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_WIFI_EXT_VDEV_VLAN,
+	NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER,
+	NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER,
+	NSS_DYNAMIC_INTERFACE_TYPE_MAX
+};
+
+typedef enum nss_dynamic_interface_type nss_dynamic_interface_assigned;
+
+/**
+ * nss_dynamic_interface_message_types
+ *	Message types for dynamic interface requests.
+ */
+enum nss_dynamic_interface_message_types {
+	NSS_DYNAMIC_INTERFACE_ALLOC_NODE,
+	NSS_DYNAMIC_INTERFACE_DEALLOC_NODE,
+	NSS_DYNAMIC_INTERFACE_MAX,
+};
+
+/**
+ * nss_dynamic_interface_error_types
+ *	Error types for dynamic interface requests.
+ */
+enum nss_dynamic_interface_error_types {
+	NSS_DYNAMIC_INTERFACE_ERR_EUNKNOWN = 1,
+	NSS_DYNAMIC_INTERFACE_ERR_EUNAVAIL,
+	NSS_DYNAMIC_INTERFACE_ERR_INVALID_TYPE,
+	NSS_DYNAMIC_INTERFACE_ERR_INVALID_INTERFACE_NUM,
+	NSS_DYNAMIC_INTERFACE_ERR_ALLOC_FUNC_UNAVAILABLE,
+	NSS_DYNAMIC_INTERFACE_ERR_DEALLOC_FUNC_UNAVAILABLE,
+	NSS_DYNAMIC_INTERFACE_ERR_EALLOC,
+	NSS_DYNAMIC_INTERFACE_ERR_IFNUM_TYPE_MISMATCH,
+	NSS_DYNAMIC_INTERFACE_ERR_MAX,
+};
+
+/**
+ * nss_dynamic_interface_stats_notification
+ *	Dynamic interface statistics structure.
+ */
+struct nss_dynamic_interface_notification {
+	uint32_t core_id;	/**< Core ID. */
+	uint32_t if_num;	/**< Dynamic interface number. */
+};
+
+#ifdef __KERNEL__ /* only kernel will use. */
+/**
+ * nss_dynamic_interface_alloc_node_msg
+ *	Message information for a dynamic interface allocation node.
+ */
+struct nss_dynamic_interface_alloc_node_msg {
+	enum nss_dynamic_interface_type type;	/**< Type of dynamic interface. */
+
+	/*
+	 * Response.
+	 */
+	int if_num;				/**< Dynamic interface number. */
+};
+
+/**
+ * nss_dynamic_interface_dealloc_node_msg
+ *	Message information for dynamic interface deallocation node.
+ */
+struct nss_dynamic_interface_dealloc_node_msg {
+	enum nss_dynamic_interface_type type;
+			/**< Type of dynamic interface. */
+	int if_num;	/**< Dynamic interface number. */
+};
+
+/**
+ * nss_dynamic_interface_msg
+ *	Data for sending and receiving dynamic interface messages.
+ */
+struct nss_dynamic_interface_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a dynamic interface message.
+	 */
+	union {
+		struct nss_dynamic_interface_alloc_node_msg alloc_node;
+				/**< Allocates a dynamic node. */
+		struct nss_dynamic_interface_dealloc_node_msg dealloc_node;
+				/**< Deallocates a dynamic node. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * nss_dynamic_interface_alloc_node
+ *	Allocates a node for a dynamic interface.
+ *
+ * @datatypes
+ * nss_dynamic_interface_type
+ *
+ * @param[in] type  Type of dynamic interface.
+ *
+ * @return
+ * Number for the dynamic interface created.
+ * @par
+ * Otherwise, -1 for a failure.
+ */
+extern int nss_dynamic_interface_alloc_node(enum nss_dynamic_interface_type type);
+
+/**
+ * nss_dynamic_interface_dealloc_node
+ *	Deallocates a node created for a dynamic interface on the NSS.
+ *
+ * @datatypes
+ * nss_dynamic_interface_type
+ *
+ * @param[in] if_num  Dynamic interface number.
+ * @param[in] type    Type of dynamic interface.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_dynamic_interface_dealloc_node(int if_num, enum nss_dynamic_interface_type type);
+
+/**
+ * nss_is_dynamic_interface
+ *	Specifies whether the interface number belongs to the dynamic interface.
+ *
+ * @param[in] if_num  Dynamic interface number.
+ *
+ * @return
+ * TRUE or FALSE
+ */
+extern bool nss_is_dynamic_interface(int if_num);
+
+/**
+ * nss_dynamic_interface_get_nss_ctx_by_type
+ *	Returns NSS context corresponding to the dynamic interface type.
+ *
+ * @datatypes
+ * nss_dynamic_interface_type
+ *
+ * @param[in] type  Type of dynamic interface.
+ *
+ * @return
+ * Pointer to the NSS context.
+ */
+extern struct nss_ctx_instance *nss_dynamic_interface_get_nss_ctx_by_type(enum nss_dynamic_interface_type type);
+
+/**
+ * nss_dynamic_interface_get_type
+ *	Returns the type of dynamic interface.
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] if_num   Interface number of dynamic interface.
+ *
+ * @return
+ * Type of dynamic interface per the dynamic interface number.
+ */
+extern enum nss_dynamic_interface_type nss_dynamic_interface_get_type(struct nss_ctx_instance *nss_ctx, int if_num);
+
+/**
+ * nss_dynamic_interface_tx
+ *	Transmits an asynchronous message to the firmware.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_dynamic_interface_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+extern nss_tx_status_t nss_dynamic_interface_tx(struct nss_ctx_instance *nss_ctx, struct nss_dynamic_interface_msg *msg);
+
+/**
+ * Callback function for dynamic interface messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_dynamic_interface_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * nss_dynamic_interface_msg_init
+ *	Initializes a dynamic interface message.
+ *
+ * @datatypes
+ * nss_dynamic_interface_msg
+ *
+ * @param[in] ndm       Pointer to the dynamic interface message.
+ * @param[in] if_num    Dynamic interface number.
+ * @param[in] type      Type of message.
+ * @param[in] len       Size of the payload.
+ * @param[in] cb        Pointer to the message callback.
+ * @param[in] app_data  Pointer to the application context that is passed to the callback function.
+ *
+ * @return
+ * None.
+ */
+void nss_dynamic_interface_msg_init(struct nss_dynamic_interface_msg *ndm, uint16_t if_num, uint32_t type, uint32_t len,
+						void *cb, void *app_data);
+
+/**
+ * nss_dynamic_interface_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_dynamic_interface_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_dynamic_interface_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_dynamic_interface_stats_unregister_notifier(struct notifier_block *nb);
+#endif /*__KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_DYNAMIC_INTERFACE_H*/
diff --git a/qca-nss-drv/exports/nss_edma.h b/qca-nss-drv/exports/nss_edma.h
new file mode 100644
index 0000000..c2c81c8
--- /dev/null
+++ b/qca-nss-drv/exports/nss_edma.h
@@ -0,0 +1,375 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_edma.h
+ *	NSS EDMA interface definitions.
+ */
+
+#ifndef __NSS_EDMA_H
+#define __NSS_EDMA_H
+
+/**
+ * @addtogroup nss_edma_subsystem
+ * @{
+ */
+
+/*
+ * NSS EDMA port and ring defines
+ */
+#define NSS_EDMA_NUM_PORTS_MAX		256
+		/**< Maximum number of EDMA ports. */
+#define NSS_EDMA_NUM_RX_RING_MAX	16
+		/**< Maximum number of physical EDMA Rx rings. */
+#define NSS_EDMA_NUM_RXFILL_RING_MAX	8
+		/**< Maximum number of physical EDMA Rx fill rings. */
+#define NSS_EDMA_NUM_TX_RING_MAX	24
+		/**< Maximum number of physical EDMA Tx rings. */
+#define NSS_EDMA_NUM_TXCMPL_RING_MAX	8
+		/**< Maximum number of physical EDMA Tx complete rings. */
+#define NSS_EDMA_STATS_MSG_MAX_PORTS	16
+		/**< Maximum ports processed per statistics message. */
+
+/**
+ * nss_edma_metadata_types
+ *	Message types for EDMA requests and responses.
+ */
+enum nss_edma_metadata_types {
+	NSS_METADATA_TYPE_EDMA_PORT_STATS_SYNC,
+	NSS_METADATA_TYPE_EDMA_RING_STATS_SYNC,
+	NSS_METADATA_TYPE_EDMA_ERR_STATS_SYNC,
+	NSS_METADATA_TYPE_EDMA_MAX
+};
+
+/**
+ * nss_edma_port_t
+ *	EDMA port types.
+ */
+enum nss_edma_port_t {
+	NSS_EDMA_PORT_PHYSICAL,
+	NSS_EDMA_PORT_VIRTUAL,
+	NSS_EDMA_PORT_TYPE_MAX
+};
+
+/**
+ * nss_edma_stats_tx_t
+ *	Types of EDMA Tx ring statistics.
+ */
+enum nss_edma_stats_tx_t {
+	NSS_EDMA_STATS_TX_ERR,
+	NSS_EDMA_STATS_TX_DROPPED,
+	NSS_EDMA_STATS_TX_DESC,
+	NSS_EDMA_STATS_TX_MAX
+};
+
+/**
+ * nss_edma_stats_rx_t
+ *	Types of EDMA Rx ring statistics.
+ */
+enum nss_edma_stats_rx_t {
+	NSS_EDMA_STATS_RX_CSUM_ERR,
+	NSS_EDMA_STATS_RX_DESC,
+	NSS_EDMA_STATS_RX_QOS_ERR,
+	NSS_EDMA_STATS_RX_SRC_PORT_INVALID,
+	NSS_EDMA_STATS_RX_SRC_IF_INVALID,
+	NSS_EDMA_STATS_RX_MAX
+};
+
+/**
+ * nss_edma_stats_txcmpl_t
+ *	Types of EDMA Tx complete statistics.
+ */
+enum nss_edma_stats_txcmpl_t {
+	NSS_EDMA_STATS_TXCMPL_DESC,
+	NSS_EDMA_STATS_TXCMPL_MAX
+};
+
+/**
+ * nss_edma_stats_rxfill_t
+ *	Types of EDMA Rx fill statistics.
+ */
+enum nss_edma_stats_rxfill_t {
+	NSS_EDMA_STATS_RXFILL_DESC,
+	NSS_EDMA_STATS_RXFILL_MAX
+};
+
+/**
+ * nss_edma_port_ring_map_t
+ *	Port to EDMA ring map.
+ */
+enum nss_edma_port_ring_map_t {
+	NSS_EDMA_PORT_RX_RING,
+	NSS_EDMA_PORT_TX_RING,
+	NSS_EDMA_PORT_RING_MAP_MAX
+};
+
+/**
+ * nss_edma_err_t
+ *	Types of EDMA error statistics.
+ */
+enum nss_edma_err_t {
+	NSS_EDMA_AXI_RD_ERR,
+	NSS_EDMA_AXI_WR_ERR,
+	NSS_EDMA_RX_DESC_FIFO_FULL_ERR,
+	NSS_EDMA_RX_BUF_SIZE_ERR,
+	NSS_EDMA_TX_SRAM_FULL_ERR,
+	NSS_EDMA_TX_CMPL_BUF_FULL_ERR,
+	NSS_EDMA_PKT_LEN_LA64K_ERR,
+	NSS_EDMA_PKT_LEN_LE33_ERR,
+	NSS_EDMA_DATA_LEN_ERR,
+	NSS_EDMA_ALLOC_FAIL_CNT,
+	NSS_EDMA_QOS_INVAL_DST_DROPS,
+	NSS_EDMA_ERR_STATS_MAX
+};
+
+/**
+ * nss_edma_rx_ring_stats
+ *	EDMA Rx ring statistics.
+ */
+struct nss_edma_rx_ring_stats {
+	uint32_t rx_csum_err;		/**< Number of Rx checksum errors. */
+	uint32_t desc_cnt;		/**< Number of descriptors processed. */
+	uint32_t qos_err;		/**< Number of QoS errors. */
+	uint32_t rx_src_port_invalid;	/**< Number of source port invalid errors. */
+	uint32_t rx_src_if_invalid;	/**< Number of source interface invalid errors. */
+};
+
+/**
+ * nss_edma_tx_ring_stats
+ *	EDMA Tx ring statistics.
+ */
+struct nss_edma_tx_ring_stats {
+	uint32_t tx_err;		/**< Number of Tx errors. */
+	uint32_t tx_dropped;		/**< Number of Tx dropped packets. */
+	uint32_t desc_cnt;		/**< Number of descriptors processed. */
+};
+
+/**
+ * nss_edma_rxfill_ring_stats
+ *	EDMA Rx fill ring statistics.
+ */
+struct nss_edma_rxfill_ring_stats {
+	uint32_t desc_cnt;		/**< Number of descriptors processed. */
+};
+
+/**
+ * nss_edma_txcmpl_ring_stats
+ *	EDMA Tx complete ring statistics.
+ */
+struct nss_edma_txcmpl_ring_stats {
+	uint32_t desc_cnt;		/**< Number of descriptors processed. */
+};
+
+/**
+ * nss_edma_port_stats
+ *	Statistics for each EDMA port.
+ */
+struct nss_edma_port_stats {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics. */
+	enum nss_edma_port_t port_type;		/**< Type of port. */
+	uint16_t edma_rx_ring;			/**< Rx ring statistics. */
+	uint16_t edma_tx_ring;			/**< Tx ring statistics. */
+};
+
+/**
+ * nss_edma_port_stats_sync
+ *	Statistics for a group of EDMA ports.
+ */
+struct nss_edma_port_stats_sync {
+	uint16_t start_port;		/**< Starting index of the subset. */
+	uint16_t end_port;		/**< Ending index of the subset. */
+	struct nss_edma_port_stats port_stats[];
+					/**< Subset of EDMA port statistics. */
+};
+
+/**
+ * nss_edma_ring_stats_sync
+ *	EDMA ring statistics.
+ */
+struct nss_edma_ring_stats_sync {
+	struct nss_edma_tx_ring_stats tx_ring[NSS_EDMA_NUM_TX_RING_MAX];
+			/**< EDMA Tx ring statistics. */
+	struct nss_edma_rx_ring_stats rx_ring[NSS_EDMA_NUM_RX_RING_MAX];
+			/**< EDMA Rx ring statistics. */
+	struct nss_edma_txcmpl_ring_stats txcmpl_ring[NSS_EDMA_NUM_TXCMPL_RING_MAX];
+			/**< EDMA Tx complete ring statistics. */
+	struct nss_edma_rxfill_ring_stats rxfill_ring[NSS_EDMA_NUM_RXFILL_RING_MAX];
+			/**< EDMA Rx fill ring statistics. */
+};
+
+/**
+ * nss_edma_misc_err_stats
+ *	EDMA error statistics.
+ */
+struct nss_edma_misc_err_stats {
+	uint32_t axi_rd_err;            /**< EDMA AXI read error. */
+	uint32_t axi_wr_err;            /**< EDMA AXI write error. */
+	uint32_t rx_desc_fifo_full_err;	/**< EDMA receive descriptor FIFO full error. */
+	uint32_t rx_buf_size_err;       /**< EDMA receive buffer size error. */
+	uint32_t tx_sram_full_err;      /**< EDMA transmit SRAM full error. */
+	uint32_t tx_cmpl_buf_full_err;  /**< EDMA transmit completion buffer full error. */
+	uint32_t pkt_len_la64k_err;     /**< EDMA packet length greater than 64k error. */
+	uint32_t pkt_len_le33_err;      /**< EDMA packet length smaller than 33b error. */
+	uint32_t data_len_err;          /**< EDMA data length error. */
+	uint32_t alloc_fail_cnt;	/**< EDMA number of times the allocation of pbuf for statistics failed. */
+	uint32_t qos_inval_dst_drops;	/**< EDMA number of QoS packet dropped due to invalid destination. */
+};
+
+/**
+ * nss_edma_err_stats_sync
+ *	Message for error statistics.
+ */
+struct nss_edma_err_stats_sync {
+	struct nss_edma_misc_err_stats msg_err_stats;	/**< Message for error statistics. */
+};
+
+/**
+ * nss_edma_msg
+ *	Data for sending and receiving EDMA messages (to synchronize with
+ *	the firmware EDMA).
+ */
+struct nss_edma_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of an EDMA message.
+	 */
+	union {
+		struct nss_edma_port_stats_sync port_stats;
+				/**< EDMA port statistics message payload. */
+		struct nss_edma_ring_stats_sync ring_stats;
+				/**< EDMA ring statistics message payload. */
+		struct nss_edma_err_stats_sync err_stats;
+				/**< EDMA error statistics message payload. */
+	} msg;			/**< EDMA message payload. */
+};
+
+/**
+ * nss_edma_port_info
+ *	NSS EDMA port statistics.
+ */
+struct nss_edma_port_info {
+	uint64_t port_stats[NSS_STATS_NODE_MAX]; 		/**< EDMA port statistics. */
+	uint64_t port_type;					/**< EDMA port type. */
+	uint64_t port_ring_map[NSS_EDMA_PORT_RING_MAP_MAX];	/**< EDMA ring statistics. */
+};
+
+/**
+ * nss_edma_stats
+ *	NSS EDMA node statistics.
+ */
+struct nss_edma_stats {
+	struct nss_edma_port_info port[NSS_EDMA_NUM_PORTS_MAX];
+				/**< EDMA port statistics. */
+	uint64_t tx_stats[NSS_EDMA_NUM_TX_RING_MAX][NSS_EDMA_STATS_TX_MAX];
+				/**< Physical EDMA Tx ring statistics. */
+	uint64_t rx_stats[NSS_EDMA_NUM_RX_RING_MAX][NSS_EDMA_STATS_RX_MAX];
+				/**< Physical EDMA Rx ring statistics. */
+	uint64_t txcmpl_stats[NSS_EDMA_NUM_TXCMPL_RING_MAX][NSS_EDMA_STATS_TXCMPL_MAX];
+				/**< Physical EDMA Tx complete statistics. */
+	uint64_t rxfill_stats[NSS_EDMA_NUM_RXFILL_RING_MAX][NSS_EDMA_STATS_RXFILL_MAX];
+				/**< Physical EDMA Rx fill statistics. */
+	uint64_t misc_err[NSS_EDMA_ERR_STATS_MAX];
+				/**< EDMA error complete statistics. */
+};
+
+#ifdef __KERNEL__
+
+/**
+ * Callback function for receiving EDMA messages.
+ *
+ * @datatypes
+ * nss_edma_msg
+ *
+ * @param[in] app_data  Pointer to the application context for this message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_edma_msg_callback_t)(void *app_data, struct nss_edma_msg *msg);
+
+/**
+ * nss_edma_notify_register
+ *	Registers a callback notifier with the NSS for sending and receiving messages.
+ *
+ * @datatypes
+ * nss_edma_msg_callback_t
+ *
+ * @param[in] cb        Callback function for the message.
+ * @param[in] app_data  Pointer to the application context for this message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_edma_notify_register(nss_edma_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_edma_notify_unregister
+ *	Deregisters a callback notifier from the NSS.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The callback notifier must have been previously registered.
+ */
+extern void nss_edma_notify_unregister(void);
+
+/**
+ * nss_edma_get_stats
+ *	Sends EDMA statistics to NSS clients.
+ *
+ * @param[in] stats	EDMA statistics to be sent to netlink.
+ * @param[in] port_id	EDMA port ID.
+ *
+ * @return
+ * None.
+ */
+void nss_edma_get_stats(uint64_t  *stats, int port_id);
+
+/**
+ * nss_edma_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_edma_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_edma_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_edma_stats_unregister_notifier(struct notifier_block *nb);
+
+#endif /* __KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_EDMA_H */
diff --git a/qca-nss-drv/exports/nss_eth_rx.h b/qca-nss-drv/exports/nss_eth_rx.h
new file mode 100644
index 0000000..90f5a53
--- /dev/null
+++ b/qca-nss-drv/exports/nss_eth_rx.h
@@ -0,0 +1,100 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_eth_rx.h
+ *	NSS Ethernet interface definitions.
+ */
+
+#ifndef __NSS_ETH_RX_H
+#define __NSS_ETH_RX_H
+
+/**
+ * @addtogroup nss_eth_rx_subsystem
+ * @{
+ */
+
+/**
+ * nss_eth_rx_stats
+ *	Ethernet node statistics.
+ */
+enum nss_eth_rx_stats {
+	NSS_ETH_RX_STATS_TOTAL_TICKS,		/**< Total clock ticks spent inside the Ethernet package. */
+	NSS_ETH_RX_STATS_WORST_CASE_TICKS,	/**< Worst case iteration of the Ethernet in ticks. */
+	NSS_ETH_RX_STATS_ITERATIONS,		/**< Number of iterations around Ethernet. */
+	NSS_ETH_RX_STATS_MAX,			/**< Maximum message type. */
+};
+
+/**
+ * nss_eth_rx_exception_events
+ *	Exception events from bridge or route handler.
+ */
+enum nss_eth_rx_exception_events {
+	NSS_ETH_RX_EXCEPTION_EVENT_UNKNOWN_L3_PROTOCOL,
+	NSS_ETH_RX_EXCEPTION_EVENT_ETH_HDR_MISSING,
+	NSS_ETH_RX_EXCEPTION_EVENT_VLAN_MISSING,
+	NSS_ETH_RX_EXCEPTION_EVENT_TRUSTSEC_HDR_MISSING,
+	NSS_ETH_RX_EXCEPTION_EVENT_MAX,
+};
+
+/**
+ * nss_eth_rx_stats_notification
+ *	Data for sending Ethernet statistics.
+ */
+struct nss_eth_rx_stats_notification {
+	uint32_t core_id;						/**< Core ID. */
+	uint64_t cmn_node_stats[NSS_STATS_NODE_MAX];			/**< Node statistics. */
+	uint64_t special_stats[NSS_ETH_RX_STATS_MAX];			/**< Special statistics. */
+	uint64_t exception_stats[NSS_ETH_RX_EXCEPTION_EVENT_MAX];	/**< Exception statistics. */
+};
+
+#ifdef __KERNEL__ /* only kernel will use. */
+/**
+ * nss_eth_rx_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_eth_rx_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_eth_rx_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_eth_rx_stats_unregister_notifier(struct notifier_block *nb);
+#endif /*__KERNEL__ */
+
+/**
+ *@}
+ */
+
+#endif /* __NSS_ETH_RX_H */
diff --git a/qca-nss-drv/exports/nss_freq.h b/qca-nss-drv/exports/nss_freq.h
new file mode 100644
index 0000000..6ce11b1
--- /dev/null
+++ b/qca-nss-drv/exports/nss_freq.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * @file nss_freq.h
+ *	NSS frequency definitions.
+ */
+
+#ifndef __NSS_FREQ_H
+#define __NSS_FREQ_H
+
+/**
+ * @addtogroup nss_freq_subsystem
+ * @{
+ */
+
+/**
+ * nss_freq_change
+ *	Changes the frequency of the NSS cores.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx       Pointer to the NSS context.
+ * @param[in] eng           Frequency value in Hz.
+ * @param[in] stats_enable  Enable NSS to send scaling statistics.
+ * @param[in] start_or_end  Start or end of the frequency change.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_freq_change(struct nss_ctx_instance *nss_ctx, uint32_t eng, uint32_t stats_enable, uint32_t start_or_end);
+
+/**
+ * nss_freq_get_cpu_usage
+ *	Returns the CPU usage value in percentage at any instance for a required core. Range of usage is 0-100.
+ *
+ * @param[in] core_id       NSS Core ID.
+ *
+ * @return
+ * CPU usage value in percentage averaged over 1 second. -1 in case of error.
+ * @note
+ * This API does not support gathering CPU usage data for core 1.
+ */
+extern int8_t nss_freq_get_cpu_usage(uint32_t core_id);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_FREQ_H */
diff --git a/qca-nss-drv/exports/nss_gre.h b/qca-nss-drv/exports/nss_gre.h
new file mode 100644
index 0000000..7f3056e
--- /dev/null
+++ b/qca-nss-drv/exports/nss_gre.h
@@ -0,0 +1,494 @@
+/*
+ ****************************************************************************
+ * Copyright (c) 2017-2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ****************************************************************************
+ */
+
+/**
+ * @file nss_gre.h
+ *	NSS GRE interface definitions.
+ */
+#ifndef _NSS_GRE_H_
+#define _NSS_GRE_H_
+
+#include <net/ip_tunnels.h>
+#include <net/ip6_tunnel.h>
+
+/**
+ * @addtogroup nss_gre_subsystem
+ * @{
+ */
+
+/**
+ * Maximum number of session debug statistics
+ */
+#define NSS_GRE_MAX_DEBUG_SESSION_STATS 16
+
+/**
+ * GRE flags
+ */
+#define NSS_GRE_CONFIG_IKEY_VALID	0x00000001	/**< Incoming key of GRE header. */
+#define NSS_GRE_CONFIG_OKEY_VALID	0x00000002	/**< Key for outgoing GRE header. */
+#define NSS_GRE_CONFIG_ISEQ_VALID	0x00000004	/**< Enable sequence checking for incoming GRE traffic. */
+#define NSS_GRE_CONFIG_OSEQ_VALID	0x00000008	/**< Add sequence number for out going GRE packets. */
+#define NSS_GRE_CONFIG_ICSUM_VALID	0x00000010	/**< Validate incoming GRE header checksum. */
+#define NSS_GRE_CONFIG_OCSUM_VALID	0x00000020	/**< Add checksum header to GRE header. */
+#define NSS_GRE_CONFIG_TOS_INHERIT	0x00000040	/**< Inherit inner IP TOS to tunnel header, if not set configure provided TOS. */
+#define NSS_GRE_CONFIG_TTL_INHERIT	0x00000080	/**< Inherit inner IP TTL to tunnel header, if not set configure provided TTL. */
+#define NSS_GRE_CONFIG_SET_DF		0x00000100	/**< Enable DF bit on tunnel IP header. */
+#define NSS_GRE_CONFIG_SET_MAC		0x00000200	/**< Add MAC header to GRE+IP tunnel header. */
+#define NSS_GRE_CONFIG_SET_PADDING	0x00000400	/**< Add PADDING to align tunnel IP/GRE header. */
+#define NSS_GRE_CONFIG_NEXT_NODE_AVAILABLE  0x00000800	/**< Use provided next node instead of existing next node. */
+#define NSS_GRE_CONFIG_COPY_METADATA 	0x00001000	/**< Enable metadata copy in NSS during alignment. */
+#define NSS_GRE_CONFIG_USE_UNALIGNED 	0x00002000	/**< Use unaligned infrastructure in NSS. */
+#define NSS_GRE_CONFIG_DSCP_VALID	0x00004000	/**< Add DSCP per packet. */
+
+/**
+ * nss_gre_error_types.
+ *	Error types for GRE configuration messages.
+ */
+enum nss_gre_error_types {
+	NSS_GRE_ERR_UNKNOWN_MSG = 1,		/**< Unknown message. */
+	NSS_GRE_ERR_IF_INVALID = 2,		/**< Invalid interface. */
+	NSS_GRE_ERR_MODE_INVALID = 3,		/**< Invalid mode type. */
+	NSS_GRE_ERR_IP_INVALID = 4,		/**< Invalid IP type. */
+	NSS_GRE_ERR_GRE_SESSION_PARAMS_INVALID = 5,	/**< Invalid GRE session parameters provided. */
+	NSS_GRE_ERR_DSCP_CFG_INVALID = 6,	/**< Both TOS and DSCP flags are enabled. */
+	NSS_GRE_ERR_MAX,			/**< Maximum GRE error. */
+};
+
+/**
+ * nss_gre_info
+ *	GRE private information.
+ */
+struct nss_gre_info {
+	/**
+	 * Union of IPv4/IPv6 tunnel.
+	 */
+	union {
+		struct ip_tunnel t4;		/**< IPv4 tunnel. */
+		struct ip6_tnl t6;		/**< IPv6 tunnel. */
+	} t;		/**< IPv4 and IPv6 tunnel. */
+	int nss_if_number_inner;		/**< NSS interface number for GRE inner. */
+	struct net_device *next_dev_inner;	/**< Next network device for inner flow. */
+	struct net_device *next_dev_outer;	/**< Next network device for outer flow. */
+	uint8_t gre_hlen;			/**< GRE header length. */
+	uint8_t pad_len;			/**< Pad length. */
+};
+
+/**
+ * nss_gre_msg_types
+ *	Message types for GRE requests and responses.
+ */
+enum nss_gre_msg_types {
+	NSS_GRE_MSG_ENCAP_CONFIGURE = NSS_IF_MAX_MSG_TYPES + 1,
+	NSS_GRE_MSG_DECAP_CONFIGURE,
+	NSS_GRE_MSG_ENCAP_DECONFIGURE,
+	NSS_GRE_MSG_DECAP_DECONFIGURE,
+	NSS_GRE_MSG_SESSION_STATS,
+	NSS_GRE_MSG_BASE_STATS,
+	NSS_GRE_MSG_MAX
+};
+
+/**
+ * GRE mode types.
+ */
+enum nss_gre_mode {
+	NSS_GRE_MODE_TUN,	/**< GRE tunnel interface. */
+	NSS_GRE_MODE_TAP,	/**< GRE TAP interface. */
+	NSS_GRE_MODE_MAX	/**< Maxmum GRE mode. */
+};
+
+/**
+ * GRE IP types.
+ */
+enum nss_gre_ip_types {
+	NSS_GRE_IP_IPV4,	/**<  Outer Tunnel is IPV4. */
+	NSS_GRE_IP_IPV6,	/**<  Outer Tunnel is IPV6. */
+	NSS_GRE_IP_MAX,		/**<  Maximum IP Types. */
+};
+
+/**
+ * nss_gre_base_types
+ *	GRE base debug statistics.
+ */
+enum nss_gre_base_types {
+	NSS_GRE_BASE_RX_PACKETS,		/**< Receive packet count. */
+	NSS_GRE_BASE_RX_DROPPED,		/**< Number of packet dropped at receive. */
+	NSS_GRE_BASE_EXP_ETH_HDR_MISSING,	/**< Ethernet header missing. */
+	NSS_GRE_BASE_EXP_ETH_TYPE_NON_IP,	/**< Packet is not IPV4 or IPV6. */
+	NSS_GRE_BASE_EXP_IP_UNKNOWN_PROTOCOL,	/**< Packet protocol is unknown. */
+	NSS_GRE_BASE_EXP_IP_HEADER_INCOMPLETE,	/**< Bad IP header. */
+	NSS_GRE_BASE_EXP_IP_BAD_TOTAL_LENGTH,	/**< IP total length is invalid. */
+	NSS_GRE_BASE_EXP_IP_BAD_CHECKSUM,	/**< IP checksum is bad. */
+	NSS_GRE_BASE_EXP_IP_DATAGRAM_INCOMPLETE,/**< Bad packet. */
+	NSS_GRE_BASE_EXP_IP_FRAGMENT,		/**< IP packet is a fragment. */
+	NSS_GRE_BASE_EXP_IP_OPTIONS_INCOMPLETE,	/**< IP option is invalid. */
+	NSS_GRE_BASE_EXP_IP_WITH_OPTIONS,	/**< IP packet with options. */
+	NSS_GRE_BASE_EXP_IPV6_UNKNOWN_PROTOCOL,	/**< Protocol is unknown. */
+	NSS_GRE_BASE_EXP_IPV6_HEADER_INCOMPLETE,/**< Incomplete ipv6 header. */
+	NSS_GRE_BASE_EXP_GRE_UNKNOWN_SESSION,	/**< Unknown GRE session. */
+	NSS_GRE_BASE_EXP_GRE_NODE_INACTIVE,	/**< GRE node is inactive. */
+	NSS_GRE_BASE_DEBUG_MAX,			/**< GRE base debug maximum. */
+};
+
+/**
+ * nss_gre_session_types
+ *	GRE session packet drop and exception events.
+ */
+enum nss_gre_session_types {
+	NSS_GRE_SESSION_PBUF_ALLOC_FAIL,		/**< Pbuf allocation failure. */
+	NSS_GRE_SESSION_DECAP_FORWARD_ENQUEUE_FAIL,	/**< Receive forward enqueue failure. */
+	NSS_GRE_SESSION_ENCAP_FORWARD_ENQUEUE_FAIL,	/**< Transmit forward enqueue failure. */
+	NSS_GRE_SESSION_DECAP_TX_FORWARDED,		/**< Number of packets forwarded after decapsulation. */
+	NSS_GRE_SESSION_ENCAP_RX_RECEIVED,		/**< Number of packets received for encapsulation. */
+	NSS_GRE_SESSION_ENCAP_RX_DROPPED,		/**< Packets dropped while enqueuing for encapsulation. */
+	NSS_GRE_SESSION_ENCAP_RX_LINEAR_FAIL,		/**< Packets dropped during encapsulation linearization. */
+	NSS_GRE_SESSION_EXP_RX_KEY_ERROR,		/**< Receive key error. */
+	NSS_GRE_SESSION_EXP_RX_SEQ_ERROR,		/**< Receive Sequence number error. */
+	NSS_GRE_SESSION_EXP_RX_CS_ERROR,		/**< Receive checksum error */
+	NSS_GRE_SESSION_EXP_RX_FLAG_MISMATCH,		/**< Receive flag mismatch. */
+	NSS_GRE_SESSION_EXP_RX_MALFORMED,		/**< Receive packet is malformed. */
+	NSS_GRE_SESSION_EXP_RX_INVALID_PROTOCOL,	/**< Receive packet protocol is invalid. */
+	NSS_GRE_SESSION_EXP_RX_NO_HEADROOM,		/**< Packet does not have enough headroom. */
+	NSS_GRE_SESSION_DEBUG_MAX,			/**< Session debug maximum. */
+};
+
+/**
+ * GRE create message structure.
+ */
+struct nss_gre_config_msg {
+	uint32_t src_ip[4];			/**< Source IPv4 or IPv6 address. */
+	uint32_t dest_ip[4];			/**< Destination IPv4 or IPv6 address. */
+	uint32_t flags;				/**< GRE Flags. */
+	uint32_t ikey;				/**< GRE Rx key.*/
+	uint32_t okey;				/**< GRE Tx key. */
+	uint32_t mode;				/**< GRE TUN or TAP. */
+	uint32_t ip_type;			/**< IPv4 or IPv6 type. */
+	uint32_t next_node_if_num;		/**< To whom to forward packets. */
+	uint32_t sibling_if_num;        	/**< Sibling interface number. */
+	uint16_t src_mac[3];			/**< Source MAC address. */
+	uint16_t dest_mac[3];			/**< Destination MAC address. */
+	uint8_t ttl;				/**< TTL or HOPLIMIT. */
+	uint8_t tos;				/**< Type of service. */
+	uint16_t metadata_size;			/**< Metadata copy size. */
+};
+
+/**
+ * GRE link up message structure.
+ */
+struct nss_gre_linkup_msg {
+	int if_number;			/**< Interface number. */
+};
+
+/**
+ * GRE link down message structure
+ */
+struct nss_gre_linkdown_msg {
+	int if_number;			/**< Interface number. */
+};
+
+/**
+ * GRE deconfig message structure
+ */
+struct nss_gre_deconfig_msg {
+	int if_number;			/**< Interface number. */
+};
+
+/**
+ * GRE session statistics message.
+ */
+struct nss_gre_session_stats_msg {
+	struct nss_cmn_node_stats node_stats;		/**< Common node statistics. */
+	uint32_t stats[NSS_GRE_SESSION_DEBUG_MAX];	/**< Session debug statistics. */
+};
+
+/**
+ * GRE base statistics message.
+ */
+struct nss_gre_base_stats_msg {
+	uint32_t stats[NSS_GRE_BASE_DEBUG_MAX];		/**< Base debug statistics. */
+};
+
+/**
+ * nss_gre_base_stats_notification
+ *	GRE transmission statistics structure.
+ */
+struct nss_gre_base_stats_notification {
+	uint64_t stats_base_ctx[NSS_GRE_BASE_DEBUG_MAX];	/**< Base debug transmission statistics. */
+	uint32_t core_id;					/**< Core ID. */
+};
+
+/**
+ * nss_gre_session_stats_notification
+ *	GRE transmission statistics structure.
+ */
+struct nss_gre_session_stats_notification {
+	uint64_t stats_session_ctx[NSS_GRE_SESSION_DEBUG_MAX];		/**< Session debug transmission statistics. */
+	uint32_t core_id;						/**< Core ID. */
+	uint32_t if_num;						/**< Interface number. */
+};
+
+/**
+ * nss_gre_msg
+ *	Message structure to send/receive GRE messages.
+ */
+struct nss_gre_msg {
+	struct nss_cmn_msg cm;					/**< Common message header. */
+
+	/**
+	 * Payload of a GRE message.
+	 */
+	union {
+		struct nss_gre_config_msg cmsg;			/**< GRE session config message. */
+		struct nss_gre_deconfig_msg dmsg;		/**< GRE session deconfig message. */
+		struct nss_gre_linkup_msg linkup;		/**< GRE link up message. */
+		struct nss_gre_linkdown_msg linkdown;		/**< GRE link down message. */
+		struct nss_gre_session_stats_msg sstats;	/**< GRE session statistics message. */
+		struct nss_gre_base_stats_msg bstats;		/**< Base statistics message. */
+	} msg;							/**< Message payload. */
+};
+
+/**
+ * Callback function to receive GRE messages
+ *
+ * @datatypes
+ * nss_gre_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_gre_msg_callback_t)(void *app_data, struct nss_gre_msg *msg);
+
+/**
+ * nss_gre_tx_msg
+ *	Sends GRE messages to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_gre_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_gre_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_gre_msg *msg);
+
+/**
+ * nss_gre_tx_msg_sync
+ *	Sends GRE messages to the NSS synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_gre_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_gre_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_msg *msg);
+
+/**
+ * nss_gre_tx_buf
+ *	Sends a packet to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] if_num   Nss interface number.
+ * @param[in] skb      Pointer to sk_buff.
+ *
+ * @return Tx status
+ */
+extern nss_tx_status_t nss_gre_tx_buf(struct nss_ctx_instance *nss_ctx, uint32_t if_num, struct sk_buff *skb);
+
+/**
+ * nss_gre_get_context.
+ *	Gets the GRE context used in nss_gre_tx.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_gre_get_context(void);
+
+/**
+ *
+ * nss_gre_ifnum_with_core_id
+ * 	Append core ID on GRE interface.
+ *
+ * @param[in] if_num   NSS interface number.
+ *
+ * @return
+ * GRE interface number with core ID.
+ */
+extern int nss_gre_ifnum_with_core_id(int if_num);
+
+/**
+ * Callback function for receiving GRE session data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_gre_data_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_gre_register_if
+ *	Registers the GRE interface with the NSS for sending and
+ *	receiving messages.
+ *
+ * @datatypes
+ * nss_gre_data_callback_t \n
+ * nss_gre_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num         NSS interface number.
+ * @param[in] type           NSS interface type.
+ * @param[in] gre_callback   Callback for the data.
+ * @param[in] msg_callback   Callback for the message.
+ * @param[in] netdev         Pointer to the associated network device.
+ * @param[in] features       Socket buffer types supported by this interface.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_gre_register_if(uint32_t if_num, uint32_t type, nss_gre_data_callback_t gre_callback,
+					nss_gre_msg_callback_t msg_callback, struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_gre_unregister_if
+ *	Deregisters the GRE interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+. *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The tunnel interface must have been previously registered.
+ */
+extern void nss_gre_unregister_if(uint32_t if_num);
+
+/**
+ * nss_gre_msg_init
+ *	Initializes a GRE message.
+ *
+ * @datatypes
+ * nss_gre_msg
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    Interface number
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Pointer to the message callback.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_gre_msg_init(struct nss_gre_msg *ncm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data);
+
+/**
+ * nss_gre_register_handler
+ *	Registers the GRE interface with the NSS debug statistics handler.
+ *
+ * @return
+ * None.
+ */
+extern void nss_gre_register_handler(void);
+
+/**
+ * Callback function for updating stats.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ *
+ * @return
+ * None.
+ */
+typedef void (*nss_gre_pkt_callback_t)(struct net_device *netdev, struct sk_buff *skb);
+
+/**
+ * nss_gre_register_pkt_callback
+ *	Register for rx packet call back.
+ *
+ * @datatypes
+ * nss_gre_pkt_callback_t
+ *
+ * @param[in] cb  Call back function which needs to be registered.
+ *
+ * @return
+ * None.
+ */
+extern void nss_gre_register_pkt_callback(nss_gre_pkt_callback_t cb);
+
+/**
+ * nss_gre_unregister_pkt_callback
+ *	Unregister for rx packet call back.
+ *
+ * @datatypes
+ * nss_gre_pkt_callback_t
+ *
+ * @return
+ * None.
+ */
+extern void nss_gre_unregister_pkt_callback(void);
+
+/**
+ * nss_gre_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_gre_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * nss_gre_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_gre_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * @}
+ */
+
+#endif /* _NSS_GRE_H_ */
diff --git a/qca-nss-drv/exports/nss_gre_redir.h b/qca-nss-drv/exports/nss_gre_redir.h
new file mode 100644
index 0000000..b271841
--- /dev/null
+++ b/qca-nss-drv/exports/nss_gre_redir.h
@@ -0,0 +1,712 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, 2017-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_gre_redir.h
+ *	NSS GRE Redirect interface definitions.
+ */
+
+#ifndef __NSS_GRE_REDIR_H
+#define __NSS_GRE_REDIR_H
+
+/**
+ * @addtogroup nss_gre_redirect_subsystem
+ * @{
+ */
+
+#define NSS_GRE_REDIR_MAX_INTERFACES 24			/**< Maximum number of redirect interfaces. */
+#define NSS_GRE_REDIR_IP_DF_OVERRIDE_FLAG 0x80		/**< Override Do not Fragment bit in IPv4 flags. */
+#define NSS_GRE_REDIR_PER_PACKET_METADATA_OFFSET 4	/**< Offset of per packet metadata from start of packet. */
+#define NSS_GRE_REDIR_MAX_RADIO 5			/**< Maximum number of radios. */
+#define NSS_GRE_REDIR_HEADER_VERSION 0			/**< Version for GRE header. */
+
+/**
+ * nss_gre_redir_ip_hdr_type
+ *	IP header types.
+ */
+enum nss_gre_redir_ip_hdr_type {
+	NSS_GRE_REDIR_IP_HDR_TYPE_IPV4 = 1,
+	NSS_GRE_REDIR_IP_HDR_TYPE_IPV6 = 2,
+};
+
+/**
+ * nss_gre_redir_message_types
+ *	Message types for GRE redirect requests and responses.
+ */
+enum nss_gre_redir_message_types {
+	NSS_GRE_REDIR_TX_TUNNEL_INNER_CONFIGURE_MSG,	/**< Configure message for inner node. */
+	NSS_GRE_REDIR_TX_TUNNEL_OUTER_CONFIGURE_MSG,	/**< Configure message for outer node. */
+	NSS_GRE_REDIR_TX_INTERFACE_MAP_MSG,		/**< Interface map message. */
+	NSS_GRE_REDIR_TX_INTERFACE_UNMAP_MSG,		/**< Interface unmap message. */
+	NSS_GRE_REDIR_TX_SJACK_MAP_MSG,			/**< SJACK map message. */
+	NSS_GRE_REDIR_TX_SJACK_UNMAP_MSG,		/**< SJACK unmap message. */
+	NSS_GRE_REDIR_RX_STATS_SYNC_MSG,		/**< Statistics synchronization message. */
+	NSS_GRE_REDIR_EXCEPTION_DS_REG_CB_MSG,		/**< Configure message to register callback. */
+	NSS_GRE_REDIR_MAX_MSG_TYPES,			/**< Maximum message type. */
+};
+
+/**
+ * nss_gre_redir_error_types
+ *	Error types for GRE redirect configuration messages.
+ */
+enum nss_gre_redir_error_types {
+	NSS_GRE_REDIR_ERROR_NONE,			/**< Configuration successful. */
+	NSS_GRE_REDIR_ERROR_UNKNOWN_MSG_TYPE,		/**< Unknown configuration message type error. */
+	NSS_GRE_REDIR_ERROR_INVALID_IP_HDR_TYPE,	/**< Invalid IP header type error. */
+	NSS_GRE_REDIR_ERROR_MAP_TABLE_FULL,		/**< Map table full error. */
+	NSS_GRE_REDIR_ERROR_MAP_INVALID_PARAM,		/**< Invalid parameter with map message error. */
+	NSS_GRE_REDIR_ERROR_UNMAP_INVALID_PARAM,	/**< Invalid parameter with unmap message error. */
+	NSS_GRE_REDIR_ERROR_ENCAP_MAP_EXIST,		/**< Encapsulation map entry already exist. */
+	NSS_GRE_REDIR_ERROR_DECAP_MAP_EXIST,		/**< Decapsulation map entry already exist. */
+	NSS_GRE_REDIR_ERROR_ENCAP_MAP_ALLOC_FAIL,	/**< Encapsulation map entry allocation failure error. */
+	NSS_GRE_REDIR_ERROR_DECAP_MAP_ALLOC_FAIL,	/**< Decapsulation map entry allocation failure error. */
+	NSS_GRE_REDIR_ERROR_ENCAP_ENTRY_UNMAPPED,	/**< Encapsulation map entry already unmapped. */
+	NSS_GRE_REDIR_ERROR_DECAP_ENTRY_UNMAPPED,	/**< Decapsulation map entry already unmapped. */
+	NSS_GRE_REDIR_ERROR_INVALID_ETH_IF,		/**< Invalid Ethernet NSS interface. */
+	NSS_GRE_REDIR_ERROR_INVALID_VAP_NEXTHOP_IF,	/**< Invalid nexthop NSS interface. */
+	NSS_GRE_REDIR_ERROR_INVALID_PEER_INTERFACE,	/**< Invalid peer interface during tunnel configuration. */
+};
+
+/**
+ * nss_gre_redir_tunnel_types
+ *	GRE tunnel types.
+ */
+enum nss_gre_redir_tunnel_types {
+	NSS_GRE_REDIR_TUNNEL_TYPE_UNKNOWN,	/**< Reserved. */
+	NSS_GRE_REDIR_TUNNEL_TYPE_TUN,		/**< Tunnel mode. */
+	NSS_GRE_REDIR_TUNNEL_TYPE_DTUN,		/**< D-tunnel mode. */
+	NSS_GRE_REDIR_TUNNEL_TYPE_SPLIT,	/**< Split mode. */
+	NSS_GRE_REDIR_TUNNEL_TYPE_MAX,		/**< Maximum tunnel type. */
+};
+
+/**
+ * nss_gre_redir_stats_types
+ *	GRE redirect statistics types.
+ */
+enum nss_gre_redir_stats_types {
+	NSS_GRE_REDIR_STATS_TX_DROPS = NSS_STATS_NODE_MAX,
+						/**< Dropped transmit packets. */
+	NSS_GRE_REDIR_STATS_SJACK_RX_PKTS,	/**< SJACK receive packet counter. */
+	NSS_GRE_REDIR_STATS_SJACK_TX_PKTS,	/**< SJACK transmit packet counter. */
+	NSS_GRE_REDIR_STATS_OFFLOAD_RX_PKTS_0,	/**< Offload receive packet counter 0. */
+	NSS_GRE_REDIR_STATS_OFFLOAD_RX_PKTS_1,	/**< Offload receive packet counter 1. */
+	NSS_GRE_REDIR_STATS_OFFLOAD_RX_PKTS_2,	/**< Offload receive packet counter 2. */
+	NSS_GRE_REDIR_STATS_OFFLOAD_RX_PKTS_3,	/**< Offload receive packet counter 3. */
+	NSS_GRE_REDIR_STATS_OFFLOAD_RX_PKTS_4,	/**< Offload receive packet counter 4. */
+	NSS_GRE_REDIR_STATS_OFFLOAD_TX_PKTS_0,	/**< Offload transmit packet counter 0. */
+	NSS_GRE_REDIR_STATS_OFFLOAD_TX_PKTS_1,	/**< Offload transmit packet counter 1. */
+	NSS_GRE_REDIR_STATS_OFFLOAD_TX_PKTS_2,	/**< Offload transmit packet counter 2. */
+	NSS_GRE_REDIR_STATS_OFFLOAD_TX_PKTS_3,	/**< Offload transmit packet counter 3. */
+	NSS_GRE_REDIR_STATS_OFFLOAD_TX_PKTS_4,	/**< Offload transmit packet counter 4. */
+	NSS_GRE_REDIR_STATS_EXCEPTION_US_RX_PKTS,
+						/**< Upstream exception receive packet counter. */
+	NSS_GRE_REDIR_STATS_EXCEPTION_US_TX_PKTS,
+						/**< Upstream exception transmit packet counter. */
+	NSS_GRE_REDIR_STATS_EXCEPTION_DS_RX_PKTS,
+						/**< Downstream exception receive packet counter. */
+	NSS_GRE_REDIR_STATS_EXCEPTION_DS_TX_PKTS,
+						/**< Downstream exception transmit packet counter. */
+	NSS_GRE_REDIR_STATS_ENCAP_SG_ALLOC_DROP,
+						/**< Encapsulation drop counters due to scatter gather buffer allocation failure. */
+	NSS_GRE_REDIR_STATS_DECAP_FAIL_DROP,
+						/**< Decapsulation drop counters due to invalid IP header. */
+	NSS_GRE_REDIR_STATS_DECAP_SPLIT_DROP,
+						/**< Decapsulation drop counters due to split flow processing. */
+	NSS_GRE_REDIR_STATS_SPLIT_SG_ALLOC_FAIL,
+						/**< Split processing fail counter due to scatter gather buffer allocation failure. */
+	NSS_GRE_REDIR_STATS_SPLIT_LINEAR_COPY_FAIL,
+						/**< Split processing fail counter due to linear copy fail. */
+	NSS_GRE_REDIR_STATS_SPLIT_NOT_ENOUGH_TAILROOM,
+						/**< Split processing fail counter due to insufficient tailroom. */
+	NSS_GRE_REDIR_STATS_EXCEPTION_DS_INVALID_DST_DROP,
+						/**< Downstream exception handling fail counter due to invalid destination. */
+	NSS_GRE_REDIR_STATS_DECAP_EAPOL_FRAMES,
+						/**< Decapsulation EAPoL frame counters. */
+	NSS_GRE_REDIR_STATS_EXCEPTION_DS_INV_APPID,
+						/**< Invalid application ID for the transmit completion packets on exception downstream node. */
+	NSS_GRE_REDIR_STATS_HEADROOM_UNAVAILABLE,
+						/**< Packet headroom unavailable to write metadata. */
+	NSS_GRE_REDIR_STATS_TX_COMPLETION_SUCCESS,
+						/**< Host enqueue success count for the transmit completion packets. */
+	NSS_GRE_REDIR_STATS_TX_COMPLETION_DROP,
+						/**< Host enqueue drop count for the transmit completion packets. */
+	NSS_GRE_REDIR_STATS_MAX			/**< Maximum statistics type. */
+};
+
+/**
+ * nss_gre_redir_inner_configure_msg
+ *	Message information for configuring GRE inner node.
+ */
+struct nss_gre_redir_inner_configure_msg {
+	uint32_t ip_hdr_type;	/**< IP header type (IPv4 or IPv6). */
+
+	/**
+	 * IPv4 or IPv6 source address (lower 4 bytes are applicable for IPv4).
+	 */
+	uint32_t ip_src_addr[4];
+
+	/**
+	 * IPv4 or IPv6 destination address (lower 4 bytes are applicable for IPv4).
+	 */
+	uint32_t ip_dest_addr[4];
+
+	/**
+	 * The host outer-interface which handles post-encapsulation exception packets
+	 * originating from this inner interface.
+	 */
+	uint32_t except_outerif;
+
+	uint8_t ip_df_policy;	/**< Default Do Not Fragment policy for the IP header. */
+	uint8_t ip_ttl;		/**< Time-to-live value for the IP header. */
+	uint8_t gre_version;	/**< Header version. */
+};
+
+/**
+ * nss_gre_redir_outer_configure_msg
+ *	Message information for configuring GRE outer node.
+ */
+struct nss_gre_redir_outer_configure_msg {
+	uint32_t ip_hdr_type;		     /**< IP header type (IPv4 or IPv6). */
+
+	/**
+	 * The host inner-interface which handles post-decapsulation exception packets
+	 * originating from this outer interface, for flows destined to a VAP handled
+	 * by host.
+	 */
+	uint32_t except_hostif;
+
+	/**
+	 * The host inner-interface which handles post-decapsulation exception packets
+	 * originating from this outer interface, for flows destined to a VAP handled
+	 * by NSS.
+	 */
+	uint32_t except_offlif;
+
+	/**
+	 * The host inner-interface which handles post-decapsulation exception packets
+	 * originating from this outer interface, for flows destined to SJACK.
+	 */
+	uint32_t except_sjackif;
+
+	/**
+	 * CPU core to which these packets should be steered.
+	 * - 0 -- Use core 0
+	 * - 1 -- Use core 1
+	 * - 2 -- Use core 2
+	 * - 3 -- Use core 3
+	 */
+	uint8_t rps_hint;
+
+	/**
+	 * Flag to indicate validity of RPS hint.
+	 */
+	uint8_t rps_hint_valid;
+
+};
+
+/**
+ * nss_gre_redir_exception_ds_reg_cb_msg
+ *	Message information to register callback on VAP for GRE exception downstream.
+ */
+struct nss_gre_redir_exception_ds_reg_cb_msg {
+	uint32_t dst_vap_nssif;	/**< NSS VAP interface on which the callback is registered. */
+};
+
+/**
+ * nss_gre_redir_interface_map_msg
+ *	Message information for adding a VAP interface-to-tunnel ID mapping.
+ */
+struct nss_gre_redir_interface_map_msg {
+	uint32_t vap_nssif;			/**< NSS VAP interface. */
+	uint32_t nexthop_nssif;			/**< Next hop NSS interface number. */
+	uint16_t radio_id;			/**< Radio ID to derive tunnel ID. */
+	uint16_t vap_id;			/**< VAP ID to derive tunnel ID. */
+	uint16_t lag_en;			/**< Flag for LAG mode. */
+	uint16_t tunnel_type;			/**< Type of tunnel. */
+
+	/**
+	 * IPsec security association pattern. Pattern
+	 * 0x5A is supported only.
+	 */
+	uint8_t ipsec_pattern;
+};
+
+/**
+ * nss_gre_redir_interface_unmap_msg
+ *	Message information for deleting a VAP interface-to-tunnel ID mapping.
+ */
+struct nss_gre_redir_interface_unmap_msg {
+	uint32_t vap_nssif;	/**< NSS VAP interface. */
+	uint16_t radio_id;	/**< Radio ID to derive tunnel ID. */
+	uint16_t vap_id;	/**< VAP ID to derive tunnel ID. */
+};
+
+/**
+ * nss_gre_redir_sjack_map_msg
+ *	Message information for adding an Ethernet interface-to-tunnel ID mapping.
+ */
+struct nss_gre_redir_sjack_map_msg {
+	uint32_t eth_nssif;			/**< NSS Ethernet interface number. */
+	uint32_t eth_id;			/**< Ethernet interface ID. */
+
+	/**
+	 * IPsec security association pattern. Pattern
+	 * 0x5A is supported only.
+	 */
+	uint8_t ipsec_pattern;
+};
+
+/**
+ * nss_gre_redir_sjack_unmap_msg
+ *	Message information for deleting an Ethernet interface-to-tunnel ID mapping.
+ */
+struct nss_gre_redir_sjack_unmap_msg {
+	uint32_t eth_nssif;	/**< NSS Ethernet interface number. */
+	uint32_t eth_id;	/**< Ethernet interface ID. */
+};
+
+/**
+ * nss_gre_redir_stats_sync_msg
+ *	Message information for synchronized GRE redirect statistics.
+ */
+struct nss_gre_redir_stats_sync_msg {
+	struct nss_cmn_node_stats node_stats;		/**< Common node statistics. */
+	uint32_t sjack_rx_packets;			/**< SJACK packet counter. */
+	uint32_t offl_rx_pkts[NSS_GRE_REDIR_MAX_RADIO];	/**< Offload packet counter. */
+	uint32_t encap_sg_alloc_drop;			/**< Encapsulation drop counters due to scatter gather buffer allocation failure. */
+	uint32_t decap_fail_drop;			/**< Decapsulation drop counters due to invalid IP header. */
+	uint32_t decap_split_drop;			/**< Decapsulation drop counters due to split flow processing. */
+	uint32_t split_sg_alloc_fail;			/**< Split processing fail counter due to scatter gather buffer allocation failure. */
+	uint32_t split_linear_copy_fail;		/**< Split processing fail counter due to linear copy fail. */
+	uint32_t split_not_enough_tailroom;		/**< Split processing fail counter due to insufficient tailroom. */
+	uint32_t exception_ds_invalid_dst_drop;		/**< Downstream exception handling fail counter due to invalid destination. */
+	uint32_t decap_eapol_frames;			/**< Decapsulation EAPoL frame counters. */
+	uint32_t exception_ds_inv_appid;		/**< Invalid application ID for the Tx completion packets on exception downstream node. */
+	uint32_t headroom_unavail;			/**< Packet headroom unavailable to write metadata. */
+	uint32_t tx_completion_success;			/**< Host enqueue success count for the Tx completion packets. */
+	uint32_t tx_completion_drop;			/**< Host enqueue drop count for the Tx completion packets. */
+};
+
+/**
+ * nss_gre_redir_tun_stats
+ *	GRE redirect statistics to accumulate all stats values.
+ */
+struct nss_gre_redir_tun_stats {
+	uint64_t rx_packets;		/**< Number of packets received. */
+	uint64_t rx_bytes;		/**< Number of bytes received. */
+	uint64_t tx_packets;		/**< Number of packets transmitted. */
+	uint64_t tx_bytes;		/**< Number of bytes transmitted. */
+	uint64_t rx_dropped[NSS_MAX_NUM_PRI];
+					/**< Packets dropped on receive due to queue full. */
+	uint64_t tx_dropped;		/**< Dropped transmit packets. */
+	uint64_t sjack_rx_packets;	/**< SJACK receive packet counter. */
+	uint64_t sjack_tx_packets;	/**< SJACK transmit packet counter. */
+	uint64_t offl_rx_pkts[NSS_GRE_REDIR_MAX_RADIO];	/**< Offload receive packet counter per radio. */
+	uint64_t offl_tx_pkts[NSS_GRE_REDIR_MAX_RADIO];	/**< Offload transmit packet counter per radio. */
+	uint64_t exception_us_rx;	/**< Upstream exception receive packet counter. */
+	uint64_t exception_us_tx;	/**< Upstream exception transmit packet counter. */
+	uint64_t exception_ds_rx;	/**< Downstream exception receive packet counter. */
+	uint64_t exception_ds_tx;	/**< Downstream exception transmit packet counter. */
+	uint64_t encap_sg_alloc_drop;
+					/**< Encapsulation drop counters due to scatter gather buffer allocation failure. */
+	uint64_t decap_fail_drop;	/**< Decapsulation drop counters due to invalid IP header. */
+	uint64_t decap_split_drop;	/**< Decapsulation drop counters due to split flow processing. */
+	uint64_t split_sg_alloc_fail;
+					/**< Split processing fail counter due to scatter gather buffer allocation failure. */
+	uint64_t split_linear_copy_fail;
+					/**< Split processing fail counter due to linear copy fail. */
+	uint64_t split_not_enough_tailroom;
+					/**< Split processing fail counter due to insufficient tailroom. */
+	uint64_t exception_ds_invalid_dst_drop;
+					/**< Downstream exception handling fail counter due to invalid destination. */
+	uint64_t decap_eapol_frames;	/**< Decapsulation EAPoL frame counters. */
+	uint64_t exception_ds_inv_appid;
+					/**< Invalid application ID for the transmit completion packets on exception downstream node. */
+	uint64_t headroom_unavail;	/**< Packet headroom unavailable to write metadata. */
+	uint64_t tx_completion_success;	/**< Host enqueue success count for the transmit completion packets. */
+	uint64_t tx_completion_drop;	/**< Host enqueue drop count for the transmit completion packets. */
+};
+
+/**
+ * nss_gre_redir_tunnel_stats
+ *	GRE redirect statistics as seen by the HLOS.
+ */
+struct nss_gre_redir_tunnel_stats {
+	struct net_device *dev;			/**< Net device. */
+	struct nss_gre_redir_tun_stats tstats;	/**< Structure to accumulate all the statistics. */
+	uint32_t ref_count;			/**< Reference count for statistics. */
+};
+
+/**
+ * nss_gre_redir_stats_notification
+ *	GRE redirect transmission statistics structure.
+ */
+struct nss_gre_redir_stats_notification {
+	struct nss_gre_redir_tunnel_stats stats_ctx;	/**< Context transmission statistics. */
+	uint32_t core_id;				/**< Core ID. */
+	uint32_t if_num;				/**< Interface number. */
+};
+
+/**
+ * nss_gre_redir_msg
+ *	Data for sending and receiving GRE tunnel redirect messages.
+ */
+struct nss_gre_redir_msg {
+	struct nss_cmn_msg cm;	/**< Common message header. */
+
+	/**
+	 * Payload of a GRE tunnel redirect message.
+	 */
+	union {
+		struct nss_gre_redir_inner_configure_msg inner_configure;
+				/**< Configure a GRE inner node. */
+		struct nss_gre_redir_outer_configure_msg outer_configure;
+				/**< Configure a GRE outer node. */
+		struct nss_gre_redir_interface_map_msg interface_map;
+				/**< Add a VAP interface-to-tunnel ID mapping. */
+		struct nss_gre_redir_interface_unmap_msg interface_unmap;
+				/**< Delete a VAP interafce-to-tunnel ID mapping. */
+		struct nss_gre_redir_sjack_map_msg sjack_map;
+				/**< Add an Ethernet interface-to-tunnel ID mapping for SJACK. */
+		struct nss_gre_redir_sjack_unmap_msg sjack_unmap;
+				/**< Delete an Ethernet interface-to-tunnel ID mapping for SJACK. */
+		struct nss_gre_redir_stats_sync_msg stats_sync;
+				/**< Synchronized tunnel statistics. */
+		struct nss_gre_redir_exception_ds_reg_cb_msg exception_ds_configure;
+				/**< Registering callback on VAP for the GRE downstream flows. */
+	} msg;			/**< Message payload for GRE redirect messages exchanged with NSS core. */
+
+};
+
+/**
+ * nss_gre_redir_encap_per_pkt_metadata
+ *	Metadata information for an HLOS-to-NSS packet.
+ */
+struct nss_gre_redir_encap_per_pkt_metadata {
+	uint16_t gre_tunnel_id;			/**< ID of the tunnel. */
+	uint8_t gre_flags;			/**< Flags field from GRE header. */
+	uint8_t gre_prio;			/**< Priority field from GRE header. */
+	uint8_t gre_seq;			/**< Sequence number. */
+	uint8_t ip_dscp;			/**< DSCP values. */
+
+	/**
+	 * Override the default DF policy for the packet by setting bit 8.
+	 * The lower 7 bits provide the DF value to be used for this packet.
+	 */
+	uint8_t ip_df_override;
+
+	/**
+	 * IPsec security association pattern. Pattern
+	 * 0x5A is supported only.
+	 */
+	uint8_t ipsec_pattern;
+};
+
+/**
+ * nss_gre_redir_decap_per_pkt_metadata
+ *	Metadata information for an NSS-to-HLOS packet.
+ */
+struct nss_gre_redir_decap_per_pkt_metadata {
+	uint32_t src_if_num;    /**< Number of the source Ethernet interface. */
+	uint16_t gre_tunnel_id; /**< ID of the tunnel. */
+	uint8_t gre_flags;	/**< Flags from GRE header. */
+	uint8_t gre_prio;	/**< Priority from GRE header. */
+	uint8_t gre_seq;	/**< Sequence number. */
+};
+
+/**
+ * nss_gre_redir_exception_us_metadata
+ *	Metadata information for upstream exception packet.
+ *
+ * Note: Additional fields need to be added by customer as required.
+ */
+struct nss_gre_redir_exception_us_metadata {
+	uint8_t tid;		/**< TID value. */
+};
+
+/**
+ * nss_gre_redir_exception_ds_metadata
+ *	Metadata information for downstream exception packet.
+ *
+ * Note: Additional fields need to be added by customer as required.
+ */
+struct nss_gre_redir_exception_ds_metadata {
+	uint32_t dst_vap_nssif;	/**< Destination VAP interface number. */
+	uint8_t tid;		/**< TID value. */
+	uint8_t app_id;		/**< Application ID. */
+	uint16_t hw_hash_idx;	/**< Hardware AST hash index value. */
+	uint32_t tx_status;	/**< Tx status. */
+};
+
+/**
+ * Callback function for receiving GRE tunnel data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_gre_redir_data_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for receiving GRE tunnel messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_gre_redir_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * nss_gre_redir_unregister_if
+ *	Deregisters a GRE tunnel interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+. *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The tunnel interface must have been previously registered.
+ *
+ * @return
+ * True if successful, else false.
+ */
+extern bool nss_gre_redir_unregister_if(uint32_t if_num);
+
+/**
+ * nss_gre_redir_tx_msg
+ *	Sends GRE redirect tunnel messages.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_gre_redir_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_msg *msg);
+
+/**
+ * nss_gre_redir_tx_buf
+ *	Sends GRE redirect tunnel packets.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] os_buf   Pointer to the OS buffer (e.g., skbuff).
+ * @param[in] if_num   Tunnel interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf,
+		uint32_t if_num);
+
+/**
+ * nss_gre_redir_tx_buf_noreuse
+ *	Sends GRE redirect tunnel packets.
+ *
+ * Note: The buffers will be not be reused or
+ * kept in the accelerator.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] os_buf   Pointer to the OS buffer (e.g., skbuff).
+ * @param[in] if_num   Tunnel interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_tx_buf_noreuse(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf,
+			uint32_t if_num);
+
+/**
+ * nss_gre_redir_stats_get
+ *	Gets GRE redirect tunnel statistics.
+ *
+ * @datatypes
+ * nss_gre_redir_tunnel_stats
+ *
+ * @param[in]  index  Index in the tunnel statistics array.
+ * @param[out] stats  Pointer to the tunnel statistics.
+ *
+ * @return
+ * TRUE or FALSE.
+ */
+extern bool nss_gre_redir_stats_get(int index, struct nss_gre_redir_tunnel_stats *stats);
+
+/**
+ * nss_gre_redir_alloc_and_register_node
+ *	Allocates and registers GRE redirect dynamic node with NSS.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_gre_redir_data_callback_t \n
+ * nss_gre_redir_msg_callback_t \n
+ *
+ * @param[in] dev      Pointer to the associated network device.
+ * @param[in] data_cb  Callback for the data.
+ * @param[in] msg_cb   Callback for the message.
+ * @param[in] type     Type of dynamic node.
+ * @param[in] app_ctx  Application context for notify callback.
+ *
+ * @return
+ * NSS interface number allocated.
+ */
+extern int nss_gre_redir_alloc_and_register_node(struct net_device *dev,
+		nss_gre_redir_data_callback_t data_cb,
+		nss_gre_redir_msg_callback_t msg_cb,
+		uint32_t type, void *app_ctx);
+
+/**
+ * nss_gre_redir_configure_inner_node
+ *	Configures inner GRE redirect node.
+ *
+ * @datatypes
+ * nss_gre_redir_inner_configure_msg
+ *
+ * @param[in] ifnum              NSS interface number.
+ * @param[in] ngrcm              Inner node configuration message.
+ *
+ * @return
+ * Status of Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_configure_inner_node(int ifnum,
+		struct nss_gre_redir_inner_configure_msg *ngrcm);
+
+/**
+ * nss_gre_redir_configure_outer_node
+ *	Configures outer GRE redirect node.
+ *
+ * @datatypes
+ * nss_gre_redir_outer_configure_msg
+ *
+ * @param[in] ifnum              NSS interface number.
+ * @param[in] ngrcm              Outer node configuration message.
+ *
+ * @return
+ * Status of Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_configure_outer_node(int ifnum,
+		struct nss_gre_redir_outer_configure_msg *ngrcm);
+
+/**
+ * nss_gre_redir_exception_ds_reg_cb
+ *	Configure a callback on VAP for downstream GRE exception flows.
+ *
+ * @datatypes
+ * nss_gre_redir_exception_ds_reg_cb_msg
+ *
+ * @param[in] ifnum              NSS interface number.
+ * @param[in] ngrcm              Downstream exception callback registration message.
+ *
+ * @return
+ * Status of Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_exception_ds_reg_cb(int ifnum,
+		struct nss_gre_redir_exception_ds_reg_cb_msg *ngrcm);
+
+/**
+ * nss_gre_redir_tx_msg_sync
+ *	Sends messages to NSS firmware synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_gre_redir_msg
+ *
+ * @param[in] nss_ctx  NSS core context.
+ * @param[in] ngrm     Pointer to GRE redirect message data.
+ *
+ * @return
+ * Status of Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_msg *ngrm);
+
+/**
+ * nss_gre_redir_get_context
+ *	Gets the GRE redirect context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_gre_redir_get_context(void);
+
+/**
+ * nss_gre_redir_get_dentry
+ *	Returns directory entry created in debugfs for statistics.
+ *
+ * @return
+ * Pointer to created directory entry for GRE redirect.
+ */
+extern struct dentry *nss_gre_redir_get_dentry(void);
+
+/**
+ * nss_gre_redir_get_device
+ *	Gets the original device from probe.
+ *
+ * @return
+ * Pointer to the device.
+ */
+extern struct device *nss_gre_redir_get_device(void);
+
+/**
+ * nss_gre_redir_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_gre_redir_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * nss_gre_redir_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_gre_redir_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_GRE_REDIR_H */
diff --git a/qca-nss-drv/exports/nss_gre_redir_lag.h b/qca-nss-drv/exports/nss_gre_redir_lag.h
new file mode 100644
index 0000000..b10264d
--- /dev/null
+++ b/qca-nss-drv/exports/nss_gre_redir_lag.h
@@ -0,0 +1,732 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_gre_redir_lag.h
+ *	NSS GRE redirect LAG interface definitions.
+ */
+
+#ifndef __NSS_GRE_REDIR_LAG_H
+#define __NSS_GRE_REDIR_LAG_H
+
+/**
+ * @addtogroup nss_gre_redirect_subsystem
+ * @{
+ */
+
+#define NSS_GRE_REDIR_LAG_MAX_NODE 12			/**< Maximum number of LAG nodes. */
+#define NSS_GRE_REDIR_LAG_MAX_SLAVE 8			/**< Maximum number of GRE redirect nodes per LAG node. */
+#define NSS_GRE_REDIR_LAG_MIN_SLAVE 2			/**< Minimum required GRE redirect nodes per LAG node. */
+#define NSS_GRE_REDIR_LAG_US_STATS_SYNC_RETRY 3		/**< Number of retries for sending query hash messages. */
+#define NSS_GRE_REDIR_LAG_US_MAX_HASH_PER_MSG 80	/**< Maximum hash entries per message. */
+
+/*
+ * nss_gre_redir_lag_err_types
+ *	GRE redirect LAG error types.
+ */
+enum nss_gre_redir_lag_err_types {
+	NSS_GRE_REDIR_LAG_SUCCESS,
+	NSS_GRE_REDIR_LAG_ERR_INCORRECT_IFNUM,
+	NSS_GRE_REDIR_LAG_ERR_CORE_UNREGISTER_FAILED,
+	NSS_GRE_REDIR_LAG_ERR_STATS_INDEX_NOT_FOUND,
+	NSS_GRE_REDIR_LAG_ERR_DEALLOC_FAILED,
+	NSS_GRE_REDIR_LAG_ERR_MAX,
+};
+
+/**
+ * nss_gre_redir_lag_us_message_types
+ *	GRE redirect LAG upstream message types.
+ */
+enum nss_gre_redir_lag_us_message_types {
+	NSS_GRE_REDIR_LAG_US_CONFIG_MSG,
+	NSS_GRE_REDIR_LAG_US_ADD_HASH_NODE_MSG,
+	NSS_GRE_REDIR_LAG_US_DEL_HASH_NODE_MSG,
+	NSS_GRE_REDIR_LAG_US_QUERY_HASH_NODE_MSG,
+	NSS_GRE_REDIR_LAG_US_CMN_STATS_SYNC_MSG,
+	NSS_GRE_REDIR_LAG_US_DB_HASH_NODE_MSG,
+	NSS_GRE_REDIR_LAG_US_MAX_MSG_TYPES,
+};
+
+/**
+ * nss_gre_redir_lag_ds_message_types
+ *	GRE redirect LAG downstream message types.
+ */
+enum nss_gre_redir_lag_ds_message_types {
+	NSS_GRE_REDIR_LAG_DS_ADD_STA_MSG,
+	NSS_GRE_REDIR_LAG_DS_DEL_STA_MSG,
+	NSS_GRE_REDIR_LAG_DS_UPDATE_STA_MSG,
+	NSS_GRE_REDIR_LAG_DS_STATS_SYNC_MSG,
+	NSS_GRE_REDIR_LAG_DS_MAX_MSG_TYPES,
+};
+
+/**
+ * nss_gre_redir_lag_ds_stats_types
+ *	GRE redirect LAG downstream statistics.
+ */
+enum nss_gre_redir_lag_ds_stats_types {
+	NSS_GRE_REDIR_LAG_DS_STATS_DST_INVALID = NSS_STATS_NODE_MAX,
+							/**< Packets that do not have a valid destination. */
+	NSS_GRE_REDIR_LAG_DS_STATS_EXCEPTION_PKT,	/**< Packets that are exceptioned to host. */
+	NSS_GRE_REDIR_LAG_DS_STATS_MAX,			/**< Maximum statistics type. */
+};
+
+/**
+ * nss_gre_redir_lag_us_stats_types
+ *	GRE redirect LAG upstream statistics.
+ */
+enum nss_gre_redir_lag_us_stats_types {
+	NSS_GRE_REDIR_LAG_US_STATS_AMSDU_PKTS = NSS_STATS_NODE_MAX,
+							/**< Number of AMSDU packets seen. */
+	NSS_GRE_REDIR_LAG_US_STATS_AMSDU_PKTS_ENQUEUED,	/**< Number of AMSDU packets enqueued. */
+	NSS_GRE_REDIR_LAG_US_STATS_AMSDU_PKTS_EXCEPTIONED,
+							/**< Number of AMSDU packets exceptioned. */
+	NSS_GRE_REDIR_LAG_US_STATS_EXCEPTIONED,		/**< Number of exceptioned packets. */
+	NSS_GRE_REDIR_LAG_US_STATS_FREED,		/**< Freed packets when equeue to NSS to host fails. */
+	NSS_GRE_REDIR_LAG_US_STATS_ADD_ATTEMPT,		/**< Add hash attempts. */
+	NSS_GRE_REDIR_LAG_US_STATS_ADD_SUCCESS,		/**< Add hash success. */
+	NSS_GRE_REDIR_LAG_US_STATS_ADD_FAIL_TABLE_FULL,	/**< Add hash failed due to full table. */
+	NSS_GRE_REDIR_LAG_US_STATS_ADD_FAIL_EXISTS,	/**< Add hash failed as entry already exists. */
+	NSS_GRE_REDIR_LAG_US_STATS_DEL_ATTEMPT,		/**< Delete hash attempts. */
+	NSS_GRE_REDIR_LAG_US_STATS_DEL_SUCCESS,		/**< Delete hash success. */
+	NSS_GRE_REDIR_LAG_US_STATS_DEL_FAIL_NOT_FOUND,	/**< Delete hash failed as entry not found in hash table. */
+	NSS_GRE_REDIR_LAG_US_STATS_MAX,			/**< Maximum statistics type. */
+};
+
+/**
+ * nss_gre_redir_lag_us_hash_mode
+ *	GRE redirect LAG upstream hash modes.
+ */
+enum nss_gre_redir_lag_us_hash_mode {
+	NSS_GRE_REDIR_LAG_US_HASH_MODE_SRC_AND_DEST,
+	NSS_GRE_REDIR_LAG_US_HASH_MODE_SRC,
+	NSS_GRE_REDIR_LAG_US_HASH_MODE_DEST,
+	NSS_GRE_REDIR_LAG_US_HASH_MODE_MAX,
+};
+
+/**
+ * nss_gre_redir_lag_us_config_msg
+ *	Upstream configure message.
+ */
+struct nss_gre_redir_lag_us_config_msg {
+	uint32_t hash_mode;					/**< Hash operating mode. */
+	uint32_t num_slaves;					/**< Number of slaves. */
+	uint32_t if_num[NSS_GRE_REDIR_LAG_MAX_SLAVE];		/**< NSS interface numbers of GRE redirect tunnels. */
+};
+
+/**
+ * nss_gre_redir_lag_us_add_hash_node_msg
+ *	Message to add hash entry.
+ */
+struct nss_gre_redir_lag_us_add_hash_node_msg {
+	uint32_t if_num;			/**< NSS interface number of GRE redirect. */
+	uint16_t src_mac[ETH_ALEN / 2];		/**< Source MAC address. */
+	uint16_t dest_mac[ETH_ALEN / 2];	/**< Destination MAC address. */
+};
+
+/**
+ * nss_gre_redir_lag_us_del_hash_node_msg
+ *	Message to delete hash entry.
+ */
+struct nss_gre_redir_lag_us_del_hash_node_msg {
+	uint16_t src_mac[ETH_ALEN / 2];		/**< Source MAC address. */
+	uint16_t dest_mac[ETH_ALEN / 2];	/**< Destination MAC address. */
+};
+
+/**
+ * nss_gre_redir_lag_us_query_hash_node_msg
+ *	Message to query if a hash entry is present.
+ */
+struct nss_gre_redir_lag_us_query_hash_node_msg {
+	uint16_t src_mac[ETH_ALEN / 2];		/**< Source MAC address. */
+	uint16_t dest_mac[ETH_ALEN / 2];	/**< Destination MAC address. */
+	uint32_t ifnum;				/**< NSS interface number of GRE redirect. */
+};
+
+/**
+ * nss_gre_redir_lag_us_cmn_sync_stats
+ *	GRE redirect LAG upstream statistics.
+ */
+struct nss_gre_redir_lag_us_cmn_sync_stats {
+	uint32_t amsdu_pkts;			/**< Number of AMSDU packets seen. */
+	uint32_t amsdu_pkts_enqueued;		/**< Number of AMSDU packets enqueued. */
+	uint32_t amsdu_pkts_exceptioned;	/**< Number of AMSDU packets exceptioned. */
+	uint32_t exceptioned;			/**< Number of exceptioned packets. */
+	uint32_t freed;				/**< Number of freed packets. */
+};
+
+/**
+ * nss_gre_redir_lag_us_cmn_db_sync_stats
+ *	Upstream database statistics.
+ */
+struct nss_gre_redir_lag_us_cmn_db_sync_stats {
+	uint32_t add_attempt;		/**< Add hash attempts. */
+	uint32_t add_success;		/**< Add hash success. */
+	uint32_t add_fail_table_full;	/**< Add hash failed due to full table. */
+	uint32_t add_fail_exists;	/**< Add hash failed as entry already exists. */
+	uint32_t del_attempt;		/**< Delete hash attempts. */
+	uint32_t del_success;		/**< Delete hash success. */
+	uint32_t del_fail_not_found;	/**< Delete hash failed as entry not found in hash table. */
+};
+
+/**
+ * nss_gre_redir_lag_us_tunnel_hash_node_stats
+ *	Hash statistics for GRE redirect LAG.
+ */
+struct nss_gre_redir_lag_us_tunnel_hash_node_stats {
+	uint64_t hits;					/**< Number of hits on this hash entry. */
+	uint32_t if_num;				/**< GRE redirect interface number. */
+	uint16_t src_mac[ETH_ALEN / 2];			/**< Source MAC address. */
+	uint16_t dest_mac[ETH_ALEN / 2];		/**< Destination MAC address. */
+};
+
+/**
+ * nss_gre_redir_lag_us_hash_stats_query_msg
+ *	Hash statistics synchronization message.
+ */
+struct nss_gre_redir_lag_us_hash_stats_query_msg {
+	/*
+	 * Request.
+	 * Hash stats request has starting index of hash entry.
+	 * Request is initiated by driver periodically.
+	 */
+	uint16_t db_entry_idx;			/**< Starting index of request. */
+
+	/*
+	 * Response.
+	 * Response contains count of hash entries. It also has next field
+	 * which used as the request index in subsequent request by caller.
+	 */
+	uint16_t db_entry_next;			/**< Next index to be requested. */
+	uint16_t count;			/**< Number of hash entries in the message. */
+	uint16_t reserved;		/**< Reserved. */
+	struct nss_gre_redir_lag_us_tunnel_hash_node_stats hstats[NSS_GRE_REDIR_LAG_US_MAX_HASH_PER_MSG];
+					/**< Array of hash table entries. */
+};
+
+/**
+ * nss_gre_redir_lag_us_cmn_sync_stats_msg
+ *	Upstream statistics synchronization message.
+ */
+struct nss_gre_redir_lag_us_cmn_sync_stats_msg {
+	struct nss_cmn_node_stats node_stats;				/**< Common node statistics. */
+	struct nss_gre_redir_lag_us_cmn_sync_stats us_stats;		/**< Upstream statistics. */
+	struct nss_gre_redir_lag_us_cmn_db_sync_stats db_stats;		/**< Common hash statistics. */
+};
+
+/**
+ *nss_gre_redir_lag_us_msg
+ *	GRE redirect LAG upstream messages.
+ */
+struct nss_gre_redir_lag_us_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/*
+	 * Payload of a GRE redirect LAG message.
+	 */
+	union {
+		struct nss_gre_redir_lag_us_config_msg config_us;			/**< Upstream configuration message. */
+		struct nss_gre_redir_lag_us_add_hash_node_msg add_hash;			/**< Add hash entry. */
+		struct nss_gre_redir_lag_us_del_hash_node_msg del_hash;			/**< Delete hash entry. */
+		struct nss_gre_redir_lag_us_query_hash_node_msg query_hash;		/**< Hash entry query message. */
+		struct nss_gre_redir_lag_us_cmn_sync_stats_msg us_sync_stats;		/**< Upstream statistics. */
+		struct nss_gre_redir_lag_us_hash_stats_query_msg hash_stats;		/**< Hash statistics message. */
+	} msg;				/**< GRE redirect LAG upstream message payload. */
+};
+
+/**
+ * nss_gre_redir_lag_us_cmn_stats
+ *	GRE redirect LAG upstream statistics.
+ */
+struct nss_gre_redir_lag_us_cmn_stats {
+	uint64_t amsdu_pkts;			/**< Number of AMSDU packets seen. */
+	uint64_t amsdu_pkts_enqueued;		/**< Number of AMSDU packets enqueued. */
+	uint64_t amsdu_pkts_exceptioned;	/**< Number of AMSDU packets exceptioned. */
+	uint64_t exceptioned;			/**< Number of exceptioned packets. */
+	uint64_t freed;				/**< Freed packets when equeue to NSS to host fails. */
+};
+
+/**
+ * nss_gre_redir_lag_us_cmn_db_stats
+ *	Upstream database statistics.
+ */
+struct nss_gre_redir_lag_us_cmn_db_stats {
+	uint64_t add_attempt;		/**< Add hash attempts. */
+	uint64_t add_success;		/**< Add hash success. */
+	uint64_t add_fail_table_full;	/**< Add hash failed due to full table. */
+	uint64_t add_fail_exists;	/**< Add hash failed as entry already exists. */
+	uint64_t del_attempt;		/**< Delete hash attempts. */
+	uint64_t del_success;		/**< Delete hash success. */
+	uint64_t del_fail_not_found;	/**< Delete hash failed as entry not found in hash table. */
+};
+
+/**
+ * nss_gre_redir_lag_us_tunnel_stats
+ *	Upstream tunnel node statistics.
+ */
+struct nss_gre_redir_lag_us_tunnel_stats {
+	uint64_t rx_packets;					/**< Received packets. */
+	uint64_t rx_bytes;					/**< Received bytes. */
+	uint64_t tx_packets;					/**< Transmit packets. */
+	uint64_t tx_bytes;					/**< Transmit bytes. */
+	uint64_t rx_dropped[NSS_MAX_NUM_PRI];			/**< Packets dropped on receive due to queue full. */
+	struct nss_gre_redir_lag_us_cmn_stats us_stats;		/**< Common node statistics. */
+	struct nss_gre_redir_lag_us_cmn_db_stats db_stats;	/**< Common hash statistics. */
+};
+
+/**
+ * nss_gre_redir_lag_us_stats_notification
+ *	GRE redirect LAG upstream transmission statistics structure.
+ */
+struct nss_gre_redir_lag_us_stats_notification {
+	struct nss_gre_redir_lag_us_tunnel_stats stats_ctx;	/**< Context transmission statistics. */
+	uint32_t core_id;					/**< Core ID. */
+	uint32_t if_num;					/**< Interface number. */
+};
+
+/**
+ * nss_gre_redir_lag_ds_add_sta_msg
+ *	Message to add station in LAG deployment.
+ */
+struct nss_gre_redir_lag_ds_add_sta_msg {
+	uint16_t mac[ETH_ALEN / 2];		/**< Station MAC address. */
+	uint8_t reorder_type;			/**< Reorder type for downstream. */
+};
+
+/**
+ * nss_gre_redir_lag_ds_delete_sta_msg
+ *	Message to delete station in LAG deployment.
+ */
+struct nss_gre_redir_lag_ds_delete_sta_msg {
+	uint16_t mac[ETH_ALEN / 2];	/**< Station MAC address. */
+};
+
+/**
+ * nss_gre_redir_lag_ds_update_sta_msg
+ *	Message to update station.
+ */
+struct nss_gre_redir_lag_ds_update_sta_msg {
+	uint16_t mac[ETH_ALEN / 2];		/**< Station MAC address. */
+	uint8_t reorder_type;			/**< Reorder type for downstream. */
+};
+
+/**
+ * nss_gre_redir_lag_ds_stats
+ * 	GRE redirect link aggregation downstream statistics structure.
+ */
+struct nss_gre_redir_lag_ds_stats {
+	uint32_t dst_invalid;			/**< Invalid destination packets. */
+	uint32_t exception_cnt;			/**< Exception count. */
+};
+
+/**
+ * nss_gre_redir_lag_ds_sync_stats_msg
+ *	Downstream statistics synchronization message.
+ */
+struct nss_gre_redir_lag_ds_sync_stats_msg {
+	struct nss_cmn_node_stats node_stats;		/**< Common node statistics. */
+	struct nss_gre_redir_lag_ds_stats ds_stats;	/**< GRE redirect LAG downstream statistics. */
+};
+
+/**
+ *nss_gre_redir_lag_ds_msg
+ *	GRE redirect LAG downstream messages.
+ */
+struct nss_gre_redir_lag_ds_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a GRE redirect LAG downstream message.
+	 */
+	union {
+		struct nss_gre_redir_lag_ds_add_sta_msg add_sta;		/**< Add station entry. */
+		struct nss_gre_redir_lag_ds_delete_sta_msg del_sta;		/**< Delete station entry. */
+		struct nss_gre_redir_lag_ds_update_sta_msg update_sta;		/**< Station entry update message. */
+		struct nss_gre_redir_lag_ds_sync_stats_msg ds_sync_stats;	/**< Downstream statistics. */
+	} msg;				/**< GRE redirect LAG downstream message payload. */
+};
+
+/**
+ * nss_gre_redir_lag_ds_tun_stats
+ *	Downstream statistics.
+ */
+struct nss_gre_redir_lag_ds_tun_stats {
+	uint64_t rx_packets;		/**< Received packets. */
+	uint64_t rx_bytes;		/**< Received bytes. */
+	uint64_t tx_packets;		/**< Transmit packets. */
+	uint64_t tx_bytes;		/**< Transmit bytes. */
+	uint64_t rx_dropped[NSS_MAX_NUM_PRI];
+					/**< Packets dropped on receive due to queue full. */
+	uint64_t dst_invalid;		/**< Packets that do not have a valid destination. */
+	uint64_t exception_cnt;		/**< Packets that are exceptioned to host. */
+	uint32_t ifnum;			/**< NSS interface number. */
+	bool valid;			/**< Valid flag. */
+};
+
+/**
+ * nss_gre_redir_lag_ds_stats_notification
+ *	GRE redirect LAG downstream transmission statistics structure.
+ */
+struct nss_gre_redir_lag_ds_stats_notification {
+	struct nss_gre_redir_lag_ds_tun_stats stats_ctx;	/**< Context transmission statistics. */
+	uint32_t core_id;					/**< Core ID. */
+	uint32_t if_num;					/**< Interface number. */
+};
+
+/**
+ * Callback function for receiving GRE redirect LAG upstream data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_gre_redir_lag_us_data_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for receiving GRE redirect LAG downstream data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_gre_redir_lag_ds_data_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+ /**
+ * Callback function for receiving GRE redirect LAG upstream messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_gre_redir_lag_us_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+ /**
+ * Callback function for receiving GRE redirect LAG downstream messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_gre_redir_lag_ds_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * nss_gre_redir_lag_us_alloc_and_register_node
+ *	Allocates and registers GRE redirect upstream LAG node.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_gre_redir_lag_us_data_callback_t \n
+ * nss_gre_redir_lag_us_msg_callback_t
+ *
+ * @param[in] dev           Net device pointer.
+ * @param[in] cb_func_data  Data callback function.
+ * @param[in] cb_func_msg   Message callback function.
+ * @param[in] app_ctx       Application context for notify callback.
+ *
+ * @return
+ * Interface number if allocation and registration is succesful, else -1.
+ */
+extern int nss_gre_redir_lag_us_alloc_and_register_node(struct net_device *dev,
+		nss_gre_redir_lag_us_data_callback_t cb_func_data,
+		nss_gre_redir_lag_us_msg_callback_t cb_func_msg, void *app_ctx);
+
+/**
+ * nss_gre_redir_lag_ds_alloc_and_register_node
+ *	Allocates and registers GRE redirect downstream LAG node.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_gre_redir_lag_ds_data_callback_t \n
+ * nss_gre_redir_lag_ds_msg_callback_t
+ *
+ * @param[in] dev           Net device pointer.
+ * @param[in] cb_func_data  Data callback function.
+ * @param[in] cb_func_msg   Message callback function.
+ * @param[in] app_ctx       Application context for notify callback.
+ *
+ * @return
+ * Interface number if allocation and registration is succesful, else -1.
+ */
+extern int nss_gre_redir_lag_ds_alloc_and_register_node(struct net_device *dev,
+		nss_gre_redir_lag_ds_data_callback_t cb_func_data,
+		nss_gre_redir_lag_ds_msg_callback_t cb_func_msg, void *app_data);
+
+/**
+ * nss_gre_redir_lag_us_configure_node
+ *	Configures LAG upstream node.
+ *
+ * @datatypes
+ * nss_gre_redir_lag_us_config_msg
+ *
+ * @param[in] ifnum              NSS interface number.
+ * @param[in] ngluc              Pointer to LAG upstream node configuration message.
+ *
+ * @return
+ * True if successful, else false.
+ */
+extern bool nss_gre_redir_lag_us_configure_node(uint32_t ifnum,
+		struct nss_gre_redir_lag_us_config_msg *ngluc);
+
+/**
+ * nss_gre_redir_lag_us_unregister_and_dealloc
+ *	Deregister and deallocate GRE redirect upstream node.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * Error code.
+ *
+ * @dependencies
+ * The GRE redirect LAG interface must have been previously registered.
+ */
+extern enum nss_gre_redir_lag_err_types nss_gre_redir_lag_us_unregister_and_dealloc(uint32_t if_num);
+
+/**
+ * nss_gre_redir_lag_ds_unregister_and_dealloc
+ *	Deregisters and dealloc GRE redirect LAG downstream interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * Error code.
+ *
+ * @dependencies
+ * The GRE redirect LAG interface must have been previously registered.
+ */
+extern enum nss_gre_redir_lag_err_types nss_gre_redir_lag_ds_unregister_and_dealloc(uint32_t if_num);
+
+/**
+ * nss_gre_redir_lag_us_tx_msg
+ *	Sends GRE redirect upstream LAG messages asynchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_gre_redir_lag_us_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_lag_us_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_lag_us_msg *msg);
+
+/**
+ * nss_gre_redir_lag_ds_tx_msg
+ *	Sends GRE redirect downstream LAG messages asynchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_gre_redir_lag_ds_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_lag_ds_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_lag_ds_msg *msg);
+
+/**
+ * nss_gre_redir_lag_us_tx_buf
+ *	Sends packets to GRE Redirect LAG upstream node.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] os_buf   Pointer to the OS buffer (e.g., skbuff).
+ * @param[in] if_num   Tunnel interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_lag_us_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf,
+						uint32_t if_num);
+
+/**
+ * nss_gre_redir_lag_ds_tx_buf
+ *	Sends packets to GRE Redirect LAG downstream node.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] os_buf   Pointer to the OS buffer (e.g., skbuff).
+ * @param[in] if_num   Tunnel interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_lag_ds_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf,
+						uint32_t if_num);
+
+/**
+ * nss_gre_redir_lag_us_tx_msg_sync
+ *	Sends upstream LAG messages to NSS firmware synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_gre_redir_lag_us_msg
+ *
+ * @param[in] nss_ctx  NSS core context.
+ * @param[in] ngrm     Pointer to GRE redirect upstream LAG message data.
+ *
+ * @return
+ * Status of Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_lag_us_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_lag_us_msg *ngrm);
+
+/**
+ * nss_gre_redir_lag_ds_tx_msg_sync
+ *	Sends downstream LAG messages to NSS firmware synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_gre_redir_lag_ds_msg
+ *
+ * @param[in] nss_ctx  NSS core context.
+ * @param[in] ngrm     Pointer to GRE redirect downstream LAG message data.
+ *
+ * @return
+ * Status of Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_lag_ds_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_lag_ds_msg *ngrm);
+
+/**
+ * nss_gre_redir_lag_us_stats_get
+ *	Fetches common node statistics for upstream GRE Redir LAG.
+ *
+ * @datatypes
+ * nss_gre_redir_lag_us_tunnel_stats
+ *
+ * @param[out] cmn_stats  Pointer to common node statistics structure.
+ * @param[in]  index      Index to fetch statistics from.
+ *
+ * @return
+ * True if successful, else false.
+ */
+extern bool nss_gre_redir_lag_us_stats_get(struct nss_gre_redir_lag_us_tunnel_stats *cmn_stats, uint32_t index);
+
+/**
+ * nss_gre_redir_lag_ds_stats_get
+ *	Fetches common node statistics for downstream GRE Redir LAG.
+ *
+ * @datatypes
+ * nss_gre_redir_lag_ds_tun_stats
+ *
+ * @param[out] cmn_stats  Pointer to common node statistics structure.
+ * @param[in]  index      Index to fetch statistics from.
+ *
+ * @return
+ * True if successful, else false.
+ */
+extern bool nss_gre_redir_lag_ds_stats_get(struct nss_gre_redir_lag_ds_tun_stats *cmn_stats, uint32_t index);
+
+/**
+ * nss_gre_redir_lag_us_get_context
+ *	Gets the GRE redirect LAG upstream context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_gre_redir_lag_us_get_context(void);
+
+/**
+ * nss_gre_redir_lag_ds_get_context
+ *	Gets the GRE redirect LAG downstream context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_gre_redir_lag_ds_get_context(void);
+
+/**
+ * nss_gre_redir_lag_ds_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_gre_redir_lag_ds_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * nss_gre_redir_lag_ds_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_gre_redir_lag_ds_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_gre_redir_lag_us_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_gre_redir_lag_us_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * nss_gre_redir_lag_us_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_gre_redir_lag_us_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_GRE_REDIR_LAG_H */
diff --git a/qca-nss-drv/exports/nss_gre_redir_mark.h b/qca-nss-drv/exports/nss_gre_redir_mark.h
new file mode 100644
index 0000000..39e024b
--- /dev/null
+++ b/qca-nss-drv/exports/nss_gre_redir_mark.h
@@ -0,0 +1,338 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_gre_redir_mark.h
+ *	NSS GRE Redirect mark interface definitions.
+ */
+
+#ifndef __NSS_GRE_REDIR_MARK_H
+#define __NSS_GRE_REDIR_MARK_H
+
+#define NSS_GRE_REDIR_MARK_HLOS_MAGIC 0xaade	/**< Metadata magic set by HLOS. */
+#define NSS_GRE_REDIR_MARK_NSS_MAGIC 0xaadf	/**< Metadata magic set by NSS. */
+
+extern struct nss_gre_redir_mark_stats gre_mark_stats;
+
+/**
+ * nss_gre_redir_mark messages
+ *	Message types for GRE redirect mark requests and responses.
+ */
+enum nss_gre_redir_mark_msg_types {
+	NSS_GRE_REDIR_MARK_REG_CB_MSG,		/**< Register callback configuration message. */
+	NSS_GRE_REDIR_MARK_STATS_SYNC_MSG,	/**< Statistics synchronization message. */
+	NSS_GRE_REDIR_MARK_MSG_MAX,		/**< Maximum message type. */
+};
+
+/**
+ * nss_gre_redir_mark errors
+ *	Error codes for GRE redirect mark configuration message.
+ */
+enum nss_gre_redir_mark_error_types {
+	NSS_GRE_REDIR_MARK_ERROR_NONE,		/**< Configuration successful. */
+	NSS_GRE_REDIR_MARK_ERROR_INV_IF_NUM,	/**< Invalid interface number for callback registration. */
+	NSS_GRE_REDIR_MARK_ERROR_INV_ETH_TYPE,	/**< Invalid Ethernet type for the destination interface. */
+	NSS_GRE_REDIR_MARK_ERROR_TYPE_MAX
+};
+
+/**
+ * nss_gre_redir_mark_stats_types
+ *	GRE redirect mark statistics types.
+ */
+enum nss_gre_redir_mark_stats_types {
+	NSS_GRE_REDIR_MARK_STATS_HLOS_MAGIC_FAILED = NSS_STATS_NODE_MAX,
+							/**< HLOS magic fail count. */
+	NSS_GRE_REDIR_MARK_STATS_INV_DST_IF_DROPS,	/**< Invalid transmit interface drop count. */
+	NSS_GRE_REDIR_MARK_STATS_DST_IF_ENQUEUE,	/**< Next egress interface enqueue success count. */
+	NSS_GRE_REDIR_MARK_STATS_DST_IF_ENQUEUE_DROPS,	/**< Next egress interface enqueue drop count. */
+	NSS_GRE_REDIR_MARK_STATS_INV_APPID,		/**< Invalid application ID for the transmit completion packets. */
+	NSS_GRE_REDIR_MARK_STATS_HEADROOM_UNAVAILABLE,	/**< Packet headroom unavailable to write metadata. */
+	NSS_GRE_REDIR_MARK_STATS_TX_COMPLETION_SUCCESS,	/**< Transmit completion host enqueue success count. */
+	NSS_GRE_REDIR_MARK_STATS_TX_COMPLETION_DROPS,	/**< Transmit completion host enqueue drop count. */
+	NSS_GRE_REDIR_MARK_STATS_MAX			/**< Maximum statistics type. */
+};
+
+/**
+ * nss_gre_redir_mark_metadata
+ *	HLOS to NSS per packet downstream metadata.
+ */
+struct nss_gre_redir_mark_metadata {
+	uint32_t dst_ifnum;		/**< Destination Tx interface number. */
+	uint8_t wifi_tid;		/**< TID value. */
+	uint8_t app_id;			/**< Application ID. */
+	uint16_t hw_hash_idx;		/**< Hardware AST hash index value. */
+	uint32_t tx_status;		/**< Transmit status. */
+	uint16_t offset;		/**< Buffer offset from the metadata. */
+	uint16_t magic;			/**< Metadata magic. */
+};
+
+/**
+ * nss_gre_redir_mark_stats
+ *	GRE redirect mark statistics.
+ */
+struct nss_gre_redir_mark_stats_sync_msg {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics. */
+	uint32_t hlos_magic_fail;               /**< HLOS magic fail count. */
+	uint32_t invalid_dst_drop;		/**< Invalid transmit interface drop count. */
+	uint32_t dst_enqueue_success;		/**< Next egress interface enqueue success count. */
+	uint32_t dst_enqueue_drop;		/**< Next egress interface enqueue drop count. */
+	uint32_t inv_appid;			/**< Invalid application ID for the transmit completion packets. */
+	uint32_t headroom_unavail;		/**< Packet headroom unavailable to write metadata. */
+	uint32_t tx_completion_success;		/**< Transmit completion host enqueue success count. */
+	uint32_t tx_completion_drop;		/**< Transmit completion host enqueue drop count. */
+};
+
+/**
+ * nss_gre_redir_mark_register_cb_msg
+ *	Transmit completion function register configuration message.
+ */
+struct nss_gre_redir_mark_register_cb_msg {
+	uint32_t nss_if_num;	/**< NSS transmit interface number on which callback needs to be registered. */
+};
+
+/**
+ * nss_gre_redir_mark_stats_notification
+ *	GRE redirect mark transmission statistics structure.
+ */
+struct nss_gre_redir_mark_stats_notification {
+	uint64_t stats_ctx[NSS_GRE_REDIR_MARK_STATS_MAX];	/**< Context transmission statistics. */
+	uint32_t core_id;					/**< Core ID. */
+	uint32_t if_num;					/**< Interface number. */
+};
+
+/**
+ * nss_gre_redir_mark_msg
+ *	Structure that describes the interface message.
+ */
+struct nss_gre_redir_mark_msg {
+	struct nss_cmn_msg cm;		/**< Common message. */
+
+	/**
+	 * Payload of a GRE redirect mark message.
+	 */
+	union {
+		struct nss_gre_redir_mark_register_cb_msg reg_cb_msg;
+					/**< Configuration message to register for callback on completion. */
+		struct nss_gre_redir_mark_stats_sync_msg stats_sync;
+					/**< Mark node statistics synchronization. */
+	} msg;				/**< Message payload for GRE redirect mark messages exchanged with NSS core. */
+};
+
+/**
+ * Callback function for receiving GRE redirect mark data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_gre_redir_mark_data_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for receiving GRE redirect mark messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_gre_redir_mark_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * nss_gre_redir_mark_unregister_if
+ *      Deregisters a GRE redirect mark interface from the NSS.
+ *
+ * @param[in] if_num  GRE redirect mark interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The GRE redirect mark interface must have been previously registered.
+ *
+ * @return
+ * True if successful, else false.
+ */
+extern bool nss_gre_redir_mark_unregister_if(uint32_t if_num);
+
+/**
+ * nss_gre_redir_mark_tx_buf
+ *      Sends data buffers to NSS firmware asynchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] os_buf   Pointer to the OS buffer (e.g. skbuff).
+ * @param[in] if_num   GRE redirect mark interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_mark_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf,
+		uint32_t if_num);
+
+/**
+ * nss_gre_redir_mark_reg_cb
+ *	Configure a callback on VAP for downstream application flows.
+ *
+ * @datatypes
+ * nss_gre_redir_mark_register_cb_msg
+ *
+ * @param[in] ifnum  NSS interface number.
+ * @param[in] ngrcm  Downstream application callback registration message.
+ *
+ * @return
+ * Status of Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_mark_reg_cb(int ifnum,
+                struct nss_gre_redir_mark_register_cb_msg *ngrcm);
+
+/**
+ * nss_gre_redir_mark_tx_msg
+ *	Sends GRE redirect mark messages.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_gre_redir_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_mark_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_mark_msg *msg);
+
+/**
+ * nss_gre_redir_mark_tx_msg_sync
+ *	Sends messages to NSS firmware synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_gre_redir_mark_msg
+ *
+ * @param[in] nss_ctx  NSS core context.
+ * @param[in] ngrm     Pointer to GRE redirect mark message data.
+ *
+ * @return
+ * Status of Tx operation.
+ */
+extern nss_tx_status_t nss_gre_redir_mark_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_mark_msg *ngrm);
+
+/**
+ * nss_gre_redir_mark_stats_get
+ *      Gets GRE redirect mark statistics.
+ *
+ * @datatypes
+ * nss_gre_redir_mark_stats
+ *
+ * @param[out] stats  Pointer to the memory address, which must be large enough to
+ *                    hold all the statistics.
+ *
+ * @return
+ * TRUE or FALSE.
+ */
+extern bool nss_gre_redir_mark_stats_get(struct nss_gre_redir_mark_stats *stats);
+
+/**
+ * nss_gre_redir_alloc_and_register_node
+ *      Registers GRE redirect mark static node with NSS.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_gre_redir_mark_data_callback_t \n
+ * nss_gre_redir_mark_msg_callback_t
+ *
+ * @param[in] netdev       Pointer to the associated network device.
+ * @param[in] if_num       NSS interface number.
+ * @param[in] cb_func_data Callback for the data.
+ * @param[in] cb_func_msg  Callback for the message.
+ * @param[in] features     Data socket buffer types supported by this interface.
+ *
+ * @return
+ * NSS interface number allocated.
+ */
+extern struct nss_ctx_instance *nss_gre_redir_mark_register_if(struct net_device *netdev, uint32_t if_num,
+		nss_gre_redir_mark_data_callback_t cb_func_data, nss_gre_redir_mark_msg_callback_t cb_func_msg,
+		uint32_t features);
+
+/**
+ * nss_gre_redir_mark_get_context
+ *	Gets the GRE redirect mark context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_gre_redir_mark_get_context(void);
+
+/**
+ * nss_gre_redir_mark_get_dentry
+ *	Returns directory entry created in debug filesystem for statistics.
+ *
+ * @return
+ * Pointer to created directory entry for GRE redirect mark.
+ */
+extern struct dentry *nss_gre_redir_mark_get_dentry(void);
+
+/*
+ * nss_gre_redir_mark_get_device
+ *	Gets the original device from probe.
+ *
+ * @return
+ * Pointer to the device.
+ */
+extern struct device *nss_gre_redir_mark_get_device(void);
+
+/**
+ * nss_gre_redir_mark_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_gre_redir_mark_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * nss_gre_redir_mark_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_gre_redir_mark_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_GRE_REDIR_MARK_H */
diff --git a/qca-nss-drv/exports/nss_gre_tunnel.h b/qca-nss-drv/exports/nss_gre_tunnel.h
new file mode 100644
index 0000000..53f76ed
--- /dev/null
+++ b/qca-nss-drv/exports/nss_gre_tunnel.h
@@ -0,0 +1,428 @@
+/*
+ ****************************************************************************
+ * Copyright (c) 2016-2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ****************************************************************************
+ */
+
+/**
+ * @file nss_gre_tunnel.h
+ *	NSS GRE Tunnel interface definitions.
+ */
+
+#ifndef __NSS_GRE_TUNNEL_H
+#define __NSS_GRE_TUNNEL_H
+
+/**
+ * @addtogroup nss_gre_tunnel_subsystem
+ * @{
+ */
+
+/**
+ * Maximum number of supported GRE tunnel sessions.
+ */
+#define NSS_MAX_GRE_TUNNEL_SESSIONS 16
+
+/**
+ * nss_gre_tunnel_message_types
+ *	Message types for a GRE tunnel rule.
+ */
+enum nss_gre_tunnel_message_types {
+	NSS_GRE_TUNNEL_MSG_CONFIGURE,
+	NSS_GRE_TUNNEL_MSG_SESSION_DESTROY,
+	NSS_GRE_TUNNEL_MSG_STATS,
+	NSS_GRE_TUNNEL_MSG_CONFIGURE_DI_TO_WLAN_ID,
+	NSS_GRE_TUNNEL_MSG_INQUIRY,
+	NSS_GRE_TUNNEL_MSG_MAX,
+};
+
+/**
+ * nss_gre_tunnel_encrypt_types
+ *	Encryption types for a GRE tunnel.
+ */
+enum nss_gre_tunnel_encrypt_types {
+	NSS_GRE_TUNNEL_ENCRYPT_NONE,
+	NSS_GRE_TUNNEL_ENCRYPT_AES128_CBC,
+	NSS_GRE_TUNNEL_ENCRYPT_AES256_CBC,
+	NSS_GRE_TUNNEL_ENCRYPT_MAX,
+};
+
+/**
+ * nss_gre_tunnel_mode_types
+ *	Mode types for a GRE tunnel.
+ */
+enum nss_gre_tunnel_mode_types {
+	NSS_GRE_TUNNEL_MODE_GRE,
+	NSS_GRE_TUNNEL_MODE_GRE_UDP,
+	NSS_GRE_TUNNEL_MODE_MAX,
+};
+
+/**
+ * nss_gre_tunnel_ip_types
+ *	IP types for a GRE tunnel.
+ */
+enum nss_gre_tunnel_ip_types {
+	NSS_GRE_TUNNEL_IP_IPV4,
+	NSS_GRE_TUNNEL_IP_IPV6,
+	NSS_GRE_TUNNEL_IP_MAX,
+};
+
+/**
+ * nss_gre_tunnel_error_types
+ *	Error types for a GRE tunnel.
+ */
+enum nss_gre_tunnel_error_types {
+	NSS_GRE_TUNNEL_ERR_UNKNOWN_MSG = 1,
+	NSS_GRE_TUNNEL_ERR_IF_INVALID = 2,
+	NSS_GRE_TUNNEL_ERR_CPARAM_INVALID = 3,
+	NSS_GRE_TUNNEL_ERR_MODE_INVALID = 4,
+	NSS_GRE_TUNNEL_ERR_ENCRYPT_INVALID = 5,
+	NSS_GRE_TUNNEL_ERR_IP_INVALID = 6,
+	NSS_GRE_TUNNEL_ERR_ENCRYPT_IDX_INVALID = 7,
+	NSS_GRE_TUNNEL_ERR_NOMEM = 8,
+	NSS_GRE_TUNNEL_ERR_PROTO_TEB_INVALID = 9,
+	NSS_GRE_TUNNEL_ERR_SIBLING_IF = 10,
+	NSS_GRE_TUNNEL_ERR_CRYPTO_NODE_ID = 11,
+	NSS_GRE_TUNNEL_ERR_RPS = 12,
+	NSS_GRE_TUNNEL_ERR_DI_INVALID = 13,
+	NSS_GRE_TUNNEL_ERR_MAX,
+};
+
+/**
+ *  nss_gre_tunnel_stats_type
+ *	GRE tunnel session debug statistic counters.
+ */
+enum nss_gre_tunnel_stats_type {
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_PKTS,			/**< Number of packets received. */
+	NSS_GRE_TUNNEL_STATS_SESSION_TX_PKTS,			/**< Number of packets transmitted. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_QUEUE_0_DROPPED,	/**< Dropped receive packets 0. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_QUEUE_1_DROPPED,	/**< Dropped receive packets 1. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_QUEUE_2_DROPPED,	/**< Dropped receive packets 2. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_QUEUE_3_DROPPED,	/**< Dropped receive packets 3. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_MALFORMED,		/**< Malformed packet was received. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_INVALID_PROT,		/**< Invalid protocol was received. */
+	NSS_GRE_TUNNEL_STATS_SESSION_DECAP_QUEUE_FULL,		/**< Decapsulation queue is full. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_SINGLE_REC_DGRAM,	/**< Single fragment was received. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_INVALID_REC_DGRAM,	/**< Invalid fragment was received. */
+	NSS_GRE_TUNNEL_STATS_SESSION_BUFFER_ALLOC_FAIL,		/**< Buffer memory allocation failed. */
+	NSS_GRE_TUNNEL_STATS_SESSION_BUFFER_COPY_FAIL,		/**< Buffer memory copy failed. */
+	NSS_GRE_TUNNEL_STATS_SESSION_OUTFLOW_QUEUE_FULL,	/**< Outflow queue is full. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_DROPPED_HROOM,	/**< Packets dropped because of insufficent headroom. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_CBUFFER_ALLOC_FAIL,	/**< Receive crypto buffer allocation failed. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_CENQUEUE_FAIL,		/**< Receive enqueue-to-crypto failed. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_DECRYPT_DONE,		/**< Receive decryption is complete. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_FORWARD_ENQUEUE_FAIL,	/**< Receive forward enqueue failed. */
+	NSS_GRE_TUNNEL_STATS_SESSION_TX_CBUFFER_ALLOC_FAIL,	/**< Receive crypto buffer allocation failed. */
+	NSS_GRE_TUNNEL_STATS_SESSION_TX_CENQUEUE_FAIL,		/**< Transmit enqueue-to-crypto failed. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_DROPPED_TROOM,	/**< Packets dropped because of insufficent tailroom. */
+	NSS_GRE_TUNNEL_STATS_SESSION_TX_FORWARD_ENQUEUE_FAIL,	/**< Transmit forward enqueue failed. */
+	NSS_GRE_TUNNEL_STATS_SESSION_TX_CIPHER_DONE,		/**< Transmit cipher is complete. */
+	NSS_GRE_TUNNEL_STATS_SESSION_CRYPTO_NOSUPP,		/**< Error count for non-supported crypto packets. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_DROPPED_MH_VERSION,	/**< Receive drop: bad meta header. */
+	NSS_GRE_TUNNEL_STATS_SESSION_RX_UNALIGNED_PKT,		/**< Counter for unaligned packets. */
+	NSS_GRE_TUNNEL_STATS_SESSION_MAX,			/**< Maximum statistics type. */
+};
+
+/**
+ * nss_gre_tunnel_di_to_wlan_id
+ *	Dynamic interface to WLAN ID message structure.
+ */
+struct nss_gre_tunnel_di_to_wlan_id {
+	uint32_t dynamic_interface_num;		/**< Dynamic interface number. */
+	uint16_t wlan_id;			/**< WLAN ID number. */
+	uint16_t fwd_policy;                    /**< Forward policy bits. */
+};
+
+/**
+ * nss_gre_tunnel_configure
+ *	Message information for configuring a GRE tunnel.
+ */
+struct nss_gre_tunnel_configure {
+	uint32_t mh_version;		/**< Meta header version. */
+	uint8_t gre_mode;		/**< GRE or GRE plus UDP. */
+	uint8_t ip_type;		/**< IPv4 or IPv6. */
+	uint16_t encrypt_type;		/**< Encryption type. */
+	uint32_t src_ip[4];		/**< Source IPv4 or IPv6 address. */
+	uint32_t dest_ip[4];		/**< Destination IPv4 or IPv6 address. */
+	uint16_t src_port;		/**< GRE plus UDP only for the source. */
+	uint16_t dest_port;		/**< GRE plus UDP only for the destination. */
+	uint32_t crypto_node_id;	/**< Cryto node identifier. */
+	uint32_t crypto_idx_encrypt;	/**< Crypto index for encryption. */
+	uint32_t crypto_idx_decrypt;	/**< Crypto index for decryption. */
+	uint32_t word0;			/**< Word0 header. */
+	uint8_t iv_val[16];		/**< Initialization vector value. */
+	uint32_t sibling_if;		/**< Sibling interface number. */
+	uint8_t ttl;			/**< Time-to-live value of the IP header. */
+	int8_t rps;			/**< Steer packets to host core. */
+	uint16_t reserved;		/**< Reserved space. */
+	uint32_t word1;			/**< Word1 header. */
+	uint32_t word2;			/**< Word2 header. */
+	uint32_t word3;			/**< Word3 header. */
+};
+
+/**
+ * nss_gre_tunnel_stats
+ *	Message statistics for a GRE tunnel.
+ */
+struct nss_gre_tunnel_stats {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics. */
+	uint32_t rx_malformed;			/**< Malformed packet was received. */
+	uint32_t rx_invalid_prot;		/**< Invalid protocol was received. */
+	uint32_t decap_queue_full;		/**< Decapsulation queue is full. */
+	uint32_t rx_single_rec_dgram;		/**< Single fragment was received. */
+	uint32_t rx_invalid_rec_dgram;		/**< Invalid fragment was received. */
+	uint32_t buffer_alloc_fail;		/**< Buffer memory allocation failed. */
+	uint32_t buffer_copy_fail;		/**< Buffer memory copy failed. */
+	uint32_t outflow_queue_full;		/**< Outflow queue is full. */
+	uint32_t rx_dropped_hroom;
+				/**< Packets dropped because of insufficent headroom. */
+	uint32_t rx_cbuf_alloc_fail;
+				/**< Receive crypto buffer allocation failed. */
+	uint32_t rx_cenqueue_fail;		/**< Receive enqueue-to-crypto failed. */
+	uint32_t rx_decrypt_done;		/**< Receive decryption is complete. */
+	uint32_t rx_forward_enqueue_fail;	/**< Receive forward enqueue failed. */
+	uint32_t tx_cbuf_alloc_fail;
+				/**< Receive crypto buffer allocation failed. */
+	uint32_t tx_cenqueue_fail;		/**< Transmit enqueue-to-crypto failed. */
+	uint32_t rx_dropped_troom;
+				/**< Packets dropped because of insufficent tailroom. */
+	uint32_t tx_forward_enqueue_fail;	/**< Transmit forward enqueue failed. */
+	uint32_t tx_cipher_done;		/**< Transmit cipher is complete. */
+	uint32_t crypto_nosupp;
+				/**< Error count for non-supported crypto packets. */
+	uint32_t rx_dropped_mh_ver;		/**< Receive drop: bad meta header. */
+	uint32_t rx_unaligned_pkt;		/**< Counter for unaligned packets. */
+#if defined(NSS_HAL_IPQ807x_SUPPORT)
+	uint32_t crypto_resp_error[NSS_CRYPTO_CMN_RESP_ERROR_MAX];
+						/** Crypto response errors. */
+#endif
+};
+
+/**
+ * nss_gre_tunnel_stats_notification
+ *	GRE tunnel transmission statistics structure.
+ */
+struct nss_gre_tunnel_stats_notification {
+	uint64_t stats_ctx[NSS_GRE_TUNNEL_STATS_SESSION_MAX + NSS_CRYPTO_CMN_RESP_ERROR_MAX];
+							/**< Context transmission statistics. */
+	uint32_t core_id;				/**< Core ID. */
+	uint32_t if_num;				/**< Interface number. */
+};
+
+/**
+ * nss_gre_tunnel_msg
+ *	Data for sending and receiving GRE tunnel messages.
+ */
+struct nss_gre_tunnel_msg {
+	struct nss_cmn_msg cm;					/**< Common message header. */
+
+	/**
+	 * Payload of a GRE tunnel message.
+	 */
+	union {
+		struct nss_gre_tunnel_configure configure;	/**< Tunnel configuration data. */
+		struct nss_gre_tunnel_stats stats;		/**< Tunnel statistics. */
+		struct nss_gre_tunnel_di_to_wlan_id dtwi;	/**< Tunnel dynamic interface number to WLAN ID mapping. */
+	} msg;							/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving GRE tunnel messages.
+ *
+ * @datatypes
+ * nss_gre_tunnel_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_gre_tunnel_msg_callback_t)(void *app_data, struct nss_gre_tunnel_msg *msg);
+
+/**
+ * Callback function for receiving GRE tunnel session data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_gre_tunnel_data_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_gre_tunnel_tx_buf
+ *	Sends a GRE tunnel packet.
+ *
+ * @datatypes
+ * sk_buff \n
+ * nss_ctx_instance
+ *
+ * @param[in] skb      Pointer to the data socket buffer.
+ * @param[in] if_num   Tunnel interface number.
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_gre_tunnel_tx_buf(struct sk_buff *skb, uint32_t if_num, struct nss_ctx_instance *nss_ctx);
+
+/**
+ * nss_gre_tunnel_tx_msg
+ *	Sends a GRE tunnel message.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_gre_tunnel_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_gre_tunnel_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_gre_tunnel_msg *msg);
+
+/**
+ * nss_gre_tunnel_tx_msg_sync
+ *	Sends a GRE tunnel message synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_gre_tunnel_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_gre_tunnel_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_tunnel_msg *msg);
+
+/**
+ * nss_gre_tunnel_msg_init
+ *	Initalizes a GRE tunnel message.
+ *
+ * @datatypes
+ * nss_gre_tunnel_msg
+ *
+ * @param[in] ngtm      Pointer to the tunnel message.
+ * @param[in] if_num    Tunnel interface number.
+ * @param[in] type      Type of message.
+ * @param[in] len       Size of the payload.
+ * @param[in] cb        Pointer to the message callback.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_gre_tunnel_msg_init(struct nss_gre_tunnel_msg *ngtm, uint16_t if_num, uint32_t type, uint32_t len, void *cb, void *app_data);
+
+/**
+ * nss_gre_tunnel_get_ctx
+ *	Returns the NSS context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_gre_tunnel_get_ctx(void);
+
+/**
+ * nss_gre_tunnel_register_if
+ *	Registers a network device with the NSS for sending and receiving tunnel
+ *	messages.
+ *
+ * @datatypes
+ * nss_gre_tunnel_data_callback_t \n
+ * nss_gre_tunnel_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num    NSS interface number.
+ * @param[in] cb        Callback function for the message.
+ * @param[in] ev_cb     Callback for the GRE tunnel message.
+ * @param[in] netdev    Pointer to the associated network device.
+ * @param[in] features  Data socket buffer types supported by this interface.
+ * @param[in] app_ctx   Pointer to the application context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_gre_tunnel_register_if(uint32_t if_num,
+						nss_gre_tunnel_data_callback_t cb,
+						nss_gre_tunnel_msg_callback_t ev_cb,
+						struct net_device *netdev,
+						uint32_t features,
+						void *app_ctx);
+
+/**
+ * nss_gre_tunnel_unregister_if
+ *	Deregisters a network device from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The network device must have been previously registered.
+ */
+extern void nss_gre_tunnel_unregister_if(uint32_t if_num);
+
+/**
+ * nss_gre_tunnel_inquiry()
+ *	Inquiry if a GRE tunnel has been established in NSS FW.
+ *
+ * @param[in] inquiry_info  Query parameters similar to creation parameters.
+ * @param[in] cb            Pointer to the message callback.
+ * @param[in] app_data      Pointer to the application context of the message.
+ *
+ * @return
+ * Status of the Tx operation
+ */
+extern nss_tx_status_t nss_gre_tunnel_inquiry(
+		struct nss_gre_tunnel_configure *inquiry_info,
+		nss_gre_tunnel_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_gre_tunnel_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_gre_tunnel_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * nss_gre_tunnel_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_gre_tunnel_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_GRE_TUNNEL_H */
diff --git a/qca-nss-drv/exports/nss_if.h b/qca-nss-drv/exports/nss_if.h
new file mode 100644
index 0000000..1b9847a
--- /dev/null
+++ b/qca-nss-drv/exports/nss_if.h
@@ -0,0 +1,454 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_if.h
+ *	NSS interface definitions.
+ */
+
+#ifndef __NSS_IF_H
+#define __NSS_IF_H
+
+#define NSS_IF_TX_TIMEOUT 3000 /* 3 Seconds */
+
+/**
+ * @addtogroup nss_driver_subsystem
+ * @{
+ */
+
+/**
+ * nss_if_message_types
+ *	Message types for the NSS interface.
+ */
+enum nss_if_message_types {
+	NSS_IF_OPEN,
+	NSS_IF_CLOSE,
+	NSS_IF_LINK_STATE_NOTIFY,
+	NSS_IF_MTU_CHANGE,
+	NSS_IF_MAC_ADDR_SET,
+	NSS_IF_STATS,
+	NSS_IF_ISHAPER_ASSIGN,
+	NSS_IF_BSHAPER_ASSIGN,
+	NSS_IF_ISHAPER_UNASSIGN,
+	NSS_IF_BSHAPER_UNASSIGN,
+	NSS_IF_ISHAPER_CONFIG,
+	NSS_IF_BSHAPER_CONFIG,
+	NSS_IF_PAUSE_ON_OFF,
+	NSS_IF_VSI_ASSIGN,
+	NSS_IF_VSI_UNASSIGN,
+	NSS_IF_SET_NEXTHOP,
+	NSS_IF_SET_IGS_NODE,
+	NSS_IF_CLEAR_IGS_NODE,
+	NSS_IF_RESET_NEXTHOP,
+	NSS_IF_PPE_PORT_CREATE,
+	NSS_IF_PPE_PORT_DESTROY,
+	NSS_IF_MAX_MSG_TYPES = 9999,
+};
+
+/**
+ * nss_if_error_types
+ *	Error types for the NSS interface.
+ */
+enum nss_if_error_types {
+	NSS_IF_ERROR_NO_ISHAPERS,
+	NSS_IF_ERROR_NO_BSHAPERS,
+	NSS_IF_ERROR_NO_ISHAPER,
+	NSS_IF_ERROR_NO_BSHAPER,
+	NSS_IF_ERROR_ISHAPER_OLD,
+	NSS_IF_ERROR_BSHAPER_OLD,
+	NSS_IF_ERROR_ISHAPER_CONFIG_FAILED,
+	NSS_IF_ERROR_BSHAPER_CONFIG_FAILED,
+	NSS_IF_ERROR_TYPE_UNKNOWN,
+	NSS_IF_ERROR_TYPE_EOPEN,
+	NSS_IF_ERROR_TYPE_INVALID_MTU,
+	NSS_IF_ERROR_TYPE_INVALID_MAC_ADDR,
+	NSS_IF_ERROR_TYPE_VSI_NOT_MATCH,
+	NSS_IF_ERROR_TYPE_VSI_REASSIGN,
+	NSS_IF_ERROR_TYPE_VSI_INVALID,
+	NSS_IF_ERROR_TYPE_MAX = 9999,
+};
+
+/**
+ * nss_if_data_align
+ *	Data alignment modes for the NSS interface.
+ */
+enum nss_if_data_align {
+	NSS_IF_DATA_ALIGN_2BYTE = 0,
+	NSS_IF_DATA_ALIGN_4BYTE = 2,
+};
+
+/**
+ * nss_if_open
+ *	Message information for opening the NSS interface.
+ */
+struct nss_if_open {
+	uint32_t tx_desc_ring;	/**< Tx descriptor ring address. */
+	uint32_t rx_desc_ring;	/**< Rx descriptor ring address. */
+	uint32_t rx_forward_if;	/**< Forward received packets to this interface. */
+	uint32_t alignment_mode;/**< Header alignment mode. */
+};
+
+/**
+ * nss_if_close
+ *	Message information for closing the NSS interface.
+ */
+struct nss_if_close {
+	uint32_t reserved;	/**< Placeholder for the structure. */
+};
+
+/**
+ * nss_if_link_state_notify
+ *	Link state notification sent to the NSS interface.
+ */
+struct nss_if_link_state_notify {
+	uint32_t state;
+			/**< Link state UP is bit 0 set. Other bits are as defined by Linux to indicate speed and duplex. */
+};
+
+/**
+ * nss_if_mtu_change
+ *	MTU change for the NSS interface.
+ */
+struct nss_if_mtu_change {
+	uint16_t min_buf_size;	/**< Changed value for the minimum buffer size. */
+};
+
+/**
+ * nss_if_pause_on_off
+ *	Enables or disables a pause frame for the NSS interface.
+ */
+struct nss_if_pause_on_off {
+	uint32_t pause_on;	/**< Turn the pause frame ON or OFF. */
+};
+
+/**
+ * nss_if_mac_address_set
+ *	MAC address setting.
+ */
+struct nss_if_mac_address_set {
+	uint8_t mac_addr[ETH_ALEN];	/**< MAC address. */
+};
+
+/**
+ * nss_if_shaper_assign
+ *	Shaper assignment message.
+ */
+struct nss_if_shaper_assign {
+	uint32_t shaper_id;		/**< ID of the request. */
+	uint32_t new_shaper_id;		/**< ID of the response. */
+};
+
+/**
+ * nss_if_shaper_unassign
+ *	Shaper unassign message.
+ */
+struct nss_if_shaper_unassign {
+	uint32_t shaper_id;		/**< ID of the request. */
+};
+
+/**
+ * nss_if_shaper_configure
+ *	Shaper configuration message.
+ */
+struct nss_if_shaper_configure {
+	struct nss_shaper_configure config;	/**< Specific shaper message for a particular interface. */
+};
+
+/**
+ * nss_if_vsi_assign
+ *	VSI assignment message.
+ */
+struct nss_if_vsi_assign {
+	uint32_t vsi;		/**< Virtual interface number. */
+};
+
+/**
+ * nss_if_vsi_unassign
+ *	VSI unassign message.
+ */
+struct nss_if_vsi_unassign {
+	uint32_t vsi;		/**< Virtual interface number. */
+};
+
+/**
+ * nss_if_set_nexthop
+ *	Message to set nexthop for an interface.
+ */
+struct nss_if_set_nexthop {
+	uint32_t nexthop;	/**< Nexthop interface number. */
+};
+
+/**
+ * nss_if_igs_config
+ *	Ingress shaper set/clear configure message structure.
+ */
+struct nss_if_igs_config {
+	int32_t igs_num;	/**< Ingress shaper interface number. */
+};
+
+/**
+ * nss_if_ppe_port_create
+ *	Message to create PPE port.
+ */
+struct nss_if_ppe_port_create {
+	int32_t ppe_port_num;	/**< PPE port number returned by NSS. */
+};
+
+/**
+ * nss_if_msgs
+ *	Information for physical NSS interface command messages.
+ */
+union nss_if_msgs {
+	struct nss_if_link_state_notify link_state_notify;
+			/**< Link status notification. */
+	struct nss_if_open open;
+			/**< Open the NSS interface. */
+	struct nss_if_close close;
+			/**< Close the NSS interface. */
+	struct nss_if_mtu_change mtu_change;
+			/**< MTU change notification. */
+	struct nss_if_mac_address_set mac_address_set;
+			/**< MAC address setting. */
+	struct nss_cmn_node_stats stats;
+			/**< Synchronize the satistics. */
+	struct nss_if_shaper_assign shaper_assign;
+			/**< Assign the shaper. */
+	struct nss_if_shaper_unassign shaper_unassign;
+			/**< Unassign the shaper. */
+	struct nss_if_shaper_configure shaper_configure;
+			/**< Configure the shaper. */
+	struct nss_if_pause_on_off pause_on_off;
+			/**< ON or OFF notification for a Pause frame. */
+	struct nss_if_vsi_assign vsi_assign;
+			/**< Assign the VSI. */
+	struct nss_if_vsi_unassign vsi_unassign;
+			/**< Remove the VSI assignment. */
+	struct nss_if_set_nexthop set_nexthop;
+			/**< Set nexthop of interface. */
+	struct nss_if_igs_config config_igs;
+			/**< Configure an ingress shaper interface. */
+	struct nss_if_ppe_port_create ppe_port_create;
+			/**< Create a PPE port. */
+};
+
+/**
+ * nss_if_msg
+ *	Data for sending and receiving base class messages for all interface types.
+ */
+struct nss_if_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+	union nss_if_msgs msg;		/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving NSS interface messages.
+ *
+ * @datatypes
+ * nss_if_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_if_msg_callback_t)(void *app_data, struct nss_if_msg *msg);
+
+/**
+ * Callback function for receiving NSS interface data.
+ *
+ * TODO: Adjust to pass app_data as unknown to the
+ * list layer and netdev/sk as known.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ */
+typedef void (*nss_if_rx_callback_t)(struct net_device *netdev, struct sk_buff *skb);
+
+/**
+ * nss_if_register
+ *	Registers the NSS interface for sending and receiving GMAC packets and messages.
+ *
+ * @datatypes
+ * nss_if_rx_callback_t \n
+ * nss_if_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num        NSS interface number.
+ * @param[in] rx_callback   Receive callback for the packet.
+ * @param[in] msg_callback  Receive callback for message.
+ * @param[in] if_ctx        Pointer to the interface context provided in the
+                            callback. This context must be the OS network
+                            device context pointer (net_device in Linux).
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_if_register(uint32_t if_num,
+					nss_if_rx_callback_t rx_callback,
+					nss_if_msg_callback_t msg_callback,
+					struct net_device *if_ctx);
+
+/**
+ * nss_if_tx_buf
+ *	Sends GMAC packets to a specific physical or virtual network interface.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] os_buf   Pointer to the OS buffer (e.g., skbuff).
+ * @param[in] if_num   Network physical or virtual interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_if_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, uint32_t if_num);
+
+/**
+ * nss_if_tx_msg
+ *	Sends a message to the NSS interface.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_if_msg
+ *
+ * @param[in,out] nss_ctx  Pointer to the NSS context.
+ * @param[in]     nim      Pointer to the NSS interface message.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_if_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_if_msg *nim);
+
+/**
+ * nss_if_msg_sync
+ *	Sends a message to the NSS interface and waits for the response.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_if_msg
+ *
+ * @param[in,out] nss_ctx  Pointer to the NSS context.
+ * @param[in]     nim      Pointer to the NSS interface message.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_if_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_if_msg *nim);
+
+/**
+ * nss_if_set_nexthop
+ *	Configure the next hop for an interface.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] if_num   NSS interface number.
+ * @param[in] nexthop  NSS interface number for next hop node.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_if_set_nexthop(struct nss_ctx_instance *nss_ctx, uint32_t if_num, uint32_t nexthop);
+
+/**
+ * nss_if_reset_nexthop
+ *	De-configure the next hop for an interface.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] if_num   NSS interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_if_reset_nexthop(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+
+/**
+ * nss_if_change_mtu
+ *	Changes the MTU of the interface.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] if_num   NSS interface number.
+ * @param[in] mtu      New MTU.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+nss_tx_status_t nss_if_change_mtu(struct nss_ctx_instance *nss_ctx, nss_if_num_t if_num, uint16_t mtu);
+
+/**
+ * nss_if_change_mac_addr
+ *	Changes the MAC address of the interface.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] if_num   NSS interface number.
+ * @param[in] mac_addr New MAC address.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+nss_tx_status_t nss_if_change_mac_addr(struct nss_ctx_instance *nss_ctx, nss_if_num_t if_num, uint8_t *mac_addr);
+
+/**
+ * nss_if_vsi_unassign
+ *	Detaches the VSI ID from the given interface.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] if_num   NSS interface number.
+ * @param[in] vsi      VSI ID.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+nss_tx_status_t nss_if_vsi_unassign(struct nss_ctx_instance *nss_ctx, nss_if_num_t if_num, uint32_t vsi);
+
+/**
+ * nss_if_vsi_assign
+ *	Attaches the VSI ID to the given interface.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] if_num   NSS interface number.
+ * @param[in] vsi      VSI ID.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+nss_tx_status_t nss_if_vsi_assign(struct nss_ctx_instance *nss_ctx, nss_if_num_t if_num, uint32_t vsi);
+
+/**
+ * @}
+ */
+
+#endif /*  __NSS_IF_H */
diff --git a/qca-nss-drv/exports/nss_igs.h b/qca-nss-drv/exports/nss_igs.h
new file mode 100644
index 0000000..651fea4
--- /dev/null
+++ b/qca-nss-drv/exports/nss_igs.h
@@ -0,0 +1,213 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_igs.h
+ *	NSS ingress shaper interface definitions.
+ */
+
+#ifndef _NSS_IGS_H_
+#define _NSS_IGS_H_
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+#ifdef CONFIG_NET_CLS_ACT
+#include <net/act_api.h>
+#endif
+#endif
+
+/**
+ * @addtogroup nss_ingress_shaper_subsystem
+ * @{
+ */
+
+/**
+ * Maximum number of supported ingress shaping interfaces.
+ */
+#define NSS_MAX_IGS_DYNAMIC_INTERFACES 8
+
+/**
+ * nss_igs_msg_types
+ *	Message types for ingress shaper requests and responses.
+ */
+enum nss_igs_msg_types {
+	NSS_IGS_MSG_SYNC_STATS = NSS_IF_MAX_MSG_TYPES + 1,
+	NSS_IGS_MSG_MAX
+};
+
+/**
+ * nss_igs_node_stats
+ *	Ingress shaping node debug statistics structure.
+ */
+struct nss_igs_node_stats {
+	uint32_t tx_dropped;		/**< Dropped post shaping. */
+	uint32_t shaper_drop;		/**< Dropped during shaper enqueue. */
+	uint32_t ipv4_parse_fail;	/**< IPv4 parse fail. */
+	uint32_t ipv4_unknown_gre_type;	/**< IPv4 unknown GRE type. */
+	uint32_t ipv4_unknown_l4;	/**< IPv4 unknown L4 type. */
+	uint32_t ipv4_no_cme;		/**< IPv4 connection match entry not found. */
+	uint32_t ipv4_frag_initial;	/**< IPv4 initial fragment. */
+	uint32_t ipv4_frag_non_initial;	/**< Ipv4 subsequent fragment. */
+	uint32_t ipv4_malformed_udp;	/**< Incomplete IPv4 UDP packet. */
+	uint32_t ipv4_malformed_tcp;	/**< Incomplete IPv4 TCP packet. */
+	uint32_t ipv4_malformed_udpl;	/**< Incomplete IPv4 UDP-Lite packet. */
+	uint32_t ipv4_malformed_gre;	/**< Incomplete IPv4 GRE packet. */
+	uint32_t ipv6_parse_fail;	/**< IPv6 parse fail. */
+	uint32_t ipv6_unknown_l4;	/**< IPv6 unknown L4 type. */
+	uint32_t ipv6_no_cme;		/**< IPv6 connection match entry not found. */
+	uint32_t ipv6_frag_initial;	/**< IPv6 initial fragment. */
+	uint32_t ipv6_frag_non_initial;	/**< Ipv6 subsequent fragment. */
+	uint32_t ipv6_malformed_udp;	/**< Incomplete IPv6 UDP packet. */
+	uint32_t ipv6_malformed_tcp;	/**< Incomplete IPv6 TCP packet. */
+	uint32_t ipv6_malformed_udpl;	/**< Incomplete IPv6 UDP-Lite packet. */
+	uint32_t ipv6_malformed_frag;	/**< Incomplete IPv6 fragment. */
+	uint32_t event_no_si;		/**< No shaper configured. */
+	uint32_t eth_parse_fail;	/**< Ethernet header parse failed. */
+	uint32_t eth_unknown_type;	/**< Non-IP/PPPoE ether type. */
+	uint32_t pppoe_non_ip;		/**< Non-IP PPPoE packet. */
+	uint32_t pppoe_malformed;	/**< Incomplete PPPoE packet. */
+};
+
+/**
+ * nss_igs_stats_sync_msg
+ *	Message information for ingress shaping synchronization statistics.
+ */
+struct nss_igs_stats_sync_msg {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics. */
+	struct nss_igs_node_stats igs_stats;	/**< Debug statistics for ingress shaping. */
+};
+
+/**
+ * nss_igs_msg
+ *	Data for sending and receiving ingress shaper messages.
+ */
+struct nss_igs_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a ingress shaper message.
+	 */
+	union {
+		union nss_if_msgs if_msg;
+				/**< NSS interface base message. */
+		struct nss_igs_stats_sync_msg stats;
+				/**< Statistics message to host. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving ingress shaper messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_igs_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * nss_igs_get_context
+ *	Gets the ingress shaper context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_igs_get_context(void);
+
+/**
+ * nss_igs_register_if
+ *	Registers a ingress shaper interface with the NSS for sending and receiving messages.
+ *
+ * @datatypes
+ * nss_igs_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num          NSS interface number.
+ * @param[in] type            NSS interface type.
+ * @param[in] msg_callback    Callback for the ingress shaper message.
+ * @param[in] netdev          Pointer to the associated network device.
+ * @param[in] features        Data socket buffer types supported by this interface.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_igs_register_if(uint32_t if_num, uint32_t type,
+		nss_igs_msg_callback_t msg_callback, struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_igs_unregister_if
+ *	Deregisters a ingress shaper interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ */
+extern void nss_igs_unregister_if(uint32_t if_num);
+
+/**
+ * nss_igs_verify_if_num
+ *	Verify whether interface is an ingress shaper interface or not.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * True if interface is an ingress shaper interface.
+ */
+extern bool nss_igs_verify_if_num(uint32_t if_num);
+
+
+#ifdef CONFIG_NET_CLS_ACT
+/*
+ * nss_igs_module_save()
+ *	Save the ingress shaping module reference.
+ *
+ * @datatypes
+ * tc_action_ops \n
+ * module
+ *
+ * @param[in] act     Operation structure for ingress shaping action.
+ * @param[in] module  Module structure of ingress shaping module.
+ *
+ * @return
+ * None.
+ */
+extern void nss_igs_module_save(struct tc_action_ops *act, struct module *module);
+#endif
+
+/*
+ * nss_igs_module_get()
+ *	Get the ingress shaping module reference.
+ *
+ * @return
+ * False if not able to take the ingress shaping module reference, otherwise true.
+ *
+ */
+extern bool nss_igs_module_get(void);
+
+/*
+ * nss_igs_module_put()
+ *	Release the ingress shaping module reference.
+ *
+ * @return
+ * None.
+ */
+extern void nss_igs_module_put(void);
+
+/**
+ * @}
+ */
+#endif
diff --git a/qca-nss-drv/exports/nss_ipsec.h b/qca-nss-drv/exports/nss_ipsec.h
new file mode 100644
index 0000000..3a9de93
--- /dev/null
+++ b/qca-nss-drv/exports/nss_ipsec.h
@@ -0,0 +1,550 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipsec.h
+ *	NSS IPSec interface definitions.
+ */
+
+#ifndef __NSS_IPSEC_H
+#define __NSS_IPSEC_H
+
+/*
+ * For some reason Linux doesn't define this in if_arp.h,
+ * refer http://www.iana.org/assignments/arp-parameters/arp-parameters.xhtml
+ * for the full list
+ */
+
+/**
+ * @addtogroup nss_ipsec_subsystem
+ * @{
+ */
+
+#define NSS_IPSEC_ARPHRD_IPSEC 31
+		/**< ARP (iana.org) hardware type for an IPsec tunnel. */
+#define NSS_IPSEC_MAX_RULES 256
+		/**< Maximum number of rules supported. */
+#define NSS_IPSEC_MAX_SA NSS_CRYPTO_MAX_IDXS
+		/**< Maximum number of SAs supported. */
+
+#if (~(NSS_IPSEC_MAX_RULES - 1) & (NSS_IPSEC_MAX_RULES >> 1))
+#error "NSS Max SA should be a power of 2"
+#endif
+
+/**
+ * Size of an IPsec message.
+ */
+#define NSS_IPSEC_MSG_LEN (sizeof(struct nss_ipsec_msg) - sizeof(struct nss_cmn_msg))
+
+/**
+ * nss_ipsec_msg_type
+ *	Rules for the IPsec interface.
+ */
+enum nss_ipsec_msg_type {
+	NSS_IPSEC_MSG_TYPE_NONE = 0,
+	NSS_IPSEC_MSG_TYPE_ADD_RULE = 1,
+	NSS_IPSEC_MSG_TYPE_DEL_RULE = 2,
+	NSS_IPSEC_MSG_TYPE_FLUSH_TUN = 3,
+	NSS_IPSEC_MSG_TYPE_SYNC_SA_STATS = 4,
+	NSS_IPSEC_MSG_TYPE_SYNC_FLOW_STATS = 5,
+	NSS_IPSEC_MSG_TYPE_SYNC_NODE_STATS = 6,
+	NSS_IPSEC_MSG_TYPE_CONFIGURE_NODE = 7,
+	NSS_IPSEC_MSG_TYPE_MAX
+};
+
+/**
+ * nss_ipsec_status
+ *	Status types for the IPsec interface.
+ */
+typedef enum nss_ipsec_status {
+	NSS_IPSEC_STATUS_OK = 0,
+	NSS_IPSEC_STATUS_ENOMEM = 1,
+	NSS_IPSEC_STATUS_ENOENT = 2,
+	NSS_IPSEC_STATUS_MAX
+} nss_ipsec_status_t;
+
+/**
+ * nss_ipsec_error_type
+ *	Error types for the IPsec interface.
+ */
+enum nss_ipsec_error_type {
+	NSS_IPSEC_ERROR_TYPE_NONE = 0,
+	NSS_IPSEC_ERROR_TYPE_HASH_DUPLICATE = 1,
+	NSS_IPSEC_ERROR_TYPE_HASH_COLLISION = 2,
+	NSS_IPSEC_ERROR_TYPE_UNHANDLED_MSG = 3,
+	NSS_IPSEC_ERROR_TYPE_INVALID_RULE = 4,
+	NSS_IPSEC_ERROR_TYPE_MAX_SA = 5,
+	NSS_IPSEC_ERROR_TYPE_MAX_FLOW = 6,
+	NSS_IPSEC_ERROR_TYPE_INVALID_CINDEX = 7,
+	NSS_IPSEC_ERROR_TYPE_INVALID_IPVER = 8,
+	NSS_IPSEC_ERROR_TYPE_MAX
+};
+
+/**
+ * nss_ipsec_type
+ *	Operation types for the IPsec interface.
+ */
+enum nss_ipsec_type {
+	NSS_IPSEC_TYPE_NONE = 0,
+	NSS_IPSEC_TYPE_ENCAP = 1,
+	NSS_IPSEC_TYPE_DECAP = 2,
+	NSS_IPSEC_TYPE_MAX
+};
+
+/**
+ * nss_ipsec_tuple
+ *	Common IPsec rule selector tuple for encapsulation and decapsulation.
+ *
+ * This selector is used for preparing a lookup tuple for incoming packets.
+ * The tuple is used to derive the index into the rule table.
+ *
+ * Choosing the selector fields depends on the IPsec encapsulation or decapsulation
+ * package. The host has no understanding of the index derived from the selector fields,
+ * and thus it provides information for all entries in the structure.
+ *
+ * The encapsulation and decapsulation packages return the index in their respective
+ * tables to the host. The host stores the rule for future reference purposes.
+ */
+struct nss_ipsec_tuple {
+	uint32_t dst_addr[4];		/**< Destination IP address. */
+	uint32_t src_addr[4];		/**< Source IP address. */
+
+	uint32_t esp_spi;		/**< SPI index. */
+
+	uint16_t dst_port;		/**< Destination port (UDP or TCP). */
+	uint16_t src_port;		/**< Source port (UDP or TCP). */
+
+	uint8_t proto_next_hdr;		/**< IP header type. */
+	uint8_t ip_ver;			/**< IP version. */
+	uint8_t res[2];			/**< Reserved for 4-byte alignment. */
+};
+
+/**
+ * nss_ipsec_rule_oip
+ *	Common information about the IPsec rule outer IP header.
+ */
+struct nss_ipsec_rule_oip {
+	uint32_t dst_addr[4];		/**< IPv4 destination address to apply. */
+	uint32_t src_addr[4];		/**< IPv4 source address to apply. */
+
+	uint32_t esp_spi;		/**< ESP SPI index to apply. */
+
+	uint16_t dst_port;		/**< Destination port (UDP or TCP). */
+	uint16_t src_port;		/**< Source port (UDP or TCP). */
+
+	uint8_t ttl_hop_limit;		/**< IPv4 time-to-live value to apply. */
+	uint8_t ip_ver;			/**< IP version. */
+	uint8_t proto_next_hdr;         /**< IP header type. */
+	uint8_t res;			/**< Reserved for 4-byte alignment. */
+};
+
+/**
+ * nss_ipsec_rule_data
+ *	IPsec rule data used for per-packet transformation.
+ */
+struct nss_ipsec_rule_data {
+
+	uint16_t crypto_index;		/**< Crypto index for the security association. */
+	uint16_t window_size;		/**< ESP sequence number window. */
+
+	uint8_t cipher_blk_len;		/**< Size of the cipher block. */
+	uint8_t iv_len;			/**< Size of the initialization vector. */
+	uint8_t nat_t_req;		/**< NAT-T required. */
+	uint8_t esp_icv_len;		/**< Size of the ICV to be produced as a result of authentication. */
+
+	uint8_t esp_seq_skip;		/**< Skip an ESP sequence number. */
+	uint8_t esp_tail_skip;		/**< Skip an ESP trailer. */
+	uint8_t use_pattern;		/**< Use random pattern in a hash calculation. */
+	uint8_t enable_esn;		/**< Enable extended sequence number. */
+
+	uint8_t dscp;                   /**< Default DSCP value of the SA. */
+	uint8_t df;			/**< Default dont fragment value of the SA. */
+	uint8_t copy_dscp;		/**< The flag tells whether to copy DSCP from inner header. */
+	uint8_t copy_df;		/**< The flag tells Whether to copy DF from inner header. */
+
+	uint32_t res2[4];		/**< Reserved 16 bytes for future use. */
+};
+
+/**
+ * nss_ipsec_rule
+ *	Push message for IPsec rules.
+ *
+ * This message is sent from the host to the NSS for performing an operation
+ * on NSS rule tables.
+ */
+struct nss_ipsec_rule {
+	struct nss_ipsec_rule_oip oip;	/**< Per rule outer IP information. */
+	struct nss_ipsec_rule_data data;/**< Per rule data. */
+
+	uint32_t index;		/**< Index provided by the NSS. */
+	uint32_t sa_idx;	/**< Rule index for the security association table. */
+};
+
+/**
+ * nss_ipsec_configure_node
+ *	Push message for setting IPsec inline mode and initializing DMA rings.
+ */
+struct nss_ipsec_configure_node {
+	bool dma_redirect;	/**< Program redirect DMA ring. */
+	bool dma_lookaside;	/**< Program lookaside DMA ring. */
+};
+
+/**
+ * nss_ipsec_sa_stats
+ *	Packet statistics per security association.
+ */
+struct nss_ipsec_sa_stats {
+	uint32_t count;			/**< Packets processed. */
+	uint32_t bytes;			/**< Bytes processed. */
+	uint32_t no_headroom;		/**< Insufficient headroom. */
+	uint32_t no_tailroom;		/**< Insufficient tailroom. */
+	uint32_t no_resource;		/**< No crypto buffer. */
+	uint32_t fail_queue;		/**< Failed to enqueue. */
+	uint32_t fail_hash;		/**< Hash mismatch. */
+	uint32_t fail_replay;		/**< Replay check failure. */
+	uint64_t seq_num;		/**< Current sequence number. */
+	uint64_t window_max;		/**< Maximum size of the window. */
+	uint32_t window_size;		/**< Current window size. */
+	uint32_t fail_hash_cont;	/**< Consecutive hash fail count. */
+	uint8_t esn_enabled;		/**< Indicates whether ESN is enabled. */
+	uint8_t res[3];			/**< Reserved for future use. */
+} /** @cond */ __attribute__((packed))/** @endcond */;
+
+/**
+ * nss_ipsec_flow_stats
+ *	Per-flow statistics.
+ */
+struct nss_ipsec_flow_stats {
+	uint32_t processed;		/**< Packets processed for this flow. */
+
+	uint8_t use_pattern;		/**< Use random pattern. */
+	uint8_t res[3];			/**< Reserved for 4-byte alignment padding. */
+};
+
+/**
+ * nss_ipsec_node_stats
+ *	Per-node statistics.
+ */
+struct nss_ipsec_node_stats {
+	uint32_t enqueued;		/**< Packets enqueued to the node. */
+	uint32_t completed;		/**< Packets processed by the node. */
+	uint32_t linearized;		/**< Packet is linear. */
+	uint32_t exceptioned;		/**< Packets exception from the NSS. */
+	uint32_t fail_enqueue;		/**< Packets failed to enqueue. */
+	uint32_t redir_rx;		/**< Packets received in redirect ring. */
+	uint32_t fail_redir;		/**< Packets dropped in redirect ring. */
+};
+
+/**
+ * nss_ipsec_stats
+ *	Common statistics structure.
+ */
+union nss_ipsec_stats {
+	struct nss_ipsec_sa_stats sa;		/**< Security association statistics. */
+	struct nss_ipsec_flow_stats flow;	/**< Flow statistics. */
+	struct nss_ipsec_node_stats node;	/**< Node statistics. */
+};
+
+/**
+ * nss_ipsec_msg
+ *	Data for sending and receiving IPsec messages.
+ */
+struct nss_ipsec_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	uint32_t tunnel_id;		/**< ID of the tunnel associated with the message. */
+	struct nss_ipsec_tuple tuple;
+			/**< Tuple to look up the SA table for encapsulation or decapsulation. */
+	enum nss_ipsec_type type;	/**< Encapsulation or decapsulation operation. */
+
+	/**
+	 * Payload of an IPsec message.
+	 */
+	union {
+		struct nss_ipsec_rule rule;
+				/**< IPsec rule message. */
+		struct nss_ipsec_configure_node node;
+				/**< IPsec node message. */
+		union nss_ipsec_stats stats;
+				/**< Retrieve statistics for the tunnel. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving message notifications.
+ *
+ * @datatypes
+ * nss_ipsec_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_ipsec_msg_callback_t)(void *app_data, struct nss_ipsec_msg *msg);
+
+/**
+ * Callback function for receiving data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the message data.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_ipsec_buf_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_ipsec_tx_msg
+ *	Sends an IPsec message to the NSS HLOS driver.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_ipsec_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS HLOS driver context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_ipsec_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_ipsec_msg *msg);
+
+/**
+ * nss_ipsec_tx_msg_sync
+ *	Sends IPsec messages synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_ipsec_msg_type \n
+ * nss_ipsec_msg \n
+ * nss_ipsec_error_type
+ *
+ * @param[in]     nss_ctx  Pointer to the NSS context.
+ * @param[in]     if_num   Configuration interface number.
+ * @param[in]     type     Type of the message.
+ * @param[in]     len      Size of the payload.
+ * @param[in]     nim      Pointer to the message data.
+ * @param[in,out] resp     Response for the configuration.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_ipsec_tx_msg_sync(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+						enum nss_ipsec_msg_type type, uint16_t len,
+						struct nss_ipsec_msg *nim, enum nss_ipsec_error_type *resp);
+
+/**
+ * nss_ipsec_tx_buf
+ *	Sends a plain text packet to NSS for IPsec encapsulation or decapsulation.
+ *
+ * @datatypes
+ * sk_buff
+ *
+ * @param[in] skb     Pointer to the message data.
+ * @param[in] if_num  Pointer to the NSS interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_ipsec_tx_buf(struct sk_buff *skb, uint32_t if_num);
+
+/**
+ * nss_ipsec_notify_register
+ *	Registers an event callback handler with the HLOS driver.
+ *
+ * When registered, the message callback is called when the NSS
+ * sends a response to the message sent by the host.
+ *
+ * @datatypes
+ * nss_ipsec_msg_callback_t
+ *
+ * @param[in] if_num    NSS interface number.
+ * @param[in] cb        Callback function for the message.
+ * @param[in] app_data  Pointer to the context of the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_ipsec_notify_register(uint32_t if_num, nss_ipsec_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_ipsec_data_register
+ *	Registers a data callback handler with the HLOS driver.
+ *
+ * The HLOS driver calls the registered data callback to return
+ * the packet to the OS.
+ *
+ * @datatypes
+ * nss_ipsec_buf_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num    NSS interface number.
+ * @param[in] cb        Callback function for the data.
+ * @param[in] netdev    Pointer to the associated network device.
+ * @param[in] features  Data socket buffer types supported by this interface.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_ipsec_data_register(uint32_t if_num, nss_ipsec_buf_callback_t cb, struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_ipsec_notify_unregister
+ *	Deregisters the message notifier from the HLOS driver.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in,out] ctx     Pointer to the context of the HLOS driver.
+ * @param[in]     if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The message notifier must have been previously registered.
+ */
+extern void nss_ipsec_notify_unregister(struct nss_ctx_instance *ctx, uint32_t if_num);
+
+/**
+ * nss_ipsec_data_unregister
+ *	Deregisters the data notifier from the HLOS driver.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in,out] ctx     Pointer to the context of the HLOS driver.
+ * @param[in]     if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The data notifier must have been previously registered.
+ */
+extern void nss_ipsec_data_unregister(struct nss_ctx_instance *ctx, uint32_t if_num);
+
+/**
+ * nss_ipsec_get_context
+ *	Gets the NSS context for the IPsec handle.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_ipsec_get_context(void);
+
+/**
+ * nss_ipsec_get_ifnum
+ *	Gets the IPsec interface number with a core ID.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * Interface number with the core ID.
+ */
+extern int32_t nss_ipsec_get_ifnum(int32_t if_num);
+
+/**
+ * nss_ipsec_msg_init
+ *	Initializes an IPsec message.
+ *
+ * @datatypes
+ * nss_ipsec_msg \n
+ * nss_ipsec_msg_callback_t
+ *
+ * @param[in,out] nim       Pointer to the NSS interface message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_ipsec_msg_init(struct nss_ipsec_msg *nim, uint16_t if_num, uint32_t type, uint32_t len,
+				nss_ipsec_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_ipsec_get_encap_interface
+ *	Gets the NSS interface number to be used for IPsec encapsulation message.
+ *
+ * @return
+ * Encapsulation interface number.
+ */
+extern int32_t nss_ipsec_get_encap_interface(void);
+
+/**
+ * nss_ipsec_get_decap_interface
+ *	Gets the NSS interface number to be used for an IPsec decapsulation message.
+ *
+ * @return
+ * Decapsulation interface number.
+ */
+extern int32_t nss_ipsec_get_decap_interface(void);
+
+/**
+ * nss_ipsec_get_data_interface
+ *	Gets the NSS interface number to be used for an IPsec data transfer.
+ *
+ * @return
+ * NSS interface number.
+ */
+extern int32_t nss_ipsec_get_data_interface(void);
+
+/**
+ * nss_ipsec_ppe_port_config
+ *	Configure Packet Processing Engine IPsec port.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * net_device
+ *
+ * @param[in] ctx     Pointer to the context of the HLOS driver.
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] if_num  Data interface number.
+ * @param[in] vsi_num Virtual switch instance number.
+ *
+ * @return
+ * True if successful, else false.
+ */
+extern bool nss_ipsec_ppe_port_config(struct nss_ctx_instance *ctx, struct net_device *netdev,
+				uint32_t if_num, uint32_t vsi_num);
+
+/**
+ * nss_ipsec_ppe_mtu_update()
+ *	Configure Packet Processing Engine MTU for IPsec in-line.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ *
+ * @param[in] ctx     Pointer to the context of the HLOS driver.
+ * @param[in] if_num  Data interface number.
+ * @param[in] mtu     Maximum transmission unit of Interface number.
+ * @param[in] mru     Maximum Receive unit of Interface number.
+ *
+ * @return
+ * True if successful, else false.
+ */
+bool nss_ipsec_ppe_mtu_update(struct nss_ctx_instance *ctx, uint32_t if_num, uint16_t mtu, uint16_t mru);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_IPSEC_H */
diff --git a/qca-nss-drv/exports/nss_ipsec_cmn.h b/qca-nss-drv/exports/nss_ipsec_cmn.h
new file mode 100644
index 0000000..5320b3f
--- /dev/null
+++ b/qca-nss-drv/exports/nss_ipsec_cmn.h
@@ -0,0 +1,691 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipsec_cmn.h
+ *	NSS IPsec interface definitions.
+ */
+
+#ifndef __NSS_IPSEC_CMN_H_
+#define __NSS_IPSEC_CMN_H_
+
+/**
+ * @addtogroup nss_ipsec_subsystem
+ * @{
+ */
+
+#define NSS_IPSEC_CMN_ARPHRD_IPSEC 31 /**< ARP (iana.org) hardware type for an IPsec tunnel. */
+
+/**
+ * Flags for SA configuration.
+ */
+#define NSS_IPSEC_CMN_FLAG_IPV6 (0x1 << 0)		/**< IPv6 header. */
+#define NSS_IPSEC_CMN_FLAG_IPV4_NATT (0x1 << 1)		/**< IPv4 NAT traversal. */
+#define NSS_IPSEC_CMN_FLAG_IPV4_UDP (0x1 << 2)		/**< IPv4 UDP traversal. */
+#define NSS_IPSEC_CMN_FLAG_ESP_ESN (0x1 << 3)		/**< Enable ESP extended sequence number. */
+#define NSS_IPSEC_CMN_FLAG_ESP_SKIP (0x1 << 4)		/**< Skip ESP sequence number and ICV. */
+#define NSS_IPSEC_CMN_FLAG_ESP_REPLAY (0x1 << 5)	/**< Check ESP replay counter. */
+#define NSS_IPSEC_CMN_FLAG_CIPHER_NULL (0x1 << 6)	/**< NULL cipher mode. */
+#define NSS_IPSEC_CMN_FLAG_CIPHER_GCM (0x1 << 7)	/**< Galios counter mode. */
+#define NSS_IPSEC_CMN_FLAG_COPY_DSCP (0x1 << 8)		/**< Copy DSCP from inner to outer header. */
+#define NSS_IPSEC_CMN_FLAG_COPY_DF (0x1 << 9)		/**< Copy DF from inner node to outer node. */
+#define NSS_IPSEC_CMN_FLAG_MODE_TRANS (0x1 << 10)	/**< Encapsulate or decapsulate in transport mode (default is tunnel mode). */
+
+#define NSS_IPSEC_CMN_FLAG_HDR_MASK \
+	(NSS_IPSEC_CMN_FLAG_IPV6 | NSS_IPSEC_CMN_FLAG_IPV4_NATT | NSS_IPSEC_CMN_FLAG_IPV4_UDP)
+							/**< Flag header mask. */
+
+#define NSS_IPSEC_CMN_FEATURE_INLINE_ACCEL 0x1		/**< Interface enabled for inline exception. */
+
+#define NSS_IPSEC_CMN_MDATA_VERSION 0x01		/**< Metadata version. */
+#define NSS_IPSEC_CMN_MDATA_MAGIC 0x8893		/**< Metadata magic. */
+#define NSS_IPSEC_CMN_MDATA_ORIGIN_HOST 0x01		/**< Metadata originates at the host. */
+#define NSS_IPSEC_CMN_MDATA_ALIGN_SZ sizeof(uint32_t)	/**< Metadata alignment size. */
+/**
+ * nss_ipsec_cmn_msg_type
+ *	IPsec message types.
+ */
+enum nss_ipsec_cmn_msg_type {
+	NSS_IPSEC_CMN_MSG_TYPE_NONE = 0,		/**< Nothing to do. */
+	NSS_IPSEC_CMN_MSG_TYPE_NODE_CONFIG = 1,		/**< Configure IPsec node. */
+	NSS_IPSEC_CMN_MSG_TYPE_CTX_CONFIG = 2,		/**< Configure IPsec dynamic node. */
+	NSS_IPSEC_CMN_MSG_TYPE_CTX_SYNC = 3,		/**< Synchronize context statistics to host. */
+	NSS_IPSEC_CMN_MSG_TYPE_SA_CREATE = 4,		/**< Create SA. */
+	NSS_IPSEC_CMN_MSG_TYPE_SA_DESTROY = 5,		/**< Destroy SA. */
+	NSS_IPSEC_CMN_MSG_TYPE_SA_SYNC = 6,		/**< Synchronize SA statistics to host. */
+	NSS_IPSEC_CMN_MSG_TYPE_FLOW_CREATE = 7,		/**< Create flow. */
+	NSS_IPSEC_CMN_MSG_TYPE_FLOW_DESTROY = 8,	/**< Delete flow. */
+	NSS_IPSEC_CMN_MSG_TYPE_MAX
+};
+
+/**
+ * nss_ipsec_cmn_msg_error
+ *	IPsec message error types.
+ */
+enum nss_ipsec_cmn_msg_error {
+	NSS_IPSEC_CMN_MSG_ERROR_NONE = 0,		/**< No error. */
+	NSS_IPSEC_CMN_MSG_ERROR_CTX_INVAL = 1,		/**< Invalid context. */
+	NSS_IPSEC_CMN_MSG_ERROR_SA_ALLOC = 2,		/**< Failed to allocate SA. */
+	NSS_IPSEC_CMN_MSG_ERROR_SA_INVAL = 3,		/**< Invalid SA. */
+	NSS_IPSEC_CMN_MSG_ERROR_SA_DUP = 4,			/**< SA exists. */
+	NSS_IPSEC_CMN_MSG_ERROR_SA_INUSE = 5,		/**< SA is in use. */
+	NSS_IPSEC_CMN_MSG_ERROR_FLOW_ALLOC = 6,		/**< Failed to allocate flow. */
+	NSS_IPSEC_CMN_MSG_ERROR_FLOW_INVAL = 7,		/**< Flow not found. */
+	NSS_IPSEC_CMN_MSG_ERROR_FLOW_DUP = 8,		/**< Duplicate flow. */
+	NSS_IPSEC_CMN_MSG_ERROR_FLOW_SA = 9,		/**< Failed to find SA for the flow. */
+	NSS_IPSEC_CMN_MSG_ERROR_NODE_REG_DYNIF = 10,
+							/**< Error registering dynamic interface. */
+	NSS_IPSEC_CMN_MSG_ERROR_UNHANDLED_MSG= 11,	/**< Unhandled message type. */
+	NSS_IPSEC_CMN_MSG_ERROR_MAX			/**< Maximum error message. */
+};
+
+/**
+ * nss_ipsec_cmn_ctx_type
+ *	IPsec context type.
+ */
+enum nss_ipsec_cmn_ctx_type {
+	NSS_IPSEC_CMN_CTX_TYPE_NONE = 0,	/**< Invalid direction. */
+	NSS_IPSEC_CMN_CTX_TYPE_INNER,		/**< Encapsulation. */
+	NSS_IPSEC_CMN_CTX_TYPE_MDATA_INNER,	/**< Metadata for encapsulation. */
+	NSS_IPSEC_CMN_CTX_TYPE_OUTER,		/**< Decapsulation. */
+	NSS_IPSEC_CMN_CTX_TYPE_MDATA_OUTER,	/**< Metadata for decapsulation. */
+	NSS_IPSEC_CMN_CTX_TYPE_REDIR,		/**< Redirect. */
+	NSS_IPSEC_CMN_CTX_TYPE_MAX
+};
+
+/**
+ * nss_ipsec_cmn_stats_types
+ *	IPsec common statistics types.
+ */
+enum nss_ipsec_cmn_stats_types {
+	NSS_IPSEC_CMN_STATS_FAIL_HEADROOM = NSS_STATS_NODE_MAX,
+						/**< Failure in headroom check. */
+	NSS_IPSEC_CMN_STATS_FAIL_TAILROOM,	/**< Failure in tailroom check. */
+	NSS_IPSEC_CMN_STATS_FAIL_REPLAY,	/**< Failure in anti-replay check. */
+	NSS_IPSEC_CMN_STATS_FAIL_REPLAY_DUP,	/**< Failure in anti-replay; duplicate records. */
+	NSS_IPSEC_CMN_STATS_FAIL_REPLAY_WIN,	/**< Failure in anti-replay; packet outside the window. */
+	NSS_IPSEC_CMN_STATS_FAIL_PBUF_CRYPTO,	/**< Failure in crypto pbuf allocation. */
+	NSS_IPSEC_CMN_STATS_FAIL_QUEUE,		/**< Failure due to queue full in IPsec. */
+	NSS_IPSEC_CMN_STATS_FAIL_QUEUE_CRYPTO,	/**< Failure due to queue full in crypto. */
+	NSS_IPSEC_CMN_STATS_FAIL_QUEUE_NEXTHOP,	/**< Failure due to queue full in next hop. */
+	NSS_IPSEC_CMN_STATS_FAIL_PBUF_ALLOC,	/**< Failure in pbuf allocation. */
+	NSS_IPSEC_CMN_STATS_FAIL_PBUF_LINEAR,	/**< Failure in pbuf linearization. */
+	NSS_IPSEC_CMN_STATS_FAIL_PBUF_STATS,	/**< Failure in pbuf allocation for statistics. */
+	NSS_IPSEC_CMN_STATS_FAIL_PBUF_ALIGN,	/**< Failure in pbuf access due to non-word alignmnt */
+	NSS_IPSEC_CMN_STATS_FAIL_CIPHER,	/**< Failure in decrypting the data. */
+	NSS_IPSEC_CMN_STATS_FAIL_AUTH,		/**< Failure in authenticating the data. */
+	NSS_IPSEC_CMN_STATS_FAIL_SEQ_OVF,	/**< Failure due to sequence number rollover. */
+	NSS_IPSEC_CMN_STATS_FAIL_BLK_LEN,	/**< Failure in decapsulation due to bad cipher block length. */
+	NSS_IPSEC_CMN_STATS_FAIL_HASH_LEN,	/**< Failure in decapsulation due to bad hash block length. */
+	NSS_IPSEC_CMN_STATS_FAIL_TRANSFORM,	/**< Failure in transformation; general error. */
+	NSS_IPSEC_CMN_STATS_FAIL_CRYPTO,	/**< Failure in crypto transformation. */
+	NSS_IPSEC_CMN_STATS_FAIL_CLE,		/**< Failure in classification; general failure. */
+	NSS_IPSEC_CMN_STATS_IS_STOPPED,		/**< Indicates if SA is stopped; for example: sequence overflow. */
+	NSS_IPSEC_CMN_STATS_MAX,		/**< Maximum statistics type. */
+};
+
+/**
+ * nss_ipsec_cmn_flow_tuple
+ *	IPsec tuple for creating flow entries.
+ *
+ * Note: This is a common selector which is used for preparing
+ * a lookup tuple for incoming packets. The tuple is used
+ * for computing the hash index in the flow table. There are multiple
+ * fields in the tuple and the recipient node decides which fields
+ * it must use from the tuple to calculate the hash index. The host
+ * has no view of the hash index and hence must compute its own index
+ * based on the tuple.
+ */
+struct nss_ipsec_cmn_flow_tuple {
+	uint32_t dest_ip[4];		/**< Destination IP. */
+	uint32_t src_ip[4];		/**< Source IP. */
+	uint32_t spi_index;		/**< ESP SPI index. */
+
+	uint16_t dst_port;		/**< Destination L4 port. */
+	uint16_t src_port;		/**< Source L4 port. */
+
+	uint8_t user_pattern;		/**< User defined field. */
+	uint8_t protocol;		/**< IP protocol types. */
+	uint8_t ip_ver;			/**< IP version. */
+};
+
+/**
+ *nss_ipsec_cmn_sa_tuple
+ *	IPsec outer header configuration.
+ */
+struct nss_ipsec_cmn_sa_tuple {
+	uint32_t dest_ip[4];		/**< Destination IP. */
+	uint32_t src_ip[4];		/**< Source IP. */
+	uint32_t spi_index;		/**< ESP SPI index. */
+
+	uint16_t dest_port;		/* Destination L4 port. */
+	uint16_t src_port;		/* Source L4 port. */
+
+	uint16_t crypto_index;		/**< Crypto index for the SA. */
+	uint8_t protocol;		/**< Outer protocol. */
+	uint8_t ip_ver;			/**< IP version. */
+
+	uint8_t hop_limit;		/**< Time-to-Live or next hop limit. */
+	uint8_t res[3];			/**< Reserved. */
+};
+
+/**
+ *nss_ipsec_cmn_sa_data
+ *	IPsec SA data used for transformation.
+ */
+struct nss_ipsec_cmn_sa_data {
+	uint32_t seq_start;		/**< Starting sequence number. */
+	uint32_t flags;			/**< Configuration flags. */
+
+	uint16_t window_size;		/**< ESP sequence number window. */
+	uint8_t dscp;			/**< Default DSCP value of the SA. */
+	uint8_t df;			/**< Default do not fragment value of the SA. */
+
+	uint8_t blk_len;		/**< Cipher block length. */
+	uint8_t iv_len;			/**< IV length. */
+	uint8_t icv_len;		/**< ESP trailers ICV length to apply. */
+	uint8_t res1;			/**< Reserved. */
+
+	uint32_t res2[4];		/**< Reserved for future use. */
+};
+
+/**
+ * nss_ipsec_cmn_flow
+ *	IPsec flow configuration message.
+ */
+struct nss_ipsec_cmn_flow {
+	struct nss_ipsec_cmn_flow_tuple flow_tuple;	/**< Flow tuple. */
+	struct nss_ipsec_cmn_sa_tuple sa_tuple;		/**< SA tuple. */
+};
+
+/**
+ * nss_ipsec_cmn_sa
+ *	IPsec SA configuration message.
+ */
+struct nss_ipsec_cmn_sa {
+	struct nss_ipsec_cmn_sa_tuple sa_tuple;		/**< SA tuple. */
+	struct nss_ipsec_cmn_sa_data sa_data;		/**< SA data. */
+};
+
+/**
+ * nss_ipsec_cmn_ctx
+ *	IPsec context configuration.
+ */
+struct nss_ipsec_cmn_ctx {
+	enum nss_ipsec_cmn_ctx_type type;	/**< Node type. */
+	uint32_t except_ifnum;			/**< Exception interface for egress. */
+	uint32_t sibling_ifnum;			/**< Sibling interface. */
+};
+
+/**
+ * nss_ipsec_cmn_node
+ *	IPsec node configuration.
+ */
+struct nss_ipsec_cmn_node {
+	bool dma_redirect;		/**< Enable redirect DMA ring. */
+	bool dma_lookaside;		/**< Enable lookaside DMA ring. */
+	uint16_t max_sa;		/**< Maximum number of SA(s) supported. */
+};
+
+/**
+ * nss_ipsec_cmn_sa_replay
+ *	IPsec replay statistics
+ */
+struct nss_ipsec_cmn_sa_replay {
+	uint64_t seq_start;		/**< Start of replay window. */
+	uint64_t seq_cur;		/**< Current sequence number. */
+	uint16_t window_size;		/**< Window size. */
+	uint8_t res[6];			/**< Reserved for future use. */
+};
+
+/**
+ * nss_ipsec_cmn_sa_stats
+ *	IPsec SA statistics.
+ */
+struct nss_ipsec_cmn_sa_stats {
+	struct nss_cmn_node_stats cmn_stats;	/**< Packet statistics. */
+	uint32_t fail_headroom;			/**< Failed headroom check. */
+	uint32_t fail_tailroom;			/**< Failed tailroom check. */
+	uint32_t fail_replay;			/**< Failure in anti-replay check. */
+	uint32_t fail_replay_dup;		/**< Failure in anti-replay; duplicate records. */
+	uint32_t fail_replay_win;		/**< Failure in anti-replay; packet outside the window. */
+	uint32_t fail_pbuf_crypto;		/**< Failed to allocate crypto pbuf. */
+	uint32_t fail_queue;			/**< Failure due to queue full in IPsec. */
+	uint32_t fail_queue_crypto;		/**< Failure due to queue full in crypto. */
+	uint32_t fail_queue_nexthop;		/**< Failure due to queue full in next hop. */
+	uint32_t fail_pbuf_alloc;		/**< Failure in pbuf allocation. */
+	uint32_t fail_pbuf_linear;		/**< Failure in pbuf linearization. */
+	uint32_t fail_pbuf_stats;		/**< Failure in pbuf allocation for statistics. */
+	uint32_t fail_pbuf_align;		/**< Failure in pbuf access due to non-word alignment. */
+	uint32_t fail_cipher;			/**< Failure in decrypting the data. */
+	uint32_t fail_auth;			/**< Failure in authenticating the data. */
+	uint32_t fail_seq_ovf;			/**< Failure due to sequence number rollover. */
+	uint32_t fail_blk_len;			/**< Failure in decapsulation due to bad cipher block length. */
+	uint32_t fail_hash_len;			/**< Failure in decapsulation due to bad hash block length. */
+	uint32_t fail_transform;		/**< Failure in transformation; general error. */
+	uint32_t fail_crypto;			/**< Failure in crypto transformation. */
+	uint32_t fail_cle;			/**< Failure in classification; general failure. */
+	uint32_t is_stopped;			/**< Indicates if SA is stopped; for example, sequence overflow. */
+};
+
+/**
+ * nss_ipsec_cmn_sa_sync
+ *	IPsec SA sync message.
+ */
+struct nss_ipsec_cmn_sa_sync {
+	struct nss_ipsec_cmn_sa_replay replay;	/**< Replay statistics. */
+	struct nss_ipsec_cmn_sa_tuple sa_tuple;	/**< SA tuple. */
+	struct nss_ipsec_cmn_sa_stats stats;	/**< Packet and failure statistics. */
+};
+
+/**
+ * nss_ipsec_cmn_ctx_stats
+ *	IPsec context statistics.
+ */
+struct nss_ipsec_cmn_ctx_stats {
+	struct nss_cmn_node_stats cmn_stats;
+					/**< Packet statistics. */
+	uint32_t exceptioned;		/**< Exceptioned to host. */
+	uint32_t linearized;		/**< Linearized packets. */
+	uint32_t redirected;		/**< Redirected from inline. */
+	uint32_t dropped;		/**< Total dropped packets. */
+	uint32_t fail_sa;		/**< Failed to find SA. */
+	uint32_t fail_flow;		/**< Failed to find flow. */
+	uint32_t fail_stats;		/**< Failed to send statistics. */
+	uint32_t fail_exception;	/**< Failed to exception. */
+	uint32_t fail_transform;	/**< Failed to produce output. */
+	uint32_t fail_linearized;	/**< Failed to linearize. */
+	uint32_t fail_mdata_ver;	/**< Invalid metadata version. */
+	uint32_t fail_ctx_active;	/**< Failed to queue as context is not active. */
+	uint32_t fail_pbuf_crypto;	/**< Failed to allocate pbuf for crypto operation. */
+	uint32_t fail_queue_crypto;	/**< Failed to queue pbuf to crypto pnode. */
+};
+
+/**
+ * nss_ipsec_cmn_ctx_sync
+ *	IPsec context synchronous message.
+ */
+struct nss_ipsec_cmn_ctx_sync {
+	enum nss_ipsec_cmn_ctx_type type;	/**< IPsec context type. */
+	struct nss_ipsec_cmn_ctx_stats stats;	/**< Context statistics. */
+};
+
+/**
+ * nss_ipsec_cmn_mdata_cmn
+ *	IPsec common metadata information.
+ */
+struct nss_ipsec_cmn_mdata_cmn {
+	uint8_t version;		/**< Metadata version. */
+	uint8_t origin;			/**< Metadata origin (host or NSS). */
+	uint16_t len;			/**< Metadata length including extra bytes. */
+	uint8_t res[2];			/**< Reserved for future. */
+	uint16_t magic;			/**< Metadata magic. */
+};
+
+/**
+ * nss_ipsec_cmn_mdata_encap
+ *	IPsec encapsulation metadata information.
+ */
+struct nss_ipsec_cmn_mdata_encap {
+	struct nss_ipsec_cmn_sa_tuple sa;	/**< SA tuple. */
+	uint32_t seq_num;			/**< Sequence number for encapsulation (zero disables it). */
+	uint16_t data_len;			/**< Length of data to encapsulate. */
+	uint16_t flags;				/**< Encapsulation metadata flags. */
+};
+
+/**
+ * nss_ipsec_cmn_mdata_decap
+ *	IPsec decapsulation metadata information.
+ */
+struct nss_ipsec_cmn_mdata_decap {
+	struct nss_ipsec_cmn_sa_tuple sa;	/**< SA tuple. */
+};
+
+/**
+ * nss_ipsec_cmn_mdata
+ *	IPsec metadata for host originated packets.
+ */
+struct nss_ipsec_cmn_mdata {
+	struct nss_ipsec_cmn_mdata_cmn cm;		/**< Common metadata. */
+
+	union {
+		struct nss_ipsec_cmn_mdata_encap encap;	/**< Encapsulation metadata. */
+		struct nss_ipsec_cmn_mdata_decap decap;	/**< Decapsulation metadata. */
+	} data;						/**< Metadata payload. */
+};
+
+/**
+ * nss_ipsec_cmn_stats_notification
+ *	IPsec common transmission statistics structure.
+ */
+struct nss_ipsec_cmn_stats_notification {
+	uint64_t stats_ctx[NSS_IPSEC_CMN_STATS_MAX];	/**< Context transmission statistics. */
+	uint32_t core_id;				/**< Core ID. */
+	uint32_t if_num;				/**< Interface number. */
+};
+
+/**
+ * nss_ipsec_cmn_msg
+ *	Message structure for NSS IPsec messages.
+ */
+struct nss_ipsec_cmn_msg {
+	struct nss_cmn_msg cm;				/**< Common message header. */
+
+	/**
+	 * Payload of IPsec interface message.
+	 */
+	union {
+		struct nss_ipsec_cmn_node node;		/**< Node configuration message. */
+		struct nss_ipsec_cmn_ctx ctx;		/**< Context configuration message. */
+		struct nss_ipsec_cmn_sa sa;		/**< SA configuration message. */
+		struct nss_ipsec_cmn_flow flow;		/**< Flow configuration message. */
+		struct nss_ipsec_cmn_sa_sync sa_sync;	/**< SA statistics message. */
+		struct nss_ipsec_cmn_ctx_sync ctx_sync; /**< Context statistics message. */
+	} msg;						/**< Message payload. */
+};
+
+/**
+ * nss_ipsec_cmn_mdata_init
+ *	Initialize the metadata common fields.
+ *
+ * @datatypes
+ * nss_ipsec_cmn_mdata
+ *
+ * @param[in] mdata Metadata pointer.
+ * @param[in] len   Metadata length including extra bytes.
+ *
+ * @return
+ * Pointer to metadata payload.
+ */
+static inline void *nss_ipsec_cmn_mdata_init(struct nss_ipsec_cmn_mdata *mdata, uint16_t len)
+{
+	mdata->cm.len = len;
+	mdata->cm.magic = NSS_IPSEC_CMN_MDATA_MAGIC;
+	mdata->cm.version = NSS_IPSEC_CMN_MDATA_VERSION;
+	mdata->cm.origin = NSS_IPSEC_CMN_MDATA_ORIGIN_HOST;
+
+	return &mdata->data;
+}
+
+/**
+ * Callback function for receiving message notifications.
+ *
+ * @datatypes
+ * nss_ipsec_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_ipsec_cmn_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * Callback function for receiving data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the message data.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_ipsec_cmn_data_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_ipsec_cmn_get_context
+ *	Gets the NSS context for the IPsec handle.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_ipsec_cmn_get_context(void);
+
+/**
+ * nss_ipsec_cmn_get_ifnum_with_coreid
+ *	Gets the IPsec interface number with a core ID.
+ *
+ * @param[in] ifnum  NSS interface number.
+ *
+ * @return
+ * Interface number with the core ID.
+ */
+extern uint32_t nss_ipsec_cmn_get_ifnum_with_coreid(int32_t ifnum);
+
+/**
+ * nss_ipsec_cmn_unregister_if
+ *	Deregisters an IPSEC tunnel interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The tunnel interface must have been previously registered.
+ *
+ * @return
+ * True if successful, else false.
+ */
+extern bool nss_ipsec_cmn_unregister_if(uint32_t if_num);
+
+/**
+ * nss_ipsec_cmn_register_if
+ *	Registers the IPsec interface with the NSS for sending and
+ *	receiving messages.
+ *
+ * @datatypes
+ * nss_ipsec_cmn_data_callback_t \n
+ * nss_ipsec_cmn_msg_callback_t \n
+ * nss_dynamic_interface_type \n
+ * net_device
+ *
+ * @param[in] if_num        NSS interface number.
+ * @param[in] netdev        Pointer to the associated network device.
+ * @param[in] cb_data       Callback for the data.
+ * @param[in] cb_msg        Callback for the message.
+ * @param[in] features      Socket buffer types supported by this interface.
+ * @param[in] type          Dynamic interface type.
+ * @param[in] app_data      Application context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_ipsec_cmn_register_if(uint32_t if_num, struct net_device *netdev,
+						nss_ipsec_cmn_data_callback_t cb_data,
+						nss_ipsec_cmn_msg_callback_t cb_msg,
+						uint32_t features, enum nss_dynamic_interface_type type, void *app_data);
+
+/**
+ * nss_ipsec_cmn_notify_unregister
+ *	Deregisters the message notifier from the HLOS driver.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in,out] ctx     Pointer to the context of the HLOS driver.
+ * @param[in]     if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The message notifier must have been previously registered.
+ */
+extern void nss_ipsec_cmn_notify_unregister(struct nss_ctx_instance *ctx, uint32_t if_num);
+
+/**
+ * nss_ipsec_cmn_notify_register
+ *	Registers an event callback to handle notifications from the IPsec firmware package.
+ *
+ * @datatypes
+ * nss_ipsec_cmn_msg_callback_t \n
+ *
+ * @param[in] ifnum     NSS interface number.
+ * @param[in] cb        Callback for IPsec message.
+ * @param[in] app_data  Pointer to the application context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_ipsec_cmn_notify_register(uint32_t ifnum, nss_ipsec_cmn_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_ipsec_cmn_msg_init
+ *	Initializes an IPsec message.
+ *
+ * @datatypes
+ * nss_ipsec_cmn_msg \n
+ * nss_ipsec_cmn_msg_type \n
+ * nss_ipsec_cmn_msg_callback_t
+ *
+ * @param[in,out] nim       Pointer to the NSS interface message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_ipsec_cmn_msg_init(struct nss_ipsec_cmn_msg *nim, uint16_t if_num, enum nss_ipsec_cmn_msg_type type,
+				uint16_t len, nss_ipsec_cmn_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_ipsec_cmn_tx_msg
+ *	Sends an asynchronous IPsec message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_ipsec_cmn_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS HLOS driver context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_ipsec_cmn_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_ipsec_cmn_msg *msg);
+
+/**
+ * nss_ipsec_cmn_tx_msg_sync
+ *	Sends a synchronous IPsec message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_ipsec_cmn_msg_type \n
+ * nss_ipsec_cmn_msg
+ *
+ * @param[in]  nss_ctx  Pointer to the NSS HLOS driver context.
+ * @param[in]  if_num   NSS interface number.
+ * @param[in]  type     Type of message.
+ * @param[in]  len      Size of the payload.
+ * @param[in]  nicm     Pointer to the NSS IPsec message.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_ipsec_cmn_tx_msg_sync(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+						enum nss_ipsec_cmn_msg_type type, uint16_t len,
+						struct nss_ipsec_cmn_msg *nicm);
+
+/**
+ * nss_ipsec_cmn_tx_buf
+ *	Sends a buffer to NSS for IPsec encapsulation or de-capsulation.
+ *
+ * @datatypes
+ * sk_buff \n
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx Pointer to the NSS HLOS driver context.
+ * @param[in] skb     Pointer to the message data.
+ * @param[in] if_num  Pointer to the NSS interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_ipsec_cmn_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *skb, uint32_t if_num);
+
+/**
+ * nss_ipsec_cmn_ppe_port_config
+ *	Configure Packet Processing Engine IPsec port.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * net_device
+ *
+ * @param[in] ctx     Pointer to the context of the HLOS driver.
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] if_num  Data interface number.
+ * @param[in] vsi_num Virtual switch instance number.
+ *
+ * @return
+ * True if successful, else false.
+ */
+extern bool nss_ipsec_cmn_ppe_port_config(struct nss_ctx_instance *ctx, struct net_device *netdev,
+					uint32_t if_num, uint32_t vsi_num);
+
+/**
+ * nss_ipsec_cmn_ppe_mtu_update()
+ *	Configure Packet Processing Engine MTU for IPsec inline.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] ctx     Pointer to the context of the HLOS driver.
+ * @param[in] if_num  Data interface number.
+ * @param[in] mtu     Maximum transmission unit of interface number.
+ * @param[in] mru     Maximum receive unit of interface number.
+ *
+ * @return
+ * True if successful, else false.
+ */
+bool nss_ipsec_cmn_ppe_mtu_update(struct nss_ctx_instance *ctx, uint32_t if_num, uint16_t mtu, uint16_t mru);
+
+/**
+ * nss_ipsec_cmn_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_ipsec_cmn_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * nss_ipsec_cmn_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_ipsec_cmn_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * @}
+ */
+
+#endif /* !__NSS_IPSEC_CMN_H */
diff --git a/qca-nss-drv/exports/nss_ipsecmgr.h b/qca-nss-drv/exports/nss_ipsecmgr.h
new file mode 100644
index 0000000..3fe3460
--- /dev/null
+++ b/qca-nss-drv/exports/nss_ipsecmgr.h
@@ -0,0 +1,443 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipsecmgr.h
+ *	NSS IPSec Manager interface definitions.
+ */
+
+#ifndef __NSS_IPSECMGR_H
+#define __NSS_IPSECMGR_H
+
+/**
+ * @addtogroup nss_ipsec_subsystem
+ * @{
+ */
+
+#define NSS_IPSECMGR_DEBUG_LVL_ERROR 1		/**< Turn on debug for an error. */
+#define NSS_IPSECMGR_DEBUG_LVL_WARN 2		/**< Turn on debug for a warning. */
+#define NSS_IPSECMGR_DEBUG_LVL_INFO 3		/**< Turn on debug for information. */
+#define NSS_IPSECMGR_DEBUG_LVL_TRACE 4		/**< Turn on debug for trace. */
+
+#define NSS_IPSECMGR_TUN_NAME "ipsectun%d"
+		/**< IPsec tunnel name. */
+#define NSS_IPSECMGR_MAX_TUNNELS (NSS_CRYPTO_MAX_IDXS/2)
+		/**< Maximum number of IPsec tunnels. */
+
+/**
+ * Length of the header added after encapsulation.
+ *
+ * This estimate must be accurate but large enough to accomodate most use cases.
+ */
+#define NSS_IPSECMGR_TUN_MAX_HDR_LEN 96
+
+/*
+ * Space required in the head and tail of the buffer
+ */
+#define NSS_IPSECMGR_TUN_HEADROOM 128		/**< Size of the buffer headroom. */
+#define NSS_IPSECMGR_TUN_TAILROOM 192		/**< Size of the buffer tailroom. */
+
+#define NSS_IPSECMGR_TUN_MTU(x) (x - NSS_IPSECMGR_TUN_MAX_HDR_LEN)
+		/**< MTU of the IPsec tunnel. */
+
+#define NSS_IPSECMGR_NATT_PORT_DATA 4500	/**< Number of the NATT port. */
+
+#define NSS_IPSECMGR_MIN_REPLAY_WIN 32		/**< Minimum size of the replay window. */
+#define NSS_IPSECMGR_MAX_REPLAY_WIN 1024	/**< Maximum size of the replay window. */
+#define NSS_IPSECMGR_MAX_ICV_LEN 32		/**< Maximum size of the ICV. */
+#define NSS_IPSECMGR_MAX_DSCP 63		/**< Maximum size of the descriptor. */
+
+/**
+ * nss_ipsecmgr_flow_type
+ *	Flow types for the IPsec manager.
+ */
+enum nss_ipsecmgr_flow_type {
+	NSS_IPSECMGR_FLOW_TYPE_NONE = 0,
+	NSS_IPSECMGR_FLOW_TYPE_V4_TUPLE = 1,
+	NSS_IPSECMGR_FLOW_TYPE_V6_TUPLE = 2,
+	NSS_IPSECMGR_FLOW_TYPE_V4_SUBNET = 3,
+	NSS_IPSECMGR_FLOW_TYPE_V6_SUBNET = 4,
+	NSS_IPSECMGR_FLOW_TYPE_MAX
+};
+
+/**
+ * nss_ipsecmgr_sa_type
+ *	Security association types for the IPsec manager.
+ */
+enum nss_ipsecmgr_sa_type {
+	NSS_IPSECMGR_SA_TYPE_NONE = 0,
+	NSS_IPSECMGR_SA_TYPE_V4 = 1,
+	NSS_IPSECMGR_SA_TYPE_V6 = 2,
+	NSS_IPSECMGR_SA_TYPE_MAX
+};
+
+/**
+ * nss_ipsecmgr_event_type
+ *	Event types for the IPsec manager.
+ */
+enum nss_ipsecmgr_event_type {
+	NSS_IPSECMGR_EVENT_NONE = 0,
+	NSS_IPSECMGR_EVENT_SA_STATS,
+	NSS_IPSECMGR_EVENT_MAX
+};
+
+/**
+ * nss_ipsecmgr_sa_v4
+ *	IPv4 security associations for the IPsec manager.
+ */
+struct nss_ipsecmgr_sa_v4 {
+	uint32_t src_ip;		/**< IPv4 source IP. */
+	uint32_t dst_ip;		/**< IPv4 destination IP. */
+	uint32_t ttl;			/**< IPv4 time-to-live. */
+	uint32_t spi_index;		/**< ESP SPI index. */
+};
+
+/**
+ * nss_ipsecmgr_sa_v6
+ *	IPv6 security associations for the IPsec manager.
+ */
+struct nss_ipsecmgr_sa_v6 {
+	uint32_t src_ip[4];	/**< IPv6 source IP. */
+	uint32_t dst_ip[4];	/**< IPv6 destination IP. */
+	uint32_t hop_limit;	/**< IPv6 hop limit. */
+	uint32_t spi_index;	/**< SPI index of the encapsulating security payload (ESP). */
+};
+
+/**
+ * nss_ipsecmgr_sa_data
+ *	Security association data for the IPsec manager.
+ *
+ * For DSCP marking, use the following settings:
+ * - Copy inner header to outer header:
+ *    - dscp_copy = 1
+ *    - dscp = 0
+ * - Fixed mark on outer header:
+ *    - dscp_copy = 0
+ *    - dscp = <0 to 63>
+ */
+struct nss_ipsecmgr_sa_data {
+	uint32_t crypto_index;	/**< Crypto session index returned by the driver. */
+
+	/**
+	 * Security association data for the IPsec manager.
+	 */
+	struct {
+		uint16_t replay_win;
+				/**< Sequence number window size for anti-replay. */
+		uint8_t icv_len;
+				/**< Hash length. */
+		uint8_t dscp;
+				/**< Default DSCP value of the security association. */
+
+		bool dscp_copy;
+				/**< Copy DSCP from the inner header to the outer header. */
+		bool nat_t_req;
+				/**< NAT-T is required. */
+		bool seq_skip;
+				/**< Skip the ESP sequence for encapsulation. */
+		bool trailer_skip;
+				/**< Skip the ESP trailer for encapsulation. */
+		bool df_copy;
+				/**< Copy DF from the inner header to the outer header. */
+		uint8_t df;
+				/**< DF value for the outer header, if nocopy is selected. */
+	} esp;		/**< Payload of security association data. */
+
+	bool enable_esn;	/**< Enable the extended sequence number. */
+	bool use_pattern;	/**< Use a random pattern in a hash calculation. */
+	uint32_t fail_hash_thresh;	/**< Threshold for consecutive hash failure. */
+};
+
+/**
+ * nss_ipsecmgr_encap_v4_tuple
+ *	IPv4 encapsulation flow tuple for the IPsec manager.
+ */
+struct nss_ipsecmgr_encap_v4_tuple {
+	uint32_t src_ip;		/**< Source IP. */
+	uint32_t dst_ip;		/**< Destination IP. */
+	uint32_t protocol;		/**< Protocol. */
+};
+
+/**
+ * nss_ipsecmgr_encap_v6_tuple
+ *	IPv6 encapsulation flow tuple for the IPsec manager.
+ */
+struct nss_ipsecmgr_encap_v6_tuple {
+	uint32_t src_ip[4];		/**< Source IP. */
+	uint32_t dst_ip[4];		/**< Destination IP. */
+	uint32_t next_hdr;		/**< Transport layer protocol. */
+};
+
+/**
+ * nss_ipsecmgr_encap_v4_subnet
+ *	IPv4 encapsulation flow subnet for the IPsec manager.
+ */
+struct nss_ipsecmgr_encap_v4_subnet {
+	uint32_t dst_subnet;		/**< Destination subnet. */
+	uint32_t dst_mask;		/**< Destination subnet mask. */
+	uint32_t protocol;		/**< IPv4 or IPv6 protocol. */
+};
+
+/**
+ * nss_ipsecmgr_encap_v6_subnet
+ *	IPv6 encapsulation flow subnet for the IPsec manager.
+ *
+ * Store least significant word in dst_subnet[0] and the most significant word
+ * in dst_subnet[3].
+ */
+struct nss_ipsecmgr_encap_v6_subnet {
+	uint32_t dst_subnet[4];		/**< Destination subnet. */
+	uint32_t dst_mask[4];		/**< Destination subnet mask. */
+	uint32_t next_hdr;		/**< Transport layer protocol. */
+};
+
+/**
+ * nss_ipsecmgr_sa
+ *	Security association information for the IPsec manager.
+ */
+struct nss_ipsecmgr_sa {
+	enum nss_ipsecmgr_sa_type type;		/**< Security association type. */
+
+	/**
+	 * IPsec manager security association data.
+	 */
+	union {
+		struct nss_ipsecmgr_sa_v4 v4;	/**< IPv4 security association. */
+		struct nss_ipsecmgr_sa_v6 v6;	/**< IPv6 security association. */
+	} data;		/**< IPsec manager security association data. */
+};
+
+/**
+ * nss_ipsecmgr_sa_stats
+ *	Security association statistics exported by the IPsec manager.
+ */
+struct nss_ipsecmgr_sa_stats {
+	struct nss_ipsecmgr_sa sa;	/**< Security association information. */
+	uint32_t crypto_index;		/**< Crypto session index. */
+
+	/**
+	 * Security association statistics used by the IPsec manager.
+	 */
+	struct {
+		uint32_t bytes;		/**< Number of bytes processed. */
+		uint32_t count;		/**< Number of packets processed. */
+	} pkts;		/**< Processing statistics. */
+
+	uint64_t seq_num;		/**< Current sequence number. */
+	uint64_t window_max;		/**< Maximum size of the window. */
+	uint32_t window_size;		/**< Current size of the window. */
+
+	bool fail_hash_alarm;
+			/**< Alarm for consecutive hash fail. */
+	bool esn_enabled;
+			/**< Specifies whether ESN is enabled. */
+};
+
+/**
+ * nss_ipsecmgr_event
+ *	Event information for the IPsec manager.
+ */
+struct nss_ipsecmgr_event {
+	enum nss_ipsecmgr_event_type type;	/**< Event type. */
+
+	/**
+	 * Event information statistics for the IPsec manager.
+	 */
+	union {
+		struct nss_ipsecmgr_sa_stats stats;
+				/**< Security association statistics. */
+	} data;			/**< Event information. */
+};
+
+/**
+ * nss_ipsecmgr_encap_flow
+ *	Encapsulation flow information for the IPsec manager.
+ */
+struct nss_ipsecmgr_encap_flow {
+	enum nss_ipsecmgr_flow_type type;	/**< Flow type. */
+
+	/**
+	 * Payload of encapsulation flow data for the IPsec manager.
+	 */
+	union {
+		struct nss_ipsecmgr_encap_v4_tuple v4_tuple;
+				/**< IPv4 tuple. */
+		struct nss_ipsecmgr_encap_v4_subnet v4_subnet;
+				/**< IPv4 subnet. */
+		struct nss_ipsecmgr_encap_v6_tuple v6_tuple;
+				/**< IPv6 tuple. */
+		struct nss_ipsecmgr_encap_v6_subnet v6_subnet;
+				/**< IPv6 subnet. */
+	} data;		/**< Encapsulation flow information. */
+};
+
+#ifdef __KERNEL__ /* only kernel will use. */
+
+/**
+ * Callback function for receiving IPsec data.
+ *
+ * @datatypes
+ * sk_buff
+ *
+ * @param[in] ctx  Pointer to the context of the data.
+ * @param[in] skb  Pointer to the data socket buffer.
+ */
+typedef void (*nss_ipsecmgr_data_cb_t) (void *ctx, struct sk_buff *skb);
+
+/**
+ * Callback function for receiving IPsec events.
+ *
+ * @datatypes
+ * nss_ipsecmgr_event
+ *
+ * @param[in] ctx  Pointer to the context of the event.
+ * @param[in] ev   Pointer to the event.
+ */
+typedef void (*nss_ipsecmgr_event_cb_t) (void *ctx, struct nss_ipsecmgr_event *ev);
+
+/**
+ * nss_ipsecmgr_callback
+ *	Callback information.
+ */
+struct nss_ipsecmgr_callback {
+	void *ctx;				/**< Context of the caller. */
+	nss_ipsecmgr_data_cb_t data_fn;		/**< Data callback function. */
+	nss_ipsecmgr_event_cb_t event_fn;	/**< Event callback function. */
+};
+
+/**
+ * nss_ipsecmgr_tunnel_add
+ *	Adds a new IPsec tunnel.
+ *
+ * @datatypes
+ * nss_ipsecmgr_callback
+ *
+ * @param[in] cb  Pointer to the message callback.
+ *
+ * @return
+ * Linux NETDEVICE or NULL.
+ */
+struct net_device *nss_ipsecmgr_tunnel_add(struct nss_ipsecmgr_callback *cb);
+
+/**
+ * nss_ipsecmgr_tunnel_del
+ *	Deletes an existing IPsec tunnel.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] tun  Pointer to the network device associated with the tunnel.
+ *
+ * @return
+ * Success or failure.
+ */
+bool nss_ipsecmgr_tunnel_del(struct net_device *tun);
+
+/**
+ * nss_ipsecmgr_tunnel_update_callback
+ *	Updates the binding of netdevice and callback.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] tun  Pointer to IPsec tunnel.
+ * @param[in] cur  Pointer to Linux netdevice.
+ *
+ * @return
+ * None.
+ */
+void nss_ipsecmgr_tunnel_update_callback(struct net_device *tun, struct net_device *cur);
+
+/**
+ * nss_ipsecmgr_encap_add
+ *	Adds an encapsulation flow rule to the IPsec offload database.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_ipsecmgr_encap_flow \n
+ * nss_ipsecmgr_sa \n
+ * nss_ipsecmgr_sa_data
+ *
+ * @param[in] tun   Pointer to the network device associated with the tunnel.
+ * @param[in] flow  Pointer to the flow or subnet to add.
+ * @param[in] sa    Pointer to the security association for the flow.
+ * @param[in] data  Pointer to additional security association data.
+ *
+ * @return
+ * Success or failure.
+ */
+bool nss_ipsecmgr_encap_add(struct net_device *tun, struct nss_ipsecmgr_encap_flow *flow, struct nss_ipsecmgr_sa *sa,
+				struct nss_ipsecmgr_sa_data *data);
+
+/**
+ * nss_ipsecmgr_encap_del
+ *	Deletes an encapsulation flow rule from the IPsec offload database.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_ipsecmgr_encap_flow \n
+ * nss_ipsecmgr_sa
+ *
+ * @param[in] tun   Pointer to the network device associated with the tunnel.
+ * @param[in] flow  Pointer to the flow or subnet to delete.
+ * @param[in] sa    Pointer to the security association for the flow.
+ *
+ * @return
+ * Success or failure.
+ */
+bool nss_ipsecmgr_encap_del(struct net_device *tun, struct nss_ipsecmgr_encap_flow *flow, struct nss_ipsecmgr_sa *sa);
+
+/**
+ * nss_ipsecmgr_decap_add
+ *	Adds a decapsulation security association to the offload database.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_ipsecmgr_sa \n
+ * nss_ipsenss_ipsecmgr_sa_datacmgr_sa
+ *
+ * @param[in] tun   Pointer to the network device associated with the tunnel.
+ * @param[in] sa    Pointer to the security association for the decapsulation.
+ * @param[in] data  Pointer to additional security association data.
+ *
+ * @return
+ * Success or failure.
+ */
+bool nss_ipsecmgr_decap_add(struct net_device *tun, struct nss_ipsecmgr_sa *sa, struct nss_ipsecmgr_sa_data *data);
+
+/**
+ * nss_ipsecmgr_sa_flush
+ *	Flushes the security association and all associated flows and subnets.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_ipsecmgr_sa
+ *
+ * @param[in] tun  Pointer to the network device associated with the tunnel.
+ * @param[in] sa   Pointer to the security association to flush.
+ *
+ * @return
+ * Success or failure.
+ */
+bool nss_ipsecmgr_sa_flush(struct net_device *tun, struct nss_ipsecmgr_sa *sa);
+
+#endif /* __KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_IPSECMGR_H */
diff --git a/qca-nss-drv/exports/nss_ipv4.h b/qca-nss-drv/exports/nss_ipv4.h
new file mode 100644
index 0000000..44fb34c
--- /dev/null
+++ b/qca-nss-drv/exports/nss_ipv4.h
@@ -0,0 +1,1311 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipv4.h
+ *	NSS IPv4 interface definitions.
+ */
+
+#ifndef __NSS_IPV4_H
+#define __NSS_IPV4_H
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+#include "nss_stats_public.h"
+#endif
+
+/**
+ * @addtogroup nss_ipv4_subsystem
+ * @{
+ */
+
+/*
+ * IPv4 connection flags (to be used with nss_ipv4_create::flags).
+ */
+#define NSS_IPV4_CREATE_FLAG_NO_SEQ_CHECK 0x01
+		/**< Rule for not checking sequence numbers. */
+#define NSS_IPV4_CREATE_FLAG_BRIDGE_FLOW 0x02
+		/**< Rule that indicates pure bridge flow (no routing is involved). */
+#define NSS_IPV4_CREATE_FLAG_ROUTED 0x04	/**< Rule for a routed connection. */
+
+#define NSS_IPV4_CREATE_FLAG_DSCP_MARKING 0x08	/**< Rule for DSCP marking. */
+#define NSS_IPV4_CREATE_FLAG_VLAN_MARKING 0x10	/**< Rule for VLAN marking. */
+#define NSS_IPV4_CREATE_FLAG_QOS_VALID 0x20	/**< Rule for QoS is valid. */
+
+/**
+ * nss_ipv4_create
+ *	Information for an IPv4 flow or connection create rule.
+ *
+ * All fields must be passed in host-endian order.
+ */
+struct nss_ipv4_create {
+	int32_t src_interface_num;
+				/**< Source interface number (virtual or physical). */
+	int32_t dest_interface_num;
+				/**< Destination interface number (virtual or physical). */
+	int32_t protocol;	/**< L4 protocol, e.g., TCP or UDP. */
+	uint32_t flags;		/**< Flags associated with this rule. */
+	uint32_t from_mtu;	/**< MTU of the incoming interface. */
+	uint32_t to_mtu;	/**< MTU of the outgoing interface. */
+	uint32_t src_ip;	/**< Source IP address. */
+	int32_t src_port;	/**< Source L4 port, e.g., TCP or UDP port. */
+	uint32_t src_ip_xlate;	/**< Translated source IP address (used with SNAT). */
+	int32_t src_port_xlate;	/**< Translated source L4 port (used with SNAT). */
+	uint32_t dest_ip;	/**< Destination IP address. */
+	int32_t dest_port;	/**< Destination L4 port, e.g., TCP or UDP port. */
+	uint32_t dest_ip_xlate;
+			/**< Translated destination IP address (used with DNAT). */
+	int32_t dest_port_xlate;
+			/**< Translated destination L4 port (used with DNAT). */
+	uint8_t src_mac[ETH_ALEN];
+			/**< Source MAC address. */
+	uint8_t dest_mac[ETH_ALEN];
+			/**< Destination MAC address. */
+	uint8_t src_mac_xlate[ETH_ALEN];
+			/**< Translated source MAC address (post-routing). */
+	uint8_t dest_mac_xlate[ETH_ALEN];
+			/**< Translated destination MAC address (post-routing). */
+	uint8_t flow_window_scale;	/**< Window scaling factor (TCP). */
+	uint32_t flow_max_window;	/**< Maximum window size (TCP). */
+	uint32_t flow_end;		/**< TCP window end. */
+	uint32_t flow_max_end;		/**< TCP window maximum end. */
+	uint32_t flow_pppoe_if_exist;
+			/**< Flow direction: PPPoE interface existence flag. */
+	int32_t flow_pppoe_if_num;
+			/**< Flow direction: PPPoE interface number. */
+	uint16_t ingress_vlan_tag;	/**< Ingress VLAN tag expected for this flow. */
+	uint8_t return_window_scale;
+			/**< Window scaling factor of the return direction (TCP). */
+	uint32_t return_max_window;
+			/**< Maximum window size of the return direction. */
+	uint32_t return_end;
+			/**< Flow end for the return direction. */
+	uint32_t return_max_end;
+			/**< Flow maximum end for the return direction. */
+	uint32_t return_pppoe_if_exist;
+			/**< Return direction: PPPoE interface existence flag. */
+	int32_t return_pppoe_if_num;
+			/**< Return direction: PPPoE interface number. */
+	uint16_t egress_vlan_tag;	/**< Egress VLAN tag expected for this flow. */
+	uint8_t spo_needed;		/**< Indicates whether SPO is required. */
+	uint32_t param_a0;		/**< Custom parameter 0. */
+	uint32_t param_a1;		/**< Custom parameter 1. */
+	uint32_t param_a2;		/**< Custom parameter 2. */
+	uint32_t param_a3;		/**< Custom parameter 3. */
+	uint32_t param_a4;		/**< Custom parameter 4. */
+	uint32_t qos_tag;		/**< Deprecated, will be removed soon. */
+	uint32_t flow_qos_tag;		/**< QoS tag value for the flow direction. */
+	uint32_t return_qos_tag;	/**< QoS tag value for the return direction. */
+	uint8_t dscp_itag;		/**< DSCP marking tag. */
+	uint8_t dscp_imask;		/**< DSCP marking input mask. */
+	uint8_t dscp_omask;		/**< DSCP marking output mask. */
+	uint8_t dscp_oval;		/**< DSCP marking output value. */
+	uint16_t vlan_itag;		/**< VLAN marking tag. */
+	uint16_t vlan_imask;		/**< VLAN marking input mask. */
+	uint16_t vlan_omask;		/**< VLAN marking output mask. */
+	uint16_t vlan_oval;		/**< VLAN marking output value. */
+	uint32_t in_vlan_tag[MAX_VLAN_DEPTH];
+			/**< Ingress VLAN tag expected for this flow. */
+	uint32_t out_vlan_tag[MAX_VLAN_DEPTH];
+			/**< Egress VLAN tag expected for this flow. */
+	uint8_t flow_dscp;		/**< IP DSCP value for the flow direction. */
+	uint8_t return_dscp;		/**< IP DSCP value for the return direction. */
+};
+
+/**
+ * nss_ipv4_destroy
+ *	Information for an IPv4 flow or connection destroy rule.
+ */
+struct nss_ipv4_destroy {
+	int32_t protocol;	/**< L4 protocol ID. */
+	uint32_t src_ip;	/**< Source IP address. */
+	int32_t src_port;	/**< Source L4 port, e.g., TCP or UDP port. */
+	uint32_t dest_ip;	/**< Destination IP address. */
+	int32_t dest_port;	/**< Destination L4 port, e.g., TCP or UDP port. */
+};
+
+/**
+ * nss_ipv4_message_types
+ *	IPv4 bridge and routing rule message types.
+ *
+ * NSS_IPV4_RX_DEPRECATED0 is a deprecated type. It is kept for backward compatibility.
+ */
+enum nss_ipv4_message_types {
+	NSS_IPV4_TX_CREATE_RULE_MSG,
+	NSS_IPV4_TX_DESTROY_RULE_MSG,
+	NSS_IPV4_RX_DEPRECATED0,
+	NSS_IPV4_RX_CONN_STATS_SYNC_MSG,
+	NSS_IPV4_RX_NODE_STATS_SYNC_MSG,
+	NSS_IPV4_TX_CONN_CFG_RULE_MSG,
+	NSS_IPV4_TX_CREATE_MC_RULE_MSG,
+	NSS_IPV4_TX_CONN_STATS_SYNC_MANY_MSG,
+	NSS_IPV4_TX_ACCEL_MODE_CFG_MSG,
+	NSS_IPV4_TX_CONN_CFG_INQUIRY_MSG,
+	NSS_IPV4_TX_CONN_TABLE_SIZE_MSG,
+	NSS_IPV4_TX_DSCP2PRI_CFG_MSG,
+	NSS_IPV4_TX_RPS_HASH_BITMAP_CFG_MSG,
+	NSS_IPV4_MAX_MSG_TYPES,
+};
+
+/**
+ * nss_ipv4_dscp_map_actions
+ *	Action types mapped to DSCP values.
+ */
+enum nss_ipv4_dscp_map_actions {
+	NSS_IPV4_DSCP_MAP_ACTION_ACCEL,
+	NSS_IPV4_DSCP_MAP_ACTION_DONT_ACCEL,
+	NSS_IPV4_DSCP_MAP_ACTION_MAX,
+};
+
+/**
+ * nss_ipv4_stats_types
+ *	IPv4 node statistics.
+ */
+enum nss_ipv4_stats_types {
+	NSS_IPV4_STATS_ACCELERATED_RX_PKTS = 0,
+		/**< Accelerated IPv4 Rx packets. */
+	NSS_IPV4_STATS_ACCELERATED_RX_BYTES,
+		/**< Accelerated IPv4 Rx bytes. */
+	NSS_IPV4_STATS_ACCELERATED_TX_PKTS,
+		/**< Accelerated IPv4 Tx packets. */
+	NSS_IPV4_STATS_ACCELERATED_TX_BYTES,
+		/**< Accelerated IPv4 Tx bytes. */
+	NSS_IPV4_STATS_CONNECTION_CREATE_REQUESTS,
+		/**< Number of IPv4 connection create requests. */
+	NSS_IPV4_STATS_CONNECTION_CREATE_COLLISIONS,
+		/**< Number of IPv4 connection create requests that collided with existing entries. */
+	NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_INTERFACE,
+		/**< Number of IPv4 connection create requests that had invalid interface. */
+	NSS_IPV4_STATS_CONNECTION_DESTROY_REQUESTS,
+		/**< Number of IPv4 connection destroy requests. */
+	NSS_IPV4_STATS_CONNECTION_DESTROY_MISSES,
+		/**< Number of IPv4 connection destroy requests that missed the cache. */
+	NSS_IPV4_STATS_CONNECTION_HASH_HITS,
+		/**< Number of IPv4 connection hash hits. */
+	NSS_IPV4_STATS_CONNECTION_HASH_REORDERS,
+		/**< Number of IPv4 connection hash reorders. */
+	NSS_IPV4_STATS_CONNECTION_FLUSHES,
+		/**< Number of IPv4 connection flushes. */
+	NSS_IPV4_STATS_CONNECTION_EVICTIONS,
+		/**< Number of IPv4 connection evictions. */
+	NSS_IPV4_STATS_FRAGMENTATIONS,
+		/**< Number of successful IPv4 fragmentations performed. */
+	NSS_IPV4_STATS_DROPPED_BY_RULE,
+		/**< Number of IPv4 packets dropped because of a drop rule.*/
+	NSS_IPV4_STATS_MC_CONNECTION_CREATE_REQUESTS,
+		/**< Number of successful IPv4 multicast create requests. */
+	NSS_IPV4_STATS_MC_CONNECTION_UPDATE_REQUESTS,
+		/**< Number of successful IPv4 multicast update requests. */
+	NSS_IPV4_STATS_MC_CONNECTION_CREATE_INVALID_INTERFACE,
+		/**< Number of IPv4 multicast connection create requests that had invalid interface. */
+	NSS_IPV4_STATS_MC_CONNECTION_DESTROY_REQUESTS,
+		/**< Number of IPv4 multicast connection destroy requests. */
+	NSS_IPV4_STATS_MC_CONNECTION_DESTROY_MISSES,
+		/**< Number of IPv4 multicast connection destroy requests that missed the cache. */
+	NSS_IPV4_STATS_MC_CONNECTION_FLUSHES,
+		/**< Number of IPv4 multicast connection flushes. */
+	NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM,
+		/**< Number of IPv4 mirror connection requests with an invalid interface number. */
+	NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE,
+		/**< Number of IPv4 mirror connection requests with an invalid interface type. */
+	NSS_IPV4_STATS_MIRROR_FAILURES,
+		/**< Number of IPv4 mirror failures. */
+	NSS_IPV4_STATS_MAX,
+		/**< Maximum message type. */
+};
+
+/*
+ * NSS IPv4 rule creation & rule update flags.
+ */
+#define NSS_IPV4_RULE_CREATE_FLAG_NO_SEQ_CHECK 0x01
+		/**< Do not perform TCP sequence number checks. */
+#define NSS_IPV4_RULE_CREATE_FLAG_BRIDGE_FLOW 0x02
+		/**< Pure bridge forwarding flow. */
+#define NSS_IPV4_RULE_CREATE_FLAG_ROUTED 0x04
+		/**< Rule for a routed connection. */
+#define NSS_IPV4_RULE_CREATE_FLAG_DSCP_MARKING 0x08
+		/**< Rule for configuring DSCP marking. */
+#define NSS_IPV4_RULE_CREATE_FLAG_VLAN_MARKING 0x10
+		/**< Rule for configuring VLAN marking. */
+#define NSS_IPV4_RULE_UPDATE_FLAG_CHANGE_MTU 0x20
+		/**< Update MTU of the connection interfaces. */
+#define NSS_IPV4_RULE_CREATE_FLAG_ICMP_NO_CME_FLUSH 0x40
+		/**< Rule for not flushing connection match entry on an ICMP packet. */
+
+/**
+ * L2 payload is not IPv4, but it consists of an encapsulating protocol that
+ * carries an IPv4 payload within it.
+ */
+#define NSS_IPV4_RULE_CREATE_FLAG_L2_ENCAP 0x80
+#define NSS_IPV4_RULE_CREATE_FLAG_DROP 0x100
+		/**< Rule to drop packets. */
+#define NSS_IPV4_RULE_CREATE_FLAG_EXCEPTION 0x200
+		/**< Rule to except packets. */
+#define NSS_IPV4_RULE_CREATE_FLAG_SRC_INTERFACE_CHECK 0x400
+		/**< Check the source interface for the rule. */
+#define NSS_IPV4_RULE_CREATE_FLAG_NO_SRC_IDENT 0x800
+		/**< Zero out the source identifier for the rule. */
+#define NSS_IPV4_RULE_CREATE_FLAG_NO_MAC 0x1000
+		/**< Flag to bypass writing MAC addresses. */
+#define NSS_IPV4_RULE_CREATE_FLAG_EMESH_SP 0x2000
+		/**< Mark rule as E-MESH Service Prioritization valid. */
+
+/*
+ * Validity flags for rule creation.
+ */
+#define NSS_IPV4_RULE_CREATE_CONN_VALID 0x01	/**< Connection is valid. */
+#define NSS_IPV4_RULE_CREATE_TCP_VALID 0x02	/**< TCP protocol fields are valid. */
+#define NSS_IPV4_RULE_CREATE_PPPOE_VALID 0x04	/**< PPPoE fields are valid. */
+#define NSS_IPV4_RULE_CREATE_QOS_VALID 0x08	/**< QoS fields are valid. */
+#define NSS_IPV4_RULE_CREATE_VLAN_VALID 0x10	/**< VLAN fields are valid. */
+#define NSS_IPV4_RULE_CREATE_DSCP_MARKING_VALID 0x20
+		/**< DSCP marking fields are valid. */
+#define NSS_IPV4_RULE_CREATE_VLAN_MARKING_VALID 0x40
+		/**< VLAN marking fields are valid. */
+#define NSS_IPV4_RULE_CREATE_SRC_MAC_VALID 0x80
+		/**< Source MAC address fields are valid. */
+#define NSS_IPV4_RULE_CREATE_NEXTHOP_VALID 0x100
+		/**< Next hop interface number fields are valid. */
+#define NSS_IPV4_RULE_CREATE_RPS_VALID 0x200
+		/**< RPS for core selection is valid. */
+#define NSS_IPV4_RULE_CREATE_DEST_MAC_VALID 0x400
+		/**< Destination MAC address fields are valid. */
+#define NSS_IPV4_RULE_CREATE_IGS_VALID 0x800
+		/**< Ingress shaping fields are valid. */
+#define NSS_IPV4_RULE_CREATE_IDENTIFIER_VALID 0x1000
+		/**< Identifier is valid. */
+#define NSS_IPV4_RULE_CREATE_MIRROR_VALID 0x2000	/**< Mirror fields are valid. */
+
+/*
+ * Multicast command rule flags
+ */
+#define NSS_IPV4_MC_RULE_CREATE_FLAG_MC_UPDATE 0x01	/**< Multicast rule update. */
+#define NSS_IPV4_MC_RULE_CREATE_FLAG_MC_EMESH_SP  0x02
+		/**< Mark multicast rule as E-MESH Service Prioritization valid. */
+
+/*
+ * Multicast command validity flags
+ */
+#define NSS_IPV4_MC_RULE_CREATE_FLAG_QOS_VALID 0x01
+		/**< QoS fields are valid. */
+#define NSS_IPV4_MC_RULE_CREATE_FLAG_DSCP_MARKING_VALID 0x02
+		/**< DSCP fields are valid. */
+#define NSS_IPV4_MC_RULE_CREATE_FLAG_INGRESS_VLAN_VALID 0x04
+		/**< Ingress VLAN fields are valid. */
+#define NSS_IPV4_MC_RULE_CREATE_FLAG_INGRESS_PPPOE 0x08
+		/**< Ingress PPPoE fields are valid. */
+#define NSS_IPV4_MC_RULE_CREATE_FLAG_IGS_VALID 0x10
+		/**< Ingress shaping fields are valid. */
+
+/*
+ * Per-interface rule flags for a multicast connection (to be used with the rule_flags
+ * field of nss_ipv4_mc_if_rule structure).
+ */
+#define NSS_IPV4_MC_RULE_CREATE_IF_FLAG_BRIDGE_FLOW 0x01
+		/**< Multicast connection rule is created for a bridge flow. */
+#define NSS_IPV4_MC_RULE_CREATE_IF_FLAG_ROUTED_FLOW 0x02
+		/**< Multicast connection rule is created for a routed flow. */
+#define NSS_IPV4_MC_RULE_CREATE_IF_FLAG_JOIN 0x04
+		/**< Interface has joined the flow. */
+#define NSS_IPV4_MC_RULE_CREATE_IF_FLAG_LEAVE 0x08
+		/**< Interface has left the flow. */
+
+/*
+ * Per-interface valid flags for a multicast connection (to be used with the valid_flags
+ * field of nss_ipv4_mc_if_rule structure).
+ */
+#define NSS_IPV4_MC_RULE_CREATE_IF_FLAG_VLAN_VALID 0x01
+		/**< VLAN fields are valid. */
+#define NSS_IPV4_MC_RULE_CREATE_IF_FLAG_PPPOE_VALID 0x02
+		/**< PPPoE fields are valid. */
+#define NSS_IPV4_MC_RULE_CREATE_IF_FLAG_NAT_VALID 0x4
+		/**< Interface is configured with the source NAT. */
+
+/*
+ * Source MAC address valid flags (to be used with mac_valid_flags field of nss_ipv4_src_mac_rule structure)
+ */
+#define NSS_IPV4_SRC_MAC_FLOW_VALID 0x01
+		/**< MAC address for the flow interface is valid. */
+#define NSS_IPV4_SRC_MAC_RETURN_VALID 0x02
+		/**< MAC address for the return interface is valid. */
+
+/*
+ * Identifier valid flags (to be used with identifier_valid_flags field of nss_ipv4_identifier_rule structure)
+ */
+#define NSS_IPV4_FLOW_IDENTIFIER_VALID 0x01
+		/**< Identifier for flow direction is valid. */
+#define NSS_IPV4_RETURN_IDENTIFIER_VALID 0x02
+		/**< Identifier for return direction is valid. */
+
+/*
+ * Mirror valid flags (to be used with the valid field of nss_ipv4_mirror_rule structure)
+ */
+#define NSS_IPV4_MIRROR_FLOW_VALID 0x01
+		/**< Mirror interface number for the flow direction is valid. */
+#define NSS_IPV4_MIRROR_RETURN_VALID 0x02
+		/**< Mirror interface number for the return direction is valid. */
+
+
+/**
+ * nss_ipv4_5tuple
+ *	Common 5-tuple information.
+ */
+struct nss_ipv4_5tuple {
+	uint32_t flow_ip;		/**< Flow IP address. */
+	uint32_t flow_ident;		/**< Flow identifier (e.g., TCP or UDP port). */
+	uint32_t return_ip;		/**< Return IP address. */
+	uint32_t return_ident;		/**< Return identier (e.g., TCP or UDP port). */
+	uint8_t protocol;		/**< Protocol number. */
+	uint8_t reserved[3];		/**< Padded for alignment. */
+};
+
+/**
+ * nss_ipv4_connection_rule
+ *	Information for creating a connection.
+ */
+struct nss_ipv4_connection_rule {
+	uint16_t flow_mac[3];		/**< Flow MAC address. */
+	uint16_t return_mac[3];		/**< Return MAC address. */
+	int32_t flow_interface_num;	/**< Flow interface number. */
+	int32_t return_interface_num;	/**< Return interface number. */
+	uint32_t flow_mtu;		/**< MTU for the flow interface. */
+	uint32_t return_mtu;		/**< MTU for the return interface. */
+	uint32_t flow_ip_xlate;		/**< Translated flow IP address. */
+	uint32_t return_ip_xlate;	/**< Translated return IP address. */
+	uint32_t flow_ident_xlate;	/**< Translated flow identifier (e.g., port). */
+	uint32_t return_ident_xlate;	/**< Translated return identifier (e.g., port). */
+};
+
+/**
+ * nss_ipv4_pppoe_rule
+ *	Information for PPPoE connection rules.
+ */
+struct nss_ipv4_pppoe_rule {
+	uint32_t flow_if_exist;
+			/**< PPPoE interface existence flag for the flow direction. */
+	int32_t flow_if_num;
+			/**< PPPoE interface number for the flow direction. */
+	uint32_t return_if_exist;
+			/**< PPPoE interface existence flag for the return direction. */
+	int32_t return_if_num;
+			/**< PPPoE interface number for the return direction. */
+};
+
+/**
+ * nss_ipv4_dscp_rule
+ *	Information for DSCP connection rules.
+ */
+struct nss_ipv4_dscp_rule {
+	uint8_t flow_dscp;	/**< Egress DSCP value for the flow direction. */
+	uint8_t return_dscp;	/**< Egress DSCP value for the return direction. */
+	uint8_t reserved[2];	/**< Padded for alignment. */
+};
+
+/**
+ * nss_ipv4_vlan_rule
+ *	Information for VLAN connection rules.
+ */
+struct nss_ipv4_vlan_rule {
+	uint32_t ingress_vlan_tag;	/**< VLAN tag for the ingress packets. */
+	uint32_t egress_vlan_tag;	/**< VLAN tag for egress packets. */
+};
+
+/**
+ * nss_ipv4_nexthop
+ *	Information for next hop interface numbers.
+ *
+ * A next hop is the next interface that will receive the packet (as opposed to
+ * the final interface when the packet leaves the device.
+ */
+struct nss_ipv4_nexthop {
+	/**
+	 * Next hop interface number of the flow direction (from which the connection
+	 * originated).
+	 */
+	int32_t flow_nexthop;
+	/**
+	 * Next hop interface number of the return direction (to which the connection
+	 * is destined).
+	 */
+	int32_t return_nexthop;
+};
+
+/**
+ * nss_ipv4_protocol_tcp_rule
+ *	Information for TCP connection rules.
+ */
+struct nss_ipv4_protocol_tcp_rule {
+	uint32_t flow_max_window;
+			/**< Largest seen window for the flow direction. */
+	uint32_t return_max_window;
+			/**< Largest seen window for the return direction. */
+
+	/**
+	 * Largest seen sequence + segment length for the flow direction.
+	 */
+	uint32_t flow_end;
+
+	/**
+	 * Largest seen sequence + segment length for the return direction.
+	 */
+	uint32_t return_end;
+
+	uint32_t flow_max_end;
+			/**< Largest seen ack + max(1, win) for the flow direction. */
+	uint32_t return_max_end;
+			/**< Largest seen ack + max(1, win) for the return direction. */
+	uint8_t flow_window_scale;
+			/**< Window scaling factor for the flow direction. */
+	uint8_t return_window_scale;
+			/**< Window scaling factor for the return direction. */
+	uint16_t reserved;		/**< Alignment padding. */
+};
+
+/**
+ * nss_ipv4_igs_rule
+ *	Information for ingress shaping connection rules.
+ */
+struct nss_ipv4_igs_rule {
+	uint16_t igs_flow_qos_tag;
+			/**< Ingress shaping QoS tag associated with this rule for the flow direction. */
+	uint16_t igs_return_qos_tag;
+			/**< Ingress shaping QoS tag associated with this rule for the return direction. */
+};
+
+/**
+ * nss_ipv4_qos_rule
+ *	Information for QoS connection rules.
+ */
+struct nss_ipv4_qos_rule {
+	uint32_t flow_qos_tag;
+			/**< QoS tag associated with this rule for the flow direction. */
+	uint32_t return_qos_tag;
+			/**< QoS tag associated with this rule for the return direction. */
+};
+
+/**
+ * nss_ipv4_src_mac_rule
+ *	Information for source MAC address rules.
+ */
+struct nss_ipv4_src_mac_rule {
+	uint32_t mac_valid_flags;	/**< MAC address validity flags. */
+	uint16_t flow_src_mac[3];	/**< Source MAC address for the flow direction. */
+	uint16_t return_src_mac[3];	/**< Source MAC address for the return direction. */
+};
+
+/**
+ * nss_ipv4_rps_rule
+ *	RPS rule structure.
+ */
+struct nss_ipv4_rps_rule {
+	uint8_t flow_rps;
+		/**< RPS for core selection for flow direction. */
+	uint8_t return_rps;
+		/**< RPS for core selection for return direction. */
+	uint8_t reserved[2];
+		/**< Padded for alignment. */
+};
+
+/**
+ * nss_ipv4_identifier_rule
+ *	Identifier rule structure.
+ */
+struct nss_ipv4_identifier_rule {
+	uint32_t identifier_valid_flags;
+		/**< Identifier validity flags. */
+	uint32_t flow_identifier;
+		/**< Identifier for flow direction. */
+	uint32_t return_identifier;
+		/**< Identifier for return direction. */
+};
+
+/**
+ * nss_ipv4_mirror_rule
+ *	Mirror rule structure.
+ */
+struct nss_ipv4_mirror_rule {
+	uint32_t valid;			/**< Mirror validity flags. */
+	nss_if_num_t flow_ifnum;	/**< Flow mirror interface number. */
+	nss_if_num_t return_ifnum;	/**< Return mirror interface number. */
+};
+
+/**
+ * nss_ipv4_error_response_types
+ *	Error types for IPv4 messages.
+ */
+enum nss_ipv4_error_response_types {
+	NSS_IPV4_UNKNOWN_MSG_TYPE = 1,
+	NSS_IPV4_CR_INVALID_PNODE_ERROR,
+	NSS_IPV4_CR_MISSING_CONNECTION_RULE_ERROR,
+	NSS_IPV4_CR_BUFFER_ALLOC_FAIL_ERROR,
+	NSS_IPV4_DR_NO_CONNECTION_ENTRY_ERROR,
+	NSS_IPV4_CR_CONN_CFG_ALREADY_CONFIGURED_ERROR,
+	NSS_IPV4_CR_CONN_CFG_NOT_MULTIPLE_OF_QUANTA_ERROR,
+	NSS_IPV4_CR_CONN_CFG_EXCEEDS_LIMIT_ERROR,
+	NSS_IPV4_CR_CONN_CFG_MEM_ALLOC_FAIL_ERROR,
+	NSS_IPV4_CR_MULTICAST_INVALID_PROTOCOL,
+	NSS_IPV4_CR_MULTICAST_UPDATE_INVALID_FLAGS,
+	NSS_IPV4_CR_MULTICAST_UPDATE_INVALID_IF,
+	NSS_IPV4_CR_ACCEL_MODE_CONFIG_INVALID,
+	NSS_IPV4_CR_INVALID_MSG_ERROR,
+	NSS_IPV4_CR_DSCP2PRI_PRI_INVALID,
+	NSS_IPV4_CR_DSCP2PRI_CONFIG_INVALID,
+	NSS_IPV4_CR_INVALID_RPS,
+	NSS_IPV4_CR_HASH_BITMAP_INVALID,
+	NSS_IPV4_DR_HW_DECEL_FAIL_ERROR,
+	NSS_IPV4_CR_RETURN_EXIST_ERROR,
+	NSS_IPV4_CR_INVALID_IDENTIFIER,
+	NSS_IPV4_CR_EMESH_SP_CONFIG_INVALID,
+	NSS_IPV4_LAST
+};
+
+/**
+ * nss_ipv4_rule_create_msg
+ *	IPv4 rule for creating sub-messages.
+ */
+struct nss_ipv4_rule_create_msg {
+	/*
+	 * Request
+	 */
+	uint16_t valid_flags;
+			/**< Bit flags associated with the validity of parameters. */
+	uint16_t rule_flags;
+			/**< Bit flags associated with the rule. */
+	struct nss_ipv4_5tuple tuple;
+			/**< Holds values of the 5 tuple. */
+	struct nss_ipv4_connection_rule conn_rule;
+			/**< Basic connection-specific data. */
+	struct nss_ipv4_protocol_tcp_rule tcp_rule;
+			/**< TCP-related accleration parameters. */
+	struct nss_ipv4_pppoe_rule pppoe_rule;
+			/**< PPPoE-related accleration parameters. */
+	struct nss_ipv4_qos_rule qos_rule;
+			/**< QoS-related accleration parameters. */
+	struct nss_ipv4_dscp_rule dscp_rule;
+			/**< DSCP-related accleration parameters. */
+	struct nss_ipv4_vlan_rule vlan_primary_rule;
+			/**< Primary VLAN-related accleration parameters. */
+	struct nss_ipv4_vlan_rule vlan_secondary_rule;
+			/**< Secondary VLAN-related accleration parameters. */
+	struct nss_ipv4_src_mac_rule src_mac_rule;
+			/**< Source MAC address-related acceleration parameters. */
+	struct nss_ipv4_nexthop nexthop_rule;
+			/**< Parameters related to the next hop. */
+	struct nss_ipv4_rps_rule rps_rule;
+			/**< RPS parameter. */
+	struct nss_ipv4_igs_rule igs_rule;
+			/**< Ingress shaping related accleration parameters. */
+	struct nss_ipv4_identifier_rule identifier;
+			/**< Rule for adding identifier. */
+	struct nss_ipv4_mirror_rule mirror_rule;
+			/**< Mirror rule parameter. */
+};
+
+/**
+ * nss_ipv4_inquiry_msg
+ *	IPv4 connection inquiry naming structure.
+ */
+struct nss_ipv4_inquiry_msg {
+	/**
+	 * Request by its 5-tuple and get response for other items.
+	 */
+	struct nss_ipv4_rule_create_msg rr;
+};
+
+/**
+ * nss_ipv4_mc_if_rule
+ *	IPv4 multicast rule for creating per-interface information.
+ */
+struct nss_ipv4_mc_if_rule {
+	uint16_t rule_flags;		/**< Bit flags associated with the rule. */
+	uint16_t valid_flags;
+			/**< Bit flags associated with the validity of parameters. */
+	uint32_t xlate_src_ip;		/**< Translated flow IP address. */
+	uint32_t xlate_src_ident;	/**< Translated flow identifier (e.g., port). */
+	uint32_t egress_vlan_tag[MAX_VLAN_DEPTH];
+					/**< VLAN tag stack for the egress packets. */
+	int32_t pppoe_if_num;		/**< PPPoE interface number. */
+	uint32_t if_num;		/**< Interface number. */
+	uint32_t if_mtu;		/**< Interface MTU. */
+	uint16_t if_mac[3];		/**< Interface MAC address. */
+	uint8_t reserved[2];		/**< Reserved 2 bytes for alignment. */
+};
+
+/**
+ * nss_ipv4_mc_rule_create_msg
+ *	IPv4 multicast rule for creating sub-messages.
+ */
+struct nss_ipv4_mc_rule_create_msg {
+	struct nss_ipv4_5tuple tuple;		/**< Holds values of the 5 tuple. */
+
+	uint32_t rule_flags;			/**< Multicast command rule flags. */
+	uint32_t valid_flags;			/**< Multicast command validity flags. */
+	uint32_t src_interface_num;
+			/**< Source interface number (virtual or physical). */
+	uint32_t ingress_vlan_tag[MAX_VLAN_DEPTH];
+			/**< VLAN tag stack for the ingress packets. */
+	uint32_t qos_tag;			/**< QoS tag for the rule. */
+	uint16_t dest_mac[3];			/**< Destination multicast MAC address. */
+	uint16_t if_count;			/**< Number of destination interfaces. */
+	uint8_t egress_dscp;			/**< Egress DSCP value for the flow. */
+	uint8_t reserved[1];			/**< Reserved 1 byte for alignment. */
+	uint16_t igs_qos_tag;			/**< Ingress shaping QoS tag for the rule. */
+
+	struct nss_ipv4_mc_if_rule if_rule[NSS_MC_IF_MAX];
+						/**< Per-interface information. */
+};
+
+/**
+ * nss_ipv4_rule_destroy_msg
+ *	IPv4 rule for destroying sub-messages.
+ */
+struct nss_ipv4_rule_destroy_msg {
+	struct nss_ipv4_5tuple tuple;	/**< Holds values of the 5 tuple. */
+};
+
+/**
+ * nss_ipv4_rule_conn_get_table_size_msg
+ *	IPv4 rule for fetching connection tables size.
+ */
+struct nss_ipv4_rule_conn_get_table_size_msg {
+	uint32_t num_conn;		/**< Number of supported IPv4 connections. */
+	uint32_t ce_table_size;		/**< Size of the connection entry table in NSS firmware. */
+	uint32_t cme_table_size;	/**< Size of the connection match entry table in NSS firmware. */
+};
+
+/**
+ * nss_ipv4_rule_conn_cfg_msg
+ *	IPv4 rule for connection configuration sub-messages.
+ */
+struct nss_ipv4_rule_conn_cfg_msg {
+	uint32_t num_conn;		/**< Number of supported IPv4 connections. */
+	uint32_t ce_mem;		/**< Memory allocated by host for connection entries table. */
+	uint32_t cme_mem;		/**< Memory allocated by host for connection match entries table. */
+};
+
+/*
+ * IPv4 rule synchronization reasons.
+ */
+#define NSS_IPV4_RULE_SYNC_REASON_STATS 0
+		/**< Rule for synchronizing statistics. */
+#define NSS_IPV4_RULE_SYNC_REASON_FLUSH 1
+		/**< Rule for flushing a cache entry. */
+#define NSS_IPV4_RULE_SYNC_REASON_EVICT 2
+		/**< Rule for evicting a cache entry. */
+#define NSS_IPV4_RULE_SYNC_REASON_DESTROY 3
+		/**< Rule for destroying a cache entry (requested by the host OS). */
+
+/**
+ * nss_ipv4_conn_sync
+ *	IPv4 connection synchronization message.
+ */
+struct nss_ipv4_conn_sync {
+	uint32_t reserved;		/**< Reserved field for backward compatibility. */
+	uint8_t protocol;		/**< Protocol number. */
+	uint32_t flow_ip;		/**< Flow IP address. */
+	uint32_t flow_ip_xlate;		/**< Translated flow IP address. */
+	uint32_t flow_ident;		/**< Flow identifier (e.g., port). */
+	uint32_t flow_ident_xlate;	/**< Translated flow identifier (e.g., port). */
+	uint32_t flow_max_window;	/**< Largest seen window for the flow direction. */
+
+	/**
+	 * Largest seen sequence + segment length for the flow direction.
+	 */
+	uint32_t flow_end;
+
+	uint32_t flow_max_end;
+			/**< Largest seen ack + max(1, win) for the flow direction. */
+	uint32_t flow_rx_packet_count;
+			/**< Rx packet count for the flow interface. */
+	uint32_t flow_rx_byte_count;
+			/**< Rx byte count for the flow interface. */
+	uint32_t flow_tx_packet_count;
+			/**< Tx packet count for the flow interface. */
+	uint32_t flow_tx_byte_count;
+			/**< Tx byte count for the flow interface. */
+	uint32_t return_ip;		/**< Return IP address. */
+	uint32_t return_ip_xlate;	/**< Translated return IP address. */
+	uint32_t return_ident;		/**< Return identier (e.g., port). */
+	uint32_t return_ident_xlate;	/**< Translated return identifier (e.g., port). */
+	uint32_t return_max_window;
+			/**< Largest seen window for the return direction. */
+
+	/**
+	 * Largest seen sequence + segment length for the return direction.
+	 */
+	uint32_t return_end;
+
+	uint32_t return_max_end;
+			/**< Largest seen ack + max(1, win) for the return direction. */
+	uint32_t return_rx_packet_count;
+			/**< Rx packet count for the return interface. */
+	uint32_t return_rx_byte_count;
+			/**< Rx byte count for the return interface. */
+	uint32_t return_tx_packet_count;
+			/**< Tx packet count for the return interface. */
+	uint32_t return_tx_byte_count;
+			/**< Tx byte count for the return interface. */
+	uint32_t inc_ticks;	/**< Number of ticks since the last synchronization. */
+	uint32_t reason;	/**< Reason for the synchronization. */
+
+	uint8_t flags;		/**< Bit flags associated with the rule. */
+	uint32_t qos_tag;	/**< QoS tag. */
+	uint32_t cause;		/**< Flush cause associated with the rule. */
+};
+
+/**
+ * nss_ipv4_conn_sync_many_msg
+ *	Information for a multiple IPv4 connection statistics synchronization message.
+ */
+struct nss_ipv4_conn_sync_many_msg {
+	/*
+	 * Request
+	 */
+	uint16_t index;		/**< Request connection statistics from the index. */
+	uint16_t size;		/**< Buffer size of this message. */
+
+	/*
+	 * Response
+	 */
+	uint16_t next;	/**< Firmware response for the next connection to be requested. */
+	uint16_t count;	/**< Number of synchronized connections included in this message. */
+	struct nss_ipv4_conn_sync conn_sync[];	/**< Array for the statistics. */
+};
+
+/**
+ * nss_ipv4_accel_mode_cfg_msg
+ *	IPv4 acceleration mode configuration.
+ */
+struct nss_ipv4_accel_mode_cfg_msg {
+	uint32_t mode;		/**< Type of acceleration mode. */
+};
+
+/**
+ * nss_ipv4_dscp2pri_cfg_msg
+ *	IPv4 dscp2pri configuration msg.
+ */
+struct nss_ipv4_dscp2pri_cfg_msg {
+	uint8_t dscp;		/**< Value of DSCP. */
+	uint8_t priority;	/**< Corresponding priority. */
+};
+
+/**
+ * nss_ipv4_rps_hash_bitmap_cfg_msg
+ *	RPS hash mask configuration.
+ *
+ * The bitmap represents the host cores to which NSS firmware can steer
+ * packets based on packet hash. The least significant bit represents core0.
+ */
+struct nss_ipv4_rps_hash_bitmap_cfg_msg {
+	uint32_t hash_bitmap;	/**< Hash mask. */
+};
+
+/**
+ * nss_ipv4_exception_events
+ *	Exception events from the bridge or route handler.
+ */
+enum nss_ipv4_exception_events {
+	NSS_IPV4_EXCEPTION_EVENT_ICMP_HEADER_INCOMPLETE,
+	NSS_IPV4_EXCEPTION_EVENT_ICMP_UNHANDLED_TYPE,
+	NSS_IPV4_EXCEPTION_EVENT_ICMP_IPV4_HEADER_INCOMPLETE,
+	NSS_IPV4_EXCEPTION_EVENT_ICMP_IPV4_UDP_HEADER_INCOMPLETE,
+	NSS_IPV4_EXCEPTION_EVENT_ICMP_IPV4_TCP_HEADER_INCOMPLETE,
+	NSS_IPV4_EXCEPTION_EVENT_ICMP_IPV4_UNKNOWN_PROTOCOL,
+	NSS_IPV4_EXCEPTION_EVENT_ICMP_NO_ICME,
+	NSS_IPV4_EXCEPTION_EVENT_ICMP_FLUSH_TO_HOST,
+	NSS_IPV4_EXCEPTION_EVENT_TCP_HEADER_INCOMPLETE,
+	NSS_IPV4_EXCEPTION_EVENT_TCP_NO_ICME,
+	NSS_IPV4_EXCEPTION_EVENT_TCP_IP_OPTION,
+	NSS_IPV4_EXCEPTION_EVENT_TCP_IP_FRAGMENT,
+	NSS_IPV4_EXCEPTION_EVENT_TCP_SMALL_TTL,
+	NSS_IPV4_EXCEPTION_EVENT_TCP_NEEDS_FRAGMENTATION,
+	NSS_IPV4_EXCEPTION_EVENT_TCP_FLAGS,
+	NSS_IPV4_EXCEPTION_EVENT_TCP_SEQ_EXCEEDS_RIGHT_EDGE,
+	NSS_IPV4_EXCEPTION_EVENT_TCP_SMALL_DATA_OFFS,
+	NSS_IPV4_EXCEPTION_EVENT_TCP_BAD_SACK,
+	NSS_IPV4_EXCEPTION_EVENT_TCP_BIG_DATA_OFFS,
+	NSS_IPV4_EXCEPTION_EVENT_TCP_SEQ_BEFORE_LEFT_EDGE,
+	NSS_IPV4_EXCEPTION_EVENT_TCP_ACK_EXCEEDS_RIGHT_EDGE,
+	NSS_IPV4_EXCEPTION_EVENT_TCP_ACK_BEFORE_LEFT_EDGE,
+	NSS_IPV4_EXCEPTION_EVENT_UDP_HEADER_INCOMPLETE,
+	NSS_IPV4_EXCEPTION_EVENT_UDP_NO_ICME,
+	NSS_IPV4_EXCEPTION_EVENT_UDP_IP_OPTION,
+	NSS_IPV4_EXCEPTION_EVENT_UDP_IP_FRAGMENT,
+	NSS_IPV4_EXCEPTION_EVENT_UDP_SMALL_TTL,
+	NSS_IPV4_EXCEPTION_EVENT_UDP_NEEDS_FRAGMENTATION,
+	NSS_IPV4_EXCEPTION_EVENT_WRONG_TARGET_MAC,
+	NSS_IPV4_EXCEPTION_EVENT_HEADER_INCOMPLETE,
+	NSS_IPV4_EXCEPTION_EVENT_BAD_TOTAL_LENGTH,
+	NSS_IPV4_EXCEPTION_EVENT_BAD_CHECKSUM,
+	NSS_IPV4_EXCEPTION_EVENT_NON_INITIAL_FRAGMENT,
+	NSS_IPV4_EXCEPTION_EVENT_DATAGRAM_INCOMPLETE,
+	NSS_IPV4_EXCEPTION_EVENT_OPTIONS_INCOMPLETE,
+	NSS_IPV4_EXCEPTION_EVENT_UNKNOWN_PROTOCOL,
+	NSS_IPV4_EXCEPTION_EVENT_ESP_HEADER_INCOMPLETE,
+	NSS_IPV4_EXCEPTION_EVENT_ESP_NO_ICME,
+	NSS_IPV4_EXCEPTION_EVENT_ESP_IP_OPTION,
+	NSS_IPV4_EXCEPTION_EVENT_ESP_IP_FRAGMENT,
+	NSS_IPV4_EXCEPTION_EVENT_ESP_SMALL_TTL,
+	NSS_IPV4_EXCEPTION_EVENT_ESP_NEEDS_FRAGMENTATION,
+	NSS_IPV4_EXCEPTION_EVENT_IVID_MISMATCH,
+	NSS_IPV4_EXCEPTION_EVENT_IVID_MISSING,
+	NSS_IPV4_EXCEPTION_EVENT_6RD_NO_ICME,
+	NSS_IPV4_EXCEPTION_EVENT_6RD_IP_OPTION,
+	NSS_IPV4_EXCEPTION_EVENT_6RD_IP_FRAGMENT,
+	NSS_IPV4_EXCEPTION_EVENT_6RD_NEEDS_FRAGMENTATION,
+	NSS_IPV4_EXCEPTION_EVENT_DSCP_MARKING_MISMATCH,
+	NSS_IPV4_EXCEPTION_EVENT_VLAN_MARKING_MISMATCH,
+	NSS_IPV4_EXCEPTION_EVENT_INTERFACE_MISMATCH,
+	NSS_IPV4_EXCEPTION_EVENT_GRE_HEADER_INCOMPLETE,
+	NSS_IPV4_EXCEPTION_EVENT_GRE_NO_ICME,
+	NSS_IPV4_EXCEPTION_EVENT_GRE_IP_OPTION,
+	NSS_IPV4_EXCEPTION_EVENT_GRE_IP_FRAGMENT,
+	NSS_IPV4_EXCEPTION_EVENT_GRE_SMALL_TTL,
+	NSS_IPV4_EXCEPTION_EVENT_GRE_NEEDS_FRAGMENTATION,
+	NSS_IPV4_EXCEPTION_EVENT_PPTP_GRE_SESSION_MATCH_FAIL,
+	NSS_IPV4_EXCEPTION_EVENT_PPTP_GRE_INVALID_PROTO,
+	NSS_IPV4_EXCEPTION_EVENT_PPTP_GRE_NO_CME,
+	NSS_IPV4_EXCEPTION_EVENT_PPTP_GRE_IP_OPTION,
+	NSS_IPV4_EXCEPTION_EVENT_PPTP_GRE_IP_FRAGMENT,
+	NSS_IPV4_EXCEPTION_EVENT_PPTP_GRE_SMALL_TTL,
+	NSS_IPV4_EXCEPTION_EVENT_PPTP_GRE_NEEDS_FRAGMENTATION,
+	NSS_IPV4_EXCEPTION_EVENT_DESTROY,
+	NSS_IPV4_EXCEPTION_EVENT_FRAG_DF_SET,
+	NSS_IPV4_EXCEPTION_EVENT_FRAG_FAIL,
+	NSS_IPV4_EXCEPTION_EVENT_ICMP_IPV4_UDPLITE_HEADER_INCOMPLETE,
+	NSS_IPV4_EXCEPTION_EVENT_UDPLITE_HEADER_INCOMPLETE,
+	NSS_IPV4_EXCEPTION_EVENT_UDPLITE_NO_ICME,
+	NSS_IPV4_EXCEPTION_EVENT_UDPLITE_IP_OPTION,
+	NSS_IPV4_EXCEPTION_EVENT_UDPLITE_IP_FRAGMENT,
+	NSS_IPV4_EXCEPTION_EVENT_UDPLITE_SMALL_TTL,
+	NSS_IPV4_EXCEPTION_EVENT_UDPLITE_NEEDS_FRAGMENTATION,
+	NSS_IPV4_EXCEPTION_EVENT_MC_UDP_NO_ICME,
+	NSS_IPV4_EXCEPTION_EVENT_MC_MEM_ALLOC_FAILURE,
+	NSS_IPV4_EXCEPTION_EVENT_MC_UPDATE_FAILURE,
+	NSS_IPV4_EXCEPTION_EVENT_MC_PBUF_ALLOC_FAILURE,
+	NSS_IPV4_EXCEPTION_EVENT_PPPOE_BRIDGE_NO_ICME,
+	NSS_IPV4_EXCEPTION_EVENT_PPPOE_NO_SESSION,
+	NSS_IPV4_EXCEPTION_EVENT_ICMP_IPV4_GRE_HEADER_INCOMPLETE,
+	NSS_IPV4_EXCEPTION_EVENT_ICMP_IPV4_ESP_HEADER_INCOMPLETE,
+	NSS_IPV4_EXCEPTION_EVENT_EMESH_PRIO_MISMATCH,
+	NSS_IPV4_EXCEPTION_EVENT_MC_UCAST_DMAC,
+	NSS_IPV4_EXCEPTION_EVENT_MAX
+};
+
+/**
+ * nss_ipv4_node_sync
+ *	IPv4 node synchronization statistics.
+ */
+struct nss_ipv4_node_sync {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics. */
+	uint32_t ipv4_connection_create_requests;
+			/**< Number of connection create requests. */
+
+	/**
+	 * Number of connection create requests that collided with existing entries.
+	 */
+	uint32_t ipv4_connection_create_collisions;
+
+	/**
+	 * Number of connection create requests that had invalid interfaces.
+	 */
+	uint32_t ipv4_connection_create_invalid_interface;
+
+	uint32_t ipv4_connection_destroy_requests;
+			/**< Number of connection destroy requests. */
+	uint32_t ipv4_connection_destroy_misses;
+			/**< Number of connection destroy requests that missed the cache. */
+	uint32_t ipv4_connection_hash_hits;	/**< Number of connection hash hits. */
+	uint32_t ipv4_connection_hash_reorders;	/**< Number of connection hash reorders. */
+	uint32_t ipv4_connection_flushes;	/**< Number of connection flushes. */
+	uint32_t ipv4_connection_evictions;	/**< Number of connection evictions. */
+	uint32_t ipv4_fragmentations;
+			/**< Number of successful IPv4 fragmentations performed. */
+	uint32_t ipv4_dropped_by_rule;
+			/**< Number of IPv4 packets dropped because of a drop rule. */
+	uint32_t ipv4_mc_connection_create_requests;
+			/**< Number of multicast connection create requests. */
+	uint32_t ipv4_mc_connection_update_requests;
+			/**< Number of multicast connection update requests. */
+
+	/**
+	 * Number of multicast connection create requests that had invalid interfaces.
+	 */
+	uint32_t ipv4_mc_connection_create_invalid_interface;
+
+	uint32_t ipv4_mc_connection_destroy_requests;
+			/**< Number of multicast connection destroy requests. */
+
+	/**
+	 * Number of multicast connection destroy requests that missed the cache.
+	 */
+	uint32_t ipv4_mc_connection_destroy_misses;
+
+	uint32_t ipv4_mc_connection_flushes;
+			/**< Number of multicast connection flushes. */
+
+	uint32_t ipv4_connection_create_invalid_mirror_ifnum;
+			/**< Number of failed create requests with an invalid mirror interface number. */
+
+	uint32_t ipv4_connection_create_invalid_mirror_iftype;
+			/**< Number of failed create requests with an invalid mirror interface type. */
+
+	uint32_t ipv4_mirror_failures;
+			/**< Mirror packet failed. */
+
+	uint32_t exception_events[NSS_IPV4_EXCEPTION_EVENT_MAX];
+			/**< Number of exception events. */
+};
+
+/**
+ * nss_ipv4_msg
+ *	Data for sending and receiving IPv4 bridge or routing messages.
+ */
+struct nss_ipv4_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of an IPv4 bridge or routing message.
+	 */
+	union {
+		struct nss_ipv4_rule_create_msg rule_create;
+				/**< Create a rule. */
+		struct nss_ipv4_rule_destroy_msg rule_destroy;
+				/**< Destroy a rule. */
+		struct nss_ipv4_conn_sync conn_stats;
+				/**< Synchronize connection statistics. */
+		struct nss_ipv4_node_sync node_stats;
+				/**< Synchronize node statistics. */
+		struct nss_ipv4_rule_conn_get_table_size_msg size;
+				/**< Get the size for connection tables. */
+		struct nss_ipv4_rule_conn_cfg_msg rule_conn_cfg;
+				/**< Configure a rule connection. */
+		struct nss_ipv4_mc_rule_create_msg mc_rule_create;
+				/**< Create a multicast rule. */
+		struct nss_ipv4_conn_sync_many_msg conn_stats_many;
+				/**< Synchronize multiple connection statistics. */
+		struct nss_ipv4_accel_mode_cfg_msg accel_mode_cfg;
+				/**< Acceleration mode. */
+		struct nss_ipv4_inquiry_msg inquiry;
+				/**< Inquiry if a connection has created. */
+		struct nss_ipv4_dscp2pri_cfg_msg dscp2pri_cfg;
+				/**< Configure dscp2pri mapping. */
+		struct nss_ipv4_rps_hash_bitmap_cfg_msg rps_hash_bitmap;
+				/**< Configure rps_hash_bitmap. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * nss_ipv4_stats_notification
+ *	Data for sending IPv4 statistics.
+ */
+struct nss_ipv4_stats_notification {
+	uint32_t core_id;					/**< Core ID. */
+	uint64_t cmn_node_stats[NSS_STATS_NODE_MAX];		/**< Node statistics. */
+	uint64_t special_stats[NSS_IPV4_STATS_MAX];		/**< IPv4 special statistics. */
+	uint64_t exception_stats[NSS_IPV4_EXCEPTION_EVENT_MAX];	/**< IPv4 exception statistics. */
+};
+
+/**
+ * Configured IPv4 connection number to use for calculating the total number of
+ * connections.
+ */
+extern int nss_ipv4_conn_cfg;
+
+#ifdef __KERNEL__ /* only kernel will use. */
+
+/**
+ * nss_ipv4_max_conn_count
+ *	Returns the maximum number of IPv4 connections that the NSS acceleration
+ *	engine supports.
+ *
+ * @return
+ * Number of connections that can be accelerated.
+ */
+int nss_ipv4_max_conn_count(void);
+
+/**
+ * Callback function for receiving IPv4 messages.
+ *
+ * @datatypes
+ * nss_ipv4_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_ipv4_msg_callback_t)(void *app_data, struct nss_ipv4_msg *msg);
+
+/**
+ * nss_ipv4_tx
+ *	Transmits an IPv4 message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_ipv4_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_ipv4_tx(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_msg *msg);
+
+/**
+ * nss_ipv4_tx_sync
+ *	Transmits a synchronous IPv4 message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_ipv4_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_ipv4_tx_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_msg *msg);
+
+/**
+ * nss_ipv4_tx_with_size
+ *	Transmits an IPv4 message with a specified size to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_ipv4_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ * @param[in] size     Actual size of this message.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_ipv4_tx_with_size(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_msg *msg, uint32_t size);
+
+/**
+ * nss_ipv4_notify_register
+ *	Registers a notifier callback to forward the IPv4 messages received from the NSS
+ *	firmware to the registered subsystem.
+ *
+ * @datatypes
+ * nss_ipv4_msg_callback_t
+ *
+ * @param[in] cb        Callback function for the message.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_ipv4_notify_register(nss_ipv4_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_ipv4_notify_unregister
+ *	Degisters an IPv4 message notifier callback from the NSS.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The notifier callback must have been previously registered.
+ */
+extern void nss_ipv4_notify_unregister(void);
+
+/**
+ * nss_ipv4_conn_sync_many_notify_register
+ *	Registers a notifier callback with the NSS for connection synchronization
+ *	message responses.
+ *
+ * @datatypes
+ * nss_ipv4_msg_callback_t
+ *
+ * @param[in] cb  Callback function for the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_ipv4_conn_sync_many_notify_register(nss_ipv4_msg_callback_t cb);
+
+/**
+ * nss_ipv4_conn_sync_many_notify_unregister
+ *	Degisters a connection synchronization notifier callback from the NSS.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The notifier callback must have been previously registered.
+ */
+extern void nss_ipv4_conn_sync_many_notify_unregister(void);
+
+/**
+ * nss_ipv4_get_mgr
+ *	Gets the NSS context that is managing IPv4 processes.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_ipv4_get_mgr(void);
+
+/**
+ * nss_ipv4_register_handler
+ *	Registers the IPv4 message handler.
+ *
+ * @return
+ * None.
+ */
+void nss_ipv4_register_handler(void);
+
+/**
+ * nss_ipv4_register_sysctl
+ *	Registers the IPv4 system control table.
+ *
+ * @return
+ * None.
+ */
+void nss_ipv4_register_sysctl(void);
+
+/**
+ * nss_ipv4_unregister_sysctl
+ *	Deregisters the IPv4 system control table.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The system control table must have been previously registered.
+ */
+void nss_ipv4_unregister_sysctl(void);
+
+/**
+ * nss_ipv4_msg_init
+ *	Initializes IPv4 messages.
+ *
+ * @datatypes
+ * nss_ipv4_msg \n
+ * nss_ipv4_msg_callback_t
+ *
+ * @param[in,out] nim       Pointer to the NSS interface message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_ipv4_msg_init(struct nss_ipv4_msg *nim, uint16_t if_num, uint32_t type, uint32_t len,
+			nss_ipv4_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_ipv4_update_conn_count
+ *	Sets the maximum number of IPv4 connections.
+ *
+ * @param[in] ipv4_max_conn  Maximum number.
+ *
+ * @return
+ * 0 -- Success
+ */
+int nss_ipv4_update_conn_count(int ipv4_max_conn);
+
+/**
+ * nss_ipv4_free_conn_tables
+ *	Frees memory allocated for connection tables.
+ *
+ * @return
+ * None.
+ */
+extern void nss_ipv4_free_conn_tables(void);
+
+/**
+ * nss_ipv4_dscp_action_get
+ *	Gets the action value of the DSCP.
+ *
+ * @param[in]	dscp	Value of the DSCP field.
+ *
+ * @return
+ * Action value of the DSCP field.
+ */
+enum nss_ipv4_dscp_map_actions nss_ipv4_dscp_action_get(uint8_t dscp);
+
+/*
+ * Logger APIs
+ */
+
+/**
+ * nss_ipv4_log_tx_msg
+ *	Logs an IPv4 message that is sent to the NSS firmware.
+ *
+ * @datatypes
+ * nss_ipv4_msg
+ *
+ * @param[in] nim  Pointer to the NSS interface message.
+ *
+ * @return
+ * None.
+ */
+void nss_ipv4_log_tx_msg(struct nss_ipv4_msg *nim);
+
+/**
+ * nss_ipv4_log_rx_msg
+ *	Logs an IPv4 message that is received from the NSS firmware.
+ *
+ * @datatypes
+ * nss_ipv4_msg
+ *
+ * @param[in] nim  Pointer to the NSS interface message.
+ *
+ * @return
+ * None.
+ */
+void nss_ipv4_log_rx_msg(struct nss_ipv4_msg *nim);
+
+/**
+ * nss_ipv4_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_ipv4_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_ipv4_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_ipv4_stats_unregister_notifier(struct notifier_block *nb);
+
+#endif /*__KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_IPV4_H */
diff --git a/qca-nss-drv/exports/nss_ipv4_reasm.h b/qca-nss-drv/exports/nss_ipv4_reasm.h
new file mode 100644
index 0000000..f7785cf
--- /dev/null
+++ b/qca-nss-drv/exports/nss_ipv4_reasm.h
@@ -0,0 +1,89 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipv4_reasm.h
+ *	NSS IPv4 reassembly interface definitions.
+ */
+
+#ifndef __NSS_IPV4_REASM_H
+#define __NSS_IPV4_REASM_H
+
+/**
+ * @addtogroup nss_ipv4_reasm_subsystem
+ * @{
+ */
+
+/*
+ * nss_ipv4_reasm_stats_types
+ *	IPv4 reassembly node statistics.
+ */
+enum nss_ipv4_reasm_stats_types {
+        NSS_IPV4_REASM_STATS_EVICTIONS,		/**< Number of evicted fragment queues due to set memory threshold. */
+	NSS_IPV4_REASM_STATS_ALLOC_FAILS,	/**< Number of fragment queue allocation failures. */
+	NSS_IPV4_REASM_STATS_TIMEOUTS,		/**< Number of expired fragment queues. */
+	NSS_IPV4_REASM_STATS_MAX,		/**< Maximum message type. */
+};
+
+/**
+ * nss_ipv4_reasm_stats_notification
+ *	Data for sending IPv4 reassembly statistics.
+ */
+struct nss_ipv4_reasm_stats_notification {
+	uint32_t core_id;					/**< Core ID. */
+	uint64_t cmn_node_stats[NSS_STATS_NODE_MAX];		/**< Common node statistics. */
+	uint64_t ipv4_reasm_stats[NSS_IPV4_REASM_STATS_MAX];	/**< IPv4 reassembly statistics. */
+};
+
+#ifdef __KERNEL__ /* only kernel will use. */
+
+/**
+ * nss_ipv4_reasm_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_ipv4_reasm_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_ipv4_reasm_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_ipv4_reasm_stats_unregister_notifier(struct notifier_block *nb);
+
+#endif /*__KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_IPV4_REASM_H */
diff --git a/qca-nss-drv/exports/nss_ipv6.h b/qca-nss-drv/exports/nss_ipv6.h
new file mode 100644
index 0000000..0b2e2d1
--- /dev/null
+++ b/qca-nss-drv/exports/nss_ipv6.h
@@ -0,0 +1,1305 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipv6.h
+ *	NSS IPv6 interface definitions.
+ */
+
+#ifndef __NSS_IPV6_H
+#define __NSS_IPV6_H
+
+/**
+ * @addtogroup nss_ipv6_subsystem
+ * @{
+ */
+
+/**
+ * Converts the format of an IPv6 address from Linux to NSS. @hideinitializer
+ */
+#define IN6_ADDR_TO_IPV6_ADDR(ipv6, in6) \
+	{ \
+		((uint32_t *)ipv6)[0] = in6.in6_u.u6_addr32[0]; \
+		((uint32_t *)ipv6)[1] = in6.in6_u.u6_addr32[1]; \
+		((uint32_t *)ipv6)[2] = in6.in6_u.u6_addr32[2]; \
+		((uint32_t *)ipv6)[3] = in6.in6_u.u6_addr32[3]; \
+	}
+
+/**
+ * Converts the format of an IPv6 address from NSS to Linux. @hideinitializer
+ */
+#define IPV6_ADDR_TO_IN6_ADDR(in6, ipv6) \
+	{ \
+		in6.in6_u.u6_addr32[0] = ((uint32_t *)ipv6)[0]; \
+		in6.in6_u.u6_addr32[1] = ((uint32_t *)ipv6)[1]; \
+		in6.in6_u.u6_addr32[2] = ((uint32_t *)ipv6)[2]; \
+		in6.in6_u.u6_addr32[3] = ((uint32_t *)ipv6)[3]; \
+	}
+
+/**
+ * Format of an IPv6 address (16 * 8 bits).
+ */
+#define IPV6_ADDR_OCTAL_FMT "%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x"
+
+/**
+ * Prints an IPv6 address (16 * 8 bits).
+ */
+#define IPV6_ADDR_TO_OCTAL(ipv6) ((uint16_t *)ipv6)[0], ((uint16_t *)ipv6)[1], ((uint16_t *)ipv6)[2], ((uint16_t *)ipv6)[3], ((uint16_t *)ipv6)[4], ((uint16_t *)ipv6)[5], ((uint16_t *)ipv6)[6], ((uint16_t *)ipv6)[7]
+
+/*
+ * IPv6 connection flags (to be used with nss_ipv6_create::flags.
+ */
+#define NSS_IPV6_CREATE_FLAG_NO_SEQ_CHECK 0x1
+		/**< Indicates that sequence numbers are not to be checked. */
+#define NSS_IPV6_CREATE_FLAG_BRIDGE_FLOW 0x02
+		/**< Indicates that this is a pure bridge flow (no routing is involved). */
+#define NSS_IPV6_CREATE_FLAG_ROUTED 0x04	/**< Rule is for a routed connection. */
+#define NSS_IPV6_CREATE_FLAG_DSCP_MARKING 0x08	/**< Rule for DSCP marking. */
+#define NSS_IPV6_CREATE_FLAG_VLAN_MARKING 0x10	/**< Rule for VLAN marking. */
+#define NSS_IPV6_CREATE_FLAG_QOS_VALID 0x20	/**< Rule for Valid QoS. */
+
+/**
+ * nss_ipv6_create
+ *	Information for an IPv6 flow or connection create rule.
+ *
+ * All fields must be passed in host-endian order.
+ */
+struct nss_ipv6_create {
+	int32_t src_interface_num;
+			/**< Source interface number (virtual or physical). */
+	int32_t dest_interface_num;
+			/**< Destination interface number (virtual or physical). */
+	int32_t protocol;	/**< L4 protocol, e.g., TCP or UDP,. */
+	uint32_t flags;		/**< Flags associated with this rule. */
+	uint32_t from_mtu;	/**< MTU of the incoming interface. */
+	uint32_t to_mtu;	/**< MTU of the outgoing interface. */
+	uint32_t src_ip[4];	/**< Source IP address. */
+	int32_t src_port;	/**< Source L4 port, e.g., TCP or UDP port. */
+	uint32_t dest_ip[4];	/**< Destination IP address. */
+	int32_t dest_port;	/**< Destination L4 port, e.g., TCP or UDP port. */
+	uint8_t src_mac[ETH_ALEN];	/**< Source MAC address. */
+	uint8_t dest_mac[ETH_ALEN];	/**< Destination MAC address. */
+	uint8_t flow_window_scale;	/**< Window scaling factor (TCP). */
+	uint32_t flow_max_window;	/**< Maximum window size (TCP). */
+	uint32_t flow_end;		/**< TCP window end. */
+	uint32_t flow_max_end;		/**< TCP window maximum end. */
+	uint32_t flow_pppoe_if_exist;
+			/**< Flow direction: PPPoE interface existence flag. */
+	int32_t flow_pppoe_if_num;
+			/**< Flow direction: PPPoE interface number. */
+	uint16_t ingress_vlan_tag;
+			/**< Ingress VLAN tag expected for this flow. */
+	uint8_t return_window_scale;
+			/**< Window scaling factor (TCP) for the return direction. */
+	uint32_t return_max_window;
+			/**< Maximum window size (TCP) for the return direction. */
+	uint32_t return_end;
+			/**< End for the return direction. */
+	uint32_t return_max_end;
+			/**< Maximum end for the return direction. */
+	uint32_t return_pppoe_if_exist;
+			/**< Return direction: PPPoE interface existence flag. */
+	int32_t return_pppoe_if_num;
+			/**< Return direction: PPPoE interface number. */
+	uint16_t egress_vlan_tag;	/**< Egress VLAN tag expected for this flow. */
+	uint32_t qos_tag;		/**< Deprecated; will be removed soon. */
+	uint32_t flow_qos_tag;		/**< QoS tag value for flow direction. */
+	uint32_t return_qos_tag;	/**< QoS tag value for the return direction. */
+	uint8_t dscp_itag;		/**< DSCP marking tag. */
+	uint8_t dscp_imask;		/**< DSCP marking input mask. */
+	uint8_t dscp_omask;		/**< DSCP marking output mask. */
+	uint8_t dscp_oval;		/**< DSCP marking output value. */
+	uint16_t vlan_itag;		/**< VLAN marking tag. */
+	uint16_t vlan_imask;		/**< VLAN marking input mask. */
+	uint16_t vlan_omask;		/**< VLAN marking output mask. */
+	uint16_t vlan_oval;		/**< VLAN marking output value. */
+	uint32_t in_vlan_tag[MAX_VLAN_DEPTH];
+					/**< Ingress VLAN tag expected for this flow. */
+	uint32_t out_vlan_tag[MAX_VLAN_DEPTH];
+					/**< Egress VLAN tag expected for this flow. */
+	uint8_t flow_dscp;		/**< IP DSCP value for flow direction. */
+	uint8_t return_dscp;		/**< IP DSCP value for the return direction. */
+};
+
+/**
+ * nss_ipv6_destroy
+ *	Information for an IPv6 flow or connection destroy rule.
+ */
+struct nss_ipv6_destroy {
+	int32_t protocol;	/**< L4 protocol, e.g., TCP or UDP. */
+	uint32_t src_ip[4];	/**< Source IP address. */
+	int32_t src_port;	/**< Source L4 port, e.g., TCP or UDP port. */
+	uint32_t dest_ip[4];	/**< Destination IP address. */
+	int32_t dest_port;	/**< Destination L4 port, e.g., TCP or UDP port. */
+};
+
+/**
+ * nss_ipv6_stats_types
+ *	IPv6 node statistics.
+ */
+enum nss_ipv6_stats_types {
+	NSS_IPV6_STATS_ACCELERATED_RX_PKTS,
+					/**< Accelerated IPv6 Rx packets. */
+	NSS_IPV6_STATS_ACCELERATED_RX_BYTES,
+					/**< Accelerated IPv6 Rx bytes. */
+	NSS_IPV6_STATS_ACCELERATED_TX_PKTS,
+					/**< Accelerated IPv6 Tx packets. */
+	NSS_IPV6_STATS_ACCELERATED_TX_BYTES,
+					/**< Accelerated IPv6 Tx bytes. */
+	NSS_IPV6_STATS_CONNECTION_CREATE_REQUESTS,
+					/**< Number of IPv6 connection create requests. */
+	NSS_IPV6_STATS_CONNECTION_CREATE_COLLISIONS,
+					/**< Number of IPv6 connection create requests that collided with existing entries. */
+	NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_INTERFACE,
+					/**< Number of IPv6 connection create requests that had invalid interface. */
+	NSS_IPV6_STATS_CONNECTION_DESTROY_REQUESTS,
+					/**< Number of IPv6 connection destroy requests. */
+	NSS_IPV6_STATS_CONNECTION_DESTROY_MISSES,
+					/**< Number of IPv6 connection destroy requests that missed the cache. */
+	NSS_IPV6_STATS_CONNECTION_HASH_HITS,
+					/**< Number of IPv6 connection hash hits. */
+	NSS_IPV6_STATS_CONNECTION_HASH_REORDERS,
+					/**< Number of IPv6 connection hash reorders. */
+	NSS_IPV6_STATS_CONNECTION_FLUSHES,
+					/**< Number of IPv6 connection flushes. */
+	NSS_IPV6_STATS_CONNECTION_EVICTIONS,
+					/**< Number of IPv6 connection evictions. */
+	NSS_IPV6_STATS_FRAGMENTATIONS,
+					/**< Number of successful IPv6 fragmentations performed. */
+	NSS_IPV6_STATS_FRAG_FAILS,
+					/**< Number of IPv6 fragmentation fails. */
+	NSS_IPV6_STATS_DROPPED_BY_RULE,
+					/**< Number of IPv6 packets dropped by a drop rule. */
+	NSS_IPV6_STATS_MC_CONNECTION_CREATE_REQUESTS,
+					/**< Number of successful IPv6 multicast create requests. */
+	NSS_IPV6_STATS_MC_CONNECTION_UPDATE_REQUESTS,
+					/**< Number of successful IPv6 multicast update requests. */
+	NSS_IPV6_STATS_MC_CONNECTION_CREATE_INVALID_INTERFACE,
+					/**< Number of IPv6 multicast connection create requests that had invalid interface. */
+	NSS_IPV6_STATS_MC_CONNECTION_DESTROY_REQUESTS,
+					/**< Number of IPv6 multicast connection destroy requests. */
+	NSS_IPV6_STATS_MC_CONNECTION_DESTROY_MISSES,
+					/**< Number of IPv6 multicast connection destroy requests that missed the cache. */
+	NSS_IPV6_STATS_MC_CONNECTION_FLUSHES,
+					/**< Number of IPv6 multicast connection flushes. */
+	NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM,
+		/**< Number of IPv6 mirror connection requests with an invalid interface number. */
+	NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE,
+		/**< Number of IPv6 mirror connection requests with an invalid interface type. */
+
+	NSS_IPV6_STATS_MIRROR_FAILURES,
+		/**< Number of IPv6 mirror failures. */
+
+	NSS_IPV6_STATS_MAX,
+					/**< Maximum message type. */
+};
+
+/**
+ * nss_ipv6_message_types
+ *	IPv6 bridge and routing rule message types.
+ *
+ * NSS_IPV6_RX_DEPRECATED0 is a deprecated type. It is kept for backward compatibility.
+ */
+enum nss_ipv6_message_types {
+	NSS_IPV6_TX_CREATE_RULE_MSG,
+	NSS_IPV6_TX_DESTROY_RULE_MSG,
+	NSS_IPV6_RX_DEPRECATED0,
+	NSS_IPV6_RX_CONN_STATS_SYNC_MSG,
+	NSS_IPV6_RX_NODE_STATS_SYNC_MSG,
+	NSS_IPV6_TX_CONN_CFG_RULE_MSG,
+	NSS_IPV6_TX_CREATE_MC_RULE_MSG,
+	NSS_IPV6_TX_CONN_STATS_SYNC_MANY_MSG,
+	NSS_IPV6_TX_ACCEL_MODE_CFG_MSG,
+	NSS_IPV6_TX_CONN_CFG_INQUIRY_MSG,
+	NSS_IPV6_TX_CONN_TABLE_SIZE_MSG,
+	NSS_IPV6_TX_DSCP2PRI_CFG_MSG,
+	NSS_IPV6_TX_RPS_HASH_BITMAP_CFG_MSG,
+	NSS_IPV6_MAX_MSG_TYPES,
+};
+
+/**
+ * nss_ipv6_dscp_map_actions
+ *	Action types mapped to DSCP values.
+ */
+enum nss_ipv6_dscp_map_actions {
+	NSS_IPV6_DSCP_MAP_ACTION_ACCEL,
+	NSS_IPV6_DSCP_MAP_ACTION_DONT_ACCEL,
+	NSS_IPV6_DSCP_MAP_ACTION_MAX,
+};
+
+/*
+ * NSS IPv6 rule creation flags.
+ */
+#define NSS_IPV6_RULE_CREATE_FLAG_NO_SEQ_CHECK 0x01
+		/**< Do not perform TCP sequence number checks. */
+#define NSS_IPV6_RULE_CREATE_FLAG_BRIDGE_FLOW 0x02
+		/**< This is a pure bridge forwarding flow. */
+#define NSS_IPV6_RULE_CREATE_FLAG_ROUTED 0x04
+		/**< Rule is for a routed connection. */
+#define NSS_IPV6_RULE_CREATE_FLAG_DSCP_MARKING 0x08
+		/**< Rule has for a DSCP marking configured. */
+#define NSS_IPV6_RULE_CREATE_FLAG_VLAN_MARKING 0x10
+		/**< Rule has for a VLAN marking configured. */
+#define NSS_IPV6_RULE_CREATE_FLAG_ICMP_NO_CME_FLUSH 0x20
+		/**< Rule for not flushing connection match entry on ICMP packet. */
+#define NSS_IPV6_RULE_UPDATE_FLAG_CHANGE_MTU 0x40
+		/**< Rule updation for MTU change. */
+
+/** The L2 payload is not IPv6 but consists of an encapsulating protocol that carries an IPv6 payload within it.
+ */
+#define NSS_IPV6_RULE_CREATE_FLAG_L2_ENCAP 0x80
+
+#define NSS_IPV6_RULE_CREATE_FLAG_DROP 0x100
+		/**< Drop packets. */
+#define NSS_IPV6_RULE_CREATE_FLAG_EXCEPTION 0x200
+		/**< Rule to except packets. */
+#define NSS_IPV6_RULE_CREATE_FLAG_SRC_INTERFACE_CHECK 0x400
+		/**< Check the source interface for the rule. */
+#define NSS_IPV6_RULE_CREATE_FLAG_NO_SRC_IDENT 0x800
+		/**< Flag to indicate NSS to ignore src_ident and use value 0 for it during rule addition. */
+#define NSS_IPV6_RULE_CREATE_FLAG_NO_MAC 0x1000
+		/**< Flag to bypass writing MAC addresses. */
+#define NSS_IPV6_RULE_CREATE_FLAG_EMESH_SP 0x2000
+		/**< Mark rule as E-MESH Service Prioritization valid. */
+
+/*
+ * IPv6 rule creation validity flags.
+ */
+#define NSS_IPV6_RULE_CREATE_CONN_VALID 0x01	/**< Connection is valid. */
+#define NSS_IPV6_RULE_CREATE_TCP_VALID 0x02	/**< TCP protocol fields are valid. */
+#define NSS_IPV6_RULE_CREATE_PPPOE_VALID 0x04	/**< PPPoE fields are valid. */
+#define NSS_IPV6_RULE_CREATE_QOS_VALID 0x08	/**< QoS fields are valid. */
+#define NSS_IPV6_RULE_CREATE_VLAN_VALID 0x10	/**< VLAN fields are valid. */
+#define NSS_IPV6_RULE_CREATE_DSCP_MARKING_VALID 0x20
+						/**< DSCP marking fields are valid. */
+#define NSS_IPV6_RULE_CREATE_VLAN_MARKING_VALID 0x40
+						/**< VLAN marking fields are valid. */
+#define NSS_IPV6_RULE_CREATE_SRC_MAC_VALID 0x80
+						/**< Source MAC address fields are valid. */
+#define NSS_IPV6_RULE_CREATE_NEXTHOP_VALID 0x100
+						/**< Next hop interface number fields are valid. */
+#define NSS_IPV6_RULE_CREATE_RPS_VALID 0x200	/**< RPS for core selection is valid. */
+#define NSS_IPV6_RULE_CREATE_DEST_MAC_VALID 0x400
+		/**< Destination MAC address fields are valid. */
+#define NSS_IPV6_RULE_CREATE_IGS_VALID 0x800	/**< Ingress shaping fields are valid. */
+#define NSS_IPV6_RULE_CREATE_IDENTIFIER_VALID 0x1000	/**< Identifier is valid. */
+#define NSS_IPV6_RULE_CREATE_MIRROR_VALID 0x2000	/**< Mirror fields are valid. */
+
+/*
+ * Multicast command rule flags
+ */
+#define NSS_IPV6_MC_RULE_CREATE_FLAG_MC_UPDATE 0x01	/**< Multicast rule update. */
+#define NSS_IPV6_MC_RULE_CREATE_FLAG_MC_EMESH_SP  0x02
+		/**< Mark multicast rule as E-MESH Service Prioritization valid. */
+
+/*
+ * Multicast command validity flags
+ */
+#define NSS_IPV6_MC_RULE_CREATE_FLAG_QOS_VALID 0x01
+		/**< QoS fields are valid. */
+#define NSS_IPV6_MC_RULE_CREATE_FLAG_DSCP_MARKING_VALID 0x02
+		/**< DSCP fields are valid. */
+#define NSS_IPV6_MC_RULE_CREATE_FLAG_INGRESS_VLAN_VALID 0x04
+		/**< Ingress VLAN fields are valid. */
+#define NSS_IPV6_MC_RULE_CREATE_FLAG_INGRESS_PPPOE 0x08
+		/**< Ingress PPPoE fields are valid. */
+#define NSS_IPV6_MC_RULE_CREATE_FLAG_IGS_VALID 0x10
+		/**< Ingress shaping fields are valid. */
+
+/*
+ * Per-interface rule flags for a multicast connection (to be used with the rule_flags
+ * field of nss_ipv6_mc_if_rule structure).
+ */
+#define NSS_IPV6_MC_RULE_CREATE_IF_FLAG_BRIDGE_FLOW 0x01
+		/**< Bridge flow. */
+#define NSS_IPV6_MC_RULE_CREATE_IF_FLAG_ROUTED_FLOW 0x02
+		/**< Routed flow. */
+#define NSS_IPV6_MC_RULE_CREATE_IF_FLAG_JOIN 0x04
+		/**< Interface has joined the flow. */
+#define NSS_IPV6_MC_RULE_CREATE_IF_FLAG_LEAVE 0x08
+		/**< Interface has left the flow. */
+
+/*
+ * Per-interface valid flags for a multicast connection (to be used with the valid_flags
+ * field of nss_ipv6_mc_if_rule structure).
+ */
+#define NSS_IPV6_MC_RULE_CREATE_IF_FLAG_VLAN_VALID 0x01
+		/**< VLAN fields are valid. */
+#define NSS_IPV6_MC_RULE_CREATE_IF_FLAG_PPPOE_VALID 0x02
+		/**< PPPoE fields are valid. */
+
+/*
+ * Source MAC address valid flags (to be used with mac_valid_flags field of nss_ipv6_src_mac_rule structure)
+ */
+#define NSS_IPV6_SRC_MAC_FLOW_VALID 0x01
+		/**< MAC address for the flow interface is valid. */
+#define NSS_IPV6_SRC_MAC_RETURN_VALID 0x02
+		/**< MAC address for the return interface is valid. */
+
+/*
+ * Identifier valid flags (to be used with identifier_valid_flags field of nss_ipv6_identifier_rule structure)
+ */
+#define NSS_IPV6_FLOW_IDENTIFIER_VALID 0x01
+		/**< Identifier for flow direction is valid. */
+#define NSS_IPV6_RETURN_IDENTIFIER_VALID 0x02
+		/**< Identifier for return direction is valid. */
+
+/*
+ * Mirror valid flags (to be used with the valid field of nss_ipv6_mirror_rule structure)
+ */
+#define NSS_IPV6_MIRROR_FLOW_VALID 0x01
+		/**< Mirror interface number for the flow direction is valid. */
+#define NSS_IPV6_MIRROR_RETURN_VALID 0x02
+		/**< Mirror interface number for the return direction is valid. */
+
+/**
+ * nss_ipv6_exception_events
+ *	Exception events from an IPv6 bridge or route handler.
+ */
+enum nss_ipv6_exception_events {
+	NSS_IPV6_EXCEPTION_EVENT_ICMP_HEADER_INCOMPLETE,
+	NSS_IPV6_EXCEPTION_EVENT_ICMP_UNHANDLED_TYPE,
+	NSS_IPV6_EXCEPTION_EVENT_ICMP_IPV6_HEADER_INCOMPLETE,
+	NSS_IPV6_EXCEPTION_EVENT_ICMP_IPV6_UDP_HEADER_INCOMPLETE,
+	NSS_IPV6_EXCEPTION_EVENT_ICMP_IPV6_TCP_HEADER_INCOMPLETE,
+	NSS_IPV6_EXCEPTION_EVENT_ICMP_IPV6_UNKNOWN_PROTOCOL,
+	NSS_IPV6_EXCEPTION_EVENT_ICMP_NO_ICME,
+	NSS_IPV6_EXCEPTION_EVENT_ICMP_FLUSH_TO_HOST,
+	NSS_IPV6_EXCEPTION_EVENT_TCP_HEADER_INCOMPLETE,
+	NSS_IPV6_EXCEPTION_EVENT_TCP_NO_ICME,
+	NSS_IPV6_EXCEPTION_EVENT_TCP_SMALL_HOP_LIMIT,
+	NSS_IPV6_EXCEPTION_EVENT_TCP_NEEDS_FRAGMENTATION,
+	NSS_IPV6_EXCEPTION_EVENT_TCP_FLAGS,
+	NSS_IPV6_EXCEPTION_EVENT_TCP_SEQ_EXCEEDS_RIGHT_EDGE,
+	NSS_IPV6_EXCEPTION_EVENT_TCP_SMALL_DATA_OFFS,
+	NSS_IPV6_EXCEPTION_EVENT_TCP_BAD_SACK,
+	NSS_IPV6_EXCEPTION_EVENT_TCP_BIG_DATA_OFFS,
+	NSS_IPV6_EXCEPTION_EVENT_TCP_SEQ_BEFORE_LEFT_EDGE,
+	NSS_IPV6_EXCEPTION_EVENT_TCP_ACK_EXCEEDS_RIGHT_EDGE,
+	NSS_IPV6_EXCEPTION_EVENT_TCP_ACK_BEFORE_LEFT_EDGE,
+	NSS_IPV6_EXCEPTION_EVENT_UDP_HEADER_INCOMPLETE,
+	NSS_IPV6_EXCEPTION_EVENT_UDP_NO_ICME,
+	NSS_IPV6_EXCEPTION_EVENT_UDP_SMALL_HOP_LIMIT,
+	NSS_IPV6_EXCEPTION_EVENT_UDP_NEEDS_FRAGMENTATION,
+	NSS_IPV6_EXCEPTION_EVENT_WRONG_TARGET_MAC,
+	NSS_IPV6_EXCEPTION_EVENT_HEADER_INCOMPLETE,
+	NSS_IPV6_EXCEPTION_EVENT_UNKNOWN_PROTOCOL,
+	NSS_IPV6_EXCEPTION_EVENT_IVID_MISMATCH,
+	NSS_IPV6_EXCEPTION_EVENT_IVID_MISSING,
+	NSS_IPV6_EXCEPTION_EVENT_DSCP_MARKING_MISMATCH,
+	NSS_IPV6_EXCEPTION_EVENT_VLAN_MARKING_MISMATCH,
+	NSS_IPV6_EXCEPTION_EVENT_INTERFACE_MISMATCH,
+	NSS_IPV6_EXCEPTION_EVENT_GRE_NO_ICME,
+	NSS_IPV6_EXCEPTION_EVENT_GRE_NEEDS_FRAGMENTATION,
+	NSS_IPV6_EXCEPTION_EVENT_GRE_SMALL_HOP_LIMIT,
+	NSS_IPV6_EXCEPTION_EVENT_DESTROY,
+	NSS_IPV6_EXCEPTION_EVENT_ICMP_IPV6_UDPLITE_HEADER_INCOMPLETE,
+	NSS_IPV6_EXCEPTION_EVENT_UDPLITE_HEADER_INCOMPLETE,
+	NSS_IPV6_EXCEPTION_EVENT_UDPLITE_NO_ICME,
+	NSS_IPV6_EXCEPTION_EVENT_UDPLITE_SMALL_HOP_LIMIT,
+	NSS_IPV6_EXCEPTION_EVENT_UDPLITE_NEEDS_FRAGMENTATION,
+	NSS_IPV6_EXCEPTION_EVENT_MC_UDP_NO_ICME,
+	NSS_IPV6_EXCEPTION_EVENT_MC_MEM_ALLOC_FAILURE,
+	NSS_IPV6_EXCEPTION_EVENT_MC_UPDATE_FAILURE,
+	NSS_IPV6_EXCEPTION_EVENT_MC_PBUF_ALLOC_FAILURE,
+	NSS_IPV6_EXCEPTION_EVENT_ESP_HEADER_INCOMPLETE,
+	NSS_IPV6_EXCEPTION_EVENT_ESP_NO_ICME,
+	NSS_IPV6_EXCEPTION_EVENT_ESP_IP_FRAGMENT,
+	NSS_IPV6_EXCEPTION_EVENT_ESP_SMALL_HOP_LIMIT,
+	NSS_IPV6_EXCEPTION_EVENT_ESP_NEEDS_FRAGMENTATION,
+	NSS_IPV6_EXCEPTION_EVENT_TUNIPIP6_NO_ICME,
+	NSS_IPV6_EXCEPTION_EVENT_TUNIPIP6_SMALL_HOP_LIMIT,
+	NSS_IPV6_EXCEPTION_EVENT_TUNIPIP6_NEEDS_FRAGMENTATION,
+	NSS_IPV6_EXCEPTION_EVENT_PPPOE_BRIDGE_NO_ICME,
+	NSS_IPV6_EXCEPTION_EVENT_DONT_FRAG_SET,
+	NSS_IPV6_EXCEPTION_EVENT_REASSEMBLY_NOT_SUPPORTED,
+	NSS_IPV6_EXCEPTION_EVENT_PPPOE_NO_SESSION,
+	NSS_IPV6_EXCEPTION_EVENT_ICMP_IPV6_GRE_HEADER_INCOMPLETE,
+	NSS_IPV6_EXCEPTION_EVENT_ICMP_IPV6_ESP_HEADER_INCOMPLETE,
+	NSS_IPV6_EXCEPTION_EVENT_EMESH_PRIO_MISMATCH,
+	NSS_IPV6_EXCEPTION_EVENT_MC_UCAST_DMAC,
+	NSS_IPV6_EXCEPTION_EVENT_MAX
+};
+
+/**
+ * nss_ipv6_5tuple
+ *	Common 5-tuple information.
+ */
+struct nss_ipv6_5tuple {
+	uint32_t flow_ip[4];		/**< Flow IP address. */
+	uint32_t flow_ident;		/**< Flow identifier (e.g., TCP or UDP port). */
+	uint32_t return_ip[4];		/**< Return IP address. */
+	uint32_t return_ident;		/**< Return identier (e.g., TCP or UDP port). */
+	uint8_t  protocol;		/**< Protocol number. */
+	uint8_t  reserved[3];		/**< Padded for alignment. */
+};
+
+/**
+ * nss_ipv6_connection_rule
+ *	Information for creating a connection.
+ */
+struct nss_ipv6_connection_rule {
+	uint16_t flow_mac[3];		/**< Flow MAC address. */
+	uint16_t return_mac[3];		/**< Return MAC address. */
+	int32_t flow_interface_num;	/**< Flow interface number. */
+	int32_t return_interface_num;	/**< Return interface number. */
+	uint32_t flow_mtu;		/**< MTU for the flow interface. */
+	uint32_t return_mtu;		/**< MTU for the return interface. */
+};
+
+/**
+ * nss_ipv6_pppoe_rule
+ *	Information for PPPoE connection rules.
+ */
+struct nss_ipv6_pppoe_rule {
+	uint32_t flow_if_exist;
+			/**< PPPoE interface existence flag for the flow direction. */
+	int32_t flow_if_num;
+			/**< PPPoE interface number for the flow direction. */
+	uint32_t return_if_exist;
+			/**< PPPoE interface existence flag for the return direction. */
+	int32_t return_if_num;
+			/**< PPPoE interface number for the return direction. */
+};
+
+/**
+ * nss_ipv6_dscp_rule
+ *	Information for DSCP connection rules.
+ */
+struct nss_ipv6_dscp_rule {
+	uint8_t flow_dscp;	/**< Egress DSCP value for the flow direction. */
+	uint8_t return_dscp;	/**< Egress DSCP value for the return direction. */
+	uint8_t reserved[2];	/**< Padded for alignment. */
+};
+
+/**
+ * nss_ipv6_vlan_rule
+ *	Information for VLAN connection rules.
+ */
+struct nss_ipv6_vlan_rule {
+	uint32_t ingress_vlan_tag;	/**< VLAN tag for the ingress packets. */
+	uint32_t egress_vlan_tag;	/**< VLAN tag for egress packets. */
+};
+
+/**
+ * nss_ipv6_nexthop
+ *	Information for the next hop interface numbers.
+ *
+ * A next hop is the next interface that will receive the packet as opposed to
+ * the final interface when the packet leaves the device.
+ */
+struct nss_ipv6_nexthop {
+	/**
+	 * Next hop interface number of the flow direction (from which the connection
+	 * originated).
+	 */
+	int32_t flow_nexthop;
+	/**
+	 * Next hop interface number of the return direction (to which the connection
+	 * is destined).
+	 */
+	int32_t return_nexthop;
+};
+
+/**
+ * nss_ipv6_protocol_tcp_rule
+ *	Information for TCP connection rules.
+ */
+struct nss_ipv6_protocol_tcp_rule {
+	uint32_t flow_max_window;
+			/**< Largest seen window for the flow direction. */
+	uint32_t flow_end;
+			/**< Largest seen sequence + segment length for the flow direction. */
+	uint32_t flow_max_end;
+			/**< Largest seen ack + max(1, win) for the flow direction. */
+	uint32_t return_max_window;
+			/**< Largest seen window for the return direction. */
+	uint32_t return_end;
+			/**< Largest seen sequence + segment length for the return direction. */
+	uint32_t return_max_end;
+			/**< Largest seen ack + max(1, win) for the return direction. */
+	uint8_t flow_window_scale;
+			/**< Window scaling factor for the flow direction. */
+	uint8_t return_window_scale;
+			/**< Window scaling factor for the return direction. */
+	uint16_t reserved;
+			/**< Alignment padding. */
+};
+
+/**
+ * nss_ipv6_igs_rule
+ *	Information for ingress shaping connection rules.
+ */
+struct nss_ipv6_igs_rule {
+	uint16_t igs_flow_qos_tag;
+			/**< Ingress shaping QoS tag associated with this rule for the flow direction. */
+	uint16_t igs_return_qos_tag;
+			/**< Ingress shaping QoS tag associated with this rule for the return direction. */
+};
+
+/**
+ * nss_ipv6_qos_rule
+ *	Information for QoS connection rules.
+ */
+struct nss_ipv6_qos_rule {
+	uint32_t flow_qos_tag;
+			/**< QoS tag associated with this rule for the flow direction. */
+	uint32_t return_qos_tag;
+			/**< QoS tag associated with this rule for the return direction. */
+};
+
+/**
+ * nss_ipv6_src_mac_rule
+ *	Information for source MAC address rules.
+ */
+struct nss_ipv6_src_mac_rule {
+	uint32_t mac_valid_flags;	/**< MAC address validity flags. */
+	uint16_t flow_src_mac[3];	/**< Source MAC address for the flow direction. */
+	uint16_t return_src_mac[3];	/**< Source MAC address for the return direction. */
+};
+
+/**
+ * nss_ipv6_rps_rule
+ *	RPS rule structure.
+ */
+struct nss_ipv6_rps_rule {
+	uint8_t flow_rps;
+		/**< RPS for core selection for flow direction. */
+	uint8_t return_rps;
+		/**< RPS for core selection for return direction. */
+	uint8_t reserved[2];
+		/**< Padded for alignment. */
+};
+
+/**
+ * nss_ipv6_identifier_rule
+ *	Identifier rule structure.
+ */
+struct nss_ipv6_identifier_rule {
+	uint32_t identifier_valid_flags;
+		/**< Identifier validity flags. */
+	uint32_t flow_identifier;
+		/**< Identifier for flow direction. */
+	uint32_t return_identifier;
+		/**< Identifier for return direction. */
+};
+
+/**
+ * nss_ipv6_mirror_rule
+ *	Mirror rule structure.
+ */
+struct nss_ipv6_mirror_rule {
+	uint32_t valid;			/**< Mirror validity flags. */
+	nss_if_num_t flow_ifnum;	/**< Flow mirror interface number. */
+	nss_if_num_t return_ifnum;	/**< Return mirror interface number. */
+};
+
+/**
+ * nss_ipv6_error_response_types
+ *	Error types for IPv6 messages.
+ */
+enum nss_ipv6_error_response_types {
+	NSS_IPV6_UNKNOWN_MSG_TYPE = 1,			/**< Unknown error. */
+	NSS_IPV6_CR_INVALID_PNODE_ERROR,		/**< Invalid interface number. */
+	NSS_IPV6_CR_MISSING_CONNECTION_RULE_ERROR,	/**< Missing connection rule. */
+	NSS_IPV6_CR_BUFFER_ALLOC_FAIL_ERROR,		/**< Buffer allocation failed. */
+	NSS_IPV6_DR_NO_CONNECTION_ENTRY_ERROR,
+		/**< No connection was found to delete. */
+	NSS_IPV6_CR_CONN_CFG_ALREADY_CONFIGURED_ERROR,
+		/**< Connection configuration was already done once. */
+
+	NSS_IPV6_CR_CONN_CFG_NOT_MULTIPLE_OF_QUANTA_ERROR,
+	/**< Input for connection configuration is not a multiple of quanta. */
+
+	/**
+	 * Input for connection configuration exceeds the maximum number of supported
+	 * connections.
+	 */
+	NSS_IPV6_CR_CONN_CFG_EXCEEDS_LIMIT_ERROR,
+
+	/**
+	 * Memory allocation for connection configuration failed at the NSS firmware.
+	 */
+	NSS_IPV6_CR_CONN_CFG_MEM_ALLOC_FAIL_ERROR,
+
+	NSS_IPV6_CR_MULTICAST_INVALID_PROTOCOL,
+		/**< Invalid L4 protocol for creating a multicast rule. */
+	NSS_IPV6_CR_MULTICAST_UPDATE_INVALID_FLAGS,
+		/**< Invalid multicast flags for updating multicast. */
+	NSS_IPV6_CR_MULTICAST_UPDATE_INVALID_IF,
+		/**< Invalid interface for updating multicast. */
+	NSS_IPV6_CR_ACCEL_MODE_CONFIG_INVALID,
+		/**< Invalid config value for acceleration mode. */
+	NSS_IPV6_CR_INVALID_MSG_ERROR,
+		/**< Invalid message size error. */
+	NSS_IPV6_CR_DSCP2PRI_PRI_INVALID,
+		/**< Priority value out of range error. */
+	NSS_IPV6_CR_DSCP2PRI_CONFIG_INVALID,
+		/**< Invalid DSCP value. */
+	NSS_IPV6_CR_INVALID_RPS,
+		/**< Invalid RPS Value. */
+	NSS_IPV6_HASH_BITMAP_INVALID,
+		/**< Invalid hash bitmap. */
+	NSS_IPV6_DR_HW_DECEL_FAIL_ERROR,
+		/**< Hardware deceleration fail error. */
+	NSS_IPV6_CR_RETURN_EXIST_ERROR,
+		/**< Rule creation failed because a 5-tuple return already exists. */
+	NSS_IPV6_CR_INVALID_IDENTIFIER,
+		/**< Invalid identifier value. */
+	NSS_IPV6_CR_EMESH_SP_CONFIG_INVALID,
+		/**< Rule creation failed because Qos tag was not set for a Emesh SP rule. */
+	NSS_IPV6_LAST
+		/**< Maximum number of error responses. */
+};
+
+/**
+ * nss_ipv6_rule_create_msg
+ *	IPv6 rule for creating sub-messages.
+ */
+struct nss_ipv6_rule_create_msg {
+	/*
+	 * Request
+	 */
+	uint16_t valid_flags;
+			/**< Bit flags associated with the validity of parameters. */
+	uint16_t rule_flags;
+			/**< Bit flags associated with the rule. */
+	struct nss_ipv6_5tuple tuple;
+			/**< Holds values of the 5 tuple. */
+	struct nss_ipv6_connection_rule conn_rule;
+			/**< Basic connection-specific data. */
+	struct nss_ipv6_protocol_tcp_rule tcp_rule;
+			/**< Protocol-related accleration parameters. */
+	struct nss_ipv6_pppoe_rule pppoe_rule;
+			/**< PPPoE-related accleration parameters. */
+	struct nss_ipv6_qos_rule qos_rule;
+			/**< QoS-related accleration parameters. */
+	struct nss_ipv6_dscp_rule dscp_rule;
+			/**< DSCP-related accleration parameters. */
+	struct nss_ipv6_vlan_rule vlan_primary_rule;
+			/**< VLAN-related accleration parameters. */
+	struct nss_ipv6_vlan_rule vlan_secondary_rule;
+			/**< VLAN-related accleration parameters. */
+	struct nss_ipv6_src_mac_rule src_mac_rule;
+			/**< Source MAC address-related acceleration parameters. */
+	struct nss_ipv6_nexthop nexthop_rule;
+			/**< Parameters related to the next hop. */
+	struct nss_ipv6_rps_rule rps_rule;
+			/**< RPS parameter. */
+	struct nss_ipv6_igs_rule igs_rule;
+			/**< Ingress shaping related accleration parameters. */
+	struct nss_ipv6_identifier_rule identifier;
+			/**< Rule for adding identifier. */
+	struct nss_ipv6_mirror_rule mirror_rule;
+			/**< Mirror rule parameter. */
+};
+
+/**
+ * nss_ipv6_inquiry_msg
+ *	IPv6 connection inquiry sub-messages.
+ */
+struct nss_ipv6_inquiry_msg {
+	/**
+	 * Request by 5-tuple and response in other items.
+	 */
+	struct nss_ipv6_rule_create_msg rr;
+};
+
+/**
+ * nss_ipv6_mc_if_rule
+ *	IPv6 multicast rule for creating a per-interface payload.
+ */
+struct nss_ipv6_mc_if_rule {
+	uint16_t rule_flags;
+			/**< Bit flags associated with the rule for this interface. */
+
+	/**
+	 * Bit flags associated with the validity of parameters for this interface.
+	 */
+	uint16_t valid_flags;
+
+	uint32_t egress_vlan_tag[MAX_VLAN_DEPTH];
+					/**< VLAN tag stack for the egress packets. */
+	int32_t pppoe_if_num;		/**< PPPoE interface number. */
+	uint32_t if_num;		/**< Interface number. */
+	uint32_t if_mtu;		/**< MTU of the interface. */
+	uint16_t if_mac[3];		/**< Interface MAC address. */
+	uint8_t reserved[2];		/**< Reserved 2 bytes for alignment. */
+};
+
+/**
+ * nss_ipv6_mc_rule_create_msg
+ *	IPv6 multicast rule for creating sub-messages.
+ */
+struct nss_ipv6_mc_rule_create_msg {
+	struct nss_ipv6_5tuple tuple;	/**< Holds values of the 5 tuple. */
+
+	uint32_t rule_flags;		/**< Multicast command rule flags. */
+	uint32_t valid_flags;		/**< Multicast command validity flags. */
+	uint32_t src_interface_num;
+			/**< Source interface number (virtual or physical). */
+	uint32_t ingress_vlan_tag[MAX_VLAN_DEPTH];
+			/**< VLAN tag stack for the ingress packets. */
+	uint32_t qos_tag;		/**< QoS tag for the flow. */
+	uint16_t dest_mac[3];		/**< Destination multicast MAC address. */
+	uint16_t if_count;		/**< Number of destination interfaces. */
+	uint8_t egress_dscp;		/**< Egress DSCP value for the flow. */
+	uint8_t reserved[1];		/**< Reserved 1 byte for alignment. */
+	uint16_t igs_qos_tag;		/**< Ingress shaping QoS tag for the flow. */
+
+	struct nss_ipv6_mc_if_rule if_rule[NSS_MC_IF_MAX];
+			/**< Per-interface information. */
+};
+
+/**
+ * nss_ipv6_rule_destroy_msg
+ *	IPv6 rule for deleting sub-messages.
+ */
+struct nss_ipv6_rule_destroy_msg {
+	struct nss_ipv6_5tuple tuple;	/**< Holds values of the 5 tuple. */
+};
+
+/**
+ * nss_ipv6_rule_conn_get_table_size_msg
+ *	IPv6 rule for fetching connection tables size.
+ */
+struct nss_ipv6_rule_conn_get_table_size_msg {
+	uint32_t num_conn;
+		/**< Number of supported IPv6 connections. */
+	uint32_t ce_table_size;
+		/**< Size of the connection entry table in NSS firmware. */
+	uint32_t cme_table_size;
+		/**< Size of the connection match entry table in NSS firmware. */
+};
+
+/**
+ * nss_ipv6_rule_conn_cfg_msg
+ *	IPv6 rule for connection configuration sub-messages.
+ */
+struct nss_ipv6_rule_conn_cfg_msg {
+	uint32_t num_conn;		/**< Number of supported IPv6 connections. */
+	uint32_t ce_mem;		/**< Memory allocated by host for connection entries table. */
+	uint32_t cme_mem;		/**< Memory allocated by host for connection match entries table. */
+};
+
+/*
+ * IPv6 rule synchronization reasons.
+ */
+#define NSS_IPV6_RULE_SYNC_REASON_STATS 0
+		/**< Rule for synchronizing statistics. */
+#define NSS_IPV6_RULE_SYNC_REASON_FLUSH 1
+		/**< Rule for flushing a cache entry. */
+#define NSS_IPV6_RULE_SYNC_REASON_EVICT 2
+		/**< Rule for evicting a cache entry. */
+#define NSS_IPV6_RULE_SYNC_REASON_DESTROY 3
+		/**< Rule for destroying a cache entry (requested by the host OS). */
+
+/**
+ * nss_ipv6_conn_sync
+ *	IPv6 connection synchronization message.
+ */
+struct nss_ipv6_conn_sync {
+	uint32_t reserved;		/**< Reserved field for backward compatibility. */
+	uint8_t protocol;		/**< Protocol number. */
+	uint32_t flow_ip[4];		/**< Flow IP address. */
+	uint32_t flow_ident;		/**< Flow identifier (e.g., port). */
+	uint32_t flow_max_window;	/**< Largest seen window for the flow direction. */
+
+	/**
+	 * Largest seen sequence + segment length for the flow direction.
+	 */
+	uint32_t flow_end;
+
+	uint32_t flow_max_end;
+			/**< Largest seen ack + max(1, win) for the flow direction. */
+	uint32_t flow_rx_packet_count;	/**< Rx packet count for the flow interface. */
+	uint32_t flow_rx_byte_count;	/**< Rx byte count for the flow interface. */
+	uint32_t flow_tx_packet_count;	/**< Tx packet count for the flow interface. */
+	uint32_t flow_tx_byte_count;	/**< Tx byte count for the flow interface. */
+	uint32_t return_ip[4];		/**< Return IP address. */
+	uint32_t return_ident;		/**< Return identier (e.g., port). */
+	uint32_t return_max_window;
+			/**< Largest seen window for the return direction. */
+
+	/**
+	 * Largest seen sequence + segment length for the return direction.
+	 */
+	uint32_t return_end;
+
+	uint32_t return_max_end;
+			/**< Largest seen ack + max(1, win) for the return direction. */
+	uint32_t return_rx_packet_count;
+			/**< Rx packet count for the return interface. */
+	uint32_t return_rx_byte_count;
+			/**< Rx byte count for the return interface. */
+	uint32_t return_tx_packet_count;
+			/**< Tx packet count for the return interface. */
+	uint32_t return_tx_byte_count;
+			/**< Tx byte count for the return interface. */
+	uint32_t inc_ticks;	/**< Number of ticks since the last synchronization. */
+	uint32_t reason;	/**< Reason for the synchronization. */
+	uint8_t flags;		/**< Bit flags associated with the rule. */
+	uint32_t qos_tag;	/**< QoS tag. */
+	uint32_t cause;		/**< Flush cause associated with the rule. */
+};
+
+/**
+ * nss_ipv6_conn_sync_many_msg
+ *	Information for a multiple IPv6 connection statistics synchronization message.
+ */
+struct nss_ipv6_conn_sync_many_msg {
+	/* Request. */
+	uint16_t index;	/**< Request connection statistics from the index. */
+	uint16_t size;	/**< Buffer size of this message. */
+
+	/* Response. */
+	uint16_t next;	/**< Firmware response for the next connection to be requested. */
+	uint16_t count;	/**< Number of synchronized connections included in this message. */
+
+	struct nss_ipv6_conn_sync conn_sync[];	/**< Array for the statistics. */
+};
+
+/**
+ * nss_ipv6_accel_mode_cfg_msg
+ *	IPv6 acceleration mode configuration.
+ */
+struct nss_ipv6_accel_mode_cfg_msg {
+	uint32_t mode;		/**< Type of acceleration mode. */
+};
+
+/**
+ * nss_ipv6_dscp2pri_cfg_msg
+ *	IPv6 dscp2pri configuration msg.
+ */
+struct nss_ipv6_dscp2pri_cfg_msg {
+	uint8_t dscp;		/**< Value of DSCP. */
+	uint8_t priority;	/**< Corresponding priority. */
+};
+
+/**
+ * nss_ipv6_rps_hash_bitmap_cfg_msg
+ *	RPS hash mask configuration.
+ *
+ * The bitmap represents the host cores to which NSS firmware can steer
+ * packets based on packet hash. The least significant bit represents core0.
+ */
+struct nss_ipv6_rps_hash_bitmap_cfg_msg {
+	uint32_t hash_bitmap;	/**< Hash mask. */
+};
+
+/**
+ * nss_ipv6_node_sync
+ *	IPv6 node synchronization statistics.
+ */
+struct nss_ipv6_node_sync {
+	struct nss_cmn_node_stats node_stats;		/**< Common node statistics. */
+	uint32_t ipv6_connection_create_requests;
+			/**< Number of connection create requests. */
+
+	/**
+	 * Number of connection create requests that collided with the existing entries.
+	 */
+	uint32_t ipv6_connection_create_collisions;
+
+	/**
+	 * Number of connection create requests that had invalid interfaces.
+	 */
+	uint32_t ipv6_connection_create_invalid_interface;
+
+	uint32_t ipv6_connection_destroy_requests;
+			/**< Number of connection destroy requests. */
+	uint32_t ipv6_connection_destroy_misses;
+			/**< Number of connection destroy requests that missed the cache. */
+	uint32_t ipv6_connection_hash_hits;	/**< Number of connection hash hits. */
+	uint32_t ipv6_connection_hash_reorders;	/**< Number of connection hash reorders. */
+	uint32_t ipv6_connection_flushes;	/**< Number of connection flushes. */
+	uint32_t ipv6_connection_evictions;	/**< Number of connection evictions. */
+	uint32_t ipv6_fragmentations;		/**< Number of successful fragmentations. */
+	uint32_t ipv6_frag_fails;		/**< Number of fragmentation fails. */
+	uint32_t ipv6_dropped_by_rule;		/**< Number of packets dropped by a drop rule.*/
+	uint32_t ipv6_mc_connection_create_requests;
+			/**< Number of multicast connection create requests. */
+	uint32_t ipv6_mc_connection_update_requests;
+			/**< Number of multicast connection update requests. */
+
+	/**
+	 * Number of multicast connection create requests that had invalid interfaces.
+	 */
+	uint32_t ipv6_mc_connection_create_invalid_interface;
+
+	uint32_t ipv6_mc_connection_destroy_requests;
+			/**< Number of multicast connection destroy requests. */
+
+	/**
+	 * Number of multicast connection destroy requests that missed the cache.
+	 */
+	uint32_t ipv6_mc_connection_destroy_misses;
+
+	uint32_t ipv6_mc_connection_flushes;
+			/**< Number of multicast connection flushes. */
+
+	uint32_t ipv6_connection_create_invalid_mirror_ifnum;
+			/**< Number of failed create requests with an invalid mirror interface number. */
+
+	uint32_t ipv6_connection_create_invalid_mirror_iftype;
+			/**< Number of failed create requests with an invalid mirror interface type. */
+
+	uint32_t ipv6_mirror_failures;
+			/**< Mirror packet failed. */
+
+	uint32_t exception_events[NSS_IPV6_EXCEPTION_EVENT_MAX];
+			/**< Number of exception events. */
+};
+
+/**
+ * nss_ipv6_msg
+ *	Data for sending and receiving IPv6 bridge or routing messages.
+ */
+struct nss_ipv6_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of an IPv6 bridge or routing message.
+	 */
+	union {
+		struct nss_ipv6_rule_create_msg rule_create;
+				/**< Create a rule. */
+		struct nss_ipv6_rule_destroy_msg rule_destroy;
+				/**< Destroy a rule. */
+		struct nss_ipv6_conn_sync conn_stats;
+				/**< Synchronize statistics. */
+		struct nss_ipv6_node_sync node_stats;
+				/**< Synchronize node statistics. */
+		struct nss_ipv6_rule_conn_get_table_size_msg size;
+				/**< Get the size for connection tables. */
+		struct nss_ipv6_rule_conn_cfg_msg rule_conn_cfg;
+				/**< Configure a rule connection. */
+		struct nss_ipv6_mc_rule_create_msg mc_rule_create;
+				/**< Create a multicast rule. */
+		struct nss_ipv6_conn_sync_many_msg conn_stats_many;
+				/**< Synchronize multiple connection statistics. */
+		struct nss_ipv6_accel_mode_cfg_msg accel_mode_cfg;
+				/**< Configure acceleration mode. */
+		struct nss_ipv6_inquiry_msg inquiry;
+				/**< Inquiry if a connection has been created. */
+		struct nss_ipv6_dscp2pri_cfg_msg dscp2pri_cfg;
+				/**< Configure DSCP-to-priority mapping. */
+		struct nss_ipv6_rps_hash_bitmap_cfg_msg rps_hash_bitmap;
+				/**< Configure rps_hash_bitmap. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * nss_ipv6_stats_notification
+ *	Data for sending IPv6 statistics.
+ */
+struct nss_ipv6_stats_notification {
+	uint32_t core_id;					/**< Core ID. */
+	uint64_t cmn_node_stats[NSS_STATS_NODE_MAX];		/**< Common node statistics. */
+	uint64_t special_stats[NSS_IPV6_STATS_MAX];		/**< IPv6 special statistics. */
+	uint64_t exception_stats[NSS_IPV6_EXCEPTION_EVENT_MAX];	/**< IPv6 exception statistics. */
+};
+
+/**
+ * Configured IPv6 connection number to use for calculating the total number of
+ * connections.
+ */
+extern int nss_ipv6_conn_cfg;
+
+#ifdef __KERNEL__
+
+/**
+ * nss_ipv6_max_conn_count
+ *	Returns the maximum number of IPv6 connections that the NSS acceleration
+ *	engine supports.
+ *
+ * @return
+ * Number of connections that can be accelerated.
+ */
+extern int nss_ipv6_max_conn_count(void);
+
+/**
+ * Callback function for receiving IPv6 messages.
+ *
+ * @datatypes
+ * nss_ipv6_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_ipv6_msg_callback_t)(void *app_data, struct nss_ipv6_msg *msg);
+
+/**
+ * nss_ipv6_tx
+ *	Transmits an IPv6 message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_ipv6_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_ipv6_tx(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_msg *msg);
+
+/**
+ * nss_ipv6_tx_sync
+ *	Transmits a synchronous IPv6 message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_ipv6_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_ipv6_tx_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_msg *msg);
+
+/**
+ * nss_ipv6_tx_with_size
+ *	Transmits an IPv6 message with a specified size to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_ipv6_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ * @param[in] size     Actual size of this message.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_ipv6_tx_with_size(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_msg *msg, uint32_t size);
+
+/**
+ * nss_ipv6_notify_register
+ *	Registers a notifier callback to forward the IPv6 messages received from the NSS
+ *	firmware to the registered subsystem.
+ *
+ * @datatypes
+ * nss_ipv6_msg_callback_t
+ *
+ * @param[in] cb        Callback function for the message.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_ipv6_notify_register(nss_ipv6_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_ipv6_notify_unregister
+ *	Deregisters a notifier callback from the NSS.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The notifier callback must have been previously registered.
+ */
+extern void nss_ipv6_notify_unregister(void);
+
+/**
+ * nss_ipv6_conn_sync_many_notify_register
+ *	Registers a notifier callback with the NSS for connection synchronization
+ *	message responses.
+ *
+ * @datatypes
+ * nss_ipv6_msg_callback_t
+ *
+ * @param[in] cb  Callback function for the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_ipv6_conn_sync_many_notify_register(nss_ipv6_msg_callback_t cb);
+
+/**
+ * nss_ipv6_conn_sync_many_notify_unregister
+ *	Degisters a notifier callback from the NSS.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The notifier callback must have been previously registered.
+ */
+extern void nss_ipv6_conn_sync_many_notify_unregister(void);
+
+/**
+ * nss_ipv6_get_mgr
+ *	Gets the NSS context that is managing the IPv6 processes.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_ipv6_get_mgr(void);
+
+/**
+ * nss_ipv6_msg_init
+ *	Initializes IPv6-specific messages.
+ *
+ * @datatypes
+ * nss_ipv6_msg \n
+ * nss_ipv6_msg_callback_t
+ *
+ * @param[in,out] nim       Pointer to the NSS interface message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_ipv6_msg_init(struct nss_ipv6_msg *nim, uint16_t if_num, uint32_t type, uint32_t len,
+			nss_ipv6_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_ipv6_register_handler
+ *	Registers the IPv6 message handler.
+ *
+ * @return
+ * None.
+ */
+void nss_ipv6_register_handler(void);
+
+/**
+ * nss_ipv6_register_sysctl
+ *	Registers the IPv6 system control table.
+ *
+ * @return
+ * None.
+ */
+void nss_ipv6_register_sysctl(void);
+
+/**
+ * nss_ipv6_unregister_sysctl
+ *	Deregisters the IPv6 system control table.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The system control table must have been previously registered.
+ */
+void nss_ipv6_unregister_sysctl(void);
+
+/**
+ * nss_ipv6_update_conn_count
+ *	Sets the maximum number of IPv6 connections.
+ *
+ * @param[in] ipv6_num_conn  Maximum number.
+ *
+ * @return
+ * 0 -- Success
+ */
+int nss_ipv6_update_conn_count(int ipv6_num_conn);
+
+/**
+ * nss_ipv6_free_conn_tables
+ *	Frees memory allocated for connection tables.
+ *
+ * @return
+ * None.
+ */
+void nss_ipv6_free_conn_tables(void);
+
+/**
+ * nss_ipv6_dscp_action_get
+ *	Gets the action value of the DSCP.
+ *
+ * @param[in]	dscp	Value of the DSCP field.
+ *
+ * @return
+ * Action value of the DSCP field.
+ */
+enum nss_ipv6_dscp_map_actions nss_ipv6_dscp_action_get(uint8_t dscp);
+
+/*
+ * Logger APIs
+ */
+
+/**
+ * nss_ipv6_log_tx_msg
+ *	Logs an IPv6 message that is sent to the NSS firmware.
+ *
+ * @datatypes
+ * nss_ipv6_msg
+ *
+ * @param[in] nim  Pointer to the NSS interface message.
+ *
+ * @return
+ * None.
+ */
+void nss_ipv6_log_tx_msg(struct nss_ipv6_msg *nim);
+
+/**
+ * nss_ipv6_log_rx_msg
+ *	Logs an IPv6 message that is received from the NSS firmware.
+ *
+ * @datatypes
+ * nss_ipv6_msg
+ *
+ * @param[in] nim  Pointer to the NSS interface message.
+ *
+ * @return
+ * None.
+ */
+void nss_ipv6_log_rx_msg(struct nss_ipv6_msg *nim);
+
+/**
+ * nss_ipv6_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_ipv6_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_ipv6_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_ipv6_stats_unregister_notifier(struct notifier_block *nb);
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_IPV6_H */
diff --git a/qca-nss-drv/exports/nss_ipv6_reasm.h b/qca-nss-drv/exports/nss_ipv6_reasm.h
new file mode 100644
index 0000000..806bf00
--- /dev/null
+++ b/qca-nss-drv/exports/nss_ipv6_reasm.h
@@ -0,0 +1,92 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipv6_reasm.h
+ *	NSS IPv6 reassembly interface definitions.
+ */
+
+#ifndef __NSS_IPV6_REASM_H
+#define __NSS_IPV6_REASM_H
+
+/**
+ * @addtogroup nss_ipv6_reasm_subsystem
+ * @{
+ */
+
+/**
+ * nss_ipv6_reasm_stats
+ *	IPv6 reassembly node statistics.
+ */
+enum nss_ipv6_reasm_stats {
+	NSS_IPV6_REASM_STATS_ALLOC_FAILS,
+				/**< Number of fragment queue allocation failures. */
+	NSS_IPV6_REASM_STATS_TIMEOUTS,
+				/**< Number of expired fragment queues. */
+	NSS_IPV6_REASM_STATS_DISCARDS,
+				/**< Number of fragment queues discarded due to malformed fragments. */
+	NSS_IPV6_REASM_STATS_MAX,
+				/**< Maximum message type. */
+};
+
+/**
+ * nss_ipv6_reasm_stats_notification
+ *	Data for sending IPv6 reassembly statistics.
+ */
+struct nss_ipv6_reasm_stats_notification {
+	uint32_t core_id;					/**< Core ID. */
+	uint64_t cmn_node_stats[NSS_STATS_NODE_MAX];		/**< Common node statistics. */
+	uint64_t ipv6_reasm_stats[NSS_IPV6_REASM_STATS_MAX];	/**< IPv6 reassembly statistics. */
+};
+
+#ifdef __KERNEL__
+
+/**
+ * nss_ipv6_reasm_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_ipv6_reasm_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_ipv6_reasm_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_ipv6_reasm_stats_unregister_notifier(struct notifier_block *nb);
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_IPV6_REASM_H */
diff --git a/qca-nss-drv/exports/nss_l2tpv2.h b/qca-nss-drv/exports/nss_l2tpv2.h
new file mode 100644
index 0000000..e36c850
--- /dev/null
+++ b/qca-nss-drv/exports/nss_l2tpv2.h
@@ -0,0 +1,327 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_l2tpv2.h
+ *	NSS L2TPv2 interface definitions.
+ */
+
+#ifndef _NSS_L2TP_V2_H_
+#define _NSS_L2TP_V2_H_
+
+/**
+ * @addtogroup nss_l2tpv2_subsystem
+ * @{
+ */
+
+/**
+ * Maximum number of supported L2TPv2 sessions.
+ */
+#define NSS_MAX_L2TPV2_DYNAMIC_INTERFACES 4
+
+/**
+ * nss_l2tpv2_metadata_types
+ *	Message types for L2TPv2 requests and responses.
+ */
+enum nss_l2tpv2_metadata_types {
+	NSS_L2TPV2_MSG_SESSION_CREATE,
+	NSS_L2TPV2_MSG_SESSION_DESTROY,
+	NSS_L2TPV2_MSG_SYNC_STATS,
+	NSS_L2TPV2_MSG_BIND_IPSEC_IF,
+	NSS_L2TPV2_MSG_MAX
+};
+
+/**
+ * nss_l2tpv2_stats_session
+ *	L2TPv2 debug statistics.
+ */
+enum nss_l2tpv2_stats_session {
+	NSS_L2TPV2_STATS_SESSION_RX_PPP_LCP_PKTS,		/**< Number of PPP LCP packets received. */
+	NSS_L2TPV2_STATS_SESSION_RX_EXP_DATA_PKTS,		/**< Number of Rx exceptioned packets. */
+	NSS_L2TPV2_STATS_SESSION_ENCAP_PBUF_ALLOC_FAIL_PKTS,	/**< Number of times packet buffer allocation failed during encapsulation. */
+	NSS_L2TPV2_STATS_SESSION_DECAP_PBUF_ALLOC_FAIL_PKTS,	/*< Number of times packet buffer allocation failed during decapsulation. */
+	NSS_L2TPV2_STATS_SESSION_DECAP_L2TPOIPSEC_SRC_ERR,
+						/**< Number of packets dropped due to source error in L2TP over IPsec flow in decapsulation. */
+	NSS_L2TPV2_STATS_SESSION_MAX		/**< Maximum message type. */
+};
+
+/**
+ * nss_l2tpv2_stats_notification
+ *	L2TPv2 statistics structure.
+ */
+struct nss_l2tpv2_stats_notification {
+	uint32_t core_id;				/**< Core ID. */
+	uint32_t if_num;				/**< Interface number. */
+	uint64_t stats[NSS_L2TPV2_STATS_SESSION_MAX];	/**< L2TPv2 statistics. */
+};
+
+#ifdef __KERNEL__ /* only kernel will use. */
+/**
+ * nss_l2tpv2_session_create_msg
+ *	Payload for creating an L2TPv2 session.
+ */
+struct nss_l2tpv2_session_create_msg {
+	uint16_t local_tunnel_id;	/**< Local identifier for the control connection. */
+	uint16_t local_session_id;	/**< Local identifier of session inside a tunnel. */
+	uint16_t peer_tunnel_id;	/**< Remote identifier for the control connection. */
+	uint16_t peer_session_id;	/**< Remote identifier of session inside a tunnel. */
+
+	uint32_t sip;			/**< Local tunnel endpoint IP address. */
+	uint32_t dip;			/**< Remote tunnel endpoint IP address. */
+	uint32_t reorder_timeout;	/**< Reorder timeout for out of order packets */
+
+	uint16_t sport;			/**< Local source port. */
+	uint16_t dport;			/**< Remote source port. */
+
+	uint8_t recv_seq;		/**< Sequence number received. */
+	uint8_t oip_ttl;		/**< Maximum time-to-live value for outer IP packet. */
+	uint8_t udp_csum;		/**< UDP checksum. */
+	uint8_t reserved;		/**< Alignment padding. */
+};
+
+/**
+ * nss_l2tpv2_session_destroy_msg
+ *	Payload for deletion an L2TPv2 session.
+ */
+struct nss_l2tpv2_session_destroy_msg {
+	uint16_t local_tunnel_id;	/**< ID of the local tunnel. */
+	uint16_t local_session_id;	/**< ID of the local session. */
+};
+
+/**
+ * nss_l2tpv2_bind_ipsec_if_msg
+ *	Message for binding the IPsec interface with L2TP.
+ *
+ * Message for configuring the L2TP session with an
+ * IPsec inner interface number. This is used when
+ * L2TP tunnel is enabled with IPsec.
+ */
+struct nss_l2tpv2_bind_ipsec_if_msg {
+	uint32_t ipsec_ifnum;	/**< Inner IPSec interface number. */
+};
+
+/**
+ * nss_l2tpv2_sync_session_stats_msg
+ *	Message information for L2TPv2 synchronization statistics.
+ */
+struct nss_l2tpv2_sync_session_stats_msg {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics. */
+	uint32_t rx_errors;			/**< Not used. Reserved for backward compatibility. */
+	uint32_t rx_seq_discards;
+			/**< Rx packets discarded because of a sequence number check. */
+	uint32_t rx_oos_packets;		/**< Number of out of sequence packets received. */
+	uint32_t tx_errors;			/**< Not used. Reserved for backward compatibility. */
+	uint32_t tx_dropped;			/**< Tx packets dropped because of encapsulation failure or next node's queue is full. */
+
+	/**
+	 * Debug statistics for L2tp v2.
+	 */
+	struct {
+		uint32_t rx_ppp_lcp_pkts;
+				/**< Number of PPP LCP packets received. */
+		uint32_t rx_exception_data_pkts;
+				/**< Data packet exceptions sent to the host. */
+		uint32_t encap_pbuf_alloc_fail;
+				/**< Buffer allocation failure during encapsulation. */
+		uint32_t decap_pbuf_alloc_fail;
+				/**< Buffer allocation failure during decapsulation. */
+		uint32_t decap_l2tpoipsec_src_error;
+				/**< Packets dropped due to the wrong source for the L2TPoIPsec flow. */
+	} debug_stats;	/**< Debug statistics object for l2tp v2. */
+};
+
+/**
+ * nss_l2tpv2_msg
+ *	Data for sending and receiving L2TPv2 messages.
+ */
+struct nss_l2tpv2_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of an L2TPv2 message.
+	 */
+	union {
+		struct nss_l2tpv2_session_create_msg session_create_msg;
+				/**< Session create message. */
+		struct nss_l2tpv2_session_destroy_msg session_destroy_msg;
+				/**< Session delete message. */
+		struct nss_l2tpv2_sync_session_stats_msg stats;
+				/**< Session statistics. */
+		struct nss_l2tpv2_bind_ipsec_if_msg bind_ipsec_if_msg;
+				/**< Bind IPsec interface message. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving L2TPv2 messages.
+ *
+ * @datatypes
+ * nss_l2tpv2_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_l2tpv2_msg_callback_t)(void *app_data, struct nss_l2tpv2_msg *msg);
+
+/**
+ * nss_l2tpv2_tx
+ *	Sends L2TPv2 messages to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_l2tpv2_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_l2tpv2_tx(struct nss_ctx_instance *nss_ctx, struct nss_l2tpv2_msg *msg);
+
+/**
+ * nss_l2tpv2_get_context.
+ *	Gets the L2TPv2 context used in L2TPv2 messages sent to the NSS.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_l2tpv2_get_context(void);
+
+/**
+ * Callback function for receiving L2TPv2 tunnel data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_l2tpv2_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_register_l2tpv2_if
+ *	Registers the L2TPv2 tunnel interface with the NSS for sending and
+ *	receiving messages.
+ *
+ * @datatypes
+ * nss_l2tpv2_callback_t \n
+ * nss_l2tpv2_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num           NSS interface number.
+ * @param[in] l2tpv2_callback  Callback for the L2TP tunnel data.
+ * @param[in] msg_callback     Callback for the L2TP tunnel message.
+ * @param[in] netdev           Pointer to the associated network device.
+ * @param[in] features         SKB types supported by this interface.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_register_l2tpv2_if(uint32_t if_num, nss_l2tpv2_callback_t l2tpv2_callback,
+					nss_l2tpv2_msg_callback_t msg_callback, struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_unregister_l2tpv2_if
+ *	Deregisters the L2TPv2 tunnel interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The tunnel interface must have been previously registered.
+ */
+extern void nss_unregister_l2tpv2_if(uint32_t if_num);
+
+/**
+ * nss_l2tpv2_msg_init
+ *	Initializes an L2TPv2 message.
+ *
+ * @datatypes
+ * nss_l2tpv2_msg
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    Interface number
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Pointer to the message callback.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_l2tpv2_msg_init(struct nss_l2tpv2_msg *ncm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data);
+
+/**
+ * nss_l2tpv2_register_handler
+ *	Registers the L2TPv2 interface with the NSS debug statistics handler.
+ *
+ * @return
+ * None.
+ */
+extern void nss_l2tpv2_register_handler(void);
+
+/**
+ * nss_l2tpv2_session_debug_stats_get
+ *	Gets L2TPv2 NSS session debug statistics.
+ *
+ * @param[out] stats_mem  Pointer to the memory address, which must be large
+ *                        enough to hold all the statistics.
+ *
+ * @return
+ * None.
+ */
+extern void nss_l2tpv2_session_debug_stats_get(void  *stats_mem);
+
+/**
+ * nss_l2tpv2_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_l2tpv2_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_l2tpv2_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_l2tpv2_stats_unregister_notifier(struct notifier_block *nb);
+#endif /*__KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* _NSS_L2TP_V2_H_ */
diff --git a/qca-nss-drv/exports/nss_lag.h b/qca-nss-drv/exports/nss_lag.h
new file mode 100644
index 0000000..4e7e7ea
--- /dev/null
+++ b/qca-nss-drv/exports/nss_lag.h
@@ -0,0 +1,211 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, 2015, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_lag.h
+ *	NSS LAG APIs
+ */
+
+/**
+ * @addtogroup nss_lag_subsystem
+ * @{
+ */
+
+/**
+ * nss_lag_metadata_types
+ *	Types of LAG metadata.
+ */
+enum nss_lag_metadata_types {
+	NSS_TX_METADATA_LAG_STATE_CHANGE = 0,
+	NSS_TX_METADATA_LAG_MAX,
+};
+
+/**
+ * nss_lag_state_change_ev
+ *	LAG change events.
+ */
+enum nss_lag_state_change_ev {
+	NSS_LAG_RELEASE = 0,
+	NSS_LAG_ENSLAVE = 1,
+};
+
+/**
+ * nss_lag_error_types
+ *	LAG return values.
+ */
+enum nss_lag_error_types {
+	NSS_LAG_ERROR_EINTERFACE = 1,
+	NSS_LAG_ERROR_EMSG = 2,
+};
+
+/**
+ * nss_lag_state_change
+ *	Link aggregation (LAG) state changes.
+ */
+struct nss_lag_state_change {
+	uint32_t lagid;				/**< ID of the link aggregation group. */
+	uint32_t interface;
+			/**< Physical interface on which the state change occurred. */
+	enum nss_lag_state_change_ev event;	/**< Type of state change event. */
+};
+
+/**
+ * nss_lag_msg
+ *	Data for sending and receiving LAG messages.
+ */
+struct nss_lag_msg {
+	struct nss_cmn_msg cm;	/**< Common message header. */
+
+	/**
+	 * Payload of a LAG message.
+	 */
+	union {
+		struct nss_lag_state_change state;
+				/**< State change message. */
+	} msg;			/**< Message payload for LAG configuration messages exchanged with NSS core. */
+};
+
+/**
+ * nss_lag_tx
+ *	Sends a LAG message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_lag_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_lag_tx(struct nss_ctx_instance *nss_ctx, struct nss_lag_msg *msg);
+
+/**
+ * Callback function for receiving LAG data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] dev   Pointer to the associated network device.
+ * @param[in] skb   Pointer to the data socket buffer.
+ * @param[in] napi  Pointer to the NAPI structure.
+ */
+typedef void (*nss_lag_callback_t)(struct net_device *dev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for receiving a LAG message.
+ *
+ * @datatypes
+ * nss_lag_msg
+ *
+ * @param[in] ctx  Pointer to the application context for this message.
+ * @param[in] nm   Pointer to the message data.
+ */
+typedef void (*nss_lag_msg_callback_t)(void *ctx, struct nss_lag_msg *nm);
+
+/**
+ * Callback function for receiving a LAG event.
+ *
+ * @datatypes
+ * nss_lag_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_lag_event_callback_t)(void *app_data, struct nss_lag_msg *msg);
+
+/**
+ * nss_register_lag_if
+ *	Registers the LAG interface with the NSS for sending and receiving data
+ *	and messages.
+ *
+ * @datatypes
+ * nss_lag_callback_t \n
+ * nss_lag_event_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num     NSS interface number.
+ * @param[in] lag_cb     Callback to receive LAG data.
+ * @param[in] lag_ev_cb  Callback to receive LAG events.
+ * @param[in] netdev     Pointer to the associated network device.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern void *nss_register_lag_if(uint32_t if_num,
+			 nss_lag_callback_t lag_cb,
+			 nss_lag_event_callback_t lag_ev_cb,
+			 struct net_device *netdev);
+
+/**
+ * nss_unregister_lag_if
+ *	Deregisters the LAG interface from the NSS.
+ *
+ * @param[in] if_num  LAG interface number
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The LAG interface must have been previously registered.
+ */
+extern void nss_unregister_lag_if(uint32_t if_num);
+
+/**
+ * nss_lag_msg_init
+ *	Initializes a LAG message.
+ *
+ * @datatypes
+ * nss_lag_msg \n
+ * nss_lag_msg_callback_t
+ *
+ * @param[in,out] nlm       Pointer to the message.
+ * @param[in]     lag_num   LAG interface number.
+ * @param[in]     type      Type of buffer.
+ * @param[in]     len       Length of the buffer.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_lag_msg_init(struct nss_lag_msg *nlm, uint16_t lag_num, uint32_t type, uint32_t len,
+				nss_lag_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_lag_tx_slave_state
+ *	Sends LAG slave state.
+ *
+ * @datatypes
+ * nss_lag_state_change_ev
+ *
+ * @param[in] lagid        LAG Group ID.
+ * @param[in] slave_ifnum  Slave interface number.
+ * @param[in] slave_state  Slave state.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_lag_tx_slave_state(uint16_t lagid,
+		int32_t slave_ifnum,
+		enum nss_lag_state_change_ev slave_state);
+
+/**
+ * @}
+ */
diff --git a/qca-nss-drv/exports/nss_lso_rx.h b/qca-nss-drv/exports/nss_lso_rx.h
new file mode 100644
index 0000000..1a000b7
--- /dev/null
+++ b/qca-nss-drv/exports/nss_lso_rx.h
@@ -0,0 +1,88 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_lso_rx.h
+ *	NSS driver LSO (Large Send Offload) Rx header file.
+ */
+
+#ifndef __NSS_LSO_RX_H
+#define __NSS_LSO_RX_H
+
+/**
+ * @addtogroup nss_lso_rx_subsystem
+ * @{
+ */
+
+/**
+ * nss_lso_rx_stats_types
+ *	LSO Rx driver statistics.
+ */
+enum nss_lso_rx_stats_types {
+	NSS_LSO_RX_STATS_TX_DROPPED,		/**< Number of packets dropped because transmit queue is full. */
+	NSS_LSO_RX_STATS_DROPPED,		/**< Number of packets dropped because of node internal errors. */
+	NSS_LSO_RX_STATS_PBUF_ALLOC_FAIL,	/**< Number of pbuf allocation failures. */
+	NSS_LSO_RX_STATS_PBUF_REFERENCE_FAIL,	/**< Number of pbuf reference failures. */
+	NSS_LSO_RX_STATS_MAX,			/**< Maximum message type. */
+};
+
+/**
+ * nss_lso_rx_stats_notification
+ *	Data for sending LSO Rx statistics.
+ */
+struct nss_lso_rx_stats_notification {
+	uint32_t core_id;				/**< Core ID. */
+	uint64_t cmn_node_stats[NSS_STATS_NODE_MAX];	/**< Common node statistics. */
+	uint64_t node_stats[NSS_LSO_RX_STATS_MAX];	/**< LSO Rx special statistics. */
+};
+
+#ifdef __KERNEL__ /* only kernel will use. */
+/**
+ * nss_lso_rx_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_lso_rx_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_lso_rx_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_lso_rx_stats_unregister_notifier(struct notifier_block *nb);
+#endif /*__KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_LSO_RX_H */
diff --git a/qca-nss-drv/exports/nss_map_t.h b/qca-nss-drv/exports/nss_map_t.h
new file mode 100644
index 0000000..dbf8788
--- /dev/null
+++ b/qca-nss-drv/exports/nss_map_t.h
@@ -0,0 +1,386 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_map_t.h
+ *	NSS MAP-T interface definitions.
+ */
+
+#ifndef _NSS_MAP_T_H_
+#define _NSS_MAP_T_H_
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+#include "nss_dynamic_interface.h"
+#endif
+
+/**
+ * @addtogroup nss_map_t_subsystem
+ * @{
+ */
+
+/**
+ * Maximum number of supported MAP-T instances.
+ */
+#define NSS_MAX_MAP_T_DYNAMIC_INTERFACES 4
+
+/**
+ * MAP-T metadata flag.
+ */
+#define NSS_MAPT_MDATA_FLAG_DF_BIT  (1 << 0)
+
+/**
+ * nss_map_t_mdata
+ *         MAP-T metadata
+ */
+struct nss_map_t_mdata {
+	uint16_t flags;				/**< Metadata flags. */
+	uint16_t res[6];			/**< Reserved for future use. */
+};
+
+/**
+ * nss_map_t_msg_types
+ *	Message types for MAP-T requests and responses.
+ */
+enum nss_map_t_msg_types {
+	NSS_MAP_T_MSG_INSTANCE_RULE_CONFIGURE,
+	NSS_MAP_T_MSG_INSTANCE_RULE_DECONFIGURE,
+	NSS_MAP_T_MSG_SYNC_STATS,
+	NSS_MAP_T_MSG_MAX
+};
+
+/**
+ * nss_map_t_stats_instance
+ *	MAP-T debug error types.
+ */
+enum nss_map_t_stats_instance {
+	NSS_MAP_T_STATS_V4_TO_V6_PBUF_EXCEPTION,
+	NSS_MAP_T_STATS_V4_TO_V6_PBUF_NO_MATCHING_RULE,
+	NSS_MAP_T_STATS_V4_TO_V6_PBUF_NOT_TCP_OR_UDP,
+	NSS_MAP_T_STATS_V4_TO_V6_RULE_ERR_LOCAL_PSID,
+	NSS_MAP_T_STATS_V4_TO_V6_RULE_ERR_LOCAL_IPV6,
+	NSS_MAP_T_STATS_V4_TO_V6_RULE_ERR_REMOTE_PSID,
+	NSS_MAP_T_STATS_V4_TO_V6_RULE_ERR_REMOTE_EA_BITS,
+	NSS_MAP_T_STATS_V4_TO_V6_RULE_ERR_REMOTE_IPV6,
+	NSS_MAP_T_STATS_V6_TO_V4_PBUF_EXCEPTION,
+	NSS_MAP_T_STATS_V6_TO_V4_PBUF_NO_MATCHING_RULE,
+	NSS_MAP_T_STATS_V6_TO_V4_PBUF_NOT_TCP_OR_UDP,
+	NSS_MAP_T_STATS_V6_TO_V4_RULE_ERR_LOCAL_IPV4,
+	NSS_MAP_T_STATS_V6_TO_V4_RULE_ERR_REMOTE_IPV4,
+	NSS_MAP_T_STATS_MAX
+};
+
+/**
+ * nss_map_t_stats_notification
+ *	MAP-T statistics structure.
+ */
+struct nss_map_t_stats_notification {
+	uint32_t core_id;				/**< Core ID. */
+	uint32_t if_num;				/**< Interface number. */
+	enum nss_dynamic_interface_type if_type;	/**< Dynamic interface type. */
+	uint64_t stats[NSS_MAP_T_STATS_MAX];		/**< MAP-T statistics. */
+};
+
+#ifdef __KERNEL__ /* only kernel will use. */
+/**
+ * nss_map_t_instance_rule_config_msg
+ *	Message information for configuring a MAP-T instance.
+ */
+struct nss_map_t_instance_rule_config_msg {
+	uint32_t rule_num;			/**< Rule sequence number */
+	uint32_t total_rules;			/**< Total number of NAT64 rules configured. */
+	uint32_t local_ipv6_prefix_len;		/**< Local IPv6 prefix length. */
+	uint32_t local_ipv4_prefix;		/**< Local IPv4 prefix. */
+	uint32_t local_ipv4_prefix_len;		/**< Local IPv4 prefix length. */
+	uint32_t local_ea_len;			/**< Local EA bits length. */
+	uint32_t local_psid_offset;		/**< Local PSID offset. */
+
+	uint32_t reserve_a;			/**< Reserved for backward compatibility. */
+
+	uint32_t remote_ipv6_prefix_len;	/**< Remote IPv6 prefix length. */
+	uint32_t remote_ipv4_prefix;		/**< Remote IPv4 prefix. */
+	uint32_t remote_ipv4_prefix_len;	/**< Remote IPv4 prefix length. */
+	uint32_t remote_ea_len;			/**< Remote EA bits length. */
+	uint32_t remote_psid_offset;		/**< Remote PSID offset. */
+
+	uint32_t local_map_style;		/**< Local MAP style. */
+	uint32_t remote_map_style;		/**< Remote MAP style. */
+
+	uint32_t sibling_if;			/**< Sibling interface number. */
+
+	uint8_t local_ipv6_prefix[16];		/**< Local IPv6 prefix. */
+	uint8_t reserve_b[16];			/**< Reserved for backward compatibility. */
+	uint8_t remote_ipv6_prefix[16];		/**< Remote IPv6 prefix. */
+
+	uint8_t valid_rule;			/**< MAP-T rule validity. */
+	uint8_t flags;				/**< MAP-T flags. */
+	uint8_t reserved[2];			/**< Reserved for byte alignment. */
+};
+
+/**
+ * nss_map_t_instance_rule_deconfig_msg
+ *	Message information for deleting a MAP-T instance.
+ */
+struct nss_map_t_instance_rule_deconfig_msg {
+	int32_t if_number;			/**< Interface number. */
+};
+
+/**
+ * nss_map_t_sync_stats_msg
+ *	Message information for MAP-T synchronization statistics.
+ */
+struct nss_map_t_sync_stats_msg {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics. */
+	uint32_t tx_dropped;			/**< Dropped Tx packets. */
+
+	/**
+	 * Debug statistics for MAP-T.
+	 */
+	union {
+
+		/**
+		 * IPv4 to IPv6 path debug statistics.
+		 */
+		struct {
+			uint32_t exception_pkts;
+					/**< Number of packets exceptioned to host in IPv4 to IPv6 fast path. */
+			uint32_t no_matching_rule;
+					/**< No matching of any rule. */
+			uint32_t not_tcp_or_udp;
+					/**< Number of packets which are neither UDP nor TCP. */
+			uint32_t rule_err_local_psid;
+					/**< Calculate the local PSID error. */
+			uint32_t rule_err_local_ipv6;
+					/**< Calculate local IPv6 error. */
+			uint32_t rule_err_remote_psid;
+					/**< Calculate remote PSID error. */
+			uint32_t rule_err_remote_ea_bits;
+					/**< Calculate remote EA bits error. */
+			uint32_t rule_err_remote_ipv6;
+					/**< Calculate remote IPv6 error. */
+		} v4_to_v6;	/**< IPv4 to IPv6 debug statistics object. */
+
+		/**
+		 * IPv6 to IPv4 path debug statistics.
+		 */
+		struct {
+			uint32_t exception_pkts;
+					/**< Number of packets exception to host in IPv6 to IPv4 fast path. */
+			uint32_t no_matching_rule;
+					/**< No matching of any rule. */
+			uint32_t not_tcp_or_udp;
+					/**< Number of packets which are neither UDP nor TCP. */
+			uint32_t rule_err_local_ipv4;
+					/**< Calculate local IPv4 error. */
+			uint32_t rule_err_remote_ipv4;
+					/**< Calculate remote IPv4 error. */
+		} v6_to_v4;	/**< IPv6 to IPv4 debug statistics object */
+
+	} debug_stats;		/**< Payload of debug statistics. */
+};
+
+/**
+ * nss_map_t_msg
+ *	Data for sending and receiving MAP-T messages.
+ */
+struct nss_map_t_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a MAP-T message.
+	 */
+	union {
+		struct nss_map_t_instance_rule_config_msg create_msg;
+				/**< Create message. */
+		struct nss_map_t_instance_rule_deconfig_msg destroy_msg;
+				/**< Destroy message. */
+		struct nss_map_t_sync_stats_msg stats;
+				/**< Statistics message to host. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving MAP-T messages.
+ *
+ * @datatypes
+ * nss_map_t_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_map_t_msg_callback_t)(void *app_data, struct nss_map_t_msg *msg);
+
+/**
+ * nss_map_t_tx
+ *	Sends a MAP-T message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_map_t_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_map_t_tx(struct nss_ctx_instance *nss_ctx, struct nss_map_t_msg *msg);
+
+/**
+ * nss_map_t_tx_sync
+ *	Sends a MAP-T message synchronously to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_map_t_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_map_t_tx_sync(struct nss_ctx_instance *nss_ctx, struct nss_map_t_msg *msg);
+
+/**
+ * nss_map_t_get_context
+ *	Gets the MAP-T context used in nss_map_t_tx.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_map_t_get_context(void);
+
+/**
+ * Callback function for receiving MAP-T tunnel data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_map_t_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_map_t_register_if
+ *	Registers a MAP-T interface with the NSS for sending and receiving tunnel messages.
+ *
+ * @datatypes
+ * nss_map_t_callback_t \n
+ * nss_map_t_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num          NSS interface number.
+ * @param[in] type            NSS interface type.
+ * @param[in] map_t_callback  Callback for the MAP-T data.
+ * @param[in] msg_callback    Callback for the MAP-T message.
+ * @param[in] netdev          Pointer to the associated network device.
+ * @param[in] features        Data socket buffer types supported by this interface.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_map_t_register_if(uint32_t if_num, uint32_t type, nss_map_t_callback_t map_t_callback,
+					nss_map_t_msg_callback_t msg_callback, struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_map_t_unregister_if
+ *	Deregisters a MAP-T tunnel interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number
+ *
+ * @return
+ * None.
+ */
+extern void nss_map_t_unregister_if(uint32_t if_num);
+
+/**
+ * nss_map_t_msg_init
+ *	Initializes a MAP-T message.
+ *
+ * @datatypes
+ * nss_map_t_msg_init
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    Interface number
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Pointer to the message callback.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_map_t_msg_init(struct nss_map_t_msg *ncm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data);
+
+/**
+ * nss_map_t_register_handler
+ *	Registers the MAP-T debug statistics handler with the NSS.
+ *
+ * @return
+ * None.
+ */
+extern void nss_map_t_register_handler(void);
+
+/**
+ * nss_map_t_instance_debug_stats_get
+ *	Gets debug statistics for a MAP-T instance.
+ *
+ * @param[out] stats_mem  Pointer to the memory address, which must be large enough to
+                         hold all the statistics.
+ *
+ * @return
+ * None.
+ */
+extern void nss_map_t_instance_debug_stats_get(void *stats_mem);
+
+/**
+ * nss_map_t_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_map_t_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_map_t_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_map_t_stats_unregister_notifier(struct notifier_block *nb);
+#endif /*__KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* _NSS_MAP_T_H_ */
diff --git a/qca-nss-drv/exports/nss_match.h b/qca-nss-drv/exports/nss_match.h
new file mode 100644
index 0000000..ae1e308
--- /dev/null
+++ b/qca-nss-drv/exports/nss_match.h
@@ -0,0 +1,296 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_match.h
+ *	NSS match interface definitions.
+ */
+
+#ifndef _NSS_MATCH_H_
+#define _NSS_MATCH_H_
+
+
+/**
+ * @addtogroup nss_match_subsystem
+ * @{
+ */
+
+/**
+ * Maximum number of supported match instances.
+ */
+#define NSS_MATCH_INSTANCE_MAX 4
+
+/**
+ * Maximum number of rules supported per instance.
+ */
+#define NSS_MATCH_INSTANCE_RULE_MAX 32
+
+/**
+ * Maximum number of masksets.
+ */
+#define NSS_MATCH_MASK_MAX 2
+
+/**
+ * Maximum number of words per maskset.
+ */
+#define NSS_MATCH_MASK_WORDS_MAX 4
+
+/**
+ * nss_match_error_type
+ *	Match message error types.
+ */
+typedef enum nss_match_error_type {
+	NSS_MATCH_SUCCESS,			/**< No error. */
+	NSS_MATCH_ERROR_UNKNOWN_MSG,		/**< Message unknown. */
+	NSS_MATCH_ERROR_DSCP_OUTOFBOUND,	/**< DSCP out of bound. */
+	NSS_MATCH_ERROR_OUTER_8021P_OUTOFBOUND,	/**< Outer 802.1p out of bound. */
+	NSS_MATCH_ERROR_INNER_8021P_OUTOFBOUND,	/**< Inner 802.1p out of bound. */
+	NSS_MATCH_ERROR_RULE_ID_OUTOFBOUND,	/**< Rule ID is out of bound. */
+	NSS_MATCH_ERROR_ACTION_TYPE_INVALID,	/**< Invalid action type. */
+	NSS_MATCH_ERROR_RULE_EXISTS,		/**< Rule ID already in use. */
+	NSS_MATCH_ERROR_RULE_DOES_NOT_EXIST,	/**< Rule does not exist. */
+	NSS_MATCH_ERROR_INSTANCE_CONFIGURED,	/**< Error in instance configuration. */
+	NSS_MATCH_ERROR_PROFILE_CONFIG_INVALID,	/**< Invalid profile configuration message. */
+	NSS_MATCH_ERROR_DB_INIT_FAILED,		/**< Database initialization failed. */
+	NSS_MATCH_ERROR_TABLE_ID_OUTOFBOUND,	/**< Table ID is out of bound. */
+	NSS_MATCH_ERROR_RULE_ADD,		/**< Error in adding rule. */
+	NSS_MATCH_ERROR_RULE_DELETE,		/**< Error in deleting rule. */
+	NSS_MATCH_ERROR_TABLE_ADD,		/**< Error in adding table. */
+	NSS_MATCH_ERROR_TABLE_DELETE,		/**< Error in deleting table. */
+	NSS_MATCH_ERROR_MASK_ID_OUTOFBOUND,	/**< Mask ID is out of bound. */
+	NSS_MATCH_ERROR_IFNUM_INVALID,		/**< Next node interface number is invalid. */
+	NSS_MATCH_ERROR_MAX,			/**< Maximum error. */
+} nss_match_status_t;
+
+/**
+ * nss_match_action_type
+ * 	Bit positions for possible actions that can be taken.
+ */
+enum nss_match_action_type {
+	NSS_MATCH_ACTION_NONE,		/**< No action. */
+	NSS_MATCH_ACTION_SETPRIO = 1,	/**< Set given priority to the packet. */
+	NSS_MATCH_ACTION_FORWARD = 2,	/**< Forward the packet to a given node. */
+	NSS_MATCH_ACTION_DROP = 4,	/**< Drop the packet. */
+	NSS_MATCH_ACTION_MAX,		/**< Maximum action type. */
+};
+
+/**
+ * nss_match_profile_type
+ *	Different profile types.
+ */
+enum nss_match_profile_type {
+	NSS_MATCH_PROFILE_TYPE_NONE,
+	NSS_MATCH_PROFILE_TYPE_VOW,		/**< Matches on interface number/DSCP/802.1P. */
+	NSS_MATCH_PROFILE_TYPE_L2,		/**< Matches on interface number/destination MAC/source MAC/Ether type. */
+	NSS_MATCH_PROFILE_TYPE_MAX,		/**< Maximum profile type. */
+};
+
+/**
+ * nss_match_msg_types.
+ *	Message types for match requests and responses.
+ */
+enum nss_match_msg_types {
+	NSS_MATCH_INSTANCE_NONE,	/**< Invalid message. */
+	NSS_MATCH_TABLE_CONFIGURE_MSG,	/**< Instance configure. */
+	NSS_MATCH_ADD_VOW_RULE_MSG,	/**< Insert VoW rule. */
+	NSS_MATCH_ADD_L2_RULE_MSG,	/**< Insert l2 rule. */
+	NSS_MATCH_DELETE_VOW_RULE_MSG,	/**< Delete VoW rule. */
+	NSS_MATCH_DELETE_L2_RULE_MSG,	/**< Delete l2 rule. */
+	NSS_MATCH_STATS_SYNC,		/**< Instance statistics. */
+	NSS_MATCH_MSG_MAX,		/**< Maximum instance messages. */
+};
+
+/**
+ * nss_match_stats_sync
+ *	Synchronization message structure.
+ */
+struct nss_match_stats_sync {
+	struct nss_cmn_node_stats p_stats;			/**< Pnode statistics. */
+	uint32_t hit_count[NSS_MATCH_INSTANCE_RULE_MAX];	/**< Exception events. */
+};
+
+/**
+ * nss_match_profile_configure_msg
+ *	Message for configuring the profile for a match instance.
+ */
+struct nss_match_profile_configure_msg {
+	uint32_t profile_type;				/**< Profile type. */
+	uint32_t valid_mask_flag;			/**< Valid maskset flag. */
+	uint32_t maskset[NSS_MATCH_MASK_MAX][NSS_MATCH_MASK_WORDS_MAX];	/**< Maskset. */
+};
+
+/*
+ * nss_match_rule_action
+ *	Message information for action.
+ */
+struct nss_match_rule_action {
+	uint32_t action_flag;		/**< Action bit map. */
+	uint32_t forward_ifnum;	/**< Next node interface number. */
+	uint16_t setprio;	/**< Priority number to be set in packet. */
+	uint16_t reserved;	/**< Reserved 2 bytes. */
+};
+
+/**
+ * nss_match_rule_vow_msg
+ *	Rule message for VoW profile.
+ */
+struct nss_match_rule_vow_msg {
+	uint16_t rule_id;	/**< Rule ID for the rule. */
+	uint16_t mask_id;       /**< Mask number used for the rule. */
+	struct nss_match_rule_action action;	/**< Action related with the rule. */
+	uint32_t if_num;	/**< Interface number. */
+	uint8_t dscp;		/**< DSCP. */
+	uint8_t outer_8021p;	/**< Outer 802.1p. */
+	uint8_t inner_8021p;	/**< Inner 802.1p. */
+	uint8_t reserved;	/**< Reserved byte. */
+};
+
+/**
+ * nss_match_rule_l2_msg
+ *	Rule message for L2 profile.
+ */
+struct nss_match_rule_l2_msg {
+	uint16_t rule_id;	/**< Rule ID for the rule. */
+	uint16_t mask_id;       /**< Mask number used for the rule. */
+	struct nss_match_rule_action action;	/**< Action related with the rule. */
+	uint32_t if_num;	/**< Interface number. */
+	uint16_t dmac[3];	/**< Destination MAC address. */
+	uint16_t smac[3];	/**< Source MAC address. */
+	uint16_t ethertype;	/**< Ethernet type. */
+};
+
+/**
+ * nss_match_msg
+ *	Data for sending and receiving match messages.
+ */
+struct nss_match_msg {
+	struct nss_cmn_msg cm;	/**< Message header. */
+
+	/**
+	 * Payload of a match message.
+	 */
+	union {
+		struct nss_match_profile_configure_msg configure_msg;	/**< Configure message. */
+		struct nss_match_rule_vow_msg vow_rule;		/**< Insertion or deletion message for VoW profile. */
+		struct nss_match_rule_l2_msg l2_rule;		/**< Insertion or deletion message for l2 profile. */
+		struct nss_match_stats_sync stats;		/**< Instance synchronization statistics. */
+	} msg;	/**< Message payload. */
+};
+
+/**
+ * nss_match_msg_tx_sync
+ *	Sends proxy match messages to the NSS.
+ *
+ * Do not call this function from a softirq or interrupt because it
+ * might sleep if the NSS firmware is busy serving another host thread.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_match_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_match_msg_tx_sync(struct nss_ctx_instance *nss_ctx, struct nss_match_msg *msg);
+
+/**
+ * Callback function for receiving match messages.
+ *
+ * @datatypes
+ * nss_match_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_match_msg_sync_callback_t)(void *app_data, struct nss_match_msg *msg);
+
+/**
+ * nss_match_get_context
+ * 	Returns NSS context of match.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_match_get_context(void);
+
+/**
+ * nss_match_register_instance
+ * 	Registers match dynamic node to NSS.
+ *
+ * @datatypes
+ * nss_match_msg_sync_callback_t
+ *
+ * @param[in] if_num     Interface number of match instance.
+ * @param[in] notify_cb  Notify callback function for the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_match_register_instance(int if_num, nss_match_msg_sync_callback_t notify_cb);
+
+/**
+ * nss_match_unregister_instance
+ * 	Unregisters match dynamic node to NSS.
+ *
+ * @param[in] if_num  Interface number of match instance.
+ *
+ * @return
+ * True if successful, else false.
+ */
+extern bool nss_match_unregister_instance(int if_num);
+
+/**
+ * nss_match_msg_init
+ * 	Initializes a match message.
+ *
+ * @datatypes
+ * nss_match_msg \n
+ * nss_match_msg_sync_callback_t
+ *
+ * @param[in,out] nmm       Pointer to the message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_match_msg_init(struct nss_match_msg *nmm, uint16_t if_num, uint32_t type, uint32_t len,
+		nss_match_msg_sync_callback_t cb, void *app_data);
+
+/**
+ * nss_match_init
+ * 	Initializes match.
+ *
+ * @return
+ * None.
+ */
+extern void nss_match_init(void);
+/**
+ * @}
+ */
+
+#endif /* _NSS_MATCH_H_ */
diff --git a/qca-nss-drv/exports/nss_mirror.h b/qca-nss-drv/exports/nss_mirror.h
new file mode 100644
index 0000000..39853e5
--- /dev/null
+++ b/qca-nss-drv/exports/nss_mirror.h
@@ -0,0 +1,317 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_mirror.h
+ *	NSS mirror interface definitions.
+ */
+
+#ifndef _NSS_MIRROR_H_
+#define _NSS_MIRROR_H_
+
+/**
+ * @addtogroup nss_mirror_subsystem
+ * @{
+ */
+
+/**
+ * Maximum number of supported mirror interfaces.
+ */
+#define NSS_MAX_MIRROR_DYNAMIC_INTERFACES 8
+
+/**
+ * nss_mirror_msg_types
+ *	Message types for mirror interface requests and responses.
+ */
+enum nss_mirror_msg_types {
+	NSS_MIRROR_MSG_CONFIGURE,		/**< Configure message type. */
+	NSS_MIRROR_MSG_ENABLE,			/**< Enable message type. */
+	NSS_MIRROR_MSG_DISABLE,			/**< Disable message type. */
+	NSS_MIRROR_MSG_SET_NEXTHOP,		/**< Set nexthop message type. */
+	NSS_MIRROR_MSG_RESET_NEXTHOP,		/**< Reset nexthop message type. */
+	NSS_MIRROR_MSG_SYNC_STATS,		/**< Statistics synchronization message type. */
+	NSS_MIRROR_MSG_MAX			/**< Maximum message type. */
+};
+
+/**
+ * nss_mirror_pkt_clone_point
+ *	Clone point to use for mirroring the packet.
+ */
+enum nss_mirror_pkt_clone_point {
+	NSS_MIRROR_PKT_CLONE_POINT_DEFAULT = 1,			/**< Clone the packet from the start. */
+	NSS_MIRROR_PKT_CLONE_POINT_BEFORE_PACKET_START,		/**< Clone n-bytes before packet start. */
+	NSS_MIRROR_PKT_CLONE_POINT_AFTER_PACKET_START,		/**< Clone n-bytes after packet start. */
+	NSS_MIRROR_PKT_CLONE_POINT_MAX
+};
+
+/**
+ * nss_mirror_error_type
+ *	Error types for mirror responses to messages from the host.
+ */
+enum nss_mirror_error_type {
+	NSS_MIRROR_ERROR_TYPE_NONE,			/**< No error. */
+	NSS_MIRROR_ERROR_TYPE_NO_MEMORY,		/**< No memory to copy. */
+	NSS_MIRROR_ERROR_TYPE_TX_FAILURE,		/**< Transmit failure. */
+	NSS_MIRROR_ERROR_TYPE_BAD_PARAM,		/**< Bad parameter. */
+	NSS_MIRROR_ERROR_TYPE_BAD_CLONE_POINT,		/**< Bad packet clone point. */
+	NSS_MIRROR_ERROR_TYPE_INSTANCE_CONFIGURED,	/**< Instance already active. */
+	NSS_MIRROR_ERROR_TYPE_INSTANCE_DISABLED,	/**< Instance already disabled. */
+	NSS_MIRROR_ERROR_TYPE_BAD_NEXTHOP,		/**< Incorrect nexthop interface. */
+	NSS_MIRROR_ERROR_TYPE_NEXTHOP_CONFIGURED,	/**< Nexthop already interface. */
+	NSS_MIRROR_ERROR_TYPE_NEXTHOP_RESET,		/**< Nexthop already reset. */
+	NSS_MIRROR_ERROR_TYPE_UNKNOWN_MSG,		/**< Unknown message. */
+	NSS_MIRROR_ERROR_TYPE_MAX,			/**< Maximum message type. */
+};
+
+/**
+ * nss_mirror_stats
+ *	Mirror interface debug statistics.
+ */
+enum nss_mirror_stats {
+	NSS_MIRROR_STATS_PKTS,			/**< Number of packets exceptioned to host. */
+	NSS_MIRROR_STATS_BYTES,			/**< Number of bytes exceptioned to host. */
+	NSS_MIRROR_STATS_TX_SEND_FAIL,		/**< Transmit send failures. */
+	NSS_MIRROR_STATS_DEST_LOOKUP_FAIL,	/**< Destination lookup failures. */
+	NSS_MIRROR_STATS_MEM_ALLOC_FAIL,	/**< Memory allocation failures. */
+	NSS_MIRROR_STATS_COPY_FAIL,		/**< Copy failures. */
+	NSS_MIRROR_STATS_MAX			/**< Maximum statistics count. */
+};
+
+/**
+ * nss_mirror_configure_msg
+ *	Mirror interface configuration information.
+ */
+struct nss_mirror_configure_msg {
+	uint32_t pkt_clone_point;	/**< Point in the packet to copy from. */
+	uint16_t pkt_clone_size;	/**< Number of bytes to copy. */
+	uint16_t pkt_clone_offset;	/**< Copy offset. */
+};
+
+/**
+ * nss_mirror_set_nexthop_msg
+ *	Mirror interface set nexthop information.
+ */
+struct nss_mirror_set_nexthop_msg {
+	uint32_t if_num;		/**< Nexthop interface number. */
+};
+
+/**
+ * nss_mirror_node_stats
+ *	Mirror interface debug statistics structure.
+ */
+struct nss_mirror_node_stats {
+	uint32_t mirror_pkts;		/**< Number of packets exceptioned to host. */
+	uint32_t mirror_bytes;		/**< Number of bytes exceptioned to host. */
+	uint32_t tx_send_fail;		/**< Transmit send failures. */
+	uint32_t dest_lookup_fail;	/**< Destination lookup failures. */
+	uint32_t mem_alloc_fail;	/**< Memory allocation failures. */
+	uint32_t copy_fail;		/**< Copy failures. */
+	uint32_t bad_param;		/**< Bad parameter. */
+};
+
+/**
+ * nss_mirror_stats_sync_msg
+ *	Message information for mirror interface synchronization statistics.
+ */
+struct nss_mirror_stats_sync_msg {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics. */
+	struct nss_mirror_node_stats mirror_stats;	/**< Debug statistics for mirror. */
+};
+
+/**
+ * nss_mirror_stats_notification
+ *	Mirror transmission statistics structure.
+ */
+struct nss_mirror_stats_notification {
+	uint64_t stats_ctx[NSS_MIRROR_STATS_MAX];	/**< Context transmission statistics. */
+	uint32_t core_id;				/**< Core ID. */
+	uint32_t if_num;				/**< Interface number. */
+};
+
+/**
+ * nss_mirror_msg
+ *	Data for sending and receiving mirror interface messages.
+ */
+struct nss_mirror_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a mirror interface message.
+	 */
+	union {
+		struct nss_mirror_configure_msg config;
+				/**< Mirror interface configure message. */
+		struct nss_mirror_set_nexthop_msg nexthop;
+				/**< Mirror interface set nexthop message. */
+		struct nss_mirror_stats_sync_msg stats;
+				/**< Statistics message to host. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving mirror instance data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_mirror_data_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for receiving mirror interface messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_mirror_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * nss_mirror_get_context
+ *	Gets the mirror interface context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_mirror_get_context(void);
+
+/**
+ * nss_mirror_tx_msg
+ *	Sends mirror interface messages to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_mirror_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_mirror_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_mirror_msg *msg);
+
+/**
+ * nss_mirror_tx_msg_sync
+ *	Sends a mirror interface message to the NSS synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_mirror_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_mirror_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_mirror_msg *msg);
+
+/**
+ * nss_mirror_unregister_if
+ *	Deregisters a mirror interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ */
+extern void nss_mirror_unregister_if(uint32_t if_num);
+
+/**
+ * nss_mirror_register_if
+ *	Registers a mirror interface with the NSS for sending and receiving messages.
+ *
+ * @datatypes
+ * nss_mirror_data_callback_t \n
+ * nss_mirror_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num          NSS interface number.
+ * @param[in] data_callback   Callback for the mirror interface data.
+ * @param[in] event_callback    Callback for the mirror interface message.
+ * @param[in] netdev          Pointer to the associated network device.
+ * @param[in] features        Data socket buffer types supported by this interface.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_mirror_register_if(uint32_t if_num,
+		nss_mirror_data_callback_t data_callback,
+		nss_mirror_msg_callback_t event_callback,
+		struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_mirror_verify_if_num
+ *	Verify whether the interface is an mirror interface or not.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * True if the interface is an mirror interface.
+ */
+extern bool nss_mirror_verify_if_num(uint32_t if_num);
+
+/**
+ * nss_mirror_register_handler
+ *	Registers the mirror interface debug statistics handler with the NSS.
+ *
+ * @return
+ * None.
+ */
+extern void nss_mirror_register_handler(void);
+
+/**
+ * nss_mirror_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_mirror_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * nss_mirror_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_mirror_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * @}
+ */
+#endif
diff --git a/qca-nss-drv/exports/nss_n2h.h b/qca-nss-drv/exports/nss_n2h.h
new file mode 100644
index 0000000..1613f41
--- /dev/null
+++ b/qca-nss-drv/exports/nss_n2h.h
@@ -0,0 +1,572 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_n2h.h
+ *	NSS to HLOS interface definitions.
+ */
+
+#ifndef __NSS_N2H_H
+#define __NSS_N2H_H
+
+/**
+ * @addtogroup nss_n2h_subsystem
+ * @{
+ */
+
+#define MAX_PAGES_PER_MSG 32	/**< Maximum number of pages per message. */
+#define NSS_N2H_RPS_PRI_DEFAULT -1	/**< Default RPS priority mapping. */
+
+/**
+ * nss_n2h_payload_info
+ *	Payload configuration based on the watermark.
+ */
+struct nss_n2h_payload_info {
+	uint32_t pool_size;		/**< Empty buffer pool size. */
+
+	/**
+	 * Low watermark.
+	 * Set this field to 0 for the system to automatically determine the watermark.
+	 */
+	uint32_t low_water;
+
+	/**
+	 * High watermark.
+	 * Set this field to 0 for the system to automatically determine the watermark.
+	 */
+	uint32_t high_water;
+};
+
+#ifdef __KERNEL__ /* only kernel will use. */
+
+/**
+ * nss_n2h_cfg_pvt
+ *	N2H private data configuration.
+ */
+struct nss_n2h_cfg_pvt {
+	struct semaphore sem;					/**< Semaphore for SMP synchronization. */
+	struct completion complete;				/**< Waits for the NSS to process the message. */
+	struct nss_n2h_payload_info empty_buf_pool_info;	/**< Empty buffer pool information. */
+	struct nss_n2h_payload_info empty_paged_buf_pool_info;	/**< Paged buffer pool information. */
+	int wifi_pool;						/**< Size of the empty Wi-Fi buffer pool. */
+	int response;						/**< Response from the firmware. */
+};
+
+#endif /*__KERNEL__ */
+
+/**
+ * nss_n2h_stats_types
+ *	N2H node statistics.
+ */
+enum nss_n2h_stats_types {
+	NSS_N2H_STATS_QUEUE_DROPPED = NSS_STATS_NODE_MAX,
+		/**< Number of packets dropped because the exception queue is too full. */
+	NSS_N2H_STATS_TOTAL_TICKS,	/**< Total clock ticks spend inside the N2H. */
+	NSS_N2H_STATS_WORST_CASE_TICKS,	/**< Worst case iteration of the exception path in ticks. */
+	NSS_N2H_STATS_ITERATIONS,	/**< Number of iterations around the N2H. */
+	NSS_N2H_STATS_PBUF_OCM_TOTAL_COUNT,	/**< Number of pbuf OCM total count. */
+	NSS_N2H_STATS_PBUF_OCM_FREE_COUNT,	/**< Number of pbuf OCM free count. */
+	NSS_N2H_STATS_PBUF_OCM_ALLOC_FAILS_WITH_PAYLOAD,
+					/**< Number of pbuf OCM allocations that have failed with payload. */
+	NSS_N2H_STATS_PBUF_OCM_ALLOC_FAILS_NO_PAYLOAD,
+					/**< Number of pbuf OCM allocations that have failed without payload. */
+	NSS_N2H_STATS_PBUF_DEFAULT_TOTAL_COUNT,	/**< Number of pbuf default total count. */
+	NSS_N2H_STATS_PBUF_DEFAULT_FREE_COUNT,	/**< Number of pbuf default free count. */
+	NSS_N2H_STATS_PBUF_DEFAULT_ALLOC_FAILS_WITH_PAYLOAD,
+					/**< Number of pbuf default allocations that have failed with payload. */
+	NSS_N2H_STATS_PBUF_DEFAULT_ALLOC_FAILS_NO_PAYLOAD,
+	/**< Number of pbuf default allocations that have failed without payload. */
+
+	NSS_N2H_STATS_PAYLOAD_ALLOC_FAILS,	/**< Number of pbuf allocations that have failed because there were no free payloads. */
+	NSS_N2H_STATS_PAYLOAD_FREE_COUNT,	/**< Number of free payloads that exist. */
+
+	NSS_N2H_STATS_H2N_CONTROL_PACKETS,	/**< Control packets received from HLOS. */
+	NSS_N2H_STATS_H2N_CONTROL_BYTES,	/**< Control bytes received from HLOS. */
+	NSS_N2H_STATS_N2H_CONTROL_PACKETS,	/**< Control packets sent to HLOS. */
+	NSS_N2H_STATS_N2H_CONTROL_BYTES,	/**< Control bytes sent to HLOS. */
+
+	NSS_N2H_STATS_H2N_DATA_PACKETS,		/**< Data packets received from HLOS. */
+	NSS_N2H_STATS_H2N_DATA_BYTES,		/**< Data bytes received from HLOS. */
+	NSS_N2H_STATS_N2H_DATA_PACKETS,		/**< Data packets sent to HLOS. */
+	NSS_N2H_STATS_N2H_DATA_BYTES,		/**< Data bytes sent to HLOS. */
+	NSS_N2H_STATS_N2H_TOT_PAYLOADS,		/**< Number of payloads in NSS. */
+	NSS_N2H_STATS_N2H_INTERFACE_INVALID,	/**< Number of bad interface access. */
+	NSS_N2H_STATS_ENQUEUE_RETRIES,		/**< Number of enqueue retries by N2H. */
+
+	NSS_N2H_STATS_MAX,			/**< Maximum message type. */
+};
+
+/**
+ * nss_n2h_metadata_types
+ *	Message types for N2H requests and responses.
+ */
+enum nss_n2h_metadata_types {
+	NSS_RX_METADATA_TYPE_N2H_STATS_SYNC = 0,
+	NSS_TX_METADATA_TYPE_N2H_RPS_CFG,
+	NSS_TX_METADATA_TYPE_N2H_EMPTY_POOL_BUF_CFG,
+	NSS_TX_METADATA_TYPE_N2H_FLUSH_PAYLOADS,
+	NSS_TX_METADATA_TYPE_N2H_MITIGATION_CFG,
+	NSS_METADATA_TYPE_N2H_ADD_BUF_POOL,
+	NSS_TX_METADATA_TYPE_SET_WATER_MARK,
+	NSS_TX_METADATA_TYPE_GET_WATER_MARK,
+	NSS_TX_METADATA_TYPE_N2H_WIFI_POOL_BUF_CFG,
+	NSS_TX_DDR_INFO_VIA_N2H_CFG,
+	NSS_TX_METADATA_TYPE_N2H_SET_PNODE_QUEUE_CFG,
+	NSS_TX_METADATA_TYPE_N2H_EMPTY_PAGED_POOL_BUF_CFG,
+	NSS_TX_METADATA_TYPE_SET_PAGED_WATER_MARK,
+	NSS_TX_METADATA_TYPE_GET_PAGED_WATER_MARK,
+	NSS_TX_METADATA_TYPE_N2H_RPS_PRI_MAP_CFG,
+	NSS_TX_METADATA_TYPE_N2H_QUEUE_LIMIT_CFG,
+	NSS_TX_METADATA_TYPE_N2H_PAGED_BUFFER_POOL_INIT,
+	NSS_TX_METADATA_TYPE_N2H_HOST_BACK_PRESSURE_CFG,
+	NSS_METADATA_TYPE_N2H_MAX,
+};
+
+/*
+ * nss_n2h_error_types
+ *	N2H error types.
+ */
+enum nss_n2h_error_types {
+	N2H_EUNKNOWN = 1,
+	N2H_ALREADY_CFG,
+	N2H_LOW_WATER_MIN_INVALID,
+	N2H_HIGH_WATER_LESS_THAN_LOW,
+	N2H_HIGH_WATER_LIMIT_INVALID,
+	N2H_LOW_WATER_LIMIT_INVALID,
+	N2H_WATER_MARK_INVALID,
+	N2H_EMPTY_BUFFER_TOO_HIGH,
+	N2H_EMPTY_BUFFER_TOO_LOW,
+	N2H_MMU_ENTRY_IS_INVALID,
+	N2H_PN_QUEUE_SET_FAILED,
+	N2H_PAGES_PER_MSG_EXCEEDED,
+	N2H_RPS_PRI_MAP_TOO_HIGH,
+};
+
+/**
+ * nss_n2h_stats_notification
+ *	N2H statistics structure.
+ */
+struct nss_n2h_stats_notification {
+	uint32_t core_id;			/**< Core ID. */
+	uint64_t n2h_stats[NSS_N2H_STATS_MAX];	/**< N2H statistics. */
+	uint64_t drv_stats[NSS_STATS_DRV_MAX];	/**< Driver statistics. */
+};
+
+/**
+ * nss_n2h_rps
+ *	N2H RPS configuration.
+ */
+struct nss_n2h_rps {
+	uint32_t enable;	/**< Enable RPS. */
+};
+
+/**
+ * nss_n2h_rps_pri_map
+ *	N2H priority configuration.
+ *
+ * This is used to direct packets with a given priority to a specific host CPU.
+ * A value of -1 in pri_map[pri] is treated as invalid and will not override
+ * RPS for that priority.
+ */
+struct nss_n2h_rps_pri_map {
+	int32_t pri_map[NSS_MAX_NUM_PRI];	/**< Priority to RPS map. */
+};
+
+/**
+ * nss_n2h_mitigation
+ *	N2H mitigation configuration.
+ */
+struct nss_n2h_mitigation {
+	uint32_t enable;	/**< Enable NSS mitigation. */
+};
+
+/**
+ * nss_n2h_buf_pool
+ *	N2H buffer pool configuration.
+ */
+struct nss_n2h_buf_pool {
+	uint32_t nss_buf_page_size;	/**< Size of the buffer page. */
+	uint32_t nss_buf_num_pages;	/**< Number of buffer pages. */
+
+	uint32_t nss_buf_pool_addr[MAX_PAGES_PER_MSG];
+			/**< Buffer addresses. */
+	nss_ptr_t nss_buf_pool_vaddr[MAX_PAGES_PER_MSG];
+			/**< Virtual addresses of the buffers. */
+#ifndef __LP64__
+	uint32_t padding[MAX_PAGES_PER_MSG];
+			/**< Pad to fit 64 bits, do not reuse. */
+#endif
+};
+
+/**
+ * nss_n2h_pnode_queue_config
+ *	Queue configuration command for pnodes in NSS.
+ */
+struct nss_n2h_pnode_queue_config {
+	uint8_t mq_en;		/**< Enable multiple queues. */
+	uint8_t reserved[3];	/**< Reserved for alignment. */
+	uint16_t qlimits[NSS_MAX_NUM_PRI];
+				/**< Limits of each queue. */
+#if (NSS_MAX_NUM_PRI & 1)
+	uint16_t reserved2;
+#endif
+};
+
+/**
+ * nss_n2h_empty_pool_buf
+ *	Old way of setting the number of empty pool buffers (payloads).
+ *
+ * The NSS firmware sets the low watermark to n -- ring_size, and the high
+ * watermark to n + ring_size.
+ */
+struct nss_n2h_empty_pool_buf {
+	uint32_t pool_size;		/**< Size of the empty buffer pool. */
+};
+
+/**
+ * nss_n2h_water_mark
+ *	New way of setting the low and high watermarks in the NSS firmware.
+ */
+struct nss_n2h_water_mark {
+	/**
+	 * Low watermark.
+	 * Lower threshold for the number of payloads that can be held by NSS firmware.
+	 * Setting this value to 0 gets the system to automatically determine the watermark.
+	 */
+	uint32_t low_water;
+
+	/**
+	 * High watermark.
+	 * Upper threshold for the number of paylods that be held by the NSS firmware.
+	 * Setting this value to 0 gets the system to automatically determine the watermark.
+	 */
+	uint32_t high_water;
+};
+
+/**
+ * nss_n2h_flush_payloads
+ *	Flush payload configuration.
+ */
+struct nss_n2h_flush_payloads {
+	uint32_t reserved;		/**< Reserved for future use. */
+};
+
+/**
+ * nss_n2h_wifi_payloads
+ *	Payloads required for Wi-Fi offloading.
+ */
+struct nss_n2h_wifi_payloads {
+	uint32_t payloads;	/**< Number of payloads for Wi-Fi use. */
+};
+
+/**
+ * nss_n2h_pbuf_mgr_stats
+ *	Payload buffer manager statistics.
+ */
+struct nss_n2h_pbuf_mgr_stats {
+	uint32_t pbuf_total_count;	/**< Total number of buffers, free or in use. */
+	uint32_t pbuf_free_count;	/**< Number of currently free buffers. */
+	uint32_t pbuf_alloc_fails_with_payload;
+					/**< Number of buffer allocation failures. */
+	uint32_t pbuf_alloc_fails_no_payload;
+					/**< Number of buffer allocation failures without payload. */
+};
+
+/**
+ * nss_n2h_paged_buffer_pool_init
+ *	Paged buffer configuration initialization.
+ */
+struct nss_n2h_paged_buffer_pool_init {
+	uint32_t reserved;		/**< Reserved for future use. */
+};
+
+/**
+ * nss_n2h_stats_sync
+ *	N2H synchronization statistics.
+ */
+struct nss_n2h_stats_sync {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics. */
+	uint32_t queue_dropped;
+			/**< Number of packets dropped because the N2H queue is too full. */
+	uint32_t total_ticks;		/**< Total clock ticks spent inside the N2H handler. */
+	uint32_t worst_case_ticks;	/**< Worst case iteration of the N2H handler in ticks. */
+	uint32_t iterations;		/**< Number of iterations around the N2H handler. */
+
+	struct nss_n2h_pbuf_mgr_stats pbuf_ocm_stats;
+			/**< Statistics for on-chip memory payload buffers. */
+	struct nss_n2h_pbuf_mgr_stats pbuf_default_stats;
+			/**< Statistics for DDR memory payload buffers. */
+
+	uint32_t payload_alloc_fails;	/**< Number of payload allocation failures. */
+	uint32_t payload_free_count;	/**< Number of free payloads. */
+
+	uint32_t h2n_ctrl_pkts;		/**< Control packets received from the HLOS. */
+	uint32_t h2n_ctrl_bytes;	/**< Control bytes received from the HLOS. */
+	uint32_t n2h_ctrl_pkts;		/**< Control packets sent to the HLOS. */
+	uint32_t n2h_ctrl_bytes;	/**< Control bytes sent to the HLOS. */
+
+	uint32_t h2n_data_pkts;		/**< Data packets received from the HLOS. */
+	uint32_t h2n_data_bytes;	/**< Data bytes received from the HLOS. */
+	uint32_t n2h_data_pkts;		/**< Data packets sent to the HLOS. */
+	uint32_t n2h_data_bytes;	/**< Data bytes sent to the HLOS. */
+	uint32_t tot_payloads;		/**< Total number of payloads in the NSS firmware. */
+
+	/**
+	 * Number of data packets with invalid interface received from the host.
+	 */
+	uint32_t data_interface_invalid;
+	uint32_t enqueue_retries;	/**< Number of times N2H retried enqueue to next node. */
+};
+
+/**
+ * nss_mmu_ddr_info
+ *	System DDR memory information required by the firmware MMU to set range guards.
+ */
+struct nss_mmu_ddr_info {
+	uint32_t ddr_size;	/**< Total size of the DDR. */
+	uint32_t start_address;	/**< System start address. */
+	uint32_t num_active_cores;
+				/**< Number of active cores. */
+	uint32_t nss_ddr_size;	/**< Total memory for NSS SoC. */
+};
+
+/**
+ * nss_n2h_queue_limit_config
+ *	Queue length limit for N2H node.
+ */
+struct nss_n2h_queue_limit_config {
+	uint32_t qlimit;	/**< Queue length size. */
+};
+
+/**
+ * nss_n2h_host_back_pressure
+ *	Host back pressure configuration.
+ */
+struct nss_n2h_host_back_pressure {
+	uint32_t enable;		/**< Enable host back pressure. */
+};
+
+/**
+ * nss_n2h_msg
+ *	Data for sending and receiving N2H messages.
+ */
+struct nss_n2h_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of an N2H message.
+	 */
+	union {
+		struct nss_n2h_stats_sync stats_sync;
+				/**< N2H statistics synchronization. */
+		struct nss_n2h_rps rps_cfg;
+				/**< RPS configuration. */
+		struct nss_n2h_rps_pri_map rps_pri_map;
+				/**< RPS priority map. */
+		struct nss_n2h_empty_pool_buf empty_pool_buf_cfg;
+				/**< Empty pool buffer configuration. */
+		struct nss_n2h_empty_pool_buf empty_paged_pool_buf_cfg;
+				/**< Empty paged pool buffer configuration. */
+		struct nss_n2h_flush_payloads flush_payloads;
+				/**< Flush payloads present in the NSS. */
+		struct nss_n2h_mitigation mitigation_cfg;
+				/**< Mitigation configuration. */
+		struct nss_n2h_buf_pool buf_pool;
+				/**< Pool buffer coniguration. */
+		struct nss_n2h_water_mark wm;
+				/**< Sets low and high watermarks. */
+		struct nss_n2h_water_mark wm_paged;
+				/**< Sets low and high watermarks for paged pool. */
+		struct nss_n2h_payload_info payload_info;
+				/**< Gets the payload information. */
+		struct nss_n2h_payload_info paged_payload_info;
+				/**< Gets the paged payload information. */
+		struct nss_n2h_wifi_payloads wp;
+				/**< Sets the number of Wi-Fi payloads. */
+		struct nss_mmu_ddr_info mmu;
+				/**< Gets the DDR size and start address to configure the MMU. */
+		struct nss_n2h_pnode_queue_config pn_q_cfg;
+				/**< Pnode queueing configuration. */
+		struct nss_n2h_queue_limit_config ql_cfg;
+				/**< Queue limit configuration. */
+		struct nss_n2h_paged_buffer_pool_init paged_buffer_pool_init;
+				/**< Paged buffer pool initialization. */
+		struct nss_n2h_host_back_pressure host_bp_cfg;
+				/**< Host back pressure configuration. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving N2H messages.
+ *
+ * @datatypes
+ * nss_n2h_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the N2H message.
+ */
+typedef void (*nss_n2h_msg_callback_t)(void *app_data, struct nss_n2h_msg *msg);
+
+/**
+ * nss_n2h_tx_msg
+ *	Sends messages to the N2H package.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_n2h_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] nnm      Pointer to the N2H message.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_n2h_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_n2h_msg *nnm);
+
+/**
+ * nss_n2h_single_core_register_sysctl
+ *	Registers the N2H sysctl entry to the sysctl tree for a single-core system.
+ *
+ * @return
+ * None.
+ */
+extern void nss_n2h_single_core_register_sysctl(void);
+
+/**
+ * nss_n2h_multi_core_register_sysctl
+ *	Registers the N2H sysctl entry to the sysctl tree for a multi-core system.
+ *
+ * @return
+ * None.
+ */
+extern void nss_n2h_multi_core_register_sysctl(void);
+
+/**
+ * nss_n2h_unregister_sysctl
+ *	Deregisters the N2H sysctl entry from the sysctl tree.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The system control must have been previously registered.
+ */
+extern void nss_n2h_unregister_sysctl(void);
+
+/**
+ * nss_n2h_flush_payloads
+ *	Sends flush payloads message to NSS
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_n2h_flush_payloads(struct nss_ctx_instance *nss_ctx);
+
+/**
+ * nss_n2h_msg_init
+ *	Initializes messages from the host to the NSS.
+ *
+ * @datatypes
+ * nss_n2h_msg \n
+ * nss_n2h_msg_callback_t
+ *
+ * @param[in,out] nim       Pointer to the NSS interface message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_n2h_msg_init(struct nss_n2h_msg *nim, uint16_t if_num, uint32_t type, uint32_t len,
+			nss_n2h_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_n2h_update_queue_config_sync
+ *	Synchrounous method to update pnode queue configuration to NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] mq_en    Enable multiple pnode queues.
+ * @param[in] qlimits  Maximum number of packets in each queues.
+ *
+ * @return
+ * Status of the configuration update operation.
+ */
+extern nss_tx_status_t nss_n2h_update_queue_config_sync(struct nss_ctx_instance *nss_ctx, bool mq_en, uint16_t *qlimits);
+
+/**
+ * nss_n2h_update_queue_config_async
+ *	Asynchrounous method to update pnode queue configuration to NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] mq_en    Enable multiple pnode queues.
+ * @param[in] qlimits  Maximum number of packets in each queues.
+ *
+ * @return
+ * Status of the configuration update operation.
+ */
+extern nss_tx_status_t nss_n2h_update_queue_config_async(struct nss_ctx_instance *nss_ctx, bool mq_en, uint16_t *qlimits);
+
+#ifdef __KERNEL__ /* only kernel will use. */
+
+/**
+ * nss_n2h_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_n2h_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_n2h_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_n2h_stats_unregister_notifier(struct notifier_block *nb);
+
+#endif /*__KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_N2H_H */
diff --git a/qca-nss-drv/exports/nss_oam.h b/qca-nss-drv/exports/nss_oam.h
new file mode 100644
index 0000000..af25e37
--- /dev/null
+++ b/qca-nss-drv/exports/nss_oam.h
@@ -0,0 +1,145 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_oam.h
+ *	NSS OAM - Operations, Administration and Maintenance Service
+ */
+
+#ifndef __NSS_OAM_H
+#define __NSS_OAM_H
+
+/**
+ * @addtogroup nss_oam_subsystem
+ * @{
+ */
+
+#define NSS_OAM_FW_VERSION_LEN	132	/**< Size of the OAM firmware version. */
+
+/**
+ * nss_oam_msg_types
+ *	OAM command types.
+ *
+ * The OAM proxy sends these command messages to the NSS OAM server via the OAM adapter.
+ */
+enum nss_oam_msg_types {
+	NSS_OAM_MSG_TYPE_NONE,
+	NSS_OAM_MSG_TYPE_GET_FW_VER,
+	NSS_OAM_MSG_TYPE_MAX,
+};
+
+/**
+ * nss_oam_error
+ *	OAM error responses.
+ */
+enum nss_oam_error {
+	NSS_OAM_ERROR_NONE,
+	NSS_OAM_ERROR_INVAL_MSG_TYPE,
+	NSS_OAM_ERROR_INVAL_MSG_LEN,
+	NSS_OAM_ERROR_MAX,
+};
+
+/**
+ * nss_oam_fw_ver
+ *	OAM firmware version.
+ */
+struct nss_oam_fw_ver {
+	uint8_t string[NSS_OAM_FW_VERSION_LEN];	/**< OAM firmware version. */
+};
+
+/**
+ * nss_oam_msg
+ *	Data for sending and receiving OAM messages.
+ */
+struct nss_oam_msg {
+	struct nss_cmn_msg cm;	/**< Common message header. */
+
+	/**
+	 * Payload of an OAM message.
+	 */
+	union {
+		struct nss_oam_fw_ver fw_ver;
+				/**< Firmware version. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving OAM messages.
+ *
+ * @datatypes
+ * nss_oam_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_oam_msg_callback_t)(void *app_data, struct nss_oam_msg *msg);
+
+/**
+ * nss_oam_tx_msg
+ *	Transmits an OAM message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_oam_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation
+ */
+extern nss_tx_status_t nss_oam_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_oam_msg *msg);
+
+/**
+ * nss_oam_notify_register
+ *	Registers a notifier callback with the NSS for sending and receiving OAM messages.
+ *
+ * @datatypes
+ * nss_oam_msg_callback_t
+ *
+ * @param[in] cb        Callback function for the message.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_oam_notify_register(nss_oam_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_oam_notify_unregister
+ *	Deregisters an OAM message notifier callback from the NSS.
+ *
+ * @return
+ * None.
+ */
+extern void nss_oam_notify_unregister(void);
+
+/**
+ * nss_register_oam_if
+ *	Registers the OAM interface handler with the NSS.
+ *
+ * @param[in] if_number  Interface number of the OAM interface.
+ *
+ * @return
+ * Boolean status of handler registration
+ */
+extern bool nss_register_oam_if(uint16_t if_number);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_OAM_H */
diff --git a/qca-nss-drv/exports/nss_phy_if.h b/qca-nss-drv/exports/nss_phy_if.h
new file mode 100644
index 0000000..80382fe
--- /dev/null
+++ b/qca-nss-drv/exports/nss_phy_if.h
@@ -0,0 +1,67 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_phy_if.h
+ *	NSS physical interface definitions.
+ */
+
+#ifndef __NSS_PHY_IF_H
+#define __NSS_PHY_IF_H
+
+/**
+ * @addtogroup nss_driver_subsystem
+ * @{
+ */
+
+/**
+ * nss_phys_if_reset_nexthop
+ *	De-configure nexthop for an interface.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] if_num   Network physical interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_phys_if_reset_nexthop(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+
+/**
+ * nss_phys_if_set_nexthop
+ *	Configure nexthop for an interface.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] if_num   Network physical interface number.
+ * @param[in] nexthop   Network physical or virtual interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_phys_if_set_nexthop(struct nss_ctx_instance *nss_ctx, uint32_t if_num, uint32_t nexthop);
+
+/**
+ * @}
+ */
+
+#endif /*  __NSS_PHY_IF_H */
diff --git a/qca-nss-drv/exports/nss_pm.h b/qca-nss-drv/exports/nss_pm.h
new file mode 100644
index 0000000..8e0cce8
--- /dev/null
+++ b/qca-nss-drv/exports/nss_pm.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * @file nss_pm.h
+ *	NSS power management definitions.
+ */
+
+#ifndef __NSS_PM_H
+#define __NSS_PM_H
+
+/**
+ * @addtogroup nss_pm_subsystem
+ * @{
+ */
+
+/**
+ * nss_pm_client
+ *	Power management (PM) clients.
+ *
+ * These clients can query for bus or clock performance levels.
+ */
+typedef enum nss_pm_client {
+	NSS_PM_CLIENT_GMAC,
+	NSS_PM_CLIENT_CRYPTO,
+	NSS_PM_CLIENT_NETAP,
+	NSS_PM_MAX_CLIENTS,
+} nss_pm_client_t;
+
+/**
+ * nss_pm_perf_level
+ *	Performance levels.
+ *
+ * This enumeration is passed as a parameter to NSS PM performance-level
+ * requests.
+ */
+typedef enum nss_pm_perf_level {
+	NSS_PM_PERF_LEVEL_SUSPEND = 0,
+	NSS_PM_PERF_LEVEL_IDLE,
+	NSS_PM_PERF_LEVEL_NOMINAL,
+	NSS_PM_PERF_LEVEL_TURBO,
+	NSS_PM_PERF_MAX_LEVELS,
+} nss_pm_perf_level_t;
+
+/**
+ * nss_pm_interface_status_t
+ *	Status of the PM client interface.
+ */
+typedef enum {
+	NSS_PM_API_SUCCESS = 0,
+	NSS_PM_API_FAILED,
+} nss_pm_interface_status_t;
+
+/**
+ * nss_pm_client_register
+ *	Registers a power management driver client.
+ *
+ * @datatypes
+ * nss_pm_client_t
+ *
+ * @param[in] client_id  ID of the client driver.
+ *
+ * @return
+ * None.
+ */
+extern void *nss_pm_client_register(nss_pm_client_t client_id);
+
+/**
+ * nss_pm_client_unregister
+ *	Deregisters a power management driver client.
+ *
+ * @datatypes
+ * nss_pm_client_t
+ *
+ * @param[in] client_id  ID of the client driver.
+ *
+ * @return
+ * None.
+ */
+int nss_pm_client_unregister(nss_pm_client_t client_id);
+
+/**
+ * nss_pm_set_perf_level
+ *	Updates the bus bandwidth level for a client.
+ *
+ * @datatypes
+ * nss_pm_perf_level_t
+ *
+ * @param[in,out] handle  Handle of the client.
+ * @param[in,out] lvl     Performance level.
+ *
+ * @return
+ * None.
+ */
+extern nss_pm_interface_status_t nss_pm_set_perf_level(void *handle, nss_pm_perf_level_t lvl);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_PM_H */
diff --git a/qca-nss-drv/exports/nss_portid.h b/qca-nss-drv/exports/nss_portid.h
new file mode 100644
index 0000000..61e8ac6
--- /dev/null
+++ b/qca-nss-drv/exports/nss_portid.h
@@ -0,0 +1,284 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2017 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_portid.h
+ *	NSS Port ID interface definitions.
+ */
+
+#ifndef __NSS_PORTID_H
+#define __NSS_PORTID_H
+
+/**
+ * @addtogroup nss_portid_subsystem
+ * @{
+ */
+
+/**
+ * Maximum number of ports on the S17c switch chip.
+ *
+ * If a new switch has more ports than S17c, this value must be updated.
+ */
+#define NSS_PORTID_MAX_SWITCH_PORT 7
+
+/**
+ * nss_portid_msg_types
+ *	Message types for port ID requests and responses.
+ */
+enum nss_portid_msg_types {
+	NSS_PORTID_CONFIGURE_MSG,
+	NSS_PORTID_UNCONFIGURE_MSG,
+	NSS_PORTID_STATS_SYNC_MSG,
+	NSS_PORTID_MAX_MSG_TYPE
+};
+
+/**
+ * nss_portid_configure_msg
+ *	Message information for configuring a port ID.
+ */
+struct nss_portid_configure_msg {
+	uint32_t port_if_num;
+			/**< Interface number corresponding to the port ID of the device. */
+	uint8_t port_id;		/**< ID of the mapped switch port. */
+	uint8_t gmac_id;		/**< ID of the mapped GMAC interface. */
+	uint8_t reserved[2];		/**< Reserved for word alignment. */
+};
+
+/**
+ * nss_portid_unconfigure_msg
+ *	Message information for deleting a port ID.
+ */
+struct nss_portid_unconfigure_msg {
+	uint32_t port_if_num;
+			/**< Interface number corresponding to the port ID of the device. */
+	uint8_t port_id;		/**< ID of the mapped switch port. */
+	uint8_t reserved[3];		/**< Reserved for word alignment. */
+};
+
+/**
+ * nss_portid_stats_sync_msg
+ *	Message information for port ID synchronization statistics.
+ */
+struct nss_portid_stats_sync_msg {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics. */
+	uint32_t rx_invalid_header;		/**< Rx with an invalid header. */
+	uint8_t port_id;			/**< ID of the mapped switch port. */
+	uint8_t reserved[3];			/**< Reserved for word alignment. */
+};
+
+/**
+ * nss_portid_msg
+ *	Data for sending and receiving port ID messages.
+ */
+struct nss_portid_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a port ID message.
+	 */
+	union {
+		struct nss_portid_configure_msg configure;
+				/**< Port ID configuration information. */
+		struct nss_portid_unconfigure_msg unconfigure;
+				/**< Port ID de-configuration information. */
+		struct nss_portid_stats_sync_msg stats_sync;
+				/**< Synchronization statistics for the port ID. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving port ID messages.
+ *
+ * @datatypes
+ * nss_portid_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] npm       Pointer to the NSS Profiler message.
+ */
+typedef void (*nss_portid_msg_callback_t)(void *app_data, struct nss_portid_msg *npm);
+
+/**
+ * Callback function for receiving port ID interface data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_portid_buf_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_portid_get_stats
+ *	Gets statistics from a port interface.
+ *
+ * @datatypes
+ * rtnl_link_stats64
+ *
+ * @param[in]  if_num  NSS interface number.
+ * @param[out] stats   Container for the statistic counters.
+ *
+ * @return
+ * TRUE or FALSE.
+ */
+bool nss_portid_get_stats(uint32_t if_num, struct rtnl_link_stats64 *stats);
+
+/**
+ * nss_portid_msg_init
+ *	Initializes a port ID message.
+ *
+ * @datatypes
+ * nss_portid_msg \n
+ * nss_portid_msg_callback_t
+ *
+ * @param[in,out] npm       Pointer to the NSS port ID message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_portid_msg_init(struct nss_portid_msg *npm, uint16_t if_num, uint32_t type, uint32_t len,
+							nss_portid_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_portid_if_tx_data
+ *	Transmits a data packet to the NSS port ID interface.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] os_buf   Pointer to the OS data buffer.
+ * @param[in] if_num   NSS interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_portid_if_tx_data(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, uint32_t if_num);
+
+/**
+ * nss_portid_tx_msg
+ *	Sends a port ID message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_portid_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_portid_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_portid_msg *msg);
+
+/**
+ * nss_portid_tx_msg_sync
+ *	Sends a port ID message to the NSS and waits for a response.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_portid_msg
+ *
+ * @param[in]     nss_ctx  Pointer to the NSS context.
+ * @param[in,out] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_portid_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_portid_msg *msg);
+
+/**
+ * nss_portid_register_port_if
+ *	Registers the port interface with the NSS.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_portid_buf_callback_t
+ *
+ * @param[in] if_num   NSS interface number.
+ * @param[in] port_id  Physical port ID of this interface.
+ * @param[in] ndev     Pointer to the associated network device.
+ * @param[in] buf_cb   Callback for the data.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_portid_register_port_if(uint32_t if_num, uint32_t port_id, struct net_device *ndev, nss_portid_buf_callback_t buf_cb);
+
+/**
+ * nss_portid_unregister_port_if
+ *	Deregisters the port interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * TRUE or FALSE.
+ *
+ * @dependencies
+ * The interface must have been previously registered.
+ */
+extern bool nss_portid_unregister_port_if(uint32_t if_num);
+
+/**
+ * nss_portid_tx_configure_port_if_msg
+ *	Sends a port interface configuration message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx      Pointer to the NSS context.
+ * @param[in] port_if_num  Interface number of the port node.
+ * @param[in] port_id      ID of the mapped switch port.
+ * @param[in] gmac_id      ID of the mapped GMAC interface.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_portid_tx_configure_port_if_msg(struct nss_ctx_instance *nss_ctx, uint32_t port_if_num, uint8_t port_id, uint8_t gmac_id);
+
+/**
+ * nss_portid_tx_unconfigure_port_if_msg
+ *	Sends a port interface de-configuration message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx      Pointer to the NSS context.
+ * @param[in] port_if_num  Interface number of the port node.
+ * @param[in] port_id      ID of the mapped switch port.
+ *
+ * @return
+ * Status of the Tx operation.
+ *
+ * @dependencies
+ * The interface must have been previously configured.
+ */
+extern nss_tx_status_t nss_portid_tx_unconfigure_port_if_msg(struct nss_ctx_instance *nss_ctx, uint32_t port_if_num, uint8_t port_id);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_PORTID_H */
diff --git a/qca-nss-drv/exports/nss_ppe.h b/qca-nss-drv/exports/nss_ppe.h
new file mode 100644
index 0000000..648bb66
--- /dev/null
+++ b/qca-nss-drv/exports/nss_ppe.h
@@ -0,0 +1,91 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ppe.h
+ *	NSS PPE interface definitions.
+ */
+
+#ifndef _NSS_PPE_H_
+#define _NSS_PPE_H_
+
+typedef int32_t nss_ppe_port_t;
+
+/**
+ * @addtogroup nss_ppe_subsystem
+ * @{
+ */
+
+/*
+ * NSS PORT defines
+ */
+#define NSS_PPE_NUM_PHY_PORTS_MAX		8
+		/**< Maximum number of PPE physical ports. */
+#define NSS_PPE_PORT_IPSEC			7
+		/**< Port number of PPE inline IPsec port. */
+
+/**
+ * nss_ppe_sc_type
+ *	PPE service code types.
+ */
+enum nss_ppe_sc_type {
+	NSS_PPE_SC_NONE,		/**< Normal PPE processing. */
+	NSS_PPE_SC_BYPASS_ALL,		/**< Bypasses all stages in PPE. */
+	NSS_PPE_SC_ADV_QOS_BRIDGED,	/**< Advance QoS redirection for bridged flow. */
+	NSS_PPE_SC_BR_QOS,		/**< Bridge QoS redirection. */
+	NSS_PPE_SC_BNC_0,		/**< QoS bounce. */
+	NSS_PPE_SC_BNC_CMPL_0,		/**< QoS bounce complete. */
+	NSS_PPE_SC_ADV_QOS_ROUTED,	/**< Advance QoS redirection for routed flow. */
+	NSS_PPE_SC_IPSEC_PPE2EIP,	/**< Inline IPsec redirection from PPE-to-EIP. */
+	NSS_PPE_SC_IPSEC_EIP2PPE,	/**< Inline IPsec redirection from EIP-to-PPE. */
+	NSS_PPE_SC_PTP,			/**< Service code for PTP packets. */
+	NSS_PPE_SC_VLAN_FILTER_BYPASS,	/**< VLAN filter bypass for bridge flows between 2 different VSIs. */
+	NSS_PPE_SC_L3_EXCEPT,		/**< Indicate exception post tunnel/TAP operation. */
+	NSS_PPE_SC_SPF_BYPASS,		/**< Source port filtering bypass in PPE. */
+	NSS_PPE_SC_MAX,			/**< Maximum service code. */
+};
+
+/**
+ * nss_ppe_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_ppe_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * nss_ppe_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_ppe_stats_register_notifier(struct notifier_block *nb);
+
+/** @} */ /* end_addtogroup nss_ppe_subsystem */
+
+#endif /* _NSS_PPE_H_ */
diff --git a/qca-nss-drv/exports/nss_ppe_vp.h b/qca-nss-drv/exports/nss_ppe_vp.h
new file mode 100644
index 0000000..abfda74
--- /dev/null
+++ b/qca-nss-drv/exports/nss_ppe_vp.h
@@ -0,0 +1,86 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ppe_vp.h
+ *	NSS PPE Virtual Port definitions.
+ */
+
+#ifndef _NSS_PPE_VP_H_
+#define _NSS_PPE_VP_H_
+
+/**
+ * @addtogroup nss_ppe_vp_subsystem
+ * @{
+ */
+
+/**
+ * nss_if_ppe_vp_destroy
+ *	Destroys the PPE VP for a given NSS interface number.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] if_num   NSS interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_ppe_vp_destroy(struct nss_ctx_instance *nss_ctx, nss_if_num_t if_num);
+
+/**
+ * nss_ppe_vp_create
+ *	Creates the PPE VP for a given NSS interface number.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] if_num   NSS interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_ppe_vp_create(struct nss_ctx_instance *nss_ctx, nss_if_num_t if_num);
+
+/**
+ * nss_ppe_vp_get_ppe_port_by_nssif
+ *	Returns the PPE VP number for a given NSS interface number.
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] nss_if  NSS interface number.
+ *
+ * @return
+ * Returns the PPE VP number corresponding to the NSS interface number.
+ */
+nss_ppe_port_t nss_ppe_vp_get_ppe_port_by_nssif(struct nss_ctx_instance *nss_ctx, nss_if_num_t nss_if);
+
+/**
+ * nss_ppe_vp_get_context
+ *	Returns the NSS context of the PPE VP.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_ppe_vp_get_context(void);
+
+/** @} */ /* end_addtogroup nss_ppe_vp_subsystem */
+
+#endif /* _NSS_PPE_VP_H_ */
diff --git a/qca-nss-drv/exports/nss_pppoe.h b/qca-nss-drv/exports/nss_pppoe.h
new file mode 100644
index 0000000..f082d30
--- /dev/null
+++ b/qca-nss-drv/exports/nss_pppoe.h
@@ -0,0 +1,384 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_pppoe.h
+ * 	NSS PPPoE interface definitions.
+ */
+
+#ifndef __NSS_PPPOE_H
+#define __NSS_PPPOE_H
+
+/**
+ * @addtogroup nss_pppoe_subsystem
+ * @{
+ */
+
+/**
+ * Maximum number of supported PPPoE sessions.
+ */
+#define NSS_MAX_PPPOE_DYNAMIC_INTERFACES 8
+
+/**
+ * nss_pppoe_metadata_types
+ *	Message types for PPPoE requests and responses.
+ */
+enum nss_pppoe_metadata_types {
+	NSS_PPPOE_MSG_SESSION_CREATE,
+	NSS_PPPOE_MSG_SESSION_DESTROY,
+	NSS_PPPOE_MSG_SYNC_STATS,
+	NSS_PPPOE_MSG_BR_ACCEL_CFG,
+	NSS_PPPOE_MSG_MAX
+};
+
+/**
+ * nss_pppoe_session_exception_events
+ *	Session exception events from the PPPoE handler.
+ */
+enum nss_pppoe_session_exception_events {
+	NSS_PPPOE_SESSION_EXCEPTION_EVENT_WRONG_VERSION_OR_TYPE,
+	NSS_PPPOE_SESSION_EXCEPTION_EVENT_WRONG_CODE,
+	NSS_PPPOE_SESSION_EXCEPTION_EVENT_UNSUPPORTED_PPP_PROTOCOL,
+	NSS_PPPOE_SESSION_EXCEPTION_EVENT_MAX
+};
+
+/**
+ * pppoe_base_exception_events
+ * 	Base node exception events from the PPPoE handler.
+ */
+enum nss_pppoe_base_exception_events {
+	NSS_PPPOE_BASE_EXCEPTION_EVENT_SHORT_PPPOE_HDR_LENGTH,
+	NSS_PPPOE_BASE_EXCEPTION_EVENT_SHORT_PACKET_LENGTH,
+	NSS_PPPOE_BASE_EXCEPTION_EVENT_WRONG_VERSION_OR_TYPE,
+	NSS_PPPOE_BASE_EXCEPTION_EVENT_WRONG_CODE,
+	NSS_PPPOE_BASE_EXCEPTION_EVENT_UNSUPPORTED_PPP_PROTOCOL,
+	NSS_PPPOE_BASE_EXCEPTION_EVENT_DISABLED_BRIDGE_PACKET,
+	NSS_PPPOE_BASE_EXCEPTION_EVENT_MAX
+};
+
+/**
+ * nss_pppoe_br_accel_mode
+ *	PPPoE bridge acceleration modes.
+ */
+enum nss_pppoe_br_accel_modes {
+	NSS_PPPOE_BR_ACCEL_MODE_DIS,
+	NSS_PPPOE_BR_ACCEL_MODE_EN_5T,
+	NSS_PPPOE_BR_ACCEL_MODE_EN_3T,
+	NSS_PPPOE_BR_ACCEL_MODE_MAX
+};
+
+/**
+ * nss_pppoe_base_stats
+ * 	PPPoE base node synchronization statistics.
+ */
+struct nss_pppoe_base_stats {
+	struct nss_cmn_node_stats node;	/**< Common node statistics. */
+	uint32_t exception[NSS_PPPOE_BASE_EXCEPTION_EVENT_MAX];
+						/**< PPPoE base node exception events. */
+};
+
+/**
+ * nss_pppoe_session_stats
+ * 	PPPoE synchronization statistics per session.
+ */
+struct nss_pppoe_session_stats {
+	struct nss_cmn_node_stats node;	/**< Common node statistics. */
+	uint32_t exception[NSS_PPPOE_SESSION_EXCEPTION_EVENT_MAX];
+						/**< PPPoE session exception events. */
+};
+
+/**
+ * nss_pppoe_stats_session
+ *	PPPoE session statistics.
+ */
+enum nss_pppoe_stats_session {
+	NSS_PPPOE_STATS_SESSION_RX_PACKETS,
+	NSS_PPPOE_STATS_SESSION_RX_BYTES,
+	NSS_PPPOE_STATS_SESSION_TX_PACKETS,
+	NSS_PPPOE_STATS_SESSION_TX_BYTES,
+	NSS_PPPOE_STATS_SESSION_WRONG_VERSION_OR_TYPE,
+	NSS_PPPOE_STATS_SESSION_WRONG_CODE,
+	NSS_PPPOE_STATS_SESSION_UNSUPPORTED_PPP_PROTOCOL,
+	NSS_PPPOE_STATS_SESSION_MAX
+};
+
+/**
+ * nss_pppoe_stats_base
+ *	PPPoE base node statistics.
+ */
+enum nss_pppoe_stats_base {
+	NSS_PPPOE_STATS_BASE_RX_PACKETS,
+	NSS_PPPOE_STATS_BASE_RX_BYTES,
+	NSS_PPPOE_STATS_BASE_TX_PACKETS,
+	NSS_PPPOE_STATS_BASE_TX_BYTES,
+	NSS_PPPOE_STATS_BASE_RX_QUEUE_0_DROPPED,
+	NSS_PPPOE_STATS_BASE_RX_QUEUE_1_DROPPED,
+	NSS_PPPOE_STATS_BASE_RX_QUEUE_2_DROPPED,
+	NSS_PPPOE_STATS_BASE_RX_QUEUE_3_DROPPED,
+	NSS_PPPOE_STATS_BASE_SHORT_PPPOE_HDR_LENGTH,
+	NSS_PPPOE_STATS_BASE_SHORT_PACKET_LENGTH,
+	NSS_PPPOE_STATS_BASE_WRONG_VERSION_OR_TYPE,
+	NSS_PPPOE_STATS_BASE_WRONG_CODE,
+	NSS_PPPOE_STATS_BASE_UNSUPPORTED_PPP_PROTOCOL,
+	NSS_PPPOE_STATS_BASE_DISABLED_BRIDGE_PACKET,
+	NSS_PPPOE_STATS_BASE_MAX
+};
+
+/**
+ * nss_pppoe_stats_notification
+ *	PPPoE statistics structure.
+ */
+struct nss_pppoe_stats_notification {
+	uint32_t core_id;					/**< Core ID. */
+	uint32_t if_num;					/**< Interface number. */
+	uint64_t session_stats[NSS_PPPOE_STATS_SESSION_MAX];	/**< PPPoE statistics. */
+	uint64_t base_stats[NSS_PPPOE_STATS_BASE_MAX];		/**< PPPoE base node statistics. */
+};
+
+#ifdef __KERNEL__ /* only kernel will use. */
+
+/**
+ * nss_pppoe_sync_stats_msg
+ *	PPPoE synchronization statistics.
+ */
+struct nss_pppoe_sync_stats_msg {
+	struct nss_pppoe_session_stats session_stats;	/**< Session statistics. */
+	struct nss_pppoe_base_stats base_stats;		/**< Base node statistics. */
+};
+
+/**
+ * nss_pppoe_destroy_msg
+ *	PPPoE session destroy message.
+ */
+struct nss_pppoe_destroy_msg {
+	uint16_t session_id;		/**< PPPoE session identification number. */
+	uint8_t server_mac[ETH_ALEN];	/**< PPPoE server MAC address. */
+	uint8_t local_mac[ETH_ALEN];	/**< Local physical interface MAC address. */
+};
+
+/**
+ * nss_pppoe_create_msg
+ *	PPPoE session create message.
+ */
+struct nss_pppoe_create_msg {
+	int32_t base_if_num;		/**< Base NSS interface number which PPPoE session created on. */
+	uint32_t mtu;			/**< PPPoE interface MTU value. */
+	uint8_t server_mac[ETH_ALEN];	/**< PPPoE server MAC address. */
+	uint8_t local_mac[ETH_ALEN];	/**< Local physical interface MAC address. */
+	uint16_t session_id;		/**< PPPoE session identification number. */
+};
+
+/**
+ * nss_pppoe_br_accel_cfg_msg
+ *	PPPoE bridge acceleration configuration message.
+ */
+struct nss_pppoe_br_accel_cfg_msg {
+	uint32_t br_accel_cfg;		/**< PPPoE bridge acceleration configuration. */
+};
+
+/**
+ * nss_pppoe_msg
+ *	Data for sending and receiving PPPoE messages.
+ */
+struct nss_pppoe_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a PPPoE message.
+	 */
+	union {
+		struct nss_pppoe_create_msg create;
+					/**< Session create message. */
+		struct nss_pppoe_destroy_msg destroy;
+					/**< Session destroy message. */
+		struct nss_pppoe_sync_stats_msg sync_stats;
+					/**< Session statistics message. */
+		struct nss_pppoe_br_accel_cfg_msg br_accel;
+					/**< PPPoE bridge acceleration configuration message. */
+	} msg;				/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving PPPoE messages.
+ *
+ * @datatypes
+ * nss_pppoe_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_pppoe_msg_callback_t)(void *app_data, struct nss_pppoe_msg *msg);
+
+/**
+ * nss_pppoe_tx_msg_sync
+ *	Sends a PPPoE message synchronously to NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_pppoe_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_pppoe_tx_msg_sync(struct nss_ctx_instance *nss_ctx,
+						struct nss_pppoe_msg *msg);
+
+/**
+ * nss_register_pppoe_session_if
+ *	Registers the PPPoE session interface with the NSS for sending and
+ *	receiving messages.
+ *
+ * @datatypes
+ * nss_pppoe_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num                 NSS interface number.
+ * @param[in] notification_callback  Callback for the message.
+ * @param[in] netdev                 Pointer to the associated network device.
+ * @param[in] features               Socket buffer types supported by this interface.
+ * @param[in] app_ctx                Pointer to the application context of the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_register_pppoe_session_if(uint32_t if_num,
+						       nss_pppoe_msg_callback_t notification_callback,
+						       struct net_device *netdev, uint32_t features, void *app_ctx);
+
+/**
+ * nss_unregister_pppoe_session_if
+ *	Deregisters the PPPoE session interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+. *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The tunnel interface must have been previously registered.
+ */
+extern void nss_unregister_pppoe_session_if(uint32_t if_num);
+
+/**
+ * nss_pppoe_get_context
+ *	Gets the PPPoE context used in PPPoE transmit message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_pppoe_get_context(void);
+
+/**
+ * nss_pppoe_debug_stats_get
+ *	Gets NSS session debug statistics.
+ *
+ * @param[out] stats_mem  Pointer to the memory address, which must be large
+ *                         enough to hold all the statistics.
+ *
+ * @return
+ * None.
+ */
+extern void nss_pppoe_debug_stats_get(void *stats_mem);
+
+/**
+ * nss_pppoe_get_bridge_accel_mode
+ *	Gets the PPPoE bridge acceleration mode.
+ *
+ * @return
+ * Current PPPoE bridge acceleration mode.
+ */
+extern enum nss_pppoe_br_accel_modes nss_pppoe_get_br_accel_mode(void);
+
+/**
+ * nss_pppoe_register_sysctl
+ *	Registers the PPPoE system control table.
+ *
+ * @return
+ * None.
+ */
+void nss_pppoe_register_sysctl(void);
+
+/**
+ * nss_pppoe_unregister_sysctl
+ *	Deregisters the PPPoE system control table.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The system control table must have been previously registered.
+ */
+void nss_pppoe_unregister_sysctl(void);
+
+/**
+ * nss_pppoe_msg_init
+ *	Initializes a PPPoE message.
+ *
+ * @datatypes
+ * nss_pppoe_msg
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    Interface number
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Pointer to the message callback.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_pppoe_msg_init(struct nss_pppoe_msg *ncm,
+				uint16_t if_num, uint32_t type, uint32_t len,
+				void *cb, void *app_data);
+
+/**
+ * nss_pppoe_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_pppoe_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_pppoe_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_pppoe_stats_unregister_notifier(struct notifier_block *nb);
+
+#endif /*__KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_PPPOE_H */
diff --git a/qca-nss-drv/exports/nss_pptp.h b/qca-nss-drv/exports/nss_pptp.h
new file mode 100644
index 0000000..6478684
--- /dev/null
+++ b/qca-nss-drv/exports/nss_pptp.h
@@ -0,0 +1,345 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_pptp.h
+ *	NSS PPTP interface definitions.
+ */
+
+#ifndef _NSS_PPTP_H_
+#define _NSS_PPTP_H_
+
+#include "nss_dynamic_interface.h"
+
+/**
+ * @addtogroup nss_pptp_subsystem
+ * @{
+ */
+
+/**
+ * Maximum number of supported PPTP sessions is 4.
+ * Number of dynamic intefaces per session is 3.
+ * Total 4 * 3 = 12
+ */
+#define NSS_MAX_PPTP_DYNAMIC_INTERFACES 12
+
+/**
+ * nss_pptp_metadata_types
+ *	Message types for PPTP requests and responses.
+ */
+enum nss_pptp_metadata_types {
+	NSS_PPTP_MSG_SESSION_CONFIGURE,
+	NSS_PPTP_MSG_SESSION_DECONFIGURE,
+	NSS_PPTP_MSG_SYNC_STATS,
+	NSS_PPTP_MSG_MAX
+};
+
+/**
+ * nss_pptp_exception_events
+ *	Exception events for PPTP encapsulation and decapsulation packets.
+ */
+enum nss_pptp_exception_events {
+	PPTP_EXCEPTION_EVENT_ENCAP_HEADROOM_ERR,
+	PPTP_EXCEPTION_EVENT_ENCAP_SMALL_SIZE,
+	PPTP_EXCEPTION_EVENT_ENCAP_PNODE_ENQUEUE_FAIL,
+	PPTP_EXCEPTION_EVENT_DECAP_NO_SEQ_NOR_ACK,
+	PPTP_EXCEPTION_EVENT_DECAP_INVAL_GRE_FLAGS,
+	PPTP_EXCEPTION_EVENT_DECAP_INVAL_GRE_PROTO,
+	PPTP_EXCEPTION_EVENT_DECAP_WRONG_SEQ,
+	PPTP_EXCEPTION_EVENT_DECAP_INVAL_PPP_HDR,
+	PPTP_EXCEPTION_EVENT_DECAP_PPP_LCP,
+	PPTP_EXCEPTION_EVENT_DECAP_UNSUPPORTED_PPP_PROTO,
+	PPTP_EXCEPTION_EVENT_DECAP_PNODE_ENQUEUE_FAIL,
+	PPTP_EXCEPTION_EVENT_MAX,
+};
+
+/**
+ * nss_pptp_stats_session
+ * 	PPTP debug statistics.
+ */
+enum nss_pptp_stats_session {
+	NSS_PPTP_STATS_ENCAP_RX_PACKETS,
+	NSS_PPTP_STATS_ENCAP_RX_BYTES,
+	NSS_PPTP_STATS_ENCAP_TX_PACKETS,
+	NSS_PPTP_STATS_ENCAP_TX_BYTES,
+	NSS_PPTP_STATS_ENCAP_RX_QUEUE_0_DROP,
+	NSS_PPTP_STATS_ENCAP_RX_QUEUE_1_DROP,
+	NSS_PPTP_STATS_ENCAP_RX_QUEUE_2_DROP,
+	NSS_PPTP_STATS_ENCAP_RX_QUEUE_3_DROP,
+	NSS_PPTP_STATS_DECAP_RX_PACKETS,
+	NSS_PPTP_STATS_DECAP_RX_BYTES,
+	NSS_PPTP_STATS_DECAP_TX_PACKETS,
+	NSS_PPTP_STATS_DECAP_TX_BYTES,
+	NSS_PPTP_STATS_DECAP_RX_QUEUE_0_DROP,
+	NSS_PPTP_STATS_DECAP_RX_QUEUE_1_DROP,
+	NSS_PPTP_STATS_DECAP_RX_QUEUE_2_DROP,
+	NSS_PPTP_STATS_DECAP_RX_QUEUE_3_DROP,
+	NSS_PPTP_STATS_SESSION_ENCAP_HEADROOM_ERR,
+	NSS_PPTP_STATS_SESSION_ENCAP_SMALL_SIZE,
+	NSS_PPTP_STATS_SESSION_ENCAP_PNODE_ENQUEUE_FAIL,
+	NSS_PPTP_STATS_SESSION_DECAP_NO_SEQ_NOR_ACK,
+	NSS_PPTP_STATS_SESSION_DECAP_INVAL_GRE_FLAGS,
+	NSS_PPTP_STATS_SESSION_DECAP_INVAL_GRE_PROTO,
+	NSS_PPTP_STATS_SESSION_DECAP_WRONG_SEQ,
+	NSS_PPTP_STATS_SESSION_DECAP_INVAL_PPP_HDR,
+	NSS_PPTP_STATS_SESSION_DECAP_PPP_LCP,
+	NSS_PPTP_STATS_SESSION_DECAP_UNSUPPORTED_PPP_PROTO,
+	NSS_PPTP_STATS_SESSION_DECAP_PNODE_ENQUEUE_FAIL,
+	NSS_PPTP_STATS_SESSION_MAX
+};
+
+/**
+ * nss_pptp_stats_notification
+ *	PPTP statistics structure.
+ */
+struct nss_pptp_stats_notification {
+	uint32_t core_id;				/**< Core ID. */
+	uint32_t if_num;				/**< Interface number. */
+	enum nss_dynamic_interface_type if_type;	/**< Dynamic interface type. */
+	uint64_t stats[NSS_PPTP_STATS_SESSION_MAX];	/**< PPTP statistics. */
+};
+
+/**
+ * nss_pptp_session_configure_msg
+ *	Message information for configuring a PPTP session.
+ */
+struct nss_pptp_session_configure_msg {
+	uint16_t src_call_id;		/**< Local call ID for caller or callee. */
+	uint16_t dst_call_id;		/**< Peer call ID for caller or callee. */
+	uint32_t sip;			/**< Local tunnel endpoint. */
+	uint32_t dip;			/**< Remote tunnel endpoint. */
+	uint32_t sibling_ifnum_pri;	/**< Primary sibling interface. */
+	uint32_t sibling_ifnum_aux;	/**< Auxiliary sibling interface. */
+};
+
+/**
+ * nss_pptp_session_deconfigure_msg
+ *	Message information for deleting a PPTP session.
+ */
+struct nss_pptp_session_deconfigure_msg {
+	uint16_t src_call_id;		/**< Local call ID */
+};
+
+/**
+ * nss_pptp_sync_session_stats_msg
+ *	Message information for PPTP synchronization statistics.
+ */
+struct nss_pptp_sync_session_stats_msg {
+	struct nss_cmn_node_stats node_stats;
+			/**< Common node statistics for the encapsulation direction. */
+	uint32_t exception_events[PPTP_EXCEPTION_EVENT_MAX];
+			/**< Statistics of events which casued packets to exception to host. */
+};
+
+/**
+ * nss_pptp_msg
+ *	Data for sending and receiving PPTP messages.
+ */
+struct nss_pptp_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a PPTP message.
+	 */
+	union {
+		struct nss_pptp_session_configure_msg session_configure_msg;
+				/**< Session configuration message. */
+		struct nss_pptp_session_deconfigure_msg session_deconfigure_msg;
+				/**< Session de-configuration message. */
+		struct nss_pptp_sync_session_stats_msg stats;
+				/**< Session statistics message. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving PPTP messages.
+ *
+ * @datatypes
+ * nss_pptp_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_pptp_msg_callback_t)(void *app_data, struct nss_pptp_msg *msg);
+
+/**
+ * nss_pptp_tx_msg_sync
+ *	Sends a PPTP message synchronously to NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_pptp_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_pptp_tx_msg_sync(struct nss_ctx_instance *nss_ctx,
+					    struct nss_pptp_msg *msg);
+
+/**
+ * nss_pptp_tx_buf
+ *	Sends a data packet to the firmware.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in]     nss_ctx  Pointer to the NSS context.
+ * @param[in]     if_num   NSS interface number.
+ * @param[in]     skb      Pointer to the data socket buffer.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_pptp_tx_buf(struct nss_ctx_instance *nss_ctx, uint32_t if_num, struct sk_buff *skb);
+
+/**
+ * nss_pptp_get_context
+ *	Gets the PPTP context used in nss_pptp_tx.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_pptp_get_context(void);
+
+/**
+ * Callback function for receiving PPTP tunnel data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_pptp_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_register_pptp_if
+ *	Registers the PPTP tunnel interface with the NSS for sending and
+ *	receiving messages.
+ *
+ * @datatypes
+ * nss_pptp_callback_t \n
+ * nss_pptp_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num                 NSS interface number.
+ * @param[in] type                   Dynamic interface type.
+ * @param[in] pptp_data_callback     Callback for the data.
+ * @param[in] notification_callback  Callback for the message.
+ * @param[in] netdev                 Pointer to the associated network device.
+ * @param[in] features               Socket buffer types supported by this interface.
+ * @param[in] app_ctx                Pointer to the application context of the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_register_pptp_if(uint32_t if_num, uint32_t type, nss_pptp_callback_t pptp_data_callback,
+					nss_pptp_msg_callback_t notification_callback, struct net_device *netdev, uint32_t features, void *app_ctx);
+
+/**
+ * nss_unregister_pptp_if
+ *	Deregisters the PPTP tunnel interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+. *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The tunnel interface must have been previously registered.
+ */
+extern void nss_unregister_pptp_if(uint32_t if_num);
+
+/**
+ * nss_pptp_msg_init
+ *	Initializes a PPTP message.
+ *
+ * @datatypes
+ * nss_pptp_msg
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    Interface number
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Pointer to the message callback.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_pptp_msg_init(struct nss_pptp_msg *ncm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data);
+
+/**
+ * nss_pptp_register_handler
+ *	Registers the PPTP interface with the NSS debug statistics handler.
+ *
+ * @return
+ * None.
+ */
+extern void nss_pptp_register_handler(void);
+
+/**
+ * nss_pptp_session_debug_stats_get
+ *	Gets NSS session debug statistics.
+ *
+ * @param[out] stats_mem  Pointer to the memory address, which must be large
+ *                         enough to hold all the statistics.
+ *
+ * @return
+ * None.
+ */
+extern void nss_pptp_session_debug_stats_get(void *stats_mem);
+
+/**
+ * nss_pptp_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_pptp_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_pptp_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_pptp_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * @}
+ */
+
+#endif /* _NSS_PPTP_H_ */
diff --git a/qca-nss-drv/exports/nss_profiler.h b/qca-nss-drv/exports/nss_profiler.h
new file mode 100644
index 0000000..89ddf65
--- /dev/null
+++ b/qca-nss-drv/exports/nss_profiler.h
@@ -0,0 +1,406 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, 2017, 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_profiler.h
+ *	NSS Profiler APIs
+ */
+
+#ifndef __NSS_PROFILER_H
+#define __NSS_PROFILER_H
+
+/**
+ * @addtogroup nss_profiler_subsystem
+ * @{
+ */
+
+/**
+ * Length of the counter name.
+ *
+ * This value allows all counter values to fit in a single 1400-byte UDP packet.
+ */
+#define PROFILE_COUNTER_NAME_LENGTH 20
+
+#define PROFILE_MAX_APP_COUNTERS 24	/**< Maximum number of application counters. */
+
+/**
+ * nss_profile_counter
+ *	Counter statistics.
+ */
+struct nss_profile_counter {
+	char name[PROFILE_COUNTER_NAME_LENGTH];		/**< Counter name. */
+	uint32_t value;					/**< Current value. */
+};
+
+/**
+ * nss_profiler_message_types
+ *	Message types for the Profiler.
+ *
+ * Do not alter this enumeration. However, adding more types is allowed.
+ */
+enum nss_profiler_message_types {
+	NSS_PROFILER_CHANGE_SAMPLING_RATE_MSG,	/**< Host-to-NSS: ask to do a rate change. */
+	NSS_PROFILER_START_MSG,			/**< Host-to-NSS: start the NSS Profiler. */
+	NSS_PROFILER_STOP_MSG,			/**< Host-to-NSS: stop the NSS Profiler. */
+	NSS_PROFILER_FLOWCTRL_MSG,		/**< Host-to-NSS: do flow control on sampling. */
+	NSS_PROFILER_DEBUG_RD_MSG,		/**< Host-to-NSS: debug the output. */
+	NSS_PROFILER_DEBUG_WR_MSG,		/**< Host-to-NSS: debug the input. */
+	NSS_PROFILER_DEBUG_REPLY_MSG,		/**< NSS-to-host: debug response. */
+	NSS_PROFILER_REPLY_MSG,			/**< Check the response. */
+	NSS_PROFILER_FIXED_INFO_MSG,		/**< NSS-to-host: constant data. */
+	NSS_PROFILER_COUNTERS_MSG,		/**< NSS-to-host: counter information. */
+	NSS_PROFILER_SAMPLES_MSG,		/**< NSS-to-host: main sample data. */
+	NSS_PROFILER_START_CAL,			/**< Not for the host to use. */
+	NSS_PROFILER_GET_SYS_STAT_EVENT,	/**< Get the system status event. */
+	NSS_PROFILER_SET_SYS_STAT_EVENT,	/**< Set the system status event. */
+	NSS_PROFILER_MAX_MSG_TYPES,		/**< Maximum number of message types. */
+};
+
+/**
+ * nss_profile_errors
+ *	Profiler error types returned from the NSS.
+ */
+enum nss_profile_errors {
+	PROFILE_ERROR_NO_PROF_INIT = 1,
+	PROFILE_ERROR_EMEM,
+	PROFILE_ERROR_BAD_PKT,
+	PROFILE_ERROR_UNKNOWN_CMD,
+	PROFILE_ERROR_NO_DMA,
+	PROFILE_ERROR_MAX
+};
+
+/**
+ * nss_profiler_cmd_param
+ *	Parameter information for the Profiler.
+ *
+ * Use this structure for per-session commands: START, STOP, FLOWCTRL, RATE.
+ */
+struct nss_profiler_cmd_param {
+	uint32_t hd_magic;		/**< Common overlay in all headers. */
+	uint32_t num_counters;
+			/**< Number of registered performance (application) counters. */
+	uint32_t ocm_size;		/**< Size of the on-chip-memory. */
+	uint32_t sram_start;		/**< DDR starting address. */
+	uint32_t rate;			/**< Sampling rate. */
+	uint32_t cpu_id;		/**< ID of the chip register. */
+	uint32_t cpu_freq;		/**< Chip clock frequency. */
+	uint32_t ddr_freq;		/**< DDR memory speed. */
+
+	struct nss_profile_counter counters[PROFILE_MAX_APP_COUNTERS];
+			/**< Application profiling counters. */
+};
+
+/**
+ * nss_profiler_data_msg
+ *	Message information for the Profiler.
+ */
+struct nss_profiler_data_msg {
+	uint32_t hd_magic;		/**< Magic header for verification. */
+	uint32_t msg_data[1];		/**< Variable length private data. */
+};
+
+/**
+ * nss_profiler_debug_msg
+ *	Message information for Profiler debugging.
+ */
+struct nss_profiler_debug_msg {
+	uint32_t hd_magic;		/**< Magic header for verification. */
+	uint32_t debug_data[256];	/**< Fixed length debug data. */
+};
+
+/**
+ * nss_profiler_msg
+ *	Data for sending and receiving Profiler messages.
+ */
+struct nss_profiler_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a Profiler message.
+	 */
+	union npm_body {
+		struct nss_profiler_cmd_param pcmdp;	/**< Command parameters. */
+		struct nss_profiler_debug_msg pdm;	/**< Debug packet. */
+		struct nss_profiler_data_msg msg;	/**< Sampling data. */
+	} payload;	/**< Message payload. The data length is set in common message header. */
+};
+
+/**
+ * nss_profile_sdma_producer
+ *	DMA descriptor of producer.
+ */
+struct nss_profile_sdma_producer {
+	uint32_t intr_num;	/**< Interrupt number. */
+	uint32_t pkg_id;	/**< Package ID that registered this entry. */
+	uint32_t buf_size;	/**< DMA buffer size. */
+	uint32_t num_bufs;	/**< Number of ring buffers. */
+	uint32_t desc_ring;	/**< Ring address (physical 32-bit). */
+	uint32_t pad3w[3];	/**< Pad 32-byte alignment. */
+};
+
+/**
+ * nss_u64_32_data
+ *	64-bit union for both 32/64 bits data aligned at 64-bit boundary.
+ */
+union nss_u64_32_data {
+	uint64_t d64;	/**< 64-bit space holder: may not be used. */
+	uint32_t d32;	/**< 32-bit direct data. */
+	void *kp;	/**< Kernel data pointer either 32 or 64 bits. */
+};
+
+/**
+ * nss_u64_32_func
+ *	64-bit union for both 32/64 bits function aligned at 64-bit boundary.
+ */
+union nss_u64_32_func {
+	uint64_t f64;		/**< 64-bit space holder: do not use. */
+	void (*fp)(void*);	/**< Function pointer: either 32 or 64 bits. */
+};
+
+/**
+ * nss_profile_sdma_consumer
+ *	DMA descriptor of consumer.
+ */
+struct nss_profile_sdma_consumer {
+	union nss_u64_32_data arg;	/**< Dispatch function argument. */
+	union nss_u64_32_func dispatch;	/**< Dispatch function pointer. */
+	union nss_u64_32_data ring;	/**< DMA descriptor ring kernel address. */
+	int64_t unused_lw;		/**< Extra room in a Ubi32 cache line. */
+};
+
+#define	ARM_CACHE_LINE_SIZE	128	/**< ARM CPU cache line size in bytes. */
+#define	NSS_CACHE_LINE_WORDS	8	/**< Ubi32 CPU cache line size in words. */
+
+/**
+ * Number of DMA per control block.
+ */
+#define	NSS_PROFILE_MAX_DMA_DESCRIPTORS	(ARM_CACHE_LINE_SIZE / sizeof(struct nss_profile_sdma_producer) - 1)
+
+/**
+ * nss_profile_sdma_ctrl
+ *	Soft DMA control block.
+ */
+struct nss_profile_sdma_ctrl {
+	int32_t num_rings;	/**< Number of descriptor rings allocated, maximum is 3. */
+	int32_t cur_ring;	/**< Which ring is in use: Default 0. */
+	int32_t pidx[NSS_PROFILE_MAX_DMA_DESCRIPTORS];	/**< Producer index. */
+
+	/**
+	 * Pad for the first Ubi32 cache line in the first ARM cache line: Unused.
+	 */
+	int32_t pad_for_1st_cl_in_1st_arm_cl[NSS_CACHE_LINE_WORDS - 2 - NSS_PROFILE_MAX_DMA_DESCRIPTORS];
+	struct nss_profile_sdma_producer producer[NSS_PROFILE_MAX_DMA_DESCRIPTORS]; /**< DMA producer structure. */
+
+	int32_t cidx[NSS_PROFILE_MAX_DMA_DESCRIPTORS];	/**< Consumer index. */
+
+	/**
+	 * Pad for the first Ubi32 cache line in the second ARM cache line: Unused.
+	 */
+	int32_t pad_for_1st_cl_in_2nd_arm_cl[NSS_CACHE_LINE_WORDS - NSS_PROFILE_MAX_DMA_DESCRIPTORS];
+	struct nss_profile_sdma_consumer consumer[NSS_PROFILE_MAX_DMA_DESCRIPTORS]; /**< DMA consumer structure. */
+};
+
+/**
+ * Callback function for receiving Profiler messages.
+ *
+ * @note: Memory (buffer) pointed by npm is owned by caller, that is, NSS driver.
+ *
+ * @datatypes
+ * nss_profiler_msg
+ *
+ * @param[in] ctx  Pointer to the context of the NSS process (core).
+ * @param[in] npm  Pointer to the NSS Profiler message.
+ */
+typedef void (*nss_profiler_callback_t)(void *ctx, struct nss_profiler_msg *npm);
+
+/**
+ * nss_profiler_notify_register
+ *	Registers the Profiler interface with the NSS driver for sending and receiving messages.
+ *
+ * This function must be called once for each core.
+ *
+ * @datatypes
+ * nss_core_id_t \n
+ * nss_profiler_callback_t
+ *
+ * @param[in] profiler_callback  Callback for the data.
+ * @param[in] core_id            NSS core ID.
+ * @param[in] ctx                Pointer to the context of the NSS core. The context is
+                                 provided to caller in the registered callback function.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ *
+ * @dependencies
+ * The caller must provide the valid core ID that is being profiled.
+ */
+extern void *nss_profiler_notify_register(nss_core_id_t core_id, nss_profiler_callback_t profiler_callback, void *ctx);
+
+/**
+ * nss_profiler_notify_unregister
+ *	Deregisters the Profiler interface from the NSS driver.
+ *
+ * @datatypes
+ * nss_core_id_t
+ *
+ * @param[in] core_id  NSS core ID.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The interface must have been previously registered.
+ */
+extern void nss_profiler_notify_unregister(nss_core_id_t core_id);
+
+/**
+ * nss_profiler_if_tx_buf
+ *	Sends a Profiler command to the NSS firmware.
+ *
+ * @param[in] nss_ctx   Pointer to the NSS context.
+ * @param[in] buf       Buffer to send to NSS firmware.
+ * @param[in] len       Length of the buffer.
+ * @param[in] cb        Pointer to the message callback.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * Status of the Tx operation.
+ *
+ * @dependencies
+ * A valid context must be provided (for the right core).
+ * This context was returned during registration.
+ */
+extern nss_tx_status_t nss_profiler_if_tx_buf(void *nss_ctx,
+		void *buf, uint32_t len, void *cb, void *app_data);
+
+/**
+ * nss_profiler_alloc_dma
+ *	Allocate profiler DMA for transmitting samples.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_profile_sdma_producer
+ *
+ * @param[in] nss_ctx   Pointer to the NSS context.
+ * @param[in] dma_p     Pointer to return DMA control.
+ *
+ * @return
+ * Buffer adddress.
+ */
+extern void *nss_profiler_alloc_dma(struct nss_ctx_instance *nss_ctx, struct nss_profile_sdma_producer **dma_p);
+
+/**
+ * nss_profiler_release_dma()
+ *      Free profiler DMA.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ *
+ * @return
+ * None.
+ */
+extern void nss_profiler_release_dma(struct nss_ctx_instance *nss_ctx);
+
+/*
+ * nss_profile_dma_register_cb
+ *      Register a handler for profile DMA.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] id       DMA ID; typical value is 0.
+ * @param[in] cb       Callback function pointer.
+ * @param[in] arg      Callback function argument pointer.
+ *
+ * @return
+ * True on success; or false on failure.
+ */
+extern bool nss_profile_dma_register_cb(struct nss_ctx_instance *nss_ctx, int id,
+				void (*cb)(void*), void *arg);
+
+/**
+ * nss_profile_dma_deregister_cb()
+ *      Deregister callback for profile DMA.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] id       DMA ID; typical value is 0.
+ *
+ * @return
+ * True on success; or false on failure.
+ */
+extern bool nss_profile_dma_deregister_cb(struct nss_ctx_instance *nss_ctx, int id);
+
+/**
+ * nss_profile_dma_get_ctrl()
+ *      API to get profile DMA control.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ *
+ * @return
+ * DMA controller.
+ */
+extern struct nss_profile_sdma_ctrl *nss_profile_dma_get_ctrl(struct nss_ctx_instance *nss_ctx);
+
+/**
+ * profile_register_performance_counter
+ *	Registers a Linux counter with the profiler for any variables.
+ *
+ * @param[in] counter	Pointer to the variable address.
+ * @param[in] name	Pointer to the variable name: if name is longer than
+			23 characters, then only the first 23 bytes are used.
+ *
+ * @return
+ * 0	if counter array is full -- too many registered counters.
+ * 1	on success
+ */
+extern int profile_register_performance_counter(volatile unsigned int *counter, char *name);
+
+/**
+ * nss_profiler_msg_init
+ *	Initializes a Profiler-specific message.
+ *
+ * @datatypes
+ * nss_profiler_msg \n
+ * nss_profiler_callback_t
+ *
+ * @param[in,out] npm       Pointer to the NSS Profiler message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the message.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_profiler_msg_init(struct nss_profiler_msg *npm, uint16_t if_num,
+				uint32_t type, uint32_t len,
+				nss_profiler_callback_t cb, void *app_data);
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/qca-nss-drv/exports/nss_project.h b/qca-nss-drv/exports/nss_project.h
new file mode 100644
index 0000000..4b1b711
--- /dev/null
+++ b/qca-nss-drv/exports/nss_project.h
@@ -0,0 +1,176 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_project.h
+ *	NSS project interface definitions.
+ */
+
+#ifndef __NSS_PROJECT_H
+#define __NSS_PROJECT_H
+
+/**
+ * @addtogroup nss_project_subsystem
+ * @{
+ */
+
+ /**
+  * Maximum number of IRQs for which a message will have statistics.
+  *
+  * Must be defined on firmware and host such that NSS_PROJECT_IRQS_PER_MESSAGE *
+  * sizeof(struct nss_project_irq_stats) + 8 + sizeof(struct nss_cmn_msg) is smaller
+  * than the maximum payload size of an sk_buff (1792), 8 being the number of
+  * bytes needed to store the thread number and number of statistics written.
+  */
+#define NSS_PROJECT_IRQS_PER_MESSAGE 32
+
+/**
+ * nss_project_message_types
+ *	Project message types.
+ */
+enum nss_project_message_types {
+	NSS_PROJECT_MSG_WT_STATS_ENABLE,
+			/**< Message to enable or disable worker thread statistics. */
+	NSS_PROJECT_MSG_WT_STATS_NOTIFY,
+			/**< NSS to HLOS message containing worker thread statistics. */
+	NSS_PROJECT_MSG_MAX,
+};
+
+/**
+ * nss_project_error_types
+ *	Project error types.
+ */
+enum nss_project_error_types {
+	NSS_PROJECT_ERROR_UNKNOWN_MSG,
+			/**< Unrecognized message type. */
+	NSS_PROJECT_ERROR_WT_STATS_UNSUPPORTED,
+			/**< The firmware does not support worker thread statistics. */
+	NSS_PROJECT_ERROR_WT_STATS_REDUNDANT_ENABLE,
+			/**< The firmware received a redundant request to enable worker thread statistics. */
+	NSS_PROJECT_ERROR_MAX,
+};
+
+/**
+ * nss_project_msg_wt_stats_enable
+ *	Enables or disables worker thread statistics collection.
+ */
+struct nss_project_msg_wt_stats_enable {
+
+	/*
+	 * NSS to HLOS
+	 */
+	uint32_t worker_thread_count;
+			/**< Number of worker threads supported by this core. */
+	uint32_t irq_count;
+			/**< Number of IRQs supported by this core. */
+
+	/*
+	 * HLOS to NSS
+	 */
+	bool enable;	/**< True to enable, false to disable. */
+};
+
+/**
+ * nss_project_irq_stats
+ *	Statistics for an individual IRQ on a worker thread.
+ */
+struct nss_project_irq_stats {
+	uint64_t count;		/**< Number of times callback has been executed */
+	uint32_t callback;	/**< Address of the callback function */
+	uint32_t irq;		/**< IRQ number to which callback function is bound */
+	uint32_t ticks_min;	/**< Fewest ticks taken in callback function */
+	uint32_t ticks_avg;	/**< Exponential moving average of ticks */
+	uint32_t ticks_max;	/**< Maximum ticks */
+	uint32_t insn_min;	/**< Fewest instructions executed in callback function */
+	uint32_t insn_avg;	/**< Exponential moving average of instruction count */
+	uint32_t insn_max;	/**< Maximum instructions */
+};
+
+/**
+ * nss_project_msg_wt_stats_notify
+ *	Message containing statistics for active worker_thread IRQs.
+ */
+struct nss_project_msg_wt_stats_notify {
+	uint32_t threadno;	/**< The thread whose stats are contained. */
+	uint32_t stats_written;	/**< The number of statistics written to the array. */
+	struct nss_project_irq_stats stats[NSS_PROJECT_IRQS_PER_MESSAGE];
+				/**< The per-IRQ statistics for the worker thread */
+};
+
+/**
+ * nss_project_msg
+ *	General message structure for project messages.
+ */
+struct nss_project_msg {
+	struct nss_cmn_msg cm;	/**< Common message header. */
+
+	/**
+	 * Payload of a message to or from the project code.
+	 */
+	union {
+		struct nss_project_msg_wt_stats_enable wt_stats_enable;
+				/**< Enable or disable worker thread statistics. */
+		struct nss_project_msg_wt_stats_notify wt_stats_notify;
+				/**< One-way worker thread statistics message. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving project messages.
+ *
+ * @datatypes
+ * nss_project_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the project message.
+ */
+typedef void (*nss_project_msg_callback_t)(void *app_data, struct nss_project_msg *msg);
+
+/**
+ * nss_project_register_sysctl
+ *	Registers the project sysctl table to the sysctl tree.
+ *
+ * @return
+ * None.
+ */
+void nss_project_register_sysctl(void);
+
+/**
+ * nss_project_unregister_sysctl
+ *	De-registers the project sysctl table from the sysctl tree.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The system control must have been previously registered.
+ */
+void nss_project_unregister_sysctl(void);
+
+/**
+ * nss_project_register_handler
+ *	Registers the project message handler.
+ *
+ * @return
+ * None.
+ */
+void nss_project_register_handler(struct nss_ctx_instance *nss_ctx);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_PROJECT_H */
diff --git a/qca-nss-drv/exports/nss_pvxlan.h b/qca-nss-drv/exports/nss_pvxlan.h
new file mode 100644
index 0000000..2de0da2
--- /dev/null
+++ b/qca-nss-drv/exports/nss_pvxlan.h
@@ -0,0 +1,371 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_pvxlan.h
+ *	NSS proxy VxLAN interface definitions.
+ */
+
+#ifndef __NSS_PVXLAN_H
+#define __NSS_PVXLAN_H
+
+/**
+ * @addtogroup nss_pvxlan_subsystem
+ * @{
+ */
+
+/**
+ * Size of the headroom required for proxy VxLAN packets.
+ */
+#define NSS_PVXLAN_HEADROOM 256
+
+/**
+ * Maximum number of supported proxy VxLAN tunnel sessions.
+ */
+#define NSS_PVXLAN_MAX_INTERFACES 32
+
+/*
+ * Proxy VxLAN Rule configure message flags
+ */
+#define NSS_PVXLAN_TUNNEL_IPV4 0x0001		/**< IPv4 tunnel. */
+#define NSS_PVXLAN_TUNNEL_IPV6 0x0002		/**< IPv6 tunnel. */
+#define NSS_PVXLAN_TUNNEL_UDP 0x0010		/**< UDP tunnel. */
+#define NSS_PVXLAN_TUNNEL_UDPLite 0x0020	/**< UDPLite tunnel. */
+#define NSS_PVXLAN_TUNNEL_ENCAP_UDPLITE_HDR_CSUM 0x0100
+	/**< Generate only UDPLite header checksum. Otherwise whole UDPLite payload. */
+
+/**
+ * nss_pvxlan_msg_type
+ *	Proxy VxLAN message types.
+ */
+typedef enum nss_pvxlan_msg_type {
+	NSS_PVXLAN_MSG_TYPE_SYNC_STATS,		/**< Statistics synchronization message. */
+	NSS_PVXLAN_MSG_TYPE_TUNNEL_CREATE_RULE,	/**< Creating tunnel rule. */
+	NSS_PVXLAN_MSG_TYPE_TUNNEL_DESTROY_RULE,
+						/**< Destroying tunnel rule. */
+	NSS_PVXLAN_MSG_TYPE_TUNNEL_ENABLE,	/**< Enable the tunnel. */
+	NSS_PVXLAN_MSG_TYPE_TUNNEL_DISABLE,	/**< Disable the tunnel. */
+	NSS_PVXLAN_MSG_TYPE_MAC_ADD,		/**< Add MAC rule to the database. */
+	NSS_PVXLAN_MSG_TYPE_MAC_DEL,		/**< Remove MAC rule from the database. */
+	NSS_PVXLAN_MSG_TYPE_MAX,		/**< Maximum message type. */
+} nss_pvxlan_msg_type_t;
+
+/**
+ * nss_pvxlan_error_response_types
+ *	Error types for proxy VxLAN responses to messages from the host.
+ */
+typedef enum nss_pvxlan_error_response_types {
+	NSS_PVXLAN_ERROR_UNKNOWN_TYPE = 1,	/**< Unknown type error. */
+	NSS_PVXLAN_ERROR_INVALID_L3_PROTO,	/**< L3 Protocol is invalid error. */
+	NSS_PVXLAN_ERROR_INVALID_UDP_PROTO,	/**< UDP Protocol is invalid error. */
+	NSS_PVXLAN_ERROR_TUNNEL_DISABLED,	/**< Tunnel is already disabled error. */
+	NSS_PVXLAN_ERROR_TUNNEL_ENABLED,	/**< Tunnel is already enabled error. */
+	NSS_PVXLAN_ERROR_TUNNEL_ENTRY_EXIST,
+						/**< Tunnel is already exist error. */
+	NSS_PVXLAN_ERROR_TUNNEL_TABLE_FULL,
+						/**< Tunnel table is full error. */
+	NSS_PVXLAN_ERROR_INVALID_TUNNEL_ID,	/**< Tunnel ID is invalid error. */
+	NSS_PVXLAN_ERROR_MAC_TABLE_FULL,	/**< MAC table is full error. */
+	NSS_PVXLAN_ERROR_MAC_EXIST,		/**< MAC does already exist in the table error. */
+	NSS_PVXLAN_ERROR_MAC_NOT_EXIST,		/**< MAC does not exist in the table error. */
+	NSS_PVXLAN_ERROR_MAC_ENTRY_UNHASHED,
+						/**< MAC entry is not hashed in table. */
+	NSS_PVXLAN_ERROR_MAC_ENTRY_INSERT_FAILED,
+						/**< Insertion to MAC table is failed. */
+	NSS_PVXLAN_ERROR_UDP_ENCAP_TUNNEL_ID_IN_USE,
+						/**< Given tunnel ID is currently used. */
+	PVXLAN_ERROR_MSG_TUNNEL_ADD_FAILED,	/**< Tunnel add information failed. */
+	PVXLAN_ERROR_MSG_MAC_ENTRY_ALLOC_FAILED,
+						/**< MAC entry allocation failed. */
+	PVXLAN_ERROR_MSG_MAC_ENTRY_DELETE_FAILED,
+						/**< MAC entry deletion failed. */
+	NSS_PVXLAN_ERROR_MAX,			/**< Maximum error type. */
+} nss_pvxlan_error_response_t;
+
+/**
+ * nss_pvxlan_stats_msg
+ *	Per-tunnel statistics messages from the NSS firmware.
+ */
+struct nss_pvxlan_stats_msg {
+	struct nss_cmn_node_stats node_stats;	/**< Common firmware statistics. */
+	uint32_t mac_db_lookup_failed;		/**< MAC Database look up failed. */
+	uint32_t udp_encap_lookup_failed;	/**< MAC Database look up failed. */
+	uint32_t dropped_malformed;		/**< Packet is malformed. */
+	uint32_t dropped_next_node_queue_full;	/**< Next node dropped the packet. */
+	uint32_t dropped_hroom;			/**< Transmit dropped due to insufficent headroom. */
+	uint32_t dropped_ver_mis;		/**< Transmit dropped due to version mismatch. */
+	uint32_t dropped_zero_sized_packet;	/**< Transmit dropped due to zero sized packet. */
+	uint32_t dropped_pbuf_alloc_failed;	/**< Receive side pbuf allocation failed. */
+	uint32_t dropped_linear_failed;		/**< Receive side linearization failed. */
+};
+
+/**
+ * nss_pvxlan_ip
+ *	IP versions.
+ */
+struct nss_pvxlan_ip {
+	/**
+	 * Union of IPv4 and IPv6 IP addresses.
+	 */
+	union {
+		uint32_t ipv4;		/**< IPv4 address. */
+		uint32_t ipv6[4];	/**< IPv6 address. */
+	} ip;		/**< Union of IPv4 and IPv6 IP addresses. */
+};
+
+/**
+ * nss_pvxlan_encap_rule
+ *	Encapsulation information for a proxy VxLAN tunnel.
+ */
+struct nss_pvxlan_encap_rule {
+	struct  nss_pvxlan_ip src;	/**< Source IP. */
+	uint32_t src_port;		/**< Source port. */
+	struct nss_pvxlan_ip dest;	/**< Destination IP. */
+	uint32_t dest_port;		/**< Destination port. */
+};
+
+/**
+ * nss_pvxlan_rule_msg
+ *	Proxy VxLAN rule message.
+ *
+ * The same rule structure applies for both encapsulation and decapsulation
+ * in a tunnel.
+ */
+struct nss_pvxlan_rule_msg {
+	struct nss_pvxlan_encap_rule encap;	/**< Encapsulation portion of the rule. */
+	uint32_t tunnel_id;			/**< Tunnel ID. */
+	uint16_t flags;				/**< Tunnel type flags. */
+	int8_t rps;
+			/**< Receive packet steering number. Set -1 to let NSS firmware decide. */
+};
+
+/**
+ * nss_pvxlan_tunnel_state_msg
+ *	To enable/disable the tunnel.
+ */
+struct nss_pvxlan_tunnel_state_msg {
+	uint32_t sibling_if_num;		/**< Sibling interface number. */
+};
+
+/**
+ * nss_pvxlan_mac_msg
+ *	Proxy VxLAN MAC message structure.
+ */
+struct nss_pvxlan_mac_msg {
+	uint16_t mac_addr[3];			/**< MAC address. */
+	uint16_t flags;				/**< Flags. */
+	uint32_t vnet_id;			/**< Virtual net ID. */
+	uint32_t tunnel_id;			/**< Tunnel ID. */
+	uint16_t policy_id;			/**< Policy ID. */
+};
+
+/**
+ * nss_pvxlan_msg
+ *	Data for sending and receiving proxy VxLAN messages.
+ */
+struct nss_pvxlan_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a proxy VxLAN common message.
+	 */
+	union {
+		struct nss_pvxlan_stats_msg stats;
+				/**< Proxy VxLAN statistics. */
+		struct nss_pvxlan_rule_msg rule_cfg;
+				/**< Rule information. */
+		struct nss_pvxlan_rule_msg rule_uncfg;
+				/**< Rule information. */
+		struct nss_pvxlan_tunnel_state_msg enable;
+				/**< Enable the tunnel. */
+		struct nss_pvxlan_mac_msg mac_add;
+				/**< MAC rule add message. */
+		struct nss_pvxlan_mac_msg mac_del;
+				/**< MAC rule delete message. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving proxy VxLAN tunnel data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_pvxlan_buf_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for receiving proxy VxLAN tunnel messages.
+ *
+ * @datatypes
+ * nss_pvxlan_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_pvxlan_msg_callback_t)(void *app_data, struct nss_pvxlan_msg *msg);
+
+/**
+ * nss_pvxlan_tx_msg
+ *	Sends proxy VxLAN tunnel messages to the NSS.
+ *
+ * Do not call this function from a softirq or interrupt because it
+ * might sleep if the NSS firmware is busy serving another host thread.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_pvxlan_msg
+ *
+ * @param[in]     nss_ctx  Pointer to the NSS context.
+ * @param[in,out] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_pvxlan_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_pvxlan_msg *msg);
+
+/**
+ * nss_pvxlan_tx_msg_sync
+ *	Sends proxy VxLAN tunnel messages to the NSS.
+ *
+ * Do not call this function from a softirq or interrupt because it
+ * might sleep if the NSS firmware is busy serving another host thread.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_pvxlan_msg
+ *
+ * @param[in]     nss_ctx  Pointer to the NSS context.
+ * @param[in,out] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_pvxlan_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_pvxlan_msg *msg);
+
+/**
+ * nss_pvxlan_tx_buf
+ *	Sends a proxy VXLAN tunnel data buffer to the NSS interface.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] buf   Pointer to the data buffer.
+ * @param[in] if_num   NSS interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_pvxlan_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *buf, uint32_t if_num);
+
+/**
+ * nss_pvxlan_unregister
+ *	Deregisters the proxy VxLAN tunnel interface from the NSS interface.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * TRUE or FALSE
+ *
+ * @dependencies
+ * The tunnel interface must have been previously registered.
+ */
+extern bool nss_pvxlan_unregister(uint32_t if_num);
+
+/**
+ * nss_pvxlan_register
+ *	Registers the proxy VxLAN tunnel interface with the NSS for sending and
+ *	receiving tunnel messages.
+ *
+ * @datatypes
+ * nss_pvxlan_msg_callback_t \n
+ * nss_pvxlan_buf_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num           NSS interface number.
+ * @param[in] data_cb          Data callback for the proxy VXLAN tunnel data.
+ * @param[in] notify_cb        Notify callback for the proxy VXLAN tunnel data.
+ * @param[in] netdev           Pointer to the associated network device.
+ * @param[in] features         Data socket buffer types supported by this interface.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_pvxlan_register(uint32_t if_num, nss_pvxlan_buf_callback_t data_cb,
+			nss_pvxlan_msg_callback_t notify_cb, struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_pvxlan_get_ctx
+ *	Gets the NSS context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_pvxlan_get_ctx(void);
+
+/**
+ * nss_pvxlan_ifnum_with_core_id
+ *	Gets the proxy VxLAN interface number with the core ID.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * Interface number with the core ID.
+ */
+extern int nss_pvxlan_ifnum_with_core_id(int if_num);
+
+/**
+ * nss_pvxlan_init
+ *	Initializes the proxy VXLAN interface.
+ *
+ * @return
+ * None.
+ */
+extern void nss_pvxlan_init(void);
+
+/**
+ * nss_pvxlan_msg_init
+ *	Initializes a proxy VxLAN message.
+ *
+ * @datatypes
+ * nss_pvxlan_msg \n
+ * nss_pvxlan_msg_callback_t
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_pvxlan_msg_init(struct nss_pvxlan_msg *ncm, uint16_t if_num, uint32_t type, uint32_t len,
+								nss_pvxlan_msg_callback_t cb, void *app_data);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_PVXLAN_H */
diff --git a/qca-nss-drv/exports/nss_qrfs.h b/qca-nss-drv/exports/nss_qrfs.h
new file mode 100644
index 0000000..486baf9
--- /dev/null
+++ b/qca-nss-drv/exports/nss_qrfs.h
@@ -0,0 +1,193 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_qrfs.h
+ *	NSS QRFS interface definitions.
+ */
+
+#ifndef __NSS_QRFS_H
+#define __NSS_QRFS_H
+
+/**
+ * @addtogroup nss_qrfs_subsystem
+ * @{
+ */
+
+/**
+ * nss_qrfs_msg_types
+ *	Message types for the NSS QRFS.
+ */
+enum nss_qrfs_msg_types {
+	NSS_QRFS_MSG_FLOW_ADD,
+	NSS_QRFS_MSG_FLOW_DELETE,
+	NSS_QRFS_MSG_MAC_ADD,
+	NSS_QRFS_MSG_MAC_DELETE,
+	NSS_QRFS_MSG_STATS_SYNC,
+	NSS_QRFS_MSG_MAX,
+};
+
+/**
+ * nss_qrfs_error_types
+ *	Error types for the NSS QRFS.
+ */
+enum nss_qrfs_error_types {
+	NSS_QRFS_ERROR_INVALID_MSG_TYPE,
+	NSS_QRFS_ERROR_INVALID_MSG_SIZE,
+	NSS_QRFS_ERROR_INVALID_IP_VERSION,
+	NSS_QRFS_ERROR_V4_FLOW_TABLE_FULL,
+	NSS_QRFS_ERROR_V6_FLOW_TABLE_FULL,
+	NSS_QRFS_ERROR_MAC_TABLE_FULL,
+	NSS_QRFS_ERROR_MAX,
+};
+
+/**
+ * nss_qrfs_flow_rule_msg
+ *	Information for the NSS QRFS flow rule message.
+ */
+struct nss_qrfs_flow_rule_msg {
+	uint16_t src_port;		/**< Source port. */
+	uint16_t dst_port;		/**< Destination port. */
+	uint32_t ip_version;		/**< IPv4:4 IPv6:6. */
+	uint32_t src_addr[4];		/**< Source IP address. */
+	uint32_t dst_addr[4];		/**< Destination IP address. */
+	uint16_t protocol;		/**< IP protocol. */
+	uint16_t cpu;			/**< CPU core ID. */
+	uint32_t if_num;		/**< Physical interface number. */
+};
+
+/**
+ * nss_qrfs_mac_rule_msg
+ *	Information for the NSS QRFS MAC rule message.
+ */
+struct nss_qrfs_mac_rule_msg {
+	uint8_t mac[ETH_ALEN];	/**< Ethernet address. */
+	uint16_t cpu;		/**< CPU core ID. */
+	uint32_t if_num;	/**< Physical interface number. */
+};
+
+/**
+ * nss_qrfs_stats_sync_msg
+ *	Information for the NSS QRFS statistics message.
+ */
+struct nss_qrfs_stats_sync_msg {
+	struct nss_cmn_node_stats node_stats;	/**< Common pnode statistics. */
+	uint32_t invalid_offset;		/**< Packets with invalid offset. */
+	uint32_t unknown_protocol;		/**< Protocol other than TCP, UDP. */
+	uint32_t ipv4_flow_rule_hits;		/**< Number of IPv4 flow rule hits. */
+	uint32_t ipv6_flow_rule_hits;		/**< Number of IPv6 flow rule hits. */
+};
+
+/**
+ * nss_qrfs_msg
+ *	Data for sending and receiving NSS QRFS rule or statistics messages.
+ */
+struct nss_qrfs_msg {
+	struct nss_cmn_msg cm;	/**< Common message header. */
+
+	/**
+	 * Payload of a NSS QRFS rule or statistics message.
+	 */
+	union {
+		struct nss_qrfs_flow_rule_msg flow_add;		/**< Add flow rule. */
+		struct nss_qrfs_flow_rule_msg flow_delete;	/**< Delete flow rule. */
+		struct nss_qrfs_mac_rule_msg mac_add;		/**< Add MAC rule. */
+		struct nss_qrfs_mac_rule_msg mac_delete;	/**< Delete MAC rule. */
+		struct nss_qrfs_stats_sync_msg stats_sync;	/**< Synchronize statistics. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving QRFS messages.
+ *
+ * @datatypes
+ * nss_qrfs_msg
+ *
+ * @param[in] app_data Pointer to the application context of the message.
+ * @param[in] msg      Pointer to the message data.
+ */
+typedef void (*nss_qrfs_msg_callback_t)(void *app_data, struct nss_qrfs_msg *msg);
+
+/**
+ * nss_qrfs_register_handler
+ *	Registers the QRFS interface with the NSS for sending and receiving
+ *	messages.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @return
+ * None.
+ */
+void nss_qrfs_register_handler(struct nss_ctx_instance *nss_ctx);
+
+/**
+ * nss_qrfs_notify_register
+ *	Registers a notifier callback for QRFS messages with the NSS.
+ *
+ * @datatypes
+ * nss_qrfs_msg_callback_t
+ *
+ * @param[in] core      NSS core number index to the notifier callback table.
+ * @param[in] cb        Callback function for the message.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_qrfs_notify_register(int core, nss_qrfs_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_qrfs_notify_unregister
+ *	Deregisters a QRFS message notifier callback from the NSS.
+ *
+ * @param[in] core  NSS core number index to the notifier callback table.
+ *
+ * @return
+ * None.
+ */
+void nss_qrfs_notify_unregister(int core);
+
+/**
+ * nss_qrfs_set_flow_rule
+ *	Sends a QRFS message to the NSS core to set the flow rule.
+ *
+ * @datatypes
+ * sk_buff
+ *
+ * @param[in] skb     Pointer to the SKB buffer.
+ * @param[in] cpu     CPU number to set in the flow table.
+ * @param[in] action  Action to perform on the flow table.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_qrfs_set_flow_rule(struct sk_buff *skb, uint32_t cpu, uint32_t action);
+
+/**
+ * nss_qrfs_init
+ *	Initializes the QRFS.
+ *
+ * @return
+ * None.
+ */
+void nss_qrfs_init(void);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_QRFS_H */
diff --git a/qca-nss-drv/exports/nss_qvpn.h b/qca-nss-drv/exports/nss_qvpn.h
new file mode 100644
index 0000000..931da43
--- /dev/null
+++ b/qca-nss-drv/exports/nss_qvpn.h
@@ -0,0 +1,522 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_qvpn.h
+ *	NSS QVPN interface definitions.
+ */
+
+#ifndef _NSS_QVPN_H_
+#define _NSS_QVPN_H_
+
+/**
+ * @addtogroup nss_qvpn_subsystem
+ * @{
+ */
+
+#define NSS_QVPN_CMDS_MAX 10			/**< Maximum number of QVPN commands supported. */
+#define NSS_QVPN_VPN_HDR_HEAD_SIZE_MAX 64	/**< Maximum size of QVPN header. */
+#define NSS_QVPN_VPN_HDR_TAIL_SIZE_MAX 32	/**< Maximum size of QVPN tail. */
+#define NSS_QVPN_IV_SIZE_MAX 16			/**< Maximum size of IV supported. */
+#define NSS_QVPN_SESS_ID_SIZE_MAX 8		/**< Maximum size of session ID. */
+
+/*
+ * QVPN L3/L4 header flags.
+ */
+#define NSS_QVPN_HDR_FLAG_IPV6   0x0001		/**< Outer L3 header is IPv6. */
+#define NSS_QVPN_HDR_FLAG_L4_UDP 0x0002		/**< L4 is UDP. */
+
+/**
+ * nss_qvpn_msg_type
+ *	Message types for QVPN NSS firmware.
+ */
+enum nss_qvpn_msg_type {
+	NSS_QVPN_MSG_TYPE_TUNNEL_CONFIGURE,	/**< Configure QVPN tunnel instance. */
+	NSS_QVPN_MSG_TYPE_TUNNEL_DECONFIGURE,	/**< Deconfigure QVPN tunnel instance. */
+	NSS_QVPN_MSG_TYPE_CRYPTO_KEY_ADD,	/**< Add a new crypto key. */
+	NSS_QVPN_MSG_TYPE_CRYPTO_KEY_DEL,	/**< Delete crypto key. */
+	NSS_QVPN_MSG_TYPE_CRYPTO_KEY_ACTIVATE,	/**< Activate crypto key. */
+	NSS_QVPN_MSG_TYPE_CRYPTO_KEY_DEACTIVATE,/**< Deactivate crypto key. */
+	NSS_QVPN_MSG_TYPE_SYNC_STATS,		/**< Statistics synchronization. */
+	NSS_QVPN_MSG_TYPE_MAX			/**< Maximum QVPN message type. */
+};
+
+/**
+ * nss_qvpn_cmds_type
+ *	Processing commands for QVPN.
+ */
+enum nss_qvpn_cmds_type {
+	NSS_QVPN_CMDS_TYPE_NONE,		/**< Add VPN header to packet. */
+	NSS_QVPN_CMDS_TYPE_ADD_VPN_HDR,		/**< Add VPN header to packet. */
+	NSS_QVPN_CMDS_TYPE_REMOVE_VPN_HDR,	/**< Remove VPN header from packet. */
+	NSS_QVPN_CMDS_TYPE_ADD_L3_L4_HDR,	/**< Add L3/L4 header to packet. */
+	NSS_QVPN_CMDS_TYPE_REMOVE_L3_L4_HDR,	/**< Remove L3/L4 header from packet. */
+	NSS_QVPN_CMDS_TYPE_ENCRYPT,		/**< Send packet for encryption. */
+	NSS_QVPN_CMDS_TYPE_DECRYPT,		/**< Send packet for decryption. */
+	NSS_QVPN_CMDS_TYPE_ANTI_REPLAY,		/**< Sequence number processing. */
+	NSS_QVPN_CMDS_TYPE_MAX			/**< Maximum command supported. */
+};
+
+/**
+ * nss_qvpn_profile
+ *	QVPN profiles supported.
+ */
+enum nss_qvpn_profile {
+	NSS_QVPN_PROFILE_NONE,		/**< No profile supported. */
+	NSS_QVPN_PROFILE_CRYPTO_ENCAP,	/**< Encapsulation profile with crypto enabled. */
+	NSS_QVPN_PROFILE_CRYPTO_DECAP,	/**< Decapsulation profile with crypto enabled. */
+	NSS_QVPN_PROFILE_ENCAP,		/**< Encapsulation Profile with crypto disabled. */
+	NSS_QVPN_PROFILE_DECAP,		/**< Decapsulation Profile with crypto disabled. */
+	NSS_QVPN_PROFILE_MAX,		/**< Maximum profile. */
+};
+
+/**
+ * nss_qvpn_pkt_drop_event
+ *	Packets drop statistics from QVPN node.
+ */
+enum nss_qvpn_pkt_drop_event {
+	NSS_QVPN_PKT_DROP_EVENT_NO_TAILROOM,		/**< Packet tail room not enough to copy HMAC to tail. */
+	NSS_QVPN_PKT_DROP_EVENT_NO_HEADROOM,		/**< Packet head room not enough to add QVPN headers. */
+	NSS_QVPN_PKT_DROP_EVENT_CBUF_ALLOC_FAIL,	/**< Received packet dropped as crypto buffer allocation failed. */
+	NSS_QVPN_PKT_DROP_EVENT_PBUF_ALLOC_FAIL,	/**< Received packet dropped as associated pbuf allocation failed. */
+	NSS_QVPN_PKT_DROP_EVENT_SYNC_ALLOC_FAIL,	/**< Pbuf dropped while doing statistics synchronization. */
+	NSS_QVPN_PKT_DROP_EVENT_PBUF_UNALIGN,		/**< Received packet dropped as unaligned buffer. */
+	NSS_QVPN_PKT_DROP_EVENT_CRYPTO_ENQ_FAIL,	/**< Received packet dropped as crypto enqueue failed. */
+	NSS_QVPN_PKT_DROP_EVENT_LINEAR_COPY_FAIL,	/**< Received packet dropped as scatter-gather linear copy failed. */
+	NSS_QVPN_PKT_DROP_EVENT_FWD_ENQ_FAIL,		/**< Received packet dropped as enqueue to next node failed. */
+	NSS_QVPN_PKT_DROP_EVENT_POST_CRYPTO_Q_FULL,	/**< Post crypto queue is full dropping pbuf. */
+	NSS_QVPN_PKT_DROP_EVENT_NODE_INACTIVE,		/**< Node is inactive dropping crypto processed packet. */
+	NSS_QVPN_PKT_DROP_EVENT_NON_CRYPTO_PB,		/**< Non crypto processed packet enqueued to post crypto queue. */
+	NSS_QVPN_PKT_DROP_EVENT_PAD_INVALID,		/**< Packet received with invalid padding. */
+	NSS_QVPN_PKT_DROP_EVENT_BLK_UNALIGNED,		/**< Received pbuf length is not cipher block aligned. */
+	NSS_QVPN_PKT_DROP_EVENT_MAX			/**< End of packet drop event list. */
+};
+
+/**
+ * nss_qvpn_exception_event
+ *	Exception events from QVPN node.
+ */
+enum nss_qvpn_exception_event {
+	NSS_QVPN_EXCEPTION_EVENT_RX_CONTROL_PKT,	/**< QVPN control packet received. */
+	NSS_QVPN_EXCEPTION_EVENT_RX_TAIL_NOSUPP,	/**< Protocol with tail not supported. */
+	QVPN_TUN_EXCEPTION_EVENT_RX__HR_INSUFF,		/**< Insufficient headroom. */
+	NSS_QVPN_EXCEPTION_EVENT_RX_SESS_ID_INVALID,	/**< Invalid session ID. */
+	NSS_QVPN_EXCEPTION_EVENT_RX_DATA_PKT,		/**< Data packets exceptioned to host. */
+	NSS_QVPN_EXCEPTION_EVENT_RX_MALFORMED,		/**< Malformed packet received. */
+	NSS_QVPN_EXCEPTION_EVENT_MAX			/**< End of exception event list. */
+};
+
+/**
+ * nss_qvpn_error_type
+ *	Error types for the QVPN interface.
+ */
+enum nss_qvpn_error_type {
+	NSS_QVPN_ERROR_TYPE_NONE,			/**< No error. */
+	NSS_QVPN_ERROR_TYPE_UNKNOWN_MSG,		/**< Unknown message. */
+	NSS_QVPN_ERROR_TUN_ALREADY_CONFIGURED,		/**< Tunnel already configured. */
+	NSS_QVPN_ERROR_TYPE_IF_INVALID,			/**< Invalid interface. */
+	NSS_QVPN_ERROR_TYPE_SIBLING_IF,			/**< Invalid sibling interface number. */
+	NSS_QVPN_ERROR_TYPE_IV_SIZE_INVALID,		/**< Invalid IV size. */
+	NSS_QVPN_ERROR_TYPE_HMAC_SIZE_INVALID,		/**< Invalid HMAC size. */
+	NSS_QVPN_ERROR_TYPE_CRYPTO_BLK_SIZE_INVALID,	/**< Invalid crypto block size. */
+	NSS_QVPN_ERROR_TYPE_SESSION_IDX_SIZE_INVALID,	/**< Invalid session index size. */
+	NSS_QVPN_ERROR_TYPE_CMD_NOT_SUPPORTED,		/**< Command not supported. */
+	NSS_QVPN_ERROR_TYPE_L4_PROTO_INVALID,		/**< L4 protocol encapsulation is not supported. */
+	NSS_QVPN_ERROR_TYPE_SIBLING_IF_TYPE,		/**< Invalid sibling interface type. */
+	NSS_QVPN_ERROR_TYPE_CMDS_COUNT_INVALID,		/**< Total number of commands is invalid. */
+	NSS_QVPN_ERROR_TYPE_ENTRY_NOT_FOUND,		/**< Entry not found. */
+	NSS_QVPN_ERROR_TYPE_ENTRY_NOT_ACTIVE,		/**< Entry not active. */
+	NSS_QVPN_ERROR_TYPE_ENTRY_ALREADY_ACTIVE,	/**< Entry already active. */
+	NSS_QVPN_ERROR_TYPE_CRYPTO_IDX_MISMATCH,	/**< Invalid crypto index. */
+	NSS_QVPN_ERROR_TYPE_KI_ALLOC_FAIL,		/**< Key information allocation failure. */
+	NSS_QVPN_ERROR_TYPE_PROFILE_INVALID,		/**< Invalid command profile. */
+	NSS_QVPN_ERROR_TYPE_RX_TAIL_NOSUPP,		/**< VPN with tail not supported. */
+	NSS_QVPN_ERROR_TYPE_MAX				/**< End of error list. */
+};
+
+/**
+ * nss_qvpn_iv_type
+ *	IV type for generating and copying in packet.
+ */
+enum nss_qvpn_iv_type {
+	NSS_QVPN_IV_TYPE_NONE,		/**< No IV. */
+	NSS_QVPN_IV_TYPE_STATIC,	/**< Use static IV configured. */
+	NSS_QVPN_IV_TYPE_DYNAMIC_RAND,	/**< Generate IV randomly. */
+	NSS_QVPN_IV_TYPE_MAX		/**< End of IV type list. */
+};
+
+/**
+ * nss_qvpn_pad_type
+ *	Pad type for generating and copying in packet.
+ */
+enum nss_qvpn_pad_type {
+	NSS_QVPN_PAD_TYPE_NONE,		/**< No padding. */
+	NSS_QVPN_PAD_TYPE_PKCS7,	/**< Generate pad buffer using PKCS7. */
+	NSS_QVPN_PAD_TYPE_INC,		/**< Generate pad buffer monotonically increasing sequence. */
+	NSS_QVPN_PAD_TYPE_MAX		/**< End of pad type. */
+};
+
+/**
+ * nss_qvpn_anti_replay_alg
+ *	Anti-replay algorithms supported.
+ */
+enum nss_qvpn_anti_replay_alg {
+	NSS_QVPN_ANTI_REPLAY_ALG_NONE,			/**< No anti-replay. */
+	NSS_QVPN_ANTI_REPLAY_ALG_REPLAY_WINDOW,		/**< Generate pad buffer monotonically increasing sequence. */
+	NSS_QVPN_ANTI_REPLAY_ALG_MAX			/**< End of anti-replay algorithm. */
+};
+
+/**
+ * nss_qvpn_crypto_mode
+ *	Crypto modes supported.
+ */
+enum nss_qvpn_crypto_mode {
+	NSS_QVPN_CRYPTO_MODE_NONE,		/**< NULL cipher and NULL authentication. */
+	NSS_QVPN_CRYPTO_MODE_ENC,		/**< Encryption only. */
+	NSS_QVPN_CRYPTO_MODE_DEC,		/**< Decryption only. */
+	NSS_QVPN_CRYPTO_MODE_AUTH,		/**< Authentication only. */
+	NSS_QVPN_CRYPTO_MODE_ENC_AUTH,		/**< Encryption and then authentication. */
+	NSS_QVPN_CRYPTO_MODE_AUTH_DEC,		/**< Authentication and then decryption. */
+	NSS_QVPN_CRYPTO_MODE_AUTH_ENC,		/**< Authentication and then encryption. */
+	NSS_QVPN_CRYPTO_MODE_DEC_AUTH,		/**< Decryption and then authentication. */
+	NSS_QVPN_CRYPTO_MODE_MAX		/**< End of crypto mode. */
+};
+
+/**
+ * nss_qvpn_hdr_configure_msg
+ *	QVPN header configuration.
+ */
+struct nss_qvpn_hdr_configure_msg {
+	uint32_t src_ip[4];					/**< Source IP address. */
+	uint32_t dst_ip[4];					/**< Destination IP address. */
+	uint16_t src_port;					/**< Source port. */
+	uint16_t dst_port;					/**< Destination port. */
+	uint16_t hdr_flags;					/**< Header flags. */
+	uint16_t seqnum_size;					/**< Size of sequence number. */
+	uint16_t seqnum_offset;					/**< Sequence number offset. */
+	uint16_t anti_replay_alg;				/**< Anti-replay algorithm. */
+	uint16_t session_id_size;				/**< Session ID size. */
+	uint16_t session_id_offset;				/**< Session ID offset. */
+	uint16_t vpn_hdr_head_size;				/**< VPN header size. */
+	uint16_t vpn_hdr_head_offset;				/**< VPN header offset. */
+	uint16_t vpn_hdr_tail_size;				/**< Size of tail. */
+	uint16_t res;						/**< Reserved for alignment. */
+	uint8_t vpn_hdr_head[NSS_QVPN_VPN_HDR_HEAD_SIZE_MAX];	/**< Content of VPN header. */
+	uint8_t vpn_hdr_tail[NSS_QVPN_VPN_HDR_TAIL_SIZE_MAX];	/**< VPN header tail content. */
+	uint8_t hop_limit;					/**< TTL or hop limit. */
+	uint8_t res1[3];					/**< Reserved for alignment. */
+};
+
+/**
+ * nss_qvpn_crypto_configure_msg
+ *	QVPN crypto configuration message.
+ */
+struct nss_qvpn_crypto_configure_msg {
+	uint16_t hmac_len;			/**< Length of HMAC to copy. */
+	uint16_t hmac_offset;			/**< Offset to copy HMAC. */
+	uint16_t auth_offset;			/**< Data offset to start authentication. */
+	uint16_t cipher_op_offset;		/**< Start of cipher data. */
+	uint16_t cipher_blk_size;		/**< Cipher block size. */
+	uint16_t pad_type;			/**< Pad algorithm. */
+	uint16_t crypto_mode;			/**< Crypto mode. */
+	uint16_t iv_len;			/**< Length of IV. */
+	uint16_t iv_offset;			/**< IV offset. */
+	uint16_t iv_type;			/**< IV generation algorithm. */
+	uint8_t iv_val[NSS_QVPN_IV_SIZE_MAX];	/**< IV to be used. */
+};
+
+/**
+ * nss_qvpn_crypto_key_add_msg
+ *	QVPN key add message.
+ */
+struct nss_qvpn_crypto_key_add_msg {
+	uint32_t crypto_idx;				/**< Crypto session ID. */
+	uint8_t session_id[NSS_QVPN_SESS_ID_SIZE_MAX];	/**< Session ID. */
+};
+
+/**
+ * nss_qvpn_crypto_key_del_msg
+ *	Delete/Deactivate key message.
+ */
+struct nss_qvpn_crypto_key_del_msg {
+	uint32_t crypto_idx;	/**< Crypto index to delete/deactivate. */
+};
+
+/**
+ * nss_qvpn_tunnel_config_msg
+ *	QVPN tunnel configure message.
+ */
+struct nss_qvpn_tunnel_config_msg {
+	uint32_t sibling_if;					/**< Sibling interface number. */
+	uint16_t total_cmds;					/**< Total number of commands. */
+	uint16_t cmd_profile;					/**< Command processing profile. */
+	uint16_t cmd[NSS_QVPN_CMDS_MAX];			/**< Commands to execute. */
+	struct nss_qvpn_crypto_key_add_msg crypto_key;		/**< Initial crypto key. */
+	struct nss_qvpn_hdr_configure_msg hdr_cfg;		/**< VPN header configuration. */
+	struct nss_qvpn_crypto_configure_msg crypto_cfg;	/**< Crypto configuration. */
+};
+
+/**
+ * nss_qvpn_crypto_key_activate_msg
+ *	Activate key message.
+ */
+struct nss_qvpn_crypto_key_activate_msg {
+	uint32_t crypto_idx;					/**< Crypto session ID. */
+	uint8_t vpn_hdr_head[NSS_QVPN_VPN_HDR_HEAD_SIZE_MAX];	/**< Content of VPN header. */
+};
+
+/**
+ * nss_qvpn_stats_sync_msg
+ *	Message information for QVPN synchronization statistics.
+ */
+struct nss_qvpn_stats_sync_msg {
+	struct nss_cmn_node_stats node_stats;				/**< Common node statistics. */
+	uint32_t crypto_resp_error[NSS_CRYPTO_CMN_RESP_ERROR_MAX];	/**< Crypto response errors. */
+	uint32_t pkt_drop_event[NSS_QVPN_PKT_DROP_EVENT_MAX];		/**< Packet drop events. */
+	uint32_t exception_event[NSS_QVPN_EXCEPTION_EVENT_MAX];		/**< QVPN exception events. */
+};
+
+/**
+ * nss_qvpn_stats_notification
+ *	QVPN transmission statistics structure.
+ */
+struct nss_qvpn_stats_notification {
+	uint64_t stats_ctx[NSS_STATS_NODE_MAX];		/**< Context transmission statistics. */
+	uint32_t core_id;				/**< Core ID. */
+	uint32_t if_num;				/**< Interface number. */
+};
+
+/**
+ * nss_qvpn_msg
+ *	QVPN message structure for configuration and statistics.
+ */
+struct nss_qvpn_msg {
+	struct nss_cmn_msg cm;							/**< Common message header. */
+
+	/**< QVPN configuration messages. */
+	union {
+		struct nss_qvpn_tunnel_config_msg tunnel_config;		/**< QVPN tunnel configure message. */
+		struct nss_qvpn_crypto_key_add_msg key_add;			/**< Crypto key add message. */
+		struct nss_qvpn_crypto_key_del_msg key_del;			/**< Crypto key delete message. */
+		struct nss_qvpn_crypto_key_activate_msg key_activate;		/**< Crypto key active message. */
+		struct nss_qvpn_stats_sync_msg stats;				/**< QVPN statistics synchronization message. */
+	} msg;	/**< QVPN configuration message. */
+};
+
+/**
+ * nss_qvpn_tx_msg
+ *	Sends an QVPN message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_qvpn_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_qvpn_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_qvpn_msg *msg);
+
+/**
+ * nss_qvpn_tx_msg_sync
+ *	Sends an QVPN message to the NSS synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_qvpn_msg \n
+ * nss_qvpn_msg_type \n
+ * nss_qvpn_error_type
+ *
+ * @param[in]     nss_ctx  Pointer to the NSS context.
+ * @param[in]     nvm      Pointer to the message data.
+ * @param[in]     if_num   NSS interface number.
+ * @param[in]     type     Type of message.
+ * @param[in]     len      Size of the payload.
+ * @param[in,out] resp     Response for the configuration.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_qvpn_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_qvpn_msg *nvm,
+		uint32_t if_num, enum nss_qvpn_msg_type type, uint16_t len,
+		enum nss_qvpn_error_type *resp);
+
+/**
+ * nss_qvpn_tx_buf
+ *	Sends data packet for QVPN encapsulation/decapsulation.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] if_num   NSS interface number.
+ * @param[in] skb      Pointer to sk_buff.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_qvpn_tx_buf(struct nss_ctx_instance *nss_ctx, uint32_t if_num, struct sk_buff *skb);
+
+/**
+ * nss_qvpn_msg_init
+ *	Initializes an QVPN message.
+ *
+ * @datatypes
+ * nss_qvpn_msg
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Pointer to the message callback.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+void nss_qvpn_msg_init(struct nss_qvpn_msg *ncm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data);
+
+/**
+ * nss_qvpn_get_context
+ *	Gets the QVPN context used in nss_qvpn_tx.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_qvpn_get_context(void);
+
+/**
+ * Callback when QVPN data is received.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_qvpn_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback to receive QVPN messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_qvpn_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * nss_qvpn_unregister_if
+ *	Deregisters the QVPN interface from the NSS.
+ *
+ * @param[in] if_num              NSS interface number.
+ *
+ * @return
+ * None.
+ */
+void nss_qvpn_unregister_if(uint32_t if_num);
+
+/**
+ * nss_qvpn_register_if
+ *	Register to send/receive QVPN messages to NSS.
+ *
+ * @datatypes
+ * nss_qvpn_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num               NSS interface number.
+ * @param[in] qvpn_data_callback   Callback for the data.
+ * @param[in] qvpn_event_callback  Callback for receiving events.
+ * @param[in] netdev               Pointer to the associated network device.
+ * @param[in] features             Data socket buffer types supported by this interface.
+ * @param[in] app_ctx              Pointer to the application context of the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_qvpn_register_if(uint32_t if_num, nss_qvpn_callback_t qvpn_data_callback,
+			nss_qvpn_msg_callback_t qvpn_event_callback, struct net_device *netdev,
+			uint32_t features, void *app_ctx);
+
+/**
+ * nss_qvpn_ifnum_with_core_id
+ *	Gets the QVPN interface number with the core ID.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * Interface number with the core ID.
+ */
+int nss_qvpn_ifnum_with_core_id(int if_num);
+
+/**
+ * nss_qvpn_register_handler
+ *	Registers the QVPN handler with the NSS.
+ *
+ * @return
+ * None.
+ */
+void nss_qvpn_register_handler(void);
+
+/**
+ * nss_qvpn_ifmap_get
+ *	Returns active QVPN interfaces.
+ *
+ * @return
+ * Pointer to interface map.
+ */
+unsigned long *nss_qvpn_ifmap_get(void);
+
+/**
+ * nss_qvpn_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_qvpn_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * nss_qvpn_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_qvpn_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * @}
+ */
+
+#endif /* _NSS_QVPN_H_ */
diff --git a/qca-nss-drv/exports/nss_rmnet_rx.h b/qca-nss-drv/exports/nss_rmnet_rx.h
new file mode 100644
index 0000000..2b7e715
--- /dev/null
+++ b/qca-nss-drv/exports/nss_rmnet_rx.h
@@ -0,0 +1,392 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_rmnet_rx.h
+ *	NSS RMNET interface message Structure and APIs
+ */
+
+#ifndef __NSS_RMNET_RX_H
+#define __NSS_RMNET_RX_H
+
+#include "nss_if.h"
+
+/**
+ * @addtogroup nss_rmnet_subsystem
+ * @{
+ */
+
+/**
+ * Maximum number of DMA channel.
+ */
+#define NSS_RMNET_RX_CHANNEL_MAX 12
+
+/**
+ * nss_rmnet_rx_dp_type
+ *	Interface datapath types. NSS-to-host path will be seen by ECM for rules.
+ */
+enum nss_rmnet_rx_dp_type {
+	NSS_RMNET_RX_DP_N2H,	/**< Interface on NSS-to-host path has zero value. */
+	NSS_RMNET_RX_DP_H2N,	/**< Interface on host-to-NSS path has non-zero value. */
+};
+
+/**
+ * nss_rmnet_rx_msg_types
+ *	Message types for interface requests and responses.
+ */
+enum nss_rmnet_rx_msg_types {
+	NSS_RMNET_RX_TX_CONFIG_MSG = NSS_IF_MAX_MSG_TYPES + 1,
+					/**< Configuration message. */
+	NSS_RMNET_RX_STATS_SYNC_MSG,	/**< Statistic synchronization message. */
+	NSS_RMNET_RX_MAX_MSG_TYPES,	/**< Maximum message type. */
+};
+
+/**
+ * nss_rmnet_rx_error_types
+ *	Error types for the RMNET interface.
+ */
+enum nss_rmnet_rx_error_types {
+	NSS_RMNET_RX_SUCCESS,				/**< No error. */
+	NSS_RMNET_RX_ERROR_TYPE_MSG_UNKNOWN,		/**< Unknown message type. */
+	NSS_RMNET_RX_ERROR_TYPE_ALREADY_CONFIGURED,	/**< Tunnel is already configured. */
+	NSS_RMNET_RX_ERROR_TYPE_SIBLING_NOTFOUND,	/**< Sibling interface is not found. */
+	NSS_RMNET_RX_ERROR_TYPE_NEXTHOP_NOTFOUND,	/**< Next hop is not found. */
+	NSS_RMNET_RX_ERROR_TYPE_SIBLING_MISMATCH,	/**< Sibling interface type mismatches. */
+	NSS_RMNET_RX_ERROR_TYPE_DMA_CHANNEL_FAIL,	/**< DMA Channel allocation failed. */
+	NSS_RMNET_RX_ERROR_TYPE_RMNET_INVALID,		/**< Interface type is invalid. */
+	NSS_RMNET_RX_ERROR_TYPE_SHAPER_INVALID,		/**< Shaper is invalid. */
+	NSS_RMNET_RX_REG_FAILURE,			/**< Registration failed. */
+	NSS_RMNET_RX_ALLOC_FAILURE,			/**< Memory allocation failed. */
+	NSS_RMNET_RX_ERROR_MAX,				/**< Maximum error type. */
+};
+
+/**
+ * nss_rmnet_rx_pvt
+ *	Private data information for the interface.
+ */
+struct nss_rmnet_rx_pvt {
+	struct semaphore sem;
+			/**< Semaphore to ensure that only one instance of a message is sent to the NSS. */
+	struct completion complete;
+			/**< Waits for message completion or time out. */
+	int response;		/**< Message process response from the NSS firmware. */
+	int sem_init_done;	/**< Semaphore initialization is done. */
+};
+
+/**
+ * nss_rmnet_rx_config_msg
+ *	Message information for configuring the interface.
+ */
+struct nss_rmnet_rx_config_msg {
+	uint32_t flags;			/**< Interface flags. */
+	uint32_t sibling;		/**< Sibling interface number. */
+	uint32_t nexthop;		/**< Next hop interface number. */
+	uint32_t no_channel;		/**< Number of channels. */
+};
+
+/**
+ * nss_rmnet_rx_stats
+ *	Interface statistics received from the NSS.
+ */
+struct nss_rmnet_rx_stats {
+	struct nss_cmn_node_stats node_stats;
+					/**< Common statistics. */
+	uint32_t enqueue_failed;	/**< Enqueue to next node is failed. */
+	uint32_t no_avail_channel;	/**< No available DMA channel. */
+	uint32_t num_linear_pbuf;	/**< Number of linear pbufs. */
+	uint32_t no_pbuf_to_linear;	/**< No pbuf to linearize. */
+	uint32_t no_enough_room;	/**< Not enough headroom to linearize the pbuf. */
+	uint32_t using_channel[NSS_RMNET_RX_CHANNEL_MAX];
+					/**< How many times a channel is used. */
+	uint32_t dma_failed;		/**< DMA copy call failed. */
+};
+
+
+/**
+ * nss_rmnet_rx_msg
+ *	Data for sending and receiving interface messages.
+ */
+struct nss_rmnet_rx_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of an RMNET interface message.
+	 */
+	union {
+		struct nss_rmnet_rx_config_msg if_config;
+				/**< Rule for creating an RMNET interface. */
+		struct nss_rmnet_rx_stats stats;
+				/**< RMNET interface statistics. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback to transmit interface data received from NSS
+ * to the transmit path of the RMNET interface.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ */
+typedef void (*nss_rmnet_rx_xmit_callback_t)(struct net_device *netdev, struct sk_buff *skb);
+
+/**
+ * Callback function for interface data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_rmnet_rx_data_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for interface messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_rmnet_rx_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * nss_rmnet_rx_handle
+ *	Context information for NSS communication.
+ */
+struct nss_rmnet_rx_handle {
+	struct nss_ctx_instance *nss_ctx;	/**< NSS context. */
+	int32_t if_num_n2h;			/**< Redirect interface number on NSS-to-host path. */
+	int32_t if_num_h2n;			/**< Redirect interface number on host-to-NSS path. */
+	struct net_device *ndev;		/**< Associated network device. */
+	struct nss_rmnet_rx_pvt *pvt;		/**< Private data structure. */
+	uint64_t *stats_n2h;			/**< RMNET interface statistics from NSS-to-host. */
+	uint64_t *stats_h2n;			/**< RMNET interface statistics from host-to-NSS. */
+	atomic_t refcnt;			/**< Reference count. */
+	nss_rmnet_rx_msg_callback_t cb;		/**< Message callback. */
+	void *app_data;		/**< Application data to be passed to the callback. */
+};
+
+/**
+ * nss_rmnet_rx_destroy_sync
+ *	Destroys the RMNET interface synchronously.
+ *
+ * @datatypes
+ * nss_rmnet_rx_handle
+ *
+ * @param[in,out] handle  Pointer to the RMNET interface handle (provided during
+ *                        dynamic interface allocation).
+ *
+ * @return
+ * Status of the Tx operation.
+ *
+ * @dependencies
+ * The interface must have been previously created.
+ */
+extern nss_tx_status_t nss_rmnet_rx_destroy_sync(struct nss_rmnet_rx_handle *handle);
+
+/**
+ * nss_rmnet_rx_create_sync_nexthop
+ *	Creates an RMNET interface synchronously with specified nexthops.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] netdev       Pointer to the associated network device.
+ * @param[in] nexthop_n2h  Nexthop interface number of NSS-to-host dynamic interface.
+ * @param[in] nexthop_h2n  Nexthop interface number of host-to-NSS dynamic interface.
+ *
+ * @return
+ * Pointer to the NSS RMNET interface handle.
+ */
+extern struct nss_rmnet_rx_handle *nss_rmnet_rx_create_sync_nexthop(struct net_device *netdev, uint32_t nexthop_n2h, uint32_t nexthop_h2n);
+
+/**
+ * nss_rmnet_rx_create
+ *	Creates an RMNET interface synchronously with generic nexthops.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] netdev       Pointer to the associated network device.
+ *
+ * @return
+ * Pointer to the NSS RMNET interface handle.
+ */
+extern struct nss_rmnet_rx_handle *nss_rmnet_rx_create(struct net_device *netdev);
+
+/**
+ * nss_rmnet_rx_tx_buf
+ *	Forwards RMNET interface packets to the NSS.
+ *
+ * @datatypes
+ * nss_rmnet_rx_handle \n
+ * sk_buff
+ *
+ * @param[in,out] handle  Pointer to the RMNET interface handle (provided during
+ *                        registration).
+ * @param[in]    skb     Pointer to the data socket buffer.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_rmnet_rx_tx_buf(struct nss_rmnet_rx_handle *handle,
+						struct sk_buff *skb);
+
+/**
+ * nss_rmnet_rx_tx_msg
+ *	Sends a message to the RMNET interface.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_rmnet_rx_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context (provided during registration).
+ * @param[in] nvim     Pointer to the RMNET interface message.
+ *
+ * @return
+ * Command Tx status.
+ */
+extern nss_tx_status_t nss_rmnet_rx_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_rmnet_rx_msg *nvim);
+
+/**
+ * nss_rmnet_rx_xmit_callback_unregister
+ *	Deregisters the transmit callback from the RMNET interface.
+ *
+ * @datatypes
+ * nss_rmnet_rx_handle
+ *
+ * @param[in,out] handle  Pointer to the RMNET interface handle.
+ *
+ * @return
+ * None.
+ */
+extern void nss_rmnet_rx_xmit_callback_unregister(struct nss_rmnet_rx_handle *handle);
+
+/**
+ * nss_rmnet_rx_xmit_callback_register
+ *	Registers a transmit callback to an RMNET interface.
+ *
+ * @datatypes
+ * nss_rmnet_rx_handle \n
+ * nss_rmnet_rx_xmit_callback_t
+ *
+ * @param[in,out] handle        Pointer to the RMNET interface handle (provided during
+ *                              dynamic interface allocation).
+ * @param[in]    cb             Callback handler for RMNET data packets.
+ *
+ * @return
+ * None.
+ */
+extern void nss_rmnet_rx_xmit_callback_register(struct nss_rmnet_rx_handle *handle,
+				nss_rmnet_rx_xmit_callback_t cb);
+
+/**
+ * nss_rmnet_rx_unregister
+ *	Deregisters an RMNET interface from the NSS driver.
+ *
+ * @datatypes
+ * nss_rmnet_rx_handle
+ *
+ * @param[in,out] handle  Pointer to the RMNET interface handle.
+ *
+ * @return
+ * None.
+ */
+extern void nss_rmnet_rx_unregister(struct nss_rmnet_rx_handle *handle);
+
+/**
+ * nss_rmnet_rx_register
+ *	Registers an RMNET Interface with NSS driver.
+ *
+ * @datatypes
+ * nss_rmnet_rx_handle \n
+ * nss_rmnet_rx_data_callback_t \n
+ * net_device
+ *
+ * @param[in,out] handle        Pointer to the RMNET interface handle (provided during
+ *                              dynamic interface allocation).
+ * @param[in]    data_callback  Callback handler for RMNET data packets.
+ * @param[in]    netdev         Pointer to the associated network device.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern void nss_rmnet_rx_register(struct nss_rmnet_rx_handle *handle,
+					nss_rmnet_rx_data_callback_t data_callback,
+					struct net_device *netdev);
+
+/**
+ * nss_rmnet_rx_get_ifnum_with_coreid
+ *	Returns the interface number with the core ID.
+ *
+ * @param[in] if_num  NSS interface number
+ *
+ * @return
+ * Interface number with the core ID.
+ */
+extern int32_t nss_rmnet_rx_get_ifnum_with_core_id(int32_t if_num);
+
+/**
+ * nss_rmnet_rx_get_ifnum
+ *	Returns the interface number with appending core ID.
+ *
+ * @param[in] dev Net device
+ *
+ * @return
+ * Interface number with the core ID.
+ */
+extern int32_t nss_rmnet_rx_get_ifnum(struct net_device *dev);
+
+/**
+ * nss_rmnet_rx_get_interface_num
+ *	Returns the RMNET interface number associated with the handle.
+ *
+ * @datatypes
+ * nss_rmnet_rx_handle
+ *
+ * @param[in] handle  Pointer to the RMNET interface handle (provided during
+		      dynamic interface allocation).
+ *
+ * @return
+ * RMNET interface number.
+ */
+extern int32_t nss_rmnet_rx_get_interface_num(struct nss_rmnet_rx_handle *handle);
+
+/**
+ * nss_rmnet_rx_get_context
+ *	Gets the RMNET interface context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_rmnet_rx_get_context(void);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_RMNET_RX_H */
diff --git a/qca-nss-drv/exports/nss_rps.h b/qca-nss-drv/exports/nss_rps.h
new file mode 100644
index 0000000..213604e
--- /dev/null
+++ b/qca-nss-drv/exports/nss_rps.h
@@ -0,0 +1,55 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_rps.h
+ *	RPS related definitions.
+ */
+
+#ifndef __NSS_RPS_H
+#define __NSS_RPS_H
+
+/**
+ * @addtogroup nss_rps_subsystem
+ * @{
+ */
+
+/**
+ * nss_rps_register_sysctl
+ *	Registers the RPS sysctl entries to the sysctl tree.
+ *
+ * @return
+ * None.
+ */
+extern void nss_rps_register_sysctl(void);
+
+/**
+ * nss_rps_unregister_sysctl
+ *	Deregisters the RPS sysctl entries from the sysctl tree.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The system control must have been previously registered.
+ */
+extern void nss_rps_unregister_sysctl(void);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_RPS_H */
diff --git a/qca-nss-drv/exports/nss_shaper.h b/qca-nss-drv/exports/nss_shaper.h
new file mode 100644
index 0000000..fbb0415
--- /dev/null
+++ b/qca-nss-drv/exports/nss_shaper.h
@@ -0,0 +1,901 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, 2017-2018 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_shaper.h
+ *	NSS Shaper definitions
+ */
+
+#ifndef __NSS_SHAPER_H
+#define __NSS_SHAPER_H
+
+/**
+ * @addtogroup nss_shaper_subsystem
+ * @{
+ */
+
+/**
+ * nss_shaper_node_types
+ *	Types of shaper nodes that are exported to the HLOS.
+  */
+enum nss_shaper_node_types {
+	NSS_SHAPER_NODE_TYPE_CODEL = 1,
+	NSS_SHAPER_NODE_TYPE_PRIO = 3,
+	NSS_SHAPER_NODE_TYPE_FIFO = 4,
+	NSS_SHAPER_NODE_TYPE_TBL = 5,
+	NSS_SHAPER_NODE_TYPE_BF = 6,
+	NSS_SHAPER_NODE_TYPE_BF_GROUP = 7,
+	NSS_SHAPER_NODE_TYPE_WRR = 9,
+	NSS_SHAPER_NODE_TYPE_WRR_GROUP = 10,
+	NSS_SHAPER_NODE_TYPE_HTB = 11,
+	NSS_SHAPER_NODE_TYPE_HTB_GROUP = 12,
+	NSS_SHAPER_NODE_TYPE_WRED = 13,
+	NSS_SHAPER_NODE_TYPE_PPE_SN = 14,
+	NSS_SHAPER_NODE_TYPE_MAX,
+};
+
+typedef enum nss_shaper_node_types nss_shaper_node_type_t;
+		/**< Types of shaper nodes that are exported to the HLOS. */
+
+/**
+ * nss_shaper_config_types
+ *	Types of shaper configuration messages.
+ */
+enum nss_shaper_config_types {
+	NSS_SHAPER_CONFIG_TYPE_ALLOC_SHAPER_NODE,
+	NSS_SHAPER_CONFIG_TYPE_FREE_SHAPER_NODE,
+	NSS_SHAPER_CONFIG_TYPE_SET_DEFAULT,
+	NSS_SHAPER_CONFIG_TYPE_SET_ROOT,
+	NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_BASIC_STATS_GET,
+	NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_ATTACH,
+	NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_DETACH,
+	NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_CHANGE_PARAM,
+	NSS_SHAPER_CONFIG_TYPE_HYBRID_MODE_ENABLE,
+	NSS_SHAPER_CONFIG_TYPE_HYBRID_MODE_DISABLE,
+	NSS_SHAPER_CONFIG_TYPE_SHAPER_NODE_MEM_REQ,
+};
+
+typedef enum nss_shaper_config_types nss_shaper_config_type_t;
+		/**< Types of shaper configuration messages. */
+
+/**
+ * nss_shaper_response_types
+ *	Types of shaper configuration responses.
+ */
+enum nss_shaper_response_types {
+	NSS_SHAPER_RESPONSE_TYPE_SUCCESS,
+	NSS_SHAPER_RESPONSE_TYPE_NO_SHAPER_NODE,
+	NSS_SHAPER_RESPONSE_TYPE_NO_SHAPER_NODES,
+	NSS_SHAPER_RESPONSE_TYPE_OLD,
+	NSS_SHAPER_RESPONSE_TYPE_UNRECOGNISED,
+	NSS_SHAPER_RESPONSE_TYPE_BAD_DEFAULT_CHOICE,
+	NSS_SHAPER_RESPONSE_TYPE_DUPLICATE_QOS_TAG,
+	NSS_SHAPER_RESPONSE_TYPE_TBL_CIR_RATE_AND_BURST_REQUIRED,
+	NSS_SHAPER_RESPONSE_TYPE_TBL_CIR_BURST_LESS_THAN_MTU,
+	NSS_SHAPER_RESPONSE_TYPE_CODEL_ALL_PARAMS_REQUIRED,
+	NSS_SHAPER_RESPONSE_TYPE_BF_GROUP_RATE_AND_BURST_REQUIRED,
+	NSS_SHAPER_RESPONSE_TYPE_BF_GROUP_BURST_LESS_THAN_MTU,
+	NSS_SHAPER_RESPONSE_TYPE_CHILD_NOT_BF_GROUP,
+	NSS_SHAPER_RESPONSE_TYPE_WRR_GROUP_INVALID_QUANTUM,
+	NSS_SHAPER_RESPONSE_TYPE_CHILD_NOT_WRR_GROUP,
+	NSS_SHAPER_RESPONSE_TYPE_WRR_INVALID_OPERATION_MODE,
+	NSS_SHAPER_RESPONSE_TYPE_HTB_GROUP_BURST_LESS_THAN_MTU,
+	NSS_SHAPER_RESPONSE_TYPE_HTB_GROUP_PRIORITY_OUT_OF_RANGE,
+	NSS_SHAPER_RESPONSE_TYPE_CHILDREN_BELONG_TO_MIXED_TYPES,
+	NSS_SHAPER_RESPONSE_TYPE_CHILD_ALREADY_PRESENT,
+	NSS_SHAPER_RESPONSE_TYPE_CHILD_MISMATCH,
+	NSS_SHAPER_RESPONSE_TYPE_CHILD_UNSUPPORTED,
+	NSS_SHAPER_RESPONSE_TYPE_CHILD_NOT_FOUND,
+	NSS_SHAPER_RESPONSE_TYPE_ATTACH_FAIL,
+	NSS_SHAPER_RESPONSE_TYPE_WRED_WEIGHT_MODE_INVALID,
+	NSS_SHAPER_RESPONSE_TYPE_PPE_SN_UCAST_BASE_OFFSET_INVALID,
+	NSS_SHAPER_RESPONSE_TYPE_PPE_SN_MCAST_BASE_OFFSET_INVALID,
+	NSS_SHAPER_RESPONSE_TYPE_PPE_SN_UCAST_QUEUE_ALLOC_FAILED,
+	NSS_SHAPER_RESPONSE_TYPE_PPE_SN_MCAST_QUEUE_ALLOC_FAILED,
+	NSS_SHAPER_RESPONSE_TYPE_PPE_SN_INVALID_LIMIT,
+	NSS_SHAPER_RESPONSE_TYPE_PPE_SN_UCAST_QUEUE_CHANGED,
+	NSS_SHAPER_RESPONSE_TYPE_PPE_SN_MCAST_QUEUE_CHANGED,
+	NSS_SHAPER_RESPONSE_TYPE_CODEL_FQ_MEM_INSUFFICIENT,
+	NSS_SHAPER_RESPONSE_TYPE_CODEL_FQ_COUNT_CHANGE_NOT_ALLOWED,
+	NSS_SHAPER_RESPONSE_TYPE_CODEL_FQ_COUNT_INVALID,
+	NSS_SHAPER_RESPONSE_TYPE_CODEL_MODE_CHANGE_NOT_ALLOWED,
+};
+
+typedef enum nss_shaper_response_types nss_shaper_response_type_t;
+		/**< Types of shaper configuration responses. */
+
+/**
+ * nss_shaper_config_alloc_shaper_node
+ *	Message information for allocating a shaper node for a NSS interface.
+ */
+struct nss_shaper_config_alloc_shaper_node {
+	nss_shaper_node_type_t node_type;	/**< Type of shaper node. */
+	uint32_t qos_tag;			/**< QoS tag of the node. */
+};
+
+/**
+ * nss_shaper_config_free_shaper_node
+ *	Message information for freeing a shaper node from a NSS interface.
+ */
+struct nss_shaper_config_free_shaper_node {
+	uint32_t qos_tag;	/**< QoS tag of the node. */
+};
+
+/**
+ * nss_shaper_config_set_root_node
+ *	Message information for setting a shaper node as the root.
+ */
+struct nss_shaper_config_set_root_node {
+	uint32_t qos_tag;	/**< QoS tag of the node. */
+};
+
+/**
+ * nss_shaper_config_set_default_node
+ *	Message information for setting a shaper node as the default node for enqueueing.
+ */
+struct nss_shaper_config_set_default_node {
+	uint32_t qos_tag;	/**< QoS tag of the node. */
+};
+
+/**
+ * nss_shaper_config_set_hybrid_mode
+ *	Message information for setting a shaper to operate in hybrid mode.
+ */
+struct nss_shaper_config_set_hybrid_mode {
+	uint32_t offset;	/**< Queue offset for packets sent to the hardware. */
+};
+
+/**
+ * nss_shaper_config_prio_attach
+ *	Message information for attaching a shaper node to a PRIO shaper node.
+ */
+struct nss_shaper_config_prio_attach {
+	uint32_t child_qos_tag;	/**< QoS tag of the child shaper node. */
+	uint32_t priority;	/**< Priority of the child shaper node. */
+};
+
+/**
+ * nss_shaper_config_prio_detach
+ *	Message information for detaching a shaper node from a PRIO shaper node.
+ */
+struct nss_shaper_config_prio_detach {
+	uint32_t priority;	/**< Priority of the child shaper node. */
+};
+
+/**
+ * nss_shaper_config_codel_alg_param
+ *	Message information for configuring a CoDel algorithm.
+ */
+struct nss_shaper_config_codel_alg_param {
+	uint16_t interval;	/**< Buffer time to smooth a state transition. */
+	uint16_t target;	/**< Acceptable delay associated with a queue. */
+	uint16_t mtu;		/**< MTU for the associated interface. */
+	uint16_t reserved;	/**< Alignment padding. */
+};
+
+/**
+ * nss_shaper_config_codel_param
+ *	Message information for configuring a CoDel shaper node.
+ */
+struct nss_shaper_config_codel_param {
+	int32_t qlen_max;	/**< Maximum number of packets that can be enqueued. */
+	struct nss_shaper_config_codel_alg_param cap;
+				/**< Configuration for the CoDel algorithm. */
+	uint32_t flows;		/**< Number of flow hash buckets. */
+	uint32_t flows_mem;	/**< Host allocated memory for flow queues. */
+	uint32_t flows_mem_sz;	/**< Memory size allocated for flow queues. */
+	uint32_t quantum;	/**< Quantum (in bytes) to round-robin the flow buckets. */
+	uint32_t ecn;		/**< 0 - ECN disabled, 1 - ECN enabled. */
+};
+
+/**
+ * nss_shaper_config_codel_mem_req
+ *	Message to get CoDel memory requirement per flow queue (needed for fq_codel).
+ */
+struct nss_shaper_config_codel_mem_req {
+	uint32_t mem_req;	/**< Memory needed per flow queue (in bytes). */
+};
+
+/**
+ * nss_shaper_config_rate_param
+ *	Message information for configuring the rate limiter algorithm.
+ */
+struct nss_shaper_config_rate_param {
+	uint32_t rate;
+			/**< Allowed traffic rate measured in bytes per second. */
+	uint32_t burst;
+			/**< Maximum bytes that can be sent in a burst. */
+	uint32_t max_size;
+			/**< Maximum size of the supported packets (in bytes). */
+
+	/**
+	 * Specifies whether the rate limiter will be bypassed (short circuited).
+	 */
+	bool short_circuit;
+};
+
+/**
+ * nss_shaper_configure_tbl_attach
+ *	Message information for attaching a shaper node to a TBL shaper node.
+ */
+struct nss_shaper_config_tbl_attach {
+	uint32_t child_qos_tag;	/**< QoS tag of the child shaper node. */
+};
+
+/**
+ * nss_shaper_configure_tbl_param
+ *	Message information for detaching a shaper node from a TBL shaper node.
+ */
+struct nss_shaper_config_tbl_param {
+	struct nss_shaper_config_rate_param lap_cir;
+		/**< Configuration parameters for the committed information rate. */
+	struct nss_shaper_config_rate_param lap_pir;
+		/**< Configuration parameters for the peak information rate. */
+};
+
+/**
+ * nss_shaper_config_bf_attach
+ *	Message information for attaching a shaper node to a BF shaper node.
+ */
+struct nss_shaper_config_bf_attach {
+	uint32_t child_qos_tag;	/**< QoS tag of the child shaper node. */
+};
+
+/**
+ * nss_shaper_config_bf_detach
+ *	Message information for detaching a shaper node from a BF shaper node.
+ */
+struct nss_shaper_config_bf_detach {
+	uint32_t child_qos_tag;	/**< QoS tag of the child shaper node. */
+};
+
+/**
+ * nss_shaper_config_bf_group_attach
+ *	Message information for attaching a shaper node to a BF group shaper node.
+ */
+struct nss_shaper_config_bf_group_attach {
+	uint32_t child_qos_tag;	/**< QoS tag of the child shaper node. */
+};
+
+/**
+ * nss_shaper_config_bf_group_param
+ *	Configuration parameters for a BF group shaper node.
+ */
+struct nss_shaper_config_bf_group_param {
+	uint32_t quantum;
+		/**< Smallest increment value for the DRRs. */
+	struct nss_shaper_config_rate_param lap;
+		/**< Configuration of the rate control algorithm. */
+};
+
+/**
+ * nss_shaper_config_fifo_limit_set
+ *	Drop modes for the FIFO shaper in the NSS interface.
+ */
+enum nss_shaper_config_fifo_drop_modes {
+	NSS_SHAPER_FIFO_DROP_MODE_HEAD = 0,
+	NSS_SHAPER_FIFO_DROP_MODE_TAIL,
+	NSS_SHAPER_FIFO_DROP_MODES,
+};
+
+typedef enum nss_shaper_config_fifo_drop_modes nss_shaper_config_fifo_drop_mode_t;
+		/**< Drop modes for the FIFO shaper in the NSS interface. */
+
+/**
+ * nss_shaper_config_fifo_param
+ *	Message information for configuring a FIFO shaper node.
+ */
+struct nss_shaper_config_fifo_param {
+	uint32_t limit;		/**< Queue limit in packets. */
+	nss_shaper_config_fifo_drop_mode_t drop_mode;
+				/**< FIFO drop mode when a queue is full. */
+};
+
+/**
+ * nss_shaper_config_wred_weight_modes
+ *	Supported weight modes.
+ */
+enum nss_shaper_config_wred_weight_modes {
+	NSS_SHAPER_WRED_WEIGHT_MODE_DSCP = 0,
+	NSS_SHAPER_WRED_WEIGHT_MODES,
+};
+
+typedef enum nss_shaper_config_wred_weight_modes nss_shaper_config_wred_weight_mode_t;
+		/**< Supported weight modes. */
+
+/**
+ * nss_shaper_red_alg_param
+ *	Message information for configuring the RED algorithm.
+ */
+struct nss_shaper_red_alg_param {
+	uint32_t min;			/**< Minimum size of the queue. */
+	uint32_t max;			/**< Maximum size of the queue. */
+
+	/**
+	 * Probability of dropped packets when the average queue size (qlen_avg) = max.
+	 */
+	uint32_t probability;
+
+	/**
+	 * Exponential weight factor to calculate the average queue size.
+	 */
+	uint32_t exp_weight_factor;
+};
+
+/**
+ * nss_shaper_config_wred_param
+ *	Message information for configuring the WRED algorithm.
+ */
+struct nss_shaper_config_wred_param {
+	uint32_t limit;			/**< Queue limit in bytes. */
+	nss_shaper_config_wred_weight_mode_t weight_mode;
+					/**< WRED weight mode. */
+	uint32_t traffic_classes;	/**< Number of traffic classes (drop probability). */
+	uint32_t def_traffic_class;	/**< Default traffic class used when there is no match. */
+	uint32_t traffic_id;		/**< Traffic class to configure. */
+	uint32_t weight_mode_value;	/**< Value to match the selected header field against. */
+	struct nss_shaper_red_alg_param rap;
+					/**< Configuration parameters for the RED algorithm. */
+	uint8_t ecn;			/**< Mark an ECN bit or drop packet. */
+};
+
+/**
+ * nss_shaper_config_wrr_attach
+ *	Message information for attaching a shaper node to a WRR shaper node.
+ */
+struct nss_shaper_config_wrr_attach {
+	uint32_t child_qos_tag;	/**< QoS tag of the child shaper node. */
+};
+
+/**
+ * nss_shaper_config_wrr_detach
+ *	Message information for detaching a child node from a WRR shaper node.
+ */
+struct nss_shaper_config_wrr_detach {
+	uint32_t child_qos_tag;	/**< QoS tag of the child shaper node. */
+};
+
+/**
+ * nss_shaper_config_wrr_group_attach
+ *	Message information for attaching a shaper node to a WRR group.
+ */
+struct nss_shaper_config_wrr_group_attach {
+	uint32_t child_qos_tag;	/**< QoS tag of the child shaper node. */
+};
+
+/**
+ * nss_shaper_wrr_operation_modes
+ *	Modes of WRR operation.
+ */
+enum nss_shaper_wrr_operation_modes {
+	NSS_SHAPER_WRR_MODE_ROUND_ROBIN = 0,
+	NSS_SHAPER_WRR_MODE_FAIR_QUEUEING = 1,
+	NSS_SHAPER_WRR_MODE_TYPE_MAX,
+};
+
+/**
+ * nss_shaper_config_wrr_param
+ *	Message information for configuring the operation mode of a WRR shaper node.
+ */
+struct nss_shaper_config_wrr_param {
+	uint32_t operation_mode;	/**< Mode in which to operate. */
+};
+
+/**
+ * nss_shaper_config_wrr_group_param
+ *	Message information for configuring a quantum value of a WRR group shaper node.
+ */
+struct nss_shaper_config_wrr_group_param {
+	uint32_t quantum;	/**< Smallest increment value for the DRRs. */
+};
+
+/**
+ * nss_shaper_config_htb_attach
+ *	Message information for attaching a shaper node to an HTB shaper node.
+ */
+struct nss_shaper_config_htb_attach {
+	uint32_t child_qos_tag;	/**< QoS tag of the child shaper node. */
+};
+
+/**
+ * nss_shaper_config_htb_group_attach
+ *	Message information for attaching a shaper node to an HTB group.
+ */
+struct nss_shaper_config_htb_group_attach {
+	uint32_t child_qos_tag;	/**< QoS tag of the child shaper node. */
+};
+
+/**
+ * nss_shaper_config_htb_group_detach
+ *	Message information for detaching a shaper node from an HTB group.
+ */
+struct nss_shaper_config_htb_group_detach {
+	uint32_t child_qos_tag;	/**< QoS tag of the child shaper node. */
+};
+
+/**
+ * nss_shaper_config_htb_group_param
+ *	Message information for configuring an HTB group shaper node.
+ */
+struct nss_shaper_config_htb_group_param {
+	uint32_t quantum;	/**< Smallest increment value for the DRRs. */
+	uint32_t priority;	/**< Value of the priority for this group. */
+	uint32_t overhead;	/**< Overhead in bytes to be added per packet. */
+	struct nss_shaper_config_rate_param rate_police;
+		/**< Configuration parameters for the policing rate. */
+	struct nss_shaper_config_rate_param rate_ceil;
+		/**< Configuration parameters for the ceiling rate. */
+};
+
+/**
+ * nss_shaper_config_ppe_sn_attach
+ *	Message information for attaching a shaper node to a PPE shaper node.
+ */
+struct nss_shaper_config_ppe_sn_attach {
+	uint32_t child_qos_tag;	/**< QoS tag of the child shaper node. */
+};
+
+/**
+ * nss_shaper_config_ppe_sn_detach
+ *	Message information for detaching a shaper node from a PPE shaper node.
+ */
+struct nss_shaper_config_ppe_sn_detach {
+	uint32_t child_qos_tag;	/**< QoS tag of the child shaper node. */
+};
+
+/**
+ * nss_shaper_config_ppe_sn_type
+ *	Types of PPE shaper nodes.
+ */
+enum nss_shaper_config_ppe_sn_type {
+	/*
+	 * Scheduler types.
+	 */
+	NSS_SHAPER_CONFIG_PPE_SN_TYPE_HTB,
+	NSS_SHAPER_CONFIG_PPE_SN_TYPE_HTB_GROUP,
+	NSS_SHAPER_CONFIG_PPE_SN_TYPE_TBL,
+	NSS_SHAPER_CONFIG_PPE_SN_TYPE_WRR,
+	NSS_SHAPER_CONFIG_PPE_SN_TYPE_WRR_GROUP,
+	NSS_SHAPER_CONFIG_PPE_SN_TYPE_PRIO,
+	NSS_SHAPER_CONFIG_PPE_SN_SCH_MAX = 0xFF,
+
+	/*
+	 * Queue types.
+	 */
+	NSS_SHAPER_CONFIG_PPE_SN_TYPE_FIFO,
+	NSS_SHAPER_CONFIG_PPE_SN_TYPE_RED,
+	NSS_SHAPER_CONFIG_PPE_SN_TYPE_MAX,
+};
+
+/**
+ * nss_shaper_config_ppe_sn_param
+ *	Message information for configuring a PPE shaper node.
+ */
+struct nss_shaper_config_ppe_sn_param {
+	enum nss_shaper_config_ppe_sn_type type;
+				/**< Type of PPE shaper node. */
+	uint16_t ucast_base;	/**< Resource ID of the base hardware for unicast queue. */
+	uint16_t ucast_offset;	/**< Offset from the base resource ID for unicast queue. */
+	uint16_t mcast_base;	/**< Resource ID of the base hardware for multicast queue. */
+	uint16_t mcast_offset;	/**< Offset from the base resource ID for multicast queue. */
+	uint8_t port;		/**< PPE port on which this shaper node is configured. */
+	uint8_t reserved;	/**< Reserved for padding. */
+	uint16_t limit;		/**< Limit of the queue. */
+};
+
+/*
+ * nss_shaper_node_config
+ *	Configuration messages for all types of shaper nodes.
+ */
+struct nss_shaper_node_config {
+	uint32_t qos_tag;	/**< ID of the shaper node to be configured. */
+
+	/**
+	 * Configuration messages for all types of shaper nodes.
+	 */
+	union {
+		struct nss_shaper_config_prio_attach prio_attach;
+			/**< Attach a shaper node to a PRIO shaper node. */
+		struct nss_shaper_config_prio_detach prio_detach;
+			/**< Detach a shaper node from a PRIO shaper node. */
+
+		struct nss_shaper_config_codel_param codel_param;
+			/**< Configure a CoDel shaper node. */
+
+		struct nss_shaper_config_codel_mem_req codel_mem_req;
+			/**< Get CoDel memory requirement. */
+
+		struct nss_shaper_config_tbl_attach tbl_attach;
+			/**< Attach a shaper node to a TBL shaper node. */
+		struct nss_shaper_config_tbl_param tbl_param;
+			/**< Configuration parameters for a TBL shaper node. */
+
+		struct nss_shaper_config_bf_attach bf_attach;
+			/**< Attach a shaper node to a BF shaper node. */
+		struct nss_shaper_config_bf_detach bf_detach;
+			/**< Detach a child shaper node from BF shaper node. */
+		struct nss_shaper_config_bf_group_attach bf_group_attach;
+			/**< Attach a shaper node to a BF group shaper node. */
+		struct nss_shaper_config_bf_group_param bf_group_param;
+			/**< Configure parameters for a BF group shaper node. */
+
+		struct nss_shaper_config_fifo_param fifo_param;
+			/**< Configure a FIFO shaper node. */
+
+		struct nss_shaper_config_wrr_attach wrr_attach;
+			/**< Attach a shaper node to a WRR shaper node. */
+		struct nss_shaper_config_wrr_detach wrr_detach;
+			/**< Detach a shaper node from a WRR shaper node. */
+		struct nss_shaper_config_wrr_param wrr_param;
+			/**< Configuration parameters for a WRR shaper node . */
+		struct nss_shaper_config_wrr_group_attach wrr_group_attach;
+			/**< Attach a shaper node to a WRR group shaper node. */
+		struct nss_shaper_config_wrr_group_param wrr_group_param;
+			/**< Configure a WRR group shaper node with a quantum value. */
+		struct nss_shaper_config_htb_attach htb_attach;
+			/**< Attach a shaper node to an HTB shaper node. */
+		struct nss_shaper_config_htb_group_attach htb_group_attach;
+			/**< Attach a shaper node to an HTB group shaper node. */
+		struct nss_shaper_config_htb_group_detach htb_group_detach;
+			/**< Detach a shaper node from an HTB group shaper node. */
+		struct nss_shaper_config_htb_group_param htb_group_param;
+			/**< Configuration parameters for an HTB group shaper node. */
+		struct nss_shaper_config_wred_param wred_param;
+			/**< Configuration parameters for a WRED shaper node. */
+		struct nss_shaper_config_ppe_sn_attach ppe_sn_attach;
+			/**< Attach a shaper node to a PPE shaper node. */
+		struct nss_shaper_config_ppe_sn_detach ppe_sn_detach;
+			/**< Detach a shaper node from a PPE shaper node. */
+		struct nss_shaper_config_ppe_sn_param ppe_sn_param;
+			/**< Configuration parameters for a PPE shaper node. */
+	} snc;	/**< Types of shaper node configuration messages. */
+};
+
+/**
+ * nss_shaper_node_codel_fq_stats_delta
+ *	CoDel flow queue mode statistics sent as deltas.
+ */
+struct nss_shaper_node_codel_fq_stats_delta {
+	uint32_t new_flow_cnt;		/**< Total number of new flows seen. */
+	uint32_t ecn_mark_cnt;		/**< Number of packets marked with ECN. */
+};
+
+/**
+ * nss_shaper_node_codel_fq_stats
+ *      CoDel flow queue mode statistics.
+ */
+struct nss_shaper_node_codel_fq_stats {
+	struct nss_shaper_node_codel_fq_stats_delta delta;
+					/**< CoDel flow queue statistics sent as deltas. */
+	uint32_t new_flows_len;		/**< Current number of new flows. */
+	uint32_t old_flows_len;		/**< Current number of old flows. */
+	uint32_t maxpacket;		/**< Largest packet seen so far. */
+};
+
+/**
+ * nss_shaper_node_codel_sq_stats
+ *      CoDel single queue mode statistics.
+ */
+struct nss_shaper_node_codel_sq_stats {
+	/**
+	 * Maximum amount of time (in milliseconds) that a packet was in this shaper
+	 * node before being dequeued.
+	 */
+        uint32_t packet_latency_peak_msec_dequeued;
+
+	/**
+	 * Maximum amount of time (in milliseconds) that a packet was in this shaper
+	 * node before being dropped.
+	 */
+        uint32_t packet_latency_peak_msec_dropped;
+};
+
+/**
+ * nss_shaper_node_codel_stats
+ *      CoDel shaper node statistics.
+ */
+struct nss_shaper_node_codel_stats {
+        struct nss_shaper_node_codel_sq_stats sq;   /**< Single queue mode statistics. */
+        struct nss_shaper_node_codel_fq_stats fq;   /**< Flow queue mode statistics. */
+};
+
+/**
+ * nss_shaper_node_stats_delta
+ *	Statistics that are sent as deltas.
+ */
+struct nss_shaper_node_stats_delta {
+	uint32_t enqueued_bytes;	/**< Bytes enqueued successfully. */
+	uint32_t enqueued_packets;	/**< Packets enqueued successfully. */
+
+	/**
+	 * Bytes dropped during an enqueue operation because of node limits.
+	 */
+	uint32_t enqueued_bytes_dropped;
+
+	/**
+	 * Packets dropped during an enqueue operation because of node limits.
+	 */
+	uint32_t enqueued_packets_dropped;
+
+	uint32_t dequeued_bytes;
+			/**< Bytes dequeued successfully from a shaper node. */
+	uint32_t dequeued_packets;
+			/**< Packets dequeued successfully from a shaper node. */
+
+	/**
+	 * Bytes dropped by this node during dequeuing (some nodes drop packets during
+	 * dequeuing rather than enqueuing).
+	 */
+	uint32_t dequeued_bytes_dropped;
+
+	/**
+	 * Packets dropped by this node during dequeuing (some nodes drop packets during
+	 * dequeuing rather than enqueuing).
+	 */
+	uint32_t dequeued_packets_dropped;
+
+	/**
+	 * Number of times any queue limit was overrun, leading to packet drops.
+	 */
+	uint32_t queue_overrun;
+
+	uint32_t unused[4];		/**< Reserved for future statistics expansion. */
+};
+
+/**
+ * nss_shaper_node_stats
+ *	Common shaper node statistics.
+ */
+struct nss_shaper_node_stats {
+	uint32_t qlen_bytes;	/**< Total size of packets waiting in the queue. */
+	uint32_t qlen_packets;	/**< Number of packets waiting in the queue. */
+	uint32_t unused[4];	/**< Reserved for future statistics expansion. */
+	struct nss_shaper_node_stats_delta delta;
+				/**< Statistics that are sent as deltas. */
+};
+
+/**
+ * nss_shaper_node_stats_response
+ *	Statistics response for shaper nodes.
+ */
+struct nss_shaper_node_stats_response {
+	struct nss_shaper_node_stats sn_stats;	/**< Common shaper node statistics. */
+
+	/**
+	 * All shaper nodes that need to maintain unique statistics need
+	 * to add their statistics structure here.
+	 */
+	union {
+		struct nss_shaper_node_codel_stats codel;
+						/**< CoDel specific statistics. */
+	} per_sn_stats;				/**< Shaper specific statistics. */
+};
+
+/**
+ * nss_shaper_node_stats_get
+ *	Statistics of a shaper node.
+ */
+struct nss_shaper_node_stats_get {
+
+	/*
+	 * Request
+	 */
+	uint32_t qos_tag;	/**< QoS tag of the shaper node. */
+
+	/*
+	 * Response
+	 */
+	struct nss_shaper_node_stats_response response;
+				/**< Shaper node statistics response */
+};
+
+/**
+ * nss_shaper_configure
+ *	Configuration message for a shaper node.
+ */
+struct nss_shaper_configure {
+	nss_shaper_config_type_t request_type;		/**< Message is a request. */
+	nss_shaper_response_type_t response_type;	/**< Message is a response. */
+
+	/**
+	 * Types of configuration messages for a shaper node.
+	 */
+	union {
+		struct nss_shaper_config_alloc_shaper_node alloc_shaper_node;
+				/**< Allocate a shaper node in the NSS interface. */
+		struct nss_shaper_config_free_shaper_node free_shaper_node;
+				/**< Free a shaper node from the NSS interface. */
+		struct nss_shaper_config_set_default_node set_default_node;
+				/**< Set a shaper node as the default node for a queue. */
+		struct nss_shaper_config_set_root_node set_root_node;
+				/**< Set a shaper node as the root shaper nod. */
+		struct nss_shaper_config_set_hybrid_mode set_hybrid_mode;
+				/**< Set a shaper to operate in Hybrid mode. */
+		struct nss_shaper_node_config shaper_node_config;
+				/**< Configuration message for any type of shaper node. */
+		struct nss_shaper_node_stats_get shaper_node_stats_get;
+				/**< Statistics for a shaper node. */
+	} msg;			/**< Types of configuration messages. */
+};
+
+/**
+ * Registrant callback to receive shaper bounced packets
+ *
+ * @datatypes
+ * sk_buff
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] skb       Pointer to the data socket buffer.
+ */
+typedef void (*nss_shaper_bounced_callback_t)(void *app_data, struct sk_buff *skb);
+
+/**
+ * nss_shaper_register_shaping
+ *	Registers a shaper node with the NSS interface for basic shaping operations.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern void *nss_shaper_register_shaping(void);
+
+/**
+ * nss_shaper_unregister_shaping
+ *	Deregisters a shaper node from the NSS interface.
+ *
+ * @param[in] ctx  Pointer to the NSS context.
+ *
+ * @dependencies
+ * The shaper node must have been previously registered.
+ */
+extern void nss_shaper_unregister_shaping(void *ctx);
+
+/**
+ * nss_shaper_register_shaper_bounce_interface
+ *	Registers a shaper bounce interface with the NSS interface for receiving
+ *	shaper-bounced packets.
+ *
+ * @datatypes
+ * nss_shaper_bounced_callback_t \n
+ * module
+ *
+ * @param[in] if_num    NSS interface number.
+ * @param[in] cb        Callback function for the message. This callback is
+ *                      invoked when the NSS returns a sk_buff after shaping.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *                      This context is passed to the callback together with the
+ *                      sk_buff to provide context to the registrant (state).
+ * @param[in] owner     Pointer to the kernel module. The module is held until it deregisters.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern void *nss_shaper_register_shaper_bounce_interface(uint32_t if_num, nss_shaper_bounced_callback_t cb, void *app_data, struct module *owner);
+
+/**
+ * nss_shaper_unregister_shaper_bounce_interface
+ *	Deregisters a shaper bounce interface from the NSS interface.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The shaper bounce interface must have been previously registered.
+ */
+extern void nss_shaper_unregister_shaper_bounce_interface(uint32_t if_num);
+
+/**
+ * nss_shaper_register_shaper_bounce_bridge
+ *	Registers a shaper bounce bridge with the NSS interface for receiving
+ *	shaper-bounced packets.
+ *
+ * @datatypes
+ * nss_shaper_bounced_callback_t \n
+ * module
+ *
+ * @param[in] if_num    NSS interface number.
+ * @param[in] cb        Callback function for the message. This callback is
+ *                      invoked when the NSS returns a sk_buff after shaping.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *                      This context is passed to the callback together with the
+ *                      sk_buff to provide context to the registrant (state).
+ * @param[in] owner     Pointer to the kernel module.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern void *nss_shaper_register_shaper_bounce_bridge(uint32_t if_num, nss_shaper_bounced_callback_t cb, void *app_data, struct module *owner);
+
+/**
+ * nss_shaper_unregister_shaper_bounce_bridge
+ *	Deregisters a shaper bounce bridge from the NSS interface.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The shaper bounce bridge must have been previously registered.
+ */
+extern void nss_shaper_unregister_shaper_bounce_bridge(uint32_t if_num);
+
+/**
+ * nss_shaper_bounce_interface_packet
+ *	Issues a packet for shaping via a bounce operation.
+ *
+ * @datatypes
+ * sk_buff
+ *
+ * @param[in]     ctx     Pointer to the NSS context provided during registration.
+ * @param[in]     if_num  NSS interface number.
+ * @param[in]     skb     Pointer to the data socket buffer.
+ *
+ * @return
+ * Success or failure.
+ */
+extern nss_tx_status_t nss_shaper_bounce_interface_packet(void *ctx, uint32_t if_num, struct sk_buff *skb);
+
+/**
+ * nss_shaper_bounce_bridge_packet
+ *	Issues a packet for shaping via a bounce bridge.
+ *
+ * @datatypes
+ * sk_buff
+ *
+ * @param[in]     ctx     Pointer to the NSS context provided during registration.
+ * @param[in]     if_num  NSS interface number.
+ * @param[in]     skb     Pointer to the data socket buffer.
+ *
+ * @return
+ * Success or failure.
+ */
+extern nss_tx_status_t nss_shaper_bounce_bridge_packet(void *ctx, uint32_t if_num, struct sk_buff *skb);
+
+/**
+ * nss_shaper_config_send
+ *	Sends a shaping configuration message.
+ *
+ * @datatypes
+ * nss_shaper_configure
+ *
+ * @param[in]     ctx     Pointer to the NSS context.
+ * @param[in]     config  Pointer to the configuration message.
+ *
+ * @return
+ * Indication if the configuration message was issued.
+ * @par
+ * This indication does not mean the configuration message was successfully
+ * processed. Success or failure is provided in the response issued to the
+ * given callback function as specified in nss_shaper_configure.
+ */
+nss_tx_status_t nss_shaper_config_send(void *ctx, struct nss_shaper_configure *config);
+
+/**
+ * nss_shaper_get_device
+ *	Gets the original device from probe.
+ *
+ * @return
+ * Pointer to the device.
+ */
+extern struct device *nss_shaper_get_dev(void);
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/qca-nss-drv/exports/nss_sjack.h b/qca-nss-drv/exports/nss_sjack.h
new file mode 100644
index 0000000..32ef356
--- /dev/null
+++ b/qca-nss-drv/exports/nss_sjack.h
@@ -0,0 +1,154 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_sjack.h
+ *	NSS SJACK interface definitions.
+ */
+
+#ifndef __NSS_SJACK_H
+#define __NSS_SJACK_H
+
+/**
+ * @addtogroup nss_sjack_subsystem
+ * @{
+ */
+
+/**
+ * nss_sjack_msg_types
+ *	Message types for SJACK requests and responses.
+ */
+enum nss_sjack_msg_types {
+	NSS_SJACK_CONFIGURE_MSG,
+	NSS_SJACK_UNCONFIGURE_MSG,
+	NSS_SJACK_STATS_SYNC_MSG,
+	NSS_SJACK_MAX_MSG_TYPE
+};
+
+/**
+ * nss_sjack_configure_msg
+ *	Message information for configuring the SJACK interface.
+ */
+struct nss_sjack_configure_msg {
+	uint32_t ingress_if_num;
+			/**< Ingress interface number corresponding to the SJACK device. */
+	uint32_t egress_if_num;
+			/**< Egress interface number corresponding to the SJACK device. */
+	uint16_t tunnel_id;		/**< SJACK tunnel ID. */
+	uint8_t ip_dscp;		/**< Differentiated services code point value. */
+	uint8_t gre_prio;		/**< GRE priority information. */
+	uint8_t gre_flags;		/**< GRE flags. */
+	uint8_t use_ipsec_sa_pattern;	/**< IPsec security association pattern flag. */
+};
+
+/**
+ * nss_sjack_unconfigure_msg
+ *	Message information for de-configuring the SJACK interface.
+ */
+struct nss_sjack_unconfigure_msg {
+	uint32_t ingress_if_num;
+			/**< Ingress interface number corresponding to the SJACK device. */
+};
+
+/**
+ * nss_sjack_stats_sync_msg
+ *	Message information for SJACK synchronization statistics.
+ */
+struct nss_sjack_stats_sync_msg {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics. */
+};
+
+/**
+ * nss_sjack_msg
+ *	Data for sending and receiving SJACK messages.
+ */
+struct nss_sjack_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of an SJACK message.
+	 */
+	union {
+		struct nss_sjack_configure_msg configure;
+				/**< Configure SJACK. */
+		struct nss_sjack_unconfigure_msg unconfigure;
+				/**< De-configure SJACK. */
+		struct nss_sjack_stats_sync_msg stats_sync;
+				/**< Synchronized statistics for SJACK. */
+	} msg;			/**< Message payload for SJACK interface messages exchanged with NSS core. */
+};
+
+/**
+ * Callback function for receiving SJACK messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_sjack_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * nss_sjack_register_if
+ *	Registers with the NSS for sending and receiving SJACK messages.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_sjack_msg_callback_t
+ *
+ * @param[in] dev             Pointer to the associated network device.
+ * @param[in] if_num          NSS interface number.
+ * @param[in] event_callback  Callback for the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_sjack_register_if(uint32_t if_num, struct net_device *dev, nss_sjack_msg_callback_t event_callback);
+
+/**
+ * nss_sjack_unregister_if
+ *	Deregisters the SJACK interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The interface must have been previously registered.
+ */
+extern void nss_sjack_unregister_if(uint32_t if_num);
+
+/**
+ * nss_sjack_tx_msg
+ *	Send SJACK messages to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_sjack_msg
+ *
+ * @param[in,out] nss_ctx  Pointer to the NSS context.
+ * @param[in]     msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_sjack_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_sjack_msg *msg);
+
+/** @} */ /* end_addtogroup nss_sjack_subsystem */
+
+#endif /* __NSS_SJACK_H */
diff --git a/qca-nss-drv/exports/nss_stats_public.h b/qca-nss-drv/exports/nss_stats_public.h
new file mode 100644
index 0000000..f282ffd
--- /dev/null
+++ b/qca-nss-drv/exports/nss_stats_public.h
@@ -0,0 +1,131 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_stats_public.h
+ *	NSS statistics Structure and APIs
+ */
+
+#ifndef __NSS_STATS_PUBLIC_H
+#define __NSS_STATS_PUBLIC_H
+
+/**
+ * @addtogroup nss_stats_public_subsystem
+ * @{
+ */
+
+/**
+ * Maximum string length.
+ *
+ * This should be equal to maximum string size of any statistics
+ * inclusive of statistics value.
+ */
+#define NSS_STATS_MAX_STR_LENGTH 96
+
+/**
+ * nss_stats_node
+ *	Node statistics.
+ */
+enum nss_stats_node {
+	NSS_STATS_NODE_RX_PKTS,			/**< Accelerated node Rx packets. */
+	NSS_STATS_NODE_RX_BYTES,		/**< Accelerated node Rx bytes. */
+	NSS_STATS_NODE_TX_PKTS,			/**< Accelerated node Tx packets. */
+	NSS_STATS_NODE_TX_BYTES,		/**< Accelerated node Tx bytes. */
+	NSS_STATS_NODE_RX_QUEUE_0_DROPPED,	/**< Accelerated node Rx Queue 0 dropped. */
+	NSS_STATS_NODE_RX_QUEUE_1_DROPPED,	/**< Accelerated node Rx Queue 1 dropped. */
+	NSS_STATS_NODE_RX_QUEUE_2_DROPPED,	/**< Accelerated node Rx Queue 2 dropped. */
+	NSS_STATS_NODE_RX_QUEUE_3_DROPPED,	/**< Accelerated node Rx Queue 3 dropped. */
+	NSS_STATS_NODE_MAX,			/**< Maximum message type. */
+};
+
+/*
+ * WARNING: There is a 1:1 mapping between values of enum nss_stats_drv and corresponding
+ * statistics string array in nss_drv_strings.c.
+ */
+/**
+ * nss_stats_drv
+ *	HLOS driver statistics.
+ */
+enum nss_stats_drv {
+	NSS_STATS_DRV_NBUF_ALLOC_FAILS = 0,	/**< Networking buffer allocation errors. */
+	NSS_STATS_DRV_PAGED_BUF_ALLOC_FAILS,	/**< Paged buffer allocation errors. */
+	NSS_STATS_DRV_TX_QUEUE_FULL_0,		/**< Tx queue full for Core 0. */
+	NSS_STATS_DRV_TX_QUEUE_FULL_1,		/**< Tx queue full for Core 1. */
+	NSS_STATS_DRV_TX_EMPTY,			/**< Host-to-network empty buffers. */
+	NSS_STATS_DRV_PAGED_TX_EMPTY,		/**< Host-to-network paged empty buffers. */
+	NSS_STATS_DRV_TX_PACKET,		/**< Host-to-network data packets. */
+	NSS_STATS_DRV_TX_CMD_REQ,		/**< Host-to-network control packets. */
+	NSS_STATS_DRV_TX_CRYPTO_REQ,		/**< Host-to-network crypto requests. */
+	NSS_STATS_DRV_TX_BUFFER_REUSE,		/**< Host-to-network reuse buffer count. */
+	NSS_STATS_DRV_RX_EMPTY,			/**< Network-to-host empty buffers. */
+	NSS_STATS_DRV_RX_PACKET,		/**< Network-to-host data packets. */
+	NSS_STATS_DRV_RX_CMD_RESP,		/**< Network-to-host command responses. */
+	NSS_STATS_DRV_RX_STATUS,		/**< Network-to-host status packets. */
+	NSS_STATS_DRV_RX_CRYPTO_RESP,		/**< Network-to-host crypto responses. */
+	NSS_STATS_DRV_RX_VIRTUAL,		/**< Network-to-host virtual packets. */
+	NSS_STATS_DRV_TX_SIMPLE,		/**< Host-to-network simple SKB packets. */
+	NSS_STATS_DRV_TX_NR_FRAGS,		/**< Host-to-network number of fragmented SKB packets. */
+	NSS_STATS_DRV_TX_FRAGLIST,		/**< Host-to-network fragmentation list of SKB packets. */
+	NSS_STATS_DRV_RX_SIMPLE,		/**< Network-to-host simple SKB packets. */
+	NSS_STATS_DRV_RX_NR_FRAGS,		/**< Network-to-host number of fragmented SKB packets. */
+	NSS_STATS_DRV_RX_SKB_FRAGLIST,		/**< Network-to-host fragmentation list of SKB packets. */
+	NSS_STATS_DRV_RX_BAD_DESCRIPTOR,	/**< Network-to-host bad descriptor reads. */
+	NSS_STATS_DRV_NSS_SKB_COUNT,		/**< NSS SKB pool count. */
+	NSS_STATS_DRV_CHAIN_SEG_PROCESSED,	/**< Network-to-host SKB chain processed count. */
+	NSS_STATS_DRV_FRAG_SEG_PROCESSED,	/**< Network-to-host fragments processed count. */
+	NSS_STATS_DRV_TX_CMD_QUEUE_FULL,	/**< Tx host-to-network control packets fail due to queue full. */
+#ifdef NSS_MULTI_H2N_DATA_RING_SUPPORT
+	NSS_STATS_DRV_TX_PACKET_QUEUE_0,	/**< Host-to-network data packets on queue0. */
+	NSS_STATS_DRV_TX_PACKET_QUEUE_1,	/**< Host-to-network data packets on queue1. */
+	NSS_STATS_DRV_TX_PACKET_QUEUE_2,	/**< Host-to-network data packets on queue2. */
+	NSS_STATS_DRV_TX_PACKET_QUEUE_3,	/**< Host-to-network data packets on queue3. */
+	NSS_STATS_DRV_TX_PACKET_QUEUE_4,	/**< Host-to-network data packets on queue4. */
+	NSS_STATS_DRV_TX_PACKET_QUEUE_5,	/**< Host-to-network data packets on queue5. */
+	NSS_STATS_DRV_TX_PACKET_QUEUE_6,	/**< Host-to-network data packets on queue6. */
+	NSS_STATS_DRV_TX_PACKET_QUEUE_7,	/**< Host-to-network data packets on queue7. */
+#endif
+	NSS_STATS_DRV_MAX,			/**< Maximum message type. */
+};
+
+/**
+ * nss_stats_types
+ *	List of statistics categories.
+ */
+enum nss_stats_types {
+	NSS_STATS_TYPE_COMMON,			/**< Common pnode statistics. */
+	NSS_STATS_TYPE_DROP,			/**< Packet drop statistics. */
+	NSS_STATS_TYPE_ERROR,			/**< Hardware or software errors different from drop or exception statistics. */
+	NSS_STATS_TYPE_EXCEPTION,		/**< Packet exception (to host) statistics. */
+	NSS_STATS_TYPE_SPECIAL,			/**< Statistics that do not fall into the above types. */
+	NSS_STATS_TYPE_MAX			/**< Maximum message type. */
+};
+
+/**
+ * nss_stats_notifier_action
+ *	Statistics notification types.
+ */
+enum nss_stats_notifier_action {
+	NSS_STATS_EVENT_NOTIFY,
+	NSS_STATS_EVENT_MAX
+};
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_STATS_PUBLIC_H */
diff --git a/qca-nss-drv/exports/nss_tls.h b/qca-nss-drv/exports/nss_tls.h
new file mode 100644
index 0000000..b23268e
--- /dev/null
+++ b/qca-nss-drv/exports/nss_tls.h
@@ -0,0 +1,469 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+/**
+ * @file nss_tls.h
+ *	NSS TLS common interface definitions, supports inner/outer interface split.
+ */
+
+#ifndef _NSS_TLS_H_
+#define _NSS_TLS_H_
+
+/**
+ * @addtogroup nss_tls_subsystem
+ * @{
+ */
+#define NSS_TLS_VER_TLS_1_1 0x0301			/**< TLS version 1.1, major and minor version. */
+#define NSS_TLS_VER_TLS_1_2 0x0302			/**< TLS version 1.2, major and minor version. */
+#define NSS_TLS_CLE_MAX 32				/**< Maximum classification error. */
+
+/**
+ * tls_msg_types
+ *	Message types for TLS requests and responses.
+ */
+enum nss_tls_msg_type {
+	NSS_TLS_MSG_TYPE_NODE_CONFIG,		/**< Configure TLS firmware node. */
+	NSS_TLS_MSG_TYPE_NODE_SYNC,		/**< Node statistics. */
+	NSS_TLS_MSG_TYPE_CTX_CONFIG,		/**< Send exception interface number. */
+	NSS_TLS_MSG_TYPE_CTX_DECONFIG,		/**< Context deconfigure message. */
+	NSS_TLS_MSG_TYPE_CTX_SYNC,		/**< Synchronize statistics. */
+	NSS_TLS_MSG_TYPE_CIPHER_UPDATE,		/**< Context session update.  */
+	NSS_TLS_MSG_MAX,			/**< Maximum message. */
+};
+
+/**
+ * nss_tls_error
+ *	TLS error.
+ */
+enum nss_tls_error {
+	NSS_TLS_ERROR_NONE = 0,             /**< No error. */
+	NSS_TLS_ERROR_UNKNOWN_MSG,          /**< Unknown message. */
+	NSS_TLS_ERROR_ALREADY_CONFIGURE,    /**< Node already configured. */
+	NSS_TLS_ERROR_FAIL_REG_INNER_CTX,   /**< Register inner context error. */
+	NSS_TLS_ERROR_FAIL_REG_OUTER_CTX,   /**< Register outer context error. */
+	NSS_TLS_ERROR_FAIL_REQ_POOL_ALLOC,  /**< Request pool allocation failed. */
+	NSS_TLS_ERROR_INVALID_BLK_LEN,      /**< Invalid block length. */
+	NSS_TLS_ERROR_INVALID_HASH_LEN,     /**< Invalid hash length. */
+	NSS_TLS_ERROR_INVALID_VER,          /**< Invalid TLS version. */
+	NSS_TLS_ERROR_INVALID_CTX_WORDS,    /**< Context words size mismatch with TLS. */
+	NSS_TLS_ERROR_FAIL_ALLOC_HWCTX,     /**< Failed to allocate hardware context. */
+	NSS_TLS_ERROR_FAIL_COPY_CTX,        /**< Failed to copy context. */
+	NSS_TLS_ERROR_FAIL_NOMEM,           /**< Failed memory allocation. */
+	NSS_TLS_ERROR_FAIL_INVAL_ALGO,	    /**< Invalid algorithm. */
+	NSS_TLS_ERROR_MAX,                  /**< Maximum TLS error. */
+};
+
+/**
+ * nss_tls_stats_types
+ *	TLS statistics types.
+ */
+enum nss_tls_stats_types {
+	NSS_TLS_STATS_SINGLE_REC = NSS_STATS_NODE_MAX,
+						/**< Number of transmit single record datagrams. */
+	NSS_TLS_STATS_MULTI_REC,		/**< Number of multiple transmit record datagrams. */
+	NSS_TLS_STATS_TX_INVAL_REQS,		/**< Number of transmit invalidations successfully requested. */
+	NSS_TLS_STATS_RX_CCS_REC,		/**< Number of change cipher specification records received. */
+	NSS_TLS_STATS_FAIL_CCS,			/**< Failure to switch to new crypto. */
+	NSS_TLS_STATS_ETH_NODE_DEACTIVE,	/**< Ethernet node deactivated because no crypto was available. */
+	NSS_TLS_STATS_CRYPTO_ALLOC_SUCCESS,	/**< Number of successful crypto allocations. */
+	NSS_TLS_STATS_CRYPTO_FREE_REQ,		/**< Number of crypto-free requests. */
+	NSS_TLS_STATS_CRYPTO_FREE_SUCCESS,	/**< Number of crypto-free successes. */
+	NSS_TLS_STATS_FAIL_CRYPTO_ALLOC,	/**< Number of failed crypto allocations. */
+	NSS_TLS_STATS_FAIL_CRYPTO_LOOKUP,	/**< Failure to find an active crypto session. */
+	NSS_TLS_STATS_FAIL_REQ_ALLOC,		/**< Failure to allocate request memory pool.  */
+	NSS_TLS_STATS_FAIL_PBUF_STATS,		/**< Failure in pbuf allocation for statistics. */
+	NSS_TLS_STATS_FAIL_CTX_ACTIVE,		/**< Failure in enqueue due to inactive context. */
+	NSS_TLS_STATS_HW_LEN_ERROR,		/**< Length error. */
+	NSS_TLS_STATS_HW_TOKEN_ERROR,		/**< Token error; unknown token command or instruction. */
+	NSS_TLS_STATS_HW_BYPASS_ERROR,		/**< Token contains too much bypass data. */
+	NSS_TLS_STATS_HW_CRYPTO_ERROR,		/**< Cryptographic block size error. */
+	NSS_TLS_STATS_HW_HASH_ERROR,		/**< Hash block size error. */
+	NSS_TLS_STATS_HW_CONFIG_ERROR,		/**< Invalid command, algorithm, or mode combination. */
+	NSS_TLS_STATS_HW_ALGO_ERROR,		/**< Unsupported algorithm. */
+	NSS_TLS_STATS_HW_HASH_OVF_ERROR,	/**< Hash input overflow. */
+	NSS_TLS_STATS_HW_AUTH_ERROR,		/**< Hash input overflow. */
+	NSS_TLS_STATS_HW_PAD_VERIFY_ERROR,	/**< Pad verification error. */
+	NSS_TLS_STATS_HW_TIMEOUT_ERROR,		/**< Data timed out. */
+	NSS_TLS_STATS_NO_DESC_IN,		/**< Ingress DMA descriptor not available. */
+	NSS_TLS_STATS_NO_DESC_OUT,		/**< Egress DMA descriptor not available. */
+	NSS_TLS_STATS_NO_REQS,			/**< Not enough requests available for records. */
+	NSS_TLS_STATS_MAX,			/**< Maximum statistics type. */
+};
+
+/**
+ * nss_tls_hw_stats
+ *	TLS HW statistics.
+ */
+struct nss_tls_hw_stats {
+	/*
+	 * Dont change the order below
+	 */
+	uint32_t hw_len_error;			/**< Length error. */
+	uint32_t hw_token_error;		/**< Token error, unknown token command/instruction. */
+	uint32_t hw_bypass_error;		/**< Token contains too much bypass data. */
+	uint32_t hw_crypto_error;		/**< Cryptograhic block size error. */
+	uint32_t hw_hash_error;			/**< Hash block size error. */
+	uint32_t hw_config_error;		/**< Invalid command/algorithm/mode/combination. */
+	uint32_t hw_algo_error;			/**< Unsupported algorithm. */
+	uint32_t hw_hash_ovf_error;		/**< Hash input overflow. */
+	uint32_t hw_auth_error;         	/**< Hash input overflow. */
+	uint32_t hw_pad_verify_error;		/**< Pad verification error. */
+	uint32_t hw_timeout_error;              /**< Data timed out. */
+};
+
+/**
+ * nss_tls_ctx_perf_stats
+ *	TLS performance statistics.
+ */
+struct nss_tls_ctx_perf_stats {
+	uint32_t no_desc_in;		/**< Ingress DMA descriptor not available. */
+	uint32_t no_desc_out;		/**< Egress DMA descriptor not available. */
+	uint32_t no_reqs;		/**< Not enough requests available for records. */
+};
+
+/**
+ * nss_tls_ctx_stats
+ *	TLS session statistics.
+ */
+struct nss_tls_ctx_stats {
+	struct nss_cmn_node_stats pkt;		/**< Common node statistics. */
+	uint32_t single_rec;			/**< Number of Tx single record datagrams. */
+	uint32_t multi_rec;			/**< Number of multiple Tx record datagrams. */
+	uint32_t tx_inval_reqs;			/**< Number of Tx invalidation successfully requested. */
+	uint32_t rx_ccs_rec;			/**< Number of change cipher spec records received. */
+	uint32_t fail_ccs;			/**< Failed to switch to new crypto. */
+	uint32_t eth_node_deactive;		/**< Ethernet node deactivated as no crypto available. */
+	uint32_t crypto_alloc_success;		/**< Number of crypto allocation succeeded. */
+	uint32_t crypto_free_req;		/**< Number of crypto free request. */
+	uint32_t crypto_free_success;		/**< Number of crypto free succeeded. */
+	uint32_t fail_crypto_alloc;		/**< Number of crypto allocation failed. */
+	uint32_t fail_crypto_lookup;		/**< Failed to find active crypto session. */
+	uint32_t fail_req_alloc;		/**< Failure to allocate request memory pool.  */
+	uint32_t fail_pbuf_stats;		/**< Failure in pbuf allocation for statistics. */
+	uint32_t fail_ctx_active;		/**< Failure in enqueue due to inactive context. */
+
+	struct nss_tls_hw_stats fail_hw;	/**< Hardware failure. */
+	struct nss_tls_ctx_perf_stats perf;	/**< Performance related statistics. */
+};
+
+/**
+ * nss_tls_node_stats
+ * 	TLS node statistics.
+ */
+struct nss_tls_node_stats {
+	uint32_t fail_ctx_alloc;	/**< Failure in allocating a context. */
+	uint32_t fail_ctx_free;		/**< Failure in freeing up the context. */
+	uint32_t fail_pbuf_stats;	/**< Failure in pbuf allocation for statistics. */
+};
+
+/**
+ * nss_tls_ctx_config
+ *	TLS context configuration.
+ */
+struct nss_tls_ctx_config {
+	uint32_t except_ifnum; 		/**< Exception interface number. */
+	uint32_t headroom;		/**< Headroom required for encapsulation. */
+	uint32_t tailroom;		/**< Tailroom required for encapsulation. */
+};
+
+/**
+ * nss_tls_cipher_update
+ *	TLS cipher update message.
+ *
+ */
+struct nss_tls_cipher_update {
+	uint32_t crypto_idx;    /**< Crypto index for cipher context. */
+	uint16_t ver;           /**< Version (TLS minor and major versions). */
+	uint8_t skip;		/**< Skip hardware processing. */
+	uint8_t reserved;	/**< Reserved for future use. */
+};
+
+/**
+ * nss_tls_stats_notification
+ *	TLS transmission statistics structure.
+ */
+struct nss_tls_stats_notification {
+	uint64_t stats_ctx[NSS_TLS_STATS_MAX];		/**< Context transmission statistics. */
+	uint32_t core_id;				/**< Core ID. */
+	uint32_t if_num;				/**< Interface number. */
+};
+
+/**
+ * nss_tls_msg
+ *	Data for sending and receiving TLS messages.
+ */
+struct nss_tls_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a TLS message.
+	 */
+	union {
+		struct nss_tls_cipher_update cipher_update;	/**< Crypto configuration. */
+		struct nss_tls_ctx_config ctx_cfg;	/**< Context configuration. */
+		struct nss_tls_ctx_stats stats;		/**< Context statistics. */
+		struct nss_tls_node_stats node_stats;	/**< Node statistics. */
+	} msg;			/**< Message payload for TLS session messages exchanged with NSS core. */
+};
+
+/**
+ * Callback function for receiving TLS messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_tls_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * Callback function for receiving TLS session data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_tls_data_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_tls_tx_buf
+ *	Sends a TLS data packet to the NSS.
+ *
+ * @datatypes
+ * sk_buff \n
+ * nss_ctx_instance
+ *
+ * @param[in]     os_buf   Pointer to the OS data buffer.
+ * @param[in]     if_num   NSS interface number.
+ * @param[in]     nss_ctx  Pointer to the NSS core context.
+ *
+ * @return
+ * Status of Tx buffer forwarded to NSS for TLS operation.
+ */
+nss_tx_status_t nss_tls_tx_buf(struct sk_buff *os_buf, uint32_t if_num, struct nss_ctx_instance *nss_ctx);
+
+/**
+ * nss_tls_tx_msg
+ *	Sends an asynchronous IPsec message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_tls_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS HLOS driver context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_tls_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_tls_msg *msg);
+
+/**
+ * nss_tls_tx_msg_sync
+ *	Sends a synchronous IPsec message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_tls_msg_type \n
+ * nss_tls_msg
+ *
+ * @param[in]  nss_ctx  Pointer to the NSS HLOS driver context.
+ * @param[in]  if_num   NSS interface number.
+ * @param[in]  type     Type of message.
+ * @param[in]  len      Size of the payload.
+ * @param[in]  ntcm     Pointer to the NSS IPsec message.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_tls_tx_msg_sync(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+						enum nss_tls_msg_type type, uint16_t len,
+						struct nss_tls_msg *ntcm);
+
+/**
+ * nss_tls_unregister_if
+ *	Deregisters a TLS session interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The TLS session interface must have been previously registered.
+ */
+extern void nss_tls_unregister_if(uint32_t if_num);
+
+/**
+ * nss_tls_register_if
+ *	Registers a TLS session interface with the NSS for sending and receiving
+ *	messages.
+ *
+ * @datatypes
+ * nss_tls_data_callback_t \n
+ * nss_tls_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num    NSS interface number.
+ * @param[in] data_cb   Callback function for the message.
+ * @param[in] msg_cb    Callback for TLS tunnel message.
+ * @param[in] netdev    Pointer to the associated network device.
+ * @param[in] features  Data socket buffer types supported by this interface.
+ * @param[in] type      Type of message.
+ * @param[in] app_ctx   Pointer to the application context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_tls_register_if(uint32_t if_num,
+							 nss_tls_data_callback_t data_cb,
+							 nss_tls_msg_callback_t msg_cb,
+							 struct net_device *netdev,
+							 uint32_t features,
+							 uint32_t type,
+							 void *app_ctx);
+
+/**
+ * nss_tls_notify_unregister
+ *	Deregisters an event callback.
+ *
+ * @param[in] ifnum  NSS interface number.
+ *
+ * @return
+ * None.
+ */
+extern void nss_tls_notify_unregister(uint32_t ifnum);
+
+/**
+ * nss_tls_notify_register
+ *	Registers an event callback to handle notification from TLS firmware package.
+ *
+ * @datatypes
+ * nss_tls_msg_callback_t
+ *
+ * @param[in] ifnum     NSS interface number.
+ * @param[in] ev_cb     Callback for TLS tunnel message.
+ * @param[in] app_data  Pointer to the application context.
+ *
+ * @return
+ * Pointer to NSS core context.
+ */
+extern struct nss_ctx_instance *nss_tls_notify_register(uint32_t ifnum, nss_tls_msg_callback_t ev_cb, void *app_data);
+
+/**
+ * nss_tls_msg_init
+ *	Initializes a TLS message sent asynchronously.
+ *
+ * @datatypes
+ * nss_tls_msg
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Pointer to the message callback.
+ * @param[in]     app_data  Pointer to the application context.
+ *
+ * @return
+ * None.
+ */
+extern void nss_tls_msg_init(struct nss_tls_msg *ncm, uint32_t if_num, uint32_t type, uint32_t len, void *cb, void *app_data);
+
+/**
+ * nss_tls_msg_sync_init
+ *	Initializes a TLS message.
+ *
+ * @datatypes
+ * nss_tls_msg
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ *
+ * @return
+ * None.
+ */
+extern void nss_tls_msg_sync_init(struct nss_tls_msg *ncm, uint32_t if_num, uint32_t type, uint32_t len);
+
+/**
+ * nss_tls_get_context
+ *	Gets the NSS core context for the TLS session.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_tls_get_context(void);
+
+/**
+ * nss_tls_get_device
+ *	Gets the original device from probe.
+ *
+ * @return
+ * Pointer to the device.
+ */
+extern struct device *nss_tls_get_dev(struct nss_ctx_instance *nss_ctx);
+
+/**
+ * nss_tls_ifmap_get
+ *	Returns active TLS interfaces.
+ *
+ * @return
+ * Pointer to the interface map.
+ */
+unsigned long *nss_tls_ifmap_get(void);
+
+/**
+ * nss_tls_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_tls_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * nss_tls_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ *	notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_tls_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * @}
+ */
+
+#endif /* _NSS_TLS_H_. */
diff --git a/qca-nss-drv/exports/nss_trustsec_tx.h b/qca-nss-drv/exports/nss_trustsec_tx.h
new file mode 100644
index 0000000..5fd2f74
--- /dev/null
+++ b/qca-nss-drv/exports/nss_trustsec_tx.h
@@ -0,0 +1,234 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2020, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_trustsec_tx.h
+ *	NSS TrustSec interface definitions.
+ */
+
+#ifndef __NSS_TRUSTSEC_TX_H
+#define __NSS_TRUSTSEC_TX_H
+
+/**
+ * @addtogroup nss_trustsec_tx_subsystem
+ * @{
+ */
+
+/**
+ * nss_trustsec_tx_msg_types
+ *	Message types for TrustSec Tx requests and responses.
+ */
+enum nss_trustsec_tx_msg_types {
+	NSS_TRUSTSEC_TX_MSG_CONFIGURE,		/** Configure the TrustSec node. */
+	NSS_TRUSTSEC_TX_MSG_UNCONFIGURE,	/** Unconfigure the TrustSec node. */
+	NSS_TRUSTSEC_TX_MSG_STATS_SYNC,		/** Statistics sychronization. */
+	NSS_TRUSTSEC_TX_MSG_UPDATE_NEXTHOP,	/** Update next hop. */
+	NSS_TRUSTSEC_TX_MSG_MAX			/** Maximum message type. */
+};
+
+/**
+ * nss_trustsec_tx_error_types
+ *	Error types for the TrustSec Tx interface.
+ */
+enum nss_trustsec_tx_error_types {
+	NSS_TRUSTSEC_TX_ERR_NONE,		/** No error. */
+	NSS_TRUSTSEC_TX_ERR_INVAL_SRC_IF,	/** Source interface is invalid. */
+	NSS_TRUSTSEC_TX_ERR_RECONFIGURE_SRC_IF,	/** Source interface is already configured. */
+	NSS_TRUSTSEC_TX_ERR_DEST_IF_NOT_FOUND,	/** Destination interface is not found. */
+	NSS_TRUSTSEC_TX_ERR_NOT_CONFIGURED,	/** Source interface is not configured. */
+	NSS_TRUSTSEC_TX_ERR_SGT_MISMATCH,	/** SGT mismatches. */
+	NSS_TRUSTSEC_TX_ERR_UNKNOWN,		/** Error is unknown. */
+	NSS_TRUSTSEC_TX_ERR_MAX,		/** Maximum error message. */
+};
+
+/**
+ * nss_trustsec_tx_configure_msg
+ *	Message information for configuring a TrustSec Tx interface.
+ */
+struct nss_trustsec_tx_configure_msg {
+	uint32_t src;	/**< Interface number of the source tunnel. */
+	uint32_t dest;	/**< Outgoing interface number. */
+	uint16_t sgt;	/**< Security Group Tag value to embed in the TrustSec header. */
+	uint8_t reserved[2];	/**< Reserved for word alignment. */
+};
+
+/**
+ * nss_trustsec_tx_unconfigure_msg
+ *	Message information for de-configuring a TrustSec Tx interface.
+ */
+struct nss_trustsec_tx_unconfigure_msg {
+	uint32_t src;		/**< Interface number of the source tunnel. */
+	uint16_t sgt;		/**< Security Group Tag value configured for this interface. */
+	uint8_t reserved[2];	/**< Reserved for word alignment. */
+};
+
+/**
+ * nss_trustsec_tx_stats_sync_msg
+ *	Statistics synchronization message for the TrustSec Tx interface.
+ */
+struct nss_trustsec_tx_stats_sync_msg {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics. */
+	uint32_t invalid_src;		/**< Received packets with an invalid source interface. */
+	uint32_t unconfigured_src;	/**< Received packets with a de-configured source interface. */
+	uint32_t headroom_not_enough;	/**< Not enough headroom to insert a TrustSec header. */
+};
+
+/**
+ * nss_trustsec_tx_update_nexthop_msg
+ *	Message information for updating the next hop for a TrustSec Tx interface.
+ */
+struct nss_trustsec_tx_update_nexthop_msg {
+	uint32_t src;	/**< Interface number of the source tunnel. */
+	uint32_t dest;	/**< Outgoing interface number. */
+	uint16_t sgt;	/**< Security Group Tag value to embed in the TrustSec header. */
+	uint8_t reserved[2];	/**< Reserved for word alignment. */
+};
+
+/**
+ * nss_trustsec_tx_msg
+ *	Data for sending and receiving TrustSec Tx messages.
+ */
+struct nss_trustsec_tx_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a TrustSec Tx message.
+	 */
+	union {
+		struct nss_trustsec_tx_configure_msg configure;
+				/**< Configure TrustSec Tx. */
+		struct nss_trustsec_tx_unconfigure_msg unconfigure;
+				/**< De-configure TrustSec Tx. */
+		struct nss_trustsec_tx_stats_sync_msg stats_sync;
+				/**< Synchronize TrustSec Tx statistics. */
+		struct nss_trustsec_tx_update_nexthop_msg upd_nexthop;
+				/**< Update next hop of TrustSec Tx. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving TrustSec Tx messages.
+ *
+ * @datatypes
+ * nss_trustsec_tx_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_trustsec_tx_msg_callback_t)(void *app_data, struct nss_trustsec_tx_msg *npm);
+
+/**
+ * nss_trustsec_tx_msg_init
+ *	Initializes a TrustSec Tx message.
+ *
+ * @datatypes
+ * nss_trustsec_tx_msg
+ *
+ * @param[in,out] npm       Pointer to the NSS Profiler message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the message.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * TRUE or FALSE.
+ */
+extern void nss_trustsec_tx_msg_init(struct nss_trustsec_tx_msg *npm, uint16_t if_num, uint32_t type, uint32_t len,
+							nss_trustsec_tx_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_trustsec_tx_msg
+ *	Sends a TrustSec Tx message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_trustsec_tx_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_trustsec_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_trustsec_tx_msg *msg);
+
+/**
+ * nss_trustsec_tx_msg_sync
+ *	Sends a TrustSec Tx message to the NSS and waits for a response.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_trustsec_tx_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_trustsec_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_trustsec_tx_msg *msg);
+
+/**
+ * nss_trustsec_tx_update_nexthop
+ *	Updates the next hop of the TrustSec.
+ *
+ * @param[in] src   Source interface number.
+ * @param[in] dest  Destination interface number.
+ * @param[in] sgt   Security Group Tag value.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern nss_tx_status_t nss_trustsec_tx_update_nexthop(uint32_t src, uint32_t dest, uint16_t sgt);
+
+/**
+ * nss_trustsec_tx_get_ctx
+ *	Gets the NSS context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_trustsec_tx_get_ctx(void);
+
+/**
+ * nss_trustsec_tx_configure_sgt
+ *	Configures the Security Group Tag value for a source interface.
+ *
+ * @param[in] src   Source interface number.
+ * @param[in] dest  Destination interface number.
+ * @param[in] sgt   Security Group Tag value.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern nss_tx_status_t nss_trustsec_tx_configure_sgt(uint32_t src, uint32_t dest, uint16_t sgt);
+
+/**
+ * nss_trustsec_tx_unconfigure_sgt
+ *	De-configures the Security Group Tag value for a source interface.
+ *
+ * @param[in] src  Source interface number.
+ * @param[in] sgt  Security Group Tag value.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern nss_tx_status_t nss_trustsec_tx_unconfigure_sgt(uint32_t src, uint16_t sgt);
+
+/** @} */ /* end_addtogroup nss_trustsec_tx_subsystem */
+
+#endif /* __NSS_TRUSTSEC_TX_H */
diff --git a/qca-nss-drv/exports/nss_tstamp.h b/qca-nss-drv/exports/nss_tstamp.h
new file mode 100644
index 0000000..3c23e4e
--- /dev/null
+++ b/qca-nss-drv/exports/nss_tstamp.h
@@ -0,0 +1,125 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_tstamp.h
+ *	NSS to HLOS Tstamp interface definitions.
+ */
+
+#ifndef __NSS_TSTAMP_H
+#define __NSS_TSTAMP_H
+
+/**
+ * nss_tstamp_msg_type
+ *	Time stamp message types.
+ */
+enum nss_tstamp_msg_type {
+	NSS_TSTAMP_MSG_TYPE_SYNC_STATS,	/**< Statistic synchronization message. */
+	NSS_TSTAMP_MSG_TYPE_MAX,	/**< Maximum message type. */
+};
+
+/**
+ *  nss_tstamp_h2n_pre_hdr
+ *	Metadata added by the time stamp HLOS driver.
+ *
+ * It is used while sending the packet to the NSS time stamp module.
+ */
+struct nss_tstamp_h2n_pre_hdr {
+	uint32_t ts_ifnum;	/**< Time stamp interface number. */
+	uint32_t ts_tx_hdr_sz;	/**< Total header size. */
+};
+
+/*
+ * nss_tstamp_n2h_pre_hdr
+ *	Metadata added by the NSS time stamp module.
+ *
+ * It is added before sending the packet to host.
+ */
+struct nss_tstamp_n2h_pre_hdr {
+	uint32_t ts_ifnum;	/**< Time stamp interface number. */
+	uint32_t ts_data_lo;	/**< Time stamp lower order bits. */
+	uint32_t ts_data_hi;	/**< Time stamp higher order bits. */
+
+	uint32_t ts_tx;		/**< Time stamp direction. */
+	uint32_t ts_hdr_sz;	/**< Size of the header including the skb data alignment padding. */
+	uint32_t reserved;	/**< Reserved for cache alignment. */
+};
+
+/**
+ * nss_tstamp_stats_msg
+ *	Statistics messages from the NSS firmware.
+ */
+struct nss_tstamp_stats_msg {
+	struct nss_cmn_node_stats node_stats;
+					/**< Common node statistics for time stamp. */
+	uint32_t boomeranged;		/**< Boomeranged packets. */
+	uint32_t dropped_fail_enqueue;	/**< Enqueue failed. */
+	uint32_t dropped_fail_alloc;	/**< Allocation for copy failed. */
+	uint32_t dropped_fail_copy;	/**< Copy failed. */
+	uint32_t dropped_no_interface;	/**< Next interface not found. */
+	uint32_t dropped_no_headroom;	/**< Packet does not have enough headroom. */
+};
+
+/**
+ * nss_tstamp_msg
+ *	Data for sending and receiving time stamp messages.
+ */
+struct nss_tstamp_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a time stamp common message.
+	 */
+	union {
+		struct nss_tstamp_stats_msg stats;
+				/**< Time stamp statistics. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving core-to-core transmissions messages.
+ *
+ * @datatypes
+ * nss_tstamp_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_tstamp_msg_callback_t)(void *app_data, struct nss_tstamp_msg *msg);
+
+/**
+ * nss_tstamp_notify_register
+ *	Registers a notifier callback for time stamp messages with the NSS.
+ *
+ * @datatypes
+ * nss_tstamp_msg_callback_t
+ *
+ * @param[in] cb        Callback function for the message.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_tstamp_notify_register(nss_tstamp_msg_callback_t cb, void *app_data);
+
+/**
+ * @brief Transfer the packet to time stamp NSS module.
+ *
+ * @return nss_tx_status
+ */
+nss_tx_status_t nss_tstamp_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *skb, uint32_t if_num);
+
+#endif /* __NSS_TSTAMP_H */
diff --git a/qca-nss-drv/exports/nss_tun6rd.h b/qca-nss-drv/exports/nss_tun6rd.h
new file mode 100644
index 0000000..b0675e8
--- /dev/null
+++ b/qca-nss-drv/exports/nss_tun6rd.h
@@ -0,0 +1,198 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, 2017-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_tun6rd.h
+ *	NSS TUN6RD interface definitions.
+ */
+
+#ifndef __NSS_TUN6RD_H
+#define __NSS_TUN6RD_H
+
+/**
+ * @addtogroup nss_tun6rd_subsystem
+ * @{
+ */
+
+/**
+ * nss_tun6rd_metadata_types
+ *	Message types for 6RD (IPv6 in IPv4) tunnel requests and responses.
+ */
+enum nss_tun6rd_metadata_types {
+	NSS_TUN6RD_ATTACH_PNODE,
+	NSS_TUN6RD_RX_STATS_SYNC,
+	NSS_TUN6RD_ADD_UPDATE_PEER,
+	NSS_TUN6RD_MAX,
+};
+
+/**
+ * nss_tun6rd_attach_tunnel_msg
+ *	Message information for configuring the 6RD tunnel.
+ */
+struct nss_tun6rd_attach_tunnel_msg {
+	uint32_t saddr;			/**< Source address of the tunnel. */
+	uint32_t daddr;			/**< Destination address of the tunnel. */
+	uint8_t  tos;			/**< Type Of Service field added to the outer header. */
+	uint8_t  ttl;			/**< Time-to-live value for the tunnel. */
+	uint32_t sibling_if_num;	/**< Sibling interface number. */
+	uint16_t reserved;		/**< Reserved field added for alignment. */
+};
+
+/**
+ * nss_tun6rd_sync_stats_msg
+ *	Message information for 6RD tunnel synchronization statistics.
+ */
+struct nss_tun6rd_sync_stats_msg {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics. */
+};
+
+/**
+ * nss_tun6rd_set_peer_msg
+ *	Message information for the 6RD tunnel peer address.
+ */
+struct nss_tun6rd_set_peer_msg {
+	uint32_t ipv6_address[4];	/**< IPv6 address. */
+	uint32_t dest;			/**< IPv4 address. */
+};
+
+/**
+ * nss_tun6rd_msg
+ *	Data for sending and receiving 6RD tunnel messages.
+ */
+struct nss_tun6rd_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a 6RD tunnel message.
+	 */
+	union {
+		struct nss_tun6rd_attach_tunnel_msg tunnel;
+				/**< Attach a 6RD tunnel. */
+		struct nss_tun6rd_sync_stats_msg stats;
+				/**< Synchronized statistics for the interface. */
+		struct nss_tun6rd_set_peer_msg peer;
+				/**< Add or update the peer. */
+	} msg;			/**< Message payload for 6RD tunnel messages exchanged with NSS core. */
+};
+
+/**
+ * Callback function for receiving 6RD tunnel messages.
+ *
+ * @datatypes
+ * nss_tun6rd_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_tun6rd_msg_callback_t)(void *app_data, struct nss_tun6rd_msg *msg);
+
+/**
+ * nss_tun6rd_tx
+ *	Sends a 6RD tunnel message.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_tun6rd_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_tun6rd_tx(struct nss_ctx_instance *nss_ctx, struct nss_tun6rd_msg *msg);
+
+/**
+ * nss_tun6rd_get_context
+ *	Gets the TUN6RD context used in nss_tun6rd_tx().
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_tun6rd_get_context(void);
+
+/**
+ * Callback function for receiving 6RD tunnel data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_tun6rd_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_register_tun6rd_if
+ *	Registers the TUN6RD interface with the NSS for sending and receiving messages.
+ *
+ * @datatypes
+ * nss_tun6rd_callback_t \n
+ * nss_tun6rd_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num           NSS interface number.
+ * @param[in] type             NSS interface type.
+ * @param[in] tun6rd_callback  Callback for the data.
+ * @param[in] msg_callback     Callback for the message.
+ * @param[in] netdev           Pointer to the associated network device.
+ * @param[in] features         Data socket buffer types supported by this interface.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_register_tun6rd_if(uint32_t if_num, uint32_t type, nss_tun6rd_callback_t tun6rd_callback,
+					nss_tun6rd_msg_callback_t msg_callback, struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_unregister_tun6rd_if
+ *	Deregisters the TUN6RD interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+. *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The 6RD tunnel interface must have been previously registered.
+ */
+extern void nss_unregister_tun6rd_if(uint32_t if_num);
+
+/**
+ * nss_tun6rd_msg_init
+ *	Initializes a TUN6RD message.
+ *
+ * @datatypes
+ * nss_tun6rd_msg
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Pointer to the message callback.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_tun6rd_msg_init(struct nss_tun6rd_msg *ncm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data);
+
+/** @} */ /* end_addtogroup nss_tun6rd_subsystem */
+
+#endif /* __NSS_TUN6RD_H */
diff --git a/qca-nss-drv/exports/nss_tunipip6.h b/qca-nss-drv/exports/nss_tunipip6.h
new file mode 100644
index 0000000..4b378a8
--- /dev/null
+++ b/qca-nss-drv/exports/nss_tunipip6.h
@@ -0,0 +1,293 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, 2017-2018, 2020, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_tunipip6.h
+ *	NSS TUNIPIP6 interface definitions.
+ */
+
+#ifndef __NSS_TUNIPIP6_H
+#define __NSS_TUNIPIP6_H
+
+/**
+ * Maximum number of supported TUNIPIP6 tunnels.
+ */
+#define NSS_TUNIPIP6_TUNNEL_MAX 32
+
+/**
+ * @addtogroup nss_tunipip6_subsystem
+ * @{
+ */
+
+/**
+ * nss_tunipip6_map_rule
+ *	Mapping rule (FMR/BMR) for forwarding traffic to the node in the same domain.
+ */
+struct nss_tunipip6_map_rule {
+	uint32_t ip6_prefix[4];		/**< An IPv6 prefix assigned by a mapping rule. */
+	uint32_t ip4_prefix;		/**< An IPv4 prefix assigned by a mapping rule. */
+	uint32_t ip6_prefix_len;	/**< IPv6 prefix length. */
+	uint32_t ip4_prefix_len;	/**< IPv4 prefix length. */
+	uint32_t ip6_suffix[4];		/**< IPv6 suffix. */
+	uint32_t ip6_suffix_len;	/**< IPv6 suffix length. */
+	uint32_t ea_len;		/**< Embedded Address (EA) bits. */
+	uint32_t psid_offset;		/**< PSID offset default 6. */
+};
+
+/**
+ * nss_tunipip6_err_types
+ * 	Error types for response to messages from the host.
+ */
+enum nss_tunipip6_err_types {
+	NSS_TUNIPIP6_ERR_TYPE_MAX_TUNNELS,		/**< Maximum number of tunnel reached. */
+	NSS_TUNIPIP6_ERR_TYPE_TUNNEL_EXIST,		/**< Tunnel already exists. */
+	NSS_TUNIPIP6_ERR_TYPE_ENCAP_BAD_PARAM,	/**< Bad configuration. */
+	NSS_TUNIPIP6_ERR_TYPE_ENCAP_FMR_EXIST,	/**< FMR already exists. */
+	NSS_TUNIPIP6_ERR_TYPE_ENCAP_NO_FMR,		/**< No FMR configured.*/
+	NSS_TUNIPIP6_ERR_TYPE_ENCAP_FMR_FULL,	/**< FMR table is full. */
+	NSS_TUNIPIP6_ERR_TYPE_ENCAP_INVALID_FMR,	/**< Invalid FMR configured.*/
+	NSS_TUNIPIP6_ERR_TYPE_ENCAP_BMR_EXIST,	/**< BMR already exists. */
+	NSS_TUNIPIP6_ERR_TYPE_ENCAP_NO_BMR,		/**< No BMR configured. */
+	NSS_TUNIPIP6_ERR_TYPE_ENCAP_FMR_MEM_ALLOC_FAILED,	/**< Pool allocation for FMR failed. */
+	NSS_TUNIPIP6_ERR_TYPE_UNKNOWN,		/**< Unknown message type. */
+	NSS_TUNIPIP6_ERROR_MAX,			/**< Maximum number of errors. */
+};
+
+/**
+ * nss_tunipip6_metadata_types
+ *	Message types for TUNIPIP6 (IPv4 in IPv6) tunnel requests and responses.
+ */
+enum nss_tunipip6_metadata_types {
+	NSS_TUNIPIP6_TX_ENCAP_IF_CREATE,
+	NSS_TUNIPIP6_TX_DECAP_IF_CREATE,
+	NSS_TUNIPIP6_STATS_SYNC,
+	NSS_TUNIPIP6_FMR_RULE_ADD,
+	NSS_TUNIPIP6_FMR_RULE_DEL,
+	NSS_TUNIPIP6_FMR_RULE_FLUSH,
+	NSS_TUNIPIP6_BMR_RULE_ADD,
+	NSS_TUNIPIP6_BMR_RULE_DEL,
+	NSS_TUNIPIP6_MAX,
+};
+
+/**
+ * nss_tunipip6_create_msg
+ *	Payload for configuring the TUNIPIP6 interface.
+ */
+struct nss_tunipip6_create_msg {
+	uint32_t saddr[4];						/**< Tunnel source address. */
+	uint32_t daddr[4];						/**< Tunnel destination address. */
+	uint32_t flowlabel;						/**< Tunnel IPv6 flow label. */
+	uint32_t flags;							/**< Tunnel additional flags. */
+	uint32_t sibling_if_num;					/**< Sibling interface number. */
+	uint8_t hop_limit;						/**< Tunnel IPv6 hop limit. */
+	uint8_t draft03;						/**< Use MAP-E draft03 specification. */
+	uint8_t ttl_inherit;						/**< Inherit IPv4 TTL to hoplimit. */
+	uint8_t tos_inherit;						/**< Inherit IPv4 ToS. */
+	uint8_t frag_id_update;						/**< Enable update of fragment identifier of IPv4. */
+	uint8_t reserved[3];						/**< Reserved bytes. */
+	uint32_t fmr_max;						/**< Maximum number of FMRs that can be configured. */
+};
+
+/**
+ * nss_tunipip6_debug_stats
+ * 	TUNIPIP6 debug statistics.
+ */
+struct nss_tunipip6_debug_stats {
+	struct {
+		struct {
+			uint32_t low_headroom;		/**< Low headroom for encapsulation. */
+			uint32_t unhandled_proto;	/**< Unhandled protocol for encapsulation. */
+		} exp;
+
+		struct {
+			uint32_t enqueue_fail;		/**< Encapsulation enqueue fail. */
+		} drop;
+
+		struct {
+			uint32_t err_tunnel_cfg;	/**< Tunnel configuration error. */
+			uint32_t total_fmr;		/**< Total number of existing FMRs. */
+			uint32_t fmr_add_req;		/**< FMR add requests. */
+			uint32_t fmr_del_req;		/**< FMR delete requests. */
+			uint32_t fmr_flush_req;		/**< FMR flush requests. */
+			uint32_t fmr_update_req;	/**< FMR update requests. */
+			uint32_t fmr_add_fail;		/**< FMR addition failed. */
+			uint32_t fmr_del_fail;		/**< FMR deletion failed. */
+			uint32_t err_no_fmr;		/**< No FMR configured. */
+			uint32_t bmr_add_req;		/**< BMR add requests. */
+			uint32_t bmr_del_req;		/**< BMR delete requests. */
+			uint32_t err_bmr_exist;		/**< BMR already configured. */
+			uint32_t err_no_bmr;		/**< No BMR configured. */
+		} cfg;
+	} encap;
+
+	struct {
+		struct {
+			uint32_t enqueue_fail;		/**< Decapsulation enqueue fail. */
+		} drop;
+	} decap;
+};
+
+/**
+ * nss_tunipip6_stats_sync_msg
+ *	Message information for TUNIPIP6 synchronization statistics.
+ */
+struct nss_tunipip6_stats_sync_msg {
+	struct nss_cmn_node_stats node_stats;		/**< Common node statistics. */
+	struct nss_tunipip6_debug_stats tun_stats;	/**< TUNIPIP6 debug statistics. */
+};
+
+/**
+ * nss_tunipip6_msg
+ *	Data for sending and receiving TUNIPIP6 messages.
+ */
+struct nss_tunipip6_msg {
+	struct nss_cmn_msg cm;			/**< Common message header. */
+
+	/**
+	 * Payload of a TUNIPIP6 message.
+	 */
+	union {
+		struct nss_tunipip6_create_msg tunipip6_create;
+				/**< Create a TUNIPIP6 tunnel. */
+		struct nss_tunipip6_stats_sync_msg stats;
+				/**< Synchronized statistics for the TUNIPIP6 interface. */
+		struct nss_tunipip6_map_rule map_rule;
+				/**< BMR/FMR rule to add/delete, new or existing rules. */
+	} msg;			/**< Message payload for TUNIPIP6 messages exchanged with NSS core. */
+};
+
+/**
+ * Callback function for receiving TUNIPIP6 messages.
+ *
+ * @datatypes
+ * nss_tunipip6_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_tunipip6_msg_callback_t)(void *app_data, struct nss_tunipip6_msg *msg);
+
+/**
+ * nss_tunipip6_tx
+ *	Sends a TUNIPIP6 message to NSS core.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_tunipip6_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_tunipip6_tx(struct nss_ctx_instance *nss_ctx, struct nss_tunipip6_msg *msg);
+
+/**
+ * nss_tunipip6_tx_sync
+ *	Sends a TUNIPIP6 message to NSS core synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_tunipip6_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_tunipip6_tx_sync(struct nss_ctx_instance *nss_ctx, struct nss_tunipip6_msg *msg);
+
+/**
+ * Callback function for receiving TUNIPIP6 data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_tunipip6_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_register_tunipip6_if
+ *	Registers the TUNIPIP6 interface with the NSS for sending and receiving
+ *	TUNIPIP6 messages.
+ *
+ * @datatypes
+ * nss_tunipip6_callback_t \n
+ * nss_tunipip6_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num             NSS interface number.
+ * @param[in] type               Dynamic interface type.
+ * @param[in] tunipip6_callback  Callback for the data.
+ * @param[in] event_callback     Callback for the message.
+ * @param[in] netdev             Pointer to the associated network device.
+ * @param[in] features           Data socket buffer types supported by this interface.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_register_tunipip6_if(uint32_t if_num, uint32_t type, nss_tunipip6_callback_t tunipip6_callback,
+					nss_tunipip6_msg_callback_t event_callback, struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_unregister_tunipip6_if
+ *	Deregisters the TUNIPIP6 interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ */
+extern void nss_unregister_tunipip6_if(uint32_t if_num);
+
+/**
+ * nss_tunipip6_msg_init
+ *	Initializes a TUNIPIP6 message.
+ *
+ * @datatypes
+ * nss_tunipip6_msg
+ *
+ * @param[in,out] ntm       Pointer to the IPIP6 tunnel message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the message.
+ * @param[in]     cb        Pointer to the message callback.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_tunipip6_msg_init(struct nss_tunipip6_msg *ntm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data);
+
+/**
+ * nss_tunipip6_get_context()
+ *	Get TUNIPIP6 context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_tunipip6_get_context(void);
+
+/** @} */ /* end_addtogroup nss_tunipip6_subsystem */
+
+#endif /* __NSS_TUN6RD_H */
diff --git a/qca-nss-drv/exports/nss_udp_st.h b/qca-nss-drv/exports/nss_udp_st.h
new file mode 100755
index 0000000..87e7e5e
--- /dev/null
+++ b/qca-nss-drv/exports/nss_udp_st.h
@@ -0,0 +1,284 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_udp_st.h
+ *	UDP Speed Test Subsystem interface definitions.
+ */
+
+#ifndef __NSS_UDP_ST_H
+#define __NSS_UDP_ST_H
+
+/**
+ * @addtogroup nss_udp_st_subsystem
+ * @{
+ */
+
+#define NSS_UDP_ST_TX_CONN_MAX 16
+#define NSS_UDP_ST_FLAG_IPV4 4		/**< L3 Protocol - IPv4. */
+#define NSS_UDP_ST_FLAG_IPV6 6		/**< L3 Protocol - IPv6. */
+
+/**
+ * nss_udp_st_message_types
+ *	UDP speed test message types.
+ */
+enum nss_udp_st_message_types {
+	NSS_UDP_ST_START_MSG,			/**< Start message. */
+	NSS_UDP_ST_STOP_MSG,			/**< Stop message. */
+	NSS_UDP_ST_CFG_RULE_MSG,		/**< Configure IPv4/IPv6 rule. */
+	NSS_UDP_ST_UNCFG_RULE_MSG,		/**< Unconfigure IPv4/IPv6 rule. */
+	NSS_UDP_ST_STATS_SYNC_MSG,		/**< Statistic syncronization. */
+	NSS_UDP_ST_TX_CREATE_MSG,		/**< Create transmit node. */
+	NSS_UDP_ST_TX_DESTROY_MSG,		/**< Destroy transmit node. */
+	NSS_UDP_ST_RESET_STATS_MSG,		/**< Reset existing statistics. */
+	NSS_UDP_ST_MAX_MSG_TYPES,		/**< Maximum message type. */
+};
+
+/**
+ * nss_udp_st_test_types
+ *	Test types of the UDP speed test.
+ */
+enum nss_udp_st_test_types {
+	NSS_UDP_ST_TEST_RX,			/**< Test type is receive. */
+	NSS_UDP_ST_TEST_TX,			/**< Test type is transmit. */
+	NSS_UDP_ST_TEST_MAX			/**< Maximum test type. */
+};
+
+/**
+ * nss_udp_st_error
+ *	UDP speed test error types.
+ */
+enum nss_udp_st_error {
+	NSS_UDP_ST_ERROR_NONE,			/**< No error. */
+	NSS_UDP_ST_ERROR_INCORRECT_RATE,	/**< Incorrect Tx rate. */
+	NSS_UDP_ST_ERROR_INCORRECT_BUFFER_SIZE,	/**< Incorrect buffer size. */
+	NSS_UDP_ST_ERROR_MEMORY_FAILURE,	/**< Memory allocation failed. */
+	NSS_UDP_ST_ERROR_INCORRECT_STATE,	/**< Trying to configure during incorrect state. */
+	NSS_UDP_ST_ERROR_INCORRECT_FLAGS,	/**< Incorrect flag configuration. */
+	NSS_UDP_ST_ERROR_ENTRY_EXIST,		/**< Given tunnel entry already exists. */
+	NSS_UDP_ST_ERROR_ENTRY_ADD_FAILED,	/**< UDP ST Encap entry addition failed. */
+	NSS_UDP_ST_ERROR_ENTRY_NOT_EXIST,	/**< Given tunnel entry does not exists. */
+	NSS_UDP_ST_ERROR_WRONG_START_MSG_TYPE,	/**< Start message type error. */
+	NSS_UDP_ST_ERROR_WRONG_STOP_MSG_TYPE,	/**< Stop message type error. */
+	NSS_UDP_ST_ERROR_TOO_MANY_USERS,	/**< Too many users tried to be added. */
+	NSS_UDP_ST_ERROR_UNKNOWN_MSG_TYPE,	/**< Unknown message type failure. */
+	NSS_UDP_ST_ERROR_PB_ALLOC,		/**< Pbuf allocation failed. */
+	NSS_UDP_ST_ERROR_PB_SIZE,		/**< Pbuf size is too small to fit buffer. */
+	NSS_UDP_ST_ERROR_DROP_QUEUE,		/**< Packet dropped enqueue next node. */
+	UDP_ST_ERROR_TIMER_MISSED,		/**< Timer call is missed. */
+	NSS_UDP_ST_ERROR_MAX,			/**< Maximum error type. */
+};
+
+/**
+ * nss_udp_st_stats_time
+ *	UDP speed test time statistics types.
+ */
+enum nss_udp_st_stats_time {
+	NSS_UDP_ST_STATS_TIME_START,		/**< Start time of the test. */
+	NSS_UDP_ST_STATS_TIME_CURRENT,		/**< Current time of the running test. */
+	NSS_UDP_ST_STATS_TIME_ELAPSED,		/**< Elapsed time of the current test. */
+	NSS_UDP_ST_STATS_TIME_MAX		/**< Maximum time statistics. */
+};
+
+/**
+ * Create TX node to start pushing rules.
+ */
+struct nss_udp_st_tx_create {
+	uint32_t rate;			/**< Rate in Mbps. */
+	uint32_t buffer_size;		/**< UDP buffer size. */
+	uint8_t dscp;			/**< DSCP value. */
+};
+
+/**
+ * Destroy Tx node.
+ */
+struct nss_udp_st_tx_destroy {
+	uint32_t flag;			/**< Tx destroy flag. */
+};
+
+/**
+ * NSS UDP speed test start structure.
+ */
+struct nss_udp_st_start {
+	uint32_t type;	/**< Started test type (for example, receive or transmit). */
+
+};
+
+/**
+ * NSS UDP speed test stop structure.
+ */
+struct nss_udp_st_stop {
+	uint32_t type;	/**< Stopped test type (for example, receive or transmit). */
+};
+
+/**
+ * NSS UDP speed test ip structure
+ */
+struct nss_udp_st_ip {
+	union {
+		uint32_t ipv4;          /**< IPv4 address. */
+		uint32_t ipv6[4];       /**< IPv6 address. */
+	} ip;
+};
+
+/**
+ * NSS UDP speed test IPv4/IPv6 configuration structure.
+ */
+struct nss_udp_st_cfg {
+	struct nss_udp_st_ip src_ip;	/**< Source IP address. */
+	int32_t src_port;		/**< Source L4 port. */
+	struct nss_udp_st_ip dest_ip;	/**< Destination IP address. */
+	int32_t dest_port;		/**< Destination L4 port. */
+	uint32_t type;			/**< Started test type (for example, receive or transmit). */
+	uint16_t ip_version;		/**< IP version to indicate IPv4 or IPv6. */
+};
+
+/**
+ * NSS UDP speed test node statistics structure.
+ */
+struct nss_udp_st_node_stats {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics for the UDP speed test. */
+	uint32_t errors[NSS_UDP_ST_ERROR_MAX];	/**< Error statistics. */
+};
+
+/**
+ * NSS UDP speed test statistics structure.
+ */
+struct nss_udp_st_stats {
+	struct nss_udp_st_node_stats nstats;	/**< Node statistics for the UDP speed test. */
+	uint32_t time_stats[NSS_UDP_ST_TEST_MAX][NSS_UDP_ST_STATS_TIME_MAX];
+						/**< Time statistics. */
+};
+
+/**
+ * NSS UDP speed test reset statistics structure.
+ */
+struct nss_udp_st_reset_stats {
+	uint32_t flag;  /**< Reset statistics flag. */
+};
+
+/**
+ * Message structure of the UDP speed test commands.
+ */
+struct nss_udp_st_msg {
+	struct nss_cmn_msg cm;          /**< Message header. */
+	union {
+		struct nss_udp_st_tx_create create;	/**< Prepare transmit message. */
+		struct nss_udp_st_tx_destroy destroy;	/**< Destroy transmit message. */
+		struct nss_udp_st_start start;		/**< Start message. */
+		struct nss_udp_st_stop stop;		/**< Stop message. */
+		struct nss_udp_st_cfg cfg;		/**< IPv4/IPv6 configuration message. */
+		struct nss_udp_st_cfg uncfg;		/**< IPv4/IPv6 unconfiguration message. */
+		struct nss_udp_st_stats stats;		/**< Statistics synchronization message. */
+		struct nss_udp_st_reset_stats reset_stats;
+							/**< Reset statistics message. */
+	} msg;
+};
+
+/**
+ * Callback function for receiving UDP speed test messages.
+ *
+ * @datatypes
+ * nss_udp_st_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_udp_st_msg_callback_t)(void *app_data, struct nss_udp_st_msg *msg);
+
+/**
+ * nss_udp_st_register_handler
+ *	Registers the UDP speed test message handler.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ *
+ * @return
+ * None.
+ */
+extern void nss_udp_st_register_handler(struct nss_ctx_instance *nss_ctx);
+
+/**
+ * nss_udp_st_tx
+ *	Transmits a UDP speed test message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_udp_st_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] num      Pointer to the message data.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+extern nss_tx_status_t nss_udp_st_tx(struct nss_ctx_instance *nss_ctx, struct nss_udp_st_msg *num);
+
+/**
+ * nss_udp_st_tx_sync
+ *	Transmits a synchronous UDP speed test message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_udp_st_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] num      Pointer to the message data.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+extern nss_tx_status_t nss_udp_st_tx_sync(struct nss_ctx_instance *nss_ctx, struct nss_udp_st_msg *num);
+
+/**
+ * nss_udp_st_msg_init
+ *	Initializes UDP speed test messages.
+ *
+ * @datatypes
+ * nss_udp_st_msg \n
+ * nss_udp_st_msg_callback_t
+ *
+ * @param[in,out] num       Pointer to the NSS interface message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_udp_st_msg_init(struct nss_udp_st_msg *num, uint16_t if_num, uint32_t type, uint32_t len,
+			nss_udp_st_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_udp_st_get_mgr
+ *	Gets the NSS context that is managing UDP speed sest processes.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_udp_st_get_mgr(void);
+
+/**
+ *@}
+ */
+
+#endif /* __NSS_UDP_ST_H */
diff --git a/qca-nss-drv/exports/nss_unaligned.h b/qca-nss-drv/exports/nss_unaligned.h
new file mode 100644
index 0000000..2eb6e1a
--- /dev/null
+++ b/qca-nss-drv/exports/nss_unaligned.h
@@ -0,0 +1,121 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_unaligned.h
+ *	NSS unaligned interface definitions.
+ */
+
+#ifndef __NSS_UNALIGNED_H
+#define __NSS_UNALIGNED_H
+
+/**
+ * @addtogroup nss_unaligned_subsystem
+ * @{
+ */
+
+#define NSS_UNALIGNED_OPS_PER_MSG 54
+			/**< The number of operations whose statistics are included in a message. */
+#define NSS_UNALIGNED_EMULATED_OPS 64
+			/**< The number of operations that are emulated. */
+
+/**
+ * nss_unaligned_msg_types
+ *	Unaligned message types.
+ */
+enum nss_unaligned_msg_types {
+	NSS_UNALIGNED_MSG_STATS,	/**< Performance statistics message. */
+	NSS_UNALIGNED_MSG_MAX,		/**< Maximum unaligned message type. */
+};
+
+/**
+ * nss_unaligned_stats_op
+ *	Performance statistics for emulating a single operation.
+ */
+struct nss_unaligned_stats_op {
+	uint32_t opcode_primary;
+		/**< Primary operation code. */
+	uint32_t opcode_extension;
+		/**< Extension operation code, if applicable. */
+	uint64_t count;
+		/**< Number of times operation was emulated. */
+	uint32_t ticks_min;
+		/**< Minimum number of ticks spent emulating operation. */
+	uint32_t ticks_avg;
+		/**< Average number of ticks spent emulating operation. */
+	uint32_t ticks_max;
+		/**< Maximum number of ticks spent emulating operation. */
+	uint32_t padding;
+		/**< Used for consistent alignment, can be re-used. */
+};
+
+/**
+ * nss_unaligned_stats
+ *	Message containing all non-zero operation statistics.
+ */
+struct nss_unaligned_stats {
+	uint64_t trap_count;
+					/**< Number of unaligned traps encountered. */
+	struct nss_unaligned_stats_op ops[NSS_UNALIGNED_EMULATED_OPS];
+					/**< Statistics for each operation. */
+};
+
+/**
+ * nss_unaligned_stats_msg
+ * 	Message containing all non-zero operation statistics.
+ */
+struct nss_unaligned_stats_msg {
+	uint64_t trap_count;		/**< Number of unaligned traps encountered. */
+	struct nss_unaligned_stats_op ops[NSS_UNALIGNED_OPS_PER_MSG];
+					/**< Statistics for each operation. */
+	uint32_t current_iteration;	/**< Number of full statistics messages sent without reaching the end. */
+};
+
+/**
+ * nss_unaligned_msg
+ *	Message from unaligned handler node.
+ */
+struct nss_unaligned_msg {
+	struct nss_cmn_msg cm;		/**< Message header. */
+
+	/**
+	 * Unaligned message payload.
+	 */
+	union {
+		struct nss_unaligned_stats_msg stats_msg;
+					/**< Message containing statistics. */
+	} msg;				/**< Message payload. */
+};
+
+/**
+ * nss_unaligned_register_handler()
+ *	Registers message handler on the NSS unaligned interface and
+ *	statistics dentry.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ *
+ * @return
+ * None.
+ */
+void nss_unaligned_register_handler(struct nss_ctx_instance *nss_ctx);
+
+/**
+ * @}
+ */
+#endif
diff --git a/qca-nss-drv/exports/nss_virt_if.h b/qca-nss-drv/exports/nss_virt_if.h
new file mode 100644
index 0000000..097b3e1
--- /dev/null
+++ b/qca-nss-drv/exports/nss_virt_if.h
@@ -0,0 +1,436 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2017, 2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_virt_if.h
+ *	NSS Virtual interface message Structure and APIs
+ */
+
+#ifndef __NSS_VIRT_IF_H
+#define __NSS_VIRT_IF_H
+
+#include "nss_if.h"
+
+/**
+ * @addtogroup nss_virtual_if_subsystem
+ * @{
+ */
+
+/**
+ * nss_virt_if_msg_types
+ *	Message types for virtual interface requests and responses.
+ */
+enum nss_virt_if_msg_types {
+	NSS_VIRT_IF_OPEN = NSS_IF_OPEN,
+	NSS_VIRT_IF_CLOSE = NSS_IF_CLOSE,
+	NSS_VIRT_IF_LINK_STATE_NOTIFY = NSS_IF_LINK_STATE_NOTIFY,
+	NSS_VIRT_IF_MTU_CHANGE = NSS_IF_MTU_CHANGE,
+	NSS_VIRT_IF_MAC_ADDR_SET = NSS_IF_MAC_ADDR_SET,
+	NSS_VIRT_IF_STATS_SYNC = NSS_IF_STATS,
+	NSS_VIRT_IF_ISHAPER_ASSIGN = NSS_IF_ISHAPER_ASSIGN,
+	NSS_VIRT_IF_BSHAPER_ASSIGN = NSS_IF_BSHAPER_ASSIGN,
+	NSS_VIRT_IF_ISHAPER_UNASSIGN = NSS_IF_ISHAPER_UNASSIGN,
+	NSS_VIRT_IF_BSHAPER_UNASSIGN = NSS_IF_BSHAPER_UNASSIGN,
+	NSS_VIRT_IF_ISHAPER_CONFIG = NSS_IF_ISHAPER_CONFIG,
+	NSS_VIRT_IF_BSHAPER_CONFIG = NSS_IF_BSHAPER_CONFIG,
+	NSS_VIRT_IF_VSI_ASSIGN = NSS_IF_VSI_ASSIGN,
+	NSS_VIRT_IF_VSI_UNASSIGN = NSS_IF_VSI_UNASSIGN,
+	NSS_VIRT_IF_TX_CONFIG_MSG = NSS_IF_MAX_MSG_TYPES + 1,
+	NSS_VIRT_IF_STATS_SYNC_MSG,
+	NSS_VIRT_IF_MAX_MSG_TYPES,
+};
+
+/**
+ * nss_virt_if_error_types
+ *	Error types for the virtual interface.
+ */
+enum nss_virt_if_error_types {
+	NSS_VIRT_IF_SUCCESS,
+	NSS_VIRT_IF_CORE_FAILURE,
+	NSS_VIRT_IF_ALLOC_FAILURE,
+	NSS_VIRT_IF_DYNAMIC_IF_FAILURE,
+	NSS_VIRT_IF_MSG_TX_FAILURE,
+	NSS_VIRT_IF_REG_FAILURE,
+	NSS_VIRT_IF_CORE_NOT_INITIALIZED,
+};
+
+/**
+ * nss_virt_if_base_node_stats
+ *	Virtual interface statistics of NSS base node.
+ */
+struct nss_virt_if_base_node_stats {
+	uint32_t active_interfaces;	/**< Number of active virtual interfaces. */
+	uint32_t ocm_alloc_failed;	/**< Number of interface allocation failure on OCM. */
+	uint32_t ddr_alloc_failed;	/**< Number of interface allocation failure on DDR. */
+};
+
+/**
+ * nss_virt_if_interface_stats
+ *	Virtual interface statistics of each pair of interfaces.
+ */
+struct nss_virt_if_interface_stats {
+	struct nss_cmn_node_stats node_stats;	/**< Common statistics. */
+	uint32_t tx_enqueue_failed;		/**< Tx enqueue failures in the firmware. */
+	uint32_t shaper_enqueue_failed;		/**< Shaper enqueue failures in the firmware. */
+	uint32_t ocm_alloc_failed;		/**< Number of allocation failure on OCM. */
+};
+
+/**
+ * nss_virt_if_stats
+ *	Virtual interface statistics received from the NSS.
+ */
+struct nss_virt_if_stats {
+	struct nss_virt_if_base_node_stats base_stats;	/**< Virtual interface statistics of NSS base node. */
+	struct nss_virt_if_interface_stats if_stats;	/**< Virtual interface statistics of each pair of interfaces. */
+};
+
+/**
+ * nss_virt_if_config_msg
+ *	Message information for configuring the virtual interface.
+ */
+struct nss_virt_if_config_msg {
+	uint32_t flags;			/**< Interface flags. */
+	uint32_t sibling;		/**< Sibling interface number. */
+	uint32_t nexthop;		/**< Next hop interface number. */
+	uint8_t mac_addr[ETH_ALEN];	/**< MAC address. */
+};
+
+/**
+ * nss_virt_if_msg
+ *	Data for sending and receiving virtual interface messages.
+ */
+struct nss_virt_if_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a virtual interface message.
+	 */
+	union {
+		union nss_if_msgs if_msgs;
+				/**< NSS interface base message. */
+		struct nss_virt_if_config_msg if_config;
+				/**< Rule for creating a virtual interface. */
+		struct nss_virt_if_stats stats;
+				/**< Virtual interface statistics. */
+	} msg;			/**< Message payload. */
+};
+
+/*
+ * nss_virt_if_pvt
+ *	Private data information for the virtual interface.
+ */
+struct nss_virt_if_pvt {
+	struct semaphore sem;
+			/**< Semaphore to ensure that only one instance of a message is sent to the NSS. */
+	struct completion complete;
+			/**< Waits for message completion or time out. */
+	int response;		/**< Message process response from the NSS firmware. */
+	int sem_init_done;	/**< Semaphore initialization is done. */
+};
+
+/**
+ * Callback to transmit virtual interface data received from NSS
+ * to the transmit path of the virtual interface.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ */
+typedef void (*nss_virt_if_xmit_callback_t)(struct net_device *netdev, struct sk_buff *skb);
+
+/**
+ * Callback function for virtual interface data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_virt_if_data_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for virtual interface messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_virt_if_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * nss_virt_if_handle
+ *	Context information for WLAN-to-NSS communication.
+ */
+struct nss_virt_if_handle {
+	struct nss_ctx_instance *nss_ctx;	/**< NSS context. */
+	int32_t if_num_n2h;			/**< Redirect interface number on NSS-to-host path. */
+	int32_t if_num_h2n;			/**< Redirect interface number on host-to-NSS path. */
+	struct net_device *ndev;		/**< Associated network device. */
+	struct nss_virt_if_pvt *pvt;		/**< Private data structure. */
+	struct nss_virt_if_stats stats;		/**< Virtual interface statistics. */
+	atomic_t refcnt;			/**< Reference count. */
+	nss_virt_if_msg_callback_t cb;		/**< Message callback. */
+	void *app_data;		/**< Application data to be passed to the callback. */
+};
+
+/**
+ * nss_virt_if_dp_type
+ *	Virtual interface datapath types. Redirect interface on NSS-to-host path will be seen by ECM for rules.
+ */
+enum nss_virt_if_dp_type {
+	NSS_VIRT_IF_DP_REDIR_N2H,		/**< Redirect interface on NSS-to-host path has zero value. */
+	NSS_VIRT_IF_DP_REDIR_H2N,		/**< Redirect interface on host-to-NSS path has non-zero value. */
+};
+
+/**
+ * nss_virt_if_create
+ *	Creates a virtual interface asynchronously.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_virt_if_msg_callback_t
+ *
+ * @param[in] netdev    Pointer to the associated network device.
+ * @param[in] cb        Callback function for the message. This callback is
+                        invoked when the response from the firmware is received.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern int nss_virt_if_create(struct net_device *netdev, nss_virt_if_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_virt_if_create_sync
+ *	Creates a virtual interface synchronously with the default nexthop values
+ *	NSS_N2H_INTERFACE and NSS_ETH_RX_INTERFACE.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ *
+ * @return
+ * Pointer to nss_virt_if_handle.
+ */
+extern struct nss_virt_if_handle *nss_virt_if_create_sync(struct net_device *netdev);
+
+/**
+ * nss_virt_if_create_sync_nexthop
+ *	Creates a virtual interface synchronously with specified nexthops.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] netdev       Pointer to the associated network device.
+ * @param[in] nexthop_n2h  Nexthop interface number of network-to-host dynamic interface.
+ * @param[in] nexthop_h2n  Nexthop interface number of host-to-network dynamic interface.
+ *
+ * @return
+ * Pointer to NSS virtual interface handle.
+ */
+extern struct nss_virt_if_handle *nss_virt_if_create_sync_nexthop(struct net_device *netdev, uint32_t nexthop_n2h, uint32_t nexthop_h2n);
+
+/**
+ * nss_virt_if_destroy
+ *	Destroys the virtual interface asynchronously.
+ *
+ * @datatypes
+ * nss_virt_if_handle \n
+ * nss_virt_if_msg_callback_t
+ *
+ * @param[in,out] handle    Pointer to the virtual interface handle (provided during
+ *                          dynamic interface allocation).
+ * @param[in]     cb        Callback function for the message. This callback is
+ *                          invoked when the response from the firmware is received.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * Status of the Tx operation.
+ *
+ * @dependencies
+ * The interface must have been previously created.
+ */
+extern nss_tx_status_t nss_virt_if_destroy(struct nss_virt_if_handle *handle, nss_virt_if_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_virt_if_destroy_sync
+ *	Destroys the virtual interface synchronously.
+ *
+ * @datatypes
+ * nss_virt_if_handle
+ *
+ * @param[in,out] handle  Pointer to the virtual interface handle (provided during
+ *                        dynamic interface allocation).
+ *
+ * @return
+ * Status of the Tx operation.
+ *
+ * @dependencies
+ * The interface must have been previously created.
+ */
+extern nss_tx_status_t nss_virt_if_destroy_sync(struct nss_virt_if_handle *handle);
+
+/**
+ * nss_virt_if_tx_msg
+ *	Sends a message to the virtual interface.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_virt_if_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context (provided during registration).
+ * @param[in] nvim     Pointer to the virtual interface message.
+ *
+ * @return
+ * Command Tx status.
+ */
+extern nss_tx_status_t nss_virt_if_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_virt_if_msg *nvim);
+
+/**
+ * nss_virt_if_tx_buf
+ *	Forwards virtual interface packets to the NSS.
+ *
+ * @datatypes
+ * nss_virt_if_handle \n
+ * sk_buff
+ *
+ * @param[in,out] handle  Pointer to the virtual interface handle (provided during
+ *                        registration).
+ * @param[in]    skb     Pointer to the data socket buffer.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_virt_if_tx_buf(struct nss_virt_if_handle *handle,
+						struct sk_buff *skb);
+
+/**
+ * nss_virt_if_xmit_callback_register
+ *	Registers a transmit callback to a virtual interface.
+ *
+ * @datatypes
+ * nss_virt_if_handle \n
+ * nss_virt_if_xmit_callback_t
+ *
+ * @param[in,out] handle        Pointer to the virtual interface handle (provided during
+ *                              dynamic interface allocation).
+ * @param[in]    cb             Callback handler for virtual data packets.
+ *
+ * @return
+ * None.
+ */
+extern void nss_virt_if_xmit_callback_register(struct nss_virt_if_handle *handle,
+				nss_virt_if_xmit_callback_t cb);
+
+/**
+ * nss_virt_if_xmit_callback_unregister
+ *	Deregisters the transmit callback from the virtual interface.
+ *
+ * @datatypes
+ * nss_virt_if_handle
+ *
+ * @param[in,out] handle  Pointer to the virtual interface handle.
+ *
+ * @return
+ * None.
+ */
+extern void nss_virt_if_xmit_callback_unregister(struct nss_virt_if_handle *handle);
+
+/**
+ * nss_virt_if_register
+ *	Registers a virtual Interface with NSS driver.
+ *
+ * @datatypes
+ * nss_virt_if_handle \n
+ * nss_virt_if_data_callback_t \n
+ * net_device
+ *
+ * @param[in,out] handle        Pointer to the virtual interface handle(provided during
+ *                              dynamic interface allocation).
+ * @param[in]    data_callback  Callback handler for virtual data packets
+ * @param[in]    netdev         Pointer to the associated network device.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern void nss_virt_if_register(struct nss_virt_if_handle *handle,
+					nss_virt_if_data_callback_t data_callback,
+					struct net_device *netdev);
+
+/**
+ * nss_virt_if_unregister
+ *	Deregisters a virtual interface from the NSS driver.
+ *
+ * @datatypes
+ * nss_virt_if_handle
+ *
+ * @param[in,out] handle  Pointer to the virtual interface handle.
+ *
+ * @return
+ * None.
+ */
+extern void nss_virt_if_unregister(struct nss_virt_if_handle *handle);
+
+/**
+ * nss_virt_if_get_interface_num
+ *	Returns the virtual interface number associated with the handle.
+ *
+ * @datatypes
+ * nss_virt_if_handle
+ *
+ * @param[in] handle  Pointer to the virtual interface handle(provided during
+                      dynamic interface allocation).
+ *
+ * @return
+ * Virtual interface number.
+ */
+extern int32_t nss_virt_if_get_interface_num(struct nss_virt_if_handle *handle);
+
+/**
+ * nss_virt_if_verify_if_num
+ *	Verifies if the interface is 802.3 redirect type.
+ *
+ * @param[in] if_num  Interface number to be verified.
+ *
+ * @return
+ * True if if_num is 802.3 redirect type.
+ */
+bool nss_virt_if_verify_if_num(uint32_t if_num);
+
+/**
+ * nss_virt_if_get_context
+ *	Gets the virtual interface context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_virt_if_get_context(void);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_VIRT_IF_H */
diff --git a/qca-nss-drv/exports/nss_vlan.h b/qca-nss-drv/exports/nss_vlan.h
new file mode 100644
index 0000000..872d2e0
--- /dev/null
+++ b/qca-nss-drv/exports/nss_vlan.h
@@ -0,0 +1,265 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_vlan.h
+ *	NSS VLAN interface definitions.
+ */
+
+#ifndef __NSS_VLAN_H
+#define __NSS_VLAN_H
+
+/**
+ * @addtogroup nss_vlan_subsystem
+ * @{
+ */
+
+/**
+ * nss_vlan_msg_types
+ *	VLAN message types.
+ */
+enum nss_vlan_msg_types {
+	NSS_VLAN_MSG_ADD_TAG = NSS_IF_MAX_MSG_TYPES + 1,
+	NSS_VLAN_MSG_TYPE_MAX,
+};
+
+/**
+ * nss_vlan_error_types
+ *	VLAN error types
+ */
+enum nss_vlan_error_types {
+	NSS_VLAN_ERROR_UNKNOWN_MSG = NSS_IF_ERROR_TYPE_MAX + 1,
+	NSS_VLAN_ERROR_TYPE_MAX,
+};
+
+#define NSS_VLAN_TYPE_SINGLE 0	/**< Single VLAN tag in message. */
+#define NSS_VLAN_TYPE_DOUBLE 1	/**< Double VLAN tag in message. */
+
+/**
+ * nss_vlan_msg_add_tag
+ *	VLAN message data for adding a VLAN tag.
+ */
+struct nss_vlan_msg_add_tag {
+	uint32_t vlan_tag;	/**< VLAN tag information. */
+	uint32_t next_hop;	/**< Parent interface. */
+	uint32_t if_num;	/**< Actual physical interface. */
+};
+
+/**
+ * nss_vlan_msg
+ *	Data for sending and receiving VLAN messages.
+ */
+struct nss_vlan_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a VLAN message.
+	 */
+	union {
+		union nss_if_msgs if_msg;
+				/**< NSS interface base messages. */
+		struct nss_vlan_msg_add_tag add_tag;
+				/**< VLAN add-a-tag message. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * nss_vlan_tx_msg
+ *	Sends a VLAN message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_vlan_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_vlan_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_vlan_msg *msg);
+
+/**
+ * nss_vlan_tx_msg_sync
+ *	Sends a VLAN message to the NSS synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_vlan_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_vlan_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_vlan_msg *msg);
+
+/**
+ * Initializes a VLAN message.
+ *
+ * @datatypes
+ * nss_vlan_msg
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Pointer to the message callback.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+void nss_vlan_msg_init(struct nss_vlan_msg *ncm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data);
+
+/**
+ * nss_vlan_get_context
+ *	Gets the VLAN context used in nss_vlan_tx.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_vlan_get_context(void);
+
+/**
+ * Callback when VLAN data is received
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_vlan_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback to receive VLAN messages
+ *
+ * @datatypes
+ * nss_vlan_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_vlan_msg_callback_t)(void *app_data, struct nss_vlan_msg *msg);
+
+/**
+ * nss_register_vlan_if
+ *	Register to send/receive VLAN messages to NSS
+ *
+ * @datatypes
+ * nss_vlan_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num              NSS interface number.
+ * @param[in] vlan_data_callback  Callback for the data.
+ * @param[in] netdev              Pointer to the associated network device.
+ * @param[in] features            Data socket buffer types supported by this interface.
+ * @param[in] app_ctx             Pointer to the application context of the message.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_register_vlan_if(uint32_t if_num, nss_vlan_callback_t vlan_data_callback,
+					      struct net_device *netdev, uint32_t features, void *app_ctx);
+
+/**
+ * Deregisters the VLAN interface from the NSS.
+ *
+ * @return
+ * None.
+ */
+void nss_unregister_vlan_if(uint32_t if_num);
+
+/**
+ * nss_vlan_tx_set_mtu_msg
+ *	Sends a VLAN message to set the MTU.
+ *
+ * @param[in] vlan_if_num  VLAN interface number.
+ * @param[in] mtu          MTU value to set.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_vlan_tx_set_mtu_msg(uint32_t vlan_if_num, uint32_t mtu);
+
+/**
+ * nss_vlan_tx_set_mac_addr_msg
+ *	Sends a VLAN message to set the MAC address.
+ *
+ * @param[in] vlan_if_num  VLAN interface number.
+ * @param[in] addr         Pointer to the MAC address.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_vlan_tx_set_mac_addr_msg(uint32_t vlan_if_num, uint8_t *addr);
+
+/**
+ * nss_vlan_tx_vsi_attach_msg
+ *	Send a VLAN message to attach a VSI.
+ *
+ * @param[in] vlan_if_num  VLAN interface number.
+ * @param[in] vsi          PPE VSI to attach.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_vlan_tx_vsi_attach_msg(uint32_t vlan_if_num, uint32_t vsi);
+
+/**
+ * nss_vlan_tx_vsi_detach_msg
+ *	Sends a VLAN message to detach VSI.
+ *
+ * @param[in] vlan_if_num  VLAN interface number.
+ * @param[in] vsi          VSI to detach.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_vlan_tx_vsi_detach_msg(uint32_t vlan_if_num, uint32_t vsi);
+
+/**
+ * nss_vlan_tx_add_tag_msg
+ *	Sends a VLAN add tag message.
+ *
+ * @param[in] vlan_if_num   VLAN interface number.
+ * @param[in] vlan_tag      VLAN tag information.
+ * @param[in] next_hop      Parent interface.
+ * @param[in] physical_dev  Physical port to which to add the VLAN tag.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_vlan_tx_add_tag_msg(uint32_t vlan_if_num, uint32_t vlan_tag, uint32_t next_hop, uint32_t physical_dev);
+
+/**
+ * Registers the VLAN handler with the NSS.
+ *
+ * @return
+ * None.
+ */
+void nss_vlan_register_handler(void);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_VLAN_H */
diff --git a/qca-nss-drv/exports/nss_vxlan.h b/qca-nss-drv/exports/nss_vxlan.h
new file mode 100644
index 0000000..594c4a2
--- /dev/null
+++ b/qca-nss-drv/exports/nss_vxlan.h
@@ -0,0 +1,350 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_vxlan.h
+ *	NSS VxLAN interface definitions.
+ */
+
+#ifndef __NSS_VXLAN_H
+#define __NSS_VXLAN_H
+
+/**
+ * @addtogroup nss_vxlan_subsystem
+ * @{
+ */
+
+/**
+ * Maximum number of supported VxLAN tunnel sessions.
+ */
+#define NSS_VXLAN_MAX_TUNNELS 64
+
+/**
+ * Maximum number of supported VxLAN FDB entries.
+ */
+#define NSS_VXLAN_MACDB_ENTRIES_MAX 1024
+
+/**
+ * MAC database entries per message.
+ */
+#define NSS_VXLAN_MACDB_ENTRIES_PER_MSG 20
+
+/*
+ *  VxLAN Rule configure message flags
+ */
+#define NSS_VXLAN_RULE_FLAG_GBP_ENABLED 0x0001			/**< Group Policy ID is eanbled. */
+#define NSS_VXLAN_RULE_FLAG_INHERIT_TOS 0x0002			/**< Use inner TOS for encapsulation. */
+#define NSS_VXLAN_RULE_FLAG_ENCAP_L4_CSUM_REQUIRED 0x0004	/**< Generate transmit checksum. */
+#define NSS_VXLAN_RULE_FLAG_IPV4 0x0010				/**< IPv4 tunnel. */
+#define NSS_VXLAN_RULE_FLAG_IPV6 0x0020				/**< IPv6 tunnel. */
+#define NSS_VXLAN_RULE_FLAG_UDP 0x0100				/**< UDP tunnel. */
+
+/**
+ * nss_vxlan_msg_type
+ *	Message types for VxLAN tunnel.
+ */
+enum nss_vxlan_msg_type {
+	NSS_VXLAN_MSG_TYPE_STATS_SYNC,		/**< Statistics synchronization message. */
+	NSS_VXLAN_MSG_TYPE_TUN_CONFIGURE,	/**< Creating tunnel rule. */
+	NSS_VXLAN_MSG_TYPE_TUN_UNCONFIGURE,	/**< Destroying tunnel rule. */
+	NSS_VXLAN_MSG_TYPE_TUN_ENABLE,		/**< Enable the tunnel. */
+	NSS_VXLAN_MSG_TYPE_TUN_DISABLE,		/**< Disable the tunnel. */
+	NSS_VXLAN_MSG_TYPE_MAC_ADD,		/**< Add MAC rule to the database. */
+	NSS_VXLAN_MSG_TYPE_MAC_DEL,		/**< Remove MAC rule from the database. */
+	NSS_VXLAN_MSG_TYPE_MACDB_STATS,		/**< MAC database statistics synchronization message. */
+	NSS_VXLAN_MSG_TYPE_MAX,			/**< Maximum message type. */
+};
+
+/**
+ * nss_vxlan_error_response_types
+ *	Error types for VxLAN responses to messages from the host.
+ */
+enum nss_vxlan_error_type {
+	NSS_VXLAN_ERROR_TYPE_NONE = 1,			/**< Unknown type error. */
+	NSS_VXLAN_ERROR_TYPE_DECAP_REGISTER_FAIL,	/**< Decapsulation node registration failed. */
+	NSS_VXLAN_ERROR_TYPE_DEST_IP_MISMATCH,		/**< Destination IP address mismatch. */
+	NSS_VXLAN_ERROR_TYPE_INVALID_VNI,		/**< Invalid virtual network ID. */
+	NSS_VXLAN_ERROR_TYPE_INVALID_L3_PROTO,		/**< L3 Protocol is invalid error. */
+	NSS_VXLAN_ERROR_TYPE_INVALID_UDP_PROTO,		/**< UDP Protocol is invalid error. */
+	NSS_VXLAN_ERROR_TYPE_INVALID_SRC_PORT,		/**< Source port range is invalid. */
+	NSS_VXLAN_ERROR_TYPE_MAC_BAD_ENTRY,		/**< MAC table has a bad entry. */
+	NSS_VXLAN_ERROR_TYPE_MAC_EXISTS,		/**< MAC entry exists in the table error. */
+	NSS_VXLAN_ERROR_TYPE_MAC_NOT_EXIST,		/**< MAC does not exist in the table error. */
+	NSS_VXLAN_ERROR_TYPE_MAC_ENTRY_UNHASHED,	/**< MAC entry is not hashed in table. */
+	NSS_VXLAN_ERROR_TYPE_MAC_ENTRY_ALLOC_FAILED,	/**< MAC entry allocation failed. */
+	NSS_VXLAN_ERROR_TYPE_MAC_ENTRY_DELETE_FAILED,	/**< MAC entry deletion failed. */
+	NSS_VXLAN_ERROR_TYPE_MAC_TABLE_FULL,		/**< MAC table is full error. */
+	NSS_VXLAN_ERROR_TYPE_SIBLING_NODE_NOT_EXIST,	/**< Sibling node does not exist. */
+	NSS_VXLAN_ERROR_TYPE_TUNNEL_CONFIGURED,		/**< Tunnel is already configured. */
+	NSS_VXLAN_ERROR_TYPE_TUNNEL_UNCONFIGURED,	/**< Tunnel is not configured. */
+	NSS_VXLAN_ERROR_TYPE_TUNNEL_ADD_FAILED,		/**< Adding tunnel information failed. */
+	NSS_VXLAN_ERROR_TYPE_TUNNEL_DISABLED,		/**< Tunnel is already disabled error. */
+	NSS_VXLAN_ERROR_TYPE_TUNNEL_ENABLED,		/**< Tunnel is already enabled error. */
+	NSS_VXLAN_ERROR_TYPE_TUNNEL_ENTRY_EXISTS,	/**< Tunnel already exists. */
+	NSS_VXLAN_ERROR_TYPE_MAX,			/**< Maximum error type. */
+};
+
+/**
+ * nss_vxlan_stats_msg
+ *	Per-tunnel statistics messages from the NSS firmware.
+ */
+struct nss_vxlan_stats_msg {
+	struct nss_cmn_node_stats node_stats;	/**< Common firmware statistics. */
+	uint32_t except_mac_db_lookup_failed;	/**< MAC database look up failed. */
+	uint32_t except_mac_move;		/**< User is moved. */
+	uint32_t except_low_hroom;		/**< Transmit exception due to insufficient headroom. */
+	uint32_t except_no_policy_id;		/**< Policy ID does not exist. */
+	uint32_t except_extra_vxlan_hdr_flags;	/**< More flags are set than NSS can process. */
+	uint32_t except_vni_lookup_failed;	/**< Virtual network ID look up failed. */
+	uint32_t dropped_malformed;		/**< Packet is malformed. */
+	uint32_t dropped_next_node_queue_full;	/**< Next node dropped the packet. */
+	uint32_t except_inner_hash;		/**< Inner hash calculation failed. */
+};
+
+/**
+ * nss_vxlan_rule_msg
+ *	 VxLAN rule message.
+ *
+ * The same rule structure applies for both encapsulation and decapsulation
+ * in a tunnel.
+ */
+struct nss_vxlan_rule_msg {
+	/*
+	 * VxLAN Rules
+	 */
+	uint32_t sibling_if_num;	/**< Sibling node interface number. */
+	uint32_t vni;			/**< Virtual network ID. */
+	uint16_t tunnel_flags;		/**< VxLAN tunnel flags. */
+
+	/*
+	 * IP rules
+	 */
+	uint16_t flow_label;		/**< Flow label. */
+	uint8_t tos;			/**< Type of service/traffic class. */
+	uint8_t ttl;			/**< TTL/hop limit. */
+
+	/*
+	 * L4 rules
+	 */
+	uint16_t src_port_min;		/**< Minimum permissible port number. */
+	uint16_t src_port_max;		/**< Maximum permissible port number. */
+	uint16_t dest_port;		/**< UDP destination port. */
+};
+
+/**
+ * nss_vxlan_encap_rule
+ *	Encapsulation information for a VxLAN tunnel.
+ */
+struct nss_vxlan_encap_rule {
+	uint32_t src_ip[4];	/**< Source IP. */
+	uint32_t dest_ip[4];	/**< Destination IP. */
+};
+
+/**
+ * nss_vxlan_mac_msg
+ *	VxLAN MAC message structure.
+ */
+struct nss_vxlan_mac_msg {
+	struct nss_vxlan_encap_rule encap;
+					/**< Tunnel encapsulation header. */
+	uint32_t vni;			/**< VxLAN network identifier. */
+	uint16_t mac_addr[3];		/**< MAC address. */
+};
+
+/**
+ * nss_vxlan_macdb_stats_entry
+ *	MAC database statistics entry.
+ */
+struct nss_vxlan_macdb_stats_entry {
+	uint32_t hits;			/**< Total hash hits on this hash entry. */
+	uint16_t mac[3];		/**< MAC address. */
+};
+
+/**
+ * nss_vxlan_macdb_stats_msg
+ *	VxLAN MAC database statistics.
+ */
+struct nss_vxlan_macdb_stats_msg {
+	uint16_t cnt;			/**< Number of MAC database entries copied. */
+	uint16_t reserved;		/**< Reserved for future use. */
+	struct nss_vxlan_macdb_stats_entry entry[NSS_VXLAN_MACDB_ENTRIES_PER_MSG];
+					/**< MAC database entries. */
+};
+
+/**
+ * nss_vxlan_msg
+ *	Data structure for sending and receiving VxLAN messages.
+ */
+struct nss_vxlan_msg {
+	struct nss_cmn_msg cm;			/**< Common message header. */
+
+	/**
+	 * Payload of a VxLAN message.
+	 */
+	union {
+		struct nss_vxlan_stats_msg stats;
+				/**< Synchronized statistics for the VxLAN interface. */
+		struct nss_vxlan_rule_msg vxlan_create;
+				/**< Allocate VxLAN tunnel node. */
+		struct nss_vxlan_rule_msg vxlan_destroy;
+				/**< Destroy VxLAN tunnel node. */
+		struct nss_vxlan_mac_msg mac_add;
+				/**< MAC add message for UDP encapsulation. */
+		struct nss_vxlan_mac_msg mac_del;
+				/**< MAC delete message. */
+		struct nss_vxlan_macdb_stats_msg db_stats;
+				/**< MAC database statistics. */
+	} msg;			/**< Payload for VxLAN tunnel messages exchanged with the NSS core. */
+};
+
+/**
+ * Callback function for receiving VxLAN tunnel data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_vxlan_buf_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for receiving VxLAN messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_vxlan_msg_callback_t)(void *app_data, struct nss_cmn_msg *msg);
+
+/**
+ * nss_vxlan_tx_msg
+ *	Sends VxLAN tunnel messages to the NSS.
+ *
+ * Do not call this function from a softirq or interrupt because it
+ * might sleep if the NSS firmware is busy serving another host thread.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_vxlan_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] nvm      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_vxlan_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_vxlan_msg *nvm);
+
+/**
+ * nss_vxlan_tx_msg_sync
+ *	Sends a VxLAN message to the NSS synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_vxlan_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] nvm      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_vxlan_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_vxlan_msg *nvm);
+
+/**
+ * nss_vxlan_unregister_if
+ *	Deregisters the VxLAN interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ */
+extern bool nss_vxlan_unregister_if(uint32_t if_num);
+
+/**
+ * nss_vxlan_register_if
+ *	Registers the VxLAN interface with the NSS.
+ *
+ * @datatypes
+ * nss_vxlan_buf_callback_t \n
+ * nss_vxlan_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num             NSS interface number.
+ * @param[in] type               Dynamic interface type.
+ * @param[in] data_cb            Callback for the data.
+ * @param[in] notify_cb          Callback for the message.
+ * @param[in] netdev             Pointer to the associated network device.
+ * @param[in] features           Data socket buffer types supported by this interface.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_vxlan_register_if(uint32_t if_num, uint32_t type, nss_vxlan_buf_callback_t data_cb,
+					nss_vxlan_msg_callback_t notify_cb, struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_vxlan_register_handler
+ *	Initializes VxLAN module in NSS
+ *
+ * @return
+ * None.
+ */
+extern void nss_vxlan_init(void);
+
+/**
+ * nss_vxlan_msg_init
+ *	Initializes a VxLAN message.
+ *
+ * @datatypes
+ * nss_vxlan_msg \n
+ * nss_vxlan_msg_callback_t
+ *
+ * @param[in,out] nvm       Pointer to the VxLAN tunnel message.
+ * @param[in]     if_num    NSS interface number.
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the message.
+ * @param[in]     cb        Pointer to the message callback.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+extern void nss_vxlan_msg_init(struct nss_vxlan_msg *nvm, uint16_t if_num, uint32_t type, uint32_t len,
+				nss_vxlan_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_vxlan_get_ctx()
+ *	Get VxLAN context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_vxlan_get_ctx(void);
+
+/**
+ * @}
+ */
+
+#endif
+/* __NSS_VXLAN_H */
diff --git a/qca-nss-drv/exports/nss_wifi.h b/qca-nss-drv/exports/nss_wifi.h
new file mode 100644
index 0000000..add613f
--- /dev/null
+++ b/qca-nss-drv/exports/nss_wifi.h
@@ -0,0 +1,1048 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2018, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_wifi.h
+ *	NSS TO HLOS Wi-Fi interface definitions.
+ */
+
+#ifndef __NSS_WIFI_H
+#define __NSS_WIFI_H
+
+/**
+ * @addtogroup nss_wifi_subsystem
+ * @{
+ */
+
+#define NSS_WIFI_MGMT_DATA_LEN  128		/**< Size of the Wi-Fi management data. */
+#define NSS_WIFI_FW_STATS_DATA_LEN  480		/**< Size of the firmware statictics data. */
+#define NSS_WIFI_RAWDATA_MAX_LEN  64		/**< Maximum size of the raw Wi-Fi data. */
+#define NSS_WIFI_TX_NUM_TOS_TIDS 8		/**< Number of TIDs. */
+#define NSS_WIFI_PEER_STATS_DATA_LEN 232	/**< Size of the peer statistics data. */
+#define NSS_WIFI_IPV6_ADDR_LEN 16		/**< Size of the IPv6 address. */
+#define NSS_WIFI_MAX_RSSI_CHAINS 4		/**< Maximum number of RSSI chains. */
+#define NSS_WIFI_WME_NUM_AC 4			/**< Number of ACs. */
+#define NSS_WIFI_MIC_KEY_LEN 8
+
+
+/**
+ * Maximum number of Wi-Fi peers per radio as a sum of
+ * maximum number of station peers (513),
+ * maximum numbero of AP VAP peers (16), and
+ * maximum number of monitor VAP peers (1).
+ */
+#define NSS_WIFI_MAX_PEER 530
+
+/**
+ * nss_wifi_metadata_types
+ *	Wi-Fi interface request and response message types.
+ */
+enum nss_wifi_metadata_types {
+	NSS_WIFI_INIT_MSG,
+	NSS_WIFI_POST_RECV_MSG,
+	NSS_WIFI_HTT_INIT_MSG,
+	NSS_WIFI_TX_INIT_MSG,
+	NSS_WIFI_RAW_SEND_MSG,
+	NSS_WIFI_MGMT_SEND_MSG,
+	NSS_WIFI_WDS_PEER_ADD_MSG,
+	NSS_WIFI_WDS_PEER_DEL_MSG,
+	NSS_WIFI_STOP_MSG,
+	NSS_WIFI_RESET_MSG,
+	NSS_WIFI_STATS_MSG,
+	NSS_WIFI_PEER_FREELIST_APPEND_MSG,
+	NSS_WIFI_RX_REORDER_ARRAY_FREELIST_APPEND_MSG,
+	NSS_WIFI_SEND_PEER_MEMORY_REQUEST_MSG,
+	NSS_WIFI_SEND_RRA_MEMORY_REQUEST_MSG,
+	NSS_WIFI_FW_STATS_MSG,
+	NSS_WIFI_MONITOR_FILTER_SET_MSG,
+	NSS_WIFI_PEER_BS_STATE_MSG,
+	NSS_WIFI_MSDU_TTL_SET_MSG,
+	NSS_WIFI_RX_VOW_EXTSTATS_SET_MSG,
+	NSS_WIFI_PKTLOG_CFG_MSG,
+	NSS_WIFI_ENABLE_PERPKT_TXSTATS_MSG,
+	NSS_WIFI_IGMP_MLD_TOS_OVERRIDE_MSG,
+	NSS_WIFI_OL_STATS_CFG_MSG,
+	NSS_WIFI_OL_STATS_MSG,
+	NSS_WIFI_TX_QUEUE_CFG_MSG,
+	NSS_WIFI_TX_MIN_THRESHOLD_CFG_MSG,
+	NSS_WIFI_DBDC_PROCESS_ENABLE_MSG,
+	NSS_WIFI_PRIMARY_RADIO_SET_MSG,
+	NSS_WIFI_FORCE_CLIENT_MCAST_TRAFFIC_SET_MSG,
+	NSS_WIFI_STORE_OTHER_PDEV_STAVAP_MSG,
+	NSS_WIFI_STA_KICKOUT_MSG,
+	NSS_WIFI_WNM_PEER_RX_ACTIVITY_MSG,
+	NSS_WIFI_PEER_STATS_MSG,
+	NSS_WIFI_WDS_VENDOR_MSG,
+	NSS_WIFI_TX_CAPTURE_SET_MSG,
+	NSS_WIFI_ALWAYS_PRIMARY_SET_MSG,
+	NSS_WIFI_FLUSH_HTT_CMD_MSG,
+	NSS_WIFI_CMD_MSG,
+	NSS_WIFI_ENABLE_OL_STATSV2_MSG,
+	NSS_WIFI_OL_PEER_TIME_MSG,
+	NSS_WIFI_PEER_SET_VLAN_ID_MSG,
+	NSS_WIFI_PEER_ISOLATION_MSG,
+	NSS_WIFI_PEER_AUTH_MSG,
+	NSS_WIFI_PEER_SECURITY_CFG,
+	NSS_WIFI_MAX_MSG
+};
+
+/*
+ * wifi_error_types
+ *	Wi-Fi error types.
+ */
+enum wifi_error_types {
+	NSS_WIFI_EMSG_NONE = 0,
+	NSS_WIFI_EMSG_UNKNOWN,
+	NSS_WIFI_EMSG_MGMT_DLEN,
+	NSS_WIFI_EMSG_MGMT_SEND,
+	NSS_WIFI_EMSG_CE_INIT_FAIL,
+	NSS_WIFI_EMSG_PDEV_INIT_FAIL,
+	NSS_WIFI_EMSG_HTT_INIT_FAIL,
+	NSS_WIFI_EMSG_PEER_ADD,
+	NSS_WIFI_EMSG_WIFI_START_FAIL,
+	NSS_WIFI_EMSG_STATE_NOT_RESET,
+	NSS_WIFI_EMSG_STATE_NOT_INIT_DONE,
+	NSS_WIFI_EMSG_STATE_NULL_CE_HANDLE,
+	NSS_WIFI_EMSG_STATE_NOT_CE_READY,
+	NSS_WIFI_EMSG_STATE_NOT_HTT_READY,
+	NSS_WIFI_EMSG_FW_STATS_DLEN,
+	NSS_WIFI_EMSG_FW_STATS_SEND,
+	NSS_WIFI_EMSG_STATE_TX_INIT_FAILED,
+	NSS_WIFI_EMSG_IGMP_MLD_TOS_OVERRIDE_CFG,
+	NSS_WIFI_EMSG_PDEV_INVALID,
+	NSS_WIFI_EMSG_OTHER_PDEV_STAVAP_INVALID,
+	NSS_WIFI_EMSG_HTT_SEND_FAIL,
+	NSS_WIFI_EMSG_CE_RING_INIT,
+	NSS_WIFI_EMSG_NOTIFY_CB,
+	NSS_WIFI_EMSG_PEERID_INVALID,
+	NSS_WIFI_EMSG_PEER_INVALID,
+	NSS_WIFI_EMSG_UNKNOWN_CMD,
+	NSS_WIFI_EMSG_MAX,
+};
+
+/**
+ * nss_wifi_ext_data_pkt_type
+ *	Exception types for Wi-Fi extended data.
+ */
+enum nss_wifi_ext_data_pkt_type {
+	NSS_WIFI_RX_EXT_INV_PEER_TYPE,
+	NSS_WIFI_RX_EXT_PKTLOG_TYPE,
+	NSS_WIFI_RX_STATS_V2_EXCEPTION,
+	NSS_WIFI_RX_MGMT_NULL_TYPE,
+	NSS_WIFI_RX_EXT_MAX_TYPE,
+};
+
+/**
+ * nss_wifi_cmd
+ *	Wi-Fi commands.
+ */
+enum nss_wifi_cmd {
+	NSS_WIFI_FILTER_NEIGH_PEERS_CMD,
+	NSS_WIFI_MAX_CMD
+};
+
+/**
+ * nss_wifi_ce_ring_state_msg
+ *	Internal state information for the copy engine ring.
+ */
+struct nss_wifi_ce_ring_state_msg {
+	uint32_t nentries;		/**< Number of entries in the copy engine ring. */
+	uint32_t nentries_mask;		/**< Number of entry masks. */
+	uint32_t sw_index;		/**< Initial software index. */
+	uint32_t write_index;		/**< Initial write index. */
+	uint32_t hw_index;		/**< Initial hardware index. */
+	uint32_t base_addr_CE_space;
+			/**< Physical address of the copy engine hardware ring. */
+	uint32_t base_addr_owner_space;
+			/**< Virtual address of the copy engine hardware ring. */
+};
+
+/**
+ * nss_wifi_ce_state_msg
+ *	Internal state information for the copy engine.
+ */
+struct nss_wifi_ce_state_msg {
+	struct nss_wifi_ce_ring_state_msg src_ring;
+			/**< Source ring information. */
+	struct nss_wifi_ce_ring_state_msg dest_ring;
+			/**< Destination ring information. */
+	uint32_t ctrl_addr;
+			/**< Control address relative to PCIe BAR. */
+};
+
+/**
+ * nss_wifi_init_msg
+ *	Wi-Fi initialization data.
+ */
+struct nss_wifi_init_msg {
+	uint32_t radio_id ;		/**< Radio index. */
+	uint32_t pci_mem;		/**< PCI memory address. */
+	uint32_t target_type;		/**< Wi-Fi target type. */
+	uint32_t mu_mimo_enhancement_en;
+			/**< Enable MU-MIMO enhancement. */
+	struct nss_wifi_ce_state_msg ce_tx_state;
+			/**< Transmit copy engine information. */
+	struct nss_wifi_ce_state_msg ce_rx_state;
+			/**< Receive copy engine information. */
+
+	/**
+	 * Indicates whether network processing is bypassed for this radio.
+	 */
+	uint32_t bypass_nw_process;
+};
+
+/**
+ * nss_wifi_htt_init_msg
+ *	Wi-Fi Host-to-Target (HTT) initialization data.
+ */
+struct nss_wifi_htt_init_msg {
+	uint32_t radio_id;		/**< Radio index. */
+	uint32_t ringsize;		/**< WLAN hardware MAC ring size. */
+	uint32_t fill_level;		/**< Initial fill level. */
+	uint32_t paddrs_ringptr;
+			/**< Physical address of the WLAN MAC hardware ring. */
+	uint32_t paddrs_ringpaddr;
+			/**< Virtual address of the WLAN MAC hardware ring. */
+	uint32_t alloc_idx_vaddr;
+			/**< Virtual address of the hardware ring index. */
+	uint32_t alloc_idx_paddr;
+			/**< Physical address of the hardware ring index. */
+};
+
+/**
+ * nss_wifi_tx_init_msg
+ *	Wi-Fi Tx initialization data.
+ */
+struct nss_wifi_tx_init_msg {
+	uint32_t radio_id;		/**< Radio index. */
+	uint32_t desc_pool_size;	/**< Number of descriptor pools allocated. */
+	uint32_t tx_desc_array;
+			/**< Host-initialized software WLAN descriptor pool memory. */
+	uint32_t wlanextdesc_addr;
+			/**< Starting address of the WLAN MAC extenstion descriptor pool. */
+	uint32_t wlanextdesc_size;
+			/**< Descriptor size of the WLAN MAC extenstion. */
+
+	/**
+	 * Starting virtual address, as shared by the Wi-Fi firmware, for HTT Tx descriptor memory.
+	 */
+	uint32_t htt_tx_desc_base_vaddr;
+
+	/**
+	 * HTT Tx descriptor memory start physical address as shared by Wi-Fi firmware.
+	 */
+	uint32_t htt_tx_desc_base_paddr;
+
+	uint32_t htt_tx_desc_offset;
+			/**< Descriptor size of the firmware shared HTT Tx. */
+	uint32_t pmap_addr;
+			/**< Firmware shared peer or TID map. */
+};
+
+/**
+ * nss_wifi_tx_queue_cfg_msg
+ *	Wi-Fi Tx queue configuration.
+ */
+struct nss_wifi_tx_queue_cfg_msg {
+	uint32_t size;			/**< Size of the Tx queue. */
+	uint32_t range;			/**< Peer range. */
+};
+
+/**
+ * nss_wifi_tx_min_threshold_cfg_msg
+ *	Minimum threshold configuration data for the Wi-Fi Tx queue.
+ */
+struct nss_wifi_tx_min_threshold_cfg_msg {
+	uint32_t min_threshold;		/**< Minimum threshold value of Tx queue. */
+};
+
+/**
+ * nss_wifi_rawsend_msg
+ *	Information for Wi-Fi raw data.
+ */
+struct nss_wifi_rawsend_msg {
+	uint32_t radio_id ;		/**< Radio index. */
+	uint32_t len;			/**< Size of the raw data. */
+	uint32_t array[NSS_WIFI_RAWDATA_MAX_LEN];
+					/**< Array of raw data. */
+};
+
+/**
+ * nss_wifi_mgmtsend_msg
+ *	Information for Wi-Fi management data.
+ */
+struct nss_wifi_mgmtsend_msg {
+	uint32_t desc_id;		/**< Descriptor index. */
+	uint32_t len;			/**< Size of the management data. */
+	uint8_t array[NSS_WIFI_MGMT_DATA_LEN];
+					/**< Array of management data. */
+};
+
+/**
+ *  nss_wifi_fw_stats_msg
+ *	Information for Wi-Fi firmware statistics.
+ */
+struct nss_wifi_fw_stats_msg {
+	uint32_t len;			/**< Size of the statistics data. */
+	uint8_t array[NSS_WIFI_FW_STATS_DATA_LEN];
+					/**< Array of statistics data. */
+};
+
+/**
+ *  nss_wifi_monitor_set_filter_msg
+ *	Wi-Fi Monitor mode for setting filter messages.
+ */
+struct nss_wifi_monitor_set_filter_msg {
+	uint32_t filter_type;		/**< Type of Monitor mode filter. */
+};
+
+/**
+ * nss_wifi_wds_peer_msg
+ *	Wi-Fi WDS peer-specific message.
+ */
+struct nss_wifi_wds_peer_msg {
+	uint8_t dest_mac[ETH_ALEN];	/**< MAC address of the destination. */
+	uint8_t reserved[2];		/**< Reserved for 4-byte alignment padding. */
+	uint8_t peer_mac[ETH_ALEN];	/**< MAC address of the base peer. */
+	uint8_t reserved1[2];		/**< Reserved for 4-byte alignment padding. */
+};
+
+/**
+ * nss_wifi_tx_capture_msg
+ *	Wi-Fi Tx data capture configuration.
+ */
+struct nss_wifi_tx_capture_msg {
+	uint32_t tx_capture_enable;	/**< Enable or disable Tx data capture. */
+};
+
+/**
+ * nss_wifi_reset_msg
+ *	Message to reset the Wi-Fi Radio.
+ */
+struct nss_wifi_reset_msg {
+	uint32_t radio_id;		/**< Radio index. */
+};
+
+/**
+ * nss_wifi_stop_msg
+ *	Message to stop the Wi-Fi Radio.
+ */
+struct nss_wifi_stop_msg {
+	uint32_t radio_id;		/**< Radio index. */
+};
+
+/**
+ * nss_wifi_pktlog_cfg_msg
+ *	Configuration information for a Wi-Fi packet log.
+ */
+struct nss_wifi_pktlog_cfg_msg {
+	uint32_t enable;		/**< Enables or disables a packet log. */
+	uint32_t bufsize;		/**< Size of the packet log buffer. */
+	uint32_t hdrsize;		/**< Size of the packet log header. */
+	uint32_t msdu_id_offset;	/**< Offset for the MSDU ID in the message. */
+};
+
+/**
+ * nss_wifi_ol_stats_cfg_msg
+ *	Wi-Fi offload statistics configuration.
+ */
+struct nss_wifi_ol_stats_cfg_msg {
+	uint32_t stats_cfg;	/**< Enable or disable offload statistics configuration. */
+};
+
+/**
+ * nss_wifi_enable_perpkt_txstats_msg
+ *	Wi-Fi per-packet Tx statistics configuration.
+ */
+struct nss_wifi_enable_perpkt_txstats_msg {
+	uint32_t perpkt_txstats_flag;	/**< Enable or disable Tx statistics. */
+};
+
+/**
+ * nss_wifi_peer_txtime_stats
+ *	Peer Tx timestamp statistics per TID.
+ */
+struct nss_wifi_peer_txtime_stats {
+	uint32_t sum_tx;	/**< Sum of sojourn for each packet. */
+	uint32_t sum_msdus;	/**< Number of MSDU per peer per TID. */
+};
+
+/**
+ * nss_wifi_peer_tstamp_stats
+ *	Peer ID and timestamp statistics per TID.
+ */
+struct nss_wifi_peer_tstamp_stats {
+	uint32_t peer_id;			/**< TID value. */
+	struct nss_wifi_peer_txtime_stats sum[NSS_WIFI_TX_NUM_TOS_TIDS];
+							/**< Timestamps. */
+	uint32_t avg[NSS_WIFI_TX_NUM_TOS_TIDS];	/**< Exponential weighted average. */
+};
+
+/**
+ * nss_wifi_ol_peer_time_msg
+ *	NSS Wi-Fi Tx timestamp message for n number of peers.
+ */
+struct nss_wifi_ol_peer_time_msg {
+	uint32_t npeers;			/**< Number of peers. */
+	struct nss_wifi_peer_tstamp_stats tstats[1];
+						/**< One instance of struct. */
+};
+
+/**
+ * nss_wifi_enable_ol_statsv2
+ *	Wi-Fi enable/disable send packet to host.
+ */
+struct nss_wifi_enable_ol_statsv2 {
+	uint32_t enable_ol_statsv2;	/**< Flag to send packet to host. */
+};
+
+/**
+ * nss_wifi_dbdc_process_enable_msg
+ *	Wi-Fi DBDC repeater process configuration.
+ */
+struct nss_wifi_dbdc_process_enable_msg {
+	uint32_t dbdc_process_enable;	/**< Enable or disable the DBDC process. */
+};
+
+/**
+ * nss_wifi_primary_radio_set_msg
+ *	Wi-Fi primary radio configuration message.
+ */
+struct nss_wifi_primary_radio_set_msg {
+	/**
+	 * Enable/Disable Flag to set the current radio as primary.
+	 */
+	uint32_t flag;
+};
+
+/**
+ * nss_wifi_always_primary_set_msg
+ *	Always set the Wi-Fi primary radio.
+ *
+ * The primary radio is set using the nss_wifi_primary_radio_set_msg flag.
+ * When the nss_wifi_always_primary_set_msg flag is set:
+ * - Tx -- Do not drop a unicast packet on the secondary station the VAP. Instead, give that
+ *   packet to the primary station the VAP.
+ * - Rx -- Do not drop a received unicast packet on the secondary station the VAP. Instead,
+ *   give that packet to the bridge by changing the SKB device as the primary station
+ *   VAP.
+ *
+ * Primary usage of this feature is to avoid a loopback.
+ */
+struct nss_wifi_always_primary_set_msg {
+	/**
+	 * Always use the primary radio for Tx and Rx in the DBDC repeater process.
+	 */
+	uint32_t flag;
+};
+
+/**
+ * nss_wifi_force_client_mcast_traffic_set_msg
+ *	Wi-Fi message to set the client multi-cast traffic for a radio.
+ */
+struct nss_wifi_force_client_mcast_traffic_set_msg {
+	uint32_t flag;		/**< Flag to force set the multi-cast traffic in a radio. */
+};
+
+/**
+ * wifi_store_other_pdev_stavap_msg
+ *	Store the other radio's station vap.
+ */
+struct nss_wifi_store_other_pdev_stavap_msg {
+	int stavap_ifnum;	/**< Station VAP interface number of the other radio. */
+};
+
+/**
+ * nss_wifi_pl_metadata
+ *	Wi-Fi packet log metadata.
+ */
+struct nss_wifi_pl_metadata {
+	uint32_t len;		/**< Length of single buffer in MSDU. */
+	uint32_t msdu_len;	/**< Total MSDU length. */
+	uint16_t da_tail;	/**< Destination address tail bytes. */
+	uint16_t sa_tail;	/**< Source address tail bytes. */
+	uint8_t vdev_id;	/**< Virtual device ID. */
+	uint8_t res1;		/**< Reserved for alignment. */
+	uint16_t res2;		/**< Reserved for alignment. */
+};
+
+/**
+ * nss_wifi_rx_ext_metadata
+ *	Wi-Fi Rx extended data plane metadata.
+ */
+struct nss_wifi_rx_ext_metadata{
+	uint16_t peer_id;	/**< ID of associated Peer. */
+	uint8_t htt_rx_status;	/**< Rx status of the HTT. */
+	uint8_t type;		/**< Reserved for 4 byte alignment. */
+};
+
+/**
+ * nss_wifi_mc_enhance_stats
+ *	Wi-Fi multicast enhancement statistics.
+ */
+struct nss_wifi_mc_enhance_stats {
+	uint32_t rcvd;	/**< Number of multicast frames received for conversion. */
+
+	/**
+	 * Number of unicast frames sent as part of multicast enhancement conversion.
+	 */
+	uint32_t ucast_converted;
+
+	/**
+	 * Number of multicast enhancement frames dropped because of an allocation
+	 * failure.
+	 */
+	uint32_t alloc_fail;
+
+	/**
+	 * Number of multicast enhancement frames dropped because of an enqueue failure.
+	 */
+	uint32_t enqueue_fail;
+
+	/**
+	 * Number of multicast enhancement frames dropped because of a copy failure.
+	 */
+	uint32_t copy_fail;
+
+	/**
+	 * Number of multicast enhancement frames dropped because of a peer flow control
+	 * send failure.
+	 */
+	uint32_t peer_flow_ctrl_send_fail;
+
+	/**
+	 * Number of multicast enhancement frames dropped when the destination MAC
+	 * address is the same as the source MAC address.
+	 */
+	uint32_t loopback_err;
+
+	/**
+	 * Number of multicast enhancement buffer frames dropped because of an empty
+	 * destination MAC address.
+	 */
+	uint32_t dst_addr_err;
+};
+
+/**
+ * nss_wifi_stats_sync_msg
+ *	Wi-Fi synchronization statistics.
+ */
+struct nss_wifi_stats_sync_msg {
+	struct nss_cmn_node_stats node_stats;	/**< Common node statistics. */
+	uint32_t tx_transmit_dropped;
+			/**< Number of packets dropped during transmission. */
+	uint32_t tx_transmit_completions;
+			/**< Number of packets for which Tx completions are received. */
+	uint32_t tx_mgmt_rcv_cnt;
+			/**< Number of management packets received from the host for Tx. */
+	uint32_t tx_mgmt_pkts;
+			/**< Number of management packets transmitted over Wi-Fi. */
+
+	/**
+	 * Number of management packets dropped because of a Tx failure.
+	 */
+	uint32_t tx_mgmt_dropped;
+
+	/**
+	 * Number of management packets for which Tx completions are received.
+	 */
+	uint32_t tx_mgmt_completions;
+
+	/**
+	 * Number of packets for which an Tx enqueue failed because of an invalid peer.
+	 */
+	uint32_t tx_inv_peer_enq_cnt;
+
+	/**
+	 * Number of packets with an invalid peer ID received from Wi-Fi.
+	 */
+	uint32_t rx_inv_peer_rcv_cnt;
+
+	uint32_t rx_pn_check_failed;
+			/**< Number of Rx packets that failed a packet number check. */
+
+	/**
+	 * Number of Rx packets that the Wi-Fi driver successfully processed.
+	 */
+	uint32_t rx_pkts_deliverd;
+
+	/**
+	 * Number of Rx bytes that the Wi-Fi driver successfully processed.
+	 */
+	uint32_t rx_bytes_deliverd;
+
+	uint32_t tx_bytes_transmit_completions;
+			/**< Number of bytes for which Tx completions are received. */
+
+	/**
+	 * Number of unaligned data packets that were received from Wi-Fi and dropped.
+	 */
+	uint32_t rx_deliver_unaligned_drop_cnt;
+
+	uint32_t tidq_enqueue_cnt[NSS_WIFI_TX_NUM_TOS_TIDS];
+			/**< Number of packets enqueued to TID Queue (TIDQ). */
+	uint32_t tidq_dequeue_cnt[NSS_WIFI_TX_NUM_TOS_TIDS];
+			/**< Number of packets dequeued from  TIDQ. */
+	uint32_t tidq_enqueue_fail_cnt[NSS_WIFI_TX_NUM_TOS_TIDS];
+			/**< Number of enqueue failures. */
+	uint32_t tidq_ttl_expire_cnt[NSS_WIFI_TX_NUM_TOS_TIDS];
+			/**< Number of packets expired from TIDQ. */
+	uint32_t tidq_dequeue_req_cnt[NSS_WIFI_TX_NUM_TOS_TIDS];
+			/**< Number of dequeue requests from the Wi-Fi firmware. */
+	uint32_t total_tidq_depth;
+			/**< Current queue Depth. */
+
+	/**
+	 * Total number of HTT fetch messages received from the Wi-Fi firmware.
+	 */
+	uint32_t rx_htt_fetch_cnt;
+
+	/**
+	 * Total number of packets that bypassed TIDQ and are sent to the Wi-Fi
+	 * firmware.
+	 */
+	uint32_t total_tidq_bypass_cnt;
+
+	/**
+	 * Total number of packets dropped because of a global queue full condition.
+	 */
+	uint32_t global_q_full_cnt;
+
+	/**
+	 * Total number of packets dropped because of a TID queue full condition.
+	 */
+	uint32_t tidq_full_cnt;
+
+	struct nss_wifi_mc_enhance_stats mc_enhance_stats;
+			/**< Multicast enhancement statistics. */
+
+	/**
+	 * Number of times a group entry was not present for multicast enhancement.
+	 */
+	uint32_t mc_enhance_group_entry_miss;
+
+	/**
+	 * Number of times a deny list was hit during multicast enhancement.
+	 */
+	uint32_t mc_enhance_denylist_hit;
+
+	/**
+	 * Total number of data packets dropped for an unauthorized peer.
+	 */
+	uint32_t peer_unauth_rx_pkt_drop;
+};
+
+/**
+ * nss_wifi_peer_freelist_append_msg
+ *	Information for creating a Wi-Fi peer freelist.
+ */
+struct nss_wifi_peer_freelist_append_msg {
+	uint32_t addr;		/**< Starting address of the peer freelist pool. */
+	uint32_t length;	/**< Size of the peer freelist pool. */
+	uint32_t num_peers;	/**< Maximum peer entries supported in the pool. */
+};
+
+/**
+ * nss_wifi_rx_reorder_array_freelist_append_msg
+ *	Information for creating a Wi-Fi TIDQ peer freelist array.
+ */
+struct nss_wifi_rx_reorder_array_freelist_append_msg {
+	uint32_t addr;		/**< Starting address of the TIDQ freelist pool. */
+	uint32_t length;	/**< Size of the TIDQ freelist pool. */
+
+	/**
+	 * Maximum number of Rx reorder array entries supported in the freelist pool.
+	 */
+	uint32_t num_rra;
+};
+
+/**
+ * wifi_bs_peer_inactivity
+ *	Active state information of the peer.
+ */
+struct nss_wifi_bs_peer_activity {
+	uint16_t nentries;	/**< Number of entries in the peer ID array. */
+	uint16_t peer_id[1];	/**< Array holding the peer IDs. */
+};
+
+/**
+ * nss_wifi_msdu_ttl_set_msg
+ *	Information for setting the Wi-Fi MSDU time-to-live value.
+ */
+struct nss_wifi_msdu_ttl_set_msg {
+	uint32_t msdu_ttl;	/**< TTL value to be set. */
+};
+
+/**
+ * nss_wifi_rx_vow_extstats_set_msg
+ *	VoW extended statitics set.
+ */
+struct nss_wifi_rx_vow_extstats_set_msg {
+	uint32_t vow_extstats_en;	/**< VoW extended statistics enable. */
+};
+
+/**
+ * nss_wifi_igmp_mld_override_tos_msg
+ *	Information for overriding TOS.
+ */
+struct nss_wifi_igmp_mld_override_tos_msg {
+	uint8_t igmp_mld_ovride_tid_en;
+			/**< Flag to enable TID override feature for IGMP/MLD configuration. */
+	uint8_t igmp_mld_ovride_tid_val;
+			/**< Value of TID to be overriden for IGMP/MLD. */
+	uint8_t res[2];	/**< Reserved for 4-byte alignment. */
+};
+
+/**
+ * nss_wifi_peer_ol_stats
+ *	Wi-Fi offload statistics.
+ */
+struct nss_wifi_peer_ol_stats {
+	uint32_t peer_id;	/**< ID of associated peer. */
+	uint32_t seq_num;	/**< Sequence number of the PPDU. */
+	uint32_t tx_unaggr;	/**< Number of unaggregated packets transmitted. */
+	uint32_t tx_aggr;	/**< Number of aggregated packets transmitted. */
+	uint32_t tx_mcast;	/**< Number of multicast packets sent. */
+	uint32_t tx_ucast;	/**< Number of unicast packets sent. */
+	uint32_t tx_data;	/**< Number data packets sent. */
+	uint32_t tx_bytes;	/**< Number of bytes transmitted. */
+	uint32_t tx_fail;	/**< Number of failed Tx packets. */
+	uint32_t thrup_bytes;	/**< Number of throughput bytes. */
+	uint32_t tx_bcast_pkts;	/**< Number of broadcast packets sent. */
+	uint32_t tx_bcast_bytes;/**< Number of broadcast bytes sent. */
+	uint32_t tx_mgmt;	/**< Number of Tx management frames. */
+	uint32_t tx_wme[NSS_WIFI_WME_NUM_AC];
+				/**< Data frames transmitted per AC. */
+	uint32_t rx_wme[NSS_WIFI_WME_NUM_AC];
+				/**< Data frames received per AC. */
+	uint32_t ppdu_retries;	/**< Number of PPDU retries. */
+	uint32_t rssi_chains[NSS_WIFI_MAX_RSSI_CHAINS];
+				/**< Acknowledgment RSSI per chain. */
+	uint32_t rx_msdus;	/**< Number of MSDUs received. */
+	uint32_t rx_bytes;	/**< Number of bytes received. */
+	uint32_t rx_mpdus;	/**< Number of MPDUs received. */
+	uint32_t rx_retries;	/**< Number of MPDU retries. */
+};
+
+/**
+ * nss_wifi_ol_stats_msg
+ *	Wi-Fi offload statistics.
+ */
+struct nss_wifi_ol_stats_msg {
+	uint32_t bawadv_cnt;	/**< Number of block-acknowledgment window advancements. */
+	uint32_t bcn_cnt;	/**< Number of beacons. */
+	uint32_t npeers;	/**< Number of peer statistics entries. */
+	struct nss_wifi_peer_ol_stats peer_ol_stats[1];
+				/**< Array to hold the peer statistics. */
+};
+
+/**
+ * nss_wifi_sta_kickout_msg
+ *	Station kickout message from NSS firmware.
+ */
+struct nss_wifi_sta_kickout_msg {
+	uint32_t peer_id;	/**< Peer ID. */
+};
+
+/**
+ * nss_wifi_peer_isolation_msg
+ *	Peer isolation message
+ */
+struct nss_wifi_peer_isolation_msg {
+	uint16_t peer_id;	/**< Peer ID. */
+	uint16_t isolation;	/**< Isolation enabled/disabled. */
+};
+
+/*
+ * nss_wifi_peer_auth_msg
+ *	Peer authentication flag status.
+ */
+struct nss_wifi_peer_auth_msg {
+	uint16_t peer_id;	/**< Peer ID. */
+	uint16_t auth_flag;	/**< Peer authentication flag. */
+};
+
+/**
+ * nss_wifi_wnm_peer_rx_activity_msg
+ *	Receive active state information for the peer.
+ */
+struct nss_wifi_wnm_peer_rx_activity_msg {
+	uint16_t nentries;	/**< Number of entries. */
+
+	/**
+	 * Array to hold the peer IDs for which the activity is reported.
+	 */
+	uint16_t peer_id[NSS_WIFI_MAX_PEER];
+};
+
+/**
+ * nss_wifi_peer_security_type_msg
+ *	Wi-fi security type message.
+ */
+struct nss_wifi_peer_security_type_msg {
+	uint16_t peer_id;			/**< Peer ID. */
+	uint8_t pkt_type;			/**< Unicast or broadcast packet type. */
+	uint8_t security_type;			/**< Security type. */
+	uint8_t mic_key[NSS_WIFI_MIC_KEY_LEN];	/**< MIC key. */
+};
+
+/**
+ * nss_wifi_append_metaheader
+ * 	Append metaheader after pbuf->data for stats_v2.
+ */
+struct nss_wifi_append_statsv2_metahdr {
+	uint32_t rxstatsmagic;	/**< Magic to be verified on host. */
+	uint32_t seq_number;	/**< Sequence number of packets sent from NSS. */
+	uint16_t peer_id;	/**< Peer ID of peer. */
+	uint16_t num_msdus;	/**< Number of MSDU in PPDU. */
+	uint16_t num_retries;	/**< Number of retries in PPDU. */
+	uint16_t num_mpdus;	/**< Number of MPDU in PPDU. */
+	uint32_t num_bytes;	/**< Number of bytes in PPDU. */
+};
+
+/**
+ * nss_wifi_peer_stats_msg
+ *	Wi-Fi peer statistics.
+ */
+struct nss_wifi_peer_stats_msg {
+	uint32_t peer_id;		/**< Peer ID. */
+	uint32_t tidq_byte_cnt[NSS_WIFI_TX_NUM_TOS_TIDS];
+			/**< Number of bytes in each TIDQ. */
+	uint32_t tidq_queue_max[NSS_WIFI_TX_NUM_TOS_TIDS];
+			/**< Maximum depth for the TID queue. */
+	uint32_t tidq_enqueue_cnt[NSS_WIFI_TX_NUM_TOS_TIDS];
+			/**< Number of packets enqueued to the TIDQ. */
+	uint32_t tidq_dequeue_cnt[NSS_WIFI_TX_NUM_TOS_TIDS];
+			/**< Number of packets dequeued from the TIDQ. */
+	uint32_t tidq_ttl_expire_cnt[NSS_WIFI_TX_NUM_TOS_TIDS];
+			/**< Number of expired packets from the TIDQ. */
+	uint32_t tidq_dequeue_req_cnt[NSS_WIFI_TX_NUM_TOS_TIDS];
+			/**< Number of dequeue requests from the Wi-Fi firmware. */
+
+	/**
+	 * Total number of packets dropped because the TID queue is full.
+	 */
+	uint32_t tidq_full_cnt[NSS_WIFI_TX_NUM_TOS_TIDS];
+};
+
+/**
+ * nss_wifi_wds_extn_peer_cfg_msg
+ *	Configuration information when the WDS extension is enabled.
+ */
+struct nss_wifi_wds_extn_peer_cfg_msg {
+	uint8_t mac_addr[ETH_ALEN];	/**< Mac address of the peer. */
+	uint8_t wds_flags;		/**< WDS flags populated from the host. */
+	uint8_t reserved;		/**< Alignment padding. */
+	uint16_t peer_id;		/**< ID of the peer. */
+};
+
+/**
+ * nss_wifi_cmd_msg
+ *	Wi-Fi radio specific special commands to NSS Firmware
+ */
+struct nss_wifi_cmd_msg {
+	uint32_t cmd;			/**< Type of command message. */
+	uint32_t value;			/**< Value of the command. */
+};
+
+/**
+ * nss_wifi_msg
+ *	Data for sending and receiving Wi-Fi messages.
+ */
+struct nss_wifi_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Message Payload.
+	 */
+	union {
+		struct nss_wifi_init_msg initmsg;
+				/**< Wi-Fi Radio initialization message. */
+		struct nss_wifi_stop_msg stopmsg;
+				/**< Wi-Fi Radio stop message. */
+		struct nss_wifi_reset_msg resetmsg;
+				/**< Wi-Fi Radio reset message. */
+		struct nss_wifi_htt_init_msg httinitmsg;
+				/**< HTT initialization message. */
+		struct nss_wifi_tx_init_msg pdevtxinitmsg;
+				/**< Tx initialization message. */
+		struct nss_wifi_rawsend_msg rawmsg;
+				/**< Wi-Fi raw data send message. */
+		struct nss_wifi_mgmtsend_msg mgmtmsg;
+				/**< Wi-Fi management data send message. */
+		struct nss_wifi_wds_peer_msg pdevwdspeermsg;
+				/**< WDS peer-specific message. */
+		struct nss_wifi_stats_sync_msg statsmsg;
+				/**< Synchronization statistics. */
+		struct nss_wifi_peer_freelist_append_msg peer_freelist_append;
+				/**< Message for creating/appending peer freelist memory. */
+
+		/**
+		 * Message for creating/appending a reorder array for Wi-Fi Receive Defragmentation.
+		 */
+		struct nss_wifi_rx_reorder_array_freelist_append_msg rx_reorder_array_freelist_append;
+
+		struct nss_wifi_fw_stats_msg fwstatsmsg;
+				/**< Wi-Fi firmware statistics information message. */
+		struct nss_wifi_monitor_set_filter_msg monitor_filter_msg;
+				/**< Set the filter message for Monitor mode. */
+		struct nss_wifi_bs_peer_activity peer_activity;
+				/**< Message to get the active peer for a radio. */
+		struct nss_wifi_msdu_ttl_set_msg msdu_ttl_set_msg;
+				/**< Set MSDU time-to-live. */
+		struct nss_wifi_rx_vow_extstats_set_msg vow_extstats_msg;
+				/**< Enable VoW extended statistics message. */
+		struct nss_wifi_pktlog_cfg_msg pcm_msg;
+				/**< Packet log configuration message. */
+		struct nss_wifi_enable_perpkt_txstats_msg ept_msg;
+				/**< Enable or disable per-packet Tx statistics. */
+		struct nss_wifi_igmp_mld_override_tos_msg wigmpmldtm_msg;
+				/**< Message to enable TID override for IGMP/MLD. */
+		struct nss_wifi_ol_stats_cfg_msg scm_msg;
+				/**< Enable or disable offload statistics configuration. */
+		struct nss_wifi_ol_stats_msg ol_stats_msg;
+				/**< Offload statistics. */
+		struct nss_wifi_tx_queue_cfg_msg wtxqcm;
+				/**< Tx queue configuration. */
+
+		/**
+		 * Minimum threshold configuration data for the Tx queue.
+		 */
+		struct nss_wifi_tx_min_threshold_cfg_msg wtx_min_threshold_cm;
+
+		struct nss_wifi_dbdc_process_enable_msg dbdcpe_msg;
+				/**< Enable or disable the DBDC repeater process. */
+		struct nss_wifi_primary_radio_set_msg wprs_msg;
+				/**< Set the current radio as the primary radio. */
+		struct nss_wifi_force_client_mcast_traffic_set_msg wfcmts_msg;
+				/**< Message to force multicast traffic for a radio. */
+		struct nss_wifi_store_other_pdev_stavap_msg wsops_msg;
+				/**< Message to store the other radio's station vap. */
+		struct nss_wifi_sta_kickout_msg sta_kickout_msg;
+				/**< Station kickout message from NSS firmware. */
+		struct nss_wifi_wnm_peer_rx_activity_msg wprm;
+				/**< Rx activity for the peer. */
+		struct nss_wifi_peer_stats_msg peer_stats_msg;
+				/**< Peer statistics message. */
+		struct nss_wifi_wds_extn_peer_cfg_msg wpeercfg;
+				/**< Configuartion information message when the WDS extension is enabled. */
+		struct nss_wifi_tx_capture_msg tx_capture_msg;
+				/**< Enable or disable Tx data capture. */
+		struct nss_wifi_always_primary_set_msg waps_msg;
+				/**< Message to always set the current radio as primary radio. */
+		struct nss_wifi_cmd_msg wcmdm;
+				/**< Pdev command information. */
+		struct nss_wifi_enable_ol_statsv2 wesh_msg;
+				/**< Enable version 2 transmit/receive statistics. */
+		struct nss_wifi_ol_peer_time_msg wopt_msg;
+				/**< Send per peer/TID timestamp statistics to host. */
+		struct nss_wifi_peer_isolation_msg isolation_msg;
+				/**< Enable or disable peer isolation. */
+		struct nss_wifi_peer_auth_msg auth_msg;
+				/**< Enable or disable peer authorization. */
+		struct nss_wifi_peer_security_type_msg securitymsg;
+				/**< Wifili peer security message. */
+	} msg; /**< Message Payload. */
+};
+
+/**
+ * nss_wifi_get_context
+ *	Gets the Wi-Fi context used in NSS GRE transmit.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_wifi_get_context(void);
+
+/**
+ * nss_wifi_tx_msg
+ *	Sends a Wi-Fi message to the NSS firmware.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_wifi_if_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_wifi_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_wifi_msg *msg);
+
+/**
+ * Callback function for receiving Wi-Fi messages.
+ *
+ * @datatypes
+ * nss_wifi_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_wifi_msg_callback_t)(void *app_data, struct nss_wifi_msg *msg);
+
+/**
+ * Callback function for receiving Wi-Fi data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_wifi_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_register_wifi_if
+ *	Registers the Wi-Fi interface with the NSS for sending and receiving messages.
+ *
+ * @datatypes
+ * nss_wifi_callback_t \n
+ * nss_wifi_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num             NSS interface number.
+ * @param[in] wifi_callback      Callback for the data.
+ * @param[in] wifi_ext_callback  Callback for the extended data.
+ * @param[in] event_callback     Callback for the message.
+ * @param[in] netdev             Pointer to the associated network device.
+ * @param[in] features           Data socket buffer types supported by this interface.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_register_wifi_if(uint32_t if_num, nss_wifi_callback_t wifi_callback,
+						nss_wifi_callback_t wifi_ext_callback, nss_wifi_msg_callback_t event_callback, struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_unregister_wifi_if
+ *	Deregisters the Wi-Fi interface from the NSS.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ */
+void nss_unregister_wifi_if(uint32_t if_num);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_WIFI_H */
diff --git a/qca-nss-drv/exports/nss_wifi_ext_vdev_if.h b/qca-nss-drv/exports/nss_wifi_ext_vdev_if.h
new file mode 100644
index 0000000..338d3b2
--- /dev/null
+++ b/qca-nss-drv/exports/nss_wifi_ext_vdev_if.h
@@ -0,0 +1,306 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_wifi_ext_vdev_if.h
+ *	NSS Wi-Fi extended virtual device interface definitions.
+ */
+
+#ifndef __NSS_WIFI_EXT_VDEV_IF_H
+#define __NSS_WIFI_EXT_VDEV_IF_H
+
+#define NSS_WIFI_EXT_VDEV_MAX 16
+
+/**
+ * @addtogroup nss_wifi_ext_vdev_subsystem
+ * @{
+ */
+
+/*
+ * nss_wifi_ext_vdev_msg_types
+ *	WiFi extension virtual device mesage types.
+ */
+enum nss_wifi_ext_vdev_msg_types {
+	NSS_WIFI_EXT_VDEV_MSG_CONFIGURE_IF = NSS_IF_MAX_MSG_TYPES + 1,
+	NSS_WIFI_EXT_VDEV_MSG_CONFIGURE_WDS,
+	NSS_WIFI_EXT_VDEV_SET_NEXT_HOP,
+	NSS_WIFI_EXT_VDEV_MSG_STATS_SYNC,
+	NSS_WIFI_EXT_VDEV_MSG_CONFIGURE_VLAN,
+	NSS_WIFI_EXT_VDEV_MSG_MAX
+};
+
+/**
+ * nss_wifi_ext_vdev_error_tyes
+ *	WiFi extension error types.
+ */
+enum nss_wifi_ext_vdev_error_types {
+	NSS_WIFI_EXT_VDEV_ERROR_NONE = NSS_IF_ERROR_TYPE_MAX + 1,
+						/** Configuration successful. */
+	NSS_WIFI_EXT_VDEV_ERROR_NULL_MAC,		/**< NULL MAC received. */
+	NSS_WIFI_EXT_VDEV_ERROR_INV_RADIO_ID,	/**< Invalid radio interface number. */
+	NSS_WIFI_EXT_VDEV_ERROR_INV_PVAP_ID,	/**< Invalid parent virtual device interface number. */
+	NSS_WIFI_EXT_VDEV_ERROR_RADIO_NOT_PRESENT,	/**< Radio node is not present. */
+	NSS_WIFI_EXT_VDEV_ERROR_INV_IF,		/**< Message sent on invalid interface number. */
+	NSS_WIFI_EXT_VDEV_ERROR_INV_VLAN_ID,	/**< Invalid VLAN ID. */
+	NSS_WIFI_EXT_VDEV_ERROR_INV_CMD,	/**< Invalid command. */
+	NSS_WIFI_EXT_VDEV_ERROR_PEERID_ALREADY_CONFIGURED,
+						/**< Peer ID is already configured. */
+	NSS_WIFI_EXT_VDEV_ERROR_MAX		/**< Maxiumum error types. */
+};
+
+/**
+ * nss_wifi_ext_vdev_wds_msg
+ *	Extended WDS configuration message.
+ */
+struct nss_wifi_ext_vdev_wds_msg {
+	uint16_t wds_peer_id;	/**< WDS station peer ID. */
+	uint16_t mac_addr[3];	/**< Remote MAC address. */
+};
+
+/**
+ * nss_wifi_ext_vdev_stats
+ *	Statistics message structure.
+ */
+struct nss_wifi_ext_vdev_stats {
+	struct nss_cmn_node_stats node_stats;	/**< Ethernet node statistics. */
+	uint32_t mc_count;			/**< Number of mulitcast counts. */
+	uint32_t nxt_hop_drp;			/**< Next hop drop. */
+};
+
+/**
+ * nss_wifi_vdev_config_msg
+ *	NSS Wi-Fi virtual device configuration message.
+ */
+struct nss_wifi_ext_vdev_configure_if_msg {
+	uint8_t mac_addr[ETH_ALEN];	/**< MAC address. */
+	uint16_t radio_ifnum;		/**< Radio interface corresponding to virtual AP. */
+	uint16_t pvap_ifnum;		/**< Parent virtual device interface number. */
+};
+
+/**
+ * nss_wifi_ext_vdev_set_next_hop_msg
+ *	Message to set the next hop.
+ */
+struct nss_wifi_ext_vdev_set_next_hop_msg {
+	uint32_t if_num;		/**< Interface number. */
+};
+
+/**
+ * nss_wifi_ext_vdev_vlan_msg
+ *	Extended VLAN configuration message.
+ */
+struct nss_wifi_ext_vdev_vlan_msg {
+	uint16_t vlan_id;	/**< VLAN ID. */
+};
+
+/**
+ * nss_wifi_ext_vdev_msg
+ *	Message structure to Send/Receive commands.
+ */
+struct nss_wifi_ext_vdev_msg {
+	struct nss_cmn_msg cm;				/**< Cnode message. */
+	union {
+		union nss_if_msgs if_msg; /**< NSS interface base message. */
+		struct nss_wifi_ext_vdev_configure_if_msg cmsg;	/**< Interface configuration message. */
+		struct nss_wifi_ext_vdev_wds_msg wmsg;	/**< WDS configure message. */
+		struct nss_wifi_ext_vdev_set_next_hop_msg wnhm;	/**< Next hop set message. */
+		struct nss_wifi_ext_vdev_stats stats;	/**< Statistics messasge. */
+		struct nss_wifi_ext_vdev_vlan_msg vmsg;	/**< VLAN message. */
+	} msg;
+};
+
+/**
+ * Callback function for receiving Wi-Fi extended virtual device data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_wifi_ext_vdev_data_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for receiving Wi-Fi extended virtual device messages.
+ *
+ * @datatypes
+ * nss_wifi_ext_vdev_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] wevm      Pointer to the message data.
+ */
+typedef void (*nss_wifi_ext_vdev_msg_callback_t)(void *app_data, struct nss_cmn_msg *ncm);
+
+/**
+ * Callback function for receiving extended data from the Wi-Fi extended virtual device interface.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ * @param[in] netdev  Pointer to the associated network device.
+ */
+typedef void (*nss_wifi_ext_vdev_ext_data_callback_t)(struct net_device *netdev,
+				struct sk_buff *skb, struct napi_struct *napi);
+/**
+ * nss_wifi_ext_vdev_msg_init
+ *	Initializes a Wi-Fi extended virtual device message.
+ *
+ * @datatypes
+ * nss_wifi_vdev_msg \n
+ * nss_wifi_vdev_msg_callback_t
+ *
+ * @param[in] nim       Pointer to the NSS interface message.
+ * @param[in] if_num    NSS interface number.
+ * @param[in] type      Type of message.
+ * @param[in] len       Length of message.
+ * @param[in] cb        Message callback.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+void nss_wifi_ext_vdev_msg_init(struct nss_wifi_ext_vdev_msg *nim, uint32_t if_num, uint32_t type, uint32_t len,
+				nss_wifi_ext_vdev_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_wifi_ext_vdev_unregister_if
+ *      Deregisters a Wi-Fi extended virtual interface from the NSS.
+ *
+ * @param[in] if_num  Wi-Fi extended virtual interface number.
+ *
+ * @return
+ * None.
+ *
+ * @dependencies
+ * The Wi-Fi extended virtual interface must have been previously registered.
+ *
+ * @return
+ * True if successful, else false.
+ */
+extern bool nss_wifi_ext_vdev_unregister_if(uint32_t if_num);
+
+/**
+ * nss_wifi_ext_vdev_tx_buf
+ *      Sends data buffers to NSS firmware asynchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] os_buf   Pointer to the OS buffer (e.g. skbuff).
+ * @param[in] if_num   Wi-Fi extended virtual interface number.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+extern nss_tx_status_t nss_wifi_ext_vdev_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf,
+		uint32_t if_num);
+
+/**
+ * nss_wifi_ext_vdev_tx_msg
+ *	Sends Wi-Fi extended virtual interface messages.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_wifi_ext_vdev_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] wevm      Pointer to the message data.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+extern nss_tx_status_t nss_wifi_ext_vdev_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_wifi_ext_vdev_msg *wevm);
+
+/**
+ * nss_wifi_ext_vdev_tx_msg_sync
+ *	Sends messages to NSS firmware synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_wifi_ext_vdev_msg
+ *
+ * @param[in] nss_ctx   NSS core context.
+ * @param[in] nwevm     Pointer to Wi-Fi extended virtual interface message data.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+extern nss_tx_status_t nss_wifi_ext_vdev_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_wifi_ext_vdev_msg *nwevm);
+
+/**
+ * nss_wifi_ext_vdev_set_next_hop
+ *	Sets the extended virtual interface next hop.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ *
+ * @param[in] ctx      NSS core context.
+ * @param[in] if_num   NSS interface number.
+ * @param[in] next_hop Next hop interface number.
+ */
+extern nss_tx_status_t nss_wifi_ext_vdev_set_next_hop(struct nss_ctx_instance *ctx, int if_num, int next_hop);
+
+/**
+ * nss_wifi_ext_vdev_get_ctx
+ *	Gets the NSS Wi-Fi extended virtual interface context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_wifi_ext_vdev_get_ctx(void);
+
+/**
+ * nss_wifi_ext_vdev_register_if
+ *      Registers Wi-Fi extended virtual interface with NSS.
+ *
+ * @datatypes
+ * net_device \n
+ * nss_wifi_ext_vdev_data_callback_t \n
+ * nss_wifi_ext_vdev_ext_data_callback_t \n
+ * nss_wifi_ext_vdev_msg_callback_t
+ *
+ * @param[in] if_num         NSS interface number.
+ * @param[in] cb_func_data   Callback for the data.
+ * @param[in] cb_func_ext    Callback for the message.
+ * @param[in] cb_func_msg    Callback for the event message.
+ * @param[in] features       Data socket buffer types supported by this interface.
+ * @param[in] netdev         Pointer to the associated network device.
+ * @param[in] app_ctx        Pointer to the application context.
+ *
+ * @return
+ * NSS interface number allocated.
+ */
+extern struct nss_ctx_instance *nss_wifi_ext_vdev_register_if(uint32_t if_num,
+		nss_wifi_ext_vdev_data_callback_t cb_func_data, nss_wifi_ext_vdev_ext_data_callback_t cb_func_ext,
+		nss_wifi_ext_vdev_msg_callback_t cb_func_msg, struct net_device *netdev, uint32_t features,
+		void *app_ctx);
+/**
+ * @}
+ */
+
+#endif
diff --git a/qca-nss-drv/exports/nss_wifi_if.h b/qca-nss-drv/exports/nss_wifi_if.h
new file mode 100644
index 0000000..3ef2b13
--- /dev/null
+++ b/qca-nss-drv/exports/nss_wifi_if.h
@@ -0,0 +1,292 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_wifi_if.h
+ *	NSS Wi-Fi interface message Structure and APIs.
+ */
+
+#ifndef __NSS_WIFI_IF_H
+#define __NSS_WIFI_IF_H
+
+/**
+ * @addtogroup nss_wifi_subsystem
+ * @{
+ */
+
+/**
+ * nss_wifi_if_msg_types
+ *	Message types for Wi-Fi interface requests and responses.
+ */
+enum nss_wifi_if_msg_types {
+	NSS_WIFI_IF_OPEN = NSS_IF_OPEN,
+	NSS_WIFI_IF_CLOSE = NSS_IF_CLOSE,
+	NSS_WIFI_IF_LINK_STATE_NOTIFY = NSS_IF_LINK_STATE_NOTIFY,
+	NSS_WIFI_IF_MTU_CHANGE = NSS_IF_MTU_CHANGE,
+	NSS_WIFI_IF_MAC_ADDR_SET = NSS_IF_MAC_ADDR_SET,
+	NSS_WIFI_IF_STATS_SYNC = NSS_IF_STATS,
+	NSS_WIFI_IF_ISHAPER_ASSIGN = NSS_IF_ISHAPER_ASSIGN,
+	NSS_WIFI_IF_BSHAPER_ASSIGN = NSS_IF_BSHAPER_ASSIGN,
+	NSS_WIFI_IF_ISHAPER_UNASSIGN = NSS_IF_ISHAPER_UNASSIGN,
+	NSS_WIFI_IF_BSHAPER_UNASSIGN = NSS_IF_BSHAPER_UNASSIGN,
+	NSS_WIFI_IF_ISHAPER_CONFIG = NSS_IF_ISHAPER_CONFIG,
+	NSS_WIFI_IF_BSHAPER_CONFIG = NSS_IF_BSHAPER_CONFIG,
+	NSS_WIFI_IF_VSI_ASSIGN = NSS_IF_VSI_ASSIGN,
+	NSS_WIFI_IF_VSI_UNASSIGN = NSS_IF_VSI_UNASSIGN,
+	NSS_WIFI_IF_TX_CREATE_MSG = NSS_IF_MAX_MSG_TYPES + 1,
+	NSS_WIFI_IF_TX_DESTROY_MSG,
+	NSS_WIFI_IF_STATS_SYNC_MSG,
+	NSS_WIFI_IF_MAX_MSG_TYPES
+};
+
+/**
+ * nss_wifi_if_error_types
+ *	Error types for the Wi-Fi interface.
+ */
+enum nss_wifi_if_error_types {
+	NSS_WIFI_IF_SUCCESS,
+	NSS_WIFI_IF_CORE_FAILURE,
+	NSS_WIFI_IF_ALLOC_FAILURE,
+	NSS_WIFI_IF_DYNAMIC_IF_FAILURE,
+	NSS_WIFI_IF_MSG_TX_FAILURE,
+	NSS_WIFI_IF_REG_FAILURE,
+	NSS_WIFI_IF_CORE_NOT_INITIALIZED
+};
+
+/**
+ * nss_wifi_if_create_msg
+ *	Payload for configuring the Wi-Fi interface.
+ */
+struct nss_wifi_if_create_msg {
+	uint32_t flags;				/**< Interface flags. */
+	uint8_t mac_addr[ETH_ALEN];		/**< MAC address. */
+};
+
+/**
+ * nss_wifi_if_destroy_msg
+ *	Payload for destroying the Wi-Fi interface.
+ */
+struct nss_wifi_if_destroy_msg {
+	int32_t reserved;			/**< Placeholder. */
+};
+
+/**
+ * nss_wifi_if_stats
+ *	Wi-Fi interface statistics received from the NSS.
+ */
+struct nss_wifi_if_stats {
+	struct nss_cmn_node_stats node_stats;
+				/**< Common statistics. */
+	uint32_t tx_enqueue_failed;
+				/**< Number of packets dropped when queuing to the next node in a network graph. */
+	uint32_t shaper_enqueue_failed;
+				/**< Number of packets dropped when queuing to the shaper node. */
+};
+
+/**
+ * nss_wifi_if_msg
+ *	Data for sending and receiving Wi-Fi interface messages.
+ */
+struct nss_wifi_if_msg {
+	struct nss_cmn_msg cm;			/**< Common message header. */
+
+	/**
+	 * Payload of a Wi-Fi interface message.
+	 */
+	union {
+		union nss_if_msgs if_msgs;
+				/**< NSS interface messages. */
+		struct nss_wifi_if_create_msg create;
+				/**< Creates a Wi-Fi interface rule. */
+		struct nss_wifi_if_destroy_msg destroy;
+				/**< Destroys a Wi-Fi interface rule. */
+		struct nss_wifi_if_stats stats;
+				/**< Interface statistics. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * nss_wifi_if_pvt
+ *	Private data information for the Wi-Fi interface.
+ */
+struct nss_wifi_if_pvt {
+	struct semaphore sem;
+			/**< Semaphore for a specified Wi-Fi interface number. */
+	struct completion complete;
+			/**< Waits for the NSS to process a message on the specified Wi-Fi interface. */
+	int response;	/**< Response received on a Wi-Fi interface number. */
+	int sem_init_done;
+			/**< Indicates whether the semaphore is initialized. */
+};
+
+/**
+ * Callback function for receiving Wi-Fi data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_wifi_if_data_callback_t)(struct net_device *netdev,
+		struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for receiving Wi-Fi messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_wifi_if_msg_callback_t)(void *app_data,
+		struct nss_cmn_msg *msg);
+
+/**
+ * nss_wifi_if_handle
+ *	Context for WLAN-to-NSS communication.
+ */
+struct nss_wifi_if_handle {
+	struct nss_ctx_instance *nss_ctx;	/**< NSS context. */
+	int32_t if_num;				/**< Interface number. */
+	struct nss_wifi_if_pvt *pvt;		/**< Private data structure. */
+	struct nss_wifi_if_stats stats;
+			/**< Statistics corresponding to this handle. */
+	nss_wifi_if_msg_callback_t cb;
+			/**< Callback registered by other modules. */
+	void *app_data;
+			/**< Application context to be passed to that callback. */
+};
+
+/**
+ * nss_wifi_if_tx_msg
+ *	Sends a message to the Wi-Fi interface.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_wifi_if_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context (provided during registration).
+ * @param[in] nwim     Pointer to the Wi-Fi interface message.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_wifi_if_tx_msg(struct nss_ctx_instance *nss_ctx,
+					struct nss_wifi_if_msg *nwim);
+
+/**
+ * nss_wifi_if_register
+ *	Registers a Wi-Fi interface with the NSS driver.
+ *
+ * @datatypes
+ * nss_wifi_if_handle \n
+ * nss_wifi_if_data_callback_t \n
+ * net_device
+ *
+ * @param[in] handle       Pointer to the Wi-Fi context (provided during Wi-Fi
+ *                             interface allocation).
+ * @param[in] rx_callback  Callback handler for Wi-Fi data packets.
+ * @param[in] netdev       Pointer to the associated network device.
+ *
+ * @return
+ * None.
+ */
+extern void nss_wifi_if_register(struct nss_wifi_if_handle *handle,
+				nss_wifi_if_data_callback_t rx_callback,
+				struct net_device *netdev);
+
+/**
+ * nss_wifi_if_unregister
+ *	Deregisters a Wi-Fi interface from the NSS driver.
+ *
+ * @datatypes
+ * nss_wifi_if_handle
+ *
+ * @param[in] handle  Pointer to the Wi-Fi context.
+ *
+ * @return
+ * None.
+ */
+extern void nss_wifi_if_unregister(struct nss_wifi_if_handle *handle);
+
+/**
+ * nss_wifi_if_create_sync
+ *	Creates a Wi-Fi interface.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ *
+ * @return
+ * Pointer to the Wi-Fi handle.
+ */
+extern struct nss_wifi_if_handle *nss_wifi_if_create_sync(struct net_device *netdev);
+
+/**
+ * nss_wifi_if_destroy_sync
+ *	Destroys the Wi-Fi interface associated with the interface number.
+ *
+ * @datatypes
+ * nss_wifi_if_handle
+ *
+ * @param[in] handle  Pointer to the Wi-Fi handle.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_wifi_if_destroy_sync(struct nss_wifi_if_handle *handle);
+
+/**
+ * nss_wifi_if_tx_buf
+ *	Sends a data packet or buffer to the NSS.
+ *
+ * @datatypes
+ * nss_wifi_if_handle \n
+ * sk_buff
+ *
+ * @param[in] handle  Context associated with the interface.
+ * @param[in] skb     Pointer to the data socket buffer.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+extern nss_tx_status_t nss_wifi_if_tx_buf(struct nss_wifi_if_handle *handle,
+					struct sk_buff *skb);
+
+/**
+ * nss_wifi_if_copy_stats
+ *	Copies Wi-Fi interface statistics for display.
+ *
+ * @param[in]  if_num  NSS interface number.
+ * @param[in]  index   Index in the statistics array.
+ * @param[out] line    Pointer to the buffer into which the statistics are copied.
+ *
+ * @return
+ * Number of bytes copied.
+ */
+int32_t nss_wifi_if_copy_stats(int32_t if_num, int index, char *line);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_WIFI_IF_H */
diff --git a/qca-nss-drv/exports/nss_wifi_mac_db_if.h b/qca-nss-drv/exports/nss_wifi_mac_db_if.h
new file mode 100644
index 0000000..dff9797
--- /dev/null
+++ b/qca-nss-drv/exports/nss_wifi_mac_db_if.h
@@ -0,0 +1,288 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+ /**
+  * @file nss_wifi_mac_db_if.h
+  *	NSS-to-HLOS interface definitions.
+  */
+#ifndef __NSS_WIFI_MAC_DB_H
+#define __NSS_WIFI_MAC_DB_H
+
+#define NSS_WIFI_MAC_DB_ENTRY_IF_LOCAL 0x1
+
+ /**
+ * @addtogroup nss_wifi_mac_db_if_subsystem
+ * @{
+ */
+
+/*
+ * MAX Wi-Fi MAC database entries sent in group
+ * is chosen considering the entry size and
+ * maximum entries a smallest buffer could accomodate.
+ */
+#define NSS_WIFI_MAC_DB_GROUP_ENTRIES_MAX 48
+
+/**
+ * nss_wifi_mac_db_msg_types
+ *	Wi-Fi MAC database messages.
+ */
+enum nss_wifi_mac_db_msg_types {
+	NSS_WIFI_MAC_DB_INIT_MSG,		/**< Wi-Fi MAC database initialization message. */
+	NSS_WIFI_MAC_DB_ADD_ENTRY_MSG,		/**< Wi-Fi MAC database add entry message. */
+	NSS_WIFI_MAC_DB_DEL_ENTRY_MSG,		/**< Wi-Fi MAC database delete entry message. */
+	NSS_WIFI_MAC_DB_UPDATE_ENTRY_MSG,	/**< Wi-Fi MAC database update entry message. */
+	NSS_WIFI_MAC_DB_DEINIT_MSG,		/**< Wi-Fi MAC database deinitialization message. */
+	NSS_WIFI_MAC_DB_GROUP_ENTRIES_ADD_MSG,	/**< Wi-Fi MAC database group entries add message. */
+	NSS_WIFI_MAC_DB_ENTRY_ACTIVITY_MSG,	/**< Wi-Fi MAC database entry activity message. */
+	NSS_WIFI_MAC_DB_CREATE_ENTRY_MSG,	/**< Wi-Fi MAC database entry create message. */
+	NSS_WIFI_MAC_DB_MAX_MSG
+};
+
+/**
+ * nss_wifi_mac_db_iftype
+ * 	Wi-Fi MAC database interface type.
+ */
+enum nss_wifi_mac_db_iftype {
+	NSS_WIFI_MAC_DB_ENTRY_IFTYPE_NONE,
+	NSS_WIFI_MAC_DB_ENTRY_IFTYPE_VAP,	/**< Wi-Fi MAC database VAP entry interface. */
+	NSS_WIFI_MAC_DB_ENTRY_IFTYPE_NON_VAP,	/**< Wi-Fi MAC database non-VAP entry interface. */
+	NSS_WIFI_MAC_DB_ENTRY_IFTYPE_MAX	/**< Wi-Fi MAC database maximum interface. */
+};
+
+/**
+ * nss_wifi_mac_db_if_opmode
+ * 	Wi-Fi MAC database interface operation mode.
+ */
+enum nss_wifi_mac_db_if_opmode {
+	NSS_WIFI_MAC_DB_ENTRY_IF_OPMODE_NONE,	/**< No entry database interface operation mode. */
+	NSS_WIFI_MAC_DB_ENTRY_IF_OPMODE_ETH,	/**< Ethernet entry database interface operation mode. */
+	NSS_WIFI_MAC_DB_ENTRY_IF_OPMODE_WIFI_AP,	/**< Wi-Fi AP entry database interface operation mode. */
+	NSS_WIFI_MAC_DB_ENTRY_IF_OPMODE_WIFI_STA,	/**< Wi-Fi station entry database interface operation mode. */
+	NSS_WIFI_MAC_DB_ENTRY_IF_OPMODE_MAX	/**< Maximum entry database interface operation mode. */
+};
+
+/**
+ * nss_wifi_mac_db_err_types
+ * Wi-Fi MAC database errors.
+ */
+enum nss_wifi_mac_db_err_types {
+	NSS_WIFI_MAC_DB_ERROR_NONE,
+		/**< Wi-Fi MAC database error none. */
+	NSS_WIFI_MAC_DB_ERROR_ENTRY_ALLOC_FAIL,
+		/**< Error used to report a Wi-Fi MAC database entry pool allocation failure. */
+	NSS_WIFI_MAC_DB_ERROR_MAC_EXISTS,
+		/**< Error used to report that a Wi-Fi MAC database entry already exists. */
+	NSS_WIFI_MAC_DB_ERROR_MAC_TABLE_FULL,
+		/**< Error used to report that a Wi-Fi MAC table is full. */
+	NSS_WIFI_MAC_DB_ERROR_MAC_ENTRY_ALLOC_FAILED,
+		/**< Error used to report a Wi-Fi MAC database entry allocation failure. */
+	NSS_WIFI_MAC_DB_ERROR_ENTRY_NOT_FOUND,
+		/**< Error used to report that a Wi-Fi MAC database entry is not present. */
+	NSS_WIFI_MAC_DB_ERROR_MAC_ENTRY_UNHASHED,
+		/**< Error used to report that a Wi-Fi MAC database entry is unhashed. */
+	NSS_WIFI_MAC_DB_ERROR_MAC_ENTRY_DELETE_FAILED,
+		/**< Error used to report a Wi-Fi MAC database entry delete failure. */
+	NSS_WIFI_MAC_DB_ERROR_INVALID_NUM_ENTRIES_FAIL,
+		/**< Error used to report the number of invalid Wi-Fi MAC database entries. */
+	NSS_WIFI_MAC_DB_ERROR_NOT_ALLOCATED_FAIL,
+		/**< Error used to report that a Wi-Fi MAC database is not allocated. */
+	NSS_WIFI_MAC_DB_ERROR_INV_IF_RECVD_FAIL,
+		/**< Error used to report that a Wi-Fi MAC database entry interface is invalid. */
+	NSS_WIFI_MAC_DB_ERROR_INVALID_EVENT,
+		/**< Error used to report that a Wi-Fi MAC database event is invalid. */
+	NSS_WIFI_MAC_DB_ERROR_PN_INVALID,
+		/**< Error used to report that a Wi-Fi MAC database entry pnode is invalid. */
+	NSS_WIFI_MAC_DB_ERROR_PHY_PN_INVALID,
+		/**< Error used to report that a Wi-Fi MAC database entry radio pnode is invalid. */
+	NSS_WIFI_MAC_DB_ERROR_ENTRY_POOL_INVALID,
+		/**< Error used to report that a Wi-Fi MAC database entry pool is invalid. */
+	NSS_WIFI_MAC_DB_ERROR_ENTRY_POOL_ALREADY_ALLOCATED,
+		/**< Error used to report that a Wi-Fi MAC database entry pool exists. */
+	NSS_WIFI_MAC_DB_ERROR_GROUP_ENTRY_ADD_FAIL,
+		/**< Error used to report that a Wi-Fi MAC database group entry add failure. */
+	NSS_WIFI_MAC_DB_ERROR_MAX,
+		/**< Wi-Fi MAC database error maximum. */
+};
+
+/**
+ * nss_wifi_mac_db_entry_create_msg
+ * 	Wi-Fi MAC database entry create message.
+ */
+struct nss_wifi_mac_db_entry_create_msg {
+	uint8_t mac_addr[ETH_ALEN];			/**< MAC address. */
+	uint16_t reserved;				/**< Reserved bytes. */
+	int32_t nss_if;					/**< NSS interface number. */
+};
+
+/**
+ * nss_wifi_mac_db_entry_activity_info
+ * 	Wi-Fi MAC database entry activity information.
+ */
+struct nss_wifi_mac_db_entry_activity_info {
+	uint8_t mac_addr[ETH_ALEN];			/**< MAC address. */
+	uint16_t reserved;				/**< Reserved bytes. */
+	int32_t nss_if;					/**< NSS interface number. */
+};
+
+/**
+ * nss_wifi_mac_db_entry_activity_info_msg
+ * 	Wi-Fi MAC database entry activity information message.
+ */
+struct nss_wifi_mac_db_entry_activity_info_msg {
+	uint32_t nentries;		/**< Number of entries. */
+	struct nss_wifi_mac_db_entry_activity_info info[1];
+					/**< Wi-Fi MAC database entry activity information. */
+};
+
+/**
+ * nss_wifi_mac_db_entry_info_msg
+ *	Wi-Fi MAC database entry information.
+ */
+struct nss_wifi_mac_db_entry_info_msg {
+	uint8_t mac_addr[ETH_ALEN];	/**< MAC address. */
+	uint16_t flag;			/**< Flag information about NSS interface. */
+	int32_t nss_if;		    	/**< NSS interface number. */
+	uint32_t iftype;		/**< NSS interface type. */
+	uint32_t opmode;		/**< NSS interface operation mode. */
+	uint32_t wiphy_ifnum;		/**< NSS interface for wireless physical device. */
+};
+
+/**
+ * nss_wifi_mac_db_entry_group_info_msg
+ *	Wi-Fi MAC database group of entries information.
+ */
+struct nss_wifi_mac_db_entry_group_info_msg {
+	uint32_t num_entries;
+		/**< Number of entries in group information message. */
+	struct nss_wifi_mac_db_entry_info_msg entry[NSS_WIFI_MAC_DB_GROUP_ENTRIES_MAX];
+		/**< Wi-Fi MAC database information specific message. */
+};
+
+/**
+ * nss_wifi_mac_db_msg
+ *	Structure that describes Wi-Fi MAC database messages.
+ */
+struct nss_wifi_mac_db_msg {
+	struct nss_cmn_msg cm;                  /**< Common message header. */
+
+	/**
+	 * Payload of Wi-Fi MAC database message.
+	 */
+	union {
+		struct nss_wifi_mac_db_entry_info_msg nmfdbeimsg;
+				/**< Wi-Fi MAC database information specific message. */
+		struct nss_wifi_mac_db_entry_group_info_msg nmfdbegimsg;
+				/**< Wi-Fi MAC database information specific message. */
+		struct nss_wifi_mac_db_entry_activity_info_msg nmfdbeact_imsg;
+				/**< Wi-Fi MAC database entry activity information message. */
+		struct nss_wifi_mac_db_entry_create_msg nmfdbecmsg;
+				/**< Wi-Fi MAC database entry create message. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * nss_wifi_mac_db_msg_callback_t
+ *	Callback to receive Wi-Fi MAC database messages.
+ *
+ * @datatypes
+ * nss_wifi_mac_db_msg
+ *
+ * @param[in] app_data Application context of the message.
+ * @param[in] msg      Message data.
+ *
+ * @return
+ * void
+ */
+typedef void (*nss_wifi_mac_db_msg_callback_t)(void *app_data, struct nss_wifi_mac_db_msg *msg);
+
+/**
+ * nss_wifi_mac_db_callback_t
+ *	Callback to receive Wi-Fi MAC database messages.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ *
+ * @return
+ * void
+ */
+typedef void (*nss_wifi_mac_db_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+
+/**
+ * nss_wifi_mac_db_tx_msg
+ *	Send Wi-Fi MAC database messages.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_wifi_mac_db_msg
+ *
+ * @param[in] nss_ctx NSS context.
+ * @param[in] msg     NSS Wi-Fi MAC database message.
+ *
+ * @return
+ * nss_tx_status_t Tx status
+ */
+extern nss_tx_status_t nss_wifi_mac_db_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_wifi_mac_db_msg *msg);
+
+/**
+ * nss_register_wifi_mac_db_if
+ *	Register to send/receive Wi-Fi MAC database messages to NSS.
+ *
+ * @datatypes
+ * nss_wifi_mac_db_callback_t \n
+ * nss_wifi_mac_db_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num             NSS interface number.
+ * @param[in] mfdb_callback      Callback for the Wi-Fi MAC database device data.
+ * @param[in] mfdb_ext_callback  Callback for the extended data.
+ * @param[in] event_callback     Callback for the message.
+ * @param[in] netdev             Pointer to the associated network device.
+ * @param[in] features           Data socket buffer types supported by this
+ *                               interface.
+ *
+ * @return
+ * nss_ctx_instance* NSS context
+ */
+struct nss_ctx_instance *nss_register_wifi_mac_db_if(uint32_t if_num, nss_wifi_mac_db_callback_t wifi_mac_db_callback,
+			nss_wifi_mac_db_callback_t wifi_mac_db_ext_callback, nss_wifi_mac_db_msg_callback_t event_callback, struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_unregister_wifi_mac_db_if
+ *	Deregister Wi-Fi MAC database SoC interface with NSS.
+ *
+ * @param[in] if_num NSS interface number.
+ *
+ * @return
+ * void
+ */
+void nss_unregister_wifi_mac_db_if(uint32_t if_num);
+struct nss_ctx_instance *nss_wifi_mac_db_get_context(void);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_WIFI_MAC_DB_H */
diff --git a/qca-nss-drv/exports/nss_wifi_mesh.h b/qca-nss-drv/exports/nss_wifi_mesh.h
new file mode 100644
index 0000000..1b49304
--- /dev/null
+++ b/qca-nss-drv/exports/nss_wifi_mesh.h
@@ -0,0 +1,1005 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_wifi_mesh.h
+ *	NSS TO HLOS Wi-Fi mesh device interface definitions.
+ */
+
+#ifndef __NSS_WIFI_MESH_H
+#define __NSS_WIFI_MESH_H
+
+/**
+ * @addtogroup nss_wifi_mesh_subsystem
+ * @{
+ */
+#define NSS_WIFI_MESH_WIFI_HDRLEN_MAX 48
+/*
+ * Wi-Fi mesh maximum dynamic interface.
+ */
+#define NSS_WIFI_MESH_MAX_DYNAMIC_INTERFACE 32
+
+/**
+ * Mesh path update flags.
+ */
+#define NSS_WIFI_MESH_PATH_UPDATE_FLAG_NEXTHOP 0x01
+#define NSS_WIFI_MESH_PATH_UPDATE_FLAG_HOPCOUNT 0x02
+#define NSS_WIFI_MESH_PATH_UPDATE_FLAG_METRIC 0x04
+#define NSS_WIFI_MESH_PATH_UPDATE_FLAG_MESH_FLAGS 0x08
+#define NSS_WIFI_MESH_PATH_UPDATE_FLAG_EXPIRY_TIME 0x10
+#define NSS_WIFI_MESH_PATH_UPDATE_FLAG_MESH_GATE 0x20
+#define NSS_WIFI_MESH_PATH_UPDATE_FLAG_BLOCK_MESH_FWD 0x40
+#define NSS_WIFI_MESH_PATH_UPDATE_FLAG_METADATA_ENABLE_VALID 0x80
+
+/**
+ * Mesh proxy path update flags.
+ */
+#define NSS_WIFI_MESH_PROXY_PATH_UPDATE_FLAG_MDA 0x1
+#define NSS_WIFI_MESH_PROXY_PATH_UPDATE_FLAG_MESH 0x2
+
+/**
+ * Mesh path update flags.
+ */
+#define NSS_WIFI_MESH_PATH_FLAG_REFRESH_SENT 0x1
+
+/**
+ * Mesh path maximum entries.
+ */
+#define NSS_WIFI_MESH_PATH_MAX_ENTRIES 10
+
+/**
+ * Mesh proxy path maximum entries.
+ */
+#define NSS_WIFI_MESH_PROXY_PATH_MAX_ENTRIES 10
+
+/**
+ * Mesh configuration flags.
+ */
+#define NSS_WIFI_MESH_CONFIG_FLAG_TTL_VALID 0x01
+#define NSS_WIFI_MESH_CONFIG_FLAG_MPATH_REFRESH_VALID 0x02
+#define NSS_WIFI_MESH_CONFIG_FLAG_BLOCK_MESH_FORWARDING_VALID 0x04
+#define NSS_WIFI_MESH_CONFIG_FLAG_LOCAL_MAC_VALID 0x08
+#define NSS_WIFI_MESH_CONFIG_FLAG_MPP_LEARNING_MODE_VALID 0x10
+#define NSS_WIFI_MESH_CONFIG_FLAG_SIBLING_IF_NUM_VALID 0x20
+#define NSS_WIFI_MESH_CONFIG_FLAG_BLOCK_MESH_FWD_VALID 0x40
+#define NSS_WIFI_MESH_CONFIG_FLAG_METADATA_ENABLE_VALID 0x80
+
+/**
+ * nss_wifi_mesh_path_flags
+ *	Wi-Fi mesh path flags.
+ */
+#define NSS_WIFI_MESH_PATH_FLAG_ACTIVE 0x01
+#define NSS_WIFI_MESH_PATH_FLAG_RESOLVING 0x02
+#define NSS_WIFI_MESH_PATH_FLAG_RESOLVED 0x04
+#define NSS_WIFI_MESH_PATH_FLAG_FIXED 0x08
+
+#define NSS_WIFI_MESH_ENCAP_METADATA_OFFSET_TYPE 4
+
+/*
+ * nss_wifi_mesh_pre_header_type {
+ *	Wi-Fi pre header types.
+ */
+enum nss_wifi_mesh_pre_header_type {
+	NSS_WIFI_MESH_PRE_HEADER_NONE = 0xdcb,		/**< No preheader. */
+	NSS_WIFI_MESH_PRE_HEADER_80211 = 0xabc,		/**< 802.11 preheader. */
+	NSS_WIFI_MESH_PRE_HEADER_MAX = 0xdea		/**< Max preheader. */
+};
+
+/*
+ * nss_wifi_mesh_extended_data_pkt_types
+ * 	Wi-Fi mesh extended data packet types.
+ */
+enum nss_wifi_mesh_extended_data_pkt_types {
+	WIFI_MESH_EXT_DATA_PKT_TYPE_NONE,		/**< No packet type. */
+	WIFI_MESH_EXT_DATA_PKT_TYPE_EXCEPTION		/**< Exception packet type. */
+};
+
+/*
+ * nss_wifi_mesh_ieee80211_hdr
+ *	Wi-Fi header
+ */
+struct nss_wifi_mesh_ieee80211_hdr {
+	uint16_t frame_ctl;				/* Frame control. */
+	uint16_t duration_id;				/* Duration ID. */
+	uint8_t addr1[ETH_ALEN];			/* Address 1. */
+	uint8_t addr2[ETH_ALEN];			/* Address 2. */
+	uint8_t addr3[ETH_ALEN];			/* Address 3. */
+	uint16_t seq_ctrl;				/* Sequence control. */
+	uint8_t addr4[ETH_ALEN];			/* Address 4. */
+}__packed;
+
+/*
+ * nss_wifi_mesh_ieee80211s_hdr
+ *	Wi-Fi mesh header
+ */
+struct nss_wifi_mesh_ieee80211s_hdr {
+	uint8_t flags;					/* Mesh flags. */
+	uint8_t ttl;					/* TTL. */
+	uint32_t seq_num;				/* Sequence number. */
+	uint8_t eaddr1[ETH_ALEN];			/* Mesh Address1. */
+	uint8_t eaddr2[ETH_ALEN];			/* Mesh Address2. */
+}__packed;
+
+/*
+ * nss_wifi_mesh_per_packet_metadata
+ *      Wi-Fi mesh per packet metadata structure.
+ */
+struct nss_wifi_mesh_per_packet_metadata {
+	uint16_t pkt_type;					/* Packet type of the metadata. */
+	uint8_t wifi_hdr_bytes[NSS_WIFI_MESH_WIFI_HDRLEN_MAX];	/* Wi-Fi header byte stream. */
+};
+
+/**
+ * nss_wifi_mesh_dp_type
+ *	Interface datapath types.
+ *	NSS-to-host path will be seen by ECM for rules.
+ */
+enum nss_wifi_mesh_dp_type {
+	NSS_WIFI_MESH_DP_INNER,		/**< Inner/encapsulation interface. */
+	NSS_WIFI_MESH_DP_OUTER,		/**< Outer/decapsulation interface. */
+};
+
+/**
+ * nss_wifi_mesh_msg_types
+ *	Wi-Fi mesh messages.
+ */
+enum nss_wifi_mesh_msg_types {
+	NSS_WIFI_MESH_MSG_INTERFACE_CONFIGURE = NSS_IF_MAX_MSG_TYPES + 1,	/**< Wi-Fi mesh interface configure message. */
+	NSS_WIFI_MESH_MSG_MPATH_ADD,						/**< Wi-Fi mesh path add message. */
+	NSS_WIFI_MESH_MSG_MPATH_DELETE,						/**< Wi-Fi mesh path delete message. */
+	NSS_WIFI_MESH_MSG_MPATH_UPDATE,						/**< Wi-Fi mesh path update. */
+	NSS_WIFI_MESH_MSG_PROXY_PATH_LEARN,					/**< Wi-Fi mesh proxy path learn. */
+	NSS_WIFI_MESH_MSG_PROXY_PATH_ADD,					/**< Wi-Fi mesh proxy path add. */
+	NSS_WIFI_MESH_MSG_PROXY_PATH_DELETE,					/**< Wi-Fi mesh proxy path delete. */
+	NSS_WIFI_MESH_MSG_PROXY_PATH_UPDATE,					/**< Wi-Fi mesh proxy path update. */
+	NSS_WIFI_MESH_MSG_PATH_NOT_FOUND,					/**< Wi-Fi mesh path not found message. */
+	NSS_WIFI_MESH_MSG_PATH_REFRESH,						/**< Wi-Fi mesh path refresh message. */
+	NSS_WIFI_MESH_MSG_PATH_EXPIRY,						/**< Wi-Fi mesh path expiry message. */
+	NSS_WIFI_MESH_MSG_PATH_TABLE_DUMP,					/**< Wi-Fi mesh path table dump. */
+	NSS_WIFI_MESH_MSG_PROXY_PATH_TABLE_DUMP,				/**< Wi-Fi mesh proxy path table dump. */
+	NSS_WIFI_MESH_MSG_STATS_SYNC,						/**< Wi-Fi mesh statistics sync messgae. */
+	NSS_WIFI_MESH_MSG_EXCEPTION_FLAG,					/**< Wi-Fi mesh exception Flag. */
+	NSS_WIFI_MESH_CONFIG_EXCEPTION,						/**< Wi-Fi mesh configuration exception. */
+	NSS_WIFI_MESH_MSG_MAX							/**< Wi-Fi mesh maximum message. */
+};
+
+/*
+ * nss_wifi_mesh_error_types
+ * Wi-Fi mesh error types.
+ */
+enum nss_wifi_mesh_error_types {
+	NSS_WIFI_MESH_ERROR_NONE = NSS_IF_ERROR_TYPE_MAX + 1,		/**< Wi-Fi mesh no error type. */
+	NSS_WIFI_MESH_ERROR_UNKNOWN_MSG,				/**< Wi-Fi mesh unknown message error. */
+	NSS_WIFI_MESH_ERROR_TTL_CONFIG,					/**< Wi-Fi mesh invalid ttl error. */
+	NSS_WIFI_MESH_ERROR_REFRESH_TIME_CONFIG,			/**< Wi-Fi mesh invalid refresh time. */
+	NSS_WIFI_MESH_ERROR_MPP_LEARNING_MODE_CONFIG,			/**< Wi-Fi mesh invalid mpp learning mode. */
+	NSS_WIFI_MESH_ERROR_PATH_ADD_MAX_RADIO_CNT,			/**< Wi-Fi mesh path add error due to maximum radio count. */
+	NSS_WIFI_MESH_ERROR_PATH_ADD_INVALID_INTERFACE_NUM,		/**< Wi-Fi mesh path invalid interface number. */
+	NSS_WIFI_MESH_ERROR_PATH_ADD_INTERFACE_NUM_NOT_FOUND,		/**< Wi-Fi mesh path interface number not found. */
+	NSS_WIFI_MESH_ERROR_PATH_TABLE_FULL,				/**< Wi-Fi mesh path table full error. */
+	NSS_WIFI_MESH_ERROR_PATH_ALLOC_FAIL,				/**< Wi-Fi mesh path alloc error. */
+	NSS_WIFI_MESH_ERROR_PATH_INSERT_FAIL,				/**< Wi-Fi mesh path insert fail. */
+	NSS_WIFI_MESH_ERROR_PATH_NOT_FOUND,				/**< Wi-Fi mesh path not found error. */
+	NSS_WIFI_MESH_ERROR_PATH_UNHASHED,				/**< Wi-Fi mesh proxy path unhashed error. */
+	NSS_WIFI_MESH_ERROR_PATH_DELETE_FAIL,				/**< Wi-Fi mesh proxy path delete error. */
+	NSS_WIFI_MESH_ERROR_PROXY_PATH_NOT_FOUND,			/**< Wi-Fi mesh proxy path not found error. */
+	NSS_WIFI_MESH_ERROR_PROXY_PATH_UNHASHED,			/**< Wi-Fi mesh proxy path unhashed error. */
+	NSS_WIFI_MESH_ERROR_PROXY_PATH_DELETE_FAIL,			/**< Wi-Fi mesh proxy path delete error. */
+	NSS_WIFI_MESH_ERROR_PROXY_PATH_EXISTS,				/**< Wi-Fi mesh proxy path exists error. */
+	NSS_WIFI_MESH_ERROR_PROXY_PATH_ALLOC_FAIL,			/**< Wi-Fi mesh proxy path alloc error. */
+	NSS_WIFI_MESH_ERROR_PROXY_PATH_INSERT_FAIL,			/**< Wi-Fi mesh proxy path insert error. */
+	NSS_WIFI_MESH_ERROR_PROXY_PATH_TABLE_FULL,			/**< Wi-Fi mesh proxy path table full error. */
+	NSS_WIFI_MESH_ERROR_PB_ALLOC_FAIL,				/**< Wi-Fi mesh pbuf allocation failures. */
+	NSS_WIFI_MESH_ERROR_ENQUEUE_TO_HOST_FAIL,			/**< Wi-Fi mesh enqueue to host failures. */
+	NSS_WIFI_MESH_ERROR_ENABLE_INTERFACE_FAIL,			/**< Wi-Fi mesh enabling interface failures. */
+	NSS_WIFI_MESH_ERROR_DISABLE_INTERFACE_FAIL,			/**< Wi-Fi mesh disabling interface failures. */
+	NSS_WIFI_MESH_ERROR_INVALID_EXCEPTION_NUM,			/**< Wi-Fi mesh invalid exception number. */
+	NSS_WIFI_MESH_ERROR_ONESHOT_ALREADY_ATTACHED,			/**< Wi-Fi mesh oneshot already attached error. */
+};
+
+/**
+ * nss_wifi_mesh_mpp_learning_mode
+ *	Mesh device proxy path learning types.
+ */
+enum nss_wifi_mesh_mpp_learning_mode {
+	NSS_WIFI_MESH_MPP_LEARNING_MODE_INDEPENDENT_NSS,		/**< Independent NSS learning. */
+	NSS_WIFI_MESH_MPP_LEARNING_MODE_NSS_ASSISTED_HOST,		/**< NSS assisted host learning. */
+	NSS_WIFI_MESH_MPP_LEARNING_MODE_MAX				/**< Mesh maximum learning type. */
+};
+
+/**
+ * nss_wifi_mesh_configurable_exceptions
+ *	Mesh configurable exceptions.
+ */
+enum nss_wifi_mesh_configurable_exceptions {
+	NSS_WIFI_MESH_DS_MESH_PATH_NOT_FOUND = 1,		/**< Downstream (Eth - Wi-Fi) mesh path not found exception. */
+	NSS_WIFI_MESH_US_MESH_PROXY_NOT_FOUND = 2,		/**< Upstream (Wi-Fi - Eth) mesh proxy path not found exception. */
+	NSS_WIFI_MESH_US_MESH_PATH_NOT_FOUND = 3,		/**< Upstream (Wi-Fi - Eth) mesh path not found exception. */
+	NSS_WIFI_MESH_EXCEPTION_MAX = 4
+};
+
+/*
+ * nss_wifi_mesh_encap_ext_data_pkt_type
+ *	Mesh encap extended data packet type.
+ */
+enum nss_wifi_mesh_encap_ext_data_pkt_type {
+	NSS_WIFI_MESH_ENCAP_EXT_DATA_PKT_TYPE_NONE,			/**< No packet type. */
+	NSS_WIFI_MESH_ENCAP_EXT_DATA_PKT_TYPE_MPATH_NOT_FOUND_EXC,	/**< Packet when mesh path is not found. */
+	NSS_WIFI_MESH_ENCAP_EXT_DATA_PKT_TYPE_MAX,			/**< Maximum packet type. */
+};
+
+/**
+ * nss_wifi_mesh_config_msg
+ *	Mesh device configuration.
+ */
+struct nss_wifi_mesh_config_msg {
+	uint8_t local_mac_addr[ETH_ALEN];	/**< Local MAC address. */
+	uint16_t reserved;			/**< Reserved field. */
+	uint32_t ttl;				/**< TTL for packet. */
+	uint32_t mesh_path_refresh_time;	/**< Mesh path refresh time. */
+	uint32_t config_flags;			/**< Flags indicating which fields are valid. */
+	uint32_t sibling_ifnum;			/**< Sibling interface number. */
+	uint8_t mpp_learning_mode;             /**< Mesh proxy path learning mode. */
+	uint8_t block_mesh_forwarding;		/**< If enabled, blocks packet forwarding. */
+	uint8_t reserved_2[2];			/**< Reserved bytes. */
+	uint32_t metadata_type;			/**< Indicates if metadata should be enabled when block_mesh_forwarding is true. */
+};
+
+/**
+ * nss_wifi_mesh_mpath_add_msg
+ *	Add a mesh path message for a mesh device.
+ */
+struct nss_wifi_mesh_mpath_add_msg {
+	uint8_t dest_mac_addr[ETH_ALEN];	/**< Destination MAC address. */
+	uint8_t next_hop_mac_addr[ETH_ALEN];	/**< Next hop MAC address. */
+	uint32_t metric;			/**< Metric for a mesh path. */
+	uint32_t link_vap_id;			/**< Radio ID of the mesh path. */
+	uint32_t expiry_time;			/**< Expiry time in order of ms. */
+	uint8_t hop_count;			/**< Hop count. */
+	uint8_t path_flags;			/**< Mesh path flags. */
+	uint8_t is_mesh_gate;			/**< Destination of this path is a mesh gate. */
+	uint8_t block_mesh_fwd;			/**< Block intra mesh forward. */
+	uint32_t metadata_type;			/**< Indicates if metadata should be enabled when block_mesh_forwarding is true. */
+};
+
+/**
+ * nss_wifi_mesh_mpath_delete_msg
+ *	Delete a mesh path message for a mesh device.
+ */
+struct nss_wifi_mesh_mpath_del_msg {
+	uint32_t link_vap_id;			/**< Radio ID of the mesh path. */
+	uint8_t mesh_dest_mac_addr[ETH_ALEN];	/**< Destination MAC address. */
+	uint8_t next_hop_mac_addr[ETH_ALEN];	/**< Next hop MAC address. */
+};
+
+/**
+ * nss_wifi_mesh_mpath_update_msg
+ *	Update a mesh path message for a mesh device.
+ */
+struct nss_wifi_mesh_mpath_update_msg {
+	uint8_t dest_mac_addr[ETH_ALEN];	/**< Destination MAC address. */
+	uint8_t next_hop_mac_addr[ETH_ALEN];	/**< Next hop MAC address. */
+	uint8_t old_next_hop_mac_addr[ETH_ALEN];/**< Old next hop MAC address. */
+	uint32_t metric;			/**< Metric for a mesh path. */
+	uint32_t link_vap_id;			/**< Radio ID of the mesh path. */
+	uint32_t expiry_time;			/**< Expiration time of mesh path. */
+	uint8_t hop_count;			/**< Hop count. */
+	uint8_t path_flags;			/**< Mesh path flags. */
+	uint8_t is_mesh_gate;			/**< Indicates if the mesh path is a mesh gate. */
+	uint8_t update_flags;			/**< Update flags. */
+	uint8_t block_mesh_fwd;			/**< Block intra mesh forward. */
+	uint8_t reserved[3];			/**< Reserved bytes. */
+	uint8_t metadata_type;			/**< Indicates if metadata should be enabled when block_mesh_forwarding is true. */
+};
+
+/**
+ * nss_wifi_mesh_proxy_path_learn_msg
+ *	Learn a mesh proxy path message for a mesh device.
+ */
+struct nss_wifi_mesh_proxy_path_learn_msg {
+	uint8_t mesh_dest_mac[ETH_ALEN];	/**< Mesh destination MAC address. */
+	uint8_t dest_mac_addr[ETH_ALEN];	/**< Destination MAC address. */
+	uint8_t path_flags;			/**< Mesh path flags. */
+	uint8_t is_update;			/**< Indicates if the learn is an update. */
+};
+
+/**
+ * nss_wifi_mesh_proxy_path_add_msg
+ *	Add a mesh proxy path message for a mesh device.
+ */
+struct nss_wifi_mesh_proxy_path_add_msg {
+	uint8_t mesh_dest_mac[ETH_ALEN];	/**< Mesh destination MAC address. */
+	uint8_t dest_mac_addr[ETH_ALEN];	/**< Destination MAC address. */
+	uint8_t path_flags;			/**< Mesh path flags. */
+};
+
+/**
+ * nss_wifi_mesh_proxy_path_update_msg
+ *	Update a mesh proxy path message for a mesh device.
+ */
+struct nss_wifi_mesh_proxy_path_update_msg {
+	uint8_t mesh_dest_mac[ETH_ALEN];	/**< Mesh destination MAC address. */
+	uint8_t dest_mac_addr[ETH_ALEN];	/**< Destination MAC address. */
+	uint8_t path_flags;			/**< Mesh path flags. */
+	uint8_t bitmap;				/**< Bitmap indicating valid fields in the update msg. */
+};
+
+/**
+ * nss_wifi_mesh_proxy_path_del_msg
+ *	Delete a mesh proxy path message for a mesh device.
+ */
+struct nss_wifi_mesh_proxy_path_del_msg {
+	uint8_t mesh_dest_mac_addr[ETH_ALEN];	/**< Mesh destination MAC. */
+	uint8_t dest_mac_addr[ETH_ALEN];	/**< Destination MAC address. */
+};
+
+/**
+ * nss_wifi_mesh_mpath_not_found_msg
+ *	Wi-Fi mesh path not found message.
+ */
+struct nss_wifi_mesh_mpath_not_found_msg {
+	uint8_t dest_mac_addr[ETH_ALEN];		/**< Destination MAC address. */
+	uint8_t transmitter_mac_addr[ETH_ALEN];		/**< Transmitter address. */
+	uint32_t link_vap_id;				/**< NSS interface number of the link vap if received from WiFi. */
+	uint8_t is_mesh_forward_path;			/**< Indicates if the message is from a forward path. */
+};
+
+/**
+ * nss_wifi_mesh_path_refresh_msg
+ *	Refresh mesh path message.
+ */
+struct nss_wifi_mesh_path_refresh_msg {
+	uint8_t dest_mac_addr[ETH_ALEN];		/**< Destination MAC address. */
+	uint8_t next_hop_mac_addr[ETH_ALEN];		/**< Next hop MAC address. */
+	uint32_t link_vap_id;				/**< Link VAP of the mesh path. */
+	uint8_t path_flags;				/**< Mesh path flags. */
+};
+
+/**
+ * nss_wifi_mesh_path_expiry_msg
+ *	Mesh path expiration message.
+ */
+struct nss_wifi_mesh_path_expiry_msg {
+	uint8_t mesh_dest_mac_addr[ETH_ALEN];		/**< Destination MAC address. */
+	uint8_t next_hop_mac_addr[ETH_ALEN];		/**< Next hop MAC address. */
+	uint32_t link_vap_id;				/**< Link VAP of the mesh path. */
+	uint8_t path_flags;				/**< Mesh path flags. */
+};
+
+/*
+ * nss_wifi_mesh_encap_stats
+ *	Encapsulation statistics.
+ */
+struct nss_wifi_mesh_encap_stats {
+	uint32_t expiry_notify_sent;		/* Number of times expiry notification sent to host. */
+	uint32_t mc_count;			/* Number of multicast packets. */
+	uint32_t mp_not_found;			/* Number of times mesh path is not found. */
+	uint32_t mp_active;			/* Number of times mesh path is active. */
+	uint32_t mpp_not_found;			/* Number of times proxy path is not found. */
+	uint32_t mpp_found;			/* Number of times proxy path is found. */
+	uint32_t encap_hdr_fail;		/* Number of times encapsulating mesh header failed. */
+	uint32_t mp_del_notify_fail;		/* Number of times notifying mesh path delete failed. */
+	uint32_t link_enqueue;			/* Number of packets enqueued to the link VAP. */
+	uint32_t link_enq_fail;			/* Number of times enqueue to link vap failed. */
+	uint32_t ra_lup_fail;			/* Number of times receiver address look up is failed. */
+	uint32_t dummy_add_count;		/* Number of times dummy path is added. */
+	uint32_t encap_mp_add_notify_fail;	/* Number of times add notification failed. */
+	uint32_t dummy_add_fail;		/* Number of times dummy addition failed. */
+	uint32_t dummy_lup_fail;		/* Number of times dummy lookup failed. */
+	uint32_t send_to_host_failed;		/* Number of packets failed to be sent to host. */
+	uint32_t sent_to_host;			/* Number of packets sent to host. */
+	uint32_t expiry_notify_fail; 		/* Number of times expiry notification to host failed. */
+	uint32_t no_headroom;			/* Number of packets dropped because there is no headroom. */
+	uint32_t path_refresh_sent;		/* Number of times path refresh is sent to host. */
+	uint32_t linearise_failed;		/* Number of packets dropped because pb_linearise. */
+};
+
+/*
+ * nss_wifi_mesh_decap_stats
+ *	Mesh decapsulation statistics.
+ */
+struct nss_wifi_mesh_decap_stats {
+	uint32_t path_refresh_sent;		/**< Number of times path refresh is sent to host. */
+	uint32_t reserved;			/**< Reserved field. */
+	uint32_t mc_drop;			/**< Number of MC drop counts. */
+	uint32_t ttl_0;				/**< Number of TTL0 counts. */
+	uint32_t mpp_lup_fail;			/**< Number of mpp lookup failures. */
+	uint32_t decap_hdr_fail;		/**< Number of decap HDR failures. */
+	uint32_t rx_fwd_fail;			/**< Number of receive forward failures. */
+	uint32_t rx_fwd_success;		/**< Number of receive forward success counts. */
+	uint32_t mp_fwd_lookup_fail;		/**< Number of mpath forward lookup failures. */
+	uint32_t mp_fwd_inactive;		/**< Number of mpath forward inactive. */
+	uint32_t nxt_mnode_fwd_success;		/**< Number of next mnode forward successes. */
+	uint32_t nxt_mnode_fwd_fail;		/**< Number of next mnode forward failures. */
+	uint32_t mpp_add_fail;			/**< Number of MPP add failures. */
+	uint32_t mpp_add_event2host_fail;	/**< Number of MPP add event-to-host failures. */
+	uint32_t mpp_upate_fail;		/**< Number of MPP update failures. */
+	uint32_t mpp_update_even2host_fail;	/**< Number of MPP update event-to-host failure counts. */
+	uint32_t mpp_learn2host_fail;		/**< Number of MPP learn-to-host failure counts. */
+	uint32_t block_mesh_fwd_packets;	/**< Number of packets that are blocked for intra mesh forward. */
+	uint32_t no_headroon;			/**< Number of packets dropped due to insufficient headroom.. */
+	uint32_t linearise_failed;		/**< Number of packets dropped due to linear copy failure. */
+	uint32_t mpp_learn_events_rate_limited;	/**< Number of mesh proxy path learn events dropped due to rate limiting */
+	uint32_t mp_missing_events_rate_limited;/**< Number of path missing notifications dropped due to rate limiting */
+};
+
+/**
+ * nss_wifi_mesh_path_dump_entry
+ *	Wi-Fi mesh path dump entry.
+ */
+struct nss_wifi_mesh_path_dump_entry {
+	uint8_t dest_mac_addr[ETH_ALEN];		/**< Destination MAC address. */
+	uint8_t next_hop_mac_addr[ETH_ALEN];		/**< Next hop MAC address. */
+	uint32_t metric;				/**< Mesh path metric. */
+	uint32_t expiry_time[2];			/**< Mesh path expiration time. */
+	uint8_t hop_count;				/**< Number of hop counts. */
+	uint8_t flags;					/**< Mesh path flags. */
+	uint8_t is_mesh_gate;				/**< Determines whether gateway capability is enabled. */
+	uint8_t reserved[1];				/**< Reserved field. */
+	uint32_t link_vap_id;				/**< Link interface number. */
+};
+
+/**
+ * nss_wifi_mesh_proxy_path_dump_entry
+ *	Wi-Fi mesh proxy path dump entry.
+ */
+struct nss_wifi_mesh_proxy_path_dump_entry {
+	uint8_t dest_mac_addr[ETH_ALEN];		/**< Destination MAC address. */
+	uint8_t mesh_dest_mac[ETH_ALEN];		/**< Mesh destination address. */
+	uint8_t flags;					/**< Mesh path flags. */
+	uint8_t reserved[3];				/**< Reserved field. */
+	uint32_t time_diff;				/**< Difference of current time and active time. */
+};
+
+/**
+ * nss_wifi_mesh_path_table_dump
+ *	Wi-Fi mesh path table dump.
+ */
+struct nss_wifi_mesh_path_table_dump {
+	uint32_t num_entries;									/**< Number of entries. */
+	uint32_t more_events;									/**< Determines whether more events are pending. */
+	struct nss_wifi_mesh_path_dump_entry path_entry[0];					/**< Mesh path entries. */
+};
+
+/**
+ * nss_wifi_mesh_proxy_path_table_dump
+ *	Wi-Fi mesh proxy path table dump.
+ */
+struct nss_wifi_mesh_proxy_path_table_dump {
+	uint32_t num_entries;										/**< Number of entries. */
+	uint32_t more_events;										/**< More events are pending. */
+	struct nss_wifi_mesh_proxy_path_dump_entry path_entry[0];	/**< Mesh proxy path entry. */
+};
+
+/**
+ * nss_wifi_mesh_assoc_link_vap
+ *	Associate a link VAP to mesh.
+ */
+struct nss_wifi_mesh_assoc_link_vap {
+	uint32_t link_vap_id;		/**< Link interface number. */
+};
+
+/**
+ * nss_wifi_mesh_path_stats
+ *	Wi-Fi mesh path statistics.
+ */
+struct nss_wifi_mesh_path_stats {
+	uint32_t alloc_failures;			/**< Mesh path allocation failures. */
+	uint32_t error_max_radio_count;			/**< Mesh path error maximum radio count. */
+	uint32_t invalid_interface_failures;		/**< Mesh path invalid interface number failures count. */
+	uint32_t add_success;				/**< Mesh path add success count. */
+	uint32_t table_full_errors;			/**< Mesh path table full error count. */
+	uint32_t insert_failures;			/**< Mesh path insert failure count. */
+	uint32_t not_found;				/**< Mesh path not found failure count. */
+	uint32_t delete_success;			/**< Mesh path delete success count. */
+	uint32_t update_success;			/**< Mesh path update success count. */
+	uint32_t mesh_path_expired;			/**< Mesh path expired. */
+	uint32_t mesh_path_refresh_needed;		/**< Mesh path refresh needed. */
+	uint32_t add_requests;				/**< Mesh path add request. */
+	uint32_t del_requests;				/**< Mesh path delete request. */
+	uint32_t update_requests;			/**< Mesh path update requests. */
+	uint32_t next_hop_updations;			/**< Mesh path next hop updations. */
+	uint32_t hop_count_updations;			/**< Mesh path hop count updations. */
+	uint32_t flag_updations;			/**< Mesh path mesh flag updations. */
+	uint32_t metric_updations;			/**< Mesh path metric updations. */
+	uint32_t block_mesh_fwd_updations;		/**< Mesh path block mesh forward updations. */
+	uint32_t delete_failures;			/**< Mesh path delete failures. */
+};
+
+/**
+ * nss_wifi_mesh_proxy_path_stats
+ *	Wi-Fi mesh proxy path statistics.
+ */
+struct nss_wifi_mesh_proxy_path_stats {
+	uint32_t alloc_failures;		/**< Mesh proxy path allocation failure count. */
+	uint32_t entry_exist_failures;		/**< Mesh proxy path entry already exists. */
+	uint32_t add_success;			/**< Mesh proxy path add success count. */
+	uint32_t table_full_errors;		/**< Mesh proxy path table full count. */
+	uint32_t insert_failures;		/**< Mesh proxy path insert failure count. */
+	uint32_t not_found;			/**< Mesh proxy path not found count. */
+	uint32_t unhashed_errors;		/**< Mesh proxy path unhased erorr count. */
+	uint32_t delete_failures;		/**< Mesh proxy path delete failure count. */
+	uint32_t delete_success;		/**< Mesh proxy path delete success count. */
+	uint32_t update_success;		/**< Mesh proxy path update success count. */
+	uint32_t lookup_success;		/**< Mesh proxy path lookup success count. */
+	uint32_t add_requests;			/**< Mesh proxy path addition requests. */
+	uint32_t del_requests;			/**< Mesh proxy path deletion requests. */
+	uint32_t update_requests;		/**< Mesh proxy path updation requests. */
+	uint32_t mda_updations;			/**< Mesh proxy path mda updations. */
+	uint32_t flag_updations;		/**< Mesh proxy path flags updations. */
+};
+
+/**
+ * nss_wifi_mesh_exception_stats
+ *	Wi-Fi mesh exception statistics.
+ */
+struct nss_wifi_mesh_exception_stats {
+	uint32_t packets_success;	/**< Mesh exception successful packets count. */
+	uint32_t packets_dropped;	/**< Mesh exception dropped packets count. */
+};
+
+/**
+ * nss_wifi_mesh_stats_sync_msg
+ *	Message to get mesh device statistics from NSS firmware to the host.
+ */
+struct nss_wifi_mesh_stats_sync_msg {
+	struct nss_cmn_node_stats pnode_stats;					/**< Common firmware statistics. */
+	struct nss_wifi_mesh_encap_stats mesh_encap_stats;            		/**< Encapsulation statistics. */
+	struct nss_wifi_mesh_decap_stats mesh_decap_stats;			/**< Decapsulation statistics. */
+	struct nss_wifi_mesh_path_stats mesh_path_stats;			/**< Mesh path statistics. */
+	struct nss_wifi_mesh_proxy_path_stats mesh_proxy_path_stats;		/**< Mesh proxy path statistics. */
+	struct nss_wifi_mesh_exception_stats mesh_except_stats;			/**< Mesh exception statistics. */
+};
+
+/* nss_wifi_mesh_exception_flag_msg
+ * 	Messsage to send exception packets to host.
+ */
+struct nss_wifi_mesh_exception_flag_msg {
+	uint8_t dest_mac_addr[ETH_ALEN];		/**< Destination MAC address. */
+	uint8_t exception;				/**< Exception flag bit. */
+	uint8_t reserved[2];				/**< Reserved field. */
+};
+
+/**
+ * nss_wifi_mesh_rate_limit_config
+ *	Message to configure exceptions
+ */
+struct nss_wifi_mesh_rate_limit_config {
+	uint32_t exception_num;				/**< Indicates the exception - enum wifi_mesh_configurable_exceptions. */
+	uint32_t enable;				/**< Indicates if exception is enabled. */
+	uint32_t rate_limit;				/**< Rate limit value in us. */
+};
+
+/**
+ * nss_wifi_mesh_encap_ext_pkt_metadata
+ *	Metadata to extended data callback
+ */
+struct nss_wifi_mesh_encap_ext_pkt_metadata {
+	uint16_t pkt_type;				/**< Packet type of the exception packet. */
+};
+
+/**
+ * nss_wifi_mesh_msg
+ *	Data sent and received in mesh device-specific messages.
+ */
+struct nss_wifi_mesh_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a virtual device specific message.
+	 */
+	union {
+		union nss_if_msgs if_msg;
+				/**< NSS interface base message. */
+		struct nss_wifi_mesh_config_msg mesh_config;
+				/**< Mesh device configuration. */
+		struct nss_wifi_mesh_mpath_add_msg mpath_add;
+				/**< Add a message for a mesh path addition. */
+		struct nss_wifi_mesh_mpath_del_msg mpath_del;
+				/**< Add a message for a mesh path deletion. */
+		struct nss_wifi_mesh_mpath_update_msg mpath_update;
+				/**< Add a message for a mesh path update. */
+		struct nss_wifi_mesh_proxy_path_learn_msg proxy_learn_msg;
+				/**< Add a message for a mesh proxy path learning. */
+		struct nss_wifi_mesh_proxy_path_add_msg proxy_add_msg;
+				/**< Add a message for a mesh proxy path addition. */
+		struct nss_wifi_mesh_proxy_path_update_msg proxy_update_msg;
+				/**< Add a message for a mesh proxy path update. */
+		struct nss_wifi_mesh_proxy_path_del_msg proxy_del_msg;
+				/**< Add a message for a mesh proxy path deletion. */
+		struct nss_wifi_mesh_mpath_not_found_msg mpath_not_found_msg;
+				/**< Mesh path not found message. */
+		struct nss_wifi_mesh_path_refresh_msg path_refresh_msg;
+				/**< Add a message for a mesh path refresh. */
+		struct nss_wifi_mesh_path_expiry_msg path_expiry_msg;
+				/**< Add a message for a mesh path expiration. */
+		struct nss_wifi_mesh_path_table_dump mpath_table_dump;
+				/**< Add a message to dump mesh path table. */
+		struct nss_wifi_mesh_proxy_path_table_dump proxy_path_table_dump;
+				/**< Add a message to dump mesh proxy path table. */
+		struct nss_wifi_mesh_stats_sync_msg stats_sync_msg;
+				/**< Statistics synchronization message. */
+		struct nss_wifi_mesh_exception_flag_msg exception_msg;
+				/**< Exception to host message. */
+		struct nss_wifi_mesh_rate_limit_config exc_cfg;
+				/**< Add a message to configure the rate limit for exception events. */
+	} msg;		/**< Virtual device message payload. */
+};
+
+/**
+ * nss_wifi_mesh_encap_stats_type
+ *	Wi-Fi mesh encapsulation statistics types.
+ */
+enum nss_wifi_mesh_encap_stats_type {
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_PNODE_RX_PACKETS,		/**< Wi-Fi mesh common node receive packets. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_PNODE_RX_BYTES,			/**< Wi-Fi mesh common node receive bytes. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_PNODE_TX_PACKETS,		/**< Wi-Fi mesh common node transmit packets. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_PNODE_TX_BYTES,			/**< Wi-Fi mesh common node transmit bytes. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_PNODE_RX_DROPPED,		/**< Wi-Fi mesh common node receive dropped. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_EXPIRY_NOTIFY_SENT,		/**< Wi-Fi mesh encapsulation statistics expiry notify sent. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_MC_COUNT,			/**< Wi-Fi mesh encapsulation statistics mc count. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_MP_NOT_FOUND,			/**< Wi-Fi mesh encapsulation statistics mpath not found. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_MP_ACTIVE,			/**< Wi-Fi mesh encapsulation statistics mpath active */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_MPP_NOT_FOUND,			/**< Wi-Fi mesh encapsulation statistics mpp not found. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_MPP_FOUND,			/**< Wi-Fi mesh encapsulation statistics mpp found. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_HDR_FAIL,			/**< Wi-Fi mesh encapsulation statistics header failed. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_MP_DEL_NOTIFY_FAIL,		/**< Wi-Fi mesh encapsulation statistics mpath delete notify. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_LINK_ENQUEUE,			/**< Wi-Fi mesh encapsulation statistics link enqueue. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_LINK_ENQUEUE_FAIL,		/**< Wi-Fi mesh encapsulation statistics link enqueue failed. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_RA_LOOKUP_FAIL,			/**< Wi-Fi mesh encapsulation statistics receiver lookup failed. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_DUMMY_ADD_COUNT,			/**< Wi-Fi mesh encapsulation statistics dummy add count. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_MP_ADD_NOTIFY_FAIL,		/**< Wi-Fi mesh encapsulation statistics mpath add notify failed. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_DUMMY_ADD_FAIL,			/**< Wi-Fi mesh encapsulation statistics dummy add failed. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_DUMMY_LOOKUP_FAIL,		/**< Wi-Fi mesh encapsulation statistics dummy look-up failed. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_SEND_TO_HOST_FAILED,		/**< Wi-Fi mesh encapsulation statistics when a packet fails to send to host. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_SENT_TO_HOST,			/**< Wi-Fi mesh encapsulation statistics when packet is sent to host. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_EXPIRY_NOTIFY_FAIL,		/**< Wi-Fi mesh encapsulation statistics expiry notified fail. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_NO_HEADROOM,			/**< Wi-Fi mesh encapsulation statistics no headroom. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_PATH_REFRESH_SENT,		/**< Wi-Fi mesh encapsulation statistics path refresh sent. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_LINEARISE_FAILED,		/**< Wi-Fi mesh encapsulation statistics when linearisation failed. */
+	NSS_WIFI_MESH_ENCAP_STATS_TYPE_MAX				/**< Wi-Fi mesh encapsulation statistics maximum. */
+};
+
+/**
+ * nss_wifi_mesh_decap_stats_type
+ *	Wi-Fi mesh decapsulation statistics types.
+ */
+enum nss_wifi_mesh_decap_stats_type {
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_PNODE_RX_PACKETS,		/**< Wi-Fi mesh common node receive packets. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_PNODE_RX_BYTES,			/**< Wi-Fi mesh common node receive bytes. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_PNODE_TX_PACKETS,		/**< Wi-Fi mesh common node transmit packets. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_PNODE_TX_BYTES,			/**< Wi-Fi mesh common node transmit bytes. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_PNODE_RX_DROPPED,		/**< Wi-Fi mesh common node receive dropped. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_PATH_REFRESH_SENT,		/**< Wi-Fi mesh decapsulation statistics path refresh sent. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_RESERVED,			/**< Wi-Fi mesh decapsulation statistics reserved field. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_MC_DROP,				/**< Wi-Fi mesh decapsulation statistics MAC dropped count. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_TTL0,				/**< Wi-Fi mesh decapsulation statistics ttl0. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_MPP_LOOKUP_FAIL,			/**< Wi-Fi mesh decapsulation statistics mpp lookup failed. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_HDR_FAIL,			/**< Wi-Fi mesh decapsulation statistics header failed. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_RX_FWD_FAIL,			/**< Wi-Fi mesh decapsulation statistics receive forward failed. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_RX_FWD_SUCCESS,			/**< Wi-Fi mesh decapsulation statistics receive forward successful. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_MP_FWD_LOOKUP_FAIL,		/**< Wi-Fi mesh decapsulation statistics mpath forward lookup failed. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_MP_FWD_INACTIVE,			/**< Wi-Fi mesh decapsulation statistics mpath forward inactive. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_MNODE_FWD_SUCCESS,		/**< Wi-Fi mesh decapsulation statistics mnode forward successful. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_MNODE_FWD_FAIL,			/**< Wi-Fi mesh decapsulation statistics mnode forward failed. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_MPP_ADD_FAIL,			/**< Wi-Fi mesh decapsulation statistics mpp add failed. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_MPP_ADD_EVENT_TO_HOST_FAIL,	/**< Wi-Fi mesh decapsulation statistics mpp add event to host failed. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_MPP_UPDATE_FAIL,			/**< Wi-Fi mesh decapsulation statistics mpp update failed. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_MPP_UPDATE_EVENT_TO_HOST_FAIL,	/**< Wi-Fi mesh decapsulation statistics mpp update event to host failed. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_MPP_LEARN_TO_HOST_FAIL,		/**< Wi-Fi mesh decapsulation statistics mpp learn to host failed. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_BLOCK_MESH_FWD_PACKETS,		/**< Wi-Fi mesh decapsulation statistics block mesh fwd packets. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_NO_HEADROOM,			/**< Wi-Fi mesh decapsulation statistics no headroom. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_LINEARISE_FAILED,		/**< Wi-Fi mesh decapsulation statistics linearise failed. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_MPP_LEARN_EVENT_RL_DROPPED,	/**< Wi-Fi mesh decapsulation statistics mpp learn event rl dropped. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_MP_MISSING_EVENT_RL_DROPPED,	/**< Wi-Fi mesh decapsulation statistics mp missing event rl dropped. */
+	NSS_WIFI_MESH_DECAP_STATS_TYPE_MAX				/**< Wi-Fi mesh decapsulation statistics maximum. */
+};
+
+/**
+ * nss_wifi_mesh_path_stats_type
+ *	Wi-Fi mesh path statistics types.
+ */
+enum nss_wifi_mesh_path_stats_type {
+	NSS_WIFI_MESH_PATH_STATS_TYPE_ALLOC_FAILURES,			/**< Wi-Fi mesh path statistics allocation failures. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_ERROR_MAX_RADIO_COUNT,		/**< Wi-Fi mesh path statistics maximum radio error count. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_INVALID_INTERFACE_FAILURES,	/**< Wi-Fi mesh path statistics invalid interface failures. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_ADD_SUCCESS,			/**< Wi-Fi mesh path statistics add success. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_TABLE_FULL_ERRORS,		/**< Wi-Fi mesh path statistics table full errors. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_INSERT_FAILURES,			/**< Wi-Fi mesh path statistics insertion failures. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_NOT_FOUND,			/**< Wi-Fi mesh path statistics not found. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_DELETE_SUCCESS,			/**< Wi-Fi mesh path statistics successful deletion. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_UPDATE_SUCCESS,			/**< Wi-Fi mesh path statistics successful updation. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_EXPIRED,				/**< Wi-Fi mesh path statistics expired. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_REFRESH_NEEDED,			/**< Wi-Fi mesh path statistics refresh needed. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_ADD_REQUESTS,			/**< Wi-Fi mesh path statistics add requests. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_DELETE_REQUESTS,			/**< Wi-Fi mesh path statistics delete requests. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_UPDATE_REQUESTS,			/**< Wi-Fi mesh path statistics update requests. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_NEXT_HOP_UPDATIONS,		/**< Wi-Fi mesh path statistics next hop updations. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_HOP_COUNT_UPDATIONS,		/**< Wi-Fi mesh path statistics hop count updations. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_MESH_FLAG_UPDATIONS,		/**< Wi-Fi mesh path statistics mesh flag updations. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_METRIC_UPDATIONS,			/**< Wi-Fi mesh path statistics metric updations. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_BLOCK_MESH_FWD_UPDATIONS,		/**< Wi-Fi mesh path statistics block mesh forward updations. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_MESH_PATH_DELETE_FAILURES,	/**< Wi-Fi mesh path statistics mesh path delete failures. */
+	NSS_WIFI_MESH_PATH_STATS_TYPE_MAX				/**< Wi-Fi mesh path statistics maximum. */
+};
+
+/**
+ * nss_wifi_mesh_proxy_path_stats_type
+ *	Wi-Fi mesh proxy path statistics types.
+ */
+enum nss_wifi_mesh_proxy_path_stats_type {
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_ALLOC_FAILURES,		/**< Wi-Fi mesh proxy path statistics allocation failures. */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_ENTRY_EXIST_FAILURES,	/**< Wi-Fi mesh proxy path statistics entry exist failures. */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_ADD_SUCCESS,		/**< Wi-Fi mesh proxy path statistics add success. */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_TABLE_FULL_ERRORS,		/**< Wi-Fi mesh proxy path statistics table full errors. */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_INSERT_FAILURES,		/**< Wi-Fi mesh proxy path statistics insert failures. */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_NOT_FOUND,			/**< Wi-Fi mesh proxy path statistics not found. */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_UNHASHED_ERRORS,		/**< Wi-Fi mesh proxy path statistics unhashed errors. */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_DELTE_FAILURES,		/**< Wi-Fi mesh proxy path statistics delete failures */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_DELETE_SUCCESS,		/**< Wi-Fi mesh proxy path statistics delete success. */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_UPDATE_SUCCESS,		/**< Wi-Fi mesh proxy path statistics update_success. */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_LOOKUP_SUCCESS,		/**< Wi-Fi mesh proxy path statistics lookup sccesss. */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_ADD_REQUESTS,		/**< Wi-Fi mesh proxy path statistics add requests. */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_DELETE_REQUESTS,		/**< Wi-Fi mesh proxy path statistics delete requests. */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_UPDATE_REQUESTS,		/**< Wi-Fi mesh proxy path statistics update request. */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_MDA_UPDATIONS,		/**< Wi-Fi mesh proxy path statistics mda updations. */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_FLAGS_UPDATIONS,		/**< Wi-Fi mesh proxy path statistics flags updations. */
+	NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_MAX				/**< Wi-Fi mesh proxy path statistics maximum. */
+};
+
+/**
+ * nss_wifi_mesh_exception_stats_type
+ *	Wi-Fi mesh exception statistics types.
+ */
+enum nss_wifi_mesh_exception_stats_type {
+	NSS_WIFI_MESH_EXCEPTION_STATS_TYPE_PACKETS_SUCCESS,		/**< Wi-Fi mesh exception statistics packets success. */
+	NSS_WIFI_MESH_EXCEPTION_STATS_TYPE_PACKETS_DROPPED,		/**< Wi-Fi mesh exception statistics packets dropped. */
+	NSS_WIFI_MESH_EXCEPTION_STATS_TYPE_MAX				/**< Wi-Fi mesh exception statistics maximum. */
+};
+
+/**
+ * nss_wifi_mesh_hdl_stats_sync_msg
+ * 	Message to get mesh device statistics from NSS firmware to the host.
+ */
+struct nss_wifi_mesh_hdl_stats_sync_msg {
+	uint64_t encap_stats[NSS_WIFI_MESH_ENCAP_STATS_TYPE_MAX];		/**< Encap statistics. */
+	uint64_t decap_stats[NSS_WIFI_MESH_DECAP_STATS_TYPE_MAX];		/**< Decap statistics. */
+	uint64_t path_stats[NSS_WIFI_MESH_PATH_STATS_TYPE_MAX];			/**< Path statistics. */
+	uint64_t proxy_path_stats[NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_MAX];	/**< Proxy path statistics. */
+	uint64_t except_stats[NSS_WIFI_MESH_EXCEPTION_STATS_TYPE_MAX];		/**< Exception statistics. */
+};
+
+/**
+ * nss_wifi_mesh_stats_notification
+ * 	Wi-Fi mesh statistics structure.
+ */
+struct nss_wifi_mesh_stats_notification {
+	uint32_t core_id;				/**< Core ID. */
+	nss_if_num_t if_num;				/**< Interface number. */
+	struct nss_wifi_mesh_hdl_stats_sync_msg stats;	/**< Encapsulation-decapsulation statistics. */
+};
+
+/**
+ * nss_wifi_mesh_tx_msg
+ *	Sends a Wi-Fi mesh message to the NSS interface.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_wifi_mesh_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS core context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+nss_tx_status_t nss_wifi_mesh_tx_msg(struct nss_ctx_instance *nss_ctx,
+				struct nss_wifi_mesh_msg *msg);
+
+/**
+ * nss_wifi_mesh_tx_buf
+ *	Sends a Wi-Fi mesh data packet to the NSS interface.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  Pointer to the NSS core context.
+ * @param[in] os_buf   Pointer to the OS data buffer.
+ * @param[in] if_num   NSS interface number.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+nss_tx_status_t nss_wifi_mesh_tx_buf(struct nss_ctx_instance *nss_ctx,
+				struct sk_buff *os_buf, nss_if_num_t if_num);
+
+/**
+ * Callback function for receiving Wi-Fi virtual device messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_wifi_mesh_msg_callback_t)(void *app_data,
+					struct nss_cmn_msg *msg);
+
+/**
+ * Callback function for receiving Wi-Fi virtual device data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_wifi_mesh_data_callback_t)(struct net_device *netdev,
+				struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for receiving extended data plane Wi-Fi virtual device data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ * @param[in] netdev  Pointer to the associated network device.
+ */
+typedef void (*nss_wifi_mesh_ext_data_callback_t)(struct net_device *netdev,
+				struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_wifi_mesh_msg_init
+ *	Initializes a Wi-Fi mesh device message.
+ *
+ * @datatypes
+ * nss_wifi_mesh_msg \n
+ * nss_wifi_mesh_msg_callback_t
+ *
+ * @param[in] nim       Pointer to the NSS interface message.
+ * @param[in] if_num    NSS interface number.
+ * @param[in] type      Type of message.
+ * @param[in] len       Length of message.
+ * @param[in] cb        Message callback.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+void nss_wifi_mesh_msg_init(struct nss_wifi_mesh_msg *nim, nss_if_num_t if_num, uint32_t type, uint32_t len,
+				nss_wifi_mesh_msg_callback_t cb, void *app_data);
+
+/**
+ * nss_wifi_mesh_get_context
+ *	Gets the NSS Wi-Fi extended virtual interface context.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+extern struct nss_ctx_instance *nss_wifi_mesh_get_context(void);
+
+/**
+ * nss_register_wifi_mesh_if
+ *	Registers a Wi-Fi mesh device interface with the NSS interface.
+ *
+ * @datatypes
+ * nss_if_num_t \n
+ * nss_wifi_mesh_data_callback_t \n
+ * nss_wifi_mesh_ext_data_callback_t \n
+ * nss_wifi_mesh_msg_callback_t \n
+ * net_device
+ * @param[in]     if_num                  NSS interface number.
+ * @param[in]     mesh_data_callback      Callback for the Wi-Fi virtual device data.
+ * @param[in]     mesh_ext_data_callback  Callback for the extended data.
+ * @param[in]     mesh_event_callback     Callback for the message.
+ * @param[in]	  dp_type                 Datapath type.
+ * @param[in]     netdev                  Pointer to the associated network device.
+ * @param[in]     features                Data socket buffer types supported by this
+ *                                        interface.
+ *
+ * @return
+ * NSS_CORE_STATUS_SUCCESS in case of success.
+ * NSS_CORE_STATUS_FAILURE in case of failure.
+ */
+uint32_t nss_register_wifi_mesh_if(nss_if_num_t if_num, nss_wifi_mesh_data_callback_t mesh_data_callback,
+			nss_wifi_mesh_ext_data_callback_t mesh_ext_data_callback, nss_wifi_mesh_msg_callback_t mesh_event_callback,
+			uint32_t dp_type, struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_unregister_wifi_mesh_if
+ *	Deregisters a Wi-Fi mesh device interface from the NSS interface.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ */
+void nss_unregister_wifi_mesh_if(nss_if_num_t if_num);
+
+/**
+ * nss_wifi_mesh_tx_msg_ext
+ *	Sends Wi-Fi mesh data packet along with metadata as a message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in,out] nss_ctx  Pointer to the NSS core context.
+ * @param[in]     os_buf   Pointer to the OS data buffer.
+ *
+ * @return
+ * Status of the transmit operation.
+ */
+nss_tx_status_t nss_wifi_mesh_tx_msg_ext(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf);
+
+/**
+ * nss_wifi_mesh_verify_if_num
+ *	Verifies the Wi-Fi mesh interface number.
+ *
+ * @datatypes
+ * interface number \n
+ *
+ * @param[in]  nss_if_num_t  NSS interface number.
+ *
+ * @return
+ * TRUE or FALSE.
+ */
+extern bool nss_wifi_mesh_verify_if_num(nss_if_num_t if_num);
+
+/**
+ * nss_wifi_mesh_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_wifi_mesh_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_wifi_mesh_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or non-zero on failure.
+ */
+extern int nss_wifi_mesh_stats_unregister_notifier(struct notifier_block *nb);
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_WIFI_MESH_H */
diff --git a/qca-nss-drv/exports/nss_wifi_vdev.h b/qca-nss-drv/exports/nss_wifi_vdev.h
new file mode 100644
index 0000000..1d88160
--- /dev/null
+++ b/qca-nss-drv/exports/nss_wifi_vdev.h
@@ -0,0 +1,1389 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_wifi_vdev.h
+ *	NSS-to-HLOS Wi-Fi virtual device interface definitions.
+ */
+
+#ifndef __NSS_WIFI_VDEV_H
+#define __NSS_WIFI_VDEV_H
+
+/**
+ * @addtogroup nss_wifi_vdev_subsystem
+ * @{
+ */
+#define NSS_WIFI_HTT_TRANSFER_HDRSIZE_WORD 6	/**< Size of the Host-To-Target (HTT) message transfer header. */
+#define NSS_WIFI_VDEV_PER_PACKET_METADATA_OFFSET 4
+/**< Offset of the metadata in a virtual device message. */
+#define NSS_WIFI_VDEV_DSCP_MAP_LEN 64		/**< Length of the DSCP MAP field. */
+#define NSS_WIFI_VDEV_IPV6_ADDR_LENGTH 16	/**< Size of the IPv6 address field. */
+#define NSS_WIFI_MAX_SRCS 4			/**< Maximum number of multicast sources. */
+#define NSS_WIFI_VDEV_MAX_ME_ENTRIES 32		/**< Maximum number of multicast enhancement entries. */
+
+/**
+ * nss_wifi_vdev_msg_types
+ *	Wi-Fi virtual device messages.
+ */
+enum nss_wifi_vdev_msg_types {
+	NSS_WIFI_VDEV_INTERFACE_CONFIGURE_MSG = NSS_IF_MAX_MSG_TYPES + 1,
+	NSS_WIFI_VDEV_INTERFACE_UP_MSG,
+	NSS_WIFI_VDEV_INTERFACE_DOWN_MSG,
+	NSS_WIFI_VDEV_INTERFACE_CMD_MSG,
+	NSS_WIFI_VDEV_SNOOPLIST_GRP_LIST_CREATE_MSG,
+	NSS_WIFI_VDEV_SNOOPLIST_GRP_LIST_DELETE_MSG,
+	NSS_WIFI_VDEV_SNOOPLIST_GRP_MEMBER_ADD_MSG,
+	NSS_WIFI_VDEV_SNOOPLIST_GRP_MEMBER_REMOVE_MSG,
+	NSS_WIFI_VDEV_SNOOPLIST_GRP_MEMBER_UPDATE_MSG,
+	NSS_WIFI_VDEV_SNOOPLIST_DENY_MEMBER_ADD_MSG,
+	NSS_WIFI_VDEV_SNOOPLIST_DENY_LIST_DELETE_MSG,
+	NSS_WIFI_VDEV_SNOOPLIST_DENY_LIST_DUMP_MSG,
+	NSS_WIFI_VDEV_SNOOPLIST_DUMP_MSG,
+	NSS_WIFI_VDEV_SNOOPLIST_RESET_MSG,
+	NSS_WIFI_VDEV_SPECIAL_DATA_TX_MSG,
+	NSS_WIFI_VDEV_VOW_DBG_CFG_MSG,
+	NSS_WIFI_VDEV_VOW_DBG_STATS_REQ_MSG,
+	NSS_WIFI_VDEV_DSCP_TID_MAP_MSG,
+	NSS_WIFI_VDEV_SNOOPLIST_TOGGLE_MSG,
+	NSS_WIFI_VDEV_UPDATECHDR_MSG,
+	NSS_WIFI_VDEV_ME_SYNC_MSG,
+	NSS_WIFI_VDEV_STATS_MSG,
+	NSS_WIFI_VDEV_SET_NEXT_HOP,
+	NSS_WIFI_VDEV_DSCP_TID_MAP_ID_MSG,
+	NSS_WIFI_VDEV_EXTAP_ADD_ENTRY,
+	NSS_WIFI_VDEV_EXTAP_REMOVE_ENTRY,
+	NSS_WIFI_VDEV_QWRAP_PSTA_DELETE_ENTRY,
+	NSS_WIFI_VDEV_QWRAP_PSTA_ADD_ENTRY,
+	NSS_WIFI_VDEV_QWRAP_ISOLATION_ENABLE,
+	NSS_WIFI_VDEV_SET_PEER_NEXT_HOP,
+	NSS_WIFI_VDEV_CONFIG_VLAN_ID_MSG,
+	NSS_WIFI_VDEV_CONFIG_VLAN_MODE_MSG,
+	NSS_WIFI_VDEV_INTERFACE_RECOVERY_RESET_MSG,
+	NSS_WIFI_VDEV_INTERFACE_RECOVERY_RECONF_MSG,
+	NSS_WIFI_VDEV_SET_GROUP_KEY,
+	NSS_WIFI_VDEV_HMMC_MEMBER_ADD_MSG,
+	NSS_WIFI_VDEV_HMMC_MEMBER_DEL_MSG,
+	NSS_WIFI_VDEV_MAX_MSG
+};
+
+/**
+ * nss_wifi_vdev_err_types
+ *	Error types for a Wi-Fi virtual device.
+ */
+enum nss_wifi_vdev_err_types {
+	NSS_WIFI_VDEV_ENONE,
+	NSS_WIFI_VDEV_EUNKNOWN_MSG,
+	NSS_WIFI_VDEV_EINV_VID_CONFIG,
+	NSS_WIFI_VDEV_EINV_EPID_CONFIG,
+	NSS_WIFI_VDEV_EINV_DL_CONFIG,
+	NSS_WIFI_VDEV_EINV_CMD,
+	NSS_WIFI_VDEV_EINV_ENCAP,
+	NSS_WIFI_VDEV_EINV_DECAP,
+	NSS_WIFI_VDEV_EINV_RX_NXTN,
+	NSS_WIFI_VDEV_EINV_VID_INDEX,
+	NSS_WIFI_VDEV_EINV_MC_CFG,
+	NSS_WIFI_VDEV_SNOOPTABLE_FULL,
+	NSS_WIFI_VDEV_SNOOPTABLE_ENOMEM,
+	NSS_WIFI_VDEV_SNOOPTABLE_GRP_LIST_UNAVAILABLE,
+	NSS_WIFI_VDEV_SNOOPTABLE_GRP_MEMBER_UNAVAILABLE,
+	NSS_WIFI_VDEV_SNOOPTABLE_PEER_UNAVAILABLE,
+	NSS_WIFI_VDEV_SNOOPTABLE_GRP_LIST_ENOMEM,
+	NSS_WIFI_VDEV_SNOOPTABLE_GRP_LIST_EXIST,
+	NSS_WIFI_VDEV_ME_ENOMEM,
+	NSS_WIFI_VDEV_EINV_NAWDS_CFG,
+	NSS_WIFI_VDEV_EINV_EXTAP_CFG,
+	NSS_WIFI_VDEV_EINV_VOW_DBG_CFG,
+	NSS_WIFI_VDEV_EINV_DSCP_TID_MAP,
+	NSS_WIFI_VDEV_INVALID_ETHER_TYPE,
+	NSS_WIFI_VDEV_SNOOPTABLE_GRP_MEMBER_EXIST,
+	NSS_WIFI_VDEV_ME_INVALID_NSRCS,
+	NSS_WIFI_VDEV_EINV_RADIO_ID,
+	NSS_WIFI_VDEV_RADIO_NOT_PRESENT,
+	NSS_WIFI_VDEV_CHDRUPD_FAIL,
+	NSS_WIFI_VDEV_ME_DENY_GRP_MAX_RCHD,
+	NSS_WIFI_VDEV_EINV_NEXT_HOP,
+	NSS_WIFI_VDEV_EINV_DSCP_TID_MAP_ID,
+	NSS_WIFI_VDEV_EINV_TID_VALUE,
+	NSS_WIFI_VDEV_EINV_EXTAP_TABLE,
+	NSS_WIFI_VDEV_EXTAP_ENTRY_UPDATE_FAIL,
+	NSS_WIFI_VDEV_QWRAP_PSTA_ADD_FAIL,
+	NSS_WIFI_VDEV_QWRAP_PSTA_DEL_FAIL,
+	NSS_WIFI_VDEV_QWRAP_ISOLATION_EN_FAIL,
+	NSS_WIFI_VDEV_QWRAP_ALLOC_FAIL,
+	NSS_WIFI_VDEV_PEER_NOT_FOUND_BY_MAC,
+	NSS_WIFI_VDEV_PEER_NEXT_HOP_NOT_FOUND,
+	NSS_VDEV_EUNKNOWN_NEXT_HOP,
+	NSS_WIFI_VDEV_VLAN_ID_CONFIG_FAIL,
+	NSS_WIFI_VDEV_VLAN_MODE_CONFIG_FAIL,
+	NSS_WIFI_VDEV_RECOVERY_RESET_FAIL,
+	NSS_WIFI_VDEV_RECOVERY_RECONF_FAIL,
+	NSS_WIFI_VDEV_CONFIG_GROUP_KEY_FAIL,
+	NSS_WIFI_VDEV_MULTIPASS_NOT_ENABLED,
+	NSS_WIFI_VDEV_ALLOC_VLAN_MAP_FAILED,
+	NSS_WIFI_VDEV_MTU_CHANGE_FAIL,
+	NSS_WIFI_VDEV_MAC_ADDR_CHANGE_FAIL,
+	NSS_WIFI_VDEV_PPE_PORT_CREATE_FAIL,
+	NSS_WIFI_VDEV_PPE_PORT_DESTROY_FAIL,
+	NSS_WIFI_VDEV_PPE_VSI_ASSIGN_FAIL,
+	NSS_WIFI_VDEV_PPE_VSI_UNASSIGN_FAIL,
+	NSS_WIFI_VDEV_EINV_MAX_CFG
+};
+
+/**
+ * nss_wifi_vdev_ext_data_pkt_type
+ *	Types of extended data plane packets sent from the NSS to the host.
+ */
+enum nss_wifi_vdev_ext_data_pkt_type {
+	NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_NONE = 0,
+	NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_IGMP = 1,	/**< IGMP packets. */
+	NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_MESH = 2,	/**< MESH packets. */
+	NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_INSPECT = 3,	/**< Host inspect packets. */
+	NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_TXINFO = 4,	/**< Tx completion information packets. */
+	NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_MPSTA_TX = 5,	/**< MP station Tx metadata. */
+	NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_MPSTA_RX = 6,	/**< MP station Rx metadata. */
+	NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_RX_ERR = 7,	/**< Rx error packets metadata. */
+	NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_EXTAP_TX = 8,	/**< ExtAP Tx metadata. */
+	NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_EXTAP_RX = 9,	/**< ExtAP Rx metadata. */
+	NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_WNM_TFS = 10,	/**< WNM TFS related metadata. */
+	NSS_WIFI_VDEV_EXT_TX_COMPL_PKT_TYPE = 11,	/**< Tx completion. */
+	NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_WDS_LEARN = 12,	/**< WDS source port learning command. */
+	NSS_WIFI_VDEV_EXT_DATA_PPDU_INFO = 13,		/**< PPDU metadata information. */
+	NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_MCBC_RX = 14,	/**< Multicast/broadcast packet received. */
+	NSS_WIFI_VDEV_MESH_EXT_DATA_PKT_TYPE_RX_SPL_PACKET = 15,
+							/**< Mesh link VAP special packet. */
+	NSS_WIFI_VDEV_MESH_EXT_DATA_PKT_TYPE_RX_MCAST_EXC = 16,
+							/**< Mesh link VAP multicast packet. */
+	NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_4ADDR = 17,	/**< 4 address exception to host. */
+	NSS_WIFI_VDEV_EXT_DATA_MPDU_INFO = 18,		/**< MPDU metadata information. */
+	NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_MAX
+};
+
+/**
+ * nss_wifi_vdev_cmd
+ *	Commands for the Wi-Fi virtual device.
+ */
+enum nss_wifi_vdev_cmd {
+	NSS_WIFI_VDEV_DROP_UNENC_CMD,	/**< Configuration to drop unencrypted frames on VAP. */
+	NSS_WIFI_VDEV_ENCAP_TYPE_CMD,	/**< Configuration to set encapsulation type on VAP. */
+	NSS_WIFI_VDEV_DECAP_TYPE_CMD,	/**< Configuration to set decapsulation type on VAP. */
+	NSS_WIFI_VDEV_ENABLE_ME_CMD,	/**< Configuration to set multicast enhancement on VAP. */
+	NSS_WIFI_VDEV_NAWDS_MODE_CMD,	/**< Configuration to set NAWDS mode on VAP. */
+	NSS_WIFI_VDEV_EXTAP_CONFIG_CMD,	/**< Configuration to set extended AP mode on VAP. */
+	NSS_WIFI_VDEV_CFG_BSTEER_CMD,	/**< Configuration to set bandsteering on VAP. */
+	NSS_WIFI_VDEV_VOW_DBG_MODE_CMD,	/**< Configuration to set video over wireless (VOW) debug mode on VAP. */
+	NSS_WIFI_VDEV_VOW_DBG_RST_STATS_CMD,
+					/**< Configuration to reset video over wireless (VOW) debug mode on VAP. */
+	NSS_WIFI_VDEV_CFG_DSCP_OVERRIDE_CMD,
+					/**< Configuration to set DSCP/TID value override on VAP. */
+	NSS_WIFI_VDEV_CFG_WNM_CAP_CMD,	/**< Configuration to set wireless network management (WNM) capability on VAP. */
+	NSS_WIFI_VDEV_CFG_WNM_TFS_CMD,	/**< Configuration to set WNM traffic filtering and sleep mode (TFS) capability on VAP. */
+	NSS_WIFI_VDEV_CFG_WDS_EXT_ENABLE_CMD,
+						/**< Configuration to set WDS extention capability on VAP. */
+	NSS_WIFI_VDEV_CFG_WDS_CMD,		/**< Configuration to set WDS on VAP. */
+	NSS_WIFI_VDEV_CFG_AP_BRIDGE_CMD,        /**< Configuration to enable/disable client isolation. */
+	NSS_WIFI_VDEV_SECURITY_TYPE_CMD,	/**< Configuration to set security type per VAP. */
+	NSS_WIFI_VDEV_CFG_AST_OVERRIDE_CMD,	/**< Configuration to set AST (Address Search Table) override on VAP. */
+	NSS_WIFI_VDEV_CFG_SON_CAP_CMD,		/**< Configuration to set software defined network capability on VAP. */
+	NSS_WIFI_VDEV_CFG_MULTIPASS_CMD,	/**< Configuration to enable multipass phrase capability on VAP. */
+	NSS_WIFI_VDEV_CFG_HLOS_TID_OVERRIDE_CMD,
+					/**< Configuration to enable HLOS TID override on VAP. */
+	NSS_WIFI_VDEV_ENABLE_IGMP_ME_CMD,	/**< Configuration to set IGMP multicast enhancement on VAP. */
+	NSS_WIFI_VDEV_CFG_WDS_BACKHAUL_CMD,
+					/**< Configuration to set WDS backhaul extension on VAP. */
+	NSS_WIFI_VDEV_CFG_MCBC_EXC_TO_HOST_CMD, /**< Configuration to set multicast/broadcast exception to host on VAP. */
+	NSS_WIFI_VDEV_MAX_CMD
+};
+
+/**
+ * nss_wifi_vdev_dp_type
+ *	Virtual device datapath types.
+ */
+enum nss_wifi_vdev_dp_type {
+	NSS_WIFI_VDEV_DP_ACCELERATED,		/**< Wi-Fi accelerated VAP type. */
+	NSS_WIFI_VDEV_DP_NON_ACCELERATED,	/**< Wi-Fi non-acclerated VAP type. */
+	NSS_WIFI_VDEV_DP_TYPE_MAX		/**< Wi-Fi maximum VAP type. */
+};
+
+/**
+ * nss_wifi_vdev_vlan_tagging_mode
+ *	Supported VLAN tagging modes.
+ */
+enum nss_wifi_vdev_vlan_tagging_mode {
+	NSS_WIFI_VDEV_VLAN_NONE,	/**< VLAN support disabled. */
+
+	/**
+	 * Default VLAN mode to add VLAN tag in Rx path and
+	 * remove VLAN tag only when matching with configured
+	 * VLAN tag in Tx path.
+	 */
+	NSS_WIFI_VDEV_VLAN_INGRESS_ADD_EGRESS_STRIP_ON_ID_MATCH,
+
+	/**
+	 * Port-based VLAN mode to add VLAN tag in Rx path
+	 * and remove any VLAN tag in Tx path.
+	 */
+	NSS_WIFI_VDEV_VLAN_INGRESS_ADD_EGRESS_STRIP_ALWAYS,
+	NSS_WIFI_VDEV_VLAN_MAX		/**< Wi-Fi maximum VLAN support type. */
+};
+
+enum vap_ext_mode {
+	WIFI_VDEV_EXT_MODE_MESH_LINK = 1,	/* Wi-Fi mesh VAP mode */
+	WIFI_VDEV_EXT_MODE_MAX,			/* Wi-Fi maximum VAP mode */
+};
+
+/**
+ * nss_wifi_vdev_config_msg
+ *	Virtual device configuration.
+ */
+struct nss_wifi_vdev_config_msg {
+	uint8_t mac_addr[ETH_ALEN];	/**< MAC address. */
+	uint16_t radio_ifnum;		/**< Corresponding radio interface number. */
+	uint32_t vdev_id;		/**< Virtual device ID. */
+	uint32_t epid;			/**< Endpoint ID of the copy engine. */
+	uint32_t downloadlen;		/**< Size of the header download length. */
+	uint32_t hdrcachelen;		/**< Size of the header cache. */
+	uint32_t hdrcache[NSS_WIFI_HTT_TRANSFER_HDRSIZE_WORD];
+					/**< Cached per descriptor metedata shared with NSS Firmware. */
+	uint32_t opmode;		/**< VAP operating mode: Access-Point (AP) or Station (STA). */
+	uint32_t mesh_mode_en;		/**< Mesh mode is enabled. */
+	uint8_t is_mpsta;
+					/**< Specifies whether the station is a VAP Master-Proxy (MP) station. */
+	uint8_t is_psta;
+					/**< Specifies whether the station is a proxy station. */
+	uint8_t special_vap_mode;
+					/**< Special VAP for monitoring received management packets. */
+	uint8_t smartmesh_mode_en;
+					/**< VAP is configured as a smart monitor VAP. */
+	uint8_t is_wrap;		/**< Specifies whether the VAP is a WRAP-AP. */
+	uint8_t is_nss_qwrap_en;	/**< VAP is configured for NSS firmware QWRAP logic. */
+	uint8_t tx_per_pkt_vdev_id_check;	/**< Transmit per-packet virtual device ID check. */
+	uint8_t align_pad;		/**< Reserved field. */
+	uint32_t vap_ext_mode;		/**< Different VAP extended modes. */
+};
+
+/**
+ * nss_wifi_vdev_enable_msg
+ *	Enable a message for a virtual device.
+ */
+struct nss_wifi_vdev_enable_msg {
+	uint8_t mac_addr[ETH_ALEN];	/**< MAC address. */
+	uint8_t reserved[2];		/**< Reserved for 4-byte alignment padding. */
+};
+
+/**
+ * nss_wifi_vdev_disable_msg
+ *	Disable message for a virtual device.
+ */
+struct nss_wifi_vdev_disable_msg {
+	uint32_t reserved;		/**< Placeholder for future enhancement. */
+};
+
+/**
+ * nss_wifi_vdev_recovery_msg
+ *	Recovery message for a virtual device.
+ */
+struct nss_wifi_vdev_recovery_msg {
+	uint32_t reserved;		/**< Placeholder for future enhancement. */
+};
+
+/**
+ * nss_wifi_vdev_set_next_hop_msg
+ *	Set next hop for Wi-Fi virtual device.
+ */
+struct nss_wifi_vdev_set_next_hop_msg {
+	uint32_t ifnumber;	/**< Next hop interface number. */
+};
+
+/**
+ * nss_wifi_vdev_extap_map
+ *	Wi-Fi EXTAP map for IPv4/IPv6 addresses.
+ */
+struct nss_wifi_vdev_extap_map {
+	uint16_t ip_version;			/**< IPv4 or IPv6 address. */
+	uint8_t h_dest[ETH_ALEN];		/**< MAC address of original backend. */
+	union {
+		uint8_t IPv4[4];		/**< IPv4 address of the backend. */
+		uint8_t IPv6[NSS_WIFI_VDEV_IPV6_ADDR_LENGTH];	/**< IPv6 group IP address. */
+	} u;
+};
+
+/**
+ * nss_wifi_vdev_cmd_msg
+ *	Virtual device commands.
+ */
+struct nss_wifi_vdev_cmd_msg {
+	uint32_t cmd;			/**< Command type. */
+	uint32_t value;			/**< Command value. */
+};
+
+/**
+ * nss_wifi_vdev_me_snptbl_grp_create_msg
+ *	Information for creating the snooptable group of a virtual device.
+ */
+struct nss_wifi_vdev_me_snptbl_grp_create_msg {
+	uint32_t ether_type;		/**< Ether type of the multicast group. */
+
+	/**
+	 * IP address of a multicast group.
+	 */
+	union {
+		uint32_t grpaddr_ip4;
+				/**< IPv4 address. */
+		uint8_t grpaddr_ip6[NSS_WIFI_VDEV_IPV6_ADDR_LENGTH];
+				/**< IPv6 address. */
+	} u;			/**< IP address of the multicast group. */
+
+	uint8_t grp_addr[ETH_ALEN];
+				/**< MAC address of the multicast group. */
+};
+
+/**
+ * nss_wifi_vdev_me_snptbl_grp_delete_msg
+ *	Information for deleting a snooplist group list.
+ */
+struct nss_wifi_vdev_me_snptbl_grp_delete_msg {
+	uint32_t ether_type;	/**< Ether type of the multicast group. */
+
+	/**
+	 * IP address of the multicast group.
+	 */
+	union {
+		uint32_t grpaddr_ip4;
+				/**< IPv4 address. */
+		uint8_t grpaddr_ip6[NSS_WIFI_VDEV_IPV6_ADDR_LENGTH];
+				/**< IPv6 address. */
+	} u;			/**< IP address of the multicast group. */
+
+	uint8_t grp_addr[ETH_ALEN];	/**< MAC address of the multicast group. */
+};
+
+/**
+ * struct nss_wifi_vdev_me_mbr_ra_info
+ *	Address details of receiver members.
+ */
+struct nss_wifi_vdev_me_mbr_ra_info {
+	bool dup;
+					/**< Duplicate bit to identify if next hop address is present. */
+	uint8_t ramac[ETH_ALEN];
+					/**< MAC address of receiver. */
+};
+
+/**
+ * nss_wifi_vdev_me_snptbl_grp_mbr_add_msg
+ *	Information for adding a snooplist group member.
+ */
+struct nss_wifi_vdev_me_snptbl_grp_mbr_add_msg {
+	uint32_t ether_type;	/**< Ether type of the multicast group. */
+
+	/**
+	 * IP address of the multicast group.
+	 */
+	union {
+		uint32_t grpaddr_ip4;
+				/**< IPv4 address. */
+		uint8_t grpaddr_ip6[NSS_WIFI_VDEV_IPV6_ADDR_LENGTH];
+				/**< IPv6 address. */
+	} u;			/**< IP address of the multicast group. */
+
+	uint32_t peer_id;	/**< Peer ID. */
+	uint8_t grp_addr[ETH_ALEN];
+				/**< MAC address of the multicast group. */
+	uint8_t grp_member_addr[ETH_ALEN];
+				/**< MAC address of the multicast group member. */
+	uint8_t mode;		/**< Multicast enhancement mode - mode 2 and mode 5. */
+	uint8_t nsrcs;		/**< Number of source IP addresses for selective source multicast. */
+	uint8_t src_ip_addr[NSS_WIFI_VDEV_IPV6_ADDR_LENGTH * NSS_WIFI_MAX_SRCS];
+				/**< Source IP address. */
+	struct nss_wifi_vdev_me_mbr_ra_info ra_entry;
+				/**< Receiver address entry corresponding to the member. */
+};
+
+/**
+ * nss_wifi_vdev_me_snptbl_grp_mbr_delete_msg
+ *	Information for removing a snooplist group member.
+ */
+struct nss_wifi_vdev_me_snptbl_grp_mbr_delete_msg {
+	uint32_t ether_type;		/**< Ether type of the multicast group. */
+
+	/**
+	 * IP address of the multicast group.
+	 */
+	union {
+		uint32_t grpaddr_ip4;
+				/**< IPv4 address. */
+		uint8_t grpaddr_ip6[NSS_WIFI_VDEV_IPV6_ADDR_LENGTH];
+				/**< IPv6 address. */
+	}u;			/**< IP address of the multicast group. */
+	uint8_t grp_addr[ETH_ALEN];
+				/**< MAC address of the multicast group. */
+	uint8_t grp_member_addr[ETH_ALEN];
+				/**< MAC address of the multicast group member. */
+};
+
+/**
+ * nss_wifi_vdev_me_snptbl_grp_mbr_update_msg
+ *	Information for updating a snooplist group member.
+ */
+struct nss_wifi_vdev_me_snptbl_grp_mbr_update_msg {
+	uint32_t ether_type;	/**< Ether type of the multicast group. */
+
+	/**
+	 * IP address of the multicast group.
+	 */
+	union {
+		uint32_t grpaddr_ip4;
+				/**< IPv4 address. */
+		uint8_t grpaddr_ip6[NSS_WIFI_VDEV_IPV6_ADDR_LENGTH];
+				/**< IPv6 address. */
+	}u;			/**< IP address of the multicast group. */
+
+	uint8_t grp_addr[ETH_ALEN];
+				/**< MAC address of the multicast group. */
+	uint8_t grp_member_addr[ETH_ALEN];
+				/**< MAC address of the multicast group member. */
+	uint8_t mode;		/**< Multicast enhancement mode - mode 2 and mode 5. */
+	uint8_t nsrcs;		/**< Number of source IP addresses for selective source multicast. */
+	uint8_t src_ip_addr[NSS_WIFI_VDEV_IPV6_ADDR_LENGTH * NSS_WIFI_MAX_SRCS];
+				/**< Source IP address. */
+};
+
+/**
+ * nss_wifi_vdev_me_hmmc_add_msg
+ *	Information for adding an entry into the host-managed multicast list.
+ */
+struct nss_wifi_vdev_me_hmmc_add_msg {
+	uint32_t ether_type;	/**< IPv4 or IPv6. */
+	union {
+		uint32_t ipv4_addr;
+			/**< IPv4 multicast group address. */
+		uint8_t ipv6_addr[NSS_WIFI_VDEV_IPV6_ADDR_LENGTH];
+			/**< IPv6 multicast group address. */
+	} u;	/**< Type of group addresses. */
+	uint32_t netmask;	/**< IP subnet netmask. */
+};
+
+/**
+ * nss_wifi_vdev_me_hmmc_del_msg
+ *	Information for deleting an entry from the host-managed multicast list.
+ */
+struct nss_wifi_vdev_me_hmmc_del_msg {
+	uint32_t ether_type;	/**< IPv4 or IPv6. */
+	union {
+		uint32_t ipv4_addr;
+			/**< IPv4 multicast group address. */
+		uint8_t ipv6_addr[NSS_WIFI_VDEV_IPV6_ADDR_LENGTH];
+			/**< IPv6 multicast group address. */
+	} u;	/**< Type of group addresses. */
+	uint32_t netmask;	/**< IP subnet netmask. */
+};
+
+/**
+ * nss_wifi_vdev_me_deny_ip_add_msg
+ *	Information for adding an entry into the denylist.
+ */
+struct nss_wifi_vdev_me_deny_ip_add_msg {
+	uint32_t ether_type;	/**< IPv4 or IPv6. */
+	union {
+		uint32_t ipv4_addr;
+			/**< IPv4 multicast group address. */
+		uint8_t ipv6_addr[NSS_WIFI_VDEV_IPV6_ADDR_LENGTH];
+			/**< IPv6 multicast group address. */
+	} u;	/**< Type of group addresses. */
+	uint32_t netmask;	/**< IP subnet netmask. */
+};
+
+/**
+ * nss_wifi_vdev_me_deny_ip_del_msg
+ *	Information for deleting an entry from the denylist.
+ */
+struct nss_wifi_vdev_me_deny_ip_del_msg {
+	uint32_t ether_type;	/**< IPv4 or IPv6. */
+	union {
+		uint32_t ipv4_addr;
+			/**< IPv4 multicast group address. */
+		uint8_t ipv6_addr[NSS_WIFI_VDEV_IPV6_ADDR_LENGTH];
+			/**< IPv6 multicast group address. */
+	} u;	/**< Type of group addresses. */
+	uint32_t netmask;	/**< IP subnet netmask. */
+};
+
+/**
+ * nss_wifi_vdev_me_snptbl_deny_grp_add_msg
+ *	Information for adding a snooplist member to a deny list.
+ */
+struct nss_wifi_vdev_me_snptbl_deny_grp_add_msg {
+	uint32_t grpaddr;	/**< IP address of the multicast group. */
+};
+
+/**
+ * nss_wifi_vdev_txmsg
+ *	Information for transmitting special data.
+ */
+struct nss_wifi_vdev_txmsg {
+	uint16_t peer_id;	/**< Peer ID. */
+	uint16_t tid;		/**< Traffic ID. */
+};
+
+/**
+ * nss_wifi_vdev_vow_dbg_stats
+ *	Types of VoW debug statistics.
+ */
+struct nss_wifi_vdev_vow_dbg_stats {
+	uint32_t rx_vow_dbg_counters;		/**< VoW Rx debug counter. */
+	uint32_t tx_vow_dbg_counters[8];	/**< VoW Tx debug counter. */
+};
+
+/**
+ * nss_wifi_vdev_vow_dbg_cfg_msg
+ *	Information for configuring VoW debug statistics.
+ */
+struct nss_wifi_vdev_vow_dbg_cfg_msg {
+	uint8_t vow_peer_list_idx;	/**< Index of the peer list. */
+	uint8_t tx_dbg_vow_peer_mac4;	/**< MAC address 4 for the peer. */
+	uint8_t tx_dbg_vow_peer_mac5;	/**< MAC address 5 for the peer. */
+};
+
+/**
+ * nss_wifi_vdev_dscp_tid_map
+ *	DSCP-to-TID mapping.
+ */
+struct nss_wifi_vdev_dscp_tid_map {
+	uint32_t dscp_tid_map[NSS_WIFI_VDEV_DSCP_MAP_LEN];
+		/**< Array holding the DSCP-to-TID mapping. */
+};
+
+/**
+ * nss_wifi_vdev_dscptid_map_id
+ *	DSCP-to-TID map ID.
+ */
+struct nss_wifi_vdev_dscptid_map_id {
+	uint8_t dscp_tid_map_id;
+		/**< DSCP-to-TID mapping ID to be used.  */
+};
+
+/**
+ * nss_wifi_vdev_set_peer_next_hop
+ *	Set per peer next hop.
+ */
+struct nss_wifi_vdev_set_peer_next_hop_msg {
+	uint8_t peer_mac_addr[ETH_ALEN];   /**< MAC peer address. */
+	uint16_t reserved;		   /**< Reserved. */
+	uint32_t if_num;                   /**< Next hop interface number. */
+};
+
+/**
+ * nss_wifi_vdev_qwrap_psta_msg
+ *	PSTA VAP entry map in QWRAP mode.
+ */
+struct nss_wifi_vdev_qwrap_psta_msg {
+	uint8_t oma[ETH_ALEN];	/**< Original MAC address of PSTA VAP. */
+	uint8_t vma[ETH_ALEN];	/**< Virtual MAC address of PSTA VAP. */
+	uint8_t vdev_id;	/**< ID of PSTA VAP.  */
+	uint8_t is_wired;	/**< Is the entry for wired PSTA VAP.  */
+	uint8_t reserved[2];	/**< Reserved for 4-byte alignment. */
+};
+
+/**
+ * nss_wifi_vdev_qwrap_isolation_en_msg
+ *	Qwrap isolation mode enable.
+ */
+struct nss_wifi_vdev_qwrap_isolation_en_msg {
+	uint8_t isolation_enable;	/**< QWRAP isolation mode enable.  */
+	uint8_t reserved[3];		/**< Reserved for 4-byte alignment. */
+};
+
+/**
+ * nss_wifi_vdev_igmp_per_packet_metadata
+ *	Per-packet metadata for IGMP packets.
+ */
+struct nss_wifi_vdev_igmp_per_packet_metadata {
+	uint32_t tid;		/**< TID. */
+	uint32_t tsf32;		/**< TSF value. */
+	uint8_t peer_mac_addr[ETH_ALEN];
+				/**< Peer MAC address. */
+	uint8_t reserved[2];	/**< Reserved for 4-byte alignment. */
+};
+
+/**
+ * nss_wifi_vdev_mesh_per_packet_metadata
+ *	Per-packet metadata for Mesh packets.
+ */
+struct nss_wifi_vdev_mesh_per_packet_metadata {
+	uint32_t status;	/**< Meshmode Status. */
+	uint32_t rssi;		/**< Received signal strength indication. */
+	uint32_t tsf;		/**< Tx expiry time. */
+	uint16_t tx_retries;	/**< Retry count. */
+};
+
+/**
+ * nss_wifi_vdev_vlan_config_msg
+ * 	Enable special handling on this VAP where VLAN tagging is added in Rx and removed in Tx.
+ */
+struct nss_wifi_vdev_vlan_config_msg {
+	uint16_t vlan_id;	/**< VLAN ID configured. */
+	uint8_t reserved[2];	/**< Reserved for 4-byte alignment. */
+};
+
+/**
+ * nss_wifi_vdev_vlan_enable_msg
+ *	Enable VLAN tagging mode on this VAP.
+ */
+struct nss_wifi_vdev_vlan_enable_msg {
+	uint8_t vlan_tagging_mode;	/**< Flag to enable default or port-based VLAN tagging mode. */
+	uint8_t reserved[3];		/**< Reserved for 4-byte alignment. */
+};
+
+/**
+ * nss_wifi_vdev_set_vlan_group_key
+ *	Set VLAN ID for special peer.
+ */
+struct nss_wifi_vdev_set_vlan_group_key {
+	uint16_t vlan_id;		/**< VLAN ID. */
+	uint16_t group_key;		/**< Group key. */
+};
+
+/**
+ * nss_wifi_vdev_txinfo_per_packet_metadata
+ *	Per-packet metadata for Tx completion information packets.
+ */
+struct nss_wifi_vdev_txinfo_per_packet_metadata {
+	uint32_t status;	/**< Tx completion status. */
+	uint16_t msdu_count;	/**< Count of MSDUs in the MSDU list. */
+	uint16_t num_msdu;	/**< Sequence Number of MSDU in the MSDU list. */
+	uint32_t msdu_q_time;	/**< Time spent by an MSDU in the Wi-Fi firmware. */
+	uint32_t ppdu_rate;	/**< PPDU rate in code rate. */
+	uint8_t ppdu_num_mpdus_success;
+				/**< Number of successful MPDUs. */
+	uint8_t ppdu_num_mpdus_fail;
+				/**< Number of failed MPDUs. */
+	uint16_t ppdu_num_msdus_success;
+				/**< Number of successful MSDUs. */
+	uint32_t ppdu_bytes_success;
+				/**< Number of successful bytes. */
+	uint32_t ppdu_duration;	/**< Estimated air time. */
+	uint8_t ppdu_retries;	/**< Number of times a PPDU is retried. */
+	uint8_t ppdu_is_aggregate;
+				/**< Flag to check whether a PPDU is aggregated. */
+	uint16_t start_seq_num;	/**< Starting MSDU ID for this PPDU. */
+	uint16_t version;	/**< PPDU statistics version. */
+	uint32_t ppdu_ack_timestamp;
+				/**< Timestamp (in ms) when an acknowledgement was received. */
+	uint32_t ppdu_bmap_enqueued_lo;
+				/**< Bitmap of packets enqueued to the hardware (LSB). */
+	uint32_t ppdu_bmap_enqueued_hi;
+				/**< Bitmap of packets enqueued to the hardware (MSB). */
+	uint32_t ppdu_bmap_tried_lo;
+				/**< Bitmap of packets sent over the air (LSB). */
+	uint32_t ppdu_bmap_tried_hi;
+				/**< Bitmap of packets sent over the air (MSB). */
+	uint32_t ppdu_bmap_failed_lo;
+				/**< Bitmap of packets that failed to be acknowledged (LSB). */
+	uint32_t ppdu_bmap_failed_hi;
+				/**< Bitmap of packets that failed to be acknowledged (MSB). */
+};
+
+/**
+ * nss_wifi_vdev_qwrap_tx_metadata_types
+ *	Per-packet metadata types for Qwrap Tx packets.
+ */
+enum nss_wifi_vdev_qwrap_tx_metadata_types {
+	NSS_WIFI_VDEV_QWRAP_TYPE_NONE = 0,
+	NSS_WIFI_VDEV_QWRAP_TYPE_TX = 1,
+	NSS_WIFI_VDEV_QWRAP_TYPE_RX_TO_TX = 2
+};
+
+/**
+ * nss_wifi_vdev_extap_pkt_types
+ *	Per-packet metadata types for ExtAP Tx packets.
+ */
+enum nss_wifi_vdev_extap_pkt_types {
+	NSS_WIFI_VDEV_EXTAP_PKT_TYPE_NONE = 0,
+	NSS_WIFI_VDEV_EXTAP_PKT_TYPE_TX = 1,
+	NSS_WIFI_VDEV_EXTAP_PKT_TYPE_RX_TO_TX = 2
+};
+
+/**
+ * nss_wifi_vdev_mpsta_per_packet_tx_metadata
+ *	Per-packet metadata for transmitting packets to an MP station.
+ */
+struct nss_wifi_vdev_mpsta_per_packet_tx_metadata {
+	uint16_t vdev_id;	/**< Virtual device ID. */
+	uint16_t metadata_type;	/**< Tx metadata type. */
+};
+
+/**
+ * nss_wifi_vdev_mpsta_per_packet_rx_metadata
+ *	Per-packet metadata for receiving packets from an MP station.
+ */
+struct nss_wifi_vdev_mpsta_per_packet_rx_metadata {
+	uint16_t vdev_id;	/**< Virtual device ID. */
+	uint16_t peer_id;	/**< Peer ID. */
+};
+
+/**
+ * nss_wifi_vdev_rx_err_per_packet_metadata
+ *	Per-packet metadata for error packets received.
+ */
+struct nss_wifi_vdev_rx_err_per_packet_metadata {
+	uint8_t peer_mac_addr[ETH_ALEN];
+				/**< Peer MAC address. */
+	uint8_t tid;		/**< TID. */
+	uint8_t vdev_id;	/**< Virtual device ID. */
+	uint8_t err_type;	/**< Error type. */
+	uint8_t rsvd[3];	/**< Reserved for future enhancement. */
+};
+
+/**
+ * nss_wifi_vdev_extap_per_packet_metadata
+ *	Per-packet metadata for ExtAP.
+ */
+struct nss_wifi_vdev_extap_per_packet_metadata {
+	uint16_t pkt_type;	/**< ExtAP packet type. */
+	uint8_t res[2];		/**< Reserved for 4-byte alignment. */
+};
+
+/**
+ * nss_wifi_vdev_tx_compl_metadata
+ *	Per-packet metadata for Tx completion message.
+ */
+struct nss_wifi_vdev_tx_compl_metadata {
+	uint8_t ta[ETH_ALEN];	/**< Transmitter MAC address. */
+	uint8_t ra[ETH_ALEN];	/**< Receiver MAC address. */
+	uint16_t ppdu_id;	/**< PPDU ID. */
+	uint16_t peer_id;	/**< Peer ID. */
+};
+
+/**
+ * nss_wifi_vdev_wds_info_type
+ *	Specifies the type of WDS notification information.
+ */
+enum wifi_vdev_ext_wds_info_type {
+	NSS_WIFI_VDEV_WDS_TYPE_NONE = 0,
+	NSS_WIFI_VDEV_WDS_TYPE_RX,	/**< Rx WDS entry. */
+	NSS_WIFI_VDEV_WDS_TYPE_MEC,	/**< Multicast Tx WDS entry. */
+	NSS_WIFI_VDEV_WDS_TYPE_DA	/**< Rx WDS entry for destination address. */
+};
+
+/**
+ * nss_wifi_vdev_per_packet_metadata
+ *	Payload of per-packet metadata.
+ */
+struct nss_wifi_vdev_wds_per_packet_metadata {
+	uint16_t peer_id;	/**< Peer ID. */
+	uint8_t is_sa_valid;	/**< Specifies whether source address is valid. */
+	uint8_t reserved;	/**< Reserve bytes for alignment. */
+	enum wifi_vdev_ext_wds_info_type wds_type;
+				/**< WDS message type. */
+	uint8_t addr4_valid;	/**< 802.11 4th address valid flag. */
+	uint8_t rsvd;		/**< Reserve bytes for alignment. */
+	uint16_t sa_idx;	/**< Source address index. */
+	uint16_t sa_sw_peer_id;	/**< Software/Address-Search-Table peer ID. */
+};
+
+/**
+ * nss_wifi_vdev_ppdu_mdata_dir
+ * 	Physical layer protocol data unit (PPDU) metadata direction.
+ */
+enum nss_wifi_vdev_ppdu_mdata_dir {
+	WIFI_VDEV_PPDU_MDATA_TX,	/**< PPDU metadata for transmit direction. */
+	WIFI_VDEV_PPDU_MDATA_RX		/**< PPDU metadata for receive direction. */
+};
+
+/**
+ * nss_wifi_vdev_ppdu_metadata
+ * 	PPDU metadata.
+ */
+struct nss_wifi_vdev_ppdu_metadata {
+	uint32_t dir;		/**< Data direction for metadata. */
+	uint32_t ppdu_id;	/**< PPDU ID. */
+	uint16_t peer_id;	/**< Peer ID. */
+	uint8_t first_msdu;	/**< First MSDU. */
+	uint8_t last_msdu;	/**< Last MSDU. */
+};
+
+/*
+ * nss_wifi_vdev_peer_mpdu_metadata
+ *	MPDU metadata.
+ */
+struct nss_wifi_vdev_peer_mpdu_metadata {
+	uint16_t peer_id;               /* Corresponding peer ID. */
+	uint8_t tid;                    /* TID of the flow or MPDU queue. */
+	uint8_t msdu_info;              /* First or last MSDU information. */
+	uint32_t ppdu_id;               /* PPDU ID. */
+	uint32_t tsf;                   /* Timing synchronization function. */
+	uint8_t transmit_cnt;           /* Transmission count. */
+	uint8_t status;                 /* Frame acknowledged/failed. */
+	uint16_t reserved;		/* Reserved. */
+};
+
+/**
+ * nss_wifi_vdev_addr4_data_metadata
+ *	Address 4 metadata
+ */
+struct nss_wifi_vdev_addr4_data_metadata {
+	uint16_t peer_id;		/**< Peer ID. */
+	uint8_t sa_valid;		/**< Source address is valid. */
+	uint8_t addr4_valid;		/**< Address 4 is valid. */
+};
+
+/**
+ * nss_wifi_vdev_per_packet_metadata
+ *	Wi-Fi per packet metadata content.
+ */
+struct nss_wifi_vdev_per_packet_metadata {
+	uint32_t pkt_type;	/**< Type of packet. */
+
+	/**
+	 * Metadata payload for special data receive messages.
+	 */
+	union {
+		struct nss_wifi_vdev_igmp_per_packet_metadata igmp_metadata;
+			/**< Per packet metadata structure for IGMP. */
+		struct nss_wifi_vdev_mesh_per_packet_metadata mesh_metadata;
+			/**< Per packet metadata structure for mesh mode. */
+		struct nss_wifi_vdev_txinfo_per_packet_metadata txinfo_metadata;
+			/**< Per packet metadata structure for Tx information. */
+		struct nss_wifi_vdev_mpsta_per_packet_tx_metadata mpsta_tx_metadata;
+			/**< Per packet Tx metadata structure for master-proxy station. */
+		struct nss_wifi_vdev_mpsta_per_packet_rx_metadata mpsta_rx_metadata;
+			/**< Per packet Rx metadata structure for master-proxy station. */
+		struct nss_wifi_vdev_rx_err_per_packet_metadata rx_err_metadata;
+			/**< Per packet metadata structure for Rx error. */
+		struct nss_wifi_vdev_tx_compl_metadata tx_compl_metadata;
+			/**< Per packet Tx metadata structure for Tx completion. */
+		struct nss_wifi_vdev_wds_per_packet_metadata wds_metadata;
+			/**< Per packet Tx metadata structure for wireless distribution system mode. */
+		struct nss_wifi_vdev_ppdu_metadata ppdu_metadata;
+			/**< Per packet PPDU metadata needed for per PPDU copy mode. */
+		struct nss_wifi_vdev_addr4_data_metadata addr4_metadata;
+			/**< Create metadata for the WDS extension interface. */
+		struct nss_wifi_vdev_peer_mpdu_metadata mpdu_metadata;
+			/**< Per packet Tx metadata structure for Tx capture info per MPDU. */
+	} metadata;
+			/**< Metadata payload for special data receive message. */
+};
+
+/**
+ * nss_wifi_vdev_meshmode_rx_metadata
+ *	Metadata payload for Mesh mode receive.
+ */
+struct nss_wifi_vdev_meshmode_rx_metadata {
+	uint16_t rs_ratephy_lo;	/**< PHY rate lower order bytes. */
+	uint16_t rs_ratephy_hi;	/**< PHY rate higher order bytes. */
+	uint16_t cntr_chan_freq;	/** Center channel frequency. */
+	uint16_t vdev_id;	/**< Virtual device ID. */
+	uint16_t peer_id;	/**< Peer ID. */
+	uint16_t rs_rssi;	/**< Received signal strength indication (noise floor adjusted). */
+	uint8_t rs_flags;	/**< First/last MSDU flags. */
+	uint8_t rs_channel;	/**< Operational channel. */
+	uint8_t rs_keyix;	/**< Key index. */
+	uint8_t padd;		/**< Padding to ensure alignment. */
+};
+
+/**
+ * nss_wifi_vdev_rawmode_rx_metadata
+ *	Metadata payload for Raw Mode receive.
+ */
+struct nss_wifi_vdev_rawmode_rx_metadata {
+	uint16_t vdev_id;	/**< Virtual device ID. */
+	uint16_t peer_id;	/**< Peer ID. */
+};
+
+/**
+ * nss_wifi_vdev_updchdr_msg
+ *	Information for updating a cache header.
+ */
+struct nss_wifi_vdev_updchdr_msg {
+	uint32_t hdrcache[NSS_WIFI_HTT_TRANSFER_HDRSIZE_WORD];
+				/**< Updated header cache. */
+	uint32_t vdev_id;	/**< Virtual device ID. */
+};
+
+/**
+ * nss_wifi_vdev_me_host_sync_grp_entry
+ *	Multicast enhancement host synchronization group table.
+ */
+struct nss_wifi_vdev_me_host_sync_grp_entry {
+	uint8_t group_addr[ETH_ALEN];		/**< Group address for this list. */
+	uint8_t grp_member_addr[ETH_ALEN];	/**< MAC address of the multicast group member. */
+
+	/**
+	 * Type of group addresses.
+	 */
+	union {
+		uint32_t grpaddr_ip4;
+			/**< IPv4 group address. */
+		uint8_t  grpaddr_ip6[NSS_WIFI_VDEV_IPV6_ADDR_LENGTH];
+			/**< IPv6 group address. */
+	} u;	/**< Type of group addresses. */
+
+	uint32_t src_ip_addr;
+			/**< Source IP address. */
+};
+
+/**
+ * wifi_vdev_me_host_sync_msg
+ *	Synchronization message for a multicast enhancement host group.
+ */
+struct nss_wifi_vdev_me_host_sync_msg {
+	uint16_t vdev_id;		/**< Virtual device ID. */
+	uint8_t nentries;		/**< Number of group entries carried by this message. */
+	uint8_t radio_ifnum;		/**< Interface number of the Wi-Fi radio. */
+	struct nss_wifi_vdev_me_host_sync_grp_entry grp_entry[NSS_WIFI_VDEV_MAX_ME_ENTRIES];
+					/**< Array for multicast group entries. */
+};
+
+/**
+ * nss_wifi_vdev_mcast_enhance_stats
+ *	Multicast enhancement-related statistics.
+ */
+struct nss_wifi_vdev_mcast_enhance_stats {
+
+	/**
+	 * Number of multicast packets recieved for multicast enhancement conversion.
+	 */
+	uint32_t mcast_rcvd;
+
+	/**
+	 * Number of unicast packets sent as part of multicast enhancement conversion.
+	 */
+	uint32_t mcast_ucast_converted;
+
+	/**
+	 * Number of multicast enhancement frames dropped because of a
+	 * buffer allocation failure.
+	 */
+	uint32_t mcast_alloc_fail;
+
+	/**
+	 * Number of multicast enhancement frames dropped because of a
+	 * buffer enqueue failure.
+	 */
+	uint32_t mcast_pbuf_enq_fail;
+
+	/**
+	 * Number of multicast enhancement frames dropped because of a
+	 * buffer copy failure.
+	 */
+	uint32_t mcast_pbuf_copy_fail;
+
+	/**
+	 * Number of multicast enhancement frames dropped because of a
+	 * failure in sending flow control to a peer.
+	 */
+	uint32_t mcast_peer_flow_ctrl_send_fail;
+
+	/**
+	 * Number of multicast enhancement buffer frames dropped when
+	 * destination MAC is the same as source MAC.
+	 */
+	uint32_t mcast_loopback_err;
+
+	/**
+	 * Number of multicast enhancement buffer frames dropped
+	 * because of an empty destination MAC.
+	 */
+	uint32_t mcast_dst_address_err;
+
+	/**
+	 * Number of multicast enhancement buffer frames dropped
+	 * because no member is listening on the group.
+	 */
+	uint32_t mcast_no_enhance_drop_cnt;
+
+	/**
+	 * Number of multicast bytes received for multicast enhancement.
+	 */
+	uint32_t mcast_rcvd_bytes;
+
+	/**
+	 * Number of IGMP packets received for conversion to unicast.
+	 */
+	uint32_t igmp_rcvd;
+
+	/**
+	 * Number of IGMP packets converted to unicast as a part of
+	 * VoW IGMP improvements.
+	 */
+	uint32_t igmp_ucast_converted;
+};
+
+/**
+ * nss_wifi_vdev_stats_sync_msg
+ *	Message to get virtual device statistics from NSS Firmware to Host.
+ */
+struct nss_wifi_vdev_stats_sync_msg {
+	uint32_t dropped;			/**< Number of dropped packets. */
+	uint32_t tx_enqueue_cnt;		/**< Transmit pnode enqueue count. */
+	uint32_t tx_enqueue_fail_cnt;		/**< Transmit pnode enqueue count. */
+	uint32_t tx_intra_bss_enqueue_cnt;	/**< Intra BSS enqueue count. */
+	uint32_t tx_intra_bss_enqueue_fail_cnt;
+						/**< Intra BSS enqueue fail count. */
+	uint32_t tx_intra_bss_mcast_send_cnt;
+						/**< Virual device multicast/broadcast packet count in AP mode. */
+	uint32_t tx_intra_bss_mcast_send_fail_cnt;
+						/**< Virtual device multicast/broadcast packet count in AP mode. */
+	uint32_t tx_enqueue_bytes;		/**< Transmit enqueue bytes count. */
+	uint32_t rx_enqueue_cnt;		/**< Ethernet node enqueue count. */
+	uint32_t rx_enqueue_fail_cnt;		/**< Ethernet node enqueue fail count. */
+	uint32_t rx_except_enqueue_cnt;		/**< N2H (NSS to Host) node enqueue count. */
+	uint32_t rx_except_enqueue_fail_cnt;	/**< N2H (NSS to Host) node enqueue fail count. */
+	uint32_t rx_enqueue_bytes;		/**< Receive enqueue bytes count. */
+	uint32_t rx_wds_learn_send_cnt;		/**< Virtual device WDS source port learn count. */
+	uint32_t rx_wds_learn_send_fail_cnt;	/**< Virtual device WDS source count fail. */
+	struct nss_wifi_vdev_mcast_enhance_stats wvmes;
+						/**< Multicast enhancement statistics. */
+	uint32_t num_tx_exception;		/**< Number of Tx exception to firmware. */
+	uint32_t tx_dma_map_fail;		/**< DMA map failure. */
+	uint32_t tx_desc_alloc_fail;		/**< Descriptor allocation failure. */
+	uint32_t tx_hw_ring_full;		/**< Hardware ring is full. */
+	uint32_t tx_tso_pkt;			/**< Number of TSO packets. */
+	uint32_t tx_num_seg;			/**< Number of segments in TSO packets. */
+	uint32_t tx_rcvd;			/**< Number of packets received from host. */
+	uint32_t tx_rcvd_bytes;			/**< Number of bytes received from host. */
+	uint32_t cce_classified;
+			/**< Number of packets that are classified and sent to firmware as an exception. */
+	uint32_t cce_classified_raw;
+			/**< Number of raw packets that are classified and sent to firmware as an exception. */
+	uint32_t tx_eapol_cnt;			/**< Number of EAPoL frames in transmit direction. */
+	uint32_t nawds_tx_mcast_cnt;		/**< Number of NAWDS packets sent. */
+	uint32_t nawds_tx_mcast_bytes;		/**< Number of NAWDS bytes sent. */
+	uint32_t per_pkt_vdev_check_fail;	/**< Number of packets that failed vdev id check in Tx. */
+	uint32_t rx_mcast_cnt;			/**< Receive multicast packet count. */
+	uint32_t rx_mcast_bytes;		/**< Receive multicast bytes count. */
+	uint32_t rx_decrypt_err;		/**< Receive decryption error */
+	uint32_t rx_mic_err;			/**< Receive MIC error */
+	uint32_t mcbc_exc_host_fail_cnt;
+			/**< Number of multicast/broadcast packets failed to send to host through exception path. */
+	uint32_t addr4_exc_fail;			/**< Number of failed 4 address exceptions. */
+	uint32_t addr4_exc_pass;			/**< Number of successful 4 address exceptions. */
+};
+
+/**
+ * nss_wifi_vdev_msg
+ *	Data for sending and receiving virtual device specific messages.
+ */
+struct nss_wifi_vdev_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a virtual device specific message.
+	 */
+	union {
+		struct nss_wifi_vdev_config_msg vdev_config;
+				/**< Virtual device configuration. */
+		struct nss_wifi_vdev_enable_msg vdev_enable;
+				/**< Enable a message for a virtual device. */
+		struct nss_wifi_vdev_cmd_msg vdev_cmd;
+				/**< Command message for a virtual device. */
+		struct nss_wifi_vdev_me_snptbl_grp_create_msg vdev_grp_list_create;
+				/**< Creates the snooptable group of a virtual device. */
+		struct nss_wifi_vdev_me_snptbl_grp_delete_msg vdev_grp_list_delete;
+				/**< Deletes a snooplist group list. */
+		struct nss_wifi_vdev_me_snptbl_grp_mbr_add_msg vdev_grp_member_add;
+				/**< Adds a snooplist group member. */
+		struct nss_wifi_vdev_me_snptbl_grp_mbr_delete_msg vdev_grp_member_remove;
+				/**< Removes a snooplist group member. */
+		struct nss_wifi_vdev_me_snptbl_grp_mbr_update_msg vdev_grp_member_update;
+				/**< Updates a snooplist group member. */
+		struct nss_wifi_vdev_me_snptbl_deny_grp_add_msg vdev_deny_member_add;
+				/**< Add a snooplist member to the deny list. */
+		struct nss_wifi_vdev_me_hmmc_add_msg vdev_hmmc_member_add;
+				/**< Adds a member to the HMMC list. */
+		struct nss_wifi_vdev_me_hmmc_del_msg vdev_hmmc_member_del;
+				/**< Deletes a member from the HMMC list. */
+		struct nss_wifi_vdev_me_deny_ip_add_msg vdev_deny_list_member_add;
+				/**< Adds a member to the denylist. */
+		struct nss_wifi_vdev_me_deny_ip_del_msg vdev_deny_list_member_del;
+				/**< Deletes a member from the denylist. */
+		struct nss_wifi_vdev_txmsg vdev_txmsgext;
+				/**< Transmits special data. */
+		struct nss_wifi_vdev_vow_dbg_cfg_msg vdev_vow_dbg_cfg;
+				/**< Configures VoW debug statistics. */
+		struct nss_wifi_vdev_vow_dbg_stats vdev_vow_dbg_stats;
+				/**< Types of VoW debug statistics. */
+		struct nss_wifi_vdev_dscp_tid_map vdev_dscp_tid_map;
+				/**< DSCP-to-TID mapping. */
+		struct nss_wifi_vdev_updchdr_msg vdev_updchdr;
+				/**< Updates a cache header. */
+		struct nss_wifi_vdev_me_host_sync_msg vdev_me_sync;
+				/**< Message for a multicast enhancement host group table synchronization. */
+		struct nss_wifi_vdev_stats_sync_msg vdev_stats;
+				/**< Message to get virtual device statistics from NSS firmware to host. */
+		struct nss_wifi_vdev_set_next_hop_msg next_hop;
+				/**< Next hop message for virtual device. */
+		struct nss_wifi_vdev_dscptid_map_id vdev_dscp_tid_map_id;
+				/**< Message to get DSCP-to-TID mapping id to be used on virtual device. */
+		struct nss_wifi_vdev_extap_map vdev_extap_map;
+				/**< Message to add entry in EXTAP table on virtual device. */
+		struct nss_wifi_vdev_qwrap_psta_msg vdev_qwrap_psta_map;
+				/**< Message to get PSTA VAP details in QWRAP mode. */
+		struct nss_wifi_vdev_qwrap_isolation_en_msg vdev_qwrap_isolation_en;
+				/**< Message to enable QWRAP isolation mode. */
+		struct nss_wifi_vdev_set_peer_next_hop_msg vdev_set_peer_next_hp;
+				/**< Message to set next hop per peer. */
+		struct nss_wifi_vdev_vlan_config_msg vdev_vlan_config;
+				/**< Message to set VLAN configured on a particular virtual device. */
+		struct nss_wifi_vdev_vlan_enable_msg vdev_vlan_enable;
+				/**< Message to enable VLAN tagging support on a particular virtual device. */
+		struct nss_wifi_vdev_set_vlan_group_key vlan_group_key;
+				/**< Message to set group key for peer. */
+	} msg;		/**< Virtual device message payload. */
+};
+
+/**
+ * nss_wifi_vdev_tx_msg
+ *	Sends a Wi-Fi message to the NSS interface.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_wifi_vdev_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS core context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_wifi_vdev_tx_msg(struct nss_ctx_instance *nss_ctx,
+				struct nss_wifi_vdev_msg *msg);
+
+/**
+ * nss_wifi_vdev_base_tx_msg
+ *	Sends a Wi-Fi message to the NSS VAP interface.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_wifi_vdev_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS core context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_wifi_vdev_base_tx_msg(struct nss_ctx_instance *nss_ctx,
+				struct nss_wifi_vdev_msg *msg);
+
+/**
+ * nss_wifi_vdev_tx_buf
+ *	Sends a Wi-Fi data packet to the NSS interface.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in] nss_ctx  Pointer to the NSS core context.
+ * @param[in] os_buf   Pointer to the OS data buffer.
+ * @param[in] if_num   NSS interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_wifi_vdev_tx_buf(struct nss_ctx_instance *nss_ctx,
+				struct sk_buff *os_buf, uint32_t if_num);
+
+/**
+ * Callback function for receiving Wi-Fi virtual device messages.
+ *
+ * @datatypes
+ * nss_cmn_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_wifi_vdev_msg_callback_t)(void *app_data,
+					struct nss_cmn_msg *msg);
+
+/**
+ * Callback function for receiving Wi-Fi virtual device data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ */
+typedef void (*nss_wifi_vdev_callback_t)(struct net_device *netdev,
+				struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * Callback function for receiving extended data plane Wi-Fi virtual device data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ * @param[in] netdev  Pointer to the associated network device.
+ */
+typedef void (*nss_wifi_vdev_ext_data_callback_t)(struct net_device *netdev,
+				struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_wifi_vdev_msg_init
+ *	Initializes a Wi-Fi virtual device message.
+ *
+ * @datatypes
+ * nss_wifi_vdev_msg \n
+ * nss_wifi_vdev_msg_callback_t
+ *
+ * @param[in] nim       Pointer to the NSS interface message.
+ * @param[in] if_num    NSS interface number.
+ * @param[in] type      Type of message.
+ * @param[in] len       Length of message.
+ * @param[in] cb        Message callback.
+ * @param[in] app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+void nss_wifi_vdev_msg_init(struct nss_wifi_vdev_msg *nim, uint32_t if_num, uint32_t type, uint32_t len,
+				nss_wifi_vdev_msg_callback_t *cb, void *app_data);
+
+/**
+ * nss_register_wifi_vdev_if
+ *	Registers a Wi-Fi virtual device interface with the NSS interface.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_wifi_vdev_callback_t \n
+ * nss_wifi_vdev_ext_data_callback_t \n
+ * nss_wifi_vdev_msg_callback_t \n
+ * net_device
+ *
+ * @param[in,out] nss_ctx                 Pointer to the NSS core context.
+ * @param[in]     if_num                  NSS interface number.
+ * @param[in]     wifi_data_callback      Callback for the Wi-Fi virtual device data.
+ * @param[in]     vdev_ext_data_callback  Callback for the extended data.
+ * @param[in]     wifi_event_callback     Callback for the message.
+ * @param[in]     netdev                  Pointer to the associated network device.
+ * @param[in]     features                Data socket buffer types supported by this
+ *                                        interface.
+ *
+ * @return
+ * None.
+ */
+uint32_t nss_register_wifi_vdev_if(struct nss_ctx_instance *nss_ctx, int32_t if_num, nss_wifi_vdev_callback_t wifi_data_callback,
+			nss_wifi_vdev_ext_data_callback_t vdev_ext_data_callback, nss_wifi_vdev_msg_callback_t wifi_event_callback,
+			struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_unregister_wifi_vdev_if
+ *	Deregisters a Wi-Fi virtual device interface from the NSS interface.
+ *
+ * @param[in] if_num  NSS interface number.
+ *
+ * @return
+ * None.
+ */
+void nss_unregister_wifi_vdev_if(uint32_t if_num);
+
+/**
+ * nss_wifi_vdev_tx_msg_ext
+ *	Sends Wi-Fi data packet along with metadata as message to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * sk_buff
+ *
+ * @param[in,out] nss_ctx  Pointer to the NSS core context.
+ * @param[in]     os_buf   Pointer to the OS data buffer.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_wifi_vdev_tx_msg_ext(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf);
+
+/**
+ * nss_wifi_vdev_set_next_hop
+ *	Send next hop message to Wi-Fi virtual device.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in]    nss_ctx  Pointer to the NSS core context.
+ * @param[in]    if_num   NSS interface number.
+ * @param[in]    next_hop Next hop interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_wifi_vdev_set_next_hop(struct nss_ctx_instance *nss_ctx, int if_num, int next_hop);
+
+/**
+ * nss_wifi_vdev_base_set_next_hop
+ *	Sends the next hop message to Wi-Fi virtual access point.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in]    nss_ctx  Pointer to the NSS core context.
+ * @param[in]    next_hop Next hop interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_wifi_vdev_base_set_next_hop(struct nss_ctx_instance *nss_ctx, int next_hop);
+
+/**
+ * nss_wifi_vdev_set_peer_next_hop
+ *	Sends the peer next hop message to Wi-Fi virtual device.
+ *
+ * @datatypes
+ * nss_ctx_instance
+ *
+ * @param[in]    nss_ctx      Pointer to the NSS core context.
+ * @param[in]    nss_if       NSS interface number.
+ * @param[in]    addr         Peer MAC address.
+ * @param[in]    next_hop_if  Next hop interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_wifi_vdev_set_peer_next_hop(struct nss_ctx_instance *nss_ctx, uint32_t nss_if, uint8_t *addr, uint32_t next_hop_if);
+
+/*
+ * nss_wifi_vdev_set_dp_type
+ *	Sets the datapath type for virtual device.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * net_device \n
+ * uint32_t \n
+ * enum nss_wifi_vdev_dp_type
+ *
+ * @param[in]   nss_ctx  Pointer to the NSS core context.
+ * @param[in]   netdev   Pointer to the associated network device.
+ * @param[in]   if_num   Interface number of the VAP.
+ * @param[in]   dp_type  Datapath type of the VAP.
+ *
+ * @return
+ * True if a success, or false if a failure.
+ */
+bool nss_wifi_vdev_set_dp_type(struct nss_ctx_instance *nss_ctx, struct net_device *netdev,
+						uint32_t if_num, enum nss_wifi_vdev_dp_type dp_type);
+/**
+ * @}
+ */
+
+#endif /* __NSS_WIFI_VDEV_H */
diff --git a/qca-nss-drv/exports/nss_wifili_if.h b/qca-nss-drv/exports/nss_wifili_if.h
new file mode 100644
index 0000000..d5bf3bc
--- /dev/null
+++ b/qca-nss-drv/exports/nss_wifili_if.h
@@ -0,0 +1,2089 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+ /**
+  * @file nss_wifili_if.h
+  *	NSS TO HLOS interface definitions.
+  *	NOTE: Here we will use wifili as a reference to
+  *	the IPQ807x Wi-Fi object.
+  */
+#ifndef __NSS_WIFILI_H
+#define __NSS_WIFILI_H
+
+ /**
+  * @addtogroup nss_wifili_subsystem
+  * @{
+  */
+
+#define NSS_WIFILI_MAX_SRNG_REG_GROUPS_MSG 2
+				/**< Maximum srng (ring) register groups. */
+#define NSS_WIFILI_MAX_NUMBER_OF_PAGE_MSG 32
+				/**< Maximum number of pages allocated from host. */
+#define NSS_WIFILI_MAX_TCL_DATA_RINGS_MSG 4
+				/**< Maximum number of Transmit Classifier data ring for NSS. */
+#define NSS_WIFILI_MAX_REO_DATA_RINGS_MSG 4
+				/**< Maximum number of Rx reorder data ring for NSS. */
+#define NSS_WIFILI_SOC_PER_PACKET_METADATA_OFFSET 4
+				/**< Metadata area for storing Rx statistics. */
+#define NSS_WIFILI_MAX_TXDESC_POOLS_MSG 4
+				/**< Maximum number of Tx Descriptor software pools. */
+#define NSS_WIFILI_MAX_TX_EXT_DESC_POOLS_MSG 4
+				/**< Maximum number of Tx Descriptor Extended software pools. */
+#define NSS_WIFILI_MAX_SOC_NUM 3
+				/**< Maximum number of SoC devices. */
+#define NSS_WIFILI_MAX_PDEV_NUM_MSG 3
+				/**< Maximum number of pdev devices. */
+#define NSS_WIFILI_MAX_MCS 12
+				/**< Maximum Modulaton And Coding Scheme (MCS) count. */
+#define NSS_WIFILI_MAX_MCS_11A 8
+				/**< Maximum MCS for 11a mode. */
+#define NSS_WIFILI_MAX_MCS_11B 7
+				/**< Maximum MCS for 11b mode. */
+#define NSS_WIFILI_MAX_MCS_11AC 10
+				/**< Maximum MCS for 11ac mode. */
+#define NSS_WIFILI_MAX_MCS_11AX 10
+				/**< Maximum MCS for 11ax mode. */
+#define NSS_WIFILI_SS_COUNT 8
+				/**< Maximum spatial streams count. */
+#define NSS_WIFILI_SUPPORTED_BW 4
+				/**< Maximum number of bandwidth supported. */
+#define NSS_WIFILI_REPT_MU_MIMO 1
+#define NSS_WIFILI_REPT_MU_OFDMA_MIMO 3
+#define NSS_WIFILI_MAX_RESERVED_TYPE 2
+				/**< Maximum reserved type. */
+#define NSS_WIFILI_SOC_PER_PACKET_METADATA_SIZE 60
+				/**< Metadata area total size. */
+#define NSS_WIFILI_MEC_PEER_ID 0xDEAD
+				/**< MEC (Multicast echo check) peer ID. */
+#define NSS_WIFILI_DA_PEER_ID 0xDAAD
+				/**< Destination address peer ID. */
+#define NSS_WIFILI_MIC_KEY_LEN 8
+				/**< MIC (Message integrity code) key length. */
+#define NSS_WIFILI_TQM_RR_MAX 7
+				/**< Maximum transmit queue release reasons. */
+#define NSS_WIFILI_HTT_STATUS_MAX 7
+				/**< Maximum HTT completion status. */
+#define NSS_WIFILI_TQM_STATUS_MAX 9
+				/**< Maximum TQM completion status. */
+#define NSS_WIFILI_REO_CODE_MAX 15
+				/**< Maximum Rx reorder error codes. */
+#define NSS_WIFILI_DMA_CODE_MAX 14
+				/**< Maximum DMA error codes. */
+#define NSS_WIFILI_MAX_TID 8
+				/**< Maximum TID values. */
+#define NSS_WIFILI_DELAY_INDEX_MAX 10
+				/**< Maximum software enqueue delay buckets. */
+#define NSS_WIFILI_MAX_NUMBER_OF_ADDTNL_SEG 64
+				/**< Maximum number of additional pages allocated from host. */
+#define NSS_WIFILI_SOC_ATTACHED_MAX_PDEV_NUM 1
+				/**< Maximum number of physical devices on the external SoC. */
+#define NSS_WIFILI_PEER_AST_FLOWQ_MAX 4
+				/**< Maximum number of flow queues. */
+#define NSS_WIFILI_WBM_INTERNAL_ERR_MAX 5
+				/**< WBM internal maximum errors. */
+
+/*
+ * Peer Size in Bytes
+ */
+#define NSS_WIFILI_PEER_SIZE 1600
+
+/*
+ * Radio specific flags
+ */
+#define NSS_WIFILI_PDEV_FLAG_V3_STATS_ENABLED 0x00000008
+				/**< Flag to enable version 3 statistics. */
+/**
+ * Peer message flags.
+ */
+#define NSS_WIFILI_PEER_MSG_DISABLE_4ADDR 0x01
+
+#ifdef __KERNEL__ /* only kernel will use. */
+
+/**
+ * Wireless Multimedia Extention Access Category to TID. @hideinitializer
+ */
+#define NSS_WIFILI_WME_AC_TO_TID(_ac) (	\
+		((_ac) == NSS_WIFILI_WME_AC_VO) ? 6 : \
+		(((_ac) == NSS_WIFILI_WME_AC_VI) ? 5 : \
+		(((_ac) == NSS_WIFILI_WME_AC_BK) ? 1 : \
+		0)))
+
+/**
+ * Wireless TID to Wireless Extension Multimedia Access Category. @hideinitializer
+ */
+#define NSS_WIFILI_TID_TO_WME_AC(_tid) (	\
+		(((_tid) == 0) || ((_tid) == 3)) ? NSS_WIFILI_WME_AC_BE : \
+		((((_tid) == 1) || ((_tid) == 2)) ? NSS_WIFILI_WME_AC_BK : \
+		((((_tid) == 4) || ((_tid) == 5)) ? NSS_WIFILI_WME_AC_VI : \
+		NSS_WIFILI_WME_AC_VO)))
+#endif /* __KERNEL */
+
+/**
+ * nss_wifili_thread_scheme_id
+ *	List of thread scheme IDs.
+ */
+enum nss_wifili_thread_scheme_id {
+	NSS_WIFILI_THREAD_SCHEME_ID_0,		/**< High priority scheme index. */
+	NSS_WIFILI_THREAD_SCHEME_ID_1,		/**< Low priority scheme index. */
+	NSS_WIFILI_THREAD_SCHEME_ID_2,		/**< High priority scheme index. */
+	NSS_WIFILI_THREAD_SCHEME_ID_MAX		/**< Maximum value of scheme index. */
+};
+
+/*
+ * nss_wifili_thread_scheme_priority
+ *	List of wifili thread scheme priority.
+ */
+enum nss_wifili_thread_scheme_priority {
+	NSS_WIFILI_LOW_PRIORITY_SCHEME,		/**< Low priority scheme. */
+	NSS_WIFILI_HIGH_PRIORITY_SCHEME,	/**< High priority scheme. */
+};
+
+/**
+ * nss_wifili_wme_stream_classes
+ *	WME stream classes.
+ */
+enum nss_wifili_wme_stream_classes {
+	NSS_WIFILI_WME_AC_BE,	/**< Best effort. */
+	NSS_WIFILI_WME_AC_BK,	/**< Background. */
+	NSS_WIFILI_WME_AC_VI,	/**< Video. */
+	NSS_WIFILI_WME_AC_VO,	/**< Voice. */
+	NSS_WIFILI_WME_AC_MAX	/**< Maximum AC Value. */
+};
+
+/**
+ * nss_wifili_packet_type
+ *	Different Packet Types.
+ */
+enum nss_wifili_packet_type {
+	NSS_WIFILI_DOT11_A,		/**< 802.11a packet type. */
+	NSS_WIFILI_DOT11_B,		/**< 802.11b packet type. */
+	NSS_WIFILI_DOT11_N,		/**< 802.11n packet type. */
+	NSS_WIFILI_DOT11_AC,		/**< 802.11ac packet type. */
+	NSS_WIFILI_DOT11_AX ,		/**< 802.11ax packet type. */
+	NSS_WIFILI_DOT11_MAX		/**< Maximum 802.11 packet types. */
+};
+
+/*
+ * nss_wifili_decap_pkt_type
+ *	Different Decapsulation packet types
+ */
+enum wifili_decap_pkt_type {
+	NSS_WIFILI_DECAP_TYPE_RAW,		/**< Raw packet type. */
+	NSS_WIFILI_DECAP_TYPE_NATIVE_WIFI,	/**< Native Wi-Fi packet type. */
+	NSS_WIFILI_DECAP_TYPE_ETHERNET,		/**< Ethernet packet type. */
+	NSS_WIFILI_DECAP_TYPE_MAX,		/**< Maximum packet type. */
+};
+
+/**
+ * nss_wifili_msg_types
+ *	NSS wifili messages.
+ */
+enum nss_wifili_msg_types {
+	NSS_WIFILI_INIT_MSG,
+	NSS_WIFILI_SOC_RESET_MSG,
+	NSS_WIFILI_PDEV_INIT_MSG,
+	NSS_WIFILI_PDEV_DEINIT_MSG,
+	NSS_WIFILI_START_MSG,
+	NSS_WIFILI_STOP_MSG,
+	NSS_WIFILI_PEER_CREATE_MSG,
+	NSS_WIFILI_PEER_DELETE_MSG,
+	NSS_WIFILI_SEND_PEER_MEMORY_REQUEST_MSG,
+	NSS_WIFILI_PEER_FREELIST_APPEND_MSG,
+	NSS_WIFILI_STATS_MSG,
+	NSS_WIFILI_WDS_VENDOR_MSG,
+	NSS_WIFILI_PEER_STATS_MSG,
+	NSS_WIFILI_WDS_PEER_ADD_MSG,
+	NSS_WIFILI_WDS_PEER_DEL_MSG,
+	NSS_WIFILI_WDS_PEER_MAP_MSG,
+	NSS_WIFILI_WDS_ACTIVE_INFO_MSG,
+	NSS_WIFILI_STATS_CFG_MSG,
+	NSS_WIFILI_TID_REOQ_SETUP_MSG,
+	NSS_WIFILI_RADIO_CMD_MSG,
+	NSS_WIFILI_LINK_DESC_INFO_MSG,
+	NSS_WIFILI_PEER_SECURITY_TYPE_MSG,
+	NSS_WIFILI_PEER_NAWDS_ENABLE_MSG,
+	NSS_WIFILI_RADIO_BUF_CFG,
+	NSS_WIFILI_DBDC_REPEATER_SET_MSG,
+	NSS_DBDC_REPEATER_AST_FLUSH_MSG,
+	NSS_WIFILI_SET_HMMC_DSCP_OVERRIDE_MSG,
+	NSS_WIFILI_SET_HMMC_DSCP_TID_MSG,
+	NSS_WIFILI_PDEV_STATS_V3_TXRX_SYNC_MSG,
+	NSS_WIFILI_PDEV_STATS_V3_DELAY_SYNC_MSG,
+	NSS_WIFILI_ENABLE_V3_STATS_MSG,
+	NSS_WIFILI_WDS_PEER_UPDATE_MSG,
+	NSS_WIFILI_STATS_V2_CFG_MSG,
+	NSS_WIFILI_SOJOURN_STATS_MSG,
+	NSS_WIFILI_PEER_SET_VLAN_ID,
+	NSS_WIFILI_UPDATE_PDEV_LMAC_ID_MSG,
+	NSS_WIFILI_PEER_AST_FLOWID_MAP_MSG,
+	NSS_WIFILI_PEER_MEC_AGEOUT_MSG,
+	NSS_WIFILI_JITTER_STATS_MSG,
+	NSS_WIFILI_ISOLATION_MSG,
+	NSS_WIFILI_PEER_EXT_STATS_MSG,
+	NSS_WIFILI_CLR_STATS,
+	NSS_WIFILI_PEER_4ADDR_EVENT_MSG,
+	NSS_WIFILI_DBDC_REPEATER_LOOP_DETECTION_MSG,
+	NSS_WIFILI_PEER_UPDATE_AUTH_FLAG,
+	NSS_WIFILI_SEND_MESH_CAPABILITY_INFO,
+	NSS_WIFILI_PDEV_TX_CAPTURE_MSG,
+	NSS_WIFILI_PEER_TX_CAPTURE_MSG,
+	NSS_WIFILI_MAX_MSG
+};
+
+/**
+ * nss_wifili_error_types
+ *	Wifili error message types for functions.
+ */
+enum nss_wifili_error_types {
+	NSS_WIFILI_EMSG_NONE,
+			/**< No error. */
+	NSS_WIFILI_EMSG_INIT_FAIL_IMPROPER_STATE,
+			/**< Device initialization failure due to improper state of device. */
+	NSS_WIFILI_EMSG_RINGS_INIT_FAIL,
+			/**< Device ring initialization failure. */
+	NSS_WIFILI_EMSG_PDEV_INIT_IMPROPER_STATE_FAIL,
+			/**< Radio initialization failure due to improper state of device. */
+	NSS_WIFILI_EMSG_PDEV_INIT_INVALID_RADIOID_FAIL,
+			/**< Radio initialization failed due to invalid radio ID. */
+	WIFILI_EMSG_PDEV_INIT_INVALID_TARGETPDEVID_FAIL,
+			/**< Radio initialization failed due to invalid target physical device ID. */
+	NSS_WIFILI_EMSG_PDEV_TX_IRQ_ALLOC_FAIL,
+			/**< IRQ line allocation for radio transmission failed. */
+	NSS_WIFILI_EMSG_PDEV_RESET_INVALID_RADIOID_FAIL,
+			/**< Radio reset failed due to invalid radio ID. */
+	NSS_WIFILI_EMSG_PDEV_RESET_PDEV_NULL_FAIL,
+			/**< Radio reset failed due to NULL physical device. */
+	NSS_WIFILI_EMSG_PDEV_RESET_IMPROPER_STATE_FAIL,
+			/**< Radio reset failed due to improper state of pdev. */
+	NSS_WIFILI_EMSG_START_IMPROPER_STATE_FAIL,
+			/**< Device start fail due to improper state */
+	NSS_WIFILI_EMSG_PEER_CREATE_FAIL,
+			/**< Peer creation failed. */
+	NSS_WIFILI_EMSG_PEER_DELETE_FAIL,
+			/**< Peer deletion failed. */
+	NSS_WIFILI_EMSG_HASHMEM_INIT_FAIL,
+			/**< Peer hash memory allocation failed. */
+	NSS_WIFILI_EMSG_PEER_FREELIST_APPEND_FAIL,
+			/**< Appending peer to freelist failed. */
+	NSS_WIFILI_EMSG_PEER_CREATE_INVALID_VDEVID_FAIL,
+			/**< Peer creation failure due to invalid virtual device ID. */
+	NSS_WIFILI_EMSG_PEER_CREATE_INVALID_PEER_ID_FAIL,
+			/**< Peer creation failure due to invalid peer ID. */
+	NSS_WIFILI_EMSG_PEER_CREATE_VDEV_NULL_FAIL,
+			/**< Peer creation failure due to NULL virtual device. */
+	NSS_WIFILI_EMSG_PEER_CREATE_PDEV_NULL_FAIL,
+			/**< Peer creation failure due to NULL physical device. */
+	NSS_WIFILI_EMSG_PEER_CREATE_ALLOC_FAIL,
+			/**< Peer creation failure due to memory allocation failure. */
+	NSS_WIFILI_EMSG_PEER_DELETE_VAPID_INVALID_FAIL,
+			/**< Peer deletion failure due to invalid virtual device ID. */
+	NSS_WIFILI_EMSG_PEER_DELETE_INVALID_PEERID_FAIL,
+			/**< Peer deletion failed due to invalid peer ID. */
+	NSS_WIFILI_EMSG_PEER_DELETE_VDEV_NULL_FAIL,
+			/**< Peer deletion failure due to NULL virtual device. */
+	NSS_WIFILI_EMSG_PEER_DELETE_PDEV_NULL_FAIL,
+			/**< Peer deletion failure due to NULL physical device. */
+	NSS_WIFILI_EMSG_PEER_DELETE_PEER_NULL_FAIL,
+			/**< Peer deletion failure due to NULL peer. */
+	NSS_WIFILI_EMSG_PEER_DELETE_PEER_CORRUPTED_FAIL,
+			/**< Peer creation failure due to corrupted peer. */
+	NSS_WIFILI_EMSG_PEER_DUPLICATE_AST_INDEX_PEER_ID_FAIL,
+			/**< AST index provided is duplicate. */
+	NSS_WIFILI_EMSG_GROUP0_TIMER_ALLOC_FAIL,
+			/**< Timer allocation failure. */
+	NSS_WIFILI_EMSG_INSUFFICIENT_WT_FAIL,
+			/**< Insufficient worker thread error. */
+	NSS_WIFILI_EMSG_INVALID_NUM_TCL_RING_FAIL,
+			/**< Invalid number of Transmit Classifier rings provided in initialization message. */
+	NSS_WIFILI_EMSG_INVALID_NUM_REO_DST_RING_FAIL,
+			/**< Invalid number of Rx reorder destination ring in initialization message. */
+	NSS_WIFILI_EMSG_HAL_SRNG_SOC_ALLOC_FAIL,
+			/**< Srng SoC memory allocation failure. */
+	NSS_WIFILI_EMSG_HAL_SRNG_INVALID_RING_INFO_FAIL,
+			/**< Device ring information is invalid. */
+	NSS_WIFILI_EMSG_HAL_SRNG_TCL_ALLOC_FAIL,
+			/**< Transmit Classifier srng ring allocation failure. */
+	NSS_WIFILI_EMSG_HAL_SRNG_TXCOMP_ALLOC_FAIL,
+			/**< Txcomp srng ring allocation failure. */
+	NSS_WIFILI_EMSG_HAL_SRNG_REODST_ALLOC_FAIL,
+			/**< Rx reorder destination srng ring allocation failure. */
+	NSS_WIFILI_EMSG_HAL_SRNG_REOREINJECT_ALLOC_FAIL,
+			/**< Rx reorder reinject srng ring allocation failure. */
+	NSS_WIFILI_EMSG_HAL_SRNG_RXRELEASE_ALLOC_FAIL,
+			/**< Rx release srng ring allocation failure. */
+	NSS_WIFILI_EMSG_HAL_SRNG_RXEXCP_ALLOC_FAIL,
+			/**< Rx exception srng ring allocation failure. */
+	NSS_WIFILI_EMSG_HAL_TX_MEMALLOC_FAIL,
+			/**< Tx HAL (hardware abstraction layer) srng ring allocation failure. */
+	NSS_WIFILI_EMSG_HAL_TX_INVLID_POOL_NUM_FAIL,
+			/**< Invalid pool number in initialization message. */
+	NSS_WIFILI_EMSG_HAL_TX_INVALID_PAGE_NUM_FAIL,
+			/**< Invalid page numner in initialization message. */
+	NSS_WIFILI_EMSG_HAL_TX_DESC_MEM_ALLOC_FAIL,
+			/**< Tx descriptor memory allocation failure. */
+	NSS_WIFILI_EMSG_HAL_RX_MEMALLOC_FAIL,
+			/**< Rx memory allocation failure. */
+	NSS_WIFILI_EMSG_PDEV_RXDMA_RING_ALLOC_FAIL,
+			/**< Rx DMA ring allocation failed. */
+	NSS_WIFILI_EMSG_NAWDSEN_PEERID_INVALID,
+			/**< Peer NAWDS enable failure due to invalid peer ID. */
+	NSS_WIFILI_EMSG_NAWDSEN_PEER_NULL,
+			/**< Peer NAWDS enable failure due to peer being NULL. */
+	NSS_WIFILI_EMSG_NAWDSEN_PEER_CORRUPTED,
+			/**< Peer NAWDS enable failure due to corrupted peer. */
+	NSS_WIFILI_EMSG_WDS_PEER_CFG_FAIL,
+			/**< WDS peer configuration failure. */
+	NSS_WIFILI_EMSG_RESET_NO_STOP,
+			/**< Reset issued without stopping the device. */
+	NSS_WIFILI_EMSG_HAL_SRNG_INVALID_RING_BASE_FAIL,
+			/**< Ring base address is invalid. */
+	NSS_WIFILI_EMSG_PDEV_RX_INIT_FAIL,
+			/**< Pdev Rx initialization failure. */
+	NSS_WIFILI_EMESG_AST_ADD_FAIL,
+			/**< AST entry addition failure for connected peer. */
+	NSS_WIFILI_EMESG_AST_REMOVE_FAIL,
+			/**< AST entry removal failure for connected peer. */
+	NSS_WIFILI_EMESG_WDS_ADD_FAIL,
+			/**< WDS peer AST entry addition failure. */
+	NSS_WIFILI_EMESG_WDS_REMOVE_FAIL,
+			/**< WDS peer AST entry removal failure. */
+	NSS_WIFILI_EMESG_WDS_MAP_FAIL,
+			/**< WDS peer AST entry hardware index mapping failure. */
+	NSS_WIFILI_EMSG_WDS_INVALID_PEERID_FAIL,
+			 /**< Invalid peer id passed in WDS messages. */
+	NSS_WIFILI_EMSG_WDS_DUPLICATE_AST_INDEX_PEER_ID_FAIL,
+			/**< AST entry index is already filled. */
+	NSS_WIFILI_EMSG_INVALID_RADIO_CMD,
+			/**< Radio command is invalid. */
+	NSS_WIFILI_EMSG_INVALID_RADIO_IFNUM,
+			/**< Radio interface number is invalid. */
+	NSS_WIFILI_EMSG_PEER_SECURITY_PEER_NULL_FAIL,
+			/**< Security message failed as peer is NULL for a peer ID. */
+	NSS_WIFILI_EMSG_PEER_SECURITY_PEER_CORRUPTED_FAIL,
+			/**< Security message failed as peer is corrupted. */
+	NSS_WIFILI_EMSG_RADIO_INVALID_BUF_CFG,
+			/**< Buffer configuration message failed as invalid range value is provided. */
+	NSS_WIFILI_EMSG_INIT_FAIL_INVALID_TARGET,
+			/**< Invalid target SoC type from host. */
+	NSS_WIFILI_EMSG_PDEV_INIT_FAIL_INVALID_LMAC_ID,
+			/**< Invalid lower MAC ID from host. */
+	NSS_WIFILI_EMSG_STATE_PDEV_NOT_INITIALIZED,
+			/**< Configured message issued when radio is not initialized. */
+	NSS_WIFILI_EMESG_RX_TLV_INVALID,
+			/**< Invalid TLV length. */
+	NSS_WIFILI_EMESG_RX_BUF_LEN_INVALID,
+			/**< Invalid Rx buffer length. */
+	NSS_WIFILI_EMSG_TX_CAPTURE_MODE_UPDATE_FAIL,
+			/**< Tx capture mode update failure. */
+	NSS_WIFILI_EMSG_UNKNOWN
+			/**< Unknown error message. */
+};
+
+/**
+ * nss_wifili_soc_extended_data_types
+ *	Enumeration of extended data type to host.
+ */
+enum nss_wifili_soc_extended_data_types {
+	NSS_WIFILI_SOC_EXT_DATA_PKT_TYPE_NONE,		/**< Packet type is none. */
+	NSS_WIFILI_SOC_EXT_DATA_PKT_MSDU_LINK_DESC,	/**< Packet type is MSDU link descriptor. */
+	NSS_WIFILI_SOC_EXT_DATA_PKT_INVALID_PEER,	/**< Packet type is invalid peer. */
+	NSS_WIFILI_SOC_EXT_DATA_PKT_MIC_ERROR,		/**< Packet received with MIC error. */
+	NSS_WIFILI_SOC_EXT_DATA_PKT_2K_JUMP_ERROR,	/**< Packet received with 2K jump in sequence number. */
+	NSS_WIFILI_SOC_EXT_DATA_PKT_WIFI_PARSE_ERROR,	/**< Packet received with Wi-Fi parse error. */
+	NSS_WIFILI_SOC_EXT_DATA_PKT_TYPE_MAX		/**< Maximum extended data types. */
+};
+
+/**
+ * nss_wifili_radio_cmd
+ *	Wi-Fi radio commands for wifili.
+ */
+enum nss_wifili_radio_cmd {
+	NSS_WIFILI_RADIO_TX_CAPTURE_CMD,		/**< Enable Tx capture. */
+	NSS_WIFILI_SET_PRIMARY_RADIO,			/**< Set current radio as primary. */
+	NSS_WIFILI_SET_ALWAYS_PRIMARY,			/**< Set always primary flag. */
+	NSS_WIFILI_SET_FORCE_CLIENT_MCAST_TRAFFIC,	/**< Flag to force multicast traffic for a radio. */
+	NSS_WIFILI_SET_DROP_SECONDARY_MCAST,		/**< Flag to drop multicast traffic on secondary radio. */
+	NSS_WIFILI_SET_DBDC_FASTLANE,			/**< Flag to set DBDC fast-lane mode. */
+	NSS_WIFILI_SET_DBDC_NOBACKHAUL_RADIO,           /**< Flag to set DBDC to no backhaul radio. */
+	NSS_WIFILI_RADIO_MAX_CMD			/**< Maximum radio command index. */
+};
+
+/*
+ * WARNING: There is a 1:1 mapping between values of enum nss_wifili_stats_txrx and corresponding
+ * statistics string array in nss_stats.c.
+ */
+
+/**
+ * nss_wifili_stats_txrx
+ *	Wifili Tx or Rx statistics.
+ */
+enum nss_wifili_stats_txrx {
+	NSS_WIFILI_STATS_RX_MSDU_ERROR,
+		/**< Number of Rx packets received from ring with MSDU error. */
+	NSS_WIFILI_STATS_RX_INV_PEER_RCV,
+		/**< Number of Rx packets with invalid peer ID. */
+	NSS_WIFILI_STATS_RX_WDS_SRCPORT_EXCEPTION,
+		/**< Number of Rx packets exceptioned to host because of source port learn fail. */
+	NSS_WIFILI_STATS_RX_WDS_SRCPORT_EXCEPTION_FAIL,
+		/**< Number of Rx source port learn fail packets failed to get enqueued to host. */
+	NSS_WIFILI_STATS_RX_DELIVERD,
+		/**< Number of packets wifili has given to next node. */
+	NSS_WIFILI_STATS_RX_DELIVER_DROPPED,
+		/**< Number of packets which wifili failed to enqueue to next node. */
+	NSS_WIFILI_STATS_RX_INTRA_BSS_UCAST,
+		/**< Number of packets that wifili sent for intra-BSS unicast packet. */
+	NSS_WIFILI_STATS_RX_INTRA_BSS_UCAST_FAIL,
+		/**< Number of packets that wifili sent for intra-BSS unicast packet failed. */
+	NSS_WIFILI_STATS_RX_INTRA_BSS_MCAST,
+		/**< Number of packets that wifili sent for intra-BSS multicast packet. */
+	NSS_WIFILI_STATS_RX_INTRA_BSS_MCAST_FAIL,
+		/**< Number of packets that wifili sent for intra-BSS multicast packet failed. */
+	NSS_WIFILI_STATS_RX_SG_RCV_SEND,
+		/**< Number of packets scatter-gather sent. */
+	NSS_WIFILI_STATS_RX_SG_RCV_FAIL,
+		/**< Number of packets scatter-gather received failure. */
+	NSS_STATS_WIFILI_RX_MCAST_ECHO,
+		/**< Number of multicast echo packets received. */
+	NSS_STATS_WIFILI_RX_INV_TID,
+		/**< Number of invalid TID. */
+
+	/*
+	 * TODO: Move per TID based
+	 */
+	NSS_WIFILI_STATS_RX_FRAG_INV_SC,
+		/**< Number of fragments with invalid sequence control. */
+	NSS_WIFILI_STATS_RX_FRAG_INV_FC,
+		/**< Number of fragments with invalid frame control. */
+	NSS_WIFILI_STATS_RX_FRAG_NON_FRAG,
+		/**< Number of non-fragments received in fragments. */
+	NSS_WIFILI_STATS_RX_FRAG_RETRY,
+		/**< Number of retries for fragments. */
+	NSS_WIFILI_STATS_RX_FRAG_OOO,
+		/**< Number of out-of-order fragments. */
+	NSS_WIFILI_STATS_RX_FRAG_OOO_SEQ,
+		/**< Number of out-of-order sequence. */
+	NSS_WIFILI_STATS_RX_FRAG_ALL_FRAG_RCV,
+		/**< Number of times all fragments for a sequence has been received. */
+	NSS_WIFILI_STATS_RX_FRAG_DELIVER,
+		/**< Number of fragments delivered to host. */
+	NSS_WIFILI_STATS_TX_ENQUEUE,
+		/**< Number of packets that got enqueued to wifili. */
+	NSS_WIFILI_STATS_TX_ENQUEUE_DROP,
+		/**< Number of packets that dropped during enqueue to wifili. */
+	NSS_WIFILI_STATS_TX_DEQUEUE,
+		/**< Number of packets that are dequeued by wifili. */
+	NSS_WIFILI_STATS_TX_HW_ENQUEUE_FAIL,
+		/**< Number of Rx packets that NSS Wi-Fi offload path could successfully process. */
+	NSS_WIFILI_STATS_TX_SENT_COUNT,
+		/**< Number of Tx packets sent to hardware. */
+	NSS_WIFILI_STATS_TXRX_MAX,
+		/**< Number of maximum Tx or Rx statistics. */
+};
+
+/*
+ * WARNING: There is a 1:1 mapping between values of enum nss_wifili_stats_tcl and corresponding
+ * statistics string array in nss_stats.c.
+ */
+
+/**
+ * nss_wifili_stats_tcl
+ *	Wifili transmit classifier statistics.
+ */
+enum nss_wifili_stats_tcl {
+	NSS_WIFILI_STATS_TCL_NO_HW_DESC,		/**< Number of transmit classifier hardware descriptor. */
+	NSS_WIFILI_STATS_TCL_RING_FULL,			/**< Number of times transmit classifier ring was full. */
+	NSS_WIFILI_STATS_TCL_RING_SENT,			/**< Number of times transmit classifier descriptor sent. */
+	NSS_WIFILI_STATS_TCL_MAX,			/**< Number of maximum transmit classifier statistics. */
+};
+
+/*
+ * WARNING: There is a 1:1 mapping between values of enum nss_wifili_stats_tx_comp and corresponding
+ * statistics string array in nss_stats.c.
+ */
+
+/**
+ * nss_wifili_stats_tx_comp
+ *	Wifili Tx completion statistics.
+ */
+enum nss_wifili_stats_tx_comp {
+	NSS_WIFILI_STATS_TX_DESC_FREE_INV_BUFSRC,	/**< Number of invalid buffer source packets. */
+	NSS_WIFILI_STATS_TX_DESC_FREE_INV_COOKIE,	/**< Number of invalid cookie packets. */
+	NSS_WIFILI_STATS_TX_DESC_FREE_HW_RING_EMPTY,	/**< Number of times hardware ring empty found. */
+	NSS_WIFILI_STATS_TX_DESC_FREE_REAPED,		/**< Number of Tx packets that are reaped out of the Tx completion ring. */
+	NSS_WIFILI_STATS_TX_CAPTURE_ENQUEUE,		/**< Number of Tx packets enqueued to host. */
+	NSS_WIFILI_STATS_TX_CAPTURE_ENQUEUE_FAIL,	/**< Number of Tx packets failed to enqueue to host. */
+	NSS_WIFILI_STATS_TX_DESC_FREE_MAX,		/**< Number of Tx completion statistics. */
+};
+
+/*
+ * WARNING: There is a 1:1 mapping between values of enum nss_wifili_stats_reo and corresponding
+ * statistics string array in nss_stats.c.
+ */
+
+/**
+ * nss_wifili_stats_reo
+ *	Wifili Rx reorder statistics.
+ */
+enum nss_wifili_stats_reo {
+	NSS_WIFILI_STATS_REO_ERROR,			/**< Number of reorder error. */
+	NSS_WIFILI_STATS_REO_REAPED,			/**< Number of reorder reaped. */
+	NSS_WIFILI_STATS_REO_INV_COOKIE,		/**< Number of invalid cookie. */
+	NSS_WIFILI_STATS_REO_FRAG_RCV,			/**< Number of fragmented packets received. */
+	NSS_WIFILI_STATS_REO_MAX,			/**< Number of reorder statistics. */
+};
+
+/*
+ * WARNING: There is a 1:1 mapping between values of enum nss_wifili_stats_txsw_pool and corresponding
+ * statistics string array in nss_stats.c.
+ */
+
+/**
+ * nss_wifili_stats_txsw_pool
+ *	Wifili Tx descriptor statistics.
+ */
+enum nss_wifili_stats_txsw_pool {
+	NSS_WIFILI_STATS_TX_DESC_IN_USE,		/**< Number of Tx packets that are currently in flight. */
+	NSS_WIFILI_STATS_TX_DESC_ALLOC_FAIL,		/**< Number of Tx software descriptor allocation failures. */
+	NSS_WIFILI_STATS_TX_DESC_ALREADY_ALLOCATED,	/**< Number of Tx software descriptor already allocated. */
+	NSS_WIFILI_STATS_TX_DESC_INVALID_FREE,		/**< Number of Tx software descriptor invalid free. */
+	NSS_WIFILI_STATS_TX_DESC_FREE_SRC_FW,		/**< Number of Tx descriptor for which release source is firmware. */
+	NSS_WIFILI_STATS_TX_DESC_FREE_COMPLETION,	/**< Number of Tx descriptor completion. */
+	NSS_WIFILI_STATS_TX_DESC_NO_PB,			/**< Number of Tx descriptor pbuf is NULL. */
+	NSS_WIFILI_STATS_TX_QUEUELIMIT_DROP,		/**< Number of Tx dropped because of queue limit. */
+	NSS_WIFILI_STATS_TX_DESC_MAX,			/**< Number of Tx descriptor statistics. */
+};
+
+/*
+ * WARNING: There is a 1:1 mapping between values of enum nss_wifili_stats_ext_txsw_pool and corresponding
+ * statistics string array in nss_stats.c
+ */
+
+/**
+ * nss_wifili_stats_ext_txsw_pool
+ *	Wifili Rx extended descriptor statistics.
+ */
+enum nss_wifili_stats_ext_txsw_pool {
+	NSS_WIFILI_STATS_EXT_TX_DESC_IN_USE,		/**< Number of extended Tx packets that are currently in flight. */
+	NSS_WIFILI_STATS_EXT_TX_DESC_ALLOC_FAIL,	/**< Number of extended Tx software descriptor allocation failures. */
+	NSS_WIFILI_STATS_EXT_TX_DESC_ALREADY_ALLOCATED,	/**< Number of extended Tx software descriptor already allocated. */
+	NSS_WIFILI_STATS_EXT_TX_DESC_INVALID_FREE,	/**< Number of extended Tx software descriptor invalid free. */
+	NSS_WIFILI_STATS_EXT_TX_DESC_MAX,		/**< Number of extended Tx descriptor statistics. */
+};
+
+/*
+ * WARNING: There is a 1:1 mapping between values of enum nss_wifili_stats_rxdma_pool and corresponding
+ * statistics string array in nss_stats.c
+ */
+
+/**
+ * nss_wifili_stats_rxdma_pool
+ *	Wifili Rx descriptor statistics.
+ */
+enum nss_wifili_stats_rxdma_pool {
+	NSS_WIFILI_STATS_RX_DESC_NO_PB,			/**< Number of Rx descriptors that have no pbufs. */
+	NSS_WIFILI_STATS_RX_DESC_ALLOC_FAIL,		/**< Number of Rx descriptor allocation failures. */
+	NSS_WIFILI_STATS_RX_DESC_IN_USE,		/**< Number of Rx descriptor allocations in use. */
+	NSS_WIFILI_STATS_RX_DESC_MAX,			/**< Maximum number of Rx descriptor statistics. */
+};
+
+/*
+ * WARNING: There is a 1:1 mapping between values of enum nss_wifili_stats_rxdma_ring and corresponding
+ * statistics string array in nss_stats.c.
+ */
+
+/**
+ * nss_wifili_stats_rxdma_ring
+ *	Wifili Rx DMA(Direct Memory Access) ring statistics.
+ */
+enum nss_wifili_stats_rxdma_ring {
+	NSS_WIFILI_STATS_RXDMA_DESC_UNAVAILABLE,	/**< Number of Rx DMA descriptor unavailable. */
+	NSS_WIFILI_STATS_RXDMA_BUF_REPLENISHED,		/**< Number of Rx DMA buffer replenished. */
+	NSS_WIFILI_STATS_RXDMA_DESC_MAX,		/**< Number of Rx DMA descriptor statistics. */
+};
+
+/*
+ * WARNING: There is a 1:1 mapping between values of enum nss_wifili_stats_wbm and corresponding
+ * statistics string array in nss_stats.c.
+ */
+
+/**
+ * nss_wifili_stats_wbm
+ *	Wifili WBM(Wireless Buffer Manager) ring statistics.
+ */
+enum nss_wifili_stats_wbm {
+	NSS_WIFILI_STATS_WBM_IE_LOCAL_ALLOC_FAIL,	/**< Number of Wireless Buffer Manager internal local allocation failures. */
+	NSS_WIFILI_STATS_WBM_SRC_DMA,			/**< Number of receive invalid source DMA. */
+	NSS_WIFILI_STATS_WBM_SRC_DMA_CODE_INV,		/**< Number of receive invalid source DMA. */
+	NSS_WIFILI_STATS_WBM_SRC_REO,			/**< Number of receive invalid source reorder. */
+	NSS_WIFILI_STATS_WBM_SRC_REO_CODE_NULLQ,	/**< Number of receive invalid reorder error with NULL queue. */
+	NSS_WIFILI_STATS_WBM_SRC_REO_CODE_INV,		/**< Number of receive invalid reorder code invalid. */
+	NSS_WIFILI_STATS_WBM_SRC_INV,			/**< Number of receive invalid source invalid. */
+	NSS_WIFILI_STATS_WBM_MAX,			/**< Number of receive Wireless Buffer Manager statistics. */
+};
+
+/**
+ * nss_wifili_stats
+ *	NSS wifili statistics.
+ */
+struct nss_wifili_stats {
+	uint64_t stats_txrx[NSS_WIFILI_MAX_PDEV_NUM_MSG][NSS_WIFILI_STATS_TXRX_MAX];
+							/**< Number of Tx or Rx statistics. */
+	uint64_t stats_tcl_ring[NSS_WIFILI_MAX_TCL_DATA_RINGS_MSG][NSS_WIFILI_STATS_TCL_MAX];
+							/**< TCL statistics for each ring. */
+	uint64_t stats_tx_comp[NSS_WIFILI_MAX_TCL_DATA_RINGS_MSG][NSS_WIFILI_STATS_TX_DESC_FREE_MAX];
+							/**< Tx completion ring statistics. */
+	uint64_t stats_tx_desc[NSS_WIFILI_MAX_TXDESC_POOLS_MSG][NSS_WIFILI_STATS_TX_DESC_MAX];
+							/**< Tx descriptor pool statistics. */
+	uint64_t stats_ext_tx_desc[NSS_WIFILI_MAX_TX_EXT_DESC_POOLS_MSG][NSS_WIFILI_STATS_EXT_TX_DESC_MAX];
+							/**< Tx extended descriptor pool statistics. */
+	uint64_t stats_reo[NSS_WIFILI_MAX_REO_DATA_RINGS_MSG][NSS_WIFILI_STATS_REO_MAX];
+							/**< Rx reorder ring statistics. */
+	uint64_t stats_rx_desc[NSS_WIFILI_MAX_PDEV_NUM_MSG][NSS_WIFILI_STATS_RX_DESC_MAX];
+							/**< Rx software pool statistics. */
+	uint64_t stats_rxdma[NSS_WIFILI_MAX_PDEV_NUM_MSG][NSS_WIFILI_STATS_RXDMA_DESC_MAX];
+							/**< Rx DMA ring statistics. */
+	uint64_t stats_wbm[NSS_WIFILI_STATS_WBM_MAX];
+							/**< Wireless Buffer Manager error ring statistics. */
+};
+
+/*
+ * NSS wifili soc stats
+ */
+struct nss_wifili_soc_stats {
+	uint32_t soc_maxpdev;	/**< Maximum number of radios per SoC. */
+	struct nss_wifili_stats stats_wifili;
+				/**< Per-SoC statistics. */
+};
+
+/**
+ * nss_wifili_stats_notification
+ *	Data for sending wifili statistics.
+ */
+struct nss_wifili_stats_notification {
+	uint32_t core_id;		/**< Core ID. */
+	uint32_t if_num;		/**< Interface number for this wifili. */
+	struct nss_wifili_stats stats;	/**< Wifili statistics. */
+};
+
+#ifdef __KERNEL__ /* only kernel will use. */
+
+/**
+ * nss_wifili_hal_srng_info
+ *	Wifili HAL srng information.
+ */
+struct nss_wifili_hal_srng_info{
+	uint8_t ring_id;
+			/**< Ring ID. */
+	uint8_t mac_id;
+			/**< Pdev ID. */
+	uint8_t resv[2];
+	uint32_t ring_base_paddr;
+			/**< Physical base address of the ring. */
+	uint32_t num_entries;
+			/**< Number of entries in ring. */
+	uint32_t flags;	/**< Miscellaneous flags. */
+	uint32_t ring_dir;
+			/**< Ring direction: source or destination. */
+	uint32_t entry_size;
+			/**< Ring entry size. */
+	uint32_t low_threshold;
+			/**< Low threshold – in number of ring entries (valid for source rings only). */
+	uint32_t hwreg_base[NSS_WIFILI_MAX_SRNG_REG_GROUPS_MSG];
+			/**< Hardware ring base address. */
+};
+
+/**
+ * nss_wifili_hal_srng_soc_msg
+ *	Wifili hal srng message.
+ */
+struct nss_wifili_hal_srng_soc_msg {
+	uint32_t dev_base_addr;
+			/**< Base address of WLAN device. */
+	uint32_t shadow_rdptr_mem_addr;
+			/**< Shadow read pointer address. */
+	uint32_t shadow_wrptr_mem_addr;
+			/**< Shadow write pointer address. */
+	uint32_t lmac_rings_start_id;
+			/**< Start ID of LMAC rings. */
+};
+
+/**
+ * struct wifili_tx_desc_addtnl_mem_msg
+ * 	Wifili additional host memory message for increeased descriptors
+ */
+struct nss_wifili_tx_desc_addtnl_mem_msg {
+	uint32_t num_addtnl_addr;
+			/**< Number of additional memory pages provided. */
+	uint32_t addtnl_memory_addr[NSS_WIFILI_MAX_NUMBER_OF_ADDTNL_SEG];
+			/**< Physical memory addresse of each additional page. */
+	uint32_t addtnl_memory_size[NSS_WIFILI_MAX_NUMBER_OF_ADDTNL_SEG];
+			/**< Size of each additional page. */
+};
+
+/**
+ * nss_wifili_tx_desc_init_msg
+ *	Wifili software descriptor pool initialization message.
+ */
+struct nss_wifili_tx_desc_init_msg {
+	uint32_t num_tx_desc;
+			/**< Count of the software descriptors. */
+	uint32_t num_tx_desc_ext;
+			/**< Count of software extented descriptors. */
+	uint32_t num_pool;
+			/**< Number of descriptor pools. */
+	uint32_t memory_addr[NSS_WIFILI_MAX_NUMBER_OF_PAGE_MSG];
+			/**< Memory start address of each page. */
+	uint32_t memory_size[NSS_WIFILI_MAX_NUMBER_OF_PAGE_MSG];
+			/**< Memory size. */
+	uint32_t num_memaddr;
+			/**< Number of memory address. */
+	uint32_t ext_desc_page_num;
+			/**< Extended descriptor page number. */
+	uint32_t num_tx_desc_2;
+			/**< Count of the software descriptors for second radio. */
+	uint32_t num_tx_desc_ext_2;
+			/**< Count of software extended descriptors for second radio. */
+	uint32_t num_tx_desc_3;
+			/**< Count of the software descriptors for third radio. */
+	uint32_t num_tx_desc_ext_3;
+			/**< Count of software extended descriptors for third radio. */
+	uint32_t num_tx_device_limit;
+			/**< Count of software Tx descriptors for the device. */
+};
+
+/**
+ * nss_wifili_rx_init_param
+ *	Rx initialization parameters.
+ */
+struct nss_wifili_rx_init_param {
+	uint16_t tlv_size;	/**< Size of Rx TLV structure. */
+	uint16_t rx_buf_len;	/**< Rx buffer length programmed to hardware. */
+};
+
+/**
+ * nss_wifili_init_msg
+ *	Wifili SoC initialization message.
+ */
+struct nss_wifili_init_msg {
+	struct nss_wifili_hal_srng_soc_msg hssm;
+	uint8_t num_tcl_data_rings;
+			/**< Number of Transmit Classifier data rings. */
+	uint8_t num_reo_dest_rings;
+			/**< Number of Rx reorder rings. */
+	uint8_t flags;
+			/**< Flags for SoC initialization */
+	uint8_t soc_mem_profile;
+			/**< SoC memory profile (256M/512M/1G). */
+	struct nss_wifili_hal_srng_info tcl_ring_info[NSS_WIFILI_MAX_TCL_DATA_RINGS_MSG];
+			/**< Transmit Classifier data ring configuration information. */
+	struct nss_wifili_hal_srng_info tx_comp_ring[NSS_WIFILI_MAX_TCL_DATA_RINGS_MSG];
+			/**< Tx completion ring configuration information. */
+	struct nss_wifili_hal_srng_info reo_dest_ring[NSS_WIFILI_MAX_REO_DATA_RINGS_MSG];
+			/**< Rx reorder destination ring configuration information. */
+	struct nss_wifili_hal_srng_info reo_exception_ring;
+			/**< Rx reorder exception ring configuration information. */
+	struct nss_wifili_hal_srng_info rx_rel_ring;
+			/**< Wireless Buffer Manager release ring configuration information. */
+	struct nss_wifili_hal_srng_info reo_reinject_ring;
+			/**< Reinject ring configuration information. */
+	struct nss_wifili_tx_desc_init_msg wtdim;
+			/**< Tx descriptor initialization message. */
+	uint32_t target_type;
+			/**< Target type based on SoC. */
+	struct nss_wifili_rx_init_param wrip;
+			/**< Rx parameters to initialize Rx context. */
+	struct nss_wifili_tx_desc_addtnl_mem_msg wtdam;
+			/**< Tx descriptor additional memory message. */
+	uint32_t tx_sw_internode_queue_size;
+			/**< Tx software internode queue size. */
+};
+
+/**
+ * nss_wifili_pdev_deinit_msg
+ *	Wifili pdev deinit message.
+ */
+struct nss_wifili_pdev_deinit_msg {
+	uint32_t ifnum;	/**< NSS interface number of pdev. */
+};
+
+/**
+ * nss_wifili_pdev_init_msg
+ *	Wifili pdev initialization message.
+ */
+struct nss_wifili_pdev_init_msg {
+	struct nss_wifili_hal_srng_info rxdma_ring;
+			/**< MAC (Media Access Control) ring configuration. */
+	uint32_t radio_id;
+			/**< MAC radio ID. */
+	uint32_t hwmode;
+			/**< MAC hardware mode. */
+	uint32_t lmac_id;
+			/**< Lower MAC ID. */
+	uint32_t num_rx_swdesc;
+			/**< Number of descriptors per Rx pool. */
+	uint32_t target_pdev_id;
+			/**< Target physical device ID. */
+	uint8_t scheme_id;
+			/**< Radio scheme ID. */
+	uint8_t reserved[3];
+			/**< Padding for alignment. */
+};
+
+/**
+ * nss_wifili_peer_ast_flowid_map_msg
+ *	Wifili peer AST flow ID map message.
+ */
+struct nss_wifili_peer_ast_flowid_map_msg {
+	uint8_t peer_mac_addr[ETH_ALEN];
+			/**< Peer MAC address. */
+	uint16_t vdev_id;
+			/**< VAP ID. */
+	uint16_t ast_idx[NSS_WIFILI_PEER_AST_FLOWQ_MAX];
+			/**< Address search table index. */
+	uint8_t tid_valid_mask[NSS_WIFILI_PEER_AST_FLOWQ_MAX];
+			/**< TID valid mask for a flow. */
+	uint8_t is_valid[NSS_WIFILI_PEER_AST_FLOWQ_MAX];
+			/**< Valid bit. */
+	uint8_t flowQ[NSS_WIFILI_PEER_AST_FLOWQ_MAX];
+			/**< Flow queue. */
+	uint16_t peer_id;
+			/**< Peer ID. */
+	uint8_t reserved[2];
+			/**< Padding for alignment. */
+};
+
+/**
+ * nss_wifili_peer_ast
+ *	Wifili peer creation message.
+ */
+struct nss_wifili_peer_msg {
+	uint8_t peer_mac_addr[6];
+			/**< Peer MAC address. */
+	uint16_t vdev_id;
+			/**< VAP ID. */
+	uint16_t peer_id;
+			/**< Peer ID. */
+	uint16_t hw_ast_idx;
+			/**< Hardware address search table index. */
+	uint8_t is_nawds;
+			/**< NAWDS enabled for peer. */
+	uint8_t pext_stats_valid;
+			/**< Peer extended statistics valid. */
+	uint16_t psta_vdev_id;
+			/**< Proxy station VAP ID. */
+	uint32_t nss_peer_mem;
+			/**< Holds peer memory adderss for NSS. */
+	uint32_t tx_ast_hash;
+			/**< AST hash to be used during packet transmission. */
+	uint32_t pext_stats_mem;
+			/**< Peer extended statistics memory. */
+	uint32_t flags;
+			/**< Peer flags. */
+};
+
+/**
+ * nss_wifili_peer_freelist_append_msg
+ *	Peer memory request.
+ */
+struct nss_wifili_peer_freelist_append_msg {
+	uint32_t addr;
+			/**< Starting address of peer_freelist pool. */
+	uint32_t length;
+			/**< Length of peer freelist pool. */
+	uint32_t num_peers;
+			/**< Maximum number of peer entries supported in pool. */
+};
+
+/**
+ * nss_wifili_wds_extn_peer_cfg_msg
+ *	Configuration information when the WDS vendor extension is enabled.
+ */
+struct nss_wifili_wds_extn_peer_cfg_msg {
+	uint8_t peer_mac_addr[ETH_ALEN];	/**< Peer MAC address. */
+	uint8_t wds_flags;			/**< WDS flags populated from the host. */
+	uint8_t reserved;			/**< Alignment padding. */
+	uint16_t peer_id;			/**< Peer ID. */
+};
+
+/**
+ * nss_wifili_tx_stats
+ *	Tx statistics.
+ */
+struct nss_wifili_tx_stats {
+	uint32_t tx_enqueue_dropped;
+			/**< Tx enqueue drop count. */
+	uint32_t tx_enqueue_cnt;
+			/**< Tx enqueue succesful count. */
+	uint32_t tx_dequeue_cnt;
+			/**< Tx dequeue count. */
+	uint32_t tx_send_fail_cnt;
+			/**< Hardware send failure count. */
+	uint32_t inv_peer;
+			/**< Invalid peer enqueue count. */
+	uint32_t inv_peer_drop_byte_cnt;
+			/**< Invalid peer drop byte count. */
+	uint32_t tx_input_pkt;
+			/**< Tx packets ready to sent. */
+	uint32_t tx_processed_pkt;
+			/**< Tx numner of packets sent. */
+	uint32_t tx_processed_bytes;
+			/**< Tx number of bytes processed. */
+};
+
+/**
+ * nss_wifili_rx_stats
+ *	Rx statistics.
+ */
+struct nss_wifili_rx_stats {
+	uint32_t rx_msdu_err;
+					/**< Rx msdu error count. */
+	uint32_t rx_inv_peer;
+					/**< Rx invalid peer count. */
+	uint32_t rx_scatter_inv_peer;
+					/**< Rx scatter invalid peer count. */
+	uint32_t rx_wds_learn_send;
+					/**< WDS source port learn packet. */
+	uint32_t rx_wds_learn_send_fail;
+					/**< WDS source port learn exception send failure count. */
+	uint32_t rx_send_dropped;
+					/**< Rx send dropped count. */
+	uint32_t rx_deliver_cnt;
+					/**< Rx deliver count to next node. */
+	uint32_t rx_deliver_cnt_fail;
+					/**< Rx deliver count failure. */
+	uint32_t rx_intra_bss_ucast_send;
+					/**< Intra-BSS unicast sent count. */
+	uint32_t rx_intra_bss_ucast_send_fail;
+					/**< Intra-BSS unicast send failure count. */
+	uint32_t rx_intra_bss_mcast_send;
+					/**< Intra-BSS multicast send count. */
+	uint32_t rx_intra_bss_mcast_send_fail;
+					/**< Intra-BSS multicast send failure count. */
+	uint32_t rx_sg_recv_send;
+					/**< Rx scatter-gather receive send count. */
+	uint32_t rx_sg_recv_fail;
+					/**< Rx scatter-gather receive failure count. */
+	uint32_t rx_me_pkts;		/**< Rx multicast echo packets count. */
+	uint32_t rx_inv_tid;		/**< Rx invalid TID. */
+
+	/*
+	 * TODO: Move per tid based.
+	 */
+	uint32_t rx_frag_inv_sc;		/**< Rx invalid frame sequence control. */
+	uint32_t rx_frag_inv_fc;		/**< Rx invalid frame control count. */
+	uint32_t rx_non_frag_err;		/**< Rx non-fragment received in fragmention. */
+	uint32_t rx_repeat_fragno;		/**< Rx fragment retry counters. */
+	uint32_t rx_ooo_frag;			/**< Rx out-of-order fragments count. */
+	uint32_t rx_ooo_frag_seq;		/**< Rx out-of-order sequence count. */
+	uint32_t rx_all_frag_rcv;		/**< Rx all fragments received count. */
+	uint32_t rx_frag_deliver;		/**< Rx fragment deliver counters. */
+};
+
+/**
+ * nss_wifili_tx_tcl_ring_stats
+ *	Transmit Classifier ring specific statistics.
+ */
+struct nss_wifili_tx_tcl_ring_stats {
+	uint32_t tcl_no_hw_desc;	/**< Number of Transmit Classifier hardware descriptors. */
+	uint32_t tcl_ring_full;		/**< Number of times Transmit Classifier ring full. */
+	uint32_t tcl_ring_sent;		/**< Total number of ring sent. */
+};
+
+/**
+ * nss_wifili_tx_comp_ring_stats
+ *	Tx completion ring statistics.
+ */
+struct nss_wifili_tx_comp_ring_stats {
+	uint32_t invalid_bufsrc;		/**< Tx completion ring descriptor invalid buffer source. */
+	uint32_t invalid_cookie;		/**< Tx completion ring descriptor has invalid cookies. */
+	uint32_t hw_ring_empty;			/**< Tx completion hardware ring empty. */
+	uint32_t ring_reaped;			/**< Tx completion successfull ring reaped. */
+	uint32_t tx_cap_enqueue_count;		/**< Number of Tx packets enqueued to host. */
+	uint32_t tx_cap_enqueue_fail_count;	/**< Number of Tx packets failed to enqueue to host. */
+};
+
+/**
+ * nss_wifili_tx_sw_pool_stats
+ *	Tx completion sw statistics.
+ */
+struct nss_wifili_tx_sw_pool_stats {
+	uint32_t desc_alloc;			/**< Tx descriptor software pool descriptor in use. */
+	uint32_t desc_alloc_fail;		/**< Tx descriptor software pool allocation failure . */
+	uint32_t desc_already_allocated;	/**< Tx descriptor re-allocation for allocated descriptor. */
+	uint32_t desc_invalid_free;		/**< Tx descriptor freeing of allocated descriptor. */
+	uint32_t tx_rel_src_fw;			/**< Tx descriptor source is firmware. */
+	uint32_t tx_rel_ext_desc;		/**< Tx descriptor scatter-gather. */
+	uint32_t tx_rel_tx_desc;		/**< Tx descriptor source is hardware*/
+	uint32_t tx_rel_no_pb;			/**< Tx descriptor has pbuf present. */
+	uint32_t tx_queue_limit_drop;		/**< Tx number of packets dropped because of queueing limits. */
+};
+
+/**
+ * wifili_tx_ext_sw_pool_stats
+ *	Tx extended descriptor pool.
+ */
+struct nss_wifili_tx_ext_sw_pool_stats {
+	uint32_t desc_alloc;			/**< Tx extend (scatter gather) descriptor in use. */
+	uint32_t desc_alloc_fail;		/**< Tx extend descriptor allocation failure. */
+	uint32_t desc_already_allocated;	/**< Tx extend descriptor already allocated. */
+	uint32_t desc_invalid_free;		/**< Tx descriptor invalid source. */
+
+};
+
+/**
+ * nss_wifili_rx_wbm_ring_stats
+ *	WBM (Wireless Buffer Manager) release ring statistics.
+ */
+struct nss_wifili_rx_wbm_ring_stats {
+	uint32_t invalid_buf_mgr;		/**< Invalid buffer manager. */
+	uint32_t err_src_rxdma;			/**< Wireless Buffer Manager source is Rx DMA ring. */
+	uint32_t err_src_rxdma_code_inv;	/**< Wireless Buffer Manager source DMA reason unknown. */
+	uint32_t err_src_reo;			/**< Wireless Buffer Manager source is receive reorder ring. */
+	uint32_t err_src_reo_code_nullq;	/**< Wireless Buffer Manager source receive reorder ring because of NULL TLV. */
+	uint32_t err_src_reo_code_inv;		/**< Wireless Buffer Manager source receive reorder ring reason unknown. */
+	uint32_t err_src_invalid;		/**< Wireless Buffer Manager source is unknown. */
+	uint32_t err_reo_codes[NSS_WIFILI_REO_CODE_MAX];
+						/**< Receive reoder error codes. */
+	uint32_t err_dma_codes[NSS_WIFILI_DMA_CODE_MAX];
+						/**< DMA error codes. */
+	uint32_t err_internal_codes[NSS_WIFILI_WBM_INTERNAL_ERR_MAX];
+						/**< Wireless Buffer Manager error codes. */
+};
+
+/**
+ * nss_wifili_rx_reo_ring_stats
+ *	Rx reorder error statistics.
+ */
+struct nss_wifili_rx_reo_ring_stats {
+	uint32_t ring_error;			/**< Rx reorder ring error. */
+	uint32_t ring_reaped;			/**< Number of ring descriptor reaped. */
+	uint32_t invalid_cookie;		/**< Number of invalid cookie. */
+	uint32_t defrag_reaped;			/**< Rx defragment receive count. */
+};
+
+/**
+ * nss_wifili_rx sw_pool_stats
+ *	Wifili DMA sw pool statistics.
+ */
+struct nss_wifili_rx_sw_pool_stats {
+	uint32_t rx_no_pb;			/**< Rx software descriptor number of buffer available. */
+	uint32_t desc_alloc;			/**< Number of descriptor in use. */
+	uint32_t desc_alloc_fail;		/**< Number of descriptor allocation failure. */
+};
+
+/**
+ * nss_wifili_rx_dma_ring_stats
+ *	Wifili Rx DMA ring statistics.
+ */
+struct nss_wifili_rx_dma_ring_stats {
+	uint32_t rx_hw_desc_unavailable;	/**< Number of times hardware descriptor is unavailable. */
+	uint32_t rx_buf_replenished;		/**< Number of buffers replenished. */
+};
+
+/**
+ * nss_wifili_dbdc_mode_stats
+ *	Wifili DBDC mode statistics.
+ */
+struct nss_wifili_dbdc_mode_stats {
+	uint32_t dbdc_flush_ast_failed;
+			/**< Number of times DBDC AST flush message send has failed. */
+	uint32_t dbdc_drop_rx_secmcast;
+			/**< Number of packets dropped in DBDC Rx for secondary multicast. */
+	uint32_t dbdc_drop_tx_secmcast;
+			/**< Number of packets dropped in DBDC Tx for secondary multicast. */
+	uint32_t dbdc_drop_rx_alwaysprimary;
+			/**< Number of packets dropped in DBDC Rx for always primary. */
+	uint32_t dbdc_drop_tx_alwaysprimary;
+			/**< Number of packets dropped in DBDC Tx for always primary. */
+	uint32_t dbdc_drop_loop_rx;
+			/**< Number of packets dropped in DBDC Rx for DBDC loop. */
+	uint32_t dbdc_drop_loop_tx;
+			/**< Number of packets dropped in DBDC Tx for DBDC loop. */
+};
+
+/**
+ * nss_wifili_delay_stats
+ * 	Wifili delay statistics.
+ */
+struct nss_wifili_delay_stats {
+	uint32_t delay_bucket[NSS_WIFILI_DELAY_INDEX_MAX];
+			/**< Delay buckets for histogram. */
+	uint32_t min_delay;
+			/**< Minimum delay. */
+	uint32_t avg_delay;
+			/**< Average delay. */
+	uint32_t max_delay;
+			/**< Maximum delay. */
+};
+
+/**
+ * nss_wifili_v3_delay_per_tid_stats
+ * 	Wifili version 3 delay per TID statistics.
+ */
+struct nss_wifili_v3_delay_per_tid_stats {
+	struct nss_wifili_delay_stats swq_delay;
+				/**< Software enqueue delay. */
+	struct nss_wifili_delay_stats hwtx_delay;
+				/**< Hardware transmit delay. */
+	struct nss_wifili_delay_stats tx_intfrm_delay;
+				/**< Transmit interframe delay at radio entry. */
+	struct nss_wifili_delay_stats rx_intfrm_delay;
+				/**< Receive interframe delay. */
+};
+
+/**
+ * nss_wifili_v3_per_tid_tx_rx_stats
+ * 	Wifili version 3 Tx and Rx statistics per TID.
+ */
+struct nss_wifili_v3_tx_rx_per_tid_stats {
+	uint32_t radio_ingress_enq_drop_cnt;
+				/**< Ingress enqueue drop count. */
+	uint32_t transmit_succes_cnt;
+				/**< Total successful transmit count. */
+	uint32_t transmit_fwdrop_cnt;
+				/**< Firmware drop count. */
+	uint32_t transmit_hwdrop_cnt;
+				/**< Hardware drop count. */
+	uint32_t transmit_desc_fail_cnt;
+				/**< Transmit descriptor fail count. */
+	uint32_t transmit_complete_cnt;
+				/**< Total transmit count. */
+	uint32_t rx_delivered_cnt;
+				/**< Total Rx packets delivered to next node. */
+	uint32_t rx_deliver_fail_cnt;
+				/**< Rx deliver fail count. */
+	uint32_t rx_intrabss_cnt;
+				/**< Intra-BSS Rx count. */
+	uint32_t rx_intrabss_fail_cnt;
+				/**< Intra-BSS Rx fail count. */
+	uint32_t num_msdu_recived;
+				/**< Number of MSDU received from hardware. */
+	uint32_t num_mcast_msdu_recived;
+				/**< Number of broadcast MSDU received. */
+	uint32_t num_bcast_msdu_recived;
+				/**< Number of multicast MSDU received. */
+	uint32_t transmit_tqm_status_cnt[NSS_WIFILI_TQM_STATUS_MAX];
+				/**< Number of frames with this TQM completion status. */
+	uint32_t transmit_htt_status_cnt[NSS_WIFILI_HTT_STATUS_MAX];
+				/**< Number of frames with this HTT completion status. */
+};
+
+/**
+ * nss_wifili_v3_tx_rx_per_ac_stats
+ * 	Wifili version 3 Tx and Rx statistics per AC.
+ */
+struct nss_wifili_v3_tx_rx_per_ac_stats {
+	uint32_t radio_ingress_enq_cnt;
+				/**< Ingress enqueue packet count. */
+	uint32_t radio_ingress_deq_cnt;
+				/**< Ingress dequeue count. */
+	uint32_t transmit_enq_cnt;
+				/**< Transmit enqueue count. */
+};
+
+/**
+ * nss_wifili_radio_tx_rx_stats_v3
+ * 	Wifili version 3 radio Tx and Rx statistics.
+ */
+struct nss_wifili_radio_tx_rx_stats_v3 {
+	struct nss_wifili_v3_tx_rx_per_tid_stats tid_stats[NSS_WIFILI_MAX_TID];
+				/**< Per-TID Tx and Rx statistics. */
+	struct nss_wifili_v3_tx_rx_per_ac_stats ac_stats[NSS_WIFILI_WME_AC_MAX];
+				/**< Per-Access Category Tx and Rx statistics. */
+};
+
+/**
+ * nss_wifili_radio_delay_stats_v3
+ * 	Wifili version 3 radio delay statistics.
+ */
+struct nss_wifili_radio_delay_stats_v3 {
+	struct nss_wifili_v3_delay_per_tid_stats v3_delay_stats[NSS_WIFILI_MAX_TID];
+				/**< Per-TID delay statistics. */
+};
+
+/**
+ * nss_wifili_pdev_v3_tx_rx_stats_sync_msg
+ * 	Wifili message to synchronize version 3 Tx and Rx statistics to HLOS.
+ */
+struct nss_wifili_pdev_v3_tx_rx_stats_sync_msg {
+	uint32_t radio_id;
+			/**< Radio ID. */
+	struct nss_wifili_radio_tx_rx_stats_v3 wlpv3_txrx_stats;
+			/**< Wifli version 3 Tx and Rx statistics. */
+};
+
+/**
+ * nss_wifili_pdev_v3_delay_stats_sync_msg
+ * 	Wifili message to synchronize version 3 delay statistics to HLOS.
+ */
+struct nss_wifili_pdev_v3_delay_stats_sync_msg {
+	uint32_t radio_id;
+			/**< Radio ID. */
+	struct nss_wifili_radio_delay_stats_v3 wlpv3_delay_stats;
+			/**< Wifli version 3 delay statistics. */
+};
+
+/**
+ * nss_wifili_device_stats
+ * 	Wifili specific statistics.
+ */
+struct nss_wifili_device_stats {
+	struct nss_wifili_tx_tcl_ring_stats tcl_stats[NSS_WIFILI_MAX_TCL_DATA_RINGS_MSG];
+									/**< Transmit Classifier ring statistics. */
+	struct nss_wifili_tx_comp_ring_stats txcomp_stats[NSS_WIFILI_MAX_TCL_DATA_RINGS_MSG];
+									/**< Tx completion ring statistics. */
+	struct nss_wifili_tx_sw_pool_stats tx_sw_pool_stats[NSS_WIFILI_MAX_TXDESC_POOLS_MSG];
+									/**< Tx software pool statistics. */
+	struct nss_wifili_tx_ext_sw_pool_stats tx_ext_sw_pool_stats[NSS_WIFILI_MAX_TX_EXT_DESC_POOLS_MSG];
+									/**< Tx extended software pool statistics. */
+	struct nss_wifili_tx_stats tx_data_stats[NSS_WIFILI_MAX_PDEV_NUM_MSG];
+									/**< Tx data statistics for each pdev. */
+	struct nss_wifili_rx_reo_ring_stats rxreo_stats[NSS_WIFILI_MAX_REO_DATA_RINGS_MSG];
+									/**< Rx reorder ring statistics. */
+	struct nss_wifili_rx_sw_pool_stats rx_sw_pool_stats[NSS_WIFILI_MAX_PDEV_NUM_MSG];
+									/**< Rx DMA software pool statistics. */
+	struct nss_wifili_rx_stats rx_data_stats[NSS_WIFILI_MAX_PDEV_NUM_MSG];
+									/**< Rx data statistics for each pdev. */
+	struct nss_wifili_rx_dma_ring_stats rxdma_stats[NSS_WIFILI_MAX_PDEV_NUM_MSG];
+									/**< Rx DMA ring statistics. */
+	struct nss_wifili_rx_wbm_ring_stats rxwbm_stats;
+									/**< Wireless Buffer Manager ring statistics. */
+	struct nss_wifili_dbdc_mode_stats dbdc_stats;
+									/**< DBDC mode statistics. */
+};
+
+/**
+ * nss_wifili_stats_sync_msg
+ *	Wifili SoC statistics synchronization message.
+ */
+struct nss_wifili_stats_sync_msg {
+	struct nss_wifili_device_stats stats;
+			/**< Device statistics. */
+};
+
+/**
+ * nss_wifili_soc_linkdesc_per_packet_metadata
+ *	Link descriptor per packet metadata.
+ */
+struct nss_wifili_soc_linkdesc_per_packet_metadata
+{
+	uint32_t desc_addr;	/**< Link descriptor address. */
+};
+
+/**
+ * nss_wifili_soc_per_packet_metadata
+ *	Per packet special data that has to be sent to host.
+ */
+struct nss_wifili_soc_per_packet_metadata {
+	uint16_t pkt_type;	/**< Packet type. */
+	uint8_t pool_id;	/**< Pool ID of invalid peer packets. */
+	uint8_t reserved;	/**< Alignment padding. */
+
+	/**
+	 *  Link descriptor per packet metadata.
+	 */
+	union {
+		struct nss_wifili_soc_linkdesc_per_packet_metadata linkdesc_metadata;
+	} metadata;	/**< Per packet link descriptor metadata. */
+};
+
+/**
+ * nss_wifili_tx_dropped
+ *	Tx peer dropped packets.
+ */
+struct nss_wifili_tx_dropped {
+	uint32_t drop_stats[NSS_WIFILI_TQM_RR_MAX];	/**< Discarded by firmware. */
+	uint32_t tx_nawds_mcast_drop_cnt;		/**< Total number of NAWDS multicast packets dropped. */
+};
+
+/**
+ * nss_wifili_tx_ctrl_stats
+ *	Tx peer statistics.
+ */
+struct nss_wifili_tx_ctrl_stats {
+	uint32_t ofdma; 		/**< Number of orthogonal frequency-division multiple
+					  access packets. */
+	uint32_t non_amsdu_cnt; 	/**< Number of MSDUs with no MSDU level aggregation. */
+	uint32_t amsdu_cnt;		/**< Number of MSDUs part of AMSDU. */
+	uint32_t tx_mcast_cnt;          /**< Total number of multicast packets sent. */
+	uint32_t tx_mcast_bytes;        /**< Total number of multicast bytes sent. */
+	uint32_t tx_ucast_cnt;          /**< Total number of unicast packets sent. */
+	uint32_t tx_ucast_bytes;        /**< Total number of unicast bytes sent. */
+	uint32_t tx_bcast_bytes;        /**< Total number of broadcast bytes sent. */
+	uint32_t tx_bcast_cnt;          /**< Total number of broadcast packets sent. */
+	struct nss_wifili_tx_dropped dropped;	/**< Tx peer dropped. */
+	uint32_t tx_success_cnt;	/**< Total number of packets sent successfully. */
+	uint32_t tx_success_bytes;	/**< Total number of bytes sent successfully. */
+	uint32_t tx_nawds_mcast_cnt;	/**< Total number of NAWDS multicast packets sent. */
+	uint32_t tx_nawds_mcast_bytes;	/**< Total number of NAWDS multicast bytes sent. */
+	uint32_t retries;		/**< Total number of retries. */
+};
+
+/**
+ * nss_wifili_peer_rx_err
+ *	Rx peer errors.
+ */
+struct nss_wifili_rx_err {
+	uint32_t mic_err;	/**< Rx MIC errors. */
+	uint32_t decrypt_err;	/**< Rx Decryption errors. */
+};
+
+/**
+ * nss_wifili_rx_ctrl_stats
+ *	Peer Rx statistics.
+ */
+struct nss_wifili_rx_ctrl_stats {
+	struct nss_wifili_rx_err err;			/**< Rx peer errors. */
+	uint32_t multipass_rx_pkt_drop;         /**< Total number of multipass packets without a VLAN header. */
+	uint32_t peer_unauth_rx_pkt_drop;		/**< Number of receive packets dropped due to an authorized peer. */
+	uint32_t reserved_type[NSS_WIFILI_MAX_RESERVED_TYPE];	/**< Reserved type for future use. */
+	uint32_t non_amsdu_cnt;			/**< Number of MSDUs with no MSDU level aggregation. */
+	uint32_t amsdu_cnt;			/**< Number of MSDUs part of AMSDU. */
+	uint32_t mcast_rcv_cnt;			/**< Total number of multicast packets received. */
+	uint32_t mcast_rcv_bytes;		/**< Total number of multicast bytes received. */
+	uint32_t rx_recvd;			/**< Total Rx received count. */
+	uint32_t rx_recvd_bytes;		/**< Total Rx received count. */
+	uint32_t nawds_mcast_drop;		/**< Total NAWDS drop count. */
+	uint32_t nawds_mcast_drop_bytes;	/**< Total NAWDS drop count. */
+	uint32_t rx_intra_bss_pkts_num;		/**< Total Intra-BSS packets received. */
+	uint32_t rx_intra_bss_pkts_bytes;	/**< Total Intra-BSS bytes received. */
+	uint32_t rx_intra_bss_fail_num;		/**< Total Intra-BSS packets failed. */
+	uint32_t rx_intra_bss_fail_bytes;	/**< Total Intra-BSS bytes received. */
+	uint32_t bcast_rcv_cnt;			/**< Total number of broadcast packets received. */
+	uint32_t bcast_rcv_bytes;		/**< Total number of broadcast bytes received. */
+	uint32_t defrag_mcast_drop;		/**< Total number of defrag multicast dropped packets. */
+};
+
+/**
+ * nss_wifili_peer_ctrl_stats
+ *	Wifili peer control statistics.
+ */
+struct nss_wifili_peer_ctrl_stats {
+	uint32_t peer_id;	/**< Peer ID. */
+	struct nss_wifili_tx_ctrl_stats tx;
+				/**< Peer Tx control statistics. */
+	struct nss_wifili_rx_ctrl_stats rx;
+				/**< Peer Rx control statistics. */
+};
+
+/**
+ * nss_wifili peer_stats
+ *	Wifili peer statistics.
+ */
+struct nss_wifili_peer_stats {
+	uint32_t npeers;	/**< Number of entries of peer statistics. */
+	struct nss_wifili_peer_ctrl_stats wpcs[1];
+				/**< Wifili peer control statistics. */
+};
+
+/**
+ * nss_wifili_peer_stats_msg
+ *	Wifili peer statistics message.
+ */
+struct nss_wifili_peer_stats_msg {
+	struct nss_wifili_peer_stats stats;
+			/**< Wifili peer statistics. */
+};
+
+/**
+ * nss_wifili_sojourn_per_tid_stats
+ *      Wifili sojourn per TID statistics.
+ */
+struct nss_wifili_sojourn_per_tid_stats {
+	uint32_t avg_sojourn_msdu;	/**< Average per-TID of all time difference. */
+	uint32_t sum_sojourn_msdu;	/**< Sum per-TID of all time difference. */
+	uint32_t num_msdus;		/**< MSDUs per TID. */
+};
+
+/**
+ * nss_wifili_sojourn_peer_stats
+ *      Wifili sojourn peer statistics.
+ */
+struct nss_wifili_sojourn_peer_stats {
+	uint32_t peer_id;				/**< Peer ID. **/
+	struct nss_wifili_sojourn_per_tid_stats stats[NSS_WIFILI_MAX_TID];	/**< Statistics per TID. **/
+};
+
+/**
+ * nss_wifili_sojourn_stats_msg
+ *      Wifili sojourn statistics message.
+ */
+struct nss_wifili_sojourn_stats_msg {
+	uint32_t npeers;					/**< Number of peers. */
+	struct nss_wifili_sojourn_peer_stats sj_peer_stats[1];	/**< Per-peer sojourn statistics. */
+};
+
+/*
+ * nss_wifili_jitter_tid_stats
+ *	Per TID jitter statistics.
+ */
+struct nss_wifili_jitter_tid_stats {
+	uint32_t avg_jitter;				/**< Average jitter. */
+	uint32_t avg_delay;				/**< Average delay. */
+	uint32_t avg_err;				/**< Average count error. */
+	uint32_t success;				/**< Transmit success count. */
+	uint32_t drop;					/**< Transmit drop count. */
+};
+
+/*
+ * nss_wifili_jitter_stats
+ *	Wifili jitter statistics.
+ */
+struct nss_wifili_jitter_stats {
+	uint32_t peer_id;		/**< Peer ID. */
+	struct nss_wifili_jitter_tid_stats stats[NSS_WIFILI_MAX_TID];	/**< Per-TID jitter statistics. */
+};
+
+/*
+ * nss_wifili_jitter_stats_msg
+ *	Wifili jitter message.
+ */
+struct nss_wifili_jitter_stats_msg {
+	uint32_t npeers;				/**< Number of peers. */
+	struct nss_wifili_jitter_stats jitter_stats[1];	/**< Jitter statistics. */
+};
+
+/**
+ * nss_wifili_wds_peer_msg
+ *	Wi-Fi Wireless distribution system (WDS) peer-specific message.
+ */
+struct nss_wifili_wds_peer_msg {
+	uint8_t dest_mac[ETH_ALEN];	/**< MAC address of the destination. */
+	uint8_t peer_mac[ETH_ALEN];	/**< MAC address of the base peer. */
+	uint8_t ast_type;		/**< AST (Address Search Table) type for this peer. */
+	uint8_t pdev_id;		/**< Radio ID for next hop peer. */
+	uint16_t peer_id;		/**< Peer ID of next hop peer. */
+};
+
+/**
+ * nss_wifili_peer_delay_stats
+ *	Per-peer delay statistics.
+ */
+struct nss_wifili_peer_delay_stats {
+        struct nss_wifili_delay_stats swq_delay;                    /**< Software enqueue delay. */
+        struct nss_wifili_delay_stats hwtx_delay;                   /**< Hardware transmit delay. */
+};
+
+/**
+ * nss_wifili_peer_ext_stats
+ *      Peer extended statistics.
+ */
+struct nss_wifili_peer_ext_stats {
+        uint32_t peer_id;                       /**< Peer ID. */
+        struct nss_wifili_peer_delay_stats delay_stats[NSS_WIFILI_MAX_TID];
+                                                /**< Delay statistics. */
+};
+
+/**
+ * nss_wifili_peer_ext_stats_msg
+ *      Peer extended statistics message.
+ */
+struct nss_wifili_peer_ext_stats_msg {
+        uint32_t npeers;                                /**< Number of peers. */
+        struct nss_wifili_peer_ext_stats ext_stats[1];      /**< Extended statistics. */
+};
+
+/**
+ * nss_wifili_stats_cfg_msg
+ *	Wifili stats enable/disable configuration message.
+ */
+struct nss_wifili_stats_cfg_msg {
+	uint32_t cfg;	/**< Enable or disable configuration. */
+};
+
+/**
+ * nss_wifili_wds_peer_map_msg
+ *	Wi-Fi Wireless distribution system(WDS) peer-specific message.
+ */
+struct nss_wifili_wds_peer_map_msg {
+	uint8_t dest_mac[ETH_ALEN];	/**< MAC address of the destination. */
+	uint16_t peer_id;		/**< Connected peer ID for this WDS peer. */
+	uint16_t ast_idx;		/**< AST (address search table) index for this peer in host. */
+	uint16_t vdev_id;;		/**< VAP ID. */
+};
+
+/**
+ * nss_wifili_wds_active_info
+ *	Wi-Fi WDS active information.
+ */
+struct nss_wifili_wds_active_info {
+	uint16_t ast_idx;	/**< Hardware AST index. */
+};
+
+/**
+ * nss_wifili_wds_active_info_msg
+ *	Wi-Fi Wireless distribution system active information message.
+ */
+struct nss_wifili_wds_active_info_msg {
+	uint16_t nentries;		/**< Number of WDS entries. */
+	struct nss_wifili_wds_active_info info[1];
+					/**< WDS active information. */
+};
+
+/**
+ * nss_wifili_mec_ageout_info
+ *	Wi-Fi multicast echo check ageout information.
+ */
+struct nss_wifili_mec_ageout_info {
+	uint8_t mac_addr[6];	/**< MAC address. */
+	uint8_t radio_id;		/**< Radio ID. */
+	uint8_t pad;			/**< Pad for word align structure. */
+
+};
+
+/**
+ * nss_wifili_mec_ageout_info_msg
+ *	Wi-Fi multicast echo check ageout information message.
+ */
+struct nss_wifili_mec_ageout_info_msg {
+	uint16_t nentries;				/**< Number of entries. */
+	struct nss_wifili_mec_ageout_info info[1];
+					/**<  Multicast echo check active information. */
+};
+
+/**
+ * nss_wifili_soc_linkdesc_buf_info_msg
+ *	Link descriptor buffer addresss information.
+ */
+struct nss_wifili_soc_linkdesc_buf_info_msg {
+	uint32_t buffer_addr_low;	/**< Link descriptor low address. */
+	uint32_t buffer_addr_high;	/**< Link descriptor high address. */
+};
+
+/**
+ * nss_wifili_peer_security_type_msg
+ *	Wifili security type message.
+ */
+struct nss_wifili_peer_security_type_msg {
+	uint16_t peer_id;			/**< Peer ID. */
+	uint8_t pkt_type;			/**< Unicast or broadcast packet type. */
+	uint8_t security_type;			/**< Security type. */
+	uint8_t mic_key[NSS_WIFILI_MIC_KEY_LEN];
+						/**< MIC key. */
+};
+
+/**
+ * nss_wifili_peer_nawds_enable_msg
+ *	Wifili NAWDS enable for this peer.
+ */
+struct nss_wifili_peer_nawds_enable_msg {
+	uint16_t peer_id;			/**< Peer ID. */
+	uint16_t is_nawds;			/**< Enable NAWDS on this peer. */
+};
+
+/**
+ * nss_wifili_peer_vlan_id_msg
+ *	Wifili peer VLAN ID message.
+ */
+struct nss_wifili_peer_vlan_id_msg {
+	uint16_t peer_id;			/**< Peer ID. */
+	uint16_t vlan_id;			/**< VLAN ID. */
+};
+
+/**
+ * nss_wifili_peer_isolation_msg
+ *	Wifili peer isolation message.
+ */
+struct nss_wifili_peer_isolation_msg {
+	uint16_t peer_id;			/**< Peer ID. */
+	uint16_t isolation;			/**< Isolation enabled/disabled. */
+};
+
+/**
+ * nss_wifili_dbdc_repeater_loop_detection_msg
+ *	Wifili DBDC repeater loop detection message.
+ */
+struct nss_wifili_dbdc_repeater_loop_detection_msg {
+	bool dbdc_loop_detected;		/**< DBDC repeater loop detection flag. */
+};
+
+/**
+ * nss_wifili_dbdc_repeater_set_msg
+ *	Wifili DBDC repeater set message.
+ */
+struct nss_wifili_dbdc_repeater_set_msg {
+	uint32_t is_dbdc_en;			/**< DBDC enable flag. */
+};
+
+/**
+ * nss_wifili_hmmc_dscp_tid_set_msg
+ *	Wifili Hy-Fi managed multicast DSCP TID set message.
+ */
+struct nss_wifili_hmmc_dscp_tid_set_msg {
+	uint16_t radio_id;			/**< Radio ID. */
+	uint16_t value;			        /**< Hy-Fi managed multicast TID value. */
+};
+
+/**
+ * nss_wifili_hmmc_dscp_override_set_msg
+ *	Wifili Hy-Fi managed multicast DSCP override set message.
+ */
+struct nss_wifili_hmmc_dscp_override_set_msg {
+	uint16_t radio_id;			/**< Radio ID. */
+	uint16_t value;			        /**< Hy-Fi managed multicast DSCP override value. */
+};
+
+/**
+ * nss_wifili_reo_tidq_msg
+ *	Rx reorder TID queue setup message.
+ */
+struct nss_wifili_reo_tidq_msg {
+	uint32_t tid;		/**< TID (traffic identification) value. */
+	uint16_t peer_id;	/**< Peer ID. */
+};
+
+/**
+ * nss_wifili_enable_v3_stats_msg
+ * 	Version 3 statistics enable message.
+ */
+struct nss_wifili_enable_v3_stats_msg {
+	uint32_t radio_id;	/**< Radio ID. */
+	uint32_t flag;		/**< Flag to enable version 3 statistics. */
+};
+
+/**
+ * nss_wifili_clr_stats_msg
+ *	NSS firmware statistics clear message.
+ */
+struct nss_wifili_clr_stats_msg {
+	uint8_t vdev_id;;	/**< VAP ID. */
+};
+
+/**
+ * nss_wifili_update_auth_flag
+ * 	Peer authentication flag message.
+ */
+struct nss_wifili_peer_update_auth_flag {
+	uint16_t peer_id;		/**< Peer ID. */
+	uint8_t auth_flag;		/**< Peer authentication flag. */
+	uint8_t reserved;		/**< Alignment padding. */
+};
+
+/**
+ * nss_wifili_update_pdev_lmac_id_msg
+ * 	Physical device ID and lower MAC ID update message.
+ */
+struct nss_wifili_update_pdev_lmac_id_msg {
+	uint32_t pdev_id;			/**< Physical device ID. */
+	uint32_t lmac_id;			/**< Lower MAC ID. */
+	uint32_t target_pdev_id;	/**< Target physical device ID. */
+};
+
+/**
+ * nss_wifili_radio_cmd_msg
+ * 	Wi-Fi radio specific special commands.
+ */
+struct nss_wifili_radio_cmd_msg {
+	enum nss_wifili_radio_cmd cmd;
+							/**< Type of command message. */
+	uint32_t value;			/**< Value of the command. */
+};
+
+/*
+ * nss_wifili_pdev_tx_capture_msg
+ *	Tx capture enable per pdev message.
+ */
+struct nss_wifili_pdev_tx_capture_msg {
+	uint8_t pdev_id;		/**< Physical device ID. */
+	uint8_t tx_cap_config;		/**< Flag to enable or disable Tx capture for physical device. */
+};
+
+/*
+ * nss_wifili_peer_tx_capture_msg
+ *	Tx capture enable per peer message.
+ */
+struct nss_wifili_peer_tx_capture_msg {
+	uint16_t peer_id;		/**< Peer ID. */
+	uint8_t tx_cap_config;		/**< Flag to enable or disable Tx capture for peer. */
+	uint8_t reserved;		/**< Reserved. */
+};
+
+/**
+ * nss_wifili_radio_buf_cfg_msg
+ *	Wi-Fi Radio buffer requirement configuration.
+ *
+ * Number of payloads needed in NSS for multi-client scenarios are configured
+ * from Wi-Fi driver as per following ranges:
+ * 0-64 peers range 1.
+ * 64-128 peers range 2.
+ * 128-256 peers range 3.
+ * >256 peers range 4.
+ * Number of payloads needed in for each peer range is configured by Wi-Fi driver
+ * for flexibility.
+ */
+struct nss_wifili_radio_buf_cfg_msg {
+	uint32_t buf_cnt;		/**< Number of buffers required. */
+	uint32_t range;			/**< Peer range. */
+};
+
+/**
+ * nss_wifili_radio_cfg_msg
+ *	Wi-Fi radio specific special configurations.
+ */
+struct nss_wifili_radio_cfg_msg {
+	uint32_t radio_if_num;	/**< NSS assigned interface number for radio. */
+
+	/**
+	 * Wi-Fi radio specific special command message.
+	 */
+	union {
+		struct nss_wifili_radio_cmd_msg radiocmdmsg;
+							/**< Radio specific commands. */
+		struct nss_wifili_radio_buf_cfg_msg radiobufcfgmsg;
+							/**< Radio specific buffer configurations. */
+	} radiomsg;	/**< Wi-Fi radio command message. */
+};
+
+/**
+ * struct wifili_peer_wds_4addr_allow_msg
+ *	Per-peer four address configuration message.
+ */
+struct nss_wifili_peer_wds_4addr_allow_msg {
+	uint32_t peer_id;	/**< Peer ID. */
+	uint32_t if_num;	/**< Associate virtual interface number. */
+	bool enable;		/**< Boolean flag to enable/disable four address frames. */
+};
+
+/**
+ * struct nss_wifili_mesh_capability_info
+ * 	Wi-Fi mesh capability flag.
+ */
+struct nss_wifili_mesh_capability_info {
+	bool mesh_enable;	/**< Wi-Fi mesh capability flag. */
+};
+
+/**
+ * nss_wifili_msg
+ *	Structure that describes wifili messages.
+ */
+struct nss_wifili_msg {
+	struct nss_cmn_msg cm;                  /**< Common message header. */
+
+	/**
+	 * Payload of wifili message.
+	 */
+	union {
+		struct nss_wifili_init_msg init;
+				/**< Wi-Fi initialization data. */
+		struct nss_wifili_pdev_init_msg pdevmsg;
+				/**< Tx initialization data. */
+		struct nss_wifili_pdev_deinit_msg pdevdeinit;
+				/**< Tx de-initialization data. */
+		struct nss_wifili_peer_msg peermsg;
+				/**< Peer-specific data for the physical device. */
+		struct nss_wifili_peer_freelist_append_msg peer_freelist_append;
+				/**< Information for creating a peer freelist. */
+		struct nss_wifili_stats_sync_msg wlsoc_stats;
+				/**< Synchronization statistics. */
+		struct nss_wifili_peer_stats_msg peer_stats;
+				/**< Wifili peer statistics. */
+		struct nss_wifili_wds_peer_msg wdspeermsg;
+				/**< WDS peer-specific message. */
+		struct nss_wifili_wds_peer_map_msg wdspeermapmsg;
+				/**< WDS peer-mapping specific message. */
+		struct nss_wifili_wds_active_info_msg wdsinfomsg;
+				/**< WDS active information specific message. */
+		struct nss_wifili_stats_cfg_msg scm;
+				/**< Wifili peer statistics configuration message. */
+		struct nss_wifili_reo_tidq_msg reotidqmsg;
+				/**< Rx reorder TID queue setup message. */
+		struct nss_wifili_radio_cfg_msg radiocfgmsg;
+				/**< Radio command message. */
+		struct nss_wifili_wds_extn_peer_cfg_msg wpeercfg;
+				/**< WDS vendor configuration message. */
+		struct nss_wifili_soc_linkdesc_buf_info_msg linkdescinfomsg;
+				/**< Link descriptor buffer address information. */
+		struct nss_wifili_peer_security_type_msg securitymsg;
+				/**< Wifili peer security message. */
+		struct nss_wifili_peer_nawds_enable_msg nawdsmsg;
+				/**< Wifili peer enable NAWDS message. */
+		struct nss_wifili_dbdc_repeater_set_msg dbdcrptrmsg;
+				/**< Wifili DBDC repeater enable message. */
+		struct nss_wifili_hmmc_dscp_override_set_msg shmmcdscpmsg;
+				/**< Wifili Hy-Fi managed multicast DSCP override set message. */
+		struct nss_wifili_hmmc_dscp_tid_set_msg shmmcdcptidmsg;
+				/**< Wifili Hy-Fi managed multicast DSCP TID map set message. */
+		struct nss_wifili_pdev_v3_tx_rx_stats_sync_msg v3_txrx_stats_msg;
+				/**< Wifili version 3 Tx and Rx statistics message. */
+		struct nss_wifili_pdev_v3_delay_stats_sync_msg v3_delay_stats_msg;
+				/**< Wifili version 3 delay statistics message. */
+		struct nss_wifili_enable_v3_stats_msg enablev3statsmsg;
+				/**< Wifili version 3 statistics enable message. */
+		struct nss_wifili_sojourn_stats_msg sj_stats_msg;
+				/**< Wifili sojourn statistics message. */
+		struct nss_wifili_peer_vlan_id_msg peervlan;
+				/**< Wifili peer VLAN ID message. */
+		struct nss_wifili_update_pdev_lmac_id_msg update_pdev_lmac_id_msg;
+				/**< Wifili peer update lower MAC ID message. */
+		struct nss_wifili_peer_ast_flowid_map_msg peer_ast_flowid_msg;
+				/**< Wifili peer AST index flow ID map message. */
+		struct nss_wifili_mec_ageout_info_msg mecagemsg;
+				/**< Multicast echo check active information specific message. */
+		struct nss_wifili_jitter_stats_msg jt_stats_msg;
+				/**<Jitter statistics message. */
+		struct nss_wifili_peer_isolation_msg isolation_msg;
+				/**< Peer isolation message. */
+				/**< Jitter statistics message. */
+		struct nss_wifili_peer_ext_stats_msg pext_msg;
+				/**< Peer extended statistics message. */
+		struct nss_wifili_clr_stats_msg clrstats;
+				/**< Clear NSS firmware statistics. */
+		struct nss_wifili_peer_wds_4addr_allow_msg wpswm;
+				/**< Peer four-address event message. */
+		struct nss_wifili_dbdc_repeater_loop_detection_msg wdrldm;
+				/**< Wifili DBDC repeater loop detection message. */
+		struct nss_wifili_peer_update_auth_flag peer_auth;
+				/**< Peer authentication flag message. */
+		struct nss_wifili_mesh_capability_info cap_info;
+				/**< Mesh capability flag. */
+		struct nss_wifili_pdev_tx_capture_msg pdevtxcapmsg;
+				/**< Wifili physical device Tx capture message. */
+		struct nss_wifili_peer_tx_capture_msg peertxcapmsg;
+				/**< Wifili peer Tx capture message. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * nss_wifili_tx_msg
+ *	Send wifili messages.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_wifili_msg
+ *
+ * @param[in] nss_ctx NSS context.
+ * @param[in] msg     NSS Wi-Fi message.
+ *
+ * @return
+ * nss_tx_status_t Tx status
+ */
+extern nss_tx_status_t nss_wifili_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_wifili_msg *msg);
+
+/**
+ * nss_wifili_tx_msg_sync
+ *	Send wifili messages synchronously.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_wifili_msg
+ *
+ * @param[in] nss_ctx NSS context.
+ * @param[in] msg     NSS Wi-Fi message.
+ *
+ * @return
+ * nss_tx_status_t Tx status.
+ */
+extern nss_tx_status_t nss_wifili_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_wifili_msg *msg);
+
+/**
+ * nss_wifili_msg_callback_t
+ *	Callback to receive wifili messages.
+ *
+ * @datatypes
+ * nss_wifili_msg
+ *
+ * @param[in] app_data Application context of the message.
+ * @param[in] msg      Message data.
+ *
+ * @return
+ * void
+ */
+typedef void (*nss_wifili_msg_callback_t)(void *app_data, struct nss_wifili_msg *msg);
+
+/**
+ * nss_wifili_callback_t
+ *	Callback to receive Wi-Fi data.
+ *
+ * @datatypes
+ * net_device \n
+ * sk_buff \n
+ * napi_struct
+ *
+ *
+ * @param[in] netdev  Pointer to the associated network device.
+ * @param[in] skb     Pointer to the data socket buffer.
+ * @param[in] napi    Pointer to the NAPI structure.
+ *
+ * @return
+ * void
+ */
+typedef void (*nss_wifili_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * nss_register_wifili_if
+ *	Register to send/receive wifili SoC messages to NSS.
+ *
+ * @datatypes
+ * nss_wifili_callback_t \n
+ * nss_wifili_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num             NSS interface number.
+ * @param[in] wifi_callback      Callback for the Wi-Fi virtual device data.
+ * @param[in] wifi_ext_callback  Callback for the extended data.
+ * @param[in] event_callback     Callback for the message.
+ * @param[in] netdev             Pointer to the associated network device.
+ * @param[in] features           Data socket buffer types supported by this
+ *                               interface.
+ *
+ * @return
+ * nss_ctx_instance* NSS context
+ */
+struct nss_ctx_instance *nss_register_wifili_if(uint32_t if_num, nss_wifili_callback_t wifi_callback,
+			nss_wifili_callback_t wifi_ext_callback, nss_wifili_msg_callback_t event_callback, struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_unregister_wifili_if
+ *	Deregister wifili SoC interface with NSS.
+ *
+ * @param[in] if_num NSS interface number.
+ *
+ * @return
+ * void
+ */
+void nss_unregister_wifili_if(uint32_t if_num);
+
+/**
+ * nss_register_wifili_radio_if
+ *	Register to send/receive wifili radio messages to NSS.
+ *
+ * @datatypes
+ * nss_wifili_callback_t \n
+ * nss_wifili_msg_callback_t \n
+ * net_device
+ *
+ * @param[in] if_num             NSS interface number.
+ * @param[in] wifi_callback      Callback for the Wi-Fi radio virtual device data.
+ * @param[in] wifi_ext_callback  Callback for the extended data.
+ * @param[in] event_callback     Callback for the message.
+ * @param[in] netdev             Pointer to the associated network device.
+ * @param[in] features           Data socket buffer types supported by this
+ *                               interface.
+ *
+ * @return
+ * nss_ctx_instance* NSS context
+ */
+struct nss_ctx_instance *nss_register_wifili_radio_if(uint32_t if_num, nss_wifili_callback_t wifi_callback,
+			nss_wifili_callback_t wifi_ext_callback, nss_wifili_msg_callback_t event_callback, struct net_device *netdev, uint32_t features);
+
+/**
+ * nss_unregister_wifili_radio_if
+ *	Deregister wifili radio interface with NSS.
+ *
+ * @param[in] if_num NSS interface number
+ *
+ * @return
+ * void
+ */
+void nss_unregister_wifili_radio_if(uint32_t if_num);
+
+/**
+ * nss_get_available_wifili_external_if
+ *	Check and return the available external interface.
+ *
+ * @return
+ * External interface number.
+ */
+nss_if_num_t nss_get_available_wifili_external_if(void);
+
+/**
+ * nss_wifili_release_external_if
+ *	Release the used interface number
+ *
+ * @datatypes
+ * nss_if_num
+ *
+ * @param[in] if_num             NSS interface number.
+ *
+ * @return
+ * void
+ */
+void nss_wifili_release_external_if(nss_if_num_t ifnum);
+
+/**
+ * nss_wifili_thread_scheme_alloc
+ *	Allocate thread scheme entry and return scheme index.
+ *
+ * @param[in] nss_ctx  NSS context pointer.
+ * @param[in] radio_ifnum  Radio interface number.
+ * @param[in] radio_priority  Radio Priority requested.
+ *
+ * @return
+ * uint8_t.
+ */
+uint8_t nss_wifili_thread_scheme_alloc(struct nss_ctx_instance *nss_ctx,
+				int32_t radio_ifnum,
+				uint32_t radio_priority);
+
+/**
+ * nss_wifili_thread_scheme_dealloc
+ *	Release thread scheme database entry.
+ *
+ * @param[in] nss_ctx  NSS context pointer.
+ * @param[in] radio_ifnum  Radio interface number.
+ *
+ * @return
+ * void.
+ */
+void nss_wifili_thread_scheme_dealloc(struct nss_ctx_instance *nss_ctx,
+				int32_t radio_ifnum);
+
+/**
+ * nss_wifili_get_radio_num
+ *    Get radio number.
+ *
+ * @param[in] nss_ctx  NSS context pointer.
+ *
+ * @return
+ * uint32_t.
+ */
+uint32_t nss_wifili_get_radio_num(struct nss_ctx_instance *nss_ctx);
+
+/**
+ * nss_wifili_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_wifili_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_wifili_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_wifili_stats_unregister_notifier(struct notifier_block *nb);
+
+#endif /*__KERNEL__ */
+
+/**
+ * @}
+ */
+
+#endif /* __NSS_WIFILI_H */
diff --git a/qca-nss-drv/nss_bridge.c b/qca-nss-drv/nss_bridge.c
new file mode 100644
index 0000000..379a307
--- /dev/null
+++ b/qca-nss-drv/nss_bridge.c
@@ -0,0 +1,501 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_bridge_log.h"
+
+#define NSS_BRIDGE_TX_TIMEOUT 1000 /* 1 Second */
+
+/*
+ * Private data structure
+ */
+static struct nss_bridge_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+	void *cb;
+	void *app_data;
+} bridge_pvt;
+
+/*
+ * nss_bridge_handler()
+ * 	Handle NSS -> HLOS messages for bridge
+ */
+static void nss_bridge_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, void *app_data)
+{
+	struct nss_bridge_msg *nbm = (struct nss_bridge_msg *)ncm;
+	nss_bridge_msg_callback_t cb;
+
+	BUG_ON(!nss_is_dynamic_interface(ncm->interface));
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_BRIDGE_MSG_TYPE_MAX) {
+		nss_warning("%px: received invalid message %d for bridge interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_bridge_msg)) {
+		nss_warning("%px: length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Trace Messages
+	 */
+	nss_bridge_log_rx_msg(nbm);
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, IPv4 sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->bridge_callback;
+		ncm->app_data = (nss_ptr_t)nss_ctx->nss_top->bridge_ctx;
+	}
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_bridge_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, nbm);
+}
+
+/*
+ * nss_bridge_get_context()
+ */
+struct nss_ctx_instance *nss_bridge_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.bridge_handler_id];
+}
+EXPORT_SYMBOL(nss_bridge_get_context);
+
+/*
+ * nss_bridge_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_bridge_callback(void *app_data, struct nss_bridge_msg *nbm)
+{
+	nss_bridge_msg_callback_t callback = (nss_bridge_msg_callback_t)bridge_pvt.cb;
+	void *data = bridge_pvt.app_data;
+
+	bridge_pvt.response = NSS_TX_SUCCESS;
+	bridge_pvt.cb = NULL;
+	bridge_pvt.app_data = NULL;
+
+	if (nbm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("bridge error response %d\n", nbm->cm.response);
+		bridge_pvt.response = nbm->cm.response;
+	}
+
+	if (callback) {
+		callback(data, nbm);
+	}
+	complete(&bridge_pvt.complete);
+}
+
+/*
+ * nss_bridge_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+bool nss_bridge_verify_if_num(uint32_t if_num)
+{
+	if (nss_is_dynamic_interface(if_num) == false) {
+		return false;
+	}
+
+	if (nss_dynamic_interface_get_type(nss_bridge_get_context(), if_num) != NSS_DYNAMIC_INTERFACE_TYPE_BRIDGE) {
+		return false;
+	}
+
+	return true;
+}
+EXPORT_SYMBOL(nss_bridge_verify_if_num);
+
+/*
+ * nss_bridge_tx_msg()
+ *	Transmit a bridge message to NSSFW
+ */
+nss_tx_status_t nss_bridge_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_bridge_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!nss_is_dynamic_interface(ncm->interface)) {
+		nss_warning("%px: tx request for interface that is not a bridge: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_BRIDGE_MSG_TYPE_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Trace Messages
+	 */
+	nss_bridge_log_tx_msg(msg);
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_bridge_tx_msg);
+
+/*
+ * nss_bridge_tx_msg_sync()
+ *	Transmit a bridge message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_bridge_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_bridge_msg *nbm)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&bridge_pvt.sem);
+	bridge_pvt.cb = (void *)nbm->cm.cb;
+	bridge_pvt.app_data = (void *)nbm->cm.app_data;
+
+	nbm->cm.cb = (nss_ptr_t)nss_bridge_callback;
+	nbm->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_bridge_tx_msg(nss_ctx, nbm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: bridge_tx_msg failed\n", nss_ctx);
+		up(&bridge_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&bridge_pvt.complete, msecs_to_jiffies(NSS_BRIDGE_TX_TIMEOUT));
+
+	if (!ret) {
+		nss_warning("%px: bridge msg tx failed due to timeout\n", nss_ctx);
+		bridge_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = bridge_pvt.response;
+	up(&bridge_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_bridge_tx_msg_sync);
+
+/*
+ * nss_bridge_msg_init()
+ *	Initialize nss_bridge_msg.
+ */
+void nss_bridge_msg_init(struct nss_bridge_msg *ncm, uint16_t if_num, uint32_t type, uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+EXPORT_SYMBOL(nss_bridge_msg_init);
+
+/*
+ * nss_bridge_tx_vsi_assign_msg
+ *	API to send vsi assign message to NSS FW
+ */
+nss_tx_status_t nss_bridge_tx_vsi_assign_msg(uint32_t if_num, uint32_t vsi)
+{
+	struct nss_ctx_instance *nss_ctx = nss_bridge_get_context();
+	struct nss_bridge_msg nbm;
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	if (nss_bridge_verify_if_num(if_num) == false) {
+		nss_warning("%px: invalid interface %d", nss_ctx, if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	nss_bridge_msg_init(&nbm, if_num, NSS_IF_VSI_ASSIGN,
+			sizeof(struct nss_if_vsi_assign), NULL, NULL);
+
+	nbm.msg.if_msg.vsi_assign.vsi = vsi;
+
+	return nss_bridge_tx_msg_sync(nss_ctx, &nbm);
+}
+EXPORT_SYMBOL(nss_bridge_tx_vsi_assign_msg);
+
+/*
+ * nss_bridge_tx_vsi_unassign_msg
+ *	API to send vsi unassign message to NSS FW
+ */
+nss_tx_status_t nss_bridge_tx_vsi_unassign_msg(uint32_t if_num, uint32_t vsi)
+{
+	struct nss_ctx_instance *nss_ctx = nss_bridge_get_context();
+	struct nss_bridge_msg nbm;
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	if (nss_bridge_verify_if_num(if_num) == false) {
+		nss_warning("%px: invalid interface %d", nss_ctx, if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	nss_bridge_msg_init(&nbm, if_num, NSS_IF_VSI_UNASSIGN,
+			sizeof(struct nss_if_vsi_unassign), NULL, NULL);
+
+	nbm.msg.if_msg.vsi_unassign.vsi = vsi;
+
+	return nss_bridge_tx_msg_sync(nss_ctx, &nbm);
+}
+EXPORT_SYMBOL(nss_bridge_tx_vsi_unassign_msg);
+
+/*
+ * nss_bridge_tx_change_mtu_msg
+ *	API to send change mtu message to NSS FW
+ */
+nss_tx_status_t nss_bridge_tx_set_mtu_msg(uint32_t bridge_if_num, uint32_t mtu)
+{
+	struct nss_ctx_instance *nss_ctx = nss_bridge_get_context();
+	struct nss_bridge_msg nbm;
+	struct nss_if_mtu_change *nimc;
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	if (nss_bridge_verify_if_num(bridge_if_num) == false) {
+		nss_warning("%px: received invalid interface %d", nss_ctx, bridge_if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	nss_bridge_msg_init(&nbm, bridge_if_num, NSS_IF_MTU_CHANGE,
+			sizeof(struct nss_if_mtu_change), NULL, NULL);
+
+	nimc = &nbm.msg.if_msg.mtu_change;
+	nimc->min_buf_size = (uint16_t)mtu;
+
+	return nss_bridge_tx_msg_sync(nss_ctx, &nbm);
+}
+EXPORT_SYMBOL(nss_bridge_tx_set_mtu_msg);
+
+/*
+ * nss_bridge_tx_set_mac_addr_msg
+ *	API to send change mac addr message to NSS FW
+ */
+nss_tx_status_t nss_bridge_tx_set_mac_addr_msg(uint32_t bridge_if_num, uint8_t *addr)
+{
+	struct nss_ctx_instance *nss_ctx = nss_bridge_get_context();
+	struct nss_bridge_msg nbm;
+	struct nss_if_mac_address_set *nmas;
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	if (nss_bridge_verify_if_num(bridge_if_num) == false) {
+		nss_warning("%px: received invalid interface %d", nss_ctx, bridge_if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	nss_bridge_msg_init(&nbm, bridge_if_num, NSS_IF_MAC_ADDR_SET,
+			sizeof(struct nss_if_mac_address_set), NULL, NULL);
+
+	nmas = &nbm.msg.if_msg.mac_address_set;
+	memcpy(nmas->mac_addr, addr, ETH_ALEN);
+	return nss_bridge_tx_msg_sync(nss_ctx, &nbm);
+}
+EXPORT_SYMBOL(nss_bridge_tx_set_mac_addr_msg);
+
+/*
+ * nss_bridge_tx_join_msg
+ *	API to send slave join message to NSS FW
+ */
+nss_tx_status_t nss_bridge_tx_join_msg(uint32_t bridge_if_num, struct net_device *netdev)
+{
+	struct nss_ctx_instance *nss_ctx = nss_bridge_get_context();
+	struct nss_bridge_msg nbm;
+	uint32_t slave_if_num;
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	if (nss_bridge_verify_if_num(bridge_if_num) == false) {
+		nss_warning("%px: received invalid interface %d\n", nss_ctx, bridge_if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	slave_if_num = nss_cmn_get_interface_number_by_dev(netdev);
+	if (slave_if_num < 0) {
+		nss_warning("%px: invalid slave device %px\n", nss_ctx, netdev);
+		return NSS_TX_FAILURE;
+	}
+
+	nbm.msg.br_join.if_num = slave_if_num;
+	nss_bridge_msg_init(&nbm, bridge_if_num, NSS_BRIDGE_MSG_JOIN,
+				sizeof(struct nss_bridge_join_msg), NULL, NULL);
+
+	return nss_bridge_tx_msg_sync(nss_ctx, &nbm);
+}
+EXPORT_SYMBOL(nss_bridge_tx_join_msg);
+
+/*
+ * nss_bridge_tx_leave_msg
+ *	API to send slave leave message to NSS FW
+ */
+nss_tx_status_t nss_bridge_tx_leave_msg(uint32_t bridge_if_num, struct net_device *netdev)
+{
+	struct nss_ctx_instance *nss_ctx = nss_bridge_get_context();
+	struct nss_bridge_msg nbm;
+	uint32_t slave_if_num;
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	if (nss_bridge_verify_if_num(bridge_if_num) == false) {
+		nss_warning("%px: received invalid interface %d\n", nss_ctx, bridge_if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	slave_if_num = nss_cmn_get_interface_number_by_dev(netdev);
+	if (slave_if_num < 0) {
+		nss_warning("%px: invalid slave device %px\n", nss_ctx, netdev);
+		return NSS_TX_FAILURE;
+	}
+
+	nbm.msg.br_leave.if_num = slave_if_num;
+	nss_bridge_msg_init(&nbm, bridge_if_num, NSS_BRIDGE_MSG_LEAVE,
+				sizeof(struct nss_bridge_leave_msg), NULL, NULL);
+
+	return nss_bridge_tx_msg_sync(nss_ctx, &nbm);
+}
+EXPORT_SYMBOL(nss_bridge_tx_leave_msg);
+
+/*
+ * nss_bridge_tx_set_fdb_learn_msg
+ *	API to send FDB learn message to NSS FW
+ */
+nss_tx_status_t nss_bridge_tx_set_fdb_learn_msg(uint32_t bridge_if_num, enum nss_bridge_fdb_learn_mode fdb_learn)
+{
+	struct nss_ctx_instance *nss_ctx = nss_bridge_get_context();
+	struct nss_bridge_msg nbm;
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	if (nss_bridge_verify_if_num(bridge_if_num) == false) {
+		nss_warning("%px: received invalid interface %d\n", nss_ctx, bridge_if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	if (fdb_learn >= NSS_BRIDGE_FDB_LEARN_MODE_MAX) {
+		nss_warning("%px: received invalid fdb learn mode %d\n", nss_ctx, fdb_learn);
+		return NSS_TX_FAILURE;
+	}
+
+	nss_bridge_msg_init(&nbm, bridge_if_num, NSS_BRIDGE_MSG_SET_FDB_LEARN,
+				sizeof(struct nss_bridge_set_fdb_learn_msg), NULL, NULL);
+
+	nbm.msg.fdb_learn.mode = fdb_learn;
+
+	return nss_bridge_tx_msg_sync(nss_ctx, &nbm);
+}
+EXPORT_SYMBOL(nss_bridge_tx_set_fdb_learn_msg);
+
+/*
+ * nss_bridge_init()
+ */
+void nss_bridge_init(void)
+{
+	sema_init(&bridge_pvt.sem, 1);
+	init_completion(&bridge_pvt.complete);
+}
+
+/*
+ * nss_bridge_unregister()
+ */
+void nss_bridge_unregister(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_bridge_get_context();
+
+	nss_assert(nss_bridge_verify_if_num(if_num));
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	nss_top_main.bridge_callback = NULL;
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_bridge_unregister);
+
+/*
+ * nss_bridge_register()
+ */
+struct nss_ctx_instance *nss_bridge_register(uint32_t if_num, struct net_device *netdev,
+						nss_bridge_callback_t bridge_data_cb,
+						nss_bridge_msg_callback_t bridge_msg_cb,
+						uint32_t features,
+						void *app_data)
+{
+	struct nss_ctx_instance *nss_ctx = nss_bridge_get_context();
+
+	nss_assert(nss_bridge_verify_if_num(if_num));
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, bridge_data_cb, NULL, app_data, netdev, features);
+
+	nss_top_main.bridge_callback = bridge_msg_cb;
+
+	nss_core_register_handler(nss_ctx, if_num, nss_bridge_handler, app_data);
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_bridge_register);
+
+/*
+ * nss_bridge_notify_register()
+ *	Register to receive bridge notify messages.
+ */
+struct nss_ctx_instance *nss_bridge_notify_register(nss_bridge_msg_callback_t cb, void *app_data)
+{
+	nss_top_main.bridge_callback = cb;
+	nss_top_main.bridge_ctx = app_data;
+	return nss_bridge_get_context();
+}
+EXPORT_SYMBOL(nss_bridge_notify_register);
+
+/*
+ * nss_bridge_notify_unregister()
+ *	Unregister to receive bridge notify messages.
+ */
+void nss_bridge_notify_unregister(void)
+{
+	nss_top_main.bridge_callback = NULL;
+}
+EXPORT_SYMBOL(nss_bridge_notify_unregister);
diff --git a/qca-nss-drv/nss_bridge_log.c b/qca-nss-drv/nss_bridge_log.c
new file mode 100644
index 0000000..3b0cf1e
--- /dev/null
+++ b/qca-nss-drv/nss_bridge_log.c
@@ -0,0 +1,135 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_bridge_log.c
+ *	NSS Bridge logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_bridge_log_message_types_str
+ *	NSS Bridge message strings
+ */
+static int8_t *nss_bridge_log_message_types_str[NSS_BRIDGE_MSG_TYPE_MAX] __maybe_unused = {
+	"Bridge Join message",
+	"Bridge Leave message",
+	"Bridge Set FDB Learn message"
+};
+
+/*
+ * nss_bridge_join_msg()
+ *	Log NSS Bridge Join message.
+ */
+static void nss_bridge_join_msg(struct nss_bridge_msg *nbm)
+{
+	struct nss_bridge_join_msg *nbjm __maybe_unused = &nbm->msg.br_join;
+	nss_trace("%px: NSS Bridge Join message \n"
+		"Interface Number: %d\n",
+		nbm, nbjm->if_num);
+}
+
+/*
+ * nss_bridge_leave_msg()
+ *	Log NSS Bridge Leave message.
+ */
+static void nss_bridge_leave_msg(struct nss_bridge_msg *nbm)
+{
+	struct nss_bridge_leave_msg *nblm __maybe_unused = &nbm->msg.br_leave;
+	nss_trace("%px: NSS Bridge Leave message: \n"
+		"Interface Number: %d\n",
+		nbm, nblm->if_num);
+}
+
+/*
+ * nss_bridge_fdb_learn_msg()
+ *	Log NSS Set Bridge FDB Learn message.
+ */
+static void nss_bridge_fdb_learn_msg(struct nss_bridge_msg *nbm)
+{
+	struct nss_bridge_set_fdb_learn_msg *nbflm __maybe_unused =
+		&nbm->msg.fdb_learn;
+	nss_trace("%px: NSS Bridge Set FDB Learn message: \n"
+		"Mode: %d\n",
+		nbm, nbflm->mode);
+}
+
+/*
+ * nss_bridge_log_verbose()
+ *	Log message contents.
+ */
+static void nss_bridge_log_verbose(struct nss_bridge_msg *nbm)
+{
+	switch (nbm->cm.type) {
+	case NSS_BRIDGE_MSG_JOIN:
+		nss_bridge_join_msg(nbm);
+		break;
+
+	case NSS_BRIDGE_MSG_LEAVE:
+		nss_bridge_leave_msg(nbm);
+		break;
+
+	case NSS_BRIDGE_MSG_SET_FDB_LEARN:
+		nss_bridge_fdb_learn_msg(nbm);
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", nbm);
+		break;
+	}
+}
+
+/*
+ * nss_bridge_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_bridge_log_tx_msg(struct nss_bridge_msg *nbm)
+{
+	if (nbm->cm.type >= NSS_BRIDGE_MSG_TYPE_MAX) {
+		nss_warning("%px: Invalid message type\n", nbm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nbm, nbm->cm.type, nss_bridge_log_message_types_str[nbm->cm.type - NSS_IF_MAX_MSG_TYPES - 1]);
+	nss_bridge_log_verbose(nbm);
+}
+
+/*
+ * nss_bridge_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_bridge_log_rx_msg(struct nss_bridge_msg *nbm)
+{
+	if (nbm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", nbm);
+		return;
+	}
+
+	if (nbm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nbm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nbm, nbm->cm.type,
+			nss_bridge_log_message_types_str[nbm->cm.type - NSS_IF_MAX_MSG_TYPES - 1],
+			nbm->cm.response, nss_cmn_response_str[nbm->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		nbm, nbm->cm.type, nss_bridge_log_message_types_str[nbm->cm.type - NSS_IF_MAX_MSG_TYPES - 1],
+		nbm->cm.response, nss_cmn_response_str[nbm->cm.response]);
+
+verbose:
+	nss_bridge_log_verbose(nbm);
+}
diff --git a/qca-nss-drv/nss_bridge_log.h b/qca-nss-drv/nss_bridge_log.h
new file mode 100644
index 0000000..af9a5f7
--- /dev/null
+++ b/qca-nss-drv/nss_bridge_log.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_BRIDGE_LOG_H
+#define __NSS_BRIDGE_LOG_H
+
+/*
+ * nss_bridge.h
+ *	NSS Bridge header file.
+ */
+
+/*
+ * Logger APIs
+ */
+
+/*
+ * nss_bridge_log_tx_msg
+ *	Logs a bridge message that is sent to the NSS firmware.
+ */
+void nss_bridge_log_tx_msg(struct nss_bridge_msg *nbm);
+
+/*
+ * nss_bridge_log_rx_msg
+ *	Logs a bridge message that is received from the NSS firmware.
+ */
+void nss_bridge_log_rx_msg(struct nss_bridge_msg *nbm);
+
+#endif /* __NSS_BRIDGE_LOG_H */
diff --git a/qca-nss-drv/nss_c2c_rx.c b/qca-nss-drv/nss_c2c_rx.c
new file mode 100644
index 0000000..4a1d5f8
--- /dev/null
+++ b/qca-nss-drv/nss_c2c_rx.c
@@ -0,0 +1,113 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_c2c_rx.c
+ *	NSS C2C_RX APIs
+ */
+
+#include <nss_hal.h>
+#include "nss_c2c_rx_stats.h"
+#include "nss_c2c_rx_strings.h"
+
+/*
+ * nss_c2c_rx_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static bool nss_c2c_rx_verify_if_num(uint32_t if_num)
+{
+	return if_num == NSS_C2C_RX_INTERFACE;
+}
+
+/*
+ * nss_c2c_rx_interface_handler()
+ *	Handle NSS -> HLOS messages for C2C_RX Statistics
+ */
+static void nss_c2c_rx_interface_handler(struct nss_ctx_instance *nss_ctx,
+		struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_c2c_rx_msg *ncrm = (struct nss_c2c_rx_msg *)ncm;
+	nss_c2c_rx_msg_callback_t cb;
+
+	if (!nss_c2c_rx_verify_if_num(ncm->interface)) {
+		nss_warning("%px: invalid interface %d for c2c_tx\n", nss_ctx, ncm->interface);
+		return;
+	}
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_C2C_RX_MSG_TYPE_MAX) {
+		nss_warning("%px: received invalid message %d for c2c_rx", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_c2c_rx_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	switch (ncrm->cm.type) {
+	case NSS_C2C_RX_MSG_TYPE_STATS:
+		/*
+		 * Update driver statistics and send statistics notifications to the registered modules.
+		 */
+		nss_c2c_rx_stats_sync(nss_ctx, &ncrm->msg.stats);
+		nss_c2c_rx_stats_notify(nss_ctx);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages
+	 * TODO: Add notify callbacks for c2c_rx
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		return;
+	}
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_c2c_rx_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, ncrm);
+}
+
+/*
+ * nss_c2c_rx_register_handler()
+ *	Register handler for messaging
+ */
+void nss_c2c_rx_register_handler(struct nss_ctx_instance *nss_ctx)
+{
+	nss_core_register_handler(nss_ctx, NSS_C2C_RX_INTERFACE, nss_c2c_rx_interface_handler, NULL);
+
+	if (nss_ctx->id == NSS_CORE_0) {
+		nss_c2c_rx_stats_dentry_create();
+	}
+	nss_c2c_rx_strings_dentry_create();
+}
+EXPORT_SYMBOL(nss_c2c_rx_register_handler);
diff --git a/qca-nss-drv/nss_c2c_rx_stats.c b/qca-nss-drv/nss_c2c_rx_stats.c
new file mode 100644
index 0000000..d9ea316
--- /dev/null
+++ b/qca-nss-drv/nss_c2c_rx_stats.c
@@ -0,0 +1,173 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_c2c_rx_stats.h"
+#include "nss_c2c_rx_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_c2c_rx_stats_notifier);
+
+/*
+ * Spinlock to protect C2C_RX statistics update/read
+ */
+DEFINE_SPINLOCK(nss_c2c_rx_stats_lock);
+
+/*
+ * nss_c2c_rx_stats
+ *	c2c_rx statistics
+ */
+uint64_t nss_c2c_rx_stats[NSS_MAX_CORES][NSS_C2C_RX_STATS_MAX];
+
+/*
+ * nss_c2c_rx_stats_read()
+ *	Read C2C_RX statistics
+ */
+static ssize_t nss_c2c_rx_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i, core;
+
+	/*
+	 * Max output lines = #stats * NSS_MAX_CORES  +
+	 * few blank lines for banner printing + Number of Extra outputlines for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_C2C_RX_STATS_MAX * NSS_MAX_CORES + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return -ENOMEM;
+	}
+
+	stats_shadow = kzalloc(NSS_C2C_RX_STATS_MAX * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return -ENOMEM;
+	}
+
+	/*
+	 * C2C_RX statistics
+	 */
+	for (core = 0; core < NSS_MAX_CORES; core++) {
+		spin_lock_bh(&nss_c2c_rx_stats_lock);
+		for (i = 0; i < NSS_C2C_RX_STATS_MAX; i++) {
+			stats_shadow[i] = nss_c2c_rx_stats[core][i];
+		}
+		spin_unlock_bh(&nss_c2c_rx_stats_lock);
+		size_wr += nss_stats_banner(lbuf, size_wr, size_al, "c2c_rx", core);
+		size_wr += nss_stats_print("c2c_rx", NULL, NSS_STATS_SINGLE_INSTANCE
+						, nss_c2c_rx_strings_stats
+						, stats_shadow
+						, NSS_C2C_RX_STATS_MAX
+						, lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_c2c_rx_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(c2c_rx);
+
+/*
+ * nss_c2c_rx_stats_dentry_create()
+ *	Create C2C_RX statistics debug entry.
+ */
+void nss_c2c_rx_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("c2c_rx", &nss_c2c_rx_stats_ops);
+}
+
+/*
+ * nss_c2c_rx_stats_sync()
+ *	Handle the syncing of NSS C2C_RX statistics.
+ */
+void nss_c2c_rx_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_c2c_rx_stats *ncrs)
+{
+	int id = nss_ctx->id;
+	int j;
+
+	spin_lock_bh(&nss_c2c_rx_stats_lock);
+
+	/*
+	 * Common node stats
+	 */
+	nss_c2c_rx_stats[id][NSS_STATS_NODE_RX_PKTS] += (ncrs->pbuf_simple + ncrs->pbuf_sg + ncrs->pbuf_returning);
+	nss_c2c_rx_stats[id][NSS_STATS_NODE_RX_BYTES] += ncrs->node_stats.rx_bytes;
+	nss_c2c_rx_stats[id][NSS_STATS_NODE_TX_PKTS] += ncrs->node_stats.tx_packets;
+	nss_c2c_rx_stats[id][NSS_STATS_NODE_TX_BYTES] += ncrs->node_stats.tx_bytes;
+
+	for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+		nss_c2c_rx_stats[id][NSS_STATS_NODE_RX_QUEUE_0_DROPPED + j] += ncrs->node_stats.rx_dropped[j];
+	}
+
+	/*
+	 * C2C_RX statistics
+	 */
+	nss_c2c_rx_stats[id][NSS_C2C_RX_STATS_PBUF_SIMPLE] += ncrs->pbuf_simple;
+	nss_c2c_rx_stats[id][NSS_C2C_RX_STATS_PBUF_SG] += ncrs->pbuf_sg;
+	nss_c2c_rx_stats[id][NSS_C2C_RX_STATS_PBUF_RETURNING] += ncrs->pbuf_returning;
+	nss_c2c_rx_stats[id][NSS_C2C_RX_STATS_INVAL_DEST] += ncrs->inval_dest;
+
+	spin_unlock_bh(&nss_c2c_rx_stats_lock);
+}
+
+/*
+ * nss_c2c_rx_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_c2c_rx_stats_notify(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_c2c_rx_stats_notification c2c_rx_stats;
+
+	c2c_rx_stats.core_id = nss_ctx->id;
+	memcpy(c2c_rx_stats.stats, nss_c2c_rx_stats[c2c_rx_stats.core_id], sizeof(c2c_rx_stats.stats));
+	atomic_notifier_call_chain(&nss_c2c_rx_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&c2c_rx_stats);
+}
+
+/*
+ * nss_c2c_rx_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_c2c_rx_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_c2c_rx_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_c2c_rx_stats_register_notifier);
+
+/*
+ * nss_c2c_rx_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_c2c_rx_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_c2c_rx_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_c2c_rx_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_c2c_rx_stats.h b/qca-nss-drv/nss_c2c_rx_stats.h
new file mode 100644
index 0000000..c53d080
--- /dev/null
+++ b/qca-nss-drv/nss_c2c_rx_stats.h
@@ -0,0 +1,63 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_C2C_RX_STATS_H
+#define __NSS_C2C_RX_STATS_H
+
+#include <nss_cmn.h>
+
+/*
+ * c2c_rx_msg_type
+ *	Message types supported
+ */
+enum c2c_rx_msg_type {
+	NSS_C2C_RX_MSG_TYPE_STATS,		/* Statistics synchronization */
+	NSS_C2C_RX_MSG_TYPE_MAX
+};
+
+/*
+ * nss_c2c_rx_stats
+ *	The NSS c2c_rx node stats structure.
+ */
+struct nss_c2c_rx_stats {
+	struct nss_cmn_node_stats node_stats;
+					/* Common node stats for core-to-core reception. */
+	uint32_t pbuf_simple;		/* Number of received simple pbuf. */
+	uint32_t pbuf_sg;		/* Number of S/G pbuf received. */
+	uint32_t pbuf_returning;	/* Number of returning S/G pbuf. */
+	uint32_t inval_dest;		/* Number of pbuf enqueue failure because of dest is invalid. */
+};
+
+/*
+ * nss_c2c_rx_msg
+ *	Message structure to send/receive c2c_rx commands
+ */
+struct nss_c2c_rx_msg {
+	struct nss_cmn_msg cm;			/* Message Header */
+	union {
+		struct nss_c2c_rx_stats stats;	/* c2c_rx statistics */
+	} msg;
+};
+
+/*
+ * C2C_RX statistics APIs
+ */
+extern void nss_c2c_rx_stats_notify(struct nss_ctx_instance *nss_ctx);
+typedef void (*nss_c2c_rx_msg_callback_t)(void *app_data, struct nss_c2c_rx_msg *msg);
+extern void nss_c2c_rx_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_c2c_rx_stats *ncrs);
+extern void nss_c2c_rx_stats_dentry_create(void);
+
+#endif /* __NSS_C2C_RX_STATS_H */
diff --git a/qca-nss-drv/nss_c2c_rx_strings.c b/qca-nss-drv/nss_c2c_rx_strings.c
new file mode 100644
index 0000000..c20754d
--- /dev/null
+++ b/qca-nss-drv/nss_c2c_rx_strings.c
@@ -0,0 +1,61 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+
+/*
+ * nss_c2c_rx_strings_stats
+ *	Core-to-core Rx statistics strings.
+ */
+struct nss_stats_info nss_c2c_rx_strings_stats[NSS_C2C_RX_STATS_MAX] = {
+	{"rx_pkts"		, NSS_STATS_TYPE_COMMON},
+	{"rx_byts"		, NSS_STATS_TYPE_COMMON},
+	{"tx_pkts"		, NSS_STATS_TYPE_COMMON},
+	{"tx_byts"		, NSS_STATS_TYPE_COMMON},
+	{"rx_queue[0]_drops"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue[1]_drops"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue[2]_drops"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue[3]_drops"	, NSS_STATS_TYPE_DROP},
+	{"pbuf_simple"		, NSS_STATS_TYPE_SPECIAL},
+	{"pbuf_sg"		, NSS_STATS_TYPE_SPECIAL},
+	{"pbuf_returning"	, NSS_STATS_TYPE_SPECIAL},
+	{"inval_dest"		, NSS_STATS_TYPE_DROP}
+};
+
+/*
+ * nss_c2c_rx_strings_read()
+ *	Read C2C Rx node statistics names.
+ */
+static ssize_t nss_c2c_rx_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_c2c_rx_strings_stats, NSS_C2C_RX_STATS_MAX);
+}
+
+/*
+ * nss_c2c_rx_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(c2c_rx);
+
+/*
+ * nss_c2c_rx_strings_dentry_create()
+ *	Create C2C Rx statistics strings debug entry.
+ */
+void nss_c2c_rx_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("c2c_rx", &nss_c2c_rx_strings_ops);
+}
diff --git a/qca-nss-drv/nss_c2c_rx_strings.h b/qca-nss-drv/nss_c2c_rx_strings.h
new file mode 100644
index 0000000..3810f11
--- /dev/null
+++ b/qca-nss-drv/nss_c2c_rx_strings.h
@@ -0,0 +1,23 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_C2C_RX_STRINGS_H
+#define __NSS_C2C_RX_STRINGS_H
+
+extern struct nss_stats_info nss_c2c_rx_strings_stats[NSS_C2C_RX_STATS_MAX];
+extern void nss_c2c_rx_strings_dentry_create(void);
+
+#endif /* __NSS_C2C_RX_STRINGS_H */
diff --git a/qca-nss-drv/nss_c2c_tx.c b/qca-nss-drv/nss_c2c_tx.c
new file mode 100644
index 0000000..244f459
--- /dev/null
+++ b/qca-nss-drv/nss_c2c_tx.c
@@ -0,0 +1,439 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_c2c_tx.c
+ *	NSS C2C_TX APIs
+ */
+
+#include <nss_hal.h>
+#include "nss_c2c_tx_stats.h"
+#include "nss_c2c_tx_log.h"
+#include "nss_c2c_tx_strings.h"
+
+int nss_c2c_tx_test_id = -1;
+
+/*
+ * Private data structure.
+ */
+struct nss_c2c_tx_pvt {
+	struct semaphore sem;		/* Semaphore structure. */
+	struct completion complete;	/* Completion structure. */
+	int response;			/* Response from FW. */
+	void *cb;			/* Original cb for sync msgs. */
+	void *app_data;			/* Original app_data for sync msgs. */
+};
+
+/*
+ * Notify data structure
+ */
+struct nss_c2c_tx_notify_data {
+	nss_c2c_tx_msg_callback_t c2c_tx_callback;
+	void *app_data;
+};
+
+static struct nss_c2c_tx_notify_data nss_c2c_tx_notify[NSS_CORE_MAX];
+static struct nss_c2c_tx_pvt nss_c2c_tx_cfg_pvt;
+
+/*
+ * nss_c2c_tx_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static inline bool nss_c2c_tx_verify_if_num(uint32_t if_num)
+{
+	return if_num == NSS_C2C_TX_INTERFACE;
+}
+
+/*
+ * nss_c2c_tx_interface_handler()
+ *	Handle NSS -> HLOS messages for C2C_TX Statistics
+ */
+static void nss_c2c_tx_msg_handler(struct nss_ctx_instance *nss_ctx,
+		struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_c2c_tx_msg *nctm = (struct nss_c2c_tx_msg *)ncm;
+	nss_c2c_tx_msg_callback_t cb;
+
+	if (!nss_c2c_tx_verify_if_num(ncm->interface)) {
+		nss_warning("%px: invalid interface %d for c2c_tx\n", nss_ctx, ncm->interface);
+		return;
+	}
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_C2C_TX_MSG_TYPE_MAX) {
+		nss_warning("%px: received invalid message %d for c2c_tx", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_c2c_tx_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_c2c_tx_log_rx_msg(nctm);
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	switch (nctm->cm.type) {
+	case NSS_C2C_TX_MSG_TYPE_TX_MAP:
+	case NSS_C2C_TX_MSG_TYPE_PERFORMANCE_TEST:
+		break;
+
+	case NSS_C2C_TX_MSG_TYPE_STATS:
+		/*
+		 * Update driver statistics and send statistics notifications to the registered modules.
+		 */
+		nss_c2c_tx_stats_sync(nss_ctx, &nctm->msg.stats);
+		nss_c2c_tx_stats_notify(nss_ctx);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_c2c_tx_notify[nss_ctx->id].c2c_tx_callback;
+		ncm->app_data = (nss_ptr_t)nss_c2c_tx_notify[nss_ctx->id].app_data;
+	}
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_c2c_tx_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, nctm);
+}
+
+/*
+ * nss_c2c_tx_register_handler()
+ *	Register handler for messaging
+ */
+void nss_c2c_tx_register_handler(struct nss_ctx_instance *nss_ctx)
+{
+	nss_info("%px: nss_c2c_tx_register_handler", nss_ctx);
+	nss_core_register_handler(nss_ctx, NSS_C2C_TX_INTERFACE, nss_c2c_tx_msg_handler, NULL);
+
+	if (nss_ctx->id == NSS_CORE_0) {
+		nss_c2c_tx_stats_dentry_create();
+	}
+	nss_c2c_tx_strings_dentry_create();
+}
+EXPORT_SYMBOL(nss_c2c_tx_register_handler);
+
+/*
+ * nss_c2c_tx_tx_msg()
+ *	Transmit an c2c_tx message to the FW with a specified size.
+ */
+nss_tx_status_t nss_c2c_tx_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_c2c_tx_msg *nctm)
+{
+	struct nss_cmn_msg *ncm = &nctm->cm;
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!nss_c2c_tx_verify_if_num(ncm->interface)) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_C2C_TX_MSG_TYPE_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_c2c_tx_log_tx_msg(nctm);
+
+	return nss_core_send_cmd(nss_ctx, nctm, sizeof(*nctm), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_c2c_tx_tx_msg);
+
+/*
+ * nss_c2c_tx_msg_cfg_map_callback()
+ *	Callback function for tx_map configuration
+ */
+static void nss_c2c_tx_msg_cfg_map_callback(void *app_data, struct nss_c2c_tx_msg *nctm)
+{
+	struct nss_ctx_instance *nss_ctx __attribute__((unused)) = (struct nss_ctx_instance *)app_data;
+	if (nctm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("%px: nss c2c_tx_map configuration failed: %d for NSS core %d\n",
+			nss_ctx, nctm->cm.error, nss_ctx->id);
+	}
+
+	nss_info("%px: nss c2c_tx_map configuration succeeded for NSS core %d\n",
+		nss_ctx, nss_ctx->id);
+}
+
+/*
+ * nss_c2c_tx_msg_performance_test_start_callback()
+ *	Callback function for c2c_tx test start configuration
+ */
+static void nss_c2c_tx_msg_performance_test_callback(void *app_data, struct nss_c2c_tx_msg *nctm)
+{
+	struct nss_ctx_instance *nss_ctx __attribute__((unused)) = (struct nss_ctx_instance *)app_data;
+
+	/*
+	 * Test start has been failed. Restore the value to initial state.
+	 */
+	if (nctm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("%px: nss c2c_tx test start failed: %d for NSS core %d\n",
+			nss_ctx, nctm->cm.error, nss_ctx->id);
+		nss_c2c_tx_test_id = -1;
+		return;
+	}
+
+	nss_info("%px: nss c2c_tx test successfully initialized for NSS core %d\n",
+		nss_ctx, nss_ctx->id);
+}
+
+/*
+ * nss_c2c_tx_msg_cfg_map()
+ *	Send NSS to c2c_map
+ */
+nss_tx_status_t nss_c2c_tx_msg_cfg_map(struct nss_ctx_instance *nss_ctx, uint32_t tx_map, uint32_t c2c_intr_addr)
+{
+	int32_t status;
+	struct nss_c2c_tx_msg nctm;
+	struct nss_c2c_tx_map *cfg_map;
+
+	nss_info("%px: C2C map:%x\n", nss_ctx, tx_map);
+	nss_c2c_tx_msg_init(&nctm, NSS_C2C_TX_INTERFACE, NSS_C2C_TX_MSG_TYPE_TX_MAP,
+		sizeof(struct nss_c2c_tx_map), nss_c2c_tx_msg_cfg_map_callback, (void *)nss_ctx);
+
+	cfg_map = &nctm.msg.map;
+	cfg_map->tx_map = tx_map;
+	cfg_map->c2c_intr_addr = c2c_intr_addr;
+
+	status = nss_c2c_tx_tx_msg(nss_ctx, &nctm);
+	if (unlikely(status != NSS_TX_SUCCESS)) {
+		return status;
+	}
+
+	return NSS_TX_SUCCESS;
+}
+
+/*
+ * nss_c2c_tx_msg_performance_test()
+ *	Send NSS c2c peformance test start message.
+ */
+nss_tx_status_t nss_c2c_tx_msg_performance_test(struct nss_ctx_instance *nss_ctx, uint32_t test_id)
+{
+	int32_t status;
+	struct nss_c2c_tx_msg nctm;
+	struct nss_c2c_tx_test *test;
+
+	nss_info("%px: C2C test message:%x\n", nss_ctx, test_id);
+	nss_c2c_tx_msg_init(&nctm, NSS_C2C_TX_INTERFACE, NSS_C2C_TX_MSG_TYPE_PERFORMANCE_TEST,
+		sizeof(struct nss_c2c_tx_test), nss_c2c_tx_msg_performance_test_callback, (void *)nss_ctx);
+
+	test = &nctm.msg.test;
+	test->test_id = test_id;
+
+	status = nss_c2c_tx_tx_msg(nss_ctx, &nctm);
+	if (unlikely(status != NSS_TX_SUCCESS)) {
+		return status;
+	}
+
+	return NSS_TX_SUCCESS;
+}
+
+/*
+ * nss_c2c_tx_msg_init()
+ *	Initialize C2C_TX message.
+ */
+void nss_c2c_tx_msg_init(struct nss_c2c_tx_msg *nctm, uint16_t if_num, uint32_t type, uint32_t len,
+			nss_c2c_tx_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&nctm->cm, if_num, type, len, (void *)cb, app_data);
+}
+EXPORT_SYMBOL(nss_c2c_tx_msg_init);
+
+/*
+ * nss_c2c_tx_performance_test_handler()
+ *	Handles the performance test.
+ */
+static int nss_c2c_tx_performance_test_handler(struct ctl_table *ctl, int write,
+				void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[0];
+	int ret, ret_c2c_tx, current_state;
+	current_state = nss_c2c_tx_test_id;
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+
+	if (ret != NSS_SUCCESS) {
+		return ret;
+	}
+
+	if (!write) {
+		return ret;
+	}
+
+	if (current_state != -1) {
+		nss_warning("%px: Another test is running.\n", nss_ctx);
+		return -EINVAL;
+	}
+
+	if (nss_c2c_tx_test_id >= NSS_C2C_TX_TEST_TYPE_MAX || nss_c2c_tx_test_id <= 0) {
+		nss_warning("%px: Invalid test ID.\n", nss_ctx);
+		nss_c2c_tx_test_id = current_state;
+		return -EINVAL;
+	}
+
+	nss_info("Starting the c2c_tx performance test\n");
+	ret_c2c_tx = nss_c2c_tx_msg_performance_test(nss_ctx, nss_c2c_tx_test_id);
+
+	if (ret_c2c_tx != NSS_SUCCESS) {
+		nss_warning("%px: Starting the test has failed.\n", nss_ctx);
+		nss_c2c_tx_test_id = -1;
+	}
+
+	return ret_c2c_tx;
+}
+
+static struct ctl_table nss_c2c_tx_table[] = {
+	{
+		.procname	= "test_code",
+		.data		= &nss_c2c_tx_test_id,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_c2c_tx_performance_test_handler,
+	},
+	{ }
+};
+
+static struct ctl_table nss_c2c_tx_dir[] = {
+	{
+		.procname		= "c2c_tx",
+		.mode			= 0555,
+		.child			= nss_c2c_tx_table,
+	},
+	{ }
+};
+
+static struct ctl_table nss_c2c_tx_root_dir[] = {
+	{
+		.procname		= "nss",
+		.mode			= 0555,
+		.child			= nss_c2c_tx_dir,
+	},
+	{ }
+};
+
+static struct ctl_table nss_c2c_tx_root[] = {
+	{
+		.procname		= "dev",
+		.mode			= 0555,
+		.child			= nss_c2c_tx_root_dir,
+	},
+	{ }
+};
+
+static struct ctl_table_header *nss_c2c_tx_header;
+
+/*
+ * nss_c2c_tx_register_sysctl()
+ */
+void nss_c2c_tx_register_sysctl(void)
+{
+
+	/*
+	 * c2c_tx sema init.
+	 */
+	sema_init(&nss_c2c_tx_cfg_pvt.sem, 1);
+	init_completion(&nss_c2c_tx_cfg_pvt.complete);
+
+	/*
+	 * Register sysctl table.
+	 */
+	nss_c2c_tx_header = register_sysctl_table(nss_c2c_tx_root);
+}
+
+/*
+ * nss_c2c_tx_unregister_sysctl()
+ *      Unregister sysctl specific to c2c_tx
+ */
+void nss_c2c_tx_unregister_sysctl(void)
+{
+	/*
+	 * Unregister sysctl table.
+	 */
+	if (nss_c2c_tx_header) {
+		unregister_sysctl_table(nss_c2c_tx_header);
+	}
+}
+
+/*
+ * nss_c2c_tx_notify_register()
+ *	Register to receive c2c_tx notify messages.
+ */
+struct nss_ctx_instance *nss_c2c_tx_notify_register(int core, nss_c2c_tx_msg_callback_t cb, void *app_data)
+{
+	if (core >= NSS_CORE_MAX) {
+		nss_warning("Input core number %d is wrong\n", core);
+		return NULL;
+	}
+
+	nss_c2c_tx_notify[core].c2c_tx_callback = cb;
+	nss_c2c_tx_notify[core].app_data = app_data;
+
+	return (struct nss_ctx_instance *)&nss_top_main.nss[core];
+}
+EXPORT_SYMBOL(nss_c2c_tx_notify_register);
+
+/*
+ * nss_c2c_tx_notify_unregister()
+ *	Unregister to receive c2c_tx notify messages.
+ */
+void nss_c2c_tx_notify_unregister(int core)
+{
+	if (core >= NSS_CORE_MAX) {
+		nss_warning("Input core number %d is wrong\n", core);
+		return;
+	}
+
+	nss_c2c_tx_notify[core].c2c_tx_callback = NULL;
+	nss_c2c_tx_notify[core].app_data = NULL;
+}
+EXPORT_SYMBOL(nss_c2c_tx_notify_unregister);
+
+/*
+ * nss_c2c_tx_init()
+ */
+void nss_c2c_tx_init(void)
+{
+	int core;
+
+	for (core = 0; core < NSS_CORE_MAX; core++) {
+		nss_c2c_tx_notify_register(core, NULL, NULL);
+	}
+}
diff --git a/qca-nss-drv/nss_c2c_tx_log.c b/qca-nss-drv/nss_c2c_tx_log.c
new file mode 100644
index 0000000..088cef3
--- /dev/null
+++ b/qca-nss-drv/nss_c2c_tx_log.c
@@ -0,0 +1,121 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_c2c_tx_log.c
+ *	NSS C2C TX logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_c2c_tx_log_message_types_str
+ *	C2C TX message strings
+ */
+static int8_t *nss_c2c_tx_log_message_types_str[NSS_C2C_TX_MSG_TYPE_MAX] __maybe_unused = {
+	"C2C TX Stats message",
+	"C2C TX Map Message",
+};
+
+/*
+ * nss_c2c_tx_log_error_response_types_str
+ *	Strings for error types for c2c_tx messages
+ */
+static int8_t *nss_c2c_tx_log_error_response_types_str[NSS_C2C_TX_MSG_ERROR_MAX] __maybe_unused = {
+	"No error",
+	"Invalid Operation"
+};
+
+/*
+ * nss_c2c_tx_map_msg()()
+ *	Log NSS C2C TX Map message.
+ */
+static void nss_c2c_tx_map_msg(struct nss_c2c_tx_msg *nctm)
+{
+	struct nss_c2c_tx_map *nctmm __maybe_unused = &nctm->msg.map;
+	nss_trace("%px: NSS C2C TX Map message: \n"
+		"C2C Receiver Queue Start Address: %d\n"
+		"C2C Interrupt Register Address: %d\n",
+		nctm,
+		nctmm->tx_map, nctmm->c2c_intr_addr);
+}
+
+/*
+ * nss_c2c_tx_log_verbose()
+ *	Log message contents.
+ */
+static void nss_c2c_tx_log_verbose(struct nss_c2c_tx_msg *nctm)
+{
+	switch (nctm->cm.type) {
+	case NSS_C2C_TX_MSG_TYPE_TX_MAP:
+		nss_c2c_tx_map_msg(nctm);
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", nctm);
+		break;
+	}
+}
+
+/*
+ * nss_c2c_tx_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_c2c_tx_log_tx_msg(struct nss_c2c_tx_msg *nctm)
+{
+	if (nctm->cm.type >= NSS_C2C_TX_MSG_TYPE_MAX) {
+		nss_info("%px: Invalid message type\n", nctm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nctm, nctm->cm.type, nss_c2c_tx_log_message_types_str[nctm->cm.type]);
+	nss_c2c_tx_log_verbose(nctm);
+}
+
+/*
+ * nss_c2c_tx_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_c2c_tx_log_rx_msg(struct nss_c2c_tx_msg *nctm)
+{
+	if (nctm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", nctm);
+		return;
+	}
+
+	if (nctm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nctm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nctm, nctm->cm.type,
+			nss_c2c_tx_log_message_types_str[nctm->cm.type],
+			nctm->cm.response, nss_cmn_response_str[nctm->cm.response]);
+		goto verbose;
+	}
+
+	if (nctm->cm.error >= NSS_C2C_TX_MSG_ERROR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			nctm, nctm->cm.type, nss_c2c_tx_log_message_types_str[nctm->cm.type],
+			nctm->cm.response, nss_cmn_response_str[nctm->cm.response],
+			nctm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		nctm, nctm->cm.type, nss_c2c_tx_log_message_types_str[nctm->cm.type],
+		nctm->cm.response, nss_cmn_response_str[nctm->cm.response],
+		nctm->cm.error, nss_c2c_tx_log_error_response_types_str[nctm->cm.error]);
+
+verbose:
+	nss_c2c_tx_log_verbose(nctm);
+}
diff --git a/qca-nss-drv/nss_c2c_tx_log.h b/qca-nss-drv/nss_c2c_tx_log.h
new file mode 100644
index 0000000..e6ec47e
--- /dev/null
+++ b/qca-nss-drv/nss_c2c_tx_log.h
@@ -0,0 +1,36 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_C2C_TX_LOG_H
+#define __NSS_C2C_TX_LOG_H
+/*
+ * nss_c2c_tx_log.h
+ *	NSS C2C TX Log Header File
+ */
+
+/*
+ * nss_c2c_tx_log_tx_msg
+ *	Logs an C2C TX message that is sent to the NSS firmware.
+ */
+void nss_c2c_tx_log_tx_msg(struct nss_c2c_tx_msg *nctm);
+
+/*
+ * nss_c2c_tx_log_rx_msg
+ *	Logs an IPv4 message that is received from the NSS firmware.
+ */
+void nss_c2c_tx_log_rx_msg(struct nss_c2c_tx_msg *nctm);
+
+#endif /* __NSS_C2C_TX_LOG_H */
diff --git a/qca-nss-drv/nss_c2c_tx_stats.c b/qca-nss-drv/nss_c2c_tx_stats.c
new file mode 100644
index 0000000..7983f3f
--- /dev/null
+++ b/qca-nss-drv/nss_c2c_tx_stats.c
@@ -0,0 +1,168 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_c2c_tx_stats.h"
+#include "nss_c2c_tx_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_c2c_tx_stats_notifier);
+
+/*
+ * Spinlock to protect C2C_TX statistics update/read
+ */
+DEFINE_SPINLOCK(nss_c2c_tx_stats_lock);
+
+/*
+ * nss_c2c_tx_stats
+ *	c2c_tx statistics
+ */
+uint64_t nss_c2c_tx_stats[NSS_MAX_CORES][NSS_C2C_TX_STATS_MAX];
+
+/*
+ * nss_c2c_tx_stats_read()
+ *	Read c2c_tx statistics
+ */
+static ssize_t nss_c2c_tx_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i, core;
+
+	/*
+	 * Max output lines = #stats * NSS_MAX_CORES  +
+	 * few blank lines for banner printing + Number of Extra outputlines for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_C2C_TX_STATS_MAX * NSS_MAX_CORES + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return -ENOMEM;
+	}
+
+	stats_shadow = kzalloc(NSS_C2C_TX_STATS_MAX * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return -ENOMEM;
+	}
+
+	/*
+	 * C2C_TX statistics
+	 */
+	for (core = 0; core < NSS_MAX_CORES; core++) {
+		spin_lock_bh(&nss_c2c_tx_stats_lock);
+		for (i = 0; i < NSS_C2C_TX_STATS_MAX; i++) {
+			stats_shadow[i] = nss_c2c_tx_stats[core][i];
+		}
+		spin_unlock_bh(&nss_c2c_tx_stats_lock);
+		size_wr += nss_stats_banner(lbuf, size_wr, size_al, "c2c_tx", core);
+		size_wr += nss_stats_print("c2c_tx", NULL, NSS_STATS_SINGLE_INSTANCE, nss_c2c_tx_strings_stats, stats_shadow, NSS_C2C_TX_STATS_MAX, lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_c2c_tx_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(c2c_tx);
+
+/*
+ * nss_c2c_tx_stats_dentry_create()
+ *	Create c2c_tx statistics debug entry.
+ */
+void nss_c2c_tx_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("c2c_tx", &nss_c2c_tx_stats_ops);
+}
+
+/*
+ * nss_c2c_tx_stats_sync()
+ *	Handle the syncing of NSS C2C_TX statistics.
+ */
+void nss_c2c_tx_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_c2c_tx_stats *nct)
+{
+	int id = nss_ctx->id;
+	int j;
+
+	spin_lock_bh(&nss_c2c_tx_stats_lock);
+
+	/*
+	 * Common node stats
+	 */
+	nss_c2c_tx_stats[id][NSS_STATS_NODE_RX_PKTS] += (nct->pbuf_simple + nct->pbuf_sg + nct->pbuf_returning);
+	nss_c2c_tx_stats[id][NSS_STATS_NODE_RX_BYTES] += nct->node_stats.rx_bytes;
+	nss_c2c_tx_stats[id][NSS_STATS_NODE_TX_PKTS] += nct->node_stats.tx_packets;
+	nss_c2c_tx_stats[id][NSS_STATS_NODE_TX_BYTES] += nct->node_stats.tx_bytes;
+
+	for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+		nss_c2c_tx_stats[id][NSS_STATS_NODE_RX_QUEUE_0_DROPPED + j] += nct->node_stats.rx_dropped[j];
+	}
+
+	/*
+	 * C2C_TX statistics
+	 */
+	nss_c2c_tx_stats[id][NSS_C2C_TX_STATS_PBUF_SIMPLE] += nct->pbuf_simple;
+	nss_c2c_tx_stats[id][NSS_C2C_TX_STATS_PBUF_SG] += nct->pbuf_sg;
+	nss_c2c_tx_stats[id][NSS_C2C_TX_STATS_PBUF_RETURNING] += nct->pbuf_returning;
+
+	spin_unlock_bh(&nss_c2c_tx_stats_lock);
+}
+
+/*
+ * nss_c2c_tx_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_c2c_tx_stats_notify(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_c2c_tx_stats_notification c2c_tx_stats;
+
+	c2c_tx_stats.core_id = nss_ctx->id;
+	memcpy(c2c_tx_stats.stats, nss_c2c_tx_stats[c2c_tx_stats.core_id], sizeof(c2c_tx_stats.stats));
+	atomic_notifier_call_chain(&nss_c2c_tx_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&c2c_tx_stats);
+}
+
+/*
+ * nss_c2c_tx_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_c2c_tx_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_c2c_tx_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_c2c_tx_stats_register_notifier);
+
+/*
+ * nss_c2c_tx_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_c2c_tx_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_c2c_tx_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_c2c_tx_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_c2c_tx_stats.h b/qca-nss-drv/nss_c2c_tx_stats.h
new file mode 100644
index 0000000..f77a3b4
--- /dev/null
+++ b/qca-nss-drv/nss_c2c_tx_stats.h
@@ -0,0 +1,29 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_C2C_TX_STATS_H
+#define __NSS_C2C_TX_STATS_H
+
+#include <nss_cmn.h>
+
+/*
+ * C2C Tx statistics APIs
+ */
+extern void nss_c2c_tx_stats_notify(struct nss_ctx_instance *nss_ctx);
+extern void nss_c2c_tx_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_c2c_tx_stats *nct);
+extern void nss_c2c_tx_stats_dentry_create(void);
+
+#endif /* __NSS_C2C_TX_STATS_H */
diff --git a/qca-nss-drv/nss_c2c_tx_strings.c b/qca-nss-drv/nss_c2c_tx_strings.c
new file mode 100644
index 0000000..8272e84
--- /dev/null
+++ b/qca-nss-drv/nss_c2c_tx_strings.c
@@ -0,0 +1,61 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+
+/*
+ * nss_c2c_tx_strings_stats
+ *	C2C Tx statistics strings.
+ */
+struct nss_stats_info nss_c2c_tx_strings_stats[NSS_C2C_TX_STATS_MAX] = {
+	{"rx_pkts"		, NSS_STATS_TYPE_COMMON},
+	{"rx_byts"		, NSS_STATS_TYPE_COMMON},
+	{"tx_pkts"		, NSS_STATS_TYPE_COMMON},
+	{"tx_byts"		, NSS_STATS_TYPE_COMMON},
+	{"rx_queue[0]_drops"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue[1]_drops"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue[2]_drops"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue[3]_drops"	, NSS_STATS_TYPE_DROP},
+	{"pbuf_simple"		, NSS_STATS_TYPE_SPECIAL},
+	{"pbuf_sg"		, NSS_STATS_TYPE_SPECIAL},
+	{"pbuf_returning"	, NSS_STATS_TYPE_SPECIAL}
+};
+
+
+/*
+ * nss_c2c_tx_strings_read()
+ *	Read c2c Tx node statistics names
+ */
+static ssize_t nss_c2c_tx_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_c2c_tx_strings_stats, NSS_C2C_TX_STATS_MAX);
+}
+
+/*
+ * nss_c2c_tx_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(c2c_tx);
+
+/*
+ * nss_c2c_tx_strings_dentry_create()
+ *	Create C2C Tx statistics strings debug entry.
+ */
+void nss_c2c_tx_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("c2c_tx", &nss_c2c_tx_strings_ops);
+}
diff --git a/qca-nss-drv/nss_c2c_tx_strings.h b/qca-nss-drv/nss_c2c_tx_strings.h
new file mode 100644
index 0000000..483177d
--- /dev/null
+++ b/qca-nss-drv/nss_c2c_tx_strings.h
@@ -0,0 +1,23 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_C2C_TX_STRINGS_H
+#define __NSS_C2C_TX_STRINGS_H
+
+extern struct nss_stats_info nss_c2c_tx_strings_stats[NSS_C2C_TX_STATS_MAX];
+extern void nss_c2c_tx_strings_dentry_create(void);
+
+#endif /* __NSS_C2C_TX_STRINGS_H */
diff --git a/qca-nss-drv/nss_capwap.c b/qca-nss-drv/nss_capwap.c
new file mode 100644
index 0000000..597c318
--- /dev/null
+++ b/qca-nss-drv/nss_capwap.c
@@ -0,0 +1,606 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+ /*
+  * nss_capwap.c
+  *	NSS CAPWAP driver interface APIs
+  */
+#include "nss_core.h"
+#include "nss_capwap.h"
+#include "nss_cmn.h"
+#include "nss_tx_rx_common.h"
+#include "nss_capwap_stats.h"
+#include "nss_capwap_log.h"
+#include "nss_capwap_strings.h"
+
+/*
+ * Spinlock for protecting tunnel operations colliding with a tunnel destroy
+ */
+DEFINE_SPINLOCK(nss_capwap_spinlock);
+
+/*
+ * Array of pointer for NSS CAPWAP handles. Each handle has per-tunnel
+ * stats based on the if_num which is an index.
+ *
+ * Per CAPWAP tunnel/interface number instance.
+ */
+struct nss_capwap_handle {
+	atomic_t refcnt;			/**< Reference count on the tunnel */
+	uint32_t if_num;			/**< Interface number */
+	uint32_t tunnel_status;			/**< 0=disable, 1=enabled */
+	struct nss_ctx_instance *ctx;		/**< Pointer to context */
+	nss_capwap_msg_callback_t msg_callback;	/**< Msg callback */
+	void *app_data;				/**< App data (argument) */
+	struct nss_capwap_tunnel_stats stats;	/**< Stats per-interface number */
+};
+static struct nss_capwap_handle *nss_capwap_hdl[NSS_MAX_DYNAMIC_INTERFACES];
+
+/*
+ * nss_capwap_get_interface_type()
+ *	Function to get the type of dynamic interface.
+ */
+static enum nss_dynamic_interface_type nss_capwap_get_interface_type(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx;
+	nss_ctx = &nss_top_main.nss[nss_top_main.capwap_handler_id];
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	return nss_dynamic_interface_get_type(nss_ctx, if_num);
+}
+
+/*
+ * nss_capwap_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static bool nss_capwap_verify_if_num(uint32_t if_num)
+{
+	enum nss_dynamic_interface_type type;
+
+	if (nss_is_dynamic_interface(if_num) == false) {
+		return false;
+	}
+
+	type = nss_capwap_get_interface_type(if_num);
+	if ((type != NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_HOST_INNER) && (type != NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_OUTER) ) {
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_capwap_refcnt_inc()
+ *	Increments refcnt on the tunnel.
+ */
+static void nss_capwap_refcnt_inc(int32_t if_num)
+{
+	if_num = if_num - NSS_DYNAMIC_IF_START;
+	atomic_inc(&nss_capwap_hdl[if_num]->refcnt);
+	nss_assert(atomic_read(&nss_capwap_hdl[if_num]->refcnt) > 0);
+}
+
+/*
+ * nss_capwap_refcnt_dec()
+ *	Decrements refcnt on the tunnel.
+ */
+static void nss_capwap_refcnt_dec(int32_t if_num)
+{
+	if_num = if_num - NSS_DYNAMIC_IF_START;
+	nss_assert(atomic_read(&nss_capwap_hdl[if_num]->refcnt) > 0);
+	atomic_dec(&nss_capwap_hdl[if_num]->refcnt);
+}
+
+/*
+ * nss_capwap_refcnt_get()
+ *	Get refcnt on the tunnel.
+ */
+static uint32_t nss_capwap_refcnt_get(int32_t if_num)
+{
+	if_num = if_num - NSS_DYNAMIC_IF_START;
+	return atomic_read(&nss_capwap_hdl[if_num]->refcnt);
+}
+
+/*
+ * nss_capwap_set_msg_callback()
+ *	This sets the message callback handler and its associated context
+ */
+static void nss_capwap_set_msg_callback(int32_t if_num, nss_capwap_msg_callback_t cb, void *app_data)
+{
+	struct nss_capwap_handle *h;
+
+	h = nss_capwap_hdl[if_num - NSS_DYNAMIC_IF_START];
+	if (!h) {
+		return;
+	}
+
+	h->app_data = app_data;
+	h->msg_callback = cb;
+}
+
+/*
+ * nss_capwap_get_msg_callback()
+ *	This gets the message callback handler and its associated context
+ */
+static nss_capwap_msg_callback_t nss_capwap_get_msg_callback(int32_t if_num, void **app_data)
+{
+	struct nss_capwap_handle *h;
+
+	h = nss_capwap_hdl[if_num - NSS_DYNAMIC_IF_START];
+	if (!h) {
+		*app_data = NULL;
+		return NULL;
+	}
+
+	*app_data = h->app_data;
+	return h->msg_callback;
+}
+
+/*
+ * nss_capwap_update_stats()
+ *	Update per-tunnel stats for each CAPWAP interface.
+ */
+static void nss_capwap_update_stats(struct nss_capwap_handle *handle, struct nss_capwap_stats_msg *fstats)
+{
+	struct nss_capwap_tunnel_stats *stats;
+	enum nss_dynamic_interface_type type;
+
+	stats = &handle->stats;
+	type = nss_capwap_get_interface_type(handle->if_num);
+
+	switch(type) {
+	case NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_OUTER:
+		stats->rx_segments += fstats->rx_segments;
+		stats->dtls_pkts += fstats->dtls_pkts;
+		stats->rx_dup_frag += fstats->rx_dup_frag;
+		stats->rx_oversize_drops += fstats->rx_oversize_drops;
+		stats->rx_frag_timeout_drops += fstats->rx_frag_timeout_drops;
+		stats->rx_n2h_drops += fstats->rx_n2h_drops;
+		stats->rx_n2h_queue_full_drops += fstats->rx_n2h_queue_full_drops;
+		stats->rx_mem_failure_drops += fstats->rx_mem_failure_drops;
+		stats->rx_csum_drops += fstats->rx_csum_drops;
+		stats->rx_malformed += fstats->rx_malformed;
+		stats->rx_frag_gap_drops += fstats->rx_frag_gap_drops;
+
+		/*
+		 * Update pnode rx stats for OUTER node.
+		 */
+		stats->pnode_stats.rx_packets += fstats->pnode_stats.rx_packets;
+		stats->pnode_stats.rx_bytes += fstats->pnode_stats.rx_bytes;
+		stats->pnode_stats.rx_dropped += nss_cmn_rx_dropped_sum(&fstats->pnode_stats);
+		break;
+
+	case NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_HOST_INNER:
+		stats->tx_segments += fstats->tx_segments;
+		stats->tx_queue_full_drops += fstats->tx_queue_full_drops;
+		stats->tx_mem_failure_drops += fstats->tx_mem_failure_drops;
+		stats->tx_dropped_sg_ref += fstats->tx_dropped_sg_ref;
+		stats->tx_dropped_ver_mis += fstats->tx_dropped_ver_mis;
+		stats->tx_dropped_hroom += fstats->tx_dropped_hroom;
+		stats->tx_dropped_dtls += fstats->tx_dropped_dtls;
+		stats->tx_dropped_nwireless += fstats->tx_dropped_nwireless;
+
+		/*
+		 * Update pnode tx stats for INNER node.
+		 */
+		stats->pnode_stats.tx_packets += fstats->pnode_stats.tx_packets;
+		stats->pnode_stats.tx_bytes += fstats->pnode_stats.tx_bytes;
+		stats->tx_dropped_inner += nss_cmn_rx_dropped_sum(&fstats->pnode_stats);
+		break;
+
+	default:
+		nss_warning("%px: Received invalid dynamic interface type: %d", handle, type);
+		nss_assert(0);
+		return;
+	}
+
+	/*
+	 * Set to 1 when the tunnel is operating in fast memory.
+	 */
+	stats->fast_mem = fstats->fast_mem;
+}
+
+/*
+ * nss_capwap_handler()
+ *	Handle NSS -> HLOS messages for CAPWAP
+ */
+static void nss_capwap_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_capwap_msg *ntm = (struct nss_capwap_msg *)ncm;
+	nss_capwap_msg_callback_t cb;
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type > NSS_CAPWAP_MSG_TYPE_MAX) {
+		nss_warning("%px: received invalid message %d for CAPWAP interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_capwap_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Trace messages.
+	 */
+	nss_capwap_log_rx_msg(ntm);
+
+	switch (ntm->cm.type) {
+	case NSS_CAPWAP_MSG_TYPE_SYNC_STATS: {
+			uint32_t if_num;
+
+			if_num = ncm->interface - NSS_DYNAMIC_IF_START;
+			if (nss_capwap_hdl[if_num] != NULL) {
+				/*
+				 * Update driver statistics and send statistics notifications to the registered modules.
+				 */
+				nss_capwap_update_stats(nss_capwap_hdl[if_num], &ntm->msg.stats);
+				nss_capwap_stats_notify(ncm->interface, nss_ctx->id);
+			}
+		}
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_capwap_get_msg_callback(ncm->interface, (void **)&ncm->app_data);
+	}
+
+	/*
+	 * Do we have a callback
+	 */
+	if (!ncm->cb) {
+		nss_trace("%px: cb is null for interface %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb = (nss_capwap_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, ntm);
+}
+
+/*
+ * nss_capwap_instance_alloc()
+ *	Allocate CAPWAP tunnel instance
+ */
+static bool nss_capwap_instance_alloc(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_capwap_handle *h;
+
+	/*
+	 * Allocate a handle
+	 */
+	h = kmalloc(sizeof(struct nss_capwap_handle), GFP_ATOMIC);
+	if (h == NULL) {
+		nss_warning("%px: no memory for allocating CAPWAP instance for interface : %d", nss_ctx, if_num);
+		return false;
+	}
+
+	memset(h, 0, sizeof(struct nss_capwap_handle));
+	h->if_num = if_num;
+
+	spin_lock_bh(&nss_capwap_spinlock);
+	if (nss_capwap_hdl[if_num - NSS_DYNAMIC_IF_START] != NULL) {
+		spin_unlock_bh(&nss_capwap_spinlock);
+		kfree(h);
+		nss_warning("%px: Another thread is already allocated instance for :%d", nss_ctx, if_num);
+		return false;
+	}
+
+	nss_capwap_hdl[if_num - NSS_DYNAMIC_IF_START] = h;
+	spin_unlock_bh(&nss_capwap_spinlock);
+
+	return true;
+}
+
+/*
+ * nss_capwap_tx_msg()
+ *	Transmit a CAPWAP message to NSS FW. Don't call this from softirq/interrupts.
+ */
+nss_tx_status_t nss_capwap_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_capwap_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+	int32_t status;
+	int32_t if_num;
+
+	BUG_ON(in_interrupt());
+	BUG_ON(in_softirq());
+	BUG_ON(in_serving_softirq());
+
+	if (nss_capwap_verify_if_num(msg->cm.interface) == false) {
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	if (ncm->type >= NSS_CAPWAP_MSG_TYPE_MAX) {
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	if_num = msg->cm.interface - NSS_DYNAMIC_IF_START;
+	spin_lock_bh(&nss_capwap_spinlock);
+	if (!nss_capwap_hdl[if_num]) {
+		spin_unlock_bh(&nss_capwap_spinlock);
+		nss_warning("%px: capwap tunnel if_num is not there: %d", nss_ctx, msg->cm.interface);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+	nss_capwap_refcnt_inc(msg->cm.interface);
+	spin_unlock_bh(&nss_capwap_spinlock);
+
+	/*
+	 * Trace messages.
+	 */
+	nss_capwap_log_tx_msg(msg);
+
+	status = nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+	nss_capwap_refcnt_dec(msg->cm.interface);
+	return status;
+}
+EXPORT_SYMBOL(nss_capwap_tx_msg);
+
+/*
+ * nss_capwap_tx_buf()
+ *	Transmit data buffer (skb) to a NSS interface number
+ */
+nss_tx_status_t nss_capwap_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, uint32_t if_num)
+{
+	BUG_ON(!nss_capwap_verify_if_num(if_num));
+
+	return nss_core_send_packet(nss_ctx, os_buf, if_num, H2N_BIT_FLAG_VIRTUAL_BUFFER | H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+EXPORT_SYMBOL(nss_capwap_tx_buf);
+
+/*
+ ***********************************
+ * Register/Unregister/Miscellaneous APIs
+ ***********************************
+ */
+
+/*
+ * nss_capwap_get_stats()
+ *	API for getting stats from a CAPWAP tunnel interface stats
+ */
+bool nss_capwap_get_stats(uint32_t if_num, struct nss_capwap_tunnel_stats *stats)
+{
+	if (nss_capwap_verify_if_num(if_num) == false) {
+		return false;
+	}
+
+	if_num = if_num - NSS_DYNAMIC_IF_START;
+	spin_lock_bh(&nss_capwap_spinlock);
+	if (nss_capwap_hdl[if_num] == NULL) {
+		spin_unlock_bh(&nss_capwap_spinlock);
+		return false;
+	}
+
+	memcpy(stats, &nss_capwap_hdl[if_num]->stats, sizeof(struct nss_capwap_tunnel_stats));
+	spin_unlock_bh(&nss_capwap_spinlock);
+	return true;
+}
+EXPORT_SYMBOL(nss_capwap_get_stats);
+
+/*
+ * nss_capwap_notify_register()
+ *	Registers a message notifier with NSS FW. It should not be called from
+ *	softirq or interrupts.
+ */
+struct nss_ctx_instance *nss_capwap_notify_register(uint32_t if_num, nss_capwap_msg_callback_t cb, void *app_data)
+{
+	struct nss_ctx_instance *nss_ctx;
+
+	nss_ctx = &nss_top_main.nss[nss_top_main.capwap_handler_id];
+
+	if (nss_capwap_verify_if_num(if_num) == false) {
+		nss_warning("%px: notfiy register received for invalid interface %d", nss_ctx, if_num);
+		return NULL;
+	}
+
+	spin_lock_bh(&nss_capwap_spinlock);
+	if (nss_capwap_hdl[if_num - NSS_DYNAMIC_IF_START] != NULL) {
+		spin_unlock_bh(&nss_capwap_spinlock);
+		nss_warning("%px: notfiy register tunnel already exists for interface %d", nss_ctx, if_num);
+		return NULL;
+	}
+	spin_unlock_bh(&nss_capwap_spinlock);
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_capwap_notify_register);
+
+/*
+ * nss_capwap_notify_unregister()
+ *	unregister the CAPWAP notifier for the given interface number (if_num).
+ *	It shouldn't be called from softirq or interrupts.
+ */
+nss_tx_status_t nss_capwap_notify_unregister(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_top_instance *nss_top;
+	int index;
+
+	if (nss_capwap_verify_if_num(if_num) == false) {
+		nss_warning("%px: notify unregister received for invalid interface %d", nss_ctx, if_num);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	nss_top = nss_ctx->nss_top;
+	if (nss_top == NULL) {
+		nss_warning("%px: notify unregister received for invalid nss_top %d", nss_ctx, if_num);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	index = if_num - NSS_DYNAMIC_IF_START;
+	spin_lock_bh(&nss_capwap_spinlock);
+	if (nss_capwap_hdl[index] == NULL) {
+		spin_unlock_bh(&nss_capwap_spinlock);
+		nss_warning("%px: notify unregister received for unallocated if_num: %d", nss_ctx, if_num);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	/*
+	 * It's the responsibility of caller to wait and call us again. We return failure saying
+	 * that we can't remove msg handler now.
+	 */
+	if (nss_capwap_refcnt_get(if_num) != 0) {
+		spin_unlock_bh(&nss_capwap_spinlock);
+		nss_warning("%px: notify unregister tunnel %d: has reference", nss_ctx, if_num);
+		return NSS_TX_FAILURE_QUEUE;
+	}
+
+	nss_capwap_set_msg_callback(if_num, NULL, NULL);
+	spin_unlock_bh(&nss_capwap_spinlock);
+
+	return NSS_TX_SUCCESS;
+}
+EXPORT_SYMBOL(nss_capwap_notify_unregister);
+
+/*
+ * nss_capwap_data_register()
+ *	Registers a data packet notifier with NSS FW.
+ */
+struct nss_ctx_instance *nss_capwap_data_register(uint32_t if_num, nss_capwap_buf_callback_t cb, struct net_device *netdev, uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx;
+	int core_status;
+
+	nss_ctx = nss_capwap_get_ctx();
+	if (nss_capwap_verify_if_num(if_num) == false) {
+		nss_warning("%px: data register received for invalid interface %d", nss_ctx, if_num);
+		return NULL;
+	}
+
+	spin_lock_bh(&nss_capwap_spinlock);
+	if (nss_ctx->subsys_dp_register[if_num].ndev != NULL) {
+		spin_unlock_bh(&nss_capwap_spinlock);
+		return NULL;
+	}
+	spin_unlock_bh(&nss_capwap_spinlock);
+
+	core_status = nss_core_register_handler(nss_ctx, if_num, nss_capwap_msg_handler, NULL);
+	if (core_status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: nss core register handler failed for if_num:%d with error :%d", nss_ctx, if_num, core_status);
+		return NULL;
+	}
+
+	if (nss_capwap_instance_alloc(nss_ctx, if_num) == false) {
+		nss_warning("%px: couldn't allocate tunnel  instance for if_num:%d", nss_ctx, if_num);
+		return NULL;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, cb, NULL, NULL, netdev, features);
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_capwap_data_register);
+
+/*
+ * nss_capwap_data_unregister()
+ *	Unregister a data packet notifier with NSS FW
+ */
+bool nss_capwap_data_unregister(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_capwap_handle *h;
+
+	nss_ctx = nss_capwap_get_ctx();
+	if (nss_capwap_verify_if_num(if_num) == false) {
+		nss_warning("%px: data unregister received for invalid interface %d", nss_ctx, if_num);
+		return false;
+	}
+
+	spin_lock_bh(&nss_capwap_spinlock);
+	/*
+	 * It's the responsibility of caller to wait and call us again.
+	 */
+	if (nss_capwap_refcnt_get(if_num) != 0) {
+		spin_unlock_bh(&nss_capwap_spinlock);
+		nss_warning("%px: notify unregister tunnel %d: has reference", nss_ctx, if_num);
+		return false;
+	}
+	h = nss_capwap_hdl[if_num - NSS_DYNAMIC_IF_START];
+	nss_capwap_hdl[if_num - NSS_DYNAMIC_IF_START] = NULL;
+	spin_unlock_bh(&nss_capwap_spinlock);
+
+	(void) nss_core_unregister_handler(nss_ctx, if_num);
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	kfree(h);
+	return true;
+}
+EXPORT_SYMBOL(nss_capwap_data_unregister);
+
+/*
+ * nss_capwap_get_ctx()
+ *	Return a CAPWAP NSS context.
+ */
+struct nss_ctx_instance *nss_capwap_get_ctx()
+{
+	struct nss_ctx_instance *nss_ctx;
+
+	nss_ctx = &nss_top_main.nss[nss_top_main.capwap_handler_id];
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_capwap_get_ctx);
+
+/*
+ * nss_capwap_ifnum_with_core_id()
+ *	Append core id to capwap interface num
+ */
+int nss_capwap_ifnum_with_core_id(int if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_capwap_get_ctx();
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	if (nss_is_dynamic_interface(if_num) == false) {
+		nss_info("%px: Invalid if_num: %d, must be a dynamic interface\n", nss_ctx, if_num);
+		return 0;
+	}
+	return NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_capwap_ifnum_with_core_id);
+
+/*
+ * nss_capwap_get_max_buf_size()
+ *	Return a CAPWAP NSS max_buf_size.
+ */
+uint32_t nss_capwap_get_max_buf_size(struct nss_ctx_instance *nss_ctx)
+{
+	return nss_core_get_max_buf_size(nss_ctx);
+}
+EXPORT_SYMBOL(nss_capwap_get_max_buf_size);
+
+/*
+ * nss_capwap_init()
+ *	Initializes CAPWAP. Gets called from nss_init.c
+ */
+void nss_capwap_init()
+{
+	memset(&nss_capwap_hdl, 0, sizeof(nss_capwap_hdl));
+	nss_capwap_stats_dentry_create();
+	nss_capwap_strings_dentry_create();
+}
+
+/*
+ * nss_capwap_msg_init()
+ *	Initialize capwap message.
+ */
+void nss_capwap_msg_init(struct nss_capwap_msg *ncm, uint16_t if_num, uint32_t type, uint32_t len,
+				nss_capwap_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, (void*)cb, app_data);
+}
+EXPORT_SYMBOL(nss_capwap_msg_init);
diff --git a/qca-nss-drv/nss_capwap_log.c b/qca-nss-drv/nss_capwap_log.c
new file mode 100644
index 0000000..b0b8564
--- /dev/null
+++ b/qca-nss-drv/nss_capwap_log.c
@@ -0,0 +1,282 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_capwap_log.c
+ *	NSS CAPWAP logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_capwap_log_message_types_str
+ *	CAPWAP message strings
+ */
+static int8_t *nss_capwap_log_message_types_str[NSS_CAPWAP_MSG_TYPE_MAX] __maybe_unused = {
+	"No Message",
+	"CAPWAP config Rule",
+	"CAPWAP unconfig Rule",
+	"CAPWAP Enable Tunnel",
+	"CAPWAP Disable Tunnel",
+	"CAPWAP Update Path MTU",
+	"CAPWAP Sync Stats",
+	"CAPWAP Version",
+	"CAPWAP DTLS",
+	"CAPWAP Add Flow Rule",
+	"CAPWAP Delete Flow Rule"
+};
+
+/*
+ * nss_capwap_log_error_response_types_str
+ *	Strings for error types for CAPWAP messages
+ */
+static int8_t *nss_capwap_log_error_response_types_str[NSS_CAPWAP_ERROR_MSG_MAX] __maybe_unused = {
+	"CAPWAP Invalid Reassembly Timeout",
+	"CAPWAP Invalid PAth MTU",
+	"CAPWAP Invalid Max Fragment",
+	"CAPWAP Invalid Buffer Size",
+	"CAPWAP Invalid L3 Protocool",
+	"CAPWAP Invalid UDP Protocol",
+	"CAPWAP Invalid Version",
+	"CAPWAP Tunnel Disabled",
+	"CAPWAP Tunnel Enabled",
+	"CAPWAP Tunnel Not Configured",
+	"CAPWAP Invalid IP Node",
+	"CAPWAP Invalid Type Flag",
+	"CAPWAP Inavlid DTLS Config",
+	"CAPWAP Flow Table Full",
+	"CAPWAP Flow Exists",
+	"CAPWAP Flow Does Not Exist"
+};
+
+/*
+ * nss_capwap_rule_msg()
+ *	Log NSS CAPWAP stats message.
+ */
+static void nss_capwap_rule_msg(struct nss_capwap_msg *ncm)
+{
+	struct nss_capwap_rule_msg *ncrm __maybe_unused = &ncm->msg.rule;
+	nss_trace("%px: NSS CAPWAP Rule message \n"
+		"Encap Rule Src IP: %px\n"
+		"Encap Rule Src Port: %d\n"
+		"Encap Rule Dst Ip: %px\n"
+		"Encap Rule Dst Port: %d\n"
+		"Encap Rule Path MTU: %d\n"
+		"Decap Rule Reassembly Timeout: %d\n"
+		"Decap Rule Max Fragments: %d\n"
+		"Decap Rule Max Buffer Size: %d\n"
+		"Stats Timer: %d\n"
+		"RPS: %d\n"
+		"Type Flags: %x\n"
+		"L3 Protocol: %d\n"
+		"UDP Protocol: %d\n"
+		"MTU: %d\n"
+		"GMAC Interface Number: %d\n"
+		"Enabled Features: %x\n"
+		"DTLS Interface Number: %d\n"
+		"BSSID: %px\n"
+		"Outer Segment Value: %x\n",
+		ncrm,
+		&ncrm->encap.src_ip.ip,
+		ncrm->encap.src_port,
+		&ncrm->encap.dest_ip.ip,
+		ncrm->encap.dest_port,
+		ncrm->encap.path_mtu,
+		ncrm->decap.reassembly_timeout,
+		ncrm->decap.max_fragments,
+		ncrm->decap.max_buffer_size,
+		ncrm->stats_timer,
+		ncrm->rps, ncrm->type_flags,
+		ncrm->l3_proto, ncrm->which_udp,
+		ncrm->mtu_adjust, ncrm->gmac_ifnum,
+		ncrm->enabled_features,
+		ncrm->dtls_inner_if_num,
+		&ncrm->bssid, ncrm->outer_sgt_value);
+}
+
+/*
+ * nss_capwap_path_mtu_msg()
+ *	Log NSS CAPWAP path MTU message.
+ */
+static void nss_capwap_path_mtu_msg(struct nss_capwap_msg *ncm)
+{
+	struct nss_capwap_path_mtu_msg *ncpmm __maybe_unused = &ncm->msg.mtu;
+	nss_trace("%px: NSS CAPWAP Path MTU message \n"
+		"CAPWAP Path MTU: %d\n",
+		ncpmm,
+		ncpmm->path_mtu);
+}
+
+/*
+ * nss_capwap_version_msg()
+ *	Log NSS CAPWAP version message.
+ */
+static void nss_capwap_version_msg(struct nss_capwap_msg *ncm)
+{
+	struct nss_capwap_version_msg *ncvm __maybe_unused = &ncm->msg.version;
+	nss_trace("%px: NSS CAPWAP Version message \n"
+		"CAPWAP Version: %d\n",
+		ncvm,
+		ncvm->version);
+}
+
+/*
+ * nss_capwap_dtls_msg()
+ *	Log NSS CAPWAP dtls message.
+ */
+static void nss_capwap_dtls_msg(struct nss_capwap_msg *ncm)
+{
+	struct nss_capwap_dtls_msg *ncdm __maybe_unused = &ncm->msg.dtls;
+	nss_trace("%px: NSS CAPWAP dtls message \n"
+		"CAPWAP DTLS Enable: %d\n"
+		"CAPWAP DTLS Inner Interface Number: %d\n"
+		"CAPWAP MTU Adjust: %d\n"
+		"CAPWAP Reserved: %x\n",
+		ncdm,
+		ncdm->enable, ncdm->dtls_inner_if_num,
+		ncdm->mtu_adjust, ncdm->reserved);
+}
+
+/*
+ * nss_capwap_flow_rule_msg()
+ *	Log NSS CAPWAP flow rule message.
+ */
+static void nss_capwap_flow_rule_msg(struct nss_capwap_flow_rule_msg *ncfrm)
+{
+	nss_trace("%px: NSS CAPWAP Flow Rule message \n"
+		"CAPWAP IP Version: %d\n"
+		"CAPWAP Layer 4 Protocol: %d\n"
+		"CAPWAP Source Port: %d\n"
+		"CAPWAP Destination Port: %d\n"
+		"CAPWAP Source IP: %x %x %x %x\n"
+		"CAPWAP Destination IP: %x %x %x %x"
+		"CAPWAP Flow ID: %d",
+		ncfrm,
+		ncfrm->ip_version, ncfrm->protocol,
+		ncfrm->src_port, ncfrm->dst_port,
+		ncfrm->src_ip[0], ncfrm->src_ip[1],
+		ncfrm->src_ip[2], ncfrm->src_ip[3],
+		ncfrm->dst_ip[0], ncfrm->dst_ip[1],
+		ncfrm->dst_ip[2], ncfrm->dst_ip[3],
+		ncfrm->flow_id);
+}
+
+/*
+ * nss_capwap_flow_rule_add_msg()
+ *	Log NSS CAPWAP flow rule add message.
+ */
+static void nss_capwap_flow_rule_add_msg(struct nss_capwap_msg *ncm)
+{
+	struct nss_capwap_flow_rule_msg *ncfrm __maybe_unused = &ncm->msg.flow_rule_add;
+	nss_capwap_flow_rule_msg(ncfrm);
+}
+
+/*
+ * nss_capwap_flow_rule_del_msg()
+ *	Log NSS CAPWAP flow rule del message.
+ */
+static void nss_capwap_flow_rule_del_msg(struct nss_capwap_msg *ncm)
+{
+	struct nss_capwap_flow_rule_msg *ncfrm __maybe_unused = &ncm->msg.flow_rule_del;
+	nss_capwap_flow_rule_msg(ncfrm);
+}
+
+/*
+ * nss_capwap_log_verbose()
+ *	Log message contents.
+ */
+static void nss_capwap_log_verbose(struct nss_capwap_msg *ncm)
+{
+	switch (ncm->cm.type) {
+	case NSS_CAPWAP_MSG_TYPE_CFG_RULE:
+		nss_capwap_rule_msg(ncm);
+		break;
+
+	case NSS_CAPWAP_MSG_TYPE_UPDATE_PATH_MTU:
+		nss_capwap_path_mtu_msg(ncm);
+		break;
+
+	case NSS_CAPWAP_MSG_TYPE_VERSION:
+		nss_capwap_version_msg(ncm);
+		break;
+
+	case NSS_CAPWAP_MSG_TYPE_DTLS:
+		nss_capwap_dtls_msg(ncm);
+		break;
+
+	case NSS_CAPWAP_MSG_TYPE_FLOW_RULE_ADD:
+		nss_capwap_flow_rule_add_msg(ncm);
+		break;
+
+	case NSS_CAPWAP_MSG_TYPE_FLOW_RULE_DEL:
+		nss_capwap_flow_rule_del_msg(ncm);
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", ncm);
+		break;
+	}
+}
+
+/*
+ * nss_capwap_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_capwap_log_tx_msg(struct nss_capwap_msg *ncm)
+{
+	if (ncm->cm.type >= NSS_CAPWAP_MSG_TYPE_MAX) {
+		nss_warning("%px: Invalid message type\n", ncm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ncm, ncm->cm.type, nss_capwap_log_message_types_str[ncm->cm.type]);
+	nss_capwap_log_verbose(ncm);
+}
+
+/*
+ * nss_capwap_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_capwap_log_rx_msg(struct nss_capwap_msg *ncm)
+{
+	if (ncm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ncm);
+		return;
+	}
+
+	if (ncm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ncm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ncm, ncm->cm.type,
+			nss_capwap_log_message_types_str[ncm->cm.type],
+			ncm->cm.response, nss_cmn_response_str[ncm->cm.response]);
+		goto verbose;
+	}
+
+	if (ncm->cm.error >= NSS_CAPWAP_ERROR_MSG_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			ncm, ncm->cm.type, nss_capwap_log_message_types_str[ncm->cm.type],
+			ncm->cm.response, nss_cmn_response_str[ncm->cm.response],
+			ncm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		ncm, ncm->cm.type, nss_capwap_log_message_types_str[ncm->cm.type],
+		ncm->cm.response, nss_cmn_response_str[ncm->cm.response],
+		ncm->cm.error, nss_capwap_log_error_response_types_str[ncm->cm.error]);
+
+verbose:
+	nss_capwap_log_verbose(ncm);
+}
diff --git a/qca-nss-drv/nss_capwap_log.h b/qca-nss-drv/nss_capwap_log.h
new file mode 100644
index 0000000..f620989
--- /dev/null
+++ b/qca-nss-drv/nss_capwap_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_CAPWAP_LOG_H__
+#define __NSS_CAPWAP_LOG_H__
+
+/*
+ * nss_capwap_log.h
+ *	NSS CAPWAP Log Header File.
+ */
+
+/*
+ * nss_capwap_log_tx_msg
+ *	Logs a CAPWAP message that is sent to the NSS firmware.
+ */
+void nss_capwap_log_tx_msg(struct nss_capwap_msg *ncm);
+
+/*
+ * nss_capwap_log_rx_msg
+ *	Logs a CAPWAP message that is received from the NSS firmware.
+ */
+void nss_capwap_log_rx_msg(struct nss_capwap_msg *ncm);
+
+#endif /* __NSS_CAPWAP_LOG_H__ */
diff --git a/qca-nss-drv/nss_capwap_stats.c b/qca-nss-drv/nss_capwap_stats.c
new file mode 100644
index 0000000..1d43878
--- /dev/null
+++ b/qca-nss-drv/nss_capwap_stats.c
@@ -0,0 +1,313 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_drv_stats.h"
+#include "nss_core.h"
+#include "nss_capwap.h"
+#include "nss_capwap_stats.h"
+#include "nss_capwap_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_capwap_stats_notifier);
+
+/*
+ * nss_capwap_stats_encap()
+ *	Make a row for CAPWAP encap stats.
+ */
+static ssize_t nss_capwap_stats_encap(char *line, int len, int i, struct nss_capwap_tunnel_stats *s)
+{
+	uint64_t tcnt = 0;
+
+	switch (i) {
+	case 0:
+		tcnt = s->pnode_stats.tx_packets;
+		break;
+	case 1:
+		tcnt = s->pnode_stats.tx_bytes;
+		break;
+	case 2:
+		tcnt = s->tx_segments;
+		break;
+	case 3:
+		tcnt = s->tx_dropped_sg_ref;
+		break;
+	case 4:
+		tcnt = s->tx_dropped_ver_mis;
+		break;
+	case 5:
+		tcnt = s->tx_dropped_inner;
+		break;
+	case 6:
+		tcnt = s->tx_dropped_hroom;
+		break;
+	case 7:
+		tcnt = s->tx_dropped_dtls;
+		break;
+	case 8:
+		tcnt = s->tx_dropped_nwireless;
+		break;
+	case 9:
+		tcnt = s->tx_queue_full_drops;
+		break;
+	case 10:
+		tcnt = s->tx_mem_failure_drops;
+		break;
+	case 11:
+		tcnt = s->fast_mem;
+		break;
+	default:
+		return 0;
+	}
+
+	return snprintf(line, len, "%s = %llu\n", nss_capwap_strings_encap_stats[i].stats_name, tcnt);
+}
+
+/*
+ * nss_capwap_stats_decap()
+ *	Make a row for CAPWAP decap stats.
+ */
+static ssize_t nss_capwap_stats_decap(char *line, int len, int i, struct nss_capwap_tunnel_stats *s)
+{
+	uint64_t tcnt = 0;
+
+	switch (i) {
+	case 0:
+		tcnt = s->pnode_stats.rx_packets;
+		break;
+	case 1:
+		tcnt = s->pnode_stats.rx_bytes;
+		break;
+	case 2:
+		tcnt = s->dtls_pkts;
+		break;
+	case 3:
+		tcnt = s->rx_segments;
+		break;
+	case 4:
+		tcnt = s->pnode_stats.rx_dropped;
+		break;
+	case 5:
+		tcnt = s->rx_oversize_drops;
+		break;
+	case 6:
+		tcnt = s->rx_frag_timeout_drops;
+		break;
+	case 7:
+		tcnt = s->rx_dup_frag;
+		break;
+	case 8:
+		tcnt = s->rx_frag_gap_drops;
+		break;
+	case 9:
+		tcnt = s->rx_n2h_drops;
+		return snprintf(line, len, "%s = %llu (n2h = %llu)\n", nss_capwap_strings_decap_stats[i].stats_name, tcnt, s->rx_n2h_queue_full_drops);
+	case 10:
+		tcnt = s->rx_n2h_queue_full_drops;
+		break;
+	case 11:
+		tcnt = s->rx_mem_failure_drops;
+		break;
+	case 12:
+		tcnt = s->rx_csum_drops;
+		break;
+	case 13:
+		tcnt = s->rx_malformed;
+		break;
+	case 14:
+		tcnt = s->fast_mem;
+		break;
+	default:
+		return 0;
+	}
+
+	return snprintf(line, len, "%s = %llu\n", nss_capwap_strings_decap_stats[i].stats_name, tcnt);
+}
+
+/*
+ * nss_capwap_stats_read()
+ *	Read CAPWAP stats
+ */
+static ssize_t nss_capwap_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos, uint16_t type)
+{
+	struct nss_stats_data *data = fp->private_data;
+	ssize_t bytes_read = 0;
+	struct nss_capwap_tunnel_stats stats;
+	size_t bytes;
+	char line[80];
+	int start;
+	uint32_t if_num = NSS_DYNAMIC_IF_START;
+	uint32_t max_if_num = NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES;
+
+	if (data) {
+		if_num = data->if_num;
+	}
+
+	/*
+	 * If we are done accomodating all the CAPWAP tunnels.
+	 */
+	if (if_num > max_if_num) {
+		return 0;
+	}
+
+	for (; if_num <= max_if_num; if_num++) {
+		bool isthere;
+		enum nss_dynamic_interface_type dtype;
+
+		if (nss_is_dynamic_interface(if_num) == false) {
+			continue;
+		}
+
+		dtype = nss_dynamic_interface_get_type(nss_capwap_get_ctx(), if_num);
+
+		/*
+		 * Read encap stats from inner node and decap stats from outer node.
+		 */
+		if ((type == 1) && (dtype != NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_HOST_INNER)) {
+			continue;
+		}
+
+		if ((type == 0) && (dtype != NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_OUTER)) {
+			continue;
+		}
+
+		/*
+		 * If CAPWAP tunnel does not exists, then isthere will be false.
+		 */
+		isthere = nss_capwap_get_stats(if_num, &stats);
+		if (!isthere) {
+			continue;
+		}
+
+		bytes = snprintf(line, sizeof(line), "----if_num : %2d----\n", if_num);
+		if ((bytes_read + bytes) > sz) {
+			break;
+		}
+
+		if (copy_to_user(ubuf + bytes_read, line, bytes) != 0) {
+			bytes_read = -EFAULT;
+			goto fail;
+		}
+		bytes_read += bytes;
+		start = 0;
+		while (bytes_read < sz) {
+			if (type == 1) {
+				bytes = nss_capwap_stats_encap(line, sizeof(line), start, &stats);
+			} else {
+				bytes = nss_capwap_stats_decap(line, sizeof(line), start, &stats);
+			}
+
+			/*
+			 * If we don't have any more lines in decap/encap.
+			 */
+			if (bytes == 0) {
+				break;
+			}
+
+			if ((bytes_read + bytes) > sz)
+				break;
+
+			if (copy_to_user(ubuf + bytes_read, line, bytes) != 0) {
+				bytes_read = -EFAULT;
+				goto fail;
+			}
+
+			bytes_read += bytes;
+			start++;
+		}
+	}
+
+	if (bytes_read > 0) {
+		*ppos = bytes_read;
+	}
+
+	if (data) {
+		data->if_num = if_num;
+	}
+fail:
+	return bytes_read;
+}
+
+/*
+ * nss_capwap_decap_stats_read()
+ *	Read CAPWAP decap stats
+ */
+static ssize_t nss_capwap_decap_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_capwap_stats_read(fp, ubuf, sz, ppos, 0);
+}
+
+/*
+ * nss_capwap_encap_stats_read()
+ *	Read CAPWAP encap stats
+ */
+static ssize_t nss_capwap_encap_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_capwap_stats_read(fp, ubuf, sz, ppos, 1);
+}
+
+/*
+ * nss_capwap_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(capwap_encap);
+NSS_STATS_DECLARE_FILE_OPERATIONS(capwap_decap);
+
+/*
+ * nss_capwap_stats_dentry_create()
+ *	Create CAPWAP statistics debug entry
+ */
+void nss_capwap_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("capwap_encap", &nss_capwap_encap_stats_ops);
+	nss_stats_create_dentry("capwap_decap", &nss_capwap_decap_stats_ops);
+}
+
+/*
+ * nss_capwap_stats_notify()
+ *	Sends notifications to the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_capwap_stats_notify(uint32_t if_num, uint32_t core_id)
+{
+	struct nss_capwap_stats_notification capwap_stats;
+
+	capwap_stats.core_id = core_id;
+	capwap_stats.if_num = if_num;
+	nss_capwap_get_stats(if_num, &capwap_stats.stats);
+	atomic_notifier_call_chain(&nss_capwap_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&capwap_stats);
+}
+
+/*
+ * nss_capwap_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_capwap_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_capwap_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_capwap_stats_register_notifier);
+
+/*
+ * nss_capwap_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_capwap_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_capwap_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_capwap_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_capwap_stats.h b/qca-nss-drv/nss_capwap_stats.h
new file mode 100644
index 0000000..c1033ec
--- /dev/null
+++ b/qca-nss-drv/nss_capwap_stats.h
@@ -0,0 +1,26 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2017,2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_CAPWAP_STATS_H__
+#define __NSS_CAPWAP_STATS_H__
+
+/*
+ * CAPWAP statistics APIs
+ */
+extern void nss_capwap_stats_notify(uint32_t if_num, uint32_t core_id);
+extern void nss_capwap_stats_dentry_create(void);
+
+#endif /* __NSS_CAPWAP_STATS_H__ */
diff --git a/qca-nss-drv/nss_capwap_strings.c b/qca-nss-drv/nss_capwap_strings.c
new file mode 100644
index 0000000..266cd50
--- /dev/null
+++ b/qca-nss-drv/nss_capwap_strings.c
@@ -0,0 +1,102 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include <nss_capwap.h>
+#include "nss_strings.h"
+#include "nss_capwap_strings.h"
+
+/*
+ * nss_capwap_strings_encap_stats
+ *	CAPWAP encap statistics string.
+ */
+struct nss_stats_info nss_capwap_strings_encap_stats[NSS_CAPWAP_STATS_ENCAP_MAX] = {
+	{"tx_packets",		NSS_STATS_TYPE_COMMON},
+	{"tx_bytes",		NSS_STATS_TYPE_COMMON},
+	{"tx_segments",		NSS_STATS_TYPE_SPECIAL},
+	{"tx_drop_seg_ref",	NSS_STATS_TYPE_DROP},
+	{"tx_drop_ver_mismatch",NSS_STATS_TYPE_DROP},
+	{"tx_dropped_inner",	NSS_STATS_TYPE_DROP},
+	{"tx_drop_hroom",	NSS_STATS_TYPE_DROP},
+	{"tx_drop_DTLS",	NSS_STATS_TYPE_DROP},
+	{"tx_drop_nwireless",	NSS_STATS_TYPE_DROP},
+	{"tx_drop_qfull",	NSS_STATS_TYPE_DROP},
+	{"tx_drop_mem_fail",	NSS_STATS_TYPE_DROP},
+	{"fast_mem",		NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_capwap_encap_strings_read()
+ *	Read CAPWAP encap statistics names.
+ */
+static ssize_t nss_capwap_encap_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_capwap_strings_encap_stats, NSS_CAPWAP_STATS_ENCAP_MAX);
+}
+
+/*
+ * nss_capwap_encap_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(capwap_encap);
+
+/*
+ * nss_capwap_strings_decap_stats
+ *	CAPWAP decap statistics string.
+ */
+struct nss_stats_info nss_capwap_strings_decap_stats[NSS_CAPWAP_STATS_DECAP_MAX] = {
+	{"rx_packets",		NSS_STATS_TYPE_COMMON},
+	{"rx_bytes",		NSS_STATS_TYPE_COMMON},
+	{"rx_DTLS_pkts",	NSS_STATS_TYPE_SPECIAL},
+	{"rx_segments",		NSS_STATS_TYPE_SPECIAL},
+	{"rx_dropped",		NSS_STATS_TYPE_DROP},
+	{"rx_drop_oversize",	NSS_STATS_TYPE_DROP},
+	{"rx_drop_frag_timeout",NSS_STATS_TYPE_DROP},
+	{"rx_drop_frag_dup",	NSS_STATS_TYPE_DROP},
+	{"rx_drop_frag_gap",	NSS_STATS_TYPE_DROP},
+	{"rx_drop_n2h",		NSS_STATS_TYPE_DROP},
+	{"rx_drop_n2h_qfull",	NSS_STATS_TYPE_DROP},
+	{"rx_drop_mem_fail",	NSS_STATS_TYPE_DROP},
+	{"rx_drop_csum",	NSS_STATS_TYPE_DROP},
+	{"rx_drop_malformed",	NSS_STATS_TYPE_DROP},
+	{"fast_mem",		NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_capwap_decap_strings_read()
+ *	Read CAPWAP decap statistics names.
+ */
+static ssize_t nss_capwap_decap_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_capwap_strings_decap_stats, NSS_CAPWAP_STATS_DECAP_MAX);
+}
+
+/*
+ * nss_capwap_decap_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(capwap_decap);
+
+/*
+ * nss_capwap_strings_dentry_create()
+ *	Create CAPWAP statistics strings debug entry.
+ */
+void nss_capwap_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("capwap_encap", &nss_capwap_encap_strings_ops);
+	nss_strings_create_dentry("capwap_decap", &nss_capwap_decap_strings_ops);
+}
diff --git a/qca-nss-drv/nss_capwap_strings.h b/qca-nss-drv/nss_capwap_strings.h
new file mode 100644
index 0000000..96f89cd
--- /dev/null
+++ b/qca-nss-drv/nss_capwap_strings.h
@@ -0,0 +1,28 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_CAPWAP_STRINGS_H
+#define __NSS_CAPWAP_STRINGS_H
+
+#include "nss_capwap_stats.h"
+
+extern struct nss_stats_info nss_capwap_strings_encap_stats[NSS_CAPWAP_STATS_ENCAP_MAX];
+extern struct nss_stats_info nss_capwap_strings_decap_stats[NSS_CAPWAP_STATS_DECAP_MAX];
+extern void nss_capwap_strings_dentry_create(void);
+
+#endif /* __NSS_CAPWAP_STRINGS_H */
diff --git a/qca-nss-drv/nss_clmap.c b/qca-nss-drv/nss_clmap.c
new file mode 100644
index 0000000..777b719
--- /dev/null
+++ b/qca-nss-drv/nss_clmap.c
@@ -0,0 +1,346 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+ /*
+  * nss_clmap.c
+  *	NSS clmap driver interface APIs
+  */
+#include "nss_core.h"
+#include "nss_clmap.h"
+#include "nss_cmn.h"
+#include "nss_tx_rx_common.h"
+#include "nss_clmap_stats.h"
+#include "nss_clmap_strings.h"
+#include "nss_clmap_log.h"
+
+#define NSS_CLMAP_TX_TIMEOUT 3000
+
+/*
+ * Private data structure
+ */
+static struct nss_clmap_pvt {
+	struct semaphore sem;		/* Semaphore structure. */
+	struct completion complete;	/* Completion structure. */
+	int response;			/* Response from FW. */
+	void *cb;			/* Original cb for msgs. */
+	void *app_data;			/* Original app_data for msgs. */
+} clmap_pvt;
+
+/*
+ * nss_clmap_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static bool nss_clmap_verify_if_num(uint32_t if_num)
+{
+	uint32_t type = nss_dynamic_interface_get_type(nss_clmap_get_ctx(), if_num);
+
+	return ((type == NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US) ||
+				(type == NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_DS));
+}
+
+/*
+ * nss_clmap_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_clmap_callback(void *app_data, struct nss_clmap_msg *nclm)
+{
+	clmap_pvt.response = NSS_TX_SUCCESS;
+	clmap_pvt.cb = NULL;
+	clmap_pvt.app_data = NULL;
+
+	if (nclm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("clmap Error response %d\n", nclm->cm.response);
+		clmap_pvt.response = nclm->cm.response;
+	}
+
+	/*
+	 * Write memory barrier.
+	 */
+	smp_wmb();
+	complete(&clmap_pvt.complete);
+}
+
+/*
+ * nss_clmap_handler()
+ *	Handle NSS -> HLOS messages for clmap.
+ */
+static void nss_clmap_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_clmap_msg *nclm = (struct nss_clmap_msg *)ncm;
+	nss_clmap_msg_callback_t cb;
+
+	BUG_ON(!nss_clmap_verify_if_num(ncm->interface));
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_CLMAP_MSG_TYPE_MAX) {
+		nss_warning("%px: received invalid message %d for clmap interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_clmap_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+	nss_clmap_log_rx_msg(nclm);
+
+	switch (nclm->cm.type) {
+	case NSS_CLMAP_MSG_TYPE_SYNC_STATS:
+		nss_clmap_stats_sync(nss_ctx, &nclm->msg.stats, ncm->interface);
+		nss_clmap_stats_notify(nss_ctx, ncm->interface);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->nss_rx_interface_handlers[ncm->interface].app_data;
+	}
+
+	/*
+	 * Do we have a callback
+	 */
+	cb = (nss_clmap_msg_callback_t)ncm->cb;
+	if (!cb) {
+		nss_trace("%px: cb is null for interface %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb((void *)ncm->app_data, ncm);
+}
+
+/*
+ * nss_clmap_tx_msg()
+ *	Transmit a clmap message to NSS FW. Don't call this from softirq/interrupts.
+ */
+nss_tx_status_t nss_clmap_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_clmap_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	if (!nss_clmap_verify_if_num(msg->cm.interface)) {
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	if (ncm->type >= NSS_CLMAP_MSG_TYPE_MAX) {
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_clmap_log_tx_msg(msg);
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_clmap_tx_msg);
+
+/*
+ * nss_clmap_tx_msg_sync()
+ *	Transmit a clmap message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_clmap_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_clmap_msg *nclm)
+{
+	nss_tx_status_t status;
+	int ret;
+
+	down(&clmap_pvt.sem);
+	nclm->cm.cb = (nss_ptr_t)nss_clmap_callback;
+	nclm->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_clmap_tx_msg(nss_ctx, nclm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: clmap_tx_msg failed\n", nss_ctx);
+		up(&clmap_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&clmap_pvt.complete, msecs_to_jiffies(NSS_CLMAP_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: clmap tx sync failed due to timeout\n", nss_ctx);
+		clmap_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = clmap_pvt.response;
+	up(&clmap_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_clmap_tx_msg_sync);
+
+/*
+ * nss_clmap_tx_buf()
+ *	Transmit data buffer (skb) to a NSS interface number
+ */
+nss_tx_status_t nss_clmap_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *buf, uint32_t if_num)
+{
+	BUG_ON(!nss_clmap_verify_if_num(if_num));
+
+	return nss_core_send_packet(nss_ctx, buf, if_num, H2N_BIT_FLAG_VIRTUAL_BUFFER);
+}
+EXPORT_SYMBOL(nss_clmap_tx_buf);
+
+/*
+ * nss_clmap_unregister()
+ * 	Un-register a clmap interface from NSS.
+ */
+bool nss_clmap_unregister(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx;
+	int status;
+
+	nss_ctx = nss_clmap_get_ctx();
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_clmap_verify_if_num(if_num)) {
+		nss_warning("%px: clmap unregister request received for invalid interface %d", nss_ctx, if_num);
+		return false;
+	}
+
+	status = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Failed to unregister handler for clmap NSS I/F:%u\n", nss_ctx, if_num);
+		return false;
+	}
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+	nss_core_unregister_handler(nss_ctx, if_num);
+	nss_clmap_stats_session_unregister(if_num);
+
+	return true;
+}
+EXPORT_SYMBOL(nss_clmap_unregister);
+
+/*
+ * nss_clmap_register()
+ * 	Registers a clmap interface with the NSS.
+ */
+struct nss_ctx_instance *nss_clmap_register(uint32_t if_num,
+						uint32_t di_type,
+						nss_clmap_buf_callback_t data_cb,
+						nss_clmap_msg_callback_t notify_cb,
+						struct net_device *netdev,
+						uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx;
+	int core_status;
+	bool stats_status = false;
+
+	nss_ctx = nss_clmap_get_ctx();
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_clmap_verify_if_num(if_num)) {
+		nss_warning("%px: clmap register request received for invalid interface %d", nss_ctx, if_num);
+		goto fail;
+	}
+
+	if (di_type == NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US) {
+		stats_status = nss_clmap_stats_session_register(if_num, NSS_CLMAP_INTERFACE_TYPE_US, netdev);
+	} else {
+		stats_status = nss_clmap_stats_session_register(if_num, NSS_CLMAP_INTERFACE_TYPE_DS, netdev);
+	}
+
+	if (!stats_status) {
+		nss_warning("%px: statistics registration failed for interface: %d\n", nss_ctx, if_num);
+		goto fail;
+	}
+
+	core_status = nss_core_register_handler(nss_ctx, if_num, nss_clmap_msg_handler, (void *)netdev);
+	if (core_status != NSS_CORE_STATUS_SUCCESS) {
+		goto core_reg_fail;
+	}
+
+	core_status = nss_core_register_msg_handler(nss_ctx, if_num, notify_cb);
+	if (core_status != NSS_CORE_STATUS_SUCCESS) {
+		goto msg_reg_fail;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, data_cb, NULL, (void *)netdev, netdev, features);
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num, di_type);
+
+	return nss_ctx;
+
+msg_reg_fail:
+	nss_core_unregister_handler(nss_ctx, if_num);
+core_reg_fail:
+	nss_clmap_stats_session_unregister(if_num);
+	nss_warning("%px: NSS core register handler failed for if_num:%d with error :%d", nss_ctx, if_num, core_status);
+fail:
+	return NULL;
+
+}
+EXPORT_SYMBOL(nss_clmap_register);
+
+/*
+ * nss_clmap_ifnum_with_core_id()
+ *	Append core ID to clmap interface num.
+ */
+int nss_clmap_ifnum_with_core_id(int if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_clmap_get_ctx();
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	if (!nss_is_dynamic_interface(if_num)) {
+		nss_warning("%px: Invalid if_num: %d, must be a dynamic interface\n", nss_ctx, if_num);
+		return 0;
+	}
+	return NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_clmap_ifnum_with_core_id);
+
+/*
+ * nss_clmap_msg_init()
+ *	Initialize clmap message.
+ */
+void nss_clmap_msg_init(struct nss_clmap_msg *ncm, uint16_t if_num, uint32_t type, uint32_t len,
+				nss_clmap_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, (void*)cb, app_data);
+}
+EXPORT_SYMBOL(nss_clmap_msg_init);
+
+/*
+ * nss_clmap_get_ctx()
+ *	Return a clmap NSS context.
+ */
+struct nss_ctx_instance *nss_clmap_get_ctx()
+{
+	struct nss_ctx_instance *nss_ctx;
+
+	nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.clmap_handler_id];
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_clmap_get_ctx);
+
+/*
+ * nss_clmap_init()
+ *	Initializes clmap. Gets called from nss_init.c.
+ */
+void nss_clmap_init()
+{
+	sema_init(&clmap_pvt.sem, 1);
+	init_completion(&clmap_pvt.complete);
+
+	nss_clmap_stats_dentry_create();
+	nss_clmap_strings_dentry_create();
+}
diff --git a/qca-nss-drv/nss_clmap_log.c b/qca-nss-drv/nss_clmap_log.c
new file mode 100644
index 0000000..45cb0a7
--- /dev/null
+++ b/qca-nss-drv/nss_clmap_log.c
@@ -0,0 +1,207 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_clmap_log.c
+ *	NSS clmap logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_clmap_log_message_types_str
+ *	clmap message strings
+ */
+static char *nss_clmap_log_message_types_str[NSS_CLMAP_MSG_TYPE_MAX] __maybe_unused = {
+	"Clmap sync stats",
+	"Clmap enable interface",
+	"Clmap disable interface",
+	"Clmap add MAC rule",
+	"Clmap delete MAC rule",
+	"Clmap flush MAC rule"
+};
+
+/*
+ * nss_clmap_log_error_types_str
+ *	Strings for error types for clmap messages
+ */
+static char *nss_clmap_log_error_types_str[NSS_CLMAP_ERROR_MAX] __maybe_unused = {
+	"Clmap unknown error",
+	"Clmap interface disabled",
+	"Clmap interface enabled",
+	"Clmap invalid VLAN",
+	"Clmap invalid tunnel ID",
+	"Clmap MAC table full",
+	"Clmap MAC exists",
+	"Clmap MAC does not exist",
+	"Clmap MAC entry unhashed",
+	"Clmap MAC entry insert failed",
+	"Clmap MAC entry alloc failed",
+	"Clmap MAC entry delete failed"
+};
+
+/*
+ * nss_clmap_log_mac_msg()
+ *	Log NSS clmap MAC rule message.
+ */
+static void nss_clmap_log_mac_msg(struct nss_clmap_mac_msg *npvcm)
+{
+	nss_trace("%px: NSS clmap MAC message \n"
+		"Clmap Mac Addr: %x : %x : %x"
+		"Clmap Flags: %u\n"
+		"Clmap VLAN ID: %u\n"
+		"Clmap Next-hop Interface Number: %d\n",
+		npvcm,
+		npvcm->mac_addr[0], npvcm->mac_addr[1],
+		npvcm->mac_addr[2], npvcm->flags,
+		npvcm->vlan_id, npvcm->nexthop_ifnum);
+}
+
+/*
+ * nss_clmap_log_interface_enable_msg()
+ *	Log NSS clmap rule enable message.
+ */
+static void nss_clmap_log_interface_enable_msg(struct nss_clmap_msg *npvm)
+{
+	nss_trace("%px: NSS clmap interface state message: Enable \n", npvm);
+}
+
+/*
+ * nss_clmap_log_interface_disable_msg()
+ *	Log NSS clmap rule disable message.
+ */
+static void nss_clmap_log_interface_disable_msg(struct nss_clmap_msg *npvm)
+{
+	nss_trace("%px: NSS clmap interface state message: Disable \n", npvm);
+}
+
+/*
+ * nss_clmap_log_mac_add_msg()
+ *	Log NSS clmap mac rule add message.
+ */
+static void nss_clmap_log_mac_add_msg(struct nss_clmap_msg *npvm)
+{
+	struct nss_clmap_mac_msg *npvcm __maybe_unused = &npvm->msg.mac_add;
+	nss_clmap_log_mac_msg(npvcm);
+}
+
+/*
+ * nss_clmap_log_mac_del_msg()
+ *	Log NSS clmap mac rule del message.
+ */
+static void nss_clmap_log_mac_del_msg(struct nss_clmap_msg *npvm)
+{
+	struct nss_clmap_mac_msg *npvcm __maybe_unused = &npvm->msg.mac_del;
+	nss_clmap_log_mac_msg(npvcm);
+}
+
+/*
+ * nss_clmap_log_mac_flush_msg()
+ *	Log NSS clmap mac rule flush message.
+ */
+static void nss_clmap_log_mac_flush_msg(struct nss_clmap_msg *npvm)
+{
+	struct nss_clmap_flush_mac_msg *npvcm __maybe_unused = &npvm->msg.mac_flush;
+	nss_trace("%px: NSS clmap MAC flush message \n"
+		"Clmap Next-hop Interface Number: %d\n",
+		npvcm, npvcm->nexthop_ifnum);
+}
+
+/*
+ * nss_clmap_log_verbose()
+ *	Log message contents.
+ */
+static void nss_clmap_log_verbose(struct nss_clmap_msg *npvm)
+{
+	switch (npvm->cm.type) {
+	case NSS_CLMAP_MSG_TYPE_INTERFACE_ENABLE:
+		nss_clmap_log_interface_enable_msg(npvm);
+		break;
+
+	case NSS_CLMAP_MSG_TYPE_INTERFACE_DISABLE:
+		nss_clmap_log_interface_disable_msg(npvm);
+		break;
+
+	case NSS_CLMAP_MSG_TYPE_MAC_ADD:
+		nss_clmap_log_mac_add_msg(npvm);
+		break;
+
+	case NSS_CLMAP_MSG_TYPE_MAC_DEL:
+		nss_clmap_log_mac_del_msg(npvm);
+		break;
+
+	case NSS_CLMAP_MSG_TYPE_MAC_FLUSH:
+		nss_clmap_log_mac_flush_msg(npvm);
+		break;
+
+	case NSS_CLMAP_MSG_TYPE_SYNC_STATS:
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", npvm);
+		break;
+	}
+}
+
+/*
+ * nss_clmap_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_clmap_log_tx_msg(struct nss_clmap_msg *npvm)
+{
+	if (npvm->cm.type >= NSS_CLMAP_MSG_TYPE_MAX) {
+		nss_warning("%px: Invalid message type\n", npvm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", npvm, npvm->cm.type, nss_clmap_log_message_types_str[npvm->cm.type]);
+	nss_clmap_log_verbose(npvm);
+}
+
+/*
+ * nss_clmap_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_clmap_log_rx_msg(struct nss_clmap_msg *npvm)
+{
+	if (npvm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", npvm);
+		return;
+	}
+
+	if (npvm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (npvm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", npvm, npvm->cm.type,
+			nss_clmap_log_message_types_str[npvm->cm.type],
+			npvm->cm.response, nss_cmn_response_str[npvm->cm.response]);
+		goto verbose;
+	}
+
+	if (npvm->cm.error >= NSS_CLMAP_ERROR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			npvm, npvm->cm.type, nss_clmap_log_message_types_str[npvm->cm.type],
+			npvm->cm.response, nss_cmn_response_str[npvm->cm.response],
+			npvm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		npvm, npvm->cm.type, nss_clmap_log_message_types_str[npvm->cm.type],
+		npvm->cm.response, nss_cmn_response_str[npvm->cm.response],
+		npvm->cm.error, nss_clmap_log_error_types_str[npvm->cm.error]);
+
+verbose:
+	nss_clmap_log_verbose(npvm);
+}
diff --git a/qca-nss-drv/nss_clmap_log.h b/qca-nss-drv/nss_clmap_log.h
new file mode 100644
index 0000000..6d193d3
--- /dev/null
+++ b/qca-nss-drv/nss_clmap_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_CLMAP_LOG_H__
+#define __NSS_CLMAP_LOG_H__
+
+/*
+ * nss_clmap_log.h
+ *	NSS clmap Log Header File.
+ */
+
+/*
+ * nss_clmap_log_tx_msg
+ *	Logs a clmap message that is sent to the NSS firmware.
+ */
+void nss_clmap_log_tx_msg(struct nss_clmap_msg *ncm);
+
+/*
+ * nss_clmap_log_rx_msg
+ *	Logs a clmap message that is received from the NSS firmware.
+ */
+void nss_clmap_log_rx_msg(struct nss_clmap_msg *ncm);
+
+#endif /* __NSS_CLMAP_LOG_H__ */
diff --git a/qca-nss-drv/nss_clmap_stats.c b/qca-nss-drv/nss_clmap_stats.c
new file mode 100644
index 0000000..a75bfff
--- /dev/null
+++ b/qca-nss-drv/nss_clmap_stats.c
@@ -0,0 +1,296 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_clmap.h"
+#include "nss_clmap_stats.h"
+#include "nss_clmap_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_clmap_stats_notifier);
+
+/*
+ * Spinlock to protect clmap statistics update/read
+ */
+DEFINE_SPINLOCK(nss_clmap_stats_lock);
+
+struct nss_clmap_stats *stats_db[NSS_CLMAP_MAX_DEBUG_INTERFACES] = {NULL};
+
+/*
+ * nss_clmap_interface_type_str
+ *	Clmap interface type string.
+ */
+static char *nss_clmap_interface_type_str[NSS_CLMAP_INTERFACE_TYPE_MAX] = {
+	"Upstream",
+	"Downstream"
+};
+
+/*
+ * nss_clmap_stats_session_unregister
+ *	Unregister debug statistic for clmap session.
+ */
+void nss_clmap_stats_session_unregister(uint32_t if_num)
+{
+	uint32_t i;
+
+	spin_lock_bh(&nss_clmap_stats_lock);
+	for (i = 0; i < NSS_CLMAP_MAX_DEBUG_INTERFACES; i++) {
+		if (stats_db[i] && (stats_db[i]->nss_if_num == if_num)) {
+			kfree(stats_db[i]);
+			stats_db[i] = NULL;
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_clmap_stats_lock);
+}
+
+/*
+ * nss_clmap_stats_session_register
+ * 	Register debug statistic for clmap session.
+ */
+bool nss_clmap_stats_session_register(uint32_t if_num, uint32_t if_type, struct net_device *netdev)
+{
+	uint32_t i;
+	bool stats_status = false;
+
+	if (!netdev) {
+		nss_warning("Could not allocate statistics memory as the net device is NULL!\n");
+		return stats_status;
+	}
+
+	spin_lock_bh(&nss_clmap_stats_lock);
+	for (i = 0; i < NSS_CLMAP_MAX_DEBUG_INTERFACES; i++) {
+		if (!stats_db[i]) {
+			stats_db[i] = (struct nss_clmap_stats *)kzalloc(sizeof(struct nss_clmap_stats), GFP_KERNEL);
+			if (!stats_db[i]) {
+				nss_warning("%px: could not allocate memory for statistics database for interface id: %d\n", netdev, if_num);
+				break;
+			}
+			stats_db[i]->valid = true;
+			stats_db[i]->nss_if_num = if_num;
+			stats_db[i]->nss_if_type = if_type;
+			stats_db[i]->if_index = netdev->ifindex;
+			stats_status = true;
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_clmap_stats_lock);
+	return stats_status;
+}
+
+/*
+ * nss_clmap_get_debug_stats()
+ *	Get clmap debug statistics.
+ */
+static int nss_clmap_get_debug_stats(struct nss_clmap_stats *stats)
+{
+	uint32_t i;
+	int interface_cnt = 0;
+
+	spin_lock_bh(&nss_clmap_stats_lock);
+	for (i = 0; i < NSS_CLMAP_MAX_DEBUG_INTERFACES; i++) {
+		if (stats_db[i]) {
+			memcpy(stats, stats_db[i], sizeof(struct nss_clmap_stats));
+			stats++;
+			interface_cnt++;
+		}
+	}
+	spin_unlock_bh(&nss_clmap_stats_lock);
+
+	return interface_cnt;
+}
+
+/*
+ * nss_clmap_stats_read()
+ *	Read clmap statistics
+ */
+static ssize_t nss_clmap_stats_read(struct file *fp, char __user *ubuf,
+					size_t sz, loff_t *ppos)
+{
+	uint32_t max_output_lines = (NSS_CLMAP_INTERFACE_STATS_MAX * NSS_CLMAP_MAX_DEBUG_INTERFACES) + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	struct net_device *dev;
+	uint32_t id;
+	struct nss_clmap_stats *clmap_stats = NULL;
+	int interface_cnt;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	/*
+	 * Allocate statistics memory only for all interfaces.
+	 */
+	clmap_stats = kzalloc((NSS_CLMAP_MAX_DEBUG_INTERFACES * sizeof(struct nss_clmap_stats)), GFP_KERNEL);
+	if (unlikely(!clmap_stats)) {
+		nss_warning("Could not allocate memory for populating clmap statistics\n");
+		kfree(lbuf);
+		return 0;
+	}
+
+	/*
+	 * Get clmap statistics.
+	 */
+	interface_cnt = nss_clmap_get_debug_stats(clmap_stats);
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "clmap stats", NSS_STATS_SINGLE_CORE);
+	for (id = 0; id < interface_cnt; id++) {
+		struct nss_clmap_stats *clmsp = clmap_stats + id;
+
+		if (unlikely(!clmsp->valid)) {
+			continue;
+		}
+
+		dev = dev_get_by_index(&init_net, clmsp->if_index);
+		if (unlikely(!dev)) {
+			nss_warning("No netdev available for nss interface id:%d\n", clmsp->nss_if_num);
+			continue;
+		}
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%d. nss interface id=%d, interface type=%s, netdevice=%s\n", id,
+				clmsp->nss_if_num, nss_clmap_interface_type_str[clmsp->nss_if_type], dev->name);
+		dev_put(dev);
+
+		size_wr += nss_stats_print("clmap", NULL, NSS_STATS_SINGLE_INSTANCE, nss_clmap_strings_stats,
+						clmsp->stats, NSS_CLMAP_INTERFACE_STATS_MAX, lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	kfree(clmap_stats);
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_clmap_stats_sync()
+ *	Sync function for clmap statistics
+ */
+void nss_clmap_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_clmap_stats_msg *stats_msg, uint32_t if_num)
+{
+	uint32_t i;
+	struct nss_clmap_stats *s = NULL;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	spin_lock_bh(&nss_clmap_stats_lock);
+	for (i = 0; i < NSS_CLMAP_MAX_DEBUG_INTERFACES; i++) {
+		if (stats_db[i] && (stats_db[i]->nss_if_num == if_num)) {
+			s = stats_db[i];
+			break;
+		}
+	}
+
+	if (!s) {
+		spin_unlock_bh(&nss_clmap_stats_lock);
+		nss_warning("%px: Interface not found: %u", nss_ctx, if_num);
+		return;
+	}
+
+        s->stats[NSS_CLMAP_INTERFACE_STATS_RX_PKTS] += stats_msg->node_stats.rx_packets;
+        s->stats[NSS_CLMAP_INTERFACE_STATS_RX_BYTES] += stats_msg->node_stats.rx_bytes;
+        s->stats[NSS_CLMAP_INTERFACE_STATS_TX_PKTS] += stats_msg->node_stats.tx_packets;
+        s->stats[NSS_CLMAP_INTERFACE_STATS_TX_BYTES] += stats_msg->node_stats.tx_bytes;
+
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		s->stats[NSS_CLMAP_INTERFACE_STATS_RX_QUEUE_0_DROPPED + i] += stats_msg->node_stats.rx_dropped[i];
+	}
+
+	s->stats[NSS_CLMAP_INTERFACE_STATS_DROPPED_MACDB_LOOKUP_FAILED] += stats_msg->dropped_macdb_lookup_failed;
+	s->stats[NSS_CLMAP_INTERFACE_STATS_DROPPED_INVALID_PACKET_SIZE] += stats_msg->dropped_invalid_packet_size;
+	s->stats[NSS_CLMAP_INTERFACE_STATS_DROPPED_LOW_HEADROOM] += stats_msg->dropped_low_hroom;
+	s->stats[NSS_CLMAP_INTERFACE_STATS_DROPPED_NEXT_NODE_QUEUE_FULL] += stats_msg->dropped_next_node_queue_full;
+	s->stats[NSS_CLMAP_INTERFACE_STATS_DROPPED_PBUF_ALLOC_FAILED] += stats_msg->dropped_pbuf_alloc_failed;
+	s->stats[NSS_CLMAP_INTERFACE_STATS_DROPPED_LINEAR_FAILED] += stats_msg->dropped_linear_failed;
+	s->stats[NSS_CLMAP_INTERFACE_STATS_SHARED_PACKET_CNT] += stats_msg->shared_packet_count;
+	s->stats[NSS_CLMAP_INTERFACE_STATS_ETHERNET_FRAME_ERROR] += stats_msg->ethernet_frame_error;
+	s->stats[NSS_CLMAP_INTERFACE_STATS_MACDB_CREATE_REQUESTS_CNT] += stats_msg->macdb_create_requests;
+	s->stats[NSS_CLMAP_INTERFACE_STATS_MACDB_CREATE_MAC_EXISTS_CNT] += stats_msg->macdb_create_mac_exists;
+	s->stats[NSS_CLMAP_INTERFACE_STATS_MACDB_CREATE_MAC_TABLE_FULL_CNT] += stats_msg->macdb_create_table_full;
+	s->stats[NSS_CLMAP_INTERFACE_STATS_MACDB_DESTROY_REQUESTS_CNT] += stats_msg->macdb_destroy_requests;
+	s->stats[NSS_CLMAP_INTERFACE_STATS_MACDB_DESTROY_MAC_NOT_FOUND_CNT] += stats_msg->macdb_destroy_mac_notfound;
+	s->stats[NSS_CLMAP_INTERFACE_STATS_MACDB_DESTROY_MAC_UNHASHED_CNT] += stats_msg->macdb_destroy_mac_unhashed;
+	s->stats[NSS_CLMAP_INTERFACE_STATS_MACDB_FLUSH_REQUESTS_CNT] += stats_msg->macdb_flush_requests;
+	spin_unlock_bh(&nss_clmap_stats_lock);
+}
+
+/*
+ * nss_clmap_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(clmap)
+
+/*
+ * nss_clmap_stats_dentry_create()
+ *	Create client map statistics debug entry.
+ */
+void nss_clmap_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("clmap", &nss_clmap_stats_ops);
+}
+
+/*
+ * nss_clmap_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_clmap_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_clmap_stats_notification clmap_stats;
+	struct nss_clmap_stats *s = NULL;
+	int i;
+
+	spin_lock_bh(&nss_clmap_stats_lock);
+	for (i = 0; i < NSS_CLMAP_MAX_DEBUG_INTERFACES; i++) {
+		if (!stats_db[i] || (stats_db[i]->nss_if_num != if_num)) {
+			continue;
+		}
+
+		s = stats_db[i];
+		clmap_stats.core_id = nss_ctx->id;
+		clmap_stats.if_num = if_num;
+		memcpy(clmap_stats.stats_ctx, s->stats, sizeof(clmap_stats.stats_ctx));
+		spin_unlock_bh(&nss_clmap_stats_lock);
+		atomic_notifier_call_chain(&nss_clmap_stats_notifier, NSS_STATS_EVENT_NOTIFY, &clmap_stats);
+		return;
+	}
+	spin_unlock_bh(&nss_clmap_stats_lock);
+}
+
+/*
+ * nss_clmap_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_clmap_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_clmap_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_clmap_stats_unregister_notifier);
+
+/*
+ * nss_clmap_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_clmap_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_clmap_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_clmap_stats_register_notifier);
diff --git a/qca-nss-drv/nss_clmap_stats.h b/qca-nss-drv/nss_clmap_stats.h
new file mode 100644
index 0000000..89f687d
--- /dev/null
+++ b/qca-nss-drv/nss_clmap_stats.h
@@ -0,0 +1,42 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_CLMAP_STATS_H
+#define __NSS_CLMAP_STATS_H
+
+#define NSS_CLMAP_MAX_DEBUG_INTERFACES 2 * NSS_CLMAP_MAX_INTERFACES
+
+/*
+ * Clmap session debug statistics.
+ */
+struct nss_clmap_stats {
+	uint64_t stats[NSS_CLMAP_INTERFACE_STATS_MAX];	/* Clmap statistics. */
+	int32_t if_index;				/* Interface index. */
+	uint32_t nss_if_num;				/* NSS interface number. */
+	enum nss_clmap_interface_type nss_if_type;	/* NSS interface type. */
+	bool valid;
+};
+
+/*
+ * Clmap statistics APIs.
+ */
+extern void nss_clmap_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern bool nss_clmap_stats_session_register(uint32_t if_num, enum nss_clmap_interface_type if_type, struct net_device *netdev);
+extern void nss_clmap_stats_session_unregister(uint32_t if_num);
+extern void nss_clmap_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_clmap_stats_msg *stats_msg, uint32_t if_num);
+extern void nss_clmap_stats_dentry_create(void);
+
+#endif /* __NSS_CLMAP_STATS_H */
diff --git a/qca-nss-drv/nss_clmap_strings.c b/qca-nss-drv/nss_clmap_strings.c
new file mode 100644
index 0000000..4a52b48
--- /dev/null
+++ b/qca-nss-drv/nss_clmap_strings.c
@@ -0,0 +1,73 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_clmap_strings.h"
+
+/*
+ * nss_clmap_strings_stats
+ *	Clmap statistics strings for nss tunnel stats
+ */
+struct nss_stats_info nss_clmap_strings_stats[NSS_CLMAP_INTERFACE_STATS_MAX] = {
+	{"rx_pkts",					NSS_STATS_TYPE_COMMON},
+	{"rx_bytes",					NSS_STATS_TYPE_COMMON},
+	{"tx_pkts",					NSS_STATS_TYPE_COMMON},
+	{"tx_bytes",					NSS_STATS_TYPE_COMMON},
+	{"rx_queue_0_dropped",				NSS_STATS_TYPE_DROP},
+	{"rx_queue_1_dropped",				NSS_STATS_TYPE_DROP},
+	{"rx_queue_2_dropped",				NSS_STATS_TYPE_DROP},
+	{"rx_queue_3_dropped",				NSS_STATS_TYPE_DROP},
+	{"MAC DB look up failed",			NSS_STATS_TYPE_SPECIAL},
+	{"Invalid packet count",			NSS_STATS_TYPE_SPECIAL},
+	{"Headroom drop",				NSS_STATS_TYPE_SPECIAL},
+	{"Next node queue full drop",			NSS_STATS_TYPE_SPECIAL},
+	{"Pbuf alloc failed drop",			NSS_STATS_TYPE_SPECIAL},
+	{"Linear failed drop",				NSS_STATS_TYPE_SPECIAL},
+	{"Shared packet count",				NSS_STATS_TYPE_SPECIAL},
+	{"Ethernet frame error",			NSS_STATS_TYPE_SPECIAL},
+	{"Macdb create requests count",			NSS_STATS_TYPE_SPECIAL},
+	{"Macdb create failures MAC exists count",	NSS_STATS_TYPE_SPECIAL},
+	{"Macdb create failures MAC table full count",	NSS_STATS_TYPE_SPECIAL},
+	{"Macdb destroy requests count",		NSS_STATS_TYPE_SPECIAL},
+	{"Macdb destroy failures MAC not found count",	NSS_STATS_TYPE_SPECIAL},
+	{"Macdb destroy failures MAC unhashed count",	NSS_STATS_TYPE_SPECIAL},
+	{"Macdb flush requests count",			NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_clmap_strings_read()
+ *	Read clmap statistics names
+ */
+static ssize_t nss_clmap_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_clmap_strings_stats, NSS_CLMAP_INTERFACE_STATS_MAX);
+}
+
+/*
+ * nss_clmap_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(clmap);
+
+/*
+ * nss_clmap_strings_dentry_create()
+ *	Create clmap statistics strings debug entry.
+ */
+void nss_clmap_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("clmap", &nss_clmap_strings_ops);
+}
diff --git a/qca-nss-drv/nss_clmap_strings.h b/qca-nss-drv/nss_clmap_strings.h
new file mode 100644
index 0000000..dbdffba
--- /dev/null
+++ b/qca-nss-drv/nss_clmap_strings.h
@@ -0,0 +1,25 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#ifndef __NSS_CLMAP_STRINGS_H
+#define __NSS_CLMAP_STRINGS_H
+
+#include "nss_clmap_stats.h"
+
+extern struct nss_stats_info nss_clmap_strings_stats[NSS_CLMAP_INTERFACE_STATS_MAX];
+extern void nss_clmap_strings_dentry_create(void);
+
+#endif /* __NSS_CLMAP_STRINGS_H */
diff --git a/qca-nss-drv/nss_cmn.c b/qca-nss-drv/nss_cmn.c
new file mode 100644
index 0000000..258994f
--- /dev/null
+++ b/qca-nss-drv/nss_cmn.c
@@ -0,0 +1,345 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_cmn.c
+ *	NSS generic APIs
+ */
+
+#if (NSS_DT_SUPPORT == 1)
+#include <linux/of.h>
+#endif
+
+#include "nss_tx_rx_common.h"
+
+/*
+ * nss_cmn_response_str
+ *	Common response structure string
+ */
+int8_t *nss_cmn_response_str[NSS_CMN_RESPONSE_LAST] = {
+	"Message Acknowledge without errors",
+	"Common message version not supported",
+	"Unknown Interface",
+	"Length Error",
+	"Message Error",
+	"FW Notification Message",
+};
+
+/*
+ * nss_cmn_msg_init()
+ *	Initialize the common message of an ASYNC message.
+ */
+void nss_cmn_msg_init(struct nss_cmn_msg *ncm, uint32_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data)
+{
+	ncm->interface = if_num;
+	ncm->version = NSS_HLOS_MESSAGE_VERSION;
+	ncm->type = type;
+	ncm->len = len;
+	ncm->cb = (nss_ptr_t)cb;
+	ncm->app_data = (nss_ptr_t)app_data;
+}
+EXPORT_SYMBOL(nss_cmn_msg_init);
+
+/*
+ * nss_cmn_msg_sync_init()
+ *	Initialize the common message of a SYNC message.
+ */
+void nss_cmn_msg_sync_init(struct nss_cmn_msg *ncm, uint32_t if_num, uint32_t type, uint32_t len)
+{
+	nss_cmn_msg_init(ncm, if_num, type, len, NULL, NULL);
+}
+EXPORT_SYMBOL(nss_cmn_msg_sync_init);
+
+/*
+ * nss_cmn_get_interface_number()
+ *	Return the interface number of the NSS net_device.
+ *
+ * Returns -1 on failure or the interface number of dev is an NSS net_device.
+ */
+int32_t nss_cmn_get_interface_number(struct nss_ctx_instance *nss_ctx, struct net_device *dev)
+{
+	int i;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	if (unlikely(nss_ctx->state != NSS_CORE_STATE_INITIALIZED)) {
+		nss_warning("%px: Interface number could not be found as core not ready\n", nss_ctx);
+		return -1;
+	}
+
+	nss_assert(dev != 0);
+
+	/*
+	 * Check physical interface table
+	 */
+	for (i = 0; i < NSS_MAX_NET_INTERFACES; i++) {
+		if (dev == nss_ctx->subsys_dp_register[i].ndev) {
+			return i;
+		}
+	}
+
+	nss_warning("%px: Interface number could not be found as interface has not registered yet\n", nss_ctx);
+	return -1;
+}
+EXPORT_SYMBOL(nss_cmn_get_interface_number);
+
+/*
+ * nss_cmn_append_core_id()
+ *	Return the NSS interface number with core ID.
+ */
+int nss_cmn_append_core_id(struct nss_ctx_instance *nss_ctx, int if_num)
+{
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	return NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_cmn_append_core_id);
+
+/*
+ * nss_cmn_get_interface_dev()
+ *	Return the net_device for NSS interface id.
+ *
+ * Returns NULL on failure or the net_device for NSS interface id.
+ */
+struct net_device *nss_cmn_get_interface_dev(struct nss_ctx_instance *ctx, uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)ctx;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	if (unlikely(nss_ctx->state != NSS_CORE_STATE_INITIALIZED)) {
+		nss_warning("%px: Interface device could not be found as core not ready\n", nss_ctx);
+		return NULL;
+	}
+
+	if (unlikely(if_num >= NSS_MAX_NET_INTERFACES)) {
+		return NULL;
+	}
+
+	return nss_ctx->subsys_dp_register[if_num].ndev;
+}
+EXPORT_SYMBOL(nss_cmn_get_interface_dev);
+
+/*
+ * nss_cmn_get_interface_number_by_dev_and_type()
+ *	Return the NSS interface id for the net_device.
+ *
+ * Returns < 0 on failure or the NSS interface id for the given device and type.
+ */
+int32_t nss_cmn_get_interface_number_by_dev_and_type(struct net_device *dev, uint32_t type)
+{
+	int i, core;
+	struct nss_subsystem_dataplane_register *nsdr;
+
+	nss_assert(dev != 0);
+	for (core = 0; core < nss_top_main.num_nss; core++) {
+		for (i = 0; i < NSS_MAX_NET_INTERFACES; i++) {
+			nsdr = &nss_top_main.nss[core].subsys_dp_register[i];
+			if (dev == nsdr->ndev && type == nsdr->type) {
+				return i;
+			}
+		}
+	}
+
+	nss_warning("Interface number could not be found for %px (%s) as interface has not registered yet\n", dev, dev->name);
+	return -1;
+}
+EXPORT_SYMBOL(nss_cmn_get_interface_number_by_dev_and_type);
+
+/*
+ * nss_cmn_get_interface_number_by_dev()
+ *	Return the NSS interface id for the net_device.
+ *
+ * Returns < 0 on failure or the NSS interface id for the given device.
+ */
+int32_t nss_cmn_get_interface_number_by_dev(struct net_device *dev)
+{
+	return nss_cmn_get_interface_number_by_dev_and_type(dev, 0);
+}
+EXPORT_SYMBOL(nss_cmn_get_interface_number_by_dev);
+
+/*
+ * nss_cmn_get_state()
+ *	return the NSS initialization state
+ */
+nss_state_t nss_cmn_get_state(struct nss_ctx_instance *ctx)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)ctx;
+	nss_state_t state = NSS_STATE_UNINITIALIZED;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	spin_lock_bh(&nss_top_main.lock);
+	if (nss_ctx->state == NSS_CORE_STATE_INITIALIZED) {
+		state = NSS_STATE_INITIALIZED;
+	}
+	spin_unlock_bh(&nss_top_main.lock);
+
+	return state;
+}
+EXPORT_SYMBOL(nss_cmn_get_state);
+
+/*
+ * nss_cmn_interface_is_redirect()
+ * 	Return true if the interface is a redirect interface.
+ */
+bool nss_cmn_interface_is_redirect(struct nss_ctx_instance *nss_ctx, int32_t interface_num)
+{
+	enum nss_dynamic_interface_type type = nss_dynamic_interface_get_type(nss_ctx, interface_num);
+
+	return type == NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_N2H
+		|| type == NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_H2N
+		|| type == NSS_DYNAMIC_INTERFACE_TYPE_VIRTIF_DEPRECATED;
+}
+EXPORT_SYMBOL(nss_cmn_interface_is_redirect);
+
+/*
+ * nss_cmn_rx_dropped_sum()
+ *	Sum rx_dropped count.
+ */
+uint32_t nss_cmn_rx_dropped_sum(struct nss_cmn_node_stats *node_stats)
+{
+	uint32_t sum = 0;
+	int i;
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		sum += node_stats->rx_dropped[i];
+	}
+	return sum;
+}
+EXPORT_SYMBOL(nss_cmn_rx_dropped_sum);
+
+/*
+ * nss_cmn_register_queue_decongestion()
+ *	Register for queue decongestion event
+ */
+nss_cb_register_status_t nss_cmn_register_queue_decongestion(struct nss_ctx_instance *nss_ctx, nss_cmn_queue_decongestion_callback_t event_callback, void *app_ctx)
+{
+	uint32_t i;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	spin_lock_bh(&nss_ctx->decongest_cb_lock);
+
+	/*
+	 * Find vacant location in callback table
+	 */
+	for (i = 0; i< NSS_MAX_CLIENTS; i++) {
+		if (nss_ctx->queue_decongestion_callback[i] == NULL) {
+			nss_ctx->queue_decongestion_callback[i] = event_callback;
+			nss_ctx->queue_decongestion_ctx[i] = app_ctx;
+			spin_unlock_bh(&nss_ctx->decongest_cb_lock);
+			return NSS_CB_REGISTER_SUCCESS;
+		}
+	}
+
+	spin_unlock_bh(&nss_ctx->decongest_cb_lock);
+	return NSS_CB_REGISTER_FAILED;
+}
+EXPORT_SYMBOL(nss_cmn_register_queue_decongestion);
+
+/*
+ * nss_cmn_unregister_queue_decongestion()
+ *	Unregister for queue decongestion event
+ */
+nss_cb_unregister_status_t nss_cmn_unregister_queue_decongestion(struct nss_ctx_instance *nss_ctx, nss_cmn_queue_decongestion_callback_t event_callback)
+{
+	uint32_t i;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	spin_lock_bh(&nss_ctx->decongest_cb_lock);
+
+	/*
+	 * Find actual location in callback table
+	 */
+	for (i = 0; i< NSS_MAX_CLIENTS; i++) {
+		if (nss_ctx->queue_decongestion_callback[i] == event_callback) {
+			nss_ctx->queue_decongestion_callback[i] = NULL;
+			nss_ctx->queue_decongestion_ctx[i] = NULL;
+			spin_unlock_bh(&nss_ctx->decongest_cb_lock);
+			return NSS_CB_UNREGISTER_SUCCESS;
+		}
+	}
+
+	spin_unlock_bh(&nss_ctx->decongest_cb_lock);
+	return NSS_CB_UNREGISTER_FAILED;
+}
+EXPORT_SYMBOL(nss_cmn_unregister_queue_decongestion);
+
+/*
+ * nss_cmn_register_service_code()
+ *	Register for service code event
+ */
+nss_cb_register_status_t nss_cmn_register_service_code(struct nss_ctx_instance *nss_ctx, nss_cmn_service_code_callback_t cb, uint8_t service_code, void *app_data)
+{
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (nss_ctx->service_code_callback[service_code]) {
+		/*
+		 * We already have a callback registered for this service code.
+		 */
+		nss_warning("%px: a callback is registered already for this service code %d\n", nss_ctx, service_code);
+
+		return NSS_CB_REGISTER_FAILED;
+	}
+
+	nss_ctx->service_code_callback[service_code] = cb;
+	nss_ctx->service_code_ctx[service_code] = app_data;
+	return NSS_CB_REGISTER_SUCCESS;
+}
+EXPORT_SYMBOL(nss_cmn_register_service_code);
+
+/*
+ * nss_cmn_unregister_service_code()
+ *	Unregister for service code event
+ */
+nss_cb_unregister_status_t nss_cmn_unregister_service_code(struct nss_ctx_instance *nss_ctx, nss_cmn_service_code_callback_t cb, uint8_t service_code)
+{
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_ctx->service_code_callback[service_code]) {
+		/*
+		 * No callback was registered for this service code.
+		 */
+		nss_warning("%px: no callback is registered for this service code %d\n", nss_ctx, service_code);
+		return NSS_CB_UNREGISTER_FAILED;
+	}
+
+	nss_ctx->service_code_callback[service_code] = NULL;
+	nss_ctx->service_code_ctx[service_code] = NULL;
+	return NSS_CB_UNREGISTER_SUCCESS;
+}
+EXPORT_SYMBOL(nss_cmn_unregister_service_code);
+
+/*
+ * nss_cmn_get_nss_enabled()
+ * 	Check if NSS mode is supported on platform
+ *
+ * This API checks the device tree parameter to decide on whether
+ * NSS mode is enabled. On older kernels this will always return true
+ */
+bool nss_cmn_get_nss_enabled(void)
+{
+#if (NSS_DT_SUPPORT == 1)
+	struct device_node *cmn = NULL;
+
+	/*
+	 * Get reference to NSS common device node
+	 */
+	cmn = of_find_node_by_name(NULL, "nss-common");
+	if (!cmn) {
+		nss_info_always("nss is not enabled on this platform\n");
+		return false;
+	}
+#endif
+	return true;
+}
+EXPORT_SYMBOL(nss_cmn_get_nss_enabled);
diff --git a/qca-nss-drv/nss_core.c b/qca-nss-drv/nss_core.c
new file mode 100644
index 0000000..eaea9ec
--- /dev/null
+++ b/qca-nss-drv/nss_core.c
@@ -0,0 +1,3251 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_core.c
+ *	NSS driver core APIs source file.
+ */
+
+#include "nss_core.h"
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/of.h>
+#include <nss_hal.h>
+#include <net/dst.h>
+#ifdef CONFIG_BRIDGE_NETFILTER
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 0, 0))
+#include <net/netfilter/br_netfilter.h>
+#else
+#include <linux/netfilter_bridge.h>
+#endif
+#endif
+#include <linux/etherdevice.h>
+#include "nss_tx_rx_common.h"
+#include "nss_data_plane.h"
+
+#define NSS_CORE_JUMBO_LINEAR_BUF_SIZE 128
+
+#if (NSS_SKB_REUSE_SUPPORT == 1)
+/*
+ * We have validated the skb recycling code within the NSS for the
+ * following kernel versions. Before enabling the driver in new kernels,
+ * the skb recycle code must be checked against Linux skb handling.
+ *
+ * Tested on: 3.4, 3.10, 3.14, 3.18, 4.4 and 5.4
+ */
+#if (!( \
+(((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)))) || \
+(((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)))) || \
+(((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)))) || \
+(((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \
+(((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \
+(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0))))))
+#error "Check skb recycle code in this file to match Linux version"
+#endif
+
+static atomic_t max_reuse = ATOMIC_INIT(PAGE_SIZE);
+
+#endif /* NSS_SKB_REUSE_SUPPORT */
+
+static int max_ipv4_conn = NSS_DEFAULT_NUM_CONN;
+module_param(max_ipv4_conn, int, S_IRUGO);
+MODULE_PARM_DESC(max_ipv4_conn, "Max number of IPv4 connections");
+
+static int max_ipv6_conn = NSS_DEFAULT_NUM_CONN;
+module_param(max_ipv6_conn, int, S_IRUGO);
+MODULE_PARM_DESC(max_ipv6_conn, "Max number of IPv6 connections");
+
+bool pn_mq_en = false;
+module_param(pn_mq_en, bool, S_IRUGO);
+MODULE_PARM_DESC(pn_mq_en, "Enable pnode ingress QoS");
+
+uint16_t pn_qlimits[NSS_MAX_NUM_PRI] = {[0 ... NSS_MAX_NUM_PRI - 1] = NSS_DEFAULT_QUEUE_LIMIT};
+module_param_array(pn_qlimits, short, NULL, 0);
+MODULE_PARM_DESC(pn_qlimits, "Queue limit per queue");
+
+/*
+ * Atomic variables to control jumbo_mru & paged_mode
+ */
+static atomic_t jumbo_mru;
+static atomic_t paged_mode;
+
+/*
+ * nss_core_update_max_ipv4_conn()
+ *	Update the maximum number of configured IPv4 connections
+ */
+void nss_core_update_max_ipv4_conn(int conn)
+{
+	max_ipv4_conn = conn;
+}
+
+/*
+ * nss_core_update_max_ipv6_conn()
+ *	Update the maximum number of configured IPv6 connections
+ */
+void nss_core_update_max_ipv6_conn(int conn)
+{
+	max_ipv6_conn = conn;
+}
+
+#if (NSS_SKB_REUSE_SUPPORT == 1)
+/*
+ * nss_core_set_max_reuse()
+ *	Set the max_reuse to the specified value
+ */
+void nss_core_set_max_reuse(int max)
+{
+	atomic_set(&max_reuse, max);
+}
+
+/*
+ * nss_core_get_max_reuse()
+ *	Does an atomic read of max_reuse
+ */
+int nss_core_get_max_reuse(void)
+{
+	return atomic_read(&max_reuse);
+}
+
+/*
+ * nss_core_get_min_reuse()
+ *	Return min reuse size
+ */
+uint32_t nss_core_get_min_reuse(struct nss_ctx_instance *nss_ctx)
+{
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	return nss_ctx->max_buf_size;
+}
+#endif /* NSS_SKB_REUSE_SUPPORT */
+
+/*
+ * nss_core_set_jumbo_mru()
+ *	Set the jumbo_mru to the specified value
+ */
+void nss_core_set_jumbo_mru(int jumbo)
+{
+	atomic_set(&jumbo_mru, jumbo);
+
+#if (NSS_SKB_REUSE_SUPPORT == 1)
+	if (jumbo > nss_core_get_max_reuse())
+		nss_core_set_max_reuse(ALIGN(jumbo * 2, PAGE_SIZE));
+#endif
+}
+
+/*
+ * nss_core_get_jumbo_mru()
+ *	Does an atomic read of jumbo_mru
+ */
+int nss_core_get_jumbo_mru(void)
+{
+	return atomic_read(&jumbo_mru);
+}
+
+/*
+ * nss_core_set_paged_mode()
+ *	Set the paged_mode to the specified value
+ */
+void nss_core_set_paged_mode(int mode)
+{
+	atomic_set(&paged_mode, mode);
+}
+
+/*
+ * nss_core_get_paged_mode()
+ *	Does an atomic read of paged_mode
+ */
+int nss_core_get_paged_mode(void)
+{
+	return atomic_read(&paged_mode);
+}
+
+/*
+ * nss_core_register_msg_handler()
+ *	Register a msg callback per interface number. One per interface.
+ */
+uint32_t nss_core_register_msg_handler(struct nss_ctx_instance *nss_ctx, uint32_t interface, nss_if_rx_msg_callback_t msg_cb)
+{
+	nss_assert(msg_cb != NULL);
+
+	/*
+	 * Validate interface id
+	 */
+	if (interface >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("Error - Interface %d not Supported\n", interface);
+		return NSS_CORE_STATUS_FAILURE;
+	}
+
+	/*
+	 * Check if already registered
+	 */
+	if (nss_ctx->nss_rx_interface_handlers[interface].msg_cb) {
+		nss_warning("Error - Duplicate Interface CB Registered for interface %d\n", interface);
+		return NSS_CORE_STATUS_FAILURE;
+	}
+
+	nss_ctx->nss_rx_interface_handlers[interface].msg_cb = msg_cb;
+
+	return NSS_CORE_STATUS_SUCCESS;
+}
+
+/*
+ * nss_core_unregister_msg_handler()
+ *	Unregister a msg callback per interface number.
+ */
+uint32_t nss_core_unregister_msg_handler(struct nss_ctx_instance *nss_ctx, uint32_t interface)
+{
+	/*
+	 * Validate interface id
+	 */
+	if (interface >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("Error - Interface %d not Supported\n", interface);
+		return NSS_CORE_STATUS_FAILURE;
+	}
+
+	nss_ctx->nss_rx_interface_handlers[interface].msg_cb = NULL;
+
+	return NSS_CORE_STATUS_SUCCESS;
+}
+
+/*
+ * nss_core_register_handler()
+
+--	Register a callback per interface code. Only one per interface.
+ */
+uint32_t nss_core_register_handler(struct nss_ctx_instance *nss_ctx, uint32_t interface, nss_core_rx_callback_t cb, void *app_data)
+{
+	nss_assert(cb != NULL);
+
+	/*
+	 * Validate interface id
+	 */
+	if (interface >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("Error - Interface %d not Supported\n", interface);
+		return NSS_CORE_STATUS_FAILURE;
+	}
+
+	/*
+	 * Check if already registered
+	 */
+	if (nss_ctx->nss_rx_interface_handlers[interface].cb != NULL) {
+		nss_warning("Error - Duplicate Interface CB Registered for interface %d\n", interface);
+		return NSS_CORE_STATUS_FAILURE;
+	}
+
+	nss_ctx->nss_rx_interface_handlers[interface].cb = cb;
+	nss_ctx->nss_rx_interface_handlers[interface].app_data = app_data;
+
+	return NSS_CORE_STATUS_SUCCESS;
+}
+
+/*
+ * nss_core_unregister_handler()
+ *	Unegister a callback per interface code.
+ */
+uint32_t nss_core_unregister_handler(struct nss_ctx_instance *nss_ctx, uint32_t interface)
+{
+	/*
+	 * Validate interface id
+	 */
+	if (interface >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("Error - Interface %d not Supported\n", interface);
+		return NSS_CORE_STATUS_FAILURE;
+	}
+
+	nss_ctx->nss_rx_interface_handlers[interface].cb = NULL;
+	nss_ctx->nss_rx_interface_handlers[interface].app_data = NULL;
+
+	return NSS_CORE_STATUS_SUCCESS;
+}
+
+/*
+ * nss_core_set_subsys_dp_type()
+ *	Set the type for the datapath subsystem
+ */
+void nss_core_set_subsys_dp_type(struct nss_ctx_instance *nss_ctx, struct net_device *ndev, uint32_t if_num, uint32_t type)
+{
+	struct nss_subsystem_dataplane_register *reg;
+
+	/*
+	 * Check that interface number is in range.
+	 */
+	BUG_ON(if_num >= NSS_MAX_NET_INTERFACES);
+
+	reg = &nss_ctx->subsys_dp_register[if_num];
+
+	/*
+	 * Check if there is already a subsystem registered at this interface number.
+	 */
+	BUG_ON(reg->ndev && reg->ndev != ndev);
+
+	reg->type = type;
+}
+
+/*
+ * nss_core_register_subsys_dp()
+ *	Registers a netdevice and associated information at a given interface.
+ *
+ * Can also be used to update an existing registry if the provided net_device
+ * is equal to the one already registered. Will fail if there is already
+ * a net_device registered to the interface not equal to the one provided,
+ * or if the interface number is out of range.
+ */
+void nss_core_register_subsys_dp(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+					nss_phys_if_rx_callback_t cb,
+					nss_phys_if_rx_ext_data_callback_t ext_cb,
+					void *app_data, struct net_device *ndev,
+					uint32_t features)
+{
+	struct nss_subsystem_dataplane_register *reg;
+
+	/*
+	 * Check that interface number is in range.
+	 */
+	BUG_ON(if_num >= NSS_MAX_NET_INTERFACES);
+
+	reg = &nss_ctx->subsys_dp_register[if_num];
+
+	/*
+	 * Check if there is already a subsystem registered at this interface number.
+	 */
+	BUG_ON(reg->ndev && reg->ndev != ndev);
+
+	reg->cb = cb;
+	reg->ext_cb = ext_cb;
+	reg->app_data = app_data;
+	reg->ndev = ndev;
+	reg->features = features;
+}
+
+/*
+ * nss_core_unregister_subsys_dp()
+ *	Unregisters the netdevice at the given interface.
+ *
+ * Fails if the interface number is not valid.
+ */
+void nss_core_unregister_subsys_dp(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_subsystem_dataplane_register *reg;
+
+	/*
+	 * Check that interface number is in range.
+	 */
+	BUG_ON(if_num >= NSS_MAX_NET_INTERFACES);
+
+	reg = &nss_ctx->subsys_dp_register[if_num];
+
+	reg->cb = NULL;
+	reg->ext_cb = NULL;
+	reg->app_data = NULL;
+	reg->ndev = NULL;
+	reg->features = 0;
+	reg->type = 0;
+}
+
+/*
+ * nss_core_handle_nss_status_pkt()
+ *	Handle the metadata/status packet.
+ */
+void nss_core_handle_nss_status_pkt(struct nss_ctx_instance *nss_ctx, struct sk_buff *nbuf)
+{
+	struct nss_cmn_msg *ncm;
+	uint32_t expected_version = NSS_HLOS_MESSAGE_VERSION;
+	nss_core_rx_callback_t cb;
+	void *app_data;
+	uint16_t nss_if;
+
+	if (skb_shinfo(nbuf)->nr_frags > 0) {
+		ncm = (struct nss_cmn_msg *)skb_frag_address(&skb_shinfo(nbuf)->frags[0]);
+	} else {
+		ncm = (struct nss_cmn_msg *)nbuf->data;
+	}
+
+	/*
+	 * Save NSS interface number in local variable
+	 */
+	nss_if = ncm->interface;
+
+	/*
+	 * Check for version number
+	 */
+	if (ncm->version != expected_version) {
+		nss_warning("%px: Message %d for interface %d received with invalid version %d, expected version %d",
+							nss_ctx, ncm->type, nss_if, ncm->version, expected_version);
+		return;
+	}
+
+	/*
+	 * Validate message size
+	 */
+	if (ncm->len > nbuf->len) {
+		nss_warning("%px: Message %d for interface %d received with invalid length %d, expected length %d",
+							nss_ctx, ncm->type, nss_if, nbuf->len, ncm->len);
+		return;
+	}
+
+	/*
+	 * Check for validity of interface number
+	 */
+	if (nss_if >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("%px: Message %d received with invalid interface number %d", nss_ctx, ncm->type, nss_if);
+		return;
+	}
+
+	cb = nss_ctx->nss_rx_interface_handlers[nss_if].cb;
+	app_data = nss_ctx->nss_rx_interface_handlers[nss_if].app_data;
+
+	if (!cb) {
+		nss_warning("%px: Callback not registered for interface %d", nss_ctx, nss_if);
+		return;
+	}
+
+	cb(nss_ctx, ncm, app_data);
+
+	if (ncm->interface != nss_if) {
+		nss_warning("%px: Invalid NSS I/F %d expected %d", nss_ctx, ncm->interface, nss_if);
+	}
+
+	return;
+}
+
+/*
+ * nss_core_handle_nss_crypto_pkt()
+ *	Handles crypto packet.
+ */
+static void nss_core_handle_crypto_pkt(struct nss_ctx_instance *nss_ctx, unsigned int interface_num,
+			struct sk_buff *nbuf, struct napi_struct *napi)
+{
+	struct nss_subsystem_dataplane_register *subsys_dp_reg = &nss_ctx->subsys_dp_register[interface_num];
+	nss_phys_if_rx_callback_t cb;
+	struct net_device *ndev;
+
+	ndev = subsys_dp_reg->ndev;
+	cb = subsys_dp_reg->cb;
+	if (likely(cb)) {
+		cb(ndev, nbuf, napi);
+		return;
+	}
+
+	dev_kfree_skb_any(nbuf);
+	return;
+}
+
+/*
+ * nss_soc_mem_info()
+ *	Getting DDR information for NSS SoC
+ */
+static uint32_t nss_soc_mem_info(void)
+{
+	struct device_node *node;
+	struct device_node *snode;
+	int addr_cells;
+	int size_cells;
+	int n_items;
+	uint32_t nss_msize = 8 << 20;	/* default: 8MB */
+	const __be32 *ppp;
+
+	node = of_find_node_by_name(NULL, "reserved-memory");
+	if (!node) {
+		nss_info_always("reserved-memory not found\n");
+		return nss_msize;
+	}
+
+	ppp = (__be32 *)of_get_property(node, "#address-cells", NULL);
+	addr_cells = ppp ? be32_to_cpup(ppp) : 2;
+	nss_info("%px addr cells %d\n", ppp, addr_cells);
+	ppp = (__be32 *)of_get_property(node, "#size-cells", NULL);
+	size_cells = ppp ? be32_to_cpup(ppp) : 2;
+	nss_info("%px size cells %d\n", ppp, size_cells);
+
+	for_each_child_of_node(node, snode) {
+		/*
+		 * compare (snode->full_name, "/reserved-memory/nss@40000000") may be safer
+		 */
+		nss_info("%px snode %s fn %s\n", snode, snode->name, snode->full_name);
+		if (strcmp(snode->name, "nss") == 0)
+			break;
+	}
+	of_node_put(node);
+	if (!snode) {
+		nss_info_always("nss@node not found: needed to determine NSS reserved DDR\n");
+		return nss_msize;
+	}
+
+	ppp = (__be32 *)of_get_property(snode, "reg", &n_items);
+	if (ppp) {
+		n_items /= sizeof(ppp[0]);
+		nss_msize = be32_to_cpup(ppp + addr_cells + size_cells - 1);
+		nss_info_always("addr/size storage words %d %d # words %d in DTS, ddr size %x\n",
+				addr_cells, size_cells, n_items, nss_msize);
+	}
+	of_node_put(snode);
+	return nss_msize;
+}
+
+/*
+ * nss_get_ddr_info()
+ *	get DDR start address and size from device tree.
+ */
+static void nss_get_ddr_info(struct nss_mmu_ddr_info *mmu, char *name)
+{
+	__be32 avail_ddr;
+	long cached;
+	struct sysinfo vals;
+	struct device_node *node;
+
+	si_meminfo(&vals);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+	cached = global_page_state(NR_FILE_PAGES);
+#else
+	cached = global_node_page_state(NR_FILE_PAGES);
+#endif
+
+	avail_ddr = (vals.totalram + cached + vals.sharedram) * vals.mem_unit;
+	mmu->num_active_cores = nss_top_main.num_nss;
+
+	/*
+	 * Since "memory" has not been used by anyone, the format is not final.
+	 * Three (3) possible formats available: one of 1 or 2 will be final.
+	 * 1)	item_size	stating_address	DDR_size	: odd # items
+	 * 2)	stating_address DDR_size	# 32-bit each; total 2 words
+	 * 3)	stating_address DDR_size	# 64-bit each; total 4 words
+	 */
+	node = of_find_node_by_name(NULL, name);
+	if (node) {
+		int isize = 0;
+		int n_items;
+		const __be32 *ppp = (__be32 *)of_get_property(node, "reg", &n_items);
+
+		n_items /= sizeof(ppp[0]);
+		nss_info_always("node size %d # items %d\n",
+				of_n_size_cells(node), n_items);
+		if (ppp) {
+			if (n_items & 1) {	/* case 1 */
+				isize = be32_to_cpup(ppp);
+				if (isize == 1)
+					goto case2;
+				if (isize == 2)
+					goto case3;
+				n_items = 0;
+			} else if (n_items == 2) {
+case2:
+				mmu->start_address = be32_to_cpup(ppp + isize);
+				mmu->ddr_size = be32_to_cpup(&ppp[isize + 1]);
+			} else if (n_items == 4) {
+case3:
+				if (!ppp[isize] && !ppp[isize * 2]) {
+					if (isize)
+						isize = 1;
+					mmu->start_address = be32_to_cpup(ppp + isize + 1);
+					mmu->ddr_size = be32_to_cpup(ppp + isize + 3);
+				} else
+					n_items = 0;
+			} else
+				n_items = 0;
+			if (n_items) {
+				of_node_put(node);
+				nss_info_always("%s: %x %u (avl %u) items %d active_cores %d\n",
+					name, mmu->start_address, mmu->ddr_size,
+					avail_ddr, n_items, mmu->num_active_cores);
+				/*
+				 * if DTS mechanism goes wrong, use available
+				 * DDR and round it up to 64MB for maximum DDR.
+				 */
+				if (avail_ddr > mmu->ddr_size)
+					mmu->ddr_size = (avail_ddr + (63 << 20))
+							& (~63 << 20);
+				return;
+			}
+		}
+		of_node_put(node);
+		nss_info_always("incorrect memory info %px items %d\n",
+			ppp, n_items);
+	}
+
+	/*
+	 * boilerplate for setting customer values;
+	 * start_address = 0 will not change default start address
+	 * set in NSS FW (likely 0x4000_0000)
+	 * total available RAM + 16 MB NSS FW DDR + ~31 MB kernel mem
+	 * we round it up by 128MB to cover potential NSS DDR increase
+	 * and a slightly large holes.
+	 * The size can be changed to a fixed value as DTS, but simplier.
+	 * mmu->ddr_size = 1024 << 20
+	 */
+	mmu->start_address = 0;
+	mmu->ddr_size = (avail_ddr + (127 << 20)) & (~127 << 20);
+	nss_info_always("RAM pages fr %lu buf %lu cached %lu %lu : %lu %u\n",
+			vals.freeram, vals.bufferram, cached, vals.sharedram,
+			vals.totalram, mmu->ddr_size);
+}
+
+/*
+ * nss_send_ddr_info()
+ *	Send DDR info to NSS
+ */
+static void nss_send_ddr_info(struct nss_ctx_instance *nss_own)
+{
+	struct nss_n2h_msg nnm;
+	struct nss_cmn_msg *ncm = &nnm.cm;
+	uint32_t ret;
+	nss_info("%px: send DDR info\n", nss_own);
+
+	nss_cmn_msg_init(ncm, NSS_N2H_INTERFACE, NSS_TX_DDR_INFO_VIA_N2H_CFG,
+			sizeof(struct nss_mmu_ddr_info), NULL, NULL);
+
+	nss_get_ddr_info(&nnm.msg.mmu, "memory");
+	nnm.msg.mmu.nss_ddr_size = nss_soc_mem_info();
+
+	ret = nss_core_send_cmd(nss_own, &nnm, sizeof(nnm), NSS_NBUF_PAYLOAD_SIZE);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_info_always("%px: Failed to send DDR info for core %d\n", nss_own, nss_own->id);
+	}
+}
+
+/*
+ * nss_core_cause_to_queue()
+ *	Map interrupt cause to queue id
+ */
+static inline uint16_t nss_core_cause_to_queue(uint16_t cause)
+{
+	if (likely(cause == NSS_N2H_INTR_DATA_QUEUE_0)) {
+		return NSS_IF_N2H_DATA_QUEUE_0;
+	}
+
+	if (likely(cause == NSS_N2H_INTR_DATA_QUEUE_1)) {
+		return NSS_IF_N2H_DATA_QUEUE_1;
+	}
+
+	if (likely(cause == NSS_N2H_INTR_DATA_QUEUE_2)) {
+		return NSS_IF_N2H_DATA_QUEUE_2;
+	}
+
+	if (likely(cause == NSS_N2H_INTR_DATA_QUEUE_3)) {
+		return NSS_IF_N2H_DATA_QUEUE_3;
+	}
+
+	if (likely(cause == NSS_N2H_INTR_EMPTY_BUFFER_QUEUE)) {
+		return NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE;
+	}
+
+	/*
+	 * There is no way we can reach here as cause was already identified to be related to valid queue
+	 */
+	nss_assert(0);
+	return 0;
+}
+
+/*
+ * nss_dump_desc()
+ *	Prints descriptor data
+ */
+static inline void nss_dump_desc(struct nss_ctx_instance *nss_ctx, struct n2h_descriptor *desc)
+{
+	printk("bad descriptor dump for nss core = %d\n", nss_ctx->id);
+	printk("\topaque = %px\n", (void *)desc->opaque);
+	printk("\tinterface = %d\n", desc->interface_num);
+	printk("\tbuffer_type = %d\n", desc->buffer_type);
+	printk("\tbit_flags = %x\n", desc->bit_flags);
+	printk("\tbuffer_addr = %x\n", desc->buffer);
+	printk("\tbuffer_len = %d\n", desc->buffer_len);
+	printk("\tpayload_offs = %d\n", desc->payload_offs);
+	printk("\tpayload_len = %d\n", desc->payload_len);
+	printk("\tpri = %d\n", desc->pri);
+}
+
+/*
+ * nss_core_skb_needs_linearize()
+ *	Looks at if this skb needs to be linearized or not.
+ */
+static inline int nss_core_skb_needs_linearize(struct sk_buff *skb, uint32_t features)
+{
+	return ((skb_has_frag_list(skb) &&
+				!(features & NETIF_F_FRAGLIST)) ||
+			(skb_shinfo(skb)->nr_frags &&
+				!(features & NETIF_F_SG)));
+}
+
+/*
+ * nss_core_handle_bounced_pkt()
+ *	Bounced packet is returned from an interface/bridge bounce operation.
+ *
+ * Return the skb to the registrant.
+ */
+static inline void nss_core_handle_bounced_pkt(struct nss_ctx_instance *nss_ctx,
+						struct nss_shaper_bounce_registrant *reg,
+						struct sk_buff *nbuf)
+{
+	void *app_data;
+	struct module *owner;
+	nss_shaper_bounced_callback_t bounced_callback;
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	spin_lock_bh(&nss_top->lock);
+
+	/*
+	 * Do we have a registrant?
+	 */
+	if (!reg->registered) {
+		spin_unlock_bh(&nss_top->lock);
+		dev_kfree_skb_any(nbuf);
+		return;
+	}
+
+	/*
+	 * Get handle to the owning registrant
+	 */
+	bounced_callback = reg->bounced_callback;
+	app_data = reg->app_data;
+	owner = reg->owner;
+
+	/*
+	 * Callback is active, unregistration is not permitted while this is in progress
+	 */
+	reg->callback_active = true;
+	spin_unlock_bh(&nss_top->lock);
+	if (!try_module_get(owner)) {
+		spin_lock_bh(&nss_top->lock);
+		reg->callback_active = false;
+		spin_unlock_bh(&nss_top->lock);
+		dev_kfree_skb_any(nbuf);
+		return;
+	}
+
+	/*
+	 * Pass bounced packet back to registrant
+	 */
+	bounced_callback(app_data, nbuf);
+	spin_lock_bh(&nss_top->lock);
+	reg->callback_active = false;
+	spin_unlock_bh(&nss_top->lock);
+	module_put(owner);
+}
+
+/*
+ * nss_core_handle_virt_if_pkt()
+ *	Handle packet destined to virtual interface.
+ */
+static inline void nss_core_handle_virt_if_pkt(struct nss_ctx_instance *nss_ctx,
+						unsigned int interface_num,
+						struct sk_buff *nbuf)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	struct nss_subsystem_dataplane_register *subsys_dp_reg = &nss_ctx->subsys_dp_register[interface_num];
+	struct net_device *ndev = NULL;
+
+	uint32_t xmit_ret;
+	uint16_t queue_offset = 0;
+
+	NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_RX_VIRTUAL]);
+
+	/*
+	 * Checksum is already done by NSS for packets forwarded to virtual interfaces
+	 */
+	nbuf->ip_summed = CHECKSUM_NONE;
+
+	/*
+	 * Obtain net_device pointer
+	 */
+	ndev = subsys_dp_reg->ndev;
+	if (unlikely(!ndev)) {
+		nss_warning("%px: Received packet for unregistered virtual interface %d",
+			nss_ctx, interface_num);
+
+		/*
+		 * NOTE: The assumption is that gather support is not
+		 * implemented in fast path and hence we can not receive
+		 * fragmented packets and so we do not need to take care
+		 * of freeing a fragmented packet
+		 */
+		dev_kfree_skb_any(nbuf);
+		return;
+	}
+
+	/*
+	 * TODO: Need to ensure the ndev is not removed before we take dev_hold().
+	 */
+	dev_hold(ndev);
+	nbuf->dev = ndev;
+
+	/*
+	 * Linearize the skb if needed
+	 *
+	 * Mixing up non linear check with in nss_core_skb_needs_linearize causes
+	 * unencessary performance impact because of netif_skb_features() API call unconditionally
+	 * Hence moved skb_is_nonlinear call outside.
+	 */
+	 if (unlikely(skb_is_nonlinear(nbuf))) {
+		if (nss_core_skb_needs_linearize(nbuf, (uint32_t)netif_skb_features(nbuf)) &&
+				__skb_linearize(nbuf)) {
+			/*
+			 * We needed to linearize, but __skb_linearize() failed. Therefore
+			 * we free the nbuf.
+			 */
+			dev_put(ndev);
+			dev_kfree_skb_any(nbuf);
+			return;
+		}
+	}
+
+	/*
+	 * Check to see if there is a xmit callback is registered
+	 * in this path. The callback will decide the queue mapping.
+	 */
+	if (unlikely((subsys_dp_reg->xmit_cb))) {
+		skb_set_queue_mapping(nbuf, 0);
+		subsys_dp_reg->xmit_cb(ndev, nbuf);
+		dev_put(ndev);
+		return;
+	}
+
+	/*
+	 * Mimic Linux behavior to allow multi-queue netdev choose which queue to use
+	 */
+	if (ndev->netdev_ops->ndo_select_queue) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+		queue_offset = ndev->netdev_ops->ndo_select_queue(ndev, nbuf, NULL, NULL);
+#else
+		queue_offset = ndev->netdev_ops->ndo_select_queue(ndev, nbuf, NULL);
+#endif
+	}
+
+	skb_set_queue_mapping(nbuf, queue_offset);
+
+	/*
+	 * Send the packet to virtual interface
+	 * NOTE: Invoking this will BYPASS any assigned QDisc - this is OKAY
+	 * as TX packets out of the NSS will have been shaped inside the NSS.
+	 */
+	xmit_ret = ndev->netdev_ops->ndo_start_xmit(nbuf, ndev);
+	if (unlikely(xmit_ret == NETDEV_TX_BUSY)) {
+		dev_kfree_skb_any(nbuf);
+		nss_info("%px: Congestion at virtual interface %d, %px", nss_ctx, interface_num, ndev);
+	}
+	dev_put(ndev);
+}
+
+/*
+ * nss_core_handle_buffer_pkt()
+ *	Handle data packet received on physical or virtual interface.
+ */
+static inline void nss_core_handle_buffer_pkt(struct nss_ctx_instance *nss_ctx,
+						unsigned int interface_num,
+						struct sk_buff *nbuf,
+						struct napi_struct *napi,
+						uint16_t flags, uint16_t qid, uint8_t service_code)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	struct nss_subsystem_dataplane_register *subsys_dp_reg = &nss_ctx->subsys_dp_register[interface_num];
+	struct net_device *ndev = NULL;
+	nss_phys_if_rx_callback_t cb;
+	uint16_t queue_offset = qid - NSS_IF_N2H_DATA_QUEUE_0;
+
+	NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_RX_PACKET]);
+
+	/*
+	 * Check if NSS was able to obtain checksum
+	 */
+	nbuf->ip_summed = CHECKSUM_UNNECESSARY;
+	if (unlikely(!(flags & N2H_BIT_FLAG_IP_TRANSPORT_CHECKSUM_VALID))) {
+		nbuf->ip_summed = CHECKSUM_NONE;
+	}
+
+	ndev = subsys_dp_reg->ndev;
+	if (!ndev) {
+		dev_kfree_skb_any(nbuf);
+		return;
+	}
+
+	/*
+	 * If we have a non-zero service code, call the corresponding service code
+	 * callback. The callback will consume the skb.
+	 * For service code, we provide the raw packet as it was received.
+	 */
+	if (unlikely(service_code)) {
+		nss_cmn_service_code_callback_t cb = nss_ctx->service_code_callback[service_code];
+		if (likely(cb)) {
+			dev_hold(ndev);
+			nbuf->dev = ndev;
+			nbuf->protocol = eth_type_trans(nbuf, ndev);
+			cb(nss_ctx->service_code_ctx[service_code], nbuf);
+			dev_put(ndev);
+			return;
+		}
+	}
+
+	/*
+	 * Deliver nbuf to the interface through callback if there is one.
+	 */
+	cb = subsys_dp_reg->cb;
+	if (likely(cb)) {
+		/*
+		 * linearize or free if requested.
+		 */
+	 	if (unlikely(skb_is_nonlinear(nbuf))) {
+			if (nss_core_skb_needs_linearize(nbuf, ndev->features) && __skb_linearize(nbuf)) {
+				dev_kfree_skb_any(nbuf);
+				return;
+			}
+		}
+
+		/*
+		 * Record RX queue if the netdev has that many RX queues
+		 */
+		if (queue_offset < ndev->real_num_rx_queues) {
+			skb_record_rx_queue(nbuf, queue_offset);
+		}
+
+		cb(ndev, (void *)nbuf, napi);
+		return;
+	}
+
+	/*
+	 * Deliver to the stack directly. Ex. there is no rule matched for
+	 * redirect interface.
+	 */
+	dev_hold(ndev);
+	nbuf->dev = ndev;
+	nbuf->protocol = eth_type_trans(nbuf, ndev);
+	netif_receive_skb(nbuf);
+	dev_put(ndev);
+}
+
+/*
+ * nss_core_handle_ext_buffer_pkt()
+ *	Handle Extended data plane packet received on physical or virtual interface.
+ */
+static inline void nss_core_handle_ext_buffer_pkt(struct nss_ctx_instance *nss_ctx,
+						unsigned int interface_num,
+						struct sk_buff *nbuf,
+						struct napi_struct *napi,
+						uint16_t flags)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	struct nss_subsystem_dataplane_register *subsys_dp_reg = &nss_ctx->subsys_dp_register[interface_num];
+	struct net_device *ndev = NULL;
+	nss_phys_if_rx_ext_data_callback_t ext_cb;
+
+	NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_RX_EXT_PACKET]);
+
+	/*
+	 * Check if NSS was able to obtain checksum
+	 */
+	nbuf->ip_summed = CHECKSUM_UNNECESSARY;
+	if (unlikely(!(flags & N2H_BIT_FLAG_IP_TRANSPORT_CHECKSUM_VALID))) {
+		nbuf->ip_summed = CHECKSUM_NONE;
+	}
+
+	ndev = subsys_dp_reg->ndev;
+	ext_cb = subsys_dp_reg->ext_cb;
+	if (likely(ext_cb) && likely(ndev)) {
+
+	 	if (unlikely(skb_is_nonlinear(nbuf))) {
+			if (nss_core_skb_needs_linearize(nbuf, ndev->features) && __skb_linearize(nbuf)) {
+				/*
+			 	* We needed to linearize, but __skb_linearize() failed. So free the nbuf.
+			 	*/
+				dev_kfree_skb_any(nbuf);
+				return;
+			}
+		}
+
+		ext_cb(ndev, (void *)nbuf, napi);
+	} else {
+		dev_kfree_skb_any(nbuf);
+	}
+}
+
+/*
+ * nss_core_rx_pbuf()
+ *	Receive a pbuf from the NSS into Linux.
+ */
+static inline void nss_core_rx_pbuf(struct nss_ctx_instance *nss_ctx, struct n2h_descriptor *desc, struct napi_struct *napi,
+				    uint8_t buffer_type, struct sk_buff *nbuf, uint16_t qid)
+{
+	unsigned int interface_num = NSS_INTERFACE_NUM_GET(desc->interface_num);
+	unsigned int core_id = NSS_INTERFACE_NUM_GET_COREID(desc->interface_num);
+	struct nss_shaper_bounce_registrant *reg = NULL;
+	int32_t status;
+
+	NSS_PKT_STATS_DEC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_NSS_SKB_COUNT]);
+
+	if (interface_num >= NSS_MAX_NET_INTERFACES) {
+		NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_RX_INVALID_INTERFACE]);
+		nss_warning("%px: Invalid interface_num: %d", nss_ctx, interface_num);
+		dev_kfree_skb_any(nbuf);
+		return;
+	}
+
+	/*
+	 * Check if core_id value is valid.
+	 */
+	if (core_id > nss_top_main.num_nss) {
+		NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_RX_INVALID_CORE_ID]);
+		nss_warning("%px: Invalid core id: %d", nss_ctx, core_id);
+		dev_kfree_skb_any(nbuf);
+		return;
+	}
+
+	/*
+	 * Check if need to convert to local core value.
+	 */
+	if (core_id) {
+		nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[core_id - 1];
+	}
+
+	switch (buffer_type) {
+	case N2H_BUFFER_PACKET:
+		nss_core_handle_buffer_pkt(nss_ctx, interface_num, nbuf, napi, desc->bit_flags, qid, desc->service_code);
+		break;
+
+	case N2H_BUFFER_PACKET_VIRTUAL:
+		nss_core_handle_virt_if_pkt(nss_ctx, interface_num, nbuf);
+		break;
+
+	case N2H_BUFFER_SHAPER_BOUNCED_INTERFACE:
+		reg = &nss_ctx->nss_top->bounce_interface_registrants[interface_num];
+		nss_core_handle_bounced_pkt(nss_ctx, reg, nbuf);
+		break;
+
+	case N2H_BUFFER_SHAPER_BOUNCED_BRIDGE:
+		reg = &nss_ctx->nss_top->bounce_bridge_registrants[interface_num];
+		nss_core_handle_bounced_pkt(nss_ctx, reg, nbuf);
+		break;
+
+	case N2H_BUFFER_PACKET_EXT:
+		nss_core_handle_ext_buffer_pkt(nss_ctx, interface_num, nbuf, napi, desc->bit_flags);
+		break;
+
+	case N2H_BUFFER_STATUS:
+		NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_RX_STATUS]);
+		nss_core_handle_nss_status_pkt(nss_ctx, nbuf);
+		dev_kfree_skb_any(nbuf);
+		break;
+
+	case N2H_BUFFER_CRYPTO_RESP:
+		NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_RX_CRYPTO_RESP]);
+		nss_core_handle_crypto_pkt(nss_ctx, interface_num, nbuf, napi);
+		break;
+
+	case N2H_BUFFER_RATE_TEST:
+
+		/*
+		 * This is a packet NSS sent for packet rate testing. The test measures the
+		 * maximum PPS we can achieve between the host and NSS. After we process
+		 * the descriptor, we directly send these test packets back to NSS without further process.
+		 * They are again marked with H2N_BUFFER_RATE_TEST buffer type so NSS can process
+		 * and count the test packets properly.
+		 */
+		NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_RX_STATUS]);
+		status = nss_core_send_buffer(nss_ctx, 0, nbuf, NSS_IF_H2N_DATA_QUEUE, H2N_BUFFER_RATE_TEST, H2N_BIT_FLAG_BUFFER_REUSABLE);
+		if (unlikely(status != NSS_CORE_STATUS_SUCCESS)) {
+			dev_kfree_skb_any(nbuf);
+			nss_warning("%px: Unable to enqueue\n", nss_ctx);
+		}
+		nss_hal_send_interrupt(nss_ctx, NSS_H2N_INTR_DATA_COMMAND_QUEUE);
+		break;
+
+	default:
+		NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_RX_INVALID_BUFFER_TYPE]);
+		nss_warning("%px: Invalid buffer type %d received from NSS", nss_ctx, buffer_type);
+		dev_kfree_skb_any(nbuf);
+	}
+}
+
+/*
+ * nss_core_set_skb_classify()
+ *	Set skb field to avoid ingress shaping.
+ */
+static inline void nss_core_set_skb_classify(struct sk_buff *nbuf)
+{
+#ifdef CONFIG_NET_CLS_ACT
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		nbuf->tc_verd = SET_TC_NCLS_NSS(nbuf->tc_verd);
+#else
+		skb_set_tc_classify_offload(nbuf);
+#endif
+#endif
+}
+
+/*
+ * nss_core_handle_nrfrag_skb()
+ *	Handled the processing of fragmented skb's
+ */
+static inline bool nss_core_handle_nr_frag_skb(struct nss_ctx_instance *nss_ctx, struct sk_buff **nbuf_ptr, struct sk_buff **jumbo_start_ptr, struct n2h_descriptor *desc, unsigned int buffer_type)
+{
+	struct sk_buff *nbuf = *nbuf_ptr;
+	struct sk_buff *jumbo_start = *jumbo_start_ptr;
+
+	uint16_t payload_len = desc->payload_len;
+	uint16_t payload_offs = desc->payload_offs;
+	uint16_t bit_flags = desc->bit_flags;
+
+	nss_assert(desc->payload_offs + desc->payload_len <= PAGE_SIZE);
+
+	dma_unmap_page(nss_ctx->dev, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE);
+
+	/*
+	 * The first and last bits are both set. Hence the received frame can't have
+	 * chains (or it's not a scattered one).
+	 */
+	if (likely(bit_flags & N2H_BIT_FLAG_FIRST_SEGMENT) && likely(bit_flags & N2H_BIT_FLAG_LAST_SEGMENT)) {
+
+		/*
+		 * We have received another head before we saw the last segment.
+		 * Free the old head as the frag list is corrupt.
+		 */
+		if (unlikely(jumbo_start)) {
+			nss_warning("%px: received a full frame before a last", jumbo_start);
+			dev_kfree_skb_any(jumbo_start);
+			*jumbo_start_ptr = NULL;
+		}
+
+		/*
+		 * NOTE: Need to use __skb_fill since we do not want to
+		 * increment nr_frags again. We just want to adjust the offset
+		 * and the length.
+		 */
+		__skb_fill_page_desc(nbuf, 0, skb_frag_page(&skb_shinfo(nbuf)->frags[0]), payload_offs, payload_len);
+
+		/*
+		 * We do not update truesize. We just keep the initial set value.
+		 */
+		nbuf->data_len = payload_len;
+		nbuf->len = payload_len;
+		nbuf->priority = desc->pri;
+
+#ifdef CONFIG_NET_CLS_ACT
+		/*
+		 * Skip the ingress QoS for the packet if the descriptor has
+		 * ingress shaped flag set.
+		 */
+		if (unlikely(desc->bit_flags & N2H_BIT_FLAG_INGRESS_SHAPED)) {
+			nss_core_set_skb_classify(nbuf);
+		}
+#endif
+
+		goto pull;
+	}
+
+	/*
+	 * Track Number of Fragments processed. First && Last is not true fragment
+	 */
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_FRAG_SEG_PROCESSED]);
+
+	/*
+	 * NSS sent us an SG chain.
+	 * Build a frags[] out of segments.
+	 */
+	if (unlikely((bit_flags & N2H_BIT_FLAG_FIRST_SEGMENT))) {
+
+		/*
+		 * We have received another head before we saw the last segment.
+		 * Free the old head as the frag list is corrupt.
+		 */
+		if (unlikely(jumbo_start)) {
+			nss_warning("%px: received the second head before a last", jumbo_start);
+			dev_kfree_skb_any(jumbo_start);
+		}
+
+		/*
+		 * We do not update truesize. We just keep the initial set value.
+		 */
+		__skb_fill_page_desc(nbuf, 0, skb_frag_page(&skb_shinfo(nbuf)->frags[0]), payload_offs, payload_len);
+		nbuf->data_len = payload_len;
+		nbuf->len = payload_len;
+		nbuf->priority = desc->pri;
+
+#ifdef CONFIG_NET_CLS_ACT
+		/*
+		 * Skip the ingress QoS for the packet if the descriptor has
+		 * ingress shaped flag set.
+		 */
+		if (unlikely(desc->bit_flags & N2H_BIT_FLAG_INGRESS_SHAPED)) {
+			nss_core_set_skb_classify(nbuf);
+		}
+#endif
+
+		/*
+		 * Set jumbo pointer to nbuf
+		 */
+		*jumbo_start_ptr = nbuf;
+
+		/*
+		 * Skip sending until last is received.
+		 */
+		return false;
+	}
+
+	NSS_PKT_STATS_DEC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_NSS_SKB_COUNT]);
+
+	/*
+	 * We've received a middle or a last segment.
+	 * Check that we have received a head first to avoid null deferencing.
+	 */
+	if (unlikely(jumbo_start == NULL)) {
+		/*
+		 * Middle before first! Free the middle.
+		 */
+		nss_warning("%px: saw a middle skb before head", nbuf);
+		dev_kfree_skb_any(nbuf);
+		return false;
+	}
+
+	/*
+	 * Free the skb after attaching the frag to the head skb.
+	 * Our page is safe although we are freeing it because we
+	 * just took a reference to it.
+	 */
+	skb_add_rx_frag(jumbo_start, skb_shinfo(jumbo_start)->nr_frags, skb_frag_page(&skb_shinfo(nbuf)->frags[0]), payload_offs, payload_len, PAGE_SIZE);
+	skb_frag_ref(jumbo_start, skb_shinfo(jumbo_start)->nr_frags - 1);
+	dev_kfree_skb_any(nbuf);
+
+	if (!(bit_flags & N2H_BIT_FLAG_LAST_SEGMENT)) {
+		/*
+		 * Skip sending until last is received.
+		 */
+		return false;
+	}
+
+	/*
+	 * Last is received. Set nbuf pointer to point to
+	 * the jumbo skb so that it continues to get processed.
+	 */
+	nbuf = jumbo_start;
+	*nbuf_ptr = nbuf;
+	*jumbo_start_ptr = NULL;
+	prefetch((void *)(nbuf->data));
+
+pull:
+	/*
+	 * We need eth hdr to be in the linear part of the skb
+	 * for data packets. Otherwise eth_type_trans fails.
+	 */
+	if (buffer_type != N2H_BUFFER_STATUS) {
+		if (!pskb_may_pull(nbuf, ETH_HLEN)) {
+			dev_kfree_skb(nbuf);
+			nss_warning("%px: could not pull eth header", nbuf);
+			return false;
+		}
+	}
+
+	return true;
+}
+
+/*
+ * nss_core_handle_linear_skb()
+ *	Handler for processing linear skbs.
+ */
+static inline bool nss_core_handle_linear_skb(struct nss_ctx_instance *nss_ctx, struct sk_buff **nbuf_ptr, struct sk_buff **head_ptr,
+						struct sk_buff **tail_ptr, struct n2h_descriptor *desc)
+{
+	uint16_t bit_flags = desc->bit_flags;
+	struct sk_buff *nbuf = *nbuf_ptr;
+	struct sk_buff *head = *head_ptr;
+	struct sk_buff *tail = *tail_ptr;
+
+	/*
+	 * We are in linear SKB mode.
+	 */
+	nbuf->data = nbuf->head + desc->payload_offs;
+	nbuf->len = desc->payload_len;
+	skb_set_tail_pointer(nbuf, nbuf->len);
+
+	dma_unmap_single(nss_ctx->dev, (desc->buffer + desc->payload_offs), desc->payload_len,
+			 DMA_FROM_DEVICE);
+
+	prefetch((void *)(nbuf->data));
+
+	if (likely(bit_flags & N2H_BIT_FLAG_FIRST_SEGMENT) && likely(bit_flags & N2H_BIT_FLAG_LAST_SEGMENT)) {
+
+		/*
+		 * We have received another head before we saw the last segment.
+		 * Free the old head as the frag list is corrupt.
+		 */
+		if (unlikely(head)) {
+			nss_warning("%px: received a full frame before a last", head);
+			dev_kfree_skb_any(head);
+			*head_ptr = NULL;
+		}
+
+		nbuf->priority = desc->pri;
+
+#ifdef CONFIG_NET_CLS_ACT
+		/*
+		 * Skip the ingress QoS for the packet if the descriptor has
+		 * ingress shaped flag set.
+		 */
+		if (unlikely(desc->bit_flags & N2H_BIT_FLAG_INGRESS_SHAPED)) {
+			nss_core_set_skb_classify(nbuf);
+		}
+#endif
+
+		/*
+		 * TODO: Check if there is any issue wrt map and unmap,
+		 * NSS should playaround with data area and should not
+		 * touch HEADROOM area
+		 */
+		NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_RX_SIMPLE]);
+		return true;
+	}
+
+	/*
+	 * Track number of skb chain processed. First && Last is not true segment.
+	 */
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_CHAIN_SEG_PROCESSED]);
+
+	/*
+	 * NSS sent us an SG chain.
+	 * Build a frag list out of segments.
+	 */
+	if (unlikely((bit_flags & N2H_BIT_FLAG_FIRST_SEGMENT))) {
+
+		/*
+		 * We have received another head before we saw the last segment.
+		 * Free the old head as the frag list is corrupt.
+		 */
+		if (unlikely(head)) {
+			nss_warning("%px: received the second head before a last", head);
+			NSS_PKT_STATS_DEC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_NSS_SKB_COUNT]);
+			dev_kfree_skb_any(head);
+		}
+
+		/*
+		 * Found head.
+		 */
+		if (unlikely(skb_has_frag_list(nbuf))) {
+			/*
+			 * We don't support chain in a chain.
+			 */
+			nss_warning("%px: skb already has a fraglist", nbuf);
+			NSS_PKT_STATS_DEC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_NSS_SKB_COUNT]);
+			dev_kfree_skb_any(nbuf);
+			return false;
+		}
+
+		skb_frag_list_init(nbuf);
+		nbuf->data_len = 0;
+		nbuf->truesize = desc->payload_len;
+		nbuf->priority = desc->pri;
+
+#ifdef CONFIG_NET_CLS_ACT
+		/*
+		 * Skip the ingress QoS for the packet if the descriptor has
+		 * ingress shaped flag set.
+		 */
+		if (unlikely(desc->bit_flags & N2H_BIT_FLAG_INGRESS_SHAPED)) {
+			nss_core_set_skb_classify(nbuf);
+		}
+#endif
+
+		*head_ptr = nbuf;
+
+		/*
+		 * Skip sending until last is received.
+		 */
+		return false;
+	}
+
+	NSS_PKT_STATS_DEC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_NSS_SKB_COUNT]);
+
+	/*
+	 * We've received a middle segment.
+	 * Check that we have received a head first to avoid null deferencing.
+	 */
+	if (unlikely(head == NULL)) {
+
+		/*
+		 * Middle before first! Free the middle.
+		 */
+		nss_warning("%px: saw a middle skb before head", nbuf);
+		dev_kfree_skb_any(nbuf);
+
+		return false;
+	}
+
+	if (!skb_has_frag_list(head)) {
+		/*
+		 * 2nd skb in the chain. head's frag_list should point to him.
+		 */
+		nbuf->next = skb_shinfo(head)->frag_list;
+		skb_shinfo(head)->frag_list = nbuf;
+	} else {
+		/*
+		 * 3rd, 4th... skb in the chain. The chain's previous tail's
+		 * next should point to him.
+		 */
+		tail->next = nbuf;
+		nbuf->next = NULL;
+	}
+	*tail_ptr = nbuf;
+
+	/*
+	 * Now we've added a new nbuf to the chain.
+	 * Update the chain length.
+	 */
+	head->data_len += desc->payload_len;
+	head->len += desc->payload_len;
+	head->truesize += desc->payload_len;
+
+	if (!(bit_flags & N2H_BIT_FLAG_LAST_SEGMENT)) {
+		/*
+		 * Skip sending until last is received.
+		 */
+		return false;
+	}
+
+	/*
+	 * Last is received. Send the frag_list.
+	 */
+	*nbuf_ptr = head;
+	*head_ptr = NULL;
+	*tail_ptr = NULL;
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_RX_SKB_FRAGLIST]);
+	return true;
+}
+
+/*
+ * nss_core_handle_empty_buffers()
+ *	Handle empty buffer returns.
+ */
+static inline void nss_core_handle_empty_buffers(struct nss_ctx_instance *nss_ctx,
+						 struct nss_if_mem_map *if_map,
+						 struct hlos_n2h_desc_ring *n2h_desc_ring,
+						 struct n2h_descriptor *desc_ring,
+						 struct n2h_descriptor *desc,
+						 uint32_t count, uint32_t hlos_index,
+						 uint16_t mask)
+{
+	while (count) {
+		/*
+		 * Since we only return the primary skb, we have no way to unmap
+		 * properly. Simple skb's are properly mapped but page data skbs
+		 * have the payload mapped (and not the skb->data slab payload).
+		 *
+		 * Warning: On non-Krait HW, we need to unmap fragments.
+		 *
+		 * This only unmaps the first segment either slab payload or
+		 * skb page data. Eventually, we need to unmap all of a frag_list
+		 * or all of page_data however this is not a big concern as of now
+		 * since on Kriats dma_map_single() does not allocate any resource
+		 * and hence dma_unmap_single() is sort off a nop.
+		 *
+		 * No need to invalidate for Tx Completions, so set dma direction = DMA_TO_DEVICE;
+		 * Similarly prefetch is not needed for an empty buffer.
+		 */
+		struct sk_buff *nbuf;
+
+		/*
+		 * Prefetch the next cache line of descriptors.
+		 */
+		if (((hlos_index & 1) == 0) && likely(count > 2)) {
+			struct n2h_descriptor *next_cache_desc = &desc_ring[(hlos_index + 2) & mask];
+			prefetch(next_cache_desc);
+		}
+
+		nbuf = (struct sk_buff *)desc->opaque;
+
+		if (unlikely(nbuf < (struct sk_buff *)PAGE_OFFSET)) {
+			/*
+			 * Invalid opaque pointer
+			 */
+			nss_dump_desc(nss_ctx, desc);
+			NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_RX_BAD_DESCRIPTOR]);
+			goto next;
+		}
+
+		dma_unmap_single(nss_ctx->dev, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_TO_DEVICE);
+		dev_kfree_skb_any(nbuf);
+
+		NSS_PKT_STATS_DEC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_NSS_SKB_COUNT]);
+		NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_RX_EMPTY]);
+
+next:
+		hlos_index = (hlos_index + 1) & (mask);
+		desc = &desc_ring[hlos_index];
+		count--;
+	}
+
+	n2h_desc_ring->hlos_index = hlos_index;
+	if_map->n2h_hlos_index[NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE] = hlos_index;
+
+	NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_hlos_index[NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE);
+	NSS_CORE_DSB();
+}
+
+/*
+ * nss_core_handle_cause_queue()
+ *	Handle interrupt cause related to N2H/H2N queues
+ */
+static int32_t nss_core_handle_cause_queue(struct int_ctx_instance *int_ctx, uint16_t cause, int16_t weight)
+{
+	int16_t count, count_temp;
+	uint16_t size, mask, qid;
+	uint32_t nss_index, hlos_index, start, end;
+	struct sk_buff *nbuf;
+	struct hlos_n2h_desc_ring *n2h_desc_ring;
+	struct n2h_desc_if_instance *desc_if;
+	struct n2h_descriptor *desc_ring;
+	struct n2h_descriptor *desc;
+	struct n2h_descriptor *next_cache_desc;
+	struct nss_ctx_instance *nss_ctx = int_ctx->nss_ctx;
+	struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
+	struct nss_if_mem_map *if_map = mem_ctx->if_map;
+
+	qid = nss_core_cause_to_queue(cause);
+
+	/*
+	 * Make sure qid < num_rings
+	 */
+	nss_assert(qid < if_map->n2h_rings);
+
+	n2h_desc_ring = &nss_ctx->n2h_desc_ring[qid];
+	desc_if = &n2h_desc_ring->desc_ring;
+	desc_ring = desc_if->desc;
+	NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE);
+	NSS_CORE_DSB();
+	nss_index = if_map->n2h_nss_index[qid];
+
+	hlos_index = n2h_desc_ring->hlos_index;
+	size = desc_if->size;
+	mask = size - 1;
+
+	/*
+	 * Check if there is work to be done for this queue
+	 */
+	count = ((nss_index - hlos_index) + size) & (mask);
+	if (unlikely(count == 0)) {
+		return 0;
+	}
+
+	/*
+	 * Restrict ourselves to suggested weight
+	 */
+	if (count > weight) {
+		count = weight;
+	}
+
+	/*
+	 * Invalidate all the descriptors we are going to read
+	 */
+	start = hlos_index;
+	end = (hlos_index + count) & mask;
+	if (end > start) {
+		dmac_inv_range((void *)&desc_ring[start], (void *)&desc_ring[end] + sizeof(struct n2h_descriptor));
+	} else {
+		/*
+		 * We have wrapped around
+		 */
+		dmac_inv_range((void *)&desc_ring[start], (void *)&desc_ring[mask] + sizeof(struct n2h_descriptor));
+		dmac_inv_range((void *)&desc_ring[0], (void *)&desc_ring[end] + sizeof(struct n2h_descriptor));
+	}
+
+	/*
+	 * Prefetch the first descriptor
+	 */
+	desc = &desc_ring[hlos_index];
+	prefetch(desc);
+
+	/*
+	 * Prefetch the next cache line of descriptors if we are starting with
+	 * the second descriptor in the cache line. If it is the first in the cache line,
+	 * this will be done inside the loop.
+	 */
+	if (((hlos_index & 1) == 1) && likely((count > 1))) {
+		next_cache_desc = &desc_ring[(hlos_index + 2) & mask];
+		prefetch(next_cache_desc);
+	}
+
+	if (qid == NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE) {
+		nss_core_handle_empty_buffers(nss_ctx, if_map, n2h_desc_ring, desc_ring, desc, count, hlos_index, mask);
+		return count;
+	}
+
+	count_temp = count;
+	while (count_temp) {
+		unsigned int buffer_type;
+		nss_ptr_t opaque;
+
+		/*
+		 * Prefetch the next cache line of descriptors.
+		 */
+		if (((hlos_index & 1) == 0) && likely(count_temp > 2)) {
+			next_cache_desc = &desc_ring[(hlos_index + 2) & mask];
+			prefetch(next_cache_desc);
+		}
+
+		buffer_type = desc->buffer_type;
+		opaque = desc->opaque;
+
+		/*
+		 * Obtain nbuf
+		 */
+		nbuf = (struct sk_buff *)opaque;
+		if (unlikely(nbuf < (struct sk_buff *)PAGE_OFFSET)) {
+			/*
+			 * Invalid opaque pointer
+			 */
+			nss_dump_desc(nss_ctx, desc);
+			NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_RX_BAD_DESCRIPTOR]);
+			goto next;
+		}
+
+		/*
+		 * Shaping uses the singleton approach as well. No need to unmap all the segments since only
+		 * one of them is actually looked at.
+		 */
+		if ((unlikely(buffer_type == N2H_BUFFER_SHAPER_BOUNCED_INTERFACE)) || (unlikely(buffer_type == N2H_BUFFER_SHAPER_BOUNCED_BRIDGE))) {
+			dma_unmap_page(nss_ctx->dev, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_TO_DEVICE);
+			goto consume;
+		}
+
+		/*
+		 * crypto buffer
+		 *
+		 */
+		if (unlikely((buffer_type == N2H_BUFFER_CRYPTO_RESP))) {
+			dma_unmap_single(NULL, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE);
+			goto consume;
+		}
+
+		/*
+		 * Check if we received a paged skb.
+		 */
+		if (skb_shinfo(nbuf)->nr_frags > 0) {
+			/*
+			 * Check if we received paged skb while constructing
+			 * a linear skb chain. If so we need to free.
+			 */
+			if (unlikely(n2h_desc_ring->head)) {
+				nss_warning("%px: we should not have an incomplete paged skb while"
+								" constructing a linear skb %px", nbuf, n2h_desc_ring->head);
+
+				NSS_PKT_STATS_DEC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_NSS_SKB_COUNT]);
+				dev_kfree_skb_any(n2h_desc_ring->head);
+				n2h_desc_ring->head = NULL;
+			}
+
+			if (!nss_core_handle_nr_frag_skb(nss_ctx, &nbuf, &n2h_desc_ring->jumbo_start, desc, buffer_type)) {
+				goto next;
+			}
+			NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_RX_NR_FRAGS]);
+			goto consume;
+		}
+
+		/*
+		 * Check if we received a linear skb while constructing
+		 * a paged skb. If so we need to free the paged_skb and handle the linear skb.
+		 */
+		if (unlikely(n2h_desc_ring->jumbo_start)) {
+			nss_warning("%px: we should not have an incomplete linear skb while"
+							" constructing a paged skb %px", nbuf, n2h_desc_ring->jumbo_start);
+
+			NSS_PKT_STATS_DEC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_NSS_SKB_COUNT]);
+			dev_kfree_skb_any(n2h_desc_ring->jumbo_start);
+			n2h_desc_ring->jumbo_start = NULL;
+		}
+
+		/*
+		 * This is a simple linear skb. Use the the linear skb
+		 * handler to process it.
+		 */
+		if (!nss_core_handle_linear_skb(nss_ctx, &nbuf, &n2h_desc_ring->head, &n2h_desc_ring->tail, desc)) {
+			goto next;
+		}
+
+consume:
+		nss_core_rx_pbuf(nss_ctx, desc, &(int_ctx->napi), buffer_type, nbuf, qid);
+
+next:
+
+		hlos_index = (hlos_index + 1) & (mask);
+		desc = &desc_ring[hlos_index];
+		count_temp--;
+	}
+
+	n2h_desc_ring->hlos_index = hlos_index;
+	if_map->n2h_hlos_index[qid] = hlos_index;
+
+	NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_hlos_index[qid], sizeof(uint32_t), DMA_TO_DEVICE);
+	NSS_CORE_DSB();
+
+	return count;
+}
+
+/*
+ * nss_core_init_nss()
+ *	Initialize NSS core state
+ */
+static void nss_core_init_nss(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map)
+{
+	struct nss_top_instance *nss_top;
+	int ret;
+
+	NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(*if_map), DMA_FROM_DEVICE);
+	NSS_CORE_DSB();
+
+	/*
+	 * NOTE: A commonly found error is that sizes and start address of per core
+	 *	virtual register map do not match in NSS and HLOS builds. This will lead
+	 *	to some hard to trace issues such as spinlock magic check failure etc.
+	 *	Following checks verify that proper virtual map has been initialized
+	 */
+	nss_assert(if_map->magic == DEV_MAGIC);
+
+#ifdef NSS_DRV_C2C_ENABLE
+	nss_ctx->c2c_start = nss_ctx->meminfo_ctx.c2c_start_dma;
+#endif
+
+	nss_top = nss_ctx->nss_top;
+	spin_lock_bh(&nss_top->lock);
+	nss_ctx->state = NSS_CORE_STATE_INITIALIZED;
+	spin_unlock_bh(&nss_top->lock);
+
+	if (nss_ctx->id) {
+		ret = nss_n2h_update_queue_config_async(nss_ctx, pn_mq_en, pn_qlimits);
+		if (ret != NSS_TX_SUCCESS) {
+			nss_warning("Failed to send pnode queue config to core 1\n");
+		}
+		return;
+	}
+
+	/*
+	 * If nss core0 is up, then we are ready to hook to nss-gmac
+	 */
+	if (nss_data_plane_schedule_registration()) {
+
+		/*
+		 * Configure the maximum number of IPv4/IPv6
+		 * connections supported by the accelerator.
+		 */
+		nss_ipv4_conn_cfg = max_ipv4_conn;
+#ifdef NSS_DRV_IPV6_ENABLE
+		nss_ipv6_conn_cfg = max_ipv6_conn;
+		nss_ipv6_update_conn_count(max_ipv6_conn);
+#endif
+		nss_ipv4_update_conn_count(max_ipv4_conn);
+
+#ifdef NSS_MEM_PROFILE_LOW
+		/*
+		 * For low memory profiles, restrict the number of empty buffer pool
+		 * size to NSS_LOW_MEM_EMPTY_POOL_BUF_SZ. Overwrite the default number
+		 * of empty buffer pool size configured during NSS initialization.
+		 */
+		ret = nss_n2h_cfg_empty_pool_size(nss_ctx, NSS_LOW_MEM_EMPTY_POOL_BUF_SZ);
+		if (ret != NSS_TX_SUCCESS) {
+			nss_warning("%px: Failed to update empty buffer pool config\n", nss_ctx);
+		}
+#endif
+	} else {
+		spin_lock_bh(&nss_top->lock);
+		nss_ctx->state = NSS_CORE_STATE_UNINITIALIZED;
+		spin_unlock_bh(&nss_top->lock);
+	}
+}
+
+/*
+ * nss_core_alloc_paged_buffers()
+ *	Allocate paged buffers for SOS.
+ */
+static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map,
+				uint16_t count, int16_t mask, int32_t hlos_index, uint32_t alloc_fail_count,
+				uint32_t buffer_type, uint32_t buffer_queue, uint32_t stats_index)
+{
+	struct sk_buff *nbuf;
+	struct page *npage;
+	struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[buffer_queue];
+	struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring;
+	struct h2n_descriptor *desc_ring = desc_if->desc;
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	while (count) {
+		struct h2n_descriptor *desc = &desc_ring[hlos_index];
+		dma_addr_t buffer;
+
+		/*
+		 * Alloc an skb AND a page.
+		 */
+		nbuf = dev_alloc_skb(NSS_CORE_JUMBO_LINEAR_BUF_SIZE);
+		if (unlikely(!nbuf)) {
+			/*
+			 * ERR:
+			 */
+			NSS_PKT_STATS_INC(&nss_top->stats_drv[alloc_fail_count]);
+			nss_warning("%px: Could not obtain empty paged buffer", nss_ctx);
+			break;
+		}
+
+		npage = alloc_page(GFP_ATOMIC);
+		if (unlikely(!npage)) {
+			/*
+			 * ERR:
+			 */
+			dev_kfree_skb_any(nbuf);
+			NSS_PKT_STATS_INC(&nss_top->stats_drv[alloc_fail_count]);
+			nss_warning("%px: Could not obtain empty page", nss_ctx);
+			break;
+		}
+
+		/*
+		 * When we alloc an skb, initially head = data = tail and len = 0.
+		 * So nobody will try to read the linear part of the skb.
+		 */
+		skb_fill_page_desc(nbuf, 0, npage, 0, PAGE_SIZE);
+		nbuf->data_len += PAGE_SIZE;
+		nbuf->len += PAGE_SIZE;
+		nbuf->truesize += PAGE_SIZE;
+
+		/* Map the page for jumbo */
+		buffer = dma_map_page(nss_ctx->dev, npage, 0, PAGE_SIZE, DMA_FROM_DEVICE);
+		desc->buffer_len = PAGE_SIZE;
+		desc->payload_offs = 0;
+
+		if (unlikely(dma_mapping_error(nss_ctx->dev, buffer))) {
+			/*
+			 * ERR:
+			 */
+			dev_kfree_skb_any(nbuf);
+			nss_warning("%px: DMA mapping failed for empty buffer", nss_ctx);
+			break;
+		}
+		/*
+		 * We are holding this skb in NSS FW, let kmemleak know about it
+		 */
+		kmemleak_not_leak(nbuf);
+		NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_NSS_SKB_COUNT]);
+		desc->opaque = (nss_ptr_t)nbuf;
+		desc->buffer = buffer;
+		desc->buffer_type = buffer_type;
+
+		/*
+		 * Flush the descriptor
+		 */
+		NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE);
+
+		hlos_index = (hlos_index + 1) & (mask);
+		count--;
+	}
+
+	/*
+	 * Wait for the flushes to be synced before writing the index
+	 */
+	NSS_CORE_DSB();
+
+	h2n_desc_ring->hlos_index = hlos_index;
+	if_map->h2n_hlos_index[buffer_queue] = hlos_index;
+
+	NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[buffer_queue], sizeof(uint32_t), DMA_TO_DEVICE);
+	NSS_CORE_DSB();
+
+	NSS_PKT_STATS_INC(&nss_top->stats_drv[stats_index]);
+}
+
+/*
+ * nss_core_alloc_jumbo_mru_buffers()
+ *	Allocate jumbo mru buffers.
+ */
+static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map,
+				int jumbo_mru, uint16_t count, int16_t mask, int32_t hlos_index)
+{
+
+	struct sk_buff *nbuf;
+	struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE];
+	struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring;
+	struct h2n_descriptor *desc_ring = desc_if->desc;
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	while (count) {
+		struct h2n_descriptor *desc = &desc_ring[hlos_index];
+		dma_addr_t buffer;
+		nbuf = dev_alloc_skb(jumbo_mru);
+		if (unlikely(!nbuf)) {
+			/*
+			 * ERR:
+			 */
+			NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_NBUF_ALLOC_FAILS]);
+			nss_warning("%px: Could not obtain empty jumbo mru buffer", nss_ctx);
+			break;
+		}
+
+		/*
+		 * Map the skb
+		 */
+		buffer = dma_map_single(nss_ctx->dev, nbuf->head, jumbo_mru, DMA_FROM_DEVICE);
+		desc->buffer_len = jumbo_mru;
+		desc->payload_offs = (uint16_t) (nbuf->data - nbuf->head);
+		if (unlikely(dma_mapping_error(nss_ctx->dev, buffer))) {
+			/*
+			 * ERR:
+			 */
+			dev_kfree_skb_any(nbuf);
+			nss_warning("%px: DMA mapping failed for empty buffer", nss_ctx);
+			break;
+		}
+
+		/*
+		 * We are holding this skb in NSS FW, let kmemleak know about it
+		 */
+		kmemleak_not_leak(nbuf);
+		NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_NSS_SKB_COUNT]);
+		desc->opaque = (nss_ptr_t)nbuf;
+		desc->buffer = buffer;
+		desc->buffer_type = H2N_BUFFER_EMPTY;
+
+		/*
+		 * Flush the descriptor
+		 */
+		NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE);
+
+		hlos_index = (hlos_index + 1) & (mask);
+		count--;
+	}
+
+	/*
+	 * Wait for the flushes to be synced before writing the index
+	 */
+	NSS_CORE_DSB();
+
+	h2n_desc_ring->hlos_index = hlos_index;
+	if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE] = hlos_index;
+
+	NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE);
+	NSS_CORE_DSB();
+
+	NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_TX_EMPTY]);
+}
+
+/*
+ * nss_core_alloc_max_avail_size_buffers()
+ *	Allocate maximum available sized buffers.
+ */
+static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map,
+				uint16_t max_buf_size, uint16_t count, int16_t mask, int32_t hlos_index)
+{
+	struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE];
+	struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring;
+	struct h2n_descriptor *desc_ring = desc_if->desc;
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	uint16_t payload_len = max_buf_size + NET_SKB_PAD;
+	uint16_t start = hlos_index;
+	uint16_t prev_hlos_index;
+
+	while (count) {
+		dma_addr_t buffer;
+		struct h2n_descriptor *desc = &desc_ring[hlos_index];
+
+		struct sk_buff *nbuf = dev_alloc_skb(max_buf_size);
+		if (unlikely(!nbuf)) {
+			/*
+			 * ERR:
+			 */
+			NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_NBUF_ALLOC_FAILS]);
+			nss_warning("%px: Could not obtain empty buffer", nss_ctx);
+			break;
+		}
+
+		/*
+		 * Map the skb
+		 */
+		buffer = dma_map_single(nss_ctx->dev, nbuf->head, payload_len, DMA_FROM_DEVICE);
+
+		if (unlikely(dma_mapping_error(nss_ctx->dev, buffer))) {
+			/*
+			 * ERR:
+			 */
+			dev_kfree_skb_any(nbuf);
+			nss_warning("%px: DMA mapping failed for empty buffer", nss_ctx);
+			break;
+		}
+
+		/*
+		 * We are holding this skb in NSS FW, let kmemleak know about it
+		 */
+		kmemleak_not_leak(nbuf);
+		NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_NSS_SKB_COUNT]);
+
+		desc->opaque = (nss_ptr_t)nbuf;
+		desc->buffer = buffer;
+		desc->buffer_len = payload_len;
+
+		hlos_index = (hlos_index + 1) & (mask);
+		count--;
+	}
+
+	/*
+	 * Find the last descriptor we need to flush.
+	 */
+	prev_hlos_index = (hlos_index - 1) & mask;
+
+	/*
+	 * Flush the descriptors, including the descriptor at prev_hlos_index.
+	 */
+	if (prev_hlos_index > start) {
+		dmac_clean_range((void *)&desc_ring[start], (void *)&desc_ring[prev_hlos_index] + sizeof(struct h2n_descriptor));
+	} else {
+		/*
+		 * We have wrapped around
+		 */
+		dmac_clean_range((void *)&desc_ring[start], (void *)&desc_ring[mask] + sizeof(struct h2n_descriptor));
+		dmac_clean_range((void *)&desc_ring[0], (void *)&desc_ring[prev_hlos_index] + sizeof(struct h2n_descriptor));
+	}
+
+	/*
+	 * Wait for the flushes to be synced before writing the index
+	 */
+	NSS_CORE_DSB();
+
+	h2n_desc_ring->hlos_index = hlos_index;
+	if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE] = hlos_index;
+
+	NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE);
+	NSS_CORE_DSB();
+
+	NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_TX_EMPTY]);
+}
+
+/*
+ * nss_core_handle_empty_buffer_sos()
+ *	Handle empty buffer SOS interrupt.
+ */
+static inline void nss_core_handle_empty_buffer_sos(struct nss_ctx_instance *nss_ctx,
+				struct nss_if_mem_map *if_map, uint16_t max_buf_size)
+{
+	uint16_t count, size, mask;
+	int32_t nss_index, hlos_index;
+	struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE];
+
+	int paged_mode = nss_core_get_paged_mode();
+	int jumbo_mru = nss_core_get_jumbo_mru();
+
+	/*
+	 * Check how many empty buffers could be filled in queue
+	 */
+	NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_FROM_DEVICE);
+	NSS_CORE_DSB();
+	nss_index = if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE];
+
+	hlos_index = h2n_desc_ring->hlos_index;
+	size = h2n_desc_ring->desc_ring.size;
+
+	mask = size - 1;
+	count = ((nss_index - hlos_index - 1) + size) & (mask);
+
+	nss_trace("%px: Adding %d buffers to empty queue\n", nss_ctx, count);
+
+	/*
+	 * Fill empty buffer queue with buffers leaving one empty descriptor
+	 * Note that total number of descriptors in queue cannot be more than (size - 1)
+	 */
+	if (!count) {
+		return;
+	}
+
+	if (paged_mode) {
+		nss_core_alloc_paged_buffers(nss_ctx, if_map, count, mask, hlos_index,
+					NSS_DRV_STATS_NBUF_ALLOC_FAILS, H2N_BUFFER_EMPTY,
+					NSS_IF_H2N_EMPTY_BUFFER_QUEUE, NSS_DRV_STATS_TX_EMPTY);
+	} else if (jumbo_mru) {
+		nss_core_alloc_jumbo_mru_buffers(nss_ctx, if_map, jumbo_mru, count,
+					mask, hlos_index);
+	} else {
+		nss_core_alloc_max_avail_size_buffers(nss_ctx, if_map, max_buf_size,
+					count, mask, hlos_index);
+	}
+
+	/*
+	 * Inform NSS that new buffers are available
+	 */
+	nss_hal_send_interrupt(nss_ctx, NSS_H2N_INTR_EMPTY_BUFFER_QUEUE);
+}
+
+/*
+ * nss_core_handle_paged_empty_buffer_sos()
+ *	Handle paged empty buffer SOS.
+ */
+static inline void nss_core_handle_paged_empty_buffer_sos(struct nss_ctx_instance *nss_ctx,
+				struct nss_if_mem_map *if_map, uint16_t max_buf_size)
+{
+	uint16_t count, size, mask;
+	int32_t nss_index, hlos_index;
+	struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE];
+
+	/*
+	 * Check how many empty buffers could be filled in queue
+	 */
+	NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE], sizeof(uint32_t), DMA_FROM_DEVICE);
+	NSS_CORE_DSB();
+	nss_index = if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE];
+
+	hlos_index = h2n_desc_ring->hlos_index;
+	size = h2n_desc_ring->desc_ring.size;
+
+	mask = size - 1;
+	count = ((nss_index - hlos_index - 1) + size) & (mask);
+	nss_trace("%px: Adding %d buffers to paged buffer queue", nss_ctx, count);
+
+	/*
+	 * Fill empty buffer queue with buffers leaving one empty descriptor
+	 * Note that total number of descriptors in queue cannot be more than (size - 1)
+	 */
+	if (!count) {
+		return;
+	}
+
+	nss_core_alloc_paged_buffers(nss_ctx, if_map, count, mask, hlos_index,
+			NSS_DRV_STATS_PAGED_BUF_ALLOC_FAILS, H2N_PAGED_BUFFER_EMPTY,
+			NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE, NSS_DRV_STATS_PAGED_TX_EMPTY);
+
+	/*
+	 * Inform NSS that new buffers are available
+	 */
+	nss_hal_send_interrupt(nss_ctx, NSS_H2N_INTR_EMPTY_PAGED_BUFFER_QUEUE);
+}
+
+/*
+ * nss_core_handle_tx_unblocked()
+ *	Handle TX Unblocked.
+ */
+static inline void nss_core_handle_tx_unblocked(struct nss_ctx_instance *nss_ctx)
+{
+	int32_t i;
+	nss_trace("%px: Data queue unblocked", nss_ctx);
+
+	/*
+	 * Call callback functions of drivers that have registered with us
+	 */
+	spin_lock_bh(&nss_ctx->decongest_cb_lock);
+
+	for (i = 0; i < NSS_MAX_CLIENTS; i++) {
+		if (nss_ctx->queue_decongestion_callback[i]) {
+			nss_ctx->queue_decongestion_callback[i](nss_ctx->queue_decongestion_ctx[i]);
+		}
+	}
+
+	spin_unlock_bh(&nss_ctx->decongest_cb_lock);
+	nss_ctx->h2n_desc_rings[NSS_IF_H2N_DATA_QUEUE].flags &= ~NSS_H2N_DESC_RING_FLAGS_TX_STOPPED;
+
+	/*
+	 * Mask Tx unblocked interrupt and unmask it again when queue full condition is reached
+	 */
+	nss_hal_disable_interrupt(nss_ctx, nss_ctx->int_ctx[0].shift_factor, NSS_N2H_INTR_TX_UNBLOCKED);
+}
+
+/*
+ * nss_core_handle_cause_nonqueue()
+ *	Handle non-queue interrupt causes (e.g. empty buffer SOS, Tx unblocked)
+ */
+static void nss_core_handle_cause_nonqueue(struct int_ctx_instance *int_ctx, uint32_t cause, int16_t weight)
+{
+	struct nss_ctx_instance *nss_ctx = int_ctx->nss_ctx;
+	struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
+	struct nss_if_mem_map *if_map = mem_ctx->if_map;
+	uint16_t max_buf_size = (uint16_t) nss_ctx->max_buf_size;
+#ifdef NSS_DRV_C2C_ENABLE
+	uint32_t c2c_intr_addr1, c2c_intr_addr2;
+	int32_t i;
+#endif
+
+	nss_assert((cause == NSS_N2H_INTR_EMPTY_BUFFERS_SOS)
+			|| (cause == NSS_N2H_INTR_TX_UNBLOCKED)
+			|| cause == NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS);
+
+	/*
+	 * If this is the first time we are receiving this interrupt then
+	 * we need to initialize local state of NSS core. This helps us save an
+	 * interrupt cause bit. Hopefully, unlikley and branch prediction algorithm
+	 * of processor will prevent any excessive penalties.
+	 */
+	if (unlikely(nss_ctx->state == NSS_CORE_STATE_UNINITIALIZED)) {
+		struct nss_top_instance *nss_top = NULL;
+		nss_core_init_nss(nss_ctx, if_map);
+		nss_send_ddr_info(nss_ctx);
+
+		nss_info_always("%px: nss core %d booted successfully\n", nss_ctx, nss_ctx->id);
+		nss_top = nss_ctx->nss_top;
+
+#ifdef NSS_DRV_C2C_ENABLE
+#if (NSS_MAX_CORES > 1)
+		/*
+		 * Pass C2C addresses of already brought up cores to the recently brought
+		 * up core. No NSS core knows the state of other other cores in system so
+		 * NSS driver needs to mediate and kick start C2C between them
+		 */
+		for (i = 0; i < nss_top_main.num_nss; i++) {
+			/*
+			 * Loop through all NSS cores and send exchange C2C addresses
+			 * TODO: Current implementation utilizes the fact that there are
+			 *	only two cores in current design. And ofcourse ignore
+			 *	the core that we are trying to initialize.
+			 */
+			if (&nss_top->nss[i] != nss_ctx) {
+				/*
+				 * Block initialization routine of any other NSS cores running on other
+				 * processors. We do not want them to mess around with their initialization
+				 * state and C2C addresses while we check their state.
+				 */
+				spin_lock_bh(&nss_top->lock);
+				if (nss_top->nss[i].state == NSS_CORE_STATE_INITIALIZED) {
+					spin_unlock_bh(&nss_top->lock);
+					c2c_intr_addr1 = (uint32_t)(nss_ctx->nphys) + NSS_REGS_C2C_INTR_SET_OFFSET;
+					nss_c2c_tx_msg_cfg_map(&nss_top->nss[i], nss_ctx->c2c_start, c2c_intr_addr1);
+					c2c_intr_addr2 = (uint32_t)(nss_top->nss[i].nphys) + NSS_REGS_C2C_INTR_SET_OFFSET;
+					nss_c2c_tx_msg_cfg_map(nss_ctx, nss_top->nss[i].c2c_start, c2c_intr_addr2);
+					continue;
+				}
+				spin_unlock_bh(&nss_top->lock);
+			}
+		}
+#endif
+#endif
+	}
+
+	/*
+	 * TODO: find better mechanism to handle empty buffers
+	 */
+	if (likely(cause == NSS_N2H_INTR_EMPTY_BUFFERS_SOS)) {
+		nss_core_handle_empty_buffer_sos(nss_ctx, if_map, max_buf_size);
+	} else if (cause == NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS) {
+		nss_core_handle_paged_empty_buffer_sos(nss_ctx, if_map, max_buf_size);
+	} else if (cause == NSS_N2H_INTR_TX_UNBLOCKED) {
+		nss_core_handle_tx_unblocked(nss_ctx);
+	}
+}
+
+/*
+ * nss_core_get_prioritized_cause()
+ *	Obtain proritized cause (from multiple interrupt causes) that
+ *	must be handled by NSS driver before other causes
+ */
+static uint32_t nss_core_get_prioritized_cause(uint32_t cause, uint32_t *type, int16_t *weight)
+{
+	*type = NSS_INTR_CAUSE_INVALID;
+	*weight = 0;
+
+	/*
+	 * NOTE: This is a very simple algorithm with fixed weight and strict priority
+	 *
+	 * TODO: Modify the algorithm later with proper weights and Round Robin
+	 */
+
+	if (cause & NSS_N2H_INTR_EMPTY_BUFFERS_SOS) {
+		*type = NSS_INTR_CAUSE_NON_QUEUE;
+		*weight = NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT;
+		return NSS_N2H_INTR_EMPTY_BUFFERS_SOS;
+	}
+
+	if (cause & NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS) {
+		*type = NSS_INTR_CAUSE_NON_QUEUE;
+		*weight = NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT;
+		return NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS;
+	}
+
+	if (cause & NSS_N2H_INTR_EMPTY_BUFFER_QUEUE) {
+		*type = NSS_INTR_CAUSE_QUEUE;
+		*weight = NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT;
+		return NSS_N2H_INTR_EMPTY_BUFFER_QUEUE;
+	}
+
+	if (cause & NSS_N2H_INTR_TX_UNBLOCKED) {
+		*type = NSS_INTR_CAUSE_NON_QUEUE;
+		*weight = NSS_TX_UNBLOCKED_PROCESSING_WEIGHT;
+		return NSS_N2H_INTR_TX_UNBLOCKED;
+	}
+
+	if (cause & NSS_N2H_INTR_DATA_QUEUE_0) {
+		*type = NSS_INTR_CAUSE_QUEUE;
+		*weight = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT;
+		return NSS_N2H_INTR_DATA_QUEUE_0;
+	}
+
+	if (cause & NSS_N2H_INTR_DATA_QUEUE_1) {
+		*type = NSS_INTR_CAUSE_QUEUE;
+		*weight = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT;
+		return NSS_N2H_INTR_DATA_QUEUE_1;
+	}
+
+	if (cause & NSS_N2H_INTR_DATA_QUEUE_2) {
+		*type = NSS_INTR_CAUSE_QUEUE;
+		*weight = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT;
+		return NSS_N2H_INTR_DATA_QUEUE_2;
+	}
+
+	if (cause & NSS_N2H_INTR_DATA_QUEUE_3) {
+		*type = NSS_INTR_CAUSE_QUEUE;
+		*weight = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT;
+		return NSS_N2H_INTR_DATA_QUEUE_3;
+	}
+
+	if (cause & NSS_N2H_INTR_COREDUMP_COMPLETE) {
+		*type = NSS_INTR_CAUSE_EMERGENCY;
+		return NSS_N2H_INTR_COREDUMP_COMPLETE;
+	}
+
+	if (cause & NSS_N2H_INTR_PROFILE_DMA) {
+		*type = NSS_INTR_CAUSE_SDMA;
+		return NSS_N2H_INTR_PROFILE_DMA;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_core_handle_napi()
+ *	NAPI handler for NSS
+ */
+int nss_core_handle_napi(struct napi_struct *napi, int budget)
+{
+	int16_t processed, weight, count = 0;
+	uint32_t prio_cause, int_cause = 0, cause_type;
+	struct int_ctx_instance *int_ctx = container_of(napi, struct int_ctx_instance, napi);
+	struct nss_ctx_instance *nss_ctx = int_ctx->nss_ctx;
+
+	/*
+	 * Read cause of interrupt
+	 */
+	nss_hal_read_interrupt_cause(nss_ctx, int_ctx->shift_factor, &int_cause);
+	nss_hal_clear_interrupt_cause(nss_ctx, int_ctx->shift_factor, int_cause);
+	int_ctx->cause |= int_cause;
+
+	do {
+		while ((int_ctx->cause) && (budget)) {
+
+			/*
+			 * Obtain the cause as per priority. Also obtain the weight
+			 *
+			 * NOTE: The idea is that all causes are processed as per priority and weight
+			 * so that no single cause can overwhelm the system.
+			 */
+			prio_cause = nss_core_get_prioritized_cause(int_ctx->cause, &cause_type, &weight);
+			if (budget < weight) {
+				weight = budget;
+			}
+
+			processed = 0;
+			switch (cause_type) {
+			case NSS_INTR_CAUSE_QUEUE:
+				processed = nss_core_handle_cause_queue(int_ctx, prio_cause, weight);
+
+				count += processed;
+				budget -= processed;
+
+				/*
+				 * If #packets processed were lesser than weight then processing for this queue/cause is
+				 * complete and we can clear this interrupt cause from interrupt context structure
+				 */
+				if (processed < weight) {
+					int_ctx->cause &= ~prio_cause;
+				}
+				break;
+
+			case NSS_INTR_CAUSE_NON_QUEUE:
+				nss_core_handle_cause_nonqueue(int_ctx, prio_cause, weight);
+				int_ctx->cause &= ~prio_cause;
+				break;
+
+			case NSS_INTR_CAUSE_SDMA:
+				nss_core_handle_napi_sdma(napi, budget);
+				int_ctx->cause &= ~prio_cause;
+				break;
+
+			case NSS_INTR_CAUSE_EMERGENCY:
+				nss_info_always("NSS core %d signal COREDUMP COMPLETE %x\n",
+					nss_ctx->id, int_ctx->cause);
+				nss_fw_coredump_notify(nss_ctx, prio_cause);
+				int_ctx->cause &= ~prio_cause;
+				break;
+
+			default:
+				nss_warning("%px: Invalid cause %x received from nss", nss_ctx, int_cause);
+				nss_assert(0);
+				break;
+			}
+		}
+
+		nss_hal_read_interrupt_cause(nss_ctx, int_ctx->shift_factor, &int_cause);
+		nss_hal_clear_interrupt_cause(nss_ctx, int_ctx->shift_factor, int_cause);
+		int_ctx->cause |= int_cause;
+	} while ((int_ctx->cause) && (budget));
+
+	if (int_ctx->cause == 0) {
+		napi_complete(napi);
+
+		/*
+		 * Re-enable any further interrupt from this IRQ
+		 */
+		nss_hal_enable_interrupt(nss_ctx, int_ctx->shift_factor, NSS_HAL_SUPPORTED_INTERRUPTS);
+	}
+
+	return count;
+}
+
+/*
+ * nss_core_handle_napi_emergency()
+ *	NAPI handler for NSS crash
+ */
+int nss_core_handle_napi_emergency(struct napi_struct *napi, int budget)
+{
+	struct int_ctx_instance *int_ctx = container_of(napi, struct int_ctx_instance, napi);
+
+	nss_info_always("NSS core %d signal COREDUMP COMPLETE %x\n",
+				int_ctx->nss_ctx->id, int_ctx->cause);
+	nss_fw_coredump_notify(int_ctx->nss_ctx, 0);
+
+	return 0;
+}
+
+/*
+ * nss_core_handle_napi_sdma()
+ *	NAPI handler for NSS soft DMA
+ */
+int nss_core_handle_napi_sdma(struct napi_struct *napi, int budget)
+{
+	struct int_ctx_instance *int_ctx = container_of(napi, struct int_ctx_instance, napi);
+	struct nss_ctx_instance *nss_ctx = int_ctx->nss_ctx;
+	struct nss_profile_sdma_ctrl *ctrl = (struct nss_profile_sdma_ctrl *)nss_ctx->meminfo_ctx.sdma_ctrl;
+
+	if (ctrl->consumer[0].dispatch.fp)
+		ctrl->consumer[0].dispatch.fp(ctrl->consumer[0].arg.kp);
+
+#if !defined(NSS_HAL_IPQ806X_SUPPORT)
+	napi_complete(napi);
+	enable_irq(int_ctx->irq);
+#endif
+	return 0;
+}
+
+/*
+ * nss_core_handle_napi_queue()
+ *	NAPI handler for NSS queue cause
+ */
+int nss_core_handle_napi_queue(struct napi_struct *napi, int budget)
+{
+	int processed;
+	struct int_ctx_instance *int_ctx = container_of(napi, struct int_ctx_instance, napi);
+
+	processed = nss_core_handle_cause_queue(int_ctx, int_ctx->cause, budget);
+	if (processed < budget) {
+		napi_complete(napi);
+		enable_irq(int_ctx->irq);
+	}
+
+	return processed;
+}
+
+/*
+ * nss_core_handle_napi_non_queue()
+ *	NAPI handler for NSS non queue cause
+ */
+int nss_core_handle_napi_non_queue(struct napi_struct *napi, int budget)
+{
+	struct int_ctx_instance *int_ctx = container_of(napi, struct int_ctx_instance, napi);
+
+	nss_core_handle_cause_nonqueue(int_ctx, int_ctx->cause, 0);
+	napi_complete(napi);
+	enable_irq(int_ctx->irq);
+	return 0;
+}
+
+/*
+ * nss_core_write_one_descriptor()
+ *	Fills-up a descriptor with required fields.
+ */
+static inline void nss_core_write_one_descriptor(struct h2n_descriptor *desc,
+	uint16_t buffer_type, uint32_t buffer, uint32_t if_num,
+	nss_ptr_t opaque, uint16_t payload_off, uint16_t payload_len, uint16_t buffer_len,
+	uint32_t qos_tag, uint16_t mss, uint16_t bit_flags)
+{
+	desc->buffer_type = buffer_type;
+	desc->buffer = buffer;
+	desc->interface_num = if_num;
+	desc->opaque = opaque;
+	desc->payload_offs = payload_off;
+	desc->payload_len = payload_len;
+	desc->buffer_len = buffer_len;
+	desc->qos_tag = qos_tag;
+	desc->mss = mss;
+	desc->bit_flags = bit_flags;
+}
+
+/*
+* nss_core_send_unwind_dma()
+*	It unwinds (or unmap) DMA from descriptors
+*/
+static inline void nss_core_send_unwind_dma(struct device *dev, struct h2n_desc_if_instance *desc_if,
+	uint16_t hlos_index, int16_t count, bool is_fraglist)
+{
+	struct h2n_descriptor *desc_ring = desc_if->desc;
+	struct h2n_descriptor *desc;
+	int16_t i, mask;
+
+	mask = desc_if->size - 1;
+	for (i = 0; i < count; i++) {
+		desc = &desc_ring[hlos_index];
+		if (is_fraglist) {
+			dma_unmap_single(dev, desc->buffer, desc->buffer_len, DMA_TO_DEVICE);
+		} else {
+			dma_unmap_page(dev, desc->buffer, desc->buffer_len, DMA_TO_DEVICE);
+		}
+		hlos_index = (hlos_index - 1) & mask;
+	}
+}
+
+/*
+ * nss_core_skb_tail_offset()
+ */
+static inline uint32_t nss_core_skb_tail_offset(struct sk_buff *skb)
+{
+#ifdef NET_SKBUFF_DATA_USES_OFFSET
+	return skb->tail;
+#else
+	return skb->tail - skb->head;
+#endif
+}
+
+/*
+ * nss_core_dma_map_single()
+ */
+static inline uint32_t nss_core_dma_map_single(struct device *dev, struct sk_buff *skb)
+{
+	return (uint32_t)dma_map_single(dev, skb->head, nss_core_skb_tail_offset(skb), DMA_TO_DEVICE);
+}
+
+#if (NSS_SKB_REUSE_SUPPORT == 1)
+/*
+ * nss_core_skb_can_reuse
+ *	check if skb can be reuse
+ */
+static inline bool nss_core_skb_can_reuse(struct nss_ctx_instance *nss_ctx,
+	uint32_t if_num, struct sk_buff *nbuf, int min_skb_size)
+{
+	/*
+	 * If we have to call a destructor, we can't re-use the buffer?
+	 */
+	if (unlikely(nbuf->destructor != NULL)) {
+		return false;
+	}
+
+	/*
+	 * Check if skb has more than single user.
+	 */
+	if (unlikely(skb_shared(nbuf))) {
+		return false;
+	}
+
+#if IS_ENABLED(CONFIG_NF_CONNTRACK)
+	/*
+	 * This check is added to avoid deadlock from nf_conntrack
+	 * when ecm is trying to flush a rule.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+	if (unlikely(nbuf->nfct)) {
+		return false;
+	}
+#else
+	if (unlikely(nbuf->_nfct)) {
+		return false;
+	}
+#endif
+#endif
+
+#ifdef CONFIG_BRIDGE_NETFILTER
+	/*
+	 * This check is added to avoid deadlock from nf_bridge
+	 * when ecm is trying to flush a rule.
+	 */
+	if (unlikely(nf_bridge_info_get(nbuf))) {
+		return false;
+	}
+#endif
+
+	/*
+	 * If skb has security parameters set do not reuse
+	 */
+	if (unlikely(skb_sec_path(nbuf))) {
+		return false;
+	}
+
+	if (unlikely(irqs_disabled()))
+		return false;
+
+	if (unlikely(skb_shinfo(nbuf)->tx_flags & SKBTX_DEV_ZEROCOPY))
+		return false;
+
+	if (unlikely(skb_is_nonlinear(nbuf)))
+		return false;
+
+	if (unlikely(skb_has_frag_list(nbuf)))
+		return false;
+
+	if (unlikely(skb_shinfo(nbuf)->nr_frags))
+		return false;
+
+	if (unlikely(nbuf->fclone != SKB_FCLONE_UNAVAILABLE))
+		return false;
+
+	min_skb_size = SKB_DATA_ALIGN(min_skb_size + NET_SKB_PAD);
+	if (unlikely(skb_end_pointer(nbuf) - nbuf->head < min_skb_size))
+		return false;
+
+	if (unlikely(skb_end_pointer(nbuf) - nbuf->head >= nss_core_get_max_reuse()))
+		return false;
+
+	if (unlikely(skb_cloned(nbuf)))
+		return false;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	if (unlikely(skb_pfmemalloc(nbuf)))
+		return false;
+#endif
+
+	return true;
+}
+
+/*
+ * nss_skb_reuse - clean up an skb
+ *	Clears the skb to be reused as a receive buffer.
+ *
+ * NOTE: This function does any necessary reference count dropping, and
+ * cleans up the skbuff as if its allocated fresh.
+ */
+void nss_skb_reuse(struct sk_buff *nbuf)
+{
+	struct skb_shared_info *shinfo;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
+	u8 head_frag = nbuf->head_frag;
+#endif
+
+	/*
+	 * Reset all the necessary head state information from skb which
+	 * we found can be recycled for NSS.
+	 */
+	skb_dst_drop(nbuf);
+
+	shinfo = skb_shinfo(nbuf);
+	memset(shinfo, 0, offsetof(struct skb_shared_info, dataref));
+	atomic_set(&shinfo->dataref, 1);
+
+	memset(nbuf, 0, offsetof(struct sk_buff, tail));
+	nbuf->data = nbuf->head + NET_SKB_PAD;
+	skb_reset_tail_pointer(nbuf);
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
+	nbuf->head_frag = head_frag;
+#endif
+}
+#endif
+
+/*
+ * nss_core_send_buffer_simple_skb()
+ *	Sends one skb to NSS FW
+ */
+static inline int32_t nss_core_send_buffer_simple_skb(struct nss_ctx_instance *nss_ctx,
+	struct h2n_desc_if_instance *desc_if, uint32_t if_num,
+	struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss)
+{
+	struct h2n_descriptor *desc_ring = desc_if->desc;
+	struct h2n_descriptor *desc;
+	uint16_t bit_flags;
+	uint16_t mask;
+	uint32_t frag0phyaddr;
+
+#if (NSS_SKB_REUSE_SUPPORT == 1)
+	uint16_t sz;
+#endif
+
+	bit_flags = flags | H2N_BIT_FLAG_FIRST_SEGMENT | H2N_BIT_FLAG_LAST_SEGMENT;
+	if (likely(nbuf->ip_summed == CHECKSUM_PARTIAL)) {
+		bit_flags |= H2N_BIT_FLAG_GEN_IP_TRANSPORT_CHECKSUM;
+		bit_flags |= H2N_BIT_FLAG_GEN_IPV4_IP_CHECKSUM;
+	} else if (nbuf->ip_summed == CHECKSUM_UNNECESSARY) {
+		bit_flags |= H2N_BIT_FLAG_GEN_IP_TRANSPORT_CHECKSUM_NONE;
+	}
+
+	mask = desc_if->size - 1;
+	desc = &desc_ring[hlos_index];
+
+#if (NSS_SKB_REUSE_SUPPORT == 1)
+	/*
+	 * Check if the caller indicates that the buffer is not to be re-used (kept in the accelerator).
+	 */
+	if (unlikely(!(bit_flags & H2N_BIT_FLAG_BUFFER_REUSABLE))) {
+		goto no_reuse;
+	}
+
+	/*
+	 * Since the caller is allowing re-use, we now check if the skb meets the criteria.
+	 */
+	if (unlikely(!nss_core_skb_can_reuse(nss_ctx, if_num, nbuf, nss_ctx->max_buf_size))) {
+		goto no_reuse;
+	}
+
+	/*
+	 * We are going to do both Tx and then Rx on this buffer, unmap the Tx
+	 * and then map Rx over the entire buffer.
+	 */
+	sz = max((uint16_t)nss_core_skb_tail_offset(nbuf), (uint16_t)(nss_ctx->max_buf_size + NET_SKB_PAD));
+	frag0phyaddr = (uint32_t)dma_map_single(nss_ctx->dev, nbuf->head, sz, DMA_TO_DEVICE);
+	if (unlikely(dma_mapping_error(nss_ctx->dev, frag0phyaddr))) {
+		goto no_reuse;
+	}
+
+	/*
+	 * We are allowed to re-use the packet
+	 */
+	nss_core_write_one_descriptor(desc, buffer_type, frag0phyaddr, if_num,
+		(nss_ptr_t)nbuf, (uint16_t)(nbuf->data - nbuf->head), nbuf->len,
+		sz, (uint32_t)nbuf->priority, mss, bit_flags);
+
+	NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE);
+
+	/*
+	 * We are done using the skb fields and can reuse it now
+	 */
+	nss_skb_reuse(nbuf);
+
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_BUFFER_REUSE]);
+	return 1;
+
+no_reuse:
+#endif
+
+	bit_flags &= ~H2N_BIT_FLAG_BUFFER_REUSABLE;
+	frag0phyaddr = nss_core_dma_map_single(nss_ctx->dev, nbuf);
+	if (unlikely(dma_mapping_error(nss_ctx->dev, frag0phyaddr))) {
+		nss_warning("%px: DMA mapping failed for virtual address = %px", nss_ctx, nbuf->head);
+		return 0;
+	}
+
+	nss_core_write_one_descriptor(desc, buffer_type, frag0phyaddr, if_num,
+		(nss_ptr_t)nbuf, (uint16_t)(nbuf->data - nbuf->head), nbuf->len,
+		(uint16_t)skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags);
+
+	NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE);
+
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_SIMPLE]);
+	return 1;
+}
+
+/*
+ * nss_core_send_buffer_nr_frags()
+ *	Sends frags array (NETIF_F_SG) to NSS FW
+ *
+ * Note - Opaque is set only on LAST fragment, and DISCARD is set for the rest of segments
+ * Used to differentiate from FRAGLIST
+ */
+static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss_ctx,
+	struct h2n_desc_if_instance *desc_if, uint32_t if_num,
+	struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss)
+{
+	struct h2n_descriptor *desc_ring = desc_if->desc;
+	struct h2n_descriptor *desc;
+	const skb_frag_t *frag;
+	dma_addr_t buffer;
+	uint32_t nr_frags;
+	uint16_t bit_flags;
+	int16_t i;
+	uint16_t mask;
+
+	uint32_t frag0phyaddr = nss_core_dma_map_single(nss_ctx->dev, nbuf);
+	if (unlikely(dma_mapping_error(nss_ctx->dev, frag0phyaddr))) {
+		nss_warning("%px: DMA mapping failed for virtual address = %px", nss_ctx, nbuf->head);
+		return 0;
+	}
+
+	/*
+	 * Set the appropriate flags.
+	 */
+	bit_flags = (flags | H2N_BIT_FLAG_DISCARD);
+
+	/*
+	 * Reset the reuse flag for non-linear buffers.
+	 */
+	bit_flags &= ~H2N_BIT_FLAG_BUFFER_REUSABLE;
+	if (likely(nbuf->ip_summed == CHECKSUM_PARTIAL)) {
+		bit_flags |= H2N_BIT_FLAG_GEN_IP_TRANSPORT_CHECKSUM;
+		bit_flags |= H2N_BIT_FLAG_GEN_IPV4_IP_CHECKSUM;
+	}
+
+	mask = desc_if->size - 1;
+	desc = &desc_ring[hlos_index];
+
+	/*
+	 * First fragment/descriptor is special
+	 */
+	nss_core_write_one_descriptor(desc, buffer_type, frag0phyaddr, if_num,
+		(nss_ptr_t)NULL, nbuf->data - nbuf->head, nbuf->len - nbuf->data_len,
+		skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags | H2N_BIT_FLAG_FIRST_SEGMENT);
+
+	NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE);
+
+	/*
+	 * Now handle rest of the fragments.
+	 */
+	nr_frags = skb_shinfo(nbuf)->nr_frags;
+	BUG_ON(nr_frags > MAX_SKB_FRAGS);
+	for (i = 0; i < nr_frags; i++) {
+		frag = &skb_shinfo(nbuf)->frags[i];
+
+		buffer = skb_frag_dma_map(nss_ctx->dev, frag, 0, skb_frag_size(frag), DMA_TO_DEVICE);
+		if (unlikely(dma_mapping_error(nss_ctx->dev, buffer))) {
+			nss_warning("%px: DMA mapping failed for fragment", nss_ctx);
+			nss_core_send_unwind_dma(nss_ctx->dev, desc_if, hlos_index, i + 1, false);
+			return -(i + 1);
+		}
+
+		hlos_index = (hlos_index + 1) & (mask);
+		desc = &(desc_if->desc[hlos_index]);
+
+		nss_core_write_one_descriptor(desc, buffer_type, buffer, if_num,
+			(nss_ptr_t)NULL, 0, skb_frag_size(frag), skb_frag_size(frag),
+			nbuf->priority, mss, bit_flags);
+
+		NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE);
+	}
+
+	/*
+	 * Update bit flag for last descriptor.
+	 * The discard flag shall be set for all fragments except the
+	 * the last one.The NSS returns the last fragment to HLOS
+	 * after the packet processing is done.We do need to send the
+	 * packet buffer address (skb) in the descriptor of last segment
+	 * when the decriptor returns from NSS the HLOS uses the
+	 * opaque field to free the memory allocated.
+	 */
+	desc->bit_flags |= H2N_BIT_FLAG_LAST_SEGMENT;
+	desc->bit_flags &= ~(H2N_BIT_FLAG_DISCARD);
+	desc->opaque = (nss_ptr_t)nbuf;
+
+	NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE);
+
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_NR_FRAGS]);
+	return i+1;
+}
+
+/*
+ * nss_core_send_buffer_fraglist()
+ *	Sends fraglist (NETIF_F_FRAGLIST) to NSS FW
+ *
+ * Note - Opaque will be set on all fragments, and DISCARD is set for the rest of segments
+ * Used to differentiate from FRAGS
+ */
+static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss_ctx,
+	struct h2n_desc_if_instance *desc_if, uint32_t if_num,
+	struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss)
+{
+	struct h2n_descriptor *desc_ring = desc_if->desc;
+	struct h2n_descriptor *desc;
+	dma_addr_t buffer;
+	uint16_t mask;
+	struct sk_buff *iter;
+	uint16_t bit_flags;
+	int16_t i;
+
+	uint32_t frag0phyaddr = nss_core_dma_map_single(nss_ctx->dev, nbuf);
+	if (unlikely(dma_mapping_error(nss_ctx->dev, frag0phyaddr))) {
+		nss_warning("%px: DMA mapping failed for virtual address = %px", nss_ctx, nbuf->head);
+		return 0;
+	}
+
+	/*
+	 * Copy and Set bit flags
+	 */
+	bit_flags = flags;
+
+	/*
+	 * Reset the reuse flag for non-linear buffers.
+	 */
+	bit_flags &= ~H2N_BIT_FLAG_BUFFER_REUSABLE;
+	if (likely(nbuf->ip_summed == CHECKSUM_PARTIAL)) {
+		bit_flags |= H2N_BIT_FLAG_GEN_IP_TRANSPORT_CHECKSUM;
+		bit_flags |= H2N_BIT_FLAG_GEN_IPV4_IP_CHECKSUM;
+	}
+
+	mask = desc_if->size - 1;
+	desc = &desc_ring[hlos_index];
+
+	/*
+	 * First fragment/descriptor is special. Will hold the Opaque
+	 */
+	nss_core_write_one_descriptor(desc, buffer_type, frag0phyaddr, if_num,
+		(nss_ptr_t)nbuf, nbuf->data - nbuf->head, nbuf->len - nbuf->data_len,
+		skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags | H2N_BIT_FLAG_FIRST_SEGMENT);
+
+	NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE);
+
+	/*
+	 * Walk the frag_list in nbuf
+	 */
+	i = 0;
+	skb_walk_frags(nbuf, iter) {
+		uint32_t nr_frags;
+
+		buffer = nss_core_dma_map_single(nss_ctx->dev, iter);
+		if (unlikely(dma_mapping_error(nss_ctx->dev, buffer))) {
+			nss_warning("%px: DMA mapping failed for virtual address = %px", nss_ctx, iter->head);
+			nss_core_send_unwind_dma(nss_ctx->dev, desc_if, hlos_index, i + 1, true);
+			return -(i+1);
+		}
+
+		/*
+		 * We currently don't support frags[] array inside a
+		 * fraglist.
+		 */
+		nr_frags = skb_shinfo(iter)->nr_frags;
+		if (unlikely(nr_frags > 0)) {
+			nss_warning("%px: fraglist with page data are not supported: %px\n", nss_ctx, iter);
+			nss_core_send_unwind_dma(nss_ctx->dev, desc_if, hlos_index, i + 1, true);
+			return -(i+1);
+		}
+
+		/*
+		 * Update index.
+		 */
+		hlos_index = (hlos_index + 1) & (mask);
+		desc = &(desc_if->desc[hlos_index]);
+
+#ifdef CONFIG_DEBUG_KMEMLEAK
+		/*
+		 * We are holding this skb in NSS FW, let kmemleak know about it.
+		 *
+		 * If the skb is a fast clone (FCLONE), then nbuf is pointing to the
+		 * cloned skb which is at the middle of the allocated block and kmemleak API
+		 * would backtrace if passed such a pointer. We will need to get to the original
+		 * skb pointer which kmemleak is aware of.
+		 */
+		if (iter->fclone == SKB_FCLONE_CLONE) {
+			kmemleak_not_leak(iter - 1);
+		} else {
+			kmemleak_not_leak(iter);
+		}
+#endif
+
+		nss_core_write_one_descriptor(desc, buffer_type, buffer, if_num,
+			(nss_ptr_t)iter, iter->data - iter->head, iter->len - iter->data_len,
+			skb_end_offset(iter), iter->priority, mss, bit_flags);
+
+		NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE);
+
+		i++;
+	}
+
+	/*
+	 * We need to defrag the frag_list, otherwise, if this structure is
+	 * received back we don't know how we can reconstruct the frag_list.
+	 * Therefore, we are clearing skb_has_fraglist. This is safe because all
+	 * information about the segments are already sent to NSS-FW.
+	 * So, the information will be in the NSS-FW.
+	 */
+	skb_shinfo(nbuf)->frag_list = NULL;
+	NSS_PKT_STATS_ADD(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_NSS_SKB_COUNT], i);
+
+	/*
+	 * Update bit flag for last descriptor.
+	 */
+	desc->bit_flags |= H2N_BIT_FLAG_LAST_SEGMENT;
+	NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE);
+
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_FRAGLIST]);
+	return i+1;
+}
+
+/*
+ * nss_core_init_handlers()
+ *	Initialize the handlers for all interfaces associated with core
+ */
+void nss_core_init_handlers(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_rx_cb_list *cb_list = nss_ctx->nss_rx_interface_handlers;
+	memset(cb_list, 0, sizeof(*cb_list) * NSS_MAX_NET_INTERFACES);
+}
+
+/*
+ * nss_core_send_buffer()
+ *	Send network buffer to NSS
+ */
+int32_t nss_core_send_buffer(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+					struct sk_buff *nbuf, uint16_t qid,
+					uint8_t buffer_type, uint16_t flags)
+{
+	int16_t count, hlos_index, nss_index, size, mask;
+	uint32_t segments;
+	struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[qid];
+	struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring;
+	struct h2n_descriptor *desc_ring;
+	struct h2n_descriptor *desc;
+	struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
+	struct nss_if_mem_map *if_map = mem_ctx->if_map;
+	uint16_t mss = 0;
+	bool is_bounce = ((buffer_type == H2N_BUFFER_SHAPER_BOUNCE_INTERFACE) || (buffer_type == H2N_BUFFER_SHAPER_BOUNCE_BRIDGE));
+
+	desc_ring = desc_if->desc;
+	size = desc_if->size;
+	mask = size - 1;
+
+	/*
+	 * If nbuf does not have fraglist, then update nr_frags
+	 * from frags[] array. Otherwise walk the frag_list.
+	 */
+	if (!skb_has_frag_list(nbuf)) {
+		segments = skb_shinfo(nbuf)->nr_frags;
+		BUG_ON(segments > MAX_SKB_FRAGS);
+	} else {
+		struct sk_buff *iter;
+		segments = 0;
+		skb_walk_frags(nbuf, iter) {
+			segments++;
+		}
+
+		/*
+		 * Check that segments do not overflow the number of descriptors
+		 */
+		if (unlikely(segments > size)) {
+			nss_warning("%px: Unable to fit in skb - %d segments in our descriptors", nss_ctx, segments);
+			return NSS_CORE_STATUS_FAILURE;
+		}
+	}
+
+	/*
+	 * Take a lock for queue
+	 */
+	spin_lock_bh(&h2n_desc_ring->lock);
+
+	/*
+	 * We need to work out if there's sufficent space in our transmit descriptor
+	 * ring to place all the segments of a nbuf.
+	 */
+	NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE);
+	NSS_CORE_DSB();
+	nss_index = if_map->h2n_nss_index[qid];
+
+	hlos_index = h2n_desc_ring->hlos_index;
+
+	count = ((nss_index - hlos_index - 1) + size) & (mask);
+
+	if (unlikely(count < (segments + 1))) {
+		/*
+		 * NOTE: tx_q_full_cnt and TX_STOPPED flags will be used
+		 *	when we will add support for DESC Q congestion management
+		 *	in future
+		 */
+		h2n_desc_ring->tx_q_full_cnt++;
+		h2n_desc_ring->flags |= NSS_H2N_DESC_RING_FLAGS_TX_STOPPED;
+		spin_unlock_bh(&h2n_desc_ring->lock);
+		nss_warning("%px: Data/Command Queue full reached", nss_ctx);
+
+#if (NSS_PKT_STATS_ENABLED == 1)
+		if (nss_ctx->id == NSS_CORE_0) {
+			NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_QUEUE_FULL_0]);
+		} else if (nss_ctx->id == NSS_CORE_1) {
+			NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_QUEUE_FULL_1]);
+		} else {
+			nss_warning("%px: Invalid nss core: %d\n", nss_ctx, nss_ctx->id);
+		}
+#endif
+
+		/*
+		 * Enable de-congestion interrupt from NSS
+		 */
+		nss_hal_enable_interrupt(nss_ctx, nss_ctx->int_ctx[0].shift_factor, NSS_N2H_INTR_TX_UNBLOCKED);
+
+		return NSS_CORE_STATUS_FAILURE_QUEUE;
+	}
+
+	desc = &desc_ring[hlos_index];
+
+	/*
+	 * Check if segmentation enabled.
+	 * Configure descriptor bit flags accordingly
+	 */
+
+	/*
+	 * When CONFIG_HIGHMEM is enabled OS is giving a single big chunk buffer without
+	 * any scattered frames.
+	 *
+	 * NOTE: We dont have to perform segmentation offload for packets that are being
+	 * bounced. These packets WILL return to the HLOS for freeing or further processing.
+	 * They will NOT be transmitted by the NSS.
+	 */
+	if (skb_is_gso(nbuf) && !is_bounce) {
+		mss = skb_shinfo(nbuf)->gso_size;
+		flags |= H2N_BIT_FLAG_SEGMENTATION_ENABLE;
+	}
+
+	/*
+	 * WARNING! : The following "is_bounce" check has a potential to cause corruption
+	 * if things change in the NSS. This check allows fragmented packets to be sent down
+	 * with incomplete payload information since NSS does not care about the payload content
+	 * when packets are bounced for shaping. If it starts caring in future, then this code
+	 * will have to change.
+	 *
+	 * WHY WE ARE DOING THIS - Skipping S/G processing helps with performance.
+	 *
+	 */
+	count = 0;
+	if (likely((segments == 0) || is_bounce)) {
+		count = nss_core_send_buffer_simple_skb(nss_ctx, desc_if, if_num,
+			nbuf, hlos_index, flags, buffer_type, mss);
+	} else if (skb_has_frag_list(nbuf)) {
+		count = nss_core_send_buffer_fraglist(nss_ctx, desc_if, if_num,
+			nbuf, hlos_index, flags, buffer_type, mss);
+	} else {
+		count = nss_core_send_buffer_nr_frags(nss_ctx, desc_if, if_num,
+			nbuf, hlos_index, flags, buffer_type, mss);
+	}
+
+	if (unlikely(count <= 0)) {
+		/*
+		 * We failed and hence we need to unmap dma regions
+		 */
+		nss_warning("%px: failed to map DMA regions:%d", nss_ctx, -count);
+		spin_unlock_bh(&h2n_desc_ring->lock);
+		return NSS_CORE_STATUS_FAILURE;
+	}
+
+	/*
+	 * Sync to ensure all flushing of the descriptors are complete
+	 */
+	NSS_CORE_DSB();
+
+	/*
+	 * Update our host index so the NSS sees we've written a new descriptor.
+	 */
+	hlos_index = (hlos_index + count) & mask;
+	h2n_desc_ring->hlos_index = hlos_index;
+	if_map->h2n_hlos_index[qid] = hlos_index;
+
+	NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[qid], sizeof(uint32_t), DMA_TO_DEVICE);
+	NSS_CORE_DSB();
+
+#ifdef CONFIG_DEBUG_KMEMLEAK
+	/*
+	 * We are holding this skb in NSS FW, let kmemleak know about it.
+	 *
+	 * If the skb is a fast clone (FCLONE), then nbuf is pointing to the
+	 * cloned skb which is at the middle of the allocated block and kmemleak API
+	 * would backtrace if passed such a pointer. We will need to get to the original
+	 * skb pointer which kmemleak is aware of.
+	 */
+	if (nbuf->fclone == SKB_FCLONE_CLONE) {
+		kmemleak_not_leak(nbuf - 1);
+	} else {
+		kmemleak_not_leak(nbuf);
+	}
+#endif
+
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_NSS_SKB_COUNT]);
+
+	spin_unlock_bh(&h2n_desc_ring->lock);
+	return NSS_CORE_STATUS_SUCCESS;
+}
+
+/*
+ * nss_core_send_cmd()
+ *	Send command message to NSS
+ */
+int32_t nss_core_send_cmd(struct nss_ctx_instance *nss_ctx, void *msg, int size, int buf_size)
+{
+	struct nss_cmn_msg *ncm = (struct nss_cmn_msg *)msg;
+	int32_t status;
+	struct sk_buff *nbuf;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	if (unlikely(nss_ctx->state != NSS_CORE_STATE_INITIALIZED)) {
+		nss_warning("%px: interface: %d type: %d message dropped as core not ready\n", nss_ctx, ncm->interface, ncm->type);
+		return NSS_TX_FAILURE_NOT_READY;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > size) {
+		nss_warning("%px: interface: %d type: %d message length %d is invalid, size = %d\n",
+					nss_ctx, ncm->interface, ncm->type, nss_cmn_get_msg_len(ncm), size);
+		return NSS_TX_FAILURE_TOO_LARGE;
+	}
+
+	if (buf_size > PAGE_SIZE) {
+		nss_warning("%px: interface: %d type: %d tx request size too large: %u",
+					nss_ctx, ncm->interface, ncm->type, buf_size);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	nbuf = dev_alloc_skb(buf_size);
+	if (unlikely(!nbuf)) {
+		NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_NBUF_ALLOC_FAILS]);
+		nss_warning("%px: interface: %d type: %d msg dropped as command allocation failed", nss_ctx, ncm->interface, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	memcpy(skb_put(nbuf, buf_size), (void *)ncm, size);
+
+	status = nss_core_send_buffer(nss_ctx, 0, nbuf, NSS_IF_H2N_CMD_QUEUE, H2N_BUFFER_CTRL, H2N_BIT_FLAG_BUFFER_REUSABLE);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		dev_kfree_skb_any(nbuf);
+		NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_CMD_QUEUE_FULL]);
+		nss_warning("%px: interface: %d type: %d unable to enqueue message status %d\n", nss_ctx, ncm->interface, ncm->type, status);
+		return status;
+	}
+
+	nss_hal_send_interrupt(nss_ctx, NSS_H2N_INTR_DATA_COMMAND_QUEUE);
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_CMD_REQ]);
+	return status;
+}
+
+/*
+ * nss_core_send_packet()
+ *	Send data packet to NSS
+ */
+int32_t nss_core_send_packet(struct nss_ctx_instance *nss_ctx, struct sk_buff *nbuf, uint32_t if_num, uint32_t flag)
+{
+	int32_t status;
+	int32_t queue_id = 0;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	if (unlikely(nss_ctx->state != NSS_CORE_STATE_INITIALIZED)) {
+		nss_warning("%px: interface: %d packet dropped as core not ready\n", nss_ctx, if_num);
+		return NSS_TX_FAILURE_NOT_READY;
+	}
+
+#ifdef NSS_MULTI_H2N_DATA_RING_SUPPORT
+	queue_id = (skb_get_queue_mapping(nbuf) & (NSS_HOST_CORES - 1)) << 1;
+	if (nbuf->priority) {
+		queue_id++;
+	}
+#endif
+	status = nss_core_send_buffer(nss_ctx, if_num, nbuf, NSS_IF_H2N_DATA_QUEUE + queue_id, H2N_BUFFER_PACKET, flag);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: interface: %d unable to enqueue packet status %d\n", nss_ctx, if_num, status);
+		return status;
+	}
+
+	nss_hal_send_interrupt(nss_ctx, NSS_H2N_INTR_DATA_COMMAND_QUEUE);
+
+#ifdef NSS_MULTI_H2N_DATA_RING_SUPPORT
+	/*
+	 * Count per queue and aggregate packet count
+	 */
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_PACKET_QUEUE_0 + queue_id]);
+#endif
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_PACKET]);
+	return status;
+}
+
+/*
+ * nss_core_ddr_info()
+ *	Getting DDR information for NSS core
+ */
+uint32_t nss_core_ddr_info(struct nss_mmu_ddr_info *mmu)
+{
+	nss_get_ddr_info(mmu, "memory");
+	return nss_soc_mem_info();
+}
diff --git a/qca-nss-drv/nss_core.h b/qca-nss-drv/nss_core.h
new file mode 100644
index 0000000..d7f62fe
--- /dev/null
+++ b/qca-nss-drv/nss_core.h
@@ -0,0 +1,1038 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * na_core.h
+ *	NSS driver core header file.
+ */
+
+#ifndef __NSS_CORE_H
+#define __NSS_CORE_H
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+#include <linux/debugfs.h>
+#include <linux/workqueue.h>
+#include <asm/cacheflush.h>
+
+#include <nss_api_if.h>
+#include "nss_phys_if.h"
+#include "nss_hlos_if.h"
+#include "nss_oam.h"
+#include "nss_data_plane.h"
+#include "nss_gmac_stats.h"
+#include "nss_meminfo.h"
+#include "nss_stats.h"
+
+/*
+ * NSS debug macros
+ */
+#define nss_info_always(s, ...) pr_alert(s, ##__VA_ARGS__)
+
+#if (NSS_DEBUG_LEVEL < 1)
+#define nss_assert(fmt, args...)
+#else
+#define nss_assert(c) if (!(c)) { BUG_ON(!(c)); }
+#endif
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define nss_warning(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_info(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define nss_trace(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#if (NSS_DEBUG_LEVEL < 2)
+#define nss_warning(s, ...)
+#else
+#define nss_warning(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_DEBUG_LEVEL < 3)
+#define nss_info(s, ...)
+#else
+#define nss_info(s, ...) pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (NSS_DEBUG_LEVEL < 4)
+#define nss_trace(s, ...)
+#else
+#define nss_trace(s, ...) pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif
+
+#if (NSS_PKT_STATS_ENABLED == 1)
+#define NSS_PKT_STATS_INC(x) nss_pkt_stats_inc((x))
+#define NSS_PKT_STATS_DEC(x) nss_pkt_stats_dec((x))
+#define NSS_PKT_STATS_ADD(x, i) nss_pkt_stats_add((x), (i))
+#define NSS_PKT_STATS_SUB(x, i) nss_pkt_stats_sub((x), (i))
+#define NSS_PKT_STATS_READ(x) nss_pkt_stats_read(x)
+#else
+#define NSS_PKT_STATS_INC(x)
+#define NSS_PKT_STATS_DEC(x)
+#define NSS_PKT_STATS_ADD(x, i)
+#define NSS_PKT_STATS_SUB(x, i)
+#define NSS_PKT_STATS_READ(x)
+#endif
+
+/*
+ * Cache operation
+ */
+#define NSS_CORE_DSB() dsb(sy)
+#define NSS_CORE_DMA_CACHE_MAINT(start, size, dir) nss_core_dma_cache_maint(start, size, dir)
+
+/*
+ * nss_core_dma_cache_maint()
+ *	Perform the appropriate cache op based on direction
+ */
+static inline void nss_core_dma_cache_maint(void *start, uint32_t size, int direction)
+{
+	switch (direction) {
+	case DMA_FROM_DEVICE:/* invalidate only */
+		dmac_inv_range(start, start + size);
+		break;
+	case DMA_TO_DEVICE:/* writeback only */
+		dmac_clean_range(start, start + size);
+		break;
+	case DMA_BIDIRECTIONAL:/* writeback and invalidate */
+		dmac_flush_range(start, start + size);
+		break;
+	default:
+		BUG();
+	}
+}
+
+#define NSS_DEVICE_IF_START NSS_PHYSICAL_IF_START
+
+#define NSS_IS_IF_TYPE(type, if_num) ((if_num >= NSS_##type##_IF_START) && (if_num < (NSS_##type##_IF_START + NSS_MAX_##type##_INTERFACES)))
+
+/*
+ * Default payload size for NSS buffers
+ */
+#define NSS_NBUF_PAYLOAD_SIZE NSS_EMPTY_BUFFER_SIZE
+#define NSS_NBUF_PAD_EXTRA 256
+#define NSS_NBUF_ETH_EXTRA 192
+
+/*
+ * N2H/H2N Queue IDs
+ */
+#define NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE 0
+#define NSS_IF_N2H_DATA_QUEUE_0 1
+#define NSS_IF_N2H_DATA_QUEUE_1 2
+#define NSS_IF_N2H_DATA_QUEUE_2 3
+#define NSS_IF_N2H_DATA_QUEUE_3 4
+
+#define NSS_IF_H2N_EMPTY_BUFFER_QUEUE 0
+#define NSS_IF_H2N_CMD_QUEUE 1
+#define NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE 2
+#define NSS_IF_H2N_DATA_QUEUE 3
+
+/*
+ * NSS Interrupt Causes
+ */
+#define NSS_INTR_CAUSE_INVALID 0
+#define NSS_INTR_CAUSE_QUEUE 1
+#define NSS_INTR_CAUSE_NON_QUEUE 2
+#define NSS_INTR_CAUSE_EMERGENCY 3
+#define NSS_INTR_CAUSE_SDMA 4
+
+/*
+ * NSS Core Status
+ */
+#define NSS_CORE_STATUS_SUCCESS 0
+#define NSS_CORE_STATUS_FAILURE 1
+#define NSS_CORE_STATUS_FAILURE_QUEUE 2
+
+/*
+ * NSS context magic
+ */
+#define NSS_CTX_MAGIC 0xDEDEDEDE
+
+/*
+ * Number of n2h descriptor rings
+ */
+#define NSS_N2H_DESC_RING_NUM 15
+#define NSS_H2N_DESC_RING_NUM 16
+
+/*
+ * NSS maximum data queue per core
+ */
+#define NSS_MAX_DATA_QUEUE 4
+
+/*
+ * NSS maximum IRQ per interrupt instance/core
+ */
+#if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT)
+#define NSS_MAX_IRQ_PER_INSTANCE 6
+#define NSS_MAX_IRQ_PER_CORE 10	/* must match with NSS_HAL_N2H_INTR_PURPOSE_MAX */
+#elif defined(NSS_HAL_IPQ50XX_SUPPORT)
+#define NSS_MAX_IRQ_PER_CORE 8
+#else
+#define NSS_MAX_IRQ_PER_INSTANCE 1
+#define NSS_MAX_IRQ_PER_CORE 2
+#endif
+
+/*
+ * NSS maximum clients
+ */
+#define NSS_MAX_CLIENTS 12
+
+/*
+ * Maximum number of service code NSS supports
+ */
+#define NSS_MAX_SERVICE_CODE 256
+
+/*
+ * Interrupt cause processing weights
+ */
+#define NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT 64
+#define NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT 64
+#define NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT 64
+#define NSS_TX_UNBLOCKED_PROCESSING_WEIGHT 1
+
+/*
+ * Cache line size of the NSS.
+ */
+#define NSS_CACHE_LINE_SIZE 32
+
+/*
+ * Statistics struct
+ *
+ * INFO: These numbers are based on previous generation chip
+ *	These may change in future
+ */
+
+/*
+ * NSS Frequency Defines and Values
+ *
+ * INFO: The LOW and MAX value together describe the "performance" band that we should operate the frequency at.
+ *
+ */
+#define NSS_FREQ_SCALE_NA	0xFAADFAAD	/* Frequency scale not supported */
+#define NSS_FREQ_NA		0x0		/* Instructions Per ms Min */
+
+#define NSS_FREQ_110		110000000	/* Frequency in hz */
+#define NSS_FREQ_110_MIN	0x03000		/* Instructions Per ms Min */
+#define NSS_FREQ_110_MAX	0x07000		/* Instructions Per ms Max */
+
+#define NSS_FREQ_187		187200000	/* Frequency in hz */
+#if defined(NSS_HAL_IPQ60XX_SUPPORT)
+#define NSS_FREQ_187_MIN	0x03000		/* Instructions Per ms Min */
+#define NSS_FREQ_187_MAX	0x10000		/* Instructions Per ms Max */
+#else
+#define NSS_FREQ_187_MIN	0x03000		/* Instructions Per ms Min */
+#define NSS_FREQ_187_MAX	0x07000		/* Instructions Per ms Max */
+#endif
+
+#define NSS_FREQ_275		275000000	/* Frequency in hz */
+#define NSS_FREQ_275_MIN	0x03000		/* Instructions Per ms Min */
+#define NSS_FREQ_275_MAX	0x07000		/* Instructions Per ms Max */
+
+#define NSS_FREQ_550		550000000	/* Frequency in hz */
+#define NSS_FREQ_550_MIN	0x07000		/* Instructions Per ms Min */
+#define NSS_FREQ_550_MAX	0x08000		/* Instructions Per ms Max */
+
+#define NSS_FREQ_600		600000000	/* Frequency in hz */
+#define NSS_FREQ_600_MIN	0x07000		/* Instructions Per ms Min */
+#define NSS_FREQ_600_MAX	0x08000		/* Instructions Per ms Max */
+
+#define NSS_FREQ_733		733000000	/* Frequency in hz */
+#define NSS_FREQ_733_MIN	0x07000		/* Instructions Per ms Min */
+#define NSS_FREQ_733_MAX	0x25000		/* Instructions Per ms Max */
+
+#define NSS_FREQ_748		748800000	/* Frequency in hz */
+#if defined(NSS_HAL_IPQ60XX_SUPPORT)
+#define NSS_FREQ_748_MIN	0x10000		/* Instructions Per ms Min */
+#define NSS_FREQ_748_MAX	0x18000		/* Instructions Per ms Max */
+#else
+#define NSS_FREQ_748_MIN	0x07000		/* Instructions Per ms Min */
+#define NSS_FREQ_748_MAX	0x14000		/* Instructions Per ms Max */
+#endif
+
+#define NSS_FREQ_800		800000000	/* Frequency in hz */
+#define NSS_FREQ_800_MIN	0x07000		/* Instructions Per ms Min */
+#define NSS_FREQ_800_MAX	0x25000		/* Instructions Per ms Max */
+
+#define NSS_FREQ_850		850000000	/* Frequency in hz */
+#define NSS_FREQ_850_MIN	0x07000		/* Instructions Per ms Min */
+#define NSS_FREQ_850_MAX	0x0c000		/* Instructions Per ms Max */
+
+#define NSS_FREQ_1000		1000000000	/* Frequency in hz */
+#define NSS_FREQ_1000_MIN	0x0c000		/* Instructions Per ms Min */
+#define NSS_FREQ_1000_MAX	0x25000		/* Instructions Per ms Max */
+
+#define NSS_FREQ_1497		1497600000	/* Frequency in hz */
+#if defined(NSS_HAL_IPQ60XX_SUPPORT)
+#define NSS_FREQ_1497_MIN	0x18000		/* Instructions Per ms Min */
+#define NSS_FREQ_1497_MAX	0x25000		/* Instructions Per ms Max */
+#else
+#define NSS_FREQ_1497_MIN	0x14000		/* Instructions Per ms Min */
+#define NSS_FREQ_1497_MAX	0x25000		/* Instructions Per ms Max */
+#endif
+
+#define NSS_FREQ_1689		1689600000	/* Frequency in hz */
+#define NSS_FREQ_1689_MIN	0x14000		/* Instructions Per ms Min */
+#define NSS_FREQ_1689_MAX	0x25000		/* Instructions Per ms Max */
+
+#if (NSS_DT_SUPPORT == 1)
+#define NSSTCM_FREQ		400000000	/* NSS TCM Frequency in Hz */
+
+/*
+ * NSS Clock names
+ */
+#define NSS_CORE_CLK		"nss-core-clk"
+#define NSS_TCM_SRC_CLK		"nss-tcm-src"
+#define NSS_TCM_CLK		"nss-tcm-clk"
+#define NSS_FABRIC0_CLK		"nss-fab0-clk"
+#define NSS_FABRIC1_CLK		"nss-fab1-clk"
+
+/*
+ * NSS Fabric speeds
+ */
+#define NSS_FABRIC0_TURBO	533000000
+#define NSS_FABRIC1_TURBO	266500000
+#define NSS_FABRIC0_NOMINAL	400000000
+#define NSS_FABRIC1_NOMINAL	200000000
+#define NSS_FABRIC0_IDLE	133333000
+#define NSS_FABRIC1_IDLE	133333000
+#endif
+
+/* Default NSS packet queue limit. */
+#define NSS_DEFAULT_QUEUE_LIMIT 256
+
+/*
+ * Gives us important data from NSS platform data
+ */
+extern struct nss_top_instance nss_top_main;
+
+/*
+ * NSS core state
+ */
+enum nss_core_state {
+	NSS_CORE_STATE_UNINITIALIZED = 0,
+	NSS_CORE_STATE_INITIALIZED,
+	/*
+	 * in following cases, only interrupts work
+	 */
+	NSS_CORE_STATE_FW_DEAD = 2,
+	NSS_CORE_STATE_FW_DUMP = 4,
+	NSS_CORE_STATE_PANIC = 8,
+};
+
+/*
+ * Forward declarations
+ */
+struct nss_top_instance;
+struct nss_ctx_instance;
+struct int_ctx_instance;
+struct net_dev_priv_instance;
+
+/*
+ * Network device private data instance
+ */
+struct netdev_priv_instance {
+	struct int_ctx_instance *int_ctx;	/* Back pointer to interrupt context */
+};
+
+/*
+ * Interrupt context instance (one per queue per NSS core)
+ */
+struct int_ctx_instance {
+	struct nss_ctx_instance *nss_ctx;
+					/* Back pointer to NSS context of core that
+					   owns this interrupt */
+	uint32_t irq;			/* HLOS IRQ numbers bind to this instance */
+	uint32_t shift_factor;	/* Shift factor for this IRQ queue */
+	uint32_t cause;			/* Interrupt cause carried forward to BH */
+	struct napi_struct napi;/* NAPI handler */
+};
+
+/*
+ * N2H descriptor ring information
+ */
+struct hlos_n2h_desc_ring {
+	struct n2h_desc_if_instance desc_ring;
+					/* Descriptor ring */
+	uint32_t hlos_index;		/* Current HLOS index for this ring */
+	struct sk_buff *head;		/* First segment of an skb fraglist */
+	struct sk_buff *tail;		/* Last segment received of an skb fraglist */
+	struct sk_buff *jumbo_start;	/* First segment of an skb with frags[] */
+};
+
+/*
+ * H2N descriptor ring information
+ */
+struct hlos_h2n_desc_rings {
+	struct h2n_desc_if_instance desc_ring;	/* Descriptor ring */
+	uint32_t hlos_index;
+	spinlock_t lock;			/* Lock to save from simultaneous access */
+	uint32_t flags;				/* Flags */
+	uint64_t tx_q_full_cnt;			/* Descriptor queue full count */
+};
+
+#define NSS_H2N_DESC_RING_FLAGS_TX_STOPPED 0x1	/* Tx has been stopped for this queue */
+
+/*
+ * struct nss_shaper_bounce_registrant
+ *	Registrant detail for shaper bounce operations
+ */
+struct nss_shaper_bounce_registrant {
+	nss_shaper_bounced_callback_t bounced_callback;		/* Invoked for each shaper bounced packet returned from the NSS */
+	void *app_data;						/* Argument given to the callback */
+	struct module *owner;					/* Owning module of the callback + arg */
+	bool registered;
+	volatile bool callback_active;				/* true when the bounce callback is being called */
+};
+
+/*
+ * CB function declarations
+ */
+typedef void (*nss_core_rx_callback_t)(struct nss_ctx_instance *, struct nss_cmn_msg *, void *);
+
+/*
+ * NSS Rx per interface callback structure
+ */
+struct nss_rx_cb_list {
+	nss_if_rx_msg_callback_t msg_cb;
+	nss_core_rx_callback_t cb;
+	void *app_data;
+};
+
+/*
+ * NSS core <-> subsystem data plane registration related paramaters.
+ *	This struct is filled with if_register/data_plane register APIs and
+ *	retrieved when handling a data packet/skb destined to that subsystem.
+ */
+struct nss_subsystem_dataplane_register {
+	nss_phys_if_rx_callback_t cb;	/* callback to be invoked */
+	nss_phys_if_xmit_callback_t xmit_cb;
+					/* Callback to be invoked for sending the packets to the transmit path */
+	nss_phys_if_rx_ext_data_callback_t ext_cb;
+					/* Extended data plane callback to be invoked.
+					   This is needed if driver needs extended handling
+					   of data packet before giving to stack */
+	void *app_data;			/* additional info passed during callback(for future use) */
+	struct net_device *ndev;	/* Netdevice associated with the interface */
+	uint32_t features;		/* skb types supported by this subsystem */
+	uint32_t type;			/* Indicates the type of this data plane */
+};
+
+/*
+ * Holds statistics for every worker thread on a core
+ */
+struct nss_worker_thread_stats {
+	struct nss_project_irq_stats *irq_stats;
+};
+
+/*
+ * NSS context instance (one per NSS core)
+ */
+struct nss_ctx_instance {
+	struct nss_top_instance *nss_top;
+					/* Back pointer to NSS Top */
+	struct device *dev;		/* Pointer to the original device from probe */
+	struct net_device napi_ndev;    /* Dummy_netdev for NAPI */
+	uint32_t id;			/* Core ID for this instance */
+	void __iomem *nmap;		/* Pointer to NSS CSM registers */
+	void __iomem *vmap;		/* Virt mem pointer to virtual register map */
+	void __iomem *qgic_map;		/* Virt mem pointer to QGIC register */
+	uint32_t nphys;			/* Phys mem pointer to CSM register map */
+	uint32_t vphys;			/* Phys mem pointer to virtual register map */
+	uint32_t qgic_phys;		/* Phys mem pointer to QGIC register map */
+	uint32_t load;			/* Load address for this core */
+	struct nss_meminfo_ctx meminfo_ctx;	/* Meminfo context */
+	enum nss_core_state state;	/* State of NSS core */
+	uint32_t c2c_start;		/* C2C start address */
+	uint32_t num_irq;                /* IRQ numbers per queue */
+	struct int_ctx_instance int_ctx[NSS_MAX_IRQ_PER_CORE];
+					/* Interrupt context instances for each queue */
+	struct hlos_h2n_desc_rings h2n_desc_rings[NSS_H2N_DESC_RING_NUM];
+					/* Host to NSS descriptor rings */
+	struct hlos_n2h_desc_ring n2h_desc_ring[NSS_N2H_DESC_RING_NUM];
+					/* NSS to Host descriptor rings */
+	uint16_t rps_en;		/* N2H Enable Multiple queues for Data Packets */
+	uint16_t n2h_mitigate_en;	/* N2H mitigation */
+	uint32_t max_buf_size;		/* Maximum buffer size */
+	uint32_t buf_sz_allocated;	/* size of bufs allocated from host */
+	nss_cmn_queue_decongestion_callback_t queue_decongestion_callback[NSS_MAX_CLIENTS];
+					/* Queue decongestion callbacks */
+	void *queue_decongestion_ctx[NSS_MAX_CLIENTS];
+					/* Queue decongestion callback contexts */
+	nss_cmn_service_code_callback_t service_code_callback[NSS_MAX_SERVICE_CODE];
+					/* Service code callbacks */
+	void *service_code_ctx[NSS_MAX_SERVICE_CODE];
+					/* Service code callback contexts */
+	spinlock_t decongest_cb_lock;	/* Lock to protect queue decongestion cb table */
+	uint16_t phys_if_mtu[NSS_MAX_PHYSICAL_INTERFACES];
+					/* Current MTU value of physical interface */
+	uint32_t worker_thread_count;	/* Number of NSS core worker threads for statistics */
+	uint32_t irq_count;		/* Number of NSS core IRQs for statistics */
+	struct nss_worker_thread_stats *wt_stats;
+					/* Worker thread statistics */
+	struct nss_unaligned_stats unaligned_stats;
+					/* Unaligned emulation performance statistics */
+	struct nss_rx_cb_list nss_rx_interface_handlers[NSS_MAX_NET_INTERFACES];
+					/* NSS interface callback handlers */
+	struct nss_subsystem_dataplane_register subsys_dp_register[NSS_MAX_NET_INTERFACES];
+					/* Subsystem registration data */
+	uint32_t magic;
+					/* Magic protection */
+};
+
+/*
+ * Main NSS context structure (singleton)
+ */
+struct nss_top_instance {
+	uint8_t num_nss;			/* Number of NSS cores supported */
+	uint8_t num_phys_ports;			/* Number of physical ports supported */
+	uint32_t clk_src;			/* Clock source: default/alternate */
+	spinlock_t lock;			/* Big lock for NSS driver */
+	spinlock_t stats_lock;			/* Statistics lock */
+	struct mutex wq_lock;			/* Mutex for NSS Work queue function */
+	struct dentry *top_dentry;		/* Top dentry for nss */
+	struct dentry *stats_dentry;		/* Top dentry for nss stats */
+	struct dentry *strings_dentry;		/* Top dentry for nss stats strings */
+	struct dentry *project_dentry;		/* per-project stats dentry */
+	struct nss_ctx_instance nss[NSS_MAX_CORES];
+						/* NSS contexts */
+	/*
+	 * Network processing handler core ids (CORE0/CORE1) for various interfaces
+	 */
+	uint8_t phys_if_handler_id[NSS_MAX_PHYSICAL_INTERFACES];
+	uint8_t virt_if_handler_id;
+	uint8_t gre_redir_handler_id;
+	uint8_t gre_redir_lag_us_handler_id;
+	uint8_t gre_redir_lag_ds_handler_id;
+	uint8_t gre_tunnel_handler_id;
+	uint8_t shaping_handler_id;
+	uint8_t ipv4_handler_id;
+	uint8_t ipv4_reasm_handler_id;
+	uint8_t ipv6_handler_id;
+	uint8_t ipv6_reasm_handler_id;
+	uint8_t crypto_handler_id;
+	uint8_t ipsec_handler_id;
+	uint8_t wlan_handler_id;
+	uint8_t tun6rd_handler_id;
+	uint8_t wifi_handler_id;
+	uint8_t ppe_handler_id;
+	uint8_t pptp_handler_id;
+	uint8_t pppoe_handler_id;
+	uint8_t l2tpv2_handler_id;
+	uint8_t dtls_handler_id;
+	uint8_t gre_handler_id;
+	uint8_t map_t_handler_id;
+	uint8_t tunipip6_handler_id;
+	uint8_t frequency_handler_id;
+	uint8_t sjack_handler_id;
+	uint8_t capwap_handler_id;
+	uint8_t tstamp_handler_id;
+	uint8_t portid_handler_id;
+	uint8_t oam_handler_id;
+	uint8_t edma_handler_id;
+	uint8_t bridge_handler_id;
+	uint8_t trustsec_tx_handler_id;
+	uint8_t vlan_handler_id;
+	uint8_t qvpn_handler_id;
+	uint8_t pvxlan_handler_id;
+	uint8_t igs_handler_id;
+	uint8_t gre_redir_mark_handler_id;
+	uint8_t clmap_handler_id;
+	uint8_t vxlan_handler_id;
+	uint8_t rmnet_rx_handler_id;
+	uint8_t match_handler_id;
+	uint8_t tls_handler_id;
+	uint8_t mirror_handler_id;
+	uint8_t wmdb_handler_id;
+	uint8_t dma_handler_id;
+	uint8_t udp_st_handler_id;
+
+	/*
+	 * Data/Message callbacks for various interfaces
+	 */
+	nss_phys_if_msg_callback_t phys_if_msg_callback[NSS_MAX_PHYSICAL_INTERFACES];
+					/* Physical interface event callback functions */
+	nss_virt_if_msg_callback_t virt_if_msg_callback[NSS_MAX_VIRTUAL_INTERFACES];
+					/* Virtual interface messsage callback functions */
+	nss_ipv4_msg_callback_t ipv4_callback;
+					/* IPv4 sync/establish callback function */
+	nss_ipv6_msg_callback_t ipv6_callback;
+					/* IPv6 sync/establish callback function */
+	nss_ipsec_msg_callback_t ipsec_encap_callback;
+	nss_ipsec_msg_callback_t ipsec_decap_callback;
+					/* IPsec event callback function */
+	nss_crypto_msg_callback_t crypto_msg_callback;
+	nss_crypto_cmn_msg_callback_t crypto_cmn_msg_callback;
+	nss_crypto_buf_callback_t crypto_buf_callback;
+	nss_crypto_pm_event_callback_t crypto_pm_callback;
+					/* crypto interface callback functions */
+	nss_profiler_callback_t profiler_callback[NSS_MAX_CORES];
+					/* Profiler interface callback function */
+	nss_tun6rd_msg_callback_t tun6rd_msg_callback;
+					/* 6rd tunnel interface event callback function */
+	nss_wifi_msg_callback_t wifi_msg_callback;
+					/* wifi interface event callback function */
+	nss_l2tpv2_msg_callback_t l2tpv2_msg_callback;
+					/* l2tP tunnel interface event callback function */
+	nss_dtls_msg_callback_t dtls_msg_callback; /* dtls interface event callback */
+
+	nss_gre_tunnel_msg_callback_t gre_tunnel_msg_callback; /* gre tunnel interface event callback */
+
+	nss_map_t_msg_callback_t map_t_msg_callback;
+					/* map-t interface event callback function */
+	nss_gre_msg_callback_t gre_msg_callback;
+					/* gre interface event callback function */
+	nss_gre_data_callback_t gre_inner_data_callback;
+					/* gre inner data callback function */
+	nss_gre_data_callback_t gre_outer_data_callback;
+					/* gre outer data callback function */
+	nss_tunipip6_msg_callback_t tunipip6_msg_callback;
+					/* ipip6 tunnel interface event callback function */
+	nss_pptp_msg_callback_t pptp_msg_callback;
+					/* PPTP tunnel interface event callback function */
+	nss_pppoe_msg_callback_t pppoe_msg_callback;
+					/* PPPoE interface event callback function */
+	struct nss_shaper_bounce_registrant bounce_interface_registrants[NSS_MAX_NET_INTERFACES];
+					/* Registrants for interface shaper bounce operations */
+	struct nss_shaper_bounce_registrant bounce_bridge_registrants[NSS_MAX_NET_INTERFACES];
+					/* Registrants for bridge shaper bounce operations */
+	nss_lag_event_callback_t lag_event_callback;
+					/* Registrants for lag operations */
+	nss_oam_msg_callback_t oam_callback;
+					/* OAM call back */
+	nss_edma_msg_callback_t edma_callback;
+					/* EDMA callback */
+	nss_bridge_msg_callback_t bridge_callback;
+					/* Bridge callback */
+	nss_vlan_msg_callback_t vlan_callback;
+					/* Vlan callback */
+	nss_wifili_msg_callback_t wifili_msg_callback;
+					/* wifili interface event callback function */
+	nss_ipsec_cmn_msg_callback_t ipsec_cmn_msg_callback;
+					/*  IPSEC common interface event callback function */
+	nss_qvpn_msg_callback_t qvpn_msg_callback;
+					/* QVPN interface event callback function */
+	nss_rmnet_rx_msg_callback_t rmnet_rx_msg_callback[NSS_MAX_VIRTUAL_INTERFACES];
+					/* Virtual interface messsage callback functions */
+	nss_wifi_mac_db_msg_callback_t wifi_mac_db_msg_callback;
+					/* wifi mac database event callback function */
+
+	uint32_t dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_MAX];
+
+	/*
+	 * Interface contexts (non network device)
+	 */
+	void *ipv4_ctx;			/* IPv4 connection manager context */
+	void *ipv6_ctx;			/* IPv6 connection manager context */
+	void *crypto_ctx;		/* Crypto interface context */
+	void *crypto_pm_ctx;		/* Crypto PM context */
+	void *profiler_ctx[NSS_MAX_CORES];
+					/* Profiler interface context */
+	void *ipsec_encap_ctx;		/* IPsec encap context */
+	void *ipsec_decap_ctx;		/* IPsec decap context */
+	void *oam_ctx;			/* oam context */
+	void *edma_ctx;			/* edma context */
+	void *bridge_ctx;		/* Bridge context */
+	void *vlan_ctx;			/* Vlan context */
+
+	/*
+	 * Statistics for various interfaces
+	 */
+	atomic64_t stats_drv[NSS_DRV_STATS_MAX];
+					/* Hlos driver statistics */
+	uint64_t stats_gmac[NSS_MAX_PHYSICAL_INTERFACES][NSS_GMAC_STATS_MAX];
+					/* GMAC statistics */
+	uint64_t stats_node[NSS_MAX_NET_INTERFACES][NSS_STATS_NODE_MAX];
+					/* IPv4 statistics per interface */
+	bool nss_hal_common_init_done;
+
+	uint16_t prev_mtu_sz;		/* mtu sz needed as of now */
+	uint16_t crypto_enabled;	/* check if crypto is enabled on the platform */
+
+	/*
+	 * TODO: Review and update following fields
+	 */
+	uint64_t last_rx_jiffies;	/* Time of the last RX message from the NA in jiffies */
+	struct nss_hal_ops *hal_ops;	/* nss_hal ops for this target platform */
+	struct nss_data_plane_ops *data_plane_ops;
+					/* nss_data_plane ops for this target platform */
+};
+
+#if (NSS_PKT_STATS_ENABLED == 1)
+/*
+ * nss_pkt_stats_inc()
+ */
+static inline void nss_pkt_stats_inc(atomic64_t *stat)
+{
+	atomic64_inc(stat);
+}
+
+/*
+ * nss_pkt_stats_dec()
+ */
+static inline void nss_pkt_stats_dec(atomic64_t *stat)
+{
+	atomic64_dec(stat);
+}
+
+/*
+ * nss_pkt_stats_add()
+ */
+static inline void nss_pkt_stats_add(atomic64_t *stat, uint32_t pkt)
+{
+	atomic64_add(pkt, stat);
+}
+
+/*
+ * nss_pkt_stats_sub()
+ */
+static inline void nss_pkt_stats_sub(atomic64_t *stat, uint32_t pkt)
+{
+	atomic64_sub(pkt, stat);
+}
+
+/*
+ * nss_pkt_stats_read()
+ */
+static inline uint64_t nss_pkt_stats_read(atomic64_t *stat)
+{
+	return atomic64_read(stat);
+}
+
+#endif
+
+/*
+ * NSS Statistics and Data for User Space
+ */
+struct nss_cmd_buffer {
+	uint32_t current_freq;	/* Current Running Freq of NSS */
+	int32_t auto_scale;	/* Enable or Disable auto_scale */
+	int32_t max_freq;	/* Maximum supported frequency index value */
+	uint32_t register_addr;	/* register addr buffer */
+	uint32_t register_data;	/* register data buffer */
+	uint32_t average_inst;	/* average of inst for nss core */
+	uint32_t coredump;	/* cmd coredump buffer */
+};
+extern struct nss_cmd_buffer nss_cmd_buf;
+
+/*
+ * The scales for NSS
+ */
+typedef enum nss_freq_scales {
+	NSS_FREQ_LOW_SCALE = 0,
+	NSS_FREQ_MID_SCALE = 1,
+	NSS_FREQ_HIGH_SCALE = 2,
+	NSS_FREQ_MAX_SCALE = 3,
+} nss_freq_scales_t;
+
+/*
+ * NSS Core Statistics and Frequencies
+ */
+#define NSS_SAMPLE_BUFFER_SIZE 4			/* Ring Buffer should be a Size of two */
+#define NSS_SAMPLE_BUFFER_MASK (NSS_SAMPLE_BUFFER_SIZE - 1)
+#define NSS_FREQUENCY_SCALE_RATE_LIMIT_UP 2		/* Adjust the Rate of Frequency Switching Up */
+#define NSS_FREQUENCY_SCALE_RATE_LIMIT_DOWN 60000	/* Adjust the Rate of Frequency Switching Down */
+#define NSS_MESSAGE_RATE_LIMIT 15000			/* Adjust the Rate of Displaying Statistic Messages */
+
+/*
+ * NSS Frequency Scale Info
+ *
+ * INFO: Contains the Scale information per Frequency
+ *	Per Scale information needed to Program PLL and make switching decisions
+ */
+struct nss_scale_info {
+	uint32_t frequency;	/* Frequency in Mhz */
+	uint32_t minimum;	/* Minimum INST_CNT per Sec */
+	uint32_t maximum;	/* Maximum INST_CNT per Sec */
+};
+
+/*
+ * NSS Runtime Sample Structure
+ *
+ * INFO: Contains the runtime statistic of the NSS core
+ *	Also contains the per frequency scale array
+ */
+struct nss_runtime_sampling {
+	struct nss_scale_info freq_scale[NSS_FREQ_MAX_SCALE];	/* NSS Max Scale Per Freq */
+	nss_freq_scales_t freq_scale_index;			/* Current Freq Index */
+	uint32_t freq_scale_ready;				/* Allow Freq Scaling */
+	uint32_t freq_scale_rate_limit_up;			/* Scaling Change Rate Limit */
+	uint32_t freq_scale_rate_limit_down;			/* Scaling Change Rate Limit */
+	uint32_t buffer[NSS_SAMPLE_BUFFER_SIZE];		/* Sample Ring Buffer */
+	uint32_t buffer_index;					/* Running Buffer Index */
+	uint32_t sum;						/* Total INST_CNT SUM */
+	uint32_t sample_count;					/* Number of Samples stored in Ring Buffer */
+	uint32_t average;					/* Average of INST_CNT */
+	uint32_t message_rate_limit;				/* Debug Message Rate Limit */
+	uint32_t initialized;					/* Flag to check for adequate initial samples */
+};
+
+/*
+ * cpu_utilization
+ */
+struct nss_freq_cpu_usage {
+	uint32_t used;					/* CPU utilization at a certain frequency percentage */
+	uint32_t max_ins;				/* Maximum instructions that can be executed in 1ms at the current frequency
+								This value is calculated by diving frequency by 1000.	*/
+	uint32_t total;					/* Total usage added over a time of NSS_FREQ_USG_AVG_FREQUENCY milliseconds*/
+	uint32_t max;					/* Maximum CPU usage since the boot (%) */
+	uint32_t min;					/* Minimum CPU usage since the boot (%) */
+	uint32_t avg_up;				/* Actual upper bound of the CPU USAGE (%)*/
+	uint16_t avg_ctr;				/* Averaging counter */
+};
+
+#if (NSS_DT_SUPPORT == 1)
+/*
+ * nss_feature_enabled
+ */
+enum nss_feature_enabled {
+	NSS_FEATURE_NOT_ENABLED = 0,		/* Feature is not enabled on this core */
+	NSS_FEATURE_ENABLED,			/* Feature is enabled on this core */
+};
+
+/*
+ * nss_platform_data
+ *      Platform data per core
+ */
+struct nss_platform_data {
+	uint32_t id;				/* NSS core ID */
+	uint32_t num_queue;			/* No. of queues supported per core */
+	uint32_t num_irq;			/* No. of irq binded per queue */
+	uint32_t irq[NSS_MAX_IRQ_PER_CORE];	/* IRQ numbers per queue */
+	void __iomem *nmap;			/* Virtual addr of NSS CSM space */
+	void __iomem *vmap;			/* Virtual addr of NSS virtual register map */
+	void __iomem *qgic_map;			/* Virtual addr of QGIC interrupt register */
+	uint32_t nphys;				/* Physical addr of NSS CSM space */
+	uint32_t vphys;				/* Physical addr of NSS virtual register map */
+	uint32_t qgic_phys;			/* Physical addr of QGIC virtual register map */
+	uint32_t load_addr;			/* Load address of NSS firmware */
+
+	enum nss_feature_enabled capwap_enabled;
+				/* Does this core handle capwap? */
+	enum nss_feature_enabled crypto_enabled;
+				/* Does this core handle crypto? */
+	enum nss_feature_enabled dtls_enabled;
+				/* Does this core handle DTLS sessions ? */
+	enum nss_feature_enabled gre_redir_enabled;
+				/* Does this core handle gre_redir Tunnel ? */
+	enum nss_feature_enabled gre_tunnel_enabled;
+				/* Does this core handle gre_tunnel Tunnel ? */
+	enum nss_feature_enabled ipsec_enabled;
+				/* Does this core handle IPsec? */
+	enum nss_feature_enabled ipv4_enabled;
+				/* Does this core handle IPv4? */
+	enum nss_feature_enabled ipv4_reasm_enabled;
+				/* Does this core handle IPv4 reassembly? */
+	enum nss_feature_enabled ipv6_enabled;
+				/* Does this core handle IPv6? */
+	enum nss_feature_enabled ipv6_reasm_enabled;
+				/* Does this core handle IPv6 reassembly? */
+	enum nss_feature_enabled l2tpv2_enabled;
+				/* Does this core handle l2tpv2 Tunnel ? */
+	enum nss_feature_enabled map_t_enabled;
+				/* Does this core handle map-t */
+	enum nss_feature_enabled gre_enabled;
+				/* Does this core handle GRE */
+	enum nss_feature_enabled oam_enabled;
+				/* Does this core handle oam? */
+	enum nss_feature_enabled ppe_enabled;
+				/* Does this core handle ppe ? */
+	enum nss_feature_enabled pppoe_enabled;
+				/* Does this core handle pppoe? */
+	enum nss_feature_enabled pptp_enabled;
+				/* Does this core handle pptp Tunnel ? */
+	enum nss_feature_enabled portid_enabled;
+				/* Does this core handle portid? */
+	enum nss_feature_enabled shaping_enabled;
+				/* Does this core handle shaping ? */
+	enum nss_feature_enabled tstamp_enabled;
+				/* Does this core handle timestamping? */
+	enum nss_feature_enabled turbo_frequency;
+				/* Does this core support turbo frequencies */
+	enum nss_feature_enabled tun6rd_enabled;
+				/* Does this core handle 6rd Tunnel ? */
+	enum nss_feature_enabled tunipip6_enabled;
+				/* Does this core handle ipip6 Tunnel ? */
+	enum nss_feature_enabled wlanredirect_enabled;
+				/* Does this core handle WLAN redirect? */
+	enum nss_feature_enabled wifioffload_enabled;
+				/* Does this core handle WIFI OFFLOAD? */
+	enum nss_feature_enabled bridge_enabled;
+				/* Does this core handle bridge configuration */
+	enum nss_feature_enabled vlan_enabled;
+				/* Does this core handle vlan configuration */
+	enum nss_feature_enabled qvpn_enabled;
+				/* Does this core handle QVPN Tunnel ? */
+	enum nss_feature_enabled pvxlan_enabled;
+				/* Does this core handle pvxlan? */
+	enum nss_feature_enabled igs_enabled;
+				/* Does this core handle igs? */
+	enum nss_feature_enabled gre_redir_mark_enabled;
+				/* Does this core handle GRE redir mark? */
+	enum nss_feature_enabled clmap_enabled;
+				/* Does this core handle clmap? */
+	enum nss_feature_enabled vxlan_enabled;
+				/* Does this core handle vxlan tunnel? */
+	enum nss_feature_enabled rmnet_rx_enabled;
+				/* Does this core handle rmnet rx? */
+	enum nss_feature_enabled match_enabled;
+				/* Does this core handle match node? */
+	enum nss_feature_enabled tls_enabled;
+				/* Does this core handle TLS Tunnel ? */
+	enum nss_feature_enabled mirror_enabled;
+				/* Does this core handle mirror? */
+	enum nss_feature_enabled udp_st_enabled;
+				/* Does this core handle udp st? */
+};
+#endif
+
+/*
+ * nss_core_log_msg_failures()
+ *	Driver function for logging failed messages.
+ */
+static inline void nss_core_log_msg_failures(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm)
+{
+	if ((ncm->response == NSS_CMN_RESPONSE_ACK) || (ncm->response == NSS_CMN_RESPONSE_NOTIFY)) {
+		return;
+	}
+
+	/*
+	 * TODO: Is it worth doing value to name on these values?
+	 */
+	nss_warning("%px: msg failure - interface: %d, type: %d, response: %d, error: %d",
+		nss_ctx, ncm->interface, ncm->type, ncm->response, ncm->error);
+}
+
+/*
+ * NSS workqueue to change frequencies
+ */
+typedef struct {
+	struct work_struct my_work;	/* Work Structure */
+	uint32_t frequency;		/* Frequency To Change */
+	uint32_t stats_enable;		/* Auto scale on/off */
+} nss_work_t;
+
+/*
+ * APIs provided by nss_core.c
+ */
+extern int nss_core_handle_napi(struct napi_struct *napi, int budget);
+extern int nss_core_handle_napi_queue(struct napi_struct *napi, int budget);
+extern int nss_core_handle_napi_non_queue(struct napi_struct *napi, int budget);
+extern int nss_core_handle_napi_emergency(struct napi_struct *napi, int budget);
+extern int nss_core_handle_napi_sdma(struct napi_struct *napi, int budget);
+extern int32_t nss_core_send_buffer(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+					struct sk_buff *nbuf, uint16_t qid,
+					uint8_t buffer_type, uint16_t flags);
+extern int32_t nss_core_send_cmd(struct nss_ctx_instance *nss_ctx, void *msg, int size, int buf_size);
+extern int32_t nss_core_send_packet(struct nss_ctx_instance *nss_ctx, struct sk_buff *nbuf, uint32_t if_num, uint32_t flag);
+extern uint32_t nss_core_ddr_info(struct nss_mmu_ddr_info *coreinfo);
+extern uint32_t nss_core_register_msg_handler(struct nss_ctx_instance *nss_ctx, uint32_t interface, nss_if_rx_msg_callback_t msg_cb);
+extern uint32_t nss_core_unregister_msg_handler(struct nss_ctx_instance *nss_ctx, uint32_t interface);
+extern uint32_t nss_core_register_handler(struct nss_ctx_instance *nss_ctx, uint32_t interface, nss_core_rx_callback_t cb, void *app_data);
+extern uint32_t nss_core_unregister_handler(struct nss_ctx_instance *nss_ctx, uint32_t interface);
+extern void nss_core_init_handlers(struct nss_ctx_instance *nss_ctx);
+void nss_core_update_max_ipv4_conn(int conn);
+void nss_core_update_max_ipv6_conn(int conn);
+extern void nss_core_register_subsys_dp(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+					nss_phys_if_rx_callback_t cb,
+					nss_phys_if_rx_ext_data_callback_t ext_cb,
+					void *app_data, struct net_device *ndev,
+					uint32_t features);
+extern void nss_core_unregister_subsys_dp(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+void nss_core_set_subsys_dp_type(struct nss_ctx_instance *nss_ctx, struct net_device *ndev, uint32_t if_num, uint32_t type);
+
+static inline nss_if_rx_msg_callback_t nss_core_get_msg_handler(struct nss_ctx_instance *nss_ctx, uint32_t interface)
+{
+	return nss_ctx->nss_rx_interface_handlers[interface].msg_cb;
+}
+
+static inline uint32_t nss_core_get_max_buf_size(struct nss_ctx_instance *nss_ctx)
+{
+	return nss_ctx->max_buf_size;
+}
+
+/*
+ * APIs provided by nss_tx_rx.c
+ */
+extern void nss_rx_handle_status_pkt(struct nss_ctx_instance *nss_ctx, struct sk_buff *nbuf);
+
+/*
+ * APIs provided by nss_stats.c
+ */
+extern void nss_stats_init(void);
+extern void nss_stats_clean(void);
+
+/*
+ * APIs provided by nss_log.c
+ */
+extern void nss_log_init(void);
+extern bool nss_debug_log_buffer_alloc(uint8_t nss_id, uint32_t nentry);
+extern int nss_logbuffer_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos);
+
+/*
+ * APIs to set jumbo_mru & paged_mode
+ */
+extern void nss_core_set_jumbo_mru(int jumbo_mru);
+extern int nss_core_get_jumbo_mru(void);
+extern void nss_core_set_paged_mode(int mode);
+extern int nss_core_get_paged_mode(void);
+#if (NSS_SKB_REUSE_SUPPORT == 1)
+extern void nss_core_set_max_reuse(int max);
+extern int nss_core_get_max_reuse(void);
+extern uint32_t nss_core_get_min_reuse(struct nss_ctx_instance *nss_ctx);
+#endif
+
+/*
+ * APIs for coredump
+ */
+extern void nss_coredump_notify_register(void);
+extern void nss_fw_coredump_notify(struct nss_ctx_instance *nss_own, int intr);
+extern int nss_coredump_init_delay_work(void);
+
+/*
+ * APIs provided by nss_freq.c
+ */
+extern bool nss_freq_sched_change(nss_freq_scales_t index, bool auto_scale);
+
+/*
+ * nss_freq_init_cpu_usage
+ *	Initializes the cpu usage computation.
+ */
+extern void nss_freq_init_cpu_usage(void);
+
+/*
+ * APIs for PPE
+ */
+extern void nss_ppe_init(void);
+extern void nss_ppe_free(void);
+
+/*
+ * APIs for N2H
+ */
+extern nss_tx_status_t nss_n2h_cfg_empty_pool_size(struct nss_ctx_instance *nss_ctx, uint32_t pool_sz);
+extern nss_tx_status_t nss_n2h_paged_buf_pool_init(struct nss_ctx_instance *nss_ctx);
+
+#endif /* __NSS_CORE_H */
diff --git a/qca-nss-drv/nss_coredump.c b/qca-nss-drv/nss_coredump.c
new file mode 100644
index 0000000..691a9a7
--- /dev/null
+++ b/qca-nss-drv/nss_coredump.c
@@ -0,0 +1,257 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_core.c
+ *	NSS driver core APIs source file.
+ */
+
+#include "nss_core.h"
+#include "nss_hal.h"
+#include "nss_log.h"
+#include <linux/kernel.h>
+#include <linux/notifier.h>	/* for panic_notifier_list */
+#include <linux/jiffies.h>	/* for time */
+#include "nss_tx_rx_common.h"
+
+#if NSS_MAX_CORES > 2	/* see comment in nss_fw_coredump_notify */
+#error	too many NSS Cores: should be 1 or 2
+#endif
+
+static struct delayed_work coredump_queuewait;
+static struct workqueue_struct *coredump_workqueue;
+
+/*
+ * nss_coredump_wait()
+ *	reboot (panic) if all finished coredump interrupts will not come.
+ *   N2H (C2C) interrupt may get lost during trap, as well NSS may start
+ * only one core; so timeout if less than desird core sends back finished
+ * coredump interrupt.
+ */
+static void nss_coredump_wait(struct work_struct *work)
+{
+	panic("did not get all coredump finished signals\n");
+}
+
+/*
+ * nss_coredump_init_delay_work()
+ *	set a wait function in case coredump finish interrupt lost or
+ * only one NSS core is up.
+ */
+int nss_coredump_init_delay_work(void)
+{
+	coredump_workqueue = create_singlethread_workqueue("coredump_wait");
+	if (!coredump_workqueue) {
+		nss_warning("can't set wait: hopefully all int will come\n");
+		return -ENOMEM;
+	}
+
+	INIT_DELAYED_WORK(&coredump_queuewait, nss_coredump_wait);
+	return 0;
+}
+
+/*
+ * nss_panic_handler()
+ *	notification callback register to panic chain
+ */
+static int nss_panic_handler(struct notifier_block *nb,
+			unsigned long action, void *data)
+{
+	int dumped, timed;
+	int i;
+
+	for (i = 0; i < nss_top_main.num_nss; i++) {
+		struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[i];
+		if (nss_ctx->state & NSS_CORE_STATE_FW_DEAD || !nss_ctx->nmap)
+			continue;
+		nss_ctx->state |= NSS_CORE_STATE_PANIC;
+		nss_hal_send_interrupt(nss_ctx, NSS_H2N_INTR_TRIGGER_COREDUMP);
+		nss_warning("panic call NSS FW %px to dump %x\n",
+			nss_ctx->nmap, nss_ctx->state);
+	}
+
+	/*
+	 * wait for FW coredump done: maximum 2 rounds for each core
+	 * 200ms per round -- 16MB * 10 over 200MHz 32-bit memory bus
+	 * panic will take another 3-5 seconds to reboot, so longer enough.
+	 */
+	dumped = timed = 0;
+	do {
+		mdelay(200);
+		for (i = 0; i < nss_top_main.num_nss; i++) {
+			struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[i];
+			if ((nss_ctx->state & NSS_CORE_STATE_FW_DEAD ||
+				!nss_ctx->nmap) &&
+			    !(nss_ctx->state & NSS_CORE_STATE_FW_DUMP)) {
+				nss_ctx->state |= NSS_CORE_STATE_FW_DUMP;
+				dumped++;
+			}
+		}
+		if (dumped >= nss_top_main.num_nss) {
+			nss_warning("NSS FW dump completed\n");
+			break;
+		}
+	} while (timed++ < nss_top_main.num_nss * 2);
+
+	if (timed >= nss_top_main.num_nss * 2)
+		nss_warning("might get %d FW dumped", dumped);
+
+	return	NOTIFY_DONE;
+}
+
+static struct notifier_block	nss_panic_nb = {
+	.notifier_call = nss_panic_handler,
+};
+
+/*
+ * nss_coredump_notify_register()
+ *	API for nss_init to register coredump notifier to panic chain
+ */
+void nss_coredump_notify_register(void)
+{
+	atomic_notifier_chain_register(&panic_notifier_list, &nss_panic_nb);
+}
+
+/*
+ * nss_fw_coredump_notify()
+ *	handler for coredump notification from NSS FW
+ */
+void nss_fw_coredump_notify(struct nss_ctx_instance *nss_own,
+				int intr __attribute__ ((unused)))
+{
+	int i, j, curr_index, useful_entries, num_cores_wait;
+	struct nss_log_descriptor *nld;
+	struct nss_log_entry *nle_init, *nle_print;
+	dma_addr_t dma_addr;
+	uint32_t offset, index;
+
+	nss_warning("%px: COREDUMP %x Baddr %px stat %x",
+			nss_own, intr, nss_own->nmap, nss_own->state);
+	nss_own->state |= NSS_CORE_STATE_FW_DEAD;
+	queue_delayed_work(coredump_workqueue, &coredump_queuewait,
+			msecs_to_jiffies(3456));
+
+	/*
+	 * If external log buffer is not set, use the nss initial log buffer.
+	 */
+	nld = (struct nss_log_descriptor *)(nss_rbe[nss_own->id].addr);
+	dma_addr = nss_rbe[nss_own->id].dma_addr;
+	if (!nld) {
+		nld = nss_own->meminfo_ctx.logbuffer;
+		dma_addr = nss_own->meminfo_ctx.logbuffer_dma;
+	}
+
+	dma_sync_single_for_cpu(NULL, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE);
+
+	/*
+	 * If the current entry is smaller than or equal to the number of NSS_LOG_COREDUMP_LINE_NUM,
+	 * only print whatever is in the buffer. Otherwise, dump last NSS_LOG_COREDUMP_LINE_NUM
+	 * to the dmessage.
+	 */
+	nss_info_always("%px: Starting NSS-FW logbuffer dump for core %u\n",
+			nss_own, nss_own->id);
+	nle_init = nld->log_ring_buffer;
+	if (nld->current_entry <= NSS_LOG_COREDUMP_LINE_NUM) {
+		curr_index = 0;
+		useful_entries = nld->current_entry;
+	} else {
+		curr_index = ((nld->current_entry - NSS_LOG_COREDUMP_LINE_NUM) % nld->log_nentries);
+		useful_entries = NSS_LOG_COREDUMP_LINE_NUM;
+	}
+
+	nle_print = nle_init + curr_index;
+	for (j = index = curr_index; j < (curr_index + useful_entries); j++, index++) {
+		if (j == nld->log_nentries) {
+			nle_print = nle_init;
+			index = 0;
+		}
+
+		offset = (index * sizeof(struct nss_log_entry))
+			+ offsetof(struct nss_log_descriptor, log_ring_buffer);
+		dma_sync_single_for_cpu(NULL, dma_addr + offset,
+				sizeof(struct nss_log_entry), DMA_FROM_DEVICE);
+		nss_info_always("%px: %s\n", nss_own, nle_print->message);
+		nle_print++;
+	}
+
+	if (nss_own->state & NSS_CORE_STATE_PANIC)
+		return;
+
+	/*
+	 * We need to wait until all other cores finish their dump.
+	 */
+	num_cores_wait = (nss_top_main.num_nss - 1);
+	if (!num_cores_wait) {
+		/*
+		 * nss_cmd_buf.coredump values:
+		 *	0 ==	normal coredump and panic
+		 * non-zero value is for debug purpose:
+		 *	1 ==	force coredump and panic
+		 * otherwise	coredump but do not panic.
+		 */
+		if (!(nss_cmd_buf.coredump & 0xFFFFFFFE)) {
+			panic("NSS FW coredump: bringing system down\n");
+		}
+		nss_info_always("NSS core dump completed & use mdump to collect dump to debug\n");
+		return;
+	}
+
+	for (i = 0; i < nss_top_main.num_nss; i++) {
+		struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[i];
+
+		/*
+		 * Skip waiting for ourselves to coredump, we already have.
+		 */
+		if (nss_ctx == nss_own) {
+			continue;
+		}
+
+		/*
+		 * Notify any live core to dump.
+		 */
+		if (!(nss_ctx->state & NSS_CORE_STATE_FW_DEAD) && nss_ctx->nmap) {
+			nss_warning("notify NSS FW %px for coredump\n", nss_ctx->nmap);
+			nss_hal_send_interrupt(nss_ctx, NSS_H2N_INTR_TRIGGER_COREDUMP);
+			continue;
+		}
+
+		/*
+		 * bit 1 is used for testing coredump. Any other
+		 * bit(s) (value other than 0/1) disable panic
+		 * in order to use mdump utility: see mdump/src/README
+		 * for more info.
+		 */
+		if (nss_cmd_buf.coredump & 0xFFFFFFFE) {
+			nss_info_always("NSS core dump completed and please use mdump to collect dump data\n");
+			continue;
+		}
+
+		/*
+		 * Ideally we need to unregister ourselves from the panic
+		 * notifier list before calling the panic to prevent infinite calling.
+		 * However, When we tried, we couldn't make it work. Therefore, We just leave the corresponding call here
+		 * if it will be needed in the future.
+		 *
+		 * atomic_notifier_chain_unregister(&panic_notifier_list, &nss_panic_nb);
+		 */
+		num_cores_wait--;
+		if (!num_cores_wait) {
+			panic("NSS FW coredump: bringing system down\n");
+			return;
+		}
+
+	}
+}
diff --git a/qca-nss-drv/nss_crypto.c b/qca-nss-drv/nss_crypto.c
new file mode 100644
index 0000000..96d8c5b
--- /dev/null
+++ b/qca-nss-drv/nss_crypto.c
@@ -0,0 +1,302 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013,2015-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_crypto.c
+ *	NSS Crypto APIs
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_crypto.h"
+#include "nss_crypto_log.h"
+
+/*
+ **********************************
+ General APIs
+ **********************************
+ */
+
+/*
+ * nss_crypto_set_msg_callback()
+ *	this sets the message callback handler and its associated context
+ */
+static inline void nss_crypto_set_msg_callback(struct nss_ctx_instance *nss_ctx, nss_crypto_msg_callback_t cb, void *crypto_ctx)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	nss_top->crypto_ctx = crypto_ctx;
+	nss_top->crypto_msg_callback = cb;
+}
+
+/*
+ * nss_crypto_get_msg_callback()
+ *	this gets the message callback handler and its associated context
+ */
+static inline nss_crypto_msg_callback_t nss_crypto_get_msg_callback(struct nss_ctx_instance *nss_ctx, void **crypto_ctx)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	*crypto_ctx = nss_top->crypto_ctx;
+	return nss_top->crypto_msg_callback;
+}
+
+/*
+ * nss_crypto_msg_handler()
+ *	this handles all the IPsec events and responses
+ */
+static void nss_crypto_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, void *app_data __attribute((unused)))
+{
+	struct nss_crypto_msg *nim = (struct nss_crypto_msg *)ncm;
+	nss_crypto_msg_callback_t cb = NULL;
+	void *crypto_ctx = NULL;
+
+	/*
+	 * Sanity check the message type
+	 */
+	if (ncm->type > NSS_CRYPTO_MSG_TYPE_MAX) {
+		nss_warning("%px: rx message type out of range: %d", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_crypto_msg)) {
+		nss_warning("%px: rx message length is invalid: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	if (ncm->interface != NSS_CRYPTO_INTERFACE) {
+		nss_warning("%px: rx message request for another interface: %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	if (ncm->response == NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: rx message response for if %d, type %d, is invalid: %d", nss_ctx, ncm->interface,
+				ncm->type, ncm->response);
+		return;
+	}
+
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_crypto_get_msg_callback(nss_ctx, &crypto_ctx);
+		ncm->app_data = (nss_ptr_t)crypto_ctx;
+	}
+
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Trace messages.
+	 */
+	nss_crypto_log_rx_msg(nim);
+
+	/*
+	 * Load, Test & call
+	 */
+	cb = (nss_crypto_msg_callback_t)ncm->cb;
+	if (unlikely(!cb)) {
+		nss_trace("%px: rx handler has been unregistered for i/f: %d", nss_ctx, ncm->interface);
+		return;
+	}
+	cb((void *)ncm->app_data, nim);
+}
+/*
+ **********************************
+ Tx APIs
+ **********************************
+ */
+
+/*
+ * nss_crypto_tx_msg
+ *	Send crypto config to NSS.
+ */
+nss_tx_status_t nss_crypto_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_crypto_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	nss_info("%px: tx message %d for if %d\n", nss_ctx, ncm->type, ncm->interface);
+
+	BUILD_BUG_ON(NSS_NBUF_PAYLOAD_SIZE < sizeof(struct nss_crypto_msg));
+
+	if (ncm->interface != NSS_CRYPTO_INTERFACE) {
+		nss_warning("%px: tx message request for another interface: %d", nss_ctx, ncm->interface);
+	}
+
+	if (ncm->type > NSS_CRYPTO_MSG_TYPE_MAX) {
+		nss_warning("%px: tx message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	nss_info("msg params version:%d, interface:%d, type:%d, cb:%px, app_data:%px, len:%d\n",
+			ncm->version, ncm->interface, ncm->type, (void *)ncm->cb, (void *)ncm->app_data, ncm->len);
+
+	/*
+	 * Trace messages.
+	 */
+	nss_crypto_log_tx_msg(msg);
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ * nss_crypto_tx_data()
+ *	NSS crypto TX data API. Sends a crypto buffer to NSS.
+ */
+nss_tx_status_t nss_crypto_tx_buf(struct nss_ctx_instance *nss_ctx, uint32_t if_num, struct sk_buff *skb)
+{
+	int32_t status;
+
+	nss_trace("%px: tx_data buf=%px", nss_ctx, skb);
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	if (unlikely(nss_ctx->state != NSS_CORE_STATE_INITIALIZED)) {
+		nss_warning("%px: tx_data packet dropped as core not ready", nss_ctx);
+		return NSS_TX_FAILURE_NOT_READY;
+	}
+
+	status = nss_core_send_buffer(nss_ctx, if_num, skb, NSS_IF_H2N_DATA_QUEUE, H2N_BUFFER_PACKET, H2N_BIT_FLAG_BUFFER_REUSABLE);
+	if (unlikely(status != NSS_CORE_STATUS_SUCCESS)) {
+		nss_warning("%px: tx_data Unable to enqueue packet", nss_ctx);
+		if (status == NSS_CORE_STATUS_FAILURE_QUEUE) {
+			return NSS_TX_FAILURE_QUEUE;
+		}
+
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Kick the NSS awake so it can process our new entry.
+	 */
+	nss_hal_send_interrupt(nss_ctx, NSS_H2N_INTR_DATA_COMMAND_QUEUE);
+
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_CRYPTO_REQ]);
+
+	return NSS_TX_SUCCESS;
+}
+
+/*
+ **********************************
+ Register APIs
+ **********************************
+ */
+
+/*
+ * nss_crypto_notify_register()
+ *	register message notifier for crypto interface
+ */
+struct nss_ctx_instance *nss_crypto_notify_register(nss_crypto_msg_callback_t cb, void *app_data)
+{
+	struct nss_ctx_instance *nss_ctx;
+
+	nss_ctx = &nss_top_main.nss[nss_top_main.crypto_handler_id];
+
+	nss_crypto_set_msg_callback(nss_ctx, cb, app_data);
+
+	return nss_ctx;
+}
+
+/*
+ * nss_crypto_notify_unregister()
+ *	unregister message notifier for crypto interface
+ */
+void nss_crypto_notify_unregister(struct nss_ctx_instance *nss_ctx)
+{
+	nss_crypto_set_msg_callback(nss_ctx, NULL, NULL);
+}
+
+/*
+ * nss_crypto_data_register()
+ *	register a data callback routine
+ */
+struct nss_ctx_instance *nss_crypto_data_register(uint32_t if_num, nss_crypto_buf_callback_t cb,
+		struct net_device *netdev, uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx;
+
+	nss_ctx = &nss_top_main.nss[nss_top_main.crypto_handler_id];
+
+	if ((if_num >= NSS_MAX_NET_INTERFACES) && (if_num < NSS_MAX_PHYSICAL_INTERFACES)) {
+		nss_warning("%px: data register received for invalid interface %d", nss_ctx, if_num);
+		return NULL;
+	}
+
+	/*
+	 * Register subsystem, ensuring that no duplicate registrations occur.
+	 */
+	nss_core_register_subsys_dp(nss_ctx, if_num, cb, NULL, NULL, netdev, features);
+
+	return nss_ctx;
+}
+
+/*
+ * nss_crypto_data_unregister()
+ *	unregister a data callback routine
+ */
+void nss_crypto_data_unregister(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	if ((if_num >= NSS_MAX_NET_INTERFACES) && (if_num < NSS_MAX_PHYSICAL_INTERFACES)) {
+		nss_warning("%px: data unregister received for invalid interface %d", nss_ctx, if_num);
+		return;
+	}
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+}
+
+/*
+ * nss_crypto_pm_notify_register()
+ *	register a PM notify callback routine
+ */
+void nss_crypto_pm_notify_register(nss_crypto_pm_event_callback_t cb, void *app_data)
+{
+	nss_top_main.crypto_pm_ctx = app_data;
+	nss_top_main.crypto_pm_callback = cb;
+}
+
+/*
+ * nss_crypto_pm_notify_unregister()
+ *	unregister a PM notify callback routine
+ */
+void nss_crypto_pm_notify_unregister(void)
+{
+	nss_top_main.crypto_pm_ctx = NULL;
+	nss_top_main.crypto_pm_callback = NULL;
+}
+
+/*
+ * nss_crypto_register_handler()
+ */
+void nss_crypto_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[nss_top_main.crypto_handler_id];
+
+	nss_core_register_handler(nss_ctx, NSS_CRYPTO_INTERFACE, nss_crypto_msg_handler, NULL);
+}
+
+/*
+ * nss_crypto_msg_init()
+ *	Initialize crypto message
+ */
+void nss_crypto_msg_init(struct nss_crypto_msg *ncm, uint16_t if_num, uint32_t type, uint32_t len,
+				nss_crypto_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, (void *)cb, app_data);
+}
+
+EXPORT_SYMBOL(nss_crypto_notify_register);
+EXPORT_SYMBOL(nss_crypto_notify_unregister);
+EXPORT_SYMBOL(nss_crypto_data_register);
+EXPORT_SYMBOL(nss_crypto_data_unregister);
+EXPORT_SYMBOL(nss_crypto_pm_notify_register);
+EXPORT_SYMBOL(nss_crypto_pm_notify_unregister);
+EXPORT_SYMBOL(nss_crypto_tx_msg);
+EXPORT_SYMBOL(nss_crypto_tx_buf);
+EXPORT_SYMBOL(nss_crypto_msg_init);
diff --git a/qca-nss-drv/nss_crypto_cmn.c b/qca-nss-drv/nss_crypto_cmn.c
new file mode 100644
index 0000000..35c4c8c
--- /dev/null
+++ b/qca-nss-drv/nss_crypto_cmn.c
@@ -0,0 +1,388 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013,2015-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_crypto_cmn.c
+ *	NSS Crypto common API implementation
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_crypto_cmn.h"
+#include "nss_crypto_cmn_strings.h"
+#include "nss_crypto_cmn_stats.h"
+#include "nss_crypto_cmn_log.h"
+
+/*
+ * Amount time the synchronous message should wait for response from
+ * NSS before the timeout happens. After the timeout the message
+ * response even if it arrives has to be discarded. Typically, the
+ * time needs to be selected based on the worst case time in case of
+ * peak throughput between host & NSS.
+ */
+#define NSS_CRYPTO_CMN_TX_TIMEO_TICKS msecs_to_jiffies(3000) /* milliseconds */
+
+/*
+ * Private data structure to hold state for
+ * the crypto specific NSS interaction
+ */
+struct nss_crypto_cmn_pvt {
+	struct semaphore sem;		/* used for synchronizing 'tx_msg_sync' */
+	struct completion complete;	/* completion callback */
+	atomic_t seq_no;		/* used for tracking tx_msg_sync requests */
+};
+
+/*
+ * This is a single instance applicable for all crypto synchronous
+ * messaging interaction with NSS.
+ */
+static struct nss_crypto_cmn_pvt g_nss_crypto_cmn;
+
+/*
+ * nss_crypto_cmn_msg_handler()
+ *	this handles all the IPsec events and responses
+ */
+static void nss_crypto_cmn_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm,
+					void *app_data __attribute((unused)))
+{
+	struct nss_crypto_cmn_msg *nim = (struct nss_crypto_cmn_msg *)ncm;
+	nss_crypto_cmn_msg_callback_t cb = NULL;
+
+	/*
+	 * Sanity check the message type
+	 */
+	if (ncm->type > NSS_CRYPTO_CMN_MSG_TYPE_MAX) {
+		nss_warning("%px: rx message type out of range: %d", nss_ctx, ncm->type);
+		return;
+	}
+
+	/*
+	 * Check if the message structure length matches that of Host side. In case
+	 * of failure this indicates ether the structure is different or this is not
+	 * the intended interface.
+	 */
+	if (nss_cmn_get_msg_len(ncm) > sizeof(*nim)) {
+		nss_warning("%px: rx message length is invalid: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	if (ncm->response == NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: rx message response for if %d, type %d, is invalid: %d", nss_ctx,
+				ncm->interface, ncm->type, ncm->response);
+		return;
+	}
+
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->crypto_cmn_msg_callback;
+		ncm->app_data = (nss_ptr_t)nss_ctx->nss_top->crypto_ctx;
+	}
+
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Trace messages.
+	 */
+	nss_crypto_cmn_log_rx_msg(nim);
+
+	switch (nim->cm.type) {
+	case NSS_CRYPTO_CMN_MSG_TYPE_SYNC_NODE_STATS:
+	case NSS_CRYPTO_CMN_MSG_TYPE_SYNC_ENG_STATS:
+	case NSS_CRYPTO_CMN_MSG_TYPE_SYNC_CTX_STATS:
+		/*
+		 * Update driver statistics and send statistics
+		 * notification to the registered modules.
+		 */
+		nss_crypto_cmn_stats_sync(nss_ctx, &nim->msg.stats);
+		nss_crypto_cmn_stats_notify(nss_ctx);
+		break;
+	}
+	/*
+	 * Load, Test & call
+	 */
+	cb = (nss_crypto_cmn_msg_callback_t)ncm->cb;
+	if (unlikely(!cb)) {
+		nss_warning("%px: rx handler has been unregistered for i/f: %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb((void *)ncm->app_data, nim);
+}
+
+/*
+ * nss_crypto_cmn_tx_msg
+ *	Send crypto config to NSS.
+ */
+nss_tx_status_t nss_crypto_cmn_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_crypto_cmn_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+	uint16_t msg_len = nss_cmn_get_msg_len(ncm);
+
+	nss_info("%px: tx message %d for if %d", nss_ctx, ncm->type, ncm->interface);
+
+	BUILD_BUG_ON(NSS_NBUF_PAYLOAD_SIZE < sizeof(*msg));
+
+	if (ncm->type > NSS_CRYPTO_CMN_MSG_TYPE_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Check if the message structure length matches the structure length. Otherwise
+	 * the sender accidentally programmed a incorrect length into the message.
+	 */
+	if (msg_len != sizeof(*msg)) {
+		nss_warning("%px: message request len bad: %d", nss_ctx, msg_len);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	nss_trace("%px: msg params version:%d, interface:%d, type:%d, cb:%px, app_data:%px, len:%d",
+			nss_ctx, ncm->version, ncm->interface, ncm->type,
+			(void *)ncm->cb, (void *)ncm->app_data, ncm->len);
+
+	/*
+	 * Trace messages.
+	 */
+	nss_crypto_cmn_log_tx_msg(msg);
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_crypto_cmn_tx_msg);
+
+/*
+ * nss_crypto_cmn_tx_msg_cb()
+ *	Callback to handle the synchronous completion of messages.
+ */
+static void nss_crypto_cmn_tx_msg_cb(void *app_data, struct nss_crypto_cmn_msg *nim)
+{
+	struct nss_crypto_cmn_pvt *pvt = &g_nss_crypto_cmn;
+	struct nss_crypto_cmn_msg *resp = (struct nss_crypto_cmn_msg *)nim->cm.app_data;
+
+	/*
+	 * Only update the message structure if the sequence no. matches
+	 * Otherwise, a timeout might have happened in between and we
+	 * are probably receiving the completion for an older message
+	 */
+	if (atomic_read(&pvt->seq_no) == nim->seq_num) {
+		memcpy(resp, nim, sizeof(struct nss_crypto_cmn_msg));
+		complete(&pvt->complete);
+	}
+}
+
+/*
+ * nss_crypto_cmn_tx_msg_sync()
+ *	Transmit a crypto message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_crypto_cmn_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_crypto_cmn_msg *msg)
+{
+	struct nss_crypto_cmn_pvt *pvt = &g_nss_crypto_cmn;
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&pvt->sem);
+	atomic_inc(&pvt->seq_no);
+
+	/*
+	 * this is a synchronous message; overload the callback
+	 * and app_data
+	 */
+	msg->cm.cb = (nss_ptr_t)nss_crypto_cmn_tx_msg_cb;
+	msg->cm.app_data = (nss_ptr_t)msg;
+	msg->seq_num = atomic_read(&pvt->seq_no);
+
+	status = nss_crypto_cmn_tx_msg(nss_ctx, msg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: tx_msg failed", nss_ctx);
+		up(&pvt->sem);
+		return status;
+	}
+
+	/*
+	 * Note: This cannot be called in atomic context
+	 */
+	ret = wait_for_completion_timeout(&pvt->complete, NSS_CRYPTO_CMN_TX_TIMEO_TICKS);
+	if (!ret) {
+		atomic_inc(&pvt->seq_no);
+		nss_warning("%px: tx_msg_sync timed out", nss_ctx);
+		up(&pvt->sem);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * This ensures that the even if the response arrives on a different
+	 * CPU core the data copied by the response callback will be visible
+	 * to the caller which is sleeping for it on a different core. For
+	 * further details read Linux/Documentation/memory-barrier.txt
+	 */
+	smp_rmb();
+	up(&pvt->sem);
+
+	return NSS_TX_SUCCESS;
+}
+EXPORT_SYMBOL(nss_crypto_cmn_tx_msg_sync);
+
+/*
+ * nss_crypto_cmn_tx_buf()
+ *	NSS crypto TX data API. Sends a crypto buffer to NSS.
+ */
+nss_tx_status_t nss_crypto_cmn_tx_buf(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+					struct sk_buff *skb)
+{
+	int32_t status;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	if (unlikely(nss_ctx->state != NSS_CORE_STATE_INITIALIZED)) {
+		nss_warning("%px: tx_data packet dropped as core not ready", nss_ctx);
+		return NSS_TX_FAILURE_NOT_READY;
+	}
+
+	status = nss_core_send_packet(nss_ctx, skb, if_num, H2N_BIT_FLAG_BUFFER_REUSABLE);
+	switch (status) {
+	case NSS_CORE_STATUS_SUCCESS:
+		break;
+
+	case NSS_CORE_STATUS_FAILURE_QUEUE: /* queue full condition */
+		nss_warning("%px: H2N queue full for tx_buf", nss_ctx);
+		return NSS_TX_FAILURE_QUEUE;
+
+	default:
+		nss_warning("%px: general failure for tx_buf", nss_ctx);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Kick the NSS awake so it can process our new entry.
+	 */
+	nss_hal_send_interrupt(nss_ctx, NSS_H2N_INTR_DATA_COMMAND_QUEUE);
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_CRYPTO_REQ]);
+
+	return NSS_TX_SUCCESS;
+}
+EXPORT_SYMBOL(nss_crypto_cmn_tx_buf);
+
+/*
+ * nss_crypto_cmn_notify_register()
+ *	register message notifier for crypto interface
+ */
+struct nss_ctx_instance *nss_crypto_cmn_notify_register(nss_crypto_cmn_msg_callback_t cb, void *app_data)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[nss_top->crypto_handler_id];
+
+	nss_top->crypto_ctx = app_data;
+	nss_top->crypto_cmn_msg_callback = cb;
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_crypto_cmn_notify_register);
+
+/*
+ * nss_crypto_cmn_notify_unregister()
+ *	De-register the message notifier for crypto interface
+ */
+void nss_crypto_cmn_notify_unregister(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+
+	nss_top->crypto_ctx = NULL;
+	nss_top->crypto_cmn_msg_callback = NULL;
+}
+EXPORT_SYMBOL(nss_crypto_cmn_notify_unregister);
+
+/*
+ * nss_crypto_cmn_data_register()
+ *	Register the data callback routine
+ */
+struct nss_ctx_instance *nss_crypto_cmn_data_register(uint32_t if_num, nss_crypto_cmn_buf_callback_t cb,
+		struct net_device *netdev, uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx;
+
+	nss_ctx = &nss_top_main.nss[nss_top_main.crypto_handler_id];
+
+	if (if_num < NSS_SPECIAL_IF_START) {
+		nss_warning("%px: interface number is not special interface %d", nss_ctx, if_num);
+		return NULL;
+	}
+
+	/*
+	 * avoid multiple registration for same interface number
+	 */
+	if (nss_ctx->subsys_dp_register[if_num].cb)
+		return nss_ctx;
+
+	/*
+	 * Note: no locking is required for updating this as
+	 * the registration is only a module load time operation.
+	 */
+	nss_core_register_subsys_dp(nss_ctx, if_num, cb, NULL, NULL, netdev, features);
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_crypto_cmn_data_register);
+
+/*
+ * nss_crypto_cmn_data_unregister()
+ *	De-register the data callback routine
+ */
+void nss_crypto_cmn_data_unregister(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	if (if_num < NSS_SPECIAL_IF_START) {
+		nss_warning("%px: interface number is not special interface %d", nss_ctx, if_num);
+		return;
+	}
+
+	/*
+	 * Note: no locking is required for updating this as
+	 * the registration is only a module load time operation.
+	 */
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_crypto_cmn_data_unregister);
+
+/*
+ * nss_crypto_cmn_get_context()
+ *	get NSS context instance for crypto handle
+ */
+struct nss_ctx_instance *nss_crypto_cmn_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.crypto_handler_id];
+}
+EXPORT_SYMBOL(nss_crypto_cmn_get_context);
+
+/*
+ * nss_crypto_cmn_register_handler()
+ */
+void nss_crypto_cmn_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_crypto_cmn_get_context();
+
+	sema_init(&g_nss_crypto_cmn.sem, 1);
+	init_completion(&g_nss_crypto_cmn.complete);
+	nss_core_register_handler(nss_ctx, NSS_CRYPTO_CMN_INTERFACE, nss_crypto_cmn_msg_handler, NULL);
+
+	nss_crypto_cmn_stats_dentry_create();
+	nss_crypto_cmn_strings_dentry_create();
+}
+
+/*
+ * nss_crypto_cmn_msg_init()
+ *	Initialize crypto message
+ */
+void nss_crypto_cmn_msg_init(struct nss_crypto_cmn_msg *ncm, uint16_t if_num, uint32_t type,
+			uint32_t len, nss_crypto_cmn_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, (void *)cb, app_data);
+}
+EXPORT_SYMBOL(nss_crypto_cmn_msg_init);
diff --git a/qca-nss-drv/nss_crypto_cmn_log.c b/qca-nss-drv/nss_crypto_cmn_log.c
new file mode 100644
index 0000000..04cd66c
--- /dev/null
+++ b/qca-nss-drv/nss_crypto_cmn_log.c
@@ -0,0 +1,210 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_crypto_cmn_log.c
+ *	NSS Crypto Common logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_crypto_cmn_log_message_types_str
+ *	Crypto Common message strings
+ */
+static int8_t *nss_crypto_cmn_log_message_types_str[NSS_CRYPTO_CMN_MSG_TYPE_MAX] __maybe_unused = {
+	"Crypto Common Invalid Message",
+	"Crypto Common CRYPTO CMN Initialize Node",
+	"Crypto Common Initialize Engine",
+	"Crypto Common Initialize DMA Pair",
+	"Crypto Common Update Context Information",
+	"Crypto Common Clear Context Information",
+	"Crypto Common Verify Context Active",
+	"Crypto Common Synchronous Node Statistics"
+	"Crypto Common Synchronouts Engine Statistics",
+	"Crypto Common Synchronous Context Statistics"
+};
+
+/*
+ * nss_crypto_cmn_log_error_response_types_str
+ *	Strings for error types for crypto common messages
+ */
+static int8_t *nss_crypto_cmn_log_error_response_types_str[NSS_CRYPTO_CMN_MSG_ERROR_MAX] __maybe_unused = {
+	"Crypto Common No Error",
+	"Crypto Common Header Version Not Supported",
+	"Crypto Common Context Index out-of-range for node",
+	"Crypto Common DMA mask out-of-range",
+	"Crypto Common DMA count exceeds Token",
+	"Crypto Common Token Allocation failed",
+	"Crypto Common Context Index out-of-range",
+	"Crypto Common Context has references",
+	"Crypto Common Bad Context Size",
+	"Crypto Common Bad Algorithm",
+	"Crypto Common Context Allocation failed",
+	"Crypto Common Context has no references",
+	"Crypto Common Invalid Context Flags"
+};
+
+/*
+ * nss_crypto_cmn_node_msg()
+ *	Log NSS crypto common node message.
+ */
+static void nss_crypto_cmn_node_msg(struct nss_crypto_cmn_msg *ncm)
+{
+	struct nss_crypto_cmn_node *ncnm __maybe_unused = &ncm->msg.node;
+	nss_trace("%px: NSS crypto common node message:\n"
+		"Crypto Common Max DMA Rings: %d\n"
+		"Crypto Common Max Contex: %d\n"
+		"Crypto Common Max Context Size: %d\n",
+		ncnm, ncnm->max_dma_rings,
+		ncnm->max_ctx, ncnm->max_ctx_size);
+}
+
+/*
+ * nss_crypto_cmn_engine_msg()
+ *	Log NSS crypto cmn engine message.
+ */
+static void nss_crypto_cmn_engine_msg(struct nss_crypto_cmn_msg *ncm)
+{
+	struct nss_crypto_cmn_engine *ncem __maybe_unused = &ncm->msg.eng;
+	nss_trace("%px: NSS crypto common engine message \n"
+		"Crypto Common Firmware Version: %px\n"
+		"Crypto Common DMA Mask: %x\n"
+		"Crypto Common Token Count: %d\n",
+		ncem, &ncem->fw_ver,
+		ncem->dma_mask, ncem->req_count);
+}
+
+/*
+ * nss_crypto_cmn_dma_msg()
+ *	Log NSS crypto cmn dma message.
+ */
+static void nss_crypto_cmn_dma_msg(struct nss_crypto_cmn_msg *ncm)
+{
+	struct nss_crypto_cmn_dma *ncdm __maybe_unused = &ncm->msg.dma;
+	nss_trace("%px: NSS crypto common dma message \n"
+		"Crypto Common DMA Pair ID: %d\n",
+		ncdm, ncdm->pair_id);
+}
+
+/*
+ * nss_crypto_cmn_ctx_msg()
+ *	Log NSS crypto cmn context message.
+ */
+static void nss_crypto_cmn_ctx_msg(struct nss_crypto_cmn_msg *ncm)
+{
+	struct nss_crypto_cmn_ctx *nccm __maybe_unused = &ncm->msg.ctx;
+	nss_trace("%px: NSS crypto common context message \n"
+		"Crypto Common Context Spare Words: %px\n"
+		"Crypto Common Index: %d\n"
+		"Crypto Common Secure Offset: %d\n"
+		"Crypto Common Cipher Key: %px\n"
+		"Crypto Common Authorization Key: %px\n"
+		"Crypto Common Nonce Value: %px\n"
+		"Crypto Common Algorithm: %x\n"
+		"Crypto Common Context Specific Flags: %x\n",
+		nccm, &nccm->spare,
+		nccm->index, nccm->sec_offset,
+		&nccm->cipher_key, &nccm->auth_key,
+		&nccm->nonce, nccm->algo, nccm->flags);
+}
+
+/*
+ * nss_crypto_cmn_log_verbose()
+ *	Log message contents.
+ */
+static void nss_crypto_cmn_log_verbose(struct nss_crypto_cmn_msg *ncm)
+{
+	switch (ncm->cm.type) {
+	case NSS_CRYPTO_CMN_MSG_TYPE_SETUP_NODE:
+		nss_crypto_cmn_node_msg(ncm);
+		break;
+
+	case NSS_CRYPTO_CMN_MSG_TYPE_SETUP_ENG:
+		nss_crypto_cmn_engine_msg(ncm);
+		break;
+
+	case NSS_CRYPTO_CMN_MSG_TYPE_SETUP_DMA:
+		nss_crypto_cmn_dma_msg(ncm);
+		break;
+
+	case NSS_CRYPTO_CMN_MSG_TYPE_SETUP_CTX:
+	case NSS_CRYPTO_CMN_MSG_TYPE_CLEAR_CTX:
+	case NSS_CRYPTO_CMN_MSG_TYPE_VERIFY_CTX:
+		nss_crypto_cmn_ctx_msg(ncm);
+		break;
+
+	case NSS_CRYPTO_CMN_MSG_TYPE_SYNC_NODE_STATS:
+	case NSS_CRYPTO_CMN_MSG_TYPE_SYNC_ENG_STATS:
+	case NSS_CRYPTO_CMN_MSG_TYPE_SYNC_CTX_STATS:
+		/* Getting logged in stats */
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", ncm);
+		break;
+	}
+}
+
+/*
+ * nss_crypto_cmn_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_crypto_cmn_log_tx_msg(struct nss_crypto_cmn_msg *ncm)
+{
+	if (ncm->cm.type >= NSS_CRYPTO_CMN_MSG_TYPE_MAX) {
+		nss_warning("%px: Invalid message type\n", ncm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ncm, ncm->cm.type, nss_crypto_cmn_log_message_types_str[ncm->cm.type]);
+	nss_crypto_cmn_log_verbose(ncm);
+}
+
+/*
+ * nss_crypto_cmn_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_crypto_cmn_log_rx_msg(struct nss_crypto_cmn_msg *ncm)
+{
+	if (ncm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ncm);
+		return;
+	}
+
+	if (ncm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ncm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ncm, ncm->cm.type,
+			nss_crypto_cmn_log_message_types_str[ncm->cm.type],
+			ncm->cm.response, nss_cmn_response_str[ncm->cm.response]);
+		goto verbose;
+	}
+
+	if (ncm->cm.error >= NSS_CRYPTO_CMN_MSG_ERROR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			ncm, ncm->cm.type, nss_crypto_cmn_log_message_types_str[ncm->cm.type],
+			ncm->cm.response, nss_cmn_response_str[ncm->cm.response],
+			ncm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		ncm, ncm->cm.type, nss_crypto_cmn_log_message_types_str[ncm->cm.type],
+		ncm->cm.response, nss_cmn_response_str[ncm->cm.response],
+		ncm->cm.error, nss_crypto_cmn_log_error_response_types_str[ncm->cm.error]);
+
+verbose:
+	nss_crypto_cmn_log_verbose(ncm);
+}
diff --git a/qca-nss-drv/nss_crypto_cmn_log.h b/qca-nss-drv/nss_crypto_cmn_log.h
new file mode 100644
index 0000000..f78a8ec
--- /dev/null
+++ b/qca-nss-drv/nss_crypto_cmn_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_CRYPTO_CMN_LOG_H__
+#define __NSS_CRYPTO_CMN_LOG_H__
+
+/*
+ * nss_crypto_cmn_log.h
+ *	NSS Crypto Common Log header file.
+ */
+
+/*
+ * nss_crypto_cmn_log_tx_msg
+ *	Logs a crypto common message that is sent to the NSS firmware.
+ */
+void nss_crypto_cmn_log_tx_msg(struct nss_crypto_cmn_msg *ncm);
+
+/*
+ * nss_crypto_cmn_log_rx_msg
+ *	Logs a crypto common message that is received from the NSS firmware.
+ */
+void nss_crypto_cmn_log_rx_msg(struct nss_crypto_cmn_msg *ncm);
+
+#endif /* __NSS_CRYPTO_CMN_LOG_H__ */
diff --git a/qca-nss-drv/nss_crypto_cmn_stats.c b/qca-nss-drv/nss_crypto_cmn_stats.c
new file mode 100644
index 0000000..c304166
--- /dev/null
+++ b/qca-nss-drv/nss_crypto_cmn_stats.c
@@ -0,0 +1,166 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_crypto_cmn_stats.h"
+#include "nss_crypto_cmn_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_crypto_cmn_stats_notifier);
+
+/*
+ * Spinlock to protect CRYPTO_CMN statistics update/read
+ */
+DEFINE_SPINLOCK(nss_crypto_cmn_stats_lock);
+
+/*
+ * nss_crypto_cmn_stats
+ *	crypto common statistics
+ */
+uint64_t nss_crypto_cmn_stats[NSS_CRYPTO_CMN_STATS_MAX];
+
+/*
+ * nss_crypto_cmn_stats_read()
+ *	Read crypto common statistics
+ */
+static ssize_t nss_crypto_cmn_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * Max output lines = #stats +
+	 * few blank lines for banner printing + Number of Extra outputlines
+	 * for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_CRYPTO_CMN_STATS_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = vzalloc(size_al);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return -ENOMEM;
+	}
+
+	stats_shadow = vzalloc(NSS_CRYPTO_CMN_STATS_MAX * 8);
+	if (unlikely(!stats_shadow)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		vfree(lbuf);
+		return -ENOMEM;
+	}
+
+	/*
+	 * crypto common statistics
+	 */
+	spin_lock_bh(&nss_crypto_cmn_stats_lock);
+	for (i = 0; i < NSS_CRYPTO_CMN_STATS_MAX; i++)
+		stats_shadow[i] = nss_crypto_cmn_stats[i];
+
+	spin_unlock_bh(&nss_crypto_cmn_stats_lock);
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "crypto_cmn", NSS_STATS_SINGLE_CORE);
+	size_wr += nss_stats_print("crypto_cmn", NULL, NSS_STATS_SINGLE_INSTANCE, nss_crypto_cmn_strings_stats,
+					stats_shadow, NSS_CRYPTO_CMN_STATS_MAX, lbuf, size_wr, size_al);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	vfree(lbuf);
+	vfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_crypto_cmn_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(crypto_cmn);
+
+/*
+ * nss_crypto_cmn_stats_dentry_create()
+ *	Create crypto common statistics debug entry.
+ */
+void nss_crypto_cmn_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("crypto_cmn", &nss_crypto_cmn_stats_ops);
+}
+
+/*
+ * nss_crypto_cmn_stats_sync()
+ *	Handle the syncing of NSS crypto common statistics.
+ */
+void nss_crypto_cmn_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_crypto_cmn_stats *nct)
+{
+	int j;
+
+	spin_lock_bh(&nss_crypto_cmn_stats_lock);
+
+	/*
+	 * Common node stats
+	 */
+	nss_crypto_cmn_stats[NSS_STATS_NODE_RX_PKTS] += nct->nstats.rx_packets;
+	nss_crypto_cmn_stats[NSS_STATS_NODE_RX_BYTES] += nct->nstats.rx_bytes;
+	nss_crypto_cmn_stats[NSS_STATS_NODE_TX_PKTS] += nct->nstats.tx_packets;
+	nss_crypto_cmn_stats[NSS_STATS_NODE_TX_BYTES] += nct->nstats.tx_bytes;
+
+	for (j = 0; j < NSS_MAX_NUM_PRI; j++)
+		nss_crypto_cmn_stats[NSS_STATS_NODE_RX_QUEUE_0_DROPPED + j] += nct->nstats.rx_dropped[j];
+
+	/*
+	 * crypto common statistics
+	 */
+	nss_crypto_cmn_stats[NSS_CRYPTO_CMN_STATS_FAIL_VERSION] += nct->fail_version;
+	nss_crypto_cmn_stats[NSS_CRYPTO_CMN_STATS_FAIL_CTX] += nct->fail_ctx;
+	nss_crypto_cmn_stats[NSS_CRYPTO_CMN_STATS_FAIL_DMA] += nct->fail_dma;
+
+	spin_unlock_bh(&nss_crypto_cmn_stats_lock);
+}
+
+/*
+ * nss_crypto_cmn_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_crypto_cmn_stats_notify(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_crypto_cmn_stats_notification crypto_cmn_stats;
+
+	crypto_cmn_stats.core_id = nss_ctx->id;
+	memcpy(crypto_cmn_stats.stats, nss_crypto_cmn_stats, sizeof(crypto_cmn_stats.stats));
+	atomic_notifier_call_chain(&nss_crypto_cmn_stats_notifier, NSS_STATS_EVENT_NOTIFY, &crypto_cmn_stats);
+}
+
+/*
+ * nss_crypto_cmn_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_crypto_cmn_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_crypto_cmn_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_crypto_cmn_stats_register_notifier);
+
+/*
+ * nss_crypto_cmn_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_crypto_cmn_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_crypto_cmn_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_crypto_cmn_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_crypto_cmn_stats.h b/qca-nss-drv/nss_crypto_cmn_stats.h
new file mode 100644
index 0000000..6319c2c
--- /dev/null
+++ b/qca-nss-drv/nss_crypto_cmn_stats.h
@@ -0,0 +1,77 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_CRYPTO_CMN_STATS_H
+#define __NSS_CRYPTO_CMN_STATS_H
+
+#include <nss_cmn.h>
+
+/**
+ * nss_crypto_cmn_stats_types
+ *	crypto common transmission node statistics
+ */
+enum nss_crypto_cmn_stats_types {
+	NSS_CRYPTO_CMN_STATS_FAIL_VERSION = NSS_STATS_NODE_MAX,	/* version mismatch failures */
+	NSS_CRYPTO_CMN_STATS_FAIL_CTX,				/* context related failures */
+	NSS_CRYPTO_CMN_STATS_FAIL_DMA,				/* dma descriptor full */
+	NSS_CRYPTO_CMN_STATS_MAX,				/* Maximum message type */
+};
+
+/**
+ * nss_crypto_cmn_stats_notification
+ *	crypto common transmission statistics structure
+ */
+struct nss_crypto_cmn_stats_notification {
+	uint32_t core_id;				/* core ID */
+	uint64_t stats[NSS_CRYPTO_CMN_STATS_MAX];	/* transmission statistics */
+};
+
+/*
+ * crypto common statistics APIs
+ */
+extern void nss_crypto_cmn_stats_notify(struct nss_ctx_instance *nss_ctx);
+extern void nss_crypto_cmn_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_crypto_cmn_stats *nct);
+extern void nss_crypto_cmn_stats_dentry_create(void);
+
+/**
+ * nss_crypto_cmn_stats_register_notifier
+ *	Registers a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_crypto_cmn_stats_register_notifier(struct notifier_block *nb);
+
+/**
+ * nss_crypto_cmn_stats_unregister_notifier
+ *	Deregisters a statistics notifier.
+ *
+ * @datatypes
+ * notifier_block
+ *
+ * @param[in] nb Notifier block.
+ *
+ * @return
+ * 0 on success or -2 on failure.
+ */
+extern int nss_crypto_cmn_stats_unregister_notifier(struct notifier_block *nb);
+
+#endif /* __NSS_CRYPTO_CMN_STATS_H */
diff --git a/qca-nss-drv/nss_crypto_cmn_strings.c b/qca-nss-drv/nss_crypto_cmn_strings.c
new file mode 100644
index 0000000..42e8d8b
--- /dev/null
+++ b/qca-nss-drv/nss_crypto_cmn_strings.c
@@ -0,0 +1,61 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_crypto_cmn_strings.h"
+
+/*
+ * nss_crypto_cmn_strings_stats
+ *	crypto common statistics strings.
+ */
+struct nss_stats_info nss_crypto_cmn_strings_stats[NSS_CRYPTO_CMN_STATS_MAX] = {
+	{"rx_pkts",		NSS_STATS_TYPE_COMMON},
+	{"rx_byts",		NSS_STATS_TYPE_COMMON},
+	{"tx_pkts",		NSS_STATS_TYPE_COMMON},
+	{"tx_byts",		NSS_STATS_TYPE_COMMON},
+	{"rx_queue[0]_drops",	NSS_STATS_TYPE_DROP},
+	{"rx_queue[1]_drops",	NSS_STATS_TYPE_DROP},
+	{"rx_queue[2]_drops",	NSS_STATS_TYPE_DROP},
+	{"rx_queue[3]_drops",	NSS_STATS_TYPE_DROP},
+	{"fail_version",	NSS_STATS_TYPE_SPECIAL},
+	{"fail_ctx",		NSS_STATS_TYPE_SPECIAL},
+	{"fail_dma",		NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_crypto_cmn_strings_read()
+ *	Read crypto common node statistics names
+ */
+static ssize_t nss_crypto_cmn_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_crypto_cmn_strings_stats, NSS_CRYPTO_CMN_STATS_MAX);
+}
+
+/*
+ * nss_crypto_cmn_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(crypto_cmn);
+
+/*
+ * nss_crypto_cmn_strings_dentry_create()
+ *	Create crypto common statistics strings debug entry.
+ */
+void nss_crypto_cmn_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("crypto_cmn", &nss_crypto_cmn_strings_ops);
+}
diff --git a/qca-nss-drv/nss_crypto_cmn_strings.h b/qca-nss-drv/nss_crypto_cmn_strings.h
new file mode 100644
index 0000000..aae0677
--- /dev/null
+++ b/qca-nss-drv/nss_crypto_cmn_strings.h
@@ -0,0 +1,25 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_CRYPTO_CMN_STRINGS_H
+#define __NSS_CRYPTO_CMN_STRINGS_H
+
+#include "nss_crypto_cmn_stats.h"
+
+extern struct nss_stats_info nss_crypto_cmn_strings_stats[NSS_CRYPTO_CMN_STATS_MAX];
+extern void nss_crypto_cmn_strings_dentry_create(void);
+
+#endif /* __NSS_CRYPTO_CMN_STRINGS_H */
diff --git a/qca-nss-drv/nss_crypto_log.c b/qca-nss-drv/nss_crypto_log.c
new file mode 100644
index 0000000..b556997
--- /dev/null
+++ b/qca-nss-drv/nss_crypto_log.c
@@ -0,0 +1,151 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_crypto_log.c
+ *	NSS Crypto logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_crypto_log_message_types_str
+ *	Crypto message strings
+ */
+static int8_t *nss_crypto_log_message_types_str[NSS_CRYPTO_MSG_TYPE_MAX] __maybe_unused = {
+	"Crypto Invalid Message",
+	"Crypto Open Engine Message",
+	"Crypto Close Engine Message",
+	"Crypto Update Session",
+	"Crypto Stats Sync",
+};
+
+/*
+ * nss_crypto_log_error_response_types_str
+ *	Strings for error types for CRYPTO messages
+ */
+static int8_t *nss_crypto_log_error_response_types_str[NSS_CRYPTO_MSG_ERROR_MAX] __maybe_unused = {
+	"Crypto No Error",
+	"Crypto Invalid Engine",
+	"Crypto Unsupported Operation",
+	"Crypto Invalid Operation",
+	"Crypto Invalid Index Range",
+	"Crypto Index Alloc Failure",
+};
+
+/*
+ * nss_crypto_config_eng_msg()
+ *	Log NSS Crypto config engine message.
+ */
+static void nss_crypto_config_eng_msg(struct nss_crypto_msg *ncm)
+{
+	struct nss_crypto_config_eng *nccem __maybe_unused = &ncm->msg.eng;
+	nss_trace("%px: NSS Crypto Config Engine Message:\n"
+		"Crypto Engine Number: %d\n"
+		"Crypto BAM Physical Base Address: %x\n"
+		"Crypto Physical Base Address: %x\n"
+		"Crypto Pipe Description Address: %px\n"
+		"Crypto Session Indices: %px\n",
+		nccem, nccem->eng_id,
+		nccem->bam_pbase, nccem->crypto_pbase,
+		&nccem->desc_paddr, &nccem->idx);
+}
+
+/*
+ * nss_crypto_config_session_msg()
+ *	Log NSS Crypto config session message.
+ */
+static void nss_crypto_config_session_msg(struct nss_crypto_msg *ncm)
+{
+	struct nss_crypto_config_session *nccsm __maybe_unused = &ncm->msg.session;
+	nss_trace("%px: NSS Crypto Config Session message \n"
+		"Crypto Session Index: %d\n"
+		"Crypto Session State: %d\n"
+		"Crypto Session Initialization Vector Length: %d\n",
+		nccsm, nccsm->idx,
+		nccsm->state, nccsm->iv_len);
+}
+
+/*
+ * nss_crypto_log_verbose()
+ *	Log message contents.
+ */
+static void nss_crypto_log_verbose(struct nss_crypto_msg *ncm)
+{
+	switch (ncm->cm.type) {
+	case NSS_CRYPTO_MSG_TYPE_OPEN_ENG:
+		nss_crypto_config_eng_msg(ncm);
+		break;
+
+	case NSS_CRYPTO_MSG_TYPE_UPDATE_SESSION:
+		nss_crypto_config_session_msg(ncm);
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", ncm);
+		break;
+	}
+}
+
+/*
+ * nss_crypto_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_crypto_log_tx_msg(struct nss_crypto_msg *ncm)
+{
+	if (ncm->cm.type >= NSS_CRYPTO_MSG_TYPE_MAX) {
+		nss_warning("%px: Invalid message type\n", ncm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ncm, ncm->cm.type, nss_crypto_log_message_types_str[ncm->cm.type]);
+	nss_crypto_log_verbose(ncm);
+}
+
+/*
+ * nss_crypto_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_crypto_log_rx_msg(struct nss_crypto_msg *ncm)
+{
+	if (ncm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ncm);
+		return;
+	}
+
+	if (ncm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ncm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ncm, ncm->cm.type,
+			nss_crypto_log_message_types_str[ncm->cm.type],
+			ncm->cm.response, nss_cmn_response_str[ncm->cm.response]);
+		goto verbose;
+	}
+
+	if (ncm->cm.error >= NSS_CRYPTO_MSG_ERROR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			ncm, ncm->cm.type, nss_crypto_log_message_types_str[ncm->cm.type],
+			ncm->cm.response, nss_cmn_response_str[ncm->cm.response],
+			ncm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		ncm, ncm->cm.type, nss_crypto_log_message_types_str[ncm->cm.type],
+		ncm->cm.response, nss_cmn_response_str[ncm->cm.response],
+		ncm->cm.error, nss_crypto_log_error_response_types_str[ncm->cm.error]);
+
+verbose:
+	nss_crypto_log_verbose(ncm);
+}
diff --git a/qca-nss-drv/nss_crypto_log.h b/qca-nss-drv/nss_crypto_log.h
new file mode 100644
index 0000000..c0d53dd
--- /dev/null
+++ b/qca-nss-drv/nss_crypto_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_CRYPTO_LOG_H__
+#define __NSS_CRYPTO_LOG_H__
+
+/*
+ * nss_crypto_log.h
+ *	NSS Crypto Log Header File
+ */
+
+/*
+ * nss_crypto_log_tx_msg
+ *	Logs a crypto message that is sent to the NSS firmware.
+ */
+void nss_crypto_log_tx_msg(struct nss_crypto_msg *ncm);
+
+/*
+ * nss_crypto_log_rx_msg
+ *	Logs a crypto message that is received from the NSS firmware.
+ */
+void nss_crypto_log_rx_msg(struct nss_crypto_msg *ncm);
+
+#endif /* __NSS_CRYPTO_LOG_H__ */
diff --git a/qca-nss-drv/nss_data_plane/hal/include/nss_data_plane_hal.h b/qca-nss-drv/nss_data_plane/hal/include/nss_data_plane_hal.h
new file mode 100644
index 0000000..aa46ead
--- /dev/null
+++ b/qca-nss-drv/nss_data_plane/hal/include/nss_data_plane_hal.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "nss_phys_if.h"
+#include <nss_dp_api_if.h>
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+#define NSS_DATA_PLANE_SUPPORTED_FEATURES (NETIF_F_HIGHDMA \
+					| NETIF_F_HW_CSUM \
+					| NETIF_F_RXCSUM \
+					| NETIF_F_SG \
+					| NETIF_F_FRAGLIST \
+					| (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_UFO))
+#else
+#define NSS_DATA_PLANE_SUPPORTED_FEATURES (NETIF_F_HIGHDMA \
+					| NETIF_F_HW_CSUM \
+					| NETIF_F_RXCSUM \
+					| NETIF_F_SG \
+					| NETIF_F_FRAGLIST \
+					| (NETIF_F_TSO | NETIF_F_TSO6))
+#endif
+
+/*
+ * nss_data_plane_param
+ */
+struct nss_data_plane_param {
+	struct nss_dp_data_plane_ctx dpc;	/* data plane ctx base class */
+	int if_num;				/* physical interface number */
+	struct nss_ctx_instance *nss_ctx;	/* which nss core */
+	struct nss_dp_gmac_stats gmac_stats;	/* SoC specific stats for GMAC */
+	int notify_open;			/* This data plane interface has been opened or not */
+	uint32_t features;			/* skb types supported by this interface */
+	uint32_t bypass_nw_process;		/* Do we want to bypass NW processing in NSS for this data plane? */
+};
+
+void nss_data_plane_hal_add_dp_ops(struct nss_dp_data_plane_ops *dp_ops);
+void nss_data_plane_hal_register(struct nss_ctx_instance *nss_ctx);
+void nss_data_plane_hal_unregister(struct nss_ctx_instance *nss_ctx);
+void nss_data_plane_hal_set_features(struct nss_dp_data_plane_ctx *dpc);
+uint16_t nss_data_plane_hal_get_mtu_sz(uint16_t mtu);
+void nss_data_plane_hal_stats_sync(struct nss_data_plane_param *ndpp, struct nss_phys_if_stats *stats);
diff --git a/qca-nss-drv/nss_data_plane/hal/nss_ipq50xx.c b/qca-nss-drv/nss_data_plane/hal/nss_ipq50xx.c
new file mode 100644
index 0000000..7e4ae9d
--- /dev/null
+++ b/qca-nss-drv/nss_data_plane/hal/nss_ipq50xx.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "nss_core.h"
+#include "nss_data_plane_hal.h"
+
+static DEFINE_SPINLOCK(nss_data_plane_hal_gmac_stats_lock);
+
+/*
+ * nss_data_plane_hal_get_stats()
+ *	Called by nss-dp to get GMAC stats
+ */
+static void nss_data_plane_hal_get_stats(struct nss_dp_data_plane_ctx *dpc,
+					struct nss_dp_gmac_stats *stats)
+{
+	struct nss_data_plane_param *dp = (struct nss_data_plane_param *)dpc;
+
+	spin_lock_bh(&nss_data_plane_hal_gmac_stats_lock);
+	memcpy(stats, &dp->gmac_stats, sizeof(*stats));
+	spin_unlock_bh(&nss_data_plane_hal_gmac_stats_lock);
+}
+
+/*
+ * nss_data_plane_hal_add_dp_ops()
+ */
+void nss_data_plane_hal_add_dp_ops(struct nss_dp_data_plane_ops *dp_ops)
+{
+	dp_ops->get_stats = nss_data_plane_hal_get_stats;
+}
+
+/*
+ * nss_data_plane_hal_register()
+ */
+void nss_data_plane_hal_register(struct nss_ctx_instance *nss_ctx)
+{
+}
+
+/*
+ * nss_data_plane_hal_unregister()
+ */
+void nss_data_plane_hal_unregister(struct nss_ctx_instance *nss_ctx)
+{
+}
+
+/*
+ * nss_data_plane_hal_set_features
+ */
+void nss_data_plane_hal_set_features(struct nss_dp_data_plane_ctx *dpc)
+{
+	dpc->dev->features |= NSS_DATA_PLANE_SUPPORTED_FEATURES;
+	dpc->dev->hw_features |= NSS_DATA_PLANE_SUPPORTED_FEATURES;
+	dpc->dev->wanted_features |= NSS_DATA_PLANE_SUPPORTED_FEATURES;
+
+	/*
+	 * Synopsys GMAC does not support checksum offload for QinQ VLANs.
+	 * Hence, we do not advertise checksum offload support for VLANs.
+	 */
+	dpc->dev->vlan_features |= NSS_DATA_PLANE_SUPPORTED_FEATURES &
+					(~(NETIF_F_RXCSUM | NETIF_F_HW_CSUM));
+}
+
+/*
+ * nss_data_plane_hal_stats_sync()
+ */
+void nss_data_plane_hal_stats_sync(struct nss_data_plane_param *ndpp,
+					struct nss_phys_if_stats *stats)
+{
+	struct nss_dp_hal_gmac_stats *gmac_stats = &ndpp->gmac_stats.stats;
+
+	spin_lock_bh(&nss_data_plane_hal_gmac_stats_lock);
+
+	gmac_stats->rx_bytes += stats->if_stats.rx_bytes;
+	gmac_stats->rx_packets += stats->if_stats.rx_packets;
+	gmac_stats->rx_errors += stats->estats.rx_errors;
+	gmac_stats->rx_receive_errors += stats->estats.rx_receive_errors;
+	gmac_stats->rx_descriptor_errors += stats->estats.rx_descriptor_errors;
+	gmac_stats->rx_late_collision_errors += stats->estats.rx_late_collision_errors;
+	gmac_stats->rx_dribble_bit_errors += stats->estats.rx_dribble_bit_errors;
+	gmac_stats->rx_length_errors += stats->estats.rx_length_errors;
+	gmac_stats->rx_ip_header_errors += stats->estats.rx_ip_header_errors;
+	gmac_stats->rx_ip_payload_errors += stats->estats.rx_ip_payload_errors;
+	gmac_stats->rx_no_buffer_errors += stats->estats.rx_no_buffer_errors;
+	gmac_stats->rx_transport_csum_bypassed += stats->estats.rx_transport_csum_bypassed;
+
+	gmac_stats->tx_bytes += stats->if_stats.tx_bytes;
+	gmac_stats->tx_packets += stats->if_stats.tx_packets;
+	gmac_stats->tx_collisions += stats->estats.tx_collisions;
+	gmac_stats->tx_errors += stats->estats.tx_errors;
+	gmac_stats->tx_jabber_timeout_errors += stats->estats.tx_jabber_timeout_errors;
+	gmac_stats->tx_frame_flushed_errors += stats->estats.tx_frame_flushed_errors;
+	gmac_stats->tx_loss_of_carrier_errors += stats->estats.tx_loss_of_carrier_errors;
+	gmac_stats->tx_no_carrier_errors += stats->estats.tx_no_carrier_errors;
+	gmac_stats->tx_late_collision_errors += stats->estats.tx_late_collision_errors;
+	gmac_stats->tx_excessive_collision_errors += stats->estats.tx_excessive_collision_errors;
+	gmac_stats->tx_excessive_deferral_errors += stats->estats.tx_excessive_deferral_errors;
+	gmac_stats->tx_underflow_errors += stats->estats.tx_underflow_errors;
+	gmac_stats->tx_ip_header_errors += stats->estats.tx_ip_header_errors;
+	gmac_stats->tx_ip_payload_errors += stats->estats.tx_ip_payload_errors;
+	gmac_stats->tx_dropped += stats->estats.tx_dropped;
+
+	gmac_stats->hw_errs[0] += stats->estats.hw_errs[0];
+	gmac_stats->hw_errs[1] += stats->estats.hw_errs[1];
+	gmac_stats->hw_errs[2] += stats->estats.hw_errs[2];
+	gmac_stats->hw_errs[3] += stats->estats.hw_errs[3];
+	gmac_stats->hw_errs[4] += stats->estats.hw_errs[4];
+	gmac_stats->hw_errs[5] += stats->estats.hw_errs[5];
+	gmac_stats->hw_errs[6] += stats->estats.hw_errs[6];
+	gmac_stats->hw_errs[7] += stats->estats.hw_errs[7];
+	gmac_stats->hw_errs[8] += stats->estats.hw_errs[8];
+	gmac_stats->hw_errs[9] += stats->estats.hw_errs[9];
+	gmac_stats->rx_missed += stats->estats.rx_missed;
+
+	gmac_stats->fifo_overflows += stats->estats.fifo_overflows;
+	gmac_stats->rx_scatter_errors += stats->estats.rx_scatter_errors;
+	gmac_stats->tx_ts_create_errors += stats->estats.tx_ts_create_errors;
+	gmac_stats->gmac_total_ticks += stats->estats.gmac_total_ticks;
+	gmac_stats->gmac_worst_case_ticks += stats->estats.gmac_worst_case_ticks;
+	gmac_stats->gmac_iterations += stats->estats.gmac_iterations;
+	gmac_stats->tx_pause_frames += stats->estats.tx_pause_frames;
+	gmac_stats->mmc_rx_overflow_errors += stats->estats.mmc_rx_overflow_errors;
+	gmac_stats->mmc_rx_watchdog_timeout_errors += stats->estats.mmc_rx_watchdog_timeout_errors;
+	gmac_stats->mmc_rx_crc_errors += stats->estats.mmc_rx_crc_errors;
+	gmac_stats->mmc_rx_ip_header_errors += stats->estats.mmc_rx_ip_header_errors;
+	gmac_stats->mmc_rx_octets_g += stats->estats.mmc_rx_octets_g;
+	gmac_stats->mmc_rx_ucast_frames += stats->estats.mmc_rx_ucast_frames;
+	gmac_stats->mmc_rx_bcast_frames += stats->estats.mmc_rx_bcast_frames;
+	gmac_stats->mmc_rx_mcast_frames += stats->estats.mmc_rx_mcast_frames;
+	gmac_stats->mmc_rx_undersize += stats->estats.mmc_rx_undersize;
+	gmac_stats->mmc_rx_oversize += stats->estats.mmc_rx_oversize;
+	gmac_stats->mmc_rx_jabber += stats->estats.mmc_rx_jabber;
+	gmac_stats->mmc_rx_octets_gb += stats->estats.mmc_rx_octets_gb;
+	gmac_stats->mmc_rx_frag_frames_g += stats->estats.mmc_rx_frag_frames_g;
+	gmac_stats->mmc_tx_octets_g += stats->estats.mmc_tx_octets_g;
+	gmac_stats->mmc_tx_ucast_frames += stats->estats.mmc_tx_ucast_frames;
+	gmac_stats->mmc_tx_bcast_frames += stats->estats.mmc_tx_bcast_frames;
+	gmac_stats->mmc_tx_mcast_frames += stats->estats.mmc_tx_mcast_frames;
+	gmac_stats->mmc_tx_deferred += stats->estats.mmc_tx_deferred;
+	gmac_stats->mmc_tx_single_col += stats->estats.mmc_tx_single_col;
+	gmac_stats->mmc_tx_multiple_col += stats->estats.mmc_tx_multiple_col;
+	gmac_stats->mmc_tx_octets_gb += stats->estats.mmc_tx_octets_gb;
+
+	spin_unlock_bh(&nss_data_plane_hal_gmac_stats_lock);
+}
+
+/*
+ * nss_data_plane_hal_get_mtu_sz()
+ */
+uint16_t nss_data_plane_hal_get_mtu_sz(uint16_t mtu)
+{
+	/*
+	 * Return MTU value as is.
+	 */
+	return mtu;
+}
diff --git a/qca-nss-drv/nss_data_plane/hal/nss_ipq60xx.c b/qca-nss-drv/nss_data_plane/hal/nss_ipq60xx.c
new file mode 100644
index 0000000..e10d687
--- /dev/null
+++ b/qca-nss-drv/nss_data_plane/hal/nss_ipq60xx.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "nss_core.h"
+#include "nss_data_plane_hal.h"
+
+/*
+ * nss_data_plane_hal_vsi_assign()
+ *	Called by nss-dp to assign vsi of a data plane
+ */
+static int nss_data_plane_hal_vsi_assign(struct nss_dp_data_plane_ctx *dpc, uint32_t vsi)
+{
+	struct nss_data_plane_param *dp = (struct nss_data_plane_param *)dpc;
+
+	return nss_phys_if_vsi_assign(dp->nss_ctx, vsi, dp->if_num);
+}
+
+/*
+ * nss_data_plane_hal_vsi_unassign()
+ *	Called by nss-dp to unassign vsi of a data plane
+ */
+static int nss_data_plane_hal_vsi_unassign(struct nss_dp_data_plane_ctx *dpc, uint32_t vsi)
+{
+	struct nss_data_plane_param *dp = (struct nss_data_plane_param *)dpc;
+
+	return nss_phys_if_vsi_unassign(dp->nss_ctx, vsi, dp->if_num);
+}
+
+/*
+ * nss_data_plane_hal_add_dp_ops()
+ */
+void nss_data_plane_hal_add_dp_ops(struct nss_dp_data_plane_ops *dp_ops)
+{
+	dp_ops->vsi_assign = nss_data_plane_hal_vsi_assign;
+	dp_ops->vsi_unassign = nss_data_plane_hal_vsi_unassign;
+}
+
+/*
+ * nss_data_plane_hal_register()
+ */
+void nss_data_plane_hal_register(struct nss_ctx_instance *nss_ctx)
+{
+	/*
+	 * Packets with the ptp service code should be delivered to
+	 * PHY driver for timestamping.
+	 */
+	nss_cmn_register_service_code(nss_ctx, nss_phy_tstamp_rx_buf,
+					NSS_PTP_EVENT_SERVICE_CODE, nss_ctx);
+}
+
+/*
+ * nss_data_plane_hal_unregister()
+ */
+void nss_data_plane_hal_unregister(struct nss_ctx_instance *nss_ctx)
+{
+	nss_cmn_unregister_service_code(nss_ctx, nss_phy_tstamp_rx_buf,
+					NSS_PTP_EVENT_SERVICE_CODE);
+}
+
+/*
+ * nss_data_plane_hal_set_features
+ */
+void nss_data_plane_hal_set_features(struct nss_dp_data_plane_ctx *dpc)
+{
+	dpc->dev->features |= NSS_DATA_PLANE_SUPPORTED_FEATURES;
+	dpc->dev->hw_features |= NSS_DATA_PLANE_SUPPORTED_FEATURES;
+	dpc->dev->vlan_features |= NSS_DATA_PLANE_SUPPORTED_FEATURES;
+	dpc->dev->wanted_features |= NSS_DATA_PLANE_SUPPORTED_FEATURES;
+}
+
+/*
+ * nss_data_plane_hal_stats_sync()
+ */
+void nss_data_plane_hal_stats_sync(struct nss_data_plane_param *ndpp,
+					struct nss_phys_if_stats *stats)
+{
+	/*
+	 * EDMA does not pass sync interface stats through phys_if_stats
+	 */
+}
+
+/*
+ * nss_data_plane_hal_get_mtu_sz()
+ */
+uint16_t nss_data_plane_hal_get_mtu_sz(uint16_t mtu)
+{
+	/*
+	 * Reserve space for preheader
+	 */
+	return mtu + NSS_DP_PREHEADER_SIZE;
+}
diff --git a/qca-nss-drv/nss_data_plane/hal/nss_ipq807x.c b/qca-nss-drv/nss_data_plane/hal/nss_ipq807x.c
new file mode 100644
index 0000000..6fe5003
--- /dev/null
+++ b/qca-nss-drv/nss_data_plane/hal/nss_ipq807x.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "nss_core.h"
+#include "nss_data_plane_hal.h"
+
+/*
+ * nss_data_plane_hal_vsi_assign()
+ *	Called by nss-dp to assign vsi of a data plane
+ */
+static int nss_data_plane_hal_vsi_assign(struct nss_dp_data_plane_ctx *dpc, uint32_t vsi)
+{
+	struct nss_data_plane_param *dp = (struct nss_data_plane_param *)dpc;
+
+	return nss_phys_if_vsi_assign(dp->nss_ctx, vsi, dp->if_num);
+}
+
+/*
+ * nss_data_plane_hal_vsi_unassign()
+ *	Called by nss-dp to unassign vsi of a data plane
+ */
+static int nss_data_plane_hal_vsi_unassign(struct nss_dp_data_plane_ctx *dpc, uint32_t vsi)
+{
+	struct nss_data_plane_param *dp = (struct nss_data_plane_param *)dpc;
+
+	return nss_phys_if_vsi_unassign(dp->nss_ctx, vsi, dp->if_num);
+}
+
+/*
+ * nss_data_plane_hal_add_dp_ops()
+ */
+void nss_data_plane_hal_add_dp_ops(struct nss_dp_data_plane_ops *dp_ops)
+{
+	dp_ops->vsi_assign = nss_data_plane_hal_vsi_assign;
+	dp_ops->vsi_unassign = nss_data_plane_hal_vsi_unassign;
+}
+
+/*
+ * nss_data_plane_hal_register()
+ */
+void nss_data_plane_hal_register(struct nss_ctx_instance *nss_ctx)
+{
+	/*
+	 * Packets with the ptp service code should be delivered to
+	 * PHY driver for timestamping.
+	 */
+	nss_cmn_register_service_code(nss_ctx, nss_phy_tstamp_rx_buf,
+					NSS_PTP_EVENT_SERVICE_CODE, nss_ctx);
+}
+
+/*
+ * nss_data_plane_hal_unregister()
+ */
+void nss_data_plane_hal_unregister(struct nss_ctx_instance *nss_ctx)
+{
+	nss_cmn_unregister_service_code(nss_ctx, nss_phy_tstamp_rx_buf,
+					NSS_PTP_EVENT_SERVICE_CODE);
+}
+
+/*
+ * nss_data_plane_hal_set_features
+ */
+void nss_data_plane_hal_set_features(struct nss_dp_data_plane_ctx *dpc)
+{
+	dpc->dev->features |= NSS_DATA_PLANE_SUPPORTED_FEATURES;
+	dpc->dev->hw_features |= NSS_DATA_PLANE_SUPPORTED_FEATURES;
+	dpc->dev->vlan_features |= NSS_DATA_PLANE_SUPPORTED_FEATURES;
+	dpc->dev->wanted_features |= NSS_DATA_PLANE_SUPPORTED_FEATURES;
+}
+
+/*
+ * nss_data_plane_hal_stats_sync()
+ */
+void nss_data_plane_hal_stats_sync(struct nss_data_plane_param *ndpp,
+					struct nss_phys_if_stats *stats)
+{
+	/*
+	 * EDMA does not pass sync interface stats through phys_if_stats
+	 */
+}
+
+/*
+ * nss_data_plane_hal_get_mtu_sz()
+ */
+uint16_t nss_data_plane_hal_get_mtu_sz(uint16_t mtu)
+{
+	/*
+	 * Reserve space for preheader
+	 */
+	return mtu + NSS_DP_PREHEADER_SIZE;
+}
diff --git a/qca-nss-drv/nss_data_plane/include/nss_data_plane.h b/qca-nss-drv/nss_data_plane/include/nss_data_plane.h
new file mode 100644
index 0000000..f20d7fa
--- /dev/null
+++ b/qca-nss-drv/nss_data_plane/include/nss_data_plane.h
@@ -0,0 +1,62 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2017,2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_data_plane
+ *	Data plane used for communication between qca-nss-drv & data plane host
+ */
+
+#ifndef __NSS_DATA_PLANE_H
+#define __NSS_DATA_PLANE_H
+
+#include <nss_api_if.h>
+#include "nss_phys_if.h"
+
+#define NSS_DATA_PLANE_MAX_PACKET_LEN	65535
+
+/*
+ * nss_data_plane_schedule_registration()
+ *	Called from nss_init to schedule a work to do data_plane register to data plane host driver
+ */
+bool nss_data_plane_schedule_registration(void);
+
+/*
+ * nss_data_plane_init_delay_work()
+ *	Initialize data_plane workqueue
+ */
+int nss_data_plane_init_delay_work(void);
+
+/*
+ * nss_data_plane_destroy_delay_work()
+ *	Destroy data_plane workqueue
+ */
+void nss_data_plane_destroy_delay_work(void);
+
+/*
+ * nss_data_plane_ops defines the API required to support multiple data plane targets
+ */
+struct nss_data_plane_ops {
+	void (*data_plane_register)(struct nss_ctx_instance *nss_ctx);
+	void (*data_plane_unregister)(void);
+	void (*data_plane_stats_sync)(struct nss_phys_if_stats *stats, uint16_t interface);
+	uint16_t (*data_plane_get_mtu_sz)(uint16_t max_mtu);
+};
+
+extern struct nss_data_plane_ops nss_data_plane_gmac_ops;
+extern struct nss_data_plane_ops nss_data_plane_ops;
+
+extern int nss_skip_nw_process;
+#endif
diff --git a/qca-nss-drv/nss_data_plane/nss_data_plane.c b/qca-nss-drv/nss_data_plane/nss_data_plane.c
new file mode 100644
index 0000000..cfc9ab3
--- /dev/null
+++ b/qca-nss-drv/nss_data_plane/nss_data_plane.c
@@ -0,0 +1,381 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_data_plane.h"
+#include "nss_core.h"
+#include "nss_tx_rx_common.h"
+#include "nss_data_plane_hal.h"
+
+/*
+ * nss_data_plane_param
+ */
+struct nss_data_plane_param nss_data_plane_params[NSS_DP_MAX_INTERFACES];
+
+/*
+ * __nss_data_plane_init()
+ */
+static int __nss_data_plane_init(struct nss_dp_data_plane_ctx *dpc)
+{
+	struct net_device *netdev = dpc->dev;
+	netdev->needed_headroom += 32;
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * __nss_data_plane_open()
+ *	Called by nss-dp to notify open to nss-fw
+ */
+static int __nss_data_plane_open(struct nss_dp_data_plane_ctx *dpc, uint32_t tx_desc_ring, uint32_t rx_desc_ring, uint32_t mode)
+{
+	struct nss_data_plane_param *dp = (struct nss_data_plane_param *)dpc;
+
+	if (dp->notify_open) {
+		return NSS_DP_SUCCESS;
+	}
+
+	if (nss_phys_if_open(dp->nss_ctx, tx_desc_ring, rx_desc_ring, mode, dp->if_num, dp->bypass_nw_process) == NSS_TX_SUCCESS) {
+		dp->notify_open = 1;
+		return NSS_DP_SUCCESS;
+	}
+	return NSS_DP_FAILURE;
+}
+
+/*
+ * __nss_data_plane_close()
+ *	Called by nss-dp to notify close to nss-fw
+ */
+static int __nss_data_plane_close(struct nss_dp_data_plane_ctx *dpc)
+{
+	struct nss_data_plane_param *dp = (struct nss_data_plane_param *)dpc;
+
+	if (!dp->notify_open) {
+		return NSS_DP_SUCCESS;
+	}
+
+	if (nss_phys_if_close(dp->nss_ctx, dp->if_num) == NSS_TX_SUCCESS) {
+		dp->notify_open = 0;
+		return NSS_DP_SUCCESS;
+	}
+	return NSS_DP_FAILURE;
+}
+
+/*
+ * __nss_data_plane_link_state()
+ *	Called by nss-dp to notify link state change to nss-fw
+ */
+static int __nss_data_plane_link_state(struct nss_dp_data_plane_ctx *dpc, uint32_t link_state)
+{
+	struct nss_data_plane_param *dp = (struct nss_data_plane_param *)dpc;
+
+	return nss_phys_if_link_state(dp->nss_ctx, link_state, dp->if_num);
+}
+
+/*
+ * __nss_data_plane_mac_addr()
+ *	Called by nss-dp to set mac address
+ */
+static int __nss_data_plane_mac_addr(struct nss_dp_data_plane_ctx *dpc, uint8_t *addr)
+{
+	struct nss_data_plane_param *dp = (struct nss_data_plane_param *)dpc;
+
+	return nss_phys_if_mac_addr(dp->nss_ctx, addr, dp->if_num);
+}
+
+/*
+ * __nss_data_plane_change_mtu()
+ *	Called by nss-dp to change mtu of a data plane
+ */
+static int __nss_data_plane_change_mtu(struct nss_dp_data_plane_ctx *dpc, uint32_t mtu)
+{
+	struct nss_data_plane_param *dp = (struct nss_data_plane_param *)dpc;
+	return nss_phys_if_change_mtu(dp->nss_ctx, mtu, dp->if_num);
+}
+
+/*
+ * __nss_data_plane_pause_on_off()
+ *	Called by nss-dp to enable/disable pause frames
+ */
+static int __nss_data_plane_pause_on_off(struct nss_dp_data_plane_ctx *dpc, uint32_t pause_on)
+{
+	struct nss_data_plane_param *dp = (struct nss_data_plane_param *)dpc;
+
+	return nss_phys_if_pause_on_off(dp->nss_ctx, pause_on, dp->if_num);
+}
+
+#ifdef NSS_DRV_QRFS_ENABLE
+/*
+ * __nss_data_plane_rx_flow_steer()
+ *	Called by nss-dp to set flow rule of a data plane
+ */
+static int __nss_data_plane_rx_flow_steer(struct nss_dp_data_plane_ctx *dpc, struct sk_buff *skb,
+						uint32_t cpu, bool is_add)
+{
+	if (is_add) {
+		return nss_qrfs_set_flow_rule(skb, cpu, NSS_QRFS_MSG_FLOW_ADD);
+	}
+
+	return nss_qrfs_set_flow_rule(skb, cpu, NSS_QRFS_MSG_FLOW_DELETE);
+}
+#endif
+
+/*
+ * __nss_data_plane_deinit()
+ *	Place holder for nss-dp ops to free NSS data plane resources
+ */
+static int __nss_data_plane_deinit(struct nss_dp_data_plane_ctx *dpc)
+{
+	/*
+	 * TODO: Implement free up of NSS data plane resources
+	 */
+	return NSS_TX_SUCCESS;
+}
+
+/*
+ * __nss_data_plane_buf()
+ *	Called by nss-dp to pass a sk_buff for xmit
+ */
+static netdev_tx_t __nss_data_plane_buf(struct nss_dp_data_plane_ctx *dpc, struct sk_buff *skb)
+{
+	struct nss_data_plane_param *dp = (struct nss_data_plane_param *)dpc;
+	int extra_head = dpc->dev->needed_headroom - skb_headroom(skb);
+	int extra_tail = 0;
+	nss_tx_status_t status;
+	struct net_device *dev = dpc->dev;
+
+	if (skb->len < ETH_HLEN) {
+		nss_warning("skb->len ( %u ) < ETH_HLEN ( %u ) \n", skb->len, ETH_HLEN);
+		goto drop;
+	}
+
+	if (skb->len > NSS_DATA_PLANE_MAX_PACKET_LEN) {
+		nss_warning("skb->len ( %u ) > Maximum packet length ( %u ) \n",
+				skb->len, NSS_DATA_PLANE_MAX_PACKET_LEN);
+		goto drop;
+	}
+
+	if (skb_cloned(skb) || extra_head > 0) {
+		/*
+		 * If it is a clone and headroom is already enough,
+		 * We just make a copy and clear the clone flag.
+		 */
+		if (extra_head <= 0)
+			extra_head = extra_tail = 0;
+		/*
+		 * If tailroom is enough to accommodate the added headroom,
+		 * then allocate a buffer of same size and do relocations.
+		 * It might help kmalloc_reserve() not double the size.
+		 */
+		if (skb->end - skb->tail >= extra_head)
+			extra_tail = -extra_head;
+
+		if (pskb_expand_head(skb, extra_head, extra_tail, GFP_ATOMIC)) {
+			nss_warning("%px: Unable to expand skb for headroom\n", dp);
+			goto drop;
+		}
+	}
+
+	status = nss_phys_if_buf(dp->nss_ctx, skb, dp->if_num);
+	if (likely(status == NSS_TX_SUCCESS)) {
+		return NETDEV_TX_OK;
+	} else if (status == NSS_TX_FAILURE_QUEUE) {
+		return NETDEV_TX_BUSY;
+	}
+
+drop:
+	dev_kfree_skb_any(skb);
+	dev->stats.tx_dropped++;
+
+	return NETDEV_TX_OK;
+}
+
+/*
+ * __nss_data_plane_set_features()
+ *	Called by nss-dp to allow data plane to modify the set of features it supports
+ */
+static void __nss_data_plane_set_features(struct nss_dp_data_plane_ctx *dpc)
+{
+	nss_data_plane_hal_set_features(dpc);
+}
+
+/*
+ * nss offload data plane ops
+ */
+static struct nss_dp_data_plane_ops dp_ops = {
+	.init		= __nss_data_plane_init,
+	.open		= __nss_data_plane_open,
+	.close		= __nss_data_plane_close,
+	.link_state	= __nss_data_plane_link_state,
+	.mac_addr	= __nss_data_plane_mac_addr,
+	.change_mtu	= __nss_data_plane_change_mtu,
+	.xmit		= __nss_data_plane_buf,
+	.set_features	= __nss_data_plane_set_features,
+	.pause_on_off	= __nss_data_plane_pause_on_off,
+#ifdef NSS_DRV_QRFS_ENABLE
+	.rx_flow_steer	= __nss_data_plane_rx_flow_steer,
+#endif
+	.deinit		= __nss_data_plane_deinit,
+};
+
+/*
+ * nss_data_plane_register_to_nss_dp()
+ */
+static bool nss_data_plane_register_to_nss_dp(struct nss_ctx_instance *nss_ctx, int if_num)
+{
+	struct nss_data_plane_param *ndpp = &nss_data_plane_params[if_num];
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	struct net_device *netdev;
+	bool is_open;
+	int core;
+
+	netdev = nss_dp_get_netdev_by_nss_if_num(if_num);
+	if (!netdev) {
+		nss_info("%px: Platform don't have data plane%d enabled, \
+				don't bring up nss_phys_if and don't register to nss-dp\n",
+				nss_ctx, if_num);
+		return false;
+	}
+
+	is_open = nss_dp_is_in_open_state(netdev);
+	ndpp->dpc.dev = netdev;
+	ndpp->nss_ctx = nss_ctx;
+	ndpp->if_num = if_num;
+	ndpp->notify_open = 0;
+	ndpp->features = 0;
+
+	/*
+	 * Add data plane ops applicable to this SoC.
+	 */
+	nss_data_plane_hal_add_dp_ops(&dp_ops);
+
+	/*
+	 * Check if NSS NW processing to be bypassed for this data plane
+	 */
+	if (nss_skip_nw_process) {
+		ndpp->bypass_nw_process = 1;
+	} else {
+		ndpp->bypass_nw_process = 0;
+	}
+
+	if (nss_dp_override_data_plane(netdev, &dp_ops, (struct nss_dp_data_plane_ctx *)ndpp) != NSS_DP_SUCCESS) {
+		nss_info("%px: Override nss-dp data plane for port %dfailed\n", nss_ctx, if_num);
+		return false;
+	}
+
+	/*
+	 * Setup the receive callback so that data pkts received form NSS-FW will
+	 * be redirected to the nss-dp driver as we are overriding the data plane
+	 */
+	nss_top->phys_if_handler_id[if_num] = nss_ctx->id;
+	nss_phys_if_register_handler(nss_ctx, if_num);
+
+	/*
+	 * Packets recieved on physical interface can be exceptioned to HLOS
+	 * from any NSS core so we need to register data plane for all
+	 */
+	for (core = 0; core < nss_top->num_nss; core++) {
+		nss_core_register_subsys_dp(&nss_top->nss[core], if_num, nss_dp_receive, NULL, NULL, netdev, ndpp->features);
+	}
+
+	/*
+	 * Now we are registered and our side is ready, if the data plane was opened, ask it to start again
+	 */
+	if (is_open) {
+		nss_dp_start_data_plane(netdev, (struct nss_dp_data_plane_ctx *)ndpp);
+	}
+	return true;
+}
+
+/*
+ * nss_data_plane_unregister_from_nss_dp()
+ */
+static void nss_data_plane_unregister_from_nss_dp(int if_num)
+{
+	/*
+	 * Do any SoC specific un-registrations.
+	 */
+	nss_data_plane_hal_unregister(nss_data_plane_params[if_num].nss_ctx);
+
+	nss_dp_restore_data_plane(nss_data_plane_params[if_num].dpc.dev);
+	nss_data_plane_params[if_num].dpc.dev = NULL;
+	nss_data_plane_params[if_num].nss_ctx = NULL;
+	nss_data_plane_params[if_num].if_num = 0;
+	nss_data_plane_params[if_num].notify_open = 0;
+	nss_data_plane_params[if_num].bypass_nw_process = 0;
+}
+
+/*
+ * __nss_data_plane_register()
+ */
+static void __nss_data_plane_register(struct nss_ctx_instance *nss_ctx)
+{
+	int i;
+
+	for (i = NSS_DP_START_IFNUM; i < NSS_DP_MAX_INTERFACES; i++) {
+		if (!nss_data_plane_register_to_nss_dp(nss_ctx, i)) {
+			nss_warning("%px: Register data plane failed for data plane %d\n", nss_ctx, i);
+		} else {
+			nss_info("%px: Register data plan to data plane %d success\n", nss_ctx, i);
+		}
+	}
+
+	/*
+	 * Do any SoC specific registrations.
+	 */
+	nss_data_plane_hal_register(nss_ctx);
+}
+
+/*
+ * __nss_data_plane_unregister()
+ */
+static void __nss_data_plane_unregister(void)
+{
+	int i, core;
+
+	for (core = 0; core < nss_top_main.num_nss; core++) {
+		for (i = NSS_DP_START_IFNUM; i < NSS_DP_MAX_INTERFACES; i++) {
+			if (nss_top_main.nss[core].subsys_dp_register[i].ndev) {
+				nss_data_plane_unregister_from_nss_dp(i);
+				nss_core_unregister_subsys_dp(&nss_top_main.nss[core], i);
+			}
+		}
+	}
+}
+
+/*
+ * __nss_data_plane_stats_sync()
+ */
+static void __nss_data_plane_stats_sync(struct nss_phys_if_stats *stats, uint16_t interface)
+{
+	nss_data_plane_hal_stats_sync(&nss_data_plane_params[interface], stats);
+}
+
+/*
+ * __nss_data_plane_get_mtu_sz()
+ */
+static uint16_t __nss_data_plane_get_mtu_sz(uint16_t mtu)
+{
+	return nss_data_plane_hal_get_mtu_sz(mtu);
+}
+
+/*
+ * nss_data_plane_ops
+ */
+struct nss_data_plane_ops nss_data_plane_ops = {
+	.data_plane_register = &__nss_data_plane_register,
+	.data_plane_unregister = &__nss_data_plane_unregister,
+	.data_plane_stats_sync = &__nss_data_plane_stats_sync,
+	.data_plane_get_mtu_sz = &__nss_data_plane_get_mtu_sz,
+};
diff --git a/qca-nss-drv/nss_data_plane/nss_data_plane_common.c b/qca-nss-drv/nss_data_plane/nss_data_plane_common.c
new file mode 100644
index 0000000..4ffaa9c
--- /dev/null
+++ b/qca-nss-drv/nss_data_plane/nss_data_plane_common.c
@@ -0,0 +1,84 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2016,2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_data_plane.h"
+#include "nss_core.h"
+
+static struct delayed_work nss_data_plane_work;
+static struct workqueue_struct *nss_data_plane_workqueue;
+
+extern bool pn_mq_en;
+extern uint16_t pn_qlimits[NSS_MAX_NUM_PRI];
+
+/*
+ * nss_data_plane_work_function()
+ *	Work function that gets queued to "install" the data plane overlays
+ */
+static void nss_data_plane_work_function(struct work_struct *work)
+{
+	int ret;
+	struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[NSS_CORE_0];
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	/*
+	 * The queue config command is a synchronous command and needs to be issued
+	 * in process context, before NSS data plane switch.
+	 */
+	ret = nss_n2h_update_queue_config_sync(nss_ctx, pn_mq_en, pn_qlimits);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_warning("Failed to send pnode queue config to core 0\n");
+	}
+
+	nss_top->data_plane_ops->data_plane_register(nss_ctx);
+}
+
+/*
+ * nss_data_plane_schedule_registration()
+ *	Called from nss_init to schedule a work to do data_plane register to data plane host
+ */
+bool nss_data_plane_schedule_registration(void)
+{
+	if (!queue_work_on(1, nss_data_plane_workqueue, &nss_data_plane_work.work)) {
+		nss_warning("Failed to register data plane workqueue on core 1\n");
+		return false;
+	}
+
+	nss_info("Register data plane workqueue on core 1\n");
+	return true;
+}
+
+/*
+ * nss_data_plane_init_delay_work()
+ */
+int nss_data_plane_init_delay_work(void)
+{
+	nss_data_plane_workqueue = create_singlethread_workqueue("nss_data_plane_workqueue");
+	if (!nss_data_plane_workqueue) {
+		nss_warning("Can't allocate workqueue\n");
+		return -ENOMEM;
+	}
+
+	INIT_DELAYED_WORK(&nss_data_plane_work, nss_data_plane_work_function);
+	return 0;
+}
+
+/*
+ * nss_data_plane_destroy_delay_work()
+ */
+void nss_data_plane_destroy_delay_work(void)
+{
+	destroy_workqueue(nss_data_plane_workqueue);
+}
diff --git a/qca-nss-drv/nss_data_plane/nss_data_plane_gmac.c b/qca-nss-drv/nss_data_plane/nss_data_plane_gmac.c
new file mode 100644
index 0000000..42e10a9
--- /dev/null
+++ b/qca-nss-drv/nss_data_plane/nss_data_plane_gmac.c
@@ -0,0 +1,396 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_data_plane.h"
+#include "nss_phys_if.h"
+#include "nss_core.h"
+#include "nss_tx_rx_common.h"
+#include <nss_gmac_api_if.h>
+
+#define NSS_DP_GMAC_SUPPORTED_FEATURES (NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_FRAGLIST | (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_UFO))
+#define NSS_DATA_PLANE_GMAC_MAX_INTERFACES 4
+
+static DEFINE_SPINLOCK(nss_data_plane_gmac_stats_lock);
+
+/*
+ * nss_data_plane_gmac_param
+ *	Holds the information that is going to pass to data plane host as a cookie
+ */
+struct nss_data_plane_gmac_param {
+	int if_num;				/* physical interface number */
+	struct net_device *dev;			/* net_device instance of this data plane */
+	struct nss_ctx_instance *nss_ctx;	/* which nss core */
+	struct nss_gmac_stats gmac_stats;	/* gmac stats */
+	int notify_open;			/* This data plane interface has been opened or not */
+	uint32_t features;			/* skb types supported by this interface */
+	uint32_t bypass_nw_process;		/* Do we want to bypass NW processing in NSS for this data plane? */
+} nss_data_plane_gmac_params[NSS_DATA_PLANE_GMAC_MAX_INTERFACES];
+
+/*
+ * __nss_data_plane_open()
+ *	Called by gmac to notify open to nss-fw
+ */
+static int __nss_data_plane_open(void *arg, uint32_t tx_desc_ring, uint32_t rx_desc_ring, uint32_t mode)
+{
+	struct nss_data_plane_gmac_param *dp = (struct nss_data_plane_gmac_param *)arg;
+
+	if (dp->notify_open) {
+		return NSS_GMAC_SUCCESS;
+	}
+	if (nss_phys_if_open(dp->nss_ctx, tx_desc_ring, rx_desc_ring, mode, dp->if_num, dp->bypass_nw_process) == NSS_TX_SUCCESS) {
+		dp->notify_open = 1;
+		return NSS_GMAC_SUCCESS;
+	}
+	return NSS_GMAC_FAILURE;
+}
+
+/*
+ * __nss_data_plane_close()
+ *	Called by gmac to notify close to nss-fw
+ */
+static int __nss_data_plane_close(void *arg)
+{
+	/*
+	 * We don't actually do synopsys gmac close in fw, just return success
+	 */
+	return NSS_GMAC_SUCCESS;
+}
+
+/*
+ * __nss_data_plane_link_state()
+ *	Called by gmac to notify link state change to nss-fw
+ */
+static int __nss_data_plane_link_state(void *arg, uint32_t link_state)
+{
+	struct nss_data_plane_gmac_param *dp = (struct nss_data_plane_gmac_param *)arg;
+
+	return nss_phys_if_link_state(dp->nss_ctx, link_state, dp->if_num);
+}
+
+/*
+ * __nss_data_plane_mac_addr()
+ *	Called by gmac to set mac address
+ */
+static int __nss_data_plane_mac_addr(void *arg, uint8_t *addr)
+{
+	struct nss_data_plane_gmac_param *dp = (struct nss_data_plane_gmac_param *)arg;
+
+	return nss_phys_if_mac_addr(dp->nss_ctx, addr, dp->if_num);
+}
+
+/*
+ * __nss_data_plane_change_mtu()
+ *	Called by gmac to change mtu of a gmac
+ */
+static int __nss_data_plane_change_mtu(void *arg, uint32_t mtu)
+{
+	struct nss_data_plane_gmac_param *dp = (struct nss_data_plane_gmac_param *)arg;
+
+	/*
+	 * MTU size check is already done in nss-gmac driver, just pass to phys_if
+	 */
+	return nss_phys_if_change_mtu(dp->nss_ctx, mtu, dp->if_num);
+}
+
+/*
+ * __nss_data_plane_pause_on_off()
+ *	Called by gmac to enable/disable pause frames
+ */
+static int __nss_data_plane_pause_on_off(void *arg, uint32_t pause_on)
+{
+	struct nss_data_plane_gmac_param *dp = (struct nss_data_plane_gmac_param *)arg;
+
+	return nss_phys_if_pause_on_off(dp->nss_ctx, pause_on, dp->if_num);
+}
+
+/*
+ * __nss_data_plane_buf()
+ *	Called by gmac to pass a sk_buff for xmit
+ */
+static int __nss_data_plane_buf(void *arg, struct sk_buff *os_buf)
+{
+	struct nss_data_plane_gmac_param *dp = (struct nss_data_plane_gmac_param *)arg;
+
+	return nss_phys_if_buf(dp->nss_ctx, os_buf, dp->if_num);
+}
+
+/*
+ * __nss_data_plane_set_features()
+ *	Called by gmac to allow data plane to modify the set of features it supports
+ */
+static void __nss_data_plane_set_features(struct net_device *netdev)
+{
+	netdev->features |= NSS_DP_GMAC_SUPPORTED_FEATURES;
+	netdev->hw_features |= NSS_DP_GMAC_SUPPORTED_FEATURES;
+	netdev->vlan_features |= NSS_DP_GMAC_SUPPORTED_FEATURES;
+	netdev->wanted_features |= NSS_DP_GMAC_SUPPORTED_FEATURES;
+}
+
+/*
+ * __nss_data_plane_get_stats()
+ */
+static void __nss_data_plane_get_stats(void *arg, struct nss_gmac_stats *stats)
+{
+	struct nss_data_plane_gmac_param *dp = (struct nss_data_plane_gmac_param *)arg;
+
+	spin_lock_bh(&nss_data_plane_gmac_stats_lock);
+	memcpy(stats, &dp->gmac_stats, sizeof(*stats));
+	spin_unlock_bh(&nss_data_plane_gmac_stats_lock);
+}
+
+/*
+ * nss offload data plane ops
+ */
+static struct nss_gmac_data_plane_ops dp_ops = {
+	.open		= __nss_data_plane_open,
+	.close		= __nss_data_plane_close,
+	.link_state	= __nss_data_plane_link_state,
+	.mac_addr	= __nss_data_plane_mac_addr,
+	.change_mtu	= __nss_data_plane_change_mtu,
+	.xmit		= __nss_data_plane_buf,
+	.set_features	= __nss_data_plane_set_features,
+	.pause_on_off	= __nss_data_plane_pause_on_off,
+	.get_stats	= __nss_data_plane_get_stats,
+};
+
+/*
+ * nss_data_plane_register_to_nss_gmac()
+ */
+static bool nss_data_plane_register_to_nss_gmac(struct nss_ctx_instance *nss_ctx, int if_num)
+{
+	struct nss_data_plane_gmac_param *ndpp = &nss_data_plane_gmac_params[if_num];
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	struct net_device *netdev;
+	bool is_open;
+	int core;
+
+	netdev = nss_gmac_get_netdev_by_macid(if_num);
+	if (!netdev) {
+		nss_info("Platform don't have gmac%d enabled, don't bring up nss_phys_if and don't register to nss-gmac", if_num);
+		return false;
+	}
+
+	is_open = nss_gmac_is_in_open_state(netdev);
+	ndpp->dev = netdev;
+	ndpp->nss_ctx = nss_ctx;
+	ndpp->if_num = if_num;
+	ndpp->notify_open = 0;
+	ndpp->features = 0;
+
+	/*
+	 * Check if NSS NW processing to be bypassed for this GMAC
+	 */
+	if (nss_skip_nw_process) {
+		ndpp->bypass_nw_process = 1;
+	} else {
+		ndpp->bypass_nw_process = 0;
+	}
+
+	if (nss_gmac_override_data_plane(netdev, &dp_ops, ndpp) != NSS_GMAC_SUCCESS) {
+		nss_info("Override nss-gmac data plane failed\n");
+		return false;
+	}
+
+	/*
+	 * Setup the receive callback so that data pkts received form NSS-FW will
+	 * be redirected to the gmac driver as we are overriding the data plane
+	 */
+	nss_top->phys_if_handler_id[if_num] = nss_ctx->id;
+	nss_phys_if_register_handler(nss_ctx, if_num);
+
+	/*
+	 * Packets recieved on physical interface can be exceptioned to HLOS
+	 * from any NSS core so we need to register data plane for all
+	 */
+	for (core = 0; core < nss_top->num_nss; core++) {
+		nss_core_register_subsys_dp(&nss_top->nss[core], if_num, nss_gmac_receive, NULL, NULL, netdev, ndpp->features);
+	}
+
+	/*
+	 * Now we are registered and our side is ready, if the gmac was opened, ask it to start again
+	 */
+	if (is_open) {
+		nss_gmac_start_data_plane(netdev, ndpp);
+	}
+	return true;
+}
+
+/*
+ * nss_data_plane_unregister_from_nss_gmac()
+ */
+static void nss_data_plane_unregister_from_nss_gmac(int if_num)
+{
+	nss_gmac_restore_data_plane(nss_data_plane_gmac_params[if_num].dev);
+	nss_data_plane_gmac_params[if_num].dev = NULL;
+	nss_data_plane_gmac_params[if_num].nss_ctx = NULL;
+	nss_data_plane_gmac_params[if_num].if_num = 0;
+	nss_data_plane_gmac_params[if_num].notify_open = 0;
+	nss_data_plane_gmac_params[if_num].bypass_nw_process = 0;
+}
+
+/*
+ * __nss_data_plane_register()
+ */
+static void __nss_data_plane_register(struct nss_ctx_instance *nss_ctx)
+{
+	int i;
+
+	for (i = 0; i < NSS_DATA_PLANE_GMAC_MAX_INTERFACES; i++) {
+		if (!nss_data_plane_register_to_nss_gmac(nss_ctx, i)) {
+			nss_warning("%px: Register data plane failed for gmac:%d\n", nss_ctx, i);
+		} else {
+			nss_info("%px: Register data plan to gmac:%d success\n", nss_ctx, i);
+		}
+	}
+}
+
+/*
+ * __nss_data_plane_unregister()
+ */
+static void __nss_data_plane_unregister(void)
+{
+	int i, core;
+
+	for (core = 0; core < nss_top_main.num_nss; core++) {
+		for (i = 0; i < NSS_DATA_PLANE_GMAC_MAX_INTERFACES; i++) {
+			if (nss_top_main.nss[core].subsys_dp_register[i].ndev) {
+				nss_data_plane_unregister_from_nss_gmac(i);
+				nss_core_unregister_subsys_dp(&nss_top_main.nss[core], i);
+			}
+		}
+	}
+}
+
+/*
+ * __nss_data_plane_stats_sync()
+ *	Handle the syncing of gmac data plane stats.
+ */
+static void __nss_data_plane_stats_sync(struct nss_phys_if_stats *stats, uint16_t interface)
+{
+	struct nss_gmac_stats *gmac_stats = &nss_data_plane_gmac_params[interface].gmac_stats;
+
+	spin_lock_bh(&nss_data_plane_gmac_stats_lock);
+	gmac_stats->rx_bytes += stats->if_stats.rx_bytes;
+	gmac_stats->rx_packets += stats->if_stats.rx_packets;
+	gmac_stats->rx_errors += stats->estats.rx_errors;
+	gmac_stats->rx_receive_errors += stats->estats.rx_receive_errors;
+	gmac_stats->rx_descriptor_errors += stats->estats.rx_descriptor_errors;
+	gmac_stats->rx_late_collision_errors += stats->estats.rx_late_collision_errors;
+	gmac_stats->rx_dribble_bit_errors += stats->estats.rx_dribble_bit_errors;
+	gmac_stats->rx_length_errors += stats->estats.rx_length_errors;
+	gmac_stats->rx_ip_header_errors += stats->estats.rx_ip_header_errors;
+	gmac_stats->rx_ip_payload_errors += stats->estats.rx_ip_payload_errors;
+	gmac_stats->rx_no_buffer_errors += stats->estats.rx_no_buffer_errors;
+	gmac_stats->rx_transport_csum_bypassed += stats->estats.rx_transport_csum_bypassed;
+
+	gmac_stats->tx_bytes += stats->if_stats.tx_bytes;
+	gmac_stats->tx_packets += stats->if_stats.tx_packets;
+	gmac_stats->tx_collisions += stats->estats.tx_collisions;
+	gmac_stats->tx_errors += stats->estats.tx_errors;
+	gmac_stats->tx_jabber_timeout_errors += stats->estats.tx_jabber_timeout_errors;
+	gmac_stats->tx_frame_flushed_errors += stats->estats.tx_frame_flushed_errors;
+	gmac_stats->tx_loss_of_carrier_errors += stats->estats.tx_loss_of_carrier_errors;
+	gmac_stats->tx_no_carrier_errors += stats->estats.tx_no_carrier_errors;
+	gmac_stats->tx_late_collision_errors += stats->estats.tx_late_collision_errors;
+	gmac_stats->tx_excessive_collision_errors += stats->estats.tx_excessive_collision_errors;
+	gmac_stats->tx_excessive_deferral_errors += stats->estats.tx_excessive_deferral_errors;
+	gmac_stats->tx_underflow_errors += stats->estats.tx_underflow_errors;
+	gmac_stats->tx_ip_header_errors += stats->estats.tx_ip_header_errors;
+	gmac_stats->tx_ip_payload_errors += stats->estats.tx_ip_payload_errors;
+	gmac_stats->tx_dropped += stats->estats.tx_dropped;
+
+	gmac_stats->hw_errs[0] += stats->estats.hw_errs[0];
+	gmac_stats->hw_errs[1] += stats->estats.hw_errs[1];
+	gmac_stats->hw_errs[2] += stats->estats.hw_errs[2];
+	gmac_stats->hw_errs[3] += stats->estats.hw_errs[3];
+	gmac_stats->hw_errs[4] += stats->estats.hw_errs[4];
+	gmac_stats->hw_errs[5] += stats->estats.hw_errs[5];
+	gmac_stats->hw_errs[6] += stats->estats.hw_errs[6];
+	gmac_stats->hw_errs[7] += stats->estats.hw_errs[7];
+	gmac_stats->hw_errs[8] += stats->estats.hw_errs[8];
+	gmac_stats->hw_errs[9] += stats->estats.hw_errs[9];
+	gmac_stats->rx_missed += stats->estats.rx_missed;
+
+	gmac_stats->fifo_overflows += stats->estats.fifo_overflows;
+	gmac_stats->rx_scatter_errors += stats->estats.rx_scatter_errors;
+	gmac_stats->tx_ts_create_errors += stats->estats.tx_ts_create_errors;
+	gmac_stats->gmac_total_ticks += stats->estats.gmac_total_ticks;
+	gmac_stats->gmac_worst_case_ticks += stats->estats.gmac_worst_case_ticks;
+	gmac_stats->gmac_iterations += stats->estats.gmac_iterations;
+	gmac_stats->tx_pause_frames += stats->estats.tx_pause_frames;
+	gmac_stats->mmc_rx_overflow_errors += stats->estats.mmc_rx_overflow_errors;
+	gmac_stats->mmc_rx_watchdog_timeout_errors += stats->estats.mmc_rx_watchdog_timeout_errors;
+	gmac_stats->mmc_rx_crc_errors += stats->estats.mmc_rx_crc_errors;
+	gmac_stats->mmc_rx_ip_header_errors += stats->estats.mmc_rx_ip_header_errors;
+	gmac_stats->mmc_rx_octets_g += stats->estats.mmc_rx_octets_g;
+	gmac_stats->mmc_rx_ucast_frames += stats->estats.mmc_rx_ucast_frames;
+	gmac_stats->mmc_rx_bcast_frames += stats->estats.mmc_rx_bcast_frames;
+	gmac_stats->mmc_rx_mcast_frames += stats->estats.mmc_rx_mcast_frames;
+	gmac_stats->mmc_rx_undersize += stats->estats.mmc_rx_undersize;
+	gmac_stats->mmc_rx_oversize += stats->estats.mmc_rx_oversize;
+	gmac_stats->mmc_rx_jabber += stats->estats.mmc_rx_jabber;
+	gmac_stats->mmc_rx_octets_gb += stats->estats.mmc_rx_octets_gb;
+	gmac_stats->mmc_rx_frag_frames_g += stats->estats.mmc_rx_frag_frames_g;
+	gmac_stats->mmc_tx_octets_g += stats->estats.mmc_tx_octets_g;
+	gmac_stats->mmc_tx_ucast_frames += stats->estats.mmc_tx_ucast_frames;
+	gmac_stats->mmc_tx_bcast_frames += stats->estats.mmc_tx_bcast_frames;
+	gmac_stats->mmc_tx_mcast_frames += stats->estats.mmc_tx_mcast_frames;
+	gmac_stats->mmc_tx_deferred += stats->estats.mmc_tx_deferred;
+	gmac_stats->mmc_tx_single_col += stats->estats.mmc_tx_single_col;
+	gmac_stats->mmc_tx_multiple_col += stats->estats.mmc_tx_multiple_col;
+	gmac_stats->mmc_tx_octets_gb += stats->estats.mmc_tx_octets_gb;
+
+	spin_unlock_bh(&nss_data_plane_gmac_stats_lock);
+}
+
+/*
+ * __nss_data_plane_get_mtu_sz()
+ */
+static uint16_t __nss_data_plane_get_mtu_sz(uint16_t max_mtu)
+{
+	/*
+	 * GMACs support 3 Modes
+	 * Normal Mode Payloads upto 1522 Bytes ( 1500 + 14 + 4(Vlan) + 4(CRC))
+	 * Mini Jumbo Mode Payloads upto 2000 Bytes (1978 + 14 + 4(Vlan) + 4 (CRC))
+	 * Full Jumbo Mode payloads upto 9622 Bytes (9600 + 14 + 4(Vlan) + 4 (CRC))
+	 */
+
+	/*
+	 * The configured MTU value on a gmac interface should be one of these
+	 * cases. Finding the Needed MTU size that is required for GMAC to
+	 * successfully receive the frame.
+	 */
+	if (max_mtu <= NSS_GMAC_NORMAL_FRAME_MTU) {
+		return NSS_GMAC_NORMAL_FRAME_MTU;
+	}
+	if (max_mtu <= NSS_GMAC_MINI_JUMBO_FRAME_MTU) {
+		return NSS_GMAC_MINI_JUMBO_FRAME_MTU;
+	}
+	if (max_mtu <= NSS_GMAC_FULL_JUMBO_FRAME_MTU) {
+		return NSS_GMAC_FULL_JUMBO_FRAME_MTU;
+	}
+	return 0;
+}
+
+/*
+ * nss_data_plane_gmac_ops
+ */
+struct nss_data_plane_ops nss_data_plane_gmac_ops = {
+	.data_plane_register = &__nss_data_plane_register,
+	.data_plane_unregister = &__nss_data_plane_unregister,
+	.data_plane_stats_sync = &__nss_data_plane_stats_sync,
+	.data_plane_get_mtu_sz = &__nss_data_plane_get_mtu_sz,
+};
diff --git a/qca-nss-drv/nss_dma.c b/qca-nss-drv/nss_dma.c
new file mode 100755
index 0000000..e88e7c6
--- /dev/null
+++ b/qca-nss-drv/nss_dma.c
@@ -0,0 +1,501 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_dma.c
+ *	NSS DMA APIs
+ */
+
+#include <nss_hal.h>
+#include "nss_dma_stats.h"
+#include "nss_dma_log.h"
+#include "nss_dma_strings.h"
+
+/*
+ * Test configuration value
+ */
+struct nss_dma_test_cfg_val {
+	int val;			/* field value */
+	int min;			/* Minimum value */
+	int max;			/* Maximum value */
+};
+
+/*
+ * Test configuration for user
+ */
+struct nss_dma_test_cfg_user {
+	struct nss_dma_test_cfg_val run;	/* test run state */
+	struct nss_dma_test_cfg_val code;	/* test run code */
+	struct nss_dma_test_cfg_val type;	/* test type code */
+	struct nss_dma_test_cfg_val packets;	/* packet count per loop */
+	int result_tx_packets;			/* test results TX packets */
+	int result_rx_packets;			/* test result RX packets */
+	int result_time;			/* test time */
+};
+
+static struct nss_dma_test_cfg_user test_cfg = {
+	.run = {.val = 0, .min = 0 /* stopped */, .max = 1 /* running */},
+	.code = {.val = 1, .min = 1 /* linearize */, .max = 2 /* split */},
+	.type = {.val = NSS_DMA_TEST_TYPE_DEFAULT, .min = NSS_DMA_TEST_TYPE_DEFAULT, .max = NSS_DMA_TEST_TYPE_MAX},
+	.packets = {.val = 1, .min = 1, .max = 65536},
+};
+
+/*
+ * Private data structure.
+ */
+struct nss_dma_pvt {
+	struct semaphore sem;		/* Semaphore structure. */
+	struct completion complete;	/* Completion structure. */
+	int response;			/* Response from FW. */
+	void *cb;			/* Original cb for sync msgs. */
+	void *app_data;			/* Original app_data for sync msgs. */
+};
+
+static struct nss_dma_pvt nss_dma_cfg_pvt;
+
+/*
+ * nss_dma_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static inline bool nss_dma_verify_if_num(uint32_t if_num)
+{
+	return if_num == NSS_DMA_INTERFACE;
+}
+
+/*
+ * nss_dma_interface_handler()
+ *	Handle NSS -> HLOS messages for DMA Statistics
+ */
+static void nss_dma_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm,
+				 __attribute__((unused))void *app_data)
+{
+	struct nss_dma_msg *ndm = (struct nss_dma_msg *)ncm;
+	nss_dma_msg_callback_t cb;
+
+	if (!nss_dma_verify_if_num(ncm->interface)) {
+		nss_warning("%px: invalid interface %d for dma\n", nss_ctx, ncm->interface);
+		return;
+	}
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_DMA_MSG_TYPE_MAX) {
+		nss_warning("%px: received invalid message %d for dma", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_dma_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_dma_log_rx_msg(ndm);
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Update driver statistics and send statistics notifications to the registered modules.
+	 */
+	if (ndm->cm.type == NSS_DMA_MSG_TYPE_SYNC_STATS) {
+		nss_dma_stats_sync(nss_ctx, &ndm->msg.stats);
+		nss_dma_stats_notify(nss_ctx);
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->nss_rx_interface_handlers[ncm->interface].app_data;
+	}
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_dma_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, ncm);
+}
+
+/*
+ * nss_dma_register_handler()
+ *	Register handler for messaging
+ */
+void nss_dma_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_dma_get_context();
+
+	nss_info("%px: nss_dma_register_handler", nss_ctx);
+	nss_core_register_handler(nss_ctx, NSS_DMA_INTERFACE, nss_dma_msg_handler, NULL);
+
+	nss_dma_stats_dentry_create();
+	nss_dma_strings_dentry_create();
+}
+EXPORT_SYMBOL(nss_dma_register_handler);
+
+/*
+ * nss_dma_tx_msg()
+ *	Transmit an dma message to the FW with a specified size.
+ */
+nss_tx_status_t nss_dma_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_dma_msg *ndm)
+{
+	struct nss_cmn_msg *ncm = &ndm->cm;
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!nss_dma_verify_if_num(ncm->interface)) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_DMA_MSG_TYPE_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_dma_log_tx_msg(ndm);
+
+	return nss_core_send_cmd(nss_ctx, ndm, sizeof(*ndm), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_dma_tx_msg);
+
+/*
+ * nss_dma_msg_test_callback()
+ *	Callback function for dma test start configuration
+ */
+static void nss_dma_msg_test_callback(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_ctx_instance *nss_ctx __attribute__((unused)) = (struct nss_ctx_instance *)app_data;
+	struct nss_dma_msg *ndm = (struct nss_dma_msg *)ncm;
+	struct nss_dma_test_cfg *ndtc = &ndm->msg.test_cfg;
+	struct nss_cmn_node_stats *ncns = &ndtc->node_stats;
+
+	test_cfg.run.val = 0; /* test completed */
+
+	/*
+	 * Test start has been failed. Restore the value to initial state.
+	 */
+	if (ndm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("%px: nss dma test failed: %d \n", nss_ctx, ndm->cm.error);
+		test_cfg.result_tx_packets = 0;
+		test_cfg.result_rx_packets = 0;
+		test_cfg.result_time = 0;
+		return;
+	}
+
+	test_cfg.result_tx_packets = ncns->tx_packets;
+	test_cfg.result_rx_packets = ncns->rx_packets;
+	test_cfg.result_time = ndtc->time_delta;
+
+	nss_info("%px: nss dma test complete\n", nss_ctx);
+	nss_info("%px: results tx=%u, rx=%u, time=%u\n", ndm, ncns->tx_packets, ncns->rx_packets, ndtc->time_delta);
+}
+
+/*
+ * nss_dma_msg_test()
+ *	Send NSS DMA test start message.
+ */
+static nss_tx_status_t nss_dma_msg_test(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_dma_msg ndm;
+	uint32_t flags = 0;
+	int32_t status;
+	size_t len;
+
+	len = sizeof(struct nss_cmn_msg) + sizeof(struct nss_dma_test_cfg);
+
+	nss_info("%px: DMA test message:%x\n", nss_ctx, test_cfg.run.val);
+	if (test_cfg.code.val == 1) {
+		flags = NSS_DMA_TEST_FLAGS_LINEARIZE;
+	}
+
+	nss_dma_msg_init(&ndm, NSS_DMA_INTERFACE, NSS_DMA_MSG_TYPE_TEST_PERF, len, nss_dma_msg_test_callback, nss_ctx);
+
+	ndm.msg.test_cfg.packet_count = test_cfg.packets.val;
+	ndm.msg.test_cfg.type = test_cfg.type.val;
+	ndm.msg.test_cfg.flags = flags;
+
+	status = nss_dma_tx_msg(nss_ctx, &ndm);
+	if (unlikely(status != NSS_TX_SUCCESS)) {
+		return status;
+	}
+
+	/*
+	 * Test is now running
+	 */
+	test_cfg.run.val = 1;
+	return NSS_TX_SUCCESS;
+}
+
+/*
+ * nss_dma_msg_init()
+ *	Initialize DMA message.
+ */
+void nss_dma_msg_init(struct nss_dma_msg *ndm, uint16_t if_num, uint32_t type, uint32_t len, nss_dma_msg_callback_t cb,
+			void *app_data)
+{
+	nss_cmn_msg_init(&ndm->cm, if_num, type, len, (void *)cb, app_data);
+}
+EXPORT_SYMBOL(nss_dma_msg_init);
+
+/*
+ * nss_crypto_cmn_get_context()
+ *	get NSS context instance for crypto handle
+ */
+struct nss_ctx_instance *nss_dma_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.dma_handler_id];
+}
+EXPORT_SYMBOL(nss_dma_get_context);
+
+/*
+ * nss_dma_test_handler()
+ *	Handles the performance test.
+ */
+static int nss_dma_test_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_ctx_instance *nss_ctx = nss_dma_get_context();
+	int cur_state = test_cfg.run.val;
+	int ret;
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret != NSS_SUCCESS) {
+		return ret;
+	}
+
+	if (!write) {
+		return ret;
+	}
+
+	/*
+	 * Check any tests are already scheduled
+	 */
+	if (cur_state > 0) {
+		nss_info("%px: Test is already running, stopping it.\n", nss_ctx);
+	} else {
+		nss_info("%px: Test is not running, starting it.\n", nss_ctx);
+	}
+
+	ret = nss_dma_msg_test(nss_ctx);
+	if (ret != NSS_SUCCESS) {
+		nss_warning("%px: Test configuration has failed.\n", nss_ctx);
+		test_cfg.run.val = 0;
+	}
+
+	return ret;
+}
+
+static struct ctl_table nss_dma_table[] = {
+	{
+		.procname	= "test_run",
+		.data		= &test_cfg.run.val,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= nss_dma_test_handler,
+		.extra1		= &test_cfg.run.min,
+		.extra2		= &test_cfg.run.max,
+	},
+	{
+		.procname	= "test_code",
+		.data		= &test_cfg.code.val,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= proc_dointvec_minmax,
+		.extra1		= &test_cfg.code.min,
+		.extra2		= &test_cfg.code.max,
+	},
+	{
+		.procname	= "test_type",
+		.data		= &test_cfg.type.val,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= proc_dointvec_minmax,
+		.extra1		= &test_cfg.type.min,
+		.extra2		= &test_cfg.type.max,
+	},
+	{
+		.procname	= "test_packets",
+		.data		= &test_cfg.packets.val,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= proc_dointvec_minmax,
+		.extra1		= &test_cfg.packets.min,
+		.extra2		= &test_cfg.packets.max,
+	},
+	{
+		.procname	= "result_tx",
+		.data		= &test_cfg.result_tx_packets,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= proc_dointvec,
+	},
+	{
+		.procname	= "result_rx",
+		.data		= &test_cfg.result_rx_packets,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= proc_dointvec,
+	},
+	{
+		.procname	= "result_time",
+		.data		= &test_cfg.result_time,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= proc_dointvec,
+	},
+	{ }
+};
+
+static struct ctl_table nss_dma_dir[] = {
+	{
+		.procname		= "dma",
+		.mode			= 0555,
+		.child			= nss_dma_table,
+	},
+	{ }
+};
+
+static struct ctl_table nss_dma_root_dir[] = {
+	{
+		.procname		= "nss",
+		.mode			= 0555,
+		.child			= nss_dma_dir,
+	},
+	{ }
+};
+
+static struct ctl_table nss_dma_root[] = {
+	{
+		.procname		= "dev",
+		.mode			= 0555,
+		.child			= nss_dma_root_dir,
+	},
+	{ }
+};
+
+static struct ctl_table_header *nss_dma_header;
+
+/*
+ * nss_dma_register_sysctl()
+ */
+void nss_dma_register_sysctl(void)
+{
+
+	/*
+	 * dma sema init.
+	 */
+	sema_init(&nss_dma_cfg_pvt.sem, 1);
+	init_completion(&nss_dma_cfg_pvt.complete);
+
+	/*
+	 * Register sysctl table.
+	 */
+	nss_dma_header = register_sysctl_table(nss_dma_root);
+}
+
+/*
+ * nss_dma_unregister_sysctl()
+ *      Unregister sysctl specific to dma
+ */
+void nss_dma_unregister_sysctl(void)
+{
+	/*
+	 * Unregister sysctl table.
+	 */
+	if (nss_dma_header) {
+		unregister_sysctl_table(nss_dma_header);
+	}
+}
+
+/*
+ * nss_dma_notify_register()
+ *	Register to receive dma notify messages.
+ */
+struct nss_ctx_instance *nss_dma_notify_register(int core, nss_dma_msg_callback_t cb, void *app_data)
+{
+	struct nss_ctx_instance *nss_ctx = nss_dma_get_context();
+	uint32_t ret;
+
+	ret = nss_core_register_handler(nss_ctx, NSS_DMA_INTERFACE, nss_dma_msg_handler, app_data);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to register event handler for DMA interface", nss_ctx);
+		return NULL;
+	}
+
+	ret = nss_core_register_msg_handler(nss_ctx, NSS_DMA_INTERFACE, cb);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_core_unregister_handler(nss_ctx, NSS_DMA_INTERFACE);
+		nss_warning("%px: unable to register event handler for DMA interface", nss_ctx);
+		return NULL;
+	}
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_dma_notify_register);
+
+/*
+ * nss_dma_notify_unregister()
+ *	Unregister to receive dma notify messages.
+ */
+void nss_dma_notify_unregister(int core)
+{
+	struct nss_ctx_instance *nss_ctx = nss_dma_get_context();
+	uint32_t ret;
+
+	BUG_ON(!nss_ctx);
+
+	ret = nss_core_unregister_msg_handler(nss_ctx, NSS_DMA_INTERFACE);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to unregister event handler for DMA interface", nss_ctx);
+		return;
+	}
+
+	ret = nss_core_unregister_handler(nss_ctx, NSS_DMA_INTERFACE);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to unregister event handler for DMA interface", nss_ctx);
+		return;
+	}
+
+	return;
+}
+EXPORT_SYMBOL(nss_dma_notify_unregister);
+
+/*
+ * nss_dma_init()
+ */
+void nss_dma_init(void)
+{
+	nss_dma_register_sysctl();
+}
diff --git a/qca-nss-drv/nss_dma_log.c b/qca-nss-drv/nss_dma_log.c
new file mode 100755
index 0000000..7f367c8
--- /dev/null
+++ b/qca-nss-drv/nss_dma_log.c
@@ -0,0 +1,140 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_dma_log.c
+ *	NSS DMA logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_dma_log_message_types_str
+ *	DMA message strings
+ */
+static int8_t *nss_dma_log_message_types_str[NSS_DMA_MSG_TYPE_MAX] __maybe_unused = {
+	"DMA invalid message",
+	"DMA Configure message",
+	"DMA Statistics sync message",
+	"DMA Test linearization performance",
+};
+
+/*
+ * nss_dma_log_error_response_types_str
+ *	Strings for error types for DMA messages
+ */
+static int8_t *nss_dma_log_error_response_types_str[NSS_DMA_MSG_ERROR_MAX] __maybe_unused = {
+	"No error",
+	"HW initialization failed",
+	"Unhandled message type for node",
+	"Error performing the test",
+};
+
+/*
+ * nss_dma_map_msg()
+ *	Log NSS DMA configure message.
+ */
+static void nss_dma_configure_msg(struct nss_dma_msg *ndm)
+{
+	nss_trace("%px: NSS DMA configure message: \n",ndm);
+}
+
+/*
+ * nss_dma_test_perf_msg()
+ *	Log NSS DMA performace test message.
+ */
+static void nss_dma_test_perf_msg(struct nss_dma_msg *ndm)
+{
+	struct nss_dma_test_cfg *ndtc = &ndm->msg.test_cfg;
+	struct nss_cmn_node_stats *ncns = &ndtc->node_stats;
+
+	nss_trace("%px: NSS DMA test perf message: \n",ndm);
+	nss_trace("%px: processed (TX: %u, RX:%u, time:%u)\n", ndm, ncns->tx_packets, ncns->rx_packets, ndtc->time_delta);
+	nss_trace("%px: test parameters (type:%u, packet_cnt:%u)\n", ndm, ndtc->type, ndtc->packet_count);
+}
+
+/*
+ * nss_dma_log_verbose()
+ *	Log message contents.
+ */
+static void nss_dma_log_verbose(struct nss_dma_msg *ndm)
+{
+	switch (ndm->cm.type) {
+	case NSS_DMA_MSG_TYPE_CONFIGURE:
+		nss_dma_configure_msg(ndm);
+		break;
+
+	case NSS_DMA_MSG_TYPE_TEST_PERF:
+		nss_dma_test_perf_msg(ndm);
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", ndm);
+		break;
+	}
+}
+
+/*
+ * nss_dma_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_dma_log_tx_msg(struct nss_dma_msg *ndm)
+{
+	if (ndm->cm.type >= NSS_DMA_MSG_TYPE_MAX) {
+		nss_info("%px: Invalid message type\n", ndm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ndm, ndm->cm.type, nss_dma_log_message_types_str[ndm->cm.type]);
+	nss_dma_log_verbose(ndm);
+}
+
+/*
+ * nss_dma_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_dma_log_rx_msg(struct nss_dma_msg *ndm)
+{
+	if (ndm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ndm);
+		return;
+	}
+
+	if (ndm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ndm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ndm, ndm->cm.type,
+			nss_dma_log_message_types_str[ndm->cm.type],
+			ndm->cm.response, nss_cmn_response_str[ndm->cm.response]);
+		goto verbose;
+	}
+
+	if (ndm->cm.error >= NSS_DMA_MSG_ERROR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			ndm, ndm->cm.type, nss_dma_log_message_types_str[ndm->cm.type],
+			ndm->cm.response, nss_cmn_response_str[ndm->cm.response],
+			ndm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		ndm, ndm->cm.type, nss_dma_log_message_types_str[ndm->cm.type],
+		ndm->cm.response, nss_cmn_response_str[ndm->cm.response],
+		ndm->cm.error, nss_dma_log_error_response_types_str[ndm->cm.error]);
+
+verbose:
+	nss_dma_log_verbose(ndm);
+}
diff --git a/qca-nss-drv/nss_dma_log.h b/qca-nss-drv/nss_dma_log.h
new file mode 100755
index 0000000..4a9b9c3
--- /dev/null
+++ b/qca-nss-drv/nss_dma_log.h
@@ -0,0 +1,38 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_DMA_LOG_H
+#define __NSS_DMA_LOG_H
+/*
+ * nss_dma_log.h
+ *	NSS DMA Log Header File
+ */
+
+/*
+ * nss_dma_log_tx_msg
+ *	Logs an DMA message that is sent to the NSS firmware.
+ */
+void nss_dma_log_tx_msg(struct nss_dma_msg *ndm);
+
+/*
+ * nss_dma_log_rx_msg
+ *	Logs an DMA message that is received from the NSS firmware.
+ */
+void nss_dma_log_rx_msg(struct nss_dma_msg *ndm);
+
+#endif /* __NSS_DMA_LOG_H */
diff --git a/qca-nss-drv/nss_dma_stats.c b/qca-nss-drv/nss_dma_stats.c
new file mode 100755
index 0000000..12812e4
--- /dev/null
+++ b/qca-nss-drv/nss_dma_stats.c
@@ -0,0 +1,163 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_dma.h"
+#include "nss_dma_stats.h"
+#include "nss_dma_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_dma_stats_notifier);
+
+/*
+ * Spinlock to protect DMA statistics update/read
+ */
+DEFINE_SPINLOCK(nss_dma_stats_lock);
+
+/*
+ * nss_dma_stats
+ *	DMA statistics
+ */
+uint64_t nss_dma_stats[NSS_DMA_STATS_MAX];
+
+/*
+ * nss_dma_stats_read()
+ *	Read DMA statistics
+ */
+static ssize_t nss_dma_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	/*
+	 * Max output lines = #stats * NSS_MAX_CORES  +
+	 * few blank lines for banner printing + Number of Extra outputlines for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_DMA_STATS_MAX  + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	uint64_t *stats_shadow;
+	ssize_t bytes_read = 0;
+	size_t size_wr = 0;
+	char *lbuf;
+	int32_t i;
+
+	lbuf = vzalloc(size_al);
+	if (!lbuf) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return -ENOMEM;
+	}
+
+	stats_shadow = vzalloc(NSS_DMA_STATS_MAX * 8);
+	if (!stats_shadow) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		vfree(lbuf);
+		return -ENOMEM;
+	}
+
+	/*
+	 * DMA statistics
+	 */
+	spin_lock_bh(&nss_dma_stats_lock);
+	for (i = 0; i < NSS_DMA_STATS_MAX; i++) {
+		stats_shadow[i] = nss_dma_stats[i];
+	}
+	spin_unlock_bh(&nss_dma_stats_lock);
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "dma", nss_top_main.dma_handler_id);
+	size_wr += nss_stats_print("dma", NULL, NSS_STATS_SINGLE_INSTANCE, nss_dma_strings_stats,
+				stats_shadow, NSS_DMA_STATS_MAX, lbuf, size_wr, size_al);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+
+	vfree(lbuf);
+	vfree(stats_shadow);
+	return bytes_read;
+}
+
+/*
+ * nss_dma_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(dma);
+
+/*
+ * nss_dma_stats_dentry_create()
+ *	Create DMA statistics debug entry.
+ */
+void nss_dma_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("dma", &nss_dma_stats_ops);
+}
+
+/*
+ * nss_dma_stats_sync()
+ *	Handle the syncing of NSS DMA statistics.
+ */
+void nss_dma_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_dma_stats *nds)
+{
+	uint64_t *dma_stats;
+	uint32_t *msg_stats;
+	uint16_t i = 0;
+
+	spin_lock_bh(&nss_dma_stats_lock);
+
+	msg_stats = (uint32_t *)nds;
+	dma_stats = nss_dma_stats;
+
+	for (i = 0; i < NSS_DMA_STATS_MAX; i++, dma_stats++, msg_stats++) {
+		*dma_stats += *msg_stats;
+	}
+
+	spin_unlock_bh(&nss_dma_stats_lock);
+}
+
+/*
+ * nss_dma_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_dma_stats_notify(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_dma_stats_notification dma_stats;
+
+	spin_lock_bh(&nss_dma_stats_lock);
+	dma_stats.core_id = nss_ctx->id;
+	memcpy(dma_stats.stats_ctx, nss_dma_stats, sizeof(dma_stats.stats_ctx));
+	spin_unlock_bh(&nss_dma_stats_lock);
+
+	atomic_notifier_call_chain(&nss_dma_stats_notifier, NSS_STATS_EVENT_NOTIFY, &dma_stats);
+}
+
+/*
+ * nss_dma_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_dma_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_dma_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_dma_stats_unregister_notifier);
+
+/*
+ * nss_dma_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_dma_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_dma_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_dma_stats_register_notifier);
diff --git a/qca-nss-drv/nss_dma_stats.h b/qca-nss-drv/nss_dma_stats.h
new file mode 100755
index 0000000..a7fc1d8
--- /dev/null
+++ b/qca-nss-drv/nss_dma_stats.h
@@ -0,0 +1,31 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_DMA_STATS_H
+#define __NSS_DMA_STATS_H
+
+#include <nss_cmn.h>
+
+/*
+ * DMA statistics APIs
+ */
+extern void nss_dma_stats_notify(struct nss_ctx_instance *nss_ctx);
+extern void nss_dma_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_dma_stats *nds);
+extern void nss_dma_stats_dentry_create(void);
+
+#endif /* __NSS_DMA_STATS_H */
diff --git a/qca-nss-drv/nss_dma_strings.c b/qca-nss-drv/nss_dma_strings.c
new file mode 100755
index 0000000..402afc7
--- /dev/null
+++ b/qca-nss-drv/nss_dma_strings.c
@@ -0,0 +1,88 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_dma_stats.h"
+
+/*
+ * nss_dma_strings_stats
+ *	DMA statistics strings.
+ */
+struct nss_stats_info nss_dma_strings_stats[NSS_DMA_STATS_MAX] = {
+	{"rx_pkts"		, NSS_STATS_TYPE_COMMON},
+	{"rx_byts"		, NSS_STATS_TYPE_COMMON},
+	{"tx_pkts"		, NSS_STATS_TYPE_COMMON},
+	{"tx_byts"		, NSS_STATS_TYPE_COMMON},
+	{"rx_queue[0]_drops"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue[1]_drops"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue[2]_drops"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue[3]_drops"	, NSS_STATS_TYPE_DROP},
+	{"no_req"		, NSS_STATS_TYPE_SPECIAL},
+	{"no_desc"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_nexthop"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_nexthop_queue"	, NSS_STATS_TYPE_SPECIAL},
+	{"fail_linear_sz"	, NSS_STATS_TYPE_SPECIAL},
+	{"fail_linear_alloc"	, NSS_STATS_TYPE_SPECIAL},
+	{"fail_linear_no_sg"	, NSS_STATS_TYPE_SPECIAL},
+	{"fail_split_sz"	, NSS_STATS_TYPE_SPECIAL},
+	{"fail_split_alloc"	, NSS_STATS_TYPE_SPECIAL},
+	{"fail_sync_alloc"	, NSS_STATS_TYPE_SPECIAL},
+	{"fail_ctx_active"	, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[0]"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[1]"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[2]"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[3]"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[4]"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[5]"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[6]"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[7]"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[8]"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[9]"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[10]"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[11]"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[12]"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[13]"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[14]"		, NSS_STATS_TYPE_SPECIAL},
+	{"fail_hw[15]"		, NSS_STATS_TYPE_SPECIAL},
+};
+
+
+/*
+ * nss_dma_strings_read()
+ *	Read DMA node statistics names
+ */
+static ssize_t nss_dma_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_dma_strings_stats, NSS_DMA_STATS_MAX);
+}
+
+/*
+ * nss_dma_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(dma);
+
+/*
+ * nss_dma_strings_dentry_create()
+ *	Create DMA statistics strings debug entry.
+ */
+void nss_dma_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("dma", &nss_dma_strings_ops);
+}
diff --git a/qca-nss-drv/nss_dma_strings.h b/qca-nss-drv/nss_dma_strings.h
new file mode 100755
index 0000000..1450216
--- /dev/null
+++ b/qca-nss-drv/nss_dma_strings.h
@@ -0,0 +1,25 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_DMA_STRINGS_H
+#define __NSS_DMA_STRINGS_H
+
+extern struct nss_stats_info nss_dma_strings_stats[NSS_DMA_STATS_MAX];
+extern void nss_dma_strings_dentry_create(void);
+
+#endif /* __NSS_DMA_STRINGS_H */
diff --git a/qca-nss-drv/nss_drv_stats.c b/qca-nss-drv/nss_drv_stats.c
new file mode 100644
index 0000000..30b8cb5
--- /dev/null
+++ b/qca-nss-drv/nss_drv_stats.c
@@ -0,0 +1,166 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_drv_strings.h"
+#include "nss_drv_stats.h"
+
+/*
+ * nss_drv_stats_read()
+ *	Read HLOS driver stats.
+ */
+static ssize_t nss_drv_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * Max output lines = #stats * NSS_MAX_CORES  +
+	 * few blank lines for banner printing + Number of Extra outputlines for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_DRV_STATS_MAX * NSS_MAX_CORES + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_DRV_STATS_MAX * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "drv", NSS_STATS_SINGLE_CORE);
+	for (i = 0; (i < NSS_DRV_STATS_MAX); i++) {
+		stats_shadow[i] = NSS_PKT_STATS_READ(&nss_top_main.stats_drv[i]);
+	}
+
+	size_wr += nss_stats_print("drv", NULL, NSS_STATS_SINGLE_INSTANCE, nss_drv_strings_stats, stats_shadow, NSS_DRV_STATS_MAX, lbuf, size_wr, size_al);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * drv_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(drv);
+
+/*
+ * nss_drv_stats_dentry_create()
+ *	Create DRV statistics debug entry.
+ */
+void nss_drv_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("drv", &nss_drv_stats_ops);
+}
+
+/*
+ * TODO: Move this (nss_wt_stats_read) function to new file (nss_wt_stats.c)
+ */
+
+/*
+ * nss_wt_stats_read()
+ *	Reads and formats worker thread statistics and outputs them to ubuf
+ */
+ssize_t nss_wt_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	struct nss_stats_data *data = fp->private_data;
+	struct nss_ctx_instance *nss_ctx = data->nss_ctx;
+	struct nss_project_irq_stats *shadow;
+	uint32_t thread_count = nss_ctx->worker_thread_count;
+	uint32_t irq_count = nss_ctx->irq_count;
+
+	/*
+	 * Three lines for each IRQ
+	 */
+	uint32_t max_output_lines = thread_count * 3 * irq_count;
+	size_t size_al = max_output_lines * NSS_STATS_MAX_STR_LENGTH;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	char *lbuf;
+	int i;
+	int j;
+
+	lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer\n");
+		return 0;
+	}
+
+	shadow = kzalloc(thread_count * irq_count * sizeof(struct nss_project_irq_stats), GFP_KERNEL);
+	if (unlikely(!shadow)) {
+		nss_warning("Could not allocate memory for stats shadow\n");
+		kfree(lbuf);
+		return 0;
+	}
+
+	spin_lock_bh(&nss_top_main.stats_lock);
+	if (unlikely(!nss_ctx->wt_stats)) {
+		spin_unlock_bh(&nss_top_main.stats_lock);
+		nss_warning("Worker thread statistics not allocated\n");
+		kfree(lbuf);
+		kfree(shadow);
+		return 0;
+	}
+	for (i = 0; i < thread_count; ++i) {
+
+		/*
+		 * The statistics shadow is an array with thread_count * irq_count
+		 * items in it. Each item is located at the index:
+		 *      (thread number) * (irq_count) + (irq number)
+		 * thus simulating a two-dimensional array.
+		 */
+		for (j = 0; j < irq_count; ++j) {
+			shadow[i * irq_count + j] = nss_ctx->wt_stats[i].irq_stats[j];
+		}
+	}
+	spin_unlock_bh(&nss_top_main.stats_lock);
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "worker thread", NSS_STATS_SINGLE_CORE);
+	for (i = 0; i < thread_count; ++i) {
+		for (j = 0; j < irq_count; ++j) {
+			struct nss_project_irq_stats *is = &(shadow[i * irq_count + j]);
+			if (!(is->count)) {
+				continue;
+			}
+
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+				"t-%d:irq-%d callback: 0x%x, count: %llu\n",
+				i, j, is->callback, is->count);
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+				"t-%d:irq-%d tick min: %10u  avg: %10u  max:%10u\n",
+				i, j, is->ticks_min, is->ticks_avg, is->ticks_max);
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+				"t-%d:irq-%d insn min: %10u  avg: %10u  max:%10u\n\n",
+				i, j, is->insn_min, is->insn_avg, is->insn_max);
+		}
+	}
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(shadow);
+
+	return bytes_read;
+}
diff --git a/qca-nss-drv/nss_drv_stats.h b/qca-nss-drv/nss_drv_stats.h
new file mode 100644
index 0000000..543dd5c
--- /dev/null
+++ b/qca-nss-drv/nss_drv_stats.h
@@ -0,0 +1,80 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_drv_stats.h
+ *	NSS driver stats header file.
+ */
+
+#ifndef __NSS_DRV_STATS_H
+#define __NSS_DRV_STATS_H
+
+#include <linux/debugfs.h>
+
+/*
+ * HLOS driver statistics
+ *
+ * WARNING: There is a 1:1 mapping between values below and corresponding
+ *	stats string array in nss_stats.c.
+ */
+enum NSS_DRV_STATS {
+	NSS_DRV_STATS_NBUF_ALLOC_FAILS = 0,	/* NBUF allocation errors */
+	NSS_DRV_STATS_PAGED_BUF_ALLOC_FAILS,	/* Paged buf allocation errors */
+	NSS_DRV_STATS_TX_QUEUE_FULL_0,		/* Tx queue full for Core 0*/
+	NSS_DRV_STATS_TX_QUEUE_FULL_1,		/* Tx queue full for Core 1*/
+	NSS_DRV_STATS_TX_EMPTY,			/* H2N Empty buffers */
+	NSS_DRV_STATS_PAGED_TX_EMPTY,		/* H2N Paged Empty buffers */
+	NSS_DRV_STATS_TX_PACKET,		/* H2N Data packets */
+	NSS_DRV_STATS_TX_CMD_REQ,		/* H2N Control packets */
+	NSS_DRV_STATS_TX_CRYPTO_REQ,		/* H2N Crypto requests */
+	NSS_DRV_STATS_TX_BUFFER_REUSE,		/* H2N Reuse buffer count */
+	NSS_DRV_STATS_RX_EMPTY,			/* N2H Empty buffers */
+	NSS_DRV_STATS_RX_PACKET,		/* N2H Data packets */
+	NSS_DRV_STATS_RX_EXT_PACKET,		/* N2H EXT type packets */
+	NSS_DRV_STATS_RX_CMD_RESP,		/* N2H Command responses */
+	NSS_DRV_STATS_RX_STATUS,		/* N2H Status packets */
+	NSS_DRV_STATS_RX_CRYPTO_RESP,		/* N2H Crypto responses */
+	NSS_DRV_STATS_RX_VIRTUAL,		/* N2H Virtual packets */
+	NSS_DRV_STATS_TX_SIMPLE,		/* H2N Simple SKB Packets */
+	NSS_DRV_STATS_TX_NR_FRAGS,		/* H2N NR Frags SKB Packets */
+	NSS_DRV_STATS_TX_FRAGLIST,		/* H2N Fraglist SKB Packets */
+	NSS_DRV_STATS_RX_SIMPLE,		/* N2H Simple SKB Packets */
+	NSS_DRV_STATS_RX_NR_FRAGS,		/* N2H NR Frags SKB Packets */
+	NSS_DRV_STATS_RX_SKB_FRAGLIST,		/* N2H Fraglist SKB Packets */
+	NSS_DRV_STATS_RX_BAD_DESCRIPTOR,	/* N2H Bad descriptor reads */
+	NSS_DRV_STATS_RX_INVALID_INTERFACE,	/* N2H Received descriptor for invalid interface */
+	NSS_DRV_STATS_RX_INVALID_CORE_ID,	/* N2H Received packet for invalid core_id */
+	NSS_DRV_STATS_RX_INVALID_BUFFER_TYPE,	/* N2H Received packet for invalid buffer type */
+	NSS_DRV_STATS_NSS_SKB_COUNT,		/* NSS SKB Pool Count */
+	NSS_DRV_STATS_CHAIN_SEG_PROCESSED,	/* N2H SKB Chain Processed Count */
+	NSS_DRV_STATS_FRAG_SEG_PROCESSED,	/* N2H Frag Processed Count */
+	NSS_DRV_STATS_TX_CMD_QUEUE_FULL,	/* Tx H2N Control packets fail due to queue full */
+#ifdef NSS_MULTI_H2N_DATA_RING_SUPPORT
+	NSS_DRV_STATS_TX_PACKET_QUEUE_0,	/* H2N Data packets on queue0 */
+	NSS_DRV_STATS_TX_PACKET_QUEUE_1,	/* H2N Data packets on queue1 */
+	NSS_DRV_STATS_TX_PACKET_QUEUE_2,	/* H2N Data packets on queue2 */
+	NSS_DRV_STATS_TX_PACKET_QUEUE_3,	/* H2N Data packets on queue3 */
+	NSS_DRV_STATS_TX_PACKET_QUEUE_4,	/* H2N Data packets on queue4 */
+	NSS_DRV_STATS_TX_PACKET_QUEUE_5,	/* H2N Data packets on queue5 */
+	NSS_DRV_STATS_TX_PACKET_QUEUE_6,	/* H2N Data packets on queue6 */
+	NSS_DRV_STATS_TX_PACKET_QUEUE_7,	/* H2N Data packets on queue7 */
+#endif
+	NSS_DRV_STATS_MAX,
+};
+
+extern void nss_drv_stats_dentry_create(void);
+extern ssize_t nss_wt_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos);
+#endif /* __NSS_DRV_STATS_H */
diff --git a/qca-nss-drv/nss_drv_strings.c b/qca-nss-drv/nss_drv_strings.c
new file mode 100644
index 0000000..2595615
--- /dev/null
+++ b/qca-nss-drv/nss_drv_strings.c
@@ -0,0 +1,92 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+
+/*
+ * nss_drv_strings_stats
+ *	Host driver stats names.
+ */
+struct nss_stats_info nss_drv_strings_stats[NSS_DRV_STATS_MAX] = {
+	{"nbuf_alloc_errors"		, NSS_STATS_TYPE_ERROR},
+	{"paged_buf_alloc_errors"	, NSS_STATS_TYPE_ERROR},
+	{"tx_queue_full[0]"		, NSS_STATS_TYPE_ERROR},
+	{"tx_queue_full[1]"		, NSS_STATS_TYPE_ERROR},
+	{"tx_buffers_empty"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_paged_buffers_empty"	, NSS_STATS_TYPE_SPECIAL},
+	{"tx_buffer_pkt"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_buffers_cmd"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_buffers_crypto"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_buffers_reuse"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_buffers_empty"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_buffers_pkt"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_buffers_ext_pkt"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_buffers_cmd_resp"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_buffers_status_sync"	, NSS_STATS_TYPE_SPECIAL},
+	{"rx_buffers_crypto"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_buffers_virtual"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_skb_simple"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_skb_nr_frags"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_skb_fraglist"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_skb_simple"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_skb_nr_frags"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_skb_fraglist"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_bad_desciptor"		, NSS_STATS_TYPE_ERROR},
+	{"invalid_interface"            , NSS_STATS_TYPE_ERROR},
+	{"invalid_core_id"              , NSS_STATS_TYPE_ERROR},
+	{"invalid_buffer_type"          , NSS_STATS_TYPE_ERROR},
+	{"nss_skb_count"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_chain_seg_processed"	, NSS_STATS_TYPE_SPECIAL},
+	{"rx_frag_seg_processed"	, NSS_STATS_TYPE_SPECIAL},
+	{"tx_buffers_cmd_queue_full"	, NSS_STATS_TYPE_ERROR},
+#ifdef NSS_MULTI_H2N_DATA_RING_SUPPORT
+	{"tx_buffers_data_queue[0]"	, NSS_STATS_TYPE_SPECIAL},
+	{"tx_buffers_data_queue[1]"	, NSS_STATS_TYPE_SPECIAL},
+	{"tx_buffers_data_queue[2]"	, NSS_STATS_TYPE_SPECIAL},
+	{"tx_buffers_data_queue[3]"	, NSS_STATS_TYPE_SPECIAL},
+	{"tx_buffers_data_queue[4]"	, NSS_STATS_TYPE_SPECIAL},
+	{"tx_buffers_data_queue[5]"	, NSS_STATS_TYPE_SPECIAL},
+	{"tx_buffers_data_queue[6]"	, NSS_STATS_TYPE_SPECIAL},
+	{"tx_buffers_data_queue[7]"	, NSS_STATS_TYPE_SPECIAL},
+#endif
+};
+
+/*
+ * nss_drv_strings_read()
+ *	Read drv node statistics names.
+ */
+static ssize_t nss_drv_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_drv_strings_stats, NSS_DRV_STATS_MAX);
+}
+
+/*
+ * nss_drv_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(drv);
+
+/*
+ * nss_drv_strings_dentry_create()
+ *      Create drv statistics strings debug entry.
+ */
+void nss_drv_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("drv", &nss_drv_strings_ops);
+}
diff --git a/qca-nss-drv/nss_drv_strings.h b/qca-nss-drv/nss_drv_strings.h
new file mode 100644
index 0000000..72a1fd7
--- /dev/null
+++ b/qca-nss-drv/nss_drv_strings.h
@@ -0,0 +1,26 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_DRV_STRINGS_H
+#define __NSS_DRV_STRINGS_H
+
+extern struct nss_stats_info nss_drv_strings_stats[NSS_DRV_STATS_MAX];
+
+extern void nss_drv_strings_dentry_create(void);
+
+#endif /* __NSS_DRV_STRINGS_H */
diff --git a/qca-nss-drv/nss_dscp_map.h b/qca-nss-drv/nss_dscp_map.h
new file mode 100644
index 0000000..441dc11
--- /dev/null
+++ b/qca-nss-drv/nss_dscp_map.h
@@ -0,0 +1,212 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_dscp_map.h
+ *	NSS dscp map parse APIs
+ */
+
+#include "nss_tx_rx_common.h"
+
+#define NSS_DSCP_MAP_PARAM_FIELD_COUNT 3
+#define NSS_DSCP_MAP_ARRAY_SIZE 64
+#define NSS_DSCP_MAP_PRIORITY_MAX NSS_MAX_NUM_PRI
+
+/*
+ * nss dscp map entry structure.
+ */
+struct nss_dscp_map_entry {
+	uint8_t action;		/* Action associated with the DSCP value.*/
+	uint8_t priority;	/* Priority associated with the DSCP value. */
+};
+
+/*
+ * nss dscp map parse output.
+ */
+struct nss_dscp_map_parse {
+	uint8_t dscp;		/* Parsed dscp value */
+	uint8_t action;		/* Parsed action value */
+	uint8_t priority;	/* Parsed priority value */
+};
+
+/*
+ * nss_dscp_map_print()
+ *	Sysctl handler for printing dscp/pri mapping.
+ */
+static int nss_dscp_map_print(struct ctl_table *ctl, void __user *buffer, size_t *lenp,
+				loff_t *ppos, struct nss_dscp_map_entry *mapping)
+{
+	char *r_buf;
+	int i, len;
+	size_t cp_bytes = 0;
+
+	/*
+	 * (64 * 8) + 22 bytes for the buffer size is sufficient to write
+	 * the table including the spaces and new line characters.
+	 */
+	r_buf = kzalloc(((NSS_DSCP_MAP_ARRAY_SIZE * 8) + 22) * sizeof(char), GFP_KERNEL);
+	if (!r_buf) {
+		nss_warning("Failed to alloc buffer to print dscp map table\n");
+		return -EFAULT;
+	}
+
+	/*
+	 * Write the priority values to the first line of the output.
+	 */
+	len = scnprintf(r_buf + cp_bytes, 11, "%s:  ", "priority");
+	cp_bytes += len;
+	for (i = 0; i < NSS_DSCP_MAP_ARRAY_SIZE; i++) {
+		len = scnprintf(r_buf + cp_bytes, 4, "%d ", mapping[i].priority);
+		if (!len) {
+			nss_warning("failed to read from buffer %d\n", mapping[i].priority);
+			kfree(r_buf);
+			return -EFAULT;
+		}
+		cp_bytes += len;
+	}
+
+	/*
+	 * Add new line character at the end.
+	 */
+	len = scnprintf(r_buf + cp_bytes, 4, "\n");
+	cp_bytes += len;
+
+	/*
+	 * Write the action values to the second line of the output.
+	 */
+	len = scnprintf(r_buf + cp_bytes, 11, "%s:    ", "action");
+	cp_bytes += len;
+	for (i = 0; i < NSS_DSCP_MAP_ARRAY_SIZE; i++) {
+		len = scnprintf(r_buf + cp_bytes, 4, "%d ", mapping[i].action);
+		if (!len) {
+			nss_warning("failed to read from buffer %d\n", mapping[i].action);
+			kfree(r_buf);
+			return -EFAULT;
+		}
+		cp_bytes += len;
+	}
+
+	/*
+	 * Add new line character at the end.
+	 */
+	len = scnprintf(r_buf + cp_bytes, 4, "\n");
+	cp_bytes += len;
+
+	cp_bytes = simple_read_from_buffer(buffer, *lenp, ppos, r_buf, cp_bytes);
+	*lenp = cp_bytes;
+	kfree(r_buf);
+	return 0;
+}
+
+/*
+ * nss_dscp_map_parse()
+ *	Sysctl handler for dscp/pri mappings.
+ */
+static int nss_dscp_map_parse(struct ctl_table *ctl, void __user *buffer, size_t *lenp,
+				loff_t *ppos, struct nss_dscp_map_parse *out)
+{
+	int count;
+	size_t cp_bytes = 0;
+	char w_buf[7];
+	loff_t w_offset = 0;
+	char *str;
+	char *tokens[NSS_DSCP_MAP_PARAM_FIELD_COUNT];
+	unsigned int dscp, priority, action;
+	int ret;
+
+	/*
+	 * Buffer length cannot be more than 7 and less than 6.
+	 */
+	if (*lenp < 6 || *lenp > 7) {
+		nss_warning("Buffer is not correct. Invalid lenght: %d\n", (int)*lenp);
+		return -EINVAL;
+	}
+
+	/*
+	 * It's a write operation
+	 */
+	cp_bytes = simple_write_to_buffer(w_buf, *lenp, &w_offset, buffer, 7);
+	if (cp_bytes != *lenp) {
+		nss_warning("failed to write to buffer\n");
+		return -EFAULT;
+	}
+
+	count = 0;
+	str = w_buf;
+	tokens[count] = strsep(&str, " ");
+	while (tokens[count] != NULL) {
+		count++;
+		if (count == NSS_DSCP_MAP_PARAM_FIELD_COUNT) {
+			nss_warning("maximum allowed field count is %d\n", NSS_DSCP_MAP_PARAM_FIELD_COUNT);
+			break;
+		}
+		tokens[count] = strsep(&str, " ");
+	}
+
+	/*
+	 * Did we read enough number of parameters from the command line.
+	 * There must be 2 parameters.
+	 */
+	if (count != NSS_DSCP_MAP_PARAM_FIELD_COUNT) {
+		nss_warning("param fields are less than expected: %d\n", count);
+		return -EINVAL;
+	}
+
+	/*
+	 * Write the tokens to integers.
+	 */
+	ret = sscanf(tokens[0], "%u", &dscp);
+	if (ret != 1) {
+		nss_warning("failed to write the dscp token to integer\n");
+		return -EFAULT;
+	}
+
+	ret = sscanf(tokens[1], "%u", &action);
+	if (ret != 1) {
+		nss_warning("failed to write the action token to integer\n");
+		return -EFAULT;
+	}
+
+	ret = sscanf(tokens[2], "%u", &priority);
+	if (ret != 1) {
+		nss_warning("failed to write the priority token to integer\n");
+		return -EFAULT;
+	}
+
+	/*
+	 * dscp value cannot be higher than 63.
+	 */
+	if (dscp >= NSS_DSCP_MAP_ARRAY_SIZE) {
+		nss_warning("invalid dscp value: %d\n", dscp);
+		return -EINVAL;
+	}
+
+	/*
+	 * Priority must be less than NSS_DSCP_MAP_PRIORITY_MAX which is 4.
+	 */
+	if (priority >= NSS_DSCP_MAP_PRIORITY_MAX) {
+		nss_warning("invalid priority value: %d\n", priority);
+		return -EINVAL;
+	}
+
+	nss_info("dscp: %d action: %d priority: %d\n", dscp, action, priority);
+
+	out->dscp = dscp;
+	out->action = action;
+	out->priority = priority;
+
+	return 0;
+}
diff --git a/qca-nss-drv/nss_dtls.c b/qca-nss-drv/nss_dtls.c
new file mode 100644
index 0000000..6d7c1a1
--- /dev/null
+++ b/qca-nss-drv/nss_dtls.c
@@ -0,0 +1,468 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_dtls_stats.h"
+#include "nss_dtls_log.h"
+
+#define NSS_DTLS_TX_TIMEOUT 3000 /* 3 Seconds */
+
+/*
+ * Data structures to store DTLS nss debug stats
+ */
+static DEFINE_SPINLOCK(nss_dtls_session_stats_lock);
+static struct nss_dtls_stats_session session_stats[NSS_MAX_DTLS_SESSIONS];
+
+/*
+ * Private data structure
+ */
+static struct nss_dtls_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+	void *cb;
+	void *app_data;
+} dtls_pvt;
+
+/*
+ * nss_dtls_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static bool nss_dtls_verify_if_num(uint32_t if_num)
+{
+	if (nss_is_dynamic_interface(if_num) == false)
+		return false;
+
+	if (nss_dynamic_interface_get_type(nss_dtls_get_context(), if_num)
+	    != NSS_DYNAMIC_INTERFACE_TYPE_DTLS)
+		return false;
+
+	return true;
+}
+
+/*
+ * nss_dtls_session_stats_sync
+ *	Per DTLS session debug stats
+ */
+static void nss_dtls_session_stats_sync(struct nss_ctx_instance *nss_ctx,
+					struct nss_dtls_session_stats *stats_msg,
+					uint16_t if_num)
+{
+	int i;
+	struct nss_dtls_stats_session *s = NULL;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	spin_lock_bh(&nss_dtls_session_stats_lock);
+	for (i = 0; i < NSS_MAX_DTLS_SESSIONS; i++) {
+		if (session_stats[i].if_num != if_num) {
+			continue;
+		}
+
+		s = &session_stats[i];
+		break;
+	}
+
+	if (!s) {
+		spin_unlock_bh(&nss_dtls_session_stats_lock);
+		return;
+	}
+
+	s->stats[NSS_DTLS_STATS_SESSION_RX_PKTS] += stats_msg->node_stats.rx_packets;
+	s->stats[NSS_DTLS_STATS_SESSION_TX_PKTS] += stats_msg->node_stats.tx_packets;
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		s->stats[NSS_DTLS_STATS_SESSION_RX_QUEUE_0_DROPPED + i] += stats_msg->node_stats.rx_dropped[i];
+	}
+	s->stats[NSS_DTLS_STATS_SESSION_RX_AUTH_DONE] += stats_msg->rx_auth_done;
+	s->stats[NSS_DTLS_STATS_SESSION_TX_AUTH_DONE] += stats_msg->tx_auth_done;
+	s->stats[NSS_DTLS_STATS_SESSION_RX_CIPHER_DONE] += stats_msg->rx_cipher_done;
+	s->stats[NSS_DTLS_STATS_SESSION_TX_CIPHER_DONE] += stats_msg->tx_cipher_done;
+	s->stats[NSS_DTLS_STATS_SESSION_RX_CBUF_ALLOC_FAIL] += stats_msg->rx_cbuf_alloc_fail;
+	s->stats[NSS_DTLS_STATS_SESSION_TX_CBUF_ALLOC_FAIL] += stats_msg->tx_cbuf_alloc_fail;
+	s->stats[NSS_DTLS_STATS_SESSION_TX_CENQUEUE_FAIL] += stats_msg->tx_cenqueue_fail;
+	s->stats[NSS_DTLS_STATS_SESSION_RX_CENQUEUE_FAIL] += stats_msg->rx_cenqueue_fail;
+	s->stats[NSS_DTLS_STATS_SESSION_TX_DROPPED_HROOM] += stats_msg->tx_dropped_hroom;
+	s->stats[NSS_DTLS_STATS_SESSION_TX_DROPPED_TROOM] += stats_msg->tx_dropped_troom;
+	s->stats[NSS_DTLS_STATS_SESSION_TX_FORWARD_ENQUEUE_FAIL] += stats_msg->tx_forward_enqueue_fail;
+	s->stats[NSS_DTLS_STATS_SESSION_RX_FORWARD_ENQUEUE_FAIL] += stats_msg->rx_forward_enqueue_fail;
+	s->stats[NSS_DTLS_STATS_SESSION_RX_INVALID_VERSION] += stats_msg->rx_invalid_version;
+	s->stats[NSS_DTLS_STATS_SESSION_RX_INVALID_EPOCH] += stats_msg->rx_invalid_epoch;
+	s->stats[NSS_DTLS_STATS_SESSION_RX_MALFORMED] += stats_msg->rx_malformed;
+	s->stats[NSS_DTLS_STATS_SESSION_RX_CIPHER_FAIL] += stats_msg->rx_cipher_fail;
+	s->stats[NSS_DTLS_STATS_SESSION_RX_AUTH_FAIL] += stats_msg->rx_auth_fail;
+	s->stats[NSS_DTLS_STATS_SESSION_RX_CAPWAP_CLASSIFY_FAIL] += stats_msg->rx_capwap_classify_fail;
+	s->stats[NSS_DTLS_STATS_SESSION_RX_SINGLE_REC_DGRAM] += stats_msg->rx_single_rec_dgram;
+	s->stats[NSS_DTLS_STATS_SESSION_RX_MULTI_REC_DGRAM] += stats_msg->rx_multi_rec_dgram;
+	s->stats[NSS_DTLS_STATS_SESSION_RX_REPLAY_FAIL] += stats_msg->rx_replay_fail;
+	s->stats[NSS_DTLS_STATS_SESSION_RX_REPLAY_DUPLICATE] += stats_msg->rx_replay_duplicate;
+	s->stats[NSS_DTLS_STATS_SESSION_RX_REPLAY_OUT_OF_WINDOW] += stats_msg->rx_replay_out_of_window;
+	s->stats[NSS_DTLS_STATS_SESSION_OUTFLOW_QUEUE_FULL] += stats_msg->outflow_queue_full;
+	s->stats[NSS_DTLS_STATS_SESSION_DECAP_QUEUE_FULL] += stats_msg->decap_queue_full;
+	s->stats[NSS_DTLS_STATS_SESSION_PBUF_ALLOC_FAIL] += stats_msg->pbuf_alloc_fail;
+	s->stats[NSS_DTLS_STATS_SESSION_PBUF_COPY_FAIL] += stats_msg->pbuf_copy_fail;
+	s->stats[NSS_DTLS_STATS_SESSION_EPOCH] = stats_msg->epoch;
+	s->stats[NSS_DTLS_STATS_SESSION_TX_SEQ_HIGH] = stats_msg->tx_seq_high;
+	s->stats[NSS_DTLS_STATS_SESSION_TX_SEQ_LOW] = stats_msg->tx_seq_low;
+	spin_unlock_bh(&nss_dtls_session_stats_lock);
+}
+
+/*
+ * nss_dtls_session_stats_get()
+ *	Get session DTLS statitics.
+ */
+void nss_dtls_session_stats_get(struct nss_dtls_stats_session *stats)
+{
+	int i;
+
+	if (!stats) {
+		nss_warning("No memory to copy dtls session stats");
+		return;
+	}
+
+	spin_lock_bh(&nss_dtls_session_stats_lock);
+	for (i = 0; i < NSS_MAX_DTLS_SESSIONS; i++) {
+		if (session_stats[i].valid) {
+			memcpy(stats, &session_stats[i],
+			       sizeof(struct nss_dtls_stats_session));
+			stats++;
+		}
+	}
+	spin_unlock_bh(&nss_dtls_session_stats_lock);
+}
+
+/*
+ * nss_dtls_handler()
+ *	Handle NSS -> HLOS messages for dtls tunnel
+ */
+static void nss_dtls_handler(struct nss_ctx_instance *nss_ctx,
+			     struct nss_cmn_msg *ncm,
+			     __attribute__((unused))void *app_data)
+{
+	struct nss_dtls_msg *ntm = (struct nss_dtls_msg *)ncm;
+	void *ctx;
+
+	nss_dtls_msg_callback_t cb;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	BUG_ON(!nss_dtls_verify_if_num(ncm->interface));
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_DTLS_MSG_MAX) {
+		nss_warning("%px: received invalid message %d "
+			    "for DTLS interface %d",
+			    nss_ctx, ncm->type, ncm->interface);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_dtls_msg)) {
+		nss_warning("%px: dtls message length is invalid: %d",
+			    nss_ctx, ncm->len);
+		return;
+	}
+
+	switch (ntm->cm.type) {
+	case NSS_DTLS_MSG_SESSION_STATS:
+		nss_dtls_session_stats_sync(nss_ctx,
+					    &ntm->msg.stats,
+					    ncm->interface);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->dtls_msg_callback;
+		ncm->app_data = (nss_ptr_t)nss_ctx->subsys_dp_register[ncm->interface].app_data;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Trace messages.
+	 */
+	nss_dtls_log_rx_msg(ntm);
+
+	/*
+	 * callback
+	 */
+	cb = (nss_dtls_msg_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	/*
+	 * call dtls session callback
+	 */
+	if (!cb) {
+		nss_warning("%px: No callback for dtls session interface %d",
+			    nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb(ctx, ntm);
+}
+
+/*
+ * nss_dtls_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_dtls_callback(void *app_data, struct nss_dtls_msg *nim)
+{
+	nss_dtls_msg_callback_t callback = (nss_dtls_msg_callback_t)dtls_pvt.cb;
+	void *data = dtls_pvt.app_data;
+
+	dtls_pvt.cb = NULL;
+	dtls_pvt.app_data = NULL;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("dtls Error response %d\n", nim->cm.response);
+
+		dtls_pvt.response = NSS_TX_FAILURE;
+		if (callback) {
+			callback(data, nim);
+		}
+
+		complete(&dtls_pvt.complete);
+		return;
+	}
+
+	dtls_pvt.response = NSS_TX_SUCCESS;
+	if (callback) {
+		callback(data, nim);
+	}
+
+	complete(&dtls_pvt.complete);
+}
+
+/*
+ * nss_dtls_tx_buf()
+ *	Transmit buffer over DTLS interface
+ */
+nss_tx_status_t nss_dtls_tx_buf(struct sk_buff *skb, uint32_t if_num,
+				struct nss_ctx_instance *nss_ctx)
+{
+	BUG_ON(!nss_dtls_verify_if_num(if_num));
+
+	return nss_core_send_packet(nss_ctx, skb, if_num, H2N_BIT_FLAG_VIRTUAL_BUFFER | H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+EXPORT_SYMBOL(nss_dtls_tx_buf);
+
+/*
+ * nss_dtls_tx_msg()
+ *	Transmit a DTLS message to NSS firmware
+ */
+nss_tx_status_t nss_dtls_tx_msg(struct nss_ctx_instance *nss_ctx,
+				struct nss_dtls_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Sanity check the message
+	 */
+	BUG_ON(!nss_dtls_verify_if_num(ncm->interface));
+
+	if (ncm->type > NSS_DTLS_MSG_MAX) {
+		nss_warning("%px: dtls message type out of range: %d",
+			    nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_dtls_log_tx_msg(msg);
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_dtls_tx_msg);
+
+/*
+ * nss_dtls_tx_msg()
+ *	Transmit a DTLS message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_dtls_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_dtls_msg *msg)
+{
+
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&dtls_pvt.sem);
+	dtls_pvt.cb = (void *)msg->cm.cb;
+	dtls_pvt.app_data = (void *)msg->cm.app_data;
+
+	msg->cm.cb = (nss_ptr_t)nss_dtls_callback;
+	msg->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_dtls_tx_msg(nss_ctx, msg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: dtls_tx_msg failed\n", nss_ctx);
+		up(&dtls_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&dtls_pvt.complete, msecs_to_jiffies(NSS_DTLS_TX_TIMEOUT));
+
+	if (!ret) {
+		nss_warning("%px: DTLS msg tx failed due to timeout\n", nss_ctx);
+		dtls_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = dtls_pvt.response;
+	up(&dtls_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_dtls_tx_msg_sync);
+
+/*
+ ***********************************
+ * Register/Unregister/Miscellaneous APIs
+ ***********************************
+ */
+
+/*
+ * nss_dtls_register_if()
+ */
+struct nss_ctx_instance *nss_dtls_register_if(uint32_t if_num,
+					      nss_dtls_data_callback_t cb,
+					      nss_dtls_msg_callback_t ev_cb,
+					      struct net_device *netdev,
+					      uint32_t features,
+					      void *app_ctx)
+{
+	int32_t i;
+
+	struct nss_ctx_instance *nss_ctx = nss_dtls_get_context();
+
+	BUG_ON(!nss_dtls_verify_if_num(if_num));
+
+	spin_lock_bh(&nss_dtls_session_stats_lock);
+	for (i = 0; i < NSS_MAX_DTLS_SESSIONS; i++) {
+		if (!session_stats[i].valid) {
+			session_stats[i].valid = true;
+			session_stats[i].if_num = if_num;
+			session_stats[i].if_index = netdev->ifindex;
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_dtls_session_stats_lock);
+
+	if (i == NSS_MAX_DTLS_SESSIONS) {
+		nss_warning("%px: Cannot find free slot for "
+			    "DTLS session stats, I/F:%u\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	if (nss_ctx->subsys_dp_register[if_num].ndev) {
+		nss_warning("%px: Cannot find free slot for "
+			    "DTLS NSS I/F:%u\n", nss_ctx, if_num);
+
+		return NULL;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, cb, NULL, app_ctx, netdev, features);
+	nss_ctx->subsys_dp_register[if_num].type = NSS_DYNAMIC_INTERFACE_TYPE_DTLS;
+
+	nss_top_main.dtls_msg_callback = ev_cb;
+	nss_core_register_handler(nss_ctx, if_num, nss_dtls_handler, app_ctx);
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_dtls_register_if);
+
+/*
+ * nss_dtls_unregister_if()
+ */
+void nss_dtls_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_dtls_get_context();
+	int32_t i;
+
+	BUG_ON(!nss_dtls_verify_if_num(if_num));
+
+	spin_lock_bh(&nss_dtls_session_stats_lock);
+	for (i = 0; i < NSS_MAX_DTLS_SESSIONS; i++) {
+		if (session_stats[i].if_num == if_num) {
+			memset(&session_stats[i], 0,
+			       sizeof(struct nss_dtls_stats_session));
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_dtls_session_stats_lock);
+
+	if (i == NSS_MAX_DTLS_SESSIONS) {
+		nss_warning("%px: Cannot find debug stats for DTLS session %d\n", nss_ctx, if_num);
+		return;
+	}
+
+	if (!nss_ctx->subsys_dp_register[if_num].ndev) {
+		nss_warning("%px: Cannot find registered netdev for DTLS NSS I/F:%u\n", nss_ctx, if_num);
+
+		return;
+	}
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	nss_top_main.dtls_msg_callback = NULL;
+	nss_core_unregister_handler(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_dtls_unregister_if);
+
+/*
+ * nss_get_dtls_context()
+ */
+struct nss_ctx_instance *nss_dtls_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.dtls_handler_id];
+}
+EXPORT_SYMBOL(nss_dtls_get_context);
+
+/*
+ * nss_dtls_msg_init()
+ *	Initialize nss_dtls msg.
+ */
+void nss_dtls_msg_init(struct nss_dtls_msg *ncm, uint16_t if_num,
+		       uint32_t type, uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+EXPORT_SYMBOL(nss_dtls_msg_init);
+
+/*
+ * nss_dtls_get_ifnum_with_coreid()
+ */
+int32_t nss_dtls_get_ifnum_with_coreid(int32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_dtls_get_context();
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	return NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_dtls_get_ifnum_with_coreid);
+
+/*
+ * nss_dtls_register_handler()
+ */
+void nss_dtls_register_handler(void)
+{
+	sema_init(&dtls_pvt.sem, 1);
+	init_completion(&dtls_pvt.complete);
+
+	nss_dtls_stats_dentry_create();
+}
diff --git a/qca-nss-drv/nss_dtls_cmn.c b/qca-nss-drv/nss_dtls_cmn.c
new file mode 100644
index 0000000..024d217
--- /dev/null
+++ b/qca-nss-drv/nss_dtls_cmn.c
@@ -0,0 +1,451 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_dtls_cmn_log.h"
+#include "nss_dtls_cmn_stats.h"
+#include "nss_dtls_cmn_strings.h"
+
+#define NSS_DTLS_CMN_TX_TIMEOUT 3000 /* 3 Seconds */
+#define NSS_DTLS_CMN_INTERFACE_MAX_LONG BITS_TO_LONGS(NSS_MAX_NET_INTERFACES)
+
+/*
+ * Private data structure.
+ */
+static struct nss_dtls_cmn_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	enum nss_dtls_cmn_error resp;
+	unsigned long if_map[NSS_DTLS_CMN_INTERFACE_MAX_LONG];
+} dtls_cmn_pvt;
+
+/*
+ * nss_dtls_cmn_verify_ifnum()
+ *	Verify if the interface number is a DTLS interface.
+ */
+static bool nss_dtls_cmn_verify_ifnum(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	enum nss_dynamic_interface_type type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+
+	if (type == NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_INNER)
+		return true;
+
+	if (type == NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_OUTER)
+		return true;
+
+	if (if_num == NSS_DTLS_INTERFACE)
+		return true;
+
+	return false;
+}
+
+/*
+ * nss_dtls_cmn_handler()
+ *	Handle NSS -> HLOS messages for dtls tunnel.
+ */
+static void nss_dtls_cmn_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, void *data)
+{
+	nss_dtls_cmn_msg_callback_t cb;
+	void *app_data;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	nss_trace("%px: handle event for interface num :%u", nss_ctx, ncm->interface);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_DTLS_CMN_MSG_MAX) {
+		nss_warning("%px:Bad message type(%d) for DTLS interface %d", nss_ctx, ncm->type, ncm->interface);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_dtls_cmn_msg)) {
+		nss_warning("%px:Bad message length(%d)", nss_ctx, ncm->len);
+		return;
+	}
+
+	if (ncm->type == NSS_DTLS_CMN_MSG_TYPE_SYNC_STATS) {
+		nss_dtls_cmn_stats_sync(nss_ctx, ncm);
+		nss_dtls_cmn_stats_notify(nss_ctx, ncm->interface);
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->nss_rx_interface_handlers[ncm->interface].app_data;
+	}
+
+	/*
+	 * Log failures.
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Trace messages.
+	 */
+	nss_dtls_cmn_log_rx_msg((struct nss_dtls_cmn_msg *)ncm);
+
+	/*
+	 * Callback.
+	 */
+	cb = (nss_dtls_cmn_msg_callback_t)ncm->cb;
+	app_data = (void *)ncm->app_data;
+
+	/*
+	 * Call DTLS session callback.
+	 */
+	if (!cb) {
+		nss_warning("%px: No callback for dtls session interface %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	nss_trace("%px: calling dtlsmgr event handler(%u)", nss_ctx, ncm->interface);
+	cb(app_data, ncm);
+}
+
+/*
+ * nss_dtls_cmn_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_dtls_cmn_callback(void *app_data, struct nss_cmn_msg *ncm)
+{
+	/*
+	 * This callback is for synchronous operation. The caller sends its
+	 * response pointer which needs to be loaded with the response
+	 * data arriving from the NSS.
+	 */
+	enum nss_dtls_cmn_error *resp = (enum nss_dtls_cmn_error *)app_data;
+
+	*resp = (ncm->response == NSS_CMN_RESPONSE_ACK) ?  NSS_DTLS_CMN_ERROR_NONE : ncm->error;
+	complete(&dtls_cmn_pvt.complete);
+
+	return;
+}
+
+/*
+ * nss_dtls_cmn_ifmap_get()
+ *	Return DTLS common active interfaces map.
+ */
+unsigned long *nss_dtls_cmn_ifmap_get(void)
+{
+	return dtls_cmn_pvt.if_map;
+}
+
+/*
+ * nss_dtls_cmn_tx_buf()
+ *	Transmit buffer over DTLS interface.
+ */
+nss_tx_status_t nss_dtls_cmn_tx_buf(struct sk_buff *skb, uint32_t if_num, struct nss_ctx_instance *nss_ctx)
+{
+	if (!nss_dtls_cmn_verify_ifnum(nss_ctx, if_num))
+		return NSS_TX_FAILURE;
+
+	return nss_core_send_packet(nss_ctx, skb, if_num, H2N_BIT_FLAG_VIRTUAL_BUFFER | H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+EXPORT_SYMBOL(nss_dtls_cmn_tx_buf);
+
+/*
+ * nss_dtls_cmn_tx_msg()
+ *	Transmit a DTLS message to NSS firmware.
+ */
+nss_tx_status_t nss_dtls_cmn_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_dtls_cmn_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	if (ncm->type >= NSS_DTLS_CMN_MSG_MAX) {
+		nss_warning("%px: dtls message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	if (!nss_dtls_cmn_verify_ifnum(nss_ctx, ncm->interface)) {
+		nss_warning("%px: dtls message interface is bad: %u", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_dtls_cmn_log_tx_msg(msg);
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_dtls_cmn_tx_msg);
+
+/*
+ * nss_dtls_cmn_tx_msg_sync()
+ *	Transmit a DTLS message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_dtls_cmn_tx_msg_sync(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+					enum nss_dtls_cmn_msg_type type, uint16_t len,
+					struct nss_dtls_cmn_msg *ndcm, enum nss_dtls_cmn_error *resp)
+{
+	struct nss_dtls_cmn_msg ndcm_local;
+	nss_tx_status_t status;
+	int ret;
+
+	/*
+	 * Length of the message should be the based on type.
+	 */
+	if (len > sizeof(ndcm_local.msg)) {
+		nss_warning("%px: (%u)Bad message length(%u) for type (%d)", nss_ctx, if_num, len, type);
+		return NSS_TX_FAILURE_TOO_LARGE;
+	}
+
+	/*
+	 * Response buffer is a required for copying the response for message.
+	 */
+	if (!resp) {
+		nss_warning("%px: (%u)Response buffer is empty, type(%d)", nss_ctx, if_num, type);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	/*
+	 * TODO: this can be removed in future as we need to ensure that the response
+	 * memory is only updated when the current outstanding request is waiting.
+	 * This can be solved by introducing sequence no. in messages and only completing
+	 * the message if the sequence no. matches. For now this is solved by passing
+	 * a known memory dtls_cmn_pvt.resp.
+	 */
+	down(&dtls_cmn_pvt.sem);
+
+	/*
+	 * We need to copy the message content into the actual message
+	 * to be sent to NSS.
+	 */
+	nss_dtls_cmn_msg_init(&ndcm_local, if_num, type, len, nss_dtls_cmn_callback, &dtls_cmn_pvt.resp);
+	memcpy(&ndcm_local.msg, &ndcm->msg, len);
+
+	status = nss_dtls_cmn_tx_msg(nss_ctx, &ndcm_local);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: dtls_tx_msg failed", nss_ctx);
+		goto done;
+	}
+
+	ret = wait_for_completion_timeout(&dtls_cmn_pvt.complete, msecs_to_jiffies(NSS_DTLS_CMN_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: DTLS msg tx failed due to timeout", nss_ctx);
+		status = NSS_TX_FAILURE_NOT_READY;
+		goto done;
+	}
+
+	/*
+	 * Read memory barrier.
+	 */
+	smp_rmb();
+
+	/*
+	 * Copy the response received.
+	 */
+	*resp = dtls_cmn_pvt.resp;
+
+	/*
+	 * Only in case of non-error response we will
+	 * indicate success.
+	 */
+	if (dtls_cmn_pvt.resp != NSS_DTLS_CMN_ERROR_NONE)
+		status = NSS_TX_FAILURE;
+
+done:
+	up(&dtls_cmn_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_dtls_cmn_tx_msg_sync);
+
+/*
+ * nss_dtls_cmn_notify_register()
+ *	Register a handler for notification from NSS firmware.
+ */
+struct nss_ctx_instance *nss_dtls_cmn_notify_register(uint32_t if_num, nss_dtls_cmn_msg_callback_t ev_cb,
+							void *app_data)
+{
+	struct nss_ctx_instance *nss_ctx = nss_dtls_cmn_get_context();
+	uint32_t ret;
+
+	BUG_ON(!nss_ctx);
+
+	ret = nss_core_register_handler(nss_ctx, if_num, nss_dtls_cmn_handler, app_data);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to register event handler for interface(%u)", nss_ctx, if_num);
+		return NULL;
+	}
+
+	ret = nss_core_register_msg_handler(nss_ctx, if_num, ev_cb);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_core_unregister_handler(nss_ctx, if_num);
+		nss_warning("%px: unable to register event handler for interface(%u)", nss_ctx, if_num);
+		return NULL;
+	}
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_dtls_cmn_notify_register);
+
+/*
+ * nss_dtls_cmn_notify_unregister()
+ *	Unregister notification callback handler.
+ */
+void nss_dtls_cmn_notify_unregister(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_dtls_cmn_get_context();
+	uint32_t ret;
+
+	BUG_ON(!nss_ctx);
+
+	ret = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to unregister event handler for interface(%u)", nss_ctx, if_num);
+		return;
+	}
+
+	ret = nss_core_unregister_handler(nss_ctx, if_num);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to unregister event handler for interface(%u)", nss_ctx, if_num);
+		return;
+	}
+
+	return;
+}
+EXPORT_SYMBOL(nss_dtls_cmn_notify_unregister);
+
+/*
+ * nss_dtls_cmn_register_if()
+ *	Register data and event callback handlers for dynamic interface.
+ */
+struct nss_ctx_instance *nss_dtls_cmn_register_if(uint32_t if_num,
+						  nss_dtls_cmn_data_callback_t data_cb,
+						  nss_dtls_cmn_msg_callback_t ev_cb,
+						  struct net_device *netdev,
+						  uint32_t features,
+						  uint32_t type,
+						  void *app_data)
+{
+	struct nss_ctx_instance *nss_ctx = nss_dtls_cmn_get_context();
+	uint32_t ret;
+
+	if (!nss_dtls_cmn_verify_ifnum(nss_ctx, if_num)) {
+		nss_warning("%px: DTLS Interface is not dynamic:%u", nss_ctx, if_num);
+		return NULL;
+	}
+
+	if (nss_ctx->subsys_dp_register[if_num].ndev) {
+		nss_warning("%px: Cannot find free slot for DTLS NSS I/F:%u", nss_ctx, if_num);
+		return NULL;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, data_cb, NULL, app_data, netdev, features);
+	nss_ctx->subsys_dp_register[if_num].type = type;
+
+	ret = nss_core_register_handler(nss_ctx, if_num, nss_dtls_cmn_handler, app_data);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to register event handler for interface(%u)", nss_ctx, if_num);
+		return NULL;
+	}
+
+	ret = nss_core_register_msg_handler(nss_ctx, if_num, ev_cb);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_core_unregister_handler(nss_ctx, if_num);
+		nss_warning("%px: unable to register event handler for interface(%u)", nss_ctx, if_num);
+		return NULL;
+	}
+
+	/*
+	 * Atomically set the bitmap for the interface number.
+	 */
+	set_bit(if_num, dtls_cmn_pvt.if_map);
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_dtls_cmn_register_if);
+
+/*
+ * nss_dtls_cmn_unregister_if()
+ *	Unregister data and event callback handlers for the interface.
+ */
+void nss_dtls_cmn_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_dtls_cmn_get_context();
+	uint32_t ret;
+
+	if (!nss_ctx->subsys_dp_register[if_num].ndev) {
+		nss_warning("%px: Cannot find registered netdev for DTLS NSS I/F:%u", nss_ctx, if_num);
+		return;
+	}
+
+	/*
+	 * Atomically clear the bitmap for the interface number.
+	 */
+	clear_bit(if_num, dtls_cmn_pvt.if_map);
+
+	ret = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to unregister event handler for interface(%u)", nss_ctx, if_num);
+		return;
+	}
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+	nss_ctx->subsys_dp_register[if_num].type = 0;
+}
+EXPORT_SYMBOL(nss_dtls_cmn_unregister_if);
+
+/*
+ * nss_dtls_get_context()
+ *	Return DTLS NSS context.
+ */
+struct nss_ctx_instance *nss_dtls_cmn_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.dtls_handler_id];
+}
+EXPORT_SYMBOL(nss_dtls_cmn_get_context);
+
+/*
+ * nss_dtls_cmn_msg_init()
+ *	Initialize nss_dtls_cmn msg.
+ */
+void nss_dtls_cmn_msg_init(struct nss_dtls_cmn_msg *ncm, uint32_t if_num,
+		       uint32_t type, uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+EXPORT_SYMBOL(nss_dtls_cmn_msg_init);
+
+/*
+ * nss_dtls_cmn_get_ifnum()
+ *	Return DTLS interface number with coreid.
+ */
+int32_t nss_dtls_cmn_get_ifnum(int32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_dtls_cmn_get_context();
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	return NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_dtls_cmn_get_ifnum);
+
+/*
+ * nss_dtls_cmn_register_handler()
+ *	DTLS initialization.
+ */
+void nss_dtls_cmn_register_handler(void)
+{
+	sema_init(&dtls_cmn_pvt.sem, 1);
+	init_completion(&dtls_cmn_pvt.complete);
+	nss_dtls_cmn_stats_dentry_create();
+	nss_dtls_cmn_strings_dentry_create();
+}
diff --git a/qca-nss-drv/nss_dtls_cmn_log.c b/qca-nss-drv/nss_dtls_cmn_log.c
new file mode 100644
index 0000000..41ad37c
--- /dev/null
+++ b/qca-nss-drv/nss_dtls_cmn_log.c
@@ -0,0 +1,178 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_dtls_cmn_log.c
+ *	NSS DTLS common logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_dtls_cmn_log_message_types_str
+ *	DTLS common message strings
+ */
+static int8_t *nss_dtls_cmn_log_message_types_str[NSS_DTLS_CMN_MSG_MAX] __maybe_unused = {
+	"DTLS_CMN Configure Node",
+	"DTLS_CMN Configure Base Context Parameter",
+	"DTLS_CMN Configure DTLS Parameters",
+	"DTLS_CMN Switch DTLS Transform",
+	"DTLS_CMN Deconfigure Context",
+	"DTLS_CMN Synchronize Stats",
+	"DTLS_CMN Node Statistics"
+};
+
+/*
+ * nss_dtls_cmn_log_error_response_types_str
+ *	Strings for error types for DTLS common messages
+ */
+static int8_t *nss_dtls_cmn_log_error_response_types_str[NSS_DTLS_CMN_ERROR_MAX] __maybe_unused = {
+	"DTLS_CMN No Error",
+	"DTLS_CMN Unknown MEssage",
+	"DTLS_CMN Invalid Destination Interface",
+	"DTLS_CMN Invalid Source Interface",
+	"DTLS_CMN Invalid Crypto",
+	"DTLS_CMN Invalid Version",
+	"DTLS_CMN Invalid Context Type",
+	"DTLS_CMN Invalid Context Words",
+	"DTLS_CMN Hardware Context Alloc Fail",
+	"DTLS_CMN Copy Context Failure",
+	"DTLS_CMN Switch Hardware Context Fail",
+	"DTLS_CMN Already Configured",
+	"DTLS_CMN No Memory",
+	"DTLS_CMN Copy Nonce Failure"
+};
+
+/*
+ * nss_dtls_cmn_hdr_config_msg()
+ *	Log DTLS common header configure message.
+ */
+static void nss_dtls_cmn_hdr_config_msg(struct nss_dtls_cmn_msg *ndm)
+{
+	struct nss_dtls_cmn_ctx_config_hdr *ndchm __maybe_unused = &ndm->msg.hdr_cfg;
+	nss_trace("%px: NSS DTLS_CMN Header Configure Message:\n"
+		"DTLS_CMN flags: %x\n"
+		"DTLS_CMN destination interface number: %d\n"
+		"DTLS_CMN source interface number: %d\n"
+		"DTLS_CMN source ip: %px\n"
+		"DTLS_CMN destination ip: %px\n"
+		"DTLS_CMN source port: %d\n"
+		"DTLS_CMN destination port: %d\n"
+		"DTLS_CMN time to live: %d\n"
+		"DTLS_CMN dscp value: %x\n"
+		"DTLS_CMN dscp copy value: %x\n"
+		"DTLS_CMN DF flag: %x\n",
+		ndchm, ndchm->flags,
+		ndchm->dest_ifnum, ndchm->src_ifnum,
+		&ndchm->sip, &ndchm->dip,
+		ndchm->sport, ndchm->dport,
+		ndchm->hop_limit_ttl, ndchm->dscp,
+		ndchm->dscp_copy, ndchm->df);
+};
+
+/*
+ * nss_dtls_cmn_dtls_config_msg()
+ *	Log DTLS common dtls configure message.
+ */
+static void nss_dtls_cmn_dtls_config_msg(struct nss_dtls_cmn_msg *ndm)
+{
+	struct nss_dtls_cmn_ctx_config_dtls *ndcdm __maybe_unused = &ndm->msg.dtls_cfg;
+	nss_trace("%px: NSS DTLS_CMN DTLS Configure Message:\n"
+		"DTLS_CMN version: %d\n"
+		"DTLS_CMN crypto Index: %d\n"
+		"DTLS_CMN window size: %d\n"
+		"DTLS_CMN initial epoch: %d\n"
+		"DTLS_CMN IV length for encapsulation: %d\n"
+		"DTLS_CMN authentication hash length for encapsulation: %d\n"
+		"DTLS_CMN cipher block length: %d\n"
+		"DTLS_CMN reserved: %x\n",
+		ndcdm, ndcdm->ver,
+		ndcdm->crypto_idx, ndcdm->window_size,
+		ndcdm->epoch, ndcdm->iv_len,
+		ndcdm->hash_len, ndcdm->blk_len,
+		ndcdm->res1);
+};
+
+/*
+ * nss_dtls_cmn_log_verbose()
+ *	Log message contents.
+ */
+static void nss_dtls_cmn_log_verbose(struct nss_dtls_cmn_msg *ndm)
+{
+	switch (ndm->cm.type) {
+	case NSS_DTLS_CMN_MSG_TYPE_CONFIGURE_HDR:
+		nss_dtls_cmn_hdr_config_msg(ndm);
+		break;
+
+	case NSS_DTLS_CMN_MSG_TYPE_CONFIGURE_DTLS:
+		nss_dtls_cmn_dtls_config_msg(ndm);
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", ndm);
+		break;
+	}
+}
+
+/*
+ * nss_dtls_cmn_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_dtls_cmn_log_tx_msg(struct nss_dtls_cmn_msg *ndm)
+{
+	if (ndm->cm.type >= NSS_DTLS_CMN_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", ndm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ndm, ndm->cm.type, nss_dtls_cmn_log_message_types_str[ndm->cm.type]);
+	nss_dtls_cmn_log_verbose(ndm);
+}
+
+/*
+ * nss_dtls_cmn_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_dtls_cmn_log_rx_msg(struct nss_dtls_cmn_msg *ndm)
+{
+	if (ndm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ndm);
+		return;
+	}
+
+	if (ndm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ndm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ndm, ndm->cm.type,
+			nss_dtls_cmn_log_message_types_str[ndm->cm.type],
+			ndm->cm.response, nss_cmn_response_str[ndm->cm.response]);
+		goto verbose;
+	}
+
+	if (ndm->cm.error >= NSS_DTLS_CMN_ERROR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			ndm, ndm->cm.type, nss_dtls_cmn_log_message_types_str[ndm->cm.type],
+			ndm->cm.response, nss_cmn_response_str[ndm->cm.response],
+			ndm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		ndm, ndm->cm.type, nss_dtls_cmn_log_message_types_str[ndm->cm.type],
+		ndm->cm.response, nss_cmn_response_str[ndm->cm.response],
+		ndm->cm.error, nss_dtls_cmn_log_error_response_types_str[ndm->cm.error]);
+
+verbose:
+	nss_dtls_cmn_log_verbose(ndm);
+}
diff --git a/qca-nss-drv/nss_dtls_cmn_log.h b/qca-nss-drv/nss_dtls_cmn_log.h
new file mode 100644
index 0000000..3a5f755
--- /dev/null
+++ b/qca-nss-drv/nss_dtls_cmn_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_DTLS_CMN_LOG_H
+#define __NSS_DTLS_CMN_LOG_H
+
+/*
+ * nss_dtls_cmn_log.h
+ *	NSS DTLS Commn Log Header File.
+ */
+
+/*
+ * nss_dtls_cmn_log_tx_msg
+ *	Logs a DTLS common message that is sent to the NSS firmware.
+ */
+void nss_dtls_cmn_log_tx_msg(struct nss_dtls_cmn_msg *ndm);
+
+/*
+ * nss_dtls_cmn_log_rx_msg
+ *	Logs a DTLS common message that is received from the NSS firmware.
+ */
+void nss_dtls_cmn_log_rx_msg(struct nss_dtls_cmn_msg *ndm);
+
+#endif /* __NSS_DTLS_CMN_LOG_H */
diff --git a/qca-nss-drv/nss_dtls_cmn_stats.c b/qca-nss-drv/nss_dtls_cmn_stats.c
new file mode 100644
index 0000000..2908b28
--- /dev/null
+++ b/qca-nss-drv/nss_dtls_cmn_stats.c
@@ -0,0 +1,215 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_dtls_cmn.h"
+#include "nss_dtls_cmn_stats.h"
+#include "nss_dtls_cmn_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_dtls_cmn_stats_notifier);
+
+/*
+ * Spinlock to protect dtls common statistics update/read
+ */
+DEFINE_SPINLOCK(nss_dtls_cmn_stats_lock);
+
+unsigned long *nss_dtls_cmn_ifmap_get(void);
+
+/*
+ * nss_dtls_cmn_ctx_stats
+ *	dtls common ctx statistics
+ */
+uint64_t nss_dtls_cmn_ctx_stats[NSS_MAX_NET_INTERFACES][NSS_DTLS_CMN_CTX_STATS_MAX];
+
+/*
+ * nss_dtls_cmn_stats_iface_type()
+ *	Return a string for each interface type.
+ */
+static const char *nss_dtls_cmn_stats_iface_type(enum nss_dynamic_interface_type type)
+{
+	switch (type) {
+	case NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_INNER:
+		return "dtls_cmn_inner";
+
+	case NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_OUTER:
+		return "dtls_cmn_outer";
+
+	default:
+		return "invalid_interface";
+
+	}
+}
+
+/*
+ * nss_dtls_cmn_stats_read()
+ *	Read dtls common node statistics.
+ */
+static ssize_t nss_dtls_cmn_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	/*
+	 * Max output lines = #stats +
+	 * few blank lines for banner printing + Number of Extra outputlines
+	 * for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_DTLS_CMN_CTX_STATS_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	struct nss_ctx_instance *nss_ctx = nss_dtls_cmn_get_context();
+	enum nss_dynamic_interface_type type;
+	unsigned long *ifmap;
+	uint64_t *stats_shadow;
+	ssize_t bytes_read = 0;
+	size_t size_wr = 0;
+	uint32_t if_num;
+	int32_t i;
+	int count;
+	char *lbuf;
+
+	ifmap = nss_dtls_cmn_ifmap_get();
+	count = bitmap_weight(ifmap, NSS_MAX_NET_INTERFACES);
+	if (count) {
+		size_al = size_al * count;
+	}
+
+	lbuf = vzalloc(size_al);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return -ENOMEM;
+	}
+
+	stats_shadow = vzalloc(NSS_DTLS_CMN_CTX_STATS_MAX * 8);
+	if (unlikely(!stats_shadow)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		vfree(lbuf);
+		return -ENOMEM;
+	}
+
+	/*
+	 * Common node stats for each DTLS dynamic interface.
+	 */
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "dtls_cmn stats", NSS_STATS_SINGLE_CORE);
+	for_each_set_bit(if_num, ifmap, NSS_MAX_NET_INTERFACES) {
+
+		type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+		if ((type != NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_INNER) &&
+			(type != NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_OUTER)) {
+			continue;
+		}
+
+		spin_lock_bh(&nss_dtls_cmn_stats_lock);
+		for (i = 0; i < NSS_DTLS_CMN_CTX_STATS_MAX; i++) {
+			stats_shadow[i] = nss_dtls_cmn_ctx_stats[if_num][i];
+		}
+		spin_unlock_bh(&nss_dtls_cmn_stats_lock);
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n%s if_num:%03u\n",
+					nss_dtls_cmn_stats_iface_type(type), if_num);
+		size_wr += nss_stats_print("dtls_cmn", NULL, NSS_STATS_SINGLE_INSTANCE, nss_dtls_cmn_ctx_stats_str,
+						stats_shadow, NSS_DTLS_CMN_CTX_STATS_MAX, lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	vfree(lbuf);
+	vfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_dtls_cmn_stats_ops.
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(dtls_cmn);
+
+/*
+ * nss_dtls_cmn_stats_dentry_create()
+ *	Create dtls common statistics debug entry.
+ */
+void nss_dtls_cmn_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("dtls_cmn", &nss_dtls_cmn_stats_ops);
+}
+
+/*
+ * nss_dtls_cmn_stats_sync()
+ *	Update dtls common node statistics.
+ */
+void nss_dtls_cmn_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm)
+{
+	struct nss_dtls_cmn_msg *ndcm = (struct nss_dtls_cmn_msg *)ncm;
+	struct nss_dtls_cmn_ctx_stats *ndccs = &ndcm->msg.stats;
+	uint64_t *ctx_stats;
+	uint32_t *msg_stats;
+	uint16_t i = 0;
+
+	spin_lock_bh(&nss_dtls_cmn_stats_lock);
+
+	msg_stats = (uint32_t *)ndccs;
+	ctx_stats = nss_dtls_cmn_ctx_stats[ncm->interface];
+
+	for (i = 0; i < NSS_DTLS_CMN_CTX_STATS_MAX; i++, ctx_stats++, msg_stats++) {
+		*ctx_stats += *msg_stats;
+	}
+
+	spin_unlock_bh(&nss_dtls_cmn_stats_lock);
+}
+
+/*
+ * nss_dtls_cmn_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_dtls_cmn_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_dtls_cmn_stats_notification *dtls_cmn_stats;
+
+	dtls_cmn_stats = kmalloc(sizeof(struct nss_dtls_cmn_stats_notification), GFP_ATOMIC);
+	if (!dtls_cmn_stats) {
+		nss_warning("Unable to allocate memory for stats notification\n");
+		return;
+	}
+
+	spin_lock_bh(&nss_dtls_cmn_stats_lock);
+	dtls_cmn_stats->core_id = nss_ctx->id;
+	dtls_cmn_stats->if_num = if_num;
+	memcpy(dtls_cmn_stats->stats_ctx, nss_dtls_cmn_ctx_stats[if_num], sizeof(dtls_cmn_stats->stats_ctx));
+	spin_unlock_bh(&nss_dtls_cmn_stats_lock);
+
+	atomic_notifier_call_chain(&nss_dtls_cmn_stats_notifier, NSS_STATS_EVENT_NOTIFY, dtls_cmn_stats);
+	kfree(dtls_cmn_stats);
+}
+
+/*
+ * nss_dtls_cmn_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_dtls_cmn_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_dtls_cmn_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_dtls_cmn_stats_unregister_notifier);
+
+/*
+ * nss_dtls_cmn_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_dtls_cmn_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_dtls_cmn_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_dtls_cmn_stats_register_notifier);
diff --git a/qca-nss-drv/nss_dtls_cmn_stats.h b/qca-nss-drv/nss_dtls_cmn_stats.h
new file mode 100644
index 0000000..80e6edf
--- /dev/null
+++ b/qca-nss-drv/nss_dtls_cmn_stats.h
@@ -0,0 +1,26 @@
+/*
+ ****************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ****************************************************************************
+ */
+
+#ifndef __NSS_DTLS_CMN_STATS_H
+#define __NSS_DTLS_CMN_STATS_H
+
+#include <nss_cmn.h>
+
+extern void nss_dtls_cmn_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_dtls_cmn_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm);
+extern void nss_dtls_cmn_stats_dentry_create(void);
+
+#endif /* __NSS_DTLS_CMN_STATS_H */
diff --git a/qca-nss-drv/nss_dtls_cmn_strings.c b/qca-nss-drv/nss_dtls_cmn_strings.c
new file mode 100644
index 0000000..8fc9197
--- /dev/null
+++ b/qca-nss-drv/nss_dtls_cmn_strings.c
@@ -0,0 +1,128 @@
+/*
+ ****************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ****************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_dtls_cmn_strings.h"
+
+/*
+ * nss_dtls_cmn_ctx_stats_str
+ *	 dtls common ctx statistics strings.
+ */
+struct nss_stats_info nss_dtls_cmn_ctx_stats_str[NSS_DTLS_CMN_CTX_STATS_MAX] = {
+	{"rx_pkts",			NSS_STATS_TYPE_COMMON},
+	{"rx_byts",			NSS_STATS_TYPE_COMMON},
+	{"tx_pkts",			NSS_STATS_TYPE_COMMON},
+	{"tx_byts",			NSS_STATS_TYPE_COMMON},
+	{"rx_queue[0]_drops",		NSS_STATS_TYPE_DROP},
+	{"rx_queue[1]_drops",		NSS_STATS_TYPE_DROP},
+	{"rx_queue[2]_drops",		NSS_STATS_TYPE_DROP},
+	{"rx_queue[3]_drops",		NSS_STATS_TYPE_DROP},
+	{"rx_single_rec",		NSS_STATS_TYPE_SPECIAL},
+	{"rx_multi_rec",		NSS_STATS_TYPE_SPECIAL},
+	{"fail_crypto_resource",	NSS_STATS_TYPE_DROP},
+	{"fail_crypto_enqueue",		NSS_STATS_TYPE_DROP},
+	{"fail_headroom",		NSS_STATS_TYPE_DROP},
+	{"fail_tailroom",		NSS_STATS_TYPE_DROP},
+	{"fail_ver",			NSS_STATS_TYPE_DROP},
+	{"fail_epoch",			NSS_STATS_TYPE_DROP},
+	{"fail_dtls_record",		NSS_STATS_TYPE_DROP},
+	{"fail_capwap",			NSS_STATS_TYPE_DROP},
+	{"fail_replay",			NSS_STATS_TYPE_DROP},
+	{"fail_replay_dup",		NSS_STATS_TYPE_DROP},
+	{"fail_replay_win",		NSS_STATS_TYPE_DROP},
+	{"fail_queue",			NSS_STATS_TYPE_DROP},
+	{"fail_queue_nexthop",		NSS_STATS_TYPE_DROP},
+	{"fail_pbuf_alloc",		NSS_STATS_TYPE_DROP},
+	{"fail_pbuf_linear",		NSS_STATS_TYPE_DROP},
+	{"fail_pbuf_stats",		NSS_STATS_TYPE_DROP},
+	{"fail_pbuf_align",		NSS_STATS_TYPE_DROP},
+	{"fail_ctx_active",		NSS_STATS_TYPE_DROP},
+	{"fail_hwctx_active",		NSS_STATS_TYPE_DROP},
+	{"fail_cipher",			NSS_STATS_TYPE_EXCEPTION},
+	{"fail_auth",			NSS_STATS_TYPE_EXCEPTION},
+	{"fail_seq_ovf",		NSS_STATS_TYPE_DROP},
+	{"fail_blk_len",		NSS_STATS_TYPE_DROP},
+	{"fail_hash_len",		NSS_STATS_TYPE_DROP},
+	{"len_error",			NSS_STATS_TYPE_DROP},
+	{"token_error",			NSS_STATS_TYPE_DROP},
+	{"bypass_error",		NSS_STATS_TYPE_DROP},
+	{"config_error",		NSS_STATS_TYPE_DROP},
+	{"algo_error",			NSS_STATS_TYPE_DROP},
+	{"hash_ovf_error",		NSS_STATS_TYPE_DROP},
+	{"ttl_error",			NSS_STATS_TYPE_DROP},
+	{"csum_error",			NSS_STATS_TYPE_DROP},
+	{"timeout_error",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[0]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[1]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[2]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[3]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[4]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[5]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[6]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[7]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[8]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[9]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[10]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[11]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[12]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[13]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[14]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[15]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[16]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[17]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[18]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[19]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[20]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[21]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[22]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[23]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[24]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[25]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[26]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[27]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[28]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[29]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[30]",		NSS_STATS_TYPE_DROP},
+	{"fail_cle_[31]",		NSS_STATS_TYPE_DROP},
+	{"seq_low",			NSS_STATS_TYPE_SPECIAL},
+	{"seq_high",			NSS_STATS_TYPE_SPECIAL},
+	{"epoch",			NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_dtls_cmn_ctx_stats_str_strings_read()
+ *	Read dtls common ctx statistics names
+ */
+static ssize_t nss_dtls_cmn_ctx_stats_str_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_dtls_cmn_ctx_stats_str, NSS_DTLS_CMN_CTX_STATS_MAX);
+}
+
+/*
+ * nss_dtls_cmn_ctx_stats_str_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(dtls_cmn_ctx_stats_str);
+
+/*
+ * nss_dtls_cmn_strings_dentry_create()
+ *	Create dtls common statistics strings debug entry.
+ */
+void nss_dtls_cmn_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("dtls_cmn_ctx_stats_str", &nss_dtls_cmn_ctx_stats_str_strings_ops);
+}
diff --git a/qca-nss-drv/nss_dtls_cmn_strings.h b/qca-nss-drv/nss_dtls_cmn_strings.h
new file mode 100644
index 0000000..0c0bc44
--- /dev/null
+++ b/qca-nss-drv/nss_dtls_cmn_strings.h
@@ -0,0 +1,25 @@
+/*
+ ****************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ****************************************************************************
+ */
+
+#ifndef __NSS_DTLS_CMN_STRINGS_H
+#define __NSS_DTLS_CMN_STRINGS_H
+
+#include "nss_dtls_cmn_stats.h"
+
+extern struct nss_stats_info nss_dtls_cmn_ctx_stats_str[NSS_DTLS_CMN_CTX_STATS_MAX];
+extern void nss_dtls_cmn_strings_dentry_create(void);
+
+#endif /* __NSS_DTLS_CMN_STRINGS_H */
diff --git a/qca-nss-drv/nss_dtls_log.c b/qca-nss-drv/nss_dtls_log.c
new file mode 100644
index 0000000..5e1e33e
--- /dev/null
+++ b/qca-nss-drv/nss_dtls_log.c
@@ -0,0 +1,185 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_dtls_log.c
+ *	NSS DTLS logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_dtls_log_message_types_str
+ *	DTLS message strings
+ */
+static int8_t *nss_dtls_log_message_types_str[NSS_DTLS_MSG_MAX] __maybe_unused = {
+	"DTLS Session Configure",
+	"DTLS Session Destroy",
+	"DTLS Session Stats",
+	"DTLS Encap Cipher Update",
+	"DTLS Encap Cipher Switch",
+	"DTLS Decap Cipher Update",
+	"DTLS Decap Cipher Switch"
+};
+
+/*
+ * nss_dtls_log_error_response_types_str
+ *	Strings for error types for DTLS messages
+ */
+static int8_t *nss_dtls_log_error_response_types_str[NSS_DTLS_ERR_MAX] __maybe_unused = {
+	"DTLS Unknown Message",
+	"DTLS Invalid APP Interface",
+	"DTLS Invalid Parameter",
+	"DTLS Invalid Version",
+	"DTLS No Memory"
+};
+
+/*
+ * nss_dtls_session_config_msg()
+ *	Log DTLS session configure message.
+ */
+static void nss_dtls_session_config_msg(struct nss_dtls_msg *ndm)
+{
+	struct nss_dtls_session_configure *ndscm __maybe_unused = &ndm->msg.cfg;
+	nss_trace("%px: NSS DTLS Session Configure Message:\n"
+		"DTLS Version: %d\n"
+		"DTLS Flags: %x\n"
+		"DTLS crypto index encap: %d\n"
+		"DTLS crypto index decap: %d\n"
+		"DTLS IV length for encapsulation: %d\n"
+		"DTLS IV length for decapsulation: %d\n"
+		"DTLS authentication hash length for encapsulation: %d\n"
+		"DTLS authentication hash length for decapsulation: %d\n"
+		"DTLS cipher algorithm for encapsulation: %x\n"
+		"DTLS authentication algorithm for encapsulation: %x\n"
+		"DTLS cipher algorithm for decapsulation: %x\n"
+		"DTLS authentication algorithm for decapsulation: %x\n"
+		"DTLS NSS interface: %x\n"
+		"DTLS source port: %d\n"
+		"DTLS destination port: %d\n"
+		"DTLS source ip: %px\n"
+		"DTLS destination ip: %px\n"
+		"DTLS window size: %d\n"
+		"DTLS epoch: %d\n"
+		"DTLS outer IP TTL: %d\n"
+		"DTLS reserved1 padding: %x\n"
+		"DTLS reserved2 padding: %x\n",
+		ndscm, ndscm->ver,
+		ndscm->flags, ndscm->crypto_idx_encap,
+		ndscm->crypto_idx_decap, ndscm->iv_len_encap,
+		ndscm->iv_len_decap, ndscm->hash_len_encap,
+		ndscm->hash_len_decap, ndscm->cipher_algo_encap,
+		ndscm->auth_algo_encap, ndscm->cipher_algo_decap,
+		ndscm->auth_algo_decap, ndscm->nss_app_if,
+		ndscm->sport, ndscm->dport,
+		&ndscm->sip, &ndscm->dip,
+		ndscm->window_size, ndscm->epoch,
+		ndscm->oip_ttl, ndscm->reserved1,
+		ndscm->reserved2);
+}
+
+/*
+ * nss_dtls_session_cipher_upddate_msg()
+ *	Log DTLS Session Cipher Update message.
+ */
+static void nss_dtls_session_cipher_update_msg(struct nss_dtls_msg *ndm)
+{
+	struct nss_dtls_session_cipher_update *ndscum __maybe_unused = &ndm->msg.cipher_update;
+	nss_trace("%px: NSS DTLS Session Cipher Update message\n"
+		"DTLS crypto index: %d\n"
+		"DTLS hash length: %d\n"
+		"DTLS crypto IV length for encapsulation: %d\n"
+		"DTLS encapsulation cipher: %x\n"
+		"DTLS encapsulation authentication algorigthm: %x\n"
+		"DTLS epoch: %d\n"
+		"DTLS reserved: %x\n",
+		ndscum, ndscum->crypto_idx,
+		ndscum->hash_len, ndscum->iv_len,
+		ndscum->cipher_algo, ndscum->auth_algo,
+		ndscum->epoch, ndscum->reserved);
+}
+
+/*
+ * nss_dtls_log_verbose()
+ *	Log message contents.
+ */
+static void nss_dtls_log_verbose(struct nss_dtls_msg *ndm)
+{
+	switch (ndm->cm.type) {
+	case NSS_DTLS_MSG_REKEY_DECAP_CIPHER_UPDATE:
+	case NSS_DTLS_MSG_REKEY_ENCAP_CIPHER_UPDATE:
+		nss_dtls_session_cipher_update_msg(ndm);
+		break;
+
+	case NSS_DTLS_MSG_SESSION_CONFIGURE:
+		nss_dtls_session_config_msg(ndm);
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", ndm);
+		break;
+	}
+}
+
+/*
+ * nss_dtls_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_dtls_log_tx_msg(struct nss_dtls_msg *ndm)
+{
+	if (ndm->cm.type >= NSS_DTLS_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", ndm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ndm, ndm->cm.type, nss_dtls_log_message_types_str[ndm->cm.type]);
+	nss_dtls_log_verbose(ndm);
+}
+
+/*
+ * nss_dtls_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_dtls_log_rx_msg(struct nss_dtls_msg *ndm)
+{
+	if (ndm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ndm);
+		return;
+	}
+
+	if (ndm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ndm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ndm, ndm->cm.type,
+			nss_dtls_log_message_types_str[ndm->cm.type],
+			ndm->cm.response, nss_cmn_response_str[ndm->cm.response]);
+		goto verbose;
+	}
+
+	if (ndm->cm.error >= NSS_DTLS_ERR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			ndm, ndm->cm.type, nss_dtls_log_message_types_str[ndm->cm.type],
+			ndm->cm.response, nss_cmn_response_str[ndm->cm.response],
+			ndm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		ndm, ndm->cm.type, nss_dtls_log_message_types_str[ndm->cm.type],
+		ndm->cm.response, nss_cmn_response_str[ndm->cm.response],
+		ndm->cm.error, nss_dtls_log_error_response_types_str[ndm->cm.error]);
+
+verbose:
+	nss_dtls_log_verbose(ndm);
+}
diff --git a/qca-nss-drv/nss_dtls_log.h b/qca-nss-drv/nss_dtls_log.h
new file mode 100644
index 0000000..99fca71
--- /dev/null
+++ b/qca-nss-drv/nss_dtls_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_DTLS_LOG_H
+#define __NSS_DTLS_LOG_H
+
+/*
+ * nss_dtls_log.h
+ *	NSS DTLS Log Header File
+ */
+
+/*
+ * nss_dtls_log_tx_msg
+ *	Logs a DTLS message that is sent to the NSS firmware.
+ */
+void nss_dtls_log_tx_msg(struct nss_dtls_msg *ndm);
+
+/*
+ * nss_dtls_log_rx_msg
+ *	Logs a DTLS message that is received from the NSS firmware.
+ */
+void nss_dtls_log_rx_msg(struct nss_dtls_msg *ndm);
+
+#endif /* __NSS_DTLS_LOG_H */
diff --git a/qca-nss-drv/nss_dtls_stats.c b/qca-nss-drv/nss_dtls_stats.c
new file mode 100644
index 0000000..0aeff87
--- /dev/null
+++ b/qca-nss-drv/nss_dtls_stats.c
@@ -0,0 +1,143 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_dtls_stats.h"
+
+/*
+ * nss_dtls_stats_session_str
+ *	DTLS statistics strings for nss session stats.
+ */
+struct nss_stats_info nss_dtls_stats_session_str[NSS_DTLS_STATS_SESSION_MAX] = {
+	{"rx_pkts"			, NSS_STATS_TYPE_COMMON},
+	{"tx_pkts"			, NSS_STATS_TYPE_COMMON},
+	{"rx_drops[0]"			, NSS_STATS_TYPE_DROP},
+	{"rx_drops[1]"			, NSS_STATS_TYPE_DROP},
+	{"rx_drops[2]"			, NSS_STATS_TYPE_DROP},
+	{"rx_drops[3]"			, NSS_STATS_TYPE_DROP},
+	{"rx_auth_done"			, NSS_STATS_TYPE_SPECIAL},
+	{"tx_auth_done"			, NSS_STATS_TYPE_SPECIAL},
+	{"rx_cipher_done"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_cipher_done"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_cbuf_alloc_fail"		, NSS_STATS_TYPE_DROP},
+	{"tx_cbuf_alloc_fail"		, NSS_STATS_TYPE_DROP},
+	{"tx_cenqueue_fail"		, NSS_STATS_TYPE_DROP},
+	{"rx_cenqueue_fail"		, NSS_STATS_TYPE_DROP},
+	{"tx_drops_hroom"		, NSS_STATS_TYPE_DROP},
+	{"tx_drops_troom"		, NSS_STATS_TYPE_DROP},
+	{"tx_forward_enqueue_fail"	, NSS_STATS_TYPE_DROP},
+	{"rx_forward_enqueue_fail"	, NSS_STATS_TYPE_DROP},
+	{"rx_invalid_version"		, NSS_STATS_TYPE_DROP},
+	{"rx_invalid_epoch"		, NSS_STATS_TYPE_DROP},
+	{"rx_malformed"			, NSS_STATS_TYPE_DROP},
+	{"rx_cipher_fail"		, NSS_STATS_TYPE_EXCEPTION},
+	{"rx_auth_fail"			, NSS_STATS_TYPE_EXCEPTION},
+	{"rx_capwap_classify_fail"	, NSS_STATS_TYPE_DROP},
+	{"rx_single_rec_dgram"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_multi_rec_dgram"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_replay_fail"		, NSS_STATS_TYPE_DROP},
+	{"rx_replay_duplicate"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_replay_out_of_window"	, NSS_STATS_TYPE_SPECIAL},
+	{"outflow_queue_full"		, NSS_STATS_TYPE_DROP},
+	{"decap_queue_full"		, NSS_STATS_TYPE_DROP},
+	{"pbuf_alloc_fail"		, NSS_STATS_TYPE_DROP},
+	{"pbuf_copy_fail"		, NSS_STATS_TYPE_DROP},
+	{"epoch"			, NSS_STATS_TYPE_DROP},
+	{"tx_seq_high"			, NSS_STATS_TYPE_SPECIAL},
+	{"tx_seq_low"			, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_dtls_stats_read()
+ *	Read DTLS session statistics.
+ */
+static ssize_t nss_dtls_stats_read(struct file *fp, char __user *ubuf,
+				   size_t sz, loff_t *ppos)
+{
+	uint32_t max_output_lines = 2 + (NSS_MAX_DTLS_SESSIONS
+					* (NSS_DTLS_STATS_SESSION_MAX + 2)) + 2;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	struct net_device *dev;
+	int id;
+	struct nss_dtls_stats_session *dtls_session_stats = NULL;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	dtls_session_stats = kzalloc((sizeof(struct nss_dtls_stats_session)
+				     * NSS_MAX_DTLS_SESSIONS), GFP_KERNEL);
+	if (unlikely(dtls_session_stats == NULL)) {
+		nss_warning("Could not allocate memory for populating DTLS stats");
+		kfree(lbuf);
+		return 0;
+	}
+
+	/*
+	 * Get all stats.
+	 */
+	nss_dtls_session_stats_get(dtls_session_stats);
+
+	/*
+	 * Session stats.
+	 */
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "dtls", NSS_STATS_SINGLE_CORE);
+
+	for (id = 0; id < NSS_MAX_DTLS_SESSIONS; id++) {
+		if (!dtls_session_stats[id].valid)
+			break;
+
+		dev = dev_get_by_index(&init_net, dtls_session_stats[id].if_index);
+		if (likely(dev)) {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+					     "%d. nss interface id=%d, netdevice=%s\n",
+					     id, dtls_session_stats[id].if_num,
+					     dev->name);
+			dev_put(dev);
+		} else {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+					     "%d. nss interface id=%d\n", id,
+					     dtls_session_stats[id].if_num);
+		}
+
+		size_wr += nss_stats_print("dtls_cmn", NULL, id, nss_dtls_stats_session_str, dtls_session_stats[id].stats, NSS_DTLS_STATS_SESSION_MAX, lbuf, size_wr, size_al);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	kfree(dtls_session_stats);
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_dtls_stats_ops.
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(dtls)
+
+/*
+ * nss_dtls_stats_dentry_create()
+ *	Create DTLS statistics debug entry.
+ */
+void nss_dtls_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("dtls", &nss_dtls_stats_ops);
+}
diff --git a/qca-nss-drv/nss_dtls_stats.h b/qca-nss-drv/nss_dtls_stats.h
new file mode 100644
index 0000000..bf6a148
--- /dev/null
+++ b/qca-nss-drv/nss_dtls_stats.h
@@ -0,0 +1,115 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_DTLS_STATS_H
+#define __NSS_DTLS_STATS_H
+
+/*
+ * DTLS session debug statistic counters
+ */
+enum nss_dtls_stats_session_types {
+	NSS_DTLS_STATS_SESSION_RX_PKTS,
+			/* Rx packets */
+	NSS_DTLS_STATS_SESSION_TX_PKTS,
+			/* Tx packets */
+	NSS_DTLS_STATS_SESSION_RX_QUEUE_0_DROPPED,
+	NSS_DTLS_STATS_SESSION_RX_QUEUE_1_DROPPED,
+	NSS_DTLS_STATS_SESSION_RX_QUEUE_2_DROPPED,
+	NSS_DTLS_STATS_SESSION_RX_QUEUE_3_DROPPED,
+	NSS_DTLS_STATS_SESSION_RX_AUTH_DONE,
+			/* Rx successful authentication */
+	NSS_DTLS_STATS_SESSION_TX_AUTH_DONE,
+			/* Tx authentication done */
+	NSS_DTLS_STATS_SESSION_RX_CIPHER_DONE,
+			/* Rx cipher done */
+	NSS_DTLS_STATS_SESSION_TX_CIPHER_DONE,
+			/* Tx cipher done */
+	NSS_DTLS_STATS_SESSION_RX_CBUF_ALLOC_FAIL,
+			/* Rx crypto buffer alloc fail */
+	NSS_DTLS_STATS_SESSION_TX_CBUF_ALLOC_FAIL,
+			/* Tx crypto buffer alloc fail */
+	NSS_DTLS_STATS_SESSION_TX_CENQUEUE_FAIL,
+			/* Tx enqueue to crypto fail */
+	NSS_DTLS_STATS_SESSION_RX_CENQUEUE_FAIL,
+			/* Rx enqueue to crypto fail */
+	NSS_DTLS_STATS_SESSION_TX_DROPPED_HROOM,
+			/* Tx drop due to insufficient headroom */
+	NSS_DTLS_STATS_SESSION_TX_DROPPED_TROOM,
+			/* Tx drop due to insufficient tailroom */
+	NSS_DTLS_STATS_SESSION_TX_FORWARD_ENQUEUE_FAIL,
+			/* Enqueue failed to Tx node after encap */
+	NSS_DTLS_STATS_SESSION_RX_FORWARD_ENQUEUE_FAIL,
+			/* Enqueue failed to Rx node after decap */
+	NSS_DTLS_STATS_SESSION_RX_INVALID_VERSION,
+			/* Rx invalid DTLS version */
+	NSS_DTLS_STATS_SESSION_RX_INVALID_EPOCH,
+			/* Rx invalid DTLS epoch */
+	NSS_DTLS_STATS_SESSION_RX_MALFORMED,
+			/* Rx malformed DTLS record */
+	NSS_DTLS_STATS_SESSION_RX_CIPHER_FAIL,
+			/* Rx cipher fail */
+	NSS_DTLS_STATS_SESSION_RX_AUTH_FAIL,
+			/* Rx authentication fail */
+	NSS_DTLS_STATS_SESSION_RX_CAPWAP_CLASSIFY_FAIL,
+			/* Rx CAPWAP classification fail */
+	NSS_DTLS_STATS_SESSION_RX_SINGLE_REC_DGRAM,
+			/* Rx single record datagrams processed */
+	NSS_DTLS_STATS_SESSION_RX_MULTI_REC_DGRAM,
+			/* Rx multi record datagrams processed */
+	NSS_DTLS_STATS_SESSION_RX_REPLAY_FAIL,
+			/* Rx anti-replay failures */
+	NSS_DTLS_STATS_SESSION_RX_REPLAY_DUPLICATE,
+			/* Rx anti-replay fail due to duplicate record */
+	NSS_DTLS_STATS_SESSION_RX_REPLAY_OUT_OF_WINDOW,
+			/* Rx anti-replay fail due to out of window record */
+	NSS_DTLS_STATS_SESSION_OUTFLOW_QUEUE_FULL,
+			/* Tx drop due to encap queue full */
+	NSS_DTLS_STATS_SESSION_DECAP_QUEUE_FULL,
+			/* Rx drop due to decap queue full */
+	NSS_DTLS_STATS_SESSION_PBUF_ALLOC_FAIL,
+			/* Drops due to buffer allocation failure */
+	NSS_DTLS_STATS_SESSION_PBUF_COPY_FAIL,
+			/* Drops due to buffer copy failure */
+	NSS_DTLS_STATS_SESSION_EPOCH,
+			/* Current Epoch */
+	NSS_DTLS_STATS_SESSION_TX_SEQ_HIGH,
+			/* Upper 16-bits of current sequence number */
+	NSS_DTLS_STATS_SESSION_TX_SEQ_LOW,
+			/* Lower 32-bits of current sequence number */
+	NSS_DTLS_STATS_SESSION_MAX,
+};
+
+/*
+ * DTLS session statistics
+ */
+struct nss_dtls_stats_session {
+	uint64_t stats[NSS_DTLS_STATS_SESSION_MAX];
+	int32_t if_index;
+	uint32_t if_num; /* nss interface number */
+	bool valid;
+};
+
+/*
+ * Stats APIs provided by nss_dtls.c
+ */
+extern void nss_dtls_session_stats_get(struct nss_dtls_stats_session *s);
+
+/*
+ * DTLS statistics APIs
+ */
+extern void nss_dtls_stats_dentry_create(void);
+
+#endif /* __NSS_DTLS_STATS_H */
diff --git a/qca-nss-drv/nss_dynamic_interface.c b/qca-nss-drv/nss_dynamic_interface.c
new file mode 100644
index 0000000..a7286bf
--- /dev/null
+++ b/qca-nss-drv/nss_dynamic_interface.c
@@ -0,0 +1,420 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_dynamic_interface_log.h"
+#include "nss_dynamic_interface_stats.h"
+
+#define NSS_DYNAMIC_INTERFACE_COMP_TIMEOUT 60000	/* 60 Sec */
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_dynamic_interface_stats_notifier);
+
+void nss_dynamic_interface_stats_notify(uint32_t if_num, uint32_t core_id);
+
+/*
+ * Message data structure to store the message result
+ */
+struct nss_dynamic_interface_msg_data {
+	struct completion complete;	/* completion structure */
+	int if_num;			/* Interface number */
+	enum nss_cmn_response response;	/* Message response */
+};
+
+static nss_dynamic_interface_assigned nss_dynamic_interface_assigned_types[NSS_CORE_MAX][NSS_MAX_DYNAMIC_INTERFACES]; /* Array of assigned interface types */
+
+/*
+ * nss_dynamic_interface_handler()
+ * 	Handle NSS -> HLOS messages for dynamic interfaces
+ */
+static void nss_dynamic_interface_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	nss_dynamic_interface_msg_callback_t cb;
+	struct nss_dynamic_interface_msg *ndim = (struct nss_dynamic_interface_msg *)ncm;
+	int32_t if_num;
+
+	BUG_ON(ncm->interface != NSS_DYNAMIC_INTERFACE);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_DYNAMIC_INTERFACE_MAX) {
+		nss_warning("%px: received invalid message %d for dynamic interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_dynamic_interface_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Trace messages.
+	 */
+	nss_dynamic_interface_log_rx_msg(ndim);
+
+	/*
+	 * Handling dynamic interface messages coming from NSS fw.
+	 */
+	switch (ndim->cm.type) {
+	case NSS_DYNAMIC_INTERFACE_ALLOC_NODE:
+		if (ncm->response == NSS_CMN_RESPONSE_ACK) {
+			nss_info("%px alloc_node response ack if_num %d\n", nss_ctx, ndim->msg.alloc_node.if_num);
+			if_num = ndim->msg.alloc_node.if_num;
+			if (if_num > 0) {
+				nss_dynamic_interface_assigned_types[nss_ctx->id][if_num - NSS_DYNAMIC_IF_START] = ndim->msg.alloc_node.type;
+			} else {
+				nss_warning("%px: if_num < 0\n", nss_ctx);
+			}
+		}
+
+		break;
+
+	case NSS_DYNAMIC_INTERFACE_DEALLOC_NODE:
+		if (ncm->response == NSS_CMN_RESPONSE_ACK) {
+			nss_info("%px dealloc_node response ack if_num %d\n", nss_ctx, ndim->msg.dealloc_node.if_num);
+			if_num = ndim->msg.dealloc_node.if_num;
+			nss_dynamic_interface_assigned_types[nss_ctx->id][if_num - NSS_DYNAMIC_IF_START] = NSS_DYNAMIC_INTERFACE_TYPE_NONE;
+			/*
+			 * Send dynamic interface dealloc notifications to the registered modules.
+			 */
+			nss_dynamic_interface_stats_notify(ndim->msg.dealloc_node.if_num, nss_ctx->id);
+		}
+
+		break;
+
+	default:
+		nss_warning("%px: Received response %d for type %d, interface %d",
+				nss_ctx, ncm->response, ncm->type, ncm->interface);
+		return;
+	}
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		nss_warning("%px: nss_dynamic_interface_handler cb is NULL\n", nss_ctx);
+		return;
+	}
+
+	/*
+	 * Callback
+	 */
+	cb = (nss_dynamic_interface_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, ncm);
+}
+
+/*
+ * nss_dynamic_interface_callback
+ *	Callback to handle the message response from NSS FW.
+ */
+static void nss_dynamic_interface_callback(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_dynamic_interface_msg_data *di_data = (struct nss_dynamic_interface_msg_data *)app_data;
+	struct nss_dynamic_interface_msg *ndim = (struct nss_dynamic_interface_msg *)ncm;
+
+	di_data->response = ncm->response;
+	di_data->if_num = ndim->msg.alloc_node.if_num;
+
+	/*
+	 * Unblock the sleeping function.
+	 */
+	complete(&di_data->complete);
+}
+
+/*
+ * nss_dynamic_interface_tx()
+ * 	Transmit a dynamic interface message to NSSFW, asynchronously.
+ */
+nss_tx_status_t nss_dynamic_interface_tx(struct nss_ctx_instance *nss_ctx, struct nss_dynamic_interface_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Sanity check the message
+	 */
+	if (ncm->interface != NSS_DYNAMIC_INTERFACE) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_DYNAMIC_INTERFACE_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_dynamic_interface_log_tx_msg(msg);
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ * nss_dynamic_interface_tx_sync()
+ *	Send the message to NSS and wait till we get an ACK or NACK for this msg.
+ */
+static nss_tx_status_t nss_dynamic_interface_tx_sync(struct nss_ctx_instance *nss_ctx, struct nss_dynamic_interface_msg_data *di_data,
+						     struct nss_dynamic_interface_msg *ndim)
+{
+	nss_tx_status_t status;
+	int ret;
+
+	status = nss_dynamic_interface_tx(nss_ctx, ndim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: not able to transmit msg successfully\n", nss_ctx);
+		return status;
+	}
+
+	/*
+	 * Blocking call, wait till we get ACK for this msg.
+	 */
+	ret = wait_for_completion_timeout(&di_data->complete, msecs_to_jiffies(NSS_DYNAMIC_INTERFACE_COMP_TIMEOUT));
+	if (ret == 0) {
+		nss_warning("%px: Waiting for ack timed out\n", nss_ctx);
+		return NSS_TX_FAILURE;
+	}
+
+	return status;
+}
+
+/*
+ * nss_dynamic_interface_alloc_node()
+ *	Allocates node of perticular type on NSS and returns interface_num for this node or -1 in case of failure.
+ *
+ * Note: This function should not be called from soft_irq or interrupt context because it blocks till ACK/NACK is
+ * received for the message sent to NSS.
+ */
+int nss_dynamic_interface_alloc_node(enum nss_dynamic_interface_type type)
+{
+	struct nss_ctx_instance *nss_ctx = NULL;
+	struct nss_dynamic_interface_msg ndim;
+	struct nss_dynamic_interface_alloc_node_msg *ndia;
+	struct nss_dynamic_interface_msg_data di_data;
+	uint32_t core_id;
+	nss_tx_status_t status;
+
+	if (type >= NSS_DYNAMIC_INTERFACE_TYPE_MAX) {
+		nss_warning("Dynamic if msg drooped as type is wrong %d\n", type);
+		return -1;
+	}
+
+	core_id = nss_top_main.dynamic_interface_table[type];
+	nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[core_id];
+	di_data.if_num = -1;
+	di_data.response = false;
+	init_completion(&di_data.complete);
+
+	nss_dynamic_interface_msg_init(&ndim, NSS_DYNAMIC_INTERFACE, NSS_DYNAMIC_INTERFACE_ALLOC_NODE,
+				sizeof(struct nss_dynamic_interface_alloc_node_msg), nss_dynamic_interface_callback, (void *)&di_data);
+
+	ndia = &ndim.msg.alloc_node;
+	ndia->type = type;
+
+	/*
+	 * Initialize if_num to -1. The allocated if_num is returned by the firmware
+	 * in the response message.
+	 */
+	ndia->if_num = -1;
+
+	/*
+	 * Calling synchronous transmit function.
+	 */
+	status = nss_dynamic_interface_tx_sync(nss_ctx, &di_data, &ndim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px not able to transmit alloc node msg\n", nss_ctx);
+		return -1;
+	}
+
+	/*
+	 * Check response and return -1 if its a NACK else proceed.
+	 */
+	if (di_data.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("%px Received NACK from NSS - Response:%d\n", nss_ctx, di_data.response);
+		return -1;
+	}
+
+	return di_data.if_num;
+}
+
+/*
+ * nss_dynamic_interface_dealloc_node()
+ *	Deallocate node of particular type and if_num in NSS.
+ *
+ * Note: This will just mark the state of node as not active, actual memory will be freed when reference count of that node becomes 0.
+ * This function should not be called from soft_irq or interrupt context because it blocks till ACK/NACK is received for the message
+ * sent to NSS.
+ */
+nss_tx_status_t nss_dynamic_interface_dealloc_node(int if_num, enum nss_dynamic_interface_type type)
+{
+	struct nss_ctx_instance *nss_ctx = NULL;
+	struct nss_dynamic_interface_msg ndim;
+	struct nss_dynamic_interface_dealloc_node_msg *ndid;
+	struct nss_dynamic_interface_msg_data di_data;
+	uint32_t core_id;
+	nss_tx_status_t status;
+
+	if (type >= NSS_DYNAMIC_INTERFACE_TYPE_MAX) {
+		nss_warning("Dynamic if msg dropped as type is wrong type %d if_num %d\n", type, if_num);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	core_id = nss_top_main.dynamic_interface_table[type];
+	nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[core_id];
+	di_data.response = false;
+	init_completion(&di_data.complete);
+
+	if (nss_is_dynamic_interface(if_num) == false) {
+		nss_warning("%px: nss_dynamic_interface if_num is not in range %d\n", nss_ctx, if_num);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	nss_dynamic_interface_msg_init(&ndim, NSS_DYNAMIC_INTERFACE, NSS_DYNAMIC_INTERFACE_DEALLOC_NODE,
+				sizeof(struct nss_dynamic_interface_dealloc_node_msg), nss_dynamic_interface_callback, (void *)&di_data);
+
+	ndid = &ndim.msg.dealloc_node;
+	ndid->type = type;
+	ndid->if_num = if_num;
+
+	/*
+	 * Calling synchronous transmit function.
+	 */
+	status = nss_dynamic_interface_tx_sync(nss_ctx, &di_data, &ndim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px not able to transmit alloc node msg\n", nss_ctx);
+		return status;
+	}
+
+	if (di_data.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("%px Received NACK from NSS\n", nss_ctx);
+		return -1;
+	}
+
+	return status;
+}
+
+/*
+ * nss_dynamic_interface_register_handler()
+ */
+void nss_dynamic_interface_register_handler(struct nss_ctx_instance *nss_ctx)
+{
+	nss_core_register_handler(nss_ctx, NSS_DYNAMIC_INTERFACE, nss_dynamic_interface_handler, NULL);
+	nss_dynamic_interface_stats_dentry_create();
+}
+
+/*
+ * nss_is_dynamic_interface()
+ *	Judge it is a valid dynamic interface
+ */
+bool nss_is_dynamic_interface(int if_num)
+{
+	return (if_num >= NSS_DYNAMIC_IF_START && if_num < NSS_SPECIAL_IF_START);
+}
+
+/*
+ * nss_dynamic_interface_get_nss_ctx_by_type()
+ * 	Gets the NSS context using NSS dynamic interface type.
+ */
+struct nss_ctx_instance *nss_dynamic_interface_get_nss_ctx_by_type(enum nss_dynamic_interface_type type)
+{
+	struct nss_ctx_instance *nss_ctx = NULL;
+	uint32_t core_id;
+
+	if (type >= NSS_DYNAMIC_INTERFACE_TYPE_MAX) {
+		nss_warning("Invalid param: Type is wrong %d\n", type);
+		return NULL;
+	}
+
+	core_id = nss_top_main.dynamic_interface_table[type];
+	nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[core_id];
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	return nss_ctx;
+}
+
+/*
+ * nss_dynamic_interface_get_type()
+ *	Gets the type of dynamic interface
+ */
+enum nss_dynamic_interface_type nss_dynamic_interface_get_type(struct nss_ctx_instance *nss_ctx, int if_num)
+{
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (nss_is_dynamic_interface(if_num) == false) {
+		return NSS_DYNAMIC_INTERFACE_TYPE_NONE;
+	}
+
+	return nss_dynamic_interface_assigned_types[nss_ctx->id][if_num - NSS_DYNAMIC_IF_START];
+}
+
+/*
+ * nss_dynamic_interface_msg_init()
+ *	Initialize dynamic interface message.
+ */
+void nss_dynamic_interface_msg_init(struct nss_dynamic_interface_msg *ndm, uint16_t if_num, uint32_t type, uint32_t len,
+						void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ndm->cm, if_num, type, len, cb, app_data);
+}
+
+/*
+ * nss_dynamic_interface_stats_notify()
+ *	Sends notifications to all the registered modules.
+ */
+void nss_dynamic_interface_stats_notify(uint32_t if_num, uint32_t core_id)
+{
+	struct nss_dynamic_interface_notification stats;
+
+	stats.core_id = core_id;
+	stats.if_num = if_num;
+	atomic_notifier_call_chain(&nss_dynamic_interface_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&stats);
+}
+EXPORT_SYMBOL(nss_dynamic_interface_stats_notify);
+
+/*
+ * nss_dynamic_interface_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_dynamic_interface_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_dynamic_interface_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_dynamic_interface_stats_register_notifier);
+
+/*
+ * nss_dynamic_interface_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_dynamic_interface_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_dynamic_interface_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_dynamic_interface_stats_unregister_notifier);
+
+EXPORT_SYMBOL(nss_dynamic_interface_alloc_node);
+EXPORT_SYMBOL(nss_dynamic_interface_dealloc_node);
+EXPORT_SYMBOL(nss_is_dynamic_interface);
+EXPORT_SYMBOL(nss_dynamic_interface_get_type);
+EXPORT_SYMBOL(nss_dynamic_interface_get_nss_ctx_by_type);
diff --git a/qca-nss-drv/nss_dynamic_interface_log.c b/qca-nss-drv/nss_dynamic_interface_log.c
new file mode 100644
index 0000000..0c49aeb
--- /dev/null
+++ b/qca-nss-drv/nss_dynamic_interface_log.c
@@ -0,0 +1,145 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_dynamic_interface_log.c
+ *	NSS Dynamic Interface logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_dynamic_interface_log_message_types_str
+ *	Dynamic Interface message strings
+ */
+static int8_t *nss_dynamic_interface_log_message_types_str[NSS_DYNAMIC_INTERFACE_MAX] __maybe_unused = {
+	"Dynamic Interface Alloc Node",
+	"Dynamic Interface Dealloc Node"
+};
+
+/*
+ * nss_dynamic_interface_log_error_response_types_str
+ *	Strings for error types for dynamic interface messages
+ */
+static int8_t *nss_dynamic_interface_log_error_response_types_str[NSS_DYNAMIC_INTERFACE_ERR_MAX] __maybe_unused = {
+	"Dynamic Interface Error Unknown Interface",
+	"Dynamic Interface Error Unavailable Interface",
+	"Dynamic Interface Error Invalid Interface Type",
+	"Dynamic Interface Error Invalid Interface Number",
+	"Dynamic Interface Error Alloc Function Unavailable",
+	"Dynamic Interface Error Dealloc Funciton Unavailable",
+	"Dynamic Interface Error Allocation Error",
+	"Dynamic Interface Error Interface Number Mismatch"
+};
+
+/*
+ * nss_dynamic_interface_alloc_node_msg()
+ *	Log Dynamic Interface alloc node message.
+ */
+static void nss_dynamic_interface_alloc_node_log_msg(struct nss_dynamic_interface_msg *ndm)
+{
+	struct nss_dynamic_interface_alloc_node_msg *ndanm __maybe_unused = &ndm->msg.alloc_node;
+	nss_trace("%px: NSS Dynamic Interface Alloc Node Message:\n"
+		"Dynamic Interface Type: %d\n"
+		"Dynamic Interface Number: %d\n",
+		ndanm, ndanm->type,
+		ndanm->if_num);
+}
+
+/*
+ * nss_dynamic_interface_dealloc_node_msg()
+ *	Log Dynamic Interface dealloc node message.
+ */
+static void nss_dynamic_interface_dealloc_node_log_msg(struct nss_dynamic_interface_msg *ndm)
+{
+	struct nss_dynamic_interface_dealloc_node_msg *nddnm __maybe_unused = &ndm->msg.dealloc_node;
+	nss_trace("%px: NSS Dynamic Interface Alloc Node Message:\n"
+		"Dynamic Interface Type: %d\n"
+		"Dynamic Interface Number: %d\n",
+		nddnm, nddnm->type,
+		nddnm->if_num);
+}
+
+/*
+ * nss_dynamic_interface_log_verbose()
+ *	Log message contents.
+ */
+static void nss_dynamic_interface_log_verbose(struct nss_dynamic_interface_msg *ndm)
+{
+	switch (ndm->cm.type) {
+	case NSS_DYNAMIC_INTERFACE_ALLOC_NODE:
+		nss_dynamic_interface_alloc_node_log_msg(ndm);
+		break;
+
+	case NSS_DYNAMIC_INTERFACE_DEALLOC_NODE:
+		nss_dynamic_interface_dealloc_node_log_msg(ndm);
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", ndm);
+		break;
+	}
+}
+
+/*
+ * nss_dynamic_interface_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_dynamic_interface_log_tx_msg(struct nss_dynamic_interface_msg *ndm)
+{
+	if (ndm->cm.type >= NSS_DYNAMIC_INTERFACE_MAX) {
+		nss_warning("%px: Invalid message type\n", ndm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ndm, ndm->cm.type, nss_dynamic_interface_log_message_types_str[ndm->cm.type]);
+	nss_dynamic_interface_log_verbose(ndm);
+}
+
+/*
+ * nss_dynamic_interface_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_dynamic_interface_log_rx_msg(struct nss_dynamic_interface_msg *ndm)
+{
+	if (ndm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ndm);
+		return;
+	}
+
+	if (ndm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ndm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ndm, ndm->cm.type,
+			nss_dynamic_interface_log_message_types_str[ndm->cm.type],
+			ndm->cm.response, nss_cmn_response_str[ndm->cm.response]);
+		goto verbose;
+	}
+
+	if (ndm->cm.error >= NSS_DYNAMIC_INTERFACE_ERR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			ndm, ndm->cm.type, nss_dynamic_interface_log_message_types_str[ndm->cm.type],
+			ndm->cm.response, nss_cmn_response_str[ndm->cm.response],
+			ndm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n, error[%d]:%s\n",
+		ndm, ndm->cm.type, nss_dynamic_interface_log_message_types_str[ndm->cm.type],
+		ndm->cm.response, nss_cmn_response_str[ndm->cm.response],
+		ndm->cm.error, nss_dynamic_interface_log_error_response_types_str[ndm->cm.error]);
+
+verbose:
+	nss_dynamic_interface_log_verbose(ndm);
+}
diff --git a/qca-nss-drv/nss_dynamic_interface_log.h b/qca-nss-drv/nss_dynamic_interface_log.h
new file mode 100644
index 0000000..266b909
--- /dev/null
+++ b/qca-nss-drv/nss_dynamic_interface_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_DYNAMIC_INTERFACE_LOG_H
+#define __NSS_DYNAMIC_INTERFACE_LOG_H
+
+/*
+ * nss_dynamic_interface.h
+ *	NSS Dynamic Interface private header file.
+ */
+
+/*
+ * nss_dynamic_interface_log_tx_msg
+ *	Logs a dynamic interface message that is sent to the NSS firmware.
+ */
+void nss_dynamic_interface_log_tx_msg(struct nss_dynamic_interface_msg *ndm);
+
+/*
+ * nss_dynamic_interface_log_rx_msg
+ *	Logs a dynamic interface message that is received from the NSS firmware.
+ */
+void nss_dynamic_interface_log_rx_msg(struct nss_dynamic_interface_msg *ndm);
+
+#endif /* __NSS_DYNAMIC_INTERFACE_LOG_H */
diff --git a/qca-nss-drv/nss_dynamic_interface_stats.c b/qca-nss-drv/nss_dynamic_interface_stats.c
new file mode 100644
index 0000000..1f190b6
--- /dev/null
+++ b/qca-nss-drv/nss_dynamic_interface_stats.c
@@ -0,0 +1,160 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_dynamic_interface.h"
+
+/*
+ * nss_dynamic_interface_type_names
+ *	Name strings for dynamic interface types
+ */
+const char *nss_dynamic_interface_type_names[NSS_DYNAMIC_INTERFACE_TYPE_MAX] = {
+	"NSS_DYNAMIC_INTERFACE_TYPE_NONE",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR",
+	"NSS_DYNAMIC_INTERFACE_TYPE_RESERVED_5",
+	"NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_OUTER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_RESERVED",
+	"NSS_DYNAMIC_INTERFACE_TYPE_VAP",
+	"NSS_DYNAMIC_INTERFACE_TYPE_RESERVED_0",
+	"NSS_DYNAMIC_INTERFACE_TYPE_PPPOE",
+	"NSS_DYNAMIC_INTERFACE_TYPE_VIRTIF_DEPRECATED",
+	"NSS_DYNAMIC_INTERFACE_TYPE_L2TPV2",
+	"NSS_DYNAMIC_INTERFACE_TYPE_RESERVED_4",
+	"NSS_DYNAMIC_INTERFACE_TYPE_PORTID",
+	"NSS_DYNAMIC_INTERFACE_TYPE_DTLS",
+	"NSS_DYNAMIC_INTERFACE_TYPE_QVPN_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_QVPN_OUTER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_BRIDGE",
+	"NSS_DYNAMIC_INTERFACE_TYPE_VLAN",
+	"NSS_DYNAMIC_INTERFACE_TYPE_RESERVED_3",
+	"NSS_DYNAMIC_INTERFACE_TYPE_WIFILI_INTERNAL",
+	"NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_OUTER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_OUTER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_OUTER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_HOST_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_OFFL_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_SJACK_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_OUTER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INLINE_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INLINE_OUTER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_N2H",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_H2N",
+	"NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_OUTER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_US",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_DS",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INNER_EXCEPTION",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_EXCEPTION_US",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_EXCEPTION_DS",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_PPTP_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_PPTP_OUTER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_PPTP_HOST_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_MDATA_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_OUTER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_MDATA_OUTER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_REDIRECT",
+	"NSS_DYNAMIC_INTERFACE_TYPE_PVXLAN_HOST_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_PVXLAN_OUTER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_IGS",
+	"NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US",
+	"NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_DS",
+	"NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_OUTER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_MATCH",
+	"NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_N2H",
+	"NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_H2N",
+	"NSS_DYNAMIC_INTERFACE_TYPE_WIFILI_EXTERNAL0",
+	"NSS_DYNAMIC_INTERFACE_TYPE_WIFILI_EXTERNAL1",
+	"NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_HOST_INNER",
+	"NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_OUTER",
+};
+
+/*
+ * nss_dynamic_interface_type_names_stats_read()
+ *	Read and display dynamic interface types names
+ */
+static ssize_t nss_dynamic_interface_type_names_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int i;
+	char *lbuf = NULL;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint32_t max_output_lines = 2 /* header & footer for stats */
+				+ NSS_DYNAMIC_INTERFACE_TYPE_MAX /* maximum number of dynamic interface types */
+				+ 2;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+
+	lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	/*
+	 * name strings
+	 */
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n dynamic interface type names start:\n\n");
+
+	for (i = 0; i < NSS_DYNAMIC_INTERFACE_TYPE_MAX; i++) {
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+				"\t%u : %s\n", i, nss_dynamic_interface_type_names[i]);
+	}
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n dynamic interface type names end\n");
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_dynamic_interface_type_names_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(dynamic_interface_type_names)
+
+/*
+ * nss_dynamic_interface_stats_dentry_create()
+ *	Create dynamic-interface statistics debug entry.
+ */
+void nss_dynamic_interface_stats_dentry_create(void)
+{
+	struct dentry *di_dentry = NULL;
+	struct dentry *di_type_name_d = NULL;
+
+	di_dentry = debugfs_create_dir("dynamic_if", nss_top_main.stats_dentry);
+	if (unlikely(di_dentry == NULL)) {
+		nss_warning("Failed to create qca-nss-drv/stats/dynamic_if directory");
+		return;
+	}
+
+	di_type_name_d = debugfs_create_file("type_names", 0400, di_dentry,
+					&nss_top_main, &nss_dynamic_interface_type_names_stats_ops);
+	if (unlikely(di_type_name_d == NULL)) {
+		nss_warning("Failed to create qca-nss-drv/stats/dynamic_if/type_names file");
+		return;
+	}
+}
diff --git a/qca-nss-drv/nss_dynamic_interface_stats.h b/qca-nss-drv/nss_dynamic_interface_stats.h
new file mode 100644
index 0000000..ef16162
--- /dev/null
+++ b/qca-nss-drv/nss_dynamic_interface_stats.h
@@ -0,0 +1,33 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_DYNAMIC_INTERFACE_STATS_H
+#define __NSS_DYNAMIC_INTERFACE_STATS_H
+
+/*
+ * nss_dynamic_interface.h
+ *	NSS Dynamic Interface private header file.
+ */
+
+/*
+ * nss_dynamic_interface_stats_dentry_create
+ *	Create dynamic interface debugfs entry.
+ */
+void nss_dynamic_interface_stats_dentry_create(void);
+
+#endif /* __NSS_DYNAMIC_INTERFACE_STATS_H */
diff --git a/qca-nss-drv/nss_edma.c b/qca-nss-drv/nss_edma.c
new file mode 100644
index 0000000..f037726
--- /dev/null
+++ b/qca-nss-drv/nss_edma.c
@@ -0,0 +1,139 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_edma.c
+ *	NSS EDMA APIs
+ */
+#include "nss_edma_stats.h"
+#include "nss_edma_strings.h"
+
+/*
+ **********************************
+ Rx APIs
+ **********************************
+ */
+
+/*
+ * nss_edma_interface_handler()
+ *	Handle NSS -> HLOS messages for EDMA node
+ */
+static void nss_edma_interface_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_edma_msg *nem = (struct nss_edma_msg *)ncm;
+	nss_edma_msg_callback_t cb;
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (nem->cm.type >= NSS_METADATA_TYPE_EDMA_MAX) {
+		nss_warning("%px: received invalid message %d for edma interface", nss_ctx, nem->cm.type);
+		return;
+	}
+
+	/*
+	 * Handle different types of messages
+	 */
+	switch (nem->cm.type) {
+	case NSS_METADATA_TYPE_EDMA_PORT_STATS_SYNC:
+		/*
+		 * Update driver statistics and send statistics notifications to the registered modules.
+		 */
+		nss_edma_metadata_port_stats_sync(nss_ctx, &nem->msg.port_stats);
+		nss_edma_stats_notify(nss_ctx);
+
+		break;
+	case NSS_METADATA_TYPE_EDMA_RING_STATS_SYNC:
+		nss_edma_metadata_ring_stats_sync(nss_ctx, &nem->msg.ring_stats);
+		break;
+	case NSS_METADATA_TYPE_EDMA_ERR_STATS_SYNC:
+		nss_edma_metadata_err_stats_sync(nss_ctx, &nem->msg.err_stats);
+		break;
+	default:
+		if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+			/*
+			 * Check response
+			 */
+			nss_info("%px: Received response %d for type %d, interface %d",
+						nss_ctx, ncm->response, ncm->type, ncm->interface);
+		}
+	}
+	/*
+	 * Update the callback and app_data for NOTIFY messages, edma sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (nem->cm.response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->edma_callback;
+		ncm->app_data = (nss_ptr_t)nss_ctx->nss_top->edma_ctx;
+	}
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * Callback
+	 */
+	cb = (nss_edma_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, nem);
+}
+
+/*
+ * nss_edma_notify_register()
+ *	Register to received EDMA events.
+ */
+struct nss_ctx_instance *nss_edma_notify_register(nss_edma_msg_callback_t cb, void *app_data)
+{
+	nss_top_main.edma_callback = cb;
+	nss_top_main.edma_ctx = app_data;
+	return &nss_top_main.nss[nss_top_main.edma_handler_id];
+}
+EXPORT_SYMBOL(nss_edma_notify_register);
+
+/*
+ * nss_edma_notify_unregister()
+ *	Unregister to received EDMA events.
+ */
+void nss_edma_notify_unregister(void)
+{
+	nss_top_main.edma_callback = NULL;
+}
+EXPORT_SYMBOL(nss_edma_notify_unregister);
+
+/*
+ * nss_get_edma_context()
+ */
+struct nss_ctx_instance *nss_edma_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.edma_handler_id];
+}
+EXPORT_SYMBOL(nss_edma_get_context);
+
+/*
+ * nss_edma_register_handler()
+ */
+void nss_edma_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_edma_get_context();
+
+	nss_core_register_handler(nss_ctx, NSS_EDMA_INTERFACE, nss_edma_interface_handler, NULL);
+
+	nss_edma_stats_dentry_create();
+	nss_edma_strings_dentry_create();
+}
diff --git a/qca-nss-drv/nss_edma_stats.c b/qca-nss-drv/nss_edma_stats.c
new file mode 100644
index 0000000..abb338e
--- /dev/null
+++ b/qca-nss-drv/nss_edma_stats.c
@@ -0,0 +1,822 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_edma_stats.c
+ *	NSS EDMA statistics APIs
+ */
+
+#include "nss_edma_stats.h"
+#include "nss_edma_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_edma_stats_notifier);
+
+struct nss_edma_stats edma_stats;
+
+/*
+ **********************************
+ EDMA statistics APIs
+ **********************************
+ */
+
+/*
+ * nss_edma_port_stats_read()
+ *	Read EDMA port statistics
+ */
+static ssize_t nss_edma_port_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * Max output lines = #stats * NSS_MAX_CORES  +
+	 * few blank lines for banner printing + Number of Extra outputlines for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_STATS_NODE_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+	struct nss_stats_data *data = fp->private_data;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_STATS_NODE_MAX * sizeof(uint64_t), GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "edma", NSS_STATS_SINGLE_CORE);
+
+	/*
+	 * Common node stats
+	 */
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "edma port %d stats:\n\n", data->edma_id);
+
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; (i < NSS_STATS_NODE_MAX); i++) {
+		stats_shadow[i] = edma_stats.port[data->edma_id].port_stats[i];
+	}
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+	size_wr += nss_stats_print("edma_port", NULL, data->edma_id
+					, nss_edma_strings_stats_node
+					, stats_shadow
+					, NSS_STATS_NODE_MAX
+					, lbuf, size_wr, size_al);
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_edma_port_type_stats_read()
+ *	Read EDMA port type
+ */
+static ssize_t nss_edma_port_type_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	/*
+	 * max output lines = #stats + start tag line + end tag line + three blank lines
+	 */
+	uint32_t max_output_lines = (1 + 2) + 3;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t port_type;
+	struct nss_stats_data *data = fp->private_data;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	size_wr = scnprintf(lbuf, size_al, "edma port type start:\n\n");
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "edma port %d type:\n\n", data->edma_id);
+
+	/*
+	 * Port type
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+	port_type = edma_stats.port[data->edma_id].port_type;
+	spin_unlock_bh(&nss_top_main.stats_lock);
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+					"port_type = %s\n", nss_edma_strings_stats_port_type[port_type].stats_name);
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nedma stats end\n");
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+
+	return bytes_read;
+}
+
+/*
+ * nss_edma_port_ring_map_stats_read()
+ *	Read EDMA port ring map
+ */
+static ssize_t nss_edma_port_ring_map_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * max output lines = #stats + start tag line + end tag line + three blank lines
+	 */
+	uint32_t max_output_lines = (4 + 2) + 3;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+	struct nss_stats_data *data = fp->private_data;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_EDMA_PORT_RING_MAP_MAX * sizeof(uint64_t), GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr = scnprintf(lbuf, size_al, "edma port ring map start:\n\n");
+
+	/*
+	 * Port ring map
+	 */
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "edma port %d ring map:\n\n", data->edma_id);
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; i < NSS_EDMA_PORT_RING_MAP_MAX; i++) {
+		stats_shadow[i] = edma_stats.port[data->edma_id].port_ring_map[i];
+	}
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+
+	size_wr += nss_stats_print("edma_port_ring", NULL, data->edma_id
+					, nss_edma_strings_stats_port_ring_map
+					, stats_shadow
+					, NSS_EDMA_PORT_RING_MAP_MAX
+					, lbuf, size_wr, size_al);
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_edma_txring_stats_read()
+ *	Read EDMA Tx ring stats
+ */
+static ssize_t nss_edma_txring_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * max output lines = #stats + start tag line + end tag line + three blank lines
+	 */
+	uint32_t max_output_lines = (NSS_EDMA_STATS_TX_MAX + 2) + 3;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+	struct nss_stats_data *data = fp->private_data;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_EDMA_STATS_TX_MAX * sizeof(uint64_t), GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr = scnprintf(lbuf, size_al, "edma Tx ring stats start:\n\n");
+
+	/*
+	 * Tx ring stats
+	 */
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "Tx ring %d stats:\n\n", data->edma_id);
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; i < NSS_EDMA_STATS_TX_MAX; i++) {
+		stats_shadow[i] = edma_stats.tx_stats[data->edma_id][i];
+	}
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+
+	size_wr += nss_stats_print("edma_tx_ring", NULL, data->edma_id
+					, nss_edma_strings_stats_tx
+					, stats_shadow
+					, NSS_EDMA_STATS_TX_MAX
+					, lbuf, size_wr, size_al);
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_edma_rxring_stats_read()
+ *	Read EDMA rxring stats
+ */
+static ssize_t nss_edma_rxring_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * max output lines = #stats + start tag line + end tag line + three blank lines
+	 */
+	uint32_t max_output_lines = (NSS_EDMA_STATS_RX_MAX + 2) + 3;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+	struct nss_stats_data *data = fp->private_data;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_EDMA_STATS_RX_MAX * sizeof(uint64_t), GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	/*
+	 * RX ring stats
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; i < NSS_EDMA_STATS_RX_MAX; i++) {
+		stats_shadow[i] = edma_stats.rx_stats[data->edma_id][i];
+	}
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+	size_wr += nss_stats_print("edma_rx_ring", NULL, data->edma_id
+					, nss_edma_strings_stats_rx
+					, stats_shadow
+					, NSS_EDMA_STATS_RX_MAX
+					, lbuf, size_wr, size_al);
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_edma_txcmplring_stats_read()
+ *	Read EDMA txcmplring stats
+ */
+static ssize_t nss_edma_txcmplring_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * max output lines = #stats + start tag line + end tag line + three blank lines
+	 */
+	uint32_t max_output_lines = (NSS_EDMA_STATS_TXCMPL_MAX + 2) + 3;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+	struct nss_stats_data *data = fp->private_data;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_EDMA_STATS_TXCMPL_MAX * sizeof(uint64_t), GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr = scnprintf(lbuf, size_al, "edma Tx cmpl ring stats start:\n\n");
+
+	/*
+	 * Tx cmpl ring stats
+	 */
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "Tx cmpl ring %d stats:\n\n", data->edma_id);
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; i < NSS_EDMA_STATS_TXCMPL_MAX; i++) {
+		stats_shadow[i] = edma_stats.txcmpl_stats[data->edma_id][i];
+	}
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+	size_wr += nss_stats_print("edma_tx_cmpl_ring", NULL, data->edma_id
+					, nss_edma_strings_stats_txcmpl
+					, stats_shadow
+					, NSS_EDMA_STATS_TXCMPL_MAX
+					, lbuf, size_wr, size_al);
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nedma Tx cmpl ring stats end\n\n");
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_edma_rxfillring_stats_read()
+ *	Read EDMA rxfillring stats
+ */
+static ssize_t nss_edma_rxfillring_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * max output lines = #stats + start tag line + end tag line + three blank lines
+	 */
+	uint32_t max_output_lines = (NSS_EDMA_STATS_RXFILL_MAX + 2) + 3;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+	struct nss_stats_data *data = fp->private_data;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_EDMA_STATS_RXFILL_MAX * sizeof(uint64_t), GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr = scnprintf(lbuf, size_al, "edma Rx fill ring stats start:\n\n");
+
+	/*
+	 * Rx fill ring stats
+	 */
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "Rx fill ring %d stats:\n\n", data->edma_id);
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; i < NSS_EDMA_STATS_RXFILL_MAX; i++) {
+		stats_shadow[i] = edma_stats.rxfill_stats[data->edma_id][i];
+	}
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+	size_wr += nss_stats_print("edma_rx_fill_ring", NULL
+					, NSS_STATS_SINGLE_INSTANCE
+					, nss_edma_strings_stats_rxfill
+					, stats_shadow
+					, NSS_EDMA_STATS_RXFILL_MAX
+					, lbuf, size_wr, size_al);
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_edma_err_stats_read()
+ *      Read EDMA err stats
+ */
+static ssize_t nss_edma_err_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * max output lines = #stats + start tag line + end tag line + three blank lines
+	 */
+	uint32_t max_output_lines = (NSS_EDMA_ERR_STATS_MAX + 2) + 3;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_EDMA_ERR_STATS_MAX * sizeof(uint64_t), GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr = scnprintf(lbuf, size_al, "edma error stats start:\n\n");
+
+	/*
+	 * Common node stats
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+
+	for (i = 0; (i < NSS_EDMA_ERR_STATS_MAX); i++)
+		stats_shadow[i] = edma_stats.misc_err[i];
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+	size_wr += nss_stats_print("edma_err", NULL, NSS_STATS_SINGLE_INSTANCE
+					, nss_edma_strings_stats_err_map
+					, stats_shadow
+					, NSS_EDMA_ERR_STATS_MAX
+					, lbuf, size_wr, size_al);
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * edma_port_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(edma_port);
+
+/*
+ * edma_port_type_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(edma_port_type);
+
+/*
+ * edma_port_ring_map_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(edma_port_ring_map);
+
+/*
+ * edma_txring_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(edma_txring);
+
+/*
+ * edma_rxring_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(edma_rxring);
+
+/*
+ * edma_txcmplring_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(edma_txcmplring);
+
+/*
+ * edma_rxfillring_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(edma_rxfillring);
+
+/*
+ * edma_err_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(edma_err);
+
+/*
+ * nss_edma_stats_dentry_create()
+ *	Create edma statistics debug entry.
+ */
+void nss_edma_stats_dentry_create(void)
+{
+	int i;
+	struct dentry *edma_d = NULL;
+	struct dentry *edma_port_dir_d = NULL;
+	struct dentry *edma_port_d = NULL;
+	struct dentry *edma_port_type_d = NULL;
+	struct dentry *edma_port_stats_d = NULL;
+	struct dentry *edma_port_ring_map_d = NULL;
+	struct dentry *edma_rings_dir_d = NULL;
+	struct dentry *edma_tx_dir_d = NULL;
+	struct dentry *edma_tx_d = NULL;
+	struct dentry *edma_rx_dir_d = NULL;
+	struct dentry *edma_rx_d = NULL;
+	struct dentry *edma_txcmpl_dir_d = NULL;
+	struct dentry *edma_txcmpl_d = NULL;
+	struct dentry *edma_rxfill_dir_d = NULL;
+	struct dentry *edma_rxfill_d = NULL;
+	struct dentry *edma_err_stats_d = NULL;
+	char file_name[10];
+
+	edma_d = debugfs_create_dir("edma", nss_top_main.stats_dentry);
+	if (unlikely(edma_d == NULL)) {
+		nss_warning("Failed to create qca-nss-drv/stats/edma directory");
+		return;
+	}
+
+	/*
+	 * edma port stats
+	 */
+	edma_port_dir_d = debugfs_create_dir("ports", edma_d);
+	if (unlikely(edma_port_dir_d == NULL)) {
+		nss_warning("Failed to create qca-nss-drv/stats/edma/ports directory");
+		return;
+	}
+
+	for (i = 0; i < NSS_EDMA_NUM_PORTS_MAX; i++) {
+		memset(file_name, 0, sizeof(file_name));
+		snprintf(file_name, sizeof(file_name), "%d", i);
+
+		edma_port_d = debugfs_create_dir(file_name, edma_port_dir_d);
+		if (unlikely(edma_port_d == NULL)) {
+			nss_warning("Failed to create qca-nss-drv/stats/edma/ports/%d directory", i);
+			return;
+		}
+
+		edma_port_stats_d = debugfs_create_file("stats", 0400, edma_port_d, (void *)(nss_ptr_t)i, &nss_edma_port_stats_ops);
+		if (unlikely(edma_port_stats_d == NULL)) {
+			nss_warning("Failed to create qca-nss-drv/stats/edma/ports/%d/stats file", i);
+			return;
+		}
+
+		edma_port_type_d = debugfs_create_file("type", 0400, edma_port_d, (void *)(nss_ptr_t)i, &nss_edma_port_type_stats_ops);
+		if (unlikely(edma_port_type_d == NULL)) {
+			nss_warning("Failed to create qca-nss-drv/stats/edma/ports/%d/type file", i);
+			return;
+		}
+
+		edma_port_ring_map_d = debugfs_create_file("ring_map", 0400, edma_port_d, (void *)(nss_ptr_t)i, &nss_edma_port_ring_map_stats_ops);
+		if (unlikely(edma_port_ring_map_d == NULL)) {
+			nss_warning("Failed to create qca-nss-drv/stats/edma/ports/%d/ring_map file", i);
+			return;
+		}
+	}
+
+	/*
+	 *  edma error stats
+	 */
+	edma_err_stats_d = NULL;
+	edma_err_stats_d = debugfs_create_file("err_stats", 0400, edma_d, &nss_top_main, &nss_edma_err_stats_ops);
+	if (unlikely(edma_port_stats_d == NULL)) {
+		nss_warning("Failed to create qca-nss-drv/stats/edma/%d/err_stats file", 0);
+		return;
+	}
+
+	/*
+	 * edma ring stats
+	 */
+	edma_rings_dir_d = debugfs_create_dir("rings", edma_d);
+	if (unlikely(edma_rings_dir_d == NULL)) {
+		nss_warning("Failed to create qca-nss-drv/stats/edma/rings directory");
+		return;
+	}
+
+	/*
+	 * edma tx ring stats
+	 */
+	edma_tx_dir_d = debugfs_create_dir("tx", edma_rings_dir_d);
+	if (unlikely(edma_tx_dir_d == NULL)) {
+		nss_warning("Failed to create qca-nss-drv/stats/edma/rings/tx directory");
+		return;
+	}
+
+	for (i = 0; i < NSS_EDMA_NUM_TX_RING_MAX; i++) {
+		memset(file_name, 0, sizeof(file_name));
+		scnprintf(file_name, sizeof(file_name), "%d", i);
+		edma_tx_d = debugfs_create_file(file_name, 0400, edma_tx_dir_d, (void *)(nss_ptr_t)i, &nss_edma_txring_stats_ops);
+		if (unlikely(edma_tx_d == NULL)) {
+			nss_warning("Failed to create qca-nss-drv/stats/edma/rings/tx/%d file", i);
+			return;
+		}
+	}
+
+	/*
+	 * edma rx ring stats
+	 */
+	edma_rx_dir_d = debugfs_create_dir("rx", edma_rings_dir_d);
+	if (unlikely(edma_rx_dir_d == NULL)) {
+		nss_warning("Failed to create qca-nss-drv/stats/edma/rings/rx directory");
+		return;
+	}
+
+	for (i = 0; i < NSS_EDMA_NUM_RX_RING_MAX; i++) {
+		memset(file_name, 0, sizeof(file_name));
+		scnprintf(file_name, sizeof(file_name), "%d", i);
+		edma_rx_d = debugfs_create_file(file_name, 0400, edma_rx_dir_d, (void *)(nss_ptr_t)i, &nss_edma_rxring_stats_ops);
+		if (unlikely(edma_rx_d == NULL)) {
+			nss_warning("Failed to create qca-nss-drv/stats/edma/rings/rx/%d file", i);
+			return;
+		}
+	}
+
+	/*
+	 * edma tx cmpl ring stats
+	 */
+	edma_txcmpl_dir_d = debugfs_create_dir("txcmpl", edma_rings_dir_d);
+	if (unlikely(edma_txcmpl_dir_d == NULL)) {
+		nss_warning("Failed to create qca-nss-drv/stats/edma/rings/txcmpl directory");
+		return;
+	}
+
+	for (i = 0; i < NSS_EDMA_NUM_TXCMPL_RING_MAX; i++) {
+		memset(file_name, 0, sizeof(file_name));
+		scnprintf(file_name, sizeof(file_name), "%d", i);
+		edma_txcmpl_d = debugfs_create_file(file_name, 0400, edma_txcmpl_dir_d, (void *)(nss_ptr_t)i, &nss_edma_txcmplring_stats_ops);
+		if (unlikely(edma_txcmpl_d == NULL)) {
+			nss_warning("Failed to create qca-nss-drv/stats/edma/rings/txcmpl/%d file", i);
+			return;
+		}
+	}
+
+	/*
+	 * edma rx fill ring stats
+	 */
+	edma_rxfill_dir_d = debugfs_create_dir("rxfill", edma_rings_dir_d);
+	if (unlikely(edma_rxfill_dir_d == NULL)) {
+		nss_warning("Failed to create qca-nss-drv/stats/edma/rings/rxfill directory");
+		return;
+	}
+
+	for (i = 0; i < NSS_EDMA_NUM_RXFILL_RING_MAX; i++) {
+		memset(file_name, 0, sizeof(file_name));
+		scnprintf(file_name, sizeof(file_name), "%d", i);
+		edma_rxfill_d = debugfs_create_file(file_name, 0400, edma_rxfill_dir_d, (void *)(nss_ptr_t)i, &nss_edma_rxfillring_stats_ops);
+		if (unlikely(edma_rxfill_d == NULL)) {
+			nss_warning("Failed to create qca-nss-drv/stats/edma/rings/rxfill/%d file", i);
+			return;
+		}
+	}
+}
+
+/*
+ * nss_edma_metadata_port_stats_sync()
+ *	Handle the syncing of EDMA port statistics.
+ */
+void nss_edma_metadata_port_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_edma_port_stats_sync *nepss)
+{
+	uint16_t i, j = 0;
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	spin_lock_bh(&nss_top->stats_lock);
+
+	/*
+	 * edma port stats
+	 * We process a subset of port stats since msg payload is not enough to hold all ports at once.
+	 */
+	for (i = nepss->start_port; i < nepss->end_port; i++) {
+		int k;
+
+		edma_stats.port[i].port_stats[NSS_STATS_NODE_RX_PKTS] += nepss->port_stats[j].node_stats.rx_packets;
+		edma_stats.port[i].port_stats[NSS_STATS_NODE_RX_BYTES] += nepss->port_stats[j].node_stats.rx_bytes;
+		edma_stats.port[i].port_stats[NSS_STATS_NODE_TX_PKTS] += nepss->port_stats[j].node_stats.tx_packets;
+		edma_stats.port[i].port_stats[NSS_STATS_NODE_TX_BYTES] += nepss->port_stats[j].node_stats.tx_bytes;
+
+		for (k = 0; k < NSS_MAX_NUM_PRI; k++) {
+			edma_stats.port[i].port_stats[NSS_STATS_NODE_RX_QUEUE_0_DROPPED + k] += nepss->port_stats[j].node_stats.rx_dropped[k];
+		}
+
+		edma_stats.port[i].port_type = nepss->port_stats[j].port_type;
+		edma_stats.port[i].port_ring_map[NSS_EDMA_PORT_RX_RING] = nepss->port_stats[j].edma_rx_ring;
+		edma_stats.port[i].port_ring_map[NSS_EDMA_PORT_TX_RING] = nepss->port_stats[j].edma_tx_ring;
+		j++;
+	}
+
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_edma_metadata_ring_stats_sync()
+ *	Handle the syncing of EDMA ring statistics.
+ */
+void nss_edma_metadata_ring_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_edma_ring_stats_sync *nerss)
+{
+	int32_t i;
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	spin_lock_bh(&nss_top->stats_lock);
+
+	/*
+	 * edma tx ring stats
+	 */
+	for (i = 0; i < NSS_EDMA_NUM_TX_RING_MAX; i++) {
+		edma_stats.tx_stats[i][NSS_EDMA_STATS_TX_ERR] += nerss->tx_ring[i].tx_err;
+		edma_stats.tx_stats[i][NSS_EDMA_STATS_TX_DROPPED] += nerss->tx_ring[i].tx_dropped;
+		edma_stats.tx_stats[i][NSS_EDMA_STATS_TX_DESC] += nerss->tx_ring[i].desc_cnt;
+	}
+
+	/*
+	 * edma rx ring stats
+	 */
+	for (i = 0; i < NSS_EDMA_NUM_RX_RING_MAX; i++) {
+		edma_stats.rx_stats[i][NSS_EDMA_STATS_RX_CSUM_ERR] += nerss->rx_ring[i].rx_csum_err;
+		edma_stats.rx_stats[i][NSS_EDMA_STATS_RX_DESC] += nerss->rx_ring[i].desc_cnt;
+		edma_stats.rx_stats[i][NSS_EDMA_STATS_RX_QOS_ERR] += nerss->rx_ring[i].qos_err;
+		edma_stats.rx_stats[i][NSS_EDMA_STATS_RX_SRC_PORT_INVALID] += nerss->rx_ring[i].rx_src_port_invalid;
+		edma_stats.rx_stats[i][NSS_EDMA_STATS_RX_SRC_IF_INVALID] += nerss->rx_ring[i].rx_src_if_invalid;
+	}
+
+	/*
+	 * edma tx cmpl ring stats
+	 */
+	for (i = 0; i < NSS_EDMA_NUM_TXCMPL_RING_MAX; i++) {
+		edma_stats.txcmpl_stats[i][NSS_EDMA_STATS_TXCMPL_DESC] += nerss->txcmpl_ring[i].desc_cnt;
+	}
+
+	/*
+	 * edma rx fill ring stats
+	 */
+	for (i = 0; i < NSS_EDMA_NUM_RXFILL_RING_MAX; i++) {
+		edma_stats.rxfill_stats[i][NSS_EDMA_STATS_RXFILL_DESC] += nerss->rxfill_ring[i].desc_cnt;
+	}
+
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_edma_metadata_err_stats_sync()
+ *	Handle the syncing of EDMA error statistics.
+ */
+void nss_edma_metadata_err_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_edma_err_stats_sync *nerss)
+{
+
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	spin_lock_bh(&nss_top->stats_lock);
+
+	edma_stats.misc_err[NSS_EDMA_AXI_RD_ERR] += nerss->msg_err_stats.axi_rd_err;
+	edma_stats.misc_err[NSS_EDMA_AXI_WR_ERR] += nerss->msg_err_stats.axi_wr_err;
+	edma_stats.misc_err[NSS_EDMA_RX_DESC_FIFO_FULL_ERR] += nerss->msg_err_stats.rx_desc_fifo_full_err;
+	edma_stats.misc_err[NSS_EDMA_RX_BUF_SIZE_ERR] += nerss->msg_err_stats.rx_buf_size_err;
+	edma_stats.misc_err[NSS_EDMA_TX_SRAM_FULL_ERR] += nerss->msg_err_stats.tx_sram_full_err;
+	edma_stats.misc_err[NSS_EDMA_TX_CMPL_BUF_FULL_ERR] += nerss->msg_err_stats.tx_cmpl_buf_full_err;
+	edma_stats.misc_err[NSS_EDMA_PKT_LEN_LA64K_ERR] += nerss->msg_err_stats.pkt_len_la64k_err;
+	edma_stats.misc_err[NSS_EDMA_PKT_LEN_LE33_ERR] += nerss->msg_err_stats.pkt_len_le33_err;
+	edma_stats.misc_err[NSS_EDMA_DATA_LEN_ERR] += nerss->msg_err_stats.data_len_err;
+	edma_stats.misc_err[NSS_EDMA_ALLOC_FAIL_CNT] += nerss->msg_err_stats.alloc_fail_cnt;
+	edma_stats.misc_err[NSS_EDMA_QOS_INVAL_DST_DROPS] += nerss->msg_err_stats.qos_inval_dst_drops;
+
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_edma_stats_notify()
+ *	Calls statistics notifier.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_edma_stats_notify(struct nss_ctx_instance *nss_ctx)
+{
+	uint32_t core_id = nss_ctx->id;
+
+	atomic_notifier_call_chain(&nss_edma_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&core_id);
+}
+
+/*
+ * nss_edma_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_edma_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_edma_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_edma_stats_register_notifier);
+
+/*
+ * nss_edma_stats_unregister_notifier()
+ *	Deregisters stats notifier.
+ */
+int nss_edma_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_edma_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_edma_stats_unregister_notifier);
+
+/*
+ * nss_edma_get_stats
+ *	Sends EDMA statistics to NSS clients.
+ */
+void nss_edma_get_stats(uint64_t  *stats, int port_id)
+{
+	memcpy(stats, edma_stats.port[port_id].port_stats, sizeof(uint64_t) * NSS_STATS_NODE_MAX);
+}
+EXPORT_SYMBOL(nss_edma_get_stats);
diff --git a/qca-nss-drv/nss_edma_stats.h b/qca-nss-drv/nss_edma_stats.h
new file mode 100644
index 0000000..305582b
--- /dev/null
+++ b/qca-nss-drv/nss_edma_stats.h
@@ -0,0 +1,36 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+/*
+ * nss_edma_stats.h
+ *	NSS EDMA statistics header file.
+ */
+
+#ifndef __NSS_EDMA_STATS_H
+#define __NSS_EDMA_STATS_H
+
+#include "nss_core.h"
+
+/*
+ * NSS EDMA statistics APIs
+ */
+extern void nss_edma_stats_notify(struct nss_ctx_instance *nss_ctx);
+extern void nss_edma_metadata_port_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_edma_port_stats_sync *nepss);
+extern void nss_edma_metadata_ring_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_edma_ring_stats_sync *nerss);
+extern void nss_edma_metadata_err_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_edma_err_stats_sync *nerss);
+extern void nss_edma_stats_dentry_create(void);
+
+#endif /* __NSS_EDMA_STATS_H */
diff --git a/qca-nss-drv/nss_edma_strings.c b/qca-nss-drv/nss_edma_strings.c
new file mode 100644
index 0000000..3d9c233
--- /dev/null
+++ b/qca-nss-drv/nss_edma_strings.c
@@ -0,0 +1,350 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include <nss_edma.h>
+#include "nss_strings.h"
+
+/*
+ * nss_edma_strings_stats_node
+ *	EDMA statistics strings.
+ */
+struct nss_stats_info nss_edma_strings_stats_node[NSS_STATS_NODE_MAX] = {
+	{"rx_pkts"		, NSS_STATS_TYPE_COMMON},
+	{"rx_byts"		, NSS_STATS_TYPE_COMMON},
+	{"tx_pkts"		, NSS_STATS_TYPE_COMMON},
+	{"tx_byts"		, NSS_STATS_TYPE_COMMON},
+	{"rx_queue[0]_drops"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue[1]_drops"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue[2]_drops"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue[3]_drops"	, NSS_STATS_TYPE_DROP}
+};
+
+/*
+ * nss_edma_common_stats_strings_read()
+ *	Read EDMA common node statistics names.
+ */
+static ssize_t nss_edma_common_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_edma_strings_stats_node, NSS_STATS_NODE_MAX);
+}
+
+/*
+ * nss_edma_common_stats_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(edma_common_stats);
+
+/*
+ * nss_edma_strings_stats_tx
+ */
+struct nss_stats_info nss_edma_strings_stats_tx[NSS_EDMA_STATS_TX_MAX] = {
+	{"tx_err"	, NSS_STATS_TYPE_ERROR},
+	{"tx_drops"	, NSS_STATS_TYPE_DROP},
+	{"desc_cnt"	, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_edma_txring_strings_read()
+ *      Read EDMA txring names.
+ */
+static ssize_t nss_edma_txring_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_edma_strings_stats_tx, NSS_EDMA_STATS_TX_MAX);
+}
+
+/*
+ * edma_txring_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(edma_txring);
+
+/*
+ * nss_edma_strings_stats_rx
+ */
+struct nss_stats_info nss_edma_strings_stats_rx[NSS_EDMA_STATS_RX_MAX] = {
+	{"rx_csum_err"		, NSS_STATS_TYPE_ERROR},
+	{"desc_cnt"		, NSS_STATS_TYPE_SPECIAL},
+	{"qos_err"		, NSS_STATS_TYPE_DROP},
+	{"rx_src_port_invalid"	, NSS_STATS_TYPE_DROP},
+	{"rx_src_interface_invalid"	, NSS_STATS_TYPE_DROP}
+};
+
+/*
+ * nss_edma_rxring_strings_read()
+ *      Read EDMA rxring names.
+ */
+static ssize_t nss_edma_rxring_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_edma_strings_stats_rx, NSS_EDMA_STATS_RX_MAX);
+}
+
+/*
+ * edma_rxring_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(edma_rxring);
+
+/*
+ * nss_edma_strings_stats_txcmpl
+ */
+struct nss_stats_info nss_edma_strings_stats_txcmpl[NSS_EDMA_STATS_TXCMPL_MAX] = {
+	{"desc_cnt"	, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_edma_txcmplring_strings_read()
+ *      Read EDMA txcmplring names.
+ */
+static ssize_t nss_edma_txcmplring_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_edma_strings_stats_txcmpl, NSS_EDMA_STATS_TXCMPL_MAX);
+}
+
+/*
+ * edma_txcmplring_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(edma_txcmplring);
+
+/*
+ * nss_edma_strings_stats_rxfill
+ */
+struct nss_stats_info nss_edma_strings_stats_rxfill[NSS_EDMA_STATS_RXFILL_MAX] = {
+	{"desc_cnt"	, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_edma_rxfillring_strings_read()
+ *      Read EDMA rxfillring names.
+ */
+static ssize_t nss_edma_rxfillring_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_edma_strings_stats_rxfill, NSS_EDMA_STATS_RXFILL_MAX);
+}
+
+/*
+ * edma_rxfillring_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(edma_rxfillring);
+
+/*
+ * nss_edma_strings_stats_port_type
+ */
+struct nss_stats_info nss_edma_strings_stats_port_type[NSS_EDMA_PORT_TYPE_MAX] = {
+	{"physical_port", NSS_STATS_TYPE_SPECIAL},
+	{"virtual_port" , NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_edma_port_type_strings_read()
+ *      Read EDMA port type names.
+ */
+static ssize_t nss_edma_port_type_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_edma_strings_stats_port_type, NSS_EDMA_PORT_TYPE_MAX);
+}
+
+/*
+ * edma_port_type_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(edma_port_type);
+
+/*
+ * nss_edma_strings_stats_port_ring_map
+ */
+struct nss_stats_info nss_edma_strings_stats_port_ring_map[NSS_EDMA_PORT_RING_MAP_MAX] = {
+	{"rx_ring"	, NSS_STATS_TYPE_SPECIAL},
+	{"tx_ring"	, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_edma_port_ring_map_strings_read()
+ *	Read EDMA port ring map names.
+ */
+static ssize_t nss_edma_port_ring_map_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_edma_strings_stats_port_ring_map, NSS_EDMA_PORT_RING_MAP_MAX);
+}
+
+/*
+ * edma_port_ring_map_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(edma_port_ring_map);
+
+/*
+ * nss_edma_strings_stats_err_map
+ */
+struct nss_stats_info nss_edma_strings_stats_err_map[NSS_EDMA_ERR_STATS_MAX] = {
+	{"axi_rd_err"		, NSS_STATS_TYPE_ERROR},
+	{"axi_wr_err"		, NSS_STATS_TYPE_ERROR},
+	{"rx_desc_fifo_full_err", NSS_STATS_TYPE_ERROR},
+	{"rx_buf_size_err"	, NSS_STATS_TYPE_ERROR},
+	{"tx_sram_full_err"	, NSS_STATS_TYPE_ERROR},
+	{"tx_cmpl_buf_full_err"	, NSS_STATS_TYPE_ERROR},
+	{"pkt_len_la64k_err"	, NSS_STATS_TYPE_ERROR},
+	{"pkt_len_le33_err"	, NSS_STATS_TYPE_ERROR},
+	{"data_len_err"		, NSS_STATS_TYPE_ERROR},
+	{"alloc_fail_cnt"	, NSS_STATS_TYPE_ERROR},
+	{"qos_inval_dst_drops"	, NSS_STATS_TYPE_DROP}
+};
+
+/*
+ * nss_edma_err_strings_read()
+ *      Read EDMA error names.
+ */
+static ssize_t nss_edma_err_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_edma_strings_stats_err_map, NSS_EDMA_ERR_STATS_MAX);
+}
+
+/*
+ * edma_err_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(edma_err);
+
+/*
+ * nss_edma_strings_dentry_create()
+ *      Create EDMA statistics strings debug entry.
+ */
+void nss_edma_strings_dentry_create(void)
+{
+	struct dentry *edma_d;
+	struct dentry *edma_port_dir_d;
+	struct dentry *edma_rings_dir_d;
+	struct dentry *edma_rx_dir_d;
+	struct dentry *edma_tx_dir_d;
+	struct dentry *edma_rxfill_dir_d;
+	struct dentry *edma_txcmpl_dir_d;
+	struct dentry *file_d;
+
+	if (!nss_top_main.strings_dentry) {
+		nss_warning("qca-nss-drv/strings is not present");
+		return;
+	}
+
+	edma_d = debugfs_create_dir("edma", nss_top_main.strings_dentry);
+	if (!edma_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/edma directory");
+		return;
+	}
+
+	/*
+	 * EDMA port stats.
+	 */
+	edma_port_dir_d = debugfs_create_dir("ports", edma_d);
+	if (!edma_port_dir_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/edma/ports directory");
+		goto fail;
+	}
+
+	file_d = debugfs_create_file("common_stats_str", 0400, edma_port_dir_d, &nss_top_main, &nss_edma_common_stats_strings_ops);
+	if (!file_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/edma/ports/common_stats_str file");
+		goto fail;
+	}
+
+	file_d = debugfs_create_file("type", 0400, edma_port_dir_d, &nss_top_main, &nss_edma_port_type_strings_ops);
+	if (!file_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/edma/ports/type file");
+		goto fail;
+	}
+
+	file_d = debugfs_create_file("ring_map", 0400, edma_port_dir_d, &nss_top_main, &nss_edma_port_ring_map_strings_ops);
+	if (!file_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/edma/ports/ring_map file");
+		goto fail;
+	}
+
+	/*
+	 *  edma error stats
+	 */
+	file_d = debugfs_create_file("err_stats", 0400, edma_d, &nss_top_main, &nss_edma_err_strings_ops);
+	if (!file_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/edma/err_stats file");
+		goto fail;
+	}
+
+	/*
+	 * edma ring stats
+	 */
+	edma_rings_dir_d = debugfs_create_dir("rings", edma_d);
+	if (!edma_rings_dir_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/edma/rings directory");
+		goto fail;
+	}
+
+	/*
+	 * edma tx ring stats
+	 */
+	edma_tx_dir_d = debugfs_create_dir("tx", edma_rings_dir_d);
+	if (!edma_tx_dir_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/edma/rings/tx directory");
+		goto fail;
+	}
+
+	file_d = debugfs_create_file("tx_str", 0400, edma_tx_dir_d, &nss_top_main, &nss_edma_txring_strings_ops);
+	if (!file_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/edma/rings/tx file");
+		goto fail;
+	}
+
+	/*
+	 * edma rx ring stats
+	 */
+	edma_rx_dir_d = debugfs_create_dir("rx", edma_rings_dir_d);
+	if (!edma_rx_dir_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/edma/rings/rx directory");
+		goto fail;
+	}
+
+	file_d = debugfs_create_file("rx_str", 0400, edma_rx_dir_d, &nss_top_main, &nss_edma_rxring_strings_ops);
+	if (!file_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/edma/rings/rx file");
+		goto fail;
+	}
+
+	/*
+	 * edma tx cmpl ring stats
+	 */
+	edma_txcmpl_dir_d = debugfs_create_dir("txcmpl", edma_rings_dir_d);
+	if (!edma_txcmpl_dir_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/edma/rings/txcmpl directory");
+		goto fail;
+	}
+
+	file_d = debugfs_create_file("txcmpl_str", 0400, edma_txcmpl_dir_d, &nss_top_main, &nss_edma_txcmplring_strings_ops);
+	if (!file_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/edma/rings/txcmpl file");
+		goto fail;
+	}
+
+	/*
+	 * edma rx fill ring stats
+	 */
+	edma_rxfill_dir_d = debugfs_create_dir("rxfill", edma_rings_dir_d);
+	if (!edma_rxfill_dir_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/edma/rings/rxfill directory");
+		goto fail;
+	}
+
+	file_d = debugfs_create_file("rxfill_str", 0400, edma_rxfill_dir_d, &nss_top_main, &nss_edma_rxfillring_strings_ops);
+	if (!file_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/edma/rings/rxfill file");
+		goto fail;
+	}
+
+	return;
+fail:
+	debugfs_remove_recursive(edma_d);
+}
diff --git a/qca-nss-drv/nss_edma_strings.h b/qca-nss-drv/nss_edma_strings.h
new file mode 100644
index 0000000..b211975
--- /dev/null
+++ b/qca-nss-drv/nss_edma_strings.h
@@ -0,0 +1,30 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_EDMA_STRINGS_H
+#define __NSS_EDMA_STRINGS_H
+
+extern struct nss_stats_info nss_edma_strings_stats_node[NSS_STATS_NODE_MAX];
+extern struct nss_stats_info nss_edma_strings_stats_tx[NSS_EDMA_STATS_TX_MAX];
+extern struct nss_stats_info nss_edma_strings_stats_rx[NSS_EDMA_STATS_RX_MAX];
+extern struct nss_stats_info nss_edma_strings_stats_txcmpl[NSS_EDMA_STATS_TXCMPL_MAX];
+extern struct nss_stats_info nss_edma_strings_stats_rxfill[NSS_EDMA_STATS_RXFILL_MAX];
+extern struct nss_stats_info nss_edma_strings_stats_port_type[NSS_EDMA_PORT_TYPE_MAX];
+extern struct nss_stats_info nss_edma_strings_stats_port_ring_map[NSS_EDMA_PORT_RING_MAP_MAX];
+extern struct nss_stats_info nss_edma_strings_stats_err_map[NSS_EDMA_ERR_STATS_MAX];
+extern void nss_edma_strings_dentry_create(void);
+
+#endif /* __NSS_EDMA_STRINGS_H */
diff --git a/qca-nss-drv/nss_eth_rx.c b/qca-nss-drv/nss_eth_rx.c
new file mode 100644
index 0000000..eba62af
--- /dev/null
+++ b/qca-nss-drv/nss_eth_rx.c
@@ -0,0 +1,77 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2017, 2019-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_eth_rx.c
+ *	NSS ETH_RX APIs
+ */
+
+#include <nss_core.h>
+#include "nss_eth_rx_stats.h"
+#include "nss_eth_rx_strings.h"
+
+/*
+ **********************************
+ Rx APIs
+ **********************************
+ */
+
+/*
+ * nss_eth_rx_interface_handler()
+ *	Handle NSS -> HLOS messages for ETH_RX node
+ */
+static void nss_eth_rx_interface_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_eth_rx_msg *nem = (struct nss_eth_rx_msg *)ncm;
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (nem->cm.type >= NSS_METADATA_TYPE_ETH_RX_MAX) {
+		nss_warning("%px: received invalid message %d for eth_rx interface", nss_ctx, nem->cm.type);
+		return;
+	}
+
+	switch (nem->cm.type) {
+	case NSS_RX_METADATA_TYPE_ETH_RX_STATS_SYNC:
+		/*
+		 * Update driver statistics and send stats notifications to the registered modules.
+		 */
+		nss_eth_rx_metadata_stats_sync(nss_ctx, &nem->msg.node_sync);
+		nss_eth_rx_stats_notify(nss_ctx);
+		break;
+
+	default:
+		if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+			/*
+			 * Check response
+			 */
+			nss_info("%px: Received response %d for type %d, interface %d",
+						nss_ctx, ncm->response, ncm->type, ncm->interface);
+		}
+	}
+}
+
+/*
+ * nss_eth_rx_register_handler()
+ */
+void nss_eth_rx_register_handler(struct nss_ctx_instance *nss_ctx)
+{
+	nss_core_register_handler(nss_ctx, NSS_ETH_RX_INTERFACE, nss_eth_rx_interface_handler, NULL);
+
+	nss_eth_rx_stats_dentry_create();
+	nss_eth_rx_strings_dentry_create();
+}
diff --git a/qca-nss-drv/nss_eth_rx_stats.c b/qca-nss-drv/nss_eth_rx_stats.c
new file mode 100644
index 0000000..cfc7057
--- /dev/null
+++ b/qca-nss-drv/nss_eth_rx_stats.c
@@ -0,0 +1,187 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017, 2019-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_eth_rx_stats.h"
+#include "nss_eth_rx_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_eth_rx_stats_notifier);
+
+uint64_t nss_eth_rx_stats[NSS_ETH_RX_STATS_MAX];			/* ETH_RX statistics */
+uint64_t nss_eth_rx_exception_stats[NSS_ETH_RX_EXCEPTION_EVENT_MAX];	/* Unknown protocol exception events per interface */
+
+/*
+ * nss_eth_rx_stats_read()
+ *	Read ETH_RX stats.
+ */
+static ssize_t nss_eth_rx_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * Max output lines = #stats * NSS_MAX_CORES  +
+	 * few blank lines for banner printing + Number of Extra outputlines for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_STATS_NODE_MAX + NSS_ETH_RX_STATS_MAX + NSS_ETH_RX_EXCEPTION_EVENT_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	/*
+	 * Note: The assumption here is that we do not have more than 64 stats.
+	 */
+	stats_shadow = kzalloc(64 * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "eth_rx", NSS_STATS_SINGLE_CORE);
+
+	size_wr += nss_stats_fill_common_stats(NSS_ETH_RX_INTERFACE, NSS_STATS_SINGLE_INSTANCE, lbuf, size_wr, size_al, "eth_rx");
+
+	/*
+	 * eth_rx node stats.
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; (i < NSS_ETH_RX_STATS_MAX); i++) {
+		stats_shadow[i] = nss_eth_rx_stats[i];
+	}
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+
+	size_wr += nss_stats_print("eth_rx", "eth_rx node stats"
+					, NSS_STATS_SINGLE_INSTANCE
+					, nss_eth_rx_strings_stats
+					, stats_shadow
+					, NSS_ETH_RX_STATS_MAX
+					, lbuf, size_wr, size_al);
+
+	/*
+	 * Exception stats.
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; (i < NSS_ETH_RX_EXCEPTION_EVENT_MAX); i++) {
+		stats_shadow[i] = nss_eth_rx_exception_stats[i];
+	}
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+
+	size_wr += nss_stats_print("eth_rx", "eth_rx exception stats"
+					, NSS_STATS_SINGLE_INSTANCE
+					, nss_eth_rx_strings_exception_stats
+					, stats_shadow
+					, NSS_ETH_RX_EXCEPTION_EVENT_MAX
+					, lbuf, size_wr, size_al);
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_eth_rx_stats_ops.
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(eth_rx);
+
+/*
+ * nss_eth_rx_stats_dentry_create()
+ *	Create eth_rx statistics debug entry.
+ */
+void nss_eth_rx_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("eth_rx", &nss_eth_rx_stats_ops);
+}
+
+/*
+ * nss_eth_rx_metadata_stats_sync()
+ *	Handle the syncing of ETH_RX node statistics.
+ */
+void nss_eth_rx_metadata_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_eth_rx_node_sync *nens)
+{
+	int32_t i;
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	spin_lock_bh(&nss_top->stats_lock);
+
+	nss_top->stats_node[NSS_ETH_RX_INTERFACE][NSS_STATS_NODE_RX_PKTS] += nens->node_stats.rx_packets;
+	nss_top->stats_node[NSS_ETH_RX_INTERFACE][NSS_STATS_NODE_RX_BYTES] += nens->node_stats.rx_bytes;
+	nss_top->stats_node[NSS_ETH_RX_INTERFACE][NSS_STATS_NODE_TX_PKTS] += nens->node_stats.tx_packets;
+	nss_top->stats_node[NSS_ETH_RX_INTERFACE][NSS_STATS_NODE_TX_BYTES] += nens->node_stats.tx_bytes;
+
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		nss_top->stats_node[NSS_ETH_RX_INTERFACE][NSS_STATS_NODE_RX_QUEUE_0_DROPPED + i] += nens->node_stats.rx_dropped[i];
+	}
+
+	nss_eth_rx_stats[NSS_ETH_RX_STATS_TOTAL_TICKS] += nens->total_ticks;
+	nss_eth_rx_stats[NSS_ETH_RX_STATS_WORST_CASE_TICKS] += nens->worst_case_ticks;
+	nss_eth_rx_stats[NSS_ETH_RX_STATS_ITERATIONS] += nens->iterations;
+
+	for (i = 0; i < NSS_ETH_RX_EXCEPTION_EVENT_MAX; i++) {
+		nss_eth_rx_exception_stats[i] += nens->exception_events[i];
+	}
+
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_eth_rx_stats_notify()
+ *	Sends notifications to the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_eth_rx_stats_notify(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_eth_rx_stats_notification eth_rx_stats;
+
+	eth_rx_stats.core_id = nss_ctx->id;
+	memcpy(eth_rx_stats.cmn_node_stats, nss_top_main.stats_node[NSS_ETH_RX_INTERFACE], sizeof(eth_rx_stats.cmn_node_stats));
+	memcpy(eth_rx_stats.special_stats, nss_eth_rx_stats, sizeof(eth_rx_stats.special_stats));
+	memcpy(eth_rx_stats.exception_stats, nss_eth_rx_exception_stats, sizeof(eth_rx_stats.exception_stats));
+	atomic_notifier_call_chain(&nss_eth_rx_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&eth_rx_stats);
+}
+
+/*
+ * nss_eth_rx_stats_register_notifier()
+ *      Registers statistics notifier.
+ */
+int nss_eth_rx_stats_register_notifier(struct notifier_block *nb)
+{
+        return atomic_notifier_chain_register(&nss_eth_rx_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_eth_rx_stats_register_notifier);
+
+/*
+ * nss_eth_rx_stats_unregister_notifier()
+ *      Deregisters statistics notifier.
+ */
+int nss_eth_rx_stats_unregister_notifier(struct notifier_block *nb)
+{
+        return atomic_notifier_chain_unregister(&nss_eth_rx_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_eth_rx_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_eth_rx_stats.h b/qca-nss-drv/nss_eth_rx_stats.h
new file mode 100644
index 0000000..c5470ba
--- /dev/null
+++ b/qca-nss-drv/nss_eth_rx_stats.h
@@ -0,0 +1,65 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_ETH_RX_STATS_H
+#define __NSS_ETH_RX_STATS_H
+
+#include <nss_cmn.h>
+
+/*
+ * nss_eth_rx_stats.h
+ *	NSS driver ETH_RX statistics header file.
+ */
+
+/*
+ * Request/Response types
+ */
+enum nss_eth_rx_metadata_types {
+	NSS_RX_METADATA_TYPE_ETH_RX_STATS_SYNC,
+	NSS_METADATA_TYPE_ETH_RX_MAX,
+};
+
+/*
+ * The NSS eth_rx node stats structure.
+ */
+struct nss_eth_rx_node_sync {
+	struct nss_cmn_node_stats node_stats;
+				/* Common node stats for ETH_RX */
+	uint32_t total_ticks;		/* Total clock ticks spend inside the eth_rx */
+	uint32_t worst_case_ticks;	/* Worst case iteration of the eth_rx in ticks */
+	uint32_t iterations;		/* Number of iterations around the eth_rx */
+	uint32_t exception_events[NSS_ETH_RX_EXCEPTION_EVENT_MAX];
+				/* Number of ETH_RX exception events */
+};
+
+/*
+ * Message structure to send/receive eth_rx commands
+ */
+struct nss_eth_rx_msg {
+	struct nss_cmn_msg cm;		/* Message Header */
+	union {
+		struct nss_eth_rx_node_sync node_sync;	/* Message: node statistics sync */
+	} msg;
+};
+
+/*
+ * eth_rx statistics APIs
+ */
+extern void nss_eth_rx_stats_notify(struct nss_ctx_instance *nss_ctx);
+extern void nss_eth_rx_metadata_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_eth_rx_node_sync *nens);
+extern void nss_eth_rx_stats_dentry_create(void);
+
+#endif /* __NSS_ETH_RX_STATS_H */
diff --git a/qca-nss-drv/nss_eth_rx_strings.c b/qca-nss-drv/nss_eth_rx_strings.c
new file mode 100644
index 0000000..8412b44
--- /dev/null
+++ b/qca-nss-drv/nss_eth_rx_strings.c
@@ -0,0 +1,106 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+
+/*
+ * nss_eth_rx_strings_stats
+ *	Ethernet Rx statistics strings.
+ */
+struct nss_stats_info nss_eth_rx_strings_stats[NSS_ETH_RX_STATS_MAX] = {
+	{"ticks"	, NSS_STATS_TYPE_SPECIAL},
+	{"worst_ticks"	, NSS_STATS_TYPE_SPECIAL},
+	{"iterations"	, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_eth_rx_strings_exception_stats
+ *	Interface statistics strings for unknown exceptions.
+ */
+struct nss_stats_info nss_eth_rx_strings_exception_stats[NSS_ETH_RX_EXCEPTION_EVENT_MAX] = {
+	{"unknown_l3_protocol"	, NSS_STATS_TYPE_EXCEPTION},
+	{"eth_hdr_missing"	, NSS_STATS_TYPE_EXCEPTION},
+	{"vlan_missing"		, NSS_STATS_TYPE_EXCEPTION},
+	{"trustsec_hdr_missing"	, NSS_STATS_TYPE_EXCEPTION}
+};
+
+/*
+ * nss_eth_rx_special_stats_strings_read()
+ *	Read Ethernet Rx special node statistics names.
+ */
+static ssize_t nss_eth_rx_special_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_eth_rx_strings_stats, NSS_ETH_RX_STATS_MAX);
+}
+
+/*
+ * nss_eth_rx_exception_stats_strings_read()
+ *	Read Ethernet Rx exception statistics names.
+ */
+static ssize_t nss_eth_rx_exception_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_eth_rx_strings_exception_stats, NSS_ETH_RX_EXCEPTION_EVENT_MAX);
+}
+
+/*
+ * nss_eth_rx_special_stats_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(eth_rx_special_stats);
+
+/*
+ * nss_eth_rx_exception_stats_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(eth_rx_exception_stats);
+
+/*
+ * nss_eth_rx_strings_dentry_create()
+ *      Create Ethernet Rx statistics strings debug entry.
+ */
+void nss_eth_rx_strings_dentry_create(void)
+{
+	struct dentry *eth_rx_d = NULL;
+	struct dentry *eth_rx_spcl_stats_d = NULL;
+	struct dentry *eth_rx_excp_stats_d = NULL;
+
+	if (!nss_top_main.strings_dentry) {
+		nss_warning("qca-nss-drv/strings is not present");
+		return;
+	}
+
+	eth_rx_d = debugfs_create_dir("eth_rx", nss_top_main.strings_dentry);
+	if (!eth_rx_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/eth_rx directory");
+		return;
+	}
+
+	eth_rx_spcl_stats_d = debugfs_create_file("special_stats_str", 0400, eth_rx_d, &nss_top_main, &nss_eth_rx_special_stats_strings_ops);
+	if (!eth_rx_spcl_stats_d) {
+		nss_warning("Failed to create qca-nss-drv/stats/eth_rx/special_stats_str file");
+		debugfs_remove_recursive(eth_rx_d);
+		return;
+	}
+
+	eth_rx_excp_stats_d = debugfs_create_file("exception_stats_str", 0400, eth_rx_d, &nss_top_main, &nss_eth_rx_exception_stats_strings_ops);
+	if (!eth_rx_excp_stats_d) {
+		nss_warning("Failed to create qca-nss-drv/stats/eth_rx/exception_stats_str file");
+		debugfs_remove_recursive(eth_rx_d);
+		return;
+	}
+}
diff --git a/qca-nss-drv/nss_eth_rx_strings.h b/qca-nss-drv/nss_eth_rx_strings.h
new file mode 100644
index 0000000..2f40440
--- /dev/null
+++ b/qca-nss-drv/nss_eth_rx_strings.h
@@ -0,0 +1,26 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_ETH_RX_STRINGS_H
+#define __NSS_ETH_RX_STRINGS_H
+
+extern struct nss_stats_info nss_eth_rx_strings_stats[NSS_ETH_RX_STATS_MAX];
+extern struct nss_stats_info nss_eth_rx_strings_exception_stats[NSS_ETH_RX_EXCEPTION_EVENT_MAX];
+extern void nss_eth_rx_strings_dentry_create(void);
+
+#endif /* __NSS_ETH_RX_STRINGS_H */
diff --git a/qca-nss-drv/nss_freq.c b/qca-nss-drv/nss_freq.c
new file mode 100644
index 0000000..d55bd63
--- /dev/null
+++ b/qca-nss-drv/nss_freq.c
@@ -0,0 +1,467 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013, 2015-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_freq.c
+ *	NSS frequency change APIs
+ */
+
+#include "nss_stats.h"
+#include "nss_tx_rx_common.h"
+#include "nss_freq_log.h"
+#include "nss_freq_stats.h"
+
+#define NSS_ACK_STARTED 0
+#define NSS_ACK_FINISHED 1
+
+#define NSS_FREQ_USG_AVG_FREQUENCY	1000		/* Time in ms over which CPU Usage is averaged */
+#define NSS_FREQ_CPU_USAGE_MAX_BOUND	75		/* MAX CPU usage equivalent to running max instructions excluding all the hazards */
+#define NSS_FREQ_CPU_USAGE_MAX		100 		/* MAX CPU usage equivalent to running max instructions including all the hazards.
+							   This is also the ideal maximum usage value. */
+
+/*
+ * Spinlock to protect the global data structure nss_freq_cpu_status
+ */
+DEFINE_SPINLOCK(nss_freq_cpu_usage_lock);
+
+/*
+ * At any point, this object has the latest data about CPU utilization.
+ */
+struct nss_freq_cpu_usage nss_freq_cpu_status;
+
+extern struct nss_runtime_sampling nss_runtime_samples;
+extern struct workqueue_struct *nss_wq;
+extern nss_work_t *nss_work;
+
+/*
+ * nss_freq_msg_init()
+ *	Initialize the freq message
+ */
+static void nss_freq_msg_init(struct nss_corefreq_msg *ncm, uint16_t if_num, uint32_t type, uint32_t len,
+			void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+
+/*
+ * nss_freq_handle_ack()
+ *	Handle the nss ack of frequency change.
+ */
+static void nss_freq_handle_ack(struct nss_ctx_instance *nss_ctx, struct nss_freq_msg *nfa)
+{
+	if (nfa->ack == NSS_ACK_STARTED) {
+		/*
+		 * NSS finished start noficiation - HW change clocks and send end notification
+		 */
+		nss_info("%px: NSS ACK Received: %d - Change HW CLK/Send Finish to NSS\n", nss_ctx, nfa->ack);
+
+		return;
+	}
+
+	if (nfa->ack == NSS_ACK_FINISHED) {
+		/*
+		 * NSS finished end notification - Done
+		 */
+		nss_info("%px: NSS ACK Received: %d - End Notification ACK - Running: %dmhz\n", nss_ctx, nfa->ack, nfa->freq_current);
+		nss_runtime_samples.freq_scale_ready = 1;
+		return;
+	}
+
+	nss_info("%px: NSS had an error - Running: %dmhz\n", nss_ctx, nfa->freq_current);
+}
+
+/*
+ * nss_freq_queue_work()
+ *	Queue Work to the NSS Workqueue based on Current index.
+ */
+static bool nss_freq_queue_work(void)
+{
+	nss_freq_scales_t index = nss_runtime_samples.freq_scale_index;
+
+	BUG_ON(!nss_wq);
+
+	nss_info("frequency:%d index:%d sample count:%x\n", nss_runtime_samples.freq_scale[index].frequency,
+					index, nss_runtime_samples.average);
+
+	/*
+	 * schedule freq change with autoscale ON
+	 */
+	return nss_freq_sched_change(index, true);
+}
+
+/*
+ * nss_freq_get_cpu_usage()
+ * 	Returns the CPU usage value in percentage at any instance for a required core. Returns -1 in case of an error.
+ *
+ * Calculation frequency is 1 second. Range of usage is 0-100. This API returns -1 if CPU usage is requested for core 1.
+ * TODO: Extend this API to get CPU usage for core 1.
+ */
+int8_t nss_freq_get_cpu_usage(uint32_t core_id)
+{
+	int8_t usage;
+
+	if (core_id == 0) {
+		spin_lock_bh(&nss_freq_cpu_usage_lock);
+		usage = nss_freq_cpu_status.used;
+		spin_unlock_bh(&nss_freq_cpu_usage_lock);
+
+		return usage;
+	}
+
+	nss_warning("CPU usage functionality is not supported for core %u\n", core_id);
+	return -1;
+}
+
+/*
+ * nss_freq_compute_cpu_usage()
+ * 	Computes the CPU utilization and maximum-minumun cpu utilization since boot.
+ */
+static void nss_freq_compute_cpu_usage(struct nss_ctx_instance *nss_ctx, uint32_t inst_cnt)
+{
+	uint32_t estimated_ins_capacity;
+	uint8_t actual_usage;
+	uint8_t usage;
+
+	spin_lock_bh(&nss_freq_cpu_usage_lock);
+
+	/*
+	 * If actual CPU usage turns up higher than 100, there is something wrong with the received data.
+	 * Upper bound average varies between 80% usage to 100% usage.
+	 *
+	 * TODO: To improve estimation algorithm for calculating how many actual instructions are executed.
+	 */
+	actual_usage = (inst_cnt * 100) / nss_freq_cpu_status.max_ins;
+	if ((actual_usage > NSS_FREQ_CPU_USAGE_MAX) || (actual_usage == 0)) {
+		spin_unlock_bh(&nss_freq_cpu_usage_lock);
+		return;
+	}
+
+	/*
+	 * Simpler version of below math: This is calculating the reduced number of maximum instructions
+	 * estimated_ins_capacity = nss_freq_cpu_status.avg_up% of nss_freq_cpu_status.max_ins
+	 * Calculating usage percentage: usage = (inst_cnt/estimated_ins_capacity) * 100
+	 */
+	estimated_ins_capacity = ((NSS_FREQ_CPU_USAGE_MAX_BOUND * nss_freq_cpu_status.max_ins) / 100);
+	if (estimated_ins_capacity == 0) {
+		spin_unlock_bh(&nss_freq_cpu_usage_lock);
+		return;
+	}
+	usage = (inst_cnt * 100) / estimated_ins_capacity;
+
+	/*
+	 * Average the instructions over NSS_FREQ_USG_AVG_FREQUENCY ms
+	 */
+	if (nss_freq_cpu_status.avg_ctr == NSS_FREQ_USG_AVG_FREQUENCY) {
+		nss_freq_cpu_status.used = nss_freq_cpu_status.total / NSS_FREQ_USG_AVG_FREQUENCY;
+
+		/*
+		 * Due to our estimation, this could go beyond the end limit of 100%
+		 */
+		if (nss_freq_cpu_status.used > NSS_FREQ_CPU_USAGE_MAX) {
+			nss_freq_cpu_status.used = NSS_FREQ_CPU_USAGE_MAX;
+		}
+
+		/*
+		 * Getting the all time max and min usage
+		 */
+		if (nss_freq_cpu_status.used > nss_freq_cpu_status.max) {
+			nss_freq_cpu_status.max = nss_freq_cpu_status.used;
+		}
+
+		if (nss_freq_cpu_status.used < nss_freq_cpu_status.min) {
+			nss_freq_cpu_status.min = nss_freq_cpu_status.used;
+		}
+
+		nss_trace("%px: max_instructions:%d cpu_usage:%d max_usage:%d min_usage:%d\n", nss_ctx,
+				nss_freq_cpu_status.max_ins, nss_freq_cpu_status.used, nss_freq_cpu_status.max, nss_freq_cpu_status.min);
+
+		nss_freq_cpu_status.total = 0;
+		nss_freq_cpu_status.avg_ctr = 0;
+	}
+
+	nss_freq_cpu_status.total += usage;
+	nss_freq_cpu_status.avg_ctr++;
+
+	spin_unlock_bh(&nss_freq_cpu_usage_lock);
+}
+
+/*
+ * nss_freq_scale_frequency()
+ * 	Frequency scaling algorithm to scale frequency.
+ */
+void nss_freq_scale_frequency(struct nss_ctx_instance *nss_ctx, uint32_t inst_cnt)
+{
+	uint32_t b_index;
+	uint32_t minimum;
+	uint32_t maximum;
+	uint32_t index = nss_runtime_samples.freq_scale_index;
+
+	/*
+	 * We do not accept any statistics if auto scaling is off,
+	 * we start with a fresh sample set when scaling is
+	 * eventually turned on.
+	 */
+	if (!nss_cmd_buf.auto_scale && nss_runtime_samples.initialized) {
+		return;
+	}
+
+	/*
+	 * Delete Current Index Value, Add New Value, Recalculate new Sum, Shift Index
+	 */
+	b_index = nss_runtime_samples.buffer_index;
+
+	nss_runtime_samples.sum = nss_runtime_samples.sum - nss_runtime_samples.buffer[b_index];
+	nss_runtime_samples.buffer[b_index] = inst_cnt;
+	nss_runtime_samples.sum = nss_runtime_samples.sum + nss_runtime_samples.buffer[b_index];
+	nss_runtime_samples.buffer_index = (b_index + 1) & NSS_SAMPLE_BUFFER_MASK;
+
+	if (nss_runtime_samples.sample_count < NSS_SAMPLE_BUFFER_SIZE) {
+		nss_runtime_samples.sample_count++;
+
+		/*
+		 * Samples Are All Ready, Start Auto Scale
+		 */
+		if (nss_runtime_samples.sample_count == NSS_SAMPLE_BUFFER_SIZE ) {
+			nss_cmd_buf.auto_scale = 1;
+			nss_runtime_samples.freq_scale_ready = 1;
+			nss_runtime_samples.initialized = 1;
+		}
+
+		return;
+	}
+
+	nss_runtime_samples.average = nss_runtime_samples.sum / nss_runtime_samples.sample_count;
+
+	/*
+	 * Print out statistics every 10 samples
+	 */
+	if (nss_runtime_samples.message_rate_limit++ >= NSS_MESSAGE_RATE_LIMIT) {
+		nss_trace("%px: Running AVG:%x Sample:%x Divider:%d\n", nss_ctx, nss_runtime_samples.average, inst_cnt, nss_runtime_samples.sample_count);
+		nss_trace("%px: Current Frequency Index:%d\n", nss_ctx, index);
+		nss_trace("%px: Auto Scale Ready:%d Auto Scale:%d\n", nss_ctx, nss_runtime_samples.freq_scale_ready, nss_cmd_buf.auto_scale);
+		nss_trace("%px: Current Rate:%x\n", nss_ctx, nss_runtime_samples.average);
+
+		nss_runtime_samples.message_rate_limit = 0;
+	}
+
+	/*
+	 * Don't scale if we are not ready or auto scale is disabled.
+	 */
+	if ((nss_runtime_samples.freq_scale_ready != 1) || (nss_cmd_buf.auto_scale != 1)) {
+		return;
+	}
+
+	/*
+	 * Scale Algorithmn
+	 *	Algorithmn will limit how fast it will transition each scale, by the number of samples seen.
+	 *	If any sample is out of scale during the idle count, the rate_limit will reset to 0.
+	 *	Scales are limited to the max number of cpu scales we support.
+	 */
+	if (nss_runtime_samples.freq_scale_rate_limit_up++ >= NSS_FREQUENCY_SCALE_RATE_LIMIT_UP) {
+		maximum = nss_runtime_samples.freq_scale[index].maximum;
+		if ((nss_runtime_samples.average > maximum) && (index < (NSS_FREQ_MAX_SCALE - 1))) {
+			nss_runtime_samples.freq_scale_index++;
+			nss_runtime_samples.freq_scale_ready = 0;
+
+			/*
+			 * If fail to increase frequency, decrease index
+			 */
+			nss_trace("frequency increase to %d inst:%x > maximum:%x\n", nss_runtime_samples.freq_scale[nss_runtime_samples.freq_scale_index].frequency, inst_cnt, maximum);
+			if (!nss_freq_queue_work()) {
+				nss_runtime_samples.freq_scale_index--;
+			}
+		}
+
+		/*
+		 * Reset the down scale counter based on running average, so can idle properly
+		 */
+		if (nss_runtime_samples.average > maximum) {
+			nss_trace("down scale timeout reset running average:%x\n", nss_runtime_samples.average);
+			nss_runtime_samples.freq_scale_rate_limit_down = 0;
+		}
+
+		nss_runtime_samples.freq_scale_rate_limit_up = 0;
+		return;
+	}
+
+	if (nss_runtime_samples.freq_scale_rate_limit_down++ >= NSS_FREQUENCY_SCALE_RATE_LIMIT_DOWN) {
+		minimum = nss_runtime_samples.freq_scale[index].minimum;
+
+		/*
+		 * Check if we need to lower the frequency. For some SoC like IPQ50xx, low frequency
+		 * is not supported. So check if the next lower frequency is configured before shifting down
+		 */
+		if ((nss_runtime_samples.average < minimum) && (index > 0) && nss_runtime_samples.freq_scale[index - 1].maximum) {
+			nss_runtime_samples.freq_scale_index--;
+			nss_runtime_samples.freq_scale_ready = 0;
+
+			/*
+			 * If fail to decrease frequency, increase index
+			 */
+			nss_trace("frequency decrease to %d inst:%x < minumum:%x\n", nss_runtime_samples.freq_scale[nss_runtime_samples.freq_scale_index].frequency, nss_runtime_samples.average, minimum);
+			if (!nss_freq_queue_work()) {
+				nss_runtime_samples.freq_scale_index++;
+			}
+		}
+		nss_runtime_samples.freq_scale_rate_limit_down = 0;
+		return;
+	}
+}
+
+/*
+ *  nss_freq_handle_core_stats()
+ *	Handle the core stats.
+ */
+static void nss_freq_handle_core_stats(struct nss_ctx_instance *nss_ctx, struct nss_core_stats *core_stats)
+{
+	uint32_t inst_cnt = core_stats->inst_cnt_total;
+
+	/*
+	 * compute CPU utilization by using the instruction count
+	 */
+	nss_freq_compute_cpu_usage(nss_ctx, inst_cnt);
+
+	/*
+	 * Perform frequency scaling
+	 */
+	nss_freq_scale_frequency(nss_ctx, inst_cnt);
+}
+
+/*
+ * nss_freq_interface_handler()
+ *	Handle NSS -> HLOS messages for Frequency Changes and Statistics.
+ */
+static void nss_freq_interface_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data) {
+
+	struct nss_corefreq_msg *ncfm = (struct nss_corefreq_msg *)ncm;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_freq_log_rx_msg(ncfm);
+
+	switch (ncfm->cm.type) {
+	case COREFREQ_METADATA_TYPE_TX_FREQ_ACK:
+		nss_freq_handle_ack(nss_ctx, &ncfm->msg.nfc);
+		break;
+	case COREFREQ_METADATA_TYPE_TX_CORE_STATS:
+		nss_freq_handle_core_stats(nss_ctx, &ncfm->msg.ncs);
+		break;
+
+	default:
+		if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+			/*
+			 * Check response
+			 */
+			nss_info("%px: Received response %d for type %d, interface %d", nss_ctx, ncm->response, ncm->type, ncm->interface);
+		}
+	}
+}
+
+/*
+ * nss_freq_change()
+ *	NSS frequency change API.
+ */
+nss_tx_status_t nss_freq_change(struct nss_ctx_instance *nss_ctx, uint32_t eng, uint32_t stats_enable, uint32_t start_or_end)
+{
+	struct nss_corefreq_msg ncm;
+	struct nss_freq_msg *nfc;
+
+	nss_info("%px: frequency changing to: %d\n", nss_ctx, eng);
+
+	/*
+	 * Update the max instruction count for a frequency during down scaling.
+	 * Better to update this as late as possible in the frequency update call.
+	 */
+	spin_lock_bh(&nss_freq_cpu_usage_lock);
+	nss_freq_cpu_status.max_ins = eng / 1000;
+	spin_unlock_bh(&nss_freq_cpu_usage_lock);
+
+	nss_freq_msg_init(&ncm, NSS_COREFREQ_INTERFACE, NSS_TX_METADATA_TYPE_NSS_FREQ_CHANGE,
+				sizeof(struct nss_freq_msg), NULL, NULL);
+	nfc = &ncm.msg.nfc;
+	nfc->frequency = eng;
+	nfc->start_or_end = start_or_end;
+	nfc->stats_enable = stats_enable;
+
+	return nss_core_send_cmd(nss_ctx, &ncm, sizeof(ncm), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ * nss_freq_sched_change()
+ *	Schedule a frequency work.
+ */
+bool nss_freq_sched_change(nss_freq_scales_t index, bool auto_scale)
+{
+	if (index >= NSS_FREQ_MAX_SCALE) {
+		nss_info("NSS freq scale beyond limit\n");
+		return false;
+	}
+
+	nss_work = (nss_work_t *)kmalloc(sizeof(nss_work_t), GFP_ATOMIC);
+	if (!nss_work) {
+		nss_info("NSS Freq WQ kmalloc fail");
+		return false;
+	}
+
+	INIT_WORK((struct work_struct *)nss_work, nss_hal_wq_function);
+
+	nss_work->frequency = nss_runtime_samples.freq_scale[index].frequency;
+
+	nss_work->stats_enable = auto_scale;
+	nss_cmd_buf.current_freq = nss_work->frequency;
+	queue_work(nss_wq, (struct work_struct *)nss_work);
+
+	return true;
+}
+
+/*
+ * nss_freq_get_context()
+ *	Get NSS context instance for frequency.
+ */
+struct nss_ctx_instance *nss_freq_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.frequency_handler_id];
+}
+EXPORT_SYMBOL(nss_freq_get_context);
+
+/*
+ * nss_freq_register_handler()
+ */
+void nss_freq_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_freq_get_context();
+	nss_core_register_handler(nss_ctx, NSS_COREFREQ_INTERFACE, nss_freq_interface_handler, NULL);
+}
+
+/*
+ * nss_freq_cpu_usage_init()
+ * 	Initialize cpu usage computing.
+ *
+ * TODO: Add support to retrieve CPU usage even if frequency scaling is disabled.
+ */
+void nss_freq_init_cpu_usage(void)
+{
+	nss_freq_cpu_status.used = 0;
+	nss_freq_cpu_status.max_ins = nss_runtime_samples.freq_scale[nss_runtime_samples.freq_scale_index].frequency / 1000;
+	nss_freq_cpu_status.total = 0;
+	nss_freq_cpu_status.max = 0;					/* Initial value is 0 to capture the highest most value during the run */
+	nss_freq_cpu_status.min = NSS_FREQ_CPU_USAGE_MAX;		/* Initial value is 100 to capture the lowest most value during the run */
+	nss_freq_cpu_status.avg_up = NSS_FREQ_CPU_USAGE_MAX_BOUND;
+	nss_freq_cpu_status.avg_ctr = 0;
+
+	nss_freq_stats_dentry_create();
+}
diff --git a/qca-nss-drv/nss_freq_log.c b/qca-nss-drv/nss_freq_log.c
new file mode 100644
index 0000000..9b96184
--- /dev/null
+++ b/qca-nss-drv/nss_freq_log.c
@@ -0,0 +1,100 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_freq_log.c
+ *	NSS Freq logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_freq_log_message_types_str
+ *	Freq message strings
+ */
+static int8_t *nss_freq_log_message_types_str[COREFREQ_METADATA_TYPE_MAX] __maybe_unused = {
+	"Freq Error Message",
+	"Freq Change",
+	"Freq ACK",
+	"TX Core Stats",
+};
+
+/*
+ * nss_freq_log_msg()
+ *	Log NSS Freq message.
+ */
+static void nss_freq_log_msg(struct nss_corefreq_msg *ncm)
+{
+	struct nss_freq_msg *nfm __maybe_unused = &ncm->msg.nfc;
+	nss_trace("%px: NSS Freq Message:\n"
+		"Frequency request: %d\n"
+		"Frequency start/end: %d\n"
+		"Frequency stats enable: %d\n"
+		"Current Frequency: %d\n"
+		"Frequency ACK: %d\n",
+		nfm, nfm->frequency, nfm->start_or_end,
+		nfm->stats_enable, nfm->freq_current,
+		nfm->ack);
+}
+
+/*
+ * nss_freq_log_verbose()
+ *	Log message contents.
+ */
+static void nss_freq_log_verbose(struct nss_corefreq_msg *ncm)
+{
+	switch (ncm->cm.type) {
+	case COREFREQ_METADATA_TYPE_RX_FREQ_CHANGE:
+	case COREFREQ_METADATA_TYPE_TX_FREQ_ACK:
+		nss_freq_log_msg(ncm);
+		break;
+
+	case COREFREQ_METADATA_TYPE_TX_CORE_STATS:
+		/*
+		 * No log for a valid stats message.
+		 */
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", ncm);
+		break;
+	}
+}
+
+/*
+ * nss_freq_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_freq_log_rx_msg(struct nss_corefreq_msg *ncm)
+{
+	if (ncm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ncm);
+		return;
+	}
+
+	if (ncm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ncm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d], response[%d]:%s\n", ncm, ncm->cm.type,
+			ncm->cm.response, nss_cmn_response_str[ncm->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		ncm, ncm->cm.type, nss_freq_log_message_types_str[ncm->cm.type],
+		ncm->cm.response, nss_cmn_response_str[ncm->cm.response]);
+
+verbose:
+	nss_freq_log_verbose(ncm);
+}
diff --git a/qca-nss-drv/nss_freq_log.h b/qca-nss-drv/nss_freq_log.h
new file mode 100644
index 0000000..ab7d7d4
--- /dev/null
+++ b/qca-nss-drv/nss_freq_log.h
@@ -0,0 +1,35 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_FREQ_LOG_H
+#define __NSS_FREQ_LOG_H
+
+/*
+ * nss_freq_log.h
+ *	NSS frequency log header file.
+ */
+
+/*
+ * Logger APIs
+ */
+
+/*
+ * nss_freq_log_rx_msg
+ *	Logs a frequency message that is received from the NSS firmware.
+ */
+void nss_freq_log_rx_msg(struct nss_corefreq_msg *nbm);
+
+#endif /* __NSS_FREQ_LOG_H */
diff --git a/qca-nss-drv/nss_freq_stats.c b/qca-nss-drv/nss_freq_stats.c
new file mode 100644
index 0000000..32e62c3
--- /dev/null
+++ b/qca-nss-drv/nss_freq_stats.c
@@ -0,0 +1,86 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_freq_stats.c
+ *	NSS Frequency statistics APIs.
+ */
+
+#include "nss_stats.h"
+#include "nss_tx_rx_common.h"
+
+/*
+ * At any point, this object has the latest data about CPU utilization.
+ */
+extern struct nss_freq_cpu_usage nss_freq_cpu_status;
+
+/*
+ * Spinlock to protect the global data structure nss_freq_cpu_status
+ */
+extern spinlock_t nss_freq_cpu_usage_lock;
+
+/*
+ * nss_freq_stats_read()
+ * 	Read frequency stats and display CPU information.
+ */
+static ssize_t nss_freq_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	/*
+	 * max output lines = Should change in case of number of lines below.
+	 */
+	uint32_t max_output_lines = (2 + 3) + 5;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint32_t avg, max, min;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	size_wr = scnprintf(lbuf, size_al, "CPU Utilization:\n");
+
+	spin_lock_bh(&nss_freq_cpu_usage_lock);
+	avg = nss_freq_cpu_status.used;
+	max = nss_freq_cpu_status.max;
+	min = nss_freq_cpu_status.min;
+	spin_unlock_bh(&nss_freq_cpu_usage_lock);
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "Note: Averaged over 1 second\n\n");
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "Core 0:\n");
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "Min\tAvg\tMax\n");
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, " %u%%\t %u%%\t %u%%\n\n", min, avg, max);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+
+	return bytes_read;
+}
+
+/*
+ * nss_freq_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(freq)
+
+/*
+ * nss_freq_dentry_create()
+ */
+void nss_freq_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("cpu_load_ubi", &nss_freq_stats_ops);
+}
\ No newline at end of file
diff --git a/qca-nss-drv/nss_freq_stats.h b/qca-nss-drv/nss_freq_stats.h
new file mode 100644
index 0000000..72e00cc
--- /dev/null
+++ b/qca-nss-drv/nss_freq_stats.h
@@ -0,0 +1,29 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+/*
+ * nss_freq_stats.h
+ *	NSS Frequency statistics header file.
+ */
+
+#ifndef __NSS_FREQ_STATS_H
+#define __NSS_FREQ_STATS_H
+
+#include "nss_core.h"
+
+extern void nss_freq_stats_dentry_create(void);
+
+#endif	/* __NSS_FREQ_STATS_H */
\ No newline at end of file
diff --git a/qca-nss-drv/nss_gmac_stats.c b/qca-nss-drv/nss_gmac_stats.c
new file mode 100644
index 0000000..23f5924
--- /dev/null
+++ b/qca-nss-drv/nss_gmac_stats.c
@@ -0,0 +1,83 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_gmac_stats.h"
+
+/*
+ * nss_gmac_stats_str
+ *	GMAC stats strings.
+ */
+struct nss_stats_info nss_gmac_stats_str[NSS_GMAC_STATS_MAX] = {
+	{"ticks"	, NSS_STATS_TYPE_SPECIAL},
+	{"worst_ticks"	, NSS_STATS_TYPE_SPECIAL},
+	{"iterations"	, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_gmac_stats_read()
+ *	Read GMAC stats.
+ */
+ssize_t nss_gmac_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	uint32_t i, id;
+
+	/*
+	 * max output lines = ((#stats + start tag + one blank) * #GMACs) Number of Extra outputlines for future
+	 * reference to add new stats + start/end tag + 3 blank
+	 */
+	uint32_t max_output_lines = NSS_GMAC_STATS_MAX * NSS_MAX_PHYSICAL_INTERFACES + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_GMAC_STATS_MAX * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "gmac", NSS_STATS_SINGLE_CORE);
+
+	for (id = 0; id < NSS_MAX_PHYSICAL_INTERFACES; id++) {
+		spin_lock_bh(&nss_top_main.stats_lock);
+		for (i = 0; (i < NSS_GMAC_STATS_MAX); i++) {
+			stats_shadow[i] = nss_top_main.stats_gmac[id][i];
+		}
+
+		spin_unlock_bh(&nss_top_main.stats_lock);
+		size_wr += nss_stats_print("gmac", "gmac stats", id
+						, nss_gmac_stats_str
+						, stats_shadow
+						, NSS_GMAC_STATS_MAX
+						, lbuf, size_wr, size_al);
+	}
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\ngmac stats end\n\n");
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
diff --git a/qca-nss-drv/nss_gmac_stats.h b/qca-nss-drv/nss_gmac_stats.h
new file mode 100644
index 0000000..646143e
--- /dev/null
+++ b/qca-nss-drv/nss_gmac_stats.h
@@ -0,0 +1,33 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_GMAC_STATS_H
+#define __NSS_GMAC_STATS_H
+
+#include <linux/debugfs.h>
+
+/*
+ * GMAC node statistics
+ */
+enum nss_stats_gmac {
+	NSS_GMAC_STATS_TOTAL_TICKS,		/* Total clock ticks spend inside the GMAC */
+	NSS_GMAC_STATS_WORST_CASE_TICKS,	/* Worst case iteration of the GMAC in ticks */
+	NSS_GMAC_STATS_ITERATIONS,		/* Number of iterations around the GMAC */
+	NSS_GMAC_STATS_MAX,
+};
+
+extern ssize_t nss_gmac_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos);
+#endif /* __NSS_GMAC_STATS_H */
diff --git a/qca-nss-drv/nss_gre.c b/qca-nss-drv/nss_gre.c
new file mode 100644
index 0000000..46cd72c
--- /dev/null
+++ b/qca-nss-drv/nss_gre.c
@@ -0,0 +1,411 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_gre_stats.h"
+#include "nss_gre_log.h"
+#include "nss_gre_strings.h"
+
+#define NSS_GRE_TX_TIMEOUT 3000 /* 3 Seconds */
+
+/*
+ * Private data structure
+ */
+static struct {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+	void *cb;
+	void *app_data;
+} nss_gre_pvt;
+
+/*
+ * TODO: Register separate callbacks for inner and outer GRE nodes.
+ */
+static atomic64_t pkt_cb_addr = ATOMIC64_INIT(0);
+
+/*
+ * nss_gre_inner_rx_handler()
+ *	GRE inner rx handler.
+ */
+static void nss_gre_inner_rx_handler(struct net_device *dev, struct sk_buff *skb,
+		    __attribute__((unused)) struct napi_struct *napi)
+{
+	nss_gre_data_callback_t cb;
+
+	nss_gre_pkt_callback_t scb = (nss_gre_pkt_callback_t)(unsigned long)atomic64_read(&pkt_cb_addr);
+	if (unlikely(scb)) {
+		struct nss_gre_info *info = (struct nss_gre_info *)netdev_priv(dev);
+		if (likely(info->next_dev_inner)) {
+			scb(info->next_dev_inner, skb);
+		}
+	}
+
+	cb = nss_top_main.gre_inner_data_callback;
+	cb(dev, skb, 0);
+}
+
+/*
+ * nss_gre_outer_rx_handler()
+ *	GRE outer rx handler.
+ */
+static void nss_gre_outer_rx_handler(struct net_device *dev, struct sk_buff *skb,
+		    __attribute__((unused)) struct napi_struct *napi)
+{
+	nss_gre_data_callback_t cb;
+
+	nss_gre_pkt_callback_t scb = (nss_gre_pkt_callback_t)(unsigned long)atomic64_read(&pkt_cb_addr);
+	if (unlikely(scb)) {
+		struct nss_gre_info *info = (struct nss_gre_info *)netdev_priv(dev);
+		if (likely(info->next_dev_outer)) {
+			scb(info->next_dev_outer, skb);
+		}
+	}
+
+	cb = nss_top_main.gre_outer_data_callback;
+	cb(dev, skb, 0);
+}
+
+/*
+ * nss_gre_msg_handler()
+ *	Handle NSS -> HLOS messages for GRE
+ */
+static void nss_gre_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_gre_msg *ntm = (struct nss_gre_msg *)ncm;
+	void *ctx;
+
+	nss_gre_msg_callback_t cb;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	BUG_ON(!(nss_is_dynamic_interface(ncm->interface) || ncm->interface == NSS_GRE_INTERFACE));
+
+	/*
+	 * Trace Messages
+	 */
+	nss_gre_log_rx_msg(ntm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_GRE_MSG_MAX) {
+		nss_warning("%px: received invalid message %d for GRE STD interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_gre_msg)) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	switch (ntm->cm.type) {
+	case NSS_GRE_MSG_SESSION_STATS:
+		/*
+		 * debug stats embedded in stats msg
+		 */
+		nss_gre_stats_session_sync(nss_ctx, &ntm->msg.sstats, ncm->interface);
+		nss_gre_stats_session_notify(nss_ctx, ncm->interface);
+		break;
+
+	case NSS_GRE_MSG_BASE_STATS:
+		nss_gre_stats_base_sync(nss_ctx, &ntm->msg.bstats);
+		nss_gre_stats_base_notify(nss_ctx);
+		break;
+
+	default:
+		break;
+
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, gre sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->gre_msg_callback;
+		ncm->app_data = (nss_ptr_t)nss_ctx->subsys_dp_register[ncm->interface].app_data;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * callback
+	 */
+	cb = (nss_gre_msg_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	/*
+	 * call gre-std callback
+	 */
+	if (!cb) {
+		nss_warning("%px: No callback for gre-std interface %d",
+			    nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb(ctx, ntm);
+}
+
+/*
+ * nss_gre_callback()
+ *	Callback to handle the completion of HLOS-->NSS messages.
+ */
+static void nss_gre_callback(void *app_data, struct nss_gre_msg *nim)
+{
+	nss_gre_msg_callback_t callback = (nss_gre_msg_callback_t)nss_gre_pvt.cb;
+	void *data = nss_gre_pvt.app_data;
+
+	nss_gre_pvt.cb = NULL;
+	nss_gre_pvt.app_data = NULL;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("gre Error response %d\n", nim->cm.response);
+		nss_gre_pvt.response = NSS_TX_FAILURE;
+	} else {
+		nss_gre_pvt.response = NSS_TX_SUCCESS;
+	}
+
+	if (callback) {
+		callback(data, nim);
+	}
+
+	complete(&nss_gre_pvt.complete);
+}
+
+/*
+ * nss_gre_register_pkt_callback()
+ *	Register for data callback.
+ */
+void nss_gre_register_pkt_callback(nss_gre_pkt_callback_t cb)
+{
+	atomic64_set(&pkt_cb_addr, (unsigned long)cb);
+}
+EXPORT_SYMBOL(nss_gre_register_pkt_callback);
+
+/*
+ * nss_gre_unregister_pkt_callback()
+ *	Unregister for data callback.
+ */
+void nss_gre_unregister_pkt_callback()
+{
+	atomic64_set(&pkt_cb_addr, 0);
+}
+EXPORT_SYMBOL(nss_gre_unregister_pkt_callback);
+
+/*
+ * nss_gre_tx_msg()
+ *	Transmit a GRE message to NSS firmware
+ */
+nss_tx_status_t nss_gre_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_gre_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!nss_is_dynamic_interface(ncm->interface)) {
+		nss_warning("%px: tx request for non dynamic interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_GRE_MSG_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Trace Messages
+	 */
+	nss_gre_log_tx_msg(msg);
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_gre_tx_msg);
+
+/*
+ * nss_gre_tx_msg_sync()
+ *	Transmit a GRE message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_gre_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_msg *msg)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&nss_gre_pvt.sem);
+	nss_gre_pvt.cb = (void *)msg->cm.cb;
+	nss_gre_pvt.app_data = (void *)msg->cm.app_data;
+
+	msg->cm.cb = (nss_ptr_t)nss_gre_callback;
+	msg->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_gre_tx_msg(nss_ctx, msg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: gre_tx_msg failed\n", nss_ctx);
+		up(&nss_gre_pvt.sem);
+		return status;
+	}
+	ret = wait_for_completion_timeout(&nss_gre_pvt.complete, msecs_to_jiffies(NSS_GRE_TX_TIMEOUT));
+
+	if (!ret) {
+		nss_warning("%px: GRE STD tx sync failed due to timeout\n", nss_ctx);
+		nss_gre_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = nss_gre_pvt.response;
+	up(&nss_gre_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_gre_tx_msg_sync);
+
+/*
+ * nss_gre_tx_buf()
+ *	Send packet to GRE interface owned by NSS
+ */
+nss_tx_status_t nss_gre_tx_buf(struct nss_ctx_instance *nss_ctx, uint32_t if_num, struct sk_buff *skb)
+{
+	return nss_core_send_packet(nss_ctx, skb, if_num, H2N_BIT_FLAG_VIRTUAL_BUFFER | H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+EXPORT_SYMBOL(nss_gre_tx_buf);
+
+/*
+ ***********************************
+ * Register/Unregister/Miscellaneous APIs
+ ***********************************
+ */
+
+/*
+ * nss_gre_register_if()
+ *	Register data and message handlers for GRE.
+ */
+struct nss_ctx_instance *nss_gre_register_if(uint32_t if_num, uint32_t type, nss_gre_data_callback_t data_callback,
+			nss_gre_msg_callback_t event_callback, struct net_device *netdev, uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.gre_handler_id];
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_is_dynamic_interface(if_num));
+
+	switch (type) {
+	case NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER:
+		nss_core_register_subsys_dp(nss_ctx, if_num, nss_gre_inner_rx_handler, NULL, netdev, netdev, features);
+		nss_top_main.gre_inner_data_callback = data_callback;
+		break;
+
+	case NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER:
+		nss_core_register_subsys_dp(nss_ctx, if_num, nss_gre_outer_rx_handler, NULL, netdev, netdev, features);
+		nss_top_main.gre_outer_data_callback = data_callback;
+		break;
+
+	default:
+		nss_warning("%px: Unable to register. Wrong interface type %d\n", nss_ctx, type);
+		return NULL;
+	}
+
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num, type);
+
+	nss_top_main.gre_msg_callback = event_callback;
+
+	nss_core_register_handler(nss_ctx, if_num, nss_gre_msg_handler, NULL);
+
+	nss_gre_stats_session_register(if_num, netdev);
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_gre_register_if);
+
+/*
+ * nss_gre_unregister_if()
+ *	Unregister data and message handler.
+ */
+void nss_gre_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.gre_handler_id];
+	struct net_device *dev;
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_is_dynamic_interface(if_num));
+
+	dev = nss_cmn_get_interface_dev(nss_ctx, if_num);
+	if (!dev) {
+		nss_warning("%px: Unable to find net device for the interface %d\n", nss_ctx, if_num);
+		return;
+	}
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+	nss_core_set_subsys_dp_type(nss_ctx, dev, if_num, NSS_DYNAMIC_INTERFACE_TYPE_NONE);
+	nss_top_main.gre_msg_callback = NULL;
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+
+	nss_gre_stats_session_unregister(if_num);
+}
+EXPORT_SYMBOL(nss_gre_unregister_if);
+
+/*
+ * nss_get_gre_context()
+ */
+struct nss_ctx_instance *nss_gre_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.gre_handler_id];
+}
+EXPORT_SYMBOL(nss_gre_get_context);
+
+/*
+ * nss_gre_ifnum_with_core_id()
+ *	Append core id to GRE interface num.
+ */
+int nss_gre_ifnum_with_core_id(int if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_get_context();
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	if (!nss_is_dynamic_interface(if_num)) {
+		nss_warning("%px: Invalid if_num: %d, must be a dynamic interface\n", nss_ctx, if_num);
+		return 0;
+	}
+
+	return NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_gre_ifnum_with_core_id);
+
+/*
+ * nss_gre_msg_init()
+ *	Initialize nss_gre msg.
+ */
+void nss_gre_msg_init(struct nss_gre_msg *ncm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+EXPORT_SYMBOL(nss_gre_msg_init);
+
+/*
+ * nss_gre_register_handler()
+ *	debugfs stats msg handler received on static gre interface
+ */
+void nss_gre_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_get_context();
+
+	nss_info("nss_gre_register_handler");
+	sema_init(&nss_gre_pvt.sem, 1);
+	init_completion(&nss_gre_pvt.complete);
+	nss_core_register_handler(nss_ctx, NSS_GRE_INTERFACE, nss_gre_msg_handler, NULL);
+	nss_gre_stats_dentry_create();
+	nss_gre_strings_dentry_create();
+}
diff --git a/qca-nss-drv/nss_gre_log.c b/qca-nss-drv/nss_gre_log.c
new file mode 100644
index 0000000..c2f752b
--- /dev/null
+++ b/qca-nss-drv/nss_gre_log.c
@@ -0,0 +1,187 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_gre_log.c
+ *	NSS GRE logger file.
+ */
+
+#include "nss_core.h"
+
+#define NSS_GRE_LOG_MESSAGE_TYPE_INDEX(type) ((type) - NSS_IF_MAX_MSG_TYPES - 1)
+
+/*
+ * nss_gre_log_message_types_str
+ *	NSS GRE message strings
+ */
+static int8_t *nss_gre_log_message_types_str[NSS_GRE_MSG_MAX] __maybe_unused = {
+	"GRE Message Configure",
+	"GRE Message Deconfigure",
+	"GRE Session Stats",
+	"GRE Base Stats"
+};
+
+/*
+ * nss_gre_log_config_msg()
+ *	Log NSS GRE Config message.
+ */
+static void nss_gre_log_config_msg(struct nss_gre_msg *ngm)
+{
+	struct nss_gre_config_msg *ngcm __maybe_unused = &ngm->msg.cmsg;
+	nss_trace("%px: NSS GRE Config message\n"
+		"GRE flags: %d\n"
+		"GRE ikey: %d\n"
+		"GRE okey: %d\n"
+		"GRE mode: %d\n"
+		"GRE ip type: %d\n"
+		"GRE interface number: %d\n"
+		"GRE Src MAC: %pM\n"
+		"GRE Dst MAC: %pM\n"
+		"GRE ttl: %d\n"
+		"GRE tos: %d\n"
+		"GRE metadata size: %d\n",
+		ngcm, ngcm->flags, ngcm->ikey, ngcm->okey,
+		ngcm->mode, ngcm->ip_type, ngcm->next_node_if_num,
+		ngcm->src_mac, ngcm->dest_mac, ngcm->ttl, ngcm->tos,
+		ngcm->metadata_size);
+	/*
+	 * Continuation of the log message. Different identifiers based on IP type.
+	 */
+	if (ngcm->ip_type == NSS_GRE_IP_IPV6) {
+		nss_trace("GRE Source IP: %pI6\n"
+			"GRE Dest IP: %pI6\n",
+			ngcm->src_ip, ngcm->dest_ip);
+	} else {
+		nss_trace("GRE Source IP: %pI4\n"
+			"GRE Dest IP: %pI4\n",
+			ngcm->src_ip, ngcm->dest_ip);
+	}
+}
+
+/*
+ * nss_gre_log_deconfig_msg()
+ *	Log NSS GRE deconfig message.
+ */
+static void nss_gre_log_deconfig_msg(struct nss_gre_msg *ngm)
+{
+	struct nss_gre_deconfig_msg *ngdm __maybe_unused = &ngm->msg.dmsg;
+	nss_trace("%px: NSS GRE deconfig message\n"
+		"GRE interface number: %d\n",
+		ngdm, ngdm->if_number);
+}
+
+/*
+ * nss_gre_log_linkup_msg()
+ *	Log NSS GRE linkup message.
+ */
+static void nss_gre_log_linkup_msg(struct nss_gre_msg *ngm)
+{
+	struct nss_gre_linkup_msg *nglm __maybe_unused = &ngm->msg.linkup;
+	nss_trace("%px: NSS GRE linkup message\n"
+		"GRE interface number: %d\n",
+		nglm, nglm->if_number);
+}
+
+/*
+ * nss_gre_log_linkdown_msg()
+ *	Log NSS GRE linkdown message.
+ */
+static void nss_gre_log_linkdown_msg(struct nss_gre_msg *ngm)
+{
+	struct nss_gre_linkdown_msg *ngdm __maybe_unused = &ngm->msg.linkdown;
+	nss_trace("%px: NSS GRE linkdown message\n"
+		"GRE interface number: %d\n",
+		ngdm, ngdm->if_number);
+}
+
+/*
+ * nss_gre_log_verbose()
+ *	Log message contents.
+ */
+static void nss_gre_log_verbose(struct nss_gre_msg *ngm)
+{
+	switch (ngm->cm.type) {
+	case NSS_GRE_MSG_ENCAP_CONFIGURE:
+	case NSS_GRE_MSG_DECAP_CONFIGURE:
+		nss_gre_log_config_msg(ngm);
+		break;
+
+	case NSS_GRE_MSG_ENCAP_DECONFIGURE:
+	case NSS_GRE_MSG_DECAP_DECONFIGURE:
+		nss_gre_log_deconfig_msg(ngm);
+		break;
+
+	case NSS_IF_OPEN:
+		nss_gre_log_linkup_msg(ngm);
+		break;
+
+	case NSS_IF_CLOSE:
+		nss_gre_log_linkdown_msg(ngm);
+		break;
+
+	case NSS_GRE_MSG_SESSION_STATS:
+	case NSS_GRE_MSG_BASE_STATS:
+		/*
+		 * No log for valid stats messages.
+		 */
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", ngm);
+		break;
+	}
+}
+
+/*
+ * nss_gre_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_gre_log_tx_msg(struct nss_gre_msg *ngm)
+{
+	if (ngm->cm.type >= NSS_GRE_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", ngm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ngm, ngm->cm.type, nss_gre_log_message_types_str[NSS_GRE_LOG_MESSAGE_TYPE_INDEX(ngm->cm.type)]);
+	nss_gre_log_verbose(ngm);
+}
+
+/*
+ * nss_gre_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_gre_log_rx_msg(struct nss_gre_msg *ngm)
+{
+	if (ngm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ngm);
+		return;
+	}
+
+	if (ngm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ngm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ngm, ngm->cm.type,
+			nss_gre_log_message_types_str[NSS_GRE_LOG_MESSAGE_TYPE_INDEX(ngm->cm.type)],
+			ngm->cm.response, nss_cmn_response_str[ngm->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		ngm, ngm->cm.type, nss_gre_log_message_types_str[NSS_GRE_LOG_MESSAGE_TYPE_INDEX(ngm->cm.type)],
+		ngm->cm.response, nss_cmn_response_str[ngm->cm.response]);
+
+verbose:
+	nss_gre_log_verbose(ngm);
+}
diff --git a/qca-nss-drv/nss_gre_log.h b/qca-nss-drv/nss_gre_log.h
new file mode 100644
index 0000000..2a21117
--- /dev/null
+++ b/qca-nss-drv/nss_gre_log.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_GRE_LOG_H
+#define __NSS_GRE_LOG_H
+
+/*
+ * nss_gre_log.h
+ *	NSS GRE header file.
+ */
+
+/*
+ * Logger APIs
+ */
+
+/*
+ * nss_gre_log_tx_msg
+ *	Logs a gre message that is sent to the NSS firmware.
+ */
+void nss_gre_log_tx_msg(struct nss_gre_msg *ngm);
+
+/*
+ * nss_gre_log_rx_msg
+ *	Logs a gre message that is received from the NSS firmware.
+ */
+void nss_gre_log_rx_msg(struct nss_gre_msg *ngm);
+
+#endif /* __NSS_GRE_LOG_H */
diff --git a/qca-nss-drv/nss_gre_redir.c b/qca-nss-drv/nss_gre_redir.c
new file mode 100644
index 0000000..73e7c9f
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir.c
@@ -0,0 +1,673 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_gre_redir_stats.h"
+#include "nss_gre_redir_strings.h"
+#include "nss_gre_redir_log.h"
+#define NSS_GRE_REDIR_TX_TIMEOUT 3000 /* 3 Seconds */
+
+static struct dentry *gre_redir_dentry;
+
+/*
+ * Private data structure for handling synchronous messaging.
+ */
+static struct {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+} nss_gre_redir_pvt;
+
+/*
+ * Array to hold tunnel stats along with if_num
+ */
+struct nss_gre_redir_tunnel_stats tun_stats[NSS_GRE_REDIR_MAX_INTERFACES];
+
+/*
+ * nss_gre_callback()
+ *	Callback to handle the completion of HLOS-->NSS messages.
+ */
+static void nss_gre_redir_msg_sync_callback(void *app_data, struct nss_gre_redir_msg *nim)
+{
+	nss_gre_redir_pvt.response = NSS_TX_SUCCESS;
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("gre Error response %d\n", nim->cm.response);
+		nss_gre_redir_pvt.response = NSS_TX_FAILURE;
+	}
+
+	complete(&nss_gre_redir_pvt.complete);
+}
+
+/*
+ * nss_gre_redir_verify_ifnum()
+ *	Verify interface type.
+ */
+bool nss_gre_redir_verify_ifnum(uint32_t if_num)
+{
+	uint32_t type;
+
+	type = nss_dynamic_interface_get_type(nss_gre_redir_get_context(), if_num);
+	return type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_HOST_INNER ||
+			type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_OFFL_INNER ||
+			type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_SJACK_INNER ||
+			type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_OUTER ||
+			type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_EXCEPTION_US ||
+			type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_EXCEPTION_DS;
+}
+
+/*
+ * nss_gre_redir_handler()
+ *	Handle NSS -> HLOS messages for GRE tunnel.
+ */
+static void nss_gre_redir_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_gre_redir_msg *ngrm = (struct nss_gre_redir_msg *)ncm;
+	void *ctx;
+	nss_gre_redir_msg_callback_t cb;
+
+	/*
+	 * interface should either be dynamic interface for receiving tunnel msg or GRE_REDIR interface for
+	 * receiving base node messages.
+	 */
+	BUG_ON(((ncm->interface < NSS_DYNAMIC_IF_START) || (ncm->interface >= (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES))) &&
+		ncm->interface != NSS_GRE_REDIR_INTERFACE);
+
+	/*
+	 * Trace Messages
+	 */
+	nss_gre_redir_log_rx_msg(ngrm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >=  NSS_GRE_REDIR_MAX_MSG_TYPES) {
+		nss_warning("%px: Received invalid message %d for gre interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_gre_redir_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, gre sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->nss_rx_interface_handlers[ncm->interface].app_data;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	switch (ncm->type) {
+	case NSS_GRE_REDIR_RX_STATS_SYNC_MSG:
+		nss_gre_redir_stats_sync(nss_ctx, ncm->interface, &ngrm->msg.stats_sync);
+		nss_gre_redir_stats_notify(nss_ctx, ncm->interface);
+		break;
+	}
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_gre_redir_msg_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	/*
+	 * call gre tunnel callback
+	 */
+	cb(ctx, ncm);
+}
+
+/*
+ * nss_gre_redir_register_if()
+ *	Register dynamic node for GRE redir.
+ */
+static struct nss_ctx_instance *nss_gre_redir_register_if(uint32_t if_num, struct net_device *netdev,
+		nss_gre_redir_data_callback_t cb_func_data, nss_gre_redir_msg_callback_t cb_func_msg, uint32_t features,
+		uint32_t type, void *app_ctx)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.gre_redir_handler_id];
+	uint32_t status;
+	int i, idx = -1;
+
+	nss_assert(nss_ctx);
+	nss_assert((if_num >= NSS_DYNAMIC_IF_START) && (if_num < (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES)));
+
+	spin_lock_bh(&nss_gre_redir_stats_lock);
+	for (i = 0; i < NSS_GRE_REDIR_MAX_INTERFACES; i++) {
+		if (tun_stats[i].dev == netdev) {
+			idx = i;
+			break;
+		}
+
+		if ((idx == -1) && (tun_stats[i].ref_count == 0)) {
+			idx = i;
+		}
+	}
+
+	if (idx == -1) {
+		spin_unlock_bh(&nss_gre_redir_stats_lock);
+		nss_warning("%px: Maximum number of gre_redir tunnel_stats instances are already allocated\n", nss_ctx);
+		return NULL;
+	}
+
+	if (!tun_stats[idx].ref_count) {
+		tun_stats[idx].dev = netdev;
+	}
+	tun_stats[idx].ref_count++;
+
+	spin_unlock_bh(&nss_gre_redir_stats_lock);
+
+	/*
+	 * Registering handler for sending tunnel interface msgs to NSS.
+	 */
+	status = nss_core_register_handler(nss_ctx, if_num, nss_gre_redir_msg_handler, app_ctx);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		spin_lock_bh(&nss_gre_redir_stats_lock);
+		tun_stats[idx].ref_count--;
+		if (!tun_stats[idx].ref_count) {
+			tun_stats[idx].dev = NULL;
+		}
+		spin_unlock_bh(&nss_gre_redir_stats_lock);
+
+		nss_warning("%px: Not able to register handler for gre_redir interface %d with NSS core\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	/*
+	 * Registering handler for sending tunnel interface msgs to NSS.
+	 */
+	status = nss_core_register_msg_handler(nss_ctx, if_num, cb_func_msg);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_core_unregister_handler(nss_ctx, if_num);
+		spin_lock_bh(&nss_gre_redir_stats_lock);
+		tun_stats[idx].ref_count--;
+		if (!tun_stats[idx].ref_count) {
+			tun_stats[idx].dev = NULL;
+		}
+		spin_unlock_bh(&nss_gre_redir_stats_lock);
+
+		nss_warning("%px: Not able to register handler for gre_redir interface %d with NSS core\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, cb_func_data, NULL, NULL, netdev, features);
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num, type);
+	return nss_ctx;
+}
+
+/*
+ * nss_gre_redir_get_context()
+ *	Retrieve context for GRE redir.
+ */
+struct nss_ctx_instance *nss_gre_redir_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.gre_redir_handler_id];
+}
+EXPORT_SYMBOL(nss_gre_redir_get_context);
+
+/*
+ * nss_gre_redir_alloc_and_register_node()
+ *	Allocates and registers GRE Inner/Outer type dynamic nodes with NSS.
+ */
+int nss_gre_redir_alloc_and_register_node(struct net_device *dev,
+		nss_gre_redir_data_callback_t data_cb,
+		nss_gre_redir_msg_callback_t msg_cb,
+		uint32_t type, void *app_ctx)
+{
+	int ifnum;
+	nss_tx_status_t status;
+	struct nss_ctx_instance *nss_ctx;
+
+	if ((type != NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_HOST_INNER) &&
+			(type != NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_OFFL_INNER) &&
+			(type != NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_SJACK_INNER) &&
+			(type != NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_OUTER) &&
+			(type != NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_EXCEPTION_US) &&
+			(type != NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_EXCEPTION_DS)) {
+
+		nss_warning("%px: Unknown type %u\n", dev, type);
+		return -1;
+	}
+
+	ifnum = nss_dynamic_interface_alloc_node(type);
+	if (ifnum == -1) {
+		nss_warning("%px: Unable to allocate GRE_REDIR node of type = %u\n", dev, type);
+		return -1;
+	}
+
+	nss_ctx = nss_gre_redir_register_if(ifnum, dev, data_cb,
+			msg_cb, 0, type, app_ctx);
+	if (!nss_ctx) {
+		nss_warning("Unable to register GRE_REDIR node of type = %u\n", type);
+		status = nss_dynamic_interface_dealloc_node(ifnum, type);
+		if (status != NSS_TX_SUCCESS) {
+			nss_warning("Unable to deallocate node.\n");
+		}
+
+		return -1;
+	}
+
+	return ifnum;
+}
+EXPORT_SYMBOL(nss_gre_redir_alloc_and_register_node);
+
+/*
+ * nss_gre_redir_configure_inner_node()
+ *	Configure an inner type gre_redir dynamic node.
+ */
+nss_tx_status_t nss_gre_redir_configure_inner_node(int ifnum,
+		struct nss_gre_redir_inner_configure_msg *ngrcm)
+{
+	struct nss_gre_redir_msg config;
+	uint32_t len, iftype, outerif_type;
+	nss_tx_status_t status;
+
+	struct nss_ctx_instance *nss_ctx __maybe_unused = nss_gre_redir_get_context();
+	if (!nss_ctx) {
+		nss_warning("Unable to retrieve NSS context.\n");
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	if (ngrcm->ip_hdr_type != NSS_GRE_REDIR_IP_HDR_TYPE_IPV4 &&
+			ngrcm->ip_hdr_type != NSS_GRE_REDIR_IP_HDR_TYPE_IPV6) {
+		nss_warning("%px: Unknown IP header type %u\n", nss_ctx, ngrcm->ip_hdr_type);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	if (ngrcm->gre_version != NSS_GRE_REDIR_HEADER_VERSION) {
+		nss_warning("%px: Incorrect header version %u\n", nss_ctx, ngrcm->gre_version);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	iftype = nss_dynamic_interface_get_type(nss_ctx, ifnum);
+	if (!((iftype == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_HOST_INNER) ||
+			(iftype == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_OFFL_INNER) ||
+			(iftype == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_SJACK_INNER))) {
+
+		nss_warning("%px: Incorrect interface type %u\n", nss_ctx, iftype);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	outerif_type = nss_dynamic_interface_get_type(nss_ctx, ngrcm->except_outerif);
+	if (outerif_type != NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_OUTER) {
+		nss_warning("%px: Incorrect type for exception interface %u\n", nss_ctx, outerif_type);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	len = sizeof(struct nss_gre_redir_inner_configure_msg);
+
+	/*
+	 * Configure the node
+	 */
+	nss_cmn_msg_init(&config.cm, ifnum, NSS_GRE_REDIR_TX_TUNNEL_INNER_CONFIGURE_MSG, len, NULL, NULL);
+	config.msg.inner_configure.ip_hdr_type = ngrcm->ip_hdr_type;
+	config.msg.inner_configure.ip_df_policy = ngrcm->ip_df_policy;
+	config.msg.inner_configure.gre_version = ngrcm->gre_version;
+	config.msg.inner_configure.ip_ttl = ngrcm->ip_ttl;
+	config.msg.inner_configure.except_outerif = ngrcm->except_outerif;
+	memcpy((void *)config.msg.inner_configure.ip_src_addr, (void *)(ngrcm->ip_src_addr), sizeof(ngrcm->ip_src_addr));
+	memcpy((void *)config.msg.inner_configure.ip_dest_addr, (void *)(ngrcm->ip_dest_addr), sizeof(ngrcm->ip_dest_addr));
+
+	status = nss_gre_redir_tx_msg_sync(nss_ctx, &config);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Unable to configure inner node %d.\n", nss_ctx, ifnum);
+	}
+
+	return status;
+}
+EXPORT_SYMBOL(nss_gre_redir_configure_inner_node);
+
+/*
+ * nss_gre_redir_exception_ds_reg_cb()
+ *	Configure a callback on VAP for downstream exception tunnel flows.
+ */
+nss_tx_status_t nss_gre_redir_exception_ds_reg_cb(int ifnum,
+		struct nss_gre_redir_exception_ds_reg_cb_msg *ngrcm)
+{
+	struct nss_gre_redir_msg config;
+	struct nss_ctx_instance *nss_ctx __maybe_unused = nss_gre_redir_get_context();
+	nss_tx_status_t status;
+	uint32_t vap_type, iftype;
+	uint32_t len = sizeof(struct nss_gre_redir_exception_ds_reg_cb_msg);
+
+	if (!nss_ctx) {
+		nss_warning("Unable to retrieve NSS context.\n");
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	iftype = nss_dynamic_interface_get_type(nss_ctx, ifnum);
+	if (iftype != NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_EXCEPTION_DS) {
+		nss_warning("%px: Incorrect interface type %u\n", nss_ctx, iftype);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	vap_type = nss_dynamic_interface_get_type(nss_ctx, ngrcm->dst_vap_nssif);
+	if ((vap_type != NSS_DYNAMIC_INTERFACE_TYPE_VAP)) {
+		nss_warning("%px: Incorrect type for vap interface type = %u", nss_ctx, vap_type);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	/*
+	 * Configure the node
+	 */
+	nss_cmn_msg_init(&config.cm, ifnum, NSS_GRE_REDIR_EXCEPTION_DS_REG_CB_MSG, len, NULL, NULL);
+	config.msg.exception_ds_configure.dst_vap_nssif = ngrcm->dst_vap_nssif;
+
+	status = nss_gre_redir_tx_msg_sync(nss_ctx, &config);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Unable to register callback from gre redir exception ds %d\n", nss_ctx, ifnum);
+	}
+
+	return status;
+}
+EXPORT_SYMBOL(nss_gre_redir_exception_ds_reg_cb);
+
+/*
+ * nss_gre_redir_configure_outer_node()
+ *	Configure an outer type gre_redir dynamic node.
+ */
+nss_tx_status_t nss_gre_redir_configure_outer_node(int ifnum,
+		struct nss_gre_redir_outer_configure_msg *ngrcm)
+{
+	struct nss_gre_redir_msg config;
+	struct nss_ctx_instance *nss_ctx __maybe_unused = nss_gre_redir_get_context();
+	nss_tx_status_t status;
+	uint32_t hostif_type, offlif_type, sjackif_type, iftype;
+	uint32_t len = sizeof(struct nss_gre_redir_outer_configure_msg);
+
+	if (!nss_ctx) {
+		nss_warning("Unable to retrieve NSS context.\n");
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	if (ngrcm->ip_hdr_type != NSS_GRE_REDIR_IP_HDR_TYPE_IPV4 &&
+			ngrcm->ip_hdr_type != NSS_GRE_REDIR_IP_HDR_TYPE_IPV6) {
+		nss_warning("%px: Unknown IP header type %u\n", nss_ctx, ngrcm->ip_hdr_type);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	iftype = nss_dynamic_interface_get_type(nss_ctx, ifnum);
+	if (iftype != NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_OUTER) {
+		nss_warning("%px: Incorrect interface type %u\n", nss_ctx, iftype);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	hostif_type = nss_dynamic_interface_get_type(nss_ctx, ngrcm->except_hostif);
+	offlif_type = nss_dynamic_interface_get_type(nss_ctx, ngrcm->except_offlif);
+	sjackif_type = nss_dynamic_interface_get_type(nss_ctx, ngrcm->except_sjackif);
+	if ((hostif_type != NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_HOST_INNER) ||
+			(offlif_type != NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_OFFL_INNER) ||
+			(ngrcm->except_sjackif
+			 && sjackif_type != NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_SJACK_INNER)) {
+
+		nss_warning("%px: Incorrect type for exception interface hostif_type = %u"
+				"offlif_type = %u sjackif_type = %u\n", nss_ctx, hostif_type,
+				offlif_type, sjackif_type);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	/*
+	 * Configure the node
+	 */
+	nss_cmn_msg_init(&config.cm, ifnum, NSS_GRE_REDIR_TX_TUNNEL_OUTER_CONFIGURE_MSG, len, NULL, NULL);
+	config.msg.outer_configure.ip_hdr_type = ngrcm->ip_hdr_type;
+	config.msg.outer_configure.rps_hint = ngrcm->rps_hint;
+	config.msg.outer_configure.except_hostif = ngrcm->except_hostif;
+	config.msg.outer_configure.except_offlif = ngrcm->except_offlif;
+	config.msg.outer_configure.except_sjackif = ngrcm->except_sjackif;
+
+	status = nss_gre_redir_tx_msg_sync(nss_ctx, &config);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Unable to configure outer node %d\n", nss_ctx, ifnum);
+	}
+
+	return status;
+}
+EXPORT_SYMBOL(nss_gre_redir_configure_outer_node);
+
+/*
+ * nss_gre_redir_tx_msg()
+ *	Transmit a GRE message to NSS FW.
+ */
+nss_tx_status_t nss_gre_redir_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_gre_redir_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+
+	/*
+	 * interface should either be dynamic interface to transmit tunnel msg or GRE_REDIR interface to transmit
+	 * base node messages.
+	 */
+	if (((ncm->interface < NSS_DYNAMIC_IF_START) || (ncm->interface >= (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES))) &&
+		ncm->interface != NSS_GRE_REDIR_INTERFACE) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_GRE_REDIR_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_gre_redir_tx_msg);
+
+/*
+ * nss_gre_redir_tx_msg_sync()
+ *	Transmit a GRE redir message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_gre_redir_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_msg *ngrm)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&nss_gre_redir_pvt.sem);
+	ngrm->cm.cb = (nss_ptr_t)nss_gre_redir_msg_sync_callback;
+	ngrm->cm.app_data = (nss_ptr_t)NULL;
+	status = nss_gre_redir_tx_msg(nss_ctx, ngrm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: gre_tx_msg failed\n", nss_ctx);
+		up(&nss_gre_redir_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&nss_gre_redir_pvt.complete, msecs_to_jiffies(NSS_GRE_REDIR_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: GRE tx sync failed due to timeout\n", nss_ctx);
+		nss_gre_redir_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = nss_gre_redir_pvt.response;
+	up(&nss_gre_redir_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_gre_redir_tx_msg_sync);
+
+/*
+ * nss_gre_redir_tx_buf()
+ *	Send packet to gre_redir interface owned by NSS.
+ */
+nss_tx_status_t nss_gre_redir_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, uint32_t if_num)
+{
+	uint32_t type;
+
+	nss_trace("%px: gre_redir If Tx packet, id:%d, data=%px", nss_ctx, if_num, os_buf->data);
+
+	/*
+	 * We expect Tx packets to the tunnel only from an interface of
+	 * type GRE_REDIR_WIFI_HOST_INNER.
+	 */
+	type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+	if (!((type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_HOST_INNER)
+		|| (type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_EXCEPTION_DS))) {
+		nss_warning("%px: Unknown type for interface %u\n", nss_ctx, type);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	return nss_core_send_packet(nss_ctx, os_buf, if_num, H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+EXPORT_SYMBOL(nss_gre_redir_tx_buf);
+
+/*
+ * nss_gre_redir_tx_buf_noreuse()
+ *	Send packet to gre_redir interface owned by NSS.
+ */
+nss_tx_status_t nss_gre_redir_tx_buf_noreuse(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, uint32_t if_num)
+{
+	uint32_t type;
+
+	nss_trace("%px: gre_redir If Tx packet, id:%d, data=%px", nss_ctx, if_num, os_buf->data);
+
+	/*
+	 * We expect Tx packets to the tunnel only from an interface of
+	 * type GRE_REDIR_WIFI_HOST_INNER.
+	 */
+	type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+	if (!((type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_HOST_INNER)
+		|| (type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_EXCEPTION_DS))) {
+		nss_warning("%px: Unknown type for interface %u\n", nss_ctx, type);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	return nss_core_send_packet(nss_ctx, os_buf, if_num, 0);
+}
+EXPORT_SYMBOL(nss_gre_redir_tx_buf_noreuse);
+
+/*
+ * nss_gre_redir_unregister_if()
+ *	Unregister dynamic node for GRE redir.
+ */
+bool nss_gre_redir_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx __maybe_unused = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.gre_redir_handler_id];
+	uint32_t status;
+	struct net_device *dev;
+	int i;
+
+	nss_assert(nss_ctx);
+	nss_assert((if_num >= NSS_DYNAMIC_IF_START) && (if_num < (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES)));
+
+	dev = nss_cmn_get_interface_dev(nss_ctx, if_num);
+	if (!dev) {
+		nss_warning("%px: Unable to find net device for the interface %d\n", nss_ctx, if_num);
+		return false;
+	}
+
+	status = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to unregister handler for gre_redir interface %d with NSS core\n", nss_ctx, if_num);
+		return false;
+	}
+
+	status = nss_core_unregister_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to unregister handler for gre_redir interface %d with NSS core\n", nss_ctx, if_num);
+		return false;
+	}
+
+	nss_core_set_subsys_dp_type(nss_ctx, dev, if_num, NSS_DYNAMIC_INTERFACE_TYPE_NONE);
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+	spin_lock_bh(&nss_gre_redir_stats_lock);
+
+	/*
+	 * Update/Clear the tunnel stats entry for this tunnel.
+	 */
+	for (i = 0; i < NSS_GRE_REDIR_MAX_INTERFACES; i++) {
+		if (tun_stats[i].dev == dev) {
+			tun_stats[i].ref_count--;
+			if (!tun_stats[i].ref_count) {
+				tun_stats[i].dev = NULL;
+			}
+
+			break;
+		}
+	}
+
+	spin_unlock_bh(&nss_gre_redir_stats_lock);
+	return true;
+}
+EXPORT_SYMBOL(nss_gre_redir_unregister_if);
+
+/*
+ * nss_gre_redir_get_device()
+ *	Gets the original device from probe.
+ */
+struct device *nss_gre_redir_get_device(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_redir_get_context();
+	return nss_ctx->dev;
+}
+EXPORT_SYMBOL(nss_gre_redir_get_device);
+
+/*
+ * nss_gre_redir_get_dentry()
+ *	Returns directory entry created in debugfs for statistics.
+ */
+struct dentry *nss_gre_redir_get_dentry(void)
+{
+	return gre_redir_dentry;
+}
+
+/*
+ * nss_gre_redir_register_handler()
+ *	Registering handler for sending msg to base gre_redir node on NSS.
+ */
+void nss_gre_redir_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx __maybe_unused = nss_gre_redir_get_context();
+	uint32_t status;
+
+	gre_redir_dentry = nss_gre_redir_stats_dentry_create();
+	if (!gre_redir_dentry) {
+		nss_warning("%px: Not able to create debugfs entry\n", nss_ctx);
+		return;
+	}
+
+	sema_init(&nss_gre_redir_pvt.sem, 1);
+	init_completion(&nss_gre_redir_pvt.complete);
+	memset(tun_stats, 0, sizeof(struct nss_gre_redir_tunnel_stats) * NSS_GRE_REDIR_MAX_INTERFACES);
+	status = nss_core_register_handler(nss_ctx, NSS_GRE_REDIR_INTERFACE, nss_gre_redir_msg_handler, NULL);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		debugfs_remove_recursive(gre_redir_dentry);
+		gre_redir_dentry = NULL;
+		nss_warning("%px: Not able to register handler for gre_redir base interface with NSS core\n", nss_ctx);
+		return;
+	}
+
+	nss_gre_redir_strings_dentry_create();
+}
diff --git a/qca-nss-drv/nss_gre_redir_lag_ds.c b/qca-nss-drv/nss_gre_redir_lag_ds.c
new file mode 100644
index 0000000..ea41320
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_lag_ds.c
@@ -0,0 +1,404 @@
+/*
+ ****************************************************************************
+ * Copyright (c) 2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ****************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_gre_redir_lag.h"
+#include "nss_gre_redir_lag_ds_stats.h"
+#include "nss_gre_redir_lag_ds_log.h"
+#include "nss_gre_redir_lag_ds_strings.h"
+
+#define NSS_GRE_REDIR_LAG_DS_TX_TIMEOUT 3000 /* 3 Seconds */
+
+struct nss_gre_redir_lag_ds_tun_stats tun_ds_stats[NSS_GRE_REDIR_LAG_MAX_NODE];
+
+/*
+ * Private data structure
+ */
+static struct {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+	nss_gre_redir_lag_ds_msg_callback_t *cb;
+	void *app_data;
+} nss_gre_redir_lag_ds_pvt;
+
+/*
+ * nss_gre_redir_lag_ds_callback()
+ *	Callback to handle the completion of HLOS-->NSS messages.
+ */
+static void nss_gre_redir_lag_ds_callback(void *app_data, struct nss_gre_redir_lag_ds_msg *nim)
+{
+	nss_gre_redir_lag_ds_msg_callback_t callback = (nss_gre_redir_lag_ds_msg_callback_t)nss_gre_redir_lag_ds_pvt.cb;
+	void *data = nss_gre_redir_lag_ds_pvt.app_data;
+
+	nss_gre_redir_lag_ds_pvt.cb = NULL;
+	nss_gre_redir_lag_ds_pvt.app_data = NULL;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("GRE LAG DS: error response %d\n", nim->cm.response);
+		nss_gre_redir_lag_ds_pvt.response = NSS_TX_FAILURE;
+	} else {
+		nss_gre_redir_lag_ds_pvt.response = NSS_TX_SUCCESS;
+	}
+
+	if (callback) {
+		callback(data, &nim->cm);
+	}
+
+	complete(&nss_gre_redir_lag_ds_pvt.complete);
+}
+
+/*
+ * nss_gre_redir_lag_ds_get_node_idx()
+ *	Returns index of statistics context.
+ */
+bool nss_gre_redir_lag_ds_get_node_idx(uint32_t ifnum, uint32_t *idx)
+{
+	uint32_t node_idx;
+	for (node_idx = 0; node_idx < NSS_GRE_REDIR_LAG_MAX_NODE; node_idx++) {
+		if ((tun_ds_stats[node_idx].valid) && (tun_ds_stats[node_idx].ifnum == ifnum)) {
+			*idx = node_idx;
+			return true;
+		}
+	}
+
+	return false;
+}
+
+/*
+ * nss_gre_redir_lag_ds_verify_ifnum()
+ *	Verify interface type.
+ */
+bool nss_gre_redir_lag_ds_verify_ifnum(uint32_t if_num)
+{
+	return nss_dynamic_interface_get_type(nss_gre_redir_lag_ds_get_context(), if_num) == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_DS;
+}
+
+/*
+ * nss_gre_redir_lag_ds_handler()
+ *	Handle NSS -> HLOS messages for gre tunnel
+ */
+static void nss_gre_redir_lag_ds_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	void *ctx;
+	struct nss_gre_redir_lag_ds_msg *ngrm = (struct nss_gre_redir_lag_ds_msg *)ncm;
+	nss_gre_redir_lag_ds_msg_callback_t cb;
+
+	/*
+	 * Interface should be a dynamic interface of type NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_DS.
+	 */
+	BUG_ON(!nss_gre_redir_lag_ds_verify_ifnum(ncm->interface));
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >=  NSS_GRE_REDIR_LAG_DS_MAX_MSG_TYPES) {
+		nss_warning("%px: received invalid message %d for gre interface\n", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_gre_redir_lag_ds_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d\n", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, gre sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->nss_rx_interface_handlers[ncm->interface].app_data;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_gre_redir_lag_ds_log_rx_msg(ngrm);
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	switch (ncm->type) {
+	case NSS_GRE_REDIR_LAG_DS_STATS_SYNC_MSG:
+		nss_gre_redir_lag_ds_stats_sync(nss_ctx, &ngrm->msg.ds_sync_stats, ncm->interface);
+		nss_gre_redir_lag_ds_stats_notify(nss_ctx, ncm->interface);
+		break;
+	}
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_gre_redir_lag_ds_msg_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	/*
+	 * call gre tunnel callback
+	 */
+	cb(ctx, ncm);
+}
+
+/*
+ * nss_gre_redir_lag_ds_unregister_if()
+ *	Unregister GRE redirect LAG downstream node.
+ */
+static enum nss_gre_redir_lag_err_types nss_gre_redir_lag_ds_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx __maybe_unused = nss_gre_redir_lag_ds_get_context();
+	uint32_t idx, status;
+
+	nss_assert(nss_ctx);
+	nss_assert(!nss_gre_redir_lag_ds_verify_ifnum(if_num));
+
+	status = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to unregister handler for gre_lag interface %d with NSS core\n", nss_ctx, if_num);
+		return NSS_GRE_REDIR_LAG_ERR_CORE_UNREGISTER_FAILED;
+	}
+
+	status = nss_core_unregister_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to unregister handler for gre_lag interface %d with NSS core\n", nss_ctx, if_num);
+		return NSS_GRE_REDIR_LAG_ERR_CORE_UNREGISTER_FAILED;
+	}
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+	spin_lock_bh(&nss_gre_redir_lag_ds_stats_lock);
+	if (!nss_gre_redir_lag_ds_get_node_idx(if_num, &idx)) {
+		spin_unlock_bh(&nss_gre_redir_lag_ds_stats_lock);
+		nss_warning("%px: Stats context not found.\n", nss_ctx);
+		return NSS_GRE_REDIR_LAG_ERR_STATS_INDEX_NOT_FOUND;
+	}
+
+	tun_ds_stats[idx].valid = false;
+	spin_unlock_bh(&nss_gre_redir_lag_ds_stats_lock);
+	return NSS_GRE_REDIR_LAG_SUCCESS;
+}
+
+/*
+ * nss_gre_redir_lag_ds_register_if()
+ *	Register GRE redirect LAG downstream node.
+ */
+static struct nss_ctx_instance *nss_gre_redir_lag_ds_register_if(uint32_t if_num, struct net_device *netdev,
+		nss_gre_redir_lag_ds_data_callback_t cb_func_data,
+		nss_gre_redir_lag_ds_msg_callback_t cb_func_msg, uint32_t features, uint32_t type, void *app_ctx)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_redir_lag_ds_get_context();
+	uint32_t status, i;
+	nss_assert(nss_ctx);
+	nss_assert(!nss_gre_redir_lag_ds_verify_ifnum(if_num));
+
+	/*
+	 * Registering handler for sending tunnel interface msgs to NSS.
+	 */
+	status = nss_core_register_handler(nss_ctx, if_num, nss_gre_redir_lag_ds_msg_handler, app_ctx);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to register handler for gre_lag interface %d with NSS core\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	/*
+	 * Registering handler for sending tunnel interface msgs to NSS.
+	 */
+	status = nss_core_register_msg_handler(nss_ctx, if_num, cb_func_msg);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_core_unregister_handler(nss_ctx, if_num);
+		nss_warning("%px: Not able to register handler for gre_lag interface %d with NSS core\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, cb_func_data, NULL, NULL, netdev, features);
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num, type);
+	spin_lock_bh(&nss_gre_redir_lag_ds_stats_lock);
+	for (i = 0; i < NSS_GRE_REDIR_LAG_MAX_NODE; i++) {
+		if (!tun_ds_stats[i].valid) {
+			tun_ds_stats[i].ifnum = if_num;
+			tun_ds_stats[i].valid = true;
+			break;
+		}
+	}
+
+	spin_unlock_bh(&nss_gre_redir_lag_ds_stats_lock);
+
+	return nss_ctx;
+}
+
+/*
+ * nss_gre_redir_lag_ds_get_context()
+ *	Retrieves context GRE redirect LAG downstream node.
+ */
+struct nss_ctx_instance *nss_gre_redir_lag_ds_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.gre_redir_lag_ds_handler_id];
+}
+EXPORT_SYMBOL(nss_gre_redir_lag_ds_get_context);
+
+/*
+ * nss_gre_redir_lag_ds_tx_msg()
+ *	Transmit a gre message to NSS.
+ */
+nss_tx_status_t nss_gre_redir_lag_ds_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_lag_ds_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace messages.
+	 */
+	nss_gre_redir_lag_ds_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message. Interface should be a dynamic interface
+	 * of type NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_DS.
+	 */
+	if (!nss_gre_redir_lag_ds_verify_ifnum(ncm->interface)) {
+		nss_warning("%px: tx request for another interface: %d\n", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_GRE_REDIR_LAG_DS_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d\n", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_gre_redir_lag_ds_tx_msg);
+
+/*
+ * nss_gre_redir_lag_ds_tx_msg_sync()
+ *	Transmit a GRE lag message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_gre_redir_lag_ds_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_lag_ds_msg *ngrm)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&nss_gre_redir_lag_ds_pvt.sem);
+	nss_gre_redir_lag_ds_pvt.cb = (void *)ngrm->cm.cb;
+	nss_gre_redir_lag_ds_pvt.app_data = (void *)ngrm->cm.app_data;
+	ngrm->cm.cb = (nss_ptr_t)nss_gre_redir_lag_ds_callback;
+	ngrm->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_gre_redir_lag_ds_tx_msg(nss_ctx, ngrm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: GRE LAG DS msg tx failed\n", nss_ctx);
+		up(&nss_gre_redir_lag_ds_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&nss_gre_redir_lag_ds_pvt.complete, msecs_to_jiffies(NSS_GRE_REDIR_LAG_DS_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: GRE LAG DS tx sync failed due to timeout\n", nss_ctx);
+		nss_gre_redir_lag_ds_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = nss_gre_redir_lag_ds_pvt.response;
+	up(&nss_gre_redir_lag_ds_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_gre_redir_lag_ds_tx_msg_sync);
+
+/*
+ * nss_gre_redir_lag_ds_unregister_and_dealloc()
+ *	Unregister and deallocate nss gre redirect LAG DS node.
+ */
+enum nss_gre_redir_lag_err_types nss_gre_redir_lag_ds_unregister_and_dealloc(uint32_t ifnum)
+{
+	uint32_t ret;
+	struct nss_ctx_instance *nss_ctx __maybe_unused = nss_gre_redir_lag_ds_get_context();
+	nss_tx_status_t status;
+
+	if (!nss_gre_redir_lag_ds_verify_ifnum(ifnum)) {
+		nss_warning("%px: Unknown interface type %u.\n", nss_ctx, ifnum);
+		return NSS_GRE_REDIR_LAG_ERR_INCORRECT_IFNUM;
+	}
+
+	ret = nss_gre_redir_lag_ds_unregister_if(ifnum);
+	if (ret) {
+		nss_warning("%px: Unable to unregister interface %u.\n", nss_ctx, ifnum);
+		return ret;
+	}
+
+	status = nss_dynamic_interface_dealloc_node(ifnum, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_DS);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Unable to deallocate node %u\n", nss_ctx, ifnum);
+		return NSS_GRE_REDIR_LAG_ERR_DEALLOC_FAILED;
+	}
+
+	return NSS_GRE_REDIR_LAG_SUCCESS;
+}
+EXPORT_SYMBOL(nss_gre_redir_lag_ds_unregister_and_dealloc);
+
+/*
+ * nss_gre_redir_lag_ds_alloc_and_register_node()
+ *	Allocates and registers GRE downstream type dynamic nodes with NSS.
+ */
+int nss_gre_redir_lag_ds_alloc_and_register_node(struct net_device *dev,
+		nss_gre_redir_lag_ds_data_callback_t cb_func_data,
+		nss_gre_redir_lag_ds_msg_callback_t cb_func_msg, void *app_ctx)
+{
+	int ifnum;
+	nss_tx_status_t status;
+	struct nss_ctx_instance *nss_ctx;
+
+	ifnum = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_DS);
+	if (ifnum == -1) {
+		nss_warning("%px: Unable to allocate GRE_LAG node of type = %u\n", dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_DS);
+		return -1;
+	}
+
+	nss_ctx = nss_gre_redir_lag_ds_register_if(ifnum, dev, cb_func_data,
+			cb_func_msg, 0, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_DS, app_ctx);
+	if (!nss_ctx) {
+		nss_warning("%px: Unable to register GRE_LAG node of type = %u\n", dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_DS);
+		status = nss_dynamic_interface_dealloc_node(ifnum, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_DS);
+		if (status != NSS_TX_SUCCESS) {
+			nss_warning("%px: Unable to deallocate node of type = %u.\n", dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_DS);
+		}
+
+		return -1;
+	}
+
+	return ifnum;
+}
+EXPORT_SYMBOL(nss_gre_redir_lag_ds_alloc_and_register_node);
+
+/*
+ * nss_gre_redir_lag_ds_register_handler()
+ *	Registering handler for sending msg to base gre_lag node on NSS.
+ */
+void nss_gre_redir_lag_ds_register_handler(void)
+{
+	if (!nss_gre_redir_lag_ds_stats_dentry_create()) {
+		nss_warning(" Unable to create debugfs entry for LAG DS node.\n");
+		return;
+	}
+
+	nss_gre_redir_lag_ds_strings_dentry_create();
+	nss_gre_redir_lag_ds_pvt.cb = NULL;
+	nss_gre_redir_lag_ds_pvt.app_data = NULL;
+	sema_init(&nss_gre_redir_lag_ds_pvt.sem, 1);
+	init_completion(&nss_gre_redir_lag_ds_pvt.complete);
+}
diff --git a/qca-nss-drv/nss_gre_redir_lag_ds_log.c b/qca-nss-drv/nss_gre_redir_lag_ds_log.c
new file mode 100644
index 0000000..158cb9d
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_lag_ds_log.c
@@ -0,0 +1,164 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_gre_redir_lag_ds_log.c
+ *	NSS GRE REDIR LAG DS logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_gre_redir_lag_ds_log_message_types_str
+ *	GRE REDIR LAG DS message strings
+ */
+static int8_t *nss_gre_redir_lag_ds_log_message_types_str[NSS_GRE_REDIR_LAG_DS_MAX_MSG_TYPES] __maybe_unused = {
+	"GRE REDIR LAG DS add station Message",
+	"GRE REDIR LAG DS delete station message",
+	"GRE REDIR LAG DS update station message",
+	"GRE REDIR LAG DS stats sync message",
+};
+
+/*
+ * nss_gre_redir_lag_ds_log_error_response_types_str
+ *	Strings for error types for GRE REDIR LAG DS messages
+ */
+static int8_t *nss_gre_redir_lag_ds_log_error_response_types_str[NSS_GRE_REDIR_LAG_ERR_MAX] __maybe_unused = {
+	"GRE REDIR LAG Success",
+	"GRE REDIR LAG Incorrect Interface",
+	"GRE REDIR LAG DS Core Unregister Failed",
+	"GRE REDIR LAG DS STats Index Not Found",
+	"GRE REDIR LAG Dealloc Failed",
+};
+
+/*
+ * nss_gre_redir_lag_ds_log_add_sta_msg()
+ *	Log NSS GRE REDIR LAG DS add STA message.
+ */
+static void nss_gre_redir_lag_ds_log_add_sta_msg(struct nss_gre_redir_lag_ds_msg *ngm)
+{
+	struct nss_gre_redir_lag_ds_add_sta_msg *ngasm __maybe_unused = &ngm->msg.add_sta;
+	nss_trace("%px: NSS GRE REDIR LAG DS Add STA Message:\n"
+		"GRE REDIR LAG DS Station MAC Address: %px\n"
+		"GRE REDIR LAG DS Reorder Type: %d\n",
+		ngasm, ngasm->mac, ngasm->reorder_type);
+}
+
+/*
+ * nss_gre_redir_lag_ds_log_del_sta_msg()
+ *	Log NSS GRE REDIR LAG DS del STA message.
+ */
+static void nss_gre_redir_lag_ds_log_del_sta_msg(struct nss_gre_redir_lag_ds_msg *ngm)
+{
+	struct nss_gre_redir_lag_ds_delete_sta_msg *ngdsm __maybe_unused = &ngm->msg.del_sta;
+	nss_trace("%px: NSS GRE REDIR LAG DS Del STA Message:\n"
+		"GRE REDIR LAG DS Station MAC Address: %px\n",
+		ngdsm, ngdsm->mac);
+}
+
+/*
+ * nss_gre_redir_lag_ds_log_add_sta_msg()
+ *	Log NSS GRE REDIR LAG DS add STA message.
+ */
+static void nss_gre_redir_lag_ds_log_update_sta_msg(struct nss_gre_redir_lag_ds_msg *ngm)
+{
+	struct nss_gre_redir_lag_ds_update_sta_msg *ngusm __maybe_unused = &ngm->msg.update_sta;
+	nss_trace("%px: NSS GRE REDIR LAG DS Update STA Message:\n"
+		"GRE REDIR LAG DS Station MAC Address: %px\n"
+		"GRE REDIR LAG DS Reorder Type: %d\n",
+		ngusm, ngusm->mac, ngusm->reorder_type);
+}
+
+/*
+ * nss_gre_redir_lag_ds_log_verbose()
+ *	Log message contents.
+ */
+static void nss_gre_redir_lag_ds_log_verbose(struct nss_gre_redir_lag_ds_msg *ngm)
+{
+	switch (ngm->cm.type) {
+	case NSS_GRE_REDIR_LAG_DS_ADD_STA_MSG:
+		nss_gre_redir_lag_ds_log_add_sta_msg(ngm);
+		break;
+
+	case NSS_GRE_REDIR_LAG_DS_DEL_STA_MSG:
+		nss_gre_redir_lag_ds_log_del_sta_msg(ngm);
+		break;
+
+	case NSS_GRE_REDIR_LAG_DS_UPDATE_STA_MSG:
+		nss_gre_redir_lag_ds_log_update_sta_msg(ngm);
+		break;
+
+	case NSS_GRE_REDIR_LAG_DS_STATS_SYNC_MSG:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", ngm);
+		break;
+	}
+}
+
+/*
+ * nss_gre_redir_lag_ds_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_gre_redir_lag_ds_log_tx_msg(struct nss_gre_redir_lag_ds_msg *ngm)
+{
+	if (ngm->cm.type >= NSS_GRE_REDIR_LAG_DS_MAX_MSG_TYPES) {
+		nss_warning("%px: Invalid message type\n", ngm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ngm, ngm->cm.type, nss_gre_redir_lag_ds_log_message_types_str[ngm->cm.type]);
+	nss_gre_redir_lag_ds_log_verbose(ngm);
+}
+
+/*
+ * nss_gre_redir_lag_ds_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_gre_redir_lag_ds_log_rx_msg(struct nss_gre_redir_lag_ds_msg *ngm)
+{
+	if (ngm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ngm);
+		return;
+	}
+
+	if (ngm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ngm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ngm, ngm->cm.type,
+			nss_gre_redir_lag_ds_log_message_types_str[ngm->cm.type],
+			ngm->cm.response, nss_cmn_response_str[ngm->cm.response]);
+		goto verbose;
+	}
+
+	if (ngm->cm.error >= NSS_GRE_REDIR_LAG_ERR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			ngm, ngm->cm.type, nss_gre_redir_lag_ds_log_message_types_str[ngm->cm.type],
+			ngm->cm.response, nss_cmn_response_str[ngm->cm.response],
+			ngm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		ngm, ngm->cm.type, nss_gre_redir_lag_ds_log_message_types_str[ngm->cm.type],
+		ngm->cm.response, nss_cmn_response_str[ngm->cm.response],
+		ngm->cm.error, nss_gre_redir_lag_ds_log_error_response_types_str[ngm->cm.error]);
+
+verbose:
+	nss_gre_redir_lag_ds_log_verbose(ngm);
+}
diff --git a/qca-nss-drv/nss_gre_redir_lag_ds_log.h b/qca-nss-drv/nss_gre_redir_lag_ds_log.h
new file mode 100644
index 0000000..b091876
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_lag_ds_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_GRE_REDIR_LAG_DS_LOG_H__
+#define __NSS_GRE_REDIR_LAG_DS_LOG_H__
+
+/*
+ * nss_gre_redir_lag_ds_log.h
+ *	NSS GRE REDIR LAG DS Log Header File
+ */
+
+/*
+ * nss_gre_redir_lag_ds_log_tx_msg
+ *	Logs a gre redir lag ds message that is sent to the NSS firmware.
+ */
+void nss_gre_redir_lag_ds_log_tx_msg(struct nss_gre_redir_lag_ds_msg *ngm);
+
+/*
+ * nss_gre_redir_lag_ds_log_rx_msg
+ *	Logs a gre redir lag ds message that is received from the NSS firmware.
+ */
+void nss_gre_redir_lag_ds_log_rx_msg(struct nss_gre_redir_lag_ds_msg *ngm);
+
+#endif /* __NSS_GRE_REDIR_LAG_DS_LOG_H__ */
diff --git a/qca-nss-drv/nss_gre_redir_lag_ds_stats.c b/qca-nss-drv/nss_gre_redir_lag_ds_stats.c
new file mode 100644
index 0000000..76b3d7f
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_lag_ds_stats.c
@@ -0,0 +1,211 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_gre_redir_lag.h"
+#include "nss_gre_redir_lag_ds_stats.h"
+#include "nss_gre_redir_lag_ds_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_gre_redir_lag_ds_stats_notifier);
+
+/*
+ * Spinlock to protect GRE redirect lag ds statistics update/read
+ */
+DEFINE_SPINLOCK(nss_gre_redir_lag_ds_stats_lock);
+
+extern struct nss_gre_redir_lag_ds_tun_stats tun_ds_stats[NSS_GRE_REDIR_LAG_MAX_NODE];
+
+/*
+ * nss_gre_redir_lag_ds_stats_get()
+ *	Get statistics for downstream LAG node.
+ */
+bool nss_gre_redir_lag_ds_stats_get(struct nss_gre_redir_lag_ds_tun_stats *cmn_stats, uint32_t index)
+{
+	if (index >= NSS_GRE_REDIR_LAG_MAX_NODE)
+		return false;
+
+	spin_lock_bh(&nss_gre_redir_lag_ds_stats_lock);
+	if (!tun_ds_stats[index].valid) {
+		spin_unlock_bh(&nss_gre_redir_lag_ds_stats_lock);
+		return false;
+	}
+
+	memcpy((void *)cmn_stats, (void *)&tun_ds_stats[index], sizeof(*cmn_stats));
+	spin_unlock_bh(&nss_gre_redir_lag_ds_stats_lock);
+	return true;
+}
+
+/*
+ * nss_gre_redir_lag_ds_stats_read()
+ *	Read gre_redir_lag_ds tunnel stats.
+ */
+static ssize_t nss_gre_redir_lag_ds_cmn_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	/*
+	 * Max output lines = #stats +
+	 * few blank lines for banner printing + Number of Extra outputlines
+	 * for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_GRE_REDIR_LAG_DS_STATS_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	struct nss_stats_data *data = fp->private_data;
+	struct nss_gre_redir_lag_ds_tun_stats stats;
+	ssize_t bytes_read = 0;
+	size_t size_wr = 0;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	while (data->index < NSS_GRE_REDIR_LAG_MAX_NODE) {
+		if (nss_gre_redir_lag_ds_stats_get(&stats, data->index)) {
+			break;
+		}
+
+		data->index++;
+	}
+
+	if (data->index >= NSS_GRE_REDIR_LAG_MAX_NODE) {
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "gre_redir_lag_ds stats", NSS_STATS_SINGLE_CORE);
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nTunnel stats for %03u\n", stats.ifnum);
+	size_wr += nss_stats_print("gre_redir_lag_ds", NULL, NSS_STATS_SINGLE_INSTANCE, nss_gre_redir_lag_ds_strings_stats,
+					&stats.rx_packets, NSS_GRE_REDIR_LAG_DS_STATS_MAX, lbuf, size_wr, size_al);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	data->index++;
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_gre_redir_lag_ds_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(gre_redir_lag_ds_cmn)
+
+/*
+ * nss_gre_redir_lag_ds_stats_dentry_create()
+ *	Create debugfs directory entry.
+ */
+struct dentry *nss_gre_redir_lag_ds_stats_dentry_create(void)
+{
+	struct dentry *gre_redir;
+	struct dentry *cmn_stats;
+
+	gre_redir = nss_gre_redir_get_dentry();
+	if (unlikely(!gre_redir)) {
+		nss_warning("Failed to retrieve directory entry qca-nss-drv/stats/gre_redir/\n");
+		return NULL;
+	}
+
+	cmn_stats = debugfs_create_file("lag_ds_cmn_stats", 0400, gre_redir,
+			&nss_top_main, &nss_gre_redir_lag_ds_cmn_stats_ops);
+	if (unlikely(!cmn_stats)) {
+		nss_warning("Failed to create qca-nss-drv/stats/gre_redir/lag_ds_cmn_stats file\n");
+		return NULL;
+	}
+
+	return cmn_stats;
+}
+
+/*
+ * nss_gre_redir_lag_ds_stats_sync()
+ *	Update synchonized statistics.
+ */
+void nss_gre_redir_lag_ds_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_lag_ds_sync_stats_msg *ngss, uint32_t ifnum)
+{
+	int idx, j;
+
+	spin_lock_bh(&nss_gre_redir_lag_ds_stats_lock);
+	if (!nss_gre_redir_lag_ds_get_node_idx(ifnum, &idx)) {
+		spin_unlock_bh(&nss_gre_redir_lag_ds_stats_lock);
+		nss_warning("%px: Unable to update hash stats msg. Stats context not found.\n", nss_ctx);
+		return;
+	}
+
+	tun_ds_stats[idx].tx_packets += ngss->node_stats.tx_packets;
+	tun_ds_stats[idx].tx_bytes += ngss->node_stats.tx_bytes;
+	tun_ds_stats[idx].rx_packets += ngss->node_stats.rx_packets;
+	tun_ds_stats[idx].rx_bytes += ngss->node_stats.rx_bytes;
+	for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+		tun_ds_stats[idx].rx_dropped[j] += ngss->node_stats.rx_dropped[j];
+	}
+
+	tun_ds_stats[idx].dst_invalid += ngss->ds_stats.dst_invalid;
+	tun_ds_stats[idx].exception_cnt += ngss->ds_stats.exception_cnt;
+	spin_unlock_bh(&nss_gre_redir_lag_ds_stats_lock);
+}
+
+/*
+ * nss_gre_redir_lag_ds_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_gre_redir_lag_ds_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_gre_redir_lag_ds_stats_notification *stats_notify;
+	int idx;
+
+	stats_notify = kzalloc(sizeof(struct nss_gre_redir_lag_ds_stats_notification), GFP_ATOMIC);
+	if (!stats_notify) {
+		nss_warning("Unable to allocate memory for stats notification\n");
+		return;
+	}
+
+	spin_lock_bh(&nss_gre_redir_lag_ds_stats_lock);
+	if (!nss_gre_redir_lag_ds_get_node_idx(if_num, &idx)) {
+		spin_unlock_bh(&nss_gre_redir_lag_ds_stats_lock);
+		nss_warning("%px: Unable to update hash stats msg. Stats context not found.\n", nss_ctx);
+		kfree(stats_notify);
+		return;
+	}
+
+	stats_notify->core_id = nss_ctx->id;
+	stats_notify->if_num = if_num;
+	memcpy(&(stats_notify->stats_ctx), &(tun_ds_stats[idx]), sizeof(stats_notify->stats_ctx));
+	spin_unlock_bh(&nss_gre_redir_lag_ds_stats_lock);
+	atomic_notifier_call_chain(&nss_gre_redir_lag_ds_stats_notifier, NSS_STATS_EVENT_NOTIFY, stats_notify);
+	kfree(stats_notify);
+}
+
+/*
+ * nss_gre_redir_lag_ds_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_gre_redir_lag_ds_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_gre_redir_lag_ds_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_gre_redir_lag_ds_stats_unregister_notifier);
+
+/*
+ * nss_gre_redir_lag_ds_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_gre_redir_lag_ds_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_gre_redir_lag_ds_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_gre_redir_lag_ds_stats_register_notifier);
diff --git a/qca-nss-drv/nss_gre_redir_lag_ds_stats.h b/qca-nss-drv/nss_gre_redir_lag_ds_stats.h
new file mode 100644
index 0000000..127f008
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_lag_ds_stats.h
@@ -0,0 +1,28 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ************************************************************************
+ */
+
+#ifndef __NSS_GRE_REDIR_LAG_DS_STATS_H__
+#define __NSS_GRE_REDIR_LAG_DS_STATS_H__
+
+extern spinlock_t nss_gre_redir_lag_ds_stats_lock;
+extern void nss_gre_redir_lag_ds_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern bool nss_gre_redir_lag_ds_verify_ifnum(uint32_t if_num);
+extern bool nss_gre_redir_lag_ds_get_node_idx(uint32_t ifnum, uint32_t *idx);
+extern void nss_gre_redir_lag_ds_stats_sync(struct nss_ctx_instance *nss_ctx,
+					struct nss_gre_redir_lag_ds_sync_stats_msg *ngss, uint32_t ifnum);
+extern struct dentry *nss_gre_redir_lag_ds_stats_dentry_create(void);
+
+#endif
diff --git a/qca-nss-drv/nss_gre_redir_lag_ds_strings.c b/qca-nss-drv/nss_gre_redir_lag_ds_strings.c
new file mode 100644
index 0000000..1851899
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_lag_ds_strings.c
@@ -0,0 +1,60 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_gre_redir_lag_ds_strings.h"
+
+/*
+ * nss_gre_redir_lag_ds_strings_stats
+ *	GRE REDIR LAG DS common statistics strings.
+ */
+struct nss_stats_info nss_gre_redir_lag_ds_strings_stats[NSS_GRE_REDIR_LAG_DS_STATS_MAX] = {
+	{"rx_packets",		NSS_STATS_TYPE_COMMON},
+	{"rx_bytes",		NSS_STATS_TYPE_COMMON},
+	{"tx_packets",		NSS_STATS_TYPE_COMMON},
+	{"tx_bytes",		NSS_STATS_TYPE_COMMON},
+	{"rx_dropped_0",	NSS_STATS_TYPE_DROP},
+	{"rx_dropped_1",	NSS_STATS_TYPE_DROP},
+	{"rx_dropped_2",	NSS_STATS_TYPE_DROP},
+	{"rx_dropped_3",	NSS_STATS_TYPE_DROP},
+	{"dst_invalid",		NSS_STATS_TYPE_EXCEPTION},
+	{"exception_packets",	NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_gre_redir_lag_ds_strings_read()
+ *	Read gre_redir_lag_ds statistics names
+ */
+static ssize_t nss_gre_redir_lag_ds_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_gre_redir_lag_ds_strings_stats, NSS_GRE_REDIR_LAG_DS_STATS_MAX);
+}
+
+/*
+ * nss_gre_redir_lag_ds_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(gre_redir_lag_ds);
+
+/*
+ * nss_gre_redir_lag_ds_strings_dentry_create()
+ *	Create gre_redir_lag_ds statistics strings debug entry.
+ */
+void nss_gre_redir_lag_ds_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("gre_redir_lag_ds", &nss_gre_redir_lag_ds_strings_ops);
+}
diff --git a/qca-nss-drv/nss_gre_redir_lag_ds_strings.h b/qca-nss-drv/nss_gre_redir_lag_ds_strings.h
new file mode 100644
index 0000000..c85bc77
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_lag_ds_strings.h
@@ -0,0 +1,25 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#ifndef __NSS_GRE_REDIR_LAG_DS_STRINGS_H
+#define __NSS_GRE_REDIR_LAG_DS_STRINGS_H
+
+#include "nss_gre_redir_lag_ds_stats.h"
+
+extern struct nss_stats_info nss_gre_redir_lag_ds_strings_stats[NSS_GRE_REDIR_LAG_DS_STATS_MAX];
+extern void nss_gre_redir_lag_ds_strings_dentry_create(void);
+
+#endif /* __NSS_GRE_REDIR_LAG_DS_STRINGS_H */
diff --git a/qca-nss-drv/nss_gre_redir_lag_us.c b/qca-nss-drv/nss_gre_redir_lag_us.c
new file mode 100644
index 0000000..8e1b758
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_lag_us.c
@@ -0,0 +1,665 @@
+/*
+ ****************************************************************************
+ * Copyright (c) 2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ****************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_gre_redir_lag_us_stats.h"
+#include "nss_gre_redir_lag_us_log.h"
+#include "nss_gre_redir_lag_us_strings.h"
+
+#define NSS_GRE_REDIR_LAG_US_TX_TIMEOUT 3000 /* 3 Seconds */
+#define NSS_GRE_REDIR_LAG_US_STATS_SYNC_PERIOD msecs_to_jiffies(4000)
+#define NSS_GRE_REDIR_LAG_US_STATS_SYNC_UDELAY 4000
+
+struct nss_gre_redir_lag_us_cmn_ctx cmn_ctx;
+
+/*
+ * Sync response context.
+ */
+static struct {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+	nss_gre_redir_lag_us_msg_callback_t *cb;
+	void *app_data;
+} nss_gre_redir_lag_us_sync_ctx;
+
+/*
+ * nss_gre_redir_lag_us_callback()
+ *	Callback to handle the completion of HLOS-->NSS messages.
+ */
+static void nss_gre_redir_lag_us_callback(void *app_data, struct nss_gre_redir_lag_us_msg *nim)
+{
+	nss_gre_redir_lag_us_msg_callback_t callback = (nss_gre_redir_lag_us_msg_callback_t)nss_gre_redir_lag_us_sync_ctx.cb;
+	void *data = nss_gre_redir_lag_us_sync_ctx.app_data;
+
+	nss_gre_redir_lag_us_sync_ctx.cb = NULL;
+	nss_gre_redir_lag_us_sync_ctx.app_data = NULL;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("GRE redir LAG US Error response %d\n", nim->cm.response);
+		nss_gre_redir_lag_us_sync_ctx.response = NSS_TX_FAILURE;
+	} else {
+		nss_gre_redir_lag_us_sync_ctx.response = NSS_TX_SUCCESS;
+	}
+
+	if (callback) {
+		callback(data, &nim->cm);
+	}
+
+	complete(&nss_gre_redir_lag_us_sync_ctx.complete);
+}
+
+/*
+ * nss_gre_redir_lag_us_hash_update_stats_req()
+ *	Update query hash message's index for next request.
+ */
+static void nss_gre_redir_lag_us_hash_update_stats_req(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_lag_us_msg *ngrm)
+{
+	uint32_t ifnum = ngrm->cm.interface;
+	uint32_t idx, sync_delay = NSS_GRE_REDIR_LAG_US_STATS_SYNC_PERIOD;
+	struct nss_gre_redir_lag_us_hash_stats_query_msg *nim = &ngrm->msg.hash_stats;
+
+	spin_lock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+	if (!nss_gre_redir_lag_us_get_node_idx(ifnum, &idx)) {
+		spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+		nss_warning("%px: Unable to update hash stats msg. Stats context not found.\n", nss_ctx);
+		return;
+	}
+
+	/*
+	 * Update start index for next iteration of the query.
+	 */
+	if (ngrm->cm.response == NSS_CMN_RESPONSE_ACK) {
+		cmn_ctx.stats_ctx[idx].db_sync_msg.msg.hash_stats.db_entry_idx = nim->db_entry_next;
+	} else {
+		cmn_ctx.stats_ctx[idx].db_sync_msg.msg.hash_stats.db_entry_idx = 0;
+	}
+
+	/*
+	 * If more hash entries are to be fetched from FW, queue work with delay of one eighth of
+	 * the polling period. Else, schedule work with a delay of polling period.
+	 */
+	if (cmn_ctx.stats_ctx[idx].db_sync_msg.msg.hash_stats.db_entry_idx)
+		sync_delay = NSS_GRE_REDIR_LAG_US_STATS_SYNC_PERIOD / 8;
+
+	queue_delayed_work(cmn_ctx.nss_gre_redir_lag_us_wq, &(cmn_ctx.stats_ctx[idx].nss_gre_redir_lag_us_work), sync_delay);
+	spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+}
+
+/*
+ * nss_gre_redir_lag_us_handler()
+ *	Handle NSS -> HLOS messages for gre tunnel
+ */
+static void nss_gre_redir_lag_us_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	void *ctx;
+	struct nss_gre_redir_lag_us_msg *ngrm = (struct nss_gre_redir_lag_us_msg *)ncm;
+	nss_gre_redir_lag_us_msg_callback_t cb;
+
+	/*
+	 * Interface should be a dynamic interface of type NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_US.
+	 */
+	BUG_ON(!nss_gre_redir_lag_us_verify_ifnum(ncm->interface));
+
+	/*
+	 * Trace messages.
+	 */
+	nss_gre_redir_lag_us_log_rx_msg(ngrm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >=  NSS_GRE_REDIR_LAG_US_MAX_MSG_TYPES) {
+		nss_warning("%px: received invalid message %d for gre interface\n", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_gre_redir_lag_us_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d\n", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, GRE sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->nss_rx_interface_handlers[ncm->interface].app_data;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	switch (ncm->type) {
+	case NSS_GRE_REDIR_LAG_US_CMN_STATS_SYNC_MSG:
+		nss_gre_redir_lag_us_stats_sync(nss_ctx, &ngrm->msg.us_sync_stats, ncm->interface);
+		nss_gre_redir_lag_us_stats_notify(nss_ctx, ncm->interface);
+		break;
+
+	case NSS_GRE_REDIR_LAG_US_DB_HASH_NODE_MSG:
+		nss_gre_redir_lag_us_hash_update_stats_req(nss_ctx, ngrm);
+		break;
+	}
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_gre_redir_lag_us_msg_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	/*
+	 * call gre tunnel callback
+	 */
+	cb(ctx, ncm);
+}
+
+/*
+ * nss_gre_redir_lag_us_tx_msg_with_size()
+ *	Transmit a GRE message to NSSFW with size.
+ */
+static nss_tx_status_t nss_gre_redir_lag_us_tx_msg_with_size(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_lag_us_msg *msg, uint32_t size)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Sanity check the message. Interface should be a dynamic
+	 * interface of type NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_US.
+	 */
+	if (!nss_gre_redir_lag_us_verify_ifnum(ncm->interface)) {
+		nss_warning("%px: tx request for another interface: %d\n", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_GRE_REDIR_LAG_US_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d\n", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), size);
+}
+
+/*
+ * nss_gre_redir_lag_us_tx_msg_sync_with_size()
+ *	Transmit a GRE LAG message to NSS firmware synchronously with size.
+ */
+static nss_tx_status_t nss_gre_redir_lag_us_tx_msg_sync_with_size(struct nss_ctx_instance *nss_ctx,
+		 struct nss_gre_redir_lag_us_msg *ngrm, uint32_t size)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&nss_gre_redir_lag_us_sync_ctx.sem);
+
+	/*
+	 * Save the client's callback, and initialize the message
+	 * with the callback which releases the semaphore after message
+	 * response is received, This callback will inturn call the client's
+	 * callback.
+	 */
+	nss_gre_redir_lag_us_sync_ctx.cb = (void *)ngrm->cm.cb;
+	nss_gre_redir_lag_us_sync_ctx.app_data = (void *)ngrm->cm.app_data;
+	ngrm->cm.cb = (nss_ptr_t)nss_gre_redir_lag_us_callback;
+	ngrm->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_gre_redir_lag_us_tx_msg_with_size(nss_ctx, ngrm, size);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: gre_tx_msg failed\n", nss_ctx);
+		up(&nss_gre_redir_lag_us_sync_ctx.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&nss_gre_redir_lag_us_sync_ctx.complete, msecs_to_jiffies(NSS_GRE_REDIR_LAG_US_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: GRE LAG US tx sync failed due to timeout\n", nss_ctx);
+		nss_gre_redir_lag_us_sync_ctx.response = NSS_TX_FAILURE;
+	}
+
+	status = nss_gre_redir_lag_us_sync_ctx.response;
+	up(&nss_gre_redir_lag_us_sync_ctx.sem);
+	return status;
+}
+
+/*
+ * nss_gre_redir_lag_us_stats_sync_req_work()
+ *	Work function for hash statistics synchronization.
+ */
+static void nss_gre_redir_lag_us_stats_sync_req_work(struct work_struct *work)
+{
+	struct delayed_work *d_work = container_of(work, struct delayed_work, work);
+	struct nss_gre_redir_lag_us_pvt_sync_stats *sync_ctx = container_of(d_work, struct nss_gre_redir_lag_us_pvt_sync_stats,
+			nss_gre_redir_lag_us_work);
+	struct nss_gre_redir_lag_us_hash_stats_query_msg *nicsm_req = &(sync_ctx->db_sync_msg.msg.hash_stats);
+	nss_tx_status_t nss_tx_status;
+	nss_gre_redir_lag_us_msg_callback_t cb;
+	void *app_data;
+	struct nss_ctx_instance *nss_ctx __maybe_unused = nss_gre_redir_lag_us_get_context();
+	int retry = NSS_GRE_REDIR_LAG_US_STATS_SYNC_RETRY;
+
+	spin_lock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+	cb = sync_ctx->cb;
+	app_data = sync_ctx->app_data;
+	spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+
+	nss_cmn_msg_init(&(sync_ctx->db_sync_msg.cm), sync_ctx->ifnum,
+			NSS_GRE_REDIR_LAG_US_DB_HASH_NODE_MSG, sizeof(struct nss_gre_redir_lag_us_hash_stats_query_msg),
+			cb, app_data);
+	while (retry) {
+		nss_tx_status = nss_gre_redir_lag_us_tx_msg_sync_with_size(nss_ctx, &(sync_ctx->db_sync_msg), PAGE_SIZE);
+		if (nss_tx_status == NSS_TX_SUCCESS) {
+			return;
+		}
+
+		retry--;
+		nss_warning("%px: TX_NOT_OKAY, try again later\n", nss_ctx);
+		usleep_range(100, 200);
+	}
+
+	/*
+	 * TX failed after retries, take fresh start.
+	 */
+	nicsm_req->count = 0;
+	nicsm_req->db_entry_idx = 0;
+	queue_delayed_work(cmn_ctx.nss_gre_redir_lag_us_wq, &(sync_ctx->nss_gre_redir_lag_us_work), NSS_GRE_REDIR_LAG_US_STATS_SYNC_PERIOD);
+}
+
+/*
+ * nss_gre_redir_lag_us_sync_work_init()
+ *	Initialize work.
+ */
+static bool nss_gre_redir_lag_us_sync_work_init(uint32_t ifnum)
+{
+	struct nss_gre_redir_lag_us_hash_stats_query_msg *hash_stats_msg;
+	struct nss_ctx_instance __maybe_unused *nss_ctx = nss_gre_redir_lag_us_get_context();
+	int ret, idx;
+
+	spin_lock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+	if (!nss_gre_redir_lag_us_get_node_idx(ifnum, &idx)) {
+		spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+		nss_warning("%px: Unable to init work. Stats context not found.\n", nss_ctx);
+		return false;
+	}
+
+	hash_stats_msg = &(cmn_ctx.stats_ctx[idx].db_sync_msg.msg.hash_stats);
+	hash_stats_msg->db_entry_idx = 0;
+	INIT_DELAYED_WORK(&(cmn_ctx.stats_ctx[idx].nss_gre_redir_lag_us_work), nss_gre_redir_lag_us_stats_sync_req_work);
+	ret = queue_delayed_work(cmn_ctx.nss_gre_redir_lag_us_wq,
+			&(cmn_ctx.stats_ctx[idx].nss_gre_redir_lag_us_work), NSS_GRE_REDIR_LAG_US_STATS_SYNC_PERIOD);
+	if (!ret) {
+		spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+		nss_warning("%px: Unable to queue work function to work queue\n", nss_ctx);
+		return false;
+	}
+
+	spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+	return true;
+}
+
+/*
+ * nss_gre_redir_lag_us_unregister_if()
+ *	Unregister GRE redirect LAG upstream node.
+ */
+static enum nss_gre_redir_lag_err_types nss_gre_redir_lag_us_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx __maybe_unused = nss_gre_redir_lag_us_get_context();
+	uint32_t status;
+	int idx;
+
+	nss_assert(nss_ctx);
+	nss_assert(!nss_gre_redir_lag_us_verify_ifnum(if_num));
+
+	status = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to unregister handler for gre_lag interface %d with NSS core\n", nss_ctx, if_num);
+		return NSS_GRE_REDIR_LAG_ERR_CORE_UNREGISTER_FAILED;
+	}
+
+	status = nss_core_unregister_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to unregister handler for gre_lag interface %d with NSS core\n", nss_ctx, if_num);
+		return NSS_GRE_REDIR_LAG_ERR_CORE_UNREGISTER_FAILED;
+	}
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	spin_lock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+	if (!nss_gre_redir_lag_us_get_node_idx(if_num, &idx)) {
+		spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+		nss_warning("Stats context not found.\n");
+		return NSS_GRE_REDIR_LAG_ERR_STATS_INDEX_NOT_FOUND;
+	}
+
+	cmn_ctx.stats_ctx[idx].cb = NULL;
+	cmn_ctx.stats_ctx[idx].app_data = NULL;
+	cmn_ctx.stats_ctx[idx].valid = false;
+	spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+
+	/*
+	 * Work is per LAG US node. Cancel works for this node.
+	 */
+	cancel_delayed_work_sync(&(cmn_ctx.stats_ctx[idx].nss_gre_redir_lag_us_work));
+	return NSS_GRE_REDIR_LAG_SUCCESS;
+}
+
+/*
+ * nss_gre_redir_lag_us_register_if()
+ *	Register GRE redirect LAG upstream node.
+ */
+static struct nss_ctx_instance *nss_gre_redir_lag_us_register_if(uint32_t if_num, struct net_device *netdev,
+		nss_gre_redir_lag_us_data_callback_t cb_func_data,
+		nss_gre_redir_lag_us_msg_callback_t cb_func_msg, uint32_t features, uint32_t type, void *app_ctx)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_redir_lag_us_get_context();
+	uint32_t status;
+	int i;
+	nss_assert(nss_ctx);
+	nss_assert(!nss_gre_redir_lag_us_verify_ifnum(if_num));
+
+	spin_lock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+	for (i = 0; i < NSS_GRE_REDIR_LAG_MAX_NODE; i++) {
+		if (!cmn_ctx.stats_ctx[i].valid) {
+			cmn_ctx.stats_ctx[i].ifnum = if_num;
+			cmn_ctx.stats_ctx[i].valid = true;
+			cmn_ctx.stats_ctx[i].cb = cb_func_msg;
+			cmn_ctx.stats_ctx[i].app_data = app_ctx;
+			break;
+		}
+	}
+
+	spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+	if (i == NSS_GRE_REDIR_LAG_MAX_NODE) {
+		nss_warning("Maximum number of LAG nodes are already present.\n");
+		return NULL;
+	}
+
+	/*
+	 * Registering handler for sending tunnel interface msgs to NSS.
+	 */
+	status = nss_core_register_handler(nss_ctx, if_num, nss_gre_redir_lag_us_msg_handler, app_ctx);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to register handler for gre_lag interface %d with NSS core\n", nss_ctx, if_num);
+		spin_lock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+		cmn_ctx.stats_ctx[i].valid = false;
+		cmn_ctx.stats_ctx[i].cb = NULL;
+		cmn_ctx.stats_ctx[i].app_data = NULL;
+		spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+		return NULL;
+	}
+
+	/*
+	 * Registering handler for sending tunnel interface msgs to NSS.
+	 */
+	status = nss_core_register_msg_handler(nss_ctx, if_num, cb_func_msg);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_core_unregister_handler(nss_ctx, if_num);
+		nss_warning("%px: Not able to register handler for gre_lag interface %d with NSS core\n", nss_ctx, if_num);
+		spin_lock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+		cmn_ctx.stats_ctx[i].valid = false;
+		cmn_ctx.stats_ctx[i].cb = NULL;
+		cmn_ctx.stats_ctx[i].app_data = NULL;
+		spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+		return NULL;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, cb_func_data, NULL, NULL, netdev, features);
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num, type);
+	return nss_ctx;
+}
+
+/*
+ * nss_gre_redir_lag_us_get_node_idx()
+ *	Returns index of statistics context.
+ */
+bool nss_gre_redir_lag_us_get_node_idx(uint32_t ifnum, uint32_t *idx)
+{
+	uint32_t node_idx;
+	for (node_idx = 0; node_idx < NSS_GRE_REDIR_LAG_MAX_NODE; node_idx++) {
+		if ((cmn_ctx.stats_ctx[node_idx].valid) && (cmn_ctx.stats_ctx[node_idx].ifnum == ifnum)) {
+			*idx = node_idx;
+			return true;
+		}
+	}
+
+	return false;
+}
+
+/*
+ * nss_gre_redir_lag_us_verify_ifnum()
+ *	Verify interface type.
+ */
+bool nss_gre_redir_lag_us_verify_ifnum(uint32_t if_num)
+{
+	return nss_dynamic_interface_get_type(nss_gre_redir_lag_us_get_context(), if_num) == NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_US;
+}
+
+/*
+ * nss_gre_redir_lag_us_get_context()
+ *	Retrieve context for GRE redirect LAG upstream node.
+ */
+struct nss_ctx_instance *nss_gre_redir_lag_us_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.gre_redir_lag_us_handler_id];
+}
+EXPORT_SYMBOL(nss_gre_redir_lag_us_get_context);
+
+/*
+ * nss_gre_redir_lag_us_configure_node()
+ *	Configure upstream lag node.
+ */
+bool nss_gre_redir_lag_us_configure_node(uint32_t ifnum,
+		struct nss_gre_redir_lag_us_config_msg *ngluc)
+{
+	struct nss_gre_redir_lag_us_msg *config;
+	uint32_t len, iftype, idx = 0, i;
+	bool ret;
+	nss_tx_status_t status;
+	struct nss_ctx_instance *nss_ctx __maybe_unused = nss_ctx = nss_gre_redir_lag_us_get_context();
+
+	if (!nss_ctx) {
+		nss_warning("Unable to retrieve NSS context.\n");
+		return false;
+	}
+
+	config = (struct nss_gre_redir_lag_us_msg *) kzalloc(sizeof(struct nss_gre_redir_lag_us_msg), GFP_KERNEL);
+	if (!config) {
+		nss_warning("%px: Unable to allocate memory to send configure message.\n", nss_ctx);
+		return false;
+	}
+
+	iftype = nss_dynamic_interface_get_type(nss_ctx, ifnum);
+	if (iftype != NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_US) {
+		nss_warning("%px: Incorrect interface type %u\n", nss_ctx, iftype);
+		kfree(config);
+		return false;
+	}
+
+	if (!ngluc) {
+		nss_warning("%px: Pointer to GRE redir LAG US message is NULL.\n", nss_ctx);
+		kfree(config);
+		return false;
+	}
+
+	if ((ngluc->num_slaves < NSS_GRE_REDIR_LAG_MIN_SLAVE) || (ngluc->num_slaves > NSS_GRE_REDIR_LAG_MAX_SLAVE)) {
+		nss_warning("%px: Number of slaves is not in reange\n", nss_ctx);
+		kfree(config);
+		return false;
+	}
+
+	ret = nss_gre_redir_lag_us_sync_work_init(ifnum);
+	if (!ret) {
+		nss_warning("%px: Unable to initialize work queue\n", nss_ctx);
+		kfree(config);
+		return false;
+	}
+
+	len = sizeof(struct nss_gre_redir_lag_us_msg) - sizeof(struct nss_cmn_msg);
+	nss_cmn_msg_init(&config->cm, ifnum, NSS_GRE_REDIR_LAG_US_CONFIG_MSG, len, NULL, NULL);
+	config->msg.config_us.hash_mode = ngluc->hash_mode;
+	config->msg.config_us.num_slaves = ngluc->num_slaves;
+	for (i = 0; i < ngluc->num_slaves; i++) {
+		config->msg.config_us.if_num[i] = ngluc->if_num[i];
+	}
+
+	status = nss_gre_redir_lag_us_tx_msg_sync(nss_ctx, config);
+	kfree(config);
+	if (status == NSS_TX_SUCCESS) {
+		return true;
+	}
+
+	spin_lock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+	if (nss_gre_redir_lag_us_get_node_idx(ifnum, &idx)) {
+		spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+		nss_warning("%px: Stats context not found.\n", nss_ctx);
+		return false;
+	}
+
+	spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+
+	/*
+	 * Work is per LAG US node. Cancel work as configuration failed.
+	 */
+	cancel_delayed_work_sync(&(cmn_ctx.stats_ctx[idx].nss_gre_redir_lag_us_work));
+	nss_warning("%px: Unable to configure upstream lag node %d.\n", nss_ctx, ifnum);
+	return false;
+}
+EXPORT_SYMBOL(nss_gre_redir_lag_us_configure_node);
+
+/*
+ * nss_gre_redir_lag_us_tx_msg()
+ *	Transmit a GRE LAG message to NSS firmware asynchronously.
+ */
+nss_tx_status_t nss_gre_redir_lag_us_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_lag_us_msg *ngrm)
+{
+	/*
+	 * Trace messages.
+	 */
+	nss_gre_redir_lag_us_log_tx_msg(ngrm);
+
+	return nss_gre_redir_lag_us_tx_msg_with_size(nss_ctx, ngrm, NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_gre_redir_lag_us_tx_msg);
+
+/*
+ * nss_gre_redir_lag_us_tx_msg_sync()
+ *	Transmit a GRE lag message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_gre_redir_lag_us_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_lag_us_msg *ngrm)
+{
+	return nss_gre_redir_lag_us_tx_msg_sync_with_size(nss_ctx, ngrm, NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_gre_redir_lag_us_tx_msg_sync);
+
+/*
+ * nss_gre_redir_lag_us_unregister_and_dealloc()
+ *	Unregister and deallocate nss gre redirect LAG US node.
+ */
+enum nss_gre_redir_lag_err_types nss_gre_redir_lag_us_unregister_and_dealloc(uint32_t ifnum)
+{
+	uint32_t ret;
+	struct nss_ctx_instance *nss_ctx __maybe_unused = nss_gre_redir_lag_us_get_context();
+	nss_tx_status_t status;
+
+	if (!nss_gre_redir_lag_us_verify_ifnum(ifnum)) {
+		nss_warning("%px: Unknown interface type %u.\n", nss_ctx, ifnum);
+		return NSS_GRE_REDIR_LAG_ERR_INCORRECT_IFNUM;
+	}
+
+	ret = nss_gre_redir_lag_us_unregister_if(ifnum);
+	if (ret) {
+		nss_warning("%px: Unable to unregister interface %u.\n", nss_ctx, ifnum);
+		return ret;
+	}
+
+	status = nss_dynamic_interface_dealloc_node(ifnum, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_US);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Unable to deallocate node %u\n", nss_ctx, ifnum);
+		return NSS_GRE_REDIR_LAG_ERR_DEALLOC_FAILED;
+	}
+
+	return NSS_GRE_REDIR_LAG_SUCCESS;
+}
+EXPORT_SYMBOL(nss_gre_redir_lag_us_unregister_and_dealloc);
+
+/*
+ * nss_gre_redir_lag_us_alloc_and_register_node()
+ *	Allocates and registers GRE upstream type dynamic nodes with NSS.
+ */
+int nss_gre_redir_lag_us_alloc_and_register_node(struct net_device *dev,
+		nss_gre_redir_lag_us_data_callback_t cb_func_data,
+		nss_gre_redir_lag_us_msg_callback_t cb_func_msg, void *app_ctx)
+{
+	int ifnum;
+	nss_tx_status_t status;
+	struct nss_ctx_instance *nss_ctx;
+
+	ifnum = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_US);
+	if (ifnum == -1) {
+		nss_warning("%px: Unable to allocate GRE_LAG node of type = %u\n", dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_US);
+		return -1;
+	}
+
+	nss_ctx = nss_gre_redir_lag_us_register_if(ifnum, dev, cb_func_data,
+			cb_func_msg, 0, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_US, app_ctx);
+	if (!nss_ctx) {
+		nss_warning("%px: Unable to register GRE_LAG node of type = %u\n", dev, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_US);
+		status = nss_dynamic_interface_dealloc_node(ifnum, NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_LAG_US);
+		if (status != NSS_TX_SUCCESS) {
+			nss_warning("%px: Unable to deallocate node.\n", dev);
+		}
+
+		return -1;
+	}
+
+	return ifnum;
+}
+EXPORT_SYMBOL(nss_gre_redir_lag_us_alloc_and_register_node);
+
+/*
+ * nss_gre_redir_lag_us_register_handler()
+ *	Registering handler for sending msg to base gre_lag node on NSS.
+ */
+void nss_gre_redir_lag_us_register_handler(void)
+{
+	struct dentry *d_entry = nss_gre_redir_lag_us_stats_dentry_create();
+
+	if (!d_entry) {
+		nss_warning(" Unable to create debugfs entry for LAG US node.\n");
+		return;
+	}
+
+	cmn_ctx.nss_gre_redir_lag_us_wq = create_singlethread_workqueue("nss_gre_redir_lag_us_workqueue");
+	if (!cmn_ctx.nss_gre_redir_lag_us_wq) {
+		debugfs_remove_recursive(d_entry);
+		nss_warning("Unable to create workqueue for LAG US node.\n");
+		return;
+	}
+
+	nss_gre_redir_lag_us_strings_dentry_create();
+	nss_gre_redir_lag_us_sync_ctx.cb = NULL;
+	nss_gre_redir_lag_us_sync_ctx.app_data = NULL;
+	sema_init(&nss_gre_redir_lag_us_sync_ctx.sem, 1);
+	init_completion(&nss_gre_redir_lag_us_sync_ctx.complete);
+	spin_lock_init(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+}
diff --git a/qca-nss-drv/nss_gre_redir_lag_us_log.c b/qca-nss-drv/nss_gre_redir_lag_us_log.c
new file mode 100644
index 0000000..8601979
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_lag_us_log.c
@@ -0,0 +1,191 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_gre_redir_lag_us_log.c
+ *	NSS GRE REDIR LAG US logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_gre_redir_lag_us_log_message_types_str
+ *	GRE REDIR LAG US message strings
+ */
+static int8_t *nss_gre_redir_lag_us_log_message_types_str[NSS_GRE_REDIR_LAG_US_MAX_MSG_TYPES] __maybe_unused = {
+	"GRE REDIR LAG US config Message",
+	"GRE REDIR LAG US add hash node message",
+	"GRE REDIR LAG US delete hash node message",
+	"GRE REDIR LAG US query hash node message",
+	"GRE REDIR LAG US stats sync message",
+	"GRE REDIR LAG US DB hash node message",
+};
+
+/*
+ * nss_gre_redir_lag_us_log_error_response_types_str
+ *	Strings for error types for GRE REDIR LAG US messages
+ */
+static int8_t *nss_gre_redir_lag_us_log_error_response_types_str[NSS_GRE_REDIR_LAG_ERR_MAX] __maybe_unused = {
+	"GRE REDIR LAG Success",
+	"GRE REDIR LAG Incorrect Interface",
+	"GRE REDIR LAG US Core Unregister Failed",
+	"GRE REDIR LAG US STats Index Not Found",
+	"GRE REDIR LAG Dealloc Failed",
+};
+
+/*
+ * nss_gre_redir_lag_us_log_config_msg()
+ *	Log NSS GRE REDIR LAG US config message.
+ */
+static void nss_gre_redir_lag_us_log_config_msg(struct nss_gre_redir_lag_us_msg *ngm)
+{
+	struct nss_gre_redir_lag_us_config_msg *ngcm __maybe_unused = &ngm->msg.config_us;
+	nss_trace("%px: NSS GRE REDIR LAG Config Message:\n"
+		"GRE REDIR LAG US Hash Mode: %d\n"
+		"GRE REDIR LAG US Number of Slaves: %d\n"
+		"GRE REDIR LAG US Interface Number: %px\n",
+		ngcm, ngcm->hash_mode, ngcm->num_slaves,
+		ngcm->if_num);
+}
+
+/*
+ * nss_gre_redir_lag_us_log_add_hash_node_msg()
+ *	Log NSS GRE REDIR LAG US add hash node message.
+ */
+static void nss_gre_redir_lag_us_log_add_hash_node_msg(struct nss_gre_redir_lag_us_msg *ngm)
+{
+	struct nss_gre_redir_lag_us_add_hash_node_msg *ngam __maybe_unused = &ngm->msg.add_hash;
+	nss_trace("%px: NSS GRE REDIR LAG Add Hash Node Message:\n"
+		"GRE REDIR LAG US Interface Number: %d\n"
+		"GRE REDIR LAG US Source MAC: %px\n"
+		"GRE REDIR LAG US Destination MAC: %px\n",
+		ngam, ngam->if_num, ngam->src_mac,
+		ngam->dest_mac);
+}
+
+/*
+ * nss_gre_redir_lag_us_log_del_hash_node_msg()
+ *	Log NSS GRE REDIR LAG US del hash node message.
+ */
+static void nss_gre_redir_lag_us_log_del_hash_node_msg(struct nss_gre_redir_lag_us_msg *ngm)
+{
+	struct nss_gre_redir_lag_us_del_hash_node_msg *ngdm __maybe_unused = &ngm->msg.del_hash;
+	nss_trace("%px: NSS GRE REDIR LAG Del Hash Node Message:\n"
+		"GRE REDIR LAG US Source MAC: %px\n"
+		"GRE REDIR LAG US Destination MAC: %px\n",
+		ngdm, ngdm->src_mac,ngdm->dest_mac);
+}
+
+/*
+ * nss_gre_redir_lag_us_log_query_hash_node_msg()
+ *	Log NSS GRE REDIR LAG US query hash node message.
+ */
+static void nss_gre_redir_lag_us_log_query_hash_node_msg(struct nss_gre_redir_lag_us_msg *ngm)
+{
+	struct nss_gre_redir_lag_us_query_hash_node_msg *ngqm __maybe_unused = &ngm->msg.query_hash;
+	nss_trace("%px: NSS GRE REDIR LAG Query Hash Node Message:\n"
+		"GRE REDIR LAG US Source MAC: %px\n"
+		"GRE REDIR LAG US Destination MAC: %px\n"
+		"GRE REDIR LAG US Interface Number: %d\n",
+		ngqm, ngqm->src_mac, ngqm->dest_mac,
+		ngqm->ifnum);
+}
+
+/*
+ * nss_gre_redir_lag_us_log_verbose()
+ *	Log message contents.
+ */
+static void nss_gre_redir_lag_us_log_verbose(struct nss_gre_redir_lag_us_msg *ngm)
+{
+	switch (ngm->cm.type) {
+	case NSS_GRE_REDIR_LAG_US_CONFIG_MSG:
+		nss_gre_redir_lag_us_log_config_msg(ngm);
+		break;
+
+	case NSS_GRE_REDIR_LAG_US_ADD_HASH_NODE_MSG:
+		nss_gre_redir_lag_us_log_add_hash_node_msg(ngm);
+		break;
+
+	case NSS_GRE_REDIR_LAG_US_DEL_HASH_NODE_MSG:
+		nss_gre_redir_lag_us_log_del_hash_node_msg(ngm);
+		break;
+
+	case NSS_GRE_REDIR_LAG_US_QUERY_HASH_NODE_MSG:
+		nss_gre_redir_lag_us_log_query_hash_node_msg(ngm);
+		break;
+
+	case NSS_GRE_REDIR_LAG_US_CMN_STATS_SYNC_MSG:
+	case NSS_GRE_REDIR_LAG_US_DB_HASH_NODE_MSG:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", ngm);
+		break;
+	}
+}
+
+/*
+ * nss_gre_redir_lag_us_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_gre_redir_lag_us_log_tx_msg(struct nss_gre_redir_lag_us_msg *ngm)
+{
+	if (ngm->cm.type >= NSS_GRE_REDIR_LAG_US_MAX_MSG_TYPES) {
+		nss_warning("%px: Invalid message type\n", ngm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ngm, ngm->cm.type, nss_gre_redir_lag_us_log_message_types_str[ngm->cm.type]);
+	nss_gre_redir_lag_us_log_verbose(ngm);
+}
+
+/*
+ * nss_gre_redir_lag_us_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_gre_redir_lag_us_log_rx_msg(struct nss_gre_redir_lag_us_msg *ngm)
+{
+	if (ngm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ngm);
+		return;
+	}
+
+	if (ngm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ngm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ngm, ngm->cm.type,
+			nss_gre_redir_lag_us_log_message_types_str[ngm->cm.type],
+			ngm->cm.response, nss_cmn_response_str[ngm->cm.response]);
+		goto verbose;
+	}
+
+	if (ngm->cm.error >= NSS_GRE_REDIR_LAG_ERR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			ngm, ngm->cm.type, nss_gre_redir_lag_us_log_message_types_str[ngm->cm.type],
+			ngm->cm.response, nss_cmn_response_str[ngm->cm.response],
+			ngm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		ngm, ngm->cm.type, nss_gre_redir_lag_us_log_message_types_str[ngm->cm.type],
+		ngm->cm.response, nss_cmn_response_str[ngm->cm.response],
+		ngm->cm.error, nss_gre_redir_lag_us_log_error_response_types_str[ngm->cm.error]);
+
+verbose:
+	nss_gre_redir_lag_us_log_verbose(ngm);
+}
diff --git a/qca-nss-drv/nss_gre_redir_lag_us_log.h b/qca-nss-drv/nss_gre_redir_lag_us_log.h
new file mode 100644
index 0000000..cbda8d9
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_lag_us_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_GRE_REDIR_LAG_US_LOG_H__
+#define __NSS_GRE_REDIR_LAG_US_LOG_H__
+
+/*
+ * nss_gre_redir_lag_us_log.h
+ *	NSS GRE REDIR LAG US Log Header File
+ */
+
+/*
+ * nss_gre_redir_lag_us_log_tx_msg
+ *	Logs a gre redir lag us message that is sent to the NSS firmware.
+ */
+void nss_gre_redir_lag_us_log_tx_msg(struct nss_gre_redir_lag_us_msg *ngm);
+
+/*
+ * nss_gre_redir_lag_us_log_rx_msg
+ *	Logs a gre redir lag us message that is received from the NSS firmware.
+ */
+void nss_gre_redir_lag_us_log_rx_msg(struct nss_gre_redir_lag_us_msg *ngm);
+
+#endif /* __NSS_GRE_REDIR_LAG_US_LOG_H__ */
diff --git a/qca-nss-drv/nss_gre_redir_lag_us_stats.c b/qca-nss-drv/nss_gre_redir_lag_us_stats.c
new file mode 100644
index 0000000..2b291bf
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_lag_us_stats.c
@@ -0,0 +1,226 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_gre_redir_lag.h"
+#include "nss_gre_redir_lag_us_stats.h"
+#include "nss_gre_redir_lag_us_strings.h"
+
+#define NSS_GRE_REDIR_LAG_US_STATS_SYNC_PERIOD msecs_to_jiffies(4000)
+#define NSS_GRE_REDIR_LAG_US_STATS_SYNC_UDELAY 4000
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_gre_redir_lag_us_stats_notifier);
+
+extern struct nss_gre_redir_lag_us_cmn_ctx cmn_ctx;
+
+/*
+ * nss_gre_redir_lag_us_stats_get
+ *	Get the common upstream statistics.
+ */
+bool nss_gre_redir_lag_us_stats_get(struct nss_gre_redir_lag_us_tunnel_stats *cmn_stats, uint32_t index)
+{
+	if (index >= NSS_GRE_REDIR_LAG_MAX_NODE) {
+		nss_warning("Index is out of valid range %u\n", index);
+		return false;
+	}
+
+	spin_lock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+	if (!cmn_ctx.stats_ctx[index].valid) {
+		spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+		nss_warning("Common context not found for the index %u\n", index);
+		return false;
+	}
+
+	memcpy((void *)cmn_stats, (void *)&(cmn_ctx.stats_ctx[index].tun_stats), sizeof(*cmn_stats));
+	spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+	return true;
+}
+
+/*
+ * nss_gre_redir_lag_us_cmn_stats_read()
+ *	Read and copy stats to user buffer.
+ */
+static ssize_t nss_gre_redir_lag_us_cmn_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	/*
+	 * Max output lines = #stats +
+	 * few blank lines for banner printing + Number of Extra outputlines
+	 * for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_GRE_REDIR_LAG_US_STATS_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	struct nss_stats_data *data = fp->private_data;
+	struct nss_gre_redir_lag_us_tunnel_stats stats;
+	ssize_t bytes_read = 0;
+	size_t size_wr = 0;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	while (data->index < NSS_GRE_REDIR_LAG_MAX_NODE) {
+		if (nss_gre_redir_lag_us_stats_get(&stats, data->index)) {
+			break;
+		}
+
+		data->index++;
+	}
+
+	if (data->index == NSS_GRE_REDIR_LAG_MAX_NODE) {
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "gre_redir_lag_us stats", NSS_STATS_SINGLE_CORE);
+	size_wr += nss_stats_print("gre_redir_lag_us", NULL, NSS_STATS_SINGLE_INSTANCE, nss_gre_redir_lag_us_strings_stats,
+					&stats.rx_packets, NSS_GRE_REDIR_LAG_US_STATS_MAX, lbuf, size_wr, size_al);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	data->index++;
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_gre_redir_lag_us_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(gre_redir_lag_us_cmn)
+
+/*
+ * nss_gre_redir_lag_us_stats_dentry_create()
+ *	Create debugfs directory for stats.
+ */
+struct dentry *nss_gre_redir_lag_us_stats_dentry_create(void)
+{
+	struct dentry *gre_redir;
+	struct dentry *cmn_stats;
+
+	gre_redir = nss_gre_redir_get_dentry();
+	if (unlikely(!gre_redir)) {
+		nss_warning("Failed to retrieve directory entry qca-nss-drv/stats/gre_redir/\n");
+		return NULL;
+	}
+
+	cmn_stats = debugfs_create_file("lag_us_cmn_stats", 0400, gre_redir,
+			&nss_top_main, &nss_gre_redir_lag_us_cmn_stats_ops);
+	if (unlikely(!cmn_stats)) {
+		nss_warning("Failed to create qca-nss-drv/stats/gre_redir/lag_us_cmn_stats file\n");
+		return NULL;
+	}
+
+	return cmn_stats;
+}
+
+/*
+ * nss_gre_redir_lag_us_stats_sync()
+ *	Update synchonized statistics.
+ */
+void nss_gre_redir_lag_us_stats_sync(struct nss_ctx_instance *nss_ctx,
+				struct nss_gre_redir_lag_us_cmn_sync_stats_msg *ngss, uint32_t ifnum)
+{
+	int idx, j;
+	struct nss_gre_redir_lag_us_tunnel_stats *node_stats;
+
+	spin_lock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+	if (!nss_gre_redir_lag_us_get_node_idx(ifnum, &idx)) {
+		spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+		nss_warning("%px: Unable to update hash stats msg. Stats context not found.\n", nss_ctx);
+		return;
+	}
+
+	node_stats = &cmn_ctx.stats_ctx[idx].tun_stats;
+
+	node_stats->tx_packets += ngss->node_stats.tx_packets;
+	node_stats->tx_bytes += ngss->node_stats.tx_bytes;
+	node_stats->rx_packets += ngss->node_stats.rx_packets;
+	node_stats->rx_bytes += ngss->node_stats.rx_bytes;
+	for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+		node_stats->rx_dropped[j] += ngss->node_stats.rx_dropped[j];
+	}
+
+	node_stats->us_stats.amsdu_pkts += ngss->us_stats.amsdu_pkts;
+	node_stats->us_stats.amsdu_pkts_enqueued += ngss->us_stats.amsdu_pkts_enqueued;
+	node_stats->us_stats.amsdu_pkts_exceptioned += ngss->us_stats.amsdu_pkts_exceptioned;
+	node_stats->us_stats.exceptioned += ngss->us_stats.exceptioned;
+	node_stats->us_stats.freed += ngss->us_stats.freed;
+	node_stats->db_stats.add_attempt += ngss->db_stats.add_attempt;
+	node_stats->db_stats.add_success += ngss->db_stats.add_success;
+	node_stats->db_stats.add_fail_table_full += ngss->db_stats.add_fail_table_full;
+	node_stats->db_stats.add_fail_exists += ngss->db_stats.add_fail_exists;
+	node_stats->db_stats.del_attempt += ngss->db_stats.del_attempt;
+	node_stats->db_stats.del_success += ngss->db_stats.del_success;
+	node_stats->db_stats.del_fail_not_found += ngss->db_stats.del_fail_not_found;
+	spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+}
+
+/*
+ * nss_gre_redir_lag_us_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_gre_redir_lag_us_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_gre_redir_lag_us_stats_notification *stats_notify;
+	int idx;
+
+	stats_notify = kzalloc(sizeof(struct nss_gre_redir_lag_us_stats_notification), GFP_ATOMIC);
+	if (!stats_notify) {
+		nss_warning("Unable to allocate memory for stats notification\n");
+		return;
+	}
+
+	spin_lock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+	if (!nss_gre_redir_lag_us_get_node_idx(if_num, &idx)) {
+		spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+		nss_warning("%px: Unable to update hash stats msg. Stats context not found.\n", nss_ctx);
+		kfree(stats_notify);
+		return;
+	}
+
+	stats_notify->core_id = nss_ctx->id;
+	stats_notify->if_num = if_num;
+	memcpy(&(stats_notify->stats_ctx), &(cmn_ctx.stats_ctx[idx].tun_stats), sizeof(stats_notify->stats_ctx));
+	spin_unlock_bh(&cmn_ctx.nss_gre_redir_lag_us_stats_lock);
+	atomic_notifier_call_chain(&nss_gre_redir_lag_us_stats_notifier, NSS_STATS_EVENT_NOTIFY, stats_notify);
+	kfree(stats_notify);
+}
+
+/*
+ * nss_gre_redir_lag_us_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_gre_redir_lag_us_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_gre_redir_lag_us_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_gre_redir_lag_us_stats_unregister_notifier);
+
+/*
+ * nss_gre_redir_lag_us_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_gre_redir_lag_us_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_gre_redir_lag_us_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_gre_redir_lag_us_stats_register_notifier);
+
diff --git a/qca-nss-drv/nss_gre_redir_lag_us_stats.h b/qca-nss-drv/nss_gre_redir_lag_us_stats.h
new file mode 100644
index 0000000..9f22312
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_lag_us_stats.h
@@ -0,0 +1,50 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_GRE_REDIR_LAG_US_STATS_H__
+#define __NSS_GRE_REDIR_LAG_US_STATS_H__
+
+/*
+ * nss_gre_redir_lag_us_pvt_sync_stats
+ *	Hash statistics synchronization context.
+ */
+struct nss_gre_redir_lag_us_pvt_sync_stats {
+	struct delayed_work nss_gre_redir_lag_us_work;		/**< Delayed work per LAG US node. */
+	struct nss_gre_redir_lag_us_msg db_sync_msg;		/**< Hash statistics message. */
+	struct nss_gre_redir_lag_us_tunnel_stats tun_stats;	/**< GRE redirect LAG common statistics. */
+	nss_gre_redir_lag_us_msg_callback_t cb;			/**< Callback for hash query message. */
+	void *app_data;						/**< app_data for hash query message. */
+	uint32_t ifnum;						/**< NSS interface number. */
+	bool valid;						/**< Valid flag. */
+};
+
+/*
+ * Common context for stats update.
+ */
+struct nss_gre_redir_lag_us_cmn_ctx {
+	struct workqueue_struct *nss_gre_redir_lag_us_wq;		/**< Work queue. */
+	spinlock_t nss_gre_redir_lag_us_stats_lock;			/**< Spin lock. */
+	struct nss_gre_redir_lag_us_pvt_sync_stats stats_ctx[NSS_GRE_REDIR_LAG_MAX_NODE];
+};
+
+extern void nss_gre_redir_lag_us_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern bool nss_gre_redir_lag_us_get_node_idx(uint32_t ifnum, uint32_t *idx);
+extern bool nss_gre_redir_lag_us_verify_ifnum(uint32_t if_num);
+extern void nss_gre_redir_lag_us_stats_sync(struct nss_ctx_instance *nss_ctx,
+					struct nss_gre_redir_lag_us_cmn_sync_stats_msg *ngss, uint32_t ifnum);
+extern struct dentry *nss_gre_redir_lag_us_stats_dentry_create(void);
+
+#endif
diff --git a/qca-nss-drv/nss_gre_redir_lag_us_strings.c b/qca-nss-drv/nss_gre_redir_lag_us_strings.c
new file mode 100644
index 0000000..c1dca2b
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_lag_us_strings.c
@@ -0,0 +1,71 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_gre_redir_lag_us_strings.h"
+
+/*
+ * nss_gre_redir_lag_us_strings_stats
+ *	GRE REDIR LAG US common statistics strings.
+ */
+struct nss_stats_info nss_gre_redir_lag_us_strings_stats[NSS_GRE_REDIR_LAG_US_STATS_MAX] = {
+	{"rx_packets",			NSS_STATS_TYPE_COMMON},
+	{"rx_bytes",			NSS_STATS_TYPE_COMMON},
+	{"tx_packets",			NSS_STATS_TYPE_COMMON},
+	{"tx_bytes",			NSS_STATS_TYPE_COMMON},
+	{"rx_dropped_0",		NSS_STATS_TYPE_DROP},
+	{"rx_dropped_1",		NSS_STATS_TYPE_DROP},
+	{"rx_dropped_2",		NSS_STATS_TYPE_DROP},
+	{"rx_dropped_3",		NSS_STATS_TYPE_DROP},
+	{"Amsdu pkts",			NSS_STATS_TYPE_SPECIAL},
+	{"Amsdu pkts enqueued",		NSS_STATS_TYPE_SPECIAL},
+	{"Amsdu pkts exceptioned",	NSS_STATS_TYPE_EXCEPTION},
+	{"Exceptioned",			NSS_STATS_TYPE_EXCEPTION},
+	{"Freed",			NSS_STATS_TYPE_SPECIAL},
+	{"add attempt",			NSS_STATS_TYPE_SPECIAL},
+	{"add success",			NSS_STATS_TYPE_SPECIAL},
+	{"add fail table full",		NSS_STATS_TYPE_SPECIAL},
+	{"add fail exists",		NSS_STATS_TYPE_SPECIAL},
+	{"del attempt",			NSS_STATS_TYPE_SPECIAL},
+	{"del success",			NSS_STATS_TYPE_SPECIAL},
+	{"del fail not found",		NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_gre_redir_lag_us_strings_read()
+ *	Read gre_redir_lag_us statistics names
+ */
+static ssize_t nss_gre_redir_lag_us_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_gre_redir_lag_us_strings_stats, NSS_GRE_REDIR_LAG_US_STATS_MAX);
+}
+
+/*
+ * nss_gre_redir_lag_us_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(gre_redir_lag_us);
+
+/*
+ * nss_gre_redir_lag_us_strings_dentry_create()
+ *	Create gre_redir_lag_us statistics strings debug entry.
+ */
+void nss_gre_redir_lag_us_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("gre_redir_lag_us", &nss_gre_redir_lag_us_strings_ops);
+}
+
diff --git a/qca-nss-drv/nss_gre_redir_lag_us_strings.h b/qca-nss-drv/nss_gre_redir_lag_us_strings.h
new file mode 100644
index 0000000..74c1054
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_lag_us_strings.h
@@ -0,0 +1,25 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#ifndef __NSS_GRE_REDIR_LAG_US_STRINGS_H
+#define __NSS_GRE_REDIR_LAG_US_STRINGS_H
+
+#include "nss_gre_redir_lag_us_stats.h"
+
+extern struct nss_stats_info nss_gre_redir_lag_us_strings_stats[NSS_GRE_REDIR_LAG_US_STATS_MAX];
+extern void nss_gre_redir_lag_us_strings_dentry_create(void);
+
+#endif /* __NSS_GRE_REDIR_LAG_US_STRINGS_H */
diff --git a/qca-nss-drv/nss_gre_redir_log.c b/qca-nss-drv/nss_gre_redir_log.c
new file mode 100644
index 0000000..1ac6afb
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_log.c
@@ -0,0 +1,242 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_gre_redir_log.c
+ *	NSS GRE REDIR logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_gre_redir_log_message_types_str
+ *	NSS GRE REDIR message strings
+ */
+static int8_t *nss_gre_redir_log_message_types_str[NSS_GRE_REDIR_MAX_MSG_TYPES] __maybe_unused = {
+	"GRE REDIR Tunnel Inner Configure",
+	"GRE REDIR Tunnel Outer Configure",
+	"GRE REDIR Interface Map",
+	"GRE REDIR Interface Unmap",
+	"GRE REDIR SJACK Map",
+	"GRE REDIR SJACK Unmap",
+	"GRE REDIR Stats Sync",
+	"GRE REDIR Exception DS register cb"
+};
+
+/*
+ * nss_gre_redir_log_inner_configure_msg()
+ *	Log NSS GRE Redir inner configure message.
+ */
+static void nss_gre_redir_log_inner_configure_msg(struct nss_gre_redir_msg *ngm)
+{
+	struct nss_gre_redir_inner_configure_msg *ngicm __maybe_unused = &ngm->msg.inner_configure;
+	nss_trace("%px: NSS GRE Redir Inner Configure message"
+		"GRE REDIR IP Header Type: %d\n"
+		"GRE REDIR Source IP: %px\n"
+		"GRE REDIR Destination IP: %px\n"
+		"GRE REDIR Outer Interface: %d\n"
+		"GRE REDIR Do not Fragment: %d\n"
+		"GRE REDIR IP TTL: %d\n"
+		"GRE REDIR Version: %d\n",
+		ngicm, ngicm->ip_hdr_type,
+		ngicm->ip_src_addr, ngicm->ip_dest_addr,
+		ngicm->except_outerif, ngicm->ip_df_policy,
+		ngicm->ip_ttl, ngicm->gre_version);
+}
+
+/*
+ * nss_gre_redir_log_interface_map_msg()
+ *	Log NSS GRE Redir interface map message.
+ */
+static void nss_gre_redir_log_interface_map_msg(struct nss_gre_redir_msg *ngm)
+{
+	struct nss_gre_redir_interface_map_msg *ngicm __maybe_unused = &ngm->msg.interface_map;
+	nss_trace("%px: NSS GRE Redir Interface Map message"
+		"GRE REDIR NSS VAP Interface: %d\n"
+		"GRE REDIR Next Hop NSS Interface: %d\n"
+		"GRE REDIR Radio ID: %d\n"
+		"GRE REDIR VAP ID: %d\n"
+		"GRE REDIR LAG Flags: %x\n"
+		"GRE REDIR Tunnel Type: %d\n"
+		"GRE REDIR IPsec pattern: %d\n",
+		ngicm, ngicm->vap_nssif,
+		ngicm->nexthop_nssif, ngicm->radio_id,
+		ngicm->vap_id, ngicm->lag_en,
+		ngicm->tunnel_type, ngicm->ipsec_pattern);
+}
+
+/*
+ * nss_gre_redir_log_interface_unmap_msg()
+ *	Log NSS GRE Redir interface unmap message.
+ */
+static void nss_gre_redir_log_interface_unmap_msg(struct nss_gre_redir_msg *ngm)
+{
+	struct nss_gre_redir_interface_unmap_msg *ngicm __maybe_unused = &ngm->msg.interface_unmap;
+	nss_trace("%px: NSS GRE Redir Interface Map message"
+		"GRE REDIR NSS VAP Interface: %d\n"
+		"GRE REDIR Radio ID: %d\n"
+		"GRE REDIR VAP ID: %d\n",
+		ngicm, ngicm->vap_nssif,
+		ngicm->radio_id, ngicm->vap_id);
+}
+
+/*
+ * nss_gre_redir_log_sjack_map_msg()
+ *	Log NSS GRE Redir interface map message.
+ */
+static void nss_gre_redir_log_sjack_map_msg(struct nss_gre_redir_msg *ngm)
+{
+	struct nss_gre_redir_sjack_map_msg *ngscm __maybe_unused = &ngm->msg.sjack_map;
+	nss_trace("%px: NSS GRE Redir SJACK Map message"
+		"GRE REDIR Eth NSS Interface: %d\n"
+		"GRE REDIR Eth Interface ID: %d\n"
+		"GRE REDIR IPSec pattern: %x\n",
+		ngscm, ngscm->eth_nssif,
+		ngscm->eth_id, ngscm->ipsec_pattern);
+}
+
+/*
+ * nss_gre_redir_log_sjack_unmap_msg()
+ *	Log NSS GRE Redir interface unmap message.
+ */
+static void nss_gre_redir_log_sjack_unmap_msg(struct nss_gre_redir_msg *ngm)
+{
+	struct nss_gre_redir_sjack_unmap_msg *ngscm __maybe_unused = &ngm->msg.sjack_unmap;
+	nss_trace("%px: NSS GRE Redir SJACK Map message"
+		"GRE REDIR Eth NSS Interface: %d\n"
+		"GRE REDIR Eth Interface ID: %d\n",
+		ngscm, ngscm->eth_nssif,
+		ngscm->eth_id);
+}
+
+/*
+ * nss_gre_redir_log_outer_configure_msg()
+ *	Log NSS GRE Redir outer configure message.
+ */
+static void nss_gre_redir_log_outer_configure_msg(struct nss_gre_redir_msg *ngm)
+{
+	struct nss_gre_redir_outer_configure_msg *ngocm __maybe_unused = &ngm->msg.outer_configure;
+	nss_trace("%px: NSS GRE Redir Outer Configure message"
+		"GRE REDIR IP Header Type: %d\n"
+		"GRE REDIR Host Inner Interface: %d\n"
+		"GRE REDIR NSS Inner Interface: %d\n"
+		"GRE REDIR SJACK Inner Interface: %d\n"
+		"GRE REDIR RPS: %d\n"
+		"GRE REDIR RPS Valid: %d\n",
+		ngocm, ngocm->ip_hdr_type,
+		ngocm->except_hostif, ngocm->except_offlif,
+		ngocm->except_sjackif, ngocm->rps_hint,
+		ngocm->rps_hint_valid);
+}
+
+/*
+ * nss_gre_redir_log_exception_ds_reg_cb_msg()
+ *	Log GRE exception downstream callback registration message.
+ */
+static void nss_gre_redir_log_exception_ds_reg_cb_msg(struct nss_gre_redir_msg *ngm)
+{
+	struct nss_gre_redir_exception_ds_reg_cb_msg *exception_ds_configure __maybe_unused = &ngm->msg.exception_ds_configure;
+	nss_trace("%px: NSS GRE redir exception completion callback registration message\n"
+			"vap_if_num: %d\n", ngm, exception_ds_configure->dst_vap_nssif);
+}
+
+/*
+ * nss_gre_redir_log_verbose()
+ *	Log message contents.
+ */
+static void nss_gre_redir_log_verbose(struct nss_gre_redir_msg *ngm)
+{
+	switch (ngm->cm.type) {
+	case NSS_GRE_REDIR_TX_TUNNEL_INNER_CONFIGURE_MSG:
+		nss_gre_redir_log_inner_configure_msg(ngm);
+		break;
+
+	case NSS_GRE_REDIR_TX_TUNNEL_OUTER_CONFIGURE_MSG:
+		nss_gre_redir_log_outer_configure_msg(ngm);
+		break;
+
+	case NSS_GRE_REDIR_TX_INTERFACE_MAP_MSG:
+		nss_gre_redir_log_interface_map_msg(ngm);
+		break;
+
+	case NSS_GRE_REDIR_TX_INTERFACE_UNMAP_MSG:
+		nss_gre_redir_log_interface_unmap_msg(ngm);
+		break;
+
+	case NSS_GRE_REDIR_TX_SJACK_MAP_MSG:
+		nss_gre_redir_log_sjack_map_msg(ngm);
+		break;
+
+	case NSS_GRE_REDIR_TX_SJACK_UNMAP_MSG:
+		nss_gre_redir_log_sjack_unmap_msg(ngm);
+		break;
+
+	case NSS_GRE_REDIR_RX_STATS_SYNC_MSG:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	case NSS_GRE_REDIR_EXCEPTION_DS_REG_CB_MSG:
+		nss_gre_redir_log_exception_ds_reg_cb_msg(ngm);
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", ngm);
+		break;
+	}
+}
+
+/*
+ * nss_gre_redir_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_gre_redir_log_tx_msg(struct nss_gre_redir_msg *ngm)
+{
+	if (ngm->cm.type >= NSS_GRE_REDIR_MAX_MSG_TYPES) {
+		nss_warning("%px: Invalid message type\n", ngm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ngm, ngm->cm.type, nss_gre_redir_log_message_types_str[ngm->cm.type]);
+	nss_gre_redir_log_verbose(ngm);
+}
+
+/*
+ * nss_gre_redir_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_gre_redir_log_rx_msg(struct nss_gre_redir_msg *ngm)
+{
+	if (ngm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ngm);
+		return;
+	}
+
+	if (ngm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ngm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ngm, ngm->cm.type,
+			nss_gre_redir_log_message_types_str[ngm->cm.type],
+			ngm->cm.response, nss_cmn_response_str[ngm->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		ngm, ngm->cm.type, nss_gre_redir_log_message_types_str[ngm->cm.type],
+		ngm->cm.response, nss_cmn_response_str[ngm->cm.response]);
+
+verbose:
+	nss_gre_redir_log_verbose(ngm);
+}
diff --git a/qca-nss-drv/nss_gre_redir_log.h b/qca-nss-drv/nss_gre_redir_log.h
new file mode 100644
index 0000000..7e1fb79
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_log.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_GRE_REDIR_LOG_H
+#define __NSS_GRE_REDIR_LOG_H
+
+/*
+ * nss_gre_redir_log.h
+ *	NSS GRE REDIR Log header file.
+ */
+
+/*
+ * Logger APIs
+ */
+
+/*
+ * nss_gre_redir_log_tx_msg
+ *	Logs a gre_redir message that is sent to the NSS firmware.
+ */
+void nss_gre_redir_log_tx_msg(struct nss_gre_redir_msg *ngm);
+
+/*
+ * nss_gre_redir_log_rx_msg
+ *	Logs a gre_redir message that is received from the NSS firmware.
+ */
+void nss_gre_redir_log_rx_msg(struct nss_gre_redir_msg *ngm);
+
+#endif /* __NSS_GRE_REDIR_LOG_H */
diff --git a/qca-nss-drv/nss_gre_redir_mark.c b/qca-nss-drv/nss_gre_redir_mark.c
new file mode 100644
index 0000000..0b8524f
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_mark.c
@@ -0,0 +1,341 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_gre_redir_mark_strings.h"
+#include "nss_gre_redir_mark_stats.h"
+#include "nss_gre_redir_mark_log.h"
+#define NSS_GRE_REDIR_MARK_TX_TIMEOUT 3000 /* 3 Seconds */
+
+/*
+ * Private data structure for handling synchronous messaging.
+ */
+static struct {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+} nss_gre_redir_mark_pvt;
+
+/*
+ * nss_gre_redir_mark_msg_sync_callback()
+ *	Callback to handle the completion of HLOS-->NSS messages.
+ */
+static void nss_gre_redir_mark_msg_sync_callback(void *app_data, struct nss_gre_redir_mark_msg *nim)
+{
+	nss_gre_redir_mark_pvt.response = NSS_TX_SUCCESS;
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("GRE mark Error response %d\n", nim->cm.response);
+		nss_gre_redir_mark_pvt.response = NSS_TX_FAILURE;
+	}
+
+	complete(&nss_gre_redir_mark_pvt.complete);
+}
+
+/*
+ * nss_gre_redir_mark_handler()
+ *	Handle NSS to HLOS messages for GRE redir mark
+ */
+static void nss_gre_redir_mark_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, void *app_data)
+{
+	struct nss_gre_redir_mark_msg *ngrm = (struct nss_gre_redir_mark_msg *)ncm;
+	nss_gre_redir_mark_msg_callback_t cb;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_GRE_REDIR_MARK_MSG_MAX) {
+		nss_warning("%px: received invalid message %d for GRE redir mark interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_gre_redir_mark_msg)) {
+		nss_warning("%px: length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Trace messages.
+	 */
+	nss_gre_redir_mark_log_rx_msg((struct nss_gre_redir_mark_msg *)ncm);
+
+	if (ncm->type == NSS_GRE_REDIR_MARK_STATS_SYNC_MSG) {
+		nss_gre_redir_mark_stats_sync(nss_ctx, ncm->interface, &ngrm->msg.stats_sync);
+		nss_gre_redir_mark_stats_notify(nss_ctx, ncm->interface);
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, GRE redir mark sends all notify messages
+	 * to the same callback/app_data. The app data here represent the netdevice of the GRE redir mark
+	 * interface.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->subsys_dp_register[ncm->interface].ndev;
+	}
+
+	/*
+	 * load and call the registered synchronous message callback.
+	 */
+	cb = (nss_gre_redir_mark_msg_callback_t)ncm->cb;
+	if (unlikely(!cb)) {
+		return;
+	}
+
+	cb((void *)ncm->app_data, ncm);
+}
+
+/*
+ * nss_gre_redir_mark_reg_cb()
+ *	Configure a callback on VAP.
+ */
+nss_tx_status_t nss_gre_redir_mark_reg_cb(int ifnum,
+                struct nss_gre_redir_mark_register_cb_msg *ngrcm)
+{
+        struct nss_gre_redir_mark_msg config;
+        struct nss_ctx_instance *nss_ctx __maybe_unused = nss_gre_redir_mark_get_context();
+        nss_tx_status_t status;
+        uint32_t vap_type;
+        uint32_t len = sizeof(struct nss_gre_redir_mark_register_cb_msg);
+
+        if (!nss_ctx) {
+                nss_warning("Unable to retrieve NSS context.\n");
+                return NSS_TX_FAILURE_BAD_PARAM;
+        }
+
+        vap_type = nss_dynamic_interface_get_type(nss_ctx, ngrcm->nss_if_num);
+        if ((vap_type != NSS_DYNAMIC_INTERFACE_TYPE_VAP)) {
+                nss_warning("%px: Incorrect type for vap interface type = %u", nss_ctx, vap_type);
+                return NSS_TX_FAILURE_BAD_PARAM;
+        }
+
+        /*
+         * Configure the node
+         */
+        nss_cmn_msg_init(&config.cm, NSS_GRE_REDIR_MARK_INTERFACE, NSS_GRE_REDIR_MARK_REG_CB_MSG, len, NULL, NULL);
+        config.msg.reg_cb_msg.nss_if_num = ngrcm->nss_if_num;
+
+        status = nss_gre_redir_mark_tx_msg_sync(nss_ctx, &config);
+        if (status != NSS_TX_SUCCESS) {
+                nss_warning("%px: Unable to register callback from GRE redir mark interface %d\n", nss_ctx, ifnum);
+        }
+
+        return status;
+}
+EXPORT_SYMBOL(nss_gre_redir_mark_reg_cb);
+
+/*
+ * nss_gre_redir_mark_tx_msg()
+ *	Transmit a GRE MARK configuration message to NSS FW.
+ */
+nss_tx_status_t nss_gre_redir_mark_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_mark_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_gre_redir_mark_log_tx_msg(msg);
+
+	/*
+	 * interface should be of type of redir mark
+	 */
+	if (ncm->interface != NSS_GRE_REDIR_MARK_INTERFACE) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_GRE_REDIR_MARK_MSG_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_gre_redir_mark_tx_msg);
+
+/*
+ * nss_gre_redir_mark_tx_msg_sync()
+ *	Transmit a GRE redir mark message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_gre_redir_mark_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_redir_mark_msg *ngrm)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	/*
+	 * Decrease the semaphore count to send the message exclusively.
+	 */
+	down(&nss_gre_redir_mark_pvt.sem);
+	ngrm->cm.cb = (nss_ptr_t)nss_gre_redir_mark_msg_sync_callback;
+	ngrm->cm.app_data = (nss_ptr_t)NULL;
+	status = nss_gre_redir_mark_tx_msg(nss_ctx, ngrm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: GRE redir mark tx_msg failed\n", nss_ctx);
+		up(&nss_gre_redir_mark_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&nss_gre_redir_mark_pvt.complete, msecs_to_jiffies(NSS_GRE_REDIR_MARK_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: GRE redir mark message tx sync failed due to timeout\n", nss_ctx);
+		nss_gre_redir_mark_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = nss_gre_redir_mark_pvt.response;
+	up(&nss_gre_redir_mark_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_gre_redir_mark_tx_msg_sync);
+
+/*
+ * nss_gre_redir_mark_tx_buf()
+ *	Send packet to GRE redir mark interface owned by NSS.
+ */
+nss_tx_status_t nss_gre_redir_mark_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, uint32_t if_num)
+{
+	nss_trace("%px: GRE redir mark If Tx packet, interface id:%d, data=%px", nss_ctx, if_num, os_buf->data);
+
+	/*
+	 * We expect Tx packets to the GRE redir mark interface only.
+	 */
+	if (if_num != NSS_GRE_REDIR_MARK_INTERFACE) {
+		nss_warning("%px: Invalid interface:%d for GRE redir mark packets\n", nss_ctx, if_num);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	return nss_core_send_packet(nss_ctx, os_buf, if_num, 0);
+}
+EXPORT_SYMBOL(nss_gre_redir_mark_tx_buf);
+
+/*
+ * nss_gre_redir_mark_get_context()
+ *	Return NSS GRE redir mark context.
+ */
+struct nss_ctx_instance *nss_gre_redir_mark_get_context(void)
+{
+	return &nss_top_main.nss[nss_top_main.gre_redir_mark_handler_id];
+}
+EXPORT_SYMBOL(nss_gre_redir_mark_get_context);
+
+/*
+ * nss_gre_redir_mark_unregister_if()
+ *	Unregister dynamic node for GRE_REDIR_MARK redir.
+ */
+bool nss_gre_redir_mark_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx __maybe_unused = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.gre_redir_handler_id];
+	struct net_device *dev;
+	uint32_t status;
+
+	nss_assert(nss_ctx);
+	nss_assert(if_num == NSS_GRE_REDIR_MARK_INTERFACE);
+
+	dev = nss_cmn_get_interface_dev(nss_ctx, if_num);
+
+	BUG_ON(!dev);
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+	status = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to unregister handler for gre_redir_mark interface %d with NSS core\n",
+				nss_ctx, if_num);
+		return false;
+	}
+
+	nss_ctx->nss_rx_interface_handlers[if_num].msg_cb = NULL;
+	return true;
+}
+EXPORT_SYMBOL(nss_gre_redir_mark_unregister_if);
+
+/*
+ * nss_gre_redir_mark_register_if()
+ *	Register staticr GRE redir mark interface with data-plane.
+ */
+struct nss_ctx_instance *nss_gre_redir_mark_register_if(struct net_device *netdev, uint32_t if_num,
+		nss_gre_redir_mark_data_callback_t cb_func_data, nss_gre_redir_mark_msg_callback_t cb_func_msg,
+		uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.gre_redir_handler_id];
+	uint32_t status;
+
+	nss_assert(nss_ctx);
+	nss_assert(if_num == NSS_GRE_REDIR_MARK_INTERFACE);
+
+	/*
+	 * Registering the interface with network data path.
+	 */
+	nss_core_register_subsys_dp(nss_ctx, if_num, cb_func_data, NULL, NULL, netdev, features);
+	status = nss_core_register_msg_handler(nss_ctx, NSS_GRE_REDIR_MARK_INTERFACE, cb_func_msg);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to register handler for gre_redir_mark interface %d with NSS core\n",
+				nss_ctx, if_num);
+		return NULL;
+	}
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_gre_redir_mark_register_if);
+
+/*
+ * nss_gre_redir_mark_get_device()
+ *	Gets the original device from probe.
+ */
+struct device *nss_gre_redir_mark_get_device(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_redir_mark_get_context();
+	return nss_ctx->dev;
+}
+EXPORT_SYMBOL(nss_gre_redir_mark_get_device);
+
+/*
+ * nss_gre_redir_mark_register_handler()
+ *	Register GRE redir mark and register handler
+ */
+void nss_gre_redir_mark_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_redir_mark_get_context();
+	struct dentry *gre_redir_mark_dentry = NULL;
+	uint32_t status = NSS_CORE_STATUS_FAILURE;
+
+	/*
+	 * Create the debug fs entry for the stats.
+	 */
+	gre_redir_mark_dentry = nss_gre_redir_mark_stats_dentry_create();
+	if (!gre_redir_mark_dentry) {
+		nss_warning("%px: Not able to create debugfs entry\n", nss_ctx);
+		return;
+	}
+
+	nss_gre_redir_mark_strings_dentry_create();
+	sema_init(&nss_gre_redir_mark_pvt.sem, 1);
+	init_completion(&nss_gre_redir_mark_pvt.complete);
+
+	nss_info("nss_gre_redir_mark_register_handler\n");
+	status = nss_core_register_handler(nss_ctx, NSS_GRE_REDIR_MARK_INTERFACE, nss_gre_redir_mark_handler, NULL);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		debugfs_remove_recursive(gre_redir_mark_dentry);
+		gre_redir_mark_dentry = NULL;
+		nss_warning("%px: Not able to register handler for GRE redir mark with NSS core\n", nss_ctx);
+		return;
+	}
+}
diff --git a/qca-nss-drv/nss_gre_redir_mark_log.c b/qca-nss-drv/nss_gre_redir_mark_log.c
new file mode 100644
index 0000000..580c5a8
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_mark_log.c
@@ -0,0 +1,119 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_gre_redir_mark_log_message_types_str
+ *	GRE redir mark message strings
+ */
+static int8_t *nss_gre_redir_mark_log_message_types_str[NSS_GRE_REDIR_MARK_MSG_MAX] __maybe_unused = {
+	"GRE redir mark register callback message",
+	"GRE redir mark statistics synchronization"
+};
+
+/*
+ * nss_gre_redir_mark_log_error_response_types_str
+ *	Strings for error types for GRE redir mark messages
+ */
+static int8_t *nss_gre_redir_mark_log_error_response_types_str[NSS_GRE_REDIR_MARK_ERROR_TYPE_MAX] __maybe_unused = {
+	"GRE redir mark No error",
+	"GRE redir mark Invalid interface for callback registration",
+	"GRE redir mark Invalid ethertype for Tx interface"
+};
+
+/*
+ * nss_gre_redir_mark_log_reg_cb_msg()
+ *	Log NSS GRE redir mark configuration message
+ */
+static void nss_gre_redir_mark_log_reg_cb_msg(struct nss_gre_redir_mark_msg *ncm)
+{
+	struct nss_gre_redir_mark_register_cb_msg *reg_cb_msg __maybe_unused = &ncm->msg.reg_cb_msg;
+	nss_trace("%px: NSS GRE redir mark callback registration message \n"
+			"nss_if_num: %d\n", ncm, reg_cb_msg->nss_if_num);
+}
+
+/*
+ * nss_gre_redir_mark_log_verbose()
+ *	Log message contents.
+ */
+static void nss_gre_redir_mark_log_verbose(struct nss_gre_redir_mark_msg *ncm)
+{
+	switch (ncm->cm.type) {
+	case NSS_GRE_REDIR_MARK_REG_CB_MSG:
+		nss_gre_redir_mark_log_reg_cb_msg(ncm);
+		break;
+
+	case NSS_GRE_REDIR_MARK_STATS_SYNC_MSG:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", ncm);
+		break;
+	}
+}
+
+/*
+ * nss_gre_redir_mark_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_gre_redir_mark_log_tx_msg(struct nss_gre_redir_mark_msg *ngm)
+{
+	if (ngm->cm.type >= NSS_GRE_REDIR_MARK_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", ngm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ngm, ngm->cm.type, nss_gre_redir_mark_log_message_types_str[ngm->cm.type]);
+	nss_gre_redir_mark_log_verbose(ngm);
+}
+/*
+ * nss_gre_redir_mark_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_gre_redir_mark_log_rx_msg(struct nss_gre_redir_mark_msg *ncm)
+{
+	if (ncm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ncm);
+		return;
+	}
+
+	if (ncm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ncm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ncm, ncm->cm.type,
+			nss_gre_redir_mark_log_message_types_str[ncm->cm.type],
+			ncm->cm.response, nss_cmn_response_str[ncm->cm.response]);
+		goto verbose;
+	}
+
+	if (ncm->cm.error >= NSS_GRE_REDIR_MARK_ERROR_TYPE_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			ncm, ncm->cm.type, nss_gre_redir_mark_log_message_types_str[ncm->cm.type],
+			ncm->cm.response, nss_cmn_response_str[ncm->cm.response],
+			ncm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		ncm, ncm->cm.type, nss_gre_redir_mark_log_message_types_str[ncm->cm.type],
+		ncm->cm.response, nss_cmn_response_str[ncm->cm.response],
+		ncm->cm.error, nss_gre_redir_mark_log_error_response_types_str[ncm->cm.error]);
+
+verbose:
+	nss_gre_redir_mark_log_verbose(ncm);
+}
diff --git a/qca-nss-drv/nss_gre_redir_mark_log.h b/qca-nss-drv/nss_gre_redir_mark_log.h
new file mode 100644
index 0000000..27e2ffb
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_mark_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_GRE_REDIR_MARK_LOG_H__
+#define __NSS_GRE_REDIR_MARK_LOG_H__
+
+/*
+ * nss_gre_redir_mark_log.h
+ *	NSS GRE_REDIR_MARK Log Header File.
+ */
+
+/*
+ * nss_gre_redir_mark_log_tx_msg
+ *	Logs GRE_REDIR_MARK message that is sent to the NSS firmware.
+ */
+void nss_gre_redir_mark_log_tx_msg(struct nss_gre_redir_mark_msg *ncm);
+
+/*
+ * nss_gre_redir_mark_log_rx_msg
+ *	Logs GRE_REDIR_MARK message that is received from the NSS firmware.
+ */
+void nss_gre_redir_mark_log_rx_msg(struct nss_gre_redir_mark_msg *ncm);
+
+#endif /* __NSS_GRE_REDIR_MARK_LOG_H__ */
diff --git a/qca-nss-drv/nss_gre_redir_mark_stats.c b/qca-nss-drv/nss_gre_redir_mark_stats.c
new file mode 100644
index 0000000..da0f646
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_mark_stats.c
@@ -0,0 +1,230 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_stats.h"
+#include "nss_gre_redir_mark.h"
+#include "nss_gre_redir_mark_stats.h"
+#include "nss_gre_redir_mark_strings.h"
+
+#define NSS_GRE_REDIR_MARK_STATS_STR_LEN 50
+#define NSS_GRE_REDIR_MARK_STATS_LEN ((NSS_GRE_REDIR_MARK_STATS_MAX + 7 ) * NSS_GRE_REDIR_MARK_STATS_STR_LEN)
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_gre_redir_mark_stats_notifier);
+
+/*
+ * Spinlock to protect GRE redirect mark statistics update/read
+ */
+DEFINE_SPINLOCK(nss_gre_redir_mark_stats_lock);
+
+/*
+ * Global GRE redirect mark stats structure.
+ */
+struct nss_gre_redir_mark_stats gre_mark_stats;
+
+/*
+ * nss_gre_redir_mark_stats_get()
+ *	Get gre_redir tunnel stats.
+ */
+bool nss_gre_redir_mark_stats_get(struct nss_gre_redir_mark_stats *stats_mem)
+{
+	if (!stats_mem) {
+		nss_warning("No memory to copy GRE redir mark stats");
+		return false;
+	}
+
+	/*
+	 * Copy the GRE redir mark stats in the memory.
+	 */
+	spin_lock_bh(&nss_gre_redir_mark_stats_lock);
+	memcpy(stats_mem, &gre_mark_stats, sizeof(struct nss_gre_redir_mark_stats));
+	spin_unlock_bh(&nss_gre_redir_mark_stats_lock);
+	return true;
+}
+EXPORT_SYMBOL(nss_gre_redir_mark_stats_get);
+
+/**
+ * nss_gre_redir_mark_stats_read()
+ *	READ GRE redir mark stats.
+ */
+static ssize_t nss_gre_redir_mark_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	/*
+	 * Max output lines = #stats +
+	 * few blank lines for banner printing + Number of Extra outputlines
+	 * for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_GRE_REDIR_MARK_STATS_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	struct nss_gre_redir_mark_stats stats;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	bool isthere;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	/*
+	 * If GRE redir mark does not exists, then (isthere) will be false.
+	 */
+	isthere = nss_gre_redir_mark_stats_get(&stats);
+	if (!isthere) {
+		nss_warning("Could not get GRE redirect stats");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "gre_redir_mark stats", NSS_STATS_SINGLE_CORE);
+	size_wr += nss_stats_print("gre_redir_mark", NULL, NSS_STATS_SINGLE_INSTANCE, nss_gre_redir_mark_strings_stats,
+					stats.stats, NSS_GRE_REDIR_MARK_STATS_MAX, lbuf, size_wr, size_al);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_gre_redir_mark_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(gre_redir_mark)
+
+/*
+ * nss_gre_redir_mark_stats_dentry_create()
+ *	Create debugfs directory entry for stats.
+ */
+struct dentry *nss_gre_redir_mark_stats_dentry_create(void)
+{
+	struct dentry *gre_redir_mark;
+
+	gre_redir_mark = debugfs_create_file("gre_redir_mark", 0400, nss_top_main.stats_dentry,
+			&nss_top_main, &nss_gre_redir_mark_stats_ops);
+	if (unlikely(!gre_redir_mark)) {
+		nss_warning("Failed to create file entry qca-nss-drv/stats/gre_redir_mark/\n");
+		return NULL;
+	}
+
+	return gre_redir_mark;
+}
+
+/*
+ * nss_gre_redir_mark_stats_sync()
+ *	Update GRE redir mark stats.
+ */
+void nss_gre_redir_mark_stats_sync(struct nss_ctx_instance *nss_ctx, int if_num, struct nss_gre_redir_mark_stats_sync_msg *ngss)
+{
+	int i;
+	struct net_device *dev;
+	dev = nss_cmn_get_interface_dev(nss_ctx, if_num);
+	if (!dev) {
+		nss_warning("%px: Unable to find net device for the interface %d\n", nss_ctx, if_num);
+		return;
+	}
+
+	if (if_num != NSS_GRE_REDIR_MARK_INTERFACE) {
+		nss_warning("%px: Unknown type for interface %d\n", nss_ctx, if_num);
+		return;
+	}
+
+	/*
+	 * Update the stats in exclusive mode to prevent the read from the process
+	 * context through debug fs.
+	 */
+	spin_lock_bh(&nss_gre_redir_mark_stats_lock);
+
+	/*
+	 * Update the common node stats
+	 */
+	gre_mark_stats.stats[NSS_STATS_NODE_TX_PKTS] += ngss->node_stats.tx_packets;
+	gre_mark_stats.stats[NSS_STATS_NODE_TX_BYTES] += ngss->node_stats.tx_bytes;
+	gre_mark_stats.stats[NSS_STATS_NODE_RX_PKTS] += ngss->node_stats.rx_packets;
+	gre_mark_stats.stats[NSS_STATS_NODE_RX_BYTES] += ngss->node_stats.rx_bytes;
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		gre_mark_stats.stats[NSS_STATS_NODE_RX_QUEUE_0_DROPPED + i] += ngss->node_stats.rx_dropped[i];
+	}
+
+	/*
+	 * Update the GRE redir mark specific stats
+	 */
+	gre_mark_stats.stats[NSS_GRE_REDIR_MARK_STATS_HLOS_MAGIC_FAILED] += ngss->hlos_magic_fail;
+	gre_mark_stats.stats[NSS_GRE_REDIR_MARK_STATS_INV_DST_IF_DROPS] += ngss->invalid_dst_drop;
+	gre_mark_stats.stats[NSS_GRE_REDIR_MARK_STATS_DST_IF_ENQUEUE] += ngss->dst_enqueue_success;
+	gre_mark_stats.stats[NSS_GRE_REDIR_MARK_STATS_DST_IF_ENQUEUE_DROPS] += ngss->dst_enqueue_drop;
+	gre_mark_stats.stats[NSS_GRE_REDIR_MARK_STATS_INV_APPID] += ngss->inv_appid;
+	gre_mark_stats.stats[NSS_GRE_REDIR_MARK_STATS_HEADROOM_UNAVAILABLE] += ngss->headroom_unavail;
+	gre_mark_stats.stats[NSS_GRE_REDIR_MARK_STATS_TX_COMPLETION_SUCCESS] += ngss->tx_completion_success;
+	gre_mark_stats.stats[NSS_GRE_REDIR_MARK_STATS_TX_COMPLETION_DROPS] += ngss->tx_completion_drop;
+
+	spin_unlock_bh(&nss_gre_redir_mark_stats_lock);
+}
+
+/*
+ * nss_gre_redir_mark_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_gre_redir_mark_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_gre_redir_mark_stats_notification *stats_notify;
+
+	stats_notify = kzalloc(sizeof(struct nss_gre_redir_mark_stats_notification), GFP_ATOMIC);
+	if (!stats_notify) {
+		nss_warning("Unable to allocate memory for stats notification\n");
+		return;
+	}
+
+	if (if_num != NSS_GRE_REDIR_MARK_INTERFACE) {
+		nss_warning("%px: Unknown type for interface %d\n", nss_ctx, if_num);
+		kfree(stats_notify);
+		return;
+	}
+
+	spin_lock_bh(&nss_gre_redir_mark_stats_lock);
+	stats_notify->core_id = nss_ctx->id;
+	stats_notify->if_num = if_num;
+	memcpy(stats_notify->stats_ctx, gre_mark_stats.stats, sizeof(stats_notify->stats_ctx));
+	spin_unlock_bh(&nss_gre_redir_mark_stats_lock);
+
+	atomic_notifier_call_chain(&nss_gre_redir_mark_stats_notifier, NSS_STATS_EVENT_NOTIFY, stats_notify);
+	kfree(stats_notify);
+}
+
+/*
+ * nss_gre_redir_mark_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_gre_redir_mark_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_gre_redir_mark_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_gre_redir_mark_stats_unregister_notifier);
+
+/*
+ * nss_gre_redir_mark_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_gre_redir_mark_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_gre_redir_mark_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_gre_redir_mark_stats_register_notifier);
diff --git a/qca-nss-drv/nss_gre_redir_mark_stats.h b/qca-nss-drv/nss_gre_redir_mark_stats.h
new file mode 100644
index 0000000..cacb3d2
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_mark_stats.h
@@ -0,0 +1,35 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_GRE_REDIR_MARK_STATS_H__
+#define __NSS_GRE_REDIR_MARK_STATS_H__
+
+/*
+ * NSS core stats -- for H2N/N2H gre_redir_mark debug stats
+ */
+struct nss_gre_redir_mark_stats {
+	uint64_t stats[NSS_GRE_REDIR_MARK_STATS_MAX];
+};
+
+/*
+ * NSS GRE REDIR Mark statistics APIs
+ */
+extern void nss_gre_redir_mark_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_gre_redir_mark_stats_sync(struct nss_ctx_instance *nss_ctx, int if_num,
+					struct nss_gre_redir_mark_stats_sync_msg *ngss);
+extern struct dentry *nss_gre_redir_mark_stats_dentry_create(void);
+
+#endif /* __NSS_GRE_REDIR_MARK_STATS_H__ */
diff --git a/qca-nss-drv/nss_gre_redir_mark_strings.c b/qca-nss-drv/nss_gre_redir_mark_strings.c
new file mode 100644
index 0000000..a8d5a98
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_mark_strings.c
@@ -0,0 +1,66 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_gre_redir_mark_strings.h"
+
+/*
+ * nss_gre_redir_mark_strings_stats
+ *	GRE redir mark statistics string
+ */
+struct nss_stats_info nss_gre_redir_mark_strings_stats[NSS_GRE_REDIR_MARK_STATS_MAX] = {
+	{"rx Packets",				NSS_STATS_TYPE_COMMON},
+	{"rx Bytes",				NSS_STATS_TYPE_COMMON},
+	{"tx Packets",				NSS_STATS_TYPE_COMMON},
+	{"tx Bytes",				NSS_STATS_TYPE_COMMON},
+	{"rx_dropped_0",			NSS_STATS_TYPE_DROP},
+	{"rx_dropped_1",			NSS_STATS_TYPE_DROP},
+	{"rx_dropped_2",			NSS_STATS_TYPE_DROP},
+	{"rx_dropped_3",			NSS_STATS_TYPE_DROP},
+	{"HLOS Magic Failed",			NSS_STATS_TYPE_SPECIAL},
+	{"tx Inv_dst_if Drops",			NSS_STATS_TYPE_DROP},
+	{"tx Dst_if Enqueue",			NSS_STATS_TYPE_SPECIAL},
+	{"tx Dst_if Enqueue Drops",		NSS_STATS_TYPE_DROP},
+	{"Invalid Appid",			NSS_STATS_TYPE_SPECIAL},
+	{"Headroom Unavailable",		NSS_STATS_TYPE_EXCEPTION},
+	{"tx Completion Host Enqueue Success",	NSS_STATS_TYPE_SPECIAL},
+	{"tx Completion Host Enqueue Drops",	NSS_STATS_TYPE_DROP}
+};
+
+/*
+ * nss_gre_redir_mark_strings_read()
+ *	Read gre_redir_mark statistics names
+ */
+static ssize_t nss_gre_redir_mark_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_gre_redir_mark_strings_stats, NSS_GRE_REDIR_MARK_STATS_MAX);
+}
+
+/*
+ * nss_gre_redir_mark_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(gre_redir_mark);
+
+/*
+ * nss_gre_redir_mark_strings_dentry_create()
+ *	Create gre_redir_mark statistics strings debug entry.
+ */
+void nss_gre_redir_mark_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("gre_redir_mark", &nss_gre_redir_mark_strings_ops);
+}
diff --git a/qca-nss-drv/nss_gre_redir_mark_strings.h b/qca-nss-drv/nss_gre_redir_mark_strings.h
new file mode 100644
index 0000000..98ed332
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_mark_strings.h
@@ -0,0 +1,25 @@
+/*
+ ****************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ****************************************************************************
+ */
+
+#ifndef __NSS_GRE_REDIR_MARK_STRINGS_H
+#define __NSS_GRE_REDIR_MARK_STRINGS_H
+
+#include "nss_gre_redir_mark_stats.h"
+
+extern struct nss_stats_info nss_gre_redir_mark_strings_stats[NSS_GRE_REDIR_MARK_STATS_MAX];
+extern void nss_gre_redir_mark_strings_dentry_create(void);
+
+#endif /* __NSS_GRE_REDIR_MARK_STRINGS_H */
diff --git a/qca-nss-drv/nss_gre_redir_stats.c b/qca-nss-drv/nss_gre_redir_stats.c
new file mode 100644
index 0000000..6adb353
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_stats.c
@@ -0,0 +1,312 @@
+/*
+ ****************************************************************************
+ * Copyright (c) 2017-2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ****************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_gre_redir.h"
+#include "nss_gre_redir_stats.h"
+#include "nss_gre_redir_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_gre_redir_stats_notifier);
+
+/*
+ * Spinlock to protect GRE redirect statistics update/read
+ */
+DEFINE_SPINLOCK(nss_gre_redir_stats_lock);
+
+/*
+ * Array to hold tunnel stats along with if_num
+ */
+extern struct nss_gre_redir_tunnel_stats tun_stats[NSS_GRE_REDIR_MAX_INTERFACES];
+
+/*
+ * nss_gre_redir_stats_get()
+ *	Get GRE redirect tunnel stats.
+ */
+bool nss_gre_redir_stats_get(int index, struct nss_gre_redir_tunnel_stats *stats)
+{
+	spin_lock_bh(&nss_gre_redir_stats_lock);
+	if (tun_stats[index].ref_count == 0) {
+		spin_unlock_bh(&nss_gre_redir_stats_lock);
+		return false;
+	}
+
+	memcpy(stats, &tun_stats[index], sizeof(struct nss_gre_redir_tunnel_stats));
+	spin_unlock_bh(&nss_gre_redir_stats_lock);
+	return true;
+}
+EXPORT_SYMBOL(nss_gre_redir_stats_get);
+
+/*
+ * nss_gre_redir_stats_read()
+ *	READ gre_redir tunnel stats.
+ */
+static ssize_t nss_gre_redir_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	 /*
+	  * Max output lines = #stats +
+	  * few blank lines for banner printing + Number of Extra outputlines
+	  * for future reference to add new stats
+	  */
+	uint32_t max_output_lines = NSS_GRE_REDIR_STATS_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines * NSS_GRE_REDIR_MAX_INTERFACES;
+	struct nss_stats_data *data = fp->private_data;
+	struct nss_gre_redir_tunnel_stats stats;
+	ssize_t bytes_read = 0;
+	size_t size_wr = 0;
+	int index = 0;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	if (data) {
+		index = data->index;
+	}
+
+	/*
+	 * If we are done accomodating all the GRE_REDIR tunnels.
+	 */
+	if (index >= NSS_GRE_REDIR_MAX_INTERFACES) {
+		kfree(lbuf);
+		return 0;
+	}
+
+	for (; index < NSS_GRE_REDIR_MAX_INTERFACES; index++) {
+		bool isthere;
+
+		/*
+		 * If gre_redir tunnel does not exists, then isthere will be false.
+		 */
+		isthere = nss_gre_redir_stats_get(index, &stats);
+		if (!isthere) {
+			continue;
+		}
+
+		size_wr += nss_stats_banner(lbuf, size_wr, size_al, "gre_redir stats", NSS_STATS_SINGLE_CORE);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nTunnel stats for %s\n", stats.dev->name);
+		size_wr += nss_stats_print("gre_redir", NULL, NSS_STATS_SINGLE_INSTANCE, nss_gre_redir_strings_stats,
+					&stats.tstats.rx_packets, NSS_GRE_REDIR_STATS_MAX, lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	if (data) {
+		data->index = index;
+	}
+
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_gre_redir_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(gre_redir)
+
+/*
+ * nss_gre_redir_stats_dentry_create()
+ *	Create debugfs directory entry for stats.
+ */
+struct dentry *nss_gre_redir_stats_dentry_create(void)
+{
+	struct dentry *gre_redir;
+	struct dentry *tun_stats;
+
+	gre_redir = debugfs_create_dir("gre_redir", nss_top_main.stats_dentry);
+	if (unlikely(!gre_redir)) {
+		nss_warning("Failed to create directory entry qca-nss-drv/stats/gre_redir/\n");
+		return NULL;
+	}
+
+	tun_stats = debugfs_create_file("tun_stats", 0400, gre_redir,
+			&nss_top_main, &nss_gre_redir_stats_ops);
+	if (unlikely(!tun_stats)) {
+		debugfs_remove_recursive(gre_redir);
+		nss_warning("Failed to create file entry qca-nss-drv/stats/gre_redir/tun_stats\n");
+		return NULL;
+	}
+
+	return gre_redir;
+}
+
+/*
+ * nss_gre_redir_stats_sync()
+ *	Update gre_redir tunnel stats.
+ */
+void nss_gre_redir_stats_sync(struct nss_ctx_instance *nss_ctx, int if_num, struct nss_gre_redir_stats_sync_msg *ngss)
+{
+	int i, j;
+	uint32_t type;
+	struct net_device *dev;
+	struct nss_gre_redir_tun_stats *node_stats;
+
+	type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+	dev = nss_cmn_get_interface_dev(nss_ctx, if_num);
+	if (!dev) {
+		nss_warning("%px: Unable to find net device for the interface %d\n", nss_ctx, if_num);
+		return;
+	}
+
+	if (!nss_gre_redir_verify_ifnum(if_num)) {
+		nss_warning("%px: Unknown type for interface %d\n", nss_ctx, if_num);
+		return;
+	}
+
+	spin_lock_bh(&nss_gre_redir_stats_lock);
+	for (i = 0; i < NSS_GRE_REDIR_MAX_INTERFACES; i++) {
+		if (tun_stats[i].dev == dev) {
+			break;
+		}
+	}
+
+	if (i == NSS_GRE_REDIR_MAX_INTERFACES) {
+		nss_warning("%px: Unable to find tunnel stats instance for interface %d\n", nss_ctx, if_num);
+		spin_unlock_bh(&nss_gre_redir_stats_lock);
+		return;
+	}
+
+	nss_assert(tun_stats[i].ref_count);
+	node_stats = &tun_stats[i].tstats;
+	switch (type) {
+	case NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_HOST_INNER:
+	case NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_OFFL_INNER:
+	case NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_SJACK_INNER:
+		node_stats->tx_packets += ngss->node_stats.tx_packets;
+		node_stats->tx_bytes += ngss->node_stats.tx_bytes;
+		node_stats->sjack_tx_packets += ngss->sjack_rx_packets;
+		node_stats->encap_sg_alloc_drop += ngss->encap_sg_alloc_drop;
+		node_stats->tx_dropped += nss_cmn_rx_dropped_sum(&(ngss->node_stats));
+		for (j = 0; j < NSS_GRE_REDIR_MAX_RADIO; j++) {
+			node_stats->offl_tx_pkts[j] += ngss->offl_rx_pkts[j];
+		}
+
+		break;
+
+	case NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_OUTER:
+		node_stats->rx_packets += ngss->node_stats.rx_packets;
+		node_stats->rx_bytes += ngss->node_stats.rx_bytes;
+		node_stats->sjack_rx_packets += ngss->sjack_rx_packets;
+		node_stats->decap_fail_drop += ngss->decap_fail_drop;
+		node_stats->decap_split_drop += ngss->decap_split_drop;
+		node_stats->split_sg_alloc_fail += ngss->split_sg_alloc_fail;
+		node_stats->split_linear_copy_fail += ngss->split_linear_copy_fail;
+		node_stats->split_not_enough_tailroom += ngss->split_not_enough_tailroom;
+		node_stats->decap_eapol_frames += ngss->decap_eapol_frames;
+		for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+			node_stats->rx_dropped[j] += ngss->node_stats.rx_dropped[j];
+		}
+
+		for (j = 0; j < NSS_GRE_REDIR_MAX_RADIO; j++) {
+			node_stats->offl_rx_pkts[j] += ngss->offl_rx_pkts[j];
+		}
+
+		break;
+
+	case NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_EXCEPTION_US:
+		node_stats->exception_us_rx += ngss->node_stats.rx_packets;
+		node_stats->exception_us_tx += ngss->node_stats.tx_packets;
+		break;
+
+	case NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_EXCEPTION_DS:
+		node_stats->exception_ds_rx += ngss->node_stats.rx_packets;
+		node_stats->exception_ds_tx += ngss->node_stats.tx_packets;
+		node_stats->exception_ds_invalid_dst_drop += ngss->exception_ds_invalid_dst_drop;
+		node_stats->exception_ds_inv_appid += ngss->exception_ds_inv_appid;
+		node_stats->headroom_unavail += ngss->headroom_unavail;
+		node_stats->tx_completion_success += ngss->tx_completion_success;
+		node_stats->tx_completion_drop += ngss->tx_completion_drop;
+		break;
+	}
+
+	spin_unlock_bh(&nss_gre_redir_stats_lock);
+}
+
+/*
+ * nss_gre_redir_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_gre_redir_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_gre_redir_stats_notification *stats_notify;
+	struct net_device *dev;
+	int i;
+
+	stats_notify = kzalloc(sizeof(struct nss_gre_redir_stats_notification), GFP_ATOMIC);
+	if (!stats_notify) {
+		nss_warning("Unable to allocate memory for stats notification\n");
+		return;
+	}
+
+	dev = nss_cmn_get_interface_dev(nss_ctx, if_num);
+	if (!dev) {
+		nss_warning("%px: Unable to find net device for the interface %d\n", nss_ctx, if_num);
+		kfree(stats_notify);
+		return;
+	}
+
+	if (!nss_gre_redir_verify_ifnum(if_num)) {
+		nss_warning("%px: Unknown type for interface %d\n", nss_ctx, if_num);
+		kfree(stats_notify);
+		return;
+	}
+
+	spin_lock_bh(&nss_gre_redir_stats_lock);
+	for (i = 0; i < NSS_GRE_REDIR_MAX_INTERFACES; i++) {
+		if (tun_stats[i].dev == dev) {
+			break;
+		}
+	}
+
+	if (i == NSS_GRE_REDIR_MAX_INTERFACES) {
+		nss_warning("%px: Unable to find tunnel stats instance for interface %d\n", nss_ctx, if_num);
+		spin_unlock_bh(&nss_gre_redir_stats_lock);
+		kfree(stats_notify);
+		return;
+	}
+
+	stats_notify->core_id = nss_ctx->id;
+	stats_notify->if_num = if_num;
+	memcpy(&(stats_notify->stats_ctx), &(tun_stats[i]), sizeof(stats_notify->stats_ctx));
+	spin_unlock_bh(&nss_gre_redir_stats_lock);
+	atomic_notifier_call_chain(&nss_gre_redir_stats_notifier, NSS_STATS_EVENT_NOTIFY, stats_notify);
+	kfree(stats_notify);
+}
+
+/*
+ * nss_gre_redir_stats_unregister_notifier()
+ *	Degisters statistics notifier.
+ */
+int nss_gre_redir_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_gre_redir_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_gre_redir_stats_unregister_notifier);
+
+/*
+ * nss_gre_redir_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_gre_redir_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_gre_redir_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_gre_redir_stats_register_notifier);
diff --git a/qca-nss-drv/nss_gre_redir_stats.h b/qca-nss-drv/nss_gre_redir_stats.h
new file mode 100644
index 0000000..28f8fae
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_stats.h
@@ -0,0 +1,30 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2017-2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_GRE_REDIR_STATS_H__
+#define __NSS_GRE_REDIR_STATS_H__
+
+/*
+ * NSS GRE REDIR statistics APIs
+ */
+extern spinlock_t nss_gre_redir_stats_lock;
+extern bool nss_gre_redir_verify_ifnum(uint32_t if_num);
+extern void nss_gre_redir_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_gre_redir_stats_sync(struct nss_ctx_instance *nss_ctx, int if_num,
+					struct nss_gre_redir_stats_sync_msg *ngss);
+extern struct dentry *nss_gre_redir_stats_dentry_create(void);
+
+#endif /* __NSS_GRE_REDIR_STATS_H__ */
diff --git a/qca-nss-drv/nss_gre_redir_strings.c b/qca-nss-drv/nss_gre_redir_strings.c
new file mode 100644
index 0000000..319be27
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_strings.c
@@ -0,0 +1,87 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_gre_redir_strings.h"
+
+/*
+ * nss_gre_redir_strings_stats
+ *	GRE redirect statistics string.
+ */
+struct nss_stats_info nss_gre_redir_strings_stats[NSS_GRE_REDIR_STATS_MAX] = {
+	{"RX Packets",				NSS_STATS_TYPE_COMMON},
+	{"RX Bytes",				NSS_STATS_TYPE_COMMON},
+	{"TX Packets",				NSS_STATS_TYPE_COMMON},
+	{"TX Bytes",				NSS_STATS_TYPE_COMMON},
+	{"RX Drops_[0]",			NSS_STATS_TYPE_DROP},
+	{"RX Drops_[1]",			NSS_STATS_TYPE_DROP},
+	{"RX Drops_[2]",			NSS_STATS_TYPE_DROP},
+	{"RX Drops_[3]",			NSS_STATS_TYPE_DROP},
+	{"TX Drops",				NSS_STATS_TYPE_DROP},
+	{"RX Sjack Packets",			NSS_STATS_TYPE_SPECIAL},
+	{"TX Sjack packets",			NSS_STATS_TYPE_SPECIAL},
+	{"RX Offload Packets_[0]",		NSS_STATS_TYPE_SPECIAL},
+	{"RX Offload Packets_[1]",		NSS_STATS_TYPE_SPECIAL},
+	{"RX Offload Packets_[2]",		NSS_STATS_TYPE_SPECIAL},
+	{"RX Offload Packets_[3]",		NSS_STATS_TYPE_SPECIAL},
+	{"RX Offload Packets_[4]",		NSS_STATS_TYPE_SPECIAL},
+	{"TX Offload Packets_[0]",		NSS_STATS_TYPE_SPECIAL},
+	{"TX Offload Packets_[1]",		NSS_STATS_TYPE_SPECIAL},
+	{"TX Offload Packets_[2]",		NSS_STATS_TYPE_SPECIAL},
+	{"TX Offload Packets_[3]",		NSS_STATS_TYPE_SPECIAL},
+	{"TX Offload Packets_[4]",		NSS_STATS_TYPE_SPECIAL},
+	{"US exception RX Packets",		NSS_STATS_TYPE_EXCEPTION},
+	{"US exception TX Packets",		NSS_STATS_TYPE_EXCEPTION},
+	{"DS exception RX Packets",		NSS_STATS_TYPE_EXCEPTION},
+	{"DS exception TX Packets",		NSS_STATS_TYPE_EXCEPTION},
+	{"Encap SG alloc drop",			NSS_STATS_TYPE_DROP},
+	{"Decap fail drop",			NSS_STATS_TYPE_DROP},
+	{"Decap split drop",			NSS_STATS_TYPE_SPECIAL},
+	{"Split SG alloc fail",			NSS_STATS_TYPE_SPECIAL},
+	{"Split linear copy fail",		NSS_STATS_TYPE_SPECIAL},
+	{"Split not enough tailroom",		NSS_STATS_TYPE_EXCEPTION},
+	{"Exception ds invalid dst",		NSS_STATS_TYPE_SPECIAL},
+	{"Decap eapol frames",			NSS_STATS_TYPE_SPECIAL},
+	{"Exception ds invalid appid",		NSS_STATS_TYPE_EXCEPTION},
+	{"Headroom Unavailable",		NSS_STATS_TYPE_EXCEPTION},
+	{"Exception ds Tx completion Success",	NSS_STATS_TYPE_SPECIAL},
+	{"Exception ds Tx completion drop",	NSS_STATS_TYPE_DROP}
+};
+
+/*
+ * nss_gre_redir_strings_read()
+ *	Read GRE redirect statistics names.
+ */
+static ssize_t nss_gre_redir_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_gre_redir_strings_stats, NSS_GRE_REDIR_STATS_MAX);
+}
+
+/*
+ * nss_gre_redir_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(gre_redir);
+
+/*
+ * nss_gre_redir_strings_dentry_create()
+ *	Create GRE redirect statistics strings debug entry.
+ */
+void nss_gre_redir_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("gre_redir", &nss_gre_redir_strings_ops);
+}
diff --git a/qca-nss-drv/nss_gre_redir_strings.h b/qca-nss-drv/nss_gre_redir_strings.h
new file mode 100644
index 0000000..b0f0ba3
--- /dev/null
+++ b/qca-nss-drv/nss_gre_redir_strings.h
@@ -0,0 +1,25 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#ifndef __NSS_GRE_REDIR_STRINGS_H
+#define __NSS_GRE_REDIR_STRINGS_H
+
+#include "nss_gre_redir_stats.h"
+
+extern struct nss_stats_info nss_gre_redir_strings_stats[NSS_GRE_REDIR_STATS_MAX];
+extern void nss_gre_redir_strings_dentry_create(void);
+
+#endif /* __NSS_GRE_REDIR_STRINGS_H */
diff --git a/qca-nss-drv/nss_gre_stats.c b/qca-nss-drv/nss_gre_stats.c
new file mode 100644
index 0000000..3808e5e
--- /dev/null
+++ b/qca-nss-drv/nss_gre_stats.c
@@ -0,0 +1,338 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_gre_stats.c
+ *	NSS GRE statistics APIs
+ *
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_gre.h"
+#include "nss_gre_stats.h"
+#include "nss_gre_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_gre_stats_notifier);
+
+/*
+ * Data structures to store GRE nss debug stats
+ */
+static DEFINE_SPINLOCK(nss_gre_stats_lock);
+static struct nss_gre_stats_session session_stats[NSS_GRE_MAX_DEBUG_SESSION_STATS];
+static struct nss_gre_stats_base base_stats;
+
+/*
+ * GRE statistics APIs
+ */
+
+/*
+ * nss_gre_stats_session_unregister()
+ *	Unregister debug statistic for GRE session.
+ */
+void nss_gre_stats_session_unregister(uint32_t if_num)
+{
+	int i;
+
+	spin_lock_bh(&nss_gre_stats_lock);
+	for (i = 0; i < NSS_GRE_MAX_DEBUG_SESSION_STATS; i++) {
+		if (session_stats[i].if_num == if_num) {
+			memset(&session_stats[i], 0, sizeof(struct nss_gre_stats_session));
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_gre_stats_lock);
+}
+
+/*
+ * nss_gre_stats_session_register()
+ *	Register debug statistic for GRE session.
+ */
+void nss_gre_stats_session_register(uint32_t if_num, struct net_device *netdev)
+{
+	int i;
+
+	spin_lock_bh(&nss_gre_stats_lock);
+	for (i = 0; i < NSS_GRE_MAX_DEBUG_SESSION_STATS; i++) {
+		if (!session_stats[i].valid) {
+			session_stats[i].valid = true;
+			session_stats[i].if_num = if_num;
+			session_stats[i].if_index = netdev->ifindex;
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_gre_stats_lock);
+}
+
+/*
+ * nss_gre_stats_session_sync()
+ *	debug statistics sync for GRE session.
+ */
+void nss_gre_stats_session_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_session_stats_msg *sstats, uint16_t if_num)
+{
+	int i, j;
+	enum nss_dynamic_interface_type interface_type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+
+	spin_lock_bh(&nss_gre_stats_lock);
+	for (i = 0; i < NSS_GRE_MAX_DEBUG_SESSION_STATS; i++) {
+		if (session_stats[i].if_num == if_num) {
+			for (j = 0; j < NSS_GRE_SESSION_DEBUG_MAX; j++) {
+				session_stats[i].stats[j] += sstats->stats[j];
+			}
+
+			if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER) {
+				session_stats[i].stats[NSS_GRE_SESSION_ENCAP_RX_RECEIVED] += sstats->node_stats.rx_packets;
+			} else if (interface_type == NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER) {
+				session_stats[i].stats[NSS_GRE_SESSION_DECAP_TX_FORWARDED] += sstats->node_stats.tx_packets;
+			}
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_gre_stats_lock);
+}
+
+/*
+ * nss_gre_stats_base_sync()
+ *	Debug statistics sync for GRE base node.
+ */
+void nss_gre_stats_base_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_base_stats_msg *bstats)
+{
+	int i;
+
+	spin_lock_bh(&nss_gre_stats_lock);
+	for (i = 0; i < NSS_GRE_BASE_DEBUG_MAX; i++) {
+		base_stats.stats[i] += bstats->stats[i];
+	}
+	spin_unlock_bh(&nss_gre_stats_lock);
+}
+
+/*
+ * nss_gre_stats_session_get()
+ *	Get GRE session debug statistics.
+ */
+static void nss_gre_stats_session_get(void *stats_mem, int size)
+{
+	struct nss_gre_stats_session *stats = (struct nss_gre_stats_session *)stats_mem;
+	int i;
+
+	if (!stats || (size < (sizeof(struct nss_gre_stats_session) * NSS_GRE_MAX_DEBUG_SESSION_STATS)))  {
+		nss_warning("No memory to copy gre stats");
+		return;
+	}
+
+	spin_lock_bh(&nss_gre_stats_lock);
+	for (i = 0; i < NSS_GRE_MAX_DEBUG_SESSION_STATS; i++) {
+		if (session_stats[i].valid) {
+			memcpy(stats, &session_stats[i], sizeof(struct nss_gre_stats_session));
+			stats++;
+		}
+	}
+	spin_unlock_bh(&nss_gre_stats_lock);
+}
+
+/*
+ * nss_gre_stats_base_get()
+ *	Get GRE debug base statistics.
+ */
+static void nss_gre_stats_base_get(void *stats_mem, int size)
+{
+	struct nss_gre_stats_base *stats = (struct nss_gre_stats_base *)stats_mem;
+
+	if (!stats) {
+		nss_warning("No memory to copy GRE base stats\n");
+		return;
+	}
+
+	if (size < sizeof(struct nss_gre_stats_base)) {
+		nss_warning("Not enough memory to copy GRE base stats\n");
+		return;
+	}
+
+	spin_lock_bh(&nss_gre_stats_lock);
+	memcpy(stats, &base_stats, sizeof(struct nss_gre_stats_base));
+	spin_unlock_bh(&nss_gre_stats_lock);
+}
+
+/*
+ * nss_gre_stats_read()
+ *	Read GRE statistics
+ */
+static ssize_t nss_gre_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	uint32_t max_output_lines = 2 /* header & footer for base debug stats */
+		+ 2 /* header & footer for session debug stats */
+		+ NSS_GRE_BASE_DEBUG_MAX  /* Base debug */
+		+ NSS_GRE_MAX_DEBUG_SESSION_STATS * (NSS_GRE_SESSION_DEBUG_MAX + 2) /*session stats */
+		+ 2;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	struct net_device *dev;
+	struct nss_gre_stats_session *sstats;
+	struct nss_gre_stats_base *bstats;
+	int id;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	bstats = kzalloc(sizeof(struct nss_gre_stats_base), GFP_KERNEL);
+	if (unlikely(!bstats)) {
+		nss_warning("Could not allocate memory for base debug statistics buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	sstats = kzalloc(sizeof(struct nss_gre_stats_session) * NSS_GRE_MAX_DEBUG_SESSION_STATS, GFP_KERNEL);
+	if (unlikely(!sstats)) {
+		nss_warning("Could not allocate memory for base debug statistics buffer");
+		kfree(lbuf);
+		kfree(bstats);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "gre", NSS_STATS_SINGLE_CORE);
+
+	/*
+	 * Get all base stats
+	 */
+	nss_gre_stats_base_get((void *)bstats, sizeof(struct nss_gre_stats_base));
+
+	size_wr += nss_stats_print("gre", NULL, NSS_STATS_SINGLE_INSTANCE
+					, nss_gre_strings_base_stats
+					, bstats->stats
+					, NSS_GRE_BASE_DEBUG_MAX
+					, lbuf, size_wr, size_al);
+
+	/*
+	 * Get all session stats
+	 */
+	nss_gre_stats_session_get(sstats, sizeof(struct nss_gre_stats_session) * NSS_GRE_MAX_DEBUG_SESSION_STATS);
+
+	for (id = 0; id < NSS_GRE_MAX_DEBUG_SESSION_STATS; id++) {
+
+		if (!((sstats + id)->valid)) {
+			continue;
+		}
+
+		dev = dev_get_by_index(&init_net, (sstats + id)->if_index);
+		if (likely(dev)) {
+
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%d. nss interface id=%d, netdevice=%s\n", id,
+					     (sstats + id)->if_num, dev->name);
+			dev_put(dev);
+		} else {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%d. nss interface id=%d\n", id,
+					     (sstats + id)->if_num);
+		}
+		size_wr += nss_stats_print("gre_session", NULL, id
+						, nss_gre_strings_session_stats
+						, (sstats + id)->stats
+						, NSS_GRE_SESSION_DEBUG_MAX
+						, lbuf, size_wr, size_al);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	kfree(sstats);
+	kfree(bstats);
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_gre_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(gre)
+
+/*
+ * nss_gre_stats_dentry_create()
+ *	Create gre statistics debug entry.
+ */
+void nss_gre_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("gre", &nss_gre_stats_ops);
+}
+
+/*
+ * nss_gre_stats_base_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_gre_stats_base_notify(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_gre_base_stats_notification gre_stats;
+
+	spin_lock_bh(&nss_gre_stats_lock);
+	gre_stats.core_id = nss_ctx->id;
+	memcpy(gre_stats.stats_base_ctx, base_stats.stats, sizeof(gre_stats.stats_base_ctx));
+	spin_unlock_bh(&nss_gre_stats_lock);
+
+	atomic_notifier_call_chain(&nss_gre_stats_notifier, NSS_STATS_EVENT_NOTIFY, &gre_stats);
+}
+
+/*
+ * nss_gre_stats_session_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_gre_stats_session_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_gre_session_stats_notification gre_stats;
+	int i;
+
+	spin_lock_bh(&nss_gre_stats_lock);
+	for (i = 0; i < NSS_GRE_MAX_DEBUG_SESSION_STATS; i++) {
+		if (session_stats[i].if_num != if_num) {
+			continue;
+		}
+
+		memcpy(gre_stats.stats_session_ctx, session_stats[i].stats, sizeof(gre_stats.stats_session_ctx));
+		gre_stats.core_id = nss_ctx->id;
+		gre_stats.if_num = if_num;
+		spin_unlock_bh(&nss_gre_stats_lock);
+		atomic_notifier_call_chain(&nss_gre_stats_notifier, NSS_STATS_EVENT_NOTIFY, &gre_stats);
+		return;
+	}
+	spin_unlock_bh(&nss_gre_stats_lock);
+}
+
+/*
+ * nss_gre_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_gre_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_gre_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_gre_stats_unregister_notifier);
+
+/*
+ * nss_gre_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_gre_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_gre_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_gre_stats_register_notifier);
diff --git a/qca-nss-drv/nss_gre_stats.h b/qca-nss-drv/nss_gre_stats.h
new file mode 100644
index 0000000..7feb1d6
--- /dev/null
+++ b/qca-nss-drv/nss_gre_stats.h
@@ -0,0 +1,55 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_gre_stats.h
+ *	NSS GRE statistics header file.
+ */
+
+#ifndef __NSS_GRE_STATS_H
+#define __NSS_GRE_STATS_H
+
+#include <nss_cmn.h>
+
+/*
+ *  GRE base debug statistics
+ */
+struct nss_gre_stats_base {
+	uint64_t stats[NSS_GRE_BASE_DEBUG_MAX];	/**< GRE debug statistics. */
+};
+
+/*
+ *  GRE session debug statistics
+ */
+struct nss_gre_stats_session {
+	uint64_t stats[NSS_GRE_SESSION_DEBUG_MAX];	/**< Session debug statistics. */
+	int32_t if_index;				/**< Netdevice's ifindex. */
+	uint32_t if_num;				/**< NSS interface number. */
+	bool valid;					/**< Is node valid ? */
+};
+
+/*
+ * GRE statistics APIs
+ */
+extern void nss_gre_stats_base_notify(struct nss_ctx_instance *nss_ctx);
+extern void nss_gre_stats_session_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_gre_stats_session_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_session_stats_msg *sstats, uint16_t if_num);
+extern void nss_gre_stats_base_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_base_stats_msg *bstats);
+extern void nss_gre_stats_session_register(uint32_t if_num, struct net_device *netdev);
+extern void nss_gre_stats_session_unregister(uint32_t if_num);
+extern void nss_gre_stats_dentry_create(void);
+
+#endif /* __NSS_GRE_STATS_H */
diff --git a/qca-nss-drv/nss_gre_strings.c b/qca-nss-drv/nss_gre_strings.c
new file mode 100644
index 0000000..26c652d
--- /dev/null
+++ b/qca-nss-drv/nss_gre_strings.c
@@ -0,0 +1,124 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_gre_strings.h"
+
+/*
+ * nss_gre_strings_base_stats
+ *	GRE debug statistics strings for base types
+ */
+struct nss_stats_info nss_gre_strings_base_stats[NSS_GRE_BASE_DEBUG_MAX] = {
+	{"base_rx_pkts",			NSS_STATS_TYPE_COMMON},
+	{"base_rx_drops",			NSS_STATS_TYPE_DROP},
+	{"base_exp_eth_hdr_missing",		NSS_STATS_TYPE_EXCEPTION},
+	{"base_exp_eth_type_non_ip",		NSS_STATS_TYPE_EXCEPTION},
+	{"base_exp_ip_unknown_protocol",	NSS_STATS_TYPE_EXCEPTION},
+	{"base_exp_ip_header_incomplete",	NSS_STATS_TYPE_EXCEPTION},
+	{"base_exp_ip_bad_total_length",	NSS_STATS_TYPE_EXCEPTION},
+	{"base_exp_ip_bad_checksum",		NSS_STATS_TYPE_EXCEPTION},
+	{"base_exp_ip_datagram_incomplete",	NSS_STATS_TYPE_EXCEPTION},
+	{"base_exp_ip_fragment",		NSS_STATS_TYPE_EXCEPTION},
+	{"base_exp_ip_options_incomplete",	NSS_STATS_TYPE_EXCEPTION},
+	{"base_exp_ip_with_options",		NSS_STATS_TYPE_EXCEPTION},
+	{"base_exp_ipv6_unknown_protocol",	NSS_STATS_TYPE_EXCEPTION},
+	{"base_exp_ipv6_header_incomplete",	NSS_STATS_TYPE_EXCEPTION},
+	{"base_exp_unknown_session",		NSS_STATS_TYPE_EXCEPTION},
+	{"base_exp_node_inactive",		NSS_STATS_TYPE_EXCEPTION}
+};
+
+/*
+ * nss_gre_base_strings_read()
+ *	 Read GRE base debug statistics names
+ */
+static ssize_t nss_gre_base_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_gre_strings_base_stats, NSS_GRE_BASE_DEBUG_MAX);
+}
+
+/*
+ * nss_gre_base_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(gre_base);
+
+/*
+ * nss_gre_strings_session_stats
+ *	GRE debug statistics strings for sessions
+ */
+struct nss_stats_info nss_gre_strings_session_stats[NSS_GRE_SESSION_DEBUG_MAX] = {
+	{"session_pbuf_alloc_fail",		NSS_STATS_TYPE_ERROR},
+	{"session_decap_forward_enqueue_fail",	NSS_STATS_TYPE_DROP},
+	{"session_encap_forward_enqueue_fail",	NSS_STATS_TYPE_DROP},
+	{"session_decap_tx_forwarded",		NSS_STATS_TYPE_SPECIAL},
+	{"session_encap_rx_received",		NSS_STATS_TYPE_SPECIAL},
+	{"session_encap_rx_drops",		NSS_STATS_TYPE_DROP},
+	{"session_encap_rx_linear_fail",	NSS_STATS_TYPE_DROP},
+	{"session_exp_rx_key_error",		NSS_STATS_TYPE_EXCEPTION},
+	{"session_exp_rx_seq_error",		NSS_STATS_TYPE_EXCEPTION},
+	{"session_exp_rx_cs_error",		NSS_STATS_TYPE_EXCEPTION},
+	{"session_exp_rx_flag_mismatch",	NSS_STATS_TYPE_EXCEPTION},
+	{"session_exp_rx_malformed",		NSS_STATS_TYPE_EXCEPTION},
+	{"session_exp_rx_invalid_protocol",	NSS_STATS_TYPE_EXCEPTION},
+	{"session_exp_rx_no_headroom",		NSS_STATS_TYPE_EXCEPTION}
+};
+
+/*
+ * nss_gre_session_strings_read()
+ *	Read GRE session debug statistics names
+ */
+static ssize_t nss_gre_session_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_gre_strings_session_stats, NSS_GRE_SESSION_DEBUG_MAX);
+}
+
+/*
+ * nss_gre_session_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(gre_session);
+
+/*
+ * nss_gre_strings_dentry_create()
+ *	Create gre statistics strings debug entry.
+ */
+void nss_gre_strings_dentry_create(void)
+{
+	struct dentry *gre_d = NULL;
+
+	if (!nss_top_main.strings_dentry) {
+		nss_warning("qca-nss-drv/strings is not present");
+		return;
+	}
+
+	gre_d = debugfs_create_dir("gre", nss_top_main.strings_dentry);
+	if (!gre_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/gre directory");
+		return;
+	}
+
+	if (!debugfs_create_file("gre_base", 0400, gre_d, &nss_top_main, &nss_gre_base_strings_ops)) {
+		nss_warning("Failed to create qca-nss-drv/strings/gre/gre_base file");
+		debugfs_remove_recursive(gre_d);
+		return;
+	}
+
+	if (!debugfs_create_file("gre_session", 0400, gre_d, &nss_top_main, &nss_gre_session_strings_ops)) {
+		nss_warning("Failed to create qca-nss-drv/strings/gre/gre_session file");
+		debugfs_remove_recursive(gre_d);
+		return;
+	}
+}
diff --git a/qca-nss-drv/nss_gre_strings.h b/qca-nss-drv/nss_gre_strings.h
new file mode 100644
index 0000000..e8a421f
--- /dev/null
+++ b/qca-nss-drv/nss_gre_strings.h
@@ -0,0 +1,26 @@
+/*
+ ****************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ****************************************************************************
+ */
+
+#ifndef __NSS_GRE_STRINGS_H
+#define __NSS_GRE_STRINGS_H
+
+#include "nss_gre_stats.h"
+
+extern struct nss_stats_info nss_gre_strings_base_stats[NSS_GRE_BASE_DEBUG_MAX];
+extern struct nss_stats_info nss_gre_strings_session_stats[NSS_GRE_SESSION_DEBUG_MAX];
+extern void nss_gre_strings_dentry_create(void);
+
+#endif /* __NSS_GRE_STRINGS_H */
diff --git a/qca-nss-drv/nss_gre_tunnel.c b/qca-nss-drv/nss_gre_tunnel.c
new file mode 100644
index 0000000..1e9a22a
--- /dev/null
+++ b/qca-nss-drv/nss_gre_tunnel.c
@@ -0,0 +1,395 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_gre_tunnel_stats.h"
+#include "nss_gre_tunnel_log.h"
+#include "nss_gre_tunnel_strings.h"
+
+#define NSS_GRE_TUNNEL_TX_TIMEOUT 3000 /* 3 Seconds */
+
+/*
+ * Private data structure
+ */
+static struct nss_gre_tunnel_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+	void *cb;
+	void *app_data;
+} gre_tunnel_pvt;
+
+/*
+ * nss_gre_tunnel_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static bool nss_gre_tunnel_verify_if_num(uint32_t if_num)
+{
+	uint32_t type = nss_dynamic_interface_get_type(nss_gre_tunnel_get_ctx(), if_num);
+
+	switch (type) {
+	case NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INNER:
+	case NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INLINE_INNER:
+	case NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_OUTER:
+	case NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INLINE_OUTER:
+	case NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INNER_EXCEPTION:
+		return true;
+	default:
+		return false;
+	}
+}
+
+/*
+ * nss_gre_tunnel_handler()
+ *	Handle NSS to HLOS messages for gre_tunnel
+ */
+static void nss_gre_tunnel_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_gre_tunnel_msg *ngtm = (struct nss_gre_tunnel_msg *)ncm;
+	void *ctx;
+
+	nss_gre_tunnel_msg_callback_t cb;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	BUG_ON(!nss_gre_tunnel_verify_if_num(ncm->interface));
+
+	/*
+	 * Trace Messages
+	 */
+	nss_gre_tunnel_log_rx_msg(ngtm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_GRE_TUNNEL_MSG_MAX) {
+		nss_warning("%px: received invalid message %d for GRE_TUNNEL interface %d", nss_ctx, ncm->type, ncm->interface);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_gre_tunnel_msg)) {
+		nss_warning("%px: gre_tunnel message length is invalid: %d", nss_ctx, ncm->len);
+		return;
+	}
+
+	/*
+	 * Check messages
+	 */
+	switch (ngtm->cm.type) {
+	case NSS_GRE_TUNNEL_MSG_STATS:
+		nss_gre_tunnel_stats_session_sync(nss_ctx, &ngtm->msg.stats, ncm->interface);
+		nss_gre_tunnel_stats_notify(nss_ctx, ncm->interface);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->gre_tunnel_msg_callback;
+		ncm->app_data = (nss_ptr_t)nss_ctx->subsys_dp_register[ncm->interface].app_data;
+	}
+
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * callback
+	 */
+	cb = (nss_gre_tunnel_msg_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	/*
+	 * call GRE Tunnel session callback
+	 */
+	if (!cb) {
+		return;
+	}
+
+	cb(ctx, ngtm);
+}
+
+/*
+ * nss_gre_tunnel_inquiry()
+ *	Inquiry if a GRE tunnel has been established in NSS FW.
+ *
+ * Input parameters:
+ *	inquiry_info->ip_type
+ *	inquiry_info->src_ip
+ *	inquiry_info->dest_ip
+ *	inquiry_info->gre_mode
+ *	 if (gre_mode == NSS_GRE_TUNNEL_MODE_GRE_UDP)
+ *		inquiry_info->src_port
+ *		inquiry_info->dest_port
+ *	inquiry_info->encrypt_type	-- currently not checked in FW,
+ */
+nss_tx_status_t nss_gre_tunnel_inquiry(
+		struct nss_gre_tunnel_configure *inquiry_info,
+		nss_gre_tunnel_msg_callback_t cb, void *app_data)
+{
+	nss_tx_status_t nss_tx_status;
+	struct nss_gre_tunnel_msg nim;
+	struct nss_ctx_instance *nss_ctx = nss_gre_tunnel_get_ctx();
+
+	/*
+	 * Initialize inquiry message structure.
+	 * This is async message and the result will be returned
+	 * to the caller by the msg_callback passed in.
+	 */
+	memset(&nim, 0, sizeof(nim));
+	nss_gre_tunnel_msg_init(&nim, NSS_GRE_TUNNEL_INTERFACE,
+			NSS_GRE_TUNNEL_MSG_INQUIRY,
+			sizeof(struct nss_gre_tunnel_configure),
+			cb, app_data);
+	nim.msg.configure = *inquiry_info;
+	nss_tx_status = nss_gre_tunnel_tx_msg(nss_ctx, &nim);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Send GT inquiry message failed\n", inquiry_info);
+	}
+
+	return nss_tx_status;
+}
+EXPORT_SYMBOL(nss_gre_tunnel_inquiry);
+
+/*
+ * nss_get_gre_tunnel_context()
+ *	Return the core ctx which the feature is on
+ */
+struct nss_ctx_instance *nss_gre_tunnel_get_ctx(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.gre_tunnel_handler_id];
+}
+EXPORT_SYMBOL(nss_gre_tunnel_get_ctx);
+
+/*
+ * nss_gre_tunnel_ifnum_with_core_id()
+ *	Append core id to GRE tunnel interface num
+ */
+int nss_gre_tunnel_ifnum_with_core_id(int if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_gre_tunnel_get_ctx();
+	BUG_ON(!nss_gre_tunnel_verify_if_num(if_num));
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (nss_is_dynamic_interface(if_num) == false) {
+		nss_info("%px: Invalid if_num: %d, must be a dynamic interface\n", nss_ctx, if_num);
+		return 0;
+	}
+
+	return NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_gre_tunnel_ifnum_with_core_id);
+
+/*
+ * nss_gre_tunnel_tx_buf()
+ *	Transmit buffer over GRE Tunnel interface
+ */
+nss_tx_status_t nss_gre_tunnel_tx_buf(struct sk_buff *skb, uint32_t if_num,
+				struct nss_ctx_instance *nss_ctx)
+{
+	BUG_ON(!nss_gre_tunnel_verify_if_num(if_num));
+
+	return nss_core_send_packet(nss_ctx, skb, if_num, H2N_BIT_FLAG_VIRTUAL_BUFFER | H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+EXPORT_SYMBOL(nss_gre_tunnel_tx_buf);
+
+/*
+ * nss_gre_tunnel_tx_msg()
+ *	Transmit a gre_tunnel message to NSS firmware
+ */
+nss_tx_status_t nss_gre_tunnel_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_gre_tunnel_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_gre_tunnel_log_tx_msg(msg);
+
+	/*
+	 * Sanity check message
+	 */
+	if (ncm->type >= NSS_GRE_TUNNEL_MSG_MAX) {
+		nss_warning("%px: gre_tunnel message type out of range: %d",
+			nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	BUG_ON(!nss_gre_tunnel_verify_if_num(ncm->interface));
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_gre_tunnel_tx_msg);
+
+/*
+ * nss_gre_tunnel_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_gre_tunnel_callback(void *app_data, struct nss_gre_tunnel_msg *ngtm)
+{
+	nss_gre_tunnel_msg_callback_t callback = (nss_gre_tunnel_msg_callback_t)gre_tunnel_pvt.cb;
+	void *data = gre_tunnel_pvt.app_data;
+
+	gre_tunnel_pvt.response = NSS_TX_SUCCESS;
+	gre_tunnel_pvt.cb = NULL;
+	gre_tunnel_pvt.app_data = NULL;
+
+	if (ngtm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("gre tunnel Error response %d\n", ngtm->cm.response);
+		gre_tunnel_pvt.response = ngtm->cm.response;
+	}
+
+	if (callback) {
+		callback(data, ngtm);
+	}
+	complete(&gre_tunnel_pvt.complete);
+}
+
+/*
+ * nss_gre_tunnel_tx_msg()
+ *	Transmit a GRE Tunnel message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_gre_tunnel_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_tunnel_msg *ngtm)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&gre_tunnel_pvt.sem);
+	gre_tunnel_pvt.cb = (void *)ngtm->cm.cb;
+	gre_tunnel_pvt.app_data = (void *)ngtm->cm.app_data;
+
+	ngtm->cm.cb = (nss_ptr_t)nss_gre_tunnel_callback;
+	ngtm->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_gre_tunnel_tx_msg(nss_ctx, ngtm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: gre_tunnel_tx_msg failed\n", nss_ctx);
+		up(&gre_tunnel_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&gre_tunnel_pvt.complete, msecs_to_jiffies(NSS_GRE_TUNNEL_TX_TIMEOUT));
+
+	if (!ret) {
+		nss_warning("%px: GRE Tunnel msg tx failed due to timeout\n", nss_ctx);
+		gre_tunnel_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = gre_tunnel_pvt.response;
+	up(&gre_tunnel_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_gre_tunnel_tx_msg_sync);
+
+/*
+ * nss_gre_tunnel_msg_init()
+ *	Initialize gre_tunnel msg.
+ */
+void nss_gre_tunnel_msg_init(struct nss_gre_tunnel_msg *ngtm, uint16_t if_num,
+			uint32_t type, uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ngtm->cm, if_num, type, len, cb, app_data);
+}
+EXPORT_SYMBOL(nss_gre_tunnel_msg_init);
+
+/*
+ * nss_gre_tunnel_register_if()
+ *	Register netdev
+ */
+struct nss_ctx_instance *nss_gre_tunnel_register_if(uint32_t if_num,
+					      nss_gre_tunnel_data_callback_t cb,
+					      nss_gre_tunnel_msg_callback_t ev_cb,
+					      struct net_device *netdev,
+					      uint32_t features,
+					      void *app_ctx)
+{
+	int32_t i;
+
+	struct nss_ctx_instance *nss_ctx = nss_gre_tunnel_get_ctx();
+
+	BUG_ON(!nss_gre_tunnel_verify_if_num(if_num));
+
+	spin_lock_bh(&nss_gre_tunnel_stats_lock);
+	for (i = 0; i < NSS_MAX_GRE_TUNNEL_SESSIONS; i++) {
+		if (!session_stats[i].valid) {
+			session_stats[i].valid = true;
+			session_stats[i].if_num = if_num;
+			session_stats[i].if_index = netdev->ifindex;
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_gre_tunnel_stats_lock);
+
+	if (i == NSS_MAX_GRE_TUNNEL_SESSIONS) {
+		nss_warning("%px: Cannot find free slot for GRE Tunnel session stats, I/F:%u\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	if (nss_ctx->subsys_dp_register[if_num].ndev) {
+		nss_warning("%px: Cannot find free slot for GRE Tunnel NSS I/F:%u\n", nss_ctx, if_num);
+		session_stats[i].valid = false;
+		session_stats[i].if_num = 0;
+		session_stats[i].if_index = 0;
+		return NULL;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, cb, NULL, app_ctx, netdev, features);
+
+	nss_top_main.gre_tunnel_msg_callback = ev_cb;
+	nss_core_register_handler(nss_ctx, if_num, nss_gre_tunnel_handler, app_ctx);
+	nss_gre_tunnel_stats_dentry_create();
+	nss_gre_tunnel_strings_dentry_create();
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_gre_tunnel_register_if);
+
+/*
+ * nss_gre_tunnel_unregister_if()
+ *	Unregister netdev
+ */
+void nss_gre_tunnel_unregister_if(uint32_t if_num)
+{
+	int32_t i;
+	struct nss_ctx_instance *nss_ctx = nss_gre_tunnel_get_ctx();
+
+	BUG_ON(!nss_gre_tunnel_verify_if_num(if_num));
+
+	spin_lock_bh(&nss_gre_tunnel_stats_lock);
+	for (i = 0; i < NSS_MAX_GRE_TUNNEL_SESSIONS; i++) {
+		if (session_stats[i].if_num == if_num) {
+			memset(&session_stats[i], 0,
+				sizeof(struct nss_gre_tunnel_stats_session));
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_gre_tunnel_stats_lock);
+
+	if (i == NSS_MAX_GRE_TUNNEL_SESSIONS) {
+		nss_warning("%px: Cannot find debug stats for GRE Tunnel session: %d\n", nss_ctx, if_num);
+		return;
+	}
+
+	if (!nss_ctx->subsys_dp_register[if_num].ndev) {
+		nss_warning("%px: Cannot find registered netdev for GRE Tunnel NSS I/F: %d\n", nss_ctx, if_num);
+
+		return;
+	}
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	nss_top_main.gre_tunnel_msg_callback = NULL;
+	nss_core_unregister_handler(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_gre_tunnel_unregister_if);
diff --git a/qca-nss-drv/nss_gre_tunnel_log.c b/qca-nss-drv/nss_gre_tunnel_log.c
new file mode 100644
index 0000000..6af7b56
--- /dev/null
+++ b/qca-nss-drv/nss_gre_tunnel_log.c
@@ -0,0 +1,168 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_gre_tunnel_log.c
+ *	NSS GRE Tunnel logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_gre_tunnel_log_message_types_str
+ *	NSS GRE Tunnel message strings
+ */
+static int8_t *nss_gre_tunnel_log_message_types_str[NSS_GRE_TUNNEL_MSG_MAX] __maybe_unused = {
+	"GRE Tunnel configure",
+	"GRE Tunnel session destroy",
+	"GRE Tunnel stats",
+	"GRE Tunnel configure DI to WLAN ID",
+	"GRE Tunnel message inquiry"
+};
+
+/*
+ * nss_gre_tunnel_log_configure_msg()
+ *	Log NSS GRE Tunnel configure message.
+ */
+static void nss_gre_tunnel_log_configure_msg(struct nss_gre_tunnel_msg *ngm)
+{
+	struct nss_gre_tunnel_configure *ngcm __maybe_unused = &ngm->msg.configure;
+	nss_trace("%px: NSS GRE Tunnel configure message \n"
+		"Meta Header Version: %d\n"
+		"GRE Mode: %x\n"
+		"IP Type: %x\n"
+		"Encryption Type: %d\n"
+		"Source Port: %d\n"
+		"Destination Port: %d\n"
+		"Crypto Node Identifier: %d\n"
+		"Encryption Crypto Index: %d\n"
+		"Decryption Crypto Index: %d\n"
+		"Word0 header: %d\n"
+		"Initialization Vector: %px\n"
+		"Sibling Interface Number: %d\n"
+		"TTL: %d\n"
+		"RPS: %d\n"
+		"Reserved: %x\n"
+		"Word1 Header: %x\n"
+		"Word2 Header: %x\n"
+		"Word3 Header: %x\n",
+		ngcm, ngcm->mh_version, ngcm->gre_mode,
+		ngcm->ip_type, ngcm->encrypt_type,
+		ngcm->src_port, ngcm->dest_port,
+		ngcm->crypto_node_id, ngcm->crypto_idx_encrypt,
+		ngcm->crypto_idx_decrypt, ngcm->word0,
+		ngcm->iv_val, ngcm->sibling_if,
+		ngcm->ttl, ngcm->rps,
+		ngcm->reserved, ngcm->word1,
+		ngcm->word2, ngcm->word3);
+
+	/*
+	 * Continuation of log message. Different identifiers based on ip_type
+	 */
+	if (ngcm->ip_type == NSS_GRE_TUNNEL_IP_IPV6) {
+		nss_trace("Source IP: %pI6\n"
+			"Destination IP: %pI6\n",
+			ngcm->src_ip, ngcm->dest_ip);
+	} else if (ngcm->ip_type == NSS_GRE_TUNNEL_IP_IPV4) {
+		nss_trace("Source IP: %pI4\n"
+			"Destination IP: %pI4\n",
+			ngcm->src_ip, ngcm->dest_ip);
+	}
+}
+
+/*
+ * nss_gre_tunnel_log_di_to_wlan_id_msg()
+ *	Log NSS GRE Tunnel Dynamic Interface to WLAN ID message.
+ */
+static void nss_gre_tunnel_log_di_to_wlan_id_msg(struct nss_gre_tunnel_msg *ngm)
+{
+	struct nss_gre_tunnel_di_to_wlan_id *ngdm __maybe_unused = &ngm->msg.dtwi;
+	nss_trace("%px: NSS GRE Dynamic Interface to WLAN ID message: \n"
+		"Dynamic Interface Number: %d\n"
+		"WLAN ID: %x\n",
+		ngdm, ngdm->dynamic_interface_num,
+		ngdm->wlan_id);
+}
+
+/*
+ * nss_gre_tunnel_log_verbose()
+ *	Log message contents.
+ */
+static void nss_gre_tunnel_log_verbose(struct nss_gre_tunnel_msg *ngm)
+{
+	switch (ngm->cm.type) {
+	case NSS_GRE_TUNNEL_MSG_CONFIGURE:
+	case NSS_GRE_TUNNEL_MSG_INQUIRY:
+		nss_gre_tunnel_log_configure_msg(ngm);
+		break;
+
+	case NSS_GRE_TUNNEL_MSG_CONFIGURE_DI_TO_WLAN_ID:
+		nss_gre_tunnel_log_di_to_wlan_id_msg(ngm);
+		break;
+
+	case NSS_GRE_TUNNEL_MSG_SESSION_DESTROY:
+	case NSS_GRE_TUNNEL_MSG_STATS:
+		/*
+		 * No log for these valid messages.
+		 */
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", ngm);
+		break;
+	}
+}
+
+/*
+ * nss_gre_tunnel_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_gre_tunnel_log_tx_msg(struct nss_gre_tunnel_msg *ngm)
+{
+	if (ngm->cm.type >= NSS_GRE_TUNNEL_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", ngm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ngm, ngm->cm.type, nss_gre_tunnel_log_message_types_str[ngm->cm.type]);
+	nss_gre_tunnel_log_verbose(ngm);
+}
+
+/*
+ * nss_gre_tunnel_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_gre_tunnel_log_rx_msg(struct nss_gre_tunnel_msg *ngm)
+{
+	if (ngm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ngm);
+		return;
+	}
+
+	if (ngm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ngm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ngm, ngm->cm.type,
+			nss_gre_tunnel_log_message_types_str[ngm->cm.type],
+			ngm->cm.response, nss_cmn_response_str[ngm->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		ngm, ngm->cm.type, nss_gre_tunnel_log_message_types_str[ngm->cm.type],
+		ngm->cm.response, nss_cmn_response_str[ngm->cm.response]);
+
+verbose:
+	nss_gre_tunnel_log_verbose(ngm);
+}
diff --git a/qca-nss-drv/nss_gre_tunnel_log.h b/qca-nss-drv/nss_gre_tunnel_log.h
new file mode 100644
index 0000000..be07513
--- /dev/null
+++ b/qca-nss-drv/nss_gre_tunnel_log.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_GRE_TUNNEL_LOG_H
+#define __NSS_GRE_TUNNEL_LOG_H
+
+/*
+ * nss_gre_tunnel.h
+ *	NSS GRE Tunnel header file.
+ */
+
+/*
+ * Logger APIs
+ */
+
+/*
+ * nss_gre_tunnel_log_tx_msg
+ *	Logs a gre_tunnel message that is sent to the NSS firmware.
+ */
+void nss_gre_tunnel_log_tx_msg(struct nss_gre_tunnel_msg *ngm);
+
+/*
+ * nss_gre_tunnel_log_rx_msg
+ *	Logs a gre_tunnel message that is received from the NSS firmware.
+ */
+void nss_gre_tunnel_log_rx_msg(struct nss_gre_tunnel_msg *ngm);
+
+#endif /* __NSS_GRE_TUNNEL_LOG_H */
diff --git a/qca-nss-drv/nss_gre_tunnel_stats.c b/qca-nss-drv/nss_gre_tunnel_stats.c
new file mode 100644
index 0000000..c3e53bf
--- /dev/null
+++ b/qca-nss-drv/nss_gre_tunnel_stats.c
@@ -0,0 +1,282 @@
+/*
+ ****************************************************************************
+ * Copyright (c) 2017, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ****************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_gre_tunnel.h"
+#include "nss_gre_tunnel_stats.h"
+#include "nss_gre_tunnel_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_gre_tunnel_stats_notifier);
+
+/*
+ * Spinlock to protect gre tunnel statistics update/read
+ */
+DEFINE_SPINLOCK(nss_gre_tunnel_stats_lock);
+
+struct nss_gre_tunnel_stats_session session_stats[NSS_MAX_GRE_TUNNEL_SESSIONS];
+
+/*
+ * nss_gre_tunnel_stats_session_sync()
+ *	Sync function for GRE Tunnel statistics
+ */
+void nss_gre_tunnel_stats_session_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_tunnel_stats *stats_msg,
+					uint16_t if_num)
+{
+	int i;
+	struct nss_gre_tunnel_stats_session *s = NULL;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	spin_lock_bh(&nss_gre_tunnel_stats_lock);
+	for (i = 0; i < NSS_MAX_GRE_TUNNEL_SESSIONS; i++) {
+		if (session_stats[i].if_num == if_num) {
+			s = &session_stats[i];
+			break;
+		}
+	}
+
+	if (!s) {
+		spin_unlock_bh(&nss_gre_tunnel_stats_lock);
+		nss_warning("%px: Session not found: %u", nss_ctx, if_num);
+		return;
+	}
+
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_RX_PKTS] += stats_msg->node_stats.rx_packets;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_TX_PKTS] += stats_msg->node_stats.tx_packets;
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		s->stats[NSS_GRE_TUNNEL_STATS_SESSION_RX_QUEUE_0_DROPPED + i] += stats_msg->node_stats.rx_dropped[i];
+	}
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_RX_MALFORMED] += stats_msg->rx_malformed;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_RX_INVALID_PROT] += stats_msg->rx_invalid_prot;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_DECAP_QUEUE_FULL] += stats_msg->decap_queue_full;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_RX_SINGLE_REC_DGRAM] += stats_msg->rx_single_rec_dgram;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_RX_INVALID_REC_DGRAM] += stats_msg->rx_invalid_rec_dgram;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_BUFFER_ALLOC_FAIL] += stats_msg->buffer_alloc_fail;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_BUFFER_COPY_FAIL] += stats_msg->buffer_copy_fail;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_OUTFLOW_QUEUE_FULL] += stats_msg->outflow_queue_full;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_RX_DROPPED_HROOM] += stats_msg->rx_dropped_hroom;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_RX_CBUFFER_ALLOC_FAIL] += stats_msg->rx_cbuf_alloc_fail;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_RX_CENQUEUE_FAIL] += stats_msg->rx_cenqueue_fail;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_RX_DECRYPT_DONE] += stats_msg->rx_decrypt_done;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_RX_FORWARD_ENQUEUE_FAIL] += stats_msg->rx_forward_enqueue_fail;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_TX_CBUFFER_ALLOC_FAIL] += stats_msg->tx_cbuf_alloc_fail;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_TX_CENQUEUE_FAIL] += stats_msg->tx_cenqueue_fail;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_RX_DROPPED_TROOM] += stats_msg->rx_dropped_troom;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_TX_FORWARD_ENQUEUE_FAIL] += stats_msg->tx_forward_enqueue_fail;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_TX_CIPHER_DONE] += stats_msg->tx_cipher_done;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_CRYPTO_NOSUPP] += stats_msg->crypto_nosupp;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_RX_DROPPED_MH_VERSION] += stats_msg->rx_dropped_mh_ver;
+	s->stats[NSS_GRE_TUNNEL_STATS_SESSION_RX_UNALIGNED_PKT] += stats_msg->rx_unaligned_pkt;
+
+	/*
+	 * Copy crypto resp err stats.
+	 */
+	for (i = 0; i < NSS_CRYPTO_CMN_RESP_ERROR_MAX; i++) {
+#if defined(NSS_HAL_IPQ807x_SUPPORT)
+		s->stats[NSS_GRE_TUNNEL_STATS_SESSION_MAX + i] += stats_msg->crypto_resp_error[i];
+#else
+		s->stats[NSS_GRE_TUNNEL_STATS_SESSION_MAX + i] = 0;
+#endif
+	}
+
+	spin_unlock_bh(&nss_gre_tunnel_stats_lock);
+}
+
+/*
+ * nss_gre_tunnel_stats_session_get()
+ *	Get session GRE Tunnel statitics.
+ */
+static void nss_gre_tunnel_stats_session_get(struct nss_gre_tunnel_stats_session *stats)
+{
+	int i;
+
+	if (!stats) {
+		nss_warning("No memory to copy gre_tunnel session stats");
+		return;
+	}
+
+	spin_lock_bh(&nss_gre_tunnel_stats_lock);
+	for (i = 0; i < NSS_MAX_GRE_TUNNEL_SESSIONS; i++) {
+		if (session_stats[i].valid) {
+			memcpy(stats, &session_stats[i],
+				sizeof(struct nss_gre_tunnel_stats_session));
+			stats++;
+		}
+	}
+	spin_unlock_bh(&nss_gre_tunnel_stats_lock);
+}
+
+/*
+ * nss_gre_tunnel_stats_read()
+ *	Read GRE Tunnel session statistics
+ */
+static ssize_t nss_gre_tunnel_stats_read(struct file *fp, char __user *ubuf,
+					size_t sz, loff_t *ppos)
+{
+	uint32_t max_output_lines = 2 + (NSS_MAX_GRE_TUNNEL_SESSIONS
+					* (NSS_GRE_TUNNEL_STATS_SESSION_MAX + 2)) + 2;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+	struct net_device *dev;
+	int id, i;
+	struct nss_gre_tunnel_stats_session *gre_tunnel_session_stats = NULL;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_CRYPTO_CMN_RESP_ERROR_MAX * 8, GFP_KERNEL);
+	if (unlikely(!stats_shadow)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	gre_tunnel_session_stats = kzalloc((sizeof(struct nss_gre_tunnel_stats_session)
+						* NSS_MAX_GRE_TUNNEL_SESSIONS), GFP_KERNEL);
+	if (unlikely(gre_tunnel_session_stats == NULL)) {
+		nss_warning("Could not allocate memory for populating GRE Tunnel stats");
+		kfree(lbuf);
+		kfree(stats_shadow);
+		return 0;
+	}
+
+	/*
+	 * Get all stats
+	 */
+	nss_gre_tunnel_stats_session_get(gre_tunnel_session_stats);
+
+	/*
+	 * Session stats
+	 */
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "GRE tunnel stats", NSS_STATS_SINGLE_CORE);
+
+	for (id = 0; id < NSS_MAX_GRE_TUNNEL_SESSIONS; id++) {
+		if (!gre_tunnel_session_stats[id].valid)
+			break;
+
+		dev = dev_get_by_index(&init_net, gre_tunnel_session_stats[id].if_index);
+		if (likely(dev)) {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+						"%d. nss interface id=%d, netdevice=%s\n",
+						id, gre_tunnel_session_stats[id].if_num,
+						dev->name);
+			dev_put(dev);
+		} else {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+						"%d. nss interface id=%d\n", id,
+						gre_tunnel_session_stats[id].if_num);
+		}
+
+		size_wr += nss_stats_print("gre_tunnel", NULL, NSS_STATS_SINGLE_INSTANCE,
+					nss_gre_tunnel_strings_stats, gre_tunnel_session_stats[id].stats,
+					NSS_GRE_TUNNEL_STATS_SESSION_MAX, lbuf, size_wr, size_al);
+
+		/*
+		 * Print crypto resp err stats.
+		 * TODO: We are not printing with the right enum string for crypto. This
+		 * is intentional since we atleast want to see some stats for now.
+		 */
+		spin_lock_bh(&nss_gre_tunnel_stats_lock);
+		for (i = 0; i < NSS_CRYPTO_CMN_RESP_ERROR_MAX; i++) {
+			stats_shadow[i] = gre_tunnel_session_stats[id].stats[NSS_GRE_TUNNEL_STATS_SESSION_MAX + i];
+		}
+
+		spin_unlock_bh(&nss_gre_tunnel_stats_lock);
+		size_wr += nss_stats_print("gre_tunnel", NULL, NSS_STATS_SINGLE_INSTANCE,
+					nss_gre_tunnel_strings_stats, stats_shadow,
+					NSS_CRYPTO_CMN_RESP_ERROR_MAX, lbuf, size_wr, size_al);
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	kfree(gre_tunnel_session_stats);
+	kfree(lbuf);
+	kfree(stats_shadow);
+	return bytes_read;
+}
+
+/*
+ * nss_gre_tunnel_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(gre_tunnel)
+
+/*
+ * nss_gre_tunnel_stats_dentry_create()
+ *	Create gre tunnel statistics debug entry.
+ */
+void nss_gre_tunnel_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("gre_tunnel", &nss_gre_tunnel_stats_ops);
+}
+
+/*
+ * nss_gre_tunnel_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_gre_tunnel_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_gre_tunnel_stats_notification gre_tunnel_stats;
+	struct nss_gre_tunnel_stats_session *s = NULL;
+	int i;
+
+	spin_lock_bh(&nss_gre_tunnel_stats_lock);
+	for (i = 0; i < NSS_MAX_GRE_TUNNEL_SESSIONS; i++) {
+		if (session_stats[i].if_num != if_num) {
+			continue;
+		}
+
+		s = &session_stats[i];
+		gre_tunnel_stats.core_id = nss_ctx->id;
+		gre_tunnel_stats.if_num = if_num;
+		memcpy(gre_tunnel_stats.stats_ctx, s->stats, sizeof(gre_tunnel_stats.stats_ctx));
+		spin_unlock_bh(&nss_gre_tunnel_stats_lock);
+		atomic_notifier_call_chain(&nss_gre_tunnel_stats_notifier, NSS_STATS_EVENT_NOTIFY, &gre_tunnel_stats);
+		return;
+	}
+	spin_unlock_bh(&nss_gre_tunnel_stats_lock);
+}
+
+/*
+ * nss_gre_tunnel_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_gre_tunnel_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_gre_tunnel_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_gre_tunnel_stats_unregister_notifier);
+
+/*
+ * nss_gre_tunnel_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_gre_tunnel_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_gre_tunnel_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_gre_tunnel_stats_register_notifier);
diff --git a/qca-nss-drv/nss_gre_tunnel_stats.h b/qca-nss-drv/nss_gre_tunnel_stats.h
new file mode 100644
index 0000000..cdee478
--- /dev/null
+++ b/qca-nss-drv/nss_gre_tunnel_stats.h
@@ -0,0 +1,44 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2016-2017, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_GRE_TUNNEL_STATS_H
+#define __NSS_GRE_TUNNEL_STATS_H
+
+/*
+ * GRE Tunnel session debug statistics
+ */
+struct nss_gre_tunnel_stats_session {
+	uint64_t stats[NSS_GRE_TUNNEL_STATS_SESSION_MAX + NSS_CRYPTO_CMN_RESP_ERROR_MAX];
+				/* GRE tunnel statistics */
+	int32_t if_index;	/* Interface index */
+	uint32_t if_num;	/* NSS interface number */
+	bool valid;
+};
+
+/*
+ * Data structures to store GRE Tunnel nss debug stats
+ */
+extern spinlock_t nss_gre_tunnel_stats_lock;
+extern struct nss_gre_tunnel_stats_session session_stats[NSS_MAX_GRE_TUNNEL_SESSIONS];
+
+/*
+ * GRE Tunnel statistics APIs
+ */
+extern void nss_gre_tunnel_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_gre_tunnel_stats_session_sync(struct nss_ctx_instance *nss_ctx, struct nss_gre_tunnel_stats *stats_msg, uint16_t if_num);
+extern void nss_gre_tunnel_stats_dentry_create(void);
+
+#endif /* __NSS_GRE_TUNNEL_STATS_H */
diff --git a/qca-nss-drv/nss_gre_tunnel_strings.c b/qca-nss-drv/nss_gre_tunnel_strings.c
new file mode 100644
index 0000000..402182e
--- /dev/null
+++ b/qca-nss-drv/nss_gre_tunnel_strings.c
@@ -0,0 +1,77 @@
+/*
+ ****************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ****************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_gre_tunnel_strings.h"
+
+/*
+ * nss_gre_tunnel_strings_stats
+ *	GRE Tunnel statistics strings for nss session stats
+ */
+struct nss_stats_info nss_gre_tunnel_strings_stats[NSS_GRE_TUNNEL_STATS_SESSION_MAX] = {
+	{"rx_pkts",			NSS_STATS_TYPE_COMMON},
+	{"tx_pkts",			NSS_STATS_TYPE_COMMON},
+	{"rx_queue_0_dropped",		NSS_STATS_TYPE_DROP},
+	{"rx_queue_1_dropped",		NSS_STATS_TYPE_DROP},
+	{"rx_queue_2_dropped",		NSS_STATS_TYPE_DROP},
+	{"rx_queue_3_dropped",		NSS_STATS_TYPE_DROP},
+	{"rx_malformed",		NSS_STATS_TYPE_SPECIAL},
+	{"rx_invalid_prot",		NSS_STATS_TYPE_SPECIAL},
+	{"decap_queue_full",		NSS_STATS_TYPE_SPECIAL},
+	{"rx_single_rec_dgram",		NSS_STATS_TYPE_SPECIAL},
+	{"rx_invalid_rec_dgram",	NSS_STATS_TYPE_SPECIAL},
+	{"buffer_alloc_fail",		NSS_STATS_TYPE_SPECIAL},
+	{"buffer_copy_fail",		NSS_STATS_TYPE_SPECIAL},
+	{"outflow_queue_full",		NSS_STATS_TYPE_SPECIAL},
+	{"tx_dropped_hroom",		NSS_STATS_TYPE_DROP},
+	{"rx_cbuffer_alloc_fail",	NSS_STATS_TYPE_SPECIAL},
+	{"rx_cenqueue_fail",		NSS_STATS_TYPE_SPECIAL},
+	{"rx_decrypt_done",		NSS_STATS_TYPE_SPECIAL},
+	{"rx_forward_enqueue_fail",	NSS_STATS_TYPE_SPECIAL},
+	{"tx_cbuffer_alloc_fail",	NSS_STATS_TYPE_SPECIAL},
+	{"tx_cenqueue_fail",		NSS_STATS_TYPE_SPECIAL},
+	{"rx_dropped_troom",		NSS_STATS_TYPE_DROP},
+	{"tx_forward_enqueue_fail",	NSS_STATS_TYPE_SPECIAL},
+	{"tx_cipher_done",		NSS_STATS_TYPE_SPECIAL},
+	{"crypto_nosupp",		NSS_STATS_TYPE_SPECIAL},
+	{"rx_dropped_mh_version",	NSS_STATS_TYPE_SPECIAL},
+	{"rx_unaligned_pkt",		NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_gre_tunnel_strings_read()
+ *	Read gre_tunnel session debug statistics names
+ */
+static ssize_t nss_gre_tunnel_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_gre_tunnel_strings_stats, NSS_GRE_TUNNEL_STATS_SESSION_MAX);
+}
+
+/*
+ * nss_gre_tunnel_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(gre_tunnel);
+
+/*
+ * nss_gre_tunnel_strings_dentry_create()
+ *	Create gre_tunnel statistics strings debug entry.
+ */
+void nss_gre_tunnel_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("gre_tunnel", &nss_gre_tunnel_strings_ops);
+}
diff --git a/qca-nss-drv/nss_gre_tunnel_strings.h b/qca-nss-drv/nss_gre_tunnel_strings.h
new file mode 100644
index 0000000..8294694
--- /dev/null
+++ b/qca-nss-drv/nss_gre_tunnel_strings.h
@@ -0,0 +1,25 @@
+/*
+ ****************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ****************************************************************************
+ */
+
+#ifndef __NSS_GRE_TUNNEL_STRINGS_H
+#define __NSS_GRE_TUNNEL_STRINGS_H
+
+#include "nss_gre_tunnel_stats.h"
+
+extern struct nss_stats_info nss_gre_tunnel_strings_stats[NSS_GRE_TUNNEL_STATS_SESSION_MAX];
+extern void nss_gre_tunnel_strings_dentry_create(void);
+
+#endif /* __NSS_GRE_TUNNEL_STRINGS_H */
diff --git a/qca-nss-drv/nss_hal/fsm9010/nss_hal_pvt.c b/qca-nss-drv/nss_hal/fsm9010/nss_hal_pvt.c
new file mode 100644
index 0000000..4a72d3d
--- /dev/null
+++ b/qca-nss-drv/nss_hal/fsm9010/nss_hal_pvt.c
@@ -0,0 +1,342 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_hal_pvt.c
+ *	NSS HAL private APIs.
+ */
+
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include "nss_hal.h"
+#include "nss_core.h"
+
+#define NSS_H2N_INTR_EMPTY_BUFFER_QUEUE_BIT     0
+#define NSS_H2N_INTR_DATA_COMMAND_QUEUE_BIT     1
+#define NSS_H2N_INTR_TX_UNBLOCKED_BIT           11
+#define NSS_H2N_INTR_TRIGGER_COREDUMP_BIT       15
+
+/*
+ * Interrupt type to cause vector.
+ */
+static uint32_t intr_cause[] = {(1 << NSS_H2N_INTR_EMPTY_BUFFER_QUEUE_BIT),
+				(1 << NSS_H2N_INTR_DATA_COMMAND_QUEUE_BIT),
+				(1 << NSS_H2N_INTR_TX_UNBLOCKED_BIT),
+				(1 << NSS_H2N_INTR_TRIGGER_COREDUMP_BIT)};
+
+/*
+ * nss_hal_wq_function()
+ *	Added to Handle BH requests to kernel
+ */
+void nss_hal_wq_function(struct work_struct *work)
+{
+	/*
+	 * Not supported in FSM9010
+	 */
+	kfree((void *)work);
+}
+
+/*
+ * nss_hal_get_num_irqs()
+ *	get number of irqs from interrupt resource of device tree
+ */
+static inline int nss_hal_get_num_irqs(struct device_node *np)
+{
+	int num_irqs = 0;
+
+	while (of_irq_to_resource(np, num_irqs, NULL)) {
+		num_irqs++;
+	}
+
+	return num_irqs;
+}
+
+/*
+ * nss_hal_handle_irq()
+ *	HLOS interrupt handler for nss interrupts
+ */
+static irqreturn_t nss_hal_handle_irq(int irq, void *ctx)
+{
+	struct int_ctx_instance *int_ctx = (struct int_ctx_instance *) ctx;
+	struct nss_ctx_instance *nss_ctx = int_ctx->nss_ctx;
+
+	/*
+	 * Mask interrupt until our bottom half re-enables it
+	 */
+	nss_hal_disable_interrupt(nss_ctx, int_ctx->shift_factor, NSS_HAL_SUPPORTED_INTERRUPTS);
+
+	/*
+	 * Schedule tasklet to process interrupt cause
+	 */
+	napi_schedule(&int_ctx->napi);
+	return IRQ_HANDLED;
+}
+
+/*
+ * nss_hal_of_get_pdata()
+ *	Retrieve platform data from device node.
+ */
+static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device *pdev)
+{
+	struct device_node *np = of_node_get(pdev->dev.of_node);
+	struct nss_platform_data *npd = NULL;
+	struct nss_ctx_instance *nss_ctx = NULL;
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct resource res_nphys, res_vphys;
+	int32_t i;
+
+	npd = devm_kzalloc(&pdev->dev, sizeof(struct nss_platform_data), GFP_KERNEL);
+	if (!npd) {
+		return NULL;
+	}
+
+	if (of_property_read_u32(np, "qcom,id", &npd->id)
+	    || of_property_read_u32(np, "qcom,num-queue", &npd->num_queue)) {
+		pr_err("%s: error reading critical device node properties\n", np->name);
+		goto out;
+	}
+
+	if (of_property_read_u32(np, "qcom,num-irq", &npd->num_irq)) {
+		npd->num_irq = nss_hal_get_num_irqs(np);
+	}
+
+	if (npd->num_irq < npd->num_queue) {
+		pr_err("%s: not enough interrupts configured for all the queues\n", np->name);
+		goto out;
+	}
+
+	if (npd->num_irq > NSS_MAX_IRQ_PER_CORE) {
+		pr_err("%s: exceeds maximum interrupt numbers per core\n", np->name);
+		goto out;
+	}
+
+	nss_ctx = &nss_top->nss[npd->id];
+	nss_ctx->id = npd->id;
+
+	if (of_address_to_resource(np, 0, &res_nphys) != 0) {
+		nss_info_always("%px: nss%d: of_address_to_resource() fail for nphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	if (of_address_to_resource(np, 1, &res_vphys) != 0) {
+		nss_info_always("%px: nss%d: of_address_to_resource() fail for vphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	/*
+	 * Save physical addresses
+	 */
+	npd->nphys = res_nphys.start;
+	npd->vphys = res_vphys.start;
+
+	npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys));
+	if (!npd->nmap) {
+		nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	nss_assert(npd->vphys);
+	npd->vmap = ioremap_cache(npd->vphys, resource_size(&res_vphys));
+	if (!npd->vmap) {
+		nss_info_always("%px: nss%d: ioremap() fail for vphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	/*
+	 * Get IRQ numbers
+	 */
+	for (i = 0 ; i < npd->num_irq; i++) {
+		npd->irq[i] = irq_of_parse_and_map(np, i);
+		if (!npd->irq[i]) {
+			nss_info_always("%px: nss%d: irq_of_parse_and_map() fail for irq %d\n", nss_ctx, nss_ctx->id, i);
+			goto out;
+		}
+	}
+
+	nss_hal_dt_parse_features(np, npd);
+
+	of_node_put(np);
+	return npd;
+
+out:
+	if (npd->nmap) {
+		iounmap((void *)npd->nmap);
+	}
+
+	if (npd->vmap) {
+		iounmap((void *)npd->vmap);
+	}
+
+	devm_kfree(&pdev->dev, npd);
+	of_node_put(np);
+	return NULL;
+}
+
+/*
+ * __nss_hal_debug_enable()
+ *	Enable NSS debug
+ */
+static void __nss_hal_debug_enable(void)
+{
+	return;
+}
+
+/*
+ * __nss_hal_common_reset()
+ */
+static int __nss_hal_common_reset(struct platform_device *nss_dev)
+{
+	return 0;
+}
+
+/*
+ * __nss_hal_core_reset()
+ */
+static int __nss_hal_core_reset(struct platform_device *nss_dev, void __iomem *map, uint32_t addr, uint32_t clk_src)
+{
+	return 0;
+}
+
+/*
+ * __nss_hal_firmware_load()
+ */
+static int __nss_hal_firmware_load(struct nss_ctx_instance *nss_ctx, struct platform_device *nss_dev, struct nss_platform_data *npd)
+{
+	return 0;
+}
+
+/*
+ * __nss_hal_clock_configure()
+ */
+static int __nss_hal_clock_configure(struct nss_ctx_instance *nss_ctx, struct platform_device *nss_dev, struct nss_platform_data *npd)
+{
+	return 0;
+}
+
+/*
+ * __nss_hal_read_interrupt_cause()
+ */
+static void __nss_hal_read_interrupt_cause(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t *cause)
+{
+	uint32_t value = nss_read_32(nss_ctx->nmap, NSS_REGS_N2H_INTR_STATUS_OFFSET);
+	*cause = (((value) >> shift_factor) & 0x7FFF);
+}
+
+/*
+ * __nss_hal_clear_interrupt_cause()
+ */
+static void __nss_hal_clear_interrupt_cause(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+	nss_write_32(nss_ctx->nmap, NSS_REGS_N2H_INTR_CLR_OFFSET, (cause << shift_factor));
+}
+
+/*
+ * __nss_hal_disable_interrupt()
+ */
+static void __nss_hal_disable_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+	nss_write_32(nss_ctx->nmap, NSS_REGS_N2H_INTR_MASK_CLR_OFFSET, (cause << shift_factor));
+}
+
+/*
+ * __nss_hal_enable_interrupt()
+ */
+static void __nss_hal_enable_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+	nss_write_32(nss_ctx->nmap, NSS_REGS_N2H_INTR_MASK_SET_OFFSET, (cause << shift_factor));
+}
+
+/*
+ * __nss_hal_send_interrupt()
+ */
+static void __nss_hal_send_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t type)
+{
+	nss_write_32(nss_ctx->nmap, NSS_REGS_C2C_INTR_SET_OFFSET, intr_cause[type]);
+}
+
+/*
+ * __nss_hal_request_irq()
+ */
+static int __nss_hal_request_irq(struct nss_ctx_instance *nss_ctx, struct nss_platform_data *npd, int irq_num)
+{
+	struct int_ctx_instance *int_ctx = &nss_ctx->int_ctx[irq_num];
+	int err;
+
+	if (irq_num == 1) {
+		int_ctx->shift_factor = 15;
+		err = request_irq(npd->irq[irq_num], nss_hal_handle_irq, 0, "nss_queue1", int_ctx);
+	} else {
+		int_ctx->shift_factor = 0;
+		err = request_irq(npd->irq[irq_num], nss_hal_handle_irq, 0, "nss", int_ctx);
+	}
+	if (err) {
+		nss_warning("%px: IRQ%d request failed", nss_ctx, npd->irq[irq_num]);
+		return err;
+	}
+
+	int_ctx->irq = npd->irq[irq_num];
+	netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi, 64);
+	return 0;
+}
+
+/*
+ * __nss_hal_init_imem
+ */
+void __nss_hal_init_imem(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
+
+	mem_ctx->imem_head = NSS_IMEM_START + NSS_IMEM_SIZE * nss_ctx->id;
+	mem_ctx->imem_end = mem_ctx->imem_head + NSS_IMEM_SIZE;
+	mem_ctx->imem_tail = mem_ctx->imem_head;
+
+	nss_info("%px: IMEM init: head: 0x%x end: 0x%x tail: 0x%x\n", nss_ctx,
+			mem_ctx->imem_head, mem_ctx->imem_end, mem_ctx->imem_tail);
+}
+
+/*
+ * __nss_hal_init_utcm_shared
+ */
+bool __nss_hal_init_utcm_shared(struct nss_ctx_instance *nss_ctx, uint32_t *meminfo_start)
+{
+	/*
+	 * Nothing to be done as there are no UTCM_SHARED defined for fsm9010
+	 */
+	return true;
+}
+
+/*
+ * nss_hal_fsm9010_ops
+ */
+struct nss_hal_ops nss_hal_fsm9010_ops = {
+	.common_reset = __nss_hal_common_reset,
+	.core_reset = __nss_hal_core_reset,
+	.clock_configure = __nss_hal_clock_configure,
+	.firmware_load = __nss_hal_firmware_load,
+	.debug_enable = __nss_hal_debug_enable,
+	.of_get_pdata = __nss_hal_of_get_pdata,
+	.request_irq = __nss_hal_request_irq,
+	.send_interrupt = __nss_hal_send_interrupt,
+	.enable_interrupt = __nss_hal_enable_interrupt,
+	.disable_interrupt = __nss_hal_disable_interrupt,
+	.clear_interrupt_cause = __nss_hal_clear_interrupt_cause,
+	.read_interrupt_cause = __nss_hal_read_interrupt_cause,
+	.init_imem = __nss_hal_init_imem,
+	.init_utcm_shared = __nss_hal_init_utcm_shared,
+};
diff --git a/qca-nss-drv/nss_hal/include/nss_hal.h b/qca-nss-drv/nss_hal/include/nss_hal.h
new file mode 100644
index 0000000..d9591a7
--- /dev/null
+++ b/qca-nss-drv/nss_hal/include/nss_hal.h
@@ -0,0 +1,129 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013, 2016-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_hal.h
+ *	NSS HAL public declarations.
+ */
+
+#ifndef __NSS_HAL_H
+#define __NSS_HAL_H
+
+#include <linux/platform_device.h>
+#include <nss_core.h>
+#include <nss_regs.h>
+#include <nss_hal_ops.h>
+
+extern struct clk *nss_core0_clk;
+extern struct clk *nss_core1_clk;
+extern struct nss_runtime_sampling nss_runtime_samples;
+extern struct clk *nss_fab0_clk;
+extern struct clk *nss_fab1_clk;
+extern void nss_hal_wq_function(struct work_struct *work);
+
+#if defined(NSS_HAL_IPQ806X_SUPPORT)
+extern struct nss_hal_ops nss_hal_ipq806x_ops;
+#endif
+#if defined(NSS_HAL_IPQ807x_SUPPORT)
+extern struct nss_hal_ops nss_hal_ipq807x_ops;
+#endif
+#if defined(NSS_HAL_IPQ60XX_SUPPORT)
+extern struct nss_hal_ops nss_hal_ipq60xx_ops;
+#endif
+#if defined(NSS_HAL_IPQ50XX_SUPPORT)
+extern struct nss_hal_ops nss_hal_ipq50xx_ops;
+#endif
+#if defined(NSS_HAL_FSM9010_SUPPORT)
+extern struct nss_hal_ops nss_hal_fsm9010_ops;
+#endif
+
+#define NSS_HAL_SUPPORTED_INTERRUPTS (NSS_N2H_INTR_EMPTY_BUFFER_QUEUE | \
+					NSS_N2H_INTR_DATA_QUEUE_0 | \
+					NSS_N2H_INTR_DATA_QUEUE_1 | \
+					NSS_N2H_INTR_EMPTY_BUFFERS_SOS | \
+					NSS_N2H_INTR_TX_UNBLOCKED | \
+					NSS_N2H_INTR_COREDUMP_COMPLETE | \
+					NSS_N2H_INTR_PROFILE_DMA | \
+					NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS)
+
+/*
+ * nss_hal_read_interrupt_cause()
+ */
+static inline void nss_hal_read_interrupt_cause(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t *cause)
+{
+	nss_top_main.hal_ops->read_interrupt_cause(nss_ctx, shift_factor, cause);
+}
+
+/*
+ * nss_hal_clear_interrupt_cause()
+ */
+static inline void nss_hal_clear_interrupt_cause(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+	nss_top_main.hal_ops->clear_interrupt_cause(nss_ctx, shift_factor, cause);
+}
+
+/*
+ * nss_hal_disable_interrupt()
+ */
+static inline void nss_hal_disable_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+	nss_top_main.hal_ops->disable_interrupt(nss_ctx, shift_factor, cause);
+}
+
+/*
+ * nss_hal_enable_interrupt()
+ */
+static inline void nss_hal_enable_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+	nss_top_main.hal_ops->enable_interrupt(nss_ctx, shift_factor, cause);
+}
+
+/*
+ * nss_hal_send_interrupt()
+ */
+static inline void nss_hal_send_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t cause)
+{
+	nss_top_main.hal_ops->send_interrupt(nss_ctx, cause);
+}
+
+/*
+ * nss_hal_debug_enable()
+ */
+static inline void nss_hal_debug_enable(void)
+{
+	nss_top_main.hal_ops->debug_enable();
+}
+
+/*
+ * nss_hal_probe()
+ */
+int nss_hal_probe(struct platform_device *nss_dev);
+
+/*
+ * nss_hal_remove()
+ */
+int nss_hal_remove(struct platform_device *nss_dev);
+
+/*
+ * nss_hal_firmware_load()
+ */
+int nss_hal_firmware_load(struct nss_ctx_instance *nss_ctx, struct platform_device *nss_dev, struct nss_platform_data *npd);
+
+/*
+ * nss_hal_dt_parse_features()
+ */
+void nss_hal_dt_parse_features(struct device_node *np, struct nss_platform_data *npd);
+#endif /* __NSS_HAL_H */
diff --git a/qca-nss-drv/nss_hal/include/nss_hal_ops.h b/qca-nss-drv/nss_hal/include/nss_hal_ops.h
new file mode 100644
index 0000000..736d37e
--- /dev/null
+++ b/qca-nss-drv/nss_hal/include/nss_hal_ops.h
@@ -0,0 +1,49 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_hal_ops.h
+ *	NSS HAL ops structure declaration.
+ */
+
+#ifndef __NSS_HAL_OPS_H
+#define __NSS_HAL_OPS_H
+
+#if (NSS_DT_SUPPORT != 1)
+#include <mach/gpiomux.h>
+#include <mach/msm_nss.h>
+#endif
+
+/*
+ * nss_hal_ops defines the HAL layer API required to support multiple targets
+ */
+struct nss_hal_ops {
+	int (*common_reset)(struct platform_device *pdev);
+	int (*core_reset)(struct platform_device *nss_dev, void __iomem *map, uint32_t addr, uint32_t clk_src);
+	int (*clock_configure)(struct nss_ctx_instance *nss_ctx, struct platform_device *nss_dev, struct nss_platform_data *npd);
+	void (*debug_enable)(void);
+	struct nss_platform_data * (*of_get_pdata)(struct platform_device *pdev);
+	int (*firmware_load)(struct nss_ctx_instance *nss_ctx, struct platform_device *nss_dev, struct nss_platform_data *npd);
+	void (*read_interrupt_cause)(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t *cause);
+	int (*request_irq)(struct nss_ctx_instance *nss_ctx, struct nss_platform_data *npd, int irq_num);
+	void (*clear_interrupt_cause)(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause);
+	void (*send_interrupt)(struct nss_ctx_instance *nss_ctx, uint32_t type);
+	void (*enable_interrupt)(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause);
+	void (*disable_interrupt)(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause);
+	void (*init_imem)(struct nss_ctx_instance *nss_ctx);
+	bool (*init_utcm_shared)(struct nss_ctx_instance *nss_ctx, uint32_t *meminfo_start);
+};
+#endif /* __NSS_HAL_OPS_H */
diff --git a/qca-nss-drv/nss_hal/include/nss_regs.h b/qca-nss-drv/nss_hal/include/nss_regs.h
new file mode 100644
index 0000000..765e8a1
--- /dev/null
+++ b/qca-nss-drv/nss_hal/include/nss_regs.h
@@ -0,0 +1,108 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013, 2015-2017, 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_regs.h
+ *	NSS register definitions.
+ */
+
+#ifndef __NSS_REGS_H
+#define __NSS_REGS_H
+
+#include <linux/types.h>
+#include <linux/io.h>
+
+/*
+ * CSM register offsets
+ */
+#define NSS_REGS_CORE_ID_OFFSET			0x0000
+#define NSS_REGS_RESET_CTRL_OFFSET		0x0004
+#define NSS_REGS_CORE_BAR_OFFSET		0x0008
+#define NSS_REGS_CORE_AMC_OFFSET		0x000c
+#define NSS_REGS_CORE_BOOT_ADDR_OFFSET		0x0010
+#define NSS_REGS_C2C_INTR_STATUS_OFFSET		0x0014
+#define NSS_REGS_C2C_INTR_SET_OFFSET		0x0018
+#define NSS_REGS_C2C_INTR_CLR_OFFSET		0x001c
+#define NSS_REGS_N2H_INTR_STATUS_OFFSET		0x0020
+#define NSS_REGS_N2H_INTR_SET_OFFSET		0x0024
+#define NSS_REGS_N2H_INTR_CLR_OFFSET		0x0028
+#define NSS_REGS_N2H_INTR_MASK_OFFSET		0x002c
+#define NSS_REGS_N2H_INTR_MASK_SET_OFFSET	0x0030
+#define NSS_REGS_N2H_INTR_MASK_CLR_OFFSET	0x0034
+#define NSS_REGS_CORE_INT_STAT0_TYPE_OFFSET	0x0038
+#define NSS_REGS_CORE_INT_STAT1_TYPE_OFFSET	0x003c
+#define NSS_REGS_CORE_INT_STAT2_TYPE_OFFSET	0x0040
+#define NSS_REGS_CORE_INT_STAT3_TYPE_OFFSET	0x0044
+#define NSS_REGS_CORE_IFETCH_RANGE_OFFSET	0x0048
+
+/*
+ * FPB register offsets
+ */
+#define NSS_REGS_FPB_CSR_CFG_OFFSET		0x0004
+
+/*
+ * Defines for N2H interrupts
+ */
+#define NSS_N2H_INTR_EMPTY_BUFFER_QUEUE		(1 << 0)
+#define NSS_N2H_INTR_DATA_QUEUE_0		(1 << 1)
+#define NSS_N2H_INTR_DATA_QUEUE_1		(1 << 2)
+#define NSS_N2H_INTR_DATA_QUEUE_2		(1 << 3)
+#define NSS_N2H_INTR_DATA_QUEUE_3		(1 << 4)
+#define NSS_N2H_INTR_EMPTY_BUFFERS_SOS		(1 << 10)
+#define NSS_N2H_INTR_TX_UNBLOCKED		(1 << 11)
+#define NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS	(1 << 12)
+#define NSS_N2H_INTR_PROFILE_DMA		(1 << 13)
+#define NSS_N2H_INTR_COREDUMP_COMPLETE		(1 << 14)
+
+/*
+ * Types of H2N interrupts
+ */
+enum nss_h2n_intr_type {
+	NSS_H2N_INTR_EMPTY_BUFFER_QUEUE = 0,
+	NSS_H2N_INTR_DATA_COMMAND_QUEUE = 1,
+	NSS_H2N_INTR_TX_UNBLOCKED = 2,
+	NSS_H2N_INTR_TRIGGER_COREDUMP = 3,
+	NSS_H2N_INTR_EMPTY_PAGED_BUFFER_QUEUE = 4,
+	NSS_H2N_INTR_TYPE_MAX = 5,
+};
+
+/*
+ * clock source for NSS cores
+ */
+enum nss_regs_clk_src_select {
+	NSS_REGS_CLK_SRC_DEFAULT,
+	NSS_REGS_CLK_SRC_ALTERNATE
+};
+
+/*
+ * nss_read_32()
+ *	Read NSS register
+ */
+static inline uint32_t nss_read_32(void __iomem *addr, uint32_t offs)
+{
+	return readl(addr + offs);
+}
+
+/*
+ * nss_write_32()
+ *	Write NSS register
+ */
+static inline void nss_write_32(void __iomem *addr, uint32_t offs, uint32_t val)
+{
+	writel(val, addr + offs);
+}
+
+#endif /* __NSS_REGS_H */
diff --git a/qca-nss-drv/nss_hal/ipq50xx/nss_hal_pvt.c b/qca-nss-drv/nss_hal/ipq50xx/nss_hal_pvt.c
new file mode 100644
index 0000000..3d6dfd0
--- /dev/null
+++ b/qca-nss-drv/nss_hal/ipq50xx/nss_hal_pvt.c
@@ -0,0 +1,667 @@
+/*
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/**
+ * nss_hal_pvt.c
+ *	NSS HAL private APIs.
+ */
+
+#include <linux/err.h>
+#include <linux/version.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include "nss_hal.h"
+#include "nss_core.h"
+
+#define NSS_QGIC_IPC_REG_OFFSET 0x8
+
+#define NSS0_H2N_INTR_BASE 13
+
+/*
+ * N2H interrupts
+ */
+#define NSS_IRQ_NAME_EMPTY_BUF_SOS "nss_empty_buf_sos"
+#define NSS_IRQ_NAME_EMPTY_BUF_QUEUE "nss_empty_buf_queue"
+#define NSS_IRQ_NAME_TX_UNBLOCK "nss-tx-unblock"
+#define NSS_IRQ_NAME_QUEUE0 "nss_queue0"
+#define NSS_IRQ_NAME_QUEUE1 "nss_queue1"
+#define NSS_IRQ_NAME_COREDUMP_COMPLETE "nss_coredump_complete"
+#define NSS_IRQ_NAME_PAGED_EMPTY_BUF_SOS "nss_paged_empty_buf_sos"
+#define NSS_IRQ_NAME_PROFILE_DMA "nss_profile_dma"
+
+/*
+ * CLKs
+ */
+#define NSS_CFG_CLK "nss-cfg-clk"
+#define NSS_DBG_CLK "nss-dbg-clk"
+#define NSS_CORE_CLK "nss-core-clk"
+#define NSS_AXI_CLK "nss-axi-clk"
+#define NSS_SNOC_AXI_CLK "nss-snoc-axi-clk"
+#define NSS_NC_AXI_CLK "nss-nc-axi-clk"
+#define NSS_UTCM_CLK "nss-utcm-clk"
+
+/*
+ * Core GCC reset
+ */
+#define NSS_CORE_GCC_RESET 0x00000007
+
+/*
+ * GCC reset
+ */
+void __iomem *nss_misc_reset;
+void __iomem *nss_misc_reset_flag;
+
+/*
+ * Purpose of each interrupt index: This should match the order defined in the NSS firmware
+ */
+enum nss_hal_n2h_intr_purpose {
+	NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS = 0,
+	NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE = 1,
+	NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED = 2,
+	NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0 = 3,
+	NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1 = 4,
+	NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE = 5,
+	NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS = 6,
+	NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA = 7,
+	NSS_HAL_N2H_INTR_PURPOSE_MAX
+};
+
+/*
+ * Interrupt type to cause vector.
+ */
+static uint32_t intr_cause[NSS_MAX_CORES][NSS_H2N_INTR_TYPE_MAX] = {
+				/* core0 */
+				{(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_EMPTY_BUFFER_QUEUE)),
+				(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_DATA_COMMAND_QUEUE)),
+				(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_TX_UNBLOCKED)),
+				(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_TRIGGER_COREDUMP)),
+				(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_EMPTY_PAGED_BUFFER_QUEUE))}
+};
+
+/*
+ * nss_hal_wq_function()
+ *	Added to Handle BH requests to kernel
+ */
+void nss_hal_wq_function(struct work_struct *work)
+{
+	nss_work_t *my_work = (nss_work_t *)work;
+
+	mutex_lock(&nss_top_main.wq_lock);
+
+	nss_freq_change(&nss_top_main.nss[NSS_CORE_0], my_work->frequency, my_work->stats_enable, 0);
+	clk_set_rate(nss_core0_clk, my_work->frequency);
+
+	nss_freq_change(&nss_top_main.nss[NSS_CORE_0], my_work->frequency, my_work->stats_enable, 1);
+
+	mutex_unlock(&nss_top_main.wq_lock);
+	kfree((void *)work);
+}
+
+/*
+ * nss_hal_handle_irq()
+ */
+static irqreturn_t nss_hal_handle_irq(int irq, void *ctx)
+{
+	struct int_ctx_instance *int_ctx = (struct int_ctx_instance *) ctx;
+
+	disable_irq_nosync(irq);
+	napi_schedule(&int_ctx->napi);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * __nss_hal_of_get_pdata()
+ *	Retrieve platform data from device node.
+ */
+static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device *pdev)
+{
+	struct device_node *np = of_node_get(pdev->dev.of_node);
+	struct nss_platform_data *npd;
+	struct nss_ctx_instance *nss_ctx = NULL;
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct resource res_nphys, res_qgic_phys;
+	int32_t i;
+
+	npd = devm_kzalloc(&pdev->dev, sizeof(struct nss_platform_data), GFP_KERNEL);
+	if (!npd) {
+		return NULL;
+	}
+
+	if (of_property_read_u32(np, "qcom,id", &npd->id)
+	    || of_property_read_u32(np, "qcom,load-addr", &npd->load_addr)
+	    || of_property_read_u32(np, "qcom,num-queue", &npd->num_queue)
+	    || of_property_read_u32(np, "qcom,num-irq", &npd->num_irq)) {
+		pr_err("%s: error reading critical device node properties\n", np->name);
+		goto out;
+	}
+
+	/*
+	 * Read frequencies. If failure, load default values.
+	 */
+	of_property_read_u32(np, "qcom,mid-frequency", &nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency);
+	of_property_read_u32(np, "qcom,max-frequency", &nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency);
+
+	if (npd->num_irq > NSS_MAX_IRQ_PER_CORE) {
+		pr_err("%s: exceeds maximum interrupt numbers per core\n", np->name);
+		goto out;
+	}
+
+	nss_ctx = &nss_top->nss[npd->id];
+	nss_ctx->id = npd->id;
+
+	if (of_address_to_resource(np, 0, &res_nphys) != 0) {
+		nss_info_always("%px: nss%d: of_address_to_resource() fail for nphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	if (of_address_to_resource(np, 1, &res_qgic_phys) != 0) {
+		nss_info_always("%px: nss%d: of_address_to_resource() fail for qgic_phys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	/*
+	 * Save physical addresses
+	 */
+	npd->nphys = res_nphys.start;
+	npd->qgic_phys = res_qgic_phys.start;
+
+	npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys));
+	if (!npd->nmap) {
+		nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys));
+	if (!npd->qgic_map) {
+		nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	NSS_CORE_DSB();
+
+	/*
+	 * Get IRQ numbers
+	 */
+	for (i = 0 ; i < npd->num_irq; i++) {
+		npd->irq[i] = irq_of_parse_and_map(np, i);
+		if (!npd->irq[i]) {
+			nss_info_always("%px: nss%d: irq_of_parse_and_map() fail for irq %d\n", nss_ctx, nss_ctx->id, i);
+			goto out;
+		}
+	}
+
+	nss_hal_dt_parse_features(np, npd);
+
+	of_node_put(np);
+	return npd;
+
+out:
+	if (npd->nmap) {
+		iounmap(npd->nmap);
+	}
+
+	if (npd->vmap) {
+		iounmap(npd->vmap);
+	}
+
+	devm_kfree(&pdev->dev, npd);
+	of_node_put(np);
+	return NULL;
+}
+
+/*
+ * nss_hal_clock_set_and_enable()
+ */
+static int nss_hal_clock_set_and_enable(struct device *dev, const char *id, unsigned long rate)
+{
+	struct clk *nss_clk = NULL;
+	int err;
+
+	nss_clk = devm_clk_get(dev, id);
+	if (IS_ERR(nss_clk)) {
+		pr_err("%px: cannot get clock: %s\n", dev, id);
+		return -EFAULT;
+	}
+
+	if (rate) {
+		err = clk_set_rate(nss_clk, rate);
+		if (err) {
+			pr_err("%px: cannot set %s freq\n", dev, id);
+			return -EFAULT;
+		}
+	}
+
+	err = clk_prepare_enable(nss_clk);
+	if (err) {
+		pr_err("%px: cannot enable clock: %s\n", dev, id);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/*
+ * __nss_hal_core_reset()
+ */
+static int __nss_hal_core_reset(struct platform_device *nss_dev, void __iomem *map, uint32_t addr, uint32_t clk_src)
+{
+	uint32_t value;
+
+	/*
+	 * Apply ubi32 core reset
+	 */
+	nss_write_32(map, NSS_REGS_RESET_CTRL_OFFSET, 0x1);
+
+	/*
+	 * De-assert reset
+	 */
+	value = nss_read_32(nss_misc_reset, 0x0);
+	value &= ~NSS_CORE_GCC_RESET;
+	nss_write_32(nss_misc_reset, 0x0, value);
+
+	/*
+	 * Program address configuration
+	 */
+	nss_write_32(map, NSS_REGS_CORE_AMC_OFFSET, 0x1);
+	nss_write_32(map, NSS_REGS_CORE_BAR_OFFSET, 0x3C000000);
+	nss_write_32(map, NSS_REGS_CORE_BOOT_ADDR_OFFSET, addr);
+
+	/*
+	 * Set crypto interrupt as level sensitive
+	 */
+	nss_write_32(map, NSS_REGS_CORE_INT_STAT2_TYPE_OFFSET, 0x80000000);
+	nss_write_32(map, NSS_REGS_CORE_INT_STAT3_TYPE_OFFSET, 0x00200000);
+
+	/*
+	 * Enable Instruction Fetch range checking between 0x4000 0000 to 0xBFFF FFFF.
+	 */
+	nss_write_32(map, NSS_REGS_CORE_IFETCH_RANGE_OFFSET, 0xBF004001);
+
+	/*
+	 * De-assert ubi32 core reset
+	 */
+	nss_write_32(map, NSS_REGS_RESET_CTRL_OFFSET, 0x0);
+
+	/*
+	 * Set values only once for core0. Grab the proper clock.
+	 */
+	nss_core0_clk = clk_get(&nss_dev->dev, NSS_CORE_CLK);
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency)) {
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/*
+ * __nss_hal_debug_enable()
+ *	Enable NSS debug
+ */
+static void __nss_hal_debug_enable(void)
+{
+
+}
+
+/*
+ * __nss_hal_common_reset
+ *	Do reset/clock configuration common to all cores
+ */
+static int __nss_hal_common_reset(struct platform_device *nss_dev)
+{
+	struct device_node *cmn = NULL;
+	struct resource res_nss_misc_reset;
+
+	/*
+	 * Get reference to NSS common device node
+	 */
+	cmn = of_find_node_by_name(NULL, "nss-common");
+	if (!cmn) {
+		pr_err("%px: Unable to find nss-common node\n", nss_dev);
+		return -EFAULT;
+	}
+
+	if (of_address_to_resource(cmn, 0, &res_nss_misc_reset) != 0) {
+		pr_err("%px: of_address_to_resource() return error for nss_misc_reset\n", nss_dev);
+		of_node_put(cmn);
+		return -EFAULT;
+	}
+
+	of_node_put(cmn);
+
+	nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset));
+	if (!nss_misc_reset) {
+		pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev);
+		return -EFAULT;
+	}
+
+	nss_top_main.nss_hal_common_init_done = true;
+	nss_info("nss_hal_common_reset Done\n");
+
+	return 0;
+}
+
+/*
+ * __nss_hal_clock_configure()
+ */
+static int __nss_hal_clock_configure(struct nss_ctx_instance *nss_ctx, struct platform_device *nss_dev, struct nss_platform_data *npd)
+{
+	int32_t i;
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_DBG_CLK, 150000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CFG_CLK, 100000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_AXI_CLK, 400000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_SNOC_AXI_CLK, 400000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NC_AXI_CLK, 266670000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_UTCM_CLK, 266670000)) {
+		return -EFAULT;
+	}
+
+	/*
+	 * No entries, then just load default
+	 */
+	if ((nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency == 0) ||
+		(nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency == 0)) {
+		nss_runtime_samples.freq_scale[NSS_FREQ_LOW_SCALE].frequency = NSS_FREQ_SCALE_NA;
+		nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency = NSS_FREQ_850;
+		nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency = NSS_FREQ_1000;
+		nss_info_always("%px: Running default frequencies\n", nss_ctx);
+	}
+
+	/*
+	 * Maple low frequency not applicable, set it accordingly
+	 */
+	nss_runtime_samples.freq_scale[NSS_FREQ_LOW_SCALE].frequency = NSS_FREQ_SCALE_NA;
+
+	/*
+	 * Test frequency from dtsi, if fail, try to set default frequency.
+	 */
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency)) {
+		if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, NSS_FREQ_1000)) {
+			return -EFAULT;
+		}
+	}
+
+	/*
+	 * Setup ranges, test frequency, and display.
+	 */
+	for (i = 0; i < NSS_FREQ_MAX_SCALE; i++) {
+		switch (nss_runtime_samples.freq_scale[i].frequency) {
+		case NSS_FREQ_850:
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_850_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_850_MAX;
+			break;
+
+		case NSS_FREQ_1000:
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_1000_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_1000_MAX;
+			break;
+
+		case NSS_FREQ_SCALE_NA:
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_NA;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_NA;
+			continue;
+
+		default:
+			nss_info_always("%px: Frequency not found %d\n", nss_ctx, nss_runtime_samples.freq_scale[i].frequency);
+			return -EFAULT;
+		}
+
+		/*
+		 * Test the frequency, if fail, then default to safe frequency and abort
+		 */
+		if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, nss_runtime_samples.freq_scale[i].frequency)) {
+			return -EFAULT;
+		}
+	}
+
+	nss_info_always("Supported Frequencies - ");
+	for (i = 0; i < NSS_FREQ_MAX_SCALE; i++) {
+		switch (nss_runtime_samples.freq_scale[i].frequency) {
+		case NSS_FREQ_850:
+			nss_info_always("850 MHz ");
+			break;
+
+		case NSS_FREQ_1000:
+			nss_info_always("1 GHz ");
+			break;
+
+		case NSS_FREQ_SCALE_NA:
+			continue;
+
+		default:
+			nss_info_always("%px: Error\nNo Table/Invalid Frequency Found\n", nss_ctx);
+			return -EFAULT;
+		}
+	}
+	nss_info_always("\n");
+
+	/*
+	 * Set values only once for core0. Grab the proper clock.
+	 */
+	nss_core0_clk = clk_get(&nss_dev->dev, NSS_CORE_CLK);
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency)) {
+		return -EFAULT;
+	}
+	return 0;
+}
+
+/*
+ * __nss_hal_read_interrupt_cause()
+ */
+static void __nss_hal_read_interrupt_cause(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t *cause)
+{
+}
+
+/*
+ * __nss_hal_clear_interrupt_cause()
+ */
+static void __nss_hal_clear_interrupt_cause(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+}
+
+/*
+ * __nss_hal_disable_interrupt()
+ */
+static void __nss_hal_disable_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+}
+
+/*
+ * __nss_hal_enable_interrupt()
+ */
+static void __nss_hal_enable_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+}
+
+/*
+ * __nss_hal_send_interrupt()
+ */
+static void __nss_hal_send_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t type)
+{
+	/*
+	 * Check if core and type is Valid
+	 */
+	nss_assert(nss_ctx->id < nss_top_main.num_nss);
+	nss_assert(type < NSS_H2N_INTR_TYPE_MAX);
+
+	nss_write_32(nss_ctx->qgic_map, NSS_QGIC_IPC_REG_OFFSET, intr_cause[nss_ctx->id][type]);
+}
+
+/*
+ * __nss_hal_request_irq()
+ */
+static int __nss_hal_request_irq(struct nss_ctx_instance *nss_ctx, struct nss_platform_data *npd, int irq_num)
+{
+	struct int_ctx_instance *int_ctx = &nss_ctx->int_ctx[irq_num];
+	uint32_t cause, napi_wgt;
+	int err = -1, irq = npd->irq[irq_num];
+	int (*napi_poll_cb)(struct napi_struct *, int) = NULL;
+	const char *irq_name;
+
+	irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
+
+	switch (irq_num) {
+	case NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS:
+		napi_poll_cb = nss_core_handle_napi_non_queue;
+		napi_wgt = NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT;
+		cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS;
+		irq_name = NSS_IRQ_NAME_EMPTY_BUF_SOS;
+		break;
+
+	case NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE:
+		napi_poll_cb = nss_core_handle_napi_queue;
+		napi_wgt = NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT;
+		cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE;
+		irq_name = NSS_IRQ_NAME_EMPTY_BUF_QUEUE;
+		break;
+
+	case NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED:
+		napi_poll_cb = nss_core_handle_napi_non_queue;
+		napi_wgt = NSS_TX_UNBLOCKED_PROCESSING_WEIGHT;
+		cause = NSS_N2H_INTR_TX_UNBLOCKED;
+		irq_name = NSS_IRQ_NAME_TX_UNBLOCK;
+		break;
+
+	case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0:
+		napi_poll_cb = nss_core_handle_napi_queue;
+		napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT;
+		cause = NSS_N2H_INTR_DATA_QUEUE_0;
+		irq_name = NSS_IRQ_NAME_QUEUE0;
+		break;
+
+	case NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1:
+		napi_poll_cb = nss_core_handle_napi_queue;
+		napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT;
+		cause = NSS_N2H_INTR_DATA_QUEUE_1;
+		irq_name = NSS_IRQ_NAME_QUEUE1;
+		break;
+
+	case NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE:
+		napi_poll_cb = nss_core_handle_napi_emergency;
+		napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT;
+		cause = NSS_N2H_INTR_COREDUMP_COMPLETE;
+		irq_name = NSS_IRQ_NAME_COREDUMP_COMPLETE;
+		break;
+
+	case NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS:
+		napi_poll_cb = nss_core_handle_napi_non_queue;
+		napi_wgt = NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT;
+		cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS;
+		irq_name = NSS_IRQ_NAME_PAGED_EMPTY_BUF_SOS;
+		break;
+
+	case NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA:
+		napi_poll_cb = nss_core_handle_napi_sdma;
+		napi_wgt = NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT;
+		cause = NSS_N2H_INTR_PROFILE_DMA;
+		irq_name = NSS_IRQ_NAME_PROFILE_DMA;
+		break;
+
+	default:
+		nss_warning("%px: nss%d: unsupported irq# %d\n", nss_ctx, nss_ctx->id, irq_num);
+		return err;
+	}
+
+	netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, napi_poll_cb, napi_wgt);
+	int_ctx->cause = cause;
+	err = request_irq(irq, nss_hal_handle_irq, 0, irq_name, int_ctx);
+	if (err) {
+		nss_warning("%px: nss%d: request_irq failed for irq# %d\n", nss_ctx, nss_ctx->id, irq_num);
+		return err;
+	}
+	int_ctx->irq = irq;
+	return 0;
+}
+
+/*
+ * __nss_hal_init_imem
+ */
+void __nss_hal_init_imem(struct nss_ctx_instance *nss_ctx)
+{
+	/*
+	 * Nothing to be done as there are no TCM in ipq50xx
+	 */
+}
+
+/*
+ * __nss_hal_init_utcm_shared
+ */
+bool __nss_hal_init_utcm_shared(struct nss_ctx_instance *nss_ctx, uint32_t *meminfo_start)
+{
+	struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
+	uint32_t utcm_shared_map_magic = meminfo_start[2];
+	uint32_t utcm_shared_start = meminfo_start[3];
+	uint32_t utcm_shared_size = meminfo_start[4];
+
+	/*
+	 * Check meminfo utcm_shared map magic
+	 */
+	if ((uint16_t)utcm_shared_map_magic != NSS_MEMINFO_RESERVE_AREA_UTCM_SHARED_MAP_MAGIC) {
+		nss_info_always("%px: failed to verify UTCM_SHARED map magic\n", nss_ctx);
+		return false;
+	}
+
+	mem_ctx->utcm_shared_head = utcm_shared_start;
+	mem_ctx->utcm_shared_end = mem_ctx->utcm_shared_head + utcm_shared_size;
+	mem_ctx->utcm_shared_tail = mem_ctx->utcm_shared_head;
+
+	nss_info("%px: UTCM_SHARED init: head: 0x%x end: 0x%x tail: 0x%x\n", nss_ctx,
+			mem_ctx->utcm_shared_head, mem_ctx->utcm_shared_end, mem_ctx->utcm_shared_tail);
+	return true;
+}
+
+/*
+ * nss_hal_ipq50xx_ops
+ */
+struct nss_hal_ops nss_hal_ipq50xx_ops = {
+	.common_reset = __nss_hal_common_reset,
+	.core_reset = __nss_hal_core_reset,
+	.clock_configure = __nss_hal_clock_configure,
+	.firmware_load = nss_hal_firmware_load,
+	.debug_enable = __nss_hal_debug_enable,
+	.of_get_pdata = __nss_hal_of_get_pdata,
+	.request_irq = __nss_hal_request_irq,
+	.send_interrupt = __nss_hal_send_interrupt,
+	.enable_interrupt = __nss_hal_enable_interrupt,
+	.disable_interrupt = __nss_hal_disable_interrupt,
+	.clear_interrupt_cause = __nss_hal_clear_interrupt_cause,
+	.read_interrupt_cause = __nss_hal_read_interrupt_cause,
+	.init_imem = __nss_hal_init_imem,
+	.init_utcm_shared = __nss_hal_init_utcm_shared,
+};
diff --git a/qca-nss-drv/nss_hal/ipq60xx/nss_hal_pvt.c b/qca-nss-drv/nss_hal/ipq60xx/nss_hal_pvt.c
new file mode 100644
index 0000000..4c84cb9
--- /dev/null
+++ b/qca-nss-drv/nss_hal/ipq60xx/nss_hal_pvt.c
@@ -0,0 +1,739 @@
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/**
+ * nss_hal_pvt.c
+ *	NSS HAL private APIs.
+ */
+
+#include <linux/err.h>
+#include <linux/version.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include "nss_hal.h"
+#include "nss_core.h"
+
+#define NSS_QGIC_IPC_REG_OFFSET 0x8
+
+#define NSS0_H2N_INTR_BASE 13
+
+/*
+ * Common CLKs
+ */
+#define NSS_NOC_CLK "nss-noc-clk"
+#define NSS_PTP_REF_CLK "nss-ptp-ref-clk"
+#define NSS_CSR_CLK "nss-csr-clk"
+#define NSS_CFG_CLK "nss-cfg-clk"
+#define NSS_NSSNOC_QOSGEN_REF_CLK "nss-nssnoc-qosgen-ref-clk"
+#define NSS_NSSNOC_SNOC_CLK "nss-nssnoc-snoc-clk"
+#define NSS_NSSNOC_TIMEOUT_REF_CLK "nss-nssnoc-timeout-ref-clk"
+#define NSS_CE_AXI_CLK "nss-ce-axi-clk"
+#define NSS_CE_APB_CLK "nss-ce-apb-clk"
+#define NSS_NSSNOC_CE_AXI_CLK "nss-nssnoc-ce-axi-clk"
+#define NSS_NSSNOC_CE_APB_CLK "nss-nssnoc-ce-apb-clk"
+#define NSS_MEM_NOC_UBI32_CLK "nss-mem-noc-ubi32-clk"
+#define NSS_SNOC_NSSNOC_CLK "nss-snoc-nssnoc-clk"
+
+/*
+ * Per-core CLKS
+ */
+#define NSS_NSSNOC_AHB_CLK "nss-nssnoc-ahb-clk"
+#define NSS_CORE_CLK "nss-core-clk"
+#define NSS_AHB_CLK "nss-ahb-clk"
+#define NSS_AXI_CLK "nss-axi-clk"
+#define NSS_NC_AXI_CLK "nss-nc-axi-clk"
+#define NSS_UTCM_CLK "nss-utcm-clk"
+
+/*
+ * Voltage values
+ */
+#define NOMINAL_VOLTAGE 1
+#define TURBO_VOLTAGE 2
+
+/*
+ * Core reset part 1
+ */
+#define NSS_CORE_GCC_RESET_1 0x00000020
+
+/*
+ * Core reset part 2
+ */
+#define NSS_CORE_GCC_RESET_2 0x00000017
+
+/*
+ * Voltage regulator
+ */
+struct regulator *npu_reg;
+
+/*
+ * GCC reset
+ */
+void __iomem *nss_misc_reset;
+void __iomem *nss_misc_reset_flag;
+
+/*
+ * Purpose of each interrupt index: This should match the order defined in the NSS firmware
+ */
+enum nss_hal_n2h_intr_purpose {
+	NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS = 0,
+	NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE = 1,
+	NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED = 2,
+	NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0 = 3,
+	NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1 = 4,
+	NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2 = 5,
+	NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3 = 6,
+	NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE = 7,
+	NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS = 8,
+	NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA = 9,
+	NSS_HAL_N2H_INTR_PURPOSE_MAX
+};
+
+/*
+ * Interrupt type to cause vector.
+ */
+static uint32_t intr_cause[NSS_MAX_CORES][NSS_H2N_INTR_TYPE_MAX] = {
+				/* core0 */
+				{(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_EMPTY_BUFFER_QUEUE)),
+				(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_DATA_COMMAND_QUEUE)),
+				(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_TX_UNBLOCKED)),
+				(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_TRIGGER_COREDUMP)),
+				(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_EMPTY_PAGED_BUFFER_QUEUE))}
+};
+
+/*
+ * nss_hal_wq_function()
+ *	Added to Handle BH requests to kernel
+ */
+void nss_hal_wq_function(struct work_struct *work)
+{
+	nss_work_t *my_work = (nss_work_t *)work;
+
+	mutex_lock(&nss_top_main.wq_lock);
+
+	nss_freq_change(&nss_top_main.nss[NSS_CORE_0], my_work->frequency, my_work->stats_enable, 0);
+	clk_set_rate(nss_core0_clk, my_work->frequency);
+
+	nss_freq_change(&nss_top_main.nss[NSS_CORE_0], my_work->frequency, my_work->stats_enable, 1);
+
+	mutex_unlock(&nss_top_main.wq_lock);
+	kfree((void *)work);
+}
+
+/*
+ * nss_hal_handle_irq()
+ */
+static irqreturn_t nss_hal_handle_irq(int irq, void *ctx)
+{
+	struct int_ctx_instance *int_ctx = (struct int_ctx_instance *) ctx;
+
+	disable_irq_nosync(irq);
+	napi_schedule(&int_ctx->napi);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * __nss_hal_of_get_pdata()
+ *	Retrieve platform data from device node.
+ */
+static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device *pdev)
+{
+	struct device_node *np = of_node_get(pdev->dev.of_node);
+	struct nss_platform_data *npd;
+	struct nss_ctx_instance *nss_ctx = NULL;
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct resource res_nphys, res_qgic_phys;
+	int32_t i;
+
+	npd = devm_kzalloc(&pdev->dev, sizeof(struct nss_platform_data), GFP_KERNEL);
+	if (!npd) {
+		return NULL;
+	}
+
+	if (of_property_read_u32(np, "qcom,id", &npd->id)
+	    || of_property_read_u32(np, "qcom,load-addr", &npd->load_addr)
+	    || of_property_read_u32(np, "qcom,num-queue", &npd->num_queue)
+	    || of_property_read_u32(np, "qcom,num-irq", &npd->num_irq)) {
+		pr_err("%s: error reading critical device node properties\n", np->name);
+		goto out;
+	}
+
+	/*
+	 * Read frequencies. If failure, load default values.
+	 */
+	of_property_read_u32(np, "qcom,low-frequency", &nss_runtime_samples.freq_scale[NSS_FREQ_LOW_SCALE].frequency);
+	of_property_read_u32(np, "qcom,mid-frequency", &nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency);
+	of_property_read_u32(np, "qcom,max-frequency", &nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency);
+
+	if (npd->num_irq > NSS_MAX_IRQ_PER_CORE) {
+		pr_err("%s: exceeds maximum interrupt numbers per core\n", np->name);
+		goto out;
+	}
+
+	nss_ctx = &nss_top->nss[npd->id];
+	nss_ctx->id = npd->id;
+
+	if (of_address_to_resource(np, 0, &res_nphys) != 0) {
+		nss_info_always("%px: nss%d: of_address_to_resource() fail for nphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	if (of_address_to_resource(np, 1, &res_qgic_phys) != 0) {
+		nss_info_always("%px: nss%d: of_address_to_resource() fail for qgic_phys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	/*
+	 * Save physical addresses
+	 */
+	npd->nphys = res_nphys.start;
+	npd->qgic_phys = res_qgic_phys.start;
+
+	npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys));
+	if (!npd->nmap) {
+		nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys));
+	if (!npd->qgic_map) {
+		nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	NSS_CORE_DSB();
+
+	/*
+	 * Get IRQ numbers
+	 */
+	for (i = 0 ; i < npd->num_irq; i++) {
+		npd->irq[i] = irq_of_parse_and_map(np, i);
+		if (!npd->irq[i]) {
+			nss_info_always("%px: nss%d: irq_of_parse_and_map() fail for irq %d\n", nss_ctx, nss_ctx->id, i);
+			goto out;
+		}
+	}
+
+	nss_hal_dt_parse_features(np, npd);
+
+	of_node_put(np);
+	return npd;
+
+out:
+	if (npd->nmap) {
+		iounmap(npd->nmap);
+	}
+
+	if (npd->vmap) {
+		iounmap(npd->vmap);
+	}
+
+	devm_kfree(&pdev->dev, npd);
+	of_node_put(np);
+	return NULL;
+}
+
+/*
+ * nss_hal_clock_set_and_enable()
+ */
+static int nss_hal_clock_set_and_enable(struct device *dev, const char *id, unsigned long rate)
+{
+	struct clk *nss_clk = NULL;
+	int err;
+
+	nss_clk = devm_clk_get(dev, id);
+	if (IS_ERR(nss_clk)) {
+		pr_err("%px: cannot get clock: %s\n", dev, id);
+		return -EFAULT;
+	}
+
+	if (rate) {
+		err = clk_set_rate(nss_clk, rate);
+		if (err) {
+			pr_err("%px: cannot set %s freq\n", dev, id);
+			return -EFAULT;
+		}
+	}
+
+	err = clk_prepare_enable(nss_clk);
+	if (err) {
+		pr_err("%px: cannot enable clock: %s\n", dev, id);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/*
+ * __nss_hal_core_reset()
+ */
+static int __nss_hal_core_reset(struct platform_device *nss_dev, void __iomem *map, uint32_t addr, uint32_t clk_src)
+{
+	uint32_t value;
+
+	/*
+	 * Apply ubi32 core reset
+	 */
+	nss_write_32(map, NSS_REGS_RESET_CTRL_OFFSET, 0x1);
+
+	/*
+	 * De-assert reset for first set
+	 */
+	value = nss_read_32(nss_misc_reset, 0x0);
+	value &= ~NSS_CORE_GCC_RESET_1;
+	nss_write_32(nss_misc_reset, 0x0, value);
+
+	/*
+	 * Minimum 10 - 20 cycles delay is required after
+	 * de-asserting NSS reset clamp
+	 */
+	usleep_range(10, 20);
+
+	/*
+	 * De-assert reset for second set
+	 */
+	value &= ~NSS_CORE_GCC_RESET_2;
+	nss_write_32(nss_misc_reset, 0x0, value);
+
+	/*
+	 * Program address configuration
+	 */
+	nss_write_32(map, NSS_REGS_CORE_AMC_OFFSET, 0x1);
+	nss_write_32(map, NSS_REGS_CORE_BAR_OFFSET, 0x3C000000);
+	nss_write_32(map, NSS_REGS_CORE_BOOT_ADDR_OFFSET, addr);
+
+	/*
+	 * Enable Instruction Fetch range checking between 0x4000 0000 to 0xBFFF FFFF.
+	 */
+	nss_write_32(map, NSS_REGS_CORE_IFETCH_RANGE_OFFSET, 0xBF004001);
+
+	/*
+	 * De-assert ubi32 core reset
+	 */
+	nss_write_32(map, NSS_REGS_RESET_CTRL_OFFSET, 0x0);
+
+	/*
+	 * Set values only once for core0. Grab the proper clock.
+	 */
+	nss_core0_clk = clk_get(&nss_dev->dev, NSS_CORE_CLK);
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency)) {
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/*
+ * __nss_hal_debug_enable()
+ *	Enable NSS debug
+ */
+static void __nss_hal_debug_enable(void)
+{
+
+}
+
+/*
+ * __nss_hal_common_reset
+ *	Do reset/clock configuration common to all cores
+ */
+static int __nss_hal_common_reset(struct platform_device *nss_dev)
+{
+
+	struct device_node *cmn = NULL;
+	struct resource res_nss_misc_reset;
+	struct resource res_nss_misc_reset_flag;
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NOC_CLK, 266670000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_PTP_REF_CLK, 150000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CSR_CLK, 200000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CFG_CLK, 100000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_QOSGEN_REF_CLK, 24000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_SNOC_CLK, 266600000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_SNOC_NSSNOC_CLK, 266670000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_TIMEOUT_REF_CLK, 6000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CE_AXI_CLK, 200000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CE_APB_CLK, 200000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_CE_AXI_CLK, 200000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_CE_APB_CLK, 200000000)) {
+		return -EFAULT;
+	}
+
+	/*
+	 * Get reference to NSS common device node
+	 */
+	cmn = of_find_node_by_name(NULL, "nss-common");
+	if (!cmn) {
+		pr_err("%px: Unable to find nss-common node\n", nss_dev);
+		return -EFAULT;
+	}
+
+	if (of_address_to_resource(cmn, 0, &res_nss_misc_reset) != 0) {
+		pr_err("%px: of_address_to_resource() return error for nss_misc_reset\n", nss_dev);
+		of_node_put(cmn);
+		return -EFAULT;
+	}
+
+	if (of_address_to_resource(cmn, 1, &res_nss_misc_reset_flag) != 0) {
+		pr_err("%px: of_address_to_resource() return error for nss_misc_reset_flag\n", nss_dev);
+		of_node_put(cmn);
+		return -EFAULT;
+	}
+
+	of_node_put(cmn);
+
+	nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset));
+	if (!nss_misc_reset) {
+		pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev);
+		return -EFAULT;
+	}
+
+	nss_misc_reset_flag = ioremap_nocache(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag));
+	if (!nss_misc_reset_flag) {
+		pr_err("%px: ioremap fail for nss_misc_reset_flag\n", nss_dev);
+		return -EFAULT;
+	}
+
+	nss_top_main.nss_hal_common_init_done = true;
+	nss_info("nss_hal_common_reset Done\n");
+
+	return 0;
+}
+
+/*
+ * __nss_hal_clock_configure()
+ */
+static int __nss_hal_clock_configure(struct nss_ctx_instance *nss_ctx, struct platform_device *nss_dev, struct nss_platform_data *npd)
+{
+	uint32_t i;
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_AHB_CLK, 200000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_AHB_CLK, 200000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_AXI_CLK, 533330000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NC_AXI_CLK, 266670000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_UTCM_CLK, 266670000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_MEM_NOC_UBI32_CLK, 533330000)) {
+		return -EFAULT;
+	}
+
+	/*
+	 * No entries, then just load default
+	 */
+	if ((nss_runtime_samples.freq_scale[NSS_FREQ_LOW_SCALE].frequency == 0) ||
+		(nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency == 0) ||
+		(nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency == 0)) {
+		nss_runtime_samples.freq_scale[NSS_FREQ_LOW_SCALE].frequency = NSS_FREQ_187;
+		nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency = NSS_FREQ_748;
+		nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency = NSS_FREQ_1497;
+		nss_info_always("Running default frequencies\n");
+	}
+
+	/*
+	 * Test frequency from dtsi, if fail, try to set default frequency.
+	 */
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency)) {
+		if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, NSS_FREQ_1497)) {
+			return -EFAULT;
+		}
+	}
+
+	/*
+	 * Setup ranges, test frequency, and display.
+	 */
+	for (i = 0; i < NSS_FREQ_MAX_SCALE; i++) {
+		if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_187) {
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_187_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_187_MAX;
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_748) {
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_748_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_748_MAX;
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1497) {
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_1497_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_1497_MAX;
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1689) {
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_1689_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_1689_MAX;
+		} else {
+			nss_info_always("Frequency not found %d\n", nss_runtime_samples.freq_scale[i].frequency);
+			return -EFAULT;
+		}
+
+		/*
+		 * Test the frequency, if fail, then default to safe frequency and abort
+		 */
+		if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, nss_runtime_samples.freq_scale[i].frequency)) {
+			return -EFAULT;
+		}
+	}
+
+	nss_info_always("Supported Frequencies - ");
+	for (i = 0; i < NSS_FREQ_MAX_SCALE; i++) {
+		if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_187) {
+			nss_info_always("187.2 MHz ");
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_748) {
+			nss_info_always("748.8 MHz ");
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1497) {
+			nss_info_always("1.4976 GHz ");
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1689) {
+			nss_info_always("1.6896 GHz ");
+		} else {
+			nss_info_always("Error\nNo Table/Invalid Frequency Found\n");
+			return -EFAULT;
+		}
+	}
+	nss_info_always("\n");
+
+	/*
+	 * Set values only once for core0. Grab the proper clock.
+	 */
+	nss_core0_clk = clk_get(&nss_dev->dev, NSS_CORE_CLK);
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency)) {
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/*
+ * __nss_hal_read_interrupt_cause()
+ */
+static void __nss_hal_read_interrupt_cause(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t *cause)
+{
+}
+
+/*
+ * __nss_hal_clear_interrupt_cause()
+ */
+static void __nss_hal_clear_interrupt_cause(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+}
+
+/*
+ * __nss_hal_disable_interrupt()
+ */
+static void __nss_hal_disable_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+}
+
+/*
+ * __nss_hal_enable_interrupt()
+ */
+static void __nss_hal_enable_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+}
+
+/*
+ * __nss_hal_send_interrupt()
+ */
+static void __nss_hal_send_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t type)
+{
+	/*
+	 * Check if core and type is Valid
+	 */
+	nss_assert(nss_ctx->id < nss_top_main.num_nss);
+	nss_assert(type < NSS_H2N_INTR_TYPE_MAX);
+
+	nss_write_32(nss_ctx->qgic_map, NSS_QGIC_IPC_REG_OFFSET, intr_cause[nss_ctx->id][type]);
+}
+
+/*
+ * __nss_hal_request_irq()
+ */
+static int __nss_hal_request_irq(struct nss_ctx_instance *nss_ctx, struct nss_platform_data *npd, int irq_num)
+{
+	struct int_ctx_instance *int_ctx = &nss_ctx->int_ctx[irq_num];
+	int err = -1, irq = npd->irq[irq_num];
+
+	irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS) {
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT);
+		int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS;
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_sos", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE) {
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT);
+		int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE;
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_queue", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED) {
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_TX_UNBLOCKED_PROCESSING_WEIGHT);
+		int_ctx->cause = NSS_N2H_INTR_TX_UNBLOCKED;
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss-tx-unblock", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0) {
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+		int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_0;
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue0", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1) {
+		int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_1;
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue1", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2) {
+		int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_2;
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue2", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3) {
+		int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_3;
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue3", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE) {
+		int_ctx->cause = NSS_N2H_INTR_COREDUMP_COMPLETE;
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_emergency, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_coredump_complete", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS) {
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT);
+		int_ctx->cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS;
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_paged_empty_buf_sos", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA) {
+		int_ctx->cause = NSS_N2H_INTR_PROFILE_DMA;
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_sdma, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_profile_dma", int_ctx);
+	}
+
+	if (err) {
+		return err;
+	}
+
+	int_ctx->irq = irq;
+	return 0;
+}
+
+/*
+ * __nss_hal_init_imem
+ */
+void __nss_hal_init_imem(struct nss_ctx_instance *nss_ctx)
+{
+	/*
+	 * Nothing to be done as there are no TCM in ipq60xx
+	 */
+}
+
+/*
+ * __nss_hal_init_utcm_shared
+ */
+bool __nss_hal_init_utcm_shared(struct nss_ctx_instance *nss_ctx, uint32_t *meminfo_start)
+{
+	struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
+	uint32_t utcm_shared_map_magic = meminfo_start[2];
+	uint32_t utcm_shared_start = meminfo_start[3];
+	uint32_t utcm_shared_size = meminfo_start[4];
+
+	/*
+	 * Check meminfo utcm_shared map magic
+	 */
+	if ((uint16_t)utcm_shared_map_magic != NSS_MEMINFO_RESERVE_AREA_UTCM_SHARED_MAP_MAGIC) {
+		nss_info_always("%px: failed to verify UTCM_SHARED map magic\n", nss_ctx);
+		return false;
+	}
+
+	mem_ctx->utcm_shared_head = utcm_shared_start;
+	mem_ctx->utcm_shared_end = mem_ctx->utcm_shared_head + utcm_shared_size;
+	mem_ctx->utcm_shared_tail = mem_ctx->utcm_shared_head;
+
+	nss_info("%px: UTCM_SHARED init: head: 0x%x end: 0x%x tail: 0x%x\n", nss_ctx,
+			mem_ctx->utcm_shared_head, mem_ctx->utcm_shared_end, mem_ctx->utcm_shared_tail);
+	return true;
+}
+
+/*
+ * nss_hal_ipq60xx_ops
+ */
+struct nss_hal_ops nss_hal_ipq60xx_ops = {
+	.common_reset = __nss_hal_common_reset,
+	.core_reset = __nss_hal_core_reset,
+	.clock_configure = __nss_hal_clock_configure,
+	.firmware_load = nss_hal_firmware_load,
+	.debug_enable = __nss_hal_debug_enable,
+	.of_get_pdata = __nss_hal_of_get_pdata,
+	.request_irq = __nss_hal_request_irq,
+	.send_interrupt = __nss_hal_send_interrupt,
+	.enable_interrupt = __nss_hal_enable_interrupt,
+	.disable_interrupt = __nss_hal_disable_interrupt,
+	.clear_interrupt_cause = __nss_hal_clear_interrupt_cause,
+	.read_interrupt_cause = __nss_hal_read_interrupt_cause,
+	.init_imem = __nss_hal_init_imem,
+	.init_utcm_shared = __nss_hal_init_utcm_shared,
+};
diff --git a/qca-nss-drv/nss_hal/ipq806x/nss_clocks.h b/qca-nss-drv/nss_hal/ipq806x/nss_clocks.h
new file mode 100644
index 0000000..1e7af1a
--- /dev/null
+++ b/qca-nss-drv/nss_hal/ipq806x/nss_clocks.h
@@ -0,0 +1,131 @@
+/* * Copyright (c) 2013 The Linux Foundation. All rights reserved.* */
+/*
+ * Copyright (c) 2013 The Linux Foundation.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_CLOCKS_H
+#define __NSS_CLOCKS_H
+
+#if (NSS_DT_SUPPORT != 1)
+#include <asm/io.h>
+#include <mach/msm_iomap.h>
+
+#define REG(off)	(MSM_CLK_CTL_BASE + (off))
+#define REG_GCC(off)	(MSM_APCS_GCC_BASE + (off))
+
+/* Peripheral clock registers. */
+#define PLL18_ACR				REG(0x1234)
+#define PLL18_MODE				REG(0x31A0)
+#define PLL18_L_VAL				REG(0x31A4)
+#define PLL18_M_VAL				REG(0x31A8)
+#define PLL18_N_VAL				REG(0x31AC)
+#define PLL18_TEST_CTL				REG(0x31B0)
+#define PLL18_CONFIG				REG(0x31B4)
+#define PLL18_STATUS				REG(0x31B8)
+#define PLL_LOCK_DET_STATUS			REG(0x3420)
+#define PLL_LOCK_DET_MASK			REG(0x3424)
+#define CE5_CORE_CLK_SRC_CTL 			REG(0x36C0)
+#define CE5_CORE_CLK_SRC0_NS 			REG(0x36C4)
+#define NSS_ACC_REG				REG(0x28EC)
+#define NSS_RESET_SPARE				REG(0x3B60)
+#define NSSFB0_CLK_SRC_CTL			REG(0x3B80)
+#define NSSFB0_CLK_SRC0_NS			REG(0x3B84)
+#define NSSFB0_CLK_SRC1_NS			REG(0x3B88)
+#define NSSFB0_CLK_CTL				REG(0x3BA0)
+#define NSSFAB_GLOBAL_BUS_NS			REG(0x3BC0)
+#define NSSFB1_CLK_SRC_CTL			REG(0x3BE0)
+#define NSSFB1_CLK_SRC0_NS			REG(0x3BE4)
+#define NSSFB1_CLK_SRC1_NS			REG(0x3BE8)
+#define NSSFB1_CLK_CTL				REG(0x3C00)
+#define CLK_HALT_NSSFAB0_NSSFAB1_STATEA		REG(0x3C20)
+#define UBI32_MPT0_CLK_CTL			REG(0x3C40)
+#define UBI32_MPT1_CLK_CTL			REG(0x3C44)
+#define CE5_HCLK_SRC_CTL			REG(0x3C60)
+#define CE5_HCLK_SRC0_NS			REG(0x3C64)
+#define CE5_HCLK_SRC1_NS			REG(0x3C68)
+#define CE5_HCLK_CTL				REG(0x3C6C)
+#define NSSFPB_CLK_CTL				REG(0x3C80)
+#define NSSFPB_CLK_SRC_CTL			REG(0x3C84)
+#define NSSFPB_CLK_SRC0_NS			REG(0x3C88)
+#define NSSFPB_CLK_SRC1_NS			REG(0x3C8C)
+#define GMAC_COREn_CLK_SRC_CTL(n)		REG(0x3CA0+32*(n))
+#define GMAC_CORE1_CLK_SRC_CTL			REG(0x3CA0)
+#define GMAC_COREn_CLK_SRC0_MD(n)		REG(0x3CA4+32*(n))
+#define GMAC_CORE1_CLK_SRC0_MD			REG(0x3CA4)
+#define GMAC_COREn_CLK_SRC1_MD(n)		REG(0x3CA8+32*(n))
+#define GMAC_CORE1_CLK_SRC1_MD			REG(0x3CA8)
+#define GMAC_COREn_CLK_SRC0_NS(n)		REG(0x3CAC+32*(n))
+#define GMAC_CORE1_CLK_SRC0_NS			REG(0x3CAC)
+#define GMAC_COREn_CLK_SRC1_NS(n)		REG(0x3CB0+32*(n))
+#define GMAC_CORE1_CLK_SRC1_NS			REG(0x3CB0)
+#define GMAC_COREn_CLK_CTL(n)			REG(0x3CB4+32*(n))
+#define GMAC_CORE1_CLK_CTL			REG(0x3CB4)
+#define GMAC_COREn_CLK_FS(n)			REG(0x3CB8+32*(n))
+#define GMAC_CORE1_CLK_FS			REG(0x3CB8)
+#define GMAC_COREn_RESET(n)			REG(0x3CBC+32*(n))
+#define GMAC_CORE1_RESET			REG(0x3CBC)
+#define UBI32_COREn_CLK_SRC_CTL(n)		REG(0x3D20+32*(n))
+#define UBI32_CORE1_CLK_SRC_CTL			REG(0x3D20)
+#define UBI32_COREn_CLK_SRC0_MD(n)		REG(0x3D24+32*(n))
+#define UBI32_CORE1_CLK_SRC0_MD			REG(0x3D24)
+#define UBI32_COREn_CLK_SRC1_MD(n)		REG(0x3D28+32*(n))
+#define UBI32_CORE1_CLK_SRC1_MD			REG(0x3D28)
+#define UBI32_COREn_CLK_SRC0_NS(n)		REG(0x3D2C+32*(n))
+#define UBI32_CORE1_CLK_SRC0_NS			REG(0x3D2C)
+#define UBI32_COREn_CLK_SRC1_NS(n)		REG(0x3D30+32*(n))
+#define UBI32_CORE1_CLK_SRC1_NS			REG(0x3D30)
+#define UBI32_COREn_CLK_CTL(n)			REG(0x3D34+32*(n))
+#define UBI32_CORE1_CLK_CTL			REG(0x3D34)
+#define UBI32_COREn_CLK_FS(n)			REG(0x3D38+32*(n))
+#define UBI32_CORE1_CLK_FS			REG(0x3D38)
+#define UBI32_COREn_RESET_CLAMP(n)		REG(0x3D3C+32*(n))
+#define UBI32_CORE1_RESET_CLAMP			REG(0x3D3C)
+#define NSS_250MHZ_CLK_SRC_CTL			REG(0x3D60)
+#define NSS_250MHZ_CLK_SRC0_NS			REG(0x3D64)
+#define NSS_250MHZ_CLK_SRC1_NS			REG(0x3D68)
+#define NSS_250MHZ_CLK_SRC0_MD			REG(0x3D6C)
+#define NSS_250MHZ_CLK_SRC1_MD			REG(0x3D70)
+#define NSS_250MHZ_CLK_CTL			REG(0x3D74)
+#define CE5_ACLK_SRC_CTL			REG(0x3D80)
+#define CE5_ACLK_SRC0_NS			REG(0x3D84)
+#define CE5_ACLK_SRC1_NS			REG(0x3D88)
+#define CE5_ACLK_CTL				REG(0x3D8C)
+#define PLL_ENA_NSS				REG(0x3DA0)
+#define NSSTCM_CLK_SRC_CTL			REG(0x3DC0)
+#define NSSTCM_CLK_SRC0_NS			REG(0x3DC4)
+#define NSSTCM_CLK_SRC1_NS			REG(0x3DC8)
+#define NSSTCM_CLK_FS				REG(0x3DCC)
+#define NSSTCM_CLK_CTL				REG(0x3DD0)
+#define CE5_CORE_0_RESET			REG(0x3E00)
+#define CE5_CORE_1_RESET			REG(0x3E04)
+#define CE5_CORE_2_RESET			REG(0x3E08)
+#define CE5_CORE_3_RESET			REG(0x3E0C)
+#define CE5_AHB_RESET				REG(0x3E10)
+#define NSS_RESET				REG(0x3E20)
+#define GMAC_AHB_RESET				REG(0x3E24)
+#define MACSEC_CORE1_RESET			REG(0x3E28)
+#define MACSEC_CORE2_RESET			REG(0x3E2C)
+#define MACSEC_CORE3_RESET			REG(0x3E30)
+#define NSS_TCM_RESET				REG(0x3E40)
+
+enum nss_hal_pvt_pll_status {
+	PLL_NOT_LOCKED,
+	PLL_LOCKED
+};
+
+#endif
+#endif /* __NSS_CLOCKS_H */
diff --git a/qca-nss-drv/nss_hal/ipq806x/nss_hal_pvt.c b/qca-nss-drv/nss_hal/ipq806x/nss_hal_pvt.c
new file mode 100644
index 0000000..b8733e0
--- /dev/null
+++ b/qca-nss-drv/nss_hal/ipq806x/nss_hal_pvt.c
@@ -0,0 +1,1237 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013, 2015-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_hal_pvt.c
+ *	NSS HAL private APIs.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/version.h>
+#include <linux/clk.h>
+#if (NSS_DT_SUPPORT != 1)
+#include <mach/gpiomux.h>
+#include <mach/msm_nss.h>
+#else
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/reset.h>
+#endif
+#include "nss_hal.h"
+#include "nss_clocks.h"
+#include "nss_core.h"
+#if (NSS_PM_SUPPORT == 1)
+#include "nss_pm.h"
+#endif
+#if (NSS_FABRIC_SCALING_SUPPORT == 1)
+#include <linux/fab_scaling.h>
+#endif
+
+#define NSS_H2N_INTR_EMPTY_BUFFER_QUEUE_BIT		0
+#define NSS_H2N_INTR_DATA_COMMAND_QUEUE_BIT		1
+#define NSS_H2N_INTR_TX_UNBLOCKED_BIT			11
+#define NSS_H2N_INTR_EMPTY_PAGED_BUFFER_QUEUE_BIT	12
+#define NSS_H2N_INTR_TRIGGER_COREDUMP_BIT		15
+
+/*
+ * Interrupt type to cause vector.
+ */
+static uint32_t intr_cause[] = {(1 << NSS_H2N_INTR_EMPTY_BUFFER_QUEUE_BIT),
+				(1 << NSS_H2N_INTR_DATA_COMMAND_QUEUE_BIT),
+				(1 << NSS_H2N_INTR_TX_UNBLOCKED_BIT),
+				(1 << NSS_H2N_INTR_TRIGGER_COREDUMP_BIT),
+				(1 << NSS_H2N_INTR_EMPTY_PAGED_BUFFER_QUEUE_BIT)};
+
+#if (NSS_DT_SUPPORT == 1)
+bool nss_crypto_is_scaled = false;
+#endif
+
+#if (NSS_FW_DBG_SUPPORT == 1)
+/*
+ * NSS debug pins configuration
+ */
+
+/*
+ * Core 0, Data
+ * No pull up, Function 2
+ */
+static struct gpiomux_setting nss_spi_data_0 = {
+	.func = GPIOMUX_FUNC_2,
+	.drv = GPIOMUX_DRV_8MA,
+	.pull = GPIOMUX_PULL_NONE,
+	.dir = GPIOMUX_IN,
+};
+
+/*
+ * Core 0, CLK, CS
+ * Pull up high, Function 2
+ */
+static struct gpiomux_setting nss_spi_cs_clk_0 = {
+	.func = GPIOMUX_FUNC_2,
+	.drv = GPIOMUX_DRV_8MA,
+	.pull = GPIOMUX_PULL_UP,
+	.dir = GPIOMUX_IN,
+};
+
+/*
+ * Core 1, CS
+ * Pull up high, Function 4
+ */
+static struct gpiomux_setting nss_spi_cs_1 = {
+	.func = GPIOMUX_FUNC_4,
+	.drv = GPIOMUX_DRV_8MA,
+	.pull = GPIOMUX_PULL_UP,
+	.dir = GPIOMUX_IN,
+};
+
+/*
+ * Core 1, CLK
+ * Pull up high, Function 5
+ */
+static struct gpiomux_setting nss_spi_clk_1 = {
+	.func = GPIOMUX_FUNC_5,
+	.drv = GPIOMUX_DRV_8MA,
+	.pull = GPIOMUX_PULL_UP,
+	.dir = GPIOMUX_IN,
+};
+
+/*
+ * Core 1, Data
+ * Pull up none, Function 5
+ */
+static struct gpiomux_setting nss_spi_data_1 = {
+	.func = GPIOMUX_FUNC_5,
+	.drv = GPIOMUX_DRV_8MA,
+	.pull = GPIOMUX_PULL_NONE,
+	.dir = GPIOMUX_IN,
+};
+
+static struct msm_gpiomux_config nss_spi_gpiomux[] = {
+	{
+		.gpio = 14,
+		.settings = {
+			[GPIOMUX_ACTIVE] = &nss_spi_data_0,
+			[GPIOMUX_SUSPENDED] = &nss_spi_data_0,
+		},
+	},
+	{
+		.gpio = 15,
+		.settings = {
+			[GPIOMUX_ACTIVE] = &nss_spi_data_0,
+			[GPIOMUX_SUSPENDED] = &nss_spi_data_0,
+		},
+	},
+	{
+		.gpio = 16,
+		.settings = {
+			[GPIOMUX_ACTIVE] = &nss_spi_cs_clk_0,
+			[GPIOMUX_SUSPENDED] = &nss_spi_cs_clk_0,
+		},
+	},
+	{
+		.gpio = 17,
+		.settings = {
+			[GPIOMUX_ACTIVE] = &nss_spi_cs_clk_0,
+			[GPIOMUX_SUSPENDED] = &nss_spi_cs_clk_0,
+		},
+	},
+	{
+		.gpio = 55,
+		.settings = {
+			[GPIOMUX_ACTIVE] = &nss_spi_data_1,
+			[GPIOMUX_SUSPENDED] = &nss_spi_data_1,
+		},
+	},
+	{
+		.gpio = 56,
+		.settings = {
+			[GPIOMUX_ACTIVE] = &nss_spi_data_1,
+			[GPIOMUX_SUSPENDED] = &nss_spi_data_1,
+		},
+	},
+	{
+		.gpio = 57,
+		.settings = {
+			[GPIOMUX_ACTIVE] = &nss_spi_cs_1,
+			[GPIOMUX_SUSPENDED] = &nss_spi_cs_1,
+		},
+	},
+	{
+		.gpio = 58,
+		.settings = {
+			[GPIOMUX_ACTIVE] = &nss_spi_clk_1,
+			[GPIOMUX_SUSPENDED] = &nss_spi_clk_1,
+		},
+	},
+};
+#endif /* NSS_FW_DBG_SUPPORT */
+
+/*
+ * nss_hal_scale_fabric()
+ *	DT supported fabric scaling
+ */
+void nss_hal_scale_fabric(uint32_t work_frequency)
+{
+#if (NSS_DT_SUPPORT == 1)
+	nss_crypto_pm_event_callback_t crypto_pm_cb;
+	bool auto_scale;
+	bool turbo;
+
+#if (NSS_FABRIC_SCALING_SUPPORT == 1)
+	/*
+	 * PM framework
+	 */
+	scale_fabrics();
+#endif
+	if ((nss_fab0_clk != NULL) && (nss_fab1_clk != NULL)) {
+		if (work_frequency >= NSS_FREQ_733) {
+			clk_set_rate(nss_fab0_clk, NSS_FABRIC0_TURBO);
+			clk_set_rate(nss_fab1_clk, NSS_FABRIC1_TURBO);
+		} else if (work_frequency > NSS_FREQ_110) {
+			clk_set_rate(nss_fab0_clk, NSS_FABRIC0_NOMINAL);
+			clk_set_rate(nss_fab1_clk, NSS_FABRIC1_NOMINAL);
+		} else {
+			clk_set_rate(nss_fab0_clk, NSS_FABRIC0_IDLE);
+			clk_set_rate(nss_fab1_clk, NSS_FABRIC1_IDLE);
+		}
+
+		/*
+		 * notify crypto about the clock change
+		 */
+		crypto_pm_cb = nss_top_main.crypto_pm_callback;
+		if (crypto_pm_cb) {
+			turbo = (work_frequency >= NSS_FREQ_733);
+			auto_scale = nss_cmd_buf.auto_scale;
+			nss_crypto_is_scaled = crypto_pm_cb(nss_top_main.crypto_pm_ctx, turbo, auto_scale);
+		}
+	}
+#endif
+}
+
+/*
+ * nss_hal_pm_support()
+ *	Supported in 3.4
+ */
+void nss_hal_pm_support(uint32_t work_frequency)
+{
+#if (NSS_PM_SUPPORT == 1)
+	if (!pm_client) {
+		return;
+	}
+
+	if (work_frequency >= NSS_FREQ_733) {
+		nss_pm_set_perf_level(pm_client, NSS_PM_PERF_LEVEL_TURBO);
+	} else if (work_frequency > NSS_FREQ_110) {
+		nss_pm_set_perf_level(pm_client, NSS_PM_PERF_LEVEL_NOMINAL);
+	} else {
+		nss_pm_set_perf_level(pm_client, NSS_PM_PERF_LEVEL_IDLE);
+	}
+#endif
+}
+
+/*
+ * nss_hal_freq_change()
+ *	Send frequency change message, and clock adjustment
+ */
+void nss_hal_freq_change(nss_work_t *my_work)
+{
+	nss_freq_change(&nss_top_main.nss[NSS_CORE_0], my_work->frequency, my_work->stats_enable, 0);
+	if (nss_top_main.nss[NSS_CORE_1].state == NSS_CORE_STATE_INITIALIZED) {
+		nss_freq_change(&nss_top_main.nss[NSS_CORE_1], my_work->frequency, my_work->stats_enable, 0);
+	}
+	clk_set_rate(nss_core0_clk, my_work->frequency);
+
+	nss_freq_change(&nss_top_main.nss[NSS_CORE_0], my_work->frequency, my_work->stats_enable, 1);
+	if (nss_top_main.nss[NSS_CORE_1].state == NSS_CORE_STATE_INITIALIZED) {
+		nss_freq_change(&nss_top_main.nss[NSS_CORE_1], my_work->frequency, my_work->stats_enable, 1);
+	}
+}
+
+/*
+ * nss_hal_wq_function()
+ *	Added to Handle BH requests to kernel
+ */
+void nss_hal_wq_function(struct work_struct *work)
+{
+	nss_work_t *my_work = (nss_work_t *)work;
+
+	mutex_lock(&nss_top_main.wq_lock);
+#if (NSS_DT_SUPPORT == 1)
+	/*
+	 * If crypto clock is in Turbo, disable scaling for other
+	 * NSS subsystem components and retain them at turbo
+	 */
+	if (nss_crypto_is_scaled) {
+		nss_cmd_buf.current_freq = nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency;
+		mutex_unlock(&nss_top_main.wq_lock);
+		return;
+	}
+#endif
+
+	nss_hal_freq_change(my_work);
+
+	/*
+	 * Supported in 3.4
+	 */
+	nss_hal_pm_support(my_work->frequency);
+
+	nss_hal_scale_fabric(my_work->frequency);
+
+	mutex_unlock(&nss_top_main.wq_lock);
+	kfree((void *)work);
+}
+
+/*
+ * nss_hal_handle_irq()
+ *	HLOS interrupt handler for nss interrupts
+ */
+static irqreturn_t nss_hal_handle_irq(int irq, void *ctx)
+{
+	struct int_ctx_instance *int_ctx = (struct int_ctx_instance *) ctx;
+	struct nss_ctx_instance *nss_ctx = int_ctx->nss_ctx;
+
+	/*
+	 * Mask interrupt until our bottom half re-enables it
+	 */
+	nss_hal_disable_interrupt(nss_ctx, int_ctx->shift_factor, NSS_HAL_SUPPORTED_INTERRUPTS);
+
+	/*
+	 * Schedule tasklet to process interrupt cause
+	 */
+	napi_schedule(&int_ctx->napi);
+	return IRQ_HANDLED;
+}
+
+#if (NSS_DT_SUPPORT != 1)
+#if defined(NSS_ENABLE_CLK)
+/*
+ * nss_hal_pvt_enable_pll18()
+ *	Enable PLL18
+ */
+static uint32_t nss_hal_pvt_enable_pll18(uint32_t speed)
+{
+	uint32_t retries = 100;
+
+	/*
+	 * Prevent Compiler from commenting out the loop.
+	 */
+	uint32_t value;
+	uint32_t mask = (1 << 2);
+
+	/*
+	 * Start with clean slate
+	 */
+	writel(0, PLL18_MODE);
+
+	/*
+	 * Effective VCO Frequency = 1100 MHz Post Divide 2
+	 */
+	if (speed == 1100) {
+		writel(0x4000042C, PLL18_L_VAL);
+		writel(0x0, PLL18_M_VAL);
+		writel(0x1, PLL18_N_VAL);
+
+		/*
+		 * PLL configuration (as provided by HW team)
+		 */
+		writel(0x01495625, PLL18_CONFIG);
+		writel(0x00003080, PLL18_TEST_CTL);
+	} else if (speed == 1466) {
+		/*
+		 * Effective VCO Frequency = 1466 MHz Post Divide 2
+		 */
+
+		writel(0x4000043A, PLL18_L_VAL);
+		writel(0x10, PLL18_M_VAL);
+		writel(0x19, PLL18_N_VAL);
+
+		/*
+		 * PLL configuration (as provided by HW team)
+		 */
+		writel(0x014B5625, PLL18_CONFIG);
+		writel(0x00003080, PLL18_TEST_CTL);
+	} else {
+		BUG_ON(1);
+	}
+
+	/*
+	 * Enable PLL18 output (sequence provided by HW team)
+	 */
+	writel(0x2, PLL18_MODE);
+	mdelay(1);
+	writel(0x6, PLL18_MODE);
+	writel(0x7, PLL18_MODE);
+
+	/*
+	 * Enable NSS Vote for PLL18.
+	 */
+	writel(mask, PLL_ENA_NSS);
+	do {
+		value = readl(PLL_LOCK_DET_STATUS);
+		if (value & mask) {
+			return PLL_LOCKED;
+		}
+
+		mdelay(1);
+	} while (retries-- > 0);
+
+	return PLL_NOT_LOCKED;
+}
+#endif
+#else
+/*
+ * __nss_hal_of_get_pdata()
+ *	Retrieve platform data from device node.
+ */
+static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device *pdev)
+{
+	struct device_node *np = of_node_get(pdev->dev.of_node);
+	struct nss_platform_data *npd;
+	struct nss_ctx_instance *nss_ctx = NULL;
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct resource res_nphys, res_vphys;
+	int32_t i;
+
+	npd = devm_kzalloc(&pdev->dev, sizeof(struct nss_platform_data), GFP_KERNEL);
+	if (!npd) {
+		return NULL;
+	}
+
+	if (of_property_read_u32(np, "qcom,id", &npd->id)
+	    || of_property_read_u32(np, "qcom,load-addr", &npd->load_addr)
+	    || of_property_read_u32(np, "qcom,num-queue", &npd->num_queue)
+	    || of_property_read_u32(np, "qcom,num-irq", &npd->num_irq)) {
+		pr_err("%s: error reading critical device node properties\n", np->name);
+		goto out;
+	}
+
+	/*
+	 * Read frequencies. If failure, load default values.
+	 */
+	of_property_read_u32(np, "qcom,low-frequency", &nss_runtime_samples.freq_scale[NSS_FREQ_LOW_SCALE].frequency);
+	of_property_read_u32(np, "qcom,mid-frequency", &nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency);
+	of_property_read_u32(np, "qcom,max-frequency", &nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency);
+
+	if (npd->num_irq < npd->num_queue) {
+		pr_err("%s: not enough interrupts configured for all the queues\n", np->name);
+		goto out;
+	}
+
+	if (npd->num_irq > NSS_MAX_IRQ_PER_CORE) {
+		pr_err("%s: exceeds maximum interrupt numbers per core\n", np->name);
+		goto out;
+	}
+
+	nss_ctx = &nss_top->nss[npd->id];
+	nss_ctx->id = npd->id;
+
+	if (of_address_to_resource(np, 0, &res_nphys) != 0) {
+		nss_info_always("%px: nss%d: of_address_to_resource() fail for nphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	if (of_address_to_resource(np, 1, &res_vphys) != 0) {
+		nss_info_always("%px: nss%d: of_address_to_resource() fail for vphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	/*
+	 * Save physical addresses
+	 */
+	npd->nphys = res_nphys.start;
+	npd->vphys = res_vphys.start;
+
+	npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys));
+	if (!npd->nmap) {
+		nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	nss_assert(npd->vphys);
+	npd->vmap = ioremap_cache(npd->vphys, resource_size(&res_vphys));
+	if (!npd->vmap) {
+		nss_info_always("%px: nss%d: ioremap() fail for vphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	/*
+	 * Clear TCM memory used by this core
+	 */
+	for (i = 0; i < resource_size(&res_vphys) ; i += 4) {
+		nss_write_32(npd->vmap, i, 0);
+		NSS_CORE_DMA_CACHE_MAINT((npd->vmap + i), 4, DMA_TO_DEVICE);
+	}
+	NSS_CORE_DSB();
+
+	/*
+	 * Get IRQ numbers
+	 */
+	for (i = 0 ; i < npd->num_irq; i++) {
+		npd->irq[i] = irq_of_parse_and_map(np, i);
+		if (!npd->irq[i]) {
+			nss_info_always("%px: nss%d: irq_of_parse_and_map() fail for irq %d\n", nss_ctx, nss_ctx->id, i);
+			goto out;
+		}
+	}
+
+	nss_hal_dt_parse_features(np, npd);
+
+	of_node_put(np);
+	return npd;
+
+out:
+	if (npd->nmap) {
+		iounmap(npd->nmap);
+	}
+
+	if (npd->vmap) {
+		iounmap(npd->vmap);
+	}
+
+	devm_kfree(&pdev->dev, npd);
+	of_node_put(np);
+	return NULL;
+}
+#endif
+
+/*
+ * __nss_hal_core_reset()
+ */
+static int __nss_hal_core_reset(struct platform_device *nss_dev, void __iomem *map, uint32_t addr, uint32_t clk_src)
+{
+#if (NSS_DT_SUPPORT == 1)
+	struct reset_control *rstctl = NULL;
+
+	/*
+	 * Remove UBI32 reset clamp
+	 */
+	rstctl = devm_reset_control_get(&nss_dev->dev, "clkrst-clamp");
+	if (IS_ERR(rstctl)) {
+		nss_info_always("%px: Deassert UBI32 core%d reset clamp failed", nss_dev, nss_dev->id);
+		return -EFAULT;
+	}
+	reset_control_deassert(rstctl);
+
+	/*
+	 * Remove UBI32 core clamp
+	 */
+	rstctl = devm_reset_control_get(&nss_dev->dev, "clamp");
+	if (IS_ERR(rstctl)) {
+		nss_info_always("%px: Deassert UBI32 core%d clamp failed", nss_dev, nss_dev->id);
+		return -EFAULT;
+	}
+	reset_control_deassert(rstctl);
+
+	/*
+	 * Remove UBI32 AHB reset
+	 */
+	rstctl = devm_reset_control_get(&nss_dev->dev, "ahb");
+	if (IS_ERR(rstctl)) {
+		nss_info_always("%px: Deassert AHB core%d reset failed", nss_dev, nss_dev->id);
+		return -EFAULT;
+	}
+	reset_control_deassert(rstctl);
+
+	/*
+	 * Remove UBI32 AXI reset
+	 */
+	rstctl = devm_reset_control_get(&nss_dev->dev, "axi");
+	if (IS_ERR(rstctl)) {
+		nss_info_always("%px: Deassert core%d AXI reset failed", nss_dev, nss_dev->id);
+		return -EFAULT;
+	}
+	reset_control_deassert(rstctl);
+#else
+#if defined(NSS_ENABLE_CLOCK)
+	/*
+	 * Enable mpt clock
+	 */
+	writel(0x10, UBI32_MPT0_CLK_CTL);
+
+	/*
+	 * UBI coren clock root enable
+	 */
+	if (clk_src == NSS_REGS_CLK_SRC_DEFAULT) {
+		/* select Src0 */
+		writel(0x02, UBI32_COREn_CLK_SRC_CTL(nss_dev->id));
+	} else {
+		/* select Src1 */
+		writel(0x03, UBI32_COREn_CLK_SRC_CTL(nss_dev->id));
+	}
+
+	/*
+	 * Src0: Bypass M value configuration.
+	 */
+
+	/*
+	 * Src1: M val is 0x01 and NOT_2D value is 0xfd, 400 MHz with PLL0.
+	 */
+	writel(0x100fd, UBI32_COREn_CLK_SRC1_MD(nss_dev->id));
+
+	/*
+	 * Bypass, pll18
+	 * Effective frequency = 550 MHz
+	 */
+	writel(0x00000001, UBI32_COREn_CLK_SRC0_NS(nss_dev->id));
+
+	/*
+	 * Dual edge, pll0, NOT(N_M) = 0xfe.
+	 * Effective frequency = 400 MHz
+	 */
+	writel(0x00fe0142, UBI32_COREn_CLK_SRC1_NS(nss_dev->id));
+
+	/*
+	 * UBI32 coren clock control branch.
+	 */
+	writel(0x4f, UBI32_COREn_CLK_FS(nss_dev->id));
+
+	/*
+	 * UBI32 coren clock control branch.
+	 */
+	writel(0x10, UBI32_COREn_CLK_CTL(nss_dev->id));
+#endif
+	/*
+	 * Remove UBI32 reset clamp
+	 */
+	writel(0xB, UBI32_COREn_RESET_CLAMP(nss_dev->id));
+
+	/*
+	 * Busy wait for few cycles
+	 */
+	mdelay(1);
+
+	/*
+	 * Remove UBI32 core clamp
+	 */
+	writel(0x3, UBI32_COREn_RESET_CLAMP(nss_dev->id));
+
+	mdelay(1);
+
+	/*
+	 * Remove UBI32 AHB reset
+	 */
+	writel(0x1, UBI32_COREn_RESET_CLAMP(nss_dev->id));
+
+	mdelay(1);
+
+	/*
+	 * Remove UBI32 AXI reset
+	 */
+	writel(0x0, UBI32_COREn_RESET_CLAMP(nss_dev->id));
+
+	mdelay(1);
+#endif /* NSS_DT_SUPPORT */
+
+	/*
+	 * Apply ubi32 core reset
+	 */
+	nss_write_32(map, NSS_REGS_RESET_CTRL_OFFSET, 1);
+
+	/*
+	 * Program address configuration
+	 */
+	nss_write_32(map, NSS_REGS_CORE_AMC_OFFSET, 1);
+	nss_write_32(map, NSS_REGS_CORE_BAR_OFFSET, 0x3c000000);
+	nss_write_32(map, NSS_REGS_CORE_BOOT_ADDR_OFFSET, addr);
+
+	/*
+	 * C2C interrupts are level sensitive
+	 */
+	nss_write_32(map, NSS_REGS_CORE_INT_STAT2_TYPE_OFFSET, 0xFFFF);
+
+	/*
+	 * Enable Instruction Fetch range checking between 0x4000 0000 to 0xBFFF FFFF.
+	 */
+	nss_write_32(map, NSS_REGS_CORE_IFETCH_RANGE_OFFSET, 0xBF004001);
+
+	/*
+	 * De-assert ubi32 core reset
+	 */
+	nss_write_32(map, NSS_REGS_RESET_CTRL_OFFSET, 0);
+
+	return 0;
+}
+
+/*
+ * __nss_hal_debug_enable()
+ *	Enable NSS debug
+ */
+static void __nss_hal_debug_enable(void)
+{
+#if (NSS_FW_DBG_SUPPORT == 1)
+	msm_gpiomux_install(nss_spi_gpiomux,
+				ARRAY_SIZE(nss_spi_gpiomux));
+#endif
+}
+
+/*
+ * __nss_hal_common_reset
+ *	Do reset/clock configuration common to all cores
+ */
+static int __nss_hal_common_reset(struct platform_device *nss_dev)
+{
+#if (NSS_DT_SUPPORT == 1)
+	struct device_node *cmn = NULL;
+	struct resource res_nss_fpb_base;
+	struct clk *nss_tcm_src = NULL;
+	struct clk *nss_tcm_clk = NULL;
+	void __iomem *fpb_base;
+	int err;
+
+	/*
+	 * Get reference to NSS common device node
+	 */
+	cmn = of_find_node_by_name(NULL, "nss-common");
+	if (!cmn) {
+		pr_err("%px: Unable to find nss-common node\n", nss_dev);
+		return -EFAULT;
+	}
+
+	if (of_address_to_resource(cmn, 0, &res_nss_fpb_base) != 0) {
+		pr_err("%px: of_address_to_resource() return error for nss_fpb_base\n", nss_dev);
+		of_node_put(cmn);
+		return -EFAULT;
+	}
+	of_node_put(cmn);
+
+	fpb_base = ioremap_nocache(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base));
+	if (!fpb_base) {
+		pr_err("%px: ioremap fail for nss_fpb_base\n", nss_dev);
+		return -EFAULT;
+	}
+
+	/*
+	 * Attach debug interface to TLMM
+	 */
+	nss_write_32(fpb_base, NSS_REGS_FPB_CSR_CFG_OFFSET, 0x360);
+
+	/*
+	 * NSS TCM CLOCK
+	 */
+	nss_tcm_src = clk_get(&nss_dev->dev, NSS_TCM_SRC_CLK);
+	if (IS_ERR(nss_tcm_src)) {
+		pr_err("%px: cannot get clock: %s\n", nss_dev, NSS_TCM_SRC_CLK);
+		return -EFAULT;
+	}
+
+	err = clk_set_rate(nss_tcm_src, NSSTCM_FREQ);
+	if (err) {
+		pr_err("%px: cannot set NSSTCM freq\n", nss_dev);
+		return -EFAULT;
+	}
+
+	err = clk_prepare_enable(nss_tcm_src);
+	if (err) {
+		pr_err("%px: cannot enable NSSTCM clock source\n", nss_dev);
+		return -EFAULT;
+	}
+
+	nss_tcm_clk = clk_get(&nss_dev->dev, NSS_TCM_CLK);
+	if (IS_ERR(nss_tcm_clk)) {
+		pr_err("%px: cannot get clock: %s\n", nss_dev, NSS_TCM_CLK);
+		return -EFAULT;
+	}
+
+	err = clk_prepare_enable(nss_tcm_clk);
+	if (err) {
+		pr_err("%px: cannot enable NSSTCM clock\n", nss_dev);
+		return -EFAULT;
+	}
+
+	/*
+	 * NSS Fabric Clocks.
+	 */
+	nss_fab0_clk = clk_get(&nss_dev->dev, NSS_FABRIC0_CLK);
+	if (IS_ERR(nss_fab0_clk)) {
+		pr_err("%px: cannot get clock: %s\n", nss_dev, NSS_FABRIC0_CLK);
+		nss_fab0_clk = NULL;
+	} else {
+		err = clk_prepare_enable(nss_fab0_clk);
+		if (err) {
+			pr_err("%px: cannot enable clock: %s\n", nss_dev, NSS_FABRIC0_CLK);
+			return -EFAULT;
+		}
+	}
+
+	nss_fab1_clk = clk_get(&nss_dev->dev, NSS_FABRIC1_CLK);
+	if (IS_ERR(nss_fab1_clk)) {
+		pr_err("%px: cannot get clock: %s\n", nss_dev, NSS_FABRIC1_CLK);
+		nss_fab1_clk = NULL;
+	} else {
+		err = clk_prepare_enable(nss_fab1_clk);
+		if (err) {
+			pr_err("%px: cannot enable clock: %s\n", nss_dev, NSS_FABRIC1_CLK);
+			return -EFAULT;
+		}
+	}
+
+	nss_top_main.nss_hal_common_init_done = true;
+	nss_info("nss_hal_common_reset Done\n");
+	return 0;
+}
+#else
+	uint32_t i;
+	uint32_t value;
+	uint32_t status_mask = 0x1;
+	uint32_t wait_cycles = 100;
+
+#if defined(NSS_ENABLE_CLK)
+	/*
+	 * NSS FPB CLOCK
+	 */
+
+	/*
+	 * Enable clock root and Divider 0
+	 * NOTE: Default value is good so no work here
+	 */
+
+	/*
+	 * PLL0 (800 MHZ). SRC_SEL is 2 (3'b010)
+	 * src_div selected is Div-6 (4'b0101).
+	 *
+	 * Effective frequency (Divider 0) = 133 MHz
+	 */
+	writel(0x2a, NSSFPB_CLK_SRC0_NS);
+
+	/*
+	 * Enable clock branch
+	 */
+	writel(0x50, NSSFPB_CLK_CTL);
+
+	/*
+	 * NSS FABRIC0 CLOCK
+	 */
+
+	/*
+	 * Enable clock root and Divider 0
+	 * NOTE: Default value is good so no work here
+	 */
+
+	/*
+	 * PLL0 (800 MHZ) and div is set to 2.
+	 * Effective frequency = 400 MHZ.
+	 */
+	writel(0x0a, NSSFB0_CLK_SRC0_NS);
+
+	/*
+	 * NSS Fabric0 Branch and dynamic clock gating enabled.
+	 */
+	writel(0x50, NSSFB0_CLK_CTL);
+
+	/*
+	 * Enable clock root and Divider 0
+	 * NOTE: Default value is good so no work here
+	 */
+
+	/*
+	 * PLL0 (800 MHZ) and div is set to 4.
+	 * Effective frequency = 200 MHZ.
+	 */
+	writel(0x1a, NSSFB1_CLK_SRC0_NS);
+
+	/*
+	 * NSS Fabric1 Branch enable and fabric clock gating enabled.
+	 */
+	writel(0x50, NSSFB1_CLK_CTL);
+
+	/*
+	 * NSS TCM CLOCK
+	 */
+
+	/*
+	 * Enable NSS TCM clock root source and select divider 0.
+	 *
+	 * NOTE: Default value is not good here
+	 */
+	writel(0x2, NSSTCM_CLK_SRC_CTL);
+
+	/*
+	 * PLL0 (800 MHZ) and div is set to 2.
+	 * Effective frequency = 400 MHZ
+	 */
+	writel(0xa, NSSTCM_CLK_SRC0_NS);
+
+	/*
+	 * NSS TCM Branch enable and fabric clock gating enabled.
+	 */
+	writel(0x50, NSSTCM_CLK_CTL);
+
+	/*
+	 * Enable global NSS clock branches.
+	 * NSS global Fab Branch enable and fabric clock gating enabled.
+	 */
+	writel(0xf, NSSFAB_GLOBAL_BUS_NS);
+
+	/*
+	 * Send reset interrupt to NSS
+	 */
+	writel(0x0, NSS_RESET);
+
+	/*
+	 * Enable PLL18
+	 */
+	pll18_status = nss_hal_pvt_enable_pll18();
+	if (!pll18_status) {
+		/*
+		 * Select alternate good source (Src1/pll0)
+		 */
+		nss_top->clk_src = NSS_REGS_CLK_SRC_ALTERNATE;
+		return;
+	}
+
+	/*
+	 * Select default source (Src0/pll18)
+	 */
+	nss_top->clk_src = NSS_REGS_CLK_SRC_DEFAULT;
+#endif
+
+	/*
+	 * Attach debug interface to TLMM
+	 */
+	nss_write_32((uint32_t)MSM_NSS_FPB_BASE, NSS_REGS_FPB_CSR_CFG_OFFSET, 0x360);
+
+	/*
+	 * NSS TCM CLOCK
+	 */
+
+	/*
+	 * Enable NSS TCM clock root source - SRC1.
+	 *
+	 */
+	writel(0x3, NSSTCM_CLK_SRC_CTL);
+
+	/* Enable PLL Voting for 0 */
+	writel((readl(PLL_ENA_NSS) | 0x1), PLL_ENA_NSS);
+	do {
+		value = readl(PLL_LOCK_DET_STATUS);
+		if (value & status_mask) {
+			break;
+		}
+		mdelay(1);
+	} while (wait_cycles-- > 0);
+
+	/*
+	 * PLL0 (800 MHZ) and div is set to 3/4.
+	 * Effective frequency = 266/400 Mhz for SRC0/1
+	 */
+	writel(0x12, NSSTCM_CLK_SRC0_NS);
+	writel(0xa, NSSTCM_CLK_SRC1_NS);
+
+	/*
+	 * NSS TCM Branch enable and fabric clock gating enabled.
+	 */
+	writel(0x50, NSSTCM_CLK_CTL);
+
+	/*
+	 * Clear TCM memory
+	 */
+	for (i = 0; i < IPQ806X_NSS_TCM_SIZE; i += 4) {
+		nss_write_32((uint32_t)MSM_NSS_TCM_BASE, i, 0);
+	}
+
+	return 0;
+}
+#endif /* NSS_DT_SUPPORT */
+
+/*
+ * __nss_hal_clock_configure()
+ */
+static int __nss_hal_clock_configure(struct nss_ctx_instance *nss_ctx, struct platform_device *nss_dev, struct nss_platform_data *npd)
+{
+#if (NSS_FABRIC_SCALING_SUPPORT == 1)
+	struct fab_scaling_info fab_data;
+#endif
+	int i, err;
+
+	/*
+	 * Both ubi core on ipq806x attach to the same clock, configure just the core0
+	 */
+	if (nss_ctx->id) {
+		return 0;
+	}
+
+	nss_core0_clk = clk_get(&nss_dev->dev, NSS_CORE_CLK);
+	if (IS_ERR(nss_core0_clk)) {
+		err = PTR_ERR(nss_core0_clk);
+		nss_info_always("%px: Regulator %s get failed, err=%d\n", nss_ctx, dev_name(&nss_dev->dev), err);
+		return err;
+	}
+
+	/*
+	 * Check if turbo is supported
+	 */
+	if (npd->turbo_frequency) {
+		nss_info_always("nss_driver - Turbo Support %d\n", npd->turbo_frequency);
+#if (NSS_PM_SUPPORT == 1)
+		nss_pm_set_turbo();
+#endif
+	} else {
+		nss_info_always("nss_driver - Turbo No Support %d\n", npd->turbo_frequency);
+	}
+
+	/*
+	 * If valid entries - from dtsi - then just init clks.
+	 * Otherwise query for clocks.
+	 */
+	if ((nss_runtime_samples.freq_scale[NSS_FREQ_LOW_SCALE].frequency != 0) &&
+		(nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency != 0) &&
+		(nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency != 0)) {
+		goto clk_complete;
+	}
+
+	/*
+	 * Load default scales, then query for higher.
+	 * If basic set cannot be set, then go to error, and abort
+	 * Two set of defaults, 110, 550, 733 or 110, 275 and 550
+	 */
+	if (clk_set_rate(nss_core0_clk, NSS_FREQ_110) != 0) {
+		return -EFAULT;
+	}
+	nss_runtime_samples.freq_scale[NSS_FREQ_LOW_SCALE].frequency = NSS_FREQ_110;
+
+	if (npd->turbo_frequency) {
+		/*
+		 * Figure out the middle scale
+		 */
+		if (clk_set_rate(nss_core0_clk, NSS_FREQ_600) == 0) {
+			nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency = NSS_FREQ_600;
+		} else if (clk_set_rate(nss_core0_clk, NSS_FREQ_550) == 0) {
+			nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency = NSS_FREQ_550;
+		} else {
+			return -EFAULT;
+		}
+
+		/*
+		 * Figure out the max scale
+		 */
+		if (clk_set_rate(nss_core0_clk, NSS_FREQ_800) == 0) {
+			nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency = NSS_FREQ_800;
+		} else if (clk_set_rate(nss_core0_clk, NSS_FREQ_733) == 0) {
+			nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency = NSS_FREQ_733;
+		} else {
+			return -EFAULT;
+		}
+
+	} else {
+		if (clk_set_rate(nss_core0_clk, NSS_FREQ_275) != 0) {
+			return -EFAULT;
+		}
+		nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency = NSS_FREQ_275;
+
+		if (clk_set_rate(nss_core0_clk, NSS_FREQ_550) != 0) {
+			return -EFAULT;
+		}
+		nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency = NSS_FREQ_550;
+	}
+
+clk_complete:
+#if (NSS_FABRIC_SCALING_SUPPORT == 1)
+	if (npd->turbo_frequency) {
+		fab_data.idle_freq = nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency;
+	} else {
+		fab_data.idle_freq = nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency;
+	}
+	fab_data.clk = nss_core0_clk;
+	fab_scaling_register(&fab_data);
+#endif
+
+	/*
+	 * Setup Ranges
+	 */
+	for (i = 0; i < NSS_FREQ_MAX_SCALE; i++) {
+		if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_110) {
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_110_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_110_MAX;
+		}
+		if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_275) {
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_275_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_275_MAX;
+		}
+		if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_550) {
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_550_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_550_MAX;
+		}
+		if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_600) {
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_600_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_600_MAX;
+		}
+		if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_733) {
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_733_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_733_MAX;
+		}
+		if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_800) {
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_800_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_800_MAX;
+		}
+	}
+
+	nss_info_always("Supported Frequencies - ");
+	for (i = 0; i < NSS_FREQ_MAX_SCALE; i++) {
+		if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_110) {
+			nss_info_always("110Mhz ");
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_275) {
+			nss_info_always("275Mhz ");
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_550) {
+			nss_info_always("550Mhz ");
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_600) {
+			nss_info_always("600Mhz ");
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_733) {
+			nss_info_always("733Mhz ");
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_800) {
+			nss_info_always("800Mhz ");
+		} else {
+			nss_info_always("Error\nNo Table/Invalid Frequency Found - Loading Old Tables -");
+			return -EFAULT;
+		}
+	}
+	nss_info_always("\n");
+
+	/*
+	 * Set default frequency
+	 */
+	err = clk_set_rate(nss_core0_clk, nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency);
+	if (err) {
+		nss_info_always("%px: cannot set nss core0 clock\n", nss_ctx);
+		return -EFAULT;
+	}
+
+	err = clk_prepare_enable(nss_core0_clk);
+	if (err) {
+		nss_info_always("%px: cannot enable nss core0 clock\n", nss_ctx);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/*
+ * __nss_hal_read_interrupt_cause()
+ */
+static void __nss_hal_read_interrupt_cause(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t *cause)
+{
+	uint32_t value = nss_read_32(nss_ctx->nmap, NSS_REGS_N2H_INTR_STATUS_OFFSET);
+	*cause = (((value) >> shift_factor) & 0x7FFF);
+}
+
+/*
+ * __nss_hal_clear_interrupt_cause()
+ */
+static void __nss_hal_clear_interrupt_cause(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+	nss_write_32(nss_ctx->nmap, NSS_REGS_N2H_INTR_CLR_OFFSET, (cause << shift_factor));
+}
+
+/*
+ * __nss_hal_disable_interrupt()
+ */
+static void __nss_hal_disable_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+	nss_write_32(nss_ctx->nmap, NSS_REGS_N2H_INTR_MASK_CLR_OFFSET, (cause << shift_factor));
+}
+
+/*
+ * __nss_hal_enable_interrupt()
+ */
+static void __nss_hal_enable_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+	nss_write_32(nss_ctx->nmap, NSS_REGS_N2H_INTR_MASK_SET_OFFSET, (cause << shift_factor));
+}
+
+/*
+ * __nss_hal_send_interrupt()
+ */
+static void __nss_hal_send_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t type)
+{
+	nss_write_32(nss_ctx->nmap, NSS_REGS_C2C_INTR_SET_OFFSET, intr_cause[type]);
+}
+
+/*
+ * __nss_hal_request_irq()
+ */
+static int __nss_hal_request_irq(struct nss_ctx_instance *nss_ctx, struct nss_platform_data *npd, int irq_num)
+{
+	struct int_ctx_instance *int_ctx = &nss_ctx->int_ctx[irq_num];
+	int err;
+
+	if (irq_num == 1) {
+		int_ctx->shift_factor = 15;
+		err = request_irq(npd->irq[irq_num], nss_hal_handle_irq, 0, "nss_queue1", int_ctx);
+	} else {
+		int_ctx->shift_factor = 0;
+		err = request_irq(npd->irq[irq_num], nss_hal_handle_irq, 0, "nss", int_ctx);
+	}
+	if (err) {
+		nss_info_always("%px: IRQ%d request failed", nss_ctx, npd->irq[irq_num]);
+		return err;
+	}
+
+	int_ctx->irq = npd->irq[irq_num];
+	netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi, 64);
+
+	return 0;
+}
+
+/*
+ * __nss_hal_init_imem
+ */
+void __nss_hal_init_imem(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
+
+	mem_ctx->imem_head = NSS_IMEM_START + NSS_IMEM_SIZE * nss_ctx->id;
+	mem_ctx->imem_end = mem_ctx->imem_head + NSS_IMEM_SIZE;
+	mem_ctx->imem_tail = mem_ctx->imem_head;
+
+	nss_info("%px: IMEM init: head: 0x%x end: 0x%x tail: 0x%x\n", nss_ctx,
+			mem_ctx->imem_head, mem_ctx->imem_end, mem_ctx->imem_tail);
+}
+
+/*
+ * __nss_hal_init_utcm_shared
+ */
+bool __nss_hal_init_utcm_shared(struct nss_ctx_instance *nss_ctx, uint32_t *meminfo_start)
+{
+	/*
+	 * Nothing to be done as there are no UTCM_SHARED defined for ipq806x
+	 */
+	return true;
+}
+
+/*
+ * nss_hal_ipq806x_ops
+ */
+struct nss_hal_ops nss_hal_ipq806x_ops = {
+	.common_reset = __nss_hal_common_reset,
+	.core_reset = __nss_hal_core_reset,
+	.clock_configure = __nss_hal_clock_configure,
+	.firmware_load = nss_hal_firmware_load,
+	.debug_enable = __nss_hal_debug_enable,
+#if (NSS_DT_SUPPORT == 1)
+	.of_get_pdata = __nss_hal_of_get_pdata,
+#endif
+	.request_irq = __nss_hal_request_irq,
+	.send_interrupt = __nss_hal_send_interrupt,
+	.enable_interrupt = __nss_hal_enable_interrupt,
+	.disable_interrupt = __nss_hal_disable_interrupt,
+	.clear_interrupt_cause = __nss_hal_clear_interrupt_cause,
+	.read_interrupt_cause = __nss_hal_read_interrupt_cause,
+	.init_imem = __nss_hal_init_imem,
+	.init_utcm_shared = __nss_hal_init_utcm_shared,
+};
diff --git a/qca-nss-drv/nss_hal/ipq807x/nss_hal_pvt.c b/qca-nss-drv/nss_hal/ipq807x/nss_hal_pvt.c
new file mode 100644
index 0000000..b95a23c
--- /dev/null
+++ b/qca-nss-drv/nss_hal/ipq807x/nss_hal_pvt.c
@@ -0,0 +1,771 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_hal_pvt.c
+ *	NSS HAL private APIs.
+ */
+
+#include <linux/err.h>
+#include <linux/version.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include "nss_hal.h"
+#include "nss_core.h"
+
+#define NSS_QGIC_IPC_REG_OFFSET 0x8
+
+#define NSS0_H2N_INTR_BASE 13
+#define NSS1_H2N_INTR_BASE 19
+
+/*
+ * Common CLKs
+ */
+#define NSS_NOC_CLK "nss-noc-clk"
+#define NSS_PTP_REF_CLK "nss-ptp-ref-clk"
+#define NSS_CSR_CLK "nss-csr-clk"
+#define NSS_CFG_CLK "nss-cfg-clk"
+#define NSS_IMEM_CLK "nss-imem-clk"
+#define NSS_NSSNOC_QOSGEN_REF_CLK "nss-nssnoc-qosgen-ref-clk"
+#define NSS_MEM_NOC_NSS_AXI_CLK "nss-mem-noc-nss-axi-clk"
+#define NSS_NSSNOC_SNOC_CLK "nss-nssnoc-snoc-clk"
+#define NSS_NSSNOC_TIMEOUT_REF_CLK "nss-nssnoc-timeout-ref-clk"
+#define NSS_CE_AXI_CLK "nss-ce-axi-clk"
+#define NSS_CE_APB_CLK "nss-ce-apb-clk"
+#define NSS_NSSNOC_CE_AXI_CLK "nss-nssnoc-ce-axi-clk"
+#define NSS_NSSNOC_CE_APB_CLK "nss-nssnoc-ce-apb-clk"
+
+/*
+ * Per-core CLKS
+ */
+#define NSS_NSSNOC_AHB_CLK "nss-nssnoc-ahb-clk"
+#define NSS_CORE_CLK "nss-core-clk"
+#define NSS_AHB_CLK "nss-ahb-clk"
+#define NSS_AXI_CLK "nss-axi-clk"
+#define NSS_MPT_CLK "nss-mpt-clk"
+#define NSS_NC_AXI_CLK "nss-nc-axi-clk"
+
+/*
+ * Voltage values
+ */
+#define NOMINAL_VOLTAGE 1
+#define TURBO_VOLTAGE 2
+
+/*
+ * Core reset part 1
+ */
+#define NSS_CORE_GCC_RESET_1 0x00000020
+
+/*
+ * Core reset part 2
+ */
+#define NSS_CORE_GCC_RESET_2 0x00000017
+
+/*
+ * Voltage regulator
+ */
+struct regulator *npu_reg;
+
+/*
+ * GCC reset
+ */
+void __iomem *nss_misc_reset;
+
+/*
+ * Purpose of each interrupt index: This should match the order defined in the NSS firmware
+ */
+enum nss_hal_n2h_intr_purpose {
+	NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS = 0,
+	NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE = 1,
+	NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED = 2,
+	NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0 = 3,
+	NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1 = 4,
+	NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2 = 5,
+	NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3 = 6,
+	NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE = 7,
+	NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS = 8,
+	NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA = 9,
+	NSS_HAL_N2H_INTR_PURPOSE_MAX
+};
+
+/*
+ * Interrupt type to cause vector.
+ */
+static uint32_t intr_cause[NSS_MAX_CORES][NSS_H2N_INTR_TYPE_MAX] = {
+				/* core0 */
+				{(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_EMPTY_BUFFER_QUEUE)),
+				(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_DATA_COMMAND_QUEUE)),
+				(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_TX_UNBLOCKED)),
+				(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_TRIGGER_COREDUMP)),
+				(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_EMPTY_PAGED_BUFFER_QUEUE))},
+				/* core 1 */
+				{(1 << (NSS1_H2N_INTR_BASE + NSS_H2N_INTR_EMPTY_BUFFER_QUEUE)),
+				(1 << (NSS1_H2N_INTR_BASE + NSS_H2N_INTR_DATA_COMMAND_QUEUE)),
+				(1 << (NSS1_H2N_INTR_BASE + NSS_H2N_INTR_TX_UNBLOCKED)),
+				(1 << (NSS1_H2N_INTR_BASE + NSS_H2N_INTR_TRIGGER_COREDUMP)),
+				(1 << (NSS1_H2N_INTR_BASE + NSS_H2N_INTR_EMPTY_PAGED_BUFFER_QUEUE))}
+};
+
+/*
+ * nss_hal_wq_function()
+ *	Added to Handle BH requests to kernel
+ */
+void nss_hal_wq_function(struct work_struct *work)
+{
+	nss_work_t *my_work = (nss_work_t *)work;
+
+	mutex_lock(&nss_top_main.wq_lock);
+
+	if (my_work->frequency > NSS_FREQ_1497) {
+		regulator_set_voltage(npu_reg, TURBO_VOLTAGE, TURBO_VOLTAGE);
+	}
+
+	nss_freq_change(&nss_top_main.nss[NSS_CORE_0], my_work->frequency, my_work->stats_enable, 0);
+	if (nss_top_main.nss[NSS_CORE_1].state == NSS_CORE_STATE_INITIALIZED) {
+		nss_freq_change(&nss_top_main.nss[NSS_CORE_1], my_work->frequency, my_work->stats_enable, 0);
+	}
+	clk_set_rate(nss_core0_clk, my_work->frequency);
+
+	nss_freq_change(&nss_top_main.nss[NSS_CORE_0], my_work->frequency, my_work->stats_enable, 1);
+	if (nss_top_main.nss[NSS_CORE_1].state == NSS_CORE_STATE_INITIALIZED) {
+		nss_freq_change(&nss_top_main.nss[NSS_CORE_1], my_work->frequency, my_work->stats_enable, 1);
+	}
+
+	clk_set_rate(nss_core1_clk, my_work->frequency);
+	if (my_work->frequency <= NSS_FREQ_1497) {
+		regulator_set_voltage(npu_reg, NOMINAL_VOLTAGE, NOMINAL_VOLTAGE);
+	}
+
+	mutex_unlock(&nss_top_main.wq_lock);
+	kfree((void *)work);
+}
+
+/*
+ * nss_hal_handle_irq()
+ */
+static irqreturn_t nss_hal_handle_irq(int irq, void *ctx)
+{
+	struct int_ctx_instance *int_ctx = (struct int_ctx_instance *) ctx;
+
+	disable_irq_nosync(irq);
+	napi_schedule(&int_ctx->napi);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * __nss_hal_of_get_pdata()
+ *	Retrieve platform data from device node.
+ */
+static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device *pdev)
+{
+	struct device_node *np = of_node_get(pdev->dev.of_node);
+	struct nss_platform_data *npd;
+	struct nss_ctx_instance *nss_ctx = NULL;
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct resource res_nphys, res_vphys, res_qgic_phys;
+	int32_t i;
+
+	npd = devm_kzalloc(&pdev->dev, sizeof(struct nss_platform_data), GFP_KERNEL);
+	if (!npd) {
+		return NULL;
+	}
+
+	if (of_property_read_u32(np, "qcom,id", &npd->id)
+	    || of_property_read_u32(np, "qcom,load-addr", &npd->load_addr)
+	    || of_property_read_u32(np, "qcom,num-queue", &npd->num_queue)
+	    || of_property_read_u32(np, "qcom,num-irq", &npd->num_irq)) {
+		pr_err("%s: error reading critical device node properties\n", np->name);
+		goto out;
+	}
+
+	/*
+	 * Read frequencies. If failure, load default values.
+	 */
+	of_property_read_u32(np, "qcom,low-frequency", &nss_runtime_samples.freq_scale[NSS_FREQ_LOW_SCALE].frequency);
+	of_property_read_u32(np, "qcom,mid-frequency", &nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency);
+	of_property_read_u32(np, "qcom,max-frequency", &nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency);
+
+	if (npd->num_irq > NSS_MAX_IRQ_PER_CORE) {
+		pr_err("%s: exceeds maximum interrupt numbers per core\n", np->name);
+		goto out;
+	}
+
+	nss_ctx = &nss_top->nss[npd->id];
+	nss_ctx->id = npd->id;
+
+	if (of_address_to_resource(np, 0, &res_nphys) != 0) {
+		nss_info_always("%px: nss%d: of_address_to_resource() fail for nphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	if (of_address_to_resource(np, 1, &res_vphys) != 0) {
+		nss_info_always("%px: nss%d: of_address_to_resource() fail for vphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	if (of_address_to_resource(np, 2, &res_qgic_phys) != 0) {
+		nss_info_always("%px: nss%d: of_address_to_resource() fail for qgic_phys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	/*
+	 * Save physical addresses
+	 */
+	npd->nphys = res_nphys.start;
+	npd->vphys = res_vphys.start;
+	npd->qgic_phys = res_qgic_phys.start;
+
+	npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys));
+	if (!npd->nmap) {
+		nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	nss_assert(npd->vphys);
+	npd->vmap = ioremap_cache(npd->vphys, resource_size(&res_vphys));
+	if (!npd->vmap) {
+		nss_info_always("%px: nss%d: ioremap() fail for vphys\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys));
+	if (!npd->qgic_map) {
+		nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id);
+		goto out;
+	}
+
+	/*
+	 * Clear TCM memory used by this core
+	 */
+	for (i = 0; i < resource_size(&res_vphys) ; i += 4) {
+		nss_write_32(npd->vmap, i, 0);
+		NSS_CORE_DMA_CACHE_MAINT((npd->vmap + i), 4, DMA_TO_DEVICE);
+	}
+	NSS_CORE_DSB();
+
+	/*
+	 * Get IRQ numbers
+	 */
+	for (i = 0 ; i < npd->num_irq; i++) {
+		npd->irq[i] = irq_of_parse_and_map(np, i);
+		if (!npd->irq[i]) {
+			nss_info_always("%px: nss%d: irq_of_parse_and_map() fail for irq %d\n", nss_ctx, nss_ctx->id, i);
+			goto out;
+		}
+	}
+
+	nss_hal_dt_parse_features(np, npd);
+
+	of_node_put(np);
+	return npd;
+
+out:
+	if (npd->nmap) {
+		iounmap(npd->nmap);
+	}
+
+	if (npd->vmap) {
+		iounmap(npd->vmap);
+	}
+
+	devm_kfree(&pdev->dev, npd);
+	of_node_put(np);
+	return NULL;
+}
+
+/*
+ * __nss_hal_core_reset()
+ */
+static int __nss_hal_core_reset(struct platform_device *nss_dev, void __iomem *map, uint32_t addr, uint32_t clk_src)
+{
+	uint32_t value;
+
+	/*
+	 * De-assert reset for first set
+	 */
+	value = nss_read_32(nss_misc_reset, 0x0);
+	value &= ~(NSS_CORE_GCC_RESET_1 << (nss_dev->id << 3));
+	nss_write_32(nss_misc_reset, 0x0, value);
+
+	/*
+	 * Minimum 10 - 20 cycles delay is required after
+	 * de-asserting UBI reset clamp
+	 */
+	usleep_range(10, 20);
+
+	/*
+	 * De-assert reset for second set
+	 */
+	value &= ~(NSS_CORE_GCC_RESET_2 << (nss_dev->id << 3));
+	nss_write_32(nss_misc_reset, 0x0, value);
+
+	/*
+	 * Apply ubi32 core reset
+	 */
+	nss_write_32(map, NSS_REGS_RESET_CTRL_OFFSET, 1);
+
+	/*
+	 * Program address configuration
+	 */
+	nss_write_32(map, NSS_REGS_CORE_AMC_OFFSET, 1);
+	nss_write_32(map, NSS_REGS_CORE_BAR_OFFSET, 0x3c000000);
+	nss_write_32(map, NSS_REGS_CORE_BOOT_ADDR_OFFSET, addr);
+
+	/*
+	 * C2C interrupts are level sensitive
+	 * Copy engine interrupts are level sensitive
+	 */
+	nss_write_32(map, NSS_REGS_CORE_INT_STAT2_TYPE_OFFSET, 0xFFFF);
+	nss_write_32(map, NSS_REGS_CORE_INT_STAT3_TYPE_OFFSET, 0xFF);
+
+	/*
+	 * Enable Instruction Fetch range checking between 0x4000 0000 to 0xBFFF FFFF.
+	 */
+	nss_write_32(map, NSS_REGS_CORE_IFETCH_RANGE_OFFSET, 0xBF004001);
+
+	/*
+	 * De-assert ubi32 core reset
+	 */
+	nss_write_32(map, NSS_REGS_RESET_CTRL_OFFSET, 0);
+
+	return 0;
+}
+
+/*
+ * __nss_hal_debug_enable()
+ *	Enable NSS debug
+ */
+static void __nss_hal_debug_enable(void)
+{
+
+}
+
+/*
+ * nss_hal_clock_set_and_enable()
+ */
+static int nss_hal_clock_set_and_enable(struct device *dev, const char *id, unsigned long rate)
+{
+	struct clk *nss_clk = NULL;
+	int err;
+
+	nss_clk = devm_clk_get(dev, id);
+	if (IS_ERR(nss_clk)) {
+		pr_err("%px: cannot get clock: %s\n", dev, id);
+		return -EFAULT;
+	}
+
+	if (rate) {
+		err = clk_set_rate(nss_clk, rate);
+		if (err) {
+			pr_err("%px: cannot set %s freq\n", dev, id);
+			return -EFAULT;
+		}
+	}
+
+	err = clk_prepare_enable(nss_clk);
+	if (err) {
+		pr_err("%px: cannot enable clock: %s\n", dev, id);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/*
+ * __nss_hal_common_reset
+ *	Do reset/clock configuration common to all cores
+ */
+static int __nss_hal_common_reset(struct platform_device *nss_dev)
+{
+	struct device_node *cmn = NULL;
+	struct resource res_nss_misc_reset;
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NOC_CLK, 461500000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_PTP_REF_CLK, 150000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CSR_CLK, 200000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CFG_CLK, 100000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_IMEM_CLK, 400000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_QOSGEN_REF_CLK, 19200000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_MEM_NOC_NSS_AXI_CLK, 461500000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_SNOC_CLK, 266600000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_TIMEOUT_REF_CLK, 4800000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CE_AXI_CLK, 200000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CE_APB_CLK, 200000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_CE_AXI_CLK, 200000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_CE_APB_CLK, 200000000)) {
+		return -EFAULT;
+	}
+
+	/*
+	 * Get reference to NSS common device node
+	 */
+	cmn = of_find_node_by_name(NULL, "nss-common");
+	if (!cmn) {
+		pr_err("%px: Unable to find nss-common node\n", nss_dev);
+		return -EFAULT;
+	}
+
+	if (of_address_to_resource(cmn, 0, &res_nss_misc_reset) != 0) {
+		pr_err("%px: of_address_to_resource() return error for nss_misc_reset\n", nss_dev);
+		of_node_put(cmn);
+		return -EFAULT;
+	}
+	of_node_put(cmn);
+
+	nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset));
+	if (!nss_misc_reset) {
+		pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev);
+		return -EFAULT;
+	}
+
+	nss_top_main.nss_hal_common_init_done = true;
+	nss_info("nss_hal_common_reset Done\n");
+	return 0;
+}
+
+/*
+ * __nss_hal_clock_configure()
+ */
+static int __nss_hal_clock_configure(struct nss_ctx_instance *nss_ctx, struct platform_device *nss_dev, struct nss_platform_data *npd)
+{
+	uint32_t i;
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_AHB_CLK, 200000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_AHB_CLK, 200000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_AXI_CLK, 461500000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_MPT_CLK, 25000000)) {
+		return -EFAULT;
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NC_AXI_CLK, 461500000)) {
+		return -EFAULT;
+	}
+
+	/*
+	 * For IPQ807x, any rate above 1497 is Turbo Voltage
+	 * Temporary set the voltage to turbo till we start scaling frequenices.
+	 * This is to ensure probing is safe and autoscaling will correct the voltage.
+	 */
+	if (!nss_ctx->id) {
+		npu_reg = devm_regulator_get(&nss_dev->dev, "npu");
+		if (IS_ERR(npu_reg)) {
+			return PTR_ERR(npu_reg);
+		}
+		if (regulator_enable(npu_reg)) {
+			return -EFAULT;
+		}
+		regulator_set_voltage(npu_reg, TURBO_VOLTAGE, TURBO_VOLTAGE);
+	}
+
+	/*
+	 * No entries, then just load default
+	 */
+	if ((nss_runtime_samples.freq_scale[NSS_FREQ_LOW_SCALE].frequency == 0) ||
+		(nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency == 0) ||
+		(nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency == 0)) {
+		nss_runtime_samples.freq_scale[NSS_FREQ_LOW_SCALE].frequency = NSS_FREQ_187;
+		nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency = NSS_FREQ_748;
+		nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency = NSS_FREQ_1497;
+		nss_info_always("Running default frequencies\n");
+	}
+
+	/*
+	 * Test frequency from dtsi, if fail, try to set default frequency.
+	 */
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency)) {
+		if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, NSS_FREQ_1497)) {
+			return -EFAULT;
+		}
+	}
+
+	/*
+	 * Setup ranges, test frequency, and display.
+	 */
+	for (i = 0; i < NSS_FREQ_MAX_SCALE; i++) {
+		if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_187) {
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_187_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_187_MAX;
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_748) {
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_748_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_748_MAX;
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1497) {
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_1497_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_1497_MAX;
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1689) {
+			nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_1689_MIN;
+			nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_1689_MAX;
+		} else {
+			nss_info_always("Frequency not found %d\n", nss_runtime_samples.freq_scale[i].frequency);
+			return -EFAULT;
+		}
+
+		/*
+		 * Test the frequency, if fail, then default to safe frequency and abort
+		 */
+		if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, nss_runtime_samples.freq_scale[i].frequency)) {
+			return -EFAULT;
+		}
+	}
+
+	nss_info_always("Supported Frequencies - ");
+	for (i = 0; i < NSS_FREQ_MAX_SCALE; i++) {
+		if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_187) {
+			nss_info_always("187.2 MHz ");
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_748) {
+			nss_info_always("748.8 MHz ");
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1497) {
+			nss_info_always("1.4976 GHz ");
+		} else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1689) {
+			nss_info_always("1.6896 GHz ");
+		} else {
+			nss_info_always("Error\nNo Table/Invalid Frequency Found\n");
+			return -EFAULT;
+		}
+	}
+	nss_info_always("\n");
+
+	/*
+	 * Set values only once for core0. Grab the proper clock.
+	 */
+	if (nss_ctx->id) {
+		nss_core1_clk = clk_get(&nss_dev->dev, NSS_CORE_CLK);
+	} else {
+		nss_core0_clk = clk_get(&nss_dev->dev, NSS_CORE_CLK);
+	}
+
+	if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency)) {
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/*
+ * __nss_hal_read_interrupt_cause()
+ */
+static void __nss_hal_read_interrupt_cause(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t *cause)
+{
+}
+
+/*
+ * __nss_hal_clear_interrupt_cause()
+ */
+static void __nss_hal_clear_interrupt_cause(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+}
+
+/*
+ * __nss_hal_disable_interrupt()
+ */
+static void __nss_hal_disable_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+}
+
+/*
+ * __nss_hal_enable_interrupt()
+ */
+static void __nss_hal_enable_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+}
+
+/*
+ * __nss_hal_send_interrupt()
+ */
+static void __nss_hal_send_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t type)
+{
+	/*
+	 * Check if core and type is Valid
+	 */
+	nss_assert(nss_ctx->id < nss_top_main.num_nss);
+	nss_assert(type < NSS_H2N_INTR_TYPE_MAX);
+
+	nss_write_32(nss_ctx->qgic_map, NSS_QGIC_IPC_REG_OFFSET, intr_cause[nss_ctx->id][type]);
+}
+
+/*
+ * __nss_hal_request_irq()
+ */
+static int __nss_hal_request_irq(struct nss_ctx_instance *nss_ctx, struct nss_platform_data *npd, int irq_num)
+{
+	struct int_ctx_instance *int_ctx = &nss_ctx->int_ctx[irq_num];
+	int err = -1, irq = npd->irq[irq_num];
+
+	irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS) {
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT);
+		int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS;
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_sos", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE) {
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT);
+		int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE;
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_queue", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED) {
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_TX_UNBLOCKED_PROCESSING_WEIGHT);
+		int_ctx->cause = NSS_N2H_INTR_TX_UNBLOCKED;
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss-tx-unblock", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0) {
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+		int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_0;
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue0", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1) {
+		int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_1;
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue1", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2) {
+		int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_2;
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue2", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3) {
+		int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_3;
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue3", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE) {
+		int_ctx->cause = NSS_N2H_INTR_COREDUMP_COMPLETE;
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_emergency, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_coredump_complete", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS) {
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT);
+		int_ctx->cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS;
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_paged_empty_buf_sos", int_ctx);
+	}
+
+	if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PROFILE_DMA) {
+		int_ctx->cause = NSS_N2H_INTR_PROFILE_DMA;
+		netif_napi_add(&nss_ctx->napi_ndev, &int_ctx->napi, nss_core_handle_napi_sdma, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+		err = request_irq(irq, nss_hal_handle_irq, 0, "nss_profile_dma", int_ctx);
+	}
+
+	if (err) {
+		return err;
+	}
+
+	int_ctx->irq = irq;
+	return 0;
+}
+
+/*
+ * __nss_hal_init_imem
+ */
+void __nss_hal_init_imem(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
+
+	mem_ctx->imem_head = NSS_IMEM_START + NSS_IMEM_SIZE * nss_ctx->id;
+	mem_ctx->imem_end = mem_ctx->imem_head + NSS_IMEM_SIZE;
+	mem_ctx->imem_tail = mem_ctx->imem_head;
+
+	nss_info("%px: IMEM init: head: 0x%x end: 0x%x tail: 0x%x\n", nss_ctx,
+			mem_ctx->imem_head, mem_ctx->imem_end, mem_ctx->imem_tail);
+}
+
+/*
+ * __nss_hal_init_utcm_shared
+ */
+bool __nss_hal_init_utcm_shared(struct nss_ctx_instance *nss_ctx, uint32_t *meminfo_start)
+{
+	/*
+	 * Nothing to be done as there are no TCM in ipq807x
+	 */
+	return true;
+}
+
+/*
+ * nss_hal_ipq807x_ops
+ */
+struct nss_hal_ops nss_hal_ipq807x_ops = {
+	.common_reset = __nss_hal_common_reset,
+	.core_reset = __nss_hal_core_reset,
+	.clock_configure = __nss_hal_clock_configure,
+	.firmware_load = nss_hal_firmware_load,
+	.debug_enable = __nss_hal_debug_enable,
+	.of_get_pdata = __nss_hal_of_get_pdata,
+	.request_irq = __nss_hal_request_irq,
+	.send_interrupt = __nss_hal_send_interrupt,
+	.enable_interrupt = __nss_hal_enable_interrupt,
+	.disable_interrupt = __nss_hal_disable_interrupt,
+	.clear_interrupt_cause = __nss_hal_clear_interrupt_cause,
+	.read_interrupt_cause = __nss_hal_read_interrupt_cause,
+	.init_imem = __nss_hal_init_imem,
+	.init_utcm_shared = __nss_hal_init_utcm_shared,
+};
diff --git a/qca-nss-drv/nss_hal/nss_hal.c b/qca-nss-drv/nss_hal/nss_hal.c
new file mode 100644
index 0000000..7e9a044
--- /dev/null
+++ b/qca-nss-drv/nss_hal/nss_hal.c
@@ -0,0 +1,829 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_hal.c
+ *	NSS HAL general APIs.
+ */
+
+#include <linux/err.h>
+#include <linux/version.h>
+#include <linux/firmware.h>
+#include <linux/of.h>
+#include <linux/irq.h>
+
+#include "nss_hal.h"
+#include "nss_arch.h"
+#include "nss_core.h"
+#include "nss_tx_rx_common.h"
+#include "nss_data_plane.h"
+#if (NSS_PM_SUPPORT == 1)
+#include "nss_pm.h"
+#endif
+#if (NSS_FABRIC_SCALING_SUPPORT == 1)
+#include <linux/fab_scaling.h>
+#endif
+
+/*
+ * Macros
+ */
+#define NSS_AP0_IMAGE "qca-nss0.bin"
+#define NSS_AP1_IMAGE "qca-nss1.bin"
+
+/*
+ * File local/Static variables/functions
+ */
+static const struct net_device_ops nss_netdev_ops;
+static const struct ethtool_ops nss_ethtool_ops;
+
+int nss_hal_firmware_load(struct nss_ctx_instance *nss_ctx, struct platform_device *nss_dev, struct nss_platform_data *npd)
+{
+	const struct firmware *nss_fw;
+	void __iomem *load_mem;
+	int rc;
+
+	if (nss_ctx->id == 0) {
+		rc = request_firmware(&nss_fw, NSS_AP0_IMAGE, &(nss_dev->dev));
+	} else if (nss_ctx->id == 1) {
+		rc = request_firmware(&nss_fw, NSS_AP1_IMAGE, &(nss_dev->dev));
+	} else {
+		nss_warning("%px: Invalid nss dev: %d\n", nss_ctx, nss_ctx->id);
+		return -EINVAL;
+	}
+
+	/*
+	 *  Check if the file read is successful
+	 */
+	if (rc) {
+		nss_info_always("%px: request_firmware failed with err code: %d", nss_ctx, rc);
+		return rc;
+	}
+
+
+	load_mem = ioremap_nocache(npd->load_addr, nss_fw->size);
+	if (!load_mem) {
+		nss_info_always("%px: ioremap_nocache failed: %x", nss_ctx, npd->load_addr);
+		release_firmware(nss_fw);
+		return rc;
+	}
+
+	nss_info_always("nss_driver - fw of size %d  bytes copied to load addr: %x, nss_id : %d\n", (int)nss_fw->size, npd->load_addr, nss_dev->id);
+	memcpy_toio(load_mem, nss_fw->data, nss_fw->size);
+	release_firmware(nss_fw);
+	iounmap(load_mem);
+	return 0;
+}
+
+/*
+ * nss_hal_dt_parse_features()
+ */
+void nss_hal_dt_parse_features(struct device_node *np, struct nss_platform_data *npd)
+{
+	/*
+	 * Read the features in
+	 */
+	npd->bridge_enabled = of_property_read_bool(np, "qcom,bridge-enabled");
+	npd->capwap_enabled = of_property_read_bool(np, "qcom,capwap-enabled");
+	npd->clmap_enabled = of_property_read_bool(np, "qcom,clmap-enabled");
+	npd->crypto_enabled = of_property_read_bool(np, "qcom,crypto-enabled");
+	npd->dtls_enabled = of_property_read_bool(np, "qcom,dtls-enabled");
+	npd->gre_enabled = of_property_read_bool(np, "qcom,gre-enabled");
+	npd->gre_redir_enabled = of_property_read_bool(np, "qcom,gre-redir-enabled");
+	npd->gre_tunnel_enabled = of_property_read_bool(np, "qcom,gre_tunnel_enabled");
+	npd->gre_redir_mark_enabled = of_property_read_bool(np, "qcom,gre-redir-mark-enabled");
+	npd->igs_enabled = of_property_read_bool(np, "qcom,igs-enabled");
+	npd->ipsec_enabled = of_property_read_bool(np, "qcom,ipsec-enabled");
+	npd->ipv4_enabled = of_property_read_bool(np, "qcom,ipv4-enabled");
+	npd->ipv4_reasm_enabled = of_property_read_bool(np, "qcom,ipv4-reasm-enabled");
+	npd->ipv6_enabled = of_property_read_bool(np, "qcom,ipv6-enabled");
+	npd->ipv6_reasm_enabled = of_property_read_bool(np, "qcom,ipv6-reasm-enabled");
+	npd->l2tpv2_enabled = of_property_read_bool(np, "qcom,l2tpv2-enabled");
+	npd->map_t_enabled = of_property_read_bool(np, "qcom,map-t-enabled");
+	npd->oam_enabled = of_property_read_bool(np, "qcom,oam-enabled");
+	npd->ppe_enabled = of_property_read_bool(np, "qcom,ppe-enabled");
+	npd->pppoe_enabled = of_property_read_bool(np, "qcom,pppoe-enabled");
+	npd->pptp_enabled = of_property_read_bool(np, "qcom,pptp-enabled");
+	npd->portid_enabled = of_property_read_bool(np, "qcom,portid-enabled");
+	npd->pvxlan_enabled = of_property_read_bool(np, "qcom,pvxlan-enabled");
+	npd->qvpn_enabled = of_property_read_bool(np, "qcom,qvpn-enabled");
+	npd->rmnet_rx_enabled = of_property_read_bool(np, "qcom,rmnet_rx-enabled");
+	npd->shaping_enabled = of_property_read_bool(np, "qcom,shaping-enabled");
+	npd->tls_enabled = of_property_read_bool(np, "qcom,tls-enabled");
+	npd->tstamp_enabled = of_property_read_bool(np, "qcom,tstamp-enabled");
+	npd->turbo_frequency = of_property_read_bool(np, "qcom,turbo-frequency");
+	npd->tun6rd_enabled = of_property_read_bool(np, "qcom,tun6rd-enabled");
+	npd->tunipip6_enabled = of_property_read_bool(np, "qcom,tunipip6-enabled");
+	npd->vlan_enabled = of_property_read_bool(np, "qcom,vlan-enabled");
+	npd->vxlan_enabled = of_property_read_bool(np, "qcom,vxlan-enabled");
+	npd->wlanredirect_enabled = of_property_read_bool(np, "qcom,wlanredirect-enabled");
+	npd->wifioffload_enabled = of_property_read_bool(np, "qcom,wlan-dataplane-offload-enabled");
+	npd->match_enabled = of_property_read_bool(np, "qcom,match-enabled");
+	npd->mirror_enabled = of_property_read_bool(np, "qcom,mirror-enabled");
+	npd->udp_st_enabled = of_property_read_bool(np, "qcom,udp-st-enabled");
+}
+/*
+ * nss_hal_clean_up_irq()
+ */
+static void nss_hal_clean_up_irq(struct int_ctx_instance *int_ctx)
+{
+	if (!int_ctx->irq) {
+		return;
+	}
+
+	/*
+	 * Wait here till the poll is complete.
+	 */
+	napi_disable(&int_ctx->napi);
+
+	/*
+	 * Interrupt can be raised here before free_irq() but as napi is
+	 * already disabled, it will be never sheduled from hard_irq
+	 * context.
+	 */
+	irq_clear_status_flags(int_ctx->irq, IRQ_DISABLE_UNLAZY);
+	free_irq(int_ctx->irq, int_ctx);
+	int_ctx->irq = 0;
+
+	netif_napi_del(&int_ctx->napi);
+}
+
+/*
+ * nss_hal_register_irq()
+ */
+static int nss_hal_register_irq(struct nss_ctx_instance *nss_ctx, struct nss_platform_data *npd,
+					struct net_device *netdev, int irq_num)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct int_ctx_instance *int_ctx = &nss_ctx->int_ctx[irq_num];
+	int err = 0;
+
+	/*
+	 * request for IRQs
+	 */
+	int_ctx->nss_ctx = nss_ctx;
+	err = nss_top->hal_ops->request_irq(nss_ctx, npd, irq_num);
+	if (err) {
+		nss_warning("%px: IRQ request for queue %d failed", nss_ctx, irq_num);
+		return err;
+	}
+
+	/*
+	 * Register NAPI for NSS core interrupt
+	 */
+	napi_enable(&int_ctx->napi);
+	return 0;
+}
+
+/*
+ * nss_hal_probe()
+ *	HLOS device probe callback
+ */
+int nss_hal_probe(struct platform_device *nss_dev)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = NULL;
+	struct nss_platform_data *npd = NULL;
+	int i, err = 0;
+#ifdef NSS_DRV_TSTAMP_ENABLE
+	struct net_device *tstamp_ndev = NULL;
+#endif
+
+	if (nss_top_main.nss_hal_common_init_done == false) {
+		err = nss_top->hal_ops->common_reset(nss_dev);
+		if (err) {
+			nss_info_always("NSS HAL common init failed\n");
+			return -EFAULT;
+		}
+	}
+
+#if (NSS_DT_SUPPORT == 1)
+	if (!nss_dev->dev.of_node) {
+		pr_err("nss-driver: Device tree not available\n");
+		return -ENODEV;
+	}
+
+	npd = nss_top->hal_ops->of_get_pdata(nss_dev);
+	if (!npd) {
+		return -EFAULT;
+	}
+
+	nss_ctx = &nss_top->nss[npd->id];
+	nss_ctx->id = npd->id;
+	nss_dev->id = nss_ctx->id;
+#else
+	npd = (struct nss_platform_data *) nss_dev->dev.platform_data;
+	nss_ctx = &nss_top->nss[nss_dev->id];
+	nss_ctx->id = nss_dev->id;
+#endif
+	nss_ctx->num_irq = npd->num_irq;
+	nss_ctx->nss_top = nss_top;
+
+	/*
+	 * dev is required for dma map/unmap
+	 */
+	nss_ctx->dev = &nss_dev->dev;
+
+	nss_info("%px: NSS_DEV_ID %s\n", nss_ctx, dev_name(&nss_dev->dev));
+
+	/*
+	 * Do firmware load from nss-drv if required
+	 */
+	err = nss_top->hal_ops->firmware_load(nss_ctx, nss_dev, npd);
+	if (err) {
+		nss_info_always("%px: firmware load from driver failed\n", nss_ctx);
+		goto err_init;
+	}
+
+	err = nss_top->hal_ops->clock_configure(nss_ctx, nss_dev, npd);
+	if (err) {
+		nss_info_always("%px: clock configure failed\n", nss_ctx);
+		goto err_init;
+	}
+
+	/*
+	 * Get load address of NSS firmware
+	 */
+	nss_info("%px: Setting NSS%d Firmware load address to %x\n", nss_ctx, nss_ctx->id, npd->load_addr);
+	nss_top->nss[nss_ctx->id].load = npd->load_addr;
+
+	/*
+	 * Get virtual and physical memory addresses for nss logical/hardware address maps
+	 */
+
+	/*
+	 * Virtual address of CSM space
+	 */
+	nss_ctx->nmap = npd->nmap;
+
+	/*
+	 * Physical address of CSM space
+	 */
+	nss_ctx->nphys = npd->nphys;
+	nss_assert(nss_ctx->nphys);
+
+	/*
+	 * Virtual address of logical registers space
+	 */
+	nss_ctx->vmap = npd->vmap;
+
+	/*
+	 * Virtual address of QGIC interrupt space
+	 */
+	nss_ctx->qgic_map = npd->qgic_map;
+
+	/*
+	 * Physical address of logical registers space
+	 */
+	nss_ctx->vphys = npd->vphys;
+	nss_info("%d:ctx=%px, vphys=%x, vmap=%px, nphys=%x, nmap=%px", nss_ctx->id,
+			nss_ctx, nss_ctx->vphys, nss_ctx->vmap, nss_ctx->nphys, nss_ctx->nmap);
+
+	if (!nss_meminfo_init(nss_ctx)) {
+		nss_info_always("%px: meminfo init failed\n", nss_ctx);
+		err = -EFAULT;
+		goto err_init;
+	}
+
+	/*
+	 * Initialize the dummy netdevice.
+	 */
+	init_dummy_netdev(&nss_ctx->napi_ndev);
+
+	for (i = 0; i < npd->num_irq; i++) {
+		err = nss_hal_register_irq(nss_ctx, npd, &nss_ctx->napi_ndev, i);
+		if (err) {
+			goto err_register_irq;
+		}
+	}
+
+#ifdef NSS_DRV_TSTAMP_ENABLE
+	/*
+	 * Allocate tstamp net_device and register the net_device
+	 */
+	if (npd->tstamp_enabled == NSS_FEATURE_ENABLED) {
+		tstamp_ndev = nss_tstamp_register_netdev();
+		if (!tstamp_ndev) {
+			nss_warning("%px: Unable to register the TSTAMP net_device", nss_ctx);
+			npd->tstamp_enabled = NSS_FEATURE_NOT_ENABLED;
+		}
+		nss_top->tstamp_handler_id = nss_dev->id;
+		nss_tstamp_register_handler(tstamp_ndev);
+	}
+#endif
+	/*
+	 * Initialize the handlers for all interfaces associated with core
+	 */
+	nss_core_init_handlers(nss_ctx);
+
+	/*
+	 * Features that will always be enabled on both cores
+	 */
+	nss_dynamic_interface_register_handler(nss_ctx);
+	nss_n2h_register_handler(nss_ctx);
+	nss_project_register_handler(nss_ctx);
+#ifdef NSS_DRV_QRFS_ENABLE
+	nss_qrfs_register_handler(nss_ctx);
+#endif
+
+#ifdef NSS_DRV_C2C_ENABLE
+	nss_c2c_tx_register_handler(nss_ctx);
+	nss_c2c_rx_register_handler(nss_ctx);
+#endif
+	nss_unaligned_register_handler(nss_ctx);
+
+	/*
+	 * Check functionalities are supported by this NSS core
+	 */
+#ifdef NSS_DRV_SHAPER_ENABLE
+	if (npd->shaping_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->shaping_handler_id = nss_dev->id;
+		nss_info("%d: NSS shaping is enabled", nss_dev->id);
+	}
+#endif
+
+	if (npd->ipv4_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->ipv4_handler_id = nss_dev->id;
+		nss_ipv4_register_handler();
+
+#ifdef NSS_DRV_EDMA_ENABLE
+		nss_top->edma_handler_id = nss_dev->id;
+		nss_edma_register_handler();
+#endif
+		nss_eth_rx_register_handler(nss_ctx);
+#ifdef NSS_DRV_LAG_ENABLE
+		nss_lag_register_handler();
+#endif
+#ifdef NSS_DRV_TRUSTSEC_ENABLE
+		nss_top->trustsec_tx_handler_id = nss_dev->id;
+		nss_trustsec_tx_register_handler();
+#endif
+
+		nss_top->virt_if_handler_id = nss_dev->id;
+
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_N2H] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_H2N] = nss_dev->id;
+	}
+
+#ifdef NSS_DRV_CAPWAP_ENABLE
+	if (npd->capwap_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->capwap_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_OUTER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_CAPWAP_HOST_INNER] = nss_dev->id;
+	}
+#endif
+
+#ifdef NSS_DRV_IPV4_REASM_ENABLE
+	if (npd->ipv4_reasm_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->ipv4_reasm_handler_id = nss_dev->id;
+		nss_ipv4_reasm_register_handler();
+	}
+#endif
+
+#ifdef NSS_DRV_IPV6_ENABLE
+	if (npd->ipv6_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->ipv6_handler_id = nss_dev->id;
+		nss_ipv6_register_handler();
+	}
+
+#ifdef NSS_DRV_IPV6_REASM_ENABLE
+	if (npd->ipv6_reasm_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->ipv6_reasm_handler_id = nss_dev->id;
+		nss_ipv6_reasm_register_handler();
+	}
+#endif
+#endif
+
+#ifdef NSS_DRV_CRYPTO_ENABLE
+	/*
+	 * TODO: when Crypto is moved to Core-1 it needs to
+	 * flush based on nss_top->crypto_enabled
+	 */
+	if (npd->crypto_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->crypto_handler_id = nss_dev->id;
+#if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT) || defined(NSS_HAL_IPQ50XX_SUPPORT)
+		nss_crypto_cmn_register_handler();
+#else
+		nss_top->crypto_enabled = 1;
+		nss_crypto_register_handler();
+#endif
+
+#if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT)
+		nss_top->dma_handler_id = nss_dev->id;
+		nss_dma_register_handler();
+#endif
+	}
+#endif
+
+#ifdef NSS_DRV_IPSEC_ENABLE
+	if (npd->ipsec_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->ipsec_handler_id = nss_dev->id;
+#if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT) || defined(NSS_HAL_IPQ50XX_SUPPORT)
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_INNER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_OUTER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_MDATA_INNER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_MDATA_OUTER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_REDIRECT] = nss_dev->id;
+		nss_ipsec_cmn_register_handler();
+#else
+		nss_ipsec_register_handler();
+#endif
+	}
+#endif
+
+	if (npd->wlanredirect_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->wlan_handler_id = nss_dev->id;
+	}
+
+#ifdef NSS_DRV_TUN6RD_ENABLE
+	if (npd->tun6rd_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->tun6rd_handler_id = nss_dev->id;
+	}
+#endif
+
+#ifdef NSS_DRV_PPTP_ENABLE
+	if (npd->pptp_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->pptp_handler_id = nss_dev->id;
+		nss_pptp_register_handler();
+	}
+#endif
+
+	if (npd->pppoe_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->pppoe_handler_id = nss_dev->id;
+		nss_pppoe_register_handler();
+	}
+
+#ifdef NSS_DRV_PPE_ENABLE
+	if (npd->ppe_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->ppe_handler_id = nss_dev->id;
+		nss_ppe_register_handler();
+		nss_ppe_vp_register_handler();
+	}
+#endif
+
+#ifdef NSS_DRV_L2TP_ENABLE
+	if (npd->l2tpv2_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->l2tpv2_handler_id = nss_dev->id;
+		nss_l2tpv2_register_handler();
+	}
+#endif
+
+#ifdef NSS_DRV_DTLS_ENABLE
+	if (npd->dtls_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->dtls_handler_id = nss_dev->id;
+#if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT) || defined(NSS_HAL_IPQ50XX_SUPPORT)
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_INNER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_OUTER] = nss_dev->id;
+		nss_dtls_cmn_register_handler();
+#else
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_DTLS] = nss_dev->id;
+		nss_dtls_register_handler();
+#endif
+	}
+#endif
+
+#ifdef NSS_DRV_MAPT_ENABLE
+	if (npd->map_t_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->map_t_handler_id = nss_dev->id;
+		nss_map_t_register_handler();
+	}
+#endif
+
+#ifdef NSS_DRV_TUNIPIP6_ENABLE
+	if (npd->tunipip6_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->tunipip6_handler_id = nss_dev->id;
+		nss_tunipip6_register_handler();
+	}
+#endif
+
+#ifdef NSS_DRV_GRE_ENABLE
+	if (npd->gre_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->gre_handler_id = nss_dev->id;
+		nss_gre_register_handler();
+	}
+#endif
+
+#ifdef NSS_DRV_GRE_REDIR_ENABLE
+	if (npd->gre_redir_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->gre_redir_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_HOST_INNER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_WIFI_OFFL_INNER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_SJACK_INNER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR_OUTER] = nss_dev->id;
+		nss_gre_redir_register_handler();
+		nss_gre_redir_lag_us_register_handler();
+		nss_gre_redir_lag_ds_register_handler();
+#ifdef NSS_DRV_SJACK_ENABLE
+		nss_top->sjack_handler_id = nss_dev->id;
+		nss_sjack_register_handler();
+#endif
+
+	}
+
+	if (npd->gre_redir_mark_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->gre_redir_mark_handler_id = nss_dev->id;
+		nss_gre_redir_mark_register_handler();
+	}
+#endif
+
+#ifdef NSS_DRV_GRE_TUNNEL_ENABLE
+	if (npd->gre_tunnel_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->gre_tunnel_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INNER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_OUTER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INLINE_INNER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INLINE_OUTER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_GRE_TUNNEL_INNER_EXCEPTION] = nss_dev->id;
+	}
+#endif
+
+#ifdef NSS_DRV_PORTID_ENABLE
+	if (npd->portid_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->portid_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_PORTID] = nss_dev->id;
+		nss_portid_register_handler();
+	}
+#endif
+
+	if (npd->wifioffload_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->wifi_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VAP] = nss_dev->id;
+		nss_wifi_register_handler();
+		nss_wifili_register_handler();
+#ifdef NSS_DRV_WIFI_EXT_VDEV_ENABLE
+		nss_wifi_ext_vdev_register_handler();
+#endif
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_WIFILI_INTERNAL] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_WIFILI_EXTERNAL0] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_WIFILI_EXTERNAL1] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_WIFI_EXT_VDEV_WDS] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_WIFI_EXT_VDEV_VLAN] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER] = nss_dev->id;
+
+		/*
+		 * Register wifi mac database when offload enabled
+		 */
+		nss_top->wmdb_handler_id = nss_dev->id;
+		nss_wifi_mac_db_register_handler();
+
+		/*
+		 * Initialize wifili thread scheme database
+		 */
+		nss_wifili_thread_scheme_db_init(nss_dev->id);
+	}
+
+#ifdef NSS_DRV_OAM_ENABLE
+	if (npd->oam_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->oam_handler_id = nss_dev->id;
+		nss_oam_register_handler();
+	}
+#endif
+
+#ifdef NSS_DRV_BRIDGE_ENABLE
+	if (npd->bridge_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->bridge_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_BRIDGE] = nss_dev->id;
+		nss_bridge_init();
+	}
+#endif
+
+	if (npd->vlan_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->vlan_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VLAN] = nss_dev->id;
+		nss_vlan_register_handler();
+	}
+
+#ifdef NSS_DRV_QVPN_ENABLE
+#if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT)
+	if (npd->qvpn_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->qvpn_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_QVPN_OUTER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_QVPN_INNER] = nss_dev->id;
+		nss_qvpn_register_handler();
+	}
+#endif
+#endif
+
+#ifdef NSS_DRV_PVXLAN_ENABLE
+	if (npd->pvxlan_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->pvxlan_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_PVXLAN_HOST_INNER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_PVXLAN_OUTER] = nss_dev->id;
+	}
+#endif
+
+#ifdef NSS_DRV_RMNET_ENABLE
+	if (npd->rmnet_rx_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->rmnet_rx_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_N2H] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_H2N] = nss_dev->id;
+	}
+#endif
+
+#ifdef NSS_DRV_IGS_ENABLE
+	if (npd->igs_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->igs_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_IGS] = nss_dev->id;
+		nss_info("%d: NSS IGS is enabled", nss_dev->id);
+	}
+#endif
+
+#ifdef NSS_DRV_CLMAP_ENABLE
+	if (npd->clmap_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->clmap_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_US] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_CLMAP_DS] = nss_dev->id;
+	}
+#endif
+
+#ifdef NSS_DRV_VXLAN_ENABLE
+	if (npd->vxlan_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->vxlan_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_INNER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_OUTER] = nss_dev->id;
+		nss_vxlan_init();
+	}
+#endif
+
+#ifdef NSS_DRV_MATCH_ENABLE
+	if (npd->match_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->match_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_MATCH] = nss_dev->id;
+		nss_match_init();
+	}
+#endif
+
+#ifdef NSS_DRV_TLS_ENABLE
+#if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT)
+	if (npd->tls_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->tls_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_TLS_INNER] = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_TLS_OUTER] = nss_dev->id;
+		nss_tls_register_handler();
+	}
+#endif
+#endif
+
+#ifdef NSS_DRV_MIRROR_ENABLE
+	if (npd->mirror_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->mirror_handler_id = nss_dev->id;
+		nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_MIRROR] = nss_dev->id;
+		nss_mirror_register_handler();
+		nss_info("%d: NSS mirror is enabled", nss_dev->id);
+	}
+
+#endif
+
+#ifdef NSS_DRV_UDP_ST_ENABLE
+	if (npd->udp_st_enabled == NSS_FEATURE_ENABLED) {
+		nss_top->udp_st_handler_id = nss_dev->id;
+		nss_udp_st_register_handler(nss_ctx);
+	}
+#endif
+
+	if (nss_ctx->id == 0) {
+#if (NSS_FREQ_SCALE_SUPPORT == 1)
+		nss_freq_register_handler();
+
+		/*
+		 * Init CPU usage detail
+		 * Note: As of now, ubi cpu usage is supported only for core0
+		 */
+		nss_freq_init_cpu_usage();
+#endif
+
+		nss_lso_rx_register_handler(nss_ctx);
+	}
+
+	nss_top->frequency_handler_id = nss_dev->id;
+
+	/*
+	 * Initialize decongestion callbacks to NULL
+	 */
+	for (i = 0; i < NSS_MAX_CLIENTS; i++) {
+		nss_ctx->queue_decongestion_callback[i] = 0;
+		nss_ctx->queue_decongestion_ctx[i] = 0;
+	}
+
+	spin_lock_init(&(nss_ctx->decongest_cb_lock));
+	nss_ctx->magic = NSS_CTX_MAGIC;
+
+	nss_info("%px: Reseting NSS core %d now", nss_ctx, nss_ctx->id);
+
+	/*
+	 * Enable clocks and bring NSS core out of reset
+	 */
+	err = nss_top->hal_ops->core_reset(nss_dev, nss_ctx->nmap, nss_ctx->load, nss_top->clk_src);
+	if (err) {
+		goto err_register_irq;
+	}
+
+	/*
+	 * Initialize max buffer size for NSS core
+	 */
+	nss_ctx->max_buf_size = NSS_NBUF_PAYLOAD_SIZE;
+
+	/*
+	 * Initialize S/G status pointers to NULL
+	 */
+	for (i = 0; i < NSS_N2H_DESC_RING_NUM; i++) {
+		nss_ctx->n2h_desc_ring[i].head = NULL;
+		nss_ctx->n2h_desc_ring[i].tail = NULL;
+		nss_ctx->n2h_desc_ring[i].jumbo_start = NULL;
+	}
+
+	/*
+	 * Enable interrupts for NSS core.
+	 */
+	for (i = 0; i < npd->num_irq; i++) {
+		nss_hal_enable_interrupt(nss_ctx, nss_ctx->int_ctx[i].shift_factor, NSS_HAL_SUPPORTED_INTERRUPTS);
+	}
+
+	nss_info("%px: All resources initialized and nss core%d has been brought out of reset", nss_ctx, nss_dev->id);
+	goto out;
+
+err_register_irq:
+	for (i = 0; i < npd->num_irq; i++) {
+		nss_hal_clean_up_irq(&nss_ctx->int_ctx[i]);
+	}
+
+err_init:
+	if (nss_dev->dev.of_node) {
+		if (npd->nmap) {
+			iounmap(npd->nmap);
+		}
+
+		if (npd->vmap) {
+			iounmap(npd->vmap);
+		}
+	}
+
+out:
+	if (nss_dev->dev.of_node) {
+		devm_kfree(&nss_dev->dev, npd);
+	}
+	return err;
+}
+
+/*
+ * nss_hal_remove()
+ *	HLOS device remove callback
+ */
+int nss_hal_remove(struct platform_device *nss_dev)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[nss_dev->id];
+	int i;
+
+	/*
+	 * Clean up debugfs
+	 */
+	nss_stats_clean();
+
+	/*
+	 * Clear up the resources associated with the interrupt
+	 */
+	for (i = 0; i < nss_ctx->num_irq; i++) {
+		nss_hal_disable_interrupt(nss_ctx, nss_ctx->int_ctx[i].shift_factor,
+					  NSS_HAL_SUPPORTED_INTERRUPTS);
+		nss_hal_clean_up_irq(&nss_ctx->int_ctx[i]);
+	}
+
+	/*
+	 * nss-drv is exiting, unregister and restore host data plane
+	 */
+	nss_top->data_plane_ops->data_plane_unregister();
+
+#if (NSS_FABRIC_SCALING_SUPPORT == 1)
+	fab_scaling_unregister(nss_core0_clk);
+#endif
+
+	if (nss_dev->dev.of_node) {
+		if (nss_ctx->nmap) {
+			iounmap(nss_ctx->nmap);
+			nss_ctx->nmap = 0;
+		}
+
+		if (nss_ctx->vmap) {
+			iounmap(nss_ctx->vmap);
+			nss_ctx->vmap = 0;
+		}
+	}
+
+	nss_info("%px: All resources freed for nss core%d", nss_ctx, nss_dev->id);
+	return 0;
+}
diff --git a/qca-nss-drv/nss_hlos_if.h b/qca-nss-drv/nss_hlos_if.h
new file mode 100644
index 0000000..fdcf21b
--- /dev/null
+++ b/qca-nss-drv/nss_hlos_if.h
@@ -0,0 +1,381 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_hlos_if.h
+ *	NSS to HLOS interface definitions.
+ */
+
+#ifndef __NSS_HLOS_IF_H
+#define __NSS_HLOS_IF_H
+
+#define NSS_MIN_NUM_CONN			256		/* MIN Connection shared between IPv4 and IPv6 */
+#define NSS_FW_DEFAULT_NUM_CONN			1024		/* Firmware default number of connections for IPv4 and IPv6 */
+#define NSS_NUM_CONN_QUANTA_MASK		(1024 - 1)	/* Quanta of number of connections 1024 */
+#define NSS_CONN_CFG_TIMEOUT			6000		/* 6 sec timeout for connection cfg message */
+
+/*
+ * The following definitions sets the maximum number of connections
+ * based on the type of memory profile that the system is operating with
+ */
+#if defined (NSS_MEM_PROFILE_LOW)
+#define NSS_DEFAULT_NUM_CONN			512		/* Default number of connections for IPv4 and IPv6 each, for low memory profile */
+#if defined (NSS_DRV_IPV6_ENABLE)
+#define NSS_MAX_TOTAL_NUM_CONN_IPV4_IPV6	1024		/* MAX Connection shared between IPv4 and IPv6 for low memory profile */
+#else
+#define NSS_MAX_TOTAL_NUM_CONN_IPV4_IPV6	512		/* MAX Connection for IPv4 for low memory profile */
+#endif
+#define NSS_LOW_MEM_EMPTY_POOL_BUF_SZ		4096		/* Default empty buffer pool size for low profile */
+#elif defined (NSS_MEM_PROFILE_MEDIUM)
+#define NSS_DEFAULT_NUM_CONN			2048		/* Default number of connections for IPv4 and IPv6 each, for medium memory profile */
+#define NSS_MAX_TOTAL_NUM_CONN_IPV4_IPV6	4096		/* MAX Connection shared between IPv4 and IPv6 for medium memory profile */
+#else
+#define NSS_DEFAULT_NUM_CONN			4096		/* Default number of connections for each IPv4 and IPv6 */
+#define NSS_MAX_TOTAL_NUM_CONN_IPV4_IPV6	8192		/* MAX Connection shared between IPv4 and IPv6 */
+#endif
+
+#if defined(NSS_SKB_FIXED_SIZE_2K) && !defined(__LP64__)
+#define NSS_EMPTY_BUFFER_SIZE			1792		/* Default buffer size for reduced memory profiles. */
+#define NSS_FIXED_BUFFER_SIZE					/* For low memory profiles, maximum buffer size/MTU is fixed */
+#else
+#define NSS_EMPTY_BUFFER_SIZE			1984		/* Default buffer size for regular memory profiles. */
+#undef NSS_FIXED_BUFFER_SIZE
+#endif
+
+enum {
+	NSS_SUCCESS = 0,
+	NSS_FAILURE = 1,
+};
+
+/*
+ * Request/Response types
+ */
+enum nss_if_metadata_types {
+	NSS_TX_METADATA_TYPE_INTERFACE_OPEN,
+	NSS_TX_METADATA_TYPE_INTERFACE_CLOSE,
+	NSS_TX_METADATA_TYPE_INTERFACE_LINK_STATE_NOTIFY,
+	NSS_TX_METADATA_TYPE_INTERFACE_MTU_CHANGE,
+	NSS_TX_METADATA_TYPE_INTERFACE_MAC_ADDR_SET,
+	NSS_TX_METADATA_TYPE_INTERFACE_MSS_SET,
+	NSS_RX_METADATA_TYPE_INTERFACE_STATS_SYNC,
+	NSS_METADATA_TYPE_INTERFACE_MAX,
+};
+
+/*
+ * General statistics messages
+ */
+
+/*
+ * IPv4 reasm node stats
+ */
+struct nss_ipv4_reasm_stats_sync {
+	struct nss_cmn_node_stats node_stats;
+					/* Common node stats for ipv4_reasm */
+	uint32_t ipv4_reasm_evictions;
+	uint32_t ipv4_reasm_alloc_fails;
+	uint32_t ipv4_reasm_timeouts;
+};
+
+/*
+ * IPv4 reasm message types
+ */
+enum nss_ipv4_reasm_message_types {
+	NSS_IPV4_REASM_STATS_SYNC_MSG,
+};
+
+/*
+ * IPv4 reassembly message structure
+ */
+struct nss_ipv4_reasm_msg {
+	struct nss_cmn_msg cm;
+	union {
+		struct nss_ipv4_reasm_stats_sync stats_sync;
+	} msg;
+};
+
+/*
+ * IPv6 reasm node stats
+ */
+struct nss_ipv6_reasm_stats_sync {
+	struct nss_cmn_node_stats node_stats;
+					/* Common node stats for ipv6_reasm */
+	uint32_t ipv6_reasm_alloc_fails;
+	uint32_t ipv6_reasm_timeouts;
+	uint32_t ipv6_reasm_discards;
+};
+
+/*
+ * IPv6 reasm message types
+ */
+enum nss_ipv6_reasm_message_types {
+	NSS_IPV6_REASM_STATS_SYNC_MSG,
+};
+
+/*
+ * IPv6 reassembly message structure
+ */
+struct nss_ipv6_reasm_msg {
+	struct nss_cmn_msg cm;
+	union {
+		struct nss_ipv6_reasm_stats_sync stats_sync;
+	} msg;
+};
+
+/*
+ * Generic interface messages
+ */
+enum nss_generic_metadata_types {
+	NSS_TX_METADATA_TYPE_GENERIC_IF_PARAMS,
+	NSS_METADATA_TYPE_GENERIC_IF_MAX
+};
+
+/*
+ * Interface params command
+ */
+struct nss_generic_if_params {
+	uint8_t buf[1];		/* Buffer */
+};
+
+/*
+ * Message structure to send/receive ipsec messages
+ */
+struct nss_generic_msg {
+	struct nss_cmn_msg cm;			/* Message Header */
+	union {
+		struct nss_generic_if_params rule;	/* Message: generic rule */
+	} msg;
+};
+
+/*
+ * NSS frequency scaling messages
+ */
+enum nss_freq_stats_metadata_types {
+	COREFREQ_METADATA_TYPE_ERROR,
+	COREFREQ_METADATA_TYPE_RX_FREQ_CHANGE,
+	COREFREQ_METADATA_TYPE_TX_FREQ_ACK,
+	COREFREQ_METADATA_TYPE_TX_CORE_STATS,
+	COREFREQ_METADATA_TYPE_MAX,
+};
+
+ /*
+ * Types of TX metadata -- legacy code needs to be removed
+ */
+enum nss_tx_metadata_types {
+	NSS_TX_METADATA_TYPE_LEGACY_0,
+	NSS_TX_METADATA_TYPE_NSS_FREQ_CHANGE,
+	NSS_TX_METADATA_TYPE_SHAPER_CONFIGURE,
+};
+
+/*
+ * The NSS freq start or stop strcture
+ */
+struct nss_freq_msg {
+	/* Request */
+	uint32_t frequency;
+	uint32_t start_or_end;
+	uint32_t stats_enable;
+
+	/* Response */
+	uint32_t freq_current;
+	int32_t ack;
+};
+
+/*
+ * NSS core stats
+ */
+struct nss_core_stats {
+	uint32_t inst_cnt_total;
+};
+
+/*
+ * Message structure to send/receive NSS Freq commands
+ */
+struct nss_corefreq_msg {
+	struct nss_cmn_msg cm;			/* Message Header */
+	union {
+		struct nss_freq_msg nfc;	/* Message: freq stats */
+		struct nss_core_stats ncs;	/* Message: NSS stats sync */
+	} msg;
+};
+
+/*
+ * H2N Buffer Types
+ */
+#define H2N_BUFFER_EMPTY			0
+#define H2N_PAGED_BUFFER_EMPTY			1
+#define H2N_BUFFER_PACKET			2
+#define H2N_BUFFER_CTRL				4
+#define H2N_BUFFER_NATIVE_WIFI			8
+#define H2N_BUFFER_SHAPER_BOUNCE_INTERFACE	9
+#define H2N_BUFFER_SHAPER_BOUNCE_BRIDGE		10
+#define H2N_BUFFER_RATE_TEST			14
+#define H2N_BUFFER_MAX				16
+
+/*
+ * H2N Bit Flag Definitions
+ */
+#define H2N_BIT_FLAG_GEN_IPV4_IP_CHECKSUM		0x0001
+#define H2N_BIT_FLAG_GEN_IP_TRANSPORT_CHECKSUM		0x0002
+#define H2N_BIT_FLAG_FIRST_SEGMENT			0x0004
+#define H2N_BIT_FLAG_LAST_SEGMENT			0x0008
+
+#define H2N_BIT_FLAG_GEN_IP_TRANSPORT_CHECKSUM_NONE	0x0010
+#define H2N_BIT_FLAG_TX_TS_REQUIRED			0x0040
+#define H2N_BIT_FLAG_DISCARD				0x0080
+#define H2N_BIT_FLAG_SEGMENTATION_ENABLE		0x0100
+
+#define H2N_BIT_FLAG_VIRTUAL_BUFFER			0x2000
+#define H2N_BIT_FLAG_BUFFER_REUSABLE			0x8000
+
+/*
+ * HLOS to NSS descriptor structure.
+ */
+struct h2n_descriptor {
+	uint32_t interface_num;	/* Interface number to which the buffer is to be sent (where appropriate) */
+	uint32_t buffer;	/* Physical buffer address. This is the address of the start of the usable buffer being provided by the HLOS */
+	uint32_t qos_tag;	/* QoS tag information of the buffer (where appropriate) */
+	uint16_t buffer_len;	/* Length of the buffer (in bytes) */
+	uint16_t payload_len;	/* Length of the active payload of the buffer (in bytes) */
+	uint16_t mss;		/* MSS to be used with TSO/UFO */
+	uint16_t payload_offs;	/* Offset from the start of the buffer to the start of the payload (in bytes) */
+	uint16_t bit_flags;	/* Bit flags associated with the buffer */
+	uint8_t buffer_type;	/* Type of buffer */
+	uint8_t reserved;	/* Reserved for future use */
+	nss_ptr_t opaque;	/* 32 or 64-bit value provided by the HLOS to associate with the buffer. The cookie has no meaning to the NSS */
+#ifndef __LP64__
+	uint32_t padding;	/* Pad to fit 64bits, do not reuse */
+#endif
+};
+
+/*
+ * N2H Buffer Types
+ */
+#define N2H_BUFFER_EMPTY			1
+#define N2H_BUFFER_PACKET			3
+#define N2H_BUFFER_COMMAND_RESP			5
+#define N2H_BUFFER_STATUS			6
+#define N2H_BUFFER_CRYPTO_RESP			8
+#define N2H_BUFFER_PACKET_VIRTUAL		10
+#define N2H_BUFFER_SHAPER_BOUNCED_INTERFACE	11
+#define N2H_BUFFER_SHAPER_BOUNCED_BRIDGE	12
+#define N2H_BUFFER_PACKET_EXT			13
+#define N2H_BUFFER_RATE_TEST			14
+#define N2H_BUFFER_MAX				16
+
+/*
+ * Command Response Types
+ */
+#define N2H_COMMAND_RESP_OK			0
+#define N2H_COMMAND_RESP_BUFFER_TOO_SMALL	1
+#define N2H_COMMAND_RESP_BUFFER_NOT_WRITEABLE	2
+#define N2H_COMMAND_RESP_UNSUPPORTED_COMMAND	3
+#define N2H_COMMAND_RESP_INVALID_PARAMETERS	4
+#define N2H_COMMAND_RESP_INACTIVE_SUBSYSTEM	5
+
+/*
+ * N2H Bit Flag Definitions
+ */
+#define N2H_BIT_FLAG_IPV4_IP_CHECKSUM_VALID		0x0001
+#define N2H_BIT_FLAG_IP_TRANSPORT_CHECKSUM_VALID	0x0002
+#define N2H_BIT_FLAG_FIRST_SEGMENT			0x0004
+#define N2H_BIT_FLAG_LAST_SEGMENT			0x0008
+#define N2H_BIT_FLAG_INGRESS_SHAPED			0x0010
+
+/*
+ * NSS to HLOS descriptor structure
+ */
+struct n2h_descriptor {
+	uint32_t interface_num;	/* Interface number to which the buffer is to be sent (where appropriate) */
+	uint32_t buffer;	/* Physical buffer address. This is the address of the start of the usable buffer being provided by the HLOS */
+	uint16_t buffer_len;	/* Length of the buffer (in bytes) */
+	uint16_t payload_len;	/* Length of the active payload of the buffer (in bytes) */
+	uint16_t payload_offs;	/* Offset from the start of the buffer to the start of the payload (in bytes) */
+	uint16_t bit_flags;	/* Bit flags associated with the buffer */
+	uint8_t buffer_type;	/* Type of buffer */
+	uint8_t response_type;	/* Response type if the buffer is a command response */
+	uint8_t pri;		/* Packet priority */
+	uint8_t service_code;	/* Service code */
+	uint32_t reserved;	/* Reserved for future use */
+	nss_ptr_t opaque;	/* 32 or 64-bit value provided by the HLOS to associate with the buffer. The cookie has no meaning to the NSS */
+#ifndef __LP64__
+	uint32_t padding;	/* Pad to fit 64 bits, do not reuse */
+#endif
+};
+
+/*
+ * Device Memory Map Definitions
+ */
+#define DEV_MAGIC		0x4e52522e
+#define DEV_INTERFACE_VERSION	1
+#define DEV_DESCRIPTORS		256 /* Do we need it here? */
+
+/**
+ * H2N descriptor METADATA
+ */
+struct h2n_desc_if_meta {
+	uint32_t desc_addr;
+	uint16_t size;
+	uint16_t padding;
+};
+
+/**
+ * H2N descriptor ring
+ */
+struct h2n_desc_if_instance {
+	struct h2n_descriptor *desc;
+	uint16_t size;			/* Size in entries of the H2N0 descriptor ring */
+};
+
+/**
+ * N2H descriptor METADATA
+ */
+struct n2h_desc_if_meta {
+	uint32_t desc_addr;
+	uint16_t size;
+	uint16_t padding;
+};
+
+/**
+ * N2H descriptor ring
+ */
+struct n2h_desc_if_instance {
+	struct n2h_descriptor *desc;
+	uint16_t size;			/* Size in entries of the H2N0 descriptor ring */
+};
+
+/**
+ * NSS virtual interface map
+ */
+struct nss_if_mem_map {
+	struct h2n_desc_if_meta h2n_desc_if[16];/* Base address of H2N0 descriptor ring */
+	struct n2h_desc_if_meta n2h_desc_if[15];/* Base address of N2H0 descriptor ring */
+	uint32_t magic;				/* Magic value used to identify NSS implementations (must be 0x4e52522e) */
+	uint16_t if_version;			/* Interface version number (must be 1 for this version) */
+	uint8_t h2n_rings;			/* Number of descriptor rings in the H2N direction */
+	uint8_t n2h_rings;			/* Number of descriptor rings in the N2H direction */
+	uint32_t h2n_nss_index[16];
+			/* Index number for the next descriptor that will be read by the NSS in the H2N0 descriptor ring (NSS owned) */
+	volatile uint32_t n2h_nss_index[15];
+			/* Index number for the next descriptor that will be written by the NSS in the N2H0 descriptor ring (NSS owned) */
+	uint8_t num_phys_ports;
+	uint8_t reserved1[3];	/* Reserved for future use */
+	uint32_t h2n_hlos_index[16];
+			/* Index number for the next descriptor that will be written by the HLOS in the H2N0 descriptor ring (HLOS owned) */
+	volatile uint32_t n2h_hlos_index[15];
+			/* Index number for the next descriptor that will be read by the HLOS in the N2H0 descriptor ring (HLOS owned) */
+	uint32_t reserved;	/* Reserved for future use */
+};
+#endif /* __NSS_HLOS_IF_H */
diff --git a/qca-nss-drv/nss_if.c b/qca-nss-drv/nss_if.c
new file mode 100644
index 0000000..0c370b1
--- /dev/null
+++ b/qca-nss-drv/nss_if.c
@@ -0,0 +1,354 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2016, 2018-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_if.c
+ *	NSS base interfaces
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_if_log.h"
+
+/*
+ * nss_if_pvt
+ *	NSS private structure to handle the completion of NSS -> HLOS messages.
+ */
+static struct nss_if_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+} nss_if;
+
+static bool nss_if_sem_init_done;
+
+/*
+ * nss_if_callback
+ *	Callback to handle the completion of NSS ->HLOS messages.
+ */
+static void nss_if_callback(void *app_data, struct nss_if_msg *nim)
+{
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("nss_if Error response %d\n", nim->cm.response);
+		nss_if.response = NSS_TX_FAILURE;
+		complete(&nss_if.complete);
+		return;
+	}
+
+	nss_if.response = NSS_TX_SUCCESS;
+	complete(&nss_if.complete);
+}
+
+/*
+ * nss_if_msg_sync()
+ *	Send a message to an interface and wait for the response.
+ */
+nss_tx_status_t nss_if_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_if_msg *nim)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	if (!nss_if_sem_init_done) {
+		sema_init(&nss_if.sem, 1);
+		init_completion(&nss_if.complete);
+		nss_if_sem_init_done = 1;
+	}
+
+	down(&nss_if.sem);
+
+	status = nss_if_tx_msg(nss_ctx, nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_if_msg failed\n", nss_ctx);
+		up(&nss_if.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&nss_if.complete, msecs_to_jiffies(NSS_IF_TX_TIMEOUT));
+
+	if (!ret) {
+		nss_warning("%px: nss_if tx failed due to timeout\n", nss_ctx);
+		nss_if.response = NSS_TX_FAILURE;
+	}
+
+	status = nss_if.response;
+	up(&nss_if.sem);
+
+	return status;
+}
+EXPORT_SYMBOL(nss_if_msg_sync);
+
+/*
+ * nss_if_msg_handler()
+ *	Handle NSS -> HLOS messages for base class interfaces
+ */
+void nss_if_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm,
+		__attribute__((unused))void *app_data)
+{
+	struct nss_if_msg *nim = (struct nss_if_msg *)ncm;
+	nss_if_msg_callback_t cb;
+
+	/*
+	 * We only support base class messages with this interface
+	 */
+	if (ncm->type > NSS_IF_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (!nss_is_dynamic_interface(ncm->interface) &&
+		!((ncm->interface >= NSS_PHYSICAL_IF_START) && (ncm->interface < NSS_VIRTUAL_IF_START))) {
+		nss_warning("%px: interface %d not in physical or dynamic if range\n", nss_ctx, ncm->interface);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_if_msg)) {
+		nss_warning("%px: message length too big: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Trace messages.
+	 */
+	nss_if_log_rx_msg(nim);
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * Callback
+	 */
+	cb = (nss_if_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, nim);
+}
+
+/*
+ * nss_if_tx_buf()
+ *	Send packet to interface owned by NSS
+ */
+nss_tx_status_t nss_if_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, uint32_t if_num)
+{
+	nss_trace("%px: If Tx packet, id:%d, data=%px", nss_ctx, if_num, os_buf->data);
+
+	if (!nss_is_dynamic_interface(if_num) &&
+		!((if_num >= NSS_PHYSICAL_IF_START) && (if_num < NSS_VIRTUAL_IF_START))) {
+		nss_warning("%px: interface %d not in physical or dynamic if range\n", nss_ctx, if_num);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	return nss_core_send_packet(nss_ctx, os_buf, if_num, H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+
+/*
+ * nss_if_tx_msg()
+ *	Transmit a message to the specific interface on this core.
+ */
+nss_tx_status_t nss_if_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_if_msg *nim)
+{
+	struct nss_cmn_msg *ncm = &nim->cm;
+	struct net_device *dev;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (ncm->type >= NSS_IF_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Sanity check the message for valid interfaces.
+	 */
+	if (ncm->interface < NSS_PHYSICAL_IF_START ||
+		ncm->interface >= NSS_MAX_NET_INTERFACES ) {
+		nss_warning("%px: Tx request for invalid interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_if_log_tx_msg(nim);
+
+	dev = nss_ctx->subsys_dp_register[ncm->interface].ndev;
+	if (!dev) {
+		nss_warning("%px: Unregister interface %d: no context", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	return nss_core_send_cmd(nss_ctx, nim, sizeof(*nim), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ * nss_if_register()
+ *	Primary registration for receiving data and msgs from an interface.
+ */
+struct nss_ctx_instance *nss_if_register(uint32_t if_num,
+				nss_if_rx_callback_t rx_callback,
+				nss_if_msg_callback_t msg_callback,
+				struct net_device *if_ctx)
+{
+	return NULL;
+}
+
+/*
+ * nss_if_unregister()
+ *	Unregisteer the callback for this interface
+ */
+void nss_if_unregister(uint32_t if_num)
+{
+}
+
+/*
+ * nss_if_reset_nexthop()
+ *	De-configures the nexthop for an interface
+ */
+nss_tx_status_t nss_if_reset_nexthop(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_if_msg nim;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	nss_trace("Resetting Nexthop. nss_ctx: %px ifnum: %u", nss_ctx, if_num);
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_IF_RESET_NEXTHOP, 0, nss_if_callback, NULL);
+
+	return nss_if_msg_sync(nss_ctx, &nim);
+}
+EXPORT_SYMBOL(nss_if_reset_nexthop);
+
+/*
+ * nss_if_set_nexthop()
+ *	Configures the nexthop for an interface
+ */
+nss_tx_status_t nss_if_set_nexthop(struct nss_ctx_instance *nss_ctx, uint32_t if_num, uint32_t nexthop)
+{
+	struct nss_if_msg nim;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (nexthop >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("%px: Invalid nexthop interface number: %d", nss_ctx, nexthop);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	nss_trace("%px: NSS If nexthop will be set to %d, id:%d\n", nss_ctx, nexthop, if_num);
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_IF_SET_NEXTHOP,
+				sizeof(struct nss_if_set_nexthop), nss_if_callback, NULL);
+
+	nim.msg.set_nexthop.nexthop = nexthop;
+
+	return nss_if_msg_sync(nss_ctx, &nim);
+}
+EXPORT_SYMBOL(nss_if_set_nexthop);
+
+/*
+ * nss_if_change_mtu()
+ *	Change the MTU of the interface.
+ */
+nss_tx_status_t nss_if_change_mtu(struct nss_ctx_instance *nss_ctx, nss_if_num_t if_num, uint16_t mtu)
+{
+	struct nss_if_msg nim;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	nss_trace("%px: NSS If MTU will be changed to %u, of NSS if num: %u\n", nss_ctx, mtu, if_num);
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_IF_MTU_CHANGE,
+				sizeof(struct nss_if_mtu_change), nss_if_callback, NULL);
+
+	nim.msg.mtu_change.min_buf_size = mtu;
+
+	return nss_if_msg_sync(nss_ctx, &nim);
+}
+EXPORT_SYMBOL(nss_if_change_mtu);
+
+/*
+ * nss_if_change_mac_addr()
+ *	Change the MAC address of the interface.
+ */
+nss_tx_status_t nss_if_change_mac_addr(struct nss_ctx_instance *nss_ctx, nss_if_num_t if_num, uint8_t *mac_addr)
+{
+	struct nss_if_msg nim;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	nss_trace("%px: NSS If MAC address will be changed to %s, of NSS if num: %u\n", nss_ctx, mac_addr, if_num);
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_IF_MAC_ADDR_SET,
+				sizeof(struct nss_if_mac_address_set), nss_if_callback, NULL);
+
+	memcpy(nim.msg.mac_address_set.mac_addr, mac_addr, ETH_ALEN);
+
+	return nss_if_msg_sync(nss_ctx, &nim);
+}
+EXPORT_SYMBOL(nss_if_change_mac_addr);
+
+/*
+ * nss_if_vsi_unassign()
+ *	API to send VSI detach message to NSS FW.
+ */
+nss_tx_status_t nss_if_vsi_unassign(struct nss_ctx_instance *nss_ctx, nss_if_num_t if_num, uint32_t vsi)
+{
+	struct nss_if_msg nim;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	nss_trace("%px: VSI to be unassigned is %u\n", nss_ctx, vsi);
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_IF_VSI_UNASSIGN,
+				sizeof(struct nss_if_vsi_unassign), nss_if_callback, NULL);
+
+	nim.msg.vsi_unassign.vsi = vsi;
+
+	return nss_if_msg_sync(nss_ctx, &nim);
+}
+EXPORT_SYMBOL(nss_if_vsi_unassign);
+
+/*
+ * nss_if_vsi_assign()
+ *	API to send VSI attach message to NSS FW.
+ */
+nss_tx_status_t nss_if_vsi_assign(struct nss_ctx_instance *nss_ctx, nss_if_num_t if_num, uint32_t vsi)
+{
+	struct nss_if_msg nim;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	nss_trace("%px: VSI to be assigned is %u\n", nss_ctx, vsi);
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_IF_VSI_ASSIGN,
+				sizeof(struct nss_if_vsi_assign), nss_if_callback, NULL);
+
+	nim.msg.vsi_assign.vsi = vsi;
+
+	return nss_if_msg_sync(nss_ctx, &nim);
+}
+EXPORT_SYMBOL(nss_if_vsi_assign);
+
+EXPORT_SYMBOL(nss_if_tx_msg);
+EXPORT_SYMBOL(nss_if_register);
+EXPORT_SYMBOL(nss_if_unregister);
diff --git a/qca-nss-drv/nss_if_log.c b/qca-nss-drv/nss_if_log.c
new file mode 100644
index 0000000..a551a42
--- /dev/null
+++ b/qca-nss-drv/nss_if_log.c
@@ -0,0 +1,429 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_if_log.c
+ *	NSS Interface logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_if_log_message_types_str
+ *	NSS interface rule message strings
+ */
+static int8_t *nss_if_log_message_types_str[NSS_IF_MAX_MSG_TYPES] __maybe_unused = {
+	"NSS interface Open message",
+	"NSS interface close message",
+	"NSS interface link state notify message",
+	"NSS interface MTU change message",
+	"NSS interface MAC address set message",
+	"NSS interface stats message",
+	"NSS interface ishaper assign message",
+	"NSS interface bshaper assign message",
+	"NSS interface ishaper unassign message",
+	"NSS interface bshaper unassign message",
+	"NSS interface ishaper config message",
+	"NSS interface bshaper config message",
+	"NSS interface pause on off message",
+	"NSS interface VSI assign message",
+	"NSS interface VSI unassign message",
+	"NSS interface set next hop message",
+	"NSS interface set IGS node message",
+	"NSS interface clear IGS node message",
+	"NSS interface reset next hop message",
+};
+
+/*
+ * nss_if_log_error_response_types_str
+ *	Strings for error types for NSS interface messages
+ */
+static int8_t *nss_if_log_error_response_types_str[NSS_IF_ERROR_TYPE_MAX] __maybe_unused = {
+	"No Ishapers",
+	"No Bshapers",
+	"No Ishaper",
+	"No Bshaper",
+	"No Old Ishaper",
+	"No Old Bshaper",
+	"Ishaper config failed",
+	"Bshaper config failed",
+	"Unknown error",
+	"Interface open error",
+	"Interface invalid MTU error",
+	"Invalid MAC address error",
+	"VSI no match error",
+	"VSI reassign error",
+	"Invalid VSI error",
+	"Max error",
+};
+
+/*
+ * nss_if_log_rule_open()
+ *	Log NSS open interface message.
+ */
+static void nss_if_log_rule_open(struct nss_if_msg *nim)
+{
+	struct nss_if_open *niom __maybe_unused = &nim->msg.open;
+	nss_trace("%px: NSS open interface message \n"
+		"tx_desc_ring: %X\n"
+		"rx_desc_ring: %X\n"
+		"rx_forward_if: %u\n"
+		"alignment_mode: %u\n",
+		nim,
+		niom->tx_desc_ring,
+		niom->rx_desc_ring,
+		niom->rx_forward_if,
+		niom->alignment_mode);
+}
+
+/*
+ * nss_if_log_rule_close()
+ *	Log NSS close interface message.
+ */
+static void nss_if_log_rule_close(struct nss_if_msg *nim)
+{
+	nss_trace("%px: NSS close interface message \n", nim);
+}
+
+/*
+ * nss_if_log_rule_link_state_notify()
+ *	Log NSS interface link state notify message.
+ */
+static void nss_if_log_rule_link_state_notify(struct nss_if_msg *nim)
+{
+	struct nss_if_link_state_notify *nilstm __maybe_unused = &nim->msg.link_state_notify;
+	nss_trace("%px: NSS interface link state notify interface message \n"
+		"state: %u\n",
+		nim,
+		nilstm->state);
+}
+
+/*
+ * nss_if_log_rule_mtu_change()
+ *	Log NSS interface MTU change message.
+ */
+static void nss_if_log_rule_mtu_change(struct nss_if_msg *nim)
+{
+	struct nss_if_mtu_change *nimcm __maybe_unused = &nim->msg.mtu_change;
+	nss_trace("%px: NSS interface MTU change message \n"
+		"min_buf_size: %u\n",
+		nim,
+		nimcm->min_buf_size);
+}
+
+/*
+ * nss_if_log_rule_mac_addr_set()
+ *	Log NSS interface MAC address set message.
+ */
+static void nss_if_log_rule_mac_addr_set(struct nss_if_msg *nim)
+{
+	struct nss_if_mac_address_set *nimasm __maybe_unused = &nim->msg.mac_address_set;
+	nss_trace("%px: NSS interface MAC address set message \n"
+		"MAC address: %X:%X:%X:%X:%X:%X\n",
+		nim,
+		nimasm->mac_addr[0], nimasm->mac_addr[1], nimasm->mac_addr[2],
+		nimasm->mac_addr[3], nimasm->mac_addr[4], nimasm->mac_addr[5]);
+}
+
+/*
+ * nss_if_log_rule_stats()
+ *	Log NSS interface stats message.
+ */
+static void nss_if_log_rule_stats(struct nss_if_msg *nim)
+{
+	uint16_t i;
+	struct nss_cmn_node_stats *nism __maybe_unused = &nim->msg.stats;
+
+	nss_trace("%px: NSS interface stats message \n"
+		"rx_packets: %u\n"
+		"rx_bytes: %u\n"
+		"tx_packets: %u\n"
+		"tx_bytes: %u\n",
+		nim,
+		nism->rx_packets,
+		nism->rx_bytes,
+		nism->tx_packets,
+		nism->tx_bytes);
+
+	for(i=0; i < NSS_MAX_NUM_PRI; i++)
+	{
+		nss_trace("rx_dropped[%u]: %u\n", i, nism->rx_dropped[i]);
+	}
+}
+
+/*
+ * nss_if_log_rule_shaper_assign()
+ *	Log NSS interface shaper assignment message.
+ */
+static void nss_if_log_rule_shaper_assign(struct nss_if_msg *nim)
+{
+	struct nss_if_shaper_assign *shaper_assign_msg __maybe_unused = &nim->msg.shaper_assign;
+	nss_trace("%px: NSS interface shaper assign message \n"
+		"shaper_id: %u\n"
+		"new_shaper_id: %u\n",
+		nim,
+		shaper_assign_msg->shaper_id,
+		shaper_assign_msg->new_shaper_id);
+}
+
+/*
+ * nss_if_log_rule_shaper_unassign()
+ *	Log NSS interface shaper unassignment message.
+ */
+static void nss_if_log_rule_shaper_unassign(struct nss_if_msg *nim)
+{
+	struct nss_if_shaper_unassign *shaper_unassign_msg __maybe_unused = &nim->msg.shaper_unassign;
+	nss_trace("%px: NSS interface shaper unassign message \n"
+		"shaper_id: %u\n",
+		nim,
+		shaper_unassign_msg->shaper_id);
+}
+
+/*
+ * nss_if_log_rule_shaper_config()
+ *	Log NSS interface shaper configuration message.
+ */
+static void nss_if_log_rule_shaper_config(struct nss_if_msg *nim)
+{
+	struct nss_if_shaper_configure *shaper_configure_msg __maybe_unused = &nim->msg.shaper_configure;
+	nss_trace("%px: NSS interface shaper configuration message \n"
+		"request_type: %u\n"
+		"response_type: %u\n",
+		nim,
+		shaper_configure_msg->config.request_type,
+		shaper_configure_msg->config.response_type);
+}
+
+/*
+ * nss_if_log_rule_pause_on_off()
+ *	Log NSS interface pause on off message.
+ */
+static void nss_if_log_rule_pause_on_off(struct nss_if_msg *nim)
+{
+	struct nss_if_pause_on_off *pause_on_off_msg __maybe_unused = &nim->msg.pause_on_off;
+	nss_trace("%px: NSS interface pause ON/OFF message \n"
+		"pause_on: %u\n",
+		nim,
+		pause_on_off_msg->pause_on);
+}
+
+/*
+ * nss_if_log_rule_vsi_assign()
+ *	Log NSS interface VSI assignment message.
+ */
+static void nss_if_log_rule_vsi_assign(struct nss_if_msg *nim)
+{
+	struct nss_if_vsi_assign *vsi_assign_msg __maybe_unused = &nim->msg.vsi_assign;
+	nss_trace("%px: NSS interface VSI assignment message \n"
+		"VSI: %u\n",
+		nim,
+		vsi_assign_msg->vsi);
+}
+
+/*
+ * nss_if_log_rule_vsi_unassign()
+ *	Log NSS interface VSI unassignment message.
+ */
+static void nss_if_log_rule_vsi_unassign(struct nss_if_msg *nim)
+{
+	struct nss_if_vsi_unassign *vsi_unassign_msg __maybe_unused = &nim->msg.vsi_unassign;
+	nss_trace("%px: NSS interface VSI unassignment message \n"
+		"VSI: %u\n",
+		nim,
+		vsi_unassign_msg->vsi);
+}
+
+/*
+ * nss_if_log_rule_set_nexthop()
+ *	Log NSS interface set nexthop message.
+ */
+static void nss_if_log_rule_set_nexthop(struct nss_if_msg *nim)
+{
+	struct nss_if_set_nexthop *nisn __maybe_unused = &nim->msg.set_nexthop;
+	nss_trace("%px: NSS interface set nethop message \n"
+		"Nexthop: %u\n",
+		nim,
+		nisn->nexthop);
+}
+
+/*
+ * nss_if_log_rule_set_igs_node()
+ *	Log NSS interface set IGS node message.
+ */
+static void nss_if_log_rule_set_igs_node(struct nss_if_msg *nim)
+{
+	struct nss_if_igs_config *igs_config_msg __maybe_unused = &nim->msg.config_igs;
+	nss_trace("%px: NSS interface set IGS node message \n"
+		"igs_num: %d\n",
+		nim,
+		igs_config_msg->igs_num);
+}
+
+/*
+ * nss_if_log_rule_clear_igs_node()
+ *	Log NSS interface clear IGS node message.
+ */
+static void nss_if_log_rule_clear_igs_node(struct nss_if_msg *nim)
+{
+	struct nss_if_igs_config *igs_config_msg __maybe_unused = &nim->msg.config_igs;
+	nss_trace("%px: NSS interface clear IGS node message \n"
+		"igs_num: %d\n",
+		nim,
+		igs_config_msg->igs_num);
+}
+
+/*
+ * nss_if_log_rule_reset_nexthop()
+ *	Log NSS interface reset nexthop message.
+ */
+static void nss_if_log_rule_reset_nexthop(struct nss_if_msg *nim)
+{
+	nss_trace("%px: NSS interface reset nexthop message \n", nim);
+}
+
+/*
+ * nss_if_log_verbose()
+ *	Log message contents.
+ */
+static void nss_if_log_verbose(struct nss_if_msg *nim)
+{
+	nss_trace("NSS interface number: %u\n", nim->cm.interface);
+
+	switch (nim->cm.type) {
+	case NSS_IF_OPEN:
+		nss_if_log_rule_open(nim);
+		break;
+
+	case NSS_IF_CLOSE:
+		nss_if_log_rule_close(nim);
+		break;
+
+	case NSS_IF_LINK_STATE_NOTIFY:
+		nss_if_log_rule_link_state_notify(nim);
+		break;
+
+	case NSS_IF_MTU_CHANGE:
+		nss_if_log_rule_mtu_change(nim);
+		break;
+
+	case NSS_IF_MAC_ADDR_SET:
+		nss_if_log_rule_mac_addr_set(nim);
+		break;
+
+	case NSS_IF_STATS:
+		nss_if_log_rule_stats(nim);
+		break;
+
+	case NSS_IF_ISHAPER_ASSIGN:
+	case NSS_IF_BSHAPER_ASSIGN:
+		nss_if_log_rule_shaper_assign(nim);
+		break;
+
+	case NSS_IF_ISHAPER_UNASSIGN:
+	case NSS_IF_BSHAPER_UNASSIGN:
+		nss_if_log_rule_shaper_unassign(nim);
+		break;
+
+	case NSS_IF_ISHAPER_CONFIG:
+	case NSS_IF_BSHAPER_CONFIG:
+		nss_if_log_rule_shaper_config(nim);
+		break;
+
+	case NSS_IF_PAUSE_ON_OFF:
+		nss_if_log_rule_pause_on_off(nim);
+		break;
+
+	case NSS_IF_VSI_ASSIGN:
+		nss_if_log_rule_vsi_assign(nim);
+		break;
+
+	case NSS_IF_VSI_UNASSIGN:
+		nss_if_log_rule_vsi_unassign(nim);
+		break;
+
+	case NSS_IF_SET_NEXTHOP:
+		nss_if_log_rule_set_nexthop(nim);
+		break;
+
+	case NSS_IF_SET_IGS_NODE:
+		nss_if_log_rule_set_igs_node(nim);
+		break;
+
+	case NSS_IF_CLEAR_IGS_NODE:
+		nss_if_log_rule_clear_igs_node(nim);
+		break;
+
+	case NSS_IF_RESET_NEXTHOP:
+		nss_if_log_rule_reset_nexthop(nim);
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", nim);
+		break;
+	}
+}
+
+/*
+ * nss_if_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_if_log_rx_msg(struct nss_if_msg *nim)
+{
+	if (nim->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_info("%px: Invalid response\n", nim);
+		return;
+	}
+
+	if (nim->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nim->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nim, nim->cm.type,
+			nss_if_log_message_types_str[nim->cm.type],
+			nim->cm.response, nss_cmn_response_str[nim->cm.response]);
+			goto verbose;
+	}
+
+	if (nim->cm.error >= NSS_IF_ERROR_TYPE_MAX) {
+		nss_info("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+		nim, nim->cm.type, nss_if_log_message_types_str[nim->cm.type],
+			nim->cm.response, nss_cmn_response_str[nim->cm.response],
+			nim->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		nim, nim->cm.type, nss_if_log_message_types_str[nim->cm.type],
+		nim->cm.response, nss_cmn_response_str[nim->cm.response],
+		nim->cm.error, nss_if_log_error_response_types_str[nim->cm.error]);
+
+verbose:
+	nss_if_log_verbose(nim);
+}
+
+/*
+ * nss_if_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_if_log_tx_msg(struct nss_if_msg *nim)
+{
+	if (nim->cm.type >= NSS_IF_MAX_MSG_TYPES) {
+		nss_info("%px: Invalid message type\n", nim);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nim, nim->cm.type, nss_if_log_message_types_str[nim->cm.type]);
+	nss_if_log_verbose(nim);
+}
diff --git a/qca-nss-drv/nss_if_log.h b/qca-nss-drv/nss_if_log.h
new file mode 100644
index 0000000..0f2a7d2
--- /dev/null
+++ b/qca-nss-drv/nss_if_log.h
@@ -0,0 +1,40 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_IF_LOG_H
+#define __NSS_IF_LOG_H
+
+/*
+ * nss_if_log.h
+ *	NSS Interface header file.
+ */
+
+/*
+ * nss_if_log_tx_msg
+ *	Logs an NSS interface message that is sent to the NSS firmware.
+ */
+void nss_if_log_tx_msg(struct nss_if_msg *nim);
+
+/*
+ * nss_if_log_rx_msg
+ *	Logs an NSS interface message that is received from the NSS firmware.
+ */
+void nss_if_log_rx_msg(struct nss_if_msg *nim);
+
+
+#endif /* __NSS_IF_LOG_H */
diff --git a/qca-nss-drv/nss_igs.c b/qca-nss-drv/nss_igs.c
new file mode 100644
index 0000000..8153a46
--- /dev/null
+++ b/qca-nss-drv/nss_igs.c
@@ -0,0 +1,207 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_igs_stats.h"
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+#ifdef CONFIG_NET_CLS_ACT
+#include <linux/tc_act/tc_nss_mirred.h>
+#endif
+#endif
+
+static struct module *nss_igs_module;
+
+/*
+ * nss_igs_verify_if_num()
+ *	Verify interface number passed to us.
+ */
+bool nss_igs_verify_if_num(uint32_t if_num)
+{
+	enum nss_dynamic_interface_type if_type;
+
+	if_type = nss_dynamic_interface_get_type(nss_igs_get_context(), if_num);
+
+	if (if_type == NSS_DYNAMIC_INTERFACE_TYPE_IGS) {
+		return true;
+	}
+	return false;
+}
+EXPORT_SYMBOL(nss_igs_verify_if_num);
+
+/*
+ * nss_igs_handler()
+ *	Handle NSS -> HLOS messages for igs device
+ */
+static void nss_igs_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm,
+		 void *app_data)
+{
+	void *ctx;
+	nss_igs_msg_callback_t cb;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	BUG_ON(!nss_igs_verify_if_num(ncm->interface));
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_IGS_MSG_MAX) {
+		nss_warning("%px: received invalid message %d for IGS interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_igs_msg)) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	switch (ncm->type) {
+	case NSS_IGS_MSG_SYNC_STATS:
+		/*
+		 * Debug stats embedded in stats msg.
+		 */
+		nss_igs_stats_sync(nss_ctx, ncm, ncm->interface);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)app_data;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_igs_msg_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	/*
+	 * call igs callback
+	 */
+	if (!cb) {
+		nss_warning("%px: No callback for igs interface %d",
+			    nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb(ctx, ncm);
+}
+
+/*
+ * nss_igs_unregister_if()
+ *	Un-registers IGS interface from the NSS firmware.
+ */
+void nss_igs_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.igs_handler_id];
+	uint32_t status;
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_igs_verify_if_num(if_num));
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+	status = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to unregister handler for interface %d with NSS core\n", nss_ctx, if_num);
+	}
+
+	nss_igs_stats_reset(if_num);
+}
+EXPORT_SYMBOL(nss_igs_unregister_if);
+
+/*
+ * nss_igs_register_if()
+ *	Registers the IGS interface with NSS FW.
+ */
+struct nss_ctx_instance *nss_igs_register_if(uint32_t if_num, uint32_t type,
+		 nss_igs_msg_callback_t event_callback, struct net_device *netdev,
+		 uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.igs_handler_id];
+	uint32_t status;
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_igs_verify_if_num(if_num));
+
+	nss_core_register_handler(nss_ctx, if_num, nss_igs_handler, netdev);
+	status = nss_core_register_msg_handler(nss_ctx, if_num, event_callback);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_core_unregister_handler(nss_ctx, if_num);
+		nss_warning("%px: Not able to register handler for interface %d with NSS core\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, NULL, 0, netdev, netdev, features);
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num, type);
+
+	nss_igs_stats_dentry_create();
+	nss_igs_stats_init(if_num, netdev);
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_igs_register_if);
+
+/*
+ * nss_igs_get_context()
+ *	Get the IGS context.
+ */
+struct nss_ctx_instance *nss_igs_get_context()
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.igs_handler_id];
+}
+EXPORT_SYMBOL(nss_igs_get_context);
+
+#ifdef CONFIG_NET_CLS_ACT
+/*
+ * nss_igs_module_save()
+ *	Save the ingress shaping module reference.
+ */
+void nss_igs_module_save(struct tc_action_ops *act, struct module *module)
+{
+	nss_assert(act);
+	nss_assert(act->type == TCA_ACT_MIRRED_NSS);
+
+	nss_igs_module = module;
+}
+EXPORT_SYMBOL(nss_igs_module_save);
+#endif
+
+/*
+ * nss_igs_module_get()
+ *	Get the ingress shaping module reference.
+ */
+bool nss_igs_module_get()
+{
+	nss_assert(nss_igs_module);
+	return try_module_get(nss_igs_module);
+}
+EXPORT_SYMBOL(nss_igs_module_get);
+
+/*
+ * nss_igs_module_put()
+ *	Release the ingress shaping module reference.
+ */
+void nss_igs_module_put()
+{
+	nss_assert(nss_igs_module);
+	module_put(nss_igs_module);
+}
+EXPORT_SYMBOL(nss_igs_module_put);
diff --git a/qca-nss-drv/nss_igs_stats.c b/qca-nss-drv/nss_igs_stats.c
new file mode 100644
index 0000000..a6b511a
--- /dev/null
+++ b/qca-nss-drv/nss_igs_stats.c
@@ -0,0 +1,307 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_igs_stats.h"
+
+/*
+ * nss_igs_stats
+ *	IGS debug statistics.
+ */
+enum nss_igs_stats {
+	NSS_IGS_STATS_TX_DROP,
+	NSS_IGS_STATS_SHAPER_DROP,
+	NSS_IGS_STATS_IPV4_PARSE_FAIL,
+	NSS_IGS_STATS_IPV4_UNKNOWN_GRE_TYPE,
+	NSS_IGS_STATS_IPV4_UNKNOWN_L4,
+	NSS_IGS_STATS_IPV4_NO_CME,
+	NSS_IGS_STATS_IPV4_FRAG_INITIAL,
+	NSS_IGS_STATS_IPV4_FRAG_NON_INITIAL,
+	NSS_IGS_STATS_IPV4_MALFORMED_UDP,
+	NSS_IGS_STATS_IPV4_MALFORMED_TCP,
+	NSS_IGS_STATS_IPV4_MALFORMED_UDPL,
+	NSS_IGS_STATS_IPV4_MALFORMED_GRE,
+	NSS_IGS_STATS_IPV6_PARSE_FAIL,
+	NSS_IGS_STATS_IPV6_UNKNOWN_L4,
+	NSS_IGS_STATS_IPV6_NO_CME,
+	NSS_IGS_STATS_IPV6_FRAG_INITIAL,
+	NSS_IGS_STATS_IPV6_FRAG_NON_INITIAL,
+	NSS_IGS_STATS_IPV6_MALFORMED_UDP,
+	NSS_IGS_STATS_IPV6_MALFORMED_TCP,
+	NSS_IGS_STATS_IPV6_MALFORMED_UDPL,
+	NSS_IGS_STATS_IPV6_MALFORMED_FRAG,
+	NSS_IGS_STATS_EVENT_NO_SI,
+	NSS_IGS_STATS_ETH_PARSE_FAIL,
+	NSS_IGS_STATS_ETH_UNKNOWN_TYPE,
+	NSS_IGS_STATS_PPPOE_NON_IP,
+	NSS_IGS_STATS_PPPOE_MALFORMED,
+	NSS_IGS_STATS_MAX
+};
+
+/*
+ * nss_igs_stats_debug_instance
+ *	Stucture for H2N/N2H IGS debug stats
+ */
+static struct nss_igs_stats_debug_instance {
+	uint64_t stats[NSS_IGS_STATS_MAX];	/* IGS statistics for each instance. */
+	int32_t if_index;			/* IFB instance netdev index. */
+	uint32_t if_num;			/* IFB instance NSS interface number */
+	bool valid;				/* IFB statistics valid bit. */
+} nss_igs_stats_debug[NSS_MAX_IGS_DYNAMIC_INTERFACES];
+
+/*
+ * Data structures to store IGS interface stats.
+ */
+static DEFINE_SPINLOCK(nss_igs_stats_debug_lock);
+
+/*
+ * nss_igs_stats_str
+ *	IGS statistics strings for nss session stats
+ */
+struct nss_stats_info nss_igs_stats_str[NSS_IGS_STATS_MAX] = {
+	{"IGS_SHAPER_TX_DROP"				, NSS_STATS_TYPE_DROP},
+	{"IGS_SHAPER_DROP"				, NSS_STATS_TYPE_DROP},
+	{"IGS_EXCEPTION_IPV4_PARSE_FAIL"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV4_UNKNOWN_GRE_TYPE"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV4_UNKNOWN_L4"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV4_NO_CME"			, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV4_FRAG_INITIAL"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV4_FRAG_NON_INITIAL"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV4_MALFORMED_UDP"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV4_MALFORMED_TCP"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV4_MALFORMED_UDPL"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV4_MALFORMED_GRE"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV6_PARSE_FAIL"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV6_UNKNOWN_L4"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV6_NO_CME"			, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV6_FRAG_INITIAL"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV6_FRAG_NON_INITIAL"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV6_MALFORMED_UDP"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV6_MALFORMED_TCP"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV6_MALFORMED_UDPL"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_IPV6_MALFORMED_FRAG"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_EVENT_NO_SI"			, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_ETH_PARSE_FAIL"			, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_ETH_UNKNOWN_TYPE"		, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_PPPOE_NON_IP"			, NSS_STATS_TYPE_EXCEPTION},
+	{"IGS_EXCEPTION_PPPOE_MALFORMED"		, NSS_STATS_TYPE_EXCEPTION}
+};
+
+/*
+ * nss_igs_stats_get()
+ *	Get IGS statistics.
+ */
+static void nss_igs_stats_get(void *stats_mem)
+{
+	struct nss_igs_stats_debug_instance *stats = (struct nss_igs_stats_debug_instance *)stats_mem;
+	int i;
+
+	if (!stats) {
+		nss_warning("No memory to copy IGS stats");
+		return;
+	}
+
+	spin_lock_bh(&nss_igs_stats_debug_lock);
+	for (i = 0; i < NSS_MAX_IGS_DYNAMIC_INTERFACES; i++) {
+		if (nss_igs_stats_debug[i].valid) {
+			memcpy(stats, &nss_igs_stats_debug[i], sizeof(struct nss_igs_stats_debug_instance));
+			stats++;
+		}
+	}
+	spin_unlock_bh(&nss_igs_stats_debug_lock);
+}
+
+/*
+ * nss_igs_stats_read()
+ *	Read IGS statistics
+ */
+static ssize_t nss_igs_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+
+	uint32_t max_output_lines = 2 /* header & footer for instance stats */
+					+ NSS_MAX_IGS_DYNAMIC_INTERFACES *
+					 ((NSS_STATS_NODE_MAX + 3 ) + (NSS_IGS_STATS_MAX + 3)) /*instance stats */
+					 + 2;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	struct net_device *dev;
+	struct nss_igs_stats_debug_instance *igs_shadow_stats;
+	int id;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	igs_shadow_stats = kzalloc(sizeof(struct nss_igs_stats_debug_instance) *
+			 NSS_MAX_IGS_DYNAMIC_INTERFACES, GFP_KERNEL);
+	if (unlikely(!igs_shadow_stats)) {
+		nss_warning("Could not allocate memory for base debug statistics buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	/*
+	 * Get all stats
+	 */
+	nss_igs_stats_get((void *)igs_shadow_stats);
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "igs", NSS_STATS_SINGLE_CORE);
+
+	/*
+	 * Session stats
+	 */
+	for (id = 0; id < NSS_MAX_IGS_DYNAMIC_INTERFACES; id++) {
+
+			if (!igs_shadow_stats[id].valid) {
+				continue;
+			}
+
+			dev = dev_get_by_index(&init_net, igs_shadow_stats[id].if_index);
+			if (likely(dev)) {
+
+				size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%d. nss interface id=%d, netdevice=%s\n", id,
+						igs_shadow_stats[id].if_num, dev->name);
+				dev_put(dev);
+			} else {
+				size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%d. nss interface id=%d\n", id,
+						igs_shadow_stats[id].if_num);
+			}
+			size_wr += nss_stats_fill_common_stats(igs_shadow_stats[id].if_num, id, lbuf, size_wr, size_al, "igs");
+
+			/*
+			 * IGS exception stats.
+			 */
+			size_wr += nss_stats_print("igs", "igs exception stats start"
+							, id
+							, nss_igs_stats_str
+							, igs_shadow_stats[id].stats
+							, NSS_IGS_STATS_MAX
+							, lbuf, size_wr, size_al);
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	kfree(igs_shadow_stats);
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_igs_stats_sync
+ *	API to sync statistics for IGS
+ */
+void nss_igs_stats_sync(struct nss_ctx_instance *nss_ctx,
+		 struct nss_cmn_msg *ncm, uint16_t if_num)
+{
+	uint8_t i, j;
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	struct nss_igs_msg *nim = (struct nss_igs_msg *)ncm;
+	struct nss_igs_stats_sync_msg *stats_msg = &nim->msg.stats;
+	struct nss_cmn_node_stats *node_stats_ptr = &stats_msg->node_stats;
+	uint32_t *igs_stats_ptr = (uint32_t *)&stats_msg->igs_stats;
+
+	spin_lock_bh(&nss_igs_stats_debug_lock);
+	for (i = 0; i < NSS_MAX_IGS_DYNAMIC_INTERFACES; i++) {
+		if (nss_igs_stats_debug[i].if_num != if_num) {
+			continue;
+		}
+
+		for (j = 0; j < NSS_IGS_STATS_MAX; j++) {
+			/*
+			 * sync stats.
+			 */
+			nss_igs_stats_debug[i].stats[j] += igs_stats_ptr[j];
+		}
+		spin_unlock_bh(&nss_igs_stats_debug_lock);
+		goto sync_cmn_stats;
+	}
+
+	spin_unlock_bh(&nss_igs_stats_debug_lock);
+	return;
+
+sync_cmn_stats:
+	spin_lock_bh(&nss_top->stats_lock);
+
+	/*
+	 * sync common stats.
+	 */
+	nss_top->stats_node[if_num][NSS_STATS_NODE_RX_PKTS] += node_stats_ptr->rx_packets;
+	nss_top->stats_node[if_num][NSS_STATS_NODE_RX_BYTES] += node_stats_ptr->rx_bytes;
+	nss_top->stats_node[if_num][NSS_STATS_NODE_TX_PKTS] += node_stats_ptr->tx_packets;
+	nss_top->stats_node[if_num][NSS_STATS_NODE_TX_BYTES] += node_stats_ptr->tx_bytes;
+
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		nss_top->stats_node[if_num][NSS_STATS_NODE_RX_QUEUE_0_DROPPED + i] +=
+			node_stats_ptr->rx_dropped[i];
+	}
+
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_igs_stats_reset()
+ *	API to reset the IGS stats.
+ */
+void nss_igs_stats_reset(uint32_t if_num)
+{
+	uint8_t i;
+
+	spin_lock_bh(&nss_igs_stats_debug_lock);
+	for (i = 0; i < NSS_MAX_IGS_DYNAMIC_INTERFACES; i++) {
+		if (nss_igs_stats_debug[i].if_num == if_num) {
+			memset(&nss_igs_stats_debug[i], 0, sizeof(struct nss_igs_stats_debug_instance));
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_igs_stats_debug_lock);
+}
+
+/*
+ * nss_igs_stats_init()
+ *	API to initialize IGS debug instance statistics.
+ */
+void nss_igs_stats_init(uint32_t if_num, struct net_device *netdev)
+{
+	uint8_t i;
+
+	spin_lock_bh(&nss_igs_stats_debug_lock);
+	for (i = 0; i < NSS_MAX_IGS_DYNAMIC_INTERFACES; i++) {
+		if (!nss_igs_stats_debug[i].valid) {
+			nss_igs_stats_debug[i].valid = true;
+			nss_igs_stats_debug[i].if_num = if_num;
+			nss_igs_stats_debug[i].if_index = netdev->ifindex;
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_igs_stats_debug_lock);
+}
+
+/*
+ * nss_igs_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(igs)
+
+/*
+ * nss_igs_stats_dentry_create()
+ *	Create igs statistics debug entry.
+ */
+void nss_igs_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("igs", &nss_igs_stats_ops);
+}
diff --git a/qca-nss-drv/nss_igs_stats.h b/qca-nss-drv/nss_igs_stats.h
new file mode 100644
index 0000000..08f9c79
--- /dev/null
+++ b/qca-nss-drv/nss_igs_stats.h
@@ -0,0 +1,45 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_IGS_STATS_H
+#define __NSS_IGS_STATS_H
+
+/*
+ * nss_igs_stats_sync
+ *	API to sync statistics for IGS
+ */
+extern void nss_igs_stats_sync(struct nss_ctx_instance *nss_ctx,
+		 struct nss_cmn_msg *ncm, uint16_t if_num);
+
+/*
+ * nss_igs_stats_reset()
+ *	API to reset the IGS stats.
+ */
+extern void nss_igs_stats_reset(uint32_t if_num);
+
+/*
+ * nss_igs_stats_init()
+ *	API to initialize IGS debug instance statistics.
+ */
+extern void nss_igs_stats_init(uint32_t if_num, struct net_device *netdev);
+
+
+/*
+ * IGS statistics APIs
+ */
+extern void nss_igs_stats_dentry_create(void);
+
+#endif /* __NSS_IGS_STATS_H */
diff --git a/qca-nss-drv/nss_init.c b/qca-nss-drv/nss_init.c
new file mode 100644
index 0000000..ebd2a12
--- /dev/null
+++ b/qca-nss-drv/nss_init.c
@@ -0,0 +1,950 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_init.c
+ *	NSS init APIs
+ *
+ */
+#include "nss_core.h"
+#if (NSS_PM_SUPPORT == 1)
+#include "nss_pm.h"
+#endif
+#include "nss_tx_rx_common.h"
+#include "nss_data_plane.h"
+#include "nss_capwap.h"
+#include "nss_strings.h"
+
+#include <nss_hal.h>
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/proc_fs.h>
+#include <linux/device.h>
+
+#if (NSS_DT_SUPPORT == 1)
+#if (NSS_FABRIC_SCALING_SUPPORT == 1)
+#include <linux/fab_scaling.h>
+#endif
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/reset.h>
+#else
+#include <mach/msm_nss.h>
+#endif
+
+#include <linux/sysctl.h>
+#include <linux/regulator/consumer.h>
+#include <linux/clk.h>
+
+/*
+ * Global declarations
+ */
+int nss_ctl_redirect __read_mostly = 0;
+int nss_ctl_debug __read_mostly = 0;
+int nss_ctl_logbuf __read_mostly = 0;
+int nss_jumbo_mru  __read_mostly = 0;
+int nss_paged_mode __read_mostly = 0;
+#if (NSS_SKB_REUSE_SUPPORT == 1)
+int nss_max_reuse __read_mostly = PAGE_SIZE;
+#endif
+int nss_skip_nw_process = 0x0;
+module_param(nss_skip_nw_process, int, S_IRUGO);
+
+/*
+ * PM client handle
+ */
+#if (NSS_PM_SUPPORT == 1)
+static void *pm_client;
+#endif
+
+/*
+ * Handler to send NSS messages
+ */
+struct clk *nss_core0_clk;
+struct clk *nss_core1_clk;
+
+/*
+ * Handle fabric requests - only on new kernel
+ */
+#if (NSS_DT_SUPPORT == 1)
+struct clk *nss_fab0_clk;
+struct clk *nss_fab1_clk;
+#endif
+
+/*
+ * Top level nss context structure
+ */
+struct nss_top_instance nss_top_main;
+struct nss_cmd_buffer nss_cmd_buf;
+struct nss_runtime_sampling nss_runtime_samples;
+struct workqueue_struct *nss_wq;
+
+/*
+ * Work Queue to handle messages to Kernel
+ */
+nss_work_t *nss_work;
+
+extern struct of_device_id nss_dt_ids[];
+
+/*
+ * nss_probe()
+ *	HLOS device probe callback
+ */
+static inline int nss_probe(struct platform_device *nss_dev)
+{
+	return nss_hal_probe(nss_dev);
+}
+
+/*
+ * nss_remove()
+ *	HLOS device remove callback
+ */
+static inline int nss_remove(struct platform_device *nss_dev)
+{
+	return nss_hal_remove(nss_dev);
+}
+
+#if (NSS_DT_SUPPORT == 1)
+/*
+ * Platform Device ID for NSS core.
+ */
+struct of_device_id nss_dt_ids[] = {
+	{ .compatible = "qcom,nss" },
+	{ .compatible = "qcom,nss0" },
+	{ .compatible = "qcom,nss1" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, nss_dt_ids);
+#endif
+
+/*
+ * nss_driver
+ *	Platform driver structure for NSS
+ */
+struct platform_driver nss_driver = {
+	.probe	= nss_probe,
+	.remove	= nss_remove,
+	.driver	= {
+		.name	= "qca-nss",
+		.owner	= THIS_MODULE,
+#if (NSS_DT_SUPPORT == 1)
+		.of_match_table = of_match_ptr(nss_dt_ids),
+#endif
+	},
+};
+
+#if (NSS_FREQ_SCALE_SUPPORT == 1)
+/*
+ * nss_reset_frequency_stats_samples()
+ *	Reset all frequency sampling state when auto scaling is turned off.
+ */
+static void nss_reset_frequency_stats_samples(void)
+{
+	nss_runtime_samples.buffer_index = 0;
+	nss_runtime_samples.sum = 0;
+	nss_runtime_samples.average = 0;
+	nss_runtime_samples.sample_count = 0;
+	nss_runtime_samples.message_rate_limit = 0;
+	nss_runtime_samples.freq_scale_rate_limit_down = 0;
+}
+
+/*
+ * nss_current_freq_handler()
+ *	Handle Userspace Frequency Change Requests
+ */
+static int nss_current_freq_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret, i;
+
+	BUG_ON(!nss_wq);
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+
+	if (!*lenp || (*ppos && !write)) {
+		printk("Frequency Set to %d\n", nss_cmd_buf.current_freq);
+		*lenp = 0;
+		return ret;
+	}
+
+	/*
+	 * Check if frequency exists in frequency Table
+	 */
+	i = 0;
+	while (i < NSS_FREQ_MAX_SCALE) {
+		if (nss_runtime_samples.freq_scale[i].frequency == nss_cmd_buf.current_freq) {
+			break;
+		}
+		i++;
+	}
+	if (i == NSS_FREQ_MAX_SCALE) {
+		printk("Frequency not found. Please check Frequency Table\n");
+		nss_cmd_buf.current_freq = nss_runtime_samples.freq_scale[nss_runtime_samples.freq_scale_index].frequency;
+		return ret;
+	}
+
+	/*
+	 * Turn off Auto Scale
+	*/
+	nss_cmd_buf.auto_scale = 0;
+	nss_runtime_samples.freq_scale_ready = 0;
+	nss_runtime_samples.freq_scale_index = i;
+
+	nss_work = (nss_work_t *)kmalloc(sizeof(nss_work_t), GFP_ATOMIC);
+	if (!nss_work) {
+		nss_info("NSS Freq WQ kmalloc fail");
+		return ret;
+	}
+	INIT_WORK((struct work_struct *)nss_work, nss_hal_wq_function);
+	nss_work->frequency = nss_cmd_buf.current_freq;
+	nss_work->stats_enable = 0;
+
+	/*
+	 * Ensure we start with a fresh set of samples later
+	 */
+	nss_reset_frequency_stats_samples();
+
+	queue_work(nss_wq, (struct work_struct *)nss_work);
+
+	return ret;
+}
+
+/*
+ * nss_auto_scale_handler()
+ *	Enables or Disable Auto Scaling
+ */
+static int nss_auto_scale_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret;
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+
+	if (!*lenp || (*ppos && !write)) {
+		return ret;
+	}
+
+	if (nss_cmd_buf.auto_scale != 1) {
+		/*
+		 * Is auto scaling currently enabled? If so, send the command to
+		 * disable stats reporting to NSS
+		 */
+		if (nss_runtime_samples.freq_scale_ready != 0) {
+			nss_cmd_buf.current_freq = nss_runtime_samples.freq_scale[nss_runtime_samples.freq_scale_index].frequency;
+			nss_work = (nss_work_t *)kmalloc(sizeof(nss_work_t), GFP_ATOMIC);
+			if (!nss_work) {
+				nss_info("NSS Freq WQ kmalloc fail");
+				return ret;
+			}
+			INIT_WORK((struct work_struct *)nss_work, nss_hal_wq_function);
+			nss_work->frequency = nss_cmd_buf.current_freq;
+			nss_work->stats_enable = 0;
+			queue_work(nss_wq, (struct work_struct *)nss_work);
+			nss_runtime_samples.freq_scale_ready = 0;
+
+			/*
+			 * The current samples would be stale later when scaling is
+			 * enabled again, hence reset them
+			 */
+			nss_reset_frequency_stats_samples();
+		}
+		return ret;
+	}
+
+	/*
+	 * Setup default values - Middle of Freq Scale Band
+	 */
+	nss_runtime_samples.freq_scale_index = 1;
+	nss_runtime_samples.sample_count = 0;
+	nss_runtime_samples.initialized = 0;
+	nss_cmd_buf.current_freq = nss_runtime_samples.freq_scale[nss_runtime_samples.freq_scale_index].frequency;
+
+	nss_work = (nss_work_t *)kmalloc(sizeof(nss_work_t), GFP_ATOMIC);
+	if (!nss_work) {
+		nss_info("NSS Freq WQ kmalloc fail");
+		return ret;
+	}
+	INIT_WORK((struct work_struct *)nss_work, nss_hal_wq_function);
+	nss_work->frequency = nss_cmd_buf.current_freq;
+	nss_work->stats_enable = 1;
+	queue_work(nss_wq, (struct work_struct *)nss_work);
+
+	nss_cmd_buf.auto_scale = 0;
+	nss_runtime_samples.freq_scale_ready = 1;
+
+	return ret;
+}
+
+/*
+ * nss_get_freq_table_handler()
+ *	Display Support Freq and Ex how to Change.
+ */
+static int nss_get_freq_table_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret, i;
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+
+	if (write) {
+		return ret;
+	}
+
+	printk("Frequency Supported - ");
+
+	i = 0;
+	while (i < NSS_FREQ_MAX_SCALE) {
+		if (nss_runtime_samples.freq_scale[i].frequency != NSS_FREQ_SCALE_NA) {
+			printk("%d Hz ", nss_runtime_samples.freq_scale[i].frequency);
+		}
+		i++;
+	}
+	printk("\n");
+
+	*lenp = 0;
+	return ret;
+}
+
+/*
+ * nss_get_average_inst_handler()
+ *	Display AVG Inst Per Ms.
+ */
+static int nss_get_average_inst_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret;
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+
+	if (write) {
+		return ret;
+	}
+
+	printk("Current Inst Per Ms %x\n", nss_runtime_samples.average);
+
+	*lenp = 0;
+	return ret;
+}
+#endif
+
+#if (NSS_FW_DBG_SUPPORT == 1)
+/*
+ * nss_debug_handler()
+ *	Enable NSS debug output
+ */
+static int nss_debug_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret;
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (!ret) {
+		if ((write) && (nss_ctl_debug != 0)) {
+			printk("Enabling NSS SPI Debug\n");
+			nss_hal_debug_enable();
+		}
+	}
+
+	return ret;
+}
+#endif
+
+/*
+ * nss_coredump_handler()
+ *	Send Signal To Coredump NSS Cores
+ */
+static int nss_coredump_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[NSS_CORE_0];
+	int ret;
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (!ret) {
+		/*
+		 * if nss_cmd_buf.coredump is not 0 or 1, panic will be disabled
+		 * when NSS FW crashes, so OEM/ODM have a chance to use mdump
+		 * to dump crash dump (coredump) and send dump to us for analysis.
+		 */
+		if ((write) && (nss_ctl_debug != 0) && nss_cmd_buf.coredump == 1) {
+			printk("Coredumping to DDR\n");
+			nss_hal_send_interrupt(nss_ctx, NSS_H2N_INTR_TRIGGER_COREDUMP);
+		}
+	}
+
+	return ret;
+}
+
+/*
+ * nss_jumbo_mru_handler()
+ *	Sysctl to modify nss_jumbo_mru
+ */
+static int nss_jumbo_mru_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret;
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret) {
+		return ret;
+	}
+
+	if (write) {
+		nss_core_set_jumbo_mru(nss_jumbo_mru);
+		nss_info("jumbo_mru set to %d\n", nss_jumbo_mru);
+	}
+
+	return ret;
+}
+
+/* nss_paged_mode_handler()
+ *	Sysctl to modify nss_paged_mode.
+ */
+
+static int nss_paged_mode_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret;
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret) {
+		return ret;
+	}
+
+	if (write) {
+		nss_core_set_paged_mode(nss_paged_mode);
+		nss_info("paged_mode set to %d\n", nss_paged_mode);
+	}
+
+	return ret;
+}
+
+#if (NSS_SKB_REUSE_SUPPORT == 1)
+/*
+ * nss_get_min_reuse_handler()
+ *	Sysctl to get min reuse sizes
+ */
+static int nss_get_min_reuse_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret;
+	struct nss_ctx_instance *nss_ctx = NULL;
+	uint32_t core_id;
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret) {
+		return ret;
+	}
+
+	printk("Min SKB reuse sizes - ");
+
+	for (core_id = 0; core_id < NSS_CORE_MAX; core_id++) {
+		nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[core_id];
+		printk("core %d: %d ", core_id, nss_core_get_min_reuse(nss_ctx));
+	}
+
+	printk("\n");
+	*lenp = 0;
+	return ret;
+}
+
+/*
+ * nss_max_reuse_handler()
+ *	Sysctl to modify nss_max_reuse
+ */
+static int nss_max_reuse_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret;
+
+	nss_max_reuse = nss_core_get_max_reuse();
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret) {
+		return ret;
+	}
+
+	if (write) {
+		nss_core_set_max_reuse(nss_max_reuse);
+		nss_info("max_reuse set to %d\n", nss_max_reuse);
+	}
+
+	return ret;
+}
+
+/*
+ * sysctl-tuning for NSS driver SKB reuse
+ */
+static struct ctl_table nss_skb_reuse_table[] = {
+	{
+		.procname		= "min_sizes",
+		.data			= NULL,
+		.maxlen			= sizeof(int),
+		.mode			= 0644,
+		.proc_handler	= &nss_get_min_reuse_handler,
+	},
+	{
+		.procname		= "max_size",
+		.data			= &nss_max_reuse,
+		.maxlen			= sizeof(int),
+		.mode			= 0644,
+		.proc_handler	= &nss_max_reuse_handler,
+	},
+	{ }
+};
+#endif
+
+#if (NSS_FREQ_SCALE_SUPPORT == 1)
+/*
+ * sysctl-tuning infrastructure.
+ */
+static struct ctl_table nss_freq_table[] = {
+	{
+		.procname		= "current_freq",
+		.data			= &nss_cmd_buf.current_freq,
+		.maxlen			= sizeof(int),
+		.mode			= 0644,
+		.proc_handler	= &nss_current_freq_handler,
+	},
+	{
+		.procname		= "freq_table",
+		.data			= &nss_cmd_buf.max_freq,
+		.maxlen			= sizeof(int),
+		.mode			= 0644,
+		.proc_handler	= &nss_get_freq_table_handler,
+	},
+	{
+		.procname		= "auto_scale",
+		.data			= &nss_cmd_buf.auto_scale,
+		.maxlen			= sizeof(int),
+		.mode			= 0644,
+		.proc_handler	= &nss_auto_scale_handler,
+	},
+	{
+		.procname		= "inst_per_sec",
+		.data			= &nss_cmd_buf.average_inst,
+		.maxlen			= sizeof(int),
+		.mode			= 0644,
+		.proc_handler	= &nss_get_average_inst_handler,
+	},
+	{ }
+};
+#endif
+
+static struct ctl_table nss_general_table[] = {
+	{
+		.procname               = "redirect",
+		.data                   = &nss_ctl_redirect,
+		.maxlen                 = sizeof(int),
+		.mode                   = 0644,
+		.proc_handler		= proc_dointvec,
+	},
+#if (NSS_FW_DBG_SUPPORT == 1)
+	{
+		.procname               = "debug",
+		.data                   = &nss_ctl_debug,
+		.maxlen                 = sizeof(int),
+		.mode                   = 0644,
+		.proc_handler		= &nss_debug_handler,
+	},
+#endif
+	{
+		.procname               = "coredump",
+		.data                   = &nss_cmd_buf.coredump,
+		.maxlen                 = sizeof(int),
+		.mode                   = 0644,
+		.proc_handler		= &nss_coredump_handler,
+	},
+	{
+		.procname               = "logbuf",
+		.data                   = &nss_ctl_logbuf,
+		.maxlen                 = sizeof(int),
+		.mode                   = 0644,
+		.proc_handler		= &nss_logbuffer_handler,
+	},
+	{
+		.procname               = "jumbo_mru",
+		.data                   = &nss_jumbo_mru,
+		.maxlen                 = sizeof(int),
+		.mode                   = 0644,
+		.proc_handler           = &nss_jumbo_mru_handler,
+	},
+	{
+		.procname               = "paged_mode",
+		.data                   = &nss_paged_mode,
+		.maxlen                 = sizeof(int),
+		.mode                   = 0644,
+		.proc_handler           = &nss_paged_mode_handler,
+	},
+	{ }
+};
+
+static struct ctl_table nss_init_dir[] = {
+#if (NSS_FREQ_SCALE_SUPPORT == 1)
+	{
+		.procname               = "clock",
+		.mode                   = 0555,
+		.child                  = nss_freq_table,
+	},
+#endif
+	{
+		.procname               = "general",
+		.mode                   = 0555,
+		.child                  = nss_general_table,
+	},
+#if (NSS_SKB_REUSE_SUPPORT == 1)
+	{
+		.procname               = "skb_reuse",
+		.mode                   = 0555,
+		.child                  = nss_skb_reuse_table,
+	},
+#endif
+	{ }
+};
+
+static struct ctl_table nss_root_dir[] = {
+	{
+		.procname		= "nss",
+		.mode			= 0555,
+		.child			= nss_init_dir,
+	},
+	{ }
+};
+
+static struct ctl_table nss_root[] = {
+	{
+		.procname		= "dev",
+		.mode			= 0555,
+		.child			= nss_root_dir,
+	},
+	{ }
+};
+
+static struct ctl_table_header *nss_dev_header;
+
+/*
+ * nss_init()
+ *	Registers nss driver
+ */
+static int __init nss_init(void)
+{
+#if (NSS_DT_SUPPORT == 1)
+	struct device_node *cmn = NULL;
+#endif
+	nss_info("Init NSS driver");
+
+#if (NSS_DT_SUPPORT == 1)
+	/*
+	 * Get reference to NSS common device node
+	 */
+	cmn = of_find_node_by_name(NULL, "nss-common");
+	if (!cmn) {
+		nss_info_always("qca-nss-drv.ko is loaded for symbol link\n");
+		return 0;
+	}
+	of_node_put(cmn);
+
+	/*
+	 * Pick up HAL by target information
+	 */
+#if defined(NSS_HAL_IPQ806X_SUPPORT)
+	if (of_machine_is_compatible("qcom,ipq8064") || of_machine_is_compatible("qcom,ipq8062")) {
+		nss_top_main.hal_ops = &nss_hal_ipq806x_ops;
+		nss_top_main.data_plane_ops = &nss_data_plane_gmac_ops;
+		nss_top_main.num_nss = 2;
+	}
+#endif
+#if defined(NSS_HAL_IPQ807x_SUPPORT)
+	if (of_machine_is_compatible("qcom,ipq807x") || of_machine_is_compatible("qcom,ipq8074")) {
+		nss_top_main.hal_ops = &nss_hal_ipq807x_ops;
+		nss_top_main.data_plane_ops = &nss_data_plane_ops;
+#if defined(NSS_MEM_PROFILE_LOW)
+		nss_top_main.num_nss = 1;
+#else
+		nss_top_main.num_nss = 2;
+#endif
+	}
+#endif
+#if defined(NSS_HAL_IPQ60XX_SUPPORT)
+	if (of_machine_is_compatible("qcom,ipq6018")) {
+		nss_top_main.hal_ops = &nss_hal_ipq60xx_ops;
+		nss_top_main.data_plane_ops = &nss_data_plane_ops;
+		nss_top_main.num_nss = 1;
+	}
+#endif
+#if defined(NSS_HAL_IPQ50XX_SUPPORT)
+	if (of_machine_is_compatible("qcom,ipq5018")) {
+		nss_top_main.hal_ops = &nss_hal_ipq50xx_ops;
+		nss_top_main.data_plane_ops = &nss_data_plane_ops;
+		nss_top_main.num_nss = 1;
+	}
+#endif
+#if defined(NSS_HAL_FSM9010_SUPPORT)
+	if (of_machine_is_compatible("qcom,fsm9010")) {
+		nss_top_main.hal_ops = &nss_hal_fsm9010_ops;
+		nss_top_main.data_plane_ops = &nss_data_plane_gmac_ops;
+		nss_top_main.num_nss = 1;
+	}
+#endif
+	if (!nss_top_main.hal_ops) {
+		nss_info_always("No supported HAL compiled on this platform\n");
+		return -EFAULT;
+	}
+#else
+	/*
+	 * For banana, only ipq806x is supported
+	 */
+	nss_top_main.hal_ops = &nss_hal_ipq806x_ops;
+	nss_top_main.data_plane_ops = &nss_data_plane_gmac_ops;
+	nss_top_main.num_nss = 2;
+
+#endif /* NSS_DT_SUPPORT */
+	nss_top_main.nss_hal_common_init_done = false;
+
+	/*
+	 * Initialize data_plane workqueue
+	 */
+	if (nss_data_plane_init_delay_work()) {
+		nss_warning("Error initializing nss_data_plane_workqueue\n");
+		return -EFAULT;
+	}
+
+	/*
+	 * Enable spin locks
+	 */
+	spin_lock_init(&(nss_top_main.lock));
+	spin_lock_init(&(nss_top_main.stats_lock));
+	mutex_init(&(nss_top_main.wq_lock));
+
+	/*
+	 * Enable NSS statistics
+	 */
+	nss_stats_init();
+
+	/*
+	 * Enable NSS statistics names.
+	 */
+	nss_strings_init();
+
+	/*
+	 * Register sysctl table.
+	 */
+	nss_dev_header = register_sysctl_table(nss_root);
+
+	/*
+	 * Registering sysctl for ipv4/6 specific config.
+	 */
+	nss_ipv4_register_sysctl();
+#ifdef NSS_DRV_IPV6_ENABLE
+	nss_ipv6_register_sysctl();
+#endif
+
+	/*
+	 * Registering sysctl for n2h specific config.
+	 */
+	if (nss_top_main.num_nss == 1) {
+		nss_n2h_single_core_register_sysctl();
+	} else {
+		nss_n2h_multi_core_register_sysctl();
+	}
+
+	/*
+	 * Registering sysctl for rps specific config.
+	 */
+	nss_rps_register_sysctl();
+
+#ifdef NSS_DRV_C2C_ENABLE
+	/*
+	 * Registering sysctl for c2c_tx specific config.
+	 */
+	nss_c2c_tx_register_sysctl();
+#endif
+
+	/*
+	 * Registering sysctl for for printing non zero stats.
+	 */
+	nss_stats_register_sysctl();
+
+	/*
+	 * Register sysctl for project config
+	 */
+	nss_project_register_sysctl();
+
+	/*
+	 * Registering sysctl for pppoe specific config.
+	 */
+	nss_pppoe_register_sysctl();
+
+	/*
+	 * Setup Runtime Sample values
+	 */
+	nss_runtime_samples.freq_scale_index = 1;
+	nss_runtime_samples.freq_scale_ready = 0;
+	nss_runtime_samples.freq_scale_rate_limit_down = 0;
+	nss_runtime_samples.buffer_index = 0;
+	nss_runtime_samples.sum = 0;
+	nss_runtime_samples.sample_count = 0;
+	nss_runtime_samples.average = 0;
+	nss_runtime_samples.message_rate_limit = 0;
+	nss_runtime_samples.initialized = 0;
+
+	nss_cmd_buf.current_freq = nss_runtime_samples.freq_scale[nss_runtime_samples.freq_scale_index].frequency;
+
+	/*
+	 * Initial Workqueue
+	 */
+	nss_wq = create_workqueue("nss_freq_queue");
+
+#if (NSS_PM_SUPPORT == 1)
+	/*
+	 * Initialize NSS Bus PM module
+	 */
+	nss_pm_init();
+
+	/*
+	 * Register with Bus driver
+	 */
+	pm_client = nss_pm_client_register(NSS_PM_CLIENT_NETAP);
+	if (!pm_client) {
+		nss_warning("Error registering with PM driver");
+	}
+#endif
+
+	/*
+	 * Initialize mtu size needed as start
+	 */
+	nss_top_main.prev_mtu_sz = ETH_DATA_LEN;
+
+	/*
+	 * register panic handler and timeout control
+	 */
+	nss_coredump_notify_register();
+	nss_coredump_init_delay_work();
+
+#ifdef NSS_DRV_CAPWAP_ENABLE
+	/*
+	 * Init capwap
+	 */
+	nss_capwap_init();
+#endif
+
+#ifdef NSS_DRV_QRFS_ENABLE
+	/*
+	 * Init QRFS
+	 */
+	nss_qrfs_init();
+#endif
+
+#ifdef NSS_DRV_C2C_ENABLE
+	/*
+	 * Init c2c_tx
+	 */
+	nss_c2c_tx_init();
+#endif
+
+#ifdef NSS_DRV_PVXLAN_ENABLE
+	/*
+	 * Init pvxlan
+	 */
+	nss_pvxlan_init();
+#endif
+
+#ifdef NSS_DRV_CLMAP_ENABLE
+	/*
+	 * Init clmap
+	 */
+	nss_clmap_init();
+#endif
+
+	/*
+	 * INIT ppe on supported platform
+	 */
+#ifdef NSS_DRV_PPE_ENABLE
+	nss_ppe_init();
+#endif
+
+#ifdef NSS_DRV_DMA_ENABLE
+	nss_dma_init();
+#endif
+
+	/*
+	 * Init Wi-Fi mesh
+	 */
+#ifdef NSS_DRV_WIFI_MESH_ENABLE
+	nss_wifi_mesh_init();
+#endif
+
+	/*
+	 * Register platform_driver
+	 */
+	return platform_driver_register(&nss_driver);
+}
+
+/*
+ * nss_cleanup()
+ *	Unregisters nss driver
+ */
+static void __exit nss_cleanup(void)
+{
+	nss_info("Exit NSS driver");
+
+	if (nss_dev_header)
+		unregister_sysctl_table(nss_dev_header);
+
+	/*
+	 * Unregister n2h specific sysctl
+	 */
+	nss_n2h_unregister_sysctl();
+
+	/*
+	 * Unregister rps specific sysctl
+	 */
+	nss_rps_unregister_sysctl();
+
+#ifdef NSS_DRV_C2C_ENABLE
+	/*
+	 * Unregister c2c_tx specific sysctl
+	 */
+	nss_c2c_tx_unregister_sysctl();
+#endif
+
+	/*
+	 * Unregister pppoe specific sysctl
+	 */
+	nss_pppoe_unregister_sysctl();
+
+	/*
+	 * Unregister ipv4/6 specific sysctl and free allocated to connection tables
+	 */
+	nss_ipv4_unregister_sysctl();
+	nss_ipv4_free_conn_tables();
+
+#ifdef NSS_DRV_IPV6_ENABLE
+	nss_ipv6_unregister_sysctl();
+	nss_ipv6_free_conn_tables();
+#endif
+
+	nss_project_unregister_sysctl();
+	nss_data_plane_destroy_delay_work();
+
+	/*
+	 * cleanup ppe on supported platform
+	 */
+#ifdef NSS_DRV_PPE_ENABLE
+	nss_ppe_free();
+#endif
+
+	platform_driver_unregister(&nss_driver);
+}
+
+module_init(nss_init);
+module_exit(nss_cleanup);
+
+MODULE_DESCRIPTION("QCA NSS Driver");
+MODULE_AUTHOR("Qualcomm Atheros Inc");
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/qca-nss-drv/nss_ipsec.c b/qca-nss-drv/nss_ipsec.c
new file mode 100644
index 0000000..49c7805
--- /dev/null
+++ b/qca-nss-drv/nss_ipsec.c
@@ -0,0 +1,597 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ipsec.c
+ *	NSS IPsec APIs
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_ipsec.h"
+#include "nss_ppe.h"
+#include "nss_ipsec_log.h"
+
+#if defined(NSS_HAL_IPQ806X_SUPPORT)
+#define NSS_IPSEC_ENCAP_INTERFACE_NUM NSS_IPSEC_ENCAP_IF_NUMBER
+#define NSS_IPSEC_DECAP_INTERFACE_NUM NSS_IPSEC_DECAP_IF_NUMBER
+#define NSS_IPSEC_DATA_INTERFACE_NUM NSS_C2C_TX_INTERFACE
+
+#elif defined(NSS_HAL_FSM9010_SUPPORT)
+#define NSS_IPSEC_ENCAP_INTERFACE_NUM NSS_IPSEC_ENCAP_IF_NUMBER
+#define NSS_IPSEC_DECAP_INTERFACE_NUM NSS_IPSEC_DECAP_IF_NUMBER
+#define NSS_IPSEC_DATA_INTERFACE_NUM NSS_IPSEC_CMN_INTERFACE
+
+#elif defined(NSS_HAL_IPQ807x_SUPPORT)
+#define NSS_IPSEC_ENCAP_INTERFACE_NUM NSS_IPSEC_CMN_INTERFACE
+#define NSS_IPSEC_DECAP_INTERFACE_NUM NSS_IPSEC_CMN_INTERFACE
+#define NSS_IPSEC_DATA_INTERFACE_NUM NSS_IPSEC_CMN_INTERFACE
+
+#elif defined(NSS_HAL_IPQ60XX_SUPPORT)
+#define NSS_IPSEC_ENCAP_INTERFACE_NUM NSS_IPSEC_CMN_INTERFACE
+#define NSS_IPSEC_DECAP_INTERFACE_NUM NSS_IPSEC_CMN_INTERFACE
+#define NSS_IPSEC_DATA_INTERFACE_NUM NSS_IPSEC_CMN_INTERFACE
+
+#elif defined(NSS_HAL_IPQ50XX_SUPPORT)
+#define NSS_IPSEC_ENCAP_INTERFACE_NUM NSS_IPSEC_CMN_INTERFACE
+#define NSS_IPSEC_DECAP_INTERFACE_NUM NSS_IPSEC_CMN_INTERFACE
+#define NSS_IPSEC_DATA_INTERFACE_NUM NSS_IPSEC_CMN_INTERFACE
+
+#else
+#define NSS_IPSEC_ENCAP_INTERFACE_NUM -1
+#define NSS_IPSEC_DECAP_INTERFACE_NUM -1
+#define NSS_IPSEC_DATA_INTERFACE_NUM -1
+
+#endif
+
+/*
+ * Amount time the synchronous message should wait for response from
+ * NSS before the timeout happens. After the timeout the message
+ * response even if it arrives has to be discarded. Typically, the
+ * time needs to be selected based on the worst case time in case of
+ * peak throughput between host & NSS.
+ */
+#define NSS_IPSEC_TX_TIMEO_TICKS msecs_to_jiffies(3000) /* 3 Seconds */
+
+/*
+ * Private data structure to hold state for
+ * the ipsec specific NSS interaction
+ */
+struct nss_ipsec_pvt {
+	struct semaphore sem;		/* used for synchronizing 'tx_msg_sync' */
+	struct completion complete;	/* completion callback */
+	atomic_t resp;	/* Response error type */
+} nss_ipsec;
+
+/*
+ * nss_ipsec_get_msg_ctx()
+ * 	return ipsec message context assoicated with the callback
+ *
+ * Note: certain SOC the decap interface specially programmed
+ */
+static inline nss_ptr_t nss_ipsec_get_msg_ctx(struct nss_ctx_instance *nss_ctx, uint32_t interface_num)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	/*
+	 * the encap is primary interface
+	 */
+	if (interface_num == NSS_IPSEC_ENCAP_INTERFACE_NUM)
+		return (nss_ptr_t)nss_top->ipsec_encap_ctx;
+
+	return (nss_ptr_t)nss_top->ipsec_decap_ctx;
+}
+
+/*
+ * nss_ipsec_get_msg_callback()
+ * 	this gets the message callback handler
+ */
+static inline nss_ptr_t nss_ipsec_get_msg_callback(struct nss_ctx_instance *nss_ctx, uint32_t interface_num)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	/*
+	 * the encap is primary interface
+	 */
+	if (interface_num == NSS_IPSEC_ENCAP_INTERFACE_NUM)
+		return (nss_ptr_t)nss_top->ipsec_encap_callback;
+
+	return (nss_ptr_t)nss_top->ipsec_decap_callback;
+}
+
+/*
+ **********************************
+ Rx APIs
+ **********************************
+ */
+
+/*
+ * nss_ipsec_msg_handler()
+ * 	this handles all the IPsec events and responses
+ */
+static void nss_ipsec_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, void *app_data __attribute((unused)))
+{
+	struct nss_ipsec_msg *nim = (struct nss_ipsec_msg *)ncm;
+	nss_ipsec_msg_callback_t cb = NULL;
+	uint32_t if_num = ncm->interface;
+
+	/*
+	 * Trace messages.
+	 */
+	nss_ipsec_log_rx_msg(nim);
+
+	/*
+	 * Sanity check the message type
+	 */
+	if (ncm->type > NSS_IPSEC_MSG_TYPE_MAX) {
+		nss_warning("%px: rx message type out of range: %d", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_ipsec_msg)) {
+		nss_warning("%px: rx message length is invalid: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	BUG_ON((if_num != NSS_IPSEC_ENCAP_INTERFACE_NUM) && (if_num != NSS_IPSEC_DECAP_INTERFACE_NUM));
+
+	if (ncm->response == NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: rx message response for if %d, type %d, is invalid: %d", nss_ctx, ncm->interface,
+				ncm->type, ncm->response);
+		return;
+	}
+
+	/*
+	 * Is this a notification? if, yes then fill up the callback and app_data from
+	 * locally stored state
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = nss_ipsec_get_msg_callback(nss_ctx, if_num);
+		ncm->app_data = nss_ipsec_get_msg_ctx(nss_ctx, if_num);
+	}
+
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * load, test & call
+	 */
+	cb = (nss_ipsec_msg_callback_t)ncm->cb;
+	if (unlikely(!cb)) {
+		nss_trace("%px: rx handler has been unregistered for i/f: %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb((void *)ncm->app_data, nim);
+}
+
+/*
+ **********************************
+ Tx APIs
+ **********************************
+ */
+
+/*
+ * nss_ipsec_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_ipsec_callback(void *app_data, struct nss_ipsec_msg *nim)
+{
+	struct nss_cmn_msg *ncm = &nim->cm;
+
+	/*
+	 * This callback is for synchronous operation. The caller sends its
+	 * response pointer which needs to be loaded with the response
+	 * data arriving from the NSS
+	 */
+	atomic_t *resp = (atomic_t *)app_data;
+
+	if (ncm->response == NSS_CMN_RESPONSE_ACK) {
+		atomic_set(resp, NSS_IPSEC_ERROR_TYPE_NONE);
+		complete(&nss_ipsec.complete);
+		return;
+	}
+
+	atomic_set(resp, ncm->error);
+	complete(&nss_ipsec.complete);
+}
+
+/*
+ * nss_ipsec_tx_msg
+ *	Send ipsec rule to NSS.
+ */
+nss_tx_status_t nss_ipsec_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_ipsec_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	nss_info("%px: message %d for if %d\n", nss_ctx, ncm->type, ncm->interface);
+
+	BUILD_BUG_ON(NSS_NBUF_PAYLOAD_SIZE < sizeof(struct nss_ipsec_msg));
+
+	/*
+	 * Trace messages.
+	 */
+	nss_ipsec_log_tx_msg(msg);
+
+	if ((ncm->interface != NSS_IPSEC_ENCAP_INTERFACE_NUM) && (ncm->interface != NSS_IPSEC_DECAP_INTERFACE_NUM)) {
+		nss_warning("%px: tx message request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_IPSEC_MSG_TYPE_MAX) {
+		nss_warning("%px: tx message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	nss_info("msg params version:%d, interface:%d, type:%d, cb:%px, app_data:%px, len:%d\n",
+			ncm->version, ncm->interface, ncm->type, (void *)ncm->cb, (void *)ncm->app_data, ncm->len);
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_ipsec_tx_msg);
+
+/*
+ * nss_ipsec_tx_msg_sync()
+ *	Transmit a ipsec message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_ipsec_tx_msg_sync(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+					enum nss_ipsec_msg_type type, uint16_t len,
+					struct nss_ipsec_msg *nim, enum nss_ipsec_error_type *resp)
+{
+	struct nss_ipsec_msg nim_local = { {0} };
+	nss_tx_status_t status;
+	int ret;
+
+	/*
+	 * Length of the message should be the based on type
+	 */
+	if (len > sizeof(nim_local.msg)) {
+		nss_warning("%px: (%u)Bad message length(%u) for type (%d)", nss_ctx, if_num, len, type);
+		return NSS_TX_FAILURE_TOO_LARGE;
+	}
+
+	/*
+	 * Response buffer is a required for copying the response for message
+	 */
+	if (!resp) {
+		nss_warning("%px: (%u)Response buffer is empty, type(%d)", nss_ctx, if_num, type);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	/*
+	 * TODO: this can be removed in future as we need to ensure that the response
+	 * memory is only updated when the current outstanding request is waiting.
+	 * This can be solved by introducing sequence no. in messages and only completing
+	 * the message if the sequence no. matches. For now this is solved by passing
+	 * a known memory nss_ipsec.resp
+	 */
+	down(&nss_ipsec.sem);
+
+	/*
+	 * Initializing it to a fail error type
+	 */
+	atomic_set(&nss_ipsec.resp, NSS_IPSEC_ERROR_TYPE_UNHANDLED_MSG);
+
+	/*
+	 * We need to copy the message content into the actual message
+	 * to be sent to NSS
+	 *
+	 * Note: Here pass the nss_ipsec.resp as the pointer. Since, the caller
+	 * provided pointer is not allocated by us and may go away when this function
+	 * returns with failure. The callback is not aware of this and may try to
+	 * access the pointer incorrectly potentially resulting in a crash.
+	 */
+	nss_ipsec_msg_init(&nim_local, if_num, type, len, nss_ipsec_callback, &nss_ipsec.resp);
+	memcpy(&nim_local.msg, &nim->msg, len);
+
+	status = nss_ipsec_tx_msg(nss_ctx, &nim_local);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: ipsec_tx_msg failed", nss_ctx);
+		goto done;
+	}
+
+	ret = wait_for_completion_timeout(&nss_ipsec.complete, NSS_IPSEC_TX_TIMEO_TICKS);
+	if (!ret) {
+		nss_warning("%px: IPsec msg tx failed due to timeout", nss_ctx);
+		status = NSS_TX_FAILURE_NOT_ENABLED;
+		goto done;
+	}
+
+	/*
+	 * Read memory barrier
+	 */
+	smp_rmb();
+
+	/*
+	 * Copy the response received
+	 */
+	*resp = atomic_read(&nss_ipsec.resp);
+
+	/*
+	 * Only in case of non-error response we will
+	 * indicate success
+	 */
+	if (*resp != NSS_IPSEC_ERROR_TYPE_NONE)
+		status = NSS_TX_FAILURE;
+
+done:
+	up(&nss_ipsec.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_ipsec_tx_msg_sync);
+
+/*
+ * nss_ipsec_tx_buf
+ * 	Send data packet for ipsec processing
+ */
+nss_tx_status_t nss_ipsec_tx_buf(struct sk_buff *skb, uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[nss_top_main.ipsec_handler_id];
+
+	nss_trace("%px: IPsec If Tx packet, id:%d, data=%px", nss_ctx, if_num, skb->data);
+
+	return nss_core_send_packet(nss_ctx, skb, if_num, H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+EXPORT_SYMBOL(nss_ipsec_tx_buf);
+
+/*
+ **********************************
+ Register APIs
+ **********************************
+ */
+
+/*
+ * nss_ipsec_notify_register()
+ * 	register message notifier for the given interface (if_num)
+ */
+struct nss_ctx_instance *nss_ipsec_notify_register(uint32_t if_num, nss_ipsec_msg_callback_t cb, void *app_data)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	uint8_t core_id = nss_top->ipsec_handler_id;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[core_id];
+
+	if (if_num >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("%px: notfiy register received for invalid interface %d", nss_ctx, if_num);
+		return NULL;
+	}
+
+	/*
+	 * the encap is primary interface
+	 */
+	if (if_num == NSS_IPSEC_ENCAP_INTERFACE_NUM) {
+		nss_top->ipsec_encap_callback = cb;
+		nss_top->ipsec_encap_ctx = app_data;
+		return nss_ctx;
+	}
+
+	nss_top->ipsec_decap_callback = cb;
+	nss_top->ipsec_decap_ctx = app_data;
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_ipsec_notify_register);
+
+/*
+ * nss_ipsec_notify_unregister()
+ * 	unregister the IPsec notifier for the given interface number (if_num)
+ */
+void nss_ipsec_notify_unregister(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	if (if_num >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("%px: notify unregister received for invalid interface %d", nss_ctx, if_num);
+		return;
+	}
+
+	/*
+	 * the encap is primary interface
+	 */
+	if (if_num == NSS_IPSEC_ENCAP_INTERFACE_NUM) {
+		nss_top->ipsec_encap_callback = NULL;
+		nss_top->ipsec_encap_ctx = NULL;
+		return;
+	}
+
+	nss_top->ipsec_decap_callback = NULL;
+	nss_top->ipsec_decap_ctx = NULL;
+}
+EXPORT_SYMBOL(nss_ipsec_notify_unregister);
+
+/*
+ * nss_ipsec_data_register()
+ * 	register a data callback routine
+ */
+struct nss_ctx_instance *nss_ipsec_data_register(uint32_t if_num, nss_ipsec_buf_callback_t cb, struct net_device *netdev, uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx, *nss_ctx0;
+
+	nss_ctx = &nss_top_main.nss[nss_top_main.ipsec_handler_id];
+
+	if ((if_num >= NSS_MAX_NET_INTERFACES) && (if_num < NSS_MAX_PHYSICAL_INTERFACES)){
+		nss_warning("%px: data register received for invalid interface %d", nss_ctx, if_num);
+		return NULL;
+	}
+
+	/*
+	 * avoid multiple registeration for multiple tunnels
+	 */
+	if (nss_ctx->subsys_dp_register[if_num].cb) {
+		return nss_ctx;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, cb, NULL, NULL, netdev, features);
+
+	if (nss_top_main.ipsec_handler_id == 1) {
+		nss_ctx0 = &nss_top_main.nss[0];
+
+		nss_core_register_subsys_dp(nss_ctx0, if_num, cb, NULL, NULL, netdev, features);
+	}
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_ipsec_data_register);
+
+/*
+ * nss_ipsec_data_unregister()
+ * 	unregister a data callback routine
+ */
+void nss_ipsec_data_unregister(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx0;
+
+	if ((if_num >= NSS_MAX_NET_INTERFACES) && (if_num < NSS_MAX_PHYSICAL_INTERFACES)){
+		nss_warning("%px: data unregister received for invalid interface %d", nss_ctx, if_num);
+		return;
+	}
+
+	if (nss_top_main.ipsec_handler_id == 1) {
+		nss_ctx0 = &nss_top_main.nss[0];
+
+		nss_core_unregister_subsys_dp(nss_ctx0, if_num);
+	}
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_ipsec_data_unregister);
+
+/*
+ * nss_ipsec_get_encap_interface()
+ * 	Get the NSS interface number for encap message
+ */
+int32_t nss_ipsec_get_encap_interface(void)
+{
+	return NSS_IPSEC_ENCAP_INTERFACE_NUM;
+}
+EXPORT_SYMBOL(nss_ipsec_get_encap_interface);
+
+/*
+ * nss_ipsec_get_decap_interface()
+ * 	Get the NSS interface number for decap message
+ */
+int32_t nss_ipsec_get_decap_interface(void)
+{
+	return NSS_IPSEC_DECAP_INTERFACE_NUM;
+}
+EXPORT_SYMBOL(nss_ipsec_get_decap_interface);
+
+/*
+ * nss_ipsec_get_data_interface()
+ * 	Get the NSS interface number used for data path
+ */
+int32_t nss_ipsec_get_data_interface(void)
+{
+	return NSS_IPSEC_DATA_INTERFACE_NUM;
+}
+EXPORT_SYMBOL(nss_ipsec_get_data_interface);
+
+/*
+ * nss_ipsec_get_context()
+ * 	Get NSS context instance for IPsec handle
+ */
+struct nss_ctx_instance *nss_ipsec_get_context(void)
+{
+	return &nss_top_main.nss[nss_top_main.ipsec_handler_id];
+}
+EXPORT_SYMBOL(nss_ipsec_get_context);
+
+/*
+ * nss_ipsec_get_ifnum()
+ *	Return IPsec interface number with coreid.
+ */
+int32_t nss_ipsec_get_ifnum(int32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ipsec_get_context();
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	return NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_ipsec_get_ifnum);
+
+/*
+ * nss_ipsec_ppe_port_config()
+ *	Configure PPE port for IPsec inline
+ */
+bool nss_ipsec_ppe_port_config(struct nss_ctx_instance *nss_ctx, struct net_device *netdev,
+					uint32_t if_num, uint32_t vsi_num)
+{
+#ifdef NSS_PPE_SUPPORTED
+	if_num = NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+
+	if (nss_ppe_tx_ipsec_config_msg(if_num, vsi_num, netdev->mtu, netdev->mtu) != NSS_TX_SUCCESS) {
+		nss_warning("%px: Failed to configure PPE IPsec port", nss_ctx);
+		return false;
+	}
+
+	return true;
+#else
+	return false;
+#endif
+}
+EXPORT_SYMBOL(nss_ipsec_ppe_port_config);
+
+/*
+ * nss_ipsec_ppe_mtu_update()
+ *	Update PPE MTU for IPsec inline
+ */
+bool nss_ipsec_ppe_mtu_update(struct nss_ctx_instance *nss_ctx, uint32_t if_num, uint16_t mtu, uint16_t mru)
+{
+#ifdef NSS_PPE_SUPPORTED
+	if_num = NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+
+	if (nss_ppe_tx_ipsec_mtu_msg(if_num, mtu, mru) != NSS_TX_SUCCESS) {
+		nss_warning("%px: Failed to update PPE MTU for IPsec port", nss_ctx);
+		return false;
+	}
+
+	return true;
+#else
+	return false;
+#endif
+}
+EXPORT_SYMBOL(nss_ipsec_ppe_mtu_update);
+
+/*
+ * nss_ipsec_register_handler()
+ */
+void nss_ipsec_register_handler()
+{
+	struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[nss_top_main.ipsec_handler_id];
+
+	BUILD_BUG_ON(NSS_IPSEC_ENCAP_INTERFACE_NUM < 0);
+	BUILD_BUG_ON(NSS_IPSEC_DECAP_INTERFACE_NUM < 0);
+
+	sema_init(&nss_ipsec.sem, 1);
+	init_completion(&nss_ipsec.complete);
+	atomic_set(&nss_ipsec.resp, NSS_IPSEC_ERROR_TYPE_NONE);
+
+	nss_ctx->nss_top->ipsec_encap_callback = NULL;
+	nss_ctx->nss_top->ipsec_decap_callback = NULL;
+
+	nss_ctx->nss_top->ipsec_encap_ctx = NULL;
+	nss_ctx->nss_top->ipsec_decap_ctx = NULL;
+
+	nss_core_register_handler(nss_ctx, NSS_IPSEC_ENCAP_INTERFACE_NUM, nss_ipsec_msg_handler, NULL);
+	nss_core_register_handler(nss_ctx, NSS_IPSEC_DECAP_INTERFACE_NUM, nss_ipsec_msg_handler, NULL);
+}
+
+/*
+ * nss_ipsec_msg_init()
+ *	Initialize ipsec message.
+ */
+void nss_ipsec_msg_init(struct nss_ipsec_msg *nim, uint16_t if_num, uint32_t type, uint32_t len,
+			nss_ipsec_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&nim->cm, if_num, type, len, (void *)cb, app_data);
+}
+EXPORT_SYMBOL(nss_ipsec_msg_init);
diff --git a/qca-nss-drv/nss_ipsec_cmn.c b/qca-nss-drv/nss_ipsec_cmn.c
new file mode 100644
index 0000000..c5f520d
--- /dev/null
+++ b/qca-nss-drv/nss_ipsec_cmn.c
@@ -0,0 +1,525 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_dynamic_interface.h"
+#include "nss_ipsec_cmn.h"
+#include "nss_ppe.h"
+#include "nss_ipsec_cmn_log.h"
+#include "nss_ipsec_cmn_stats.h"
+#include "nss_ipsec_cmn_strings.h"
+
+#define NSS_IPSEC_CMN_TX_TIMEOUT 3000 /* 3 Seconds */
+#define NSS_IPSEC_CMN_INTERFACE_MAX_LONG BITS_TO_LONGS(NSS_MAX_NET_INTERFACES)
+
+/*
+ * Private data structure for handling synchronous messaging.
+ */
+static struct nss_ipsec_cmn_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	struct nss_ipsec_cmn_msg nicm;
+	unsigned long if_map[NSS_IPSEC_CMN_INTERFACE_MAX_LONG];
+} ipsec_cmn_pvt;
+
+/*
+ * nss_ipsec_cmn_verify_ifnum()
+ *	Verify if the interface number is a IPsec interface.
+ */
+static bool nss_ipsec_cmn_verify_ifnum(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	enum nss_dynamic_interface_type type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+
+	if (if_num == NSS_IPSEC_CMN_INTERFACE)
+		return true;
+
+	switch (type) {
+	case NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_INNER:
+	case NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_OUTER:
+	case NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_MDATA_INNER:
+	case NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_MDATA_OUTER:
+	case NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_REDIRECT:
+		return true;
+
+	default:
+		return false;
+	}
+
+	return false;
+}
+
+/*
+ * nss_ipsec_cmn_msg_handler()
+ *	Handle NSS -> HLOS messages for IPSEC tunnel.
+ */
+static void nss_ipsec_cmn_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, void *app_data)
+{
+	nss_ipsec_cmn_msg_callback_t cb;
+	struct nss_ipsec_cmn_msg *nim;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	/*
+	 * Trace messages.
+	 */
+	nim = (struct nss_ipsec_cmn_msg *)ncm;
+	nss_ipsec_cmn_log_rx_msg(nim);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >=  NSS_IPSEC_CMN_MSG_TYPE_MAX) {
+		nss_warning("%px: Invalid message type(%u) for interface(%u)\n", nss_ctx, ncm->type, ncm->interface);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_ipsec_cmn_msg)) {
+		nss_warning("%px: Invalid message length(%d)\n", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	if (ncm->type == NSS_IPSEC_CMN_MSG_TYPE_CTX_SYNC) {
+		nss_ipsec_cmn_stats_sync(nss_ctx, ncm);
+		nss_ipsec_cmn_stats_notify(nss_ctx, ncm->interface);
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, ipsec_cmn sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->nss_rx_interface_handlers[ncm->interface].app_data;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Callback
+	 */
+	cb = (nss_ipsec_cmn_msg_callback_t)ncm->cb;
+	app_data = (void *)ncm->app_data;
+
+	/*
+	 * Call IPsec message callback
+	 */
+	if (!cb) {
+		nss_warning("%px: No callback for IPsec interface %d\n", nss_ctx, ncm->interface);
+		return;
+	}
+
+	nss_trace("%px: calling ipsecsmgr message handler(%u)\n", nss_ctx, ncm->interface);
+	cb(app_data, ncm);
+}
+
+/*
+ * nss_ipsec_cmn_sync_resp()
+ *	Callback to handle the completion of HLOS-->NSS messages.
+ */
+static void nss_ipsec_cmn_sync_resp(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_ipsec_cmn_msg *pvt_msg = app_data;
+	struct nss_ipsec_cmn_msg *resp_msg = container_of(ncm, struct nss_ipsec_cmn_msg, cm);
+
+	/*
+	 * Copy response message to pvt message
+	 */
+	memcpy(pvt_msg, resp_msg, sizeof(*resp_msg));
+
+	/*
+	 * Write memory barrier
+	 */
+	smp_wmb();
+
+	complete(&ipsec_cmn_pvt.complete);
+}
+
+/*
+ * nss_ipsec_cmn_ifmap_get()
+ *	Return IPsec common active interfaces map.
+ */
+unsigned long *nss_ipsec_cmn_ifmap_get(void)
+{
+	return ipsec_cmn_pvt.if_map;
+}
+
+/*
+ * nss_ipsec_cmn_get_context()
+ *	Retrieve context for IPSEC redir.
+ */
+struct nss_ctx_instance *nss_ipsec_cmn_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.ipsec_handler_id];
+}
+EXPORT_SYMBOL(nss_ipsec_cmn_get_context);
+
+/*
+ * nss_ipsec_cmn_get_ifnum_with_coreid()
+ *	Return IPsec interface number with coreid.
+ */
+uint32_t nss_ipsec_cmn_get_ifnum_with_coreid(int32_t ifnum)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ipsec_cmn_get_context();
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	return NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, ifnum);
+}
+EXPORT_SYMBOL(nss_ipsec_cmn_get_ifnum_with_coreid);
+
+/*
+ * nss_ipsec_cmn_msg_init()
+ *	Initialize message
+ */
+void nss_ipsec_cmn_msg_init(struct nss_ipsec_cmn_msg *nim, uint16_t if_num, enum nss_ipsec_cmn_msg_type type,
+				uint16_t len, nss_ipsec_cmn_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&nim->cm, if_num, type, len, cb, app_data);
+}
+EXPORT_SYMBOL(nss_ipsec_cmn_msg_init);
+
+/*
+ * nss_ipsec_cmn_tx_msg()
+ *	Transmit a IPSEC message to NSS FW.
+ */
+nss_tx_status_t nss_ipsec_cmn_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_ipsec_cmn_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace messages.
+	 */
+	nss_ipsec_cmn_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (ncm->type >= NSS_IPSEC_CMN_MSG_TYPE_MAX) {
+		nss_warning("%px: Invalid message type(%u)\n", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	if (!nss_ipsec_cmn_verify_ifnum(nss_ctx, ncm->interface)) {
+		nss_warning("%px: Invalid message interface(%u)\n", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_ipsec_cmn_msg)) {
+		nss_warning("%px: Invalid message length(%u)\n", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_ipsec_cmn_tx_msg);
+
+/*
+ * nss_ipsec_cmn_tx_msg_sync()
+ *	Transmit a IPSEC redir message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_ipsec_cmn_tx_msg_sync(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+					enum nss_ipsec_cmn_msg_type type, uint16_t len,
+					struct nss_ipsec_cmn_msg *nicm)
+{
+	struct nss_ipsec_cmn_msg *local_nicm = &ipsec_cmn_pvt.nicm;
+	nss_tx_status_t status;
+	int ret = 0;
+
+	/*
+	 * Length of the message should be the based on type
+	 */
+	if (len > sizeof(struct nss_ipsec_cmn_msg)) {
+		nss_warning("%px: Invalid message length(%u), type (%d), I/F(%u)\n", nss_ctx, len, type, if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	down(&ipsec_cmn_pvt.sem);
+
+	/*
+	 * We need to copy the message content into the actual message
+	 * to be sent to NSS
+	 */
+	memset(local_nicm, 0, sizeof(*local_nicm));
+
+	nss_ipsec_cmn_msg_init(local_nicm, if_num, type, len, nss_ipsec_cmn_sync_resp, local_nicm);
+	memcpy(&local_nicm->msg, &nicm->msg, len);
+
+	status = nss_ipsec_cmn_tx_msg(nss_ctx, local_nicm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Failed to send message\n", nss_ctx);
+		goto done;
+	}
+
+	ret = wait_for_completion_timeout(&ipsec_cmn_pvt.complete, msecs_to_jiffies(NSS_IPSEC_CMN_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: Failed to receive response, timeout(%d)\n", nss_ctx, ret);
+		status = NSS_TX_FAILURE_NOT_READY;
+		goto done;
+	}
+
+	/*
+	 * Read memory barrier
+	 */
+	smp_rmb();
+
+	if (local_nicm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		status = NSS_TX_FAILURE;
+		nicm->cm.response = local_nicm->cm.response;
+		nicm->cm.error = local_nicm->cm.error;
+		goto done;
+	}
+
+	/*
+	 * Copy the message received
+	 */
+	memcpy(&nicm->msg, &local_nicm->msg, len);
+
+done:
+	up(&ipsec_cmn_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_ipsec_cmn_tx_msg_sync);
+
+/*
+ * nss_ipsec_cmn_tx_buf()
+ *	Send packet to IPsec interface in NSS.
+ */
+nss_tx_status_t nss_ipsec_cmn_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, uint32_t if_num)
+{
+	nss_trace("%px: Send to IPsec I/F(%u), skb(%px)\n", nss_ctx, if_num, os_buf);
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_ipsec_cmn_verify_ifnum(nss_ctx, if_num)) {
+		nss_warning("%px: Interface number(%d) is not IPSec type\n", nss_ctx, if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_packet(nss_ctx, os_buf, if_num, H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+EXPORT_SYMBOL(nss_ipsec_cmn_tx_buf);
+
+/*
+ * nss_ipsec_cmn_register_if()
+ *	Register dynamic node for IPSEC redir.
+ */
+struct nss_ctx_instance *nss_ipsec_cmn_register_if(uint32_t if_num, struct net_device *netdev,
+						nss_ipsec_cmn_data_callback_t cb_data,
+						nss_ipsec_cmn_msg_callback_t cb_msg,
+						uint32_t features, enum nss_dynamic_interface_type type, void *app_ctx)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ipsec_cmn_get_context();
+	uint32_t status;
+
+	if (!nss_ipsec_cmn_verify_ifnum(nss_ctx, if_num)) {
+		nss_warning("%px: Invalid IPsec interface(%u)\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	if (nss_ctx->subsys_dp_register[if_num].ndev) {
+		nss_warning("%px: Failed find free slot for IPsec NSS I/F:%u\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+#ifdef NSS_DRV_PPE_ENABLE
+	if (features & NSS_IPSEC_CMN_FEATURE_INLINE_ACCEL)
+		nss_ppe_tx_ipsec_add_intf_msg(nss_ipsec_cmn_get_ifnum_with_coreid(if_num));
+#endif
+
+	/*
+	 * Registering handler for sending tunnel interface msgs to NSS.
+	 */
+	status = nss_core_register_handler(nss_ctx, if_num, nss_ipsec_cmn_msg_handler, app_ctx);
+	if (status != NSS_CORE_STATUS_SUCCESS){
+		nss_warning("%px: Failed to register message handler for IPsec NSS I/F:%u\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	status = nss_core_register_msg_handler(nss_ctx, if_num, cb_msg);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_core_unregister_handler(nss_ctx, if_num);
+		nss_warning("%px: Failed to register message handler for IPsec NSS I/F:%u\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, cb_data, NULL, app_ctx, netdev, features);
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num, type);
+
+	/*
+	 * Atomically set the bitmap for the interface number
+	 */
+	set_bit(if_num, ipsec_cmn_pvt.if_map);
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_ipsec_cmn_register_if);
+
+/*
+ * nss_ipsec_cmn_unregister_if()
+ *	Unregister dynamic node for IPSEC redir.
+ */
+bool nss_ipsec_cmn_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ipsec_cmn_get_context();
+	struct net_device *dev;
+	uint32_t status;
+
+	nss_assert(nss_ctx);
+
+	if (!nss_ipsec_cmn_verify_ifnum(nss_ctx, if_num)) {
+		nss_warning("%px: Invalid IPsec interface(%u)\n", nss_ctx, if_num);
+		return false;
+	}
+
+	dev = nss_cmn_get_interface_dev(nss_ctx, if_num);
+	if (!dev) {
+		nss_warning("%px: Failed to find registered netdev for IPsec NSS I/F:%u\n", nss_ctx, if_num);
+		return false;
+	}
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	/*
+	 * Atomically clear the bitmap for the interface number
+	 */
+	clear_bit(if_num, ipsec_cmn_pvt.if_map);
+
+	status = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Failed to unregister handler for IPsec NSS I/F:%u\n", nss_ctx, if_num);
+		return false;
+	}
+
+	status = nss_core_unregister_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Failed to unregister handler for IPsec NSS I/F:%u\n", nss_ctx, if_num);
+		return false;
+	}
+
+	return true;
+}
+EXPORT_SYMBOL(nss_ipsec_cmn_unregister_if);
+
+/*
+ * nss_ipsec_cmn_notify_register()
+ *	Register a handler for notification from NSS firmware.
+ */
+struct nss_ctx_instance *nss_ipsec_cmn_notify_register(uint32_t if_num, nss_ipsec_cmn_msg_callback_t cb, void *app_data)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ipsec_cmn_get_context();
+	uint32_t ret;
+
+	BUG_ON(!nss_ctx);
+
+	ret = nss_core_register_handler(nss_ctx, if_num, nss_ipsec_cmn_msg_handler, app_data);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to register event handler for interface(%u)\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	ret = nss_core_register_msg_handler(nss_ctx, if_num, cb);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_core_unregister_handler(nss_ctx, if_num);
+		nss_warning("%px: Failed to register message handler for IPsec NSS I/F:%u\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_ipsec_cmn_notify_register);
+
+/*
+ * nss_ipsec_cmn_notify_unregister()
+ * 	unregister the IPsec notifier for the given interface number (if_num)
+ */
+void nss_ipsec_cmn_notify_unregister(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	uint32_t ret;
+
+	if (if_num >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("%px: notify unregister received for invalid interface %d\n", nss_ctx, if_num);
+		return;
+	}
+
+	ret = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to unregister event handler for interface(%u)\n", nss_ctx, if_num);
+		return;
+	}
+
+	ret = nss_core_unregister_handler(nss_ctx, if_num);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to unregister event handler for interface(%u)\n", nss_ctx, if_num);
+		return;
+	}
+}
+EXPORT_SYMBOL(nss_ipsec_cmn_notify_unregister);
+
+/*
+ * nss_ipsec_cmn_ppe_port_config()
+ *	Configure PPE port for IPsec inline
+ */
+bool nss_ipsec_cmn_ppe_port_config(struct nss_ctx_instance *nss_ctx, struct net_device *netdev,
+					uint32_t if_num, uint32_t vsi_num)
+{
+#ifdef NSS_PPE_SUPPORTED
+	if_num = NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+
+	if (nss_ppe_tx_ipsec_config_msg(if_num, vsi_num, netdev->mtu, netdev->mtu) != NSS_TX_SUCCESS) {
+		nss_warning("%px: Failed to configure PPE IPsec port\n", nss_ctx);
+		return false;
+	}
+
+	return true;
+#else
+	return false;
+#endif
+}
+EXPORT_SYMBOL(nss_ipsec_cmn_ppe_port_config);
+
+/*
+ * nss_ipsec_cmn_ppe_mtu_update()
+ *	Update PPE MTU for IPsec inline
+ */
+bool nss_ipsec_cmn_ppe_mtu_update(struct nss_ctx_instance *nss_ctx, uint32_t if_num, uint16_t mtu, uint16_t mru)
+{
+#ifdef NSS_PPE_SUPPORTED
+	if_num = NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+
+	if (nss_ppe_tx_ipsec_mtu_msg(if_num, mtu, mru) != NSS_TX_SUCCESS) {
+		nss_warning("%px: Failed to update PPE MTU for IPsec port\n", nss_ctx);
+		return false;
+	}
+
+	return true;
+#else
+	return false;
+#endif
+}
+EXPORT_SYMBOL(nss_ipsec_cmn_ppe_mtu_update);
+
+/*
+ * nss_ipsec_cmn_register_handler()
+ *	Registering handler for sending msg to base ipsec_cmn node on NSS.
+ */
+void nss_ipsec_cmn_register_handler(void)
+{
+	sema_init(&ipsec_cmn_pvt.sem, 1);
+	init_completion(&ipsec_cmn_pvt.complete);
+	nss_ipsec_cmn_stats_dentry_create();
+	nss_ipsec_cmn_strings_dentry_create();
+}
diff --git a/qca-nss-drv/nss_ipsec_cmn_log.c b/qca-nss-drv/nss_ipsec_cmn_log.c
new file mode 100644
index 0000000..8ae7928
--- /dev/null
+++ b/qca-nss-drv/nss_ipsec_cmn_log.c
@@ -0,0 +1,354 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ipsec_cmn_log.c
+ *	NSS IPSEC logger file.
+ */
+
+#include "nss_core.h"
+
+#define NSS_IPSEC_LOG_IPV4 4
+#define NSS_IPSEC_LOG_IPV6 6
+
+/*
+ * nss_ipsec_cmn_log_msg_types_str
+ *	IPSEC message strings
+ */
+static int8_t *nss_ipsec_cmn_log_msg_types_str[NSS_IPSEC_CMN_MSG_TYPE_MAX] __maybe_unused = {
+	"IPSEC CMN Msg None",
+	"IPSEC CMN Node Config",
+	"IPSEC CMN CTX Config",
+	"IPSEC CMN CTX Sync",
+	"IPSEC CMN SA Create",
+	"IPSEC CMN SA Destroy",
+	"IPSEC CMN SA Sync",
+	"IPSEC CMN Flow Create",
+	"IPSEC CMN Flow Destroy",
+};
+
+/*
+ * nss_ipsec_cmn_log_node_msg_types_str
+ *	IPSEC cmn node message strings
+ */
+static int8_t *nss_ipsec_cmn_log_node_str[] __maybe_unused = {
+	"IPSEC CMN Node DMA Redirect",
+	"IPSEC CMN Node DMA Lookaside",
+	"IPSEC CMN Node Maximum SA",
+};
+
+/*
+ * nss_ipsec_cmn_log_ctx_msg_types_str
+ *	IPSEC cmn ctx message strings
+ */
+static int8_t *nss_ipsec_cmn_log_ctx_str[] __maybe_unused = {
+	"IPSEC CMN CTX Type",
+	"IPSEC CMN CTX Exception Interface",
+};
+
+/*
+ * nss_ipsec_cmn_log_ctx_types_str
+ *	IPSEC cmn context strings
+ */
+static int8_t *nss_ipsec_cmn_ctx_types_str[] __maybe_unused = {
+	"IPSEC CMN CTX NONE",
+	"IPSEC CMN CTX INNER",
+	"IPSEC CMN CTX INNER BOUNCE",
+	"IPSEC CMN CTX OUTER",
+	"IPSEC CMN CTX OUTER BOUNCE",
+	"IPSEC CMN CTX REDIRECT",
+};
+
+/*
+ * nss_ipsec_cmn_log_flow_tuple_str
+ *	IPSEC cmn flow tuple strings
+ */
+static int8_t *nss_ipsec_cmn_log_flow_tuple_str[] __maybe_unused = {
+	"Dest IP",
+	"Src IP",
+	"Spi Index",
+	"Dest Port",
+	"Src Port",
+	"User Pattern",
+	"User Protocol",
+	"IP Version",
+};
+
+/*
+ * nss_ipsec_cmn_log_sa_tuple_str
+ *	IPSEC cmn SA tuple strings
+ */
+static int8_t *nss_ipsec_cmn_log_sa_tuple_str[] __maybe_unused = {
+	"Dest IP",
+	"Src IP",
+	"Spi Index",
+	"Dest Port",
+	"Src Port",
+	"Crypto Index",
+	"Protocol",
+	"IP Version",
+	"Hop Limit",
+};
+
+/*
+ * nss_ipsec_cmn_log_sa_data_str
+ *	IPSEC cmn SA tuple strings
+ */
+static int8_t *nss_ipsec_cmn_log_sa_data_str[] __maybe_unused = {
+	"Sequence Start",
+	"Flags",
+	"Window Size",
+	"DSCP",
+	"DF",
+	"Block Length",
+	"IV length",
+	"ICV length",
+};
+
+/*
+ * nss_ipsec_cmn_log_error_str
+ *	Strings for error types for IPSEC messages
+ */
+static int8_t *nss_ipsec_cmn_log_error_str[NSS_IPSEC_CMN_MSG_ERROR_MAX] __maybe_unused = {
+	"IPSEC No Error",
+	"IPSEC Invalid Context",
+	"IPSEC SA allocation Error",
+	"IPSEC Invalid SA",
+	"IPSEC Duplicate SA",
+	"IPSEC SA is in Use",
+	"IPSEC Error in Flow Allocation",
+	"IPSEC Invalid Flow",
+	"IPSEC Duplicate Flow",
+	"IPSEC Failure to find SA for Flow",
+	"IPSEC Failed to Register Dynamic Interface",
+	"IPSEC Unhandled Message",
+};
+
+/*
+ * nss_ipsec_cmn_log_node_msg()
+ *	Log NSS IPSEC node message.
+ */
+static void nss_ipsec_cmn_log_node_msg(struct nss_ipsec_cmn_msg *nim)
+{
+	struct nss_ipsec_cmn_node *node_msg __maybe_unused = &nim->msg.node;
+
+	nss_trace("%px: NSS IPSEC Node Message:\n"
+		  "%s: %d\n"
+		  "%s: %d\n"
+		  "%s: %d\n", nim,
+		  nss_ipsec_cmn_log_node_str[0], node_msg->dma_redirect,
+		  nss_ipsec_cmn_log_node_str[1], node_msg->dma_lookaside,
+		  nss_ipsec_cmn_log_node_str[2], node_msg->max_sa);
+}
+
+/*
+ * nss_ipsec_cmn_log_ctx_msg()
+ *	Log NSS IPSEC ctx message.
+ */
+static void nss_ipsec_cmn_log_ctx_msg(struct nss_ipsec_cmn_msg *nim)
+{
+	struct nss_ipsec_cmn_ctx *ctx_msg __maybe_unused = &nim->msg.ctx;
+
+	nss_trace("%px: NSS IPSEC CTX Message:\n"
+		  "%s: %s\n"
+		  "%s: %d\n", nim,
+		  nss_ipsec_cmn_log_ctx_str[0], nss_ipsec_cmn_ctx_types_str[ctx_msg->type],
+		  nss_ipsec_cmn_log_ctx_str[1], ctx_msg->except_ifnum);
+}
+
+/*
+ * nss_ipsec_cmn_log_sa_msg()
+ *	Log NSS IPSEC SA message.
+ */
+static void nss_ipsec_cmn_log_sa_msg(struct nss_ipsec_cmn_msg *nim)
+{
+	struct nss_ipsec_cmn_sa *sa_msg __maybe_unused = &nim->msg.sa;
+	struct nss_ipsec_cmn_sa_tuple *tuple = &sa_msg->sa_tuple;
+	struct nss_ipsec_cmn_sa_data *data __maybe_unused = &sa_msg->sa_data;
+
+	nss_trace("%px: NSS IPSEC SA Message:\n", nim);
+
+	if (tuple->ip_ver == 4) {
+		nss_trace("%s: %pI4\n%s: %pI4\n",
+			  nss_ipsec_cmn_log_sa_tuple_str[0], tuple->dest_ip,
+			  nss_ipsec_cmn_log_sa_tuple_str[1], tuple->src_ip);
+	} else {
+		nss_trace("%s: %pI6\n%s: %pI6\n",
+			  nss_ipsec_cmn_log_sa_tuple_str[0], tuple->dest_ip,
+			  nss_ipsec_cmn_log_sa_tuple_str[1], tuple->src_ip);
+	}
+
+	nss_trace( "%s: %x\n%s: %d\n%s: %d\n%s: %d\n"
+		  "%s: %d\n%s: %d\n%s: %d\n"
+		  "%s: %d\n%s: %x\n%s: %d\n%s: %d\n"
+		  "%s: %d\n%s: %d\n%s: %d\n%s: %d\n",
+		  nss_ipsec_cmn_log_sa_tuple_str[2], tuple->spi_index,
+		  nss_ipsec_cmn_log_sa_tuple_str[3], tuple->dest_port,
+		  nss_ipsec_cmn_log_sa_tuple_str[4], tuple->src_port,
+		  nss_ipsec_cmn_log_sa_tuple_str[5], tuple->crypto_index,
+		  nss_ipsec_cmn_log_sa_tuple_str[6], tuple->protocol,
+		  nss_ipsec_cmn_log_sa_tuple_str[7], tuple->ip_ver,
+		  nss_ipsec_cmn_log_sa_tuple_str[8], tuple->hop_limit,
+
+		  nss_ipsec_cmn_log_sa_data_str[0], data->seq_start,
+		  nss_ipsec_cmn_log_sa_data_str[1], data->flags,
+		  nss_ipsec_cmn_log_sa_data_str[2], data->window_size,
+		  nss_ipsec_cmn_log_sa_data_str[3], data->dscp,
+		  nss_ipsec_cmn_log_sa_data_str[4], data->df,
+		  nss_ipsec_cmn_log_sa_data_str[5], data->blk_len,
+		  nss_ipsec_cmn_log_sa_data_str[6], data->iv_len,
+		  nss_ipsec_cmn_log_sa_data_str[7], data->icv_len);
+
+}
+
+/*
+ * nss_ipsec_cmn_log_flow_msg()
+ *	Log NSS IPSEC Flow message.
+ */
+static void nss_ipsec_cmn_log_flow_msg(struct nss_ipsec_cmn_msg *nim)
+{
+	struct nss_ipsec_cmn_flow *flow_msg __maybe_unused = &nim->msg.flow;
+	struct nss_ipsec_cmn_flow_tuple *flow = &flow_msg->flow_tuple;
+	struct nss_ipsec_cmn_sa_tuple *sa = &flow_msg->sa_tuple;
+
+	nss_trace("%px: NSS IPSEC Flow Message:\n", nim);
+
+	if (sa->ip_ver == 4) {
+		nss_trace("%s: %pI4\n%s: %pI4\n",
+			  nss_ipsec_cmn_log_sa_tuple_str[0], sa->dest_ip,
+			  nss_ipsec_cmn_log_sa_tuple_str[1], sa->src_ip);
+	} else {
+		nss_trace("%s: %pI6\n%s: %pI6\n",
+			  nss_ipsec_cmn_log_sa_tuple_str[0], sa->dest_ip,
+			  nss_ipsec_cmn_log_sa_tuple_str[1], sa->src_ip);
+	}
+
+	if (flow->ip_ver == 4) {
+		nss_trace("%s: %pI4\n%s: %pI4\n",
+			  nss_ipsec_cmn_log_sa_tuple_str[0], flow->dest_ip,
+			  nss_ipsec_cmn_log_sa_tuple_str[1], flow->src_ip);
+	} else {
+		nss_trace("%s: %pI6\n%s: %pI6\n",
+			  nss_ipsec_cmn_log_sa_tuple_str[0], flow->dest_ip,
+			  nss_ipsec_cmn_log_sa_tuple_str[1], flow->src_ip);
+	}
+
+	nss_trace( "%s: %x\n%s: %d\n%s: %d\n%s: %d\n"
+		  "%s: %d\n",
+		  nss_ipsec_cmn_log_flow_tuple_str[2], flow->spi_index,
+		  nss_ipsec_cmn_log_flow_tuple_str[3], flow->dst_port,
+		  nss_ipsec_cmn_log_flow_tuple_str[4], flow->src_port,
+		  nss_ipsec_cmn_log_flow_tuple_str[5], flow->user_pattern,
+		  nss_ipsec_cmn_log_flow_tuple_str[6], flow->protocol);
+
+	nss_trace( "%s: %x\n%s: %d\n%s: %d\n%s: %d\n"
+		  "%s: %d\n%s: %d\n%s: %d\n",
+		  nss_ipsec_cmn_log_sa_tuple_str[2], sa->spi_index,
+		  nss_ipsec_cmn_log_sa_tuple_str[3], sa->dest_port,
+		  nss_ipsec_cmn_log_sa_tuple_str[4], sa->src_port,
+		  nss_ipsec_cmn_log_sa_tuple_str[5], sa->crypto_index,
+		  nss_ipsec_cmn_log_sa_tuple_str[6], sa->protocol,
+		  nss_ipsec_cmn_log_sa_tuple_str[7], sa->ip_ver,
+		  nss_ipsec_cmn_log_sa_tuple_str[8], sa->hop_limit);
+}
+
+/*
+ * nss_ipsec_cmn_log_verbose()
+ *	Log message contents.
+ */
+static void nss_ipsec_cmn_log_verbose(struct nss_ipsec_cmn_msg *nim)
+{
+	switch (nim->cm.type) {
+	case NSS_IPSEC_CMN_MSG_TYPE_NODE_CONFIG:
+		nss_ipsec_cmn_log_node_msg(nim);
+		break;
+
+	case NSS_IPSEC_CMN_MSG_TYPE_CTX_CONFIG:
+		nss_ipsec_cmn_log_ctx_msg(nim);
+		break;
+
+	case NSS_IPSEC_CMN_MSG_TYPE_SA_CREATE:
+	case NSS_IPSEC_CMN_MSG_TYPE_SA_DESTROY:
+		nss_ipsec_cmn_log_sa_msg(nim);
+		break;
+
+	case NSS_IPSEC_CMN_MSG_TYPE_FLOW_CREATE:
+	case NSS_IPSEC_CMN_MSG_TYPE_FLOW_DESTROY:
+		nss_ipsec_cmn_log_flow_msg(nim);
+		break;
+
+	case NSS_IPSEC_CMN_MSG_TYPE_CTX_SYNC:
+	case NSS_IPSEC_CMN_MSG_TYPE_SA_SYNC:
+		/*
+		 * No log for these valid messages.
+		 */
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", nim);
+		break;
+	}
+}
+
+/*
+ * nss_ipsec_cmn_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_ipsec_cmn_log_tx_msg(struct nss_ipsec_cmn_msg *nim)
+{
+	if (nim->cm.type >= NSS_IPSEC_CMN_MSG_TYPE_MAX) {
+		nss_warning("%px: Invalid message type\n", nim);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nim, nim->cm.type, nss_ipsec_cmn_log_msg_types_str[nim->cm.type]);
+	nss_ipsec_cmn_log_verbose(nim);
+}
+
+/*
+ * nss_ipsec_cmn_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_ipsec_cmn_log_rx_msg(struct nss_ipsec_cmn_msg *nim)
+{
+	if (nim->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", nim);
+		return;
+	}
+
+	if (nim->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nim->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nim, nim->cm.type,
+			nss_ipsec_cmn_log_msg_types_str[nim->cm.type],
+			nim->cm.response, nss_cmn_response_str[nim->cm.response]);
+		goto verbose;
+	}
+
+	if (nim->cm.error >= NSS_IPSEC_CMN_MSG_ERROR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			nim, nim->cm.type, nss_ipsec_cmn_log_msg_types_str[nim->cm.type],
+			nim->cm.response, nss_cmn_response_str[nim->cm.response],
+			nim->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		nim, nim->cm.type, nss_ipsec_cmn_log_msg_types_str[nim->cm.type],
+		nim->cm.response, nss_cmn_response_str[nim->cm.response],
+		nim->cm.error, nss_ipsec_cmn_log_error_str[nim->cm.error]);
+
+verbose:
+	nss_ipsec_cmn_log_verbose(nim);
+}
diff --git a/qca-nss-drv/nss_ipsec_cmn_log.h b/qca-nss-drv/nss_ipsec_cmn_log.h
new file mode 100644
index 0000000..d99c8be
--- /dev/null
+++ b/qca-nss-drv/nss_ipsec_cmn_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_IPSEC_CMN_LOG_H__
+#define __NSS_IPSEC_CMN_LOG_H__
+
+/*
+ * nss_ipsec_cmn_log.h
+ *	NSS Crypto Log Header File
+ */
+
+/*
+ * nss_ipsec_cmn_log_tx_msg
+ *	Logs a ipsec message that is sent to the NSS firmware.
+ */
+void nss_ipsec_cmn_log_tx_msg(struct nss_ipsec_cmn_msg *nim);
+
+/*
+ * nss_ipsec_cmn_log_rx_msg
+ *	Logs a ipsec message that is received from the NSS firmware.
+ */
+void nss_ipsec_cmn_log_rx_msg(struct nss_ipsec_cmn_msg *nim);
+
+#endif /* __NSS_IPSEC_CMN_LOG_H__ */
diff --git a/qca-nss-drv/nss_ipsec_cmn_stats.c b/qca-nss-drv/nss_ipsec_cmn_stats.c
new file mode 100644
index 0000000..192f229
--- /dev/null
+++ b/qca-nss-drv/nss_ipsec_cmn_stats.c
@@ -0,0 +1,219 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_ipsec_cmn.h"
+#include "nss_ipsec_cmn_stats.h"
+#include "nss_ipsec_cmn_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_ipsec_cmn_stats_notifier);
+
+/*
+ * Spinlock to protect IPsec common statistics update/read
+ */
+DEFINE_SPINLOCK(nss_ipsec_cmn_stats_lock);
+
+unsigned long *nss_ipsec_cmn_ifmap_get(void);
+const char *nss_ipsec_cmn_stats_iface_type(enum nss_dynamic_interface_type type);
+
+/*
+ * nss_ipsec_cmn_stats
+ *	ipsec common statistics
+ */
+uint64_t nss_ipsec_cmn_stats[NSS_MAX_NET_INTERFACES][NSS_IPSEC_CMN_STATS_MAX];
+
+/*
+ * nss_ipsec_cmn_stats_read()
+ *	Read ipsec_cmn node statistics.
+ */
+static ssize_t nss_ipsec_cmn_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	/*
+	 * Max output lines = #stats +
+	 * few blank lines for banner printing + Number of Extra outputlines
+	 * for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_IPSEC_CMN_STATS_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	struct nss_ctx_instance *nss_ctx = nss_ipsec_cmn_get_context();
+	enum nss_dynamic_interface_type type;
+	unsigned long *ifmap;
+	uint64_t *stats_shadow;
+	ssize_t bytes_read = 0;
+	size_t size_wr = 0;
+	uint32_t if_num;
+	int32_t i;
+	int count;
+	char *lbuf;
+
+	ifmap = nss_ipsec_cmn_ifmap_get();
+	count = bitmap_weight(ifmap, NSS_MAX_NET_INTERFACES);
+	if (count) {
+		size_al = size_al * count;
+	}
+
+	lbuf = vzalloc(size_al);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return -ENOMEM;
+	}
+
+	stats_shadow = vzalloc(NSS_IPSEC_CMN_STATS_MAX * 8);
+	if (unlikely(!stats_shadow)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		vfree(lbuf);
+		return -ENOMEM;
+	}
+
+	/*
+	 * Common node stats for each IPSEC dynamic interface.
+	 */
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "ipsec_cmn stats", NSS_STATS_SINGLE_CORE);
+	for_each_set_bit(if_num, ifmap, NSS_MAX_NET_INTERFACES) {
+
+		type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+		if ((type < NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_INNER) ||
+			(type > NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_REDIRECT)) {
+			continue;
+		}
+
+		spin_lock_bh(&nss_ipsec_cmn_stats_lock);
+		for (i = 0; i < NSS_IPSEC_CMN_STATS_MAX; i++) {
+			stats_shadow[i] = nss_ipsec_cmn_stats[if_num][i];
+		}
+		spin_unlock_bh(&nss_ipsec_cmn_stats_lock);
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n%s if_num:%03u\n",
+					nss_ipsec_cmn_stats_iface_type(type), if_num);
+		size_wr += nss_stats_print("ipsec_cmn", NULL, NSS_STATS_SINGLE_INSTANCE, nss_ipsec_cmn_strings_stats,
+							stats_shadow, NSS_IPSEC_CMN_STATS_MAX, lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	vfree(lbuf);
+	vfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_ipsec_cmn_stats_ops.
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(ipsec_cmn);
+
+/*
+ * nss_ipsec_cmn_stats_sync()
+ *	Update ipsec_cmn node statistics.
+ */
+void nss_ipsec_cmn_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm)
+{
+	struct nss_ipsec_cmn_msg *nicm = (struct nss_ipsec_cmn_msg *)ncm;
+	struct nss_ipsec_cmn_ctx_stats *ndccs = &nicm->msg.ctx_sync.stats;
+	uint64_t *ctx_stats;
+	uint32_t *msg_stats;
+	uint16_t i = 0;
+
+	spin_lock_bh(&nss_ipsec_cmn_stats_lock);
+
+	msg_stats = (uint32_t *)ndccs;
+	ctx_stats = nss_ipsec_cmn_stats[ncm->interface];
+
+	for (i = 0; i < NSS_IPSEC_CMN_STATS_MAX; i++, ctx_stats++, msg_stats++) {
+		*ctx_stats += *msg_stats;
+	}
+
+	spin_unlock_bh(&nss_ipsec_cmn_stats_lock);
+}
+
+/*
+ * nss_ipsec_cmn_stats_iface_type()
+ *	Return a string for each interface type.
+ */
+const char *nss_ipsec_cmn_stats_iface_type(enum nss_dynamic_interface_type type)
+{
+	switch (type) {
+	case NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_INNER:
+		return "ipsec_cmn_inner";
+
+	case NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_MDATA_INNER:
+		return "ipsec_cmn_mdata_inner";
+
+	case NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_OUTER:
+		return "ipsec_cmn_outer";
+
+	case NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_MDATA_OUTER:
+		return "ipsec_cmn_mdata_outer";
+
+	case NSS_DYNAMIC_INTERFACE_TYPE_IPSEC_CMN_REDIRECT:
+		return "ipsec_cmn_redirect";
+
+	default:
+		return "invalid_interface";
+	}
+}
+
+/*
+ * nss_ipsec_cmn_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_ipsec_cmn_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_ipsec_cmn_stats_notification ipsec_cmn_stats;
+
+	spin_lock_bh(&nss_ipsec_cmn_stats_lock);
+	ipsec_cmn_stats.core_id = nss_ctx->id;
+	ipsec_cmn_stats.if_num = if_num;
+	memcpy(ipsec_cmn_stats.stats_ctx, nss_ipsec_cmn_stats[if_num], sizeof(ipsec_cmn_stats.stats_ctx));
+	spin_unlock_bh(&nss_ipsec_cmn_stats_lock);
+
+	atomic_notifier_call_chain(&nss_ipsec_cmn_stats_notifier, NSS_STATS_EVENT_NOTIFY, &ipsec_cmn_stats);
+}
+
+/*
+ * nss_ipsec_cmn_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_ipsec_cmn_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_ipsec_cmn_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_ipsec_cmn_stats_unregister_notifier);
+
+/*
+ * nss_ipsec_cmn_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_ipsec_cmn_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_ipsec_cmn_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_ipsec_cmn_stats_register_notifier);
+
+/*
+ * nss_ipsec_cmn_stats_dentry_create()
+ *	Create ipsec common statistics debug entry.
+ */
+void nss_ipsec_cmn_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("ipsec_cmn", &nss_ipsec_cmn_stats_ops);
+}
diff --git a/qca-nss-drv/nss_ipsec_cmn_stats.h b/qca-nss-drv/nss_ipsec_cmn_stats.h
new file mode 100644
index 0000000..5110568
--- /dev/null
+++ b/qca-nss-drv/nss_ipsec_cmn_stats.h
@@ -0,0 +1,28 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#ifndef __NSS_IPSEC_CMN_STATS_H
+#define __NSS_IPSEC_CMN_STATS_H
+
+#include <nss_cmn.h>
+
+extern void nss_ipsec_cmn_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_ipsec_cmn_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm);
+extern void nss_ipsec_cmn_stats_dentry_create(void);
+
+#endif /* __NSS_IPSEC_CMN_STATS_H */
diff --git a/qca-nss-drv/nss_ipsec_cmn_strings.c b/qca-nss-drv/nss_ipsec_cmn_strings.c
new file mode 100644
index 0000000..bf2cff6
--- /dev/null
+++ b/qca-nss-drv/nss_ipsec_cmn_strings.c
@@ -0,0 +1,82 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_ipsec_cmn_strings.h"
+
+/*
+ * nss_ipsec_cmn_strings_stats
+ *	ipsec common statistics strings.
+ */
+struct nss_stats_info nss_ipsec_cmn_strings_stats[NSS_IPSEC_CMN_STATS_MAX] = {
+	{"rx_pkts",			NSS_STATS_TYPE_COMMON},
+	{"rx_byts",			NSS_STATS_TYPE_COMMON},
+	{"tx_pkts",			NSS_STATS_TYPE_COMMON},
+	{"tx_byts",			NSS_STATS_TYPE_COMMON},
+	{"rx_queue[0]_drops",		NSS_STATS_TYPE_DROP},
+	{"rx_queue[1]_drops",		NSS_STATS_TYPE_DROP},
+	{"rx_queue[2]_drops",		NSS_STATS_TYPE_DROP},
+	{"rx_queue[3]_drops",		NSS_STATS_TYPE_DROP},
+	{"fail_headroom",		NSS_STATS_TYPE_DROP},
+	{"fail_tailroom",		NSS_STATS_TYPE_DROP},
+	{"fail_replay",			NSS_STATS_TYPE_DROP},
+	{"fail_replay_dup",		NSS_STATS_TYPE_DROP},
+	{"fail_replay_win",		NSS_STATS_TYPE_DROP},
+	{"fail_pbuf_crypto",		NSS_STATS_TYPE_DROP},
+	{"fail_queue",			NSS_STATS_TYPE_DROP},
+	{"fail_queue_crypto",		NSS_STATS_TYPE_DROP},
+	{"fail_queue_nexthop",		NSS_STATS_TYPE_DROP},
+	{"fail_pbuf_alloc",		NSS_STATS_TYPE_DROP},
+	{"fail_pbuf_linear",		NSS_STATS_TYPE_DROP},
+	{"fail_pbuf_stats",		NSS_STATS_TYPE_DROP},
+	{"fail_pbuf_align",		NSS_STATS_TYPE_DROP},
+	{"fail_cipher",			NSS_STATS_TYPE_EXCEPTION},
+	{"fail_auth",			NSS_STATS_TYPE_EXCEPTION},
+	{"fail_seq_ovf",		NSS_STATS_TYPE_DROP},
+	{"fail_blk_len",		NSS_STATS_TYPE_DROP},
+	{"fail_hash_len",		NSS_STATS_TYPE_DROP},
+	{"fail_transform",		NSS_STATS_TYPE_DROP},
+	{"fail_crypto",			NSS_STATS_TYPE_DROP},
+	{"fail_cle",			NSS_STATS_TYPE_DROP},
+	{"is_stopped",			NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_ipsec_cmn_strings_read()
+ *	Read ipsec common statistics names
+ */
+static ssize_t nss_ipsec_cmn_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_ipsec_cmn_strings_stats, NSS_IPSEC_CMN_STATS_MAX);
+}
+
+/*
+ * nss_ipsec_cmn_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(ipsec_cmn);
+
+/*
+ * nss_ipsec_cmn_strings_dentry_create()
+ *	Create ipsec common statistics strings debug entry.
+ */
+void nss_ipsec_cmn_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("ipsec_cmn", &nss_ipsec_cmn_strings_ops);
+}
diff --git a/qca-nss-drv/nss_ipsec_cmn_strings.h b/qca-nss-drv/nss_ipsec_cmn_strings.h
new file mode 100644
index 0000000..c22f4c0
--- /dev/null
+++ b/qca-nss-drv/nss_ipsec_cmn_strings.h
@@ -0,0 +1,27 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#ifndef __NSS_IPSEC_CMN_STRINGS_H
+#define __NSS_IPSEC_CMN_STRINGS_H
+
+#include "nss_ipsec_cmn_stats.h"
+
+extern struct nss_stats_info nss_ipsec_cmn_strings_stats[NSS_IPSEC_CMN_STATS_MAX];
+extern void nss_ipsec_cmn_strings_dentry_create(void);
+
+#endif /* __NSS_IPSEC_CMN_STRINGS_H */
diff --git a/qca-nss-drv/nss_ipsec_log.c b/qca-nss-drv/nss_ipsec_log.c
new file mode 100644
index 0000000..2f1570e
--- /dev/null
+++ b/qca-nss-drv/nss_ipsec_log.c
@@ -0,0 +1,205 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ipsec_log.c
+ *	NSS IPSEC logger file.
+ */
+
+#include "nss_core.h"
+
+#define NSS_IPSEC_LOG_IPV4 4
+#define NSS_IPSEC_LOG_IPV6 6
+
+/*
+ * nss_ipsec_log_message_types_str
+ *	IPSEC message strings
+ */
+static int8_t *nss_ipsec_log_message_types_str[NSS_IPSEC_MSG_TYPE_MAX] __maybe_unused = {
+	"IPSEC Msg None",
+	"IPSEC ADD Rule",
+	"IPSEC DEL Rule",
+	"IPSEC Flush Tunnel",
+	"IPSEC SA Stats",
+	"IPSEC Flow Stats",
+	"IPSEC Node Stats",
+	"IPSEC Configure Node",
+};
+
+/*
+ * nss_ipsec_log_error_response_types_str
+ *	Strings for error types for IPSEC messages
+ */
+static int8_t *nss_ipsec_log_error_response_types_str[NSS_IPSEC_ERROR_TYPE_MAX] __maybe_unused = {
+	"IPSEC No Error",
+	"IPSEC Hash Duplicate",
+	"IPSEC Hash Collision",
+	"IPSEC Unhandled Message",
+	"IPSEC Invalid Rule",
+	"IPSEC MAX SA",
+	"IPSEC MAX Flow",
+	"IPSEC Invalid CINDEX",
+	"IPSEC Invalid IP Version",
+};
+
+/*
+ * nss_ipsec_log_rule_msg()
+ *	Log NSS IPSEC rule message.
+ */
+static void nss_ipsec_log_rule_msg(struct nss_ipsec_msg *nim)
+{
+	struct nss_ipsec_rule *nir __maybe_unused = &nim->msg.rule;
+
+	nss_trace("%px: NSS IPSEC Rule Message:\n"
+		"IPSEC ESP SPI Index: %dn"
+		"IPSEC TTL Hop Limit: %dn"
+		"IPSEC IP Version: %x\n"
+		"IPSEC Crypto Index: %d\n"
+		"IPSEC Window Size: %d\n"
+		"IPSEC Cipher Block Len: %d\n"
+		"IPSEC Initialization Vector Length: %d\n"
+		"IPSEC NAT-T Required: %d\n"
+		"IPSEC ICV Length: %d\n"
+		"IPSEC Skip Seq Number: %d\n"
+		"IPSEC Skip ESP Trailer: %d\n"
+		"IPSEC Use Pattern: %d\n"
+		"IPSEC Enable Extended Sequence Number: %d\n"
+		"IPSEC DSCP Value: %d\n"
+		"IPSEC Don't Fragment Flag: %d\n"
+		"IPSEC DSCP Copy %d\n"
+		"IPSEC DF Copy: %d\n"
+		"IPSEC NSS Index: %d\n"
+		"IPSEC SA Index: %d\n",
+		nir, nir->oip.esp_spi,
+		nir->oip.ttl_hop_limit, nir->oip.ip_ver,
+		nir->data.crypto_index, nir->data.window_size,
+		nir->data.cipher_blk_len, nir->data.iv_len,
+		nir->data.nat_t_req, nir->data.esp_icv_len,
+		nir->data.esp_seq_skip, nir->data.esp_tail_skip,
+		nir->data.use_pattern, nir->data.enable_esn,
+		nir->data.dscp, nir->data.df,
+		nir->data.copy_dscp, nir->data.copy_df,
+		nir->index, nir->sa_idx);
+
+	/*
+	 * Continuation of previous log. Different identifiers based on ip_ver
+	 */
+	if (nir->oip.ip_ver == NSS_IPSEC_LOG_IPV6) {
+		nss_trace("IPSEC Destination Address: %pI6\n"
+			"IPSEC Source Address: %pI6\n",
+			nir->oip.dst_addr, nir->oip.src_addr);
+	} else if (nir->oip.ip_ver == NSS_IPSEC_LOG_IPV4) {
+		nss_trace("IPSEC Destination Address: %pI4\n"
+			"IPSEC Source Address: %pI4\n",
+			nir->oip.dst_addr, nir->oip.src_addr);
+	}
+}
+
+/*
+ * nss_ipsec_log_configure_node_msg()
+ *	Log NSS IPSEC configure node message.
+ */
+static void nss_ipsec_log_configure_node_msg(struct nss_ipsec_msg *nim)
+{
+	struct nss_ipsec_configure_node *nicn __maybe_unused = &nim->msg.node;
+	nss_trace("%px: NSS IPSEC Configure Node\n"
+		"IPSEC DMA Redirect: %d\n"
+		"IPSEC DMA Lookaside: %d\n",
+		nicn, nicn->dma_redirect,
+		nicn->dma_lookaside);
+}
+
+/*
+ * nss_ipsec_log_verbose()
+ *	Log message contents.
+ */
+static void nss_ipsec_log_verbose(struct nss_ipsec_msg *nim)
+{
+	switch (nim->cm.type) {
+	case NSS_IPSEC_MSG_TYPE_ADD_RULE:
+	case NSS_IPSEC_MSG_TYPE_DEL_RULE:
+		nss_ipsec_log_rule_msg(nim);
+		break;
+
+	case NSS_IPSEC_MSG_TYPE_CONFIGURE_NODE:
+		nss_ipsec_log_configure_node_msg(nim);
+		break;
+
+	case NSS_IPSEC_MSG_TYPE_NONE:
+	case NSS_IPSEC_MSG_TYPE_FLUSH_TUN:
+	case NSS_IPSEC_MSG_TYPE_SYNC_SA_STATS:
+	case NSS_IPSEC_MSG_TYPE_SYNC_FLOW_STATS:
+	case NSS_IPSEC_MSG_TYPE_SYNC_NODE_STATS:
+		/*
+		 * No log for these valid messages.
+		 */
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", nim);
+		break;
+	}
+}
+
+/*
+ * nss_ipsec_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_ipsec_log_tx_msg(struct nss_ipsec_msg *nim)
+{
+	if (nim->cm.type >= NSS_IPSEC_MSG_TYPE_MAX) {
+		nss_warning("%px: Invalid message type\n", nim);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nim, nim->cm.type, nss_ipsec_log_message_types_str[nim->cm.type]);
+	nss_ipsec_log_verbose(nim);
+}
+
+/*
+ * nss_ipsec_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_ipsec_log_rx_msg(struct nss_ipsec_msg *nim)
+{
+	if (nim->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", nim);
+		return;
+	}
+
+	if (nim->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nim->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nim, nim->cm.type,
+			nss_ipsec_log_message_types_str[nim->cm.type],
+			nim->cm.response, nss_cmn_response_str[nim->cm.response]);
+		goto verbose;
+	}
+
+	if (nim->cm.error >= NSS_IPSEC_ERROR_TYPE_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			nim, nim->cm.type, nss_ipsec_log_message_types_str[nim->cm.type],
+			nim->cm.response, nss_cmn_response_str[nim->cm.response],
+			nim->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		nim, nim->cm.type, nss_ipsec_log_message_types_str[nim->cm.type],
+		nim->cm.response, nss_cmn_response_str[nim->cm.response],
+		nim->cm.error, nss_ipsec_log_error_response_types_str[nim->cm.error]);
+
+verbose:
+	nss_ipsec_log_verbose(nim);
+}
diff --git a/qca-nss-drv/nss_ipsec_log.h b/qca-nss-drv/nss_ipsec_log.h
new file mode 100644
index 0000000..5342c20
--- /dev/null
+++ b/qca-nss-drv/nss_ipsec_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_IPSEC_LOG_H__
+#define __NSS_IPSEC_LOG_H__
+
+/*
+ * nss_ipsec_log.h
+ *	NSS Crypto Log Header File
+ */
+
+/*
+ * nss_ipsec_log_tx_msg
+ *	Logs a ipsec message that is sent to the NSS firmware.
+ */
+void nss_ipsec_log_tx_msg(struct nss_ipsec_msg *nim);
+
+/*
+ * nss_ipsec_log_rx_msg
+ *	Logs a ipsec message that is received from the NSS firmware.
+ */
+void nss_ipsec_log_rx_msg(struct nss_ipsec_msg *nim);
+
+#endif /* __NSS_IPSEC_LOG_H__ */
diff --git a/qca-nss-drv/nss_ipv4.c b/qca-nss-drv/nss_ipv4.c
new file mode 100644
index 0000000..e1e0452
--- /dev/null
+++ b/qca-nss-drv/nss_ipv4.c
@@ -0,0 +1,782 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ipv4.c
+ *	NSS IPv4 APIs
+ */
+#include <linux/sysctl.h>
+#include "nss_dscp_map.h"
+#include "nss_ipv4_stats.h"
+#include "nss_ipv4_strings.h"
+
+#define NSS_IPV4_TX_MSG_TIMEOUT 1000	/* 1 sec timeout for IPv4 messages */
+
+/*
+ * Private data structure for ipv4 configuration
+ */
+struct nss_ipv4_pvt {
+	struct semaphore sem;		/* Semaphore structure */
+	struct completion complete;	/* completion structure */
+	int response;			/* Response from FW */
+	void *cb;			/* Original cb for sync msgs */
+	void *app_data;			/* Original app_data for sync msgs */
+} nss_ipv4_pvt;
+
+/*
+ * Private data structure for ipv4 connection information.
+ */
+struct nss_ipv4_conn_table_info {
+	uint32_t ce_table_size;		/* Size of connection table entry in NSS FW */
+	uint32_t cme_table_size;	/* Size of connection match table entry in NSS FW */
+	unsigned long ce_mem;		/* Start address for connection entry table */
+	unsigned long cme_mem;		/* Start address for connection match entry table */
+} nss_ipv4_ct_info;
+
+int nss_ipv4_conn_cfg = NSS_DEFAULT_NUM_CONN;
+int nss_ipv4_accel_mode_cfg __read_mostly = 1;
+
+static struct nss_dscp_map_entry mapping[NSS_DSCP_MAP_ARRAY_SIZE];
+
+/*
+ * Callback for conn_sync_many request message.
+ */
+nss_ipv4_msg_callback_t nss_ipv4_conn_sync_many_msg_cb = NULL;
+
+/*
+ * nss_ipv4_dscp_map_usage()
+ *	Help function shows the usage of the command.
+ */
+static inline void nss_ipv4_dscp_map_usage(void)
+{
+	nss_info_always("\nUsage:\n");
+	nss_info_always("echo <dscp> <action> <prio> > /proc/sys/dev/nss/ipv4cfg/ipv4_dscp_map\n\n");
+	nss_info_always("dscp[0-63] action[0-%u] prio[0-%u]:\n\n",
+				NSS_IPV4_DSCP_MAP_ACTION_MAX - 1,
+				NSS_DSCP_MAP_PRIORITY_MAX - 1);
+}
+
+/*
+ * nss_ipv4_get_total_conn_count()
+ *	 Returns the sum of IPv4 and IPv6 connections.
+ */
+static uint32_t nss_ipv4_get_total_conn_count(int ipv4_num_conn)
+{
+
+#ifdef NSS_DRV_IPV6_ENABLE
+	return ipv4_num_conn + nss_ipv6_conn_cfg;
+#else
+	return ipv4_num_conn;
+#endif
+}
+
+/*
+ * nss_ipv4_rx_msg_handler()
+ *	Handle NSS -> HLOS messages for IPv4 bridge/route
+ */
+static void nss_ipv4_rx_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_ipv4_msg *nim = (struct nss_ipv4_msg *)ncm;
+	nss_ipv4_msg_callback_t cb;
+
+	BUG_ON(ncm->interface != NSS_IPV4_RX_INTERFACE);
+
+	/*
+	 * Sanity check the message type
+	 */
+	if (ncm->type >= NSS_IPV4_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_ipv4_msg)) {
+		nss_warning("%px: message length is invalid: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_ipv4_log_rx_msg(nim);
+
+	switch (nim->cm.type) {
+	case NSS_IPV4_RX_NODE_STATS_SYNC_MSG:
+		/*
+		 * Update driver statistics on node sync and send statistics notifications to the registered modules.
+		 */
+		nss_ipv4_stats_node_sync(nss_ctx, &nim->msg.node_stats);
+		nss_ipv4_stats_notify(nss_ctx);
+		break;
+
+	case NSS_IPV4_RX_CONN_STATS_SYNC_MSG:
+		/*
+		 * Update driver statistics on connection sync.
+		 */
+		nss_ipv4_stats_conn_sync(nss_ctx, &nim->msg.conn_stats);
+		break;
+
+	case NSS_IPV4_TX_CONN_STATS_SYNC_MANY_MSG:
+		/*
+		 * Update driver statistics on connection sync many.
+		 */
+		nss_ipv4_stats_conn_sync_many(nss_ctx, &nim->msg.conn_stats_many);
+		ncm->cb = (nss_ptr_t)nss_ipv4_conn_sync_many_msg_cb;
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, IPv4 sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (nim->cm.response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->ipv4_callback;
+		ncm->app_data = (nss_ptr_t)nss_ctx->nss_top->ipv4_ctx;
+	}
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * Callback
+	 */
+	cb = (nss_ipv4_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, nim);
+}
+
+/*
+ * nss_ipv4_tx_sync_callback()
+ *	Callback to handle the completion of synchronous tx messages.
+ */
+static void nss_ipv4_tx_sync_callback(void *app_data, struct nss_ipv4_msg *nim)
+{
+	nss_ipv4_msg_callback_t callback = (nss_ipv4_msg_callback_t)nss_ipv4_pvt.cb;
+	void *data = nss_ipv4_pvt.app_data;
+
+	nss_ipv4_pvt.cb = NULL;
+	nss_ipv4_pvt.app_data = NULL;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("ipv4 error response %d\n", nim->cm.response);
+		nss_ipv4_pvt.response = NSS_TX_FAILURE;
+	} else {
+		nss_ipv4_pvt.response = NSS_TX_SUCCESS;
+	}
+
+	if (callback) {
+		callback(data, nim);
+	}
+
+	complete(&nss_ipv4_pvt.complete);
+}
+
+/*
+ * nss_ipv4_dscp_action_get()
+ *	Gets the action mapped to dscp.
+ */
+enum nss_ipv4_dscp_map_actions nss_ipv4_dscp_action_get(uint8_t dscp)
+{
+	if (dscp >= NSS_DSCP_MAP_ARRAY_SIZE) {
+		nss_warning("dscp:%u invalid\n", dscp);
+		return NSS_IPV4_DSCP_MAP_ACTION_MAX;
+	}
+
+	return mapping[dscp].action;
+}
+EXPORT_SYMBOL(nss_ipv4_dscp_action_get);
+
+/*
+ * nss_ipv4_max_conn_count()
+ *	Return the maximum number of IPv4 connections that the NSS acceleration engine supports.
+ */
+int nss_ipv4_max_conn_count(void)
+{
+	return nss_ipv4_conn_cfg;
+}
+EXPORT_SYMBOL(nss_ipv4_max_conn_count);
+
+/*
+ * nss_ipv4_conn_inquiry()
+ *	Inquiry if a connection has been established in NSS FW
+ */
+nss_tx_status_t nss_ipv4_conn_inquiry(struct nss_ipv4_5tuple *ipv4_5t_p,
+				nss_ipv4_msg_callback_t cb)
+{
+	nss_tx_status_t nss_tx_status;
+	struct nss_ipv4_msg nim;
+	struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[0];
+
+	/*
+	 * Initialize inquiry message structure.
+	 * This is async message and the result will be returned
+	 * to the caller by the msg_callback passed in.
+	 */
+	memset(&nim, 0, sizeof(nim));
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE,
+			NSS_IPV4_TX_CONN_CFG_INQUIRY_MSG,
+			sizeof(struct nss_ipv4_inquiry_msg),
+			cb, NULL);
+	nim.msg.inquiry.rr.tuple = *ipv4_5t_p;
+	nss_tx_status = nss_ipv4_tx(nss_ctx, &nim);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Send inquiry message failed\n", ipv4_5t_p);
+	}
+
+	return nss_tx_status;
+}
+EXPORT_SYMBOL(nss_ipv4_conn_inquiry);
+
+/*
+ * nss_ipv4_tx_with_size()
+ *	Transmit an ipv4 message to the FW with a specified size.
+ */
+nss_tx_status_t nss_ipv4_tx_with_size(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_msg *nim, uint32_t size)
+{
+	struct nss_cmn_msg *ncm = &nim->cm;
+
+	/*
+	 * Sanity check the message
+	 */
+	if (ncm->interface != NSS_IPV4_RX_INTERFACE) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_IPV4_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_ipv4_log_tx_msg(nim);
+
+	return nss_core_send_cmd(nss_ctx, nim, sizeof(*nim), size);
+}
+EXPORT_SYMBOL(nss_ipv4_tx_with_size);
+
+/*
+ * nss_ipv4_tx()
+ *	Transmit an ipv4 message to the FW.
+ */
+nss_tx_status_t nss_ipv4_tx(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_msg *nim)
+{
+	return nss_ipv4_tx_with_size(nss_ctx, nim, NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_ipv4_tx);
+
+/*
+ * nss_ipv4_tx_sync()
+ *	Transmit a synchronous ipv4 message to the FW.
+ */
+nss_tx_status_t nss_ipv4_tx_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_msg *nim)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&nss_ipv4_pvt.sem);
+	nss_ipv4_pvt.cb = (void *)nim->cm.cb;
+	nss_ipv4_pvt.app_data = (void *)nim->cm.app_data;
+
+	nim->cm.cb = (nss_ptr_t)nss_ipv4_tx_sync_callback;
+	nim->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_ipv4_tx(nss_ctx, nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss ipv4 msg tx failed\n", nss_ctx);
+		up(&nss_ipv4_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&nss_ipv4_pvt.complete, msecs_to_jiffies(NSS_IPV4_TX_MSG_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: IPv4 tx sync failed due to timeout\n", nss_ctx);
+		nss_ipv4_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = nss_ipv4_pvt.response;
+	up(&nss_ipv4_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_ipv4_tx_sync);
+
+/*
+ **********************************
+ Register/Unregister/Miscellaneous APIs
+ **********************************
+ */
+
+/*
+ * nss_ipv4_notify_register()
+ *	Register to received IPv4 events.
+ *
+ * NOTE: Do we want to pass an nss_ctx here so that we can register for ipv4 on any core?
+ */
+struct nss_ctx_instance *nss_ipv4_notify_register(nss_ipv4_msg_callback_t cb, void *app_data)
+{
+	/*
+	 * TODO: We need to have a new array in support of the new API
+	 * TODO: If we use a per-context array, we would move the array into nss_ctx based.
+	 */
+	nss_top_main.ipv4_callback = cb;
+	nss_top_main.ipv4_ctx = app_data;
+	return &nss_top_main.nss[nss_top_main.ipv4_handler_id];
+}
+EXPORT_SYMBOL(nss_ipv4_notify_register);
+
+/*
+ * nss_ipv4_notify_unregister()
+ *	Unregister to received IPv4 events.
+ *
+ * NOTE: Do we want to pass an nss_ctx here so that we can register for ipv4 on any core?
+ */
+void nss_ipv4_notify_unregister(void)
+{
+	nss_top_main.ipv4_callback = NULL;
+}
+EXPORT_SYMBOL(nss_ipv4_notify_unregister);
+
+/*
+ * nss_ipv4_conn_sync_many_notify_register()
+ *	Register to receive IPv4 conn_sync_many message response.
+ */
+void nss_ipv4_conn_sync_many_notify_register(nss_ipv4_msg_callback_t cb)
+{
+	nss_ipv4_conn_sync_many_msg_cb = cb;
+}
+EXPORT_SYMBOL(nss_ipv4_conn_sync_many_notify_register);
+
+/*
+ * nss_ipv4_conn_sync_many_notify_unregister()
+ *	Unregister to receive IPv4 conn_sync_many message response.
+ */
+void nss_ipv4_conn_sync_many_notify_unregister(void)
+{
+	nss_ipv4_conn_sync_many_msg_cb = NULL;
+}
+EXPORT_SYMBOL(nss_ipv4_conn_sync_many_notify_unregister);
+
+/*
+ * nss_ipv4_get_mgr()
+ *
+ * TODO: This only suppports a single ipv4, do we ever want to support more?
+ */
+struct nss_ctx_instance *nss_ipv4_get_mgr(void)
+{
+	return (void *)&nss_top_main.nss[nss_top_main.ipv4_handler_id];
+}
+EXPORT_SYMBOL(nss_ipv4_get_mgr);
+
+/*
+ * nss_ipv4_register_handler()
+ *	Register our handler to receive messages for this interface
+ */
+void nss_ipv4_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ipv4_get_mgr();
+
+	if (nss_core_register_handler(nss_ctx, NSS_IPV4_RX_INTERFACE, nss_ipv4_rx_msg_handler, NULL) != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("IPv4 handler failed to register");
+	}
+
+	nss_ipv4_stats_dentry_create();
+	nss_ipv4_strings_dentry_create();
+}
+
+/*
+ * nss_ipv4_conn_cfg_process_callback()
+ *	Call back function for the ipv4 connection configure process
+ */
+static void nss_ipv4_conn_cfg_process_callback(void *app_data, struct nss_ipv4_msg *nim)
+{
+	struct nss_ipv4_rule_conn_cfg_msg *nirccm = &nim->msg.rule_conn_cfg;
+	struct nss_ctx_instance *nss_ctx __maybe_unused = nss_ipv4_get_mgr();
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("%px: IPv4 connection configuration failed with error: %d\n", nss_ctx, nim->cm.error);
+		nss_core_update_max_ipv4_conn(NSS_FW_DEFAULT_NUM_CONN);
+		nss_ipv4_free_conn_tables();
+		return;
+	}
+
+	nss_ipv4_conn_cfg = ntohl(nirccm->num_conn);
+	nss_info("%px: IPv4 connection configuration success: %d\n", nss_ctx, nim->cm.error);
+}
+
+/*
+ * nss_ipv4_conn_cfg_process()
+ *	Process request to configure number of ipv4 connections
+ */
+static int nss_ipv4_conn_cfg_process(struct nss_ctx_instance *nss_ctx, int conn)
+{
+	struct nss_ipv4_msg nim;
+	struct nss_ipv4_rule_conn_cfg_msg *nirccm;
+	nss_tx_status_t nss_tx_status;
+
+	if ((!nss_ipv4_ct_info.ce_table_size) || (!nss_ipv4_ct_info.cme_table_size)) {
+		nss_warning("%px: connection entry or connection match entry table size not available\n",
+				nss_ctx);
+		return -EINVAL;
+	}
+
+	nss_info("%px: IPv4 supported connections: %d\n", nss_ctx, conn);
+
+	nss_ipv4_ct_info.ce_mem = __get_free_pages(GFP_ATOMIC | __GFP_NOWARN | __GFP_ZERO,
+					get_order(nss_ipv4_ct_info.ce_table_size));
+	if (!nss_ipv4_ct_info.ce_mem) {
+		nss_warning("%px: Memory allocation failed for IPv4 Connections: %d\n",
+							nss_ctx,
+							conn);
+		goto fail;
+	}
+
+	nss_ipv4_ct_info.cme_mem = __get_free_pages(GFP_ATOMIC | __GFP_NOWARN | __GFP_ZERO,
+					get_order(nss_ipv4_ct_info.cme_table_size));
+	if (!nss_ipv4_ct_info.ce_mem) {
+		nss_warning("%px: Memory allocation failed for IPv4 Connections: %d\n",
+							nss_ctx,
+							conn);
+		goto fail;
+	}
+
+	memset(&nim, 0, sizeof(struct nss_ipv4_msg));
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_CONN_CFG_RULE_MSG,
+		sizeof(struct nss_ipv4_rule_conn_cfg_msg), nss_ipv4_conn_cfg_process_callback, NULL);
+
+	nirccm = &nim.msg.rule_conn_cfg;
+	nirccm->num_conn = htonl(conn);
+	nirccm->ce_mem = dma_map_single(nss_ctx->dev, (void *)nss_ipv4_ct_info.ce_mem, nss_ipv4_ct_info.ce_table_size, DMA_TO_DEVICE);
+	if (unlikely(dma_mapping_error(nss_ctx->dev, nirccm->ce_mem))) {
+		nss_warning("%px: DMA mapping failed for virtual address = %px", nss_ctx, (void *)nss_ipv4_ct_info.ce_mem);
+		goto fail;
+	}
+
+	nirccm->cme_mem = dma_map_single(nss_ctx->dev, (void *)nss_ipv4_ct_info.cme_mem, nss_ipv4_ct_info.cme_table_size, DMA_TO_DEVICE);
+	if (unlikely(dma_mapping_error(nss_ctx->dev, nirccm->cme_mem))) {
+		nss_warning("%px: DMA mapping failed for virtual address = %px", nss_ctx, (void *)nss_ipv4_ct_info.cme_mem);
+		goto fail;
+	}
+
+	nss_tx_status = nss_ipv4_tx(nss_ctx, &nim);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_tx error setting IPv4 Connections: %d\n",
+							nss_ctx,
+							conn);
+		goto fail;
+	}
+
+	return 0;
+
+fail:
+	nss_ipv4_free_conn_tables();
+	return -EINVAL;;
+}
+
+/*
+ * nss_ipv4_update_conn_count_callback()
+ *	Callback function for the ipv4 get connection info message.
+ */
+static void nss_ipv4_update_conn_count_callback(void *app_data, struct nss_ipv4_msg *nim)
+{
+	struct nss_ipv4_rule_conn_get_table_size_msg *nircgts = &nim->msg.size;
+	struct nss_ctx_instance *nss_ctx = nss_ipv4_get_mgr();
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("%px: IPv4 fetch connection info failed with error: %d\n", nss_ctx, nim->cm.error);
+		nss_core_update_max_ipv4_conn(NSS_FW_DEFAULT_NUM_CONN);
+		return;
+	}
+
+	nss_info("IPv4 get connection info success\n");
+
+	nss_ipv4_ct_info.ce_table_size = ntohl(nircgts->ce_table_size);
+	nss_ipv4_ct_info.cme_table_size = ntohl(nircgts->cme_table_size);
+
+	if (nss_ipv4_conn_cfg_process(nss_ctx, ntohl(nircgts->num_conn)) != 0) {
+		nss_warning("%px: IPv4 connection entry or connection match entry table size\
+				not available\n", nss_ctx);
+	}
+
+	return;
+}
+
+/*
+ * nss_ipv4_update_conn_count()
+ *	Sets the maximum number of IPv4 connections.
+ *
+ * It first gets the connection tables size information from NSS FW
+ * and then configures the connections in NSS FW.
+ */
+int nss_ipv4_update_conn_count(int ipv4_num_conn)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ipv4_get_mgr();
+	struct nss_ipv4_msg nim;
+	struct nss_ipv4_rule_conn_get_table_size_msg *nircgts;
+	nss_tx_status_t nss_tx_status;
+	uint32_t sum_of_conn;
+
+	/*
+	 * By default, NSS FW is configured with default number of connections.
+	 */
+	if (ipv4_num_conn == NSS_FW_DEFAULT_NUM_CONN) {
+		nss_info("%px: Default number of connections (%d) already configured\n", nss_ctx, ipv4_num_conn);
+		return 0;
+	}
+
+	/*
+	 * The input should be multiple of 1024.
+	 * Input for ipv4 and ipv6 sum together should not exceed 8k
+	 * Min. value should be at least 256 connections. This is the
+	 * minimum connections we will support for each of them.
+	 */
+	sum_of_conn = nss_ipv4_get_total_conn_count(ipv4_num_conn);
+
+	if ((ipv4_num_conn & NSS_NUM_CONN_QUANTA_MASK) ||
+		(sum_of_conn > NSS_MAX_TOTAL_NUM_CONN_IPV4_IPV6) ||
+		(ipv4_num_conn < NSS_MIN_NUM_CONN)) {
+		nss_warning("%px: input supported connections (%d) does not adhere\
+				specifications\n1) not multiple of 1024,\n2) is less than \
+				min val: %d, OR\n	IPv4/6 total exceeds %d\n",
+				nss_ctx,
+				ipv4_num_conn,
+				NSS_MIN_NUM_CONN,
+				NSS_MAX_TOTAL_NUM_CONN_IPV4_IPV6);
+		return -EINVAL;
+	}
+
+	memset(&nim, 0, sizeof(struct nss_ipv4_msg));
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_CONN_TABLE_SIZE_MSG,
+		sizeof(struct nss_ipv4_rule_conn_get_table_size_msg), nss_ipv4_update_conn_count_callback, NULL);
+
+	nircgts = &nim.msg.size;
+	nircgts->num_conn = htonl(ipv4_num_conn);
+	nss_tx_status = nss_ipv4_tx(nss_ctx, &nim);
+
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Send fetch connection info message failed\n", nss_ctx);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ipv4_free_conn_tables()
+ *	Frees memory allocated for connection tables
+ */
+void nss_ipv4_free_conn_tables(void)
+{
+	if (nss_ipv4_ct_info.ce_mem) {
+		free_pages(nss_ipv4_ct_info.ce_mem, get_order(nss_ipv4_ct_info.ce_table_size));
+	}
+
+	if (nss_ipv4_ct_info.cme_mem) {
+		free_pages(nss_ipv4_ct_info.cme_mem, get_order(nss_ipv4_ct_info.cme_table_size));
+	}
+
+	memset(&nss_ipv4_ct_info, 0, sizeof(struct nss_ipv4_conn_table_info));
+	return;
+}
+
+/*
+ * nss_ipv4_accel_mode_cfg_handler()
+ *	Configure acceleration mode for IPv4
+ */
+static int nss_ipv4_accel_mode_cfg_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[0];
+	struct nss_ipv4_msg nim;
+	struct nss_ipv4_accel_mode_cfg_msg *nipcm;
+	nss_tx_status_t nss_tx_status;
+	int ret = NSS_FAILURE;
+	int current_value;
+
+	/*
+	 * Take snap shot of current value
+	 */
+	current_value = nss_ipv4_accel_mode_cfg;
+
+	/*
+	 * Write the variable with user input
+	 */
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret || (!write)) {
+		return ret;
+	}
+
+	memset(&nim, 0, sizeof(struct nss_ipv4_msg));
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_ACCEL_MODE_CFG_MSG,
+		sizeof(struct nss_ipv4_accel_mode_cfg_msg), NULL, NULL);
+
+	nipcm = &nim.msg.accel_mode_cfg;
+	nipcm->mode = htonl(nss_ipv4_accel_mode_cfg);
+
+	nss_tx_status = nss_ipv4_tx_sync(nss_ctx, &nim);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Send acceleration mode message failed\n", nss_ctx);
+		nss_ipv4_accel_mode_cfg = current_value;
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ipv4_dscp_map_cfg_handler()
+ *	Sysctl handler for dscp/pri mappings.
+ */
+static int nss_ipv4_dscp_map_cfg_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[0];
+	struct nss_dscp_map_parse out;
+	struct nss_ipv4_msg nim;
+	struct nss_ipv4_dscp2pri_cfg_msg *nipd2p;
+	nss_tx_status_t status;
+	int ret;
+
+	if (!write) {
+		return nss_dscp_map_print(ctl, buffer, lenp, ppos, mapping);
+	}
+
+	ret = nss_dscp_map_parse(ctl, buffer, lenp, ppos, &out);
+	if (ret) {
+		nss_warning("failed to parse dscp mapping:%d\n", ret);
+		nss_ipv4_dscp_map_usage();
+		return ret;
+	}
+
+	if (out.action >= NSS_IPV4_DSCP_MAP_ACTION_MAX) {
+		nss_warning("invalid action value: %d\n", out.action);
+		nss_ipv4_dscp_map_usage();
+		return -EINVAL;
+	}
+
+	memset(&nim, 0, sizeof(struct nss_ipv4_msg));
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_DSCP2PRI_CFG_MSG,
+		sizeof(struct nss_ipv4_dscp2pri_cfg_msg), NULL, NULL);
+
+	nipd2p = &nim.msg.dscp2pri_cfg;
+	nipd2p->dscp = out.dscp;
+	nipd2p->priority = out.priority;
+
+	status = nss_ipv4_tx_sync(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: ipv4 dscp2pri config message failed\n", nss_ctx);
+		return -EFAULT;
+	}
+
+	/*
+	 * NSS firmware acknowleged the configuration, so update the mapping
+	 * table on HOST side as well.
+	 */
+	mapping[out.dscp].action = out.action;
+	mapping[out.dscp].priority = out.priority;
+
+	return 0;
+}
+
+static struct ctl_table nss_ipv4_table[] = {
+	{
+		.procname	= "ipv4_accel_mode",
+		.data		= &nss_ipv4_accel_mode_cfg,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_ipv4_accel_mode_cfg_handler,
+	},
+	{
+		.procname	= "ipv4_dscp_map",
+		.data		= &mapping[NSS_DSCP_MAP_ARRAY_SIZE],
+		.maxlen		= sizeof(struct nss_dscp_map_entry),
+		.mode		= 0644,
+		.proc_handler	= &nss_ipv4_dscp_map_cfg_handler,
+	},
+	{ }
+};
+
+static struct ctl_table nss_ipv4_dir[] = {
+	{
+		.procname		= "ipv4cfg",
+		.mode			= 0555,
+		.child			= nss_ipv4_table,
+	},
+	{ }
+};
+
+static struct ctl_table nss_ipv4_root_dir[] = {
+	{
+		.procname		= "nss",
+		.mode			= 0555,
+		.child			= nss_ipv4_dir,
+	},
+	{ }
+};
+
+static struct ctl_table nss_ipv4_root[] = {
+	{
+		.procname		= "dev",
+		.mode			= 0555,
+		.child			= nss_ipv4_root_dir,
+	},
+	{ }
+};
+
+static struct ctl_table_header *nss_ipv4_header;
+
+/*
+ * nss_ipv4_register_sysctl()
+ *	Register sysctl specific to ipv4
+ */
+void nss_ipv4_register_sysctl(void)
+{
+	sema_init(&nss_ipv4_pvt.sem, 1);
+	init_completion(&nss_ipv4_pvt.complete);
+
+	/*
+	 * Register sysctl table.
+	 */
+	nss_ipv4_header = register_sysctl_table(nss_ipv4_root);
+}
+
+/*
+ * nss_ipv4_unregister_sysctl()
+ *	Unregister sysctl specific to ipv4
+ */
+void nss_ipv4_unregister_sysctl(void)
+{
+	/*
+	 * Unregister sysctl table.
+	 */
+	if (nss_ipv4_header) {
+		unregister_sysctl_table(nss_ipv4_header);
+	}
+}
+
+/*
+ * nss_ipv4_msg_init()
+ *	Initialize IPv4 message.
+ */
+void nss_ipv4_msg_init(struct nss_ipv4_msg *nim, uint16_t if_num, uint32_t type, uint32_t len,
+			nss_ipv4_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&nim->cm, if_num, type, len, (void *)cb, app_data);
+}
+EXPORT_SYMBOL(nss_ipv4_msg_init);
diff --git a/qca-nss-drv/nss_ipv4_log.c b/qca-nss-drv/nss_ipv4_log.c
new file mode 100644
index 0000000..0841405
--- /dev/null
+++ b/qca-nss-drv/nss_ipv4_log.c
@@ -0,0 +1,355 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016, 2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ipv4_log.c
+ *	NSS IPv4 logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_ipv4_log_message_types_str
+ *	IPv4 bridge/route rule message strings
+ */
+static int8_t *nss_ipv4_log_message_types_str[NSS_IPV4_MAX_MSG_TYPES] __maybe_unused = {
+	"IPv4 create rule message",
+	"IPv4 destroy rule message",
+	"Deprecated: NSS_IPV4_RX_ESTABLISH_RULE_MSG",
+	"IPv4 connection stats sync message",
+	"IPv4 generic statistics sync message",
+	"IPv4 number of connections supported rule message",
+	"IPv4 multicast create rule message",
+	"IPv4 request FW to send many conn sync message",
+};
+
+/*
+ * nss_ipv4_log_error_response_types_str
+ *	Strings for error types for ipv4 messages
+ */
+static int8_t *nss_ipv4_log_error_response_types_str[NSS_IPV4_LAST] __maybe_unused = {
+	"No error",
+	"Unknown error",
+	"Invalid interface number",
+	"Missing connection rule",
+	"Buffer allocation failure",
+	"No connection found to delete",
+	"Conn cfg already done once",
+	"Conn cfg input is not multiple of quanta",
+	"Conn cfg input exceeds max supported connections",
+	"Conn cfg mem alloc fail at NSS FW",
+	"Invalid L4 protocol for multicast rule create",
+	"Invalid multicast flags for multicast update",
+	"Invalid interface for multicast update",
+};
+
+/*
+ * nss_ipv4_log_rule_create_msg()
+ *	Log IPv4 create rule message.
+ */
+static void nss_ipv4_log_rule_create_msg(struct nss_ipv4_msg *nim)
+{
+	struct nss_ipv4_rule_create_msg *nircm __maybe_unused = &nim->msg.rule_create;
+	nss_trace("%px: IPv4 create rule message \n"
+		"Protocol: %d\n"
+		"from_mtu: %u\n"
+		"to_mtu: %u\n"
+		"from_ip: %pI4h:%d\n"
+		"to_ip: %pI4h:%d\n"
+		"from_ip_xlate: %pI4h:%d\n"
+		"to_ip_xlate: %pI4h:%d\n"
+		"from_mac: %pM\n"
+		"to_mac: %pM\n"
+		"src_iface_num: %u\n"
+		"dest_iface_num: %u\n"
+		"ingress_inner_vlan_tag: %u\n"
+		"egress_inner_vlan_tag: %u\n"
+		"ingress_outer_vlan_tag: %u\n"
+		"egress_outer_vlan_tag: %u\n"
+		"rule_flags: %x\n"
+		"valid_flags: %x\n"
+		"return_pppoe_if_exist: %u\n"
+		"return_pppoe_if_num: %u\n"
+		"flow_pppoe_if_exist: %u\n"
+		"flow_pppoe_if_num: %u\n"
+		"flow_qos_tag: %x (%u)\n"
+		"return_qos_tag: %x (%u)\n"
+		"flow_dscp: %x\n"
+		"return_dscp: %x\n"
+		"flow_mirror_ifnum: %u\n"
+		"return_mirror_ifnum: %u\n",
+		nim,
+		nircm->tuple.protocol,
+		nircm->conn_rule.flow_mtu,
+		nircm->conn_rule.return_mtu,
+		&nircm->tuple.flow_ip, nircm->tuple.flow_ident,
+		&nircm->tuple.return_ip, nircm->tuple.return_ident,
+		&nircm->conn_rule.flow_ip_xlate, nircm->conn_rule.flow_ident_xlate,
+		&nircm->conn_rule.return_ip_xlate, nircm->conn_rule.return_ident_xlate,
+		nircm->conn_rule.flow_mac,
+		nircm->conn_rule.return_mac,
+		nircm->conn_rule.flow_interface_num,
+		nircm->conn_rule.return_interface_num,
+		nircm->vlan_primary_rule.ingress_vlan_tag,
+		nircm->vlan_primary_rule.egress_vlan_tag,
+		nircm->vlan_secondary_rule.ingress_vlan_tag,
+		nircm->vlan_secondary_rule.egress_vlan_tag,
+		nircm->rule_flags,
+		nircm->valid_flags,
+		nircm->pppoe_rule.return_if_exist,
+		nircm->pppoe_rule.return_if_num,
+		nircm->pppoe_rule.flow_if_exist,
+		nircm->pppoe_rule.flow_if_num,
+		nircm->qos_rule.flow_qos_tag, nircm->qos_rule.flow_qos_tag,
+		nircm->qos_rule.return_qos_tag, nircm->qos_rule.return_qos_tag,
+		nircm->dscp_rule.flow_dscp,
+		nircm->dscp_rule.return_dscp,
+		nircm->mirror_rule.flow_ifnum,
+		nircm->mirror_rule.return_ifnum);
+}
+
+/*
+ * nss_ipv4_log_destroy_rule_msg()
+ *	Log IPv4 destroy rule message.
+ */
+static void nss_ipv4_log_destroy_rule_msg(struct nss_ipv4_msg *nim)
+{
+	struct nss_ipv4_rule_destroy_msg *nirdm __maybe_unused = &nim->msg.rule_destroy;
+	nss_trace("%px: IPv4 destroy rule message: \n"
+		"flow_ip: %pI4h:%d\n"
+		"return_ip: %pI4h:%d\n"
+		"protocol: %d\n",
+		nim,
+		&nirdm->tuple.flow_ip, nirdm->tuple.flow_ident,
+		&nirdm->tuple.return_ip, nirdm->tuple.return_ident,
+		nirdm->tuple.protocol);
+}
+
+/*
+ * nss_ipv4_log_conn_sync()
+ *	Log IPv4 connection stats sync message.
+ */
+static void nss_ipv4_log_conn_sync(struct nss_ipv4_msg *nim)
+{
+	struct nss_ipv4_conn_sync *sync = &nim->msg.conn_stats;
+	if (sync->flow_tx_packet_count || sync->return_tx_packet_count) {
+		nss_trace("%px: IPv4 connection stats sync message: \n"
+			"Protocol: %d\n"
+			"src_addr: %pI4h:%d\n"
+			"dest_addr: %pI4h:%d\n"
+			"flow_rx_packet_count: %u\n"
+			"flow_rx_byte_count: %u\n"
+			"return_rx_packet_count: %u\n"
+			"return_rx_byte_count: %u\n"
+			"flow_tx_packet_count: %u\n"
+			"flow_tx_byte_count: %u\n"
+			"return_tx_packet_count: %u\n"
+			"return_tx_byte_count: %u\n",
+			nim,
+			(int)sync->protocol,
+			&sync->flow_ip, (int)sync->flow_ident,
+			&sync->return_ip_xlate, (int)sync->return_ident_xlate,
+			sync->flow_rx_packet_count,
+			sync->flow_rx_byte_count,
+			sync->return_rx_packet_count,
+			sync->return_rx_byte_count,
+			sync->flow_tx_packet_count,
+			sync->flow_tx_byte_count,
+			sync->return_tx_packet_count,
+			sync->return_tx_byte_count);
+		}
+}
+
+/*
+ * nss_ipv4_log_conn_cfg_msg()
+ *	Log IPv4 number of connections supported rule message.
+ */
+static void nss_ipv4_log_conn_cfg_msg(struct nss_ipv4_msg *nim)
+{
+	struct nss_ipv4_rule_conn_cfg_msg *nirccm __maybe_unused = &nim->msg.rule_conn_cfg;
+	nss_trace("%px: IPv4 number of connections supported rule message: \n"
+		"num_conn: %d\n",
+		nim,
+		nirccm->num_conn);
+}
+
+/*
+ * nss_ipv4_log_mc_rule_create_msg()
+ *	Log IPv4 multicast create rule message.
+ */
+static void nss_ipv4_log_mc_rule_create_msg(struct nss_ipv4_msg *nim)
+{
+	uint16_t vif;
+	struct nss_ipv4_mc_rule_create_msg *nimrcm = &nim->msg.mc_rule_create;
+	for (vif = 0; vif < nimrcm->if_count ; vif++) {
+		nss_trace("%px: IPv4 multicast create rule message \n"
+			"Rule flag: %x\n"
+			"Vif: %d\n"
+			"Protocol: %d\n"
+			"to_mtu: %u\n"
+			"from_ip: %pI4h:%d\n"
+			"to_ip: %pI4h:%d\n"
+			"to_mac: %pM\n"
+			"dest_iface_num: %u\n"
+			"out_vlan[0] %x\n"
+			"out_vlan[1] %x\n",
+			nim,
+			nimrcm->if_rule[vif].rule_flags,
+			vif,
+			nimrcm->tuple.protocol,
+			nimrcm->if_rule[vif].if_mtu,
+			&nimrcm->tuple.flow_ip, nimrcm->tuple.flow_ident,
+			&nimrcm->tuple.return_ip, nimrcm->tuple.return_ident,
+			nimrcm->if_rule[vif].if_mac,
+			nimrcm->if_rule[vif].if_num,
+			nimrcm->if_rule[vif].egress_vlan_tag[0],
+			nimrcm->if_rule[vif].egress_vlan_tag[1]);
+	}
+}
+
+/*
+ * nss_ipv4_log_conn_sync_many_msg()
+ *	Log IPv4 many conn sync message.
+ */
+static void nss_ipv4_log_conn_sync_many_msg(struct nss_ipv4_msg *nim)
+{
+	uint16_t i;
+	struct nss_ipv4_conn_sync_many_msg *nicsm = &nim->msg.conn_stats_many;
+	for (i = 0; i < nicsm->count; i++) {
+		struct nss_ipv4_conn_sync *sync = &nicsm->conn_sync[i];
+		if (sync->flow_tx_packet_count || sync->return_tx_packet_count) {
+			nss_trace("%px: IPv4 many conn sync message \n"
+				"count: %d\n"
+				"i: %d\n"
+				"Protocol: %d\n"
+				"src_addr: %pI4h:%d\n"
+				"dest_addr: %pI4h:%d\n"
+				"flow_rx_packet_count: %u\n"
+				"flow_rx_byte_count: %u\n"
+				"return_rx_packet_count: %u\n"
+				"return_rx_byte_count: %u\n"
+				"flow_tx_packet_count: %u\n"
+				"flow_tx_byte_count: %u\n"
+				"return_tx_packet_count: %u\n"
+				"return_tx_byte_count: %u\n",
+				nim,
+				nicsm->count,
+				i,
+				(int)sync->protocol,
+				&sync->flow_ip, (int)sync->flow_ident,
+				&sync->return_ip_xlate, (int)sync->return_ident_xlate,
+				sync->flow_rx_packet_count,
+				sync->flow_rx_byte_count,
+				sync->return_rx_packet_count,
+				sync->return_rx_byte_count,
+				sync->flow_tx_packet_count,
+				sync->flow_tx_byte_count,
+				sync->return_tx_packet_count,
+				sync->return_tx_byte_count);
+		}
+	}
+}
+
+/*
+ * nss_ipv4_log_verbose()
+ *	Log message contents.
+ */
+static void nss_ipv4_log_verbose(struct nss_ipv4_msg *nim)
+{
+	switch (nim->cm.type) {
+	case NSS_IPV4_TX_CREATE_RULE_MSG:
+		nss_ipv4_log_rule_create_msg(nim);
+		break;
+
+	case NSS_IPV4_TX_DESTROY_RULE_MSG:
+		nss_ipv4_log_destroy_rule_msg(nim);
+		break;
+
+	case NSS_IPV4_RX_CONN_STATS_SYNC_MSG:
+		nss_ipv4_log_conn_sync(nim);
+		break;
+
+	case NSS_IPV4_RX_NODE_STATS_SYNC_MSG:
+		/* Getting logged in stats */
+		break;
+
+	case NSS_IPV4_TX_CONN_CFG_RULE_MSG:
+		nss_ipv4_log_conn_cfg_msg(nim);
+		break;
+
+	case NSS_IPV4_TX_CREATE_MC_RULE_MSG:
+		nss_ipv4_log_mc_rule_create_msg(nim);
+		break;
+
+	case NSS_IPV4_TX_CONN_STATS_SYNC_MANY_MSG:
+		nss_ipv4_log_conn_sync_many_msg(nim);
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", nim);
+		break;
+	}
+}
+
+/*
+ * nss_ipv4_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_ipv4_log_tx_msg(struct nss_ipv4_msg *nim)
+{
+	if (nim->cm.type >= NSS_IPV4_MAX_MSG_TYPES) {
+		nss_info("%px: Invalid message type\n", nim);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nim, nim->cm.type, nss_ipv4_log_message_types_str[nim->cm.type]);
+	nss_ipv4_log_verbose(nim);
+}
+
+/*
+ * nss_ipv4_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_ipv4_log_rx_msg(struct nss_ipv4_msg *nim)
+{
+	if (nim->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_info("%px: Invalid response\n", nim);
+		return;
+	}
+
+	if (nim->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nim->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nim, nim->cm.type,
+			nss_ipv4_log_message_types_str[nim->cm.type],
+			nim->cm.response, nss_cmn_response_str[nim->cm.response]);
+		goto verbose;
+	}
+
+	if (nim->cm.error >= NSS_IPV4_LAST) {
+		nss_info("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			nim, nim->cm.type, nss_ipv4_log_message_types_str[nim->cm.type],
+			nim->cm.response, nss_cmn_response_str[nim->cm.response],
+			nim->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		nim, nim->cm.type, nss_ipv4_log_message_types_str[nim->cm.type],
+		nim->cm.response, nss_cmn_response_str[nim->cm.response],
+		nim->cm.error, nss_ipv4_log_error_response_types_str[nim->cm.error]);
+
+verbose:
+	nss_ipv4_log_verbose(nim);
+}
diff --git a/qca-nss-drv/nss_ipv4_reasm.c b/qca-nss-drv/nss_ipv4_reasm.c
new file mode 100644
index 0000000..402a46c
--- /dev/null
+++ b/qca-nss-drv/nss_ipv4_reasm.c
@@ -0,0 +1,76 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014,2017,2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ipv4_reasm.c
+ *	NSS IPv4 Reassembly APIs
+ */
+#include <nss_core.h>
+#include "nss_ipv4_reasm_stats.h"
+#include "nss_ipv4_reasm_strings.h"
+
+/*
+ * nss_ipv4_reasm_msg_handler()
+ *	Handle NSS -> HLOS messages for IPv4 reasm
+ */
+static void nss_ipv4_reasm_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_ipv4_reasm_msg *nim = (struct nss_ipv4_reasm_msg *)ncm;
+
+	BUG_ON(ncm->interface != NSS_IPV4_REASM_INTERFACE);
+
+	/*
+	 * Handle deprecated messages.  Eventually these messages should be removed.
+	 */
+	switch (nim->cm.type) {
+	case NSS_IPV4_REASM_STATS_SYNC_MSG:
+		/*
+		 * Update Ipv4 reasm driver statistics and send statistics notifications to the registered modules.
+		 */
+		nss_ipv4_reasm_stats_sync(nss_ctx, &nim->msg.stats_sync);
+		nss_ipv4_reasm_stats_notify(nss_ctx);
+
+		break;
+	default:
+		nss_warning("IPv4 reasm received an unknown message type");
+	}
+}
+
+/*
+ * nss_ipv4_reasm_get_context()
+ * 	get NSS context instance for ipv4 reassembly
+ */
+struct nss_ctx_instance *nss_ipv4_reasm_get_context(void)
+{
+	return &nss_top_main.nss[nss_top_main.ipv4_reasm_handler_id];
+}
+EXPORT_SYMBOL(nss_ipv4_reasm_get_context);
+
+/*
+ * nss_ipv4_reasm_register_handler()
+ *	Register our handler to receive messages for this interface
+ */
+void nss_ipv4_reasm_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ipv4_reasm_get_context();
+
+	if (nss_core_register_handler(nss_ctx, NSS_IPV4_REASM_INTERFACE, nss_ipv4_reasm_msg_handler, NULL) != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("IPv4 reasm handler failed to register");
+	}
+
+	nss_ipv4_reasm_stats_dentry_create();
+	nss_ipv4_reasm_strings_dentry_create();
+}
diff --git a/qca-nss-drv/nss_ipv4_reasm_stats.c b/qca-nss-drv/nss_ipv4_reasm_stats.c
new file mode 100644
index 0000000..350e619
--- /dev/null
+++ b/qca-nss-drv/nss_ipv4_reasm_stats.c
@@ -0,0 +1,167 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017,2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_ipv4_reasm_stats.h"
+#include "nss_ipv4_reasm.h"
+#include "nss_ipv4_reasm_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_ipv4_reasm_stats_notifier);
+
+uint64_t nss_ipv4_reasm_stats[NSS_IPV4_REASM_STATS_MAX]; /* IPv4 reasm statistics */
+
+/*
+ * nss_ipv4_reasm_stats_read()
+ *	Read IPV4 reassembly stats
+ */
+static ssize_t nss_ipv4_reasm_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * Max output lines = #stats + few blank lines for banner printing +
+	 * Number of Extra outputlines for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_STATS_NODE_MAX + NSS_IPV4_REASM_STATS_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_IPV4_REASM_STATS_MAX * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "ipv4_reasm", NSS_STATS_SINGLE_CORE);
+
+	size_wr += nss_stats_fill_common_stats(NSS_IPV4_REASM_INTERFACE, NSS_STATS_SINGLE_INSTANCE, lbuf, size_wr, size_al, "ipv4_reasm");
+
+	/*
+	 * IPv4 reasm node stats
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; (i < NSS_IPV4_REASM_STATS_MAX); i++) {
+		stats_shadow[i] = nss_ipv4_reasm_stats[i];
+	}
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+	size_wr += nss_stats_print("ipv4_reasm", NULL, NSS_STATS_SINGLE_INSTANCE
+					, nss_ipv4_reasm_strings_stats
+					, stats_shadow
+					, NSS_IPV4_REASM_STATS_MAX
+					, lbuf, size_wr, size_al);
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_ipv4_reasm_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(ipv4_reasm);
+
+/*
+ * nss_ipv4_reasm_stats_dentry_create()
+ *	Create the IPv4 reasm statistics debug entry
+ */
+void nss_ipv4_reasm_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("ipv4_reasm", &nss_ipv4_reasm_stats_ops);
+}
+
+/*
+ * nss_ipv4_reasm_stats_sync()
+ *	Update driver specific information from the messsage.
+ */
+void nss_ipv4_reasm_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_reasm_stats_sync *nirs)
+{
+	int i;
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	spin_lock_bh(&nss_top->stats_lock);
+
+	/*
+	 * Common node stats
+	 */
+	nss_top->stats_node[NSS_IPV4_REASM_INTERFACE][NSS_STATS_NODE_RX_PKTS] += nirs->node_stats.rx_packets;
+	nss_top->stats_node[NSS_IPV4_REASM_INTERFACE][NSS_STATS_NODE_RX_BYTES] += nirs->node_stats.rx_bytes;
+	nss_top->stats_node[NSS_IPV4_REASM_INTERFACE][NSS_STATS_NODE_TX_PKTS] += nirs->node_stats.tx_packets;
+	nss_top->stats_node[NSS_IPV4_REASM_INTERFACE][NSS_STATS_NODE_TX_BYTES] += nirs->node_stats.tx_bytes;
+
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		nss_top->stats_node[NSS_IPV4_REASM_INTERFACE][NSS_STATS_NODE_RX_QUEUE_0_DROPPED + i] += nirs->node_stats.rx_dropped[i];
+	}
+
+	/*
+	 * IPv4 reasm node stats
+	 */
+	nss_ipv4_reasm_stats[NSS_IPV4_REASM_STATS_EVICTIONS] += nirs->ipv4_reasm_evictions;
+	nss_ipv4_reasm_stats[NSS_IPV4_REASM_STATS_ALLOC_FAILS] += nirs->ipv4_reasm_alloc_fails;
+	nss_ipv4_reasm_stats[NSS_IPV4_REASM_STATS_TIMEOUTS] += nirs->ipv4_reasm_timeouts;
+
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_ipv4_reasm_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_ipv4_reasm_stats_notify(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_ipv4_reasm_stats_notification ipv4_reasm_stats;
+
+	ipv4_reasm_stats.core_id = nss_ctx->id;
+	memcpy(ipv4_reasm_stats.cmn_node_stats, nss_top_main.stats_node[NSS_IPV4_REASM_INTERFACE], sizeof(ipv4_reasm_stats.cmn_node_stats));
+	memcpy(ipv4_reasm_stats.ipv4_reasm_stats, nss_ipv4_reasm_stats, sizeof(ipv4_reasm_stats.ipv4_reasm_stats));
+	atomic_notifier_call_chain(&nss_ipv4_reasm_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&ipv4_reasm_stats);
+}
+
+/*
+ * nss_ipv4_reasm_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_ipv4_reasm_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_ipv4_reasm_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_ipv4_reasm_stats_register_notifier);
+
+/*
+ * nss_ipv4_reasm_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_ipv4_reasm_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_ipv4_reasm_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_ipv4_reasm_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_ipv4_reasm_stats.h b/qca-nss-drv/nss_ipv4_reasm_stats.h
new file mode 100644
index 0000000..f8c5f39
--- /dev/null
+++ b/qca-nss-drv/nss_ipv4_reasm_stats.h
@@ -0,0 +1,27 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017,2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_IPV4_REASM_STATS_H
+#define __NSS_IPV4_REASM_STATS_H
+
+/*
+ * IPV4 reasm statistics APIs
+ */
+extern void nss_ipv4_reasm_stats_notify(struct nss_ctx_instance *nss_ctx);
+extern void nss_ipv4_reasm_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_reasm_stats_sync *nirs);
+extern void nss_ipv4_reasm_stats_dentry_create(void);
+
+#endif /* __NSS_IPV4_REASM_STATS_H */
diff --git a/qca-nss-drv/nss_ipv4_reasm_strings.c b/qca-nss-drv/nss_ipv4_reasm_strings.c
new file mode 100644
index 0000000..445d134
--- /dev/null
+++ b/qca-nss-drv/nss_ipv4_reasm_strings.c
@@ -0,0 +1,55 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include <nss_ipv4_reasm.h>
+#include "nss_strings.h"
+
+/*
+ * nss_ipv4_reasm_strings_stats
+ *	IPv4 reassembly statistics strings.
+ */
+struct nss_stats_info nss_ipv4_reasm_strings_stats[NSS_IPV4_REASM_STATS_MAX] = {
+	{"evictions"	, NSS_STATS_TYPE_DROP},
+	{"alloc_fails"	, NSS_STATS_TYPE_DROP},
+	{"timeouts"	, NSS_STATS_TYPE_DROP}
+};
+
+/*
+ * nss_ipv4_reasm_strings_read()
+ *	Read IPv4 reassembly node statistics names.
+ */
+static ssize_t nss_ipv4_reasm_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_ipv4_reasm_strings_stats, NSS_IPV4_REASM_STATS_MAX);
+}
+
+/*
+ * nss_ipv4_reasm_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(ipv4_reasm);
+
+/*
+ * nss_ipv4_reasm_strings_dentry_create()
+ *	Create IPv4 reassembly statistics strings debug entry.
+ */
+void nss_ipv4_reasm_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("ipv4_reasm", &nss_ipv4_reasm_strings_ops);
+}
diff --git a/qca-nss-drv/nss_ipv4_reasm_strings.h b/qca-nss-drv/nss_ipv4_reasm_strings.h
new file mode 100644
index 0000000..9a0b362
--- /dev/null
+++ b/qca-nss-drv/nss_ipv4_reasm_strings.h
@@ -0,0 +1,25 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_IPV4_REASM_STRINGS_H
+#define __NSS_IPV4_REASM_STRINGS_H
+
+extern struct nss_stats_info nss_ipv4_reasm_strings_stats[NSS_IPV4_REASM_STATS_MAX];
+extern void nss_ipv4_reasm_strings_dentry_create(void);
+
+#endif /* __NSS_IPV4_REASM_STRINGS_H */
diff --git a/qca-nss-drv/nss_ipv4_stats.c b/qca-nss-drv/nss_ipv4_stats.c
new file mode 100644
index 0000000..39b162c
--- /dev/null
+++ b/qca-nss-drv/nss_ipv4_stats.c
@@ -0,0 +1,239 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2019-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include <nss_ipv4.h>
+#include "nss_ipv4_stats.h"
+#include "nss_ipv4_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_ipv4_stats_notifier);
+
+uint64_t nss_ipv4_stats[NSS_IPV4_STATS_MAX];
+uint64_t nss_ipv4_exception_stats[NSS_IPV4_EXCEPTION_EVENT_MAX];
+
+/*
+ * nss_ipv4_stats_read()
+ *	Read IPV4 stats
+ */
+static ssize_t nss_ipv4_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * max output lines = #stats + Number of Extra outputlines for future reference to add new stats +
+	 * start tag line + end tag line + three blank lines
+	 */
+	uint32_t max_output_lines = NSS_STATS_NODE_MAX + NSS_IPV4_STATS_MAX + NSS_IPV4_EXCEPTION_EVENT_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	/*
+	 * Note: The assumption here is that exception event count is larger than other statistics count for IPv4
+	 */
+	stats_shadow = kzalloc(NSS_IPV4_EXCEPTION_EVENT_MAX * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "ipv4", NSS_STATS_SINGLE_CORE);
+	size_wr += nss_stats_fill_common_stats(NSS_IPV4_RX_INTERFACE, NSS_STATS_SINGLE_INSTANCE, lbuf, size_wr, size_al, "ipv4");
+
+	/*
+	 * IPv4 node stats
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; i < NSS_IPV4_STATS_MAX; i++) {
+		stats_shadow[i] = nss_ipv4_stats[i];
+	}
+	spin_unlock_bh(&nss_top_main.stats_lock);
+	size_wr += nss_stats_print("ipv4", "ipv4 special stats"
+					, NSS_STATS_SINGLE_INSTANCE
+					, nss_ipv4_strings_stats
+					, stats_shadow
+					, NSS_IPV4_STATS_MAX
+					, lbuf, size_wr, size_al);
+
+	/*
+	 * Exception stats
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; (i < NSS_IPV4_EXCEPTION_EVENT_MAX); i++) {
+		stats_shadow[i] = nss_ipv4_exception_stats[i];
+	}
+	spin_unlock_bh(&nss_top_main.stats_lock);
+	size_wr += nss_stats_print("ipv4", "ipv4 exception stats"
+					, NSS_STATS_SINGLE_INSTANCE
+					, nss_ipv4_strings_exception_stats
+					, stats_shadow
+					, NSS_IPV4_EXCEPTION_EVENT_MAX
+					, lbuf, size_wr, size_al);
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_ipv4_stats_conn_sync()
+ *	Update driver specific information from the messsage.
+ */
+void nss_ipv4_stats_conn_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_conn_sync *nirs)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	/*
+	 * Update statistics maintained by NSS driver
+	 */
+	spin_lock_bh(&nss_top->stats_lock);
+	nss_ipv4_stats[NSS_IPV4_STATS_ACCELERATED_RX_PKTS] += nirs->flow_rx_packet_count + nirs->return_rx_packet_count;
+	nss_ipv4_stats[NSS_IPV4_STATS_ACCELERATED_RX_BYTES] += nirs->flow_rx_byte_count + nirs->return_rx_byte_count;
+	nss_ipv4_stats[NSS_IPV4_STATS_ACCELERATED_TX_PKTS] += nirs->flow_tx_packet_count + nirs->return_tx_packet_count;
+	nss_ipv4_stats[NSS_IPV4_STATS_ACCELERATED_TX_BYTES] += nirs->flow_tx_byte_count + nirs->return_tx_byte_count;
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_ipv4_stats_conn_sync_many()
+ *	Update driver specific information from the conn_sync_many messsage.
+ */
+void nss_ipv4_stats_conn_sync_many(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_conn_sync_many_msg *nicsm)
+{
+	int i;
+
+	/*
+	 * Sanity check for the stats count
+	 */
+	if (nicsm->count * sizeof(struct nss_ipv4_conn_sync) >= nicsm->size) {
+		nss_warning("%px: stats sync count %u exceeds the size of this msg %u", nss_ctx, nicsm->count, nicsm->size);
+		return;
+	}
+
+	for (i = 0; i < nicsm->count; i++) {
+		nss_ipv4_stats_conn_sync(nss_ctx, &nicsm->conn_sync[i]);
+	}
+}
+
+/*
+ * nss_ipv4_stats_node_sync()
+ *	Update driver specific information from the messsage.
+ */
+void nss_ipv4_stats_node_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_node_sync *nins)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	uint32_t i;
+
+	/*
+	 * Update statistics maintained by NSS driver
+	 */
+	spin_lock_bh(&nss_top->stats_lock);
+	nss_top->stats_node[NSS_IPV4_RX_INTERFACE][NSS_STATS_NODE_RX_PKTS] += nins->node_stats.rx_packets;
+	nss_top->stats_node[NSS_IPV4_RX_INTERFACE][NSS_STATS_NODE_RX_BYTES] += nins->node_stats.rx_bytes;
+	nss_top->stats_node[NSS_IPV4_RX_INTERFACE][NSS_STATS_NODE_TX_PKTS] += nins->node_stats.tx_packets;
+	nss_top->stats_node[NSS_IPV4_RX_INTERFACE][NSS_STATS_NODE_TX_BYTES] += nins->node_stats.tx_bytes;
+
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		nss_top->stats_node[NSS_IPV4_RX_INTERFACE][NSS_STATS_NODE_RX_QUEUE_0_DROPPED + i] += nins->node_stats.rx_dropped[i];
+	}
+
+	nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_CREATE_REQUESTS] += nins->ipv4_connection_create_requests;
+	nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_CREATE_COLLISIONS] += nins->ipv4_connection_create_collisions;
+	nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_INTERFACE] += nins->ipv4_connection_create_invalid_interface;
+	nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_DESTROY_REQUESTS] += nins->ipv4_connection_destroy_requests;
+	nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_DESTROY_MISSES] += nins->ipv4_connection_destroy_misses;
+	nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_HASH_HITS] += nins->ipv4_connection_hash_hits;
+	nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_HASH_REORDERS] += nins->ipv4_connection_hash_reorders;
+	nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_FLUSHES] += nins->ipv4_connection_flushes;
+	nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_EVICTIONS] += nins->ipv4_connection_evictions;
+	nss_ipv4_stats[NSS_IPV4_STATS_FRAGMENTATIONS] += nins->ipv4_fragmentations;
+	nss_ipv4_stats[NSS_IPV4_STATS_MC_CONNECTION_CREATE_REQUESTS] += nins->ipv4_mc_connection_create_requests;
+	nss_ipv4_stats[NSS_IPV4_STATS_MC_CONNECTION_UPDATE_REQUESTS] += nins->ipv4_mc_connection_update_requests;
+	nss_ipv4_stats[NSS_IPV4_STATS_MC_CONNECTION_CREATE_INVALID_INTERFACE] += nins->ipv4_mc_connection_create_invalid_interface;
+	nss_ipv4_stats[NSS_IPV4_STATS_MC_CONNECTION_DESTROY_REQUESTS] += nins->ipv4_mc_connection_destroy_requests;
+	nss_ipv4_stats[NSS_IPV4_STATS_MC_CONNECTION_DESTROY_MISSES] += nins->ipv4_mc_connection_destroy_misses;
+	nss_ipv4_stats[NSS_IPV4_STATS_MC_CONNECTION_FLUSHES] += nins->ipv4_mc_connection_flushes;
+	nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM] += nins->ipv4_connection_create_invalid_mirror_ifnum;
+	nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE] += nins->ipv4_connection_create_invalid_mirror_iftype;
+	nss_ipv4_stats[NSS_IPV4_STATS_MIRROR_FAILURES] += nins->ipv4_mirror_failures;
+
+	for (i = 0; i < NSS_IPV4_EXCEPTION_EVENT_MAX; i++) {
+		nss_ipv4_exception_stats[i] += nins->exception_events[i];
+	}
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_ipv4_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(ipv4);
+
+/*
+ * nss_ipv4_stats_dentry_create()
+ *	Create IPv4 statistics debug entry.
+ */
+void nss_ipv4_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("ipv4", &nss_ipv4_stats_ops);
+}
+
+/*
+ * nss_ipv4_stats_notify()
+ *	Sends notifications to the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_ipv4_stats_notify(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_ipv4_stats_notification ipv4_stats;
+
+	ipv4_stats.core_id = nss_ctx->id;
+	memcpy(ipv4_stats.cmn_node_stats, nss_top_main.stats_node[NSS_IPV4_RX_INTERFACE], sizeof(ipv4_stats.cmn_node_stats));
+	memcpy(ipv4_stats.special_stats, nss_ipv4_stats, sizeof(ipv4_stats.special_stats));
+	memcpy(ipv4_stats.exception_stats, nss_ipv4_exception_stats, sizeof(ipv4_stats.exception_stats));
+	atomic_notifier_call_chain(&nss_ipv4_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&ipv4_stats);
+}
+
+/*
+ * nss_ipv4_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_ipv4_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_ipv4_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_ipv4_stats_register_notifier);
+
+/*
+ * nss_ipv4_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_ipv4_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_ipv4_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_ipv4_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_ipv4_stats.h b/qca-nss-drv/nss_ipv4_stats.h
new file mode 100644
index 0000000..ad85c35
--- /dev/null
+++ b/qca-nss-drv/nss_ipv4_stats.h
@@ -0,0 +1,29 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017, 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_IPV4_STATS_H
+#define __NSS_IPV4_STATS_H
+
+/*
+ * NSS IPV4 statistics APIs
+ */
+extern void nss_ipv4_stats_notify(struct nss_ctx_instance *nss_ctx);
+extern void nss_ipv4_stats_node_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_node_sync *nins);
+extern void nss_ipv4_stats_conn_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_conn_sync *nirs);
+extern void nss_ipv4_stats_conn_sync_many(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_conn_sync_many_msg *nicsm);
+extern void nss_ipv4_stats_dentry_create(void);
+
+#endif /* __NSS_IPV4_STATS_H */
diff --git a/qca-nss-drv/nss_ipv4_strings.c b/qca-nss-drv/nss_ipv4_strings.c
new file mode 100644
index 0000000..867e201
--- /dev/null
+++ b/qca-nss-drv/nss_ipv4_strings.c
@@ -0,0 +1,209 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include <nss_ipv4.h>
+#include "nss_strings.h"
+
+/*
+ * nss_ipv4_strings_exception_stats
+ *	Interface statistics strings for ipv4 exceptions.
+ */
+struct nss_stats_info nss_ipv4_strings_exception_stats[NSS_IPV4_EXCEPTION_EVENT_MAX] = {
+	{"icmp_hdr_incomplete"			, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_unhandled_type"			, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_ipv4_hdr_incomplete"		, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_ipv4_udp_hdr_incomplete"		, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_ipv4_tcp_header_incomplete"	, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_sipv4_unknown_protocol"		, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_no_icme"				, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_flush_to_host"			, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_header_incomplete"		, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_no_icme"				, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_ip_option"			, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_ip_fragment"			, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_small_ttl"			, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_needs_fragmentation"		, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_flags"				, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_seq_exceeds_right_edge"		, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_small_data_offs"			, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_bad_sack"				, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_big_data_offs"			, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_seq_before_left_edge"		, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_ack_exceeds_right_edge"		, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_ack_before_left_edge"		, NSS_STATS_TYPE_EXCEPTION},
+	{"udp_header_incomplete"		, NSS_STATS_TYPE_EXCEPTION},
+	{"udp_no_icme"				, NSS_STATS_TYPE_EXCEPTION},
+	{"udp_ip_option"			, NSS_STATS_TYPE_EXCEPTION},
+	{"udp_ip_fragment"			, NSS_STATS_TYPE_EXCEPTION},
+	{"udp_small_ttl"			, NSS_STATS_TYPE_EXCEPTION},
+	{"udp_needs_fragmentation"		, NSS_STATS_TYPE_EXCEPTION},
+	{"wrong_target_mac"			, NSS_STATS_TYPE_EXCEPTION},
+	{"header_incomplete"			, NSS_STATS_TYPE_EXCEPTION},
+	{"bad_total_length"			, NSS_STATS_TYPE_EXCEPTION},
+	{"bad_checksum"				, NSS_STATS_TYPE_EXCEPTION},
+	{"non_initial_fragment"			, NSS_STATS_TYPE_EXCEPTION},
+	{"datagram_incomplete"			, NSS_STATS_TYPE_EXCEPTION},
+	{"options_incomplete"			, NSS_STATS_TYPE_EXCEPTION},
+	{"unknown_protocol"			, NSS_STATS_TYPE_EXCEPTION},
+	{"esp_header_incomplete"		, NSS_STATS_TYPE_EXCEPTION},
+	{"esp_no_icme"				, NSS_STATS_TYPE_EXCEPTION},
+	{"esp_ip_option"			, NSS_STATS_TYPE_EXCEPTION},
+	{"esp_ip_fragment"			, NSS_STATS_TYPE_EXCEPTION},
+	{"esp_small_ttl"			, NSS_STATS_TYPE_EXCEPTION},
+	{"esp_needs_fragmentation"		, NSS_STATS_TYPE_EXCEPTION},
+	{"ingress_vid_mismatch"			, NSS_STATS_TYPE_EXCEPTION},
+	{"ingress_vid_missing"			, NSS_STATS_TYPE_EXCEPTION},
+	{"6rd_no_icme"				, NSS_STATS_TYPE_EXCEPTION},
+	{"6rd_ip_option"			, NSS_STATS_TYPE_EXCEPTION},
+	{"6rd_ip_fragment"			, NSS_STATS_TYPE_EXCEPTION},
+	{"6rd_needs_fragmentation"		, NSS_STATS_TYPE_EXCEPTION},
+	{"dscp_marking_mismatch"		, NSS_STATS_TYPE_EXCEPTION},
+	{"vlan_marking_mismatch"		, NSS_STATS_TYPE_EXCEPTION},
+	{"interface_mismatch"			, NSS_STATS_TYPE_EXCEPTION},
+	{"gre_header_incomplete"		, NSS_STATS_TYPE_EXCEPTION},
+	{"gre_no_icme"				, NSS_STATS_TYPE_EXCEPTION},
+	{"gre_ip_option"			, NSS_STATS_TYPE_EXCEPTION},
+	{"gre_ip_fragment"			, NSS_STATS_TYPE_EXCEPTION},
+	{"gre_small_ttl"			, NSS_STATS_TYPE_EXCEPTION},
+	{"gre_needs_fragmentation"		, NSS_STATS_TYPE_EXCEPTION},
+	{"pptp_gre_session_match_fail"		, NSS_STATS_TYPE_EXCEPTION},
+	{"pptp_gre_invalid_proto"		, NSS_STATS_TYPE_EXCEPTION},
+	{"pptp_gre_no_cme"			, NSS_STATS_TYPE_EXCEPTION},
+	{"pptp_gre_ip_option"			, NSS_STATS_TYPE_EXCEPTION},
+	{"pptp_gre_ip_fragment"			, NSS_STATS_TYPE_EXCEPTION},
+	{"pptp_gre_small_ttl"			, NSS_STATS_TYPE_EXCEPTION},
+	{"pptp_gre_needs_fragmentation"		, NSS_STATS_TYPE_EXCEPTION},
+	{"destroy"				, NSS_STATS_TYPE_EXCEPTION},
+	{"frag_df_set"				, NSS_STATS_TYPE_EXCEPTION},
+	{"frag_fail"				, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_ipv4_udplite_header_incomplete"	, NSS_STATS_TYPE_EXCEPTION},
+	{"udplite_header_incomplete"		, NSS_STATS_TYPE_EXCEPTION},
+	{"udplite_no_icme"			, NSS_STATS_TYPE_EXCEPTION},
+	{"udplite_ip_option"			, NSS_STATS_TYPE_EXCEPTION},
+	{"udplite_ip_fragment"			, NSS_STATS_TYPE_EXCEPTION},
+	{"udplite_small_ttl"			, NSS_STATS_TYPE_EXCEPTION},
+	{"udplite_needs_fragmentation"		, NSS_STATS_TYPE_EXCEPTION},
+	{"mc_udp_no_icme"			, NSS_STATS_TYPE_EXCEPTION},
+	{"mc_mem_alloc_failure"			, NSS_STATS_TYPE_EXCEPTION},
+	{"mc_update_failure"			, NSS_STATS_TYPE_EXCEPTION},
+	{"mc_pbuf_alloc_failure"		, NSS_STATS_TYPE_EXCEPTION},
+	{"pppoe_bridge_no_icme"			, NSS_STATS_TYPE_EXCEPTION},
+	{"pppoe_no_session"			, NSS_STATS_TYPE_DROP},
+	{"icmp_ipv4_gre_hdr_incomplete"		, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_ipv4_esp_hdr_incomplete"		, NSS_STATS_TYPE_EXCEPTION},
+	{"emesh_prio_mismatch"			, NSS_STATS_TYPE_EXCEPTION},
+	{"mc_ucast_dmac_failure"		, NSS_STATS_TYPE_EXCEPTION},
+};
+
+/*
+ * nss_ipv4_strings_stats
+ *	IPv4 statistics strings.
+ */
+struct nss_stats_info nss_ipv4_strings_stats[NSS_IPV4_STATS_MAX] = {
+	{"rx_pkts"			, NSS_STATS_TYPE_SPECIAL},
+	{"rx_bytes"			, NSS_STATS_TYPE_SPECIAL},
+	{"tx_pkts"			, NSS_STATS_TYPE_SPECIAL},
+	{"tx_bytes"			, NSS_STATS_TYPE_SPECIAL},
+	{"create_requests"		, NSS_STATS_TYPE_SPECIAL},
+	{"create_collisions"		, NSS_STATS_TYPE_SPECIAL},
+	{"create_invalid_interface"	, NSS_STATS_TYPE_SPECIAL},
+	{"destroy_requests"		, NSS_STATS_TYPE_SPECIAL},
+	{"destroy_misses"		, NSS_STATS_TYPE_SPECIAL},
+	{"hash_hits"			, NSS_STATS_TYPE_SPECIAL},
+	{"hash_reorders"		, NSS_STATS_TYPE_SPECIAL},
+	{"flushes"			, NSS_STATS_TYPE_SPECIAL},
+	{"evictions"			, NSS_STATS_TYPE_SPECIAL},
+	{"fragmentations"		, NSS_STATS_TYPE_SPECIAL},
+	{"by_rule_drops"		, NSS_STATS_TYPE_DROP},
+	{"mc_create_requests"		, NSS_STATS_TYPE_SPECIAL},
+	{"mc_update_requests"		, NSS_STATS_TYPE_SPECIAL},
+	{"mc_create_invalid_interface"	, NSS_STATS_TYPE_SPECIAL},
+	{"mc_destroy_requests"		, NSS_STATS_TYPE_SPECIAL},
+	{"mc_destroy_misses"		, NSS_STATS_TYPE_SPECIAL},
+	{"mc_flushes"			, NSS_STATS_TYPE_SPECIAL},
+	{"mirror_invalid_ifnum_conn_create_req"		, NSS_STATS_TYPE_SPECIAL},
+	{"mirror_invalid_iftype_conn_create_req"	, NSS_STATS_TYPE_SPECIAL},
+	{"mirror_failures"		, NSS_STATS_TYPE_SPECIAL},
+};
+
+/*
+ * nss_ipv4_special_stats_strings_read()
+ *	Read IPV4 special node statistics names.
+ */
+static ssize_t nss_ipv4_special_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_ipv4_strings_stats, NSS_IPV4_STATS_MAX);
+}
+
+/*
+ * nss_ipv4_exception_stats_strings_read()
+ *	Read IPV4 exception statistics names.
+ */
+static ssize_t nss_ipv4_exception_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_ipv4_strings_exception_stats, NSS_IPV4_EXCEPTION_EVENT_MAX);
+}
+
+/*
+ * nss_ipv4_special_stats_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(ipv4_special_stats);
+
+/*
+ * nss_ipv4_exception_stats_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(ipv4_exception_stats);
+
+/*
+ * nss_ipv4_strings_dentry_create()
+ *      Create IPv4 statistics strings debug entry.
+ */
+void nss_ipv4_strings_dentry_create(void)
+{
+	struct dentry *dir_d;
+	struct dentry *file_d;
+
+	if (!nss_top_main.strings_dentry) {
+		nss_warning("qca-nss-drv/strings is not present");
+		return;
+	}
+
+	dir_d = debugfs_create_dir("ipv4", nss_top_main.strings_dentry);
+	if (!dir_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/ipv4 directory");
+		return;
+	}
+
+	file_d = debugfs_create_file("special_stats_str", 0400, dir_d, &nss_top_main, &nss_ipv4_special_stats_strings_ops);
+	if (!file_d) {
+		nss_warning("Failed to create qca-nss-drv/stats/ipv4/special_stats_str file");
+		goto fail;
+	}
+
+	file_d = debugfs_create_file("exception_stats_str", 0400, dir_d, &nss_top_main, &nss_ipv4_exception_stats_strings_ops);
+	if (!file_d) {
+		nss_warning("Failed to create qca-nss-drv/stats/ipv4/exception_stats_str file");
+		goto fail;
+	}
+
+	return;
+fail:
+	debugfs_remove_recursive(dir_d);
+}
diff --git a/qca-nss-drv/nss_ipv4_strings.h b/qca-nss-drv/nss_ipv4_strings.h
new file mode 100644
index 0000000..fd819c7
--- /dev/null
+++ b/qca-nss-drv/nss_ipv4_strings.h
@@ -0,0 +1,26 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_IPV4_STRINGS_H
+#define __NSS_IPV4_STRINGS_H
+
+extern struct nss_stats_info nss_ipv4_strings_stats[NSS_IPV4_STATS_MAX];
+extern struct nss_stats_info nss_ipv4_strings_exception_stats[NSS_IPV4_EXCEPTION_EVENT_MAX];
+extern void nss_ipv4_strings_dentry_create(void);
+
+#endif /* __NSS_IPV4_STRINGS_H */
diff --git a/qca-nss-drv/nss_ipv6.c b/qca-nss-drv/nss_ipv6.c
new file mode 100644
index 0000000..2f9f14b
--- /dev/null
+++ b/qca-nss-drv/nss_ipv6.c
@@ -0,0 +1,776 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ipv6.c
+ *	NSS IPv6 APIs
+ */
+#include <nss_core.h>
+#include "nss_dscp_map.h"
+#include "nss_ipv6_stats.h"
+#include "nss_ipv6_strings.h"
+
+#define NSS_IPV6_TX_MSG_TIMEOUT 1000	/* 1 sec timeout for IPv6 messages */
+
+/*
+ * Private data structure for ipv6 configure messages
+ */
+struct nss_ipv6_cfg_pvt {
+	struct semaphore sem;		/* Semaphore structure */
+	struct completion complete;	/* Completion structure */
+	int response;			/* Response from FW */
+	void *cb;			/* Original cb for sync msgs */
+	void *app_data;			/* Original app_data for sync msgs */
+} nss_ipv6_pvt;
+
+/*
+ * Private data structure for ipv6 connection information.
+ */
+struct nss_ipv6_conn_table_info {
+	uint32_t ce_table_size;		/* Size of connection entry table in NSS FW */
+	uint32_t cme_table_size;	/* Size of connection match entry table in NSS FW */
+	unsigned long ce_mem;		/* Start address for connection entry table */
+	unsigned long cme_mem;		/* Start address for connection match entry table */
+} nss_ipv6_ct_info;
+
+int nss_ipv6_conn_cfg = NSS_DEFAULT_NUM_CONN;
+int nss_ipv6_accel_mode_cfg __read_mostly = 1;
+
+static struct nss_dscp_map_entry mapping[NSS_DSCP_MAP_ARRAY_SIZE];
+
+/*
+ * Callback for conn_sync_many request message.
+ */
+nss_ipv6_msg_callback_t nss_ipv6_conn_sync_many_msg_cb = NULL;
+
+/*
+ * nss_ipv6_dscp_map_usage()
+ *	Help function shows the usage of the command.
+ */
+static inline void nss_ipv6_dscp_map_usage(void)
+{
+	nss_info_always("\nUsage:\n");
+	nss_info_always("echo <dscp> <action> <prio> > /proc/sys/dev/nss/ipv6cfg/ipv6_dscp_map\n\n");
+	nss_info_always("dscp[0-63] action[0-%u] prio[0-%u]:\n\n",
+				NSS_IPV6_DSCP_MAP_ACTION_MAX - 1,
+				NSS_DSCP_MAP_PRIORITY_MAX - 1);
+}
+
+/*
+ * nss_ipv6_rx_msg_handler()
+ *	Handle NSS -> HLOS messages for IPv6 bridge/route
+ */
+static void nss_ipv6_rx_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_ipv6_msg *nim = (struct nss_ipv6_msg *)ncm;
+	nss_ipv6_msg_callback_t cb;
+
+	BUG_ON(ncm->interface != NSS_IPV6_RX_INTERFACE);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_IPV6_MAX_MSG_TYPES) {
+		nss_warning("%px: received invalid message %d for IPv6 interface", nss_ctx, nim->cm.type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_ipv6_msg)) {
+		nss_warning("%px: message length is invalid: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_ipv6_log_rx_msg(nim);
+
+	/*
+	 * Handle deprecated messages. Eventually these messages should be removed.
+	 */
+	switch (nim->cm.type) {
+	case NSS_IPV6_RX_NODE_STATS_SYNC_MSG:
+		/*
+		* Update driver statistics on node sync and send statistics notifications to the registered modules.
+		*/
+		nss_ipv6_stats_node_sync(nss_ctx, &nim->msg.node_stats);
+		nss_ipv6_stats_notify(nss_ctx);
+		break;
+
+	case NSS_IPV6_RX_CONN_STATS_SYNC_MSG:
+		/*
+		 * Update driver statistics on connection sync.
+		 */
+		nss_ipv6_stats_conn_sync(nss_ctx, &nim->msg.conn_stats);
+		break;
+
+	case NSS_IPV6_TX_CONN_STATS_SYNC_MANY_MSG:
+		/*
+		 * Update driver statistics on connection sync many.
+		 */
+		nss_ipv6_stats_conn_sync_many(nss_ctx, &nim->msg.conn_stats_many);
+		ncm->cb = (nss_ptr_t)nss_ipv6_conn_sync_many_msg_cb;
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, IPv6 sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (nim->cm.response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->ipv6_callback;
+		ncm->app_data = (nss_ptr_t)nss_ctx->nss_top->ipv6_ctx;
+	}
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * Callback
+	 */
+	cb = (nss_ipv6_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, nim);
+}
+
+/*
+ * nss_ipv6_tx_sync_callback()
+ *	Callback to handle the completion of synchronous tx messages.
+ */
+static void nss_ipv6_tx_sync_callback(void *app_data, struct nss_ipv6_msg *nim)
+{
+	nss_ipv6_msg_callback_t callback = (nss_ipv6_msg_callback_t)nss_ipv6_pvt.cb;
+	void *data = nss_ipv6_pvt.app_data;
+
+	nss_ipv6_pvt.cb = NULL;
+	nss_ipv6_pvt.app_data = NULL;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("ipv6 error response %d\n", nim->cm.response);
+		nss_ipv6_pvt.response = NSS_TX_FAILURE;
+	} else {
+		nss_ipv6_pvt.response = NSS_TX_SUCCESS;
+	}
+
+	if (callback) {
+		callback(data, nim);
+	}
+
+	complete(&nss_ipv6_pvt.complete);
+}
+
+/*
+ * nss_ipv6_dscp_action_get()
+ *	Gets the action mapped to dscp.
+ */
+enum nss_ipv6_dscp_map_actions nss_ipv6_dscp_action_get(uint8_t dscp)
+{
+	if (dscp >= NSS_DSCP_MAP_ARRAY_SIZE) {
+		nss_warning("dscp:%u invalid\n", dscp);
+		return NSS_IPV6_DSCP_MAP_ACTION_MAX;
+	}
+
+	return mapping[dscp].action;
+}
+EXPORT_SYMBOL(nss_ipv6_dscp_action_get);
+
+/*
+ * nss_ipv6_max_conn_count()
+ *	Return the maximum number of IPv6 connections that the NSS acceleration engine supports.
+ */
+int nss_ipv6_max_conn_count(void)
+{
+	return nss_ipv6_conn_cfg;
+}
+EXPORT_SYMBOL(nss_ipv6_max_conn_count);
+
+/*
+ * nss_ipv6_conn_inquiry()
+ *	Inquiry if a connection has been established in NSS FW
+ */
+nss_tx_status_t nss_ipv6_conn_inquiry(struct nss_ipv6_5tuple *ipv6_5t_p,
+				nss_ipv6_msg_callback_t cb)
+{
+	nss_tx_status_t nss_tx_status;
+	struct nss_ipv6_msg nim;
+	struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[0];
+
+	/*
+	 * Initialize inquiry message structure.
+	 * This is async message and the result will be returned
+	 * to the caller by the msg_callback passed in.
+	 */
+	memset(&nim, 0, sizeof(nim));
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE,
+			NSS_IPV6_TX_CONN_CFG_INQUIRY_MSG,
+			sizeof(struct nss_ipv6_inquiry_msg),
+			cb, NULL);
+	nim.msg.inquiry.rr.tuple = *ipv6_5t_p;
+	nss_tx_status = nss_ipv6_tx(nss_ctx, &nim);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Send inquiry message failed\n", ipv6_5t_p);
+	}
+
+	return nss_tx_status;
+}
+EXPORT_SYMBOL(nss_ipv6_conn_inquiry);
+
+/*
+ * nss_ipv6_tx_with_size()
+ *	Transmit an ipv6 message to the FW with a specified size.
+ */
+nss_tx_status_t nss_ipv6_tx_with_size(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_msg *nim, uint32_t size)
+{
+	struct nss_cmn_msg *ncm = &nim->cm;
+
+	/*
+	 * Sanity check the message
+	 */
+	if (ncm->interface != NSS_IPV6_RX_INTERFACE) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_IPV6_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_ipv6_log_tx_msg(nim);
+
+	return nss_core_send_cmd(nss_ctx, nim, sizeof(*nim), size);
+}
+EXPORT_SYMBOL(nss_ipv6_tx_with_size);
+
+/*
+ * nss_ipv6_tx()
+ *	Transmit an ipv6 message to the FW.
+ */
+nss_tx_status_t nss_ipv6_tx(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_msg *nim)
+{
+	return nss_ipv6_tx_with_size(nss_ctx, nim, NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_ipv6_tx);
+
+/*
+ * nss_ipv6_tx_sync()
+ *	Transmit a synchronous ipv6 message to the FW.
+ */
+nss_tx_status_t nss_ipv6_tx_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_msg *nim)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&nss_ipv6_pvt.sem);
+	nss_ipv6_pvt.cb = (void *)nim->cm.cb;
+	nss_ipv6_pvt.app_data = (void *)nim->cm.app_data;
+
+	nim->cm.cb = (nss_ptr_t)nss_ipv6_tx_sync_callback;
+	nim->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_ipv6_tx(nss_ctx, nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss ipv6 msg tx failed\n", nss_ctx);
+		up(&nss_ipv6_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&nss_ipv6_pvt.complete, msecs_to_jiffies(NSS_IPV6_TX_MSG_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: IPv6 tx sync failed due to timeout\n", nss_ctx);
+		nss_ipv6_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = nss_ipv6_pvt.response;
+	up(&nss_ipv6_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_ipv6_tx_sync);
+
+/*
+ **********************************
+ Register/Unregister/Miscellaneous APIs
+ **********************************
+ */
+
+/*
+ * nss_ipv6_notify_register()
+ *	Register to received IPv6 events.
+ *
+ * NOTE: Do we want to pass an nss_ctx here so that we can register for ipv6 on any core?
+ */
+struct nss_ctx_instance *nss_ipv6_notify_register(nss_ipv6_msg_callback_t cb, void *app_data)
+{
+	/*
+	 * TODO: We need to have a new array in support of the new API
+	 * TODO: If we use a per-context array, we would move the array into nss_ctx based.
+	 */
+	nss_top_main.ipv6_callback = cb;
+	nss_top_main.ipv6_ctx = app_data;
+	return &nss_top_main.nss[nss_top_main.ipv6_handler_id];
+}
+EXPORT_SYMBOL(nss_ipv6_notify_register);
+
+/*
+ * nss_ipv6_notify_unregister()
+ *	Unregister to received IPv6 events.
+ *
+ * NOTE: Do we want to pass an nss_ctx here so that we can register for ipv6 on any core?
+ */
+void nss_ipv6_notify_unregister(void)
+{
+	nss_top_main.ipv6_callback = NULL;
+}
+EXPORT_SYMBOL(nss_ipv6_notify_unregister);
+
+/*
+ * nss_ipv6_conn_sync_many_notify_register()
+ *	Register to receive IPv6 conn_sync_many message response.
+ */
+void nss_ipv6_conn_sync_many_notify_register(nss_ipv6_msg_callback_t cb)
+{
+	nss_ipv6_conn_sync_many_msg_cb = cb;
+}
+EXPORT_SYMBOL(nss_ipv6_conn_sync_many_notify_register);
+
+/*
+ * nss_ipv6_conn_sync_many_notify_unregister()
+ *	Unregister to receive IPv6 conn_sync_many message response.
+ */
+void nss_ipv6_conn_sync_many_notify_unregister(void)
+{
+	nss_ipv6_conn_sync_many_msg_cb = NULL;
+}
+EXPORT_SYMBOL(nss_ipv6_conn_sync_many_notify_unregister);
+
+/*
+ * nss_ipv6_get_mgr()
+ *
+ * TODO: This only suppports a single ipv6, do we ever want to support more?
+ */
+struct nss_ctx_instance *nss_ipv6_get_mgr(void)
+{
+	return (void *)&nss_top_main.nss[nss_top_main.ipv6_handler_id];
+}
+EXPORT_SYMBOL(nss_ipv6_get_mgr);
+
+/*
+ * nss_ipv6_register_handler()
+ *	Register our handler to receive messages for this interface
+ */
+void nss_ipv6_register_handler()
+{
+	struct nss_ctx_instance *nss_ctx = nss_ipv6_get_mgr();
+
+	if (nss_core_register_handler(nss_ctx, NSS_IPV6_RX_INTERFACE, nss_ipv6_rx_msg_handler, NULL) != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("IPv6 handler failed to register");
+	}
+
+	nss_ipv6_stats_dentry_create();
+	nss_ipv6_strings_dentry_create();
+}
+
+/*
+ * nss_ipv6_conn_cfg_process_callback()
+ *	Call back function for the ipv6 connection configuration process.
+ */
+static void nss_ipv6_conn_cfg_process_callback(void *app_data, struct nss_ipv6_msg *nim)
+{
+	struct nss_ipv6_rule_conn_cfg_msg *nirccm = &nim->msg.rule_conn_cfg;
+	struct nss_ctx_instance *nss_ctx __maybe_unused = nss_ipv6_get_mgr();
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("%px: IPv6 connection configuration failed with error: %d\n", nss_ctx, nim->cm.error);
+		nss_core_update_max_ipv6_conn(NSS_FW_DEFAULT_NUM_CONN);
+		nss_ipv6_free_conn_tables();
+		return;
+	}
+
+	nss_ipv6_conn_cfg = ntohl(nirccm->num_conn);
+
+	nss_info("%px: IPv6 connection configuration success: %d\n", nss_ctx, nim->cm.error);
+}
+
+/*
+ * nss_ipv6_conn_cfg_process()
+ *	Process request to configure number of ipv6 connections
+ */
+static int nss_ipv6_conn_cfg_process(struct nss_ctx_instance *nss_ctx, int conn)
+{
+	struct nss_ipv6_msg nim;
+	struct nss_ipv6_rule_conn_cfg_msg *nirccm;
+	nss_tx_status_t nss_tx_status;
+
+	if ((!nss_ipv6_ct_info.ce_table_size) || (!nss_ipv6_ct_info.cme_table_size)) {
+		nss_warning("%px: connection entry or connection match entry table size not available\n",
+				nss_ctx);
+		return -EINVAL;
+	}
+
+	nss_info("%px: IPv6 supported connections: %d\n", nss_ctx, conn);
+
+	nss_ipv6_ct_info.ce_mem = __get_free_pages(GFP_ATOMIC | __GFP_NOWARN | __GFP_ZERO,
+					get_order(nss_ipv6_ct_info.ce_table_size));
+	if (!nss_ipv6_ct_info.ce_mem) {
+		nss_warning("%px: Memory allocation failed for IPv6 Connections: %d\n",
+							nss_ctx,
+							conn);
+		goto fail;
+	}
+	nss_info("%px: CE Memory allocated for IPv6 Connections: %d\n",
+							nss_ctx,
+							conn);
+
+	nss_ipv6_ct_info.cme_mem = __get_free_pages(GFP_ATOMIC | __GFP_NOWARN | __GFP_ZERO,
+					get_order(nss_ipv6_ct_info.cme_table_size));
+	if (!nss_ipv6_ct_info.cme_mem) {
+		nss_warning("%px: Memory allocation failed for IPv6 Connections: %d\n",
+							nss_ctx,
+							conn);
+		goto fail;
+	}
+	nss_info("%px: CME Memory allocated for IPv6 Connections: %d\n",
+							nss_ctx,
+							conn);
+
+	memset(&nim, 0, sizeof(struct nss_ipv6_msg));
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_CONN_CFG_RULE_MSG,
+		sizeof(struct nss_ipv6_rule_conn_cfg_msg), nss_ipv6_conn_cfg_process_callback, NULL);
+
+	nirccm = &nim.msg.rule_conn_cfg;
+	nirccm->num_conn = htonl(conn);
+	nirccm->ce_mem = dma_map_single(nss_ctx->dev, (void *)nss_ipv6_ct_info.ce_mem, nss_ipv6_ct_info.ce_table_size, DMA_TO_DEVICE);
+	if (unlikely(dma_mapping_error(nss_ctx->dev, nirccm->ce_mem))) {
+		nss_warning("%px: DMA mapping failed for virtual address = %px", nss_ctx, (void *)nss_ipv6_ct_info.ce_mem);
+		goto fail;
+	}
+
+	nirccm->cme_mem = dma_map_single(nss_ctx->dev, (void *)nss_ipv6_ct_info.cme_mem, nss_ipv6_ct_info.cme_table_size, DMA_TO_DEVICE);
+	if (unlikely(dma_mapping_error(nss_ctx->dev, nirccm->cme_mem))) {
+		nss_warning("%px: DMA mapping failed for virtual address = %px", nss_ctx, (void *)nss_ipv6_ct_info.cme_mem);
+		goto fail;
+	}
+
+	nss_tx_status = nss_ipv6_tx(nss_ctx, &nim);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_tx error setting IPv6 Connections: %d\n",
+						nss_ctx,
+						conn);
+		goto fail;
+	}
+
+	return 0;
+
+fail:
+	nss_ipv6_free_conn_tables();
+	return -EINVAL;
+}
+
+/*
+ * nss_ipv6_update_conn_count_callback()
+ *	Call back function for the ipv6 get connection info message.
+ */
+static void nss_ipv6_update_conn_count_callback(void *app_data, struct nss_ipv6_msg *nim)
+{
+	struct nss_ipv6_rule_conn_get_table_size_msg *nircgts = &nim->msg.size;
+	struct nss_ctx_instance *nss_ctx = nss_ipv6_get_mgr();
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("%px: IPv6 fetch connection info failed with error: %d\n", nss_ctx, nim->cm.error);
+		nss_core_update_max_ipv6_conn(NSS_FW_DEFAULT_NUM_CONN);
+		return;
+	}
+
+	nss_info("IPv6 get connection info success\n");
+
+	nss_ipv6_ct_info.ce_table_size = ntohl(nircgts->ce_table_size);
+	nss_ipv6_ct_info.cme_table_size = ntohl(nircgts->cme_table_size);
+
+	if (nss_ipv6_conn_cfg_process(nss_ctx, ntohl(nircgts->num_conn)) != 0) {
+		nss_warning("%px: IPv6 connection entry or connection match entry table size\
+				not available\n", nss_ctx);
+	}
+
+	return;
+}
+
+/*
+ * nss_ipv6_update_conn_count()
+ *	Sets the maximum number of IPv6 connections.
+ *
+ * It first gets the connection tables size information from NSS FW
+ * and then configures the connections in NSS FW.
+ */
+int nss_ipv6_update_conn_count(int ipv6_num_conn)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ipv6_get_mgr();
+	struct nss_ipv6_msg nim;
+	struct nss_ipv6_rule_conn_get_table_size_msg *nircgts;
+	nss_tx_status_t nss_tx_status;
+	uint32_t sum_of_conn;
+
+	/*
+	 * By default, NSS FW is configured with default number of connections.
+	 */
+	if (ipv6_num_conn == NSS_FW_DEFAULT_NUM_CONN) {
+		nss_info("%px: Default number of connections (%d) already configured\n", nss_ctx, ipv6_num_conn);
+		return 0;
+	}
+
+	/*
+	 * Specifications for input
+	 * 1) The input should be power of 2.
+	 * 2) Input for ipv4 and ipv6 sum togther should not exceed 8k
+	 * 3) Min. value should be at leat 256 connections. This is the
+	 * minimum connections we will support for each of them.
+	 */
+	sum_of_conn = nss_ipv4_conn_cfg + ipv6_num_conn;
+	if ((ipv6_num_conn & NSS_NUM_CONN_QUANTA_MASK) ||
+		(sum_of_conn > NSS_MAX_TOTAL_NUM_CONN_IPV4_IPV6) ||
+		(ipv6_num_conn < NSS_MIN_NUM_CONN)) {
+		nss_warning("%px: input supported connections (%d) does not adhere\
+				specifications\n1) not power of 2,\n2) is less than \
+				min val: %d, OR\n	IPv4/6 total exceeds %d\n",
+				nss_ctx,
+				ipv6_num_conn,
+				NSS_MIN_NUM_CONN,
+				NSS_MAX_TOTAL_NUM_CONN_IPV4_IPV6);
+		return -EINVAL;
+	}
+
+	memset(&nim, 0, sizeof(struct nss_ipv6_msg));
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_CONN_TABLE_SIZE_MSG,
+		sizeof(struct nss_ipv6_rule_conn_get_table_size_msg), nss_ipv6_update_conn_count_callback, NULL);
+
+	nircgts = &nim.msg.size;
+	nircgts->num_conn = htonl(ipv6_num_conn);
+	nss_tx_status = nss_ipv6_tx(nss_ctx, &nim);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Send acceleration mode message failed\n", nss_ctx);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ipv6_free_conn_tables()
+ *	Frees memory allocated for connection tables
+ */
+void nss_ipv6_free_conn_tables(void)
+{
+	if (nss_ipv6_ct_info.ce_mem) {
+		free_pages(nss_ipv6_ct_info.ce_mem, get_order(nss_ipv6_ct_info.ce_table_size));
+	}
+
+	if (nss_ipv6_ct_info.cme_mem) {
+		free_pages(nss_ipv6_ct_info.cme_mem, get_order(nss_ipv6_ct_info.cme_table_size));
+	}
+
+	memset(&nss_ipv6_ct_info, 0, sizeof(struct nss_ipv6_conn_table_info));
+	return;
+}
+
+/*
+ * nss_ipv6_accel_mode_cfg_handler()
+ *	Configure acceleration mode for IPv6
+ */
+static int nss_ipv6_accel_mode_cfg_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[0];
+	struct nss_ipv6_msg nim;
+	struct nss_ipv6_accel_mode_cfg_msg *nipcm;
+	nss_tx_status_t nss_tx_status;
+	int ret = NSS_FAILURE;
+	int current_value;
+
+	/*
+	 * Take snap shot of current value
+	 */
+	current_value = nss_ipv6_accel_mode_cfg;
+
+	/*
+	 * Write the variable with user input
+	 */
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret || (!write)) {
+		return ret;
+	}
+
+	memset(&nim, 0, sizeof(struct nss_ipv6_msg));
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_ACCEL_MODE_CFG_MSG,
+		sizeof(struct nss_ipv6_accel_mode_cfg_msg), NULL, NULL);
+
+	nipcm = &nim.msg.accel_mode_cfg;
+	nipcm->mode = htonl(nss_ipv6_accel_mode_cfg);
+
+	nss_tx_status = nss_ipv6_tx_sync(nss_ctx, &nim);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Send acceleration mode message failed\n", nss_ctx);
+		nss_ipv6_accel_mode_cfg = current_value;
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ipv6_dscp_map_cfg_handler()
+ *	Sysctl handler for dscp/pri mappings.
+ */
+static int nss_ipv6_dscp_map_cfg_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[0];
+	struct nss_dscp_map_parse out;
+	struct nss_ipv6_msg nim;
+	struct nss_ipv6_dscp2pri_cfg_msg *nipd2p;
+	nss_tx_status_t status;
+	int ret;
+
+	if (!write) {
+		return nss_dscp_map_print(ctl, buffer, lenp, ppos, mapping);
+	}
+
+	ret = nss_dscp_map_parse(ctl, buffer, lenp, ppos, &out);
+	if (ret) {
+		nss_warning("failed to parse dscp mapping:%d\n", ret);
+		return ret;
+	}
+
+	if (out.action >= NSS_IPV6_DSCP_MAP_ACTION_MAX) {
+		nss_warning("invalid action value: %d\n", out.action);
+		nss_ipv6_dscp_map_usage();
+		return -EINVAL;
+	}
+
+	memset(&nim, 0, sizeof(struct nss_ipv6_msg));
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_DSCP2PRI_CFG_MSG,
+		sizeof(struct nss_ipv6_dscp2pri_cfg_msg), NULL, NULL);
+
+	nipd2p = &nim.msg.dscp2pri_cfg;
+	nipd2p->dscp = out.dscp;
+	nipd2p->priority = out.priority;
+
+	status = nss_ipv6_tx_sync(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: ipv6 dscp2pri config message failed\n", nss_ctx);
+		return -EFAULT;
+	}
+
+	/*
+	 * NSS firmware acknowleged the configuration, so update the mapping
+	 * table on HOST side as well.
+	 */
+	mapping[out.dscp].action = out.action;
+	mapping[out.dscp].priority = out.priority;
+
+	return 0;
+}
+
+static struct ctl_table nss_ipv6_table[] = {
+	{
+		.procname		= "ipv6_accel_mode",
+		.data			= &nss_ipv6_accel_mode_cfg,
+		.maxlen			= sizeof(int),
+		.mode			= 0644,
+		.proc_handler		= &nss_ipv6_accel_mode_cfg_handler,
+	},
+	{
+		.procname		= "ipv6_dscp_map",
+		.data			= &mapping[NSS_DSCP_MAP_ARRAY_SIZE],
+		.maxlen			= sizeof(struct nss_dscp_map_entry),
+		.mode			= 0644,
+		.proc_handler		= &nss_ipv6_dscp_map_cfg_handler,
+	},
+	{ }
+};
+
+static struct ctl_table nss_ipv6_dir[] = {
+	{
+		.procname		= "ipv6cfg",
+		.mode			= 0555,
+		.child			= nss_ipv6_table,
+	},
+	{ }
+};
+
+static struct ctl_table nss_ipv6_root_dir[] = {
+	{
+		.procname		= "nss",
+		.mode			= 0555,
+		.child			= nss_ipv6_dir,
+	},
+	{ }
+};
+
+static struct ctl_table nss_ipv6_root[] = {
+	{
+		.procname		= "dev",
+		.mode			= 0555,
+		.child			= nss_ipv6_root_dir,
+	},
+	{ }
+};
+
+static struct ctl_table_header *nss_ipv6_header;
+
+/*
+ * nss_ipv6_register_sysctl()
+ *	Register sysctl specific to ipv6
+ */
+void nss_ipv6_register_sysctl(void)
+{
+	sema_init(&nss_ipv6_pvt.sem, 1);
+	init_completion(&nss_ipv6_pvt.complete);
+
+	/*
+	 * Register sysctl table.
+	 */
+	nss_ipv6_header = register_sysctl_table(nss_ipv6_root);
+}
+
+/*
+ * nss_ipv6_unregister_sysctl()
+ *	Unregister sysctl specific to ipv6
+ */
+void nss_ipv6_unregister_sysctl(void)
+{
+	/*
+	 * Unregister sysctl table.
+	 */
+	if (nss_ipv6_header) {
+		unregister_sysctl_table(nss_ipv6_header);
+	}
+}
+
+/*
+ * nss_ipv6_msg_init()
+ *	Initialize IPv6 message.
+ */
+void nss_ipv6_msg_init(struct nss_ipv6_msg *nim, uint16_t if_num, uint32_t type, uint32_t len,
+			nss_ipv6_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&nim->cm, if_num, type, len, (void *)cb, app_data);
+}
+EXPORT_SYMBOL(nss_ipv6_msg_init);
diff --git a/qca-nss-drv/nss_ipv6_log.c b/qca-nss-drv/nss_ipv6_log.c
new file mode 100644
index 0000000..ed60610
--- /dev/null
+++ b/qca-nss-drv/nss_ipv6_log.c
@@ -0,0 +1,387 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016, 2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ipv6_log.c
+ *	NSS IPv6 logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * This macro converts IPv6 address to network format
+ */
+#define NSS_IPV6_ADDR_TO_NW(nss6, nw) \
+	{ \
+		nw[0] = htonl(nss6[0]); \
+		nw[1] = htonl(nss6[1]); \
+		nw[2] = htonl(nss6[2]); \
+		nw[3] = htonl(nss6[3]); \
+	}
+
+/*
+ * nss_ipv6_log_message_types_str
+ *	IPv6 bridge/route rule messages strings
+ */
+static int8_t *nss_ipv6_log_message_types_str[NSS_IPV6_MAX_MSG_TYPES] __maybe_unused = {
+	"IPv6 create rule message",
+	"IPv6 destroy rule message",
+	"Deprecated: NSS_IPV4_RX_ESTABLISH_RULE_MSG",
+	"IPv6 connection stats sync message",
+	"IPv6 generic statistics sync message",
+	"IPv6 number of connections supported rule message",
+	"IPv6 multicast create rule message",
+	"IPv6 request FW to send many conn sync message",
+};
+
+/*
+ * nss_ipv6_log_error_response_types_str
+ *	Strings for error types for ipv6 messages
+ */
+static int8_t *nss_ipv6_log_error_response_types_str[] __maybe_unused = {
+	"No error",
+	"Unknown error",
+	"Invalid interface number",
+	"Missing connection rule",
+	"Buffer allocation failure",
+	"No connection found to delete",
+	"Conn cfg already done once",
+	"Conn cfg input is not multiple of quanta",
+	"Conn cfg input exceeds max supported connections",
+	"Conn cfg mem alloc fail at NSS FW",
+	"Invalid L4 protocol for multicast rule create",
+	"Invalid multicast flags for multicast update",
+	"Invalid interface for multicast update",
+};
+
+/*
+ * nss_ipv6_log_rule_create_msg()
+ *	Log IPv6 create rule message.
+ */
+static void nss_ipv6_log_rule_create_msg(struct nss_ipv6_msg *nim)
+{
+	uint32_t src_ip[4];
+	uint32_t dest_ip[4];
+	struct nss_ipv6_rule_create_msg *nircm = &nim->msg.rule_create;
+
+	NSS_IPV6_ADDR_TO_NW(nircm->tuple.flow_ip, src_ip);
+	NSS_IPV6_ADDR_TO_NW(nircm->tuple.return_ip, dest_ip);
+
+	nss_trace("%px: IPv6 create rule message \n"
+		"Protocol: %d\n"
+		"from_mtu: %u\n"
+		"to_mtu: %u\n"
+		"from_ip: %pI6:%d\n"
+		"to_ip: %pI6:%d\n"
+		"from_mac: %pM\n"
+		"to_mac: %pM\n"
+		"src_iface_num: %u\n"
+		"dest_iface_num: %u\n"
+		"ingress_inner_vlan_tag: %u\n"
+		"egress_inner_vlan_tag: %u\n"
+		"ingress_outer_vlan_tag: %u\n"
+		"egress_outer_vlan_tag: %u\n"
+		"rule_flags: %x\n"
+		"valid_flags: %x\n"
+		"return_pppoe_if_exist: %u\n"
+		"return_pppoe_if_num: %u\n"
+		"flow_pppoe_if_exist: %u\n"
+		"flow_pppoe_if_num: %u\n"
+		"flow_qos_tag: %x (%u)\n"
+		"return_qos_tag: %x (%u)\n"
+		"flow_dscp: %x\n"
+		"return_dscp: %x\n"
+		"flow_mirror_ifnum: %u\n"
+		"return_mirror_ifnum: %u\n",
+		nim,
+		nircm->tuple.protocol,
+		nircm->conn_rule.flow_mtu,
+		nircm->conn_rule.return_mtu,
+		src_ip, nircm->tuple.flow_ident,
+		dest_ip, nircm->tuple.return_ident,
+		nircm->conn_rule.flow_mac,
+		nircm->conn_rule.return_mac,
+		nircm->conn_rule.flow_interface_num,
+		nircm->conn_rule.return_interface_num,
+		nircm->vlan_primary_rule.ingress_vlan_tag,
+		nircm->vlan_primary_rule.egress_vlan_tag,
+		nircm->vlan_secondary_rule.ingress_vlan_tag,
+		nircm->vlan_secondary_rule.egress_vlan_tag,
+		nircm->rule_flags,
+		nircm->valid_flags,
+		nircm->pppoe_rule.return_if_exist,
+		nircm->pppoe_rule.return_if_num,
+		nircm->pppoe_rule.flow_if_exist,
+		nircm->pppoe_rule.flow_if_num,
+		nircm->qos_rule.flow_qos_tag, nircm->qos_rule.flow_qos_tag,
+		nircm->qos_rule.return_qos_tag, nircm->qos_rule.return_qos_tag,
+		nircm->dscp_rule.flow_dscp,
+		nircm->dscp_rule.return_dscp,
+		nircm->mirror_rule.flow_ifnum,
+		nircm->mirror_rule.return_ifnum);
+}
+
+/*
+ * nss_ipv6_log_destroy_rule_msg()
+ *	Log IPv6 destroy rule message.
+ */
+static void nss_ipv6_log_destroy_rule_msg(struct nss_ipv6_msg *nim)
+{
+	uint32_t src_ip[4];
+	uint32_t dest_ip[4];
+	struct nss_ipv6_rule_destroy_msg *nirdm = &nim->msg.rule_destroy;
+
+	NSS_IPV6_ADDR_TO_NW(nirdm->tuple.flow_ip, src_ip);
+	NSS_IPV6_ADDR_TO_NW(nirdm->tuple.return_ip, dest_ip);
+
+	nss_trace("%px: IPv6 destroy rule message: \n"
+		"flow_ip: %pI6:%d\n"
+		"return_ip: %pI6:%d\n"
+		"protocol: %d\n",
+		nim,
+		src_ip, nirdm->tuple.flow_ident,
+		dest_ip, nirdm->tuple.return_ident,
+		nirdm->tuple.protocol);
+}
+
+/*
+ * nss_ipv6_log_conn_sync()
+ *	Log IPv6 connection stats sync message.
+ */
+static void nss_ipv6_log_conn_sync(struct nss_ipv6_msg *nim)
+{
+	struct nss_ipv6_conn_sync *sync = &nim->msg.conn_stats;
+	if (sync->flow_tx_packet_count || sync->return_tx_packet_count) {
+		uint32_t src_ip[4];
+		uint32_t dest_ip[4];
+
+		NSS_IPV6_ADDR_TO_NW(sync->flow_ip, src_ip);
+		NSS_IPV6_ADDR_TO_NW(sync->return_ip, dest_ip);
+
+		nss_trace("%px: IPv6 connection stats sync message: \n"
+			"Protocol: %d\n"
+			"src_addr: %pI6:%d\n"
+			"dest_addr: %pI6:%d\n"
+			"flow_rx_packet_count: %u\n"
+			"flow_rx_byte_count: %u\n"
+			"return_rx_packet_count: %u\n"
+			"return_rx_byte_count: %u\n"
+			"flow_tx_packet_count: %u\n"
+			"flow_tx_byte_count: %u\n"
+			"return_tx_packet_count: %u\n"
+			"return_tx_byte_count: %u\n",
+			nim,
+			(int)sync->protocol,
+			src_ip, (int)sync->flow_ident,
+			dest_ip, (int)sync->return_ident,
+			sync->flow_rx_packet_count,
+			sync->flow_rx_byte_count,
+			sync->return_rx_packet_count,
+			sync->return_rx_byte_count,
+			sync->flow_tx_packet_count,
+			sync->flow_tx_byte_count,
+			sync->return_tx_packet_count,
+			sync->return_tx_byte_count);
+		}
+}
+
+/*
+ * nss_ipv6_log_conn_cfg_msg()
+ *	Log IPv6 number of connections supported rule message.
+ */
+static void nss_ipv6_log_conn_cfg_msg(struct nss_ipv6_msg *nim)
+{
+	struct nss_ipv6_rule_conn_cfg_msg *nirccm __maybe_unused = &nim->msg.rule_conn_cfg;
+	nss_trace("%px: IPv6 number of connections supported rule message: \n"
+		"num_conn: %d\n",
+		nim,
+		nirccm->num_conn);
+}
+
+/*
+ * nss_ipv6_log_mc_rule_create_msg()
+ *	Log IPv6 multicast create rule message.
+ */
+static void nss_ipv6_log_mc_rule_create_msg(struct nss_ipv6_msg *nim)
+{
+	uint16_t vif;
+	uint32_t src_ip[4];
+	uint32_t dest_ip[4];
+	struct nss_ipv6_mc_rule_create_msg *nimrcm = &nim->msg.mc_rule_create;
+
+	NSS_IPV6_ADDR_TO_NW(nimrcm->tuple.flow_ip, src_ip);
+	NSS_IPV6_ADDR_TO_NW(nimrcm->tuple.return_ip, dest_ip);
+
+	for (vif = 0; vif < nimrcm->if_count ; vif++) {
+		nss_trace("%px: IPv6 multicast create rule message \n"
+			"Rule flag: %x\n"
+			"Vif: %d\n"
+			"Protocol: %d\n"
+			"to_mtu: %u\n"
+			"from_ip: %pI6:%d\n"
+			"to_ip: %pI6:%d\n"
+			"to_mac: %pM\n"
+			"dest_iface_num: %u\n"
+			"out_vlan[0] %x\n"
+			"out_vlan[1] %x\n",
+			nim,
+			nimrcm->if_rule[vif].rule_flags,
+			vif,
+			nimrcm->tuple.protocol,
+			nimrcm->if_rule[vif].if_mtu,
+			src_ip, nimrcm->tuple.flow_ident,
+			dest_ip, nimrcm->tuple.return_ident,
+			nimrcm->if_rule[vif].if_mac,
+			nimrcm->if_rule[vif].if_num,
+			nimrcm->if_rule[vif].egress_vlan_tag[0],
+			nimrcm->if_rule[vif].egress_vlan_tag[1]);
+	}
+}
+
+/*
+ * nss_ipv6_log_conn_sync_many_msg()
+ *	Log IPv6 many conn sync message.
+ */
+static void nss_ipv6_log_conn_sync_many_msg(struct nss_ipv6_msg *nim)
+{
+	uint16_t i;
+	struct nss_ipv6_conn_sync_many_msg *nicsm = &nim->msg.conn_stats_many;
+	for (i = 0; i < nicsm->count; i++) {
+		struct nss_ipv6_conn_sync *sync = &nicsm->conn_sync[i];
+		if (sync->flow_tx_packet_count || sync->return_tx_packet_count) {
+			uint32_t src_ip[4];
+			uint32_t dest_ip[4];
+
+			NSS_IPV6_ADDR_TO_NW(sync->flow_ip, src_ip);
+			NSS_IPV6_ADDR_TO_NW(sync->return_ip, dest_ip);
+
+			nss_trace("%px: IPv6 many conn sync message \n"
+				"count: %d\n"
+				"i: %d\n"
+				"Protocol: %d\n"
+				"src_addr: %pI6:%d\n"
+				"dest_addr: %pI6:%d\n"
+				"flow_rx_packet_count: %u\n"
+				"flow_rx_byte_count: %u\n"
+				"return_rx_packet_count: %u\n"
+				"return_rx_byte_count: %u\n"
+				"flow_tx_packet_count: %u\n"
+				"flow_tx_byte_count: %u\n"
+				"return_tx_packet_count: %u\n"
+				"return_tx_byte_count: %u\n",
+				nim,
+				nicsm->count,
+				i,
+				(int)sync->protocol,
+				src_ip, (int)sync->flow_ident,
+				dest_ip, (int)sync->return_ident,
+				sync->flow_rx_packet_count,
+				sync->flow_rx_byte_count,
+				sync->return_rx_packet_count,
+				sync->return_rx_byte_count,
+				sync->flow_tx_packet_count,
+				sync->flow_tx_byte_count,
+				sync->return_tx_packet_count,
+				sync->return_tx_byte_count);
+		}
+	}
+}
+
+/*
+ * nss_ipv6_log_verbose()
+ *	Log message contents.
+ */
+static void nss_ipv6_log_verbose(struct nss_ipv6_msg *nim)
+{
+	switch (nim->cm.type) {
+	case NSS_IPV6_TX_CREATE_RULE_MSG:
+		nss_ipv6_log_rule_create_msg(nim);
+		break;
+
+	case NSS_IPV6_TX_DESTROY_RULE_MSG:
+		nss_ipv6_log_destroy_rule_msg(nim);
+		break;
+
+	case NSS_IPV6_RX_CONN_STATS_SYNC_MSG:
+		nss_ipv6_log_conn_sync(nim);
+		break;
+
+	case NSS_IPV6_RX_NODE_STATS_SYNC_MSG:
+		/* Getting logged in stats */
+		break;
+
+	case NSS_IPV6_TX_CONN_CFG_RULE_MSG:
+		nss_ipv6_log_conn_cfg_msg(nim);
+		break;
+
+	case NSS_IPV6_TX_CREATE_MC_RULE_MSG:
+		nss_ipv6_log_mc_rule_create_msg(nim);
+		break;
+
+	case NSS_IPV6_TX_CONN_STATS_SYNC_MANY_MSG:
+		nss_ipv6_log_conn_sync_many_msg(nim);
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", nim);
+		break;
+	}
+}
+
+/*
+ * nss_ipv6_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_ipv6_log_tx_msg(struct nss_ipv6_msg *nim)
+{
+	nss_info("%px: type[%d]: %s\n", nim, nim->cm.type, nss_ipv6_log_message_types_str[nim->cm.type]);
+	nss_ipv6_log_verbose(nim);
+}
+
+/*
+ * nss_ipv6_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_ipv6_log_rx_msg(struct nss_ipv6_msg *nim)
+{
+	if (nim->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_info("%px: Invalid response\n", nim);
+		return;
+	}
+
+	if (nim->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nim->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]: %s, response[%d]: %s\n", nim, nim->cm.type,
+			nss_ipv6_log_message_types_str[nim->cm.type],
+			nim->cm.response, nss_cmn_response_str[nim->cm.response]);
+		goto verbose;
+	}
+
+	if (nim->cm.error > NSS_IPV6_CR_MULTICAST_UPDATE_INVALID_IF) {
+		nss_info("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			nim, nim->cm.type, nss_ipv6_log_message_types_str[nim->cm.type],
+			nim->cm.response, nss_cmn_response_str[nim->cm.response],
+			nim->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		nim, nim->cm.type, nss_ipv6_log_message_types_str[nim->cm.type],
+		nim->cm.response, nss_cmn_response_str[nim->cm.response],
+		nim->cm.error, nss_ipv6_log_error_response_types_str[nim->cm.error]);
+
+verbose:
+	nss_ipv6_log_verbose(nim);
+}
diff --git a/qca-nss-drv/nss_ipv6_reasm.c b/qca-nss-drv/nss_ipv6_reasm.c
new file mode 100644
index 0000000..4ad8a7c
--- /dev/null
+++ b/qca-nss-drv/nss_ipv6_reasm.c
@@ -0,0 +1,72 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015,2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ipv6_reasm.c
+ *	NSS IPv6 Reassembly APIs
+ */
+#include <nss_core.h>
+#include "nss_ipv6_reasm_stats.h"
+#include "nss_ipv6_reasm_strings.h"
+
+/*
+ * nss_ipv6_reasm_msg_handler()
+ *	Handle NSS -> HLOS messages for IPv6 reasm
+ */
+static void nss_ipv6_reasm_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_ipv6_reasm_msg *nim = (struct nss_ipv6_reasm_msg *)ncm;
+
+	BUG_ON(ncm->interface != NSS_IPV6_REASM_INTERFACE);
+
+	switch (nim->cm.type) {
+	case NSS_IPV6_REASM_STATS_SYNC_MSG:
+		/*
+		 * Update driver statistics on node sync and send statistics notifications to the registered modules.
+		 */
+		nss_ipv6_reasm_stats_sync(nss_ctx, &nim->msg.stats_sync);
+		nss_ipv6_reasm_stats_notify(nss_ctx);
+		break;
+	default:
+		nss_warning("IPv6 reasm received an unknown message type");
+	}
+}
+
+/*
+ * nss_ipv6_reasm_get_context()
+ * 	get NSS context instance for ipv6 reassembly
+ */
+struct nss_ctx_instance *nss_ipv6_reasm_get_context(void)
+{
+	return &nss_top_main.nss[nss_top_main.ipv6_reasm_handler_id];
+}
+EXPORT_SYMBOL(nss_ipv6_reasm_get_context);
+
+/*
+ * nss_ipv6_reasm_register_handler()
+ *	Register our handler to receive messages for this interface
+ */
+void nss_ipv6_reasm_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ipv6_reasm_get_context();
+
+	if (nss_core_register_handler(nss_ctx, NSS_IPV6_REASM_INTERFACE, nss_ipv6_reasm_msg_handler, NULL) != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("IPv6 reasm handler failed to register");
+	}
+
+	nss_ipv6_reasm_stats_dentry_create();
+	nss_ipv6_reasm_strings_dentry_create();
+}
diff --git a/qca-nss-drv/nss_ipv6_reasm_stats.c b/qca-nss-drv/nss_ipv6_reasm_stats.c
new file mode 100644
index 0000000..d376f5a
--- /dev/null
+++ b/qca-nss-drv/nss_ipv6_reasm_stats.c
@@ -0,0 +1,167 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017,2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_ipv6_reasm_stats.h"
+#include "nss_ipv6_reasm.h"
+#include "nss_ipv6_reasm_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_ipv6_reasm_stats_notifier);
+
+uint64_t nss_ipv6_reasm_stats[NSS_IPV6_REASM_STATS_MAX]; /* IPv6 reasm statistics */
+
+/*
+ * nss_ipv6_reasm_stats_read()
+ *	Read IPV6 reassembly stats
+ */
+static ssize_t nss_ipv6_reasm_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+	/*
+	 * Max output lines = #stats + few blank lines for banner printing +
+	 * Number of Extra outputlines for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_STATS_NODE_MAX + NSS_IPV6_REASM_STATS_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_IPV6_REASM_STATS_MAX * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "ipv6_reasm", NSS_STATS_SINGLE_CORE);
+
+	size_wr += nss_stats_fill_common_stats(NSS_IPV6_REASM_INTERFACE, NSS_STATS_SINGLE_INSTANCE, lbuf, size_wr, size_al, "ipv6_reasm");
+
+	/*
+	 * Ipv6 reasm node stats
+	 */
+
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; (i < NSS_IPV6_REASM_STATS_MAX); i++) {
+		stats_shadow[i] = nss_ipv6_reasm_stats[i];
+	}
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+
+	size_wr += nss_stats_print("ipv6_reasm", NULL, NSS_STATS_SINGLE_INSTANCE
+					, nss_ipv6_reasm_strings_stats
+					, stats_shadow
+					, NSS_IPV6_REASM_STATS_MAX
+					, lbuf, size_wr, size_al);
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_ipv6_reasm_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(ipv6_reasm);
+
+/*
+ * nss_ipv6_reasm_stats_dentry_create()
+ *	Create IPv6 reasm statistics debug entry.
+ */
+void nss_ipv6_reasm_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("ipv6_reasm", &nss_ipv6_reasm_stats_ops);
+}
+
+/*
+ * nss_ipv6_reasm_stats_sync()
+ *	Update driver specific information from the messsage.
+ */
+void nss_ipv6_reasm_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_reasm_stats_sync *nirs)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	int j;
+
+	spin_lock_bh(&nss_top->stats_lock);
+
+	/*
+	 * Common node stats
+	 */
+	nss_top->stats_node[NSS_IPV6_REASM_INTERFACE][NSS_STATS_NODE_RX_PKTS] += nirs->node_stats.rx_packets;
+	nss_top->stats_node[NSS_IPV6_REASM_INTERFACE][NSS_STATS_NODE_RX_BYTES] += nirs->node_stats.rx_bytes;
+	nss_top->stats_node[NSS_IPV6_REASM_INTERFACE][NSS_STATS_NODE_TX_PKTS] += nirs->node_stats.tx_packets;
+	nss_top->stats_node[NSS_IPV6_REASM_INTERFACE][NSS_STATS_NODE_TX_BYTES] += nirs->node_stats.tx_bytes;
+
+	for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+		nss_top->stats_node[NSS_IPV6_REASM_INTERFACE][NSS_STATS_NODE_RX_QUEUE_0_DROPPED + j] += nirs->node_stats.rx_dropped[j];
+	}
+
+	/*
+	 * IPv6 reasm node stats
+	 */
+	nss_ipv6_reasm_stats[NSS_IPV6_REASM_STATS_ALLOC_FAILS] += nirs->ipv6_reasm_alloc_fails;
+	nss_ipv6_reasm_stats[NSS_IPV6_REASM_STATS_TIMEOUTS] += nirs->ipv6_reasm_timeouts;
+	nss_ipv6_reasm_stats[NSS_IPV6_REASM_STATS_DISCARDS] += nirs->ipv6_reasm_discards;
+
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_ipv6_reasm_stats_notify()
+ *	Sends notifications to the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_ipv6_reasm_stats_notify(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_ipv6_reasm_stats_notification ipv6_reasm_stats;
+
+	ipv6_reasm_stats.core_id = nss_ctx->id;
+	memcpy(ipv6_reasm_stats.cmn_node_stats, nss_top_main.stats_node[NSS_IPV6_REASM_INTERFACE], sizeof(ipv6_reasm_stats.cmn_node_stats));
+	memcpy(ipv6_reasm_stats.ipv6_reasm_stats, nss_ipv6_reasm_stats, sizeof(ipv6_reasm_stats.ipv6_reasm_stats));
+	atomic_notifier_call_chain(&nss_ipv6_reasm_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&ipv6_reasm_stats);
+}
+
+/*
+ * nss_ipv6_reasm_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_ipv6_reasm_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_ipv6_reasm_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_ipv6_reasm_stats_register_notifier);
+
+/*
+ * nss_ipv6_reasm_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_ipv6_reasm_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_ipv6_reasm_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_ipv6_reasm_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_ipv6_reasm_stats.h b/qca-nss-drv/nss_ipv6_reasm_stats.h
new file mode 100644
index 0000000..cdae314
--- /dev/null
+++ b/qca-nss-drv/nss_ipv6_reasm_stats.h
@@ -0,0 +1,27 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017,2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_IPV6_REASM_STATS_H
+#define __NSS_IPV6_REASM_STATS_H
+
+/*
+ * NSS IPv6 reasm statistics APIs
+ */
+extern void nss_ipv6_reasm_stats_notify(struct nss_ctx_instance *nss_ctx);
+extern void nss_ipv6_reasm_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_reasm_stats_sync *nirs);
+extern void nss_ipv6_reasm_stats_dentry_create(void);
+
+#endif /* __NSS_IPV6_REASM_STATS_H */
diff --git a/qca-nss-drv/nss_ipv6_reasm_strings.c b/qca-nss-drv/nss_ipv6_reasm_strings.c
new file mode 100644
index 0000000..7b6436a
--- /dev/null
+++ b/qca-nss-drv/nss_ipv6_reasm_strings.c
@@ -0,0 +1,55 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include <nss_ipv6_reasm.h>
+#include "nss_strings.h"
+
+/*
+ * nss_ipv6_reasm_strings_stats
+ *	IPv6 reassembly statistics strings.
+ */
+struct nss_stats_info nss_ipv6_reasm_strings_stats[NSS_IPV6_REASM_STATS_MAX] = {
+	{"alloc_fails"	, NSS_STATS_TYPE_DROP},
+	{"timeouts"	, NSS_STATS_TYPE_DROP},
+	{"discards"	, NSS_STATS_TYPE_DROP}
+};
+
+/*
+ * nss_ipv6_reasm_strings_read()
+ *	Read IPv6 reassembly node statistics names.
+ */
+static ssize_t nss_ipv6_reasm_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_ipv6_reasm_strings_stats, NSS_IPV6_REASM_STATS_MAX);
+}
+
+/*
+ * nss_ipv6_reasm_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(ipv6_reasm);
+
+/*
+ * nss_ipv6_reasm_strings_dentry_create()
+ *      Create IPv6 reassembly statistics strings debug entry.
+ */
+void nss_ipv6_reasm_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("ipv6_reasm", &nss_ipv6_reasm_strings_ops);
+}
diff --git a/qca-nss-drv/nss_ipv6_reasm_strings.h b/qca-nss-drv/nss_ipv6_reasm_strings.h
new file mode 100644
index 0000000..6cac544
--- /dev/null
+++ b/qca-nss-drv/nss_ipv6_reasm_strings.h
@@ -0,0 +1,25 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_IPV6_REASM_STRINGS_H
+#define __NSS_IPV6_REASM_STRINGS_H
+
+extern struct nss_stats_info nss_ipv6_reasm_strings_stats[NSS_IPV6_REASM_STATS_MAX];
+extern void nss_ipv6_reasm_strings_dentry_create(void);
+
+#endif /* __NSS_IPV6_REASM_STRINGS_H */
diff --git a/qca-nss-drv/nss_ipv6_stats.c b/qca-nss-drv/nss_ipv6_stats.c
new file mode 100644
index 0000000..617f55b
--- /dev/null
+++ b/qca-nss-drv/nss_ipv6_stats.c
@@ -0,0 +1,243 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2019-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include <nss_ipv6.h>
+#include "nss_ipv6_stats.h"
+#include "nss_ipv6_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_ipv6_stats_notifier);
+
+uint64_t nss_ipv6_stats[NSS_IPV6_STATS_MAX];
+uint64_t nss_ipv6_exception_stats[NSS_IPV6_EXCEPTION_EVENT_MAX];
+
+/*
+ * nss_ipv6_stats_read()
+ *	Read IPV6 stats.
+ */
+static ssize_t nss_ipv6_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * max output lines = #stats + Number of Extra outputlines for future reference to add new stats +
+	 * start tag line + end tag line + three blank lines.
+	 */
+	uint32_t max_output_lines = NSS_STATS_NODE_MAX + NSS_IPV6_STATS_MAX + NSS_IPV6_EXCEPTION_EVENT_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	/*
+	 * Note: The assumption here is that exception event count is larger than other statistics count for IPv6.
+	 */
+	stats_shadow = kzalloc(NSS_IPV6_EXCEPTION_EVENT_MAX * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "ipv6", NSS_STATS_SINGLE_CORE);
+	size_wr += nss_stats_fill_common_stats(NSS_IPV6_RX_INTERFACE, NSS_STATS_SINGLE_INSTANCE, lbuf, size_wr, size_al, "ipv6");
+
+	/*
+	 * IPv6 node stats
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; (i < NSS_IPV6_STATS_MAX); i++) {
+		stats_shadow[i] = nss_ipv6_stats[i];
+	}
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+
+	size_wr += nss_stats_print("ipv6", "ipv6 node stats", NSS_STATS_SINGLE_INSTANCE
+					, nss_ipv6_strings_stats
+					, stats_shadow
+					, NSS_IPV6_STATS_MAX
+					, lbuf, size_wr, size_al);
+
+	/*
+	 * Exception stats
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; (i < NSS_IPV6_EXCEPTION_EVENT_MAX); i++) {
+		stats_shadow[i] = nss_ipv6_exception_stats[i];
+	}
+	spin_unlock_bh(&nss_top_main.stats_lock);
+
+	size_wr += nss_stats_print("ipv6", "ipv6 exception stats", NSS_STATS_SINGLE_INSTANCE
+					, nss_ipv6_strings_exception_stats
+					, stats_shadow
+					, NSS_IPV6_EXCEPTION_EVENT_MAX
+					, lbuf, size_wr, size_al);
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_ipv6_stats_conn_sync()
+ *	Update driver specific information from the messsage.
+ */
+void nss_ipv6_stats_conn_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_conn_sync *nics)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+
+	/*
+	 * Update statistics maintained by NSS driver
+	 */
+	spin_lock_bh(&nss_top->stats_lock);
+	nss_ipv6_stats[NSS_IPV6_STATS_ACCELERATED_RX_PKTS] += nics->flow_rx_packet_count + nics->return_rx_packet_count;
+	nss_ipv6_stats[NSS_IPV6_STATS_ACCELERATED_RX_BYTES] += nics->flow_rx_byte_count + nics->return_rx_byte_count;
+	nss_ipv6_stats[NSS_IPV6_STATS_ACCELERATED_TX_PKTS] += nics->flow_tx_packet_count + nics->return_tx_packet_count;
+	nss_ipv6_stats[NSS_IPV6_STATS_ACCELERATED_TX_BYTES] += nics->flow_tx_byte_count + nics->return_tx_byte_count;
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_ipv6_stats_conn_sync_many()
+ *	Update driver specific information from the conn_sync_many messsage.
+ */
+void nss_ipv6_stats_conn_sync_many(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_conn_sync_many_msg *nicsm)
+{
+	uint32_t i;
+
+	/*
+	 * Sanity check for the stats count
+	 */
+	if (nicsm->count * sizeof(struct nss_ipv6_conn_sync) >= nicsm->size) {
+		nss_warning("%px: stats sync count %u exceeds the size of this msg %u", nss_ctx, nicsm->count, nicsm->size);
+		return;
+	}
+
+	for (i = 0; i < nicsm->count; i++) {
+		nss_ipv6_stats_conn_sync(nss_ctx, &nicsm->conn_sync[i]);
+	}
+}
+
+/*
+ * nss_ipv6_stats_node_sync()
+ *	Update driver specific information from the messsage.
+ */
+void nss_ipv6_stats_node_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_node_sync *nins)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	uint32_t i;
+
+	/*
+	 * Update statistics maintained by NSS driver
+	 */
+	spin_lock_bh(&nss_top->stats_lock);
+	nss_top->stats_node[NSS_IPV6_RX_INTERFACE][NSS_STATS_NODE_RX_PKTS] += nins->node_stats.rx_packets;
+	nss_top->stats_node[NSS_IPV6_RX_INTERFACE][NSS_STATS_NODE_RX_BYTES] += nins->node_stats.rx_bytes;
+	nss_top->stats_node[NSS_IPV6_RX_INTERFACE][NSS_STATS_NODE_TX_PKTS] += nins->node_stats.tx_packets;
+	nss_top->stats_node[NSS_IPV6_RX_INTERFACE][NSS_STATS_NODE_TX_BYTES] += nins->node_stats.tx_bytes;
+
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		nss_top->stats_node[NSS_IPV6_RX_INTERFACE][NSS_STATS_NODE_RX_QUEUE_0_DROPPED + i] += nins->node_stats.rx_dropped[i];
+	}
+
+	nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_CREATE_REQUESTS] += nins->ipv6_connection_create_requests;
+	nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_CREATE_COLLISIONS] += nins->ipv6_connection_create_collisions;
+	nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_INTERFACE] += nins->ipv6_connection_create_invalid_interface;
+	nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_DESTROY_REQUESTS] += nins->ipv6_connection_destroy_requests;
+	nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_DESTROY_MISSES] += nins->ipv6_connection_destroy_misses;
+	nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_HASH_HITS] += nins->ipv6_connection_hash_hits;
+	nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_HASH_REORDERS] += nins->ipv6_connection_hash_reorders;
+	nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_FLUSHES] += nins->ipv6_connection_flushes;
+	nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_EVICTIONS] += nins->ipv6_connection_evictions;
+	nss_ipv6_stats[NSS_IPV6_STATS_FRAGMENTATIONS] += nins->ipv6_fragmentations;
+	nss_ipv6_stats[NSS_IPV6_STATS_FRAG_FAILS] += nins->ipv6_frag_fails;
+	nss_ipv6_stats[NSS_IPV6_STATS_MC_CONNECTION_CREATE_REQUESTS] += nins->ipv6_mc_connection_create_requests;
+	nss_ipv6_stats[NSS_IPV6_STATS_MC_CONNECTION_UPDATE_REQUESTS] += nins->ipv6_mc_connection_update_requests;
+	nss_ipv6_stats[NSS_IPV6_STATS_MC_CONNECTION_CREATE_INVALID_INTERFACE] += nins->ipv6_mc_connection_create_invalid_interface;
+	nss_ipv6_stats[NSS_IPV6_STATS_MC_CONNECTION_DESTROY_REQUESTS] += nins->ipv6_mc_connection_destroy_requests;
+	nss_ipv6_stats[NSS_IPV6_STATS_MC_CONNECTION_DESTROY_MISSES] += nins->ipv6_mc_connection_destroy_misses;
+	nss_ipv6_stats[NSS_IPV6_STATS_MC_CONNECTION_FLUSHES] += nins->ipv6_mc_connection_flushes;
+	nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM] += nins->ipv6_connection_create_invalid_mirror_ifnum;
+	nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE] += nins->ipv6_connection_create_invalid_mirror_iftype;
+	nss_ipv6_stats[NSS_IPV6_STATS_MIRROR_FAILURES] += nins->ipv6_mirror_failures;
+
+	for (i = 0; i < NSS_IPV6_EXCEPTION_EVENT_MAX; i++) {
+		nss_ipv6_exception_stats[i] += nins->exception_events[i];
+	}
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_ipv6_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(ipv6);
+
+/*
+ * nss_ipv6_stats_dentry_create()
+ *	Create IPv6 statistics debug entry.
+ */
+void nss_ipv6_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("ipv6", &nss_ipv6_stats_ops);
+}
+
+/*
+ * nss_ipv6_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_ipv6_stats_notify(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_ipv6_stats_notification ipv6_stats;
+
+	ipv6_stats.core_id = nss_ctx->id;
+	memcpy(ipv6_stats.cmn_node_stats, nss_top_main.stats_node[NSS_IPV6_RX_INTERFACE], sizeof(ipv6_stats.cmn_node_stats));
+	memcpy(ipv6_stats.special_stats, nss_ipv6_stats, sizeof(ipv6_stats.special_stats));
+	memcpy(ipv6_stats.exception_stats, nss_ipv6_exception_stats, sizeof(ipv6_stats.exception_stats));
+
+	atomic_notifier_call_chain(&nss_ipv6_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&ipv6_stats);
+}
+
+/*
+ * nss_ipv6_stats_register_notifier()
+ *      Registers statistics notifier.
+ */
+int nss_ipv6_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_ipv6_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_ipv6_stats_register_notifier);
+
+/*
+ * nss_ipv6_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_ipv6_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_ipv6_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_ipv6_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_ipv6_stats.h b/qca-nss-drv/nss_ipv6_stats.h
new file mode 100644
index 0000000..1eaff5e
--- /dev/null
+++ b/qca-nss-drv/nss_ipv6_stats.h
@@ -0,0 +1,29 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017,2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_IPV6_STATS_H
+#define __NSS_IPV6_STATS_H
+
+/*
+ * IPV6 statistics APIs
+ */
+extern void nss_ipv6_stats_notify(struct nss_ctx_instance *nss_ctx);
+extern void nss_ipv6_stats_node_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_node_sync *nins);
+extern void nss_ipv6_stats_conn_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_conn_sync *nics);
+extern void nss_ipv6_stats_conn_sync_many(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_conn_sync_many_msg *nicsm);
+extern void nss_ipv6_stats_dentry_create(void);
+
+#endif /* __NSS_IPV6_STATS_H */
diff --git a/qca-nss-drv/nss_ipv6_strings.c b/qca-nss-drv/nss_ipv6_strings.c
new file mode 100644
index 0000000..a6af312
--- /dev/null
+++ b/qca-nss-drv/nss_ipv6_strings.c
@@ -0,0 +1,186 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include <nss_ipv6.h>
+#include "nss_strings.h"
+
+/*
+ * nss_ipv6_strings_exception_stats
+ *	Interface statistics strings for IPv6 exceptions.
+ */
+struct nss_stats_info nss_ipv6_strings_exception_stats[NSS_IPV6_EXCEPTION_EVENT_MAX] = {
+	{"icmp_header_incomplete"			, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_unhandled_type"				, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_header_incomplete"			, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_udp_header_incomplete"			, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_tcp_header_incomplete"			, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_unknown_protocol"			, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_no_icme"					, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_flush_to_host"				, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_header_incomplete"			, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_no_icme"					, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_small_hop_limit"				, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_needs_fragmentation"			, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_flags"					, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_seq_exceeds_right_edge"			, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_small_data_offs"				, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_bad_sack"					, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_big_data_offs"				, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_seq_before_left_edge"			, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_ack_exceeds_right_edge"			, NSS_STATS_TYPE_EXCEPTION},
+	{"tcp_ack_before_left_edge"			, NSS_STATS_TYPE_EXCEPTION},
+	{"udp_header_incomplete"			, NSS_STATS_TYPE_EXCEPTION},
+	{"udp_no_icme"					, NSS_STATS_TYPE_EXCEPTION},
+	{"udp_small_hop_limit"				, NSS_STATS_TYPE_EXCEPTION},
+	{"udp_needs_fragmentation"			, NSS_STATS_TYPE_EXCEPTION},
+	{"wrong_target_mac"				, NSS_STATS_TYPE_EXCEPTION},
+	{"header_incomplete"				, NSS_STATS_TYPE_EXCEPTION},
+	{"unknown_protocol"				, NSS_STATS_TYPE_EXCEPTION},
+	{"ingress_vid_mismatch"				, NSS_STATS_TYPE_EXCEPTION},
+	{"ingress_vid_missing"				, NSS_STATS_TYPE_EXCEPTION},
+	{"dscp_marking_mismatch"			, NSS_STATS_TYPE_EXCEPTION},
+	{"vlan_marking_mismatch"			, NSS_STATS_TYPE_EXCEPTION},
+	{"interface_mismatch"				, NSS_STATS_TYPE_EXCEPTION},
+	{"gre_no_icme"					, NSS_STATS_TYPE_EXCEPTION},
+	{"gre_needs_fragmentation"			, NSS_STATS_TYPE_EXCEPTION},
+	{"gre_small_hop_limit"				, NSS_STATS_TYPE_EXCEPTION},
+	{"destroy"					, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_udplite_header_incomplete"		, NSS_STATS_TYPE_EXCEPTION},
+	{"udplite_header_incomplete"			, NSS_STATS_TYPE_EXCEPTION},
+	{"udplite_no_icme"				, NSS_STATS_TYPE_EXCEPTION},
+	{"udplite_small_hop_limit"			, NSS_STATS_TYPE_EXCEPTION},
+	{"udplite_needs_fragmentation"			, NSS_STATS_TYPE_EXCEPTION},
+	{"mc_udp_no_icme"				, NSS_STATS_TYPE_EXCEPTION},
+	{"mc_mem_alloc_failure"				, NSS_STATS_TYPE_EXCEPTION},
+	{"mc_update_failure"				, NSS_STATS_TYPE_EXCEPTION},
+	{"mc_pbuf_alloc_failure"			, NSS_STATS_TYPE_EXCEPTION},
+	{"esp_header_incomplete"			, NSS_STATS_TYPE_EXCEPTION},
+	{"esp_no_icme"					, NSS_STATS_TYPE_EXCEPTION},
+	{"esp_ip_fragment"				, NSS_STATS_TYPE_EXCEPTION},
+	{"esp_small_hop_limit"				, NSS_STATS_TYPE_EXCEPTION},
+	{"esp_needs_fragmentation"			, NSS_STATS_TYPE_EXCEPTION},
+	{"tunipip6_no_icme"				, NSS_STATS_TYPE_EXCEPTION},
+	{"tunipip6_small_hop_limit"			, NSS_STATS_TYPE_EXCEPTION},
+	{"tunipip6_needs_fragmentation"			, NSS_STATS_TYPE_EXCEPTION},
+	{"pppoe_bridge_no_icme"				, NSS_STATS_TYPE_EXCEPTION},
+	{"dont_frag_set"				, NSS_STATS_TYPE_EXCEPTION},
+	{"reassembly_not_supported"			, NSS_STATS_TYPE_EXCEPTION},
+	{"pppoe_no_session"				, NSS_STATS_TYPE_DROP},
+	{"icmp_gre_header_incomplete"			, NSS_STATS_TYPE_EXCEPTION},
+	{"icmp_esp_header_incomplete"			, NSS_STATS_TYPE_EXCEPTION},
+	{"emesh_prio_mismatch"				, NSS_STATS_TYPE_EXCEPTION},
+	{"mc_ucast_dmac_failure"			, NSS_STATS_TYPE_EXCEPTION},
+};
+
+/*
+ * nss_ipv6_strings_stats
+ *	IPv6 stats strings.
+ */
+struct nss_stats_info nss_ipv6_strings_stats[NSS_IPV6_STATS_MAX] = {
+	{"rx_pkts"			,NSS_STATS_TYPE_SPECIAL},
+	{"rx_bytes"			,NSS_STATS_TYPE_SPECIAL},
+	{"tx_pkts"			,NSS_STATS_TYPE_SPECIAL},
+	{"tx_bytes"			,NSS_STATS_TYPE_SPECIAL},
+	{"create_requests"		,NSS_STATS_TYPE_SPECIAL},
+	{"create_collisions"		,NSS_STATS_TYPE_SPECIAL},
+	{"create_invalid_interface"	,NSS_STATS_TYPE_SPECIAL},
+	{"destroy_requests"		,NSS_STATS_TYPE_SPECIAL},
+	{"destroy_misses"		,NSS_STATS_TYPE_SPECIAL},
+	{"hash_hits"			,NSS_STATS_TYPE_SPECIAL},
+	{"hash_reorders"		,NSS_STATS_TYPE_SPECIAL},
+	{"flushes"			,NSS_STATS_TYPE_SPECIAL},
+	{"evictions"			,NSS_STATS_TYPE_SPECIAL},
+	{"fragmentations"		,NSS_STATS_TYPE_SPECIAL},
+	{"frag_fails"			,NSS_STATS_TYPE_SPECIAL},
+	{"by_rule_drops"		,NSS_STATS_TYPE_DROP},
+	{"mc_create_requests"		,NSS_STATS_TYPE_SPECIAL},
+	{"mc_update_requests"		,NSS_STATS_TYPE_SPECIAL},
+	{"mc_create_invalid_interface"	,NSS_STATS_TYPE_SPECIAL},
+	{"mc_destroy_requests"		,NSS_STATS_TYPE_SPECIAL},
+	{"mc_destroy_misses"		,NSS_STATS_TYPE_SPECIAL},
+	{"mc_flushes"			,NSS_STATS_TYPE_SPECIAL},
+	{"mirror_invalid_ifnum_conn_create_req"		,NSS_STATS_TYPE_SPECIAL},
+	{"mirror_invalid_iftype_conn_create_req"	,NSS_STATS_TYPE_SPECIAL},
+	{"mirror_failures"		,NSS_STATS_TYPE_SPECIAL},
+};
+
+/*
+ * nss_ipv6_special_stats_strings_read()
+ *	Read IPv6 special node statistics names.
+ */
+static ssize_t nss_ipv6_special_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_ipv6_strings_stats, NSS_IPV6_STATS_MAX);
+}
+
+/*
+ * nss_ipv6_exception_stats_strings_read()
+ *	Read IPv6 exception statistics names.
+ */
+static ssize_t nss_ipv6_exception_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_ipv6_strings_exception_stats, NSS_IPV6_EXCEPTION_EVENT_MAX);
+}
+
+/*
+ * nss_ipv6_special_stats_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(ipv6_special_stats);
+
+/*
+ * nss_ipv6_exception_stats_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(ipv6_exception_stats);
+
+/*
+ * nss_ipv6_strings_dentry_create()
+ *      Create IPv6 statistics strings debug entry.
+ */
+void nss_ipv6_strings_dentry_create(void)
+{
+	struct dentry *ipv6_d = NULL;
+	struct dentry *ipv6_spcl_stats_d = NULL;
+	struct dentry *ipv6_excp_stats_d = NULL;
+
+	if (!nss_top_main.strings_dentry) {
+		nss_warning("qca-nss-drv/strings is not present");
+		return;
+	}
+
+	ipv6_d = debugfs_create_dir("ipv6", nss_top_main.strings_dentry);
+	if (!ipv6_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/ipv6 directory");
+		return;
+	}
+
+	ipv6_spcl_stats_d = debugfs_create_file("special_stats_str", 0400, ipv6_d, &nss_top_main, &nss_ipv6_special_stats_strings_ops);
+	if (!ipv6_spcl_stats_d) {
+		nss_warning("Failed to create qca-nss-drv/stats/ipv6/special_stats_str file");
+		debugfs_remove_recursive(ipv6_d);
+		return;
+	}
+
+	ipv6_excp_stats_d = debugfs_create_file("exception_stats_str", 0400, ipv6_d, &nss_top_main, &nss_ipv6_exception_stats_strings_ops);
+	if (!ipv6_excp_stats_d) {
+		nss_warning("Failed to create qca-nss-drv/stats/ipv6/exception_stats_str file");
+		debugfs_remove_recursive(ipv6_d);
+		return;
+	}
+}
diff --git a/qca-nss-drv/nss_ipv6_strings.h b/qca-nss-drv/nss_ipv6_strings.h
new file mode 100644
index 0000000..4f582e5
--- /dev/null
+++ b/qca-nss-drv/nss_ipv6_strings.h
@@ -0,0 +1,26 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_IPV6_STRINGS_H
+#define __NSS_IPV6_STRINGS_H
+
+extern struct nss_stats_info nss_ipv6_strings_stats[NSS_IPV6_STATS_MAX];
+extern struct nss_stats_info nss_ipv6_strings_exception_stats[NSS_IPV6_EXCEPTION_EVENT_MAX];
+extern void nss_ipv6_strings_dentry_create(void);
+
+#endif /* __NSS_IPV6_STRINGS_H */
diff --git a/qca-nss-drv/nss_l2tpv2.c b/qca-nss-drv/nss_l2tpv2.c
new file mode 100644
index 0000000..2c73b48
--- /dev/null
+++ b/qca-nss-drv/nss_l2tpv2.c
@@ -0,0 +1,284 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/l2tp.h>
+#include <net/sock.h>
+#include "nss_tx_rx_common.h"
+#include "nss_l2tpv2_stats.h"
+#include "nss_l2tpv2_log.h"
+#include "nss_l2tpv2_strings.h"
+
+/*
+ * Data structures to store l2tpv2 nss debug stats
+ */
+static DEFINE_SPINLOCK(nss_l2tpv2_session_debug_stats_lock);
+static struct nss_l2tpv2_stats_session_debug  nss_l2tpv2_session_debug_stats[NSS_MAX_L2TPV2_DYNAMIC_INTERFACES];
+
+/*
+ * nss_l2tpv2_session_debug_stats_sync
+ *	Per session debug stats for l2tpv2
+ */
+void nss_l2tpv2_session_debug_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_l2tpv2_sync_session_stats_msg *stats_msg, uint16_t if_num)
+{
+	int i;
+	spin_lock_bh(&nss_l2tpv2_session_debug_stats_lock);
+	for (i = 0; i < NSS_MAX_L2TPV2_DYNAMIC_INTERFACES; i++) {
+		if (nss_l2tpv2_session_debug_stats[i].if_num == if_num) {
+			nss_l2tpv2_session_debug_stats[i].stats[NSS_L2TPV2_STATS_SESSION_RX_PPP_LCP_PKTS] += stats_msg->debug_stats.rx_ppp_lcp_pkts;
+			nss_l2tpv2_session_debug_stats[i].stats[NSS_L2TPV2_STATS_SESSION_RX_EXP_DATA_PKTS] += stats_msg->debug_stats.rx_exception_data_pkts;
+			nss_l2tpv2_session_debug_stats[i].stats[NSS_L2TPV2_STATS_SESSION_ENCAP_PBUF_ALLOC_FAIL_PKTS] += stats_msg->debug_stats.encap_pbuf_alloc_fail;
+			nss_l2tpv2_session_debug_stats[i].stats[NSS_L2TPV2_STATS_SESSION_DECAP_PBUF_ALLOC_FAIL_PKTS] += stats_msg->debug_stats.decap_pbuf_alloc_fail;
+			nss_l2tpv2_session_debug_stats[i].stats[NSS_L2TPV2_STATS_SESSION_DECAP_L2TPOIPSEC_SRC_ERR] += stats_msg->debug_stats.decap_l2tpoipsec_src_error;
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_l2tpv2_session_debug_stats_lock);
+}
+
+/*
+ * nss_l2tpv2_global_session_stats_get()
+ *	Get session l2tpv2 statitics.
+ */
+void nss_l2tpv2_session_debug_stats_get(void *stats_mem)
+{
+	struct nss_l2tpv2_stats_session_debug *stats = (struct nss_l2tpv2_stats_session_debug *)stats_mem;
+	int i;
+
+	if (!stats) {
+		nss_warning("No memory to copy l2tpv2 session stats");
+		return;
+	}
+
+	spin_lock_bh(&nss_l2tpv2_session_debug_stats_lock);
+	for (i = 0; i < NSS_MAX_L2TPV2_DYNAMIC_INTERFACES; i++) {
+		if (nss_l2tpv2_session_debug_stats[i].valid) {
+			memcpy(stats, &nss_l2tpv2_session_debug_stats[i], sizeof(struct nss_l2tpv2_stats_session_debug));
+			stats++;
+		}
+	}
+	spin_unlock_bh(&nss_l2tpv2_session_debug_stats_lock);
+}
+
+/*
+ * nss_l2tpv2_handler()
+ *	Handle NSS -> HLOS messages for l2tpv2 tunnel
+ */
+
+static void nss_l2tpv2_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_l2tpv2_msg *ntm = (struct nss_l2tpv2_msg *)ncm;
+	void *ctx;
+
+	nss_l2tpv2_msg_callback_t cb;
+
+	BUG_ON(!(nss_is_dynamic_interface(ncm->interface) || ncm->interface == NSS_L2TPV2_INTERFACE));
+
+	/*
+	 * Trace Messages
+	 */
+	nss_l2tpv2_log_rx_msg(ntm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_L2TPV2_MSG_MAX) {
+		nss_warning("%px: received invalid message %d for L2TP interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_l2tpv2_msg)) {
+		nss_warning("%px: message length is invalid: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	switch (ntm->cm.type) {
+
+	case NSS_L2TPV2_MSG_SYNC_STATS:
+		/*
+		 * Update session debug stats in session stats msg and send statistics notifications to the registered modules
+		 */
+		nss_l2tpv2_session_debug_stats_sync(nss_ctx, &ntm->msg.stats, ncm->interface);
+		nss_l2tpv2_stats_notify(nss_ctx, ncm->interface);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, l2tpv2 sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->l2tpv2_msg_callback;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_l2tpv2_msg_callback_t)ncm->cb;
+	ctx = nss_ctx->subsys_dp_register[ncm->interface].ndev;
+
+	/*
+	 * call l2tpv2 tunnel callback
+	 */
+	if (!ctx) {
+		nss_warning("%px: Event received for l2tpv2 tunnel interface %d before registration", nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb(ctx, ntm);
+}
+
+/*
+ * nss_l2tpv2_tx()
+ *	Transmit a l2tpv2 message to NSS firmware
+ */
+nss_tx_status_t nss_l2tpv2_tx(struct nss_ctx_instance *nss_ctx, struct nss_l2tpv2_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_l2tpv2_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!nss_is_dynamic_interface(ncm->interface)) {
+		nss_warning("%px: tx request for non dynamic interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_L2TPV2_MSG_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ ***********************************
+ * Register/Unregister/Miscellaneous APIs
+ ***********************************
+ */
+
+/*
+ * nss_register_l2tpv2_if()
+ */
+struct nss_ctx_instance *nss_register_l2tpv2_if(uint32_t if_num, nss_l2tpv2_callback_t l2tpv2_callback,
+			nss_l2tpv2_msg_callback_t event_callback, struct net_device *netdev, uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.l2tpv2_handler_id];
+	int i = 0;
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_is_dynamic_interface(if_num));
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, l2tpv2_callback, NULL, NULL, netdev, features);
+
+	nss_top_main.l2tpv2_msg_callback = event_callback;
+
+	nss_core_register_handler(nss_ctx, if_num, nss_l2tpv2_handler, NULL);
+
+	spin_lock_bh(&nss_l2tpv2_session_debug_stats_lock);
+	for (i = 0; i < NSS_MAX_L2TPV2_DYNAMIC_INTERFACES; i++) {
+		if (!nss_l2tpv2_session_debug_stats[i].valid) {
+			nss_l2tpv2_session_debug_stats[i].valid = true;
+			nss_l2tpv2_session_debug_stats[i].if_num = if_num;
+			nss_l2tpv2_session_debug_stats[i].if_index = netdev->ifindex;
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_l2tpv2_session_debug_stats_lock);
+
+	return nss_ctx;
+}
+
+/*
+ * nss_unregister_l2tpv2_if()
+ */
+void nss_unregister_l2tpv2_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.l2tpv2_handler_id];
+	int i;
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_is_dynamic_interface(if_num));
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	nss_top_main.l2tpv2_msg_callback = NULL;
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+
+	spin_lock_bh(&nss_l2tpv2_session_debug_stats_lock);
+	for (i = 0; i < NSS_MAX_L2TPV2_DYNAMIC_INTERFACES; i++) {
+		if (nss_l2tpv2_session_debug_stats[i].if_num == if_num) {
+			memset(&nss_l2tpv2_session_debug_stats[i], 0, sizeof(struct nss_l2tpv2_stats_session_debug));
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_l2tpv2_session_debug_stats_lock);
+}
+
+/*
+ * nss_get_l2tpv2_context()
+ */
+struct nss_ctx_instance *nss_l2tpv2_get_context()
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.l2tpv2_handler_id];
+}
+
+/*
+ * nss_l2tpv2_msg_init()
+ *	Initialize nss_l2tpv2 msg.
+ */
+void nss_l2tpv2_msg_init(struct nss_l2tpv2_msg *ncm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+
+/* nss_l2tpv2_register_handler()
+ *   debugfs stats msg handler received on static l2tpv2 interface
+ */
+void nss_l2tpv2_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_l2tpv2_get_context();
+
+	nss_info("nss_l2tpv2_register_handler");
+	nss_core_register_handler(nss_ctx, NSS_L2TPV2_INTERFACE, nss_l2tpv2_handler, NULL);
+
+	nss_l2tpv2_stats_dentry_create();
+	nss_l2tpv2_strings_dentry_create();
+}
+
+EXPORT_SYMBOL(nss_l2tpv2_get_context);
+EXPORT_SYMBOL(nss_l2tpv2_tx);
+EXPORT_SYMBOL(nss_unregister_l2tpv2_if);
+EXPORT_SYMBOL(nss_l2tpv2_msg_init);
+EXPORT_SYMBOL(nss_register_l2tpv2_if);
diff --git a/qca-nss-drv/nss_l2tpv2_log.c b/qca-nss-drv/nss_l2tpv2_log.c
new file mode 100644
index 0000000..fc1b31f
--- /dev/null
+++ b/qca-nss-drv/nss_l2tpv2_log.c
@@ -0,0 +1,143 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_l2tpv2_log.c
+ *	NSS L2TPV2 logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_l2tpv2_log_message_types_str
+ *	NSS L2TPV2 message strings
+ */
+static int8_t *nss_l2tpv2_log_message_types_str[NSS_L2TPV2_MSG_MAX] __maybe_unused = {
+	"L2TPV2 Sesstion Create",
+	"L2TPV2 Session Destroy",
+	"L2TPV2 Stats",
+};
+
+/*
+ * nss_l2tpv2_log_session_create_msg()
+ *	Log NSS L2TPV2 Session Create.
+ */
+static void nss_l2tpv2_log_session_create_msg(struct nss_l2tpv2_msg *nlm)
+{
+	struct nss_l2tpv2_session_create_msg *nlcm __maybe_unused = &nlm->msg.session_create_msg;
+	nss_trace("%px: NSS L2TPV2 Session Create message \n"
+		"L2TPV2 Local Tunnel ID: %x\n"
+		"L2TPV2 Local Session ID: %x\n"
+		"L2TPV2 Peer Tunnel ID: %x\n"
+		"L2TPV2 Peer Session ID: %x\n"
+		"L2TPV2 Source IP: %x\n"
+		"L2TPV2 Destnation IP: %x\n"
+		"L2TPV2 Reorder Timeout: %d\n"
+		"L2TPV2 Source Port: %d\n"
+		"L2TPV2 Destination Port: %d\n"
+		"L2TPV2 Received Sequence Number: %d\n"
+		"L2TPV2 Outer IP Packet TTL: %d\n"
+		"L2TPV2 UDP Checksum: %d\n",
+		nlcm, nlcm->local_tunnel_id,
+		nlcm->local_session_id, nlcm->peer_tunnel_id,
+		nlcm->peer_session_id, nlcm->sip,
+		nlcm->dip, nlcm->reorder_timeout,
+		nlcm->sport, nlcm->dport,
+		nlcm->recv_seq, nlcm->oip_ttl,
+		nlcm->udp_csum);
+}
+
+/*
+ * nss_l2tpv2_log_session_destroy_msg()
+ *	Log NSS L2TPV2 Session Create.
+ */
+static void nss_l2tpv2_log_session_destroy_msg(struct nss_l2tpv2_msg *nlm)
+{
+	struct nss_l2tpv2_session_destroy_msg *nldm __maybe_unused = &nlm->msg.session_destroy_msg;
+	nss_trace("%px: NSS L2TPV2 Session Destroy message \n"
+		"L2TPV2 Local Tunnel ID: %x\n"
+		"L2TPV2 Local Session ID: %x\n",
+		nldm, nldm->local_tunnel_id,
+		nldm->local_session_id);
+}
+
+/*
+ * nss_l2tpv2_log_verbose()
+ *	Log message contents.
+ */
+static void nss_l2tpv2_log_verbose(struct nss_l2tpv2_msg *nlm)
+{
+	switch (nlm->cm.type) {
+	case NSS_L2TPV2_MSG_SESSION_CREATE:
+		nss_l2tpv2_log_session_create_msg(nlm);
+		break;
+
+	case NSS_L2TPV2_MSG_SESSION_DESTROY:
+		nss_l2tpv2_log_session_destroy_msg(nlm);
+		break;
+
+	case NSS_L2TPV2_MSG_SYNC_STATS:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", nlm);
+		break;
+	}
+}
+
+/*
+ * nss_l2tpv2_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_l2tpv2_log_tx_msg(struct nss_l2tpv2_msg *nlm)
+{
+	if (nlm->cm.type >= NSS_L2TPV2_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", nlm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nlm, nlm->cm.type, nss_l2tpv2_log_message_types_str[nlm->cm.type]);
+	nss_l2tpv2_log_verbose(nlm);
+}
+
+/*
+ * nss_l2tpv2_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_l2tpv2_log_rx_msg(struct nss_l2tpv2_msg *nlm)
+{
+	if (nlm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", nlm);
+		return;
+	}
+
+	if (nlm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nlm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nlm, nlm->cm.type,
+			nss_l2tpv2_log_message_types_str[nlm->cm.type],
+			nlm->cm.response, nss_cmn_response_str[nlm->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		nlm, nlm->cm.type, nss_l2tpv2_log_message_types_str[nlm->cm.type],
+		nlm->cm.response, nss_cmn_response_str[nlm->cm.response]);
+
+verbose:
+	nss_l2tpv2_log_verbose(nlm);
+}
diff --git a/qca-nss-drv/nss_l2tpv2_log.h b/qca-nss-drv/nss_l2tpv2_log.h
new file mode 100644
index 0000000..56cc9de
--- /dev/null
+++ b/qca-nss-drv/nss_l2tpv2_log.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_L2TPV2_LOG_H
+#define __NSS_L2TPV2_LOG_H
+
+/*
+ * nss_l2tpv2.h
+ *	NSS L2TPV2 header file.
+ */
+
+/*
+ * Logger APIs
+ */
+
+/*
+ * nss_l2tpv2_log_tx_msg
+ *	Logs a l2tpv2 message that is sent to the NSS firmware.
+ */
+void nss_l2tpv2_log_tx_msg(struct nss_l2tpv2_msg *ntm);
+
+/*
+ * nss_l2tpv2_log_rx_msg
+ *	Logs a l2tpv2 message that is received from the NSS firmware.
+ */
+void nss_l2tpv2_log_rx_msg(struct nss_l2tpv2_msg *ntm);
+
+#endif /* __NSS_L2TPV2_LOG_H */
diff --git a/qca-nss-drv/nss_l2tpv2_stats.c b/qca-nss-drv/nss_l2tpv2_stats.c
new file mode 100644
index 0000000..0784b54
--- /dev/null
+++ b/qca-nss-drv/nss_l2tpv2_stats.c
@@ -0,0 +1,156 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017,2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_l2tpv2_stats.h"
+#include "nss_l2tpv2_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_l2tpv2_stats_notifier);
+
+/*
+ * nss_l2tpv2_stats_read()
+ *	Read l2tpv2 statistics.
+ */
+static ssize_t nss_l2tpv2_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	/*
+	 * Max output lines = #stats * NSS_MAX_CORES  +
+	 * Few output lines for banner printing + Number of Extra outputlines for future reference to add new stats.
+	 */
+	uint32_t max_output_lines = NSS_MAX_L2TPV2_DYNAMIC_INTERFACES * (NSS_L2TPV2_STATS_SESSION_MAX + 2) /*session stats */
+					+ NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines ;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	struct net_device *dev;
+	struct nss_l2tpv2_stats_session_debug l2tpv2_session_stats[NSS_MAX_L2TPV2_DYNAMIC_INTERFACES];
+	int id;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	memset(&l2tpv2_session_stats, 0, sizeof(struct nss_l2tpv2_stats_session_debug) * NSS_MAX_L2TPV2_DYNAMIC_INTERFACES);
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "l2tpv2", NSS_STATS_SINGLE_CORE);
+
+	/*
+	 * Get all stats
+	 */
+	nss_l2tpv2_session_debug_stats_get((void *)&l2tpv2_session_stats);
+
+	/*
+	 * Session stats
+	 */
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nl2tp v2 session stats start:\n\n");
+	for (id = 0; id < NSS_MAX_L2TPV2_DYNAMIC_INTERFACES; id++) {
+
+			if (!l2tpv2_session_stats[id].valid) {
+				break;
+			}
+
+			dev = dev_get_by_index(&init_net, l2tpv2_session_stats[id].if_index);
+			if (likely(dev)) {
+
+				size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%d. nss interface id=%d, netdevice=%s\n", id,
+						l2tpv2_session_stats[id].if_num, dev->name);
+				dev_put(dev);
+			} else {
+				size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%d. nss interface id=%d\n", id,
+						l2tpv2_session_stats[id].if_num);
+			}
+
+			size_wr += nss_stats_print("l2tpv2", "l2tp v2 session stats"
+							, id
+							, nss_l2tpv2_strings_session_stats
+							, l2tpv2_session_stats[id].stats
+							, NSS_L2TPV2_STATS_SESSION_MAX
+							, lbuf, size_wr, size_al);
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_l2tpv2_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(l2tpv2);
+
+/*
+ * nss_l2tpv2_stats_dentry_create()
+ *	Create l2tpv2 statistics debug entry.
+ */
+void nss_l2tpv2_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("l2tpv2", &nss_l2tpv2_stats_ops);
+}
+
+/*
+ * nss_l2tpv2_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_l2tpv2_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_l2tpv2_stats_notification l2tpv2_stats;
+	struct nss_l2tpv2_stats_session_debug l2tpv2_session_stats[NSS_MAX_L2TPV2_DYNAMIC_INTERFACES];
+	int id;
+
+	memset(&l2tpv2_session_stats, 0, sizeof(l2tpv2_session_stats));
+
+	/*
+	 * Get all stats
+	 */
+	nss_l2tpv2_session_debug_stats_get((void *)&l2tpv2_session_stats);
+
+	for (id = 0; id < NSS_MAX_L2TPV2_DYNAMIC_INTERFACES; id++) {
+		if (l2tpv2_session_stats[id].if_num == if_num) {
+			memcpy(&l2tpv2_stats.stats, &l2tpv2_session_stats[id].stats, sizeof(l2tpv2_stats.stats));
+		}
+	}
+	l2tpv2_stats.core_id = nss_ctx->id;
+	l2tpv2_stats.if_num = if_num;
+	atomic_notifier_call_chain(&nss_l2tpv2_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&l2tpv2_stats);
+}
+
+/*
+ * nss_l2tpv2_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_l2tpv2_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_l2tpv2_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_l2tpv2_stats_register_notifier);
+
+/*
+ * nss_l2tpv2_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_l2tpv2_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_l2tpv2_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_l2tpv2_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_l2tpv2_stats.h b/qca-nss-drv/nss_l2tpv2_stats.h
new file mode 100644
index 0000000..0c8ecda
--- /dev/null
+++ b/qca-nss-drv/nss_l2tpv2_stats.h
@@ -0,0 +1,33 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2017,2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_L2TPV2_STATS_H
+#define __NSS_L2TPV2_STATS_H
+
+struct nss_l2tpv2_stats_session_debug {
+	uint64_t stats[NSS_L2TPV2_STATS_SESSION_MAX];
+	int32_t if_index;
+	uint32_t if_num; /* nss interface number */
+	bool valid;
+};
+
+/*
+ * l2tpv2 statistics APIs
+ */
+extern void nss_l2tpv2_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_l2tpv2_stats_dentry_create(void);
+
+#endif /* __NSS_L2TPV2_STATS_H */
diff --git a/qca-nss-drv/nss_l2tpv2_strings.c b/qca-nss-drv/nss_l2tpv2_strings.c
new file mode 100644
index 0000000..d5db00c
--- /dev/null
+++ b/qca-nss-drv/nss_l2tpv2_strings.c
@@ -0,0 +1,57 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include <nss_l2tpv2.h>
+#include "nss_strings.h"
+
+/*
+ * nss_l2tpv2_strings_session_stats
+ *	L2TPv2 statistics strings for NSS session statistics.
+ */
+struct nss_stats_info nss_l2tpv2_strings_session_stats[NSS_L2TPV2_STATS_SESSION_MAX] = {
+	{"rx_ppp_lcp_pkts"		, NSS_STATS_TYPE_EXCEPTION},
+	{"rx_exp_pkts"			, NSS_STATS_TYPE_EXCEPTION},
+	{"encap_pbuf_alloc_fails"	, NSS_STATS_TYPE_SPECIAL},
+	{"decap_pbuf_alloc_fails"	, NSS_STATS_TYPE_SPECIAL},
+	{"decap_l2tpoipsec_src_err"	, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_l2tpv2_strings_read()
+ *	Read L2TPv2 node statistics names.
+ */
+static ssize_t nss_l2tpv2_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_l2tpv2_strings_session_stats, NSS_L2TPV2_STATS_SESSION_MAX);
+}
+
+/*
+ * nss_l2tpv2_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(l2tpv2);
+
+/*
+ * nss_l2tpv2_strings_dentry_create()
+ *	Create L2TPv2 statistics strings debug entry.
+ */
+void nss_l2tpv2_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("l2tpv2", &nss_l2tpv2_strings_ops);
+}
diff --git a/qca-nss-drv/nss_l2tpv2_strings.h b/qca-nss-drv/nss_l2tpv2_strings.h
new file mode 100644
index 0000000..2e8f871
--- /dev/null
+++ b/qca-nss-drv/nss_l2tpv2_strings.h
@@ -0,0 +1,25 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_L2TPV2_STRINGS_H
+#define __NSS_L2TPV2_STRINGS_H
+
+extern struct nss_stats_info nss_l2tpv2_strings_session_stats[NSS_L2TPV2_STATS_SESSION_MAX];
+extern void nss_l2tpv2_strings_dentry_create(void);
+
+#endif /* __NSS_L2TPV2_STRINGS_H */
diff --git a/qca-nss-drv/nss_lag.c b/qca-nss-drv/nss_lag.c
new file mode 100644
index 0000000..02362e1
--- /dev/null
+++ b/qca-nss-drv/nss_lag.c
@@ -0,0 +1,273 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_tx_rx_lag.c
+ *	NSS LAG Tx APIs
+ */
+
+#include <linux/if_bonding.h>
+
+#include "nss_tx_rx_common.h"
+#include "nss_lag_log.h"
+
+#define NSS_LAG_RESP_TIMEOUT 60000	/* 60 Sec */
+
+/*
+ * Private data structure of dynamic interface
+ */
+struct nss_lag_pvt {
+	struct completion complete;		/* completion structure */
+	enum nss_cmn_response response;		/* Message response */
+};
+
+/*
+ * nss_lag_state_callback()
+ *	Call back function for nss LAG State
+ */
+void nss_lag_state_callback(void *arg, struct nss_lag_msg *nm)
+{
+	struct nss_lag_pvt *lag_msg_state = arg;
+
+	/*
+	 * Unblock the sleeping function.
+	 */
+	lag_msg_state->response = nm->cm.response;
+	complete(&lag_msg_state->complete);
+}
+
+/*
+ * nss_lag_verify_ifnum()
+ *
+ */
+static void nss_lag_verify_ifnum(uint32_t if_num)
+{
+	nss_assert((if_num == NSS_LAG0_INTERFACE_NUM) ||
+		   (if_num == NSS_LAG1_INTERFACE_NUM) ||
+		   (if_num == NSS_LAG2_INTERFACE_NUM) ||
+		   (if_num == NSS_LAG3_INTERFACE_NUM));
+}
+
+/*
+ * nss_lag_get_context()
+ */
+static struct nss_ctx_instance *nss_lag_get_context(void)
+{
+	uint8_t ipv4_handler_id = nss_top_main.ipv4_handler_id;
+
+	return (struct nss_ctx_instance *)&nss_top_main.nss[ipv4_handler_id];
+}
+
+/*
+ * nss_lag_tx()
+ *	Transmit a LAG msg to the firmware.
+ */
+nss_tx_status_t nss_lag_tx(struct nss_ctx_instance *nss_ctx, struct nss_lag_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_lag_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+	nss_lag_verify_ifnum(ncm->interface);
+
+	if (ncm->type > NSS_TX_METADATA_LAG_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_lag_tx);
+
+/**
+ * nss_register_lag_if()
+ */
+void *nss_register_lag_if(uint32_t if_num,
+			 nss_lag_callback_t lag_cb,
+			 nss_lag_event_callback_t lag_ev_cb,
+			 struct net_device *netdev)
+{
+	struct nss_ctx_instance *nss_ctx = nss_lag_get_context();
+	uint32_t features = 0;
+
+	nss_assert(nss_ctx);
+	nss_lag_verify_ifnum(if_num);
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, lag_cb, NULL, NULL, netdev, features);
+
+	nss_top_main.lag_event_callback = lag_ev_cb;
+
+	/*
+	 * Return the NSS driver context for LAG (same as for ipv4 functions)
+	 */
+	return (void *)nss_ctx;
+}
+EXPORT_SYMBOL(nss_register_lag_if);
+
+/**
+ * nss_unregister_lag_if()
+ */
+void nss_unregister_lag_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_lag_get_context();
+
+	nss_assert(nss_ctx);
+	nss_lag_verify_ifnum(if_num);
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	nss_top_main.lag_event_callback = NULL;
+}
+EXPORT_SYMBOL(nss_unregister_lag_if);
+
+/**
+ * nss_lag_handler()
+ */
+void nss_lag_handler(struct nss_ctx_instance *nss_ctx,
+		     struct nss_cmn_msg *ncm,
+		     void *app_data)
+{
+	struct nss_lag_msg *lm = (struct nss_lag_msg *)ncm;
+	void *ctx = NULL;
+	nss_lag_event_callback_t cb;
+
+	BUG_ON(ncm->interface != NSS_LAG0_INTERFACE_NUM
+	       && ncm->interface != NSS_LAG1_INTERFACE_NUM
+		&& ncm->interface != NSS_LAG2_INTERFACE_NUM
+		&& ncm->interface != NSS_LAG3_INTERFACE_NUM);
+
+	/*
+	 * Trace Messages
+	 */
+	nss_lag_log_rx_msg(lm);
+
+	if (ncm->type >= NSS_TX_METADATA_LAG_MAX) {
+		nss_warning("%px: received invalid message %d for LAG interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_lag_msg)) {
+		nss_warning("%px: invalid length for LAG message: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/**
+	 * Update the callback and app_data for NOTIFY messages.
+	 * LAG sends all notify messages to the same callback.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->lag_event_callback;
+	}
+
+	/**
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/**
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/**
+	 * callback
+	 */
+	cb = (nss_lag_event_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	cb(ctx, lm);
+}
+
+/**
+ * nss_lag_register_handler()
+ */
+void nss_lag_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_lag_get_context();
+
+	nss_core_register_handler(nss_ctx, NSS_LAG0_INTERFACE_NUM, nss_lag_handler, NULL);
+	nss_core_register_handler(nss_ctx, NSS_LAG1_INTERFACE_NUM, nss_lag_handler, NULL);
+	nss_core_register_handler(nss_ctx, NSS_LAG2_INTERFACE_NUM, nss_lag_handler, NULL);
+	nss_core_register_handler(nss_ctx, NSS_LAG3_INTERFACE_NUM, nss_lag_handler, NULL);
+}
+
+/**
+ * nss_lag_msg_init()
+ *	Initialize lag message
+ */
+void nss_lag_msg_init(struct nss_lag_msg *nlm, uint16_t lag_num, uint32_t type, uint32_t len,
+		nss_lag_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&nlm->cm, lag_num, type, len, (void *)cb, app_data);
+}
+EXPORT_SYMBOL(nss_lag_msg_init);
+
+/**
+ * nss_lag_tx_slave_state()
+ */
+nss_tx_status_t nss_lag_tx_slave_state(uint16_t lagid, int32_t slave_ifnum,
+		enum nss_lag_state_change_ev slave_state)
+{
+	struct nss_lag_msg nm;
+	struct nss_lag_state_change *nlsc = NULL;
+	nss_tx_status_t status;
+	int ret;
+	struct nss_ctx_instance *nss_ctx = nss_lag_get_context();
+	struct nss_lag_pvt lag_msg_state;
+
+	init_completion(&lag_msg_state.complete);
+	lag_msg_state.response = false;
+
+	/*
+	 * Construct a message to the NSS to update it
+	 */
+	nss_lag_msg_init(&nm, lagid,
+			 NSS_TX_METADATA_LAG_STATE_CHANGE,
+			 sizeof(struct nss_lag_state_change),
+			 nss_lag_state_callback, &lag_msg_state);
+
+	nlsc = &nm.msg.state;
+	nlsc->event = slave_state;
+	nlsc->interface = slave_ifnum;
+
+	status = nss_lag_tx(nss_ctx, &nm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Send LAG update failed, status: %d\n", nss_ctx,
+				status);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Blocking call, wait till we get ACK for this msg.
+	 */
+	ret = wait_for_completion_timeout(&lag_msg_state.complete,
+			msecs_to_jiffies(NSS_LAG_RESP_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: Waiting for ack timed out\n", nss_ctx);
+		return NSS_TX_FAILURE;
+	}
+
+	return lag_msg_state.response;
+}
+EXPORT_SYMBOL(nss_lag_tx_slave_state);
diff --git a/qca-nss-drv/nss_lag_log.c b/qca-nss-drv/nss_lag_log.c
new file mode 100644
index 0000000..da83df0
--- /dev/null
+++ b/qca-nss-drv/nss_lag_log.c
@@ -0,0 +1,103 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_lag_log.c
+ *	NSS LAG logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_lag_log_message_types_str
+ *	NSS LAG message strings
+ */
+static int8_t *nss_lag_log_message_types_str[NSS_TX_METADATA_LAG_MAX] __maybe_unused = {
+	"LAG State Change",
+};
+
+/*
+ * nss_lag_log_state_change_msg()
+ *	Log NSS LAG State Change.
+ */
+static void nss_lag_log_state_change_msg(struct nss_lag_msg *nlm)
+{
+	struct nss_lag_state_change *nlcm __maybe_unused = &nlm->msg.state;
+	nss_trace("%px: NSS LAG State Change message \n"
+		"LAG ID: %x\n"
+		"LAG Interface: %x\n"
+		"LAG Event: %d\n",
+		nlcm, nlcm->lagid,
+		nlcm->interface, nlcm->event);
+}
+
+/*
+ * nss_lag_log_verbose()
+ *	Log message contents.
+ */
+static void nss_lag_log_verbose(struct nss_lag_msg *nlm)
+{
+	switch (nlm->cm.type) {
+	case NSS_TX_METADATA_LAG_STATE_CHANGE:
+		nss_lag_log_state_change_msg(nlm);
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", nlm);
+		break;
+	}
+}
+
+/*
+ * nss_lag_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_lag_log_tx_msg(struct nss_lag_msg *nlm)
+{
+	if (nlm->cm.type >= NSS_TX_METADATA_LAG_MAX) {
+		nss_warning("%px: Invalid message type\n", nlm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nlm, nlm->cm.type, nss_lag_log_message_types_str[nlm->cm.type]);
+	nss_lag_log_verbose(nlm);
+}
+
+/*
+ * nss_lag_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_lag_log_rx_msg(struct nss_lag_msg *nlm)
+{
+	if (nlm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", nlm);
+		return;
+	}
+
+	if (nlm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nlm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nlm, nlm->cm.type,
+			nss_lag_log_message_types_str[nlm->cm.type],
+			nlm->cm.response, nss_cmn_response_str[nlm->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		nlm, nlm->cm.type, nss_lag_log_message_types_str[nlm->cm.type],
+		nlm->cm.response, nss_cmn_response_str[nlm->cm.response]);
+
+verbose:
+	nss_lag_log_verbose(nlm);
+}
diff --git a/qca-nss-drv/nss_lag_log.h b/qca-nss-drv/nss_lag_log.h
new file mode 100644
index 0000000..4efe393
--- /dev/null
+++ b/qca-nss-drv/nss_lag_log.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_LAG_LOG_H
+#define __NSS_LAG_LOG_H
+
+/*
+ * nss_lag.h
+ *	NSS LAG header file.
+ */
+
+/*
+ * Logger APIs
+ */
+
+/*
+ * nss_lag_log_tx_msg
+ *	Logs a lag message that is sent to the NSS firmware.
+ */
+void nss_lag_log_tx_msg(struct nss_lag_msg *nlm);
+
+/*
+ * nss_lag_log_rx_msg
+ *	Logs a lag message that is received from the NSS firmware.
+ */
+void nss_lag_log_rx_msg(struct nss_lag_msg *nlm);
+
+#endif /* __NSS_LAG_LOG_H */
diff --git a/qca-nss-drv/nss_log.c b/qca-nss-drv/nss_log.c
new file mode 100644
index 0000000..bfdca65
--- /dev/null
+++ b/qca-nss-drv/nss_log.c
@@ -0,0 +1,602 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+/*
+ * nss_log.c
+ *	NSS FW debug logger retrieval from DDR (memory)
+ *
+ */
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/posix-timers.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <nss_hal.h>
+#include "nss_core.h"
+#include "nss_log.h"
+
+/*
+ * Private data for each device file open instance
+ */
+struct nss_log_data {
+	void *load_mem;		/* Pointer to struct nss_log_descriptor - descriptor data */
+	dma_addr_t dma_addr;	/* Handle to DMA */
+	uint32_t last_entry;	/* Last known sampled entry (or index) */
+	uint32_t nentries;	/* Caches the total number of entries of log buffer */
+	int nss_id;		/* NSS Core id being used */
+	struct nss_ctx_instance *nss_ctx;
+				/* NSS ctx instance */
+};
+
+struct nss_log_ring_buffer_addr nss_rbe[NSS_MAX_CORES];
+
+static DEFINE_MUTEX(nss_log_mutex);
+static wait_queue_head_t nss_log_wq;
+static nss_log_msg_callback_t nss_debug_interface_cb;
+static void *nss_debug_interface_app_data = NULL;
+
+static wait_queue_head_t msg_wq;
+enum nss_cmn_response msg_response;
+static bool msg_event;
+
+/*
+ * nss_log_llseek()
+ *	Seek operation.
+ */
+static loff_t nss_log_llseek(struct file *file, loff_t offset, int origin)
+{
+	struct nss_log_data *data = file->private_data;
+
+	switch (origin) {
+	case SEEK_SET:
+		break;
+	case SEEK_CUR:
+		offset += file->f_pos;
+		break;
+	case SEEK_END:
+		offset = ((data->nentries * sizeof(struct nss_log_entry)) + sizeof(struct nss_log_descriptor)) - offset;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return (offset >= 0) ? (file->f_pos = offset) : -EINVAL;
+}
+
+/*
+ * nss_log_open()
+ *	Open operation for our device. We let as many instance run together
+ */
+static int nss_log_open(struct inode *inode, struct file *filp)
+{
+	struct nss_log_data *data = NULL;
+	struct nss_top_instance *nss_top;
+	struct nss_ctx_instance *nss_ctx;
+	int nss_id;
+
+	/*
+	 * i_private is passed to us by debug_fs_create()
+	 */
+	nss_id = (int)(nss_ptr_t)inode->i_private;
+	if (nss_id < 0 || nss_id >= nss_top_main.num_nss) {
+		nss_warning("nss_id is not valid :%d\n", nss_id);
+		return -ENODEV;
+	}
+
+	nss_top = &nss_top_main;
+	nss_ctx = &nss_top->nss[nss_id];
+
+	data = kzalloc(sizeof(struct nss_log_data), GFP_KERNEL);
+	if (!data) {
+		nss_warning("%px: Failed to allocate memory for log_data", nss_ctx);
+		return -ENOMEM;
+	}
+
+	mutex_lock(&nss_log_mutex);
+	if (!nss_rbe[nss_id].addr) {
+		mutex_unlock(&nss_log_mutex);
+		kfree(data);
+		nss_warning("%px: Ring buffer not configured yet for nss_id:%d", nss_ctx, nss_id);
+		return -EIO;
+	}
+
+	/*
+	 * Actual ring buffer.
+	 */
+	data->load_mem = nss_rbe[nss_id].addr;
+	data->last_entry = 0;
+	data->nentries = nss_rbe[nss_id].nentries;
+	data->dma_addr = nss_rbe[nss_id].dma_addr;
+	data->nss_ctx = nss_ctx;
+
+	/*
+	 * Increment the reference count so that we don't free
+	 * the memory
+	 */
+	nss_rbe[nss_id].ref_cnt++;
+	data->nss_id = nss_id;
+	filp->private_data = data;
+	mutex_unlock(&nss_log_mutex);
+
+	return 0;
+}
+
+/*
+ * nss_log_release()
+ *	release gets called when close() is called on the file
+ *	descriptor. We unmap the IO region.
+ */
+static int nss_log_release(struct inode *inode, struct file *filp)
+{
+	struct nss_log_data *data = filp->private_data;
+
+	if (!data) {
+		return -EINVAL;
+	}
+
+	mutex_lock(&nss_log_mutex);
+	nss_rbe[data->nss_id].ref_cnt--;
+	BUG_ON(nss_rbe[data->nss_id].ref_cnt < 0);
+	if (!nss_rbe[data->nss_id].ref_cnt) {
+		wake_up(&nss_log_wq);
+	}
+	mutex_unlock(&nss_log_mutex);
+	kfree(data);
+	return 0;
+}
+
+/*
+ * nss_log_current_entry()
+ *	Reads current entry index from NSS log descriptor.
+ */
+static uint32_t nss_log_current_entry(struct nss_log_descriptor *desc)
+{
+	rmb();
+	return desc->current_entry;
+}
+
+/*
+ * nss_log_read()
+ *	Read operation lets command like cat and tail read our memory log buffer data.
+ */
+static ssize_t nss_log_read(struct file *filp, char __user *buf, size_t size, loff_t *ppos)
+{
+	struct nss_log_data *data = filp->private_data;
+	struct nss_log_descriptor *desc;
+	size_t bytes = 0;
+	size_t b;
+	struct nss_log_entry *rb;
+	uint32_t entry;
+	uint32_t offset, index;
+	char msg[NSS_LOG_OUTPUT_LINE_SIZE];
+
+	if (!data) {
+		return -EINVAL;
+	}
+
+	desc = data->load_mem;
+	if (!desc) {
+		nss_warning("%px: load_mem is NULL", data);
+		return -EINVAL;
+	}
+
+	/*
+	 * If buffer is too small to fit even one entry.
+	 */
+	if (size < NSS_LOG_OUTPUT_LINE_SIZE) {
+		return 0;
+	}
+
+	/*
+	 * Get the current index
+	 */
+	dma_sync_single_for_cpu(data->nss_ctx->dev, data->dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE);
+
+	entry = nss_log_current_entry(desc);
+
+	/*
+	 * If the current and last sampled indexes are same then bail out.
+	 */
+	if (unlikely(data->last_entry == entry)) {
+		return 0;
+	}
+
+	/*
+	 * If this is the first read (after open) on our device file.
+	 */
+	if (unlikely(!(*ppos))) {
+		/*
+		 * If log buffer has rolled over. Almost all the time
+		 * it will be true.
+		 */
+		if (likely(entry > data->nentries)) {
+			/*
+			 * Determine how much we can stuff in one
+			 * buffer passed to us and accordingly
+			 * reduce our index.
+			 */
+			data->last_entry = entry - data->nentries;
+		} else {
+			data->last_entry = 0;
+		}
+	} else if (unlikely(entry > data->nentries && ((entry - data->nentries) > data->last_entry))) {
+		/*
+		 * If FW is producing debug buffer at a pace faster than
+		 * we can consume, then we restrict our iteration.
+		 */
+		data->last_entry = entry - data->nentries;
+	}
+
+	/*
+	 * Iterate over indexes.
+	 */
+	while (entry > data->last_entry) {
+		index = offset = (data->last_entry % data->nentries);
+		offset = (offset * sizeof(struct nss_log_entry))
+			 + offsetof(struct nss_log_descriptor, log_ring_buffer);
+
+		dma_sync_single_for_cpu(data->nss_ctx->dev, data->dma_addr + offset,
+			sizeof(struct nss_log_entry), DMA_FROM_DEVICE);
+		rb = &desc->log_ring_buffer[index];
+
+		b = scnprintf(msg, sizeof(msg), NSS_LOG_LINE_FORMAT,
+			rb->thread_num, rb->timestamp, rb->message);
+
+		data->last_entry++;
+
+		/*
+		 * Copy to user buffer and if we fail then we return
+		 * failure.
+		 */
+		if (copy_to_user(buf + bytes, msg, b)) {
+			return -EFAULT;
+		}
+
+		bytes += b;
+
+		/*
+		 * If we ran out of space in the buffer.
+		 */
+		if ((bytes + NSS_LOG_OUTPUT_LINE_SIZE) >= size)
+			break;
+	}
+
+	if (bytes > 0)
+		*ppos =  bytes;
+
+	return bytes;
+}
+
+struct file_operations nss_logs_core_ops = {
+	.owner = THIS_MODULE,
+	.open = nss_log_open,
+	.read = nss_log_read,
+	.release = nss_log_release,
+	.llseek = nss_log_llseek,
+};
+
+/*
+ * nss_debug_interface_set_callback()
+ *	Sets the callback
+ */
+void nss_debug_interface_set_callback(nss_log_msg_callback_t cb, void *app_data)
+{
+	nss_debug_interface_cb = cb;
+	nss_debug_interface_app_data = app_data;
+}
+
+/*
+ * nss_debug_interface_event()
+ *	Received an event from NSS FW
+ */
+static void nss_debug_interface_event(void *app_data, struct nss_log_debug_interface_msg *nim)
+{
+	struct nss_cmn_msg *ncm = (struct nss_cmn_msg *)nim;
+
+	msg_response = ncm->response;
+	msg_event = true;
+	wake_up(&msg_wq);
+}
+
+/*
+ * nss_debug_interface_handler()
+ *	handle NSS -> HLOS messages for debug interfaces
+ */
+static void nss_debug_interface_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_log_debug_interface_msg *ntm = (struct nss_log_debug_interface_msg *)ncm;
+	nss_log_msg_callback_t cb;
+
+	BUG_ON(ncm->interface != NSS_DEBUG_INTERFACE);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type > NSS_DEBUG_INTERFACE_TYPE_MAX) {
+		nss_warning("%px: received invalid message %d for CAPWAP interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_log_debug_interface_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_debug_interface_cb;
+		ncm->app_data = (nss_ptr_t)nss_debug_interface_app_data;
+	}
+
+	/*
+	 * Do we have a callback
+	 */
+	if (!ncm->cb) {
+		nss_trace("%px: cb is null for interface %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb = (nss_log_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, ntm);
+}
+
+/*
+ * nss_debug_interface_tx()
+ *	Transmit a debug interface message to NSS FW
+ */
+static nss_tx_status_t nss_debug_interface_tx(struct nss_ctx_instance *nss_ctx, struct nss_log_debug_interface_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Sanity check the message
+	 */
+	if (ncm->interface != NSS_DEBUG_INTERFACE) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_DEBUG_INTERFACE_TYPE_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ * nss_debug_log_buffer_alloc()
+ *	Allocates and Initializes log buffer for the use in NSS FW (logging)
+ */
+bool nss_debug_log_buffer_alloc(uint8_t nss_id, uint32_t nentry)
+{
+	struct nss_log_debug_interface_msg msg;
+	struct nss_log_debug_memory_msg *dbg;
+	struct nss_top_instance *nss_top;
+	struct nss_ctx_instance *nss_ctx;
+	dma_addr_t dma_addr;
+	uint32_t size;
+	void *addr = NULL;
+	nss_tx_status_t status;
+
+	if (nss_id >= nss_top_main.num_nss) {
+		return false;
+	}
+
+	nss_top = &nss_top_main;
+	nss_ctx = &nss_top->nss[nss_id];
+
+	if (nss_ctx->state != NSS_CORE_STATE_INITIALIZED) {
+		nss_warning("%px: NSS Core:%d is not initialized yet\n", nss_ctx, nss_id);
+		return false;
+	}
+
+	size = sizeof(struct nss_log_descriptor) + (sizeof(struct nss_log_entry) * nentry);
+	addr = kmalloc(size, GFP_ATOMIC);
+	if (!addr) {
+		nss_warning("%px: Failed to allocate memory for logging (size:%d)\n", nss_ctx, size);
+		return false;
+	}
+
+	memset(addr, 0, size);
+	dma_addr = (uint32_t)dma_map_single(nss_ctx->dev, addr, size, DMA_FROM_DEVICE);
+	if (unlikely(dma_mapping_error(nss_ctx->dev, dma_addr))) {
+		nss_warning("%px: Failed to map address in DMA", nss_ctx);
+		kfree(addr);
+		return false;
+	}
+
+	/*
+	 * If we already have ring buffer associated with nss_id, then
+	 * we must wait before we attach a new ring buffer.
+	 */
+	mutex_lock(&nss_log_mutex);
+	if (nss_rbe[nss_id].addr) {
+		mutex_unlock(&nss_log_mutex);
+
+		/*
+		 * Someone is using the current logbuffer. Wait until ref count become 0.
+		 * We have to return mutex here, because the current user requires it to
+		 * release the reference.
+		 */
+		if (!wait_event_timeout(nss_log_wq, !nss_rbe[nss_id].ref_cnt, 5 * HZ)) {
+			nss_warning("%px: Timeout waiting for refcnt to become 0\n", nss_ctx);
+			goto fail;
+		}
+
+		mutex_lock(&nss_log_mutex);
+		if (!nss_rbe[nss_id].addr) {
+			mutex_unlock(&nss_log_mutex);
+			goto fail;
+		}
+		if (nss_rbe[nss_id].ref_cnt > 0) {
+			mutex_unlock(&nss_log_mutex);
+			nss_warning("%px: Some other thread is contending..opting out\n", nss_ctx);
+			goto fail;
+		}
+	}
+
+	memset(&msg, 0, sizeof(struct nss_log_debug_interface_msg));
+	nss_cmn_msg_init(&msg.cm, NSS_DEBUG_INTERFACE, NSS_DEBUG_INTERFACE_TYPE_LOG_BUF_INIT,
+		sizeof(struct nss_log_debug_memory_msg), nss_debug_interface_event, NULL);
+
+	dbg = &msg.msg.addr;
+	dbg->nentry = nentry;
+	dbg->version = NSS_DEBUG_LOG_VERSION;
+	dbg->phy_addr = dma_addr;
+
+	msg_event = false;
+	status = nss_debug_interface_tx(nss_ctx, &msg);
+	if (status != NSS_TX_SUCCESS) {
+		mutex_unlock(&nss_log_mutex);
+		nss_warning("%px: Failed to send message to debug interface:%d\n", nss_ctx, status);
+		goto fail;
+	}
+
+	/*
+	 * Wait for 5 seconds since this is a critical operation.
+	 * Mutex is not unlocked here because we do not want someone to acquire the mutex and use the logbuffer
+	 * while we are waiting message from NSS.
+	 */
+	if (!wait_event_timeout(msg_wq, msg_event, 5 * HZ)) {
+		mutex_unlock(&nss_log_mutex);
+		nss_warning("%px: Timeout send message to debug interface\n", nss_ctx);
+		goto fail;
+	}
+
+	if (msg_response != NSS_CMN_RESPONSE_ACK) {
+		mutex_unlock(&nss_log_mutex);
+		nss_warning("%px: Response error for send message to debug interface:%d\n", nss_ctx, msg_response);
+		goto fail;
+	}
+
+	/*
+	 * If we had to free the previous allocation for ring buffer.
+	 */
+	if (nss_rbe[nss_id].addr) {
+		uint32_t old_size;
+		old_size = sizeof(struct nss_log_descriptor) +
+			(sizeof(struct nss_log_entry) * nss_rbe[nss_id].nentries);
+		dma_unmap_single(nss_ctx->dev, nss_rbe[nss_id].dma_addr, old_size, DMA_FROM_DEVICE);
+		kfree(nss_rbe[nss_id].addr);
+	}
+
+	nss_rbe[nss_id].addr = addr;
+	nss_rbe[nss_id].nentries = nentry;
+	nss_rbe[nss_id].ref_cnt = 0;
+	nss_rbe[nss_id].dma_addr = dma_addr;
+	mutex_unlock(&nss_log_mutex);
+	wake_up(&nss_log_wq);
+	return true;
+
+fail:
+	dma_unmap_single(nss_ctx->dev, dma_addr, size, DMA_FROM_DEVICE);
+	kfree(addr);
+	wake_up(&nss_log_wq);
+	return false;
+}
+
+/*
+ * nss_logbuffer_handler()
+ *	Enable NSS debug output
+ */
+int nss_logbuffer_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret;
+	int core_status;
+	int i;
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret)  {
+		return ret;
+	}
+
+	if (!write) {
+		return ret;
+	}
+
+	if (nss_ctl_logbuf < 32) {
+		nss_warning("Invalid NSS FW logbuffer size:%d (must be > 32)\n", nss_ctl_logbuf);
+		nss_ctl_logbuf = 0;
+		return ret;
+	}
+
+	for (i = 0; i < nss_top_main.num_nss; i++) {
+		/*
+		 * Register the callback handler and allocate the debug log buffers
+		 */
+		core_status = nss_core_register_handler(&nss_top_main.nss[i], NSS_DEBUG_INTERFACE, nss_debug_interface_handler, NULL);
+		if (core_status != NSS_CORE_STATUS_SUCCESS) {
+			nss_warning("NSS logbuffer init failed with register handler:%d\n", core_status);
+		}
+
+		if (!nss_debug_log_buffer_alloc(i, nss_ctl_logbuf)) {
+			nss_warning("%d: Failed to set debug log buffer on NSS core", i);
+		}
+	}
+
+	return ret;
+}
+
+/*
+ * nss_log_init()
+ *	Initializes NSS FW logs retrieval logic from /sys
+ */
+void nss_log_init(void)
+{
+	int i;
+	struct dentry *logs_dentry;
+	struct dentry *core_log_dentry;
+
+	memset(nss_rbe, 0, sizeof(nss_rbe));
+	init_waitqueue_head(&nss_log_wq);
+	init_waitqueue_head(&msg_wq);
+
+	/*
+	 * Create directory for obtaining NSS FW logs from each core
+	 */
+	logs_dentry = debugfs_create_dir("logs", nss_top_main.top_dentry);
+	if (unlikely(!logs_dentry)) {
+		nss_warning("Failed to create qca-nss-drv/logs directory in debugfs");
+		return;
+	}
+
+	for (i = 0; i < nss_top_main.num_nss; i++) {
+		char file[16];
+		extern struct file_operations nss_logs_core_ops;
+
+		snprintf(file, sizeof(file), "core%d", i);
+		core_log_dentry = debugfs_create_file(file, 0400,
+						logs_dentry, (void *)(nss_ptr_t)i, &nss_logs_core_ops);
+		if (unlikely(!core_log_dentry)) {
+			nss_warning("Failed to create qca-nss-drv/logs/%s file in debugfs", file);
+			return;
+		}
+	}
+
+	nss_debug_interface_set_callback(nss_debug_interface_event, NULL);
+}
diff --git a/qca-nss-drv/nss_log.h b/qca-nss-drv/nss_log.h
new file mode 100644
index 0000000..1d27e94
--- /dev/null
+++ b/qca-nss-drv/nss_log.h
@@ -0,0 +1,115 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, 2018, 2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+/*
+ * nss_log.h
+ *	NSS FW debug log memory header file
+ */
+
+#ifndef __NSS_LOG_H
+#define __NSS_LOG_H
+
+#define NSS_DEBUG_LOG_VERSION		0x1
+
+/**
+ * Dynamic Interface types
+ */
+enum nss_debug_interface_msg_type {
+	NSS_DEBUG_INTERFACE_TYPE_NONE = 0,
+	NSS_DEBUG_INTERFACE_TYPE_LOG_BUF_INIT = 1,
+	NSS_DEBUG_INTERFACE_TYPE_MAX,
+};
+
+/*
+ * The size of each log entry to be displayed.
+ */
+#define	NSS_LOG_OUTPUT_LINE_SIZE	151	/* 5 + 12 + 132 + '\n' + '\0' (see below) */
+#define	NSS_LOG_LINE_FORMAT		"%3d: %010u: %s\n"
+#define	NSS_LOG_LINE_WIDTH		132
+#define	NSS_LOG_COOKIE			0xFF785634
+
+/*
+ * Dump last N entry during the coredump.
+ * This number should be lower than the minimum size of the logbuf
+ * which 32 right now.
+ */
+#define NSS_LOG_COREDUMP_LINE_NUM	25
+
+/*
+ * Saves the ring buffer address for logging per NSS core
+ */
+struct nss_log_ring_buffer_addr {
+	void *addr;		/* Pointer to struct nss_log_descriptor */
+	dma_addr_t dma_addr;	/* DMA Handle */
+	uint32_t nentries;	/* Number of entries in the ring buffer */
+	int ref_cnt;		/* Reference count */
+};
+
+/*
+ * nss_log_entry is shared between Host and NSS FW
+ */
+struct nss_log_entry {
+	uint64_t sequence_num;		/* Sequence number */
+	uint32_t cookie;		/* Magic for verification */
+	uint32_t thread_num;		/* thread-id */
+	uint32_t timestamp;		/* timestamp in ticks */
+	char message[NSS_LOG_LINE_WIDTH];	/* actual debug message */
+} __attribute__((aligned(NSS_CACHE_LINE_SIZE)));
+
+/*
+ * The NSS log descripts holds ring-buffer along with other variables and
+ * it is shared between NSS FW and Host.
+ *
+ * NSS FW writes to ring buffer and current_entry but read by only Host.
+ */
+struct nss_log_descriptor {
+	uint32_t cookie;		/* Magic for verification */
+	uint32_t log_nentries;		/* No.of log entries */
+	uint32_t current_entry;		/* pointer to current log entry */
+	uint8_t  pad[20];			/* pad to align ring buffer at cacheline boundary */
+	struct nss_log_entry log_ring_buffer[0];	/* The actual log entry ring buffer */
+} __attribute__((aligned(NSS_CACHE_LINE_SIZE)));
+
+struct nss_log_debug_memory_msg {
+	uint32_t version;
+	uint32_t nentry;
+	uint32_t phy_addr;
+};
+
+struct nss_log_debug_interface_msg {
+	struct nss_cmn_msg cm;
+	union {
+		struct nss_log_debug_memory_msg addr;
+	} msg;
+};
+
+/**
+ * @brief Callback to receive debug interface messages
+ *
+ * @param app_data Application context of the message
+ * @param msg Message data
+ *
+ * @return void
+ */
+typedef void (*nss_log_msg_callback_t)(void *app_data, struct nss_log_debug_interface_msg *msg);
+
+/*
+ * Exported by nss_init.c and used in nss_log.c
+ */
+extern int nss_ctl_logbuf;
+
+extern struct nss_log_ring_buffer_addr nss_rbe[NSS_MAX_CORES];
+
+#endif /* __NSS_LOG_H */
diff --git a/qca-nss-drv/nss_lso_rx.c b/qca-nss-drv/nss_lso_rx.c
new file mode 100644
index 0000000..3abda01
--- /dev/null
+++ b/qca-nss-drv/nss_lso_rx.c
@@ -0,0 +1,62 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014,2017,2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_lso_rx.c
+ *	NSS LSO_RX APIs
+ */
+
+#include <nss_core.h>
+#include "nss_lso_rx_stats.h"
+#include "nss_lso_rx_strings.h"
+
+/*
+ * nss_rx_lso_rx_interface_handler()
+ *	Handle NSS -> HLOS messages for LSO_RX Changes and Statistics
+ */
+static void nss_rx_lso_rx_interface_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data) {
+
+	struct nss_lso_rx_msg *nlrm = (struct nss_lso_rx_msg *)ncm;
+
+	switch (nlrm->cm.type) {
+	case NSS_LSO_RX_STATS_SYNC_MSG:
+		/*
+		 * Update LSO_RX driver statistics and send statistics notifications to the registered modules
+		 */
+		nss_lso_rx_stats_sync(nss_ctx, &nlrm->msg.stats_sync);
+		nss_lso_rx_stats_notify(nss_ctx);
+		break;
+
+	default:
+		if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+			/*
+			 * Check response
+			 */
+			nss_info("%px: Received response %d for type %d, interface %d", nss_ctx, ncm->response, ncm->type, ncm->interface);
+		}
+	}
+}
+
+/*
+ * nss_lso_rx_register_handler()
+ *	Register handler for messaging
+ */
+void nss_lso_rx_register_handler(struct nss_ctx_instance *nss_ctx)
+{
+	nss_core_register_handler(nss_ctx, NSS_LSO_RX_INTERFACE, nss_rx_lso_rx_interface_handler, NULL);
+	nss_lso_rx_stats_dentry_create();
+	nss_lso_rx_strings_dentry_create();
+}
diff --git a/qca-nss-drv/nss_lso_rx_stats.c b/qca-nss-drv/nss_lso_rx_stats.c
new file mode 100644
index 0000000..2763a2a
--- /dev/null
+++ b/qca-nss-drv/nss_lso_rx_stats.c
@@ -0,0 +1,172 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017,2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_lso_rx_stats.h"
+#include "nss_lso_rx_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_lso_rx_stats_notifier);
+
+uint64_t nss_lso_rx_stats[NSS_LSO_RX_STATS_MAX];	/* LSO_RX statistics */
+
+/*
+ * nss_lso_rx_stats_read()
+ *	Read LSO_RX stats
+ */
+static ssize_t nss_lso_rx_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * Max output lines = #stats + few blank lines for banner printing +
+	 * Number of Extra outputlines for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_STATS_NODE_MAX + NSS_LSO_RX_STATS_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_LSO_RX_STATS_MAX * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "lso_rx", NSS_STATS_SINGLE_CORE);
+	size_wr += nss_stats_fill_common_stats(NSS_LSO_RX_INTERFACE, NSS_STATS_SINGLE_INSTANCE, lbuf, size_wr, size_al, "lso_rx");
+
+	/*
+	 * lso_rx node stats
+	 */
+
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; (i < NSS_LSO_RX_STATS_MAX); i++) {
+		stats_shadow[i] = nss_lso_rx_stats[i];
+	}
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+	size_wr += nss_stats_print("lso_rx", "lso_rx node stats"
+					, NSS_STATS_SINGLE_INSTANCE
+					, nss_lso_rx_strings_stats
+					, stats_shadow
+					, NSS_LSO_RX_STATS_MAX
+					, lbuf, size_wr, size_al);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_lso_rx_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(lso_rx);
+
+/*
+ * nss_lso_rx_stats_dentry_create()
+ *	Create lso_rx statistics debug entry.
+ */
+void nss_lso_rx_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("lso_rx", &nss_lso_rx_stats_ops);
+}
+
+/*
+ * nss_lso_rx_stats_sync()
+ *	Handle the syncing of lso_rx node statistics.
+ */
+void nss_lso_rx_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_lso_rx_stats_sync *nlrss)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	int j;
+
+	spin_lock_bh(&nss_top->stats_lock);
+
+	/*
+	 * common node stats
+	 */
+	nss_top->stats_node[NSS_LSO_RX_INTERFACE][NSS_STATS_NODE_RX_PKTS] += nlrss->node_stats.rx_packets;
+	nss_top->stats_node[NSS_LSO_RX_INTERFACE][NSS_STATS_NODE_RX_BYTES] += nlrss->node_stats.rx_bytes;
+	nss_top->stats_node[NSS_LSO_RX_INTERFACE][NSS_STATS_NODE_TX_PKTS] += nlrss->node_stats.tx_packets;
+	nss_top->stats_node[NSS_LSO_RX_INTERFACE][NSS_STATS_NODE_TX_BYTES] += nlrss->node_stats.tx_bytes;
+
+	for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+		nss_top->stats_node[NSS_LSO_RX_INTERFACE][NSS_STATS_NODE_RX_QUEUE_0_DROPPED + j] += nlrss->node_stats.rx_dropped[j];
+	}
+
+	/*
+	 * General LSO_RX stats
+	 */
+	nss_lso_rx_stats[NSS_LSO_RX_STATS_TX_DROPPED] += nlrss->tx_dropped;
+	nss_lso_rx_stats[NSS_LSO_RX_STATS_DROPPED] += nlrss->dropped;
+
+	/*
+	 * pbuf
+	 */
+	nss_lso_rx_stats[NSS_LSO_RX_STATS_PBUF_ALLOC_FAIL] += nlrss->pbuf_alloc_fail;
+	nss_lso_rx_stats[NSS_LSO_RX_STATS_PBUF_REFERENCE_FAIL] += nlrss->pbuf_reference_fail;
+
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_lso_rx_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_lso_rx_stats_notify(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_lso_rx_stats_notification lso_rx_stats;
+
+	lso_rx_stats.core_id = nss_ctx->id;
+	memcpy(lso_rx_stats.cmn_node_stats, nss_top_main.stats_node[NSS_LSO_RX_INTERFACE], sizeof(lso_rx_stats.cmn_node_stats));
+	memcpy(lso_rx_stats.node_stats, nss_lso_rx_stats, sizeof(lso_rx_stats.node_stats));
+	atomic_notifier_call_chain(&nss_lso_rx_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&lso_rx_stats);
+}
+
+/*
+ * nss_lso_rx_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_lso_rx_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_lso_rx_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_lso_rx_stats_register_notifier);
+
+/*
+ * nss_lso_rx_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_lso_rx_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_lso_rx_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_lso_rx_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_lso_rx_stats.h b/qca-nss-drv/nss_lso_rx_stats.h
new file mode 100644
index 0000000..54ab6dc
--- /dev/null
+++ b/qca-nss-drv/nss_lso_rx_stats.h
@@ -0,0 +1,67 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017,2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_LSO_RX_STATS_H
+#define __NSS_LSO_RX_STATS_H
+
+#include <nss_cmn.h>
+
+/*
+ * lso_rx_node statistics.
+ */
+struct nss_lso_rx_stats_sync {
+	struct nss_cmn_node_stats node_stats;
+
+	uint32_t tx_dropped;				/* Number of packets dropped because lso_rx transmit queue is full */
+	uint32_t dropped;				/* Total of packets dropped by the node internally */
+	uint32_t pbuf_alloc_fail;			/* Count number of pbuf alloc fails */
+	uint32_t pbuf_reference_fail;			/* Count number of pbuf ref fails */
+
+	/*
+	 * If we're generating per-packet statistics then we count total lso_rx processing ticks
+	 * worst-case ticks and the number of iterations around the lso_rx handler that we take.
+	 */
+	uint32_t total_ticks;				/* Total clock ticks spend inside the lso_rx handler */
+	uint32_t worst_case_ticks;
+							/* Worst case iteration of the lso_rx handler in ticks */
+	uint32_t iterations;				/* Number of iterations around the lso_rx handler */
+};
+
+/*
+ * Message types for lso_rx
+ */
+enum nss_lso_rx_metadata_types {
+	NSS_LSO_RX_STATS_SYNC_MSG,			/* Message type - stats sync message */
+};
+
+/*
+ * Message structure to send receive LSO_RX commands
+ */
+struct nss_lso_rx_msg {
+	struct nss_cmn_msg cm;					/* Message header */
+	union {
+		struct nss_lso_rx_stats_sync stats_sync;	/* Stats sub-message */
+	} msg;
+};
+
+/*
+ * lso_rx statistics APIs
+ */
+extern void nss_lso_rx_stats_notify(struct nss_ctx_instance *nss_ctx);
+extern void nss_lso_rx_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_lso_rx_stats_sync *nlrss);
+extern void nss_lso_rx_stats_dentry_create(void);
+
+#endif /* __NSS_LSO_RX_STATS_H */
diff --git a/qca-nss-drv/nss_lso_rx_strings.c b/qca-nss-drv/nss_lso_rx_strings.c
new file mode 100644
index 0000000..627f1de
--- /dev/null
+++ b/qca-nss-drv/nss_lso_rx_strings.c
@@ -0,0 +1,57 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include <nss_lso_rx.h>
+#include "nss_strings.h"
+#include "nss_lso_rx_strings.h"
+
+/*
+ * nss_lso_rx_strings_stats
+ *	LSO Rx statistics strings.
+ */
+struct nss_stats_info nss_lso_rx_strings_stats[NSS_LSO_RX_STATS_MAX] = {
+	{"tx_drops"		,NSS_STATS_TYPE_DROP},
+	{"drops"		,NSS_STATS_TYPE_DROP},
+	{"pbuf_alloc_fail"	,NSS_STATS_TYPE_ERROR},
+	{"pbuf_reference_fail"	,NSS_STATS_TYPE_ERROR}
+};
+
+/*
+ * nss_lso_rx_strings_read()
+ *	Read LSO Rx node statistics names.
+ */
+static ssize_t nss_lso_rx_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_lso_rx_strings_stats, NSS_LSO_RX_STATS_MAX);
+}
+
+/*
+ * nss_lso_rx_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(lso_rx);
+
+/*
+ * nss_lso_rx_strings_dentry_create()
+ *	Create LSO Rx statistics strings debug entry.
+ */
+void nss_lso_rx_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("lso_rx", &nss_lso_rx_strings_ops);
+}
diff --git a/qca-nss-drv/nss_lso_rx_strings.h b/qca-nss-drv/nss_lso_rx_strings.h
new file mode 100644
index 0000000..901ed30
--- /dev/null
+++ b/qca-nss-drv/nss_lso_rx_strings.h
@@ -0,0 +1,25 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_LSO_RX_STRINGS_H
+#define __NSS_LSO_RX_STRINGS_H
+
+extern struct nss_stats_info nss_lso_rx_strings_stats[NSS_LSO_RX_STATS_MAX];
+extern void nss_lso_rx_strings_dentry_create(void);
+
+#endif /* __NSS_LSO_RX_STRINGS_H */
diff --git a/qca-nss-drv/nss_map_t.c b/qca-nss-drv/nss_map_t.c
new file mode 100644
index 0000000..cfa7ab9
--- /dev/null
+++ b/qca-nss-drv/nss_map_t.c
@@ -0,0 +1,412 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_map_t_stats.h"
+#include "nss_map_t_log.h"
+#include "nss_map_t_strings.h"
+
+#define NSS_MAP_T_TX_TIMEOUT 3000 /* 3 Seconds */
+
+/*
+ * Private data structure
+ */
+static struct {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+	void *cb;
+	void *app_data;
+} nss_map_t_pvt;
+
+/*
+ * Data structures to store map_t nss debug stats
+ */
+static DEFINE_SPINLOCK(nss_map_t_debug_stats_lock);
+static struct nss_map_t_stats_instance_debug nss_map_t_debug_stats[NSS_MAX_MAP_T_DYNAMIC_INTERFACES];
+
+/*
+ * nss_map_t_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static bool nss_map_t_verify_if_num(uint32_t if_num)
+{
+	enum nss_dynamic_interface_type if_type;
+
+	if (nss_is_dynamic_interface(if_num) == false) {
+		return false;
+	}
+
+	if_type = nss_dynamic_interface_get_type(nss_map_t_get_context(), if_num);
+	switch (if_type) {
+	case NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_INNER:
+	case NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_OUTER:
+		return true;
+
+	default:
+		return false;
+	}
+}
+
+/*
+ * nss_map_t_instance_debug_stats_sync
+ *	debug stats for map_t
+ */
+void nss_map_t_instance_debug_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_map_t_sync_stats_msg *stats_msg, uint16_t if_num)
+{
+	int i;
+	enum nss_dynamic_interface_type if_type;
+
+	if_type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+
+	spin_lock_bh(&nss_map_t_debug_stats_lock);
+	for (i = 0; i < NSS_MAX_MAP_T_DYNAMIC_INTERFACES; i++) {
+		if (nss_map_t_debug_stats[i].if_num != if_num) {
+			continue;
+		}
+		switch (if_type) {
+		case NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_INNER:
+			nss_map_t_debug_stats[i].stats[NSS_MAP_T_STATS_V4_TO_V6_PBUF_EXCEPTION] +=
+				stats_msg->debug_stats.v4_to_v6.exception_pkts;
+			nss_map_t_debug_stats[i].stats[NSS_MAP_T_STATS_V4_TO_V6_PBUF_NO_MATCHING_RULE] +=
+				stats_msg->debug_stats.v4_to_v6.no_matching_rule;
+			nss_map_t_debug_stats[i].stats[NSS_MAP_T_STATS_V4_TO_V6_PBUF_NOT_TCP_OR_UDP] +=
+				stats_msg->debug_stats.v4_to_v6.not_tcp_or_udp;
+			nss_map_t_debug_stats[i].stats[NSS_MAP_T_STATS_V4_TO_V6_RULE_ERR_LOCAL_PSID] +=
+				stats_msg->debug_stats.v4_to_v6.rule_err_local_psid;
+			nss_map_t_debug_stats[i].stats[NSS_MAP_T_STATS_V4_TO_V6_RULE_ERR_LOCAL_IPV6] +=
+				stats_msg->debug_stats.v4_to_v6.rule_err_local_ipv6;
+			nss_map_t_debug_stats[i].stats[NSS_MAP_T_STATS_V4_TO_V6_RULE_ERR_REMOTE_PSID] +=
+				stats_msg->debug_stats.v4_to_v6.rule_err_remote_psid;
+			nss_map_t_debug_stats[i].stats[NSS_MAP_T_STATS_V4_TO_V6_RULE_ERR_REMOTE_EA_BITS] +=
+				stats_msg->debug_stats.v4_to_v6.rule_err_remote_ea_bits;
+			nss_map_t_debug_stats[i].stats[NSS_MAP_T_STATS_V4_TO_V6_RULE_ERR_REMOTE_IPV6] +=
+				stats_msg->debug_stats.v4_to_v6.rule_err_remote_ipv6;
+			break;
+
+		case NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_OUTER:
+			nss_map_t_debug_stats[i].stats[NSS_MAP_T_STATS_V6_TO_V4_PBUF_EXCEPTION] +=
+				stats_msg->debug_stats.v6_to_v4.exception_pkts;
+			nss_map_t_debug_stats[i].stats[NSS_MAP_T_STATS_V6_TO_V4_PBUF_NO_MATCHING_RULE] +=
+				stats_msg->debug_stats.v6_to_v4.no_matching_rule;
+			nss_map_t_debug_stats[i].stats[NSS_MAP_T_STATS_V6_TO_V4_PBUF_NOT_TCP_OR_UDP] +=
+				stats_msg->debug_stats.v6_to_v4.not_tcp_or_udp;
+			nss_map_t_debug_stats[i].stats[NSS_MAP_T_STATS_V6_TO_V4_RULE_ERR_LOCAL_IPV4] +=
+				stats_msg->debug_stats.v6_to_v4.rule_err_local_ipv4;
+			nss_map_t_debug_stats[i].stats[NSS_MAP_T_STATS_V6_TO_V4_RULE_ERR_REMOTE_IPV4] +=
+				stats_msg->debug_stats.v6_to_v4.rule_err_remote_ipv4;
+			break;
+
+		default:
+			nss_warning("Invalid MAP-T interface encountered: %u\n", if_type);
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_map_t_debug_stats_lock);
+}
+
+/*
+ * nss_map_t_instance_debug_stats_get()
+ *	Get map_t statitics.
+ */
+void nss_map_t_instance_debug_stats_get(void *stats_mem)
+{
+	struct nss_map_t_stats_instance_debug *stats = (struct nss_map_t_stats_instance_debug *)stats_mem;
+	int i;
+
+	if (!stats) {
+		nss_warning("No memory to copy map_t stats");
+		return;
+	}
+
+	spin_lock_bh(&nss_map_t_debug_stats_lock);
+	for (i = 0; i < NSS_MAX_MAP_T_DYNAMIC_INTERFACES; i++) {
+		if (nss_map_t_debug_stats[i].valid) {
+			memcpy(stats, &nss_map_t_debug_stats[i], sizeof(struct nss_map_t_stats_instance_debug));
+			stats++;
+		}
+	}
+	spin_unlock_bh(&nss_map_t_debug_stats_lock);
+}
+
+/*
+ * nss_map_t_handler()
+ *	Handle NSS -> HLOS messages for map_t tunnel
+ */
+static void nss_map_t_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_map_t_msg *ntm = (struct nss_map_t_msg *)ncm;
+	void *ctx;
+
+	nss_map_t_msg_callback_t cb;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	BUG_ON(!nss_map_t_verify_if_num(ncm->interface));
+
+	/*
+	 * Trace Messages
+	 */
+	nss_map_t_log_rx_msg(ntm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_MAP_T_MSG_MAX) {
+		nss_warning("%px: received invalid message %d for MAP-T interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_map_t_msg)) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	switch (ntm->cm.type) {
+	case NSS_MAP_T_MSG_SYNC_STATS:
+		/*
+		 * Update debug stats in stats msg and send statistics notifications to the registered modules
+		 */
+		nss_map_t_instance_debug_stats_sync(nss_ctx, &ntm->msg.stats, ncm->interface);
+		nss_map_t_stats_notify(nss_ctx, ncm->interface);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, map_t sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->map_t_msg_callback;
+		ncm->app_data = (nss_ptr_t)nss_ctx->subsys_dp_register[ncm->interface].app_data;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * callback
+	 */
+	cb = (nss_map_t_msg_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	/*
+	 * call map-t callback
+	 */
+	if (!cb) {
+		nss_warning("%px: No callback for map-t interface %d",
+			    nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb(ctx, ntm);
+}
+
+/*
+ * nss_map_t_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_map_t_callback(void *app_data, struct nss_map_t_msg *nim)
+{
+	nss_map_t_msg_callback_t callback = (nss_map_t_msg_callback_t)nss_map_t_pvt.cb;
+	void *data = nss_map_t_pvt.app_data;
+
+	nss_map_t_pvt.cb = NULL;
+	nss_map_t_pvt.app_data = NULL;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("map_t Error response %d\n", nim->cm.response);
+		nss_map_t_pvt.response = NSS_TX_FAILURE;
+	} else {
+		nss_map_t_pvt.response = NSS_TX_SUCCESS;
+	}
+
+	if (callback) {
+		callback(data, nim);
+	}
+
+	complete(&nss_map_t_pvt.complete);
+}
+
+/*
+ * nss_map_t_tx()
+ *	Transmit a map_t message to NSS firmware
+ */
+nss_tx_status_t nss_map_t_tx(struct nss_ctx_instance *nss_ctx, struct nss_map_t_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_map_t_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!nss_map_t_verify_if_num(ncm->interface)) {
+		nss_warning("%px: tx request is not for a MAP-T dynamic interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_MAP_T_MSG_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_map_t_tx);
+
+/*
+ * nss_map_t_tx_sync()
+ *	Transmit a MAP-T message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_map_t_tx_sync(struct nss_ctx_instance *nss_ctx, struct nss_map_t_msg *msg)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&nss_map_t_pvt.sem);
+	nss_map_t_pvt.cb = (void *)msg->cm.cb;
+	nss_map_t_pvt.app_data = (void *)msg->cm.app_data;
+
+	msg->cm.cb = (nss_ptr_t)nss_map_t_callback;
+	msg->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_map_t_tx(nss_ctx, msg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: map_t_tx_msg failed\n", nss_ctx);
+		up(&nss_map_t_pvt.sem);
+		return status;
+	}
+	ret = wait_for_completion_timeout(&nss_map_t_pvt.complete, msecs_to_jiffies(NSS_MAP_T_TX_TIMEOUT));
+
+	if (!ret) {
+		nss_warning("%px: MAP-T tx sync failed due to timeout\n", nss_ctx);
+		nss_map_t_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = nss_map_t_pvt.response;
+	up(&nss_map_t_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_map_t_tx_sync);
+
+/*
+ ***********************************
+ * Register/Unregister/Miscellaneous APIs
+ ***********************************
+ */
+
+/*
+ * nss_map_t_register_if()
+ */
+struct nss_ctx_instance *nss_map_t_register_if(uint32_t if_num, uint32_t type, nss_map_t_callback_t map_t_callback,
+			nss_map_t_msg_callback_t event_callback, struct net_device *netdev, uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.map_t_handler_id];
+	int i = 0;
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_map_t_verify_if_num(if_num));
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, map_t_callback, 0, netdev, netdev, features);
+	nss_ctx->subsys_dp_register[if_num].type = type;
+
+	nss_top_main.map_t_msg_callback = event_callback;
+
+	nss_core_register_handler(nss_ctx, if_num, nss_map_t_handler, NULL);
+
+	spin_lock_bh(&nss_map_t_debug_stats_lock);
+	for (i = 0; i < NSS_MAX_MAP_T_DYNAMIC_INTERFACES; i++) {
+		if (!nss_map_t_debug_stats[i].valid) {
+			nss_map_t_debug_stats[i].valid = true;
+			nss_map_t_debug_stats[i].if_num = if_num;
+			nss_map_t_debug_stats[i].if_index = netdev->ifindex;
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_map_t_debug_stats_lock);
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_map_t_register_if);
+
+/*
+ * nss_map_t_unregister_if()
+ */
+void nss_map_t_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.map_t_handler_id];
+	int i;
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_map_t_verify_if_num(if_num));
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	nss_top_main.map_t_msg_callback = NULL;
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+
+	spin_lock_bh(&nss_map_t_debug_stats_lock);
+	for (i = 0; i < NSS_MAX_MAP_T_DYNAMIC_INTERFACES; i++) {
+		if (nss_map_t_debug_stats[i].if_num == if_num) {
+			memset(&nss_map_t_debug_stats[i], 0, sizeof(struct nss_map_t_stats_instance_debug));
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_map_t_debug_stats_lock);
+}
+EXPORT_SYMBOL(nss_map_t_unregister_if);
+
+/*
+ * nss_get_map_t_context()
+ */
+struct nss_ctx_instance *nss_map_t_get_context()
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.map_t_handler_id];
+}
+EXPORT_SYMBOL(nss_map_t_get_context);
+
+/*
+ * nss_map_t_msg_init()
+ *	Initialize nss_map_t msg.
+ */
+void nss_map_t_msg_init(struct nss_map_t_msg *ncm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+EXPORT_SYMBOL(nss_map_t_msg_init);
+
+/*
+ * nss_map_t_register_handler()
+ *	debugfs stats msg handler received on static map_t interface
+ */
+void nss_map_t_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_map_t_get_context();
+
+	nss_info("nss_map_t_register_handler");
+	sema_init(&nss_map_t_pvt.sem, 1);
+	init_completion(&nss_map_t_pvt.complete);
+	nss_core_register_handler(nss_ctx, NSS_MAP_T_INTERFACE, nss_map_t_handler, NULL);
+
+	nss_map_t_stats_dentry_create();
+	nss_map_t_strings_dentry_create();
+}
diff --git a/qca-nss-drv/nss_map_t_log.c b/qca-nss-drv/nss_map_t_log.c
new file mode 100644
index 0000000..5f1ef39
--- /dev/null
+++ b/qca-nss-drv/nss_map_t_log.c
@@ -0,0 +1,151 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_map_t_log.c
+ *	NSS MAP_T logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_map_t_log_message_types_str
+ *	NSS MAP_T message strings
+ */
+static int8_t *nss_map_t_log_message_types_str[NSS_MAP_T_MSG_MAX] __maybe_unused = {
+	"MAP_T Rule Configure",
+	"MAP_T Rule Deconfigure",
+	"MAP_T Stats",
+};
+
+/*
+ * nss_map_t_log_rule_configure_msg()
+ *	Log NSS MAP_T Rule Configure.
+ */
+static void nss_map_t_log_rule_configure_msg(struct nss_map_t_msg *ntm)
+{
+	struct nss_map_t_instance_rule_config_msg *ntcm __maybe_unused = &ntm->msg.create_msg;
+	nss_trace("%px: NSS MAP_T Rule Configure message \n"
+		"MAP_T Rule Seq Number: %d\n"
+		"MAP_T Total Number of Rules: %d\n"
+		"MAP_T Local IPv6 Prefix Length: %d\n"
+		"MAP_T Local IPv4 Prefix: %d\n"
+		"MAP_T Local IPv4 Prefix Length: %d\n"
+		"MAP_T Local EA Bits Length: %d\n"
+		"MAP_T Local PSID Offset: %d\n"
+		"MAP_T Reserved A: %d\n"
+		"MAP_T Remote IPv6 Prefix Length: %d\n"
+		"MAP_T Remote IPv4 Prefix: %d\n"
+		"MAP_T Remote IPv4 Prefix Length: %d\n"
+		"MAP_T Remote EA Bits Length: %d\n"
+		"MAP_T Remote PSID Offset: %d\n"
+		"MAP_T Local MAP Style: %d\n"
+		"MAP_T Remote Map Style: %d\n"
+		"MAP_T Local IPv6 Prefix: %px\n"
+		"MAP_T Reserved B: %px\n"
+		"MAP_T Remote IPv6 Prefix: %px\n"
+		"MAP_T Valid Rule: %d\n",
+		ntcm, ntcm->rule_num, ntcm->total_rules,
+		ntcm->local_ipv6_prefix_len, ntcm->local_ipv4_prefix,
+		ntcm->local_ipv4_prefix_len, ntcm->local_ea_len,
+		ntcm->local_psid_offset, ntcm->reserve_a,
+		ntcm->remote_ipv6_prefix_len,
+		ntcm->remote_ipv4_prefix, ntcm->remote_ipv4_prefix_len,
+		ntcm->remote_ea_len, ntcm->remote_psid_offset,
+		ntcm->local_map_style, ntcm->remote_map_style,
+		ntcm->local_ipv6_prefix, ntcm->reserve_b,
+		ntcm->remote_ipv6_prefix, ntcm->valid_rule);
+}
+
+/*
+ * nss_map_t_log_rule_deconfig_msg()
+ *	Log NSS MAP_T Rule Deconfigure.
+ */
+static void nss_map_t_log_rule_deconfig_msg(struct nss_map_t_msg *ntm)
+{
+	struct nss_map_t_instance_rule_deconfig_msg *ntdm __maybe_unused = &ntm->msg.destroy_msg;
+	nss_trace("%px: NSS MAP_T Rule Deconfigure message \n"
+		"MAP_T Interface Number: %d\n",
+		ntdm, ntdm->if_number);
+}
+
+/*
+ * nss_map_t_log_verbose()
+ *	Log message contents.
+ */
+static void nss_map_t_log_verbose(struct nss_map_t_msg *ntm)
+{
+	switch (ntm->cm.type) {
+	case NSS_MAP_T_MSG_INSTANCE_RULE_CONFIGURE:
+		nss_map_t_log_rule_configure_msg(ntm);
+		break;
+
+	case NSS_MAP_T_MSG_INSTANCE_RULE_DECONFIGURE:
+		nss_map_t_log_rule_deconfig_msg(ntm);
+		break;
+
+	case NSS_MAP_T_MSG_SYNC_STATS:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", ntm);
+		break;
+	}
+}
+
+/*
+ * nss_map_t_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_map_t_log_tx_msg(struct nss_map_t_msg *ntm)
+{
+	if (ntm->cm.type >= NSS_MAP_T_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", ntm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ntm, ntm->cm.type, nss_map_t_log_message_types_str[ntm->cm.type]);
+	nss_map_t_log_verbose(ntm);
+}
+
+/*
+ * nss_map_t_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_map_t_log_rx_msg(struct nss_map_t_msg *ntm)
+{
+	if (ntm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ntm);
+		return;
+	}
+
+	if (ntm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ntm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ntm, ntm->cm.type,
+			nss_map_t_log_message_types_str[ntm->cm.type],
+			ntm->cm.response, nss_cmn_response_str[ntm->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		ntm, ntm->cm.type, nss_map_t_log_message_types_str[ntm->cm.type],
+		ntm->cm.response, nss_cmn_response_str[ntm->cm.response]);
+
+verbose:
+	nss_map_t_log_verbose(ntm);
+}
diff --git a/qca-nss-drv/nss_map_t_log.h b/qca-nss-drv/nss_map_t_log.h
new file mode 100644
index 0000000..3944889
--- /dev/null
+++ b/qca-nss-drv/nss_map_t_log.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_MAP_T_LOG_H
+#define __NSS_MAP_T_LOG_H
+
+/*
+ * nss_map_t.h
+ *	NSS MAP_T header file.
+ */
+
+/*
+ * Logger APIs
+ */
+
+/*
+ * nss_map_t_log_tx_msg
+ *	Logs a map_t message that is sent to the NSS firmware.
+ */
+void nss_map_t_log_tx_msg(struct nss_map_t_msg *ntm);
+
+/*
+ * nss_map_t_log_rx_msg
+ *	Logs a map_t message that is received from the NSS firmware.
+ */
+void nss_map_t_log_rx_msg(struct nss_map_t_msg *ntm);
+
+#endif /* __NSS_MAP_T_LOG_H */
diff --git a/qca-nss-drv/nss_map_t_stats.c b/qca-nss-drv/nss_map_t_stats.c
new file mode 100644
index 0000000..2dc4d9f
--- /dev/null
+++ b/qca-nss-drv/nss_map_t_stats.c
@@ -0,0 +1,154 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017,2019-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_map_t_stats.h"
+#include "nss_map_t_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_map_t_stats_notifier);
+
+/*
+ * nss_map_t_stats_read()
+ *	Read map_t statistics
+ */
+static ssize_t nss_map_t_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+
+	uint32_t max_output_lines = 2 /* header & footer for instance stats */
+					+ NSS_MAX_MAP_T_DYNAMIC_INTERFACES * (NSS_MAP_T_STATS_MAX + 2) /*instance stats */
+					+ 2;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	struct net_device *dev;
+	struct nss_map_t_stats_instance_debug map_t_instance_stats[NSS_MAX_MAP_T_DYNAMIC_INTERFACES];
+	int id, i;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	memset(&map_t_instance_stats, 0, sizeof(struct nss_map_t_stats_instance_debug) * NSS_MAX_MAP_T_DYNAMIC_INTERFACES);
+
+	/*
+	 * Get all stats
+	 */
+	nss_map_t_instance_debug_stats_get((void *)&map_t_instance_stats);
+
+	/*
+	 * Session stats
+	 */
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nmap_t instance stats start:\n\n");
+	for (id = 0; id < NSS_MAX_MAP_T_DYNAMIC_INTERFACES; id++) {
+
+			if (!map_t_instance_stats[id].valid) {
+				continue;
+			}
+
+			dev = dev_get_by_index(&init_net, map_t_instance_stats[id].if_index);
+			if (likely(dev)) {
+
+				size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%d. nss interface id=%d, netdevice=%s\n", id,
+						map_t_instance_stats[id].if_num, dev->name);
+				dev_put(dev);
+			} else {
+				size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%d. nss interface id=%d\n", id,
+						map_t_instance_stats[id].if_num);
+			}
+
+			for (i = 0; i < NSS_MAP_T_STATS_MAX; i++) {
+				size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+						     "\t%s = %llu\n", nss_map_t_strings_instance_stats[i].stats_name,
+						      map_t_instance_stats[id].stats[i]);
+			}
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+	}
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nmap_t instance stats end\n");
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_map_t_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(map_t);
+
+/*
+ * nss_map_t_stats_dentry_create()
+ *	Create map_t statistics debug entry.
+ */
+void nss_map_t_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("map_t", &nss_map_t_stats_ops);
+}
+
+/*
+ * nss_map_t_stats_notify()
+ *	Sends notifications to the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_map_t_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_map_t_stats_notification map_t_stats;
+	struct nss_map_t_stats_instance_debug map_t_instance_stats[NSS_MAX_MAP_T_DYNAMIC_INTERFACES];
+	int id;
+
+	memset(&map_t_instance_stats, 0, sizeof(map_t_instance_stats));
+
+	/*
+	 * Get all stats
+	 */
+	nss_map_t_instance_debug_stats_get((void *)&map_t_instance_stats);
+
+	for (id = 0; id < NSS_MAX_MAP_T_DYNAMIC_INTERFACES; id++) {
+		if (map_t_instance_stats[id].if_num == if_num) {
+			memcpy(&map_t_stats.stats, &map_t_instance_stats[id].stats, sizeof(map_t_stats.stats));
+		}
+	}
+	map_t_stats.if_type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+	map_t_stats.core_id = nss_ctx->id;
+	map_t_stats.if_num = if_num;
+	atomic_notifier_call_chain(&nss_map_t_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&map_t_stats);
+}
+
+/*
+ * nss_map_t_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_map_t_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_map_t_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_map_t_stats_register_notifier);
+
+/*
+ * nss_map_t_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_map_t_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_map_t_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_map_t_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_map_t_stats.h b/qca-nss-drv/nss_map_t_stats.h
new file mode 100644
index 0000000..8fa623a
--- /dev/null
+++ b/qca-nss-drv/nss_map_t_stats.h
@@ -0,0 +1,36 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2017,2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_MAP_T_STATS_H
+#define __NSS_MAP_T_STATS_H
+
+/*
+ * NSS core stats -- for H2N/N2H map_t debug stats
+ */
+struct nss_map_t_stats_instance_debug {
+	uint64_t stats[NSS_MAP_T_STATS_MAX];
+	int32_t if_index;
+	uint32_t if_num; /* nss interface number */
+	bool valid;
+};
+
+/*
+ * MAP-T statistics APIs
+ */
+extern void nss_map_t_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_map_t_stats_dentry_create(void);
+
+#endif /* __NSS_MAP_T_STATS_H */
diff --git a/qca-nss-drv/nss_map_t_strings.c b/qca-nss-drv/nss_map_t_strings.c
new file mode 100644
index 0000000..90fbf7e
--- /dev/null
+++ b/qca-nss-drv/nss_map_t_strings.c
@@ -0,0 +1,65 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include <nss_map_t.h>
+#include "nss_strings.h"
+
+/*
+ * nss_map_t_strings_instance_stats
+ *	MAP-T statistics strings for NSS session statistics.
+ */
+struct nss_stats_info nss_map_t_strings_instance_stats[NSS_MAP_T_STATS_MAX] = {
+	{"V4_TO_V6_PBUF_EXCEPTION_PKTS",	NSS_STATS_TYPE_EXCEPTION},
+	{"V4_TO_V6_PBUF_NO_MATCHING_RULE",	NSS_STATS_TYPE_SPECIAL},
+	{"V4_TO_V6_PBUF_NOT_TCP_OR_UDP",	NSS_STATS_TYPE_SPECIAL},
+	{"V4_TO_V6_RULE_ERR_LOCAL_PSID",	NSS_STATS_TYPE_ERROR},
+	{"V4_TO_V6_RULE_ERR_LOCAL_IPV6",	NSS_STATS_TYPE_ERROR},
+	{"V4_TO_V6_RULE_ERR_REMOTE_PSID",	NSS_STATS_TYPE_ERROR},
+	{"V4_TO_V6_RULE_ERR_REMOTE_EA_BITS",	NSS_STATS_TYPE_ERROR},
+	{"V4_TO_V6_RULE_ERR_REMOTE_IPV6",	NSS_STATS_TYPE_ERROR},
+	{"V6_TO_V4_PBUF_EXCEPTION_PKTS",	NSS_STATS_TYPE_EXCEPTION},
+	{"V6_TO_V4_PBUF_NO_MATCHING_RULE",	NSS_STATS_TYPE_SPECIAL},
+	{"V6_TO_V4_PBUF_NOT_TCP_OR_UDP",	NSS_STATS_TYPE_SPECIAL},
+	{"V6_TO_V4_RULE_ERR_LOCAL_IPV4",	NSS_STATS_TYPE_ERROR},
+	{"V6_TO_V4_RULE_ERR_REMOTE_IPV4",	NSS_STATS_TYPE_ERROR}
+};
+
+/*
+ * nss_map_t_strings_read()
+ *	Read MAP-T node statistics names.
+ */
+static ssize_t nss_map_t_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_map_t_strings_instance_stats, NSS_MAP_T_STATS_MAX);
+}
+
+/*
+ * nss_map_t_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(map_t);
+
+/*
+ * nss_map_t_strings_dentry_create()
+ *	Create MAP-T statistics strings debug entry.
+ */
+void nss_map_t_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("map_t", &nss_map_t_strings_ops);
+}
diff --git a/qca-nss-drv/nss_map_t_strings.h b/qca-nss-drv/nss_map_t_strings.h
new file mode 100644
index 0000000..acf2cd0
--- /dev/null
+++ b/qca-nss-drv/nss_map_t_strings.h
@@ -0,0 +1,25 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_MAP_T_STRINGS_H
+#define __NSS_MAP_T_STRINGS_H
+
+extern struct nss_stats_info nss_map_t_strings_instance_stats[NSS_MAP_T_STATS_MAX];
+extern void nss_map_t_strings_dentry_create(void);
+
+#endif /* __NSS_MAP_T_STRINGS_H */
diff --git a/qca-nss-drv/nss_match.c b/qca-nss-drv/nss_match.c
new file mode 100644
index 0000000..dcdfa6c
--- /dev/null
+++ b/qca-nss-drv/nss_match.c
@@ -0,0 +1,299 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+/*
+ * nss_match.c
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_match_log.h"
+#include "nss_match_stats.h"
+#include "nss_match_strings.h"
+
+#define NSS_MATCH_TX_TIMEOUT 1000	/* 1 Seconds */
+
+/*
+ * Private data structure for match interface
+ */
+static struct nss_match_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	int32_t response;
+} match_pvt;
+
+/*
+ * nss_get_match_context()
+ */
+struct nss_ctx_instance *nss_match_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.match_handler_id];
+}
+EXPORT_SYMBOL(nss_match_get_context);
+
+/*
+ * nss_match_verify_if_num()
+ */
+static bool nss_match_verify_if_num(uint32_t if_num)
+{
+	if (nss_is_dynamic_interface(if_num) == false) {
+		return false;
+	}
+
+	if (nss_dynamic_interface_get_type(nss_match_get_context(), if_num)
+		!= NSS_DYNAMIC_INTERFACE_TYPE_MATCH) {
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_match_msg_sync_callback
+ *	Callback to handle the completion of NSS to HLOS messages.
+ */
+static void nss_match_msg_sync_callback(void *app_data, struct nss_match_msg *matchm)
+{
+	match_pvt.response = NSS_TX_SUCCESS;
+
+	if (matchm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("Match Error response %d\n", matchm->cm.response);
+		match_pvt.response = NSS_TX_FAILURE;
+	}
+
+	complete(&match_pvt.complete);
+}
+
+/*
+ * nss_match_msg_tx()
+ *	Sends message to NSS.
+ */
+static nss_tx_status_t nss_match_msg_tx(struct nss_ctx_instance *nss_ctx, struct nss_match_msg *matchm)
+{
+	struct nss_cmn_msg *ncm = &matchm->cm;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	/*
+	 * Trace Messages
+	 */
+	nss_match_log_tx_msg(matchm);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!nss_match_verify_if_num(ncm->interface)) {
+		nss_warning("%px: Tx request for non dynamic interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_MATCH_MSG_MAX) {
+		nss_warning("%px: Message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, matchm, sizeof(*matchm), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ * nss_match_handler()
+ *	Handle NSS to HLOS messages for Match node
+ */
+static void nss_match_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_match_msg *nem = (struct nss_match_msg *)ncm;
+
+	nss_match_msg_sync_callback_t cb;
+	void *ctx;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	BUG_ON(!nss_match_verify_if_num(ncm->interface));
+
+	/*
+	 * Trace Messages
+	 */
+	nss_match_log_rx_msg(nem);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (nem->cm.type >= NSS_MATCH_MSG_MAX) {
+		nss_warning("%px: Received invalid message %d for MATCH interface", nss_ctx, nem->cm.type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_match_msg)) {
+		nss_warning("%px: Unexpected message length: %d, on interface: %d",
+				nss_ctx, nss_cmn_get_msg_len(ncm), ncm->interface);
+		return;
+	}
+
+	switch (nem->cm.type) {
+	case NSS_MATCH_STATS_SYNC:
+
+		/*
+		 * Update common node statistics
+		 */
+		nss_match_stats_sync(nss_ctx, nem);
+		nss_match_stats_notify(nss_ctx, nem->cm.interface);
+	}
+
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_match_msg_sync_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	cb(ctx, nem);
+}
+
+/*
+ * nss_match_msg_tx_sync()
+ *	Send a message to match node and wait for the response.
+ */
+nss_tx_status_t nss_match_msg_tx_sync(struct nss_ctx_instance *nss_ctx, struct nss_match_msg *matchm)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+	down(&match_pvt.sem);
+
+	matchm->cm.cb = (nss_ptr_t)nss_match_msg_sync_callback;
+	matchm->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_match_msg_tx(nss_ctx, matchm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_match_msg_tx failed\n", nss_ctx);
+		up(&match_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&match_pvt.complete, msecs_to_jiffies(NSS_MATCH_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: MATCH tx failed due to timeout\n", nss_ctx);
+		match_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = match_pvt.response;
+	up(&match_pvt.sem);
+
+	return status;
+}
+EXPORT_SYMBOL(nss_match_msg_tx_sync);
+
+/*
+ * nss_match_unregister_instance()
+ *	Unregisters match instance.
+ */
+bool nss_match_unregister_instance(int if_num)
+{
+	struct nss_ctx_instance *nss_ctx;
+	uint32_t status;
+
+	nss_ctx = nss_match_get_context();
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_match_verify_if_num(if_num)) {
+		nss_warning("%px: Incorrect interface number: %d", nss_ctx, if_num);
+		return false;
+	}
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+	status = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to unregister handler for interface %d with NSS core\n", nss_ctx, if_num);
+		return false;
+	}
+
+	nss_match_ifnum_delete(if_num);
+
+	return true;
+}
+EXPORT_SYMBOL(nss_match_unregister_instance);
+
+/*
+ * nss_match_register_instance()
+ *	Registers match instance.
+ */
+struct nss_ctx_instance *nss_match_register_instance(int if_num, nss_match_msg_sync_callback_t notify_cb)
+{
+	struct nss_ctx_instance *nss_ctx;
+	uint32_t status;
+
+	nss_ctx = nss_match_get_context();
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_match_verify_if_num(if_num)) {
+		nss_warning("%px: Incorrect interface number: %d", nss_ctx, if_num);
+		return NULL;
+	}
+
+	nss_core_register_handler(nss_ctx, if_num, nss_match_handler, NULL);
+	status = nss_core_register_msg_handler(nss_ctx, if_num, (nss_if_rx_msg_callback_t)notify_cb);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to register handler for interface %d with NSS core\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	if (!nss_match_ifnum_add(if_num)) {
+		nss_warning("%px: Unable to add match inteface : %u\n", nss_ctx, if_num);
+		nss_core_unregister_handler(nss_ctx, if_num);
+		nss_core_unregister_msg_handler(nss_ctx, if_num);
+		return NULL;
+	}
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_match_register_instance);
+
+/*
+ * nss_match_msg_init()
+ *	Initialize match message.
+ */
+void nss_match_msg_init(struct nss_match_msg *nmm, uint16_t if_num, uint32_t type, uint32_t len,
+		nss_match_msg_sync_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&nmm->cm, if_num, type, len, (void*)cb, app_data);
+}
+EXPORT_SYMBOL(nss_match_msg_init);
+
+/*
+ * nss_match_init()
+ * 	Initialize match.
+ */
+void nss_match_init()
+{
+	nss_match_stats_dentry_create();
+	nss_match_strings_dentry_create();
+	sema_init(&match_pvt.sem, 1);
+	init_completion(&match_pvt.complete);
+}
diff --git a/qca-nss-drv/nss_match_log.c b/qca-nss-drv/nss_match_log.c
new file mode 100644
index 0000000..2afdf64
--- /dev/null
+++ b/qca-nss-drv/nss_match_log.c
@@ -0,0 +1,225 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+/*
+ * nss_match_log.c
+ *	NSS match logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_match_log_message_types_str
+ *	Match message strings.
+ */
+static char *nss_match_log_message_types_str[NSS_MATCH_MSG_MAX] __maybe_unused = {
+	"Match no message",
+	"Match profile configure",
+	"Match add VoW rule",
+	"Match add L2 rule",
+	"Match delete VoW rule",
+	"Match delete L2 rule",
+	"Match sync stats"
+};
+
+/*
+ * nss_match_log_error_types_str
+ *	Strings for error types for match messages
+ */
+static char *nss_match_log_error_types_str[NSS_MATCH_ERROR_MAX] __maybe_unused = {
+	"Match success",
+	"Match unknown message",
+	"Match DSCP is not in the range",
+	"Match 802.1p outer is not in the range",
+	"Match 802.1p inner is not in the range",
+	"Match rule ID is not in the range",
+	"Match action type is not in the range",
+	"Match rule ID already exists",
+	"Match rule ID doesn't exists",
+	"Match instance already configured",
+	"Match profile configuration message is invalid",
+	"Match database initialzation failed",
+	"Match table ID is not in the range",
+	"Match error in adding rule",
+	"Match error in deleting rule",
+	"Match error in adding table",
+	"Match error in deleting table",
+	"Match error mask ID is not in the range",
+	"Match error next node interface number is invalid",
+};
+
+/*
+ * nss_match_log_profile_configure_msg()
+ * 	Log NSS match profile configuration message.
+ */
+static void nss_match_log_profile_configure_msg(struct nss_match_msg *nmm)
+{
+	struct nss_match_profile_configure_msg *nmcm __maybe_unused = &nmm->msg.configure_msg;
+	int mask_num, mask_word;
+
+	nss_trace("%px: NSS match configuration message \n"
+			"Match profile type: %u \n"
+			"Match mask flag: %u \n",
+			nmcm,
+			nmcm->profile_type,
+			nmcm->valid_mask_flag);
+
+	for (mask_num = 0; mask_num < NSS_MATCH_MASK_MAX; mask_num++) {
+		nss_trace("Match mask number %d\n", mask_num + 1);
+		for (mask_word = 0; mask_word < NSS_MATCH_MASK_WORDS_MAX; mask_word++) {
+			nss_trace("%x ", nmcm->maskset[mask_num][mask_word]);
+		}
+	}
+}
+
+/*
+ * nss_match_log_vow_rule_msg()
+ * 	Log NSS match VoW rule message.
+ */
+static void nss_match_log_vow_rule_msg(struct nss_match_msg *nmm)
+{
+	struct nss_match_rule_vow_msg *nmvrm __maybe_unused = &nmm->msg.vow_rule;
+	nss_trace("%px: NSS match VoW rule message \n"
+			"Match rule id: %hu \n"
+			"Match mask id: %hu \n"
+			"Match action: action flag = %u, next node = %u, priority = %hu \n"
+			"Match interface number: %u \n"
+			"Match DSCP: %hu \n"
+			"Match outer_8021p: %hu \n"
+			"Match inner_8021p: %hu \n",
+			nmvrm,
+			nmvrm->rule_id,
+			nmvrm->mask_id,
+			nmvrm->action.action_flag, nmvrm->action.forward_ifnum, nmvrm->action.setprio,
+			nmvrm->if_num,
+			nmvrm->dscp,
+			nmvrm->outer_8021p,
+			nmvrm->inner_8021p);
+}
+
+/*
+ * nss_match_log_l2_rule_msg()
+ * 	Log NSS match L2 rule message.
+ */
+static void nss_match_log_l2_rule_msg(struct nss_match_msg *nmm)
+{
+	struct nss_match_rule_l2_msg *nmlrm __maybe_unused = &nmm->msg.l2_rule;
+	nss_trace("%px: NSS match L2 rule message \n"
+			"Match rule id: %hu \n"
+			"Match mask id: %hu \n"
+			"Match action: action flag = %u, next node = %u, priority = %hu \n"
+			"Match interface number: %u \n"
+			"Match destination mac address: %x :%x :%x \n"
+			"Match source mac address: %x :%x :%x \n"
+			"Match ether type: %x \n",
+			nmlrm,
+			nmlrm->rule_id,
+			nmlrm->mask_id,
+			nmlrm->action.action_flag, nmlrm->action.forward_ifnum, nmlrm->action.setprio,
+			nmlrm->if_num,
+			nmlrm->dmac[0], nmlrm->dmac[1], nmlrm->dmac[2],
+			nmlrm->smac[0], nmlrm->smac[1], nmlrm->smac[2],
+			nmlrm->ethertype);
+
+}
+
+/*
+ * nss_clmap_log_verbose()
+ *	Log message contents.
+ */
+static void nss_match_log_verbose(struct nss_match_msg *nmm)
+{
+	switch (nmm->cm.type) {
+	case NSS_MATCH_TABLE_CONFIGURE_MSG:
+		nss_match_log_profile_configure_msg(nmm);
+		break;
+
+	case NSS_MATCH_ADD_VOW_RULE_MSG:
+		nss_match_log_vow_rule_msg(nmm);
+		break;
+
+	case NSS_MATCH_ADD_L2_RULE_MSG:
+		nss_match_log_l2_rule_msg(nmm);
+		break;
+
+	case NSS_MATCH_DELETE_VOW_RULE_MSG:
+		nss_match_log_vow_rule_msg(nmm);
+		break;
+
+	case NSS_MATCH_DELETE_L2_RULE_MSG:
+		nss_match_log_l2_rule_msg(nmm);
+		break;
+
+	case NSS_MATCH_STATS_SYNC:
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", nmm);
+		break;
+	}
+}
+
+/*
+ * nss_match_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_match_log_tx_msg(struct nss_match_msg *nmm)
+{
+	if (nmm->cm.type >= NSS_MATCH_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", nmm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nmm, nmm->cm.type, nss_match_log_message_types_str[nmm->cm.type]);
+	nss_match_log_verbose(nmm);
+}
+
+/*
+ * nss_match_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_match_log_rx_msg(struct nss_match_msg *nmm)
+{
+	if (nmm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", nmm);
+		return;
+	}
+
+	if (nmm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nmm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nmm, nmm->cm.type,
+			nss_match_log_message_types_str[nmm->cm.type],
+			nmm->cm.response, nss_cmn_response_str[nmm->cm.response]);
+		goto verbose;
+	}
+
+	if (nmm->cm.error >= NSS_MATCH_ERROR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			nmm, nmm->cm.type, nss_match_log_message_types_str[nmm->cm.type],
+			nmm->cm.response, nss_cmn_response_str[nmm->cm.response],
+			nmm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		nmm, nmm->cm.type, nss_match_log_message_types_str[nmm->cm.type],
+		nmm->cm.response, nss_cmn_response_str[nmm->cm.response],
+		nmm->cm.error, nss_match_log_error_types_str[nmm->cm.error]);
+
+verbose:
+	nss_match_log_verbose(nmm);
+}
diff --git a/qca-nss-drv/nss_match_log.h b/qca-nss-drv/nss_match_log.h
new file mode 100644
index 0000000..df5b8a9
--- /dev/null
+++ b/qca-nss-drv/nss_match_log.h
@@ -0,0 +1,39 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_MATCH_LOG_H__
+#define __NSS_MATCH_LOG_H__
+
+/**
+ * nss_match_log.h
+ *	NSS match Log Header File.
+ */
+
+/*
+ * nss_match_log_tx_msg
+ *	Logs a match message that is sent to the NSS firmware.
+ */
+void nss_match_log_tx_msg(struct nss_match_msg *nmm);
+
+/*
+ * nss_match_log_rx_msg
+ *	Logs a match message that is received from the NSS firmware.
+ */
+void nss_match_log_rx_msg(struct nss_match_msg *nmm);
+
+#endif /* __NSS_MATCH_LOG_H__ */
diff --git a/qca-nss-drv/nss_match_stats.c b/qca-nss-drv/nss_match_stats.c
new file mode 100644
index 0000000..2978234
--- /dev/null
+++ b/qca-nss-drv/nss_match_stats.c
@@ -0,0 +1,245 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+/*
+ * nss_match_stats.c
+ */
+#include "nss_core.h"
+#include "nss_stats.h"
+#include <nss_match.h>
+#include "nss_match_stats.h"
+#include "nss_match_strings.h"
+
+#define NSS_MATCH_STATS_SIZE_PER_IF (NSS_STATS_MAX_STR_LENGTH * NSS_STATS_NODE_MAX)
+                                        /* Total number of statistics per match interface. */
+
+int match_ifnum[NSS_MATCH_INSTANCE_MAX] = {0};
+uint64_t nss_match_stats[NSS_MATCH_INSTANCE_MAX][NSS_MATCH_STATS_MAX];
+static DEFINE_SPINLOCK(nss_match_stats_lock);
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_match_stats_notifier);
+
+/*
+ * nss_match_stats_read()
+ *	Read match node statiistics.
+ */
+static ssize_t nss_match_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	/*
+	 * Max output lines = #stats +
+	 * few blank lines for banner printing + Number of Extra outputlines
+	 * for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_MATCH_STATS_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines * NSS_MATCH_INSTANCE_MAX;
+	ssize_t bytes_read = 0;
+	size_t size_wr = 0;
+	uint32_t if_num;
+	int index;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "match stats", NSS_STATS_SINGLE_CORE);
+
+	/*
+	 * Common node stats for each match dynamic interface.
+	 */
+	for (index = 0; index < NSS_MATCH_INSTANCE_MAX; index++) {
+
+		spin_lock_bh(&nss_match_stats_lock);
+		if_num = match_ifnum[index];
+		spin_unlock_bh(&nss_match_stats_lock);
+
+		if (if_num) {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\nMatch node if_num:%03u", if_num);
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n ---------------------- \n");
+			size_wr += nss_stats_print("match", NULL, NSS_STATS_SINGLE_INSTANCE, nss_match_strings_stats,
+						nss_match_stats[index], NSS_MATCH_STATS_MAX, lbuf, size_wr, size_al);
+			continue;
+		}
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	return bytes_read;
+}
+
+
+/*
+ * nss_match_stats_sync()
+ *	Update match common node statistics.
+ */
+void nss_match_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_match_msg *nmm)
+{
+	struct nss_match_stats_sync *ndccs = &nmm->msg.stats;
+	uint64_t *ctx_stats;
+	uint32_t *msg_stats;
+	uint32_t if_num;
+	uint16_t i = 0;
+	int index;
+
+	for (index = 0; index < NSS_MATCH_INSTANCE_MAX; index++) {
+		spin_lock_bh(&nss_match_stats_lock);
+		if_num = match_ifnum[index];
+		spin_unlock_bh(&nss_match_stats_lock);
+
+		if (if_num == nmm->cm.interface) {
+			break;
+		}
+	}
+
+	if (index == NSS_MATCH_INSTANCE_MAX) {
+		nss_warning("Invalid Match index\n");
+		return;
+	}
+
+	spin_lock_bh(&nss_match_stats_lock);
+	msg_stats = (uint32_t *)ndccs;
+	ctx_stats = nss_match_stats[index];
+
+	for (i = 0; i < NSS_MATCH_STATS_MAX; i++, ctx_stats++, msg_stats++) {
+		*ctx_stats += *msg_stats;
+	}
+
+	spin_unlock_bh(&nss_match_stats_lock);
+}
+
+/*
+ * nss_match_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(match)
+
+/*
+ * nss_match_ifnum_add()
+ *	Add match node interface ID.
+ */
+bool nss_match_ifnum_add(int if_num)
+{
+	int index = 0;
+
+	spin_lock_bh(&nss_match_stats_lock);
+
+	for (index = 0; index < NSS_MATCH_INSTANCE_MAX; index++) {
+		if (match_ifnum[index]) {
+			continue;
+		}
+
+		match_ifnum[index] = if_num;
+
+		spin_unlock_bh(&nss_match_stats_lock);
+		return true;
+	}
+
+	spin_unlock_bh(&nss_match_stats_lock);
+	return false;
+}
+
+/*
+ * nss_match_ifnum_delete()
+ *	Delete match node interface ID.
+ */
+bool nss_match_ifnum_delete(int if_num)
+{
+	int index = 0;
+
+	spin_lock_bh(&nss_match_stats_lock);
+
+	for (index = 0; index < NSS_MATCH_INSTANCE_MAX; index++) {
+		if (match_ifnum[index] != if_num) {
+			continue;
+		}
+
+		match_ifnum[index] = 0;
+
+		spin_unlock_bh(&nss_match_stats_lock);
+		return true;
+	}
+
+	spin_unlock_bh(&nss_match_stats_lock);
+	return false;
+}
+
+/*
+ * nss_match_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_match_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_match_stats_notification match_stats;
+	uint32_t interface;
+	int index;
+
+	match_stats.core_id = nss_ctx->id;
+	match_stats.if_num = if_num;
+
+	for (index = 0; index < NSS_MATCH_INSTANCE_MAX; index++) {
+		spin_lock_bh(&nss_match_stats_lock);
+		interface = match_ifnum[index];
+		spin_unlock_bh(&nss_match_stats_lock);
+
+		if (interface == if_num) {
+			break;
+		}
+	}
+
+	if (index == NSS_MATCH_INSTANCE_MAX) {
+		nss_warning("Invalid Match index\n");
+		return;
+	}
+
+	spin_lock_bh(&nss_match_stats_lock);
+	memcpy(match_stats.stats_ctx, nss_match_stats[index], sizeof(match_stats.stats_ctx));
+	spin_unlock_bh(&nss_match_stats_lock);
+	atomic_notifier_call_chain(&nss_match_stats_notifier, NSS_STATS_EVENT_NOTIFY, &match_stats);
+}
+
+/*
+ * nss_match_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_match_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_match_stats_notifier, nb);
+}
+
+/*
+ * nss_match_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_match_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_match_stats_notifier, nb);
+}
+
+/*
+ * nss_match_stats_dentry_create()
+ *	Create match statistics debug entry.
+ */
+void nss_match_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("match", &nss_match_stats_ops);
+}
diff --git a/qca-nss-drv/nss_match_stats.h b/qca-nss-drv/nss_match_stats.h
new file mode 100644
index 0000000..3cbc746
--- /dev/null
+++ b/qca-nss-drv/nss_match_stats.h
@@ -0,0 +1,81 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#ifndef __NSS_MATCH_STATS_H__
+#define __NSS_MATCH_STATS_H__
+
+/**
+ * nss_match_stats_types
+ *	Match statistics types.
+ */
+enum nss_match_stats_types {
+	NSS_MATCH_STATS_HIT_COUNT_0 = NSS_STATS_NODE_MAX,
+					/**< Hit count of rule ID 1. */
+	NSS_MATCH_STATS_HIT_COUNT_1,	/**< Hit count of rule ID 2. */
+	NSS_MATCH_STATS_HIT_COUNT_2,	/**< Hit count of rule ID 3. */
+	NSS_MATCH_STATS_HIT_COUNT_3,	/**< Hit count of rule ID 4. */
+	NSS_MATCH_STATS_HIT_COUNT_4,	/**< Hit count of rule ID 5. */
+	NSS_MATCH_STATS_HIT_COUNT_5,	/**< Hit count of rule ID 6. */
+	NSS_MATCH_STATS_HIT_COUNT_6,	/**< Hit count of rule ID 7. */
+	NSS_MATCH_STATS_HIT_COUNT_7,	/**< Hit count of rule ID 8. */
+	NSS_MATCH_STATS_HIT_COUNT_8,	/**< Hit count of rule ID 9. */
+	NSS_MATCH_STATS_HIT_COUNT_9,	/**< Hit count of rule ID 10. */
+	NSS_MATCH_STATS_HIT_COUNT_10,	/**< Hit count of rule ID 11. */
+	NSS_MATCH_STATS_HIT_COUNT_11,	/**< Hit count of rule ID 12. */
+	NSS_MATCH_STATS_HIT_COUNT_12,	/**< Hit count of rule ID 13. */
+	NSS_MATCH_STATS_HIT_COUNT_13,	/**< Hit count of rule ID 14. */
+	NSS_MATCH_STATS_HIT_COUNT_14,	/**< Hit count of rule ID 15. */
+	NSS_MATCH_STATS_HIT_COUNT_15,	/**< Hit count of rule ID 16. */
+	NSS_MATCH_STATS_HIT_COUNT_16,	/**< Hit count of rule ID 17. */
+	NSS_MATCH_STATS_HIT_COUNT_17,	/**< Hit count of rule ID 18. */
+	NSS_MATCH_STATS_HIT_COUNT_18,	/**< Hit count of rule ID 19. */
+	NSS_MATCH_STATS_HIT_COUNT_19,	/**< Hit count of rule ID 20. */
+	NSS_MATCH_STATS_HIT_COUNT_20,	/**< Hit count of rule ID 21. */
+	NSS_MATCH_STATS_HIT_COUNT_21,	/**< Hit count of rule ID 22. */
+	NSS_MATCH_STATS_HIT_COUNT_22,	/**< Hit count of rule ID 23. */
+	NSS_MATCH_STATS_HIT_COUNT_23,	/**< Hit count of rule ID 24. */
+	NSS_MATCH_STATS_HIT_COUNT_24,	/**< Hit count of rule ID 25. */
+	NSS_MATCH_STATS_HIT_COUNT_25,	/**< Hit count of rule ID 26. */
+	NSS_MATCH_STATS_HIT_COUNT_26,	/**< Hit count of rule ID 27. */
+	NSS_MATCH_STATS_HIT_COUNT_27,	/**< Hit count of rule ID 28. */
+	NSS_MATCH_STATS_HIT_COUNT_28,	/**< Hit count of rule ID 29. */
+	NSS_MATCH_STATS_HIT_COUNT_29,	/**< Hit count of rule ID 30. */
+	NSS_MATCH_STATS_HIT_COUNT_30,	/**< Hit count of rule ID 31. */
+	NSS_MATCH_STATS_HIT_COUNT_31,	/**< Hit count of rule ID 32. */
+	NSS_MATCH_STATS_MAX,		/**< Maximum statistics type. */
+};
+
+/**
+ * nss_match_stats_notification
+ *	Match transmission statistics structure.
+ */
+struct nss_match_stats_notification {
+	uint64_t stats_ctx[NSS_MATCH_STATS_MAX];	/**< Context transmission statistics. */
+	uint32_t core_id;				/**< Core ID. */
+	uint32_t if_num;				/**< Interface number. */
+};
+
+extern bool nss_match_ifnum_add(int if_num);
+extern bool nss_match_ifnum_delete(int if_num);
+extern void nss_match_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_match_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_match_msg *nmm);
+extern void nss_match_stats_dentry_create(void);
+extern int nss_match_stats_unregister_notifier(struct notifier_block *nb);
+extern int nss_match_stats_register_notifier(struct notifier_block *nb);
+
+#endif /* __NSS_MATCH_STATS_H__ */
diff --git a/qca-nss-drv/nss_match_strings.c b/qca-nss-drv/nss_match_strings.c
new file mode 100644
index 0000000..67d8451
--- /dev/null
+++ b/qca-nss-drv/nss_match_strings.c
@@ -0,0 +1,92 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_match_strings.h"
+
+/*
+ * nss_match_strings_stats
+ *	match statistics strings.
+ */
+struct nss_stats_info nss_match_strings_stats[NSS_MATCH_STATS_MAX] = {
+	{"rx_pkts",		NSS_STATS_TYPE_COMMON},
+	{"rx_byts",		NSS_STATS_TYPE_COMMON},
+	{"tx_pkts",		NSS_STATS_TYPE_COMMON},
+	{"tx_byts",		NSS_STATS_TYPE_COMMON},
+	{"rx_queue[0]_drops",	NSS_STATS_TYPE_DROP},
+	{"rx_queue[1]_drops",	NSS_STATS_TYPE_DROP},
+	{"rx_queue[2]_drops",	NSS_STATS_TYPE_DROP},
+	{"rx_queue[3]_drops",	NSS_STATS_TYPE_DROP},
+	{"hit_count[0]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[1]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[2]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[3]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[4]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[5]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[6]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[7]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[8]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[9]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[10]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[11]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[12]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[13]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[14]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[15]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[16]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[17]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[18]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[19]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[20]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[21]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[22]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[23]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[24]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[25]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[26]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[27]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[28]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[29]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[30]",	NSS_STATS_TYPE_SPECIAL},
+	{"hit_count[31]",	NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_match_stats_strings_read()
+ *	Read match statistics names
+ */
+static ssize_t nss_match_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_match_strings_stats, NSS_MATCH_STATS_MAX);
+}
+
+/*
+ * nss_match_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(match);
+
+/*
+ * nss_match_strings_dentry_create()
+ *	Create match statistics strings debug entry.
+ */
+void nss_match_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("match", &nss_match_strings_ops);
+}
diff --git a/qca-nss-drv/nss_match_strings.h b/qca-nss-drv/nss_match_strings.h
new file mode 100644
index 0000000..9eb9f62
--- /dev/null
+++ b/qca-nss-drv/nss_match_strings.h
@@ -0,0 +1,27 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#ifndef __NSS_MATCH_STRINGS_H
+#define __NSS_MATCH_STRINGS_H
+
+#include "nss_match_stats.h"
+
+extern struct nss_stats_info nss_match_strings_stats[NSS_MATCH_STATS_MAX];
+extern void nss_match_strings_dentry_create(void);
+
+#endif /* __NSS_MATCH_STRINGS_H */
diff --git a/qca-nss-drv/nss_meminfo.c b/qca-nss-drv/nss_meminfo.c
new file mode 100644
index 0000000..707c87a
--- /dev/null
+++ b/qca-nss-drv/nss_meminfo.c
@@ -0,0 +1,805 @@
+/*
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * nss_meminfo.c
+ *	NSS meminfo subsystem
+ */
+
+#include <linux/seq_file_net.h>
+#include "nss_tx_rx_common.h"
+#include "nss_core.h"
+#include "nss_arch.h"
+#include "nss_meminfo.h"
+
+/*
+ * Store user configuration
+ */
+static char nss_meminfo_user_config[NSS_MEMINFO_USER_CONFIG_MAXLEN];
+module_param_string(meminfo_user_config, nss_meminfo_user_config,
+		    NSS_MEMINFO_USER_CONFIG_MAXLEN, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
+MODULE_PARM_DESC(nss_meminfo_user_config, "meminfo user configuration");
+
+static bool nss_meminfo_debugfs_exist;
+
+/*
+ * Name table of memory type presented to user.
+ */
+char *nss_meminfo_memtype_table[NSS_MEMINFO_MEMTYPE_MAX] = {"IMEM", "SDRAM", "UTCM_SHARED"};
+
+/*
+ * nss_meminfo_alloc_sdram()
+ *	Allocate a SDRAM block.
+ */
+static void *nss_meminfo_alloc_sdram(struct nss_ctx_instance *nss_ctx, uint32_t size)
+{
+	void *addr = 0;
+
+	/*
+	 * kmalloc() return cache line aligned buffer.
+	 */
+	addr = kmalloc(size, GFP_KERNEL | __GFP_ZERO);
+	if (!addr)
+		nss_info_always("%px: failed to alloc a sdram block of size %u\n", nss_ctx, size);
+
+	kmemleak_not_leak((void *)addr);
+	return addr;
+}
+
+/*
+ * nss_meminfo_free_sdram()
+ *	Free SDRAM memory.
+ */
+static inline void nss_meminfo_free_sdram(struct nss_ctx_instance *nss_ctx, uint32_t dma_addr,
+						void *kern_addr, uint32_t size)
+{
+	/*
+	 * Unmap it since every SDRAM memory had been mapped.
+	 */
+	dma_unmap_single(nss_ctx->dev, dma_addr, size, DMA_FROM_DEVICE);
+	kfree(kern_addr);
+}
+
+/*
+ * nss_meminfo_alloc_imem()
+ *	Allocate an IMEM block in a sequential way.
+ */
+static uint32_t nss_meminfo_alloc_imem(struct nss_ctx_instance *nss_ctx, uint32_t size, int alignment)
+{
+	struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
+	uint32_t new_tail;
+	uint32_t addr = 0;
+	int mask;
+
+	mask = alignment - 1;
+
+	/*
+	 * Alignment has to be a power of 2.
+	 */
+	nss_assert(!(alignment & mask));
+
+	new_tail = mem_ctx->imem_tail;
+
+	/*
+	 * Align up the address if it not aligned.
+	 */
+	if (new_tail & mask)
+		new_tail = (new_tail + mask) & ~mask;
+
+	if (size > (mem_ctx->imem_end - new_tail)) {
+		nss_info_always("%px: failed to alloc an IMEM block of size %u\n", nss_ctx, size);
+		return addr;
+	}
+
+	addr = new_tail;
+	mem_ctx->imem_tail = new_tail + size;
+
+	return addr;
+}
+
+/*
+ * nss_meminfo_free_imem()
+ *	Free an IMEM block. Ignore the padding bytes for alignment requirement.
+ */
+static void nss_meminfo_free_imem(struct nss_ctx_instance *nss_ctx, uint32_t addr, uint32_t size)
+{
+	struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
+	mem_ctx->imem_tail -= size;
+}
+
+/*
+ * nss_meminfo_alloc_utcm_shared()
+ *	Allocate an UTCM_SHARED block in a sequential way.
+ */
+static uint32_t nss_meminfo_alloc_utcm_shared(struct nss_ctx_instance *nss_ctx, uint32_t size, int alignment)
+{
+	struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
+	uint32_t new_tail;
+	uint32_t addr = 0;
+	int mask;
+
+	mask = alignment - 1;
+
+	/*
+	 * Alignment has to be a power of 2.
+	 */
+	nss_assert(!(alignment & mask));
+
+	new_tail = mem_ctx->utcm_shared_tail;
+
+	/*
+	 * Align up the address if it not aligned.
+	 */
+	if (new_tail & mask)
+		new_tail = (new_tail + mask) & ~mask;
+
+	if (size > (mem_ctx->utcm_shared_end - new_tail)) {
+		nss_info_always("%px: failed to alloc an UTCM_SHARED block of size %u\n", nss_ctx, size);
+		return addr;
+	}
+
+	addr = new_tail;
+	mem_ctx->utcm_shared_tail = new_tail + size;
+
+	return addr;
+}
+
+/*
+ * nss_meminfo_free_utcm_shared()
+ *	Free an UTCM_SHARED block. Ignore the padding bytes for alignment requirement.
+ */
+static void nss_meminfo_free_utcm_shared(struct nss_ctx_instance *nss_ctx, uint32_t addr, uint32_t size)
+{
+	struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
+	mem_ctx->utcm_shared_tail -= size;
+}
+
+/*
+ * nss_meminfo_if_user_overwrite()
+ *	Return user configured memory type. Otherwise, return -1.
+ */
+static int nss_meminfo_if_user_overwrite(struct nss_ctx_instance *nss_ctx, const char *name)
+{
+	char *user_config;
+	char **mtype_table;
+	char needle[NSS_MEMINFO_BLOCK_NAME_MAXLEN + 6];
+	char user_choice[NSS_MEMINFO_MEMTYPE_NAME_MAXLEN];
+	int i;
+	char *p;
+
+	user_config = nss_meminfo_user_config;
+	mtype_table = nss_meminfo_memtype_table;
+
+	snprintf(needle, sizeof(needle), "<%1d, %s, ", nss_ctx->id, name);
+
+	p = strstr(user_config, needle);
+	if (!p)
+		return -1;
+
+	p += strlen(needle);
+
+	for (i = 0; i < NSS_MEMINFO_MEMTYPE_NAME_MAXLEN - 1; i++) {
+		/*
+		 * Each user config is like <core_id, object_name, memory_type>,
+		 * it starts with '<' and ends with '>'.
+		 */
+		if (*p == '>' || *p == '\0')
+			break;
+		user_choice[i] = *p;
+		p++;
+	}
+
+	user_choice[i] = '\0';
+
+	for (i = 0; i < NSS_MEMINFO_MEMTYPE_MAX; i++)
+		if (!strcmp(mtype_table[i], user_choice))
+			return i;
+
+	return -1;
+}
+
+/*
+ * nss_meminfo_free_block_lists()
+ *	Free block node and memory associated with each each memory object.
+ */
+static void nss_meminfo_free_block_lists(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_meminfo_ctx *mem_ctx;
+	struct nss_meminfo_block_list *l;
+	int i;
+
+	mem_ctx = &nss_ctx->meminfo_ctx;
+	for (i = 0; i < NSS_MEMINFO_MEMTYPE_MAX; i++) {
+		struct nss_meminfo_block *b;
+		l = &mem_ctx->block_lists[i];
+		b = l->head;
+		while (b) {
+			struct nss_meminfo_block *tmp;
+			/*
+			 * Free IMEM/SDRAM/UTCM_SHARED memory.
+			 */
+			switch (i) {
+			case NSS_MEMINFO_MEMTYPE_IMEM:
+				nss_meminfo_free_imem(nss_ctx, b->dma_addr, b->size);
+				break;
+			case NSS_MEMINFO_MEMTYPE_SDRAM:
+				nss_meminfo_free_sdram(nss_ctx, b->dma_addr, b->kern_addr, b->size);
+				break;
+			case NSS_MEMINFO_MEMTYPE_UTCM_SHARED:
+				nss_meminfo_free_utcm_shared(nss_ctx, b->dma_addr, b->size);
+				break;
+			}
+
+			/*
+			 * Free the struct nss_meminfo_block itself.
+			 */
+			tmp = b;
+			b = b->next;
+			kfree(tmp);
+		}
+	}
+}
+
+/*
+ * nss_meminfo_init_block_lists()
+ *	Initialize block lists and allocate memory for each block.
+ */
+static bool nss_meminfo_init_block_lists(struct nss_ctx_instance *nss_ctx)
+{
+	/*
+	 * There is no corresponding mapped address in kernel for UTCM_SHARED.
+	 * UTCM_SHARED access from kernel is not allowed. Mem Objects requesting
+	 * UTCM_SHARED are not expected to use any kernel mapped address.
+	 * Was for UTCM_SHARED, but move to here as default especially for KW scan.
+	 * Thus, NSS_MEMINFO_POISON is the default value for non-mappable memory request.
+	 */
+	void *kern_addr = (void *)NSS_MEMINFO_POISON;
+	uint32_t dma_addr = 0;
+	struct nss_meminfo_ctx *mem_ctx;
+	struct nss_meminfo_block_list *l;
+	struct nss_meminfo_request *r;
+	struct nss_meminfo_map *map;
+	int mtype;
+	int i;
+
+	mem_ctx = &nss_ctx->meminfo_ctx;
+
+	/*
+	 * Fill memory type for each block list.
+	 */
+	for (i = 0; i < NSS_MEMINFO_MEMTYPE_MAX; i++)
+		mem_ctx->block_lists[i].memtype = i;
+
+	map = &mem_ctx->meminfo_map;
+
+	/*
+	 * Loop through all meminfo requests by checking the per-request magic.
+	 */
+	for (r = map->requests; r->magic == NSS_MEMINFO_REQUEST_MAGIC; r++) {
+		struct nss_meminfo_block *b = (struct nss_meminfo_block *)
+						kmalloc(sizeof(struct nss_meminfo_block), GFP_KERNEL);
+		if (!b) {
+			nss_info_always("%px: failed to allocate meminfo block\n", nss_ctx);
+			goto cleanup;
+		}
+
+		b->index = map->num_requests++;
+		b->size = r->size;
+
+		/*
+		 * Look up the user-defined memory type.
+		 * Return user-defined memory type if exists. Otherwise, return -1.
+		 */
+		mtype = nss_meminfo_if_user_overwrite(nss_ctx, r->name);
+		if (mtype == -1)
+			mtype = r->memtype_default;
+		r->memtype_user = mtype;
+
+		switch (mtype) {
+		case NSS_MEMINFO_MEMTYPE_IMEM:
+			/*
+			 * For SOC's where TCM is not present
+			 */
+			if (!nss_ctx->vphys) {
+				nss_info_always("%px:IMEM requested but TCM not defined "
+								"for this SOC\n", nss_ctx);
+				goto cleanup;
+			}
+
+			/*
+			 * Return SoC real address for IMEM as DMA address.
+			 */
+			dma_addr = nss_meminfo_alloc_imem(nss_ctx, r->size, r->alignment);
+			if (!dma_addr) {
+				nss_info_always("%px: failed to alloc IMEM block\n", nss_ctx);
+				goto cleanup;
+			}
+
+			/*
+			 * Calulate offset to the kernel address (vmap) where the
+			 * whole IMEM is mapped onto instead of calling ioremap().
+			 */
+			kern_addr = nss_ctx->vmap + dma_addr - nss_ctx->vphys;
+			break;
+		case NSS_MEMINFO_MEMTYPE_SDRAM:
+			kern_addr = nss_meminfo_alloc_sdram(nss_ctx, r->size);
+			if (!kern_addr) {
+				nss_info_always("%px: failed to alloc SDRAM block\n", nss_ctx);
+				goto cleanup;
+			}
+
+			dma_addr = dma_map_single(nss_ctx->dev, kern_addr, r->size, DMA_TO_DEVICE);
+			if (unlikely(dma_mapping_error(nss_ctx->dev, dma_addr))) {
+				nss_info_always("%px: failed to map SDRAM block\n", nss_ctx);
+				goto cleanup;
+			}
+			break;
+		case NSS_MEMINFO_MEMTYPE_UTCM_SHARED:
+			/*
+			 * Return SoC real address for UTCM_SHARED as DMA address.
+			 */
+			dma_addr = nss_meminfo_alloc_utcm_shared(nss_ctx, r->size, r->alignment);
+			if (!dma_addr) {
+				nss_info_always("%px: failed to alloc UTCM_SHARED block\n", nss_ctx);
+				goto cleanup;
+			}
+			break;
+		case NSS_MEMINFO_MEMTYPE_INFO:
+			/*
+			 * if FW request heap_ddr_size, fill it in from DTS values.
+			 */
+			if (!strcmp(r->name, "heap_ddr_size")) {
+				struct nss_mmu_ddr_info coreinfo;
+				r->size = nss_core_ddr_info(&coreinfo);
+
+				/*
+				 * split memory among the number of cores
+				 */
+				r->size /= coreinfo.num_active_cores;
+				dma_addr = coreinfo.start_address + nss_ctx->id * r->size;
+				nss_info_always("%px: NSS core %d DDR from %x to %x\n", nss_ctx,
+						nss_ctx->id, dma_addr, dma_addr + r->size);
+			}
+			break;
+		default:
+			nss_info_always("%px: %d unsupported memory type\n", nss_ctx, mtype);
+			goto cleanup;
+		}
+
+		/*
+		 * Update the request with DMA address for the memory that only be used by FW.
+		 */
+		r->addr = dma_addr;
+
+		/*
+		 * nss_if_mem_map settings
+		 */
+		if (!strcmp(r->name, "nss_if_mem_map_inst")) {
+			BUG_ON(mtype == NSS_MEMINFO_MEMTYPE_UTCM_SHARED);
+			mem_ctx->if_map_memtype = mtype;
+			mem_ctx->if_map_dma = dma_addr;
+			mem_ctx->if_map = (struct nss_if_mem_map *)kern_addr;
+		}
+
+		if (!strcmp(r->name, "debug_boot_log_desc")) {
+			BUG_ON(mtype == NSS_MEMINFO_MEMTYPE_UTCM_SHARED);
+			mem_ctx->logbuffer_memtype = mtype;
+			mem_ctx->logbuffer_dma = dma_addr;
+			mem_ctx->logbuffer = (struct nss_log_descriptor *)kern_addr;
+		}
+
+		if (!strcmp(r->name, "c2c_descs_if_mem_map")) {
+			mem_ctx->c2c_start_memtype = mtype;
+			mem_ctx->c2c_start_dma = dma_addr;
+		}
+
+		if (strcmp(r->name, "profile_dma_ctrl") == 0) {
+			mem_ctx->sdma_ctrl = kern_addr;
+		nss_info_always("%px: set sdma %px\n", nss_ctx, kern_addr);
+		}
+
+		/*
+		 * Flush the updated meminfo request.
+		 */
+		NSS_CORE_DMA_CACHE_MAINT(r, sizeof(struct nss_meminfo_request), DMA_TO_DEVICE);
+		NSS_CORE_DSB();
+
+		/*
+		 * Update the list
+		 */
+		l = &mem_ctx->block_lists[mtype];
+		l->num_blks++;
+		l->total_size += r->size;
+
+		b->next = l->head;
+		l->head = b;
+	}
+
+	/*
+	 * Verify memory map end magic
+	 */
+	if (*((uint16_t *)r) != NSS_MEMINFO_MAP_END_MAGIC)
+		goto cleanup;
+
+	return true;
+
+cleanup:
+	nss_meminfo_free_block_lists(nss_ctx);
+	return false;
+}
+
+/*
+ * nss_meminfo_allocate_n2h_h2n_rings()
+ *	Allocate N2H/H2N rings.
+ */
+static bool nss_meminfo_allocate_n2h_h2n_rings(struct nss_ctx_instance *nss_ctx,
+						struct nss_meminfo_n2h_h2n_info *info)
+{
+	switch (info->memtype) {
+	case NSS_MEMINFO_MEMTYPE_SDRAM:
+		info->kern_addr = nss_meminfo_alloc_sdram(nss_ctx, info->total_size);
+		if (!info->kern_addr)
+			return false;
+
+		info->dma_addr = dma_map_single(nss_ctx->dev, (void *)info->kern_addr,
+						info->total_size, DMA_TO_DEVICE);
+		if (unlikely(dma_mapping_error(nss_ctx->dev, info->dma_addr))) {
+			kfree((void *)info->kern_addr);
+			return false;
+		}
+		break;
+	case NSS_MEMINFO_MEMTYPE_IMEM:
+		/*
+		 * For SOC's where TCM is not present
+		 */
+		if (!nss_ctx->vphys) {
+			nss_info_always("%px:IMEM requested but TCM not defined "
+							"for this SOC\n", nss_ctx);
+			return false;
+		}
+
+		info->dma_addr = nss_meminfo_alloc_imem(nss_ctx, info->total_size, L1_CACHE_BYTES);
+		if (!info->dma_addr)
+			return false;
+
+		info->kern_addr = nss_ctx->vmap + info->dma_addr - nss_ctx->vphys;
+		break;
+	default:
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_meminfo_configure_n2h_h2n_rings()
+ *	Configure N2H/H2N rings and if_map.
+ */
+static bool nss_meminfo_configure_n2h_h2n_rings(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
+	struct nss_meminfo_n2h_h2n_info *h2n_info;
+	struct nss_meminfo_n2h_h2n_info *n2h_info;
+	struct nss_if_mem_map *if_map;
+	int i;
+	int mtype;
+
+	h2n_info = &mem_ctx->h2n_info;
+	n2h_info = &mem_ctx->n2h_info;
+
+	/*
+	 * Check memory type. SDRAM is the default option.
+	 */
+	mtype = nss_meminfo_if_user_overwrite(nss_ctx, "h2n_rings");
+	if (mtype == -1)
+		mtype = NSS_MEMINFO_MEMTYPE_SDRAM;
+
+	h2n_info->memtype = mtype;
+
+	mtype = nss_meminfo_if_user_overwrite(nss_ctx, "n2h_rings");
+	if (mtype == -1)
+		mtype = NSS_MEMINFO_MEMTYPE_SDRAM;
+
+	n2h_info->memtype = mtype;
+
+	n2h_info->total_size = sizeof(struct n2h_descriptor) * NSS_N2H_RING_COUNT * (NSS_RING_SIZE + 2);
+	h2n_info->total_size = sizeof(struct h2n_descriptor) * NSS_H2N_RING_COUNT * (NSS_RING_SIZE + 2);
+
+	/*
+	 * N2H ring allocations
+	 */
+	if (!(nss_meminfo_allocate_n2h_h2n_rings(nss_ctx, n2h_info))) {
+		nss_info_always("%px: failed to allocate/map n2h rings\n", nss_ctx);
+		return false;
+	}
+
+	/*
+	 * H2N ring allocations
+	 */
+	if (!(nss_meminfo_allocate_n2h_h2n_rings(nss_ctx, h2n_info))) {
+		nss_info_always("%px: failed to allocate/map h2n_rings\n", nss_ctx);
+		goto cleanup;
+	}
+
+	/*
+	 * Returning true allows to execute firmware bin
+	 */
+	if (!mem_ctx->if_map) {
+		return true;
+	}
+
+	/*
+	 * Bring a fresh copy of if_map from memory in order to read it correctly.
+	 */
+	if_map = mem_ctx->if_map;
+	NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_FROM_DEVICE);
+	NSS_CORE_DSB();
+
+	if_map->n2h_rings = NSS_N2H_RING_COUNT;
+	if_map->h2n_rings = NSS_H2N_RING_COUNT;
+
+	/*
+	 * N2H ring settings
+	 */
+	for (i = 0; i < NSS_N2H_RING_COUNT; i++) {
+		struct hlos_n2h_desc_ring *n2h_desc_ring = &nss_ctx->n2h_desc_ring[i];
+		n2h_desc_ring->desc_ring.desc = (struct n2h_descriptor *)(n2h_info->kern_addr + i * sizeof(struct n2h_descriptor) * (NSS_RING_SIZE + 2));
+		n2h_desc_ring->desc_ring.size = NSS_RING_SIZE;
+		n2h_desc_ring->hlos_index = if_map->n2h_hlos_index[i];
+
+		if_map->n2h_desc_if[i].size = NSS_RING_SIZE;
+		if_map->n2h_desc_if[i].desc_addr = n2h_info->dma_addr + i * sizeof(struct n2h_descriptor) * (NSS_RING_SIZE + 2);
+		nss_info("%px: N2H ring %d, size %d, addr = %x\n", nss_ctx, i, if_map->n2h_desc_if[i].size, if_map->n2h_desc_if[i].desc_addr);
+	}
+
+	/*
+	 * H2N ring settings
+	 */
+	for (i = 0; i < NSS_H2N_RING_COUNT; i++) {
+		struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[i];
+		h2n_desc_ring->desc_ring.desc = (struct h2n_descriptor *)(h2n_info->kern_addr + i * sizeof(struct h2n_descriptor) * (NSS_RING_SIZE + 2));
+		h2n_desc_ring->desc_ring.size = NSS_RING_SIZE;
+		h2n_desc_ring->hlos_index = if_map->h2n_hlos_index[i];
+		spin_lock_init(&h2n_desc_ring->lock);
+
+		if_map->h2n_desc_if[i].size = NSS_RING_SIZE;
+		if_map->h2n_desc_if[i].desc_addr = h2n_info->dma_addr + i * sizeof(struct h2n_descriptor) * (NSS_RING_SIZE + 2);
+		nss_info("%px: H2N ring %d, size %d, addr = %x\n", nss_ctx, i, if_map->h2n_desc_if[i].size, if_map->h2n_desc_if[i].desc_addr);
+	}
+
+	/*
+	 * Flush the updated nss_if_mem_map.
+	 */
+	NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_TO_DEVICE);
+	NSS_CORE_DSB();
+
+	return true;
+
+cleanup:
+	if (n2h_info->memtype == NSS_MEMINFO_MEMTYPE_SDRAM)
+		nss_meminfo_free_sdram(nss_ctx, n2h_info->dma_addr, n2h_info->kern_addr, n2h_info->total_size);
+	else
+		nss_meminfo_free_imem(nss_ctx, n2h_info->dma_addr, n2h_info->total_size);
+
+	nss_meminfo_free_block_lists(nss_ctx);
+	return false;
+}
+
+/*
+ * nss_meminfo_config_show()
+ *	function to show meinfo configuration per core.
+ */
+static int nss_meminfo_config_show(struct seq_file *seq, void *v)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_meminfo_ctx *mem_ctx;
+	struct nss_meminfo_n2h_h2n_info *n2h_info;
+	struct nss_meminfo_n2h_h2n_info *h2n_info;
+	struct nss_meminfo_map *map;
+	struct nss_meminfo_request *r;
+	int nss_id;
+	int i;
+
+	/*
+	 * i_private is passed to us by debug_fs_create()
+	 */
+	nss_id = (int)(nss_ptr_t)seq->private;
+	if (nss_id < 0 || nss_id >= nss_top_main.num_nss) {
+		nss_warning("nss_id: %d is not valid\n", nss_id);
+		return -ENODEV;
+	}
+
+	nss_ctx = &nss_top_main.nss[nss_id];
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	mem_ctx = &nss_ctx->meminfo_ctx;
+	map = &mem_ctx->meminfo_map;
+	n2h_info = &mem_ctx->n2h_info;
+	h2n_info = &mem_ctx->h2n_info;
+
+	seq_printf(seq, "%-5s %-32s %-7s %-7s %-10s %-10s\n",
+			"Index", "Name", "Default", "User", "Size", "DMA Addr");
+	seq_printf(seq, "%-5s %-32s %-7s %-7s 0x%-8x 0x%-8x\n",
+			"N/A", "n2h_rings", "SDRAM",
+			nss_meminfo_memtype_table[n2h_info->memtype],
+			n2h_info->total_size, n2h_info->dma_addr);
+	seq_printf(seq, "%-5s %-32s %-7s %-7s 0x%-8x 0x%-8x\n",
+			"N/A", "h2n_rings", "SDRAM",
+			nss_meminfo_memtype_table[h2n_info->memtype],
+			h2n_info->total_size, h2n_info->dma_addr);
+
+	r = map->requests;
+	for (i = 0; i < map->num_requests; i++) {
+		seq_printf(seq, "%-5d %-32s %-7s %-7s 0x%-8x 0x%-8x\n",
+				i, r[i].name,
+				nss_meminfo_memtype_table[r[i].memtype_default],
+				nss_meminfo_memtype_table[r[i].memtype_user],
+				r[i].size, r[i].addr);
+	}
+
+	seq_printf(seq, "Available IMEM: 0x%x\n", mem_ctx->imem_end - mem_ctx->imem_tail);
+	seq_printf(seq, "How to configure? \n");
+	seq_printf(seq, "Overwrite the /etc/modules.d/32-qca-nss-drv with following contents then reboot\n\n");
+	seq_printf(seq, "qca-nss-drv meminfo_user_config=\"<core_id, name, memory_type>, ..\"\n\n");
+	seq_printf(seq, "For example, <1, h2n_rings, IMEM> stands for: h2n_rings of core 1 is on IMEM\n");
+	seq_printf(seq, "Note:UTCM_SHARED cannot be used for n2h_rings, h2n_rings and debug_log_boot_desc.\n");
+
+	return 0;
+}
+
+/*
+ * nss_meminfo_debugfs_file_open()
+ *	function to open meminfo debugfs.
+ */
+static int nss_meminfo_debugfs_file_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, nss_meminfo_config_show, inode->i_private);
+}
+
+static struct file_operations nss_meminfo_debugfs_ops = {
+	.owner   = THIS_MODULE,
+	.open    = nss_meminfo_debugfs_file_open,
+	.read    = seq_read,
+	.llseek  = seq_lseek,
+	.release = single_release,
+};
+
+/*
+ * nss_meminfo_init_debugfs()
+ *	Init meminfo debugfs.
+ */
+static void nss_meminfo_init_debugfs(struct nss_ctx_instance *nss_ctx)
+{
+	int i;
+	struct dentry *meminfo_main_dentry;
+	struct dentry *meminfo_core_dentries[NSS_MAX_CORES];
+
+	if (nss_meminfo_debugfs_exist)
+		return;
+
+	/*
+	 * Create directory for showing meminfo configuration of each core.
+	 */
+	meminfo_main_dentry = debugfs_create_dir("meminfo", nss_top_main.top_dentry);
+	if (unlikely(!meminfo_main_dentry)) {
+		nss_warning("Failed to create qca-nss-drv/meminfo directory in debugfs\n");
+		return;
+	}
+
+	for (i = 0; i < nss_top_main.num_nss; i++) {
+		char file[10];
+		snprintf(file, sizeof(file), "core%d", i);
+		meminfo_core_dentries[i] = debugfs_create_file(file, 0400, meminfo_main_dentry,
+						(void *)(nss_ptr_t)i, &nss_meminfo_debugfs_ops);
+		if (unlikely(!meminfo_core_dentries[i])) {
+			int j;
+			for (j = 0; j < i; j++)
+				debugfs_remove(meminfo_core_dentries[j]);
+			debugfs_remove(meminfo_main_dentry);
+			nss_warning("Failed to create qca-nss-drv/meminfo/%s file in debugfs", file);
+			return;
+		}
+	}
+
+	nss_meminfo_debugfs_exist = true;
+	nss_info("nss meminfo user config: %s\n", nss_meminfo_user_config);
+}
+
+/*
+ * nss_meminfo_init
+ *	Initilization
+ *
+ */
+bool nss_meminfo_init(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_meminfo_ctx *mem_ctx;
+	uint32_t *meminfo_start;
+	struct nss_meminfo_map *map;
+	struct nss_top_instance *nss_top = &nss_top_main;
+
+	mem_ctx = &nss_ctx->meminfo_ctx;
+
+	/*
+	 * meminfo_start is the label where the start address of meminfo map is stored.
+	 */
+	meminfo_start = (uint32_t *)ioremap_nocache(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET,
+							NSS_MEMINFO_RESERVE_AREA_SIZE);
+	if (!meminfo_start) {
+		nss_info_always("%px: cannot remap meminfo start\n", nss_ctx);
+		return false;
+	}
+
+	/*
+	 * Check meminfo start magic
+	 */
+	if ((uint16_t)meminfo_start[0] != NSS_MEMINFO_RESERVE_AREA_MAGIC) {
+		nss_info_always("%px: failed to verify meminfo start magic\n", nss_ctx);
+		return false;
+	}
+
+	map = &mem_ctx->meminfo_map;
+	map->start = (uint32_t *)ioremap_cache(meminfo_start[1], NSS_MEMINFO_MAP_SIZE);
+	if (!map->start) {
+		nss_info_always("%px: failed to remap meminfo map\n", nss_ctx);
+		return false;
+	}
+
+	/*
+	 * Check meminfo map magic
+	 */
+	if ((uint16_t)map->start[0] != NSS_MEMINFO_MAP_START_MAGIC) {
+		nss_info_always("%px: failed to verify meminfo map magic\n", nss_ctx);
+		return false;
+	}
+
+	/*
+	 * Meminfo map settings
+	 */
+	map->num_requests = 0;
+	map->requests = (struct nss_meminfo_request *)(map->start + 1);
+
+	/*
+	 * Init IMEM
+	 */
+	nss_top->hal_ops->init_imem(nss_ctx);
+
+	/*
+	 * Init UTCM_SHARED if supported
+	 */
+	if (!nss_top->hal_ops->init_utcm_shared(nss_ctx, meminfo_start)) {
+		nss_info_always("%px: failed to initialize UTCM_SHARED meminfo\n", nss_ctx);
+		return false;
+	}
+
+	/*
+	 * Init meminfo block lists
+	 */
+	if (!nss_meminfo_init_block_lists(nss_ctx)) {
+		nss_info_always("%px: failed to initialize meminfo block lists\n", nss_ctx);
+		return false;
+	}
+
+	/*
+	 * Configure N2H/H2N rings and nss_if_mem_map
+	 */
+	if (!nss_meminfo_configure_n2h_h2n_rings(nss_ctx))
+		return false;
+
+	nss_meminfo_init_debugfs(nss_ctx);
+
+	nss_info_always("%px: meminfo init succeed\n", nss_ctx);
+	return true;
+}
diff --git a/qca-nss-drv/nss_meminfo.h b/qca-nss-drv/nss_meminfo.h
new file mode 100644
index 0000000..5c006cc
--- /dev/null
+++ b/qca-nss-drv/nss_meminfo.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * nss_meminfo.h
+ *	nss meminfo header file.
+ */
+
+#ifndef __NSS_MEMINFO_H
+#define __NSS_MEMINFO_H
+
+#define NSS_MEMINFO_RESERVE_AREA_SIZE	0x1000	/* Size of reserved space in firmware start code aligned to one page */
+#define NSS_MEMINFO_RESERVE_AREA_MAGIC	0x9526	/* Magic at the beginning of reserved space */
+#define NSS_MEMINFO_MAP_START_OFFSET	8	/* Offset of memory map start address in reserved space */
+#define NSS_MEMINFO_MAP_SIZE		0x1000	/* Size of memory map per core aligned to one page */
+#define NSS_MEMINFO_MAP_START_MAGIC	0x9527
+#define NSS_MEMINFO_REQUEST_MAGIC	0X9528
+#define NSS_MEMINFO_MAP_END_MAGIC	0x9529
+#define NSS_MEMINFO_RESERVE_AREA_UTCM_SHARED_MAP_MAGIC 	0x9530 /* Magic at the beginning of UTCM_SHARED reserved space */
+#define NSS_MEMINFO_BLOCK_NAME_MAXLEN	48
+#define NSS_MEMINFO_MEMTYPE_NAME_MAXLEN	32
+#define NSS_MEMINFO_USER_CONFIG_MAXLEN	1024
+#define NSS_MEMINFO_POISON 		0x95	/* Invalid kernel memory address assigned for non mapable mem types */
+
+/*
+ * Memory types available
+ */
+enum nss_meminfo_memtype {
+	NSS_MEMINFO_MEMTYPE_IMEM,	/* NSS-IMEM also called TCM */
+	NSS_MEMINFO_MEMTYPE_SDRAM,	/* SDRAM also called DDR */
+	NSS_MEMINFO_MEMTYPE_UTCM_SHARED, /* UTCM memory allocated for DMA objects */
+	NSS_MEMINFO_MEMTYPE_INFO,	/* Exchange information during boot up */
+	NSS_MEMINFO_MEMTYPE_MAX
+};
+
+/*
+ * Memory request
+ * Firmware package defines each request asking host to feed the request.
+ */
+struct nss_meminfo_request {
+	uint16_t magic;					/* Request magic */
+	char name[NSS_MEMINFO_BLOCK_NAME_MAXLEN];	/* Memory block name */
+	uint16_t memtype_default;			/* Memory type requested */
+	uint16_t memtype_user;				/* User-defined memory type */
+	uint32_t alignment;				/* Alignment requirement */
+	uint32_t size;					/* Size requested */
+	uint32_t addr;					/* Memory block address got from host */
+};
+
+/*
+ * Memory map
+ * It starts with a magic then an array of memory request and end with a checksum.
+ * Firmware creates the map for host to parse.
+ */
+struct nss_meminfo_map {
+	uint32_t *start;				/* Start address */
+	uint32_t num_requests;				/* Number of requests */
+	struct nss_meminfo_request *requests;		/* Start of Request array */
+};
+
+/*
+ * Memory block
+ * Block node for each request.
+ */
+struct nss_meminfo_block {
+	struct nss_meminfo_block *next;	/* Next block in the same list */
+	uint32_t index;			/* Index to request array */
+	uint32_t size;			/* Size of memory block */
+	uint32_t dma_addr;		/* DMA address */
+	void *kern_addr;		/* Kernel address */
+};
+
+/*
+ * Memory block list
+ * List of block node of same memory type.
+ */
+struct nss_meminfo_block_list {
+	enum nss_meminfo_memtype memtype;	/* memory type */
+	uint32_t num_blks;			/* Number of blocks */
+	uint32_t total_size;			/* Size of all memory blocks in this list */
+	struct nss_meminfo_block *head;		/* list head */
+};
+
+/*
+ * H2N/N2H rings information
+ */
+struct nss_meminfo_n2h_h2n_info {
+	enum nss_meminfo_memtype memtype;	/* Memory type */
+	uint32_t total_size;			/* Total size */
+	uint32_t dma_addr;			/* DMA address */
+	void *kern_addr;			/* Kernel address */
+};
+
+/*
+ * Memory context
+ */
+struct nss_meminfo_ctx {
+	struct nss_meminfo_n2h_h2n_info n2h_info;	/* N2H rings info*/
+	struct nss_meminfo_n2h_h2n_info h2n_info;	/* H2N rings info */
+	uint32_t imem_head;				/* IMEM start address */
+	uint32_t imem_end;				/* IMEM end address */
+	uint32_t imem_tail;				/* IMEM data end */
+	uint32_t utcm_shared_head;			/* UTCM_SHARED start address */
+	uint32_t utcm_shared_end;			/* UTCM_SHARED end address */
+	uint32_t utcm_shared_tail;			/* UTCM_SHARED data end */
+	struct nss_if_mem_map *if_map;			/* nss_if_mem_map_inst virtual address */
+	uint32_t if_map_dma;				/* nss_if_mem_map_inst physical address */
+	enum nss_meminfo_memtype if_map_memtype;	/* Memory type for nss_if_mem_map */
+	struct nss_log_descriptor *logbuffer;		/* nss_logbuffer virtual address */
+	uint32_t logbuffer_dma;				/* nss_logbuffer physical address */
+	enum nss_meminfo_memtype logbuffer_memtype;	/* Memory type for logbuffer */
+	uint32_t c2c_start_dma;				/* nss_c2c start physical address */
+	enum nss_meminfo_memtype c2c_start_memtype;	/* Memory type for c2c_start */
+	void *sdma_ctrl;				/* Soft DMA controller */
+
+	struct nss_meminfo_map meminfo_map;		/* Meminfo map */
+	struct nss_meminfo_block_list block_lists[NSS_MEMINFO_MEMTYPE_MAX];
+							/* Block lists for each memory type */
+};
+
+bool nss_meminfo_init(struct nss_ctx_instance *nss_ctx);
+#endif
diff --git a/qca-nss-drv/nss_mirror.c b/qca-nss-drv/nss_mirror.c
new file mode 100644
index 0000000..a2e5061
--- /dev/null
+++ b/qca-nss-drv/nss_mirror.c
@@ -0,0 +1,296 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_mirror_stats.h"
+#include "nss_mirror_strings.h"
+#include "nss_mirror_log.h"
+
+#define NSS_MIRROR_TX_TIMEOUT 3000 /* 3 Seconds */
+
+/*
+ * Private data structure
+ */
+static struct {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+} nss_mirror_pvt;
+
+atomic_t nss_mirror_num_instances;		/* Number of active mirror stats instances. */
+
+/*
+ * nss_mirror_verify_if_num()
+ *	Verify interface number passed to us.
+ */
+bool nss_mirror_verify_if_num(uint32_t if_num)
+{
+	enum nss_dynamic_interface_type if_type;
+
+	if_type = nss_dynamic_interface_get_type(nss_mirror_get_context(), if_num);
+	if (if_type == NSS_DYNAMIC_INTERFACE_TYPE_MIRROR) {
+		return true;
+	}
+
+	return false;
+}
+EXPORT_SYMBOL(nss_mirror_verify_if_num);
+
+/*
+ * nss_mirror_handler()
+ *	Handle NSS -> HLOS messages for mirror device.
+ */
+static void nss_mirror_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm,
+		 void *app_data)
+{
+	struct nss_mirror_msg *nmm = (struct nss_mirror_msg *)ncm;
+	void *ctx;
+	nss_mirror_msg_callback_t cb;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	nss_assert(nss_mirror_verify_if_num(ncm->interface));
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_MIRROR_MSG_MAX) {
+		nss_warning("%px: received invalid message %d for mirror interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_mirror_msg)) {
+		nss_warning("%px: Length of message is greater than expected.", nss_ctx);
+		return;
+	}
+
+	/*
+	 * Log messages.
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+	nss_mirror_log_rx_msg(nmm);
+
+	switch (ncm->type) {
+	case NSS_MIRROR_MSG_SYNC_STATS:
+		/*
+		 * Debug stats embedded in stats msg.
+		 */
+		nss_mirror_stats_sync(nss_ctx, nmm, ncm->interface);
+		nss_mirror_stats_notify(nss_ctx, ncm->interface);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)app_data;
+	}
+
+	/*
+	 * Callback.
+	 */
+	cb = (nss_mirror_msg_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	/*
+	 * Call mirror interface callback.
+	 */
+	if (!cb) {
+		nss_warning("%px: No callback for mirror interface %d",
+			    nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb(ctx, ncm);
+}
+
+/*
+ * nss_mirror_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_mirror_callback(void *app_data, struct nss_cmn_msg *ncm)
+{
+	nss_mirror_pvt.response = NSS_TX_SUCCESS;
+
+	if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("mirror interface error response %d\n", ncm->response);
+		nss_mirror_pvt.response = NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Write memory barrier.
+	 */
+	smp_wmb();
+	complete(&nss_mirror_pvt.complete);
+}
+
+/*
+ * nss_mirror_tx_msg()
+ *	Transmit a mirror interface message to NSS firmware.
+ */
+nss_tx_status_t nss_mirror_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_mirror_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Sanity check the message.
+	 */
+	if (!nss_mirror_verify_if_num(ncm->interface)) {
+		nss_warning("%px: tx request for non mirror interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_MIRROR_MSG_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_mirror_log_tx_msg(msg);
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_mirror_tx_msg);
+
+/*
+ * nss_mirror_tx_msg_sync()
+ *	Transmit a mirror interface message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_mirror_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_mirror_msg *msg)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&nss_mirror_pvt.sem);
+	msg->cm.cb = (nss_ptr_t)nss_mirror_callback;
+	msg->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_mirror_tx_msg(nss_ctx, msg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: mirror_tx_msg failed\n", nss_ctx);
+		up(&nss_mirror_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&nss_mirror_pvt.complete, msecs_to_jiffies(NSS_MIRROR_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: Mirror interface tx sync failed due to timeout\n", nss_ctx);
+		nss_mirror_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = nss_mirror_pvt.response;
+	up(&nss_mirror_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_mirror_tx_msg_sync);
+
+/*
+ * nss_mirror_unregister_if()
+ *	Un-registers mirror interface from the NSS.
+ */
+void nss_mirror_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.mirror_handler_id];
+	uint32_t status;
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_mirror_verify_if_num(if_num));
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+
+	status = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to unregister handler for interface %d with NSS core\n", nss_ctx, if_num);
+	}
+
+	atomic_dec(&nss_mirror_num_instances);
+	nss_mirror_stats_reset(if_num);
+}
+EXPORT_SYMBOL(nss_mirror_unregister_if);
+
+/*
+ * nss_mirror_register_if()
+ *	Registers the mirror interface with NSS.
+ */
+struct nss_ctx_instance *nss_mirror_register_if(uint32_t if_num,
+		 nss_mirror_data_callback_t data_callback,
+		 nss_mirror_msg_callback_t event_callback,
+		 struct net_device *netdev, uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.mirror_handler_id];
+	int ret;
+
+	nss_assert(nss_ctx);
+	nss_assert(netdev);
+	nss_assert(nss_mirror_verify_if_num(if_num));
+
+	if (atomic_read(&nss_mirror_num_instances) == NSS_MAX_MIRROR_DYNAMIC_INTERFACES) {
+		nss_warning("%px: Maximum number of mirror interfaces are already allocated\n", nss_ctx);
+		return NULL;
+	}
+
+	ret = nss_mirror_stats_init(if_num, netdev);
+	if (ret < 0) {
+		nss_warning("%px: Error in initializaing mirror stats.\n", nss_ctx);
+		return NULL;
+	}
+
+	nss_core_register_handler(nss_ctx, if_num, nss_mirror_handler, netdev);
+	ret = nss_core_register_msg_handler(nss_ctx, if_num, event_callback);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_core_unregister_handler(nss_ctx, if_num);
+		nss_warning("%px: Not able to register handler for mirror interface %d with NSS core\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, data_callback, NULL, NULL, netdev, features);
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num, NSS_DYNAMIC_INTERFACE_TYPE_MIRROR);
+
+	atomic_inc(&nss_mirror_num_instances);
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_mirror_register_if);
+
+/*
+ * nss_mirror_get_context()
+ *	Get the mirror instance context.
+ */
+struct nss_ctx_instance *nss_mirror_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.mirror_handler_id];
+}
+EXPORT_SYMBOL(nss_mirror_get_context);
+
+/*
+ * nss_mirror_register_handler()
+ *	Initialize and register mirror instance handler.
+ */
+void nss_mirror_register_handler(void)
+{
+	nss_info("nss_mirror_register_handler");
+	sema_init(&nss_mirror_pvt.sem, 1);
+	init_completion(&nss_mirror_pvt.complete);
+
+	nss_mirror_stats_dentry_create();
+	nss_mirror_strings_dentry_create();
+}
diff --git a/qca-nss-drv/nss_mirror_log.c b/qca-nss-drv/nss_mirror_log.c
new file mode 100644
index 0000000..5fb8858
--- /dev/null
+++ b/qca-nss-drv/nss_mirror_log.c
@@ -0,0 +1,198 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_mirror_log.c
+ *	NSS Mirror logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_mirror_log_message_types_str
+ *	MIRROR message strings
+ */
+static int8_t *nss_mirror_log_message_types_str[NSS_MIRROR_MSG_MAX] __maybe_unused = {
+	"Mirror Configure Msg",
+	"Mirror Enable Msg",
+	"Mirror Disable Msg",
+	"Mirror Set Nexthop Msg",
+	"Mirror Reset Nexthop Msg",
+	"Mirror Stats Sync Msg",
+};
+
+/*
+ * nss_mirror_log_error_response_types_str
+ *	Strings for error types for Mirror messages
+ */
+static int8_t *nss_mirror_log_error_response_types_str[NSS_MIRROR_ERROR_TYPE_MAX] __maybe_unused = {
+	"Mirror no error",
+	"Mirror No Memory",
+	"Mirror Transmit Failure",
+	"Mirror Bad Parameter",
+	"Mirror Bad Clone Point",
+	"Mirror Intance Configured",
+	"Mirror Intance Disabled",
+	"Mirror Bad Nexthop",
+	"Mirror Nexthop Configured",
+	"Mirror Nexthop Reset",
+	"Mirror Unknown Message",
+};
+
+/*
+ * nss_mirror_log_configure_msg()
+ *	Log NSS Mirror Configure message.
+ */
+static void nss_mirror_log_configure_msg(struct nss_mirror_msg *nmm)
+{
+	struct nss_mirror_configure_msg *config_msg __maybe_unused = &nmm->msg.config;
+
+	nss_trace("%px: NSS Mirror Config message \n"
+		"Packet clone size: %u\n"
+		"Packet clone point: %hu\n",
+		config_msg,
+		config_msg->pkt_clone_size,
+		config_msg->pkt_clone_point);
+}
+
+/*
+ * nss_mirror_log_set_nexthop_msg()
+ *	Log NSS Mirror Set Nexthop message.
+ */
+static void nss_mirror_log_set_nexthop_msg(struct nss_mirror_msg *nmm)
+{
+	struct nss_mirror_set_nexthop_msg *nexthop_msg __maybe_unused = &nmm->msg.nexthop;
+
+	nss_trace("%px: NSS Mirror Nexthop message \n"
+		"Nexthop interface number: %u\n",
+		nexthop_msg,
+		nexthop_msg->if_num);
+}
+
+/*
+ * nss_mirror_log_enable_msg()
+ *	Log NSS Mirror Enable message.
+ */
+static void nss_mirror_log_enable_msg(struct nss_mirror_msg *nmm)
+{
+	nss_trace("%px: NSS Mirror message: Enable \n", nmm);
+}
+
+/*
+ * nss_mirror_log_disable_msg()
+ *	Log NSS Mirror Disable message.
+ */
+static void nss_mirror_log_disable_msg(struct nss_mirror_msg *nmm)
+{
+	nss_trace("%px: NSS Mirror message: Disable \n", nmm);
+}
+
+/*
+ * nss_mirror_log_reset_nexthop_msg()
+ *	Log NSS Mirror Reset Nexthop message.
+ */
+static void nss_mirror_log_reset_nexthop_msg(struct nss_mirror_msg *nmm)
+{
+	nss_trace("%px: NSS Mirror message: Reset Nexthop \n", nmm);
+}
+
+/*
+ * nss_mirror_log_verbose()
+ *	Log message contents.
+ */
+static void nss_mirror_log_verbose(struct nss_mirror_msg *nmm)
+{
+	switch (nmm->cm.type) {
+	case NSS_MIRROR_MSG_CONFIGURE:
+		nss_mirror_log_configure_msg(nmm);
+		break;
+
+	case NSS_MIRROR_MSG_ENABLE:
+		nss_mirror_log_enable_msg(nmm);
+		break;
+
+	case NSS_MIRROR_MSG_DISABLE:
+		nss_mirror_log_disable_msg(nmm);
+		break;
+
+	case NSS_MIRROR_MSG_SET_NEXTHOP:
+		nss_mirror_log_set_nexthop_msg(nmm);
+		break;
+
+	case NSS_MIRROR_MSG_RESET_NEXTHOP:
+		nss_mirror_log_reset_nexthop_msg(nmm);
+		break;
+
+	case NSS_MIRROR_MSG_SYNC_STATS:
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", nmm);
+		break;
+	}
+}
+
+/*
+ * nss_mirror_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_mirror_log_tx_msg(struct nss_mirror_msg *nmm)
+{
+	if (nmm->cm.type >= NSS_MIRROR_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", nmm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nmm, nmm->cm.type, nss_mirror_log_message_types_str[nmm->cm.type]);
+	nss_mirror_log_verbose(nmm);
+}
+
+/*
+ * nss_mirror_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_mirror_log_rx_msg(struct nss_mirror_msg *nmm)
+{
+	if (nmm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", nmm);
+		return;
+	}
+
+	if (nmm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nmm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nmm, nmm->cm.type,
+			nss_mirror_log_message_types_str[nmm->cm.type],
+			nmm->cm.response, nss_cmn_response_str[nmm->cm.response]);
+		goto verbose;
+	}
+
+	if (nmm->cm.error >= NSS_MIRROR_ERROR_TYPE_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			nmm, nmm->cm.type, nss_mirror_log_message_types_str[nmm->cm.type],
+			nmm->cm.response, nss_cmn_response_str[nmm->cm.response],
+			nmm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		nmm, nmm->cm.type, nss_mirror_log_message_types_str[nmm->cm.type],
+		nmm->cm.response, nss_cmn_response_str[nmm->cm.response],
+		nmm->cm.error, nss_mirror_log_error_response_types_str[nmm->cm.error]);
+
+verbose:
+	nss_mirror_log_verbose(nmm);
+}
diff --git a/qca-nss-drv/nss_mirror_log.h b/qca-nss-drv/nss_mirror_log.h
new file mode 100644
index 0000000..a81a4a0
--- /dev/null
+++ b/qca-nss-drv/nss_mirror_log.h
@@ -0,0 +1,39 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_MIRROR_LOG_H__
+#define __NSS_MIRROR_LOG_H__
+
+/*
+ * nss_mirror_log.h
+ *	NSS Mirror Log Header File.
+ */
+
+/*
+ * nss_mirror_log_tx_msg
+ *	Logs a Mirror message that is sent to the NSS firmware.
+ */
+void nss_mirror_log_tx_msg(struct nss_mirror_msg *nmm);
+
+/*
+ * nss_mirror_log_rx_msg
+ *	Logs a Mirror message that is received from the NSS firmware.
+ */
+void nss_mirror_log_rx_msg(struct nss_mirror_msg *nmm);
+
+#endif /* __NSS_MIRROR_LOG_H__*/
diff --git a/qca-nss-drv/nss_mirror_stats.c b/qca-nss-drv/nss_mirror_stats.c
new file mode 100644
index 0000000..51fa93c
--- /dev/null
+++ b/qca-nss-drv/nss_mirror_stats.c
@@ -0,0 +1,324 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_mirror.h"
+#include "nss_mirror_stats.h"
+#include "nss_mirror_strings.h"
+
+static struct nss_mirror_stats_debug_instance *stats_db[NSS_MAX_MIRROR_DYNAMIC_INTERFACES];
+					/* Mirror stats data structure. */
+
+/*
+ * Atomic notifier data structure for statistics
+ */
+ATOMIC_NOTIFIER_HEAD(nss_mirror_stats_notifier);
+
+static DEFINE_SPINLOCK(nss_mirror_stats_lock);
+
+/*
+ * nss_mirror_stats_get()
+ *	Get mirror interface statistics.
+ */
+static void nss_mirror_stats_get(void *stats_mem, uint32_t stats_num)
+{
+	struct nss_mirror_stats_debug_instance *stats = (struct nss_mirror_stats_debug_instance *)stats_mem;
+	int i;
+
+	if (!stats) {
+		nss_warning("No memory to copy mirror interface stats");
+		return;
+	}
+
+	spin_lock_bh(&nss_mirror_stats_lock);
+	for (i = 0; i < NSS_MAX_MIRROR_DYNAMIC_INTERFACES; i++) {
+
+		/*
+		 * Copy maximum for given number of instances only.
+		 */
+		if (likely(stats_db[i])) {
+			if (likely(stats_num)) {
+				memcpy(stats, stats_db[i], sizeof(struct nss_mirror_stats_debug_instance));
+				stats++;
+				stats_num--;
+			} else {
+				break;
+			}
+		}
+	}
+	spin_unlock_bh(&nss_mirror_stats_lock);
+}
+
+/*
+ * nss_mirror_stats_read()
+ *	Read mirror interface statistics.
+ */
+static ssize_t nss_mirror_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+
+	uint32_t max_output_lines = 2 /* header & footer for instance stats */
+					+ NSS_MAX_MIRROR_DYNAMIC_INTERFACES *
+					 ((NSS_STATS_NODE_MAX + 3 ) + (NSS_MIRROR_STATS_MAX + 3)) /*instance stats */
+					 + 2;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	struct net_device *dev;
+	struct nss_mirror_stats_debug_instance *mirror_shadow_stats;
+	uint32_t id, mirror_active_instances = atomic_read(&nss_mirror_num_instances);
+	char *lbuf;
+
+	if (!mirror_active_instances) {
+		return 0;
+	}
+
+	lbuf = vzalloc(size_al);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	mirror_shadow_stats = vzalloc(sizeof(struct nss_mirror_stats_debug_instance) *
+			 mirror_active_instances);
+	if (unlikely(!mirror_shadow_stats)) {
+		nss_warning("Could not allocate memory for base debug statistics buffer");
+		vfree(lbuf);
+		return 0;
+	}
+
+	/*
+	 * Get all stats
+	 */
+	nss_mirror_stats_get((void *)mirror_shadow_stats, mirror_active_instances);
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "mirror stats", NSS_STATS_SINGLE_CORE);
+
+	/*
+	 * Session stats
+	 */
+	for (id = 0; id < mirror_active_instances; id++) {
+			dev = dev_get_by_index(&init_net, mirror_shadow_stats[id].if_index);
+			if (likely(dev)) {
+
+				size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%d. nss interface id=%d, netdevice=%s\n", id,
+						mirror_shadow_stats[id].if_num, dev->name);
+				dev_put(dev);
+			} else {
+				size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%d. nss interface id=%d\n", id,
+						mirror_shadow_stats[id].if_num);
+			}
+
+			size_wr += nss_stats_fill_common_stats(mirror_shadow_stats[id].if_num, id, lbuf, size_wr, size_al, "mirror");
+
+			/*
+			 * Mirror interface exception stats.
+			 */
+			size_wr += nss_stats_print("mirror", "mirror exception stats",
+							 id,
+							 nss_mirror_strings_stats,
+							 mirror_shadow_stats[id].stats,
+							 NSS_MIRROR_STATS_MAX,
+							 lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	vfree(mirror_shadow_stats);
+	vfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_mirror_stats_sync()
+ *	API to sync statistics for mirror interface.
+ */
+void nss_mirror_stats_sync(struct nss_ctx_instance *nss_ctx,
+		 struct nss_mirror_msg *nmm, uint16_t if_num)
+{
+	uint8_t i, j;
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	struct nss_mirror_stats_sync_msg *stats_msg = &nmm->msg.stats;
+	struct nss_cmn_node_stats *node_stats_ptr = &stats_msg->node_stats;
+	uint32_t *mirror_stats_ptr = (uint32_t *)&stats_msg->mirror_stats;
+
+	spin_lock_bh(&nss_mirror_stats_lock);
+	for (i = 0; i < NSS_MAX_MIRROR_DYNAMIC_INTERFACES; i++) {
+		if (!stats_db[i] || (stats_db[i]->if_num != if_num)) {
+			continue;
+		}
+
+		for (j = 0; j < NSS_MIRROR_STATS_MAX; j++) {
+			/*
+			 * Sync stats.
+			 */
+			stats_db[i]->stats[j] += mirror_stats_ptr[j];
+		}
+		spin_unlock_bh(&nss_mirror_stats_lock);
+		goto sync_cmn_stats;
+	}
+
+	spin_unlock_bh(&nss_mirror_stats_lock);
+	nss_warning("Invalid mirror stats sync message received for %d interface\n", if_num);
+	return;
+
+sync_cmn_stats:
+	spin_lock_bh(&nss_mirror_stats_lock);
+
+	/*
+	 * Sync common stats.
+	 */
+	nss_top->stats_node[if_num][NSS_STATS_NODE_RX_PKTS] += node_stats_ptr->rx_packets;
+	nss_top->stats_node[if_num][NSS_STATS_NODE_RX_BYTES] += node_stats_ptr->rx_bytes;
+	nss_top->stats_node[if_num][NSS_STATS_NODE_TX_PKTS] += node_stats_ptr->tx_packets;
+	nss_top->stats_node[if_num][NSS_STATS_NODE_TX_BYTES] += node_stats_ptr->tx_bytes;
+
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		nss_top->stats_node[if_num][NSS_STATS_NODE_RX_QUEUE_0_DROPPED + i] +=
+			node_stats_ptr->rx_dropped[i];
+	}
+
+	spin_unlock_bh(&nss_mirror_stats_lock);
+}
+
+/*
+ * nss_mirror_stats_reset()
+ *	API to reset the mirror interface stats.
+ */
+void nss_mirror_stats_reset(uint32_t if_num)
+{
+	struct nss_mirror_stats_debug_instance *mirror_debug_instance = NULL;
+	uint8_t i;
+
+	/*
+	 * Reset common node stats.
+	 */
+	nss_stats_reset_common_stats(if_num);
+
+	/*
+	 * Reset mirror stats.
+	 */
+	spin_lock_bh(&nss_mirror_stats_lock);
+	for (i = 0; i < NSS_MAX_MIRROR_DYNAMIC_INTERFACES; i++) {
+		if (!stats_db[i] || (stats_db[i]->if_num != if_num)) {
+			continue;
+		}
+
+		mirror_debug_instance = stats_db[i];
+		stats_db[i] = NULL;
+		break;
+	}
+	spin_unlock_bh(&nss_mirror_stats_lock);
+
+	if (mirror_debug_instance) {
+		vfree(mirror_debug_instance);
+	}
+}
+
+/*
+ * nss_mirror_stats_init()
+ *	API to initialize mirror debug instance statistics.
+ */
+int nss_mirror_stats_init(uint32_t if_num, struct net_device *netdev)
+{
+	struct nss_mirror_stats_debug_instance *mirror_debug_instance = NULL;
+	uint8_t i;
+
+	mirror_debug_instance =
+		(struct nss_mirror_stats_debug_instance *)vzalloc(sizeof(struct nss_mirror_stats_debug_instance));
+	if (!mirror_debug_instance) {
+		nss_warning("Memory alloc failed for mirror stats instance.\n");
+		return -1;
+	}
+
+	spin_lock_bh(&nss_mirror_stats_lock);
+	for (i = 0; i < NSS_MAX_MIRROR_DYNAMIC_INTERFACES; i++) {
+		if (stats_db[i] != NULL) {
+			continue;
+		}
+
+		stats_db[i] = mirror_debug_instance;
+		stats_db[i]->if_num = if_num;
+		stats_db[i]->if_index = netdev->ifindex;
+		spin_unlock_bh(&nss_mirror_stats_lock);
+		return 0;
+	}
+	spin_unlock_bh(&nss_mirror_stats_lock);
+	vfree(mirror_debug_instance);
+	return -1;
+}
+
+/*
+ * nss_mirror_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(mirror)
+
+/*
+ * nss_mirror_stats_dentry_create()
+ *	Create mirror interface statistics debug entry.
+ */
+void nss_mirror_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("mirror", &nss_mirror_stats_ops);
+}
+
+/*
+ * nss_mirror_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_mirror_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_mirror_stats_notification mirror_stats;
+	int i;
+
+	spin_lock_bh(&nss_mirror_stats_lock);
+	for (i = 0; i < NSS_MAX_MIRROR_DYNAMIC_INTERFACES; i++) {
+		if (!stats_db[i] || (stats_db[i]->if_num != if_num)) {
+			continue;
+		}
+
+		memcpy(mirror_stats.stats_ctx, stats_db[i]->stats, sizeof(mirror_stats.stats_ctx));
+		mirror_stats.core_id = nss_ctx->id;
+		mirror_stats.if_num = if_num;
+		spin_unlock_bh(&nss_mirror_stats_lock);
+		atomic_notifier_call_chain(&nss_mirror_stats_notifier, NSS_STATS_EVENT_NOTIFY, &mirror_stats);
+		return;
+	}
+	spin_unlock_bh(&nss_mirror_stats_lock);
+}
+
+/*
+ * nss_mirror_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_mirror_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_mirror_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_mirror_stats_unregister_notifier);
+
+/*
+ * nss_mirror_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_mirror_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_mirror_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_mirror_stats_register_notifier);
diff --git a/qca-nss-drv/nss_mirror_stats.h b/qca-nss-drv/nss_mirror_stats.h
new file mode 100644
index 0000000..22622a5
--- /dev/null
+++ b/qca-nss-drv/nss_mirror_stats.h
@@ -0,0 +1,44 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_MIRROR_STATS_H
+#define __NSS_MIRROR_STATS_H
+
+/*
+ * Number of active mirror stats instances.
+ */
+extern atomic_t nss_mirror_num_instances;
+
+/*
+ * nss_mirror_stats_debug_instance
+ *	Stucture for H2N/N2H mirror interface debug stats.
+ */
+struct nss_mirror_stats_debug_instance {
+	uint64_t stats[NSS_MIRROR_STATS_MAX];	/* Mirror statistics for each instance. */
+	int32_t if_index;			/* Mirror instance netdev index. */
+	uint32_t if_num;			/* Mirror instance NSS interface number */
+};
+
+extern void nss_mirror_stats_sync(struct nss_ctx_instance *nss_ctx,
+		 struct nss_mirror_msg *nmm, uint16_t if_num);
+extern void nss_mirror_stats_reset(uint32_t if_num);
+extern int nss_mirror_stats_init(uint32_t if_num, struct net_device *netdev);
+extern void nss_mirror_stats_dentry_create(void);
+extern void nss_mirror_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+
+#endif /* __NSS_MIRROR_STATS_H */
diff --git a/qca-nss-drv/nss_mirror_strings.c b/qca-nss-drv/nss_mirror_strings.c
new file mode 100644
index 0000000..fb68e04
--- /dev/null
+++ b/qca-nss-drv/nss_mirror_strings.c
@@ -0,0 +1,58 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_mirror_strings.h"
+
+/*
+ * nss_mirror_strings_stats
+ *	Mirror statistics strings for nss session stats.
+ */
+struct nss_stats_info nss_mirror_strings_stats[NSS_MIRROR_STATS_MAX] = {
+	{"pkts",		NSS_STATS_TYPE_SPECIAL},
+	{"bytes",		NSS_STATS_TYPE_SPECIAL},
+	{"tx_fail",		NSS_STATS_TYPE_DROP},
+	{"dest_lookup_fail",	NSS_STATS_TYPE_DROP},
+	{"mem_alloc_fail",	NSS_STATS_TYPE_ERROR},
+	{"copy_fail",		NSS_STATS_TYPE_ERROR},
+};
+
+/*
+ * nss_mirror_strings_read()
+ *	Read mirror statistics names
+ */
+static ssize_t nss_mirror_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_mirror_strings_stats, NSS_MIRROR_STATS_MAX);
+}
+
+/*
+ * nss_mirror_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(mirror);
+
+/*
+ * nss_mirror_strings_dentry_create()
+ *	Create mirror statistics strings debug entry.
+ */
+void nss_mirror_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("mirror", &nss_mirror_strings_ops);
+}
diff --git a/qca-nss-drv/nss_mirror_strings.h b/qca-nss-drv/nss_mirror_strings.h
new file mode 100644
index 0000000..24b73f4
--- /dev/null
+++ b/qca-nss-drv/nss_mirror_strings.h
@@ -0,0 +1,27 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#ifndef __NSS_MIRROR_STRINGS_H
+#define __NSS_MIRROR_STRINGS_H
+
+#include "nss_mirror_stats.h"
+
+extern struct nss_stats_info nss_mirror_strings_stats[NSS_MIRROR_STATS_MAX];
+extern void nss_mirror_strings_dentry_create(void);
+
+#endif /* __NSS_MIRROR_STRINGS_H */
diff --git a/qca-nss-drv/nss_n2h.c b/qca-nss-drv/nss_n2h.c
new file mode 100644
index 0000000..ea5c2d0
--- /dev/null
+++ b/qca-nss-drv/nss_n2h.c
@@ -0,0 +1,2250 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_n2h.c
+ *	NSS N2H node APIs
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_n2h_stats.h"
+#include "nss_n2h_strings.h"
+#include "nss_drv_strings.h"
+
+#define NSS_N2H_MAX_BUF_POOL_SIZE (1024 * 1024 * 20) /* 20MB */
+#define NSS_N2H_MIN_EMPTY_POOL_BUF_SZ		32
+#define NSS_N2H_MAX_EMPTY_POOL_BUF_SZ		131072
+#define NSS_N2H_DEFAULT_EMPTY_POOL_BUF_SZ	8192
+#define NSS_N2H_TX_TIMEOUT 3000 /* 3 Seconds */
+
+int nss_n2h_empty_pool_buf_cfg[NSS_MAX_CORES] __read_mostly = {-1, -1};
+int nss_n2h_empty_paged_pool_buf_cfg[NSS_MAX_CORES] __read_mostly = {-1, -1};
+int nss_n2h_water_mark[NSS_MAX_CORES][2] __read_mostly = {{-1, -1}, {-1, -1} };
+int nss_n2h_paged_water_mark[NSS_MAX_CORES][2] __read_mostly = {{-1, -1}, {-1, -1} };
+int nss_n2h_wifi_pool_buf_cfg __read_mostly = -1;
+int nss_n2h_core0_mitigation_cfg __read_mostly = 1;
+int nss_n2h_core1_mitigation_cfg __read_mostly = 1;
+int nss_n2h_core0_add_buf_pool_size __read_mostly;
+int nss_n2h_core1_add_buf_pool_size __read_mostly;
+int nss_n2h_queue_limit[NSS_MAX_CORES] __read_mostly = {NSS_DEFAULT_QUEUE_LIMIT, NSS_DEFAULT_QUEUE_LIMIT};
+int nss_n2h_host_bp_config[NSS_MAX_CORES] __read_mostly;
+
+struct nss_n2h_registered_data {
+	nss_n2h_msg_callback_t n2h_callback;
+	void *app_data;
+};
+
+static struct nss_n2h_cfg_pvt nss_n2h_nepbcfgp[NSS_MAX_CORES];
+static struct nss_n2h_registered_data nss_n2h_rd[NSS_MAX_CORES];
+static struct nss_n2h_cfg_pvt nss_n2h_rcp;
+static struct nss_n2h_cfg_pvt nss_n2h_mitigationcp[NSS_CORE_MAX];
+static struct nss_n2h_cfg_pvt nss_n2h_bufcp[NSS_CORE_MAX];
+static struct nss_n2h_cfg_pvt nss_n2h_wp;
+static struct nss_n2h_cfg_pvt nss_n2h_q_cfg_pvt;
+static struct nss_n2h_cfg_pvt nss_n2h_q_lim_pvt;
+static struct nss_n2h_cfg_pvt nss_n2h_host_bp_cfg_pvt;
+
+/*
+ * nss_n2h_interface_handler()
+ *	Handle NSS -> HLOS messages for N2H node
+ */
+static void nss_n2h_interface_handler(struct nss_ctx_instance *nss_ctx,
+					struct nss_cmn_msg *ncm,
+					void *app_data)
+{
+	struct nss_n2h_msg *nnm = (struct nss_n2h_msg *)ncm;
+	nss_n2h_msg_callback_t cb;
+
+	BUG_ON(ncm->interface != NSS_N2H_INTERFACE);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (nnm->cm.type >= NSS_METADATA_TYPE_N2H_MAX) {
+		nss_warning("%px: received invalid message %d for Offload stats interface", nss_ctx, nnm->cm.type);
+		return;
+	}
+
+	switch (nnm->cm.type) {
+	case NSS_TX_METADATA_TYPE_N2H_RPS_CFG:
+		nss_info("NSS N2H rps_en %d \n",nnm->msg.rps_cfg.enable);
+		break;
+
+	case NSS_TX_METADATA_TYPE_N2H_MITIGATION_CFG:
+		nss_info("NSS N2H mitigation_dis %d \n",nnm->msg.mitigation_cfg.enable);
+		break;
+
+	case NSS_TX_METADATA_TYPE_N2H_EMPTY_POOL_BUF_CFG:
+		nss_info("%px: empty pool buf cfg response from FW", nss_ctx);
+		break;
+
+	case NSS_TX_METADATA_TYPE_N2H_FLUSH_PAYLOADS:
+		nss_info("%px: flush payloads cmd response from FW", nss_ctx);
+		break;
+
+	case NSS_RX_METADATA_TYPE_N2H_STATS_SYNC:
+		/*
+		 * Update driver statistics and send statistics notifications to the registered modules.
+		 */
+		nss_n2h_stats_sync(nss_ctx, &nnm->msg.stats_sync);
+		nss_n2h_stats_notify(nss_ctx);
+		break;
+
+	default:
+		if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+			/*
+			 * Check response
+			 */
+			nss_info("%px: Received response %d for type %d, interface %d",
+						nss_ctx, ncm->response, ncm->type, ncm->interface);
+		}
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, n2h sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (nnm->cm.response == NSS_CMN_RESPONSE_NOTIFY) {
+		/*
+		 * Place holder for the user to create right call
+		 * back and app data when response is NSS_CMN_RESPONSE_NOTIFY
+		 */
+		ncm->cb = (nss_ptr_t)nss_n2h_rd[nss_ctx->id].n2h_callback;
+		ncm->app_data = (nss_ptr_t)nss_n2h_rd[nss_ctx->id].app_data;
+	}
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * Callback
+	 */
+	cb = (nss_n2h_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, nnm);
+}
+
+/*
+ * nss_n2h_mitigation_cfg_callback()
+ *	call back function for mitigation configuration
+ */
+static void nss_n2h_mitigation_cfg_callback(void *app_data, struct nss_n2h_msg *nnm)
+{
+	uint32_t core_num = (uint32_t)(nss_ptr_t)app_data;
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[core_num];
+
+	if (nnm->cm.response != NSS_CMN_RESPONSE_ACK) {
+
+		/*
+		 * Error, hence we are not updating the nss_n2h_mitigate_en
+		 */
+		nss_n2h_mitigationcp[core_num].response = NSS_FAILURE;
+		complete(&nss_n2h_mitigationcp[core_num].complete);
+		nss_warning("core%d: MITIGATION configuration failed : %d\n", core_num, nnm->cm.error);
+		return;
+	}
+
+	nss_info("core%d: MITIGATION configuration succeeded: %d\n", core_num, nnm->cm.error);
+
+	nss_ctx->n2h_mitigate_en = nnm->msg.mitigation_cfg.enable;
+	nss_n2h_mitigationcp[core_num].response = NSS_SUCCESS;
+	complete(&nss_n2h_mitigationcp[core_num].complete);
+}
+
+/*
+ * nss_n2h_buf_cfg_callback()
+ *	call back function for pbuf configuration
+ */
+static void nss_n2h_bufs_cfg_callback(void *app_data, struct nss_n2h_msg *nnm)
+{
+	uint32_t core_num = (uint32_t)(nss_ptr_t)app_data;
+	unsigned int allocated_sz;
+
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[core_num];
+
+	if (nnm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_n2h_bufcp[core_num].response = NSS_FAILURE;
+		nss_warning("core%d: buf configuration failed : %d\n", core_num, nnm->cm.error);
+		goto done;
+	}
+
+	nss_info("core%d: buf configuration succeeded: %d\n", core_num, nnm->cm.error);
+
+	allocated_sz = nnm->msg.buf_pool.nss_buf_page_size * nnm->msg.buf_pool.nss_buf_num_pages;
+	nss_ctx->buf_sz_allocated += allocated_sz;
+
+	nss_n2h_bufcp[core_num].response = NSS_SUCCESS;
+
+done:
+	complete(&nss_n2h_bufcp[core_num].complete);
+}
+
+/*
+ * nss_n2h_payload_stats_callback()
+ *	It gets called response to payload accounting.
+ */
+static void nss_n2h_payload_stats_callback(void *app_data,
+					struct nss_n2h_msg *nnm)
+{
+	uint32_t core_num = (uint32_t)(nss_ptr_t)app_data;
+
+	if (nnm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		struct nss_n2h_empty_pool_buf *nnepbcm;
+		nnepbcm = &nnm->msg.empty_pool_buf_cfg;
+
+		nss_warning("%d: core empty pool buf set failure: %d\n",
+				core_num, nnm->cm.error);
+		nss_n2h_nepbcfgp[core_num].response = NSS_FAILURE;
+		complete(&nss_n2h_nepbcfgp[core_num].complete);
+		return;
+	}
+
+	if (nnm->cm.type == NSS_TX_METADATA_TYPE_GET_WATER_MARK) {
+		nss_n2h_nepbcfgp[core_num].empty_buf_pool_info.pool_size =
+			ntohl(nnm->msg.payload_info.pool_size);
+		nss_n2h_nepbcfgp[core_num].empty_buf_pool_info.low_water =
+			ntohl(nnm->msg.payload_info.low_water);
+		nss_n2h_nepbcfgp[core_num].empty_buf_pool_info.high_water =
+			ntohl(nnm->msg.payload_info.high_water);
+	}
+
+	if (nnm->cm.type == NSS_TX_METADATA_TYPE_GET_PAGED_WATER_MARK) {
+		nss_n2h_nepbcfgp[core_num].empty_paged_buf_pool_info.pool_size =
+			ntohl(nnm->msg.paged_payload_info.pool_size);
+		nss_n2h_nepbcfgp[core_num].empty_paged_buf_pool_info.low_water =
+			ntohl(nnm->msg.paged_payload_info.low_water);
+		nss_n2h_nepbcfgp[core_num].empty_paged_buf_pool_info.high_water =
+			ntohl(nnm->msg.paged_payload_info.high_water);
+	}
+
+	nss_n2h_nepbcfgp[core_num].response = NSS_SUCCESS;
+	complete(&nss_n2h_nepbcfgp[core_num].complete);
+}
+
+/*
+ * nss_n2h_set_wifi_payloads_callback()
+ *	call back function for response to wifi pool configuration
+ *
+ */
+static void nss_n2h_set_wifi_payloads_callback(void *app_data,
+					struct nss_n2h_msg *nnm)
+{
+	struct nss_ctx_instance *nss_ctx __maybe_unused = (struct nss_ctx_instance *)app_data;
+	if (nnm->cm.response != NSS_CMN_RESPONSE_ACK) {
+
+		nss_n2h_wp.response = NSS_FAILURE;
+		complete(&nss_n2h_wp.complete);
+		nss_warning("%px: wifi pool configuration failed : %d\n", nss_ctx,
+				nnm->cm.error);
+		return;
+	}
+
+	nss_info("%px: wifi payload configuration succeeded: %d\n", nss_ctx,
+			nnm->cm.error);
+	nss_n2h_wp.response = NSS_SUCCESS;
+	nss_n2h_wp.wifi_pool = ntohl(nnm->msg.wp.payloads);
+	complete(&nss_n2h_wp.complete);
+}
+
+/*
+ * nss_n2h_get_payload_info()
+ *	Gets Payload information.
+ */
+static int nss_n2h_get_payload_info(nss_ptr_t core_num, struct nss_n2h_msg *nnm, struct nss_n2h_payload_info *nnepbcm)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[core_num];
+	nss_tx_status_t nss_tx_status;
+	int ret = NSS_FAILURE;
+
+	/*
+	 * Note that semaphore should be already held.
+	 */
+
+	nss_tx_status = nss_n2h_tx_msg(nss_ctx, nnm);
+
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: core %d nss_tx error errorn", nss_ctx, (int)core_num);
+		return NSS_FAILURE;
+	}
+
+	/*
+	 * Blocking call, wait till we get ACK for this msg.
+	 */
+	ret = wait_for_completion_timeout(&nss_n2h_nepbcfgp[core_num].complete,
+			msecs_to_jiffies(NSS_CONN_CFG_TIMEOUT));
+	if (ret == 0) {
+		nss_warning("%px: core %d waiting for ack timed out\n", nss_ctx, (int)core_num);
+		return NSS_FAILURE;
+	}
+
+	if (NSS_FAILURE == nss_n2h_nepbcfgp[core_num].response) {
+		nss_warning("%px: core %d response returned failure\n", nss_ctx, (int)core_num);
+		return NSS_FAILURE;
+	}
+
+	return NSS_SUCCESS;
+}
+
+/*
+ * nss_n2h_get_default_payload_info()
+ *	Gets the default payload information.
+ */
+static int nss_n2h_get_default_payload_info(nss_ptr_t core_num)
+{
+	struct nss_n2h_msg nnm;
+
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE,
+			NSS_TX_METADATA_TYPE_GET_WATER_MARK,
+			sizeof(struct nss_n2h_payload_info),
+			nss_n2h_payload_stats_callback,
+			(void *)core_num);
+
+	return nss_n2h_get_payload_info(core_num, &nnm,
+			&nnm.msg.payload_info);
+}
+
+/*
+ * nss_n2h_get_paged_payload_info()
+ *	Gets the paged payload information.
+ */
+static int nss_n2h_get_paged_payload_info(nss_ptr_t core_num)
+{
+	struct nss_n2h_msg nnm;
+
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE,
+			NSS_TX_METADATA_TYPE_GET_PAGED_WATER_MARK,
+			sizeof(struct nss_n2h_payload_info),
+			nss_n2h_payload_stats_callback,
+			(void *)core_num);
+
+	return nss_n2h_get_payload_info(core_num, &nnm,
+			&nnm.msg.paged_payload_info);
+}
+
+/*
+ * nss_n2h_set_empty_buf_pool()
+ *	Sets empty pool buffer
+ */
+static int nss_n2h_set_empty_buf_pool(struct ctl_table *ctl, int write,
+				void __user *buffer,
+				size_t *lenp, loff_t *ppos,
+				nss_ptr_t core_num, int *new_val)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[core_num];
+	struct nss_n2h_msg nnm;
+	struct nss_n2h_empty_pool_buf *nnepbcm;
+	nss_tx_status_t nss_tx_status;
+	int ret = NSS_FAILURE;
+
+	/*
+	 * Acquiring semaphore
+	 */
+	down(&nss_n2h_nepbcfgp[core_num].sem);
+
+	/*
+	 * Take snap shot of current value
+	 */
+	nss_n2h_nepbcfgp[core_num].empty_buf_pool_info.pool_size = *new_val;
+
+	if (!write) {
+		ret = nss_n2h_get_default_payload_info(core_num);
+		*new_val = nss_n2h_nepbcfgp[core_num].empty_buf_pool_info.pool_size;
+		if (ret == NSS_FAILURE) {
+			up(&nss_n2h_nepbcfgp[core_num].sem);
+			return -EBUSY;
+		}
+
+		up(&nss_n2h_nepbcfgp[core_num].sem);
+
+		ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+		return ret;
+	}
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret) {
+		up(&nss_n2h_nepbcfgp[core_num].sem);
+		return ret;
+	}
+
+	if ((*new_val < NSS_N2H_MIN_EMPTY_POOL_BUF_SZ)) {
+		nss_warning("%px: core %d setting %d < min number of buffer",
+				nss_ctx, (int)core_num, *new_val);
+		goto failure;
+	}
+
+	nss_info("%px: core %d number of empty pool buffer is : %d\n",
+		nss_ctx, (int)core_num, *new_val);
+
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE,
+			NSS_TX_METADATA_TYPE_N2H_EMPTY_POOL_BUF_CFG,
+			sizeof(struct nss_n2h_empty_pool_buf),
+			nss_n2h_payload_stats_callback,
+			(nss_ptr_t *)core_num);
+
+	nnepbcm = &nnm.msg.empty_pool_buf_cfg;
+	nnepbcm->pool_size = htonl(*new_val);
+	nss_tx_status = nss_n2h_tx_msg(nss_ctx, &nnm);
+
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: core %d nss_tx error empty pool buffer: %d\n",
+				nss_ctx, (int)core_num, *new_val);
+		goto failure;
+	}
+
+	/*
+	 * Blocking call, wait till we get ACK for this msg.
+	 */
+	ret = wait_for_completion_timeout(&nss_n2h_nepbcfgp[core_num].complete,
+			msecs_to_jiffies(NSS_CONN_CFG_TIMEOUT));
+	if (ret == 0) {
+		nss_warning("%px: core %d Waiting for ack timed out\n", nss_ctx, (int)core_num);
+		goto failure;
+	}
+
+	/*
+	 * ACK/NACK received from NSS FW
+	 * If ACK: Callback function will update nss_n2h_empty_pool_buf with
+	 * nss_n2h_nepbcfgp.num_conn_valid, which holds the user input
+	 */
+	if (NSS_FAILURE == nss_n2h_nepbcfgp[core_num].response) {
+		goto failure;
+	}
+
+	up(&nss_n2h_nepbcfgp[core_num].sem);
+	return 0;
+
+failure:
+	/*
+	 * Restore the current_value to its previous state
+	 */
+	*new_val = nss_n2h_nepbcfgp[core_num].empty_buf_pool_info.pool_size;
+	up(&nss_n2h_nepbcfgp[core_num].sem);
+	return NSS_FAILURE;
+}
+
+/*
+ * nss_n2h_set_empty_paged_pool_buf()
+ *	Sets empty paged pool buffer
+ */
+static int nss_n2h_set_empty_paged_pool_buf(struct ctl_table *ctl, int write,
+				void __user *buffer,
+				size_t *lenp, loff_t *ppos,
+				nss_ptr_t core_num, int *new_val)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[core_num];
+	struct nss_n2h_msg nnm;
+	struct nss_n2h_empty_pool_buf *nneppbcm;
+	nss_tx_status_t nss_tx_status;
+	int ret = NSS_FAILURE;
+
+	/*
+	 * Acquiring semaphore
+	 */
+	down(&nss_n2h_nepbcfgp[core_num].sem);
+
+	/*
+	 * Take snap shot of current value
+	 */
+	nss_n2h_nepbcfgp[core_num].empty_paged_buf_pool_info.pool_size = *new_val;
+
+	if (!write) {
+		ret = nss_n2h_get_paged_payload_info(core_num);
+		*new_val = nss_n2h_nepbcfgp[core_num].empty_paged_buf_pool_info.pool_size;
+		if (ret == NSS_FAILURE) {
+			up(&nss_n2h_nepbcfgp[core_num].sem);
+			return -EBUSY;
+		}
+
+		up(&nss_n2h_nepbcfgp[core_num].sem);
+
+		ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+		return ret;
+	}
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret) {
+		up(&nss_n2h_nepbcfgp[core_num].sem);
+		return ret;
+	}
+
+	if ((*new_val < NSS_N2H_MIN_EMPTY_POOL_BUF_SZ)) {
+		nss_warning("%px: core %d setting %d < min number of buffer",
+				nss_ctx, (int)core_num, *new_val);
+		goto failure;
+	}
+
+	nss_info("%px: core %d number of empty paged pool buffer is : %d\n",
+		nss_ctx, (int)core_num, *new_val);
+
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE,
+			NSS_TX_METADATA_TYPE_N2H_EMPTY_PAGED_POOL_BUF_CFG,
+			sizeof(struct nss_n2h_empty_pool_buf),
+			nss_n2h_payload_stats_callback,
+			(nss_ptr_t *)core_num);
+
+	nneppbcm = &nnm.msg.empty_pool_buf_cfg;
+	nneppbcm->pool_size = htonl(*new_val);
+	nss_tx_status = nss_n2h_tx_msg(nss_ctx, &nnm);
+
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: core %d nss_tx error empty paged pool buffer: %d\n",
+				nss_ctx, (int)core_num, *new_val);
+		goto failure;
+	}
+
+	/*
+	 * Blocking call, wait till we get ACK for this msg.
+	 */
+	ret = wait_for_completion_timeout(&nss_n2h_nepbcfgp[core_num].complete,
+			msecs_to_jiffies(NSS_CONN_CFG_TIMEOUT));
+	if (ret == 0) {
+		nss_warning("%px: core %d Waiting for ack timed out\n", nss_ctx, (int)core_num);
+		goto failure;
+	}
+
+	/*
+	 * ACK/NACK received from NSS FW
+	 * If ACK: Callback function will update nss_n2h_empty_pool_buf with
+	 * nss_n2h_nepbcfgp.num_conn_valid, which holds the user input
+	 */
+	if (NSS_FAILURE == nss_n2h_nepbcfgp[core_num].response) {
+		goto failure;
+	}
+
+	up(&nss_n2h_nepbcfgp[core_num].sem);
+	return 0;
+
+failure:
+	/*
+	 * Restore the current_value to its previous state
+	 */
+	*new_val = nss_n2h_nepbcfgp[core_num].empty_paged_buf_pool_info.pool_size;
+	up(&nss_n2h_nepbcfgp[core_num].sem);
+	return NSS_FAILURE;
+}
+
+/*
+ * nss_n2h_set_water_mark()
+ *	Sets water mark for N2H SOS
+ */
+static int nss_n2h_set_water_mark(struct ctl_table *ctl, int write,
+					void __user *buffer,
+					size_t *lenp, loff_t *ppos,
+					uint32_t core_num, int *low, int *high)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[core_num];
+	struct nss_n2h_msg nnm;
+	struct nss_n2h_water_mark *wm;
+	nss_tx_status_t nss_tx_status;
+	int ret = NSS_FAILURE;
+
+	/*
+	 * Acquiring semaphore
+	 */
+	down(&nss_n2h_nepbcfgp[core_num].sem);
+
+	/*
+	 * Take snap shot of current value
+	 */
+	nss_n2h_nepbcfgp[core_num].empty_buf_pool_info.low_water = *low;
+	nss_n2h_nepbcfgp[core_num].empty_buf_pool_info.high_water = *high;
+
+	if (!write || *low == -1 || *high == -1) {
+		ret = nss_n2h_get_default_payload_info(core_num);
+		if (ret == NSS_FAILURE) {
+			up(&nss_n2h_nepbcfgp[core_num].sem);
+			return -EBUSY;
+		}
+
+		*low = nss_n2h_nepbcfgp[core_num].empty_buf_pool_info.low_water;
+		*high = nss_n2h_nepbcfgp[core_num].empty_buf_pool_info.high_water;
+	}
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (!write || ret) {
+		up(&nss_n2h_nepbcfgp[core_num].sem);
+		return ret;
+	}
+
+	if ((*low < NSS_N2H_MIN_EMPTY_POOL_BUF_SZ) ||
+		(*high < NSS_N2H_MIN_EMPTY_POOL_BUF_SZ)) {
+		nss_warning("%px: core %d setting %d, %d < min number of buffer",
+				nss_ctx, core_num, *low, *high);
+		goto failure;
+	}
+
+	if ((*low > NSS_N2H_MAX_EMPTY_POOL_BUF_SZ) ||
+		(*high > NSS_N2H_MAX_EMPTY_POOL_BUF_SZ)) {
+		nss_warning("%px: core %d setting %d, %d is > upper limit",
+				nss_ctx, core_num, *low, *high);
+		goto failure;
+	}
+
+	if (*low > *high) {
+		nss_warning("%px: core %d setting low %d is more than high %d",
+				nss_ctx, core_num, *low, *high);
+		goto failure;
+	}
+
+	nss_info("%px: core %d number of low : %d and high : %d\n",
+		nss_ctx, core_num, *low, *high);
+
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE,
+			NSS_TX_METADATA_TYPE_SET_WATER_MARK,
+			sizeof(struct nss_n2h_water_mark),
+			nss_n2h_payload_stats_callback,
+			(void *)(nss_ptr_t)core_num);
+
+	wm = &nnm.msg.wm;
+	wm->low_water = htonl(*low);
+	wm->high_water = htonl(*high);
+	nss_tx_status = nss_n2h_tx_msg(nss_ctx, &nnm);
+
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: core %d nss_tx error setting : %d, %d\n",
+				nss_ctx, core_num, *low, *high);
+		goto failure;
+	}
+
+	/*
+	 * Blocking call, wait till we get ACK for this msg.
+	 */
+	ret = wait_for_completion_timeout(&nss_n2h_nepbcfgp[core_num].complete,
+			msecs_to_jiffies(NSS_CONN_CFG_TIMEOUT));
+	if (ret == 0) {
+		nss_warning("%px: core %d Waiting for ack timed out\n", nss_ctx,
+			core_num);
+		goto failure;
+	}
+
+	/*
+	 * ACK/NACK received from NSS FW
+	 */
+	if (NSS_FAILURE == nss_n2h_nepbcfgp[core_num].response)
+		goto failure;
+
+	up(&nss_n2h_nepbcfgp[core_num].sem);
+	return NSS_SUCCESS;
+
+failure:
+	/*
+	 * Restore the current_value to its previous state
+	 */
+	*low = nss_n2h_nepbcfgp[core_num].empty_buf_pool_info.low_water;
+	*high = nss_n2h_nepbcfgp[core_num].empty_buf_pool_info.high_water;
+	up(&nss_n2h_nepbcfgp[core_num].sem);
+	return -EINVAL;
+}
+
+/*
+ * nss_n2h_set_paged_water_mark()
+ *	Sets water mark for paged pool N2H SOS
+ */
+static int nss_n2h_set_paged_water_mark(struct ctl_table *ctl, int write,
+					void __user *buffer,
+					size_t *lenp, loff_t *ppos,
+					uint32_t core_num, int *low, int *high)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[core_num];
+	struct nss_n2h_msg nnm;
+	struct nss_n2h_water_mark *pwm;
+	nss_tx_status_t nss_tx_status;
+	int ret = NSS_FAILURE;
+
+	/*
+	 * Acquiring semaphore
+	 */
+	down(&nss_n2h_nepbcfgp[core_num].sem);
+
+	/*
+	 * Take snap shot of current value
+	 */
+	nss_n2h_nepbcfgp[core_num].empty_paged_buf_pool_info.low_water = *low;
+	nss_n2h_nepbcfgp[core_num].empty_paged_buf_pool_info.high_water = *high;
+
+	if (!write || *low == -1 || *high == -1) {
+		ret = nss_n2h_get_paged_payload_info(core_num);
+		if (ret == NSS_FAILURE) {
+			up(&nss_n2h_nepbcfgp[core_num].sem);
+			return -EBUSY;
+		}
+
+		*low = nss_n2h_nepbcfgp[core_num].empty_paged_buf_pool_info.low_water;
+		*high = nss_n2h_nepbcfgp[core_num].empty_paged_buf_pool_info.high_water;
+	}
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (!write || ret) {
+		up(&nss_n2h_nepbcfgp[core_num].sem);
+		return ret;
+	}
+
+	if ((*low < NSS_N2H_MIN_EMPTY_POOL_BUF_SZ) ||
+		(*high < NSS_N2H_MIN_EMPTY_POOL_BUF_SZ)) {
+		nss_warning("%px: core %d setting %d, %d < min number of buffer",
+				nss_ctx, core_num, *low, *high);
+		goto failure;
+	}
+
+	if ((*low > NSS_N2H_MAX_EMPTY_POOL_BUF_SZ) ||
+		(*high > NSS_N2H_MAX_EMPTY_POOL_BUF_SZ)) {
+		nss_warning("%px: core %d setting %d, %d is > upper limit",
+				nss_ctx, core_num, *low, *high);
+		goto failure;
+	}
+
+	if (*low > *high) {
+		nss_warning("%px: core %d setting low %d is more than high %d",
+				nss_ctx, core_num, *low, *high);
+		goto failure;
+	}
+
+	nss_info("%px: core %d number of low : %d and high : %d\n",
+		nss_ctx, core_num, *low, *high);
+
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE,
+			NSS_TX_METADATA_TYPE_SET_PAGED_WATER_MARK,
+			sizeof(struct nss_n2h_water_mark),
+			nss_n2h_payload_stats_callback,
+			(void *)(nss_ptr_t)core_num);
+
+	pwm = &nnm.msg.wm_paged;
+	pwm->low_water = htonl(*low);
+	pwm->high_water = htonl(*high);
+	nss_tx_status = nss_n2h_tx_msg(nss_ctx, &nnm);
+
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: core %d nss_tx error setting : %d, %d\n",
+				nss_ctx, core_num, *low, *high);
+		goto failure;
+	}
+
+	/*
+	 * Blocking call, wait till we get ACK for this msg.
+	 */
+	ret = wait_for_completion_timeout(&nss_n2h_nepbcfgp[core_num].complete,
+			msecs_to_jiffies(NSS_CONN_CFG_TIMEOUT));
+	if (ret == 0) {
+		nss_warning("%px: core %d Waiting for ack timed out\n", nss_ctx,
+			core_num);
+		goto failure;
+	}
+
+	/*
+	 * ACK/NACK received from NSS FW
+	 */
+	if (NSS_FAILURE == nss_n2h_nepbcfgp[core_num].response)
+		goto failure;
+
+	up(&nss_n2h_nepbcfgp[core_num].sem);
+	return NSS_SUCCESS;
+
+failure:
+	/*
+	 * Restore the current_value to its previous state
+	 */
+	*low = nss_n2h_nepbcfgp[core_num].empty_paged_buf_pool_info.low_water;
+	*high = nss_n2h_nepbcfgp[core_num].empty_paged_buf_pool_info.high_water;
+	up(&nss_n2h_nepbcfgp[core_num].sem);
+	return -EINVAL;
+}
+
+/*
+ * nss_n2h_cfg_wifi_pool()
+ *	Sets number of wifi payloads to adjust high water mark for N2H SoS
+ */
+static int nss_n2h_cfg_wifi_pool(struct ctl_table *ctl, int write,
+					void __user *buffer,
+					size_t *lenp, loff_t *ppos,
+					int *payloads)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[0];
+	struct nss_n2h_msg nnm;
+	struct nss_n2h_wifi_payloads *wp;
+	nss_tx_status_t nss_tx_status;
+	int ret = NSS_FAILURE;
+
+	/*
+	 * Acquiring semaphore
+	 */
+	down(&nss_n2h_wp.sem);
+
+	if (!write) {
+		*payloads = nss_n2h_wp.wifi_pool;
+
+		up(&nss_n2h_wp.sem);
+		ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+		return ret;
+	}
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret) {
+		up(&nss_n2h_wp.sem);
+		return ret;
+	}
+
+	/*
+	 * If payloads parameter is not set, we do
+	 * nothing.
+	 */
+	if (*payloads == -1)
+		goto failure;
+
+	if ((*payloads < NSS_N2H_MIN_EMPTY_POOL_BUF_SZ)) {
+		nss_warning("%px: wifi setting %d < min number of buffer",
+				nss_ctx, *payloads);
+		goto failure;
+	}
+
+	if ((*payloads > NSS_N2H_MAX_EMPTY_POOL_BUF_SZ)) {
+		nss_warning("%px: wifi setting %d > max number of buffer",
+				nss_ctx, *payloads);
+		goto failure;
+	}
+
+	nss_info("%px: wifi payloads : %d\n",
+		nss_ctx, *payloads);
+
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE,
+			NSS_TX_METADATA_TYPE_N2H_WIFI_POOL_BUF_CFG,
+			sizeof(struct nss_n2h_wifi_payloads),
+			nss_n2h_set_wifi_payloads_callback,
+			(void *)nss_ctx);
+
+	wp = &nnm.msg.wp;
+	wp->payloads = htonl(*payloads);
+	nss_tx_status = nss_n2h_tx_msg(nss_ctx, &nnm);
+
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: wifi setting %d nss_tx error",
+				nss_ctx, *payloads);
+		goto failure;
+	}
+
+	/*
+	 * Blocking call, wait till we get ACK for this msg.
+	 */
+	ret = wait_for_completion_timeout(&nss_n2h_wp.complete,
+			msecs_to_jiffies(NSS_CONN_CFG_TIMEOUT));
+	if (ret == 0) {
+		nss_warning("%px: Waiting for ack timed out\n", nss_ctx);
+		goto failure;
+	}
+
+	/*
+	 * ACK/NACK received from NSS FW
+	 */
+	if (NSS_FAILURE == nss_n2h_wp.response)
+		goto failure;
+
+	up(&nss_n2h_wp.sem);
+	return NSS_SUCCESS;
+
+failure:
+	up(&nss_n2h_wp.sem);
+	return -EINVAL;
+}
+
+/*
+ * nss_n2h_empty_pool_buf_core1_handler()
+ *	Sets the number of empty buffer for core 1
+ */
+static int nss_n2h_empty_pool_buf_cfg_core1_handler(struct ctl_table *ctl,
+				int write, void __user *buffer,
+				size_t *lenp, loff_t *ppos)
+{
+	return nss_n2h_set_empty_buf_pool(ctl, write, buffer, lenp, ppos,
+			NSS_CORE_1, &nss_n2h_empty_pool_buf_cfg[NSS_CORE_1]);
+}
+
+/*
+ * nss_n2h_empty_pool_buf_core0_handler()
+ *	Sets the number of empty buffer for core 0
+ */
+static int nss_n2h_empty_pool_buf_cfg_core0_handler(struct ctl_table *ctl,
+				int write, void __user *buffer,
+				size_t *lenp, loff_t *ppos)
+{
+	return nss_n2h_set_empty_buf_pool(ctl, write, buffer, lenp, ppos,
+			NSS_CORE_0, &nss_n2h_empty_pool_buf_cfg[NSS_CORE_0]);
+}
+
+/*
+ * nss_n2h_empty_paged_pool_buf_cfg_core1_handler()
+ *	Sets the number of empty paged buffer for core 1
+ */
+static int nss_n2h_empty_paged_pool_buf_cfg_core1_handler(struct ctl_table *ctl,
+				int write, void __user *buffer,
+				size_t *lenp, loff_t *ppos)
+{
+	return nss_n2h_set_empty_paged_pool_buf(ctl, write, buffer, lenp, ppos,
+			NSS_CORE_1, &nss_n2h_empty_paged_pool_buf_cfg[NSS_CORE_1]);
+}
+
+/*
+ * nss_n2h_empty_paged_pool_buf_cfg_core0_handler()
+ *	Sets the number of empty paged buffer for core 0
+ */
+static int nss_n2h_empty_paged_pool_buf_cfg_core0_handler(struct ctl_table *ctl,
+				int write, void __user *buffer,
+				size_t *lenp, loff_t *ppos)
+{
+	return nss_n2h_set_empty_paged_pool_buf(ctl, write, buffer, lenp, ppos,
+			NSS_CORE_0, &nss_n2h_empty_paged_pool_buf_cfg[NSS_CORE_0]);
+}
+
+/*
+ * nss_n2h_water_mark_core1_handler()
+ *	Sets water mark for core 1
+ */
+static int nss_n2h_water_mark_core1_handler(struct ctl_table *ctl,
+			int write, void __user *buffer,
+			size_t *lenp, loff_t *ppos)
+{
+	return nss_n2h_set_water_mark(ctl, write, buffer, lenp, ppos,
+			NSS_CORE_1, &nss_n2h_water_mark[NSS_CORE_1][0],
+			&nss_n2h_water_mark[NSS_CORE_1][1]);
+}
+
+/*
+ * nss_n2h_water_mark_core0_handler()
+ *	Sets water mark for core 0
+ */
+static int nss_n2h_water_mark_core0_handler(struct ctl_table *ctl,
+			int write, void __user *buffer,
+			size_t *lenp, loff_t *ppos)
+{
+	return nss_n2h_set_water_mark(ctl, write, buffer, lenp, ppos,
+			NSS_CORE_0, &nss_n2h_water_mark[NSS_CORE_0][0],
+			&nss_n2h_water_mark[NSS_CORE_0][1]);
+}
+
+/*
+ * nss_n2h_paged_water_mark_core1_handler()
+ *	Sets paged water mark for core 1
+ */
+static int nss_n2h_paged_water_mark_core1_handler(struct ctl_table *ctl,
+			int write, void __user *buffer,
+			size_t *lenp, loff_t *ppos)
+{
+	return nss_n2h_set_paged_water_mark(ctl, write, buffer, lenp, ppos,
+			NSS_CORE_1, &nss_n2h_paged_water_mark[NSS_CORE_1][0],
+			&nss_n2h_paged_water_mark[NSS_CORE_1][1]);
+}
+
+/*
+ * nss_n2h_paged_water_mark_core0_handler()
+ *	Sets paged water mark for core 0
+ */
+static int nss_n2h_paged_water_mark_core0_handler(struct ctl_table *ctl,
+			int write, void __user *buffer,
+			size_t *lenp, loff_t *ppos)
+{
+	return nss_n2h_set_paged_water_mark(ctl, write, buffer, lenp, ppos,
+			NSS_CORE_0, &nss_n2h_paged_water_mark[NSS_CORE_0][0],
+			&nss_n2h_paged_water_mark[NSS_CORE_0][1]);
+}
+
+/*
+ * nss_n2h_wifi_payloads_handler()
+ *	Sets number of wifi payloads
+ */
+static int nss_n2h_wifi_payloads_handler(struct ctl_table *ctl,
+			int write, void __user *buffer,
+			size_t *lenp, loff_t *ppos)
+{
+	return nss_n2h_cfg_wifi_pool(ctl, write, buffer, lenp, ppos,
+			&nss_n2h_wifi_pool_buf_cfg);
+}
+
+/*
+ * nss_n2h_update_queue_config_callback()
+ *	Callback to handle the completion of queue config command
+ */
+static void nss_n2h_update_queue_config_callback(void *app_data, struct nss_n2h_msg *nim)
+{
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("n2h Error response %d\n", nim->cm.response);
+		nss_n2h_q_cfg_pvt.response = NSS_TX_FAILURE;
+	} else {
+		nss_n2h_q_cfg_pvt.response = NSS_TX_SUCCESS;
+	}
+
+	complete(&nss_n2h_q_cfg_pvt.complete);
+}
+
+/*
+ * nss_n2h_update_queue_config_async()
+ *	Asynchronous call to send pnode queue configuration.
+ */
+nss_tx_status_t nss_n2h_update_queue_config_async(struct nss_ctx_instance *nss_ctx, bool mq_en, uint16_t *qlimits)
+{
+
+	struct nss_n2h_msg nnm;
+	struct nss_n2h_pnode_queue_config *cfg;
+	nss_tx_status_t status;
+	int i;
+
+	if (!mq_en) {
+		return NSS_TX_SUCCESS;
+	}
+
+	/*
+	 * MQ mode doesnot make any sense if number of priority queues in NSS
+	 * is 1
+	 */
+	if (NSS_MAX_NUM_PRI <= 1) {
+		return NSS_TX_SUCCESS;
+	}
+
+	memset(&nnm, 0, sizeof(struct nss_n2h_msg));
+
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE,
+			 NSS_TX_METADATA_TYPE_N2H_SET_PNODE_QUEUE_CFG,
+			 sizeof(struct nss_n2h_pnode_queue_config), NULL, 0);
+
+	cfg = &nnm.msg.pn_q_cfg;
+
+	/*
+	 * Update limits
+	 */
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		cfg->qlimits[i] = qlimits[i];
+	}
+	cfg->mq_en = true;
+
+	status = nss_n2h_tx_msg(nss_ctx, &nnm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_tx error to send pnode queue config\n", nss_ctx);
+		return status;
+	}
+
+	return NSS_TX_SUCCESS;
+}
+EXPORT_SYMBOL(nss_n2h_update_queue_config_async);
+
+/*
+ * nss_n2h_update_queue_config_sync()
+ *	Synchronous call to send pnode queue configuration.
+ */
+nss_tx_status_t nss_n2h_update_queue_config_sync(struct nss_ctx_instance *nss_ctx, bool mq_en, uint16_t *qlimits)
+{
+
+	struct nss_n2h_msg nnm;
+	struct nss_n2h_pnode_queue_config *cfg;
+	nss_tx_status_t status;
+	int ret, i;
+
+	if (!mq_en) {
+		return NSS_TX_SUCCESS;
+	}
+
+	/*
+	 * MQ mode doesnot make any sense if number of priority queues in NSS
+	 * is 1
+	 */
+	if (NSS_MAX_NUM_PRI <= 1) {
+		return NSS_TX_SUCCESS;
+	}
+
+	memset(&nnm, 0, sizeof(struct nss_n2h_msg));
+
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE,
+			 NSS_TX_METADATA_TYPE_N2H_SET_PNODE_QUEUE_CFG,
+			 sizeof(struct nss_n2h_pnode_queue_config), nss_n2h_update_queue_config_callback, 0);
+
+	cfg = &nnm.msg.pn_q_cfg;
+
+	/*
+	 * Update limits
+	 */
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		cfg->qlimits[i] = qlimits[i];
+	}
+	cfg->mq_en = true;
+
+	down(&nss_n2h_q_cfg_pvt.sem);
+
+	status = nss_n2h_tx_msg(nss_ctx, &nnm);
+
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: n2h_tx_msg failed\n", nss_ctx);
+		up(&nss_n2h_q_cfg_pvt.sem);
+		return status;
+	}
+	ret = wait_for_completion_timeout(&nss_n2h_q_cfg_pvt.complete, msecs_to_jiffies(NSS_N2H_TX_TIMEOUT));
+
+	if (!ret) {
+		nss_warning("%px: Timeout expired for pnode queue config sync message\n", nss_ctx);
+		nss_n2h_q_cfg_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = nss_n2h_q_cfg_pvt.response;
+	up(&nss_n2h_q_cfg_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_n2h_update_queue_config_sync);
+
+/*
+ * nss_n2h_mitigation_cfg()
+ *	Send Message to NSS to disable MITIGATION.
+ */
+static nss_tx_status_t nss_n2h_mitigation_cfg(struct nss_ctx_instance *nss_ctx, int enable_mitigation, nss_core_id_t core_num)
+{
+	struct nss_n2h_msg nnm;
+	struct nss_n2h_mitigation *mitigation_cfg;
+	nss_tx_status_t nss_tx_status;
+	int ret;
+
+	nss_assert(core_num < NSS_CORE_MAX);
+
+	down(&nss_n2h_mitigationcp[core_num].sem);
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE, NSS_TX_METADATA_TYPE_N2H_MITIGATION_CFG,
+			sizeof(struct nss_n2h_mitigation),
+			nss_n2h_mitigation_cfg_callback,
+			(void *)core_num);
+
+	mitigation_cfg = &nnm.msg.mitigation_cfg;
+	mitigation_cfg->enable = enable_mitigation;
+
+	nss_tx_status = nss_n2h_tx_msg(nss_ctx, &nnm);
+
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_tx error setting mitigation\n", nss_ctx);
+		goto failure;
+	}
+
+	/*
+	 * Blocking call, wait till we get ACK for this msg.
+	 */
+	ret = wait_for_completion_timeout(&nss_n2h_mitigationcp[core_num].complete, msecs_to_jiffies(NSS_CONN_CFG_TIMEOUT));
+	if (ret == 0) {
+		nss_warning("%px: Waiting for ack timed out\n", nss_ctx);
+		goto failure;
+	}
+
+	/*
+	 * ACK/NACK received from NSS FW
+	 */
+	if (NSS_FAILURE == nss_n2h_mitigationcp[core_num].response) {
+		goto failure;
+	}
+
+	up(&nss_n2h_mitigationcp[core_num].sem);
+	return NSS_SUCCESS;
+
+failure:
+	up(&nss_n2h_mitigationcp[core_num].sem);
+	return NSS_FAILURE;
+}
+
+static inline void nss_n2h_buf_pool_free(struct nss_n2h_buf_pool *buf_pool)
+{
+	int page_count;
+	for (page_count = 0; page_count < buf_pool->nss_buf_num_pages; page_count++) {
+		kfree((void *)buf_pool->nss_buf_pool_vaddr[page_count]);
+	}
+}
+
+/*
+ * nss_n2h_buf_cfg()
+ *	Send Message to NSS to enable pbufs.
+ */
+static nss_tx_status_t nss_n2h_buf_pool_cfg(struct nss_ctx_instance *nss_ctx,
+					int buf_pool_size, nss_core_id_t core_num)
+{
+	static struct nss_n2h_msg nnm;
+	struct nss_n2h_buf_pool *buf_pool;
+	nss_tx_status_t nss_tx_status;
+	int ret;
+	int page_count;
+	int num_pages = ALIGN(buf_pool_size, PAGE_SIZE)/PAGE_SIZE;
+
+	nss_assert(core_num < NSS_CORE_MAX);
+
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE, NSS_METADATA_TYPE_N2H_ADD_BUF_POOL,
+			sizeof(struct nss_n2h_buf_pool),
+			nss_n2h_bufs_cfg_callback,
+			(void *)core_num);
+
+	do {
+
+		down(&nss_n2h_bufcp[core_num].sem);
+
+		buf_pool = &nnm.msg.buf_pool;
+		buf_pool->nss_buf_page_size = PAGE_SIZE;
+
+		for (page_count = 0; page_count < MAX_PAGES_PER_MSG && num_pages; page_count++, num_pages--) {
+			void *kern_addr = kzalloc(PAGE_SIZE, GFP_ATOMIC);
+			if (!kern_addr) {
+				BUG_ON(!page_count);
+				break;
+			}
+
+			kmemleak_not_leak(kern_addr);
+			buf_pool->nss_buf_pool_vaddr[page_count] = (nss_ptr_t)kern_addr;
+			buf_pool->nss_buf_pool_addr[page_count] = dma_map_single(nss_ctx->dev, kern_addr, PAGE_SIZE, DMA_TO_DEVICE);
+		}
+
+		buf_pool->nss_buf_num_pages = page_count;
+		nss_tx_status = nss_n2h_tx_msg(nss_ctx, &nnm);
+		if (nss_tx_status != NSS_TX_SUCCESS) {
+
+			nss_n2h_buf_pool_free(buf_pool);
+			nss_warning("%px: nss_tx error setting pbuf\n", nss_ctx);
+			goto failure;
+		}
+
+		/*
+		 * Blocking call, wait till we get ACK for this msg.
+		 */
+		ret = wait_for_completion_timeout(&nss_n2h_bufcp[core_num].complete, msecs_to_jiffies(NSS_CONN_CFG_TIMEOUT));
+		if (ret == 0) {
+			nss_warning("%px: Waiting for ack timed out\n", nss_ctx);
+			goto failure;
+		}
+
+		/*
+		 * ACK/NACK received from NSS FW
+		 */
+		if (NSS_FAILURE == nss_n2h_bufcp[core_num].response) {
+
+			nss_n2h_buf_pool_free(buf_pool);
+			goto failure;
+		}
+
+		up(&nss_n2h_bufcp[core_num].sem);
+	} while(num_pages);
+
+	return NSS_SUCCESS;
+failure:
+	up(&nss_n2h_bufcp[core_num].sem);
+	return NSS_FAILURE;
+}
+
+/*
+ * nss_mitigation_handler()
+ * Enable NSS MITIGATION
+ */
+static int nss_n2h_mitigationcfg_core0_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[NSS_CORE_0];
+	int ret;
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret) {
+		return ret;
+	}
+
+	/*
+	 * It's a read operation
+	 */
+	if (!write) {
+		return ret;
+	}
+
+	if (!nss_n2h_core0_mitigation_cfg) {
+		printk(KERN_INFO "Disabling NSS MITIGATION\n");
+		nss_n2h_mitigation_cfg(nss_ctx, 0, NSS_CORE_0);
+		return 0;
+	}
+	printk(KERN_INFO "Invalid input value.Valid value is 0, Runtime re-enabling not supported\n");
+	return -EINVAL;
+}
+
+/*
+ * nss_mitigation_handler()
+ * Enable NSS MITIGATION
+ */
+static int nss_n2h_mitigationcfg_core1_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[NSS_CORE_1];
+	int ret;
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret) {
+		return ret;
+	}
+
+	/*
+	 * It's a read operation
+	 */
+	if (!write) {
+		return ret;
+	}
+
+	if (!nss_n2h_core1_mitigation_cfg) {
+		printk(KERN_INFO "Disabling NSS MITIGATION\n");
+		nss_n2h_mitigation_cfg(nss_ctx, 0, NSS_CORE_1);
+		return 0;
+	}
+	printk(KERN_INFO "Invalid input value.Valid value is 0, Runtime re-enabling not supported\n");
+	return -EINVAL;
+}
+
+/*
+ * nss_buf_handler()
+ *	Add extra NSS bufs from host memory
+ */
+static int nss_n2h_buf_cfg_core0_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[NSS_CORE_0];
+	int ret;
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret) {
+		return ret;
+	}
+
+	/*
+	 * It's a read operation
+	 */
+	if (!write) {
+		return ret;
+	}
+
+	if (nss_ctx->buf_sz_allocated) {
+		nss_n2h_core0_add_buf_pool_size = nss_ctx->buf_sz_allocated;
+		return -EPERM;
+	}
+
+	if ((nss_n2h_core0_add_buf_pool_size >= 1) && (nss_n2h_core0_add_buf_pool_size <= NSS_N2H_MAX_BUF_POOL_SIZE)) {
+		printk(KERN_INFO "configuring additional NSS pbufs\n");
+		ret = nss_n2h_buf_pool_cfg(nss_ctx, nss_n2h_core0_add_buf_pool_size, NSS_CORE_0);
+		nss_n2h_core0_add_buf_pool_size = nss_ctx->buf_sz_allocated;
+		printk(KERN_INFO "additional pbufs of size %d got added to NSS\n", nss_ctx->buf_sz_allocated);
+		return ret;
+	}
+
+	printk(KERN_INFO "Invalid input value. should be greater than 1 and less than %d\n", NSS_N2H_MAX_BUF_POOL_SIZE);
+	return -EINVAL;
+}
+
+/*
+ * nss_n2h_buf_handler()
+ *	Add extra NSS bufs from host memory
+ */
+static int nss_n2h_buf_cfg_core1_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[NSS_CORE_1];
+	int ret;
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret) {
+		return ret;
+	}
+
+	/*
+	 * It's a read operation
+	 */
+	if (!write) {
+		return ret;
+	}
+
+	if (nss_ctx->buf_sz_allocated) {
+		nss_n2h_core1_add_buf_pool_size = nss_ctx->buf_sz_allocated;
+		return -EPERM;
+	}
+
+	if ((nss_n2h_core1_add_buf_pool_size >= 1) && (nss_n2h_core1_add_buf_pool_size <= NSS_N2H_MAX_BUF_POOL_SIZE)) {
+		printk(KERN_INFO "configuring additional NSS pbufs\n");
+		ret = nss_n2h_buf_pool_cfg(nss_ctx, nss_n2h_core1_add_buf_pool_size, NSS_CORE_1);
+		nss_n2h_core1_add_buf_pool_size = nss_ctx->buf_sz_allocated;
+		printk(KERN_INFO "additional pbufs of size %d got added to NSS\n", nss_ctx->buf_sz_allocated);
+		return ret;
+	}
+
+	printk(KERN_INFO "Invalid input value. should be greater than 1 and less than %d\n", NSS_N2H_MAX_BUF_POOL_SIZE);
+	return -EINVAL;
+}
+
+/*
+ * nss_n2h_queue_limit_callback()
+ *	Callback to handle the completion of queue limit command.
+ */
+static void nss_n2h_queue_limit_callback(void *app_data, struct nss_n2h_msg *nim)
+{
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("n2h error response %d\n", nim->cm.response);
+	}
+
+	nss_n2h_q_lim_pvt.response = nim->cm.response;
+	complete(&nss_n2h_q_lim_pvt.complete);
+}
+
+/*
+ * nss_n2h_set_queue_limit_sync()
+ *	Sets the n2h queue size limit synchronously.
+ */
+static int nss_n2h_set_queue_limit_sync(struct ctl_table *ctl, int write, void __user *buffer,
+					size_t *lenp, loff_t *ppos, uint32_t core_id)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[core_id];
+	struct nss_n2h_msg nim;
+	struct nss_n2h_queue_limit_config *nnqlc = NULL;
+	int ret, current_val;
+	nss_tx_status_t nss_tx_status;
+
+	/*
+	 * Take a snap shot of current value
+	 */
+	current_val = nss_n2h_queue_limit[core_id];
+
+	/*
+	 * Write the variable with user input
+	 */
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret || (!write)) {
+		return ret;
+	}
+
+	/*
+	 * We dont allow shortening of the queue size at run-time
+	 */
+	if (nss_n2h_queue_limit[core_id] < current_val) {
+		nss_warning("%px: New queue limit %d less than previous value %d. Cant allow shortening\n",
+				nss_ctx, nss_n2h_queue_limit[core_id], current_val);
+		nss_n2h_queue_limit[core_id] = current_val;
+		return NSS_TX_FAILURE;
+	}
+
+	memset(&nim, 0, sizeof(struct nss_n2h_msg));
+	nss_n2h_msg_init(&nim, NSS_N2H_INTERFACE,
+			NSS_TX_METADATA_TYPE_N2H_QUEUE_LIMIT_CFG,
+			sizeof(struct nss_n2h_queue_limit_config), nss_n2h_queue_limit_callback, NULL);
+
+	nnqlc = &nim.msg.ql_cfg;
+	nnqlc->qlimit = nss_n2h_queue_limit[core_id];
+
+	/*
+	 * Send synchronous message to firmware
+	 */
+	down(&nss_n2h_q_lim_pvt.sem);
+
+	nss_tx_status = nss_n2h_tx_msg(nss_ctx, &nim);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: n2h queue limit message send failed\n", nss_ctx);
+		nss_n2h_queue_limit[core_id] = current_val;
+		up(&nss_n2h_q_lim_pvt.sem);
+		return nss_tx_status;
+	}
+
+	ret = wait_for_completion_timeout(&nss_n2h_q_lim_pvt.complete, msecs_to_jiffies(NSS_N2H_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: Timeout expired for queue limit sync message\n", nss_ctx);
+		nss_n2h_queue_limit[core_id] = current_val;
+		up(&nss_n2h_q_lim_pvt.sem);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * If setting the queue limit failed, reset the value to original value
+	 */
+	if (nss_n2h_q_lim_pvt.response != NSS_CMN_RESPONSE_ACK) {
+		nss_n2h_queue_limit[core_id] = current_val;
+	}
+
+	up(&nss_n2h_q_lim_pvt.sem);
+	return NSS_TX_SUCCESS;
+}
+
+/*
+ * nss_n2h_queue_limit_core0_handler()
+ *	Sets the n2h queue size limit for core0
+ */
+static int nss_n2h_queue_limit_core0_handler(struct ctl_table *ctl,
+				int write, void __user *buffer,
+				size_t *lenp, loff_t *ppos)
+{
+	return nss_n2h_set_queue_limit_sync(ctl, write, buffer, lenp, ppos,
+			NSS_CORE_0);
+}
+
+/*
+ * nss_n2h_queue_limit_core1_handler()
+ *	Sets the n2h queue size limit for core1
+ */
+static int nss_n2h_queue_limit_core1_handler(struct ctl_table *ctl,
+				int write, void __user *buffer,
+				size_t *lenp, loff_t *ppos)
+{
+	return nss_n2h_set_queue_limit_sync(ctl, write, buffer, lenp, ppos,
+			NSS_CORE_1);
+}
+
+/*
+ * nss_n2h_host_bp_cfg_callback()
+ *	Callback function for back pressure configuration.
+ */
+static void nss_n2h_host_bp_cfg_callback(void *app_data, struct nss_n2h_msg *nnm)
+{
+	struct nss_ctx_instance *nss_ctx __maybe_unused = (struct nss_ctx_instance *)app_data;
+	if (nnm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_n2h_host_bp_cfg_pvt.response = NSS_FAILURE;
+		complete(&nss_n2h_host_bp_cfg_pvt.complete);
+		nss_warning("%px: n2h back pressure configuration failed : %d\n", nss_ctx, nnm->cm.error);
+		return;
+	}
+
+	nss_info("%px: n2h back pressure configuration succeeded: %d\n", nss_ctx, nnm->cm.error);
+	nss_n2h_host_bp_cfg_pvt.response = NSS_SUCCESS;
+	complete(&nss_n2h_host_bp_cfg_pvt.complete);
+}
+
+/*
+ * nss_n2h_host_bp_cfg()
+ *	Send Message to n2h to enable back pressure.
+ */
+static nss_tx_status_t nss_n2h_host_bp_cfg_sync(struct nss_ctx_instance *nss_ctx, int enable_bp)
+{
+	struct nss_n2h_msg nnm;
+	nss_tx_status_t nss_tx_status;
+	int ret;
+
+	down(&nss_n2h_host_bp_cfg_pvt.sem);
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE, NSS_TX_METADATA_TYPE_N2H_HOST_BACK_PRESSURE_CFG,
+			sizeof(struct nss_n2h_host_back_pressure),
+			nss_n2h_host_bp_cfg_callback,
+			(void *)nss_ctx);
+
+	nnm.msg.host_bp_cfg.enable = enable_bp;
+
+	nss_tx_status = nss_n2h_tx_msg(nss_ctx, &nnm);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_tx error setting back pressure\n", nss_ctx);
+		up(&nss_n2h_host_bp_cfg_pvt.sem);
+		return NSS_FAILURE;
+	}
+
+	/*
+	 * Blocking call, wait till we get ACK for this msg.
+	 */
+	ret = wait_for_completion_timeout(&nss_n2h_host_bp_cfg_pvt.complete, msecs_to_jiffies(NSS_CONN_CFG_TIMEOUT));
+	if (ret == 0) {
+		nss_warning("%px: Waiting for ack timed out\n", nss_ctx);
+		up(&nss_n2h_host_bp_cfg_pvt.sem);
+		return NSS_FAILURE;
+	}
+
+	/*
+	 * Response received from NSS FW
+	 */
+	if (nss_n2h_host_bp_cfg_pvt.response == NSS_FAILURE) {
+		up(&nss_n2h_host_bp_cfg_pvt.sem);
+		return NSS_FAILURE;
+	}
+
+	up(&nss_n2h_host_bp_cfg_pvt.sem);
+	return NSS_SUCCESS;
+}
+
+/*
+ * nss_n2h_host_bp_cfg_handler()
+ *	Enable n2h back pressure.
+ */
+static int nss_n2h_host_bp_cfg_handler(struct ctl_table *ctl, int write,
+				void __user *buffer, size_t *lenp, loff_t *ppos, uint32_t core_id)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[core_id];
+	int ret, ret_bp, current_state;
+	current_state = nss_n2h_host_bp_config[core_id];
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+
+	if (ret != NSS_SUCCESS) {
+		return ret;
+	}
+
+	if (!write) {
+		return ret;
+	}
+
+	if ((nss_n2h_host_bp_config[core_id] != 0) && (nss_n2h_host_bp_config[core_id] != 1)) {
+		nss_info_always("Invalid input value. Valid values are 0 and 1\n");
+		nss_n2h_host_bp_config[core_id] = current_state;
+		return ret;
+	}
+
+	nss_info("Configuring n2h back pressure\n");
+	ret_bp = nss_n2h_host_bp_cfg_sync(nss_ctx, nss_n2h_host_bp_config[core_id]);
+
+	if (ret_bp != NSS_SUCCESS) {
+		nss_warning("%px: n2h back pressure config failed\n", nss_ctx);
+		nss_n2h_host_bp_config[core_id] = current_state;
+	}
+
+	return ret_bp;
+}
+
+/*
+ * nss_n2h_host_bp_cfg_core0_handler()
+ *	Enable n2h back pressure in core 0.
+ */
+static int nss_n2h_host_bp_cfg_core0_handler(struct ctl_table *ctl, int write,
+				void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	return nss_n2h_host_bp_cfg_handler(ctl, write, buffer, lenp, ppos, NSS_CORE_0);
+}
+
+/*
+ * nss_n2h_host_bp_cfg_core1_handler()
+ *	Enable n2h back pressure in core 1.
+ */
+static int nss_n2h_host_bp_cfg_core1_handler(struct ctl_table *ctl, int write,
+				void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	return nss_n2h_host_bp_cfg_handler(ctl, write, buffer, lenp, ppos, NSS_CORE_1);
+}
+
+static struct ctl_table nss_n2h_table_single_core[] = {
+	{
+		.procname	= "n2h_empty_pool_buf_core0",
+		.data		= &nss_n2h_empty_pool_buf_cfg[NSS_CORE_0],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_empty_pool_buf_cfg_core0_handler,
+	},
+	{
+		.procname	= "n2h_empty_paged_pool_buf_core0",
+		.data		= &nss_n2h_empty_paged_pool_buf_cfg[NSS_CORE_0],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_empty_paged_pool_buf_cfg_core0_handler,
+	},
+	{
+		.procname	= "n2h_low_water_core0",
+		.data		= &nss_n2h_water_mark[NSS_CORE_0][0],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_water_mark_core0_handler,
+	},
+	{
+		.procname	= "n2h_high_water_core0",
+		.data		= &nss_n2h_water_mark[NSS_CORE_0][1],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_water_mark_core0_handler,
+	},
+	{
+		.procname	= "n2h_paged_low_water_core0",
+		.data		= &nss_n2h_paged_water_mark[NSS_CORE_0][0],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_paged_water_mark_core0_handler,
+	},
+	{
+		.procname	= "n2h_paged_high_water_core0",
+		.data		= &nss_n2h_paged_water_mark[NSS_CORE_0][1],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_paged_water_mark_core0_handler,
+	},
+	{
+		.procname	= "n2h_wifi_pool_buf",
+		.data		= &nss_n2h_wifi_pool_buf_cfg,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_wifi_payloads_handler,
+	},
+	{
+		.procname	= "mitigation_core0",
+		.data		= &nss_n2h_core0_mitigation_cfg,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_mitigationcfg_core0_handler,
+	},
+	{
+		.procname	= "extra_pbuf_core0",
+		.data		= &nss_n2h_core0_add_buf_pool_size,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_buf_cfg_core0_handler,
+	},
+	{
+		.procname	= "n2h_queue_limit_core0",
+		.data		= &nss_n2h_queue_limit[NSS_CORE_0],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_queue_limit_core0_handler,
+	},
+	{
+		.procname	= "host_bp_enable0",
+		.data		= &nss_n2h_host_bp_config[NSS_CORE_0],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_host_bp_cfg_core0_handler,
+	},
+
+	{ }
+};
+
+static struct ctl_table nss_n2h_table_multi_core[] = {
+	{
+		.procname	= "n2h_empty_pool_buf_core0",
+		.data		= &nss_n2h_empty_pool_buf_cfg[NSS_CORE_0],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_empty_pool_buf_cfg_core0_handler,
+	},
+	{
+		.procname	= "n2h_empty_pool_buf_core1",
+		.data		= &nss_n2h_empty_pool_buf_cfg[NSS_CORE_1],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_empty_pool_buf_cfg_core1_handler,
+	},
+	{
+		.procname	= "n2h_empty_paged_pool_buf_core0",
+		.data		= &nss_n2h_empty_paged_pool_buf_cfg[NSS_CORE_0],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_empty_paged_pool_buf_cfg_core0_handler,
+	},
+	{
+		.procname	= "n2h_empty_paged_pool_buf_core1",
+		.data		= &nss_n2h_empty_paged_pool_buf_cfg[NSS_CORE_1],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_empty_paged_pool_buf_cfg_core1_handler,
+	},
+
+	{
+		.procname	= "n2h_low_water_core0",
+		.data		= &nss_n2h_water_mark[NSS_CORE_0][0],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_water_mark_core0_handler,
+	},
+	{
+		.procname	= "n2h_low_water_core1",
+		.data		= &nss_n2h_water_mark[NSS_CORE_1][0],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_water_mark_core1_handler,
+	},
+	{
+		.procname	= "n2h_high_water_core0",
+		.data		= &nss_n2h_water_mark[NSS_CORE_0][1],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_water_mark_core0_handler,
+	},
+	{
+		.procname	= "n2h_high_water_core1",
+		.data		= &nss_n2h_water_mark[NSS_CORE_1][1],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_water_mark_core1_handler,
+	},
+	{
+		.procname	= "n2h_paged_low_water_core0",
+		.data		= &nss_n2h_paged_water_mark[NSS_CORE_0][0],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_paged_water_mark_core0_handler,
+	},
+	{
+		.procname	= "n2h_paged_low_water_core1",
+		.data		= &nss_n2h_paged_water_mark[NSS_CORE_1][0],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_paged_water_mark_core1_handler,
+	},
+	{
+		.procname	= "n2h_paged_high_water_core0",
+		.data		= &nss_n2h_paged_water_mark[NSS_CORE_0][1],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_paged_water_mark_core0_handler,
+	},
+	{
+		.procname	= "n2h_paged_high_water_core1",
+		.data		= &nss_n2h_paged_water_mark[NSS_CORE_1][1],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_paged_water_mark_core1_handler,
+	},
+	{
+		.procname	= "n2h_wifi_pool_buf",
+		.data		= &nss_n2h_wifi_pool_buf_cfg,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_wifi_payloads_handler,
+	},
+	{
+		.procname	= "mitigation_core0",
+		.data		= &nss_n2h_core0_mitigation_cfg,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_mitigationcfg_core0_handler,
+	},
+	{
+		.procname	= "mitigation_core1",
+		.data		= &nss_n2h_core1_mitigation_cfg,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_mitigationcfg_core1_handler,
+	},
+	{
+		.procname	= "extra_pbuf_core0",
+		.data		= &nss_n2h_core0_add_buf_pool_size,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_buf_cfg_core0_handler,
+	},
+	{
+		.procname	= "extra_pbuf_core1",
+		.data		= &nss_n2h_core1_add_buf_pool_size,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_buf_cfg_core1_handler,
+	},
+	{
+		.procname	= "n2h_queue_limit_core0",
+		.data		= &nss_n2h_queue_limit[NSS_CORE_0],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_queue_limit_core0_handler,
+	},
+	{
+		.procname	= "n2h_queue_limit_core1",
+		.data		= &nss_n2h_queue_limit[NSS_CORE_1],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_queue_limit_core1_handler,
+	},
+	{
+		.procname	= "host_bp_enable0",
+		.data		= &nss_n2h_host_bp_config[NSS_CORE_0],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_host_bp_cfg_core0_handler,
+	},
+	{
+		.procname	= "host_bp_enable1",
+		.data		= &nss_n2h_host_bp_config[NSS_CORE_1],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_n2h_host_bp_cfg_core1_handler,
+	},
+	{ }
+};
+
+/*
+ * This table will be overwritten during single-core registration
+ */
+static struct ctl_table nss_n2h_dir[] = {
+	{
+		.procname		= "n2hcfg",
+		.mode			= 0555,
+		.child			= nss_n2h_table_multi_core,
+	},
+	{ }
+};
+
+static struct ctl_table nss_n2h_root_dir[] = {
+	{
+		.procname		= "nss",
+		.mode			= 0555,
+		.child			= nss_n2h_dir,
+	},
+	{ }
+};
+
+static struct ctl_table nss_n2h_root[] = {
+	{
+		.procname		= "dev",
+		.mode			= 0555,
+		.child			= nss_n2h_root_dir,
+	},
+	{ }
+};
+
+static struct ctl_table_header *nss_n2h_header;
+
+/*
+ * nss_n2h_cfg_empty_pool_size()
+ *	Config empty buffer pool
+ */
+nss_tx_status_t nss_n2h_cfg_empty_pool_size(struct nss_ctx_instance *nss_ctx, uint32_t pool_sz)
+{
+	struct nss_n2h_msg nnm;
+	struct nss_n2h_empty_pool_buf *nnepbcm;
+	nss_tx_status_t nss_tx_status;
+
+	if (pool_sz < NSS_N2H_MIN_EMPTY_POOL_BUF_SZ) {
+		nss_warning("%px: setting pool size %d < min number of buffer",
+				nss_ctx, pool_sz);
+		return NSS_TX_FAILURE;
+	}
+
+	if (pool_sz > NSS_N2H_MAX_EMPTY_POOL_BUF_SZ) {
+		nss_warning("%px: setting pool size %d > max number of buffer",
+				nss_ctx, pool_sz);
+		return NSS_TX_FAILURE;
+	}
+
+	nss_info("%px: update number of empty buffer pool size: %d\n",
+		nss_ctx, pool_sz);
+
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE,
+			NSS_TX_METADATA_TYPE_N2H_EMPTY_POOL_BUF_CFG,
+			sizeof(struct nss_n2h_empty_pool_buf), NULL, 0);
+
+	nnepbcm = &nnm.msg.empty_pool_buf_cfg;
+	nnepbcm->pool_size = htonl(pool_sz);
+	nss_tx_status = nss_n2h_tx_msg(nss_ctx, &nnm);
+
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_tx error empty buffer pool: %d\n", nss_ctx, pool_sz);
+		return nss_tx_status;
+	}
+
+	return nss_tx_status;
+}
+
+/*
+ * nss_n2h_paged_buf_pool_init()
+ *	Sends a command down to NSS to initialize paged buffer pool
+ */
+nss_tx_status_t nss_n2h_paged_buf_pool_init(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_n2h_msg nnm;
+	nss_tx_status_t nss_tx_status;
+
+	/*
+	 * No additional information needed at this point
+	 */
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE,
+			NSS_TX_METADATA_TYPE_N2H_PAGED_BUFFER_POOL_INIT,
+			sizeof(struct nss_n2h_paged_buffer_pool_init),
+			NULL,
+			NULL);
+
+	nss_tx_status = nss_n2h_tx_msg(nss_ctx, &nnm);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: failed to send paged buf configuration init command to NSS\n",
+				nss_ctx);
+		return NSS_TX_FAILURE;
+	}
+
+	return NSS_TX_SUCCESS;
+}
+
+/*
+ * nss_n2h_flush_payloads()
+ *	Sends a command down to NSS for flushing all payloads
+ */
+nss_tx_status_t nss_n2h_flush_payloads(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_n2h_msg nnm;
+	struct nss_n2h_flush_payloads *nnflshpl;
+	nss_tx_status_t nss_tx_status;
+
+	nnflshpl = &nnm.msg.flush_payloads;
+
+	/*
+	 * TODO: No additional information sent in message
+	 * as of now. Need to initialize message content accordingly
+	 * if needed.
+	 */
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE,
+			NSS_TX_METADATA_TYPE_N2H_FLUSH_PAYLOADS,
+			sizeof(struct nss_n2h_flush_payloads),
+			NULL,
+			NULL);
+
+	nss_tx_status = nss_n2h_tx_msg(nss_ctx, &nnm);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: failed to send flush payloads command to NSS\n",
+				nss_ctx);
+
+		return NSS_TX_FAILURE;
+	}
+
+	return NSS_TX_SUCCESS;
+}
+
+/*
+ * nss_n2h_msg_init()
+ *	Initialize n2h message.
+ */
+void nss_n2h_msg_init(struct nss_n2h_msg *nim, uint16_t if_num, uint32_t type,
+		      uint32_t len, nss_n2h_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&nim->cm, if_num, type, len, (void *)cb, app_data);
+}
+
+/*
+ * nss_n2h_tx_msg()
+ *	Send messages to NSS n2h package.
+ */
+nss_tx_status_t nss_n2h_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_n2h_msg *nnm)
+{
+	struct nss_cmn_msg *ncm = &nnm->cm;
+
+	/*
+	 * Sanity check the message
+	 */
+	if (ncm->interface != NSS_N2H_INTERFACE) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_METADATA_TYPE_N2H_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, nnm, sizeof(*nnm), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ * nss_n2h_notify_register()
+ *	Register to received N2H events.
+ *
+ * NOTE: Do we want to pass an nss_ctx here so that we can register for n2h on any core?
+ */
+struct nss_ctx_instance *nss_n2h_notify_register(int core, nss_n2h_msg_callback_t cb, void *app_data)
+{
+	if (core >= nss_top_main.num_nss) {
+		nss_warning("Input core number %d is wrong \n", core);
+		return NULL;
+	}
+	/*
+	 * TODO: We need to have a new array in support of the new API
+	 * TODO: If we use a per-context array, we would move the array into nss_ctx based.
+	 */
+	nss_n2h_rd[core].n2h_callback = cb;
+	nss_n2h_rd[core].app_data = app_data;
+	return &nss_top_main.nss[core];
+}
+
+/*
+ * nss_n2h_register_handler()
+ */
+void nss_n2h_register_handler(struct nss_ctx_instance *nss_ctx)
+{
+	sema_init(&nss_n2h_q_cfg_pvt.sem, 1);
+	init_completion(&nss_n2h_q_cfg_pvt.complete);
+
+	nss_core_register_handler(nss_ctx, NSS_N2H_INTERFACE, nss_n2h_interface_handler, NULL);
+
+	if (nss_ctx->id == NSS_CORE_0) {
+		nss_n2h_stats_dentry_create();
+	}
+	nss_n2h_strings_dentry_create();
+
+	nss_drv_strings_dentry_create();
+}
+
+/*
+ * nss_n2h_single_core_register_sysctl()
+ */
+void nss_n2h_single_core_register_sysctl(void)
+{
+	/*
+	 * RPS sema init
+	 */
+	sema_init(&nss_n2h_rcp.sem, 1);
+	init_completion(&nss_n2h_rcp.complete);
+
+	/*
+	 * MITIGATION sema init for core0
+	 */
+	sema_init(&nss_n2h_mitigationcp[NSS_CORE_0].sem, 1);
+	init_completion(&nss_n2h_mitigationcp[NSS_CORE_0].complete);
+
+	/*
+	 * PBUF addition sema init for core0
+	 */
+	sema_init(&nss_n2h_bufcp[NSS_CORE_0].sem, 1);
+	init_completion(&nss_n2h_bufcp[NSS_CORE_0].complete);
+
+	/*
+	 * Core0
+	 */
+	sema_init(&nss_n2h_nepbcfgp[NSS_CORE_0].sem, 1);
+	init_completion(&nss_n2h_nepbcfgp[NSS_CORE_0].complete);
+	nss_n2h_nepbcfgp[NSS_CORE_0].empty_buf_pool_info.pool_size =
+		nss_n2h_empty_pool_buf_cfg[NSS_CORE_0];
+	nss_n2h_nepbcfgp[NSS_CORE_0].empty_buf_pool_info.low_water =
+		nss_n2h_water_mark[NSS_CORE_0][0];
+	nss_n2h_nepbcfgp[NSS_CORE_0].empty_buf_pool_info.high_water =
+		nss_n2h_water_mark[NSS_CORE_0][1];
+	nss_n2h_nepbcfgp[NSS_CORE_0].empty_paged_buf_pool_info.pool_size =
+		nss_n2h_empty_paged_pool_buf_cfg[NSS_CORE_0];
+	nss_n2h_nepbcfgp[NSS_CORE_0].empty_paged_buf_pool_info.low_water =
+		nss_n2h_paged_water_mark[NSS_CORE_0][0];
+	nss_n2h_nepbcfgp[NSS_CORE_0].empty_paged_buf_pool_info.high_water =
+		nss_n2h_paged_water_mark[NSS_CORE_0][1];
+
+	/*
+	 * WiFi pool buf cfg sema init
+	 */
+	sema_init(&nss_n2h_wp.sem, 1);
+	init_completion(&nss_n2h_wp.complete);
+
+	/*
+	 * N2H queue config sema init
+	 */
+	sema_init(&nss_n2h_q_lim_pvt.sem, 1);
+	init_completion(&nss_n2h_q_lim_pvt.complete);
+
+	/*
+	 * Back pressure config sema init
+	 */
+	sema_init(&nss_n2h_host_bp_cfg_pvt.sem, 1);
+	init_completion(&nss_n2h_host_bp_cfg_pvt.complete);
+
+	nss_n2h_notify_register(NSS_CORE_0, NULL, NULL);
+
+	/*
+	 * Register sysctl table.
+	 */
+	nss_n2h_dir[0].child = nss_n2h_table_single_core;
+	nss_n2h_header = register_sysctl_table(nss_n2h_root);
+}
+
+/*
+ * nss_n2h_multi_core_register_sysctl()
+ */
+void nss_n2h_multi_core_register_sysctl(void)
+{
+	/*
+	 * RPS sema init
+	 */
+	sema_init(&nss_n2h_rcp.sem, 1);
+	init_completion(&nss_n2h_rcp.complete);
+
+	/*
+	 * MITIGATION sema init for core0
+	 */
+	sema_init(&nss_n2h_mitigationcp[NSS_CORE_0].sem, 1);
+	init_completion(&nss_n2h_mitigationcp[NSS_CORE_0].complete);
+
+	/*
+	 * MITIGATION sema init for core1
+	 */
+	sema_init(&nss_n2h_mitigationcp[NSS_CORE_1].sem, 1);
+	init_completion(&nss_n2h_mitigationcp[NSS_CORE_1].complete);
+
+	/*
+	 * PBUF addition sema init for core0
+	 */
+	sema_init(&nss_n2h_bufcp[NSS_CORE_0].sem, 1);
+	init_completion(&nss_n2h_bufcp[NSS_CORE_0].complete);
+
+	/*
+	 * PBUF addition sema init for core1
+	 */
+	sema_init(&nss_n2h_bufcp[NSS_CORE_1].sem, 1);
+	init_completion(&nss_n2h_bufcp[NSS_CORE_1].complete);
+
+	/*
+	 * Core0
+	 */
+	sema_init(&nss_n2h_nepbcfgp[NSS_CORE_0].sem, 1);
+	init_completion(&nss_n2h_nepbcfgp[NSS_CORE_0].complete);
+	nss_n2h_nepbcfgp[NSS_CORE_0].empty_buf_pool_info.pool_size =
+		nss_n2h_empty_pool_buf_cfg[NSS_CORE_0];
+	nss_n2h_nepbcfgp[NSS_CORE_0].empty_buf_pool_info.low_water =
+		nss_n2h_water_mark[NSS_CORE_0][0];
+	nss_n2h_nepbcfgp[NSS_CORE_0].empty_buf_pool_info.high_water =
+		nss_n2h_water_mark[NSS_CORE_0][1];
+	nss_n2h_nepbcfgp[NSS_CORE_0].empty_paged_buf_pool_info.pool_size =
+		nss_n2h_empty_paged_pool_buf_cfg[NSS_CORE_0];
+	nss_n2h_nepbcfgp[NSS_CORE_0].empty_paged_buf_pool_info.low_water =
+		nss_n2h_paged_water_mark[NSS_CORE_0][0];
+	nss_n2h_nepbcfgp[NSS_CORE_0].empty_paged_buf_pool_info.high_water =
+		nss_n2h_paged_water_mark[NSS_CORE_0][1];
+
+	/*
+	 * Core1
+	 */
+	sema_init(&nss_n2h_nepbcfgp[NSS_CORE_1].sem, 1);
+	init_completion(&nss_n2h_nepbcfgp[NSS_CORE_1].complete);
+	nss_n2h_nepbcfgp[NSS_CORE_1].empty_buf_pool_info.pool_size =
+		nss_n2h_empty_pool_buf_cfg[NSS_CORE_1];
+	nss_n2h_nepbcfgp[NSS_CORE_1].empty_buf_pool_info.low_water =
+		nss_n2h_water_mark[NSS_CORE_1][0];
+	nss_n2h_nepbcfgp[NSS_CORE_1].empty_buf_pool_info.high_water =
+		nss_n2h_water_mark[NSS_CORE_1][1];
+	nss_n2h_nepbcfgp[NSS_CORE_1].empty_paged_buf_pool_info.pool_size =
+		nss_n2h_empty_paged_pool_buf_cfg[NSS_CORE_1];
+	nss_n2h_nepbcfgp[NSS_CORE_1].empty_paged_buf_pool_info.low_water =
+		nss_n2h_paged_water_mark[NSS_CORE_1][0];
+	nss_n2h_nepbcfgp[NSS_CORE_1].empty_paged_buf_pool_info.high_water =
+		nss_n2h_paged_water_mark[NSS_CORE_1][1];
+
+	/*
+	 * WiFi pool buf cfg sema init
+	 */
+	sema_init(&nss_n2h_wp.sem, 1);
+	init_completion(&nss_n2h_wp.complete);
+
+	/*
+	 * N2H queue config sema init
+	 */
+	sema_init(&nss_n2h_q_lim_pvt.sem, 1);
+	init_completion(&nss_n2h_q_lim_pvt.complete);
+
+	/*
+	 * Back pressure config sema init
+	 */
+	sema_init(&nss_n2h_host_bp_cfg_pvt.sem, 1);
+	init_completion(&nss_n2h_host_bp_cfg_pvt.complete);
+
+	nss_n2h_notify_register(NSS_CORE_0, NULL, NULL);
+	nss_n2h_notify_register(NSS_CORE_1, NULL, NULL);
+
+	/*
+	 * Register sysctl table.
+	 */
+	nss_n2h_header = register_sysctl_table(nss_n2h_root);
+}
+
+/*
+ * nss_n2h_unregister_sysctl()
+ *	Unregister sysctl specific to n2h
+ */
+void nss_n2h_unregister_sysctl(void)
+{
+	/*
+	 * Unregister sysctl table.
+	 */
+	if (nss_n2h_header) {
+		unregister_sysctl_table(nss_n2h_header);
+	}
+}
+
+EXPORT_SYMBOL(nss_n2h_notify_register);
diff --git a/qca-nss-drv/nss_n2h_stats.c b/qca-nss-drv/nss_n2h_stats.c
new file mode 100644
index 0000000..60ff88b
--- /dev/null
+++ b/qca-nss-drv/nss_n2h_stats.c
@@ -0,0 +1,214 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_n2h_stats.h"
+#include "nss_n2h.h"
+#include "nss_n2h_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_n2h_stats_notifier);
+
+uint64_t nss_n2h_stats[NSS_MAX_CORES][NSS_N2H_STATS_MAX];
+
+/*
+ * nss_n2h_stats_read()
+ *	Read N2H stats
+ */
+static ssize_t nss_n2h_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i, core;
+
+	/*
+	 * Max output lines = #stats + few blank lines for banner printing +
+	 * Number of Extra outputlines for future reference to add new stats
+	 */
+	uint32_t max_output_lines = (NSS_N2H_STATS_MAX + 3) * NSS_MAX_CORES + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_N2H_STATS_MAX * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	/*
+	 * N2H node stats
+	 */
+	for (core = 0; core < nss_top_main.num_nss; core++) {
+		spin_lock_bh(&nss_top_main.stats_lock);
+		for (i = 0; i < NSS_N2H_STATS_MAX; i++) {
+			stats_shadow[i] = nss_n2h_stats[core][i];
+		}
+		spin_unlock_bh(&nss_top_main.stats_lock);
+		size_wr += nss_stats_banner(lbuf, size_wr, size_al, "n2h", core);
+		size_wr += nss_stats_print("n2h", NULL, NSS_STATS_SINGLE_INSTANCE
+						, nss_n2h_strings_stats
+						, stats_shadow
+						, NSS_N2H_STATS_MAX
+						, lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_n2h_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(n2h);
+
+/*
+ * nss_n2h_stats_dentry_create()
+ *	Create N2H statistics debug entry.
+ */
+void nss_n2h_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("n2h", &nss_n2h_stats_ops);
+}
+
+/*
+ * nss_n2h_stats_sync()
+ *	Handle the syncing of NSS statistics.
+ */
+void nss_n2h_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_n2h_stats_sync *nnss)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	int id = nss_ctx->id;
+	int j;
+
+	spin_lock_bh(&nss_top->stats_lock);
+
+	/*
+	 * common node stats
+	 */
+	nss_n2h_stats[id][NSS_STATS_NODE_RX_PKTS] += nnss->node_stats.rx_packets;
+	nss_n2h_stats[id][NSS_STATS_NODE_RX_BYTES] += nnss->node_stats.rx_bytes;
+	nss_n2h_stats[id][NSS_STATS_NODE_TX_PKTS] += nnss->node_stats.tx_packets;
+	nss_n2h_stats[id][NSS_STATS_NODE_TX_BYTES] += nnss->node_stats.tx_bytes;
+
+	for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+		nss_n2h_stats[id][NSS_STATS_NODE_RX_QUEUE_0_DROPPED + j] += nnss->node_stats.rx_dropped[j];
+	}
+
+	/*
+	 * General N2H stats
+	 */
+	nss_n2h_stats[id][NSS_N2H_STATS_QUEUE_DROPPED] += nnss->queue_dropped;
+	nss_n2h_stats[id][NSS_N2H_STATS_TOTAL_TICKS] += nnss->total_ticks;
+	nss_n2h_stats[id][NSS_N2H_STATS_WORST_CASE_TICKS] += nnss->worst_case_ticks;
+	nss_n2h_stats[id][NSS_N2H_STATS_ITERATIONS] += nnss->iterations;
+
+	/*
+	 * pbuf manager ocm and default pool stats
+	 */
+	nss_n2h_stats[id][NSS_N2H_STATS_PBUF_OCM_ALLOC_FAILS_WITH_PAYLOAD] += nnss->pbuf_ocm_stats.pbuf_alloc_fails_with_payload;
+	nss_n2h_stats[id][NSS_N2H_STATS_PBUF_OCM_FREE_COUNT] = nnss->pbuf_ocm_stats.pbuf_free_count;
+	nss_n2h_stats[id][NSS_N2H_STATS_PBUF_OCM_TOTAL_COUNT] = nnss->pbuf_ocm_stats.pbuf_total_count;
+	nss_n2h_stats[id][NSS_N2H_STATS_PBUF_OCM_ALLOC_FAILS_NO_PAYLOAD] += nnss->pbuf_ocm_stats.pbuf_alloc_fails_no_payload;
+
+	nss_n2h_stats[id][NSS_N2H_STATS_PBUF_DEFAULT_ALLOC_FAILS_WITH_PAYLOAD] += nnss->pbuf_default_stats.pbuf_alloc_fails_with_payload;
+	nss_n2h_stats[id][NSS_N2H_STATS_PBUF_DEFAULT_FREE_COUNT] = nnss->pbuf_default_stats.pbuf_free_count;
+	nss_n2h_stats[id][NSS_N2H_STATS_PBUF_DEFAULT_TOTAL_COUNT] = nnss->pbuf_default_stats.pbuf_total_count;
+	nss_n2h_stats[id][NSS_N2H_STATS_PBUF_DEFAULT_ALLOC_FAILS_NO_PAYLOAD] += nnss->pbuf_default_stats.pbuf_alloc_fails_no_payload;
+
+	/*
+	 * payload mgr stats
+	 */
+	nss_n2h_stats[id][NSS_N2H_STATS_PAYLOAD_ALLOC_FAILS] += nnss->payload_alloc_fails;
+	nss_n2h_stats[id][NSS_N2H_STATS_PAYLOAD_FREE_COUNT] = nnss->payload_free_count;
+
+	/*
+	 * Host <=> NSS control traffic stats
+	 */
+	nss_n2h_stats[id][NSS_N2H_STATS_H2N_CONTROL_PACKETS] += nnss->h2n_ctrl_pkts;
+	nss_n2h_stats[id][NSS_N2H_STATS_H2N_CONTROL_BYTES] += nnss->h2n_ctrl_bytes;
+	nss_n2h_stats[id][NSS_N2H_STATS_N2H_CONTROL_PACKETS] += nnss->n2h_ctrl_pkts;
+	nss_n2h_stats[id][NSS_N2H_STATS_N2H_CONTROL_BYTES] += nnss->n2h_ctrl_bytes;
+
+	/*
+	 * Host <=> NSS control data traffic stats
+	 */
+	nss_n2h_stats[id][NSS_N2H_STATS_H2N_DATA_PACKETS] += nnss->h2n_data_pkts;
+	nss_n2h_stats[id][NSS_N2H_STATS_H2N_DATA_BYTES] += nnss->h2n_data_bytes;
+	nss_n2h_stats[id][NSS_N2H_STATS_N2H_DATA_PACKETS] += nnss->n2h_data_pkts;
+	nss_n2h_stats[id][NSS_N2H_STATS_N2H_DATA_BYTES] += nnss->n2h_data_bytes;
+
+	/*
+	 * Payloads related stats
+	 */
+	nss_n2h_stats[id][NSS_N2H_STATS_N2H_TOT_PAYLOADS] = nnss->tot_payloads;
+
+	nss_n2h_stats[id][NSS_N2H_STATS_N2H_INTERFACE_INVALID] += nnss->data_interface_invalid;
+	nss_n2h_stats[id][NSS_N2H_STATS_ENQUEUE_RETRIES] += nnss->enqueue_retries;
+
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_n2h_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_n2h_stats_notify(struct nss_ctx_instance *nss_ctx)
+{
+	int i;
+	struct nss_n2h_stats_notification stats;
+
+	for (i = 0; (i < NSS_STATS_DRV_MAX); i++) {
+		stats.drv_stats[i] = NSS_PKT_STATS_READ(&nss_top_main.stats_drv[i]);
+	}
+
+	stats.core_id = nss_ctx->id;
+	memcpy(stats.n2h_stats, nss_n2h_stats[stats.core_id], sizeof(stats.n2h_stats));
+	atomic_notifier_call_chain(&nss_n2h_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&stats);
+}
+
+/*
+ * nss_n2h_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_n2h_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_n2h_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_n2h_stats_register_notifier);
+
+/*
+ * nss_n2h_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_n2h_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_n2h_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_n2h_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_n2h_stats.h b/qca-nss-drv/nss_n2h_stats.h
new file mode 100644
index 0000000..96d065e
--- /dev/null
+++ b/qca-nss-drv/nss_n2h_stats.h
@@ -0,0 +1,27 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2017,2019-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_N2H_STATS_H
+#define __NSS_N2H_STATS_H
+
+/*
+ * N2H statistics APIs
+ */
+extern void nss_n2h_stats_notify(struct nss_ctx_instance *nss_ctx);
+extern void nss_n2h_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_n2h_stats_sync *nnss);
+extern void nss_n2h_stats_dentry_create(void);
+
+#endif /* __NSS_N2H_STATS_H */
diff --git a/qca-nss-drv/nss_n2h_strings.c b/qca-nss-drv/nss_n2h_strings.c
new file mode 100644
index 0000000..c4c2ce5
--- /dev/null
+++ b/qca-nss-drv/nss_n2h_strings.c
@@ -0,0 +1,85 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include <nss_n2h.h>
+#include "nss_strings.h"
+
+/*
+ * nss_n2h_strings_stats
+ *	N2H statistics strings.
+ */
+struct nss_stats_info nss_n2h_strings_stats[NSS_N2H_STATS_MAX] = {
+	{"rx_pkts"			, NSS_STATS_TYPE_COMMON},
+	{"rx_byts"			, NSS_STATS_TYPE_COMMON},
+	{"tx_pkts"			, NSS_STATS_TYPE_COMMON},
+	{"tx_byts"			, NSS_STATS_TYPE_COMMON},
+	{"rx_queue[0]_drops"		, NSS_STATS_TYPE_DROP},
+	{"rx_queue[1]_drops"		, NSS_STATS_TYPE_DROP},
+	{"rx_queue[2]_drops"		, NSS_STATS_TYPE_DROP},
+	{"rx_queue[3]_drops"		, NSS_STATS_TYPE_DROP},
+	{"queue_drops"			, NSS_STATS_TYPE_DROP},
+	{"ticks"			, NSS_STATS_TYPE_SPECIAL},
+	{"worst_ticks"			, NSS_STATS_TYPE_SPECIAL},
+	{"iterations"			, NSS_STATS_TYPE_SPECIAL},
+	{"pbuf_ocm_total_count"		, NSS_STATS_TYPE_SPECIAL},
+	{"pbuf_ocm_free_count"		, NSS_STATS_TYPE_SPECIAL},
+	{"pbuf_ocm_alloc_fail_payload"	, NSS_STATS_TYPE_SPECIAL},
+	{"pbuf_ocm_alloc_fail_nopayload", NSS_STATS_TYPE_SPECIAL},
+	{"pbuf_def_total_count"		, NSS_STATS_TYPE_SPECIAL},
+	{"pbuf_def_free_count"		, NSS_STATS_TYPE_SPECIAL},
+	{"pbuf_def_alloc_fail_payload"	, NSS_STATS_TYPE_SPECIAL},
+	{"pbuf_def_alloc_fail_nopayload", NSS_STATS_TYPE_SPECIAL},
+	{"payload_alloc_fails"		, NSS_STATS_TYPE_SPECIAL},
+	{"payload_free_count"		, NSS_STATS_TYPE_SPECIAL},
+	{"h2n_control_pkts"		, NSS_STATS_TYPE_SPECIAL},
+	{"h2n_control_byts"		, NSS_STATS_TYPE_SPECIAL},
+	{"n2h_control_pkts"		, NSS_STATS_TYPE_SPECIAL},
+	{"n2h_control_byts"		, NSS_STATS_TYPE_SPECIAL},
+	{"h2n_data_pkts"		, NSS_STATS_TYPE_SPECIAL},
+	{"h2n_data_byts"		, NSS_STATS_TYPE_SPECIAL},
+	{"n2h_data_pkts"		, NSS_STATS_TYPE_SPECIAL},
+	{"n2h_data_byts"		, NSS_STATS_TYPE_SPECIAL},
+	{"n2h_tot_payloads"		, NSS_STATS_TYPE_SPECIAL},
+	{"n2h_data_interface_invalid"	, NSS_STATS_TYPE_SPECIAL},
+	{"n2h_enqueue_retries"		, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_n2h_strings_read()
+ *	Read N2H node statistics names.
+ */
+static ssize_t nss_n2h_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_n2h_strings_stats, NSS_N2H_STATS_MAX);
+}
+
+/*
+ * nss_n2h_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(n2h);
+
+/*
+ * nss_n2h_strings_dentry_create()
+ *	Create N2H statistics strings debug entry.
+ */
+void nss_n2h_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("n2h", &nss_n2h_strings_ops);
+}
diff --git a/qca-nss-drv/nss_n2h_strings.h b/qca-nss-drv/nss_n2h_strings.h
new file mode 100644
index 0000000..5d8c213
--- /dev/null
+++ b/qca-nss-drv/nss_n2h_strings.h
@@ -0,0 +1,25 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_N2H_STRINGS_H
+#define __NSS_N2H_STRINGS_H
+
+extern struct nss_stats_info nss_n2h_strings_stats[NSS_N2H_STATS_MAX];
+extern void nss_n2h_strings_dentry_create(void);
+
+#endif /* __NSS_N2H_STRINGS_H */
diff --git a/qca-nss-drv/nss_oam.c b/qca-nss-drv/nss_oam.c
new file mode 100644
index 0000000..baf43d3
--- /dev/null
+++ b/qca-nss-drv/nss_oam.c
@@ -0,0 +1,141 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_oam.c
+ *	OAM - Operations, Administration and Maintenance Service for NSS
+ *
+ * This adapter module is responsible for sending and
+ * receiving to and from NSS FW
+ * This file contains the API for communicating NSS FW to send/receive
+ * commands OAM commands.
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_oam_log.h"
+
+/*
+ * nss_oam_rx_msg_handler()
+ *	Message handler for OAM messages from NSS
+ */
+static void nss_oam_rx_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused)) void *app_data)
+{
+	struct nss_oam_msg *nom = (struct nss_oam_msg *)ncm;
+	nss_oam_msg_callback_t cb;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_oam_log_rx_msg(nom);
+
+	/*
+	 * Sanity check the message type
+	 */
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_oam_msg)) {
+		nss_warning("%px: recevied with invalid msg size: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	if (ncm->type > NSS_OAM_MSG_TYPE_MAX) {
+		nss_warning("%px: received with invalid resp type: %d", nss_ctx, ncm->type);
+		return;
+	}
+
+	/*
+	 * Log the failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_top_main.oam_callback;
+		ncm->app_data = (nss_ptr_t)nss_top_main.oam_ctx;
+	}
+
+	cb = (nss_oam_msg_callback_t)ncm->cb;
+	if (unlikely(!cb)) {
+		nss_trace("%px: rx handler has been unregistered for i/f: %d", nss_ctx, ncm->interface);
+		return;
+	}
+	cb((void *)ncm->app_data, nom);
+}
+
+/*
+ * nss_oam_tx()
+ *	Transmit an oam message to the FW.
+ */
+nss_tx_status_t nss_oam_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_oam_msg *nom)
+{
+	struct nss_cmn_msg *ncm = &nom->cm;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_oam_log_tx_msg(nom);
+
+	if (ncm->type > NSS_OAM_MSG_TYPE_MAX) {
+		nss_warning("%px: CMD type for oam module is invalid - %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	if (ncm->interface != NSS_OAM_INTERFACE) {
+		nss_warning("%px: tx message request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, nom, sizeof(*nom), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_oam_tx_msg);
+
+/*
+ * nss_oam_notify_register()
+ *	Register to receive OAM events.
+ */
+struct nss_ctx_instance *nss_oam_notify_register(nss_oam_msg_callback_t cb, void *app_data)
+{
+	if (nss_top_main.oam_ctx || nss_top_main.oam_callback) {
+		nss_warning("Failed to register notify callback - already registered\n");
+		return NULL;
+	}
+
+	nss_top_main.oam_ctx = app_data;
+	nss_top_main.oam_callback = cb;
+	return &nss_top_main.nss[nss_top_main.oam_handler_id];
+}
+EXPORT_SYMBOL(nss_oam_notify_register);
+
+/*
+ * nss_oam_notify_unregister()
+ *	Unregister to received OAM events.
+ */
+void nss_oam_notify_unregister(void)
+{
+	nss_top_main.oam_callback = NULL;
+	nss_top_main.oam_ctx = NULL;
+}
+EXPORT_SYMBOL(nss_oam_notify_unregister);
+
+/*
+ * nss_register_oam_handler()
+ *	Register our handler to receive messages for this interface
+ */
+void nss_oam_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[nss_top_main.oam_handler_id];
+
+	if (nss_core_register_handler(nss_ctx, NSS_OAM_INTERFACE, nss_oam_rx_msg_handler, NULL) != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("OAM handler failed to register");
+	}
+}
diff --git a/qca-nss-drv/nss_oam_log.c b/qca-nss-drv/nss_oam_log.c
new file mode 100644
index 0000000..08ffec4
--- /dev/null
+++ b/qca-nss-drv/nss_oam_log.c
@@ -0,0 +1,101 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_oam_log.c
+ *	NSS OAM logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_oam_log_message_types_str
+ *	NSS OAM message strings
+ */
+static int8_t *nss_oam_log_message_types_str[NSS_OAM_MSG_TYPE_MAX] __maybe_unused = {
+	"OAM Message None",
+	"OAM Get FW Version",
+};
+
+/*
+ * nss_oam_log_get_fw_version_msg()
+ *	Log NSS OAM GET FW Version.
+ */
+static void nss_oam_log_get_fw_version_msg(struct nss_oam_msg *nom)
+{
+	struct nss_oam_fw_ver *nofm __maybe_unused = &nom->msg.fw_ver;
+	nss_trace("%px: NSS OAM Get FW Version message \n"
+		"OAM FW Version: %px\n",
+		nofm, nofm->string);
+}
+
+/*
+ * nss_oam_log_verbose()
+ *	Log message contents.
+ */
+static void nss_oam_log_verbose(struct nss_oam_msg *nom)
+{
+	switch (nom->cm.type) {
+	case NSS_OAM_MSG_TYPE_GET_FW_VER:
+		nss_oam_log_get_fw_version_msg(nom);
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", nom);
+		break;
+	}
+}
+
+/*
+ * nss_oam_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_oam_log_tx_msg(struct nss_oam_msg *nom)
+{
+	if (nom->cm.type >= NSS_OAM_MSG_TYPE_MAX) {
+		nss_warning("%px: Invalid message type\n", nom);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nom, nom->cm.type, nss_oam_log_message_types_str[nom->cm.type]);
+	nss_oam_log_verbose(nom);
+}
+
+/*
+ * nss_oam_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_oam_log_rx_msg(struct nss_oam_msg *nom)
+{
+	if (nom->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", nom);
+		return;
+	}
+
+	if (nom->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nom->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nom, nom->cm.type,
+			nss_oam_log_message_types_str[nom->cm.type],
+			nom->cm.response, nss_cmn_response_str[nom->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		nom, nom->cm.type, nss_oam_log_message_types_str[nom->cm.type],
+		nom->cm.response, nss_cmn_response_str[nom->cm.response]);
+
+verbose:
+	nss_oam_log_verbose(nom);
+}
diff --git a/qca-nss-drv/nss_oam_log.h b/qca-nss-drv/nss_oam_log.h
new file mode 100644
index 0000000..b02611b
--- /dev/null
+++ b/qca-nss-drv/nss_oam_log.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_OAM_LOG_H
+#define __NSS_OAM_LOG_H
+
+/*
+ * nss_oam.h
+ *	NSS OAM header file.
+ */
+
+/*
+ * Logger APIs
+ */
+
+/*
+ * nss_oam_log_tx_msg
+ *	Logs a oam message that is sent to the NSS firmware.
+ */
+void nss_oam_log_tx_msg(struct nss_oam_msg *nom);
+
+/*
+ * nss_oam_log_rx_msg
+ *	Logs a oam message that is received from the NSS firmware.
+ */
+void nss_oam_log_rx_msg(struct nss_oam_msg *nom);
+
+#endif /* __NSS_OAM_LOG_H */
diff --git a/qca-nss-drv/nss_phys_if.c b/qca-nss-drv/nss_phys_if.c
new file mode 100644
index 0000000..4e5811a
--- /dev/null
+++ b/qca-nss-drv/nss_phys_if.c
@@ -0,0 +1,629 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_phy_if.c
+ *	NSS physical interface functions
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_tstamp.h"
+#if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT)
+#include <nss_dp_api_if.h>
+#endif
+
+#define NSS_PHYS_IF_TX_TIMEOUT 3000 /* 3 Seconds */
+
+/*
+ * NSS phys_if modes
+ */
+#define NSS_PHYS_IF_MODE0	0	/* phys_if mode 0 */
+#define NSS_PHYS_IF_MODE1	1	/* phys_if mode 1 */
+#define NSS_PHYS_IF_MODE2	2	/* phys_if mode 2 */
+
+/*
+ * Private data structure for phys_if interface
+ */
+static struct nss_phys_if_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+} phif;
+
+static int nss_phys_if_sem_init_done;
+
+/*
+ * nss_phys_if_update_driver_stats()
+ *	Snoop the extended message and update driver statistics.
+ */
+static void nss_phys_if_update_driver_stats(struct nss_ctx_instance *nss_ctx, uint32_t id, struct nss_phys_if_stats *stats)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	uint64_t *top_stats = &(nss_top->stats_gmac[id][0]);
+
+	spin_lock_bh(&nss_top->stats_lock);
+	top_stats[NSS_GMAC_STATS_TOTAL_TICKS] += stats->estats.gmac_total_ticks;
+	if (unlikely(top_stats[NSS_GMAC_STATS_WORST_CASE_TICKS] < stats->estats.gmac_worst_case_ticks)) {
+		top_stats[NSS_GMAC_STATS_WORST_CASE_TICKS] = stats->estats.gmac_worst_case_ticks;
+	}
+	top_stats[NSS_GMAC_STATS_ITERATIONS] += stats->estats.gmac_iterations;
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_phys_if_msg_handler()
+ *	Handle NSS -> HLOS messages for physical interface/gmacs
+ */
+static void nss_phys_if_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm,
+		__attribute__((unused))void *app_data)
+{
+	struct nss_phys_if_msg *nim = (struct nss_phys_if_msg *)ncm;
+	nss_phys_if_msg_callback_t cb;
+
+	/*
+	 * Sanity check the message type
+	 */
+	if (ncm->type > NSS_PHYS_IF_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (!NSS_IS_IF_TYPE(PHYSICAL, ncm->interface)) {
+		nss_warning("%px: response for another interface: %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_phys_if_msg)) {
+		nss_warning("%px: message length too big: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Messages value that are within the base class are handled by the base class.
+	 */
+	if (ncm->type < NSS_IF_MAX_MSG_TYPES) {
+		return nss_if_msg_handler(nss_ctx, ncm, app_data);
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Snoop messages for local driver and handle deprecated interfaces.
+	 */
+	switch (nim->cm.type) {
+	case NSS_PHYS_IF_EXTENDED_STATS_SYNC:
+		/*
+		 * To create the old API gmac statistics, we use the new extended GMAC stats.
+		 */
+		nss_phys_if_update_driver_stats(nss_ctx, ncm->interface, &nim->msg.stats);
+		nss_top_main.data_plane_ops->data_plane_stats_sync(&nim->msg.stats, ncm->interface);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, IPv4 sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->phys_if_msg_callback[ncm->interface];
+		ncm->app_data = (nss_ptr_t)nss_ctx->subsys_dp_register[ncm->interface].ndev;
+	}
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * Callback
+	 */
+	cb = (nss_phys_if_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, nim);
+}
+
+/*
+ * nss_phys_if_callback
+ *	Callback to handle the completion of NSS ->HLOS messages.
+ */
+static void nss_phys_if_callback(void *app_data, struct nss_phys_if_msg *nim)
+{
+	if(nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("phys_if Error response %d\n", nim->cm.response);
+		phif.response = NSS_TX_FAILURE;
+		complete(&phif.complete);
+		return;
+	}
+
+	phif.response = NSS_TX_SUCCESS;
+	complete(&phif.complete);
+}
+
+/*
+ * nss_phys_if_buf()
+ *	Send packet to physical interface owned by NSS
+ */
+nss_tx_status_t nss_phys_if_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, uint32_t if_num)
+{
+	nss_trace("%px: Phys If Tx packet, id:%d, data=%px", nss_ctx, if_num, os_buf->data);
+
+#ifdef NSS_DRV_TSTAMP_ENABLE
+	/*
+	 * If we need the packet to be timestamped by GMAC Hardware at Tx
+	 * send the packet to tstamp NSS module
+	 */
+	if (unlikely(skb_shinfo(os_buf)->tx_flags & SKBTX_HW_TSTAMP)) {
+		/* try PHY Driver hook for transmit timestamping firstly */
+#if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT)
+		nss_phy_tstamp_tx_buf(os_buf->dev, os_buf);
+#endif
+		if (!(skb_shinfo(os_buf)->tx_flags & SKBTX_IN_PROGRESS))
+			return nss_tstamp_tx_buf(nss_ctx, os_buf, if_num);
+	}
+#endif
+
+	return nss_core_send_packet(nss_ctx, os_buf, if_num, H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+
+/*
+ * nss_phys_if_msg()
+ */
+nss_tx_status_t nss_phys_if_msg(struct nss_ctx_instance *nss_ctx, struct nss_phys_if_msg *nim)
+{
+	struct nss_cmn_msg *ncm = &nim->cm;
+	struct net_device *dev;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!NSS_IS_IF_TYPE(PHYSICAL, ncm->interface)) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_PHYS_IF_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	dev = nss_ctx->subsys_dp_register[ncm->interface].ndev;
+	if (!dev) {
+		nss_warning("%px: Unregister physical interface %d: no context", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	return nss_core_send_cmd(nss_ctx, nim, sizeof(*nim), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ * nss_phys_if_tx_msg_sync()
+ *	Send a message to physical interface & wait for the response.
+ */
+nss_tx_status_t nss_phys_if_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_phys_if_msg *nim)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&phif.sem);
+
+	status = nss_phys_if_msg(nss_ctx, nim);
+	if(status != NSS_TX_SUCCESS)
+	{
+		nss_warning("%px: nss_phys_if_msg failed\n", nss_ctx);
+		up(&phif.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&phif.complete, msecs_to_jiffies(NSS_PHYS_IF_TX_TIMEOUT));
+
+	if(!ret)
+	{
+		nss_warning("%px: phys_if tx failed due to timeout\n", nss_ctx);
+		phif.response = NSS_TX_FAILURE;
+	}
+
+	status = phif.response;
+	up(&phif.sem);
+
+	return status;
+}
+
+/*
+ **********************************
+ Register/Unregister/Miscellaneous APIs
+ **********************************
+ */
+
+/*
+ * nss_phys_if_register()
+ */
+struct nss_ctx_instance *nss_phys_if_register(uint32_t if_num,
+				nss_phys_if_rx_callback_t rx_callback,
+				nss_phys_if_msg_callback_t msg_callback,
+				struct net_device *netdev,
+				uint32_t features)
+{
+	uint8_t id = nss_top_main.phys_if_handler_id[if_num];
+	struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[id];
+
+	nss_assert(nss_ctx);
+	nss_assert(if_num <= NSS_MAX_PHYSICAL_INTERFACES);
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, rx_callback, NULL, NULL, netdev, features);
+
+	nss_top_main.phys_if_msg_callback[if_num] = msg_callback;
+
+	nss_ctx->phys_if_mtu[if_num] = ETH_DATA_LEN;
+	return nss_ctx;
+}
+
+/*
+ * nss_phys_if_unregister()
+ */
+void nss_phys_if_unregister(uint32_t if_num)
+{
+	uint8_t id = nss_top_main.phys_if_handler_id[if_num];
+	struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[id];
+
+	nss_assert(nss_ctx);
+	nss_assert(if_num < NSS_MAX_PHYSICAL_INTERFACES);
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	nss_top_main.phys_if_msg_callback[if_num] = NULL;
+
+	nss_top_main.nss[0].phys_if_mtu[if_num] = 0;
+	nss_top_main.nss[1].phys_if_mtu[if_num] = 0;
+}
+
+/*
+ * nss_phys_if_register_handler()
+ */
+void nss_phys_if_register_handler(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	uint32_t ret;
+
+	ret = nss_core_register_handler(nss_ctx, if_num, nss_phys_if_msg_handler, NULL);
+
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("Message handler FAILED to be registered for interface %d", if_num);
+		return;
+	}
+
+	if(!nss_phys_if_sem_init_done) {
+		sema_init(&phif.sem, 1);
+		init_completion(&phif.complete);
+		nss_phys_if_sem_init_done = 1;
+	}
+}
+
+/*
+ * nss_phys_if_open()
+ *	Send open command to physical interface
+ */
+nss_tx_status_t nss_phys_if_open(struct nss_ctx_instance *nss_ctx, uint32_t tx_desc_ring, uint32_t rx_desc_ring, uint32_t mode, uint32_t if_num, uint32_t bypass_nw_process)
+{
+	struct nss_phys_if_msg nim;
+	struct nss_if_open *nio;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	nss_info("%px: Phys If Open, id:%d, TxDesc: %x, RxDesc: %x\n", nss_ctx, if_num, tx_desc_ring, rx_desc_ring);
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_PHYS_IF_OPEN,
+			sizeof(struct nss_if_open), nss_phys_if_callback, NULL);
+
+	nio = &nim.msg.if_msg.open;
+	nio->tx_desc_ring = tx_desc_ring;
+	nio->rx_desc_ring = rx_desc_ring;
+
+	if (mode == NSS_PHYS_IF_MODE0) {
+		nio->rx_forward_if = NSS_ETH_RX_INTERFACE;
+		nio->alignment_mode = NSS_IF_DATA_ALIGN_2BYTE;
+	} else if (mode == NSS_PHYS_IF_MODE1) {
+		nio->rx_forward_if = NSS_SJACK_INTERFACE;
+		nio->alignment_mode = NSS_IF_DATA_ALIGN_4BYTE;
+	} else if (mode == NSS_PHYS_IF_MODE2) {
+		nio->rx_forward_if = NSS_PORTID_INTERFACE;
+		nio->alignment_mode = NSS_IF_DATA_ALIGN_2BYTE;
+	} else {
+		nss_info("%px: Phys If Open, unknown mode %d\n", nss_ctx, mode);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * If Network processing in NSS is bypassed
+	 * update next hop and alignment accordingly
+	 */
+	if (bypass_nw_process) {
+		nio->rx_forward_if = NSS_N2H_INTERFACE;
+		nio->alignment_mode = NSS_IF_DATA_ALIGN_2BYTE;
+	}
+
+	return nss_phys_if_msg_sync(nss_ctx, &nim);
+}
+
+/*
+ * nss_phys_if_close()
+ *	Send close command to physical interface
+ */
+nss_tx_status_t nss_phys_if_close(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_phys_if_msg nim;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	nss_info("%px: Phys If Close, id:%d \n", nss_ctx, if_num);
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_PHYS_IF_CLOSE,
+			sizeof(struct nss_if_close), nss_phys_if_callback, NULL);
+
+	return nss_phys_if_msg_sync(nss_ctx, &nim);
+}
+
+/*
+ * nss_phys_if_link_state()
+ *	Send link state to physical interface
+ */
+nss_tx_status_t nss_phys_if_link_state(struct nss_ctx_instance *nss_ctx, uint32_t link_state, uint32_t if_num)
+{
+	struct nss_phys_if_msg nim;
+	struct nss_if_link_state_notify *nils;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	nss_info("%px: Phys If Link State, id:%d, State: %x\n", nss_ctx, if_num, link_state);
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_PHYS_IF_LINK_STATE_NOTIFY,
+			sizeof(struct nss_if_link_state_notify), nss_phys_if_callback, NULL);
+
+	nils = &nim.msg.if_msg.link_state_notify;
+	nils->state = link_state;
+	return nss_phys_if_msg_sync(nss_ctx, &nim);
+}
+
+/*
+ * nss_phys_if_mac_addr()
+ *	Send a MAC address to physical interface
+ */
+nss_tx_status_t nss_phys_if_mac_addr(struct nss_ctx_instance *nss_ctx, uint8_t *addr, uint32_t if_num)
+{
+	struct nss_phys_if_msg nim;
+	struct nss_if_mac_address_set *nmas;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	nss_info("%px: Phys If MAC Address, id:%d\n", nss_ctx, if_num);
+	nss_assert(addr != 0);
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_PHYS_IF_MAC_ADDR_SET,
+			sizeof(struct nss_if_mac_address_set), nss_phys_if_callback, NULL);
+
+	nmas = &nim.msg.if_msg.mac_address_set;
+	memcpy(nmas->mac_addr, addr, ETH_ALEN);
+	return nss_phys_if_msg_sync(nss_ctx, &nim);
+}
+
+/*
+ * nss_phys_if_change_mtu()
+ *	Send a MTU change command
+ */
+nss_tx_status_t nss_phys_if_change_mtu(struct nss_ctx_instance *nss_ctx, uint32_t mtu, uint32_t if_num)
+{
+	struct nss_phys_if_msg nim;
+	struct nss_if_mtu_change *nimc;
+	uint16_t mtu_sz, max_mtu;
+	int i;
+	nss_tx_status_t status;
+
+/*
+ * We disallow MTU changes for low memory profiles in order to keep the buffer size constant
+ */
+#ifdef NSS_FIXED_BUFFER_SIZE
+	if (mtu > ETH_DATA_LEN) {
+		nss_info_always("MTU change beyond 1500 restricted for low memory profile \n");
+		return NSS_TX_FAILURE;
+	}
+#endif
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	nss_info("%px: Phys If Change MTU, id:%d, mtu=%d\n", nss_ctx, if_num, mtu);
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_PHYS_IF_MTU_CHANGE,
+			sizeof(struct nss_if_mtu_change), nss_phys_if_callback, NULL);
+
+	nimc = &nim.msg.if_msg.mtu_change;
+	nimc->min_buf_size = mtu;
+
+	status = nss_phys_if_msg_sync(nss_ctx, &nim);
+	if (status != NSS_TX_SUCCESS) {
+		return status;
+	}
+
+	/*
+	 * Update the mtu and max_buf_size accordingly
+	 */
+	nss_ctx->phys_if_mtu[if_num] = (uint16_t)mtu;
+
+	/*
+	 * Loop through MTU values of all Physical
+	 * interfaces and get the maximum one of all
+	 */
+	max_mtu = nss_ctx->phys_if_mtu[0];
+	for (i = 1; i < NSS_MAX_PHYSICAL_INTERFACES; i++) {
+		if (max_mtu < nss_ctx->phys_if_mtu[i]) {
+			max_mtu = nss_ctx->phys_if_mtu[i];
+		}
+	}
+
+	mtu_sz = nss_top_main.data_plane_ops->data_plane_get_mtu_sz(max_mtu);
+
+/*
+ * We need to ensure the max_buf_size for 256MB profile stays
+ * constant at NSS_EMPTY_BUFFER_SIZE. We do this by disallowing changes
+ * to it due to MTU changes. Also, NSS_EMPTY_BUFFER_SIZE includes the
+ * PAD and ETH_HLEN, and is aligned to SMP_CACHE_BYTES
+ */
+#ifndef NSS_FIXED_BUFFER_SIZE
+	nss_ctx->max_buf_size = ((mtu_sz + ETH_HLEN + SMP_CACHE_BYTES - 1) & ~(SMP_CACHE_BYTES - 1)) + NSS_NBUF_ETH_EXTRA + NSS_NBUF_PAD_EXTRA;
+
+	/*
+	 * max_buf_size should not be lesser than NSS_NBUF_PAYLOAD_SIZE
+	 */
+	if (nss_ctx->max_buf_size < NSS_NBUF_PAYLOAD_SIZE) {
+		nss_ctx->max_buf_size = NSS_NBUF_PAYLOAD_SIZE;
+	}
+#else
+	nss_ctx->max_buf_size = NSS_EMPTY_BUFFER_SIZE;
+#endif
+
+#if (NSS_SKB_REUSE_SUPPORT == 1)
+	if (nss_ctx->max_buf_size > nss_core_get_max_reuse())
+		nss_core_set_max_reuse(ALIGN(nss_ctx->max_buf_size * 2, PAGE_SIZE));
+#endif
+
+	nss_info("Current mtu:%u mtu_sz:%u max_buf_size:%d\n", mtu, mtu_sz, nss_ctx->max_buf_size);
+
+	if (mtu_sz > nss_ctx->nss_top->prev_mtu_sz) {
+
+		/* If crypto is enabled on platform
+		 * Send the flush payloads message
+		 */
+		if (nss_ctx->nss_top->crypto_enabled) {
+			if (nss_n2h_flush_payloads(nss_ctx) != NSS_TX_SUCCESS) {
+				nss_info("Unable to send flush payloads command to NSS\n");
+			}
+		}
+	}
+	nss_ctx->nss_top->prev_mtu_sz = mtu_sz;
+
+	return status;
+}
+
+/*
+ * nss_phys_if_vsi_assign()
+ *	Send a vsi assign to physical interface
+ */
+nss_tx_status_t nss_phys_if_vsi_assign(struct nss_ctx_instance *nss_ctx, uint32_t vsi, uint32_t if_num)
+{
+	struct nss_phys_if_msg nim;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	nss_info("%px: Phys If VSI Assign, id:%d\n", nss_ctx, if_num);
+
+	memset(&nim, 0, sizeof(struct nss_phys_if_msg));
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_PHYS_IF_VSI_ASSIGN,
+			sizeof(struct nss_if_vsi_assign), nss_phys_if_callback, NULL);
+
+	nim.msg.if_msg.vsi_assign.vsi = vsi;
+	return nss_phys_if_msg_sync(nss_ctx, &nim);
+}
+
+/*
+ * nss_phys_if_vsi_unassign()
+ *	Send a vsi unassign to physical interface
+ */
+nss_tx_status_t nss_phys_if_vsi_unassign(struct nss_ctx_instance *nss_ctx, uint32_t vsi, uint32_t if_num)
+{
+	struct nss_phys_if_msg nim;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	nss_info("%px: Phys If VSI Unassign, id:%d\n", nss_ctx, if_num);
+
+	memset(&nim, 0, sizeof(struct nss_phys_if_msg));
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_PHYS_IF_VSI_UNASSIGN,
+			sizeof(struct nss_if_vsi_unassign), nss_phys_if_callback, NULL);
+
+	nim.msg.if_msg.vsi_unassign.vsi = vsi;
+	return nss_phys_if_msg_sync(nss_ctx, &nim);
+}
+
+/*
+ * nss_phys_if_pause_on_off()
+ *	Send a pause enabled/disabled message to GMAC
+ */
+nss_tx_status_t nss_phys_if_pause_on_off(struct nss_ctx_instance *nss_ctx, uint32_t pause_on, uint32_t if_num)
+{
+	struct nss_phys_if_msg nim;
+	struct nss_if_pause_on_off *nipe;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	nss_info("%px: phys if pause is set to %d, id:%d\n", nss_ctx, pause_on, if_num);
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_PHYS_IF_PAUSE_ON_OFF,
+			sizeof(struct nss_if_pause_on_off), nss_phys_if_callback, NULL);
+
+	nipe = &nim.msg.if_msg.pause_on_off;
+	nipe->pause_on = pause_on;
+
+	return nss_phys_if_msg_sync(nss_ctx, &nim);
+}
+
+/*
+ * nss_phys_if_reset_nexthop()
+ *	De-configures nexthop for an interface
+ */
+nss_tx_status_t nss_phys_if_reset_nexthop(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_phys_if_msg nim;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_PHYS_IF_RESET_NEXTHOP,
+				0, nss_phys_if_callback, NULL);
+
+	return nss_phys_if_msg_sync(nss_ctx, &nim);
+}
+EXPORT_SYMBOL(nss_phys_if_reset_nexthop);
+
+/*
+ * nss_phys_if_set_nexthop()
+ *	Configures nexthop for an interface
+ */
+nss_tx_status_t nss_phys_if_set_nexthop(struct nss_ctx_instance *nss_ctx, uint32_t if_num, uint32_t nexthop)
+{
+	struct nss_phys_if_msg nim;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (nexthop >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("%px: Invalid nexthop interface number: %d", nss_ctx, nexthop);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	nss_info("%px: Phys If nexthop will be set to %d, id:%d\n", nss_ctx, nexthop, if_num);
+
+	nss_cmn_msg_init(&nim.cm, if_num, NSS_PHYS_IF_SET_NEXTHOP,
+				sizeof(struct nss_if_set_nexthop), nss_phys_if_callback, NULL);
+	nim.msg.if_msg.set_nexthop.nexthop = nexthop;
+
+	return nss_phys_if_msg_sync(nss_ctx, &nim);
+}
+EXPORT_SYMBOL(nss_phys_if_set_nexthop);
+
+/*
+ * nss_get_state()
+ *	Return the NSS initialization state
+ */
+nss_state_t nss_get_state(void *ctx)
+{
+	return nss_cmn_get_state(ctx);
+}
+
+EXPORT_SYMBOL(nss_get_state);
diff --git a/qca-nss-drv/nss_phys_if.h b/qca-nss-drv/nss_phys_if.h
new file mode 100644
index 0000000..0df6bc3
--- /dev/null
+++ b/qca-nss-drv/nss_phys_if.h
@@ -0,0 +1,326 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * nss_phys_if
+ *	Physical interface message structure
+ */
+
+#ifndef __NSS_PHYS_IF_H
+#define __NSS_PHYS_IF_H
+
+/**
+ * Physical IF
+ */
+
+/**
+ * The NSS per-GMAC statistics sync structure.
+ */
+struct nss_phys_if_estats {
+	uint32_t rx_errors;		/**< Number of RX errors */
+	uint32_t rx_receive_errors;	/**< Number of RX receive errors */
+	uint32_t rx_descriptor_errors;	/**< Number of RX descriptor errors */
+	uint32_t rx_late_collision_errors;
+					/**< Number of RX late collision errors */
+	uint32_t rx_dribble_bit_errors;	/**< Number of RX dribble bit errors */
+	uint32_t rx_length_errors;	/**< Number of RX length errors */
+	uint32_t rx_ip_header_errors;	/**< Number of RX IP header errors */
+	uint32_t rx_ip_payload_errors;	/**< Number of RX IP payload errors */
+	uint32_t rx_no_buffer_errors;	/**< Number of RX no-buffer errors */
+	uint32_t rx_transport_csum_bypassed;
+					/**< Number of RX packets where the transport checksum was bypassed */
+	uint32_t tx_collisions;		/**< Number of TX collisions */
+	uint32_t tx_errors;		/**< Number of TX errors */
+	uint32_t tx_jabber_timeout_errors;
+					/**< Number of TX jabber timeout errors */
+	uint32_t tx_frame_flushed_errors;
+					/**< Number of TX frame flushed errors */
+	uint32_t tx_loss_of_carrier_errors;
+					/**< Number of TX loss of carrier errors */
+	uint32_t tx_no_carrier_errors;	/**< Number of TX no carrier errors */
+	uint32_t tx_late_collision_errors;
+					/**< Number of TX late collision errors */
+	uint32_t tx_excessive_collision_errors;
+					/**< Number of TX excessive collision errors */
+	uint32_t tx_excessive_deferral_errors;
+					/**< Number of TX excessive deferral errors */
+	uint32_t tx_underflow_errors;	/**< Number of TX underflow errors */
+	uint32_t tx_ip_header_errors;	/**< Number of TX IP header errors */
+	uint32_t tx_ip_payload_errors;	/**< Number of TX IP payload errors */
+	uint32_t tx_dropped;		/**< Number of TX dropped packets */
+	uint32_t hw_errs[10];		/**< GMAC DMA error counters */
+	uint32_t rx_missed;		/**< Number of RX packets missed by the DMA */
+	uint32_t fifo_overflows;	/**< Number of RX FIFO overflows signalled by the DMA */
+	uint32_t rx_scatter_errors;	/**< Number of scattered frames received by the DMA */
+	uint32_t tx_ts_create_errors;	/**< Number of tx timestamp creation errors */
+	uint32_t gmac_total_ticks;	/**< Total clock ticks spend inside the GMAC */
+	uint32_t gmac_worst_case_ticks;	/**< Worst case iteration of the GMAC in ticks */
+	uint32_t gmac_iterations;	/**< Number of iterations around the GMAC */
+	uint32_t tx_pause_frames;	/**< Number of pause frames sent by the GMAC */
+	uint32_t mmc_rx_overflow_errors;
+					/**< Number of RX overflow errors */
+	uint32_t mmc_rx_watchdog_timeout_errors;
+					/**< Number of RX watchdog timeout errors */
+	uint32_t mmc_rx_crc_errors;	/**< Number of RX CRC errors */
+	uint32_t mmc_rx_ip_header_errors;
+					/**< Number of RX IP header errors */
+	uint32_t mmc_rx_octets_g;		/* Number of good octets received */
+	uint32_t mmc_rx_ucast_frames;	/* Number of Unicast frames received */
+	uint32_t mmc_rx_bcast_frames;	/* Number of Bcast frames received */
+	uint32_t mmc_rx_mcast_frames;	/* Number of Mcast frames received */
+	uint32_t mmc_rx_undersize;	/* Number of RX undersize frames */
+	uint32_t mmc_rx_oversize;	/* Number of RX oversize frames */
+	uint32_t mmc_rx_jabber;		/* Number of jabber frames */
+	uint32_t mmc_rx_octets_gb;	/* Number of good/bad octets */
+	uint32_t mmc_rx_frag_frames_g;	/* Number of good ipv4 frag frames */
+	uint32_t mmc_tx_octets_g;	/* Number of good octets sent */
+	uint32_t mmc_tx_ucast_frames;	/* Number of Unicast frames sent*/
+	uint32_t mmc_tx_bcast_frames;	/* Number of Broadcast frames sent */
+	uint32_t mmc_tx_mcast_frames;	/* Number of Multicast frames sent */
+	uint32_t mmc_tx_deferred;	/* Number of Deferred frames sent */
+	uint32_t mmc_tx_single_col;	/* Number of single collisions */
+	uint32_t mmc_tx_multiple_col;	/* Number of multiple collisions */
+	uint32_t mmc_tx_octets_gb;	/* Number of good/bad octets sent*/
+};
+
+/**
+ * The NSS GMAC statistics sync structure.
+ */
+struct nss_phys_if_stats {
+	struct nss_cmn_node_stats if_stats;		/**< Generic interface stats */
+	struct nss_phys_if_estats estats;	/**< Extended Statistics specific to GMAC */
+};
+
+/**
+ * @brief Request/Response types
+ */
+enum nss_phys_if_msg_types {
+	NSS_PHYS_IF_OPEN = NSS_IF_OPEN,
+	NSS_PHYS_IF_CLOSE = NSS_IF_CLOSE,
+	NSS_PHYS_IF_LINK_STATE_NOTIFY = NSS_IF_LINK_STATE_NOTIFY,
+	NSS_PHYS_IF_MTU_CHANGE = NSS_IF_MTU_CHANGE,
+	NSS_PHYS_IF_MAC_ADDR_SET = NSS_IF_MAC_ADDR_SET,
+	NSS_PHYS_IF_STATS = NSS_IF_STATS,
+	NSS_PHYS_IF_ISHAPER_ASSIGN = NSS_IF_ISHAPER_ASSIGN,
+	NSS_PHYS_IF_BSHAPER_ASSIGN = NSS_IF_BSHAPER_ASSIGN,
+	NSS_PHYS_IF_ISHAPER_UNASSIGN = NSS_IF_ISHAPER_UNASSIGN,
+	NSS_PHYS_IF_BSHAPER_UNASSIGN = NSS_IF_BSHAPER_UNASSIGN,
+	NSS_PHYS_IF_ISHAPER_CONFIG = NSS_IF_ISHAPER_CONFIG,
+	NSS_PHYS_IF_BSHAPER_CONFIG = NSS_IF_BSHAPER_CONFIG,
+	NSS_PHYS_IF_PAUSE_ON_OFF = NSS_IF_PAUSE_ON_OFF,
+	NSS_PHYS_IF_VSI_ASSIGN = NSS_IF_VSI_ASSIGN,
+	NSS_PHYS_IF_VSI_UNASSIGN = NSS_IF_VSI_UNASSIGN,
+	NSS_PHYS_IF_SET_NEXTHOP = NSS_IF_SET_NEXTHOP,
+	NSS_PHYS_IF_RESET_NEXTHOP = NSS_IF_RESET_NEXTHOP,
+	NSS_PHYS_IF_EXTENDED_STATS_SYNC = NSS_IF_MAX_MSG_TYPES + 1,
+	NSS_PHYS_IF_MAX_MSG_TYPES
+};
+
+/**
+ * Message structure to send/receive physical interface commands
+ *
+ * NOTE: Do not adjust the location of if_msg relative to new
+ * message types as it represents the base messages for all
+ * intefaces.
+ */
+struct nss_phys_if_msg {
+	struct nss_cmn_msg cm;				/**< Message Header */
+	union {
+		union nss_if_msgs if_msg;		/**< Interfaces messages */
+		struct nss_phys_if_stats stats;		/**< Phys If Statistics */
+	} msg;
+};
+
+/**
+ * @brief Callback to receive physical interface messages
+ *
+ * @param app_data Application context for this message
+ * @param msg NSS physical interface message
+ *
+ * @return void
+ */
+typedef void (*nss_phys_if_msg_callback_t)(void *app_data, struct nss_phys_if_msg *msg);
+
+/**
+ * @brief Callback to send physical interface data to the tranmsit path.
+ *
+ * @param netdev Net device
+ * @param skb Data buffer
+ *
+ * @return void
+ */
+typedef void (*nss_phys_if_xmit_callback_t)(struct net_device *netdev, struct sk_buff *skb);
+
+/**
+ * @brief Callback to receive physical interface data
+ * 	 TODO: Adjust to pass app_data as unknown to the
+ * 	 list layer and netdev/sk as known.
+ *
+ * @param app_data Application context for this message
+ * @param os_buf Data buffer
+ *
+ * @return void
+ */
+typedef void (*nss_phys_if_rx_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * @brief Callback to recieve extended data plane packet on interface.
+ *
+ * @param app_data Application context for this message
+ * @param skb Data buffer
+ * @param napi napi pointer
+ *
+ * @return void
+ */
+typedef void (*nss_phys_if_rx_ext_data_callback_t)(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi);
+
+/**
+ * @brief Register to send/receive GMAC packets/messages
+ *
+ * @param if_num GMAC i/f number
+ * @param rx_callback Receive callback for packets
+ * @param event_callback Receive callback for events
+ * @param netdev netdevice associated with this interface.
+ * @param features denote the skb types supported by this interface
+ *
+ * @return void* NSS context
+ */
+struct nss_ctx_instance *nss_phys_if_register(uint32_t if_num,
+					nss_phys_if_rx_callback_t rx_callback,
+					nss_phys_if_msg_callback_t msg_callback,
+					struct net_device *netdev,
+					uint32_t features);
+
+/**
+ * @brief Send GMAC packet
+ *
+ * @param nss_ctx NSS context
+ * @param os_buf OS buffer (e.g. skbuff)
+ * @param if_num GMAC i/f number
+ *
+ * @return nss_tx_status_t Tx status
+ */
+nss_tx_status_t nss_phys_if_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, uint32_t if_num);
+
+/**
+ * @brief Send message to physical interface
+ *
+ * @param nim Physical interface message
+ *
+ * @return command Tx status
+ */
+nss_tx_status_t nss_phys_if_msg(struct nss_ctx_instance *nss_ctx, struct nss_phys_if_msg *nim);
+
+/**
+ * @brief Send a message to physical interface & wait for the response.
+ *
+ * @param nim Physical interface message
+ *
+ * @return command Tx status
+ */
+nss_tx_status_t nss_phys_if_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_phys_if_msg *nim);
+
+/**
+ * @brief Open GMAC interface on NSS
+ *
+ * @param nss_ctx NSS context
+ * @param tx_desc_ring Tx descriptor ring address
+ * @param rx_desc_ring Rx descriptor ring address
+ * @param if_num GMAC i/f number
+ * @param bypass_nw_process network processing in nss is bypassed for GMAC
+ *
+ * @return nss_tx_status_t Tx status
+ */
+nss_tx_status_t nss_phys_if_open(struct nss_ctx_instance *nss_ctx, uint32_t tx_desc_ring, uint32_t rx_desc_ring, uint32_t mode, uint32_t if_num,
+								uint32_t bypass_nw_process);
+
+/**
+ * @brief Close GMAC interface on NSS
+ *
+ * @param nss_ctx NSS context
+ * @param if_num GMAC i/f number
+ *
+ * @return nss_tx_status_t Tx status
+ */
+nss_tx_status_t nss_phys_if_close(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+
+/**
+ * @brief Send link state message to NSS
+ *
+ * @param nss_ctx NSS context
+ * @param link_state Link state
+ * @param if_num GMAC i/f number
+ *
+ * @return nss_tx_status_t Tx status
+ */
+nss_tx_status_t nss_phys_if_link_state(struct nss_ctx_instance *nss_ctx, uint32_t link_state, uint32_t if_num);
+
+/**
+ * @brief Send MAC address to NSS
+ *
+ * @param nss_ctx NSS context
+ * @param addr MAC address pointer
+ * @param if_num GMAC i/f number
+ *
+ * @return nss_tx_status_t Tx status
+ */
+nss_tx_status_t nss_phys_if_mac_addr(struct nss_ctx_instance *nss_ctx, uint8_t *addr, uint32_t if_num);
+
+/**
+ * @brief Send MTU change notification to NSS
+ *
+ * @param nss_ctx NSS context
+ * @param mtu MTU
+ * @param if_num GMAC i/f number
+ *
+ * @return nss_tx_status_t Tx status
+ */
+nss_tx_status_t nss_phys_if_change_mtu(struct nss_ctx_instance *nss_ctx, uint32_t mtu, uint32_t if_num);
+
+/**
+ * @brief Send vsi assign to NSS
+ *
+ * @param nss_ctx NSS context
+ * @param vsi VSI number
+ * @param if_num GMAC i/f number
+ *
+ * @return nss_tx_status_t Tx status
+ */
+nss_tx_status_t nss_phys_if_vsi_assign(struct nss_ctx_instance *nss_ctx, uint32_t vsi, uint32_t if_num);
+
+/**
+ * @brief Send vsi unassign to NSS
+ *
+ * @param nss_ctx NSS context
+ * @param vsi VSI number
+ * @param if_num GMAC i/f number
+ *
+ * @return nss_tx_status_t Tx status
+ */
+nss_tx_status_t nss_phys_if_vsi_unassign(struct nss_ctx_instance *nss_ctx, uint32_t vsi, uint32_t if_num);
+
+/**
+ * @brief Send pause frame enabled notification to NSS
+ *
+ * @param nss_ctx NSS context
+ * @param pause_on Pause on or off
+ * @param if_num GMAC i/f number
+ *
+ * @return nss_tx_status_t Tx status
+ */
+nss_tx_status_t nss_phys_if_pause_on_off(struct nss_ctx_instance *nss_ctx, uint32_t pause_on, uint32_t if_num);
+
+#endif /* __NSS_PHYS_IF_H */
diff --git a/qca-nss-drv/nss_pm.c b/qca-nss-drv/nss_pm.c
new file mode 100644
index 0000000..75527cd
--- /dev/null
+++ b/qca-nss-drv/nss_pm.c
@@ -0,0 +1,447 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_pm.c
+ *    NSS Power Management APIs
+ *
+ */
+#include <linux/debugfs.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <nss_api_if.h>
+#include <nss_core.h>
+
+#if (NSS_DT_SUPPORT != 1)
+#include <nss_clocks.h>
+#endif
+
+#if (NSS_PM_SUPPORT == 1)
+#include "nss_pm.h"
+
+/*
+ * Global NSS PM structure
+ */
+struct nss_pm_global_ctx ctx;
+
+/*
+ * Bus vector table for GMAC driver
+ */
+static struct msm_bus_paths nss_gmac_bw_level_tbl[NSS_PM_PERF_MAX_LEVELS] = {
+		[NSS_PM_PERF_LEVEL_SUSPEND] =  GMAC_BW_MBPS(0, 0),
+				/* 0 MHz to DDR, 0 MHz to TCM */
+		[NSS_PM_PERF_LEVEL_IDLE] =  GMAC_BW_MBPS(133, 5),
+				/* 133 MHz to DDR, 5 MHz to TCM */
+		[NSS_PM_PERF_LEVEL_NOMINAL] =  GMAC_BW_MBPS(200, 400),
+				/* 200 MHz to DDR, 10 MHz to TCM */
+		[NSS_PM_PERF_LEVEL_TURBO] = GMAC_BW_MBPS(266, 533),
+				/* 266 MHz to DDR, 20 MHz to TCM  */
+};
+
+/*
+ * Bus vector table for Crypto driver
+ */
+static struct msm_bus_paths nss_crypto_bw_level_tbl[NSS_PM_PERF_MAX_LEVELS] = {
+		[NSS_PM_PERF_LEVEL_SUSPEND] =  CRYPTO_BW_MBPS(0, 0),
+				/* 0 MHz to DDR, 0 MHz to TCM */
+		[NSS_PM_PERF_LEVEL_IDLE] =  CRYPTO_BW_MBPS(133, 5),
+				/* 133 MHz to DDR, 5 MHz to TCM */
+		[NSS_PM_PERF_LEVEL_NOMINAL] =  CRYPTO_BW_MBPS(200, 400),
+				/* 200 MHz to DDR, 10 MHz to TCM */
+		[NSS_PM_PERF_LEVEL_TURBO] = CRYPTO_BW_MBPS(266, 533),
+				/* 266 MHz to DDR, 20 MHz to TCM  */
+};
+
+#ifdef  NSS_PM_NETAP_GMAC_SCALING
+
+/*
+ * Bus vector table for NSS HLOS driver
+ * This requests bw for both NSS Fab0 and Fab1 on behalf of GMAC and NSS Drivers
+ */
+static struct msm_bus_paths nss_netap_bw_level_tbl[NSS_PM_PERF_MAX_LEVELS] = {
+		[NSS_PM_PERF_LEVEL_SUSPEND] =  GMAC_BW_MBPS(0, 0),
+			/* 0 MHz to DDR, 0 MHz to TCM */
+		[NSS_PM_PERF_LEVEL_IDLE] =  GMAC_BW_MBPS(122, 122),
+			/* 133 MHz to DDR and TCM */
+		[NSS_PM_PERF_LEVEL_NOMINAL] =  GMAC_BW_MBPS(200, 200),
+			/* 400 MHz to DDR and TCM */
+		[NSS_PM_PERF_LEVEL_TURBO] = GMAC_BW_MBPS(400, 400),
+			/* 533 MHz to DDR and TCM  */
+};
+
+#else
+
+/*
+ * Bus vector table for NSS HLOS driver
+ */
+static struct msm_bus_paths nss_netap_bw_level_tbl[NSS_PM_PERF_MAX_LEVELS] = {
+		[NSS_PM_PERF_LEVEL_SUSPEND] =  NETAP_BW_MBPS(0, 0),
+			/* 0 MHz to DDR, 0 MHz to TCM */
+		[NSS_PM_PERF_LEVEL_IDLE] =  NETAP_BW_MBPS(133, 133),
+			/* 133 MHz to DDR and TCM */
+		[NSS_PM_PERF_LEVEL_NOMINAL] =  NETAP_BW_MBPS(400, 400),
+			/* 400 MHz to DDR and TCM */
+		[NSS_PM_PERF_LEVEL_TURBO] = NETAP_BW_MBPS(533, 533),
+			/* 533 MHz to DDR and TCM  */
+};
+
+#endif
+
+/*
+ * Bus Driver Platform data for GMAC, Crypto and Netap clients
+ */
+static struct msm_bus_scale_pdata nss_bus_scale[] = {
+	[NSS_PM_CLIENT_GMAC] = {
+		.usecase = nss_gmac_bw_level_tbl,
+		.num_usecases = ARRAY_SIZE(nss_gmac_bw_level_tbl),
+		.active_only = 1,
+		.name = "qca-nss-gmac",
+	},
+
+	[NSS_PM_CLIENT_CRYPTO] = {
+		.usecase = nss_crypto_bw_level_tbl,
+		.num_usecases = ARRAY_SIZE(nss_crypto_bw_level_tbl),
+		.active_only = 1,
+		.name = "qca-nss-crypto",
+	},
+
+	[NSS_PM_CLIENT_NETAP] = {
+		.usecase = nss_netap_bw_level_tbl,
+		.num_usecases = ARRAY_SIZE(nss_netap_bw_level_tbl),
+		.active_only = 1,
+		.name = "qca-nss-drv",
+	},
+};
+
+/*
+ * nss_pm_dbg_perf_level_get
+ *    debugfs hook to get the current performance level
+ */
+static int nss_pm_dbg_perf_level_get(void *data, u64 *val)
+{
+	nss_pm_client_data_t *pm_client;
+
+	pm_client = (nss_pm_client_data_t *)data;
+	*val = pm_client->current_perf_lvl;
+
+	return NSS_PM_API_SUCCESS;
+}
+
+/*
+ * nss_pm_dbg_autoscale_get
+ *    debugfs hook to get the current autoscale setting
+ */
+static int nss_pm_dbg_autoscale_get(void *data, u64 *val)
+{
+	nss_pm_client_data_t *pm_client;
+
+	pm_client = (nss_pm_client_data_t *)data;
+	*val = pm_client->auto_scale;
+
+	return NSS_PM_API_SUCCESS;
+}
+
+/*
+ * nss_pm_dbg_perf_level_set
+ *    debugfs hook to set perf level for a client
+ */
+static int nss_pm_dbg_perf_level_set(void *data, u64 val)
+{
+	uint32_t perf_level;
+
+	perf_level = (uint32_t) val;
+
+	if (perf_level >= NSS_PM_PERF_MAX_LEVELS ||
+			perf_level < NSS_PM_PERF_LEVEL_IDLE) {
+		nss_pm_warning("unsupported performance level %d \n", perf_level);
+		return NSS_PM_API_FAILED;
+	}
+
+	nss_pm_set_perf_level(data, perf_level);
+	return NSS_PM_API_SUCCESS;
+}
+
+/*
+ * nss_pm_dbg_autoscale_set
+ *    debugfs hook to enable auto scaling for a client
+ */
+static int nss_pm_dbg_autoscale_set(void *data, u64 val)
+{
+	nss_pm_client_data_t *pm_client;
+
+	if (val > 1) {
+		nss_pm_warning(" Invalid set value, valid values are 0/1 \n");
+		return NSS_PM_API_FAILED;
+	}
+
+	pm_client->auto_scale = (uint32_t)val;
+	return NSS_PM_API_SUCCESS;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(perf_level_fops, nss_pm_dbg_perf_level_get, nss_pm_dbg_perf_level_set, "%llu\n");
+
+DEFINE_SIMPLE_ATTRIBUTE(autoscale_fops, nss_pm_dbg_autoscale_get, nss_pm_dbg_autoscale_set, "%llu\n");
+#endif /** (NSS_PM_SUPPORT == 1) */
+
+/*
+ * nss_pm_client_register
+ *    Initialize GMAC specific PM parameters
+ *
+ * Creates debugfs hooks for user-space control of NSS Client PM
+ * Initializes Bus BW to Idle Perf level
+ * Returns PM handle to the caller.
+ *
+ */
+void *nss_pm_client_register(nss_pm_client_t client_id)
+{
+#if (NSS_PM_SUPPORT == 1)
+	int ret;
+	struct dentry *pm_dentry;
+	nss_pm_client_data_t *pm_client;
+
+	if (unlikely(client_id >= NSS_PM_MAX_CLIENTS))  {
+		nss_pm_warning("nss_pm_client_register invalid client id %d \n", client_id);
+		goto error;
+	}
+
+	pm_client  =  &ctx.nss_pm_client[client_id];
+
+	pm_client->bus_perf_client = msm_bus_scale_register_client(&nss_bus_scale[client_id]);
+	if (!pm_client->bus_perf_client) {
+		nss_pm_warning("unable to register bus client \n");
+		goto error;
+	}
+
+	ret = msm_bus_scale_client_update_request(pm_client->bus_perf_client, NSS_PM_PERF_LEVEL_IDLE);
+	if (ret) {
+		nss_pm_warning("initial bandwidth req failed (%d)\n", ret);
+		msm_bus_scale_unregister_client((uint32_t) pm_client->bus_perf_client);
+		goto error;
+	}
+
+	pm_client->current_perf_lvl = NSS_PM_PERF_LEVEL_IDLE;
+
+	switch (client_id) {
+		case NSS_PM_CLIENT_GMAC:
+			pm_dentry = debugfs_create_dir("gmac" , ctx.pm_dentry);
+			break;
+
+		case NSS_PM_CLIENT_CRYPTO:
+			pm_dentry = debugfs_create_dir("crypto" , ctx.pm_dentry);
+			break;
+
+		case NSS_PM_CLIENT_NETAP:
+			pm_dentry = debugfs_create_dir("netap" , ctx.pm_dentry);
+			break;
+
+		default:
+			nss_pm_warning("debugfs create failed invalid client id %d \n", client_id);
+			msm_bus_scale_unregister_client((uint32_t) pm_client->bus_perf_client);
+			goto error;
+
+	}
+
+	if (unlikely(pm_dentry == NULL)) {
+		nss_pm_info("debugfs not created for %d client pm \n", client_id);
+		goto out;
+	}
+
+	pm_client->dentry = pm_dentry;
+	pm_client->client_id = client_id;
+
+	if (!debugfs_create_file("perf_level", S_IRUGO | S_IWUSR, pm_dentry, pm_client, &perf_level_fops)) {
+		nss_pm_info("debugfs perf_level file not created for %d client pm \n", client_id);
+	}
+
+	if (!debugfs_create_file("auto-scale", S_IRUGO | S_IWUSR, pm_dentry, pm_client, &autoscale_fops)) {
+		nss_pm_info("debugfs auto-scale file not created for %d client pm \n", client_id);
+	}
+
+out:
+	return (void *)pm_client;
+error:
+#endif
+	return NULL;
+}
+EXPORT_SYMBOL(nss_pm_client_register);
+
+/*
+ * nss_pm_client_unregister
+ *    Unregister the client for any PM operations
+ */
+int nss_pm_client_unregister(nss_pm_client_t client_id)
+{
+#if (NSS_PM_SUPPORT == 1)
+	nss_pm_client_data_t *pm_client;
+
+	if (unlikely(client_id >= NSS_PM_MAX_CLIENTS))  {
+		nss_pm_warning("nss_pm_client_unregister invalid client id %d \n", client_id);
+		goto error;
+	}
+
+	pm_client  =  &ctx.nss_pm_client[client_id];
+
+	if (unlikely(pm_client == NULL))  {
+		nss_pm_warning("nss_pm_client_unregister client not registered %d \n", client_id);
+		goto error;
+	}
+
+	if (pm_client->bus_perf_client) {
+		msm_bus_scale_unregister_client((uint32_t) pm_client->bus_perf_client);
+	} else {
+		nss_pm_info("nss_pm_client_unregister: client not registered \n");
+	}
+
+	if (likely(pm_client->dentry != NULL)) {
+		debugfs_remove_recursive(pm_client->dentry);
+	}
+
+	return NSS_PM_API_SUCCESS;
+
+error:
+#endif
+	return NSS_PM_API_FAILED;
+}
+
+/*
+ * nss_pm_set_perf_level()
+ *    Sets the performance level of client specific Fabrics and Clocks to requested level
+ */
+nss_pm_interface_status_t nss_pm_set_perf_level(void *handle, nss_pm_perf_level_t lvl)
+{
+#if ((NSS_DT_SUPPORT == 1) && (NSS_FREQ_SCALE_SUPPORT == 1))
+	nss_freq_scales_t index;
+
+	switch (lvl) {
+	case NSS_PM_PERF_LEVEL_TURBO:
+		index = NSS_FREQ_HIGH_SCALE;
+		break;
+
+	case NSS_PM_PERF_LEVEL_NOMINAL:
+		index = NSS_FREQ_MID_SCALE;
+		break;
+
+	default:
+		index = NSS_PM_PERF_LEVEL_IDLE;
+	}
+
+#if !defined(NSS_HAL_IPQ807x_SUPPORT)
+	nss_freq_sched_change(index, false);
+#endif
+
+#elif (NSS_PM_SUPPORT == 1)
+
+	int ret = 0;
+	nss_pm_client_data_t *pm_client;
+
+	pm_client = (nss_pm_client_data_t *) handle;
+	if (pm_client->current_perf_lvl == lvl) {
+		nss_pm_trace("Already at perf level %d , ignoring request \n", lvl);
+		return NSS_PM_API_SUCCESS;
+	}
+
+	if (!pm_client->bus_perf_client) {
+		nss_pm_warning("Bus driver client not registered.request failed \n");
+		return NSS_PM_API_FAILED;
+	}
+
+	/*
+	 * Do client specific operations here
+	 */
+	if (pm_client->client_id == NSS_PM_CLIENT_NETAP) {
+		if ((lvl == NSS_PM_PERF_LEVEL_TURBO) && (ctx.turbo_support == true)) {
+			/*
+			 * For turbo perf level, switch TCM source to
+			 * SRC1 to set TCM clock = 400 MHz
+			 * SRC0 and SRC1 are set to 266 and 400 MHz resp.
+			 * in nss_hal/ipq806x/nss_hal_pvt.c
+			 */
+			writel(0x3, NSSTCM_CLK_SRC_CTL);
+		} else {
+			/*
+			 * For Nominal and Idle perf level, switch to SRC0 to
+			 * set TCM clock = 266 MHz
+			 */
+			writel(0x2, NSSTCM_CLK_SRC_CTL);
+
+			if (lvl == NSS_PM_PERF_LEVEL_TURBO) {
+				lvl = NSS_PM_PERF_LEVEL_NOMINAL;
+			}
+		}
+	}
+
+	if (pm_client->client_id == NSS_PM_CLIENT_CRYPTO) {
+		if ((lvl == NSS_PM_PERF_LEVEL_TURBO) && (ctx.turbo_support == true))  {
+			/*
+			 * For Turbo mode, set Crypto core and
+			 * Fabric  port clocks to 213 MHz
+			 */
+			writel(0x23, CE5_ACLK_SRC0_NS);
+			writel(0x23, CE5_HCLK_SRC0_NS);
+			writel(0x23, CE5_CORE_CLK_SRC0_NS);
+
+			writel(0x2, CE5_ACLK_SRC_CTL);
+			writel(0x2, CE5_HCLK_SRC_CTL);
+			writel(0x2, CE5_CORE_CLK_SRC_CTL);
+		} else {
+			lvl = NSS_PM_PERF_LEVEL_NOMINAL;
+		}
+	}
+
+	/* Update bandwidth if request has changed. This may sleep. */
+	ret = msm_bus_scale_client_update_request(pm_client->bus_perf_client, lvl);
+	if (ret) {
+		nss_pm_warning("bandwidth request failed (%d)\n", ret);
+		return NSS_PM_API_FAILED;
+	}
+
+	nss_pm_info("perf level request, current: %d new: %d \n", pm_client->current_perf_lvl, lvl);
+	pm_client->current_perf_lvl = lvl;
+#endif
+
+	return NSS_PM_API_SUCCESS;
+}
+EXPORT_SYMBOL(nss_pm_set_perf_level);
+
+#if (NSS_PM_SUPPORT == 1)
+/*
+ * nss_pm_set_turbo()
+ *   Sets the turbo support flag globally for all clients
+ */
+void nss_pm_set_turbo() {
+
+	nss_pm_info("NSS Bus PM - Platform supports Turbo Mode \n");
+	ctx.turbo_support = true;
+}
+
+/*
+ * nss_pm_init()
+ *    Initialize NSS PM top level structures
+ */
+void nss_pm_init(void) {
+
+	nss_pm_info("NSS Bus PM (platform - IPQ806x, build - %s:%s)\n", __DATE__, __TIME__);
+
+	ctx.pm_dentry = debugfs_create_dir("qca-nss-pm", NULL);
+
+	/* Default turbo support is set to off */
+	ctx.turbo_support = false;
+
+	if (unlikely(ctx.pm_dentry == NULL)) {
+		nss_pm_warning("Failed to create qca-nss-drv directory in debugfs");
+	}
+}
+#endif
diff --git a/qca-nss-drv/nss_pm.h b/qca-nss-drv/nss_pm.h
new file mode 100644
index 0000000..aaca293
--- /dev/null
+++ b/qca-nss-drv/nss_pm.h
@@ -0,0 +1,164 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_pm.h
+ *    NSS PM Driver header file
+ */
+
+#ifndef __NSS_PM_H
+#define __NSS_PM_H
+
+#include<linux/version.h>
+
+#include <mach/msm_nss_gmac.h>
+#include <mach/msm_nss_crypto.h>
+#include <mach/msm_bus_board.h>
+#include <mach/msm_bus.h>
+
+#include <nss_api_if.h>
+
+/*
+ * NSS PM debug macros
+ */
+#if (NSS_PM_DEBUG_LEVEL < 1)
+#define nss_pm_assert(fmt, args...)
+#else
+#define nss_pm_assert(c) if (!(c)) { BUG_ON(!(c)); }
+#endif
+
+#if (NSS_PM_DEBUG_LEVEL < 2)
+#define nss_pm_warning(fmt, args...)
+#else
+#define nss_pm_warning(fmt, args...) printk(KERN_WARNING "nss_pm:"fmt, ##args)
+#endif
+
+#if (NSS_PM_DEBUG_LEVEL < 3)
+#define nss_pm_info(fmt, args...)
+#else
+#define nss_pm_info(fmt, args...) printk(KERN_INFO "nss_pm:"fmt, ##args)
+#endif
+
+#if (NSS_PM_DEBUG_LEVEL < 4)
+#define nss_pm_trace(fmt, args...)
+#else
+#define nss_pm_trace(fmt, args...) printk(KERN_DEBUG "nss_pm:"fmt, ##args)
+#endif
+
+/*
+ * Define this to use NETAP driver also request for NSS Fab1 BW on behalf of GMAC driver
+ */
+#define NSS_PM_NETAP_GMAC_SCALING 1
+
+/*
+ * PM Client data structure
+ */
+typedef struct {
+	uint32_t bus_perf_client;
+	uint32_t clk_handle;
+	uint32_t current_perf_lvl;
+	uint32_t auto_scale;
+	struct dentry *dentry;
+	nss_pm_client_t client_id;
+} nss_pm_client_data_t;
+
+/*
+ * NSS PM driver context
+ */
+struct nss_pm_global_ctx {
+	struct dentry *pm_dentry;
+	bool turbo_support;
+	nss_pm_client_data_t nss_pm_client[NSS_PM_MAX_CLIENTS];
+};
+
+/*
+ * Macro defining Bus vector for GMAC driver
+ */
+#define GMAC_BW_MBPS(_data_bw, _desc_bw) \
+{ \
+	.vectors = (struct msm_bus_vectors[]){ \
+		{\
+			.src = MSM_BUS_MASTER_NSS_GMAC_0, \
+			.dst = MSM_BUS_SLAVE_EBI_CH0, \
+			.ab = (_data_bw) * 16 * 1000000ULL, \
+			.ib = (_data_bw) * 16 * 1000000ULL, \
+		}, \
+		{ \
+			.src =  MSM_BUS_MASTER_NSS_GMAC_0, \
+			.dst = MSM_BUS_SLAVE_NSS_TCM, \
+			.ab = (_desc_bw) * 8 * 1000000ULL, \
+			.ib = (_desc_bw) * 8 * 1000000ULL, \
+		}, \
+	}, \
+	.num_paths = 2, \
+}
+
+/*
+ *  Macro defining Bus vector for NSS crypto driver
+ */
+#define CRYPTO_BW_MBPS(_data_bw, _desc_bw) \
+{ \
+	.vectors = (struct msm_bus_vectors[]){ \
+		{\
+			.src = MSM_BUS_MASTER_NSS_CRYPTO5_0, \
+			.dst = MSM_BUS_SLAVE_EBI_CH0, \
+			.ab = 0, \
+			.ib = 0, \
+		}, \
+		{ \
+			.src =  MSM_BUS_MASTER_NSS_CRYPTO5_0, \
+			.dst = MSM_BUS_SLAVE_NSS_TCM, \
+			.ab = (_desc_bw) * 8 * 1000000ULL, \
+			.ib = (_desc_bw) * 8 * 1000000ULL, \
+		}, \
+	}, \
+	.num_paths = 2, \
+}
+
+/*
+ * Macro defining Bus vector for NSS driver
+ *
+ */
+#define NETAP_BW_MBPS(_data_bw, _desc_bw) \
+{ \
+	.vectors = (struct msm_bus_vectors[]){ \
+		{\
+			.src = MSM_BUS_MASTER_UBI32_0, \
+			.dst = MSM_BUS_SLAVE_EBI_CH0, \
+			.ab = (_data_bw) * 16 * 1000000ULL, \
+			.ib = (_data_bw) * 16 * 1000000ULL, \
+		}, \
+		{ \
+			.src = MSM_BUS_MASTER_UBI32_0, \
+			.dst = MSM_BUS_SLAVE_NSS_TCM, \
+			.ab = (_desc_bw) * 8 * 1000000ULL, \
+			.ib = (_desc_bw) * 8 * 1000000ULL, \
+		}, \
+	}, \
+	.num_paths = 2, \
+}
+
+/*
+ * Initialize NSS PM top level structures
+ */
+void nss_pm_init(void);
+
+/*
+ * Sets the turbo support flag globally for all PM clients
+ */
+void nss_pm_set_turbo(void);
+
+#endif  /** __NSS_PM_H */
diff --git a/qca-nss-drv/nss_portid.c b/qca-nss-drv/nss_portid.c
new file mode 100644
index 0000000..65982f0
--- /dev/null
+++ b/qca-nss-drv/nss_portid.c
@@ -0,0 +1,423 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_portid_stats.h"
+#include "nss_portid_log.h"
+
+/*
+ * Spinlock to protect portid interface create/destroy/update
+ */
+DEFINE_SPINLOCK(nss_portid_spinlock);
+
+#define NSS_PORTID_TX_TIMEOUT 3000 /* 3 Seconds */
+
+/*
+ * Private data structure for phys_if interface
+ */
+static struct nss_portid_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+} pid;
+
+/*
+ * Array of portid interface handles. Indexing based on the physical port_id
+ */
+struct nss_portid_handle nss_portid_hdl[NSS_PORTID_MAX_SWITCH_PORT];
+
+/*
+ * nss_portid_handler()
+ * 	Handle NSS -> HLOS messages for portid
+ */
+static void nss_portid_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm,
+				__attribute__((unused))void *app_data)
+{
+	nss_portid_msg_callback_t cb;
+	struct nss_portid_msg *npm = (struct nss_portid_msg *)ncm;
+
+	BUG_ON(ncm->interface != NSS_PORTID_INTERFACE);
+
+	/*
+	 * Trace Messages
+	 */
+	nss_portid_log_rx_msg(npm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_PORTID_MAX_MSG_TYPE) {
+		nss_warning("%px: received invalid message %d for portid interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_portid_msg)) {
+		nss_warning("%px: message size incorrect: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	switch (ncm->type) {
+	case NSS_PORTID_STATS_SYNC_MSG:
+		/*
+		 * Update portid statistics.
+		 */
+		nss_portid_stats_sync(nss_ctx, &npm->msg.stats_sync);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, portid sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->subsys_dp_register[ncm->interface].ndev;
+	}
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_portid_msg_callback_t)ncm->cb;
+
+	cb((void *)ncm->app_data, npm);
+}
+
+/*
+ * nss_portid_get_ctx()
+ *	Return a portid's NSS context.
+ */
+struct nss_ctx_instance *nss_portid_get_ctx(void)
+{
+	struct nss_ctx_instance *nss_ctx;
+
+	nss_ctx = &nss_top_main.nss[nss_top_main.portid_handler_id];
+	return nss_ctx;
+}
+
+/*
+ * nss_portid_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static bool nss_portid_verify_if_num(uint32_t if_num)
+{
+	if (nss_is_dynamic_interface(if_num) == false) {
+		return false;
+	}
+
+	if (nss_dynamic_interface_get_type(nss_portid_get_ctx(), if_num) != NSS_DYNAMIC_INTERFACE_TYPE_PORTID) {
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_portid_get_stats()
+ *	API for getting stats from a port interface
+ */
+bool nss_portid_get_stats(uint32_t if_num, struct rtnl_link_stats64 *stats)
+{
+	int i;
+
+	spin_lock_bh(&nss_portid_spinlock);
+	for (i = 0; i < NSS_PORTID_MAX_SWITCH_PORT; i++) {
+		if (nss_portid_hdl[i].if_num == if_num) {
+			memcpy(stats, &nss_portid_hdl[i].stats, sizeof(*stats));
+			spin_unlock_bh(&nss_portid_spinlock);
+			return true;
+		}
+	}
+	spin_unlock_bh(&nss_portid_spinlock);
+	return false;
+}
+EXPORT_SYMBOL(nss_portid_get_stats);
+
+/*
+ * nss_portid_if_tx_data()
+ *	Transmit data buffer (skb) to a NSS interface number
+ */
+nss_tx_status_t nss_portid_if_tx_data(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, uint32_t if_num)
+{
+	return nss_if_tx_buf(nss_ctx, os_buf, if_num);
+}
+EXPORT_SYMBOL(nss_portid_if_tx_data);
+
+/*
+ * nss_portid_tx_msg()
+ * 	Transmit a portid message to NSSFW
+ */
+nss_tx_status_t nss_portid_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_portid_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_portid_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (ncm->interface != NSS_PORTID_INTERFACE) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_PORTID_MAX_MSG_TYPE) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_portid_tx_msg);
+
+/*
+ * nss_portid_callback
+ *	Callback to handle the completion of NSS ->HLOS messages.
+ */
+static void nss_portid_callback(void *app_data, struct nss_portid_msg *npm)
+{
+	if(npm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("portid error response %d\n", npm->cm.response);
+		pid.response = NSS_TX_FAILURE;
+		complete(&pid.complete);
+		return;
+	}
+
+	pid.response = NSS_TX_SUCCESS;
+	complete(&pid.complete);
+}
+
+/*
+ * nss_portid_tx_msg_sync()
+ *	Send a message to portid interface & wait for the response.
+ */
+nss_tx_status_t nss_portid_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_portid_msg *msg)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&pid.sem);
+
+	status = nss_portid_tx_msg(nss_ctx, msg);
+	if(status != NSS_TX_SUCCESS)
+	{
+		nss_warning("%px: nss_phys_if_msg failed\n", nss_ctx);
+		up(&pid.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&pid.complete, msecs_to_jiffies(NSS_PORTID_TX_TIMEOUT));
+
+	if(!ret)
+	{
+		nss_warning("%px: portid tx failed due to timeout\n", nss_ctx);
+		pid.response = NSS_TX_FAILURE;
+	}
+
+	status = pid.response;
+	up(&pid.sem);
+
+	return status;
+}
+EXPORT_SYMBOL(nss_portid_tx_msg_sync);
+
+/*
+ * nss_portid_msg_init()
+ *	Initialize portid message.
+ */
+void nss_portid_msg_init(struct nss_portid_msg *npm, uint16_t if_num, uint32_t type, uint32_t len,
+				nss_portid_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&npm->cm, if_num, type, len, (void*)cb, app_data);
+}
+EXPORT_SYMBOL(nss_portid_msg_init);
+
+/*
+ * nss_portid_tx_configure_port_if_msg
+ *	API to send configure port message to NSS FW
+ */
+nss_tx_status_t nss_portid_tx_configure_port_if_msg(struct nss_ctx_instance *nss_ctx, uint32_t port_if_num, uint8_t port_id, uint8_t gmac_id)
+{
+	struct nss_portid_msg npm;
+	struct nss_portid_configure_msg *npcm;
+
+	if (nss_portid_verify_if_num(port_if_num) == false) {
+		nss_warning("received invalid interface %d", port_if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	if (port_id >= NSS_PORTID_MAX_SWITCH_PORT) {
+		nss_warning("port_id %d exceeds NSS_PORTID_MAX_SWITCH_PORT\n", port_id);
+		return NSS_TX_FAILURE;
+	}
+
+	if (gmac_id >= NSS_MAX_PHYSICAL_INTERFACES) {
+		nss_warning("gmac_id %d not valid\n", gmac_id);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Prepare message to configure a port interface
+	 */
+	npcm = &npm.msg.configure;
+	npcm->port_if_num = port_if_num;
+	npcm->port_id = port_id;
+	npcm->gmac_id = gmac_id;
+
+	nss_portid_msg_init(&npm, NSS_PORTID_INTERFACE, NSS_PORTID_CONFIGURE_MSG,
+				sizeof(struct nss_portid_configure_msg), nss_portid_callback, NULL);
+	nss_info("Dynamic interface allocated, sending message to FW with port_if_num %d port_id %d gmac_id %d\n",
+									npcm->port_if_num, npcm->port_id, npcm->gmac_id);
+	return nss_portid_tx_msg_sync(nss_ctx, &npm);
+}
+EXPORT_SYMBOL(nss_portid_tx_configure_port_if_msg);
+
+/*
+ * nss_portid_tx_unconfigure_port_if_msg
+ *	API to send unconfigure port message to NSS FW
+ */
+nss_tx_status_t nss_portid_tx_unconfigure_port_if_msg(struct nss_ctx_instance *nss_ctx, uint32_t port_if_num, uint8_t port_id)
+{
+	struct nss_portid_msg npm;
+	struct nss_portid_unconfigure_msg *npum;
+
+	if (nss_portid_verify_if_num(port_if_num) == false) {
+		nss_warning("received invalid interface %d", port_if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	if (port_id >= NSS_PORTID_MAX_SWITCH_PORT) {
+		nss_warning("port_id %d exceeds NSS_PORTID_MAX_SWITCH_PORT\n", port_id);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Prepare message to unconfigure a port interface
+	 */
+	npum = &npm.msg.unconfigure;
+	npum->port_if_num = port_if_num;
+	npum->port_id = port_id;
+
+	nss_portid_msg_init(&npm, NSS_PORTID_INTERFACE, NSS_PORTID_UNCONFIGURE_MSG,
+				sizeof(struct nss_portid_configure_msg), nss_portid_callback, NULL);
+
+	return nss_portid_tx_msg_sync(nss_ctx, &npm);
+}
+EXPORT_SYMBOL(nss_portid_tx_unconfigure_port_if_msg);
+
+/*
+ * nss_portid_register_port_if()
+ *	Register with portid node and get back nss_ctx
+ */
+struct nss_ctx_instance *nss_portid_register_port_if(uint32_t if_num, uint32_t port_id, struct net_device *netdev,
+						nss_portid_buf_callback_t buf_callback)
+{
+	struct nss_ctx_instance *nss_ctx = nss_portid_get_ctx();
+
+	if (nss_portid_verify_if_num(if_num) == false) {
+		nss_warning("nss portid register received invalid interface %d", if_num);
+		return NULL;
+	}
+
+	if (port_id >= NSS_PORTID_MAX_SWITCH_PORT) {
+		nss_warning("nss portid register received invalid port number %d", port_id);
+		return NULL;
+	}
+
+	spin_lock(&nss_portid_spinlock);
+	if (nss_portid_hdl[port_id].if_num != 0) {
+		nss_warning("nss portid failed: port already registered %d", port_id);
+		spin_unlock(&nss_portid_spinlock);
+		return NULL;
+	}
+	nss_portid_hdl[port_id].if_num = if_num;
+	spin_unlock(&nss_portid_spinlock);
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, buf_callback, NULL, NULL, netdev, 0);
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_portid_register_port_if);
+
+/*
+ * nss_portid_unregister_port_if()
+ *	Unregister portid node with NSS FW
+ */
+bool nss_portid_unregister_port_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx;
+	int i;
+
+	nss_ctx = nss_portid_get_ctx();
+	if (nss_portid_verify_if_num(if_num) == false) {
+		nss_warning("%px: unregister received for invalid interface %d", nss_ctx, if_num);
+		return false;
+	}
+
+	spin_lock(&nss_portid_spinlock);
+	for (i = 0; i < NSS_PORTID_MAX_SWITCH_PORT; i++) {
+		if (nss_portid_hdl[i].if_num == if_num) {
+			nss_portid_hdl[i].if_num = 0;
+		}
+	}
+	spin_unlock(&nss_portid_spinlock);
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	return true;
+}
+EXPORT_SYMBOL(nss_portid_unregister_port_if);
+
+/*
+ * nss_portid_init()
+ *	Initializes portid node. Gets called from nss_init.c
+ */
+void nss_portid_init(void)
+{
+	memset(&nss_portid_hdl, 0, sizeof(struct nss_portid_handle) * NSS_PORTID_MAX_SWITCH_PORT);
+}
+
+/*
+ * nss_portid_register_handler()
+ *	Registering handler for sending msg to portid node on NSS.
+ */
+void nss_portid_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_portid_get_ctx();
+
+	nss_core_register_handler(nss_ctx, NSS_PORTID_INTERFACE, nss_portid_handler, NULL);
+
+	nss_portid_stats_dentry_create();
+
+	sema_init(&pid.sem, 1);
+	init_completion(&pid.complete);
+}
diff --git a/qca-nss-drv/nss_portid_log.c b/qca-nss-drv/nss_portid_log.c
new file mode 100644
index 0000000..700e118
--- /dev/null
+++ b/qca-nss-drv/nss_portid_log.c
@@ -0,0 +1,129 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_portid_log.c
+ *	NSS PORTID logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_portid_log_message_types_str
+ *	NSS PORTID message strings
+ */
+static int8_t *nss_portid_log_message_types_str[NSS_PORTID_MAX_MSG_TYPE] __maybe_unused = {
+	"PORTID Configure",
+	"PORTID Unconfigure",
+	"PORTID Stats",
+};
+
+/*
+ * nss_portid_log_configure_msg()
+ *	Log NSS PORTID Configure.
+ */
+static void nss_portid_log_configure_msg(struct nss_portid_msg *npm)
+{
+	struct nss_portid_configure_msg *npcm __maybe_unused = &npm->msg.configure;
+	nss_trace("%px: NSS PORTID Configure message \n"
+		"PORTID Interface Number: %d\n"
+		"PORTID Interface ID: %d\n"
+		"PORTID GMAC ID: %d\n",
+		npcm, npcm->port_if_num,
+		npcm->port_id, npcm->gmac_id);
+}
+
+/*
+ * nss_portid_log_unconfigure_msg()
+ *	Log NSS PORTID Unconfigure.
+ */
+static void nss_portid_log_unconfigure_msg(struct nss_portid_msg *npm)
+{
+	struct nss_portid_unconfigure_msg *npum __maybe_unused = &npm->msg.unconfigure;
+	nss_trace("%px: NSS PORTID Configure message \n"
+		"PORTID Interface Number: %d\n"
+		"PORTID Interface ID: %d\n",
+		npum, npum->port_if_num,
+		npum->port_id);
+}
+
+/*
+ * nss_portid_log_verbose()
+ *	Log message contents.
+ */
+static void nss_portid_log_verbose(struct nss_portid_msg *npm)
+{
+	switch (npm->cm.type) {
+	case NSS_PORTID_CONFIGURE_MSG:
+		nss_portid_log_configure_msg(npm);
+		break;
+
+	case NSS_PORTID_UNCONFIGURE_MSG:
+		nss_portid_log_unconfigure_msg(npm);
+		break;
+
+	case NSS_PORTID_STATS_SYNC_MSG:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", npm);
+		break;
+	}
+}
+
+/*
+ * nss_portid_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_portid_log_tx_msg(struct nss_portid_msg *npm)
+{
+	if (npm->cm.type >= NSS_PORTID_MAX_MSG_TYPE) {
+		nss_warning("%px: Invalid message type\n", npm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", npm, npm->cm.type, nss_portid_log_message_types_str[npm->cm.type]);
+	nss_portid_log_verbose(npm);
+}
+
+/*
+ * nss_portid_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_portid_log_rx_msg(struct nss_portid_msg *npm)
+{
+	if (npm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", npm);
+		return;
+	}
+
+	if (npm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (npm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", npm, npm->cm.type,
+			nss_portid_log_message_types_str[npm->cm.type],
+			npm->cm.response, nss_cmn_response_str[npm->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		npm, npm->cm.type, nss_portid_log_message_types_str[npm->cm.type],
+		npm->cm.response, nss_cmn_response_str[npm->cm.response]);
+
+verbose:
+	nss_portid_log_verbose(npm);
+}
diff --git a/qca-nss-drv/nss_portid_log.h b/qca-nss-drv/nss_portid_log.h
new file mode 100644
index 0000000..54d904f
--- /dev/null
+++ b/qca-nss-drv/nss_portid_log.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_PORTID_LOG_H
+#define __NSS_PORTID_LOG_H
+
+/*
+ * nss_portid.h
+ *	NSS PORTID header file.
+ */
+
+/*
+ * Logger APIs
+ */
+
+/*
+ * nss_portid_log_tx_msg
+ *	Logs a portid message that is sent to the NSS firmware.
+ */
+void nss_portid_log_tx_msg(struct nss_portid_msg *ntm);
+
+/*
+ * nss_portid_log_rx_msg
+ *	Logs a portid message that is received from the NSS firmware.
+ */
+void nss_portid_log_rx_msg(struct nss_portid_msg *ntm);
+
+#endif /* __NSS_PORTID_LOG_H */
diff --git a/qca-nss-drv/nss_portid_stats.c b/qca-nss-drv/nss_portid_stats.c
new file mode 100644
index 0000000..8b6086d
--- /dev/null
+++ b/qca-nss-drv/nss_portid_stats.c
@@ -0,0 +1,153 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2019-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_portid_stats.h"
+
+extern spinlock_t nss_portid_spinlock;
+extern struct nss_portid_handle nss_portid_hdl[];
+
+/*
+ * nss_portid_stats_str
+ *	PortID statistics strings.
+ */
+struct nss_stats_info nss_portid_stats_str[NSS_PORTID_STATS_MAX] = {
+	{"rx_invalid_header"	, NSS_STATS_TYPE_EXCEPTION}
+};
+
+uint64_t nss_portid_stats[NSS_PORTID_STATS_MAX];
+
+/*
+ * nss_portid_stats_read()
+ *	Read PortID stats.
+ */
+static ssize_t nss_portid_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+	/*
+	 * Max output lines = #stats + few output lines for banner printing +
+	 * Number of Extra outputlines for future reference to add new stats.
+	 */
+	uint32_t max_output_lines = NSS_STATS_NODE_MAX + NSS_PORTID_STATS_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_STATS_NODE_MAX * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "portid", NSS_STATS_SINGLE_CORE);
+	size_wr += nss_stats_fill_common_stats(NSS_PORTID_INTERFACE, NSS_STATS_SINGLE_INSTANCE, lbuf, size_wr, size_al, "portid");
+
+	/*
+	 * PortID node stats
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; (i < NSS_PORTID_STATS_MAX); i++) {
+		stats_shadow[i] = nss_portid_stats[i];
+	}
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+
+	size_wr += nss_stats_print("portid", NULL, NSS_STATS_SINGLE_INSTANCE
+					, nss_portid_stats_str
+					, stats_shadow
+					, NSS_PORTID_STATS_MAX
+					, lbuf, size_wr, size_al);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_portid_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(portid)
+
+/*
+ * nss_portid_stats_dentry_create()
+ *	Create portid node statistics debug entry.
+ */
+void nss_portid_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("portid", &nss_portid_stats_ops);
+}
+
+/*
+ * nss_portid_stats_sync()
+ *	Update portid node stats.
+ */
+void nss_portid_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_portid_stats_sync_msg *npsm)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	struct nss_portid_handle *hdl;
+	int j;
+
+	if (npsm->port_id == NSS_PORTID_MAX_SWITCH_PORT) {
+		/*
+		 * Update PORTID base node stats.
+		 */
+		spin_lock_bh(&nss_top->stats_lock);
+		nss_top->stats_node[NSS_PORTID_INTERFACE][NSS_STATS_NODE_RX_PKTS] += npsm->node_stats.rx_packets;
+		nss_top->stats_node[NSS_PORTID_INTERFACE][NSS_STATS_NODE_RX_BYTES] += npsm->node_stats.rx_bytes;
+		nss_top->stats_node[NSS_PORTID_INTERFACE][NSS_STATS_NODE_TX_PKTS] += npsm->node_stats.tx_packets;
+		nss_top->stats_node[NSS_PORTID_INTERFACE][NSS_STATS_NODE_TX_BYTES] += npsm->node_stats.tx_bytes;
+
+		for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+			nss_top->stats_node[NSS_PORTID_INTERFACE][NSS_STATS_NODE_RX_QUEUE_0_DROPPED + j] += npsm->node_stats.rx_dropped[j];
+		}
+
+		nss_portid_stats[NSS_PORTID_STATS_RX_INVALID_HEADER] += npsm->rx_invalid_header;
+		spin_unlock_bh(&nss_top->stats_lock);
+		return;
+	}
+
+	if (npsm->port_id >= NSS_PORTID_MAX_SWITCH_PORT) {
+		nss_warning("port_id %d exceeds NSS_PORTID_MAX_SWITCH_PORT\n", npsm->port_id);
+		return;
+	}
+
+	/*
+	 * Update PORTID interface stats.
+	 */
+	spin_lock_bh(&nss_portid_spinlock);
+	hdl = &nss_portid_hdl[npsm->port_id];
+	if (hdl->if_num == 0) {
+		nss_warning("%px: nss_portid recv'd stats with unconfigured port %d", nss_ctx, npsm->port_id);
+		spin_unlock_bh(&nss_portid_spinlock);
+		return;
+	}
+	hdl->stats.rx_packets += npsm->node_stats.rx_packets;
+	hdl->stats.rx_bytes += npsm->node_stats.rx_bytes;
+	hdl->stats.rx_dropped += nss_cmn_rx_dropped_sum(&npsm->node_stats);
+	hdl->stats.tx_packets += npsm->node_stats.tx_packets;
+	hdl->stats.tx_bytes += npsm->node_stats.tx_bytes;
+	spin_unlock_bh(&nss_portid_spinlock);
+}
diff --git a/qca-nss-drv/nss_portid_stats.h b/qca-nss-drv/nss_portid_stats.h
new file mode 100644
index 0000000..b1a1ee5
--- /dev/null
+++ b/qca-nss-drv/nss_portid_stats.h
@@ -0,0 +1,39 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_PORTID_STATS_H
+#define __NSS_PORTID_STATS_H
+
+/*
+ * PortID statistics
+ */
+enum nss_portid_stats_types {
+	NSS_PORTID_STATS_RX_INVALID_HEADER,
+	NSS_PORTID_STATS_MAX,
+};
+
+struct nss_portid_handle {
+	uint32_t if_num;			/**< Interface number */
+	struct rtnl_link_stats64 stats;		/**< statistics counters */
+};
+
+/*
+ * PortID statistics APIs
+ */
+extern void nss_portid_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_portid_stats_sync_msg *npsm);
+extern void nss_portid_stats_dentry_create(void);
+
+#endif /* __NSS_PORTID_STATS_H */
diff --git a/qca-nss-drv/nss_ppe.c b/qca-nss-drv/nss_ppe.c
new file mode 100644
index 0000000..46ce217
--- /dev/null
+++ b/qca-nss-drv/nss_ppe.c
@@ -0,0 +1,374 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_ppe.h"
+#include "nss_ppe_stats.h"
+#include "nss_ppe_strings.h"
+
+DEFINE_SPINLOCK(nss_ppe_stats_lock);
+
+struct nss_ppe_stats_debug nss_ppe_debug_stats;
+struct nss_ppe_pvt ppe_pvt;
+
+/*
+ * nss_ppe_verify_ifnum()
+ *	Verify PPE interface number.
+ */
+static inline bool nss_ppe_verify_ifnum(int if_num)
+{
+	return nss_is_dynamic_interface(if_num) || (if_num == NSS_PPE_INTERFACE);
+}
+
+/*
+ * nss_ppe_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_ppe_callback(void *app_data, struct nss_ppe_msg *npm)
+{
+	nss_ppe_msg_callback_t callback = (nss_ppe_msg_callback_t)ppe_pvt.cb;
+	void *data = ppe_pvt.app_data;
+
+	ppe_pvt.response = NSS_TX_SUCCESS;
+	ppe_pvt.cb = NULL;
+	ppe_pvt.app_data = NULL;
+
+	if (npm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("ppe error response %d\n", npm->cm.response);
+		ppe_pvt.response = npm->cm.response;
+	}
+
+	if (callback) {
+		callback(data, npm);
+	}
+	complete(&ppe_pvt.complete);
+}
+
+/*
+ * nss_ppe_tx_msg()
+ *	Transmit a ppe message to NSSFW
+ */
+nss_tx_status_t nss_ppe_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_ppe_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace messages.
+	 */
+	nss_ppe_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (ncm->type >= NSS_PPE_MSG_MAX) {
+		nss_warning("%px: message type out of range: %d\n", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	if (!nss_ppe_verify_ifnum(ncm->interface)) {
+		nss_warning("%px: invalid interface %d\n", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ * nss_ppe_tx_msg_sync()
+ *	Transmit a ppe message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_ppe_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_ppe_msg *npm)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&ppe_pvt.sem);
+	ppe_pvt.cb = (void *)npm->cm.cb;
+	ppe_pvt.app_data = (void *)npm->cm.app_data;
+
+	npm->cm.cb = (nss_ptr_t)nss_ppe_callback;
+	npm->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_ppe_tx_msg(nss_ctx, npm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: ppe_tx_msg failed\n", nss_ctx);
+		up(&ppe_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&ppe_pvt.complete, msecs_to_jiffies(NSS_PPE_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: ppe msg tx failed due to timeout\n", nss_ctx);
+		ppe_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = ppe_pvt.response;
+	up(&ppe_pvt.sem);
+	return status;
+}
+
+/*
+ * nss_ppe_get_context()
+ *	Get NSS context instance for ppe
+ */
+struct nss_ctx_instance *nss_ppe_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.ppe_handler_id];
+}
+
+/*
+ * nss_ppe_msg_init()
+ *	Initialize nss_ppe_msg.
+ */
+void nss_ppe_msg_init(struct nss_ppe_msg *ncm, uint16_t if_num, uint32_t type, uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+
+/*
+ * nss_ppe_tx_ipsec_config_msg
+ *	API to send inline IPsec port configure message to NSS FW
+ */
+nss_tx_status_t nss_ppe_tx_ipsec_config_msg(uint32_t nss_ifnum, uint32_t vsi_num, uint16_t mtu,
+						__attribute__((unused))uint16_t mru)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ppe_get_context();
+	struct nss_ppe_msg npm = {0};
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	if (vsi_num >= NSS_PPE_VSI_NUM_MAX) {
+		nss_warning("Invalid vsi number:%u\n", vsi_num);
+		return NSS_TX_FAILURE;
+	}
+
+	nss_ppe_msg_init(&npm, NSS_PPE_INTERFACE, NSS_PPE_MSG_IPSEC_PORT_CONFIG,
+			sizeof(struct nss_ppe_ipsec_port_config_msg), NULL, NULL);
+
+	npm.msg.ipsec_config.nss_ifnum = nss_ifnum;
+	npm.msg.ipsec_config.vsi_num = vsi_num;
+	npm.msg.ipsec_config.mtu = mtu;
+
+	return nss_ppe_tx_msg_sync(nss_ctx, &npm);
+}
+
+/*
+ * nss_ppe_tx_ipsec_mtu_msg
+ *	API to send IPsec port MTU change message to NSS FW
+ */
+nss_tx_status_t nss_ppe_tx_ipsec_mtu_msg(uint32_t nss_ifnum, uint16_t mtu, __attribute__((unused))uint16_t mru)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ppe_get_context();
+	struct nss_ppe_msg npm = {0};
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	nss_ppe_msg_init(&npm, NSS_PPE_INTERFACE, NSS_PPE_MSG_IPSEC_PORT_MTU_CHANGE,
+			sizeof(struct nss_ppe_ipsec_port_mtu_msg), NULL, NULL);
+
+	npm.msg.ipsec_mtu.nss_ifnum = nss_ifnum;
+	npm.msg.ipsec_mtu.mtu = mtu;
+
+	return nss_ppe_tx_msg_sync(nss_ctx, &npm);
+}
+
+/*
+ * nss_ppe_tx_ipsec_add_intf_msg
+ *	API to attach NSS interface to IPsec port
+ */
+nss_tx_status_t nss_ppe_tx_ipsec_add_intf_msg(uint32_t nss_ifnum)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ppe_get_context();
+	struct nss_ppe_msg npm = {0};
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	nss_ppe_msg_init(&npm, NSS_PPE_INTERFACE, NSS_PPE_MSG_IPSEC_ADD_INTF,
+			sizeof(struct nss_ppe_ipsec_add_intf_msg), NULL, NULL);
+
+	npm.msg.ipsec_addif.nss_ifnum = nss_ifnum;
+
+	return nss_ppe_tx_msg_sync(nss_ctx, &npm);
+}
+
+/*
+ * nss_ppe_tx_ipsec_del_intf_msg
+ *	API to detach NSS interface to IPsec port
+ */
+nss_tx_status_t nss_ppe_tx_ipsec_del_intf_msg(uint32_t nss_ifnum)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ppe_get_context();
+	struct nss_ppe_msg npm = {0};
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	nss_ppe_msg_init(&npm, NSS_PPE_INTERFACE, NSS_PPE_MSG_IPSEC_DEL_INTF,
+			sizeof(struct nss_ppe_ipsec_del_intf_msg), NULL, NULL);
+
+	npm.msg.ipsec_delif.nss_ifnum = nss_ifnum;
+
+	return nss_ppe_tx_msg_sync(nss_ctx, &npm);
+}
+
+/*
+ * nss_ppe_handler()
+ *	Handle NSS -> HLOS messages for ppe
+ */
+static void nss_ppe_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_ppe_msg *msg = (struct nss_ppe_msg *)ncm;
+	void *ctx;
+
+	nss_ppe_msg_callback_t cb;
+
+	nss_trace("nss_ctx: %px ppe msg: %px\n", nss_ctx, msg);
+	BUG_ON(!nss_ppe_verify_ifnum(ncm->interface));
+
+	/*
+	 * Trace messages.
+	 */
+	nss_ppe_log_rx_msg(msg);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_PPE_MSG_MAX) {
+		nss_warning("%px: received invalid message %d for PPE interface\n", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_ppe_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d\n", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	switch (msg->cm.type) {
+	case NSS_PPE_MSG_SYNC_STATS:
+		/*
+		 * session debug stats embeded in session stats msg
+		 */
+		nss_ppe_stats_sync(nss_ctx, &msg->msg.stats, ncm->interface);
+		nss_ppe_stats_notify(nss_ctx, ncm->interface);
+		return;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_ppe_msg_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	cb(ctx, msg);
+}
+
+/*
+ * nss_ppe_register_handler()
+ *	debugfs stats msg handler received on static ppe interface
+ *
+ *	TODO: Export API so that others can also read PPE stats.
+ */
+void nss_ppe_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ppe_get_context();
+
+	nss_core_register_handler(nss_ctx, NSS_PPE_INTERFACE, nss_ppe_handler, NULL);
+
+	if (nss_ppe_debug_stats.valid) {
+		nss_ppe_stats_dentry_create();
+		nss_ppe_strings_dentry_create();
+	}
+}
+
+/*
+ * nss_ppe_free()
+ *	Uninitialize PPE base
+ */
+void nss_ppe_free(void)
+{
+	/*
+	 * Check if PPE base is already uninitialized.
+	 */
+	if (!ppe_pvt.ppe_base) {
+		return;
+	}
+
+	/*
+	 * Unmap PPE base address
+	 */
+	iounmap(ppe_pvt.ppe_base);
+	ppe_pvt.ppe_base = NULL;
+
+	spin_lock_bh(&nss_ppe_stats_lock);
+	nss_ppe_debug_stats.valid = false;
+	nss_ppe_debug_stats.if_num = 0;
+	nss_ppe_debug_stats.if_index = 0;
+	spin_unlock_bh(&nss_ppe_stats_lock);
+}
+
+/*
+ * nss_ppe_init()
+ *	Initialize PPE base
+ */
+void nss_ppe_init(void)
+{
+	/*
+	 * Check if PPE base is already initialized.
+	 */
+	if (ppe_pvt.ppe_base) {
+		return;
+	}
+
+	/*
+	 * Get the PPE base address
+	 */
+	ppe_pvt.ppe_base = ioremap_nocache(PPE_BASE_ADDR, PPE_REG_SIZE);
+	if (!ppe_pvt.ppe_base) {
+		nss_warning("DRV can't get PPE base address\n");
+		return;
+	}
+
+	spin_lock_bh(&nss_ppe_stats_lock);
+	nss_ppe_debug_stats.valid = true;
+	nss_ppe_debug_stats.if_num = 0;
+	nss_ppe_debug_stats.if_index = 0;
+	spin_unlock_bh(&nss_ppe_stats_lock);
+
+	sema_init(&ppe_pvt.sem, 1);
+	init_completion(&ppe_pvt.complete);
+}
diff --git a/qca-nss-drv/nss_ppe.h b/qca-nss-drv/nss_ppe.h
new file mode 100644
index 0000000..d710211
--- /dev/null
+++ b/qca-nss-drv/nss_ppe.h
@@ -0,0 +1,423 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ppe.h
+ *      NSS PPE header file
+ */
+
+#include <net/sock.h>
+#include "nss_tx_rx_common.h"
+
+#define PPE_BASE_ADDR			0x3a000000
+#define PPE_REG_SIZE			0x1000000
+
+#define PPE_L3_DBG_WR_OFFSET		0x200c04
+#define PPE_L3_DBG_RD_OFFSET		0x200c0c
+#define PPE_L3_DBG0_OFFSET		0x10001
+#define PPE_L3_DBG1_OFFSET		0x10002
+#define PPE_L3_DBG2_OFFSET		0x10003
+#define PPE_L3_DBG3_OFFSET		0x10004
+#define PPE_L3_DBG4_OFFSET		0x10005
+#define PPE_L3_DBG_PORT_OFFSET		0x11e80
+
+#define PPE_PKT_CODE_WR_OFFSET		0x100080
+#define PPE_PKT_CODE_RD_OFFSET		0x100084
+#define PPE_PKT_CODE_DROP0_OFFSET	0xf000000
+#define PPE_PKT_CODE_DROP1_OFFSET	0x10000000
+#define PPE_PKT_CODE_CPU_OFFSET		0x40000000
+
+#define PPE_PKT_CODE_DROP0_GET(x)	(((x) & 0xe0000000) >> 29)
+#define PPE_PKT_CODE_DROP1_GET(x)	(((x) & 0x7) << 3)
+#define PPE_PKT_CODE_DROP_GET(d0, d1)	(PPE_PKT_CODE_DROP0_GET(d0) | PPE_PKT_CODE_DROP1_GET(d1))
+
+#define PPE_PKT_CODE_CPU_GET(x)		(((x) >> 3) & 0xff)
+
+#define PPE_IPE_PC_REG 0x100000
+
+/*
+ * NSS_SYS_REG_DROP_CPU_CNT_TBL
+ * 	Address map and access APIs for DROP_CPU_CNT table.
+ */
+#define PPE_DROP_CPU_CNT_TBL_OFFSET 0x60000
+#define PPE_DROP_CPU_CNT_TBL_ENTRY_SIZE 0x10
+#define PPE_DROP_CPU_CNT_TBL_BASE_OFFSET (PPE_IPE_PC_REG + PPE_DROP_CPU_CNT_TBL_OFFSET)
+#define PPE_CPU_CODE_MAX_NUM 256
+
+/*
+ * CPU code offset
+ */
+#define PPE_CPU_CODE_OFFSET(n) (PPE_DROP_CPU_CNT_TBL_BASE_OFFSET + ((n) * PPE_DROP_CPU_CNT_TBL_ENTRY_SIZE))
+
+/*
+ * DROP code offset
+ */
+#define PPE_DROP_CODE_IDX(code, src_port) (PPE_CPU_CODE_MAX_NUM + (8 * (code)) + (src_port))
+#define PPE_DROP_CODE_OFFSET(code, src_port) (PPE_DROP_CPU_CNT_TBL_BASE_OFFSET + ((PPE_DROP_CODE_IDX(code, src_port)) * PPE_DROP_CPU_CNT_TBL_ENTRY_SIZE))
+
+#define NSS_PPE_TX_TIMEOUT 1000 /* 1 Second */
+
+/*
+ * Maximum number of VSI
+ */
+#define NSS_PPE_VSI_NUM_MAX 32
+
+/*
+ * ppe nss debug stats lock
+ */
+extern spinlock_t nss_ppe_stats_lock;
+
+/*
+ * Private data structure
+ */
+struct nss_ppe_pvt {
+	void * __iomem ppe_base;
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+	void *cb;
+	void *app_data;
+};
+
+/*
+ * Data structure to store to PPE private context
+ */
+extern struct nss_ppe_pvt ppe_pvt;
+
+/**
+ * nss_ppe_message_types
+ *	Message types for Packet Processing Engine (PPE) requests and responses.
+ *
+ * Note: PPE messages are added as short term approach, expect all
+ * messages below to be deprecated for more integrated approach.
+ */
+enum nss_ppe_message_types {
+	NSS_PPE_MSG_SYNC_STATS,
+	NSS_PPE_MSG_IPSEC_PORT_CONFIG,
+	NSS_PPE_MSG_IPSEC_PORT_MTU_CHANGE,
+	NSS_PPE_MSG_IPSEC_ADD_INTF,
+	NSS_PPE_MSG_IPSEC_DEL_INTF,
+	NSS_PPE_MSG_MAX,
+};
+
+/**
+ * nss_ppe_msg_error_type
+ *	PPE error types.
+ */
+enum nss_ppe_msg_error_type {
+	PPE_MSG_ERROR_OK,
+	PPE_MSG_ERROR_UNKNOWN_TYPE,
+	PPE_MSG_ERROR_PORT_CREATION_FAIL,
+	PPE_MSG_ERROR_INVALID_PORT_VSI,
+	PPE_MSG_ERROR_INVALID_L3_IF,
+	PPE_MSG_ERROR_IPSEC_PORT_CONFIG,
+	PPE_MSG_ERROR_IPSEC_INTF_TABLE_FULL,
+	PPE_MSG_ERROR_IPSEC_INTF_ATTACHED,
+	PPE_MSG_ERROR_IPSEC_INTF_UNATTACHED,
+	PPE_ERROR_MAX
+};
+
+/**
+ * nss_ppe_stats_sc
+ *	Message structure for per service code stats.
+ */
+struct nss_ppe_stats_sc {
+	uint32_t nss_ppe_sc_cb_unregister;	/* Per service-code counter for callback not registered */
+	uint32_t nss_ppe_sc_cb_success;		/* Per service-code coutner for successful callback */
+	uint32_t nss_ppe_sc_cb_failure;		/* Per service-code counter for failure callback */
+};
+
+/**
+ * nss_ppe_stats
+ *	Message structure for ppe general stats
+ */
+struct nss_ppe_stats {
+	uint32_t nss_ppe_v4_l3_flows;		/**< Number of IPv4 routed flows. */
+	uint32_t nss_ppe_v4_l2_flows;		/**< Number of IPv4 bridge flows. */
+	uint32_t nss_ppe_v4_create_req;		/**< Number of IPv4 create requests. */
+	uint32_t nss_ppe_v4_create_fail;	/**< Number of IPv4 create failures. */
+	uint32_t nss_ppe_v4_destroy_req;	/**< Number of IPv4 delete requests. */
+	uint32_t nss_ppe_v4_destroy_fail;	/**< Number of IPv4 delete failures. */
+	uint32_t nss_ppe_v4_mc_create_req;	/**< Number of IPv4 MC create requests. */
+	uint32_t nss_ppe_v4_mc_create_fail;	/**< Number of IPv4 MC create failure. */
+	uint32_t nss_ppe_v4_mc_update_req;	/**< Number of IPv4 MC update requests. */
+	uint32_t nss_ppe_v4_mc_update_fail;	/**< Number of IPv4 MC update failure. */
+	uint32_t nss_ppe_v4_mc_destroy_req;	/**< Number of IPv4 MC delete requests. */
+	uint32_t nss_ppe_v4_mc_destroy_fail;	/**< Number of IPv4 MC delete failure. */
+	uint32_t nss_ppe_v4_unknown_interface;	/**< Number of IPv4 create failures */
+
+	uint32_t nss_ppe_v6_l3_flows;		/**< Number of IPv6 routed flows. */
+	uint32_t nss_ppe_v6_l2_flows;		/**< Number of IPv6 bridge flows. */
+	uint32_t nss_ppe_v6_create_req;		/**< Number of IPv6 create requests. */
+	uint32_t nss_ppe_v6_create_fail;	/**< Number of IPv6 create failures. */
+	uint32_t nss_ppe_v6_destroy_req;	/**< Number of IPv6 delete requests. */
+	uint32_t nss_ppe_v6_destroy_fail;	/**< Number of IPv6 delete failures. */
+	uint32_t nss_ppe_v6_mc_create_req;	/**< Number of IPv6 MC create requests. */
+	uint32_t nss_ppe_v6_mc_create_fail;	/**< Number of IPv6 MC create failure. */
+	uint32_t nss_ppe_v6_mc_update_req;	/**< Number of IPv6 MC update requests. */
+	uint32_t nss_ppe_v6_mc_update_fail;	/**< Number of IPv6 MC update failure. */
+	uint32_t nss_ppe_v6_mc_destroy_req;	/**< Number of IPv6 MC delete requests. */
+	uint32_t nss_ppe_v6_mc_destroy_fail;	/**< Number of IPv6 MC delete failure. */
+	uint32_t nss_ppe_v6_unknown_interface;	/**< Number of IPv6 create failures */
+
+	uint32_t nss_ppe_fail_vp_full;
+			/**< Request failed because the virtual port table is full */
+	uint32_t nss_ppe_fail_nh_full;
+			/**< Request failed because the next hop table is full. */
+	uint32_t nss_ppe_fail_flow_full;
+			/**< Request failed because the flow table is full. */
+	uint32_t nss_ppe_fail_host_full;
+			/**< Request failed because the host table is full. */
+	uint32_t nss_ppe_fail_pubip_full;
+			/**< Request failed because the public IP table is full. */
+	uint32_t nss_ppe_fail_port_setup;
+			/**< Request failed because the PPE port is not setup. */
+	uint32_t nss_ppe_fail_rw_fifo_full;
+			/**< Request failed because the read/write FIFO is full. */
+	uint32_t nss_ppe_fail_flow_command;
+			/**< Request failed because the PPE flow command failed. */
+	uint32_t nss_ppe_fail_unknown_proto;
+			/**< Request failed because of an unknown protocol. */
+	uint32_t nss_ppe_fail_ppe_unresponsive;
+			/**< Request failed because the PPE is not responding. */
+	uint32_t nss_ppe_ce_opaque_invalid;
+			/**< Request failed because of invalid opaque in connection entry. */
+	uint32_t nss_ppe_fail_fqg_full;
+			/**< Request failed because the flow QoS group is full. */
+};
+
+
+/**
+ * nss_ppe_sync_stats_msg
+ *	Message information for PPE synchronization statistics.
+ */
+struct nss_ppe_sync_stats_msg {
+	struct nss_ppe_stats stats;			/**< General stats */
+	struct nss_ppe_stats_sc sc_stats[NSS_PPE_SC_MAX];
+							/**< Per service-code stats */
+};
+
+/**
+ * nss_ppe_ipsec_port_config_msg
+ *	Message structure for inline IPsec port configuration.
+ */
+struct nss_ppe_ipsec_port_config_msg {
+	uint32_t nss_ifnum;		/**< NSS interface number corresponding to inline IPsec port. */
+	uint16_t mtu;			/**< MTU value for inline IPsec port. */
+	uint8_t vsi_num;		/**< Default port VSI for inline IPsec port. */
+};
+
+/**
+ * nss_ppe_ipsec_port_mtu_msg
+ *	Message structure for inline IPsec port MTU change.
+ */
+struct nss_ppe_ipsec_port_mtu_msg {
+	uint32_t nss_ifnum;		/**< NSS interface number corresponding to inline IPsec port. */
+	uint16_t mtu;			/**< MTU value for inline IPsec port. */
+};
+
+/**
+ * nss_ppe_ipsec_add_intf_msg
+ *	Message structure for adding dynamic IPsec/DTLS interface to inline IPsec port.
+ */
+struct nss_ppe_ipsec_add_intf_msg {
+	uint32_t nss_ifnum;	/**< Dynamic IPsec/DTLS interface number. */
+};
+
+/**
+ * nss_ppe_ipsec_del_intf_msg
+ *	Message structure for deleting dynamic IPsec/DTLS interface to inline IPsec port.
+ */
+struct nss_ppe_ipsec_del_intf_msg {
+	uint32_t nss_ifnum;	/**< Dynamic IPsec/DTLS interface number. */
+};
+
+/**
+ * nss_ppe_msg
+ *	Data for sending and receiving PPE host-to-NSS messages.
+ */
+struct nss_ppe_msg {
+	struct nss_cmn_msg cm;		/**< Common message header. */
+
+	/**
+	 * Payload of a PPE host-to-NSS message.
+	 */
+	union {
+		struct nss_ppe_sync_stats_msg stats;
+				/**< Synchronization statistics. */
+		struct nss_ppe_ipsec_port_config_msg ipsec_config;
+				/**< PPE inline IPsec port configuration message. */
+		struct nss_ppe_ipsec_port_mtu_msg ipsec_mtu;
+				/**< Inline IPsec port MTU change message. */
+		struct nss_ppe_ipsec_add_intf_msg ipsec_addif;
+				/**< Inline IPsec NSS interface attach message. */
+		struct nss_ppe_ipsec_del_intf_msg ipsec_delif;
+				/**< Inline IPsec NSS interface detach message. */
+	} msg;			/**< Message payload. */
+};
+
+/**
+ * Callback function for receiving PPE messages.
+ *
+ * @datatypes
+ * nss_ppe_msg
+ *
+ * @param[in] app_data  Pointer to the application context of the message.
+ * @param[in] msg       Pointer to the message data.
+ */
+typedef void (*nss_ppe_msg_callback_t)(void *app_data, struct nss_ppe_msg *msg);
+
+/**
+ * nss_ppe_tx_msg
+ *	Sends PPE messages to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_ppe_msg
+ *
+ * @param[in] nss_ctx  Pointer to the NSS context.
+ * @param[in] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_ppe_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_ppe_msg *msg);
+
+/**
+ * nss_ppe_tx_msg_sync
+ *	Sends PPE messages synchronously to the NSS.
+ *
+ * @datatypes
+ * nss_ctx_instance \n
+ * nss_ppe_msg
+ *
+ * @param[in]     nss_ctx  Pointer to the NSS context.
+ * @param[in,out] msg      Pointer to the message data.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_ppe_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_ppe_msg *msg);
+
+/**
+ * nss_ppe_msg_init
+ *	Initializes a PPE message.
+ *
+ * @datatypes
+ * nss_ppe_msg
+ *
+ * @param[in,out] ncm       Pointer to the message.
+ * @param[in]     if_num    Interface number
+ * @param[in]     type      Type of message.
+ * @param[in]     len       Size of the payload.
+ * @param[in]     cb        Callback function for the message.
+ * @param[in]     app_data  Pointer to the application context of the message.
+ *
+ * @return
+ * None.
+ */
+void nss_ppe_msg_init(struct nss_ppe_msg *ncm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data);
+
+/**
+ * nss_ppe_get_context
+ *	Gets the PPE context used in nss_ppe_tx.
+ *
+ * @return
+ * Pointer to the NSS core context.
+ */
+struct nss_ctx_instance *nss_ppe_get_context(void);
+
+/**
+ * nss_ppe_tx_ipsec_config_msg
+ *      Sends the PPE a message to configure inline IPsec port.
+ *
+ * @param[in] if_num        Static IPsec interface number.
+ * @param[in] vsi_num       Default VSI number associated with inline IPsec port.
+ * @param[in] mtu           Default MTU of static inline IPsec port.
+ * @param[in] mru           Default MRU of static inline IPsec port.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_ppe_tx_ipsec_config_msg(uint32_t nss_ifnum, uint32_t vsi_num, uint16_t mtu, uint16_t mru);
+
+/**
+ * nss_ppe_tx_ipsec_mtu_msg
+ *      Sends the PPE a message to configure MTU value on IPsec port.
+ *
+ * @param[in] nss_ifnum  Static IPsec interface number.
+ * @param[in] mtu        MTU of static IPsec interface.
+ * @param[in] mru        MRU of static IPsec interface.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_ppe_tx_ipsec_mtu_msg(uint32_t nss_ifnum, uint16_t mtu, uint16_t mru);
+
+/**
+ * nss_ppe_tx_ipsec_add_intf_msg
+ *      Sends the PPE a message to attach a dynamic interface number to IPsec port.
+ *
+ * @param[in] if_num  Dynamic IPsec/DTLS interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_ppe_tx_ipsec_add_intf_msg(uint32_t nss_ifnum);
+
+/**
+ * nss_ppe_tx_ipsec_del_intf_msg
+ *      Sends the PPE a message to detach a dynamic interface number to IPsec port.
+ *
+ * @param[in] if_num  Dynamic IPsec/DTLS interface number.
+ *
+ * @return
+ * Status of the Tx operation.
+ */
+nss_tx_status_t nss_ppe_tx_ipsec_del_intf_msg(uint32_t nss_ifnum);
+
+/*
+ * nss_ppe_reg_read()
+ */
+static inline void nss_ppe_reg_read(u32 reg, u32 *val)
+{
+	*val = readl((ppe_pvt.ppe_base + reg));
+}
+
+/*
+ * nss_ppe_reg_write()
+ */
+static inline void nss_ppe_reg_write(u32 reg, u32 val)
+{
+	writel(val, (ppe_pvt.ppe_base + reg));
+}
+
+/*
+ * nss_ppe_log.h
+ *	NSS PPE Log Header File
+ */
+
+/*
+ * nss_ppe_log_tx_msg
+ *	Logs a ppe message that is sent to the NSS firmware.
+ */
+void nss_ppe_log_tx_msg(struct nss_ppe_msg *npm);
+
+/*
+ * nss_ppe_log_rx_msg
+ *	Logs a ppe message that is received from the NSS firmware.
+ */
+void nss_ppe_log_rx_msg(struct nss_ppe_msg *npm);
diff --git a/qca-nss-drv/nss_ppe_log.c b/qca-nss-drv/nss_ppe_log.c
new file mode 100644
index 0000000..a651732
--- /dev/null
+++ b/qca-nss-drv/nss_ppe_log.c
@@ -0,0 +1,189 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ppe_log.c
+ *	NSS PPE logger file.
+ */
+
+#include "nss_core.h"
+#include "nss_ppe.h"
+
+/*
+ * nss_ppe_log_message_types_str
+ *	PPE message strings
+ */
+static int8_t *nss_ppe_log_message_types_str[NSS_PPE_MSG_MAX] __maybe_unused = {
+	"PPE Stats",
+	"PPE IPSEC Port Config",
+	"PPE IPSEC Port MTU Change",
+	"PPE IPSEC Add Interface",
+	"PPE IPSEC Del Interface",
+};
+
+/*
+ * nss_ppe_log_error_response_types_str
+ *	Strings for error types for PPE messages
+ */
+static int8_t *nss_ppe_log_error_response_types_str[PPE_ERROR_MAX] __maybe_unused = {
+	"PPE No Error",
+	"PPE Uknown Type",
+	"PPE Port Creation Failure",
+	"PPE Invalid Port VSI",
+	"PPE Invalid L3 Interface",
+	"PPE IPSEC Port Config Error",
+	"PPE IPSEC Interface Table Full",
+	"PPE IPSEC Interface Attached",
+	"PPE IPSEC Interface Unattached",
+};
+
+/*
+ * nss_ppe_log_port_config_msg()
+ *	Log NSS PPE port config message.
+ */
+static void nss_ppe_log_port_config_msg(struct nss_ppe_msg *npm)
+{
+	struct nss_ppe_ipsec_port_config_msg *npcm __maybe_unused = &npm->msg.ipsec_config;
+	nss_trace("%px: NSS PPE Port Configure Message:\n"
+		"PPE NSS Interface Number: %d\n"
+		"PPE MTU: %d\n"
+		"PPE VSI Number: %d\n",
+		npcm, npcm->nss_ifnum,
+		npcm->mtu, npcm->vsi_num);
+}
+
+/*
+ * nss_ppe_log_port_mtu_msg()
+ *	Log NSS PPE port mtu message.
+ */
+static void nss_ppe_log_port_mtu_msg(struct nss_ppe_msg *npm)
+{
+	struct nss_ppe_ipsec_port_mtu_msg *npmm __maybe_unused = &npm->msg.ipsec_mtu;
+	nss_trace("%px: NSS PPE Port Configure Message:\n"
+		"PPE NSS Interface Number: %d\n"
+		"PPE MTU: %d\n",
+		npmm, npmm->nss_ifnum,
+		npmm->mtu);
+}
+
+/*
+ * nss_ppe_log_add_intf_msg()
+ *	Log NSS PPE IPSEC Add Interface Message.
+ */
+static void nss_ppe_log_add_intf_msg(struct nss_ppe_msg *npm)
+{
+	struct nss_ppe_ipsec_add_intf_msg *npam __maybe_unused = &npm->msg.ipsec_addif;
+	nss_trace("%px: NSS PPE IPSEC add Interface Message:\n"
+		"PPE NSS Interface Number: %d\n",
+		npam, npam->nss_ifnum);
+}
+
+/*
+ * nss_ppe_log_del_intf_msg()
+ *	Log NSS PPE IPSEC Delete Interface Message.
+ */
+static void nss_ppe_log_del_intf_msg(struct nss_ppe_msg *npm)
+{
+	struct nss_ppe_ipsec_del_intf_msg *npdm __maybe_unused = &npm->msg.ipsec_delif;
+	nss_trace("%px: NSS PPE IPSEC Delete Interface Message:\n"
+		"PPE NSS Interface Number: %d\n",
+		npdm, npdm->nss_ifnum);
+}
+
+/*
+ * nss_ppe_log_verbose()
+ *	Log message contents.
+ */
+static void nss_ppe_log_verbose(struct nss_ppe_msg *npm)
+{
+	switch (npm->cm.type) {
+	case NSS_PPE_MSG_IPSEC_PORT_CONFIG:
+		nss_ppe_log_port_config_msg(npm);
+		break;
+
+	case NSS_PPE_MSG_IPSEC_PORT_MTU_CHANGE:
+		nss_ppe_log_port_mtu_msg(npm);
+		break;
+
+	case NSS_PPE_MSG_IPSEC_ADD_INTF:
+		nss_ppe_log_add_intf_msg(npm);
+		break;
+
+	case NSS_PPE_MSG_IPSEC_DEL_INTF:
+		nss_ppe_log_del_intf_msg(npm);
+		break;
+
+	case NSS_PPE_MSG_SYNC_STATS:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", npm);
+		break;
+	}
+}
+
+/*
+ * nss_ppe_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_ppe_log_tx_msg(struct nss_ppe_msg *npm)
+{
+	if (npm->cm.type >= NSS_PPE_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", npm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", npm, npm->cm.type, nss_ppe_log_message_types_str[npm->cm.type]);
+	nss_ppe_log_verbose(npm);
+}
+
+/*
+ * nss_ppe_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_ppe_log_rx_msg(struct nss_ppe_msg *npm)
+{
+	if (npm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", npm);
+		return;
+	}
+
+	if (npm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (npm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", npm, npm->cm.type,
+			nss_ppe_log_message_types_str[npm->cm.type],
+			npm->cm.response, nss_cmn_response_str[npm->cm.response]);
+		goto verbose;
+	}
+
+	if (npm->cm.error >= PPE_ERROR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			npm, npm->cm.type, nss_ppe_log_message_types_str[npm->cm.type],
+			npm->cm.response, nss_cmn_response_str[npm->cm.response],
+			npm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		npm, npm->cm.type, nss_ppe_log_message_types_str[npm->cm.type],
+		npm->cm.response, nss_cmn_response_str[npm->cm.response],
+		npm->cm.error, nss_ppe_log_error_response_types_str[npm->cm.error]);
+
+verbose:
+	nss_ppe_log_verbose(npm);
+}
diff --git a/qca-nss-drv/nss_ppe_stats.c b/qca-nss-drv/nss_ppe_stats.c
new file mode 100644
index 0000000..e544856
--- /dev/null
+++ b/qca-nss-drv/nss_ppe_stats.c
@@ -0,0 +1,925 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_ppe.h"
+#include "nss_ppe_stats.h"
+#include "nss_ppe_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_ppe_stats_notifier);
+
+static uint8_t ppe_cc_nonexception[NSS_PPE_STATS_CPU_CODE_NONEXCEPTION_MAX] = {
+	NSS_PPE_STATS_CPU_CODE_EXP_FAKE_L2_PROT_ERR,
+	NSS_PPE_STATS_CPU_CODE_EXP_FAKE_MAC_HEADER_ERR,
+	NSS_PPE_STATS_CPU_CODE_EXP_BITMAP_MAX,
+	NSS_PPE_STATS_CPU_CODE_L2_EXP_MRU_FAIL,
+	NSS_PPE_STATS_CPU_CODE_L2_EXP_MTU_FAIL,
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_IP_PREFIX_BC,
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_MTU_FAIL,
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_MRU_FAIL,
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_ICMP_RDT,
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_IP_RT_TTL1_TO_ME,
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_IP_RT_TTL_ZERO,
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_SERVICE_CODE_LOOP,
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_DE_ACCELERATE,
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_FLOW_SRC_IF_CHK_FAIL,
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_SYNC_TOGGLE_MISMATCH,
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_MTU_DF_FAIL,
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_PPPOE_MULTICAST,
+	NSS_PPE_STATS_CPU_CODE_MGMT_OFFSET,
+	NSS_PPE_STATS_CPU_CODE_MGMT_EAPOL,
+	NSS_PPE_STATS_CPU_CODE_MGMT_PPPOE_DIS,
+	NSS_PPE_STATS_CPU_CODE_MGMT_IGMP,
+	NSS_PPE_STATS_CPU_CODE_MGMT_ARP_REQ,
+	NSS_PPE_STATS_CPU_CODE_MGMT_ARP_REP,
+	NSS_PPE_STATS_CPU_CODE_MGMT_DHCPv4,
+	NSS_PPE_STATS_CPU_CODE_MGMT_MLD,
+	NSS_PPE_STATS_CPU_CODE_MGMT_NS,
+	NSS_PPE_STATS_CPU_CODE_MGMT_NA,
+	NSS_PPE_STATS_CPU_CODE_MGMT_DHCPv6,
+	NSS_PPE_STATS_CPU_CODE_PTP_OFFSET,
+	NSS_PPE_STATS_CPU_CODE_PTP_SYNC,
+	NSS_PPE_STATS_CPU_CODE_PTP_FOLLOW_UP,
+	NSS_PPE_STATS_CPU_CODE_PTP_DELAY_REQ,
+	NSS_PPE_STATS_CPU_CODE_PTP_DELAY_RESP,
+	NSS_PPE_STATS_CPU_CODE_PTP_PDELAY_REQ,
+	NSS_PPE_STATS_CPU_CODE_PTP_PDELAY_RESP,
+	NSS_PPE_STATS_CPU_CODE_PTP_PDELAY_RESP_FOLLOW_UP,
+	NSS_PPE_STATS_CPU_CODE_PTP_ANNOUNCE,
+	NSS_PPE_STATS_CPU_CODE_PTP_MANAGEMENT,
+	NSS_PPE_STATS_CPU_CODE_PTP_SIGNALING,
+	NSS_PPE_STATS_CPU_CODE_PTP_PKT_RSV_MSG,
+	NSS_PPE_STATS_CPU_CODE_IPV4_SG_UNKNOWN,
+	NSS_PPE_STATS_CPU_CODE_IPV6_SG_UNKNOWN,
+	NSS_PPE_STATS_CPU_CODE_ARP_SG_UNKNOWN,
+	NSS_PPE_STATS_CPU_CODE_ND_SG_UNKNOWN,
+	NSS_PPE_STATS_CPU_CODE_IPV4_SG_VIO,
+	NSS_PPE_STATS_CPU_CODE_IPV6_SG_VIO,
+	NSS_PPE_STATS_CPU_CODE_ARP_SG_VIO,
+	NSS_PPE_STATS_CPU_CODE_ND_SG_VIO,
+	NSS_PPE_STATS_CPU_CODE_L3_ROUTING_IP_TO_ME,
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_SNAT_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_DNAT_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_RT_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_BR_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_MC_BRIDGE_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_ROUTE_PREHEAD_RT_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_ROUTE_PREHEAD_SNAPT_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_ROUTE_PREHEAD_DNAPT_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_ROUTE_PREHEAD_SNAT_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_ROUTE_PREHEAD_DNAT_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_NO_ROUTE_PREHEAD_NAT_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_NO_ROUTE_PREHEAD_NAT_ERROR,
+	NSS_PPE_STATS_CPU_CODE_L3_ROUTE_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_NO_ROUTE_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_NO_ROUTE_NH_INVALID_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_NO_ROUTE_PREHEAD_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_BRIDGE_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_MISS_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L2_NEW_MAC_ADDRESS,
+	NSS_PPE_STATS_CPU_CODE_L2_HASH_COLLISION,
+	NSS_PPE_STATS_CPU_CODE_L2_STATION_MOVE,
+	NSS_PPE_STATS_CPU_CODE_L2_LEARN_LIMIT,
+	NSS_PPE_STATS_CPU_CODE_L2_SA_LOOKUP_ACTION,
+	NSS_PPE_STATS_CPU_CODE_L2_DA_LOOKUP_ACTION,
+	NSS_PPE_STATS_CPU_CODE_APP_CTRL_ACTION,
+	NSS_PPE_STATS_CPU_CODE_IN_VLAN_FILTER_ACTION,
+	NSS_PPE_STATS_CPU_CODE_IN_VLAN_XLT_MISS,
+	NSS_PPE_STATS_CPU_CODE_EG_VLAN_FILTER_DROP,
+	NSS_PPE_STATS_CPU_CODE_ACL_PRE_ACTION,
+	NSS_PPE_STATS_CPU_CODE_ACL_POST_ACTION,
+	NSS_PPE_STATS_CPU_CODE_SERVICE_CODE_ACTION,
+};
+
+/*
+ * nss_ppe_stats_str_sc_type
+ *      PPE service-code stats type
+ */
+static int8_t *nss_ppe_stats_str_sc_type[NSS_PPE_SC_MAX] = {
+	"SC_NONE           ",
+	"SC_BYPASS_ALL     ",
+	"SC_ADV_QOS_BRIDGED",
+	"SC_BR_QOS         ",
+	"SC_BNC_0          ",
+	"SC_BNC_CMPL_0     ",
+	"SC_ADV_QOS_ROUTED ",
+	"SC_IPSEC_PPE2EIP  ",
+	"SC_IPSEC_EIP2PPE  ",
+	"SC_PTP            ",
+	"SC_VLAN_FILTER	   ",
+	"SC_L3_EXCEPT      ",
+};
+
+/*
+ * nss_ppe_stats_sync
+ *	PPE connection sync statistics from NSS
+ */
+void nss_ppe_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_ppe_sync_stats_msg *stats_msg, uint16_t if_num)
+{
+	uint32_t sc;
+	spin_lock_bh(&nss_ppe_stats_lock);
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V4_L3_FLOWS] = stats_msg->stats.nss_ppe_v4_l3_flows;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V4_L2_FLOWS] = stats_msg->stats.nss_ppe_v4_l2_flows;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V4_CREATE_REQ] += stats_msg->stats.nss_ppe_v4_create_req;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V4_CREATE_FAIL] += stats_msg->stats.nss_ppe_v4_create_fail;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V4_DESTROY_REQ] += stats_msg->stats.nss_ppe_v4_destroy_req;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V4_DESTROY_FAIL] += stats_msg->stats.nss_ppe_v4_destroy_fail;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V4_MC_CREATE_REQ] += stats_msg->stats.nss_ppe_v4_mc_create_req;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V4_MC_CREATE_FAIL] += stats_msg->stats.nss_ppe_v4_mc_create_fail;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V4_MC_UPDATE_REQ] += stats_msg->stats.nss_ppe_v4_mc_update_req;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V4_MC_UPDATE_FAIL] += stats_msg->stats.nss_ppe_v4_mc_update_fail;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V4_MC_DESTROY_REQ] += stats_msg->stats.nss_ppe_v4_mc_destroy_req;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V4_MC_DESTROY_FAIL] += stats_msg->stats.nss_ppe_v4_mc_destroy_fail;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V4_UNKNOWN_INTERFACE] += stats_msg->stats.nss_ppe_v4_unknown_interface;
+
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V6_L3_FLOWS] = stats_msg->stats.nss_ppe_v6_l3_flows;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V6_L2_FLOWS] = stats_msg->stats.nss_ppe_v6_l2_flows;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V6_CREATE_REQ] += stats_msg->stats.nss_ppe_v6_create_req;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V6_CREATE_FAIL] += stats_msg->stats.nss_ppe_v6_create_fail;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V6_DESTROY_REQ] += stats_msg->stats.nss_ppe_v6_destroy_req;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V6_DESTROY_FAIL] += stats_msg->stats.nss_ppe_v6_destroy_fail;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V6_MC_CREATE_REQ] += stats_msg->stats.nss_ppe_v6_mc_create_req;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V6_MC_CREATE_FAIL] += stats_msg->stats.nss_ppe_v6_mc_create_fail;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V6_MC_UPDATE_REQ] += stats_msg->stats.nss_ppe_v6_mc_update_req;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V6_MC_UPDATE_FAIL] += stats_msg->stats.nss_ppe_v6_mc_update_fail;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V6_MC_DESTROY_REQ] += stats_msg->stats.nss_ppe_v6_mc_destroy_req;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V6_MC_DESTROY_FAIL] += stats_msg->stats.nss_ppe_v6_mc_destroy_fail;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_V6_UNKNOWN_INTERFACE] += stats_msg->stats.nss_ppe_v6_unknown_interface;
+
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_FAIL_VP_FULL] += stats_msg->stats.nss_ppe_fail_vp_full;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_FAIL_NH_FULL] += stats_msg->stats.nss_ppe_fail_nh_full;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_FAIL_FLOW_FULL] += stats_msg->stats.nss_ppe_fail_flow_full;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_FAIL_HOST_FULL] += stats_msg->stats.nss_ppe_fail_host_full;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_FAIL_PUBIP_FULL] += stats_msg->stats.nss_ppe_fail_pubip_full;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_FAIL_PORT_SETUP] += stats_msg->stats.nss_ppe_fail_port_setup;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_FAIL_RW_FIFO_FULL] += stats_msg->stats.nss_ppe_fail_rw_fifo_full;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_FAIL_FLOW_COMMAND] += stats_msg->stats.nss_ppe_fail_flow_command;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_FAIL_UNKNOWN_PROTO] += stats_msg->stats.nss_ppe_fail_unknown_proto;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_FAIL_PPE_UNRESPONSIVE] += stats_msg->stats.nss_ppe_fail_ppe_unresponsive;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_CE_OPAQUE_INVALID] += stats_msg->stats.nss_ppe_ce_opaque_invalid;
+	nss_ppe_debug_stats.conn_stats[NSS_PPE_STATS_FAIL_FQG_FULL] += stats_msg->stats.nss_ppe_fail_fqg_full;
+
+	/*
+	 * Update service-code stats.
+	 */
+	for (sc = 0; sc < NSS_PPE_SC_MAX; sc++) {
+		nss_ppe_debug_stats.sc_stats[sc].nss_ppe_sc_cb_unregister += stats_msg->sc_stats[sc].nss_ppe_sc_cb_unregister;
+		nss_ppe_debug_stats.sc_stats[sc].nss_ppe_sc_cb_success += stats_msg->sc_stats[sc].nss_ppe_sc_cb_success;
+		nss_ppe_debug_stats.sc_stats[sc].nss_ppe_sc_cb_failure += stats_msg->sc_stats[sc].nss_ppe_sc_cb_failure;
+	}
+
+	spin_unlock_bh(&nss_ppe_stats_lock);
+}
+
+/*
+ * nss_ppe_stats_conn_get()
+ *	Get PPE connection statistics.
+ */
+static void nss_ppe_stats_conn_get(uint64_t *stats)
+{
+	if (!stats) {
+		nss_warning("No memory to copy ppe connection stats");
+		return;
+	}
+
+	/*
+	 * Get flow stats
+	 */
+	spin_lock_bh(&nss_ppe_stats_lock);
+	memcpy(stats, nss_ppe_debug_stats.conn_stats, (sizeof(uint64_t) * NSS_PPE_STATS_CONN_MAX));
+	spin_unlock_bh(&nss_ppe_stats_lock);
+}
+
+/*
+ * nss_ppe_stats_sc_get()
+ *	Get PPE service-code statistics.
+ */
+static void nss_ppe_stats_sc_get(struct nss_ppe_sc_stats_debug *sc_stats)
+{
+	if (!sc_stats) {
+		nss_warning("No memory to copy ppe service code stats");
+		return;
+	}
+
+	/*
+	 * Get flow stats
+	 */
+	spin_lock_bh(&nss_ppe_stats_lock);
+	memcpy(sc_stats, nss_ppe_debug_stats.sc_stats, (sizeof(struct nss_ppe_sc_stats_debug) * NSS_PPE_SC_MAX));
+	spin_unlock_bh(&nss_ppe_stats_lock);
+}
+
+/*
+ * nss_ppe_stats_l3_get()
+ *	Get PPE L3 debug statistics.
+ */
+static void nss_ppe_stats_l3_get(uint32_t *stats)
+{
+	if (!stats) {
+		nss_warning("No memory to copy ppe l3 dbg stats\n");
+		return;
+	}
+
+	spin_lock_bh(&nss_ppe_stats_lock);
+	nss_ppe_reg_write(PPE_L3_DBG_WR_OFFSET, PPE_L3_DBG0_OFFSET);
+	nss_ppe_reg_read(PPE_L3_DBG_RD_OFFSET, &stats[NSS_PPE_STATS_L3_DBG_0]);
+
+	nss_ppe_reg_write(PPE_L3_DBG_WR_OFFSET, PPE_L3_DBG1_OFFSET);
+	nss_ppe_reg_read(PPE_L3_DBG_RD_OFFSET, &stats[NSS_PPE_STATS_L3_DBG_1]);
+
+	nss_ppe_reg_write(PPE_L3_DBG_WR_OFFSET, PPE_L3_DBG2_OFFSET);
+	nss_ppe_reg_read(PPE_L3_DBG_RD_OFFSET, &stats[NSS_PPE_STATS_L3_DBG_2]);
+
+	nss_ppe_reg_write(PPE_L3_DBG_WR_OFFSET, PPE_L3_DBG3_OFFSET);
+	nss_ppe_reg_read(PPE_L3_DBG_RD_OFFSET, &stats[NSS_PPE_STATS_L3_DBG_3]);
+
+	nss_ppe_reg_write(PPE_L3_DBG_WR_OFFSET, PPE_L3_DBG4_OFFSET);
+	nss_ppe_reg_read(PPE_L3_DBG_RD_OFFSET, &stats[NSS_PPE_STATS_L3_DBG_4]);
+
+	nss_ppe_reg_write(PPE_L3_DBG_WR_OFFSET, PPE_L3_DBG_PORT_OFFSET);
+	nss_ppe_reg_read(PPE_L3_DBG_RD_OFFSET, &stats[NSS_PPE_STATS_L3_DBG_PORT]);
+	spin_unlock_bh(&nss_ppe_stats_lock);
+}
+
+/*
+ * nss_ppe_stats_code_get()
+ *	Get PPE CPU and DROP code for last packet processed.
+ */
+static void nss_ppe_stats_code_get(uint32_t *stats)
+{
+	uint32_t drop_0, drop_1, cpu_code;
+
+	nss_trace("%s(%d) Start\n", __func__, __LINE__);
+	if (!stats) {
+		nss_warning("No memory to copy ppe code\n");
+		return;
+	}
+
+	spin_lock_bh(&nss_ppe_stats_lock);
+	nss_ppe_reg_write(PPE_PKT_CODE_WR_OFFSET, PPE_PKT_CODE_DROP0_OFFSET);
+	nss_ppe_reg_read(PPE_PKT_CODE_RD_OFFSET, &drop_0);
+
+	nss_ppe_reg_write(PPE_PKT_CODE_WR_OFFSET, PPE_PKT_CODE_DROP1_OFFSET);
+	nss_ppe_reg_read(PPE_PKT_CODE_RD_OFFSET, &drop_1);
+
+	stats[NSS_PPE_STATS_CODE_DROP] = PPE_PKT_CODE_DROP_GET(drop_0, drop_1);
+
+	nss_ppe_reg_write(PPE_PKT_CODE_WR_OFFSET, PPE_PKT_CODE_CPU_OFFSET);
+	nss_ppe_reg_read(PPE_PKT_CODE_RD_OFFSET, &cpu_code);
+
+	stats[NSS_PPE_STATS_CODE_CPU] = PPE_PKT_CODE_CPU_GET(cpu_code);
+
+	spin_unlock_bh(&nss_ppe_stats_lock);
+}
+
+/*
+ * nss_ppe_port_drop_code_get()
+ *	Get ppe per port drop code.
+ */
+static void nss_ppe_port_drop_code_get(uint32_t *stats, uint8_t port_id)
+{
+	uint8_t i;
+	nss_trace("%s(%d) Start\n", __func__, __LINE__);
+	if (!stats) {
+		nss_warning("No memory to copy ppe code\n");
+		return;
+	}
+
+	if (port_id > NSS_PPE_NUM_PHY_PORTS_MAX) {
+		nss_warning("Port id is out of range\n");
+		return;
+	}
+
+	spin_lock_bh(&nss_ppe_stats_lock);
+
+	for (i = 0; i < NSS_PPE_STATS_DROP_CODE_MAX; i++) {
+		nss_ppe_reg_read(PPE_DROP_CODE_OFFSET(i, port_id), &stats[i]);
+	}
+
+	spin_unlock_bh(&nss_ppe_stats_lock);
+}
+
+/*
+ * nss_ppe_cpu_code_exception_get()
+ *	Get ppe cpu code specific for flow exceptions.
+ */
+static void nss_ppe_cpu_code_exception_get(uint32_t *stats)
+{
+	uint8_t i;
+	nss_trace("%s(%d) Start\n", __func__, __LINE__);
+	if (!stats) {
+		nss_warning("No memory to copy ppe code\n");
+		return;
+	}
+
+	spin_lock_bh(&nss_ppe_stats_lock);
+
+	for (i = 0; i < NSS_PPE_STATS_CPU_CODE_EXCEPTION_MAX ; i++) {
+		nss_ppe_reg_read(PPE_CPU_CODE_OFFSET(i), &stats[i]);
+	}
+
+	spin_unlock_bh(&nss_ppe_stats_lock);
+}
+
+/*
+ * nss_ppe_cpu_code_nonexception_get()
+ *	Get ppe cpu code specific for flow exceptions.
+ */
+static void nss_ppe_cpu_code_nonexception_get(uint32_t *stats)
+{
+	uint8_t i;
+	nss_trace("%s(%d) Start\n", __func__, __LINE__);
+	if (!stats) {
+		nss_warning("No memory to copy ppe code\n");
+		return;
+	}
+
+	spin_lock_bh(&nss_ppe_stats_lock);
+
+	for (i = 0; i < NSS_PPE_STATS_CPU_CODE_NONEXCEPTION_MAX; i++) {
+		nss_ppe_reg_read(PPE_CPU_CODE_OFFSET(ppe_cc_nonexception[i]), &stats[i]);
+	}
+
+	spin_unlock_bh(&nss_ppe_stats_lock);
+}
+
+/*
+ * nss_ppe_conn_stats_read()
+ *	Read ppe connection statistics
+ */
+static ssize_t nss_ppe_conn_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int i;
+	char *lbuf = NULL;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+	uint64_t ppe_stats[NSS_PPE_STATS_CONN_MAX];
+	uint32_t max_output_lines = NSS_PPE_STATS_CONN_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+
+	lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_PPE_STATS_CONN_MAX * 8, GFP_KERNEL);
+	if (unlikely(!stats_shadow)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	memset(ppe_stats, 0, sizeof(uint64_t) * NSS_PPE_STATS_CONN_MAX);
+
+	/*
+	 * Get all stats
+	 */
+	nss_ppe_stats_conn_get(ppe_stats);
+
+	/*
+	 * flow stats
+	 */
+	spin_lock_bh(&nss_ppe_stats_lock);
+	for (i = 0; i < NSS_PPE_STATS_CONN_MAX; i++) {
+		stats_shadow[i] = ppe_stats[i];
+	}
+
+	spin_unlock_bh(&nss_ppe_stats_lock);
+	size_wr += nss_stats_print("ppe", "ppe flow counters", NSS_STATS_SINGLE_INSTANCE, nss_ppe_stats_str_conn, stats_shadow,
+					NSS_PPE_STATS_CONN_MAX, lbuf, size_wr, size_al);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+
+	kfree(lbuf);
+	kfree(stats_shadow);
+	return bytes_read;
+}
+
+/*
+ * nss_ppe_sc_stats_read()
+ *	Read ppe service code statistics
+ */
+static ssize_t nss_ppe_sc_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int i;
+	char *lbuf = NULL;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	struct nss_ppe_sc_stats_debug sc_stats[NSS_PPE_SC_MAX];
+	uint32_t max_output_lines = (NSS_PPE_SC_MAX * NSS_PPE_STATS_SERVICE_CODE_MAX) + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+
+	lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	memset(sc_stats, 0, sizeof(sc_stats));
+
+	/*
+	 * Get stats
+	 */
+	nss_ppe_stats_sc_get(sc_stats);
+
+	/*
+	 * service code stats
+	 */
+
+	for (i = 0; i < NSS_PPE_SC_MAX; i++) {
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "ppe service code type: %s\n",
+					nss_ppe_stats_str_sc_type[i]);
+		size_wr += nss_stats_print("ppe", "ppe service code counters", NSS_STATS_SINGLE_INSTANCE,
+						nss_ppe_stats_str_sc, &sc_stats[i].nss_ppe_sc_cb_unregister,
+						NSS_PPE_STATS_SERVICE_CODE_MAX, lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_ppe_l3_stats_read()
+ *	Read PPE L3 debug statistics
+ */
+static ssize_t nss_ppe_l3_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int i;
+	char *lbuf = NULL;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+	uint32_t ppe_stats[NSS_PPE_STATS_L3_MAX];
+	uint32_t max_output_lines = NSS_PPE_STATS_L3_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+
+	lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_PPE_STATS_L3_MAX * 8, GFP_KERNEL);
+	if (unlikely(!stats_shadow)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	memset(ppe_stats, 0, sizeof(uint32_t) * NSS_PPE_STATS_L3_MAX);
+
+	/*
+	 * Get all stats
+	 */
+	nss_ppe_stats_l3_get(ppe_stats);
+
+	/*
+	 * flow stats
+	 */
+	spin_lock_bh(&nss_ppe_stats_lock);
+	for (i = 0; i < NSS_PPE_STATS_L3_MAX; i++) {
+		stats_shadow[i] = ppe_stats[i];
+	}
+
+	spin_unlock_bh(&nss_ppe_stats_lock);
+	size_wr += nss_stats_print("ppe", "ppe l3 debug stats", NSS_STATS_SINGLE_INSTANCE, nss_ppe_stats_str_l3,
+					stats_shadow, NSS_PPE_STATS_L3_MAX, lbuf, size_wr, size_al);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+	return bytes_read;
+}
+
+/*
+ * nss_ppe_code_stats_read()
+ *	Read ppe CPU & DROP code
+ */
+static ssize_t nss_ppe_code_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int i;
+	char *lbuf = NULL;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+	uint32_t ppe_stats[NSS_PPE_STATS_CODE_MAX];
+	uint32_t max_output_lines = NSS_PPE_STATS_CODE_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+
+	lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_PPE_STATS_CODE_MAX * 8, GFP_KERNEL);
+	if (unlikely(!stats_shadow)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	memset(ppe_stats, 0, sizeof(uint32_t) * NSS_PPE_STATS_CODE_MAX);
+
+	/*
+	 * Get all stats
+	 */
+	nss_ppe_stats_code_get(ppe_stats);
+
+	/*
+	 * flow stats
+	 */
+	spin_lock_bh(&nss_ppe_stats_lock);
+	for (i = 0; i < NSS_PPE_STATS_CODE_MAX; i++) {
+		stats_shadow[i] = ppe_stats[i];
+	}
+
+	spin_unlock_bh(&nss_ppe_stats_lock);
+	size_wr += nss_stats_print("ppe", "ppe session stats", NSS_STATS_SINGLE_INSTANCE, nss_ppe_stats_str_code, stats_shadow,
+					NSS_PPE_STATS_CODE_MAX, lbuf, size_wr, size_al);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+
+	kfree(lbuf);
+	kfree(stats_shadow);
+	return bytes_read;
+}
+
+/*
+ * nss_ppe_port_dc_stats_read()
+ *      Read PPE per port drop code stats
+ */
+static ssize_t nss_ppe_port_dc_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * max output lines = #stats + few blank lines for future reference to add new stats.
+	 */
+	uint32_t max_output_lines = NSS_PPE_STATS_DROP_CODE_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+	struct nss_stats_data *data = fp->private_data;
+	uint32_t *ppe_stats;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	ppe_stats = kzalloc(sizeof(uint32_t) * NSS_PPE_STATS_DROP_CODE_MAX, GFP_KERNEL);
+	if (unlikely(ppe_stats == NULL)) {
+		kfree(lbuf);
+		nss_warning("Could not allocate memory for ppe stats buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc((NSS_PPE_STATS_DROP_CODE_MAX) * 8, GFP_KERNEL);
+	if (unlikely(!stats_shadow)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		kfree(ppe_stats);
+		return 0;
+	}
+
+	/*
+	 * Get drop code counters for specific port
+	 */
+	nss_ppe_port_drop_code_get(ppe_stats, data->edma_id);
+
+	/*
+	 * Drop code stats
+	 */
+	spin_lock_bh(&nss_ppe_stats_lock);
+	for (i = 0; i < NSS_PPE_STATS_DROP_CODE_MAX; i++) {
+		stats_shadow[i] = ppe_stats[i];
+	}
+
+	spin_unlock_bh(&nss_ppe_stats_lock);
+	size_wr += nss_stats_print("ppe", "ppe drop code stats", NSS_STATS_SINGLE_INSTANCE, nss_ppe_stats_str_dc,
+					stats_shadow, NSS_PPE_STATS_DROP_CODE_MAX, lbuf, size_wr, size_al);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(ppe_stats);
+	kfree(lbuf);
+	kfree(stats_shadow);
+	return bytes_read;
+}
+
+/*
+ * nss_ppe_exception_cc_stats_read()
+ *	Read PPE CPU code stats specific to flow exceptions
+ */
+static ssize_t nss_ppe_exception_cc_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * max output lines = #stats + few blank lines for future reference to add new stats.
+	 */
+	uint32_t max_output_lines = NSS_PPE_STATS_CPU_CODE_EXCEPTION_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+	uint32_t *ppe_stats;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	ppe_stats = kzalloc(sizeof(uint32_t) * NSS_PPE_STATS_CPU_CODE_EXCEPTION_MAX, GFP_KERNEL);
+	if (unlikely(ppe_stats == NULL)) {
+		kfree(lbuf);
+		nss_warning("Could not allocate memory for ppe stats buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_PPE_STATS_CPU_CODE_EXCEPTION_MAX * 8, GFP_KERNEL);
+	if (unlikely(!stats_shadow)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		kfree(ppe_stats);
+		return 0;
+	}
+
+	/*
+	 * Get CPU code counters for flow specific exceptions
+	 */
+	nss_ppe_cpu_code_exception_get(ppe_stats);
+
+	/*
+	 * CPU code stats
+	 */
+	spin_lock_bh(&nss_ppe_stats_lock);
+	for (i = 0; i < NSS_PPE_STATS_CPU_CODE_EXCEPTION_MAX; i++) {
+		stats_shadow[i] = ppe_stats[i];
+	}
+
+	spin_unlock_bh(&nss_ppe_stats_lock);
+	size_wr += nss_stats_print("ppe", "ppe cpu code flow-exception stats", NSS_STATS_SINGLE_INSTANCE,
+					nss_ppe_stats_str_cc, stats_shadow, NSS_PPE_STATS_CPU_CODE_EXCEPTION_MAX,
+					lbuf, size_wr, size_al);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(ppe_stats);
+	kfree(lbuf);
+	kfree(stats_shadow);
+	return bytes_read;
+}
+
+/*
+ * nss_ppe_nonexception_cc_stats_read()
+ *      Read PPE CPU code stats for other than flow exceptions
+ */
+static ssize_t nss_ppe_nonexception_cc_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * max output lines = #stats + few blank lines for future reference to add new stats.
+	 */
+	uint32_t max_output_lines = NSS_PPE_STATS_CPU_CODE_NONEXCEPTION_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+	uint32_t *ppe_stats;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	ppe_stats = kzalloc(sizeof(uint32_t) * NSS_PPE_STATS_CPU_CODE_NONEXCEPTION_MAX, GFP_KERNEL);
+	if (unlikely(ppe_stats == NULL)) {
+		kfree(lbuf);
+		nss_warning("Could not allocate memory for ppe stats buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_PPE_STATS_CPU_CODE_NONEXCEPTION_MAX * 8, GFP_KERNEL);
+	if (unlikely(!stats_shadow)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		kfree(ppe_stats);
+		return 0;
+	}
+
+	/*
+	 * Get CPU code counters for non flow exceptions
+	 */
+	nss_ppe_cpu_code_nonexception_get(ppe_stats);
+
+	/*
+	 * CPU code stats
+	 */
+
+	spin_lock_bh(&nss_ppe_stats_lock);
+	for (i = 0; i < NSS_PPE_STATS_CPU_CODE_NONEXCEPTION_MAX; i++) {
+		stats_shadow[i] = ppe_stats[i];
+	}
+
+	spin_unlock_bh(&nss_ppe_stats_lock);
+	size_wr += nss_stats_print("ppe", "ppe cpu code non-flow exception stats", NSS_STATS_SINGLE_INSTANCE,
+					&nss_ppe_stats_str_cc[NSS_PPE_STATS_CPU_CODE_NONEXCEPTION_START],
+					stats_shadow, NSS_PPE_STATS_CPU_CODE_NONEXCEPTION_MAX, lbuf, size_wr, size_al);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(ppe_stats);
+	kfree(stats_shadow);
+	kfree(lbuf);
+
+	return bytes_read;
+}
+
+/*
+ * nss_ppe_conn_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(ppe_conn)
+
+/*
+ * nss_ppe_l3_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(ppe_l3)
+
+/*
+ * nss_ppe_code_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(ppe_code)
+
+/*
+ * nss_ppe_port_dc_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(ppe_port_dc)
+/*
+ *  nss_ppe_exception_cc_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(ppe_exception_cc)
+
+/*
+ *  nss_ppe_nonexception_cc_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(ppe_nonexception_cc)
+
+/*
+ * nss_ppe_sc_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(ppe_sc)
+
+/*
+ * nss_ppe_stats_dentry_create()
+ *	Create PPE statistics debug entry.
+ */
+void nss_ppe_stats_dentry_create(void)
+{
+	int i;
+	struct dentry *ppe_dentry = NULL;
+	struct dentry *ppe_code_d = NULL;
+	struct dentry *ppe_drop_d = NULL;
+	struct dentry *ppe_cpu_d = NULL;
+	char file_name[10];
+
+	ppe_dentry = debugfs_create_dir("ppe", nss_top_main.stats_dentry);
+	if (!ppe_dentry) {
+		nss_warning("Failed to create qca-nss-drv/stats/ppe directory");
+		return;
+	}
+
+	if (!debugfs_create_file("connection", 0400, ppe_dentry, &nss_top_main, &nss_ppe_conn_stats_ops)) {
+		nss_warning("Failed to create qca-nss-drv/stats/ppe/connection file");
+		debugfs_remove_recursive(ppe_dentry);
+		return;
+	}
+
+	if (!debugfs_create_file("sc_stats", 0400, ppe_dentry, &nss_top_main, &nss_ppe_sc_stats_ops)) {
+		nss_warning("Failed to create qca-nss-drv/stats/ppe/sc_stats file");
+		debugfs_remove_recursive(ppe_dentry);
+		return;
+	}
+
+	if (!debugfs_create_file("l3", 0400, ppe_dentry, &nss_top_main, &nss_ppe_l3_stats_ops)) {
+		nss_warning("Failed to create qca-nss-drv/stats/ppe/l3 file");
+		debugfs_remove_recursive(ppe_dentry);
+		return;
+	}
+
+	if (!debugfs_create_file("ppe_code", 0400, ppe_dentry, &nss_top_main, &nss_ppe_code_stats_ops)) {
+		nss_warning("Failed to create qca-nss-drv/stats/ppe/ppe_code file");
+		debugfs_remove_recursive(ppe_dentry);
+		return;
+	}
+
+	/*
+	 * ppe exception and drop code stats
+	 */
+	ppe_code_d = debugfs_create_dir("code", ppe_dentry);
+	if (!ppe_code_d) {
+		nss_warning("Failed to create qca-nss-drv/stats/ppe/code directory");
+		return;
+	}
+
+	ppe_cpu_d = debugfs_create_dir("cpu", ppe_code_d);
+	if (!ppe_cpu_d) {
+		nss_warning("Failed to create qca-nss-drv/stats/ppe/code/cpu directory");
+		return;
+	}
+
+	if (!debugfs_create_file("exception", 0400, ppe_cpu_d, &nss_top_main, &nss_ppe_exception_cc_stats_ops)) {
+		nss_warning("Failed to create qca-nss-drv/stats/ppe/code/exception file");
+		debugfs_remove_recursive(ppe_cpu_d);
+		return;
+	}
+
+	if (!debugfs_create_file("non-exception", 0400, ppe_cpu_d, &nss_top_main, &nss_ppe_nonexception_cc_stats_ops)) {
+		nss_warning("Failed to create qca-nss-drv/stats/ppe/code/non-exception file");
+		debugfs_remove_recursive(ppe_cpu_d);
+		return;
+	}
+
+	ppe_drop_d = debugfs_create_dir("drop", ppe_code_d);
+	if (!ppe_drop_d) {
+		nss_warning("Failed to create qca-nss-drv/stats/ppe/code/drop directory");
+		return;
+	}
+
+	for (i = 0; i < NSS_PPE_NUM_PHY_PORTS_MAX; i++) {
+		if (i > 0) {
+			memset(file_name, 0, sizeof(file_name));
+			snprintf(file_name, sizeof(file_name), "%d", i);
+		}
+
+		if (!debugfs_create_file((i == 0) ? "cpu" : file_name, 0400, ppe_drop_d,
+			(void *)(nss_ptr_t)i, &nss_ppe_port_dc_stats_ops)) {
+			nss_warning("Failed to create qca-nss-drv/stats/ppe/code/drop/%d file", i);
+			debugfs_remove_recursive(ppe_drop_d);
+			return;
+		}
+	}
+}
+
+/*
+ * nss_ppe_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_ppe_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_ppe_stats_notification ppe_stats;
+
+	spin_lock_bh(&nss_ppe_stats_lock);
+	ppe_stats.core_id = nss_ctx->id;
+	ppe_stats.if_num = if_num;
+	memcpy(ppe_stats.ppe_stats_conn, nss_ppe_debug_stats.conn_stats, sizeof(ppe_stats.ppe_stats_conn));
+	memcpy(ppe_stats.ppe_stats_sc, nss_ppe_debug_stats.sc_stats, sizeof(ppe_stats.ppe_stats_sc));
+	spin_unlock_bh(&nss_ppe_stats_lock);
+
+	atomic_notifier_call_chain(&nss_ppe_stats_notifier, NSS_STATS_EVENT_NOTIFY, &ppe_stats);
+}
+
+/*
+ * nss_ppe_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_ppe_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_ppe_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_ppe_stats_unregister_notifier);
+
+/*
+ * nss_ppe_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_ppe_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_ppe_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_ppe_stats_register_notifier);
diff --git a/qca-nss-drv/nss_ppe_stats.h b/qca-nss-drv/nss_ppe_stats.h
new file mode 100644
index 0000000..bd2cecb
--- /dev/null
+++ b/qca-nss-drv/nss_ppe_stats.h
@@ -0,0 +1,447 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2018, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ppe_stats.h
+ *	NSS PPE statistics header file.
+ */
+
+#ifndef __NSS_PPE_STATS_H
+#define __NSS_PPE_STATS_H
+
+#include <nss_cmn.h>
+
+/*
+ * NSS PPE connection statistics
+ */
+enum nss_ppe_stats_conn {
+	NSS_PPE_STATS_V4_L3_FLOWS,		/* No of v4 routed flows */
+	NSS_PPE_STATS_V4_L2_FLOWS,		/* No of v4 bridge flows */
+	NSS_PPE_STATS_V4_CREATE_REQ,		/* No of v4 create requests */
+	NSS_PPE_STATS_V4_CREATE_FAIL,		/* No of v4 create failure */
+	NSS_PPE_STATS_V4_DESTROY_REQ,		/* No of v4 delete requests */
+	NSS_PPE_STATS_V4_DESTROY_FAIL,		/* No of v4 delete failure */
+	NSS_PPE_STATS_V4_MC_CREATE_REQ,		/* No of v4 MC create requests */
+	NSS_PPE_STATS_V4_MC_CREATE_FAIL,	/* No of v4 MC create failure */
+	NSS_PPE_STATS_V4_MC_UPDATE_REQ,		/* No of v4 MC update requests */
+	NSS_PPE_STATS_V4_MC_UPDATE_FAIL,	/* No of v4 MC update failure */
+	NSS_PPE_STATS_V4_MC_DESTROY_REQ,	/* No of v4 MC delete requests */
+	NSS_PPE_STATS_V4_MC_DESTROY_FAIL,	/* No of v4 MC delete failure */
+	NSS_PPE_STATS_V4_UNKNOWN_INTERFACE,	/* No of v4 create failure due to invalid if */
+
+	NSS_PPE_STATS_V6_L3_FLOWS,		/* No of v6 routed flows */
+	NSS_PPE_STATS_V6_L2_FLOWS,		/* No of v6 bridge flows */
+	NSS_PPE_STATS_V6_CREATE_REQ,		/* No of v6 create requests */
+	NSS_PPE_STATS_V6_CREATE_FAIL,		/* No of v6 create failure */
+	NSS_PPE_STATS_V6_DESTROY_REQ,		/* No of v6 delete requests */
+	NSS_PPE_STATS_V6_DESTROY_FAIL,		/* No of v6 delete failure */
+	NSS_PPE_STATS_V6_MC_CREATE_REQ,		/* No of v6 MC create requests */
+	NSS_PPE_STATS_V6_MC_CREATE_FAIL,	/* No of v6 MC create failure */
+	NSS_PPE_STATS_V6_MC_UPDATE_REQ,		/* No of v6 MC update requests */
+	NSS_PPE_STATS_V6_MC_UPDATE_FAIL,	/* No of v6 MC update failure */
+	NSS_PPE_STATS_V6_MC_DESTROY_REQ,	/* No of v6 MC delete requests */
+	NSS_PPE_STATS_V6_MC_DESTROY_FAIL,	/* No of v6 MC delete failure */
+	NSS_PPE_STATS_V6_UNKNOWN_INTERFACE,	/* No of v6 create failure due to invalid if */
+
+	NSS_PPE_STATS_FAIL_VP_FULL,		/* Create req fail due to VP table full */
+	NSS_PPE_STATS_FAIL_NH_FULL,		/* Create req fail due to nexthop table full */
+	NSS_PPE_STATS_FAIL_FLOW_FULL,		/* Create req fail due to flow table full */
+	NSS_PPE_STATS_FAIL_HOST_FULL,		/* Create req fail due to host table full */
+	NSS_PPE_STATS_FAIL_PUBIP_FULL,		/* Create req fail due to pub-ip table full */
+	NSS_PPE_STATS_FAIL_PORT_SETUP,		/* Create req fail due to PPE port not setup */
+	NSS_PPE_STATS_FAIL_RW_FIFO_FULL,	/* Create req fail due to rw fifo full */
+	NSS_PPE_STATS_FAIL_FLOW_COMMAND,	/* Create req fail due to PPE flow command failure */
+	NSS_PPE_STATS_FAIL_UNKNOWN_PROTO,	/* Create req fail due to unknown protocol */
+	NSS_PPE_STATS_FAIL_PPE_UNRESPONSIVE,	/* Create req fail due to PPE not responding */
+	NSS_PPE_STATS_CE_OPAQUE_INVALID,	/* Create req fail due to invalid opaque in CE */
+	NSS_PPE_STATS_FAIL_FQG_FULL,		/* Create req fail due to flow qos group full */
+	NSS_PPE_STATS_CONN_MAX
+};
+
+/*
+ * NSS PPE SC statistics
+ */
+enum nss_ppe_stats_service_code {
+	NSS_PPE_STATS_SERVICE_CODE_CB_UNREGISTER,
+	NSS_PPE_STATS_SERVICE_CODE_PROCESS_OK,
+	NSS_PPE_STATS_SERVICE_CODE_PROCESS_FAIL,
+	NSS_PPE_STATS_SERVICE_CODE_MAX
+};
+
+/*
+ * NSS PPE L3 statistics
+ */
+enum nss_ppe_stats_l3 {
+	NSS_PPE_STATS_L3_DBG_0,		/* PPE L3 debug register 0 */
+	NSS_PPE_STATS_L3_DBG_1,		/* PPE L3 debug register 1 */
+	NSS_PPE_STATS_L3_DBG_2,		/* PPE L3 debug register 2 */
+	NSS_PPE_STATS_L3_DBG_3,		/* PPE L3 debug register 3 */
+	NSS_PPE_STATS_L3_DBG_4,		/* PPE L3 debug register 4 */
+	NSS_PPE_STATS_L3_DBG_PORT,	/* PPE L3 debug register Port */
+	NSS_PPE_STATS_L3_MAX
+};
+
+/*
+ * NSS PPE_code statistics
+ */
+enum nss_ppe_stats_code {
+	NSS_PPE_STATS_CODE_CPU,		/* PPE CPU code for last packet processed */
+	NSS_PPE_STATS_CODE_DROP,	/* PPE DROP code for last packet processed */
+	NSS_PPE_STATS_CODE_MAX
+};
+
+/*
+ * PPE drop codes
+ */
+enum nss_ppe_stats_dc {
+	NSS_PPE_STATS_DROP_CODE_UNKNOWN,                                /* PPE drop code unknown */
+	NSS_PPE_STATS_DROP_CODE_EXP_UNKNOWN_L2_PROT,                    /* PPE drop code exp unknown l2 prot */
+	NSS_PPE_STATS_DROP_CODE_EXP_PPPOE_WRONG_VER_TYPE,               /* PPE drop code exp pppoe wrong ver type */
+	NSS_PPE_STATS_DROP_CODE_EXP_PPPOE_WRONG_CODE,                   /* PPE drop code exp pppoe wrong code */
+	NSS_PPE_STATS_DROP_CODE_EXP_PPPOE_UNSUPPORTED_PPP_PROT,         /* PPE drop code exp pppoe unsupported ppp prot */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_WRONG_VER,                     /* PPE drop code exp ipv4 wrong ver */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_SMALL_IHL,                     /* PPE drop code exp ipv4 small ihl */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_WITH_OPTION,                   /* PPE drop code exp ipv4 with option */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_HDR_INCOMPLETE,                /* PPE drop code exp ipv4 hdr incomplete */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_BAD_TOTAL_LEN,                 /* PPE drop code exp ipv4 bad total len */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_DATA_INCOMPLETE,               /* PPE drop code exp ipv4 data incomplete */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_FRAG,                          /* PPE drop code exp ipv4 frag */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_PING_OF_DEATH,                 /* PPE drop code exp ipv4 ping of death */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_SNALL_TTL,                     /* PPE drop code exp ipv4 snall ttl */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_UNK_IP_PROT,                   /* PPE drop code exp ipv4 unk ip prot */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_CHECKSUM_ERR,                  /* PPE drop code exp ipv4 checksum err */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_INV_SIP,                       /* PPE drop code exp ipv4 inv sip */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_INV_DIP,                       /* PPE drop code exp ipv4 inv dip */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_LAND_ATTACK,                   /* PPE drop code exp ipv4 land attack */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_AH_HDR_INCOMPLETE,             /* PPE drop code exp ipv4 ah hdr incomplete */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_AH_HDR_CROSS_BORDER,           /* PPE drop code exp ipv4 ah hdr cross border */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV4_ESP_HDR_INCOMPLETE,            /* PPE drop code exp ipv4 esp hdr incomplete */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_WRONG_VER,                     /* PPE drop code exp ipv6 wrong ver */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_HDR_INCOMPLETE,                /* PPE drop code exp ipv6 hdr incomplete */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_BAD_PAYLOAD_LEN,               /* PPE drop code exp ipv6 bad payload len */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_DATA_INCOMPLETE,               /* PPE drop code exp ipv6 data incomplete */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_WITH_EXT_HDR,                  /* PPE drop code exp ipv6 with ext hdr */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_SMALL_HOP_LIMIT,               /* PPE drop code exp ipv6 small hop limit */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_INV_SIP,                       /* PPE drop code exp ipv6 inv sip */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_INV_DIP,                       /* PPE drop code exp ipv6 inv dip */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_LAND_ATTACK,                   /* PPE drop code exp ipv6 land attack */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_FRAG,                          /* PPE drop code exp ipv6 frag */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_PING_OF_DEATH,                 /* PPE drop code exp ipv6 ping of death */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_WITH_MORE_EXT_HDR,             /* PPE drop code exp ipv6 with more ext hdr */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_UNK_LAST_NEXT_HDR,             /* PPE drop code exp ipv6 unk last next hdr */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_MOBILITY_HDR_INCOMPLETE,       /* PPE drop code exp ipv6 mobility hdr incomplete */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_MOBILITY_HDR_CROSS_BORDER,     /* PPE drop code exp ipv6 mobility hdr cross border */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_AH_HDR_INCOMPLETE,             /* PPE drop code exp ipv6 ah hdr incomplete */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_AH_HDR_CROSS_BORDER,           /* PPE drop code exp ipv6 ah hdr cross border */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_ESP_HDR_INCOMPLETE,            /* PPE drop code exp ipv6 esp hdr incomplete */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_ESP_HDR_CROSS_BORDER,          /* PPE drop code exp ipv6 esp hdr cross border */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_OTHER_EXT_HDR_INCOMPLETE,      /* PPE drop code exp ipv6 other ext hdr incomplete */
+	NSS_PPE_STATS_DROP_CODE_EXP_IPV6_OTHER_EXT_HDR_CROSS_BORDER,    /* PPE drop code exp ipv6 other ext hdr cross border */
+	NSS_PPE_STATS_DROP_CODE_EXP_TCP_HDR_INCOMPLETE,                 /* PPE drop code exp tcp hdr incomplete */
+	NSS_PPE_STATS_DROP_CODE_EXP_TCP_HDR_CROSS_BORDER,               /* PPE drop code exp tcp hdr cross border */
+	NSS_PPE_STATS_DROP_CODE_EXP_TCP_SMAE_SP_DP,                     /* PPE drop code exp tcp smae sp dp */
+	NSS_PPE_STATS_DROP_CODE_EXP_TCP_SMALL_DATA_OFFSET,              /* PPE drop code exp tcp small data offset */
+	NSS_PPE_STATS_DROP_CODE_EXP_TCP_FLAGS_0,                        /* PPE drop code exp tcp flags 0 */
+	NSS_PPE_STATS_DROP_CODE_EXP_TCP_FLAGS_1,                        /* PPE drop code exp tcp flags 1 */
+	NSS_PPE_STATS_DROP_CODE_EXP_TCP_FLAGS_2,                        /* PPE drop code exp tcp flags 2 */
+	NSS_PPE_STATS_DROP_CODE_EXP_TCP_FLAGS_3,                        /* PPE drop code exp tcp flags 3 */
+	NSS_PPE_STATS_DROP_CODE_EXP_TCP_FLAGS_4,                        /* PPE drop code exp tcp flags 4 */
+	NSS_PPE_STATS_DROP_CODE_EXP_TCP_FLAGS_5,                        /* PPE drop code exp tcp flags 5 */
+	NSS_PPE_STATS_DROP_CODE_EXP_TCP_FLAGS_6,                        /* PPE drop code exp tcp flags 6 */
+	NSS_PPE_STATS_DROP_CODE_EXP_TCP_FLAGS_7,                        /* PPE drop code exp tcp flags 7 */
+	NSS_PPE_STATS_DROP_CODE_EXP_TCP_CHECKSUM_ERR,                   /* PPE drop code exp tcp checksum err */
+	NSS_PPE_STATS_DROP_CODE_EXP_UDP_HDR_INCOMPLETE,                 /* PPE drop code exp udp hdr incomplete */
+	NSS_PPE_STATS_DROP_CODE_EXP_UDP_HDR_CROSS_BORDER,               /* PPE drop code exp udp hdr cross border */
+	NSS_PPE_STATS_DROP_CODE_EXP_UDP_SMAE_SP_DP,                     /* PPE drop code exp udp smae sp dp */
+	NSS_PPE_STATS_DROP_CODE_EXP_UDP_BAD_LEN,                        /* PPE drop code exp udp bad len */
+	NSS_PPE_STATS_DROP_CODE_EXP_UDP_DATA_INCOMPLETE,                /* PPE drop code exp udp data incomplete */
+	NSS_PPE_STATS_DROP_CODE_EXP_UDP_CHECKSUM_ERR,                   /* PPE drop code exp udp checksum err */
+	NSS_PPE_STATS_DROP_CODE_EXP_UDP_LITE_HDR_INCOMPLETE,            /* PPE drop code exp udp lite hdr incomplete */
+	NSS_PPE_STATS_DROP_CODE_EXP_UDP_LITE_HDR_CROSS_BORDER,          /* PPE drop code exp udp lite hdr cross border */
+	NSS_PPE_STATS_DROP_CODE_EXP_UDP_LITE_SMAE_SP_DP,                /* PPE drop code exp udp lite smae sp dp */
+	NSS_PPE_STATS_DROP_CODE_EXP_UDP_LITE_CSM_COV_1_TO_7,            /* PPE drop code exp udp lite csm cov 1 to 7 */
+	NSS_PPE_STATS_DROP_CODE_EXP_UDP_LITE_CSM_COV_TOO_LONG,          /* PPE drop code exp udp lite csm cov too long */
+	NSS_PPE_STATS_DROP_CODE_EXP_UDP_LITE_CSM_COV_CROSS_BORDER,      /* PPE drop code exp udp lite csm cov cross border */
+	NSS_PPE_STATS_DROP_CODE_EXP_UDP_LITE_CHECKSUM_ERR,              /* PPE drop code exp udp lite checksum err */
+	NSS_PPE_STATS_DROP_CODE_L3_MC_BRIDGE_ACTION,                    /* PPE drop code l3 mc bridge action */
+	NSS_PPE_STATS_DROP_CODE_L3_NO_ROUTE_PREHEAD_NAT_ACTION,         /* PPE drop code l3 no route prehead nat action */
+	NSS_PPE_STATS_DROP_CODE_L3_NO_ROUTE_PREHEAD_NAT_ERROR,          /* PPE drop code l3 no route prehead nat error */
+	NSS_PPE_STATS_DROP_CODE_L3_ROUTE_ACTION,                        /* PPE drop code l3 route action */
+	NSS_PPE_STATS_DROP_CODE_L3_NO_ROUTE_ACTION,                     /* PPE drop code l3 no route action */
+	NSS_PPE_STATS_DROP_CODE_L3_NO_ROUTE_NH_INVALID_ACTION,          /* PPE drop code l3 no route nh invalid action */
+	NSS_PPE_STATS_DROP_CODE_L3_NO_ROUTE_PREHEAD_ACTION,             /* PPE drop code l3 no route prehead action */
+	NSS_PPE_STATS_DROP_CODE_L3_BRIDGE_ACTION,                       /* PPE drop code l3 bridge action */
+	NSS_PPE_STATS_DROP_CODE_L3_FLOW_ACTION,                         /* PPE drop code l3 flow action */
+	NSS_PPE_STATS_DROP_CODE_L3_FLOW_MISS_ACTION,                    /* PPE drop code l3 flow miss action */
+	NSS_PPE_STATS_DROP_CODE_L2_EXP_MRU_FAIL,                        /* PPE drop code l2 exp mru fail */
+	NSS_PPE_STATS_DROP_CODE_L2_EXP_MTU_FAIL,                        /* PPE drop code l2 exp mtu fail */
+	NSS_PPE_STATS_DROP_CODE_L3_EXP_IP_PREFIX_BC,                    /* PPE drop code l3 exp ip prefix bc */
+	NSS_PPE_STATS_DROP_CODE_L3_EXP_MTU_FAIL,                        /* PPE drop code l3 exp mtu fail */
+	NSS_PPE_STATS_DROP_CODE_L3_EXP_MRU_FAIL,                        /* PPE drop code l3 exp mru fail */
+	NSS_PPE_STATS_DROP_CODE_L3_EXP_ICMP_RDT,                        /* PPE drop code l3 exp icmp rdt */
+	NSS_PPE_STATS_DROP_CODE_FAKE_MAC_HEADER_ERR,                    /* PPE drop code fake mac header err */
+	NSS_PPE_STATS_DROP_CODE_L3_EXP_IP_RT_TTL_ZERO,                  /* PPE drop code l3 exp ip rt ttl zero */
+	NSS_PPE_STATS_DROP_CODE_L3_FLOW_SERVICE_CODE_LOOP,              /* PPE drop code l3 flow service code loop */
+	NSS_PPE_STATS_DROP_CODE_L3_FLOW_DE_ACCELEARTE,                  /* PPE drop code l3 flow de accelearte */
+	NSS_PPE_STATS_DROP_CODE_L3_EXP_FLOW_SRC_IF_CHK_FAIL,            /* PPE drop code l3 exp flow src if chk fail */
+	NSS_PPE_STATS_DROP_CODE_L3_FLOW_SYNC_TOGGLE_MISMATCH,           /* PPE drop code l3 flow sync toggle mismatch */
+	NSS_PPE_STATS_DROP_CODE_L3_EXP_MTU_DF_FAIL,                     /* PPE drop code l3 exp mtu df fail */
+	NSS_PPE_STATS_DROP_CODE_L3_EXP_PPPOE_MULTICAST,                 /* PPE drop code l3 exp pppoe multicast */
+	NSS_PPE_STATS_DROP_CODE_IPV4_SG_UNKNOWN,                        /* PPE drop code ipv4 sg unknown */
+	NSS_PPE_STATS_DROP_CODE_IPV6_SG_UNKNOWN,                        /* PPE drop code ipv6 sg unknown */
+	NSS_PPE_STATS_DROP_CODE_ARP_SG_UNKNOWN,                         /* PPE drop code arp sg unknown */
+	NSS_PPE_STATS_DROP_CODE_ND_SG_UNKNOWN,                          /* PPE drop code nd sg unknown */
+	NSS_PPE_STATS_DROP_CODE_IPV4_SG_VIO,                            /* PPE drop code ipv4 sg vio */
+	NSS_PPE_STATS_DROP_CODE_IPV6_SG_VIO,                            /* PPE drop code ipv6 sg vio */
+	NSS_PPE_STATS_DROP_CODE_ARP_SG_VIO,                             /* PPE drop code arp sg vio */
+	NSS_PPE_STATS_DROP_CODE_ND_SG_VIO,                              /* PPE drop code nd sg vio */
+	NSS_PPE_STATS_DROP_CODE_L2_NEW_MAC_ADDRESS,                     /* PPE drop code l2 new mac address */
+	NSS_PPE_STATS_DROP_CODE_L2_HASH_COLLISION,                      /* PPE drop code l2 hash collision */
+	NSS_PPE_STATS_DROP_CODE_L2_STATION_MOVE,                        /* PPE drop code l2 station move */
+	NSS_PPE_STATS_DROP_CODE_L2_LEARN_LIMIT,                         /* PPE drop code l2 learn limit */
+	NSS_PPE_STATS_DROP_CODE_L2_SA_LOOKUP_ACTION,                    /* PPE drop code l2 sa lookup action */
+	NSS_PPE_STATS_DROP_CODE_L2_DA_LOOKUP_ACTION,                    /* PPE drop code l2 da lookup action */
+	NSS_PPE_STATS_DROP_CODE_APP_CTRL_ACTION,                        /* PPE drop code app ctrl action */
+	NSS_PPE_STATS_DROP_CODE_IN_VLAN_FILTER_ACTION,                  /* PPE drop code in vlan filter action */
+	NSS_PPE_STATS_DROP_CODE_IN_VLAN_XLT_MISS,                       /* PPE drop code in vlan xlt miss */
+	NSS_PPE_STATS_DROP_CODE_EG_VLAN_FILTER_DROP,                    /* PPE drop code eg vlan filter drop */
+	NSS_PPE_STATS_DROP_CODE_ACL_PRE_ACTION,                         /* PPE drop code acl pre action */
+	NSS_PPE_STATS_DROP_CODE_ACL_POST_ACTION,                        /* PPE drop code acl post action */
+	NSS_PPE_STATS_DROP_CODE_MC_BC_SA,                               /* PPE drop code mc bc sa */
+	NSS_PPE_STATS_DROP_CODE_NO_DESTINATION,                         /* PPE drop code no destination */
+	NSS_PPE_STATS_DROP_CODE_STG_IN_FILTER,                          /* PPE drop code stg in filter */
+	NSS_PPE_STATS_DROP_CODE_STG_EG_FILTER,                          /* PPE drop code stg eg filter */
+	NSS_PPE_STATS_DROP_CODE_SOURCE_FILTER_FAIL,                     /* PPE drop code source filter fail */
+	NSS_PPE_STATS_DROP_CODE_TRUNK_SEL_FAIL,                         /* PPE drop code trunk sel fail */
+	NSS_PPE_STATS_DROP_CODE_TX_EN_FAIL,                             /* PPE drop code tx en fail */
+	NSS_PPE_STATS_DROP_CODE_VLAN_TAG_FMT,                           /* PPE drop code vlan tag fmt */
+	NSS_PPE_STATS_DROP_CODE_CRC_ERR,                                /* PPE drop code crc err */
+	NSS_PPE_STATS_DROP_CODE_PAUSE_FRAME,                            /* PPE drop code pause frame */
+	NSS_PPE_STATS_DROP_CODE_PROMISC,                                /* PPE drop code promisc */
+	NSS_PPE_STATS_DROP_CODE_ISOLATION,                              /* PPE drop code isolation */
+	NSS_PPE_STATS_DROP_CODE_MGMT_APP,                               /* PPE drop code mgmt app */
+	NSS_PPE_STATS_DROP_CODE_FAKE_L2_PROT_ERR,                       /* PPE drop code fake l2 prot err */
+	NSS_PPE_STATS_DROP_CODE_POLICER,                                /* PPE drop code policer */
+	NSS_PPE_STATS_DROP_CODE_MAX                                     /* PPE drop code max */
+};
+
+/*
+ * PPE CPU codes
+ */
+#define NSS_PPE_STATS_CPU_CODE_MAX 150
+#define NSS_PPE_STATS_CPU_CODE_EXCEPTION_MAX 69
+#define NSS_PPE_STATS_CPU_CODE_NONEXCEPTION_START 69
+#define NSS_PPE_STATS_CPU_CODE_NONEXCEPTION_MAX (NSS_PPE_STATS_CPU_CODE_MAX - NSS_PPE_STATS_CPU_CODE_NONEXCEPTION_START)
+
+enum nss_ppe_stats_cc {
+	NSS_PPE_STATS_CPU_CODE_FORWARDING                         = 0, /* PPE cpu code forwarding */
+	NSS_PPE_STATS_CPU_CODE_EXP_UNKNOWN_L2_PROT                = 1, /* PPE cpu code exp unknown l2 prot */
+	NSS_PPE_STATS_CPU_CODE_EXP_PPPOE_WRONG_VER_TYPE           = 2, /* PPE cpu code exp pppoe wrong ver type */
+	NSS_PPE_STATS_CPU_CODE_EXP_PPPOE_WRONG_CODE               = 3, /* PPE cpu code exp pppoe wrong code */
+	NSS_PPE_STATS_CPU_CODE_EXP_PPPOE_UNSUPPORTED_PPP_PROT     = 4, /* PPE cpu code exp pppoe unsupported ppp prot */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_WRONG_VER                 = 5, /* PPE cpu code exp ipv4 wrong ver */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_SMALL_IHL                 = 6, /* PPE cpu code exp ipv4 small ihl */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_WITH_OPTION               = 7, /* PPE cpu code exp ipv4 with option */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_HDR_INCOMPLETE            = 8, /* PPE cpu code exp ipv4 hdr incomplete */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_BAD_TOTAL_LEN             = 9, /* PPE cpu code exp ipv4 bad total len */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_DATA_INCOMPLETE           = 10, /* PPE cpu code exp ipv4 data incomplete */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_FRAG                      = 11, /* PPE cpu code exp ipv4 frag */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_PING_OF_DEATH             = 12, /* PPE cpu code exp ipv4 ping of death */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_SNALL_TTL                 = 13, /* PPE cpu code exp ipv4 snall ttl */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_UNK_IP_PROT               = 14, /* PPE cpu code exp ipv4 unk ip prot */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_CHECKSUM_ERR              = 15, /* PPE cpu code exp ipv4 checksum err */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_INV_SIP                   = 16, /* PPE cpu code exp ipv4 inv sip */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_INV_DIP                   = 17, /* PPE cpu code exp ipv4 inv dip */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_LAND_ATTACK               = 18, /* PPE cpu code exp ipv4 land attack */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_AH_HDR_INCOMPLETE         = 19, /* PPE cpu code exp ipv4 ah hdr incomplete */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_AH_HDR_CROSS_BORDER       = 20, /* PPE cpu code exp ipv4 ah hdr cross border */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV4_ESP_HDR_INCOMPLETE        = 21, /* PPE cpu code exp ipv4 esp hdr incomplete */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_WRONG_VER                 = 22, /* PPE cpu code exp ipv6 wrong ver */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_HDR_INCOMPLETE            = 23, /* PPE cpu code exp ipv6 hdr incomplete */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_BAD_PAYLOAD_LEN           = 24, /* PPE cpu code exp ipv6 bad payload len */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_DATA_INCOMPLETE           = 25, /* PPE cpu code exp ipv6 data incomplete */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_WITH_EXT_HDR              = 26, /* PPE cpu code exp ipv6 with ext hdr */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_SMALL_HOP_LIMIT           = 27, /* PPE cpu code exp ipv6 small hop limit */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_INV_SIP                   = 28, /* PPE cpu code exp ipv6 inv sip */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_INV_DIP                   = 29, /* PPE cpu code exp ipv6 inv dip */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_LAND_ATTACK               = 30, /* PPE cpu code exp ipv6 land attack */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_FRAG                      = 31, /* PPE cpu code exp ipv6 frag */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_PING_OF_DEATH             = 32, /* PPE cpu code exp ipv6 ping of death */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_WITH_MORE_EXT_HDR         = 33, /* PPE cpu code exp ipv6 with more ext hdr */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_UNK_LAST_NEXT_HDR         = 34, /* PPE cpu code exp ipv6 unk last next hdr */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_MOBILITY_HDR_INCOMPLETE   = 35, /* PPE cpu code exp ipv6 mobility hdr incomplete */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_MOBILITY_HDR_CROSS_BORDER = 36, /* PPE cpu code exp ipv6 mobility hdr cross border */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_AH_HDR_INCOMPLETE         = 37, /* PPE cpu code exp ipv6 ah hdr incomplete */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_AH_HDR_CROSS_BORDER       = 38, /* PPE cpu code exp ipv6 ah hdr cross border */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_ESP_HDR_INCOMPLETE        = 39, /* PPE cpu code exp ipv6 esp hdr incomplete */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_ESP_HDR_CROSS_BORDER      = 40, /* PPE cpu code exp ipv6 esp hdr cross border */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_OTHER_EXT_HDR_INCOMPLETE  = 41, /* PPE cpu code exp ipv6 other ext hdr incomplete */
+	NSS_PPE_STATS_CPU_CODE_EXP_IPV6_OTHER_EXT_HDR_CROSS_BORDER = 42, /* PPE cpu code exp ipv6 other ext hdr cross border */
+	NSS_PPE_STATS_CPU_CODE_EXP_TCP_HDR_INCOMPLETE             = 43, /* PPE cpu code exp tcp hdr incomplete */
+	NSS_PPE_STATS_CPU_CODE_EXP_TCP_HDR_CROSS_BORDER           = 44, /* PPE cpu code exp tcp hdr cross border */
+	NSS_PPE_STATS_CPU_CODE_EXP_TCP_SMAE_SP_DP                 = 45, /* PPE cpu code exp tcp smae sp dp */
+	NSS_PPE_STATS_CPU_CODE_EXP_TCP_SMALL_DATA_OFFSET          = 46, /* PPE cpu code exp tcp small data offset */
+	NSS_PPE_STATS_CPU_CODE_EXP_TCP_FLAGS_0                    = 47, /* PPE cpu code exp tcp flags 0 */
+	NSS_PPE_STATS_CPU_CODE_EXP_TCP_FLAGS_1                    = 48, /* PPE cpu code exp tcp flags 1 */
+	NSS_PPE_STATS_CPU_CODE_EXP_TCP_FLAGS_2                    = 49, /* PPE cpu code exp tcp flags 2 */
+	NSS_PPE_STATS_CPU_CODE_EXP_TCP_FLAGS_3                    = 50, /* PPE cpu code exp tcp flags 3 */
+	NSS_PPE_STATS_CPU_CODE_EXP_TCP_FLAGS_4                    = 51, /* PPE cpu code exp tcp flags 4 */
+	NSS_PPE_STATS_CPU_CODE_EXP_TCP_FLAGS_5                    = 52, /* PPE cpu code exp tcp flags 5 */
+	NSS_PPE_STATS_CPU_CODE_EXP_TCP_FLAGS_6                    = 53, /* PPE cpu code exp tcp flags 6 */
+	NSS_PPE_STATS_CPU_CODE_EXP_TCP_FLAGS_7                    = 54, /* PPE cpu code exp tcp flags 7 */
+	NSS_PPE_STATS_CPU_CODE_EXP_TCP_CHECKSUM_ERR               = 55, /* PPE cpu code exp tcp checksum err */
+	NSS_PPE_STATS_CPU_CODE_EXP_UDP_HDR_INCOMPLETE             = 56, /* PPE cpu code exp udp hdr incomplete */
+	NSS_PPE_STATS_CPU_CODE_EXP_UDP_HDR_CROSS_BORDER           = 57, /* PPE cpu code exp udp hdr cross border */
+	NSS_PPE_STATS_CPU_CODE_EXP_UDP_SMAE_SP_DP                 = 58, /* PPE cpu code exp udp smae sp dp */
+	NSS_PPE_STATS_CPU_CODE_EXP_UDP_BAD_LEN                    = 59, /* PPE cpu code exp udp bad len */
+	NSS_PPE_STATS_CPU_CODE_EXP_UDP_DATA_INCOMPLETE            = 60, /* PPE cpu code exp udp data incomplete */
+	NSS_PPE_STATS_CPU_CODE_EXP_UDP_CHECKSUM_ERR               = 61, /* PPE cpu code exp udp checksum err */
+	NSS_PPE_STATS_CPU_CODE_EXP_UDP_LITE_HDR_INCOMPLETE        = 62, /* PPE cpu code exp udp lite hdr incomplete */
+	NSS_PPE_STATS_CPU_CODE_EXP_UDP_LITE_HDR_CROSS_BORDER      = 63, /* PPE cpu code exp udp lite hdr cross border */
+	NSS_PPE_STATS_CPU_CODE_EXP_UDP_LITE_SMAE_SP_DP            = 64, /* PPE cpu code exp udp lite smae sp dp */
+	NSS_PPE_STATS_CPU_CODE_EXP_UDP_LITE_CSM_COV_1_TO_7        = 65, /* PPE cpu code exp udp lite csm cov 1 to 7 */
+	NSS_PPE_STATS_CPU_CODE_EXP_UDP_LITE_CSM_COV_TOO_LONG      = 66, /* PPE cpu code exp udp lite csm cov too long */
+	NSS_PPE_STATS_CPU_CODE_EXP_UDP_LITE_CSM_COV_CROSS_BORDER  = 67, /* PPE cpu code exp udp lite csm cov cross border */
+	NSS_PPE_STATS_CPU_CODE_EXP_UDP_LITE_CHECKSUM_ERR          = 68, /* PPE cpu code exp udp lite checksum err */
+	NSS_PPE_STATS_CPU_CODE_EXP_FAKE_L2_PROT_ERR               = 69, /* PPE cpu code exp fake l2 prot err */
+	NSS_PPE_STATS_CPU_CODE_EXP_FAKE_MAC_HEADER_ERR            = 70, /* PPE cpu code exp fake mac header err */
+	NSS_PPE_STATS_CPU_CODE_EXP_BITMAP_MAX                     = 78, /* PPE cpu code exp bitmap max */
+	NSS_PPE_STATS_CPU_CODE_L2_EXP_MRU_FAIL                    = 79, /* PPE cpu code l2 exp mru fail */
+	NSS_PPE_STATS_CPU_CODE_L2_EXP_MTU_FAIL                    = 80, /* PPE cpu code l2 exp mtu fail */
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_IP_PREFIX_BC                = 81, /* PPE cpu code l3 exp ip prefix bc */
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_MTU_FAIL                    = 82, /* PPE cpu code l3 exp mtu fail */
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_MRU_FAIL                    = 83, /* PPE cpu code l3 exp mru fail */
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_ICMP_RDT                    = 84, /* PPE cpu code l3 exp icmp rdt */
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_IP_RT_TTL1_TO_ME            = 85, /* PPE cpu code l3 exp ip rt ttl1 to me */
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_IP_RT_TTL_ZERO              = 86, /* PPE cpu code l3 exp ip rt ttl zero */
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_SERVICE_CODE_LOOP          = 87, /* PPE cpu code l3 flow service code loop */
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_DE_ACCELERATE              = 88, /* PPE cpu code l3 flow de accelerate */
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_FLOW_SRC_IF_CHK_FAIL        = 89, /* PPE cpu code l3 exp flow src if chk fail */
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_SYNC_TOGGLE_MISMATCH       = 90, /* PPE cpu code l3 flow sync toggle mismatch */
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_MTU_DF_FAIL                 = 91, /* PPE cpu code l3 exp mtu df fail */
+	NSS_PPE_STATS_CPU_CODE_L3_EXP_PPPOE_MULTICAST             = 92, /* PPE cpu code l3 exp pppoe multicast */
+	NSS_PPE_STATS_CPU_CODE_MGMT_OFFSET                        = 96, /* PPE cpu code mgmt offset */
+	NSS_PPE_STATS_CPU_CODE_MGMT_EAPOL                         = 97, /* PPE cpu code mgmt eapol */
+	NSS_PPE_STATS_CPU_CODE_MGMT_PPPOE_DIS                     = 98, /* PPE cpu code mgmt pppoe dis */
+	NSS_PPE_STATS_CPU_CODE_MGMT_IGMP                          = 99, /* PPE cpu code mgmt igmp */
+	NSS_PPE_STATS_CPU_CODE_MGMT_ARP_REQ                       = 100, /* PPE cpu code mgmt arp req */
+	NSS_PPE_STATS_CPU_CODE_MGMT_ARP_REP                       = 101, /* PPE cpu code mgmt arp rep */
+	NSS_PPE_STATS_CPU_CODE_MGMT_DHCPv4                        = 102, /* PPE cpu code mgmt dhcpv4 */
+	NSS_PPE_STATS_CPU_CODE_MGMT_MLD                           = 107, /* PPE cpu code mgmt mld */
+	NSS_PPE_STATS_CPU_CODE_MGMT_NS                            = 108, /* PPE cpu code mgmt ns */
+	NSS_PPE_STATS_CPU_CODE_MGMT_NA                            = 109, /* PPE cpu code mgmt na */
+	NSS_PPE_STATS_CPU_CODE_MGMT_DHCPv6                        = 110, /* PPE cpu code mgmt dhcpv6 */
+	NSS_PPE_STATS_CPU_CODE_PTP_OFFSET                         = 112, /* PPE cpu code ptp offset */
+	NSS_PPE_STATS_CPU_CODE_PTP_SYNC                           = 113, /* PPE cpu code ptp sync */
+	NSS_PPE_STATS_CPU_CODE_PTP_FOLLOW_UP                      = 114, /* PPE cpu code ptp follow up */
+	NSS_PPE_STATS_CPU_CODE_PTP_DELAY_REQ                      = 115, /* PPE cpu code ptp delay req */
+	NSS_PPE_STATS_CPU_CODE_PTP_DELAY_RESP                     = 116, /* PPE cpu code ptp delay resp */
+	NSS_PPE_STATS_CPU_CODE_PTP_PDELAY_REQ                     = 117, /* PPE cpu code ptp pdelay req */
+	NSS_PPE_STATS_CPU_CODE_PTP_PDELAY_RESP                    = 118, /* PPE cpu code ptp pdelay resp */
+	NSS_PPE_STATS_CPU_CODE_PTP_PDELAY_RESP_FOLLOW_UP          = 119, /* PPE cpu code ptp pdelay resp follow up */
+	NSS_PPE_STATS_CPU_CODE_PTP_ANNOUNCE                       = 120, /* PPE cpu code ptp announce */
+	NSS_PPE_STATS_CPU_CODE_PTP_MANAGEMENT                     = 121, /* PPE cpu code ptp management */
+	NSS_PPE_STATS_CPU_CODE_PTP_SIGNALING                      = 122, /* PPE cpu code ptp signaling */
+	NSS_PPE_STATS_CPU_CODE_PTP_PKT_RSV_MSG                    = 127, /* PPE cpu code ptp pkt rsv msg */
+	NSS_PPE_STATS_CPU_CODE_IPV4_SG_UNKNOWN                    = 136, /* PPE cpu code ipv4 sg unknown */
+	NSS_PPE_STATS_CPU_CODE_IPV6_SG_UNKNOWN                    = 137, /* PPE cpu code ipv6 sg unknown */
+	NSS_PPE_STATS_CPU_CODE_ARP_SG_UNKNOWN                     = 138, /* PPE cpu code arp sg unknown */
+	NSS_PPE_STATS_CPU_CODE_ND_SG_UNKNOWN                      = 139, /* PPE cpu code nd sg unknown */
+	NSS_PPE_STATS_CPU_CODE_IPV4_SG_VIO                        = 140, /* PPE cpu code ipv4 sg vio */
+	NSS_PPE_STATS_CPU_CODE_IPV6_SG_VIO                        = 141, /* PPE cpu code ipv6 sg vio */
+	NSS_PPE_STATS_CPU_CODE_ARP_SG_VIO                         = 142, /* PPE cpu code arp sg vio */
+	NSS_PPE_STATS_CPU_CODE_ND_SG_VIO                          = 143, /* PPE cpu code nd sg vio */
+	NSS_PPE_STATS_CPU_CODE_L3_ROUTING_IP_TO_ME                = 148, /* PPE cpu code l3 routing ip to me */
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_SNAT_ACTION                = 149, /* PPE cpu code l3 flow snat action */
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_DNAT_ACTION                = 150, /* PPE cpu code l3 flow dnat action */
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_RT_ACTION                  = 151, /* PPE cpu code l3 flow rt action */
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_BR_ACTION                  = 152, /* PPE cpu code l3 flow br action */
+	NSS_PPE_STATS_CPU_CODE_L3_MC_BRIDGE_ACTION                = 153, /* PPE cpu code l3 mc bridge action */
+	NSS_PPE_STATS_CPU_CODE_L3_ROUTE_PREHEAD_RT_ACTION         = 154, /* PPE cpu code l3 route prehead rt action */
+	NSS_PPE_STATS_CPU_CODE_L3_ROUTE_PREHEAD_SNAPT_ACTION      = 155, /* PPE cpu code l3 route prehead snapt action */
+	NSS_PPE_STATS_CPU_CODE_L3_ROUTE_PREHEAD_DNAPT_ACTION      = 156, /* PPE cpu code l3 route prehead dnapt action */
+	NSS_PPE_STATS_CPU_CODE_L3_ROUTE_PREHEAD_SNAT_ACTION       = 157, /* PPE cpu code l3 route prehead snat action */
+	NSS_PPE_STATS_CPU_CODE_L3_ROUTE_PREHEAD_DNAT_ACTION       = 158, /* PPE cpu code l3 route prehead dnat action */
+	NSS_PPE_STATS_CPU_CODE_L3_NO_ROUTE_PREHEAD_NAT_ACTION     = 159, /* PPE cpu code l3 no route prehead nat action */
+	NSS_PPE_STATS_CPU_CODE_L3_NO_ROUTE_PREHEAD_NAT_ERROR      = 160, /* PPE cpu code l3 no route prehead nat error */
+	NSS_PPE_STATS_CPU_CODE_L3_ROUTE_ACTION                    = 161, /* PPE cpu code l3 route action */
+	NSS_PPE_STATS_CPU_CODE_L3_NO_ROUTE_ACTION                 = 162, /* PPE cpu code l3 no route action */
+	NSS_PPE_STATS_CPU_CODE_L3_NO_ROUTE_NH_INVALID_ACTION      = 163, /* PPE cpu code l3 no route nh invalid action */
+	NSS_PPE_STATS_CPU_CODE_L3_NO_ROUTE_PREHEAD_ACTION         = 164, /* PPE cpu code l3 no route prehead action */
+	NSS_PPE_STATS_CPU_CODE_L3_BRIDGE_ACTION                   = 165, /* PPE cpu code l3 bridge action */
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_ACTION                     = 166, /* PPE cpu code l3 flow action */
+	NSS_PPE_STATS_CPU_CODE_L3_FLOW_MISS_ACTION                = 167, /* PPE cpu code l3 flow miss action */
+	NSS_PPE_STATS_CPU_CODE_L2_NEW_MAC_ADDRESS                 = 168, /* PPE cpu code l2 new mac address */
+	NSS_PPE_STATS_CPU_CODE_L2_HASH_COLLISION                  = 169, /* PPE cpu code l2 hash collision */
+	NSS_PPE_STATS_CPU_CODE_L2_STATION_MOVE                    = 170, /* PPE cpu code l2 station move */
+	NSS_PPE_STATS_CPU_CODE_L2_LEARN_LIMIT                     = 171, /* PPE cpu code l2 learn limit */
+	NSS_PPE_STATS_CPU_CODE_L2_SA_LOOKUP_ACTION                = 172, /* PPE cpu code l2 sa lookup action */
+	NSS_PPE_STATS_CPU_CODE_L2_DA_LOOKUP_ACTION                = 173, /* PPE cpu code l2 da lookup action */
+	NSS_PPE_STATS_CPU_CODE_APP_CTRL_ACTION                    = 174, /* PPE cpu code app ctrl action */
+	NSS_PPE_STATS_CPU_CODE_IN_VLAN_FILTER_ACTION              = 175, /* PPE cpu code in vlan filter action */
+	NSS_PPE_STATS_CPU_CODE_IN_VLAN_XLT_MISS                   = 176, /* PPE cpu code in vlan xlt miss */
+	NSS_PPE_STATS_CPU_CODE_EG_VLAN_FILTER_DROP                = 177, /* PPE cpu code eg vlan filter drop */
+	NSS_PPE_STATS_CPU_CODE_ACL_PRE_ACTION                     = 178, /* PPE cpu code acl pre action */
+	NSS_PPE_STATS_CPU_CODE_ACL_POST_ACTION                    = 179, /* PPE cpu code acl post action */
+	NSS_PPE_STATS_CPU_CODE_SERVICE_CODE_ACTION                = 180, /* PPE cpu code service code action */
+};
+
+/*
+ * nss_ppe_sc_stats_debug
+ */
+struct nss_ppe_sc_stats_debug {
+	uint64_t nss_ppe_sc_cb_unregister;      /* Per service-code counter for callback not registered */
+	uint64_t nss_ppe_sc_cb_success;         /* Per service-code coutner for successful callback */
+	uint64_t nss_ppe_sc_cb_failure;         /* Per service-code counter for failure callback */
+};
+
+/*
+ * NSS PPE statistics
+ */
+struct nss_ppe_stats_debug {
+	uint64_t conn_stats[NSS_PPE_STATS_CONN_MAX];
+	uint32_t l3_stats[NSS_PPE_STATS_L3_MAX];
+	uint32_t code_stats[NSS_PPE_STATS_CODE_MAX];
+	struct nss_ppe_sc_stats_debug sc_stats[NSS_PPE_SC_MAX];
+	int32_t if_index;
+	uint32_t if_num;	/* nss interface number */
+	bool valid;
+};
+
+/*
+ * Data structures to store NSS PPE debug statistics
+ */
+extern struct nss_ppe_stats_debug nss_ppe_debug_stats;
+
+/**
+ * nss_ppe_stats_notification
+ *	PPE transmission statistics structure.
+ */
+struct nss_ppe_stats_notification {
+	struct nss_ppe_sc_stats_debug ppe_stats_sc[NSS_PPE_SC_MAX];	/* PPE service code stats. */
+	uint64_t ppe_stats_conn[NSS_PPE_STATS_CONN_MAX];		/* PPE connection statistics. */
+	uint32_t core_id;						/* Core ID. */
+	uint32_t if_num;						/* Interface number. */
+};
+
+/*
+ * NSS PPE statistics APIs
+ */
+extern void nss_ppe_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_ppe_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_ppe_sync_stats_msg *stats_msg, uint16_t if_num);
+extern void nss_ppe_stats_dentry_create(void);
+
+#endif /* __NSS_PPE_STATS_H */
diff --git a/qca-nss-drv/nss_ppe_strings.c b/qca-nss-drv/nss_ppe_strings.c
new file mode 100644
index 0000000..2949964
--- /dev/null
+++ b/qca-nss-drv/nss_ppe_strings.c
@@ -0,0 +1,532 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_ppe.h"
+#include "nss_strings.h"
+#include "nss_ppe_strings.h"
+
+/*
+ * nss_ppe_stats_str_conn
+ *	PPE statistics strings for nss flow stats
+ */
+struct nss_stats_info nss_ppe_stats_str_conn[NSS_PPE_STATS_CONN_MAX] = {
+	{"v4 routed flows",			NSS_STATS_TYPE_SPECIAL},
+	{"v4 bridge flows",			NSS_STATS_TYPE_SPECIAL},
+	{"v4 conn create req",			NSS_STATS_TYPE_SPECIAL},
+	{"v4 conn create fail",			NSS_STATS_TYPE_SPECIAL},
+	{"v4 conn destroy req",			NSS_STATS_TYPE_SPECIAL},
+	{"v4 conn destroy fail",		NSS_STATS_TYPE_SPECIAL},
+	{"v4 conn MC create req",		NSS_STATS_TYPE_SPECIAL},
+	{"v4 conn MC create fail",		NSS_STATS_TYPE_SPECIAL},
+	{"v4 conn MC update req",		NSS_STATS_TYPE_SPECIAL},
+	{"v4 conn MC update fail",		NSS_STATS_TYPE_SPECIAL},
+	{"v4 conn MC delete req",		NSS_STATS_TYPE_SPECIAL},
+	{"v4 conn MC delete fail",		NSS_STATS_TYPE_SPECIAL},
+	{"v4 conn unknown if",			NSS_STATS_TYPE_SPECIAL},
+	{"v6 routed flows",			NSS_STATS_TYPE_SPECIAL},
+	{"v6 bridge flows",			NSS_STATS_TYPE_SPECIAL},
+	{"v6 conn create req",			NSS_STATS_TYPE_SPECIAL},
+	{"v6 conn create fail",			NSS_STATS_TYPE_SPECIAL},
+	{"v6 conn destroy req",			NSS_STATS_TYPE_SPECIAL},
+	{"v6 conn destroy fail",		NSS_STATS_TYPE_SPECIAL},
+	{"v6 conn MC create req",		NSS_STATS_TYPE_SPECIAL},
+	{"v6 conn MC create fail",		NSS_STATS_TYPE_SPECIAL},
+	{"v6 conn MC update req",		NSS_STATS_TYPE_SPECIAL},
+	{"v6 conn MC update fail",		NSS_STATS_TYPE_SPECIAL},
+	{"v6 conn MC delete req",		NSS_STATS_TYPE_SPECIAL},
+	{"v6 conn MC delete fail",		NSS_STATS_TYPE_SPECIAL},
+	{"v6 conn unknown if",			NSS_STATS_TYPE_SPECIAL},
+	{"conn fail - vp full",			NSS_STATS_TYPE_SPECIAL},
+	{"conn fail - nexthop full",		NSS_STATS_TYPE_SPECIAL},
+	{"conn fail - flow full",		NSS_STATS_TYPE_SPECIAL},
+	{"conn fail - host full",		NSS_STATS_TYPE_SPECIAL},
+	{"conn fail - pub-ip full",		NSS_STATS_TYPE_SPECIAL},
+	{"conn fail - port not setup",		NSS_STATS_TYPE_SPECIAL},
+	{"conn fail - rw fifo full",		NSS_STATS_TYPE_SPECIAL},
+	{"conn fail - flow cmd failure",	NSS_STATS_TYPE_SPECIAL},
+	{"conn fail - unknown proto",		NSS_STATS_TYPE_SPECIAL},
+	{"conn fail - ppe not responding",	NSS_STATS_TYPE_SPECIAL},
+	{"conn fail - CE opaque invalid",	NSS_STATS_TYPE_SPECIAL},
+	{"conn fail - fqg full",		NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_ppe_stats_str_conn_strings_read()
+ *	Read ppe NSS flow statistics names
+ */
+static ssize_t nss_ppe_stats_str_conn_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_ppe_stats_str_conn, NSS_PPE_STATS_CONN_MAX);
+}
+
+/*
+ * nss_ppe_stats_str_conn_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(ppe_stats_str_conn);
+
+/*
+ * nss_ppe_stats_str_l3
+ *	PPE statistics strings for nss debug stats
+ */
+struct nss_stats_info nss_ppe_stats_str_l3[NSS_PPE_STATS_L3_MAX] = {
+	{"L3 dbg reg 0",	NSS_STATS_TYPE_SPECIAL},
+	{"L3 dbg reg 1",	NSS_STATS_TYPE_SPECIAL},
+	{"L3 dbg reg 2",	NSS_STATS_TYPE_SPECIAL},
+	{"L3 dbg reg 3",	NSS_STATS_TYPE_SPECIAL},
+	{"L3 dbg reg 4",	NSS_STATS_TYPE_SPECIAL},
+	{"L3 dbg reg port",	NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_ppe_stats_str_l3_strings_read()
+ *	Read ppe NSS debug statistics names
+ */
+static ssize_t nss_ppe_stats_str_l3_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_ppe_stats_str_l3, NSS_PPE_STATS_L3_MAX);
+}
+
+/*
+ * nss_ppe_stats_str_l3_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(ppe_stats_str_l3);
+
+/*
+ * nss_ppe_stats_str_code
+ *	PPE statistics strings for nss debug stats
+ */
+struct nss_stats_info nss_ppe_stats_str_code[NSS_PPE_STATS_CODE_MAX] = {
+	{"CPU_CODE",	NSS_STATS_TYPE_SPECIAL},
+	{"DROP_CODE",	NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_ppe_stats_str_code_strings_read()
+ *	Read ppe NSS debug statistics names
+ */
+static ssize_t nss_ppe_stats_str_code_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_ppe_stats_str_code, NSS_PPE_STATS_CODE_MAX);
+}
+
+/*
+ * nss_ppe_stats_str_code_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(ppe_stats_str_code);
+
+/*
+ * nss_ppe_stats_str_dc
+ *	PPE statistics strings for drop code
+ */
+struct nss_stats_info nss_ppe_stats_str_dc[NSS_PPE_STATS_DROP_CODE_MAX] = {
+	{"DROP_CODE_NONE",					NSS_STATS_TYPE_SPECIAL},
+	{"DROP_CODE_EXP_UNKNOWN_L2_PORT",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_PPPOE_WRONG_VER_TYPE",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_PPPOE_WRONG_CODE",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_PPPOE_UNSUPPORTED_PPP_PROT",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_WRONG_VER",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_SMALL_IHL",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_WITH_OPTION",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_HDR_INCOMPLETE",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_BAD_TOTAL_LEN",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_DATA_INCOMPLETE",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_FRAG",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_PING_OF_DEATH",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_SNALL_TTL",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_UNK_IP_PROT",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_CHECKSUM_ERR",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_INV_SIP",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_INV_DIP",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_LAND_ATTACK",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_AH_HDR_INCOMPLETE",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_AH_HDR_CROSS_BORDER",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV4_ESP_HDR_INCOMPLETE",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_WRONG_VER",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_HDR_INCOMPLETE",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_BAD_PAYLOAD_LEN",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_DATA_INCOMPLETE",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_WITH_EXT_HDR",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_SMALL_HOP_LIMIT",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_INV_SIP",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_INV_DIP",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_LAND_ATTACK",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_FRAG",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_PING_OF_DEATH",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_WITH_MORE_EXT_HDR",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_UNK_LAST_NEXT_HDR",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_MOBILITY_HDR_INCOMPLETE",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_MOBILITY_HDR_CROSS_BORDER",	NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_AH_HDR_INCOMPLETE",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_AH_HDR_CROSS_BORDER",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_ESP_HDR_INCOMPLETE",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_ESP_HDR_CROSS_BORDER",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_OTHER_EXT_HDR_INCOMPLETE",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_IPV6_OTHER_EXT_HDR_CROSS_BORDER",	NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_TCP_HDR_INCOMPLETE",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_TCP_HDR_CROSS_BORDER",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_TCP_SMAE_SP_DP",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_TCP_SMALL_DATA_OFFSET",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_TCP_FLAGS_0",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_TCP_FLAGS_1",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_TCP_FLAGS_2",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_TCP_FLAGS_3",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_TCP_FLAGS_4",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_TCP_FLAGS_5",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_TCP_FLAGS_6",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_TCP_FLAGS_7",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_TCP_CHECKSUM_ERR",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_UDP_HDR_INCOMPLETE",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_UDP_HDR_CROSS_BORDER",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_UDP_SMAE_SP_DP",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_UDP_BAD_LEN",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_UDP_DATA_INCOMPLETE",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_UDP_CHECKSUM_ERR",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_UDP_LITE_HDR_INCOMPLETE",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_UDP_LITE_HDR_CROSS_BORDER",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_UDP_LITE_SMAE_SP_DP",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_UDP_LITE_CSM_COV_1_TO_7",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_UDP_LITE_CSM_COV_TOO_LONG",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_UDP_LITE_CSM_COV_CROSS_BORDER",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EXP_UDP_LITE_CHECKSUM_ERR",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_MC_BRIDGE_ACTION",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_NO_ROUTE_PREHEAD_NAT_ACTION",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_NO_ROUTE_PREHEAD_NAT_ERROR",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_ROUTE_ACTION",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_NO_ROUTE_ACTION",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_NO_ROUTE_NH_INVALID_ACTION",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_NO_ROUTE_PREHEAD_ACTION",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_BRIDGE_ACTION",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_FLOW_ACTION",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_FLOW_MISS_ACTION",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L2_EXP_MRU_FAIL",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L2_EXP_MTU_FAIL",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_EXP_IP_PREFIX_BC",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_EXP_MTU_FAIL",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_EXP_MRU_FAIL",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_EXP_ICMP_RDT",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_FAKE_MAC_HEADER_ERR",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_EXP_IP_RT_TTL_ZERO",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_FLOW_SERVICE_CODE_LOOP",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_FLOW_DE_ACCELEARTE",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_EXP_FLOW_SRC_IF_CHK_FAIL",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_FLOW_SYNC_TOGGLE_MISMATCH",		NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_EXP_MTU_DF_FAIL",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L3_EXP_PPPOE_MULTICAST",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_IPV4_SG_UNKNOWN",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_IPV6_SG_UNKNOWN",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_ARP_SG_UNKNOWN",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_ND_SG_UNKNOWN",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_IPV4_SG_VIO",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_IPV6_SG_VIO",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_ARP_SG_VIO",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_ND_SG_VIO",					NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L2_NEW_MAC_ADDRESS",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L2_HASH_COLLISION",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L2_STATION_MOVE",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L2_LEARN_LIMIT",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L2_SA_LOOKUP_ACTION",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_L2_DA_LOOKUP_ACTION",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_APP_CTRL_ACTION",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_IN_VLAN_FILTER_ACTION",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_IN_VLAN_XLT_MISS",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_EG_VLAN_FILTER_DROP",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_ACL_PRE_ACTION",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_ACL_POST_ACTION",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_MC_BC_SA",					NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_NO_DESTINATION",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_STG_IN_FILTER",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_STG_EG_FILTER",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_SOURCE_FILTER_FAIL",			NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_TRUNK_SEL_FAIL",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_TX_EN_FAIL",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_VLAN_TAG_FMT",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_CRC_ERR",					NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_PAUSE_FRAME",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_PROMISC",					NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_ISOLATION",					NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_MGMT_APP",					NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_FAKE_L2_PROT_ERR",				NSS_STATS_TYPE_DROP},
+	{"DROP_CODE_POLICER",					NSS_STATS_TYPE_DROP}
+};
+
+/*
+ * nss_ppe_stats_str_dc_strings_read()
+ *	Read ppe drop code statistics names
+ */
+static ssize_t nss_ppe_stats_str_dc_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_ppe_stats_str_dc, NSS_PPE_STATS_DROP_CODE_MAX);
+}
+
+/*
+ * nss_ppe_stats_str_dc_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(ppe_stats_str_dc);
+
+/*
+ * nss_ppe_stats_str_sc
+ *	PPE statistics strings for service-code stats
+ */
+struct nss_stats_info nss_ppe_stats_str_sc[NSS_PPE_STATS_SERVICE_CODE_MAX] = {
+	{"cb_unregister",	NSS_STATS_TYPE_SPECIAL},
+	{"process_ok",		NSS_STATS_TYPE_SPECIAL},
+	{"process_fail",	NSS_STATS_TYPE_ERROR}
+};
+
+/*
+ * nss_ppe_stats_str_sc_strings_read()
+ *	Read ppe service code statistics names
+ */
+static ssize_t nss_ppe_stats_str_sc_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_ppe_stats_str_sc, NSS_PPE_STATS_SERVICE_CODE_MAX);
+}
+
+/*
+ * nss_ppe_stats_str_sc_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(ppe_stats_str_sc);
+
+/*
+ * nss_ppe_stats_str_cc
+ *	PPE statistics strings for cpu code
+ */
+struct nss_stats_info nss_ppe_stats_str_cc[NSS_PPE_STATS_CPU_CODE_MAX] = {
+	{"CPU_CODE_FORWARDING",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_UNKNOWN_L2_PROT",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_PPPOE_WRONG_VER_TYPE",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_WRONG_CODE",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_PPPOE_UNSUPPORTED_PPP_PROT",	NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_WRONG_VER",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_SMALL_IHL",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_WITH_OPTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_HDR_INCOMPLETE",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV4_BAD_TOTAL_LEN",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_DATA_INCOMPLETE",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_IPV4_FRAG",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV4_PING_OF_DEATH",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_SNALL_TTL",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV4_UNK_IP_PROT",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_CHECKSUM_ERR",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_INV_SIP",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_INV_DIP",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_LAND_ATTACK",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV4_AH_HDR_INCOMPLETE",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV4_AH_CROSS_BORDER",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV4_ESP_HDR_INCOMPLETE",	NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_WRONG_VER",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_HDR_INCOMPLETE",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV6_BAD_PAYLOAD_LEN",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_DATA_INCOMPLETE",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV6_WITH_EXT_HDR",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV6_SMALL_HOP_LIMIT",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_INV_SIP",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_INV_DIP",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_LAND_ATTACK",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_IPV6_FRAG",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV6_PING_OF_DEATH",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV6_WITH_EXT_HDR",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV6_UNK_NEXT_HDR",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV6_MOBILITY_HDR_INCOMPLETE",	NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV6_MOBILITY_CROSS_BORDER",	NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV6_AH_HDR_INCOMPLETE",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV6_AH_CROSS_BORDER",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV6_ESP_HDR_INCOMPLETE",	NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV6_ESP_CROSS_BORDER",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV6_OTHER_HDR_INCOMPLETE",	NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_IPV6_OTHER_EXT_CROSS_BORDER",	NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_HDR_INCOMPLETE",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_TCP_HDR_CROSS_BORDER",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_TCP_SMAE_SP_DP",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_TCP_SMALL_DATA_OFFSET",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_FLAGS_0",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_FLAGS_1",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_FLAGS_2",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_FLAGS_3",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_FLAGS_4",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_FLAGS_5",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_FLAGS_6",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_FLAGS_7",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_CHECKSUM_ERR",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_HDR_INCOMPLETE",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_UDP_HDR_CROSS_BORDER",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_UDP_SMAE_SP_DP",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_BAD_LEN",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_DATA_INCOMPLETE",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_CHECKSUM_ERR",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_UDP_LITE_HDR_INCOMPLETE",	NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_UDP_LITE_CROSS_BORDER",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_UDP_LITE_SP_DP",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_UDP_LITE_CSM_COV_TO_7",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_UDP_LITE_CSM_TOO_LONG",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_UDP_LITE_CSM_CROSS_BORDER",	NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_UDP_LITE_CHECKSUM_ERR",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_FAKE_L2_PROT_ERR",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EXP_FAKE_MAC_HEADER_ERR",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_BITMAP_MAX",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L2_MRU_FAIL",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L2_MTU_FAIL",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_EXP_IP_PREFIX_BC",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_MTU_FAIL",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_MRU_FAIL",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_ICMP_RDT",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_EXP_IP_RT_TO_ME",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_EXP_IP_TTL_ZERO",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_FLOW_SERVICE_CODE_LOOP",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_DE_ACCELERATE",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_EXP_FLOW_SRC_CHK_FAIL",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_FLOW_SYNC_TOGGLE_MISMATCH",	NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_EXP_MTU_DF_FAIL",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_PPPOE_MULTICAST",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_MGMT_OFFSET",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_MGMT_EAPOL",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_PPPOE_DIS",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_MGMT_IGMP",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_ARP_REQ",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_ARP_REP",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_MGMT_DHCPv4",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_MGMT_MLD",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_MGMT_NS",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_MGMT_NA",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_MGMT_DHCPv6",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_PTP_OFFSET",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_PTP_SYNC",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_FOLLOW_UP",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_DELAY_REQ",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_DELAY_RESP",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_PDELAY_REQ",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_PDELAY_RESP",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_PTP_PDELAY_RESP_FOLLOW_UP",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_PTP_ANNOUNCE",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_PTP_MANAGEMENT",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_PTP_SIGNALING",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_PTP_RSV_MSG",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_SG_UNKNOWN",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_SG_UNKNOWN",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_SG_UNKNOWN",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_SG_UNKNOWN",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_SG_VIO",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_SG_VIO",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_SG_VIO",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_SG_VIO",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_ROUTING_IP_TO_ME",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_SNAT_ACTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_DNAT_ACTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_RT_ACTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_BR_ACTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_BRIDGE_ACTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_ROUTE_PREHEAD_RT_ACTION",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_ROUTE_PREHEAD_SNAPT_ACTION",	NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_ROUTE_PREHEAD_DNAPT_ACTION",	NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_ROUTE_PREHEAD_SNAT_ACTION",	NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_ROUTE_PREHEAD_DNAT_ACTION",	NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_NO_ROUTE_NAT_ACTION",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_NO_ROUTE_NAT_ERROR",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_ROUTE_ACTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_ROUTE_ACTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_NO_ROUTE_INVALID_ACTION",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_NO_ROUTE_PREHEAD_ACTION",		NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_BRIDGE_ACTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_FLOW_ACTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L3_MISS_ACTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L2_MAC_ADDRESS",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_HASH_COLLISION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_STATION_MOVE",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_LEARN_LIMIT",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L2_LOOKUP_ACTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_L2_LOOKUP_ACTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_CTRL_ACTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_IN_FILTER_ACTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_IN_XLT_MISS",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_EG_FILTER_DROP",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_PRE_ACTION",				NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_POST_ACTION",			NSS_STATS_TYPE_EXCEPTION},
+	{"CPU_CODE_CODE_ACTION",			NSS_STATS_TYPE_EXCEPTION}
+};
+
+/*
+ * nss_ppe_stats_str_cc_strings_read()
+ *	Read ppe cpu code statistics names
+ */
+static ssize_t nss_ppe_stats_str_cc_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_ppe_stats_str_cc, NSS_PPE_STATS_CPU_CODE_MAX);
+}
+
+/*
+ * nss_ppe_stats_str_cc_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(ppe_stats_str_cc);
+
+/*
+ * nss_ppe_strings_dentry_create()
+ *	Create ppe statistics strings debug entry.
+ */
+void nss_ppe_strings_dentry_create(void)
+{
+	struct dentry *ppe_d = NULL;
+
+	if (!nss_top_main.strings_dentry) {
+		nss_warning("qca-nss-drv/strings is not present");
+		return;
+	}
+
+	ppe_d = debugfs_create_dir("ppe", nss_top_main.strings_dentry);
+	if (!ppe_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/ppe directory");
+		return;
+	}
+
+	if (!debugfs_create_file("stats_str_conn", 0400, ppe_d, &nss_top_main, &nss_ppe_stats_str_conn_strings_ops)) {
+		nss_warning("Failed to create qca-nss-drv/strings/ppe/stats_str_conn file");
+		debugfs_remove_recursive(ppe_d);
+		return;
+	}
+
+	if (!debugfs_create_file("stats_str_sc", 0400, ppe_d, &nss_top_main, &nss_ppe_stats_str_sc_strings_ops)) {
+		nss_warning("Failed to create qca-nss-drv/strings/ppe/stats_str_sc file");
+		debugfs_remove_recursive(ppe_d);
+		return;
+	}
+
+	if (!debugfs_create_file("stats_str_l3", 0400, ppe_d, &nss_top_main, &nss_ppe_stats_str_l3_strings_ops)) {
+		nss_warning("Failed to create qca-nss-drv/strings/ppe/stats_str_l3 file");
+		debugfs_remove_recursive(ppe_d);
+		return;
+	}
+
+	if (!debugfs_create_file("stats_str_code", 0400, ppe_d, &nss_top_main, &nss_ppe_stats_str_code_strings_ops)) {
+		nss_warning("Failed to create qca-nss-drv/strings/ppe/stats_str_code file");
+		debugfs_remove_recursive(ppe_d);
+		return;
+	}
+
+	if (!debugfs_create_file("stats_str_dc", 0400, ppe_d, &nss_top_main, &nss_ppe_stats_str_dc_strings_ops)) {
+		nss_warning("Failed to create qca-nss-drv/strings/ppe/stats_str_dc file");
+		debugfs_remove_recursive(ppe_d);
+		return;
+	}
+
+	if (!debugfs_create_file("stats_str_cc", 0400, ppe_d, &nss_top_main, &nss_ppe_stats_str_cc_strings_ops)) {
+		nss_warning("Failed to create qca-nss-drv/strings/ppe/stats_str_cc file");
+		debugfs_remove_recursive(ppe_d);
+		return;
+	}
+}
diff --git a/qca-nss-drv/nss_ppe_strings.h b/qca-nss-drv/nss_ppe_strings.h
new file mode 100644
index 0000000..e8fe77e
--- /dev/null
+++ b/qca-nss-drv/nss_ppe_strings.h
@@ -0,0 +1,32 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#ifndef __NSS_PPE_STRINGS_H
+#define __NSS_PPE_STRINGS_H
+
+#include "nss_ppe_stats.h"
+
+extern struct nss_stats_info nss_ppe_stats_str_conn[NSS_PPE_STATS_CONN_MAX];
+extern struct nss_stats_info nss_ppe_stats_str_sc[NSS_PPE_STATS_SERVICE_CODE_MAX];
+extern struct nss_stats_info nss_ppe_stats_str_l3[NSS_PPE_STATS_L3_MAX];
+extern struct nss_stats_info nss_ppe_stats_str_code[NSS_PPE_STATS_CODE_MAX];
+extern struct nss_stats_info nss_ppe_stats_str_dc[NSS_PPE_STATS_DROP_CODE_MAX];
+extern struct nss_stats_info nss_ppe_stats_str_cc[NSS_PPE_STATS_CPU_CODE_MAX];
+extern void nss_ppe_strings_dentry_create(void);
+
+#endif /* __NSS_PPE_STRINGS_H */
diff --git a/qca-nss-drv/nss_ppe_vp.c b/qca-nss-drv/nss_ppe_vp.c
new file mode 100644
index 0000000..a5411ce
--- /dev/null
+++ b/qca-nss-drv/nss_ppe_vp.c
@@ -0,0 +1,864 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * Header file for qca-ssdk APIs
+ */
+#include <ref/ref_vsi.h>
+
+#include "nss_ppe_vp.h"
+#include "nss_ppe_vp_stats.h"
+
+#define NSS_PPE_VP_TX_TIMEOUT 1000 /* 1 Second */
+
+static struct nss_vp_mapping *vp_map[NSS_MAX_DYNAMIC_INTERFACES] = {NULL};
+unsigned char nss_ppe_vp_cmd[NSS_PPE_VP_MAX_CMD_STR] __read_mostly;
+
+/*
+ * Private data structure
+ */
+static struct nss_ppe_vp_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+	void *cb;
+	void *app_data;
+	nss_ppe_port_t ppe_port_num;
+} ppe_vp_pvt;
+
+DEFINE_SPINLOCK(nss_ppe_vp_stats_lock);
+DEFINE_SPINLOCK(nss_ppe_vp_map_lock);
+
+struct nss_ppe_vp_stats_debug nss_ppe_vp_debug_stats;
+static struct dentry *nss_ppe_vp_dentry;
+
+/*
+ * nss_ppe_vp_get_map_index()
+ *	Get the index of the NSS-VP number mapping array.
+ */
+static inline int32_t nss_ppe_vp_get_map_index(nss_if_num_t if_num)
+{
+	return (if_num - NSS_DYNAMIC_IF_START);
+}
+
+/*
+ * nss_ppe_vp_verify_ifnum()
+ *	Verify PPE VP interface number.
+ */
+static inline bool nss_ppe_vp_verify_ifnum(int if_num)
+{
+	return (if_num == NSS_PPE_VP_INTERFACE);
+}
+
+/*
+ * nss_ppe_vp_map_dealloc()
+ *	Deallocate memory for the NSS interface number and PPE VP number mapping.
+ */
+static inline void nss_ppe_vp_map_dealloc(struct nss_vp_mapping *map)
+{
+	vfree(map);
+}
+
+/*
+ * nss_ppe_vp_map_alloc()
+ *	Allocate memory for the NSS interface number and PPE VP number mapping.
+ */
+static inline struct nss_vp_mapping *nss_ppe_vp_map_alloc(void)
+{
+	struct nss_vp_mapping *nss_vp_info = vzalloc(sizeof(struct nss_vp_mapping));
+	if (!nss_vp_info) {
+		nss_warning("No memory for allocating NSS-VP mapping instance");
+	}
+
+	return nss_vp_info;
+}
+
+/*
+ * nss_ppe_vp_proc_help()
+ *	Print usage information for ppe_vp configure sysctl.
+ */
+static void nss_ppe_vp_proc_help(void)
+{
+	nss_info_always("== for dynamic interface types read following file ==");
+	nss_info_always("/sys/kernel/debug/qca-nss-drv/stats/dynamic_if/type_names");
+	nss_info_always("NSS PPE VP create: echo <interface name> <dynamic interface type> > /proc/sys/nss/ppe_vp/create");
+	nss_info_always("NSS PPE VP destroy: echo <interface name> <dynamic interface type> > /proc/sys/nss/ppe_vp/destroy");
+}
+
+/*
+ * nss_ppe_vp_del_map()
+ *	Delete mapping between NSS interface number and VP number.
+ */
+static bool nss_ppe_vp_del_map(struct nss_ctx_instance *nss_ctx, nss_if_num_t if_num)
+{
+	int32_t idx;
+	nss_ppe_port_t ppe_port_num;
+	struct nss_vp_mapping *nss_vp_info;
+	uint16_t vp_index;
+
+	nss_assert((if_num >= NSS_DYNAMIC_IF_START) && (if_num < (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES)));
+
+	idx = nss_ppe_vp_get_map_index(if_num);
+	if ((idx < 0) || (idx >= NSS_MAX_DYNAMIC_INTERFACES)) {
+		nss_warning("%px: Invalid index. Cannot delete the PPE VP mapping. idx:%u", nss_ctx, idx);
+		return false;
+	}
+
+	spin_lock_bh(&nss_ppe_vp_map_lock);
+	nss_vp_info = vp_map[idx];
+	if (!nss_vp_info) {
+		spin_unlock_bh(&nss_ppe_vp_map_lock);
+		nss_warning("%px: Could not find the vp num in the mapping. NSS if num:%u", nss_ctx, if_num);
+		return false;
+	}
+
+	ppe_port_num = nss_vp_info->ppe_port_num;
+
+	nss_ppe_vp_map_dealloc(nss_vp_info);
+	vp_map[idx] = NULL;
+	spin_unlock_bh(&nss_ppe_vp_map_lock);
+
+	/*
+	 * Clear the PPE VP stats once PPE VP is deleted
+	 */
+	vp_index = ppe_port_num - NSS_PPE_VP_START;
+	spin_lock_bh(&nss_ppe_vp_stats_lock);
+	memset(&nss_ppe_vp_debug_stats.vp_stats[vp_index], 0, sizeof(struct nss_ppe_vp_statistics_debug));
+	spin_unlock_bh(&nss_ppe_vp_stats_lock);
+
+	nss_info("%px: Deleted NSS interface number and PPE VP number mapping successfully: NSS if num:%u at index:%u", nss_ctx, if_num, idx);
+
+	return true;
+}
+
+/*
+ * nss_ppe_vp_add_map()
+ *	Add mapping between NSS interface number and VP number.
+ */
+static bool nss_ppe_vp_add_map(struct nss_ctx_instance *nss_ctx ,nss_if_num_t if_num, struct nss_vp_mapping *nss_vp_info)
+{
+	uint32_t idx;
+	nss_ppe_port_t ppe_port_num;
+
+	nss_assert((if_num >= NSS_DYNAMIC_IF_START) && (if_num < (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES)));
+
+	if (!nss_vp_info) {
+		nss_warning("%px: Received invalid argument.", nss_ctx);
+		return false;
+	}
+
+	idx = nss_ppe_vp_get_map_index(if_num);
+	if ((idx < 0) || (idx >= NSS_MAX_DYNAMIC_INTERFACES)) {
+		nss_warning("%px: Invalid index. Cannot add the PPE VP mapping. idx:%u", nss_ctx, idx);
+		return false;
+	}
+
+	spin_lock_bh(&nss_ppe_vp_map_lock);
+	if (vp_map[idx]) {
+		spin_unlock_bh(&nss_ppe_vp_map_lock);
+		nss_warning("%px: Mapping exists already. NSS if num:%d index:%u, VP num:%u", nss_ctx, if_num, idx, vp_map[idx]->ppe_port_num);
+		return false;
+	}
+
+	vp_map[idx] = nss_vp_info;
+	ppe_port_num = vp_map[idx]->ppe_port_num;
+	spin_unlock_bh(&nss_ppe_vp_map_lock);
+
+	nss_info("%px: Mapping added successfully. NSS if num:%d index:%u, VP num:%u", nss_ctx, if_num, idx, ppe_port_num);
+
+	return true;
+}
+
+/*
+ * nss_ppe_vp_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_ppe_vp_callback(void *app_data, struct nss_ppe_vp_msg *npvm)
+{
+	if (npvm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("ppe_vp error response %d", npvm->cm.response);
+		ppe_vp_pvt.response = NSS_TX_FAILURE;
+		complete(&ppe_vp_pvt.complete);
+		return;
+	}
+
+	if (npvm->cm.type == NSS_IF_PPE_PORT_CREATE) {
+		ppe_vp_pvt.ppe_port_num = npvm->msg.if_msg.ppe_port_create.ppe_port_num;
+		nss_trace("PPE VP callback success VP num: %u", npvm->msg.if_msg.ppe_port_create.ppe_port_num);
+	}
+	ppe_vp_pvt.response = NSS_TX_SUCCESS;
+
+	complete(&ppe_vp_pvt.complete);
+}
+
+/*
+ * nss_ppe_vp_parse_vp_cmd()
+ *	Parse PPE VP create and destroy message and return the NSS interface number.
+ * Command usage:
+ * echo <interface name> <dynamic interface type> /proc/sys/nss/ppe_vp/create>
+ * echo ath0 6 > /proc/sys/nss/ppe_vp/create
+ * Since ath0 has only one type i.e. ath0 is NSS_DYNAMIC_INTERFACE_TYPE_VAP, the above command can be rewritten as
+ * echo ath0 > /proc/sys/nss/ppe_vp/create => Here 6 can be ignored.
+ */
+static nss_if_num_t nss_ppe_vp_parse_vp_cmd(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int32_t if_num;
+	struct net_device *dev;
+	uint32_t  dynamic_if_type = (uint32_t)NSS_DYNAMIC_INTERFACE_TYPE_NONE;
+	struct nss_ctx_instance *nss_ctx = nss_ppe_vp_get_context();
+	char *pos;
+	char cmd_buf[NSS_PPE_VP_MAX_CMD_STR] = {0}, dev_name[NSS_PPE_VP_MAX_CMD_STR] = {0};
+	size_t count = *lenp;
+	int ret = proc_dostring(ctl, write, buffer, lenp, ppos);
+
+	if (!write) {
+		nss_ppe_vp_proc_help();
+		return ret;
+	}
+
+	if (!nss_ctx) {
+		nss_warning("%px: NSS Context not found.", nss_ctx);
+		return -ENODEV;
+	}
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (count >= NSS_PPE_VP_MAX_CMD_STR) {
+		nss_ppe_vp_proc_help();
+		nss_warning("%px: Input string too big", nss_ctx);
+		return -E2BIG;
+	}
+
+	if (copy_from_user(cmd_buf, buffer, count)) {
+		nss_warning("%px: Cannot copy user's entry to kernel memory", nss_ctx);
+		return -EFAULT;
+	}
+
+	if ((pos = strrchr(cmd_buf, '\n')) != NULL) {
+		*pos = '\0';
+	}
+
+	if (sscanf(cmd_buf, "%s %u", dev_name, &dynamic_if_type) < 0) {
+		nss_warning("%px: PPE VP command parse failed", nss_ctx);
+		return -EFAULT;
+	}
+
+	dev = dev_get_by_name(&init_net, dev_name);
+	if (!dev) {
+		nss_warning("%px: Cannot find the net device", nss_ctx);
+		return -ENODEV;
+	}
+
+	nss_info("%px: Dynamic interface type: %u", nss_ctx, dynamic_if_type);
+	if ((dynamic_if_type < NSS_DYNAMIC_INTERFACE_TYPE_NONE) || (dynamic_if_type >= NSS_DYNAMIC_INTERFACE_TYPE_MAX)) {
+		nss_warning("%px: Invalid dynamic interface type: %d", nss_ctx, dynamic_if_type);
+		dev_put(dev);
+		return -EFAULT;
+	}
+
+	if_num = nss_cmn_get_interface_number_by_dev_and_type(dev, dynamic_if_type);
+	if (if_num < 0) {
+		nss_warning("%px: Invalid interface number:%s", nss_ctx, dev_name);
+		dev_put(dev);
+		return -EFAULT;
+	}
+
+	nss_info("%px: PPE VP create/destroy for, nss_if_num:%d dev_name:%s dynamic_if_type:%u", nss_ctx, if_num, dev_name, dynamic_if_type);
+	dev_put(dev);
+
+	return if_num;
+}
+
+/*
+ * nss_ppe_vp_tx_msg()
+ *	Transmit a ppe_vp message to NSS FW
+ */
+nss_tx_status_t nss_ppe_vp_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_ppe_vp_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+	nss_if_num_t if_num = ncm->interface;
+
+	/*
+	 * Trace messages.
+	 */
+	nss_ppe_vp_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!((ncm->type == NSS_IF_PPE_PORT_CREATE) || (ncm->type == NSS_IF_PPE_PORT_DESTROY))) {
+		nss_warning("%px: Invalid message type: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	if (!(if_num >= NSS_DYNAMIC_IF_START && (if_num < (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES)))) {
+		nss_warning("%px: invalid interface %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ * nss_ppe_vp_tx_msg_sync()
+ *	Transmit a ppe_vp message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_ppe_vp_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_ppe_vp_msg *npvm)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&ppe_vp_pvt.sem);
+
+	status = nss_ppe_vp_tx_msg(nss_ctx, npvm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: ppe_tx_msg failed", nss_ctx);
+		up(&ppe_vp_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&ppe_vp_pvt.complete, msecs_to_jiffies(NSS_PPE_VP_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: ppe_vp msg tx failed due to timeout", nss_ctx);
+		ppe_vp_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = ppe_vp_pvt.response;
+	up(&ppe_vp_pvt.sem);
+
+	return status;
+}
+
+/*
+ * nss_ppe_vp_get_context()
+ *	Get NSS context instance for ppe_vp
+ */
+struct nss_ctx_instance *nss_ppe_vp_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.ppe_handler_id];
+}
+EXPORT_SYMBOL(nss_ppe_vp_get_context);
+
+/*
+ * nss_ppe_vp_get_ppe_port_by_nssif()
+ *	Get vp number for a given NSS interface number.
+ */
+nss_ppe_port_t nss_ppe_vp_get_ppe_port_by_nssif(struct nss_ctx_instance *nss_ctx, nss_if_num_t if_num)
+{
+	uint32_t idx;
+	nss_ppe_port_t ppe_port_num;
+
+	if (!((if_num >= NSS_DYNAMIC_IF_START) && (if_num < (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES)))) {
+		nss_warning("%px: NSS invalid nss if num: %u", nss_ctx, if_num);
+		return -1;
+	}
+
+	idx = nss_ppe_vp_get_map_index(if_num);
+	if (idx < 0 || idx >= NSS_MAX_DYNAMIC_INTERFACES) {
+		nss_warning("%px: NSS invalid index: %d nss if num: %u",nss_ctx, idx, if_num);
+		return -1;
+	}
+
+	spin_lock_bh(&nss_ppe_vp_map_lock);
+	if (!vp_map[idx]) {
+		spin_unlock_bh(&nss_ppe_vp_map_lock);
+		nss_warning("%px: NSS interface and VP mapping is not present for nss if num: %u",nss_ctx, if_num);
+		return -1;
+	}
+	ppe_port_num = vp_map[idx]->ppe_port_num;
+	spin_unlock_bh(&nss_ppe_vp_map_lock);
+
+	nss_info("%px: VP num %d nss_if: %d",nss_ctx, ppe_port_num, if_num);
+
+	return ppe_port_num;
+}
+EXPORT_SYMBOL(nss_ppe_vp_get_ppe_port_by_nssif);
+
+/*
+ * nss_ppe_vp_destroy()
+ *	Destroy PPE virtual port for the given nss interface number.
+ */
+nss_tx_status_t nss_ppe_vp_destroy(struct nss_ctx_instance *nss_ctx, nss_if_num_t if_num)
+{
+	nss_tx_status_t status;
+	struct nss_ppe_vp_msg *npvm;
+	uint32_t idx;
+	int32_t vsi_id_valid = false;
+	int32_t vsi_id;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	idx = nss_ppe_vp_get_map_index(if_num);
+	if (idx < 0 || idx >= NSS_MAX_DYNAMIC_INTERFACES) {
+		nss_warning("%px: Cannot destroy PPE VP. Invalid index: %d. nss_if_num: %u", nss_ctx, idx, if_num);
+		return -1;
+	}
+
+	spin_lock_bh(&nss_ppe_vp_map_lock);
+	if (vp_map[idx]) {
+		vsi_id = vp_map[idx]->vsi_id;
+		vsi_id_valid = vp_map[idx]->vsi_id_valid;
+	}
+	spin_unlock_bh(&nss_ppe_vp_map_lock);
+
+	if (vsi_id_valid) {
+		/*
+		 * Send the dettach VSI message to the Firmware.
+		 */
+		if (nss_if_vsi_unassign(nss_ctx, if_num, vsi_id)) {
+			nss_warning("%px: PPE VP destroy failed. Failed to detach VSI to PPE VP interface %d vsi:%d", nss_ctx, if_num, vsi_id);
+			return NSS_TX_FAILURE;
+		}
+
+		if (ppe_vsi_free(NSS_PPE_VP_SWITCH_ID, vsi_id)) {
+			nss_warning("%px: PPE VP destroy failed. Failed to free PPE VSI. nss_if:%d vsi:%d", nss_ctx, if_num, vsi_id);
+			return NSS_TX_FAILURE;
+		}
+
+		nss_info("%px: PPE VP VSI detached successfully. VSI ID freed successfully. NSS if num:%u, VSI ID:%u", nss_ctx, if_num, vsi_id);
+	}
+
+	npvm = kzalloc(sizeof(struct nss_ppe_vp_msg), GFP_KERNEL);
+	if (!npvm) {
+		nss_warning("%px: Unable to allocate memeory of PPE VP message", nss_ctx);
+		return NSS_TX_FAILURE;
+	}
+
+	nss_trace("%px: PPE_VP will be destroyed for an interface: %d", nss_ctx, if_num);
+
+	/*
+	 * Destroy PPE VP for a dynamic interface.
+	 */
+	nss_cmn_msg_init(&npvm->cm, if_num, NSS_IF_PPE_PORT_DESTROY, 0, nss_ppe_vp_callback, NULL);
+
+	status = nss_ppe_vp_tx_msg_sync(nss_ctx, npvm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Unable to send PPE VP destroy message", nss_ctx);
+		kfree(npvm);
+		return NSS_TX_FAILURE;
+	}
+
+	kfree(npvm);
+
+	/*
+	 * Delete mapping between the NSS interface number and the VP number.
+	 */
+	if (!nss_ppe_vp_del_map(nss_ctx, if_num)) {
+		nss_warning("%px: Failed to delete the mapping for nss_if:%d", nss_ctx, if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	return status;
+}
+EXPORT_SYMBOL(nss_ppe_vp_destroy);
+
+/*
+ * nss_ppe_vp_create()
+ *	Create PPE virtual port for the given nss interface number.
+ */
+nss_tx_status_t nss_ppe_vp_create(struct nss_ctx_instance *nss_ctx, nss_if_num_t if_num)
+{
+	uint32_t vsi_id;
+	nss_tx_status_t status;
+	struct nss_ppe_vp_msg *npvm;
+	struct nss_vp_mapping *nss_vp_info;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	/*
+	 * TODO: No need to create VSI for tunnel interfaces. Only for VAP interfaces VSI is needed.
+	 * Allocate the VSI for the dynamic interface on which VP will be created.
+	 */
+	if (ppe_vsi_alloc(NSS_PPE_VP_SWITCH_ID, &vsi_id)) {
+		nss_warning("%px, Failed to alloc VSI ID, PPE VP create failed. nss_if:%u", nss_ctx, if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	npvm = kzalloc(sizeof(struct nss_ppe_vp_msg), GFP_KERNEL);
+	if (!npvm) {
+		nss_warning("%px: Unable to allocate memeory of PPE VP message", nss_ctx);
+		goto free_vsi;
+	}
+
+	nss_trace("%px: PPE_VP will be created for an interface: %d", nss_ctx, if_num);
+
+	/*
+	 * Create PPE VP for a dynamic interface.
+	 */
+	nss_cmn_msg_init(&npvm->cm, if_num, NSS_IF_PPE_PORT_CREATE,
+			sizeof(struct nss_if_ppe_port_create), nss_ppe_vp_callback, NULL);
+
+	status = nss_ppe_vp_tx_msg_sync(nss_ctx, npvm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Unable to send ppe_vp create message", nss_ctx);
+		goto free_alloc;
+	}
+
+	/*
+	 * Send the attach VSI message to the Firmware.
+	 */
+	if (nss_if_vsi_assign(nss_ctx, if_num, vsi_id) != NSS_TX_SUCCESS) {
+		nss_warning("%px: Failed to attach VSI to PPE VP interface. nss_if:%u vsi:%u", nss_ctx, if_num, vsi_id);
+		goto destroy_vp;
+	}
+
+	nss_vp_info = nss_ppe_vp_map_alloc();
+	if (!nss_vp_info) {
+		nss_warning("%px: No memory for allocating NSS-VP mapping instance", nss_ctx);
+		goto detach_vsi;
+	}
+
+	nss_vp_info->vsi_id = vsi_id;
+	nss_vp_info->vsi_id_valid = true;
+	nss_vp_info->if_num = if_num;
+	nss_vp_info->ppe_port_num = ppe_vp_pvt.ppe_port_num;
+
+	nss_info("%px: PPE VP allocated VSI ID:%u NSS interface number:%u VP no from Firmware:%u", nss_ctx, vsi_id, if_num, nss_vp_info->ppe_port_num);
+
+	/*
+	 * Add mapping between the NSS interface number and the VP number.
+	 */
+	if (!nss_ppe_vp_add_map(nss_ctx, if_num, nss_vp_info)) {
+		nss_warning("%px: Failed to add mapping for NSS interface number: %d", nss_ctx, if_num);
+		goto free_nss_vp_info;
+	}
+
+	kfree(npvm);
+
+	return status;
+
+free_nss_vp_info:
+	nss_ppe_vp_map_dealloc(nss_vp_info);
+
+detach_vsi:
+	nss_trace("%px: Detaching VSI ID :%u NSS Interface no:%u", nss_ctx, vsi_id, if_num);
+	if (nss_if_vsi_unassign(nss_ctx, if_num, vsi_id)) {
+		nss_warning("%px: Failed to free PPE VP VSI. nss_if:%u vsi:%u", nss_ctx, if_num, vsi_id);
+	}
+
+destroy_vp:
+	nss_trace("%px: Destroy Vp for NSS Interface num:%u VP num:%u", nss_ctx, if_num, npvm->msg.if_msg.ppe_port_create.ppe_port_num);
+	if (nss_ppe_vp_destroy(nss_ctx, if_num)) {
+		nss_warning("%px: PPE VP destroy failed, nss_if:%u", nss_ctx, if_num);
+	}
+
+free_alloc:
+	kfree(npvm);
+
+free_vsi:
+	nss_trace("%px: Free VSI ID :%u NSS Interface no:%u", nss_ctx, vsi_id, if_num);
+	if (ppe_vsi_free(NSS_PPE_VP_SWITCH_ID, vsi_id)) {
+		nss_warning("%px: Failed to free PPE VP VSI. NSS if num:%u vsi:%u", nss_ctx, if_num, vsi_id);
+	}
+
+	return NSS_TX_FAILURE;
+}
+EXPORT_SYMBOL(nss_ppe_vp_create);
+
+/*
+ * nss_ppe_vp_destroy_notify()
+ *	Get PPE VP destroy notification from NSS
+ */
+static void nss_ppe_vp_destroy_notify(struct nss_ctx_instance *nss_ctx, struct nss_ppe_vp_destroy_notify_msg *destroy_notify)
+{
+	nss_if_num_t nss_if_num;
+	uint32_t i;
+	int32_t vsi_id;
+	bool vsi_id_valid = false;
+	nss_ppe_port_t ppe_port_num = destroy_notify->ppe_port_num;
+
+	/*
+	 * Find NSS interface number corresponding to the VP num.
+	 */
+	spin_lock_bh(&nss_ppe_vp_map_lock);
+	for (i = 0; i < NSS_MAX_DYNAMIC_INTERFACES; i++) {
+		if (vp_map[i] && (ppe_port_num == vp_map[i]->ppe_port_num)) {
+			nss_if_num = vp_map[i]->if_num;
+			vsi_id = vp_map[i]->vsi_id;
+			vsi_id_valid = vp_map[i]->vsi_id_valid;
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_ppe_vp_map_lock);
+
+	if (i == NSS_MAX_DYNAMIC_INTERFACES) {
+		nss_warning("%px: Could not find the NSS interface number mapping for VP number: %u\n", nss_ctx, ppe_port_num);
+		return;
+	}
+
+	/*
+	 * Delete the nss_if_num to VP num mapping and reset the stats entry for this VP.
+	 */
+	if (!nss_ppe_vp_del_map(nss_ctx, nss_if_num)) {
+		nss_warning("%px: Failed to delete the mapping for nss_if: %d\n", nss_ctx, nss_if_num);
+		return;
+	}
+
+	if (vsi_id_valid && ppe_vsi_free(NSS_PPE_VP_SWITCH_ID, vsi_id)) {
+		nss_warning("%px: Failed to free PPE VSI. nss_if: %d vsi: %d\n", nss_ctx, nss_if_num, vsi_id);
+	}
+}
+
+/*
+ * nss_ppe_vp_handler()
+ *	Handle NSS -> HLOS messages for ppe
+ */
+static void nss_ppe_vp_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_ppe_vp_msg *msg = (struct nss_ppe_vp_msg *)ncm;
+	nss_ppe_vp_msg_callback_t cb;
+	void *ctx;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	nss_trace("%px ppe_vp msg: %px\n", nss_ctx, msg);
+	BUG_ON(!nss_ppe_vp_verify_ifnum(ncm->interface));
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_PPE_VP_MSG_MAX) {
+		nss_warning("%px: received invalid message %d for PPE_VP interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_ppe_vp_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_ppe_vp_log_rx_msg(msg);
+
+	switch (msg->cm.type) {
+	case NSS_PPE_VP_MSG_SYNC_STATS:
+		/*
+		 * Per VP stats msg
+		 */
+		nss_ppe_vp_stats_sync(nss_ctx, &msg->msg.stats, ncm->interface);
+		break;
+
+	case NSS_PPE_VP_MSG_DESTROY_NOTIFY:
+		/*
+		 * VP destroy notification
+		 */
+		nss_ppe_vp_destroy_notify(nss_ctx, &msg->msg.destroy_notify);
+		break;
+	}
+
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->nss_rx_interface_handlers[ncm->interface].app_data;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * Callback
+	 */
+	cb = (nss_ppe_vp_msg_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	cb(ctx, msg);
+}
+
+/*
+ * nss_ppe_vp_destroy_handler()
+ *	PPE VP destroy handler.
+ */
+static int nss_ppe_vp_destroy_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ppe_vp_get_context();
+	int32_t if_num;
+	nss_tx_status_t nss_tx_status;
+
+	if (!nss_ctx) {
+		nss_warning("%px: NSS Context not found.", nss_ctx);
+		return -ENODEV;
+	}
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if_num = nss_ppe_vp_parse_vp_cmd(ctl, write, buffer, lenp, ppos);
+	if (if_num < 0) {
+		nss_warning("%px: Invalid interface number: %d", nss_ctx, if_num);
+		return -EFAULT;
+	}
+
+	if (nss_ppe_vp_get_ppe_port_by_nssif(nss_ctx, if_num) < 0) {
+		nss_warning("%px: VP is not present for interface: %d", nss_ctx, if_num);
+		return -EEXIST;
+	}
+
+	nss_tx_status = nss_ppe_vp_destroy(nss_ctx, if_num);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Sending message failed, cannot destroy PPE_VP node nss_if: %u", nss_ctx, if_num);
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_ppe_vp_create_handler()
+ *	PPE VP create handler.
+ */
+static int nss_ppe_vp_create_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int32_t if_num;
+	struct nss_ctx_instance *nss_ctx = nss_ppe_vp_get_context();
+	nss_tx_status_t nss_tx_status;
+
+	if (!nss_ctx) {
+		nss_warning("%px: NSS Context not found.", nss_ctx);
+		return -ENODEV;
+	}
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if_num = nss_ppe_vp_parse_vp_cmd(ctl, write, buffer, lenp, ppos);
+	if (if_num < 0) {
+		nss_warning("%px: Invalid interface number: %d", nss_ctx, if_num);
+		return -EFAULT;
+	}
+
+	nss_info("%px: NSS interface number: %d", nss_ctx, if_num);
+
+	if (nss_ppe_vp_get_ppe_port_by_nssif(nss_ctx, if_num) > 0) {
+		nss_warning("%px: VP is already present for nss_if_num: %d", nss_ctx, if_num);
+		return -EEXIST;
+	}
+
+	nss_tx_status = nss_ppe_vp_create(nss_ctx, if_num);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Sending message failed, cannot create PPE VP node for nss_if_num: %u", nss_ctx, if_num);
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
+static struct ctl_table nss_ppe_vp_table[] = {
+	{
+		.procname       = "create",
+		.data           = &nss_ppe_vp_cmd,
+		.maxlen         = sizeof(nss_ppe_vp_cmd),
+		.mode           = 0644,
+		.proc_handler   = &nss_ppe_vp_create_handler,
+	},
+	{
+		.procname       = "destroy",
+		.data           = &nss_ppe_vp_cmd,
+		.maxlen         = sizeof(nss_ppe_vp_cmd),
+		.mode           = 0644,
+		.proc_handler   = &nss_ppe_vp_destroy_handler,
+	},
+	{ }
+};
+
+static struct ctl_table nss_ppe_vp_dir[] = {
+	{
+		.procname	= "ppe_vp",
+		.mode		= 0555,
+		.child		= nss_ppe_vp_table,
+	},
+	{ }
+};
+
+static struct ctl_table nss_ppe_vp_root_dir[] = {
+	{
+		.procname	= "nss",
+		.mode		= 0555,
+		.child		= nss_ppe_vp_dir,
+	},
+	{ }
+};
+
+static struct ctl_table_header *nss_ppe_vp_procfs_header;
+
+/*
+ * nss_ppe_vp_procfs_register()
+ *	Register sysctl specific to ppe_vp
+ */
+void nss_ppe_vp_procfs_register(void)
+{
+	/*
+	 * Register sysctl table.
+	 */
+	nss_ppe_vp_procfs_header = register_sysctl_table(nss_ppe_vp_root_dir);
+}
+
+/*
+ * uss_ppe_vp_procfs_unregister()
+ *	Unregister sysctl specific for ppe_vp
+ */
+void nss_ppe_vp_procfs_unregister(void)
+{
+	/*
+	 * Unregister sysctl table.
+	 */
+	if (nss_ppe_vp_procfs_header) {
+		unregister_sysctl_table(nss_ppe_vp_procfs_header);
+	}
+}
+
+/*
+ * nss_ppe_vp_register_handler()
+ *
+ */
+void nss_ppe_vp_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ppe_vp_get_context();
+
+	nss_ppe_vp_dentry = nss_ppe_vp_stats_dentry_create();
+	if (nss_ppe_vp_dentry == NULL) {
+		nss_warning("%px: Not able to create debugfs entry", nss_ctx);
+		return;
+	}
+
+	nss_core_register_handler(nss_ctx, NSS_PPE_VP_INTERFACE, nss_ppe_vp_handler, NULL);
+	nss_ppe_vp_procfs_register();
+
+	sema_init(&ppe_vp_pvt.sem, 1);
+	init_completion(&ppe_vp_pvt.complete);
+}
+
+/*
+ * nss_ppe_vp_unregister_handler()
+ *
+ */
+void nss_ppe_vp_unregister_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_ppe_vp_get_context();
+
+	debugfs_remove_recursive(nss_ppe_vp_dentry);
+	nss_ppe_vp_procfs_unregister();
+	nss_core_unregister_handler(nss_ctx, NSS_PPE_VP_INTERFACE);
+}
diff --git a/qca-nss-drv/nss_ppe_vp.h b/qca-nss-drv/nss_ppe_vp.h
new file mode 100644
index 0000000..ee65649
--- /dev/null
+++ b/qca-nss-drv/nss_ppe_vp.h
@@ -0,0 +1,130 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ppe_vp.h
+ *      NSS PPE virtual port header file
+ */
+
+#include <net/sock.h>
+#include "nss_tx_rx_common.h"
+
+/*
+ * Maximum number of virtual port supported by PPE hardware
+ */
+#define NSS_PPE_VP_MAX_NUM 192
+#define NSS_PPE_VP_START 64
+#define NSS_PPE_VP_NODE_STATS_MAX 32
+#define NSS_PPE_VP_SWITCH_ID 0
+#define NSS_PPE_VP_MAX_CMD_STR 200
+
+/*
+ * ppe_vp nss debug stats lock
+ */
+extern spinlock_t nss_ppe_vp_stats_lock;
+
+/*
+ * nss_ppe_vp_msg_error_type
+ *	ppe_vp message errors
+ */
+enum nss_ppe_vp_msg_error_type {
+	NSS_PPE_VP_MSG_ERROR_TYPE_UNKNOWN,	/* Unknown message error */
+	PPE_VP_MSG_ERROR_TYPE_INVALID_DI,	/* Invalid dynamic interface type */
+	NSS_PPE_VP_MSG_ERROR_TYPE_MAX		/* Maximum error type */
+};
+
+/*
+ * nss_ppe_vp_message_types
+ *	Message types for Packet Processing Engine (PPE) requests and responses.
+ */
+enum nss_ppe_vp_message_types {
+	NSS_PPE_VP_MSG_SYNC_STATS,
+	NSS_PPE_VP_MSG_DESTROY_NOTIFY,
+	NSS_PPE_VP_MSG_MAX,
+};
+
+/*
+ * nss_ppe_vp_statistics
+ *	Message structure for ppe_vp statistics
+ */
+struct nss_ppe_vp_statistics {
+	uint32_t nss_if;			/* NSS interface number corresponding to VP */
+	nss_ppe_port_t ppe_port_num;			/* VP number */
+	uint32_t rx_drop;			/* Rx drops due to VP node inactive */
+	uint32_t tx_drop;			/* Tx drops due to VP node inactive */
+	uint32_t packet_big_err;		/* Number of packets not sent to PPE because packet was too large */
+	struct nss_cmn_node_stats stats;	/* Common node statistics */
+};
+
+/*
+ * nss_ppe_vp_sync_stats_msg
+ *	Message information for ppe_vp synchronization statistics.
+ */
+struct nss_ppe_vp_sync_stats_msg {
+	uint16_t count;				/* Number of VP node stats with the sync message */
+	uint32_t rx_dropped[NSS_MAX_NUM_PRI];	/* Rx packet dropped due to queue full */
+	struct nss_ppe_vp_statistics vp_stats[NSS_PPE_VP_NODE_STATS_MAX];
+						/* Per service-code stats */
+};
+
+/*
+ * nss_ppe_vp_destroy_notify_msg
+ *	Message received as part of destroy notification from Firmware to Host.
+ */
+struct nss_ppe_vp_destroy_notify_msg {
+	nss_ppe_port_t ppe_port_num;			/* VP number */
+};
+
+/*
+ * nss_ppe_vp_msg
+ *	Message for receiving ppe_vp NSS to host messages.
+ */
+struct nss_ppe_vp_msg {
+	struct nss_cmn_msg cm;		/* Common message header. */
+
+	/*
+	 * Payload.
+	 */
+	union {
+		union nss_if_msgs if_msg;
+				/* NSS interface base messages. */
+		struct nss_ppe_vp_sync_stats_msg stats;
+				/* Synchronization statistics. */
+		struct nss_ppe_vp_destroy_notify_msg destroy_notify;
+				/* Information for the VP destroyed in Firmware. */
+	} msg;			/* Message payload. */
+};
+
+/*
+ * nss_vp_mapping
+ *	Structure to maintain the one-to-one mapping between the NSS interface number and VP number.
+ */
+struct nss_vp_mapping {
+	nss_if_num_t if_num;	/* NSS interface number. */
+	nss_ppe_port_t ppe_port_num;	/* PPE port number corresponding to the NSS interface number. */
+	uint32_t vsi_id;	/* VSI ID allocated for NSS interface */
+	bool vsi_id_valid;	/* Set to true if vsi_id field has a valid VSI else set to false. */
+};
+
+typedef void (*nss_ppe_vp_msg_callback_t)(void *app_data, struct nss_ppe_vp_msg *msg);
+
+/*
+ * Logging APIs.
+ */
+void nss_ppe_vp_log_tx_msg(struct nss_ppe_vp_msg *npvm);
+void nss_ppe_vp_log_rx_msg(struct nss_ppe_vp_msg *npvm);
diff --git a/qca-nss-drv/nss_ppe_vp_log.c b/qca-nss-drv/nss_ppe_vp_log.c
new file mode 100644
index 0000000..8c853df
--- /dev/null
+++ b/qca-nss-drv/nss_ppe_vp_log.c
@@ -0,0 +1,135 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ppe_vp_log.c
+ *	NSS PPE logger file.
+ */
+
+#include "nss_core.h"
+#include "nss_ppe_vp.h"
+
+/*
+ * nss_ppe_vp_log_error_response_types_str
+ *	Strings for error types for PPE-VP messages
+ */
+static int8_t *nss_ppe_vp_log_error_response_types_str[NSS_PPE_VP_MSG_ERROR_TYPE_MAX] __maybe_unused = {
+	"PPE VP Unknown message type",
+	"PPE VP Invalid dynamic interface type",
+};
+
+/*
+ * nss_ppe_vp_log_destroy_notify_msg()
+ *	Log NSS PPE VP destroy notification message.
+ */
+static void nss_ppe_vp_log_destroy_notify_msg(struct nss_ppe_vp_msg *npvm)
+{
+	struct nss_ppe_vp_destroy_notify_msg *npdnm __maybe_unused = &npvm->msg.destroy_notify;
+
+	nss_trace("%px: NSS PPE VP destroy notification message:\n"
+			"VP number: %u\n",
+			npdnm, npdnm->ppe_port_num);
+}
+
+/*
+ * nss_ppe_vp_log_verbose()
+ *	Log message contents.
+ */
+static void nss_ppe_vp_log_verbose(struct nss_ppe_vp_msg *npvm)
+{
+	switch (npvm->cm.type) {
+
+	case NSS_IF_PPE_PORT_CREATE:
+		nss_info("%px: PPE interface create message type:%d\n", npvm, npvm->cm.type);
+		break;
+
+	case NSS_IF_PPE_PORT_DESTROY:
+		nss_info("%px: PPE interface destroy message type:%d\n", npvm, npvm->cm.type);
+		break;
+
+	case NSS_IF_VSI_ASSIGN:
+		nss_info("%px: PPE interface VSI assign message type:%d\n", npvm, npvm->cm.type);
+		break;
+
+	case NSS_IF_VSI_UNASSIGN:
+		nss_info("%px: PPE interface VSI unassign message type:%d\n", npvm, npvm->cm.type);
+		break;
+
+	case NSS_PPE_VP_MSG_DESTROY_NOTIFY:
+		nss_ppe_vp_log_destroy_notify_msg(npvm);
+		break;
+
+	case NSS_PPE_VP_MSG_SYNC_STATS:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", npvm);
+		break;
+	}
+}
+
+/*
+ * nss_ppe_vp_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_ppe_vp_log_tx_msg(struct nss_ppe_vp_msg *npvm)
+{
+
+	if (!((npvm->cm.type == NSS_IF_PPE_PORT_CREATE) || (npvm->cm.type == NSS_IF_PPE_PORT_DESTROY))) {
+		nss_warning("%px: Invalid message type\n", npvm);
+		return;
+	}
+
+	nss_info("%px: type:%d\n", npvm, npvm->cm.type);
+	nss_ppe_vp_log_verbose(npvm);
+}
+
+/*
+ * nss_ppe_vp_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_ppe_vp_log_rx_msg(struct nss_ppe_vp_msg *npvm)
+{
+	if (npvm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", npvm);
+		return;
+	}
+
+	if (npvm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (npvm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type: %d, response[%d]: %s\n", npvm, npvm->cm.type,
+			npvm->cm.response, nss_cmn_response_str[npvm->cm.response]);
+		goto verbose;
+	}
+
+	if (npvm->cm.error >= NSS_PPE_VP_MSG_ERROR_TYPE_MAX) {
+		nss_warning("%px: msg failure - type: %d, response[%d]: %s, error[%d]:Invalid error\n",
+			npvm, npvm->cm.type, npvm->cm.response, nss_cmn_response_str[npvm->cm.response],
+			npvm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type: %d, response[%d]: %s, error[%d]: %s\n",
+		npvm, npvm->cm.type, npvm->cm.response, nss_cmn_response_str[npvm->cm.response],
+		npvm->cm.error, nss_ppe_vp_log_error_response_types_str[npvm->cm.error]);
+
+verbose:
+	nss_ppe_vp_log_verbose(npvm);
+}
diff --git a/qca-nss-drv/nss_ppe_vp_stats.c b/qca-nss-drv/nss_ppe_vp_stats.c
new file mode 100644
index 0000000..57c7995
--- /dev/null
+++ b/qca-nss-drv/nss_ppe_vp_stats.c
@@ -0,0 +1,229 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_ppe_vp.h"
+#include "nss_ppe_vp_stats.h"
+
+/*
+ * nss_ppe_vp_stats_cntrs
+ *	PPE VP stats counters displayed using debugfs
+ */
+enum nss_ppe_vp_stats_cntrs {
+	NSS_PPE_VP_STATS_VP_NUM,
+	NSS_PPE_VP_STATS_NSS_IF,
+	NSS_PPE_VP_STATS_RX_PKTS,
+	NSS_PPE_VP_STATS_RX_BYTES,
+	NSS_PPE_VP_STATS_TX_PKTS,
+	NSS_PPE_VP_STATS_TX_BYTES,
+	NSS_PPE_VP_STATS_RX_INACTIVE,
+	NSS_PPE_VP_STATS_TX_INACTIVE,
+	NSS_PPE_VP_STATS_PACKET_BIG,
+	NSS_PPE_VP_STATS_TX_Q_0_DROP,
+	NSS_PPE_VP_STATS_TX_Q_1_DROP,
+	NSS_PPE_VP_STATS_TX_Q_2_DROP,
+	NSS_PPE_VP_STATS_TX_Q_3_DROP,
+	NSS_PPE_VP_STATS_MAX
+};
+
+/*
+ * nss_ppe_vp_stats_rx_cntrs
+ *	PPE VP RX stats counters displayed using debugfs
+ */
+enum nss_ppe_vp_stats_rx_cntrs {
+	NSS_PPE_VP_STATS_RX_Q_0_DROP,
+	NSS_PPE_VP_STATS_RX_Q_1_DROP,
+	NSS_PPE_VP_STATS_RX_Q_2_DROP,
+	NSS_PPE_VP_STATS_RX_Q_3_DROP,
+	NSS_PPE_VP_STATS_RX_MAX
+};
+
+/*
+ * nss_ppe_vp_rx_stats_str
+ *	PPE VP Rx statistics strings
+ */
+struct nss_stats_info nss_ppe_vp_stats_rx_str[NSS_PPE_VP_STATS_RX_MAX] = {
+	{"rx_queue_0_drop"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue_1_drop"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue_2_drop"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue_3_drop"	, NSS_STATS_TYPE_DROP},
+};
+
+/*
+ * nss_ppe_vp_stats_str
+ *	PPE VP statistics strings
+ */
+struct nss_stats_info nss_ppe_vp_stats_str[NSS_PPE_VP_STATS_MAX] = {
+	{"ppe_port_num"		, NSS_STATS_TYPE_SPECIAL},
+	{"nss_if"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_packets"		, NSS_STATS_TYPE_COMMON},
+	{"rx_bytes"		, NSS_STATS_TYPE_COMMON},
+	{"tx_packets"		, NSS_STATS_TYPE_COMMON},
+	{"tx_bytes"		, NSS_STATS_TYPE_COMMON},
+	{"rx_inactive"		, NSS_STATS_TYPE_DROP},
+	{"tx_inactive"		, NSS_STATS_TYPE_DROP},
+	{"packet_large_err"	, NSS_STATS_TYPE_EXCEPTION},
+	{"tx_queue_0_drop"	, NSS_STATS_TYPE_DROP},
+	{"tx_queue_1_drop"	, NSS_STATS_TYPE_DROP},
+	{"tx_queue_2_drop"	, NSS_STATS_TYPE_DROP},
+	{"tx_queue_3_drop"	, NSS_STATS_TYPE_DROP},
+};
+
+/*
+ * nss_ppe_vp_stats_sync
+ *	PPE VP sync statistics from NSS
+ */
+void nss_ppe_vp_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_ppe_vp_sync_stats_msg *stats_msg, uint16_t if_num)
+{
+	uint16_t count = stats_msg->count;
+	uint16_t vp_index, i;
+
+	spin_lock_bh(&nss_ppe_vp_stats_lock);
+
+	/*
+	 * Update general rx dropped stats.
+	 */
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		nss_ppe_vp_debug_stats.rx_dropped[i] += stats_msg->rx_dropped[i];
+	}
+
+	/*
+	 * Update per VP tx and rx stats.
+	 */
+	while (count) {
+		count--;
+
+		/*
+		 * Update stats in global array
+		 */
+		vp_index = stats_msg->vp_stats[count].ppe_port_num - NSS_PPE_VP_START;
+		nss_ppe_vp_debug_stats.vp_stats[vp_index].ppe_port_num = stats_msg->vp_stats[count].ppe_port_num;
+		nss_ppe_vp_debug_stats.vp_stats[vp_index].nss_if = stats_msg->vp_stats[count].nss_if;
+		nss_ppe_vp_debug_stats.vp_stats[vp_index].rx_packets += stats_msg->vp_stats[count].stats.rx_packets;
+		nss_ppe_vp_debug_stats.vp_stats[vp_index].rx_bytes += stats_msg->vp_stats[count].stats.rx_bytes;
+		nss_ppe_vp_debug_stats.vp_stats[vp_index].tx_packets += stats_msg->vp_stats[count].stats.tx_packets;
+		nss_ppe_vp_debug_stats.vp_stats[vp_index].tx_bytes += stats_msg->vp_stats[count].stats.tx_bytes;
+		nss_ppe_vp_debug_stats.vp_stats[vp_index].rx_inactive_drop += stats_msg->vp_stats[count].rx_drop;
+		nss_ppe_vp_debug_stats.vp_stats[vp_index].tx_inactive_drop += stats_msg->vp_stats[count].tx_drop;
+		nss_ppe_vp_debug_stats.vp_stats[vp_index].packet_big_err += stats_msg->vp_stats[count].packet_big_err;
+		for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+			nss_ppe_vp_debug_stats.vp_stats[vp_index].tx_dropped[i] += stats_msg->vp_stats[count].stats.rx_dropped[i];
+		}
+
+		nss_trace("sync count:%d ppe_port_num %d rx_packets %d tx_packets %d\n",
+				count, stats_msg->vp_stats[count].ppe_port_num,
+				stats_msg->vp_stats[count].stats.rx_packets,
+				stats_msg->vp_stats[count].stats.tx_packets);
+	}
+	spin_unlock_bh(&nss_ppe_vp_stats_lock);
+}
+
+/*
+ * nss_ppe_vp_stats_read()
+ *	Read ppe vp statistics
+ */
+static ssize_t nss_ppe_vp_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int i;
+	char *lbuf = NULL;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	struct nss_ppe_vp_stats_debug *ppe_vp_stats;
+	uint32_t max_output_lines = ((NSS_PPE_VP_STATS_RX_MAX + NSS_PPE_VP_STATS_MAX) * NSS_PPE_VP_MAX_NUM) + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t stats_sz = sizeof(struct nss_ppe_vp_stats_debug);
+
+	ppe_vp_stats = kzalloc(stats_sz, GFP_KERNEL);
+	if (!ppe_vp_stats) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+
+	lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		kfree(ppe_vp_stats);
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	/*
+	 * Get vp stats
+	 */
+	spin_lock_bh(&nss_ppe_vp_stats_lock);
+	memcpy(ppe_vp_stats, &nss_ppe_vp_debug_stats, stats_sz);
+	spin_unlock_bh(&nss_ppe_vp_stats_lock);
+
+	/*
+	 * VP stats
+	 */
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "ppe_vp", NSS_STATS_SINGLE_CORE);
+
+	/*
+	 * Print Rx dropped.
+	 */
+	size_wr += nss_stats_print("ppe_vp", "ppe_vp rx dropped:"
+			, NSS_STATS_SINGLE_INSTANCE
+			, nss_ppe_vp_stats_rx_str
+			, ppe_vp_stats->rx_dropped
+			, NSS_PPE_VP_STATS_RX_MAX
+			, lbuf, size_wr, size_al);
+
+	/*
+	 * Print individual VP stats
+	 */
+	for (i = 0; i < NSS_PPE_VP_MAX_NUM; i++) {
+		if (!ppe_vp_stats->vp_stats[i].nss_if) {
+			continue;
+		}
+
+		size_wr += nss_stats_print("ppe_vp", "ppe_vp stats"
+				, NSS_STATS_SINGLE_INSTANCE
+				, nss_ppe_vp_stats_str
+				, (uint64_t *) &ppe_vp_stats->vp_stats[i]
+				, NSS_PPE_VP_STATS_MAX
+				, lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	kfree(ppe_vp_stats);
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_ppe_vp_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(ppe_vp)
+
+/*
+ * nss_ppe_vp_stats_dentry_create()
+ *	Create PPE statistics debug entry.
+ */
+struct dentry *nss_ppe_vp_stats_dentry_create(void)
+{
+	struct dentry *ppe_vp_d = debugfs_create_file("ppe_vp", 0400, nss_top_main.stats_dentry,
+					&nss_top_main, &nss_ppe_vp_stats_ops);
+	if (unlikely(ppe_vp_d == NULL)) {
+		nss_warning("Failed to create qca-nss-drv/stats/ppe_vp file");
+		return NULL;
+	}
+
+	return ppe_vp_d;
+}
diff --git a/qca-nss-drv/nss_ppe_vp_stats.h b/qca-nss-drv/nss_ppe_vp_stats.h
new file mode 100644
index 0000000..b435da5
--- /dev/null
+++ b/qca-nss-drv/nss_ppe_vp_stats.h
@@ -0,0 +1,63 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_ppe_vp_stats.h
+ *	NSS PPE-VP statistics header file.
+ */
+
+#ifndef __NSS_PPE_VP_STATS_H
+#define __NSS_PPE_VP_STATS_H
+
+/*
+ * NSS PPE-VP statistics
+ */
+struct nss_ppe_vp_statistics_debug {
+	uint64_t ppe_port_num;			/* VP number */
+	uint64_t nss_if;			/* NSS interface number corresponding to VP */
+	uint64_t rx_packets;                    /* Number of packets received. */
+	uint64_t rx_bytes;                    	/* Number of bytes received. */
+	uint64_t tx_packets;                    /* Number of packets transmitted. */
+	uint64_t tx_bytes;                    	/* Number of bytes transmitted. */
+	uint64_t rx_inactive_drop;		/* Number of packets dropped from PPE to VP due to VP inactive */
+	uint64_t tx_inactive_drop;		/* Number of packets dropped from VP to PPE due to VP inactive */
+	uint64_t packet_big_err;		/* Number of packets not sent to PPE because packet was too large */
+	uint64_t tx_dropped[NSS_MAX_NUM_PRI];   /* Tx packets dropped on due to queue full. */
+};
+
+/*
+ * NSS PPE-VP statistics
+ */
+struct nss_ppe_vp_stats_debug {
+	uint64_t rx_dropped[NSS_MAX_NUM_PRI];   /* Packets dropped on receive due to queue full. */
+	struct nss_ppe_vp_statistics_debug vp_stats[NSS_PPE_VP_MAX_NUM];
+						/* Per VP Tx and Rx stats. */
+};
+
+/*
+ * Data structures to store NSS PPE_VP debug statistics
+ */
+extern struct nss_ppe_vp_stats_debug nss_ppe_vp_debug_stats;
+
+/*
+ * NSS PPE-VP statistics APIs
+ */
+extern void nss_ppe_vp_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_ppe_vp_sync_stats_msg *stats_msg, uint16_t if_num);
+extern struct dentry *nss_ppe_vp_stats_dentry_create(void);
+
+#endif /* __NSS_PPE_VP_STATS_H */
diff --git a/qca-nss-drv/nss_pppoe.c b/qca-nss-drv/nss_pppoe.c
new file mode 100644
index 0000000..df613f7
--- /dev/null
+++ b/qca-nss-drv/nss_pppoe.c
@@ -0,0 +1,435 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_pppoe.c
+ *	NSS PPPoE APIs
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_pppoe_stats.h"
+#include "nss_pppoe_log.h"
+#include "nss_pppoe_strings.h"
+
+#define NSS_PPPOE_TX_TIMEOUT 3000 /* 3 Seconds */
+
+int nss_pppoe_br_accel_mode __read_mostly = NSS_PPPOE_BR_ACCEL_MODE_EN_5T;
+
+/*
+ * Private data structure
+ */
+static struct nss_pppoe_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+	void *cb;
+	void *app_data;
+} pppoe_pvt;
+
+/*
+ * nss_pppoe_br_help()
+ *	Usage information for pppoe bride accel mode
+ */
+static inline void nss_pppoe_br_help(int mode)
+{
+	printk("Incorrect pppoe bridge accel mode: %d\n", mode);
+	printk("Supported modes\n");
+	printk("%d: pppoe bridge acceleration disable\n", NSS_PPPOE_BR_ACCEL_MODE_DIS);
+	printk("%d: pppoe bridge acceleration enable with 5-tuple\n", NSS_PPPOE_BR_ACCEL_MODE_EN_5T);
+	printk("%d: pppoe bridge acceleration enable with 3-tuple\n", NSS_PPPOE_BR_ACCEL_MODE_EN_3T);
+}
+
+/*
+ * nss_pppoe_get_context()
+ */
+struct nss_ctx_instance *nss_pppoe_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.pppoe_handler_id];
+}
+EXPORT_SYMBOL(nss_pppoe_get_context);
+
+/*
+ * nss_pppoe_tx_msg()
+ *	Transmit a PPPoE message to NSS firmware
+ */
+static nss_tx_status_t nss_pppoe_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_pppoe_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+	enum nss_dynamic_interface_type type;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_pppoe_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+	type = nss_dynamic_interface_get_type(nss_pppoe_get_context(), ncm->interface);
+	if ((ncm->interface != NSS_PPPOE_INTERFACE) && (type != NSS_DYNAMIC_INTERFACE_TYPE_PPPOE)) {
+		nss_warning("%px: tx request for not PPPoE interface: %d type: %d\n",
+				nss_ctx, ncm->interface, type);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_PPPOE_MSG_MAX) {
+		nss_warning("%px: message type out of range: %d\n", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ * nss_pppoe_sync_msg_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_pppoe_sync_msg_callback(void *app_data, struct nss_pppoe_msg *npm)
+{
+	nss_pppoe_msg_callback_t callback = (nss_pppoe_msg_callback_t)pppoe_pvt.cb;
+	void *data = pppoe_pvt.app_data;
+
+	pppoe_pvt.cb = NULL;
+	pppoe_pvt.app_data = NULL;
+
+	pppoe_pvt.response = NSS_TX_SUCCESS;
+	if (npm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("pppoe Error response %d\n", npm->cm.response);
+		pppoe_pvt.response = NSS_TX_FAILURE;
+	}
+
+	if (callback) {
+		callback(data, npm);
+	}
+
+	complete(&pppoe_pvt.complete);
+}
+
+/*
+ * nss_pppoe_handler()
+ *	Handle NSS -> HLOS messages for PPPoE
+ */
+static void nss_pppoe_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_pppoe_msg *npm = (struct nss_pppoe_msg *)ncm;
+	void *ctx;
+	nss_pppoe_msg_callback_t cb;
+
+	BUG_ON(!(nss_is_dynamic_interface(ncm->interface) || ncm->interface == NSS_PPPOE_INTERFACE));
+
+	/*
+	 * Trace Messages
+	 */
+	nss_pppoe_log_rx_msg(npm);
+
+	/*
+	 * Sanity check the message type
+	 */
+	if (ncm->type >= NSS_PPPOE_MSG_MAX) {
+		nss_warning("%px: message type out of range: %d\n", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_pppoe_msg)) {
+		nss_warning("%px: message length is invalid: %d\n", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Handling PPPoE messages coming from NSS fw.
+	 */
+	switch (npm->cm.type) {
+	case NSS_PPPOE_MSG_SYNC_STATS:
+		/*
+		 * Update PPPoE debug statistics and send statistics notifications to the registered modules
+		 */
+		nss_pppoe_stats_sync(nss_ctx, &npm->msg.sync_stats, ncm->interface);
+		nss_pppoe_stats_notify(nss_ctx, ncm->interface);
+		break;
+	default:
+		nss_warning("%px: Received response %d for type %d, interface %d\n",
+				nss_ctx, ncm->response, ncm->type, ncm->interface);
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, pppoe sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->pppoe_msg_callback;
+		ncm->app_data = (nss_ptr_t)nss_ctx->subsys_dp_register[ncm->interface].app_data;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_pppoe_msg_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	cb(ctx, npm);
+}
+
+/*
+ * nss_pppoe_br_accel_mode_handler()
+ *	Enable/disable pppoe bridge acceleration in NSS
+ */
+int nss_pppoe_br_accel_mode_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_ctx_instance *nss_ctx = nss_pppoe_get_context();
+	struct nss_pppoe_msg npm;
+	struct nss_pppoe_br_accel_cfg_msg *npbacm;
+	nss_tx_status_t status;
+	int ret;
+	enum nss_pppoe_br_accel_modes current_value, new_val;
+
+	/*
+	 * Take snap shot of current value
+	 */
+	current_value = nss_pppoe_br_accel_mode;
+
+	/*
+	 * Write the variable with user input
+	 */
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret || (!write)) {
+		return ret;
+	}
+
+	new_val = nss_pppoe_br_accel_mode;
+	if ((new_val < NSS_PPPOE_BR_ACCEL_MODE_DIS) || (new_val >= NSS_PPPOE_BR_ACCEL_MODE_MAX)) {
+		nss_warning("%px: value out of range: %d\n", nss_ctx, new_val);
+		nss_pppoe_br_accel_mode = current_value;
+		nss_pppoe_br_help(new_val);
+		return -EINVAL;
+	}
+
+	memset(&npm, 0, sizeof(struct nss_pppoe_msg));
+	nss_pppoe_msg_init(&npm, NSS_PPPOE_INTERFACE, NSS_PPPOE_MSG_BR_ACCEL_CFG,
+		sizeof(struct nss_pppoe_br_accel_cfg_msg), NULL, NULL);
+
+	npbacm = &npm.msg.br_accel;
+	npbacm->br_accel_cfg = new_val;
+
+	status = nss_pppoe_tx_msg_sync(nss_ctx, &npm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Send acceleration mode message failed\n", nss_ctx);
+		nss_pppoe_br_accel_mode = current_value;
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/*
+ * nss_pppoe_get_br_accel_mode()
+ *	Gets PPPoE bridge acceleration mode
+ */
+enum nss_pppoe_br_accel_modes nss_pppoe_get_br_accel_mode(void)
+{
+	return nss_pppoe_br_accel_mode;
+}
+EXPORT_SYMBOL(nss_pppoe_get_br_accel_mode);
+
+/*
+ * nss_pppoe_tx_msg_sync()
+ */
+nss_tx_status_t nss_pppoe_tx_msg_sync(struct nss_ctx_instance *nss_ctx,
+						struct nss_pppoe_msg *msg)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&pppoe_pvt.sem);
+	pppoe_pvt.cb = (void *)msg->cm.cb;
+	pppoe_pvt.app_data = (void *)msg->cm.app_data;
+
+	msg->cm.cb = (nss_ptr_t)nss_pppoe_sync_msg_callback;
+	msg->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_pppoe_tx_msg(nss_ctx, msg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_pppoe_tx_msg failed\n", nss_ctx);
+		up(&pppoe_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&pppoe_pvt.complete, msecs_to_jiffies(NSS_PPPOE_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: PPPoE msg tx failed due to timeout\n", nss_ctx);
+		pppoe_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = pppoe_pvt.response;
+	up(&pppoe_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_pppoe_tx_msg_sync);
+
+/*
+ * nss_register_pppoe_session_if()
+ */
+struct nss_ctx_instance *nss_register_pppoe_session_if(uint32_t if_num,
+						       nss_pppoe_msg_callback_t notification_callback,
+						       struct net_device *netdev, uint32_t features, void *app_ctx)
+{
+	struct nss_ctx_instance *nss_ctx = nss_pppoe_get_context();
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_is_dynamic_interface(if_num));
+
+	if (!nss_pppoe_stats_pppoe_session_init(if_num, netdev)) {
+		return NULL;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, NULL, NULL, app_ctx, netdev, features);
+
+	nss_top_main.pppoe_msg_callback = notification_callback;
+
+	nss_core_register_handler(nss_ctx, if_num, nss_pppoe_handler, NULL);
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_register_pppoe_session_if);
+
+/*
+ * nss_unregister_pppoe_session_if()
+ */
+void nss_unregister_pppoe_session_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_pppoe_get_context();
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_is_dynamic_interface(if_num));
+
+	nss_pppoe_stats_pppoe_session_deinit(if_num);
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	nss_top_main.pppoe_msg_callback = NULL;
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+
+}
+EXPORT_SYMBOL(nss_unregister_pppoe_session_if);
+
+static struct ctl_table nss_pppoe_table[] = {
+	{
+		.procname               = "br_accel_mode",
+		.data                   = &nss_pppoe_br_accel_mode,
+		.maxlen                 = sizeof(int),
+		.mode                   = 0644,
+		.proc_handler           = &nss_pppoe_br_accel_mode_handler,
+	},
+	{ }
+};
+
+static struct ctl_table nss_pppoe_dir[] = {
+	{
+		.procname		= "pppoe",
+		.mode			= 0555,
+		.child			= nss_pppoe_table,
+	},
+	{ }
+};
+
+static struct ctl_table nss_pppoe_root_dir[] = {
+	{
+		.procname		= "nss",
+		.mode			= 0555,
+		.child			= nss_pppoe_dir,
+	},
+	{ }
+};
+
+static struct ctl_table nss_pppoe_root[] = {
+	{
+		.procname		= "dev",
+		.mode			= 0555,
+		.child			= nss_pppoe_root_dir,
+	},
+	{ }
+};
+
+static struct ctl_table_header *nss_pppoe_header;
+
+/*
+ * nss_pppoe_register_sysctl()
+ *	Register sysctl specific to pppoe
+ */
+void nss_pppoe_register_sysctl(void)
+{
+	/*
+	 * Register sysctl table.
+	 */
+	nss_pppoe_header = register_sysctl_table(nss_pppoe_root);
+}
+
+/*
+ * nss_pppoe_unregister_sysctl()
+ *	Unregister sysctl specific to pppoe
+ */
+void nss_pppoe_unregister_sysctl(void)
+{
+	/*
+	 * Unregister sysctl table.
+	 */
+	if (nss_pppoe_header) {
+		unregister_sysctl_table(nss_pppoe_header);
+	}
+}
+
+/*
+ * nss_pppoe_register_handler()
+ */
+void nss_pppoe_register_handler(void)
+{
+	nss_info("nss_pppoe_register_handler\n");
+	nss_core_register_handler(nss_pppoe_get_context(), NSS_PPPOE_INTERFACE, nss_pppoe_handler, NULL);
+
+	sema_init(&pppoe_pvt.sem, 1);
+	init_completion(&pppoe_pvt.complete);
+
+	nss_pppoe_stats_dentry_create();
+	nss_pppoe_strings_dentry_create();
+}
+
+/*
+ * nss_pppoe_msg_init()
+ */
+void nss_pppoe_msg_init(struct nss_pppoe_msg *npm, uint16_t if_num, uint32_t type, uint32_t len,
+			void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&npm->cm, if_num, type, len, (void *)cb, app_data);
+
+}
+EXPORT_SYMBOL(nss_pppoe_msg_init);
diff --git a/qca-nss-drv/nss_pppoe_log.c b/qca-nss-drv/nss_pppoe_log.c
new file mode 100644
index 0000000..7ab8b19
--- /dev/null
+++ b/qca-nss-drv/nss_pppoe_log.c
@@ -0,0 +1,133 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_pppoe_log.c
+ *	NSS PPPOE logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_pppoe_log_message_types_str
+ *	NSS PPPOE message strings
+ */
+static int8_t *nss_pppoe_log_message_types_str[NSS_PPPOE_MSG_MAX] __maybe_unused = {
+	"PPPOE Session Create",
+	"PPPOE Session Destroy",
+	"PPPOE Stats",
+};
+
+/*
+ * nss_pppoe_log_session_create_msg()
+ *	Log NSS Session Create.
+ */
+static void nss_pppoe_log_session_create_msg(struct nss_pppoe_msg *npm)
+{
+	struct nss_pppoe_create_msg *npcm __maybe_unused = &npm->msg.create;
+	nss_trace("%px: NSS PPPOE Session Create message \n"
+		"PPPOE Base Interface Number: %d\n"
+		"PPPOE MTU: %d\n"
+		"PPPOE Server MAC: %pM\n"
+		"PPPOE Local MAC: %pM\n"
+		"PPPOE Session ID: %d\n",
+		npcm, npcm->base_if_num,
+		npcm->mtu, npcm->server_mac,
+		npcm->local_mac, npcm->session_id);
+}
+
+/*
+ * nss_pppoe_log_session_destroy_msg()
+ *	Log NSS Session Destroy.
+ */
+static void nss_pppoe_log_session_destroy_msg(struct nss_pppoe_msg *npm)
+{
+	struct nss_pppoe_destroy_msg *npdm __maybe_unused = &npm->msg.destroy;
+	nss_trace("%px: NSS PPPOE Session Destroy message \n"
+		"PPPOE Session ID: %d\n"
+		"PPPOE Server MAC: %pM\n"
+		"PPPOE Local MAC: %pM\n",
+		npdm, npdm->session_id,
+		npdm->server_mac, npdm->local_mac);
+}
+
+/*
+ * nss_pppoe_log_verbose()
+ *	Log message contents.
+ */
+static void nss_pppoe_log_verbose(struct nss_pppoe_msg *npm)
+{
+	switch (npm->cm.type) {
+	case NSS_PPPOE_MSG_SESSION_CREATE:
+		nss_pppoe_log_session_create_msg(npm);
+		break;
+
+	case NSS_PPPOE_MSG_SESSION_DESTROY:
+		nss_pppoe_log_session_destroy_msg(npm);
+		break;
+
+	case NSS_PPPOE_MSG_SYNC_STATS:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", npm);
+		break;
+	}
+}
+
+/*
+ * nss_pppoe_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_pppoe_log_tx_msg(struct nss_pppoe_msg *npm)
+{
+	if (npm->cm.type >= NSS_PPPOE_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", npm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", npm, npm->cm.type, nss_pppoe_log_message_types_str[npm->cm.type]);
+	nss_pppoe_log_verbose(npm);
+}
+
+/*
+ * nss_pppoe_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_pppoe_log_rx_msg(struct nss_pppoe_msg *npm)
+{
+	if (npm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", npm);
+		return;
+	}
+
+	if (npm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (npm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", npm, npm->cm.type,
+			nss_pppoe_log_message_types_str[npm->cm.type],
+			npm->cm.response, nss_cmn_response_str[npm->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		npm, npm->cm.type, nss_pppoe_log_message_types_str[npm->cm.type],
+		npm->cm.response, nss_cmn_response_str[npm->cm.response]);
+
+verbose:
+	nss_pppoe_log_verbose(npm);
+}
diff --git a/qca-nss-drv/nss_pppoe_log.h b/qca-nss-drv/nss_pppoe_log.h
new file mode 100644
index 0000000..4636b08
--- /dev/null
+++ b/qca-nss-drv/nss_pppoe_log.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_PPPOE_LOG_H
+#define __NSS_PPPOE_LOG_H
+
+/*
+ * nss_pppoe.h
+ *	NSS PPPOE header file.
+ */
+
+/*
+ * Logger APIs
+ */
+
+/*
+ * nss_pppoe_log_tx_msg
+ *	Logs a pppoe message that is sent to the NSS firmware.
+ */
+void nss_pppoe_log_tx_msg(struct nss_pppoe_msg *nim);
+
+/*
+ * nss_pppoe_log_rx_msg
+ *	Logs a pppoe message that is received from the NSS firmware.
+ */
+void nss_pppoe_log_rx_msg(struct nss_pppoe_msg *nim);
+
+#endif /* __NSS_PPPOE_LOG_H */
diff --git a/qca-nss-drv/nss_pppoe_stats.c b/qca-nss-drv/nss_pppoe_stats.c
new file mode 100644
index 0000000..75b24c8
--- /dev/null
+++ b/qca-nss-drv/nss_pppoe_stats.c
@@ -0,0 +1,265 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include <nss_pppoe.h>
+#include "nss_pppoe_stats.h"
+#include "nss_pppoe_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_pppoe_stats_notifier);
+
+/*
+ * Lock used for PPPoE statistics
+ */
+static DEFINE_SPINLOCK(nss_pppoe_stats_lock);
+
+/*
+ * PPPoE session stats structure for debug interface
+ */
+struct nss_pppoe_stats_session_stats {
+	uint64_t stats[NSS_PPPOE_STATS_SESSION_MAX];
+						/* stats for the session */
+	int32_t if_index;	/* net device index for the session */
+	uint32_t if_num;	/* nss interface number */
+	bool valid;			/* dynamic interface valid flag */
+};
+
+/*
+ * PPPoE interface stats structure for base node and sessions
+ */
+struct nss_pppoe_stats {
+	uint64_t base_stats[NSS_PPPOE_STATS_BASE_MAX];
+						/* Base node stats */
+	struct nss_pppoe_stats_session_stats session_stats[NSS_MAX_PPPOE_DYNAMIC_INTERFACES];
+					/* Per session stats */
+};
+
+/*
+ * Global PPPoE stats decleration.
+ */
+static struct nss_pppoe_stats pppoe_stats;
+
+/*
+ * nss_pppoe_stats_read()
+ *	Read pppoe statistics
+ */
+static ssize_t nss_pppoe_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+
+	uint32_t max_output_lines = 2 /* header & footer for session stats */
+					+ NSS_MAX_PPPOE_DYNAMIC_INTERFACES * (NSS_PPPOE_STATS_SESSION_MAX + 2) /*session stats */
+					+ 2 + NSS_PPPOE_STATS_BASE_MAX + 2;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	struct net_device *dev;
+	int id;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	/*
+	 * Base node stats
+	 */
+	size_wr += nss_stats_print("pppoe", "pppoe base node stats start"
+					, NSS_STATS_SINGLE_INSTANCE
+					, nss_pppoe_strings_base_stats
+					, pppoe_stats.base_stats
+					, NSS_PPPOE_STATS_BASE_MAX
+					, lbuf, size_wr, size_al);
+
+	/*
+	 * Session stats
+	 */
+	for (id = 0; id < NSS_MAX_PPPOE_DYNAMIC_INTERFACES; id++) {
+		if (!pppoe_stats.session_stats[id].valid) {
+			continue;
+		}
+
+		dev = dev_get_by_index(&init_net, pppoe_stats.session_stats[id].if_index);
+		if (unlikely(!dev)) {
+			continue;
+		}
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%d. nss interface id=%d, netdevice=%s\n", id,
+				pppoe_stats.session_stats[id].if_num, dev->name);
+		dev_put(dev);
+
+		size_wr += nss_stats_print("pppoe", "pppoe session node stats"
+						, id
+						, nss_pppoe_strings_session_stats
+						, pppoe_stats.session_stats[id].stats
+						, NSS_PPPOE_STATS_SESSION_MAX
+						, lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_pppoe_stats_pppoe_session_init()
+ *	Initialize the session statistics.
+ */
+bool nss_pppoe_stats_pppoe_session_init(uint32_t if_num, struct net_device *dev)
+{
+	int i;
+
+	spin_lock_bh(&nss_pppoe_stats_lock);
+	for (i = 0; i < NSS_MAX_PPPOE_DYNAMIC_INTERFACES; i++) {
+		if (!pppoe_stats.session_stats[i].valid) {
+			pppoe_stats.session_stats[i].valid = true;
+			pppoe_stats.session_stats[i].if_num = if_num;
+			pppoe_stats.session_stats[i].if_index = dev->ifindex;
+			spin_unlock_bh(&nss_pppoe_stats_lock);
+			return true;
+		}
+	}
+	spin_unlock_bh(&nss_pppoe_stats_lock);
+
+	return false;
+}
+
+/*
+ * nss_pppoe_stats_pppoe_session_deinit()
+ *	De-initialize the session's stats.
+ */
+void nss_pppoe_stats_pppoe_session_deinit(uint32_t if_num)
+{
+	int i;
+
+	spin_lock_bh(&nss_pppoe_stats_lock);
+	for (i = 0; i < NSS_MAX_PPPOE_DYNAMIC_INTERFACES; i++) {
+		if (pppoe_stats.session_stats[i].if_num == if_num) {
+			memset(&pppoe_stats.session_stats[i], 0, sizeof(pppoe_stats.session_stats[i]));
+		}
+	}
+	spin_unlock_bh(&nss_pppoe_stats_lock);
+}
+
+/*
+ * nss_pppoe_stats_sync
+ *	Per session debug stats for pppoe
+ */
+void nss_pppoe_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_pppoe_sync_stats_msg *stats_msg, uint16_t if_num)
+{
+	int i;
+	spin_lock_bh(&nss_pppoe_stats_lock);
+	for (i = 0; i < NSS_MAX_PPPOE_DYNAMIC_INTERFACES; i++) {
+		if (pppoe_stats.session_stats[i].if_num == if_num) {
+			int j;
+
+			/*
+			 * Sync PPPoE session stats.
+			 */
+			pppoe_stats.session_stats[i].stats[NSS_PPPOE_STATS_SESSION_RX_PACKETS] += stats_msg->session_stats.node.rx_packets;
+			pppoe_stats.session_stats[i].stats[NSS_PPPOE_STATS_SESSION_RX_BYTES] += stats_msg->session_stats.node.rx_bytes;
+			pppoe_stats.session_stats[i].stats[NSS_PPPOE_STATS_SESSION_TX_PACKETS] += stats_msg->session_stats.node.tx_packets;
+			pppoe_stats.session_stats[i].stats[NSS_PPPOE_STATS_SESSION_TX_BYTES] += stats_msg->session_stats.node.tx_bytes;
+			pppoe_stats.session_stats[i].stats[NSS_PPPOE_STATS_SESSION_WRONG_VERSION_OR_TYPE] += stats_msg->session_stats.exception[NSS_PPPOE_SESSION_EXCEPTION_EVENT_WRONG_VERSION_OR_TYPE];
+			pppoe_stats.session_stats[i].stats[NSS_PPPOE_STATS_SESSION_WRONG_CODE] += stats_msg->session_stats.exception[NSS_PPPOE_SESSION_EXCEPTION_EVENT_WRONG_CODE];
+			pppoe_stats.session_stats[i].stats[NSS_PPPOE_STATS_SESSION_UNSUPPORTED_PPP_PROTOCOL] += stats_msg->session_stats.exception[NSS_PPPOE_SESSION_EXCEPTION_EVENT_UNSUPPORTED_PPP_PROTOCOL];
+
+			/*
+			 * Sync PPPoE base node stats coming with this session's stats.
+			 */
+			pppoe_stats.base_stats[NSS_PPPOE_STATS_BASE_RX_PACKETS] += stats_msg->base_stats.node.rx_packets;
+			pppoe_stats.base_stats[NSS_PPPOE_STATS_BASE_RX_BYTES] += stats_msg->base_stats.node.rx_bytes;
+			pppoe_stats.base_stats[NSS_PPPOE_STATS_BASE_TX_PACKETS] += stats_msg->base_stats.node.tx_packets;
+			pppoe_stats.base_stats[NSS_PPPOE_STATS_BASE_TX_BYTES] += stats_msg->base_stats.node.tx_bytes;
+
+			for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+				pppoe_stats.base_stats[NSS_PPPOE_STATS_BASE_RX_QUEUE_0_DROPPED + j] += stats_msg->base_stats.node.rx_dropped[j];
+			}
+
+			/*
+			 * Sync PPPoE base exception stats coming with this session's stats.
+			 */
+			pppoe_stats.base_stats[NSS_PPPOE_STATS_BASE_SHORT_PPPOE_HDR_LENGTH] += stats_msg->base_stats.exception[NSS_PPPOE_BASE_EXCEPTION_EVENT_SHORT_PPPOE_HDR_LENGTH];
+			pppoe_stats.base_stats[NSS_PPPOE_STATS_BASE_SHORT_PACKET_LENGTH] += stats_msg->base_stats.exception[NSS_PPPOE_BASE_EXCEPTION_EVENT_SHORT_PACKET_LENGTH];
+			pppoe_stats.base_stats[NSS_PPPOE_STATS_BASE_WRONG_VERSION_OR_TYPE] += stats_msg->base_stats.exception[NSS_PPPOE_BASE_EXCEPTION_EVENT_WRONG_VERSION_OR_TYPE];
+			pppoe_stats.base_stats[NSS_PPPOE_STATS_BASE_WRONG_CODE] += stats_msg->base_stats.exception[NSS_PPPOE_BASE_EXCEPTION_EVENT_WRONG_CODE];
+			pppoe_stats.base_stats[NSS_PPPOE_STATS_BASE_UNSUPPORTED_PPP_PROTOCOL] += stats_msg->base_stats.exception[NSS_PPPOE_BASE_EXCEPTION_EVENT_UNSUPPORTED_PPP_PROTOCOL];
+			pppoe_stats.base_stats[NSS_PPPOE_STATS_BASE_DISABLED_BRIDGE_PACKET] += stats_msg->base_stats.exception[NSS_PPPOE_BASE_EXCEPTION_EVENT_DISABLED_BRIDGE_PACKET];
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_pppoe_stats_lock);
+}
+
+/*
+ * nss_pppoe_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(pppoe);
+
+/*
+ * nss_pppoe_stats_dentry_create()
+ *	Create PPPoE node statistics debug entry.
+ */
+void nss_pppoe_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("pppoe", &nss_pppoe_stats_ops);
+}
+
+/*
+ * nss_pppoe_stats_notify()
+ *	Sends notifications to the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_pppoe_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_pppoe_stats_notification nss_pppoe_stats;
+	int id;
+
+	for (id = 0; id < NSS_MAX_PPPOE_DYNAMIC_INTERFACES; id++) {
+		if (pppoe_stats.session_stats[id].if_num == if_num) {
+			memcpy(&nss_pppoe_stats.session_stats, &pppoe_stats.session_stats[id].stats, sizeof(nss_pppoe_stats.session_stats));
+		}
+	}
+	memcpy(&nss_pppoe_stats.base_stats, &pppoe_stats.base_stats, sizeof(nss_pppoe_stats.base_stats));
+	nss_pppoe_stats.core_id = nss_ctx->id;
+	nss_pppoe_stats.if_num = if_num;
+	atomic_notifier_call_chain(&nss_pppoe_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&nss_pppoe_stats);
+}
+
+/*
+ * nss_pppoe_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_pppoe_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_pppoe_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_pppoe_stats_register_notifier);
+
+/*
+ * nss_pppoe_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_pppoe_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_pppoe_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_pppoe_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_pppoe_stats.h b/qca-nss-drv/nss_pppoe_stats.h
new file mode 100644
index 0000000..41c726e
--- /dev/null
+++ b/qca-nss-drv/nss_pppoe_stats.h
@@ -0,0 +1,28 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2017,2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_PPPOE_STATS_H
+#define __NSS_PPPOE_STATS_H
+
+/*
+ * PPPoE statistics APIs
+ */
+extern void nss_pppoe_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_pppoe_stats_dentry_create(void);
+extern void nss_pppoe_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_pppoe_sync_stats_msg *stats_msg, uint16_t if_num);
+extern bool nss_pppoe_stats_pppoe_session_init(uint32_t if_num, struct net_device *dev);
+extern void nss_pppoe_stats_pppoe_session_deinit(uint32_t if_num);
+#endif /* __NSS_PPPOE_STATS_H */
diff --git a/qca-nss-drv/nss_pppoe_strings.c b/qca-nss-drv/nss_pppoe_strings.c
new file mode 100644
index 0000000..953945b
--- /dev/null
+++ b/qca-nss-drv/nss_pppoe_strings.c
@@ -0,0 +1,121 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include <nss_pppoe.h>
+#include "nss_strings.h"
+
+/*
+ * nss_pppoe_strings_session_stats
+ *	PPPoE session stats strings.
+ */
+struct nss_stats_info nss_pppoe_strings_session_stats[NSS_PPPOE_STATS_SESSION_MAX]  = {
+	{"rx_pkts"			, NSS_STATS_TYPE_COMMON},
+	{"rx_byts"			, NSS_STATS_TYPE_COMMON},
+	{"tx_pkts"			, NSS_STATS_TYPE_COMMON},
+	{"tx_byts"			, NSS_STATS_TYPE_COMMON},
+	{"wrong_version_or_type"	, NSS_STATS_TYPE_EXCEPTION},
+	{"wrong_code"			, NSS_STATS_TYPE_EXCEPTION},
+	{"unsupported_ppp_protocol"	, NSS_STATS_TYPE_EXCEPTION}
+};
+
+/*
+ * nss_pppoe_strings_base_stats
+ *	PPPoE base node stats strings.
+ */
+struct nss_stats_info nss_pppoe_strings_base_stats[NSS_PPPOE_STATS_BASE_MAX] = {
+	{"rx_packets"                   , NSS_STATS_TYPE_COMMON},
+	{"rx_bytes"                     , NSS_STATS_TYPE_COMMON},
+	{"tx_packets"                   , NSS_STATS_TYPE_COMMON},
+	{"tx_bytes"                     , NSS_STATS_TYPE_COMMON},
+	{"rx_dropped[0]"                , NSS_STATS_TYPE_DROP},
+	{"rx_dropped[1]"                , NSS_STATS_TYPE_DROP},
+	{"rx_dropped[2]"                , NSS_STATS_TYPE_DROP},
+	{"rx_dropped[3]"                , NSS_STATS_TYPE_DROP},
+	{"short_pppoe_hdr_length"       , NSS_STATS_TYPE_EXCEPTION},
+	{"short_packet_length"          , NSS_STATS_TYPE_EXCEPTION},
+	{"wrong_version_or_type"        , NSS_STATS_TYPE_EXCEPTION},
+	{"wrong_code"                   , NSS_STATS_TYPE_EXCEPTION},
+	{"unsupported_ppp_protocol"     , NSS_STATS_TYPE_EXCEPTION},
+	{"disabled_bridge_packet"       , NSS_STATS_TYPE_EXCEPTION}
+};
+
+/*
+ * nss_pppoe_isession_stats_strings_read()
+ *	Read PPPoE session statistics names.
+ */
+static ssize_t nss_pppoe_session_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_pppoe_strings_session_stats, NSS_PPPOE_STATS_SESSION_MAX);
+}
+
+/*
+ * nss_pppoe_base_stats_strings_read()
+ *      Read PPPoE base statistics names.
+ */
+static ssize_t nss_pppoe_base_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_pppoe_strings_base_stats, NSS_PPPOE_STATS_BASE_MAX);
+}
+
+/*
+ * nss_pppoe_session_stats_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(pppoe_session_stats);
+
+/*
+ * nss_pppoe_base_stats_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(pppoe_base_stats);
+
+/*
+ * nss_pppoe_strings_dentry_create()
+ *	Create PPPoE statistics strings debug entry.
+ */
+void nss_pppoe_strings_dentry_create(void)
+{
+	struct dentry *pppoe_d = NULL;
+	struct dentry *pppoe_session_stats_d = NULL;
+	struct dentry *pppoe_base_stats_d = NULL;
+
+	if (!nss_top_main.strings_dentry) {
+		nss_warning("qca-nss-drv/strings is not present");
+		return;
+	}
+
+	pppoe_d = debugfs_create_dir("pppoe", nss_top_main.strings_dentry);
+	if (!pppoe_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/pppoe directory");
+		return;
+	}
+
+	pppoe_session_stats_d = debugfs_create_file("session_stats_str", 0400, pppoe_d, &nss_top_main, &nss_pppoe_session_stats_strings_ops);
+	if (!pppoe_session_stats_d) {
+		nss_warning("Failed to create qca-nss-drv/stats/pppoe/session_stats_str file");
+		debugfs_remove_recursive(pppoe_d);
+		return;
+	}
+
+	pppoe_base_stats_d = debugfs_create_file("base_stats_str", 0400, pppoe_d, &nss_top_main, &nss_pppoe_base_stats_strings_ops);
+	if (!pppoe_base_stats_d) {
+		nss_warning("Failed to create qca-nss-drv/stats/pppoe/base_stats_str file");
+		debugfs_remove_recursive(pppoe_d);
+		return;
+	}
+}
diff --git a/qca-nss-drv/nss_pppoe_strings.h b/qca-nss-drv/nss_pppoe_strings.h
new file mode 100644
index 0000000..8cf9393
--- /dev/null
+++ b/qca-nss-drv/nss_pppoe_strings.h
@@ -0,0 +1,26 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_PPPOE_STRINGS_H
+#define __NSS_PPPOE_STRINGS_H
+
+extern struct nss_stats_info nss_pppoe_strings_session_stats[NSS_PPPOE_STATS_SESSION_MAX];
+extern struct nss_stats_info nss_pppoe_strings_base_stats[NSS_PPPOE_STATS_BASE_MAX];
+extern void nss_pppoe_strings_dentry_create(void);
+
+#endif /* __NSS_PPPOE_STRINGS_H */
diff --git a/qca-nss-drv/nss_pptp.c b/qca-nss-drv/nss_pptp.c
new file mode 100644
index 0000000..73cf434
--- /dev/null
+++ b/qca-nss-drv/nss_pptp.c
@@ -0,0 +1,472 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <net/sock.h>
+#include "nss_tx_rx_common.h"
+#include "nss_pptp_stats.h"
+#include "nss_pptp_log.h"
+#include "nss_pptp_strings.h"
+
+#define NSS_PPTP_TX_TIMEOUT 3000 /* 3 Seconds */
+
+/*
+ * Data structures to store pptp nss debug stats
+ */
+static DEFINE_SPINLOCK(nss_pptp_session_debug_stats_lock);
+static struct nss_pptp_stats_session_debug nss_pptp_session_debug_stats[NSS_MAX_PPTP_DYNAMIC_INTERFACES];
+
+/*
+ * Private data structure
+ */
+static struct nss_pptp_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+	void *cb;
+	void *app_data;
+} pptp_pvt;
+
+/*
+ * nss_pptp_session_debug_stats_sync
+ *	Per session debug stats for pptp
+ */
+void nss_pptp_session_debug_stats_sync(struct nss_ctx_instance *nss_ctx,
+				struct nss_pptp_sync_session_stats_msg *stats_msg, uint16_t if_num)
+{
+	int i, j, if_type;
+
+	if_type = nss_dynamic_interface_get_type(nss_pptp_get_context(), if_num);
+	spin_lock_bh(&nss_pptp_session_debug_stats_lock);
+	for (i = 0; i < NSS_MAX_PPTP_DYNAMIC_INTERFACES; i++) {
+		if (nss_pptp_session_debug_stats[i].if_num == if_num) {
+			break;
+		}
+	}
+
+	if (i == NSS_MAX_PPTP_DYNAMIC_INTERFACES) {
+		spin_unlock_bh(&nss_pptp_session_debug_stats_lock);
+		return;
+	}
+
+	if (if_type == NSS_DYNAMIC_INTERFACE_TYPE_PPTP_OUTER) {
+		nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_DECAP_RX_PACKETS] +=
+			stats_msg->node_stats.rx_packets;
+		nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_DECAP_RX_BYTES] +=
+			stats_msg->node_stats.rx_bytes;
+		nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_DECAP_TX_PACKETS] +=
+			stats_msg->node_stats.tx_packets;
+		nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_DECAP_TX_BYTES] +=
+			stats_msg->node_stats.tx_bytes;
+		for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+			nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_DECAP_RX_QUEUE_0_DROP + j] +=
+				stats_msg->node_stats.rx_dropped[j];
+		}
+	} else {
+		nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_ENCAP_RX_PACKETS] +=
+			stats_msg->node_stats.rx_packets;
+		nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_ENCAP_RX_BYTES] +=
+			stats_msg->node_stats.rx_bytes;
+		nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_ENCAP_TX_PACKETS] +=
+			stats_msg->node_stats.tx_packets;
+		nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_ENCAP_TX_BYTES] +=
+			stats_msg->node_stats.tx_bytes;
+		for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+			nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_ENCAP_RX_QUEUE_0_DROP + j] +=
+				stats_msg->node_stats.rx_dropped[j];
+		}
+	}
+
+	nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_SESSION_ENCAP_HEADROOM_ERR] +=
+		stats_msg->exception_events[PPTP_EXCEPTION_EVENT_ENCAP_HEADROOM_ERR];
+	nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_SESSION_ENCAP_SMALL_SIZE] +=
+		stats_msg->exception_events[PPTP_EXCEPTION_EVENT_ENCAP_SMALL_SIZE];
+	nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_SESSION_ENCAP_PNODE_ENQUEUE_FAIL] +=
+		stats_msg->exception_events[PPTP_EXCEPTION_EVENT_ENCAP_PNODE_ENQUEUE_FAIL];
+	nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_SESSION_DECAP_NO_SEQ_NOR_ACK] +=
+		stats_msg->exception_events[PPTP_EXCEPTION_EVENT_DECAP_NO_SEQ_NOR_ACK];
+	nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_SESSION_DECAP_INVAL_GRE_FLAGS] +=
+		stats_msg->exception_events[PPTP_EXCEPTION_EVENT_DECAP_INVAL_GRE_FLAGS];
+	nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_SESSION_DECAP_INVAL_GRE_PROTO] +=
+		stats_msg->exception_events[PPTP_EXCEPTION_EVENT_DECAP_INVAL_GRE_PROTO];
+	nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_SESSION_DECAP_WRONG_SEQ] +=
+		stats_msg->exception_events[PPTP_EXCEPTION_EVENT_DECAP_WRONG_SEQ];
+	nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_SESSION_DECAP_INVAL_PPP_HDR] +=
+		stats_msg->exception_events[PPTP_EXCEPTION_EVENT_DECAP_INVAL_PPP_HDR];
+	nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_SESSION_DECAP_PPP_LCP] +=
+		stats_msg->exception_events[PPTP_EXCEPTION_EVENT_DECAP_PPP_LCP];
+	nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_SESSION_DECAP_UNSUPPORTED_PPP_PROTO] +=
+		stats_msg->exception_events[PPTP_EXCEPTION_EVENT_DECAP_UNSUPPORTED_PPP_PROTO];
+	nss_pptp_session_debug_stats[i].stats[NSS_PPTP_STATS_SESSION_DECAP_PNODE_ENQUEUE_FAIL] +=
+		stats_msg->exception_events[PPTP_EXCEPTION_EVENT_DECAP_PNODE_ENQUEUE_FAIL];
+
+	spin_unlock_bh(&nss_pptp_session_debug_stats_lock);
+}
+
+/*
+ * nss_pptp_global_session_stats_get()
+ *	Get session pptp statitics.
+ */
+void nss_pptp_session_debug_stats_get(void *stats_mem)
+{
+	struct nss_pptp_stats_session_debug *stats = (struct nss_pptp_stats_session_debug *)stats_mem;
+	int i;
+
+	if (!stats) {
+		nss_warning("No memory to copy pptp session stats");
+		return;
+	}
+
+	spin_lock_bh(&nss_pptp_session_debug_stats_lock);
+	for (i = 0; i < NSS_MAX_PPTP_DYNAMIC_INTERFACES; i++) {
+		if (nss_pptp_session_debug_stats[i].valid) {
+			memcpy(stats, &nss_pptp_session_debug_stats[i], sizeof(struct nss_pptp_stats_session_debug));
+			stats++;
+		}
+	}
+	spin_unlock_bh(&nss_pptp_session_debug_stats_lock);
+}
+
+/*
+ * nss_pptp_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static bool nss_pptp_verify_if_num(uint32_t if_num)
+{
+	uint32_t if_type;
+
+	if (nss_is_dynamic_interface(if_num) == false) {
+		return false;
+	}
+
+	if_type = nss_dynamic_interface_get_type(nss_pptp_get_context(), if_num);
+	switch(if_type) {
+	case NSS_DYNAMIC_INTERFACE_TYPE_PPTP_INNER:
+	case NSS_DYNAMIC_INTERFACE_TYPE_PPTP_OUTER:
+	case NSS_DYNAMIC_INTERFACE_TYPE_PPTP_HOST_INNER:
+		return true;
+	}
+
+	return false;
+}
+
+/*
+ * nss_pptp_handler()
+ *	Handle NSS -> HLOS messages for pptp tunnel
+ */
+static void nss_pptp_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_pptp_msg *ntm = (struct nss_pptp_msg *)ncm;
+	void *ctx;
+
+	nss_pptp_msg_callback_t cb;
+
+	BUG_ON(!nss_pptp_verify_if_num(ncm->interface));
+
+	/*
+	 * Trace Messages
+	 */
+	nss_pptp_log_rx_msg(ntm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_PPTP_MSG_MAX) {
+		nss_warning("%px: received invalid message %d for PPTP interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_pptp_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	switch (ntm->cm.type) {
+
+	case NSS_PPTP_MSG_SYNC_STATS:
+		/*
+		 * Update session debug stats in stats msg and send statistics notifications to the registered modules.
+		 */
+		nss_pptp_session_debug_stats_sync(nss_ctx, &ntm->msg.stats, ncm->interface);
+		nss_pptp_stats_notify(nss_ctx, ncm->interface);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, pptp sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->pptp_msg_callback;
+		ncm->app_data =  (nss_ptr_t)nss_ctx->subsys_dp_register[ncm->interface].app_data;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_pptp_msg_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	/*
+	 * call pptp tunnel callback
+	 */
+	if (!cb) {
+		nss_warning("%px: Event received for pptp tunnel interface %d before registration", nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb(ctx, ntm);
+}
+
+/*
+ * nss_pptp_tx_msg()
+ *	Transmit a pptp message to NSS firmware
+ */
+static nss_tx_status_t nss_pptp_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_pptp_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_pptp_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!nss_is_dynamic_interface(ncm->interface)) {
+		nss_warning("%px: tx request for non dynamic interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_PPTP_MSG_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ * nss_pptp_sync_msg_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_pptp_sync_msg_callback(void *app_data, struct nss_pptp_msg *nim)
+{
+	nss_pptp_msg_callback_t callback = (nss_pptp_msg_callback_t)pptp_pvt.cb;
+	void *data = pptp_pvt.app_data;
+
+	pptp_pvt.cb = NULL;
+	pptp_pvt.app_data = NULL;
+
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("pptp Error response %d\n", nim->cm.response);
+
+		pptp_pvt.response = NSS_TX_FAILURE;
+		if (callback) {
+			callback(data, nim);
+		}
+
+		complete(&pptp_pvt.complete);
+		return;
+	}
+
+	pptp_pvt.response = NSS_TX_SUCCESS;
+	if (callback) {
+		callback(data, nim);
+	}
+
+	complete(&pptp_pvt.complete);
+}
+
+/*
+ * nss_pptp_tx_msg()
+ *	Transmit a pptp message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_pptp_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_pptp_msg *msg)
+{
+
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&pptp_pvt.sem);
+	pptp_pvt.cb = (void *)msg->cm.cb;
+	pptp_pvt.app_data = (void *)msg->cm.app_data;
+
+	msg->cm.cb = (nss_ptr_t)nss_pptp_sync_msg_callback;
+	msg->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_pptp_tx_msg(nss_ctx, msg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: pptp_tx_msg failed\n", nss_ctx);
+		up(&pptp_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&pptp_pvt.complete, msecs_to_jiffies(NSS_PPTP_TX_TIMEOUT));
+
+	if (!ret) {
+		nss_warning("%px: PPTP msg tx failed due to timeout\n", nss_ctx);
+		pptp_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = pptp_pvt.response;
+	up(&pptp_pvt.sem);
+	return status;
+}
+
+/*
+ * nss_pptp_tx_buf()
+ *	Send packet to pptp interface owned by NSS
+ */
+nss_tx_status_t nss_pptp_tx_buf(struct nss_ctx_instance *nss_ctx, uint32_t if_num, struct sk_buff *skb)
+{
+	nss_trace("%px: pptp If Tx packet, id:%d, data=%px", nss_ctx, if_num, skb->data);
+
+	return nss_core_send_packet(nss_ctx, skb, if_num, H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+
+/*
+ * nss_register_pptp_if()
+ */
+struct nss_ctx_instance *nss_register_pptp_if(uint32_t if_num,
+					uint32_t type,
+					nss_pptp_callback_t pptp_data_callback,
+					nss_pptp_msg_callback_t notification_callback,
+					struct net_device *netdev,
+					uint32_t features,
+					void *app_ctx)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.pptp_handler_id];
+	int i = 0;
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_pptp_verify_if_num(if_num));
+
+	nss_ctx->subsys_dp_register[if_num].type = type;
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, pptp_data_callback, NULL, app_ctx, netdev, features);
+
+	nss_top_main.pptp_msg_callback = notification_callback;
+
+	nss_core_register_handler(nss_ctx, if_num, nss_pptp_handler, NULL);
+
+	spin_lock_bh(&nss_pptp_session_debug_stats_lock);
+	for (i = 0; i < NSS_MAX_PPTP_DYNAMIC_INTERFACES; i++) {
+		if (!nss_pptp_session_debug_stats[i].valid) {
+			nss_pptp_session_debug_stats[i].valid = true;
+			nss_pptp_session_debug_stats[i].if_num = if_num;
+			nss_pptp_session_debug_stats[i].if_index = netdev->ifindex;
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_pptp_session_debug_stats_lock);
+
+	return nss_ctx;
+}
+
+/*
+ * nss_unregister_pptp_if()
+ */
+void nss_unregister_pptp_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.pptp_handler_id];
+	int i;
+	int j;
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_is_dynamic_interface(if_num));
+
+	spin_lock_bh(&nss_pptp_session_debug_stats_lock);
+	for (i = 0; i < NSS_MAX_PPTP_DYNAMIC_INTERFACES; i++) {
+		if (nss_pptp_session_debug_stats[i].valid == true &&
+			nss_pptp_session_debug_stats[i].if_num == if_num) {
+			nss_pptp_session_debug_stats[i].valid = false;
+			nss_pptp_session_debug_stats[i].if_num = 0;
+			nss_pptp_session_debug_stats[i].if_index = 0;
+			for (j = 0; j < NSS_PPTP_STATS_SESSION_MAX; j++)
+				nss_pptp_session_debug_stats[i].stats[j] = 0;
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_pptp_session_debug_stats_lock);
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	nss_top_main.pptp_msg_callback = NULL;
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+}
+
+/*
+ * nss_get_pptp_context()
+ */
+struct nss_ctx_instance *nss_pptp_get_context()
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.pptp_handler_id];
+}
+
+/*
+ * nss_pptp_msg_init()
+ *      Initialize nss_pptp msg.
+ */
+void nss_pptp_msg_init(struct nss_pptp_msg *ncm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+
+/* nss_pptp_register_handler()
+ *   debugfs stats msg handler received on static pptp interface
+ */
+void nss_pptp_register_handler(void)
+{
+	int i;
+
+	nss_info("nss_pptp_register_handler");
+	nss_core_register_handler(nss_pptp_get_context(), NSS_PPTP_INTERFACE, nss_pptp_handler, NULL);
+
+	spin_lock_bh(&nss_pptp_session_debug_stats_lock);
+	for (i = 0; i < NSS_MAX_PPTP_DYNAMIC_INTERFACES; i++) {
+		nss_pptp_session_debug_stats[i].valid = false;
+		nss_pptp_session_debug_stats[i].if_num = 0;
+		nss_pptp_session_debug_stats[i].if_index = 0;
+	}
+	spin_unlock_bh(&nss_pptp_session_debug_stats_lock);
+
+	sema_init(&pptp_pvt.sem, 1);
+	init_completion(&pptp_pvt.complete);
+
+	nss_pptp_stats_dentry_create();
+	nss_pptp_strings_dentry_create();
+}
+
+EXPORT_SYMBOL(nss_pptp_get_context);
+EXPORT_SYMBOL(nss_pptp_tx_msg_sync);
+EXPORT_SYMBOL(nss_pptp_tx_buf);
+EXPORT_SYMBOL(nss_unregister_pptp_if);
+EXPORT_SYMBOL(nss_pptp_msg_init);
+EXPORT_SYMBOL(nss_register_pptp_if);
diff --git a/qca-nss-drv/nss_pptp_log.c b/qca-nss-drv/nss_pptp_log.c
new file mode 100644
index 0000000..136a3c8
--- /dev/null
+++ b/qca-nss-drv/nss_pptp_log.c
@@ -0,0 +1,129 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_pptp_log.c
+ *	NSS PPTP logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_pptp_log_message_types_str
+ *	NSS PPTP message strings
+ */
+static int8_t *nss_pptp_log_message_types_str[NSS_PPTP_MSG_MAX] __maybe_unused = {
+	"PPTP Session Configure",
+	"PPTP Session Deconfigure",
+	"PPTP Stats",
+};
+
+/*
+ * nss_pptp_log_configure_msg()
+ *	Log NSS PPTP Session Configure.
+ */
+static void nss_pptp_log_configure_msg(struct nss_pptp_msg *npm)
+{
+	struct nss_pptp_session_configure_msg *npcm __maybe_unused = &npm->msg.session_configure_msg;
+	nss_trace("%px: NSS PPTP Session Configure message\n"
+		"PPTP Source Call ID: %x\n"
+		"PPTP Destination Call ID: %x\n"
+		"PPTP Source IP: %pI4\n"
+		"PPTP Destination IP: %pI4\n",
+		npcm, npcm->src_call_id,
+		npcm->dst_call_id, &npcm->sip,
+		&npcm->dip);
+}
+
+/*
+ * nss_pptp_log_deconfigure_msg()
+ *	Log NSS PPTP Session Deconfigure.
+ */
+static void nss_pptp_log_deconfigure_msg(struct nss_pptp_msg *npm)
+{
+	struct nss_pptp_session_deconfigure_msg *npdm __maybe_unused = &npm->msg.session_deconfigure_msg;
+	nss_trace("%px: NSS PPTP Session Configure message \n"
+		"PPTP Source Call ID: %x\n",
+		npdm, npdm->src_call_id);
+}
+
+/*
+ * nss_pptp_log_verbose()
+ *	Log message contents.
+ */
+static void nss_pptp_log_verbose(struct nss_pptp_msg *npm)
+{
+	switch (npm->cm.type) {
+	case NSS_PPTP_MSG_SESSION_CONFIGURE:
+		nss_pptp_log_configure_msg(npm);
+		break;
+
+	case NSS_PPTP_MSG_SESSION_DECONFIGURE:
+		nss_pptp_log_deconfigure_msg(npm);
+		break;
+
+	case NSS_PPTP_MSG_SYNC_STATS:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", npm);
+		break;
+	}
+}
+
+/*
+ * nss_pptp_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_pptp_log_tx_msg(struct nss_pptp_msg *npm)
+{
+	if (npm->cm.type >= NSS_PPTP_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", npm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", npm, npm->cm.type, nss_pptp_log_message_types_str[npm->cm.type]);
+	nss_pptp_log_verbose(npm);
+}
+
+/*
+ * nss_pptp_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_pptp_log_rx_msg(struct nss_pptp_msg *npm)
+{
+	if (npm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", npm);
+		return;
+	}
+
+	if (npm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (npm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", npm, npm->cm.type,
+			nss_pptp_log_message_types_str[npm->cm.type],
+			npm->cm.response, nss_cmn_response_str[npm->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		npm, npm->cm.type, nss_pptp_log_message_types_str[npm->cm.type],
+		npm->cm.response, nss_cmn_response_str[npm->cm.response]);
+
+verbose:
+	nss_pptp_log_verbose(npm);
+}
diff --git a/qca-nss-drv/nss_pptp_log.h b/qca-nss-drv/nss_pptp_log.h
new file mode 100644
index 0000000..bb800d5
--- /dev/null
+++ b/qca-nss-drv/nss_pptp_log.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_PPTP_LOG_H
+#define __NSS_PPTP_LOG_H
+
+/*
+ * nss_pptp.h
+ *	NSS PPTP header file.
+ */
+
+/*
+ * Logger APIs
+ */
+
+/*
+ * nss_pptp_log_tx_msg
+ *	Logs a pptp message that is sent to the NSS firmware.
+ */
+void nss_pptp_log_tx_msg(struct nss_pptp_msg *ntm);
+
+/*
+ * nss_pptp_log_rx_msg
+ *	Logs a pptp message that is received from the NSS firmware.
+ */
+void nss_pptp_log_rx_msg(struct nss_pptp_msg *ntm);
+
+#endif /* __NSS_PPTP_LOG_H */
diff --git a/qca-nss-drv/nss_pptp_stats.c b/qca-nss-drv/nss_pptp_stats.c
new file mode 100644
index 0000000..afbe00e
--- /dev/null
+++ b/qca-nss-drv/nss_pptp_stats.c
@@ -0,0 +1,154 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_pptp_stats.h"
+#include "nss_pptp_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_pptp_stats_notifier);
+
+struct nss_pptp_stats_session_debug pptp_session_stats[NSS_MAX_PPTP_DYNAMIC_INTERFACES];
+
+/*
+ * nss_pptp_stats_read()
+ *	Read pptp statistics
+ */
+static ssize_t nss_pptp_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+
+	uint32_t max_output_lines = 2 /* header & footer for session stats */
+					+ NSS_MAX_PPTP_DYNAMIC_INTERFACES * (NSS_PPTP_STATS_SESSION_MAX + 2) /*session stats */
+					+ 2;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines ;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	struct net_device *dev;
+	int id, i;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	memset(&pptp_session_stats, 0, sizeof(struct nss_pptp_stats_session_debug) * NSS_MAX_PPTP_DYNAMIC_INTERFACES);
+
+	/*
+	 * Get all stats
+	 */
+	nss_pptp_session_debug_stats_get((void *)&pptp_session_stats);
+
+	/*
+	 * Session stats
+	 */
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\npptp session stats start:\n\n");
+	for (id = 0; id < NSS_MAX_PPTP_DYNAMIC_INTERFACES; id++) {
+
+			if (!pptp_session_stats[id].valid) {
+				break;
+			}
+
+			dev = dev_get_by_index(&init_net, pptp_session_stats[id].if_index);
+			if (likely(dev)) {
+
+				size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%d. nss interface id=%d, netdevice=%s\n", id,
+						pptp_session_stats[id].if_num, dev->name);
+				dev_put(dev);
+			} else {
+				size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "%d. nss interface id=%d\n", id,
+						pptp_session_stats[id].if_num);
+			}
+
+			for (i = 0; i < NSS_PPTP_STATS_SESSION_MAX; i++) {
+				size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+						     "\t%s = %llu\n", nss_pptp_strings_session_debug_stats[i].stats_name,
+						      pptp_session_stats[id].stats[i]);
+			}
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+	}
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\npptp session stats end\n");
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_pptp_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(pptp);
+
+/*
+ * nss_pptp_stats_dentry_create()
+ *	Create PPTP node statistics debug entry.
+ */
+void nss_pptp_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("pptp", &nss_pptp_stats_ops);
+}
+
+/*
+ * nss_pptp_stats_notify()
+ *	Sends notifications to the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_pptp_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_pptp_stats_notification pptp_stats;
+	int id;
+
+	memset(&pptp_session_stats, 0, sizeof(pptp_session_stats));
+
+	/*
+	 * Get all stats
+	 */
+	nss_pptp_session_debug_stats_get((void *)&pptp_session_stats);
+
+	for (id = 0; id < NSS_MAX_PPTP_DYNAMIC_INTERFACES; id++) {
+		if (pptp_session_stats[id].if_num == if_num) {
+			memcpy(&pptp_stats.stats, &pptp_session_stats[id].stats, sizeof(pptp_stats.stats));
+		}
+	}
+	pptp_stats.if_type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+	pptp_stats.core_id = nss_ctx->id;
+	pptp_stats.if_num = if_num;
+	atomic_notifier_call_chain(&nss_pptp_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&pptp_stats);
+}
+
+/*
+ * nss_pptp_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_pptp_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_pptp_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_pptp_stats_register_notifier);
+
+/*
+ * nss_pptp_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_pptp_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_pptp_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_pptp_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_pptp_stats.h b/qca-nss-drv/nss_pptp_stats.h
new file mode 100644
index 0000000..11c0166
--- /dev/null
+++ b/qca-nss-drv/nss_pptp_stats.h
@@ -0,0 +1,36 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2016-2017,2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_PPTP_STATS_H
+#define __NSS_PPTP_STATS_H
+
+/*
+ * NSS PPTP node statistics session
+ */
+struct nss_pptp_stats_session_debug {
+	uint64_t stats[NSS_PPTP_STATS_SESSION_MAX];
+	int32_t if_index;
+	uint32_t if_num; /* nss interface number */
+	bool valid;
+};
+
+/*
+ * NSS PPTP statistics APIs
+ */
+extern void nss_pptp_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_pptp_stats_dentry_create(void);
+
+#endif /* __NSS_PPTP_STATS_H */
diff --git a/qca-nss-drv/nss_pptp_strings.c b/qca-nss-drv/nss_pptp_strings.c
new file mode 100644
index 0000000..966ec07
--- /dev/null
+++ b/qca-nss-drv/nss_pptp_strings.c
@@ -0,0 +1,79 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include <nss_pptp.h>
+#include "nss_strings.h"
+
+/*
+ * nss_pptp_strings_session_debug_stats
+ *	PPTP statistics strings for NSS session statistics.
+ */
+struct nss_stats_info nss_pptp_strings_session_debug_stats[NSS_PPTP_STATS_SESSION_MAX] = {
+	{"ENCAP_RX_PACKETS",		NSS_STATS_TYPE_COMMON},
+	{"ENCAP_RX_BYTES",		NSS_STATS_TYPE_COMMON},
+	{"ENCAP_TX_PACKETS",		NSS_STATS_TYPE_COMMON},
+	{"ENCAP_TX_BYTES",		NSS_STATS_TYPE_COMMON},
+	{"ENCAP_RX_QUEUE_0_DROP",	NSS_STATS_TYPE_DROP},
+	{"ENCAP_RX_QUEUE_1_DROP",	NSS_STATS_TYPE_DROP},
+	{"ENCAP_RX_QUEUE_2_DROP",	NSS_STATS_TYPE_DROP},
+	{"ENCAP_RX_QUEUE_3_DROP",	NSS_STATS_TYPE_DROP},
+	{"DECAP_RX_PACKETS",		NSS_STATS_TYPE_COMMON},
+	{"DECAP_RX_BYTES",		NSS_STATS_TYPE_COMMON},
+	{"DECAP_TX_PACKETS",		NSS_STATS_TYPE_COMMON},
+	{"DECAP_TX_BYTES",		NSS_STATS_TYPE_COMMON},
+	{"DECAP_RX_QUEUE_0_DROP",	NSS_STATS_TYPE_DROP},
+	{"DECAP_RX_QUEUE_1_DROP",	NSS_STATS_TYPE_DROP},
+	{"DECAP_RX_QUEUE_2_DROP",	NSS_STATS_TYPE_DROP},
+	{"DECAP_RX_QUEUE_3_DROP",	NSS_STATS_TYPE_DROP},
+	{"ENCAP_HEADROOM_ERR",		NSS_STATS_TYPE_ERROR},
+	{"ENCAP_SMALL_SIZE",		NSS_STATS_TYPE_SPECIAL},
+	{"ENCAP_PNODE_ENQUEUE_FAIL",	NSS_STATS_TYPE_ERROR},
+	{"DECAP_NO_SEQ_NOR_ACK",	NSS_STATS_TYPE_ERROR},
+	{"DECAP_INVAL_GRE_FLAGS",	NSS_STATS_TYPE_ERROR},
+	{"DECAP_INVAL_GRE_PROTO",	NSS_STATS_TYPE_ERROR},
+	{"DECAP_WRONG_SEQ",		NSS_STATS_TYPE_ERROR},
+	{"DECAP_INVAL_PPP_HDR",		NSS_STATS_TYPE_ERROR},
+	{"DECAP_PPP_LCP",		NSS_STATS_TYPE_SPECIAL},
+	{"DECAP_UNSUPPORTED_PPP_PROTO",	NSS_STATS_TYPE_ERROR},
+	{"DECAP_PNODE_ENQUEUE_FAIL",	NSS_STATS_TYPE_ERROR}
+};
+
+/*
+ * nss_pptp_strings_read()
+ *	Read PPTP node statistics names.
+ */
+static ssize_t nss_pptp_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_pptp_strings_session_debug_stats, NSS_PPTP_STATS_SESSION_MAX);
+}
+
+/*
+ * nss_pptp_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(pptp);
+
+/*
+ * nss_pptp_strings_dentry_create()
+ *	Create PPTP statistics strings debug entry.
+ */
+void nss_pptp_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("pptp", &nss_pptp_strings_ops);
+}
diff --git a/qca-nss-drv/nss_pptp_strings.h b/qca-nss-drv/nss_pptp_strings.h
new file mode 100644
index 0000000..788a387
--- /dev/null
+++ b/qca-nss-drv/nss_pptp_strings.h
@@ -0,0 +1,25 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_PPTP_STRINGS_H
+#define __NSS_PPTP_STRINGS_H
+
+extern struct nss_stats_info nss_pptp_strings_session_debug_stats[NSS_PPTP_STATS_SESSION_MAX];
+extern void nss_pptp_strings_dentry_create(void);
+
+#endif /* __NSS_PPTP_STRINGS_H */
diff --git a/qca-nss-drv/nss_profiler.c b/qca-nss-drv/nss_profiler.c
new file mode 100755
index 0000000..5717ac3
--- /dev/null
+++ b/qca-nss-drv/nss_profiler.c
@@ -0,0 +1,254 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_profiler.c
+ *	NSS profiler APIs
+ */
+
+#include "nss_tx_rx_common.h"
+
+/*
+ * nss_profiler_rx_msg_handler()
+ *	Handle profiler information.
+ */
+static void nss_profiler_rx_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, void *app)
+{
+	struct nss_profiler_msg *pm = (struct nss_profiler_msg*)ncm;
+	void *ctx = nss_ctx->nss_top->profiler_ctx[nss_ctx->id];
+	nss_profiler_callback_t cb = nss_ctx->nss_top->profiler_callback[nss_ctx->id];
+
+	if (ncm->type >= NSS_PROFILER_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (ncm->type <= NSS_PROFILER_FLOWCTRL_MSG) {
+		if (ncm->len > sizeof(pm->payload.pcmdp)) {
+			nss_warning("%px: reply for cmd %d size is wrong %d : %d\n", nss_ctx, ncm->type, ncm->len, ncm->interface);
+			return;
+		}
+	} else if (ncm->type <= NSS_PROFILER_DEBUG_REPLY_MSG) {
+		if (ncm->len > sizeof(pm->payload.pdm)) {
+			nss_warning("%px: reply for debug %d is too big %d\n", nss_ctx, ncm->type, ncm->len);
+			return;
+		}
+	} else if (ncm->type <= NSS_PROFILER_COUNTERS_MSG) {
+		if (ncm->len < (sizeof(pm->payload.pcmdp) - (PROFILE_MAX_APP_COUNTERS - pm->payload.pcmdp.num_counters) * sizeof(pm->payload.pcmdp.counters[0])) || ncm->len > sizeof(pm->payload.pcmdp)) {
+			nss_warning("%px: %d params data is too big %d : %d\n", nss_ctx, ncm->type, ncm->len, ncm->interface);
+			return;
+		}
+	}
+
+	/*
+	 * status per request callback
+	 */
+	if (ncm->response != NSS_CMN_RESPONSE_NOTIFY && ncm->cb) {
+		nss_info("%px: reply CB %px for %d %d\n", nss_ctx, (void *)ncm->cb, ncm->type, ncm->response);
+		cb = (nss_profiler_callback_t)ncm->cb;
+	}
+
+	/*
+	 * sample related callback
+	 */
+	if (!cb || !ctx) {
+		nss_warning("%px: Event received for profiler interface before registration", nss_ctx);
+		return;
+	}
+
+	cb(ctx, (struct nss_profiler_msg *)ncm);
+}
+
+/*
+ * nss_tx_profiler_if_buf()
+ *	NSS profiler Tx API
+ */
+nss_tx_status_t nss_profiler_if_tx_buf(void *ctx, void *buf, uint32_t len,
+					void *cb, void *app_data)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)ctx;
+	struct nss_profiler_msg *npm;
+	struct nss_profiler_data_msg *pdm = (struct nss_profiler_data_msg *)buf;
+	nss_tx_status_t ret;
+
+	nss_trace("%px: Profiler If Tx, buf=%px", nss_ctx, buf);
+
+	if (sizeof(npm->payload) < len) {
+		nss_warning("%px: (%u)Bad message length(%u)", nss_ctx, NSS_PROFILER_INTERFACE, len);
+		return NSS_TX_FAILURE_TOO_LARGE;
+	}
+
+	if (NSS_NBUF_PAYLOAD_SIZE < (len + sizeof(npm->cm))) {
+		nss_warning("%px: (%u)Message length(%u) is larger than payload size (%u)",
+			nss_ctx, NSS_PROFILER_INTERFACE, (uint32_t)(len + sizeof(npm->cm)), NSS_NBUF_PAYLOAD_SIZE);
+		return NSS_TX_FAILURE_TOO_LARGE;
+	}
+
+	npm = kzalloc(sizeof(*npm), GFP_KERNEL);
+	if (!npm) {
+		nss_warning("%px: Failed to allocate memory for message\n", nss_ctx);
+		return NSS_TX_FAILURE;
+	}
+
+	memcpy(&npm->payload, pdm, len);
+	nss_profiler_msg_init(npm, NSS_PROFILER_INTERFACE, pdm->hd_magic & 0xFF, len,
+				cb, app_data);
+
+	ret = nss_core_send_cmd(nss_ctx, npm, sizeof(npm->cm) + len, NSS_NBUF_PAYLOAD_SIZE);
+	kfree(npm);
+	return ret;
+}
+EXPORT_SYMBOL(nss_profiler_if_tx_buf);
+
+/*
+ * nss_profiler_alloc_dma()
+ *	Allocate a DMA for profiler.
+ */
+void *nss_profiler_alloc_dma(struct nss_ctx_instance *nss_ctx, struct nss_profile_sdma_producer **dma_p)
+{
+	int size;
+	void *kaddr;
+	struct nss_profile_sdma_producer *dma;
+	struct nss_profile_sdma_ctrl *ctrl = (struct nss_profile_sdma_ctrl *)nss_ctx->meminfo_ctx.sdma_ctrl;
+	if (!ctrl)
+		return NULL;
+
+	dma = ctrl->producer;
+	*dma_p = dma;
+	size = dma->num_bufs * dma->buf_size;
+	kaddr = kmalloc(size, GFP_KERNEL | __GFP_ZERO);
+
+	if (kaddr) {
+		dma->desc_ring = dma_map_single(nss_ctx->dev, kaddr, size, DMA_FROM_DEVICE);
+		NSS_CORE_DSB();
+	}
+	ctrl->consumer[0].ring.kp = kaddr;
+	return kaddr;
+}
+EXPORT_SYMBOL(nss_profiler_alloc_dma);
+
+/*
+ * nss_profiler_release_dma()
+ *	Free profiler DMA.
+ */
+void nss_profiler_release_dma(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_profile_sdma_ctrl *ctrl;
+	if (!nss_ctx)
+		return;
+
+	ctrl = nss_ctx->meminfo_ctx.sdma_ctrl;
+
+	if (ctrl && ctrl->consumer[0].ring.kp) {
+		kfree(ctrl->consumer[0].ring.kp);
+		ctrl->consumer[0].ring.kp = NULL;
+	}
+}
+EXPORT_SYMBOL(nss_profiler_release_dma);
+
+/*
+ * nss_profile_dma_register_cb
+ *      Register a handler for profile DMA.
+ */
+bool nss_profile_dma_register_cb(struct nss_ctx_instance *nss_ctx, int id,
+				void (*cb)(void*), void *arg)
+{
+	struct nss_profile_sdma_ctrl *ctrl = (struct nss_profile_sdma_ctrl *)nss_ctx->meminfo_ctx.sdma_ctrl;
+	nss_info("%px dma_register_cb %d: %px %px\n", ctrl, id, cb, arg);
+	if (!ctrl)
+		return false;
+
+	ctrl->consumer[id].dispatch.fp = cb;
+	ctrl->consumer[id].arg.kp = arg;
+	return true;
+}
+EXPORT_SYMBOL(nss_profile_dma_register_cb);
+
+/*
+ * nss_profile_dma_deregister_cb
+ *      Deregister callback for profile DMA.
+ */
+bool nss_profile_dma_deregister_cb(struct nss_ctx_instance *nss_ctx, int id)
+{
+	struct nss_profile_sdma_ctrl *ctrl = (struct nss_profile_sdma_ctrl *)nss_ctx->meminfo_ctx.sdma_ctrl;
+	if (!ctrl)
+		return false;
+
+	ctrl->consumer[id].dispatch.fp = NULL;
+	return true;
+}
+EXPORT_SYMBOL(nss_profile_dma_deregister_cb);
+
+/*
+ * nss_profile_dma_get_ctrl
+ *      Wrapper to get profile DMA control.
+ */
+struct nss_profile_sdma_ctrl *nss_profile_dma_get_ctrl(struct nss_ctx_instance *nss_ctx)
+{
+	struct nss_profile_sdma_ctrl *ctrl = nss_ctx->meminfo_ctx.sdma_ctrl;
+	if (!ctrl) {
+		return ctrl;
+	}
+
+	dmac_inv_range(ctrl, &ctrl->cidx);
+	dsb(sy);
+	return ctrl;
+}
+EXPORT_SYMBOL(nss_profile_dma_get_ctrl);
+
+/*
+ * nss_profiler_notify_register()
+ */
+void *nss_profiler_notify_register(nss_core_id_t core_id, nss_profiler_callback_t profiler_callback, void *ctx)
+{
+	nss_assert(core_id < NSS_CORE_MAX);
+
+	if (NSS_CORE_STATUS_SUCCESS !=
+		nss_core_register_handler(&nss_top_main.nss[core_id], NSS_PROFILER_INTERFACE, nss_profiler_rx_msg_handler, NULL)) {
+			nss_warning("Message handler FAILED to be registered for profiler");
+			return NULL;
+	}
+
+	nss_top_main.profiler_ctx[core_id] = ctx;
+	nss_top_main.profiler_callback[core_id] = profiler_callback;
+
+	return (void *)&nss_top_main.nss[core_id];
+}
+EXPORT_SYMBOL(nss_profiler_notify_register);
+
+/*
+ * nss_profiler_notify_unregister()
+ */
+void nss_profiler_notify_unregister(nss_core_id_t core_id)
+{
+	nss_assert(core_id < NSS_CORE_MAX);
+
+	nss_core_unregister_handler(&nss_top_main.nss[core_id], NSS_PROFILER_INTERFACE);
+	nss_top_main.profiler_callback[core_id] = NULL;
+	nss_top_main.profiler_ctx[core_id] = NULL;
+}
+EXPORT_SYMBOL(nss_profiler_notify_unregister);
+
+/*
+ * nss_profiler_msg_init()
+ *	Initialize profiler message.
+ */
+void nss_profiler_msg_init(struct nss_profiler_msg *npm, uint16_t if_num, uint32_t type, uint32_t len,
+				nss_profiler_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&npm->cm, if_num, type, len, (void *)cb, app_data);
+}
+EXPORT_SYMBOL(nss_profiler_msg_init);
diff --git a/qca-nss-drv/nss_project.c b/qca-nss-drv/nss_project.c
new file mode 100644
index 0000000..07402fb
--- /dev/null
+++ b/qca-nss-drv/nss_project.c
@@ -0,0 +1,338 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * @file nss_project.h
+ *	NSS project APIs.
+ */
+#include "nss_tx_rx_common.h"
+
+static int nss_project_wt_stats_enable;
+
+/*
+ * nss_project_free_wt_stats()
+ *	Frees a number of allocated worker thread statistics.
+ */
+static void nss_project_free_wt_stats(struct nss_worker_thread_stats *wt_stats, int num_alloc)
+{
+	int i;
+
+	if (!wt_stats) {
+		return;
+	}
+
+	for (i = 0; i < num_alloc; i++) {
+		kfree(wt_stats[i].irq_stats);
+	}
+	kfree(wt_stats);
+}
+
+/*
+ * nss_project_alloc_wt_stats()
+ * 	Allocates worker thread stats for a given  number of threads and IRQs.
+ */
+static struct nss_worker_thread_stats *nss_project_alloc_wt_stats(uint32_t thread_count, uint32_t irq_count)
+{
+	struct nss_worker_thread_stats *wt_stats;
+	int i;
+
+	wt_stats = kzalloc(thread_count * sizeof(struct nss_worker_thread_stats), GFP_ATOMIC);
+	if (unlikely(!wt_stats)) {
+		return NULL;
+	}
+
+	for (i = 0; i < thread_count; i++) {
+		wt_stats[i].irq_stats =
+			kzalloc(irq_count * sizeof(struct nss_project_irq_stats), GFP_ATOMIC);
+		if (unlikely(!wt_stats[i].irq_stats)) {
+			nss_project_free_wt_stats(wt_stats, i);
+			return NULL;
+		}
+	}
+
+	return wt_stats;
+}
+
+/*
+ * nss_project_wt_stats_enable_callback()
+ *	Callback function for wt stats enable messages
+ */
+static void nss_project_wt_stats_enable_callback(void *app_data, struct nss_project_msg *msg)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)app_data;
+	struct nss_project_msg_wt_stats_enable *stats_enable = &msg->msg.wt_stats_enable;
+	struct nss_worker_thread_stats *stats_temp;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	if (msg->cm.response != NSS_CMN_RESPONSE_ACK) {
+		return;
+	}
+
+	nss_info("%px: Received response ACK for worker thread stats enable msg.\n", nss_ctx);
+
+	/*
+	 * If statistics have already been allocated, nothing else to do.
+	 */
+	if (nss_ctx->wt_stats) {
+		return;
+	}
+
+	stats_temp = nss_project_alloc_wt_stats(stats_enable->worker_thread_count,
+						stats_enable->irq_count);
+	if (unlikely(!stats_temp)) {
+		nss_warning("%px: Unable to allocate worker thread statistics.\n", nss_ctx);
+		return;
+	}
+
+	spin_lock_bh(&nss_ctx->nss_top->stats_lock);
+	nss_ctx->wt_stats = stats_temp;
+	nss_ctx->worker_thread_count = stats_enable->worker_thread_count;
+	nss_ctx->irq_count = stats_enable->irq_count;
+	spin_unlock_bh(&nss_ctx->nss_top->stats_lock);
+}
+
+/*
+ * nss_project_wt_stats_send_enable()
+ *	Sends message to firmware to enable or disable worker_thread statistics collection.
+ */
+static nss_tx_status_t nss_project_wt_stats_send_enable(struct nss_ctx_instance *nss_ctx, bool enable)
+{
+	struct nss_project_msg *npm;
+	struct nss_cmn_msg *ncm;
+	nss_tx_status_t ret;
+
+	npm = kzalloc(sizeof(*npm), GFP_KERNEL);
+	if (!npm) {
+		nss_warning("%px: Failed to allocate buffer for message\n", nss_ctx);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Populate the message
+	 */
+	ncm = &npm->cm;
+	nss_cmn_msg_init(ncm, NSS_PROJECT_INTERFACE,
+		NSS_PROJECT_MSG_WT_STATS_ENABLE,
+		sizeof(struct nss_project_msg_wt_stats_enable),
+		(void *)nss_project_wt_stats_enable_callback,
+		(void *)nss_ctx);
+	npm->msg.wt_stats_enable.enable = enable;
+
+	ret = nss_core_send_cmd(nss_ctx, npm, sizeof(*npm), NSS_NBUF_PAYLOAD_SIZE);
+	kfree(npm);
+	return ret;
+}
+
+/*
+ * nss_project_wt_stats_update()
+ *	Updates stored statistics with the data found in the notify.
+ */
+static void nss_project_wt_stats_update(struct nss_ctx_instance *nss_ctx,
+			struct nss_project_msg_wt_stats_notify *stats_notify)
+{
+	struct nss_worker_thread_stats *wt_stats;
+	int i;
+
+	if (unlikely(!nss_ctx->wt_stats)) {
+		nss_warning("%px: Worker thread statistics not yet allocated.\n", nss_ctx);
+		return;
+	}
+
+	if (unlikely(stats_notify->threadno >= nss_ctx->worker_thread_count)) {
+		nss_warning("%px: Invalid WT number %d\n", nss_ctx, stats_notify->threadno);
+		return;
+	}
+
+	if (unlikely(stats_notify->stats_written > NSS_PROJECT_IRQS_PER_MESSAGE)) {
+		nss_warning("%px: Invalid worker thread stats written count %d\n",
+				nss_ctx, stats_notify->stats_written);
+		return;
+	}
+
+	wt_stats = &(nss_ctx->wt_stats[stats_notify->threadno]);
+
+	if (unlikely(!wt_stats->irq_stats)) {
+		nss_warning("%px: Worker thread statistics not allocated for thread %d\n",
+				nss_ctx, stats_notify->threadno);
+		return;
+	}
+
+	spin_lock_bh(&nss_ctx->nss_top->stats_lock);
+	for (i = 0; i < stats_notify->stats_written; ++i) {
+		int irq = stats_notify->stats[i].irq;
+		if (unlikely(irq >= nss_ctx->irq_count)) {
+			nss_warning("%px: Invalid IRQ number %d\n", nss_ctx, irq);
+			continue;
+		}
+
+		wt_stats->irq_stats[irq] = stats_notify->stats[i];
+	}
+	spin_unlock_bh(&nss_ctx->nss_top->stats_lock);
+}
+
+/*
+ * nss_project_msg_handler()
+ *	Handles metadata messages on the project interface.
+ */
+static void nss_project_msg_handler(struct nss_ctx_instance *nss_ctx,
+	struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_project_msg *npm = (struct nss_project_msg *)ncm;
+	nss_project_msg_callback_t cb;
+
+	/*
+	 * Sanity checks on message
+	 */
+	if (npm->cm.type >= NSS_PROJECT_MSG_MAX) {
+		nss_warning("%px: message type out of range: %d\n", nss_ctx, npm->cm.type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(&(npm->cm)) > sizeof(struct nss_project_msg)) {
+		nss_warning("%px: message length is invalid: %d\n", nss_ctx, nss_cmn_get_msg_len(&(npm->cm)));
+		return;
+	}
+
+	switch (npm->cm.type) {
+	case NSS_PROJECT_MSG_WT_STATS_NOTIFY:
+		nss_project_wt_stats_update(nss_ctx, &(npm->msg.wt_stats_notify));
+		return;
+	}
+
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	if (!ncm->cb) {
+		return;
+	}
+
+	cb = (nss_project_msg_callback_t)ncm->cb;
+	cb((void *)nss_ctx, npm);
+}
+
+/*
+ * nss_project_wt_stats_handler()
+ *	Sysctl handler for wt_stats.
+ *
+ * Uses proc_dointvec to process data. For a write operation, also sends worker
+ * thread stats enable messages containing the new value to each NSS core.
+ */
+static int nss_project_wt_stats_handler(struct ctl_table *ctl, int write,
+	void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret;
+	int i;
+
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+
+	/*
+	 * In case of error, stop now.
+	 */
+	if (ret) {
+		return ret;
+	}
+
+	/*
+	 * No additional behavior necessary for a read operation.
+	 */
+	if (!write) {
+		return ret;
+	}
+
+	/*
+	 * If a value was written, send a message containing that value to each
+	 * NSS core.
+	 */
+	for (i = 0; i < nss_top_main.num_nss; ++i) {
+		nss_project_wt_stats_send_enable(&(nss_top_main.nss[i]),
+			nss_project_wt_stats_enable);
+	}
+	return ret;
+
+}
+
+/*
+ * Tree of ctl_tables used to put the wt_stats proc node in the correct place in
+ * the file system. Allows the command $ echo 1 > proc/sys/dev/nss/project/wt_stats
+ * to enable worker thread statistics (echoing 0 into the same target will disable).
+ */
+static struct ctl_table nss_project_table[] = {
+	{
+		.procname		= "wt_stats",
+		.data			= &nss_project_wt_stats_enable,
+		.maxlen			= sizeof(int),
+		.mode			= 0644,
+		.proc_handler		= &nss_project_wt_stats_handler,
+	},
+	{ }
+};
+
+static struct ctl_table nss_project_dir[] = {
+	{
+		.procname		= "project",
+		.mode			= 0555,
+		.child			= nss_project_table,
+	},
+	{ }
+};
+
+static struct ctl_table nss_project_root_dir[] = {
+	{
+		.procname		= "nss",
+		.mode			= 0555,
+		.child			= nss_project_dir,
+	},
+	{ }
+};
+
+static struct ctl_table nss_project_root[] = {
+	{
+		.procname		= "dev",
+		.mode			= 0555,
+		.child			= nss_project_root_dir,
+	},
+	{ }
+};
+
+static struct ctl_table_header *nss_project_header;
+
+/*
+ * nss_project_register_sysctl()
+ *	Registers any sysctl handlers for the project.
+ */
+void nss_project_register_sysctl(void)
+{
+	nss_project_header = register_sysctl_table(nss_project_root);
+}
+
+/*
+ * nss_project_unregister_sysctl()
+ *	De-registers any sysctl handlers for the project.
+ */
+void nss_project_unregister_sysctl(void)
+{
+	if (nss_project_header) {
+		unregister_sysctl_table(nss_project_header);
+	}
+}
+
+/*
+ * nss_project_register_handler()
+ *	Registers the handler for NSS->HLOS messages
+ */
+void nss_project_register_handler(struct nss_ctx_instance *nss_ctx)
+{
+	nss_core_register_handler(nss_ctx, NSS_PROJECT_INTERFACE, nss_project_msg_handler, NULL);
+}
diff --git a/qca-nss-drv/nss_pvxlan.c b/qca-nss-drv/nss_pvxlan.c
new file mode 100644
index 0000000..abe78ee
--- /dev/null
+++ b/qca-nss-drv/nss_pvxlan.c
@@ -0,0 +1,446 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+ /*
+  * nss_pvxlan.c
+  *	NSS PVXLAN driver interface APIs
+  */
+#include "nss_core.h"
+#include "nss_pvxlan.h"
+#include "nss_cmn.h"
+#include "nss_tx_rx_common.h"
+#include "nss_pvxlan_stats.h"
+#include "nss_pvxlan_log.h"
+
+#define NSS_PVXLAN_TX_TIMEOUT 3000
+
+/*
+ * Spinlock for protecting tunnel operations colliding with a tunnel destroy
+ */
+DEFINE_SPINLOCK(nss_pvxlan_spinlock);
+
+/*
+ * Private data structure
+ */
+static struct nss_pvxlan_pvt {
+	struct semaphore sem;		/* Semaphore structure. */
+	struct completion complete;	/* Completion structure. */
+	int response;			/* Response from FW. */
+	void *cb;			/* Original cb for msgs. */
+	void *app_data;			/* Original app_data for msgs. */
+} pvxlan_pvt;
+
+/*
+ * Per PVxLAN tunnel/interface number instance.
+ */
+struct nss_pvxlan_handle {
+	atomic_t refcnt;			/* Reference count on the tunnel */
+	uint32_t if_num;			/* Interface number */
+	uint32_t tunnel_status;			/* 0=disable, 1=enabled */
+	nss_pvxlan_msg_callback_t msg_callback;	/* Msg callback */
+	void *app_data;				/* App data (argument) */
+};
+
+/*
+ * Array of pointer for NSS PvLAN handles. Each handle has per-tunnel
+ * stats based on the if_num which is an index.
+ */
+static struct nss_pvxlan_handle *nss_pvxlan_hdl[NSS_MAX_DYNAMIC_INTERFACES];
+
+/*
+ * nss_pvxlan_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static bool nss_pvxlan_verify_if_num(uint32_t if_num)
+{
+	uint32_t type = nss_dynamic_interface_get_type(nss_pvxlan_get_ctx(), if_num);
+
+	return ((type == NSS_DYNAMIC_INTERFACE_TYPE_PVXLAN_HOST_INNER) ||
+				(type == NSS_DYNAMIC_INTERFACE_TYPE_PVXLAN_OUTER));
+}
+
+/*
+ * nss_pvxlan_hdl_instance_free()
+ *	Free PVxLAN tunnel handle instance.
+ */
+static bool nss_pvxlan_hdl_instance_free(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_pvxlan_handle *h;
+
+	spin_lock_bh(&nss_pvxlan_spinlock);
+	h = nss_pvxlan_hdl[if_num - NSS_DYNAMIC_IF_START];
+	if (!h) {
+		spin_unlock_bh(&nss_pvxlan_spinlock);
+		nss_warning("%px: Instance does not exist: %d", nss_ctx, if_num);
+		return false;
+	}
+
+	if (h->if_num != if_num) {
+		spin_unlock_bh(&nss_pvxlan_spinlock);
+		nss_warning("%px: Not correct if_num: %d", nss_ctx, if_num);
+		return false;
+	}
+
+	nss_pvxlan_hdl[if_num - NSS_DYNAMIC_IF_START] = NULL;
+	spin_unlock_bh(&nss_pvxlan_spinlock);
+	kfree(h);
+	return true;
+}
+
+/*
+ * nss_pvxlan_hdl_instance_alloc()
+ *	Allocate PVxLAN tunnel instance.
+ */
+static bool nss_pvxlan_hdl_instance_alloc(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+							nss_pvxlan_msg_callback_t notify_cb, void *app_data)
+{
+	struct nss_pvxlan_handle *h;
+
+	/*
+	 * Allocate a handle
+	 */
+	h = kzalloc(sizeof(struct nss_pvxlan_handle), GFP_ATOMIC);
+	if (!h) {
+		nss_warning("%px: no memory for allocating PVxLAN handle instance for interface : %d", nss_ctx, if_num);
+		return false;
+	}
+	h->if_num = if_num;
+
+	spin_lock_bh(&nss_pvxlan_spinlock);
+	if (nss_pvxlan_hdl[if_num - NSS_DYNAMIC_IF_START] != NULL) {
+		spin_unlock_bh(&nss_pvxlan_spinlock);
+		kfree(h);
+		nss_warning("%px: The handle has been taken by another thread :%d", nss_ctx, if_num);
+		return false;
+	}
+
+	h->msg_callback = notify_cb;
+	h->app_data = app_data;
+	nss_pvxlan_hdl[if_num - NSS_DYNAMIC_IF_START] = h;
+	spin_unlock_bh(&nss_pvxlan_spinlock);
+
+	return true;
+}
+
+/*
+ * nss_pvxlan_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_pvxlan_callback(void *app_data, struct nss_pvxlan_msg *nvxm)
+{
+	nss_pvxlan_msg_callback_t callback = (nss_pvxlan_msg_callback_t)pvxlan_pvt.cb;
+	void *data = pvxlan_pvt.app_data;
+
+	pvxlan_pvt.response = NSS_TX_SUCCESS;
+	pvxlan_pvt.cb = NULL;
+	pvxlan_pvt.app_data = NULL;
+
+	if (nvxm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("Pvxlan Error response %d\n", nvxm->cm.response);
+		pvxlan_pvt.response = nvxm->cm.response;
+	}
+
+	if (callback) {
+		callback(data, nvxm);
+	}
+	complete(&pvxlan_pvt.complete);
+}
+
+/*
+ * nss_pvxlan_handler()
+ *	Handle NSS -> HLOS messages for PVxLAN.
+ */
+static void nss_pvxlan_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_pvxlan_msg *nvxm = (struct nss_pvxlan_msg *)ncm;
+	nss_pvxlan_msg_callback_t cb;
+	struct nss_pvxlan_handle * h;
+
+	BUG_ON(!nss_pvxlan_verify_if_num(ncm->interface));
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_PVXLAN_MSG_TYPE_MAX) {
+		nss_warning("%px: received invalid message %d for PVXLAN interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_pvxlan_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+	nss_pvxlan_log_rx_msg(nvxm);
+
+	switch (nvxm->cm.type) {
+	case NSS_PVXLAN_MSG_TYPE_SYNC_STATS:
+		nss_pvxlan_stats_sync(nss_ctx, &nvxm->msg.stats, ncm->interface);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		uint32_t if_num = ncm->interface - NSS_DYNAMIC_IF_START;
+		spin_lock_bh(&nss_pvxlan_spinlock);
+		h = nss_pvxlan_hdl[if_num];
+		if (h) {
+			ncm->cb = (nss_ptr_t)h->msg_callback;
+			ncm->app_data = (nss_ptr_t)h->app_data;
+		}
+		spin_unlock_bh(&nss_pvxlan_spinlock);
+
+	}
+
+	cb = (nss_pvxlan_msg_callback_t)ncm->cb;
+
+	/*
+	 * Do we have a callback
+	 */
+	if (!cb) {
+		nss_trace("%px: cb is null for interface %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb((void *)ncm->app_data, nvxm);
+}
+
+/*
+ * nss_pvxlan_tx_msg()
+ *	Transmit a PVXLAN message to NSS FW. Don't call this from softirq/interrupts.
+ */
+nss_tx_status_t nss_pvxlan_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_pvxlan_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	if (!nss_pvxlan_verify_if_num(msg->cm.interface)) {
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	if (ncm->type >= NSS_PVXLAN_MSG_TYPE_MAX) {
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_pvxlan_log_tx_msg(msg);
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_pvxlan_tx_msg);
+
+/*
+ * nss_pvxlan_tx_msg_sync()
+ *	Transmit a pvxlan message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_pvxlan_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_pvxlan_msg *nvxm)
+{
+	nss_tx_status_t status;
+	int ret;
+
+	down(&pvxlan_pvt.sem);
+	nvxm->cm.cb = (nss_ptr_t)nss_pvxlan_callback;
+	nvxm->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_pvxlan_tx_msg(nss_ctx, nvxm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: pvxlan_tx_msg failed\n", nss_ctx);
+		up(&pvxlan_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&pvxlan_pvt.complete, msecs_to_jiffies(NSS_PVXLAN_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: pvxlan tx sync failed due to timeout\n", nss_ctx);
+		pvxlan_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = pvxlan_pvt.response;
+	up(&pvxlan_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_pvxlan_tx_msg_sync);
+
+/*
+ * nss_pvxlan_tx_buf()
+ *	Transmit data buffer (skb) to a NSS interface number
+ */
+nss_tx_status_t nss_pvxlan_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *buf, uint32_t if_num)
+{
+	BUG_ON(!nss_pvxlan_verify_if_num(if_num));
+
+	return nss_core_send_packet(nss_ctx, buf, if_num, H2N_BIT_FLAG_VIRTUAL_BUFFER | H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+EXPORT_SYMBOL(nss_pvxlan_tx_buf);
+
+/*
+ ***********************************
+ * Register/Unregister/Miscellaneous APIs
+ ***********************************
+ */
+
+/*
+ * nss_pvxlan_unregister()
+ *	Unregister a data packet notifier with NSS FW.
+ */
+bool nss_pvxlan_unregister(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx;
+	int32_t i;
+
+	nss_ctx = nss_pvxlan_get_ctx();
+	if (!nss_pvxlan_verify_if_num(if_num)) {
+		nss_warning("%px: data unregister received for invalid interface %d", nss_ctx, if_num);
+		return false;
+	}
+
+	spin_lock_bh(&nss_pvxlan_tunnel_stats_debug_lock);
+	for (i = 0; i < NSS_PVXLAN_MAX_INTERFACES; i++) {
+		if (nss_pvxlan_tunnel_debug_stats[i].if_num != if_num) {
+			continue;
+		}
+
+		memset(&nss_pvxlan_tunnel_debug_stats[i], 0,
+			sizeof(struct nss_pvxlan_tunnel_stats_debug));
+		break;
+	}
+	spin_unlock_bh(&nss_pvxlan_tunnel_stats_debug_lock);
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+	nss_pvxlan_hdl_instance_free(nss_ctx, if_num);
+	return true;
+}
+EXPORT_SYMBOL(nss_pvxlan_unregister);
+
+/*
+ * nss_pvxlan_register()
+ *	Registers a data packet notifier with NSS FW.
+ */
+struct nss_ctx_instance *nss_pvxlan_register(uint32_t if_num,
+						nss_pvxlan_buf_callback_t data_cb,
+						nss_pvxlan_msg_callback_t notify_cb,
+						struct net_device *netdev,
+						uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx;
+	int core_status;
+	int32_t i;
+
+	nss_ctx = nss_pvxlan_get_ctx();
+	if (!nss_pvxlan_verify_if_num(if_num)) {
+		nss_warning("%px: data register received for invalid interface %d", nss_ctx, if_num);
+		return NULL;
+	}
+
+	core_status = nss_core_register_handler(nss_ctx, if_num, nss_pvxlan_msg_handler, NULL);
+	if (core_status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: nss core register handler failed for if_num:%d with error :%d", nss_ctx, if_num, core_status);
+		return NULL;
+	}
+
+	if (!nss_pvxlan_hdl_instance_alloc(nss_ctx, if_num, notify_cb, (void *)netdev)) {
+		nss_core_unregister_handler(nss_ctx, if_num);
+		nss_warning("%px: couldn't allocate handle instance for if_num:%d", nss_ctx, if_num);
+		return NULL;
+	}
+
+	spin_lock_bh(&nss_pvxlan_tunnel_stats_debug_lock);
+	for (i = 0; i < NSS_PVXLAN_MAX_INTERFACES; i++) {
+		if (nss_pvxlan_tunnel_debug_stats[i].valid) {
+			continue;
+		}
+
+		nss_pvxlan_tunnel_debug_stats[i].valid = true;
+		nss_pvxlan_tunnel_debug_stats[i].if_num = if_num;
+		nss_pvxlan_tunnel_debug_stats[i].if_index = netdev->ifindex;
+		break;
+	}
+	spin_unlock_bh(&nss_pvxlan_tunnel_stats_debug_lock);
+
+	if (i == NSS_PVXLAN_MAX_INTERFACES) {
+		nss_warning("%px: No available debug stats instance :%d", nss_ctx, if_num);
+		nss_pvxlan_hdl_instance_free(nss_ctx, if_num);
+		nss_core_unregister_handler(nss_ctx, if_num);
+		return NULL;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, data_cb, NULL, NULL, netdev, features);
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_pvxlan_register);
+
+/*
+ * nss_pvxlan_ifnum_with_core_id()
+ *	Append core id to pvxlan interface num.
+ */
+int nss_pvxlan_ifnum_with_core_id(int if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_pvxlan_get_ctx();
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_is_dynamic_interface(if_num)) {
+		nss_warning("%px: Invalid if_num: %d, must be a dynamic interface\n", nss_ctx, if_num);
+		return 0;
+	}
+	return NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_pvxlan_ifnum_with_core_id);
+
+/*
+ * nss_pvxlan_msg_init()
+ *	Initialize pvxlan message.
+ */
+void nss_pvxlan_msg_init(struct nss_pvxlan_msg *ncm, uint16_t if_num, uint32_t type, uint32_t len,
+				nss_pvxlan_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, (void*)cb, app_data);
+}
+EXPORT_SYMBOL(nss_pvxlan_msg_init);
+
+/*
+ * nss_pvxlan_get_ctx()
+ *	Return a Pvxlan NSS context.
+ */
+struct nss_ctx_instance *nss_pvxlan_get_ctx()
+{
+	struct nss_ctx_instance *nss_ctx;
+
+	nss_ctx = &nss_top_main.nss[nss_top_main.pvxlan_handler_id];
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_pvxlan_get_ctx);
+
+/*
+ * nss_pvxlan_init()
+ *	Initializes Pvxlan. Gets called from nss_init.c.
+ */
+void nss_pvxlan_init()
+{
+	nss_pvxlan_stats_dentry_create();
+	sema_init(&pvxlan_pvt.sem, 1);
+	init_completion(&pvxlan_pvt.complete);
+
+	memset(&nss_pvxlan_hdl, 0, sizeof(nss_pvxlan_hdl));
+}
diff --git a/qca-nss-drv/nss_pvxlan_log.c b/qca-nss-drv/nss_pvxlan_log.c
new file mode 100644
index 0000000..af516ab
--- /dev/null
+++ b/qca-nss-drv/nss_pvxlan_log.c
@@ -0,0 +1,244 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_pvxlan_log.c
+ *	NSS PVXLAN logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_pvxlan_log_message_types_str
+ *	PVXLAN message strings
+ */
+static int8_t *nss_pvxlan_log_message_types_str[NSS_PVXLAN_MSG_TYPE_MAX] __maybe_unused = {
+	"PVxLAN Sync Stats",
+	"PVxLAN Tunnel Configure Rule",
+	"PVxLAN Tunnel Unconfigure Rule",
+	"PVxLAN Enable Tunnel",
+	"PVxLAN Disable Tunnel",
+	"PVxLAN Add MAC rule",
+	"PVxLAN Delete MAC rule"
+};
+
+/*
+ * nss_pvxlan_log_error_response_types_str
+ *	Strings for error types for PVXLAN messages
+ */
+static int8_t *nss_pvxlan_log_error_response_types_str[NSS_PVXLAN_ERROR_MAX] __maybe_unused = {
+	"PVXLAN Invalid L3 Protocool",
+	"PVXLAN Invalid UDP Protocol",
+	"PVXLAN Tunnel Disabled",
+	"PVXLAN Tunnel Enabled",
+	"PVXLAN Tunnel Not Configured",
+	"PVXLAN Invalid IP Node",
+	"PVXLAN Invalid Flag",
+	"PVXLAN MAC Table Full",
+	"PVXLAN MAC Exists",
+	"PVXLAN MAC Does Not Exist"
+};
+
+/*
+ * nss_pvxlan_log_rule_msg()
+ *	Log NSS PVXLAN rule message.
+ */
+static void nss_pvxlan_log_rule_msg(struct nss_pvxlan_rule_msg *npvrm)
+{
+	nss_trace("%px: NSS PVXLAN Rule message \n"
+		"Encap Rule Src IP: %px\n"
+		"Encap Rule Src Port: %d\n"
+		"Encap Rule Dst Ip: %px\n"
+		"Encap Rule Dst Port: %d\n"
+		"RPS: %d\n"
+		"Flags: %x\n"
+		"Tunnel ID: %d\n",
+		npvrm,
+		&npvrm->encap.src.ip,
+		npvrm->encap.src_port,
+		&npvrm->encap.dest.ip,
+		npvrm->encap.dest_port,
+		npvrm->rps, npvrm->flags,
+		npvrm->tunnel_id);
+}
+
+/*
+ * nss_pvxlan_mac_rule_msg()
+ *	Log NSS PVxLAN MAC rule message.
+ */
+static void nss_pvxlan_log_mac_msg(struct nss_pvxlan_mac_msg *npvcm)
+{
+	nss_trace("%px: NSS PVXLAN MAC message \n"
+		"PVxLAN Mac Addr: %x : %x : %x"
+		"PVxLAN Flags: %u\n"
+		"PVxLAN VNet ID: %u\n"
+		"PVxLAN Tunnel ID: %d\n"
+		"PVxLAN Policy ID: %d",
+		npvcm,
+		npvcm->mac_addr[0], npvcm->mac_addr[1],
+		npvcm->mac_addr[2], npvcm->flags,
+		npvcm->vnet_id, npvcm->tunnel_id,
+		npvcm->policy_id);
+}
+
+/*
+ * nss_pvxlan_log_rule_cfg_msg()
+ *	Log NSS PVxLAN rule configure message.
+ */
+static void nss_pvxlan_log_rule_cfg_msg(struct nss_pvxlan_msg *npvm)
+{
+	struct nss_pvxlan_rule_msg *npvrm __maybe_unused = &npvm->msg.rule_cfg;
+	nss_pvxlan_log_rule_msg(npvrm);
+}
+
+/*
+ * nss_pvxlan_log_rule_uncfg_msg()
+ *	Log NSS PVxLAN rule unconfigure message.
+ */
+static void nss_pvxlan_log_rule_uncfg_msg(struct nss_pvxlan_msg *npvm)
+{
+	struct nss_pvxlan_rule_msg *npvrm __maybe_unused = &npvm->msg.rule_uncfg;
+	nss_pvxlan_log_rule_msg(npvrm);
+}
+
+/*
+ * nss_pvxlan_log_enable_msg()
+ *	Log NSS PVxLAN rule enable message.
+ */
+static void nss_pvxlan_log_enable_msg(struct nss_pvxlan_msg *npvm)
+{
+	struct nss_pvxlan_tunnel_state_msg *npvrm __maybe_unused = &npvm->msg.enable;
+	nss_trace("%px: NSS PVXLAN Tunnel state message: Enable \n", npvrm);
+}
+
+/*
+ * nss_pvxlan_log_disable_msg()
+ *	Log NSS PVxLAN rule disable message.
+ */
+static void nss_pvxlan_log_disable_msg(struct nss_pvxlan_msg *npvm)
+{
+	nss_trace("%px: NSS PVXLAN Tunnel state message: Disable \n", npvm);
+}
+
+/*
+ * nss_pvxlan_log_mac_add_msg()
+ *	Log NSS PVXLAN mac rule add message.
+ */
+static void nss_pvxlan_log_mac_add_msg(struct nss_pvxlan_msg *npvm)
+{
+	struct nss_pvxlan_mac_msg *npvcm __maybe_unused = &npvm->msg.mac_add;
+	nss_pvxlan_log_mac_msg(npvcm);
+}
+
+/*
+ * nss_pvxlan_log_mac_del_msg()
+ *	Log NSS PVXLAN mac rule del message.
+ */
+static void nss_pvxlan_log_mac_del_msg(struct nss_pvxlan_msg *npvm)
+{
+	struct nss_pvxlan_mac_msg *npvcm __maybe_unused = &npvm->msg.mac_del;
+	nss_pvxlan_log_mac_msg(npvcm);
+}
+
+/*
+ * nss_pvxlan_log_verbose()
+ *	Log message contents.
+ */
+static void nss_pvxlan_log_verbose(struct nss_pvxlan_msg *npvm)
+{
+	switch (npvm->cm.type) {
+	case NSS_PVXLAN_MSG_TYPE_TUNNEL_CREATE_RULE:
+		nss_pvxlan_log_rule_cfg_msg(npvm);
+		break;
+
+	case NSS_PVXLAN_MSG_TYPE_TUNNEL_DESTROY_RULE:
+		nss_pvxlan_log_rule_uncfg_msg(npvm);
+		break;
+
+	case NSS_PVXLAN_MSG_TYPE_TUNNEL_ENABLE:
+		nss_pvxlan_log_enable_msg(npvm);
+		break;
+
+	case NSS_PVXLAN_MSG_TYPE_TUNNEL_DISABLE:
+		nss_pvxlan_log_disable_msg(npvm);
+		break;
+
+	case NSS_PVXLAN_MSG_TYPE_MAC_ADD:
+		nss_pvxlan_log_mac_add_msg(npvm);
+		break;
+
+	case NSS_PVXLAN_MSG_TYPE_MAC_DEL:
+		nss_pvxlan_log_mac_del_msg(npvm);
+		break;
+
+	case NSS_PVXLAN_MSG_TYPE_SYNC_STATS:
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", npvm);
+		break;
+	}
+}
+
+/*
+ * nss_pvxlan_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_pvxlan_log_tx_msg(struct nss_pvxlan_msg *npvm)
+{
+	if (npvm->cm.type >= NSS_PVXLAN_MSG_TYPE_MAX) {
+		nss_warning("%px: Invalid message type\n", npvm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", npvm, npvm->cm.type, nss_pvxlan_log_message_types_str[npvm->cm.type]);
+	nss_pvxlan_log_verbose(npvm);
+}
+
+/*
+ * nss_pvxlan_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_pvxlan_log_rx_msg(struct nss_pvxlan_msg *npvm)
+{
+	if (npvm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", npvm);
+		return;
+	}
+
+	if (npvm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (npvm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", npvm, npvm->cm.type,
+			nss_pvxlan_log_message_types_str[npvm->cm.type],
+			npvm->cm.response, nss_cmn_response_str[npvm->cm.response]);
+		goto verbose;
+	}
+
+	if (npvm->cm.error >= NSS_PVXLAN_ERROR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			npvm, npvm->cm.type, nss_pvxlan_log_message_types_str[npvm->cm.type],
+			npvm->cm.response, nss_cmn_response_str[npvm->cm.response],
+			npvm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		npvm, npvm->cm.type, nss_pvxlan_log_message_types_str[npvm->cm.type],
+		npvm->cm.response, nss_cmn_response_str[npvm->cm.response],
+		npvm->cm.error, nss_pvxlan_log_error_response_types_str[npvm->cm.error]);
+
+verbose:
+	nss_pvxlan_log_verbose(npvm);
+}
diff --git a/qca-nss-drv/nss_pvxlan_log.h b/qca-nss-drv/nss_pvxlan_log.h
new file mode 100644
index 0000000..cdc0dd7
--- /dev/null
+++ b/qca-nss-drv/nss_pvxlan_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_PVXLAN_LOG_H__
+#define __NSS_PVXLAN_LOG_H__
+
+/*
+ * nss_pvxlan_log.h
+ *	NSS PVXLAN Log Header File.
+ */
+
+/*
+ * nss_pvxlan_log_tx_msg
+ *	Logs a PVxLAN message that is sent to the NSS firmware.
+ */
+void nss_pvxlan_log_tx_msg(struct nss_pvxlan_msg *ncm);
+
+/*
+ * nss_pvxlan_log_rx_msg
+ *	Logs a PVxLAN message that is received from the NSS firmware.
+ */
+void nss_pvxlan_log_rx_msg(struct nss_pvxlan_msg *ncm);
+
+#endif /* __NSS_PVXLAN_LOG_H__ */
diff --git a/qca-nss-drv/nss_pvxlan_stats.c b/qca-nss-drv/nss_pvxlan_stats.c
new file mode 100644
index 0000000..59f8616
--- /dev/null
+++ b/qca-nss-drv/nss_pvxlan_stats.c
@@ -0,0 +1,213 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_pvxlan_stats.h"
+
+DEFINE_SPINLOCK(nss_pvxlan_tunnel_stats_debug_lock);
+struct nss_pvxlan_tunnel_stats_debug nss_pvxlan_tunnel_debug_stats[NSS_PVXLAN_MAX_INTERFACES];
+
+/*
+ * nss_pvxlan_tunnel_stats_debug_str
+ *	PVxLAN statistics strings for nss tunnel stats
+ */
+static int8_t *nss_pvxlan_tunnel_stats_debug_str[NSS_PVXLAN_MAX_INTERFACES] = {
+	"rx_pkts",
+	"rx_bytes",
+	"tx_pkts",
+	"tx_bytes",
+	"rx_queue_0_dropped",
+	"rx_queue_1_dropped",
+	"rx_queue_2_dropped",
+	"rx_queue_3_dropped",
+	"MAC DB look up failed",
+	"UDP ENCAP look up failed",
+	"dropped packet malformed",
+	"dropped next node queue is full",
+	"dropped headroom insufficient",
+	"dropped version mismatch",
+	"dropped zero sized packet",
+	"dropped pbuf alloc failed",
+	"dropped linearization failed"
+};
+
+/*
+ * nss_pvxlan_tunnel_stats_debug_get()
+ *	Get PVxLAN Tunnel statitics.
+ */
+static void nss_pvxlan_tunnel_stats_debug_get(struct nss_pvxlan_tunnel_stats_debug *stats)
+{
+	uint32_t i;
+
+	if (!stats) {
+		nss_warning("No memory to copy pvxlan tunnel stats");
+		return;
+	}
+
+	spin_lock_bh(&nss_pvxlan_tunnel_stats_debug_lock);
+	for (i = 0; i < NSS_PVXLAN_MAX_INTERFACES; i++) {
+		if (nss_pvxlan_tunnel_debug_stats[i].valid) {
+			memcpy(stats, &nss_pvxlan_tunnel_debug_stats[i],
+				sizeof(struct nss_pvxlan_tunnel_stats_debug));
+			stats++;
+		}
+	}
+	spin_unlock_bh(&nss_pvxlan_tunnel_stats_debug_lock);
+}
+
+/*
+ * nss_pvxlan_stats_read()
+ *	Read PVxLAN Tunnel statistics
+ */
+static ssize_t nss_pvxlan_stats_read(struct file *fp, char __user *ubuf,
+					size_t sz, loff_t *ppos)
+{
+	uint32_t max_output_lines = 2 + (NSS_PVXLAN_MAX_INTERFACES
+					* (NSS_PVXLAN_TUNNEL_STATS_MAX + 2)) + 2;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	struct net_device *dev;
+	uint32_t id, i;
+	struct nss_pvxlan_tunnel_stats_debug *pvxlan_tunnel_stats = NULL;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	pvxlan_tunnel_stats = kzalloc((sizeof(struct nss_pvxlan_tunnel_stats_debug)
+						* NSS_PVXLAN_MAX_INTERFACES), GFP_KERNEL);
+	if (unlikely(!pvxlan_tunnel_stats)) {
+		nss_warning("Could not allocate memory for populating PVxLAN stats");
+		kfree(lbuf);
+		return 0;
+	}
+
+	/*
+	 * Get all stats
+	 */
+	nss_pvxlan_tunnel_stats_debug_get(pvxlan_tunnel_stats);
+
+	/*
+	 * Tunnel stats
+	 */
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+				"\n PVxLAN Tunnel stats start:\n\n");
+
+	for (id = 0; id < NSS_PVXLAN_MAX_INTERFACES; id++) {
+		if (!pvxlan_tunnel_stats[id].valid)
+			break;
+
+		dev = dev_get_by_index(&init_net, pvxlan_tunnel_stats[id].if_index);
+		if (likely(dev)) {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+						"%d. nss interface id=%d, netdevice=%s\n",
+						id, pvxlan_tunnel_stats[id].if_num,
+						dev->name);
+			dev_put(dev);
+		} else {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+						"%d. nss interface id=%d\n", id,
+						pvxlan_tunnel_stats[id].if_num);
+		}
+
+		for (i = 0; i < NSS_PVXLAN_TUNNEL_STATS_MAX; i++) {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+						"\t%s = %llu\n",
+						nss_pvxlan_tunnel_stats_debug_str[i],
+						pvxlan_tunnel_stats[id].stats[i]);
+		}
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+	}
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+				"\n PVxLAN Tunnel stats end\n");
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	kfree(pvxlan_tunnel_stats);
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_pvxlan_stats_sync()
+ *	Sync function for pvxlan statistics
+ */
+void nss_pvxlan_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_pvxlan_stats_msg *stats_msg, uint32_t if_num)
+{
+	uint32_t i;
+	struct nss_pvxlan_tunnel_stats_debug *s = NULL;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	spin_lock_bh(&nss_pvxlan_tunnel_stats_debug_lock);
+	for (i = 0; i < NSS_PVXLAN_MAX_INTERFACES; i++) {
+		if (nss_pvxlan_tunnel_debug_stats[i].if_num == if_num) {
+			s = &nss_pvxlan_tunnel_debug_stats[i];
+			break;
+		}
+	}
+
+	if (!s) {
+		spin_unlock_bh(&nss_pvxlan_tunnel_stats_debug_lock);
+		nss_warning("%px: Tunnel not found: %u", nss_ctx, if_num);
+		return;
+	}
+
+	s->stats[NSS_PVXLAN_TUNNEL_STATS_RX_PKTS] += stats_msg->node_stats.rx_packets;
+	s->stats[NSS_PVXLAN_TUNNEL_STATS_RX_BYTES] += stats_msg->node_stats.rx_bytes;
+	s->stats[NSS_PVXLAN_TUNNEL_STATS_TX_PKTS] += stats_msg->node_stats.tx_packets;
+	s->stats[NSS_PVXLAN_TUNNEL_STATS_TX_BYTES] += stats_msg->node_stats.tx_bytes;
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		s->stats[NSS_PVXLAN_TUNNEL_STATS_RX_QUEUE_0_DROPPED + i] += stats_msg->node_stats.rx_dropped[i];
+	}
+	s->stats[NSS_PVXLAN_TUNNEL_STATS_MAC_DB_LOOKUP_FAILED] +=
+				 stats_msg->mac_db_lookup_failed;
+	s->stats[NSS_PVXLAN_TUNNEL_STATS_UDP_ENCAP_LOOKUP_FAILED] +=
+				stats_msg->udp_encap_lookup_failed;
+	s->stats[NSS_PVXLAN_TUNNEL_STATS_DROP_MALFORMED] +=
+		stats_msg->dropped_malformed;
+	s->stats[NSS_PVXLAN_TUNNEL_STATS_DROP_NEXT_NODE_QUEUE_FULL] +=
+		stats_msg->dropped_next_node_queue_full;
+	s->stats[NSS_PVXLAN_TUNNEL_STATS_DROP_HEADROOM_INSUFFICIENT] +=
+		stats_msg->dropped_hroom;
+	s->stats[NSS_PVXLAN_TUNNEL_STATS_DROP_VERSION_MISMATCH] +=
+		stats_msg->dropped_ver_mis;
+	s->stats[NSS_PVXLAN_TUNNEL_STATS_DROP_ZERO_SIZED_PACKET] +=
+		stats_msg->dropped_zero_sized_packet;
+	s->stats[NSS_PVXLAN_TUNNEL_STATS_DROP_PBUF_ALLOC_FAILED] +=
+		stats_msg->dropped_pbuf_alloc_failed;
+	s->stats[NSS_PVXLAN_TUNNEL_STATS_DROP_LINEAR_FAILED] +=
+		stats_msg->dropped_linear_failed;
+	spin_unlock_bh(&nss_pvxlan_tunnel_stats_debug_lock);
+}
+
+/*
+ * nss_pvxlan_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(pvxlan)
+
+/*
+ * nss_pvxlan_stats_dentry_create()
+ *	Create gre tunnel statistics debug entry.
+ */
+void nss_pvxlan_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("pvxlan", &nss_pvxlan_stats_ops);
+}
diff --git a/qca-nss-drv/nss_pvxlan_stats.h b/qca-nss-drv/nss_pvxlan_stats.h
new file mode 100644
index 0000000..874bf78
--- /dev/null
+++ b/qca-nss-drv/nss_pvxlan_stats.h
@@ -0,0 +1,66 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_PVXLAN_STATS_H
+#define __NSS_PVXLAN_STATS_H
+
+/*
+ * pvxlan statistic counters
+ */
+enum nss_pvxlan_tunnel_stats {
+	NSS_PVXLAN_TUNNEL_STATS_RX_PKTS,
+	NSS_PVXLAN_TUNNEL_STATS_RX_BYTES,
+	NSS_PVXLAN_TUNNEL_STATS_TX_PKTS,
+	NSS_PVXLAN_TUNNEL_STATS_TX_BYTES,
+	NSS_PVXLAN_TUNNEL_STATS_RX_QUEUE_0_DROPPED,
+	NSS_PVXLAN_TUNNEL_STATS_RX_QUEUE_1_DROPPED,
+	NSS_PVXLAN_TUNNEL_STATS_RX_QUEUE_2_DROPPED,
+	NSS_PVXLAN_TUNNEL_STATS_RX_QUEUE_3_DROPPED,
+	NSS_PVXLAN_TUNNEL_STATS_MAC_DB_LOOKUP_FAILED,
+	NSS_PVXLAN_TUNNEL_STATS_UDP_ENCAP_LOOKUP_FAILED,
+	NSS_PVXLAN_TUNNEL_STATS_DROP_MALFORMED,
+	NSS_PVXLAN_TUNNEL_STATS_DROP_NEXT_NODE_QUEUE_FULL,
+	NSS_PVXLAN_TUNNEL_STATS_DROP_HEADROOM_INSUFFICIENT,
+	NSS_PVXLAN_TUNNEL_STATS_DROP_VERSION_MISMATCH,
+	NSS_PVXLAN_TUNNEL_STATS_DROP_ZERO_SIZED_PACKET,
+	NSS_PVXLAN_TUNNEL_STATS_DROP_PBUF_ALLOC_FAILED,
+	NSS_PVXLAN_TUNNEL_STATS_DROP_LINEAR_FAILED,
+	NSS_PVXLAN_TUNNEL_STATS_MAX,
+};
+
+/*
+ * PVxLAN session debug statistics
+ */
+struct nss_pvxlan_tunnel_stats_debug {
+	uint64_t stats[NSS_PVXLAN_TUNNEL_STATS_MAX];
+	int32_t if_index;
+	uint32_t if_num; /* nss interface number */
+	bool valid;
+};
+
+/*
+ * Data structures to store PVxLAN nss debug stats
+ */
+extern spinlock_t nss_pvxlan_tunnel_stats_debug_lock;
+extern struct nss_pvxlan_tunnel_stats_debug nss_pvxlan_tunnel_debug_stats[NSS_PVXLAN_MAX_INTERFACES];
+
+/*
+ * PVxLAN statistics APIs
+ */
+extern void nss_pvxlan_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_pvxlan_stats_msg *stats_msg, uint32_t if_num);
+extern void nss_pvxlan_stats_dentry_create(void);
+
+#endif /* __NSS_PVXLAN_STATS_H */
diff --git a/qca-nss-drv/nss_qrfs.c b/qca-nss-drv/nss_qrfs.c
new file mode 100644
index 0000000..cfbff59
--- /dev/null
+++ b/qca-nss-drv/nss_qrfs.c
@@ -0,0 +1,472 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_qrfs_stats.h"
+#include "nss_qrfs_log.h"
+
+/*
+ * Notify data structure
+ */
+struct nss_qrfs_notify_data {
+	nss_qrfs_msg_callback_t qrfs_callback;
+	void *app_data;
+};
+
+static struct nss_qrfs_notify_data nss_qrfs_notify[NSS_CORE_MAX];
+
+/*
+ * nss_qrfs_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static bool nss_qrfs_verify_if_num(uint32_t if_num)
+{
+	return if_num == NSS_QRFS_INTERFACE;
+}
+
+/*
+ * nss_qrfs_msg_handler()
+ *	Handle NSS -> HLOS messages for QRFS
+ */
+static void nss_qrfs_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, void *app_data)
+{
+	struct nss_qrfs_msg *nqm = (struct nss_qrfs_msg *)ncm;
+	nss_qrfs_msg_callback_t cb;
+
+	/*
+	 * Trace messages.
+	 */
+	nss_qrfs_log_rx_msg(nqm);
+
+	if (!nss_qrfs_verify_if_num(ncm->interface)) {
+		nss_warning("%px: invalid interface %d for QRFS\n", nss_ctx, ncm->interface);
+		return;
+	}
+
+	/*
+	 * Is this a valid request/response?
+	 */
+	if (ncm->type >= NSS_QRFS_MSG_MAX) {
+		nss_warning("%px: invalid message %d for QRFS\n", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_qrfs_msg)) {
+		nss_warning("%px: message length is greater than required: %d\n", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	switch (ncm->type) {
+	case NSS_QRFS_MSG_STATS_SYNC:
+		/*
+		 * Update QRFS statistics.
+		 */
+		nss_qrfs_stats_sync(nss_ctx, &nqm->msg.stats_sync);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_qrfs_notify[nss_ctx->id].qrfs_callback;
+		ncm->app_data = (nss_ptr_t)nss_qrfs_notify[nss_ctx->id].app_data;
+	}
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_qrfs_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, nqm);
+}
+
+/*
+ * nss_qrfs_get_ctx()
+ */
+static struct nss_ctx_instance *nss_qrfs_get_ctx(int core_id)
+{
+	return &nss_top_main.nss[core_id];
+}
+
+/*
+ * nss_qrfs_get_flow_keys()
+ *	Get 5 tuple information from flow keys and set in flow rule message.
+ */
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 18, 21))
+static bool nss_qrfs_get_flow_keys(struct nss_ctx_instance *nss_ctx, struct sk_buff *skb,
+					struct nss_qrfs_flow_rule_msg *nqfrm)
+{
+	struct flow_keys keys;
+	uint16_t protocol = skb->protocol;
+	bool res;
+	struct ipv6hdr *ip6hdr;
+
+	res = skb_flow_dissect(skb, &keys);
+	if (!res) {
+		nss_warning("%px: failed to get flow keys\n", nss_ctx);
+		return res;
+	}
+
+	nqfrm->protocol = keys.ip_proto;
+	nqfrm->src_port = keys.port16[0];
+	nqfrm->dst_port = keys.port16[1];
+
+	if (protocol == htons(ETH_P_IP)) {
+		nqfrm->ip_version = 4;
+		nqfrm->src_addr[0] = keys.src;
+		nqfrm->dst_addr[0] = keys.dst;
+		return true;
+	}
+
+	nqfrm->ip_version = 6;
+	ip6hdr = (struct ipv6hdr *)skb_network_header(skb);
+	if (!ip6hdr) {
+		nss_warning("%px: failed to get IPv6 address\n", nss_ctx);
+		return false;
+	}
+
+	memcpy(nqfrm->src_addr, &ip6hdr->saddr, sizeof(struct in6_addr));
+	memcpy(nqfrm->dst_addr, &ip6hdr->daddr, sizeof(struct in6_addr));
+
+	return true;
+}
+#else
+static bool nss_qrfs_get_flow_keys(struct nss_ctx_instance *nss_ctx, struct sk_buff *skb,
+					struct nss_qrfs_flow_rule_msg *nqfrm)
+{
+	struct flow_keys keys;
+	bool res;
+
+	res = skb_flow_dissect_flow_keys(skb, &keys, 0);
+	if (!res) {
+		nss_warning("%px: failed to get flow keys\n", nss_ctx);
+		return res;
+	}
+
+	nqfrm->protocol = (uint16_t)keys.basic.ip_proto;
+	nqfrm->src_port = keys.ports.src;
+	nqfrm->dst_port = keys.ports.dst;
+
+	if (keys.basic.n_proto == htons(ETH_P_IP)) {
+		nqfrm->ip_version = 4;
+		nqfrm->src_addr[0] = keys.addrs.v4addrs.src;
+		nqfrm->dst_addr[0] = keys.addrs.v4addrs.dst;
+		return true;
+	}
+
+	nqfrm->ip_version = 6;
+	memcpy(nqfrm->src_addr, &keys.addrs.v6addrs.src, sizeof(struct in6_addr));
+	memcpy(nqfrm->dst_addr, &keys.addrs.v6addrs.dst, sizeof(struct in6_addr));
+
+	return true;
+}
+#endif
+
+/*
+ * nss_qrfs_flow_add_msg_callback()
+ *	Callback function for receiving flow add response messages.
+ */
+static void nss_qrfs_flow_add_msg_callback(void *app_data, struct nss_qrfs_msg *nqm)
+{
+	struct nss_ctx_instance *nss_ctx __maybe_unused = (struct nss_ctx_instance *)app_data;
+	struct nss_qrfs_flow_rule_msg *nqfrm;
+
+	if (nqm->cm.type != NSS_QRFS_MSG_FLOW_ADD) {
+		nss_warning("%px: invalid flow response message %d\n", nss_ctx, nqm->cm.type);
+		return;
+	}
+
+	nqfrm = &nqm->msg.flow_add;
+
+	if ((nqfrm->ip_version != 4) && (nqfrm->ip_version != 6)) {
+		nss_warning("%px: invalid IP version %d\n", nss_ctx, nqfrm->ip_version);
+		return;
+	}
+
+	if (nqm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("%px: flow add configuration error: %d for NSS core %d\n",
+				nss_ctx, nqm->cm.error, nss_ctx->id);
+	}
+}
+
+/*
+ * nss_qrfs_flow_delete_msg_callback()
+ *	Callback function for receiving flow delete response messages.
+ */
+static void nss_qrfs_flow_delete_msg_callback(void *app_data, struct nss_qrfs_msg *nqm)
+{
+	struct nss_ctx_instance *nss_ctx __maybe_unused = (struct nss_ctx_instance *)app_data;
+	struct nss_qrfs_flow_rule_msg *nqfrm;
+
+	if (nqm->cm.type != NSS_QRFS_MSG_FLOW_DELETE) {
+		nss_warning("%px: invalid flow response message %d\n", nss_ctx, nqm->cm.type);
+		return;
+	}
+
+	nqfrm = &nqm->msg.flow_delete;
+
+	if ((nqfrm->ip_version != 4) && (nqfrm->ip_version != 6)) {
+		nss_warning("%px: invalid IP version %d\n", nss_ctx, nqfrm->ip_version);
+		return;
+	}
+
+	if (nqm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("%px: flow delete configuration error: %d for NSS core %d\n",
+				nss_ctx, nqm->cm.error, nss_ctx->id);
+	}
+}
+
+/*
+ * nss_qrfs_msg_init()
+ *	Initialize the common header of QRFS message
+ */
+static void nss_qrfs_msg_init(struct nss_qrfs_msg *nqm, uint16_t if_num, uint32_t type, uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&nqm->cm, if_num, type, len, cb, app_data);
+}
+
+/*
+ * nss_qrfs_tx_msg()
+ *	Transmit a QRFS message to NSS firmware
+ */
+static nss_tx_status_t nss_qrfs_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_qrfs_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace messages.
+	 */
+	nss_qrfs_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!nss_qrfs_verify_if_num(ncm->interface)) {
+		nss_warning("%px: interface is not QRFS interface: %d\n", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_QRFS_MSG_MAX) {
+		nss_warning("%px: message type is out of range: %d\n", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ * nss_qrfs_add_flow_rule()
+ *	Set a QRFS flow rule add message and transmit the message to NSS core.
+ */
+static nss_tx_status_t nss_qrfs_add_flow_rule(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+					struct sk_buff *skb, uint32_t cpu, bool need_cb)
+{
+	struct nss_qrfs_msg nqm;
+	struct nss_qrfs_flow_rule_msg *nqfrm;
+	nss_tx_status_t status;
+	nss_qrfs_msg_callback_t cb = NULL;
+	void *app_data = NULL;
+	bool res;
+
+	memset(&nqm, 0, sizeof(struct nss_qrfs_msg));
+
+	if (need_cb) {
+		cb = nss_qrfs_flow_add_msg_callback;
+		app_data = (void *)nss_ctx;
+	}
+
+	/*
+	 * Initialize common header of QRFS flow rule add message.
+	 */
+	nss_qrfs_msg_init(&nqm, NSS_QRFS_INTERFACE, NSS_QRFS_MSG_FLOW_ADD,
+				sizeof(struct nss_qrfs_flow_rule_msg), cb, app_data);
+
+	/*
+	 * Set flow rule of QRFS flow rule add message
+	 */
+	nqfrm = &nqm.msg.flow_add;
+	res = nss_qrfs_get_flow_keys(nss_ctx, skb, nqfrm);
+	if (!res) {
+		return NSS_TX_FAILURE;
+	}
+
+	nqfrm->cpu = (uint16_t)cpu;
+	nqfrm->if_num = if_num;
+
+	/*
+	 * Send QRFS flow rule add message to NSS core
+	 */
+	status = nss_qrfs_tx_msg(nss_ctx, &nqm);
+	if (status == NSS_TX_SUCCESS) {
+		return status;
+	}
+
+	return NSS_TX_FAILURE;
+}
+
+/*
+ * nss_qrfs_delete_flow_rule()
+ *	Set a QRFS delete flow rule message and transmit the message to all NSS core.
+ */
+static nss_tx_status_t nss_qrfs_delete_flow_rule(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+						struct sk_buff *skb, uint32_t cpu, bool need_cb)
+{
+	struct nss_qrfs_msg nqm;
+	struct nss_qrfs_flow_rule_msg *nqfrm;
+	nss_tx_status_t status;
+	nss_qrfs_msg_callback_t cb = NULL;
+	void *app_data = NULL;
+	bool res;
+
+	memset(&nqm, 0, sizeof(struct nss_qrfs_msg));
+
+	if (need_cb) {
+		cb = nss_qrfs_flow_delete_msg_callback;
+		app_data = (void *)nss_ctx;
+	}
+
+	/*
+	 * Initialize common header of QRFS flow rule delete message.
+	 */
+	nss_qrfs_msg_init(&nqm, NSS_QRFS_INTERFACE, NSS_QRFS_MSG_FLOW_DELETE,
+				sizeof(struct nss_qrfs_flow_rule_msg), cb, app_data);
+
+	/*
+	 * Set flow rule of QRFS flow rule delete message
+	 */
+	nqfrm = &nqm.msg.flow_delete;
+	res = nss_qrfs_get_flow_keys(nss_ctx, skb, nqfrm);
+	if (!res) {
+		return NSS_TX_FAILURE;
+	}
+
+	nqfrm->cpu = (uint16_t)cpu;
+	nqfrm->if_num = if_num;
+
+	/*
+	 * Send QRFS flow rule delete message to NSS core
+	 */
+	status = nss_qrfs_tx_msg(nss_ctx, &nqm);
+	if (status == NSS_TX_SUCCESS) {
+		return status;
+	}
+
+	return NSS_TX_FAILURE;
+}
+
+/*
+ * nss_qrfs_set_flow_rule()
+ *	Set a QRFS flow rule message and transmit the message to all NSS cores.
+ */
+nss_tx_status_t nss_qrfs_set_flow_rule(struct sk_buff *skb, uint32_t cpu, uint32_t action)
+{
+	struct nss_ctx_instance *nss_ctx;
+	nss_tx_status_t status;
+	int i;
+
+	for (i = 0; i < NSS_CORE_MAX; i++) {
+		nss_ctx = nss_qrfs_get_ctx(i);
+
+		/*
+		 * Set QRFS flow rule message and transmit the message to NSS core.
+		 *
+		 * TODO: Remove if_num parameter from add_flow_rule() and
+		 * delete_flow_rule(), since it is unused in firmware.
+		 */
+		if (action == NSS_QRFS_MSG_FLOW_ADD) {
+			status = nss_qrfs_add_flow_rule(nss_ctx, 0, skb, cpu, true);
+		} else {
+			status = nss_qrfs_delete_flow_rule(nss_ctx, 0, skb, cpu, true);
+		}
+
+		if (status != NSS_TX_SUCCESS) {
+			nss_warning("%px: failed to send flow rule to NSS core %d\n", nss_ctx, i);
+			return NSS_TX_FAILURE;
+		}
+	}
+
+	return NSS_TX_SUCCESS;
+}
+EXPORT_SYMBOL(nss_qrfs_set_flow_rule);
+
+/*
+ * nss_qrfs_register_handler()
+ */
+void nss_qrfs_register_handler(struct nss_ctx_instance *nss_ctx)
+{
+	nss_core_register_handler(nss_ctx, NSS_QRFS_INTERFACE, nss_qrfs_msg_handler, NULL);
+
+	if (nss_ctx->id == NSS_CORE_0) {
+		nss_qrfs_stats_dentry_create();
+	}
+}
+EXPORT_SYMBOL(nss_qrfs_register_handler);
+
+/*
+ * nss_qrfs_notify_register()
+ *	Register to receive QRFS notify messages.
+ */
+struct nss_ctx_instance *nss_qrfs_notify_register(int core, nss_qrfs_msg_callback_t cb, void *app_data)
+{
+	if (core >= NSS_CORE_MAX) {
+		nss_warning("Input core number %d is wrong\n", core);
+		return NULL;
+	}
+
+	nss_qrfs_notify[core].qrfs_callback = cb;
+	nss_qrfs_notify[core].app_data = app_data;
+
+	return (struct nss_ctx_instance *)&nss_top_main.nss[core];
+}
+
+/*
+ * nss_qrfs_notify_unregister()
+ *	Unregister to receive QRFS notify messages.
+ */
+void nss_qrfs_notify_unregister(int core)
+{
+	if (core >= NSS_CORE_MAX) {
+		nss_warning("Input core number %d is wrong\n", core);
+		return;
+	}
+
+	nss_qrfs_notify[core].qrfs_callback = NULL;
+	nss_qrfs_notify[core].app_data = NULL;
+}
+
+/*
+ * nss_qrfs_init()
+ */
+void nss_qrfs_init(void)
+{
+	int core;
+
+	for (core = 0; core < NSS_CORE_MAX; core++) {
+		nss_qrfs_notify_register(core, NULL, NULL);
+	}
+}
diff --git a/qca-nss-drv/nss_qrfs_log.c b/qca-nss-drv/nss_qrfs_log.c
new file mode 100644
index 0000000..d481e28
--- /dev/null
+++ b/qca-nss-drv/nss_qrfs_log.c
@@ -0,0 +1,174 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_qrfs_log.c
+ *	NSS QRFS logger file.
+ */
+
+#include "nss_core.h"
+#define NSS_QRFS_LOG_IPV4 4
+#define NSS_QRFS_LOG_IPV6 6
+
+/*
+ * nss_qrfs_log_message_types_str
+ *	QRFS message strings
+ */
+static int8_t *nss_qrfs_log_message_types_str[NSS_QRFS_MSG_MAX] __maybe_unused = {
+	"QRFS Flow Add Message",
+	"QRFS Flow Delete Message",
+	"QRFS MAC Add Message",
+	"QRFS MAC Delete Message",
+	"QRFS Stats Sync",
+};
+
+/*
+ * nss_qrfs_log_error_response_types_str
+ *	Strings for error types for QRFS messages
+ */
+static int8_t *nss_qrfs_log_error_response_types_str[NSS_QRFS_ERROR_MAX] __maybe_unused = {
+	"QRFS Invalid Message Type",
+	"QRFS Invalid Message Size",
+	"QRFS Invalid IP Version",
+	"QRFS V4 Flow Table Full",
+	"QRFS V6 Flow Table Full",
+	"QRFS MAC Table Full",
+};
+
+/*
+ * nss_qrfs_log_flow_rule_msg()
+ *	Log NSS QRFS Flow Rule Message.
+ */
+static void nss_qrfs_log_flow_rule_msg(struct nss_qrfs_flow_rule_msg *nqfm)
+{
+	nss_trace("%px: NSS QRFS Flow Rule Message:\n"
+		"QRFS Source Port: %d\n"
+		"QRFS Destination Port: %d\n"
+		"QRFS IP Version: %d\n"
+		"QRFS Protcol: %d\n"
+		"QRFS CPU ID: %d\n"
+		"QRFS Physical Interface Number: %d\n",
+		nqfm, nqfm->src_port,
+		nqfm->dst_port, nqfm->ip_version,
+		nqfm->protocol, nqfm->cpu,
+		nqfm->if_num);
+
+	/*
+	 * Continuation of log. Different identifiers based on ip_version
+	 */
+	if (nqfm->ip_version == NSS_QRFS_LOG_IPV6) {
+		nss_trace("QRFS Source Address: %pI6\n"
+			"QRFS Destination Address: %pI6\n",
+			nqfm->src_addr, nqfm->dst_addr);
+	} else if (nqfm->ip_version == NSS_QRFS_LOG_IPV4) {
+		nss_trace("QRFS Source Address: %pI4\n"
+			"QRFS Destination Address: %pI4\n",
+			nqfm->src_addr, nqfm->dst_addr);
+	}
+}
+
+/*
+ * nss_qrfs_log_mac_rule_msg()
+ *	Log NSS QRFS MAC Rule Message.
+ */
+static void nss_qrfs_log_mac_rule_msg(struct nss_qrfs_mac_rule_msg *nqmm)
+{
+	nss_trace("%px: NSS QRFS MAC Rule Message:\n"
+		"QRFS MAC: %pM\n"
+		"QRFS CPU ID: %d\n"
+		"QRFS Physical Interface Number: %d\n",
+		nqmm, nqmm->mac,
+		nqmm->cpu, nqmm->if_num);
+}
+
+/*
+ * nss_qrfs_log_verbose()
+ *	Log message contents.
+ */
+static void nss_qrfs_log_verbose(struct nss_qrfs_msg *nqm)
+{
+	switch (nqm->cm.type) {
+	case NSS_QRFS_MSG_FLOW_ADD:
+	case NSS_QRFS_MSG_FLOW_DELETE:
+		nss_qrfs_log_flow_rule_msg(&nqm->msg.flow_add);
+		break;
+
+	case NSS_QRFS_MSG_MAC_ADD:
+	case NSS_QRFS_MSG_MAC_DELETE:
+		nss_qrfs_log_mac_rule_msg(&nqm->msg.mac_add);
+		break;
+
+	case NSS_QRFS_MSG_STATS_SYNC:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", nqm);
+		break;
+	}
+}
+
+/*
+ * nss_qrfs_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_qrfs_log_tx_msg(struct nss_qrfs_msg *nqm)
+{
+	if (nqm->cm.type >= NSS_QRFS_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", nqm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nqm, nqm->cm.type, nss_qrfs_log_message_types_str[nqm->cm.type]);
+	nss_qrfs_log_verbose(nqm);
+}
+
+/*
+ * nss_qrfs_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_qrfs_log_rx_msg(struct nss_qrfs_msg *nqm)
+{
+	if (nqm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", nqm);
+		return;
+	}
+
+	if (nqm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nqm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nqm, nqm->cm.type,
+			nss_qrfs_log_message_types_str[nqm->cm.type],
+			nqm->cm.response, nss_cmn_response_str[nqm->cm.response]);
+		goto verbose;
+	}
+
+	if (nqm->cm.error >= NSS_QRFS_ERROR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			nqm, nqm->cm.type, nss_qrfs_log_message_types_str[nqm->cm.type],
+			nqm->cm.response, nss_cmn_response_str[nqm->cm.response],
+			nqm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		nqm, nqm->cm.type, nss_qrfs_log_message_types_str[nqm->cm.type],
+		nqm->cm.response, nss_cmn_response_str[nqm->cm.response],
+		nqm->cm.error, nss_qrfs_log_error_response_types_str[nqm->cm.error]);
+
+verbose:
+	nss_qrfs_log_verbose(nqm);
+}
diff --git a/qca-nss-drv/nss_qrfs_log.h b/qca-nss-drv/nss_qrfs_log.h
new file mode 100644
index 0000000..de9832e
--- /dev/null
+++ b/qca-nss-drv/nss_qrfs_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_QRFS_LOG_H__
+#define __NSS_QRFS_LOG_H__
+
+/*
+ * nss_qrfs_log.h
+ *	NSS QRFS Log Header File
+ */
+
+/*
+ * nss_qrfs_log_tx_msg
+ *	Logs a qrfs message that is sent to the NSS firmware.
+ */
+void nss_qrfs_log_tx_msg(struct nss_qrfs_msg *nqm);
+
+/*
+ * nss_qrfs_log_rx_msg
+ *	Logs a qrfs message that is received from the NSS firmware.
+ */
+void nss_qrfs_log_rx_msg(struct nss_qrfs_msg *nqm);
+
+#endif /* __NSS_QRFS_LOG_H__ */
diff --git a/qca-nss-drv/nss_qrfs_stats.c b/qca-nss-drv/nss_qrfs_stats.c
new file mode 100644
index 0000000..6949083
--- /dev/null
+++ b/qca-nss-drv/nss_qrfs_stats.c
@@ -0,0 +1,148 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_qrfs_stats.h"
+
+/*
+ * Spinlock to protect QRFS statistics update/read
+ */
+DEFINE_SPINLOCK(nss_qrfs_stats_lock);
+
+/*
+ * nss_qrfs_stats_str
+ *	QRFS stats strings
+ */
+struct nss_stats_info nss_qrfs_stats_str[NSS_QRFS_STATS_MAX] = {
+	{"rx_pkts"		, NSS_STATS_TYPE_COMMON},
+	{"rx_byts"		, NSS_STATS_TYPE_COMMON},
+	{"tx_pkts"		, NSS_STATS_TYPE_COMMON},
+	{"tx_byts"		, NSS_STATS_TYPE_COMMON},
+	{"rx_queue[0]_drops"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue[1]_drops"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue[2]_drops"	, NSS_STATS_TYPE_DROP},
+	{"rx_queue[3]_drops"	, NSS_STATS_TYPE_DROP},
+	{"invalid_offset"	, NSS_STATS_TYPE_EXCEPTION},
+	{"unknown_protocol"	, NSS_STATS_TYPE_EXCEPTION},
+	{"ipv4_flow_rule_hits"	, NSS_STATS_TYPE_SPECIAL},
+	{"ipv6_flow_rule_hits"	, NSS_STATS_TYPE_SPECIAL}
+};
+
+uint64_t nss_qrfs_stats[NSS_MAX_CORES][NSS_QRFS_STATS_MAX];
+
+/*
+ * nss_qrfs_stats_read()
+ *	Read QRFS statistics.
+ */
+static ssize_t nss_qrfs_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i, core;
+
+	/*
+	 * Max output lines = #stats + few blank lines for banner printing +
+	 * Number of Extra outputlines for future reference to add new stats.
+	 */
+	uint32_t max_output_lines = (NSS_QRFS_STATS_MAX + 3) * NSS_MAX_CORES + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_QRFS_STATS_MAX * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "qrfs", NSS_STATS_SINGLE_CORE);
+	/*
+	 * QRFS statistics
+	 */
+	for (core = 0; core < nss_top_main.num_nss; core++) {
+		spin_lock_bh(&nss_qrfs_stats_lock);
+		for (i = 0; i < NSS_QRFS_STATS_MAX; i++) {
+			stats_shadow[i] = nss_qrfs_stats[core][i];
+		}
+		spin_unlock_bh(&nss_qrfs_stats_lock);
+
+		size_wr += nss_stats_print("qrfs", NULL, NSS_STATS_SINGLE_INSTANCE
+						, nss_qrfs_stats_str
+						, stats_shadow
+						, NSS_QRFS_STATS_MAX
+						, lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_qrfs_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(qrfs)
+
+/*
+ * nss_qrfs_stats_dentry_create()
+ *	Create QRFS statistics debug entry.
+ */
+void nss_qrfs_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("qrfs", &nss_qrfs_stats_ops);
+}
+
+/*
+ * nss_qrfs_stats_sync()
+ *	Handle the syncing of NSS QRFS statistics.
+ */
+void nss_qrfs_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_qrfs_stats_sync_msg *nqssm)
+{
+	int id = nss_ctx->id;
+	int j;
+
+	spin_lock_bh(&nss_qrfs_stats_lock);
+
+	/*
+	 * Common node stats
+	 */
+	nss_qrfs_stats[id][NSS_STATS_NODE_RX_PKTS] += nqssm->node_stats.rx_packets;
+	nss_qrfs_stats[id][NSS_STATS_NODE_RX_BYTES] += nqssm->node_stats.rx_bytes;
+	nss_qrfs_stats[id][NSS_STATS_NODE_TX_PKTS] += nqssm->node_stats.tx_packets;
+	nss_qrfs_stats[id][NSS_STATS_NODE_TX_BYTES] += nqssm->node_stats.tx_bytes;
+
+	for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+		nss_qrfs_stats[id][NSS_STATS_NODE_RX_QUEUE_0_DROPPED + j] += nqssm->node_stats.rx_dropped[j];
+	}
+
+	/*
+	 * QRFS statistics
+	 */
+	nss_qrfs_stats[id][NSS_QRFS_STATS_INVALID_OFFSET] += nqssm->invalid_offset;
+	nss_qrfs_stats[id][NSS_QRFS_STATS_UNKNOWN_PROTO] += nqssm->unknown_protocol;
+	nss_qrfs_stats[id][NSS_QRFS_STATS_IPV4_FLOW_HITS] += nqssm->ipv4_flow_rule_hits;
+	nss_qrfs_stats[id][NSS_QRFS_STATS_IPV6_FLOW_HITS] += nqssm->ipv6_flow_rule_hits;
+
+	spin_unlock_bh(&nss_qrfs_stats_lock);
+}
diff --git a/qca-nss-drv/nss_qrfs_stats.h b/qca-nss-drv/nss_qrfs_stats.h
new file mode 100644
index 0000000..7992270
--- /dev/null
+++ b/qca-nss-drv/nss_qrfs_stats.h
@@ -0,0 +1,38 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_QRFS_STATS_H
+#define __NSS_QRFS_STATS_H
+
+/*
+ * QRFS node statistics
+ */
+enum nss_qrfs_stats_types {
+	NSS_QRFS_STATS_INVALID_OFFSET = NSS_STATS_NODE_MAX,
+					/* Number of packets with invalid L3, L4 offset */
+	NSS_QRFS_STATS_UNKNOWN_PROTO,	/* Number of packets with protocol other than TCP, UDP */
+	NSS_QRFS_STATS_IPV4_FLOW_HITS,	/* Number of IPv4 flow rule hits */
+	NSS_QRFS_STATS_IPV6_FLOW_HITS,	/* Number of IPv6 flow rule hits */
+	NSS_QRFS_STATS_MAX,
+};
+
+/*
+ * QRFS statistics APIs
+ */
+extern void nss_qrfs_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_qrfs_stats_sync_msg *nqssm);
+extern void nss_qrfs_stats_dentry_create(void);
+
+#endif /* __NSS_QRFS_STATS_H */
diff --git a/qca-nss-drv/nss_qvpn.c b/qca-nss-drv/nss_qvpn.c
new file mode 100644
index 0000000..b6068d9
--- /dev/null
+++ b/qca-nss-drv/nss_qvpn.c
@@ -0,0 +1,344 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_qvpn_stats.h"
+#include "nss_qvpn_strings.h"
+#include "nss_qvpn_log.h"
+
+#define NSS_QVPN_TX_TIMEOUT 1000	/* 1 Second */
+#define NSS_QVPN_INTERFACE_MAX_LONG BITS_TO_LONGS(NSS_MAX_NET_INTERFACES)	/**< QVPN interface mapping bits. */
+
+/*
+ * Private data structure
+ */
+static struct nss_qvpn_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	unsigned long if_map[NSS_QVPN_INTERFACE_MAX_LONG];
+	enum nss_qvpn_error_type resp;
+} qvpn_pvt;
+
+/*
+ * nss_qvpn_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static bool nss_qvpn_verify_if_num(uint32_t if_num)
+{
+	enum nss_dynamic_interface_type if_type;
+
+	if_type = nss_dynamic_interface_get_type(nss_qvpn_get_context(), if_num);
+	if ((if_type != NSS_DYNAMIC_INTERFACE_TYPE_QVPN_INNER) &&
+	    (if_type != NSS_DYNAMIC_INTERFACE_TYPE_QVPN_OUTER)) {
+		nss_warning("%px: if_num = %u interface type returned is %d\n", nss_qvpn_get_context(), if_num, if_type);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_qvpn_handler()
+ *	Handle NSS to HLOS messages for QVPN
+ */
+static void nss_qvpn_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, void *app_data)
+{
+	nss_qvpn_msg_callback_t cb;
+
+	nss_assert(nss_qvpn_verify_if_num(ncm->interface));
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_QVPN_MSG_TYPE_MAX) {
+		nss_warning("%px: received invalid message %d for qvpn interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_qvpn_msg)) {
+		nss_warning("%px: length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Log failures
+	 */
+
+	nss_core_log_msg_failures(nss_ctx, ncm);
+	/*
+	 * Trace messages.
+	 */
+	nss_qvpn_log_rx_msg((struct nss_qvpn_msg *)ncm);
+
+	if (ncm->type == NSS_QVPN_MSG_TYPE_SYNC_STATS) {
+		nss_qvpn_stats_tunnel_sync(nss_ctx, ncm);
+		nss_qvpn_stats_notify(nss_ctx, ncm->interface);
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, qvpn sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->nss_rx_interface_handlers[ncm->interface].app_data;
+	}
+
+	/*
+	 * load, test & call
+	 */
+	cb = (nss_qvpn_msg_callback_t)ncm->cb;
+	if (unlikely(!cb)) {
+		nss_trace("%px: rx handler unregistered for i/f: %u\n", nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb((void *)ncm->app_data, ncm);
+}
+
+/*
+ * nss_qvpn_callback()
+ *	Callback to handle the completion of NSS to HLOS messages.
+ */
+static void nss_qvpn_callback(void *app_data, struct nss_qvpn_msg *nvm)
+{
+	enum nss_qvpn_error_type *resp = (enum nss_qvpn_error_type *)app_data;
+
+	*resp = (nvm->cm.response == NSS_CMN_RESPONSE_ACK) ?  NSS_QVPN_ERROR_TYPE_NONE : nvm->cm.error;
+
+	/*
+	 * Write memory barrier
+	 */
+	smp_wmb();
+
+	complete(&qvpn_pvt.complete);
+}
+
+/*
+ * nss_qvpn_ifmap_get()
+ *	Return QVPN active interfaces map.
+ */
+unsigned long *nss_qvpn_ifmap_get(void)
+{
+	return qvpn_pvt.if_map;
+}
+
+/*
+ * nss_qvpn_get_context()
+ *	Return NSS QVPN context.
+ */
+struct nss_ctx_instance *nss_qvpn_get_context(void)
+{
+	return &nss_top_main.nss[nss_top_main.qvpn_handler_id];
+}
+EXPORT_SYMBOL(nss_qvpn_get_context);
+
+/*
+ * nss_qvpn_tx_msg()
+ *	Transmit a QVPN message to NSS firmware
+ */
+nss_tx_status_t nss_qvpn_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_qvpn_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!nss_qvpn_verify_if_num(ncm->interface)) {
+		nss_warning("%px: tx request for interface that is not a qvpn: %u\n", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	if (ncm->type >= NSS_QVPN_MSG_TYPE_MAX) {
+		nss_warning("%px: message type out of range: %d\n", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_qvpn_log_tx_msg(msg);
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_qvpn_tx_msg);
+
+/*
+ * nss_qvpn_tx_msg_sync()
+ *	Transmit a QVPN message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_qvpn_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_qvpn_msg *nvm,
+		uint32_t if_num, enum nss_qvpn_msg_type type, uint16_t len, enum nss_qvpn_error_type *resp)
+{
+	struct nss_qvpn_msg nqm;
+	nss_tx_status_t status;
+	int ret = 0;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (len > sizeof(nqm.msg)) {
+		nss_warning("%px: Incorrect message length=%u for type %d and if_num=%u\n", nss_ctx, len, type, if_num);
+		return NSS_TX_FAILURE_TOO_LARGE;
+	}
+
+	if (!resp) {
+		nss_warning("%px: Invalid input, resp=NULL\n", nss_ctx);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	nss_qvpn_msg_init(&nqm, if_num, type, len, nss_qvpn_callback, &qvpn_pvt.resp);
+	memcpy(&nqm.msg, &nvm->msg, len);
+
+	down(&qvpn_pvt.sem);
+
+	status = nss_qvpn_tx_msg(nss_ctx, &nqm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: qvpn_tx_msg failed\n", nss_ctx);
+		goto done;
+	}
+
+	ret = wait_for_completion_timeout(&qvpn_pvt.complete, msecs_to_jiffies(NSS_QVPN_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: qvpn msg tx failed due to timeout\n", nss_ctx);
+		status = NSS_TX_FAILURE_SYNC_TIMEOUT;
+		goto done;
+	}
+
+	/*
+	 * Read memory barrier
+	 */
+	smp_rmb();
+
+	*resp = qvpn_pvt.resp;
+	if (*resp != NSS_QVPN_ERROR_TYPE_NONE)
+		status = NSS_TX_FAILURE;
+done:
+	up(&qvpn_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_qvpn_tx_msg_sync);
+
+/*
+ * nss_qvpn_tx_buf()
+ *	Send packet to QVPN interface owned by NSS
+ */
+nss_tx_status_t nss_qvpn_tx_buf(struct nss_ctx_instance *nss_ctx, uint32_t if_num, struct sk_buff *skb)
+{
+	if (!nss_qvpn_verify_if_num(if_num)) {
+		nss_warning("%px: tx request for interface that is not a qvpn: %u\n", nss_ctx, if_num);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	return nss_core_send_packet(nss_ctx, skb, if_num, H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+EXPORT_SYMBOL(nss_qvpn_tx_buf);
+
+/*
+ * nss_qvpn_msg_init()
+ *	Initialize nss_qvpn_msg.
+ */
+void nss_qvpn_msg_init(struct nss_qvpn_msg *ncm, uint16_t if_num, uint32_t type, uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+EXPORT_SYMBOL(nss_qvpn_msg_init);
+
+/*
+ * nss_qvpn_register_if()
+ *	Register QVPN interface.
+ */
+struct nss_ctx_instance *nss_qvpn_register_if(uint32_t if_num, nss_qvpn_callback_t qvpn_data_callback,
+					      nss_qvpn_msg_callback_t qvpn_event_callback,
+					      struct net_device *netdev, uint32_t features, void *app_ctx)
+{
+	struct nss_ctx_instance *nss_ctx = nss_qvpn_get_context();
+	uint32_t status;
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_qvpn_verify_if_num(if_num));
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, qvpn_data_callback, NULL, app_ctx, netdev, features);
+	nss_core_register_handler(nss_ctx, if_num, nss_qvpn_handler, app_ctx);
+	status = nss_core_register_msg_handler(nss_ctx, if_num, qvpn_event_callback);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to register handler for interface %d with NSS core\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	set_bit(if_num, qvpn_pvt.if_map);
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_qvpn_register_if);
+
+/*
+ * nss_unregister_qvpn_if()
+ *	Unregister QVPN interface.
+ */
+void nss_qvpn_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_qvpn_get_context();
+	uint32_t status;
+
+	nss_assert(nss_qvpn_verify_if_num(if_num));
+
+	clear_bit(if_num, qvpn_pvt.if_map);
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+	status = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Failed to unregister handler for IPsec NSS I/F:%u\n", nss_ctx, if_num);
+		return;
+	}
+
+	status = nss_core_unregister_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Failed to unregister handler for IPsec NSS I/F:%u\n", nss_ctx, if_num);
+		return;
+	}
+}
+EXPORT_SYMBOL(nss_qvpn_unregister_if);
+
+/*
+ * nss_qvpn_ifnum_with_core_id()
+ *	Append core id to QVPN interface number
+ */
+int nss_qvpn_ifnum_with_core_id(int if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_qvpn_get_context();
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	if (nss_qvpn_verify_if_num(if_num) == false) {
+		nss_info("%px: if_num: %u is not QVPN interface\n", nss_ctx, if_num);
+		return 0;
+	}
+	return NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_qvpn_ifnum_with_core_id);
+
+/*
+ * nss_qvpn_register_handler()
+ *	Intialize QVPN driver and register handler.
+ */
+void nss_qvpn_register_handler(void)
+{
+	nss_info("nss_qvpn_register_handler\n");
+	sema_init(&qvpn_pvt.sem, 1);
+	init_completion(&qvpn_pvt.complete);
+	nss_qvpn_stats_dentry_create();
+	nss_qvpn_strings_dentry_create();
+}
diff --git a/qca-nss-drv/nss_qvpn_log.c b/qca-nss-drv/nss_qvpn_log.c
new file mode 100644
index 0000000..d71c79e
--- /dev/null
+++ b/qca-nss-drv/nss_qvpn_log.c
@@ -0,0 +1,262 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_qvpn_log.c
+ *	NSS qvpn logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_qvpn_log_message_types_str
+ *	qvpn message strings
+ */
+static int8_t *nss_qvpn_log_message_types_str[NSS_QVPN_MSG_TYPE_MAX] __maybe_unused = {
+	"QVPN tunnel config",
+	"QVPN tunnel deconfig",
+	"QVPN crypto key add",
+	"QVPN crypto key delete",
+	"QVPN crypto crypto key activate",
+	"QVPN crypto key Deactivate",
+	"QVPN statistics synchronization"
+};
+
+/*
+ * nss_qvpn_log_error_response_types_str
+ *	Strings for error types for qvpn messages
+ */
+static int8_t *nss_qvpn_log_error_response_types_str[NSS_QVPN_ERROR_TYPE_MAX] __maybe_unused = {
+	"QVPN No error",
+	"QVPN Unknown message",
+	"QVPN Tunnel already configured",
+	"QVPN Invalid interface",
+	"QVPN Invalid sibling interface number",
+	"QVPN Invalid IV size",
+	"QVPN Invalid HMAC size",
+	"QVPN Invalid crypto block size",
+	"QVPN Invalid session idx size",
+	"QVPN Supported processing command count invalid",
+	"QVPN L4 protocol encapsulation is not supported",
+	"QVPN Invalid sibling interface type",
+	"QVPN Total number of commands is invalid",
+	"QVPN Entry not found",
+	"QVPN Entry not active",
+	"QVPN Entry already active",
+	"QVPN Invalid crypto index",
+	"QVPN Key info allocation failure",
+	"QVPN Invalid command profile",
+	"QVPN VPN with tail not supported"
+};
+
+/*
+ * nss_qvpn_tun_config_msg()
+ *	Log NSS QVPN configuration message.
+ */
+static void nss_qvpn_log_tun_config_msg(struct nss_qvpn_msg *ncm)
+{
+	struct nss_qvpn_tunnel_config_msg *nqtcm __maybe_unused = &ncm->msg.tunnel_config;
+	nss_trace("%px: NSS QVPN tunnel config message \n"
+		"Sibling interface: %d"
+		"Total number of commands: %d"
+		"Commands: %px"
+		"Source IP: %x:%x:%x:%x\n"
+		"Source Port: %d\n"
+		"Destination IP:  %x:%x:%x:%x\n"
+		"Destination Port: %d\n"
+		"Header Flags: %x\n"
+		"Sequence number size: %d\n"
+		"Sequence number offset: %d\n"
+		"Anti-replay algorithm: %d\n"
+		"Session ID size: %d\n"
+		"Session ID offset: %x\n"
+		"VPN header head size: %d\n"
+		"VPN header head offset: %d\n"
+		"VPN header tail size: %d\n"
+		"VPN header head: %px\n"
+		"VPN header tail: %px\n",
+		nqtcm,
+		nqtcm->sibling_if,
+		nqtcm->total_cmds,
+		nqtcm->cmd,
+		nqtcm->hdr_cfg.src_ip[0], nqtcm->hdr_cfg.src_ip[1], nqtcm->hdr_cfg.src_ip[2], nqtcm->hdr_cfg.src_ip[3],
+		nqtcm->hdr_cfg.src_port,
+		nqtcm->hdr_cfg.dst_ip[0], nqtcm->hdr_cfg.dst_ip[1], nqtcm->hdr_cfg.dst_ip[2], nqtcm->hdr_cfg.dst_ip[3],
+		nqtcm->hdr_cfg.dst_port,
+		nqtcm->hdr_cfg.hdr_flags,
+		nqtcm->hdr_cfg.seqnum_size,
+		nqtcm->hdr_cfg.seqnum_offset,
+		nqtcm->hdr_cfg.anti_replay_alg,
+		nqtcm->hdr_cfg.session_id_size,
+		nqtcm->hdr_cfg.session_id_offset,
+		nqtcm->hdr_cfg.vpn_hdr_head_size,
+		nqtcm->hdr_cfg.vpn_hdr_head_offset,
+		nqtcm->hdr_cfg.vpn_hdr_tail_size,
+		nqtcm->hdr_cfg.vpn_hdr_head,
+		nqtcm->hdr_cfg.vpn_hdr_tail);
+}
+
+/*
+ * nss_qvpn_log_tun_deconfig_msg()
+ *	Log NSS qvpn tunnel deconfigure message.
+ */
+static void nss_qvpn_log_tun_deconfig_msg(struct nss_qvpn_msg *ncm)
+{
+	nss_trace("%px: NSS QVPN deconfigure message \n", ncm);
+}
+
+/*
+ * nss_qvpn_log_crypto_key_add_msg()
+ *	Log NSS QVPN crypto key add message.
+ */
+static void nss_qvpn_log_crypto_key_add_msg(struct nss_qvpn_msg *ncm)
+{
+	struct nss_qvpn_crypto_key_add_msg *nqckam __maybe_unused = &ncm->msg.key_add;
+	nss_trace("%px: NSS QVPN crypto key add message \n"
+		"Crypto index: %d\n"
+		"Crypto session ID: %px",
+		nqckam,
+		nqckam->crypto_idx,
+		nqckam->session_id);
+}
+
+/*
+ * nss_qvpn_log_crypto_key_activate_msg()
+ *	Log NSS QVPN crypto key activate message.
+ */
+static void nss_qvpn_log_crypto_key_activate_msg(struct nss_qvpn_msg *ncm)
+{
+	struct nss_qvpn_crypto_key_activate_msg *nqckam __maybe_unused = &ncm->msg.key_activate;
+	nss_trace("%px: NSS QVPN crypto key activate message \n"
+		"Crypto index: %d\n"
+		"Crypto VPN header head: %px",
+		nqckam,
+		nqckam->crypto_idx,
+		nqckam->vpn_hdr_head);
+}
+
+/*
+ * nss_qvpn_log_crypto_key_del_msg()
+ *	Log NSS QVPN crypto key delete message.
+ */
+static void nss_qvpn_log_crypto_key_del_msg(struct nss_qvpn_msg *ncm)
+{
+	struct nss_qvpn_crypto_key_del_msg *nqckdm __maybe_unused = &ncm->msg.key_del;
+	nss_trace("%px: NSS QVPN crypto key delete message \n"
+		"Crypto index: %d\n",
+		nqckdm,
+		nqckdm->crypto_idx);
+}
+
+/*
+ * nss_qvpn_log_crypto_key_deactivate_msg()
+ *	Log NSS QVPN crypto key deactivate message.
+ */
+static void nss_qvpn_log_crypto_key_deactivate_msg(struct nss_qvpn_msg *ncm)
+{
+	struct nss_qvpn_crypto_key_del_msg *nqckdm __maybe_unused = &ncm->msg.key_del;
+	nss_trace("%px: NSS QVPN crypto key deactivate message \n"
+		"Crypto index: %d\n",
+		nqckdm,
+		nqckdm->crypto_idx);
+}
+
+/*
+ * nss_qvpn_log_verbose()
+ *	Log message contents.
+ */
+static void nss_qvpn_log_verbose(struct nss_qvpn_msg *ncm)
+{
+	switch (ncm->cm.type) {
+	case NSS_QVPN_MSG_TYPE_TUNNEL_CONFIGURE:
+		nss_qvpn_log_tun_config_msg(ncm);
+		break;
+
+	case NSS_QVPN_MSG_TYPE_TUNNEL_DECONFIGURE:
+		nss_qvpn_log_tun_deconfig_msg(ncm);
+		break;
+
+	case NSS_QVPN_MSG_TYPE_CRYPTO_KEY_ADD:
+		nss_qvpn_log_crypto_key_add_msg(ncm);
+		break;
+
+	case NSS_QVPN_MSG_TYPE_CRYPTO_KEY_ACTIVATE:
+		nss_qvpn_log_crypto_key_activate_msg(ncm);
+		break;
+
+	case NSS_QVPN_MSG_TYPE_CRYPTO_KEY_DEL:
+		nss_qvpn_log_crypto_key_del_msg(ncm);
+		break;
+
+	case NSS_QVPN_MSG_TYPE_CRYPTO_KEY_DEACTIVATE:
+		nss_qvpn_log_crypto_key_deactivate_msg(ncm);
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", ncm);
+		break;
+	}
+}
+
+/*
+ * nss_qvpn_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_qvpn_log_tx_msg(struct nss_qvpn_msg *ncm)
+{
+	if (ncm->cm.type >= NSS_QVPN_MSG_TYPE_MAX) {
+		nss_warning("%px: Invalid message type\n", ncm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ncm, ncm->cm.type, nss_qvpn_log_message_types_str[ncm->cm.type]);
+	nss_qvpn_log_verbose(ncm);
+}
+
+/*
+ * nss_qvpn_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_qvpn_log_rx_msg(struct nss_qvpn_msg *ncm)
+{
+	if (ncm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ncm);
+		return;
+	}
+
+	if (ncm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ncm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ncm, ncm->cm.type,
+			nss_qvpn_log_message_types_str[ncm->cm.type],
+			ncm->cm.response, nss_cmn_response_str[ncm->cm.response]);
+		goto verbose;
+	}
+
+	if (ncm->cm.error >= NSS_QVPN_ERROR_TYPE_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			ncm, ncm->cm.type, nss_qvpn_log_message_types_str[ncm->cm.type],
+			ncm->cm.response, nss_cmn_response_str[ncm->cm.response],
+			ncm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		ncm, ncm->cm.type, nss_qvpn_log_message_types_str[ncm->cm.type],
+		ncm->cm.response, nss_cmn_response_str[ncm->cm.response],
+		ncm->cm.error, nss_qvpn_log_error_response_types_str[ncm->cm.error]);
+
+verbose:
+	nss_qvpn_log_verbose(ncm);
+}
diff --git a/qca-nss-drv/nss_qvpn_log.h b/qca-nss-drv/nss_qvpn_log.h
new file mode 100644
index 0000000..e1dee89
--- /dev/null
+++ b/qca-nss-drv/nss_qvpn_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_QVPN_LOG_H__
+#define __NSS_QVPN_LOG_H__
+
+/*
+ * nss_qvpn_log.h
+ *	NSS QVPN Log Header File.
+ */
+
+/*
+ * nss_qvpn_log_tx_msg
+ *	Logs QVPN message that is sent to the NSS firmware.
+ */
+void nss_qvpn_log_tx_msg(struct nss_qvpn_msg *ncm);
+
+/*
+ * nss_qvpn_log_rx_msg
+ *	Logs QVPN message that is received from the NSS firmware.
+ */
+void nss_qvpn_log_rx_msg(struct nss_qvpn_msg *ncm);
+
+#endif /* __NSS_QVPN_LOG_H__ */
diff --git a/qca-nss-drv/nss_qvpn_stats.c b/qca-nss-drv/nss_qvpn_stats.c
new file mode 100644
index 0000000..4a9bdc1
--- /dev/null
+++ b/qca-nss-drv/nss_qvpn_stats.c
@@ -0,0 +1,203 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include <nss_qvpn.h>
+#include "nss_qvpn_stats.h"
+#include "nss_qvpn_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_qvpn_stats_notifier);
+
+/*
+ * Spinlock to protect qvpn statistics update/read
+ */
+DEFINE_SPINLOCK(nss_qvpn_stats_lock);
+
+uint64_t nss_qvpn_stats[NSS_MAX_NET_INTERFACES][NSS_STATS_NODE_MAX]; /* to store the qvpn statistics */
+
+/*
+ * nss_qvpn_stats_iface_type()
+ *	Return a string for each interface type.
+ */
+static const char *nss_qvpn_stats_iface_type(enum nss_dynamic_interface_type type)
+{
+	switch (type) {
+	case NSS_DYNAMIC_INTERFACE_TYPE_QVPN_INNER:
+		return "qvpn_inner";
+
+	case NSS_DYNAMIC_INTERFACE_TYPE_QVPN_OUTER:
+		return "qvpn_outer";
+
+	default:
+		return "invalid_interface";
+	}
+}
+
+/*
+ * nss_qvpn_stats_read()
+ *	Read qvpn node statiistics.
+ */
+static ssize_t nss_qvpn_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	/*
+	 * Max output lines = #stats +
+	 * few blank lines for banner printing + Number of Extra outputlines
+	 * for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_STATS_NODE_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	struct nss_ctx_instance *nss_ctx = nss_qvpn_get_context();
+	enum nss_dynamic_interface_type type;
+	unsigned long *ifmap;
+	uint64_t *stats_shadow;
+	ssize_t bytes_read = 0;
+	size_t size_wr = 0;
+	uint32_t if_num;
+	int32_t i;
+	int count;
+	char *lbuf;
+
+	ifmap = nss_qvpn_ifmap_get();
+	count = bitmap_weight(ifmap, NSS_MAX_NET_INTERFACES);
+	if (count) {
+		size_al = size_al * count;
+	}
+
+	lbuf = vzalloc(size_al);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return -ENOMEM;
+	}
+
+	stats_shadow = vzalloc(NSS_STATS_NODE_MAX * 8);
+	if (unlikely(!stats_shadow)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		vfree(lbuf);
+		return -ENOMEM;
+	}
+
+	/*
+	 * Common node stats for each QVPN dynamic interface.
+	 */
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "qvpn stats", NSS_STATS_SINGLE_CORE);
+	for_each_set_bit(if_num, ifmap, NSS_MAX_NET_INTERFACES) {
+
+		type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+		if ((type != NSS_DYNAMIC_INTERFACE_TYPE_QVPN_INNER) &&
+			(type != NSS_DYNAMIC_INTERFACE_TYPE_QVPN_OUTER)) {
+			continue;
+		}
+
+		spin_lock_bh(&nss_qvpn_stats_lock);
+		for (i = 0; i < NSS_STATS_NODE_MAX; i++) {
+			stats_shadow[i] = nss_qvpn_stats[if_num][i];
+		}
+		spin_unlock_bh(&nss_qvpn_stats_lock);
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n%s if_num:%03u\n",
+					nss_qvpn_stats_iface_type(type), if_num);
+		size_wr += nss_stats_print("qvpn", NULL, NSS_STATS_SINGLE_INSTANCE, nss_qvpn_strings_stats,
+						stats_shadow, NSS_STATS_NODE_MAX, lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	vfree(lbuf);
+	vfree(stats_shadow);
+	return bytes_read;
+}
+
+/*
+ * nss_qvpn_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(qvpn)
+
+/*
+ * nss_qvpn_stats_tunnel_sync
+ *	Update qvpn interface statistics.
+ */
+void nss_qvpn_stats_tunnel_sync(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm)
+{
+	struct nss_qvpn_msg *ndcm = (struct nss_qvpn_msg *)ncm;
+	struct nss_qvpn_stats_sync_msg  *msg_stats = &ndcm->msg.stats;
+
+	spin_lock_bh(&nss_qvpn_stats_lock);
+
+	/*
+	 * Update common node stats
+	 */
+	nss_qvpn_stats[ncm->interface][NSS_STATS_NODE_RX_PKTS] += msg_stats->node_stats.rx_packets;
+	nss_qvpn_stats[ncm->interface][NSS_STATS_NODE_RX_BYTES] += msg_stats->node_stats.rx_bytes;
+	nss_qvpn_stats[ncm->interface][NSS_STATS_NODE_RX_QUEUE_0_DROPPED] += msg_stats->node_stats.rx_dropped[0];
+	nss_qvpn_stats[ncm->interface][NSS_STATS_NODE_RX_QUEUE_1_DROPPED] += msg_stats->node_stats.rx_dropped[1];
+	nss_qvpn_stats[ncm->interface][NSS_STATS_NODE_RX_QUEUE_2_DROPPED] += msg_stats->node_stats.rx_dropped[2];
+	nss_qvpn_stats[ncm->interface][NSS_STATS_NODE_RX_QUEUE_3_DROPPED] += msg_stats->node_stats.rx_dropped[3];
+
+	nss_qvpn_stats[ncm->interface][NSS_STATS_NODE_TX_PKTS] += msg_stats->node_stats.tx_packets;
+	nss_qvpn_stats[ncm->interface][NSS_STATS_NODE_TX_BYTES] += msg_stats->node_stats.tx_bytes;
+
+	spin_unlock_bh(&nss_qvpn_stats_lock);
+}
+
+/*
+ * nss_qvpn_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_qvpn_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_qvpn_stats_notification qvpn_stats;
+
+	spin_lock_bh(&nss_qvpn_stats_lock);
+	qvpn_stats.core_id = nss_ctx->id;
+	qvpn_stats.if_num = if_num;
+	memcpy(qvpn_stats.stats_ctx, nss_qvpn_stats[if_num], sizeof(qvpn_stats.stats_ctx));
+	spin_unlock_bh(&nss_qvpn_stats_lock);
+
+	atomic_notifier_call_chain(&nss_qvpn_stats_notifier, NSS_STATS_EVENT_NOTIFY, &qvpn_stats);
+}
+
+/*
+ * nss_qvpn_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_qvpn_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_qvpn_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_qvpn_stats_unregister_notifier);
+
+/*
+ * nss_qvpn_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_qvpn_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_qvpn_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_qvpn_stats_register_notifier);
+
+/*
+ * nss_qvpn_stats_dentry_create()
+ *	Create QVPN statistics debug entry.
+ */
+void nss_qvpn_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("qvpn", &nss_qvpn_stats_ops);
+}
diff --git a/qca-nss-drv/nss_qvpn_stats.h b/qca-nss-drv/nss_qvpn_stats.h
new file mode 100644
index 0000000..74bbe11
--- /dev/null
+++ b/qca-nss-drv/nss_qvpn_stats.h
@@ -0,0 +1,24 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef _NSS_QVPN_STATS_H_
+#define _NSS_QVPN_STATS_H_
+
+extern void nss_qvpn_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_qvpn_stats_tunnel_sync(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm);
+extern void nss_qvpn_stats_dentry_create(void);
+
+#endif /* _NSS_QVPN_STATS_H_ */
diff --git a/qca-nss-drv/nss_qvpn_strings.c b/qca-nss-drv/nss_qvpn_strings.c
new file mode 100644
index 0000000..2af34aa
--- /dev/null
+++ b/qca-nss-drv/nss_qvpn_strings.c
@@ -0,0 +1,60 @@
+/*
+ *****************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *****************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_qvpn_strings.h"
+
+/*
+ * nss_qvpn_strings_stats
+ *	qvpn statistics strings.
+ */
+struct nss_stats_info nss_qvpn_strings_stats[NSS_STATS_NODE_MAX] = {
+	{"rx_pkts",                     NSS_STATS_TYPE_COMMON},
+	{"rx_byts",                     NSS_STATS_TYPE_COMMON},
+	{"tx_pkts",                     NSS_STATS_TYPE_COMMON},
+	{"tx_byts",                     NSS_STATS_TYPE_COMMON},
+	{"rx_queue[0]_drops",           NSS_STATS_TYPE_DROP},
+	{"rx_queue[1]_drops",           NSS_STATS_TYPE_DROP},
+	{"rx_queue[2]_drops",           NSS_STATS_TYPE_DROP},
+	{"rx_queue[3]_drops",           NSS_STATS_TYPE_DROP}
+};
+
+/*
+ * nss_qvpn_strings_read()
+ *	Read qvpn statistics names
+ */
+static ssize_t nss_qvpn_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_qvpn_strings_stats, NSS_STATS_NODE_MAX);
+}
+
+/*
+ * nss_qvpn_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(qvpn);
+
+/*
+ * nss_qvpn_strings_dentry_create()
+ *	Create qvpn statistics strings debug entry.
+ */
+void nss_qvpn_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("qvpn", &nss_qvpn_strings_ops);
+}
diff --git a/qca-nss-drv/nss_qvpn_strings.h b/qca-nss-drv/nss_qvpn_strings.h
new file mode 100644
index 0000000..4b874d8
--- /dev/null
+++ b/qca-nss-drv/nss_qvpn_strings.h
@@ -0,0 +1,27 @@
+/*
+ ****************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ****************************************************************************
+ */
+
+#ifndef __NSS_QVPN_STRINGS_H
+#define __NSS_QVPN_STRINGS_H
+
+#include "nss_qvpn_stats.h"
+
+extern struct nss_stats_info nss_qvpn_strings_stats[NSS_STATS_NODE_MAX];
+extern void nss_qvpn_strings_dentry_create(void);
+
+#endif /* __NSS_QVPN_STRINGS_H */
diff --git a/qca-nss-drv/nss_rmnet_rx.c b/qca-nss-drv/nss_rmnet_rx.c
new file mode 100644
index 0000000..c77ef3f
--- /dev/null
+++ b/qca-nss-drv/nss_rmnet_rx.c
@@ -0,0 +1,781 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_rmnet_rx.c
+ *	NSS rmnet receive handler APIs
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_rmnet_rx_stats.h"
+#include <net/arp.h>
+
+#define NSS_RMNET_RX_TX_TIMEOUT			3000 /* 3 Seconds */
+#define NSS_RMNET_RX_GET_INDEX(if_num)	(if_num - NSS_DYNAMIC_IF_START)
+
+/*
+ * Spinlock to protect the global data structure rmnet handle.
+ */
+DEFINE_SPINLOCK(nss_rmnet_rx_lock);
+
+extern int nss_ctl_redirect;
+
+/*
+ * Data structure that holds theinterface context.
+ */
+struct nss_rmnet_rx_handle *rmnet_rx_handle[NSS_MAX_DYNAMIC_INTERFACES];
+
+/*
+ * nss_rmnet_rx_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+bool nss_rmnet_rx_verify_if_num(uint32_t if_num)
+{
+	enum nss_dynamic_interface_type type = nss_dynamic_interface_get_type(nss_rmnet_rx_get_context(), if_num);
+
+	return type == NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_N2H
+		|| type == NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_H2N;
+}
+
+/*
+ * nss_rmnet_rx_msg_handler()
+ *	Handle msg responses from the FW on interfaces
+ */
+static void nss_rmnet_rx_msg_handler(struct nss_ctx_instance *nss_ctx,
+					struct nss_cmn_msg *ncm,
+					void *app_data)
+{
+	struct nss_rmnet_rx_msg *nvim = (struct nss_rmnet_rx_msg *)ncm;
+	int32_t if_num;
+
+	nss_rmnet_rx_msg_callback_t cb;
+	struct nss_rmnet_rx_handle *handle = NULL;
+
+	/*
+	 * Sanity check the message type
+	 */
+	if (ncm->type > NSS_RMNET_RX_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return;
+	}
+
+	/*
+	 * Messages value that are within the base class are handled by the base class.
+	 */
+	if (ncm->type < NSS_IF_MAX_MSG_TYPES) {
+		return nss_if_msg_handler(nss_ctx, ncm, app_data);
+	}
+
+	if (!nss_rmnet_rx_verify_if_num(ncm->interface)) {
+		nss_warning("%px: response for another interface: %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	if_num = NSS_RMNET_RX_GET_INDEX(ncm->interface);
+
+	spin_lock_bh(&nss_rmnet_rx_lock);
+	if (!rmnet_rx_handle[if_num]) {
+		spin_unlock_bh(&nss_rmnet_rx_lock);
+		nss_warning("%px: rmnet_rx handle is NULL\n", nss_ctx);
+		return;
+	}
+
+	handle = rmnet_rx_handle[if_num];
+	spin_unlock_bh(&nss_rmnet_rx_lock);
+
+	switch (nvim->cm.type) {
+	case NSS_RMNET_RX_STATS_SYNC_MSG:
+		nss_rmnet_rx_stats_sync(handle, &nvim->msg.stats, ncm->interface);
+		break;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, IPv4 sends all notify messages
+	 * to the same callback/app_data.
+	 *
+	 * TODO: RMNet driver does not provide a registration for a notifier callback.
+	 * Since dynamic interface are allocated on both cores and since the array for
+	 * registered callback is not core specific, we call the Wi-Fi callback
+	 * inappropriately. Disable the callback locally until we have per-core
+	 * callback registrations.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)NULL;
+		ncm->app_data = (nss_ptr_t)nss_ctx->subsys_dp_register[ncm->interface].ndev;
+	}
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * Callback
+	 */
+	cb = (nss_rmnet_rx_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, ncm);
+}
+
+/*
+ * nss_rmnet_rx_callback
+ *	Callback to handle the completion of NSS ->HLOS messages.
+ */
+static void nss_rmnet_rx_callback(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_rmnet_rx_handle *handle = (struct nss_rmnet_rx_handle *)app_data;
+	struct nss_rmnet_rx_pvt *nvip = handle->pvt;
+
+	if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("%px: rmnet_rx Error response %d\n", handle->nss_ctx, ncm->response);
+		nvip->response = NSS_TX_FAILURE;
+		complete(&nvip->complete);
+		return;
+	}
+
+	nvip->response = NSS_TX_SUCCESS;
+	complete(&nvip->complete);
+}
+
+/*
+ * nss_rmnet_rx_tx_msg_sync
+ *	Send a message from HLOS to NSS synchronously.
+ */
+static nss_tx_status_t nss_rmnet_rx_tx_msg_sync(struct nss_rmnet_rx_handle *handle,
+						struct nss_rmnet_rx_msg *nvim)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+	struct nss_rmnet_rx_pvt *nwip = handle->pvt;
+	struct nss_ctx_instance *nss_ctx = handle->nss_ctx;
+
+	down(&nwip->sem);
+
+	status = nss_rmnet_rx_tx_msg(nss_ctx, nvim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_rmnet_rx_msg failed\n", nss_ctx);
+		up(&nwip->sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&nwip->complete,
+						msecs_to_jiffies(NSS_RMNET_RX_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: rmnet_rx tx failed due to timeout\n", nss_ctx);
+		nwip->response = NSS_TX_FAILURE;
+	}
+
+	status = nwip->response;
+	up(&nwip->sem);
+
+	return status;
+}
+
+/*
+ * nss_rmnet_rx_msg_init()
+ *	Initialize virt specific message structure.
+ */
+static void nss_rmnet_rx_msg_init(struct nss_rmnet_rx_msg *nvim,
+					uint16_t if_num,
+					uint32_t type,
+					uint32_t len,
+					nss_rmnet_rx_msg_callback_t cb,
+					struct nss_rmnet_rx_handle *app_data)
+{
+	nss_cmn_msg_init(&nvim->cm, if_num, type, len, (void *)cb, (void *)app_data);
+}
+
+/*
+ * nss_rmnet_rx_handle_destroy_sync()
+ *	Destroy the virt handle either due to request from user or due to error, synchronously.
+ */
+static int nss_rmnet_rx_handle_destroy_sync(struct nss_rmnet_rx_handle *handle)
+{
+	nss_tx_status_t status;
+	int32_t if_num_n2h = handle->if_num_n2h;
+	int32_t if_num_h2n = handle->if_num_h2n;
+	int32_t index_n2h;
+	int32_t index_h2n;
+
+	if (!nss_rmnet_rx_verify_if_num(if_num_n2h) || !nss_rmnet_rx_verify_if_num(if_num_h2n)) {
+		nss_warning("%px: bad interface numbers %d %d\n", handle->nss_ctx, if_num_n2h, if_num_h2n);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	index_n2h = NSS_RMNET_RX_GET_INDEX(if_num_n2h);
+	index_h2n = NSS_RMNET_RX_GET_INDEX(if_num_h2n);
+
+	status = nss_dynamic_interface_dealloc_node(if_num_n2h, NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_N2H);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Dynamic interface destroy failed status %d\n", handle->nss_ctx, status);
+		return status;
+	}
+
+	status = nss_dynamic_interface_dealloc_node(if_num_h2n, NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_H2N);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Dynamic interface destroy failed status %d\n", handle->nss_ctx, status);
+		return status;
+	}
+
+	spin_lock_bh(&nss_rmnet_rx_lock);
+	rmnet_rx_handle[index_n2h] = NULL;
+	rmnet_rx_handle[index_h2n] = NULL;
+	spin_unlock_bh(&nss_rmnet_rx_lock);
+
+	kfree(handle->pvt);
+	kfree(handle);
+
+	return status;
+}
+
+/*
+ * nss_rmnet_rx_handle_create_sync()
+ *	Initialize virt handle which holds the if_num and stats per interface.
+ */
+static struct nss_rmnet_rx_handle *nss_rmnet_rx_handle_create_sync(struct nss_ctx_instance *nss_ctx, int32_t if_num_n2h, int32_t if_num_h2n, int32_t *cmd_rsp)
+{
+	int32_t index_n2h;
+	int32_t index_h2n;
+	struct nss_rmnet_rx_handle *handle;
+
+	if (!nss_rmnet_rx_verify_if_num(if_num_n2h) || !nss_rmnet_rx_verify_if_num(if_num_h2n)) {
+		nss_warning("%px: bad interface numbers %d %d\n", nss_ctx, if_num_n2h, if_num_h2n);
+		return NULL;
+	}
+
+	index_n2h = NSS_RMNET_RX_GET_INDEX(if_num_n2h);
+	index_h2n = NSS_RMNET_RX_GET_INDEX(if_num_h2n);
+
+	handle = (struct nss_rmnet_rx_handle *)kzalloc(sizeof(struct nss_rmnet_rx_handle),
+									GFP_KERNEL);
+	if (!handle) {
+		nss_warning("%px: handle memory alloc failed\n", nss_ctx);
+		*cmd_rsp = NSS_RMNET_RX_ALLOC_FAILURE;
+		goto error1;
+	}
+
+	handle->nss_ctx = nss_ctx;
+	handle->if_num_n2h = if_num_n2h;
+	handle->if_num_h2n = if_num_h2n;
+	handle->pvt = (struct nss_rmnet_rx_pvt *)kzalloc(sizeof(struct nss_rmnet_rx_pvt),
+								GFP_KERNEL);
+	if (!handle->pvt) {
+		nss_warning("%px: failure allocating memory for nss_rmnet_rx_pvt\n", nss_ctx);
+		*cmd_rsp = NSS_RMNET_RX_ALLOC_FAILURE;
+		goto error2;
+	}
+
+	handle->stats_n2h = (uint64_t *)kzalloc(sizeof(uint64_t) * NSS_RMNET_RX_STATS_MAX,
+								GFP_KERNEL);
+	if (!handle->stats_n2h) {
+		nss_warning("%px: failure allocating memory for N2H stats\n", nss_ctx);
+		*cmd_rsp = NSS_RMNET_RX_ALLOC_FAILURE;
+		goto error3;
+	}
+
+	handle->stats_h2n = (uint64_t *)kzalloc(sizeof(uint64_t) * NSS_RMNET_RX_STATS_MAX,
+								GFP_KERNEL);
+	if (!handle->stats_h2n) {
+		nss_warning("%px: failure allocating memory for H2N stats\n", nss_ctx);
+		*cmd_rsp = NSS_RMNET_RX_ALLOC_FAILURE;
+		goto error4;
+	}
+
+	handle->cb = NULL;
+	handle->app_data = NULL;
+
+	spin_lock_bh(&nss_rmnet_rx_lock);
+	rmnet_rx_handle[index_n2h] = handle;
+	rmnet_rx_handle[index_h2n] = handle;
+	spin_unlock_bh(&nss_rmnet_rx_lock);
+
+	*cmd_rsp = NSS_RMNET_RX_SUCCESS;
+
+	return handle;
+
+error4:
+	kfree(handle->stats_n2h);
+error3:
+	kfree(handle->pvt);
+error2:
+	kfree(handle);
+error1:
+	return NULL;
+}
+
+/*
+ * nss_rmnet_rx_register_handler_sync()
+ *	register msg handler for interface and initialize semaphore and completion.
+ */
+static uint32_t nss_rmnet_rx_register_handler_sync(struct nss_ctx_instance *nss_ctx, struct nss_rmnet_rx_handle *handle)
+{
+	uint32_t ret;
+	struct nss_rmnet_rx_pvt *nvip = NULL;
+	int32_t if_num_n2h = handle->if_num_n2h;
+	int32_t if_num_h2n = handle->if_num_h2n;
+
+	ret = nss_core_register_handler(nss_ctx, if_num_n2h, nss_rmnet_rx_msg_handler, NULL);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Failed to register message handler for redir_n2h interface %d\n", nss_ctx, if_num_n2h);
+		return NSS_RMNET_RX_REG_FAILURE;
+	}
+
+	ret = nss_core_register_handler(nss_ctx, if_num_h2n, nss_rmnet_rx_msg_handler, NULL);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_core_unregister_handler(nss_ctx, if_num_n2h);
+		nss_warning("%px: Failed to register message handler for redir_h2n interface %d\n", nss_ctx, if_num_h2n);
+		return NSS_RMNET_RX_REG_FAILURE;
+	}
+
+	nvip = handle->pvt;
+	if (!nvip->sem_init_done) {
+		sema_init(&nvip->sem, 1);
+		init_completion(&nvip->complete);
+		nvip->sem_init_done = 1;
+	}
+
+	nss_rmnet_rx_stats_dentry_create();
+	return NSS_RMNET_RX_SUCCESS;
+}
+
+/*
+ * nss_rmnet_rx_destroy_sync()
+ *	Destroy the virt interface associated with the interface number, synchronously.
+ */
+nss_tx_status_t nss_rmnet_rx_destroy_sync(struct nss_rmnet_rx_handle *handle)
+{
+	nss_tx_status_t status;
+	struct net_device *dev;
+	int32_t if_num_n2h;
+	int32_t if_num_h2n;
+	struct nss_ctx_instance *nss_ctx;
+	uint32_t ret;
+
+	if (!handle) {
+		nss_warning("handle is NULL\n");
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	if_num_n2h = handle->if_num_n2h;
+	if_num_h2n = handle->if_num_h2n;
+	nss_ctx = handle->nss_ctx;
+
+	if (unlikely(nss_ctx->state != NSS_CORE_STATE_INITIALIZED)) {
+		nss_warning("%px: Interface could not be destroyed as core not ready\n", nss_ctx);
+		return NSS_TX_FAILURE_NOT_READY;
+	}
+
+	spin_lock_bh(&nss_top_main.lock);
+	if (!nss_ctx->subsys_dp_register[if_num_n2h].ndev || !nss_ctx->subsys_dp_register[if_num_h2n].ndev) {
+		spin_unlock_bh(&nss_top_main.lock);
+		nss_warning("%px: Unregister virt interface %d %d: no context\n", nss_ctx, if_num_n2h, if_num_h2n);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	dev = nss_ctx->subsys_dp_register[if_num_n2h].ndev;
+	nss_assert(dev == nss_ctx->subsys_dp_register[if_num_h2n].ndev);
+	nss_core_unregister_subsys_dp(nss_ctx, if_num_n2h);
+	nss_core_unregister_subsys_dp(nss_ctx, if_num_h2n);
+	spin_unlock_bh(&nss_top_main.lock);
+	dev_put(dev);
+
+	status = nss_rmnet_rx_handle_destroy_sync(handle);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: handle destroy failed for if_num_n2h %d and if_num_h2n %d\n", nss_ctx, if_num_n2h, if_num_h2n);
+		return NSS_TX_FAILURE;
+	}
+
+	ret = nss_core_unregister_handler(nss_ctx, if_num_n2h);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to unregister handler for redir_n2h interface %d with NSS core\n", nss_ctx, if_num_n2h);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	ret = nss_core_unregister_handler(nss_ctx, if_num_h2n);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to unregister handler for redir_h2n interface %d with NSS core\n", nss_ctx, if_num_h2n);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	return status;
+}
+EXPORT_SYMBOL(nss_rmnet_rx_destroy_sync);
+
+/*
+ * nss_rmnet_rx_create_sync_nexthop()
+ *	Create redir_n2h and redir_h2n interfaces, synchronously and associate it with same netdev.
+ */
+struct nss_rmnet_rx_handle *nss_rmnet_rx_create_sync_nexthop(struct net_device *netdev, uint32_t nexthop_n2h, uint32_t nexthop_h2n)
+{
+	struct nss_ctx_instance *nss_ctx = nss_rmnet_rx_get_context();
+	struct nss_rmnet_rx_msg nvim;
+	struct nss_rmnet_rx_config_msg *nvcm;
+	uint32_t ret;
+	struct nss_rmnet_rx_handle *handle = NULL;
+	int32_t if_num_n2h, if_num_h2n;
+
+	if (unlikely(nss_ctx->state != NSS_CORE_STATE_INITIALIZED)) {
+		nss_warning("%px: Interface could not be created as core not ready\n", nss_ctx);
+		return NULL;
+	}
+
+	if_num_n2h = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_N2H);
+	if (if_num_n2h < 0) {
+		nss_warning("%px: failure allocating redir_n2h\n", nss_ctx);
+		return NULL;
+	}
+
+	if_num_h2n = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_H2N);
+	if (if_num_h2n < 0) {
+		nss_warning("%px: failure allocating redir_h2n\n", nss_ctx);
+		nss_dynamic_interface_dealloc_node(if_num_n2h, NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_N2H);
+		return NULL;
+	}
+
+	handle = nss_rmnet_rx_handle_create_sync(nss_ctx, if_num_n2h, if_num_h2n, &ret);
+	if (!handle) {
+		nss_warning("%px: rmnet_rx handle creation failed ret %d\n", nss_ctx, ret);
+		nss_dynamic_interface_dealloc_node(if_num_n2h, NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_N2H);
+		nss_dynamic_interface_dealloc_node(if_num_h2n, NSS_DYNAMIC_INTERFACE_TYPE_RMNET_RX_H2N);
+		return NULL;
+	}
+
+	/*
+	 * Initializes the semaphore and also sets the msg handler for if_num.
+	 */
+	ret = nss_rmnet_rx_register_handler_sync(nss_ctx, handle);
+	if (ret != NSS_RMNET_RX_SUCCESS) {
+		nss_warning("%px: Registration handler failed reason: %d\n", nss_ctx, ret);
+		goto error1;
+	}
+
+	nss_rmnet_rx_msg_init(&nvim, handle->if_num_n2h, NSS_RMNET_RX_TX_CONFIG_MSG,
+				sizeof(struct nss_rmnet_rx_config_msg), nss_rmnet_rx_callback, handle);
+
+	nvcm = &nvim.msg.if_config;
+	nvcm->flags = 0;
+	nvcm->sibling = if_num_h2n;
+	nvcm->nexthop = nexthop_n2h;
+	nvcm->no_channel = 0;
+
+	ret = nss_rmnet_rx_tx_msg_sync(handle, &nvim);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_rmnet_rx_tx_msg_sync failed %u\n", nss_ctx, ret);
+		goto error2;
+	}
+
+	nvim.cm.interface = if_num_h2n;
+	nvcm->sibling = if_num_n2h;
+	nvcm->nexthop = nexthop_h2n;
+	nvcm->no_channel = NSS_RMNET_RX_CHANNEL_MAX;
+
+	ret = nss_rmnet_rx_tx_msg_sync(handle, &nvim);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_rmnet_rx_tx_msg_sync failed %u\n", nss_ctx, ret);
+		goto error2;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, (uint32_t)if_num_n2h, NULL, NULL, NULL, netdev, 0);
+	nss_core_register_subsys_dp(nss_ctx, (uint32_t)if_num_h2n, NULL, NULL, NULL, netdev, 0);
+
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num_n2h, NSS_RMNET_RX_DP_N2H);
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num_h2n, NSS_RMNET_RX_DP_H2N);
+
+	/*
+	 * Hold a reference to the net_device
+	 */
+	dev_hold(netdev);
+
+	/*
+	 * The context returned is the handle interface # which contains all the info related to
+	 * the interface if_num.
+	 */
+
+	return handle;
+
+error2:
+	nss_core_unregister_handler(nss_ctx, if_num_n2h);
+	nss_core_unregister_handler(nss_ctx, if_num_h2n);
+
+error1:
+	nss_rmnet_rx_handle_destroy_sync(handle);
+	return NULL;
+}
+EXPORT_SYMBOL(nss_rmnet_rx_create_sync_nexthop);
+
+/*
+ * nss_rmnet_rx_create()
+ *	Create rmnet_n2h and rmnet_h2n interfaces with generic next hops and associate it with same netdev.
+ *
+ * When rmnet and eth_rx is running at the same core, we directly send packets to eth_rx node.
+ * When they are running at different cores, the packets needs to arrive eth_rx through C2C.
+ */
+struct nss_rmnet_rx_handle *nss_rmnet_rx_create(struct net_device *netdev)
+{
+	uint32_t nexthop_n2h = NSS_N2H_INTERFACE;
+	uint32_t nexthop_h2n = NSS_C2C_TX_INTERFACE;
+
+	if (nss_top_main.rmnet_rx_handler_id == 0) {
+		nexthop_h2n = NSS_ETH_RX_INTERFACE;
+	}
+
+
+	return nss_rmnet_rx_create_sync_nexthop(netdev, nexthop_n2h, nexthop_h2n);
+}
+EXPORT_SYMBOL(nss_rmnet_rx_create);
+
+/*
+ * nss_rmnet_rx_tx_buf()
+ *	HLOS interface has received a packet which we redirect to the NSS, if appropriate to do so.
+ */
+nss_tx_status_t nss_rmnet_rx_tx_buf(struct nss_rmnet_rx_handle *handle,
+						struct sk_buff *skb)
+{
+	int32_t if_num = handle->if_num_h2n;
+	struct nss_ctx_instance *nss_ctx = handle->nss_ctx;
+	int cpu = 0;
+
+	if (unlikely(nss_ctl_redirect == 0)) {
+		return NSS_TX_FAILURE_NOT_ENABLED;
+	}
+
+	if (unlikely(skb->vlan_tci)) {
+		return NSS_TX_FAILURE_NOT_SUPPORTED;
+	}
+
+	if (!nss_rmnet_rx_verify_if_num(if_num)) {
+		nss_warning("%px: bad interface number %d\n", nss_ctx, if_num);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	nss_trace("%px: RmnetRx packet, if_num:%d, skb:%px", nss_ctx, if_num, skb);
+
+	/*
+	 * Sanity check the SKB to ensure that it's suitable for us
+	 */
+	if (unlikely(skb->len <= ETH_HLEN)) {
+		nss_warning("%px: Rmnet Rx packet: %px too short", nss_ctx, skb);
+		return NSS_TX_FAILURE_TOO_SHORT;
+	}
+
+	/*
+	 * set skb queue mapping
+	 */
+	cpu = get_cpu();
+	put_cpu();
+	skb_set_queue_mapping(skb, cpu);
+
+	return nss_core_send_packet(nss_ctx, skb, if_num, H2N_BIT_FLAG_VIRTUAL_BUFFER);
+}
+EXPORT_SYMBOL(nss_rmnet_rx_tx_buf);
+
+/*
+ * nss_rmnet_rx_tx_msg()
+ */
+nss_tx_status_t nss_rmnet_rx_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_rmnet_rx_msg *nvim)
+{
+	struct nss_cmn_msg *ncm = &nvim->cm;
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!nss_rmnet_rx_verify_if_num(ncm->interface)) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_RMNET_RX_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, nvim, sizeof(*nvim), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_rmnet_rx_tx_msg);
+
+/*
+ * nss_rmnet_rx_xmit_callback_unregister()
+ *	Unregister interface xmit callback.
+ */
+void nss_rmnet_rx_xmit_callback_unregister(struct nss_rmnet_rx_handle *handle)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_subsystem_dataplane_register *reg;
+
+	if (!handle) {
+		nss_warning("handle is NULL\n");
+		return;
+	}
+
+	nss_ctx = handle->nss_ctx;
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_rmnet_rx_verify_if_num(handle->if_num_n2h)) {
+		nss_warning("if_num is invalid\n");
+		return;
+	}
+
+	reg = &nss_ctx->subsys_dp_register[handle->if_num_n2h];
+	reg->xmit_cb = NULL;
+}
+EXPORT_SYMBOL(nss_rmnet_rx_xmit_callback_unregister);
+
+/*
+ * nss_rmnet_rx_xmit_callback_register()
+ *	Register interface xmit callback.
+ */
+void nss_rmnet_rx_xmit_callback_register(struct nss_rmnet_rx_handle *handle,
+				nss_rmnet_rx_xmit_callback_t cb)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_subsystem_dataplane_register *reg;
+
+	if (!handle) {
+		nss_warning("handle is NULL\n");
+		return;
+	}
+
+	nss_ctx = handle->nss_ctx;
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_rmnet_rx_verify_if_num(handle->if_num_n2h)) {
+		nss_warning("if_num is invalid\n");
+		return;
+	}
+
+	reg = &nss_ctx->subsys_dp_register[handle->if_num_n2h];
+	reg->xmit_cb = cb;
+}
+EXPORT_SYMBOL(nss_rmnet_rx_xmit_callback_register);
+
+/*
+ * nss_rmnet_rx_unregister()
+ */
+void nss_rmnet_rx_unregister(struct nss_rmnet_rx_handle *handle)
+{
+	struct nss_ctx_instance *nss_ctx;
+	int32_t if_num;
+
+	if (!handle) {
+		nss_warning("handle is NULL\n");
+		return;
+	}
+
+	nss_ctx = handle->nss_ctx;
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_rmnet_rx_verify_if_num(handle->if_num_n2h)) {
+		nss_warning("if_num is invalid\n");
+		return;
+	}
+
+	if_num = handle->if_num_n2h;
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_rmnet_rx_unregister);
+
+/*
+ * nss_rmnet_rx_register()
+ */
+void nss_rmnet_rx_register(struct nss_rmnet_rx_handle *handle,
+				nss_rmnet_rx_data_callback_t data_callback,
+				struct net_device *netdev)
+{
+	struct nss_ctx_instance *nss_ctx;
+	int32_t if_num;
+
+	if (!handle) {
+		nss_warning("handle is NULL\n");
+		return;
+	}
+
+	nss_ctx = handle->nss_ctx;
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_rmnet_rx_verify_if_num(handle->if_num_n2h)) {
+		nss_warning("if_num is invalid\n");
+		return;
+	}
+
+	if_num = handle->if_num_n2h;
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, data_callback, NULL, NULL, netdev, (uint32_t)netdev->features);
+}
+EXPORT_SYMBOL(nss_rmnet_rx_register);
+
+/*
+ * nss_rmnet_rx_get_ifnum_with_core_id()
+ *	Append core id to rmnet interface number
+ */
+int32_t nss_rmnet_rx_get_ifnum_with_core_id(int32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_rmnet_rx_get_context();
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	if (nss_rmnet_rx_verify_if_num(if_num) == false) {
+		nss_info("%px: if_num: %u is not RMNET interface\n", nss_ctx, if_num);
+		return -1;
+	}
+	return NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_rmnet_rx_get_ifnum_with_core_id);
+
+/*
+ * nss_rmnet_rx_get_ifnum()
+ *	Return rmnet interface number with core ID
+ */
+int32_t nss_rmnet_rx_get_ifnum(struct net_device *dev)
+{
+	int32_t ifnum = nss_cmn_get_interface_number_by_dev(dev);
+	return nss_rmnet_rx_get_ifnum_with_core_id(ifnum);
+}
+EXPORT_SYMBOL(nss_rmnet_rx_get_ifnum);
+
+/*
+ * nss_rmnet_rx_get_interface_num()
+ *	Get interface number for an interface
+ */
+int32_t nss_rmnet_rx_get_interface_num(struct nss_rmnet_rx_handle *handle)
+{
+	if (!handle) {
+		nss_warning("rmnet_rx handle is NULL\n");
+		return -1;
+	}
+
+	/*
+	 * Return if_num_n2h whose datapath type is 0.
+	 */
+	return handle->if_num_n2h;
+}
+EXPORT_SYMBOL(nss_rmnet_rx_get_interface_num);
+
+/*
+ * nss_rmnet_rx_get_context()
+ */
+struct nss_ctx_instance *nss_rmnet_rx_get_context(void)
+{
+	return &nss_top_main.nss[nss_top_main.rmnet_rx_handler_id];
+}
+EXPORT_SYMBOL(nss_rmnet_rx_get_context);
diff --git a/qca-nss-drv/nss_rmnet_rx_stats.c b/qca-nss-drv/nss_rmnet_rx_stats.c
new file mode 100644
index 0000000..efbcaff
--- /dev/null
+++ b/qca-nss-drv/nss_rmnet_rx_stats.c
@@ -0,0 +1,209 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_rmnet_rx_stats.h"
+
+/*
+ * Data structure that holds the virtual interface context.
+ */
+extern struct nss_rmnet_rx_handle *rmnet_rx_handle[];
+
+/*
+ * Spinlock to protect the global data structure virt_handle.
+ */
+extern spinlock_t nss_rmnet_rx_lock;
+
+/*
+ * nss_rmnet_rx_stats_str
+ *	rmnet_rx interface stats strings
+ */
+struct nss_stats_info nss_rmnet_rx_stats_str[NSS_RMNET_RX_STATS_MAX] = {
+	{"rx_packets"			, NSS_STATS_TYPE_COMMON},
+	{"rx_bytes"			, NSS_STATS_TYPE_COMMON},
+	{"tx_packets"			, NSS_STATS_TYPE_COMMON},
+	{"tx_bytes"			, NSS_STATS_TYPE_COMMON},
+	{"rx_queue_0_dropped"		, NSS_STATS_TYPE_DROP},
+	{"rx_queue_1_dropped"		, NSS_STATS_TYPE_DROP},
+	{"rx_queue_2_dropped"		, NSS_STATS_TYPE_DROP},
+	{"rx_queue_3_dropped"		, NSS_STATS_TYPE_DROP},
+	{"enqueue failed"		, NSS_STATS_TYPE_DROP},
+	{"no available channel"		, NSS_STATS_TYPE_SPECIAL},
+	{"linear pbuf count"		, NSS_STATS_TYPE_SPECIAL},
+	{"no pbuf to linear"		, NSS_STATS_TYPE_SPECIAL},
+	{"no enough room"		, NSS_STATS_TYPE_SPECIAL},
+	{"channel[0]"			, NSS_STATS_TYPE_SPECIAL},
+	{"channel[1]"			, NSS_STATS_TYPE_SPECIAL},
+	{"channel[2]"			, NSS_STATS_TYPE_SPECIAL},
+	{"channel[3]"			, NSS_STATS_TYPE_SPECIAL},
+	{"channel[4]"			, NSS_STATS_TYPE_SPECIAL},
+	{"channel[5]"			, NSS_STATS_TYPE_SPECIAL},
+	{"channel[6]"			, NSS_STATS_TYPE_SPECIAL},
+	{"channel[7]"			, NSS_STATS_TYPE_SPECIAL},
+	{"channel[8]"			, NSS_STATS_TYPE_SPECIAL},
+	{"channel[9]"			, NSS_STATS_TYPE_SPECIAL},
+	{"channel[10]"			, NSS_STATS_TYPE_SPECIAL},
+	{"channel[11]"			, NSS_STATS_TYPE_SPECIAL},
+	{"DMA full"			, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_rmnet_rx_stats_get()
+ *	Get rmnet_rx interface stats by interface number.
+ */
+static bool nss_rmnet_rx_stats_get(struct nss_ctx_instance *nss_ctx, uint32_t if_num, uint64_t *stats, bool is_base)
+{
+	int i;
+	uint32_t if_num_curr = if_num;
+	uint64_t *stats_local;
+
+	if_num = if_num - NSS_DYNAMIC_IF_START;
+
+	spin_lock_bh(&nss_rmnet_rx_lock);
+	if (!rmnet_rx_handle[if_num]) {
+		spin_unlock_bh(&nss_rmnet_rx_lock);
+		return false;
+	}
+
+	if (if_num_curr == rmnet_rx_handle[if_num]->if_num_n2h) {
+		stats_local = rmnet_rx_handle[if_num]->stats_n2h;
+	} else {
+		stats_local = rmnet_rx_handle[if_num]->stats_h2n;
+	}
+
+	for (i = 0; i < NSS_RMNET_RX_STATS_MAX; i++) {
+		stats[i] = stats_local[i];
+	}
+	spin_unlock_bh(&nss_rmnet_rx_lock);
+
+	return true;
+}
+
+/*
+ * nss_rmnet_rx_stats_read()
+ *	Read rmnet_rx statistics
+ */
+static ssize_t nss_rmnet_rx_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	struct nss_stats_data *data = fp->private_data;
+	struct nss_ctx_instance *nss_ctx = nss_rmnet_rx_get_context();
+	int32_t if_num = NSS_DYNAMIC_IF_START;
+	int32_t max_if_num = if_num + NSS_MAX_DYNAMIC_INTERFACES;
+	uint32_t max_output_lines = ((NSS_RMNET_RX_STATS_MAX + 3) * NSS_MAX_DYNAMIC_INTERFACES)
+									+ NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		nss_warning("%px: Could not allocate memory for local statistics buffer", data);
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_RMNET_RX_STATS_MAX * sizeof(uint64_t), GFP_KERNEL);
+	if (unlikely(!stats_shadow)) {
+		nss_warning("%px: Could not allocate memory for local shadow buffer", data);
+		kfree(lbuf);
+		return 0;
+	}
+
+	if (data) {
+		if_num = data->if_num;
+	}
+
+	if (if_num > max_if_num) {
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "rmnet_rx", NSS_STATS_SINGLE_CORE);
+
+	/*
+	 * Interface statistics for all interfaces.
+	 */
+	for (; if_num < max_if_num; if_num++) {
+
+		if (!nss_rmnet_rx_stats_get(nss_ctx, if_num, stats_shadow, false)) {
+			continue;
+		}
+
+		size_wr += nss_stats_print("rmnet_rx", "interface", if_num,
+				nss_rmnet_rx_stats_str, stats_shadow, NSS_RMNET_RX_STATS_MAX,
+				lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_rmnet_rx_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(rmnet_rx)
+
+/*
+ * nss_rmnet_rx_stats_dentry_create()
+ *	Create rmnet_rx statistics debug entry.
+ */
+void nss_rmnet_rx_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("rmnet_rx", &nss_rmnet_rx_stats_ops);
+}
+
+/*
+ * nss_rmnet_rx_stats_sync()
+ *	Sync stats from the NSS FW
+ */
+void nss_rmnet_rx_stats_sync(struct nss_rmnet_rx_handle *handle,
+			     struct nss_rmnet_rx_stats *nwis, uint32_t if_num)
+{
+	int i;
+	uint64_t *stats;
+	spin_lock_bh(&nss_rmnet_rx_lock);
+	if (if_num == handle->if_num_n2h) {
+		stats = handle->stats_n2h;
+	} else {
+		stats = handle->stats_h2n;
+	}
+
+	stats[NSS_RMNET_RX_STATS_RX_PKTS] += nwis->node_stats.rx_packets;
+	stats[NSS_RMNET_RX_STATS_RX_BYTES] += nwis->node_stats.rx_bytes;
+	stats[NSS_RMNET_RX_STATS_TX_PKTS] += nwis->node_stats.tx_packets;
+	stats[NSS_RMNET_RX_STATS_TX_BYTES] += nwis->node_stats.tx_bytes;
+
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		stats[NSS_RMNET_RX_STATS_QUEUE_0_DROPPED + i] += nwis->node_stats.rx_dropped[i];
+	}
+
+	stats[NSS_RMNET_RX_STATS_ENQUEUE_FAILED] += nwis->enqueue_failed;
+	stats[NSS_RMNET_RX_STATS_NO_AVAIL_CHANNEL] += nwis->no_avail_channel;
+	stats[NSS_RMNET_RX_STATS_NUM_LINEAR_PBUF] += nwis->num_linear_pbuf;
+	stats[NSS_RMNET_RX_STATS_NO_PBUF_TO_LINEAR] += nwis->no_pbuf_to_linear;
+	stats[NSS_RMNET_RX_STATS_NO_ENOUGH_ROOM] += nwis->no_enough_room;
+
+	for (i = 0; i < NSS_RMNET_RX_CHANNEL_MAX; i++) {
+		stats[NSS_RMNET_RX_STATS_USING_CHANNEL0 + i] += nwis->using_channel[i];
+	}
+
+	stats[NSS_RMNET_RX_STATS_DMA_FAILED] += nwis->dma_failed;
+	spin_unlock_bh(&nss_rmnet_rx_lock);
+}
diff --git a/qca-nss-drv/nss_rmnet_rx_stats.h b/qca-nss-drv/nss_rmnet_rx_stats.h
new file mode 100644
index 0000000..638593a
--- /dev/null
+++ b/qca-nss-drv/nss_rmnet_rx_stats.h
@@ -0,0 +1,61 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_RMNET_RX_STATS_H
+#define __NSS_RMNET_RX_STATS_H
+
+/*
+ * rmnet_rx interface statistics types.
+ */
+enum nss_rmnet_rx_stats_types {
+	NSS_RMNET_RX_STATS_RX_PKTS,
+	NSS_RMNET_RX_STATS_RX_BYTES,
+	NSS_RMNET_RX_STATS_TX_PKTS,
+	NSS_RMNET_RX_STATS_TX_BYTES,
+	NSS_RMNET_RX_STATS_QUEUE_0_DROPPED,
+	NSS_RMNET_RX_STATS_QUEUE_1_DROPPED,
+	NSS_RMNET_RX_STATS_QUEUE_2_DROPPED,
+	NSS_RMNET_RX_STATS_QUEUE_3_DROPPED,
+	NSS_RMNET_RX_STATS_ENQUEUE_FAILED,
+	NSS_RMNET_RX_STATS_NO_AVAIL_CHANNEL,
+	NSS_RMNET_RX_STATS_NUM_LINEAR_PBUF,
+	NSS_RMNET_RX_STATS_NO_PBUF_TO_LINEAR,
+	NSS_RMNET_RX_STATS_NO_ENOUGH_ROOM,
+	NSS_RMNET_RX_STATS_USING_CHANNEL0,
+	NSS_RMNET_RX_STATS_USING_CHANNEL1,
+	NSS_RMNET_RX_STATS_USING_CHANNEL2,
+	NSS_RMNET_RX_STATS_USING_CHANNEL3,
+	NSS_RMNET_RX_STATS_USING_CHANNEL4,
+	NSS_RMNET_RX_STATS_USING_CHANNEL5,
+	NSS_RMNET_RX_STATS_USING_CHANNEL6,
+	NSS_RMNET_RX_STATS_USING_CHANNEL7,
+	NSS_RMNET_RX_STATS_USING_CHANNEL8,
+	NSS_RMNET_RX_STATS_USING_CHANNEL9,
+	NSS_RMNET_RX_STATS_USING_CHANNEL10,
+	NSS_RMNET_RX_STATS_USING_CHANNEL11,
+	NSS_RMNET_RX_STATS_DMA_FAILED,
+	NSS_RMNET_RX_STATS_MAX,
+};
+
+/*
+ * Virtual interface statistics APIs
+ */
+extern void nss_rmnet_rx_stats_sync(struct nss_rmnet_rx_handle *handle, struct nss_rmnet_rx_stats *nwis, uint32_t if_num);
+extern void nss_rmnet_rx_stats_dentry_create(void);
+
+#endif /* __NSS_RMNET_RX_STATS_H */
diff --git a/qca-nss-drv/nss_rps.c b/qca-nss-drv/nss_rps.c
new file mode 100644
index 0000000..c2a603f
--- /dev/null
+++ b/qca-nss-drv/nss_rps.c
@@ -0,0 +1,644 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2017, 2019-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_rps.c
+ *	NSS RPS based APIs
+ */
+
+#include "nss_tx_rx_common.h"
+
+#define NSS_RPS_MAX_CORE_HASH_BITMAP  ((1 << (NSS_HOST_CORES)) - 1)
+			/**< Maximum value that when all cores are available. */
+#define NSS_RPS_PRI_MAP_PARAM_FIELD_COUNT 2
+
+int nss_rps_config __read_mostly;
+int nss_rps_hash_bitmap = NSS_RPS_MAX_CORE_HASH_BITMAP;
+int nss_rps_pri_map[NSS_MAX_NUM_PRI];
+
+/*
+ * It is used to parse priority and core from the input.
+ */
+struct nss_rps_pri_map_parse_data {
+	uint8_t pri;	/**< Priority Index. */
+	int8_t core;	/**< Host core-id. */
+};
+
+/*
+ * Private data structure.
+ */
+struct nss_rps_pvt {
+	struct semaphore sem;		/* Semaphore structure. */
+	struct completion complete;	/* Completion structure. */
+	int response;			/* Response from FW. */
+	void *cb;			/* Original cb for sync msgs. */
+	void *app_data;			/* Original app_data for sync msgs. */
+};
+
+static struct nss_rps_pvt nss_rps_cfg_pvt;
+
+/*
+ * nss_rps_pri_map_usage()
+ *      Help function shows the usage of the command.
+ */
+static inline void nss_rps_pri_map_usage(void)
+{
+	nss_info_always("\nUsage:\n");
+	nss_info_always("echo <priority> <core> > /proc/sys/dev/nss/rps/pri_map\n\n");
+	nss_info_always("priority[0 to %u] core[-1 to %u]:\n\n",
+			NSS_MAX_NUM_PRI - 1,
+			NSS_HOST_CORES - 1);
+}
+
+/*
+ * nss_rps_pri_map_print()
+ *	Sysctl handler for printing rps/pri mapping.
+ */
+static int nss_rps_pri_map_print(struct ctl_table *ctl, void __user *buffer,
+				size_t *lenp, loff_t *ppos, int *pri_map)
+{
+	char *r_buf;
+	int i, len;
+	size_t cp_bytes = 0;
+
+	/*
+	 * (2 * 4) + 12 bytes for the buffer size is sufficient to write
+	 * the table including the spaces and new line characters.
+	 */
+	r_buf = kzalloc(((4 * NSS_MAX_NUM_PRI) + 12) * sizeof(char),
+			GFP_KERNEL);
+	if (!r_buf) {
+		nss_warning("Failed to alloc buffer to print pri map\n");
+		return -EFAULT;
+	}
+
+	/*
+	 * Write the core values that corresponds to each priorities.
+	 */
+	len = scnprintf(r_buf + cp_bytes, 8, "Cores: ");
+	cp_bytes += len;
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		len = scnprintf(r_buf + cp_bytes, 4, "%d ", pri_map[i]);
+		if (!len) {
+			nss_warning("failed to read from buffer %d\n", pri_map[i]);
+			kfree(r_buf);
+			return -EFAULT;
+		}
+		cp_bytes += len;
+	}
+
+	/*
+	 * Add new line character at the end.
+	 */
+	len = scnprintf(r_buf + cp_bytes, 4, "\n");
+	cp_bytes += len;
+
+	cp_bytes = simple_read_from_buffer(buffer, *lenp, ppos, r_buf, cp_bytes);
+	*lenp = cp_bytes;
+	kfree(r_buf);
+	return 0;
+}
+
+/*
+ * nss_rps_pri_map_parse()
+ *	Sysctl handler for rps/pri mappings.
+ */
+static int nss_rps_pri_map_parse(struct ctl_table *ctl, void __user *buffer,
+	size_t *lenp, loff_t *ppos, struct nss_rps_pri_map_parse_data *out)
+{
+	size_t cp_bytes = 0;
+	char w_buf[5];
+	loff_t w_offset = 0;
+	char *str;
+	unsigned int pri;
+	int core, res;
+
+	/*
+	 * Buffer length cannot be different than 4 or 5.
+	 */
+	if (*lenp < 4 || *lenp > 5) {
+		nss_warning("Buffer is not correct. Invalid lenght: %d\n", (int)*lenp);
+		return -EINVAL;
+	}
+
+	/*
+	 * It's a write operation
+	 */
+	cp_bytes = simple_write_to_buffer(w_buf, *lenp, &w_offset, buffer, 5);
+	if (cp_bytes != *lenp) {
+		nss_warning("failed to write to buffer\n");
+		return -EFAULT;
+	}
+
+	str = w_buf;
+	res = sscanf(str, "%u %d", &pri, &core);
+	if (res != NSS_RPS_PRI_MAP_PARAM_FIELD_COUNT) {
+		nss_warning("failed to read the buffer\n");
+		return -EFAULT;
+	}
+	/*
+	 * pri value cannot be higher than NSS_MAX_NUM_PRI.
+	 */
+	if (pri >= NSS_MAX_NUM_PRI) {
+		nss_warning("invalid pri value: %d\n", pri);
+		return -EINVAL;
+	}
+
+	/*
+	 * Host core must be less than NSS_HOST_CORE.
+	 */
+	if (core >= NSS_HOST_CORES || core < NSS_N2H_RPS_PRI_DEFAULT) {
+		nss_warning("invalid priority value: %d\n", core);
+		return -EINVAL;
+	}
+
+	nss_info("priority: %d core: %d\n", pri, core);
+
+	out->pri = pri;
+	out->core = core;
+	return 0;
+}
+
+/*
+ * nss_rps_cfg_callback()
+ *	Callback function for rps configuration.
+ */
+static void nss_rps_cfg_callback(void *app_data, struct nss_n2h_msg *nnm)
+{
+	struct nss_ctx_instance *nss_ctx =  (struct nss_ctx_instance *)app_data;
+	if (nnm->cm.response != NSS_CMN_RESPONSE_ACK) {
+
+		/*
+		 * Error, hence we are not updating the nss_rps
+		 * Send a FAILURE to restore the current value
+		 * to its previous state.
+		 */
+		nss_rps_cfg_pvt.response = NSS_FAILURE;
+		complete(&nss_rps_cfg_pvt.complete);
+		nss_warning("%px: RPS configuration failed : %d\n", nss_ctx,
+								   nnm->cm.error);
+		return;
+	}
+
+	nss_info("%px: RPS configuration succeeded: %d\n", nss_ctx,
+							   nnm->cm.error);
+	nss_ctx->rps_en = nnm->msg.rps_cfg.enable;
+	nss_rps_cfg_pvt.response = NSS_SUCCESS;
+	complete(&nss_rps_cfg_pvt.complete);
+}
+
+/*
+ * nss_rps_pri_map_cfg_callback()
+ *	Callback function for rps pri map configuration.
+ */
+static void nss_rps_pri_map_cfg_callback(void *app_data, struct nss_n2h_msg *nnm)
+{
+	if (nnm->cm.response != NSS_CMN_RESPONSE_ACK) {
+
+		/*
+		 * Error, hence we are not updating the nss_pri_map
+		 * Send a failure to restore the current value
+		 * to its previous state.
+		 */
+		nss_rps_cfg_pvt.response = NSS_FAILURE;
+		complete(&nss_rps_cfg_pvt.complete);
+		nss_warning("%px: RPS pri_map configuration failed : %d\n",
+				app_data, nnm->cm.error);
+		return;
+	}
+
+	nss_info("%px: RPS pri_map configuration succeeded: %d\n",
+			app_data, nnm->cm.error);
+
+	nss_rps_cfg_pvt.response = NSS_SUCCESS;
+	complete(&nss_rps_cfg_pvt.complete);
+}
+
+/*
+ * nss_rps_cfg()
+ *	Send Message to NSS to enable RPS.
+ */
+static nss_tx_status_t nss_rps_cfg(struct nss_ctx_instance *nss_ctx, int enable_rps)
+{
+	struct nss_n2h_msg nnm;
+	nss_tx_status_t nss_tx_status;
+	int ret;
+
+	down(&nss_rps_cfg_pvt.sem);
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE, NSS_TX_METADATA_TYPE_N2H_RPS_CFG,
+			sizeof(struct nss_n2h_rps),
+			nss_rps_cfg_callback,
+			(void *)nss_ctx);
+
+	nnm.msg.rps_cfg.enable = enable_rps;
+
+	nss_tx_status = nss_n2h_tx_msg(nss_ctx, &nnm);
+
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_tx error setting rps\n", nss_ctx);
+
+		up(&nss_rps_cfg_pvt.sem);
+		return NSS_FAILURE;
+	}
+
+	/*
+	 * Blocking call, wait till we get ACK for this msg.
+	 */
+	ret = wait_for_completion_timeout(&nss_rps_cfg_pvt.complete, msecs_to_jiffies(NSS_CONN_CFG_TIMEOUT));
+	if (ret == 0) {
+		nss_warning("%px: Waiting for ack timed out\n", nss_ctx);
+		up(&nss_rps_cfg_pvt.sem);
+		return NSS_FAILURE;
+	}
+
+	/*
+	 * ACK/NACK received from NSS FW
+	 * If NACK: Handler function will restore nss_rps_config
+	 * to previous state.
+	 */
+	if (NSS_FAILURE == nss_rps_cfg_pvt.response) {
+		up(&nss_rps_cfg_pvt.sem);
+		return NSS_FAILURE;
+	}
+
+	up(&nss_rps_cfg_pvt.sem);
+	return NSS_SUCCESS;
+}
+
+/*
+ * nss_rps_ipv4_hash_bitmap_cfg()
+ *	Send Message to NSS to configure hash_bitmap.
+ */
+static nss_tx_status_t nss_rps_ipv4_hash_bitmap_cfg(struct nss_ctx_instance *nss_ctx, int hash_bitmap)
+{
+	struct nss_ipv4_msg nim;
+	nss_tx_status_t nss_tx_status;
+
+	down(&nss_rps_cfg_pvt.sem);
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_RPS_HASH_BITMAP_CFG_MSG,
+			sizeof(struct nss_ipv4_rps_hash_bitmap_cfg_msg),
+			  NULL, NULL);
+
+	nim.msg.rps_hash_bitmap.hash_bitmap = hash_bitmap;
+
+	nss_tx_status = nss_ipv4_tx_sync(nss_ctx, &nim);
+
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_tx error setting rps\n", nss_ctx);
+
+		up(&nss_rps_cfg_pvt.sem);
+		return NSS_FAILURE;
+	}
+
+	up(&nss_rps_cfg_pvt.sem);
+	return NSS_SUCCESS;
+}
+
+#ifdef NSS_DRV_IPV6_ENABLE
+/*
+ * nss_rps_ipv6_hash_bitmap_cfg()
+ *	Send Message to NSS to configure hash_bitmap.
+ */
+static nss_tx_status_t nss_rps_ipv6_hash_bitmap_cfg(struct nss_ctx_instance *nss_ctx, int hash_bitmap)
+{
+	struct nss_ipv6_msg nim;
+	nss_tx_status_t nss_tx_status;
+
+	down(&nss_rps_cfg_pvt.sem);
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_RPS_HASH_BITMAP_CFG_MSG,
+			sizeof(struct nss_ipv4_rps_hash_bitmap_cfg_msg),
+			  NULL, NULL);
+
+	nim.msg.rps_hash_bitmap.hash_bitmap = hash_bitmap;
+
+	nss_tx_status = nss_ipv6_tx_sync(nss_ctx, &nim);
+
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_tx error setting rps\n", nss_ctx);
+
+		up(&nss_rps_cfg_pvt.sem);
+		return NSS_FAILURE;
+	}
+
+	up(&nss_rps_cfg_pvt.sem);
+	return NSS_SUCCESS;
+}
+#endif
+
+/*
+ * nss_rps_pri_map_cfg()
+ *	Send Message to NSS to configure pri_map.
+ */
+static nss_tx_status_t nss_rps_pri_map_cfg(struct nss_ctx_instance *nss_ctx, int *pri_map)
+{
+	struct nss_n2h_msg nnm;
+	struct nss_n2h_rps_pri_map *rps_pri_map;
+	nss_tx_status_t nss_tx_status;
+	int ret, i;
+
+	down(&nss_rps_cfg_pvt.sem);
+	nss_n2h_msg_init(&nnm, NSS_N2H_INTERFACE, NSS_TX_METADATA_TYPE_N2H_RPS_PRI_MAP_CFG,
+			sizeof(struct nss_n2h_rps_pri_map),
+			nss_rps_pri_map_cfg_callback,
+			(void *)nss_ctx);
+
+	rps_pri_map = &nnm.msg.rps_pri_map;
+
+	/*
+	 * Fill entries at pri_map.
+	 */
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		rps_pri_map->pri_map[i] = pri_map[i];
+	}
+
+	nss_tx_status = nss_n2h_tx_msg(nss_ctx, &nnm);
+
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_tx error setting rps\n", nss_ctx);
+
+		up(&nss_rps_cfg_pvt.sem);
+		return NSS_FAILURE;
+	}
+
+	/*
+	 * Blocking call, wait till we get ACK for this msg.
+	 */
+	ret = wait_for_completion_timeout(&nss_rps_cfg_pvt.complete, msecs_to_jiffies(NSS_CONN_CFG_TIMEOUT));
+	if (ret == 0) {
+		nss_warning("%px: Waiting for ack timed out\n", nss_ctx);
+		up(&nss_rps_cfg_pvt.sem);
+		return NSS_FAILURE;
+	}
+
+	/*
+	 * ACK/NACK received from NSS FW
+	 * If NACK: Handler function will restore nss_rps_config
+	 * to previous state.
+	 */
+	if (NSS_FAILURE == nss_rps_cfg_pvt.response) {
+		up(&nss_rps_cfg_pvt.sem);
+		return NSS_FAILURE;
+	}
+
+	up(&nss_rps_cfg_pvt.sem);
+	return NSS_SUCCESS;
+}
+
+/*
+ * nss_rps_cfg_handler()
+ *	Enable NSS RPS.
+ */
+static int nss_rps_cfg_handler(struct ctl_table *ctl, int write,
+				void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx;
+	int ret, ret_rps, current_state, i;
+	current_state = nss_rps_config;
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+
+	if (ret != NSS_SUCCESS) {
+		return ret;
+	}
+
+	if (!write) {
+		return ret;
+	}
+
+	if (nss_rps_config == 0) {
+		nss_info_always("Runtime disabling of NSS RPS not supported\n");
+		return ret;
+	}
+
+	if (nss_rps_config != 1) {
+		nss_info_always("Invalid input value. Valid values are 0 and 1\n");
+		return ret;
+	}
+
+	for (i = 0; i < nss_top_main.num_nss; i++) {
+		nss_ctx = &nss_top->nss[i];
+		nss_info("Enabling NSS RPS\n");
+		ret_rps = nss_rps_cfg(nss_ctx, 1);
+
+		/*
+		 * In here, we also need to revert the state of the previously enabled cores.
+		 * However, runtime disabling is currently not supported since queues are not
+		 * flushed in NSS FW.
+		 * TODO: Flush queues in NSS FW.
+		 */
+		if (ret_rps != NSS_SUCCESS) {
+			nss_warning("%px: rps enabling failed\n", nss_ctx);
+			nss_rps_config = current_state;
+			return ret_rps;
+		}
+	}
+	return NSS_SUCCESS;
+}
+
+/*
+ * nss_rps_hash_bitmap_cfg_handler()
+ *	Configure NSS rps_hash_bitmap
+ */
+static int nss_rps_hash_bitmap_cfg_handler(struct ctl_table *ctl, int write,
+				void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[0];
+	int ret, ret_ipv4, current_state;
+
+	current_state = nss_rps_hash_bitmap;
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+
+	if (ret != NSS_SUCCESS) {
+		nss_rps_hash_bitmap = current_state;
+		return ret;
+	}
+
+	if (!write) {
+		return ret;
+	}
+
+	if (nss_rps_hash_bitmap <= (NSS_RPS_MAX_CORE_HASH_BITMAP)) {
+		nss_info("Configuring NSS RPS hash_bitmap\n");
+		ret_ipv4 = nss_rps_ipv4_hash_bitmap_cfg(nss_ctx, nss_rps_hash_bitmap);
+
+		if (ret_ipv4 != NSS_SUCCESS) {
+			nss_warning("%px: ipv4 hash_bitmap config message failed\n", nss_ctx);
+			nss_rps_hash_bitmap = current_state;
+			return ret_ipv4;
+		}
+
+#ifdef NSS_DRV_IPV6_ENABLE
+		{
+			int ret_ipv6;
+			ret_ipv6 = nss_rps_ipv6_hash_bitmap_cfg(nss_ctx, nss_rps_hash_bitmap);
+
+			if (ret_ipv6 != NSS_SUCCESS) {
+				nss_warning("%px: ipv6 hash_bitmap config message failed\n", nss_ctx);
+				nss_rps_hash_bitmap = current_state;
+				if (nss_rps_ipv4_hash_bitmap_cfg(nss_ctx, nss_rps_hash_bitmap != NSS_SUCCESS)) {
+					nss_warning("%px: ipv4 and ipv6 have different hash_bitmaps.\n", nss_ctx);
+				}
+				return ret_ipv6;
+			}
+		}
+#endif
+		return 0;
+	}
+
+	nss_info_always("Invalid input value. Valid values are less than %d\n", (NSS_RPS_MAX_CORE_HASH_BITMAP));
+	return ret;
+}
+
+/* nss_rps_pri_map_cfg_handler()
+ *	Configure NSS rps_pri_map
+ */
+static int nss_rps_pri_map_cfg_handler(struct ctl_table *ctl, int write,
+				void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx = &nss_top->nss[0];
+
+	int ret, ret_pri_map;
+	struct nss_rps_pri_map_parse_data out, current_state;
+	if (!write) {
+		return nss_rps_pri_map_print(ctl, buffer, lenp, ppos, nss_rps_pri_map);
+	}
+
+	ret = nss_rps_pri_map_parse(ctl, buffer, lenp, ppos, &out);
+
+	if (ret != NSS_SUCCESS) {
+		nss_rps_pri_map_usage();
+		return ret;
+	}
+
+	nss_info("Configuring NSS RPS Priority Map\n");
+	current_state.pri = out.pri;
+	current_state.core = nss_rps_pri_map[out.pri];
+	nss_rps_pri_map[out.pri] = out.core;
+	ret_pri_map = nss_rps_pri_map_cfg(nss_ctx, nss_rps_pri_map);
+	if (ret_pri_map != NSS_SUCCESS) {
+		nss_rps_pri_map[current_state.pri] = current_state.core;
+		nss_warning("%px: pri_map config message failed\n", nss_ctx);
+	}
+
+	return ret_pri_map;
+}
+
+static struct ctl_table nss_rps_table[] = {
+	{
+		.procname	= "enable",
+		.data		= &nss_rps_config,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_rps_cfg_handler,
+	},
+	{
+		.procname	= "hash_bitmap",
+		.data		= &nss_rps_hash_bitmap,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_rps_hash_bitmap_cfg_handler,
+	},
+	{
+		.procname	= "pri_map",
+		.data		= &nss_rps_pri_map[NSS_MAX_NUM_PRI],
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &nss_rps_pri_map_cfg_handler,
+	},
+	{ }
+};
+
+static struct ctl_table nss_rps_dir[] = {
+	{
+		.procname		= "rps",
+		.mode			= 0555,
+		.child			= nss_rps_table,
+	},
+	{ }
+};
+
+static struct ctl_table nss_rps_root_dir[] = {
+	{
+		.procname		= "nss",
+		.mode			= 0555,
+		.child			= nss_rps_dir,
+	},
+	{ }
+};
+
+static struct ctl_table nss_rps_root[] = {
+	{
+		.procname		= "dev",
+		.mode			= 0555,
+		.child			= nss_rps_root_dir,
+	},
+	{ }
+};
+
+static struct ctl_table_header *nss_rps_header;
+
+/*
+ * nss_rps_pri_map_init_handler()
+ *	Initialize pri_map for priority based rps selection.
+ */
+void nss_rps_pri_map_init_handler(void)
+{
+	int i;
+
+	/*
+	 Initialize the mapping table with the default values.
+	*/
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		nss_rps_pri_map[i] = NSS_N2H_RPS_PRI_DEFAULT;
+	}
+
+}
+
+/*
+ * nss_rps_register_sysctl()
+ */
+void nss_rps_register_sysctl(void)
+{
+
+	/*
+	 * rps sema init.
+	 */
+	sema_init(&nss_rps_cfg_pvt.sem, 1);
+	init_completion(&nss_rps_cfg_pvt.complete);
+
+	nss_rps_pri_map_init_handler();
+
+	/*
+	 * Register sysctl table.
+	 */
+	nss_rps_header = register_sysctl_table(nss_rps_root);
+}
+
+/*
+ * nss_rps_unregister_sysctl()
+ *      Unregister sysctl specific to rps
+ */
+void nss_rps_unregister_sysctl(void)
+{
+	/*
+	 * Unregister sysctl table.
+	 */
+	if (nss_rps_header) {
+		unregister_sysctl_table(nss_rps_header);
+	}
+}
diff --git a/qca-nss-drv/nss_shaper.c b/qca-nss-drv/nss_shaper.c
new file mode 100644
index 0000000..2726b8b
--- /dev/null
+++ b/qca-nss-drv/nss_shaper.c
@@ -0,0 +1,367 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, 2016-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+
+/*
+ * nss_shaper_register_shaping()
+ *	Register to obtain an NSS context for basic shaping operations
+ */
+void *nss_shaper_register_shaping(void)
+{
+	if (nss_top_main.shaping_handler_id == (uint8_t)-1) {
+		nss_warning("%px: SHAPING IS NOT ENABLED", __func__);
+		return NULL;
+	}
+	return (void *)&nss_top_main.nss[nss_top_main.shaping_handler_id];
+}
+
+/*
+ * nss_shaper_unregister_shaping()
+ *	Unregister an NSS shaping context
+ */
+void nss_shaper_unregister_shaping(void *nss_ctx)
+{
+}
+
+/*
+ * nss_shaper_register_shaper_bounce_interface()
+ *	Register for performing shaper bounce operations for interface shaper
+ */
+void *nss_shaper_register_shaper_bounce_interface(uint32_t if_num, nss_shaper_bounced_callback_t cb, void *app_data, struct module *owner)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_shaper_bounce_registrant *reg;
+
+	nss_info("Shaper bounce interface register: %u, cb: %px, app_data: %px, owner: %px",
+			if_num, cb, app_data, owner);
+
+	/*
+	 * Must be valid interface number
+	 */
+	if (if_num >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("Invalid if_num: %u", if_num);
+		BUG_ON(false);
+	}
+
+	/*
+	 * Shaping enabled?
+	 */
+	if (nss_top_main.shaping_handler_id == (uint8_t)-1) {
+		nss_warning("%px: SHAPING IS NOT ENABLED", __func__);
+		return NULL;
+	}
+
+	/*
+	 * Can we hold the module?
+	 */
+	if (!try_module_get(owner)) {
+		nss_warning("%px: Unable to hold owner", __func__);
+		return NULL;
+	}
+
+	spin_lock_bh(&nss_top->lock);
+
+	/*
+	 * Must not have existing registrant
+	 */
+	reg = &nss_top->bounce_interface_registrants[if_num];
+	if (reg->registered) {
+		spin_unlock_bh(&nss_top->stats_lock);
+		module_put(owner);
+		nss_warning("Already registered: %u", if_num);
+		BUG_ON(false);
+	}
+
+	/*
+	 * Register
+	 */
+	reg->bounced_callback = cb;
+	reg->app_data = app_data;
+	reg->owner = owner;
+	reg->registered = true;
+	spin_unlock_bh(&nss_top->lock);
+
+	return (void *)&nss_top->nss[nss_top->shaping_handler_id];
+}
+
+/*
+ * nss_shaper_unregister_shaper_bounce_interface()
+ *	Unregister for shaper bounce operations for interface shaper
+ */
+void nss_shaper_unregister_shaper_bounce_interface(uint32_t if_num)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_shaper_bounce_registrant *reg;
+	struct module *owner;
+
+	nss_info("Shaper bounce interface unregister: %u", if_num);
+
+	/*
+	 * Must be valid interface number
+	 */
+	if (if_num >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("Invalid if_num: %u", if_num);
+		BUG_ON(false);
+	}
+
+	spin_lock_bh(&nss_top->lock);
+
+	/*
+	 * Must have existing registrant
+	 */
+	reg = &nss_top->bounce_interface_registrants[if_num];
+	if (!reg->registered) {
+		spin_unlock_bh(&nss_top->stats_lock);
+		nss_warning("Already unregistered: %u", if_num);
+		BUG_ON(false);
+	}
+
+	/*
+	 * Unegister
+	 */
+	owner = reg->owner;
+	reg->owner = NULL;
+	reg->registered = false;
+	spin_unlock_bh(&nss_top->lock);
+
+	module_put(owner);
+}
+
+/*
+ * nss_shaper_register_shaper_bounce_bridge()
+ *	Register for performing shaper bounce operations for bridge shaper
+ */
+void *nss_shaper_register_shaper_bounce_bridge(uint32_t if_num, nss_shaper_bounced_callback_t cb, void *app_data, struct module *owner)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_shaper_bounce_registrant *reg;
+
+	nss_info("Shaper bounce bridge register: %u, cb: %px, app_data: %px, owner: %px",
+			if_num, cb, app_data, owner);
+
+	/*
+	 * Must be valid interface number
+	 */
+	if (if_num >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("Invalid if_num: %u", if_num);
+		BUG_ON(false);
+	}
+
+	/*
+	 * Shaping enabled?
+	 */
+	if (nss_top_main.shaping_handler_id == (uint8_t)-1) {
+		nss_warning("%px: SHAPING IS NOT ENABLED", __func__);
+		return NULL;
+	}
+
+	/*
+	 * Can we hold the module?
+	 */
+	if (!try_module_get(owner)) {
+		nss_warning("%px: Unable to hold owner", __func__);
+		return NULL;
+	}
+
+	spin_lock_bh(&nss_top->lock);
+
+	/*
+	 * Must not have existing registrant
+	 */
+	reg = &nss_top->bounce_bridge_registrants[if_num];
+	if (reg->registered) {
+		spin_unlock_bh(&nss_top->stats_lock);
+		module_put(owner);
+		nss_warning("Already registered: %u", if_num);
+		BUG_ON(false);
+	}
+
+	/*
+	 * Register
+	 */
+	reg->bounced_callback = cb;
+	reg->app_data = app_data;
+	reg->owner = owner;
+	reg->registered = true;
+	spin_unlock_bh(&nss_top->lock);
+
+	nss_ctx = &nss_top->nss[nss_top->shaping_handler_id];
+	return (void *)nss_ctx;
+}
+
+/*
+ * nss_shaper_unregister_shaper_bounce_bridge()
+ *	Unregister for shaper bounce operations for bridge shaper
+ */
+void nss_shaper_unregister_shaper_bounce_bridge(uint32_t if_num)
+{
+	struct nss_top_instance *nss_top = &nss_top_main;
+	struct nss_shaper_bounce_registrant *reg;
+	struct module *owner;
+
+	nss_info("Shaper bounce bridge unregister: %u", if_num);
+
+	/*
+	 * Must be valid interface number
+	 */
+	if (if_num >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("Invalid if_num: %u", if_num);
+		BUG_ON(false);
+	}
+
+	spin_lock_bh(&nss_top->lock);
+
+	/*
+	 * Must have existing registrant
+	 */
+	reg = &nss_top->bounce_bridge_registrants[if_num];
+	if (!reg->registered) {
+		spin_unlock_bh(&nss_top->stats_lock);
+		nss_warning("Already unregistered: %u", if_num);
+		BUG_ON(false);
+	}
+
+	/*
+	 * Wait until any bounce callback that is active is finished
+	 */
+	while (reg->callback_active) {
+		spin_unlock_bh(&nss_top->stats_lock);
+		yield();
+		spin_lock_bh(&nss_top->stats_lock);
+	}
+
+	/*
+	 * Unegister
+	 */
+	owner = reg->owner;
+	reg->owner = NULL;
+	reg->registered = false;
+	spin_unlock_bh(&nss_top->lock);
+
+	module_put(owner);
+}
+
+/*
+ * nss_shaper_bounce_interface_packet()
+ *	Bounce a packet to the NSS for interface shaping.
+ *
+ * You must have registered for interface bounce shaping to call this.
+ */
+nss_tx_status_t nss_shaper_bounce_interface_packet(void *ctx, uint32_t if_num, struct sk_buff *skb)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)ctx;
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	struct nss_shaper_bounce_registrant *reg;
+	int32_t status;
+
+	/*
+	 * Must be valid interface number
+	 */
+	if (if_num >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("Invalid if_num: %u", if_num);
+		BUG_ON(false);
+	}
+
+	/*
+	 * Must have existing registrant
+	 */
+	spin_lock_bh(&nss_top->lock);
+	reg = &nss_top->bounce_interface_registrants[if_num];
+	if (!reg->registered) {
+		spin_unlock_bh(&nss_top->stats_lock);
+		nss_warning("unregistered: %u", if_num);
+		return NSS_TX_FAILURE;
+	}
+	spin_unlock_bh(&nss_top->lock);
+
+	status = nss_core_send_buffer(nss_ctx, if_num, skb, NSS_IF_H2N_DATA_QUEUE,
+					H2N_BUFFER_SHAPER_BOUNCE_INTERFACE, 0);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		return NSS_TX_FAILURE;
+	}
+	nss_hal_send_interrupt(nss_ctx, NSS_H2N_INTR_DATA_COMMAND_QUEUE);
+
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_PACKET]);
+	return NSS_TX_SUCCESS;
+}
+
+/*
+ * nss_shaper_bounce_bridge_packet()
+ *	Bounce a packet to the NSS for bridge shaping.
+ *
+ * You must have registered for bridge bounce shaping to call this.
+ */
+nss_tx_status_t nss_shaper_bounce_bridge_packet(void *ctx, uint32_t if_num, struct sk_buff *skb)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)ctx;
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	struct nss_shaper_bounce_registrant *reg;
+	int32_t status;
+
+	/*
+	 * Must be valid interface number
+	 */
+	if (if_num >= NSS_MAX_NET_INTERFACES) {
+		nss_warning("Invalid if_num: %u", if_num);
+		BUG_ON(false);
+	}
+
+	/*
+	 * Must have existing registrant
+	 */
+	spin_lock_bh(&nss_top->lock);
+	reg = &nss_top->bounce_bridge_registrants[if_num];
+	if (!reg->registered) {
+		spin_unlock_bh(&nss_top->stats_lock);
+		nss_warning("unregistered: %u", if_num);
+		return NSS_TX_FAILURE;
+	}
+	spin_unlock_bh(&nss_top->lock);
+
+	nss_info("%s: Bridge bounce skb: %px, if_num: %u, ctx: %px", __func__, skb, if_num, nss_ctx);
+	status = nss_core_send_buffer(nss_ctx, if_num, skb, NSS_IF_H2N_DATA_QUEUE,
+					H2N_BUFFER_SHAPER_BOUNCE_BRIDGE, 0);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_info("%s: Bridge bounce core send rejected", __func__);
+		return NSS_TX_FAILURE;
+	}
+	nss_hal_send_interrupt(nss_ctx, NSS_H2N_INTR_DATA_COMMAND_QUEUE);
+
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_PACKET]);
+	return NSS_TX_SUCCESS;
+}
+
+/*
+ * nss_shaper_get_device()
+ *	Gets the original device from probe.
+ */
+struct device *nss_shaper_get_dev(void)
+{
+	struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[nss_top_main.shaping_handler_id];
+	return nss_ctx->dev;
+}
+
+EXPORT_SYMBOL(nss_shaper_bounce_bridge_packet);
+EXPORT_SYMBOL(nss_shaper_bounce_interface_packet);
+EXPORT_SYMBOL(nss_shaper_unregister_shaper_bounce_interface);
+EXPORT_SYMBOL(nss_shaper_register_shaper_bounce_interface);
+EXPORT_SYMBOL(nss_shaper_unregister_shaper_bounce_bridge);
+EXPORT_SYMBOL(nss_shaper_register_shaper_bounce_bridge);
+EXPORT_SYMBOL(nss_shaper_register_shaping);
+EXPORT_SYMBOL(nss_shaper_unregister_shaping);
+EXPORT_SYMBOL(nss_shaper_get_dev);
diff --git a/qca-nss-drv/nss_sjack.c b/qca-nss-drv/nss_sjack.c
new file mode 100644
index 0000000..086eedf
--- /dev/null
+++ b/qca-nss-drv/nss_sjack.c
@@ -0,0 +1,189 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_sjack_stats.h"
+#include "nss_sjack_log.h"
+
+/*
+ * nss_sjack_handler()
+ * 	Handle NSS -> HLOS messages for sjack
+ */
+static void nss_sjack_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm,
+				__attribute__((unused))void *app_data)
+{
+	void *ctx;
+	nss_sjack_msg_callback_t cb;
+	struct nss_sjack_msg *nsm = (struct nss_sjack_msg *)ncm;
+
+	BUG_ON(ncm->interface != NSS_SJACK_INTERFACE);
+
+	/*
+	 * Trace Messages
+	 */
+	nss_sjack_log_rx_msg(nsm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >=  NSS_SJACK_MAX_MSG_TYPE) {
+		nss_warning("%px: received invalid message %d for sjack interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_sjack_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, sjack sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	switch (ncm->type) {
+	case NSS_SJACK_STATS_SYNC_MSG:
+		/*
+		 * Update sjack statistics on node sync.
+		 */
+		nss_sjack_stats_node_sync(nss_ctx, &nsm->msg.stats_sync);
+		break;
+	}
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_sjack_msg_callback_t)ncm->cb;
+	ctx = nss_ctx->subsys_dp_register[ncm->interface].ndev;
+
+	cb(ctx, ncm);
+}
+
+/*
+ * nss_sjack_tx_msg()
+ * 	Transmit a sjack message to NSSFW
+ */
+nss_tx_status_t nss_sjack_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_sjack_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_sjack_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (ncm->interface != NSS_SJACK_INTERFACE) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_SJACK_MAX_MSG_TYPE) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ * nss_sjack_register_if()
+ */
+struct nss_ctx_instance *nss_sjack_register_if(uint32_t if_num, struct net_device *netdev,
+						nss_sjack_msg_callback_t event_callback)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.sjack_handler_id];
+	uint32_t status;
+
+	nss_assert(nss_ctx);
+	nss_assert(if_num == NSS_SJACK_INTERFACE);
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, NULL, NULL, NULL, netdev, 0);
+
+	status = nss_core_register_msg_handler(nss_ctx, NSS_SJACK_INTERFACE, event_callback);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to register handler for interface %d with NSS core\n", nss_ctx, if_num);
+		return NULL;
+	}
+
+	return nss_ctx;
+}
+
+/*
+ * nss_sjack_unregister_if()
+ */
+void nss_sjack_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.sjack_handler_id];
+	uint32_t status;
+
+	nss_assert(nss_ctx);
+	nss_assert(if_num == NSS_SJACK_INTERFACE);
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	status = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to unregister handler for interface %d with NSS core\n", nss_ctx, if_num);
+		return;
+	}
+
+	return;
+}
+
+/*
+ * nss_sjack_get_context()
+ * 	get NSS context instance for sjack
+ */
+struct nss_ctx_instance *nss_sjack_get_context(void)
+{
+	return &nss_top_main.nss[nss_top_main.sjack_handler_id];
+}
+EXPORT_SYMBOL(nss_sjack_get_context);
+
+/*
+ * nss_sjack_register_handler()
+ *	Registering handler for sending msg to sjack node on NSS.
+ */
+void nss_sjack_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_sjack_get_context();
+
+	nss_core_register_handler(nss_ctx, NSS_SJACK_INTERFACE, nss_sjack_handler, NULL);
+
+	nss_sjack_stats_dentry_create();
+}
+
+EXPORT_SYMBOL(nss_sjack_register_if);
+EXPORT_SYMBOL(nss_sjack_unregister_if);
+EXPORT_SYMBOL(nss_sjack_tx_msg);
diff --git a/qca-nss-drv/nss_sjack_log.c b/qca-nss-drv/nss_sjack_log.c
new file mode 100644
index 0000000..c585b74
--- /dev/null
+++ b/qca-nss-drv/nss_sjack_log.c
@@ -0,0 +1,133 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_sjack_log.c
+ *	NSS SJACK logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_sjack_log_message_types_str
+ *	NSS SJACK message strings
+ */
+static int8_t *nss_sjack_log_message_types_str[NSS_SJACK_MAX_MSG_TYPE] __maybe_unused = {
+	"SJACK Configure",
+	"SJACK Unconfigure",
+	"SJACK Stats",
+};
+
+/*
+ * nss_sjack_log_configure_msg()
+ *	Log NSS SJACK Configure.
+ */
+static void nss_sjack_log_configure_msg(struct nss_sjack_msg *nsm)
+{
+	struct nss_sjack_configure_msg *nscm __maybe_unused = &nsm->msg.configure;
+	nss_trace("%px: NSS SJACK Configure message \n"
+		"SJACK Ingress Interface Number: %d\n"
+		"SJACK Engress Interface Number: %d\n"
+		"SJACK Tunnel ID: %d\n"
+		"SJACK DSCP Value: %d\n"
+		"SJACK GRE Priority: %d\n"
+		"SJACK GRE Flags: %d\n"
+		"SJACK IPSEC SA Pattern Flag: %d\n",
+		nscm, nscm->ingress_if_num,
+		nscm->egress_if_num, nscm->tunnel_id,
+		nscm->ip_dscp, nscm->gre_prio,
+		nscm->gre_flags, nscm->use_ipsec_sa_pattern);
+}
+
+/*
+ * nss_sjack_log_unconfigure_msg()
+ *	Log NSS SJACK Unconfigure.
+ */
+static void nss_sjack_log_unconfigure_msg(struct nss_sjack_msg *nsm)
+{
+	struct nss_sjack_unconfigure_msg *nsum __maybe_unused = &nsm->msg.unconfigure;
+	nss_trace("%px: NSS SJACK UnConfigure message \n"
+		"SJACK Ingress Interface Number: %d\n",
+		nsum, nsum->ingress_if_num);
+}
+
+/*
+ * nss_sjack_log_verbose()
+ *	Log message contents.
+ */
+static void nss_sjack_log_verbose(struct nss_sjack_msg *nsm)
+{
+	switch (nsm->cm.type) {
+	case NSS_SJACK_CONFIGURE_MSG:
+		nss_sjack_log_configure_msg(nsm);
+		break;
+
+	case NSS_SJACK_UNCONFIGURE_MSG:
+		nss_sjack_log_unconfigure_msg(nsm);
+		break;
+
+	case NSS_SJACK_STATS_SYNC_MSG:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", nsm);
+		break;
+	}
+}
+
+/*
+ * nss_sjack_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_sjack_log_tx_msg(struct nss_sjack_msg *nsm)
+{
+	if (nsm->cm.type >= NSS_SJACK_MAX_MSG_TYPE) {
+		nss_warning("%px: Invalid message type\n", nsm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nsm, nsm->cm.type, nss_sjack_log_message_types_str[nsm->cm.type]);
+	nss_sjack_log_verbose(nsm);
+}
+
+/*
+ * nss_sjack_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_sjack_log_rx_msg(struct nss_sjack_msg *nsm)
+{
+	if (nsm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", nsm);
+		return;
+	}
+
+	if (nsm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nsm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nsm, nsm->cm.type,
+			nss_sjack_log_message_types_str[nsm->cm.type],
+			nsm->cm.response, nss_cmn_response_str[nsm->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		nsm, nsm->cm.type, nss_sjack_log_message_types_str[nsm->cm.type],
+		nsm->cm.response, nss_cmn_response_str[nsm->cm.response]);
+
+verbose:
+	nss_sjack_log_verbose(nsm);
+}
diff --git a/qca-nss-drv/nss_sjack_log.h b/qca-nss-drv/nss_sjack_log.h
new file mode 100644
index 0000000..56435a4
--- /dev/null
+++ b/qca-nss-drv/nss_sjack_log.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_SJACK_LOG_H
+#define __NSS_SJACK_LOG_H
+
+/*
+ * nss_sjack.h
+ *	NSS SJACK header file.
+ */
+
+/*
+ * Logger APIs
+ */
+
+/*
+ * nss_sjack_log_tx_msg
+ *	Logs a sjack message that is sent to the NSS firmware.
+ */
+void nss_sjack_log_tx_msg(struct nss_sjack_msg *nsm);
+
+/*
+ * nss_sjack_log_rx_msg
+ *	Logs a sjack message that is received from the NSS firmware.
+ */
+void nss_sjack_log_rx_msg(struct nss_sjack_msg *nsm);
+
+#endif /* __NSS_SJACK_LOG_H */
diff --git a/qca-nss-drv/nss_sjack_stats.c b/qca-nss-drv/nss_sjack_stats.c
new file mode 100644
index 0000000..139a349
--- /dev/null
+++ b/qca-nss-drv/nss_sjack_stats.c
@@ -0,0 +1,94 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2019 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_sjack_stats.h"
+
+/*
+ * nss_sjack_stats_read()
+ *	Read SJACK stats
+ */
+static ssize_t nss_sjack_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	/*
+	 * max output lines = #stats + start tag line + end tag line + three blank lines
+	 */
+	uint32_t max_output_lines = NSS_STATS_NODE_MAX + 5;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_STATS_NODE_MAX * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "sjack", NSS_STATS_SINGLE_CORE);
+	size_wr += nss_stats_fill_common_stats(NSS_SJACK_INTERFACE, NSS_STATS_SINGLE_INSTANCE, lbuf, size_wr, size_al, "sjack");
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_sjack_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(sjack)
+
+/*
+ * nss_sjack_stats_dentry_create()
+ *	Create SJACK node statistics debug entry.
+ */
+void nss_sjack_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("sjack", &nss_sjack_stats_ops);
+}
+
+/*
+ * nss_sjack_stats_node_sync()
+ *	Update sjack node stats.
+ */
+void nss_sjack_stats_node_sync(struct nss_ctx_instance *nss_ctx, struct nss_sjack_stats_sync_msg *nins)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	int j;
+
+	/*
+	 * Update SJACK node stats.
+	 */
+	spin_lock_bh(&nss_top->stats_lock);
+	nss_top->stats_node[NSS_SJACK_INTERFACE][NSS_SJACK_STATS_RX_PKTS] += nins->node_stats.rx_packets;
+	nss_top->stats_node[NSS_SJACK_INTERFACE][NSS_SJACK_STATS_RX_BYTES] += nins->node_stats.rx_bytes;
+	nss_top->stats_node[NSS_SJACK_INTERFACE][NSS_SJACK_STATS_TX_PKTS] += nins->node_stats.tx_packets;
+	nss_top->stats_node[NSS_SJACK_INTERFACE][NSS_SJACK_STATS_TX_BYTES] += nins->node_stats.tx_bytes;
+
+	for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+		nss_top->stats_node[NSS_SJACK_INTERFACE][NSS_SJACK_STATS_RX_QUEUE_0_DROPPED + j] += nins->node_stats.rx_dropped[j];
+	}
+
+	spin_unlock_bh(&nss_top->stats_lock);
+}
diff --git a/qca-nss-drv/nss_sjack_stats.h b/qca-nss-drv/nss_sjack_stats.h
new file mode 100644
index 0000000..cbcd604
--- /dev/null
+++ b/qca-nss-drv/nss_sjack_stats.h
@@ -0,0 +1,45 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_SJACK_STATS_H
+#define __NSS_SJACK_STATS_H
+
+/*
+ * SJACK statistics
+ */
+enum nss_sjack_stats_types {
+	NSS_SJACK_STATS_RX_PKTS,	/* sjack node RX packets */
+	NSS_SJACK_STATS_RX_BYTES,	/* sjack node RX bytes */
+	NSS_SJACK_STATS_TX_PKTS,	/* sjack node TX packets */
+	NSS_SJACK_STATS_TX_BYTES,	/* sjack node TX bytes */
+	NSS_SJACK_STATS_RX_QUEUE_0_DROPPED,
+					/* sjack node RX Queue 0 dropped */
+	NSS_SJACK_STATS_RX_QUEUE_1_DROPPED,
+					/* sjack node RX Queue 1 dropped */
+	NSS_SJACK_STATS_RX_QUEUE_2_DROPPED,
+					/* sjack node RX Queue 2 dropped */
+	NSS_SJACK_STATS_RX_QUEUE_3_DROPPED,
+					/* sjack node RX Queue 3 dropped */
+	NSS_SJACK_STATS_MAX,
+};
+
+/*
+ * SJACK statistics APIs
+ */
+extern void nss_sjack_stats_node_sync(struct nss_ctx_instance *nss_ctx, struct nss_sjack_stats_sync_msg *nins);
+extern void nss_sjack_stats_dentry_create(void);
+
+#endif /* __NSS_SJACK_STATS_H */
diff --git a/qca-nss-drv/nss_stats.c b/qca-nss-drv/nss_stats.c
new file mode 100644
index 0000000..9605c37
--- /dev/null
+++ b/qca-nss-drv/nss_stats.c
@@ -0,0 +1,481 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_drv_stats.h"
+
+/*
+ * Maximum banner length:
+ */
+#define NSS_STATS_BANNER_MAX_LENGTH 80
+
+/*
+ * Maximum number of digits a stats value can have:
+ */
+#define NSS_STATS_DIGITS_MAX 16
+
+/*
+ * Spaces to print core details inside banner
+ */
+#define NSS_STATS_BANNER_SPACES 12
+
+/*
+ * Max characters for a node name.
+ */
+#define NSS_STATS_NODE_NAME_MAX 24
+
+int nonzero_stats_print = 0;
+
+/*
+ * nss_stats_spacing()
+ *	Framework to maintain consistent spacing between stats value and stats type.
+ */
+static size_t nss_stats_spacing(uint64_t stats_val, char *lbuf, size_t size_wr, size_t size_al)
+{
+	int i;
+	int digit_counter = (stats_val == 0 ? 1 : 0);
+	while (stats_val != 0) {
+		/*
+		 * TODO: need to check for (nss_ptr_t)
+		 */
+		stats_val = (nss_ptr_t)stats_val / 10;
+		digit_counter++;
+	}
+
+	for (i = 0; i < NSS_STATS_DIGITS_MAX - digit_counter; i++) {
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, " ");
+	}
+
+	return size_wr;
+}
+
+/*
+ * nss_stats_nonzero_handler()
+ *	Handler to take nonzero stats print configuration.
+ */
+static int nss_stats_nonzero_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret;
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	return ret;
+}
+
+static struct ctl_table nss_stats_table[] = {
+	{
+		.procname		= "non_zero_stats",
+		.data			= &nonzero_stats_print,
+		.maxlen			= sizeof(int),
+		.mode			= 0644,
+		.proc_handler		= &nss_stats_nonzero_handler,
+	},
+	{ }
+};
+
+static struct ctl_table nss_stats_dir[] = {
+	{
+		.procname		= "stats",
+		.mode			= 0555,
+		.child			= nss_stats_table,
+	},
+	{ }
+};
+
+static struct ctl_table nss_stats_root_dir[] = {
+	{
+		.procname		= "nss",
+		.mode			= 0555,
+		.child			= nss_stats_dir,
+	},
+	{ }
+};
+
+static struct ctl_table nss_stats_root[] = {
+	{
+		.procname		= "dev",
+		.mode			= 0555,
+		.child			= nss_stats_root_dir,
+	},
+	{ }
+};
+static struct ctl_table_header *nss_stats_header;
+
+/*
+ * nss_stats_register_sysctl()
+ *	Register a sysctl table for stats.
+ */
+void nss_stats_register_sysctl(void)
+{
+	/*
+	 * Register sysctl table.
+	 */
+	nss_stats_header = register_sysctl_table(nss_stats_root);
+}
+
+/*
+ * nss_stats_open()
+ *	Opens stats file.
+ */
+int nss_stats_open(struct inode *inode, struct file *filp)
+{
+	struct nss_stats_data *data = NULL;
+
+	data = kzalloc(sizeof(struct nss_stats_data), GFP_KERNEL);
+	if (!data) {
+		return -ENOMEM;
+	}
+
+	memset(data, 0, sizeof (struct nss_stats_data));
+	data->if_num = NSS_DYNAMIC_IF_START;
+	data->index = 0;
+	data->edma_id = (nss_ptr_t)inode->i_private;
+	data->nss_ctx = (struct nss_ctx_instance *)(inode->i_private);
+	filp->private_data = data;
+
+	return 0;
+}
+
+/*
+ * nss_stats_release()
+ *	Releases stats file.
+ */
+int nss_stats_release(struct inode *inode, struct file *filp)
+{
+	struct nss_stats_data *data = filp->private_data;
+
+	if (data) {
+		kfree(data);
+	}
+
+	return 0;
+}
+
+/*
+ * nss_stats_clean()
+ *	Cleanup NSS statistics files.
+ */
+void nss_stats_clean(void)
+{
+	/*
+	 * Remove debugfs tree
+	 */
+	if (likely(nss_top_main.top_dentry != NULL)) {
+		debugfs_remove_recursive(nss_top_main.top_dentry);
+		nss_top_main.top_dentry = NULL;
+	}
+}
+
+/*
+ * nss_stats_reset_common_stats()
+ *	Reset common node statistics.
+ */
+void nss_stats_reset_common_stats(uint32_t if_num)
+{
+	if (unlikely(if_num >= NSS_MAX_NET_INTERFACES)) {
+		return;
+	}
+
+	spin_lock_bh(&nss_top_main.stats_lock);
+	memset(nss_top_main.stats_node[if_num], 0, NSS_STATS_NODE_MAX * sizeof(uint64_t));
+	spin_unlock_bh(&nss_top_main.stats_lock);
+}
+
+/*
+ * nss_stats_fill_common_stats()
+ *	Fill common node statistics.
+ */
+size_t nss_stats_fill_common_stats(uint32_t if_num, int instance, char *lbuf, size_t size_wr, size_t size_al, char *node)
+{
+	uint64_t stats_val[NSS_STATS_NODE_MAX];
+	int i;
+	size_t orig_size_wr = size_wr;
+
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; i < NSS_STATS_NODE_MAX; i++) {
+		stats_val[i] = nss_top_main.stats_node[if_num][i];
+	}
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+	size_wr += nss_stats_print(node, NULL, instance, nss_strings_stats_node, stats_val, NSS_STATS_NODE_MAX, lbuf, size_wr, size_al);
+	return size_wr - orig_size_wr;
+}
+
+/*
+ * nss_stats_banner()
+ *	Printing banner for node.
+ */
+size_t nss_stats_banner(char *lbuf, size_t size_wr, size_t size_al, char *node, int core)
+{
+	uint16_t banner_char_length, i;
+	size_t orig_size_wr = size_wr;
+	char node_upr[NSS_STATS_NODE_NAME_MAX + 1];
+
+	if (strlen(node) > NSS_STATS_NODE_NAME_MAX) {
+		nss_warning("Node name %s larger than %d characters\n", node, NSS_STATS_NODE_NAME_MAX);
+		return 0;
+	}
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+	for (i = 0; i < NSS_STATS_BANNER_MAX_LENGTH ; i++) {
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "_");
+	}
+	if (core > NSS_STATS_SINGLE_CORE) {
+		banner_char_length = (uint16_t)((NSS_STATS_BANNER_MAX_LENGTH - (strlen(node) + NSS_STATS_BANNER_SPACES)) / 2);
+	} else {
+		banner_char_length = (uint16_t)((NSS_STATS_BANNER_MAX_LENGTH - (strlen(node) + 2)) / 2);
+	}
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\n");
+	for (i = 0; i < banner_char_length; i++) {
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "<");
+	}
+
+	strlcpy(node_upr, node, NSS_STATS_NODE_NAME_MAX);
+	for (i = 0; node_upr[i] != '\0' && i < NSS_STATS_NODE_NAME_MAX; i++) {
+		node_upr[i] = toupper(node_upr[i]);
+	}
+
+	/*
+	 * TODO: Enhance so that both core0 and core1 print the same way for a
+	 * node that has presence in both cores. i.e. Core0 should have [CORE 0]
+	 * and not just Core1.
+	 */
+	if (core > 1) {
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, " %s [CORE %d] ", node_upr, core);
+	} else {
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, " %s ", node_upr);
+	}
+	for (i = 0; i < banner_char_length; i++) {
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, ">");
+	}
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+	for (i = 0; i < NSS_STATS_BANNER_MAX_LENGTH; i++) {
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "_");
+	}
+
+	size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n\n");
+	return size_wr - orig_size_wr;
+}
+
+/*
+ * nss_stats_print()
+ *	Helper API to print stats.
+ */
+size_t nss_stats_print(char *node, char *stat_details, int instance, struct nss_stats_info *stats_info,
+				uint64_t *stats_val, uint16_t max, char *lbuf, size_t size_wr, size_t size_al)
+{
+	uint16_t i, j;
+	uint16_t maxlen = 0;
+	char stats_string[NSS_STATS_MAX_STR_LENGTH];
+	size_t orig_size_wr = size_wr;
+	char node_lwr[NSS_STATS_NODE_NAME_MAX + 1];
+
+	if (strlen(node) > NSS_STATS_NODE_NAME_MAX) {
+		nss_warning("Node name %s (%u chars) is longer than max chars of %d\n",
+				node, (uint32_t)strlen(node), NSS_STATS_NODE_NAME_MAX);
+		return 0;
+	}
+
+	/*
+	 * Calculating the maximum of the array for indentation purposes.
+	 */
+	for (i = 0; i < max; i++){
+		if (strlen(stats_info[i].stats_name) > maxlen) {
+			maxlen = strlen(stats_info[i].stats_name);
+		}
+	}
+
+	if (stat_details != NULL) {
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n#%s\n\n", stat_details);
+	}
+
+	for (i = 0; i < max; i++){
+		if (nonzero_stats_print == 1 && stats_val[i] == 0) {
+			continue;
+		}
+
+		strlcpy(stats_string, stats_info[i].stats_name, NSS_STATS_MAX_STR_LENGTH);
+
+		/*
+		 * Converting  uppercase to lower case.
+		 */
+		for (j = 0; stats_string[j] != '\0' && j < NSS_STATS_MAX_STR_LENGTH; j++) {
+			stats_string[j] = tolower(stats_string[j]);
+		}
+
+		strlcpy(node_lwr, node, NSS_STATS_NODE_NAME_MAX);
+		for (j = 0; node_lwr[j] != '\0' && j < NSS_STATS_NODE_NAME_MAX; j++) {
+			node_lwr[j] = tolower(node_lwr[j]);
+		}
+
+		/*
+		 * Space before %s is needed to avoid printing stat name from start of the line.
+		 */
+		if (instance < 0) {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\t%s_%s", node_lwr, stats_string);
+		} else {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\t%s[%d]_%s", node_lwr, instance, stats_string);
+		}
+
+		for (j = 0; j < (1 + maxlen - strlen(stats_string)); j++){
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, " ");
+		}
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "= %llu", stats_val[i]);
+		size_wr = nss_stats_spacing(stats_val[i], lbuf, size_wr, size_al);
+
+		/*
+		 * Switch case will take care of the indentation and spacing details.
+		 */
+		switch (stats_info[i].stats_type) {
+		case NSS_STATS_TYPE_COMMON:
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "common\n");
+			break;
+
+		case NSS_STATS_TYPE_SPECIAL:
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "special\n");
+			break;
+
+		case NSS_STATS_TYPE_DROP:
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "drop\n");
+			break;
+
+		case NSS_STATS_TYPE_ERROR:
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "error\n");
+			break;
+
+		case NSS_STATS_TYPE_EXCEPTION:
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "exception\n");
+			break;
+
+		default:
+			nss_warning("unknown statistics type");
+			break;
+		}
+	}
+
+	return size_wr - orig_size_wr;
+}
+
+/*
+ * nss_stats_create_dentry()
+ *	Create statistics debug entry for subsystem.
+ */
+void nss_stats_create_dentry(char *name, const struct file_operations *ops)
+{
+	if (!debugfs_create_file(name, 0400, nss_top_main.stats_dentry, &nss_top_main, ops)) {
+		nss_warning("Failed to create debug entry for subsystem %s\n", name);
+	}
+}
+
+/*
+ * TODO: Move the rest of the code to (nss_wt_stats.c, nss_gmac_stats.c) accordingly.
+ */
+
+/*
+ * gmac_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(gmac);
+
+/*
+ * wt_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(wt);
+
+/*
+ * nss_stats_init()
+ *	Enable NSS statistics.
+ */
+void nss_stats_init(void)
+{
+	struct dentry *core_dentry = NULL;
+	struct dentry *wt_dentry = NULL;
+	char file_name[10];
+	int i;
+
+	/*
+	 * NSS driver entry
+	 */
+	nss_top_main.top_dentry = debugfs_create_dir("qca-nss-drv", NULL);
+	if (unlikely(nss_top_main.top_dentry == NULL)) {
+		nss_warning("Failed to create qca-nss-drv directory in debugfs");
+
+		/*
+		 * Non availability of debugfs directory is not a catastrophy.
+		 * We can still go ahead with other initialization.
+		 */
+		return;
+	}
+
+	nss_top_main.stats_dentry = debugfs_create_dir("stats", nss_top_main.top_dentry);
+	if (unlikely(nss_top_main.stats_dentry == NULL)) {
+		nss_warning("Failed to create qca-nss-drv directory in debugfs");
+
+		/*
+		 * Non availability of debugfs directory is not a catastrophy.
+		 * We can still go ahead with rest of initialization.
+		 */
+		return;
+	}
+
+	/*
+	 * Create files to obtain statistics.
+	 */
+
+	/*
+	 * drv_stats
+	 */
+	nss_drv_stats_dentry_create();
+
+	/*
+	 * gmac_stats
+	 */
+	nss_stats_create_dentry("gmac", &nss_gmac_stats_ops);
+
+	/*
+	 * Per-project stats
+	 */
+	nss_top_main.project_dentry = debugfs_create_dir("project",
+						nss_top_main.stats_dentry);
+	if (unlikely(nss_top_main.project_dentry == NULL)) {
+		nss_warning("Failed to create qca-nss-drv/stats/project directory in debugfs");
+		return;
+	}
+
+	for (i = 0; i < nss_top_main.num_nss; ++i) {
+		memset(file_name, 0, sizeof(file_name));
+		scnprintf(file_name, sizeof(file_name), "core%d", i);
+		core_dentry = debugfs_create_dir(file_name,
+						nss_top_main.project_dentry);
+		if (unlikely(core_dentry == NULL)) {
+			nss_warning("Failed to create qca-nss-drv/stats/project/core%d directory in debugfs", i);
+			return;
+		}
+
+		wt_dentry = debugfs_create_file("worker_threads",
+						0400,
+						core_dentry,
+						&(nss_top_main.nss[i]),
+						&nss_wt_stats_ops);
+		if (unlikely(wt_dentry == NULL)) {
+			nss_warning("Failed to create qca-nss-drv/stats/project/core%d/worker_threads file in debugfs", i);
+			return;
+		}
+	}
+
+	nss_log_init();
+}
diff --git a/qca-nss-drv/nss_stats.h b/qca-nss-drv/nss_stats.h
new file mode 100644
index 0000000..385c71a
--- /dev/null
+++ b/qca-nss-drv/nss_stats.h
@@ -0,0 +1,76 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2019-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_stats.h
+ *	printing stats header file
+ */
+
+#ifndef __NSS_STATS_PRINT_H
+#define __NSS_STATS_PRINT_H
+#include <linux/ctype.h>
+#include <nss_drv_stats.h>
+#include <nss_def.h>
+#include <nss_stats_public.h>
+
+/*
+ * Defines to be used by single instance/core packages.
+*/
+#define NSS_STATS_SINGLE_CORE -1
+#define NSS_STATS_SINGLE_INSTANCE -1
+
+/*
+ * Number of Extra outputlines for future reference to add new stats + start tag line + end tag line + three blank lines
+ */
+#define NSS_STATS_EXTRA_OUTPUT_LINES 35
+
+#define NSS_STATS_DECLARE_FILE_OPERATIONS(name) \
+static const struct file_operations nss_##name##_stats_ops = { \
+	.open = nss_stats_open, \
+	.read = nss_##name##_stats_read, \
+	.llseek = generic_file_llseek, \
+	.release = nss_stats_release, \
+};
+
+/*
+ * Private data for every file descriptor
+ */
+struct nss_stats_data {
+	uint32_t if_num;	/**< Interface number for stats */
+	uint32_t index;		/**< Index for GRE_REDIR stats */
+	uint32_t edma_id;	/**< EDMA port ID or ring ID */
+	struct nss_ctx_instance *nss_ctx;
+				/**< The core for project stats */
+};
+
+/*
+ * Structure definition carrying stats info.
+ */
+struct nss_stats_info {
+	char stats_name[NSS_STATS_MAX_STR_LENGTH];	/* stat name */
+	enum nss_stats_types stats_type;		/* enum that tags stat type  */
+};
+
+extern void nss_stats_register_sysctl(void);
+void nss_stats_init(void);
+extern int nss_stats_release(struct inode *inode, struct file *filp);
+extern int nss_stats_open(struct inode *inode, struct file *filp);
+void nss_stats_create_dentry(char *name, const struct file_operations *ops);
+extern void nss_stats_reset_common_stats(uint32_t if_num);
+extern size_t nss_stats_fill_common_stats(uint32_t if_num, int instance, char *lbuf, size_t size_wr, size_t size_al, char *node);
+extern size_t nss_stats_banner(char *lbuf , size_t size_wr, size_t size_al, char *node, int core);
+extern size_t nss_stats_print(char *node, char *stat_details, int instance, struct nss_stats_info *stats_info, uint64_t *stats_val, uint16_t max, char *lbuf, size_t size_wr, size_t size_al);
+#endif /* __NSS_STATS_H */
diff --git a/qca-nss-drv/nss_strings.c b/qca-nss-drv/nss_strings.c
new file mode 100644
index 0000000..432b154
--- /dev/null
+++ b/qca-nss-drv/nss_strings.c
@@ -0,0 +1,148 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_strings.c
+ *	NSS driver strings APIs.
+ */
+
+#include "nss_strings.h"
+#include "nss_core.h"
+#include "nss_drv_strings.h"
+
+/*
+ * common stats
+ */
+struct nss_stats_info nss_strings_stats_node[NSS_STATS_NODE_MAX] = {
+	{"rx_pkts"              , NSS_STATS_TYPE_COMMON},
+	{"rx_byts"              , NSS_STATS_TYPE_COMMON},
+	{"tx_pkts"              , NSS_STATS_TYPE_COMMON},
+	{"tx_byts"              , NSS_STATS_TYPE_COMMON},
+	{"rx_queue[0]_drops"    , NSS_STATS_TYPE_DROP},
+	{"rx_queue[1]_drops"    , NSS_STATS_TYPE_DROP},
+	{"rx_queue[2]_drops"    , NSS_STATS_TYPE_DROP},
+	{"rx_queue[3]_drops"    , NSS_STATS_TYPE_DROP}
+};
+
+/*
+ * nss_strings_print()
+ *	Helper API to print stats names
+ */
+size_t nss_strings_print(char __user *ubuf, size_t sz, loff_t *ppos, struct nss_stats_info *stats_info, uint16_t max)
+{
+	int32_t i;
+	size_t size_al = (NSS_STATS_MAX_STR_LENGTH + 12) * max;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (!lbuf) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	for (i = 0; i < max; i++) {
+		/*
+		 * Print what we have but don't exceed the buffer.
+		 */
+		if (size_wr >= size_al) {
+			nss_info_always("Buffer overflowed.\n");
+			break;
+		}
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+				"\t%d , %s\n", stats_info[i].stats_type, stats_info[i].stats_name);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+
+	return bytes_read;
+}
+
+/*
+ * nss_strings_create_dentry()
+ *	Create strings debug entry for subsystem.
+ */
+void nss_strings_create_dentry(char *name, const struct file_operations *ops)
+{
+	if (!nss_top_main.strings_dentry || !debugfs_create_file(name, 0400, nss_top_main.strings_dentry, &nss_top_main, ops)) {
+		nss_warning("Failed to create debug entry for subsystem %s\n", name);
+	}
+}
+
+/*
+ * nss_strings_open()
+ */
+int nss_strings_open(struct inode *inode, struct file *filp)
+{
+	struct nss_strings_data *data = NULL;
+
+	data = kzalloc(sizeof(struct nss_strings_data), GFP_KERNEL);
+	if (!data) {
+		return -ENOMEM;
+	}
+	data->if_num = NSS_DYNAMIC_IF_START;
+	data->nss_ctx = (struct nss_ctx_instance *)(inode->i_private);
+	filp->private_data = data;
+
+	return 0;
+}
+
+/*
+ * nss_strings_release()
+ */
+int nss_strings_release(struct inode *inode, struct file *filp)
+{
+	struct nss_strings_data *data = filp->private_data;
+
+	if (data) {
+		kfree(data);
+	}
+
+	return 0;
+}
+
+/*
+ * nss_common_node_stats_strings_read()
+ *	Read common node statistics names.
+ */
+static ssize_t nss_common_node_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_strings_stats_node, NSS_STATS_NODE_MAX);
+}
+
+/*
+ * nss_common_node_stats_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(common_node_stats);
+
+/*
+ * nss_strings_init()
+ *	Enable NSS statistics
+ */
+void nss_strings_init(void)
+{
+	nss_top_main.strings_dentry = debugfs_create_dir("strings", nss_top_main.top_dentry);
+	if (unlikely(nss_top_main.strings_dentry == NULL)) {
+		nss_warning("Failed to create strings directory in debugfs/qca-nss-drv");
+		return;
+	}
+
+	/*
+	 * Common node statistics
+	 */
+	nss_strings_create_dentry("common_node_stats", &nss_common_node_stats_strings_ops);
+}
diff --git a/qca-nss-drv/nss_strings.h b/qca-nss-drv/nss_strings.h
new file mode 100644
index 0000000..32bf466
--- /dev/null
+++ b/qca-nss-drv/nss_strings.h
@@ -0,0 +1,52 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_strings.h
+ *	NSS driver strings header file.
+ */
+
+#ifndef __NSS_STRINGS_H
+#define __NSS_STRINGS_H
+
+#include <linux/debugfs.h>
+#include "nss_stats.h"
+
+#define NSS_STRINGS_DECLARE_FILE_OPERATIONS(name) \
+static const struct file_operations nss_##name##_strings_ops = { \
+	.open = nss_strings_open, \
+	.read = nss_##name##_strings_read, \
+	.llseek = generic_file_llseek, \
+	.release = nss_strings_release, \
+}
+
+/*
+ * Private data for every file descriptor
+ */
+struct nss_strings_data {
+	uint32_t if_num;			/**< Interface number for stats */
+	struct nss_ctx_instance *nss_ctx;	/**< The core for project stats */
+};
+
+extern struct nss_stats_info nss_strings_stats_node[NSS_STATS_NODE_MAX];
+void nss_strings_init(void);
+int nss_strings_release(struct inode *inode, struct file *filp);
+int nss_strings_open(struct inode *inode, struct file *filp);
+void nss_strings_create_dentry(char *name, const struct file_operations *ops);
+size_t nss_strings_fill_common_stats(char __user *ubuf, size_t sz, loff_t *ppos);
+size_t nss_strings_print(char __user *ubuf, size_t sz, loff_t *ppos, struct nss_stats_info *stats_info, uint16_t max);
+
+#endif /* __NSS_STRINGS_H */
diff --git a/qca-nss-drv/nss_tls.c b/qca-nss-drv/nss_tls.c
new file mode 100644
index 0000000..ff53363
--- /dev/null
+++ b/qca-nss-drv/nss_tls.c
@@ -0,0 +1,475 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_tls_log.h"
+#include "nss_tls_stats.h"
+#include "nss_tls_strings.h"
+
+#define NSS_TLS_INTERFACE_MAX_LONG BITS_TO_LONGS(NSS_MAX_NET_INTERFACES)
+#define NSS_TLS_TX_TIMEOUT 3000 /* 3 Seconds */
+
+/*
+ * Private data structure for handling synchronous messaging.
+ */
+static struct nss_tls_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	struct nss_tls_msg ntcm;
+	unsigned long if_map[NSS_TLS_INTERFACE_MAX_LONG];
+} tls_pvt;
+
+/*
+ * nss_tls_verify_ifnum()
+ *	Verify if the interface number is a TLS interface.
+ */
+static bool nss_tls_verify_ifnum(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	enum nss_dynamic_interface_type type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+
+	if (type == NSS_DYNAMIC_INTERFACE_TYPE_TLS_INNER)
+		return true;
+
+	if (type == NSS_DYNAMIC_INTERFACE_TYPE_TLS_OUTER)
+		return true;
+
+	if (if_num == NSS_TLS_INTERFACE)
+		return true;
+
+	return false;
+}
+
+/*
+ * nss_tls_handler()
+ *	Handle NSS -> HLOS messages for tls tunnel
+ */
+static void nss_tls_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, void *data)
+{
+	nss_tls_msg_callback_t cb;
+	void *app_data;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	nss_trace("%px: handle event for interface num :%u", nss_ctx, ncm->interface);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_TLS_MSG_MAX) {
+		nss_warning("%px:Bad message type(%d) for TLS interface %d", nss_ctx, ncm->type, ncm->interface);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_tls_msg)) {
+		nss_warning("%px:Bad message length(%d)", nss_ctx, ncm->len);
+		return;
+	}
+
+	if (ncm->type == NSS_TLS_MSG_TYPE_CTX_SYNC) {
+		nss_tls_stats_sync(nss_ctx, ncm);
+		nss_tls_stats_notify(nss_ctx, ncm->interface);
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->nss_rx_interface_handlers[ncm->interface].app_data;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Trace messages.
+	 */
+	nss_tls_log_rx_msg((struct nss_tls_msg *)ncm);
+
+	/*
+	 * Callback
+	 */
+	cb = (nss_tls_msg_callback_t)ncm->cb;
+	app_data = (void *)ncm->app_data;
+
+	/*
+	 * Call TLS session callback
+	 */
+	if (!cb) {
+		nss_warning("%px: No callback for tls session interface %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	nss_trace("%px: calling tlsmgr event handler(%u)", nss_ctx, ncm->interface);
+	cb(app_data, ncm);
+}
+
+/*
+ * nss_tls_sync_resp()
+ *	Callback to handle the completion of HLOS-->NSS messages.
+ */
+static void nss_tls_sync_resp(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_tls_msg *pvt_msg = app_data;
+	struct nss_tls_msg *resp_msg = container_of(ncm, struct nss_tls_msg, cm);
+
+	/*
+	 * Copy response message to pvt message
+	 */
+	memcpy(pvt_msg, resp_msg, sizeof(*resp_msg));
+
+	/*
+	 * Write memory barrier
+	 */
+	smp_wmb();
+
+	complete(&tls_pvt.complete);
+}
+
+/*
+ * nss_tls_ifmap_get()
+ *	Return TLS active interfaces map.
+ */
+unsigned long *nss_tls_ifmap_get(void)
+{
+	return tls_pvt.if_map;
+}
+
+/*
+ * nss_tls_tx_buf()
+ *	Transmit buffer over TLS interface
+ */
+nss_tx_status_t nss_tls_tx_buf(struct sk_buff *skb, uint32_t if_num, struct nss_ctx_instance *nss_ctx)
+{
+	int32_t status;
+
+	if (!nss_tls_verify_ifnum(nss_ctx, if_num))
+		return NSS_TX_FAILURE;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (unlikely(nss_ctx->state != NSS_CORE_STATE_INITIALIZED)) {
+		nss_warning("%px: tx_data packet dropped as core not ready", nss_ctx);
+		return NSS_TX_FAILURE_NOT_READY;
+	}
+
+	status = nss_core_send_buffer(nss_ctx, if_num, skb, NSS_IF_H2N_DATA_QUEUE, H2N_BUFFER_PACKET, 0);
+	switch (status) {
+	case NSS_CORE_STATUS_SUCCESS:
+		break;
+
+	case NSS_CORE_STATUS_FAILURE_QUEUE: /* queue full condition */
+		nss_warning("%px: H2N queue full for tx_buf", nss_ctx);
+		return NSS_TX_FAILURE_QUEUE;
+
+	default:
+		nss_warning("%px: general failure for tx_buf", nss_ctx);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Kick the NSS awake so it can process our new entry.
+	 */
+	nss_hal_send_interrupt(nss_ctx, NSS_H2N_INTR_DATA_COMMAND_QUEUE);
+
+	return NSS_TX_SUCCESS;
+}
+EXPORT_SYMBOL(nss_tls_tx_buf);
+
+/*
+ * nss_tls_tx_msg()
+ *	Transmit a TLS message to NSS firmware
+ */
+nss_tx_status_t nss_tls_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_tls_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	if (ncm->type >= NSS_TLS_MSG_MAX) {
+		nss_warning("%px: tls message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	if (!nss_tls_verify_ifnum(nss_ctx, ncm->interface)) {
+		nss_warning("%px: tls message interface is bad: %u", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_tls_log_tx_msg(msg);
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_tls_tx_msg);
+
+/*
+ * nss_tls_tx_msg_sync()
+ *	Transmit a TLS message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_tls_tx_msg_sync(struct nss_ctx_instance *nss_ctx, uint32_t if_num,
+					enum nss_tls_msg_type type, uint16_t len,
+					struct nss_tls_msg *ntcm)
+{
+	struct nss_tls_msg *local_ntcm = &tls_pvt.ntcm;
+	nss_tx_status_t status;
+	int ret = 0;
+
+	/*
+	 * Length of the message should be the based on type
+	 */
+	if (len > sizeof(struct nss_tls_msg)) {
+		nss_warning("%px: Invalid message length(%u), type (%d), I/F(%u)\n", nss_ctx, len, type, if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	down(&tls_pvt.sem);
+
+	/*
+	 * We need to copy the message content into the actual message
+	 * to be sent to NSS
+	 */
+	memset(local_ntcm, 0, sizeof(*local_ntcm));
+
+	nss_tls_msg_init(local_ntcm, if_num, type, len, nss_tls_sync_resp, local_ntcm);
+	memcpy(&local_ntcm->msg, &ntcm->msg, len);
+
+	status = nss_tls_tx_msg(nss_ctx, local_ntcm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Failed to send message\n", nss_ctx);
+		goto done;
+	}
+
+	ret = wait_for_completion_timeout(&tls_pvt.complete, msecs_to_jiffies(NSS_TLS_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: Failed to receive response, timeout(%d)\n", nss_ctx, ret);
+		status = NSS_TX_FAILURE_NOT_READY;
+		goto done;
+	}
+
+	/*
+	 * Read memory barrier
+	 */
+	smp_rmb();
+
+	if (local_ntcm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		status = NSS_TX_FAILURE;
+		ntcm->cm.response = local_ntcm->cm.response;
+		ntcm->cm.error = local_ntcm->cm.error;
+		goto done;
+	}
+
+	/*
+	 * Copy the message received
+	 */
+	memcpy(&ntcm->msg, &local_ntcm->msg, len);
+
+done:
+	up(&tls_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_tls_tx_msg_sync);
+
+/*
+ * nss_tls_notify_register()
+ *	Register a handler for notification from NSS firmware.
+ */
+struct nss_ctx_instance *nss_tls_notify_register(uint32_t if_num, nss_tls_msg_callback_t ev_cb, void *app_data)
+{
+	struct nss_ctx_instance *nss_ctx = nss_tls_get_context();
+	uint32_t ret;
+
+	BUG_ON(!nss_ctx);
+
+	ret = nss_core_register_handler(nss_ctx, if_num, nss_tls_handler, app_data);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to register event handler for interface(%u)", nss_ctx, if_num);
+		return NULL;
+	}
+
+	ret = nss_core_register_msg_handler(nss_ctx, if_num, ev_cb);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_core_unregister_handler(nss_ctx, if_num);
+		nss_warning("%px: unable to register event handler for interface(%u)", nss_ctx, if_num);
+		return NULL;
+	}
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_tls_notify_register);
+
+/*
+ * nss_tls_notify_unregister()
+ *	Unregister notification callback handler.
+ */
+void nss_tls_notify_unregister(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_tls_get_context();
+	uint32_t ret;
+
+	BUG_ON(!nss_ctx);
+
+	ret = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to un register event handler for interface(%u)", nss_ctx, if_num);
+		return;
+	}
+
+	ret = nss_core_unregister_handler(nss_ctx, if_num);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to un register event handler for interface(%u)", nss_ctx, if_num);
+		return;
+	}
+
+	return;
+}
+EXPORT_SYMBOL(nss_tls_notify_unregister);
+
+/*
+ * nss_tls_register_if()
+ *	Register data and event callback handlers for dynamic interface.
+ */
+struct nss_ctx_instance *nss_tls_register_if(uint32_t if_num,
+						  nss_tls_data_callback_t data_cb,
+						  nss_tls_msg_callback_t ev_cb,
+						  struct net_device *netdev,
+						  uint32_t features,
+						  uint32_t type,
+						  void *app_data)
+{
+	struct nss_ctx_instance *nss_ctx = nss_tls_get_context();
+	uint32_t ret;
+
+	if (!nss_tls_verify_ifnum(nss_ctx, if_num)) {
+		nss_warning("%px: TLS Interface is not dynamic:%u", nss_ctx, if_num);
+		return NULL;
+	}
+
+	if (nss_ctx->subsys_dp_register[if_num].ndev) {
+		nss_warning("%px: Cannot find free slot for TLS NSS I/F:%u", nss_ctx, if_num);
+		return NULL;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, data_cb, NULL, app_data, netdev, features);
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num, type);
+
+	ret = nss_core_register_handler(nss_ctx, if_num, nss_tls_handler, app_data);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to register event handler for interface(%u)", nss_ctx, if_num);
+		return NULL;
+	}
+
+	ret = nss_core_register_msg_handler(nss_ctx, if_num, ev_cb);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_core_unregister_handler(nss_ctx, if_num);
+		nss_warning("%px: unable to register event handler for interface(%u)", nss_ctx, if_num);
+		return NULL;
+	}
+
+	/*
+	 * Atomically set the bitmap for the interface number
+	 */
+	set_bit(if_num, tls_pvt.if_map);
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_tls_register_if);
+
+/*
+ * nss_tls_unregister_if()
+ *	Unregister data and event callback handlers for the interface.
+ */
+void nss_tls_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_tls_get_context();
+	uint32_t ret;
+
+	if (!nss_ctx->subsys_dp_register[if_num].ndev) {
+		nss_warning("%px: Cannot find registered netdev for TLS NSS I/F:%u", nss_ctx, if_num);
+		return;
+	}
+
+	/*
+	 * Atomically clear the bitmap for the interface number
+	 */
+	clear_bit(if_num, tls_pvt.if_map);
+
+	ret = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to un register event handler for interface(%u)", nss_ctx, if_num);
+		return;
+	}
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_tls_unregister_if);
+
+/*
+ * nss_tls_get_context()
+ *	Return TLS NSS context.
+ */
+struct nss_ctx_instance *nss_tls_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.tls_handler_id];
+}
+EXPORT_SYMBOL(nss_tls_get_context);
+
+/*
+ * nss_tls_get_device()
+ *	Gets the original device from probe.
+ */
+struct device *nss_tls_get_dev(struct nss_ctx_instance *nss_ctx)
+{
+	return nss_ctx->dev;
+}
+EXPORT_SYMBOL(nss_tls_get_dev);
+
+/*
+ * nss_tls_msg_init()
+ *	Initialize nss_tls msg to be sent asynchronously.
+ */
+void nss_tls_msg_init(struct nss_tls_msg *ncm, uint32_t if_num, uint32_t type, uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+EXPORT_SYMBOL(nss_tls_msg_init);
+
+/*
+ * nss_tls_msg_sync_init()
+ *	Initialize nss_tls_msg to be sent synchronously.
+ */
+void nss_tls_msg_sync_init(struct nss_tls_msg *ncm, uint32_t if_num, uint32_t type, uint32_t len)
+{
+	nss_cmn_msg_sync_init(&ncm->cm, if_num, type, len);
+}
+EXPORT_SYMBOL(nss_tls_msg_sync_init);
+
+/*
+ * nss_tls_register_handler()
+ *	TLS initialization.
+ */
+void nss_tls_register_handler(void)
+{
+	sema_init(&tls_pvt.sem, 1);
+	init_completion(&tls_pvt.complete);
+	nss_tls_stats_dentry_create();
+	nss_tls_strings_dentry_create();
+}
diff --git a/qca-nss-drv/nss_tls_log.c b/qca-nss-drv/nss_tls_log.c
new file mode 100644
index 0000000..11afe45
--- /dev/null
+++ b/qca-nss-drv/nss_tls_log.c
@@ -0,0 +1,167 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+/*
+ * nss_tls_log.c
+ *	NSS TLS logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_tls_log_message_types_str
+ *	TLS message strings
+ */
+static int8_t *nss_tls_log_message_types_str[NSS_TLS_MSG_MAX] __maybe_unused = {
+	"TLS Node Configure",
+	"TLS Context Configure",
+	"TLS Context Deconfigure",
+	"TLS Cipher Update",
+	"TLS Context Sync",
+	"TLS Node Sync",
+};
+
+/*
+ * nss_tls_log_error_response_types_str
+ *	Strings for error types for TLS messages
+ */
+static int8_t *nss_tls_log_error_response_types_str[NSS_TLS_ERROR_MAX] __maybe_unused = {
+	"TLS no_error",
+	"TLS unknown message",
+	"TLS fail node already config",
+	"TLS fail inner ctx",
+	"TLS fail outer ctx",
+	"TLS fail req pool",
+	"TLS invalid block len",
+	"TLS invalid hash len",
+	"TLS invalid version",
+	"TLS invalid context words",
+	"TLS fail alloc hwctx",
+	"TLS fail copy ctx",
+	"TLS Invalid algorithm",
+	"TLS fail nomem"
+};
+
+/*
+ * nss_tls_node_config_msg()
+ *	Log TLS node configure message.
+ */
+static void nss_tls_node_config_msg(struct nss_tls_msg *ntm)
+{
+	nss_trace("%px: NSS TLS Node Configure Message:\n"
+			"TLS Interface: %d\n", ntm, ntm->cm.interface);
+}
+
+/*
+ * nss_tls_ctx_config_msg()
+ *	Log TLS session configure message.
+ */
+static void nss_tls_ctx_config_msg(struct nss_tls_msg *ntm)
+{
+	struct nss_tls_ctx_config *ntccm __maybe_unused = &ntm->msg.ctx_cfg;
+	nss_trace("%px: NSS TLS Context Configure Message:\n"
+		"TLS Except if_num: %d\n",
+		ntccm, ntccm->except_ifnum);
+}
+
+/*
+ * nss_tls_cipher_upddate_msg()
+ *	Log TLS Cipher Update message.
+ */
+static void nss_tls_cipher_update_msg(struct nss_tls_msg *ntm)
+{
+	struct nss_tls_cipher_update *ntcum __maybe_unused = &ntm->msg.cipher_update;
+	nss_trace("%px: NSS TLS Cipher Update message\n"
+		"TLS crypto index: %d\n",
+		ntcum, ntcum->crypto_idx);
+}
+
+/*
+ * nss_tls_log_verbose()
+ *	Log message contents.
+ */
+static void nss_tls_log_verbose(struct nss_tls_msg *ntm)
+{
+	switch (ntm->cm.type) {
+	case NSS_TLS_MSG_TYPE_NODE_CONFIG:
+		nss_tls_node_config_msg(ntm);
+		break;
+
+	case NSS_TLS_MSG_TYPE_CIPHER_UPDATE:
+		nss_tls_cipher_update_msg(ntm);
+		break;
+
+	case NSS_TLS_MSG_TYPE_CTX_CONFIG:
+		nss_tls_ctx_config_msg(ntm);
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", ntm);
+		break;
+	}
+}
+
+/*
+ * nss_tls_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_tls_log_tx_msg(struct nss_tls_msg *ntm)
+{
+	if (ntm->cm.type >= NSS_TLS_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", ntm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ntm, ntm->cm.type, nss_tls_log_message_types_str[ntm->cm.type]);
+	nss_tls_log_verbose(ntm);
+}
+
+/*
+ * nss_tls_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_tls_log_rx_msg(struct nss_tls_msg *ntm)
+{
+	if (ntm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ntm);
+		return;
+	}
+
+	if (ntm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ntm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ntm, ntm->cm.type,
+			nss_tls_log_message_types_str[ntm->cm.type],
+			ntm->cm.response, nss_cmn_response_str[ntm->cm.response]);
+		goto verbose;
+	}
+
+	if (ntm->cm.error >= NSS_TLS_ERROR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			ntm, ntm->cm.type, nss_tls_log_message_types_str[ntm->cm.type],
+			ntm->cm.response, nss_cmn_response_str[ntm->cm.response],
+			ntm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		ntm, ntm->cm.type, nss_tls_log_message_types_str[ntm->cm.type],
+		ntm->cm.response, nss_cmn_response_str[ntm->cm.response],
+		ntm->cm.error, nss_tls_log_error_response_types_str[ntm->cm.error]);
+
+verbose:
+	nss_tls_log_verbose(ntm);
+}
diff --git a/qca-nss-drv/nss_tls_log.h b/qca-nss-drv/nss_tls_log.h
new file mode 100644
index 0000000..37846c2
--- /dev/null
+++ b/qca-nss-drv/nss_tls_log.h
@@ -0,0 +1,39 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
+ **************************************************************************
+ */
+
+#ifndef __NSS_TLS_LOG_H
+#define __NSS_TLS_LOG_H
+
+/*
+ * nss_tls_log.h
+ *	NSS TLS Log Header File
+ */
+
+/*
+ * nss_tls_log_tx_msg
+ *	Logs a TLS message that is sent to the NSS firmware.
+ */
+void nss_tls_log_tx_msg(struct nss_tls_msg *ndm);
+
+/*
+ * nss_tls_log_rx_msg
+ *	Logs a TLS message that is received from the NSS firmware.
+ */
+void nss_tls_log_rx_msg(struct nss_tls_msg *ndm);
+
+#endif /* __NSS_TLS_LOG_H */
diff --git a/qca-nss-drv/nss_tls_stats.c b/qca-nss-drv/nss_tls_stats.c
new file mode 100644
index 0000000..5808270
--- /dev/null
+++ b/qca-nss-drv/nss_tls_stats.c
@@ -0,0 +1,206 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ******************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_tls.h"
+#include "nss_tls_stats.h"
+#include "nss_tls_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_tls_stats_notifier);
+
+/*
+ * Spinlock to protect tls statistics update/read
+ */
+DEFINE_SPINLOCK(nss_tls_stats_lock);
+
+uint64_t nss_tls_stats[NSS_MAX_NET_INTERFACES][NSS_TLS_STATS_MAX];
+
+/*
+ * nss_tls_stats_iface_type()
+ *	Return a string for each interface type.
+ */
+static const char *nss_tls_stats_iface_type(enum nss_dynamic_interface_type type)
+{
+	switch (type) {
+	case NSS_DYNAMIC_INTERFACE_TYPE_TLS_INNER:
+		return "tls_inner";
+
+	case NSS_DYNAMIC_INTERFACE_TYPE_TLS_OUTER:
+		return "tls_outer";
+
+	default:
+		return "invalid_interface";
+	}
+}
+
+/*
+ * nss_tls_stats_read()
+ *	Read tls node statiistics.
+ */
+static ssize_t nss_tls_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	/*
+	 * Max output lines = #stats +
+	 * few blank lines for banner printing + Number of Extra outputlines
+	 * for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_TLS_STATS_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	struct nss_ctx_instance *nss_ctx = nss_tls_get_context();
+	enum nss_dynamic_interface_type type;
+	unsigned long *ifmap;
+	uint64_t *stats_shadow;
+	ssize_t bytes_read = 0;
+	size_t size_wr = 0;
+	uint32_t if_num;
+	int32_t i;
+	int count;
+	char *lbuf;
+
+	ifmap = nss_tls_ifmap_get();
+	count = bitmap_weight(ifmap, NSS_MAX_NET_INTERFACES);
+	if (count) {
+		size_al = size_al * count;
+	}
+
+	lbuf = vzalloc(size_al);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return -ENOMEM;
+	}
+
+	stats_shadow = vzalloc(NSS_TLS_STATS_MAX * 8);
+	if (unlikely(!stats_shadow)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		vfree(lbuf);
+		return -ENOMEM;
+	}
+
+	/*
+	 * Common node stats for each TLS dynamic interface.
+	 */
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "tls stats", NSS_STATS_SINGLE_CORE);
+	for_each_set_bit(if_num, ifmap, NSS_MAX_NET_INTERFACES) {
+
+		type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+		if ((type != NSS_DYNAMIC_INTERFACE_TYPE_TLS_INNER) &&
+			(type != NSS_DYNAMIC_INTERFACE_TYPE_TLS_OUTER)) {
+			continue;
+		}
+
+		spin_lock_bh(&nss_tls_stats_lock);
+		for (i = 0; i < NSS_TLS_STATS_MAX; i++) {
+			stats_shadow[i] = nss_tls_stats[if_num][i];
+		}
+		spin_unlock_bh(&nss_tls_stats_lock);
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n%s if_num:%03u\n",
+					nss_tls_stats_iface_type(type), if_num);
+		size_wr += nss_stats_print("tls", NULL, NSS_STATS_SINGLE_INSTANCE, nss_tls_strings_stats,
+						stats_shadow, NSS_TLS_STATS_MAX, lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	vfree(lbuf);
+	vfree(stats_shadow);
+	return bytes_read;
+}
+
+/*
+ * nss_tls_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(tls);
+
+/*
+ * nss_tls_stats_dentry_create()
+ *	Create tls statistics debug entry.
+ */
+void nss_tls_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("tls", &nss_tls_stats_ops);
+}
+
+/*
+ * nss_tls_stats_sync()
+ *	Update tls node statistics.
+ */
+void nss_tls_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm)
+{
+	struct nss_tls_msg *ndcm = (struct nss_tls_msg *)ncm;
+	struct nss_tls_ctx_stats *ndccs = &ndcm->msg.stats;
+	uint64_t *ctx_stats;
+	uint32_t *msg_stats;
+	int i;
+
+	spin_lock_bh(&nss_tls_stats_lock);
+
+	/*
+	 * Update common node stats,
+	 * Note: TLS only supports a single queue for RX
+	 */
+	msg_stats = (uint32_t *)ndccs;
+	ctx_stats = nss_tls_stats[ncm->interface];
+
+	for (i = 0; i < NSS_TLS_STATS_MAX; i++, ctx_stats++, msg_stats++) {
+		*ctx_stats += *msg_stats;
+	}
+
+	spin_unlock_bh(&nss_tls_stats_lock);
+}
+
+/*
+ * nss_tls_stats_notify()
+ *	Sends notifications to all the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_tls_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_tls_stats_notification tls_stats;
+
+	spin_lock_bh(&nss_tls_stats_lock);
+	tls_stats.core_id = nss_ctx->id;
+	tls_stats.if_num = if_num;
+	memcpy(tls_stats.stats_ctx, nss_tls_stats[if_num], sizeof(tls_stats.stats_ctx));
+	spin_unlock_bh(&nss_tls_stats_lock);
+
+	atomic_notifier_call_chain(&nss_tls_stats_notifier, NSS_STATS_EVENT_NOTIFY, &tls_stats);
+}
+
+/*
+ * nss_tls_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_tls_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_tls_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_tls_stats_unregister_notifier);
+
+/*
+ * nss_tls_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_tls_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_tls_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_tls_stats_register_notifier);
diff --git a/qca-nss-drv/nss_tls_stats.h b/qca-nss-drv/nss_tls_stats.h
new file mode 100644
index 0000000..3883f62
--- /dev/null
+++ b/qca-nss-drv/nss_tls_stats.h
@@ -0,0 +1,28 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ******************************************************************************
+ */
+
+#ifndef __NSS_TLS_STATS_H
+#define __NSS_TLS_STATS_H
+
+#include <nss_cmn.h>
+
+extern void nss_tls_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_tls_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm);
+extern void nss_tls_stats_dentry_create(void);
+
+#endif /* __NSS_TLS_STATS_H */
diff --git a/qca-nss-drv/nss_tls_strings.c b/qca-nss-drv/nss_tls_strings.c
new file mode 100644
index 0000000..8c48548
--- /dev/null
+++ b/qca-nss-drv/nss_tls_strings.c
@@ -0,0 +1,88 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ******************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_strings.h"
+#include "nss_tls_strings.h"
+
+/*
+ * nss_tls_strings_stats
+ *	tls statistics strings.
+ */
+struct nss_stats_info nss_tls_strings_stats[NSS_TLS_STATS_MAX] = {
+	{"rx_pkts",			NSS_STATS_TYPE_COMMON},
+	{"rx_byts",			NSS_STATS_TYPE_COMMON},
+	{"tx_pkts",			NSS_STATS_TYPE_COMMON},
+	{"tx_byts",			NSS_STATS_TYPE_COMMON},
+	{"rx_queue[0]_drops",		NSS_STATS_TYPE_DROP},
+	{"rx_queue[1]_drops",		NSS_STATS_TYPE_DROP},
+	{"rx_queue[2]_drops",		NSS_STATS_TYPE_DROP},
+	{"rx_queue[3]_drops",		NSS_STATS_TYPE_DROP},
+	{"single_rec",			NSS_STATS_TYPE_SPECIAL},
+	{"multi_rec",			NSS_STATS_TYPE_SPECIAL},
+	{"tx_inval_reqs",		NSS_STATS_TYPE_SPECIAL},
+	{"rx_ccs_rec",			NSS_STATS_TYPE_SPECIAL},
+	{"fail_ccs",			NSS_STATS_TYPE_ERROR},
+	{"eth_node_deactive",		NSS_STATS_TYPE_SPECIAL},
+	{"crypto_alloc_success",	NSS_STATS_TYPE_SPECIAL},
+	{"crypto_free_req",		NSS_STATS_TYPE_SPECIAL},
+	{"crypto_free_success",		NSS_STATS_TYPE_SPECIAL},
+	{"fail_crypto_alloc",		NSS_STATS_TYPE_EXCEPTION},
+	{"fail_crypto_lookup",		NSS_STATS_TYPE_EXCEPTION},
+	{"fail_req_alloc",		NSS_STATS_TYPE_ERROR},
+	{"fail_pbuf_stats",		NSS_STATS_TYPE_ERROR},
+	{"fail_ctx_active",		NSS_STATS_TYPE_ERROR},
+	{"hw_len_error",		NSS_STATS_TYPE_ERROR},
+	{"hw_token_error",		NSS_STATS_TYPE_ERROR},
+	{"hw_bypass_error",		NSS_STATS_TYPE_ERROR},
+	{"hw_crypto_error",		NSS_STATS_TYPE_ERROR},
+	{"hw_hash_error",		NSS_STATS_TYPE_ERROR},
+	{"hw_config_error",		NSS_STATS_TYPE_ERROR},
+	{"hw_algo_error",		NSS_STATS_TYPE_ERROR},
+	{"hw_hash_ovf_error",		NSS_STATS_TYPE_ERROR},
+	{"hw_auth_error",		NSS_STATS_TYPE_ERROR},
+	{"hw_pad_verify_error",		NSS_STATS_TYPE_ERROR},
+	{"hw_timeout_error",		NSS_STATS_TYPE_ERROR},
+	{"no_desc_in",			NSS_STATS_TYPE_EXCEPTION},
+	{"no_desc_out",			NSS_STATS_TYPE_EXCEPTION},
+	{"no_reqs",			NSS_STATS_TYPE_EXCEPTION}
+};
+
+/*
+ * nss_tls_strings_read()
+ *	Read tls statistics names
+ */
+static ssize_t nss_tls_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_tls_strings_stats, NSS_TLS_STATS_MAX);
+}
+
+/*
+ * nss_tls_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(tls);
+
+/*
+ * nss_tls_strings_dentry_create()
+ *	Create tls statistics strings debug entry.
+ */
+void nss_tls_strings_dentry_create(void)
+{
+	nss_strings_create_dentry("tls", &nss_tls_strings_ops);
+}
diff --git a/qca-nss-drv/nss_tls_strings.h b/qca-nss-drv/nss_tls_strings.h
new file mode 100644
index 0000000..1509722
--- /dev/null
+++ b/qca-nss-drv/nss_tls_strings.h
@@ -0,0 +1,27 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ******************************************************************************
+ */
+
+#ifndef __NSS_TLS_STRINGS_H
+#define __NSS_TLS_STRINGS_H
+
+#include "nss_tls_stats.h"
+
+extern struct nss_stats_info nss_tls_strings_stats[NSS_TLS_STATS_MAX];
+extern void nss_tls_strings_dentry_create(void);
+
+#endif /* __NSS_TLS_STRINGS_H */
diff --git a/qca-nss-drv/nss_trustsec_tx.c b/qca-nss-drv/nss_trustsec_tx.c
new file mode 100644
index 0000000..2ba6ee6
--- /dev/null
+++ b/qca-nss-drv/nss_trustsec_tx.c
@@ -0,0 +1,299 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_trustsec_tx_stats.h"
+#include "nss_trustsec_tx_log.h"
+
+#define NSS_TRUSTSEC_TX_TIMEOUT 3000 /* 3 Seconds */
+
+/*
+ * Private data structure for trustsec_tx interface
+ */
+static struct nss_trustsec_tx_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+} ttx;
+
+/*
+ * nss_trustsec_tx_handler()
+ *	Handle NSS -> HLOS messages for trustsec_tx
+ */
+static void nss_trustsec_tx_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm,
+				__attribute__((unused))void *app_data)
+{
+	nss_trustsec_tx_msg_callback_t cb;
+	struct nss_trustsec_tx_msg *npm = (struct nss_trustsec_tx_msg *)ncm;
+
+	BUG_ON(ncm->interface != NSS_TRUSTSEC_TX_INTERFACE);
+
+	/*
+	 * Trace messages.
+	 */
+	nss_trustsec_tx_log_rx_msg(npm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_TRUSTSEC_TX_MSG_MAX) {
+		nss_warning("%px: received invalid message %d for trustsec_tx interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_trustsec_tx_msg)) {
+		nss_warning("%px: message size incorrect: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	switch (ncm->type) {
+	case NSS_TRUSTSEC_TX_MSG_STATS_SYNC:
+		/*
+		 * Update trustsec_tx statistics.
+		 */
+		nss_trustsec_tx_stats_sync(nss_ctx, &npm->msg.stats_sync);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, trustsec_tx sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->subsys_dp_register[ncm->interface].ndev;
+	}
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_trustsec_tx_msg_callback_t)ncm->cb;
+
+	cb((void *)ncm->app_data, npm);
+}
+
+/*
+ * nss_trustsec_tx_msg()
+ *	Transmit a trustsec_tx message to NSSFW
+ */
+nss_tx_status_t nss_trustsec_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_trustsec_tx_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace messages.
+	 */
+	nss_trustsec_tx_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (ncm->interface != NSS_TRUSTSEC_TX_INTERFACE) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_TRUSTSEC_TX_MSG_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_trustsec_tx_msg);
+
+/*
+ * nss_trustsec_tx_callback
+ *	Callback to handle the completion of NSS ->HLOS messages.
+ */
+static void nss_trustsec_tx_callback(void *app_data, struct nss_trustsec_tx_msg *npm)
+{
+	if (npm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("trustsec_tx error response %d\n", npm->cm.response);
+		ttx.response = NSS_TX_FAILURE;
+		complete(&ttx.complete);
+		return;
+	}
+
+	ttx.response = NSS_TX_SUCCESS;
+	complete(&ttx.complete);
+}
+
+/*
+ * nss_trustsec_tx_msg_sync()
+ *	Send a message to trustsec_tx interface & wait for the response.
+ */
+nss_tx_status_t nss_trustsec_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_trustsec_tx_msg *msg)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&ttx.sem);
+
+	msg->cm.cb = (nss_ptr_t)nss_trustsec_tx_callback;
+	msg->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_trustsec_tx_msg(nss_ctx, msg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_trustsec_tx_msg failed\n", nss_ctx);
+		up(&ttx.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&ttx.complete, msecs_to_jiffies(NSS_TRUSTSEC_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: trustsec_tx tx failed due to timeout\n", nss_ctx);
+		ttx.response = NSS_TX_FAILURE;
+	}
+
+	status = ttx.response;
+	up(&ttx.sem);
+
+	return status;
+}
+EXPORT_SYMBOL(nss_trustsec_tx_msg_sync);
+
+/*
+ * nss_trustsec_tx_get_ctx()
+ *	Return a TrustSec TX NSS context.
+ */
+struct nss_ctx_instance *nss_trustsec_tx_get_ctx()
+{
+	return &nss_top_main.nss[nss_top_main.trustsec_tx_handler_id];
+}
+EXPORT_SYMBOL(nss_trustsec_tx_get_ctx);
+
+/*
+ * nss_trustsec_tx_msg_init()
+ *	Initialize trustsec_tx message.
+ */
+void nss_trustsec_tx_msg_init(struct nss_trustsec_tx_msg *npm, uint16_t if_num, uint32_t type, uint32_t len,
+				nss_trustsec_tx_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&npm->cm, if_num, type, len, (void *)cb, app_data);
+}
+EXPORT_SYMBOL(nss_trustsec_tx_msg_init);
+
+/*
+ * nss_trustsec_tx_update_nexthop()
+ */
+nss_tx_status_t nss_trustsec_tx_update_nexthop(uint32_t src, uint32_t dest, uint16_t sgt)
+{
+	struct nss_ctx_instance *ctx = nss_trustsec_tx_get_ctx();
+	struct nss_trustsec_tx_msg ttx_msg = {{0}};
+	struct nss_trustsec_tx_update_nexthop_msg *ttxunh;
+	nss_tx_status_t status;
+
+	ttxunh = &ttx_msg.msg.upd_nexthop;
+	ttxunh->src = src;
+	ttxunh->dest = dest;
+	ttxunh->sgt = sgt;
+
+	nss_trustsec_tx_msg_init(&ttx_msg, NSS_TRUSTSEC_TX_INTERFACE, NSS_TRUSTSEC_TX_MSG_UPDATE_NEXTHOP,
+			sizeof(*ttxunh), NULL, NULL);
+
+	BUG_ON(in_atomic());
+	status = nss_trustsec_tx_msg_sync(ctx, &ttx_msg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: configure trustsec_tx failed: %d\n", ctx, status);
+	}
+
+	return status;
+}
+EXPORT_SYMBOL(nss_trustsec_tx_update_nexthop);
+
+/*
+ * nss_trustsec_tx_configure_sgt()
+ */
+nss_tx_status_t nss_trustsec_tx_configure_sgt(uint32_t src, uint32_t dest, uint16_t sgt)
+{
+	struct nss_ctx_instance *ctx = nss_trustsec_tx_get_ctx();
+	struct nss_trustsec_tx_msg ttx_msg = {{0}};
+	struct nss_trustsec_tx_configure_msg *ttxcfg;
+	nss_tx_status_t status;
+
+	ttxcfg = &ttx_msg.msg.configure;
+	ttxcfg->src = src;
+	ttxcfg->dest = dest;
+	ttxcfg->sgt = sgt;
+
+	nss_trustsec_tx_msg_init(&ttx_msg, NSS_TRUSTSEC_TX_INTERFACE, NSS_TRUSTSEC_TX_MSG_CONFIGURE,
+			sizeof(*ttxcfg), NULL, NULL);
+
+	BUG_ON(in_atomic());
+	status = nss_trustsec_tx_msg_sync(ctx, &ttx_msg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: configure trustsec_tx failed: %d\n", ctx, status);
+	}
+
+	return status;
+}
+EXPORT_SYMBOL(nss_trustsec_tx_configure_sgt);
+
+/*
+ * nss_trustsec_tx_unconfigure()
+ */
+nss_tx_status_t nss_trustsec_tx_unconfigure_sgt(uint32_t src, uint16_t sgt)
+{
+	struct nss_ctx_instance *ctx = nss_trustsec_tx_get_ctx();
+	struct nss_trustsec_tx_msg ttx_msg = {{0}};
+	struct nss_trustsec_tx_unconfigure_msg *ttxucfg;
+	nss_tx_status_t status;
+
+	ttxucfg = &ttx_msg.msg.unconfigure;
+	ttxucfg->src = src;
+	ttxucfg->sgt = sgt;
+
+	nss_trustsec_tx_msg_init(&ttx_msg, NSS_TRUSTSEC_TX_INTERFACE, NSS_TRUSTSEC_TX_MSG_UNCONFIGURE,
+			sizeof(*ttxucfg), NULL, NULL);
+
+	BUG_ON(in_atomic());
+	status = nss_trustsec_tx_msg_sync(ctx, &ttx_msg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: unconfigure trustsec_tx failed: %d\n", ctx, status);
+	}
+
+	return status;
+}
+EXPORT_SYMBOL(nss_trustsec_tx_unconfigure_sgt);
+
+/*
+ * nss_trustsec_tx_register_handler()
+ *	Registering handler for sending msg to trustsec_tx node on NSS.
+ */
+void nss_trustsec_tx_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_trustsec_tx_get_ctx();
+
+	nss_core_register_handler(nss_ctx, NSS_TRUSTSEC_TX_INTERFACE, nss_trustsec_tx_handler, NULL);
+
+	nss_trustsec_tx_stats_dentry_create();
+
+	sema_init(&ttx.sem, 1);
+	init_completion(&ttx.complete);
+}
diff --git a/qca-nss-drv/nss_trustsec_tx_log.c b/qca-nss-drv/nss_trustsec_tx_log.c
new file mode 100644
index 0000000..3ed5b51
--- /dev/null
+++ b/qca-nss-drv/nss_trustsec_tx_log.c
@@ -0,0 +1,170 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_trustsec_tx_log.c
+ *	NSS TRUSTSEC_TX logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_trustsec_tx_log_message_types_str
+ *	TRUSTSEC_TX message strings
+ */
+static int8_t *nss_trustsec_tx_log_message_types_str[NSS_TRUSTSEC_TX_MSG_MAX] __maybe_unused = {
+	"TRUSTSEC_TX Configure Message",
+	"TRUSTSEC_TX Unconfigure Message",
+	"TRUSTSEC_TX Stats Sync",
+	"TRUSTSEC_TX Update next Hop",
+};
+
+/*
+ * nss_trustsec_tx_log_error_response_types_str
+ *	Strings for error types for TRUSTSEC_TX messages
+ */
+static int8_t *nss_trustsec_tx_log_error_response_types_str[NSS_TRUSTSEC_TX_ERR_UNKNOWN] __maybe_unused = {
+	"TRUSTSEC_TX Invalid Source Interface",
+	"TRUSTSEC_TX Reconfigure Source Interface"
+	"TRUSTSEC_TX Destination Interface Not Found",
+	"TRUSTSEC_TX Not Configured",
+	"TRUSTSEC_TX SGT Mismatch",
+	"TRUSTSEC_TX Unknown Error",
+};
+
+/*
+ * nss_trustsec_tx_log_configure_msg()
+ *	Log NSS TRUSTSEC_TX configure message.
+ */
+static void nss_trustsec_tx_log_configure_msg(struct nss_trustsec_tx_msg *ntm)
+{
+	struct nss_trustsec_tx_configure_msg *ntcm __maybe_unused = &ntm->msg.configure;
+	nss_trace("%px: NSS TRUSTSEC_TX Configure Message:\n"
+		"TRUSTSEC_TX Source: %d\n"
+		"TRUSTSEC_TX Destination: %d\n"
+		"TRUSTSEC_TX Security Group Tag: %d\n",
+		ntcm, ntcm->src,
+		ntcm->dest, ntcm->sgt);
+}
+
+/*
+ * nss_trustsec_tx_log_unconfigure_msg()
+ *	Log NSS TRUSTSEC_TX unconfigure message.
+ */
+static void nss_trustsec_tx_log_unconfigure_msg(struct nss_trustsec_tx_msg *ntm)
+{
+	struct nss_trustsec_tx_unconfigure_msg *ntcm __maybe_unused = &ntm->msg.unconfigure;
+	nss_trace("%px: NSS TRUSTSEC_TX Unconfigure Message:\n"
+		"TRUSTSEC_TX Source: %d\n"
+		"TRUSTSEC_TX Security Group Tag: %d\n",
+		ntcm, ntcm->src, ntcm->sgt);
+}
+
+/*
+ * nss_trustsec_tx_log_update_nexthop_msg()
+ *	Log NSS TRUSTSEC_TX update nexthop message.
+ */
+static void nss_trustsec_tx_log_update_nexthop_msg(struct nss_trustsec_tx_msg *ntm)
+{
+	struct nss_trustsec_tx_update_nexthop_msg *ntunm __maybe_unused = &ntm->msg.upd_nexthop;
+	nss_trace("%px: NSS TRUSTSEC_TX Update Next Hop Message:\n"
+		"TRUSTSEC_TX Source: %d\n"
+		"TRUSTSEC_TX Destination: %d\n"
+		"TRUSTSEC_TX Security Group Tag: %d\n",
+		ntunm, ntunm->src,
+		ntunm->dest, ntunm->sgt);
+}
+
+/*
+ * nss_trustsec_tx_log_verbose()
+ *	Log message contents.
+ */
+static void nss_trustsec_tx_log_verbose(struct nss_trustsec_tx_msg *ntm)
+{
+	switch (ntm->cm.type) {
+	case NSS_TRUSTSEC_TX_MSG_CONFIGURE:
+		nss_trustsec_tx_log_configure_msg(ntm);
+		break;
+
+	case NSS_TRUSTSEC_TX_MSG_UNCONFIGURE:
+		nss_trustsec_tx_log_unconfigure_msg(ntm);
+		break;
+
+	case NSS_TRUSTSEC_TX_MSG_UPDATE_NEXTHOP:
+		nss_trustsec_tx_log_update_nexthop_msg(ntm);
+		break;
+
+	case NSS_TRUSTSEC_TX_MSG_STATS_SYNC:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", ntm);
+		break;
+	}
+}
+
+/*
+ * nss_trustsec_tx_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_trustsec_tx_log_tx_msg(struct nss_trustsec_tx_msg *ntm)
+{
+	if (ntm->cm.type >= NSS_TRUSTSEC_TX_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", ntm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ntm, ntm->cm.type, nss_trustsec_tx_log_message_types_str[ntm->cm.type]);
+	nss_trustsec_tx_log_verbose(ntm);
+}
+
+/*
+ * nss_trustsec_tx_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_trustsec_tx_log_rx_msg(struct nss_trustsec_tx_msg *ntm)
+{
+	if (ntm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ntm);
+		return;
+	}
+
+	if (ntm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ntm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ntm, ntm->cm.type,
+			nss_trustsec_tx_log_message_types_str[ntm->cm.type],
+			ntm->cm.response, nss_cmn_response_str[ntm->cm.response]);
+		goto verbose;
+	}
+
+	if (ntm->cm.error >= NSS_TRUSTSEC_TX_ERR_UNKNOWN) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			ntm, ntm->cm.type, nss_trustsec_tx_log_message_types_str[ntm->cm.type],
+			ntm->cm.response, nss_cmn_response_str[ntm->cm.response],
+			ntm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		ntm, ntm->cm.type, nss_trustsec_tx_log_message_types_str[ntm->cm.type],
+		ntm->cm.response, nss_cmn_response_str[ntm->cm.response],
+		ntm->cm.error, nss_trustsec_tx_log_error_response_types_str[ntm->cm.error]);
+
+verbose:
+	nss_trustsec_tx_log_verbose(ntm);
+}
diff --git a/qca-nss-drv/nss_trustsec_tx_log.h b/qca-nss-drv/nss_trustsec_tx_log.h
new file mode 100644
index 0000000..58633c9
--- /dev/null
+++ b/qca-nss-drv/nss_trustsec_tx_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_TRUSTSEC_TX_LOG_H__
+#define __NSS_TRUSTSEC_TX_LOG_H__
+
+/*
+ * nss_trustsec_tx_log.h
+ *	NSS TRUSTSEC_TX Log Header File
+ */
+
+/*
+ * nss_trustsec_tx_log_tx_msg
+ *	Logs a trustsec_tx message that is sent to the NSS firmware.
+ */
+void nss_trustsec_tx_log_tx_msg(struct nss_trustsec_tx_msg *ncm);
+
+/*
+ * nss_trustsec_tx_log_rx_msg
+ *	Logs a trustsec_tx message that is received from the NSS firmware.
+ */
+void nss_trustsec_tx_log_rx_msg(struct nss_trustsec_tx_msg *ncm);
+
+#endif /* __NSS_TRUSTSEC_TX_LOG_H__ */
diff --git a/qca-nss-drv/nss_trustsec_tx_stats.c b/qca-nss-drv/nss_trustsec_tx_stats.c
new file mode 100644
index 0000000..5302321
--- /dev/null
+++ b/qca-nss-drv/nss_trustsec_tx_stats.c
@@ -0,0 +1,145 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_trustsec_tx_stats.h"
+
+/*
+ * nss_trustsec_tx_stats_str
+ *	Trustsec TX statistics strings.
+ */
+
+struct nss_stats_info nss_trustsec_tx_stats_str[NSS_TRUSTSEC_TX_STATS_MAX] = {
+	{"INVALID_SRC"		, NSS_STATS_TYPE_ERROR},
+	{"UNCONFIGURED_SRC"	, NSS_STATS_TYPE_ERROR},
+	{"HEADROOM_NOT_ENOUGH"	, NSS_STATS_TYPE_ERROR}
+};
+
+/*
+ * trustsec_tx_stats
+ *	Trustsec TX statistics.
+ */
+uint64_t trustsec_tx_stats[NSS_TRUSTSEC_TX_STATS_MAX];
+
+/*
+ * Trustsec TX statistics APIs
+ */
+
+/*
+ * nss_trustsec_tx_stats_sync()
+ *	Update trustsec_tx node statistics.
+ */
+void nss_trustsec_tx_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_trustsec_tx_stats_sync_msg *ntsm)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	int j;
+
+	spin_lock_bh(&nss_top->stats_lock);
+
+	/*
+	 * Update common node stats
+	 */
+	nss_top->stats_node[NSS_TRUSTSEC_TX_INTERFACE][NSS_STATS_NODE_RX_PKTS] += ntsm->node_stats.rx_packets;
+	nss_top->stats_node[NSS_TRUSTSEC_TX_INTERFACE][NSS_STATS_NODE_RX_BYTES] += ntsm->node_stats.rx_bytes;
+	nss_top->stats_node[NSS_TRUSTSEC_TX_INTERFACE][NSS_STATS_NODE_TX_PKTS] += ntsm->node_stats.tx_packets;
+	nss_top->stats_node[NSS_TRUSTSEC_TX_INTERFACE][NSS_STATS_NODE_TX_BYTES] += ntsm->node_stats.tx_bytes;
+
+	for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+		nss_top->stats_node[NSS_TRUSTSEC_TX_INTERFACE][NSS_STATS_NODE_RX_QUEUE_0_DROPPED + j] += ntsm->node_stats.rx_dropped[j];
+	}
+
+	/*
+	 * Update trustsec node stats
+	 */
+	trustsec_tx_stats[NSS_TRUSTSEC_TX_STATS_INVALID_SRC] += ntsm->invalid_src;
+	trustsec_tx_stats[NSS_TRUSTSEC_TX_STATS_UNCONFIGURED_SRC] += ntsm->unconfigured_src;
+	trustsec_tx_stats[NSS_TRUSTSEC_TX_STATS_HEADROOM_NOT_ENOUGH] += ntsm->headroom_not_enough;
+
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_trustsec_tx_stats_read()
+ *	Read trustsec_tx statiistics.
+ */
+static ssize_t nss_trustsec_tx_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i;
+
+	/*
+	 * Max output lines = #stats + few blank lines for banner printing +
+	 * Number of Extra outputlines for future reference to add new stats.
+	 */
+	uint32_t max_output_lines = NSS_STATS_NODE_MAX + NSS_TRUSTSEC_TX_STATS_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_STATS_NODE_MAX * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "trustsec_tx", NSS_STATS_SINGLE_CORE);
+
+	/*
+	 * Common node stats
+	 */
+	size_wr += nss_stats_fill_common_stats(NSS_TRUSTSEC_TX_INTERFACE, NSS_STATS_SINGLE_INSTANCE, lbuf, size_wr, size_al, "trustsec_tx");
+
+	/*
+	 * TrustSec TX node stats
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; (i < NSS_TRUSTSEC_TX_STATS_MAX); i++) {
+		stats_shadow[i] = trustsec_tx_stats[i];
+	}
+
+	spin_unlock_bh(&nss_top_main.stats_lock);
+	size_wr += nss_stats_print("trustsec_tx", NULL, NSS_STATS_SINGLE_INSTANCE
+					, nss_trustsec_tx_stats_str
+					, stats_shadow
+					, NSS_TRUSTSEC_TX_STATS_MAX
+					, lbuf, size_wr, size_al);
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_trustsec_tx_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(trustsec_tx)
+
+/*
+ * nss_trustsec_tx_stats_dentry_create()
+ *	Create trustsec_tx statistics debug entry.
+ */
+void nss_trustsec_tx_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("trustsec_tx", &nss_trustsec_tx_stats_ops);
+}
diff --git a/qca-nss-drv/nss_trustsec_tx_stats.h b/qca-nss-drv/nss_trustsec_tx_stats.h
new file mode 100644
index 0000000..11a4d8f
--- /dev/null
+++ b/qca-nss-drv/nss_trustsec_tx_stats.h
@@ -0,0 +1,44 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_trustsec_tx_stats.h
+ *      NSS TRUSTSEC TX statistics header file.
+ */
+
+#ifndef __NSS_TRUSTSEC_TX_STATS_H
+#define __NSS_TRUSTSEC_TX_STATS_H
+
+/*
+ * Trustsec TX statistics
+ */
+enum nss_trustsec_tx_stats {
+	NSS_TRUSTSEC_TX_STATS_INVALID_SRC,
+					/* Number of packets with invalid src if */
+	NSS_TRUSTSEC_TX_STATS_UNCONFIGURED_SRC,
+					/* Number of packets with unconfigured src if */
+	NSS_TRUSTSEC_TX_STATS_HEADROOM_NOT_ENOUGH,
+					/* Number of packets with not enough headroom */
+	NSS_TRUSTSEC_TX_STATS_MAX
+};
+
+/*
+ * Trustsec TX statistics APIs
+ */
+extern void nss_trustsec_tx_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_trustsec_tx_stats_sync_msg *ntsm);
+extern void nss_trustsec_tx_stats_dentry_create(void);
+
+#endif /* __NSS_TRUSTSEC_TX_STATS_H */
diff --git a/qca-nss-drv/nss_tstamp.c b/qca-nss-drv/nss_tstamp.c
new file mode 100644
index 0000000..1984afb
--- /dev/null
+++ b/qca-nss-drv/nss_tstamp.c
@@ -0,0 +1,423 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_tstamp.c
+ *	NSS Tstamp APIs
+ */
+
+#include <linux/ip.h>
+#include <linux/ipv6.h>
+#include <linux/etherdevice.h>
+#include <linux/netdevice.h>
+#include <net/route.h>
+#include <net/ip6_route.h>
+#include "nss_tx_rx_common.h"
+#include "nss_tstamp.h"
+#include "nss_tstamp_stats.h"
+
+#define NSS_TSTAMP_HEADER_SIZE max(sizeof(struct nss_tstamp_h2n_pre_hdr), sizeof(struct nss_tstamp_n2h_pre_hdr))
+
+/*
+ * Notify data structure
+ */
+struct nss_tstamp_notify_data {
+	nss_tstamp_msg_callback_t tstamp_callback;
+	void *app_data;
+};
+
+static struct nss_tstamp_notify_data nss_tstamp_notify = {
+	.tstamp_callback = NULL,
+	.app_data = NULL,
+};
+
+static struct net_device_stats *nss_tstamp_ndev_stats(struct net_device *ndev);
+
+/*
+ * dummy netdevice ops
+ */
+static const struct net_device_ops nss_tstamp_ndev_ops = {
+	.ndo_get_stats = nss_tstamp_ndev_stats,
+};
+
+/*
+ * nss_tstamp_ndev_setup()
+ *	Dummy setup for net_device handler
+ */
+static void nss_tstamp_ndev_setup(struct net_device *ndev)
+{
+	return;
+}
+
+/*
+ * nss_tstamp_ndev_stats()
+ *	Return net device stats
+ */
+static struct net_device_stats *nss_tstamp_ndev_stats(struct net_device *ndev)
+{
+	return &ndev->stats;
+}
+
+/*
+ * nss_tstamp_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static bool nss_tstamp_verify_if_num(uint32_t if_num)
+{
+	return (if_num == NSS_TSTAMP_TX_INTERFACE) || (if_num == NSS_TSTAMP_RX_INTERFACE);
+}
+
+/*
+ * nss_tstamp_interface_handler()
+ *	Handle NSS -> HLOS messages for TSTAMP Statistics
+ */
+static void nss_tstamp_interface_handler(struct nss_ctx_instance *nss_ctx,
+		struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_tstamp_msg *ntm = (struct nss_tstamp_msg *)ncm;
+	nss_tstamp_msg_callback_t cb;
+
+	if (!nss_tstamp_verify_if_num(ncm->interface)) {
+		nss_warning("%px: invalid interface %d for tstamp_tx", nss_ctx, ncm->interface);
+		return;
+	}
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_TSTAMP_MSG_TYPE_MAX) {
+		nss_warning("%px: received invalid message %d for tstamp", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_tstamp_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	switch (ntm->cm.type) {
+	case NSS_TSTAMP_MSG_TYPE_SYNC_STATS:
+		nss_tstamp_stats_sync(nss_ctx, &ntm->msg.stats, ncm->interface);
+		break;
+	default:
+		nss_warning("%px: Unknown message type %d",
+				 nss_ctx, ncm->type);
+		return;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_tstamp_notify.tstamp_callback;
+		ncm->app_data = (nss_ptr_t)nss_tstamp_notify.app_data;
+	}
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_tstamp_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, ntm);
+}
+
+/*
+ * nss_tstamp_copy_data()
+ *	Copy timestamps from received nss frame into skb
+ */
+static void nss_tstamp_copy_data(struct nss_tstamp_n2h_pre_hdr *ntm, struct sk_buff *skb)
+{
+	struct skb_shared_hwtstamps *tstamp;
+
+	tstamp = skb_hwtstamps(skb);
+	tstamp->hwtstamp = ktime_set(ntm->ts_data_hi, ntm->ts_data_lo);
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 16, 0))
+	tstamp->syststamp = ktime_set(ntm->ts_data_hi, ntm->ts_data_lo);
+#endif
+}
+
+/*
+ * nss_tstamp_get_dev()
+ *	Get the net_device associated with the packet.
+ */
+static struct net_device *nss_tstamp_get_dev(struct sk_buff *skb)
+{
+	struct dst_entry *dst;
+	struct net_device *dev;
+	struct rtable *rt;
+	struct flowi6 fl6;
+	uint32_t ip_addr;
+
+	/*
+	 * It seems like the data came over IPsec, hence indicate
+	 * it to the Linux over this interface
+	 */
+	skb_reset_network_header(skb);
+	skb_reset_mac_header(skb);
+
+	skb->pkt_type = PACKET_HOST;
+
+	switch (ip_hdr(skb)->version) {
+	case IPVERSION:
+		ip_addr = ip_hdr(skb)->saddr;
+
+		rt = ip_route_output(&init_net, ip_addr, 0, 0, 0);
+		if (IS_ERR(rt)) {
+			return NULL;
+		}
+
+		dst = (struct dst_entry *)rt;
+		skb->protocol = cpu_to_be16(ETH_P_IP);
+		break;
+
+	case 6:
+		memset(&fl6, 0, sizeof(fl6));
+		memcpy(&fl6.daddr, &ipv6_hdr(skb)->saddr, sizeof(fl6.daddr));
+
+		dst = ip6_route_output(&init_net, NULL, &fl6);
+		if (IS_ERR(dst)) {
+			return NULL;
+		}
+
+		skb->protocol = cpu_to_be16(ETH_P_IPV6);
+		break;
+
+	default:
+		nss_warning("%px:could not get dev for the skb\n", skb);
+		return NULL;
+	}
+
+	dev = dst->dev;
+	dev_hold(dev);
+
+	dst_release(dst);
+	return dev;
+}
+
+/*
+ * nss_tstamp_buf_receive()
+ *	Receive nss exception packets.
+ */
+static void nss_tstamp_buf_receive(struct net_device *ndev, struct sk_buff *skb, struct napi_struct *napi)
+{
+	struct nss_tstamp_n2h_pre_hdr *n2h_hdr = (struct nss_tstamp_n2h_pre_hdr *)skb->data;
+	struct nss_ctx_instance *nss_ctx;
+	struct net_device *dev;
+	uint32_t tstamp_sz;
+
+	BUG_ON(!n2h_hdr);
+
+	tstamp_sz = n2h_hdr->ts_hdr_sz;
+	if (tstamp_sz > (NSS_TSTAMP_HEADER_SIZE)) {
+		goto free;
+	}
+
+	nss_ctx = &nss_top_main.nss[nss_top_main.tstamp_handler_id];
+	BUG_ON(!nss_ctx);
+
+	skb_pull_inline(skb, tstamp_sz);
+
+	/*
+	 * copy the time stamp and convert into ktime_t
+	 */
+	nss_tstamp_copy_data(n2h_hdr, skb);
+	if (unlikely(n2h_hdr->ts_tx)) {
+		/*
+		 * We are in TX Path
+		 */
+		skb_tstamp_tx(skb, skb_hwtstamps(skb));
+
+		ndev->stats.tx_packets++;
+		ndev->stats.tx_bytes += skb->len;
+		goto free;
+	}
+
+	/*
+	 * We are in RX path.
+	 */
+	dev = nss_cmn_get_interface_dev(nss_ctx, n2h_hdr->ts_ifnum);
+	if (!dev) {
+		ndev->stats.rx_dropped++;
+		goto free;
+	}
+
+	/*
+	 * Hold the dev until we finish
+	 */
+	dev_hold(dev);
+
+	switch(dev->type) {
+	case NSS_IPSEC_ARPHRD_IPSEC:
+		/*
+		 * Release the prev dev reference
+		 */
+		dev_put(dev);
+
+		/*
+		 * find the actual IPsec tunnel device
+		 */
+		dev = nss_tstamp_get_dev(skb);
+		break;
+
+	default:
+		/*
+		 * This is a plain non-encrypted data packet.
+		 */
+		skb->protocol = eth_type_trans(skb, dev);
+		break;
+	}
+
+	skb->skb_iif = dev->ifindex;
+	skb->dev = dev;
+
+	ndev->stats.rx_packets++;
+	ndev->stats.rx_bytes += skb->len;
+
+	netif_receive_skb(skb);
+
+	/*
+	 * release the device as we are done
+	 */
+	dev_put(dev);
+	return;
+free:
+	dev_kfree_skb_any(skb);
+	return;
+}
+
+/*
+ * nss_tstamp_tx_buf()
+ *	Send data packet for tstamp processing
+ */
+nss_tx_status_t nss_tstamp_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *skb, uint32_t if_num)
+{
+	struct nss_tstamp_h2n_pre_hdr *h2n_hdr;
+	int extra_head;
+	int extra_tail = 0;
+	char *align_data;
+	uint32_t hdr_sz;
+
+	nss_trace("%px: Tstamp If Tx packet, id:%d, data=%px", nss_ctx, NSS_TSTAMP_RX_INTERFACE, skb->data);
+
+	/*
+	 * header size + alignment size
+	 */
+	hdr_sz = NSS_TSTAMP_HEADER_SIZE;
+	extra_head = hdr_sz - skb_headroom(skb);
+
+	/*
+	 * Expand the head for h2n_hdr
+	 */
+	if (extra_head > 0) {
+		/*
+		 * Try to accommodate using available tailroom.
+		 */
+		if (skb->end - skb->tail >= extra_head)
+			extra_tail = -extra_head;
+		if (pskb_expand_head(skb, extra_head, extra_tail, GFP_KERNEL)) {
+			nss_trace("%px: expand head room failed", nss_ctx);
+			return NSS_TX_FAILURE;
+		}
+	}
+
+	align_data = PTR_ALIGN((skb->data - hdr_sz), sizeof(uint32_t));
+	hdr_sz = (nss_ptr_t)skb->data - (nss_ptr_t)align_data;
+
+	h2n_hdr = (struct nss_tstamp_h2n_pre_hdr *)skb_push(skb, hdr_sz);
+	h2n_hdr->ts_ifnum = if_num;
+	h2n_hdr->ts_tx_hdr_sz = hdr_sz;
+
+	return nss_core_send_packet(nss_ctx, skb, NSS_TSTAMP_RX_INTERFACE, H2N_BIT_FLAG_VIRTUAL_BUFFER | H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+EXPORT_SYMBOL(nss_tstamp_tx_buf);
+
+/*
+ * nss_tstamp_register_netdev()
+ *	register dummy netdevice for tstamp interface
+ */
+struct net_device *nss_tstamp_register_netdev(void)
+{
+	struct net_device *ndev;
+	uint32_t err = 0;
+
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 16, 0))
+	ndev = alloc_netdev(sizeof(struct netdev_priv_instance), "qca-nss-tstamp", nss_tstamp_ndev_setup);
+#else
+	ndev = alloc_netdev(sizeof(struct netdev_priv_instance), "qca-nss-tstamp", NET_NAME_ENUM, nss_tstamp_ndev_setup);
+#endif
+	if (!ndev) {
+		nss_warning("Tstamp: Could not allocate tstamp net_device ");
+		return NULL;
+	}
+
+	ndev->netdev_ops = &nss_tstamp_ndev_ops;
+
+	err = register_netdev(ndev);
+	if (err) {
+		nss_warning("Tstamp: Could not register tstamp net_device ");
+		free_netdev(ndev);
+		return NULL;
+	}
+
+	return ndev;
+}
+
+/*
+ * nss_tstamp_notify_register()
+ *	Register to receive tstamp notify messages.
+ */
+struct nss_ctx_instance *nss_tstamp_notify_register(nss_tstamp_msg_callback_t cb, void *app_data)
+{
+	struct nss_ctx_instance *nss_ctx;
+
+	nss_ctx = &nss_top_main.nss[nss_top_main.tstamp_handler_id];
+
+	nss_tstamp_notify.tstamp_callback = cb;
+	nss_tstamp_notify.app_data = app_data;
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_tstamp_notify_register);
+
+/*
+ * nss_tstamp_register_handler()
+ */
+void nss_tstamp_register_handler(struct net_device *ndev)
+{
+	uint32_t features = 0;
+	struct nss_ctx_instance *nss_ctx;
+
+	nss_ctx = &nss_top_main.nss[nss_top_main.tstamp_handler_id];
+
+	nss_core_register_subsys_dp(nss_ctx, NSS_TSTAMP_TX_INTERFACE, nss_tstamp_buf_receive, NULL, NULL, ndev, features);
+
+	nss_core_register_handler(nss_ctx, NSS_TSTAMP_TX_INTERFACE, nss_tstamp_interface_handler, NULL);
+
+	nss_core_register_handler(nss_ctx, NSS_TSTAMP_RX_INTERFACE, nss_tstamp_interface_handler, NULL);
+
+	nss_tstamp_stats_dentry_create();
+}
diff --git a/qca-nss-drv/nss_tstamp_stats.c b/qca-nss-drv/nss_tstamp_stats.c
new file mode 100644
index 0000000..6285ad8
--- /dev/null
+++ b/qca-nss-drv/nss_tstamp_stats.c
@@ -0,0 +1,165 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include "nss_tstamp_stats.h"
+
+/*
+ * Spinlock to protect TSTAMP statistics update/read
+ */
+DEFINE_SPINLOCK(nss_tstamp_stats_lock);
+
+/*
+ * nss_tstamp_stats_str
+ *	TSTAMP stats strings
+ */
+struct nss_stats_info nss_tstamp_stats_str[NSS_TSTAMP_STATS_MAX] = {
+	{"rx_packets"			, NSS_STATS_TYPE_COMMON},
+	{"rx_bytes"			, NSS_STATS_TYPE_COMMON},
+	{"tx_packets"			, NSS_STATS_TYPE_COMMON},
+	{"tx_bytes"			, NSS_STATS_TYPE_COMMON},
+	{"rx_queue_0_dropped"		, NSS_STATS_TYPE_DROP},
+	{"rx_queue_1_dropped"		, NSS_STATS_TYPE_DROP},
+	{"rx_queue_2_dropped"		, NSS_STATS_TYPE_DROP},
+	{"rx_queue_3_dropped"		, NSS_STATS_TYPE_DROP},
+	{"boomeranged"			, NSS_STATS_TYPE_SPECIAL},
+	{"dropped_fail_enqueue"		, NSS_STATS_TYPE_DROP},
+	{"dropped_fail_alloc"		, NSS_STATS_TYPE_DROP},
+	{"dropped_fail_copy"		, NSS_STATS_TYPE_DROP},
+	{"dropped_no_interface"		, NSS_STATS_TYPE_DROP},
+	{"dropped_no_headroom"		, NSS_STATS_TYPE_DROP}
+};
+
+/*
+ * nss_tstamp_stats
+ *	tstamp statistics
+ */
+uint64_t nss_tstamp_stats[2][NSS_TSTAMP_STATS_MAX];
+
+/*
+ * nss_tstamp_stats_read()
+ *	Read tstamp statistics
+ */
+static ssize_t nss_tstamp_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	int32_t i, num;
+
+	/*
+	 * Max output lines = (#stats + tx or rx tag + two blank lines) * 2(TX and RX)  +
+	 * start tag line + end tag line + three blank lines
+	 */
+	uint32_t max_output_lines = (NSS_TSTAMP_STATS_MAX + 3) * 2 + 5;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return -ENOMEM;
+	}
+
+	stats_shadow = kzalloc(NSS_TSTAMP_STATS_MAX * sizeof(uint64_t), GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return -ENOMEM;
+	}
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "tstamp", NSS_STATS_SINGLE_CORE);
+	/*
+	 * TSTAMP statistics
+	 */
+	for (num = 0; num < 2; num++) {
+		if (num == 0) {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\ntstamp TX stats:\n\n");
+		} else {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\ntstamp RX stats:\n\n");
+		}
+
+		spin_lock_bh(&nss_tstamp_stats_lock);
+		for (i = 0; i < NSS_TSTAMP_STATS_MAX; i++) {
+			stats_shadow[i] = nss_tstamp_stats[num][i];
+		}
+		spin_unlock_bh(&nss_tstamp_stats_lock);
+		size_wr += nss_stats_print("tstamp", NULL, NSS_STATS_SINGLE_INSTANCE
+						, nss_tstamp_stats_str
+						, stats_shadow
+						, NSS_TSTAMP_STATS_MAX
+						, lbuf, size_wr, size_al);
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_tstamp_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(tstamp)
+
+/*
+ * nss_tstamp_stats_dentry_create()
+ *	Create tstamp statistics debug entry.
+ */
+void nss_tstamp_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("tstamp", &nss_tstamp_stats_ops);
+}
+
+/*
+ * nss_tstamp_stats_sync()
+ *	Handle the syncing of NSS TSTAMP statistics.
+ */
+void nss_tstamp_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_tstamp_stats_msg *nts, uint32_t interface)
+{
+	int id, j;
+
+	if (interface == NSS_TSTAMP_TX_INTERFACE) {
+		id = 0;
+	} else {
+		id = 1;
+	}
+
+	spin_lock_bh(&nss_tstamp_stats_lock);
+
+	/*
+	 * Common node stats
+	 */
+	nss_tstamp_stats[id][NSS_STATS_NODE_RX_PKTS] += nts->node_stats.rx_packets;
+	nss_tstamp_stats[id][NSS_STATS_NODE_RX_BYTES] += nts->node_stats.rx_bytes;
+	nss_tstamp_stats[id][NSS_STATS_NODE_TX_PKTS] += nts->node_stats.tx_packets;
+	nss_tstamp_stats[id][NSS_STATS_NODE_TX_BYTES] += nts->node_stats.tx_bytes;
+
+	for (j = 0; j < NSS_MAX_NUM_PRI; j++) {
+		nss_tstamp_stats[id][NSS_STATS_NODE_RX_QUEUE_0_DROPPED + j] += nts->node_stats.rx_dropped[j];
+	}
+
+	/*
+	 * TSTAMP statistics
+	 */
+	nss_tstamp_stats[id][NSS_TSTAMP_STATS_BOOMERANGED] += nts->boomeranged;
+	nss_tstamp_stats[id][NSS_TSTAMP_STATS_DROPPED_FAIL_ENQUEUE] += nts->dropped_fail_enqueue;
+	nss_tstamp_stats[id][NSS_TSTAMP_STATS_DROPPED_FAIL_ALLOC] += nts->dropped_fail_alloc;
+	nss_tstamp_stats[id][NSS_TSTAMP_STATS_DROPPED_FAIL_COPY] += nts->dropped_fail_copy;
+	nss_tstamp_stats[id][NSS_TSTAMP_STATS_DROPPED_NO_INTERFACE] += nts->dropped_no_interface;
+	nss_tstamp_stats[id][NSS_TSTAMP_STATS_DROPPED_NO_HEADROOM] += nts->dropped_no_headroom;
+	spin_unlock_bh(&nss_tstamp_stats_lock);
+}
diff --git a/qca-nss-drv/nss_tstamp_stats.h b/qca-nss-drv/nss_tstamp_stats.h
new file mode 100644
index 0000000..d488ae7
--- /dev/null
+++ b/qca-nss-drv/nss_tstamp_stats.h
@@ -0,0 +1,48 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_TSTAMP_STATS_H
+#define __NSS_TSTAMP_STATS_H
+
+#include <nss_cmn.h>
+
+/**
+ * TSTAMP node statistics
+ */
+enum nss_tstamp_stats_types {
+
+	NSS_TSTAMP_STATS_BOOMERANGED = NSS_STATS_NODE_MAX,
+					/**< Number of boomeranged packets. */
+	NSS_TSTAMP_STATS_DROPPED_FAIL_ENQUEUE,
+					/**< Number of failed enqueue drops. */
+	NSS_TSTAMP_STATS_DROPPED_FAIL_ALLOC,
+					/**< Number of failed allocation drops. */
+	NSS_TSTAMP_STATS_DROPPED_FAIL_COPY,
+					/**< Number of failed copy drops. */
+	NSS_TSTAMP_STATS_DROPPED_NO_INTERFACE,
+					/**< Number of failed no interface drops. */
+	NSS_TSTAMP_STATS_DROPPED_NO_HEADROOM,
+					/**< Number of failed no headroom drops. */
+	NSS_TSTAMP_STATS_MAX,
+};
+
+/*
+ * TSTAMP statistics APIs
+ */
+extern void nss_tstamp_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_tstamp_stats_msg *nts, uint32_t interface);
+extern void nss_tstamp_stats_dentry_create(void);
+
+#endif /* __NSS_TSTAMP_STATS_H */
diff --git a/qca-nss-drv/nss_tun6rd.c b/qca-nss-drv/nss_tun6rd.c
new file mode 100644
index 0000000..af1a4ac
--- /dev/null
+++ b/qca-nss-drv/nss_tun6rd.c
@@ -0,0 +1,183 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_tun6rd_log.h"
+
+/*
+ * nss_tun6rd_handler()
+ * 	Handle NSS -> HLOS messages for 6rd tunnel
+ */
+static void nss_tun6rd_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_tun6rd_msg *ntm = (struct nss_tun6rd_msg *)ncm;
+	void *ctx;
+
+	nss_tun6rd_msg_callback_t cb;
+
+	BUG_ON(!nss_is_dynamic_interface(ncm->interface));
+
+	/*
+	 * Trace Messages
+	 */
+	nss_tun6rd_log_rx_msg(ntm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_TUN6RD_MAX) {
+		nss_warning("%px: received invalid message %d for Tun6RD interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_tun6rd_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+ 	 * Update the callback and app_data for NOTIFY messages, tun6rd sends all notify messages
+ 	 * to the same callback/app_data.
+ 	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->tun6rd_msg_callback;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_tun6rd_msg_callback_t)ncm->cb;
+	ctx = nss_ctx->subsys_dp_register[ncm->interface].ndev;
+
+	/*
+	 * call 6rd tunnel callback
+	 */
+	if (!ctx) {
+		nss_warning("%px: Event received for 6rd tunnel interface %d before registration", nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb(ctx, ntm);
+}
+
+/*
+ * nss_tun6rd_tx()
+ * 	Transmit a tun6rd message to NSSFW
+ */
+nss_tx_status_t nss_tun6rd_tx(struct nss_ctx_instance *nss_ctx, struct nss_tun6rd_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_tun6rd_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!nss_is_dynamic_interface(ncm->interface)) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_TUN6RD_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ ***********************************
+ * Register/Unregister/Miscellaneous APIs
+ ***********************************
+ */
+
+/*
+ * nss_register_tun6rd_if()
+ */
+struct nss_ctx_instance *nss_register_tun6rd_if(uint32_t if_num, uint32_t type, nss_tun6rd_callback_t tun6rd_callback,
+			nss_tun6rd_msg_callback_t event_callback, struct net_device *netdev, uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.tun6rd_handler_id];
+
+	nss_assert(nss_ctx);
+	nss_assert((if_num >=  NSS_DYNAMIC_IF_START) && (if_num < NSS_SPECIAL_IF_START));
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, tun6rd_callback, NULL, NULL, netdev, features);
+	nss_ctx->subsys_dp_register[if_num].type = type;
+
+	nss_top_main.tun6rd_msg_callback = event_callback;
+
+	nss_core_register_handler(nss_ctx, if_num, nss_tun6rd_handler, NULL);
+
+	return nss_ctx;
+}
+
+/*
+ * nss_tun6rd_get_context()
+ */
+struct nss_ctx_instance *nss_tun6rd_get_context()
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.tun6rd_handler_id];
+}
+
+/*
+ * nss_unregister_tun6rd_if()
+ */
+void nss_unregister_tun6rd_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.tun6rd_handler_id];
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_is_dynamic_interface(if_num));
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+	nss_ctx->subsys_dp_register[if_num].type = 0;
+
+	nss_top_main.tun6rd_msg_callback = NULL;
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+}
+
+/*
+ * nss_tun6rd_msg_init()
+ *      Initialize nss_tun6rd msg.
+ */
+void nss_tun6rd_msg_init(struct nss_tun6rd_msg *ncm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+
+EXPORT_SYMBOL(nss_tun6rd_get_context);
+EXPORT_SYMBOL(nss_tun6rd_tx);
+EXPORT_SYMBOL(nss_register_tun6rd_if);
+EXPORT_SYMBOL(nss_unregister_tun6rd_if);
+EXPORT_SYMBOL(nss_tun6rd_msg_init);
diff --git a/qca-nss-drv/nss_tun6rd_log.c b/qca-nss-drv/nss_tun6rd_log.c
new file mode 100644
index 0000000..121d70f
--- /dev/null
+++ b/qca-nss-drv/nss_tun6rd_log.c
@@ -0,0 +1,132 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_tun6rd_log.c
+ *	NSS TUN6RD logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_tun6rd_log_message_types_str
+ *	NSS TUN6RD message strings
+ */
+static int8_t *nss_tun6rd_log_message_types_str[NSS_TUN6RD_MAX] __maybe_unused = {
+	"TUN6RD Attach PNODE",
+	"TUN6RD Stats",
+	"TUN6RD Update Peer",
+};
+
+/*
+ * nss_tun6rd_log_attach_pnode_msg()
+ *	Log NSS TUN6RD Attach PNODE
+ */
+static void nss_tun6rd_log_attach_pnode_msg(struct nss_tun6rd_msg *ntm)
+{
+	struct nss_tun6rd_attach_tunnel_msg *ntam __maybe_unused = &ntm->msg.tunnel;
+	nss_trace("%px: NSS TUN6RD Attach Tunnel message \n"
+		"TUN6RD Source Address: %pI4\n"
+		"TUN6RD Destination Address: %pI4\n"
+		"TUN6RD Type of Service: %d\n"
+		"TUN6RD Time To Live: %d\n"
+		"TUN6RD Sibling Interface Number: %d\n",
+		ntam, &ntam->saddr,
+		&ntam->daddr, ntam->tos,
+		ntam->ttl, ntam->sibling_if_num);
+}
+
+/*
+ * nss_tun6rd_log_set_peer_msg()
+ *	Log NSS TUN6RD Set Peer Message
+ */
+static void nss_tun6rd_log_set_peer_msg(struct nss_tun6rd_msg *ntm)
+{
+	struct nss_tun6rd_set_peer_msg *ntspm __maybe_unused = &ntm->msg.peer;
+	nss_trace("%px: NSS TUN6RD Set Peer message \n"
+		"TUN6RD IPv6 Address: %pI6\n"
+		"TUN6RD Destination: %pI4\n",
+		ntspm, ntspm->ipv6_address,
+		&ntspm->dest);
+}
+
+/*
+ * nss_tun6rd_log_verbose()
+ *	Log message contents.
+ */
+static void nss_tun6rd_log_verbose(struct nss_tun6rd_msg *ntm)
+{
+	switch (ntm->cm.type) {
+	case NSS_TUN6RD_ATTACH_PNODE:
+		nss_tun6rd_log_attach_pnode_msg(ntm);
+		break;
+
+	case NSS_TUN6RD_ADD_UPDATE_PEER:
+		nss_tun6rd_log_set_peer_msg(ntm);
+		break;
+
+	case NSS_TUN6RD_RX_STATS_SYNC:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", ntm);
+		break;
+	}
+}
+
+/*
+ * nss_tun6rd_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_tun6rd_log_tx_msg(struct nss_tun6rd_msg *ntm)
+{
+	if (ntm->cm.type >= NSS_TUN6RD_MAX) {
+		nss_warning("%px: Invalid message type\n", ntm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ntm, ntm->cm.type, nss_tun6rd_log_message_types_str[ntm->cm.type]);
+	nss_tun6rd_log_verbose(ntm);
+}
+
+/*
+ * nss_tun6rd_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_tun6rd_log_rx_msg(struct nss_tun6rd_msg *ntm)
+{
+	if (ntm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ntm);
+		return;
+	}
+
+	if (ntm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ntm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ntm, ntm->cm.type,
+			nss_tun6rd_log_message_types_str[ntm->cm.type],
+			ntm->cm.response, nss_cmn_response_str[ntm->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		ntm, ntm->cm.type, nss_tun6rd_log_message_types_str[ntm->cm.type],
+		ntm->cm.response, nss_cmn_response_str[ntm->cm.response]);
+
+verbose:
+	nss_tun6rd_log_verbose(ntm);
+}
diff --git a/qca-nss-drv/nss_tun6rd_log.h b/qca-nss-drv/nss_tun6rd_log.h
new file mode 100644
index 0000000..c7c3b3a
--- /dev/null
+++ b/qca-nss-drv/nss_tun6rd_log.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_TUN6RD_LOG_H
+#define __NSS_TUN6RD_LOG_H
+
+/*
+ * nss_tun6rd.h
+ *	NSS TUN6RD header file.
+ */
+
+/*
+ * Logger APIs
+ */
+
+/*
+ * nss_tun6rd_log_tx_msg
+ *	Logs a tun6rd message that is sent to the NSS firmware.
+ */
+void nss_tun6rd_log_tx_msg(struct nss_tun6rd_msg *ntm);
+
+/*
+ * nss_tun6rd_log_rx_msg
+ *	Logs a tun6rd message that is received from the NSS firmware.
+ */
+void nss_tun6rd_log_rx_msg(struct nss_tun6rd_msg *ntm);
+
+#endif /* __NSS_TUN6RD_LOG_H */
diff --git a/qca-nss-drv/nss_tunipip6.c b/qca-nss-drv/nss_tunipip6.c
new file mode 100644
index 0000000..1801e86
--- /dev/null
+++ b/qca-nss-drv/nss_tunipip6.c
@@ -0,0 +1,291 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_tunipip6_log.h"
+#include "nss_tunipip6_stats.h"
+
+#define NSS_TUNIPIP6_TX_TIMEOUT 3000
+
+/*
+ * Data structure used to handle sync message.
+ */
+static struct nss_tunipip6_pvt {
+	struct semaphore sem;           /* Semaphore structure. */
+	struct completion complete;     /* Completion structure. */
+	int response;                   /* Response from FW. */
+	void *cb;                       /* Original cb for msgs. */
+	void *app_data;                 /* Original app_data for msgs. */
+} tunipip6_pvt;
+
+/*
+ * nss_tunipip6_verify_if_num
+ *	Verify the interface is a valid interface
+ */
+static bool nss_tunipip6_verify_if_num(uint32_t if_num)
+{
+	enum nss_dynamic_interface_type type;
+
+	type = nss_dynamic_interface_get_type(nss_tunipip6_get_context(), if_num);
+
+	switch (type) {
+	case NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER:
+	case NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_OUTER:
+		return true;
+	default:
+		return false;
+	}
+}
+
+/*
+ * nss_tunipip6_handler()
+ *	Handle NSS -> HLOS messages for ipip6 tunnel
+ */
+static void nss_tunipip6_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_tunipip6_msg *ntm = (struct nss_tunipip6_msg *)ncm;
+	void *ctx;
+	nss_tunipip6_msg_callback_t cb;
+
+	BUG_ON(!nss_tunipip6_verify_if_num(ncm->interface));
+
+	/*
+	 * Trace Messages
+	 */
+	nss_tunipip6_log_rx_msg(ntm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_TUNIPIP6_MAX) {
+		nss_warning("%px: received invalid message %d for DS-Lite interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_tunipip6_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	switch (ntm->cm.type) {
+	case NSS_TUNIPIP6_STATS_SYNC:
+		/*
+		 * Sync common node stats.
+		 */
+		nss_tunipip6_stats_sync(nss_ctx, ntm);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, tunipip6 sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->tunipip6_msg_callback;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_tunipip6_msg_callback_t)ncm->cb;
+	ctx = nss_ctx->subsys_dp_register[ncm->interface].ndev;
+
+	/*
+	 * call ipip6 tunnel callback
+	 */
+	if (!ctx) {
+		 nss_warning("%px: Event received for DS-Lite tunnel interface %d before registration", nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb(ctx, ntm);
+}
+
+/*
+ * nss_tunipip6_tx()
+ * 	Transmit a tunipip6 message to NSSFW
+ */
+nss_tx_status_t nss_tunipip6_tx(struct nss_ctx_instance *nss_ctx, struct nss_tunipip6_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_tunipip6_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!nss_tunipip6_verify_if_num(ncm->interface)) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_TUNIPIP6_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_tunipip6_tx);
+
+/*
+ * nss_tunipip6_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_tunipip6_callback(void *app_data, struct nss_tunipip6_msg *nclm)
+{
+	tunipip6_pvt.response = NSS_TX_SUCCESS;
+	tunipip6_pvt.cb = NULL;
+	tunipip6_pvt.app_data = NULL;
+
+	if (nclm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("%px: tunipip6 Error response %d Error: %d\n", app_data, nclm->cm.response, nclm->cm.error);
+		tunipip6_pvt.response = nclm->cm.response;
+	}
+
+	/*
+	 * Write memory barrier.
+	 */
+	smp_wmb();
+	complete(&tunipip6_pvt.complete);
+}
+
+/*
+ * nss_tunipip6_tx_sync()
+ * 	Transmit a tunipip6 message to NSSFW synchronously.
+ */
+nss_tx_status_t nss_tunipip6_tx_sync(struct nss_ctx_instance *nss_ctx, struct nss_tunipip6_msg *msg)
+{
+	nss_tx_status_t status;
+	int ret;
+
+	down(&tunipip6_pvt.sem);
+	msg->cm.cb = (nss_ptr_t)nss_tunipip6_callback;
+	msg->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_tunipip6_tx(nss_ctx, msg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: tunipip6_tx_msg failed\n", nss_ctx);
+		up(&tunipip6_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&tunipip6_pvt.complete, msecs_to_jiffies(NSS_TUNIPIP6_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: tunipip6 tx sync failed due to timeout\n", nss_ctx);
+		tunipip6_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = tunipip6_pvt.response;
+	up(&tunipip6_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_tunipip6_tx_sync);
+
+/*
+ * **********************************
+ *  Register/Unregister/Miscellaneous APIs
+ * **********************************
+ */
+
+/*
+ * nss_register_tunipip6_if()
+ */
+struct nss_ctx_instance *nss_register_tunipip6_if(uint32_t if_num,
+			uint32_t dynamic_interface_type,
+			nss_tunipip6_callback_t tunipip6_callback,
+			nss_tunipip6_msg_callback_t event_callback,
+			struct net_device *netdev,
+			uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.tunipip6_handler_id];
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_tunipip6_verify_if_num(if_num));
+
+	nss_ctx->subsys_dp_register[if_num].type = dynamic_interface_type;
+	nss_top_main.tunipip6_msg_callback = event_callback;
+	nss_core_register_subsys_dp(nss_ctx, if_num, tunipip6_callback, NULL, NULL, netdev, features);
+	nss_core_register_handler(nss_ctx, if_num, nss_tunipip6_handler, NULL);
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_register_tunipip6_if);
+
+/*
+ * nss_unregister_tunipip6_if()
+ */
+void nss_unregister_tunipip6_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.tunipip6_handler_id];
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_tunipip6_verify_if_num(if_num));
+
+	nss_stats_reset_common_stats(if_num);
+	nss_core_unregister_handler(nss_ctx, if_num);
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	nss_top_main.tunipip6_msg_callback = NULL;
+}
+EXPORT_SYMBOL(nss_unregister_tunipip6_if);
+
+/*
+ * nss_tunipip6_get_context()
+ */
+struct nss_ctx_instance *nss_tunipip6_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.tunipip6_handler_id];
+}
+EXPORT_SYMBOL(nss_tunipip6_get_context);
+
+/*
+ * nss_tunipip6_register_handler()
+ */
+void nss_tunipip6_register_handler()
+{
+	struct nss_ctx_instance *nss_ctx = nss_tunipip6_get_context();
+
+	nss_core_register_handler(nss_ctx, NSS_TUNIPIP6_INTERFACE, nss_tunipip6_handler, NULL);
+	nss_tunipip6_stats_dentry_create();
+	sema_init(&tunipip6_pvt.sem, 1);
+	init_completion(&tunipip6_pvt.complete);
+}
+
+/*
+ * nss_tunipip6_msg_init()
+ *	Initialize nss_tunipip6 msg.
+ */
+void nss_tunipip6_msg_init(struct nss_tunipip6_msg *ntm, uint16_t if_num, uint32_t type,  uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ntm->cm, if_num, type, len, cb, app_data);
+}
+EXPORT_SYMBOL(nss_tunipip6_msg_init);
diff --git a/qca-nss-drv/nss_tunipip6_log.c b/qca-nss-drv/nss_tunipip6_log.c
new file mode 100644
index 0000000..1565ed8
--- /dev/null
+++ b/qca-nss-drv/nss_tunipip6_log.c
@@ -0,0 +1,189 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_tunipip6_log.c
+ *	NSS TUNIPIP6 logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_tunipip6_log_message_types_str
+ *	NSS TUNIPIP6 message strings
+ */
+static int8_t *nss_tunipip6_log_message_types_str[NSS_TUNIPIP6_MAX] __maybe_unused = {
+	"TUNIPIP6 Encap Interface Create",
+	"TUNIPIP6 Decap Interface Create",
+	"TUNIPIP6 Stats",
+	"TUNIPIP6 FMR add",
+	"TUNIPIP6 FMR delete",
+	"TUNIPIP6 FMR flush",
+	"TUNIPIP6 BMR add",
+	"TUNIPIP6 BMR delete",
+};
+
+/*
+ * nss_tunipip6_log_error_types_str
+ *	Strings for error types for TUNIPIP6 messages
+ */
+static char *nss_tunipip6_log_error_types_str[NSS_TUNIPIP6_ERROR_MAX] __maybe_unused = {
+	"TUNIPIP6 maximum tunnel reached",
+	"TUNIPIP6 tunnel already exists",
+	"TUNIPIP6 configuration parameters are incorrect",
+	"TUNIPIP6 FMR already exists ",
+	"TUNIPIP6 no FMR configured",
+	"TUNIPIP6 FMR table is full",
+	"TUNIPIP6 invalid FMR",
+	"TUNIPIP6 BMR already exists",
+	"TUNIPIP6 no BMR configured",
+	"TUNIPIP6 memory allocation for FMR failed",
+	"TUNIPIP6 unknown error",
+};
+
+/*
+ * nss_tunipip6_log_map_rule()
+ *	Log NSS TUNIPIP6 map rule.
+ */
+static void nss_tunipip6_log_map_rule(struct nss_tunipip6_msg *ntm)
+{
+	struct nss_tunipip6_map_rule *nmr __maybe_unused = &ntm->msg.map_rule;
+	nss_trace("%px: NSS TUNIPIP6 Interface Create message \n"
+		"TUNIPIP6 Map Rule IPv6 prefix: %pI6\n"
+		"TUNIPIP6 Map Rule IPv6 prefix length: %d\n"
+		"TUNIPIP6 Map Rule IPv4 prefix: %pI4\n"
+		"TUNIPIP6 Map Rule IPv4 prefix length: %d\n"
+		"TUNIPIP6 Map Rule IPv6 suffix: %pI6\n"
+		"TUNIPIP6 Map Rule IPv6 suffix length: %d\n"
+		"TUNIPIP6 Map Rule EA length: %d\n"
+		"TUNIPIP6 Map Rule PSID offset: %d\n",
+		nmr, nmr->ip6_prefix,
+		nmr->ip6_prefix_len,&nmr->ip4_prefix,
+		nmr->ip4_prefix_len, nmr->ip6_suffix,
+		nmr->ip6_suffix_len, nmr->ea_len,
+		nmr->psid_offset);
+}
+
+/*
+ * nss_tunipip6_log_if_create_msg()
+ *	Log NSS TUNIPIP6 Interface Create
+ */
+static void nss_tunipip6_log_if_create_msg(struct nss_tunipip6_msg *ntm)
+{
+	struct nss_tunipip6_create_msg *ntcm __maybe_unused = &ntm->msg.tunipip6_create;
+	nss_trace("%px: NSS TUNIPIP6 Interface Create message \n"
+		"TUNIPIP6 Source Address: %pI6\n"
+		"TUNIPIP6 Destination Address: %pI6\n"
+		"TUNIPIP6 Flow Label: %d\n"
+		"TUNIPIP6 Flags: %d\n"
+		"TUNIPIP6 Hop Limit: %d\n"
+		"TUNIPIP6 Draft03 Specification: %d\n"
+		"TUNIPIP6 TTL inherit: %u\n"
+		"TUNIPIP6 TOS inherit: %u\n"
+		"TUNIPIP6 Frag ID Update: %u\n"
+		"TUNIPIP6 Max FMR: %u\n",
+		ntcm, ntcm->saddr,
+		ntcm->daddr, ntcm->flowlabel,
+		ntcm->flags, ntcm->hop_limit,
+		ntcm->draft03,
+		ntcm->ttl_inherit,
+		ntcm->tos_inherit,
+		ntcm->frag_id_update,
+		ntcm->fmr_max);
+}
+
+/*
+ * nss_tunipip6_log_verbose()
+ *	Log message contents.
+ */
+static void nss_tunipip6_log_verbose(struct nss_tunipip6_msg *ntm)
+{
+	switch (ntm->cm.type) {
+	case NSS_TUNIPIP6_TX_ENCAP_IF_CREATE:
+	case NSS_TUNIPIP6_TX_DECAP_IF_CREATE:
+		nss_tunipip6_log_if_create_msg(ntm);
+		break;
+
+	case NSS_TUNIPIP6_STATS_SYNC:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	case NSS_TUNIPIP6_BMR_RULE_ADD:
+	case NSS_TUNIPIP6_BMR_RULE_DEL:
+	case NSS_TUNIPIP6_FMR_RULE_ADD:
+	case NSS_TUNIPIP6_FMR_RULE_DEL:
+		nss_tunipip6_log_map_rule(ntm);
+		break;
+	case NSS_TUNIPIP6_FMR_RULE_FLUSH:
+		nss_trace("%px: FMR rule flush.\n", ntm);
+		break;
+	default:
+		nss_trace("%px: Invalid message type\n", ntm);
+		break;
+	}
+}
+
+/*
+ * nss_tunipip6_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_tunipip6_log_tx_msg(struct nss_tunipip6_msg *ntm)
+{
+	if (ntm->cm.type >= NSS_TUNIPIP6_MAX) {
+		nss_warning("%px: Invalid message type\n", ntm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ntm, ntm->cm.type, nss_tunipip6_log_message_types_str[ntm->cm.type]);
+	nss_tunipip6_log_verbose(ntm);
+}
+
+/*
+ * nss_tunipip6_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_tunipip6_log_rx_msg(struct nss_tunipip6_msg *ntm)
+{
+	if (ntm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ntm);
+		return;
+	}
+
+	if (ntm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ntm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ntm, ntm->cm.type,
+			nss_tunipip6_log_message_types_str[ntm->cm.type],
+			ntm->cm.response, nss_cmn_response_str[ntm->cm.response]);
+		goto verbose;
+	}
+
+	if (ntm->cm.error >= NSS_TUNIPIP6_ERROR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			ntm, ntm->cm.type, nss_tunipip6_log_message_types_str[ntm->cm.type],
+			ntm->cm.response, nss_cmn_response_str[ntm->cm.response],
+			ntm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		ntm, ntm->cm.type, nss_tunipip6_log_message_types_str[ntm->cm.type],
+		ntm->cm.response, nss_cmn_response_str[ntm->cm.response],
+		ntm->cm.error, nss_tunipip6_log_error_types_str[ntm->cm.error]);
+
+verbose:
+	nss_tunipip6_log_verbose(ntm);
+}
diff --git a/qca-nss-drv/nss_tunipip6_log.h b/qca-nss-drv/nss_tunipip6_log.h
new file mode 100644
index 0000000..2ebccee
--- /dev/null
+++ b/qca-nss-drv/nss_tunipip6_log.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_TUNIPIP6_LOG_H
+#define __NSS_TUNIPIP6_LOG_H
+
+/*
+ * nss_tunipip6.h
+ *	NSS TUNIPIP6 header file.
+ */
+
+/*
+ * Logger APIs
+ */
+
+/*
+ * nss_tunipip6_log_tx_msg
+ *	Logs a tunipip6 message that is sent to the NSS firmware.
+ */
+void nss_tunipip6_log_tx_msg(struct nss_tunipip6_msg *ntm);
+
+/*
+ * nss_tunipip6_log_rx_msg
+ *	Logs a tunipip6 message that is received from the NSS firmware.
+ */
+void nss_tunipip6_log_rx_msg(struct nss_tunipip6_msg *ntm);
+
+#endif /* __NSS_TUNIPIP6_LOG_H */
diff --git a/qca-nss-drv/nss_tunipip6_stats.c b/qca-nss-drv/nss_tunipip6_stats.c
new file mode 100644
index 0000000..76834d3
--- /dev/null
+++ b/qca-nss-drv/nss_tunipip6_stats.c
@@ -0,0 +1,124 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_tunipip6.h"
+#include "nss_stats.h"
+#include "nss_tunipip6_stats.h"
+
+#define NSS_TUNIPIP6_STATS_MAX_LINES (NSS_STATS_NODE_MAX + 32)
+					/**< Maximum number of lines for tunipip6 statistics dump. */
+#define NSS_TUNIPIP6_STATS_SIZE_PER_IF (NSS_STATS_MAX_STR_LENGTH * NSS_TUNIPIP6_STATS_MAX_LINES)
+					/**< Total number of statistics per tunipip6 interface. */
+
+/*
+ * nss_tunipip6_stats_read()
+ *	Read tunipip6 common node statistics
+ */
+static ssize_t nss_tunipip6_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	struct nss_ctx_instance *nss_ctx = nss_tunipip6_get_context();
+	enum nss_dynamic_interface_type type;
+	ssize_t bytes_read = 0;
+	size_t len = 0, size;
+	uint32_t if_num;
+	char *buf;
+
+	/*
+	 * Allocate memory for NSS_TUNIPIP6_TUNNEL_MAX tunnels and one
+	 * static interface.
+	 */
+	size = NSS_TUNIPIP6_STATS_SIZE_PER_IF * (NSS_TUNIPIP6_TUNNEL_MAX << 1) + 1;
+	buf = vzalloc(size);
+	if (!buf) {
+		nss_warning("tunipip6: Could not allocate memory for local statistics buffer\n");
+		return 0;
+	}
+
+	len += nss_stats_banner(buf, len, size, "tunipip6", NSS_STATS_SINGLE_CORE);
+
+	len += scnprintf(buf + len, size - len, "\nBase node if_num:%03u", NSS_TUNIPIP6_INTERFACE);
+	len += scnprintf(buf + len, size - len, "\n-------------------\n");
+	len += nss_stats_fill_common_stats(NSS_TUNIPIP6_INTERFACE, NSS_STATS_SINGLE_INSTANCE, buf, len, size - len, "tunipip6");
+
+	/*
+	 * Common node stats for each tunipip6 dynamic interface.
+	 */
+	for (if_num = NSS_DYNAMIC_IF_START; if_num < NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES; if_num++) {
+		type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+		switch (type) {
+		case NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER:
+			len += scnprintf(buf + len, size - len, "\nInner if_num:%03u", if_num);
+			break;
+
+		case NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_OUTER:
+			len += scnprintf(buf + len, size - len, "\nOuter if_num:%03u", if_num);
+			break;
+
+		default:
+			continue;
+		}
+
+		len += scnprintf(buf + len, size - len, "\n-------------------\n");
+		len += nss_stats_fill_common_stats(if_num, NSS_STATS_SINGLE_INSTANCE, buf, len, size - len, "tunipip6");
+	}
+
+        bytes_read = simple_read_from_buffer(ubuf, sz, ppos, buf, len);
+        vfree(buf);
+        return bytes_read;
+}
+
+/*
+ * nss_tunipip6_stats_sync()
+ * 	Update tunipip6 common node statistics.
+ */
+void nss_tunipip6_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_tunipip6_msg *ntm)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	struct nss_tunipip6_stats_sync_msg *msg_stats = &ntm->msg.stats;
+	uint64_t i, *dest;
+	uint32_t *src;
+
+	spin_lock_bh(&nss_top->stats_lock);
+
+	/*
+	 * Update common node stats
+	 */
+	dest = nss_top->stats_node[ntm->cm.interface];
+	src = &msg_stats->node_stats.rx_packets;
+	for (i = NSS_STATS_NODE_RX_PKTS; i <= NSS_STATS_NODE_RX_QUEUE_3_DROPPED; i++) {
+		*dest++ = *src++;
+	}
+
+	spin_unlock_bh(&nss_top->stats_lock);
+
+}
+
+/*
+ * nss_tunipip6_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(tunipip6)
+
+/*
+ * nss_tunipip6_stats_dentry_create()
+ *	Create tunipip6 statistics debug entry.
+ */
+void nss_tunipip6_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("tunipip6", &nss_tunipip6_stats_ops);
+}
diff --git a/qca-nss-drv/nss_tunipip6_stats.h b/qca-nss-drv/nss_tunipip6_stats.h
new file mode 100644
index 0000000..0f1748f
--- /dev/null
+++ b/qca-nss-drv/nss_tunipip6_stats.h
@@ -0,0 +1,34 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_TUNIPIP6_STATS_H
+#define __NSS_TUNIPIP6_STATS_H
+
+/*
+ * nss_tunipip6_stats_dentry_create()
+ * 	Creates tunipip6 interface statistics debug entry.
+ */
+void nss_tunipip6_stats_dentry_create(void);
+
+/*
+ * nss_tunipip6_stats_sync()
+ * 	Update tunipip6 common node statistics.
+ */
+void nss_tunipip6_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_tunipip6_msg *ntm);
+
+#endif /* __NSS_TUNIPIP6_STATS_H */
diff --git a/qca-nss-drv/nss_tx_msg_sync.c b/qca-nss-drv/nss_tx_msg_sync.c
new file mode 100644
index 0000000..9eb0c70
--- /dev/null
+++ b/qca-nss-drv/nss_tx_msg_sync.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * nss_tx_msg_sync.c
+ *	NSS Tx msg sync core APIs
+ */
+
+#include "nss_tx_rx_common.h"
+
+/*
+ * nss_tx_msg_sync_callback()
+ *	Internal callback used to handle the message response.
+ */
+static void nss_tx_msg_sync_callback(void *app_data, struct nss_cmn_msg *ncm)
+{
+	uint32_t resp_offset;
+
+	/*
+	 * Per-message sync data was used as app_data.
+	 * Retrieve the address of the original message from it.
+	 */
+	struct nss_tx_msg_sync_cmn_data *sync_data = (struct nss_tx_msg_sync_cmn_data *)app_data;
+	struct nss_cmn_msg *original_msg = (struct nss_cmn_msg *)sync_data->original_msg;
+
+	/*
+	 * Set TX status. And Copy back ncm->error and ncm->response if it is NACK.
+	 */
+	sync_data->status = NSS_TX_SUCCESS;
+	if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("Tx msg sync error response %d\n", ncm->response);
+		sync_data->status = NSS_TX_FAILURE_SYNC_FW_ERR;
+		original_msg->error = ncm->error;
+		original_msg->response = ncm->response;
+	}
+
+	/*
+	 * ncm is the return message containing message response.
+	 * It is different from the original message caller built.
+	 * Because the return message is only visible in this callback context,
+	 * we copy back message response by specifying offset and length to
+	 * the return message. So the caller can use response in their context
+	 * once wake up instead of calling a passed-in user callback here.
+	 */
+	resp_offset = sync_data->resp_offset + sizeof(struct nss_cmn_msg);
+
+	if (sync_data->copy_len > 0)
+		memcpy((uint8_t *)((nss_ptr_t)original_msg + resp_offset),
+			(uint8_t *)((nss_ptr_t)ncm + resp_offset),
+			sync_data->copy_len);
+
+	/*
+	 * Wake up the caller
+	 */
+	complete(&sync_data->complete);
+}
+
+/*
+ * nss_tx_msg_sync_internal()
+ *	Internal call for sending messages to FW synchronously.
+ */
+static nss_tx_status_t nss_tx_msg_sync_internal(struct nss_ctx_instance *nss_ctx,
+						nss_tx_msg_sync_subsys_async_t tx_msg_async,
+						nss_tx_msg_sync_subsys_async_with_size_t tx_msg_async_with_size,
+						uint32_t msg_buf_size,
+						struct nss_tx_msg_sync_cmn_data *sync_data,
+						struct nss_cmn_msg *ncm,
+						uint32_t timeout)
+{
+	nss_tx_status_t status;
+	int ret;
+
+	/*
+	 * Per-msg sync data is used as app_data.
+	 * A generic callback is used to handle the return message.
+	 */
+	ncm->cb = (nss_ptr_t)nss_tx_msg_sync_callback;
+	ncm->app_data = (nss_ptr_t)sync_data;
+
+	BUG_ON(!tx_msg_async && !tx_msg_async_with_size);
+
+	/*
+	 * Per-subsystem asynchronous call to send down the message.
+	 */
+	if (tx_msg_async)
+		status = tx_msg_async(nss_ctx, ncm);
+	else
+		status = tx_msg_async_with_size(nss_ctx, ncm, msg_buf_size);
+
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Tx msg async failed\n", nss_ctx);
+		return status;
+	}
+
+	/*
+	 * Sleep. Wake up either by notification or timeout.
+	 */
+	ret = wait_for_completion_timeout(&sync_data->complete, msecs_to_jiffies(timeout));
+	if (!ret) {
+		nss_warning("%px: Tx msg sync timeout\n", nss_ctx);
+		return NSS_TX_FAILURE_SYNC_TIMEOUT;
+	}
+
+	/*
+	 * Wake up. Message response has been received within timeout.
+	 */
+	return sync_data->status;
+}
+
+/*
+ * nss_tx_msg_sync()
+ *	Send messages to FW synchronously with default message buffer size.
+ *
+ * tx_msg_async specifies the per-subsystem asynchronous call.
+ * timeout specifies the maximum sleep time for the completion.
+ * ncm is the original message the caller built.
+ * Since the caller cannot access the return message containing message response,
+ * we copy back message response from return message.
+ * resp_offset and copy_len specify the part of return message it'll copy.
+ */
+nss_tx_status_t nss_tx_msg_sync(struct nss_ctx_instance *nss_ctx,
+				nss_tx_msg_sync_subsys_async_t tx_msg_async,
+				uint32_t timeout, struct nss_cmn_msg *ncm,
+				uint32_t resp_offset, uint32_t copy_len)
+{
+	struct nss_tx_msg_sync_cmn_data sync_data;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	/*
+	 * Check Tx msg async API
+	 */
+	if (!unlikely(tx_msg_async)) {
+		nss_warning("%px: missing Tx msg async API\n", nss_ctx);
+		return NSS_TX_FAILURE_SYNC_BAD_PARAM;
+	}
+
+	/*
+	 * Initialize the per-message sync data.
+	 */
+	init_completion(&sync_data.complete);
+	sync_data.status = NSS_TX_FAILURE;
+	sync_data.original_msg = (void *)ncm;
+	sync_data.resp_offset = resp_offset;
+	sync_data.copy_len = copy_len;
+
+	return nss_tx_msg_sync_internal(nss_ctx, tx_msg_async, NULL, 0, &sync_data, ncm, timeout);
+}
+EXPORT_SYMBOL(nss_tx_msg_sync);
+
+/*
+ * nss_tx_msg_sync_with_size()
+ *	Send messages to FW synchronously with specified message buffer size.
+ */
+nss_tx_status_t nss_tx_msg_sync_with_size(struct nss_ctx_instance *nss_ctx,
+				nss_tx_msg_sync_subsys_async_with_size_t tx_msg_async_with_size,
+				uint32_t msg_buf_size, uint32_t timeout,
+				struct nss_cmn_msg *ncm, uint32_t resp_offset, uint32_t copy_len)
+{
+	struct nss_tx_msg_sync_cmn_data sync_data;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	/*
+	 * Check Tx msg async API
+	 */
+	if (!unlikely(tx_msg_async_with_size)) {
+		nss_warning("%px: missing Tx msg async API\n", nss_ctx);
+		return NSS_TX_FAILURE_SYNC_BAD_PARAM;
+	}
+
+	/*
+	 * Initialize the per-message sync data.
+	 */
+	init_completion(&sync_data.complete);
+	sync_data.status = NSS_TX_FAILURE;
+	sync_data.original_msg = (void *)ncm;
+	sync_data.resp_offset = resp_offset;
+	sync_data.copy_len = copy_len;
+
+	return nss_tx_msg_sync_internal(nss_ctx, NULL, tx_msg_async_with_size,
+					msg_buf_size, &sync_data, ncm, timeout);
+}
+EXPORT_SYMBOL(nss_tx_msg_sync_with_size);
diff --git a/qca-nss-drv/nss_tx_msg_sync.h b/qca-nss-drv/nss_tx_msg_sync.h
new file mode 100644
index 0000000..248287e
--- /dev/null
+++ b/qca-nss-drv/nss_tx_msg_sync.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * nss_tx_msg_sync.h
+ *	NSS Tx msg sync header file
+ */
+
+#ifndef __NSS_TX_MSG_SYNC_H
+#define __NSS_TX_MSG_SYNC_H
+
+#include <nss_core.h>
+
+/*
+ * Amount time in msec the synchronous message should wait for response
+ * from NSS before the timeout happens.
+ */
+#define NSS_TX_MSG_SYNC_DEFAULT_TIMEOUT_MSEC	(5000)
+
+/*
+ * Per-message sync data
+ *	Used as message app_data.
+ */
+struct nss_tx_msg_sync_cmn_data {
+	struct completion complete;		/* Completion structure */
+	nss_tx_status_t status;			/* Tx status */
+	void *original_msg;			/* Address of the caller-build message */
+	uint32_t resp_offset;			/* Response offset in message payload */
+	uint32_t copy_len;			/* Length in bytes copied from the return message */
+};
+
+/*
+ * nss_tx_msg_sync_subsys_async_t()
+ *	Tx msg asynchronous API of each subsystem.
+ */
+typedef nss_tx_status_t (*nss_tx_msg_sync_subsys_async_t)(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm);
+
+/*
+ * nss_tx_msg_sync_subsys_async_with_size_t()
+ *	Tx msg asynchronous API of each subsystem with message buffer size specified.
+ */
+typedef nss_tx_status_t (*nss_tx_msg_sync_subsys_async_with_size_t)(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, uint32_t size);
+
+/*
+ * nss_tx_msg_sync()
+ *	Core function to send message to FW synchronously.
+ *
+ * tx_msg_async specifies the per-subsystem asynchronous call.
+ * timeout specifies the maximum sleep time for the completion.
+ * ncm is the original message the caller built.
+ * Since the caller cannot access the return message containing message response,
+ * we copy back message response from the return message.
+ * resp_offset and copy_len specify the part of return message it'll copy.
+ */
+nss_tx_status_t nss_tx_msg_sync(struct nss_ctx_instance *nss_ctx,
+				nss_tx_msg_sync_subsys_async_t tx_msg_async,
+				uint32_t timeout, struct nss_cmn_msg *ncm,
+				uint32_t resp_offset, uint32_t copy_len);
+
+/*
+ * nss_tx_msg_sync_with_size()
+ *	Send messages to FW synchronously with specified message buffer size.
+ */
+nss_tx_status_t nss_tx_msg_sync_with_size(struct nss_ctx_instance *nss_ctx,
+				nss_tx_msg_sync_subsys_async_with_size_t tx_msg_async_with_size,
+				uint32_t msg_buf_size, uint32_t timeout,
+				struct nss_cmn_msg *ncm, uint32_t resp_offset, uint32_t copy_len);
+
+#endif /* __NSS_TX_MSG_SYNC_H */
diff --git a/qca-nss-drv/nss_tx_rx_common.h b/qca-nss-drv/nss_tx_rx_common.h
new file mode 100644
index 0000000..6e148c4
--- /dev/null
+++ b/qca-nss-drv/nss_tx_rx_common.h
@@ -0,0 +1,114 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_tx_rx_common.h
+ *	NSS APIs common header file
+ */
+
+#ifndef __NSS_TX_RX_COMMON_H
+#define __NSS_TX_RX_COMMON_H
+
+#include <nss_hal.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/kmemleak.h>
+#include "nss_tx_msg_sync.h"
+
+/*
+ * Global definitions
+ */
+#define NSS_HLOS_MESSAGE_VERSION 1	/* Update when the common message structure changed */
+
+#if (NSS_DEBUG_LEVEL > 0)
+#define NSS_VERIFY_CTX_MAGIC(x) nss_verify_ctx_magic(x)
+#define NSS_VERIFY_INIT_DONE(x) nss_verify_init_done(x)
+
+/*
+ * nss_verify_ctx_magic()
+ */
+static inline void nss_verify_ctx_magic(struct nss_ctx_instance *nss_ctx)
+{
+	nss_assert(nss_ctx->magic == NSS_CTX_MAGIC);
+}
+
+static inline void nss_verify_init_done(struct nss_ctx_instance *nss_ctx)
+{
+	nss_assert(nss_ctx->state == NSS_CORE_STATE_INITIALIZED);
+}
+
+#else
+#define NSS_VERIFY_CTX_MAGIC(x)
+#define NSS_VERIFY_INIT_DONE(x)
+#endif
+
+/*
+ * CB handlers for variour interfaces
+ */
+void nss_phys_if_register_handler(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_c2c_tx_register_handler(struct nss_ctx_instance *nss_ctx);
+extern void nss_c2c_rx_register_handler(struct nss_ctx_instance *nss_ctx);
+extern void nss_crypto_register_handler(void);
+extern void nss_crypto_cmn_register_handler(void);
+extern void nss_ipsec_register_handler(void);
+extern void nss_ipsec_cmn_register_handler(void);
+extern void nss_ipv4_register_handler(void);
+extern void nss_ipv4_reasm_register_handler(void);
+extern void nss_ipv6_register_handler(void);
+extern void nss_ipv6_reasm_register_handler(void);
+extern void nss_n2h_register_handler(struct nss_ctx_instance *nss_ctx);
+extern void nss_tunipip6_register_handler(void);
+extern void nss_pppoe_register_handler(void);
+extern void nss_freq_register_handler(void);
+extern void nss_eth_rx_register_handler(struct nss_ctx_instance *nss_ctx);
+extern void nss_edma_register_handler(void);
+extern void nss_lag_register_handler(void);
+extern void nss_dynamic_interface_register_handler(struct nss_ctx_instance *nss_ctx);
+extern void nss_gre_redir_register_handler(void);
+extern void nss_gre_redir_lag_us_register_handler(void);
+extern void nss_gre_redir_lag_ds_register_handler(void);
+extern void nss_lso_rx_register_handler(struct nss_ctx_instance *nss_ctx);
+extern void nss_sjack_register_handler(void);
+extern void nss_wifi_register_handler(void);
+extern struct net_device *nss_tstamp_register_netdev(void);
+extern void nss_tstamp_register_handler(struct net_device *ndev);
+extern void nss_portid_register_handler(void);
+extern void nss_oam_register_handler(void);
+extern void nss_dtls_register_handler(void);
+extern void nss_dtls_cmn_register_handler(void);
+extern void nss_tls_register_handler(void);
+extern void nss_gre_tunnel_register_handler(void);
+extern void nss_trustsec_tx_register_handler(void);
+extern void nss_wifili_register_handler(void);
+extern void nss_ppe_register_handler(void);
+extern void nss_gre_redir_mark_register_handler(void);
+extern void nss_ppe_vp_register_handler(void);
+extern void nss_wifi_mac_db_register_handler(void);
+extern void nss_wifi_ext_vdev_register_handler(void);
+extern void nss_wifili_thread_scheme_db_init(uint8_t core_id);
+extern void nss_wifi_mesh_init(void);
+
+/*
+ * nss_if_msg_handler()
+ *	External reference for internal base class handler for interface messages.
+ *
+ * This is not registered with nss_core.c as it is really a base class feature
+ * of the phys_if and virt_if handlers.
+ */
+extern void nss_if_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm,
+		__attribute__((unused))void *app_data);
+
+#endif /* __NSS_TX_RX_COMMON_H */
diff --git a/qca-nss-drv/nss_udp_st.c b/qca-nss-drv/nss_udp_st.c
new file mode 100755
index 0000000..eeab9ad
--- /dev/null
+++ b/qca-nss-drv/nss_udp_st.c
@@ -0,0 +1,233 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_udp_st.c
+ *	NSS UDP_ST APIs
+ */
+
+#include "nss_core.h"
+#include "nss_udp_st_stats.h"
+#include "nss_udp_st_strings.h"
+#include "nss_udp_st_log.h"
+
+#define NSS_UDP_ST_TX_MSG_TIMEOUT 1000	/* 1 sec timeout for udp_st messages */
+
+/*
+ * Private data structure for udp_st configuration
+ */
+struct nss_udp_st_pvt {
+	struct semaphore sem;		/* Semaphore structure */
+	struct completion complete;	/* completion structure */
+	int response;			/* Response from FW */
+	void *cb;			/* Original cb for sync msgs */
+	void *app_data;			/* Original app_data for sync msgs */
+} nss_udp_st_pvt;
+
+/*
+ * nss_udp_st_msg_handler()
+ *	Handle NSS -> HLOS messages for UDP_ST node
+ */
+static void nss_udp_st_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_udp_st_msg *num = (struct nss_udp_st_msg *)ncm;
+	nss_udp_st_msg_callback_t cb;
+
+	/*
+	 * Is this a valid message type?
+	 */
+	if (num->cm.type >= NSS_UDP_ST_MAX_MSG_TYPES) {
+		nss_warning("%px: received invalid message %d for udp_st interface", nss_ctx, num->cm.type);
+		return;
+	}
+
+	/*
+	 * Log messages.
+	 */
+	nss_udp_st_log_rx_msg(num);
+
+	switch (num->cm.type) {
+	case NSS_UDP_ST_STATS_SYNC_MSG:
+		/*
+		 * Update driver statistics and send stats notifications to the registered modules.
+		 */
+		nss_udp_st_stats_sync(nss_ctx, &num->msg.stats);
+		break;
+
+	case NSS_UDP_ST_RESET_STATS_MSG:
+		/*
+		 * This is a response to the statistics reset message.
+		 */
+		nss_udp_st_stats_reset(NSS_UDP_ST_INTERFACE);
+		break;
+	default:
+		if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+			/*
+			 * Check response.
+			 */
+			nss_info("%px: Received response %d for type %d, interface %d",
+						nss_ctx, ncm->response, ncm->type, ncm->interface);
+		}
+	}
+
+	/*
+	 * Return for NOTIFY messages because there is no notifier functions.
+	 */
+	if (num->cm.response == NSS_CMN_RESPONSE_NOTIFY) {
+		return;
+	}
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * Callback
+	 */
+	cb = (nss_udp_st_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, num);
+}
+
+/*
+ * nss_udp_st_tx_sync_callback()
+ *	Callback to handle the completion of synchronous tx messages.
+ */
+static void nss_udp_st_tx_sync_callback(void *app_data, struct nss_udp_st_msg *num)
+{
+	nss_udp_st_msg_callback_t callback = (nss_udp_st_msg_callback_t)nss_udp_st_pvt.cb;
+	void *data = nss_udp_st_pvt.app_data;
+
+	nss_udp_st_pvt.cb = NULL;
+	nss_udp_st_pvt.app_data = NULL;
+
+	if (num->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("udp_st error response %d\n", num->cm.response);
+		nss_udp_st_pvt.response = NSS_TX_FAILURE;
+	} else {
+		nss_udp_st_pvt.response = NSS_TX_SUCCESS;
+	}
+
+	if (callback) {
+		callback(data, num);
+	}
+
+	complete(&nss_udp_st_pvt.complete);
+}
+
+/*
+ * nss_udp_st_tx()
+ *	Transmit a udp_st message to the FW.
+ */
+nss_tx_status_t nss_udp_st_tx(struct nss_ctx_instance *nss_ctx, struct nss_udp_st_msg *num)
+{
+	struct nss_cmn_msg *ncm = &num->cm;
+
+	/*
+	 * Sanity check the message
+	 */
+	if (ncm->interface != NSS_UDP_ST_INTERFACE) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_UDP_ST_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_udp_st_log_tx_msg(num);
+
+	return nss_core_send_cmd(nss_ctx, num, sizeof(*num), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_udp_st_tx);
+
+/*
+ * nss_udp_st_tx_sync()
+ *	Transmit a synchronous udp_st message to the FW.
+ */
+nss_tx_status_t nss_udp_st_tx_sync(struct nss_ctx_instance *nss_ctx, struct nss_udp_st_msg *num)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&nss_udp_st_pvt.sem);
+	nss_udp_st_pvt.cb = (void *)num->cm.cb;
+	nss_udp_st_pvt.app_data = (void *)num->cm.app_data;
+
+	num->cm.cb = (nss_ptr_t)nss_udp_st_tx_sync_callback;
+	num->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_udp_st_tx(nss_ctx, num);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss udp_st msg tx failed\n", nss_ctx);
+		up(&nss_udp_st_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&nss_udp_st_pvt.complete, msecs_to_jiffies(NSS_UDP_ST_TX_MSG_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: udp_st tx sync failed due to timeout\n", nss_ctx);
+		nss_udp_st_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = nss_udp_st_pvt.response;
+	up(&nss_udp_st_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_udp_st_tx_sync);
+
+/*
+ * nss_udp_st_msg_init()
+ *	Initialize udp_st message.
+ */
+void nss_udp_st_msg_init(struct nss_udp_st_msg *num, uint16_t if_num, uint32_t type, uint32_t len,
+			nss_udp_st_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&num->cm, if_num, type, len, (void *)cb, app_data);
+}
+EXPORT_SYMBOL(nss_udp_st_msg_init);
+
+/*
+ * nss_udp_st_register_handler()
+ */
+void nss_udp_st_register_handler(struct nss_ctx_instance *nss_ctx)
+{
+	nss_core_register_handler(nss_ctx, NSS_UDP_ST_INTERFACE, nss_udp_st_msg_handler, NULL);
+
+	nss_udp_st_stats_dentry_create();
+	nss_udp_st_strings_dentry_create();
+
+	sema_init(&nss_udp_st_pvt.sem, 1);
+	init_completion(&nss_udp_st_pvt.complete);
+}
+
+/*
+ * nss_udp_st_get_mgr()
+ *
+ */
+struct nss_ctx_instance *nss_udp_st_get_mgr(void)
+{
+	return (void *)&nss_top_main.nss[nss_top_main.udp_st_handler_id];
+}
+EXPORT_SYMBOL(nss_udp_st_get_mgr);
diff --git a/qca-nss-drv/nss_udp_st_log.c b/qca-nss-drv/nss_udp_st_log.c
new file mode 100644
index 0000000..bd4e07b
--- /dev/null
+++ b/qca-nss-drv/nss_udp_st_log.c
@@ -0,0 +1,254 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_udp_st_log.c
+ *	NSS UDP Speedtest logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_udp_st_log_message_types_str
+ *	udp_st message strings
+ */
+static int8_t *nss_udp_st_log_message_types_str[NSS_UDP_ST_MAX_MSG_TYPES] __maybe_unused = {
+	"UDP_ST Start Msg",
+	"UDP_ST Stop Msg",
+	"UDP_ST Configure Rule Msg",
+	"UDP_ST Unconfigure Rule Msg",
+	"UDP_ST Stats Sync Msg",
+	"UDP_ST TX Create Msg",
+	"UDP_ST TX Destroy Msg",
+	"UDP_ST Reset Stats Msg",
+};
+
+/*
+ * nss_udp_st_log_error_response_types_str
+ *	Strings for error types for udp_st messages
+ */
+static int8_t *nss_udp_st_log_error_response_types_str[NSS_UDP_ST_ERROR_MAX] __maybe_unused = {
+	"UDP_ST No Error",
+	"UDP_ST Incorrect Rate",
+	"UDP_ST Incorrect Buffer Size",
+	"UDP_ST Memory Failure",
+	"UDP_ST Incorrect State",
+	"UDP_ST Incorrect Flags",
+	"UDP_ST Entry Exist",
+	"UDP_ST Entry Add Failed",
+	"UDP_ST Entry Not Exist",
+	"UDP_ST Wrong Start Msg Type",
+	"UDP_ST Wrong Stop Msg Type",
+	"UDP_ST Too Many Users",
+	"UDP_ST Unknown Msg Type",
+	"UDP_ST Pbuf Alloc Failure",
+	"UDP_ST Pbuf Size Failure",
+	"UDP_ST Drop Queue",
+	"UDP_ST Timer call missed",
+};
+
+/*
+ * nss_udp_st_log_tx_create_destroy_msg()
+ *	Log NSS udp_st Tx create/destroy message.
+ */
+static void nss_udp_st_log_tx_create_destroy_msg(struct nss_udp_st_msg *num, uint8_t *msg_type)
+{
+	struct nss_udp_st_tx_create *create __maybe_unused = &num->msg.create;
+	nss_trace("%px: NSS udp_st message: %s\n"
+		"Rate: %u\n"
+		"Buffer Size: %u\n"
+		"DSCP: %u\n",
+		create,
+		msg_type,
+		create->rate,
+		create->buffer_size,
+		create->dscp);
+}
+
+/*
+ * nss_udp_st_log_uncfg_rule_msg()
+ *	Log NSS udp_st unconfig rule message.
+ */
+static void nss_udp_st_log_uncfg_rule_msg(struct nss_udp_st_msg *num)
+{
+	struct nss_udp_st_cfg *uncfg __maybe_unused = &num->msg.uncfg;
+	nss_trace("%px: NSS udp_st message: Unconfig\n"
+		"IP version: %u\n",
+		uncfg,
+		uncfg->ip_version);
+
+	if (uncfg->ip_version == NSS_UDP_ST_FLAG_IPV4) {
+		nss_trace("Src IP: %pI4\n"
+			"Dest IP: %pI4\n",
+			&(uncfg->src_ip.ip.ipv4),
+			&(uncfg->dest_ip.ip.ipv4));
+	} else {
+		nss_trace("Src IP: %pI6\n"
+			"Dest IP: %pI6\n",
+			&(uncfg->src_ip.ip.ipv6),
+			&(uncfg->dest_ip.ip.ipv6));
+	}
+
+	nss_trace("Src Port: %u\n Dest Port: %u\n Type: %u\n",
+		uncfg->src_port, uncfg->dest_port, uncfg->type);
+}
+
+/*
+ * nss_udp_st_log_cfg_rule_msg()
+ *	Log NSS udp_st config rule message.
+ */
+static void nss_udp_st_log_cfg_rule_msg(struct nss_udp_st_msg *num)
+{
+	struct nss_udp_st_cfg *cfg __maybe_unused = &num->msg.cfg;
+	nss_trace("%px: NSS udp_st message: Config\n"
+		"IP version: %u\n",
+		cfg,
+		cfg->ip_version);
+
+	if (cfg->ip_version == NSS_UDP_ST_FLAG_IPV4) {
+		nss_trace("Src IP: %pI4\n"
+			"Dest IP: %pI4\n",
+			&(cfg->src_ip.ip.ipv4),
+			&(cfg->dest_ip.ip.ipv4));
+	} else {
+		nss_trace("Src IP: %pI6\n"
+			"Dest IP: %pI6\n",
+			&(cfg->src_ip.ip.ipv6),
+			&(cfg->dest_ip.ip.ipv6));
+	}
+
+	nss_trace("Src Port: %u\n Dest Port: %u\n Type: %u\n",
+		cfg->src_port, cfg->dest_port, cfg->type);
+}
+
+/*
+ * nss_udp_st_log_stop_msg()
+ *	Log NSS udp_st stop message.
+ */
+static void nss_udp_st_log_stop_msg(struct nss_udp_st_msg *num)
+{
+	struct nss_udp_st_stop *stop __maybe_unused = &num->msg.stop;
+	nss_trace("%px: NSS udp_st message: Stop\n"
+		"Type: %u\n",
+		stop,
+		stop->type);
+}
+
+/*
+ * nss_udp_st_log_start_msg()
+ *	Log NSS udp_st start message.
+ */
+static void nss_udp_st_log_start_msg(struct nss_udp_st_msg *num)
+{
+	struct nss_udp_st_start *start __maybe_unused = &num->msg.start;
+	nss_trace("%px: NSS udp_st message: Start\n"
+		"Type: %u\n",
+		start,
+		start->type);
+}
+
+/*
+ * nss_udp_st_log_verbose()
+ *	Log message contents.
+ */
+static void nss_udp_st_log_verbose(struct nss_udp_st_msg *num)
+{
+	switch (num->cm.type) {
+	case NSS_UDP_ST_START_MSG:
+		nss_udp_st_log_start_msg(num);
+		break;
+
+	case NSS_UDP_ST_STOP_MSG:
+		nss_udp_st_log_stop_msg(num);
+		break;
+
+	case NSS_UDP_ST_CFG_RULE_MSG:
+		nss_udp_st_log_cfg_rule_msg(num);
+		break;
+
+	case NSS_UDP_ST_UNCFG_RULE_MSG:
+		nss_udp_st_log_uncfg_rule_msg(num);
+		break;
+
+	case NSS_UDP_ST_TX_CREATE_MSG:
+		nss_udp_st_log_tx_create_destroy_msg(num, "Create");
+		break;
+
+	case NSS_UDP_ST_TX_DESTROY_MSG:
+		nss_udp_st_log_tx_create_destroy_msg(num, "Destroy");
+		break;
+
+	case NSS_UDP_ST_RESET_STATS_MSG:
+	case NSS_UDP_ST_STATS_SYNC_MSG:
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", num);
+		break;
+	}
+}
+
+/*
+ * nss_udp_st_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_udp_st_log_tx_msg(struct nss_udp_st_msg *num)
+{
+	if (num->cm.type >= NSS_UDP_ST_MAX_MSG_TYPES) {
+		nss_warning("%px: Invalid message type\n", num);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", num, num->cm.type, nss_udp_st_log_message_types_str[num->cm.type]);
+	nss_udp_st_log_verbose(num);
+}
+
+/*
+ * nss_udp_st_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_udp_st_log_rx_msg(struct nss_udp_st_msg *num)
+{
+	if (num->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", num);
+		return;
+	}
+
+	if (num->cm.response == NSS_CMN_RESPONSE_NOTIFY || (num->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", num, num->cm.type,
+			nss_udp_st_log_message_types_str[num->cm.type],
+			num->cm.response, nss_cmn_response_str[num->cm.response]);
+		goto verbose;
+	}
+
+	if (num->cm.error >= NSS_UDP_ST_ERROR_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			num, num->cm.type, nss_udp_st_log_message_types_str[num->cm.type],
+			num->cm.response, nss_cmn_response_str[num->cm.response],
+			num->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		num, num->cm.type, nss_udp_st_log_message_types_str[num->cm.type],
+		num->cm.response, nss_cmn_response_str[num->cm.response],
+		num->cm.error, nss_udp_st_log_error_response_types_str[num->cm.error]);
+
+verbose:
+	nss_udp_st_log_verbose(num);
+}
diff --git a/qca-nss-drv/nss_udp_st_log.h b/qca-nss-drv/nss_udp_st_log.h
new file mode 100644
index 0000000..fa2a551
--- /dev/null
+++ b/qca-nss-drv/nss_udp_st_log.h
@@ -0,0 +1,39 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_UDP_ST_LOG_H__
+#define __NSS_UDP_ST_LOG_H__
+
+/*
+ * nss_udp_st_log.h
+ *	NSS UDP Speedtest Log Header File.
+ */
+
+/*
+ * nss_udp_st_log_tx_msg
+ *	Logs a udp_st message that is sent to the NSS firmware.
+ */
+void nss_udp_st_log_tx_msg(struct nss_udp_st_msg *num);
+
+/*
+ * nss_udp_st_log_rx_msg
+ *	Logs a udp_st message that is received from the NSS firmware.
+ */
+void nss_udp_st_log_rx_msg(struct nss_udp_st_msg *num);
+
+#endif /* __NSS_UDP_ST_LOG_H__*/
diff --git a/qca-nss-drv/nss_udp_st_stats.c b/qca-nss-drv/nss_udp_st_stats.c
new file mode 100755
index 0000000..0fee47b
--- /dev/null
+++ b/qca-nss-drv/nss_udp_st_stats.c
@@ -0,0 +1,178 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_udp_st_stats.h"
+#include "nss_udp_st_strings.h"
+
+uint32_t nss_udp_st_errors[NSS_UDP_ST_ERROR_MAX];
+uint32_t nss_udp_st_stats_time[NSS_UDP_ST_TEST_MAX][NSS_UDP_ST_STATS_TIME_MAX];
+
+/*
+ * nss_udp_st_stats_read()
+ *	Read UDP_ST stats.
+ */
+static ssize_t nss_udp_st_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	/*
+	 * Max output lines = #stats * NSS_MAX_CORES  +
+	 * few blank lines for banner printing + Number of Extra outputlines for future reference to add new stats
+	 */
+	uint32_t max_output_lines = NSS_STATS_NODE_MAX + NSS_UDP_ST_ERROR_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+	uint32_t i;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	/*
+	 * Note: The assumption here is that we do not have more than 64 stats.
+	 */
+	stats_shadow = kzalloc(64 * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "udp_st", NSS_STATS_SINGLE_CORE);
+
+	size_wr += nss_stats_fill_common_stats(NSS_UDP_ST_INTERFACE, NSS_STATS_SINGLE_INSTANCE, lbuf, size_wr, size_al, "udp_st");
+
+	/*
+	 * Error stats
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; (i < NSS_UDP_ST_ERROR_MAX); i++) {
+		stats_shadow[i] = nss_udp_st_errors[i];
+	}
+	spin_unlock_bh(&nss_top_main.stats_lock);
+	size_wr += nss_stats_print("udp_st", "udp_st error stats"
+					, NSS_STATS_SINGLE_INSTANCE
+					, nss_udp_st_strings_error_stats
+					, stats_shadow
+					, NSS_UDP_ST_ERROR_MAX
+					, lbuf, size_wr, size_al);
+
+	/*
+	 * Rx time stats
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; (i < NSS_UDP_ST_STATS_TIME_MAX); i++) {
+		stats_shadow[i] = nss_udp_st_stats_time[NSS_UDP_ST_TEST_RX][i];
+	}
+	spin_unlock_bh(&nss_top_main.stats_lock);
+	size_wr += nss_stats_print("udp_st", "udp_st Rx time stats (ms)"
+					, NSS_STATS_SINGLE_INSTANCE
+					, nss_udp_st_strings_rx_time_stats
+					, stats_shadow
+					, NSS_UDP_ST_STATS_TIME_MAX
+					, lbuf, size_wr, size_al);
+
+	/*
+	 * Tx time stats
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; (i < NSS_UDP_ST_STATS_TIME_MAX); i++) {
+		stats_shadow[i] = nss_udp_st_stats_time[NSS_UDP_ST_TEST_TX][i];
+	}
+	spin_unlock_bh(&nss_top_main.stats_lock);
+	size_wr += nss_stats_print("udp_st", "udp_st Tx time stats (ms)"
+					, NSS_STATS_SINGLE_INSTANCE
+					, nss_udp_st_strings_tx_time_stats
+					, stats_shadow
+					, NSS_UDP_ST_STATS_TIME_MAX
+					, lbuf, size_wr, size_al);
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_udp_st_stats_ops.
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(udp_st);
+
+/*
+ * nss_udp_st_stats_dentry_create()
+ *	Create udp_st statistics debug entry.
+ */
+void nss_udp_st_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("udp_st", &nss_udp_st_stats_ops);
+}
+
+/*
+ * nss_udp_st_stats_reset()
+ *	Reset the udp_st statistics.
+ */
+void nss_udp_st_stats_reset(uint32_t if_num)
+{
+	uint32_t i;
+
+	/*
+	 * Reset common node stats.
+	 */
+	nss_stats_reset_common_stats(if_num);
+
+	/*
+	 * Reset error stats.
+	 */
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; i < NSS_UDP_ST_ERROR_MAX; i++) {
+		nss_udp_st_errors[i] = 0;
+	}
+	spin_unlock_bh(&nss_top_main.stats_lock);
+}
+
+/*
+ * nss_udp_st_stats_sync()
+ *	Handle the syncing of UDP_ST node statistics.
+ */
+void nss_udp_st_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_udp_st_stats *nus)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	uint32_t i, j;
+
+	spin_lock_bh(&nss_top->stats_lock);
+
+	nss_top->stats_node[NSS_UDP_ST_INTERFACE][NSS_STATS_NODE_RX_PKTS] += nus->nstats.node_stats.rx_packets;
+	nss_top->stats_node[NSS_UDP_ST_INTERFACE][NSS_STATS_NODE_RX_BYTES] += nus->nstats.node_stats.rx_bytes;
+	nss_top->stats_node[NSS_UDP_ST_INTERFACE][NSS_STATS_NODE_TX_PKTS] += nus->nstats.node_stats.tx_packets;
+	nss_top->stats_node[NSS_UDP_ST_INTERFACE][NSS_STATS_NODE_TX_BYTES] += nus->nstats.node_stats.tx_bytes;
+
+	for (i = 0; i < NSS_UDP_ST_ERROR_MAX; i++) {
+		nss_udp_st_errors[i] += nus->nstats.errors[i];
+	}
+
+	for (i = 0; i < NSS_UDP_ST_TEST_MAX; i++) {
+		for (j = 0; j < NSS_UDP_ST_STATS_TIME_MAX; j++) {
+			nss_udp_st_stats_time[i][j] = nus->time_stats[i][j];
+		}
+	}
+	spin_unlock_bh(&nss_top->stats_lock);
+}
diff --git a/qca-nss-drv/nss_udp_st_stats.h b/qca-nss-drv/nss_udp_st_stats.h
new file mode 100755
index 0000000..86b387d
--- /dev/null
+++ b/qca-nss-drv/nss_udp_st_stats.h
@@ -0,0 +1,36 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_UDP_ST_STATS_H
+#define __NSS_UDP_ST_STATS_H
+
+#include <nss_cmn.h>
+
+/*
+ * nss_udp_st_stats.h
+ *	NSS driver UDP_ST statistics header file.
+ */
+
+/*
+ * udp_st statistics APIs
+ */
+extern void nss_udp_st_stats_reset(uint32_t if_num);
+extern void nss_udp_st_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_udp_st_stats *nus);
+extern void nss_udp_st_stats_dentry_create(void);
+
+#endif /* __NSS_UDP_ST_STATS_H */
diff --git a/qca-nss-drv/nss_udp_st_strings.c b/qca-nss-drv/nss_udp_st_strings.c
new file mode 100644
index 0000000..3b67b13
--- /dev/null
+++ b/qca-nss-drv/nss_udp_st_strings.c
@@ -0,0 +1,151 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include <nss_udp_st.h>
+#include "nss_strings.h"
+
+/*
+ * nss_udp_st_strings_error_stats
+ *	Statistics strings for udp_st errors.
+ */
+struct nss_stats_info nss_udp_st_strings_error_stats[NSS_UDP_ST_ERROR_MAX] = {
+	{"error_none"				, NSS_STATS_TYPE_SPECIAL},
+	{"incorrect_rate"			, NSS_STATS_TYPE_DROP},
+	{"incorrect_buffer_size"		, NSS_STATS_TYPE_DROP},
+	{"memory_failure"			, NSS_STATS_TYPE_DROP},
+	{"incorrect_state"			, NSS_STATS_TYPE_DROP},
+	{"incorrect_flags"			, NSS_STATS_TYPE_DROP},
+	{"entry_exist"				, NSS_STATS_TYPE_DROP},
+	{"entry_add_failed"			, NSS_STATS_TYPE_DROP},
+	{"entry_not_exist"			, NSS_STATS_TYPE_DROP},
+	{"wrong_start_msg_type"			, NSS_STATS_TYPE_DROP},
+	{"wrong_stop_msg_type"			, NSS_STATS_TYPE_DROP},
+	{"too_many_users"			, NSS_STATS_TYPE_DROP},
+	{"unknown_msg_type"			, NSS_STATS_TYPE_DROP},
+	{"pb_alloc_failure"			, NSS_STATS_TYPE_DROP},
+	{"pb_size_failure"			, NSS_STATS_TYPE_DROP},
+	{"drop_queue_failure"			, NSS_STATS_TYPE_DROP},
+	{"timer call is missed"			, NSS_STATS_TYPE_SPECIAL},
+};
+
+/*
+ * nss_udp_st_strings_rx_time_stats
+ *	Statistics strings for Rx udp_st time.
+ */
+struct nss_stats_info nss_udp_st_strings_rx_time_stats[NSS_UDP_ST_STATS_TIME_MAX] = {
+	{"rx_start_time"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_current_time"		, NSS_STATS_TYPE_SPECIAL},
+	{"rx_elapsed_time"		, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_udp_st_strings_tx_time_stats
+ *	Statistics strings for Tx udp_st time.
+ */
+struct nss_stats_info nss_udp_st_strings_tx_time_stats[NSS_UDP_ST_STATS_TIME_MAX] = {
+	{"tx_start_time"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_current_time"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_elapsed_time"			, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_udp_st_error_stats_strings_read()
+ *	Read udp_st error statistics names.
+ */
+static ssize_t nss_udp_st_error_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_udp_st_strings_error_stats, NSS_UDP_ST_ERROR_MAX);
+}
+
+/*
+ * nss_udp_st_rx_time_stats_strings_read()
+ *	Read Rx udp_st time statistics names.
+ */
+static ssize_t nss_udp_st_rx_time_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_udp_st_strings_rx_time_stats, NSS_UDP_ST_STATS_TIME_MAX);
+}
+
+/*
+ * nss_udp_st_tx_time_stats_strings_read()
+ *	Read Tx udp_st time statistics names.
+ */
+static ssize_t nss_udp_st_tx_time_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_udp_st_strings_tx_time_stats, NSS_UDP_ST_STATS_TIME_MAX);
+}
+
+/*
+ * nss_udp_st_error_stats_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(udp_st_error_stats);
+
+/*
+ * nss_udp_st_rx_time_stats_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(udp_st_rx_time_stats);
+
+/*
+ * nss_udp_st_tx_time_stats_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(udp_st_tx_time_stats);
+
+/*
+ * nss_udp_st_strings_dentry_create()
+ *      Create udp_st statistics strings debug entry.
+ */
+void nss_udp_st_strings_dentry_create(void)
+{
+	struct dentry *dir_d;
+	struct dentry *file_d;
+
+	if (!nss_top_main.strings_dentry) {
+		nss_warning("qca-nss-drv/strings is not present");
+		return;
+	}
+
+	dir_d = debugfs_create_dir("udp_st", nss_top_main.strings_dentry);
+	if (!dir_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/udp_st directory");
+		return;
+	}
+
+	file_d = debugfs_create_file("error_stats_str", 0400, dir_d, &nss_top_main, &nss_udp_st_error_stats_strings_ops);
+	if (!file_d) {
+		nss_warning("Failed to create qca-nss-drv/stats/udp_st/error_stats_str file");
+		goto fail;
+	}
+
+	file_d = debugfs_create_file("rx_time_stats_str", 0400, dir_d, &nss_top_main, &nss_udp_st_rx_time_stats_strings_ops);
+	if (!file_d) {
+		nss_warning("Failed to create qca-nss-drv/stats/udp_st/rx_time_stats_str file");
+		goto fail;
+	}
+
+	file_d = debugfs_create_file("tx_time_stats_str", 0400, dir_d, &nss_top_main, &nss_udp_st_tx_time_stats_strings_ops);
+	if (!file_d) {
+		nss_warning("Failed to create qca-nss-drv/stats/udp_st/tx_time_stats_str file");
+		goto fail;
+	}
+
+	return;
+fail:
+	debugfs_remove_recursive(dir_d);
+}
diff --git a/qca-nss-drv/nss_udp_st_strings.h b/qca-nss-drv/nss_udp_st_strings.h
new file mode 100644
index 0000000..6f5b513
--- /dev/null
+++ b/qca-nss-drv/nss_udp_st_strings.h
@@ -0,0 +1,28 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_UDP_ST_STRINGS_H
+#define __NSS_UDP_ST_STRINGS_H
+
+extern struct nss_stats_info nss_udp_st_strings_error_stats[NSS_UDP_ST_ERROR_MAX];
+extern struct nss_stats_info nss_udp_st_strings_rx_time_stats[NSS_UDP_ST_STATS_TIME_MAX];
+extern struct nss_stats_info nss_udp_st_strings_tx_time_stats[NSS_UDP_ST_STATS_TIME_MAX];
+
+extern void nss_udp_st_strings_dentry_create(void);
+
+#endif /* __NSS_UDP_ST_STRINGS_H */
diff --git a/qca-nss-drv/nss_unaligned.c b/qca-nss-drv/nss_unaligned.c
new file mode 100644
index 0000000..099abdb
--- /dev/null
+++ b/qca-nss-drv/nss_unaligned.c
@@ -0,0 +1,91 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_unaligned.c
+ *	NSS unaligned APIs
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_unaligned_stats.h"
+#include "nss_unaligned_log.h"
+
+/*
+ * nss_unaligned_update_stats()
+ *	Updates the statistics in the nss_ctx.
+ */
+static void nss_unaligned_update_stats(struct nss_ctx_instance *nss_ctx,
+					struct nss_unaligned_stats_msg *usm)
+{
+	uint32_t start_index = NSS_UNALIGNED_OPS_PER_MSG * usm->current_iteration;
+	uint32_t i;
+	spin_lock_bh(&nss_top_main.stats_lock);
+	nss_ctx->unaligned_stats.trap_count = usm->trap_count;
+	for (i = 0; i < NSS_UNALIGNED_OPS_PER_MSG; i++) {
+		uint32_t index = i + start_index;
+		if (unlikely(index >= NSS_UNALIGNED_EMULATED_OPS)) {
+			break;
+		}
+		nss_ctx->unaligned_stats.ops[index] = usm->ops[i];
+	}
+	spin_unlock_bh(&nss_top_main.stats_lock);
+}
+
+/*
+ * nss_unaligned_msg_handler()
+ *	Handles metadata messages on the unaligned interface.
+ */
+static void nss_unaligned_msg_handler(struct nss_ctx_instance *nss_ctx,
+		struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_unaligned_msg *um = (struct nss_unaligned_msg *)ncm;
+
+	/*
+	 * Sanity checks on message
+	 */
+	if (um->cm.type >= NSS_UNALIGNED_MSG_MAX) {
+		nss_warning("%px: message type out of range: %d\n", nss_ctx, um->cm.type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(&(um->cm)) > sizeof(struct nss_unaligned_msg)) {
+		nss_warning("%px: message length is invalid: %d\n", nss_ctx, nss_cmn_get_msg_len(&(um->cm)));
+		return;
+	}
+
+	nss_unaligned_log_rx_msg(um);
+
+	switch (um->cm.type) {
+	case NSS_UNALIGNED_MSG_STATS:
+		nss_unaligned_update_stats(nss_ctx, &um->msg.stats_msg);
+		return;
+	}
+
+	nss_core_log_msg_failures(nss_ctx, ncm);
+}
+
+/*
+ * nss_unaligned_register_handler()
+ *	Registers message handler on the NSS unaligned interface and stats dentry.
+ */
+void nss_unaligned_register_handler(struct nss_ctx_instance *nss_ctx)
+{
+	nss_core_register_handler(nss_ctx, NSS_UNALIGNED_INTERFACE, nss_unaligned_msg_handler, NULL);
+
+	if (nss_ctx->id == NSS_CORE_0) {
+		nss_unaligned_stats_dentry_create();
+	}
+}
diff --git a/qca-nss-drv/nss_unaligned_log.c b/qca-nss-drv/nss_unaligned_log.c
new file mode 100644
index 0000000..079e2d7
--- /dev/null
+++ b/qca-nss-drv/nss_unaligned_log.c
@@ -0,0 +1,75 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_unaligned_log.c
+ *	NSS unaligned logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_unaligned_log_message_types_str
+ *	NSS unaligned message strings
+ */
+static int8_t *nss_unaligned_log_message_types_str[NSS_UNALIGNED_MSG_MAX] __maybe_unused = {
+	"Unaligned Stats Message",
+};
+
+/*
+ * nss_unaligned_log_verbose()
+ *	Log message contents.
+ */
+static void nss_unaligned_log_verbose(struct nss_unaligned_msg *um)
+{
+	switch (um->cm.type) {
+	case NSS_UNALIGNED_MSG_STATS:
+		/*
+		 * No log for valid stats message.
+		 */
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", um);
+		break;
+	}
+}
+
+/*
+ * nss_unaligned_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_unaligned_log_rx_msg(struct nss_unaligned_msg *um)
+{
+	if (um->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", um);
+		return;
+	}
+
+	if (um->cm.response == NSS_CMN_RESPONSE_NOTIFY || (um->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", um, um->cm.type,
+			nss_unaligned_log_message_types_str[um->cm.type],
+			um->cm.response, nss_cmn_response_str[um->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		um, um->cm.type, nss_unaligned_log_message_types_str[um->cm.type],
+		um->cm.response, nss_cmn_response_str[um->cm.response]);
+
+verbose:
+	nss_unaligned_log_verbose(um);
+}
diff --git a/qca-nss-drv/nss_unaligned_log.h b/qca-nss-drv/nss_unaligned_log.h
new file mode 100644
index 0000000..98ec707
--- /dev/null
+++ b/qca-nss-drv/nss_unaligned_log.h
@@ -0,0 +1,31 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_UNALIGNED_LOG_H__
+#define __NSS_UNALIGNED_LOG_H__
+
+/*
+ * nss_unaligned_log.h
+ *	NSS Unaligned Log Header File.
+ */
+
+/*
+ * nss_unaligned_log_rx_msg
+ *	Logs an unaligned trap handler message that is received from the NSS firmware.
+ */
+void nss_unaligned_log_rx_msg(struct nss_unaligned_msg *um);
+
+#endif /* __NSS_UNALIGNED_LOG_H__ */
diff --git a/qca-nss-drv/nss_unaligned_stats.c b/qca-nss-drv/nss_unaligned_stats.c
new file mode 100644
index 0000000..af0fd74
--- /dev/null
+++ b/qca-nss-drv/nss_unaligned_stats.c
@@ -0,0 +1,88 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_unaligned_stats.h"
+
+/*
+ * nss_unaligned_stats_read()
+ *	Read unaligned stats
+ */
+static ssize_t nss_unaligned_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	uint32_t max_output_lines = NSS_MAX_CORES * NSS_UNALIGNED_OPS_PER_MSG;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	struct nss_unaligned_stats *stats_shadow;
+	uint32_t i, j;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(!lbuf)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_MAX_CORES * sizeof(struct nss_unaligned_stats), GFP_KERNEL);
+	if (unlikely(!stats_shadow)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	spin_lock_bh(&nss_top_main.stats_lock);
+	for (i = 0; i < NSS_MAX_CORES; i++) {
+		stats_shadow[i] = nss_top_main.nss[i].unaligned_stats;
+	}
+	spin_unlock_bh(&nss_top_main.stats_lock);
+
+	for (i = 0; i < NSS_MAX_CORES; i++) {
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+			"core: %u, total unaligned traps: %llu\n",
+			i, stats_shadow[i].trap_count);
+		for (j = 0; j < NSS_UNALIGNED_OPS_PER_MSG; j++) {
+			struct nss_unaligned_stats_op op = stats_shadow[i].ops[j];
+			if (op.count == 0) {
+				break;
+			}
+
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+				"op: %2x, ext: %2x, count:%10llu, min: %10u, avg: %10u, max: %10u\n",
+				op.opcode_primary, op.opcode_extension, op.count, op.ticks_min,
+				op.ticks_avg, op.ticks_max);
+		}
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+
+	return bytes_read;
+}
+
+/*
+ * nss_unaligned_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(unaligned)
+
+/*
+ * nss_unaligned_stats_dentry_create()
+ *	Create unaligned statistics debug entry.
+ */
+void nss_unaligned_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("unaligned", &nss_unaligned_stats_ops);
+}
diff --git a/qca-nss-drv/nss_unaligned_stats.h b/qca-nss-drv/nss_unaligned_stats.h
new file mode 100644
index 0000000..761cda6
--- /dev/null
+++ b/qca-nss-drv/nss_unaligned_stats.h
@@ -0,0 +1,22 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_UNALIGNED_STATS_H
+#define __NSS_UNALIGNED_STATS_H
+
+extern void nss_unaligned_stats_dentry_create(void);
+
+#endif
diff --git a/qca-nss-drv/nss_virt_if.c b/qca-nss-drv/nss_virt_if.c
new file mode 100644
index 0000000..b530517
--- /dev/null
+++ b/qca-nss-drv/nss_virt_if.c
@@ -0,0 +1,736 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_virt_if.c
+ *	NSS virtual/redirect handler APIs
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_virt_if_stats.h"
+#include <net/arp.h>
+
+#define NSS_VIRT_IF_TX_TIMEOUT			3000 /* 3 Seconds */
+#define NSS_VIRT_IF_GET_INDEX(if_num)	(if_num-NSS_DYNAMIC_IF_START)
+
+extern int nss_ctl_redirect;
+
+/*
+ * Data structure that holds the virtual interface context.
+ */
+struct nss_virt_if_handle *nss_virt_if_handle_t[NSS_MAX_DYNAMIC_INTERFACES];
+
+/*
+ * Spinlock to protect the global data structure virt_handle.
+ */
+DEFINE_SPINLOCK(nss_virt_if_lock);
+
+/*
+ * nss_virt_if_get_context()
+ */
+struct nss_ctx_instance *nss_virt_if_get_context(void)
+{
+	return &nss_top_main.nss[nss_top_main.virt_if_handler_id];
+}
+
+/*
+ * nss_virt_if_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+bool nss_virt_if_verify_if_num(uint32_t if_num)
+{
+	enum nss_dynamic_interface_type type = nss_dynamic_interface_get_type(nss_virt_if_get_context(), if_num);
+
+	return type == NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_N2H
+		|| type == NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_H2N;
+}
+EXPORT_SYMBOL(nss_virt_if_verify_if_num);
+
+/*
+ * nss_virt_if_msg_handler()
+ *	Handle msg responses from the FW on virtual interfaces
+ */
+static void nss_virt_if_msg_handler(struct nss_ctx_instance *nss_ctx,
+					struct nss_cmn_msg *ncm,
+					void *app_data)
+{
+	struct nss_virt_if_msg *nvim = (struct nss_virt_if_msg *)ncm;
+	int32_t if_num;
+
+	nss_virt_if_msg_callback_t cb;
+	struct nss_virt_if_handle *handle = NULL;
+
+	/*
+	 * Sanity check the message type
+	 */
+	if (ncm->type > NSS_VIRT_IF_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return;
+	}
+
+	/*
+	 * Messages value that are within the base class are handled by the base class.
+	 */
+	if (ncm->type < NSS_IF_MAX_MSG_TYPES) {
+		return nss_if_msg_handler(nss_ctx, ncm, app_data);
+	}
+
+	if (!nss_virt_if_verify_if_num(ncm->interface)) {
+		nss_warning("%px: response for another interface: %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	if_num = NSS_VIRT_IF_GET_INDEX(ncm->interface);
+
+	spin_lock_bh(&nss_virt_if_lock);
+	if (!nss_virt_if_handle_t[if_num]) {
+		spin_unlock_bh(&nss_virt_if_lock);
+		nss_warning("%px: virt_if handle is NULL\n", nss_ctx);
+		return;
+	}
+
+	handle = nss_virt_if_handle_t[if_num];
+	spin_unlock_bh(&nss_virt_if_lock);
+
+	switch (nvim->cm.type) {
+	case NSS_VIRT_IF_STATS_SYNC_MSG:
+		nss_virt_if_stats_sync(handle, &nvim->msg.stats);
+		break;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, IPv4 sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->subsys_dp_register[ncm->interface].ndev;
+	}
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * Callback
+	 */
+	cb = (nss_virt_if_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, ncm);
+}
+
+/*
+ * nss_virt_if_callback
+ *	Callback to handle the completion of NSS ->HLOS messages.
+ */
+static void nss_virt_if_callback(void *app_data, struct nss_cmn_msg *ncm)
+{
+	struct nss_virt_if_handle *handle = (struct nss_virt_if_handle *)app_data;
+	struct nss_virt_if_pvt *nvip = handle->pvt;
+
+	if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("%px: virt_if Error response %d\n", handle->nss_ctx, ncm->response);
+		nvip->response = NSS_TX_FAILURE;
+		complete(&nvip->complete);
+		return;
+	}
+
+	nvip->response = NSS_TX_SUCCESS;
+	complete(&nvip->complete);
+}
+
+/*
+ * nss_virt_if_tx_msg_sync
+ *	Send a message from HLOS to NSS synchronously.
+ */
+static nss_tx_status_t nss_virt_if_tx_msg_sync(struct nss_virt_if_handle *handle,
+						struct nss_virt_if_msg *nvim)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+	struct nss_virt_if_pvt *nwip = handle->pvt;
+	struct nss_ctx_instance *nss_ctx = handle->nss_ctx;
+
+	down(&nwip->sem);
+
+	status = nss_virt_if_tx_msg(nss_ctx, nvim);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_virt_if_msg failed\n", nss_ctx);
+		up(&nwip->sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&nwip->complete,
+						msecs_to_jiffies(NSS_VIRT_IF_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: virt_if tx failed due to timeout\n", nss_ctx);
+		nwip->response = NSS_TX_FAILURE;
+	}
+
+	status = nwip->response;
+	up(&nwip->sem);
+
+	return status;
+}
+
+/*
+ * nss_virt_if_msg_init()
+ *	Initialize virt specific message structure.
+ */
+static void nss_virt_if_msg_init(struct nss_virt_if_msg *nvim,
+					uint16_t if_num,
+					uint32_t type,
+					uint32_t len,
+					nss_virt_if_msg_callback_t cb,
+					struct nss_virt_if_handle *app_data)
+{
+	nss_cmn_msg_init(&nvim->cm, if_num, type, len, (void *)cb, (void *)app_data);
+}
+
+/*
+ * nss_virt_if_handle_destroy_sync()
+ *	Destroy the virt handle either due to request from user or due to error, synchronously.
+ */
+static int nss_virt_if_handle_destroy_sync(struct nss_virt_if_handle *handle)
+{
+	nss_tx_status_t status;
+	int32_t if_num_n2h = handle->if_num_n2h;
+	int32_t if_num_h2n = handle->if_num_h2n;
+	int32_t index_n2h;
+	int32_t index_h2n;
+
+	if (!nss_virt_if_verify_if_num(if_num_n2h) || !nss_virt_if_verify_if_num(if_num_h2n)) {
+		nss_warning("%px: bad interface numbers %d %d\n", handle->nss_ctx, if_num_n2h, if_num_h2n);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	index_n2h = NSS_VIRT_IF_GET_INDEX(if_num_n2h);
+	index_h2n = NSS_VIRT_IF_GET_INDEX(if_num_h2n);
+
+	status = nss_dynamic_interface_dealloc_node(if_num_n2h, NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_N2H);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Dynamic interface destroy failed status %d\n", handle->nss_ctx, status);
+		return status;
+	}
+
+	status = nss_dynamic_interface_dealloc_node(if_num_h2n, NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_H2N);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Dynamic interface destroy failed status %d\n", handle->nss_ctx, status);
+		return status;
+	}
+
+	spin_lock_bh(&nss_virt_if_lock);
+	nss_virt_if_handle_t[index_n2h] = NULL;
+	nss_virt_if_handle_t[index_h2n] = NULL;
+	spin_unlock_bh(&nss_virt_if_lock);
+
+	kfree(handle->pvt);
+	kfree(handle);
+
+	return status;
+}
+
+/*
+ * nss_virt_if_handle_create_sync()
+ *	Initialize virt handle which holds the if_num and stats per interface.
+ */
+static struct nss_virt_if_handle *nss_virt_if_handle_create_sync(struct nss_ctx_instance *nss_ctx, int32_t if_num_n2h, int32_t if_num_h2n, int32_t *cmd_rsp)
+{
+	int32_t index_n2h;
+	int32_t index_h2n;
+	struct nss_virt_if_handle *handle;
+
+	if (!nss_virt_if_verify_if_num(if_num_n2h) || !nss_virt_if_verify_if_num(if_num_h2n)) {
+		nss_warning("%px: bad interface numbers %d %d\n", nss_ctx, if_num_n2h, if_num_h2n);
+		return NULL;
+	}
+
+	index_n2h = NSS_VIRT_IF_GET_INDEX(if_num_n2h);
+	index_h2n = NSS_VIRT_IF_GET_INDEX(if_num_h2n);
+
+	handle = (struct nss_virt_if_handle *)kzalloc(sizeof(struct nss_virt_if_handle),
+									GFP_KERNEL);
+	if (!handle) {
+		nss_warning("%px: handle memory alloc failed\n", nss_ctx);
+		*cmd_rsp = NSS_VIRT_IF_ALLOC_FAILURE;
+		goto error1;
+	}
+
+	handle->nss_ctx = nss_ctx;
+	handle->if_num_n2h = if_num_n2h;
+	handle->if_num_h2n = if_num_h2n;
+	handle->pvt = (struct nss_virt_if_pvt *)kzalloc(sizeof(struct nss_virt_if_pvt),
+								GFP_KERNEL);
+	if (!handle->pvt) {
+		nss_warning("%px: failure allocating memory for nss_virt_if_pvt\n", nss_ctx);
+		*cmd_rsp = NSS_VIRT_IF_ALLOC_FAILURE;
+		goto error2;
+	}
+
+	handle->cb = NULL;
+	handle->app_data = NULL;
+
+	spin_lock_bh(&nss_virt_if_lock);
+	nss_virt_if_handle_t[index_n2h] = handle;
+	nss_virt_if_handle_t[index_h2n] = handle;
+	spin_unlock_bh(&nss_virt_if_lock);
+
+	*cmd_rsp = NSS_VIRT_IF_SUCCESS;
+
+	return handle;
+
+error2:
+	kfree(handle);
+error1:
+	return NULL;
+}
+
+/*
+ * nss_virt_if_register_handler_sync()
+ * 	register msg handler for virtual interface and initialize semaphore and completion.
+ */
+static uint32_t nss_virt_if_register_handler_sync(struct nss_ctx_instance *nss_ctx, struct nss_virt_if_handle *handle)
+{
+	uint32_t ret;
+	struct nss_virt_if_pvt *nvip = NULL;
+	int32_t if_num_n2h = handle->if_num_n2h;
+	int32_t if_num_h2n = handle->if_num_h2n;
+
+	ret = nss_core_register_handler(nss_ctx, if_num_n2h, nss_virt_if_msg_handler, NULL);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Failed to register message handler for redir_n2h interface %d\n", nss_ctx, if_num_n2h);
+		return NSS_VIRT_IF_CORE_FAILURE;
+	}
+
+	ret = nss_core_register_handler(nss_ctx, if_num_h2n, nss_virt_if_msg_handler, NULL);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_core_unregister_handler(nss_ctx, if_num_n2h);
+		nss_warning("%px: Failed to register message handler for redir_h2n interface %d\n", nss_ctx, if_num_h2n);
+		return NSS_VIRT_IF_CORE_FAILURE;
+	}
+
+	nvip = handle->pvt;
+	if (!nvip->sem_init_done) {
+		sema_init(&nvip->sem, 1);
+		init_completion(&nvip->complete);
+		nvip->sem_init_done = 1;
+	}
+
+	nss_virt_if_stats_dentry_create();
+	return NSS_VIRT_IF_SUCCESS;
+}
+
+/*
+ * nss_virt_if_create_sync_nexthop()
+ *	Create redir_n2h and redir_h2n interfaces, synchronously and associate it with same netdev.
+ */
+struct nss_virt_if_handle *nss_virt_if_create_sync_nexthop(struct net_device *netdev, uint32_t nexthop_n2h, uint32_t nexthop_h2n)
+{
+	struct nss_ctx_instance *nss_ctx = nss_virt_if_get_context();
+	struct nss_virt_if_msg nvim;
+	struct nss_virt_if_config_msg *nvcm;
+	uint32_t ret;
+	struct nss_virt_if_handle *handle = NULL;
+	int32_t if_num_n2h, if_num_h2n;
+
+	if (unlikely(nss_ctx->state != NSS_CORE_STATE_INITIALIZED)) {
+		nss_warning("%px: Interface could not be created as core not ready\n", nss_ctx);
+		return NULL;
+	}
+
+	if_num_n2h = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_N2H);
+	if (if_num_n2h < 0) {
+		nss_warning("%px: failure allocating redir_n2h\n", nss_ctx);
+		return NULL;
+	}
+
+	if_num_h2n = nss_dynamic_interface_alloc_node(NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_H2N);
+	if (if_num_h2n < 0) {
+		nss_warning("%px: failure allocating redir_h2n\n", nss_ctx);
+		nss_dynamic_interface_dealloc_node(if_num_n2h, NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_N2H);
+		return NULL;
+	}
+
+	handle = nss_virt_if_handle_create_sync(nss_ctx, if_num_n2h, if_num_h2n, &ret);
+	if (!handle) {
+		nss_warning("%px: virt_if handle creation failed ret %d\n", nss_ctx, ret);
+		nss_dynamic_interface_dealloc_node(if_num_n2h, NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_N2H);
+		nss_dynamic_interface_dealloc_node(if_num_h2n, NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_H2N);
+		return NULL;
+	}
+
+	/*
+	 * Initializes the semaphore and also sets the msg handler for if_num.
+	 */
+	ret = nss_virt_if_register_handler_sync(nss_ctx, handle);
+	if (ret != NSS_VIRT_IF_SUCCESS) {
+		nss_warning("%px: Registration handler failed reason: %d\n", nss_ctx, ret);
+		goto error1;
+	}
+
+	nss_virt_if_msg_init(&nvim, handle->if_num_n2h, NSS_VIRT_IF_TX_CONFIG_MSG,
+				sizeof(struct nss_virt_if_config_msg), nss_virt_if_callback, handle);
+
+	nvcm = &nvim.msg.if_config;
+	nvcm->flags = 0;
+	nvcm->sibling = if_num_h2n;
+	nvcm->nexthop = nexthop_n2h;
+	memcpy(nvcm->mac_addr, netdev->dev_addr, ETH_ALEN);
+
+	ret = nss_virt_if_tx_msg_sync(handle, &nvim);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_virt_if_tx_msg_sync failed %u\n", nss_ctx, ret);
+		goto error2;
+	}
+
+	nvim.cm.interface = if_num_h2n;
+	nvcm->sibling = if_num_n2h;
+	nvcm->nexthop = nexthop_h2n;
+
+	ret = nss_virt_if_tx_msg_sync(handle, &nvim);
+	if (ret != NSS_TX_SUCCESS) {
+		nss_warning("%px: nss_virt_if_tx_msg_sync failed %u\n", nss_ctx, ret);
+		goto error2;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, handle->if_num_n2h, NULL, NULL, NULL, netdev, 0);
+	nss_core_register_subsys_dp(nss_ctx, handle->if_num_h2n, NULL, NULL, NULL, netdev, 0);
+
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num_n2h, NSS_VIRT_IF_DP_REDIR_N2H);
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num_h2n, NSS_VIRT_IF_DP_REDIR_H2N);
+
+	/*
+	 * Hold a reference to the net_device
+	 */
+	dev_hold(netdev);
+
+	/*
+	 * The context returned is the handle interface # which contains all the info related to
+	 * the interface if_num.
+	 */
+
+	return handle;
+
+error2:
+	nss_core_unregister_handler(nss_ctx, if_num_n2h);
+	nss_core_unregister_handler(nss_ctx, if_num_h2n);
+
+error1:
+	nss_virt_if_handle_destroy_sync(handle);
+	return NULL;
+}
+EXPORT_SYMBOL(nss_virt_if_create_sync_nexthop);
+
+/*
+ * nss_virt_if_create_sync()
+ *	Create redir_n2h and redir_h2n interfaces, synchronously and associate it with same netdev.
+ * It uses the default nexthop interfaces.
+ *
+ *
+ */
+struct nss_virt_if_handle *nss_virt_if_create_sync(struct net_device *netdev)
+{
+	/*
+	 * NSS_N2H_INTERFACE is the nexthop of the dynamic interface which is created for handling the
+	 * n2h traffic.
+	 * NSS_ETH_RX_INTERFACE is the nexthop of the dynamic interface which is created for handling the
+	 * h2n traffic.
+	 */
+	return nss_virt_if_create_sync_nexthop(netdev, NSS_N2H_INTERFACE, NSS_ETH_RX_INTERFACE);
+}
+EXPORT_SYMBOL(nss_virt_if_create_sync);
+
+/*
+ * nss_virt_if_destroy_sync()
+ *	Destroy the virt interface associated with the interface number, synchronously.
+ */
+nss_tx_status_t nss_virt_if_destroy_sync(struct nss_virt_if_handle *handle)
+{
+	nss_tx_status_t status;
+	struct net_device *dev;
+	int32_t if_num_n2h;
+	int32_t if_num_h2n;
+	struct nss_ctx_instance *nss_ctx;
+	uint32_t ret;
+
+	if (!handle) {
+		nss_warning("handle is NULL\n");
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	if_num_n2h = handle->if_num_n2h;
+	if_num_h2n = handle->if_num_h2n;
+	nss_ctx = handle->nss_ctx;
+
+	if (unlikely(nss_ctx->state != NSS_CORE_STATE_INITIALIZED)) {
+		nss_warning("%px: Interface could not be destroyed as core not ready\n", nss_ctx);
+		return NSS_TX_FAILURE_NOT_READY;
+	}
+
+	spin_lock_bh(&nss_top_main.lock);
+	if (!nss_ctx->subsys_dp_register[if_num_n2h].ndev || !nss_ctx->subsys_dp_register[if_num_h2n].ndev) {
+		spin_unlock_bh(&nss_top_main.lock);
+		nss_warning("%px: Unregister virt interface %d %d: no context\n", nss_ctx, if_num_n2h, if_num_h2n);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	dev = nss_ctx->subsys_dp_register[if_num_n2h].ndev;
+	nss_assert(dev == nss_ctx->subsys_dp_register[if_num_h2n].ndev);
+	nss_core_unregister_subsys_dp(nss_ctx, if_num_n2h);
+	nss_core_unregister_subsys_dp(nss_ctx, if_num_h2n);
+	spin_unlock_bh(&nss_top_main.lock);
+	dev_put(dev);
+
+	status = nss_virt_if_handle_destroy_sync(handle);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: handle destroy failed for if_num_n2h %d and if_num_h2n %d\n", nss_ctx, if_num_n2h, if_num_h2n);
+		return NSS_TX_FAILURE;
+	}
+
+	ret = nss_core_unregister_handler(nss_ctx, if_num_n2h);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to unregister handler for redir_n2h interface %d with NSS core\n", nss_ctx, if_num_n2h);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	ret = nss_core_unregister_handler(nss_ctx, if_num_h2n);
+	if (ret != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Not able to unregister handler for redir_h2n interface %d with NSS core\n", nss_ctx, if_num_h2n);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	return status;
+}
+EXPORT_SYMBOL(nss_virt_if_destroy_sync);
+
+/*
+ * nss_virt_if_tx_buf()
+ *	HLOS interface has received a packet which we redirect to the NSS, if appropriate to do so.
+ */
+nss_tx_status_t nss_virt_if_tx_buf(struct nss_virt_if_handle *handle,
+						struct sk_buff *skb)
+{
+	int32_t if_num = handle->if_num_h2n;
+	struct nss_ctx_instance *nss_ctx = handle->nss_ctx;
+	int cpu = 0;
+
+	if (unlikely(nss_ctl_redirect == 0)) {
+		return NSS_TX_FAILURE_NOT_ENABLED;
+	}
+
+	if (unlikely(skb->vlan_tci)) {
+		return NSS_TX_FAILURE_NOT_SUPPORTED;
+	}
+
+	if (!nss_virt_if_verify_if_num(if_num)) {
+		nss_warning("%px: bad interface number %d\n", nss_ctx, if_num);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	nss_trace("%px: Virtual Rx packet, if_num:%d, skb:%px", nss_ctx, if_num, skb);
+
+	/*
+	 * Sanity check the SKB to ensure that it's suitable for us
+	 */
+	if (unlikely(skb->len <= ETH_HLEN)) {
+		nss_warning("%px: Virtual Rx packet: %px too short", nss_ctx, skb);
+		return NSS_TX_FAILURE_TOO_SHORT;
+	}
+
+	/*
+	 * set skb queue mapping
+	 */
+	cpu = get_cpu();
+	put_cpu();
+	skb_set_queue_mapping(skb, cpu);
+
+	return nss_core_send_packet(nss_ctx, skb, if_num, H2N_BIT_FLAG_VIRTUAL_BUFFER |
+                                                        H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+EXPORT_SYMBOL(nss_virt_if_tx_buf);
+
+/*
+ * nss_virt_if_tx_msg()
+ */
+nss_tx_status_t nss_virt_if_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_virt_if_msg *nvim)
+{
+	struct nss_cmn_msg *ncm = &nvim->cm;
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!nss_virt_if_verify_if_num(ncm->interface)) {
+		nss_warning("%px: tx request for another interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type > NSS_VIRT_IF_MAX_MSG_TYPES) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, nvim, sizeof(*nvim), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_virt_if_tx_msg);
+
+/*
+ * nss_virt_if_xmit_callback_register()
+ *	Register virtual interface xmit callback.
+ */
+void nss_virt_if_xmit_callback_register(struct nss_virt_if_handle *handle,
+				nss_virt_if_xmit_callback_t cb)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_subsystem_dataplane_register *reg;
+
+	if (!handle) {
+		nss_warning("handle is NULL\n");
+		return;
+	}
+
+	nss_ctx = handle->nss_ctx;
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_virt_if_verify_if_num(handle->if_num_n2h)) {
+		nss_warning("if_num is invalid\n");
+		return;
+	}
+
+	reg = &nss_ctx->subsys_dp_register[handle->if_num_n2h];
+	reg->xmit_cb = cb;
+}
+EXPORT_SYMBOL(nss_virt_if_xmit_callback_register);
+
+/*
+ * nss_virt_if_xmit_callback_unregister()
+ *	Unregister virtual interface xmit callback.
+ */
+void nss_virt_if_xmit_callback_unregister(struct nss_virt_if_handle *handle)
+{
+	struct nss_ctx_instance *nss_ctx;
+	struct nss_subsystem_dataplane_register *reg;
+
+	if (!handle) {
+		nss_warning("handle is NULL\n");
+		return;
+	}
+
+	nss_ctx = handle->nss_ctx;
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_virt_if_verify_if_num(handle->if_num_n2h)) {
+		nss_warning("if_num is invalid\n");
+		return;
+	}
+
+	reg = &nss_ctx->subsys_dp_register[handle->if_num_n2h];
+	reg->xmit_cb = NULL;
+}
+EXPORT_SYMBOL(nss_virt_if_xmit_callback_unregister);
+
+/*
+ * nss_virt_if_register()
+ */
+void nss_virt_if_register(struct nss_virt_if_handle *handle,
+				nss_virt_if_data_callback_t data_callback,
+				struct net_device *netdev)
+{
+	struct nss_ctx_instance *nss_ctx;
+	int32_t if_num;
+	uint32_t status;
+
+	if (!handle) {
+		nss_warning("handle is NULL\n");
+		return;
+	}
+
+	nss_ctx = handle->nss_ctx;
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_virt_if_verify_if_num(handle->if_num_n2h)) {
+		nss_warning("if_num is invalid\n");
+		return;
+	}
+
+	if_num = handle->if_num_n2h;
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, data_callback, NULL, NULL, netdev, (uint32_t)netdev->features);
+	status = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to unregister event handler for interface(%u)", nss_ctx, if_num);
+		return;
+	}
+}
+EXPORT_SYMBOL(nss_virt_if_register);
+
+/*
+ * nss_virt_if_unregister()
+ */
+void nss_virt_if_unregister(struct nss_virt_if_handle *handle)
+{
+	struct nss_ctx_instance *nss_ctx;
+	int32_t if_num;
+	uint32_t status;
+
+	if (!handle) {
+		nss_warning("handle is NULL\n");
+		return;
+	}
+
+	nss_ctx = handle->nss_ctx;
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_virt_if_verify_if_num(handle->if_num_n2h)) {
+		nss_warning("if_num is invalid\n");
+		return;
+	}
+
+	if_num = handle->if_num_n2h;
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	status = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to unregister event handler for interface(%u)", nss_ctx, if_num);
+		return;
+	}
+}
+EXPORT_SYMBOL(nss_virt_if_unregister);
+
+/*
+ * nss_virt_if_get_interface_num()
+ *	Get interface number for a virtual interface
+ */
+int32_t nss_virt_if_get_interface_num(struct nss_virt_if_handle *handle)
+{
+	if (!handle) {
+		nss_warning("virt_if handle is NULL\n");
+		return -1;
+	}
+
+	/*
+	 * Return if_num_n2h whose datapath type is 0.
+	 */
+	return handle->if_num_n2h;
+}
+EXPORT_SYMBOL(nss_virt_if_get_interface_num);
diff --git a/qca-nss-drv/nss_virt_if_stats.c b/qca-nss-drv/nss_virt_if_stats.c
new file mode 100644
index 0000000..d43b72c
--- /dev/null
+++ b/qca-nss-drv/nss_virt_if_stats.c
@@ -0,0 +1,339 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_virt_if_stats.h"
+
+/*
+ * Data structure that holds the virtual interface context.
+ */
+extern struct nss_virt_if_handle *nss_virt_if_handle_t[];
+
+/*
+ * Spinlock to protect the global data structure virt_handle.
+ */
+extern spinlock_t nss_virt_if_lock;
+
+/*
+ * nss_virt_if_base_node_stats_str
+ *	virt_if base node stats strings
+ */
+static int8_t *nss_virt_if_base_node_stats_str[NSS_VIRT_IF_BASE_NODE_STATS_MAX] = {
+	"active_interfaces",
+	"ocm_alloc_failed",
+	"ddr_alloc_failed",
+};
+
+/*
+ * nss_virt_if_interface_stats_str
+ *	virt_if interface stats strings
+ */
+static int8_t *nss_virt_if_interface_stats_str[NSS_VIRT_IF_INTERFACE_STATS_MAX] = {
+	"rx_packets",
+	"rx_bytes",
+	"rx_dropped",
+	"tx_packets",
+	"tx_bytes",
+	"tx_enqueue_failed",
+	"shaper_enqueue_failed",
+	"ocm_alloc_failed",
+};
+
+/*
+ * nss_virt_if_base_node_stats_fill_row()
+ *	Fill one row of virt_if base node stats.
+ */
+static int32_t nss_virt_if_base_node_stats_fill_row(char *line, int len, int start, struct nss_virt_if_base_node_stats *stats)
+{
+	uint64_t tcnt = 0;
+	switch (start) {
+	case NSS_VIRT_IF_BASE_NODE_STATS_ACTIVE_INTERFACES:
+		tcnt = stats->active_interfaces;
+		break;
+
+	case NSS_VIRT_IF_BASE_NODE_STATS_OCM_ALLOC_FAILED:
+		tcnt = stats->ocm_alloc_failed;
+		break;
+
+	case NSS_VIRT_IF_BASE_NODE_STATS_DDR_ALLOC_FAILED:
+		tcnt = stats->ddr_alloc_failed;
+		break;
+
+	default:
+		return 0;
+	}
+
+	return scnprintf(line, len, "%s = %llu\n", nss_virt_if_base_node_stats_str[start], tcnt);
+}
+
+/*
+ * nss_virt_if_interface_stats_fill_row()
+ *	Fill one row of virt_if interface stats.
+ */
+static int32_t nss_virt_if_interface_stats_fill_row(char *line, int len, int start, struct nss_virt_if_interface_stats *stats)
+{
+	uint64_t tcnt = 0;
+	switch (start) {
+	case NSS_VIRT_IF_INTERFACE_STATS_RX_PACKETS:
+		tcnt = stats->node_stats.rx_packets;
+		break;
+
+	case NSS_VIRT_IF_INTERFACE_STATS_RX_BYTES:
+		tcnt = stats->node_stats.rx_bytes;
+		break;
+
+	case NSS_VIRT_IF_INTERFACE_STATS_RX_DROPPED:
+		tcnt = nss_cmn_rx_dropped_sum(&stats->node_stats);
+		break;
+
+	case NSS_VIRT_IF_INTERFACE_STATS_TX_PACKETS:
+		tcnt = stats->node_stats.tx_packets;
+		break;
+
+	case NSS_VIRT_IF_INTERFACE_STATS_TX_BYTES:
+		tcnt = stats->node_stats.tx_bytes;
+		break;
+
+	case NSS_VIRT_IF_INTERFACE_STATS_TX_ENQUEUE_FAILED:
+		tcnt = stats->tx_enqueue_failed;
+		break;
+
+	case NSS_VIRT_IF_INTERFACE_STATS_SHAPER_ENQUEUE_FAILED:
+		tcnt = stats->shaper_enqueue_failed;
+		break;
+
+	case NSS_VIRT_IF_INTERFACE_STATS_OCM_ALLOC_FAILED:
+		tcnt = stats->ocm_alloc_failed;
+		break;
+
+	default:
+		return 0;
+	}
+
+	return scnprintf(line, len, "%s = %llu\n", nss_virt_if_interface_stats_str[start], tcnt);
+}
+
+/*
+ * nss_virt_if_stats_get()
+ *	Get virt_if base node stats or interface stats by interface number.
+ */
+bool nss_virt_if_stats_get(struct nss_ctx_instance *nss_ctx, uint32_t if_num, void *stats, bool is_base)
+{
+	if (nss_virt_if_verify_if_num(if_num) == false) {
+		return false;
+	}
+
+	/*
+	 * Statistics for redir_h2n and redir_n2h are collected on redir_h2n in NSS.
+	 */
+	if (nss_dynamic_interface_get_type(nss_ctx, if_num) != NSS_DYNAMIC_INTERFACE_TYPE_GENERIC_REDIR_H2N)
+		return false;
+
+	if_num = if_num - NSS_DYNAMIC_IF_START;
+	spin_lock_bh(&nss_virt_if_lock);
+	if (!nss_virt_if_handle_t[if_num]) {
+		spin_unlock_bh(&nss_virt_if_lock);
+		return false;
+	}
+
+	/*
+	 * Check if it is base node statistics or interface statistics.
+	 */
+	if (is_base) {
+		memcpy((struct nss_virt_if_base_node_stats *)stats,
+			&nss_virt_if_handle_t[if_num]->stats.base_stats,
+			sizeof(struct nss_virt_if_base_node_stats));
+	} else {
+		memcpy((struct nss_virt_if_interface_stats *)stats,
+			&nss_virt_if_handle_t[if_num]->stats.if_stats,
+			sizeof(struct nss_virt_if_interface_stats));
+	}
+
+	spin_unlock_bh(&nss_virt_if_lock);
+	return true;
+}
+
+/*
+ * nss_virt_if_stats_read()
+ *	Read virt_if statistics
+ */
+static ssize_t nss_virt_if_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	struct nss_stats_data *data = fp->private_data;
+	struct nss_ctx_instance *nss_ctx = nss_virt_if_get_context();
+	int32_t if_num = NSS_DYNAMIC_IF_START;
+	int32_t max_if_num = if_num + NSS_MAX_DYNAMIC_INTERFACES;
+	size_t bytes = 0;
+	ssize_t bytes_read = 0;
+	char line[80];
+	int start, end;
+	int32_t if_num_valid = NSS_DYNAMIC_IF_START - 1;
+	struct nss_virt_if_base_node_stats base_node_stats_local;
+	struct nss_virt_if_interface_stats interface_stats_local;
+
+	if (data) {
+		if_num = data->if_num;
+	}
+
+	if (if_num > max_if_num) {
+		return 0;
+	}
+
+	/*
+	 * Interface statistics for all virtual interface pairs.
+	 */
+	for (; if_num < max_if_num; if_num++) {
+
+		if (!nss_virt_if_stats_get(nss_ctx, if_num, &interface_stats_local, false))
+			continue;
+
+		bytes = scnprintf(line, sizeof(line), "if_num %d stats start:\n\n", if_num);
+		if ((bytes_read + bytes) > sz)
+			break;
+
+		if (copy_to_user(ubuf + bytes_read, line, bytes) != 0)
+			return -EFAULT;
+
+		bytes_read += bytes;
+
+		start = NSS_VIRT_IF_INTERFACE_STATS_RX_PACKETS;
+		end = NSS_VIRT_IF_INTERFACE_STATS_MAX;
+		while (bytes_read < sz && start < end) {
+			bytes = nss_virt_if_interface_stats_fill_row(line, sizeof(line), start, &interface_stats_local);
+			if (!bytes)
+				break;
+
+			if ((bytes_read + bytes) > sz)
+				break;
+
+			if (copy_to_user(ubuf + bytes_read, line, bytes) != 0)
+				return -EFAULT;
+
+			bytes_read += bytes;
+			start++;
+		}
+
+		/*
+		 * Save one valid interface number for base node statistics.
+		 */
+		if_num_valid = if_num;
+
+		bytes = scnprintf(line, sizeof(line), "if_num %d stats end:\n\n", if_num);
+		if (bytes_read > (sz - bytes))
+			break;
+
+		if (copy_to_user(ubuf + bytes_read, line, bytes) != 0)
+			return -EFAULT;
+
+		bytes_read += bytes;
+	}
+
+	/*
+	 * Base node statistics.
+	 */
+	if (!nss_virt_if_stats_get(nss_ctx, if_num_valid, &base_node_stats_local, true))
+		goto done;
+
+	bytes = scnprintf(line, sizeof(line), "base node stats begin (shown on if_num %d):\n\n", if_num_valid);
+	if ((bytes_read + bytes) > sz)
+		goto done;
+
+	if (copy_to_user(ubuf + bytes_read, line, bytes) != 0)
+		return -EFAULT;
+
+	bytes_read += bytes;
+
+	start = NSS_VIRT_IF_BASE_NODE_STATS_ACTIVE_INTERFACES;
+	end = NSS_VIRT_IF_BASE_NODE_STATS_MAX;
+	while (bytes_read < sz && start < end) {
+		bytes = nss_virt_if_base_node_stats_fill_row(line, sizeof(line), start, &base_node_stats_local);
+		if (!bytes)
+			break;
+
+		if ((bytes_read + bytes) > sz)
+			break;
+
+		if (copy_to_user(ubuf + bytes_read, line, bytes) != 0)
+			return -EFAULT;
+
+		bytes_read += bytes;
+		start++;
+	}
+
+	bytes = scnprintf(line, sizeof(line), "base node stats end.\n\n");
+	if ((bytes_read + bytes) > sz)
+		goto done;
+
+	if (copy_to_user(ubuf + bytes_read, line, bytes) != 0)
+		return -EFAULT;
+
+	bytes_read += bytes;
+
+done:
+	if (bytes_read > 0) {
+		*ppos = bytes_read;
+	}
+
+	if (data) {
+		data->if_num = if_num;
+	}
+
+	return bytes_read;
+}
+
+/*
+ * nss_virt_if_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(virt_if)
+
+/*
+ * nss_virt_if_stats_dentry_create()
+ *	Create virt_if statistics debug entry.
+ */
+void nss_virt_if_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("virt_if", &nss_virt_if_stats_ops);
+}
+
+/*
+ * nss_virt_if_stats_sync()
+ *	Sync stats from the NSS FW
+ */
+void nss_virt_if_stats_sync(struct nss_virt_if_handle *handle,
+				struct nss_virt_if_stats *nwis)
+{
+	struct nss_virt_if_stats *stats = &handle->stats;
+	int i;
+
+	spin_lock_bh(&nss_virt_if_lock);
+	stats->if_stats.node_stats.rx_packets += nwis->if_stats.node_stats.rx_packets;
+	stats->if_stats.node_stats.rx_bytes += nwis->if_stats.node_stats.rx_bytes;
+	stats->if_stats.node_stats.tx_packets += nwis->if_stats.node_stats.tx_packets;
+	stats->if_stats.node_stats.tx_bytes += nwis->if_stats.node_stats.tx_bytes;
+
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		stats->if_stats.node_stats.rx_dropped[i] += nwis->if_stats.node_stats.rx_dropped[i];
+	}
+
+	stats->if_stats.tx_enqueue_failed += nwis->if_stats.tx_enqueue_failed;
+	stats->if_stats.shaper_enqueue_failed += nwis->if_stats.shaper_enqueue_failed;
+	stats->if_stats.ocm_alloc_failed += nwis->if_stats.ocm_alloc_failed;
+
+	stats->base_stats.active_interfaces = nwis->base_stats.active_interfaces;
+	stats->base_stats.ocm_alloc_failed = nwis->base_stats.ocm_alloc_failed;
+	stats->base_stats.ddr_alloc_failed = nwis->base_stats.ddr_alloc_failed;
+	spin_unlock_bh(&nss_virt_if_lock);
+}
diff --git a/qca-nss-drv/nss_virt_if_stats.h b/qca-nss-drv/nss_virt_if_stats.h
new file mode 100644
index 0000000..0c26fac
--- /dev/null
+++ b/qca-nss-drv/nss_virt_if_stats.h
@@ -0,0 +1,51 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2017,2019 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_VIRT_IF_STATS_H
+#define __NSS_VIRT_IF_STATS_H
+
+/*
+ * virt_if base node statistics types.
+ */
+enum nss_virt_if_base_node_stats_types {
+	NSS_VIRT_IF_BASE_NODE_STATS_ACTIVE_INTERFACES,		/* Number of active virtual interfaces */
+	NSS_VIRT_IF_BASE_NODE_STATS_OCM_ALLOC_FAILED,		/* Number of interface allocation failure on OCM */
+	NSS_VIRT_IF_BASE_NODE_STATS_DDR_ALLOC_FAILED,		/* Number of interface allocation failure on DDR */
+	NSS_VIRT_IF_BASE_NODE_STATS_MAX,
+};
+
+/*
+ * virt_if interface statistics types.
+ */
+enum nss_virt_if_interface_stats_types {
+	NSS_VIRT_IF_INTERFACE_STATS_RX_PACKETS,			/* Rx packets */
+	NSS_VIRT_IF_INTERFACE_STATS_RX_BYTES,			/* Rx bytes */
+	NSS_VIRT_IF_INTERFACE_STATS_RX_DROPPED,			/* Rx drop count */
+	NSS_VIRT_IF_INTERFACE_STATS_TX_PACKETS,			/* Tx packets */
+	NSS_VIRT_IF_INTERFACE_STATS_TX_BYTES,			/* Tx bytes */
+	NSS_VIRT_IF_INTERFACE_STATS_TX_ENQUEUE_FAILED,		/* Number of Tx enqueue failure */
+	NSS_VIRT_IF_INTERFACE_STATS_SHAPER_ENQUEUE_FAILED,	/* Number of shaper enqueue failure */
+	NSS_VIRT_IF_INTERFACE_STATS_OCM_ALLOC_FAILED,		/* Number of interface allocation failure on OCM */
+	NSS_VIRT_IF_INTERFACE_STATS_MAX,
+};
+
+/*
+ * Virtual interface statistics APIs
+ */
+extern void nss_virt_if_stats_sync(struct nss_virt_if_handle *handle, struct nss_virt_if_stats *nwis);
+extern void nss_virt_if_stats_dentry_create(void);
+
+#endif /* __NSS_VIRT_IF_STATS_H */
diff --git a/qca-nss-drv/nss_vlan.c b/qca-nss-drv/nss_vlan.c
new file mode 100644
index 0000000..23b5c0b
--- /dev/null
+++ b/qca-nss-drv/nss_vlan.c
@@ -0,0 +1,411 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_vlan_log.h"
+
+#define NSS_VLAN_TX_TIMEOUT 1000 /* 1 Second */
+
+/*
+ * Private data structure
+ */
+static struct nss_vlan_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+	void *cb;
+	void *app_data;
+} vlan_pvt;
+
+/*
+ * nss_vlan_get_context()
+ */
+struct nss_ctx_instance *nss_vlan_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.vlan_handler_id];
+}
+EXPORT_SYMBOL(nss_vlan_get_context);
+
+/*
+ * nss_vlan_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static bool nss_vlan_verify_if_num(uint32_t if_num)
+{
+	if (!nss_is_dynamic_interface(if_num)) {
+		return false;
+	}
+
+	if (nss_dynamic_interface_get_type(nss_vlan_get_context(), if_num) != NSS_DYNAMIC_INTERFACE_TYPE_VLAN) {
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * nss_vlan_handler()
+ *	Handle NSS -> HLOS messages for vlan
+ */
+static void nss_vlan_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, void *app_data)
+{
+	struct nss_vlan_msg *nvm = (struct nss_vlan_msg *)ncm;
+	nss_vlan_msg_callback_t cb;
+
+	nss_assert(nss_vlan_verify_if_num(ncm->interface));
+
+	/*
+	 * Trace messages.
+	 */
+	nss_vlan_log_rx_msg(nvm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_VLAN_MSG_TYPE_MAX) {
+		nss_warning("%px: received invalid message %d for vlan interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_vlan_msg)) {
+		nss_warning("%px: length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, vlan sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->vlan_callback;
+		ncm->app_data = (nss_ptr_t)app_data;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	/*
+	 * callback
+	 */
+	cb = (nss_vlan_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, nvm);
+}
+
+/*
+ * nss_vlan_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_vlan_callback(void *app_data, struct nss_vlan_msg *nvm)
+{
+	nss_vlan_msg_callback_t callback = (nss_vlan_msg_callback_t)vlan_pvt.cb;
+	void *data = vlan_pvt.app_data;
+
+	vlan_pvt.response = NSS_TX_SUCCESS;
+	vlan_pvt.cb = NULL;
+	vlan_pvt.app_data = NULL;
+
+	if (nvm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("vlan error response %d\n", nvm->cm.response);
+		vlan_pvt.response = nvm->cm.response;
+	}
+
+	if (callback) {
+		callback(data, nvm);
+	}
+	complete(&vlan_pvt.complete);
+}
+
+/*
+ * nss_vlan_tx_msg()
+ *	Transmit a vlan message to NSSFW
+ */
+nss_tx_status_t nss_vlan_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_vlan_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace messages.
+	 */
+	nss_vlan_log_tx_msg(msg);
+
+	/*
+	 * Sanity check the message
+	 */
+	if (!nss_vlan_verify_if_num(ncm->interface)) {
+		nss_warning("%px: tx request for interface that is not a vlan: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_VLAN_MSG_TYPE_MAX) {
+		nss_warning("%px: message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_vlan_tx_msg);
+
+/*
+ * nss_vlan_tx_msg_sync()
+ *	Transmit a vlan message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_vlan_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_vlan_msg *nvm)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&vlan_pvt.sem);
+	vlan_pvt.cb = (void *)nvm->cm.cb;
+	vlan_pvt.app_data = (void *)nvm->cm.app_data;
+
+	nvm->cm.cb = (nss_ptr_t)nss_vlan_callback;
+	nvm->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_vlan_tx_msg(nss_ctx, nvm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: vlan_tx_msg failed\n", nss_ctx);
+		up(&vlan_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&vlan_pvt.complete, msecs_to_jiffies(NSS_VLAN_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: vlan msg tx failed due to timeout\n", nss_ctx);
+		vlan_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = vlan_pvt.response;
+	up(&vlan_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_vlan_tx_msg_sync);
+
+/*
+ * nss_vlan_msg_init()
+ *	Initialize nss_vlan_msg.
+ */
+void nss_vlan_msg_init(struct nss_vlan_msg *ncm, uint16_t if_num, uint32_t type, uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+EXPORT_SYMBOL(nss_vlan_msg_init);
+
+/*
+ * nss_vlan_tx_change_mtu_msg
+ *	API to send change mtu message to NSS FW
+ */
+nss_tx_status_t nss_vlan_tx_set_mtu_msg(uint32_t vlan_if_num, uint32_t mtu)
+{
+	struct nss_ctx_instance *nss_ctx = nss_vlan_get_context();
+	struct nss_vlan_msg nvm;
+	struct nss_if_mtu_change *nimc;
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	if (nss_vlan_verify_if_num(vlan_if_num) == false) {
+		nss_warning("%px: received invalid interface %d", nss_ctx, vlan_if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	nss_vlan_msg_init(&nvm, vlan_if_num, NSS_IF_MTU_CHANGE,
+			sizeof(struct nss_if_mtu_change), NULL, NULL);
+
+	nimc = &nvm.msg.if_msg.mtu_change;
+	nimc->min_buf_size = (uint16_t)mtu;
+
+	return nss_vlan_tx_msg_sync(nss_ctx, &nvm);
+}
+EXPORT_SYMBOL(nss_vlan_tx_set_mtu_msg);
+
+/*
+ * nss_vlan_tx_set_mac_addr_msg
+ *	API to send change mac addr message to NSS FW
+ */
+nss_tx_status_t nss_vlan_tx_set_mac_addr_msg(uint32_t vlan_if_num, uint8_t *addr)
+{
+	struct nss_ctx_instance *nss_ctx = nss_vlan_get_context();
+	struct nss_vlan_msg nvm;
+	struct nss_if_mac_address_set *nmas;
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	if (nss_vlan_verify_if_num(vlan_if_num) == false) {
+		nss_warning("%px: received invalid interface %d", nss_ctx, vlan_if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	nss_vlan_msg_init(&nvm, vlan_if_num, NSS_IF_MAC_ADDR_SET,
+			sizeof(struct nss_if_mac_address_set), NULL, NULL);
+
+	nmas = &nvm.msg.if_msg.mac_address_set;
+	memcpy(nmas->mac_addr, addr, ETH_ALEN);
+	return nss_vlan_tx_msg_sync(nss_ctx, &nvm);
+}
+EXPORT_SYMBOL(nss_vlan_tx_set_mac_addr_msg);
+
+/*
+ * nss_vlan_tx_vsi_attach_msg
+ *	API to send VSI attach message to NSS FW
+ */
+nss_tx_status_t nss_vlan_tx_vsi_attach_msg(uint32_t vlan_if_num, uint32_t vsi)
+{
+	struct nss_ctx_instance *nss_ctx = nss_vlan_get_context();
+	struct nss_vlan_msg nvm;
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	if (nss_vlan_verify_if_num(vlan_if_num) == false) {
+		nss_warning("%px: received invalid interface %d\n", nss_ctx, vlan_if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	nvm.msg.if_msg.vsi_assign.vsi = vsi;
+	nss_vlan_msg_init(&nvm, vlan_if_num, NSS_IF_VSI_ASSIGN,
+				sizeof(struct nss_if_vsi_assign), NULL, NULL);
+
+	return nss_vlan_tx_msg_sync(nss_ctx, &nvm);
+}
+EXPORT_SYMBOL(nss_vlan_tx_vsi_attach_msg);
+
+/*
+ * nss_vlan_tx_vsi_detach_msg
+ *	API to send VSI detach message to NSS FW
+ */
+nss_tx_status_t nss_vlan_tx_vsi_detach_msg(uint32_t vlan_if_num, uint32_t vsi)
+{
+	struct nss_ctx_instance *nss_ctx = nss_vlan_get_context();
+	struct nss_vlan_msg nvm;
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	if (nss_vlan_verify_if_num(vlan_if_num) == false) {
+		nss_warning("%px: received invalid interface %d\n", nss_ctx, vlan_if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	nvm.msg.if_msg.vsi_unassign.vsi = vsi;
+	nss_vlan_msg_init(&nvm, vlan_if_num, NSS_IF_VSI_UNASSIGN,
+				sizeof(struct nss_if_vsi_unassign), NULL, NULL);
+
+	return nss_vlan_tx_msg_sync(nss_ctx, &nvm);
+}
+EXPORT_SYMBOL(nss_vlan_tx_vsi_detach_msg);
+
+/*
+ * nss_vlan_tx_add_tag_msg
+ *	API to send vlan add tag message to NSS FW
+ */
+nss_tx_status_t nss_vlan_tx_add_tag_msg(uint32_t vlan_if_num, uint32_t vlan_tag, uint32_t next_hop, uint32_t physical_dev)
+{
+	struct nss_ctx_instance *nss_ctx = nss_vlan_get_context();
+	struct nss_vlan_msg nvm;
+
+	if (!nss_ctx) {
+		nss_warning("Can't get nss context\n");
+		return NSS_TX_FAILURE;
+	}
+
+	if (nss_vlan_verify_if_num(vlan_if_num) == false) {
+		nss_warning("%px: received invalid interface %d\n", nss_ctx, vlan_if_num);
+		return NSS_TX_FAILURE;
+	}
+
+	nvm.msg.add_tag.next_hop = next_hop;
+	nvm.msg.add_tag.if_num = physical_dev;
+	nvm.msg.add_tag.vlan_tag = vlan_tag;
+	nss_vlan_msg_init(&nvm, vlan_if_num, NSS_VLAN_MSG_ADD_TAG,
+				sizeof(struct nss_vlan_msg_add_tag), NULL, NULL);
+
+	return nss_vlan_tx_msg_sync(nss_ctx, &nvm);
+}
+EXPORT_SYMBOL(nss_vlan_tx_add_tag_msg);
+
+/**
+ * @brief Register to send/receive vlan messages to NSS
+ *
+ * @param if_num NSS interface number
+ * @param vlan_data_callback Callback for vlan data
+ * @param netdev netdevice associated with the vlan interface
+ * @param features denotes the skb types supported by this interface
+ *
+ * @return nss_ctx_instance* NSS context
+ */
+struct nss_ctx_instance *nss_register_vlan_if(uint32_t if_num, nss_vlan_callback_t vlan_data_callback,
+					      struct net_device *netdev, uint32_t features, void *app_ctx)
+{
+	struct nss_ctx_instance *nss_ctx = nss_vlan_get_context();
+
+	nss_assert(nss_vlan_verify_if_num(if_num));
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, vlan_data_callback, NULL, app_ctx, netdev, features);
+
+	nss_core_register_handler(nss_ctx, if_num, nss_vlan_handler, app_ctx);
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_register_vlan_if);
+
+/*
+ * nss_unregister_vlan_if()
+ */
+void nss_unregister_vlan_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_vlan_get_context();
+
+	nss_assert(nss_vlan_verify_if_num(if_num));
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_unregister_vlan_if);
+
+/*
+ * nss_vlan_register_handler()
+ *   debugfs stats msg handler received on static vlan interface
+ */
+void nss_vlan_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_vlan_get_context();
+
+	nss_info("nss_vlan_register_handler\n");
+	nss_core_register_handler(nss_ctx, NSS_VLAN_INTERFACE, nss_vlan_handler, NULL);
+
+	sema_init(&vlan_pvt.sem, 1);
+	init_completion(&vlan_pvt.complete);
+}
+EXPORT_SYMBOL(nss_vlan_register_handler);
diff --git a/qca-nss-drv/nss_vlan_log.c b/qca-nss-drv/nss_vlan_log.c
new file mode 100644
index 0000000..b9e946a
--- /dev/null
+++ b/qca-nss-drv/nss_vlan_log.c
@@ -0,0 +1,120 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_vlan_log.c
+ *	NSS VLAN logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_vlan_log_message_types_str
+ *	VLAN message strings
+ */
+static int8_t *nss_vlan_log_message_types_str[NSS_VLAN_MSG_TYPE_MAX] __maybe_unused = {
+	"VLAN ADD TAG",
+};
+
+/*
+ * nss_vlan_log_error_response_types_str
+ *	Strings for error types for VLAN messages
+ */
+static int8_t *nss_vlan_log_error_response_types_str[NSS_VLAN_ERROR_TYPE_MAX] __maybe_unused = {
+	"VLAN Unknown Message",
+};
+
+/*
+ * nss_vlan_log_add_tag_msg()
+ *	Log NSS VLAN Add Tag message.
+ */
+static void nss_vlan_log_add_tag_msg(struct nss_vlan_msg *nvm)
+{
+	struct nss_vlan_msg_add_tag *nvtm __maybe_unused = &nvm->msg.add_tag;
+	nss_trace("%px: NSS VLAN Add Tag Message:\n"
+		"VLAN Tag: %d\n"
+		"VLAN Next Hop: %d\n"
+		"VLAN Interface Number: %d\n",
+		nvtm, nvtm->vlan_tag,
+		nvtm->next_hop, nvtm->if_num);
+}
+
+/*
+ * nss_vlan_log_verbose()
+ *	Log message contents.
+ */
+static void nss_vlan_log_verbose(struct nss_vlan_msg *nvm)
+{
+	switch (nvm->cm.type) {
+	case NSS_VLAN_MSG_ADD_TAG:
+		nss_vlan_log_add_tag_msg(nvm);
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", nvm);
+		break;
+	}
+}
+
+/*
+ * nss_vlan_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_vlan_log_tx_msg(struct nss_vlan_msg *nvm)
+{
+	if (nvm->cm.type >= NSS_VLAN_MSG_TYPE_MAX) {
+		nss_warning("%px: Invalid message type\n", nvm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nvm, nvm->cm.type, nss_vlan_log_message_types_str[nvm->cm.type]);
+	nss_vlan_log_verbose(nvm);
+}
+
+/*
+ * nss_vlan_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_vlan_log_rx_msg(struct nss_vlan_msg *nvm)
+{
+	if (nvm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", nvm);
+		return;
+	}
+
+	if (nvm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nvm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nvm, nvm->cm.type,
+			nss_vlan_log_message_types_str[nvm->cm.type],
+			nvm->cm.response, nss_cmn_response_str[nvm->cm.response]);
+		goto verbose;
+	}
+
+	if (nvm->cm.error >= NSS_VLAN_ERROR_TYPE_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			nvm, nvm->cm.type, nss_vlan_log_message_types_str[nvm->cm.type],
+			nvm->cm.response, nss_cmn_response_str[nvm->cm.response],
+			nvm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		nvm, nvm->cm.type, nss_vlan_log_message_types_str[nvm->cm.type],
+		nvm->cm.response, nss_cmn_response_str[nvm->cm.response],
+		nvm->cm.error, nss_vlan_log_error_response_types_str[nvm->cm.error]);
+
+verbose:
+	nss_vlan_log_verbose(nvm);
+}
diff --git a/qca-nss-drv/nss_vlan_log.h b/qca-nss-drv/nss_vlan_log.h
new file mode 100644
index 0000000..21b365d
--- /dev/null
+++ b/qca-nss-drv/nss_vlan_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_VLAN_LOG_H__
+#define __NSS_VLAN_LOG_H__
+
+/*
+ * nss_vlan_log.h
+ *	NSS VLAN Log Header File
+ */
+
+/*
+ * nss_vlan_log_tx_msg
+ *	Logs a vlan message that is sent to the NSS firmware.
+ */
+void nss_vlan_log_tx_msg(struct nss_vlan_msg *ncm);
+
+/*
+ * nss_vlan_log_rx_msg
+ *	Logs a vlan message that is received from the NSS firmware.
+ */
+void nss_vlan_log_rx_msg(struct nss_vlan_msg *ncm);
+
+#endif /* __NSS_VLAN_LOG_H__ */
diff --git a/qca-nss-drv/nss_vxlan.c b/qca-nss-drv/nss_vxlan.c
new file mode 100644
index 0000000..0381491
--- /dev/null
+++ b/qca-nss-drv/nss_vxlan.c
@@ -0,0 +1,327 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_vxlan.c
+ *	NSS VxLAN driver interface APIs
+ */
+#include "nss_core.h"
+#include "nss_vxlan.h"
+#include "nss_cmn.h"
+#include "nss_tx_rx_common.h"
+#include "nss_vxlan_log.h"
+#include "nss_vxlan_stats.h"
+
+#define NSS_VXLAN_TX_TIMEOUT 3000
+
+/*
+ * Private data structure
+ */
+static struct {
+	struct semaphore sem;		/* Semaphore structure. */
+	struct completion complete;	/* Completion structure. */
+	int response;			/* Response from FW. */
+	void *cb;			/* Original cb for msgs. */
+	void *app_data;			/* Original app_data for msgs. */
+} nss_vxlan_pvt;
+
+/*
+ * nss_vxlan_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static bool nss_vxlan_verify_if_num(uint32_t if_num)
+{
+	uint32_t type;
+
+	if (if_num == NSS_VXLAN_INTERFACE) {
+		return true;
+	}
+
+	type = nss_dynamic_interface_get_type(nss_vxlan_get_ctx(), if_num);
+
+	return ((type == NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_INNER) ||
+			(type == NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_OUTER));
+}
+
+/*
+ * nss_vxlan_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_vxlan_callback(void *app_data, struct nss_cmn_msg *msg)
+{
+	nss_vxlan_msg_callback_t callback = (nss_vxlan_msg_callback_t)nss_vxlan_pvt.cb;
+	void *data = nss_vxlan_pvt.app_data;
+
+	nss_vxlan_pvt.response = NSS_TX_SUCCESS;
+	nss_vxlan_pvt.cb = NULL;
+	nss_vxlan_pvt.app_data = NULL;
+
+	if (msg->response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("Vxlan Error response %d\n", msg->response);
+		nss_vxlan_pvt.response = NSS_TX_FAILURE;
+	}
+
+	if (callback) {
+		callback(data, msg);
+	}
+	complete(&nss_vxlan_pvt.complete);
+}
+
+/*
+ * nss_vxlan_handler()
+ *	Handle NSS -> HLOS messages for vxlan.
+ */
+static void nss_vxlan_msg_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_vxlan_msg *nvm = (struct nss_vxlan_msg *)ncm;
+	nss_vxlan_msg_callback_t cb;
+
+	BUG_ON(!nss_vxlan_verify_if_num(ncm->interface));
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_VXLAN_MSG_TYPE_MAX) {
+		nss_warning("%px: received invalid message %d for vxlan interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_vxlan_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Log messages.
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+	nss_vxlan_log_rx_msg(nvm);
+
+	switch (nvm->cm.type) {
+	case NSS_VXLAN_MSG_TYPE_STATS_SYNC:
+		/*
+		 * Update common node statistics
+		 */
+		nss_vxlan_stats_sync(nss_ctx, nvm);
+	}
+
+	/*
+	 * Update the callback for NOTIFY messages
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+	}
+
+	cb = (nss_vxlan_msg_callback_t)ncm->cb;
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!cb) {
+		nss_trace("%px: cb is null for interface %d\n", nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb((void *)nss_ctx->subsys_dp_register[ncm->interface].ndev, ncm);
+}
+
+/*
+ * nss_vxlan_tx_msg()
+ *	Transmit a vxlan message to NSS FW. Don't call this from softirq/interrupts.
+ */
+nss_tx_status_t nss_vxlan_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_vxlan_msg *nvm)
+{
+	struct nss_cmn_msg *ncm = &nvm->cm;
+
+	if (!nss_vxlan_verify_if_num(ncm->interface)) {
+		nss_warning("%px: wrong interface number %u\n", nss_ctx, nvm->cm.interface);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	if (ncm->type >= NSS_VXLAN_MSG_TYPE_MAX) {
+		nss_warning("%px: wrong message type %u\n", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE_BAD_PARAM;
+	}
+
+	/*
+	 * Trace messages.
+	 */
+	nss_vxlan_log_tx_msg(nvm);
+
+	return nss_core_send_cmd(nss_ctx, nvm, sizeof(*nvm), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_vxlan_tx_msg);
+
+/*
+ * nss_vxlan_tx_msg_sync()
+ *	Transmit a vxlan message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_vxlan_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_vxlan_msg *nvm)
+{
+	nss_tx_status_t status;
+	int ret;
+
+	down(&nss_vxlan_pvt.sem);
+	nss_vxlan_pvt.cb = (void *)nvm->cm.cb;
+	nss_vxlan_pvt.app_data = (void *)nvm->cm.app_data;
+
+	nvm->cm.cb = (nss_ptr_t)nss_vxlan_callback;
+	nvm->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_vxlan_tx_msg(nss_ctx, nvm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: vxlan_tx_msg failed\n", nss_ctx);
+		up(&nss_vxlan_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&nss_vxlan_pvt.complete, msecs_to_jiffies(NSS_VXLAN_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: vxlan tx sync failed due to timeout\n", nss_ctx);
+		nss_vxlan_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = nss_vxlan_pvt.response;
+	up(&nss_vxlan_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_vxlan_tx_msg_sync);
+
+/*
+ * nss_vxlan_msg_init()
+ *	Initialize VxLAN message.
+ */
+void nss_vxlan_msg_init(struct nss_vxlan_msg *nvm, uint16_t if_num, uint32_t type, uint32_t len,
+				nss_vxlan_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&nvm->cm, if_num, type, len, (void*)cb, app_data);
+}
+EXPORT_SYMBOL(nss_vxlan_msg_init);
+
+/*
+ * nss_vxlan_unregister_if()
+ *	Unregister a data packet notifier with NSS FW.
+ */
+bool nss_vxlan_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx;
+
+	nss_ctx = nss_vxlan_get_ctx();
+	if (!nss_vxlan_verify_if_num(if_num)) {
+		nss_warning("%px: data unregister received for invalid interface %d", nss_ctx, if_num);
+		return false;
+	}
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+	nss_core_unregister_msg_handler(nss_ctx, if_num);
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+	return true;
+}
+EXPORT_SYMBOL(nss_vxlan_unregister_if);
+
+/*
+ * nss_vxlan_register_if()
+ *	Registers a data packet notifier with NSS FW.
+ */
+struct nss_ctx_instance *nss_vxlan_register_if(uint32_t if_num,
+						uint32_t type,
+						nss_vxlan_buf_callback_t data_cb,
+						nss_vxlan_msg_callback_t notify_cb,
+						struct net_device *netdev,
+						uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx;
+	int core_status;
+
+	nss_ctx = nss_vxlan_get_ctx();
+	if (!nss_vxlan_verify_if_num(if_num)) {
+		nss_warning("%px: data register received for invalid interface %d", nss_ctx, if_num);
+		return NULL;
+	}
+
+	core_status = nss_core_register_handler(nss_ctx, if_num, nss_vxlan_msg_handler, NULL);
+	if (core_status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: nss core register handler failed for if_num:%d with error :%d", nss_ctx, if_num, core_status);
+		return NULL;
+	}
+
+	core_status = nss_core_register_msg_handler(nss_ctx, if_num, notify_cb);
+	if (core_status != NSS_CORE_STATUS_SUCCESS) {
+		nss_core_unregister_handler(nss_ctx, if_num);
+		nss_warning("%px: nss core register handler failed for if_num:%d with error :%d", nss_ctx, if_num, core_status);
+		return NULL;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, data_cb, NULL, NULL, netdev, features);
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num, type);
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_vxlan_register_if);
+
+/*
+ * nss_vxlan_ifnum_with_core_id()
+ *	Append core id to vxlan interface num.
+ */
+int nss_vxlan_ifnum_with_core_id(int if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_vxlan_get_ctx();
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (!nss_vxlan_verify_if_num(if_num)) {
+		nss_warning("%px: Invalid if_num: %d, must be a dynamic interface\n", nss_ctx, if_num);
+		return 0;
+	}
+	return NSS_INTERFACE_NUM_APPEND_COREID(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_vxlan_ifnum_with_core_id);
+
+/*
+ * nss_vxlan_get_ctx()
+ *	Return a VxLAN NSS context.
+ */
+struct nss_ctx_instance *nss_vxlan_get_ctx()
+{
+	struct nss_ctx_instance *nss_ctx;
+
+	nss_ctx = &nss_top_main.nss[nss_top_main.vxlan_handler_id];
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_vxlan_get_ctx);
+
+/*
+ * nss_vxlan_init()
+ *	Initializes Vxlan. Gets called from nss_init.c.
+ */
+void nss_vxlan_init()
+{
+	uint32_t core_status;
+	struct nss_ctx_instance *nss_ctx = nss_vxlan_get_ctx();
+	if (!nss_ctx) {
+		nss_warning("%px: VxLAN is not registered", nss_ctx);
+		return;
+	}
+
+	nss_vxlan_stats_dentry_create();
+	sema_init(&nss_vxlan_pvt.sem, 1);
+	init_completion(&nss_vxlan_pvt.complete);
+	core_status = nss_core_register_handler(nss_ctx, NSS_VXLAN_INTERFACE, nss_vxlan_msg_handler, NULL);
+
+	if (core_status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: nss core register handler failed for if_num:%d with error :%d", nss_ctx, NSS_VXLAN_INTERFACE, core_status);
+	}
+
+}
diff --git a/qca-nss-drv/nss_vxlan_log.c b/qca-nss-drv/nss_vxlan_log.c
new file mode 100644
index 0000000..7bbfc5e
--- /dev/null
+++ b/qca-nss-drv/nss_vxlan_log.c
@@ -0,0 +1,257 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_vxlan_log.c
+ *	NSS VXLAN logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_vxlan_log_message_types_str
+ *	VXLAN message strings
+ */
+static int8_t *nss_vxlan_log_message_types_str[NSS_VXLAN_MSG_TYPE_MAX] __maybe_unused = {
+	"VxLAN Sync Stats",
+	"VxLAN Tunnel Configure Rule",
+	"VxLAN Tunnel Unconfigure Rule",
+	"VxLAN Enable Tunnel",
+	"VxLAN Disable Tunnel",
+	"VxLAN Add MAC rule",
+	"VxLAN Delete MAC rule",
+	"VxLAN MAC DB Stats"
+};
+
+/*
+ * nss_vxlan_log_error_response_types_str
+ *	Strings for error types for VXLAN messages
+ */
+static int8_t *nss_vxlan_log_error_response_types_str[NSS_VXLAN_ERROR_TYPE_MAX] __maybe_unused = {
+	"VxLAN Unknown Error",
+	"VXLAN Decap Register fail",
+	"VXLAN Dest IP mismatch",
+	"VXLAN Invalid VNI",
+	"VXLAN Invalid L3 Proto",
+	"VXLAN Invalid UDP Proto",
+	"VXLAN Invalid Src Port",
+	"VXLAN MAC Bad entry",
+	"VXLAN MAC Entry exists",
+	"VXLAN MAC Entry does not exist",
+	"VXLAN MAC Entry unhashed",
+	"VXLAN MAC Entry alloc failed",
+	"VXLAN MAC Entry delete failed",
+	"VXLAN MAC Table full",
+	"VXLAN Sibling Node does not exist",
+	"VXLAN Tunnel Configured",
+	"VXLAN Tunnel Unconfigured",
+	"VXLAN Tunnel addition failed",
+	"VXLAN Tunnel Disabled",
+	"VXLAN Tunnel Enabled",
+	"VXLAN Tunnel Entry exists"
+};
+
+/*
+ * nss_vxlan_log_rule_msg()
+ *	Log NSS VXLAN rule message.
+ */
+static void nss_vxlan_log_rule_msg(struct nss_vxlan_rule_msg *nvrm)
+{
+	nss_trace("%px: NSS VXLAN Rule message \n"
+		"VxLAN Tunnel Flags: %x\n"
+		"VNET ID: %u\n"
+		"Flowlabel: %u\n"
+		"TOS: %u\n"
+		"TTL: %u\n"
+		"source port min: %u max: %u"
+		"destination port: %u",
+		nvrm,
+		nvrm->tunnel_flags,
+		nvrm->vni,
+		nvrm->flow_label,
+		nvrm->tos,
+		nvrm->ttl,
+		nvrm->src_port_min,
+		nvrm->src_port_max,
+		nvrm->dest_port);
+}
+
+/*
+ * nss_vxlan_mac_rule_msg()
+ *	Log NSS Vxlan MAC rule message.
+ */
+static void nss_vxlan_log_mac_msg(struct nss_vxlan_mac_msg *nvmm)
+{
+	nss_trace("%px: NSS VXLAN MAC message \n"
+		"Encap Rule Src IP: %px\n"
+		"Encap Rule Dst Ip: %px\n"
+		"Vxlan VNet ID: %u\n"
+		"Vxlan Mac Addr: %pM",
+		nvmm,
+		&nvmm->encap.src_ip,
+		&nvmm->encap.dest_ip,
+		nvmm->vni,
+		nvmm->mac_addr);
+}
+
+/*
+ * nss_vxlan_log_rule_create_msg()
+ *	Log NSS Vxlan rule create message.
+ */
+static void nss_vxlan_log_rule_create_msg(struct nss_vxlan_msg *nvm)
+{
+	struct nss_vxlan_rule_msg *nvrm __maybe_unused = &nvm->msg.vxlan_create;
+	nss_vxlan_log_rule_msg(nvrm);
+}
+
+/*
+ * nss_vxlan_log_rule_destroy_msg()
+ *	Log NSS Vxlan rule destroy message.
+ */
+static void nss_vxlan_log_rule_destroy_msg(struct nss_vxlan_msg *nvm)
+{
+	struct nss_vxlan_rule_msg *nvrm __maybe_unused = &nvm->msg.vxlan_destroy;
+	nss_vxlan_log_rule_msg(nvrm);
+}
+
+/*
+ * nss_vxlan_log_enable_msg()
+ *	Log NSS Vxlan rule enable message.
+ */
+static void nss_vxlan_log_enable_msg(struct nss_vxlan_msg *nvm)
+{
+	nss_trace("%px: NSS VXLAN Tunnel state message: Enable \n", nvm);
+}
+
+/*
+ * nss_vxlan_log_disable_msg()
+ *	Log NSS Vxlan rule disable message.
+ */
+static void nss_vxlan_log_disable_msg(struct nss_vxlan_msg *nvm)
+{
+	nss_trace("%px: NSS VXLAN Tunnel state message: Disable \n", nvm);
+}
+
+/*
+ * nss_vxlan_log_mac_add_msg()
+ *	Log NSS VXLAN mac rule add message.
+ */
+static void nss_vxlan_log_mac_add_msg(struct nss_vxlan_msg *nvm)
+{
+	struct nss_vxlan_mac_msg *nvmm __maybe_unused = &nvm->msg.mac_add;
+	nss_vxlan_log_mac_msg(nvmm);
+}
+
+/*
+ * nss_vxlan_log_mac_del_msg()
+ *	Log NSS VXLAN mac rule del message.
+ */
+static void nss_vxlan_log_mac_del_msg(struct nss_vxlan_msg *nvm)
+{
+	struct nss_vxlan_mac_msg *nvmm __maybe_unused = &nvm->msg.mac_del;
+	nss_vxlan_log_mac_msg(nvmm);
+}
+
+/*
+ * nss_vxlan_log_verbose()
+ *	Log message contents.
+ */
+static void nss_vxlan_log_verbose(struct nss_vxlan_msg *nvm)
+{
+	switch (nvm->cm.type) {
+	case NSS_VXLAN_MSG_TYPE_TUN_CONFIGURE:
+		nss_vxlan_log_rule_create_msg(nvm);
+		break;
+
+	case NSS_VXLAN_MSG_TYPE_TUN_UNCONFIGURE:
+		nss_vxlan_log_rule_destroy_msg(nvm);
+		break;
+
+	case NSS_VXLAN_MSG_TYPE_TUN_ENABLE:
+		nss_vxlan_log_enable_msg(nvm);
+		break;
+
+	case NSS_VXLAN_MSG_TYPE_TUN_DISABLE:
+		nss_vxlan_log_disable_msg(nvm);
+		break;
+
+	case NSS_VXLAN_MSG_TYPE_MAC_ADD:
+		nss_vxlan_log_mac_add_msg(nvm);
+		break;
+
+	case NSS_VXLAN_MSG_TYPE_MAC_DEL:
+		nss_vxlan_log_mac_del_msg(nvm);
+		break;
+
+	case NSS_VXLAN_MSG_TYPE_STATS_SYNC:
+	case NSS_VXLAN_MSG_TYPE_MACDB_STATS:
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", nvm);
+		break;
+	}
+}
+
+/*
+ * nss_vxlan_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_vxlan_log_tx_msg(struct nss_vxlan_msg *nvm)
+{
+	if (nvm->cm.type >= NSS_VXLAN_MSG_TYPE_MAX) {
+		nss_warning("%px: Invalid message type\n", nvm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nvm, nvm->cm.type, nss_vxlan_log_message_types_str[nvm->cm.type]);
+	nss_vxlan_log_verbose(nvm);
+}
+
+/*
+ * nss_vxlan_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_vxlan_log_rx_msg(struct nss_vxlan_msg *nvm)
+{
+	if (nvm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", nvm);
+		return;
+	}
+
+	if (nvm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nvm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nvm, nvm->cm.type,
+			nss_vxlan_log_message_types_str[nvm->cm.type],
+			nvm->cm.response, nss_cmn_response_str[nvm->cm.response]);
+		goto verbose;
+	}
+
+	if (nvm->cm.error >= NSS_VXLAN_ERROR_TYPE_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			nvm, nvm->cm.type, nss_vxlan_log_message_types_str[nvm->cm.type],
+			nvm->cm.response, nss_cmn_response_str[nvm->cm.response],
+			nvm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		nvm, nvm->cm.type, nss_vxlan_log_message_types_str[nvm->cm.type],
+		nvm->cm.response, nss_cmn_response_str[nvm->cm.response],
+		nvm->cm.error, nss_vxlan_log_error_response_types_str[nvm->cm.error]);
+
+verbose:
+	nss_vxlan_log_verbose(nvm);
+}
diff --git a/qca-nss-drv/nss_vxlan_log.h b/qca-nss-drv/nss_vxlan_log.h
new file mode 100644
index 0000000..2db12be
--- /dev/null
+++ b/qca-nss-drv/nss_vxlan_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_VXLAN_LOG_H__
+#define __NSS_VXLAN_LOG_H__
+
+/*
+ * nss_vxlan_log.h
+ *	NSS VXLAN Log Header File.
+ */
+
+/*
+ * nss_vxlan_log_tx_msg
+ *	Logs a Vxlan message that is sent to the NSS firmware.
+ */
+void nss_vxlan_log_tx_msg(struct nss_vxlan_msg *nvm);
+
+/*
+ * nss_vxlan_log_rx_msg
+ *	Logs a Vxlan message that is received from the NSS firmware.
+ */
+void nss_vxlan_log_rx_msg(struct nss_vxlan_msg *nvm);
+
+#endif /* __NSS_VXLAN_LOG_H__ */
diff --git a/qca-nss-drv/nss_vxlan_stats.c b/qca-nss-drv/nss_vxlan_stats.c
new file mode 100644
index 0000000..0559d0a
--- /dev/null
+++ b/qca-nss-drv/nss_vxlan_stats.c
@@ -0,0 +1,122 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_stats.h"
+#include "nss_vxlan_stats.h"
+#include <nss_vxlan.h>
+
+#define NSS_VXLAN_STATS_MAX_LINES (NSS_STATS_NODE_MAX + 32)
+					/**< Maximum number of lines for VXLAN statistics dump. */
+#define NSS_VXLAN_STATS_SIZE_PER_IF (NSS_STATS_MAX_STR_LENGTH * NSS_VXLAN_STATS_MAX_LINES)
+					/**< Total number of statistics per VXLAN interface. */
+
+/*
+ * nss_vxlan_stats_read()
+ *	Read vxlan node statiistics.
+ */
+static ssize_t nss_vxlan_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	struct nss_ctx_instance *nss_ctx = nss_vxlan_get_ctx();
+	enum nss_dynamic_interface_type type;
+	ssize_t bytes_read = 0;
+	size_t len = 0, size;
+	uint32_t if_num;
+	char *buf;
+
+	size = NSS_VXLAN_STATS_SIZE_PER_IF;
+	buf = kzalloc(size, GFP_KERNEL);
+	if (!buf) {
+		nss_warning("Could not allocate memory for local statistics buffer\n");
+		return 0;
+	}
+
+	/*
+	 * Common node stats for each VxLAN dynamic interface.
+	 */
+	for (if_num = 0; if_num < NSS_MAX_NET_INTERFACES; if_num++) {
+		if (if_num == NSS_VXLAN_INTERFACE) {
+			len += scnprintf(buf + len, size - len, "\nBase node if_num:%03u", if_num);
+			len += scnprintf(buf + len, size - len, "\n-------------------\n");
+			len += nss_stats_fill_common_stats(if_num, NSS_STATS_SINGLE_INSTANCE, buf, len, size - len, "vxlan");
+			continue;
+		}
+
+		type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+		switch (type) {
+		case NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_INNER:
+			len += scnprintf(buf + len, size - len, "\nInner if_num:%03u", if_num);
+			break;
+
+		case NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_OUTER:
+			len += scnprintf(buf + len, size - len, "\nOuter if_num:%03u", if_num);
+			break;
+
+		default:
+			continue;
+		}
+
+		len += scnprintf(buf + len, size - len, "\n-------------------\n");
+		len += nss_stats_fill_common_stats(if_num, NSS_STATS_SINGLE_INSTANCE, buf, len, size - len, "vxlan");
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, buf, len);
+	kfree(buf);
+	return bytes_read;
+}
+
+/*
+ * nss_vxlan_stats_sync()
+ *	Update vxlan common node statistics.
+ */
+void nss_vxlan_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_vxlan_msg *nvm)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	struct nss_vxlan_stats_msg *msg_stats = &nvm->msg.stats;
+	uint64_t *if_stats;
+
+	spin_lock_bh(&nss_top->stats_lock);
+
+	/*
+	 * Update common node stats
+	 */
+	if_stats = nss_top->stats_node[nvm->cm.interface];
+	if_stats[NSS_STATS_NODE_RX_PKTS] += msg_stats->node_stats.rx_packets;
+	if_stats[NSS_STATS_NODE_RX_BYTES] += msg_stats->node_stats.rx_bytes;
+	if_stats[NSS_STATS_NODE_RX_QUEUE_0_DROPPED] += msg_stats->node_stats.rx_dropped[0];
+	if_stats[NSS_STATS_NODE_RX_QUEUE_1_DROPPED] += msg_stats->node_stats.rx_dropped[1];
+	if_stats[NSS_STATS_NODE_RX_QUEUE_2_DROPPED] += msg_stats->node_stats.rx_dropped[2];
+	if_stats[NSS_STATS_NODE_RX_QUEUE_3_DROPPED] += msg_stats->node_stats.rx_dropped[3];
+
+	if_stats[NSS_STATS_NODE_TX_PKTS] += msg_stats->node_stats.tx_packets;
+	if_stats[NSS_STATS_NODE_TX_BYTES] += msg_stats->node_stats.tx_bytes;
+
+	spin_unlock_bh(&nss_top->stats_lock);
+}
+
+/*
+ * nss_vxlan_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(vxlan)
+
+/*
+ * nss_vxlan_stats_dentry_create()
+ *	Create vxlan statistics debug entry.
+ */
+void nss_vxlan_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("vxlan", &nss_vxlan_stats_ops);
+}
diff --git a/qca-nss-drv/nss_vxlan_stats.h b/qca-nss-drv/nss_vxlan_stats.h
new file mode 100644
index 0000000..b4748f4
--- /dev/null
+++ b/qca-nss-drv/nss_vxlan_stats.h
@@ -0,0 +1,32 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef _NSS_VXLAN_STATS_H_
+#define _NSS_VXLAN_STATS_H_
+
+/*
+ * nss_vxlan_stats_dentry_create
+ *	Creates vxlan interface statistics debug entry.
+ */
+void nss_vxlan_stats_dentry_create(void);
+
+/*
+ * nss_vxlan_stats_sync
+ *	Update vxlan common node statistics.
+ */
+void nss_vxlan_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_vxlan_msg *nvm);
+
+#endif /* _NSS_VXLAN_STATS_H_ */
diff --git a/qca-nss-drv/nss_wifi.c b/qca-nss-drv/nss_wifi.c
new file mode 100644
index 0000000..559d947
--- /dev/null
+++ b/qca-nss-drv/nss_wifi.c
@@ -0,0 +1,198 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_wifi_stats.h"
+#include "nss_wifi_log.h"
+
+/*
+ * nss_wifi_get_context()
+ *	Get NSS context of Wifi.
+ */
+struct nss_ctx_instance *nss_wifi_get_context()
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wifi_handler_id];
+}
+
+/*
+ * nss_wifi_handler()
+ * 	Handle NSS -> HLOS messages for wifi
+ */
+static void nss_wifi_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_wifi_msg *ntm = (struct nss_wifi_msg *)ncm;
+	void *ctx;
+	nss_wifi_msg_callback_t cb;
+
+	nss_info("%px: NSS ->HLOS message for wifi\n", nss_ctx);
+
+	BUG_ON(((ncm->interface < NSS_WIFI_INTERFACE0) || (ncm->interface > NSS_WIFI_INTERFACE2)));
+
+	/*
+	 * Trace messages.
+	 */
+	nss_wifi_log_rx_msg(ntm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_WIFI_MAX_MSG) {
+		nss_warning("%px: received invalid message %d for wifi interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_wifi_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Snoop messages for local driver and handle
+	 */
+	switch (ntm->cm.type) {
+	case NSS_WIFI_STATS_MSG:
+		/*
+		 * To create the old API gmac statistics, we use the new extended GMAC stats.
+		 */
+		nss_wifi_stats_sync(nss_ctx, &ntm->msg.statsmsg, ncm->interface);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages, wifi sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->wifi_msg_callback;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		nss_info("%px: cb null for wifi interface %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	/*
+	 * Get callback & context
+	 */
+	cb = (nss_wifi_msg_callback_t)ncm->cb;
+	ctx = nss_ctx->subsys_dp_register[ncm->interface].ndev;
+
+	/*
+	 * call wifi msg callback
+	 */
+	if (!ctx) {
+		nss_warning("%px: Event received for wifi interface %d before registration", nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb(ctx, ntm);
+}
+
+/*
+ * nss_wifi_tx_msg
+ * 	Transmit a wifi message to NSS FW
+ */
+nss_tx_status_t nss_wifi_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_wifi_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace messages.
+	 */
+	nss_wifi_log_tx_msg(msg);
+
+	if (ncm->type > NSS_WIFI_MAX_MSG) {
+		nss_warning("%px: wifi message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+
+/*
+ ****************************************
+ * Register/Unregister/Miscellaneous APIs
+ ****************************************
+ */
+
+/*
+ * nss_register_wifi_if()
+ * 	Register Wifi with nss driver
+ */
+struct nss_ctx_instance *nss_register_wifi_if(uint32_t if_num, nss_wifi_callback_t wifi_callback,
+			nss_wifi_callback_t wifi_ext_callback,
+			nss_wifi_msg_callback_t event_callback, struct net_device *netdev, uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wifi_handler_id];
+
+	nss_assert(nss_ctx);
+	nss_assert((if_num >= NSS_MAX_VIRTUAL_INTERFACES) && (if_num < NSS_MAX_NET_INTERFACES));
+
+	nss_info("%px: nss_register_wifi_if if_num %d wifictx %px", nss_ctx, if_num, netdev);
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, wifi_callback, wifi_ext_callback, NULL, netdev, features);
+
+	nss_top_main.wifi_msg_callback = event_callback;
+
+	return nss_ctx;
+}
+
+/*
+ * nss_unregister_wifi_if()
+ * 	Unregister wifi with nss driver
+ */
+void nss_unregister_wifi_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wifi_handler_id];
+
+	nss_assert(nss_ctx);
+	nss_assert((if_num >= NSS_MAX_VIRTUAL_INTERFACES) && (if_num < NSS_MAX_NET_INTERFACES));
+
+	nss_ctx->nss_top->wifi_msg_callback = NULL;
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+}
+
+/*
+ * nss_wifi_register_handler()
+ * 	Register handle for notfication messages received on wifi interface
+ */
+void nss_wifi_register_handler(void )
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wifi_handler_id];
+
+	nss_assert(nss_ctx);
+
+	nss_info("nss_wifi_register_handler");
+
+	nss_core_register_handler(nss_ctx, NSS_WIFI_INTERFACE0, nss_wifi_handler, NULL);
+	nss_core_register_handler(nss_ctx, NSS_WIFI_INTERFACE1, nss_wifi_handler, NULL);
+	nss_core_register_handler(nss_ctx, NSS_WIFI_INTERFACE2, nss_wifi_handler, NULL);
+
+	nss_wifi_stats_dentry_create();
+}
+
+EXPORT_SYMBOL(nss_wifi_get_context);
+EXPORT_SYMBOL(nss_wifi_tx_msg);
+EXPORT_SYMBOL(nss_register_wifi_if);
+EXPORT_SYMBOL(nss_unregister_wifi_if);
diff --git a/qca-nss-drv/nss_wifi_ext_vdev.c b/qca-nss-drv/nss_wifi_ext_vdev.c
new file mode 100644
index 0000000..bb27239
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_ext_vdev.c
@@ -0,0 +1,338 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_wifi_ext_vdev_stats.h"
+#include "nss_wifi_ext_vdev_log.h"
+
+#define NSS_WIFI_EXT_VDEV_TX_TIMEOUT 3000 /* 3 seconds */
+
+/*
+ * Private data structure
+ */
+static struct nss_wifi_ext_vdev_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+	void *cb;
+	void *app_data;
+} wifi_ext_vdev_pvt;
+
+/*
+ * nss_wifi_ext_vdev_verify_if_num()
+ *	Verify if_num passed to us.
+ */
+static bool nss_wifi_ext_vdev_verify_if_num(uint32_t if_num)
+{
+	uint32_t type = nss_dynamic_interface_get_type(nss_wifi_ext_vdev_get_ctx(), if_num);
+
+	switch (type) {
+	case NSS_DYNAMIC_INTERFACE_TYPE_WIFI_EXT_VDEV_WDS:
+	case NSS_DYNAMIC_INTERFACE_TYPE_WIFI_EXT_VDEV_VLAN:
+		return true;
+	default:
+		return false;
+	}
+}
+
+/*
+ * nss_wifi_ext_vdev_handler()
+ *	Handle NSS -> HLOS messages for wifi_ext_vdev
+ */
+static void nss_wifi_ext_vdev_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, void *app_data)
+{
+	struct nss_wifi_ext_vdev_msg *nwevm = (struct nss_wifi_ext_vdev_msg *)ncm;
+	void *ctx;
+
+	nss_wifi_ext_vdev_msg_callback_t cb;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	BUG_ON(!nss_wifi_ext_vdev_verify_if_num(ncm->interface));
+
+	/*
+	 * Trace Messages
+	 */
+	nss_wifi_ext_vdev_log_rx_msg(nwevm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_WIFI_EXT_VDEV_MSG_MAX) {
+		nss_warning("%px: received invalid message %d for WiFi extended VAP interface %d", nss_ctx, ncm->type, ncm->interface);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_wifi_ext_vdev_msg)) {
+		nss_warning("%px: wifi_ext_vdev message length is invalid: %d", nss_ctx, ncm->len);
+		return;
+	}
+
+	/*
+	 * Check messages
+	 */
+	switch (nwevm->cm.type) {
+	case NSS_WIFI_EXT_VDEV_MSG_STATS_SYNC:
+		nss_wifi_ext_vdev_stats_sync(nss_ctx, &nwevm->msg.stats, ncm->interface);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for NOTIFY messages
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->subsys_dp_register[ncm->interface].app_data;
+	}
+
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * callback
+	 */
+	cb = (nss_wifi_ext_vdev_msg_callback_t)ncm->cb;
+	ctx = (void *)ncm->app_data;
+
+	/*
+	 * call the callback
+	 */
+	if (!cb) {
+		return;
+	}
+
+	cb(ctx, ncm);
+}
+
+/*
+ * nss_wifi_ext_vdev_msg_init()
+ *	Initialize wifi message.
+ */
+void nss_wifi_ext_vdev_msg_init(struct nss_wifi_ext_vdev_msg *nim, uint32_t if_num,
+			uint32_t type, uint32_t len,
+			nss_wifi_ext_vdev_msg_callback_t cb, void *app_data)
+{
+	nss_cmn_msg_init(&nim->cm, if_num, type, len, cb, app_data);
+}
+EXPORT_SYMBOL(nss_wifi_ext_vdev_msg_init);
+
+/*
+ * nss_wifi_ext_vdev_tx_msg()
+ *	Transmit a wifi vdev message to NSSFW
+ */
+nss_tx_status_t nss_wifi_ext_vdev_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_wifi_ext_vdev_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace Messages
+	 */
+	nss_wifi_ext_vdev_log_tx_msg(msg);
+
+	if (ncm->type >= NSS_WIFI_EXT_VDEV_MSG_MAX) {
+		nss_warning("%px: wifi vdev message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	BUG_ON(!nss_wifi_ext_vdev_verify_if_num(ncm->interface));
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_wifi_ext_vdev_tx_msg);
+
+/*
+ * nss_wifi_ext_vdev_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_wifi_ext_vdev_callback(void *app_data, struct nss_cmn_msg *ncm)
+{
+	nss_wifi_ext_vdev_msg_callback_t callback = (nss_wifi_ext_vdev_msg_callback_t)wifi_ext_vdev_pvt.cb;
+	void *data = wifi_ext_vdev_pvt.app_data;
+
+	wifi_ext_vdev_pvt.response = NSS_TX_SUCCESS;
+	wifi_ext_vdev_pvt.cb = NULL;
+	wifi_ext_vdev_pvt.app_data = NULL;
+
+	if (ncm->response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("WiFi extension vap Error response %d\n", ncm->response);
+		wifi_ext_vdev_pvt.response = NSS_TX_FAILURE;
+	}
+
+	if (callback) {
+		callback(data, ncm);
+	}
+	complete(&wifi_ext_vdev_pvt.complete);
+}
+
+/*
+ * nss_wifi_ext_vdev_tx_msg()
+ *	Transmit a WiFi extended virtual interface to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_wifi_ext_vdev_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_wifi_ext_vdev_msg *nwevm)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&wifi_ext_vdev_pvt.sem);
+	wifi_ext_vdev_pvt.cb = (void *)nwevm->cm.cb;
+	wifi_ext_vdev_pvt.app_data = (void *)nwevm->cm.app_data;
+
+	nwevm->cm.cb = (nss_ptr_t)nss_wifi_ext_vdev_callback;
+	nwevm->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_wifi_ext_vdev_tx_msg(nss_ctx, nwevm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: wifi_ext_vdev_tx_msg failed\n", nss_ctx);
+		up(&wifi_ext_vdev_pvt.sem);
+		return status;
+	}
+
+	/*
+	 * Wait for the acknowledgement
+	 */
+	ret = wait_for_completion_timeout(&wifi_ext_vdev_pvt.complete, msecs_to_jiffies(NSS_WIFI_EXT_VDEV_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: WiFi extended vap msg tx failed due to timeout\n", nss_ctx);
+		wifi_ext_vdev_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = wifi_ext_vdev_pvt.response;
+	up(&wifi_ext_vdev_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_wifi_ext_vdev_tx_msg_sync);
+
+/*
+ * nss_wifi_ext_vdev_tx_buf
+ * 	Send data packet for vap processing
+ */
+nss_tx_status_t nss_wifi_ext_vdev_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *skb, uint32_t if_num)
+{
+	BUG_ON(!nss_wifi_ext_vdev_verify_if_num(if_num));
+
+	return nss_core_send_packet(nss_ctx, skb, if_num, H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+EXPORT_SYMBOL(nss_wifi_ext_vdev_tx_buf);
+
+/*
+ * nss_wifi_ext_vdev_set_next_hop()
+ *	Set the WiFI extended vap next hop.
+ */
+nss_tx_status_t nss_wifi_ext_vdev_set_next_hop(struct nss_ctx_instance *ctx, int if_num, int next_hop)
+{
+	struct nss_wifi_ext_vdev_msg *nwevm = kzalloc(sizeof(struct nss_wifi_ext_vdev_msg), GFP_KERNEL);
+	struct nss_wifi_ext_vdev_set_next_hop_msg *nhm = NULL;
+	nss_tx_status_t status;
+
+	if (!nwevm) {
+		nss_warning("%px: Unable to allocate next hop message", ctx);
+		return NSS_TX_FAILURE;
+	}
+
+	nhm = &nwevm->msg.wnhm;
+
+	nhm->if_num = next_hop;
+	nss_wifi_ext_vdev_msg_init(nwevm, if_num, NSS_WIFI_EXT_VDEV_SET_NEXT_HOP,
+			sizeof(struct nss_wifi_ext_vdev_set_next_hop_msg), NULL, NULL);
+
+	status = nss_wifi_ext_vdev_tx_msg(ctx, nwevm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Unable to send next hop message", ctx);
+	}
+
+	kfree(nwevm);
+	return status;
+}
+EXPORT_SYMBOL(nss_wifi_ext_vdev_set_next_hop);
+
+/*
+ * nss_get_wifi_ext_vdev_ext_context()
+ *	Return the core ctx which the feature is on
+ */
+struct nss_ctx_instance *nss_wifi_ext_vdev_get_ctx(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wifi_handler_id];
+}
+EXPORT_SYMBOL(nss_wifi_ext_vdev_get_ctx);
+
+/*
+ * nss_wifi_ext_vdev_register_if()
+ */
+struct nss_ctx_instance *nss_wifi_ext_vdev_register_if(uint32_t if_num,
+				nss_wifi_ext_vdev_data_callback_t data_callback,
+				nss_wifi_ext_vdev_ext_data_callback_t ext_callback,
+				nss_wifi_ext_vdev_msg_callback_t event_callback,
+				struct net_device *netdev,
+				uint32_t features, void *app_data)
+{
+	struct nss_ctx_instance *nss_ctx = nss_wifi_ext_vdev_get_ctx();
+
+	BUG_ON(!nss_wifi_ext_vdev_verify_if_num(if_num));
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, data_callback, ext_callback, app_data, netdev, features);
+
+	nss_core_register_msg_handler(nss_ctx, if_num, event_callback);
+
+	nss_core_register_handler(nss_ctx, if_num, nss_wifi_ext_vdev_handler, app_data);
+
+	nss_wifi_ext_vdev_stats_register(if_num, netdev);
+
+	return nss_ctx;
+}
+EXPORT_SYMBOL(nss_wifi_ext_vdev_register_if);
+
+/*
+ * nss_wifi_ext_vdev_unregister_if()
+ */
+bool nss_wifi_ext_vdev_unregister_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_wifi_ext_vdev_get_ctx();
+	struct net_device *netdev;
+
+	BUG_ON(!nss_wifi_ext_vdev_verify_if_num(if_num));
+
+	nss_assert(nss_ctx);
+
+	netdev = nss_cmn_get_interface_dev(nss_ctx, if_num);
+	if (!netdev) {
+		nss_warning("%px: Unable to find net device for the interface %d\n", nss_ctx, if_num);
+		return false;
+	}
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	nss_core_unregister_msg_handler(nss_ctx, if_num);
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+
+	nss_wifi_ext_vdev_stats_unregister(if_num, netdev);
+	return true;
+}
+EXPORT_SYMBOL(nss_wifi_ext_vdev_unregister_if);
+
+/*
+ * nss_wifi_ext_vdev_register_handler()
+ *	Register debugfs handler received on base interface
+ */
+void nss_wifi_ext_vdev_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = nss_wifi_ext_vdev_get_ctx();
+
+	nss_info("nss_wifi_ext_vdev_handler");
+	sema_init(&wifi_ext_vdev_pvt.sem, 1);
+	init_completion(&wifi_ext_vdev_pvt.complete);
+	nss_core_register_handler(nss_ctx, NSS_WIFI_EXT_VDEV_INTERFACE, nss_wifi_ext_vdev_handler, NULL);
+	nss_wifi_ext_vdev_stats_dentry_create();
+}
diff --git a/qca-nss-drv/nss_wifi_ext_vdev_log.c b/qca-nss-drv/nss_wifi_ext_vdev_log.c
new file mode 100644
index 0000000..7fd1888
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_ext_vdev_log.c
@@ -0,0 +1,220 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_wifi_ext_vdev_log.c
+ *	NSS WiFi extended VAP logger file.
+ */
+
+#include "nss_core.h"
+
+#define NSS_WIFI_EXT_VDEV_LOG_MESSAGE_TYPE_INDEX(type) ((type) - NSS_IF_MAX_MSG_TYPES)
+
+/*
+ * nss_wifi_ext_vdev_log_message_types_str
+ *	NSS WiFi extended VAP message strings
+ */
+static int8_t *nss_wifi_ext_vdev_log_message_types_str[NSS_WIFI_EXT_VDEV_MSG_MAX] __maybe_unused = {
+	"WiFi Common I/F Message",
+	"WiFi Extendev VAP configure",
+	"WiFi Extendev VAP configure wds",
+	"WiFi Extendev VAP configure next hop",
+	"WiFi Extendev VAP stats",
+	"WiFi Extended VAP configure VLAN"
+};
+
+/*
+ * nss_wifi_ext_vdev_log_configure_msg()
+ *	Log NSS WiFi extended vap configure message.
+ */
+static void nss_wifi_ext_vdev_log_configure_if_msg(struct nss_wifi_ext_vdev_msg *nwevm)
+{
+	struct nss_wifi_ext_vdev_configure_if_msg *cmsg __maybe_unused = &nwevm->msg.cmsg;
+	nss_trace("%px: WiFi extended VAP configure message \n"
+		"Mac address: %pM\n"
+		"Radio interface num: %d\n"
+		"Parent VAP interface num: %d\n",
+		cmsg, cmsg->mac_addr, cmsg->radio_ifnum,
+		cmsg->pvap_ifnum);
+
+}
+
+/*
+ * nss_wifi_ext_vdev_log_wds_msg()
+ *	Log NSS WiFi extended vap wds message.
+ */
+static void nss_wifi_ext_vdev_log_wds_msg(struct nss_wifi_ext_vdev_msg *nwevm)
+{
+	struct nss_wifi_ext_vdev_wds_msg *wmsg __maybe_unused = &nwevm->msg.wmsg;
+	nss_trace("%px: NSS WiFi extended VAP wds message: \n"
+		"WDS sta ID: %d\n"
+		"WDS sta macaddr: %pM\n",
+		wmsg, wmsg->wds_peer_id,
+		wmsg->mac_addr);
+}
+
+/*
+ * nss_wifi_ext_vdev_set_nxt_hop_msg()
+ *	Set the next hop message.
+ */
+static void nss_wifi_ext_vdev_set_nxt_hop_msg(struct nss_wifi_ext_vdev_msg *nwevm)
+{
+	struct nss_wifi_ext_vdev_set_next_hop_msg *wnhm __maybe_unused = &nwevm->msg.wnhm;
+	nss_trace("%px: NSS WiFi extended vap set next hop message: \n"
+		"Next hop if num: %d\n",
+		wnhm, wnhm->if_num);
+
+}
+
+/*
+ * nss_wifi_ext_vdev_linkup_msg()
+ *	Log NSS linkup message.
+ */
+static void nss_wifi_ext_vdev_linkup_msg(struct nss_wifi_ext_vdev_msg *nwevm)
+{
+	union nss_if_msgs *if_msg __maybe_unused = &nwevm->msg.if_msg;
+	nss_trace("%px: NSS WiFi ext linkup message\n", if_msg);
+}
+
+/*
+ * nss_wifi_ext_vdev_linkdown_msg()
+ *	Log NSS linkdown message.
+ */
+static void nss_wifi_ext_vdev_linkdown_msg(struct nss_wifi_ext_vdev_msg *nwevm)
+{
+	union nss_if_msgs *if_msg __maybe_unused = &nwevm->msg.if_msg;
+	nss_trace("%px: NSS WiFi ext linkdown message\n", if_msg);
+}
+
+/*
+ * nss_wifi_ext_vdev_macaddr_set_msg()
+ *	Set/Change the mac address
+ */
+static void nss_wifi_ext_vdev_macaddr_set_msg(struct nss_wifi_ext_vdev_msg *nwevm)
+{
+	union nss_if_msgs *if_msg = &nwevm->msg.if_msg;
+	struct nss_if_mac_address_set *nimas __maybe_unused = &if_msg->mac_address_set;
+	nss_trace("%px: NSS WiFi ext change mac addr: \n"
+		"mac addr %pM\n",
+		nimas, nimas->mac_addr);
+}
+
+/*
+ * nss_wifi_ext_vdev_log_vlan_msg()
+ *	Configure vlan message.
+ */
+static void nss_wifi_ext_vdev_log_vlan_msg(struct nss_wifi_ext_vdev_msg *nwevm)
+{
+	struct nss_wifi_ext_vdev_vlan_msg *vmsg __maybe_unused = &nwevm->msg.vmsg;
+	nss_trace("%px: NSS WiFi extended VAP vlan message: \n"
+		"vlan ID %hu\n",
+		vmsg, vmsg->vlan_id);
+}
+
+/*
+ * nss_wifi_ext_vdev_log_verbose()
+ *	Log message contents.
+ */
+static void nss_wifi_ext_vdev_log_verbose(struct nss_wifi_ext_vdev_msg *nwevm)
+{
+	switch (nwevm->cm.type) {
+	case NSS_WIFI_EXT_VDEV_MSG_CONFIGURE_IF:
+		nss_wifi_ext_vdev_log_configure_if_msg(nwevm);
+		break;
+
+	case NSS_WIFI_EXT_VDEV_MSG_CONFIGURE_WDS :
+		nss_wifi_ext_vdev_log_wds_msg(nwevm);
+		break;
+
+	case NSS_WIFI_EXT_VDEV_SET_NEXT_HOP:
+		nss_wifi_ext_vdev_set_nxt_hop_msg(nwevm);
+		break;
+
+	case NSS_WIFI_EXT_VDEV_MSG_STATS_SYNC:
+		break;
+
+	case NSS_IF_OPEN:
+		nss_wifi_ext_vdev_linkup_msg(nwevm);
+		break;
+
+	case NSS_IF_CLOSE:
+		nss_wifi_ext_vdev_linkdown_msg(nwevm);
+		break;
+
+	case NSS_IF_MAC_ADDR_SET:
+		nss_wifi_ext_vdev_macaddr_set_msg(nwevm);
+		break;
+
+	case NSS_WIFI_EXT_VDEV_MSG_CONFIGURE_VLAN:
+		nss_wifi_ext_vdev_log_vlan_msg(nwevm);
+		break;
+
+	default:
+		nss_trace("%px: Invalid message type\n", nwevm);
+		break;
+	}
+}
+
+/*
+ * nss_wifi_ext_vdev_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_wifi_ext_vdev_log_tx_msg(struct nss_wifi_ext_vdev_msg *nwevm)
+{
+	uint32_t type_idx = 0;
+	if (nwevm->cm.type >= NSS_WIFI_EXT_VDEV_MSG_MAX) {
+		nss_warning("%px: Invalid message type\n", nwevm);
+		return;
+	}
+
+	type_idx = (nwevm->cm.type > NSS_IF_MAX_MSG_TYPES) ?
+			(NSS_WIFI_EXT_VDEV_LOG_MESSAGE_TYPE_INDEX(nwevm->cm.type)) : 0;
+
+	nss_info("%px: type[%d]:%s\n", nwevm, nwevm->cm.type, nss_wifi_ext_vdev_log_message_types_str[type_idx]);
+	nss_wifi_ext_vdev_log_verbose(nwevm);
+}
+
+/*
+ * nss_wifi_ext_vdev_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_wifi_ext_vdev_log_rx_msg(struct nss_wifi_ext_vdev_msg *nwevm)
+{
+	uint32_t type_idx = 0;
+	if (nwevm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", nwevm);
+		return;
+	}
+
+	type_idx = (nwevm->cm.type > NSS_IF_MAX_MSG_TYPES) ?
+			(NSS_WIFI_EXT_VDEV_LOG_MESSAGE_TYPE_INDEX(nwevm->cm.type)) : 0;
+
+	if (nwevm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nwevm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nwevm, nwevm->cm.type,
+			nss_wifi_ext_vdev_log_message_types_str[type_idx],
+			nwevm->cm.response, nss_cmn_response_str[nwevm->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		nwevm, nwevm->cm.type, nss_wifi_ext_vdev_log_message_types_str[type_idx],
+		nwevm->cm.response, nss_cmn_response_str[nwevm->cm.response]);
+
+verbose:
+	nss_wifi_ext_vdev_log_verbose(nwevm);
+}
diff --git a/qca-nss-drv/nss_wifi_ext_vdev_log.h b/qca-nss-drv/nss_wifi_ext_vdev_log.h
new file mode 100644
index 0000000..a5c8510
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_ext_vdev_log.h
@@ -0,0 +1,34 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_WIFI_EXT_VDEV_LOG_H
+#define __NSS_WIFI_EXT_VDEV_LOG_H
+
+/*
+ * nss_wifi_ext_vdev_log_tx_msg
+ *	Logs a wifi_ext_vdev message that is sent to the NSS firmware.
+ */
+void nss_wifi_ext_vdev_log_tx_msg(struct nss_wifi_ext_vdev_msg *nwevm);
+
+/*
+ * nss_wifi_ext_vdev_log_rx_msg
+ *	Logs a wifi_ext_vdev message that is received from the NSS firmware.
+ */
+void nss_wifi_ext_vdev_log_rx_msg(struct nss_wifi_ext_vdev_msg *nwevm);
+
+#endif /* __NSS_WIFI_EXT_VDEV_LOG_H */
diff --git a/qca-nss-drv/nss_wifi_ext_vdev_stats.c b/qca-nss-drv/nss_wifi_ext_vdev_stats.c
new file mode 100644
index 0000000..493ca84
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_ext_vdev_stats.c
@@ -0,0 +1,234 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_wifi_ext_vdev_stats.h"
+
+DEFINE_SPINLOCK(nss_wifi_ext_vdev_debug_lock);
+struct nss_wifi_ext_vdev_debug nss_wifi_ext_vdev_debug_stats[NSS_WIFI_EXT_VDEV_MAX];
+
+/*
+ * nss_wifi_ext_vdev_debug_str
+ *	WiFi extended VAP statistics strings.
+ */
+struct nss_stats_info nss_wifi_ext_vdev_debug_str[NSS_WIFI_EXT_VDEV_STATS_MAX] = {
+	{"node_rx_pkts"					, NSS_STATS_TYPE_COMMON},
+	{"node_rx_bytes"				, NSS_STATS_TYPE_COMMON},
+	{"node_tx_pkts"					, NSS_STATS_TYPE_COMMON},
+	{"node_tx_bytes"				, NSS_STATS_TYPE_COMMON},
+	{"node_rx_dropped"				, NSS_STATS_TYPE_DROP},
+	{"mc_count"					, NSS_STATS_TYPE_SPECIAL},
+	{"uc_count"					, NSS_STATS_TYPE_SPECIAL},
+	{"nxt_hop_drop"					, NSS_STATS_TYPE_DROP},
+};
+
+/*
+ * WiFi extended vdev statistics APIs
+ */
+
+/*
+ * nss_wifi_ext_vdev_stats_register()
+ *	Register debug statistic for WiFi extended VAP.
+ */
+void nss_wifi_ext_vdev_stats_register(uint32_t if_num, struct net_device *netdev)
+{
+	int i;
+
+	spin_lock_bh(&nss_wifi_ext_vdev_debug_lock);
+	for (i = 0; i < NSS_WIFI_EXT_VDEV_MAX; i++) {
+		if (!nss_wifi_ext_vdev_debug_stats[i].valid) {
+			nss_wifi_ext_vdev_debug_stats[i].valid = true;
+			nss_wifi_ext_vdev_debug_stats[i].if_num = if_num;
+			nss_wifi_ext_vdev_debug_stats[i].if_index = netdev->ifindex;
+			break;
+		}
+	}
+
+	spin_unlock_bh(&nss_wifi_ext_vdev_debug_lock);
+}
+
+/*
+ * nss_wifi_ext_vdev_stats_unregister()
+ *	Register debug statistic for WiFi extended vap.
+ */
+void nss_wifi_ext_vdev_stats_unregister(uint32_t if_num, struct net_device *netdev)
+{
+	int i;
+
+	spin_lock_bh(&nss_wifi_ext_vdev_debug_lock);
+	for (i = 0; i < NSS_WIFI_EXT_VDEV_MAX; i++) {
+		if (nss_wifi_ext_vdev_debug_stats[i].if_num == if_num) {
+			memset(&nss_wifi_ext_vdev_debug_stats[i], 0,
+			       sizeof(struct nss_wifi_ext_vdev_debug));
+			break;
+		}
+	}
+	spin_unlock_bh(&nss_wifi_ext_vdev_debug_lock);
+}
+
+/*
+ * nss_wifi_ext_vdev_stats_sync()
+ *	Sync function for WiFi extendev vap statistics.
+ */
+void nss_wifi_ext_vdev_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_wifi_ext_vdev_stats *stats_msg,
+					uint16_t if_num)
+{
+	int i;
+	struct nss_wifi_ext_vdev_debug *s = NULL;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	spin_lock_bh(&nss_wifi_ext_vdev_debug_lock);
+	for (i = 0; i < NSS_WIFI_EXT_VDEV_MAX; i++) {
+		if (nss_wifi_ext_vdev_debug_stats[i].if_num == if_num) {
+			s = &nss_wifi_ext_vdev_debug_stats[i];
+			break;
+		}
+	}
+
+	if (!s) {
+		spin_unlock_bh(&nss_wifi_ext_vdev_debug_lock);
+		nss_warning("%px: Interface:%u not found", nss_ctx, if_num);
+		return;
+	}
+
+	s->stats[NSS_WIFI_EXT_VDEV_STATS_NODE_RX_PKTS ] += stats_msg->node_stats.rx_packets;
+	s->stats[NSS_WIFI_EXT_VDEV_STATS_NODE_RX_BYTES] += stats_msg->node_stats.rx_bytes;
+	s->stats[NSS_WIFI_EXT_VDEV_STATS_NODE_TX_PKTS] += stats_msg->node_stats.tx_packets;
+	s->stats[NSS_WIFI_EXT_VDEV_STATS_NODE_TX_BYTES] += stats_msg->node_stats.tx_bytes;
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		s->stats[NSS_WIFI_EXT_VDEV_STATS_NODE_TOTAL_DROPPED] += stats_msg->node_stats.rx_dropped[i];
+	}
+	s->stats[NSS_WIFI_EXT_VDEV_STATS_MULTICAST_COUNT] += stats_msg->mc_count;
+	s->stats[NSS_WIFI_EXT_VDEV_STATS_UNICAST_COUNT] += stats_msg->node_stats.rx_packets - stats_msg->mc_count;
+	s->stats[NSS_WIFI_EXT_VDEV_STATS_NEXT_HOP_DROP_COUNT] += stats_msg->nxt_hop_drp;
+	spin_unlock_bh(&nss_wifi_ext_vdev_debug_lock);
+}
+
+/*
+ * nss_wifi_ext_vdev_debug_get()
+ *	Get WiFi extendev vap debug statitics.
+ */
+static void nss_wifi_ext_vdev_debug_get(struct nss_wifi_ext_vdev_debug *stats)
+{
+	int i;
+
+	if (!stats) {
+		nss_warning("No memory to copy WiFi extended VAP stats");
+		return;
+	}
+
+	spin_lock_bh(&nss_wifi_ext_vdev_debug_lock);
+	for (i = 0; i < NSS_WIFI_EXT_VDEV_MAX; i++) {
+		if (nss_wifi_ext_vdev_debug_stats[i].valid) {
+			memcpy(stats, &nss_wifi_ext_vdev_debug_stats[i],
+				sizeof(struct nss_wifi_ext_vdev_debug));
+			stats++;
+		}
+	}
+	spin_unlock_bh(&nss_wifi_ext_vdev_debug_lock);
+}
+
+/*
+ * nss_wifi_ext_vdev_read()
+ *	Read WiFi extended VAP statistics
+ */
+static ssize_t nss_wifi_ext_vdev_stats_read(struct file *fp, char __user *ubuf,
+					size_t sz, loff_t *ppos)
+{
+	uint32_t max_output_lines = 2 /* header and footer of the interface stats*/
+		+ (NSS_WIFI_EXT_VDEV_STATS_MAX * (NSS_WIFI_EXT_VDEV_MAX + 2)) /* Interface stats */
+		+ 2;
+
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	size_t bytes_read = 0;
+	struct net_device *dev;
+	int id;
+	struct nss_wifi_ext_vdev_debug *wifi_ext_vdev_stats = NULL;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	wifi_ext_vdev_stats = kzalloc((sizeof(struct nss_wifi_ext_vdev_debug) * NSS_WIFI_EXT_VDEV_MAX), GFP_KERNEL);
+	if (unlikely(wifi_ext_vdev_stats == NULL)) {
+		nss_warning("Could not allocate memory for populating stats");
+		kfree(lbuf);
+		return 0;
+	}
+
+	/*
+	 * Get all stats
+	 */
+	nss_wifi_ext_vdev_debug_get(wifi_ext_vdev_stats);
+
+	/*
+	 * WiFi extended vap stats.
+	 */
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "WiFi extended VAP stats", NSS_STATS_SINGLE_CORE);
+
+	for (id = 0; id < NSS_WIFI_EXT_VDEV_MAX; id++) {
+		if (!wifi_ext_vdev_stats[id].valid) {
+			continue;
+		}
+
+		dev = dev_get_by_index(&init_net, wifi_ext_vdev_stats[id].if_index);
+		if (likely(dev)) {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+						"%d. nss interface id=%d, netdevice=%s\n",
+						id, wifi_ext_vdev_stats[id].if_num,
+						dev->name);
+			dev_put(dev);
+		} else {
+			size_wr += scnprintf(lbuf + size_wr, size_al - size_wr,
+						"%d. nss interface id=%d\n", id,
+						wifi_ext_vdev_stats[id].if_num);
+		}
+
+		size_wr += nss_stats_print("vdev", "debug", id
+						, nss_wifi_ext_vdev_debug_str
+						, wifi_ext_vdev_stats[id].stats
+						, NSS_WIFI_EXT_VDEV_STATS_MAX
+						, lbuf, size_wr, size_al);
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+
+	kfree(wifi_ext_vdev_stats);
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/*
+ * nss_wifi_ext_vdev_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(wifi_ext_vdev);
+
+/*
+ * nss_wifi_ext_vdev_dentry_create()
+ *	Create wifi extension vap statistics debug entry.
+ */
+void nss_wifi_ext_vdev_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("wifi_ext_vdev", &nss_wifi_ext_vdev_stats_ops);
+}
diff --git a/qca-nss-drv/nss_wifi_ext_vdev_stats.h b/qca-nss-drv/nss_wifi_ext_vdev_stats.h
new file mode 100644
index 0000000..589e2c0
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_ext_vdev_stats.h
@@ -0,0 +1,60 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_WIFI_EXT_VDEV_STATS_H
+#define __NSS_WIFI_EXT_VDEV_STATS_H
+
+/*
+ * WiFi extendev vap debug statistic counters.
+ */
+enum nss_wifi_ext_vdev_stats_types {
+	NSS_WIFI_EXT_VDEV_STATS_NODE_RX_PKTS,
+	NSS_WIFI_EXT_VDEV_STATS_NODE_RX_BYTES,
+	NSS_WIFI_EXT_VDEV_STATS_NODE_TX_PKTS,
+	NSS_WIFI_EXT_VDEV_STATS_NODE_TX_BYTES,
+	NSS_WIFI_EXT_VDEV_STATS_NODE_TOTAL_DROPPED,
+	NSS_WIFI_EXT_VDEV_STATS_MULTICAST_COUNT,
+	NSS_WIFI_EXT_VDEV_STATS_UNICAST_COUNT,
+	NSS_WIFI_EXT_VDEV_STATS_NEXT_HOP_DROP_COUNT,
+	NSS_WIFI_EXT_VDEV_STATS_MAX,
+};
+
+/*
+ * WiFi extendev vap debug statistics.
+ */
+struct nss_wifi_ext_vdev_debug {
+	uint64_t stats[NSS_WIFI_EXT_VDEV_STATS_MAX];
+	int32_t if_index;					/**< Netdevice's ifindex. */
+	uint32_t if_num;					/**< NSS interface number. */
+	bool valid;						/**< Is node valid ? */
+};
+
+/*
+ * Data structures to store WiFi extended VAP debug stats.
+ */
+extern struct nss_wifi_ext_vdev_debug nss_wifi_ext_vdev_debug_stats[NSS_WIFI_EXT_VDEV_MAX];
+
+/*
+ * WiFi extendev vap statistics APIs
+ */
+extern void nss_wifi_ext_vdev_stats_register(uint32_t if_num, struct net_device *netdev);
+extern void nss_wifi_ext_vdev_stats_unregister(uint32_t if_num, struct net_device *netdev);
+extern void nss_wifi_ext_vdev_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_wifi_ext_vdev_stats *stats_msg, uint16_t if_num);
+extern void nss_wifi_ext_vdev_stats_dentry_create(void);
+
+#endif /* __NSS_WIFI_EXT_VDEV_STATS_H */
diff --git a/qca-nss-drv/nss_wifi_log.c b/qca-nss-drv/nss_wifi_log.c
new file mode 100644
index 0000000..4d6b4c5
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_log.c
@@ -0,0 +1,806 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_wifi_log.c
+ *	NSS WIFI logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_wifi_log_message_types_str
+ *	WIFI message strings
+ */
+static int8_t *nss_wifi_log_message_types_str[NSS_WIFI_MAX_MSG] __maybe_unused = {
+	"WIFI INIT MSG",
+	"WIFI POST RECV MSG",
+	"WIFI HTT INIT MSG",
+	"WIFI TX INIT MSG",
+	"WIFI RAW SEND MSG",
+	"WIFI MGMT SEND MSG",
+	"WIFI WDS PEER ADD MSG",
+	"WIFI WDS PEER DEL MSG",
+	"WIFI STOP MSG",
+	"WIFI RESET MSG",
+	"WIFI STATS MSG",
+	"WIFI PEER FREELIST APPEND MSG",
+	"WIFI RX REORDER ARRAY FREELIST APPEND MSG",
+	"WIFI SEND PEER MEMORY REQUEST MSG",
+	"WIFI SEND RRA MEMORY REQUEST MSG",
+	"WIFI FW STATS MSG",
+	"WIFI MONITOR FILTER SET MSG",
+	"WIFI PEER BS STATE MSG",
+	"WIFI MSDU TTL SET MSG",
+	"WIFI RX VOW EXTSTATS SET MSG",
+	"WIFI PKTLOG CFG MSG",
+	"WIFI ENABLE PERPKT TXSTATS MSG",
+	"WIFI IGMP MLD TOS OVERRIDE MSG",
+	"WIFI OL STATS CFG MSG",
+	"WIFI OL STATS MSG",
+	"WIFI TX QUEUE CFG MSG",
+	"WIFI TX MIN THRESHOLD CFG MSG",
+	"WIFI DBDC PROCESS ENABLE MSG",
+	"WIFI PRIMARY RADIO SET MSG",
+	"WIFI FORCE CLIENT MCAST TRAFFIC SET MSG",
+	"WIFI STORE OTHER PDEV STAVAP MSG",
+	"WIFI STA KICKOUT MSG",
+	"WIFI WNM PEER RX ACTIVITY MSG",
+	"WIFI PEER STATS MSG",
+	"WIFI WDS VENDOR MSG",
+	"WIFI TX CAPTURE SET MSG",
+	"WIFI ALWAYS PRIMARY SET MSG",
+	"WIFI FLUSH HTT CMD MSG",
+	"WIFI CMD MSG",
+	"WIFI ENABLE OL STATSV2 MSG",
+	"WIFI OL PEER TIME MSG",
+};
+
+/*
+ * nss_wifi_log_error_response_types_str
+ *	Strings for error types for WIFI messages
+ */
+static int8_t *nss_wifi_log_error_response_types_str[NSS_WIFI_EMSG_MAX] __maybe_unused = {
+	"WIFI NO ERROR",
+	"WIFI UNKNOWN MSG",
+	"WIFI MGMT DLEN",
+	"WIFI MGMT SEND",
+	"WIFI CE INIT FAIL",
+	"WIFI PDEV INIT FAIL",
+	"WIFI HTT INIT FAIL",
+	"WIFI PEER ADD",
+	"WIFI WIFI START FAIL",
+	"WIFI STATE NOT RESET",
+	"WIFI STATE NOT INIT DONE",
+	"WIFI STATE NULL CE HANDLE",
+	"WIFI STATE NOT CE READY",
+	"WIFI STATE NOT HTT READY",
+	"WIFI FW STATS DLEN",
+	"WIFI FW STATS SEND",
+	"WIFI STATE TX INIT FAILED",
+	"WIFI IGMP MLD TOS OVERRIDE CFG",
+	"WIFI PDEV INVALID",
+	"WIFI OTHER PDEV STAVAP INVALID",
+	"WIFI HTT SEND FAIL",
+	"WIFI CE RING INIT",
+	"WIFI NOTIFY CB",
+	"WIFI PEERID INVALID",
+	"WIFI PEER INVALID",
+	"WIFI UNKNOWN CMD"
+};
+
+/*
+ * nss_wifi_log_init_msg()
+ *	Log NSS WIFI Init message.
+ */
+static void nss_wifi_log_init_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_init_msg *nwim __maybe_unused = &ncm->msg.initmsg;
+
+	nss_trace("%px: NSS WIFI Init Message:\n"
+		"WIFI Radio ID: %d\n"
+		"WIFI PCI Memory Address: %x\n"
+		"WIFI Target Type: %d\n"
+		"WIFI MU MIMO Enhancement Enable Flag: %d\n"
+		"WIFI Transmit Copy Engine Source Ring:\n"
+		"\tNumber of Entries: %d\n"
+		"\tNumber of Entries Mask: %x\n"
+		"\tInitial Software Index: %d\n"
+		"\tInitial Write Index: %d\n"
+		"\tInitial Hardware Index: %d\n"
+		"\tPhysical Address: %x\n"
+		"\tVirtual Address: %x\n"
+		"WIFI Transmit Copy Engine Dest Ring:\n"
+		"\tNumber of Entries: %d\n"
+		"\tNumber of Entries Mask: %x\n"
+		"\tInitial Software Index: %d\n"
+		"\tInitial Write Index: %d\n"
+		"\tInitial Hardware Index: %d\n"
+		"\tPhysical Address: %x\n"
+		"\tVirtual Address: %x\n"
+		"WIFI Transmit Control Address of PCIe Bar: %x\n"
+		"WIFI Receive Copy Engine Source Ring:\n"
+		"\tNumber of Entries: %d\n"
+		"\tNumber of Entries Mask: %x\n"
+		"\tInitial Software Index: %d\n"
+		"\tInitial Write Index: %d\n"
+		"\tInitial Hardware Index: %d\n"
+		"\tPhysical Address: %x\n"
+		"\tVirtual Address: %x\n"
+		"WIFI Receive Copy Engine Dest Ring:\n"
+		"\tNumber of Entries: %d\n"
+		"\tNumber of Entries Mask: %x\n"
+		"\tInitial Software Index: %d\n"
+		"\tInitial Write Index: %d\n"
+		"\tInitial Hardware Index: %d\n"
+		"\tPhysical Address: %x\n"
+		"\tVirtual Address: %x\n"
+		"WIFI Receive Control Address of PCIe Bar: %x\n"
+		"WIFI Bypass Network Process: %d",
+		nwim, nwim->radio_id,
+		nwim->pci_mem, nwim->target_type,
+		nwim->mu_mimo_enhancement_en, nwim->ce_tx_state.src_ring.nentries,
+		nwim->ce_tx_state.src_ring.nentries_mask, nwim->ce_tx_state.src_ring.sw_index,
+		nwim->ce_tx_state.src_ring.write_index, nwim->ce_tx_state.src_ring.hw_index,
+		nwim->ce_tx_state.src_ring.base_addr_CE_space, nwim->ce_tx_state.src_ring.base_addr_owner_space,
+		nwim->ce_tx_state.dest_ring.nentries, nwim->ce_tx_state.dest_ring.nentries_mask,
+		nwim->ce_tx_state.dest_ring.sw_index, nwim->ce_tx_state.dest_ring.write_index,
+		nwim->ce_tx_state.dest_ring.hw_index, nwim->ce_tx_state.dest_ring.base_addr_CE_space,
+		nwim->ce_tx_state.dest_ring.base_addr_owner_space, nwim->ce_tx_state.ctrl_addr,
+		nwim->ce_rx_state.src_ring.nentries, nwim->ce_rx_state.src_ring.nentries_mask,
+		nwim->ce_rx_state.src_ring.sw_index, nwim->ce_rx_state.src_ring.write_index,
+		nwim->ce_rx_state.src_ring.hw_index, nwim->ce_rx_state.src_ring.base_addr_CE_space,
+		nwim->ce_rx_state.src_ring.base_addr_owner_space, nwim->ce_rx_state.dest_ring.nentries,
+		nwim->ce_rx_state.dest_ring.nentries_mask, nwim->ce_rx_state.dest_ring.sw_index,
+		nwim->ce_rx_state.dest_ring.write_index, nwim->ce_rx_state.dest_ring.hw_index,
+		nwim->ce_rx_state.dest_ring.base_addr_CE_space, nwim->ce_rx_state.dest_ring.base_addr_owner_space,
+		nwim->ce_rx_state.ctrl_addr, nwim->bypass_nw_process);
+}
+
+/*
+ * nss_wifi_log_stop_msg()
+ *	Log NSS WIFI Init message.
+ */
+static void nss_wifi_log_stop_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_stop_msg *nwsm __maybe_unused = &ncm->msg.stopmsg;
+	nss_trace("%px: NSS WIFI Init Message:\n"
+		"WIFI Radio ID: %d\n",
+		nwsm, nwsm->radio_id);
+}
+
+/*
+ * nss_wifi_log_reset_msg()
+ *	Log NSS WIFI Init message.
+ */
+static void nss_wifi_log_reset_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_reset_msg *nwrm __maybe_unused = &ncm->msg.resetmsg;
+	nss_trace("%px: NSS WIFI Init Message:\n"
+		"WIFI Radio ID: %d\n",
+		nwrm, nwrm->radio_id);
+}
+
+/*
+ * nss_wifi_log_htt_init_msg()
+ *	Log NSS WIFI HTT Init message.
+ */
+static void nss_wifi_log_htt_init_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_htt_init_msg *nwim __maybe_unused = &ncm->msg.httinitmsg;
+	nss_trace("%px: NSS WIFI HTT Init Message:\n"
+		"WIFI Radio ID: %d\n"
+		"WIFI Ring Size: %d\n"
+		"WIFI Fill Level: %d\n"
+		"WIFI MAC Hardware Ring Phy Address: %x\n"
+		"WIFI MAC Hardware Ring Virtual Address: %x\n"
+		"WIFI Hardware Ring Index Phy Address: %x\n"
+		"WIFI Hardware Ring Index Virtual Address: %x\n",
+		nwim, nwim->radio_id,
+		nwim->ringsize, nwim->fill_level,
+		nwim->paddrs_ringptr, nwim->paddrs_ringpaddr,
+		nwim->alloc_idx_paddr, nwim->alloc_idx_vaddr);
+}
+
+/*
+ * nss_wifi_log_tx_init_msg()
+ *	Log NSS TX HTT Init message.
+ */
+static void nss_wifi_log_tx_init_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_tx_init_msg *nwim __maybe_unused = &ncm->msg.pdevtxinitmsg;
+	nss_trace("%px: NSS WIFI HTT Init Message:\n"
+		"WIFI Radio ID: %d\n"
+		"WIFI Number of Descriptor Pools Allocated: %d\n"
+		"WIFI TX Descriptor Array: %x\n"
+		"WIFI MAC extenstion descriptor Address: %x\n"
+		"WIFI WLAN MAC extenstion descriptor size: %d\n"
+		"WIFI HTT Tx descriptor memory start virtual address: %x\n"
+		"WIFI HTT Tx descriptor memory base virtual address: %x\n"
+		"WIFI HTT Tx descriptor memory offset: %x\n"
+		"WIFI Firmware shared TID map: %x\n",
+		nwim, nwim->radio_id,
+		nwim->desc_pool_size, nwim->tx_desc_array,
+		nwim->wlanextdesc_addr, nwim->wlanextdesc_size,
+		nwim->htt_tx_desc_base_vaddr, nwim->htt_tx_desc_base_paddr,
+		nwim->htt_tx_desc_offset, nwim->pmap_addr);
+}
+
+/*
+ * nss_wifi_log_rawsend_msg()
+ *	Log NSS WIFI RAW Send message.
+ */
+static void nss_wifi_log_rawsend_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_rawsend_msg *nwrm __maybe_unused = &ncm->msg.rawmsg;
+	nss_trace("%px: NSS WIFI RAW Send Message:\n"
+		"WIFI Radio ID: %d\n"
+		"WIFI Size of Raw Data: %d\n"
+		"WIFI Raw Data: %px",
+		nwrm, nwrm->radio_id,
+		nwrm->len, nwrm->array);
+}
+
+/*
+ * nss_wifi_log_mgmtsend_msg()
+ *	Log NSS WIFI Management Send message.
+ */
+static void nss_wifi_log_mgmtsend_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_mgmtsend_msg *nwmm __maybe_unused = &ncm->msg.mgmtmsg;
+	nss_trace("%px: NSS WIFI Management Send Message:\n"
+		"WIFI Descriptor ID: %d\n"
+		"WIFI Size of Management Data: %d\n"
+		"WIFI Management Data: %px",
+		nwmm, nwmm->desc_id,
+		nwmm->len, nwmm->array);
+}
+
+/*
+ * nss_wifi_log_wds_peer_msg()
+ *	Log NSS WIFI WDS Peer message.
+ */
+static void nss_wifi_log_wds_peer_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_wds_peer_msg *nwmm __maybe_unused = &ncm->msg.pdevwdspeermsg;
+	nss_trace("%px: NSS WIFI WDS Peer Message:\n"
+		"WIFI Dest MAC: %pM\n"
+		"WIFI Peer MAC: %pM\n",
+		nwmm, nwmm->dest_mac,
+		nwmm->peer_mac);
+}
+
+/*
+ * nss_wifi_log_peer_freelist_append_msg()
+ *	Log NSS WIFI Create/Append Freelist message
+ */
+static void nss_wifi_log_peer_freelist_append_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_peer_freelist_append_msg *nwpm __maybe_unused = &ncm->msg.peer_freelist_append;
+	nss_trace("%px: NSS WIFI Create/Append Freelist Message:\n"
+		"WIFI Starting Address of Peer Freelist Pool: %x\n"
+		"WIFI Length of freelist pool: %d\n"
+		"WIFI Number of Peers supported in freelist pool: %d\n",
+		nwpm, nwpm->addr,
+		nwpm->length, nwpm->num_peers);
+}
+
+/*
+ * nss_wifi_log_rx_reorder_array_freelist_append_msg()
+ *	Log NSS WIFI RX Reorder Array Freelist message
+ */
+static void nss_wifi_log_rx_reorder_array_freelist_append_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_rx_reorder_array_freelist_append_msg *nwpm __maybe_unused = &ncm->msg.rx_reorder_array_freelist_append;
+	nss_trace("%px: NSS WIFI RX Reorder Array Freelist Message:\n"
+		"WIFI Starting Address of TIDQ Freelist Pool: %x\n"
+		"WIFI Length of TIDQ freelist pool: %d\n"
+		"WIFI Number of Rx reorder array entries supported in freelist pool: %d\n",
+		nwpm, nwpm->addr,
+		nwpm->length, nwpm->num_rra);
+}
+
+/*
+ * nss_wifi_log_set_filter_msg()
+ *	Log NSS WIFI Set Filter message
+ */
+static void nss_wifi_log_set_filter_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_monitor_set_filter_msg *nwfm __maybe_unused = &ncm->msg.monitor_filter_msg;
+	nss_trace("%px: NSS WIFI Set Filter Message:\n"
+		"WIFI Filter Type: %dn",
+		nwfm, nwfm->filter_type);
+}
+
+/*
+ * nss_wifi_log_peer_activity_msg()
+ *	Log NSS WIFI Get Active Peer for Radio message
+ */
+static void nss_wifi_log_peer_activity_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_bs_peer_activity *nwpm __maybe_unused = &ncm->msg.peer_activity;
+	nss_trace("%px: NSS WIFI Get Active Peer Message:\n"
+		"WIFI Number of Entries in Peer ID Array: %d\n"
+		"WIFI PEER ID: %d\n",
+		nwpm, nwpm->nentries,
+		nwpm->peer_id[0]);
+}
+
+/*
+ * nss_wifi_rx_vow_extstats_set_msg()
+ *	Log NSS WIFI VoW Extended Statistics Set Message.
+ */
+static void nss_wifi_log_rx_vow_extstats_set_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_rx_vow_extstats_set_msg *nwpm __maybe_unused = &ncm->msg.vow_extstats_msg;
+	nss_trace("%px: NSS WIFI VoW Extended Statistics Set Message:\n"
+		"WIFI VoW Extended Statistics Enable:: %d\n",
+		nwpm, nwpm->vow_extstats_en);
+}
+
+/*
+ * nss_wifi_log_pktlog_cfg_msg()
+ *	Log NSS WIFI Packet Log Configuration Message.
+ */
+static void nss_wifi_log_pktlog_cfg_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_pktlog_cfg_msg *nwpm __maybe_unused = &ncm->msg.pcm_msg;
+	nss_trace("%px: NSS WIFI Packet Log Configuration Message:\n"
+		"WIFI Packet Log Enable: %d\n"
+		"WIFI PAcket Log buffer Size: %d\n"
+		"WIFI Size of packet log header: %d\n"
+		"WIFI Offset for the MSDU ID: %d\n",
+		nwpm, nwpm->enable,
+		nwpm->bufsize, nwpm->hdrsize,
+		nwpm->msdu_id_offset);
+}
+
+/*
+ * nss_wifi_log_enable_perpkt_txstats_msg()
+ *	Log NSS WIFI Enable TX Stats Message.
+ */
+static void nss_wifi_log_enable_perpkt_txstats_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_enable_perpkt_txstats_msg *nwpm __maybe_unused = &ncm->msg.ept_msg;
+	nss_trace("%px: NSS WIFI Enable TX Stats Message:\n"
+		"WIFI TX Stats Enable Flag: %d\n",
+		nwpm, nwpm->perpkt_txstats_flag);
+}
+
+/*
+ * nss_wifi_log_override_tos_msg()
+ *	Log NSS WIFI Override TOS Message.
+ */
+static void nss_wifi_log_override_tos_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_igmp_mld_override_tos_msg *nwpm __maybe_unused = &ncm->msg.wigmpmldtm_msg;
+	nss_trace("%px: NSS WIFI Override TOS Message:\n"
+		"WIFI enable TID override Flag: %d\n"
+		"WIFI Value of TID to be overriden: %d\n",
+		nwpm, nwpm->igmp_mld_ovride_tid_en,
+		nwpm->igmp_mld_ovride_tid_val);
+}
+
+/*
+ * nss_wifi_log_ol_stats_cfg_msg()
+ *	Log NSS WIFI Offload Stats Config Message.
+ */
+static void nss_wifi_log_ol_stats_cfg_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_ol_stats_cfg_msg *nwpm __maybe_unused = &ncm->msg.scm_msg;
+	nss_trace("%px: NSS WIFI Enable/Disable Offload Stats Message:\n"
+		"WIFI enable/disable offload stats config: %d\n",
+		nwpm, nwpm->stats_cfg);
+}
+
+/*
+ * nss_wifi_log_tx_queue_cfg_msg()
+ *	Log NSS WIFI TX Queue Configuration message.
+ */
+static void nss_wifi_log_tx_queue_cfg_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_tx_queue_cfg_msg *nwpm __maybe_unused = &ncm->msg.wtxqcm;
+	nss_trace("%px: NSS WIFI TX Queue Config Message:\n"
+		"WIFI TX Queue Size: %d\n"
+		"WIFI TX Queue Range: %d\n",
+		nwpm, nwpm->size, nwpm->range);
+}
+
+/*
+ * nss_wifi_log_tx_min_threshold_cfg()
+ *	Log NSS WIFI TX Queue Min Threshold Configuration message.
+ */
+static void nss_wifi_log_tx_min_threshold_cfg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_tx_min_threshold_cfg_msg *nwpm __maybe_unused = &ncm->msg.wtx_min_threshold_cm;
+	nss_trace("%px: NSS WIFI TX Queue Min Threshold Config Message:\n"
+		"WIFI TX Queue Min Threshold Value: %d\n",
+		nwpm, nwpm->min_threshold);
+}
+
+/*
+ * nss_wifi_log_dbdc_process_enable_msg()
+ *	Log NSS WIFI DBDC repeater process configuration.
+ */
+static void nss_wifi_log_dbdc_process_enable_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_dbdc_process_enable_msg *nwpm __maybe_unused = &ncm->msg.dbdcpe_msg;
+	nss_trace("%px: NSS WIFI DBDC repeater process configuration:\n"
+		"WIFI DBDC Process Enable Flag: %d\n",
+		nwpm, nwpm->dbdc_process_enable);
+}
+
+/*
+ * nss_wifi_log_primary_radio_set_msg()
+ *	Log NSS WIFI Primary Radio Set message.
+ */
+static void nss_wifi_log_primary_radio_set_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_primary_radio_set_msg *nwpm __maybe_unused = &ncm->msg.wprs_msg;
+	nss_trace("%px: NSS WIFI Primary Radio Set Message:\n"
+		"WIFI Current Radio as Primary Radio Enable/Disable Flag: %d\n",
+		nwpm, nwpm->flag);
+}
+
+/*
+ * nss_wifi_log_force_client_mcast_traffic_set_msg()
+ *	Log NSS WIFI Force Multicat Traffic for Radio
+ */
+static void nss_wifi_log_force_client_mcast_traffic_set_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_force_client_mcast_traffic_set_msg *nwpm __maybe_unused = &ncm->msg.wfcmts_msg;
+	nss_trace("%px: NSS WIFI Force Multicat Traffic for Radio Message:\n"
+		"WIFI Radio Multicast Traffic Flag: %d\n",
+		nwpm, nwpm->flag);
+}
+
+/*
+ * nss_wifi_log_store_other_pdev_stavap_msg()
+ *	Log NSS WIFI Store Other Radio Station VAP Message.
+ */
+static void nss_wifi_log_store_other_pdev_stavap_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_store_other_pdev_stavap_msg *nwpm __maybe_unused = &ncm->msg.wsops_msg;
+	nss_trace("%px: NSS WIFI Store Other Radio Station VAP Message:\n"
+		"WIFI Station VAP Interface Number: %d\n",
+		nwpm, nwpm->stavap_ifnum);
+}
+
+/*
+ * nss_wifi_log_sta_kickout_msg()
+ *	Log NSS WIFI Station Kickout Message.
+ */
+static void nss_wifi_log_sta_kickout_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_sta_kickout_msg *nwpm __maybe_unused = &ncm->msg.sta_kickout_msg;
+	nss_trace("%px: NSS WIFI Station Kickout Message:\n"
+		"WIFI PEER ID: %d\n",
+		nwpm, nwpm->peer_id);
+}
+
+/*
+ * nss_wifi_log_wnm_peer_rx_activity()
+ *	Log NSS WIFI RX Active State Information of Peer.
+ */
+static void nss_wifi_log_wnm_peer_rx_activity(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_wnm_peer_rx_activity_msg *nwpm __maybe_unused = &ncm->msg.wprm;
+	nss_trace("%px: NSS WIFI RX Active State Information of Peer:\n"
+		"WIFI Peer ID: %px\n"
+		"WIFI Number of Entries: %d\n",
+		nwpm, nwpm->peer_id, nwpm->nentries);
+}
+
+/*
+ * nss_wifi_log_wds_extn_peer_cfg_msg()
+ *	Log NSS WIFI WDS Extension Enabled Configuraion Message.
+ */
+static void nss_wifi_log_wds_extn_peer_cfg_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_wds_extn_peer_cfg_msg *nwpm __maybe_unused = &ncm->msg.wpeercfg;
+	nss_trace("%px: NSS WIFI Extension Enabled Configuraion Message:\n"
+		"WIFI Peer MAC Address: %pM\n"
+		"WIFI WDS Flags: %d\n"
+		"WIFI Peer ID: %d\n",
+		nwpm, nwpm->mac_addr, nwpm->wds_flags,
+		nwpm->peer_id);
+}
+
+/*
+ * nss_wifi_log_tx_capture_msg()
+ *	Log NSS WIFI Enable TX Capture Message.
+ */
+static void nss_wifi_log_tx_capture_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_tx_capture_msg *nwpm __maybe_unused = &ncm->msg.tx_capture_msg;
+	nss_trace("%px: NSS WIFI Enable TX Capture Message:\n"
+		"WIFI TX Capture Enable Flag: %d\n",
+		nwpm, nwpm->tx_capture_enable);
+}
+
+/*
+ * nss_wifi_log_always_primary_set_msg()
+ *	Log NSS WIFI Always Set Current Radio Primary Message.
+ */
+static void nss_wifi_log_always_primary_set_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_always_primary_set_msg *nwpm __maybe_unused = &ncm->msg.waps_msg;
+	nss_trace("%px: NSS WIFI Always Set Current Radio Primary Message:\n"
+		"WIFI Always Set Flag: %d\n",
+		nwpm, nwpm->flag);
+}
+
+/*
+ * nss_wifi_log_cmd_msg()
+ *	Log NSS WIFI PDEV Command Message.
+ */
+static void nss_wifi_log_cmd_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_cmd_msg *nwpm __maybe_unused = &ncm->msg.wcmdm;
+	nss_trace("%px: NSS WIFI PDEV Command Message:\n"
+		"WIFI Type of Command: %d\n"
+		"WIFI Value of Command: %d\n",
+		nwpm, nwpm->cmd, nwpm->value);
+}
+
+/*
+ * nss_wifi_log_enable_ol_statsv2_msg()
+ *	Log NSS WIFI Enable Version 2 of TX/RX Stats
+ */
+static void nss_wifi_log_enable_ol_statsv2_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_enable_ol_statsv2 *nwpm __maybe_unused = &ncm->msg.wesh_msg;
+	nss_trace("%px: NSS WIFI Enable Version 2 of TX/RX Stats:\n"
+		"WIFI Enable Version 2 Stats: %d\n",
+		nwpm, nwpm->enable_ol_statsv2);
+}
+
+/*
+ * nss_wifi_log_enable_ol_peer_time_msg()
+ *	Log NSS WIFI Enable Per Peer Stats to Host
+ */
+static void nss_wifi_log_enable_ol_peer_time_msg(struct nss_wifi_msg *ncm)
+{
+	struct nss_wifi_ol_peer_time_msg *nwpm __maybe_unused = &ncm->msg.wopt_msg;
+	int32_t i;
+
+	nss_trace("%px: NSS WIFI Enable Per PEer Stats to Host:\n"
+		"WIFI Number of Peers: %d\n"
+		"WIFI Peed ID: %d\n",
+		nwpm, nwpm->npeers,
+		nwpm->tstats[0].peer_id);
+	/*
+	 * Continuation of the log.
+	 */
+	nss_trace("WIFI TX Timestamp:\n");
+	nss_trace("\tSum of sojourn for each packet:");
+	for (i = 0; i < NSS_WIFI_TX_NUM_TOS_TIDS; i++) {
+		nss_trace("\t\t%d = %x", i, nwpm->tstats[0].sum[i].sum_tx);
+	}
+	nss_trace("\tNumber of MSDU per peer per TID:");
+	for (i = 0; i < NSS_WIFI_TX_NUM_TOS_TIDS; i++) {
+		nss_trace("\t\t%d = %x", i, nwpm->tstats[0].sum[i].sum_msdus);
+	}
+	nss_trace("WIFI Exponential Weighted Average:");
+	for (i = 0; i < NSS_WIFI_TX_NUM_TOS_TIDS; i++) {
+		nss_trace("\t%d = %d", i, nwpm->tstats[0].avg[i]);
+	}
+}
+
+/*
+ * nss_wifi_log_verbose()
+ *	Log message contents.
+ */
+static void nss_wifi_log_verbose(struct nss_wifi_msg *ncm)
+{
+	switch (ncm->cm.type) {
+	case NSS_WIFI_INIT_MSG:
+		nss_wifi_log_init_msg(ncm);
+		break;
+
+	case NSS_WIFI_HTT_INIT_MSG:
+		nss_wifi_log_htt_init_msg(ncm);
+		break;
+
+	case NSS_WIFI_TX_INIT_MSG:
+		nss_wifi_log_tx_init_msg(ncm);
+		break;
+
+	case NSS_WIFI_RAW_SEND_MSG:
+		nss_wifi_log_rawsend_msg(ncm);
+		break;
+
+	case NSS_WIFI_MGMT_SEND_MSG:
+		nss_wifi_log_mgmtsend_msg(ncm);
+		break;
+
+	case NSS_WIFI_WDS_PEER_ADD_MSG:
+		nss_wifi_log_wds_peer_msg(ncm);
+		break;
+
+	case NSS_WIFI_WDS_PEER_DEL_MSG:
+		nss_wifi_log_wds_peer_msg(ncm);
+		break;
+
+	case NSS_WIFI_STOP_MSG:
+		nss_wifi_log_stop_msg(ncm);
+		break;
+
+	case NSS_WIFI_RESET_MSG:
+		nss_wifi_log_reset_msg(ncm);
+		break;
+
+	case NSS_WIFI_PEER_FREELIST_APPEND_MSG:
+		nss_wifi_log_peer_freelist_append_msg(ncm);
+		break;
+
+	case NSS_WIFI_RX_REORDER_ARRAY_FREELIST_APPEND_MSG:
+		nss_wifi_log_rx_reorder_array_freelist_append_msg(ncm);
+		break;
+
+	case NSS_WIFI_MONITOR_FILTER_SET_MSG:
+		nss_wifi_log_set_filter_msg(ncm);
+		break;
+
+	case NSS_WIFI_PEER_BS_STATE_MSG:
+		nss_wifi_log_peer_activity_msg(ncm);
+		break;
+
+	case NSS_WIFI_RX_VOW_EXTSTATS_SET_MSG:
+		nss_wifi_log_rx_vow_extstats_set_msg(ncm);
+		break;
+
+	case NSS_WIFI_PKTLOG_CFG_MSG:
+		nss_wifi_log_pktlog_cfg_msg(ncm);
+		break;
+
+	case NSS_WIFI_ENABLE_PERPKT_TXSTATS_MSG:
+		nss_wifi_log_enable_perpkt_txstats_msg(ncm);
+		break;
+
+	case NSS_WIFI_IGMP_MLD_TOS_OVERRIDE_MSG:
+		nss_wifi_log_override_tos_msg(ncm);
+		break;
+
+	case NSS_WIFI_OL_STATS_CFG_MSG:
+		nss_wifi_log_ol_stats_cfg_msg(ncm);
+		break;
+
+	case NSS_WIFI_TX_QUEUE_CFG_MSG:
+		nss_wifi_log_tx_queue_cfg_msg(ncm);
+		break;
+
+	case NSS_WIFI_TX_MIN_THRESHOLD_CFG_MSG:
+		nss_wifi_log_tx_min_threshold_cfg(ncm);
+		break;
+
+	case NSS_WIFI_DBDC_PROCESS_ENABLE_MSG:
+		nss_wifi_log_dbdc_process_enable_msg(ncm);
+		break;
+
+	case NSS_WIFI_PRIMARY_RADIO_SET_MSG:
+		nss_wifi_log_primary_radio_set_msg(ncm);
+		break;
+
+	case NSS_WIFI_FORCE_CLIENT_MCAST_TRAFFIC_SET_MSG:
+		nss_wifi_log_force_client_mcast_traffic_set_msg(ncm);
+		break;
+
+	case NSS_WIFI_STORE_OTHER_PDEV_STAVAP_MSG:
+		nss_wifi_log_store_other_pdev_stavap_msg(ncm);
+		break;
+
+	case NSS_WIFI_STA_KICKOUT_MSG:
+		nss_wifi_log_sta_kickout_msg(ncm);
+		break;
+
+	case NSS_WIFI_WNM_PEER_RX_ACTIVITY_MSG:
+		nss_wifi_log_wnm_peer_rx_activity(ncm);
+		break;
+
+	case NSS_WIFI_WDS_VENDOR_MSG:
+		nss_wifi_log_wds_extn_peer_cfg_msg(ncm);
+		break;
+
+	case NSS_WIFI_TX_CAPTURE_SET_MSG:
+		nss_wifi_log_tx_capture_msg(ncm);
+		break;
+
+	case NSS_WIFI_ALWAYS_PRIMARY_SET_MSG:
+		nss_wifi_log_always_primary_set_msg(ncm);
+		break;
+
+	case NSS_WIFI_CMD_MSG:
+		nss_wifi_log_cmd_msg(ncm);
+		break;
+
+	case NSS_WIFI_ENABLE_OL_STATSV2_MSG:
+		nss_wifi_log_enable_ol_statsv2_msg(ncm);
+		break;
+
+	case NSS_WIFI_OL_PEER_TIME_MSG:
+		nss_wifi_log_enable_ol_peer_time_msg(ncm);
+		break;
+
+	case NSS_WIFI_FLUSH_HTT_CMD_MSG:
+	case NSS_WIFI_OL_STATS_MSG:
+	case NSS_WIFI_MSDU_TTL_SET_MSG:
+	case NSS_WIFI_PEER_STATS_MSG:
+	case NSS_WIFI_FW_STATS_MSG:
+	case NSS_WIFI_SEND_RRA_MEMORY_REQUEST_MSG:
+	case NSS_WIFI_STATS_MSG:
+	case NSS_WIFI_POST_RECV_MSG:
+	case NSS_WIFI_SEND_PEER_MEMORY_REQUEST_MSG:
+		/*
+		 * No log for these valid messages.
+		 */
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", ncm);
+		break;
+	}
+}
+
+/*
+ * nss_wifi_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_wifi_log_tx_msg(struct nss_wifi_msg *ncm)
+{
+	if (ncm->cm.type >= NSS_WIFI_MAX_MSG) {
+		nss_warning("%px: Invalid message type\n", ncm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", ncm, ncm->cm.type, nss_wifi_log_message_types_str[ncm->cm.type]);
+	nss_wifi_log_verbose(ncm);
+}
+
+/*
+ * nss_wifi_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_wifi_log_rx_msg(struct nss_wifi_msg *ncm)
+{
+	if (ncm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", ncm);
+		return;
+	}
+
+	if (ncm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (ncm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", ncm, ncm->cm.type,
+			nss_wifi_log_message_types_str[ncm->cm.type],
+			ncm->cm.response, nss_cmn_response_str[ncm->cm.response]);
+		goto verbose;
+	}
+
+	if (ncm->cm.error >= NSS_WIFI_EMSG_MAX) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			ncm, ncm->cm.type, nss_wifi_log_message_types_str[ncm->cm.type],
+			ncm->cm.response, nss_cmn_response_str[ncm->cm.response],
+			ncm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		ncm, ncm->cm.type, nss_wifi_log_message_types_str[ncm->cm.type],
+		ncm->cm.response, nss_cmn_response_str[ncm->cm.response],
+		ncm->cm.error, nss_wifi_log_error_response_types_str[ncm->cm.error]);
+
+verbose:
+	nss_wifi_log_verbose(ncm);
+}
diff --git a/qca-nss-drv/nss_wifi_log.h b/qca-nss-drv/nss_wifi_log.h
new file mode 100644
index 0000000..c47a62b
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_WIFI_LOG_H__
+#define __NSS_WIFI_LOG_H__
+
+/*
+ * nss_WIFI_log.h
+ *	NSS WIFI Log Header File
+ */
+
+/*
+ * nss_WIFI_log_tx_msg
+ *	Logs a WIFI message that is sent to the NSS firmware.
+ */
+void nss_wifi_log_tx_msg(struct nss_wifi_msg *ncm);
+
+/*
+ * nss_WIFI_log_rx_msg
+ *	Logs a WIFI message that is received from the NSS firmware.
+ */
+void nss_wifi_log_rx_msg(struct nss_wifi_msg *ncm);
+
+#endif /* __NSS_WIFI_LOG_H__ */
diff --git a/qca-nss-drv/nss_wifi_mac_db.c b/qca-nss-drv/nss_wifi_mac_db.c
new file mode 100644
index 0000000..5fb825a
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_mac_db.c
@@ -0,0 +1,215 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_wifi_mac_db_if.h"
+
+/*
+ * Compile time assertion.
+ */
+#define NSS_WIFI_MAC_DB_COMPILE_TIME_ASSERT(assertion_name, predicate) \
+    typedef char assertion_name[(predicate) ? 1 : -1]
+
+#define NSS_WIFI_MAC_DB_TX_TIMEOUT 1000 /* Millisecond to jiffies*/
+
+/*
+ * Validate the Wi-Fi MAC database message size not exceeding buffer size.
+ */
+NSS_WIFI_MAC_DB_COMPILE_TIME_ASSERT(NSS_WIFI_MAC_DB_MAX_BUF_MSG,
+		(sizeof(struct nss_wifi_mac_db_msg) < NSS_NBUF_PAYLOAD_SIZE));
+
+/*
+ * nss_wifi_mac_db_get_context()
+ */
+struct nss_ctx_instance *nss_wifi_mac_db_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wmdb_handler_id];
+}
+EXPORT_SYMBOL(nss_wifi_mac_db_get_context);
+
+/*
+ * nss_wifi_mac_db_pvt
+ *	Private data structure
+ */
+static struct nss_wifi_mac_db_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+	void *cb;
+	void *app_data;
+} wifi_mac_db_pvt;
+
+/*
+ * nss_wifi_mac_db_handler()
+ *	Handle NSS -> HLOS messages for wifi_mac_db
+ */
+static void nss_wifi_mac_db_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_wifi_mac_db_msg *ntm = (struct nss_wifi_mac_db_msg *)ncm;
+	void *ctx;
+	nss_wifi_mac_db_msg_callback_t cb;
+
+	nss_info("%px: NSS->HLOS message for wifi_mac_db\n", nss_ctx);
+
+	/*
+	 * The interface number shall be wifi_mac_db soc interface or wifi_mac_db radio interface
+	 */
+	BUG_ON((ncm->interface != NSS_WIFI_MAC_DB_INTERFACE));
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_WIFI_MAC_DB_MAX_MSG) {
+		nss_warning("%px: Received invalid message %d for wifi_mac_db interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_wifi_mac_db_msg)) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Update the callback and app_data for notify messages, wifi_mac_db sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->wifi_mac_db_msg_callback;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		nss_info("%px: cb null for wifi_mac_db interface %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	/*
+	 * Get callback & context
+	 */
+	cb = (nss_wifi_mac_db_msg_callback_t)ncm->cb;
+	ctx = nss_ctx->subsys_dp_register[ncm->interface].ndev;
+
+	/*
+	 * call wifi_mac_db msg callback
+	 */
+	if (!ctx) {
+		nss_warning("%px: Event received for wifi_mac_db interface %d before registration", nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb(ctx, ntm);
+}
+
+/*
+ * nss_wifi_mac_db_tx_msg
+ *	Transmit a wifi_mac_db message to NSS FW
+ *
+ * NOTE: The caller is expected to handle synchronous wait for message
+ * response if needed.
+ */
+nss_tx_status_t nss_wifi_mac_db_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_wifi_mac_db_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	if (ncm->type >= NSS_WIFI_MAC_DB_MAX_MSG) {
+		nss_warning("%px: wifi_mac_db message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * The interface number shall be one of the wifi_mac_db soc interfaces
+	 */
+	if ((ncm->interface != NSS_WIFI_MAC_DB_INTERFACE)) {
+		nss_warning("%px: tx request for interface that is not a wifi_mac_db: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_wifi_mac_db_tx_msg);
+
+/*
+ ****************************************
+ * Register/Unregister/Miscellaneous APIs
+ ****************************************
+ */
+
+/*
+ * nss_register_wifi_mac_db_if()
+ *	Register wifi_mac_db with nss driver
+ */
+struct nss_ctx_instance *nss_register_wifi_mac_db_if(uint32_t if_num, nss_wifi_mac_db_callback_t wifi_mac_db_callback,
+			nss_wifi_mac_db_callback_t wifi_mac_db_ext_callback,
+			nss_wifi_mac_db_msg_callback_t event_callback, struct net_device *netdev, uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wmdb_handler_id];
+
+	/*
+	 * The interface number shall be wifi_mac_db interface
+	 */
+	nss_assert(if_num == NSS_WIFI_MAC_DB_INTERFACE);
+
+	nss_info("%px: nss_register_wifi_mac_db_if if_num:%d wifi_mac_db_dev:%px", nss_ctx, if_num, netdev);
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, wifi_mac_db_callback, NULL, NULL, netdev, features);
+
+	nss_top_main.wifi_mac_db_msg_callback = event_callback;
+
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wmdb_handler_id];
+}
+EXPORT_SYMBOL(nss_register_wifi_mac_db_if);
+
+/*
+ * nss_unregister_wifi_mac_db_if()
+ *	Unregister wifi_mac_db with nss driver
+ */
+void nss_unregister_wifi_mac_db_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wmdb_handler_id];
+
+	/*
+	 * The interface number shall be wifi_mac_db interface
+	 */
+	nss_assert(if_num == NSS_WIFI_MAC_DB_INTERFACE);
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_unregister_wifi_mac_db_if);
+
+/*
+ * nss_wifi_mac_db_register_handler()
+ *	Register handle for notfication messages received on wifi mac db
+ */
+void nss_wifi_mac_db_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx =
+		(struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wmdb_handler_id];
+
+	nss_info("wifi_mac_db_register_handler");
+	nss_core_register_handler(nss_ctx, NSS_WIFI_MAC_DB_INTERFACE, nss_wifi_mac_db_handler, NULL);
+
+	sema_init(&wifi_mac_db_pvt.sem, 1);
+	init_completion(&wifi_mac_db_pvt.complete);
+}
diff --git a/qca-nss-drv/nss_wifi_mesh.c b/qca-nss-drv/nss_wifi_mesh.c
new file mode 100644
index 0000000..d4a6c0a
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_mesh.c
@@ -0,0 +1,242 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_core.h"
+#include "nss_cmn.h"
+#include "nss_wifi_mesh.h"
+#include "nss_wifi_mesh_log.h"
+#include "nss_wifi_mesh_strings.h"
+
+/*
+ * nss_wifi_mesh_verify_if_num()
+ *	Verify interface number.
+ */
+bool nss_wifi_mesh_verify_if_num(nss_if_num_t if_num)
+{
+	enum nss_dynamic_interface_type if_type = nss_dynamic_interface_get_type(nss_wifi_mesh_get_context(), if_num);
+
+	return ((if_type == NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER) ||
+				(if_type == NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER));
+}
+EXPORT_SYMBOL(nss_wifi_mesh_verify_if_num);
+
+/* nss_wifi_mesh_handler()
+ *	Handles Wi-Fi mesh messages from NSS to HLOS.
+ */
+static void nss_wifi_mesh_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, void *app_data)
+{
+	nss_wifi_mesh_msg_callback_t cb;
+	struct nss_wifi_mesh_msg *nwmm = (struct nss_wifi_mesh_msg *)ncm;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	nss_assert(nss_is_dynamic_interface(ncm->interface));
+	nss_assert(nss_wifi_mesh_verify_if_num(ncm->interface));
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_WIFI_MESH_MSG_MAX) {
+		nss_warning("%px: Received invalid message %d for wifi_mesh interface\n", nss_ctx, ncm->type);
+		return;
+	}
+
+
+	/*
+	 * For variable array the size of the common length will be greater the nss_wifi_mesh_msg
+	 * length. Add conditional checking for messages where length check will fail.
+	 */
+	if ((nss_cmn_get_msg_len(ncm) > sizeof(struct nss_wifi_mesh_msg)) &&
+		(ncm->type != NSS_WIFI_MESH_MSG_PATH_TABLE_DUMP) &&
+		(ncm->type != NSS_WIFI_MESH_MSG_PROXY_PATH_TABLE_DUMP)) {
+			nss_warning("%px: Length of message is greater than expected, type: %d, len: %d",
+			    		nss_ctx, ncm->type, ncm->len);
+		return;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Trace Messages
+	 */
+	nss_wifi_mesh_log_rx_msg(nwmm);
+
+	/*
+	 * Update the stats and send statistics notifications to the registered modules.
+	 */
+	if (nwmm->cm.type == NSS_WIFI_MESH_MSG_STATS_SYNC) {
+		nss_wifi_mesh_update_stats(ncm->interface, &nwmm->msg.stats_sync_msg);
+		nss_wifi_mesh_stats_notify(ncm->interface, nss_ctx->id);
+	}
+
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)app_data;
+	}
+
+	if (!ncm->cb) {
+		return;
+	}
+
+	cb = (nss_wifi_mesh_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, ncm);
+}
+
+/*
+ * nss_wifi_mesh_msg_init()
+ * 	Initiliaze a Wi-Fi mesh message.
+ */
+void nss_wifi_mesh_msg_init(struct nss_wifi_mesh_msg *nwm, nss_if_num_t if_num, uint32_t type, uint32_t len,
+			nss_wifi_mesh_msg_callback_t cb, void *app_data)
+{
+	nss_assert(nss_wifi_mesh_verify_if_num(if_num));
+	nss_cmn_msg_init(&nwm->cm, if_num, type, len, cb, app_data);
+}
+EXPORT_SYMBOL(nss_wifi_mesh_msg_init);
+
+/*
+ * nss_wifi_mesh_tx_buf
+ * 	Send data packet for vap processing asynchronously.
+ */
+nss_tx_status_t nss_wifi_mesh_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, nss_if_num_t if_num)
+{
+	nss_assert(nss_is_dynamic_interface(if_num));
+	return nss_core_send_packet(nss_ctx, os_buf, if_num, H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+EXPORT_SYMBOL(nss_wifi_mesh_tx_buf);
+
+/*
+ * nss_wifi_mesh_tx_msg
+ *	Transmit a Wi-Fi mesh message to the NSS firmware asynchronously.
+ *
+ * NOTE: The caller is expected to handle synchronous waiting for message
+ * response if needed.
+ */
+nss_tx_status_t nss_wifi_mesh_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_wifi_mesh_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (ncm->type >= NSS_WIFI_MESH_MSG_MAX) {
+		nss_warning("%px: wifi_mesh message type out of range: %d\n", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * Log messages.
+	 */
+	nss_wifi_mesh_log_tx_msg(msg);
+
+	/*
+	 * The interface number shall be one of the Wi-Fi mesh socket interfaces.
+	 */
+	nss_assert(nss_is_dynamic_interface(ncm->interface));
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_wifi_mesh_tx_msg);
+
+/*
+ ****************************************
+ * Register/Unregister/Miscellaneous APIs
+ ****************************************
+ */
+
+/*
+ * nss_wifi_mesh_get_context()
+ *	Return the core ctx which the feature is on.
+ */
+struct nss_ctx_instance *nss_wifi_mesh_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wifi_handler_id];
+}
+EXPORT_SYMBOL(nss_wifi_mesh_get_context);
+
+/*
+ * nss_unregister_wifi_mesh_if()
+ *	Unregister Wi-Fi mesh from the NSS driver.
+ */
+void nss_unregister_wifi_mesh_if(nss_if_num_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = nss_wifi_mesh_get_context();
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+	nss_core_unregister_msg_handler(nss_ctx, if_num);
+	nss_core_unregister_handler(nss_ctx, if_num);
+	nss_wifi_mesh_stats_handle_free(if_num);
+}
+EXPORT_SYMBOL(nss_unregister_wifi_mesh_if);
+
+/*
+ * nss_register_wifi_mesh_if()
+ *	Register wifi_mesh with nss driver.
+ */
+uint32_t nss_register_wifi_mesh_if(nss_if_num_t if_num,
+				   nss_wifi_mesh_data_callback_t  mesh_data_callback,
+				   nss_wifi_mesh_ext_data_callback_t mesh_ext_data_callback,
+				   nss_wifi_mesh_msg_callback_t mesh_event_callback,
+				   uint32_t dp_type, struct net_device *netdev, uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx = nss_wifi_mesh_get_context();
+	uint32_t status;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	nss_assert(netdev);
+	nss_assert(nss_wifi_mesh_verify_if_num(if_num));
+
+	if (!nss_wifi_mesh_stats_handle_alloc(if_num, netdev->ifindex)) {
+		nss_warning("%px: couldn't allocate stats handle for device name: %s, if_num: 0x%x\n", nss_ctx, netdev->name, if_num);
+		return NSS_CORE_STATUS_FAILURE;
+	}
+
+	nss_core_register_handler(nss_ctx, if_num, nss_wifi_mesh_handler, netdev);
+
+	status = nss_core_register_msg_handler(nss_ctx, if_num, mesh_event_callback);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to register event handler for interface(%u)\n", nss_ctx, if_num);
+		nss_core_unregister_handler(nss_ctx, if_num);
+		nss_wifi_mesh_stats_handle_free(if_num);
+		return status;
+	}
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, mesh_data_callback, mesh_ext_data_callback, NULL, netdev, features);
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num, dp_type);
+	return NSS_CORE_STATUS_SUCCESS;
+}
+EXPORT_SYMBOL(nss_register_wifi_mesh_if);
+
+/*
+ * nss_wifi_mesh_init()
+ *	Initialize the mesh stats dentries.
+ */
+void nss_wifi_mesh_init(void)
+{
+	if (!nss_wifi_mesh_strings_dentry_create()) {
+		nss_warning("Unable to create dentry for Wi-Fi mesh strings\n");
+	}
+
+	if (!nss_wifi_mesh_stats_dentry_create()) {
+		nss_warning("Unable to create dentry for Wi-Fi mesh stats\n");
+	}
+}
diff --git a/qca-nss-drv/nss_wifi_mesh_log.c b/qca-nss-drv/nss_wifi_mesh_log.c
new file mode 100644
index 0000000..bf9ddc6
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_mesh_log.c
@@ -0,0 +1,368 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_wifi_mesh_log.c
+ *	NSS WiFi Mesh logger file.
+ */
+
+#include "nss_core.h"
+#include "nss_wifi_mesh.h"
+
+#define NSS_WIFI_MESH_LOG_MESSAGE_TYPE_INDEX(type) ((type) - NSS_IF_MAX_MSG_TYPES)
+
+/*
+ * nss_wifi_mesh_log_message_types_str
+ *	NSS Wi-Fi mesh message strings.
+ */
+static uint8_t *nss_wifi_mesh_log_message_types_str[NSS_WIFI_MESH_LOG_MESSAGE_TYPE_INDEX(NSS_WIFI_MESH_MSG_MAX)] __maybe_unused = {
+	"WiFi Mesh configure",
+	"WiFi Mesh configure Mpath Add",
+	"WiFi Mesh configure Mpath Delete",
+	"WiFi Mesh configure Mpath Update",
+	"WiFi Mesh configure Proxy Learn",
+	"WiFi Mesh configure Proxy Add",
+	"WiFi Mesh configure Proxy Update",
+	"WiFi Mesh configure Proxy Delete",
+	"WiFi Mesh configure Mpath Not Found",
+	"WiFi Mesh configure Refresh"
+	"WiFi Mesh configure Mpath Table Dump",
+	"WiFi Mesh configure Proxy Path Table Dump",
+	"WiFi Mesh configure Assoc Link Vap",
+	"WiFi Mesh configure Exception Message",
+	"WiFi Mesh configure Stats Sync"
+};
+
+/*
+ * nss_wifi_mesh_log_configure_msg()
+ *	Log a NSS Wi-Fi mesh interface configure message.
+ */
+static void nss_wifi_mesh_log_configure_if_msg(struct nss_wifi_mesh_msg *nwmm)
+{
+	struct nss_wifi_mesh_config_msg *cmsg __maybe_unused = &nwmm->msg.mesh_config;
+	nss_trace("%px: WiFi Mesh configure message\n"
+		"Local Mac address: %pM\n"
+		"TTL: %d\n"
+		"Mesh Path Refresh Time: %d\n"
+		"Mpp Learning Mode: %d\n"
+		"Block Mesh Forwarding: %d\n"
+		"Configs Flags: 0x%x\n",
+		cmsg, cmsg->local_mac_addr, cmsg->ttl,
+		cmsg->mesh_path_refresh_time,
+		cmsg->mpp_learning_mode,
+		cmsg->block_mesh_forwarding,
+		cmsg->config_flags);
+}
+
+/*
+ * nss_wifi_mesh_log_mpath_add_msg()
+ *	Log a NSS Wi-Fi mesh mpath add message.
+ */
+static void nss_wifi_mesh_log_mpath_add_msg(struct nss_wifi_mesh_msg *nwmm)
+{
+	struct nss_wifi_mesh_mpath_add_msg *mamsg __maybe_unused = &nwmm->msg.mpath_add;
+	nss_trace("%px: NSS WiFi Mesh Mpath add message:\n"
+		"Dest Mac address: %pM\n"
+		"Next Hop Mac address: %pM\n"
+		"Metric: %d\n"
+		"Expiry Time: %d\n"
+		"Hop Count: %d\n"
+		"Flags: 0x%x\n"
+		"Link Vap id: %d\n"
+		"Is Mesh Gate: %d\n",
+		mamsg, mamsg->dest_mac_addr, mamsg->next_hop_mac_addr,
+		mamsg->metric, mamsg->expiry_time, mamsg->hop_count,
+		mamsg->path_flags, mamsg->link_vap_id, mamsg->is_mesh_gate);
+}
+
+/*
+ * nss_wifi_mesh_log_mpath_delete_msg()
+ *	Log a NSS Wi-Fi mesh mpath delete message.
+ */
+static void nss_wifi_mesh_log_mpath_delete_msg(struct nss_wifi_mesh_msg *nwmm)
+{
+	struct nss_wifi_mesh_mpath_del_msg *mdmsg __maybe_unused = &nwmm->msg.mpath_del;
+	nss_trace("%px: NSS WiFi Mesh Mpath delete message:\n"
+		"Dest Mac Address: %pM\n"
+		"Link Vap id: %d\n"
+		"Next Hop Mac address: %pM\n",
+		mdmsg, mdmsg->mesh_dest_mac_addr, mdmsg->link_vap_id, mdmsg->next_hop_mac_addr);
+}
+
+/*
+ * nss_wifi_mesh_log_mpath_update_msg()
+ *	Log a NSS Wi-Fi mesh mpath update message.
+ */
+static void nss_wifi_mesh_log_mpath_update_msg(struct nss_wifi_mesh_msg *nwmm)
+{
+	struct nss_wifi_mesh_mpath_update_msg *mumsg __maybe_unused = &nwmm->msg.mpath_update;
+	nss_trace("%px: NSS WiFi Mesh Mpath update message:\n"
+		"Dest Mac address: %pM\n"
+		"Next Hop Mac address: %pM\n"
+		"Metric: %d\n"
+		"Expiry Time: %d\n"
+		"Hop Count: %d\n"
+		"Flags: 0x%x\n"
+		"Link Vap id: %d\n"
+		"Is Mesh Gate: %d\n"
+		"Update Flags: %d\n",
+		mumsg, mumsg->dest_mac_addr, mumsg->next_hop_mac_addr,
+		mumsg->metric, mumsg->expiry_time, mumsg->hop_count,
+		mumsg->path_flags, mumsg->link_vap_id, mumsg->is_mesh_gate,
+		mumsg->update_flags);
+}
+
+/*
+ * nss_wifi_mesh_log_proxy_path_learn_msg()
+ *	Log a NSS Wi-Fi mesh proxy path learn message.
+ */
+static void nss_wifi_mesh_log_proxy_path_learn_msg(struct nss_wifi_mesh_msg *nwmm)
+{
+	struct nss_wifi_mesh_proxy_path_learn_msg *pplm __maybe_unused = &nwmm->msg.proxy_learn_msg;
+	nss_trace("%px: NSS WiFi Mesh Proxy Path Learn message:\n"
+		"Mesh Dest Mac address: %pM\n"
+		"Destination Mac address: %pM\n"
+		"flags: 0x%x\n",
+		pplm, pplm->mesh_dest_mac, pplm->dest_mac_addr,
+		pplm->path_flags);
+}
+
+/*
+ * nss_wifi_mesh_log_proxy_path_add_msg()
+ *	Log a NSS Wi-Fi Mesh proxy path add message.
+ */
+static void nss_wifi_mesh_log_proxy_path_add_msg(struct nss_wifi_mesh_msg *nwmm)
+{
+	struct nss_wifi_mesh_proxy_path_add_msg *ppam __maybe_unused = &nwmm->msg.proxy_add_msg;
+	nss_trace("%px: NSS WiFi Mesh Proxy Path Add message:\n"
+		"Mesh Dest Mac address: %pM\n"
+		"Destination Mac address: %pM\n"
+		"flags: 0x%x\n",
+		ppam, ppam->mesh_dest_mac, ppam->dest_mac_addr,
+		ppam->path_flags);
+}
+
+/*
+ * nss_wifi_mesh_log_proxy_path_delete_msg()
+ *	Log a NSS Wi-Fi proxy path delete message.
+ */
+static void nss_wifi_mesh_log_proxy_path_delete_msg(struct nss_wifi_mesh_msg *nwmm)
+{
+	struct nss_wifi_mesh_proxy_path_del_msg *ppdm __maybe_unused = &nwmm->msg.proxy_del_msg;
+	nss_trace("%px: NSS WiFi Mesh Proxy Path Delete message:\n"
+		"Mesh Dest Mac address: %pM\n"
+		"Destination Mac address: %pM\n",
+		ppdm, ppdm->mesh_dest_mac_addr, ppdm->dest_mac_addr);
+}
+
+/*
+ * nss_wifi_mesh_log_proxy_path_update_msg()
+ *	Log a NSS Wi-Fi mesh proxy path update message.
+ */
+static void nss_wifi_mesh_log_proxy_path_update_msg(struct nss_wifi_mesh_msg *nwmm)
+{
+	struct nss_wifi_mesh_proxy_path_update_msg *ppum __maybe_unused = &nwmm->msg.proxy_update_msg;
+	nss_trace("%px: NSS WiFi Mesh Proxy Path Add message:\n"
+		"Mesh Dest Mac address: %pM\n"
+		"Destination Mac address: %pM\n"
+		"flags: 0x%x\n"
+		"Bitmap: %d\n",
+		ppum, ppum->mesh_dest_mac, ppum->dest_mac_addr,
+		ppum->path_flags, ppum->bitmap);
+}
+
+/*
+ * nss_wifi_mesh_log_mpath_not_found_msg()
+ *	Log a NSS Wi-Fi mesh mpath not found message.
+ */
+static void nss_wifi_mesh_log_mpath_not_found_msg(struct nss_wifi_mesh_msg *nwmm)
+{
+	struct nss_wifi_mesh_mpath_not_found_msg *mnfm __maybe_unused = &nwmm->msg.mpath_not_found_msg;
+	nss_trace("%px: NSS WiFi Mesh Mpath not found message:\n"
+		"Destination Mac address: %pM\n"
+		"Transmitter Mac address: %pM\n"
+		"Link Vap Id: %d\n"
+		"Is Mesh Forwarding Path: %d\n",
+		mnfm, mnfm->dest_mac_addr, mnfm->transmitter_mac_addr,
+		mnfm->link_vap_id, mnfm->is_mesh_forward_path);
+}
+
+/*
+ * nss_wifi_mesh_log_mpath_refresh_msg()
+ *	Log a NSS Wi-Fi mesh mpath refresh message.
+ */
+static void nss_wifi_mesh_log_mpath_refresh_msg(struct nss_wifi_mesh_msg *nwmm)
+{
+	struct nss_wifi_mesh_path_refresh_msg *mprm __maybe_unused = &nwmm->msg.path_refresh_msg;
+	nss_trace("%px: NSS WiFi Mesh Mpath refresh message:\n"
+		"Destination Mac address: %pM\n"
+		"Next Hop Mac address: %pM\n"
+		"Flags: 0x%x\n"
+		"Link Vap Id: %d\n",
+		mprm, mprm->dest_mac_addr, mprm->next_hop_mac_addr,
+		mprm->path_flags, mprm->link_vap_id);
+}
+
+/*
+ * nss_wifi_mesh_log_mpath_expiry_msg()
+ *	Log a NSS Wi-Fi mesh mpath expiry message.
+ */
+static void nss_wifi_mesh_log_mpath_expiry_msg(struct nss_wifi_mesh_msg *nwmm)
+{
+	struct nss_wifi_mesh_path_expiry_msg *mpem __maybe_unused = &nwmm->msg.path_expiry_msg;
+	nss_trace("%px: NSS WiFi Mesh Mpath expiry message:\n"
+		"Destination Mac address: %pM\n"
+		"Next Hop Mac address: %pM\n"
+		"Flags: 0x%x\n"
+		"Link Vap Id: %d\n",
+		mpem, mpem->mesh_dest_mac_addr, mpem->next_hop_mac_addr,
+		mpem->path_flags, mpem->link_vap_id);
+}
+
+/*
+ * nss_wifi_mesh_log_exception_flag_msg()
+ *	Log a NSS Wi-Fi mesh exception flag message.
+ */
+static void nss_wifi_mesh_log_exception_flag_msg(struct nss_wifi_mesh_msg *nwmm)
+{
+	struct nss_wifi_mesh_exception_flag_msg *efm __maybe_unused = &nwmm->msg.exception_msg;
+	nss_trace("%px: NSS WiFi Mesh Exception Flag message:\n"
+		"Destination Mac address: %pM\n",
+		efm, efm->dest_mac_addr);
+}
+
+/*
+ * nss_wifi_mesh_log_verbose()
+ *	Log message contents.
+ */
+static void nss_wifi_mesh_log_verbose(struct nss_wifi_mesh_msg *nwmm)
+{
+	switch (nwmm->cm.type) {
+	case NSS_WIFI_MESH_MSG_INTERFACE_CONFIGURE:
+		nss_wifi_mesh_log_configure_if_msg(nwmm);
+		break;
+
+	case NSS_WIFI_MESH_MSG_MPATH_ADD:
+		nss_wifi_mesh_log_mpath_add_msg(nwmm);
+		break;
+
+	case NSS_WIFI_MESH_MSG_MPATH_DELETE:
+		nss_wifi_mesh_log_mpath_delete_msg(nwmm);
+		break;
+
+	case NSS_WIFI_MESH_MSG_MPATH_UPDATE:
+		nss_wifi_mesh_log_mpath_update_msg(nwmm);
+		break;
+
+	case NSS_WIFI_MESH_MSG_PROXY_PATH_LEARN:
+		nss_wifi_mesh_log_proxy_path_learn_msg(nwmm);
+		break;
+
+	case NSS_WIFI_MESH_MSG_PROXY_PATH_ADD:
+		nss_wifi_mesh_log_proxy_path_add_msg(nwmm);
+		break;
+
+	case NSS_WIFI_MESH_MSG_PROXY_PATH_DELETE:
+		nss_wifi_mesh_log_proxy_path_delete_msg(nwmm);
+		break;
+
+	case NSS_WIFI_MESH_MSG_PROXY_PATH_UPDATE:
+		nss_wifi_mesh_log_proxy_path_update_msg(nwmm);
+		break;
+
+	case NSS_WIFI_MESH_MSG_PATH_NOT_FOUND:
+		nss_wifi_mesh_log_mpath_not_found_msg(nwmm);
+		break;
+
+	case NSS_WIFI_MESH_MSG_PATH_REFRESH:
+		nss_wifi_mesh_log_mpath_refresh_msg(nwmm);
+		break;
+
+	case NSS_WIFI_MESH_MSG_PATH_EXPIRY:
+		nss_wifi_mesh_log_mpath_expiry_msg(nwmm);
+		break;
+
+	case NSS_WIFI_MESH_MSG_PATH_TABLE_DUMP:
+		break;
+
+	case NSS_WIFI_MESH_MSG_PROXY_PATH_TABLE_DUMP:
+		break;
+
+	case NSS_WIFI_MESH_MSG_STATS_SYNC:
+		break;
+
+	case NSS_WIFI_MESH_MSG_EXCEPTION_FLAG:
+		nss_wifi_mesh_log_exception_flag_msg(nwmm);
+		break;
+
+	default:
+		nss_trace("%px: Invalid message, type: %d\n", nwmm, nwmm->cm.type);
+		break;
+	}
+}
+
+/*
+ * nss_wifi_mesh_log_tx_msg()
+ *	Log messages transmitted to firmware.
+ */
+void nss_wifi_mesh_log_tx_msg(struct nss_wifi_mesh_msg *nwmm)
+{
+	uint32_t index;
+	if ((nwmm->cm.type >= NSS_WIFI_MESH_MSG_MAX) || (nwmm->cm.type <= NSS_IF_MAX_MSG_TYPES)) {
+		nss_warning("%px: Invalid message, type: %d\n", nwmm, nwmm->cm.type);
+		return;
+	}
+
+	index = NSS_WIFI_MESH_LOG_MESSAGE_TYPE_INDEX(nwmm->cm.type);
+
+	nss_info("%px: type[%d]:%s\n", nwmm, nwmm->cm.type, nss_wifi_mesh_log_message_types_str[index - 1]);
+	nss_wifi_mesh_log_verbose(nwmm);
+}
+
+/*
+ * nss_wifi_mesh_log_rx_msg()
+ *	Log messages received from firmware.
+ */
+void nss_wifi_mesh_log_rx_msg(struct nss_wifi_mesh_msg *nwmm)
+{
+	uint32_t index;
+	if (nwmm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response, message type: %d\n", nwmm, nwmm->cm.type);
+		return;
+	}
+
+	if (nwmm->cm.type <= NSS_IF_MAX_MSG_TYPES) {
+		return;
+	}
+
+	index = NSS_WIFI_MESH_LOG_MESSAGE_TYPE_INDEX(nwmm->cm.type);
+
+	if (nwmm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nwmm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nwmm, nwmm->cm.type,
+			nss_wifi_mesh_log_message_types_str[index - 1],
+			nwmm->cm.response, nss_cmn_response_str[nwmm->cm.response]);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s\n",
+		nwmm, nwmm->cm.type, nss_wifi_mesh_log_message_types_str[index - 1],
+		nwmm->cm.response, nss_cmn_response_str[nwmm->cm.response]);
+
+verbose:
+	nss_wifi_mesh_log_verbose(nwmm);
+}
diff --git a/qca-nss-drv/nss_wifi_mesh_log.h b/qca-nss-drv/nss_wifi_mesh_log.h
new file mode 100644
index 0000000..a6c5436
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_mesh_log.h
@@ -0,0 +1,34 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_WIFI_MESH_LOG_H
+#define __NSS_WIFI_MESH_LOG_H
+
+/*
+ * nss_wifi_mesh_log_tx_msg
+ *	Logs a Wi-Fi mesh message that was sent to the NSS firmware.
+ */
+void nss_wifi_mesh_log_tx_msg(struct nss_wifi_mesh_msg *nwmm);
+
+/*
+ * nss_wifi_mesh_log_rx_msg
+ *	Logs a Wi-Fi mesh message that was received from the NSS firmware.
+ */
+void nss_wifi_mesh_log_rx_msg(struct nss_wifi_mesh_msg *nwmm);
+
+#endif /* __NSS_WIFI_MESH_LOG_H */
diff --git a/qca-nss-drv/nss_wifi_mesh_stats.c b/qca-nss-drv/nss_wifi_mesh_stats.c
new file mode 100644
index 0000000..d9695e4
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_mesh_stats.c
@@ -0,0 +1,662 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_tx_rx_common.h"
+#include "nss_wifi_mesh.h"
+#include "nss_wifi_mesh_stats.h"
+#include "nss_wifi_mesh_strings.h"
+
+#define NSS_WIFI_MESH_OUTER_STATS 0
+#define NSS_WIFI_MESH_INNER_STATS 1
+#define NSS_WIFI_MESH_PATH_STATS 2
+#define NSS_WIFI_MESH_PROXY_PATH_STATS 3
+#define NSS_WIFI_MESH_EXCEPTION_STATS 4
+
+/*
+ * Wi-Fi mesh stats dentry file size.
+ */
+#define NSS_WIFI_MESH_DENTRY_FILE_SIZE 19
+
+/*
+ * Spinlock for protecting tunnel operations colliding with a tunnel destroy
+ */
+static DEFINE_SPINLOCK(nss_wifi_mesh_stats_lock);
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+static ATOMIC_NOTIFIER_HEAD(nss_wifi_mesh_stats_notifier);
+
+/*
+ * Declare an array of Wi-Fi mesh stats handle.
+ */
+struct nss_wifi_mesh_stats_handle *nss_wifi_mesh_stats_hdl[NSS_WIFI_MESH_MAX_DYNAMIC_INTERFACE];
+
+/*
+ * nss_wifi_mesh_max_statistics()
+ * 	Wi-Fi mesh maximum statistics.
+ */
+static uint32_t nss_wifi_mesh_max_statistics(void)
+{
+	uint32_t max1;
+	uint32_t exception_stats_max = NSS_WIFI_MESH_EXCEPTION_STATS_TYPE_MAX;
+	uint32_t encap_stats_max = NSS_WIFI_MESH_ENCAP_STATS_TYPE_MAX;
+	uint32_t decap_stats_max = NSS_WIFI_MESH_DECAP_STATS_TYPE_MAX;
+	uint32_t path_stats_max = NSS_WIFI_MESH_PATH_STATS_TYPE_MAX;
+	uint32_t proxy_path_stats_max = NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_MAX;
+
+	max1 = max(max(encap_stats_max, decap_stats_max), max(path_stats_max, proxy_path_stats_max));
+
+	return (max(max1, exception_stats_max));
+}
+
+/*
+ * nss_wifi_mesh_stats_handle_alloc()
+ *	Allocate Wi-Fi mesh tunnel instance
+ */
+bool nss_wifi_mesh_stats_handle_alloc(nss_if_num_t if_num, int32_t ifindex)
+{
+	struct nss_wifi_mesh_stats_handle *h;
+	uint32_t idx;
+
+	/*
+	 * Allocate a handle
+	 */
+	h = kzalloc(sizeof(struct nss_wifi_mesh_stats_handle), GFP_ATOMIC);
+	if (!h) {
+		nss_warning("Failed to allocate memory for Wi-Fi mesh instance for interface : 0x%x\n", if_num);
+		return false;
+	}
+
+	spin_lock(&nss_wifi_mesh_stats_lock);
+	for (idx = 0; idx < NSS_WIFI_MESH_MAX_DYNAMIC_INTERFACE; idx++) {
+		if (nss_wifi_mesh_stats_hdl[idx] && nss_wifi_mesh_stats_hdl[idx]->if_num == if_num) {
+			spin_unlock(&nss_wifi_mesh_stats_lock);
+			nss_warning("Already a handle present for this interface number: 0x%x\n", if_num);
+			kfree(h);
+			return false;
+		}
+	}
+
+	for (idx = 0; idx < NSS_WIFI_MESH_MAX_DYNAMIC_INTERFACE; idx++) {
+		if (nss_wifi_mesh_stats_hdl[idx]) {
+			continue;
+		}
+
+		h->if_num = if_num;
+		h->mesh_idx = idx;
+		h->ifindex = ifindex;
+		nss_wifi_mesh_stats_hdl[idx] = h;
+		spin_unlock(&nss_wifi_mesh_stats_lock);
+		return true;
+	}
+	spin_unlock(&nss_wifi_mesh_stats_lock);
+	nss_warning("No free index available for handle with ifnum: 0x%x\n", if_num);
+	kfree(h);
+	return false;
+}
+
+/*
+ * nss_wifi_mesh_stats_handle_free()
+ *	Free Wi-Fi mesh tunnel handle instance.
+ */
+bool nss_wifi_mesh_stats_handle_free(nss_if_num_t if_num)
+{
+	struct nss_wifi_mesh_stats_handle *h;
+
+	spin_lock(&nss_wifi_mesh_stats_lock);
+	h = nss_wifi_mesh_get_stats_handle(if_num);
+	if (!h) {
+		spin_unlock(&nss_wifi_mesh_stats_lock);
+		nss_warning("Unable to free Wi-Fi mesh stats handle instance for interface number: 0x%x\n", if_num);
+		return false;
+	}
+
+	nss_wifi_mesh_stats_hdl[h->mesh_idx] = NULL;
+	spin_unlock(&nss_wifi_mesh_stats_lock);
+	kfree(h);
+	return true;
+}
+
+/**
+ * nss_wifi_mesh_get_stats_handle()
+ * 	Get Wi-Fi mesh stats handle from interface number.
+ */
+struct nss_wifi_mesh_stats_handle *nss_wifi_mesh_get_stats_handle(nss_if_num_t if_num)
+{
+	uint32_t idx;
+
+	assert_spin_locked(&nss_wifi_mesh_stats_lock);
+
+	for (idx = 0; idx < NSS_WIFI_MESH_MAX_DYNAMIC_INTERFACE; idx++) {
+		if (nss_wifi_mesh_stats_hdl[idx]) {
+			if (nss_wifi_mesh_stats_hdl[idx]->if_num == if_num) {
+				struct nss_wifi_mesh_stats_handle *h = nss_wifi_mesh_stats_hdl[idx];
+				return h;
+			}
+		}
+	}
+	return NULL;
+}
+
+/*
+ * nss_wifi_mesh_get_stats()
+ *	API for getting stats from a Wi-Fi mesh interface stats
+ */
+static bool nss_wifi_mesh_get_stats(nss_if_num_t if_num, struct nss_wifi_mesh_hdl_stats_sync_msg *stats)
+{
+	struct nss_wifi_mesh_stats_handle *h;
+
+	if (!nss_wifi_mesh_verify_if_num(if_num)) {
+		return false;
+	}
+
+	spin_lock(&nss_wifi_mesh_stats_lock);
+	h = nss_wifi_mesh_get_stats_handle(if_num);
+	if (!h) {
+		spin_unlock(&nss_wifi_mesh_stats_lock);
+		nss_warning("Invalid Wi-Fi mesh stats handle for interface number: %d\n", if_num);
+		return false;
+	}
+
+	memcpy(stats, &h->stats, sizeof(*stats));
+	spin_unlock(&nss_wifi_mesh_stats_lock);
+	return true;
+}
+
+/*
+ * nss_wifi_mesh_get_valid_interface_count()
+ * 	Get count of valid Wi-Fi mesh interfaces up.
+ */
+static uint32_t nss_wifi_mesh_get_valid_interface_count(uint16_t type, uint32_t if_num, uint32_t max_if_num)
+{
+	uint32_t interface_count = 0;
+	enum nss_dynamic_interface_type dtype;
+
+	for (; if_num <= max_if_num; if_num++) {
+		if (!nss_is_dynamic_interface(if_num)) {
+			continue;
+		}
+
+		dtype = nss_dynamic_interface_get_type(nss_wifi_mesh_get_context(), if_num);
+
+		if ((type == NSS_WIFI_MESH_OUTER_STATS) && (dtype != NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER)) {
+			continue;
+		}
+
+		if ((type == NSS_WIFI_MESH_INNER_STATS) && (dtype != NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER)) {
+			continue;
+		}
+
+		if ((type == NSS_WIFI_MESH_PATH_STATS) && (dtype != NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER)) {
+			continue;
+		}
+
+		if ((type == NSS_WIFI_MESH_PROXY_PATH_STATS) && (dtype != NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER)) {
+			continue;
+		}
+		interface_count++;
+	}
+	return interface_count;
+}
+
+/**
+ * nss_wifi_mesh_stats_read()
+ * 	Read Wi-Fi Mesh stats.
+ */
+static ssize_t nss_wifi_mesh_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos, uint16_t type)
+{
+	uint32_t max_output_lines, max_stats;
+	size_t size_al, size_wr = 0;
+	ssize_t bytes_read = 0;
+	struct nss_stats_data *data = fp->private_data;
+	int ifindex;
+	uint32_t if_num = NSS_DYNAMIC_IF_START;
+	uint32_t interface_count = 0;
+	uint32_t max_if_num = NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES;
+	struct nss_wifi_mesh_hdl_stats_sync_msg *stats;
+	struct net_device *ndev;
+	struct nss_wifi_mesh_stats_handle *handle;
+	char *lbuf;
+	enum nss_dynamic_interface_type dtype;
+
+	if (data) {
+		if_num = data->if_num;
+	}
+
+	/*
+	 * If we are done accomodating all the Wi-Fi mesh interfaces.
+	 */
+	if (if_num > max_if_num) {
+		return 0;
+	}
+
+	/*
+	 * Get number of Wi-Fi mesh interfaces up.
+	 */
+	interface_count = nss_wifi_mesh_get_valid_interface_count(type, if_num, max_if_num);
+	if (!interface_count) {
+		nss_warning("%px: Invalid number of valid interface for if_num: 0x%x\n", data, if_num);
+		return 0;
+	}
+
+	/*
+	 * max output lines = #stats + Number of Extra outputlines for future reference to add new stats +
+	 * Maximum node stats + Maximum of all the stats + three blank lines.
+	 */
+	max_stats = nss_wifi_mesh_max_statistics();
+	max_output_lines = max_stats + NSS_STATS_NODE_MAX + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines * interface_count;
+
+	lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer\n");
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "wifi_mesh", NSS_STATS_SINGLE_CORE);
+
+	stats = kzalloc(sizeof(struct nss_wifi_mesh_hdl_stats_sync_msg), GFP_KERNEL);
+	if (!stats) {
+		nss_warning("%px: Failed to allocate stats memory for if_num: 0x%x\n", data, if_num);
+		kfree(lbuf);
+		return 0;
+	}
+
+	for (; if_num <= max_if_num; if_num++) {
+		bool ret;
+
+		if (!nss_is_dynamic_interface(if_num)) {
+			continue;
+		}
+
+		dtype = nss_dynamic_interface_get_type(nss_wifi_mesh_get_context(), if_num);
+
+		if ((type == NSS_WIFI_MESH_OUTER_STATS) && (dtype != NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER)) {
+			continue;
+		}
+
+		if ((type == NSS_WIFI_MESH_INNER_STATS) && (dtype != NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER)) {
+			continue;
+		}
+
+		if ((type == NSS_WIFI_MESH_PATH_STATS) && (dtype != NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER)) {
+			continue;
+		}
+
+		if ((type == NSS_WIFI_MESH_PROXY_PATH_STATS) && (dtype != NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER)) {
+			continue;
+		}
+
+		/*
+		 * If Wi-Fi mesh stats handle does not exists, then ret will be false.
+		 */
+		ret = nss_wifi_mesh_get_stats(if_num, stats);
+		if (!ret) {
+			continue;
+		}
+
+		spin_lock(&nss_wifi_mesh_stats_lock);
+		handle = nss_wifi_mesh_get_stats_handle(if_num);
+		if (!handle) {
+			spin_unlock(&nss_wifi_mesh_stats_lock);
+			nss_warning("Invalid Wi-Fi mesh stats handle, if_num: %d\n", if_num);
+			continue;
+		}
+		ifindex = handle->ifindex;
+		spin_unlock(&nss_wifi_mesh_stats_lock);
+
+		ndev = dev_get_by_index(&init_net, ifindex);
+		if (!ndev) {
+			continue;
+		}
+
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n%s if_num:%03u\n",
+				     ndev->name, if_num);
+		dev_put(ndev);
+
+		/*
+		 * Read encap stats, path stats, proxy path stats from inner node and decap stats from outer node.
+		 */
+		switch (type) {
+		case NSS_WIFI_MESH_INNER_STATS:
+			size_wr += nss_stats_print("wifi_mesh", "encap stats", NSS_STATS_SINGLE_INSTANCE
+					, nss_wifi_mesh_strings_encap_stats
+					, stats->encap_stats
+					, NSS_WIFI_MESH_ENCAP_STATS_TYPE_MAX
+					, lbuf, size_wr, size_al);
+			break;
+
+		case NSS_WIFI_MESH_PATH_STATS:
+			size_wr += nss_stats_print("wifi_mesh", "path stats", NSS_STATS_SINGLE_INSTANCE
+					, nss_wifi_mesh_strings_path_stats
+					, stats->path_stats
+					, NSS_WIFI_MESH_PATH_STATS_TYPE_MAX
+					, lbuf, size_wr, size_al);
+			break;
+
+		case NSS_WIFI_MESH_PROXY_PATH_STATS:
+			size_wr += nss_stats_print("wifi_mesh", "proxy path stats", NSS_STATS_SINGLE_INSTANCE
+					, nss_wifi_mesh_strings_proxy_path_stats
+					, stats->proxy_path_stats
+					, NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_MAX
+					, lbuf, size_wr, size_al);
+			break;
+
+		case NSS_WIFI_MESH_OUTER_STATS:
+			size_wr += nss_stats_print("wifi_mesh", "decap stats", NSS_STATS_SINGLE_INSTANCE
+					, nss_wifi_mesh_strings_decap_stats
+					, stats->decap_stats
+					, NSS_WIFI_MESH_DECAP_STATS_TYPE_MAX
+					, lbuf, size_wr, size_al);
+			break;
+
+		case NSS_WIFI_MESH_EXCEPTION_STATS:
+			size_wr += nss_stats_print("wifi_mesh", "exception stats", NSS_STATS_SINGLE_INSTANCE
+					, nss_wifi_mesh_strings_exception_stats
+					, stats->except_stats
+					, NSS_WIFI_MESH_EXCEPTION_STATS_TYPE_MAX
+					, lbuf, size_wr, size_al);
+			break;
+
+		default:
+			nss_warning("%px: Invalid stats type: %d\n", stats, type);
+			nss_assert(0);
+			kfree(stats);
+			kfree(lbuf);
+			return 0;
+		}
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, size_wr);
+	kfree(stats);
+	kfree(lbuf);
+	return bytes_read;
+}
+
+/**
+ * nss_wifi_mesh_decap_stats_read()
+ *	Read Wi-Fi Mesh decap stats.
+ */
+static ssize_t nss_wifi_mesh_decap_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_wifi_mesh_stats_read(fp, ubuf, sz, ppos, NSS_WIFI_MESH_OUTER_STATS);
+}
+
+/**
+ * nss_wifi_mesh_encap_stats_read()
+ *	Read Wi-Fi Mesh encap stats
+ */
+static ssize_t nss_wifi_mesh_encap_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_wifi_mesh_stats_read(fp, ubuf, sz, ppos, NSS_WIFI_MESH_INNER_STATS);
+}
+
+/**
+ * nss_wifi_mesh_path_stats_read()
+ *	Read Wi-Fi Mesh path stats
+ */
+static ssize_t nss_wifi_mesh_path_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_wifi_mesh_stats_read(fp, ubuf, sz, ppos, NSS_WIFI_MESH_PATH_STATS);
+}
+
+/**
+ * nss_wifi_mesh_proxy_path_stats_read()
+ *	Read Wi-Fi Mesh proxy path stats
+ */
+static ssize_t nss_wifi_mesh_proxy_path_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_wifi_mesh_stats_read(fp, ubuf, sz, ppos, NSS_WIFI_MESH_PROXY_PATH_STATS);
+}
+
+/**
+ * nss_wifi_mesh_exception_stats_read()
+ *	Read Wi-Fi Mesh exception stats
+ */
+static ssize_t nss_wifi_mesh_exception_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_wifi_mesh_stats_read(fp, ubuf, sz, ppos, NSS_WIFI_MESH_EXCEPTION_STATS);
+}
+
+/*
+ * nss_wifi_mesh_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(wifi_mesh_encap);
+NSS_STATS_DECLARE_FILE_OPERATIONS(wifi_mesh_decap);
+NSS_STATS_DECLARE_FILE_OPERATIONS(wifi_mesh_path);
+NSS_STATS_DECLARE_FILE_OPERATIONS(wifi_mesh_proxy_path);
+NSS_STATS_DECLARE_FILE_OPERATIONS(wifi_mesh_exception);
+
+/*
+ * nss_wifi_mesh_get_interface_type()
+ * 	Function to get the type of dynamic interface.
+ */
+static enum nss_dynamic_interface_type nss_wifi_mesh_get_interface_type(nss_if_num_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = &nss_top_main.nss[nss_top_main.wifi_handler_id];
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+	return nss_dynamic_interface_get_type(nss_ctx, if_num);
+}
+
+/*
+ * nss_wifi_mesh_update_stats()
+ *	Update stats for Wi-Fi mesh interface.
+ */
+void nss_wifi_mesh_update_stats(nss_if_num_t if_num, struct nss_wifi_mesh_stats_sync_msg *mstats)
+{
+	struct nss_wifi_mesh_stats_handle *handle;
+	struct nss_wifi_mesh_hdl_stats_sync_msg *stats;
+	enum nss_dynamic_interface_type type;
+	uint64_t *dst;
+	uint32_t *src;
+	int i;
+
+	spin_lock(&nss_wifi_mesh_stats_lock);
+	handle = nss_wifi_mesh_get_stats_handle(if_num);
+	if (!handle) {
+		spin_unlock(&nss_wifi_mesh_stats_lock);
+		nss_warning("Invalid Wi-Fi mesh stats handle, if_num: %d\n", if_num);
+		return;
+	}
+
+	type = nss_wifi_mesh_get_interface_type(handle->if_num);;
+	stats = &handle->stats;
+
+	switch (type) {
+	case NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_INNER:
+		/*
+		 * Update pnode Rx stats.
+		 */
+		stats->encap_stats[NSS_WIFI_MESH_ENCAP_STATS_TYPE_PNODE_RX_PACKETS] += mstats->pnode_stats.rx_packets;
+		stats->encap_stats[NSS_WIFI_MESH_ENCAP_STATS_TYPE_PNODE_RX_BYTES] += mstats->pnode_stats.rx_bytes;
+		stats->encap_stats[NSS_WIFI_MESH_ENCAP_STATS_TYPE_PNODE_RX_DROPPED] += nss_cmn_rx_dropped_sum(&mstats->pnode_stats);
+
+		/*
+		 * Update pnode Tx stats.
+		 */
+		stats->encap_stats[NSS_WIFI_MESH_ENCAP_STATS_TYPE_PNODE_TX_PACKETS] += mstats->pnode_stats.tx_packets;
+		stats->encap_stats[NSS_WIFI_MESH_ENCAP_STATS_TYPE_PNODE_TX_BYTES] += mstats->pnode_stats.tx_bytes;
+
+		/*
+		 * Update encap stats.
+		 */
+		dst = &stats->encap_stats[NSS_WIFI_MESH_ENCAP_STATS_TYPE_EXPIRY_NOTIFY_SENT];
+		src = &mstats->mesh_encap_stats.expiry_notify_sent;
+		for (i = NSS_WIFI_MESH_ENCAP_STATS_TYPE_EXPIRY_NOTIFY_SENT; i < NSS_WIFI_MESH_ENCAP_STATS_TYPE_MAX; i++) {
+			*dst++ += *src++;
+		}
+
+		/*
+		 * Update mesh path stats.
+		 */
+		dst = &stats->path_stats[NSS_WIFI_MESH_PATH_STATS_TYPE_ALLOC_FAILURES];
+		src = &mstats->mesh_path_stats.alloc_failures;
+		for (i = NSS_WIFI_MESH_PATH_STATS_TYPE_ALLOC_FAILURES; i < NSS_WIFI_MESH_PATH_STATS_TYPE_MAX; i++) {
+			*dst++ += *src++;
+		}
+
+		/*
+		 * Update mesh proxy path stats.
+		 */
+		dst = &stats->proxy_path_stats[NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_ALLOC_FAILURES];
+		src = &mstats->mesh_proxy_path_stats.alloc_failures;
+		for (i = NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_ALLOC_FAILURES; i < NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_MAX; i++) {
+			*dst++ += *src++;
+		}
+
+		/*
+		 * Update exception stats.
+		 */
+		dst = &stats->except_stats[NSS_WIFI_MESH_EXCEPTION_STATS_TYPE_PACKETS_SUCCESS];
+		src = &mstats->mesh_except_stats.packets_success;
+		for (i = NSS_WIFI_MESH_EXCEPTION_STATS_TYPE_PACKETS_SUCCESS; i < NSS_WIFI_MESH_EXCEPTION_STATS_TYPE_MAX; i++) {
+			*dst++ += *src++;
+		}
+		spin_unlock(&nss_wifi_mesh_stats_lock);
+		break;
+
+	case NSS_DYNAMIC_INTERFACE_TYPE_WIFI_MESH_OUTER:
+		/*
+		 * Update pnode Rx stats.
+		 */
+		stats->decap_stats[NSS_WIFI_MESH_DECAP_STATS_TYPE_PNODE_RX_PACKETS] += mstats->pnode_stats.rx_packets;
+		stats->decap_stats[NSS_WIFI_MESH_DECAP_STATS_TYPE_PNODE_RX_BYTES] += mstats->pnode_stats.rx_bytes;
+		stats->decap_stats[NSS_WIFI_MESH_DECAP_STATS_TYPE_PNODE_RX_DROPPED] += nss_cmn_rx_dropped_sum(&mstats->pnode_stats);
+
+		/*
+		 * Update pnode Tx stats.
+		 */
+		stats->decap_stats[NSS_WIFI_MESH_DECAP_STATS_TYPE_PNODE_TX_PACKETS] += mstats->pnode_stats.tx_packets;
+		stats->decap_stats[NSS_WIFI_MESH_DECAP_STATS_TYPE_PNODE_TX_BYTES] += mstats->pnode_stats.tx_bytes;
+
+		/*
+		 * Update decap stats.
+		 */
+		dst = &stats->decap_stats[NSS_WIFI_MESH_DECAP_STATS_TYPE_PATH_REFRESH_SENT];
+		src = &mstats->mesh_decap_stats.path_refresh_sent;
+		for (i = NSS_WIFI_MESH_DECAP_STATS_TYPE_PATH_REFRESH_SENT; i < NSS_WIFI_MESH_DECAP_STATS_TYPE_MAX; i++) {
+			*dst++ += *src++;
+		}
+		spin_unlock(&nss_wifi_mesh_stats_lock);
+		break;
+
+	default:
+		spin_unlock(&nss_wifi_mesh_stats_lock);
+		nss_warning("%px: Received invalid dynamic interface type: %d\n", handle, type);
+		nss_assert(0);
+	}
+}
+
+/*
+ * nss_wifi_mesh_stats_notify()
+ *	Sends notifications to the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_wifi_mesh_stats_notify(nss_if_num_t if_num, uint32_t core_id)
+{
+	struct nss_wifi_mesh_stats_notification wifi_mesh_stats;
+
+	if (!nss_wifi_mesh_get_stats(if_num, &wifi_mesh_stats.stats)) {
+		nss_warning("No handle is present with ifnum: 0x%x\n", if_num);
+		return;
+	}
+
+	wifi_mesh_stats.core_id = core_id;
+	wifi_mesh_stats.if_num = if_num;
+	atomic_notifier_call_chain(&nss_wifi_mesh_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)&wifi_mesh_stats);
+}
+
+/*
+ * nss_wifi_mesh_stats_dentry_create()
+ *	Create Wi-Fi Mesh statistics debug entry
+ */
+struct dentry *nss_wifi_mesh_stats_dentry_create(void)
+{
+	struct dentry *stats_dentry_dir;
+	struct dentry *stats_file;
+	char dir_name[NSS_WIFI_MESH_DENTRY_FILE_SIZE] = {0};
+
+	if (!nss_top_main.stats_dentry) {
+		nss_warning("qca-nss-drv/stats is not present\n");
+		return NULL;
+	}
+
+	snprintf(dir_name, sizeof(dir_name), "wifi_mesh");
+
+	stats_dentry_dir = debugfs_create_dir(dir_name,  nss_top_main.stats_dentry);
+	if (!stats_dentry_dir) {
+		nss_warning("Failed to create qca-nss-drv/stats/wifi_mesh directory\n");
+		return NULL;
+	}
+
+	stats_file = debugfs_create_file("encap_stats", 0400, stats_dentry_dir, &nss_top_main, &nss_wifi_mesh_encap_stats_ops);
+	if (!stats_file) {
+		nss_warning("Failed to create qca-nss-drv/stats/wifi_mesh/encap_stats file\n");
+		goto fail;
+	}
+
+	stats_file = debugfs_create_file("decap_stats", 0400, stats_dentry_dir, &nss_top_main, &nss_wifi_mesh_decap_stats_ops);
+	if (!stats_file) {
+		nss_warning("Failed to create qca-nss-drv/stats/wifi_mesh/decap_stats file\n");
+		goto fail;
+	}
+
+	stats_file = debugfs_create_file("path_stats", 0400, stats_dentry_dir, &nss_top_main, &nss_wifi_mesh_path_stats_ops);
+	if (!stats_file) {
+		nss_warning("Failed to create qca-nss-drv/stats/wifi_mesh/path_stats file\n");
+		goto fail;
+	}
+
+	stats_file = debugfs_create_file("proxy_path_stats", 0400, stats_dentry_dir, &nss_top_main, &nss_wifi_mesh_proxy_path_stats_ops);
+	if (!stats_file) {
+		nss_warning("Failed to create qca-nss-drv/stats/wifi_mesh/proxy_path_stats file\n");
+		goto fail;
+	}
+	stats_file = debugfs_create_file("exception_stats", 0400, stats_dentry_dir, &nss_top_main, &nss_wifi_mesh_exception_stats_ops);
+	if (!stats_file) {
+		nss_warning("Failed to create qca-nss-drv/stats/wifi_mesh/exception_stats file\n");
+		goto fail;
+	}
+	return stats_dentry_dir;
+fail:
+	debugfs_remove_recursive(stats_dentry_dir);
+	return NULL;
+}
+
+/**
+ * nss_wifi_mesh_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_wifi_mesh_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_wifi_mesh_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_wifi_mesh_stats_register_notifier);
+
+/**
+ * nss_wifi_mesh_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_wifi_mesh_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_wifi_mesh_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_wifi_mesh_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_wifi_mesh_stats.h b/qca-nss-drv/nss_wifi_mesh_stats.h
new file mode 100644
index 0000000..0e3a118
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_mesh_stats.h
@@ -0,0 +1,42 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_WIFI_MESH_STATS_H__
+#define __NSS_WIFI_MESH_STATS_H__
+
+/**
+ * Array of pointer for NSS Wi-Fi mesh handles.
+ * Each handle has per-tunnel statistics based on the interface number which is an index.
+ */
+struct nss_wifi_mesh_stats_handle {
+	nss_if_num_t if_num;				/**< Interface number. */
+	uint32_t ifindex;				/**< Netdev index. */
+	uint32_t mesh_idx;				/**< Mesh index.  */
+	struct nss_wifi_mesh_hdl_stats_sync_msg stats;	/**< Stats per-interface number. */
+};
+
+/*
+ * Wi-Fi Mesh statistics APIs
+ */
+extern void nss_wifi_mesh_update_stats(nss_if_num_t if_num, struct nss_wifi_mesh_stats_sync_msg *mstats);
+extern void nss_wifi_mesh_stats_notify(nss_if_num_t if_num, uint32_t core_id);
+extern struct dentry *nss_wifi_mesh_stats_dentry_create(void);
+extern struct nss_wifi_mesh_stats_handle *nss_wifi_mesh_get_stats_handle(nss_if_num_t if_num);
+extern bool nss_wifi_mesh_stats_handle_alloc(nss_if_num_t if_num, int32_t ifindex);
+extern bool nss_wifi_mesh_stats_handle_free(nss_if_num_t if_num);
+#endif /* __NSS_WIFI_MESH_STATS_H__ */
diff --git a/qca-nss-drv/nss_wifi_mesh_strings.c b/qca-nss-drv/nss_wifi_mesh_strings.c
new file mode 100644
index 0000000..25f6473
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_mesh_strings.c
@@ -0,0 +1,276 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include <nss_wifi_mesh.h>
+#include "nss_wifi_mesh_stats.h"
+#include "nss_strings.h"
+#include "nss_wifi_mesh_strings.h"
+
+/*
+ * nss_wifi_mesh_strings_encap_stats
+ *	Wi-Fi mesh encap statistics string.
+ */
+struct nss_stats_info nss_wifi_mesh_strings_encap_stats[NSS_WIFI_MESH_ENCAP_STATS_TYPE_MAX] = {
+	{"rx_packets",			NSS_STATS_TYPE_COMMON},
+	{"rx_bytes",			NSS_STATS_TYPE_COMMON},
+	{"tx_packets",			NSS_STATS_TYPE_COMMON},
+	{"tx_bytes",			NSS_STATS_TYPE_COMMON},
+	{"rx_dropped",			NSS_STATS_TYPE_COMMON},
+	{"expiry_notify_sent",		NSS_STATS_TYPE_SPECIAL},
+	{"mc_count",			NSS_STATS_TYPE_SPECIAL},
+	{"mp_not_found",		NSS_STATS_TYPE_SPECIAL},
+	{"mp_active",			NSS_STATS_TYPE_SPECIAL},
+	{"mpp_not_found",		NSS_STATS_TYPE_SPECIAL},
+	{"mpp_found",			NSS_STATS_TYPE_SPECIAL},
+	{"encap_hdr_fail",		NSS_STATS_TYPE_SPECIAL},
+	{"mp_del_notify_fail",		NSS_STATS_TYPE_SPECIAL},
+	{"link_enqueue",		NSS_STATS_TYPE_SPECIAL},
+	{"link_enq_fail",		NSS_STATS_TYPE_SPECIAL},
+	{"ra_lup_fail",			NSS_STATS_TYPE_SPECIAL},
+	{"dummy_add_count",		NSS_STATS_TYPE_SPECIAL},
+	{"encap_mp_add_notify_fail", 	NSS_STATS_TYPE_SPECIAL},
+	{"dummy_add_fail", 		NSS_STATS_TYPE_SPECIAL},
+	{"dummy_lup_fail", 		NSS_STATS_TYPE_SPECIAL},
+	{"send_to_host_failed",		NSS_STATS_TYPE_SPECIAL},
+	{"sent_to_host",		NSS_STATS_TYPE_SPECIAL},
+	{"expiry_notify_fail",		NSS_STATS_TYPE_SPECIAL},
+	{"no_headroom", 		NSS_STATS_TYPE_SPECIAL},
+	{"path_refresh_sent", 		NSS_STATS_TYPE_SPECIAL},
+	{"linearise_failed", 		NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_wifi_mesh_encap_strings_read()
+ *	Read Wi-Fi mesh encap statistics names.
+ */
+static ssize_t nss_wifi_mesh_encap_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_wifi_mesh_strings_encap_stats, NSS_WIFI_MESH_ENCAP_STATS_TYPE_MAX);
+}
+
+/*
+ * nss_wifi_mesh_strings_path_stats
+ * 	Wi-Fi mesh path statistics string.
+ */
+struct nss_stats_info nss_wifi_mesh_strings_path_stats[NSS_WIFI_MESH_PATH_STATS_TYPE_MAX] = {
+	{"alloc_failures",		NSS_STATS_TYPE_SPECIAL},
+	{"error_max_radio_count",	NSS_STATS_TYPE_SPECIAL},
+	{"invalid_interface_failures",	NSS_STATS_TYPE_SPECIAL},
+	{"add_success",			NSS_STATS_TYPE_SPECIAL},
+	{"table_full_errors",		NSS_STATS_TYPE_SPECIAL},
+	{"insert_failures",		NSS_STATS_TYPE_SPECIAL},
+	{"not_found",			NSS_STATS_TYPE_SPECIAL},
+	{"delete_success",		NSS_STATS_TYPE_SPECIAL},
+	{"update_success",		NSS_STATS_TYPE_SPECIAL},
+	{"mesh_path_expired",		NSS_STATS_TYPE_SPECIAL},
+	{"mesh_path_refresh_needed",	NSS_STATS_TYPE_SPECIAL},
+	{"add_requests",		NSS_STATS_TYPE_SPECIAL},
+	{"del_requests",		NSS_STATS_TYPE_SPECIAL},
+	{"update_requests",		NSS_STATS_TYPE_SPECIAL},
+	{"next_hop_updations",		NSS_STATS_TYPE_SPECIAL},
+	{"hop_count_updations",		NSS_STATS_TYPE_SPECIAL},
+	{"flag_updations",		NSS_STATS_TYPE_SPECIAL},
+	{"metric_updations",		NSS_STATS_TYPE_SPECIAL},
+	{"block_mesh_fwd_updations",	NSS_STATS_TYPE_SPECIAL},
+	{"delete_failures",		NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_wifi_mesh_path_strings_read()
+ *	Read Wi-Fi mesh path statistics names.
+ */
+static ssize_t nss_wifi_mesh_path_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_wifi_mesh_strings_path_stats, NSS_WIFI_MESH_PATH_STATS_TYPE_MAX);
+}
+
+/*
+ * nss_wifi_mesh_strings_proxy_path_stats
+ * 	Wi-Fi mesh proxy path statistics string.
+ */
+struct nss_stats_info nss_wifi_mesh_strings_proxy_path_stats[NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_MAX] = {
+	{"alloc_failures",		NSS_STATS_TYPE_SPECIAL},
+	{"entry_exist_failures",	NSS_STATS_TYPE_SPECIAL},
+	{"add_success",			NSS_STATS_TYPE_SPECIAL},
+	{"table_full_errors",		NSS_STATS_TYPE_SPECIAL},
+	{"insert_failures",		NSS_STATS_TYPE_SPECIAL},
+	{"not_found",			NSS_STATS_TYPE_SPECIAL},
+	{"unhashed_errors",		NSS_STATS_TYPE_SPECIAL},
+	{"delete_failures",		NSS_STATS_TYPE_SPECIAL},
+	{"delete_success",		NSS_STATS_TYPE_SPECIAL},
+	{"update_success",		NSS_STATS_TYPE_SPECIAL},
+	{"lookup_success",		NSS_STATS_TYPE_SPECIAL},
+	{"add_requests",		NSS_STATS_TYPE_SPECIAL},
+	{"del_requests",		NSS_STATS_TYPE_SPECIAL},
+	{"update_requests",		NSS_STATS_TYPE_SPECIAL},
+	{"mda_updations",		NSS_STATS_TYPE_SPECIAL},
+	{"flag_updations",		NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_wifi_mesh_proxy_path_strings_read()
+ *	Read Wi-Fi mesh proxy path statistics names.
+ */
+static ssize_t nss_wifi_mesh_proxy_path_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_wifi_mesh_strings_proxy_path_stats, NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_MAX);
+}
+
+/*
+ * nss_wifi_mesh_strings_decap_stats
+ *	Wi-Fi mesh decap statistics string.
+ */
+struct nss_stats_info nss_wifi_mesh_strings_decap_stats[NSS_WIFI_MESH_DECAP_STATS_TYPE_MAX] = {
+	{"rx_packets",			NSS_STATS_TYPE_COMMON},
+	{"rx_bytes",			NSS_STATS_TYPE_COMMON},
+	{"tx_packets",			NSS_STATS_TYPE_COMMON},
+	{"tx_bytes",			NSS_STATS_TYPE_COMMON},
+	{"rx_dropped",			NSS_STATS_TYPE_COMMON},
+	{"path_refresh_sent",		NSS_STATS_TYPE_SPECIAL},
+	{"reserved",			NSS_STATS_TYPE_SPECIAL},
+	{"mc_drop",			NSS_STATS_TYPE_DROP},
+	{"ttl_0",			NSS_STATS_TYPE_SPECIAL},
+	{"mpp_lup_fail",		NSS_STATS_TYPE_SPECIAL},
+	{"decap_hdr_fail",		NSS_STATS_TYPE_SPECIAL},
+	{"rx_fwd_fail",			NSS_STATS_TYPE_SPECIAL},
+	{"rx_fwd_success",		NSS_STATS_TYPE_SPECIAL},
+	{"mp_fwd_lookup_fail",		NSS_STATS_TYPE_SPECIAL},
+	{"mp_fwd_inactive",		NSS_STATS_TYPE_SPECIAL},
+	{"nxt_mnode_fwd_success",	NSS_STATS_TYPE_SPECIAL},
+	{"nxt_mnode_fwd_fail",		NSS_STATS_TYPE_SPECIAL},
+	{"mpp_add_fail",		NSS_STATS_TYPE_SPECIAL},
+	{"mpp_add_event2host_fail",	NSS_STATS_TYPE_SPECIAL},
+	{"mpp_upate_fail",		NSS_STATS_TYPE_SPECIAL},
+	{"mpp_update_even2host_fail", 	NSS_STATS_TYPE_SPECIAL},
+	{"mpp_learn2host_fail",		NSS_STATS_TYPE_SPECIAL},
+	{"block_mesh_fwd_packets",	NSS_STATS_TYPE_SPECIAL},
+	{"no_headroom",			NSS_STATS_TYPE_SPECIAL},
+	{"linearise_failed",		NSS_STATS_TYPE_SPECIAL},
+	{"mpp_learn_event_rl_dropped",	NSS_STATS_TYPE_DROP},
+	{"mp_missging_event_rl_dropped", NSS_STATS_TYPE_DROP}
+};
+
+/*
+ * nss_wifi_mesh_decap_strings_read()
+ *	Read Wi-Fi mesh decap statistics names.
+ */
+static ssize_t nss_wifi_mesh_decap_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_wifi_mesh_strings_decap_stats, NSS_WIFI_MESH_DECAP_STATS_TYPE_MAX);
+}
+
+/*
+ * nss_wifi_mesh_strings_exception_stats
+ *	Wi-Fi mesh exception statistics string.
+ */
+struct nss_stats_info nss_wifi_mesh_strings_exception_stats[NSS_WIFI_MESH_EXCEPTION_STATS_TYPE_MAX] = {
+	{"packets_success",		NSS_STATS_TYPE_SPECIAL},
+	{"packets_failure",		NSS_STATS_TYPE_DROP}
+};
+
+/*
+ * nss_wifi_mesh_exception_strings_read()
+ *	Read Wi-Fi mesh exception statistics names.
+ */
+static ssize_t nss_wifi_mesh_exception_stats_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_wifi_mesh_strings_exception_stats, NSS_WIFI_MESH_EXCEPTION_STATS_TYPE_MAX);
+}
+
+/*
+ * nss_wifi_mesh_decap_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(wifi_mesh_decap_stats);
+
+/*
+ * nss_wifi_mesh_encap_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(wifi_mesh_encap_stats);
+
+/*
+ * nss_wifi_mesh_path_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(wifi_mesh_path_stats);
+
+/*
+ * nss_wifi_mesh_proxy_path_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(wifi_mesh_proxy_path_stats);
+
+/*
+ * nss_wifi_mesh_exception_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(wifi_mesh_exception_stats);
+
+/*
+ * nss_wifi_mesh_strings_dentry_create()
+ *	Create Wi-Fi mesh statistics strings debug entry.
+ */
+struct dentry *nss_wifi_mesh_strings_dentry_create(void)
+{
+	struct dentry *str_dentry_dir;
+	struct dentry *str_file;
+
+	if (!nss_top_main.strings_dentry) {
+		nss_warning("qca-nss-drv/strings is not present\n");
+		return NULL;
+	}
+
+	str_dentry_dir = debugfs_create_dir("wifi_mesh", nss_top_main.strings_dentry);
+	if (!str_dentry_dir) {
+		nss_warning("Failed to create qca-nss-drv/string/wifi_mesh directory\n");
+		return NULL;
+	}
+
+	str_file = debugfs_create_file("encap_stats", 0400, str_dentry_dir, &nss_top_main, &nss_wifi_mesh_encap_stats_strings_ops);
+	if (!str_file) {
+		nss_warning("Failed to create qca-nss-drv/string/wifi_mesh/encap_stats file\n");
+		goto fail;
+	}
+
+	str_file = debugfs_create_file("decap_stats", 0400, str_dentry_dir, &nss_top_main, &nss_wifi_mesh_decap_stats_strings_ops);
+	if (!str_file) {
+		nss_warning("Failed to create qca-nss-drv/string/wifi_mesh/decap_stats file\n");
+		goto fail;
+	}
+
+	str_file = debugfs_create_file("path_stats", 0400, str_dentry_dir, &nss_top_main, &nss_wifi_mesh_path_stats_strings_ops);
+	if (!str_file) {
+		nss_warning("Failed to create qca-nss-drv/string/wifi_mesh/path_stats file\n");
+		goto fail;
+	}
+
+	str_file = debugfs_create_file("proxy_path_stats", 0400, str_dentry_dir, &nss_top_main, &nss_wifi_mesh_proxy_path_stats_strings_ops);
+	if (!str_file) {
+		nss_warning("Failed to create qca-nss-drv/string/wifi_mesh/proxy_path_stats file\n");
+		goto fail;
+	}
+
+	str_file = debugfs_create_file("exception_stats", 0400, str_dentry_dir, &nss_top_main, &nss_wifi_mesh_exception_stats_strings_ops);
+	if (!str_file) {
+		nss_warning("Failed to create qca-nss-drv/string/wifi_mesh/exception_stats file\n");
+		goto fail;
+	}
+
+	return str_dentry_dir;
+fail:
+	debugfs_remove_recursive(str_dentry_dir);
+	return NULL;
+}
diff --git a/qca-nss-drv/nss_wifi_mesh_strings.h b/qca-nss-drv/nss_wifi_mesh_strings.h
new file mode 100644
index 0000000..e858cbd
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_mesh_strings.h
@@ -0,0 +1,32 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_WIFI_MESH_STRINGS_H
+#define __NSS_WIFI_MESH_STRINGS_H
+
+#include "nss_wifi_mesh_stats.h"
+#include "nss_strings.h"
+
+extern struct nss_stats_info nss_wifi_mesh_strings_encap_stats[NSS_WIFI_MESH_ENCAP_STATS_TYPE_MAX];
+extern struct nss_stats_info nss_wifi_mesh_strings_decap_stats[NSS_WIFI_MESH_DECAP_STATS_TYPE_MAX];
+extern struct nss_stats_info nss_wifi_mesh_strings_path_stats[NSS_WIFI_MESH_PATH_STATS_TYPE_MAX];
+extern struct nss_stats_info nss_wifi_mesh_strings_proxy_path_stats[NSS_WIFI_MESH_PROXY_PATH_STATS_TYPE_MAX];
+extern struct nss_stats_info nss_wifi_mesh_strings_exception_stats[NSS_WIFI_MESH_EXCEPTION_STATS_TYPE_MAX];
+extern struct dentry *nss_wifi_mesh_strings_dentry_create(void);
+
+#endif /* __NSS_WIFI_MESH_STRINGS_H */
diff --git a/qca-nss-drv/nss_wifi_stats.c b/qca-nss-drv/nss_wifi_stats.c
new file mode 100644
index 0000000..0ee244d
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_stats.c
@@ -0,0 +1,215 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2019-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_core.h"
+#include "nss_wifi.h"
+#include "nss_wifi_stats.h"
+
+/*
+ * nss_wifi_stats_str
+ * 	Wifi statistics strings.
+ */
+struct nss_stats_info nss_wifi_stats_str[NSS_WIFI_STATS_MAX] = {
+	{"rx_pkts"				, NSS_STATS_TYPE_COMMON},
+	{"rx_queue[0]_drops"			, NSS_STATS_TYPE_DROP},
+	{"rx_queue[1]_drops"			, NSS_STATS_TYPE_DROP},
+	{"rx_queue[2]_drops"			, NSS_STATS_TYPE_DROP},
+	{"rx_queue[3]_drops"			, NSS_STATS_TYPE_DROP},
+	{"tx_pkts"				, NSS_STATS_TYPE_COMMON},
+	{"tx_drops"				, NSS_STATS_TYPE_DROP},
+	{"tx_transmit_completed"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_mgmt_received"			, NSS_STATS_TYPE_SPECIAL},
+	{"tx_mgmt_transmitted"			, NSS_STATS_TYPE_SPECIAL},
+	{"tx_mgmt_drops"			, NSS_STATS_TYPE_DROP},
+	{"tx_mgmt_completed"			, NSS_STATS_TYPE_SPECIAL},
+	{"tx_inv_peer_enq_cnt"			, NSS_STATS_TYPE_SPECIAL},
+	{"rx_inv_peer_rcv_cnt"			, NSS_STATS_TYPE_SPECIAL},
+	{"rx_pn_check_failed"			, NSS_STATS_TYPE_DROP},
+	{"rx_pkts_deliverd"			, NSS_STATS_TYPE_SPECIAL},
+	{"rx_bytes_delivered"			, NSS_STATS_TYPE_SPECIAL},
+	{"tx_bytes_completed"			, NSS_STATS_TYPE_SPECIAL},
+	{"rx_deliver_unaligned_drop_cnt"	, NSS_STATS_TYPE_DROP},
+	{"tidq_enqueue_cnt_0"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_enqueue_cnt_1"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_enqueue_cnt_2"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_enqueue_cnt_3"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_enqueue_cnt_4"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_enqueue_cnt_5"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_enqueue_cnt_6"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_enqueue_cnt_7"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_dequeue_cnt_0"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_dequeue_cnt_1"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_dequeue_cnt_2"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_dequeue_cnt_3"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_dequeue_cnt_4"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_dequeue_cnt_5"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_dequeue_cnt_6"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_dequeue_cnt_7"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_enqueue_fail_cnt_0"		, NSS_STATS_TYPE_DROP},
+	{"tidq_enqueue_fail_cnt_1"		, NSS_STATS_TYPE_DROP},
+	{"tidq_enqueue_fail_cnt_2"		, NSS_STATS_TYPE_DROP},
+	{"tidq_enqueue_fail_cnt_3"		, NSS_STATS_TYPE_DROP},
+	{"tidq_enqueue_fail_cnt_4"		, NSS_STATS_TYPE_DROP},
+	{"tidq_enqueue_fail_cnt_5"		, NSS_STATS_TYPE_DROP},
+	{"tidq_enqueue_fail_cnt_6"		, NSS_STATS_TYPE_DROP},
+	{"tidq_enqueue_fail_cnt_7"		, NSS_STATS_TYPE_DROP},
+	{"tidq_ttl_expire_cnt_0"		, NSS_STATS_TYPE_DROP},
+	{"tidq_ttl_expire_cnt_1"		, NSS_STATS_TYPE_DROP},
+	{"tidq_ttl_expire_cnt_2"		, NSS_STATS_TYPE_DROP},
+	{"tidq_ttl_expire_cnt_3"		, NSS_STATS_TYPE_DROP},
+	{"tidq_ttl_expire_cnt_4"		, NSS_STATS_TYPE_DROP},
+	{"tidq_ttl_expire_cnt_5"		, NSS_STATS_TYPE_DROP},
+	{"tidq_ttl_expire_cnt_6"		, NSS_STATS_TYPE_DROP},
+	{"tidq_ttl_expire_cnt_7"		, NSS_STATS_TYPE_DROP},
+	{"tidq_dequeue_req_cnt_0"		, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_dequeue_req_cnt_1"		, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_dequeue_req_cnt_2"		, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_dequeue_req_cnt_3"		, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_dequeue_req_cnt_4"		, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_dequeue_req_cnt_5"		, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_dequeue_req_cnt_6"		, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_dequeue_req_cnt_7"		, NSS_STATS_TYPE_SPECIAL},
+	{"total_tidq_depth"			, NSS_STATS_TYPE_SPECIAL},
+	{"rx_htt_fetch_cnt"			, NSS_STATS_TYPE_SPECIAL},
+	{"total_tidq_bypass_cnt"		, NSS_STATS_TYPE_SPECIAL},
+	{"global_q_full_cnt"			, NSS_STATS_TYPE_SPECIAL},
+	{"tidq_full_cnt"			, NSS_STATS_TYPE_SPECIAL},
+	{"peer_unauth_rx_pkt_drop"		, NSS_STATS_TYPE_DROP}
+};
+
+uint64_t nss_wifi_stats[NSS_MAX_WIFI_RADIO_INTERFACES][NSS_WIFI_STATS_MAX]; /* WIFI statistics */
+
+/*
+ * nss_wifi_stats_read()
+ *	Read wifi statistics.
+ */
+static ssize_t nss_wifi_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	uint32_t i, id;
+
+	/*
+	 * Max output lines = #stats * NSS_MAX_CORES  +
+	 * Few output lines for banner printing + Number of Extra outputlines for future reference to add new stats.
+	 */
+	uint32_t max_output_lines = NSS_WIFI_STATS_MAX * NSS_MAX_WIFI_RADIO_INTERFACES + NSS_STATS_EXTRA_OUTPUT_LINES;
+	size_t size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	uint64_t *stats_shadow;
+
+	char *lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	stats_shadow = kzalloc(NSS_WIFI_STATS_MAX * 8, GFP_KERNEL);
+	if (unlikely(stats_shadow == NULL)) {
+		nss_warning("Could not allocate memory for local shadow buffer");
+		kfree(lbuf);
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "wifi", NSS_STATS_SINGLE_CORE);
+
+	for (id = 0; id < NSS_MAX_WIFI_RADIO_INTERFACES; id++) {
+		spin_lock_bh(&nss_top_main.stats_lock);
+		for (i = 0; (i < NSS_WIFI_STATS_MAX); i++) {
+			stats_shadow[i] = nss_wifi_stats[id][i];
+		}
+
+		spin_unlock_bh(&nss_top_main.stats_lock);
+		size_wr += nss_stats_print("wifi", NULL, id, nss_wifi_stats_str, stats_shadow, NSS_WIFI_STATS_MAX, lbuf, size_wr, size_al);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+	kfree(stats_shadow);
+	return bytes_read;
+}
+
+/*
+ * nss_wifi_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(wifi)
+
+/*
+ * nss_wifi_stats_dentry_create()
+ *	Create wifi statistics debug entry.
+ */
+void nss_wifi_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("wifi", &nss_wifi_stats_ops);
+}
+
+/*
+ * nss_wifi_stats_sync()
+ *	Handle the syncing of WIFI stats.
+ */
+void nss_wifi_stats_sync(struct nss_ctx_instance *nss_ctx,
+		struct nss_wifi_stats_sync_msg *stats, uint16_t interface)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	uint32_t radio_id = interface - NSS_WIFI_INTERFACE0;
+	uint8_t i = 0;
+
+	if (radio_id >= NSS_MAX_WIFI_RADIO_INTERFACES) {
+		nss_warning("%px: invalid interface: %d", nss_ctx, interface);
+		return;
+	}
+
+	spin_lock_bh(&nss_top->stats_lock);
+
+	/*
+	 * Tx/Rx stats
+	 */
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_RX_PKTS] += stats->node_stats.rx_packets;
+	for (i = 0; i < NSS_MAX_NUM_PRI; i++) {
+		nss_wifi_stats[radio_id][NSS_WIFI_STATS_RX_QUEUE_0_DROPPED + i] += stats->node_stats.rx_dropped[i];
+	}
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_TX_PKTS] += stats->node_stats.tx_packets;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_TX_DROPPED] += stats->tx_transmit_dropped;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_TX_COMPLETED] += stats->tx_transmit_completions;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_MGMT_RCV_CNT] += stats->tx_mgmt_rcv_cnt;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_MGMT_TX_PKTS] += stats->tx_mgmt_pkts;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_MGMT_TX_DROPPED] += stats->tx_mgmt_dropped;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_MGMT_TX_COMPLETIONS] += stats->tx_mgmt_completions;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_TX_INV_PEER_ENQUEUE_CNT] += stats->tx_inv_peer_enq_cnt;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_RX_INV_PEER_RCV_CNT] += stats->rx_inv_peer_rcv_cnt;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_RX_PN_CHECK_FAILED] += stats->rx_pn_check_failed;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_RX_DELIVERED] += stats->rx_pkts_deliverd;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_RX_BYTES_DELIVERED] += stats->rx_bytes_deliverd;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_TX_BYTES_COMPLETED] += stats->tx_bytes_transmit_completions;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_RX_DELIVER_UNALIGNED_DROP_CNT] += stats->rx_deliver_unaligned_drop_cnt;
+
+	for (i = 0; i < NSS_WIFI_TX_NUM_TOS_TIDS; i++) {
+		nss_wifi_stats[radio_id][NSS_WIFI_STATS_TIDQ_ENQUEUE_CNT + i] += stats->tidq_enqueue_cnt[i];
+		nss_wifi_stats[radio_id][NSS_WIFI_STATS_TIDQ_DEQUEUE_CNT + i] += stats->tidq_dequeue_cnt[i];
+		nss_wifi_stats[radio_id][NSS_WIFI_STATS_TIDQ_ENQUEUE_FAIL_CNT + i] += stats->tidq_enqueue_fail_cnt[i];
+		nss_wifi_stats[radio_id][NSS_WIFI_STATS_TIDQ_TTL_EXPIRE_CNT + i] += stats->tidq_ttl_expire_cnt[i];
+		nss_wifi_stats[radio_id][NSS_WIFI_STATS_TIDQ_DEQUEUE_REQ_CNT + i] += stats->tidq_dequeue_req_cnt[i];
+	}
+
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_RX_HTT_FETCH_CNT] += stats->rx_htt_fetch_cnt;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_TOTAL_TIDQ_DEPTH] = stats->total_tidq_depth;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_TOTAL_TIDQ_BYPASS_CNT] += stats->total_tidq_bypass_cnt;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_GLOBAL_Q_FULL_CNT] += stats->global_q_full_cnt;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_TIDQ_FULL_CNT] += stats->tidq_full_cnt;
+	nss_wifi_stats[radio_id][NSS_WIFI_STATS_UNATH_RX_PKT_DROP] += stats->peer_unauth_rx_pkt_drop;
+
+	spin_unlock_bh(&nss_top->stats_lock);
+}
diff --git a/qca-nss-drv/nss_wifi_stats.h b/qca-nss-drv/nss_wifi_stats.h
new file mode 100644
index 0000000..330d258
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_stats.h
@@ -0,0 +1,63 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_WIFI_STATS_H
+#define __NSS_WIFI_STATS_H
+
+/*
+ * wifi statistics
+ */
+enum nss_wifi_stats_types {
+	NSS_WIFI_STATS_RX_PKTS,
+	NSS_WIFI_STATS_RX_QUEUE_0_DROPPED,
+	NSS_WIFI_STATS_RX_QUEUE_1_DROPPED,
+	NSS_WIFI_STATS_RX_QUEUE_2_DROPPED,
+	NSS_WIFI_STATS_RX_QUEUE_3_DROPPED,
+	NSS_WIFI_STATS_TX_PKTS,
+	NSS_WIFI_STATS_TX_DROPPED,
+	NSS_WIFI_STATS_TX_COMPLETED,
+	NSS_WIFI_STATS_MGMT_RCV_CNT,
+	NSS_WIFI_STATS_MGMT_TX_PKTS,
+	NSS_WIFI_STATS_MGMT_TX_DROPPED,
+	NSS_WIFI_STATS_MGMT_TX_COMPLETIONS,
+	NSS_WIFI_STATS_TX_INV_PEER_ENQUEUE_CNT,
+	NSS_WIFI_STATS_RX_INV_PEER_RCV_CNT,
+	NSS_WIFI_STATS_RX_PN_CHECK_FAILED,
+	NSS_WIFI_STATS_RX_DELIVERED,
+	NSS_WIFI_STATS_RX_BYTES_DELIVERED,
+	NSS_WIFI_STATS_TX_BYTES_COMPLETED,
+	NSS_WIFI_STATS_RX_DELIVER_UNALIGNED_DROP_CNT,
+	NSS_WIFI_STATS_TIDQ_ENQUEUE_CNT,
+	NSS_WIFI_STATS_TIDQ_DEQUEUE_CNT = NSS_WIFI_STATS_TIDQ_ENQUEUE_CNT + 8,
+	NSS_WIFI_STATS_TIDQ_ENQUEUE_FAIL_CNT = NSS_WIFI_STATS_TIDQ_DEQUEUE_CNT + 8,
+	NSS_WIFI_STATS_TIDQ_TTL_EXPIRE_CNT = NSS_WIFI_STATS_TIDQ_ENQUEUE_FAIL_CNT + 8,
+	NSS_WIFI_STATS_TIDQ_DEQUEUE_REQ_CNT = NSS_WIFI_STATS_TIDQ_TTL_EXPIRE_CNT + 8,
+	NSS_WIFI_STATS_TOTAL_TIDQ_DEPTH = NSS_WIFI_STATS_TIDQ_DEQUEUE_REQ_CNT + 8,
+	NSS_WIFI_STATS_RX_HTT_FETCH_CNT,
+	NSS_WIFI_STATS_TOTAL_TIDQ_BYPASS_CNT,
+	NSS_WIFI_STATS_GLOBAL_Q_FULL_CNT,
+	NSS_WIFI_STATS_TIDQ_FULL_CNT,
+	NSS_WIFI_STATS_UNATH_RX_PKT_DROP,
+	NSS_WIFI_STATS_MAX,
+};
+
+/*
+ * wifi statistics APIs
+ */
+extern void nss_wifi_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_wifi_stats_sync_msg *stats, uint16_t interface);
+extern void nss_wifi_stats_dentry_create(void);
+
+#endif /* __NSS_WIFI_STATS_H */
diff --git a/qca-nss-drv/nss_wifi_vdev.c b/qca-nss-drv/nss_wifi_vdev.c
new file mode 100644
index 0000000..54e24bb
--- /dev/null
+++ b/qca-nss-drv/nss_wifi_vdev.c
@@ -0,0 +1,387 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+
+/*
+ * nss_wifi_vdev_handler()
+ *	Handle NSS -> HLOS messages for wifi_vdev
+ */
+static void nss_wifi_vdev_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	nss_wifi_vdev_msg_callback_t cb;
+
+	nss_info("%px: NSS->HLOS message for wifi vdev on interface:%d", nss_ctx, ncm->interface);
+
+	BUG_ON(((ncm->interface < NSS_DYNAMIC_IF_START) || (ncm->interface >= (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES))));
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_WIFI_VDEV_MAX_MSG) {
+		nss_warning("%px: received invalid message %d for wifi vdev interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if (nss_cmn_get_msg_len(ncm) > sizeof(struct nss_wifi_vdev_msg)) {
+		nss_warning("%px: Length of message %d is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm), (int)sizeof(struct nss_wifi_vdev_msg));
+		return;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * callback
+	 */
+	if (!nss_ctx->subsys_dp_register[ncm->interface].ndev) {
+		nss_warning("%px: Event received wifi vdev interface %d before registration", nss_ctx, ncm->interface);
+		return;
+
+	}
+
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_core_get_msg_handler(nss_ctx, ncm->interface);
+		ncm->app_data = (nss_ptr_t)nss_ctx->subsys_dp_register[ncm->interface].ndev;
+	}
+
+	/*
+	 * Do we have a callback?
+	 */
+	if (!ncm->cb) {
+		return;
+	}
+
+	cb = (nss_wifi_vdev_msg_callback_t)ncm->cb;
+	cb((void *)ncm->app_data, ncm);
+}
+
+/*
+ * nss_wifi_vdev_msg_init()
+ *	Initialize wifi message.
+ */
+void nss_wifi_vdev_msg_init(struct nss_wifi_vdev_msg *nim, uint32_t if_num, uint32_t type, uint32_t len,
+			nss_wifi_vdev_msg_callback_t *cb, void *app_data)
+{
+	nss_cmn_msg_init(&nim->cm, if_num, type, len, (void *)cb, app_data);
+}
+EXPORT_SYMBOL(nss_wifi_vdev_msg_init);
+
+/*
+ * nss_wifi_vdev_base_tx_msg()
+ *	Transmit a wifi vdev base message to NSSFW
+ */
+nss_tx_status_t nss_wifi_vdev_base_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_wifi_vdev_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	nss_trace("%px: Sending wifi vdev message on interface :%d", nss_ctx, ncm->interface);
+
+	/*
+	 * Sanity checks on the message
+	 */
+
+	/*
+	 * The interface number shall be wifi vdev base vap
+	 */
+	 if (ncm->interface != NSS_VAP_INTERFACE) {
+		nss_warning("%px: wifi vdev base tx request not on wifi vdev vap: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_WIFI_VDEV_MAX_MSG) {
+		nss_warning("%px: wifi vdev base message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_wifi_vdev_base_tx_msg);
+
+/*
+ * nss_wifi_vdev_tx_msg()
+ *	Transmit a wifi vdev message to NSSFW
+ */
+nss_tx_status_t nss_wifi_vdev_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_wifi_vdev_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	nss_trace("%px: Sending wifi vdev message on interface :%d", nss_ctx, ncm->interface);
+
+	/*
+	 * Sanity checks on the message
+	 */
+
+	/*
+	 * Interface shall be of dynamic interface type
+	 */
+	 if ((ncm->interface < NSS_DYNAMIC_IF_START) || (ncm->interface >= (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES))) {
+		nss_warning("%px: wifi vdev tx request for invalid interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_WIFI_VDEV_MAX_MSG) {
+		nss_warning("%px: wifi vdev message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_wifi_vdev_tx_msg);
+
+/*
+ * nss_wifi_vdev_tx_msg_ext()
+ * 	Send special data packet with metadata for vap processing
+ */
+nss_tx_status_t nss_wifi_vdev_tx_msg_ext(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf)
+{
+	struct nss_wifi_vdev_msg *nm;
+	struct nss_cmn_msg *ncm;
+	nss_tx_status_t status;
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	if (unlikely(nss_ctx->state != NSS_CORE_STATE_INITIALIZED)) {
+		nss_warning("%px: wifi vdev message dropped as core not ready", nss_ctx);
+		return NSS_TX_FAILURE_NOT_READY;
+	}
+
+	nm = (struct nss_wifi_vdev_msg *) os_buf->data;
+	ncm = &nm->cm;
+
+	nss_trace("%px: Sending wifi vdev message on interface :%d", nss_ctx, ncm->interface);
+
+	/*
+	 * Interface shall be of dynamic interface type
+	 */
+	if ((ncm->interface < NSS_DYNAMIC_IF_START) || (ncm->interface >= (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES))) {
+		nss_warning("%px: wifi vdev tx request for invalid interface: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	if (ncm->type >= NSS_WIFI_VDEV_MAX_MSG) {
+		nss_warning("%px: wifi vdev message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	status = nss_core_send_buffer(nss_ctx, 0, os_buf, NSS_IF_H2N_CMD_QUEUE, H2N_BUFFER_CTRL, H2N_BIT_FLAG_BUFFER_REUSABLE);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: Unable to enqueue 'wifi vdev message'", nss_ctx);
+		return NSS_TX_FAILURE;
+	}
+
+	nss_hal_send_interrupt(nss_ctx, NSS_H2N_INTR_DATA_COMMAND_QUEUE);
+
+	NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_CMD_REQ]);
+
+return status;
+}
+EXPORT_SYMBOL(nss_wifi_vdev_tx_msg_ext);
+
+/*
+ * nss_wifi_vdev_tx_buf
+ * 	Send data packet for vap processing
+ */
+nss_tx_status_t nss_wifi_vdev_tx_buf(struct nss_ctx_instance *nss_ctx, struct sk_buff *os_buf, uint32_t if_num)
+{
+	enum nss_dynamic_interface_type if_type;
+
+	BUG_ON(((if_num < NSS_DYNAMIC_IF_START) || (if_num >= (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES))));
+
+	if_type = nss_dynamic_interface_get_type(nss_ctx, if_num);
+	if (if_type != NSS_DYNAMIC_INTERFACE_TYPE_VAP) {
+		nss_warning("%px: non vap %d packet tx not allowed", nss_ctx, if_num);
+		return NSS_TX_FAILURE_NOT_SUPPORTED;
+	}
+
+	return nss_core_send_packet(nss_ctx, os_buf, if_num, H2N_BIT_FLAG_BUFFER_REUSABLE);
+}
+EXPORT_SYMBOL(nss_wifi_vdev_tx_buf);
+
+/*
+ * nss_wifi_vdev_set_next_hop()
+ */
+nss_tx_status_t nss_wifi_vdev_set_next_hop(struct nss_ctx_instance *ctx, int if_num, int next_hop)
+{
+	nss_tx_status_t status;
+	struct nss_wifi_vdev_msg *wifivdevmsg = kzalloc(sizeof(struct nss_wifi_vdev_msg), GFP_KERNEL);
+	struct nss_wifi_vdev_set_next_hop_msg *next_hop_msg = NULL;
+
+	if (!wifivdevmsg) {
+		nss_warning("%px: Unable to allocate next hop message", ctx);
+		return NSS_TX_FAILURE;
+	}
+
+	next_hop_msg = &wifivdevmsg->msg.next_hop;
+
+	next_hop_msg->ifnumber = next_hop;
+	nss_wifi_vdev_msg_init(wifivdevmsg, if_num, NSS_WIFI_VDEV_SET_NEXT_HOP, sizeof(struct nss_wifi_vdev_set_next_hop_msg), NULL, NULL);
+
+	status = nss_wifi_vdev_tx_msg(ctx, wifivdevmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Unable to send next hop message", ctx);
+	}
+
+	kfree(wifivdevmsg);
+	return status;
+}
+EXPORT_SYMBOL(nss_wifi_vdev_set_next_hop);
+
+/*
+ * nss_wifi_vdev_base_set_next_hop()
+ */
+nss_tx_status_t nss_wifi_vdev_base_set_next_hop(struct nss_ctx_instance *ctx, int next_hop)
+{
+	nss_tx_status_t status;
+	struct nss_wifi_vdev_msg *wifivdevmsg = kzalloc(sizeof(struct nss_wifi_vdev_msg), GFP_KERNEL);
+	struct nss_wifi_vdev_set_next_hop_msg *next_hop_msg = NULL;
+
+	if (!wifivdevmsg) {
+		nss_warning("%px: Unable to allocate next hop message", ctx);
+		return NSS_TX_FAILURE;
+	}
+
+	next_hop_msg = &wifivdevmsg->msg.next_hop;
+
+	next_hop_msg->ifnumber = next_hop;
+	nss_wifi_vdev_msg_init(wifivdevmsg, NSS_VAP_INTERFACE, NSS_WIFI_VDEV_SET_NEXT_HOP, sizeof(struct nss_wifi_vdev_set_next_hop_msg), NULL, NULL);
+
+	status = nss_wifi_vdev_base_tx_msg(ctx, wifivdevmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Unable to send next hop message", ctx);
+	}
+
+	kfree(wifivdevmsg);
+	return status;
+}
+EXPORT_SYMBOL(nss_wifi_vdev_base_set_next_hop);
+
+/*
+ * nss_wifi_vdev_set_peer_next_hop()
+ */
+nss_tx_status_t nss_wifi_vdev_set_peer_next_hop(struct nss_ctx_instance *ctx, uint32_t nss_if, uint8_t *addr, uint32_t next_hop_if)
+{
+	nss_tx_status_t status;
+	struct nss_wifi_vdev_msg *wifivdevmsg = kzalloc(sizeof(struct nss_wifi_vdev_msg), GFP_KERNEL);
+	struct nss_wifi_vdev_set_peer_next_hop_msg *peer_next_hop_msg = NULL;
+
+	if (!wifivdevmsg) {
+		nss_warning("%px: Unable to allocate next hop message", ctx);
+		return NSS_TX_FAILURE;
+	}
+
+	peer_next_hop_msg = &wifivdevmsg->msg.vdev_set_peer_next_hp;
+	memcpy(peer_next_hop_msg->peer_mac_addr, addr, ETH_ALEN);
+
+	peer_next_hop_msg->if_num = next_hop_if;
+	nss_wifi_vdev_msg_init(wifivdevmsg, nss_if, NSS_WIFI_VDEV_SET_PEER_NEXT_HOP,
+			sizeof(struct nss_wifi_vdev_set_peer_next_hop_msg), NULL, NULL);
+
+	status = nss_wifi_vdev_tx_msg(ctx, wifivdevmsg);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: Unable to send peer next hop message", ctx);
+	}
+
+	kfree(wifivdevmsg);
+	return status;
+}
+EXPORT_SYMBOL(nss_wifi_vdev_set_peer_next_hop);
+
+/*
+ * nss_wifi_vdev_set_dp_type()
+ *	Set the vap datapath type of the packet.
+ */
+bool nss_wifi_vdev_set_dp_type(struct nss_ctx_instance *nss_ctx, struct net_device *netdev,
+						uint32_t if_num, enum nss_wifi_vdev_dp_type dp_type)
+{
+
+	NSS_VERIFY_CTX_MAGIC(nss_ctx);
+
+	nss_assert((if_num >= NSS_DYNAMIC_IF_START) && (if_num < (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES)));
+
+	if (unlikely(nss_ctx->state != NSS_CORE_STATE_INITIALIZED)) {
+		nss_warning("%px: Vap interface dp type could not be set as core is not initialized\n", nss_ctx);
+		return false;
+	}
+
+	/*
+	 * set the subsytem dp type for the Wi-Fi vdev
+	 */
+	nss_core_set_subsys_dp_type(nss_ctx, netdev, if_num, dp_type);
+
+	return true;
+}
+EXPORT_SYMBOL(nss_wifi_vdev_set_dp_type);
+
+/*
+ ***********************************
+ * Register/Unregister/Miscellaneous APIs
+ ***********************************
+ */
+
+/*
+ * nss_register_wifi_vdev_if()
+ */
+uint32_t nss_register_wifi_vdev_if(struct nss_ctx_instance *nss_ctx,
+				int32_t if_num,
+				nss_wifi_vdev_callback_t vdev_data_callback,
+				nss_wifi_vdev_ext_data_callback_t vdev_ext_data_callback,
+				nss_wifi_vdev_msg_callback_t vdev_event_callback,
+				struct net_device *netdev,
+				uint32_t features)
+{
+	uint32_t status;
+
+	nss_assert((if_num >= NSS_DYNAMIC_IF_START) && (if_num < (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES)));
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, vdev_data_callback, vdev_ext_data_callback, NULL, netdev, features);
+
+	status = nss_core_register_msg_handler(nss_ctx, if_num, vdev_event_callback);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to register event handler for interface(%u)", nss_ctx, if_num);
+		return status;
+	}
+
+	nss_core_register_handler(nss_ctx, if_num, nss_wifi_vdev_handler, NULL);
+
+	return NSS_CORE_STATUS_SUCCESS;
+}
+EXPORT_SYMBOL(nss_register_wifi_vdev_if);
+
+/*
+ * nss_unregister_wifi_vdev_if()
+ */
+void nss_unregister_wifi_vdev_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wifi_handler_id];
+	uint32_t status;
+
+	nss_assert(nss_ctx);
+	nss_assert((if_num >= NSS_DYNAMIC_IF_START) && (if_num < (NSS_DYNAMIC_IF_START + NSS_MAX_DYNAMIC_INTERFACES)));
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+
+	status = nss_core_unregister_msg_handler(nss_ctx, if_num);
+	if (status != NSS_CORE_STATUS_SUCCESS) {
+		nss_warning("%px: unable to unregister event handler for interface(%u)", nss_ctx, if_num);
+		return;
+	}
+
+	nss_core_unregister_handler(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_unregister_wifi_vdev_if);
diff --git a/qca-nss-drv/nss_wifili.c b/qca-nss-drv/nss_wifili.c
new file mode 100644
index 0000000..c1904e4
--- /dev/null
+++ b/qca-nss-drv/nss_wifili.c
@@ -0,0 +1,670 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_wifili_stats.h"
+#include "nss_wifili_log.h"
+#include "nss_wifili_strings.h"
+
+#define NSS_WIFILI_TX_TIMEOUT 1000 /* Millisecond to jiffies*/
+#define NSS_WIFILI_INVALID_SCHEME_ID  -1
+#define NSS_WIFILI_THREAD_SCHEME_ENTRY_MAX  4 /* Maximum number of thread scheme entries. */
+#define NSS_WIFILI_EXTERNAL_INTERFACE_MAX 2 /* Maximum external I/F supported */
+
+/*
+ * NSS external interface number table
+ */
+nss_if_num_t nss_wifili_external_tbl[NSS_WIFILI_EXTERNAL_INTERFACE_MAX] =
+	{NSS_WIFILI_EXTERNAL_INTERFACE0, NSS_WIFILI_EXTERNAL_INTERFACE1};
+
+/*
+ * nss_wifili_thread_scheme_entry
+ *	Details of thread scheme.
+ */
+struct nss_wifili_thread_scheme_entry {
+	int32_t radio_ifnum;		/* Radio interface number. */
+	uint32_t radio_priority;	/* Priority of radio. */
+	uint32_t scheme_priority;	/* Priority of scheme. */
+	uint8_t scheme_index;		/* Scheme index allocated to radio. */
+	bool allocated;			/* Flag to check if scheme is allocated. */
+};
+
+/*
+ * nss_wifili_thread_scheme_db
+ *	Wifili thread scheme database.
+ */
+struct nss_wifili_thread_scheme_db {
+	spinlock_t lock;	/* Lock to protect from simultaneous access. */
+	uint32_t radio_count;	/* Radio counter. */
+	struct nss_wifili_thread_scheme_entry nwtse[NSS_WIFILI_THREAD_SCHEME_ENTRY_MAX];
+				/* Metadata for each of scheme. */
+};
+
+/*
+ * nss_wifili_external_if_state_tbl
+ *	External interface state table
+ */
+struct nss_wifili_external_if_state_tbl {
+	nss_if_num_t ifnum;
+	bool in_use;
+};
+
+/*
+ * nss_wifili_external_if_info
+ *	Wifili external interface info
+ */
+struct nss_wifili_external_if_info {
+	spinlock_t lock;
+	struct nss_wifili_external_if_state_tbl state_tbl[NSS_WIFILI_EXTERNAL_INTERFACE_MAX];
+} nss_wifi_eif_info;
+
+/*
+ * nss_wifili_pvt
+ *	Private data structure
+ */
+static struct nss_wifili_pvt {
+	struct semaphore sem;
+	struct completion complete;
+	int response;
+	void *cb;
+	void *app_data;
+} wifili_pvt;
+
+/*
+ * Scheme to radio mapping database
+ */
+static struct nss_wifili_thread_scheme_db ts_db[NSS_MAX_CORES];
+
+/*
+ * nss_wifili_handler()
+ *	Handle NSS -> HLOS messages for wifi
+ */
+static void nss_wifili_handler(struct nss_ctx_instance *nss_ctx, struct nss_cmn_msg *ncm, __attribute__((unused))void *app_data)
+{
+	struct nss_wifili_msg *ntm = (struct nss_wifili_msg *)ncm;
+	void *ctx;
+	nss_wifili_msg_callback_t cb;
+
+	nss_info("%px: NSS->HLOS message for wifili\n", nss_ctx);
+
+	/*
+	 * The interface number shall be wifili soc interface or wifili radio interface
+	 */
+	BUG_ON((nss_is_dynamic_interface(ncm->interface))
+		|| ((ncm->interface != NSS_WIFILI_INTERNAL_INTERFACE)
+		&& (ncm->interface != NSS_WIFILI_EXTERNAL_INTERFACE0)
+		&& (ncm->interface != NSS_WIFILI_EXTERNAL_INTERFACE1)));
+
+	/*
+	 * Trace messages.
+	 */
+	nss_wifili_log_rx_msg(ntm);
+
+	/*
+	 * Is this a valid request/response packet?
+	 */
+	if (ncm->type >= NSS_WIFILI_MAX_MSG) {
+		nss_warning("%px: Received invalid message %d for wifili interface", nss_ctx, ncm->type);
+		return;
+	}
+
+	if ((nss_cmn_get_msg_len(ncm) > sizeof(struct nss_wifili_msg)) &&
+		ntm->cm.type != NSS_WIFILI_PEER_EXT_STATS_MSG) {
+		nss_warning("%px: Length of message is greater than required: %d", nss_ctx, nss_cmn_get_msg_len(ncm));
+		return;
+	}
+
+	/*
+	 * Snoop messages for local driver and handle
+	 */
+	switch (ntm->cm.type) {
+	case NSS_WIFILI_STATS_MSG:
+		/*
+		 * Update WIFI driver statistics and send statistics notifications to the registered modules
+		 */
+		nss_wifili_stats_sync(nss_ctx, &ntm->msg.wlsoc_stats, ncm->interface);
+		nss_wifili_stats_notify(nss_ctx, ncm->interface);
+		break;
+	}
+
+	/*
+	 * Update the callback and app_data for notify messages, wifili sends all notify messages
+	 * to the same callback/app_data.
+	 */
+	if (ncm->response == NSS_CMN_RESPONSE_NOTIFY) {
+		ncm->cb = (nss_ptr_t)nss_ctx->nss_top->wifili_msg_callback;
+	}
+
+	/*
+	 * Log failures
+	 */
+	nss_core_log_msg_failures(nss_ctx, ncm);
+
+	/*
+	 * Do we have a call back
+	 */
+	if (!ncm->cb) {
+		nss_info("%px: cb null for wifili interface %d", nss_ctx, ncm->interface);
+		return;
+	}
+
+	/*
+	 * Get callback & context
+	 */
+	cb = (nss_wifili_msg_callback_t)ncm->cb;
+	ctx = nss_ctx->subsys_dp_register[ncm->interface].ndev;
+
+	/*
+	 * call wifili msg callback
+	 */
+	if (!ctx) {
+		nss_warning("%px: Event received for wifili interface %d before registration", nss_ctx, ncm->interface);
+		return;
+	}
+
+	cb(ctx, ntm);
+}
+
+/*
+ * nss_wifili_callback()
+ *	Callback to handle the completion of NSS->HLOS messages.
+ */
+static void nss_wifili_callback(void *app_data, struct nss_wifili_msg *nvm)
+{
+	nss_wifili_msg_callback_t callback = (nss_wifili_msg_callback_t)wifili_pvt.cb;
+	void *data = wifili_pvt.app_data;
+
+	wifili_pvt.response = NSS_TX_SUCCESS;
+	wifili_pvt.cb = NULL;
+	wifili_pvt.app_data = NULL;
+
+	if (nvm->cm.response != NSS_CMN_RESPONSE_ACK) {
+		nss_warning("wifili error response %d\n", nvm->cm.response);
+		wifili_pvt.response = nvm->cm.response;
+	}
+
+	if (callback) {
+		callback(data, nvm);
+	}
+	complete(&wifili_pvt.complete);
+}
+
+/*
+ * nss_wifili_tx_msg
+ *	Transmit a wifili message to NSS FW
+ *
+ * NOTE: The caller is expected to handle synchronous wait for message
+ * response if needed.
+ */
+nss_tx_status_t nss_wifili_tx_msg(struct nss_ctx_instance *nss_ctx, struct nss_wifili_msg *msg)
+{
+	struct nss_cmn_msg *ncm = &msg->cm;
+
+	/*
+	 * Trace messages.
+	 */
+	nss_wifili_log_tx_msg(msg);
+
+	if (ncm->type >= NSS_WIFILI_MAX_MSG) {
+		nss_warning("%px: wifili message type out of range: %d", nss_ctx, ncm->type);
+		return NSS_TX_FAILURE;
+	}
+
+	/*
+	 * The interface number shall be one of the wifili soc interfaces
+	 */
+	if ((ncm->interface != NSS_WIFILI_INTERNAL_INTERFACE)
+		&& (ncm->interface != NSS_WIFILI_EXTERNAL_INTERFACE0)
+		&& (ncm->interface != NSS_WIFILI_EXTERNAL_INTERFACE1)) {
+		nss_warning("%px: tx request for interface that is not a wifili: %d", nss_ctx, ncm->interface);
+		return NSS_TX_FAILURE;
+	}
+
+	return nss_core_send_cmd(nss_ctx, msg, sizeof(*msg), NSS_NBUF_PAYLOAD_SIZE);
+}
+EXPORT_SYMBOL(nss_wifili_tx_msg);
+
+/*
+ * nss_wifili_tx_msg_sync()
+ *	Transmit a wifili message to NSS firmware synchronously.
+ */
+nss_tx_status_t nss_wifili_tx_msg_sync(struct nss_ctx_instance *nss_ctx, struct nss_wifili_msg *nvm)
+{
+	nss_tx_status_t status;
+	int ret = 0;
+
+	down(&wifili_pvt.sem);
+	wifili_pvt.cb = (void *)nvm->cm.cb;
+	wifili_pvt.app_data = (void *)nvm->cm.app_data;
+
+	nvm->cm.cb = (nss_ptr_t)nss_wifili_callback;
+	nvm->cm.app_data = (nss_ptr_t)NULL;
+
+	status = nss_wifili_tx_msg(nss_ctx, nvm);
+	if (status != NSS_TX_SUCCESS) {
+		nss_warning("%px: wifili_tx_msg failed\n", nss_ctx);
+		up(&wifili_pvt.sem);
+		return status;
+	}
+
+	ret = wait_for_completion_timeout(&wifili_pvt.complete, msecs_to_jiffies(NSS_WIFILI_TX_TIMEOUT));
+	if (!ret) {
+		nss_warning("%px: wifili msg tx failed due to timeout\n", nss_ctx);
+		wifili_pvt.response = NSS_TX_FAILURE;
+	}
+
+	status = wifili_pvt.response;
+	up(&wifili_pvt.sem);
+	return status;
+}
+EXPORT_SYMBOL(nss_wifili_tx_msg_sync);
+
+/*
+ * nss_wifili_get_context()
+ */
+struct nss_ctx_instance *nss_wifili_get_context(void)
+{
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wifi_handler_id];
+}
+EXPORT_SYMBOL(nss_wifili_get_context);
+
+/*
+ * nss_wifili_release_external_if()
+ *	Release the external interface.
+ */
+void nss_wifili_release_external_if(nss_if_num_t ifnum)
+{
+	uint32_t idx;
+
+	spin_lock_bh(&nss_wifi_eif_info.lock);
+	for (idx = 0; idx < NSS_WIFILI_EXTERNAL_INTERFACE_MAX; idx++) {
+		if (nss_wifi_eif_info.state_tbl[idx].ifnum != ifnum) {
+			continue;
+		}
+
+		if (!nss_wifi_eif_info.state_tbl[idx].in_use) {
+			spin_unlock_bh(&nss_wifi_eif_info.lock);
+			nss_warning("%px: I/F num:%d is not in use\n", &nss_wifi_eif_info, ifnum);
+			return;
+		}
+
+		nss_wifi_eif_info.state_tbl[idx].in_use = false;
+		break;
+	}
+
+	spin_unlock_bh(&nss_wifi_eif_info.lock);
+
+	if (idx == NSS_WIFILI_EXTERNAL_INTERFACE_MAX) {
+		nss_warning("%px: Trying to release invalid ifnum:%d\n", &nss_wifi_eif_info, ifnum);
+	}
+}
+EXPORT_SYMBOL(nss_wifili_release_external_if);
+
+/*
+ * nss_get_available_wifili_external_if()
+ *	Check and return the available external interface
+ */
+nss_if_num_t nss_get_available_wifili_external_if(void)
+{
+	nss_if_num_t ifnum = -1;
+	uint32_t idx;
+
+	/*
+	 * Check if the external interface is registered.
+	 * Return the interface number if not registered.
+	 */
+	spin_lock_bh(&nss_wifi_eif_info.lock);
+	for (idx = 0; idx < NSS_WIFILI_EXTERNAL_INTERFACE_MAX; idx++) {
+		if (nss_wifi_eif_info.state_tbl[idx].in_use) {
+			continue;
+		}
+
+		nss_wifi_eif_info.state_tbl[idx].in_use = true;
+		ifnum = nss_wifi_eif_info.state_tbl[idx].ifnum;
+		break;
+	}
+
+	spin_unlock_bh(&nss_wifi_eif_info.lock);
+
+	BUG_ON(idx == NSS_WIFILI_EXTERNAL_INTERFACE_MAX);
+	return ifnum;
+}
+EXPORT_SYMBOL(nss_get_available_wifili_external_if);
+
+/*
+ * nss_wifili_get_radio_num()
+ *     Get NSS wifili radio count.
+ *
+ * Wi-Fi host driver needs to know the current radio count
+ * to extract the radio priority from ini file.
+ */
+uint32_t nss_wifili_get_radio_num(struct nss_ctx_instance *nss_ctx)
+{
+	uint8_t core_id;
+	uint32_t radio_count;
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_ctx->id < nss_top_main.num_nss);
+
+	core_id = nss_ctx->id;
+
+	spin_lock_bh(&ts_db[core_id].lock);
+	radio_count = ts_db[core_id].radio_count;
+	spin_unlock_bh(&ts_db[core_id].lock);
+
+	return radio_count;
+}
+EXPORT_SYMBOL(nss_wifili_get_radio_num);
+
+/*
+ * nss_wifili_thread_scheme_alloc()
+ *	Allocate NSS worker thread scheme index.
+ *
+ * API does search on scheme database and returns scheme index based on
+ * priority of radio and free entry available.
+ * Wi-Fi driver fetches radio priority from ini file and calls this API
+ * to get the scheme index based on radio priority.
+ *
+ */
+uint8_t nss_wifili_thread_scheme_alloc(struct nss_ctx_instance *nss_ctx,
+					int32_t radio_ifnum,
+					enum nss_wifili_thread_scheme_priority radio_priority)
+{
+	uint8_t i;
+	uint8_t scheme_idx;
+	uint8_t core_id;
+	uint8_t next_avail_entry_idx = NSS_WIFILI_THREAD_SCHEME_ENTRY_MAX;
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_ctx->id < nss_top_main.num_nss);
+
+	core_id = nss_ctx->id;
+
+	/*
+	 * Iterate through scheme database and allocate
+	 * scheme_id matching the priority requested.
+	 */
+	spin_lock_bh(&ts_db[core_id].lock);
+	for (i = 0; i < NSS_WIFILI_THREAD_SCHEME_ENTRY_MAX; i++) {
+		if (ts_db[core_id].nwtse[i].allocated) {
+			continue;
+		}
+
+		if (radio_priority ==
+				ts_db[core_id].nwtse[i].scheme_priority) {
+			ts_db[core_id].nwtse[i].radio_ifnum = radio_ifnum;
+			ts_db[core_id].nwtse[i].radio_priority = radio_priority;
+			ts_db[core_id].nwtse[i].allocated = true;
+			ts_db[core_id].radio_count++;
+			scheme_idx = ts_db[core_id].nwtse[i].scheme_index;
+			spin_unlock_bh(&ts_db[core_id].lock);
+
+			nss_info("%px: Allocated scheme index:%d radio_ifnum:%d",
+					nss_ctx,
+					scheme_idx,
+					radio_ifnum);
+
+			return scheme_idx;
+		}
+
+		next_avail_entry_idx = i;
+	}
+
+	/*
+	 * When radio priority does not match any of scheme entry priority
+	 * and database has unallocated entries, provide available unallocated entry.
+	 * This prevents any catastrophic failure during attach of Wi-Fi radio.
+	 */
+	if (next_avail_entry_idx != NSS_WIFILI_THREAD_SCHEME_ENTRY_MAX) {
+
+		ts_db[core_id].nwtse[next_avail_entry_idx].radio_ifnum = radio_ifnum;
+		ts_db[core_id].nwtse[next_avail_entry_idx].radio_priority = radio_priority;
+		ts_db[core_id].nwtse[next_avail_entry_idx].allocated = true;
+		ts_db[core_id].radio_count++;
+		scheme_idx = ts_db[core_id].nwtse[next_avail_entry_idx].scheme_index;
+		spin_unlock_bh(&ts_db[core_id].lock);
+
+		nss_info("%px: Priority did not match for radio_ifnum:%d, allocated a next available scheme:%d",
+				nss_ctx,
+				radio_ifnum,
+				scheme_idx);
+
+		return scheme_idx;
+	}
+	spin_unlock_bh(&ts_db[core_id].lock);
+
+	nss_warning("%px: Could not find scheme - radio_ifnum:%d radio_map:%d\n",
+			nss_ctx,
+			radio_ifnum,
+			radio_priority);
+
+	return NSS_WIFILI_INVALID_SCHEME_ID;
+}
+EXPORT_SYMBOL(nss_wifili_thread_scheme_alloc);
+
+/*
+ * nss_wifili_thread_scheme_dealloc()
+ *	Reset thread scheme metadata.
+ */
+void nss_wifili_thread_scheme_dealloc(struct nss_ctx_instance *nss_ctx,
+					int32_t radio_ifnum)
+{
+	uint32_t id;
+	uint8_t core_id;
+
+	nss_assert(nss_ctx);
+	nss_assert(nss_ctx->id < nss_top_main.num_nss);
+
+	core_id = nss_ctx->id;
+
+	/*
+	 * Radio count cannot be zero here.
+	 */
+	nss_assert(ts_db[core_id].radio_count);
+
+	spin_lock_bh(&ts_db[core_id].lock);
+	for (id = 0; id < NSS_WIFILI_THREAD_SCHEME_ENTRY_MAX; id++) {
+		if (ts_db[core_id].nwtse[id].radio_ifnum != radio_ifnum) {
+			continue;
+		}
+
+		ts_db[core_id].nwtse[id].radio_priority = 0;
+		ts_db[core_id].nwtse[id].allocated = false;
+		ts_db[core_id].nwtse[id].radio_ifnum = 0;
+		ts_db[core_id].radio_count--;
+		break;
+	}
+	spin_unlock_bh(&ts_db[core_id].lock);
+
+	if (id == NSS_WIFILI_THREAD_SCHEME_ENTRY_MAX) {
+		nss_warning("%px: Could not find scheme database with radio_ifnum:%d",
+				nss_ctx,
+				radio_ifnum);
+	}
+}
+EXPORT_SYMBOL(nss_wifili_thread_scheme_dealloc);
+
+/*
+ * nss_wifili_thread_scheme_db_init()
+ *	Initialize thread scheme database.
+ */
+void nss_wifili_thread_scheme_db_init(uint8_t core_id)
+{
+	uint32_t id;
+
+	spin_lock_init(&ts_db[core_id].lock);
+
+	/*
+	 * Iterate through scheme database and assign
+	 * scheme_id and priority for each entry
+	 */
+	ts_db[core_id].radio_count = 0;
+	for (id = 0; id < NSS_WIFILI_THREAD_SCHEME_ENTRY_MAX; id++) {
+		ts_db[core_id].nwtse[id].radio_priority = 0;
+		ts_db[core_id].nwtse[id].radio_ifnum = 0;
+		ts_db[core_id].nwtse[id].allocated = false;
+
+		switch (id) {
+		case 0:
+			ts_db[core_id].nwtse[id].scheme_priority = NSS_WIFILI_HIGH_PRIORITY_SCHEME;
+			ts_db[core_id].nwtse[id].scheme_index = NSS_WIFILI_THREAD_SCHEME_ID_0;
+			break;
+		case 1:
+			ts_db[core_id].nwtse[id].scheme_priority = NSS_WIFILI_LOW_PRIORITY_SCHEME;
+			ts_db[core_id].nwtse[id].scheme_index = NSS_WIFILI_THREAD_SCHEME_ID_1;
+			break;
+		case 2:
+		case 3:
+			ts_db[core_id].nwtse[id].scheme_priority = NSS_WIFILI_HIGH_PRIORITY_SCHEME;
+			ts_db[core_id].nwtse[id].scheme_index = NSS_WIFILI_THREAD_SCHEME_ID_2;
+			break;
+		default:
+			nss_warning("Invalid scheme index:%d", id);
+		}
+	}
+}
+
+/*
+ * nss_wifili_msg_init()
+ *	Initialize nss_wifili_msg.
+ */
+void nss_wifili_msg_init(struct nss_wifili_msg *ncm, uint16_t if_num, uint32_t type, uint32_t len, void *cb, void *app_data)
+{
+	nss_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+EXPORT_SYMBOL(nss_wifili_msg_init);
+
+/*
+ ****************************************
+ * Register/Unregister/Miscellaneous APIs
+ ****************************************
+ */
+
+/*
+ * nss_register_wifili_if()
+ *	Register wifili with nss driver
+ */
+struct nss_ctx_instance *nss_register_wifili_if(uint32_t if_num, nss_wifili_callback_t wifili_callback,
+			nss_wifili_callback_t wifili_ext_callback,
+			nss_wifili_msg_callback_t event_callback, struct net_device *netdev, uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wifi_handler_id];
+
+	/*
+	 * The interface number shall be wifili soc interface
+	 */
+	nss_assert((if_num == NSS_WIFILI_INTERNAL_INTERFACE)
+			|| (if_num == NSS_WIFILI_EXTERNAL_INTERFACE0)
+			|| (if_num == NSS_WIFILI_EXTERNAL_INTERFACE1));
+
+	nss_info("nss_register_wifili_if if_num %d wifictx %px", if_num, netdev);
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, wifili_callback, wifili_ext_callback, NULL, netdev, features);
+
+	nss_top_main.wifili_msg_callback = event_callback;
+
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wifi_handler_id];
+}
+EXPORT_SYMBOL(nss_register_wifili_if);
+
+/*
+ * nss_unregister_wifili_if()
+ *	Unregister wifili with nss driver
+ */
+void nss_unregister_wifili_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wifi_handler_id];
+
+	/*
+	 * The interface number shall be wifili soc interface
+	 */
+	nss_assert((if_num == NSS_WIFILI_INTERNAL_INTERFACE)
+			|| (if_num == NSS_WIFILI_EXTERNAL_INTERFACE0)
+			|| (if_num == NSS_WIFILI_EXTERNAL_INTERFACE1));
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+	nss_wifili_release_external_if(if_num);
+}
+EXPORT_SYMBOL(nss_unregister_wifili_if);
+
+/*
+ * nss_register_wifili_radio_if()
+ *	Register wifili radio with nss driver
+ */
+struct nss_ctx_instance *nss_register_wifili_radio_if(uint32_t if_num, nss_wifili_callback_t wifili_callback,
+			nss_wifili_callback_t wifili_ext_callback,
+			nss_wifili_msg_callback_t event_callback, struct net_device *netdev, uint32_t features)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wifi_handler_id];
+
+	/*
+	 * The interface number shall be wifili radio dynamic interface
+	 */
+	nss_assert(nss_is_dynamic_interface(if_num));
+	nss_info("nss_register_wifili_if if_num %d wifictx %px", if_num, netdev);
+
+	nss_core_register_subsys_dp(nss_ctx, if_num, wifili_callback, wifili_ext_callback, NULL, netdev, features);
+
+	return (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wifi_handler_id];
+}
+EXPORT_SYMBOL(nss_register_wifili_radio_if);
+
+/*
+ * nss_unregister_wifili_radio_if()
+ *	Unregister wifili radio with nss driver
+ */
+void nss_unregister_wifili_radio_if(uint32_t if_num)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wifi_handler_id];
+
+	/*
+	 * The interface number shall be wifili radio dynamic interface
+	 */
+	nss_assert(nss_is_dynamic_interface(if_num));
+
+	nss_core_unregister_subsys_dp(nss_ctx, if_num);
+}
+EXPORT_SYMBOL(nss_unregister_wifili_radio_if);
+
+/*
+ * nss_wifili_register_handler()
+ *	Register handle for notfication messages received on wifi interface
+ */
+void nss_wifili_register_handler(void)
+{
+	struct nss_ctx_instance *nss_ctx = (struct nss_ctx_instance *)&nss_top_main.nss[nss_top_main.wifi_handler_id];
+	uint32_t idx;
+
+	nss_info("nss_wifili_register_handler");
+	nss_core_register_handler(nss_ctx, NSS_WIFILI_INTERNAL_INTERFACE, nss_wifili_handler, NULL);
+	nss_core_register_handler(nss_ctx, NSS_WIFILI_EXTERNAL_INTERFACE0, nss_wifili_handler, NULL);
+	nss_core_register_handler(nss_ctx, NSS_WIFILI_EXTERNAL_INTERFACE1, nss_wifili_handler, NULL);
+
+	nss_wifili_stats_dentry_create();
+	nss_wifili_strings_dentry_create();
+
+	sema_init(&wifili_pvt.sem, 1);
+	init_completion(&wifili_pvt.complete);
+
+	/*
+	 * Intialize the external interfaces info.
+	 */
+	spin_lock_init(&nss_wifi_eif_info.lock);
+	for (idx = 0; idx < NSS_WIFILI_EXTERNAL_INTERFACE_MAX; idx++) {
+		nss_wifi_eif_info.state_tbl[idx].ifnum = nss_wifili_external_tbl[idx];
+		nss_wifi_eif_info.state_tbl[idx].in_use = false;
+	}
+}
diff --git a/qca-nss-drv/nss_wifili_log.c b/qca-nss-drv/nss_wifili_log.c
new file mode 100644
index 0000000..7c679df
--- /dev/null
+++ b/qca-nss-drv/nss_wifili_log.c
@@ -0,0 +1,553 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_wifili_log.c
+ *	NSS WIFILI logger file.
+ */
+
+#include "nss_core.h"
+
+/*
+ * nss_wifili_log_message_types_str
+ *	WIFILI message strings
+ */
+static int8_t *nss_wifili_log_message_types_str[NSS_WIFILI_MAX_MSG] __maybe_unused = {
+	"WIFILI INIT MSG",
+	"WIFILI SOC RESET MSG",
+	"WIFILI PDEV INIT MSG",
+	"WIFILI PDEV DEINIT MSG",
+	"WIFILI START MSG",
+	"WIFILI STOP MSG",
+	"WIFILI PEER CREATE MSG",
+	"WIFILI PEER DELETE MSG",
+	"WIFILI SEND PEER MEMORY REQUEST MSG",
+	"WIFILI PEER FREELIST APPEND MSG",
+	"WIFILI STATS MSG",
+	"WIFILI WDS VENDOR MSG",
+	"WIFILI PEER STATS MSG",
+	"WIFILI WDS PEER ADD MSG",
+	"WIFILI WDS PEER DEL MSG",
+	"WIFILI WDS PEER MAP MSG",
+	"WIFILI WDS ACTIVE INFO MSG",
+	"WIFILI STATS CFG MSG",
+	"WIFILI TID REOQ SETUP MSG",
+	"WIFILI RADIO CMD MSG",
+	"WIFILI LINK DESC INFO MSG",
+	"WIFILI PEER SECURITY TYPE MSG",
+	"WIFILI PEER NAWDS ENABLE MSG",
+	"WIFILI RADIO BUF CFG",
+	"WIFILI DBDC REPEATER SET MSG",
+	"WIFILI DBDC REPEATER AST FLUSH MSG"
+};
+
+/*
+ * nss_wifili_log_error_response_types_str
+ *	Strings for error types for WIFILI messages
+ */
+static int8_t *nss_wifili_log_error_response_types_str[NSS_WIFILI_EMSG_UNKNOWN] __maybe_unused = {
+	"WIFILI NO ERROR",
+	"WIFILI INIT FAIL IMPROPER STATE",
+	"WIFILI RINGS INIT FAIL",
+	"WIFILI PDEV INIT IMPROPER STATE FAIL",
+	"WIFILI PDEV INIT INVALID RADIOID FAIL",
+	"WIFILI PDEV TX IRQ ALLOC FAIL",
+	"WIFILI PDEV RESET INVALID RADIOID FAIL",
+	"WIFILI PDEV RESET PDEV NULL FAIL",
+	"WIFILI PDEV RESET IMPROPER STATE FAIL",
+	"WIFILI START IMPROPER STATE FAIL",
+	"WIFILI PEER CREATE FAIL",
+	"WIFILI PEER DELETE FAIL",
+	"WIFILI HASHMEM INIT FAIL",
+	"WIFILI PEER FREELIST APPEND FAIL",
+	"WIFILI PEER CREATE INVALID VDEVID FAIL",
+	"WIFILI PEER CREATE INVALID PEER ID FAIL",
+	"WIFILI PEER CREATE VDEV NULL FAIL",
+	"WIFILI PEER CREATE PDEV NULL FAIL",
+	"WIFILI PEER CREATE ALLOC FAIL",
+	"WIFILI PEER DELETE VAPID INVALID FAIL",
+	"WIFILI PEER DELETE INVALID PEERID FAIL",
+	"WIFILI PEER DELETE VDEV NULL FAIL",
+	"WIFILI PEER DELETE PDEV NULL FAIL",
+	"WIFILI PEER DELETE PEER NULL FAIL",
+	"WIFILI PEER DELETE PEER CORRUPTED FAIL",
+	"WIFILI PEER DUPLICATE AST INDEX PEER ID FAIL",
+	"WIFILI GROUP0 TIMER ALLOC FAIL",
+	"WIFILI INSUFFICIENT WT FAIL",
+	"WIFILI INVALID NUM TCL RING FAIL",
+	"WIFILI INVALID NUM REO DST RING FAIL",
+	"WIFILI HAL SRNG SOC ALLOC FAIL",
+	"WIFILI HAL SRNG INVALID RING INFO FAIL",
+	"WIFILI HAL SRNG TCL ALLOC FAIL",
+	"WIFILI HAL SRNG TXCOMP ALLOC FAIL",
+	"WIFILI HAL SRNG REODST ALLOC FAIL",
+	"WIFILI HAL SRNG REOREINJECT ALLOC FAIL",
+	"WIFILI HAL SRNG RXRELEASE ALLOC FAIL",
+	"WIFILI HAL SRNG RXEXCP ALLOC FAIL",
+	"WIFILI HAL TX MEMALLOC FAIL",
+	"WIFILI HAL TX INVLID POOL NUM FAIL",
+	"WIFILI HAL TX INVALID PAGE NUM FAIL",
+	"WIFILI HAL TX DESC MEM ALLOC FAIL",
+	"WIFILI HAL RX MEMALLOC FAIL",
+	"WIFILI PDEV RXDMA RING ALLOC FAIL",
+	"WIFILI NAWDSEN PEERID INVALID",
+	"WIFILI NAWDSEN PEER NULL",
+	"WIFILI NAWDSEN PEER CORRUPTED",
+	"WIFILI WDS PEER CFG FAIL",
+	"WIFILI RESET NO STOP",
+	"WIFILI HAL SRNG INVALID RING BASE FAIL",
+	"WIFILI PDEV RX INIT FAIL",
+	"WIFILI EMESG AST ADD FAIL",
+	"WIFILI EMESG AST REMOVE FAIL",
+	"WIFILI EMESG WDS ADD FAIL",
+	"WIFILI EMESG WDS REMOVE FAIL",
+	"WIFILI EMESG WDS MAP FAIL",
+	"WIFILI WDS INVALID PEERID FAIL",
+	"WIFILI WDS DUPLICATE AST INDEX PEER ID FAIL",
+	"WIFILI INVALID RADIO CMD",
+	"WIFILI INVALID RADIO IFNUM",
+	"WIFILI PEER SECURITY PEER NULL FAIL",
+	"WIFILI PEER SECURITY PEER CORRUPTED FAIL",
+	"WIFILI RADIO INVALID BUF CFG",
+};
+
+/*
+ * nss_wifili_log_wifili_hal_srng()
+ *	Log NSS WIFILI HAL SRNG Information
+ */
+static void nss_wifili_log_wifili_hal_srng(struct nss_wifili_hal_srng_info *ring)
+{
+	int32_t i;
+	nss_trace("\tRing ID: %d\n"
+		"\tMAC ID: %d\n"
+		"\tRing base physical address: %x\n"
+		"\tNumber of entries: %d\n"
+		"\tFlags: %x\n"
+		"\tDirection: %d\n"
+		"\tEntry size: %d\n"
+		"\tLow Threshold: %d\n",
+		ring->ring_id, ring->mac_id,
+		ring->ring_base_paddr, ring->num_entries,
+		ring->flags, ring->ring_dir,
+		ring->entry_size, ring->low_threshold);
+	nss_trace("Ring Base Addresses:");
+	for (i = 0; i < NSS_WIFILI_MAX_SRNG_REG_GROUPS_MSG; i++) {
+		nss_trace("\t%x", ring->hwreg_base[i]);
+	}
+}
+
+/*
+ * nss_wifili_log_init_msg()
+ *	Log NSS WIFILI Init message.
+ */
+static void nss_wifili_log_init_msg(struct nss_wifili_msg *nwm)
+{
+	struct nss_wifili_init_msg *nwim __maybe_unused = &nwm->msg.init;
+	int32_t i;
+	nss_trace("%px: NSS WIFILI Init Message:\n"
+		"WIFILI HAL Source Ring Base Address: %x\n"
+		"WIFILI HAL Source Ring Shadow Read Pointer Address: %x\n"
+		"WIFILI HAL Source Ring Shadow Write Pointer Address: %x\n"
+		"WIFILI Number of Transmit Classifier data rings: %d\n"
+		"WIFILI Number of reorder rings: %d\n"
+		"WIFILI Flags for SoC initialization: %d\n"
+		"WIFILI Tx descriptor initialization number of software descriptors: %d"
+		"WIFILI Tx descriptor initialization number of software extended descriptors: %d"
+		"WIFILI Tx descriptor initialization number of descriptor pools: %d"
+		"WIFILI Tx descriptor initialization number of memory addresses: %d"
+		"WIFILI Tx descriptor initialization extended descriptor page number: %d"
+		"WIFILI Tx descriptor initialization number of software secriptors for second radio: %d"
+		"WIFILI Tx descriptor initialization number of software extended descriptors for second radio: %d",
+		nwim, nwim->hssm.dev_base_addr,
+		nwim->hssm.shadow_rdptr_mem_addr, nwim->hssm.shadow_wrptr_mem_addr,
+		nwim->num_tcl_data_rings, nwim->num_reo_dest_rings,
+		nwim->flags, nwim->wtdim.num_tx_desc,
+		nwim->wtdim.num_tx_desc_ext, nwim->wtdim.num_pool,
+		nwim->wtdim.num_memaddr, nwim->wtdim.ext_desc_page_num,
+		nwim->wtdim.num_tx_desc_2, nwim->wtdim.num_tx_desc_ext_2);
+	/*
+	 * Continuation of the log.
+	 */
+	nss_trace("WIFILI Tx descriptor initialization memory start address and size:");
+	for (i = 0; i < NSS_WIFILI_MAX_NUMBER_OF_PAGE_MSG; i++) {
+		nss_trace("\tPage[%d]: Addr: %x Size: %d", i, nwim->wtdim.memory_addr[i], nwim->wtdim.memory_size[i]);
+	}
+	nss_trace("WIFILI Transmit Classifier data ring Information:");
+	for (i = 0; i < NSS_WIFILI_MAX_TCL_DATA_RINGS_MSG; i++) {
+		nss_wifili_log_wifili_hal_srng(&nwim->tcl_ring_info[i]);
+	}
+	nss_trace("WIFILI TX Completion Ring configuration information:");
+	for (i = 0; i < NSS_WIFILI_MAX_TCL_DATA_RINGS_MSG; i++) {
+		nss_wifili_log_wifili_hal_srng(&nwim->tx_comp_ring[i]);
+	}
+	nss_trace("WIFILI Reorder destination ring configuration information:");
+	for (i = 0; i < NSS_WIFILI_MAX_REO_DATA_RINGS_MSG; i++) {
+		nss_wifili_log_wifili_hal_srng(&nwim->reo_dest_ring[i]);
+	}
+	nss_trace("WIFILI Reorder exception ring configuration information:");
+	nss_wifili_log_wifili_hal_srng(&nwim->reo_exception_ring);
+	nss_trace("WIFILI Reinject ring configuration information:");
+	nss_wifili_log_wifili_hal_srng(&nwim->reo_reinject_ring);
+}
+
+/*
+ * nss_wifili_log_pdev_init_msg()
+ *	Log NSS WIFILI PDEV Init message.
+ */
+static void nss_wifili_log_pdev_init_msg(struct nss_wifili_msg *nwm)
+{
+	struct nss_wifili_pdev_init_msg *nwim __maybe_unused = &nwm->msg.pdevmsg;
+	nss_trace("%px: NSS WIFILI PDEV Init Message:\n"
+		"WIFILI Radio ID: %x\n"
+		"WIFILI MAC Hardware Mode: %d\n"
+		"WIFILI Lower MAC ID: %x\n",
+		nwim, nwim->radio_id,
+		nwim->hwmode, nwim->lmac_id);
+	/*
+	 * Continuation of the log.
+	 */
+	nss_trace("WIFILI Media Access Point ring information:");
+	nss_wifili_log_wifili_hal_srng(&nwim->rxdma_ring);
+}
+
+/*
+ * nss_wifili_log_pdev_init_msg()
+ *	Log NSS WIFILI PDEV Deinit message.
+ */
+static void nss_wifili_log_pdev_deinit_msg(struct nss_wifili_msg *nwm)
+{
+	struct nss_wifili_pdev_deinit_msg *nwim __maybe_unused = &nwm->msg.pdevdeinit;
+	nss_trace("%px: NSS WIFILI PDEV Deinit Message:\n"
+		"WIFILI Interface Number: %d\n",
+		nwim, nwim->ifnum);
+}
+
+/*
+ * nss_wifili_log_peer_msg()
+ *	Log NSS WIFILI Peer message.
+ */
+static void nss_wifili_log_peer_msg(struct nss_wifili_msg *nwm)
+{
+	struct nss_wifili_peer_msg *nwim __maybe_unused = &nwm->msg.peermsg;
+	nss_trace("%px: NSS WIFILI Peer Message:\n"
+		"WIFILI Peer MAC Address: %pM\n"
+		"WIFILI VAP ID: %d\n"
+		"WIFILI Peed ID: %d\n"
+		"WIFILI Hardware address search table index: %d\n"
+		"WIFILI NAWDS enabled for peer: %d\n"
+		"WIFILI peer memory adderss for NSS: %x\n",
+		nwim, nwim->peer_mac_addr,
+		nwim->vdev_id, nwim->peer_id,
+		nwim->hw_ast_idx, nwim->is_nawds,
+		nwim->nss_peer_mem);
+}
+
+/*
+ * nss_wifili_log_peer_freelist_append_msg()
+ *	Log NSS WIFILI Peer memory request message.
+ */
+static void nss_wifili_log_peer_freelist_append_msg(struct nss_wifili_msg *nwm)
+{
+	struct nss_wifili_peer_freelist_append_msg *nwim __maybe_unused = &nwm->msg.peer_freelist_append;
+	nss_trace("%px: NSS WIFILI Peer Memory Request Message:\n"
+		"WIFILI Starting Address of Freelist: %x\n"
+		"WIFILI Length: %d\n"
+		"WIFILI Maximum number of peer entries supported in pool: %d\n",
+		nwim, nwim->addr,
+		nwim->length, nwim->num_peers);
+}
+
+/*
+ * nss_wifili_log_wds_peer_msg()
+ *	Log NSS WIFILI WDS Peer message.
+ */
+static void nss_wifili_log_wds_peer_msg(struct nss_wifili_msg *nwm)
+{
+	struct nss_wifili_wds_peer_msg *nwim __maybe_unused = &nwm->msg.wdspeermsg;
+	nss_trace("%px: NSS WIFILI WDS Peer Message:\n"
+		"WIFILI Destination MAC: %pM\n"
+		"WIFILI Peer MAC: %pM\n",
+		nwim, nwim->dest_mac, nwim->peer_mac);
+}
+
+/*
+ * nss_wifili_log_wds_active_info_msg()
+ *	Log NSS WIFILI WDS Active Info message.
+ */
+static void nss_wifili_log_wds_active_info_msg(struct nss_wifili_msg *nwm)
+{
+	struct nss_wifili_wds_active_info_msg *nwim __maybe_unused = &nwm->msg.wdsinfomsg;
+	nss_trace("%px: NSS WIFILI WDS Active Info Message:\n"
+		"WIFILI Number OF Entries: %d\n"
+		"WIFILI Hardware AST Index: %d\n",
+		nwim, nwim->nentries, nwim->info[0].ast_idx);
+}
+
+/*
+ * nss_wifili_log_stats_cfg_msg()
+ *	Log NSS WIFILI Stats Configuration Message.
+ */
+static void nss_wifili_log_stats_cfg_msg(struct nss_wifili_msg *nwm)
+{
+	struct nss_wifili_stats_cfg_msg *nwim __maybe_unused = &nwm->msg.scm;
+	nss_trace("%px: NSS WIFILI Stats Config Message:\n"
+		"WIFILI Enable/Disable Config: %d\n",
+		nwim, nwim->cfg);
+}
+
+/*
+ * nss_wifili_log_reo_tidq_msg()
+ *	Log NSS WIFILI REO TIDQ Setup Message.
+ */
+static void nss_wifili_log_reo_tidq_msg(struct nss_wifili_msg *nwm)
+{
+	struct nss_wifili_reo_tidq_msg *nwim __maybe_unused = &nwm->msg.reotidqmsg;
+	nss_trace("%px: NSS WIFILI reo tidq setup Message:\n"
+		"WIFILI Traffic Identification Value: %d\n"
+		"WIFILI Peer ID: %d\n",
+		nwim, nwim->tid, nwim->peer_id);
+}
+
+/*
+ * nss_wifili_log_radio_cfg_msg()
+ *	Log NSS WIFILI Radio Command Message.
+ */
+static void nss_wifili_log_radio_cfg_msg(struct nss_wifili_msg *nwm)
+{
+	struct nss_wifili_radio_cfg_msg *nwim __maybe_unused = &nwm->msg.radiocfgmsg;
+	nss_trace("%px: NSS WIFILI Radio Command Message:\n"
+		"WIFILI Radio Interface Number %d\n",
+		nwim, nwim->radio_if_num);
+}
+
+/*
+ * nss_wifili_log_wds_extn_peer_cfg_msg()
+ *	Log NSS WIFILI WDS vendor extension configuration message.
+ */
+static void nss_wifili_log_wds_extn_peer_cfg_msg(struct nss_wifili_msg *nwm)
+{
+	struct nss_wifili_wds_extn_peer_cfg_msg *nwim __maybe_unused = &nwm->msg.wpeercfg;
+	nss_trace("%px: NSS WIFILI WDS vendor extension configuration message:\n"
+		"WIFILI Peer MAC Addr: %pM\n"
+		"WIFILI WDS Flags: %d\n"
+		"WIFILI Peer ID: %d\n",
+		nwim, nwim->peer_mac_addr,
+		nwim->wds_flags, nwim->peer_id);
+}
+
+/*
+ * nss_wifili_log_soc_linkdesc_buf_info_msg()
+ *	Log NSS WIFILI Link descriptor buffer address information.
+ */
+static void nss_wifili_log_soc_linkdesc_buf_info_msg(struct nss_wifili_msg *nwm)
+{
+	struct nss_wifili_soc_linkdesc_buf_info_msg *nwim __maybe_unused = &nwm->msg.linkdescinfomsg;
+	nss_trace("%px: NSS WIFILI Link descriptor buffer address information:\n"
+		"WIFILI Link Descriptor Low Address: %x\n"
+		"WIFILI Link Descriptor High Address: %x\n",
+		nwim, nwim->buffer_addr_low,
+		nwim->buffer_addr_high);
+}
+
+/*
+ * nss_wifili_log_peer_security_msg()
+ *	Log NSS WIFILI Peer Security Message.
+ */
+static void nss_wifili_log_peer_security_msg(struct nss_wifili_msg *nwm)
+{
+	struct nss_wifili_peer_security_type_msg *nwim __maybe_unused = &nwm->msg.securitymsg;
+	int32_t i;
+	nss_trace("%px: NSS WIFILI Peer Security Message:\n"
+		"WIFILI Peer ID: %d\n"
+		"WIFILI Packet Type: %d\n"
+		"WIFILI Security Type: %d\n",
+		nwim, nwim->peer_id,
+		nwim->pkt_type, nwim->security_type);
+	/*
+	 * Continuation of the log.
+	 */
+	nss_trace("WIFILI MIC KEY:");
+	for (i = 0; i < NSS_WIFILI_MIC_KEY_LEN; i++) {
+		nss_trace("\t%x", nwim->mic_key[i]);
+	}
+}
+
+/*
+ * nss_wifili_log_peer_nawds_enable_msg()
+ *	Log NSS WIFILI NAWDS enable for peer.
+ */
+static void nss_wifili_log_peer_nawds_enable_msg(struct nss_wifili_msg *nwm)
+{
+	struct nss_wifili_peer_nawds_enable_msg *nwim __maybe_unused = &nwm->msg.nawdsmsg;
+	nss_trace("%px: NSS WIFILI NAWDS enable for peer:\n"
+		"WIFILI Peer ID: %d\n"
+		"WIFILI Enable NAWDS: %d\n",
+		nwim, nwim->peer_id, nwim->is_nawds);
+}
+
+/*
+ * nss_wifili_log_dbdc_repeater_set_msg()
+ *	Log NSS WIFILI DBDC Repeaster Enable Message
+ */
+static void nss_wifili_log_dbdc_repeater_set_msg(struct nss_wifili_msg *nwm)
+{
+	struct nss_wifili_dbdc_repeater_set_msg *nwim __maybe_unused = &nwm->msg.dbdcrptrmsg;
+	nss_trace("%px: NSS WIFILI DBDC Repeater Enable Message:\n"
+		"WIFILI DBDC Enable Flag: %d\n",
+		nwim, nwim->is_dbdc_en);
+}
+
+/*
+ * nss_wifili_log_verbose()
+ *	Log message contents.
+ */
+static void nss_wifili_log_verbose(struct nss_wifili_msg *nwm)
+{
+	switch (nwm->cm.type) {
+	case NSS_WIFILI_INIT_MSG:
+		nss_wifili_log_init_msg(nwm);
+		break;
+
+	case NSS_WIFILI_SOC_RESET_MSG:
+		break;
+
+	case NSS_WIFILI_PDEV_INIT_MSG:
+		nss_wifili_log_pdev_init_msg(nwm);
+		break;
+
+	case NSS_WIFILI_PDEV_DEINIT_MSG:
+		nss_wifili_log_pdev_deinit_msg(nwm);
+		break;
+
+	case NSS_WIFILI_PEER_CREATE_MSG:
+	case NSS_WIFILI_PEER_DELETE_MSG:
+		nss_wifili_log_peer_msg(nwm);
+		break;
+
+	case NSS_WIFILI_PEER_FREELIST_APPEND_MSG:
+		nss_wifili_log_peer_freelist_append_msg(nwm);
+		break;
+
+	case NSS_WIFILI_WDS_VENDOR_MSG:
+		nss_wifili_log_wds_extn_peer_cfg_msg(nwm);
+		break;
+
+	case NSS_WIFILI_WDS_PEER_ADD_MSG:
+	case NSS_WIFILI_WDS_PEER_DEL_MSG:
+	case NSS_WIFILI_WDS_PEER_MAP_MSG:
+		nss_wifili_log_wds_peer_msg(nwm);
+		break;
+
+	case NSS_WIFILI_WDS_ACTIVE_INFO_MSG:
+		nss_wifili_log_wds_active_info_msg(nwm);
+		break;
+
+	case NSS_WIFILI_STATS_CFG_MSG:
+		nss_wifili_log_stats_cfg_msg(nwm);
+		break;
+
+	case NSS_WIFILI_TID_REOQ_SETUP_MSG:
+		nss_wifili_log_reo_tidq_msg(nwm);
+		break;
+
+	case NSS_WIFILI_RADIO_CMD_MSG:
+		nss_wifili_log_radio_cfg_msg(nwm);
+		break;
+
+	case NSS_WIFILI_LINK_DESC_INFO_MSG:
+		nss_wifili_log_soc_linkdesc_buf_info_msg(nwm);
+		break;
+
+	case NSS_WIFILI_PEER_SECURITY_TYPE_MSG:
+		nss_wifili_log_peer_security_msg(nwm);
+		break;
+
+	case NSS_WIFILI_PEER_NAWDS_ENABLE_MSG:
+		nss_wifili_log_peer_nawds_enable_msg(nwm);
+		break;
+
+	case NSS_WIFILI_DBDC_REPEATER_SET_MSG:
+		nss_wifili_log_dbdc_repeater_set_msg(nwm);
+		break;
+
+	case NSS_WIFILI_SOJOURN_STATS_MSG:
+	case NSS_DBDC_REPEATER_AST_FLUSH_MSG:
+	case NSS_WIFILI_SEND_PEER_MEMORY_REQUEST_MSG:
+	case NSS_WIFILI_PEER_STATS_MSG:
+	case NSS_WIFILI_RADIO_BUF_CFG:
+	case NSS_WIFILI_STATS_MSG:
+	case NSS_WIFILI_START_MSG:
+	case NSS_WIFILI_STOP_MSG:
+		/*
+		 * No log for these valid messages.
+		 */
+		break;
+
+	default:
+		nss_warning("%px: Invalid message type\n", nwm);
+		break;
+	}
+}
+
+/*
+ * nss_wifili_log_tx_msg()
+ *	Log messages transmitted to FW.
+ */
+void nss_wifili_log_tx_msg(struct nss_wifili_msg *nwm)
+{
+	if (nwm->cm.type >= NSS_WIFILI_MAX_MSG) {
+		nss_warning("%px: Invalid message type\n", nwm);
+		return;
+	}
+
+	nss_info("%px: type[%d]:%s\n", nwm, nwm->cm.type, nss_wifili_log_message_types_str[nwm->cm.type]);
+	nss_wifili_log_verbose(nwm);
+}
+
+/*
+ * nss_wifili_log_rx_msg()
+ *	Log messages received from FW.
+ */
+void nss_wifili_log_rx_msg(struct nss_wifili_msg *nwm)
+{
+	if (nwm->cm.response >= NSS_CMN_RESPONSE_LAST) {
+		nss_warning("%px: Invalid response\n", nwm);
+		return;
+	}
+
+	if (nwm->cm.response == NSS_CMN_RESPONSE_NOTIFY || (nwm->cm.response == NSS_CMN_RESPONSE_ACK)) {
+		nss_info("%px: type[%d]:%s, response[%d]:%s\n", nwm, nwm->cm.type,
+			nss_wifili_log_message_types_str[nwm->cm.type],
+			nwm->cm.response, nss_cmn_response_str[nwm->cm.response]);
+		goto verbose;
+	}
+
+	if (nwm->cm.error >= NSS_WIFILI_EMSG_UNKNOWN) {
+		nss_warning("%px: msg failure - type[%d]:%s, response[%d]:%s, error[%d]:Invalid error\n",
+			nwm, nwm->cm.type, nss_wifili_log_message_types_str[nwm->cm.type],
+			nwm->cm.response, nss_cmn_response_str[nwm->cm.response],
+			nwm->cm.error);
+		goto verbose;
+	}
+
+	nss_info("%px: msg nack - type[%d]:%s, response[%d]:%s, error[%d]:%s\n",
+		nwm, nwm->cm.type, nss_wifili_log_message_types_str[nwm->cm.type],
+		nwm->cm.response, nss_cmn_response_str[nwm->cm.response],
+		nwm->cm.error, nss_wifili_log_error_response_types_str[nwm->cm.error]);
+
+verbose:
+	nss_wifili_log_verbose(nwm);
+}
diff --git a/qca-nss-drv/nss_wifili_log.h b/qca-nss-drv/nss_wifili_log.h
new file mode 100644
index 0000000..a381ab6
--- /dev/null
+++ b/qca-nss-drv/nss_wifili_log.h
@@ -0,0 +1,37 @@
+/*
+ ******************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * ****************************************************************************
+ */
+
+#ifndef __NSS_WIFILI_LOG_H__
+#define __NSS_WIFILI_LOG_H__
+
+/*
+ * nss_WIFILI_log.h
+ *	NSS WIFILI Log Header File
+ */
+
+/*
+ * nss_WIFILI_log_tx_msg
+ *	Logs a WIFILI message that is sent to the NSS firmware.
+ */
+void nss_wifili_log_tx_msg(struct nss_wifili_msg *ncm);
+
+/*
+ * nss_WIFILI_log_rx_msg
+ *	Logs a WIFILI message that is received from the NSS firmware.
+ */
+void nss_wifili_log_rx_msg(struct nss_wifili_msg *ncm);
+
+#endif /* __NSS_WIFILI_LOG_H__ */
diff --git a/qca-nss-drv/nss_wifili_stats.c b/qca-nss-drv/nss_wifili_stats.c
new file mode 100644
index 0000000..5cc9218
--- /dev/null
+++ b/qca-nss-drv/nss_wifili_stats.c
@@ -0,0 +1,516 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_wifili_stats.c
+ *	NSS wifili statistics APIs
+ */
+
+#include "nss_tx_rx_common.h"
+#include "nss_core.h"
+#include "nss_wifili_if.h"
+#include "nss_wifili_stats.h"
+#include "nss_wifili_strings.h"
+
+/*
+ * Declare atomic notifier data structure for statistics.
+ */
+ATOMIC_NOTIFIER_HEAD(nss_wifili_stats_notifier);
+
+/*
+ * Statistics structures
+ * The structure will hold the statistics for 3 SOCs.
+ */
+struct nss_wifili_soc_stats soc_stats[NSS_WIFILI_MAX_SOC_NUM];
+
+/*
+ * nss_wifili_stats_read()
+ *	Read wifili statistics
+ */
+static ssize_t nss_wifili_stats_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	uint32_t i;
+
+	/*
+	 * max output lines = ((#stats + eight blank lines) * #WIFILI #STATS) + start/end tag + 3 blank
+	 * + Number of Extra outputlines for future reference to add new stats
+	 */
+	uint32_t max_pdev = 0;
+	uint32_t max_output_lines;
+	size_t size_al = 0;
+	size_t size_wr = 0;
+	ssize_t bytes_read = 0;
+	char *lbuf = NULL;
+	uint32_t soc_idx;
+	struct nss_wifili_stats *stats_wifili = NULL;
+
+	/*
+	 * Max number of pdev depends on type of soc (Internal/Attached).
+	 */
+	for (soc_idx = 0; soc_idx < NSS_WIFILI_MAX_SOC_NUM; soc_idx++) {
+		max_pdev += soc_stats[soc_idx].soc_maxpdev;
+	}
+
+	/*
+	 * Max pdev cannot be null.
+	 */
+	if (unlikely(max_pdev == 0)) {
+		nss_warning("Cannot have max pdev zero ");
+		return 0;
+	}
+
+	max_output_lines = (((NSS_WIFILI_STATS_MAX + 9) * max_pdev) +
+				NSS_WIFILI_STATS_WBM_MAX + NSS_STATS_EXTRA_OUTPUT_LINES);
+
+	size_al = NSS_STATS_MAX_STR_LENGTH * max_output_lines;
+
+	lbuf = kzalloc(size_al, GFP_KERNEL);
+	if (unlikely(lbuf == NULL)) {
+		nss_warning("Could not allocate memory for local statistics buffer");
+		return 0;
+	}
+
+	size_wr += nss_stats_banner(lbuf, size_wr, size_al, "wifili", NSS_STATS_SINGLE_CORE);
+
+	for (soc_idx = 0; soc_idx < NSS_WIFILI_MAX_SOC_NUM; soc_idx++) {
+		stats_wifili = &(soc_stats[soc_idx].stats_wifili);
+		for (i = 0; i < soc_stats[soc_idx].soc_maxpdev; i++) {
+
+			spin_lock_bh(&nss_top_main.stats_lock);
+			size_wr += nss_stats_print("wifili", "txrx", i
+					, nss_wifili_strings_stats_txrx
+					, stats_wifili->stats_txrx[i]
+					, NSS_WIFILI_STATS_TXRX_MAX
+					, lbuf, size_wr, size_al);
+			spin_unlock_bh(&nss_top_main.stats_lock);
+			size_wr += scnprintf(lbuf + size_wr
+					, size_al - size_wr, "\n");
+
+			/*
+			 * Filling TCL ring stats
+			 */
+			spin_lock_bh(&nss_top_main.stats_lock);
+			size_wr += nss_stats_print("wifili", "tcl ring", i
+					, nss_wifili_strings_stats_tcl
+					, stats_wifili->stats_tcl_ring[i]
+					, NSS_WIFILI_STATS_TCL_MAX
+					, lbuf, size_wr, size_al);
+			spin_unlock_bh(&nss_top_main.stats_lock);
+			size_wr += scnprintf(lbuf + size_wr
+					, size_al - size_wr, "\n");
+
+			/*
+			 * Filling TCL comp stats
+			 */
+			spin_lock_bh(&nss_top_main.stats_lock);
+			size_wr += nss_stats_print("wifili", "tcl comp", i
+					, nss_wifili_strings_stats_tx_comp
+					, stats_wifili->stats_tx_comp[i]
+					, NSS_WIFILI_STATS_TX_DESC_FREE_MAX
+					, lbuf, size_wr, size_al);
+			spin_unlock_bh(&nss_top_main.stats_lock);
+			size_wr += scnprintf(lbuf + size_wr
+					, size_al - size_wr, "\n");
+
+			/*
+			 * Filling reo ring stats
+			 */
+			spin_lock_bh(&nss_top_main.stats_lock);
+			size_wr += nss_stats_print("wifili", "reo ring", i
+					, nss_wifili_strings_stats_reo
+					, stats_wifili->stats_reo[i]
+					, NSS_WIFILI_STATS_REO_MAX
+					, lbuf, size_wr, size_al);
+
+			spin_unlock_bh(&nss_top_main.stats_lock);
+			size_wr += scnprintf(lbuf + size_wr
+					, size_al - size_wr, "\n");
+
+			/*
+			 * Filling TX SW Pool
+			 */
+			spin_lock_bh(&nss_top_main.stats_lock);
+			size_wr += nss_stats_print("wifili", "tx sw pool", i
+					, nss_wifili_strings_stats_txsw_pool
+					, stats_wifili->stats_tx_desc[i]
+					, NSS_WIFILI_STATS_TX_DESC_MAX
+					, lbuf, size_wr, size_al);
+			spin_unlock_bh(&nss_top_main.stats_lock);
+			size_wr += scnprintf(lbuf + size_wr
+					, size_al - size_wr, "\n");
+
+			/*
+			 * Filling TX EXt SW Pool
+			 */
+			spin_lock_bh(&nss_top_main.stats_lock);
+			size_wr += nss_stats_print("wifili", "tx ext sw pool", i
+					, nss_wifili_strings_stats_ext_txsw_pool
+					, stats_wifili->stats_ext_tx_desc[i]
+					, NSS_WIFILI_STATS_EXT_TX_DESC_MAX
+					, lbuf, size_wr, size_al);
+			spin_unlock_bh(&nss_top_main.stats_lock);
+			size_wr += scnprintf(lbuf + size_wr
+					, size_al - size_wr, "\n");
+
+			/*
+			 * Filling rxdma pool stats
+			 */
+			spin_lock_bh(&nss_top_main.stats_lock);
+			size_wr += nss_stats_print("wifili", "rxdma pool", i
+					, nss_wifili_strings_stats_rxdma_pool
+					, stats_wifili->stats_rx_desc[i]
+					, NSS_WIFILI_STATS_RX_DESC_MAX
+					, lbuf, size_wr, size_al);
+			spin_unlock_bh(&nss_top_main.stats_lock);
+			size_wr += scnprintf(lbuf + size_wr
+					, size_al - size_wr, "\n");
+
+			/*
+			 * Filling rxdma ring stats
+			 */
+			spin_lock_bh(&nss_top_main.stats_lock);
+			size_wr += nss_stats_print("wifili", "rxdma ring", i
+					, nss_wifili_strings_stats_rxdma_ring
+					, stats_wifili->stats_rxdma[i]
+					, NSS_WIFILI_STATS_RXDMA_DESC_MAX
+					, lbuf, size_wr, size_al);
+			spin_unlock_bh(&nss_top_main.stats_lock);
+			size_wr += scnprintf(lbuf + size_wr
+					, size_al - size_wr, "\n");
+		}
+
+		/*
+		 * Filling wbm ring stats
+		 */
+		spin_lock_bh(&nss_top_main.stats_lock);
+		size_wr += nss_stats_print("wifili", "wbm ring"
+				, NSS_STATS_SINGLE_INSTANCE
+				, nss_wifili_strings_stats_wbm
+				, stats_wifili->stats_wbm
+				, NSS_WIFILI_STATS_WBM_MAX
+				, lbuf, size_wr, size_al);
+		spin_unlock_bh(&nss_top_main.stats_lock);
+		size_wr += scnprintf(lbuf + size_wr, size_al - size_wr, "\n");
+	}
+
+	bytes_read = simple_read_from_buffer(ubuf, sz, ppos, lbuf, strlen(lbuf));
+	kfree(lbuf);
+
+	return bytes_read;
+}
+
+/*
+ * wifili_stats_ops
+ */
+NSS_STATS_DECLARE_FILE_OPERATIONS(wifili);
+
+/*
+ * nss_wifili_stats_dentry_create()
+ *	Create wifili statistics debug entry.
+ */
+void nss_wifili_stats_dentry_create(void)
+{
+	nss_stats_create_dentry("wifili", &nss_wifili_stats_ops);
+}
+
+/*
+ * nss_wifili_stats_sync()
+ *	Handle the syncing of WIFI stats.
+ */
+void nss_wifili_stats_sync(struct nss_ctx_instance *nss_ctx,
+		struct nss_wifili_stats_sync_msg *wlsoc_stats, uint16_t interface)
+{
+	struct nss_top_instance *nss_top = nss_ctx->nss_top;
+	struct nss_wifili_soc_stats *nwss = NULL;
+	struct nss_wifili_stats *stats = NULL;
+	struct nss_wifili_device_stats *devstats = &wlsoc_stats->stats;
+	uint32_t index;
+
+	/*
+	 * Max number of pdev depends on type of soc (Internal/Attached).
+	 */
+	switch (interface) {
+	case NSS_WIFILI_INTERNAL_INTERFACE:
+		nwss = &soc_stats[0];
+		nwss->soc_maxpdev = NSS_WIFILI_MAX_PDEV_NUM_MSG;
+		break;
+
+	case NSS_WIFILI_EXTERNAL_INTERFACE0:
+		nwss = &soc_stats[1];
+		nwss->soc_maxpdev = NSS_WIFILI_SOC_ATTACHED_MAX_PDEV_NUM;
+		break;
+
+	case NSS_WIFILI_EXTERNAL_INTERFACE1:
+		nwss = &soc_stats[2];
+		nwss->soc_maxpdev = NSS_WIFILI_SOC_ATTACHED_MAX_PDEV_NUM;
+		break;
+
+	default:
+		nss_warning("%px: Invalid wifili interface\n", nss_ctx);
+		return;
+	}
+
+	/*
+	 * Wifili statistics structure.
+	 */
+	stats = &(nwss->stats_wifili);
+
+	spin_lock_bh(&nss_top->stats_lock);
+
+	for (index = 0; index < nwss->soc_maxpdev; index++) {
+		/*
+		 * Rx stats
+		 */
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_MSDU_ERROR] +=
+							devstats->rx_data_stats[index].rx_msdu_err;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_INV_PEER_RCV] +=
+							(devstats->rx_data_stats[index].rx_inv_peer +
+							devstats->rx_data_stats[index].rx_scatter_inv_peer);
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_WDS_SRCPORT_EXCEPTION] +=
+							devstats->rx_data_stats[index].rx_wds_learn_send;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_WDS_SRCPORT_EXCEPTION_FAIL] +=
+							devstats->rx_data_stats[index].rx_wds_learn_send_fail;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_DELIVERD] +=
+							devstats->rx_data_stats[index].rx_deliver_cnt;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_DELIVER_DROPPED] +=
+							devstats->rx_data_stats[index].rx_deliver_cnt_fail;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_INTRA_BSS_UCAST] +=
+							devstats->rx_data_stats[index].rx_intra_bss_ucast_send;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_INTRA_BSS_UCAST_FAIL] +=
+							devstats->rx_data_stats[index].rx_intra_bss_ucast_send_fail;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_INTRA_BSS_MCAST] +=
+							devstats->rx_data_stats[index].rx_intra_bss_mcast_send;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_INTRA_BSS_MCAST_FAIL] +=
+							devstats->rx_data_stats[index].rx_intra_bss_mcast_send_fail;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_SG_RCV_SEND] +=
+							devstats->rx_data_stats[index].rx_sg_recv_send;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_SG_RCV_FAIL] +=
+							devstats->rx_data_stats[index].rx_sg_recv_fail;
+		stats->stats_txrx[index][NSS_STATS_WIFILI_RX_MCAST_ECHO] +=
+							devstats->rx_data_stats[index].rx_me_pkts;
+		stats->stats_txrx[index][NSS_STATS_WIFILI_RX_INV_TID] +=
+							devstats->rx_data_stats[index].rx_inv_tid;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_FRAG_INV_SC] +=
+							devstats->rx_data_stats[index].rx_frag_inv_sc;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_FRAG_INV_FC] +=
+							devstats->rx_data_stats[index].rx_frag_inv_fc;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_FRAG_NON_FRAG] +=
+							devstats->rx_data_stats[index].rx_non_frag_err;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_FRAG_RETRY] +=
+							devstats->rx_data_stats[index].rx_repeat_fragno;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_FRAG_OOO] +=
+							devstats->rx_data_stats[index].rx_ooo_frag;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_FRAG_OOO_SEQ] +=
+							devstats->rx_data_stats[index].rx_ooo_frag_seq;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_FRAG_ALL_FRAG_RCV] +=
+							devstats->rx_data_stats[index].rx_all_frag_rcv;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_RX_FRAG_DELIVER] +=
+							devstats->rx_data_stats[index].rx_frag_deliver;
+
+		/*
+		 * Tx stats
+		 */
+		stats->stats_txrx[index][NSS_WIFILI_STATS_TX_ENQUEUE] +=
+							devstats->tx_data_stats[index].tx_enqueue_cnt;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_TX_ENQUEUE_DROP] +=
+							devstats->tx_data_stats[index].tx_enqueue_dropped;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_TX_DEQUEUE] +=
+							devstats->tx_data_stats[index].tx_dequeue_cnt;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_TX_HW_ENQUEUE_FAIL] +=
+							devstats->tx_data_stats[index].tx_send_fail_cnt;
+		stats->stats_txrx[index][NSS_WIFILI_STATS_TX_SENT_COUNT] +=
+							devstats->tx_data_stats[index].tx_processed_pkt;
+	}
+
+	/*
+	 * update the tcl ring stats
+	 */
+	for (index = 0; index < NSS_WIFILI_MAX_TCL_DATA_RINGS_MSG; index++) {
+		stats->stats_tcl_ring[index][NSS_WIFILI_STATS_TCL_NO_HW_DESC] +=
+							devstats->tcl_stats[index].tcl_no_hw_desc;
+		stats->stats_tcl_ring[index][NSS_WIFILI_STATS_TCL_RING_FULL] +=
+							devstats->tcl_stats[index].tcl_ring_full;
+		stats->stats_tcl_ring[index][NSS_WIFILI_STATS_TCL_RING_SENT] +=
+							devstats->tcl_stats[index].tcl_ring_sent;
+	}
+
+	/*
+	 * update the tcl comp stats
+	 */
+	for (index = 0; index < NSS_WIFILI_MAX_TCL_DATA_RINGS_MSG; index++) {
+		stats->stats_tx_comp[index][NSS_WIFILI_STATS_TX_DESC_FREE_INV_BUFSRC] +=
+								devstats->txcomp_stats[index].invalid_bufsrc;
+		stats->stats_tx_comp[index][NSS_WIFILI_STATS_TX_DESC_FREE_INV_COOKIE] +=
+								devstats->txcomp_stats[index].invalid_cookie;
+		stats->stats_tx_comp[index][NSS_WIFILI_STATS_TX_DESC_FREE_HW_RING_EMPTY] +=
+								devstats->txcomp_stats[index].hw_ring_empty;
+		stats->stats_tx_comp[index][NSS_WIFILI_STATS_TX_DESC_FREE_REAPED] +=
+								devstats->txcomp_stats[index].ring_reaped;
+		stats->stats_tx_comp[index][NSS_WIFILI_STATS_TX_CAPTURE_ENQUEUE] +=
+								devstats->txcomp_stats[index].tx_cap_enqueue_count;
+		stats->stats_tx_comp[index][NSS_WIFILI_STATS_TX_CAPTURE_ENQUEUE_FAIL] +=
+								devstats->txcomp_stats[index].tx_cap_enqueue_fail_count;
+	}
+
+	/*
+	 * update reo ring stats
+	 */
+	for (index = 0; index < NSS_WIFILI_MAX_REO_DATA_RINGS_MSG; index++) {
+		stats->stats_reo[index][NSS_WIFILI_STATS_REO_ERROR] +=
+								devstats->rxreo_stats[index].ring_error;
+		stats->stats_reo[index][NSS_WIFILI_STATS_REO_REAPED] +=
+								devstats->rxreo_stats[index].ring_reaped;
+		stats->stats_reo[index][NSS_WIFILI_STATS_REO_INV_COOKIE] +=
+								devstats->rxreo_stats[index].invalid_cookie;
+		stats->stats_reo[index][NSS_WIFILI_STATS_REO_FRAG_RCV] +=
+								devstats->rxreo_stats[index].defrag_reaped;
+	}
+
+	/*
+	 * update tx sw pool
+	 */
+	for (index = 0; index < NSS_WIFILI_MAX_TXDESC_POOLS_MSG; index++) {
+		stats->stats_tx_desc[index][NSS_WIFILI_STATS_TX_DESC_IN_USE] =
+								devstats->tx_sw_pool_stats[index].desc_alloc;
+		stats->stats_tx_desc[index][NSS_WIFILI_STATS_TX_DESC_ALLOC_FAIL] +=
+								devstats->tx_sw_pool_stats[index].desc_alloc_fail;
+		stats->stats_tx_desc[index][NSS_WIFILI_STATS_TX_DESC_ALREADY_ALLOCATED] +=
+								devstats->tx_sw_pool_stats[index].desc_already_allocated;
+		stats->stats_tx_desc[index][NSS_WIFILI_STATS_TX_DESC_INVALID_FREE] +=
+								devstats->tx_sw_pool_stats[index].desc_invalid_free;
+		stats->stats_tx_desc[index][NSS_WIFILI_STATS_TX_DESC_FREE_SRC_FW] +=
+								devstats->tx_sw_pool_stats[index].tx_rel_src_fw;
+		stats->stats_tx_desc[index][NSS_WIFILI_STATS_TX_DESC_FREE_COMPLETION] +=
+								devstats->tx_sw_pool_stats[index].tx_rel_tx_desc;
+		stats->stats_tx_desc[index][NSS_WIFILI_STATS_TX_DESC_NO_PB] +=
+								devstats->tx_sw_pool_stats[index].tx_rel_no_pb;
+		stats->stats_tx_desc[index][NSS_WIFILI_STATS_TX_QUEUELIMIT_DROP] +=
+								devstats->tx_sw_pool_stats[index].tx_queue_limit_drop;
+	}
+
+	/*
+	 * update ext tx desc pool stats
+	 */
+	for (index = 0; index < NSS_WIFILI_MAX_TX_EXT_DESC_POOLS_MSG; index++) {
+		stats->stats_ext_tx_desc[index][NSS_WIFILI_STATS_EXT_TX_DESC_IN_USE] =
+								devstats->tx_ext_sw_pool_stats[index].desc_alloc;
+		stats->stats_ext_tx_desc[index][NSS_WIFILI_STATS_EXT_TX_DESC_ALLOC_FAIL] +=
+								devstats->tx_ext_sw_pool_stats[index].desc_alloc_fail;
+		stats->stats_ext_tx_desc[index][NSS_WIFILI_STATS_EXT_TX_DESC_ALREADY_ALLOCATED] +=
+								devstats->tx_ext_sw_pool_stats[index].desc_already_allocated;
+		stats->stats_ext_tx_desc[index][NSS_WIFILI_STATS_EXT_TX_DESC_INVALID_FREE] +=
+								devstats->tx_ext_sw_pool_stats[index].desc_invalid_free;
+	}
+
+	/*
+	 * update rx desc pool stats
+	 */
+	for (index = 0; index < nwss->soc_maxpdev; index++) {
+		stats->stats_rx_desc[index][NSS_WIFILI_STATS_RX_DESC_NO_PB] +=
+								devstats->rx_sw_pool_stats[index].rx_no_pb;
+		stats->stats_rx_desc[index][NSS_WIFILI_STATS_RX_DESC_ALLOC_FAIL] +=
+								devstats->rx_sw_pool_stats[index].desc_alloc_fail;
+		stats->stats_rx_desc[index][NSS_WIFILI_STATS_RX_DESC_IN_USE] =
+								devstats->rx_sw_pool_stats[index].desc_alloc;
+	}
+
+	/*
+	 * update rx dma ring stats
+	 */
+	for (index = 0; index < nwss->soc_maxpdev; index++) {
+		stats->stats_rxdma[index][NSS_WIFILI_STATS_RXDMA_DESC_UNAVAILABLE] +=
+								devstats->rxdma_stats[index].rx_hw_desc_unavailable;
+		stats->stats_rxdma[index][NSS_WIFILI_STATS_RXDMA_BUF_REPLENISHED] +=
+								devstats->rxdma_stats[index].rx_buf_replenished;
+	}
+
+	/*
+	 * update wbm ring stats
+	 */
+	stats->stats_wbm[NSS_WIFILI_STATS_WBM_IE_LOCAL_ALLOC_FAIL] += devstats->rxwbm_stats.invalid_buf_mgr;
+	stats->stats_wbm[NSS_WIFILI_STATS_WBM_SRC_DMA] += devstats->rxwbm_stats.err_src_rxdma;
+	stats->stats_wbm[NSS_WIFILI_STATS_WBM_SRC_DMA_CODE_INV] += devstats->rxwbm_stats.err_src_rxdma_code_inv;
+	stats->stats_wbm[NSS_WIFILI_STATS_WBM_SRC_REO] += devstats->rxwbm_stats.err_src_reo;
+	stats->stats_wbm[NSS_WIFILI_STATS_WBM_SRC_REO_CODE_NULLQ] += devstats->rxwbm_stats.err_src_reo_code_nullq;
+	stats->stats_wbm[NSS_WIFILI_STATS_WBM_SRC_REO_CODE_INV] += devstats->rxwbm_stats.err_src_reo_code_inv;
+	stats->stats_wbm[NSS_WIFILI_STATS_WBM_SRC_INV] += devstats->rxwbm_stats.err_src_invalid;
+	spin_unlock_bh(&nss_top->stats_lock);
+	return;
+}
+
+/*
+ * nss_wifili_stats_notify()
+ *	Sends notifications to the registered modules.
+ *
+ * Leverage NSS-FW statistics timing to update Netlink.
+ */
+void nss_wifili_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num)
+{
+	struct nss_wifili_stats_notification *wifili_stats;
+	uint32_t index = 0;
+
+	wifili_stats = kzalloc(sizeof(struct nss_wifili_stats_notification), GFP_ATOMIC);
+	if (!wifili_stats) {
+		nss_warning("%px: Failed to allocate memory for wifili stats\n", nss_ctx);
+		return;
+	}
+
+	wifili_stats->core_id = nss_ctx->id;
+	switch (if_num) {
+	case NSS_WIFILI_INTERNAL_INTERFACE:
+		index = 0;
+		break;
+
+	case NSS_WIFILI_EXTERNAL_INTERFACE0:
+		index = 1;
+		break;
+
+	case NSS_WIFILI_EXTERNAL_INTERFACE1:
+		index = 2;
+		break;
+
+	default:
+		nss_warning("%px: Invalid wifili interface\n", nss_ctx);
+		goto done;
+	}
+	wifili_stats->if_num = if_num;
+	memcpy(&wifili_stats->stats, &soc_stats[index].stats_wifili, sizeof(wifili_stats->stats));
+	atomic_notifier_call_chain(&nss_wifili_stats_notifier, NSS_STATS_EVENT_NOTIFY, (void *)wifili_stats);
+
+done:
+	kfree(wifili_stats);
+	return;
+}
+
+/*
+ * nss_wifili_stats_register_notifier()
+ *	Registers statistics notifier.
+ */
+int nss_wifili_stats_register_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&nss_wifili_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_wifili_stats_register_notifier);
+
+/*
+ * nss_wifili_stats_unregister_notifier()
+ *	Deregisters statistics notifier.
+ */
+int nss_wifili_stats_unregister_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&nss_wifili_stats_notifier, nb);
+}
+EXPORT_SYMBOL(nss_wifili_stats_unregister_notifier);
diff --git a/qca-nss-drv/nss_wifili_stats.h b/qca-nss-drv/nss_wifili_stats.h
new file mode 100644
index 0000000..9c073ce
--- /dev/null
+++ b/qca-nss-drv/nss_wifili_stats.h
@@ -0,0 +1,35 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * nss_wifili_stats.h
+ *	NSS wifili statistics header file.
+ */
+
+#ifndef __NSS_WIFILI_STATS_H
+#define __NSS_WIFILI_STATS_H
+
+#include "nss_core.h"
+#include "nss_wifili_if.h"
+
+/*
+ * NSS wifili statistics APIs
+ */
+extern void nss_wifili_stats_notify(struct nss_ctx_instance *nss_ctx, uint32_t if_num);
+extern void nss_wifili_stats_sync(struct nss_ctx_instance *nss_ctx, struct nss_wifili_stats_sync_msg *wlsoc_stats, uint16_t interface);
+extern void nss_wifili_stats_dentry_create(void);
+
+#endif /* __NSS_WIFILI_STATS_H */
diff --git a/qca-nss-drv/nss_wifili_strings.c b/qca-nss-drv/nss_wifili_strings.c
new file mode 100644
index 0000000..de224ec
--- /dev/null
+++ b/qca-nss-drv/nss_wifili_strings.c
@@ -0,0 +1,368 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include "nss_stats.h"
+#include "nss_core.h"
+#include <nss_wifili_if.h>
+#include "nss_strings.h"
+#include "nss_wifili_strings.h"
+
+/*
+ * nss_wifili_strings_stats_txrx
+ *	wifili txrx statistics
+ */
+struct nss_stats_info nss_wifili_strings_stats_txrx[NSS_WIFILI_STATS_TXRX_MAX] = {
+	{"rx_msdu_error"			, NSS_STATS_TYPE_ERROR},
+	{"rx_inv_peer_rcv"			, NSS_STATS_TYPE_SPECIAL},
+	{"rx_wds_srcport_exception"		, NSS_STATS_TYPE_EXCEPTION},
+	{"rx_wds_srcport_exception_fail"	, NSS_STATS_TYPE_DROP},
+	{"rx_deliverd"				, NSS_STATS_TYPE_SPECIAL},
+	{"rx_deliver_drops"			, NSS_STATS_TYPE_DROP},
+	{"rx_intra_bss_ucast"			, NSS_STATS_TYPE_SPECIAL},
+	{"rx_intra_bss_ucast_fail"		, NSS_STATS_TYPE_DROP},
+	{"rx_intra_bss_mcast"			, NSS_STATS_TYPE_SPECIAL},
+	{"rx_intra_bss_mcast_fail"		, NSS_STATS_TYPE_DROP},
+	{"rx_sg_rcv_send"			, NSS_STATS_TYPE_SPECIAL},
+	{"rx_sg_rcv_fail"			, NSS_STATS_TYPE_DROP},
+	{"rx_mcast_echo"			, NSS_STATS_TYPE_SPECIAL},
+	{"rx_inv_tid"				, NSS_STATS_TYPE_SPECIAL},
+	{"stats_rx_frag_inv_sc"			, NSS_STATS_TYPE_SPECIAL},
+	{"stats_rx_frag_inv_fc"			, NSS_STATS_TYPE_SPECIAL},
+	{"stats_rx_frag_non_frag"		, NSS_STATS_TYPE_SPECIAL},
+	{"stats_rx_frag_retry"			, NSS_STATS_TYPE_SPECIAL},
+	{"stats_rx_frag_ooo"			, NSS_STATS_TYPE_SPECIAL},
+	{"stats_rx_frag_ooo_seq"		, NSS_STATS_TYPE_SPECIAL},
+	{"stats_rx_frag_all_frag_rcv"		, NSS_STATS_TYPE_SPECIAL},
+	{"stats_rx_frag_deliver"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_enqueue"				, NSS_STATS_TYPE_SPECIAL},
+	{"tx_enqueue_drop"			, NSS_STATS_TYPE_DROP},
+	{"tx_dequeue"				, NSS_STATS_TYPE_SPECIAL},
+	{"tx_hw_enqueue_fail"			, NSS_STATS_TYPE_DROP},
+	{"tx_sent_count"			, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_wifili_strings_stats_tcl
+ *	wifili tcl stats
+ */
+struct nss_stats_info nss_wifili_strings_stats_tcl[NSS_WIFILI_STATS_TCL_MAX] = {
+	{"tcl_no_hw_desc"	, NSS_STATS_TYPE_SPECIAL},
+	{"tcl_ring_full"	, NSS_STATS_TYPE_SPECIAL},
+	{"tcl_ring_sent"	, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_wifili_strings_stats_tx_comp
+ *	wifili tx comp stats
+ */
+struct nss_stats_info nss_wifili_strings_stats_tx_comp[NSS_WIFILI_STATS_TX_DESC_FREE_MAX] = {
+	{"tx_desc_free_inv_bufsrc"		, NSS_STATS_TYPE_ERROR},
+	{"tx_desc_free_inv_cookie"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_desc_free_hw_ring_empty"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_desc_free_reaped"			, NSS_STATS_TYPE_SPECIAL},
+	{"tx_capture_enqueue_count"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_capture_enqueue_fail_count"	, NSS_STATS_TYPE_ERROR}
+};
+
+/*
+ * nss_wifili_strings_stats_reo
+ *	wifili tx reo stats
+ */
+struct nss_stats_info nss_wifili_strings_stats_reo[NSS_WIFILI_STATS_REO_MAX] = {
+	{"reo_error"		, NSS_STATS_TYPE_ERROR},
+	{"reo_reaped"		, NSS_STATS_TYPE_SPECIAL},
+	{"reo_inv_cookie"	, NSS_STATS_TYPE_SPECIAL},
+	{"stats_reo_frag_rcv"	, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_wifili_strings_stats_txsw_pool
+ *	wifili tx desc stats
+ */
+struct nss_stats_info nss_wifili_strings_stats_txsw_pool[NSS_WIFILI_STATS_TX_DESC_MAX] = {
+	{"tx_desc_in_use"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_desc_alloc_fail"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_desc_already_allocated"	, NSS_STATS_TYPE_SPECIAL},
+	{"tx_desc_invalid_free"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_desc_free_src_fw"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_desc_free_completion"	, NSS_STATS_TYPE_SPECIAL},
+	{"tx_desc_no_pb"		, NSS_STATS_TYPE_SPECIAL},
+	{"tx_desc_queuelimit_drop"	, NSS_STATS_TYPE_DROP}
+};
+
+/*
+ * nss_wifili_strings_stats_ext_txsw_pool
+ *	wifili tx ext desc stats
+ */
+struct nss_stats_info nss_wifili_strings_stats_ext_txsw_pool[NSS_WIFILI_STATS_EXT_TX_DESC_MAX] = {
+	{"ext_tx_desc_in_use"			, NSS_STATS_TYPE_SPECIAL},
+	{"ext_tx_desc_alloc_fail"		, NSS_STATS_TYPE_SPECIAL},
+	{"ext_tx_desc_already_allocated"	, NSS_STATS_TYPE_SPECIAL},
+	{"ext_tx_desc_invalid_free"		, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_wifili_strings_stats_rxdma_pool
+ *	wifili rx desc stats
+ */
+struct nss_stats_info nss_wifili_strings_stats_rxdma_pool[NSS_WIFILI_STATS_RX_DESC_MAX] = {
+	{"rx_desc_no_pb"	, NSS_STATS_TYPE_SPECIAL},
+	{"rx_desc_alloc_fail"	, NSS_STATS_TYPE_SPECIAL},
+	{"rx_desc_in_use"	, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_wifili_strings_stats_rxdma_ring
+ *	wifili rx dma ring stats
+ */
+struct nss_stats_info nss_wifili_strings_stats_rxdma_ring[NSS_WIFILI_STATS_RXDMA_DESC_MAX] = {
+	{"rxdma_hw_desc_unavailable"	, NSS_STATS_TYPE_SPECIAL},
+	{"rxdma_buf_replenished"	, NSS_STATS_TYPE_SPECIAL}
+};
+
+/*
+ * nss_wifili_strings_stats_wbm
+ *	wifili wbm ring stats
+ */
+struct nss_stats_info nss_wifili_strings_stats_wbm[NSS_WIFILI_STATS_WBM_MAX] = {
+	{"wbm_ie_local_alloc_fail"	, NSS_STATS_TYPE_ERROR},
+	{"wbm_src_dma"			, NSS_STATS_TYPE_SPECIAL},
+	{"wbm_src_dma_code_inv"		, NSS_STATS_TYPE_SPECIAL},
+	{"wbm_src_reo"			, NSS_STATS_TYPE_SPECIAL},
+	{"wbm_src_reo_code_nullq"	, NSS_STATS_TYPE_SPECIAL},
+	{"wbm_src_reo_code_inv"		, NSS_STATS_TYPE_ERROR},
+	{"wbm_src_inv"			, NSS_STATS_TYPE_ERROR}
+};
+
+/*
+ * nss_wifili_txrx_strings_read()
+ *	Read wifili Tx Rx statistics names.
+ */
+static ssize_t nss_wifili_txrx_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_wifili_strings_stats_txrx, NSS_WIFILI_STATS_TXRX_MAX);
+}
+
+/*
+ * nss_wifili_tcl_ring_strings_read()
+ *	Read wifili TCL ring statistics names.
+ */
+static ssize_t nss_wifili_tcl_ring_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_wifili_strings_stats_tcl, NSS_WIFILI_STATS_TCL_MAX);
+}
+
+/*
+ * nss_wifili_tcl_comp_strings_read()
+ *	Read wifili TCL comp statistics names.
+ */
+static ssize_t nss_wifili_tcl_comp_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_wifili_strings_stats_tx_comp, NSS_WIFILI_STATS_TX_DESC_FREE_MAX);
+}
+
+/*
+ * nss_wifili_reo_ring_strings_read()
+ *	Read wifili reorder ring statistics names.
+ */
+static ssize_t nss_wifili_reo_ring_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_wifili_strings_stats_reo, NSS_WIFILI_STATS_REO_MAX);
+}
+
+/*
+ * nss_wifili_tx_sw_strings_read()
+ *	Read wifili Tx sw statistics names.
+ */
+static ssize_t nss_wifili_tx_sw_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_wifili_strings_stats_txsw_pool, NSS_WIFILI_STATS_TX_DESC_MAX);
+}
+
+/*
+ * nss_wifili_tx_ext_sw_strings_read()
+ *	Read wifili Tx ext sw statistics names.
+ */
+static ssize_t nss_wifili_tx_ext_sw_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_wifili_strings_stats_ext_txsw_pool, NSS_WIFILI_STATS_EXT_TX_DESC_MAX);
+}
+
+/*
+ * nss_wifili_rx_dma_pool_strings_read()
+ *	Read wifili Rx DMA pool statistics names.
+ */
+static ssize_t nss_wifili_rx_dma_pool_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_wifili_strings_stats_rxdma_pool, NSS_WIFILI_STATS_RX_DESC_MAX);
+}
+
+/*
+ * nss_wifili_rx_dma_ring_strings_read()
+ *	Read wifili Rx DMA ring statistics names.
+ */
+static ssize_t nss_wifili_rx_dma_ring_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_wifili_strings_stats_rxdma_ring, NSS_WIFILI_STATS_RXDMA_DESC_MAX);
+}
+
+/*
+ * nss_wifili_wbm_ring_strings_read()
+ *	Read wifili WBM ring statistics names.
+ */
+static ssize_t nss_wifili_wbm_ring_strings_read(struct file *fp, char __user *ubuf, size_t sz, loff_t *ppos)
+{
+	return nss_strings_print(ubuf, sz, ppos, nss_wifili_strings_stats_wbm, NSS_WIFILI_STATS_WBM_MAX);
+}
+
+/*
+ * nss_wifili_txrx_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(wifili_txrx);
+
+/*
+ * nss_wifili_tcl_ring_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(wifili_tcl_ring);
+
+/*
+ * nss_wifili_tcl_comp_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(wifili_tcl_comp);
+
+/*
+ * nss_wifili_reo_ring_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(wifili_reo_ring);
+
+/*
+ * nss_wifili_tx_sw_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(wifili_tx_sw);
+
+/*
+ * nss_wifili_tx_ext_sw_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(wifili_tx_ext_sw);
+
+/*
+ * nss_wifili_rx_dma_pool_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(wifili_rx_dma_pool);
+
+/*
+ * nss_wifili_rx_dma_ring_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(wifili_rx_dma_ring);
+
+/*
+ * nss_wifili_wbm_ring_strings_ops
+ */
+NSS_STRINGS_DECLARE_FILE_OPERATIONS(wifili_wbm_ring);
+
+/*
+ * nss_wifili_strings_dentry_create()
+ *	Create wifili statistics strings debug entry.
+ */
+void nss_wifili_strings_dentry_create(void)
+{
+	struct dentry *wifili_d = NULL;
+	struct dentry *wifili_txrx_d = NULL;
+	struct dentry *wifili_tcl_ring_d = NULL;
+	struct dentry *wifili_tcl_comp_d = NULL;
+	struct dentry *wifili_reo_ring_d = NULL;
+	struct dentry *wifili_tx_sw_d = NULL;
+	struct dentry *wifili_tx_ext_sw_d = NULL;
+	struct dentry *wifili_rx_dma_pool_d = NULL;
+	struct dentry *wifili_rx_dma_ring_d = NULL;
+	struct dentry *wifili_wbm_ring_d = NULL;
+
+	if (!nss_top_main.strings_dentry) {
+		nss_warning("qca-nss-drv/strings is not present");
+		return;
+	}
+
+	wifili_d = debugfs_create_dir("wifili", nss_top_main.strings_dentry);
+	if (!wifili_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/wifili directory");
+		return;
+	}
+
+	wifili_txrx_d = debugfs_create_file("txrx_str", 0400, wifili_d, &nss_top_main, &nss_wifili_txrx_strings_ops);
+	if (!wifili_txrx_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/wifili/txrx_str file");
+		debugfs_remove_recursive(wifili_d);
+		return;
+	}
+
+	wifili_tcl_ring_d = debugfs_create_file("tcl_ring_str", 0400, wifili_d, &nss_top_main, &nss_wifili_tcl_ring_strings_ops);
+	if (!wifili_tcl_ring_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/wifili/tcl_ring_str file");
+		debugfs_remove_recursive(wifili_d);
+		return;
+	}
+
+	wifili_tcl_comp_d = debugfs_create_file("tcl_comp_str", 0400, wifili_d, &nss_top_main, &nss_wifili_tcl_comp_strings_ops);
+	if (!wifili_tcl_comp_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/wifili/tcl_comp_str file");
+		debugfs_remove_recursive(wifili_d);
+		return;
+	}
+
+	wifili_reo_ring_d = debugfs_create_file("reo_ring_str", 0400, wifili_d, &nss_top_main, &nss_wifili_reo_ring_strings_ops);
+	if (!wifili_reo_ring_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/wifili/reo_ring_str file");
+		debugfs_remove_recursive(wifili_d);
+		return;
+	}
+
+	wifili_tx_sw_d = debugfs_create_file("tx_sw_str", 0400, wifili_d, &nss_top_main, &nss_wifili_tx_sw_strings_ops);
+	if (!wifili_tx_sw_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/wifili/tx_sw_str file");
+		debugfs_remove_recursive(wifili_d);
+		return;
+	}
+
+	wifili_tx_ext_sw_d = debugfs_create_file("tx_ext_sw_str", 0400, wifili_d, &nss_top_main, &nss_wifili_tx_ext_sw_strings_ops);
+	if (!wifili_tx_ext_sw_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/wifili/tx_ext_sw_str file");
+		debugfs_remove_recursive(wifili_d);
+		return;
+	}
+
+	wifili_rx_dma_pool_d = debugfs_create_file("rx_dma_pool_str", 0400, wifili_d, &nss_top_main, &nss_wifili_rx_dma_pool_strings_ops);
+	if (!wifili_rx_dma_pool_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/wifili/rx_dma_pool_str file");
+		debugfs_remove_recursive(wifili_d);
+		return;
+	}
+
+	wifili_rx_dma_ring_d = debugfs_create_file("rx_dma_ring_str", 0400, wifili_d, &nss_top_main, &nss_wifili_rx_dma_ring_strings_ops);
+	if (!wifili_rx_dma_ring_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/wifili/rx_dma_ring_str file");
+		debugfs_remove_recursive(wifili_d);
+		return;
+	}
+
+	wifili_wbm_ring_d = debugfs_create_file("wbm_ring_str", 0400, wifili_d, &nss_top_main, &nss_wifili_wbm_ring_strings_ops);
+	if (!wifili_wbm_ring_d) {
+		nss_warning("Failed to create qca-nss-drv/strings/wifili/wbm_ring_str file");
+		debugfs_remove_recursive(wifili_d);
+		return;
+	}
+}
diff --git a/qca-nss-drv/nss_wifili_strings.h b/qca-nss-drv/nss_wifili_strings.h
new file mode 100644
index 0000000..263d172
--- /dev/null
+++ b/qca-nss-drv/nss_wifili_strings.h
@@ -0,0 +1,44 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_WIFILI_STRINGS_H
+#define __NSS_WIFILI_STRINGS_H
+
+/*
+ * Maximum string length:
+ * This should be equal to maximum string size of any stats
+ * inclusive of stats value
+ */
+#define NSS_WIFILI_STATS_MAX    (NSS_WIFILI_STATS_TXRX_MAX + NSS_WIFILI_STATS_TCL_MAX + \
+                                NSS_WIFILI_STATS_TX_DESC_FREE_MAX + NSS_WIFILI_STATS_REO_MAX + \
+                                NSS_WIFILI_STATS_TX_DESC_MAX + NSS_WIFILI_STATS_EXT_TX_DESC_MAX + \
+                                NSS_WIFILI_STATS_RX_DESC_MAX + NSS_WIFILI_STATS_RXDMA_DESC_MAX)
+
+extern struct nss_stats_info nss_wifili_strings_stats_txrx[NSS_WIFILI_STATS_TXRX_MAX];
+extern struct nss_stats_info nss_wifili_strings_stats_tcl[NSS_WIFILI_STATS_TCL_MAX];
+extern struct nss_stats_info nss_wifili_strings_stats_tx_comp[NSS_WIFILI_STATS_TX_DESC_FREE_MAX];
+extern struct nss_stats_info nss_wifili_strings_stats_reo[NSS_WIFILI_STATS_REO_MAX];
+extern struct nss_stats_info nss_wifili_strings_stats_txsw_pool[NSS_WIFILI_STATS_TX_DESC_MAX];
+extern struct nss_stats_info nss_wifili_strings_stats_ext_txsw_pool[NSS_WIFILI_STATS_EXT_TX_DESC_MAX];
+extern struct nss_stats_info nss_wifili_strings_stats_rxdma_pool[NSS_WIFILI_STATS_RX_DESC_MAX];
+extern struct nss_stats_info nss_wifili_strings_stats_rxdma_ring[NSS_WIFILI_STATS_RXDMA_DESC_MAX];
+extern struct nss_stats_info nss_wifili_strings_stats_wbm[NSS_WIFILI_STATS_WBM_MAX];
+
+extern void nss_wifili_strings_dentry_create(void);
+
+#endif /* __NSS_WIFILI_STRINGS_H */
diff --git a/qca-nss-ecm/.gitignore b/qca-nss-ecm/.gitignore
new file mode 100644
index 0000000..cb831ad
--- /dev/null
+++ b/qca-nss-ecm/.gitignore
@@ -0,0 +1,14 @@
+
+# Ignore general build intermediate files
+*.o
+*.cmd
+*.ko
+*.mod.*
+*.mod
+Module.symvers
+modules.order
+/.tmp_versions/
+built-in.a
+
+# don't ignore .gitignore itself
+!.gitignore
diff --git a/qca-nss-ecm/Makefile b/qca-nss-ecm/Makefile
new file mode 100644
index 0000000..8d3d02f
--- /dev/null
+++ b/qca-nss-ecm/Makefile
@@ -0,0 +1,428 @@
+##########################################################################
+# Copyright (c) 2014-2016, 2018-2021, The Linux Foundation. All rights reserved.
+# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+#
+# Permission to use, copy, modify, and/or distribute this software for
+# any purpose with or without fee is hereby granted, provided that the
+# above copyright notice and this permission notice appear in all copies.
+#
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+##########################################################################
+
+# ###################################################
+# Makefile for the QCA NSS ECM
+# ###################################################
+
+ifeq ($(ECM_FRONT_END_SFE_ENABLE), y)
+obj-m += examples/ecm_sfe_l2.o
+endif
+obj-m +=examples/ecm_ae_select.o
+
+obj-m += ecm.o
+ifeq ($(BUILD_ECM_WIFI_PLUGIN),y)
+obj-m += ecm_wifi_plugins/
+endif
+
+# #####################################################
+# Example builds.
+# Enable example build by using the menuconfig options.
+# #####################################################
+ifeq ($(EXAMPLES_BUILD_PCC),y)
+obj-m += examples/ecm_pcc_test.o
+endif
+ifeq ($(EXAMPLES_BUILD_MARK),y)
+obj-m += examples/ecm_mark_test.o
+endif
+ifeq ($(EXAMPLES_BUILD_OVS),y)
+obj-m += examples/ecm_ovs.o
+endif
+
+ecm-y := \
+	 frontends/cmn/ecm_ae_classifier.o \
+	 frontends/cmn/ecm_ipv4.o \
+	 frontends/cmn/ecm_ported_ipv4.o \
+	 ecm_tracker_udp.o \
+	 ecm_tracker_tcp.o \
+	 ecm_tracker_datagram.o \
+	 ecm_tracker.o \
+	 frontends/ecm_front_end_ipv4.o \
+	 frontends/ecm_front_end_common.o \
+	 ecm_db/ecm_db.o \
+	 ecm_db/ecm_db_connection.o \
+	 ecm_db/ecm_db_mapping.o \
+	 ecm_db/ecm_db_host.o \
+	 ecm_db/ecm_db_node.o \
+	 ecm_db/ecm_db_iface.o \
+	 ecm_db/ecm_db_listener.o \
+	 ecm_db/ecm_db_timer.o \
+	 ecm_classifier.o \
+	 ecm_classifier_default.o \
+	 ecm_interface.o \
+	 ecm_conntrack_notifier.o \
+	 ecm_init.o \
+	 ecm_notifier.o
+
+ecm-$(ECM_IPV6_ENABLE) += frontends/ecm_front_end_ipv6.o
+ecm-$(ECM_IPV6_ENABLE) += frontends/cmn/ecm_ipv6.o
+ecm-$(ECM_IPV6_ENABLE) += frontends/cmn/ecm_ported_ipv6.o
+ecm-$(ECM_NON_PORTED_SUPPORT_ENABLE) += frontends/cmn/ecm_non_ported_ipv4.o
+ifeq ($(ECM_NON_PORTED_SUPPORT_ENABLE), y)
+ecm-$(ECM_IPV6_ENABLE) += frontends/cmn/ecm_non_ported_ipv6.o
+endif
+ifeq ($(ECM_FRONT_END_NSS_ENABLE), y)
+ecm-$(ECM_MULTICAST_ENABLE) += frontends/cmn/ecm_multicast_ipv4.o
+ifeq ($(ECM_IPV6_ENABLE), y)
+ecm-$(ECM_MULTICAST_ENABLE) += frontends/cmn/ecm_multicast_ipv6.o
+endif
+endif
+
+# #############################################################################
+# Define ECM_FRONT_END_NSS_ENABLE=y in order to select
+# nss as ECM's front end.
+# #############################################################################
+ecm-$(ECM_FRONT_END_NSS_ENABLE) += frontends/nss/ecm_nss_common.o
+ecm-$(ECM_FRONT_END_NSS_ENABLE) += frontends/nss/ecm_nss_ipv4.o
+ecm-$(ECM_FRONT_END_NSS_ENABLE) += frontends/nss/ecm_nss_ported_ipv4.o
+ccflags-$(ECM_FRONT_END_NSS_ENABLE) += -DECM_FRONT_END_NSS_ENABLE
+
+# #############################################################################
+# Define ECM_FRONT_END_SFE_ENABLE=y in order to select
+# sfe as ECM's front end.
+# #############################################################################
+ecm-$(ECM_FRONT_END_SFE_ENABLE) += frontends/sfe/ecm_sfe_common.o
+ecm-$(ECM_FRONT_END_SFE_ENABLE) += frontends/sfe/ecm_sfe_ipv4.o
+ecm-$(ECM_FRONT_END_SFE_ENABLE) += frontends/sfe/ecm_sfe_ported_ipv4.o
+ccflags-$(ECM_FRONT_END_SFE_ENABLE) += -DECM_FRONT_END_SFE_ENABLE
+
+# #############################################################################
+# Define ECM_FRONT_END_CONN_LIMIT_ENABLE=y in order to limit accelerated
+# connections for low-memory profiles.
+# #############################################################################
+ccflags-$(ECM_FRONT_END_CONN_LIMIT_ENABLE) += -DECM_FRONT_END_CONN_LIMIT_ENABLE
+
+# #############################################################################
+# Define ECM_INTERFACE_BOND_ENABLE=y in order to enable
+# Bonding / Link Aggregation support.
+# #############################################################################
+ecm-$(ECM_INTERFACE_BOND_ENABLE) += frontends/cmn/ecm_bond_notifier.o
+ccflags-$(ECM_INTERFACE_BOND_ENABLE) += -DECM_INTERFACE_BOND_ENABLE
+
+# #############################################################################
+# Define ECM_INTERFACE_PPPOE_ENABLE=y in order
+# to enable support for PPPoE acceleration.
+# #############################################################################
+ccflags-$(ECM_INTERFACE_PPPOE_ENABLE) += -DECM_INTERFACE_PPPOE_ENABLE
+
+# #############################################################################
+# Define ECM_INTERFACE_L2TPV2_ENABLE=y in order
+# to enable support for l2tpv2 acceleration.
+# #############################################################################
+ccflags-$(ECM_INTERFACE_L2TPV2_ENABLE) += -DECM_INTERFACE_L2TPV2_ENABLE
+
+# #############################################################################
+# Define ECM_INTERFACE_PPTP_ENABLE=y in order
+# to enable support for pptp acceleration.
+# #############################################################################
+ccflags-$(ECM_INTERFACE_PPTP_ENABLE) += -DECM_INTERFACE_PPTP_ENABLE
+
+# #############################################################################
+# if pppoe, l2tpv2, pptp acceleration is enabled, ppp should
+# be enabled automatically
+# #############################################################################
+ECM_INTERFACE_PPP_ENABLE=y
+ifeq "$(ECM_INTERFACE_PPPOE_ENABLE)" "n"
+ifeq "$(ECM_INTERFACE_L2TPV2_ENABLE)" "n"
+ifeq "$(ECM_INTERFACE_PPTP_ENABLE)" "n"
+ECM_INTERFACE_PPP_ENABLE=n
+endif
+endif
+endif
+ccflags-$(ECM_INTERFACE_PPP_ENABLE) += -DECM_INTERFACE_PPP_ENABLE
+
+# #############################################################################
+# Define ECM_INTERFACE_GRE_TAP_ENABLE=y in order
+# to enable support for GRE TAP interface.
+# #############################################################################
+ccflags-$(ECM_INTERFACE_GRE_TAP_ENABLE) += -DECM_INTERFACE_GRE_TAP_ENABLE
+
+# #############################################################################
+# Define ECM_INTERFACE_GRE_TUN_ENABLE=y in order
+# to enable support for GRE TUN interface.
+# #############################################################################
+ccflags-$(ECM_INTERFACE_GRE_TUN_ENABLE) += -DECM_INTERFACE_GRE_TUN_ENABLE
+
+ifeq ($(ECM_IPV6_ENABLE), y)
+# #############################################################################
+# Define ECM_INTERFACE_SIT_ENABLE=y in order
+# to enable support for SIT interface.
+# #############################################################################
+ccflags-$(ECM_INTERFACE_SIT_ENABLE) += -DECM_INTERFACE_SIT_ENABLE
+
+# #############################################################################
+# Define ECM_INTERFACE_TUNIPIP6_ENABLE=y in order
+# to enable support for TUNIPIP6 interface.
+# #############################################################################
+ccflags-$(ECM_INTERFACE_TUNIPIP6_ENABLE) += -DECM_INTERFACE_TUNIPIP6_ENABLE
+
+# #############################################################################
+# Define ECM_INTERFACE_MAP_T_ENABLE=y in order
+# to enable support for MAP-T interface.
+# #############################################################################
+ccflags-$(ECM_INTERFACE_MAP_T_ENABLE) += -DECM_INTERFACE_MAP_T_ENABLE
+endif
+
+# #############################################################################
+# Define ECM_INTERFACE_RAWIP_ENABLE=y in order
+# to enable support for RAWIP interface.
+# #############################################################################
+ccflags-$(ECM_INTERFACE_RAWIP_ENABLE) += -DECM_INTERFACE_RAWIP_ENABLE
+
+# #############################################################################
+# Define ECM_INTERFACE_VXLAN_ENABLE=y in order
+# to enable support for VxLAN interface.
+# #############################################################################
+ccflags-$(ECM_INTERFACE_VXLAN_ENABLE) += -DECM_INTERFACE_VXLAN_ENABLE
+
+# #############################################################################
+# Define ECM_IPV6_ENABLE=y in order to enable IPv6 support in the ECM.
+# #############################################################################
+ccflags-$(ECM_IPV6_ENABLE) += -DECM_IPV6_ENABLE
+
+# #############################################################################
+# Define ECM_MULTICAST_ENABLE=y in order to enable support for ECM Multicast
+# #############################################################################
+ifeq ($(ECM_FRONT_END_NSS_ENABLE), y)
+ecm-$(ECM_MULTICAST_ENABLE) += frontends/nss/ecm_nss_multicast_ipv4.o
+ifeq ($(ECM_IPV6_ENABLE), y)
+ecm-$(ECM_MULTICAST_ENABLE) += frontends/nss/ecm_nss_multicast_ipv6.o
+endif
+ecm-$(ECM_MULTICAST_ENABLE) += ecm_db/ecm_db_multicast.o
+ccflags-$(ECM_MULTICAST_ENABLE) += -DECM_MULTICAST_ENABLE
+endif
+
+# #############################################################################
+# Define ECM_XFRM_ENABLE=y in order to enable
+# #############################################################################
+ifeq ($(ECM_FRONT_END_NSS_ENABLE), y)
+ccflags-$(ECM_XFRM_ENABLE) += -DECM_XFRM_ENABLE
+endif
+
+# #############################################################################
+# Define ECM_INTERFACE_OVS_BRIDGE_ENABLE=y in order to enable support for OVS
+# #############################################################################
+ccflags-$(ECM_INTERFACE_OVS_BRIDGE_ENABLE) += -DECM_INTERFACE_OVS_BRIDGE_ENABLE
+
+# #############################################################################
+# Define ECM_INTERFACE_VLAN_ENABLE=y in order to enable support for VLAN
+# #############################################################################
+ccflags-$(ECM_INTERFACE_VLAN_ENABLE) += -DECM_INTERFACE_VLAN_ENABLE
+
+# #############################################################################
+# Define ECM_INTERFACE_MACVLAN_ENABLE=y in order to enable support for MACVLAN
+# #############################################################################
+ccflags-$(ECM_INTERFACE_MACVLAN_ENABLE) += -DECM_INTERFACE_MACVLAN_ENABLE
+
+# #############################################################################
+# Define ECM_INTERFACE_IPSEC_ENABLE=y in order to enable support for IPSEC
+# #############################################################################
+ccflags-$(ECM_INTERFACE_IPSEC_ENABLE) += -DECM_INTERFACE_IPSEC_ENABLE
+
+ECM_INTERFACE_IPSEC_GLUE_LAYER_SUPPORT_ENABLE=n
+ifeq ($(SoC),$(filter $(SoC), ipq807x ipq807x_64 ipq60xx ipq60xx_64 ipq50xx ipq50xx_64))
+ECM_INTERFACE_IPSEC_GLUE_LAYER_SUPPORT_ENABLE=$(ECM_INTERFACE_IPSEC_ENABLE)
+ccflags-$(ECM_INTERFACE_IPSEC_GLUE_LAYER_SUPPORT_ENABLE) += -DECM_INTERFACE_IPSEC_GLUE_LAYER_SUPPORT_ENABLE
+endif
+
+ifeq ($(ECM_FRONT_END_NSS_ENABLE), y)
+ecm-$(ECM_IPV6_ENABLE) += frontends/nss/ecm_nss_ipv6.o
+ecm-$(ECM_IPV6_ENABLE) += frontends/nss/ecm_nss_ported_ipv6.o
+endif
+ifeq ($(ECM_FRONT_END_SFE_ENABLE), y)
+ecm-$(ECM_IPV6_ENABLE) += frontends/sfe/ecm_sfe_ipv6.o
+ecm-$(ECM_IPV6_ENABLE) += frontends/sfe/ecm_sfe_ported_ipv6.o
+endif
+
+# #############################################################################
+# Define ECM_CLASSIFIER_OVS_ENABLE=y in order to enable ovs classifier.
+# #############################################################################
+ecm-$(ECM_CLASSIFIER_OVS_ENABLE) += ecm_classifier_ovs.o
+ccflags-$(ECM_CLASSIFIER_OVS_ENABLE) += -DECM_CLASSIFIER_OVS_ENABLE
+
+# #############################################################################
+# Define ECM_CLASSIFIER_MARK_ENABLE=y in order to enable mark classifier.
+# #############################################################################
+ECM_CLASSIFIER_MARK_ENABLE=y
+ecm-$(ECM_CLASSIFIER_MARK_ENABLE) += ecm_classifier_mark.o
+ccflags-$(ECM_CLASSIFIER_MARK_ENABLE) += -DECM_CLASSIFIER_MARK_ENABLE
+
+# #############################################################################
+# Define ECM_CLASSIFIER_MSCS_ENABLE=y in order to enable mscs flow classifier.
+# #############################################################################
+ecm-$(ECM_CLASSIFIER_MSCS_ENABLE) += ecm_classifier_mscs.o
+ccflags-$(ECM_CLASSIFIER_MSCS_ENABLE) += -DECM_CLASSIFIER_MSCS_ENABLE
+
+# #############################################################################
+# Define ECM_CLASSIFIER_NL_ENABLE=y in order to enable NL classifier.
+# #############################################################################
+ecm-$(ECM_CLASSIFIER_NL_ENABLE) += ecm_classifier_nl.o
+ccflags-$(ECM_CLASSIFIER_NL_ENABLE) += -DECM_CLASSIFIER_NL_ENABLE
+
+# #############################################################################
+# Define ECM_CLASSIFIER_DSCP_ENABLE=y in order to enable DSCP classifier.
+# #############################################################################
+ECM_CLASSIFIER_DSCP_ENABLE=y
+ecm-$(ECM_CLASSIFIER_DSCP_ENABLE) += ecm_classifier_dscp.o
+ccflags-$(ECM_CLASSIFIER_DSCP_ENABLE) += -DECM_CLASSIFIER_DSCP_ENABLE
+ccflags-$(ECM_CLASSIFIER_DSCP_IGS) += -DECM_CLASSIFIER_DSCP_IGS
+
+# #############################################################################
+# Define ECM_CLASSIFIER_HYFI_ENABLE=y in order to enable
+# the Hy-Fi classifier in ECM. Currently disabled until the integration
+# with Hy-Fi is completed.
+# #############################################################################
+#
+ecm-$(ECM_CLASSIFIER_HYFI_ENABLE) += ecm_classifier_hyfi.o
+ccflags-$(ECM_CLASSIFIER_HYFI_ENABLE) += -DECM_CLASSIFIER_HYFI_ENABLE
+
+# #############################################################################
+# Define ECM_CLASSIFIER_PCC_ENABLE=y in order to enable
+# the Parental Controls subsystem classifier in ECM. Currently disabled until
+# customers require it / if they need to integrate their Parental Controls with it.
+# #############################################################################
+ECM_CLASSIFIER_PCC_ENABLE=y
+ecm-$(ECM_CLASSIFIER_PCC_ENABLE) += ecm_classifier_pcc.o
+ccflags-$(ECM_CLASSIFIER_PCC_ENABLE) += -DECM_CLASSIFIER_PCC_ENABLE
+
+# #############################################################################
+# Define ECM_CLASSIFIER_EMESH_ENABLE=y in order to enable E-Mesh classifier.
+# #############################################################################
+ecm-$(ECM_CLASSIFIER_EMESH_ENABLE) += ecm_classifier_emesh.o
+ccflags-$(ECM_CLASSIFIER_EMESH_ENABLE) += -DECM_CLASSIFIER_EMESH_ENABLE
+
+# #############################################################################
+# Define ECM_NON_PORTED_SUPPORT_ENABLE=y in order to enable non-ported protocol.
+# #############################################################################
+
+
+ifeq ($(ECM_FRONT_END_NSS_ENABLE), y)
+ecm-$(ECM_NON_PORTED_SUPPORT_ENABLE) += frontends/nss/ecm_nss_non_ported_ipv4.o
+ifeq ($(ECM_IPV6_ENABLE), y)
+ecm-$(ECM_NON_PORTED_SUPPORT_ENABLE) += frontends/nss/ecm_nss_non_ported_ipv6.o
+endif
+endif
+
+ifeq ($(ECM_FRONT_END_SFE_ENABLE), y)
+ecm-$(ECM_NON_PORTED_SUPPORT_ENABLE) += frontends/sfe/ecm_sfe_non_ported_ipv4.o
+ifeq ($(ECM_IPV6_ENABLE), y)
+ecm-$(ECM_NON_PORTED_SUPPORT_ENABLE) += frontends/sfe/ecm_sfe_non_ported_ipv6.o
+endif
+endif
+
+ccflags-$(ECM_NON_PORTED_SUPPORT_ENABLE) += -DECM_NON_PORTED_SUPPORT_ENABLE
+
+# #############################################################################
+# Define ECM_STATE_OUTPUT_ENABLE=y to support XML state output
+# #############################################################################
+ECM_STATE_OUTPUT_ENABLE=y
+ecm-$(ECM_STATE_OUTPUT_ENABLE) += ecm_state.o
+ccflags-$(ECM_STATE_OUTPUT_ENABLE) += -DECM_STATE_OUTPUT_ENABLE
+
+# #############################################################################
+# Define ECM_DB_ADVANCED_STATS_ENABLE to support XML state output
+# #############################################################################
+ECM_DB_ADVANCED_STATS_ENABLE=y
+ccflags-$(ECM_DB_ADVANCED_STATS_ENABLE) += -DECM_DB_ADVANCED_STATS_ENABLE
+
+# #############################################################################
+# Define ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y in order to enable
+# the database to track relationships between objects.
+# #############################################################################
+ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y
+ccflags-$(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) += -DECM_DB_XREF_ENABLE
+
+# #############################################################################
+# Define ECM_TRACKER_DPI_SUPPORT_ENABLE=y in order to enable support for
+# deep packet inspection and tracking of data with the trackers.
+# #############################################################################
+ECM_TRACKER_DPI_SUPPORT_ENABLE=y
+ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE) += -DECM_TRACKER_DPI_SUPPORT_ENABLE
+
+# #############################################################################
+# Define ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y in order to enable
+# support for the database keeping lists of connections that are assigned
+# on a per TYPE of classifier basis.
+# #############################################################################
+ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y
+ccflags-$(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) += -DECM_DB_CTA_TRACK_ENABLE
+
+# #############################################################################
+# Define ECM_BAND_STEERING_ENABLE=y in order to enable
+# band steering feature.
+# #############################################################################
+ECM_BAND_STEERING_ENABLE=y
+ccflags-$(ECM_BAND_STEERING_ENABLE) += -DECM_BAND_STEERING_ENABLE
+
+# #############################################################################
+# Define ECM_INTERFACE_OVPN_ENABLE=y in order
+# to enable support for OVPN acceleration.
+# #############################################################################
+ccflags-$(ECM_INTERFACE_OVPN_ENABLE) += -DECM_INTERFACE_OVPN_ENABLE
+
+# #############################################################################
+# Debug flags, set these to = 0 if you want to disable all debugging for that
+# file.
+# By turning off debugs you gain maximum ECM performance.
+# #############################################################################
+ccflags-y += -DECM_CLASSIFIER_DEBUG_LEVEL=1
+ccflags-y += -DECM_CLASSIFIER_OVS_DEBUG_LEVEL=1
+ccflags-y += -DECM_CLASSIFIER_MARK_DEBUG_LEVEL=1
+ccflags-y += -DECM_CLASSIFIER_DSCP_DEBUG_LEVEL=1
+ccflags-y += -DECM_CLASSIFIER_HYFI_DEBUG_LEVEL=1
+ccflags-y += -DECM_CLASSIFIER_PCC_DEBUG_LEVEL=1
+ccflags-y += -DECM_CLASSIFIER_NL_DEBUG_LEVEL=1
+ccflags-y += -DECM_CLASSIFIER_EMESH_DEBUG_LEVEL=1
+ccflags-y += -DECM_CLASSIFIER_MSCS_DEBUG_LEVEL=1
+ccflags-y += -DECM_CLASSIFIER_DEFAULT_DEBUG_LEVEL=1
+ccflags-y += -DECM_DB_DEBUG_LEVEL=1
+ccflags-y += -DECM_INIT_DEBUG_LEVEL=3
+ccflags-y += -DECM_FRONT_END_IPV4_DEBUG_LEVEL=1
+ccflags-y += -DECM_FRONT_END_IPV6_DEBUG_LEVEL=1
+ccflags-y += -DECM_FRONT_END_COMMON_DEBUG_LEVEL=1
+ccflags-y += -DECM_NSS_COMMON_DEBUG_LEVEL=1
+ccflags-y += -DECM_NSS_IPV4_DEBUG_LEVEL=1
+ccflags-y += -DECM_NSS_PORTED_IPV4_DEBUG_LEVEL=1
+ccflags-y += -DECM_NSS_NON_PORTED_IPV4_DEBUG_LEVEL=1
+ccflags-y += -DECM_NSS_MULTICAST_IPV4_DEBUG_LEVEL=1
+ccflags-y += -DECM_NSS_IPV6_DEBUG_LEVEL=1
+ccflags-y += -DECM_NSS_PORTED_IPV6_DEBUG_LEVEL=1
+ccflags-y += -DECM_NSS_NON_PORTED_IPV6_DEBUG_LEVEL=1
+ccflags-y += -DECM_NSS_MULTICAST_IPV6_DEBUG_LEVEL=1
+ccflags-y += -DECM_SFE_COMMON_DEBUG_LEVEL=1
+ccflags-y += -DECM_SFE_IPV4_DEBUG_LEVEL=1
+ccflags-y += -DECM_SFE_PORTED_IPV4_DEBUG_LEVEL=1
+ccflags-y += -DECM_SFE_NON_PORTED_IPV4_DEBUG_LEVEL=1
+ccflags-y += -DECM_SFE_IPV6_DEBUG_LEVEL=1
+ccflags-y += -DECM_SFE_PORTED_IPV6_DEBUG_LEVEL=1
+ccflags-y += -DECM_SFE_NON_PORTED_IPV6_DEBUG_LEVEL=1
+ccflags-y += -DECM_CONNTRACK_NOTIFIER_DEBUG_LEVEL=1
+ccflags-y += -DECM_TRACKER_DEBUG_LEVEL=1
+ccflags-y += -DECM_TRACKER_DATAGRAM_DEBUG_LEVEL=1
+ccflags-y += -DECM_TRACKER_TCP_DEBUG_LEVEL=1
+ccflags-y += -DECM_TRACKER_UDP_DEBUG_LEVEL=1
+ccflags-y += -DECM_BOND_NOTIFIER_DEBUG_LEVEL=1
+ccflags-y += -DECM_INTERFACE_DEBUG_LEVEL=1
+ccflags-y += -DECM_STATE_DEBUG_LEVEL=1
+ccflags-y += -DECM_OPENWRT_SUPPORT=1
+ccflags-y += -DECM_NOTIFIER_DEBUG_LEVEL=1
+ccflags-y += -DECM_AE_CLASSIFIER_DEBUG_LEVEL=1
+
+ccflags-y += -I$(obj)/ -I$(obj)/ecm_db -I$(obj)/frontends/include -I$(obj)/frontends/nss -I$(obj)/frontends/sfe -I$(obj)/frontends/cmn -I$(obj)/exports
+ccflags-y += -Werror
+
+obj ?= .
diff --git a/qca-nss-ecm/build.sh b/qca-nss-ecm/build.sh
new file mode 100755
index 0000000..452d82c
--- /dev/null
+++ b/qca-nss-ecm/build.sh
@@ -0,0 +1,102 @@
+#!/bin/bash
+
+set -e
+set -o errtrace
+trap 'echo Fatal error: script $0 aborting at line $LINENO, command \"$BASH_COMMAND\" returned $?; exit 1' ERR
+
+PRODUCT_LIST="sirocco"
+
+NUM_JOBS=$(grep -c processor /proc/cpuinfo)
+
+MODULE_NAME="qca-nss-ecm"
+###################################################
+# Setup build toollchain
+###################################################
+sdk_top_dir=$(readlink -e $(dirname $0)/..)
+TOP_DIR=$(readlink -e ${sdk_top_dir}/..)
+
+#export ARCH and build related envs.
+source ${TOP_DIR}/sdk/build_scripts/setup_env.sh
+
+kernel_path=$(readlink -e ${sdk_top_dir}/../kernel)
+qca_sfe_path=$(readlink -e ${sdk_top_dir}/qca-nss-sfe/)
+soc_type=ipq50xx
+extra_cflags="-I${qca_sfe_path}/exports"
+
+build_flags="ECM_CLASSIFIER_HYFI_ENABLE=n ECM_MULTICAST_ENABLE=n ECM_INTERFACE_IPSEC_ENABLE=n ECM_INTERFACE_PPTP_ENABLE=n ECM_INTERFACE_L2TPV2_ENABLE=n ECM_INTERFACE_GRE_TAP_ENABLE=n ECM_INTERFACE_GRE_TUN_ENABLE=n ECM_INTERFACE_SIT_ENABLE=n ECM_INTERFACE_TUNIPIP6_ENABLE=n ECM_INTERFACE_RAWIP_ENABLE=n ECM_INTERFACE_BOND_ENABLE=n ECM_XFRM_ENABLE=n ECM_FRONT_END_SFE_ENABLE=y ECM_NON_PORTED_SUPPORT_ENABLE=n ECM_INTERFACE_MAP_T_ENABLE=n ECM_INTERFACE_VXLAN_ENABLE=n ECM_INTERFACE_OVS_BRIDGE_ENABLE=n ECM_CLASSIFIER_OVS_ENABLE=n ECM_CLASSIFIER_DSCP_IGS=n ECM_IPV6_ENABLE=y ECM_FRONT_END_NSS_ENABLE=n EXAMPLES_BUILD_OVS=n"
+
+##################################################
+# Build Kernel Module
+##################################################
+function BuildKModule() {
+    # make kernel module
+    echo "Build ${MODULE_NAME}"
+    ${CROSS_MAKE} -C ${kernel_path} M=${sdk_top_dir}/${MODULE_NAME} ${build_flags} SoC=${soc_type} EXTRA_CFLAGS="${extra_cflags}" \
+	    KBUILD_EXTRA_SYMBOLS="${qca_sfe_path}/Module.symvers" V=1
+}
+
+##################################################
+# Build & Install
+##################################################
+function BuildAndInstall() {
+    local product=$1
+    local eureka_src_path=$(readlink -e $2)
+    if [ -z ${eureka_src_path} ]; then
+      echo "eureka_src_path doesn't exist"
+      exit 1
+    fi
+
+    # clean previous build
+    find . -name "*.o" -delete
+    find . -name "*.cmd" -delete
+    find . -name "*.ko" -delete
+    find . -name "*.mod.*" -delete
+    find . -name "*.mod" -delete
+    find . -name Module.symvers -delete
+
+    # build module
+    BuildKModule
+
+    # install module
+    echo "Install ${MODULE_NAME}.ko"
+    local module_target_dir="$(GetModulePath ${eureka_src_path} ${product})"
+    mkdir -p ${module_target_dir}
+    cp -f ecm.ko ${module_target_dir}/${MODULE_NAME}.ko
+    cp -f examples/ecm_sfe_l2.ko ${module_target_dir}
+}
+
+function Usage() {
+    cat << EOF
+Usage:
+    $0 <product> <eureka_src_path>
+    Valid products: ${PRODUCT_LIST}
+EOF
+}
+
+function IsProductValid() {
+  local product
+  local ret=1
+
+  for product in ${PRODUCT_LIST}; do
+    if [ "${product}" == "$1" ]; then
+      ret=0
+      break
+    fi
+  done
+
+  return ${ret}
+}
+
+#########################
+####### Main Entry ######
+#########################
+if (( $# < 2 )); then
+  Usage
+else
+  if IsProductValid $1; then
+    BuildAndInstall $1 $2
+  else
+    echo "$1 is a invalid product"
+    Usage
+  fi
+fi
diff --git a/qca-nss-ecm/ecm_classifier.c b/qca-nss-ecm/ecm_classifier.c
new file mode 100644
index 0000000..954ee60
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier.c
@@ -0,0 +1,272 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016, 2018-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <net/ip.h>
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/etherdevice.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_CLASSIFIER_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_db.h"
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+#include "ecm_classifier_nl.h"
+#endif
+#ifdef ECM_CLASSIFIER_HYFI_ENABLE
+#include "ecm_classifier_hyfi.h"
+#endif
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+#include "ecm_classifier_dscp.h"
+#endif
+#ifdef ECM_CLASSIFIER_PCC_ENABLE
+#include "ecm_classifier_pcc.h"
+#endif
+#ifdef ECM_CLASSIFIER_MARK_ENABLE
+#include "ecm_classifier_mark.h"
+#endif
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+#include "ecm_classifier_ovs.h"
+#endif
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+#include "ecm_classifier_emesh.h"
+#endif
+#ifdef ECM_CLASSIFIER_MSCS_ENABLE
+#include "ecm_classifier_mscs.h"
+#endif
+
+/*
+ * Default slow path packets allowed before the acceleration
+ *  0 - The feature is disabled. Acceleration starts immediately.
+ *  1 - Acceleration will not start until both direction traffic is seen.
+ *  N - Acceleration will not start until N packets are seen in the slow path.
+ */
+int ecm_classifier_accel_delay_pkts = 0;
+
+/*
+ * ecm_classifier_assign_classifier()
+ *	Instantiate and assign classifier of type upon the connection, also returning it if it could be allocated.
+ */
+struct ecm_classifier_instance *ecm_classifier_assign_classifier(struct ecm_db_connection_instance *ci, ecm_classifier_type_t type)
+{
+	DEBUG_TRACE("%px: Assign classifier of type: %d\n", ci, type);
+	DEBUG_ASSERT(type != ECM_CLASSIFIER_TYPE_DEFAULT, "Must never need to instantiate default type in this way");
+
+	switch (type) {
+#ifdef ECM_CLASSIFIER_PCC_ENABLE
+	case ECM_CLASSIFIER_TYPE_PCC: {
+		struct ecm_classifier_pcc_instance *pcci;
+
+		pcci = ecm_classifier_pcc_instance_alloc(ci);
+		if (!pcci) {
+			DEBUG_TRACE("%px: Failed to create Parental Controls classifier\n", ci);
+			return NULL;
+		}
+		DEBUG_TRACE("%px: Created Parental Controls classifier: %px\n", ci, pcci);
+		ecm_db_connection_classifier_assign(ci, (struct ecm_classifier_instance *)pcci);
+		return (struct ecm_classifier_instance *)pcci;
+	}
+#endif
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+	case ECM_CLASSIFIER_TYPE_OVS: {
+		struct ecm_classifier_ovs_instance *ecvi;
+
+		ecvi = ecm_classifier_ovs_instance_alloc(ci);
+		if (!ecvi) {
+			DEBUG_TRACE("%px: Failed to create ovs classifier\n", ci);
+			return NULL;
+		}
+		DEBUG_TRACE("%px: Created ovs classifier: %px\n", ci, ecvi);
+		ecm_db_connection_classifier_assign(ci, (struct ecm_classifier_instance *)ecvi);
+		return (struct ecm_classifier_instance *)ecvi;
+	}
+#endif
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+	case ECM_CLASSIFIER_TYPE_NL: {
+		struct ecm_classifier_nl_instance *cnli;
+
+		cnli = ecm_classifier_nl_instance_alloc(ci);
+		if (!cnli) {
+			DEBUG_TRACE("%px: Failed to create Netlink classifier\n", ci);
+			return NULL;
+		}
+		DEBUG_TRACE("%px: Created Netlink classifier: %px\n", ci, cnli);
+		ecm_db_connection_classifier_assign(ci, (struct ecm_classifier_instance *)cnli);
+		return (struct ecm_classifier_instance *)cnli;
+	}
+#endif
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+	case ECM_CLASSIFIER_TYPE_EMESH: {
+		struct ecm_classifier_emesh_instance *cemi;
+
+		cemi = ecm_classifier_emesh_instance_alloc(ci);
+		if (!cemi) {
+			DEBUG_TRACE("%px: Failed to create emesh classifier\n", ci);
+			return NULL;
+		}
+		DEBUG_TRACE("%px: Created emesh classifier: %px\n", ci, cemi);
+		ecm_db_connection_classifier_assign(ci, (struct ecm_classifier_instance *)cemi);
+		return (struct ecm_classifier_instance *)cemi;
+	}
+#endif
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+	case ECM_CLASSIFIER_TYPE_DSCP: {
+		struct ecm_classifier_dscp_instance *cdscpi;
+
+		cdscpi = ecm_classifier_dscp_instance_alloc(ci);
+		if (!cdscpi) {
+			DEBUG_TRACE("%px: Failed to create DSCP classifier\n", ci);
+			return NULL;
+		}
+		DEBUG_TRACE("%px: Created DSCP classifier: %px\n", ci, cdscpi);
+		ecm_db_connection_classifier_assign(ci, (struct ecm_classifier_instance *)cdscpi);
+		return (struct ecm_classifier_instance *)cdscpi;
+	}
+#endif
+#ifdef ECM_CLASSIFIER_HYFI_ENABLE
+	case ECM_CLASSIFIER_TYPE_HYFI: {
+		struct ecm_classifier_hyfi_instance *chfi;
+
+		chfi = ecm_classifier_hyfi_instance_alloc(ci);
+		if (!chfi) {
+			DEBUG_TRACE("%px: Failed to create HyFi classifier\n", ci);
+			return NULL;
+		}
+		DEBUG_TRACE("%px: Created HyFi classifier: %px\n", ci, chfi);
+		ecm_db_connection_classifier_assign(ci, (struct ecm_classifier_instance *)chfi);
+		return (struct ecm_classifier_instance *)chfi;
+	}
+#endif
+#ifdef ECM_CLASSIFIER_MARK_ENABLE
+	case ECM_CLASSIFIER_TYPE_MARK: {
+		struct ecm_classifier_mark_instance *ecmi;
+
+		ecmi = ecm_classifier_mark_instance_alloc(ci);
+		if (!ecmi) {
+			DEBUG_TRACE("%px: Failed to create mark classifier\n", ci);
+			return NULL;
+		}
+		DEBUG_TRACE("%px: Created mark classifier: %px\n", ci, ecmi);
+		ecm_db_connection_classifier_assign(ci, (struct ecm_classifier_instance *)ecmi);
+		return (struct ecm_classifier_instance *)ecmi;
+	}
+#endif
+#ifdef ECM_CLASSIFIER_MSCS_ENABLE
+	case ECM_CLASSIFIER_TYPE_MSCS: {
+		struct ecm_classifier_mscs_instance *ecmi;
+
+		ecmi = ecm_classifier_mscs_instance_alloc(ci);
+		if (!ecmi) {
+			DEBUG_TRACE("%px: Failed to create mscs classifier\n", ci);
+			return NULL;
+		}
+		DEBUG_TRACE("%px: Created mscs classifier: %px\n", ci, ecmi);
+		ecm_db_connection_classifier_assign(ci, (struct ecm_classifier_instance *)ecmi);
+		return (struct ecm_classifier_instance *)ecmi;
+	}
+#endif
+	default:
+		DEBUG_ASSERT(NULL, "%px: Unsupported type: %d\n", ci, type);
+		return NULL;
+	}
+}
+
+/*
+ * ecm_classifier_reclassify()
+ *	Signal reclassify upon the assigned classifiers.
+ *
+ * Classifiers that unassigned themselves we TRY to re-instantiate them.
+ * Returns false if the function is not able to instantiate all missing classifiers.
+ * This function does not release and references to classifiers in the assignments[].
+ */
+bool ecm_classifier_reclassify(struct ecm_db_connection_instance *ci, int assignment_count, struct ecm_classifier_instance *assignments[])
+{
+	ecm_classifier_type_t classifier_type;
+	int i;
+	bool full_reclassification = true;
+
+	/*
+	 * assignment_count will always be <= the number of classifier types available
+	 */
+	for (i = 0, classifier_type = ECM_CLASSIFIER_TYPE_DEFAULT; i < assignment_count; ++i, ++classifier_type) {
+		ecm_classifier_type_t aci_type;
+		struct ecm_classifier_instance *aci;
+
+		aci = assignments[i];
+		aci_type = aci->type_get(aci);
+		DEBUG_TRACE("%px: Reclassify: %d\n", ci, aci_type);
+		aci->reclassify(aci);
+
+		/*
+		 * If the connection has a full complement of assigned classifiers then these will match 1:1 with the classifier_type (all in same order).
+		 * If not, we have to create the missing ones.
+		 */
+		if (aci_type == classifier_type) {
+			continue;
+		}
+
+		/*
+		 * Need to instantiate the missing classifier types until we get to the same type as aci_type then we are back in sync to continue reclassification
+		 */
+		while (classifier_type != aci_type) {
+			struct ecm_classifier_instance *naci;
+			DEBUG_TRACE("%px: Instantiate missing type: %d\n", ci, classifier_type);
+			DEBUG_ASSERT(classifier_type < ECM_CLASSIFIER_TYPES, "Algorithm bad");
+
+			naci = ecm_classifier_assign_classifier(ci, classifier_type);
+			if (!naci) {
+				full_reclassification = false;
+			} else {
+				naci->deref(naci);
+			}
+
+			classifier_type++;
+		}
+	}
+
+	/*
+	 * Add missing types
+	 */
+	for (; classifier_type < ECM_CLASSIFIER_TYPES; ++classifier_type) {
+		struct ecm_classifier_instance *naci;
+		DEBUG_TRACE("%px: Instantiate missing type: %d\n", ci, classifier_type);
+
+		naci = ecm_classifier_assign_classifier(ci, classifier_type);
+		if (!naci) {
+			full_reclassification = false;
+		} else {
+			naci->deref(naci);
+		}
+	}
+
+	DEBUG_TRACE("%px: reclassify done: %u\n", ci, full_reclassification);
+	return full_reclassification;
+}
diff --git a/qca-nss-ecm/ecm_classifier.h b/qca-nss-ecm/ecm_classifier.h
new file mode 100644
index 0000000..02f3627
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier.h
@@ -0,0 +1,357 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, 2018-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern int ecm_classifier_accel_delay_pkts;	/* Default slow path packets allowed before the acceleration */
+
+struct ecm_classifier_instance;
+
+/*
+ * Classifier types.
+ * MUST BE RECORDED IN ASCENDING ORDER OF PRIORITY
+ */
+enum ecm_classifier_types {
+	ECM_CLASSIFIER_TYPE_DEFAULT = 0,	/* MUST BE FIRST, Default classifier */
+#ifdef ECM_CLASSIFIER_MARK_ENABLE
+	ECM_CLASSIFIER_TYPE_MARK,		/* Mark classifier */
+#endif
+#ifdef ECM_CLASSIFIER_HYFI_ENABLE
+	ECM_CLASSIFIER_TYPE_HYFI,		/* HyFi classifier */
+#endif
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+	ECM_CLASSIFIER_TYPE_DSCP,		/* Provides DSCP and DSCP remarking support */
+#endif
+#ifdef ECM_CLASSIFIER_MSCS_ENABLE
+	ECM_CLASSIFIER_TYPE_MSCS,		/* Mirrored Stream Classification Signalling(MSCS) classifier */
+#endif
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+	ECM_CLASSIFIER_TYPE_EMESH,		/* E-Mesh classifier */
+#endif
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+	ECM_CLASSIFIER_TYPE_NL,			/* Provides netlink interface */
+#endif
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+	ECM_CLASSIFIER_TYPE_OVS,		/* OVS classifier */
+#endif
+#ifdef ECM_CLASSIFIER_PCC_ENABLE
+	ECM_CLASSIFIER_TYPE_PCC,		/* Parental control subsystem support classifier */
+#endif
+	ECM_CLASSIFIER_TYPES,			/* MUST BE LAST */
+};
+typedef enum ecm_classifier_types ecm_classifier_type_t;
+
+/*
+ * enum ecm_classifier_relevances
+ *	Whether a classifier is relevant to a connection
+ */
+enum ecm_classifier_relevances {
+	ECM_CLASSIFIER_RELEVANCE_MAYBE = 0,	/* Classifier has not yet determined relevance */
+	ECM_CLASSIFIER_RELEVANCE_NO,		/* Classifier is not relevant to a connection (classifier will be unassigned from the connection after returning this from a process() call) */
+	ECM_CLASSIFIER_RELEVANCE_YES,		/* Classifier is relevant to the connection, process actions will be inspected by the front end when returning this from a process() call */
+};
+typedef enum ecm_classifier_relevances ecm_classifier_relevence_t;
+
+/*
+ * enum ecm_classifier_acceleration_modes
+ *	Modes in which a connection may be accelerated
+ *
+ * These are used by a classifier to indicate its desire to accelerate.
+ */
+enum ecm_classifier_acceleration_modes {
+	ECM_CLASSIFIER_ACCELERATION_MODE_DONT_CARE = 0,		/* Classifier does not care if the connection is accelerated */
+	ECM_CLASSIFIER_ACCELERATION_MODE_NO,			/* Connection must not be accelerated */
+	ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL,			/* Connection can be accelerated whenever */
+};
+typedef enum ecm_classifier_acceleration_modes ecm_classifier_acceleration_mode_t;
+
+/*
+ * Process actions
+ * A process result, that is relevant, may contain zero or more actions for the front end.
+ * Due to the parallel processing nature of classifiers, *usually* the action(s) of the highest priority
+ * classifier will override any lower priority actions.  This is up to front end discretion, of course.
+ */
+#define ECM_CLASSIFIER_PROCESS_ACTION_DROP 0x00000001		/* Drop */
+#define ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG 0x00000002	/* Contains flow & return qos tags */
+#define ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE 0x00000004	/* Contains an accel mode */
+#define ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP 0x00000008	/* Contains a timer group change */
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+#define ECM_CLASSIFIER_PROCESS_ACTION_DSCP 0x00000010		/* Contains DSCP marking information */
+#define ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY 0x00000020	/* Denies any DSCP changes */
+
+#define ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG 0x00000040	/* Contains flow & return ingress qos tags */
+#endif
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+#define ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG 0x00000080	/* Contains OVS VLAN tags */
+#define ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG 0x00000100	/* Contains OVS QinQ VLAN tags */
+#define ECM_CLASSIFIER_PROCESS_ACTION_OVS_MCAST_DENY_ACCEL 0x00000200		/* Multicast OVS flow */
+#endif
+
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+#define ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW 0x00000400	/* Mark the E-MESH Service Prioritization flow */
+#endif
+
+#define ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP_NO_TOUCH 0x00000400	/* Do not update CI time */
+
+#ifdef ECM_CLASSIFIER_PCC_ENABLE
+#define ECM_CLASSIFIER_PROCESS_ACTION_MIRROR_ENABLED 0x00000800	/* Contains mirror dynamic interface number */
+#endif
+
+#define ECM_CLASSIFIER_PROCESS_ACTION_MARK 0x00001000	/* Contains flow & return skb mark */
+
+/*
+ * struct ecm_classifier_process_response
+ *	Response structure returned by a process call
+ */
+struct ecm_classifier_process_response {
+	ecm_classifier_relevence_t relevance;		/* Is this classifier relevant to the connection? */
+	uint32_t became_relevant;			/* DB time the classifier became relevant or not relevant, if relevance is maybe this field is not relevant! */
+
+	uint32_t process_actions;			/* Actions this process response contains */
+
+	/*
+	 * The following fields are only to be inspected if this response is relevant AND the process_actions indicates so
+	 */
+	bool drop;					/* Drop packet at hand */
+	uint32_t flow_qos_tag;				/* QoS tag to use for the packet */
+	uint32_t return_qos_tag;			/* QoS tag to use for the packet */
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+#ifdef ECM_CLASSIFIER_DSCP_IGS
+	uint16_t igs_flow_qos_tag;			/* Ingress QoS tag to use for the packet */
+	uint16_t igs_return_qos_tag;			/* Ingress QoS tag to use for the return packet */
+#endif
+	uint8_t flow_dscp;				/* DSCP mark for flow */
+	uint8_t return_dscp;				/* DSCP mark for return */
+	uint32_t flow_mark;				/* Mark to use for the packet*/
+	uint32_t return_mark;				/* Mark to use for the return packet*/
+#endif
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+	uint32_t ingress_vlan_tag[2];			/* Ingress VLAN tags */
+	uint32_t egress_vlan_tag[2];			/* Egress VLAN tags */
+#ifdef ECM_MULTICAST_ENABLE
+	int32_t egress_netdev_index[ECM_DB_MULTICAST_IF_MAX];	 /* Multicast egress net device interface index */
+	uint32_t egress_mc_vlan_tag[ECM_DB_MULTICAST_IF_MAX][2]; /* Multicast egress VLAN tags */
+#endif
+#endif
+#ifdef ECM_CLASSIFIER_PCC_ENABLE
+	int flow_mirror_ifindex;			/* Flow mirror device index value */
+	int return_mirror_ifindex;			/* Return mirror device index value */
+#endif
+	ecm_classifier_acceleration_mode_t accel_mode;	/* Acceleration needed for this connection */
+	ecm_db_timer_group_t timer_group;		/* Timer group the connection should be in */
+};
+
+/*
+ * Sync rule structure.
+ *	Acceleration engine's sync parameters will be stored
+ * in this data structure to update the classifiers.
+ */
+struct ecm_classifier_rule_sync {
+	uint32_t tx_packet_count[ECM_CONN_DIR_MAX];
+	uint32_t tx_byte_count[ECM_CONN_DIR_MAX];
+	uint32_t rx_packet_count[ECM_CONN_DIR_MAX];
+	uint32_t rx_byte_count[ECM_CONN_DIR_MAX];
+	uint32_t reason;
+};
+
+/*
+ * Create rule structure.
+ *	Additional create rule parameters from the classifiers
+ * will be copied to this data structure before pushing them to
+ * the underlying accelaration engine.
+ */
+struct ecm_classifier_rule_create {
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+	struct sk_buff *skb;
+#endif
+};
+
+/*
+ * To be implemented by all classifiers
+ */
+typedef void (*ecm_classifier_ref_method_t)(struct ecm_classifier_instance *ci);
+typedef int (*ecm_classifier_deref_callback_t)(struct ecm_classifier_instance *ci);
+typedef void (*ecm_classifier_process_callback_t)(struct ecm_classifier_instance *ci, ecm_tracker_sender_type_t sender, struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb, struct ecm_classifier_process_response *process_response);
+											/* Process new data for connection, process_response is populated with the response of processing */
+typedef void (*ecm_classifier_sync_from_v4_callback_t)(struct ecm_classifier_instance *ci, struct ecm_classifier_rule_create *ecrc);
+											/* Sync the accel engine state with state from the classifier */
+typedef void (*ecm_classifier_sync_to_v4_callback_t)(struct ecm_classifier_instance *ci, struct ecm_classifier_rule_sync *sync);
+											/* Sync the classifier state with current accel engine state */
+typedef void (*ecm_classifier_sync_from_v6_callback_t)(struct ecm_classifier_instance *ci, struct ecm_classifier_rule_create *ecrc);
+											/* Sync the accel engine state with state from the classifier */
+typedef void (*ecm_classifier_sync_to_v6_callback_t)(struct ecm_classifier_instance *ci, struct ecm_classifier_rule_sync *sync);
+											/* Sync the classifier state with current accel engine state */
+typedef ecm_classifier_type_t (*ecm_classifier_type_get_callback_t)(struct ecm_classifier_instance *ci);
+											/* Get type of classifier this is */
+typedef bool (*ecm_classifier_reclassify_allowed_get_callback_t)(struct ecm_classifier_instance *ci);
+											/* Get whether reclassification is allowed */
+typedef void (*ecm_classifier_reclassify_callback_t)(struct ecm_classifier_instance *ci);
+											/* Reclassify */
+typedef void (*ecm_classifier_last_process_response_get_callback_t)(struct ecm_classifier_instance *ci, struct ecm_classifier_process_response *process_response);
+											/* Get last process response */
+#ifdef ECM_STATE_OUTPUT_ENABLE
+typedef int (*ecm_classifier_state_get_callback_t)(struct ecm_classifier_instance *ci, struct ecm_state_file_instance *sfi);
+											/* Get state output.  Returns 0 upon success. */
+#endif
+
+typedef void (*ecm_classifier_update_t)(struct ecm_classifier_instance *ci, enum ecm_rule_update_type type, void *arg);
+
+/*
+ * Determines if a connection should be kept.
+ */
+typedef bool (*ecm_classifier_should_keep_connection_t)
+	(struct ecm_classifier_instance *ci, uint8_t *mac);
+
+/*
+ * Base class for all types of classifiers
+ */
+struct ecm_classifier_instance {
+	struct ecm_classifier_instance *ca_next;	/* DB use only: Connection assignment next pointer */
+	struct ecm_classifier_instance *ca_prev;	/* DB use only: Connection assignment prev pointer */
+
+	ecm_classifier_process_callback_t process;	/* Process new skb */
+	ecm_classifier_sync_from_v4_callback_t sync_from_v4;
+							/* Sync the accel engine with state from the classifier */
+	ecm_classifier_sync_to_v4_callback_t sync_to_v4;/* Sync the classifier with state from the accel engine */
+	ecm_classifier_sync_from_v6_callback_t sync_from_v6;
+							/* Sync the accel engine with state from the classifier */
+	ecm_classifier_sync_to_v6_callback_t sync_to_v6;/* Sync the classifier with state from the accel engine */
+	ecm_classifier_type_get_callback_t type_get;	/* Get type of classifier */
+	ecm_classifier_reclassify_allowed_get_callback_t reclassify_allowed;
+							/* Get whether reclassification is allowed */
+	ecm_classifier_reclassify_callback_t reclassify;
+							/* Reclassify */
+	ecm_classifier_last_process_response_get_callback_t last_process_response_get;
+							/* Return last process response */
+	ecm_classifier_should_keep_connection_t should_keep_connection;
+							/* Check if connection should be kept when FDB updates */
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ecm_classifier_state_get_callback_t state_get;
+							/* Return its state */
+#endif
+	ecm_classifier_update_t update;			/* Updates the classifier instance */
+
+	ecm_classifier_ref_method_t ref;
+	ecm_classifier_deref_callback_t deref;
+};
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_classifier_process_response_state_get()
+ *	Output detail for the process response
+ *
+ * Returns 0 on success.
+ */
+static inline int ecm_classifier_process_response_state_get(struct ecm_state_file_instance *sfi, struct ecm_classifier_process_response *pr)
+{
+	int result;
+
+	if ((result = ecm_state_prefix_add(sfi, "pr"))) {
+		return result;
+	}
+
+	if (pr->relevance == ECM_CLASSIFIER_RELEVANCE_NO) {
+		return ecm_state_write(sfi, "relevant", "%s", "no");
+	}
+
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DROP) {
+		if (pr->drop) {
+			if ((result = ecm_state_write(sfi, "drop", "yes"))) {
+				return result;
+			}
+		} else {
+			if ((result = ecm_state_write(sfi, "drop", "no"))) {
+				return result;
+			}
+		}
+	}
+
+	if (pr->relevance == ECM_CLASSIFIER_RELEVANCE_MAYBE) {
+		if ((result = ecm_state_write(sfi, "accel", "denied"))) {
+			return result;
+		}
+		if ((result = ecm_state_write(sfi, "relevant", "maybe"))) {
+			return result;
+		}
+	} else {
+		if ((result = ecm_state_write(sfi, "relevant", "yes"))) {
+			return result;
+		}
+		if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE) {
+			if (pr->accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL) {
+				if ((result = ecm_state_write(sfi, "accel", "wanted"))) {
+					return result;
+				}
+			}
+			else if (pr->accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_NO) {
+				if ((result = ecm_state_write(sfi, "accel", "denied"))) {
+					return result;
+				}
+			}
+			/* Else don't care */
+		}
+	}
+
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+		if ((result = ecm_state_write(sfi, "flow_qos_tag", "%u", pr->flow_qos_tag))) {
+			return result;
+		}
+		if ((result = ecm_state_write(sfi, "return_qos_tag", "%u", pr->return_qos_tag))) {
+			return result;
+		}
+	}
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+#ifdef ECM_CLASSIFIER_DSCP_IGS
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG) {
+		if ((result = ecm_state_write(sfi, "igs_flow_qos_tag", "%u", pr->igs_flow_qos_tag))) {
+			return result;
+		}
+		if ((result = ecm_state_write(sfi, "igs_return_qos_tag", "%u", pr->igs_return_qos_tag))) {
+			return result;
+		}
+	}
+#endif
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+		if ((result = ecm_state_write(sfi, "flow_dscp", "%u", pr->flow_dscp))) {
+			return result;
+		}
+		if ((result = ecm_state_write(sfi, "return_dscp", "%u", pr->return_dscp))) {
+			return result;
+		}
+	}
+
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_MARK) {
+		if ((result = ecm_state_write(sfi, "flow_mark", "%u", pr->flow_mark))) {
+			return result;
+		}
+		if ((result = ecm_state_write(sfi, "return_mark", "%u", pr->return_mark))) {
+			return result;
+		}
+	}
+#endif
+
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP) {
+		if ((result = ecm_state_write(sfi, "timer_group", "%d", pr->timer_group))) {
+			return result;
+		}
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+extern struct ecm_classifier_instance *ecm_classifier_assign_classifier(struct ecm_db_connection_instance *ci, ecm_classifier_type_t type);
+extern bool ecm_classifier_reclassify(struct ecm_db_connection_instance *ci, int assignment_count, struct ecm_classifier_instance *assignments[]);
diff --git a/qca-nss-ecm/ecm_classifier_default.c b/qca-nss-ecm/ecm_classifier_default.c
new file mode 100644
index 0000000..39315a9
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_default.c
@@ -0,0 +1,802 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2016, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/debugfs.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_CLASSIFIER_DEFAULT_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_front_end_common.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_CLASSIFIER_DEFAULT_INTERNAL_INSTANCE_MAGIC 0x8761
+#define ECM_CLASSIFIER_DEFAULT_STATE_FILE_INSTANCE_MAGIC 0x3321
+
+/*
+ * struct ecm_classifier_default_internal_instance
+ * 	State to allow tracking of dynamic priority for a connection
+ */
+struct ecm_classifier_default_internal_instance {
+	struct ecm_classifier_default_instance base;		/* Base type */
+
+	uint32_t ci_serial;					/* RO: Serial of the connection */
+	int protocol;						/* RO: Protocol of the connection */
+
+	struct ecm_classifier_process_response process_response;
+								/* Last process response computed */
+
+	ecm_db_timer_group_t timer_group;			/* The timer group the connection should be in based on state */
+
+	ecm_tracker_sender_type_t ingress_sender;		/* RO: Which sender is sending ingress data */
+	ecm_tracker_sender_type_t egress_sender;		/* RO: Which sender is sending egress data */
+
+	struct ecm_tracker_instance *ti;			/* RO: Tracker used for state and timer group checking. Pointer will not change so safe to access outside of lock. */
+	bool packet_seen[ECM_CONN_DIR_MAX];                     /* Per-direction packet seen flag */
+	int refs;						/* Integer to trap we never go negative */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+static  DEFINE_SPINLOCK(ecm_classifier_default_lock);			/* Concurrency control SMP access */
+static int ecm_classifier_default_count = 0;			/* Tracks number of instances allocated */
+
+/*
+ * Operational control
+ */
+static ecm_classifier_acceleration_mode_t ecm_classifier_default_accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+								/* Cause connections whose hosts are both on-link to be accelerated */
+static int ecm_classifier_default_enabled = 1;		/* When disabled the qos algorithm will not be applied to skb's */
+
+/*
+ * Management thread control
+ */
+static bool ecm_classifier_default_terminate_pending = false;	/* True when the user wants us to terminate */
+
+/*
+ * Character device stuff - used to communicate status back to user space
+ */
+#define ECM_CLASSIFIER_DEFAULT_STATE_FILE_BUFFER_SIZE 1024
+struct ecm_classifier_default_state_file_instance {
+	struct ecm_classifier_default_internal_instance *cdii;
+	bool doc_start_written;
+	bool doc_end_written;
+	char msg_buffer[ECM_CLASSIFIER_DEFAULT_STATE_FILE_BUFFER_SIZE];	/* Used to hold the current state message being output */
+	char *msgp;							/* Points into the msg buffer as we output it piece by piece */
+	int msg_len;							/* Length of the buffer still to be written out */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+static struct dentry *ecm_classifier_default_dentry;		/* Debugfs dentry object */
+
+/*
+ * _ecm_classifier_default_ref()
+ *	Ref
+ */
+static void _ecm_classifier_default_ref(struct ecm_classifier_default_internal_instance *cdii)
+{
+	cdii->refs++;
+	DEBUG_TRACE("%px: cdii ref %d\n", cdii, cdii->refs);
+	DEBUG_ASSERT(cdii->refs > 0, "%px: ref wrap\n", cdii);
+}
+
+/*
+ * ecm_classifier_default_ref()
+ *	Ref
+ */
+static void ecm_classifier_default_ref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_default_internal_instance *cdii;
+	cdii = (struct ecm_classifier_default_internal_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(cdii, ECM_CLASSIFIER_DEFAULT_INTERNAL_INSTANCE_MAGIC, "%px: magic failed", cdii);
+	spin_lock_bh(&ecm_classifier_default_lock);
+	_ecm_classifier_default_ref(cdii);
+	spin_unlock_bh(&ecm_classifier_default_lock);
+}
+
+/*
+ * ecm_classifier_default_deref()
+ *	Deref
+ */
+static int ecm_classifier_default_deref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_default_internal_instance *cdii;
+	cdii = (struct ecm_classifier_default_internal_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(cdii, ECM_CLASSIFIER_DEFAULT_INTERNAL_INSTANCE_MAGIC, "%px: magic failed", cdii);
+	spin_lock_bh(&ecm_classifier_default_lock);
+	cdii->refs--;
+	DEBUG_ASSERT(cdii->refs >= 0, "%px: refs wrapped\n", cdii);
+	DEBUG_TRACE("%px: Default classifier deref %d\n", cdii, cdii->refs);
+	if (cdii->refs) {
+		int refs = cdii->refs;
+		spin_unlock_bh(&ecm_classifier_default_lock);
+		return refs;
+	}
+
+	/*
+	 * Object to be destroyed
+	 */
+	ecm_classifier_default_count--;
+	DEBUG_ASSERT(ecm_classifier_default_count >= 0, "%px: ecm_classifier_default_count wrap\n", cdii);
+
+	spin_unlock_bh(&ecm_classifier_default_lock);
+
+	/*
+	 * Release our tracker
+	 */
+	cdii->ti->deref(cdii->ti);
+
+	/*
+	 * Final
+	 */
+	DEBUG_INFO("%px: Final default classifier instance\n", cdii);
+	kfree(cdii);
+
+	return 0;
+}
+
+/*
+ * ecm_classifier_default_ready_for_accel()
+ *	Checks if the connection is ready for the acceleration.
+ *
+ * This function is called, if the acceleration delay feature is enabled.
+ */
+static bool ecm_classifier_default_ready_for_accel(
+			struct ecm_classifier_default_internal_instance *cdii,
+			ecm_tracker_sender_type_t sender)
+{
+	uint64_t slow_pkts;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+
+	/*
+	 * We delay the acceleration for TCP and UDP protocols only.
+	 * Non-ported protocols mostly the outer connections of the flows.
+	 * Acceleration delay is required to inspect the packets and
+	 * the outer connections are generally do not need inspection.
+	 */
+	if (cdii->protocol != IPPROTO_TCP && cdii->protocol != IPPROTO_UDP) {
+		DEBUG_TRACE("%px: Accel delay is not enabled for protocol: %d\n", cdii, cdii->protocol);
+		return true;
+	}
+
+	/*
+	 * Delay forever until seeing the reply packet.
+	 */
+	if (ecm_classifier_accel_delay_pkts == 1) {
+		DEBUG_INFO("%px: Checking both direction traffic\n", cdii);
+
+		/*
+		 * Set the flow and return direction packet seen flags.
+		 */
+		if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+			cdii->packet_seen[ECM_CONN_DIR_FLOW] = true;
+		} else {
+			cdii->packet_seen[ECM_CONN_DIR_RETURN] = true;
+		}
+
+		/*
+		 * Check if both direction traffic is seen.
+		 */
+		return cdii->packet_seen[ECM_CONN_DIR_FLOW] && cdii->packet_seen[ECM_CONN_DIR_RETURN];
+	}
+
+	/*
+	 * Delay the acceleration until we see <N> number of packets.
+	 * ecm_classifier_accel_delay_pkts = <N>
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(cdii->ci_serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: No ci found for %u\n", cdii, cdii->ci_serial);
+		return false;
+	}
+
+	/*
+	 * Get the packet count we have seen in the slow path so far.
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	slow_pkts = ecm_front_end_get_slow_packet_count(feci);
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Check if we have seen slow path packets as the predefined count.
+	 */
+	if (slow_pkts < ecm_classifier_accel_delay_pkts) {
+		DEBUG_TRACE("%px: delay the acceleration: slow packets: %llu default delay packet count: %d\n",
+			    cdii, slow_pkts, ecm_classifier_accel_delay_pkts);
+
+		/*
+		 * We haven't reached the slow path packet limit.
+		 * We can wait more to accelerate the connection.
+		 */
+		return false;
+	}
+
+	/*
+	 * We waited enough time for the acceleration, we can allow it now.
+	 */
+	DEBUG_INFO("%px: Let the flow accel, waited enough packet\n", cdii);
+	return true;
+}
+
+/*
+ * ecm_classifier_default_process()
+ *	Process the flow for acceleration decision.
+ */
+static void ecm_classifier_default_process(struct ecm_classifier_instance *aci, ecm_tracker_sender_type_t sender,
+					   struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb,
+					   struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_tracker_instance *ti;
+	ecm_tracker_sender_state_t from_state;
+	ecm_tracker_sender_state_t to_state;
+	ecm_tracker_connection_state_t prevailing_state;
+	ecm_db_timer_group_t tg;
+	struct ecm_classifier_default_internal_instance *cdii = (struct ecm_classifier_default_internal_instance *)aci;
+	struct nf_conn *ct;
+	enum ip_conntrack_info ctinfo;
+
+	DEBUG_CHECK_MAGIC(cdii, ECM_CLASSIFIER_DEFAULT_INTERNAL_INSTANCE_MAGIC, "%px: invalid state magic\n", cdii);
+
+	/*
+	 * Get qos result and accel mode
+	 * Default classifier is rarely disabled.
+	 */
+	if (unlikely(!ecm_classifier_default_enabled)) {
+		/*
+		 * Still relevant but have no actions that need processing
+		 */
+		spin_lock_bh(&ecm_classifier_default_lock);
+		cdii->process_response.process_actions = 0;
+		*process_response = cdii->process_response;
+		spin_unlock_bh(&ecm_classifier_default_lock);
+		return;
+	}
+
+	/*
+	 * Update connection state
+	 * Compute the timer group this connection should be in.
+	 * For this we need the tracker and the state to be updated.
+	 * NOTE: Tracker does not need to be ref'd it will exist for as long as this default classifier instance does
+	 * which is at least for the duration of this call.
+	 */
+	ti = cdii->ti;
+	ti->state_update(ti, sender, ip_hdr, skb);
+	ti->state_get(ti, &from_state, &to_state, &prevailing_state, &tg);
+	spin_lock_bh(&ecm_classifier_default_lock);
+	if (unlikely(cdii->timer_group != tg)) {
+		/*
+		 * Timer group has changed
+		 */
+		cdii->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP;
+		cdii->process_response.timer_group = tg;
+
+		/*
+		 * Record for future change comparisons
+		 */
+		DEBUG_INFO("%px: timer group changed from %d to %d\n", cdii, cdii->timer_group, tg);
+		cdii->timer_group = tg;
+	}
+
+	/*
+	 * Don't care?
+	 */
+	if (ecm_classifier_default_accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_DONT_CARE) {
+		cdii->process_response.process_actions &= ~ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+		*process_response = cdii->process_response;
+		spin_unlock_bh(&ecm_classifier_default_lock);
+		return;
+	}
+	spin_unlock_bh(&ecm_classifier_default_lock);
+
+	/*
+	 * Handle non-TCP case
+	 */
+	if (cdii->protocol != IPPROTO_TCP) {
+		if (unlikely(prevailing_state != ECM_TRACKER_CONNECTION_STATE_ESTABLISHED)) {
+			DEBUG_INFO("%px: Protocol: %d is non-TCP, prevailing_state: %d\n", cdii, cdii->protocol, prevailing_state);
+			spin_lock_bh(&ecm_classifier_default_lock);
+			goto accel_no;
+		}
+		DEBUG_INFO("%px: Protocol: %d is non-TCP, prevailing_state ESTABLISHED\n", cdii, cdii->protocol);
+		goto check_delay;
+	}
+
+	/*
+	 * Check the TCP connection state, when the ct is NULL.
+	 * ct valid case was already checked in the ecm_nss{sfe}_ported_ipv4{6}_process functions.
+	 * If we are not established then we deny acceleration.
+	 */
+	ct = nf_ct_get(skb, &ctinfo);
+	if (!ct) {
+		DEBUG_TRACE("%px: No Conntrack found for packet, using ECM tracker state\n", cdii);
+
+		if (unlikely(prevailing_state == ECM_TRACKER_CONNECTION_STATE_ESTABLISHED)) {
+			DEBUG_INFO("%px: TCP prevailing_state ESTABLISHED\n", cdii);
+			goto check_delay;
+		}
+
+		DEBUG_INFO("%px: TCP prevailing_state: %d\n", cdii, prevailing_state);
+
+		spin_lock_bh(&ecm_classifier_default_lock);
+		if ((prevailing_state == ECM_TRACKER_CONNECTION_STATE_FAULT) || (prevailing_state == ECM_TRACKER_CONNECTION_STATE_CLOSED)) {
+			cdii->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP_NO_TOUCH;
+		}
+		goto accel_no;
+	}
+
+	/*
+	* If the connection is shutting down do not manage it.
+	* state can not be SYN_SENT, SYN_RECV because connection is assured
+	* Not managed states: FIN_WAIT, CLOSE_WAIT, LAST_ACK, TIME_WAIT, CLOSE.
+	*/
+	spin_lock_bh(&ct->lock);
+	if (ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED) {
+		spin_unlock_bh(&ct->lock);
+		DEBUG_TRACE("%px: Connection in termination state %#X\n", ct, ct->proto.tcp.state);
+		spin_lock_bh(&ecm_classifier_default_lock);
+		goto accel_no;
+	}
+	spin_unlock_bh(&ct->lock);
+
+check_delay:
+	/*
+	 * Should we delay the acceleration?
+	 */
+	if (ecm_classifier_accel_delay_pkts) {
+		if (!ecm_classifier_default_ready_for_accel(cdii, sender)) {
+			DEBUG_INFO("%px: connection is not ready for accel\n", cdii);
+			spin_lock_bh(&ecm_classifier_default_lock);
+			goto accel_no;
+		}
+		DEBUG_INFO("%px: connection is ready for accel\n", cdii);
+	}
+
+	/*
+	 * Return the process response
+	 */
+	spin_lock_bh(&ecm_classifier_default_lock);
+	cdii->process_response.accel_mode = ecm_classifier_default_accel_mode;
+	cdii->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	*process_response = cdii->process_response;
+	spin_unlock_bh(&ecm_classifier_default_lock);
+	return;
+
+accel_no:
+	cdii->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+	cdii->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	*process_response = cdii->process_response;
+	spin_unlock_bh(&ecm_classifier_default_lock);
+}
+
+/*
+ * ecm_classifier_default_type_get()
+ *	Get type of classifier this is
+ */
+static ecm_classifier_type_t ecm_classifier_default_type_get(struct ecm_classifier_instance *aci)
+{
+	struct ecm_classifier_default_internal_instance *cdii;
+	cdii = (struct ecm_classifier_default_internal_instance *)aci;
+
+	DEBUG_CHECK_MAGIC(cdii, ECM_CLASSIFIER_DEFAULT_INTERNAL_INSTANCE_MAGIC, "%px: magic failed", cdii);
+	return ECM_CLASSIFIER_TYPE_DEFAULT;
+}
+
+/*
+ * ecm_classifier_default_reclassify_allowed()
+ *	Get whether reclassification is allowed
+ */
+static bool ecm_classifier_default_reclassify_allowed(struct ecm_classifier_instance *aci)
+{
+	struct ecm_classifier_default_internal_instance *cdii;
+	cdii = (struct ecm_classifier_default_internal_instance *)aci;
+
+	DEBUG_CHECK_MAGIC(cdii, ECM_CLASSIFIER_DEFAULT_INTERNAL_INSTANCE_MAGIC, "%px: magic failed", cdii);
+	return true;
+}
+
+/*
+ * ecm_classifier_default_reclassify()
+ *	Reclassify
+ */
+static void ecm_classifier_default_reclassify(struct ecm_classifier_instance *aci)
+{
+	struct ecm_classifier_default_internal_instance *cdii;
+	cdii = (struct ecm_classifier_default_internal_instance *)aci;
+	DEBUG_CHECK_MAGIC(cdii, ECM_CLASSIFIER_DEFAULT_INTERNAL_INSTANCE_MAGIC, "%px: magic failed", cdii);
+}
+
+/*
+ * ecm_classifier_default_last_process_response_get()
+ *	Get result code returned by the last process call
+ */
+static void ecm_classifier_default_last_process_response_get(struct ecm_classifier_instance *aci,
+							struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_default_internal_instance *cdii;
+	cdii = (struct ecm_classifier_default_internal_instance *)aci;
+	DEBUG_CHECK_MAGIC(cdii, ECM_CLASSIFIER_DEFAULT_INTERNAL_INSTANCE_MAGIC, "%px: magic failed", cdii);
+
+	spin_lock_bh(&ecm_classifier_default_lock);
+	*process_response = cdii->process_response;
+	spin_unlock_bh(&ecm_classifier_default_lock);
+}
+
+/*
+ * ecm_classifier_default_sync_to_v4()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_default_sync_to_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	struct ecm_classifier_default_internal_instance *cdii __attribute__((unused));
+
+	cdii = (struct ecm_classifier_default_internal_instance *)aci;
+	DEBUG_CHECK_MAGIC(cdii, ECM_CLASSIFIER_DEFAULT_INTERNAL_INSTANCE_MAGIC, "%px: magic failed", cdii);
+}
+
+/*
+ * ecm_classifier_default_sync_from_v4()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_default_sync_from_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_default_internal_instance *cdii __attribute__((unused));
+
+	cdii = (struct ecm_classifier_default_internal_instance *)aci;
+	DEBUG_CHECK_MAGIC(cdii, ECM_CLASSIFIER_DEFAULT_INTERNAL_INSTANCE_MAGIC, "%px: magic failed", cdii);
+}
+
+/*
+ * ecm_classifier_default_sync_to_v6()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_default_sync_to_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	struct ecm_classifier_default_internal_instance *cdii __attribute__((unused));
+
+	cdii = (struct ecm_classifier_default_internal_instance *)aci;
+	DEBUG_CHECK_MAGIC(cdii, ECM_CLASSIFIER_DEFAULT_INTERNAL_INSTANCE_MAGIC, "%px: magic failed", cdii);
+}
+
+/*
+ * ecm_classifier_default_sync_from_v6()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_default_sync_from_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_default_internal_instance *cdii __attribute__((unused));
+
+	cdii = (struct ecm_classifier_default_internal_instance *)aci;
+	DEBUG_CHECK_MAGIC(cdii, ECM_CLASSIFIER_DEFAULT_INTERNAL_INSTANCE_MAGIC, "%px: magic failed", cdii);
+}
+
+/*
+ * ecm_classifier_tracker_get_and_ref()
+ *	Obtain default classifiers tracker (usually for state tracking for the connection as it always exists for the connection)
+ */
+static struct ecm_tracker_instance *ecm_classifier_tracker_get_and_ref(struct ecm_classifier_default_instance *dci)
+{
+	struct ecm_classifier_default_internal_instance *cdii;
+	struct ecm_tracker_instance *ti;
+
+	cdii = (struct ecm_classifier_default_internal_instance *)dci;
+	DEBUG_CHECK_MAGIC(cdii, ECM_CLASSIFIER_DEFAULT_INTERNAL_INSTANCE_MAGIC, "%px: magic failed", cdii);
+
+	ti = cdii->ti;
+	ti->ref(ti);
+	return ti;
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_classifier_default_state_get()
+ *	Return state
+ */
+static int ecm_classifier_default_state_get(struct ecm_classifier_instance *ci, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	struct ecm_classifier_default_internal_instance *cdii;
+	struct ecm_classifier_process_response process_response;
+	ecm_db_timer_group_t timer_group;
+	ecm_tracker_sender_type_t ingress_sender;
+	ecm_tracker_sender_type_t egress_sender;
+
+	cdii = (struct ecm_classifier_default_internal_instance *)ci;
+	DEBUG_CHECK_MAGIC(cdii, ECM_CLASSIFIER_DEFAULT_INTERNAL_INSTANCE_MAGIC, "%px: magic failed", cdii);
+
+	if ((result = ecm_state_prefix_add(sfi, "default"))) {
+		return result;
+	}
+
+	spin_lock_bh(&ecm_classifier_default_lock);
+	egress_sender = cdii->egress_sender;
+	ingress_sender = cdii->ingress_sender;
+	timer_group = cdii->timer_group;
+	process_response = cdii->process_response;
+	spin_unlock_bh(&ecm_classifier_default_lock);
+
+	if ((result = ecm_state_write(sfi, "ingress_sender", "%d", ingress_sender))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "egress_sender", "%d", egress_sender))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "timer_group", "%d", timer_group))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "accel_delay_pkt_default", "%d", ecm_classifier_accel_delay_pkts))) {
+		return result;
+	}
+
+	/*
+	 * Output our last process response
+	 */
+	if ((result = ecm_classifier_process_response_state_get(sfi, &process_response))) {
+		return result;
+	}
+
+	if ((result = ecm_state_prefix_add(sfi, "trackers"))) {
+		return result;
+	}
+
+	/*
+	 * Output our tracker state
+	 */
+	if ((result = cdii->ti->state_text_get(cdii->ti, sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_prefix_remove(sfi))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+/*
+ * ecm_classifier_default_instance_alloc()
+ *	Allocate an instance of the default classifier
+ */
+struct ecm_classifier_default_instance *ecm_classifier_default_instance_alloc(struct ecm_db_connection_instance *ci, int protocol, ecm_db_direction_t dir, int from_port, int to_port)
+{
+	struct ecm_classifier_default_internal_instance *cdii;
+	struct ecm_classifier_default_instance *cdi;
+
+	/*
+	 * Allocate the instance
+	 */
+	cdii = (struct ecm_classifier_default_internal_instance *)kzalloc(sizeof(struct ecm_classifier_default_internal_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!cdii) {
+		DEBUG_WARN("Failed to allocate default instance\n");
+		return NULL;
+	}
+
+	/*
+	 * Allocate a tracker for state etc.
+	 */
+	if (protocol == IPPROTO_TCP) {
+		DEBUG_TRACE("%px: Alloc tracker for TCP connection: %px\n", cdii, ci);
+		cdii->ti = (struct ecm_tracker_instance *)ecm_tracker_tcp_alloc();
+		if (!cdii->ti) {
+			DEBUG_WARN("%px: Failed to alloc tracker\n", cdii);
+			kfree(cdii);
+			return NULL;
+		}
+		ecm_tracker_tcp_init((struct ecm_tracker_tcp_instance *)cdii->ti, ECM_TRACKER_CONNECTION_TRACKING_LIMIT_DEFAULT, 1500, 1500);
+	} else if (protocol == IPPROTO_UDP) {
+		DEBUG_TRACE("%px: Alloc tracker for UDP connection: %px\n", cdii, ci);
+		cdii->ti = (struct ecm_tracker_instance *)ecm_tracker_udp_alloc();
+		if (!cdii->ti) {
+			DEBUG_WARN("%px: Failed to alloc tracker\n", cdii);
+			kfree(cdii);
+			return NULL;
+		}
+		ecm_tracker_udp_init((struct ecm_tracker_udp_instance *)cdii->ti, ECM_TRACKER_CONNECTION_TRACKING_LIMIT_DEFAULT, from_port, to_port);
+	} else {
+		DEBUG_TRACE("%px: Alloc tracker for non-ported connection: %px\n", cdii, ci);
+		cdii->ti = (struct ecm_tracker_instance *)ecm_tracker_datagram_alloc();
+		if (!cdii->ti) {
+			DEBUG_WARN("%px: Failed to alloc tracker\n", cdii);
+			kfree(cdii);
+			return NULL;
+		}
+		ecm_tracker_datagram_init((struct ecm_tracker_datagram_instance *)cdii->ti, ECM_TRACKER_CONNECTION_TRACKING_LIMIT_DEFAULT);
+	}
+
+	DEBUG_SET_MAGIC(cdii, ECM_CLASSIFIER_DEFAULT_INTERNAL_INSTANCE_MAGIC);
+	cdii->refs = 1;
+	cdii->ci_serial = ecm_db_connection_serial_get(ci);
+	cdii->protocol = protocol;
+
+	/*
+	 * We are always relevant to the connection
+	 */
+	cdii->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+
+	/*
+	 * Using the connection direction identify egress and ingress host addresses
+	 */
+	if (dir == ECM_DB_DIRECTION_INGRESS_NAT) {
+		cdii->ingress_sender = ECM_TRACKER_SENDER_TYPE_SRC;
+		cdii->egress_sender = ECM_TRACKER_SENDER_TYPE_DEST;
+	} else {
+		cdii->egress_sender = ECM_TRACKER_SENDER_TYPE_SRC;
+		cdii->ingress_sender = ECM_TRACKER_SENDER_TYPE_DEST;
+	}
+	DEBUG_TRACE("%px: Ingress sender = %d egress sender = %d\n", cdii, cdii->ingress_sender, cdii->egress_sender);
+
+	/*
+	 * Methods specific to the default classifier
+	 */
+	cdi = (struct ecm_classifier_default_instance *)cdii;
+	cdi->tracker_get_and_ref = ecm_classifier_tracker_get_and_ref;
+
+	/*
+	 * Methods generic to all classifiers.
+	 */
+	cdi->base.process = ecm_classifier_default_process;
+	cdi->base.sync_from_v4 = ecm_classifier_default_sync_from_v4;
+	cdi->base.sync_to_v4 = ecm_classifier_default_sync_to_v4;
+	cdi->base.sync_from_v6 = ecm_classifier_default_sync_from_v6;
+	cdi->base.sync_to_v6 = ecm_classifier_default_sync_to_v6;
+	cdi->base.type_get = ecm_classifier_default_type_get;
+	cdi->base.reclassify_allowed = ecm_classifier_default_reclassify_allowed;
+	cdi->base.reclassify = ecm_classifier_default_reclassify;
+	cdi->base.last_process_response_get = ecm_classifier_default_last_process_response_get;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	cdi->base.state_get = ecm_classifier_default_state_get;
+#endif
+	cdi->base.ref = ecm_classifier_default_ref;
+	cdi->base.deref = ecm_classifier_default_deref;
+
+	spin_lock_bh(&ecm_classifier_default_lock);
+
+	/*
+	 * Final check if we are pending termination
+	 */
+	if (ecm_classifier_default_terminate_pending) {
+		spin_unlock_bh(&ecm_classifier_default_lock);
+		DEBUG_INFO("%px: Terminating\n", ci);
+		cdii->ti->deref(cdii->ti);
+		kfree(cdii);
+		return NULL;
+	}
+
+	/*
+	 * Increment stats
+	 */
+	ecm_classifier_default_count++;
+	DEBUG_ASSERT(ecm_classifier_default_count > 0, "%px: ecm_classifier_default_count wrap\n", cdii);
+	spin_unlock_bh(&ecm_classifier_default_lock);
+
+	DEBUG_INFO("Default classifier instance alloc: %px\n", cdii);
+	return cdi;
+}
+EXPORT_SYMBOL(ecm_classifier_default_instance_alloc);
+
+/*
+ * ecm_classifier_default_init()
+ */
+int ecm_classifier_default_init(struct dentry *dentry)
+{
+	DEBUG_INFO("Default classifier Module init\n");
+
+	DEBUG_ASSERT(ECM_CLASSIFIER_TYPE_DEFAULT == 0, "DO NOT CHANGE DEFAULT PRIORITY");
+
+	ecm_classifier_default_dentry = debugfs_create_dir("ecm_classifier_default", dentry);
+	if (!ecm_classifier_default_dentry) {
+		DEBUG_ERROR("Failed to create ecm default classifier directory in debugfs\n");
+		return -1;
+	}
+
+	if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry,
+					(u32 *)&ecm_classifier_default_enabled)) {
+		DEBUG_ERROR("Failed to create ecm deafult classifier enabled file in debugfs\n");
+		debugfs_remove_recursive(ecm_classifier_default_dentry);
+		return -1;
+	}
+
+	if (!debugfs_create_u32("accel_mode", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry,
+					(u32 *)&ecm_classifier_default_accel_mode)) {
+		DEBUG_ERROR("Failed to create ecm deafult classifier accel_mode file in debugfs\n");
+		debugfs_remove_recursive(ecm_classifier_default_dentry);
+		return -1;
+	}
+
+	if (!debugfs_create_u32("accel_delay_pkts", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry,
+					(u32 *)&ecm_classifier_accel_delay_pkts)) {
+		DEBUG_ERROR("Failed to create accel delay packet counts in debugfs\n");
+		debugfs_remove_recursive(ecm_classifier_default_dentry);
+		return -1;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_classifier_default_init);
+
+/*
+ * ecm_classifier_default_exit()
+ */
+void ecm_classifier_default_exit(void)
+{
+	DEBUG_INFO("Default classifier Module exit\n");
+	spin_lock_bh(&ecm_classifier_default_lock);
+	ecm_classifier_default_terminate_pending = true;
+	spin_unlock_bh(&ecm_classifier_default_lock);
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_classifier_default_dentry) {
+		debugfs_remove_recursive(ecm_classifier_default_dentry);
+	}
+}
+EXPORT_SYMBOL(ecm_classifier_default_exit);
diff --git a/qca-nss-ecm/ecm_classifier_default.h b/qca-nss-ecm/ecm_classifier_default.h
new file mode 100644
index 0000000..8b0d35c
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_default.h
@@ -0,0 +1,49 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+struct ecm_classifier_default_instance;
+
+/*
+ * Structure used to synchronise a classifier instance with the state as presented by the accel engine
+ */
+struct ecm_classifier_default_sync {
+	uint8_t qos;
+	uint32_t qws;
+	uint32_t qwr;
+	uint16_t qbc;
+	uint32_t from_data_total;		/* Amount of bytes sent by 'from' */
+	uint32_t to_data_total;			/* Amount of bytes sent by 'to' */
+};
+
+typedef void (*ecm_classifier_default_process_callback_t)(struct ecm_classifier_default_instance *dci, ecm_tracker_sender_type_t sender, struct iphdr *ip_hdr, int ip_hdr_len, int ip_total_len, struct sk_buff *skb);
+typedef ecm_db_timer_group_t (*ecm_classifier_default_timer_group_change_callback_t)(struct ecm_classifier_default_instance *dci);
+typedef struct ecm_tracker_instance *(*ecm_classifier_default_tracker_get_and_ref_callback_t)(struct ecm_classifier_default_instance *dci);
+
+struct ecm_classifier_default_instance {
+	struct ecm_classifier_instance base;	/* Base class implemented by this classifier */
+
+	/*
+	 * Functions specific to the default classifier.
+	 */
+	ecm_classifier_default_process_callback_t process;		/* Process new data for connection - Used ONLY by front ends */
+	ecm_classifier_default_timer_group_change_callback_t timer_group_change;
+									/* Utility to other classifiers: detect if update is needed to timer group */
+	ecm_classifier_default_tracker_get_and_ref_callback_t tracker_get_and_ref;
+									/* Utility to front end: Obtain default classifier tracker */
+};
+
+struct ecm_classifier_default_instance *ecm_classifier_default_instance_alloc(struct ecm_db_connection_instance *ci, int protocol, ecm_db_direction_t dir, int from_port, int to_port);
+
diff --git a/qca-nss-ecm/ecm_classifier_dscp.c b/qca-nss-ecm/ecm_classifier_dscp.c
new file mode 100644
index 0000000..22b04d6
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_dscp.c
@@ -0,0 +1,850 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2016, 2019-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/debugfs.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+#include <linux/netfilter/xt_dscp.h>
+#include <net/netfilter/nf_conntrack_dscpremark_ext.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_CLASSIFIER_DSCP_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_dscp.h"
+#include "ecm_front_end_common.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_CLASSIFIER_DSCP_INSTANCE_MAGIC 0xFA43
+
+/*
+ * struct ecm_classifier_dscp_instance
+ * 	State to allow tracking of dynamic qos for a connection
+ */
+struct ecm_classifier_dscp_instance {
+	struct ecm_classifier_instance base;			/* Base type */
+
+	struct ecm_classifier_dscp_instance *next;		/* Next classifier state instance (for accouting and reporting purposes) */
+	struct ecm_classifier_dscp_instance *prev;		/* Next classifier state instance (for accouting and reporting purposes) */
+
+	uint32_t ci_serial;					/* RO: Serial of the connection */
+	struct ecm_classifier_process_response process_response;/* Last process response computed */
+	bool packet_seen[ECM_CONN_DIR_MAX];			/* Per-direction packet seen flag */
+	int refs;						/* Integer to trap we never go negative */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+/*
+ * Operational control
+ */
+static int ecm_classifier_dscp_enabled = 1;			/* Operational behaviour */
+
+/*
+ * Management thread control
+ */
+static bool ecm_classifier_dscp_terminate_pending = false;	/* True when the user wants us to terminate */
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_classifier_dscp_dentry;
+
+/*
+ * Locking of the classifier structures
+ */
+static DEFINE_SPINLOCK(ecm_classifier_dscp_lock);			/* Protect SMP access. */
+
+/*
+ * List of our classifier instances
+ */
+static struct ecm_classifier_dscp_instance *ecm_classifier_dscp_instances = NULL;
+								/* list of all active instances */
+static int ecm_classifier_dscp_count = 0;			/* Tracks number of instances allocated */
+
+/*
+ * ecm_classifier_dscp_ref()
+ *	Ref
+ */
+static void ecm_classifier_dscp_ref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_dscp_instance *cdscpi;
+	cdscpi = (struct ecm_classifier_dscp_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(cdscpi, ECM_CLASSIFIER_DSCP_INSTANCE_MAGIC, "%px: magic failed\n", cdscpi);
+	spin_lock_bh(&ecm_classifier_dscp_lock);
+	cdscpi->refs++;
+	DEBUG_TRACE("%px: cdscpi ref %d\n", cdscpi, cdscpi->refs);
+	DEBUG_ASSERT(cdscpi->refs > 0, "%px: ref wrap\n", cdscpi);
+	spin_unlock_bh(&ecm_classifier_dscp_lock);
+}
+
+/*
+ * ecm_classifier_dscp_deref()
+ *	Deref
+ */
+static int ecm_classifier_dscp_deref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_dscp_instance *cdscpi;
+	cdscpi = (struct ecm_classifier_dscp_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(cdscpi, ECM_CLASSIFIER_DSCP_INSTANCE_MAGIC, "%px: magic failed\n", cdscpi);
+	spin_lock_bh(&ecm_classifier_dscp_lock);
+	cdscpi->refs--;
+	DEBUG_ASSERT(cdscpi->refs >= 0, "%px: refs wrapped\n", cdscpi);
+	DEBUG_TRACE("%px: DSCP classifier deref %d\n", cdscpi, cdscpi->refs);
+	if (cdscpi->refs) {
+		int refs = cdscpi->refs;
+		spin_unlock_bh(&ecm_classifier_dscp_lock);
+		return refs;
+	}
+
+	/*
+	 * Object to be destroyed
+	 */
+	ecm_classifier_dscp_count--;
+	DEBUG_ASSERT(ecm_classifier_dscp_count >= 0, "%px: ecm_classifier_dscp_count wrap\n", cdscpi);
+
+	/*
+	 * UnLink the instance from our list
+	 */
+	if (cdscpi->next) {
+		cdscpi->next->prev = cdscpi->prev;
+	}
+	if (cdscpi->prev) {
+		cdscpi->prev->next = cdscpi->next;
+	} else {
+		DEBUG_ASSERT(ecm_classifier_dscp_instances == cdscpi, "%px: list bad %px\n", cdscpi, ecm_classifier_dscp_instances);
+		ecm_classifier_dscp_instances = cdscpi->next;
+	}
+	cdscpi->next = NULL;
+	cdscpi->prev = NULL;
+	spin_unlock_bh(&ecm_classifier_dscp_lock);
+
+	/*
+	 * Final
+	 */
+	DEBUG_INFO("%px: Final DSCP classifier instance\n", cdscpi);
+	kfree(cdscpi);
+
+	return 0;
+}
+
+/*
+ * ecm_classifier_dscp_is_bidi_packet_seen()
+ *	Return true if both direction packets are seen.
+ */
+static inline bool ecm_classifier_dscp_is_bidi_packet_seen(struct ecm_classifier_dscp_instance *cdscpi)
+{
+	return ((cdscpi->packet_seen[ECM_CONN_DIR_FLOW] == true) && (cdscpi->packet_seen[ECM_CONN_DIR_RETURN] == true));
+}
+
+/*
+ * ecm_classifier_dscp_fill_info()
+ *	Save the QoS and DSCP values in the classifier instance.
+ */
+static void ecm_classifier_dscp_fill_info(struct ecm_classifier_dscp_instance *cdscpi,
+					 ecm_tracker_sender_type_t sender,
+					 struct ecm_tracker_ip_header *ip_hdr,
+					 struct sk_buff *skb)
+{
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		cdscpi->process_response.flow_qos_tag = skb->priority;
+		cdscpi->process_response.flow_mark = skb->mark;
+		cdscpi->process_response.flow_dscp = ip_hdr->ds >> XT_DSCP_SHIFT;
+		cdscpi->packet_seen[ECM_CONN_DIR_FLOW] = true;
+	} else {
+		cdscpi->process_response.return_qos_tag = skb->priority;
+		cdscpi->process_response.return_mark = skb->mark;
+		cdscpi->process_response.return_dscp = ip_hdr->ds >> XT_DSCP_SHIFT;
+		cdscpi->packet_seen[ECM_CONN_DIR_RETURN] = true;
+	}
+}
+
+/*
+ * ecm_classifier_dscp_update()
+ *	Called from the frontend files to update the classifier instance.
+ */
+void ecm_classifier_dscp_update(struct ecm_classifier_instance *aci, enum ecm_rule_update_type type, void *arg)
+{
+	struct nf_ct_dscpremark_ext *dscpcte;
+	struct nf_conn *ct = (struct nf_conn *)arg;
+	struct ecm_classifier_dscp_instance *cdscpi = (struct ecm_classifier_dscp_instance *)aci;
+	DEBUG_CHECK_MAGIC(cdscpi, ECM_CLASSIFIER_DSCP_INSTANCE_MAGIC, "%px: magic failed\n", cdscpi);
+
+	if (type != ECM_RULE_UPDATE_TYPE_CONNMARK) {
+		DEBUG_WARN("%px: unsupported update type: %d\n", aci, type);
+		return;
+	}
+
+	/*
+	 * Since we set the mark values from the DSCP extension, we need to update this
+	 * extension as well. Because in case of a rule flush, the updated value should be read.
+	 * UDP flows should also overwrite the classifier's response mark field which is set with the
+	 * skb->mark.
+	 */
+	spin_lock_bh(&ct->lock);
+	dscpcte = nf_ct_dscpremark_ext_find(ct);
+	if (!dscpcte) {
+		spin_unlock_bh(&ct->lock);
+		DEBUG_WARN("%px: no dscp extension\n", aci);
+		return;
+	}
+	dscpcte->flow_mark = ct->mark;
+	dscpcte->reply_mark = ct->mark;
+	dscpcte->flow_set_flags |= NF_CT_DSCPREMARK_EXT_MARK;
+	dscpcte->return_set_flags |= NF_CT_DSCPREMARK_EXT_MARK;
+	spin_unlock_bh(&ct->lock);
+
+	cdscpi->process_response.flow_mark = ct->mark;
+	cdscpi->process_response.return_mark = ct->mark;
+}
+
+/*
+ * ecm_classifier_dscp_process()
+ *	Process new data for connection
+ */
+static void ecm_classifier_dscp_process(struct ecm_classifier_instance *aci, ecm_tracker_sender_type_t sender,
+						struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb,
+						struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_dscp_instance *cdscpi;
+	ecm_classifier_relevence_t relevance;
+	struct ecm_db_connection_instance *ci = NULL;
+	struct ecm_front_end_connection_instance *feci;
+	ecm_front_end_acceleration_mode_t accel_mode;
+	int protocol;
+	uint32_t became_relevant = 0;
+	struct nf_conn *ct;
+	enum ip_conntrack_info ctinfo;
+	struct nf_ct_dscpremark_ext *dscpcte;
+	bool dscp_marked = false;
+	uint64_t slow_pkts;
+
+	cdscpi = (struct ecm_classifier_dscp_instance *)aci;
+	DEBUG_CHECK_MAGIC(cdscpi, ECM_CLASSIFIER_DSCP_INSTANCE_MAGIC, "%px: magic failed\n", cdscpi);
+
+	/*
+	 * Are we yet to decide if this instance is relevant to the connection?
+	 */
+	spin_lock_bh(&ecm_classifier_dscp_lock);
+	relevance = cdscpi->process_response.relevance;
+
+	/*
+	 * Are we relevant?
+	 */
+	if (relevance == ECM_CLASSIFIER_RELEVANCE_NO) {
+		*process_response = cdscpi->process_response;
+		spin_unlock_bh(&ecm_classifier_dscp_lock);
+		return;
+	}
+
+	/*
+	 * Yes or maybe relevant.
+	 *
+	 * Need to decide our relevance to this connection.
+	 * We are only relevent to a connection iff:
+	 * 1. We are enabled.
+	 * 2. Connection can be accelerated.
+	 * 3. Connection has a ct, ct has a dscp remark extension and the rule is validated.
+	 * Any other condition and we are not and will stop analysing this connection.
+	 */
+	if (!ecm_classifier_dscp_enabled) {
+		cdscpi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+		*process_response = cdscpi->process_response;
+		spin_unlock_bh(&ecm_classifier_dscp_lock);
+		return;
+	}
+	spin_unlock_bh(&ecm_classifier_dscp_lock);
+
+	/*
+	 * Can we accelerate?
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(cdscpi->ci_serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: No ci found for %u\n", cdscpi, cdscpi->ci_serial);
+		spin_lock_bh(&ecm_classifier_dscp_lock);
+		cdscpi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+		goto dscp_classifier_out;
+	}
+
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	accel_mode = feci->accel_state_get(feci);
+	slow_pkts = ecm_front_end_get_slow_packet_count(feci);
+	feci->deref(feci);
+	protocol = ecm_db_connection_protocol_get(ci);
+	ecm_db_connection_deref(ci);
+	if (ECM_FRONT_END_ACCELERATION_NOT_POSSIBLE(accel_mode)) {
+		spin_lock_bh(&ecm_classifier_dscp_lock);
+		cdscpi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+		goto dscp_classifier_out;
+	}
+
+	/*
+	 * Is there a valid conntrack?
+	 */
+	ct = nf_ct_get(skb, &ctinfo);
+	if (!ct) {
+		DEBUG_WARN("%px: no conntrack found\n", cdscpi);
+		spin_lock_bh(&ecm_classifier_dscp_lock);
+		cdscpi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+		goto dscp_classifier_out;
+	}
+
+	/*
+	 * Is there a DSCPREMARK extension?
+	 */
+	spin_lock_bh(&ct->lock);
+	dscpcte = nf_ct_dscpremark_ext_find(ct);
+	if (!dscpcte) {
+		spin_unlock_bh(&ct->lock);
+		DEBUG_WARN("%px: no DSCP conntrack extension found\n", cdscpi);
+		spin_lock_bh(&ecm_classifier_dscp_lock);
+		cdscpi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+		goto dscp_classifier_out;
+	}
+
+	/*
+	 * Was a DSCP rule enabled for the flow using the iptables 'DSCP'
+	 * target?
+	 */
+	if (nf_conntrack_dscpremark_ext_get_dscp_rule_validity(ct)
+				== NF_CT_DSCPREMARK_EXT_RULE_VALID) {
+		DEBUG_TRACE("%px: DSCP remark extension is valid\n", cdscpi);
+		dscp_marked = true;
+	}
+	spin_unlock_bh(&ct->lock);
+
+	/*
+	 * We are relevant to the connection
+	 */
+	became_relevant = ecm_db_time_get();
+
+	spin_lock_bh(&ecm_classifier_dscp_lock);
+	cdscpi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	cdscpi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	cdscpi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+	cdscpi->process_response.became_relevant = became_relevant;
+
+	if (protocol == IPPROTO_TCP) {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,4,0)
+		/*
+		 * If DSCP conntrack extension is filled in the frontend, use those values
+		 * instead of waiting both direction traffic again.
+		 */
+		if ((dscpcte->flow_set_flags == (NF_CT_DSCPREMARK_EXT_PRIO | NF_CT_DSCPREMARK_EXT_DSCP | NF_CT_DSCPREMARK_EXT_MARK))
+			&& (dscpcte->return_set_flags == (NF_CT_DSCPREMARK_EXT_PRIO | NF_CT_DSCPREMARK_EXT_DSCP | NF_CT_DSCPREMARK_EXT_MARK))) {
+			/*
+			 * If sender and the conntrack info direction are consistent, fill the response field
+			 * with the flow/return values as it is. Otherwise reverse the assignments.
+			 */
+			if (((sender == ECM_TRACKER_SENDER_TYPE_SRC) && (IP_CT_DIR_ORIGINAL == CTINFO2DIR(ctinfo))) ||
+				((sender == ECM_TRACKER_SENDER_TYPE_DEST) && (IP_CT_DIR_REPLY == CTINFO2DIR(ctinfo)))) {
+				cdscpi->process_response.flow_qos_tag = dscpcte->flow_priority;
+				cdscpi->process_response.return_qos_tag = dscpcte->reply_priority;
+				cdscpi->process_response.flow_mark = dscpcte->flow_mark;
+				cdscpi->process_response.return_mark = dscpcte->reply_mark;
+				cdscpi->process_response.flow_dscp = dscpcte->flow_dscp;
+				cdscpi->process_response.return_dscp = dscpcte->reply_dscp;
+			} else {
+				cdscpi->process_response.flow_qos_tag = dscpcte->reply_priority;
+				cdscpi->process_response.return_qos_tag = dscpcte->flow_priority;
+				cdscpi->process_response.flow_mark = dscpcte->reply_mark;
+				cdscpi->process_response.return_mark = dscpcte->flow_mark;
+				cdscpi->process_response.flow_dscp = dscpcte->reply_dscp;
+				cdscpi->process_response.return_dscp = dscpcte->flow_dscp;
+			}
+			DEBUG_TRACE("%px: DSCP extension is used to set the QoS values\n", cdscpi);
+			goto done;
+		}
+#endif
+
+		/*
+		 * Stop the processing if both side packets are already seen.
+		 * Above the process response is already set to allow the acceleration.
+		 */
+		if (ecm_classifier_dscp_is_bidi_packet_seen(cdscpi)) {
+			DEBUG_TRACE("%px: TCP bi-di packets seen\n", cdscpi);
+			goto done;
+		}
+
+		/*
+		 * Store the QoS and DSCP info in the classifier instance and deny the
+		 * acceleration if both side info is not yet available.
+		 *
+		 * This setting is a backup setting for the QoS values, in case the DSCP
+		 * conntrack extension is not filled. This situation happens when the conntrack
+		 * table is flushed by the user with the echo f > /proc/net/nf_conntrack command.
+		 * After this flush, the conntarck entry and the ECM connection entry are destroyed,
+		 * but the TCP connection remains established. When the next packet comes to ECM,
+		 * since there is no TCP handshake, the DSCP conntarck extension is not set. So,
+		 * we need to read these values from the packet's IP header.
+		 */
+		ecm_classifier_dscp_fill_info(cdscpi, sender, ip_hdr, skb);
+		if (!ecm_classifier_dscp_is_bidi_packet_seen(cdscpi)) {
+			DEBUG_TRACE("%px: TCP both side info is not yet picked\n", cdscpi);
+			cdscpi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+			goto dscp_classifier_out;
+		}
+	} else {
+		/*
+		 * If the acceleration delay option is enabled, we will wait
+		 * until seeing both side traffic.
+		 *
+		 * There are 2 options:
+		 * Option 1: Wait forever until to see the reply direction traffic
+		 * Option 2: Wait for seeing N number of packets. If we still don't see reply,
+		 * set the uni-directional values.
+		 */
+		if (ecm_classifier_accel_delay_pkts) {
+			/*
+			 * Stop the processing if both side packets are already seen.
+			 * Above the process response is already set to allow the
+			 * acceleration.
+			 */
+			if (ecm_classifier_dscp_is_bidi_packet_seen(cdscpi)) {
+				DEBUG_TRACE("%px: UDP bi-di packets seen\n", cdscpi);
+				goto done;
+			}
+
+			/*
+			 * Store the QoS and DSCP info in the classifier instance and allow the
+			 * acceleration if both side info is not yet available.
+			 */
+			ecm_classifier_dscp_fill_info(cdscpi, sender, ip_hdr, skb);
+			if (ecm_classifier_dscp_is_bidi_packet_seen(cdscpi)) {
+				DEBUG_TRACE("%px: UDP both side info is picked\n", cdscpi);
+				goto done;
+			}
+
+			/*
+			 * Deny the acceleration if any of the below options holds true.
+			 * For option 1, we wait forever
+			 * For option 2, we wait until seeing ecm_classifier_accel_delay_pkts.
+			 */
+			if ((ecm_classifier_accel_delay_pkts == 1) || (slow_pkts < ecm_classifier_accel_delay_pkts)) {
+				DEBUG_TRACE("%px: accel_delay_pkts: %d slow_pkts: %llu accel is not allowed yet\n",
+						cdscpi, ecm_classifier_accel_delay_pkts, slow_pkts);
+				cdscpi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+				goto dscp_classifier_out;
+			}
+		}
+
+		/*
+		 * If we didn't see both direction traffic during the acceleration
+		 * delay time, we can allow the acceleration by setting the uni-directional
+		 * values to both flow and return QoS and DSCP.
+		 */
+		if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+			cdscpi->process_response.flow_qos_tag = skb->priority;
+			cdscpi->process_response.flow_mark = skb->mark;
+			cdscpi->process_response.flow_dscp = ip_hdr->ds >> XT_DSCP_SHIFT;
+
+			/*
+			 * If UDP bi-di traffic is being run, it is possible that other direction's
+			 * QoS and DSCP values are also set by the subsequent packets before we push
+			 * the rule to NSS. So, let's update them, if they are not set.
+			 */
+			if (cdscpi->process_response.return_qos_tag == 0) {
+				cdscpi->process_response.return_qos_tag = skb->priority;
+			}
+
+			if (cdscpi->process_response.return_mark == 0) {
+				cdscpi->process_response.return_mark = skb->mark;
+			}
+
+			if (cdscpi->process_response.return_dscp == 0) {
+				cdscpi->process_response.return_dscp = ip_hdr->ds >> XT_DSCP_SHIFT;
+			}
+
+		} else {
+			cdscpi->process_response.return_qos_tag = skb->priority;
+			cdscpi->process_response.return_mark = skb->mark;
+			cdscpi->process_response.return_dscp = ip_hdr->ds >> XT_DSCP_SHIFT;
+
+			/*
+			 * If UDP bi-di traffic is being run, it is possible that other direction's
+			 * QoS and DSCP values are also set by the subsequent packets before we push
+			 * the rule to NSS. So, let's update them, if they are not set.
+			 */
+			if (cdscpi->process_response.flow_qos_tag == 0) {
+				cdscpi->process_response.flow_qos_tag = skb->priority;
+			}
+
+			if (cdscpi->process_response.flow_mark == 0) {
+				cdscpi->process_response.flow_mark = skb->mark;
+			}
+
+			if (cdscpi->process_response.flow_dscp == 0) {
+				cdscpi->process_response.flow_dscp = ip_hdr->ds >> XT_DSCP_SHIFT;
+			}
+		}
+
+		/*
+		 * If the flow and return set flags are set for the MARK, we overwrite the mark field.
+		 * These values are stored in the dscp extentension in the update callback.
+		 */
+		if ((dscpcte->flow_set_flags & NF_CT_DSCPREMARK_EXT_MARK) &&
+				(dscpcte->return_set_flags & NF_CT_DSCPREMARK_EXT_MARK)) {
+			cdscpi->process_response.flow_mark = dscpcte->flow_mark;
+			cdscpi->process_response.return_mark = dscpcte->reply_mark;
+		}
+	}
+done:
+	cdscpi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG;
+	cdscpi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_MARK;
+
+#ifdef ECM_CLASSIFIER_DSCP_IGS
+	/*
+	 * IGS qostag values in conntrack are stored as per the direction of the flow.
+	 * But ECM always create an acceleration connection rule treating packet's source
+	 * address as the source of the connection irrespective of the CT's direction.
+	 * So, the IGS qostag values should be appropriately filled in ECM acceleration
+	 * connection rule.
+	 * Scenario's example: For WAN to LAN traffic for tunnel, the CT will be created from
+	 * WAN to LAN but the CI will not be created as ECM will not get the packet in this
+	 * direction. CI will be created for packet from LAN to WAN.
+	 */
+	cdscpi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG;
+	if (((sender == ECM_TRACKER_SENDER_TYPE_SRC) && (IP_CT_DIR_ORIGINAL == CTINFO2DIR(ctinfo))) ||
+		((sender == ECM_TRACKER_SENDER_TYPE_DEST) && (IP_CT_DIR_REPLY == CTINFO2DIR(ctinfo)))) {
+		cdscpi->process_response.igs_flow_qos_tag = dscpcte->igs_flow_qos_tag;
+		cdscpi->process_response.igs_return_qos_tag = dscpcte->igs_reply_qos_tag;
+	} else {
+		cdscpi->process_response.igs_return_qos_tag = dscpcte->igs_flow_qos_tag;
+		cdscpi->process_response.igs_flow_qos_tag = dscpcte->igs_reply_qos_tag;
+	}
+#endif
+	/*
+	 * Check if we need to set DSCP
+	 */
+	if (dscp_marked) {
+		cdscpi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+	}
+
+dscp_classifier_out:
+
+	/*
+	 * Return our process response
+	 */
+	*process_response = cdscpi->process_response;
+	spin_unlock_bh(&ecm_classifier_dscp_lock);
+}
+
+/*
+ * ecm_classifier_dscp_sync_to_v4()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_dscp_sync_to_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	struct ecm_classifier_dscp_instance *cdscpi __attribute__((unused));
+
+	cdscpi = (struct ecm_classifier_dscp_instance *)aci;
+	DEBUG_CHECK_MAGIC(cdscpi, ECM_CLASSIFIER_DSCP_INSTANCE_MAGIC, "%px: magic failed", cdscpi);
+}
+
+/*
+ * ecm_classifier_dscp_sync_from_v4()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_dscp_sync_from_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_dscp_instance *cdscpi __attribute__((unused));
+
+	cdscpi = (struct ecm_classifier_dscp_instance *)aci;
+	DEBUG_CHECK_MAGIC(cdscpi, ECM_CLASSIFIER_DSCP_INSTANCE_MAGIC, "%px: magic failed", cdscpi);
+}
+
+/*
+ * ecm_classifier_dscp_sync_to_v6()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_dscp_sync_to_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	struct ecm_classifier_dscp_instance *cdscpi __attribute__((unused));
+
+	cdscpi = (struct ecm_classifier_dscp_instance *)aci;
+	DEBUG_CHECK_MAGIC(cdscpi, ECM_CLASSIFIER_DSCP_INSTANCE_MAGIC, "%px: magic failed", cdscpi);
+}
+
+/*
+ * ecm_classifier_dscp_sync_from_v6()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_dscp_sync_from_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_dscp_instance *cdscpi __attribute__((unused));
+
+	cdscpi = (struct ecm_classifier_dscp_instance *)aci;
+	DEBUG_CHECK_MAGIC(cdscpi, ECM_CLASSIFIER_DSCP_INSTANCE_MAGIC, "%px: magic failed", cdscpi);
+}
+
+/*
+ * ecm_classifier_dscp_type_get()
+ *	Get type of classifier this is
+ */
+static ecm_classifier_type_t ecm_classifier_dscp_type_get(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_dscp_instance *cdscpi;
+	cdscpi = (struct ecm_classifier_dscp_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(cdscpi, ECM_CLASSIFIER_DSCP_INSTANCE_MAGIC, "%px: magic failed\n", cdscpi);
+	return ECM_CLASSIFIER_TYPE_DSCP;
+}
+
+/*
+ * ecm_classifier_dscp_last_process_response_get()
+ *	Get result code returned by the last process call
+ */
+static void ecm_classifier_dscp_last_process_response_get(struct ecm_classifier_instance *ci,
+							struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_dscp_instance *cdscpi;
+
+	cdscpi = (struct ecm_classifier_dscp_instance *)ci;
+	DEBUG_CHECK_MAGIC(cdscpi, ECM_CLASSIFIER_DSCP_INSTANCE_MAGIC, "%px: magic failed\n", cdscpi);
+
+	spin_lock_bh(&ecm_classifier_dscp_lock);
+	*process_response = cdscpi->process_response;
+	spin_unlock_bh(&ecm_classifier_dscp_lock);
+}
+
+/*
+ * ecm_classifier_dscp_reclassify_allowed()
+ *	Indicate if reclassify is allowed
+ */
+static bool ecm_classifier_dscp_reclassify_allowed(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_dscp_instance *cdscpi;
+	cdscpi = (struct ecm_classifier_dscp_instance *)ci;
+	DEBUG_CHECK_MAGIC(cdscpi, ECM_CLASSIFIER_DSCP_INSTANCE_MAGIC, "%px: magic failed\n", cdscpi);
+
+	return true;
+}
+
+/*
+ * ecm_classifier_dscp_reclassify()
+ *	Reclassify
+ */
+static void ecm_classifier_dscp_reclassify(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_dscp_instance *cdscpi;
+	cdscpi = (struct ecm_classifier_dscp_instance *)ci;
+	DEBUG_CHECK_MAGIC(cdscpi, ECM_CLASSIFIER_DSCP_INSTANCE_MAGIC, "%px: magic failed\n", cdscpi);
+
+	/*
+	 * Revert back to MAYBE relevant - we will evaluate when we get the next process() call.
+	 */
+	spin_lock_bh(&ecm_classifier_dscp_lock);
+	cdscpi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_MAYBE;
+	spin_unlock_bh(&ecm_classifier_dscp_lock);
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_classifier_dscp_state_get()
+ *	Return state
+ */
+static int ecm_classifier_dscp_state_get(struct ecm_classifier_instance *ci, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	struct ecm_classifier_dscp_instance *cdscpi;
+	struct ecm_classifier_process_response process_response;
+
+	cdscpi = (struct ecm_classifier_dscp_instance *)ci;
+	DEBUG_CHECK_MAGIC(cdscpi, ECM_CLASSIFIER_DSCP_INSTANCE_MAGIC, "%px: magic failed", cdscpi);
+
+	if ((result = ecm_state_prefix_add(sfi, "dscp"))) {
+		return result;
+	}
+
+	spin_lock_bh(&ecm_classifier_dscp_lock);
+	process_response = cdscpi->process_response;
+	spin_unlock_bh(&ecm_classifier_dscp_lock);
+
+	/*
+	 * Output our last process response
+	 */
+	if ((result = ecm_classifier_process_response_state_get(sfi, &process_response))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+/*
+ * ecm_classifier_dscp_instance_alloc()
+ *	Allocate an instance of the DSCP classifier
+ */
+struct ecm_classifier_dscp_instance *ecm_classifier_dscp_instance_alloc(struct ecm_db_connection_instance *ci)
+{
+	struct ecm_classifier_dscp_instance *cdscpi;
+
+	/*
+	 * Allocate the instance
+	 */
+	cdscpi = (struct ecm_classifier_dscp_instance *)kzalloc(sizeof(struct ecm_classifier_dscp_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!cdscpi) {
+		DEBUG_WARN("Failed to allocate DSCP instance\n");
+		return NULL;
+	}
+
+	DEBUG_SET_MAGIC(cdscpi, ECM_CLASSIFIER_DSCP_INSTANCE_MAGIC);
+	cdscpi->refs = 1;
+	cdscpi->base.process = ecm_classifier_dscp_process;
+	cdscpi->base.sync_from_v4 = ecm_classifier_dscp_sync_from_v4;
+	cdscpi->base.sync_to_v4 = ecm_classifier_dscp_sync_to_v4;
+	cdscpi->base.sync_from_v6 = ecm_classifier_dscp_sync_from_v6;
+	cdscpi->base.sync_to_v6 = ecm_classifier_dscp_sync_to_v6;
+	cdscpi->base.type_get = ecm_classifier_dscp_type_get;
+	cdscpi->base.last_process_response_get = ecm_classifier_dscp_last_process_response_get;
+	cdscpi->base.reclassify_allowed = ecm_classifier_dscp_reclassify_allowed;
+	cdscpi->base.reclassify = ecm_classifier_dscp_reclassify;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	cdscpi->base.state_get = ecm_classifier_dscp_state_get;
+#endif
+	cdscpi->base.ref = ecm_classifier_dscp_ref;
+	cdscpi->base.deref = ecm_classifier_dscp_deref;
+	cdscpi->base.update = ecm_classifier_dscp_update;
+	cdscpi->ci_serial = ecm_db_connection_serial_get(ci);
+	cdscpi->process_response.process_actions = 0;
+	cdscpi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_MAYBE;
+
+	spin_lock_bh(&ecm_classifier_dscp_lock);
+
+	/*
+	 * Final check if we are pending termination
+	 */
+	if (ecm_classifier_dscp_terminate_pending) {
+		spin_unlock_bh(&ecm_classifier_dscp_lock);
+		DEBUG_INFO("%px: Terminating\n", ci);
+		kfree(cdscpi);
+		return NULL;
+	}
+
+	/*
+	 * Link the new instance into our list at the head
+	 */
+	cdscpi->next = ecm_classifier_dscp_instances;
+	if (ecm_classifier_dscp_instances) {
+		ecm_classifier_dscp_instances->prev = cdscpi;
+	}
+	ecm_classifier_dscp_instances = cdscpi;
+
+	/*
+	 * Increment stats
+	 */
+	ecm_classifier_dscp_count++;
+	DEBUG_ASSERT(ecm_classifier_dscp_count > 0, "%px: ecm_classifier_dscp_count wrap\n", cdscpi);
+	spin_unlock_bh(&ecm_classifier_dscp_lock);
+
+	DEBUG_INFO("DSCP instance alloc: %px\n", cdscpi);
+	return cdscpi;
+}
+EXPORT_SYMBOL(ecm_classifier_dscp_instance_alloc);
+
+/*
+ * ecm_classifier_dscp_init()
+ */
+int ecm_classifier_dscp_init(struct dentry *dentry)
+{
+	DEBUG_INFO("DSCP classifier Module init\n");
+
+	ecm_classifier_dscp_dentry = debugfs_create_dir("ecm_classifier_dscp", dentry);
+	if (!ecm_classifier_dscp_dentry) {
+		DEBUG_ERROR("Failed to create ecm dscp directory in debugfs\n");
+		return -1;
+	}
+
+	if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_dscp_dentry,
+					(u32 *)&ecm_classifier_dscp_enabled)) {
+		DEBUG_ERROR("Failed to create dscp enabled file in debugfs\n");
+		debugfs_remove_recursive(ecm_classifier_dscp_dentry);
+		return -1;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_classifier_dscp_init);
+
+/*
+ * ecm_classifier_dscp_exit()
+ */
+void ecm_classifier_dscp_exit(void)
+{
+	DEBUG_INFO("DSCP classifier Module exit\n");
+
+	spin_lock_bh(&ecm_classifier_dscp_lock);
+	ecm_classifier_dscp_terminate_pending = true;
+	spin_unlock_bh(&ecm_classifier_dscp_lock);
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_classifier_dscp_dentry) {
+		debugfs_remove_recursive(ecm_classifier_dscp_dentry);
+	}
+}
+EXPORT_SYMBOL(ecm_classifier_dscp_exit);
diff --git a/qca-nss-ecm/ecm_classifier_dscp.h b/qca-nss-ecm/ecm_classifier_dscp.h
new file mode 100644
index 0000000..214fbc6
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_dscp.h
@@ -0,0 +1,22 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+struct ecm_classifier_dscp_instance;
+struct ecm_classifier_dscp_instance *ecm_classifier_dscp_instance_alloc(struct ecm_db_connection_instance *ci);
+void ecm_classifier_dscp_update(struct ecm_classifier_instance *aci, enum ecm_rule_update_type type, void *arg);
diff --git a/qca-nss-ecm/ecm_classifier_emesh.c b/qca-nss-ecm/ecm_classifier_emesh.c
new file mode 100644
index 0000000..f8e8c80
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_emesh.c
@@ -0,0 +1,1028 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/debugfs.h>
+#include <linux/string.h>
+#include <linux/netfilter_bridge.h>
+#include <net/ip.h>
+#include <linux/inet.h>
+#include <sp_api.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_CLASSIFIER_EMESH_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_db.h"
+#include "ecm_interface.h"
+#include "ecm_classifier_emesh_public.h"
+#include "ecm_front_end_ipv4.h"
+#include "ecm_front_end_ipv6.h"
+#include "ecm_front_end_common.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_CLASSIFIER_EMESH_INSTANCE_MAGIC 0xFECA
+
+/*
+ * Latency parameter operation
+ */
+#define ECM_CLASSIFIER_EMESH_ADD_LATENCY_PARAMS 0x1
+#define ECM_CLASSIFIER_EMESH_SUB_LATENCY_PARAMS 0x2
+
+/*
+ * Flag to enable SPM rule lookup
+ */
+#define ECM_CLASSIFIER_EMESH_ENABLE_SPM_RULE_LOOKUP 0x1
+#define ECM_CLASSIFIER_EMESH_ENABLE_LATENCY_UPDATE 0x2
+
+/*
+ * struct ecm_classifier_emesh_instance
+ * 	State to allow tracking of dynamic qos for a connection
+ */
+struct ecm_classifier_emesh_instance {
+	struct ecm_classifier_instance base;			/* Base type */
+
+	struct ecm_classifier_emesh_instance *next;		/* Next classifier state instance (for accouting and reporting purposes) */
+	struct ecm_classifier_emesh_instance *prev;		/* Next classifier state instance (for accouting and reporting purposes) */
+
+	uint32_t ci_serial;					/* RO: Serial of the connection */
+	uint32_t pcp[ECM_CONN_DIR_MAX];				/* PCP values for the connections */
+	struct ecm_classifier_process_response process_response;/* Last process response computed */
+
+	int refs;						/* Integer to trap we never go negative */
+	uint8_t packet_seen[ECM_CONN_DIR_MAX];				/* Per direction packet seen flag */
+	uint32_t service_interval_dl;		/* wlan downlink latency parameter: Service interval associated with this connection */
+	uint32_t burst_size_dl;			/* wlan downlink latency parameter: Burst Size associated with this connection */
+	uint32_t service_interval_ul;		/* wlan uplink latency parameter: Service interval associated with this connection */
+	uint32_t burst_size_ul;			/* wlan uplink latency parameter: Burst Size associated with this connection */
+
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+/*
+ * Operational control
+ */
+static uint32_t ecm_classifier_emesh_enabled;			/* Operational behaviour */
+static uint32_t ecm_classifier_emesh_latency_config_enabled;	/* Mesh Latency profile enable flag */
+
+/*
+ * Management thread control
+ */
+static bool ecm_classifier_emesh_terminate_pending = false;	/* True when the user wants us to terminate */
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_classifier_emesh_dentry;
+
+/*
+ * Locking of the classifier structures
+ */
+static DEFINE_SPINLOCK(ecm_classifier_emesh_lock);			/* Protect SMP access. */
+
+/*
+ * List of our classifier instances
+ */
+static struct ecm_classifier_emesh_instance *ecm_classifier_emesh_instances = NULL;
+								/* list of all active instances */
+static int ecm_classifier_emesh_count = 0;			/* Tracks number of instances allocated */
+
+/*
+ * Callback structure to support Mesh latency param config in WLAN driver
+ */
+static struct ecm_classifier_emesh_callbacks ecm_emesh;
+
+/*
+ * ecm_classifier_emesh_ref()
+ *	Ref
+ */
+static void ecm_classifier_emesh_ref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_emesh_instance *cemi;
+	cemi = (struct ecm_classifier_emesh_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(cemi, ECM_CLASSIFIER_EMESH_INSTANCE_MAGIC, "%px: magic failed\n", cemi);
+	spin_lock_bh(&ecm_classifier_emesh_lock);
+	cemi->refs++;
+	DEBUG_TRACE("%px: cemi ref %d\n", cemi, cemi->refs);
+	DEBUG_ASSERT(cemi->refs > 0, "%px: ref wrap\n", cemi);
+	spin_unlock_bh(&ecm_classifier_emesh_lock);
+}
+
+/*
+ * ecm_classifier_emesh_deref()
+ *	Deref
+ */
+static int ecm_classifier_emesh_deref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_emesh_instance *cemi;
+	cemi = (struct ecm_classifier_emesh_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(cemi, ECM_CLASSIFIER_EMESH_INSTANCE_MAGIC, "%px: magic failed\n", cemi);
+	spin_lock_bh(&ecm_classifier_emesh_lock);
+	cemi->refs--;
+	DEBUG_ASSERT(cemi->refs >= 0, "%px: refs wrapped\n", cemi);
+	DEBUG_TRACE("%px: EMESH classifier deref %d\n", cemi, cemi->refs);
+	if (cemi->refs) {
+		int refs = cemi->refs;
+		spin_unlock_bh(&ecm_classifier_emesh_lock);
+		return refs;
+	}
+
+	/*
+	 * Object to be destroyed
+	 */
+	ecm_classifier_emesh_count--;
+	DEBUG_ASSERT(ecm_classifier_emesh_count >= 0, "%px: ecm_classifier_emesh_count wrap\n", cemi);
+
+	/*
+	 * UnLink the instance from our list
+	 */
+	if (cemi->next) {
+		cemi->next->prev = cemi->prev;
+	}
+
+	if (cemi->prev) {
+		cemi->prev->next = cemi->next;
+	} else {
+		DEBUG_ASSERT(ecm_classifier_emesh_instances == cemi, "%px: list bad %px\n", cemi, ecm_classifier_emesh_instances);
+		ecm_classifier_emesh_instances = cemi->next;
+	}
+	spin_unlock_bh(&ecm_classifier_emesh_lock);
+
+	/*
+	 * Final
+	 */
+	DEBUG_INFO("%px: Final EMESH classifier instance\n", cemi);
+	kfree(cemi);
+
+	return 0;
+}
+
+/*
+ * ecm_classifier_emesh_is_bidi_packet_seen()
+ *	Return true if both direction packets are seen.
+ */
+static inline bool ecm_classifier_emesh_is_bidi_packet_seen(struct ecm_classifier_emesh_instance *cemi)
+{
+	return ((cemi->packet_seen[ECM_CONN_DIR_FLOW] == true) && (cemi->packet_seen[ECM_CONN_DIR_RETURN] == true));
+}
+
+/*
+ * ecm_classifier_emesh_fill_pcp()
+ *	Save the PCP value in the classifier instance.
+ */
+static void ecm_classifier_emesh_fill_pcp(struct ecm_classifier_emesh_instance *cemi,
+		 ecm_tracker_sender_type_t sender, enum ip_conntrack_info ctinfo,
+		 struct sk_buff *skb)
+{
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		cemi->pcp[ECM_CONN_DIR_FLOW] = skb->priority;
+		cemi->packet_seen[ECM_CONN_DIR_FLOW] = true;
+	} else {
+		cemi->pcp[ECM_CONN_DIR_RETURN] = skb->priority;
+		cemi->packet_seen[ECM_CONN_DIR_RETURN] = true;
+	}
+}
+
+/*
+ * ecm_classifier_emesh_process()
+ *	Process new data for connection
+ */
+static void ecm_classifier_emesh_process(struct ecm_classifier_instance *aci, ecm_tracker_sender_type_t sender,
+						struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb,
+						struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_emesh_instance *cemi;
+	ecm_classifier_relevence_t relevance;
+	struct ecm_db_connection_instance *ci = NULL;
+	struct ecm_front_end_connection_instance *feci;
+	ecm_front_end_acceleration_mode_t accel_mode;
+	uint32_t became_relevant = 0;
+	struct nf_conn *ct;
+	enum ip_conntrack_info ctinfo;
+	int protocol;
+	uint64_t slow_pkts;
+
+	cemi = (struct ecm_classifier_emesh_instance *)aci;
+	DEBUG_CHECK_MAGIC(cemi, ECM_CLASSIFIER_EMESH_INSTANCE_MAGIC, "%px: magic failed\n", cemi);
+
+	spin_lock_bh(&ecm_classifier_emesh_lock);
+	relevance = cemi->process_response.relevance;
+
+	/*
+	 * Are we relevant?
+	 * If the classifier is set as ir-relevant to the connection,
+	 * the process response of the classifier instance was set from
+	 * the earlier packets.
+	 */
+	if (relevance == ECM_CLASSIFIER_RELEVANCE_NO) {
+		/*
+		 * Lock still held
+		 */
+		goto emesh_classifier_out;
+	}
+
+	/*
+	 * Yes or maybe relevant.
+	 *
+	 * Need to decide our relevance to this connection.
+	 * We are only relevent to a connection iff:
+	 * 1. We are enabled.
+	 * 2. Connection can be accelerated.
+	 * Any other condition and we are not and will stop analysing this connection.
+	 */
+	if (!ecm_classifier_emesh_enabled) {
+		/*
+		 * Lock still held
+		 */
+		cemi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+		goto emesh_classifier_out;
+	}
+	spin_unlock_bh(&ecm_classifier_emesh_lock);
+
+	/*
+	 * Can we accelerate?
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(cemi->ci_serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: No ci found for %u\n", cemi, cemi->ci_serial);
+		spin_lock_bh(&ecm_classifier_emesh_lock);
+		cemi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+		goto emesh_classifier_out;
+	}
+
+	/*
+	 * Check if SPM rule lookup flag is enabled
+	 */
+	if (ecm_classifier_emesh_latency_config_enabled & ECM_CLASSIFIER_EMESH_ENABLE_SPM_RULE_LOOKUP) {
+		uint8_t dmac[ETH_ALEN];
+		uint8_t smac[ETH_ALEN];
+		if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+			DEBUG_TRACE("%px: sender is SRC\n", aci);
+			ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, smac);
+			ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, dmac);
+		} else {
+			DEBUG_TRACE("%px: sender is DEST\n", aci);
+			ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, smac);
+			ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, dmac);
+		}
+
+		/*
+		 * Invoke SPM rule lookup API for skb priority update
+		 * For bridging traffic, it will be matched with the rule table on SPM prerouting hook
+		 */
+		if (skb->skb_iif != skb->dev->ifindex) {
+			sp_mapdb_apply(skb, smac, dmac);
+		}
+	}
+
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	accel_mode = feci->accel_state_get(feci);
+	slow_pkts = ecm_front_end_get_slow_packet_count(feci);
+	feci->deref(feci);
+	protocol = ecm_db_connection_protocol_get(ci);
+	ecm_db_connection_deref(ci);
+
+	if (ECM_FRONT_END_ACCELERATION_NOT_POSSIBLE(accel_mode)) {
+		spin_lock_bh(&ecm_classifier_emesh_lock);
+		cemi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+		goto emesh_classifier_out;
+	}
+
+	/*
+	 * Is there a valid conntrack?
+	 */
+	ct = nf_ct_get(skb, &ctinfo);
+	if (!ct) {
+		spin_lock_bh(&ecm_classifier_emesh_lock);
+		cemi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+		goto emesh_classifier_out;
+	}
+
+	/*
+	 * We are relevant to the connection.
+	 * Set the process response to its default value, that is, to
+	 * allow the acceleration.
+	 */
+	became_relevant = ecm_db_time_get();
+
+	spin_lock_bh(&ecm_classifier_emesh_lock);
+	cemi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	cemi->process_response.became_relevant = became_relevant;
+
+	cemi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	cemi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+	spin_unlock_bh(&ecm_classifier_emesh_lock);
+
+	if (protocol == IPPROTO_TCP) {
+		/*
+		 * Stop the processing if both side packets are already seen.
+		 * Above the process response is already set to allow the acceleration.
+		 */
+		if (ecm_classifier_emesh_is_bidi_packet_seen(cemi)) {
+			spin_lock_bh(&ecm_classifier_emesh_lock);
+			goto emesh_classifier_out;
+		}
+
+		/*
+		 * Store the PCP value in the classifier instance and deny the
+		 * acceleration if both side PCP value is not yet available.
+		 */
+		ecm_classifier_emesh_fill_pcp(cemi, sender, ctinfo, skb);
+		if (!ecm_classifier_emesh_is_bidi_packet_seen(cemi)) {
+			DEBUG_TRACE("%px: Both side PCP value is not yet picked\n", cemi);
+			spin_lock_bh(&ecm_classifier_emesh_lock);
+			cemi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+			goto emesh_classifier_out;
+		}
+	} else {
+		/*
+		 * If the acceleration delay option is enabled, we will wait
+		 * until seeing both side traffic.
+		 *
+		 * There are 2 options:
+		 * Option 1: Wait forever until to see the reply direction traffic
+		 * Option 2: Wait for seeing N number of packets. If we still don't see reply,
+		 * set the uni-directional values.
+		 */
+		if (ecm_classifier_accel_delay_pkts) {
+			/*
+			 * Stop the processing if both side packets are already seen.
+			 * Above the process response is already set to allow the
+			 * acceleration.
+			 */
+			if (ecm_classifier_emesh_is_bidi_packet_seen(cemi)) {
+				spin_lock_bh(&ecm_classifier_emesh_lock);
+				goto emesh_classifier_out;
+			}
+
+			/*
+			 * Store the PCP value in the classifier instance and allow the
+			 * acceleration if both side PCP value is not yet available.
+			 */
+			ecm_classifier_emesh_fill_pcp(cemi, sender, ctinfo, skb);
+			if (ecm_classifier_emesh_is_bidi_packet_seen(cemi)) {
+				DEBUG_TRACE("%px: Both side PCP value is picked\n", cemi);
+				goto done;
+			}
+
+			/*
+			 * Deny the acceleration if any of the below options holds true.
+			 * For option 1, we wait forever
+			 * For option 2, we wait until seeing ecm_classifier_accel_delay_pkts.
+			 */
+			if ((ecm_classifier_accel_delay_pkts == 1) || (slow_pkts < ecm_classifier_accel_delay_pkts)) {
+				DEBUG_TRACE("%px: accel_delay_pkts: %d slow_pkts: %llu accel is not allowed yet\n",
+						cemi, ecm_classifier_accel_delay_pkts, slow_pkts);
+				spin_lock_bh(&ecm_classifier_emesh_lock);
+				cemi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+				goto emesh_classifier_out;
+			}
+		}
+
+		/*
+		 * If we didn't see both direction traffic during the acceleration
+		 * delay time, we can allow the acceleration by setting the uni-directional
+		 * values to both flow and return PCP.
+		 */
+		cemi->pcp[ECM_CONN_DIR_FLOW] = skb->priority;
+		cemi->pcp[ECM_CONN_DIR_RETURN] = skb->priority;
+	}
+
+done:
+	DEBUG_TRACE("Protocol: %d, Flow Priority: %d, Return priority: %d, sender: %d\n",
+			protocol, cemi->pcp[ECM_CONN_DIR_FLOW],
+			cemi->pcp[ECM_CONN_DIR_RETURN], sender);
+
+	spin_lock_bh(&ecm_classifier_emesh_lock);
+
+	cemi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG;
+
+	if (((sender == ECM_TRACKER_SENDER_TYPE_SRC) && (IP_CT_DIR_ORIGINAL == CTINFO2DIR(ctinfo))) ||
+			((sender == ECM_TRACKER_SENDER_TYPE_DEST) && (IP_CT_DIR_REPLY == CTINFO2DIR(ctinfo)))) {
+		cemi->process_response.flow_qos_tag = cemi->pcp[ECM_CONN_DIR_FLOW];
+		cemi->process_response.return_qos_tag = cemi->pcp[ECM_CONN_DIR_RETURN];
+	} else {
+		cemi->process_response.flow_qos_tag = cemi->pcp[ECM_CONN_DIR_RETURN];
+		cemi->process_response.return_qos_tag = cemi->pcp[ECM_CONN_DIR_FLOW];
+	}
+
+emesh_classifier_out:
+
+	/*
+	 * Return our process response
+	 */
+	*process_response = cemi->process_response;
+	spin_unlock_bh(&ecm_classifier_emesh_lock);
+}
+
+/*
+ * ecm_classifier_emesh_update_latency_param_on_conn_decel()
+ *	Update mesh latency parameters to wlan host driver when a connection gets decelerated in ECM
+ */
+void ecm_classifier_emesh_update_latency_param_on_conn_decel(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	struct ecm_classifier_emesh_instance *cemi;
+	struct ecm_db_connection_instance *ci;
+	uint8_t peer_mac[ETH_ALEN];
+
+	cemi = (struct ecm_classifier_emesh_instance *)aci;
+	DEBUG_CHECK_MAGIC(cemi, ECM_CLASSIFIER_EMESH_INSTANCE_MAGIC, "%px: magic failed", cemi);
+
+	/*
+	 * Return if E-Mesh functionality is not enabled.
+	 */
+	if (!ecm_classifier_emesh_enabled) {
+		return;
+	}
+
+	if (!(ecm_classifier_emesh_latency_config_enabled
+				& ECM_CLASSIFIER_EMESH_ENABLE_LATENCY_UPDATE)) {
+		return;
+	}
+
+	if (!ecm_emesh.update_peer_mesh_latency_params) {
+		return;
+	}
+
+	ci = ecm_db_connection_serial_find_and_ref(cemi->ci_serial);
+	if (!ci) {
+		DEBUG_WARN("%px: No ci found for %u\n", cemi, cemi->ci_serial);
+		return;
+	}
+
+	/*
+	 * Get mac address for destination node
+	 */
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, peer_mac);
+	ecm_emesh.update_peer_mesh_latency_params(peer_mac,
+			cemi->service_interval_dl, cemi->burst_size_dl, cemi->service_interval_ul, cemi->burst_size_ul,
+			cemi->pcp[ECM_CONN_DIR_FLOW], ECM_CLASSIFIER_EMESH_SUB_LATENCY_PARAMS);
+
+	/*
+	 * Get mac address for source node
+	 */
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, peer_mac);
+	ecm_emesh.update_peer_mesh_latency_params(peer_mac,
+			cemi->service_interval_dl, cemi->burst_size_dl, cemi->service_interval_ul, cemi->burst_size_ul,
+			cemi->pcp[ECM_CONN_DIR_FLOW], ECM_CLASSIFIER_EMESH_SUB_LATENCY_PARAMS);
+
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_classifier_emesh_sync_to_v4()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_emesh_sync_to_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	struct ecm_classifier_emesh_instance *cemi;
+	cemi = (struct ecm_classifier_emesh_instance *)aci;
+	DEBUG_CHECK_MAGIC(cemi, ECM_CLASSIFIER_EMESH_INSTANCE_MAGIC, "%px: magic failed", cemi);
+
+	switch(sync->reason) {
+	case ECM_FRONT_END_IPV4_RULE_SYNC_REASON_FLUSH:
+	case ECM_FRONT_END_IPV4_RULE_SYNC_REASON_EVICT:
+	case ECM_FRONT_END_IPV4_RULE_SYNC_REASON_DESTROY:
+		ecm_classifier_emesh_update_latency_param_on_conn_decel(aci, sync);
+		break;
+	default:
+		break;
+	}
+}
+
+/*
+ * ecm_classifier_emesh_update_wlan_latency_params_on_conn_accel()
+ *	Update wifi latency parameters associated with SP rule to wlan host driver
+ *	when a connection getting accelerated in ECM
+ */
+static void ecm_classifier_emesh_update_wlan_latency_params_on_conn_accel(struct ecm_classifier_instance *aci,
+		struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_emesh_instance *cemi;
+	struct ecm_db_connection_instance *ci;
+	uint8_t service_interval_dl;
+	uint32_t burst_size_dl;
+	uint8_t service_interval_ul;
+	uint32_t burst_size_ul;
+	struct sk_buff *skb;
+	uint8_t dmac[ETH_ALEN];
+	uint8_t smac[ETH_ALEN];
+
+	/*
+	 * Return if E-Mesh functionality is not enabled.
+	 */
+	if (!ecm_classifier_emesh_enabled) {
+		return;
+	}
+
+	if (!(ecm_classifier_emesh_latency_config_enabled
+			& ECM_CLASSIFIER_EMESH_ENABLE_LATENCY_UPDATE)) {
+		/*
+		 * Flow based latency parameter updation to WLAN host driver not enabled
+		 */
+		return;
+	}
+
+	/*
+	 * When mesh low latency feature flags is enabled, ECM gets
+	 * latency config parameters associated with a SPM rule and send
+	 * to WLAN host driver invoking callback
+	 */
+	if (!ecm_emesh.update_peer_mesh_latency_params) {
+		return;
+	}
+
+	skb = ecrc->skb;
+
+	cemi = (struct ecm_classifier_emesh_instance *)aci;
+	DEBUG_CHECK_MAGIC(cemi, ECM_CLASSIFIER_EMESH_INSTANCE_MAGIC, "%px: magic failed", cemi);
+
+	ci = ecm_db_connection_serial_find_and_ref(cemi->ci_serial);
+	if (!ci) {
+		DEBUG_WARN("%px: No ci found for %u\n", cemi, cemi->ci_serial);
+		return;
+	}
+
+	/*
+	 * Invoke SPM rule lookup API to update skb priority
+	 * When latency config is enabled, fetch latency parameter
+	 * associated with a SPM rule.Since we do not know direction of
+	 * connection, we get src and destination mac address of both
+	 * connection and let wlan driver find corresponding wlan peer
+	 * connected
+	 */
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, smac);
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, dmac);
+	sp_mapdb_get_wlan_latency_params(skb, &service_interval_dl, &burst_size_dl,
+			&service_interval_ul, &burst_size_ul, smac, dmac);
+
+	spin_lock_bh(&ecm_classifier_emesh_lock);
+
+	/*
+	 * Update latency parameters to accelerated connection
+	 */
+	cemi->service_interval_dl = service_interval_dl;
+	cemi->burst_size_dl = burst_size_dl;
+	cemi->service_interval_ul = service_interval_ul;
+	cemi->burst_size_ul = burst_size_ul;
+	spin_unlock_bh(&ecm_classifier_emesh_lock);
+
+	/*
+	 * If one of the latency parameters are zero, there could be
+	 * 2 possibilities - 1. no rule match 2. sp rule does not have
+	 * latency parameter configured.
+	 */
+	if ((service_interval_ul && burst_size_ul) || (service_interval_dl && burst_size_dl)) {
+		/*
+		 * Send destination mac address of this connection
+		 */
+		ecm_emesh.update_peer_mesh_latency_params(dmac,
+				service_interval_dl, burst_size_dl, service_interval_ul, burst_size_ul,
+				skb->priority, ECM_CLASSIFIER_EMESH_ADD_LATENCY_PARAMS);
+	}
+
+	/*
+	 * Get latency parameter for other direction
+	 */
+	sp_mapdb_get_wlan_latency_params(skb, &service_interval_dl, &burst_size_dl,
+			&service_interval_ul, &burst_size_ul, dmac, smac);
+
+	if ((service_interval_ul && burst_size_ul) || (service_interval_dl && burst_size_dl)) {
+		/*
+		 * Send source mac address of this connection
+		 */
+		ecm_emesh.update_peer_mesh_latency_params(smac,
+				service_interval_dl, burst_size_dl, service_interval_ul, burst_size_ul,
+				skb->priority, ECM_CLASSIFIER_EMESH_ADD_LATENCY_PARAMS);
+	}
+
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_classifier_emesh_sync_from_v4()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_emesh_sync_from_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	ecm_classifier_emesh_update_wlan_latency_params_on_conn_accel(aci, ecrc);
+
+}
+
+/*
+ * ecm_classifier_emesh_sync_to_v6()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_emesh_sync_to_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	struct ecm_classifier_emesh_instance *cemi;
+	cemi = (struct ecm_classifier_emesh_instance *)aci;
+	DEBUG_CHECK_MAGIC(cemi, ECM_CLASSIFIER_EMESH_INSTANCE_MAGIC, "%px: magic failed", cemi);
+
+	switch(sync->reason) {
+	case ECM_FRONT_END_IPV6_RULE_SYNC_REASON_FLUSH:
+	case ECM_FRONT_END_IPV6_RULE_SYNC_REASON_EVICT:
+	case ECM_FRONT_END_IPV6_RULE_SYNC_REASON_DESTROY:
+		ecm_classifier_emesh_update_latency_param_on_conn_decel(aci, sync);
+		break;
+	default:
+		break;
+	}
+}
+
+/*
+ * ecm_classifier_emesh_sync_from_v6()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_emesh_sync_from_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	ecm_classifier_emesh_update_wlan_latency_params_on_conn_accel(aci, ecrc);
+}
+
+/*
+ * ecm_classifier_emesh_type_get()
+ *	Get type of classifier this is
+ */
+static ecm_classifier_type_t ecm_classifier_emesh_type_get(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_emesh_instance *cemi;
+	cemi = (struct ecm_classifier_emesh_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(cemi, ECM_CLASSIFIER_EMESH_INSTANCE_MAGIC, "%px: magic failed\n", cemi);
+	return ECM_CLASSIFIER_TYPE_EMESH;
+}
+
+/*
+ * ecm_classifier_emesh_last_process_response_get()
+ *	Get result code returned by the last process call
+ */
+static void ecm_classifier_emesh_last_process_response_get(struct ecm_classifier_instance *ci,
+							struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_emesh_instance *cemi;
+
+	cemi = (struct ecm_classifier_emesh_instance *)ci;
+	DEBUG_CHECK_MAGIC(cemi, ECM_CLASSIFIER_EMESH_INSTANCE_MAGIC, "%px: magic failed\n", cemi);
+
+	spin_lock_bh(&ecm_classifier_emesh_lock);
+	*process_response = cemi->process_response;
+	spin_unlock_bh(&ecm_classifier_emesh_lock);
+}
+
+/*
+ * ecm_classifier_emesh_reclassify_allowed()
+ *	Indicate if reclassify is allowed
+ */
+static bool ecm_classifier_emesh_reclassify_allowed(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_emesh_instance *cemi;
+	cemi = (struct ecm_classifier_emesh_instance *)ci;
+	DEBUG_CHECK_MAGIC(cemi, ECM_CLASSIFIER_EMESH_INSTANCE_MAGIC, "%px: magic failed\n", cemi);
+
+	return true;
+}
+
+/*
+ * ecm_classifier_emesh_reclassify()
+ *	Reclassify
+ */
+static void ecm_classifier_emesh_reclassify(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_emesh_instance *cemi;
+	cemi = (struct ecm_classifier_emesh_instance *)ci;
+	DEBUG_CHECK_MAGIC(cemi, ECM_CLASSIFIER_EMESH_INSTANCE_MAGIC, "%px: magic failed\n", cemi);
+
+	/*
+	 * Revert back to MAYBE relevant - we will evaluate when we get the next process() call.
+	 */
+	spin_lock_bh(&ecm_classifier_emesh_lock);
+	cemi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_MAYBE;
+	spin_unlock_bh(&ecm_classifier_emesh_lock);
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_classifier_emesh_state_get()
+ *	Return state
+ */
+static int ecm_classifier_emesh_state_get(struct ecm_classifier_instance *ci, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	struct ecm_classifier_emesh_instance *cemi;
+	struct ecm_classifier_process_response process_response;
+
+	cemi = (struct ecm_classifier_emesh_instance *)ci;
+	DEBUG_CHECK_MAGIC(cemi, ECM_CLASSIFIER_EMESH_INSTANCE_MAGIC, "%px: magic failed", cemi);
+
+	if ((result = ecm_state_prefix_add(sfi, "emesh"))) {
+		return result;
+	}
+
+	spin_lock_bh(&ecm_classifier_emesh_lock);
+	process_response = cemi->process_response;
+	spin_unlock_bh(&ecm_classifier_emesh_lock);
+
+	/*
+	 * Output our last process response
+	 */
+	if ((result = ecm_classifier_process_response_state_get(sfi, &process_response))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+/*
+ * ecm_classifier_emesh_instance_alloc()
+ *	Allocate an instance of the EMESH classifier
+ */
+struct ecm_classifier_emesh_instance *ecm_classifier_emesh_instance_alloc(struct ecm_db_connection_instance *ci)
+{
+	struct ecm_classifier_emesh_instance *cemi;
+
+	/*
+	 * Allocate the instance
+	 */
+	cemi = (struct ecm_classifier_emesh_instance *)kzalloc(sizeof(struct ecm_classifier_emesh_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!cemi) {
+		DEBUG_WARN("Failed to allocate EMESH instance\n");
+		return NULL;
+	}
+
+	DEBUG_SET_MAGIC(cemi, ECM_CLASSIFIER_EMESH_INSTANCE_MAGIC);
+	cemi->refs = 1;
+	cemi->base.process = ecm_classifier_emesh_process;
+	cemi->base.sync_from_v4 = ecm_classifier_emesh_sync_from_v4;
+	cemi->base.sync_to_v4 = ecm_classifier_emesh_sync_to_v4;
+	cemi->base.sync_from_v6 = ecm_classifier_emesh_sync_from_v6;
+	cemi->base.sync_to_v6 = ecm_classifier_emesh_sync_to_v6;
+	cemi->base.type_get = ecm_classifier_emesh_type_get;
+	cemi->base.last_process_response_get = ecm_classifier_emesh_last_process_response_get;
+	cemi->base.reclassify_allowed = ecm_classifier_emesh_reclassify_allowed;
+	cemi->base.reclassify = ecm_classifier_emesh_reclassify;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	cemi->base.state_get = ecm_classifier_emesh_state_get;
+#endif
+	cemi->base.ref = ecm_classifier_emesh_ref;
+	cemi->base.deref = ecm_classifier_emesh_deref;
+	cemi->ci_serial = ecm_db_connection_serial_get(ci);
+	cemi->process_response.process_actions = 0;
+	cemi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_MAYBE;
+
+	spin_lock_bh(&ecm_classifier_emesh_lock);
+
+	/*
+	 * Final check if we are pending termination
+	 */
+	if (ecm_classifier_emesh_terminate_pending) {
+		spin_unlock_bh(&ecm_classifier_emesh_lock);
+		DEBUG_INFO("%px: Terminating\n", ci);
+		kfree(cemi);
+		return NULL;
+	}
+
+	/*
+	 * Link the new instance into our list at the head
+	 */
+	cemi->next = ecm_classifier_emesh_instances;
+	if (ecm_classifier_emesh_instances) {
+		ecm_classifier_emesh_instances->prev = cemi;
+	}
+	ecm_classifier_emesh_instances = cemi;
+
+	/*
+	 * Increment stats
+	 */
+	ecm_classifier_emesh_count++;
+	DEBUG_ASSERT(ecm_classifier_emesh_count > 0, "%px: ecm_classifier_emesh_count wrap\n", cemi);
+	spin_unlock_bh(&ecm_classifier_emesh_lock);
+
+	DEBUG_INFO("EMESH instance alloc: %px\n", cemi);
+	return cemi;
+}
+EXPORT_SYMBOL(ecm_classifier_emesh_instance_alloc);
+
+
+/*
+ * ecm_classifier_emesh_rule_update_cb()
+ *	Callback for service prioritization notification update.
+ */
+static void ecm_classifier_emesh_rule_update_cb(uint8_t add_rm_md,
+		         uint32_t valid_flag, struct sp_rule *r)
+{
+	ip_addr_t ip_addr;
+	struct in6_addr ipv6addr = IN6ADDR_ANY_INIT;
+	/*
+	 * Return if E-Mesh functionality is not enabled.
+	 */
+	if (!ecm_classifier_emesh_enabled) {
+		return;
+	}
+
+	DEBUG_TRACE("SP rule update notification received\n");
+	/*
+	 * Order of priority of rule fields to match and flush connections:
+	 * Port ---> IP address ---> Mac Address ---> Protocol
+	 * Flush connections for both directions as ECM creates reverse
+	 * direction rule as well
+	 */
+	if (valid_flag & SP_RULE_FLAG_MATCH_SRC_PORT) {
+		ecm_db_connection_defunct_by_port(r->inner.src_port, ECM_DB_OBJ_DIR_FROM);
+		ecm_db_connection_defunct_by_port(r->inner.src_port, ECM_DB_OBJ_DIR_TO);
+		return;
+	}
+
+	if (valid_flag & SP_RULE_FLAG_MATCH_DST_PORT) {
+		ecm_db_connection_defunct_by_port(r->inner.dst_port, ECM_DB_OBJ_DIR_FROM);
+		ecm_db_connection_defunct_by_port(r->inner.dst_port, ECM_DB_OBJ_DIR_TO);
+		return;
+	}
+
+	if (valid_flag & SP_RULE_FLAG_MATCH_SRC_IPV4) {
+		ECM_NIN4_ADDR_TO_IP_ADDR(ip_addr, r->inner.src_ipv4_addr);
+		ecm_db_host_connections_defunct_by_dir(ip_addr, ECM_DB_OBJ_DIR_FROM);
+		ecm_db_host_connections_defunct_by_dir(ip_addr, ECM_DB_OBJ_DIR_TO);
+		return;
+	}
+
+	if (valid_flag & SP_RULE_FLAG_MATCH_DST_IPV4) {
+		ECM_NIN4_ADDR_TO_IP_ADDR(ip_addr, r->inner.dst_ipv4_addr);
+		ecm_db_host_connections_defunct_by_dir(ip_addr, ECM_DB_OBJ_DIR_FROM);
+		ecm_db_host_connections_defunct_by_dir(ip_addr, ECM_DB_OBJ_DIR_TO);
+		return;
+	}
+
+	if (valid_flag & SP_RULE_FLAG_MATCH_SRC_IPV6) {
+		memcpy(ipv6addr.s6_addr32, r->inner.src_ipv6_addr, 4);
+		ECM_NIN6_ADDR_TO_IP_ADDR(ip_addr, ipv6addr);
+		ecm_db_host_connections_defunct_by_dir(ip_addr, ECM_DB_OBJ_DIR_FROM);
+		ecm_db_host_connections_defunct_by_dir(ip_addr, ECM_DB_OBJ_DIR_TO);
+		return;
+	}
+
+	if (valid_flag & SP_RULE_FLAG_MATCH_DST_IPV6) {
+		memcpy(ipv6addr.s6_addr32, r->inner.dst_ipv6_addr, 4);
+		ECM_NIN6_ADDR_TO_IP_ADDR(ip_addr, ipv6addr);
+		ecm_db_host_connections_defunct_by_dir(ip_addr, ECM_DB_OBJ_DIR_FROM);
+		ecm_db_host_connections_defunct_by_dir(ip_addr, ECM_DB_OBJ_DIR_TO);
+		return;
+	}
+
+	if (valid_flag & SP_RULE_FLAG_MATCH_SOURCE_MAC) {
+		ecm_interface_node_connections_defunct((uint8_t *)r->inner.sa, ECM_DB_IP_VERSION_IGNORE);
+		return;
+	}
+
+	if (valid_flag & SP_RULE_FLAG_MATCH_DST_MAC) {
+		ecm_interface_node_connections_defunct((uint8_t *)r->inner.da, ECM_DB_IP_VERSION_IGNORE);
+		return;
+	}
+
+	if (valid_flag & SP_RULE_FLAG_MATCH_PROTOCOL) {
+		ecm_db_connection_defunct_by_protocol(r->inner.protocol_number);
+		return;
+	}
+
+	/*
+	 * Destroy all the connections that are currently assigned to Emesh classifier
+	 * The usage of the incoming parameters in this service prioritization
+	 * callback will be done in future to perform more refined flush of
+	 * connections.
+	 */
+	ecm_db_connection_make_defunct_by_assignment_type(ECM_CLASSIFIER_TYPE_EMESH);
+}
+
+/*
+ * ecm_classifier_emesh_latency_config_callback_register()
+ */
+int ecm_classifier_emesh_latency_config_callback_register(struct ecm_classifier_emesh_callbacks *emesh_cb)
+{
+	spin_lock_bh(&ecm_classifier_emesh_lock);
+	if (ecm_emesh.update_peer_mesh_latency_params) {
+		spin_unlock_bh(&ecm_classifier_emesh_lock);
+		DEBUG_ERROR("EMESH latency config callbacks are registered\n");
+		return -1;
+	}
+
+	ecm_emesh.update_peer_mesh_latency_params = emesh_cb->update_peer_mesh_latency_params;
+	spin_unlock_bh(&ecm_classifier_emesh_lock);
+	return 0;
+}
+EXPORT_SYMBOL(ecm_classifier_emesh_latency_config_callback_register);
+
+/*
+ * ecm_classifier_emesh_latency_config_callback_unregister()
+ */
+void ecm_classifier_emesh_latency_config_callback_unregister(void)
+{
+	spin_lock_bh(&ecm_classifier_emesh_lock);
+	ecm_emesh.update_peer_mesh_latency_params = NULL;
+	spin_unlock_bh(&ecm_classifier_emesh_lock);
+}
+EXPORT_SYMBOL(ecm_classifier_emesh_latency_config_callback_unregister);
+
+/*
+ * ecm_classifier_emesh_init()
+ */
+int ecm_classifier_emesh_init(struct dentry *dentry)
+{
+	int ret;
+
+	DEBUG_INFO("EMESH classifier Module init\n");
+
+	ecm_classifier_emesh_dentry = debugfs_create_dir("ecm_classifier_emesh", dentry);
+	if (!ecm_classifier_emesh_dentry) {
+		DEBUG_ERROR("Failed to create ecm emesh directory in debugfs\n");
+		return -1;
+	}
+
+	if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry,
+				(u32 *)&ecm_classifier_emesh_enabled)) {
+		DEBUG_ERROR("Failed to create ecm emesh classifier enabled file in debugfs\n");
+		debugfs_remove_recursive(ecm_classifier_emesh_dentry);
+		return -1;
+	}
+
+	if (!debugfs_create_u32("latency_config_enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry,
+				(u32 *)&ecm_classifier_emesh_latency_config_enabled)) {
+		DEBUG_ERROR("Failed to create ecm emesh classifier latency config enabled file in debugfs\n");
+		debugfs_remove_recursive(ecm_classifier_emesh_dentry);
+		return -1;
+	}
+
+	/*
+	 * Register for service prioritization notification update.
+	 */
+	ret = sp_mapdb_rule_update_register_notify(ecm_classifier_emesh_rule_update_cb);
+	if (ret) {
+		DEBUG_ERROR("SP update registration failed: %d\n", ret);
+		debugfs_remove_recursive(ecm_classifier_emesh_dentry);
+		return -1;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_classifier_emesh_init);
+
+/*
+ * ecm_classifier_emesh_exit()
+ */
+void ecm_classifier_emesh_exit(void)
+{
+	DEBUG_INFO("Emesh classifier Module exit\n");
+
+	spin_lock_bh(&ecm_classifier_emesh_lock);
+	ecm_classifier_emesh_terminate_pending = true;
+	spin_unlock_bh(&ecm_classifier_emesh_lock);
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_classifier_emesh_dentry) {
+		debugfs_remove_recursive(ecm_classifier_emesh_dentry);
+	}
+
+	/*
+	 * De-register service prioritization notification update.
+	 */
+	sp_mapdb_rule_update_unregister_notify();
+}
+EXPORT_SYMBOL(ecm_classifier_emesh_exit);
diff --git a/qca-nss-ecm/ecm_classifier_emesh.h b/qca-nss-ecm/ecm_classifier_emesh.h
new file mode 100644
index 0000000..8aff5dd
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_emesh.h
@@ -0,0 +1,20 @@
+/*
+ ***************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ ***************************************************************************
+ */
+
+struct ecm_classifier_emesh_instance;
+struct ecm_classifier_emesh_instance *ecm_classifier_emesh_instance_alloc(struct ecm_db_connection_instance *ci);
diff --git a/qca-nss-ecm/ecm_classifier_hyfi.c b/qca-nss-ecm/ecm_classifier_hyfi.c
new file mode 100644
index 0000000..a57a13e
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_hyfi.c
@@ -0,0 +1,1179 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2016, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+#include <hyfi_ecm.h>
+#include <hyfi_hash.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_CLASSIFIER_HYFI_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_hyfi.h"
+#include "ecm_front_end_ipv4.h"
+#include "ecm_interface.h"
+/*
+ * Magic numbers
+ */
+#define ECM_CLASSIFIER_HYFI_INSTANCE_MAGIC 0xFE25
+
+/*
+ * Definitions
+ */
+#define ECM_CLASSIFIER_HYFI_STATE_INIT              ( 1 << 0 )
+#define ECM_CLASSIFIER_HYFI_STATE_REGISTERED	    ( 1 << 1 )
+#define ECM_CLASSIFIER_HYFI_STATE_IGNORE            ( 1 << 2 )
+
+/*
+ * struct ecm_classifier_hyfi_instance
+ * 	State to allow tracking of dynamic qos for a connection
+ */
+struct ecm_classifier_hyfi_instance {
+	struct ecm_classifier_instance base;			/* Base type */
+
+	struct ecm_classifier_hyfi_instance *next;		/* Next classifier state instance (for accouting and reporting purposes) */
+	struct ecm_classifier_hyfi_instance *prev;		/* Next classifier state instance (for accouting and reporting purposes) */
+
+	uint32_t ci_serial;					/* RO: Serial of the connection */
+	struct ecm_classifier_process_response process_response;/* Last process response computed */
+
+	uint32_t hyfi_state;
+	struct hyfi_ecm_flow_data_t flow;
+
+	int refs;						/* Integer to trap we never go negative */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+	bool multi_bridge_flow;
+	char bridge_name[IFNAMSIZ]; /* Destination bridge device of this hyfi instance */
+};
+
+/*
+ * Listener for db events
+ */
+struct ecm_db_listener_instance *ecm_classifier_hyfi_li = NULL;
+
+/*
+ * Operational control - defaults to false (disabled)
+ */
+static int ecm_classifier_hyfi_enabled;		/* Operational behaviour */
+
+/*
+ * Management thread control
+ */
+static bool ecm_classifier_hyfi_terminate_pending = false;		/* True when the user wants us to terminate */
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_classifier_hyfi_dentry;
+
+/*
+ * Locking of the classifier structures
+ */
+static DEFINE_SPINLOCK(ecm_classifier_hyfi_lock);			/* Protect SMP access. */
+
+/*
+ * List of our classifier instances
+ */
+static struct ecm_classifier_hyfi_instance *ecm_classifier_hyfi_instances = NULL;
+									/* list of all active instances */
+static int ecm_classifier_hyfi_count = 0;					/* Tracks number of instances allocated */
+
+/*
+ * ecm_classifier_hyfi_ref()
+ *	Ref
+ */
+static void ecm_classifier_hyfi_ref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_hyfi_instance *chfi;
+	chfi = (struct ecm_classifier_hyfi_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(chfi, ECM_CLASSIFIER_HYFI_INSTANCE_MAGIC, "%px: magic failed\n", chfi);
+	spin_lock_bh(&ecm_classifier_hyfi_lock);
+	chfi->refs++;
+	DEBUG_TRACE("%px: chfi ref %d\n", chfi, chfi->refs);
+	DEBUG_ASSERT(chfi->refs > 0, "%px: ref wrap\n", chfi);
+	spin_unlock_bh(&ecm_classifier_hyfi_lock);
+}
+
+/*
+ * ecm_classifier_hyfi_deref()
+ *	Deref
+ */
+static int ecm_classifier_hyfi_deref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_hyfi_instance *chfi;
+	chfi = (struct ecm_classifier_hyfi_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(chfi, ECM_CLASSIFIER_HYFI_INSTANCE_MAGIC, "%px: magic failed\n", chfi);
+	spin_lock_bh(&ecm_classifier_hyfi_lock);
+	chfi->refs--;
+	DEBUG_ASSERT(chfi->refs >= 0, "%px: refs wrapped\n", chfi);
+	DEBUG_TRACE("%px: HyFi classifier deref %d\n", chfi, chfi->refs);
+	if (chfi->refs) {
+		int refs = chfi->refs;
+		spin_unlock_bh(&ecm_classifier_hyfi_lock);
+		return refs;
+	}
+
+	/*
+	 * Object to be destroyed
+	 */
+	ecm_classifier_hyfi_count--;
+	DEBUG_ASSERT(ecm_classifier_hyfi_count >= 0, "%px: ecm_classifier_hyfi_count wrap\n", chfi);
+
+	/*
+	 * UnLink the instance from our list
+	 */
+	if (chfi->next) {
+		chfi->next->prev = chfi->prev;
+	}
+	if (chfi->prev) {
+		chfi->prev->next = chfi->next;
+	} else {
+		DEBUG_ASSERT(ecm_classifier_hyfi_instances == chfi, "%px: list bad %px\n", chfi, ecm_classifier_hyfi_instances);
+		ecm_classifier_hyfi_instances = chfi->next;
+	}
+	chfi->next = NULL;
+	chfi->prev = NULL;
+
+	spin_unlock_bh(&ecm_classifier_hyfi_lock);
+
+	/*
+	 * Final
+	 */
+	DEBUG_INFO("%px: Final HyFi classifier instance\n", chfi);
+	kfree(chfi);
+
+	return 0;
+}
+
+/*
+ * ecm_classifier_hyfi_process()
+ *	Process new data for connection
+ */
+static void ecm_classifier_hyfi_process(struct ecm_classifier_instance *aci, ecm_tracker_sender_type_t sender,
+						struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb,
+						struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_hyfi_instance *chfi;
+	ecm_classifier_relevence_t relevance;
+	bool enabled;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	ecm_front_end_acceleration_mode_t accel_mode;
+	uint32_t became_relevant = 0;
+	uint32_t flag = 0;
+
+	chfi = (struct ecm_classifier_hyfi_instance *)aci;
+	DEBUG_CHECK_MAGIC(chfi, ECM_CLASSIFIER_HYFI_INSTANCE_MAGIC, "%px: magic failed\n", chfi);
+
+	/*
+	 * Are we yet to decide if this instance is relevant to the connection?
+	 */
+	spin_lock_bh(&ecm_classifier_hyfi_lock);
+	relevance = chfi->process_response.relevance;
+	if (relevance != ECM_CLASSIFIER_RELEVANCE_MAYBE) {
+		/*
+		 * We already know
+		 * NOTE: Lock still held
+		 */
+		goto hyfi_classifier_out;
+	}
+
+	enabled = ecm_classifier_hyfi_enabled;
+	spin_unlock_bh(&ecm_classifier_hyfi_lock);
+
+	/*
+	 * Need to decide our relevance to this connection.
+	 * If classifier is enabled and the front end says it can accel then we are "relevant".
+	 * Any other condition and we are not and will stop analysing this connection.
+	 */
+	relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+	ci = ecm_db_connection_serial_find_and_ref(chfi->ci_serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: No ci found for %u\n", chfi, chfi->ci_serial);
+		accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED;
+	} else {
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+		accel_mode = feci->accel_state_get(feci);
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+	}
+
+	if (enabled && ECM_FRONT_END_ACCELERATION_POSSIBLE(accel_mode) &&
+		hyfi_ecm_bridge_attached(chfi->bridge_name)) {
+		relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+		became_relevant = ecm_db_time_get();
+	}
+
+	spin_lock_bh(&ecm_classifier_hyfi_lock);
+	chfi->process_response.relevance = relevance;
+	chfi->process_response.became_relevant = became_relevant;
+
+hyfi_classifier_out:
+	;
+
+	/*
+	 * Return our process response
+	 */
+	*process_response = chfi->process_response;
+	if (relevance == ECM_CLASSIFIER_RELEVANCE_NO) {
+		goto hyfi_classifier_done;
+	}
+
+	/*
+	 * Fast path, already accelerated or ignored
+	 */
+	if (chfi->hyfi_state & (ECM_CLASSIFIER_HYFI_STATE_REGISTERED | ECM_CLASSIFIER_HYFI_STATE_IGNORE)) {
+		if (chfi->hyfi_state & ECM_CLASSIFIER_HYFI_STATE_REGISTERED) {
+			DEBUG_INFO("%px: Regen of Flow serial: %d Flow hash: 0x%02x (@%lu)\n",
+				aci, chfi->flow.ecm_serial, chfi->flow.hash, jiffies);
+		}
+		goto hyfi_classifier_done;
+	}
+
+	/*
+	 * Compute the hashes in both forward and reverse directions
+	 */
+	if (unlikely(hyfi_hash_skbuf(skb, &chfi->flow.hash, &flag,
+		&chfi->flow.priority, &chfi->flow.seq)))
+		goto hyfi_classifier_done;
+
+	if (unlikely(hyfi_hash_skbuf_reverse(skb, &chfi->flow.reverse_hash)))
+		goto hyfi_classifier_done;
+
+	chfi->flow.ecm_serial = chfi->ci_serial;
+	if (flag & ECM_HYFI_IS_IPPROTO_UDP)
+		hyfi_ecm_set_flag(&chfi->flow, ECM_HYFI_IS_IPPROTO_UDP);
+	else
+		hyfi_ecm_clear_flag(&chfi->flow, ECM_HYFI_IS_IPPROTO_UDP);
+
+	memcpy(&chfi->flow.sa, eth_hdr(skb)->h_source, ETH_ALEN);
+	memcpy(&chfi->flow.da, eth_hdr(skb)->h_dest, ETH_ALEN);
+
+	DEBUG_INFO("%px: Flow serial: %d\nFlow hash: 0x%02x, priority 0x%08x, "
+			"flag: %d\nSA: %pM\nDA: %pM (@%lu)\n\n",
+			aci, chfi->flow.ecm_serial, chfi->flow.hash,
+			chfi->flow.priority, chfi->flow.flag,
+			chfi->flow.sa, chfi->flow.da, jiffies);
+
+	chfi->hyfi_state = ECM_CLASSIFIER_HYFI_STATE_REGISTERED;
+
+hyfi_classifier_done:
+	;
+
+	spin_unlock_bh(&ecm_classifier_hyfi_lock);
+}
+
+/*
+ * ecm_classifier_hyfi_get_intf_id()
+ *	Get the interface ID from the level of the
+ *	connection hierarchy that matches the interface selected by HyFi.
+ *
+ * If the hierarchy contains a bridge, the correct interface will be in the level
+ * of the hierarchy after the bridge.
+ * If the hierarchy doesn't contain a bridge, look for an interface that has its
+ * master set to the HyFi bridge.
+ *
+ * If neither of these conditions hold, this hierarchy can't be relevant to HyFi,
+ * and return -1.
+ */
+static int32_t ecm_classifier_hyfi_get_intf_id(struct ecm_db_connection_instance *ci,
+	ecm_db_obj_dir_t dir)
+{
+	int32_t intf_first;
+	int32_t system_index = -1;
+	struct ecm_db_iface_instance *interfaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	int32_t i;
+	char name[IFNAMSIZ];
+
+	intf_first = ecm_db_connection_interfaces_get_and_ref(ci, interfaces, dir);
+
+	if (intf_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Error fetching interfaces\n", ci);
+		return -1;
+	}
+
+	/*
+	 * Search from innermost to outermost interface
+	 */
+	for (i = ECM_DB_IFACE_HEIRARCHY_MAX - 1; i >= intf_first; i--) {
+		int32_t index;
+		if (ecm_db_iface_type_get(interfaces[i]) == ECM_DB_IFACE_TYPE_BRIDGE) {
+			/*
+			 * Found the bridge - next interface should be the one we want
+			 */
+			if (i <= intf_first) {
+				DEBUG_WARN("%px: Found bridge at position %d, but first interface "
+					"is %d, can't fetch HyFi relevant interface\n", ci,
+					i, intf_first);
+				break;
+			}
+
+			index = ecm_db_iface_interface_identifier_get(interfaces[i-1]);
+
+			if (!hyfi_ecm_is_port_on_hyfi_bridge(index)) {
+				DEBUG_TRACE("%px: Found non-Hy-Fi bridge, ignoring\n", ci);
+				break;
+			}
+
+			ecm_db_iface_interface_name_get(interfaces[i-1], &name[0]);
+			DEBUG_TRACE("%px: Found bridge: '%s' interface is %d (%s)\n", ci,
+				ecm_db_obj_dir_strings[dir], index, name);
+			system_index = index;
+			break;
+		}
+
+		/*
+		 * Bridge not found yet - check if this interface belongs to the bridge
+		 */
+		index = ecm_db_iface_interface_identifier_get(interfaces[i]);
+		if (hyfi_ecm_is_port_on_hyfi_bridge(index)) {
+			ecm_db_iface_interface_name_get(interfaces[i], &name[0]);
+			DEBUG_TRACE("%px: Found bridge port: '%s' interface is %d (%s)\n", ci,
+				ecm_db_obj_dir_strings[dir], index,
+				name);
+			system_index = index;
+			break;
+		}
+
+		/*
+		 * Match not found - keep searching
+		 */
+	}
+
+	ecm_db_connection_interfaces_deref(interfaces, intf_first);
+
+	return system_index;
+}
+
+/* ecm_classifier_hyfi_get_bridge_name()
+ *	Get the bridge name from the connection hierarchy
+ */
+static void ecm_classifier_hyfi_get_bridge_name(struct ecm_db_connection_instance *ci,
+		char *name_buffer, ecm_db_obj_dir_t dir)
+{
+	int32_t intf_first;
+	struct ecm_db_iface_instance *interfaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	int32_t i;
+
+	intf_first = ecm_db_connection_interfaces_get_and_ref(ci, interfaces, dir);
+
+	if (intf_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Error fetching bridge name\n", ci);
+		return;
+	}
+
+	for (i = intf_first; i < ECM_DB_IFACE_HEIRARCHY_MAX; i++) {
+		struct net_device *dev;
+		dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(interfaces[i]));
+
+		if (dev && ecm_front_end_is_bridge_port(dev)) {
+			struct net_device *master;
+			master = ecm_interface_get_and_hold_dev_master(dev);
+			if (master) {
+				strlcpy(name_buffer, master->name, IFNAMSIZ);
+				dev_put(master);
+				dev_put(dev);
+				break;
+			}
+		}
+		if (dev)
+			dev_put(dev);
+	}
+
+	ecm_db_connection_interfaces_deref(interfaces, intf_first);
+}
+
+/*
+ * ecm_classifier_hyfi_sync_to_v4()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_hyfi_sync_to_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	struct ecm_classifier_hyfi_instance *chfi;
+	struct ecm_db_connection_instance *ci;
+	uint64_t from_packets = 0;
+	uint64_t from_bytes = 0;
+	uint64_t to_packets = 0;
+	uint64_t to_bytes = 0;
+	uint64_t from_packets_dropped = 0;
+	uint64_t from_bytes_dropped = 0;
+	uint64_t to_packets_dropped = 0;
+	uint64_t to_bytes_dropped = 0;
+	int32_t ret_fwd, ret_rev;
+	uint32_t time_now;
+	uint32_t time_elapsed_fwd = 0;
+	uint32_t time_elapsed_rev = 0;
+	uint8_t flow_dest_addr[ETH_ALEN];
+	uint64_t fwd_bytes, rev_bytes, fwd_packets, rev_packets;
+	bool should_keep_on_fdb_update_fwd = false;
+	bool should_keep_on_fdb_update_rev = false;
+	int32_t to_system_index;
+	int32_t from_system_index;
+
+	if (sync->reason != ECM_FRONT_END_IPV4_RULE_SYNC_REASON_STATS) {
+		DEBUG_TRACE("%px: Update not due to stats: %d\n",
+			aci, sync->reason);
+		return;
+	}
+
+	chfi = (struct ecm_classifier_hyfi_instance *)aci;
+	DEBUG_CHECK_MAGIC(chfi, ECM_CLASSIFIER_HYFI_INSTANCE_MAGIC, "%px: magic failed", chfi);
+
+	if (chfi->hyfi_state &
+			(ECM_CLASSIFIER_HYFI_STATE_IGNORE)) {
+		return;
+	}
+
+	ci = ecm_db_connection_serial_find_and_ref(chfi->ci_serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: No ci found for %u\n", chfi, chfi->ci_serial);
+		return;
+	}
+
+	/*
+	 * Update the stats on Hy-Fi side
+	 */
+	to_system_index = ecm_classifier_hyfi_get_intf_id(ci, ECM_DB_OBJ_DIR_TO);
+	from_system_index = ecm_classifier_hyfi_get_intf_id(ci, ECM_DB_OBJ_DIR_FROM);
+
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, &flow_dest_addr[0]);
+	ecm_db_connection_data_stats_get(ci, &from_bytes, &to_bytes,
+			&from_packets, &to_packets,
+			&from_bytes_dropped, &to_bytes_dropped,
+			&from_packets_dropped, &to_packets_dropped);
+
+	DEBUG_INFO("UPDATE STATS: Flow serial: %d\npriority 0x%08x, flag: %d\nSA: %pM\nDA: %pM\n\n",
+			chfi->flow.ecm_serial, chfi->flow.priority, chfi->flow.flag,
+			chfi->flow.sa, chfi->flow.da);
+
+	time_now = jiffies;
+	/*
+	 * Make sure destination address still matches
+	 */
+	if (memcmp(&flow_dest_addr[0], &chfi->flow.da[0], ETH_ALEN)) {
+		DEBUG_INFO("UPDATE STATS: Direction of flow is "
+			"reverse of expectation\n");
+		fwd_bytes = (to_bytes - to_bytes_dropped);
+		fwd_packets = (to_packets - to_packets_dropped);
+		rev_bytes = (from_bytes - from_bytes_dropped);
+		rev_packets = (from_packets - from_packets_dropped);
+	} else {
+		fwd_bytes = (from_bytes - from_bytes_dropped);
+		fwd_packets = (from_packets - from_packets_dropped);
+		rev_bytes = (to_bytes - to_bytes_dropped);
+		rev_packets = (to_packets - to_packets_dropped);
+	}
+
+	/*
+	 * Update forward direction 'from' bytes
+	 */
+	ret_fwd = hyfi_ecm_update_stats(&chfi->flow, chfi->flow.hash,
+		&chfi->flow.da[0], &chfi->flow.sa[0],
+		fwd_bytes, fwd_packets, time_now,
+		&should_keep_on_fdb_update_fwd,
+		&time_elapsed_fwd, chfi->bridge_name);
+	DEBUG_INFO("ret_fwd %d Forward hash: 0x%02x, from_bytes = %lld, from_packets = %lld, "
+		"num_bytes_dropped = %lld, num_packets_dropped = %lld\n",
+		ret_fwd, chfi->flow.hash, from_bytes, from_packets,
+		from_bytes_dropped, from_packets_dropped);
+
+	/*
+	 * Update reverse direction 'to' bytes
+	 */
+	ret_rev = hyfi_ecm_update_stats(&chfi->flow, chfi->flow.reverse_hash,
+		&chfi->flow.sa[0], &chfi->flow.da[0],
+		rev_bytes, rev_packets, time_now,
+		&should_keep_on_fdb_update_rev,
+		&time_elapsed_rev, chfi->bridge_name);
+
+	DEBUG_INFO("ret_rev %d Reverse hash: 0x%02x, to_bytes = %lld, to_packets = %lld, "
+		"num_bytes_dropped = %lld, num_packets_dropped = %lld\n",
+		ret_rev, chfi->flow.reverse_hash, to_bytes, to_packets,
+		to_bytes_dropped, to_packets_dropped);
+
+	chfi->flow.last_update = time_now;
+	chfi->flow.last_elapsed_time = time_elapsed_fwd >= time_elapsed_rev ?
+		time_elapsed_fwd : time_elapsed_rev;
+
+	if (!time_elapsed_fwd) {
+		if (should_keep_on_fdb_update_fwd) {
+			hyfi_ecm_set_flag(&chfi->flow,
+				ECM_HYFI_SHOULD_KEEP_ON_FDB_UPDATE_FWD);
+		} else {
+			hyfi_ecm_clear_flag(&chfi->flow,
+				ECM_HYFI_SHOULD_KEEP_ON_FDB_UPDATE_FWD);
+		}
+	}
+
+	if (!time_elapsed_rev) {
+		if (should_keep_on_fdb_update_rev) {
+			hyfi_ecm_set_flag(&chfi->flow,
+				ECM_HYFI_SHOULD_KEEP_ON_FDB_UPDATE_REV);
+		} else {
+			hyfi_ecm_clear_flag(&chfi->flow,
+				ECM_HYFI_SHOULD_KEEP_ON_FDB_UPDATE_REV);
+		}
+	}
+
+	if (!hyfi_ecm_port_matches(&chfi->flow, to_system_index,
+			 from_system_index, chfi->bridge_name)) {
+		struct ecm_front_end_connection_instance *feci;
+		unsigned long start_time, end_time;
+
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+		start_time = feci->stats.cmd_time_begun;
+		end_time = feci->stats.cmd_time_completed;
+		if (chfi->flow.cmd_time_begun != start_time &&
+			chfi->flow.cmd_time_completed != end_time) {
+
+			/*
+			 * Only do another regenerate operation if the timestamps have
+			 * changed (indicating that the front-end has completed the
+			 * previously requested operation)
+			 */
+			feci->regenerate(feci, ci);
+			DEBUG_INFO("%px: Mismatch for %u egress port between HyFi and "
+				"ECM,\nregenerate start %lu, end %lu, "
+				"previous start %lu, end %lu (@%u)\n",
+				ci, chfi->flow.ecm_serial, start_time, end_time,
+				chfi->flow.cmd_time_begun, chfi->flow.cmd_time_completed,
+				time_now);
+			chfi->flow.cmd_time_begun = start_time;
+			chfi->flow.cmd_time_completed = end_time;
+		} else {
+			DEBUG_INFO("%px: Mismatch for %u egress port between HyFi and "
+				"ECM,\nbut previous regeneration in progress start "
+				" %lu, end %lu (@%u)\n",
+				ci, chfi->flow.ecm_serial, start_time, end_time, time_now);
+		}
+		feci->deref(feci);
+	}
+
+	ecm_db_connection_deref(ci);
+
+	if (ret_fwd < 0 || ret_rev < 0) {
+		DEBUG_ERROR_RATELIMITED("%px: Error updating stats", aci);
+		return;
+	}
+
+	/*
+	 * Only need to be interested in forward or reverse direction
+	 */
+	if (ret_fwd == 0 || ret_rev == 0) {
+		chfi->hyfi_state = ECM_CLASSIFIER_HYFI_STATE_REGISTERED;
+	} else if (ret_fwd == 2 || ret_rev == 2) {
+		/*
+		 * Not attached, may be interested in the future
+		 */
+		chfi->hyfi_state = ECM_CLASSIFIER_HYFI_STATE_INIT;
+	} else {
+		/*
+		 * Not interested
+		 */
+		chfi->hyfi_state = ECM_CLASSIFIER_HYFI_STATE_IGNORE;
+	}
+}
+
+/*
+ * ecm_classifier_hyfi_sync_from_v4()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_hyfi_sync_from_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_hyfi_instance *chfi;
+
+	chfi = (struct ecm_classifier_hyfi_instance *)aci;
+	DEBUG_CHECK_MAGIC(chfi, ECM_CLASSIFIER_HYFI_INSTANCE_MAGIC, "%px: magic failed", chfi);
+}
+
+/*
+ * ecm_classifier_hyfi_sync_to_v6()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_hyfi_sync_to_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	/* Same processing as v4 */
+	ecm_classifier_hyfi_sync_to_v4(aci, sync);
+}
+
+/*
+ * ecm_classifier_hyfi_sync_from_v6()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_hyfi_sync_from_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_hyfi_instance *chfi;
+
+	chfi = (struct ecm_classifier_hyfi_instance *)aci;
+	DEBUG_CHECK_MAGIC(chfi, ECM_CLASSIFIER_HYFI_INSTANCE_MAGIC, "%px: magic failed", chfi);
+
+}
+
+/*
+ * ecm_classifier_hyfi_type_get()
+ *	Get type of classifier this is
+ */
+static ecm_classifier_type_t ecm_classifier_hyfi_type_get(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_hyfi_instance *chfi;
+	chfi = (struct ecm_classifier_hyfi_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(chfi, ECM_CLASSIFIER_HYFI_INSTANCE_MAGIC, "%px: magic failed\n", chfi);
+	return ECM_CLASSIFIER_TYPE_HYFI;
+}
+
+/*
+ * ecm_classifier_hyfi_last_process_response_get()
+ *	Get result code returned by the last process call
+ */
+static void ecm_classifier_hyfi_last_process_response_get(struct ecm_classifier_instance *ci,
+							struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_hyfi_instance *chfi;
+
+	chfi = (struct ecm_classifier_hyfi_instance *)ci;
+	DEBUG_CHECK_MAGIC(chfi, ECM_CLASSIFIER_HYFI_INSTANCE_MAGIC, "%px: magic failed\n", chfi);
+
+	spin_lock_bh(&ecm_classifier_hyfi_lock);
+	*process_response = chfi->process_response;
+	spin_unlock_bh(&ecm_classifier_hyfi_lock);
+}
+
+/*
+ * ecm_classifier_hyfi_reclassify_allowed()
+ *	Indicate if reclassify is allowed
+ */
+static bool ecm_classifier_hyfi_reclassify_allowed(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_hyfi_instance *chfi;
+	chfi = (struct ecm_classifier_hyfi_instance *)ci;
+	DEBUG_CHECK_MAGIC(chfi, ECM_CLASSIFIER_HYFI_INSTANCE_MAGIC, "%px: magic failed\n", chfi);
+
+	return true;
+}
+
+/*
+ * ecm_classifier_hyfi_reclassify()
+ *	Reclassify
+ */
+static void ecm_classifier_hyfi_reclassify(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_hyfi_instance *chfi;
+	chfi = (struct ecm_classifier_hyfi_instance *)ci;
+	DEBUG_CHECK_MAGIC(chfi, ECM_CLASSIFIER_HYFI_INSTANCE_MAGIC, "%px: magic failed\n", chfi);
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_classifier_hyfi_state_get()
+ *	Return state
+ */
+static int ecm_classifier_hyfi_state_get(struct ecm_classifier_instance *ci, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	struct ecm_classifier_hyfi_instance *chfi;
+	struct ecm_classifier_process_response process_response;
+
+	chfi = (struct ecm_classifier_hyfi_instance *)ci;
+	DEBUG_CHECK_MAGIC(chfi, ECM_CLASSIFIER_HYFI_INSTANCE_MAGIC, "%px: magic failed", chfi);
+
+	if ((result = ecm_state_prefix_add(sfi, "hyfi"))) {
+		return result;
+	}
+
+	spin_lock_bh(&ecm_classifier_hyfi_lock);
+	process_response = chfi->process_response;
+	spin_unlock_bh(&ecm_classifier_hyfi_lock);
+
+	/*
+	 * Output our last process response
+	 */
+	if ((result = ecm_classifier_process_response_state_get(sfi, &process_response))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+static bool ecm_classifier_hyfi_should_keep_connection(
+	struct ecm_classifier_instance *aci, uint8_t *mac)
+{
+	struct ecm_classifier_hyfi_instance *chfi;
+
+	chfi = (struct ecm_classifier_hyfi_instance *)aci;
+	DEBUG_CHECK_MAGIC(chfi, ECM_CLASSIFIER_HYFI_INSTANCE_MAGIC,
+		"%px: magic failed", chfi);
+
+	if (chfi->hyfi_state &
+			(ECM_CLASSIFIER_HYFI_STATE_IGNORE)) {
+		/* HyFi doesn't care if connection deleted */
+		return false;
+	}
+
+	return hyfi_ecm_should_keep(&chfi->flow, mac, chfi->bridge_name);
+}
+
+/*
+ * ecm_classifier_hyfi_instance_alloc()
+ *	Allocate an instance of the HyFi classifier
+ */
+struct ecm_classifier_hyfi_instance *ecm_classifier_hyfi_instance_alloc(struct ecm_db_connection_instance *ci)
+{
+	struct ecm_classifier_hyfi_instance *chfi;
+	char to_bridge[IFNAMSIZ];
+	char from_bridge[IFNAMSIZ];
+
+	/*
+	 * Allocate the instance
+	 */
+	chfi = (struct ecm_classifier_hyfi_instance *)kzalloc(sizeof(struct ecm_classifier_hyfi_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!chfi) {
+		DEBUG_WARN("Failed to allocate HyFi instance\n");
+		return NULL;
+	}
+
+	DEBUG_SET_MAGIC(chfi, ECM_CLASSIFIER_HYFI_INSTANCE_MAGIC);
+	chfi->refs = 1;
+	chfi->base.process = ecm_classifier_hyfi_process;
+	chfi->base.sync_from_v4 = ecm_classifier_hyfi_sync_from_v4;
+	chfi->base.sync_to_v4 = ecm_classifier_hyfi_sync_to_v4;
+	chfi->base.sync_from_v6 = ecm_classifier_hyfi_sync_from_v6;
+	chfi->base.sync_to_v6 = ecm_classifier_hyfi_sync_to_v6;
+	chfi->base.type_get = ecm_classifier_hyfi_type_get;
+	chfi->base.last_process_response_get = ecm_classifier_hyfi_last_process_response_get;
+	chfi->base.reclassify_allowed = ecm_classifier_hyfi_reclassify_allowed;
+	chfi->base.reclassify = ecm_classifier_hyfi_reclassify;
+	chfi->base.should_keep_connection =
+		ecm_classifier_hyfi_should_keep_connection;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	chfi->base.state_get = ecm_classifier_hyfi_state_get;
+#endif
+	chfi->base.ref = ecm_classifier_hyfi_ref;
+	chfi->base.deref = ecm_classifier_hyfi_deref;
+	chfi->ci_serial = ecm_db_connection_serial_get(ci);
+	chfi->process_response.process_actions = 0;
+	chfi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_MAYBE;
+
+	/*
+	 * Find and save the bridge name. This will be passed to hyfi module later
+	 */
+	to_bridge[0] = 0;
+	from_bridge[0] = 0;
+	ecm_classifier_hyfi_get_bridge_name(ci, to_bridge, ECM_DB_OBJ_DIR_TO);
+	ecm_classifier_hyfi_get_bridge_name(ci, from_bridge, ECM_DB_OBJ_DIR_FROM);
+
+	if (!strlen(to_bridge) || !strlen(from_bridge)) {
+		/* one of the bridge name is null, typical
+		 * routed connection. Consider valid bridge*/
+		if (strlen(to_bridge)) {
+			strlcpy(chfi->bridge_name, to_bridge, IFNAMSIZ);
+		} else if (strlen(from_bridge)) {
+			strlcpy(chfi->bridge_name, from_bridge, IFNAMSIZ);
+		}
+	} else if (!strncmp(to_bridge, from_bridge, IFNAMSIZ)) {
+		/* Pure bridge connection. Consider any one bridge */
+		strlcpy(chfi->bridge_name, to_bridge, IFNAMSIZ);
+	} else {
+		/* multi-bridge connection */
+		chfi->multi_bridge_flow = true;
+
+		/* TODO: Currently we are not supporting
+		 * multi-bridge connection, stats wont be
+		 * updated for multi-bridge flow */
+	}
+
+	/*
+	 * Init Hy-Fi state
+	 */
+	chfi->hyfi_state = ECM_CLASSIFIER_HYFI_STATE_INIT;
+
+	spin_lock_bh(&ecm_classifier_hyfi_lock);
+
+	/*
+	 * Final check if we are pending termination
+	 */
+	if (ecm_classifier_hyfi_terminate_pending) {
+		spin_unlock_bh(&ecm_classifier_hyfi_lock);
+		DEBUG_INFO("%px: Terminating\n", ci);
+		kfree(chfi);
+		return NULL;
+	}
+
+	/*
+	 * Link the new instance into our list at the head
+	 */
+	chfi->next = ecm_classifier_hyfi_instances;
+	if (ecm_classifier_hyfi_instances) {
+		ecm_classifier_hyfi_instances->prev = chfi;
+	}
+	ecm_classifier_hyfi_instances = chfi;
+
+	/*
+	 * Increment stats
+	 */
+	ecm_classifier_hyfi_count++;
+	DEBUG_ASSERT(ecm_classifier_hyfi_count > 0, "%px: ecm_classifier_hyfi_count wrap\n", chfi);
+	spin_unlock_bh(&ecm_classifier_hyfi_lock);
+
+	DEBUG_INFO("HyFi instance alloc: %px\n", chfi);
+	return chfi;
+}
+EXPORT_SYMBOL(ecm_classifier_hyfi_instance_alloc);
+
+/*
+ * ecm_classifier_hyfi_connection_added()
+ *	Invoked when a connection is added to the DB
+ */
+static void ecm_classifier_hyfi_connection_added(void *arg, struct ecm_db_connection_instance *ci)
+{
+#if (DEBUG_LEVEL > 2)
+	uint32_t serial = ecm_db_connection_serial_get(ci);
+	DEBUG_INFO("%px: HYFI LISTENER: added conn with serial: %u\n", ci, serial);
+#endif
+}
+
+/*
+ * ecm_classifier_hyfi_connection_removed()
+ *	Invoked when a connection is removed from the DB
+ */
+static void ecm_classifier_hyfi_connection_removed(void *arg, struct ecm_db_connection_instance *ci)
+{
+	struct ecm_classifier_instance *aci;
+	struct ecm_classifier_hyfi_instance *chfi;
+	uint32_t serial = ecm_db_connection_serial_get(ci);
+
+	DEBUG_INFO("%px: HYFI LISTENER: removed conn with serial: %u\n", ci, serial);
+
+	/*
+	 * Only handle events if there is an HyFi classifier attached
+	 */
+	aci = ecm_db_connection_assigned_classifier_find_and_ref(ci, ECM_CLASSIFIER_TYPE_HYFI);
+	if (!aci) {
+		DEBUG_TRACE("%px: Connection removed ignored"
+			" - no HyFi classifier\n", ci);
+		return;
+	}
+
+	chfi = (struct ecm_classifier_hyfi_instance *)aci;
+	DEBUG_INFO("%px: removed conn with serial: %u, "
+		"hash 0x%x, rev hash 0x%x\n",
+		aci, serial, chfi->flow.hash, chfi->flow.reverse_hash);
+
+	/*
+	 * Mark as decelerated
+	 */
+	hyfi_ecm_decelerate(chfi->flow.hash, serial, &chfi->flow.da[0], chfi->bridge_name);
+	hyfi_ecm_decelerate(chfi->flow.reverse_hash, serial, &chfi->flow.sa[0], chfi->bridge_name);
+
+	aci->deref(aci);
+}
+
+/*
+ * ecm_classifier_hyfi_set_set_command()
+ *	Set hyfi command to accel/decel connection.
+ */
+static ssize_t ecm_classifier_hyfi_set_command(struct file *file,
+						const char __user *user_buf,
+						size_t sz, loff_t *ppos)
+{
+#define ECM_CLASSIFIER_HYFI_SET_IP_COMMAND_FIELDS 2
+	char *cmd_buf;
+	int field_count;
+	char *field_ptr;
+	char *fields[ECM_CLASSIFIER_HYFI_SET_IP_COMMAND_FIELDS];
+	char cmd;
+	uint32_t serial;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_classifier_hyfi_instance *chfi;
+	struct ecm_classifier_instance *classi;
+
+	/*
+	 * Check if we are enabled
+	 */
+	spin_lock_bh(&ecm_classifier_hyfi_lock);
+	if (!ecm_classifier_hyfi_enabled) {
+		spin_unlock_bh(&ecm_classifier_hyfi_lock);
+		return -EINVAL;
+	}
+	spin_unlock_bh(&ecm_classifier_hyfi_lock);
+
+	/*
+	 * buf is formed as:
+	 * [0]   [1]
+	 * <CMD>/<SERIAL>
+	 * CMD:
+	 *	s = Decelerate based on <SERIAL> number given.
+	 */
+	cmd_buf = (char *)kzalloc(sz + 1, GFP_ATOMIC);
+	if (!cmd_buf) {
+		return -ENOMEM;
+	}
+
+	sz = simple_write_to_buffer(cmd_buf, sz, ppos, user_buf, sz);
+
+	/*
+	 * Split the buffer into its fields
+	 */
+	field_count = 0;
+	field_ptr = cmd_buf;
+	fields[field_count] = strsep(&field_ptr, "/");
+	while (fields[field_count] != NULL) {
+		DEBUG_TRACE("FIELD %d: %s\n", field_count, fields[field_count]);
+		field_count++;
+		if (field_count == ECM_CLASSIFIER_HYFI_SET_IP_COMMAND_FIELDS) {
+			break;
+		}
+		fields[field_count] = strsep(&field_ptr, "/");
+	}
+
+	if (field_count != ECM_CLASSIFIER_HYFI_SET_IP_COMMAND_FIELDS) {
+		DEBUG_WARN("invalid field count %d\n", field_count);
+		kfree(cmd_buf);
+		return -EINVAL;
+	}
+
+	if (!sscanf(fields[0], "%c", &cmd)) {
+		DEBUG_WARN("invalid cmd\n");
+		kfree(cmd_buf);
+		return -EINVAL;
+	}
+	if (!sscanf(fields[1], "%u", &serial)) {
+		DEBUG_WARN("invalid serial\n");
+		kfree(cmd_buf);
+		return -EINVAL;
+	}
+
+	kfree(cmd_buf);
+
+	/*
+	 * Locate the connection using the serial or tuple given
+	 */
+	switch (cmd) {
+	case 's':
+		DEBUG_TRACE("Lookup connection using serial: %u\n", serial);
+		ci = ecm_db_connection_serial_find_and_ref(serial);
+		break;
+	default:
+		DEBUG_WARN("invalid cmd %c\n", cmd);
+		return -EINVAL;
+	}
+
+	if (!ci) {
+		DEBUG_WARN("database connection not found\n");
+		return -ENOMEM;
+	}
+	DEBUG_TRACE("Connection found: %px\n", ci);
+
+	/*
+	 * Get the Hy-Fi classifier instance
+	 */
+	classi = ecm_db_connection_assigned_classifier_find_and_ref(
+		ci, ECM_CLASSIFIER_TYPE_HYFI);
+
+	if (!classi) {
+		DEBUG_WARN("%px: No Hy-Fi classifier instance\n", ci);
+		ecm_db_connection_deref(ci);
+		return -ENOMEM;
+	}
+
+	chfi = (struct ecm_classifier_hyfi_instance *)classi;
+
+	/*
+	 * Now action the command
+	 */
+	switch (cmd) {
+	case 's':
+	case 'f':
+
+		/*
+		 * Regenerate the connection
+		 */
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+		/*
+		 * Store the begin / end timestamps here (from the previous
+		 * operation). Will not attempt another regen if
+		 * ports don't match until this regenerate is completed (which
+		 * can be detected by a change in the timestamps).
+		 */
+		chfi->flow.cmd_time_begun = feci->stats.cmd_time_begun;
+		chfi->flow.cmd_time_completed = feci->stats.cmd_time_completed;
+		feci->regenerate(feci, ci);
+		feci->deref(feci);
+
+		DEBUG_TRACE("%px: Force regeneration %u start_time %lu end_time"
+			" %lu (@%lu)\n", ci, serial,
+			chfi->flow.cmd_time_begun,
+			chfi->flow.cmd_time_completed, jiffies);
+		break;
+	}
+	classi->deref(classi);
+	ecm_db_connection_deref(ci);
+
+	return sz;
+}
+
+/*
+ * File operations for hyfi classifier command.
+ */
+static struct file_operations ecm_classifier_hyfi_cmd_fops = {
+	.write = ecm_classifier_hyfi_set_command,
+	.llseek = generic_file_llseek,
+	.owner = THIS_MODULE
+};
+
+/*
+ * ecm_classifier_hyfi_rules_init()
+ */
+int ecm_classifier_hyfi_rules_init(struct dentry *dentry)
+{
+	DEBUG_INFO("HyFi classifier Module init\n");
+
+	ecm_classifier_hyfi_dentry = debugfs_create_dir("ecm_classifier_hyfi", dentry);
+	if (!ecm_classifier_hyfi_dentry) {
+		DEBUG_ERROR("Failed to create ecm hyfi classifier directory in debugfs\n");
+		goto classifier_task_cleanup;
+	}
+
+	if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_hyfi_dentry,
+					(u32 *)&ecm_classifier_hyfi_enabled)) {
+		DEBUG_ERROR("Failed to create ecm hyfi classifier enabled file in debugfs\n");
+		goto classifier_task_cleanup;
+	}
+
+	if (!debugfs_create_file("cmd", S_IWUSR, ecm_classifier_hyfi_dentry,
+					NULL, &ecm_classifier_hyfi_cmd_fops)) {
+		DEBUG_ERROR("Failed to create ecm hyfi classifier cmd file in debugfs\n");
+		goto classifier_task_cleanup;
+	}
+
+	/*
+	 * Allocate listener instance to listen for db events
+	 */
+	ecm_classifier_hyfi_li = ecm_db_listener_alloc();
+	if (!ecm_classifier_hyfi_li) {
+		DEBUG_ERROR("Failed to allocate listener\n");
+		goto classifier_task_cleanup;
+	}
+
+	/*
+	 * Add the listener into the database
+	 * NOTE: Ref the thread count for the listener
+	 */
+	ecm_db_listener_add(ecm_classifier_hyfi_li,
+			NULL /* ecm_classifier_hyfi_iface_added */,
+			NULL /* ecm_classifier_hyfi_iface_removed */,
+			NULL /* ecm_classifier_hyfi_node_added */,
+			NULL /* ecm_classifier_hyfi_node_removed */,
+			NULL /* ecm_classifier_hyfi_host_added */,
+			NULL /* ecm_classifier_hyfi_host_removed */,
+			NULL /* ecm_classifier_hyfi_mapping_added */,
+			NULL /* ecm_classifier_hyfi_mapping_removed */,
+			ecm_classifier_hyfi_connection_added,
+			ecm_classifier_hyfi_connection_removed,
+			NULL /* ecm_classifier_hyfi_listener_final */,
+			ecm_classifier_hyfi_li);
+
+	return 0;
+
+classifier_task_cleanup:
+
+	debugfs_remove_recursive(ecm_classifier_hyfi_dentry);
+	return -1;
+}
+EXPORT_SYMBOL(ecm_classifier_hyfi_rules_init);
+
+/*
+ * ecm_classifier_hyfi_rules_exit()
+ */
+void ecm_classifier_hyfi_rules_exit(void)
+{
+	DEBUG_INFO("HyFi classifier Module exit\n");
+
+	spin_lock_bh(&ecm_classifier_hyfi_lock);
+	ecm_classifier_hyfi_terminate_pending = true;
+	spin_unlock_bh(&ecm_classifier_hyfi_lock);
+
+	/*
+	 * Release our ref to the listener.
+	 * This will cause it to be unattached to the db listener list.
+	 * NOTE: Our thread refs will be released on final callback when
+	 * we know there will be no more callbacks to it.
+	 */
+	if (ecm_classifier_hyfi_li) {
+		ecm_db_listener_deref(ecm_classifier_hyfi_li);
+		ecm_classifier_hyfi_li = NULL;
+	}
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_classifier_hyfi_dentry) {
+		debugfs_remove_recursive(ecm_classifier_hyfi_dentry);
+	}
+}
+EXPORT_SYMBOL(ecm_classifier_hyfi_rules_exit);
diff --git a/qca-nss-ecm/ecm_classifier_hyfi.h b/qca-nss-ecm/ecm_classifier_hyfi.h
new file mode 100644
index 0000000..ec30ab9
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_hyfi.h
@@ -0,0 +1,18 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+struct ecm_classifier_hyfi_instance;
+struct ecm_classifier_hyfi_instance *ecm_classifier_hyfi_instance_alloc(struct ecm_db_connection_instance *ci);
diff --git a/qca-nss-ecm/ecm_classifier_mark.c b/qca-nss-ecm/ecm_classifier_mark.c
new file mode 100644
index 0000000..d054d8e
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_mark.c
@@ -0,0 +1,786 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * Mark Classifier.
+ * This module provides an interface to customer's external module to interract with the ECM.
+ * It allows the customer to make smart decisions on the packets before offloading the connection to the
+ * acceleration engine.
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/debugfs.h>
+#include <linux/ctype.h>
+#include <net/tcp.h>
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/etherdevice.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_CLASSIFIER_MARK_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_mark.h"
+#include "ecm_classifier_mark_public.h"
+#include "ecm_front_end_common.h"
+#include "ecm_front_end_ipv4.h"
+#ifdef ECM_IPV6_ENABLE
+#include "ecm_front_end_ipv6.h"
+#endif
+
+/*
+ * Magic numbers
+ */
+#define ECM_CLASSIFIER_MARK_INSTANCE_MAGIC 0x2567
+
+/*
+ * struct ecm_classifier_mark_instance
+ * 	State per connection for MARK classifier
+ */
+struct ecm_classifier_mark_instance {
+	struct ecm_classifier_instance base;			/* Base type */
+
+	uint32_t ci_serial;					/* RO: Serial of the connection */
+
+	struct ecm_classifier_mark_instance *next;		/* Next classifier state instance (for accouting and reporting purposes) */
+	struct ecm_classifier_mark_instance *prev;		/* Next classifier state instance (for accouting and reporting purposes) */
+
+	uint32_t mark;						/* Mark value which this classifier extracted from the buffer */
+	struct ecm_classifier_process_response process_response;
+								/* Last process response computed */
+	int refs;						/* Integer to trap we never go negative */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+/*
+ * Operational control. By default it is disabled.
+ */
+static int ecm_classifier_mark_enabled;			/* Operational behaviour */
+
+/*
+ * Management thread control
+ */
+static bool ecm_classifier_mark_terminate_pending;	/* True when the user wants us to terminate */
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_classifier_mark_dentry;
+
+/*
+ * Locking of the classifier structures
+ */
+static DEFINE_SPINLOCK(ecm_classifier_mark_lock);			/* Protect SMP access. */
+
+/*
+ * List of our classifier instances
+ */
+static struct ecm_classifier_mark_instance *ecm_classifier_mark_instances = NULL;
+								/* list of all active instances */
+static int ecm_classifier_mark_count = 0;			/* Tracks number of instances allocated */
+
+/*
+ * Callbacks to the external modules.
+ */
+ecm_classifier_mark_get_callback_t mark_get_cb[ECM_CLASSIFIER_MARK_TYPE_MAX] = { NULL };
+								/* Callbacks which gets the mark from the packets */
+ecm_classifier_mark_sync_to_ipv4_callback_t sync_to_ipv4_cb[ECM_CLASSIFIER_MARK_TYPE_MAX] = { NULL };
+								/* Callbacks which syncs the IPv4 stats to the registered external subsystems */
+ecm_classifier_mark_sync_to_ipv6_callback_t sync_to_ipv6_cb[ECM_CLASSIFIER_MARK_TYPE_MAX] = { NULL };
+								/* Callbacks which syncs the IPv6 stats to the registered external subsystems */
+
+/*
+ * _ecm_classifier_mark_ref()
+ *	Ref
+ */
+static void _ecm_classifier_mark_ref(struct ecm_classifier_mark_instance *ecmi)
+{
+	ecmi->refs++;
+	DEBUG_TRACE("%px: ecmi ref %d\n", ecmi, ecmi->refs);
+	DEBUG_ASSERT(ecmi->refs > 0, "%px: ref wrap\n", ecmi);
+}
+
+/*
+ * ecm_classifier_mark_ref()
+ *	Ref
+ */
+static void ecm_classifier_mark_ref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_mark_instance *ecmi;
+	ecmi = (struct ecm_classifier_mark_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(ecmi, ECM_CLASSIFIER_MARK_INSTANCE_MAGIC, "%px: magic failed", ecmi);
+	spin_lock_bh(&ecm_classifier_mark_lock);
+	_ecm_classifier_mark_ref(ecmi);
+	spin_unlock_bh(&ecm_classifier_mark_lock);
+}
+
+/*
+ * ecm_classifier_mark_deref()
+ *	Deref
+ */
+static int ecm_classifier_mark_deref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_mark_instance *ecmi;
+	ecmi = (struct ecm_classifier_mark_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(ecmi, ECM_CLASSIFIER_MARK_INSTANCE_MAGIC, "%px: magic failed", ecmi);
+	spin_lock_bh(&ecm_classifier_mark_lock);
+	ecmi->refs--;
+	DEBUG_ASSERT(ecmi->refs >= 0, "%px: refs wrapped\n", ecmi);
+	DEBUG_TRACE("%px: Mark classifier deref %d\n", ecmi, ecmi->refs);
+	if (ecmi->refs) {
+		int refs = ecmi->refs;
+		spin_unlock_bh(&ecm_classifier_mark_lock);
+		return refs;
+	}
+
+	/*
+	 * Object to be destroyed
+	 */
+	ecm_classifier_mark_count--;
+	DEBUG_ASSERT(ecm_classifier_mark_count >= 0, "%px: ecm_classifier_mark_count wrap\n", ecmi);
+
+	/*
+	 * UnLink the instance from our list
+	 */
+	if (ecmi->next) {
+		ecmi->next->prev = ecmi->prev;
+	}
+	if (ecmi->prev) {
+		ecmi->prev->next = ecmi->next;
+	} else {
+		DEBUG_ASSERT(ecm_classifier_mark_instances == ecmi, "%px: list bad %px\n", ecmi, ecm_classifier_mark_instances);
+		ecm_classifier_mark_instances = ecmi->next;
+	}
+	ecmi->next = NULL;
+	ecmi->prev = NULL;
+	spin_unlock_bh(&ecm_classifier_mark_lock);
+
+	/*
+	 * Final
+	 */
+	DEBUG_INFO("%px: Final mark classifier instance\n", ecmi);
+	kfree(ecmi);
+
+	return 0;
+}
+
+/*
+ * ecm_classifier_mark_process()
+ *	Process new packet
+ *
+ * NOTE: This function would only ever be called if all other classifiers have failed.
+ */
+static void ecm_classifier_mark_process(struct ecm_classifier_instance *aci, ecm_tracker_sender_type_t sender,
+									struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb,
+									struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_mark_instance *ecmi = (struct ecm_classifier_mark_instance *)aci;
+	ecm_classifier_mark_result_t result;
+	struct ecm_db_connection_instance *ci;
+	bool skb_header_adjusted = false;
+	uint32_t l2_encap_len;
+	uint16_t l2_encap_proto;
+	uint16_t skb_proto;
+	uint32_t mark = 0;
+	ecm_classifier_mark_get_callback_t cb = NULL;
+	ecm_classifier_mark_type_t type = ECM_CLASSIFIER_MARK_TYPE_L2_ENCAP;
+			/* TODO: By default we use this type. In the future the type will be gotten from the connection instance*/
+
+	DEBUG_CHECK_MAGIC(ecmi, ECM_CLASSIFIER_MARK_INSTANCE_MAGIC, "%px: invalid state magic\n", ecmi);
+
+	/*
+	 * Not relevant to the connection if not enabled.
+	 */
+	if (unlikely(!ecm_classifier_mark_enabled)) {
+		/*
+		 * Not relevant.
+		 */
+		DEBUG_WARN("%px: Mark classifier is not enabled.\n", aci);
+		goto not_relevant;
+	}
+
+	/*
+	 * Get connection
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(ecmi->ci_serial);
+	if (!ci) {
+		/*
+		 * Connection has gone from under us
+		 */
+		DEBUG_WARN("%px: connection instance gone while processing classifier.\n", aci);
+		goto not_relevant;
+	}
+
+	/*
+	 * Get the L2 encap protocol of the connection.
+	 */
+	l2_encap_proto = ecm_db_connection_l2_encap_proto_get(ci);
+	if (!l2_encap_proto) {
+		/*
+		 * The caller is not interested in the inspection. Not relevant.
+		 */
+		DEBUG_WARN("%px: L2 encap protocol is zero.\n", aci);
+		ecm_db_connection_deref(ci);
+		goto not_relevant;
+	}
+
+	/*
+	 * Is there an external callback to get the mark value from the packet?
+	 */
+	rcu_read_lock();
+	cb = rcu_dereference(mark_get_cb[type]);
+	if (!cb) {
+		/*
+		 * Not relevant.
+		 */
+		rcu_read_unlock();
+		DEBUG_WARN("%px: No inspection callback set with type: %d.\n", aci, type);
+		ecm_db_connection_deref(ci);
+		goto not_relevant;
+	}
+
+	/*
+	 * Before giving the skb to the external callback for getting the mark value,
+	 * let's adjust the L2 encap header.
+	 * If the skb's protocol is not equal to the connection's L2 encap protocol,
+	 * this means the skb's L2 header is pulled off. So, let's push it back.
+	 */
+	if (l2_encap_proto != ntohs(skb->protocol)) {
+		DEBUG_TRACE("%px: Connections L2 encap protocol: %x is different than skb's protocol: %x, need header adjustment.\n",
+			    aci, l2_encap_proto, ntohs(skb->protocol));
+		l2_encap_len = ecm_front_end_l2_encap_header_len(l2_encap_proto);
+		skb_header_adjusted = true;
+		ecm_front_end_push_l2_encap_header(skb, l2_encap_len);
+		skb_proto = skb->protocol;
+		skb->protocol = htons(l2_encap_proto);
+	}
+
+	/*
+	 * Call the external callback and get the result.
+	 */
+	result = cb(skb, &mark);
+	rcu_read_unlock();
+
+	/*
+	 * Pull the skb's L2 header, if it is adjusted in this classifier.
+	 */
+	if (skb_header_adjusted) {
+		DEBUG_TRACE("%px: Adjust the L2 header back.\n", aci);
+		ecm_front_end_pull_l2_encap_header(skb, l2_encap_len);
+		skb->protocol = skb_proto;
+	}
+
+	/*
+	 * Handle the result
+	 */
+	switch (result) {
+	case ECM_CLASSIFIER_MARK_RESULT_NOT_YET:
+		/*
+		 * Deny accel but don't change the permit state - we try again later
+		 */
+		DEBUG_WARN("%px: External callback has not decided yet.\n", aci);
+		goto deny_accel;
+	case ECM_CLASSIFIER_MARK_RESULT_NOT_RELEVANT:
+		/*
+		 * The callback told us that the classifier is not relevant to this connection.
+		 */
+		DEBUG_WARN("%px: External callback decided not relevant.\n", aci);
+		ecm_db_connection_deref(ci);
+		goto not_relevant;
+	case ECM_CLASSIFIER_MARK_RESULT_SUCCESS:
+
+		/*
+		 * Copy the returned mark value to the connection and the classifier instance.
+		 * We copy the mark value to the classifier instance as well here for quick access
+		 * in the sync functions.
+		 */
+		DEBUG_WARN("%px: External callback returned the mark value: %x\n", aci, mark);
+		ecm_db_connection_mark_set(ci, mark);
+		ecmi->mark = mark;
+		break;
+	default:
+		DEBUG_ASSERT(false, "Unhandled result: %d\n", result);
+	}
+
+	/*
+	 * Acceleration is permitted
+	 */
+	spin_lock_bh(&ecm_classifier_mark_lock);
+	ecmi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	ecmi->process_response.process_actions = ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	ecmi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+	*process_response = ecmi->process_response;
+	spin_unlock_bh(&ecm_classifier_mark_lock);
+	ecm_db_connection_deref(ci);
+
+	return;
+
+not_relevant:
+	/*
+	 * ecm_classifier_mark_lock MUST be held
+	 */
+	spin_lock_bh(&ecm_classifier_mark_lock);
+	ecmi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+	*process_response = ecmi->process_response;
+	spin_unlock_bh(&ecm_classifier_mark_lock);
+	return;
+
+deny_accel:
+	/*
+	 * ecm_classifier_mark_lock MUST be held
+	 */
+	spin_lock_bh(&ecm_classifier_mark_lock);
+	ecmi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	ecmi->process_response.process_actions = ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	ecmi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+	*process_response = ecmi->process_response;
+	spin_unlock_bh(&ecm_classifier_mark_lock);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_classifier_mark_type_get()
+ *	Get type of classifier this is
+ */
+static ecm_classifier_type_t ecm_classifier_mark_type_get(struct ecm_classifier_instance *aci)
+{
+	struct ecm_classifier_mark_instance *ecmi;
+	ecmi = (struct ecm_classifier_mark_instance *)aci;
+
+	DEBUG_CHECK_MAGIC(ecmi, ECM_CLASSIFIER_MARK_INSTANCE_MAGIC, "%px: magic failed", ecmi);
+	return ECM_CLASSIFIER_TYPE_MARK;
+}
+
+/*
+ * ecm_classifier_mark_reclassify_allowed()
+ *	Get whether reclassification is allowed
+ */
+static bool ecm_classifier_mark_reclassify_allowed(struct ecm_classifier_instance *aci)
+{
+	struct ecm_classifier_mark_instance *ecmi;
+	ecmi = (struct ecm_classifier_mark_instance *)aci;
+
+	DEBUG_CHECK_MAGIC(ecmi, ECM_CLASSIFIER_MARK_INSTANCE_MAGIC, "%px: magic failed", ecmi);
+	return true;
+}
+
+/*
+ * ecm_classifier_mark_reclassify()
+ *	Reclassify
+ */
+static void ecm_classifier_mark_reclassify(struct ecm_classifier_instance *aci)
+{
+	struct ecm_classifier_mark_instance *ecmi;
+	ecmi = (struct ecm_classifier_mark_instance *)aci;
+	DEBUG_CHECK_MAGIC(ecmi, ECM_CLASSIFIER_MARK_INSTANCE_MAGIC, "%px: magic failed", ecmi);
+
+	/*
+	 * Revert back to MAYBE relevant - we will evaluate when we get the next process() call.
+	 */
+	spin_lock_bh(&ecm_classifier_mark_lock);
+	ecmi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_MAYBE;
+	spin_unlock_bh(&ecm_classifier_mark_lock);
+}
+
+/*
+ * ecm_classifier_mark_last_process_response_get()
+ *	Get result code returned by the last process call
+ */
+static void ecm_classifier_mark_last_process_response_get(struct ecm_classifier_instance *aci,
+							struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_mark_instance *ecmi;
+	ecmi = (struct ecm_classifier_mark_instance *)aci;
+	DEBUG_CHECK_MAGIC(ecmi, ECM_CLASSIFIER_MARK_INSTANCE_MAGIC, "%px: magic failed", ecmi);
+
+	spin_lock_bh(&ecm_classifier_mark_lock);
+	*process_response = ecmi->process_response;
+	spin_unlock_bh(&ecm_classifier_mark_lock);
+}
+
+/*
+ * ecm_classifier_mark_sync_to_v4()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_mark_sync_to_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	int protocol;
+	int src_port;
+	int dst_port;
+	ip_addr_t src_ip;
+	ip_addr_t dst_ip;
+	__be32 src_ip4;
+	__be32 dest_ip4;
+	struct ecm_db_connection_instance *ci;
+	ecm_classifier_mark_sync_to_ipv4_callback_t cb = NULL;
+	ecm_classifier_mark_type_t type = ECM_CLASSIFIER_MARK_TYPE_L2_ENCAP;
+			/* TODO: By default we use this type. In the future the type will be gotten from the connection instance */
+	struct ecm_classifier_mark_instance *ecmi = (struct ecm_classifier_mark_instance *)aci;
+	DEBUG_CHECK_MAGIC(ecmi, ECM_CLASSIFIER_MARK_INSTANCE_MAGIC, "%px: magic failed", ecmi);
+
+	/*
+	 * Nothing to update.
+	 * We only care about flows that are actively being accelerated.
+	 */
+	if (!(sync->tx_packet_count[ECM_CONN_DIR_FLOW] || sync->tx_packet_count[ECM_CONN_DIR_RETURN])) {
+		return;
+	}
+
+	/*
+	 * Handle only the stats sync. We don't care about the evict or flush syncs.
+	 */
+	if (sync->reason != ECM_FRONT_END_IPV4_RULE_SYNC_REASON_STATS) {
+		return;
+	}
+
+	ci = ecm_db_connection_serial_find_and_ref(ecmi->ci_serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: No ci found for %u\n", ecmi, ecmi->ci_serial);
+		return;
+	}
+
+	protocol = ecm_db_connection_protocol_get(ci);
+	src_port = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+	dst_port = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO));
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+
+	ecm_db_connection_deref(ci);
+
+	ECM_IP_ADDR_TO_NIN4_ADDR(src_ip4, src_ip);
+	ECM_IP_ADDR_TO_NIN4_ADDR(dest_ip4, dst_ip);
+
+	rcu_read_lock();
+	cb = rcu_dereference(sync_to_ipv4_cb[type]);
+	if (!cb) {
+		rcu_read_unlock();
+		DEBUG_WARN("%px: IPv4 mark sync callback is not set\n", ecmi);
+		return;
+	}
+
+	cb(ecmi->mark, src_ip4, src_port, dest_ip4, dst_port, protocol);
+	rcu_read_unlock();
+}
+
+/*
+ * ecm_classifier_mark_sync_from_v4()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_mark_sync_from_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_mark_instance *ecmi __attribute__((unused));
+
+	ecmi = (struct ecm_classifier_mark_instance *)aci;
+	DEBUG_CHECK_MAGIC(ecmi, ECM_CLASSIFIER_MARK_INSTANCE_MAGIC, "%px: magic failed", ecmi);
+}
+
+/*
+ * ecm_classifier_mark_sync_to_v6()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_mark_sync_to_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	int protocol;
+	int src_port;
+	int dst_port;
+	ip_addr_t src_ip;
+	ip_addr_t dst_ip;
+	struct in6_addr src_ip6;
+	struct in6_addr dest_ip6;
+	struct ecm_db_connection_instance *ci;
+	ecm_classifier_mark_sync_to_ipv6_callback_t cb = NULL;
+	ecm_classifier_mark_type_t type = ECM_CLASSIFIER_MARK_TYPE_L2_ENCAP;
+			/* TODO: By default we use this type. In the future the type will be gotten from the connection instance */
+	struct ecm_classifier_mark_instance *ecmi = (struct ecm_classifier_mark_instance *)aci;
+	DEBUG_CHECK_MAGIC(ecmi, ECM_CLASSIFIER_MARK_INSTANCE_MAGIC, "%px: magic failed", ecmi);
+
+	/*
+	 * Nothing to update.
+	 * We only care about flows that are actively being accelerated.
+	 */
+	if (!(sync->tx_packet_count[ECM_CONN_DIR_FLOW] || sync->tx_packet_count[ECM_CONN_DIR_RETURN])) {
+		return;
+	}
+
+	/*
+	 * Handle only the stats sync. We don't care about the evict or flush syncs.
+	 */
+	if (sync->reason != ECM_FRONT_END_IPV4_RULE_SYNC_REASON_STATS) {
+		return;
+	}
+
+	ci = ecm_db_connection_serial_find_and_ref(ecmi->ci_serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: No ci found for %u\n", ecmi, ecmi->ci_serial);
+		return;
+	}
+
+	protocol = ecm_db_connection_protocol_get(ci);
+	src_port = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+	dst_port = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO));
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+
+	ecm_db_connection_deref(ci);
+
+	ECM_IP_ADDR_TO_NIN6_ADDR(src_ip6, src_ip);
+	ECM_IP_ADDR_TO_NIN6_ADDR(dest_ip6, dst_ip);
+
+	rcu_read_lock();
+	cb = rcu_dereference(sync_to_ipv6_cb[type]);
+	if (!cb) {
+		rcu_read_unlock();
+		DEBUG_WARN("%px: IPv6 mark sync callback is not set\n", ecmi);
+		return;
+	}
+	cb(ecmi->mark, &src_ip6, src_port, &dest_ip6, dst_port, protocol);
+	rcu_read_unlock();
+}
+
+/*
+ * ecm_classifier_mark_sync_from_v6()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_mark_sync_from_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_mark_instance *ecmi __attribute__((unused));
+
+	ecmi = (struct ecm_classifier_mark_instance *)aci;
+	DEBUG_CHECK_MAGIC(ecmi, ECM_CLASSIFIER_MARK_INSTANCE_MAGIC, "%px: magic failed", ecmi);
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_classifier_mark_state_get()
+ *	Gets the state of this classfier and outputs it to debugfs.
+ */
+static int ecm_classifier_mark_state_get(struct ecm_classifier_instance *ci, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	struct ecm_classifier_mark_instance *ecmi;
+	struct ecm_classifier_process_response process_response;
+	uint32_t mark;
+
+	ecmi = (struct ecm_classifier_mark_instance *)ci;
+	DEBUG_CHECK_MAGIC(ecmi, ECM_CLASSIFIER_MARK_INSTANCE_MAGIC, "%px: magic failed", ecmi);
+
+	if ((result = ecm_state_prefix_add(sfi, "mark"))) {
+		return result;
+	}
+
+	spin_lock_bh(&ecm_classifier_mark_lock);
+	mark = ecmi->mark;
+	process_response = ecmi->process_response;
+	spin_unlock_bh(&ecm_classifier_mark_lock);
+
+	if ((result = ecm_state_write(sfi, "value", "%d", mark))) {
+		return result;
+	}
+
+	/*
+	 * Output our last process response
+	 */
+	if ((result = ecm_classifier_process_response_state_get(sfi, &process_response))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+/*
+ * ecm_classifier_mark_instance_alloc()
+ *	Allocate an instance of the mark classifier
+ */
+struct ecm_classifier_mark_instance *ecm_classifier_mark_instance_alloc(struct ecm_db_connection_instance *ci)
+{
+	struct ecm_classifier_mark_instance *ecmi;
+
+	/*
+	 * Allocate the instance
+	 */
+	ecmi = (struct ecm_classifier_mark_instance *)kzalloc(sizeof(struct ecm_classifier_mark_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!ecmi) {
+		DEBUG_WARN("i%px: Failed to allocate Mark Classifier instance\n", ci);
+		return NULL;
+	}
+
+	DEBUG_SET_MAGIC(ecmi, ECM_CLASSIFIER_MARK_INSTANCE_MAGIC);
+	ecmi->refs = 1;
+
+	/*
+	 * Methods generic to all classifiers.
+	 */
+	ecmi->base.process = ecm_classifier_mark_process;
+	ecmi->base.sync_from_v4 = ecm_classifier_mark_sync_from_v4;
+	ecmi->base.sync_to_v4 = ecm_classifier_mark_sync_to_v4;
+	ecmi->base.sync_from_v6 = ecm_classifier_mark_sync_from_v6;
+	ecmi->base.sync_to_v6 = ecm_classifier_mark_sync_to_v6;
+	ecmi->base.type_get = ecm_classifier_mark_type_get;
+	ecmi->base.reclassify_allowed = ecm_classifier_mark_reclassify_allowed;
+	ecmi->base.reclassify = ecm_classifier_mark_reclassify;
+	ecmi->base.last_process_response_get = ecm_classifier_mark_last_process_response_get;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ecmi->base.state_get = ecm_classifier_mark_state_get;
+#endif
+	ecmi->base.ref = ecm_classifier_mark_ref;
+	ecmi->base.deref = ecm_classifier_mark_deref;
+	ecmi->ci_serial = ecm_db_connection_serial_get(ci);
+
+	ecmi->process_response.process_actions = 0;
+	ecmi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_MAYBE;
+
+	/*
+	 * Final check if we are pending termination
+	 */
+	spin_lock_bh(&ecm_classifier_mark_lock);
+	if (ecm_classifier_mark_terminate_pending) {
+		spin_unlock_bh(&ecm_classifier_mark_lock);
+		DEBUG_WARN("%px: Terminating\n", ci);
+		kfree(ecmi);
+		return NULL;
+	}
+
+	/*
+	 * Link the new instance into our list at the head
+	 */
+	ecmi->next = ecm_classifier_mark_instances;
+	if (ecm_classifier_mark_instances) {
+		ecm_classifier_mark_instances->prev = ecmi;
+	}
+	ecm_classifier_mark_instances = ecmi;
+
+	/*
+	 * Increment stats
+	 */
+	ecm_classifier_mark_count++;
+	DEBUG_ASSERT(ecm_classifier_mark_count > 0, "%px: ecm_classifier_mark_count wrap for instance: %px\n", ci, ecmi);
+	spin_unlock_bh(&ecm_classifier_mark_lock);
+
+	DEBUG_INFO("%px: Mark classifier instance alloc: %px\n", ci, ecmi);
+	return ecmi;
+}
+EXPORT_SYMBOL(ecm_classifier_mark_instance_alloc);
+
+/*
+ * ecm_classifier_mark_register_callbacks()
+ *	Register external callbacks.
+ */
+int ecm_classifier_mark_register_callbacks(ecm_classifier_mark_type_t type,
+					   ecm_classifier_mark_get_callback_t mark_get,
+					   ecm_classifier_mark_sync_to_ipv4_callback_t sync_to_ipv4,
+					   ecm_classifier_mark_sync_to_ipv6_callback_t sync_to_ipv6)
+{
+	spin_lock_bh(&ecm_classifier_mark_lock);
+	if (ecm_classifier_mark_terminate_pending) {
+		spin_unlock_bh(&ecm_classifier_mark_lock);
+		DEBUG_WARN("Terminating\n");
+		return -1;
+	}
+	spin_unlock_bh(&ecm_classifier_mark_lock);
+
+	DEBUG_ASSERT(!mark_get_cb[type] && !sync_to_ipv4_cb[type] && !sync_to_ipv6_cb[type],
+			"Mark callbacks are already registered\n");
+	rcu_assign_pointer(mark_get_cb[type], mark_get);
+	rcu_assign_pointer(sync_to_ipv4_cb[type], sync_to_ipv4);
+	rcu_assign_pointer(sync_to_ipv6_cb[type], sync_to_ipv6);
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_classifier_mark_register_callbacks);
+
+/*
+ * ecm_classifier_mark_unregister_callbacks()
+ *	Unregister external callbacks.
+ */
+void ecm_classifier_mark_unregister_callbacks(ecm_classifier_mark_type_t type)
+{
+	rcu_assign_pointer(mark_get_cb[type], NULL);
+	rcu_assign_pointer(sync_to_ipv4_cb[type], NULL);
+	rcu_assign_pointer(sync_to_ipv6_cb[type], NULL);
+
+}
+EXPORT_SYMBOL(ecm_classifier_mark_unregister_callbacks);
+
+/*
+ * ecm_classifier_mark_init()
+ */
+int ecm_classifier_mark_init(struct dentry *dentry)
+{
+	DEBUG_INFO("Mark classifier Module init\n");
+
+	ecm_classifier_mark_dentry = debugfs_create_dir("ecm_classifier_mark", dentry);
+	if (!ecm_classifier_mark_dentry) {
+		DEBUG_ERROR("Failed to create ecm mark directory in debugfs\n");
+		return -1;
+	}
+
+	if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mark_dentry,
+					(u32 *)&ecm_classifier_mark_enabled)) {
+		DEBUG_ERROR("Failed to create mark enabled file in debugfs\n");
+		debugfs_remove_recursive(ecm_classifier_mark_dentry);
+		return -1;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_classifier_mark_init);
+
+/*
+ * ecm_classifier_mark_exit()
+ */
+void ecm_classifier_mark_exit(void)
+{
+	DEBUG_INFO("Mark classifier Module exit\n");
+
+	spin_lock_bh(&ecm_classifier_mark_lock);
+	ecm_classifier_mark_terminate_pending = true;
+	spin_unlock_bh(&ecm_classifier_mark_lock);
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_classifier_mark_dentry) {
+		debugfs_remove_recursive(ecm_classifier_mark_dentry);
+	}
+
+}
+EXPORT_SYMBOL(ecm_classifier_mark_exit);
diff --git a/qca-nss-ecm/ecm_classifier_mark.h b/qca-nss-ecm/ecm_classifier_mark.h
new file mode 100644
index 0000000..39693b8
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_mark.h
@@ -0,0 +1,18 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+struct ecm_classifier_mark_instance;
+struct ecm_classifier_mark_instance *ecm_classifier_mark_instance_alloc(struct ecm_db_connection_instance *ci);
diff --git a/qca-nss-ecm/ecm_classifier_mark_public.h b/qca-nss-ecm/ecm_classifier_mark_public.h
new file mode 100644
index 0000000..d5351b4
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_mark_public.h
@@ -0,0 +1,63 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * Mark types are used to register specific external mdoule callbacks to ECM.
+ * Each type of callback can process the packets based on its need.
+ */
+enum ecm_classifier_mark_types {
+	ECM_CLASSIFIER_MARK_TYPE_L2_ENCAP,
+	ECM_CLASSIFIER_MARK_TYPE_MAX
+};
+typedef enum ecm_classifier_mark_types ecm_classifier_mark_type_t;
+
+/*
+ * Result values of the external inspection module to the ECM's mark classifier.
+ * Based on the result the mark classifier takes the action for the inspected connection.
+ */
+enum ecm_classifier_mark_results {
+	ECM_CLASSIFIER_MARK_RESULT_NOT_YET,		/* Classifier has not decided yet - try again later */
+	ECM_CLASSIFIER_MARK_RESULT_NOT_RELEVANT,	/* Classifier is not relevant to this connection */
+	ECM_CLASSIFIER_MARK_RESULT_SUCCESS,		/* Inspection is completed successfully */
+};
+typedef enum ecm_classifier_mark_results ecm_classifier_mark_result_t;
+
+/*
+ * Callback function which extracts a mark value from the skb and write it to the mark parameter.
+ */
+typedef ecm_classifier_mark_result_t (*ecm_classifier_mark_get_callback_t)(struct sk_buff *skb, uint32_t *mark);
+
+/*
+ * Callback functions which are called from the mark classifier's IPv4 and IPv6 sync_to
+ * functions to update the external modules.
+ */
+typedef void (*ecm_classifier_mark_sync_to_ipv4_callback_t)(uint32_t mark,
+							    __be32 src_ip, int src_port,
+							    __be32 dest_ip, int dest_port,
+							    int protocol);
+typedef void (*ecm_classifier_mark_sync_to_ipv6_callback_t)(uint32_t mark,
+							    struct in6_addr *src_ip, int src_port,
+							    struct in6_addr *dest_ip, int dest_port,
+							    int protocol);
+
+/*
+ * Register/Unregister callback functions which are called from the external modules.
+ */
+extern int ecm_classifier_mark_register_callbacks(ecm_classifier_mark_type_t type, ecm_classifier_mark_get_callback_t mark_get,
+						  ecm_classifier_mark_sync_to_ipv4_callback_t sync_to_ipv4,
+						  ecm_classifier_mark_sync_to_ipv6_callback_t sync_to_ipv6);
+extern void ecm_classifier_mark_unregister_callbacks(ecm_classifier_mark_type_t type);
+
diff --git a/qca-nss-ecm/ecm_classifier_mscs.c b/qca-nss-ecm/ecm_classifier_mscs.c
new file mode 100644
index 0000000..3ba2ebf
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_mscs.c
@@ -0,0 +1,652 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/debugfs.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_CLASSIFIER_MSCS_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_mscs.h"
+#include "exports/ecm_classifier_mscs_public.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_CLASSIFIER_MSCS_INSTANCE_MAGIC 0x1234
+
+/*
+ * struct ecm_classifier_mscs_instance
+ * 	State to allow tracking of MSCS QoS tag for a connection
+ */
+struct ecm_classifier_mscs_instance {
+	struct ecm_classifier_instance base;			/* Base type */
+
+	struct ecm_classifier_mscs_instance *next;		/* Next classifier state instance (for accouting and reporting purposes) */
+	struct ecm_classifier_mscs_instance *prev;		/* Next classifier state instance (for accouting and reporting purposes) */
+
+	uint32_t ci_serial;					/* RO: Serial of the connection */
+	struct ecm_classifier_process_response process_response;/* Last process response computed */
+
+	int refs;						/* Integer to trap we never go negative */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+/*
+ * Operational control
+ */
+static int ecm_classifier_mscs_enabled = 0;			/* Operational behaviour */
+
+/*
+ * Management thread control
+ */
+static bool ecm_classifier_mscs_terminate_pending;	/* True when the user wants us to terminate */
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_classifier_mscs_dentry;
+
+/*
+ * Locking of the classifier structures
+ */
+static DEFINE_SPINLOCK(ecm_classifier_mscs_lock);			/* Protect SMP access. */
+
+/*
+ * List of our classifier instances
+ */
+static struct ecm_classifier_mscs_instance *ecm_classifier_mscs_instances;
+								/* list of all active instances */
+static int ecm_classifier_mscs_count;			/* Tracks number of instances allocated */
+
+/*
+ * Callback structure to support MSCS peer lookup in external module
+ */
+static struct ecm_classifier_mscs_callbacks ecm_mscs;
+
+/*
+ * ecm_classifier_mscs_ref()
+ *	Ref
+ */
+static void ecm_classifier_mscs_ref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_mscs_instance *cmscsi;
+	cmscsi = (struct ecm_classifier_mscs_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(cmscsi, ECM_CLASSIFIER_MSCS_INSTANCE_MAGIC, "%px: magic failed\n", cmscsi);
+	spin_lock_bh(&ecm_classifier_mscs_lock);
+	cmscsi->refs++;
+	DEBUG_TRACE("%px: cmscsi ref %d\n", cmscsi, cmscsi->refs);
+	DEBUG_ASSERT(cmscsi->refs > 0, "%px: ref wrap\n", cmscsi);
+	spin_unlock_bh(&ecm_classifier_mscs_lock);
+}
+
+/*
+ * ecm_classifier_mscs_deref()
+ *	Deref
+ */
+static int ecm_classifier_mscs_deref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_mscs_instance *cmscsi;
+	cmscsi = (struct ecm_classifier_mscs_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(cmscsi, ECM_CLASSIFIER_MSCS_INSTANCE_MAGIC, "%px: magic failed\n", cmscsi);
+	spin_lock_bh(&ecm_classifier_mscs_lock);
+	cmscsi->refs--;
+	DEBUG_ASSERT(cmscsi->refs >= 0, "%px: refs wrapped\n", cmscsi);
+	DEBUG_TRACE("%px: MSCS classifier deref %d\n", cmscsi, cmscsi->refs);
+	if (cmscsi->refs) {
+		int refs = cmscsi->refs;
+		spin_unlock_bh(&ecm_classifier_mscs_lock);
+		return refs;
+	}
+
+	/*
+	 * Object to be destroyed
+	 */
+	ecm_classifier_mscs_count--;
+	DEBUG_ASSERT(ecm_classifier_mscs_count >= 0, "%px: ecm_classifier_mscs_count wrap\n", cmscsi);
+
+	/*
+	 * UnLink the instance from our list
+	 */
+	if (cmscsi->next) {
+		cmscsi->next->prev = cmscsi->prev;
+	}
+	if (cmscsi->prev) {
+		cmscsi->prev->next = cmscsi->next;
+	} else {
+		DEBUG_ASSERT(ecm_classifier_mscs_instances == cmscsi, "%px: list bad %px\n", cmscsi, ecm_classifier_mscs_instances);
+		ecm_classifier_mscs_instances = cmscsi->next;
+	}
+	cmscsi->next = NULL;
+	cmscsi->prev = NULL;
+	spin_unlock_bh(&ecm_classifier_mscs_lock);
+
+	/*
+	 * Final
+	 */
+	DEBUG_INFO("%px: Final MSCS classifier instance\n", cmscsi);
+	kfree(cmscsi);
+
+	return 0;
+}
+
+/*
+ * ecm_classifier_mscs_process()
+ *	Process new data for connection
+ */
+static void ecm_classifier_mscs_process(struct ecm_classifier_instance *aci, ecm_tracker_sender_type_t sender,
+						struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb,
+						struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_mscs_instance *cmscsi;
+	ecm_classifier_relevence_t relevance;
+	struct ecm_db_connection_instance *ci = NULL;
+	struct ecm_front_end_connection_instance *feci;
+	ecm_front_end_acceleration_mode_t accel_mode;
+	int protocol;
+	uint32_t became_relevant = 0;
+	ecm_classifier_mscs_process_callback_t cb = NULL;
+	ecm_classifier_mscs_result_t result = 0;
+	uint8_t smac[ETH_ALEN];
+	uint8_t dmac[ETH_ALEN];
+#ifdef ECM_MULTICAST_ENABLE
+	ip_addr_t dst_ip;
+#endif
+
+	cmscsi = (struct ecm_classifier_mscs_instance *)aci;
+	DEBUG_CHECK_MAGIC(cmscsi, ECM_CLASSIFIER_MSCS_INSTANCE_MAGIC, "%px: magic failed\n", cmscsi);
+
+	/*
+	 * Are we yet to decide if this instance is relevant to the connection?
+	 */
+	spin_lock_bh(&ecm_classifier_mscs_lock);
+	relevance = cmscsi->process_response.relevance;
+
+	/*
+	 * Are we relevant?
+	 */
+	if (relevance == ECM_CLASSIFIER_RELEVANCE_NO) {
+		/*
+		 * Lock still held
+		 */
+		goto mscs_classifier_out;
+	}
+
+	if (!ecm_classifier_mscs_enabled) {
+		/*
+		 * Lock still held
+		 */
+		cmscsi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+		goto mscs_classifier_out;
+	}
+	spin_unlock_bh(&ecm_classifier_mscs_lock);
+
+	/*
+	 * Can we accelerate?
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(cmscsi->ci_serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: No ci found for %u\n", cmscsi, cmscsi->ci_serial);
+		spin_lock_bh(&ecm_classifier_mscs_lock);
+		cmscsi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+		goto mscs_classifier_out;
+	}
+
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	accel_mode = feci->accel_state_get(feci);
+	feci->deref(feci);
+	protocol = ecm_db_connection_protocol_get(ci);
+
+	/*
+	 * MSCS classifier is not applicable for Multicast Traffic
+	 */
+#ifdef ECM_MULTICAST_ENABLE
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+	if (ecm_ip_addr_is_multicast(dst_ip)) {
+		DEBUG_TRACE("%px: Multicast Traffic, skip MSCS classification\n", ci);
+		ecm_db_connection_deref(ci);
+		spin_lock_bh(&ecm_classifier_mscs_lock);
+		cmscsi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+		goto mscs_classifier_out;
+	}
+#endif
+
+	/*
+	 * Get the source mac address for this connection
+	 */
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		DEBUG_TRACE("%px: sender is SRC\n", aci);
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, smac);
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, dmac);
+	} else {
+		DEBUG_TRACE("%px: sender is DEST\n", aci);
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, smac);
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, dmac);
+	}
+	ecm_db_connection_deref(ci);
+
+	spin_lock_bh(&ecm_classifier_mscs_lock);
+
+	/*
+	 * Get the WiFi datapath callback registered with MSCS client to check
+	 * if MSCS QoS tag is valid for WiFi peer corresponding to
+	 * skb->src_mac_addr
+	 */
+	cb = ecm_mscs.get_peer_priority;
+	if (!cb) {
+		cmscsi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+		goto mscs_classifier_out;
+	}
+
+	spin_unlock_bh(&ecm_classifier_mscs_lock);
+
+	/*
+	 * Invoke callback registered to classifier for peer look up
+	 */
+	result = cb(smac, dmac, skb);
+
+	/*
+	 * check the result of callback
+	 */
+	if (result == ECM_CLASSIFIER_MSCS_RESULT_DENY_PRIORITY) {
+		spin_lock_bh(&ecm_classifier_mscs_lock);
+		cmscsi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+		goto mscs_classifier_out;
+	}
+
+	/*
+	 * We are relevant to the connection
+	 */
+	became_relevant = ecm_db_time_get();
+	DEBUG_TRACE("MSCS Flow Priority: Flow priority: %d, Return priority: %d sender: %d\n",
+			skb->priority, skb->priority, sender);
+
+	spin_lock_bh(&ecm_classifier_mscs_lock);
+	cmscsi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	cmscsi->process_response.became_relevant = became_relevant;
+
+	cmscsi->process_response.process_actions = ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG;
+
+	if (result == ECM_CLASSIFIER_MSCS_RESULT_UPDATE_PRIORITY) {
+		cmscsi->process_response.flow_qos_tag = skb->priority;
+		cmscsi->process_response.return_qos_tag = skb->priority;
+	} else if (result == ECM_CLASSIFIER_MSCS_RESULT_UPDATE_INVALID_TAG) {
+		cmscsi->process_response.flow_qos_tag = ECM_CLASSIFIER_MSCS_INVALID_QOS_TAG;
+		cmscsi->process_response.return_qos_tag = ECM_CLASSIFIER_MSCS_INVALID_QOS_TAG;
+	}
+
+mscs_classifier_out:
+
+	/*
+	 * Return our process response
+	 */
+	*process_response = cmscsi->process_response;
+	spin_unlock_bh(&ecm_classifier_mscs_lock);
+}
+
+/*
+ * ecm_classifier_mscs_sync_to_v4()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_mscs_sync_to_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	struct ecm_classifier_mscs_instance *cmscsi __attribute__((unused));
+
+	cmscsi = (struct ecm_classifier_mscs_instance *)aci;
+	DEBUG_CHECK_MAGIC(cmscsi, ECM_CLASSIFIER_MSCS_INSTANCE_MAGIC, "%px: magic failed", cmscsi);
+}
+
+/*
+ * ecm_classifier_mscs_sync_from_v4()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_mscs_sync_from_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_mscs_instance *cmscsi __attribute__((unused));
+
+	cmscsi = (struct ecm_classifier_mscs_instance *)aci;
+	DEBUG_CHECK_MAGIC(cmscsi, ECM_CLASSIFIER_MSCS_INSTANCE_MAGIC, "%px: magic failed", cmscsi);
+}
+
+/*
+ * ecm_classifier_mscs_sync_to_v6()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_mscs_sync_to_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	struct ecm_classifier_mscs_instance *cmscsi __attribute__((unused));
+
+	cmscsi = (struct ecm_classifier_mscs_instance *)aci;
+	DEBUG_CHECK_MAGIC(cmscsi, ECM_CLASSIFIER_MSCS_INSTANCE_MAGIC, "%px: magic failed", cmscsi);
+}
+
+/*
+ * ecm_classifier_mscs_sync_from_v6()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_mscs_sync_from_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_mscs_instance *cmscsi __attribute__((unused));
+
+	cmscsi = (struct ecm_classifier_mscs_instance *)aci;
+	DEBUG_CHECK_MAGIC(cmscsi, ECM_CLASSIFIER_MSCS_INSTANCE_MAGIC, "%px: magic failed", cmscsi);
+}
+
+/*
+ * ecm_classifier_mscs_type_get()
+ *	Get type of classifier this is
+ */
+static ecm_classifier_type_t ecm_classifier_mscs_type_get(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_mscs_instance *cmscsi;
+	cmscsi = (struct ecm_classifier_mscs_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(cmscsi, ECM_CLASSIFIER_MSCS_INSTANCE_MAGIC, "%px: magic failed\n", cmscsi);
+	return ECM_CLASSIFIER_TYPE_MSCS;
+}
+
+/*
+ * ecm_classifier_mscs_last_process_response_get()
+ *	Get result code returned by the last process call
+ */
+static void ecm_classifier_mscs_last_process_response_get(struct ecm_classifier_instance *ci,
+							struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_mscs_instance *cmscsi;
+
+	cmscsi = (struct ecm_classifier_mscs_instance *)ci;
+	DEBUG_CHECK_MAGIC(cmscsi, ECM_CLASSIFIER_MSCS_INSTANCE_MAGIC, "%px: magic failed\n", cmscsi);
+
+	spin_lock_bh(&ecm_classifier_mscs_lock);
+	*process_response = cmscsi->process_response;
+	spin_unlock_bh(&ecm_classifier_mscs_lock);
+}
+
+/*
+ * ecm_classifier_mscs_reclassify_allowed()
+ *	Indicate if reclassify is allowed
+ */
+static bool ecm_classifier_mscs_reclassify_allowed(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_mscs_instance *cmscsi;
+	cmscsi = (struct ecm_classifier_mscs_instance *)ci;
+	DEBUG_CHECK_MAGIC(cmscsi, ECM_CLASSIFIER_MSCS_INSTANCE_MAGIC, "%px: magic failed\n", cmscsi);
+
+	return false;
+}
+
+/*
+ * ecm_classifier_mscs_reclassify()
+ *	Reclassify
+ */
+static void ecm_classifier_mscs_reclassify(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_mscs_instance *cmscsi;
+	cmscsi = (struct ecm_classifier_mscs_instance *)ci;
+	DEBUG_CHECK_MAGIC(cmscsi, ECM_CLASSIFIER_MSCS_INSTANCE_MAGIC, "%px: magic failed\n", cmscsi);
+
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_classifier_mscs_state_get()
+ *	Return state
+ */
+static int ecm_classifier_mscs_state_get(struct ecm_classifier_instance *ci, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	struct ecm_classifier_mscs_instance *cmscsi;
+	struct ecm_classifier_process_response process_response;
+
+	cmscsi = (struct ecm_classifier_mscs_instance *)ci;
+	DEBUG_CHECK_MAGIC(cmscsi, ECM_CLASSIFIER_MSCS_INSTANCE_MAGIC, "%px: magic failed", cmscsi);
+
+	if ((result = ecm_state_prefix_add(sfi, "mscs"))) {
+		return result;
+	}
+
+	spin_lock_bh(&ecm_classifier_mscs_lock);
+	process_response = cmscsi->process_response;
+	spin_unlock_bh(&ecm_classifier_mscs_lock);
+
+	/*
+	 * Output our last process response
+	 */
+	if ((result = ecm_classifier_process_response_state_get(sfi, &process_response))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+/*
+ * ecm_classifier_mscs_instance_alloc()
+ *	Allocate an instance of the mscs classifier
+ */
+struct ecm_classifier_mscs_instance *ecm_classifier_mscs_instance_alloc(struct ecm_db_connection_instance *ci)
+{
+	struct ecm_classifier_mscs_instance *cmscsi;
+
+	/*
+	 * Allocate the instance
+	 */
+	cmscsi = (struct ecm_classifier_mscs_instance *)kzalloc(sizeof(struct ecm_classifier_mscs_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!cmscsi) {
+		DEBUG_WARN("Failed to allocate mscs instance\n");
+		return NULL;
+	}
+
+	DEBUG_SET_MAGIC(cmscsi, ECM_CLASSIFIER_MSCS_INSTANCE_MAGIC);
+	cmscsi->refs = 1;
+	cmscsi->base.process = ecm_classifier_mscs_process;
+	cmscsi->base.sync_from_v4 = ecm_classifier_mscs_sync_from_v4;
+	cmscsi->base.sync_to_v4 = ecm_classifier_mscs_sync_to_v4;
+	cmscsi->base.sync_from_v6 = ecm_classifier_mscs_sync_from_v6;
+	cmscsi->base.sync_to_v6 = ecm_classifier_mscs_sync_to_v6;
+	cmscsi->base.type_get = ecm_classifier_mscs_type_get;
+	cmscsi->base.last_process_response_get = ecm_classifier_mscs_last_process_response_get;
+	cmscsi->base.reclassify_allowed = ecm_classifier_mscs_reclassify_allowed;
+	cmscsi->base.reclassify = ecm_classifier_mscs_reclassify;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	cmscsi->base.state_get = ecm_classifier_mscs_state_get;
+#endif
+	cmscsi->base.ref = ecm_classifier_mscs_ref;
+	cmscsi->base.deref = ecm_classifier_mscs_deref;
+	cmscsi->ci_serial = ecm_db_connection_serial_get(ci);
+	cmscsi->process_response.process_actions = 0;
+	cmscsi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_MAYBE;
+
+	spin_lock_bh(&ecm_classifier_mscs_lock);
+
+	/*
+	 * Final check if we are pending termination
+	 */
+	if (ecm_classifier_mscs_terminate_pending) {
+		spin_unlock_bh(&ecm_classifier_mscs_lock);
+		DEBUG_INFO("%px: Terminating\n", ci);
+		kfree(cmscsi);
+		return NULL;
+	}
+
+	/*
+	 * Link the new instance into our list at the head
+	 */
+	cmscsi->next = ecm_classifier_mscs_instances;
+	if (ecm_classifier_mscs_instances) {
+		ecm_classifier_mscs_instances->prev = cmscsi;
+	}
+	ecm_classifier_mscs_instances = cmscsi;
+
+	/*
+	 * Increment stats
+	 */
+	ecm_classifier_mscs_count++;
+	DEBUG_ASSERT(ecm_classifier_mscs_count > 0, "%px: ecm_classifier_mscs_count wrap\n", cmscsi);
+	spin_unlock_bh(&ecm_classifier_mscs_lock);
+
+	DEBUG_INFO("mscs instance alloc: %px\n", cmscsi);
+	return cmscsi;
+}
+EXPORT_SYMBOL(ecm_classifier_mscs_instance_alloc);
+
+/*
+ * ecm_classifier_mscs_rul_get_enabled()
+ */
+static int ecm_classifier_mscs_rule_get_enabled(void *data, u64 *val)
+{
+	*val = ecm_classifier_mscs_enabled;
+
+	return 0;
+}
+
+/*
+ * ecm_classifier_mscs_rule_set_enabled()
+ */
+static int ecm_classifier_mscs_rule_set_enabled(void *data, u64 val)
+{
+	DEBUG_TRACE("ecm_classifier_mscs_enabled = %u\n", (uint32_t)val);
+
+	if ((val != 0) && (val != 1)) {
+		DEBUG_WARN("Invalid value: %u. Valid values are 0 and 1.\n", (uint32_t)val);
+		return -EINVAL;
+	}
+
+	ecm_classifier_mscs_enabled = (uint32_t)val;
+
+	return 0;
+}
+
+/*
+ * Debugfs attribute for Emesh Enabled parameter.
+ */
+DEFINE_SIMPLE_ATTRIBUTE(ecm_classifier_mscs_enabled_fops, ecm_classifier_mscs_rule_get_enabled, ecm_classifier_mscs_rule_set_enabled, "%llu\n");
+
+/*
+ * ecm_interface_ovpn_register
+ */
+int ecm_classifier_mscs_callback_register(struct ecm_classifier_mscs_callbacks *mscs_cb)
+{
+	spin_lock_bh(&ecm_classifier_mscs_lock);
+	if (ecm_mscs.get_peer_priority) {
+		spin_unlock_bh(&ecm_classifier_mscs_lock);
+		DEBUG_ERROR("MSCS callbacks are registered\n");
+		return -1;
+	}
+
+	ecm_mscs.get_peer_priority = mscs_cb->get_peer_priority;
+	spin_unlock_bh(&ecm_classifier_mscs_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_classifier_mscs_callback_register);
+
+/*
+ * ecm_interface_ovpn_unregister
+ */
+void ecm_classifier_mscs_callback_unregister (void)
+{
+	spin_lock_bh(&ecm_classifier_mscs_lock);
+	ecm_mscs.get_peer_priority = NULL;
+	spin_unlock_bh(&ecm_classifier_mscs_lock);
+}
+EXPORT_SYMBOL(ecm_classifier_mscs_callback_unregister);
+
+/*
+ * ecm_classifier_mscs_init()
+ */
+int ecm_classifier_mscs_init(struct dentry *dentry)
+{
+	DEBUG_INFO("mscs classifier Module init\n");
+
+	ecm_classifier_mscs_dentry = debugfs_create_dir("ecm_classifier_mscs", dentry);
+	if (!ecm_classifier_mscs_dentry) {
+		DEBUG_ERROR("Failed to create ecm mscs directory in debugfs\n");
+		return -1;
+	}
+
+	if (!debugfs_create_file("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mscs_dentry,
+				NULL, &ecm_classifier_mscs_enabled_fops)) {
+		DEBUG_ERROR("Failed to create ecm nl classifier enabled file in debugfs\n");
+		debugfs_remove_recursive(ecm_classifier_mscs_dentry);
+		return -1;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_classifier_mscs_init);
+
+/*
+ * ecm_classifier_mscs_exit()
+ */
+void ecm_classifier_mscs_exit(void)
+{
+	DEBUG_INFO("mscs classifier Module exit\n");
+
+	spin_lock_bh(&ecm_classifier_mscs_lock);
+	ecm_classifier_mscs_terminate_pending = true;
+	spin_unlock_bh(&ecm_classifier_mscs_lock);
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_classifier_mscs_dentry) {
+		debugfs_remove_recursive(ecm_classifier_mscs_dentry);
+	}
+}
+EXPORT_SYMBOL(ecm_classifier_mscs_exit);
diff --git a/qca-nss-ecm/ecm_classifier_mscs.h b/qca-nss-ecm/ecm_classifier_mscs.h
new file mode 100644
index 0000000..e6fb35c
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_mscs.h
@@ -0,0 +1,18 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+struct ecm_classifier_mscs_instance;
+struct ecm_classifier_mscs_instance *ecm_classifier_mscs_instance_alloc(struct ecm_db_connection_instance *ci);
diff --git a/qca-nss-ecm/ecm_classifier_nl.c b/qca-nss-ecm/ecm_classifier_nl.c
new file mode 100644
index 0000000..73ae2f1
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_nl.c
@@ -0,0 +1,1511 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2016, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <linux/netfilter/nf_conntrack_zones_common.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+#include <net/genetlink.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_CLASSIFIER_NL_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_classifier_nl.h"
+#include "ecm_db.h"
+#include "ecm_front_end_ipv4.h"
+#ifdef ECM_IPV6_ENABLE
+#include "ecm_front_end_ipv6.h"
+#endif
+
+/*
+ * Magic numbers
+ */
+#define ECM_CLASSIFIER_NL_INSTANCE_MAGIC 0xFE12
+
+#define ECM_CLASSIFIER_NL_F_ACCEL	(1 << 0) /* acceleration requested */
+#define ECM_CLASSIFIER_NL_F_ACCEL_OK	(1 << 1) /* acceleration confirmed */
+#define ECM_CLASSIFIER_NL_F_CLOSED	(1 << 2) /* close event issued */
+
+/*
+ * struct ecm_classifier_nl_instance
+ * 	State to allow tracking of dynamic qos for a connection
+ */
+struct ecm_classifier_nl_instance {
+	struct ecm_classifier_instance base;			/* Base type */
+
+	struct ecm_classifier_nl_instance *next;		/* Next classifier state instance (for accouting and reporting purposes) */
+	struct ecm_classifier_nl_instance *prev;		/* Next classifier state instance (for accouting and reporting purposes) */
+
+	uint32_t ci_serial;					/* RO: Serial of the connection */
+	struct ecm_classifier_process_response process_response;/* Last process response computed */
+	int refs;						/* Integer to trap we never go negative */
+	unsigned int flags;					/* See ECM_CLASSIFIER_NL_F_* */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+/*
+ * Operational control
+ */
+static bool ecm_classifier_nl_enabled = false;		/* Operational behaviour */
+
+/*
+ * Management thread control
+ */
+static bool ecm_classifier_nl_terminate_pending = false;		/* True when the user wants us to terminate */
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_classifier_nl_dentry;
+
+/*
+ * Locking of the classifier structures
+ */
+static DEFINE_SPINLOCK(ecm_classifier_nl_lock);			/* Protect SMP access. */
+
+/*
+ * List of our classifier instances
+ */
+static struct ecm_classifier_nl_instance *ecm_classifier_nl_instances = NULL;
+									/* list of all active instances */
+static int ecm_classifier_nl_count = 0;					/* Tracks number of instances allocated */
+
+/*
+ * Listener for db events
+ */
+struct ecm_db_listener_instance *ecm_classifier_nl_li = NULL;
+
+/*
+ * Generic Netlink family and multicast group names
+ */
+static struct genl_multicast_group ecm_cl_nl_genl_mcgrp[] = {
+	{
+		.name = ECM_CL_NL_GENL_MCGRP,
+	},
+};
+
+static struct genl_family ecm_cl_nl_genl_family = {
+	.id = GENL_ID_GENERATE,
+	.hdrsize = 0,
+	.name = ECM_CL_NL_GENL_NAME,
+	.version = ECM_CL_NL_GENL_VERSION,
+	.maxattr = ECM_CL_NL_GENL_ATTR_MAX,
+};
+
+/*
+ * helper for sending basic genl commands requiring only a tuple attribute
+ *
+ * TODO: implement a message queue serviced by a thread to allow automatic
+ *	 retries for accel_ok and closed messages.
+ */
+static int
+ecm_classifier_nl_send_genl_msg(enum ECM_CL_NL_GENL_CMD cmd,
+				struct ecm_cl_nl_genl_attr_tuple *tuple)
+{
+	int ret;
+	int buf_len;
+	int total_len;
+	void *msg_head;
+	struct sk_buff *skb;
+
+	/*
+	 * Calculate our packet payload size.
+	 * Start with our family header.
+	 */
+	buf_len = ecm_cl_nl_genl_family.hdrsize;
+
+	/*
+	 * Add the nla_total_size of each attribute we're going to nla_put().
+	 */
+	buf_len += nla_total_size(sizeof(*tuple));
+
+	/*
+	 * Lastly we need to add space for the NL message header since
+	 * genlmsg_new only accounts for the GENL header and not the
+	 * outer NL header. To do this, we use a NL helper function which
+	 * calculates the total size of a netlink message given a payload size.
+	 * Note this value does not include the GENL header, but that's
+	 * added automatically by genlmsg_new.
+	 */
+	total_len = nlmsg_total_size(buf_len);
+	skb = genlmsg_new(total_len, GFP_ATOMIC);
+	if (!skb) {
+		DEBUG_WARN("failed to alloc nlmsg\n");
+		return -ENOMEM;
+	}
+
+	msg_head = genlmsg_put(skb,
+			       0, /* netlink PID */
+			       0, /* sequence number */
+			       &ecm_cl_nl_genl_family,
+			       0, /* flags */
+			       cmd);
+	if (!msg_head) {
+		DEBUG_WARN("failed to add genl headers\n");
+		nlmsg_free(skb);
+		return -ENOMEM;
+	}
+
+	ret = nla_put(skb, ECM_CL_NL_GENL_ATTR_TUPLE, sizeof(*tuple), tuple);
+	if (ret != 0) {
+		DEBUG_WARN("failed to put tuple into genl msg: %d\n", ret);
+		nlmsg_free(skb);
+		return ret;
+	}
+
+	ret = genlmsg_end(skb, msg_head);
+	if (ret < 0) {
+		DEBUG_WARN("failed to finalize genl msg: %d\n", ret);
+		nlmsg_free(skb);
+		return ret;
+	}
+
+	/* genlmsg_multicast frees the skb in both success and error cases */
+	ret = genlmsg_multicast(&ecm_cl_nl_genl_family,
+				skb,
+				0,
+				0,
+				GFP_ATOMIC);
+	if (ret != 0) {
+		DEBUG_WARN("genl multicast failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+/*
+ * ecm_cl_nl_genl_attr_tuple_encode()
+ *	Helper function to convert connection IP info into a genl_attr_tuple
+ */
+static int ecm_cl_nl_genl_attr_tuple_encode(struct ecm_cl_nl_genl_attr_tuple *tuple,
+				 int ip_version,
+				 int proto,
+				 ip_addr_t src_ip,
+				 int src_port,
+				 ip_addr_t dst_ip,
+				 int dst_port)
+{
+	memset(tuple, 0, sizeof(*tuple));
+	tuple->proto = (uint8_t)proto;
+	tuple->src_port = htons((uint16_t)src_port);
+	tuple->dst_port = htons((uint16_t)dst_port);
+	if (ip_version == 4) {
+		tuple->af = AF_INET;
+		ECM_IP_ADDR_TO_NIN4_ADDR(tuple->src_ip.in.s_addr, src_ip);
+		ECM_IP_ADDR_TO_NIN4_ADDR(tuple->dst_ip.in.s_addr, dst_ip);
+		return 0;
+	}
+#ifdef ECM_IPV6_ENABLE
+	if (ip_version == 6) {
+		tuple->af = AF_INET6;
+		ECM_IP_ADDR_TO_NIN6_ADDR(tuple->src_ip.in6, src_ip);
+		ECM_IP_ADDR_TO_NIN6_ADDR(tuple->dst_ip.in6, dst_ip);
+		return 0;
+	}
+#endif
+	return -EAFNOSUPPORT;
+}
+
+/*
+ * ecm_cl_nl_genl_attr_tuple_decode()
+ *	Helper function to convert a genl_attr_tuple into connection IP info
+ */
+static int ecm_cl_nl_genl_attr_tuple_decode(struct ecm_cl_nl_genl_attr_tuple *tuple,
+				 int *proto,
+				 ip_addr_t src_ip,
+				 int *src_port,
+				 ip_addr_t dst_ip,
+				 int *dst_port)
+{
+	*proto = tuple->proto;
+	*src_port = ntohs(tuple->src_port);
+	*dst_port = ntohs(tuple->dst_port);
+	if (AF_INET == tuple->af) {
+		ECM_NIN4_ADDR_TO_IP_ADDR(src_ip, tuple->src_ip.in.s_addr);
+		ECM_NIN4_ADDR_TO_IP_ADDR(dst_ip, tuple->dst_ip.in.s_addr);
+		return 0;
+	}
+#ifdef ECM_IPV6_ENABLE
+	if (AF_INET6 == tuple->af) {
+		ECM_NIN6_ADDR_TO_IP_ADDR(src_ip, tuple->src_ip.in6);
+		ECM_NIN6_ADDR_TO_IP_ADDR(dst_ip, tuple->dst_ip.in6);
+		return 0;
+	}
+#endif
+	return -EAFNOSUPPORT;
+}
+
+/*
+ * ecm_classifier_nl_genl_msg_ACCEL_OK()
+ *	Indicates that Accelleration is okay to the netlink channel
+ */
+static void ecm_classifier_nl_genl_msg_ACCEL_OK(struct ecm_classifier_nl_instance *cnli)
+{
+	struct ecm_db_connection_instance *ci;
+	int ret;
+	int ip_version;
+	int proto;
+	int src_port;
+	int dst_port;
+	ip_addr_t src_ip;
+	ip_addr_t dst_ip;
+	struct ecm_cl_nl_genl_attr_tuple tuple;
+
+	/*
+	 * Lookup the associated connection
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(cnli->ci_serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: No ci found for %u\n", cnli, cnli->ci_serial);
+		return;
+	}
+
+	spin_lock_bh(&ecm_classifier_nl_lock);
+
+	/* if we've already issued an ACCEL_OK on this connection,
+	   do not send it again */
+	if (cnli->flags & ECM_CLASSIFIER_NL_F_ACCEL_OK) {
+		spin_unlock_bh(&ecm_classifier_nl_lock);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+
+	proto = ecm_db_connection_protocol_get(ci);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	src_port = (uint16_t)ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+	dst_port = ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO);
+
+	ip_version = ecm_db_connection_ip_version_get(ci);
+	ecm_db_connection_deref(ci);
+
+	ret = ecm_cl_nl_genl_attr_tuple_encode(&tuple,
+						ip_version,
+						proto,
+						src_ip,
+						src_port,
+						dst_ip,
+						dst_port);
+	if (ret != 0) {
+		DEBUG_WARN("failed to encode genl_attr_tuple: %d\n", ret);
+		return;
+	}
+
+	ret = ecm_classifier_nl_send_genl_msg(ECM_CL_NL_GENL_CMD_ACCEL_OK,
+					      &tuple);
+	if (ret != 0) {
+		DEBUG_WARN("failed to send ACCEL_OK: %px, serial %u\n",
+			   cnli, cnli->ci_serial);
+		return;
+	}
+
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	cnli->flags |= ECM_CLASSIFIER_NL_F_ACCEL_OK;
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+}
+
+/*
+ * ecm_classifier_nl_genl_msg_closed()
+ *	Invoke this when the connection has been closed and it has been accelerated previously.
+ *
+ * GGG TODO The purpose of this is not clear, esp. wrt. "accel ok" message.
+ * DO NOT CALL THIS UNLESS ECM_CLASSIFIER_NL_F_ACCEL_OK has been set.
+ */
+static void ecm_classifier_nl_genl_msg_closed(struct ecm_db_connection_instance *ci, struct ecm_classifier_nl_instance *cnli,
+					int proto, ip_addr_t src_ip, ip_addr_t dst_ip, int src_port, int dst_port)
+{
+	int ip_version;
+	int ret;
+	struct ecm_cl_nl_genl_attr_tuple tuple;
+
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	cnli->flags |= ECM_CLASSIFIER_NL_F_CLOSED;
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+
+	ip_version = ecm_db_connection_ip_version_get(ci);
+	ret = ecm_cl_nl_genl_attr_tuple_encode(&tuple,
+						ip_version,
+						proto,
+						src_ip,
+						src_port,
+						dst_ip,
+						dst_port);
+	if (ret != 0) {
+		DEBUG_WARN("failed to encode genl_attr_tuple: %d\n", ret);
+		return;
+	}
+
+	ecm_classifier_nl_send_genl_msg(ECM_CL_NL_GENL_CMD_CONNECTION_CLOSED, &tuple);
+}
+
+/*
+ * ignore ecm_classifier_messages ACCEL_OK and CLOSED
+ */
+static int ecm_classifier_nl_genl_msg_DUMP(struct sk_buff *skb,
+					   struct netlink_callback *cb)
+{
+	return 0;
+}
+
+/*
+ * ecm_classifier_nl_genl_msg_ACCEL()
+ *	handles a ECM_CL_NL_ACCEL message
+ */
+static int ecm_classifier_nl_genl_msg_ACCEL(struct sk_buff *skb,
+					    struct genl_info *info)
+{
+	int ret;
+	struct nlattr *na;
+	struct ecm_cl_nl_genl_attr_tuple *tuple;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_classifier_nl_instance *cnli;
+
+	/* the netlink message comes to us in network order, but ECM
+	   stores addresses in host order */
+	int proto;
+	int src_port;
+	int dst_port;
+	ip_addr_t src_ip;
+	ip_addr_t dst_ip;
+
+	/*
+	 * Check if we are enabled
+	 */
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	if (!ecm_classifier_nl_enabled) {
+		spin_unlock_bh(&ecm_classifier_nl_lock);
+		return -ECONNREFUSED;
+	}
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+
+	na = info->attrs[ECM_CL_NL_GENL_ATTR_TUPLE];
+	tuple = nla_data(na);
+
+	ret = ecm_cl_nl_genl_attr_tuple_decode(tuple,
+					       &proto,
+					       src_ip,
+					       &src_port,
+					       dst_ip,
+					       &dst_port);
+	if (ret != 0) {
+		DEBUG_WARN("failed to decode genl_attr_tuple: %d\n", ret);
+		return ret;
+	}
+
+	/*
+	 * Locate the connection using the tuple given
+	 */
+	DEBUG_TRACE("ACCEL: Lookup connection "
+		    ECM_IP_ADDR_OCTAL_FMT ":%d <> "
+		    ECM_IP_ADDR_OCTAL_FMT ":%d "
+		    "protocol %d\n",
+		    ECM_IP_ADDR_TO_OCTAL(src_ip),
+		    src_port,
+		    ECM_IP_ADDR_TO_OCTAL(dst_ip),
+		    dst_port,
+		    tuple->proto);
+	ci = ecm_db_connection_find_and_ref(src_ip,
+					    dst_ip,
+					    proto,
+					    src_port,
+					    dst_port);
+	if (!ci) {
+		DEBUG_WARN("database connection not found\n");
+		return -ENOENT;
+	}
+	DEBUG_TRACE("Connection found: %px\n", ci);
+
+	/*
+	 * Get the NL classifier for this connection
+	 */
+	cnli = (struct ecm_classifier_nl_instance *)
+		ecm_db_connection_assigned_classifier_find_and_ref(ci,
+			ECM_CLASSIFIER_TYPE_NL);
+	if (!cnli) {
+		ecm_db_connection_deref(ci);
+		return -EUNATCH;
+	}
+
+	/*
+	 * Allow acceleration of the connection.  This will be done as
+	 * packets are processed in the usual way.
+	 */
+	DEBUG_TRACE("Permit accel: %px\n", ci);
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	cnli->process_response.accel_mode =
+		ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+	cnli->flags |= ECM_CLASSIFIER_NL_F_ACCEL;
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+
+	cnli->base.deref((struct ecm_classifier_instance *)cnli);
+	ecm_db_connection_deref(ci);
+
+	return 0;
+}
+
+/*
+ * ecm_classifier_nl_ref()
+ *	Ref
+ */
+static void ecm_classifier_nl_ref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_nl_instance *cnli;
+	cnli = (struct ecm_classifier_nl_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(cnli, ECM_CLASSIFIER_NL_INSTANCE_MAGIC, "%px: magic failed\n", cnli);
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	cnli->refs++;
+	DEBUG_TRACE("%px: cnli ref %d\n", cnli, cnli->refs);
+	DEBUG_ASSERT(cnli->refs > 0, "%px: ref wrap\n", cnli);
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+}
+
+/*
+ * ecm_classifier_nl_deref()
+ *	Deref
+ */
+static int ecm_classifier_nl_deref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_nl_instance *cnli;
+	cnli = (struct ecm_classifier_nl_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(cnli, ECM_CLASSIFIER_NL_INSTANCE_MAGIC, "%px: magic failed\n", cnli);
+
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	cnli->refs--;
+	DEBUG_ASSERT(cnli->refs >= 0, "%px: refs wrapped\n", cnli);
+	DEBUG_TRACE("%px: Netlink classifier deref %d\n", cnli, cnli->refs);
+	if (cnli->refs) {
+		int refs = cnli->refs;
+		spin_unlock_bh(&ecm_classifier_nl_lock);
+		return refs;
+	}
+
+	/*
+	 * Object to be destroyed
+	 */
+	ecm_classifier_nl_count--;
+	DEBUG_ASSERT(ecm_classifier_nl_count >= 0, "%px: ecm_classifier_nl_count wrap\n", cnli);
+
+	/*
+	 * UnLink the instance from our list
+	 */
+	if (cnli->next) {
+		cnli->next->prev = cnli->prev;
+	}
+	if (cnli->prev) {
+		cnli->prev->next = cnli->next;
+	} else {
+		DEBUG_ASSERT(ecm_classifier_nl_instances == cnli, "%px: list bad %px\n", cnli, ecm_classifier_nl_instances);
+		ecm_classifier_nl_instances = cnli->next;
+	}
+	cnli->next = NULL;
+	cnli->prev = NULL;
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+
+	/*
+	 * Final
+	 */
+	DEBUG_INFO("%px: Final Netlink classifier instance\n", cnli);
+	kfree(cnli);
+
+	return 0;
+}
+
+#if defined(CONFIG_NF_CONNTRACK_MARK)
+void
+ecm_classifier_nl_process_mark(struct ecm_classifier_nl_instance *cnli,
+			       uint32_t mark)
+{
+	bool updated;
+	ecm_front_end_acceleration_mode_t accel_mode;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+
+	updated = false;
+
+	spin_lock_bh(&ecm_classifier_nl_lock);
+
+	/*
+	 * If the mark is different to either of the current flow or return qos tags then we override them.
+	 * NOTE: This will force a change of the skb priority and also drive through these qos tags in any acceleration rule.
+	 */
+	if ((mark != cnli->process_response.flow_qos_tag) || (mark != cnli->process_response.return_qos_tag)) {
+		cnli->process_response.flow_qos_tag = mark;
+		cnli->process_response.return_qos_tag = mark;
+		cnli->process_response.process_actions |=
+			ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG;
+		updated = true;
+	}
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+
+	if (!updated) {
+		return;
+	}
+
+	/*
+	 * we need to make sure to propagate the new mark to the
+	 * accel engine if the connection has been accelerated.  to do that,
+	 * since there's no way to directly update an offload rule,
+	 * we simply decelerate the connection which should result
+	 * in a re-acceleration when the next packet is processed
+	 * by the front end, thereby applying the new mark.
+	 */
+
+	/*
+	 * Lookup the associated connection
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(cnli->ci_serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: No ci found for %u\n", cnli, cnli->ci_serial);
+		return;
+	}
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	accel_mode = feci->accel_state_get(feci);
+	if ((accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL)
+			|| (accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING)) {
+		DEBUG_TRACE("%px: mark changed on offloaded connection, decelerate. new mark: 0x%08x\n",
+			    cnli, mark);
+		feci->decelerate(feci);
+	} else {
+		DEBUG_TRACE("%px: mark changed on non-offloaded connection. new mark: 0x%08x\n",
+			    cnli, mark);
+	}
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+EXPORT_SYMBOL(ecm_classifier_nl_process_mark);
+#endif
+
+/*
+ * ecm_classifier_nl_process()
+ *	Process new data for connection
+ */
+static void ecm_classifier_nl_process(struct ecm_classifier_instance *aci, ecm_tracker_sender_type_t sender,
+						struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb,
+						struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_nl_instance *cnli;
+	ecm_classifier_relevence_t relevance;
+	bool enabled;
+	struct ecm_db_connection_instance *ci;
+	ecm_front_end_acceleration_mode_t accel_mode;
+	uint32_t became_relevant = 0;
+
+	cnli = (struct ecm_classifier_nl_instance *)aci;
+	DEBUG_CHECK_MAGIC(cnli, ECM_CLASSIFIER_NL_INSTANCE_MAGIC, "%px: magic failed\n", cnli);
+
+	/*
+	 * Have we decided our relevance?  If so return our state.
+	 */
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	relevance = cnli->process_response.relevance;
+	if (relevance != ECM_CLASSIFIER_RELEVANCE_MAYBE) {
+		*process_response = cnli->process_response;
+		spin_unlock_bh(&ecm_classifier_nl_lock);
+		return;
+	}
+
+	/*
+	 * Decide upon relevance
+	 */
+	enabled = ecm_classifier_nl_enabled;
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+
+	/*
+	 * If classifier is enabled, the connection is routed and the front end says it can accel then we are "relevant".
+	 * Any other condition and we are not and will stop analysing this connection.
+	 */
+	relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+	ci = ecm_db_connection_serial_find_and_ref(cnli->ci_serial);
+	if (ci) {
+		struct ecm_front_end_connection_instance *feci;
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+		accel_mode = feci->accel_state_get(feci);
+		feci->deref(feci);
+		if (enabled && ECM_FRONT_END_ACCELERATION_POSSIBLE(accel_mode) && ecm_db_connection_is_routed_get(ci)) {
+			relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+			became_relevant = ecm_db_time_get();
+		}
+		ecm_db_connection_deref(ci);
+	}
+
+	/*
+	 * Return process response
+	 */
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	cnli->process_response.relevance = relevance;
+	cnli->process_response.became_relevant = became_relevant;
+	*process_response = cnli->process_response;
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+}
+
+/*
+ * ecm_classifier_nl_sync_to_v4()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_nl_sync_to_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	struct ecm_classifier_nl_instance *cnli;
+
+	if (!(sync->tx_packet_count[ECM_CONN_DIR_FLOW] || sync->tx_packet_count[ECM_CONN_DIR_RETURN])) {
+		/*
+		 * Nothing to update.
+		 * We only care about flows that are actively being accelerated.
+		 */
+		return;
+	}
+
+	cnli = (struct ecm_classifier_nl_instance *)aci;
+	DEBUG_CHECK_MAGIC(cnli, ECM_CLASSIFIER_NL_INSTANCE_MAGIC, "%px: magic failed", cnli);
+
+	switch(sync->reason) {
+	case ECM_FRONT_END_IPV4_RULE_SYNC_REASON_FLUSH:
+		/* do nothing */
+		DEBUG_TRACE("%px: nl_sync_to_v4: SYNC_FLUSH\n", cnli);
+		break;
+	case ECM_FRONT_END_IPV4_RULE_SYNC_REASON_EVICT:
+		/* do nothing */
+		DEBUG_TRACE("%px: nl_sync_to_v4: SYNC_EVICT\n", cnli);
+		break;
+	case ECM_FRONT_END_IPV4_RULE_SYNC_REASON_DESTROY:
+		DEBUG_TRACE("%px: nl_sync_to_v4: SYNC_DESTROY\n", cnli);
+		break;
+	case ECM_FRONT_END_IPV4_RULE_SYNC_REASON_STATS:
+		DEBUG_TRACE("%px: nl_sync_to_v4: SYNC_STATS\n", cnli);
+		ecm_classifier_nl_genl_msg_ACCEL_OK(cnli);
+		break;
+	default:
+		DEBUG_TRACE("%px: nl_sync_to_v4: unsupported reason\n", cnli);
+		break;
+	}
+}
+
+/*
+ * ecm_classifier_nl_sync_from_v4()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_nl_sync_from_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_nl_instance *cnli;
+
+	cnli = (struct ecm_classifier_nl_instance *)aci;
+	DEBUG_CHECK_MAGIC(cnli, ECM_CLASSIFIER_NL_INSTANCE_MAGIC, "%px: magic failed", cnli);
+}
+
+/*
+ * ecm_classifier_nl_sync_to_v6()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_nl_sync_to_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	struct ecm_classifier_nl_instance *cnli;
+
+	cnli = (struct ecm_classifier_nl_instance *)aci;
+	DEBUG_CHECK_MAGIC(cnli, ECM_CLASSIFIER_NL_INSTANCE_MAGIC, "%px: magic failed", cnli);
+
+	if (!(sync->tx_packet_count[ECM_CONN_DIR_FLOW] || sync->tx_packet_count[ECM_CONN_DIR_RETURN])) {
+		/*
+		 * No traffic has been accelerated.
+		 * Nothing to update. We only care about flows that are actively being accelerated.
+		 */
+		DEBUG_TRACE("%px: No traffic\n", cnli);
+		return;
+	}
+
+	/*
+	 * If this sync does NOT contain a final sync then we have seen traffic
+	 * and that acceleration is continuing - acceleration is OK
+	 */
+	switch(sync->reason) {
+	case ECM_FRONT_END_IPV6_RULE_SYNC_REASON_FLUSH:
+		/* do nothing */
+		DEBUG_TRACE("%px: nl_sync_to_v6: SYNC_FLUSH\n", cnli);
+		break;
+	case ECM_FRONT_END_IPV6_RULE_SYNC_REASON_EVICT:
+		/* do nothing */
+		DEBUG_TRACE("%px: nl_sync_to_v6: SYNC_EVICT\n", cnli);
+		break;
+	case ECM_FRONT_END_IPV6_RULE_SYNC_REASON_DESTROY:
+		/* do nothing */
+		DEBUG_TRACE("%px: nl_sync_to_v6: SYNC_DESTROY\n", cnli);
+		break;
+	case ECM_FRONT_END_IPV6_RULE_SYNC_REASON_STATS:
+		DEBUG_TRACE("%px: nl_sync_to_v6: SYNC_STATS\n", cnli);
+		ecm_classifier_nl_genl_msg_ACCEL_OK(cnli);
+		break;
+	default:
+		DEBUG_TRACE("%px: nl_sync_to_v6: unsupported reason\n", cnli);
+		break;
+	}
+}
+
+/*
+ * ecm_classifier_nl_sync_from_v6()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_nl_sync_from_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_nl_instance *cnli;
+
+	cnli = (struct ecm_classifier_nl_instance *)aci;
+	DEBUG_CHECK_MAGIC(cnli, ECM_CLASSIFIER_NL_INSTANCE_MAGIC, "%px: magic failed", cnli);
+
+}
+
+/*
+ * ecm_classifier_nl_type_get()
+ *	Get type of classifier this is
+ */
+static ecm_classifier_type_t ecm_classifier_nl_type_get(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_nl_instance *cnli;
+	cnli = (struct ecm_classifier_nl_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(cnli, ECM_CLASSIFIER_NL_INSTANCE_MAGIC, "%px: magic failed\n", cnli);
+	return ECM_CLASSIFIER_TYPE_NL;
+}
+
+/*
+ * ecm_classifier_nl_last_process_response_get()
+ *	Get result code returned by the last process call
+ */
+static void ecm_classifier_nl_last_process_response_get(struct ecm_classifier_instance *ci,
+							struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_nl_instance *cnli;
+
+	cnli = (struct ecm_classifier_nl_instance *)ci;
+	DEBUG_CHECK_MAGIC(cnli, ECM_CLASSIFIER_NL_INSTANCE_MAGIC, "%px: magic failed\n", cnli);
+
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	*process_response = cnli->process_response;
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+}
+
+/*
+ * ecm_classifier_nl_reclassify_allowed()
+ *	Indicate if reclassify is allowed
+ */
+static bool ecm_classifier_nl_reclassify_allowed(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_nl_instance *cnli;
+	cnli = (struct ecm_classifier_nl_instance *)ci;
+	DEBUG_CHECK_MAGIC(cnli, ECM_CLASSIFIER_NL_INSTANCE_MAGIC, "%px: magic failed\n", cnli);
+
+	return true;
+}
+
+/*
+ * ecm_classifier_nl_reclassify()
+ *	Reclassify
+ */
+static void ecm_classifier_nl_reclassify(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_nl_instance *cnli;
+	cnli = (struct ecm_classifier_nl_instance *)ci;
+	DEBUG_CHECK_MAGIC(cnli, ECM_CLASSIFIER_NL_INSTANCE_MAGIC, "%px: magic failed\n", cnli);
+
+	/*
+	 * Revert back to MAYBE relevant - we will evaluate when we get the next process() call.
+	 */
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	cnli->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_MAYBE;
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_classifier_nl_state_get()
+ *	Return state
+ */
+static int ecm_classifier_nl_state_get(struct ecm_classifier_instance *ci, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	struct ecm_classifier_nl_instance *cnli;
+	struct ecm_classifier_process_response process_response;
+
+	cnli = (struct ecm_classifier_nl_instance *)ci;
+	DEBUG_CHECK_MAGIC(cnli, ECM_CLASSIFIER_NL_INSTANCE_MAGIC, "%px: magic failed", cnli);
+
+	if ((result = ecm_state_prefix_add(sfi, "nl"))) {
+		return result;
+	}
+
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	process_response = cnli->process_response;
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+
+	/*
+	 * Output our last process response
+	 */
+	if ((result = ecm_classifier_process_response_state_get(sfi, &process_response))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+/*
+ * ecm_classifier_nl_ct_get_and_ref()
+ * 	Returns the conntrack entry for an ecm_db_connection_instance.
+ * @param ci The connection instance to be used for the conntrack search.
+ * @return struct nf_conn * A pointer and a reference to a matching conntrack
+ *                          entry, or NULL if no such entry is found.
+ * @pre The ci instance is not NULL.
+ * @note This function takes a reference to the associated conntrack entry if
+ *       it is found, and the caller must nf_ct_put() this entry when done.
+ * @note FIXME: The param ci should be const, but none of the called functions
+ *       are declared const.  This would be a larger change.
+ */
+static struct nf_conn *ecm_classifier_nl_ct_get_and_ref(struct ecm_db_connection_instance *ci)
+{
+	int ip_version;
+	int proto;
+	int src_port;
+	int dst_port;
+	ip_addr_t src_ip;
+	ip_addr_t dst_ip;
+	struct nf_conntrack_tuple_hash *h;
+	struct nf_conntrack_tuple tuple = {};
+
+	DEBUG_ASSERT(ci != NULL, "ci was NULL for ct lookup");
+	ip_version = ecm_db_connection_ip_version_get(ci);
+	proto = ecm_db_connection_protocol_get(ci);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	src_port = (uint16_t)ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO_NAT, dst_ip);
+	dst_port = (uint16_t)ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO_NAT);
+
+	if (ip_version == 4) {
+		tuple.src.l3num = AF_INET;
+		ECM_IP_ADDR_TO_NIN4_ADDR(tuple.src.u3.ip, src_ip);
+		ECM_IP_ADDR_TO_NIN4_ADDR(tuple.dst.u3.ip, dst_ip);
+		goto ip_check_done;
+	}
+#ifdef ECM_IPV6_ENABLE
+	if (ip_version == 6) {
+		tuple.src.l3num = AF_INET6;
+		ECM_IP_ADDR_TO_NIN6_ADDR(tuple.src.u3.in6, src_ip);
+		ECM_IP_ADDR_TO_NIN6_ADDR(tuple.dst.u3.in6, dst_ip);
+		goto ip_check_done;
+	}
+#endif
+	return NULL;
+
+ip_check_done:
+	tuple.dst.protonum = proto;
+	tuple.src.u.all = htons(src_port);
+	tuple.dst.u.all = htons(dst_port);
+
+	h = nf_conntrack_find_get(&init_net, &nf_ct_zone_dflt, &tuple);
+	if (!h) {
+		return NULL;
+	}
+
+	return nf_ct_tuplehash_to_ctrack(h);
+}
+
+/*
+ * ecm_classifier_nl_connection_added()
+ *	Invoked when a connection is added to the DB
+ */
+static void ecm_classifier_nl_connection_added(void *arg, struct ecm_db_connection_instance *ci)
+{
+	struct nf_conn *ct;
+	struct ecm_classifier_instance *classi;
+	struct ecm_classifier_nl_instance *cnli;
+	uint32_t serial __attribute__((unused)) = ecm_db_connection_serial_get(ci);
+	DEBUG_INFO("%px: NL Listener: conn added with serial: %u\n", ci, serial);
+
+	/*
+	 * Only handle events if there is an NL classifier attached
+	 */
+	classi = ecm_db_connection_assigned_classifier_find_and_ref(ci, ECM_CLASSIFIER_TYPE_NL);
+	if (!classi) {
+		DEBUG_TRACE("%px: Connection added ignored - no NL classifier\n", ci);
+		return;
+	}
+	cnli = (struct ecm_classifier_nl_instance *)classi;
+	DEBUG_TRACE("%px: added conn, serial: %u, NL classifier: %px\n", ci,
+		    serial, classi);
+
+	ct = ecm_classifier_nl_ct_get_and_ref(ci);
+	if (!ct) {
+		DEBUG_TRACE("%px: Connection add skipped - no associated CT entry.\n", ci);
+		goto classi;
+	}
+	DEBUG_TRACE("%px: added conn, serial: %u, NL classifier: %px, CT: %px\n",
+		    ci, serial, classi, ct);
+
+#if defined(CONFIG_NF_CONNTRACK_MARK)
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	cnli->process_response.flow_qos_tag = ct->mark;
+	cnli->process_response.return_qos_tag = ct->mark;
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+#endif
+	nf_ct_put(ct);
+
+classi:
+	classi->deref(classi);
+
+	return;
+}
+
+/*
+ * ecm_classifier_nl_connection_removed()
+ *	Invoked when a connection is removed from the DB
+ */
+static void ecm_classifier_nl_connection_removed(void *arg, struct ecm_db_connection_instance *ci)
+{
+	uint32_t serial __attribute__((unused)) = ecm_db_connection_serial_get(ci);
+	struct ecm_classifier_instance *classi;
+	struct ecm_classifier_nl_instance *cnli;
+	bool accel_ok;
+	int proto;
+	int src_port;
+	int dst_port;
+	ip_addr_t src_ip;
+	ip_addr_t dst_ip;
+
+	DEBUG_INFO("%px: NL Listener: conn removed with serial: %u\n", ci, serial);
+
+	/*
+	 * Only handle events if there is an NL classifier attached
+	 */
+	classi = ecm_db_connection_assigned_classifier_find_and_ref(ci, ECM_CLASSIFIER_TYPE_NL);
+	if (!classi) {
+		DEBUG_TRACE("%px: Connection removed ignored - no NL classifier\n", ci);
+		return;
+	}
+
+	cnli = (struct ecm_classifier_nl_instance *)classi;
+	DEBUG_INFO("%px: removed conn with serial: %u, NL classifier: %px\n", ci, serial, cnli);
+
+	/*
+	 * If the connection was accelerated OK then issue a close
+	 */
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	accel_ok = (cnli->flags & ECM_CLASSIFIER_NL_F_ACCEL_OK)? true : false;
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+	if (!accel_ok) {
+		DEBUG_INFO("%px: cnli: %px, accel not ok\n", ci, cnli);
+		classi->deref(classi);
+		return;
+	}
+
+	proto = ecm_db_connection_protocol_get(ci);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	src_port = (uint16_t)ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+	dst_port = ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO);
+
+	DEBUG_INFO("%px: NL classifier: %px, issue Close\n", ci, cnli);
+	ecm_classifier_nl_genl_msg_closed(ci, cnli, proto, src_ip, dst_ip, src_port, dst_port);
+
+	classi->deref(classi);
+}
+
+/*
+ * ecm_classifier_nl_instance_alloc()
+ *	Allocate an instance of the Netlink classifier
+ */
+struct ecm_classifier_nl_instance *ecm_classifier_nl_instance_alloc(struct ecm_db_connection_instance *ci)
+{
+	struct ecm_classifier_nl_instance *cnli;
+
+	/*
+	 * Allocate the instance
+	 */
+	cnli = (struct ecm_classifier_nl_instance *)kzalloc(sizeof(struct ecm_classifier_nl_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!cnli) {
+		DEBUG_WARN("Failed to allocate Netlink instance\n");
+		return NULL;
+	}
+
+	DEBUG_SET_MAGIC(cnli, ECM_CLASSIFIER_NL_INSTANCE_MAGIC);
+	cnli->refs = 1;
+	cnli->base.process = ecm_classifier_nl_process;
+	cnli->base.sync_from_v4 = ecm_classifier_nl_sync_from_v4;
+	cnli->base.sync_to_v4 = ecm_classifier_nl_sync_to_v4;
+	cnli->base.sync_from_v6 = ecm_classifier_nl_sync_from_v6;
+	cnli->base.sync_to_v6 = ecm_classifier_nl_sync_to_v6;
+	cnli->base.type_get = ecm_classifier_nl_type_get;
+	cnli->base.last_process_response_get = ecm_classifier_nl_last_process_response_get;
+	cnli->base.reclassify_allowed = ecm_classifier_nl_reclassify_allowed;
+	cnli->base.reclassify = ecm_classifier_nl_reclassify;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	cnli->base.state_get = ecm_classifier_nl_state_get;
+#endif
+	cnli->base.ref = ecm_classifier_nl_ref;
+	cnli->base.deref = ecm_classifier_nl_deref;
+	cnli->ci_serial = ecm_db_connection_serial_get(ci);
+
+	/*
+	 * Classifier initially denies acceleration.
+	 */
+	cnli->process_response.flow_qos_tag = 0;
+	cnli->process_response.return_qos_tag = 0;
+	cnli->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_MAYBE;
+	cnli->process_response.process_actions =
+		ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	cnli->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+
+	spin_lock_bh(&ecm_classifier_nl_lock);
+
+	/*
+	 * Final check if we are pending termination
+	 */
+	if (ecm_classifier_nl_terminate_pending) {
+		spin_unlock_bh(&ecm_classifier_nl_lock);
+		DEBUG_INFO("%px: Terminating\n", ci);
+		kfree(cnli);
+		return NULL;
+	}
+
+	/*
+	 * Link the new instance into our list at the head
+	 */
+	cnli->next = ecm_classifier_nl_instances;
+	if (ecm_classifier_nl_instances) {
+		ecm_classifier_nl_instances->prev = cnli;
+	}
+	ecm_classifier_nl_instances = cnli;
+
+	/*
+	 * Increment stats
+	 */
+	ecm_classifier_nl_count++;
+	DEBUG_ASSERT(ecm_classifier_nl_count > 0, "%px: ecm_classifier_nl_count wrap\n", cnli);
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+
+	DEBUG_INFO("Netlink instance alloc: %px\n", cnli);
+	return cnli;
+}
+EXPORT_SYMBOL(ecm_classifier_nl_instance_alloc);
+
+/*
+ * ecm_classifier_nl_set_command()
+ *	Set Netlink command to accel/decel connection.
+ */
+static ssize_t ecm_classifier_nl_set_command(struct file *file,
+						const char __user *user_buf,
+						size_t sz, loff_t *ppos)
+
+{
+#define ECM_CLASSIFIER_NL_SET_IP_COMMAND_FIELDS 7
+	char *cmd_buf;
+	int field_count;
+	char *field_ptr;
+	char *fields[ECM_CLASSIFIER_NL_SET_IP_COMMAND_FIELDS];
+	char cmd;
+	uint32_t serial;
+	ip_addr_t src_ip;
+	uint32_t src_port;
+	int proto;
+	ip_addr_t dest_ip;
+	uint32_t dest_port;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_classifier_nl_instance *cnli;
+	struct ecm_front_end_connection_instance *feci;
+
+	/*
+	 * Check if we are enabled
+	 */
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	if (!ecm_classifier_nl_enabled) {
+		spin_unlock_bh(&ecm_classifier_nl_lock);
+		return -EINVAL;
+	}
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+
+	/*
+	 * buf is formed as:
+	 * [0]   [1]      [2]      [3]        [4]     [5]       [6]
+	 * <CMD>/<SERIAL>/<src_ip>/<src_port>/<proto>/<dest_ip>/<dest_port>
+	 * CMD:
+	 *	F = Accelerate based on IP address, <SERIAL> unused
+	 *	f = Decelerate based on IP address, <SERIAL> unused
+	 *	S = Accelerate based on serial, <SERIAL> only becomes relevant
+	 *	s = Decelerate based on serial, <SERIAL> only becomes relevant
+	 */
+	cmd_buf = (char *)kzalloc(sz + 1, GFP_ATOMIC);
+	if (!cmd_buf) {
+		return -ENOMEM;
+	}
+
+	sz = simple_write_to_buffer(cmd_buf, sz, ppos, user_buf, sz);
+
+	/*
+	 * Split the buffer into its fields
+	 */
+	field_count = 0;
+	field_ptr = cmd_buf;
+	fields[field_count] = strsep(&field_ptr, "/");
+	while (fields[field_count] != NULL) {
+		DEBUG_TRACE("FIELD %d: %s\n", field_count, fields[field_count]);
+		field_count++;
+		if (field_count == ECM_CLASSIFIER_NL_SET_IP_COMMAND_FIELDS) {
+			break;
+		}
+		fields[field_count] = strsep(&field_ptr, "/");
+	}
+
+	if (field_count != ECM_CLASSIFIER_NL_SET_IP_COMMAND_FIELDS) {
+		DEBUG_WARN("invalid field count %d\n", field_count);
+		kfree(cmd_buf);
+		return -EINVAL;
+	}
+
+	sscanf(fields[0], "%c", &cmd);
+	sscanf(fields[1], "%u", &serial);
+	ecm_string_to_ip_addr(src_ip, fields[2]);
+	sscanf(fields[3], "%u", &src_port);
+	sscanf(fields[4], "%d", &proto);
+	ecm_string_to_ip_addr(dest_ip, fields[5]);
+	sscanf(fields[6], "%u", &dest_port);
+
+	kfree(cmd_buf);
+
+	/*
+	 * Locate the connection using the serial or tuple given
+	 */
+	switch (cmd) {
+	case 'F':
+	case 'f':
+		DEBUG_TRACE("Lookup connection " ECM_IP_ADDR_OCTAL_FMT ":%d <> " ECM_IP_ADDR_OCTAL_FMT ":%d protocol %d\n",
+				ECM_IP_ADDR_TO_OCTAL(src_ip), src_port, ECM_IP_ADDR_TO_OCTAL(dest_ip), dest_port, proto);
+		ci = ecm_db_connection_find_and_ref(src_ip, dest_ip, proto, src_port, dest_port);
+		break;
+	case 'S':
+	case 's':
+		DEBUG_TRACE("Lookup connection using serial: %u\n", serial);
+		ci = ecm_db_connection_serial_find_and_ref(serial);
+		break;
+	default:
+		DEBUG_WARN("invalid cmd %c\n", cmd);
+		return -EINVAL;
+	}
+
+	if (!ci) {
+		DEBUG_WARN("database connection not found\n");
+		return -ENOMEM;
+	}
+	DEBUG_TRACE("Connection found: %px\n", ci);
+
+	/*
+	 * Get the NL classifier
+	 */
+	cnli = (struct ecm_classifier_nl_instance *)ecm_db_connection_assigned_classifier_find_and_ref(ci, ECM_CLASSIFIER_TYPE_NL);
+	if (!cnli) {
+		ecm_db_connection_deref(ci);
+		return -ENOMEM;
+	}
+
+	/*
+	 * Now action the command
+	 */
+	switch (cmd) {
+	case 's':
+	case 'f':
+		/*
+		 * Decelerate the connection, NL is denying further accel until it says so.
+		 */
+		DEBUG_TRACE("Force decel: %px\n", ci);
+		spin_lock_bh(&ecm_classifier_nl_lock);
+		cnli->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+		spin_unlock_bh(&ecm_classifier_nl_lock);
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+		feci->decelerate(feci);
+		feci->deref(feci);
+		break;
+	case 'S':
+	case 'F':
+		/*
+		 * Allow acceleration of the connection.  This will be done as packets are processed in the usual way.
+		 */
+		DEBUG_TRACE("Permit accel: %px\n", ci);
+		spin_lock_bh(&ecm_classifier_nl_lock);
+		cnli->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+		cnli->flags |= ECM_CLASSIFIER_NL_F_ACCEL;
+		spin_unlock_bh(&ecm_classifier_nl_lock);
+		break;
+	}
+
+	cnli->base.deref((struct ecm_classifier_instance *)cnli);
+	ecm_db_connection_deref(ci);
+
+	return sz;
+}
+
+/*
+ * ecm_classifier_nl_rule_get_enabled()
+ */
+static int ecm_classifier_nl_rule_get_enabled(void *data, u64 *val)
+{
+	DEBUG_TRACE("get enabled\n");
+
+	*val = ecm_classifier_nl_enabled;
+
+	return 0;
+}
+
+/*
+ * ecm_classifier_nl_rule_set_enabled()
+ */
+static int ecm_classifier_nl_rule_set_enabled(void *data, u64 val)
+{
+	bool prev_state;
+
+	/*
+	 * Boolean-ise
+	 */
+	if (val) {
+		val = true;
+	}
+	DEBUG_TRACE("ecm_classifier_nl_enabled = %d\n", (int)val);
+
+	/*
+	 * Operate under our locks
+	 */
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	prev_state = ecm_classifier_nl_enabled;
+	ecm_classifier_nl_enabled = (bool)val;
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+
+	/*
+	 * If there is a change in operating state, and that change is that we are now disabled
+	 * then we need to re-generate all connections relevant to this classifier type
+	 */
+	if (!val && (prev_state ^ (bool)val)) {
+		/*
+		 * Change in state to become disabled.
+		 */
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+		ecm_db_connection_regenerate_by_assignment_type(ECM_CLASSIFIER_TYPE_NL);
+#else
+		ecm_db_regeneration_needed();
+#endif
+	}
+	return 0;
+}
+
+/*
+ * Debugfs attribute for the nl classifier enabled flag.
+ */
+DEFINE_SIMPLE_ATTRIBUTE(ecm_classifier_nl_enabled_fops, ecm_classifier_nl_rule_get_enabled, ecm_classifier_nl_rule_set_enabled, "%llu\n");
+
+/*
+ * File operations for nl classifier command.
+ */
+static struct file_operations ecm_classifier_nl_cmd_fops = {
+	.write = ecm_classifier_nl_set_command,
+};
+
+/*
+ * Generic Netlink attr checking policies
+ */
+static struct nla_policy
+ecm_cl_nl_genl_policy[ECM_CL_NL_GENL_ATTR_COUNT] = {
+	[ECM_CL_NL_GENL_ATTR_TUPLE] = {
+		.type = NLA_UNSPEC,
+		.len = sizeof(struct ecm_cl_nl_genl_attr_tuple), },
+};
+
+/*
+ * Generic Netlink message-to-handler mapping
+ */
+static struct genl_ops ecm_cl_nl_genl_ops[] = {
+	{
+		.cmd = ECM_CL_NL_GENL_CMD_ACCEL,
+		.flags = 0,
+		.policy = ecm_cl_nl_genl_policy,
+		.doit = ecm_classifier_nl_genl_msg_ACCEL,
+		.dumpit = NULL,
+	},
+	{
+		.cmd = ECM_CL_NL_GENL_CMD_ACCEL_OK,
+		.flags = 0,
+		.policy = ecm_cl_nl_genl_policy,
+		.doit = NULL,
+		.dumpit = ecm_classifier_nl_genl_msg_DUMP,
+	},
+	{
+		.cmd = ECM_CL_NL_GENL_CMD_CONNECTION_CLOSED,
+		.flags = 0,
+		.policy = ecm_cl_nl_genl_policy,
+		.doit = NULL,
+		.dumpit = ecm_classifier_nl_genl_msg_DUMP,
+	},
+};
+
+static int ecm_classifier_nl_register_genl(void)
+{
+
+	return genl_register_family_with_ops_groups(&ecm_cl_nl_genl_family,
+						      ecm_cl_nl_genl_ops,
+						      ecm_cl_nl_genl_mcgrp);
+}
+
+static void ecm_classifier_nl_unregister_genl(void)
+{
+	genl_unregister_family(&ecm_cl_nl_genl_family);
+}
+
+/*
+ * ecm_classifier_nl_rules_init()
+ */
+int ecm_classifier_nl_rules_init(struct dentry *dentry)
+{
+	int result;
+	DEBUG_INFO("Netlink classifier Module init\n");
+
+	ecm_classifier_nl_dentry = debugfs_create_dir("ecm_classifier_nl", dentry);
+	if (!ecm_classifier_nl_dentry) {
+		DEBUG_ERROR("Failed to create ecm nl classifier directory in debugfs\n");
+		return -1;
+	}
+
+	if (!debugfs_create_file("enabled", S_IRUGO | S_IWUSR, ecm_classifier_nl_dentry,
+					NULL, &ecm_classifier_nl_enabled_fops)) {
+		DEBUG_ERROR("Failed to create ecm nl classifier enabled file in debugfs\n");
+		debugfs_remove_recursive(ecm_classifier_nl_dentry);
+		return -1;
+	}
+
+	if (!debugfs_create_file("cmd", S_IRUGO | S_IWUSR, ecm_classifier_nl_dentry,
+					NULL, &ecm_classifier_nl_cmd_fops)) {
+		DEBUG_ERROR("Failed to create ecm nl classifier cmd file in debugfs\n");
+		debugfs_remove_recursive(ecm_classifier_nl_dentry);
+		return -1;
+	}
+
+	result = ecm_classifier_nl_register_genl();
+	if (result) {
+		DEBUG_ERROR("Failed to register genl sockets\n");
+		return result;
+	}
+
+	/*
+	 * Allocate listener instance to listen for db events
+	 */
+	ecm_classifier_nl_li = ecm_db_listener_alloc();
+	if (!ecm_classifier_nl_li) {
+		DEBUG_ERROR("Failed to allocate listener\n");
+		return -1;
+	}
+
+	/*
+	 * Add the listener into the database
+	 * NOTE: Ref the thread count for the listener
+	 */
+	ecm_db_listener_add(ecm_classifier_nl_li,
+			NULL /* ecm_classifier_nl_iface_added */,
+			NULL /* ecm_classifier_nl_iface_removed */,
+			NULL /* ecm_classifier_nl_node_added */,
+			NULL /* ecm_classifier_nl_node_removed */,
+			NULL /* ecm_classifier_nl_host_added */,
+			NULL /* ecm_classifier_nl_host_removed */,
+			NULL /* ecm_classifier_nl_mapping_added */,
+			NULL /* ecm_classifier_nl_mapping_removed */,
+			ecm_classifier_nl_connection_added,
+			ecm_classifier_nl_connection_removed,
+			NULL /* ecm_classifier_nl_listener_final */,
+			ecm_classifier_nl_li);
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_classifier_nl_rules_init);
+
+/*
+ * ecm_classifier_nl_rules_exit()
+ */
+void ecm_classifier_nl_rules_exit(void)
+{
+	DEBUG_INFO("Netlink classifier Module exit\n");
+
+	/*
+	 * Release our ref to the listener.
+	 * This will cause it to be unattached to the db listener list.
+	 * GGG TODO THIS IS TOTALLY BROKEN (DUE TO REF COUNT HANDLING NOT BEING HONOURED)
+	 */
+	if (ecm_classifier_nl_li) {
+		ecm_db_listener_deref(ecm_classifier_nl_li);
+		ecm_classifier_nl_li = NULL;
+	}
+
+	spin_lock_bh(&ecm_classifier_nl_lock);
+	ecm_classifier_nl_terminate_pending = true;
+	spin_unlock_bh(&ecm_classifier_nl_lock);
+
+	ecm_classifier_nl_unregister_genl();
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_classifier_nl_dentry) {
+		debugfs_remove_recursive(ecm_classifier_nl_dentry);
+	}
+}
+EXPORT_SYMBOL(ecm_classifier_nl_rules_exit);
diff --git a/qca-nss-ecm/ecm_classifier_nl.h b/qca-nss-ecm/ecm_classifier_nl.h
new file mode 100644
index 0000000..6623992
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_nl.h
@@ -0,0 +1,72 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/if_ether.h>
+
+struct ecm_classifier_nl_instance;
+
+struct ecm_classifier_nl_instance *
+ecm_classifier_nl_instance_alloc(struct ecm_db_connection_instance *ci);
+
+/*
+ *  Callback for for conmark updates
+ *
+ *  Saves the new mark to the per-connection context and decelerates
+ *  the connection if offloaded.
+ */
+void ecm_classifier_nl_process_mark(struct ecm_classifier_nl_instance *cnli,
+				    uint32_t mark);
+
+/*
+ * Generic Netlink defines and structs
+ */
+#define ECM_CL_NL_GENL_VERSION	(1)			/* API version */
+#define ECM_CL_NL_GENL_NAME	"ECMCLNL"		/* family name */
+#define ECM_CL_NL_GENL_MCGRP	"ECMCLNL_MCGRP"		/* multicast group */
+
+enum ECM_CL_NL_GENL_CMD {
+	ECM_CL_NL_GENL_CMD_UNSPEC,
+	ECM_CL_NL_GENL_CMD_ACCEL,
+	ECM_CL_NL_GENL_CMD_ACCEL_OK,
+	ECM_CL_NL_GENL_CMD_CONNECTION_CLOSED,
+	ECM_CL_NL_GENL_CMD_COUNT,
+};
+#define ECM_CL_NL_GENL_CMD_MAX (ECM_CL_NL_GENL_CMD_COUNT - 1)
+
+enum ECM_CL_NL_GENL_ATTR {
+	ECM_CL_NL_GENL_ATTR_UNSPEC,
+	ECM_CL_NL_GENL_ATTR_TUPLE,
+	ECM_CL_NL_GENL_ATTR_COUNT,
+};
+#define ECM_CL_NL_GENL_ATTR_MAX (ECM_CL_NL_GENL_ATTR_COUNT - 1)
+
+union ecm_cl_nl_genl_attr_ip {
+	struct in_addr in;
+	struct in6_addr in6;
+};
+
+/* network order */
+struct ecm_cl_nl_genl_attr_tuple {
+	uint16_t	af;
+	uint8_t		proto;
+	union ecm_cl_nl_genl_attr_ip src_ip;
+	union ecm_cl_nl_genl_attr_ip dst_ip;
+	uint16_t	src_port;
+	uint16_t	dst_port;
+	uint8_t		src_mac[ETH_ALEN];
+	uint8_t		dest_mac[ETH_ALEN];
+};
+
diff --git a/qca-nss-ecm/ecm_classifier_ovs.c b/qca-nss-ecm/ecm_classifier_ovs.c
new file mode 100644
index 0000000..b9d98d4
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_ovs.c
@@ -0,0 +1,2298 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * OVS Classifier.
+ * This classifier is called for the connections which are created
+ * on OVS interfaces. The connections can be routed or bridged connections.
+ * The classifier processes these connection flows and decides if the connection
+ * is ready to be accelerated. Moreover, it has an interface to an external classifier
+ * to make smart decisions on the flows, such as extracting the VLAN information from the
+ * OVS flow tables and gives it to the ECM front end to be passed to the acceleration engine.
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/debugfs.h>
+#include <linux/ctype.h>
+#include <net/tcp.h>
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/etherdevice.h>
+#include <linux/netfilter/xt_dscp.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_CLASSIFIER_OVS_DEBUG_LEVEL
+
+#include <ovsmgr.h>
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_ovs.h"
+#include "ecm_classifier_ovs_public.h"
+#include "ecm_front_end_common.h"
+#include "ecm_front_end_ipv4.h"
+#ifdef ECM_IPV6_ENABLE
+#include "ecm_front_end_ipv6.h"
+#endif
+#include "ecm_interface.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_CLASSIFIER_OVS_INSTANCE_MAGIC 0x2568
+
+/*
+ * struct ecm_classifier_ovs_instance
+ * 	State per connection for OVS classifier
+ */
+struct ecm_classifier_ovs_instance {
+	struct ecm_classifier_instance base;			/* Base type */
+
+	uint32_t ci_serial;					/* RO: Serial of the connection */
+
+	struct ecm_classifier_ovs_instance *next;		/* Next classifier state instance (for accouting and reporting purposes) */
+	struct ecm_classifier_ovs_instance *prev;		/* Next classifier state instance (for accouting and reporting purposes) */
+
+	struct ecm_classifier_process_response process_response;
+								/* Last process response computed */
+	int refs;						/* Integer to trap we never go negative */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+/*
+ * Operational control.
+ */
+static int ecm_classifier_ovs_enabled = 1;			/* Operational behaviour */
+
+/*
+ * Management thread control
+ */
+static bool ecm_classifier_ovs_terminate_pending;	/* True when the user wants us to terminate */
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_classifier_ovs_dentry;
+
+/*
+ * Locking of the classifier structures
+ */
+static DEFINE_SPINLOCK(ecm_classifier_ovs_lock);			/* Protect SMP access. */
+
+/*
+ * List of our classifier instances
+ */
+static struct ecm_classifier_ovs_instance *ecm_classifier_ovs_instances = NULL;
+								/* list of all active instances */
+static int ecm_classifier_ovs_count = 0;			/* Tracks number of instances allocated */
+
+/*
+ * Callback object.
+ */
+static struct ecm_classifier_ovs_callbacks ovs;
+
+/*
+ * ecm_classifier_ovs_ref()
+ *	Ref
+ */
+static void ecm_classifier_ovs_ref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_ovs_instance *ecvi;
+	ecvi = (struct ecm_classifier_ovs_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(ecvi, ECM_CLASSIFIER_OVS_INSTANCE_MAGIC, "%px: magic failed", ecvi);
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	ecvi->refs++;
+	DEBUG_ASSERT(ecvi->refs > 0, "%px: ref wrap\n", ecvi);
+	DEBUG_TRACE("%px: ecvi ref %d\n", ecvi, ecvi->refs);
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+}
+
+/*
+ * ecm_classifier_ovs_deref()
+ *	Deref
+ */
+static int ecm_classifier_ovs_deref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_ovs_instance *ecvi;
+	ecvi = (struct ecm_classifier_ovs_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(ecvi, ECM_CLASSIFIER_OVS_INSTANCE_MAGIC, "%px: magic failed", ecvi);
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	ecvi->refs--;
+	DEBUG_ASSERT(ecvi->refs >= 0, "%px: refs wrapped\n", ecvi);
+	DEBUG_TRACE("%px: ecvi deref %d\n", ecvi, ecvi->refs);
+	if (ecvi->refs) {
+		int refs = ecvi->refs;
+		spin_unlock_bh(&ecm_classifier_ovs_lock);
+		return refs;
+	}
+
+	/*
+	 * Object to be destroyed
+	 */
+	ecm_classifier_ovs_count--;
+	DEBUG_ASSERT(ecm_classifier_ovs_count >= 0, "%px: ecm_classifier_ovs_count wrap\n", ecvi);
+
+	/*
+	 * UnLink the instance from our list
+	 */
+	if (ecvi->next) {
+		ecvi->next->prev = ecvi->prev;
+	}
+	if (ecvi->prev) {
+		ecvi->prev->next = ecvi->next;
+	} else {
+		DEBUG_ASSERT(ecm_classifier_ovs_instances == ecvi, "%px: list bad %px\n", ecvi, ecm_classifier_ovs_instances);
+		ecm_classifier_ovs_instances = ecvi->next;
+	}
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+
+	/*
+	 * Final
+	 */
+	DEBUG_INFO("%px: Final ovs classifier instance\n", ecvi);
+	kfree(ecvi);
+
+	return 0;
+}
+
+/*
+ * ecm_classifier_ovs_interface_get_and_ref()
+ *	Gets the OVS bridge port in the specified direction hierarchy.
+ */
+static inline struct net_device *ecm_classifier_ovs_interface_get_and_ref(struct ecm_db_connection_instance *ci,
+									   ecm_db_obj_dir_t dir, bool ovs_port)
+{
+	int32_t if_first;
+	struct ecm_db_iface_instance *interfaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	int32_t i;
+
+	/*
+	 * Get the interface hierarchy.
+	 */
+	if_first = ecm_db_connection_interfaces_get_and_ref(ci, interfaces, dir);
+	if (if_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Failed to get %s interfaces list\n", ci, ecm_db_obj_dir_strings[dir]);
+		return NULL;
+	}
+
+	/*
+	 * Go through the hierarchy and get the OVS port.
+	 */
+	for (i = ECM_DB_IFACE_HEIRARCHY_MAX - 1; i >= if_first; i--) {
+		struct net_device *dev = dev_get_by_index(&init_net,
+							  ecm_db_iface_interface_identifier_get(interfaces[i]));
+		if (!dev) {
+			DEBUG_WARN("%px: Failed to get net device with %d index\n", ci, i);
+			continue;
+		}
+
+		if (ovs_port) {
+			if (ecm_interface_is_ovs_bridge_port(dev)) {
+				ecm_db_connection_interfaces_deref(interfaces, if_first);
+				DEBUG_TRACE("%px: %s_dev: %s at %d index is an OVS bridge port\n", ci, ecm_db_obj_dir_strings[dir], dev->name, i);
+				return dev;
+			}
+
+		} else {
+			if (ovsmgr_is_ovs_master(dev)) {
+				ecm_db_connection_interfaces_deref(interfaces, if_first);
+				DEBUG_TRACE("%px: %s_dev: %s at %d index is an OVS bridge dev\n", ci, ecm_db_obj_dir_strings[dir], dev->name, i);
+				return dev;
+			}
+		}
+
+		DEBUG_TRACE("%px: dev: %s index: %d\n", ci, dev->name, i);
+		dev_put(dev);
+	}
+
+	DEBUG_TRACE("%px: No OVS bridge port on the %s direction\n", ci, ecm_db_obj_dir_strings[dir]);
+	ecm_db_connection_interfaces_deref(interfaces, if_first);
+	return NULL;
+}
+
+#ifdef ECM_MULTICAST_ENABLE
+/*
+ * ecm_classifier_ovs_process_multicast()
+ * 	Process multicast packet
+ */
+static void ecm_classifier_ovs_process_multicast(struct ecm_db_connection_instance *ci, struct sk_buff *skb,
+							struct ecm_classifier_ovs_instance *ecvi,
+							struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_ovs_process_response resp;
+	ecm_classifier_ovs_process_callback_t cb;
+	struct ecm_db_iface_instance *to_mc_ifaces;
+	struct net_device *from_dev = NULL, *indev_master = NULL;
+	struct net_device *to_dev[ECM_DB_MULTICAST_IF_MAX] = {NULL};
+	struct ovsmgr_dp_flow flow;
+	ip_addr_t src_ip;
+	ip_addr_t dst_ip;
+	int32_t *to_mc_ifaces_first;
+	int if_cnt, i;
+	bool valid_ovs_ports = false;
+
+	/*
+	 * Classifier is always relevant for multicast
+	 * if we have enabled OVS support in ECM.
+	 */
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	ecvi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+
+	/*
+	 * No multicast port found, drop the connection.
+	 */
+	if_cnt = ecm_db_multicast_connection_to_interfaces_get_and_ref_all(ci, &to_mc_ifaces, &to_mc_ifaces_first);
+	if (unlikely(!if_cnt)) {
+		spin_lock_bh(&ecm_classifier_ovs_lock);
+		ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DROP;
+		ecvi->process_response.drop = true;
+		*process_response = ecvi->process_response;
+		spin_unlock_bh(&ecm_classifier_ovs_lock);
+		DEBUG_WARN("%px: No multicast 'to' interface found\n", ci);
+		goto done;
+	}
+
+	for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+		int32_t *to_iface_first;
+		int j;
+
+		/*
+		 * Get to interface list, skip if the list is invalid.
+		 */
+		to_iface_first = ecm_db_multicast_if_first_get_at_index(to_mc_ifaces_first, i);
+		if (*to_iface_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			continue;
+		}
+
+		for (j = to_mc_ifaces_first[i]; j < ECM_DB_IFACE_HEIRARCHY_MAX; j++) {
+			struct ecm_db_iface_instance **ifaces;
+			struct ecm_db_iface_instance *ii_temp;
+			struct net_device *to_dev_temp;
+
+			ii_temp = ecm_db_multicast_if_heirarchy_get(to_mc_ifaces, i);
+			ifaces = (struct ecm_db_iface_instance **)ecm_db_multicast_if_instance_get_at_index(ii_temp, j);
+			to_dev_temp = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(*ifaces));
+			if (unlikely(!to_dev_temp)) {
+				continue;
+			}
+
+			/*
+			 * Get the physical OVS port.
+			 */
+			if (!ecm_interface_is_ovs_bridge_port(to_dev_temp)) {
+				dev_put(to_dev_temp);
+				continue;
+			}
+
+			to_dev[i] = to_dev_temp;
+			valid_ovs_ports = true;
+		}
+	}
+	ecm_db_multicast_connection_to_interfaces_deref_all(to_mc_ifaces, to_mc_ifaces_first);
+
+	from_dev = ecm_classifier_ovs_interface_get_and_ref(ci, ECM_DB_OBJ_DIR_FROM, true);
+	if (!from_dev && !valid_ovs_ports) {
+		spin_lock_bh(&ecm_classifier_ovs_lock);
+		*process_response = ecvi->process_response;
+		spin_unlock_bh(&ecm_classifier_ovs_lock);
+		DEBUG_WARN("%px: None of the from/to interfaces are OVS bridge port\n", ci);
+		goto done;
+	}
+
+	/*
+	 * Below are the possible multicast flows.
+	 *
+	 * 1. L2 Multicast (Bridge)
+	 * 	ovsbr (eth0, eth1,eth2)
+	 * 	a. sender: eth0, receiver: eth1, eth2
+	 *
+	 * 2. L3 Multicast (Route)
+	 * 	Upstream: br-wan (eth0)
+	 * 	Downstream: br-home (eth1, eth2)
+	 * 	a. Downstream flow => sender: eth0, receiver: eth1, eth2
+	 * 	b. Upstream flow => sender: eth1, receiver: eth0
+	 *
+	 * 3. L2 + L3 Multicast (Bridge + Route)
+	 * 	Upstream: br-wan (eth0)
+	 * 	Downstream: br-home (eth1, eth2)
+	 * 	a. sender: eth1, receiver: eth0, eth2
+	 */
+
+	/*
+	 * Is there an external callback to get the ovs value from the packet?
+	 */
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	cb = ovs.ovs_process;
+	if (!cb) {
+		/*
+		 * Allow acceleration.
+		 * Keep the classifier relevant to connection for stats update..
+		 */
+		spin_unlock_bh(&ecm_classifier_ovs_lock);
+		DEBUG_WARN("%px: No external process callback set\n", ci);
+		goto allow_accel;
+	}
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+
+	memset(&flow, 0, sizeof(struct ovsmgr_dp_flow));
+
+	if (from_dev) {
+		flow.indev = from_dev;
+		indev_master = ovsmgr_dev_get_master(flow.indev);
+		DEBUG_ASSERT(indev_master, "%px: Expected a master\n", ci);
+	}
+
+	flow.is_routed = ecm_db_connection_is_routed_get(ci);
+	flow.tuple.ip_version = ecm_db_connection_ip_version_get(ci);
+	flow.tuple.protocol = ecm_db_connection_protocol_get(ci);
+	flow.tuple.src_port = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+	flow.tuple.dst_port = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO));
+
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, flow.smac);
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, flow.dmac);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+
+	if (flow.tuple.ip_version == 4) {
+		ECM_IP_ADDR_TO_NIN4_ADDR(flow.tuple.ipv4.src, src_ip);
+		ECM_IP_ADDR_TO_NIN4_ADDR(flow.tuple.ipv4.dst, dst_ip);
+	} else if (flow.tuple.ip_version == 6) {
+		ECM_IP_ADDR_TO_NIN6_ADDR(flow.tuple.ipv6.src, src_ip);
+		ECM_IP_ADDR_TO_NIN6_ADDR(flow.tuple.ipv6.dst, dst_ip);
+	} else {
+		DEBUG_ASSERT(NULL, "%px: unexpected ip_version: %d", ci, flow.tuple.ip_version );
+	}
+
+	/*
+	 * Check if the connection is a "bridge + route"
+	 * flow.
+	 */
+	if (flow.is_routed) {
+		/*
+		 * Get the ingress VLAN information from ovs-mgr
+		 */
+		if (from_dev) {
+			struct net_device *br_dev;
+			ecm_classifier_ovs_result_t result;
+
+			/*
+			 * from_dev = eth1
+			 * br_dev = ovs-br1
+			 */
+			br_dev = ecm_classifier_ovs_interface_get_and_ref(ci, ECM_DB_OBJ_DIR_FROM, false);
+			DEBUG_TRACE("%px: processing route flow from_dev = %s, br_dev = %s", ecvi, from_dev->name, br_dev->name);
+
+			/*
+			 * We always take the flow from bridge to port, so indev is port device and outdev is bridge device.
+			 */
+			flow.indev = from_dev;
+			flow.outdev = br_dev;
+
+			DEBUG_TRACE("%px: Route Flow Process (from): src MAC: %pM src_dev: %s src: %pI4:%d proto: %d dest: %pI4:%d dest_dev: %s dest MAC: %pM\n",
+					&flow, flow.smac, flow.indev->name, &flow.tuple.ipv4.src, flow.tuple.src_port, flow.tuple.protocol,
+					&flow.tuple.ipv4.dst, flow.tuple.dst_port, flow.outdev->name, flow.dmac);
+
+			memset(&resp, 0, sizeof(struct ecm_classifier_ovs_process_response));
+
+			/*
+			 * Call the external callback and get the result.
+			 */
+			result = cb(&flow, skb, &resp);
+
+			dev_put(br_dev);
+
+			/*
+			 * Handle the result
+			 */
+			switch (result) {
+			case ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_ACCEL:
+			case ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_QINQ_ACCEL:
+				/*
+				 * Allow accel after setting the external module response.
+				 */
+				DEBUG_WARN("%px: External callback process succeeded\n", ecvi);
+				spin_lock_bh(&ecm_classifier_ovs_lock);
+				ecvi->process_response.ingress_vlan_tag[0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+				ecvi->process_response.ingress_vlan_tag[1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+				if (resp.egress_vlan[0].h_vlan_TCI) {
+					ecvi->process_response.ingress_vlan_tag[0] = resp.egress_vlan[0].h_vlan_encapsulated_proto << 16 | resp.egress_vlan[0].h_vlan_TCI;
+				}
+
+				ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG;
+				if (result == ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_QINQ_ACCEL) {
+					if (resp.egress_vlan[1].h_vlan_TCI) {
+						ecvi->process_response.ingress_vlan_tag[1] = resp.egress_vlan[1].h_vlan_encapsulated_proto << 16 | resp.egress_vlan[1].h_vlan_TCI;
+					}
+
+					ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG;
+				}
+				spin_unlock_bh(&ecm_classifier_ovs_lock);
+				DEBUG_TRACE("%px: Multicast ingress vlan tag[0]: %x tag[1]: %x\n", ecvi, ecvi->process_response.ingress_vlan_tag[0],
+						ecvi->process_response.ingress_vlan_tag[1]);
+				break;
+
+			case ECM_CLASSIFIER_OVS_RESULT_DENY_ACCEL:
+				/*
+				 * External callback failed to process VLAN process. So, let's deny the acceleration
+				 * and try more with the subsequent packets.
+				 */
+				DEBUG_WARN("%px: External callback failed to process VLAN tags\n", ecvi);
+				spin_lock_bh(&ecm_classifier_ovs_lock);
+				ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_MCAST_DENY_ACCEL;
+				ecvi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+				*process_response = ecvi->process_response;
+				spin_unlock_bh(&ecm_classifier_ovs_lock);
+				goto done;
+
+			case ECM_CLASSIFIER_OVS_RESULT_ALLOW_ACCEL:
+				/*
+				 * There is no VLAN tag in the flow. Just allow the acceleration.
+				 */
+				DEBUG_WARN("%px: External callback didn't find any VLAN relation\n", ecvi);
+				break;
+
+			default:
+				DEBUG_ASSERT(false, "%px: Unhandled result: %d\n", ci, result);
+			}
+		}
+	}
+
+	/*
+	 * During multicast update path, skb is passed as NULL.
+	 * We need to fill the ingress_vlan with the same vlan
+	 * information that we have stored during connection instance
+	 * creation. OVS manager needs this information to provide the
+	 * right response.
+	 */
+	if (!skb) {
+		flow.ingress_vlan = ecm_db_multicast_tuple_get_ovs_ingress_vlan(ci->ti);
+	}
+
+	/*
+	 * Call the external callback and get the result.
+	 */
+	for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+		ecm_classifier_ovs_result_t result = 0;
+
+		if (!to_dev[i]) {
+			continue;
+		}
+
+		flow.outdev = to_dev[i];
+
+		/*
+		 * For routed flows, indev should be the OVS bridge of the
+		 * corresponding port.
+		 */
+		if (flow.is_routed) {
+			struct net_device *outdev_master;
+
+			/*
+			 * During bridge+route scenario, the indev can be
+			 * an ovs bridge port or and ovs bridge. if master device
+			 * for indev and outdev are same then it a bridged traffic.
+			 * Otherwise, set the indev to master of the egress port.
+			 */
+			outdev_master = ovsmgr_dev_get_master(flow.outdev);
+			DEBUG_ASSERT(outdev_master, "%px: Expected a master\n", ci);
+			if (indev_master && (indev_master->ifindex == outdev_master->ifindex)) {
+				flow.indev = from_dev;
+				ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, flow.smac);
+			} else {
+				flow.indev = outdev_master;
+				ether_addr_copy(flow.smac, flow.indev->dev_addr);
+			}
+		}
+
+		DEBUG_TRACE("%px: src MAC: %pM src_dev: %s src: %pI4:%d proto: %d dest: %pI4:%d dest_dev: %s dest MAC: %pM\n",
+				ci, flow.smac, flow.indev->name, &flow.tuple.ipv4.src, flow.tuple.src_port, flow.tuple.protocol,
+				&flow.tuple.ipv4.dst, flow.tuple.dst_port, flow.outdev->name, flow.dmac);
+
+		memset(&resp, 0, sizeof(struct ecm_classifier_ovs_process_response));
+		result = cb(&flow, skb, &resp);
+
+		switch(result) {
+		case ECM_CLASSIFIER_OVS_RESULT_DENY_ACCEL_EGRESS:
+			DEBUG_TRACE("%px: %s is not a valid OVS port\n", ci, to_dev[i]->name);
+			ecm_db_multicast_connection_to_interfaces_clear_at_index(ci, i);
+			break;
+
+		case ECM_CLASSIFIER_OVS_RESULT_DENY_ACCEL:
+			/*
+			 * If we receive "ECM_CLASSIFIER_OVS_RESULT_DENY_ACCEL"
+			 * for any of the OVS port, then the connection should be
+			 * deleted.
+			 */
+			DEBUG_TRACE("%px: flow does not exist for the OVS port: %s\n", ci, to_dev[i]->name);
+			spin_lock_bh(&ecm_classifier_ovs_lock);
+			ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_MCAST_DENY_ACCEL;
+			ecvi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+			*process_response = ecvi->process_response;
+			spin_unlock_bh(&ecm_classifier_ovs_lock);
+			goto done;
+
+		case ECM_CLASSIFIER_OVS_RESULT_ALLOW_ACCEL:
+			DEBUG_TRACE("%px: Acceleration allowed for multicast OVS port: %s\n", ci, to_dev[i]->name);
+			break;
+
+		case ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_ACCEL:
+		case ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_QINQ_ACCEL:
+			/*
+			 * Allow accel after setting the external module response.
+			 * Primary VLAN tag is always present even it is QinQ.
+			 */
+			DEBUG_WARN("%px: External callback process succeeded\n", ci);
+
+			/*
+			 * Initialize the VLAN entries since the ports can join/leave
+			 * in-between and that will change the position of an existing port
+			 * in the "egress_mc_vlan_tag" array.
+			 */
+			spin_lock_bh(&ecm_classifier_ovs_lock);
+			ecvi->process_response.egress_mc_vlan_tag[i][0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+			ecvi->process_response.egress_mc_vlan_tag[i][1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+			ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG;
+			ecvi->process_response.egress_netdev_index[i] = flow.outdev->ifindex;
+
+			/*
+			 * If we have a valid TCI for ingress VLAN then we assume
+			 * the flow is bridged. Because for routed flows, ingress VLAN
+			 * will not be available.
+			 */
+			if (resp.ingress_vlan[0].h_vlan_TCI) {
+				ecvi->process_response.ingress_vlan_tag[0] = resp.ingress_vlan[0].h_vlan_encapsulated_proto << 16 | resp.ingress_vlan[0].h_vlan_TCI;
+			}
+
+			if (resp.egress_vlan[0].h_vlan_TCI) {
+				ecvi->process_response.egress_mc_vlan_tag[i][0] = resp.egress_vlan[0].h_vlan_encapsulated_proto << 16 | resp.egress_vlan[0].h_vlan_TCI;
+			}
+
+			if (result == ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_QINQ_ACCEL) {
+				if (resp.ingress_vlan[1].h_vlan_TCI) {
+					ecvi->process_response.ingress_vlan_tag[1] = resp.ingress_vlan[1].h_vlan_encapsulated_proto << 16 | resp.ingress_vlan[1].h_vlan_TCI;
+				}
+
+				if (resp.egress_vlan[1].h_vlan_TCI) {
+					ecvi->process_response.egress_mc_vlan_tag[i][1] = resp.egress_vlan[1].h_vlan_encapsulated_proto << 16 | resp.egress_vlan[1].h_vlan_TCI;
+				}
+
+				ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG;
+			}
+
+			spin_unlock_bh(&ecm_classifier_ovs_lock);
+			DEBUG_TRACE("%px: Multicast ingress vlan tag[0] : 0x%x tag[1] : 0x%x\n", ci, ecvi->process_response.ingress_vlan_tag[0],
+					ecvi->process_response.ingress_vlan_tag[1]);
+			DEBUG_TRACE("%px: Multicast egress vlan tag[%d][0] : 0x%x tag[%d][1] : 0x%x\n", ci, i, ecvi->process_response.egress_mc_vlan_tag[i][0],
+					i, ecvi->process_response.egress_mc_vlan_tag[i][1]);
+			break;
+
+		default:
+			DEBUG_ASSERT(false, "Unhandled result: %d\n", result);
+		}
+	}
+
+	/*
+	 * It is possible that after verifying each egress port with ovs manager,
+	 * no egress ovs ports are allowed for acceleration.
+	 *
+	 * Deny the multicast connection as there are no active 'to' interface.
+	 */
+	if (!ecm_db_multicast_connection_to_interfaces_get_count(ci)) {
+		DEBUG_TRACE("%px: No valid multicast 'to' interfaces found\n", ci);
+		spin_lock_bh(&ecm_classifier_ovs_lock);
+		ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_MCAST_DENY_ACCEL;
+		ecvi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+		*process_response = ecvi->process_response;
+		spin_unlock_bh(&ecm_classifier_ovs_lock);
+		goto done;
+	}
+
+allow_accel:
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	ecvi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+	*process_response = ecvi->process_response;
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+
+done:
+	if (from_dev)
+		dev_put(from_dev);
+
+	/*
+	 * Deref the ovs net devices
+	 */
+	if (valid_ovs_ports) {
+		for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+			if (to_dev[i]) {
+				dev_put(to_dev[i]);
+			}
+		}
+	}
+
+	return;
+}
+#endif
+
+/*
+ * ecm_classifier_ovs_process_route_flow()
+ *	Process routed flows.
+ */
+static void ecm_classifier_ovs_process_route_flow(struct ecm_classifier_ovs_instance *ecvi, struct ecm_db_connection_instance *ci,
+							struct sk_buff *skb, struct net_device *from_dev, struct net_device *to_dev,
+							struct ecm_classifier_process_response *process_response,
+							ecm_classifier_ovs_process_callback_t cb)
+{
+	ecm_classifier_ovs_result_t result;
+	struct ecm_classifier_ovs_process_response resp;
+	struct ovsmgr_dp_flow flow;
+	struct net_device *br_dev;
+	ip_addr_t src_ip, dst_ip;
+
+	memset(&flow, 0, sizeof(flow));
+
+	flow.is_routed = true;
+	flow.tuple.ip_version = ecm_db_connection_ip_version_get(ci);
+	flow.tuple.protocol = ecm_db_connection_protocol_get(ci);
+
+	/*
+	 * For routed flows both from and to side can be OVS bridge port, if there
+	 * is a routed flow between two OVS bridges. (e.g: ovs-br1 and ovs-br2)
+	 *
+	 * Connection Direction:
+	 * 				PC1 -----> eth1-ovs-br1 (DUT) ovs-br2-eth2 -----> PC2
+							from_dev	to_dev
+	 *
+	 * 1. SNAT/DNAT Enabled:	FROM				FROM_NAT	TO/TO_NAT
+	 * 2. SNAT/DNAT Disabled:	FROM/FROM_NAT					TO/TO_NAT
+	 *
+	 * Connection Direction:
+	 * 				PC1 <----- eth1-ovs-br1 (DUT) ovs-br2-eth2 <----- PC2
+	 *						to_dev		from_dev
+	 *
+	 * 3. SNAT/DNAT Enabled:	TO				TO_NAT		FROM/FROM_NAT
+	 * 4. SNAT/DNAT Disabled:	TO/TO_NAT					FROM/FROM_NAT
+	 *
+	 * 5. Tunnelled packet:  PC1 ------------> eth1---[ovs-br1]---gretap (DUT) eth0----->[gretap device]
+	 * 	After the packet is encapsulated, the packet is routed and the
+	 * 	flow is not relavant flow.
+	 */
+	if (from_dev) {
+		/*
+		 * Case 1/2
+		 * from_dev = eth1
+		 * br_dev = ovs-br1
+		 *
+		 * Case 3/4
+		 * from_dev = eth2
+		 * br_dev = ovs-br2
+		 *
+		 * case 5
+		 * from_dev = greptap
+		 * br_dev = NULL
+		 */
+		br_dev = ecm_classifier_ovs_interface_get_and_ref(ci, ECM_DB_OBJ_DIR_FROM, false);
+		if (!br_dev) {
+			DEBUG_WARN("%px: from_dev = %s is a OVS bridge port, bridge interface is not found\n",
+					ecvi, from_dev->name);
+			goto route_not_relevant;
+		}
+
+		DEBUG_TRACE("%px: processing route flow from_dev = %s, br_dev = %s", ecvi, from_dev->name, br_dev->name);
+
+		/*
+		 * We always take the flow from bridge to port, so indev is brdige and outdev is port device.
+		 */
+		flow.indev = br_dev;
+		flow.outdev = from_dev;
+
+		flow.tuple.src_port = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO_NAT));
+		flow.tuple.dst_port = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO_NAT, src_ip);
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, dst_ip);
+
+		if (flow.tuple.ip_version == 4) {
+			ECM_IP_ADDR_TO_NIN4_ADDR(flow.tuple.ipv4.src, src_ip);
+			ECM_IP_ADDR_TO_NIN4_ADDR(flow.tuple.ipv4.dst, dst_ip);
+		} else if (flow.tuple.ip_version == 6) {
+			ECM_IP_ADDR_TO_NIN6_ADDR(flow.tuple.ipv6.src, src_ip);
+			ECM_IP_ADDR_TO_NIN6_ADDR(flow.tuple.ipv6.dst, dst_ip);
+		} else {
+			DEBUG_ASSERT(NULL, "%px: unexpected ip_version: %d", ecvi, flow.tuple.ip_version );
+		}
+
+		ether_addr_copy(flow.smac, br_dev->dev_addr);
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, flow.dmac);
+
+		memset(&resp, 0, sizeof(struct ecm_classifier_ovs_process_response));
+
+		/*
+		 * Initialize the dscp with the default value.
+		 */
+		resp.dscp = OVSMGR_INVALID_DSCP;
+
+		DEBUG_TRACE("%px: Route Flow Process (from): src MAC: %pM src_dev: %s src: %pI4:%d proto: %d dest: %pI4:%d dest_dev: %s dest MAC: %pM\n",
+				&flow, flow.smac, flow.indev->name, &flow.tuple.ipv4.src, flow.tuple.src_port, flow.tuple.protocol,
+				&flow.tuple.ipv4.dst, flow.tuple.dst_port, flow.outdev->name, flow.dmac);
+		/*
+		 * Call the external callback and get the result.
+		 */
+		result = cb(&flow, skb, &resp);
+
+		dev_put(br_dev);
+
+		if (resp.dscp != OVSMGR_INVALID_DSCP) {
+			/*
+			 * Copy DSCP value to the classifier's process response's flow_dscp field,
+			 * because this is the from_dev and the direction of the flow is flow direction.
+			 */
+			spin_lock_bh(&ecm_classifier_ovs_lock);
+			ecvi->process_response.flow_dscp = resp.dscp >> XT_DSCP_SHIFT;
+			ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+			spin_unlock_bh(&ecm_classifier_ovs_lock);
+			DEBUG_TRACE("FLOW DSCP : 0x%x\n", ecvi->process_response.flow_dscp);
+		}
+
+		/*
+		 * Handle the result
+		 */
+		switch (result) {
+		case ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_ACCEL:
+		case ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_QINQ_ACCEL:
+			/*
+			 * Allow accel after setting the external module response.
+			 */
+			DEBUG_WARN("%px: External callback process succeeded\n", ecvi);
+
+			spin_lock_bh(&ecm_classifier_ovs_lock);
+			if (resp.egress_vlan[0].h_vlan_TCI) {
+				ecvi->process_response.ingress_vlan_tag[0] = resp.egress_vlan[0].h_vlan_encapsulated_proto << 16 | resp.egress_vlan[0].h_vlan_TCI;
+				DEBUG_TRACE("Ingress vlan tag[0] set : %x\n", ecvi->process_response.ingress_vlan_tag[0]);
+			}
+
+			ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG;
+
+			if (result == ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_QINQ_ACCEL) {
+				if (resp.egress_vlan[1].h_vlan_TCI) {
+					ecvi->process_response.ingress_vlan_tag[1] = resp.egress_vlan[1].h_vlan_encapsulated_proto << 16 | resp.egress_vlan[1].h_vlan_TCI;
+					DEBUG_TRACE("Ingress vlan tag[0] set : %x\n", ecvi->process_response.ingress_vlan_tag[1]);
+				}
+
+				ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG;
+			}
+			spin_unlock_bh(&ecm_classifier_ovs_lock);
+			break;
+
+		case ECM_CLASSIFIER_OVS_RESULT_DENY_ACCEL:
+			/*
+			 * External callback failed to process VLAN process. So, let's deny the acceleration
+			 * and try more with the subsequent packets.
+			 */
+			DEBUG_WARN("%px: External callback failed to process VLAN tags\n", ecvi);
+			goto route_deny_accel;
+
+		case ECM_CLASSIFIER_OVS_RESULT_ALLOW_ACCEL:
+
+			/*
+			 * There is no VLAN tag in the flow. Just allow the acceleration.
+			 */
+			DEBUG_WARN("%px: External callback didn't find any VLAN relation\n", ecvi);
+			break;
+
+		default:
+			DEBUG_ASSERT(false, "Unhandled result: %d\n", result);
+		}
+	}
+
+	if (to_dev) {
+		/*
+		 * Case 1/2
+		 * from_dev = eth2
+		 * br_dev = ovs-br2
+		 *
+		 * Case 3/4
+		 * from_dev = eth1
+		 * br_dev = ovs-br1
+		 */
+		br_dev = ecm_classifier_ovs_interface_get_and_ref(ci, ECM_DB_OBJ_DIR_TO, false);
+		if (!br_dev) {
+			DEBUG_WARN("%px: to_dev = %s is a OVS bridge port, bridge interface is not found\n",
+					ecvi, to_dev->name);
+			goto route_deny_accel;
+		}
+
+		DEBUG_TRACE("%px: processing route flow to_dev = %s, br_dev = %s", ecvi, to_dev->name, br_dev->name);
+
+		flow.indev = br_dev;
+		flow.outdev = to_dev;
+
+		flow.tuple.src_port = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM_NAT));
+		flow.tuple.dst_port = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO));
+
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM_NAT, src_ip);
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+
+		if (flow.tuple.ip_version == 4) {
+			ECM_IP_ADDR_TO_NIN4_ADDR(flow.tuple.ipv4.src, src_ip);
+			ECM_IP_ADDR_TO_NIN4_ADDR(flow.tuple.ipv4.dst, dst_ip);
+		} else if (flow.tuple.ip_version == 6) {
+			ECM_IP_ADDR_TO_NIN6_ADDR(flow.tuple.ipv6.src, src_ip);
+			ECM_IP_ADDR_TO_NIN6_ADDR(flow.tuple.ipv6.dst, dst_ip);
+		} else {
+			DEBUG_ASSERT(NULL, "%px: unexpected ip_version: %d", ecvi, flow.tuple.ip_version );
+		}
+
+		ether_addr_copy(flow.smac, br_dev->dev_addr);
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, flow.dmac);
+
+		memset(&resp, 0, sizeof(struct ecm_classifier_ovs_process_response));
+
+		/*
+		 * Initialize the dscp with the default value.
+		 */
+		resp.dscp = OVSMGR_INVALID_DSCP;
+
+		DEBUG_TRACE("%px: Route Flow Process (to): src MAC: %pM src_dev: %s src: %pI4:%d proto: %d dest: %pI4:%d dest_dev: %s dest MAC: %pM\n",
+				&flow, flow.smac, flow.indev->name, &flow.tuple.ipv4.src, flow.tuple.src_port, flow.tuple.protocol,
+				&flow.tuple.ipv4.dst, flow.tuple.dst_port, flow.outdev->name, flow.dmac);
+		/*
+		 * Call the external callback and get the result.
+		 */
+		result = cb(&flow, skb, &resp);
+
+		dev_put(br_dev);
+
+		if (resp.dscp != OVSMGR_INVALID_DSCP) {
+			/*
+			 * Copy DSCP value to the classifier's process response's return_dscp field,
+			 * because this is the to_dev and the direction of the flow is reply direction.
+			 */
+			spin_lock_bh(&ecm_classifier_ovs_lock);
+			ecvi->process_response.return_dscp = resp.dscp >> XT_DSCP_SHIFT;
+			ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+			spin_unlock_bh(&ecm_classifier_ovs_lock);
+			DEBUG_TRACE("RETURN DSCP : 0x%x\n", ecvi->process_response.return_dscp);
+		}
+
+		/*
+		 * Handle the result
+		 */
+		switch (result) {
+		case ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_ACCEL:
+		case ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_QINQ_ACCEL:
+			/*
+			 * Allow accel after setting the external module response.
+			 */
+			DEBUG_WARN("%px: External callback process succeeded\n", ecvi);
+
+			spin_lock_bh(&ecm_classifier_ovs_lock);
+			if (resp.egress_vlan[0].h_vlan_TCI) {
+				ecvi->process_response.egress_vlan_tag[0] = resp.egress_vlan[0].h_vlan_encapsulated_proto << 16 | resp.egress_vlan[0].h_vlan_TCI;
+				DEBUG_TRACE("Egress vlan tag[0] set : %x\n", ecvi->process_response.egress_vlan_tag[0]);
+			}
+
+			ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG;
+
+			if (result == ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_QINQ_ACCEL) {
+				if (resp.egress_vlan[1].h_vlan_TCI) {
+					ecvi->process_response.egress_vlan_tag[1] = resp.egress_vlan[1].h_vlan_encapsulated_proto << 16 | resp.egress_vlan[1].h_vlan_TCI;
+					DEBUG_TRACE("Ingress vlan tag[0] set : %x\n", ecvi->process_response.ingress_vlan_tag[1]);
+				}
+
+				ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG;
+			}
+			spin_unlock_bh(&ecm_classifier_ovs_lock);
+			break;
+
+		case ECM_CLASSIFIER_OVS_RESULT_DENY_ACCEL:
+			/*
+			 * External callback failed to process VLAN process. So, let's deny the acceleration
+			 * and try more with the subsequent packets.
+			 */
+			DEBUG_WARN("%px: External callback failed to process VLAN tags\n", ecvi);
+			goto route_deny_accel;
+
+		case ECM_CLASSIFIER_OVS_RESULT_ALLOW_ACCEL:
+
+			/*
+			 * There is no VLAN tag in the flow. Just allow the acceleration.
+			 */
+			DEBUG_WARN("%px: External callback didn't find any VLAN relation\n", ecvi);
+			break;
+
+		default:
+			DEBUG_ASSERT(false, "Unhandled result: %d\n", result);
+		}
+	}
+
+	/*
+	 * Acceleration is permitted
+	 */
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	ecvi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	ecvi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+	*process_response = ecvi->process_response;
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+
+	return;
+
+route_deny_accel:
+	/*
+	 * ecm_classifier_ovs_lock MUST be held
+	 */
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	ecvi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	ecvi->process_response.process_actions = ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	ecvi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+	*process_response = ecvi->process_response;
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+
+	return;
+
+route_not_relevant:
+	/*
+	 * ecm_classifier_ovs_lock MUST be held
+	 */
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	ecvi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+	*process_response = ecvi->process_response;
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+}
+
+/*
+ * ecm_classifier_ovs_process()
+ *	Process new packet
+ *
+ * NOTE: This function would only ever be called if all other classifiers have failed.
+ */
+static void ecm_classifier_ovs_process(struct ecm_classifier_instance *aci, ecm_tracker_sender_type_t sender,
+									struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb,
+									struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_ovs_instance *ecvi = (struct ecm_classifier_ovs_instance *)aci;
+	ecm_classifier_ovs_result_t result = 0;
+	struct ecm_db_connection_instance *ci;
+	ecm_classifier_ovs_process_callback_t cb = NULL;
+	ip_addr_t src_ip;
+	ip_addr_t dst_ip;
+	struct ecm_classifier_ovs_process_response resp;
+	struct ovsmgr_dp_flow flow;
+	struct net_device *from_dev = NULL;
+	struct net_device *to_dev = NULL;
+
+	DEBUG_CHECK_MAGIC(ecvi, ECM_CLASSIFIER_OVS_INSTANCE_MAGIC, "%px: invalid state magic\n", ecvi);
+
+	/*
+	 * Not relevant to the connection if not enabled.
+	 */
+	if (unlikely(!ecm_classifier_ovs_enabled)) {
+		/*
+		 * Not relevant.
+		 */
+		DEBUG_WARN("%px: ovs classifier is not enabled\n", aci);
+		goto not_relevant;
+	}
+
+	/*
+	 * Get connection
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(ecvi->ci_serial);
+	if (!ci) {
+		/*
+		 * Connection has gone from under us
+		 */
+		DEBUG_WARN("%px: connection instance gone while processing classifier\n", aci);
+		goto not_relevant;
+	}
+
+#ifdef ECM_MULTICAST_ENABLE
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+	if (ecm_ip_addr_is_multicast(dst_ip)) {
+		ecm_classifier_ovs_process_multicast(ci, skb, ecvi, process_response);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+#endif
+
+	/*
+	 * Get the possible OVS bridge ports. If both are NULL, the classifier is not
+	 * relevant to this connection.
+	 */
+	from_dev = ecm_classifier_ovs_interface_get_and_ref(ci, ECM_DB_OBJ_DIR_FROM, true);
+	to_dev = ecm_classifier_ovs_interface_get_and_ref(ci, ECM_DB_OBJ_DIR_TO, true);
+	if (!from_dev && !to_dev) {
+		/*
+		 * So, the classifier is not relevant to this connection.
+		 */
+		DEBUG_WARN("%px: None of the from/to interfaces are OVS bridge port\n", aci);
+		ecm_db_connection_deref(ci);
+		goto not_relevant;
+	}
+
+	/*
+	 * Is there an external callback to get the ovs value from the packet?
+	 */
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	cb = ovs.ovs_process;
+	if (!cb) {
+		/*
+		 * Allow acceleration.
+		 * Keep the classifier relevant to connection for stats update..
+		 */
+		spin_unlock_bh(&ecm_classifier_ovs_lock);
+		DEBUG_WARN("%px: No external process callback set\n", aci);
+		if (from_dev)
+			dev_put(from_dev);
+
+		if (to_dev)
+			dev_put(to_dev);
+
+		spin_lock_bh(&ecm_classifier_ovs_lock);
+		goto allow_accel;
+	}
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+
+	/*
+	 * If the flow is a routed flow, set the is_routed flag of the flow.
+	 */
+	if (ecm_db_connection_is_routed_get(ci)) {
+		ecm_classifier_ovs_process_route_flow(ecvi, ci, skb, from_dev, to_dev, process_response, cb);
+
+		if (from_dev)
+			dev_put(from_dev);
+
+		if (to_dev)
+			dev_put(to_dev);
+
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	memset(&flow, 0, sizeof(struct ovsmgr_dp_flow));
+
+	/*
+	 * If the connection is a bridge flow, both devices should be present.
+	 * TODO: This is an unexpected situation and should be assertion.
+	 * We should also make sure that both devices are on the same OVS bridge.
+	 */
+	if (!from_dev || !to_dev) {
+		DEBUG_ERROR("%px: One of the ports is NULL from_dev: %px to_dev: %px\n", aci, from_dev, to_dev);
+
+		if (from_dev)
+			dev_put(from_dev);
+
+		if (to_dev)
+			dev_put(to_dev);
+
+		ecm_db_connection_deref(ci);
+		goto not_relevant;
+	}
+
+	/*
+	 * Flow is an OVS bridge flow.
+	 */
+	flow.tuple.ip_version = ecm_db_connection_ip_version_get(ci);
+	flow.tuple.protocol = ecm_db_connection_protocol_get(ci);
+
+	/*
+	 * For the flow lookup, we need to use the  proper 5-tuple, in/out dev and
+	 * src/dest MAC address. If the packet is coming from the destination side of the connection
+	 * (e.g: ACK packets of the TCP connection) these values should be reversed.
+	 */
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		DEBUG_TRACE("%px: sender is SRC\n", aci);
+		flow.indev = from_dev;
+		flow.outdev = to_dev;
+
+		flow.tuple.src_port = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+		flow.tuple.dst_port = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO));
+
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, flow.smac);
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, flow.dmac);
+	} else {
+		DEBUG_TRACE("%px: sender is DEST\n", aci);
+		flow.indev = to_dev;
+		flow.outdev = from_dev;
+
+		flow.tuple.src_port = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO));
+		flow.tuple.dst_port = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, src_ip);
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, dst_ip);
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, flow.smac);
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, flow.dmac);
+
+	}
+
+	if (flow.tuple.ip_version == 4) {
+		ECM_IP_ADDR_TO_NIN4_ADDR(flow.tuple.ipv4.src, src_ip);
+		ECM_IP_ADDR_TO_NIN4_ADDR(flow.tuple.ipv4.dst, dst_ip);
+	} else if (flow.tuple.ip_version == 6) {
+		ECM_IP_ADDR_TO_NIN6_ADDR(flow.tuple.ipv6.src, src_ip);
+		ECM_IP_ADDR_TO_NIN6_ADDR(flow.tuple.ipv6.dst, dst_ip);
+	} else {
+		DEBUG_ASSERT(NULL, "%px: unexpected ip_version: %d", aci, flow.tuple.ip_version );
+	}
+
+	memset(&resp, 0, sizeof(struct ecm_classifier_ovs_process_response));
+
+	/*
+	 * Set default values for flow and return DSCP.
+	 * External module will call the DSCP query twice to
+	 * find both directions' values.
+	 */
+	resp.flow_dscp = OVSMGR_INVALID_DSCP;
+	resp.return_dscp = OVSMGR_INVALID_DSCP;
+
+	/*
+	 * Call the external callback and get the result.
+	 */
+	result = cb(&flow, skb, &resp);
+
+	if (from_dev)
+		dev_put(from_dev);
+
+	if (to_dev)
+		dev_put(to_dev);
+
+	/*
+	 * Handle the result
+	 */
+	switch (result) {
+	case ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_ACCEL:
+	case ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_QINQ_ACCEL:
+		/*
+		 * Allow accel after setting the external module response.
+		 */
+		DEBUG_WARN("%px: External callback process succeeded\n", aci);
+
+		spin_lock_bh(&ecm_classifier_ovs_lock);
+		ecvi->process_response.ingress_vlan_tag[0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+		ecvi->process_response.egress_vlan_tag[0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+		ecvi->process_response.ingress_vlan_tag[1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+		ecvi->process_response.egress_vlan_tag[1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+
+		/*
+		 * Primary VLAN tag is always present even it is QinQ.
+		 */
+		ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG;
+
+		/*
+		 * If the sender type is source, which means the packet is coming from the originator,
+		 * we assign the ECM-ingress<>OVS-ingress, ECM-egress<>OVS-egress values.
+		 */
+		if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+			if (resp.ingress_vlan[0].h_vlan_TCI) {
+				ecvi->process_response.ingress_vlan_tag[0] = resp.ingress_vlan[0].h_vlan_encapsulated_proto << 16 | resp.ingress_vlan[0].h_vlan_TCI;
+				DEBUG_TRACE("Ingress vlan tag[0] set : 0x%x\n", ecvi->process_response.ingress_vlan_tag[0]);
+			}
+
+			if (resp.egress_vlan[0].h_vlan_TCI) {
+				ecvi->process_response.egress_vlan_tag[0] = resp.egress_vlan[0].h_vlan_encapsulated_proto << 16 | resp.egress_vlan[0].h_vlan_TCI;
+				DEBUG_TRACE("Egress vlan tag[0] set : 0x%x\n", ecvi->process_response.egress_vlan_tag[0]);
+			}
+
+			if (result == ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_QINQ_ACCEL) {
+				if (resp.ingress_vlan[1].h_vlan_TCI) {
+					ecvi->process_response.ingress_vlan_tag[1] = resp.ingress_vlan[1].h_vlan_encapsulated_proto << 16 | resp.ingress_vlan[1].h_vlan_TCI;
+					DEBUG_TRACE("Ingress vlan tag[0] set : 0x%x\n", ecvi->process_response.ingress_vlan_tag[1]);
+				}
+
+				if (resp.egress_vlan[1].h_vlan_TCI) {
+					ecvi->process_response.egress_vlan_tag[1] = resp.egress_vlan[1].h_vlan_encapsulated_proto << 16 | resp.egress_vlan[1].h_vlan_TCI;
+					DEBUG_TRACE("Egress vlan tag[1] set : 0x%x\n", ecvi->process_response.egress_vlan_tag[1]);
+				}
+
+				/*
+				 * QinQ tag is present. Let's pass this information to the frontend through the process action flag.
+				 */
+				ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG;
+			}
+		} else {
+			/*
+			 * Sender type is destination, which means packet si coming from the counter originator side,
+			 * we assign the ECM-ingress<>OVS-egress and ECM-egress<>OVS-ingress values.
+			 */
+			if (resp.ingress_vlan[0].h_vlan_TCI) {
+				ecvi->process_response.egress_vlan_tag[0] = resp.ingress_vlan[0].h_vlan_encapsulated_proto << 16 | resp.ingress_vlan[0].h_vlan_TCI;
+				DEBUG_TRACE("Egress vlan tag[0] set : 0x%x\n", ecvi->process_response.egress_vlan_tag[0]);
+			}
+
+			if (resp.egress_vlan[0].h_vlan_TCI) {
+				ecvi->process_response.ingress_vlan_tag[0] = resp.egress_vlan[0].h_vlan_encapsulated_proto << 16 | resp.egress_vlan[0].h_vlan_TCI;
+				DEBUG_TRACE("Ingress vlan tag[0] set : 0x%x\n", ecvi->process_response.ingress_vlan_tag[0]);
+			}
+
+			if (result == ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_QINQ_ACCEL) {
+				if (resp.ingress_vlan[1].h_vlan_TCI) {
+					ecvi->process_response.egress_vlan_tag[1] = resp.ingress_vlan[1].h_vlan_encapsulated_proto << 16 | resp.ingress_vlan[1].h_vlan_TCI;
+					DEBUG_TRACE("Egress vlan tag[0] set : 0x%x\n", ecvi->process_response.egress_vlan_tag[1]);
+				}
+
+				if (resp.egress_vlan[1].h_vlan_TCI) {
+					ecvi->process_response.ingress_vlan_tag[1] = resp.egress_vlan[1].h_vlan_encapsulated_proto << 16 | resp.egress_vlan[1].h_vlan_TCI;
+					DEBUG_TRACE("Ingress vlan tag[1] set : 0x%x\n", ecvi->process_response.ingress_vlan_tag[1]);
+				}
+
+				/*
+				 * QinQ tag is present. Let's pass this information to the frontend through the process action flag.
+				 */
+				ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG;
+			}
+		}
+
+		break;
+
+	case ECM_CLASSIFIER_OVS_RESULT_DENY_ACCEL:
+		/*
+		 * External callback failed to process VLAN process. So, let's deny the acceleration
+		 * and try more with the subsequent packets.
+		 */
+		DEBUG_WARN("%px: External callback failed to process VLAN tags\n", aci);
+		goto deny_accel;
+
+	case ECM_CLASSIFIER_OVS_RESULT_ALLOW_ACCEL:
+
+		/*
+		 * There is no VLAN tag in the flow. Just allow the acceleration.
+		 */
+		DEBUG_WARN("%px: External callback didn't find any VLAN relation\n", aci);
+		spin_lock_bh(&ecm_classifier_ovs_lock);
+		break;
+
+	default:
+		DEBUG_ASSERT(false, "Unhandled result: %d\n", result);
+	}
+
+	/*
+	 * If external module set any of the flow or return DSCP,
+	 * we copy them to the classifier's process response based
+	 * on the direction of the traffic. The external module
+	 * should always set first the flow and then the return values.
+	 */
+	if ((resp.flow_dscp != OVSMGR_INVALID_DSCP) || (resp.return_dscp != OVSMGR_INVALID_DSCP)) {
+		if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+			/*
+			 * Copy DSCP values
+			 */
+			ecvi->process_response.flow_dscp = (resp.flow_dscp != OVSMGR_INVALID_DSCP) ? resp.flow_dscp >> XT_DSCP_SHIFT : 0;
+			ecvi->process_response.return_dscp = (resp.return_dscp != OVSMGR_INVALID_DSCP) ? resp.return_dscp >> XT_DSCP_SHIFT : ecvi->process_response.flow_dscp;
+			DEBUG_TRACE("FLOW DSCP: 0x%x RETURN DSCP: 0x%x\n",
+					ecvi->process_response.flow_dscp, ecvi->process_response.return_dscp);
+		} else {
+			/*
+			 * Copy DSCP values
+			 */
+			ecvi->process_response.flow_dscp = (resp.return_dscp != OVSMGR_INVALID_DSCP) ? resp.return_dscp >> XT_DSCP_SHIFT : 0;
+			ecvi->process_response.return_dscp = (resp.flow_dscp != OVSMGR_INVALID_DSCP) ? resp.flow_dscp >> XT_DSCP_SHIFT : ecvi->process_response.flow_dscp;
+			DEBUG_TRACE("FLOW DSCP: 0x%x RETURN DSCP: 0x%x\n",
+					ecvi->process_response.flow_dscp, ecvi->process_response.return_dscp);
+		}
+		ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+	}
+
+allow_accel:
+	/*
+	 * Acceleration is permitted
+	 */
+	ecvi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	ecvi->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	ecvi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+
+	*process_response = ecvi->process_response;
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+	ecm_db_connection_deref(ci);
+	return;
+
+not_relevant:
+	/*
+	 * ecm_classifier_ovs_lock MUST be held
+	 */
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	ecvi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+	*process_response = ecvi->process_response;
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+	return;
+
+deny_accel:
+	/*
+	 * ecm_classifier_ovs_lock MUST be held
+	 */
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	ecvi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	ecvi->process_response.process_actions = ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	ecvi->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+	*process_response = ecvi->process_response;
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_classifier_ovs_type_get()
+ *	Get type of classifier this is
+ */
+static ecm_classifier_type_t ecm_classifier_ovs_type_get(struct ecm_classifier_instance *aci)
+{
+	struct ecm_classifier_ovs_instance *ecvi;
+	ecvi = (struct ecm_classifier_ovs_instance *)aci;
+
+	DEBUG_CHECK_MAGIC(ecvi, ECM_CLASSIFIER_OVS_INSTANCE_MAGIC, "%px: magic failed", ecvi);
+	return ECM_CLASSIFIER_TYPE_OVS;
+}
+
+/*
+ * ecm_classifier_ovs_reclassify_allowed()
+ *	Get whether reclassification is allowed
+ */
+static bool ecm_classifier_ovs_reclassify_allowed(struct ecm_classifier_instance *aci)
+{
+	struct ecm_classifier_ovs_instance *ecvi;
+	ecvi = (struct ecm_classifier_ovs_instance *)aci;
+
+	DEBUG_CHECK_MAGIC(ecvi, ECM_CLASSIFIER_OVS_INSTANCE_MAGIC, "%px: magic failed", ecvi);
+	return true;
+}
+
+/*
+ * ecm_classifier_ovs_reclassify()
+ *	Reclassify
+ */
+static void ecm_classifier_ovs_reclassify(struct ecm_classifier_instance *aci)
+{
+	struct ecm_classifier_ovs_instance *ecvi;
+	ecvi = (struct ecm_classifier_ovs_instance *)aci;
+	DEBUG_CHECK_MAGIC(ecvi, ECM_CLASSIFIER_OVS_INSTANCE_MAGIC, "%px: magic failed", ecvi);
+
+	/*
+	 * Revert back to MAYBE relevant - we will evaluate when we get the next process() call.
+	 */
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	ecvi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_MAYBE;
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+}
+
+/*
+ * ecm_classifier_ovs_last_process_response_get()
+ *	Get result code returned by the last process call
+ */
+static void ecm_classifier_ovs_last_process_response_get(struct ecm_classifier_instance *aci,
+	struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_ovs_instance *ecvi;
+	ecvi = (struct ecm_classifier_ovs_instance *)aci;
+	DEBUG_CHECK_MAGIC(ecvi, ECM_CLASSIFIER_OVS_INSTANCE_MAGIC, "%px: magic failed", ecvi);
+
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	*process_response = ecvi->process_response;
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+}
+
+/*
+ * ecm_classifier_ovs_stats_sync()
+ *	Sync the stats of the OVS flow.
+ */
+static inline void ecm_classifier_ovs_stats_sync(struct ovsmgr_dp_flow *flow,
+					  uint32_t pkts, uint32_t bytes,
+					  struct net_device *indev, struct net_device *outdev,
+					  uint8_t *smac, uint8_t *dmac,
+					  ip_addr_t sip, ip_addr_t dip,
+					  uint16_t sport, uint16_t dport, uint16_t tci, uint16_t tpid)
+{
+	struct ovsmgr_dp_flow_stats stats;
+
+	flow->indev = indev;
+	flow->outdev = outdev;
+
+	ether_addr_copy(flow->smac, smac);
+	ether_addr_copy(flow->dmac, dmac);
+
+	/*
+	 * Set default VLAN tci and vlan encapsulated proto.
+	 */
+	flow->ingress_vlan.h_vlan_TCI = 0;
+	flow->ingress_vlan.h_vlan_encapsulated_proto = 0;
+
+	if (tci) {
+		flow->ingress_vlan.h_vlan_TCI = tci;
+		flow->ingress_vlan.h_vlan_encapsulated_proto = tpid;
+	}
+
+	flow->tuple.src_port = sport;
+	flow->tuple.dst_port = dport;
+
+	if (flow->tuple.ip_version == 4) {
+		ECM_IP_ADDR_TO_NIN4_ADDR(flow->tuple.ipv4.src, sip);
+		ECM_IP_ADDR_TO_NIN4_ADDR(flow->tuple.ipv4.dst, dip);
+		DEBUG_TRACE("%px: STATS: src MAC: %pM src_dev: %s src: %pI4:%d proto: %d dest: %pI4:%d dest_dev: %s dest MAC: %pM TCI: %x, TPID: %x\n",
+				flow, flow->smac, flow->indev->name, &flow->tuple.ipv4.src, flow->tuple.src_port, flow->tuple.protocol,
+				&flow->tuple.ipv4.dst, flow->tuple.dst_port, flow->outdev->name, flow->dmac,
+				flow->ingress_vlan.h_vlan_TCI, flow->ingress_vlan.h_vlan_encapsulated_proto);
+	} else {
+		ECM_IP_ADDR_TO_NIN6_ADDR(flow->tuple.ipv6.src, sip);
+		ECM_IP_ADDR_TO_NIN6_ADDR(flow->tuple.ipv6.dst, dip);
+		DEBUG_TRACE("%px: STATS: src MAC: %pM src_dev: %s src: %pI6:%d proto: %d dest: %pI6:%d dest_dev: %s dest MAC: %pM, TCI: %x, TPID: %x\n",
+				flow, flow->smac, flow->indev->name, &flow->tuple.ipv6.src, flow->tuple.src_port, flow->tuple.protocol,
+				&flow->tuple.ipv6.dst, flow->tuple.dst_port, flow->outdev->name, flow->dmac,
+				flow->ingress_vlan.h_vlan_TCI, flow->ingress_vlan.h_vlan_encapsulated_proto);
+	}
+
+	/*
+	 * Set the flow stats and update the flow database.
+	 */
+	stats.pkts = pkts;
+	stats.bytes = bytes;
+
+	ovsmgr_flow_stats_update(flow, &stats);
+}
+
+#ifdef ECM_MULTICAST_ENABLE
+/*
+ * ecm_classifier_ovs_multicast_sync_to_stats()
+ *	Common multicast sync_to function for IPv4 and IPv6.
+ */
+static void ecm_classifier_ovs_multicast_sync_to_stats(struct ecm_classifier_ovs_instance *ecvi,
+					struct ecm_db_connection_instance *ci, struct ecm_classifier_rule_sync *sync)
+{
+	struct net_device *from_dev;
+	struct net_device *to_ovs_port[ECM_DB_MULTICAST_IF_MAX];
+	struct net_device *to_ovs_brdev[ECM_DB_MULTICAST_IF_MAX];
+	struct net_device *br_dev;
+	ip_addr_t src_ip;
+	ip_addr_t dst_ip;
+	uint8_t smac[ETH_ALEN];
+	uint8_t dmac[ETH_ALEN];
+	uint16_t sport;
+	uint16_t dport;
+	struct ovsmgr_dp_flow flow;
+	int if_cnt, i, valid_ifcnt = 0, ifindex;
+	uint16_t tpid = 0, tci = 0;
+
+	/*
+	 * Get the possible OVS bridge ports.
+	 */
+	from_dev = ecm_classifier_ovs_interface_get_and_ref(ci, ECM_DB_OBJ_DIR_FROM, true);
+	if_cnt = ecm_interface_multicast_ovs_to_interface_get_and_ref(ci, to_ovs_port, to_ovs_brdev);
+	if (!from_dev && !if_cnt) {
+		DEBUG_WARN("%px: None of the from/to interfaces is OVS bridge port\n", ci);
+		return;
+	}
+
+	memset(&flow, 0, sizeof(flow));
+
+	/*
+	 * IP version and protocol are common for routed and bridge flows.
+	 */
+	flow.tuple.ip_version = ecm_db_connection_ip_version_get(ci);
+	flow.tuple.protocol = ecm_db_connection_protocol_get(ci);
+	flow.is_routed = ecm_db_connection_is_routed_get(ci);
+	if (!flow.is_routed) {
+		/* For multicast bridge flows, ovs creates a single rule with multiple
+		 * egress interfaces. We need only one egress interface to sync the flow statistics.
+		 *
+		 * Sync the flow direction.
+		 * eth1 to eth2
+		 */
+		sport = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+		dport = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO));
+
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, smac);
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, dmac);
+
+		if (ecvi->process_response.ingress_vlan_tag[0] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+			tci = ecvi->process_response.ingress_vlan_tag[0] & 0xffff;
+			tpid = (ecvi->process_response.ingress_vlan_tag[0] >> 16) & 0xffff;
+			DEBUG_TRACE("%px: Ingress VLAN : %x:%x\n", ci, tci, tpid);
+		}
+
+		ecm_classifier_ovs_stats_sync(&flow,
+				sync->rx_packet_count[ECM_CONN_DIR_FLOW], sync->rx_byte_count[ECM_CONN_DIR_FLOW],
+				from_dev, to_ovs_port[0],
+				smac, dmac,
+				src_ip, dst_ip,
+				sport, dport, tci, tpid);
+
+		goto done;
+	}
+
+	/*
+	 * The 'to' interfaces ports can be part of different OVS bridges.
+	 * ovs-br1-(eth0, eth1, eth2)
+	 * ovs-br2-(eth3)
+	 * ovs-br3 (eth4, eth5)
+	 *
+	 * Find unique ovs port and ovs bridge combination, as for statistics
+	 * update we need only one port from each OVS bridge.
+	 *
+	 * The logic will derive the below output for the
+	 * above mentioned ovs 'to' interface list.
+	 * to_ovs_port: eth0, eth3, eth4
+	 * to_ovs_brdev: ovs-br1, ovs-br2, ovs-br3
+	 *
+	 */
+	if (if_cnt) {
+		ifindex = to_ovs_brdev[0]->ifindex;
+		for (i = 1, valid_ifcnt = 1; i < if_cnt; i++) {
+			if (ifindex == to_ovs_brdev[i]->ifindex) {
+				dev_put(to_ovs_port[i]);
+				continue;
+			}
+
+			to_ovs_port[valid_ifcnt] = to_ovs_port[i];
+			to_ovs_brdev[valid_ifcnt] = to_ovs_brdev[i];
+			valid_ifcnt++;
+		}
+	}
+
+	/*
+	 * For routed flows below configurations are possible.
+	 *
+	 * 1. From interface is OVS bridge port, to interface is
+	 * another OVS bridge port
+	 * PC1 -----> eth1-ovs-br1--->ovs-br2-eth2----->PC2
+	 *
+	 * 2. From interface is OVS bridge port, multiple to
+	 * OVS bridge port (OVS master is same).
+	 * PC1 -----> eth1-ovs-br1--->ovs-br2-eth2,eth3----->PC2
+	 *
+	 * 3. From interface is OVS bridge port, multiple to
+	 * OVS bridge port (OVS masters are different).
+	 * PC1 -----> eth1-ovs-br1--->ovs-br2-eth2/ovs-br3-eth3----->PC2
+	 */
+	if (from_dev) {
+		/*
+		 * from_dev = eth1
+		 * br_dev = ovs-br1
+		 */
+		br_dev = ecm_classifier_ovs_interface_get_and_ref(ci, ECM_DB_OBJ_DIR_FROM, false);
+		if (!br_dev) {
+			DEBUG_WARN("%px: from_dev = %s is a OVS bridge port, bridge interface is not found\n",
+					ci, from_dev->name);
+			goto done;
+		}
+
+		/*
+		 * Sync the flow direction.
+		 * eth1 to ovs-br1
+		 */
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, smac);
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, dmac);
+
+		sport = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+		dport = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO));
+
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+
+		if (ecvi->process_response.ingress_vlan_tag[0] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+			tci = ecvi->process_response.ingress_vlan_tag[0] & 0xffff;
+			tpid = (ecvi->process_response.ingress_vlan_tag[0] >> 16) & 0xffff;
+			DEBUG_TRACE("%px: Ingress VLAN : %x:%x\n", ci, tci, tpid);
+		}
+
+		ecm_classifier_ovs_stats_sync(&flow,
+				sync->rx_packet_count[ECM_CONN_DIR_FLOW], sync->rx_byte_count[ECM_CONN_DIR_FLOW],
+				from_dev, br_dev,
+				smac, dmac,
+				src_ip, dst_ip,
+				sport, dport, tci, tpid);
+		dev_put(br_dev);
+	}
+
+	/*
+	 * For routed flow, to side can be multiple OVS bridge ports and
+	 * the ports can be part of different OVS bridge master.
+	 *
+	 * 1. outdev = eth2
+	 * indev = ovs-br2
+	 * Sync the flow direction.
+	 * ovs-br2 to eth2
+	 *
+	 * 2. outdev = eth3
+	 * indev = ovs-br2
+	 * Sync the flow direction.
+	 * ovs-br2 to eth3
+	 *
+	 * 3. outdev = eth3
+	 * indev = ovs-br3
+	 * Sync the flow direction.
+	 * ovs-br3 to eth3
+	 *
+	 */
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, dmac);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+	for (i = 0; i < valid_ifcnt; i++) {
+		ether_addr_copy(smac, to_ovs_brdev[i]->dev_addr);
+
+		sport = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+		dport = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO));
+
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+
+		/*
+		 * tci and tpid is 0 for pkts received from ovs bridge
+		 */
+		tci = tpid = 0;
+
+		ecm_classifier_ovs_stats_sync(&flow,
+				sync->rx_packet_count[ECM_CONN_DIR_FLOW], sync->rx_byte_count[ECM_CONN_DIR_FLOW],
+				to_ovs_brdev[i], to_ovs_port[i],
+				smac, dmac,
+				src_ip, dst_ip,
+				sport, dport, tci, tpid);
+	}
+
+done:
+	if (from_dev)
+		dev_put(from_dev);
+
+	for (i = 0; i < valid_ifcnt; i++) {
+		dev_put(to_ovs_port[i]);
+	}
+}
+#endif
+
+/*
+ * ecm_classifier_ovs_sync_to_stats()
+ *	Common sync_to function for IPv4 and IPv6.
+ */
+static void ecm_classifier_ovs_sync_to_stats(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	ip_addr_t src_ip;
+	ip_addr_t dst_ip;
+	struct ecm_db_connection_instance *ci;
+	struct ovsmgr_dp_flow flow;
+	struct net_device *from_dev;
+	struct net_device *to_dev;
+	struct net_device *br_dev;
+	uint8_t smac[ETH_ALEN];
+	uint8_t dmac[ETH_ALEN];
+	uint16_t sport;
+	uint16_t dport;
+	uint16_t tpid = 0, tci = 0;
+
+	struct ecm_classifier_ovs_instance *ecvi = (struct ecm_classifier_ovs_instance *)aci;
+
+	DEBUG_CHECK_MAGIC(ecvi, ECM_CLASSIFIER_OVS_INSTANCE_MAGIC, "%px: magic failed", ecvi);
+
+	ci = ecm_db_connection_serial_find_and_ref(ecvi->ci_serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: No ci found for %u\n", ecvi, ecvi->ci_serial);
+		return;
+	}
+
+#ifdef ECM_MULTICAST_ENABLE
+	/*
+	 * Check for multicast connection.
+	 */
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+	if (ecm_ip_addr_is_multicast(dst_ip)) {
+		ecm_classifier_ovs_multicast_sync_to_stats(ecvi, ci, sync);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+#endif
+	memset(&flow, 0, sizeof(flow));
+
+	/*
+	 * Get the possible OVS bridge ports.
+	 */
+	from_dev = ecm_classifier_ovs_interface_get_and_ref(ci, ECM_DB_OBJ_DIR_FROM, true);
+	to_dev = ecm_classifier_ovs_interface_get_and_ref(ci, ECM_DB_OBJ_DIR_TO, true);
+
+	/*
+	 * IP version and protocol are common for routed and bridge flows.
+	 */
+	flow.tuple.ip_version = ecm_db_connection_ip_version_get(ci);
+	flow.tuple.protocol = ecm_db_connection_protocol_get(ci);
+	flow.is_routed = ecm_db_connection_is_routed_get(ci);
+
+	/*
+	 * Get the tci and tpid values of the ingress side of the flow.
+	 */
+	if (ecvi->process_response.ingress_vlan_tag[0] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+		tci = ecvi->process_response.ingress_vlan_tag[0] & 0xffff;
+		tpid = (ecvi->process_response.ingress_vlan_tag[0] >> 16) & 0xffff;
+		DEBUG_TRACE("%px: Ingress VLAN : %x:%x\n", aci, tci, tpid);
+	}
+
+	/*
+	 * Bridge flow
+	 */
+	if (!flow.is_routed) {
+		/*
+		 * Sync the flow direction (eth1 to eth2)
+		 *
+		 * ECM depends on netdev private flags to identify
+		 * if it is an OVS port, if the port is removed from
+		 * bridge while traffic is running then the device is
+		 * not part of bridge.  Do not update statistics if ports
+		 * are removed from bridge.
+		 */
+		if (!from_dev || !to_dev) {
+			ecm_db_connection_deref(ci);
+			return;
+		}
+
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, smac);
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, dmac);
+
+		sport = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+		dport = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO));
+
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+
+		DEBUG_TRACE("%px: Flow direction stats update\n", aci);
+		ecm_classifier_ovs_stats_sync(&flow,
+				  sync->rx_packet_count[ECM_CONN_DIR_FLOW], sync->rx_byte_count[ECM_CONN_DIR_FLOW],
+				  from_dev, to_dev,
+				  smac, dmac,
+				  src_ip, dst_ip,
+				  sport, dport, tci, tpid);
+
+		/*
+		 * Sync the return direction (eth2 to eth1)
+		 * All the flow parameters are reversed.
+		 */
+		DEBUG_TRACE("%px: Return direction stats update\n", aci);
+
+		/*
+		 * Reset the tci and tpid values and get the egress side of the flow.
+		 */
+		tci = tpid = 0;
+		if (ecvi->process_response.egress_vlan_tag[0] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+			tci = ecvi->process_response.egress_vlan_tag[0] & 0xffff;
+			tpid = (ecvi->process_response.egress_vlan_tag[0] >> 16) & 0xffff;
+			DEBUG_TRACE("%px: Egress VLAN : %x:%x\n", aci, tci, tpid);
+		}
+
+		ecm_classifier_ovs_stats_sync(&flow,
+				  sync->rx_packet_count[ECM_CONN_DIR_RETURN], sync->rx_byte_count[ECM_CONN_DIR_RETURN],
+				  to_dev, from_dev,
+				  dmac, smac,
+				  dst_ip, src_ip,
+				  dport, sport, tci, tpid);
+		goto done;
+	}
+
+	/*
+	 * For routed flows both from and to side can be OVS bridge port, if there
+	 * is a routed flow between two OVS bridges. (e.g: ovs-br1 and ovs-br2)
+	 *
+	 * These are the netdevice places and the IP address values based on the
+	 * 4 different NAT cases.
+	 *
+	 * SNAT:
+	 * PC1 -----> eth1-ovs-br1--->ovs-br2-eth2 -----> PC2
+	 *		(from_dev)	(to_dev)
+	 * src_ip			src_ip_nat	dest_ip/dest_ip_nat
+	 *
+	 * DNAT
+	 * PC1 <----- eth1-ovs-br1<---ovs-br2-eth2 <----- PC2
+	 *		(to_dev)	(from_dev)
+	 * dest_ip			dest_ip_nat	src_ip/src_ip_nat
+	 *
+	 * Non-NAT - Egress
+	 * PC1 -----> eth1-ovs-br1--->ovs-br2-eth2 -----> PC2
+	 *		(from_dev)	(to_dev)
+	 * src_ip/src_ip_nat				dest_ip/dest_ip_nat
+	 *
+	 * Non-NAT - Ingress
+	 * PC1 <----- eth1-ovs-br1<---ovs-br2-eth2 <----- PC2
+	 *		(to_dev)	(from_dev)
+	 * dest_ip/dest_ip_nat				src_ip/src_ip_nat
+	 */
+	if (from_dev) {
+		/*
+		 * from_dev = eth1/eth2  (can be tagged)
+		 * br_dev = ovs-br1/ovs_br2 (untagged)
+		 */
+		br_dev = ecm_classifier_ovs_interface_get_and_ref(ci, ECM_DB_OBJ_DIR_FROM, false);
+		if (!br_dev) {
+			DEBUG_WARN("%px: from_dev = %s is a OVS bridge port, bridge interface is not found\n",
+					aci, from_dev->name);
+			goto done;
+		}
+
+		/*
+		 * Sync the flow direction (eth1/eth2 to ovs-br1/ovs_br2) based on the NAT case.
+		 */
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, smac);
+		ether_addr_copy(dmac, br_dev->dev_addr);
+
+		/*
+		 * If from_dev is a bridge port, dest_ip_nat and dest_port_nat satisfies all the NAT cases.
+		 * So, we need to get the ECM_DB_OBJ_DIR_TO_NAT direction's IP and port number from the connection.
+		 */
+		sport = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+		dport = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO_NAT));
+
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO_NAT, dst_ip);
+
+		ecm_classifier_ovs_stats_sync(&flow,
+				  sync->rx_packet_count[ECM_CONN_DIR_FLOW], sync->rx_byte_count[ECM_CONN_DIR_FLOW],
+				  from_dev, br_dev,
+				  smac, dmac,
+				  src_ip, dst_ip,
+				  sport, dport, tci, tpid);
+
+		/*
+		 * Sync the return direction (ovs-br1/ovs_br2 to eth1/eth2) based on the NAT case.
+		 * All the flow parameters are reversed.
+		 */
+		ecm_classifier_ovs_stats_sync(&flow,
+				  sync->tx_packet_count[ECM_CONN_DIR_FLOW], sync->tx_byte_count[ECM_CONN_DIR_FLOW],
+				  br_dev, from_dev,
+				  dmac, smac,
+				  dst_ip, src_ip,
+				  dport, sport, 0, 0);
+		dev_put(br_dev);
+	}
+
+	if (to_dev) {
+		/*
+		 * to_dev = eth2/eth1 (can be tagged)
+		 * br_dev = ovs-br2/ovs-br1 (untagged)
+		 */
+		br_dev = ecm_classifier_ovs_interface_get_and_ref(ci, ECM_DB_OBJ_DIR_TO, false);
+		if (!br_dev) {
+			DEBUG_WARN("%px: to_dev = %s is a OVS bridge port, bridge interface is not found\n",
+					aci, to_dev->name);
+			goto done;
+		}
+
+		/*
+		 * Reset the tci and tpid values and get the egress side of the flow.
+		 */
+		tci = tpid = 0;
+		if (ecvi->process_response.egress_vlan_tag[0] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+			tci = ecvi->process_response.egress_vlan_tag[0] & 0xffff;
+			tpid = (ecvi->process_response.egress_vlan_tag[0] >> 16) & 0xffff;
+			DEBUG_TRACE("%px: Egress VLAN : %x:%x\n", aci, tci, tpid);
+		}
+
+		/*
+		 * Sync the flow direction (ovs-br2/ovs_br1 to eth2/eth1) based on the NAT case.
+		 */
+		ether_addr_copy(smac, br_dev->dev_addr);
+		ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, dmac);
+
+		/*
+		 * If to_dev is a bridge port, src_ip_nat and src_port_nat satisfies all the NAT cases.
+		 * So, we need to get the ECM_DB_OBJ_DIR_FROM_NAT direction's IP and port number from the connection.
+		 */
+		sport = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM_NAT));
+		dport = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO));
+
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM_NAT, src_ip);
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+
+		ecm_classifier_ovs_stats_sync(&flow,
+				  sync->tx_packet_count[ECM_CONN_DIR_RETURN], sync->tx_byte_count[ECM_CONN_DIR_RETURN],
+				  br_dev, to_dev,
+				  smac, dmac,
+				  src_ip, dst_ip,
+				  sport, dport, 0, 0);
+		/*
+		 * Sync the return direction (eth2/eth1 to ovs-br2/ovs-br1) based on the NAT case.
+		 * All the flow parameters are reversed.
+		 */
+		ecm_classifier_ovs_stats_sync(&flow,
+				  sync->rx_packet_count[ECM_CONN_DIR_RETURN], sync->rx_byte_count[ECM_CONN_DIR_RETURN],
+				  to_dev, br_dev,
+				  dmac, smac,
+				  dst_ip, src_ip,
+				  dport, sport, tci, tpid);
+		dev_put(br_dev);
+	}
+
+done:
+	ecm_db_connection_deref(ci);
+
+	if (from_dev)
+		dev_put(from_dev);
+	if (to_dev)
+		dev_put(to_dev);
+}
+
+/*
+ * ecm_classifier_ovs_sync_to_v4()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_ovs_sync_to_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	/*
+	 * Nothing to update.
+	 * We only care about flows that are actively being accelerated.
+	 */
+	if (!(sync->tx_packet_count[ECM_CONN_DIR_FLOW] || sync->tx_packet_count[ECM_CONN_DIR_RETURN])) {
+		return;
+	}
+
+	/*
+	 * Handle only the stats sync. We don't care about the evict or flush syncs.
+	 */
+	if (sync->reason != ECM_FRONT_END_IPV4_RULE_SYNC_REASON_STATS) {
+		return;
+	}
+
+	/*
+	 * Common sync_to function call.
+	 */
+	ecm_classifier_ovs_sync_to_stats(aci, sync);
+}
+
+/*
+ * ecm_classifier_ovs_sync_from_v4()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_ovs_sync_from_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_ovs_instance *ecvi __attribute__((unused));
+
+	ecvi = (struct ecm_classifier_ovs_instance *)aci;
+	DEBUG_CHECK_MAGIC(ecvi, ECM_CLASSIFIER_OVS_INSTANCE_MAGIC, "%px: magic failed", ecvi);
+}
+
+/*
+ * ecm_classifier_ovs_sync_to_v6()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_ovs_sync_to_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	/*
+	 * Nothing to update.
+	 * We only care about flows that are actively being accelerated.
+	 */
+	if (!(sync->tx_packet_count[ECM_CONN_DIR_FLOW] || sync->tx_packet_count[ECM_CONN_DIR_RETURN])) {
+		return;
+	}
+
+	/*
+	 * Handle only the stats sync. We don't care about the evict or flush syncs.
+	 */
+	if (sync->reason != ECM_FRONT_END_IPV6_RULE_SYNC_REASON_STATS) {
+		return;
+	}
+
+	/*
+	 * Common sync_to function call.
+	 */
+	ecm_classifier_ovs_sync_to_stats(aci, sync);
+}
+
+/*
+ * ecm_classifier_ovs_sync_from_v6()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_ovs_sync_from_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_ovs_instance *ecvi __attribute__((unused));
+
+	ecvi = (struct ecm_classifier_ovs_instance *)aci;
+	DEBUG_CHECK_MAGIC(ecvi, ECM_CLASSIFIER_OVS_INSTANCE_MAGIC, "%px: magic failed", ecvi);
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_classifier_ovs_state_get()
+ *	Gets the state of this classfier and outputs it to debugfs.
+ */
+static int ecm_classifier_ovs_state_get(struct ecm_classifier_instance *ci, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	struct ecm_classifier_ovs_instance *ecvi;
+	struct ecm_classifier_process_response pr;
+
+	ecvi = (struct ecm_classifier_ovs_instance *)ci;
+	DEBUG_CHECK_MAGIC(ecvi, ECM_CLASSIFIER_OVS_INSTANCE_MAGIC, "%px: magic failed", ecvi);
+
+	if ((result = ecm_state_prefix_add(sfi, "ovs"))) {
+		return result;
+	}
+
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	pr = ecvi->process_response;
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+
+	/*
+	 * Output our last process response
+	 */
+	if ((result = ecm_classifier_process_response_state_get(sfi, &pr))) {
+		goto done;
+	}
+
+
+	if (pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG) {
+#ifdef ECM_MULTICAST_ENABLE
+		int i;
+#endif
+		/*
+		 * TODO: Clean up the function later to print classifier
+		 * specific data in each classifier’s state_get function.
+		 */
+		if (pr.ingress_vlan_tag[0] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+			if ((result = ecm_state_write(sfi, "ingress_vlan_tag[0]", "0x%x", pr.ingress_vlan_tag[0]))) {
+				goto done;
+			}
+		}
+
+		if (pr.ingress_vlan_tag[1] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+			if ((result = ecm_state_write(sfi, "ingress_vlan_tag[1]", "0x%x", pr.ingress_vlan_tag[1]))) {
+				goto done;
+			}
+		}
+
+		if (pr.egress_vlan_tag[0] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+			if ((result = ecm_state_write(sfi, "egress_vlan_tag[0]", "0x%x", pr.egress_vlan_tag[0]))) {
+				goto done;
+			}
+		}
+
+		if (pr.egress_vlan_tag[1] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+			if ((result = ecm_state_write(sfi, "egress_vlan_tag[1]", "0x%x", pr.egress_vlan_tag[1]))) {
+				goto done;
+			}
+		}
+
+#ifdef ECM_MULTICAST_ENABLE
+		for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+			struct net_device *dev;
+
+			if (pr.egress_mc_vlan_tag[i][0] == ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+				continue;
+			}
+
+			dev = dev_get_by_index(&init_net, pr.egress_netdev_index[i]);
+			if (dev) {
+				if ((result = ecm_state_write(sfi, "port_egress", "%s", dev->name))) {
+					dev_put(dev);
+					goto done;
+				}
+				dev_put(dev);
+			}
+
+			if ((result = ecm_state_write(sfi, "port_egress_vlan_tag[0]", "0x%x", pr.egress_mc_vlan_tag[i][0]))) {
+				goto done;
+			}
+
+			if (pr.egress_mc_vlan_tag[i][1] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+				if ((result = ecm_state_write(sfi, "port_egress_vlan_tag[1]", "0x%x", pr.egress_mc_vlan_tag[i][1]))) {
+					goto done;
+				}
+			}
+		}
+#endif
+	}
+
+done:
+	ecm_state_prefix_remove(sfi);
+	return result;
+}
+#endif
+
+/*
+ * ecm_classifier_ovs_instance_alloc()
+ *	Allocate an instance of the ovs classifier
+ */
+struct ecm_classifier_ovs_instance *ecm_classifier_ovs_instance_alloc(struct ecm_db_connection_instance *ci)
+{
+	struct ecm_classifier_ovs_instance *ecvi;
+#ifdef ECM_MULTICAST_ENABLE
+	int i;
+#endif
+
+	/*
+	 * Allocate the instance
+	 */
+	ecvi = (struct ecm_classifier_ovs_instance *)kzalloc(sizeof(struct ecm_classifier_ovs_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!ecvi) {
+		DEBUG_WARN("i%px: Failed to allocate ovs Classifier instance\n", ci);
+		return NULL;
+	}
+
+	DEBUG_SET_MAGIC(ecvi, ECM_CLASSIFIER_OVS_INSTANCE_MAGIC);
+	ecvi->refs = 1;
+
+	/*
+	 * Methods generic to all classifiers.
+	 */
+	ecvi->base.process = ecm_classifier_ovs_process;
+	ecvi->base.sync_from_v4 = ecm_classifier_ovs_sync_from_v4;
+	ecvi->base.sync_to_v4 = ecm_classifier_ovs_sync_to_v4;
+	ecvi->base.sync_from_v6 = ecm_classifier_ovs_sync_from_v6;
+	ecvi->base.sync_to_v6 = ecm_classifier_ovs_sync_to_v6;
+	ecvi->base.type_get = ecm_classifier_ovs_type_get;
+	ecvi->base.reclassify_allowed = ecm_classifier_ovs_reclassify_allowed;
+	ecvi->base.reclassify = ecm_classifier_ovs_reclassify;
+	ecvi->base.last_process_response_get = ecm_classifier_ovs_last_process_response_get;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ecvi->base.state_get = ecm_classifier_ovs_state_get;
+#endif
+	ecvi->base.ref = ecm_classifier_ovs_ref;
+	ecvi->base.deref = ecm_classifier_ovs_deref;
+	ecvi->ci_serial = ecm_db_connection_serial_get(ci);
+
+	ecvi->process_response.process_actions = 0;
+	ecvi->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_MAYBE;
+	ecvi->process_response.ingress_vlan_tag[0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	ecvi->process_response.egress_vlan_tag[0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	ecvi->process_response.ingress_vlan_tag[1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	ecvi->process_response.egress_vlan_tag[1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+
+#ifdef ECM_MULTICAST_ENABLE
+	for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+		ecvi->process_response.egress_mc_vlan_tag[i][0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+		ecvi->process_response.egress_mc_vlan_tag[i][1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	}
+#endif
+
+	/*
+	 * Final check if we are pending termination
+	 */
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	if (ecm_classifier_ovs_terminate_pending) {
+		spin_unlock_bh(&ecm_classifier_ovs_lock);
+		DEBUG_WARN("%px: Terminating\n", ci);
+		kfree(ecvi);
+		return NULL;
+	}
+
+	/*
+	 * Link the new instance into our list at the head
+	 */
+	ecvi->next = ecm_classifier_ovs_instances;
+	if (ecm_classifier_ovs_instances) {
+		ecm_classifier_ovs_instances->prev = ecvi;
+	}
+	ecm_classifier_ovs_instances = ecvi;
+
+	/*
+	 * Increment stats
+	 */
+	ecm_classifier_ovs_count++;
+	DEBUG_ASSERT(ecm_classifier_ovs_count > 0, "%px: ecm_classifier_ovs_count wrap for instance: %px\n", ci, ecvi);
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+
+	DEBUG_INFO("%px: ovs classifier instance alloc: %px\n", ci, ecvi);
+	return ecvi;
+}
+EXPORT_SYMBOL(ecm_classifier_ovs_instance_alloc);
+
+/*
+ * ecm_classifier_ovs_register_callbacks()
+ */
+int ecm_classifier_ovs_register_callbacks(struct ecm_classifier_ovs_callbacks *ovs_cbs)
+{
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+
+	if (unlikely(!ecm_classifier_ovs_enabled)) {
+		spin_unlock_bh(&ecm_classifier_ovs_lock);
+		return -1;
+	}
+
+	ovs.ovs_process = ovs_cbs->ovs_process;
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_classifier_ovs_register_callbacks);
+
+/*
+ * ecm_classifier_ovs_unregister_callbacks()
+ */
+void ecm_classifier_ovs_unregister_callbacks(void)
+{
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	ovs.ovs_process = NULL;
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+}
+EXPORT_SYMBOL(ecm_classifier_ovs_unregister_callbacks);
+
+/*
+ * ecm_classifier_ovs_init()
+ */
+int ecm_classifier_ovs_init(struct dentry *dentry)
+{
+	DEBUG_INFO("ovs classifier Module init\n");
+
+	ecm_classifier_ovs_dentry = debugfs_create_dir("ecm_classifier_ovs", dentry);
+	if (!ecm_classifier_ovs_dentry) {
+		DEBUG_ERROR("Failed to create ecm ovs directory in debugfs\n");
+		return -1;
+	}
+
+	if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_ovs_dentry,
+					(u32 *)&ecm_classifier_ovs_enabled)) {
+		DEBUG_ERROR("Failed to create ovs enabled file in debugfs\n");
+		debugfs_remove_recursive(ecm_classifier_ovs_dentry);
+		return -1;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_classifier_ovs_init);
+
+/*
+ * ecm_classifier_ovs_exit()
+ */
+void ecm_classifier_ovs_exit(void)
+{
+	DEBUG_INFO("ovs classifier Module exit\n");
+
+	spin_lock_bh(&ecm_classifier_ovs_lock);
+	ecm_classifier_ovs_terminate_pending = true;
+	spin_unlock_bh(&ecm_classifier_ovs_lock);
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_classifier_ovs_dentry) {
+		debugfs_remove_recursive(ecm_classifier_ovs_dentry);
+	}
+
+}
+EXPORT_SYMBOL(ecm_classifier_ovs_exit);
diff --git a/qca-nss-ecm/ecm_classifier_ovs.h b/qca-nss-ecm/ecm_classifier_ovs.h
new file mode 100644
index 0000000..1aaa7b7
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_ovs.h
@@ -0,0 +1,18 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+struct ecm_classifier_ovs_instance;
+struct ecm_classifier_ovs_instance *ecm_classifier_ovs_instance_alloc(struct ecm_db_connection_instance *ci);
diff --git a/qca-nss-ecm/ecm_classifier_ovs_public.h b/qca-nss-ecm/ecm_classifier_ovs_public.h
new file mode 100644
index 0000000..10f7747
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_ovs_public.h
@@ -0,0 +1,57 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * Result values of the external inspection module to the ECM's ovs classifier.
+ * Based on the result the ovs classifier takes the action for the inspected connection.
+ */
+enum ecm_classifier_ovs_results {
+	ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_ACCEL,		/* VLAN process succeeded */
+	ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_QINQ_ACCEL,	/* VLAN process succeeded for QinQ */
+	ECM_CLASSIFIER_OVS_RESULT_ALLOW_ACCEL,			/* No VLAN present, just accelerate */
+	ECM_CLASSIFIER_OVS_RESULT_DENY_ACCEL_EGRESS,		/* Flow egress is not allowed for acceleration */
+	ECM_CLASSIFIER_OVS_RESULT_DENY_ACCEL			/* Do not accelerate */
+};
+typedef enum ecm_classifier_ovs_results ecm_classifier_ovs_result_t;
+
+struct ecm_classifier_ovs_process_response {
+	uint32_t dscp;			/* Used by the routed connections */
+	uint32_t flow_dscp;		/* Bridge connection's flow DSCP value */
+	uint32_t return_dscp;		/* Bridge connection's return DSCP value */
+	struct vlan_hdr ingress_vlan[2];
+					/* Ingress VLAN header */
+	struct vlan_hdr egress_vlan[2];
+					/* Egress VLAN header */
+};
+
+
+/*
+ * Callback function which processes the connection information.
+ */
+typedef ecm_classifier_ovs_result_t (*ecm_classifier_ovs_process_callback_t)(struct ovsmgr_dp_flow *flow,
+									     struct sk_buff *skb,
+									     struct ecm_classifier_ovs_process_response *resp);
+
+struct ecm_classifier_ovs_callbacks {
+	ecm_classifier_ovs_process_callback_t ovs_process;
+};
+
+/*
+ * Register/Unregister callback functions which are called from the external modules.
+ */
+int ecm_classifier_ovs_register_callbacks(struct ecm_classifier_ovs_callbacks *callbacks);
+void ecm_classifier_ovs_unregister_callbacks(void);
+
diff --git a/qca-nss-ecm/ecm_classifier_pcc.c b/qca-nss-ecm/ecm_classifier_pcc.c
new file mode 100644
index 0000000..6c6fcd4
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_pcc.c
@@ -0,0 +1,1261 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * Parental Controls Classifier.
+ * While not implementing parental controls feature itself.
+ * This module provides an interface for customer parental controls systems to interract with the ECM.
+ * This ensures that acceleration will not interfere with parental controls logics, especially DPI.
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/debugfs.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_CLASSIFIER_PCC_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_pcc.h"
+#include "ecm_classifier_pcc_public.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_CLASSIFIER_PCC_INSTANCE_MAGIC 0x2351
+
+/*
+ * struct ecm_classifier_pcc_instance
+ * 	State per connection for PCC classifier
+ */
+struct ecm_classifier_pcc_instance {
+	struct ecm_classifier_instance base;			/* Base type */
+
+	ecm_classifier_pcc_result_t accel_permit_state;		/* Permission state for acceleration */
+	uint32_t ci_serial;					/* RO: Serial of the connection */
+	long process_jiffies_last;				/* Rate limiting the calls to the registrant */
+	uint32_t reg_calls_to;					/* #calls to registrant */
+	uint32_t reg_calls_from;				/* #calls from registrant */
+	uint32_t feature_flags;					/* Feature flags */
+
+	struct ecm_classifier_process_response process_response;
+								/* Last process response computed */
+	int refs;						/* Integer to trap we never go negative */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+static DEFINE_SPINLOCK(ecm_classifier_pcc_lock);		/* Concurrency control SMP access */
+static int ecm_classifier_pcc_count = 0;			/* Tracks number of instances allocated */
+static struct ecm_classifier_pcc_registrant *ecm_classifier_registrant = NULL;
+								/* Singleton Parent Controls code */
+
+/*
+ * Operational control
+ */
+static bool ecm_classifier_pcc_enabled = false;			/* Enable / disable state of the classifier function */
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_classifier_pcc_dentry;
+
+/*
+ * ecm_classifier_pcc_register()
+ *	Register a new PCC module.
+ *
+ */
+int ecm_classifier_pcc_register(struct ecm_classifier_pcc_registrant *r)
+{
+	/*
+	 * Hold the module of the registrant
+	 */
+	if (!try_module_get(r->this_module)) {
+		return -ESHUTDOWN;
+	}
+
+	/*
+	 * Hold the registrant we have been given for our purposes.
+	 */
+	r->ref(r);
+
+	spin_lock_bh(&ecm_classifier_pcc_lock);
+	if (ecm_classifier_registrant) {
+		spin_unlock_bh(&ecm_classifier_pcc_lock);
+		DEBUG_WARN("Registrant already\n");
+		module_put(r->this_module);
+		r->deref(r);
+		return -EALREADY;
+	}
+	ecm_classifier_registrant = r;
+	ecm_classifier_pcc_enabled = true;
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+
+	/*
+	 * Destroy all the connections
+	 */
+	ecm_db_connection_defunct_all();
+	return 0;
+}
+EXPORT_SYMBOL(ecm_classifier_pcc_register);
+
+/*
+ * ecm_classifier_pcc_unregister_begin()
+ *	Begin unregistration process
+ */
+void ecm_classifier_pcc_unregister_begin(struct ecm_classifier_pcc_registrant *r)
+{
+	struct ecm_classifier_pcc_registrant *reg;
+
+	spin_lock_bh(&ecm_classifier_pcc_lock);
+	reg = ecm_classifier_registrant;
+	if (!reg) {
+		spin_unlock_bh(&ecm_classifier_pcc_lock);
+		DEBUG_WARN("No Registrant\n");
+		return;
+	}
+	if (reg != r) {
+		spin_unlock_bh(&ecm_classifier_pcc_lock);
+		DEBUG_WARN("Unexpected registrant, given: %px, expecting: %px\n", r, reg);
+		return;
+	}
+
+	ecm_classifier_registrant = NULL;
+	ecm_classifier_pcc_enabled = false;
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+
+	/*
+	 * Release our ref upon the registrant that we took when it was registered
+	 */
+	reg->deref(reg);
+	module_put(reg->this_module);
+
+	/*
+	 * Destroy all the connections
+	 */
+	ecm_db_connection_defunct_all();
+}
+EXPORT_SYMBOL(ecm_classifier_pcc_unregister_begin);
+
+/*
+ * ecm_classifier_pcc_decel_v4()
+ *	Decelerate connection.
+ *
+ * Big endian parameters apart from protocol
+ */
+bool ecm_classifier_pcc_decel_v4(uint8_t *src_mac, __be32 src_ip, int src_port,
+		uint8_t *dest_mac, __be32 dest_ip, int dest_port, int protocol)
+{
+	/*
+	 * MAC addresses are not used to decelerate the connection, but in the future
+	 * MAC based deceleration can be added to this function.
+	 */
+	return ecm_db_connection_decel_v4(src_ip, src_port, dest_ip, dest_port, protocol);
+}
+EXPORT_SYMBOL(ecm_classifier_pcc_decel_v4);
+
+/*
+ * ecm_classifier_pcc_decel_v6()
+ *	Decelerate connection.
+ *
+ * Big endian parameters apart from protocol
+ */
+bool ecm_classifier_pcc_decel_v6(uint8_t *src_mac, struct in6_addr *src_ip,
+		 int src_port, uint8_t *dest_mac, struct in6_addr *dest_ip,
+		 int dest_port, int protocol)
+{
+	/*
+	 * MAC addresses are not used to decelerate the connection, but in the future
+	 * MAC based deceleration can be added to this function.
+	 */
+	return ecm_db_connection_decel_v6(src_ip, src_port, dest_ip, dest_port, protocol);
+}
+EXPORT_SYMBOL(ecm_classifier_pcc_decel_v6);
+
+/*
+ * ecm_classifier_pcc_permit_accel_v4()
+ *	Permit acceleration.
+ *
+ * Big endian parameters apart from protocol
+ */
+void ecm_classifier_pcc_permit_accel_v4(uint8_t *src_mac, __be32 src_ip, int src_port, uint8_t *dest_mac, __be32 dest_ip, int dest_port, int protocol)
+{
+	ip_addr_t ecm_src_ip;
+	ip_addr_t ecm_dest_ip;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_classifier_instance *classi;
+	struct ecm_classifier_pcc_instance *pcci;
+
+	/*
+	 * Look up ECM connection from the given tuple
+	 */
+	src_port = ntohs(src_port);
+	dest_port = ntohs(dest_port);
+	ECM_NIN4_ADDR_TO_IP_ADDR(ecm_src_ip, src_ip);
+	ECM_NIN4_ADDR_TO_IP_ADDR(ecm_dest_ip, dest_ip);
+
+	DEBUG_INFO("Permit Accel v4, lookup connection using \n"
+			"Protocol: %d\n"
+			"src: " ECM_IP_ADDR_DOT_FMT ":%d\n"
+			"dest: " ECM_IP_ADDR_DOT_FMT ":%d\n",
+			protocol,
+			ECM_IP_ADDR_TO_DOT(ecm_src_ip), src_port,
+			ECM_IP_ADDR_TO_DOT(ecm_dest_ip), dest_port);
+
+	ci = ecm_db_connection_find_and_ref(ecm_src_ip, ecm_dest_ip, protocol, src_port, dest_port);
+	if (!ci) {
+		DEBUG_TRACE("Not found\n");
+		return;
+	}
+
+	/*
+	 * Get the PCC classifier
+	 */
+	classi = ecm_db_connection_assigned_classifier_find_and_ref(ci, ECM_CLASSIFIER_TYPE_PCC);
+	if (!classi) {
+		DEBUG_TRACE("No PCC classi\n");
+		ecm_db_connection_deref(ci);
+		return;
+	}
+	pcci = (struct ecm_classifier_pcc_instance *)classi;
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: magic failed", pcci);
+
+	/*
+	 * Set the permitted accel state to PERMITTED
+	 * NOTE: When we next see activity on this connection it shall be accelerated (save depending on other classifiers decisions too).
+	 */
+	spin_lock_bh(&ecm_classifier_pcc_lock);
+	pcci->accel_permit_state = ECM_CLASSIFIER_PCC_RESULT_PERMITTED;
+	pcci->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	pcci->process_response.process_actions = ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	pcci->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+	pcci->reg_calls_from++;
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+
+	classi->deref(classi);
+	ecm_db_connection_deref(ci);
+}
+EXPORT_SYMBOL(ecm_classifier_pcc_permit_accel_v4);
+
+/*
+ * ecm_classifier_pcc_permit_accel_v6()
+ *	Permit acceleration
+ *
+ * Big endian parameters apart from protocol.
+ *
+ * NOTE: If IPv6 is not supported in ECM this function must still exist as a stub to avoid compilation problems for registrants.
+ */
+void ecm_classifier_pcc_permit_accel_v6(uint8_t *src_mac, struct in6_addr *src_ip, int src_port, uint8_t *dest_mac, struct in6_addr *dest_ip, int dest_port, int protocol)
+{
+#ifdef ECM_IPV6_ENABLE
+	struct in6_addr in6;
+	ip_addr_t ecm_src_ip;
+	ip_addr_t ecm_dest_ip;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_classifier_instance *classi;
+	struct ecm_classifier_pcc_instance *pcci;
+
+	/*
+	 * Look up ECM connection from the given tuple
+	 */
+	src_port = ntohs(src_port);
+	dest_port = ntohs(dest_port);
+	in6 = *src_ip;
+	ECM_NIN6_ADDR_TO_IP_ADDR(ecm_src_ip, in6);
+	in6 = *dest_ip;
+	ECM_NIN6_ADDR_TO_IP_ADDR(ecm_dest_ip, in6);
+
+	DEBUG_INFO("Permit Accel v6, lookup connection using \n"
+			"Protocol: %d\n"
+			"src: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"dest: " ECM_IP_ADDR_OCTAL_FMT ":%d\n",
+			protocol,
+			ECM_IP_ADDR_TO_OCTAL(ecm_src_ip), src_port,
+			ECM_IP_ADDR_TO_OCTAL(ecm_dest_ip), dest_port);
+
+	ci = ecm_db_connection_find_and_ref(ecm_src_ip, ecm_dest_ip, protocol, src_port, dest_port);
+	if (!ci) {
+		DEBUG_TRACE("Not found\n");
+		return;
+	}
+
+	/*
+	 * Get the PCC classifier
+	 */
+	classi = ecm_db_connection_assigned_classifier_find_and_ref(ci, ECM_CLASSIFIER_TYPE_PCC);
+	if (!classi) {
+		DEBUG_TRACE("No PCC classi\n");
+		ecm_db_connection_deref(ci);
+		return;
+	}
+	pcci = (struct ecm_classifier_pcc_instance *)classi;
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: magic failed", pcci);
+
+	/*
+	 * Set the permitted accel state to PERMITTED
+	 * NOTE: When we next see activity on this connection it shall be accelerated (save depending on other classifiers decisions too).
+	 */
+	spin_lock_bh(&ecm_classifier_pcc_lock);
+	pcci->accel_permit_state = ECM_CLASSIFIER_PCC_RESULT_PERMITTED;
+	pcci->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	pcci->process_response.process_actions = ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	pcci->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+	pcci->reg_calls_from++;
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+
+	classi->deref(classi);
+	ecm_db_connection_deref(ci);
+#endif
+}
+EXPORT_SYMBOL(ecm_classifier_pcc_permit_accel_v6);
+
+/*
+ * ecm_classifier_pcc_deny_accel_v4()
+ *	Deny acceleration
+ */
+void ecm_classifier_pcc_deny_accel_v4(uint8_t *src_mac, __be32 src_ip, int src_port, uint8_t *dest_mac, __be32 dest_ip, int dest_port, int protocol)
+{
+	ip_addr_t ecm_src_ip;
+	ip_addr_t ecm_dest_ip;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_classifier_instance *classi;
+	struct ecm_classifier_pcc_instance *pcci;
+	struct ecm_front_end_connection_instance *feci;
+
+	/*
+	 * Look up ECM connection from the given tuple
+	 */
+	src_port = ntohs(src_port);
+	dest_port = ntohs(dest_port);
+	ECM_NIN4_ADDR_TO_IP_ADDR(ecm_src_ip, src_ip);
+	ECM_NIN4_ADDR_TO_IP_ADDR(ecm_dest_ip, dest_ip);
+
+	DEBUG_INFO("Deny Accel v4, lookup connection using \n"
+			"Protocol: %d\n"
+			"src: " ECM_IP_ADDR_DOT_FMT ":%d\n"
+			"dest: " ECM_IP_ADDR_DOT_FMT ":%d\n",
+			protocol,
+			ECM_IP_ADDR_TO_DOT(ecm_src_ip), src_port,
+			ECM_IP_ADDR_TO_DOT(ecm_dest_ip), dest_port);
+
+	ci = ecm_db_connection_find_and_ref(ecm_src_ip, ecm_dest_ip, protocol, src_port, dest_port);
+	if (!ci) {
+		DEBUG_TRACE("Not found\n");
+		return;
+	}
+
+	/*
+	 * Get the PCC classifier
+	 */
+	classi = ecm_db_connection_assigned_classifier_find_and_ref(ci, ECM_CLASSIFIER_TYPE_PCC);
+	if (!classi) {
+		DEBUG_TRACE("No PCC classi\n");
+		ecm_db_connection_deref(ci);
+		return;
+	}
+	pcci = (struct ecm_classifier_pcc_instance *)classi;
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: magic failed", pcci);
+
+	/*
+	 * Set the permitted accel state to DENIED
+	 * NOTE: When we next see activity on this connection it shall be accelerated (save depending on other classifiers decisions too).
+	 */
+	spin_lock_bh(&ecm_classifier_pcc_lock);
+	pcci->accel_permit_state = ECM_CLASSIFIER_PCC_RESULT_DENIED;
+	pcci->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	pcci->process_response.process_actions = ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	pcci->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+	pcci->reg_calls_from++;
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+
+	/*
+	 * Get the front end and issue a deceleration
+	 * If the connection is not accelerated anyway this will have no effect
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	feci->decelerate(feci);
+	feci->deref(feci);
+
+	classi->deref(classi);
+	ecm_db_connection_deref(ci);
+}
+EXPORT_SYMBOL(ecm_classifier_pcc_deny_accel_v4);
+
+/*
+ * ecm_classifier_pcc_deny_accel_v6()
+ *	Deny acceleration
+ *
+ * NOTE: If IPv6 is not supported in ECM this function must still exist as a stub to avoid compilation problems for registrants.
+ */
+void ecm_classifier_pcc_deny_accel_v6(uint8_t *src_mac, struct in6_addr *src_ip, int src_port, uint8_t *dest_mac, struct in6_addr *dest_ip, int dest_port, int protocol)
+{
+#ifdef ECM_IPV6_ENABLE
+	struct in6_addr in6;
+	ip_addr_t ecm_src_ip;
+	ip_addr_t ecm_dest_ip;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_classifier_instance *classi;
+	struct ecm_classifier_pcc_instance *pcci;
+	struct ecm_front_end_connection_instance *feci;
+
+	/*
+	 * Look up ECM connection from the given tuple
+	 */
+	src_port = ntohs(src_port);
+	dest_port = ntohs(dest_port);
+	in6 = *src_ip;
+	ECM_NIN6_ADDR_TO_IP_ADDR(ecm_src_ip, in6);
+	in6 = *dest_ip;
+	ECM_NIN6_ADDR_TO_IP_ADDR(ecm_dest_ip, in6);
+
+	DEBUG_INFO("Deny Accel v6, lookup connection using \n"
+			"Protocol: %d\n"
+			"src: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"dest: " ECM_IP_ADDR_OCTAL_FMT ":%d\n",
+			protocol,
+			ECM_IP_ADDR_TO_OCTAL(ecm_src_ip), src_port,
+			ECM_IP_ADDR_TO_OCTAL(ecm_dest_ip), dest_port);
+
+	ci = ecm_db_connection_find_and_ref(ecm_src_ip, ecm_dest_ip, protocol, src_port, dest_port);
+	if (!ci) {
+		DEBUG_TRACE("Not found\n");
+		return;
+	}
+
+	/*
+	 * Get the PCC classifier
+	 */
+	classi = ecm_db_connection_assigned_classifier_find_and_ref(ci, ECM_CLASSIFIER_TYPE_PCC);
+	if (!classi) {
+		DEBUG_TRACE("No PCC classi\n");
+		ecm_db_connection_deref(ci);
+		return;
+	}
+	pcci = (struct ecm_classifier_pcc_instance *)classi;
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: magic failed", pcci);
+
+	/*
+	 * Set the permitted accel state to DENIED
+	 * NOTE: When we next see activity on this connection it shall be accelerated (save depending on other classifiers decisions too).
+	 */
+	spin_lock_bh(&ecm_classifier_pcc_lock);
+	pcci->accel_permit_state = ECM_CLASSIFIER_PCC_RESULT_DENIED;
+	pcci->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	pcci->process_response.process_actions = ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	pcci->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+	pcci->reg_calls_from++;
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+
+	/*
+	 * Get the front end and issue a deceleration
+	 * If the connection is not accelerated anyway this will have no effect
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	feci->decelerate(feci);
+	feci->deref(feci);
+
+	classi->deref(classi);
+	ecm_db_connection_deref(ci);
+#endif
+}
+EXPORT_SYMBOL(ecm_classifier_pcc_deny_accel_v6);
+
+/*
+ * ecm_classifier_pcc_unregister_force()
+ *	Unregister the registrant, if any
+ */
+static void ecm_classifier_pcc_unregister_force(struct ecm_classifier_pcc_instance *pcci)
+{
+	struct ecm_classifier_pcc_registrant *reg;
+
+	spin_lock_bh(&ecm_classifier_pcc_lock);
+	reg = ecm_classifier_registrant;
+	if (!reg) {
+		spin_unlock_bh(&ecm_classifier_pcc_lock);
+		return;
+	}
+	ecm_classifier_registrant = NULL;
+	ecm_classifier_pcc_enabled = false;
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+
+	/*
+	 * Release our ref upon the registrant that we took when it was registered
+	 */
+	DEBUG_INFO("Force unregistration of: %px\n", reg);
+	reg->deref(reg);
+
+	/*
+	 * Release hold on registrant module
+	 */
+	module_put(reg->this_module);
+
+	/*
+	 * Destroy all the connections
+	 */
+	ecm_db_connection_defunct_all();
+}
+
+/*
+ * _ecm_classifier_pcc_ref()
+ *	Ref
+ */
+static void _ecm_classifier_pcc_ref(struct ecm_classifier_pcc_instance *pcci)
+{
+	pcci->refs++;
+	DEBUG_TRACE("%px: pcci ref %d\n", pcci, pcci->refs);
+	DEBUG_ASSERT(pcci->refs > 0, "%px: ref wrap\n", pcci);
+}
+
+/*
+ * ecm_classifier_pcc_ref()
+ *	Ref
+ */
+static void ecm_classifier_pcc_ref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_pcc_instance *pcci;
+	pcci = (struct ecm_classifier_pcc_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: magic failed", pcci);
+	spin_lock_bh(&ecm_classifier_pcc_lock);
+	_ecm_classifier_pcc_ref(pcci);
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+}
+
+/*
+ * ecm_classifier_pcc_deref()
+ *	Deref
+ */
+static int ecm_classifier_pcc_deref(struct ecm_classifier_instance *ci)
+{
+	struct ecm_classifier_pcc_instance *pcci;
+	pcci = (struct ecm_classifier_pcc_instance *)ci;
+
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: magic failed", pcci);
+	spin_lock_bh(&ecm_classifier_pcc_lock);
+	pcci->refs--;
+	DEBUG_ASSERT(pcci->refs >= 0, "%px: refs wrapped\n", pcci);
+	DEBUG_TRACE("%px: Parental Controls classifier deref %d\n", pcci, pcci->refs);
+	if (pcci->refs) {
+		int refs = pcci->refs;
+		spin_unlock_bh(&ecm_classifier_pcc_lock);
+		return refs;
+	}
+
+	/*
+	 * Object to be destroyed
+	 */
+	ecm_classifier_pcc_count--;
+	DEBUG_ASSERT(ecm_classifier_pcc_count >= 0, "%px: ecm_classifier_pcc_count wrap\n", pcci);
+
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+
+	/*
+	 * Final
+	 */
+	DEBUG_INFO("%px: Final Parental Controls classifier instance\n", pcci);
+	kfree(pcci);
+
+	return 0;
+}
+
+/*
+ * ecm_classifier_pcc_get_mirror_info()
+ *	Get mirroring related information.
+ */
+static int ecm_classifier_pcc_get_mirror_info(struct ecm_classifier_pcc_info cinfo,
+		 int *flow_mirror_ifindex_ptr, int *return_mirror_ifindex_ptr)
+{
+	struct net_device *flow_dev = cinfo.mirror.tuple_mirror_dev;
+	struct net_device *return_dev = cinfo.mirror.tuple_ret_mirror_dev;
+
+	if (!flow_dev && !return_dev) {
+		DEBUG_ERROR("No mirror net devices are specified\n");
+		return -1;
+	}
+
+	/*
+	 * Fetch mirror interface information.
+	 */
+	if (flow_dev) {
+		dev_hold(flow_dev);
+		*flow_mirror_ifindex_ptr = flow_dev->ifindex;
+		dev_put(flow_dev);
+	}
+
+	if (return_dev) {
+		dev_hold(return_dev);
+		*return_mirror_ifindex_ptr = return_dev->ifindex;
+		dev_put(return_dev);
+	}
+
+	return 0;
+}
+
+/*
+ * ecm_classifier_pcc_process()
+ *	Process new packet
+ *
+ * NOTE: This function would only ever be called if all other classifiers have failed.
+ */
+static void ecm_classifier_pcc_process(struct ecm_classifier_instance *aci, ecm_tracker_sender_type_t sender,
+									struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb,
+									struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_pcc_instance *pcci = (struct ecm_classifier_pcc_instance *)aci;
+	ecm_classifier_pcc_result_t accel_permit_state;
+	ecm_classifier_pcc_result_t reg_result;
+	struct ecm_db_connection_instance *ci;
+	long jiffies_now;
+	int ip_version;
+	uint8_t src_mac[ETH_ALEN];
+	uint8_t dest_mac[ETH_ALEN];
+	int protocol;
+	int src_port;
+	int dst_port;
+	ip_addr_t src_ip;
+	ip_addr_t dst_ip;
+	struct ecm_classifier_pcc_registrant *registrant;
+	struct ecm_classifier_pcc_info cinfo = {0};
+	int flow_mirror_ifindex = -1;
+	int return_mirror_ifindex = -1;
+
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: invalid state magic\n", pcci);
+
+	/*
+	 * Get connection
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(pcci->ci_serial);
+	if (!ci) {
+		/*
+		 * Connection has gone from under us
+		 */
+		spin_lock_bh(&ecm_classifier_pcc_lock);
+		goto not_relevant;
+	}
+
+	/*
+	 * Early detection of DNS server port
+	 */
+	dst_port = ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO);
+
+	spin_lock_bh(&ecm_classifier_pcc_lock);
+
+	/*
+	 * Not relevant to the connection if not enabled.
+	 */
+	if (unlikely(!ecm_classifier_pcc_enabled)) {
+		/*
+		 * Not relevant.
+		 */
+		goto not_relevant;
+	}
+
+	/*
+	 * What is our acceleration permit state?
+	 * If it is something other than ECM_CLASSIFIER_PCC_RESULT_NOT_YET then we have a definitive result already.
+	 */
+	accel_permit_state = pcci->accel_permit_state;
+	if (accel_permit_state != ECM_CLASSIFIER_PCC_RESULT_NOT_YET) {
+		*process_response = pcci->process_response;
+		spin_unlock_bh(&ecm_classifier_pcc_lock);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	/*
+	 * If the destination port is to DNS server then we implicitly deny acceleration
+	 */
+	if (dst_port == 53) {
+		/*
+		 * By setting the permit state to DENIED we will always deny from this point on
+		 */
+		pcci->accel_permit_state = ECM_CLASSIFIER_PCC_RESULT_DENIED;
+		goto deny_accel;
+	}
+
+	/*
+	 * We need to call to the registrant BUT we cannot do this at a rate that exceeds 1/sec
+	 * NOTE: Not worried about wrap around, it's only one second.
+	 */
+	jiffies_now = jiffies;
+	if ((jiffies_now - pcci->process_jiffies_last) < HZ) {
+		/*
+		 * We cannot permit acceleration just yet
+		 * Deny accel but don't change the permit state - we try again later
+		 */
+		goto deny_accel;
+	}
+	pcci->process_jiffies_last = jiffies_now;
+
+	/*
+	 * We have to call out to our registrant to see if we can get permission to accelerate.
+	 * Get our registrant
+	 */
+	registrant = ecm_classifier_registrant;
+	registrant->ref(registrant);
+
+	/*
+	 * Bump reg calls made to the registrant.
+	 */
+	pcci->reg_calls_to++;
+
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+
+	/*
+	 * See if we can hold the registrant module - it may be unloading.
+	 */
+	if (!try_module_get(registrant->this_module)) {
+		/*
+		 * Module is unloading.
+		 */
+		registrant->deref(registrant);
+
+		/*
+		 * Force unregistration
+		 */
+		ecm_classifier_pcc_unregister_force(pcci);
+
+		/*
+		 * We are implicitly "not relevant".
+		 */
+		spin_lock_bh(&ecm_classifier_pcc_lock);
+		goto not_relevant;
+	}
+
+	/*
+	 * Ask the registrant if we may accelerate (big endian)
+	 */
+	ip_version = ecm_db_connection_ip_version_get(ci);
+	protocol = ecm_db_connection_protocol_get(ci);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	src_port = htons(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+	dst_port = htons(dst_port);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_mac);
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, dest_mac);
+
+	/*
+	 * Default is permitted in case ip_version is unsupported here
+	 */
+	reg_result = ECM_CLASSIFIER_PCC_RESULT_PERMITTED;
+	if (ip_version == 4) {
+		__be32 src_ip4;
+		__be32 dest_ip4;
+
+		ECM_IP_ADDR_TO_NIN4_ADDR(src_ip4, src_ip);
+		ECM_IP_ADDR_TO_NIN4_ADDR(dest_ip4, dst_ip);
+
+		/*
+		 * get_accel_info_v4 callback has higher priority over
+		 * okay_to_accel_v4 callback.
+		 * get_accel_info_v4 callback is the advance version of older
+		 * okay_to_accel_v4 callback, from which the registrant can not
+		 * only can tell the final acceleration decision about the flow but
+		 * can also request for additional features like mirroring.
+		 * get_accel_info_v4 callback is also backward compatible, means
+		 * it can be used by the registrant for only specifying acceleration
+		 * decisions.
+		 */
+		if (registrant->get_accel_info_v4){
+			reg_result = registrant->get_accel_info_v4(registrant,
+					 src_mac, src_ip4, src_port, dest_mac,
+					 dest_ip4, dst_port, protocol, &cinfo);
+			pcci->feature_flags = cinfo.feature_flags;
+		} else {
+			reg_result = registrant->okay_to_accel_v4(registrant,
+					 src_mac, src_ip4, src_port, dest_mac,
+					 dest_ip4, dst_port, protocol);
+			pcci->feature_flags = ECM_CLASSIFIER_PCC_FEATURE_NONE;
+		}
+	}
+#ifdef ECM_IPV6_ENABLE
+	if (ip_version == 6) {
+		struct in6_addr src_ip6;
+		struct in6_addr dest_ip6;
+		ECM_IP_ADDR_TO_NIN6_ADDR(src_ip6, src_ip);
+		ECM_IP_ADDR_TO_NIN6_ADDR(dest_ip6, dst_ip);
+
+		/*
+		 * get_accel_info_v6 callback has higher priority over
+		 * okay_to_accel_v6 callback.
+		 * get_accel_info_v6 callback is the advance version of older
+		 * okay_to_accel_v6 callback, from which the registrant can not
+		 * only can tell the final acceleration decision about the flow but
+		 * can also request for additional features like mirroring.
+		 * get_accel_info_v6 callback is also backward compatible, means
+		 * it can be used by the registrant for only specifying acceleration
+		 * decisions.
+		 */
+		if (registrant->get_accel_info_v6){
+			reg_result = registrant->get_accel_info_v6(registrant,
+					 src_mac, &src_ip6, src_port, dest_mac,
+					 &dest_ip6, dst_port, protocol, &cinfo);
+			pcci->feature_flags = cinfo.feature_flags;
+		} else {
+			reg_result = registrant->okay_to_accel_v6(registrant,
+					 src_mac, &src_ip6, src_port, dest_mac,
+					 &dest_ip6, dst_port, protocol);
+			pcci->feature_flags = ECM_CLASSIFIER_PCC_FEATURE_NONE;
+		}
+	}
+#endif
+
+	/*
+	 * Release the ref taken for this call
+	 */
+	registrant->deref(registrant);
+
+	/*
+	 * Release the module ref taken.
+	 */
+	module_put(registrant->this_module);
+
+	/*
+	 * Handle the features requested by registrants, if any.
+	 */
+	if (cinfo.feature_flags & ECM_CLASSIFIER_PCC_FEATURE_MIRROR) {
+		if (ecm_classifier_pcc_get_mirror_info(cinfo, &flow_mirror_ifindex,
+					&return_mirror_ifindex) < 0) {
+			spin_lock_bh(&ecm_classifier_pcc_lock);
+			goto deny_accel;
+		}
+	}
+
+	/*
+	 * Handle the result
+	 */
+	switch (reg_result) {
+	case ECM_CLASSIFIER_PCC_RESULT_NOT_YET:
+		/*
+		 * Deny accel but don't change the permit state - we try again later
+		 */
+		spin_lock_bh(&ecm_classifier_pcc_lock);
+		goto deny_accel;
+	case ECM_CLASSIFIER_PCC_RESULT_DENIED:
+		/*
+		 * Deny accel and set the permit state to denied - this connection is denied from this point on.
+		 */
+		spin_lock_bh(&ecm_classifier_pcc_lock);
+		pcci->accel_permit_state = ECM_CLASSIFIER_PCC_RESULT_DENIED;
+		goto deny_accel;
+	case ECM_CLASSIFIER_PCC_RESULT_PERMITTED:
+		break;
+	default:
+		DEBUG_ASSERT(false, "Unhandled result: %d\n", reg_result);
+	}
+
+	/*
+	 * Acceleration is permitted
+	 */
+	spin_lock_bh(&ecm_classifier_pcc_lock);
+
+	/*
+	 * Fill mirror information in the process response.
+	 */
+	if (cinfo.feature_flags & ECM_CLASSIFIER_PCC_FEATURE_MIRROR) {
+		pcci->process_response.flow_mirror_ifindex = flow_mirror_ifindex;
+		pcci->process_response.return_mirror_ifindex = return_mirror_ifindex;
+		pcci->process_response.process_actions |=
+			 ECM_CLASSIFIER_PROCESS_ACTION_MIRROR_ENABLED;
+	}
+
+	pcci->accel_permit_state = ECM_CLASSIFIER_PCC_RESULT_PERMITTED;
+	pcci->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	pcci->process_response.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	pcci->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+	*process_response = pcci->process_response;
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+	ecm_db_connection_deref(ci);
+
+	return;
+
+not_relevant:
+
+	/*
+	 * ecm_classifier_pcc_lock MUST be held
+	 */
+	pcci->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_NO;
+	pcci->process_response.process_actions = 0;
+	*process_response = pcci->process_response;
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+	if (ci) {
+		ecm_db_connection_deref(ci);
+	}
+	return;
+
+deny_accel:
+
+	/*
+	 * ecm_classifier_pcc_lock MUST be held
+	 */
+	pcci->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+	pcci->process_response.process_actions = ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE;
+	pcci->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+	*process_response = pcci->process_response;
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+	ecm_db_connection_deref(ci);
+	return;
+
+}
+
+/*
+ * ecm_classifier_pcc_type_get()
+ *	Get type of classifier this is
+ */
+static ecm_classifier_type_t ecm_classifier_pcc_type_get(struct ecm_classifier_instance *aci)
+{
+	struct ecm_classifier_pcc_instance *pcci;
+	pcci = (struct ecm_classifier_pcc_instance *)aci;
+
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: magic failed", pcci);
+	return ECM_CLASSIFIER_TYPE_PCC;
+}
+
+/*
+ * ecm_classifier_pcc_reclassify_allowed()
+ *	Get whether reclassification is allowed
+ */
+static bool ecm_classifier_pcc_reclassify_allowed(struct ecm_classifier_instance *aci)
+{
+	struct ecm_classifier_pcc_instance *pcci;
+	pcci = (struct ecm_classifier_pcc_instance *)aci;
+
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: magic failed", pcci);
+	return true;
+}
+
+/*
+ * ecm_classifier_pcc_reclassify()
+ *	Reclassify
+ */
+static void ecm_classifier_pcc_reclassify(struct ecm_classifier_instance *aci)
+{
+	struct ecm_classifier_pcc_instance *pcci;
+	pcci = (struct ecm_classifier_pcc_instance *)aci;
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: magic failed", pcci);
+
+	/*
+	 * Connection needs to be reset to 'as new'
+	 * NOTE: Implicitly the connection would have been decelerated now so we don't need to worry about that.
+	 */
+	spin_lock_bh(&ecm_classifier_pcc_lock);
+	pcci->accel_permit_state = ECM_CLASSIFIER_PCC_RESULT_NOT_YET;
+
+	/*
+	 * Reset jiffies for rate limiting registrant calls
+	 */
+	pcci->process_jiffies_last = jiffies;
+
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+}
+
+/*
+ * ecm_classifier_pcc_last_process_response_get()
+ *	Get result code returned by the last process call
+ */
+static void ecm_classifier_pcc_last_process_response_get(struct ecm_classifier_instance *aci,
+							struct ecm_classifier_process_response *process_response)
+{
+	struct ecm_classifier_pcc_instance *pcci;
+	pcci = (struct ecm_classifier_pcc_instance *)aci;
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: magic failed", pcci);
+
+	spin_lock_bh(&ecm_classifier_pcc_lock);
+	*process_response = pcci->process_response;
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+}
+
+/*
+ * ecm_classifier_pcc_sync_to_v4()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_pcc_sync_to_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	struct ecm_classifier_pcc_instance *pcci __attribute__((unused));
+
+	pcci = (struct ecm_classifier_pcc_instance *)aci;
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: magic failed", pcci);
+}
+
+/*
+ * ecm_classifier_pcc_sync_from_v4()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_pcc_sync_from_v4(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_pcc_instance *pcci __attribute__((unused));
+
+	pcci = (struct ecm_classifier_pcc_instance *)aci;
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: magic failed", pcci);
+}
+
+/*
+ * ecm_classifier_pcc_sync_to_v6()
+ *	Front end is pushing accel engine state to us
+ */
+static void ecm_classifier_pcc_sync_to_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_sync *sync)
+{
+	struct ecm_classifier_pcc_instance *pcci __attribute__((unused));
+
+	pcci = (struct ecm_classifier_pcc_instance *)aci;
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: magic failed", pcci);
+}
+
+/*
+ * ecm_classifier_pcc_sync_from_v6()
+ *	Front end is retrieving accel engine state from us
+ */
+static void ecm_classifier_pcc_sync_from_v6(struct ecm_classifier_instance *aci, struct ecm_classifier_rule_create *ecrc)
+{
+	struct ecm_classifier_pcc_instance *pcci __attribute__((unused));
+
+	pcci = (struct ecm_classifier_pcc_instance *)aci;
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: magic failed", pcci);
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_classifier_pcc_state_get()
+ *	Return state
+ */
+static int ecm_classifier_pcc_state_get(struct ecm_classifier_instance *ci, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	struct ecm_classifier_pcc_instance *pcci;
+	struct ecm_classifier_process_response process_response;
+	ecm_classifier_pcc_result_t accel_permit_state;
+	uint32_t reg_calls_to;
+	uint32_t reg_calls_from;
+	uint32_t feature_flags;
+
+	pcci = (struct ecm_classifier_pcc_instance *)ci;
+	DEBUG_CHECK_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC, "%px: magic failed", pcci);
+
+	if ((result = ecm_state_prefix_add(sfi, "pcc"))) {
+		return result;
+	}
+
+	spin_lock_bh(&ecm_classifier_pcc_lock);
+	accel_permit_state = pcci->accel_permit_state;
+	process_response = pcci->process_response;
+	reg_calls_to = pcci->reg_calls_to;
+	reg_calls_from = pcci->reg_calls_from;
+	feature_flags = pcci->feature_flags;
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+
+	if ((result = ecm_state_write(sfi, "accel_permit_state", "%d", accel_permit_state))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "reg_calls_to", "%d", reg_calls_to))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "reg_calls_from", "%d", reg_calls_from))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "feature_flags", "0x%x", feature_flags))) {
+		return result;
+	}
+
+	if (process_response.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_MIRROR_ENABLED) {
+		struct net_device *dev;
+
+		if ((dev = dev_get_by_index(&init_net, process_response.flow_mirror_ifindex))) {
+			if ((result = ecm_state_write(sfi, "flow_mirror", "%s",
+							dev->name))) {
+				dev_put(dev);
+				return result;
+			}
+			dev_put(dev);
+		}
+
+		if ((dev = dev_get_by_index(&init_net, process_response.return_mirror_ifindex))) {
+			if ((result = ecm_state_write(sfi, "return_mirror", "%s",
+							dev->name))) {
+				dev_put(dev);
+				return result;
+			}
+			dev_put(dev);
+		}
+	}
+
+	/*
+	 * Output our last process response
+	 */
+	if ((result = ecm_classifier_process_response_state_get(sfi, &process_response))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+/*
+ * ecm_classifier_pcc_instance_alloc()
+ *	Allocate an instance of the Parental Controls classifier
+ */
+struct ecm_classifier_pcc_instance *ecm_classifier_pcc_instance_alloc(struct ecm_db_connection_instance *ci)
+{
+	struct ecm_classifier_pcc_instance *pcci;
+	struct ecm_classifier_instance *cdi;
+
+	/*
+	 * Allocate the instance
+	 */
+	pcci = (struct ecm_classifier_pcc_instance *)kzalloc(sizeof(struct ecm_classifier_pcc_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!pcci) {
+		DEBUG_WARN("Failed to allocate Parental Controls Classifier instance\n");
+		return NULL;
+	}
+
+	DEBUG_SET_MAGIC(pcci, ECM_CLASSIFIER_PCC_INSTANCE_MAGIC);
+	pcci->refs = 1;
+	pcci->ci_serial = ecm_db_connection_serial_get(ci);
+
+	/*
+	 * We are relevant to the connection at this time
+	 */
+	pcci->process_response.relevance = ECM_CLASSIFIER_RELEVANCE_YES;
+
+	/*
+	 * Don't know yet whether we are allowed to accelerate - need to query the registrant
+	 */
+	pcci->accel_permit_state = ECM_CLASSIFIER_PCC_RESULT_NOT_YET;
+
+	/*
+	 * Reset jiffies for rate limiting registrant calls
+	 */
+	pcci->process_jiffies_last = jiffies;
+
+	/*
+	 * Methods generic to all classifiers.
+	 */
+	cdi = (struct ecm_classifier_instance *)pcci;
+	cdi->process = ecm_classifier_pcc_process;
+	cdi->sync_from_v4 = ecm_classifier_pcc_sync_from_v4;
+	cdi->sync_to_v4 = ecm_classifier_pcc_sync_to_v4;
+	cdi->sync_from_v6 = ecm_classifier_pcc_sync_from_v6;
+	cdi->sync_to_v6 = ecm_classifier_pcc_sync_to_v6;
+	cdi->type_get = ecm_classifier_pcc_type_get;
+	cdi->reclassify_allowed = ecm_classifier_pcc_reclassify_allowed;
+	cdi->reclassify = ecm_classifier_pcc_reclassify;
+	cdi->last_process_response_get = ecm_classifier_pcc_last_process_response_get;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	cdi->state_get = ecm_classifier_pcc_state_get;
+#endif
+	cdi->ref = ecm_classifier_pcc_ref;
+	cdi->deref = ecm_classifier_pcc_deref;
+
+	/*
+	 * Increment stats
+	 */
+	spin_lock_bh(&ecm_classifier_pcc_lock);
+	ecm_classifier_pcc_count++;
+	DEBUG_ASSERT(ecm_classifier_pcc_count > 0, "%px: ecm_classifier_pcc_count wrap\n", pcci);
+	spin_unlock_bh(&ecm_classifier_pcc_lock);
+
+	DEBUG_INFO("Parental Controls classifier instance alloc: %px\n", pcci);
+	return pcci;
+}
+EXPORT_SYMBOL(ecm_classifier_pcc_instance_alloc);
+
+/*
+ * ecm_classifier_pcc_init()
+ */
+int ecm_classifier_pcc_init(struct dentry *dentry)
+{
+	DEBUG_INFO("Parental Controls classifier Module init\n");
+
+	ecm_classifier_pcc_dentry = debugfs_create_dir("ecm_classifier_pcc", dentry);
+	if (!ecm_classifier_pcc_dentry) {
+		DEBUG_ERROR("Failed to create ecm pcc directory in debugfs\n");
+		return -1;
+	}
+
+	if (!debugfs_create_u32("enabled", S_IRUGO, ecm_classifier_pcc_dentry,
+					(u32 *)&ecm_classifier_pcc_enabled)) {
+		DEBUG_ERROR("Failed to create pcc enabled file in debugfs\n");
+		debugfs_remove_recursive(ecm_classifier_pcc_dentry);
+		return -1;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_classifier_pcc_init);
+
+/*
+ * ecm_classifier_pcc_exit()
+ */
+void ecm_classifier_pcc_exit(void)
+{
+	DEBUG_INFO("Parental Controls classifier Module exit\n");
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_classifier_pcc_dentry) {
+		debugfs_remove_recursive(ecm_classifier_pcc_dentry);
+	}
+
+}
+EXPORT_SYMBOL(ecm_classifier_pcc_exit);
diff --git a/qca-nss-ecm/ecm_classifier_pcc.h b/qca-nss-ecm/ecm_classifier_pcc.h
new file mode 100644
index 0000000..e5f199a
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_pcc.h
@@ -0,0 +1,18 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+struct ecm_classifier_pcc_instance;
+struct ecm_classifier_pcc_instance *ecm_classifier_pcc_instance_alloc(struct ecm_db_connection_instance *ci);
diff --git a/qca-nss-ecm/ecm_classifier_pcc_public.h b/qca-nss-ecm/ecm_classifier_pcc_public.h
new file mode 100644
index 0000000..5ef7856
--- /dev/null
+++ b/qca-nss-ecm/ecm_classifier_pcc_public.h
@@ -0,0 +1,133 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2021, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * Structure used to synchronise a classifier instance with the state as presented by the accel engine
+ */
+enum ecm_classifier_pcc_results {
+	ECM_CLASSIFIER_PCC_RESULT_NOT_YET,		/* Accel is neither permitted nor denied just yet - try again later */
+	ECM_CLASSIFIER_PCC_RESULT_DENIED,		/* Accel is denied for this connection */
+	ECM_CLASSIFIER_PCC_RESULT_PERMITTED,		/* Accel is permitted for this connection */
+};
+typedef enum ecm_classifier_pcc_results ecm_classifier_pcc_result_t;
+
+/*
+ * Feature flags.
+ *
+ * The registrant(customer) can request multiple features to be enabled on the
+ * connection, using a bitmap of features with the 'ecm_classifier_pcc_info'
+ * object. Note that currently only 'mirror' feature is supported to begin with.
+ */
+enum ecm_classifier_pcc_feature_flags {
+	ECM_CLASSIFIER_PCC_FEATURE_NONE,
+	ECM_CLASSIFIER_PCC_FEATURE_MIRROR = 0x1,	/* Set by customer if mirror is needed on the connection */
+};
+
+/*
+ * Mirror netdevices to be used for mirroring an offloaded flow
+ */
+struct ecm_classifier_pcc_mirror_info {
+	struct net_device *tuple_mirror_dev;	/* Tuple direction mirror netdevice. */
+	struct net_device *tuple_ret_mirror_dev;	/* Tuple return direction mirror netdevice. */
+};
+
+/*
+ * Feature information related to the connection, returned by registrant's callback
+ */
+struct ecm_classifier_pcc_info {
+	uint32_t feature_flags;			/* Bitmap of requested features (ecm_classifier_pcc_feature_ids) */
+	struct ecm_classifier_pcc_mirror_info mirror;
+};
+
+struct ecm_classifier_pcc_registrant;
+
+typedef void (*ecm_classifier_pcc_ref_method_t)(struct ecm_classifier_pcc_registrant *r);
+typedef void (*ecm_classifier_pcc_deref_method_t)(struct ecm_classifier_pcc_registrant *r);
+typedef ecm_classifier_pcc_result_t (*ecm_classifier_pcc_okay_to_accel_v4_method_t)(struct ecm_classifier_pcc_registrant *r, uint8_t *src_mac, __be32 src_ip, int src_port, uint8_t *dest_mac, __be32 dest_ip, int dest_port, int protocol);
+typedef ecm_classifier_pcc_result_t (*ecm_classifier_pcc_okay_to_accel_v6_method_t)(struct ecm_classifier_pcc_registrant *r, uint8_t *src_mac, struct in6_addr *src_ip, int src_port, uint8_t *dest_mac, struct in6_addr *dest_ip, int dest_port, int protocol);
+
+/*
+ * The below two APIs can be used to query the customer's PCC registrant when ECM
+ * is processing the packet. The return value is used to decide whether acceleration
+ * is needed for the conntection or not. Customer can (optionally) also share additional
+ * connection properties to enable for the connection using the object 'cinfo' that is passed
+ * to them. Currently support is present only for one connection property named 'mirror'.
+ * Note: Object pointed to by 'cinfo' is allocated by ECM
+ */
+typedef ecm_classifier_pcc_result_t
+ (*ecm_classifier_pcc_get_accel_info_v4_method_t)(struct ecm_classifier_pcc_registrant *r,
+		  uint8_t *src_mac, __be32 src_ip, int src_port,
+		  uint8_t *dest_mac, __be32 dest_ip, int dest_port,
+		  int protocol, struct ecm_classifier_pcc_info *cinfo);
+
+typedef ecm_classifier_pcc_result_t
+ (*ecm_classifier_pcc_get_accel_info_v6_method_t)(struct ecm_classifier_pcc_registrant *r,
+		  uint8_t *src_mac, struct in6_addr *src_ip, int src_port,
+		  uint8_t *dest_mac, struct in6_addr *dest_ip, int dest_port,
+		  int protocol, struct ecm_classifier_pcc_info *cinfo);
+
+/*
+ * struct ecm_classifier_pcc_registrant
+ *	Used by customer parental control code to register their existance with the ECM PCC classifier
+ */
+struct ecm_classifier_pcc_registrant {
+	uint16_t version;					/* Customer Parental Controls (CPC) supplies 1 for this field. */
+
+	struct ecm_classifier_pcc_registrant *pcc_next;		/* ECM PCC use */
+	struct ecm_classifier_pcc_registrant *pcc_prev;		/* ECM PCC use */
+	uint32_t pcc_flags;					/* ECM PCC use */
+
+	atomic_t ref_count;					/* CPC sets this to 1 initially when registering with ECM.
+								 * PCC takes its own private 'ref' for the registrant so after registering the CPC should 'deref' the initial '1'.
+								 * CPC MUST NOT deallocate this structure until the ref_count is dropped to zero by deref() calls
+								 */
+	struct module *this_module;				/* Pointer to the registrants module */
+
+	ecm_classifier_pcc_ref_method_t ref;			/* When called the ref_count is incremented by 1 */
+	ecm_classifier_pcc_deref_method_t deref;		/* When called the ref_count is decremented by 1.
+								 * When ref_count becomes 0 no further calls will be made upon this registrant
+								 */
+	ecm_classifier_pcc_okay_to_accel_v4_method_t okay_to_accel_v4;
+								/* ECM PCC asks the CPC if the given connection is okay to accelerate */
+	ecm_classifier_pcc_okay_to_accel_v6_method_t okay_to_accel_v6;
+								/* ECM PCC asks the CPC if the given connection is okay to accelerate */
+	ecm_classifier_pcc_get_accel_info_v4_method_t get_accel_info_v4;
+								/* ECM PCC asks the CPC for the acceleration information */
+	ecm_classifier_pcc_get_accel_info_v6_method_t get_accel_info_v6;
+								/* ECM PCC asks the CPC for the acceleration information */
+};
+
+extern int ecm_classifier_pcc_register(struct ecm_classifier_pcc_registrant *r);
+extern void ecm_classifier_pcc_unregister_begin(struct ecm_classifier_pcc_registrant *r);
+
+extern void ecm_classifier_pcc_permit_accel_v4(uint8_t *src_mac, __be32 src_ip, int src_port, uint8_t *dest_mac, __be32 dest_ip, int dest_port, int protocol);
+extern void ecm_classifier_pcc_deny_accel_v4(uint8_t *src_mac, __be32 src_ip, int src_port, uint8_t *dest_mac, __be32 dest_ip, int dest_port, int protocol);
+
+/*
+ * This API can be used to decelerate an existing IPv4 ECM connection.
+ */
+extern bool ecm_classifier_pcc_decel_v4(uint8_t *src_mac, __be32 src_ip, int src_port,
+		 uint8_t *dest_mac, __be32 dest_ip, int dest_port, int protocol);
+
+extern void ecm_classifier_pcc_permit_accel_v6(uint8_t *src_mac, struct in6_addr *src_ip, int src_port, uint8_t *dest_mac, struct in6_addr *dest_ip, int dest_port, int protocol);
+extern void ecm_classifier_pcc_deny_accel_v6(uint8_t *src_mac, struct in6_addr *src_ip, int src_port, uint8_t *dest_mac, struct in6_addr *dest_ip, int dest_port, int protocol);
+
+/*
+ * This API can be used to decelerate an existing IPv6 ECM connection.
+ */
+extern bool ecm_classifier_pcc_decel_v6(uint8_t *src_mac, struct in6_addr *src_ip,
+		 int src_port, uint8_t *dest_mac, struct in6_addr *dest_ip,
+		 int dest_port, int protocol);
diff --git a/qca-nss-ecm/ecm_conntrack_notifier.c b/qca-nss-ecm/ecm_conntrack_notifier.c
new file mode 100644
index 0000000..ff48ef0
--- /dev/null
+++ b/qca-nss-ecm/ecm_conntrack_notifier.c
@@ -0,0 +1,468 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017, 2019-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * ecm_conntrack_notifier.c
+ * 	Conntrack notifier functionality.
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_CONNTRACK_NOTIFIER_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_db.h"
+#include "ecm_front_end_ipv4.h"
+#include "ecm_front_end_ipv6.h"
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+#include "ecm_classifier_nl.h"
+#endif
+
+/*
+ * Locking of the classifier - concurrency control
+ */
+static DEFINE_SPINLOCK(ecm_conntrack_notifier_lock __attribute__((unused)));	/* Protect against SMP access between netfilter, events and private threaded function. */
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_conntrack_notifier_dentry;
+
+/*
+ * General operational control
+ */
+static int ecm_conntrack_notifier_stopped = 0;	/* When non-zero further traffic will not be processed */
+
+#ifdef ECM_IPV6_ENABLE
+/*
+ * ecm_conntrack_ipv6_event_destroy()
+ *	Handles conntrack destroy events
+ */
+static void ecm_conntrack_ipv6_event_destroy(struct nf_conn *ct)
+{
+	struct ecm_db_connection_instance *ci;
+
+	DEBUG_INFO("Destroy event for ct: %px\n", ct);
+
+	ci = ecm_db_connection_ipv6_from_ct_get_and_ref(ct);
+	if (!ci) {
+		DEBUG_TRACE("%px: not found\n", ct);
+		return;
+	}
+	DEBUG_INFO("%px: Connection defunct %px\n", ct, ci);
+
+	/*
+	 * Force destruction of the connection by making it defunct
+	 */
+	ecm_db_connection_make_defunct(ci);
+	ecm_db_connection_deref(ci);
+}
+
+#if defined(CONFIG_NF_CONNTRACK_MARK)
+/*
+ * ecm_conntrack_ipv6_event_mark()
+ *	Handles conntrack mark events
+ */
+static void ecm_conntrack_ipv6_event_mark(struct nf_conn *ct)
+{
+	struct ecm_db_connection_instance *ci;
+	struct ecm_classifier_instance *__attribute__((unused))cls;
+
+	DEBUG_INFO("%px: IPv6 mark event ct->mark: %d\n", ct, ct->mark);
+
+	/*
+	 * Ignore transitions to zero
+	 */
+	if (ct->mark == 0) {
+		return;
+	}
+
+	ci = ecm_db_connection_ipv6_from_ct_get_and_ref(ct);
+	if (!ci) {
+		DEBUG_TRACE("%px: not found\n", ct);
+		return;
+	}
+
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+	/*
+	 * As of now, only the Netlink classifier is interested in conmark changes
+	 * GGG TODO Add a classifier method to propagate this information to any and all types of classifier.
+	 */
+	cls = ecm_db_connection_assigned_classifier_find_and_ref(ci, ECM_CLASSIFIER_TYPE_NL);
+	if (cls) {
+		ecm_classifier_nl_process_mark((struct ecm_classifier_nl_instance *)cls, ct->mark);
+		cls->deref(cls);
+	}
+#endif
+	if (ci->feci->update_rule) {
+		ci->feci->update_rule(ci->feci, ECM_RULE_UPDATE_TYPE_CONNMARK, ct);
+	}
+
+	/*
+	 * All done
+	 */
+	ecm_db_connection_deref(ci);
+}
+#endif
+
+/*
+ * ecm_conntrack_ipv6_event()
+ *	Callback event invoked when conntrack connection state changes, currently we handle destroy events to quickly release state
+ */
+int ecm_conntrack_ipv6_event(unsigned long events, struct nf_conn *ct)
+{
+	/*
+	 * If operations have stopped then do not process event
+	 */
+	if (unlikely(ecm_front_end_ipv6_stopped)) {
+		DEBUG_WARN("Ignoring event - stopped\n");
+		return NOTIFY_DONE;
+	}
+
+	if (!ct) {
+		DEBUG_WARN("Error: no ct\n");
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * handle destroy events
+	 */
+	if (events & (1 << IPCT_DESTROY)) {
+		DEBUG_TRACE("%px: Event is destroy\n", ct);
+		ecm_conntrack_ipv6_event_destroy(ct);
+	}
+
+#if defined(CONFIG_NF_CONNTRACK_MARK)
+	/*
+	 * handle mark change events
+	 */
+	if (events & (1 << IPCT_MARK)) {
+		DEBUG_TRACE("%px: Event is mark\n", ct);
+		ecm_conntrack_ipv6_event_mark(ct);
+	}
+#endif
+	return NOTIFY_DONE;
+}
+EXPORT_SYMBOL(ecm_conntrack_ipv6_event);
+#endif
+
+/*
+ * ecm_conntrack_ipv4_event_destroy()
+ *	Handles conntrack destroy events
+ */
+static void ecm_conntrack_ipv4_event_destroy(struct nf_conn *ct)
+{
+	struct ecm_db_connection_instance *ci;
+
+	DEBUG_INFO("Destroy event for ct: %px\n", ct);
+
+	ci = ecm_db_connection_ipv4_from_ct_get_and_ref(ct);
+	if (!ci) {
+		DEBUG_TRACE("%px: not found\n", ct);
+		return;
+	}
+	DEBUG_INFO("%px: Connection defunct %px\n", ct, ci);
+
+	/*
+	 * Force destruction of the connection by making it defunct
+	 */
+	ecm_db_connection_make_defunct(ci);
+	ecm_db_connection_deref(ci);
+}
+
+#if defined(CONFIG_NF_CONNTRACK_MARK)
+/*
+ * ecm_conntrack_ipv4_event_mark()
+ *	Handles conntrack mark events
+ */
+static void ecm_conntrack_ipv4_event_mark(struct nf_conn *ct)
+{
+	struct ecm_db_connection_instance *ci;
+	struct ecm_classifier_instance *__attribute__((unused))cls;
+
+	DEBUG_INFO("%px: IPv4 mark event ct->mark: %d\n", ct, ct->mark);
+
+	/*
+	 * Ignore transitions to zero
+	 */
+	if (ct->mark == 0) {
+		return;
+	}
+
+	ci = ecm_db_connection_ipv4_from_ct_get_and_ref(ct);
+	if (!ci) {
+		DEBUG_TRACE("%px: not found\n", ct);
+		return;
+	}
+
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+	/*
+	 * As of now, only the Netlink classifier is interested in conmark changes
+	 * GGG TODO Add a classifier method to propagate this information to any and all types of classifier.
+	 */
+	cls = ecm_db_connection_assigned_classifier_find_and_ref(ci, ECM_CLASSIFIER_TYPE_NL);
+	if (cls) {
+		ecm_classifier_nl_process_mark((struct ecm_classifier_nl_instance *)cls, ct->mark);
+		cls->deref(cls);
+	}
+#endif
+	if (ci->feci->update_rule) {
+		ci->feci->update_rule(ci->feci, ECM_RULE_UPDATE_TYPE_CONNMARK, ct);
+	}
+
+	/*
+	 * All done
+	 */
+	ecm_db_connection_deref(ci);
+}
+#endif
+
+/*
+ * ecm_conntrack_ipv4_event()
+ *	Callback event invoked when conntrack connection state changes, currently we handle destroy events to quickly release state
+ */
+int ecm_conntrack_ipv4_event(unsigned long events, struct nf_conn *ct)
+{
+	/*
+	 * If operations have stopped then do not process event
+	 */
+	if (unlikely(ecm_front_end_ipv4_stopped)) {
+		DEBUG_WARN("Ignoring event - stopped\n");
+		return NOTIFY_DONE;
+	}
+
+	if (!ct) {
+		DEBUG_WARN("Error: no ct\n");
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * handle destroy events
+	 */
+	if (events & (1 << IPCT_DESTROY)) {
+		DEBUG_TRACE("%px: Event is destroy\n", ct);
+		ecm_conntrack_ipv4_event_destroy(ct);
+	}
+
+#if defined(CONFIG_NF_CONNTRACK_MARK)
+	/*
+	 * handle mark change events
+	 */
+	if (events & (1 << IPCT_MARK)) {
+		DEBUG_TRACE("%px: Event is mark\n", ct);
+		ecm_conntrack_ipv4_event_mark(ct);
+	}
+#endif
+	return NOTIFY_DONE;
+}
+EXPORT_SYMBOL(ecm_conntrack_ipv4_event);
+
+#ifdef CONFIG_NF_CONNTRACK_EVENTS
+/*
+ * ecm_conntrack_event()
+ *	Callback event invoked when conntrack connection state changes, currently we handle destroy events to quickly release state
+ */
+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
+static int ecm_conntrack_event(struct notifier_block *this, unsigned long events, void *ptr)
+#else
+static int ecm_conntrack_event(unsigned int events, struct nf_ct_event *item)
+#endif
+{
+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
+	struct nf_ct_event *item = (struct nf_ct_event *)ptr;
+#endif
+	struct nf_conn *ct = item->ct;
+
+	/*
+	 * If operations have stopped then do not process event
+	 */
+	spin_lock_bh(&ecm_conntrack_notifier_lock);
+	if (unlikely(ecm_conntrack_notifier_stopped)) {
+		DEBUG_WARN("Ignoring event - stopped\n");
+		spin_unlock_bh(&ecm_conntrack_notifier_lock);
+		return NOTIFY_DONE;
+	}
+	spin_unlock_bh(&ecm_conntrack_notifier_lock);
+
+	if (!ct) {
+		DEBUG_WARN("Error: no ct\n");
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Fake untracked conntrack objects were removed on 4.12 kernel version
+	 * and onwards.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
+	if (unlikely(ct == nf_ct_untracked_get())) {
+		/*
+		 * Special untracked connection is not monitored
+		 */
+		DEBUG_TRACE("Fake connection event - ignoring\n");
+		return NOTIFY_DONE;
+	}
+#endif
+
+	/*
+	 * Only interested if this is IPv4 or IPv6.
+	 */
+	if (nf_ct_l3num(ct) == AF_INET) {
+		return ecm_conntrack_ipv4_event(events, ct);
+	}
+#ifdef ECM_IPV6_ENABLE
+	if (nf_ct_l3num(ct) == AF_INET6) {
+		return ecm_conntrack_ipv6_event(events, ct);
+	}
+#endif
+	return NOTIFY_DONE;
+}
+
+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
+/*
+ * struct notifier_block ecm_conntrack_notifier
+ *	Netfilter conntrack event system to monitor connection tracking changes
+ */
+static struct notifier_block ecm_conntrack_notifier = {
+	.notifier_call	= ecm_conntrack_event,
+};
+#else
+/*
+ * struct nf_ct_event_notifier ecm_conntrack_notifier
+ *	Netfilter conntrack event system to monitor connection tracking changes
+ */
+static struct nf_ct_event_notifier ecm_conntrack_notifier = {
+	.fcn	= ecm_conntrack_event,
+};
+#endif
+#endif
+
+/*
+ * ecm_conntrack_notifier_stop()
+ */
+void ecm_conntrack_notifier_stop(int num)
+{
+	ecm_conntrack_notifier_stopped = num;
+}
+EXPORT_SYMBOL(ecm_conntrack_notifier_stop);
+
+/*
+ * ecm_conntrack_notifier_init()
+ */
+int ecm_conntrack_notifier_init(struct dentry *dentry)
+{
+	int result __attribute__((unused));
+	DEBUG_INFO("ECM Conntrack Notifier init\n");
+
+	ecm_conntrack_notifier_dentry = debugfs_create_dir("ecm_conntrack_notifier", dentry);
+	if (!ecm_conntrack_notifier_dentry) {
+		DEBUG_ERROR("Failed to create ecm conntrack notifier directory in debugfs\n");
+		return -1;
+	}
+
+	if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_conntrack_notifier_dentry,
+					(u32 *)&ecm_conntrack_notifier_stopped)) {
+		DEBUG_ERROR("Failed to create ecm conntrack notifier stopped file in debugfs\n");
+		debugfs_remove_recursive(ecm_conntrack_notifier_dentry);
+		return -1;
+	}
+
+#ifdef CONFIG_NF_CONNTRACK_EVENTS
+	/*
+	 * Eventing subsystem is available so we register a notifier hook to get fast notifications of expired connections
+	 */
+	result = nf_conntrack_register_notifier(&init_net, &ecm_conntrack_notifier);
+	if (result < 0) {
+		DEBUG_ERROR("Can't register nf notifier hook.\n");
+		debugfs_remove_recursive(ecm_conntrack_notifier_dentry);
+		return result;
+	}
+#endif
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_conntrack_notifier_init);
+
+/*
+ * ecm_conntrack_notifier_exit()
+ */
+void ecm_conntrack_notifier_exit(void)
+{
+	DEBUG_INFO("ECM Conntrack Notifier exit\n");
+#ifdef CONFIG_NF_CONNTRACK_EVENTS
+	nf_conntrack_unregister_notifier(&init_net, &ecm_conntrack_notifier);
+#endif
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_conntrack_notifier_dentry) {
+		debugfs_remove_recursive(ecm_conntrack_notifier_dentry);
+	}
+}
+EXPORT_SYMBOL(ecm_conntrack_notifier_exit);
diff --git a/qca-nss-ecm/ecm_conntrack_notifier.h b/qca-nss-ecm/ecm_conntrack_notifier.h
new file mode 100644
index 0000000..52d724b
--- /dev/null
+++ b/qca-nss-ecm/ecm_conntrack_notifier.h
@@ -0,0 +1,20 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern void ecm_conntrack_notifier_stop(int num);
+extern int ecm_conntrack_notifier_init(struct dentry *dentry);
+extern void ecm_conntrack_notifier_exit(void);
+
diff --git a/qca-nss-ecm/ecm_db/ecm_db.c b/qca-nss-ecm/ecm_db/ecm_db.c
new file mode 100644
index 0000000..722d6d5
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db.c
@@ -0,0 +1,555 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <linux/random.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <net/ip6_route.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_DB_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_classifier_default.h"
+#include "ecm_db.h"
+#include "ecm_front_end_ipv4.h"
+#ifdef ECM_IPV6_ENABLE
+#include "ecm_front_end_ipv6.h"
+#endif
+#include "ecm_notifier_pvt.h"
+#include "ecm_interface.h"
+
+/*
+ * Locking of the database - concurrency control
+ */
+DEFINE_SPINLOCK(ecm_db_lock);					/* Protect the table from SMP access. */
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_db_dentry;
+
+/*
+ * Management thread control
+ */
+bool ecm_db_terminate_pending = false;			/* When true the user has requested termination */
+
+/*
+ * Random seed used during hash calculations
+ */
+uint32_t ecm_db_jhash_rnd __read_mostly;
+
+/*
+ * ecm_db_obj_dir_strings[]
+ *      Common array that maps the object direction to a string
+ */
+char *ecm_db_obj_dir_strings[ECM_DB_OBJ_DIR_MAX] = {
+        "FROM",
+        "TO",
+        "FROM_NAT",
+        "TO_NAT"
+};
+
+/*
+ * Global listener instance for DB events.
+ */
+static struct ecm_db_listener_instance *ecm_db_li;
+
+/*
+ * ecm_db_adv_stats_state_write()
+ *	Write out advanced stats state
+ */
+int ecm_db_adv_stats_state_write(struct ecm_state_file_instance *sfi,uint64_t from_data_total, uint64_t to_data_total,
+				uint64_t from_packet_total, uint64_t to_packet_total, uint64_t from_data_total_dropped,
+				uint64_t to_data_total_dropped, uint64_t from_packet_total_dropped, uint64_t to_packet_total_dropped)
+{
+	int result;
+
+	if ((result = ecm_state_prefix_add(sfi, "adv_stats"))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "from_data_total", "%llu", from_data_total))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "to_data_total", "%llu", to_data_total))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "from_packet_total", "%llu", from_packet_total))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "to_packet_total", "%llu", to_packet_total))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "from_data_total_dropped", "%llu", from_data_total_dropped))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "to_data_total_dropped", "%llu", to_data_total_dropped))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "from_packet_total_dropped", "%llu", from_packet_total_dropped))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "to_packet_total_dropped", "%llu", to_packet_total_dropped))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+
+/*
+ * ecm_db_get_defunct_all()
+ *	Reading this file returns the accumulated total of all objects
+ */
+static ssize_t ecm_db_get_defunct_all(struct file *file,
+					char __user *user_buf,
+					size_t sz, loff_t *ppos)
+{
+	int ret;
+	int num;
+	char *buf;
+
+	buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!buf) {
+		return -ENOMEM;
+	}
+
+	/*
+	 * Operate under our locks
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	num = _ecm_db_connection_count_get() + _ecm_db_mapping_count_get() + _ecm_db_host_count_get()
+			+ _ecm_db_node_count_get() + _ecm_db_iface_count_get();
+	spin_unlock_bh(&ecm_db_lock);
+
+	ret = snprintf(buf, (ssize_t)PAGE_SIZE, "%d\n", num);
+	if (ret < 0) {
+		kfree(buf);
+		return ret;
+	}
+
+	ret = simple_read_from_buffer(user_buf, sz, ppos, buf, ret);
+	kfree(buf);
+	return ret;
+}
+
+/*
+ * ecm_db_set_defunct_all()
+ */
+static ssize_t ecm_db_set_defunct_all(struct file *file,
+					const char __user *user_buf,
+					size_t sz, loff_t *ppos)
+{
+	ecm_db_connection_defunct_all();
+	return sz;
+}
+
+/*
+ * File operations for defunct_all.
+ */
+static struct file_operations ecm_db_defunct_all_fops = {
+	.read = ecm_db_get_defunct_all,
+	.write = ecm_db_set_defunct_all,
+};
+
+/*
+ * ecm_db_ipv4_route_table_update_event()
+ *	This is a call back for "routing table update event for IPv4".
+ */
+static int ecm_db_ipv4_route_table_update_event(struct notifier_block *nb,
+					       unsigned long event,
+					       void *ptr)
+{
+	DEBUG_TRACE("route table update event v4\n");
+
+	/*
+	 * Disable IPv4 frontend processing until defunct function call is completed.
+	 */
+	ecm_front_end_ipv4_stop(1);
+
+	ecm_db_connection_defunct_ip_version(4);
+
+	/*
+	 * Re-enable IPv4 frontend processing.
+	 */
+	ecm_front_end_ipv4_stop(0);
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block ecm_db_iproute_table_update_nb = {
+	.notifier_call = ecm_db_ipv4_route_table_update_event,
+};
+
+#ifdef ECM_IPV6_ENABLE
+/*
+ * ecm_db_ipv6_route_table_update_event()
+ *	This is a call back for "routing table update event for IPv6".
+ */
+static int ecm_db_ipv6_route_table_update_event(struct notifier_block *nb,
+					       unsigned long event,
+					       void *ptr)
+{
+	struct fib6_config *cfg = (struct fib6_config *)ptr;
+	struct ecm_db_connection_instance *ci;
+
+	DEBUG_TRACE("route table update event v6\n");
+
+	if ((event != RTM_DELROUTE) && (event != RTM_NEWROUTE)) {
+		DEBUG_WARN("%px: Unhandled route table event: %lu\n", cfg, event);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * If a default route is changed, fc_dst address is set to all zeros.
+	 * In this case, we should defunct all the IPv6 flows.
+	 */
+	if (ipv6_addr_any(&cfg->fc_dst)) {
+		DEBUG_TRACE("%px fc_dst (%pI6), default route is changed, defunct all IPv6 connections\n",
+			    cfg, &cfg->fc_dst);
+		ecm_db_connection_defunct_ip_version(6);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * Disable IPv6 frontend processing until defunct function call is completed.
+	 */
+	ecm_front_end_ipv6_stop(1);
+
+	/*
+	 * Iterate all connections
+	 */
+	ci = ecm_db_connections_get_and_ref_first();
+	while (ci) {
+		struct ecm_db_connection_instance *cin;
+		struct in6_addr prefix_addr;
+		struct in6_addr ecm_in6;
+		ip_addr_t ecm_addr;
+		struct ecm_db_iface_instance *interfaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+		int32_t if_first;
+		struct net_device *ecm_dev;
+		struct net_device *fc_dev;
+		bool is_dest_ip_match = true;
+		ecm_db_obj_dir_t obj_dir = ECM_DB_OBJ_DIR_TO;
+
+		if (ci->ip_version != 6) {
+			goto next;
+		}
+
+		/*
+		 * Get the ECM connection's destination IPv6 address.
+		 */
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, ecm_addr);
+		ECM_IP_ADDR_TO_NIN6_ADDR(ecm_in6, ecm_addr);
+
+		/*
+		 * Compute ECM connection's prefix destination address by masking it with the
+		 * route config's destination address prefix length.
+		 */
+		ipv6_addr_prefix(&prefix_addr, &ecm_in6, cfg->fc_dst_len);
+
+		DEBUG_TRACE("dest addr prefix: %pI6 prefix_len: %d ecm_in6: %pI6\n", &prefix_addr, cfg->fc_dst_len, &ecm_in6);
+
+		/*
+		 * Compare the ECM connection's destination address prefix with the route config's
+		 * destination address. If they are not equal, try with the ECM's source address prefix.
+		 * Because ECM can create the connection in the reply direction, and in this case, ECM
+		 * connection's source prefix IP address will match with the route config's dst IP address.
+		 *
+		 * If none of them match with the route config's destination address, this means that
+		 * this connection is not related to this route change event.
+		 * We should check with the next connection.
+		 */
+		if (ipv6_addr_cmp(&prefix_addr, &cfg->fc_dst)) {
+			DEBUG_TRACE("dest addr prefix: %pI6 not equal to cfg->fc_dst: %pI6, go to next connection\n", &prefix_addr, &cfg->fc_dst);
+
+			/*
+			 * ECM's destination address didn't match.
+			 * Get the ECM connection's source IPv6 address.
+			 */
+			ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, ecm_addr);
+			ECM_IP_ADDR_TO_NIN6_ADDR(ecm_in6, ecm_addr);
+
+			/*
+			 * Compute ECM connection's prefix source address by masking it with the
+			 * route config's destination address prefix length.
+			 */
+			ipv6_addr_prefix(&prefix_addr, &ecm_in6, cfg->fc_dst_len);
+
+			DEBUG_TRACE("src addr prefix: %pI6 prefix_len: %d ecm_in6: %pI6\n", &prefix_addr, cfg->fc_dst_len, &ecm_in6);
+
+			if (ipv6_addr_cmp(&prefix_addr, &cfg->fc_dst)) {
+				DEBUG_TRACE("src addr prefix: %pI6 not equal to cfg->fc_dst: %pI6, go to next connection\n", &prefix_addr, &cfg->fc_dst);
+				goto next;
+			}
+
+			is_dest_ip_match = false;
+			obj_dir = ECM_DB_OBJ_DIR_FROM;
+		}
+
+		DEBUG_TRACE("%px: ECM connection's %s address prefix: %pI6 equals to cfg->fc_dst: %pI6\n",
+			    ci, is_dest_ip_match?"dest":"src", &prefix_addr, &cfg->fc_dst);
+
+		/*
+		 * If the event is a route delete event, comparing only the IP address is enough
+		 * to defunct the connection.
+		 */
+		if (event == RTM_DELROUTE) {
+			DEBUG_TRACE("%px: Route DELETE event, defunct the connection\n", ci);
+			ecm_db_connection_make_defunct(ci);
+			goto next;
+		}
+
+		DEBUG_TRACE("%px: Route ADD event\n", ci);
+
+		/*
+		 * If there is a route for this connection's source or destination IP address, we should
+		 * compare the devices as well, because the IP address could remain the same, but
+		 * the output device could be changed. So, the flows should take the new out device
+		 * for their route.
+		 */
+		if_first = ecm_db_connection_interfaces_get_and_ref(ci, interfaces, obj_dir);
+		if (if_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			DEBUG_WARN("%px: Failed to get %s interfaces list\n",
+					ci, ecm_db_obj_dir_strings[obj_dir]);
+			goto next;
+		}
+
+		/*
+		 * Inner most interface has the IP address, so we should get that interface.
+		 */
+		ecm_dev = dev_get_by_index(&init_net,
+				  ecm_db_iface_interface_identifier_get(interfaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1]));
+		if (!ecm_dev) {
+			DEBUG_WARN("%px: unable to find ecm netdevice\n", ci);
+			ecm_db_connection_interfaces_deref(interfaces, if_first);
+			goto next;
+		}
+		ecm_db_connection_interfaces_deref(interfaces, if_first);
+
+		fc_dev = dev_get_by_index(&init_net, cfg->fc_ifindex);
+		if (!fc_dev) {
+			DEBUG_WARN("%px: unable to find fib6_config netdevice\n", ci);
+			dev_put(ecm_dev);
+			goto next;
+		}
+
+		/*
+		 * Compare the ECM connection's netdevice with the route change config's netdevice.
+		 * If they are different, this means the new route effected the connection. So, defunct it.
+		 */
+		if (ecm_dev != fc_dev) {
+			DEBUG_TRACE("%px: fib6_config dev: %s is different from ecm dev: %s, defunct the connection\n",
+				    ci, fc_dev->name, ecm_dev->name);
+			ecm_db_connection_make_defunct(ci);
+		}
+		dev_put(fc_dev);
+		dev_put(ecm_dev);
+next:
+		cin = ecm_db_connection_get_and_ref_next(ci);
+		ecm_db_connection_deref(ci);
+		ci = cin;
+	}
+
+	/*
+	 * Re-enable IPv6 frontend processing.
+	 */
+	ecm_front_end_ipv6_stop(0);
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block ecm_db_ip6route_table_update_nb = {
+	.notifier_call = ecm_db_ipv6_route_table_update_event,
+};
+#endif
+
+/*
+ * ecm_db_init()
+ */
+int ecm_db_init(struct dentry *dentry)
+{
+	DEBUG_INFO("ECM Module init\n");
+
+	ecm_db_dentry = debugfs_create_dir("ecm_db", dentry);
+	if (!ecm_db_dentry) {
+		DEBUG_ERROR("Failed to create ecm db directory in debugfs\n");
+		return -1;
+	}
+
+	/*
+	 * Get a random seed for jhash()
+	 */
+	get_random_bytes(&ecm_db_jhash_rnd, sizeof(ecm_db_jhash_rnd));
+	printk(KERN_INFO "ECM database jhash random seed: 0x%x\n", ecm_db_jhash_rnd);
+
+	if (!ecm_db_connection_init(ecm_db_dentry)) {
+		goto init_cleanup;
+	}
+
+	if (!ecm_db_host_init(ecm_db_dentry)) {
+		goto init_cleanup_1;
+	}
+
+	if (!ecm_db_mapping_init(ecm_db_dentry)) {
+		goto init_cleanup_2;
+	}
+
+	if (!ecm_db_node_init(ecm_db_dentry)) {
+		goto init_cleanup_3;
+	}
+
+	if (!ecm_db_iface_init(ecm_db_dentry)) {
+		goto init_cleanup_4;
+	}
+
+	if (!debugfs_create_file("defunct_all", S_IRUGO | S_IWUSR, ecm_db_dentry,
+					NULL, &ecm_db_defunct_all_fops)) {
+		DEBUG_ERROR("Failed to create ecm db defunct_all file in debugfs\n");
+		goto init_cleanup_4;
+	}
+
+	ecm_db_li = ecm_db_listener_alloc();
+	if (!ecm_db_li) {
+		DEBUG_ERROR("%px: Failed to allocate a listener instance\n", dentry);
+		goto init_cleanup_4;
+	}
+	ecm_db_listener_add(ecm_db_li,
+			NULL, /* ecm_notifier_iface_added */
+			NULL, /* ecm_notifier_iface_removed */
+			NULL, /* ecm_notifier_node_added */
+			NULL, /* ecm_notifier_node_removed */
+			NULL, /* ecm_notifier_host_added */
+			NULL, /* ecm_notifier_host_removed */
+			NULL, /* ecm_notifier_mapping_added */
+			NULL, /* ecm_notifier_mapping_removed */
+			ecm_notifier_connection_added,
+			ecm_notifier_connection_removed,
+			NULL, /* ecm_notifier_connection_final */
+			NULL);
+
+	/*
+	 * Initialize the timer resources.
+	 */
+	ecm_db_timer_init();
+
+	/*
+	 * register for route table modification events
+	 */
+	ip_rt_register_notifier(&ecm_db_iproute_table_update_nb);
+#ifdef ECM_IPV6_ENABLE
+	rt6_register_notifier(&ecm_db_ip6route_table_update_nb);
+#endif
+	return 0;
+
+init_cleanup_4:
+	ecm_db_node_exit();
+init_cleanup_3:
+	ecm_db_mapping_exit();
+init_cleanup_2:
+	ecm_db_host_exit();
+init_cleanup_1:
+	ecm_db_connection_exit();
+init_cleanup:
+	debugfs_remove_recursive(ecm_db_dentry);
+	return -1;
+}
+EXPORT_SYMBOL(ecm_db_init);
+
+/*
+ * ecm_db_exit()
+ */
+void ecm_db_exit(void)
+{
+	DEBUG_INFO("ECM DB Module exit\n");
+
+	spin_lock_bh(&ecm_db_lock);
+	ecm_db_terminate_pending = true;
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * unregister for route table update events
+	 */
+	ip_rt_unregister_notifier(&ecm_db_iproute_table_update_nb);
+#ifdef ECM_IPV6_ENABLE
+	rt6_unregister_notifier(&ecm_db_ip6route_table_update_nb);
+#endif
+	ecm_db_connection_defunct_all();
+
+	/*
+	 * Clean-up the timer resources.
+	 */
+	ecm_db_timer_exit();
+
+	if (ecm_db_li) {
+		ecm_db_listener_deref(ecm_db_li);
+		ecm_db_li = NULL;
+	}
+
+	/*
+	 * Free the database.
+	 */
+	ecm_db_node_exit();
+	ecm_db_mapping_exit();
+	ecm_db_host_exit();
+	ecm_db_connection_exit();
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_db_dentry) {
+		debugfs_remove_recursive(ecm_db_dentry);
+	}
+}
+EXPORT_SYMBOL(ecm_db_exit);
diff --git a/qca-nss-ecm/ecm_db/ecm_db.h b/qca-nss-ecm/ecm_db/ecm_db.h
new file mode 100644
index 0000000..fe0bed9
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db.h
@@ -0,0 +1,47 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * API's
+ */
+#ifndef ECM_DB_H_
+#define ECM_DB_H_
+
+#include "ecm_db_connection.h"
+#include "ecm_db_mapping.h"
+#include "ecm_db_host.h"
+#include "ecm_db_node.h"
+#include "ecm_db_iface.h"
+#include "ecm_db_listener.h"
+#include "ecm_db_multicast.h"
+#include "ecm_db_timer.h"
+
+extern spinlock_t ecm_db_lock;
+
+/*
+ * Management thread control
+ */
+extern bool ecm_db_terminate_pending;	/* When true the user has requested termination */
+
+/*
+ * Random seed used during hash calculations
+ */
+extern uint32_t ecm_db_jhash_rnd __read_mostly;
+
+int ecm_db_adv_stats_state_write(struct ecm_state_file_instance *sfi,uint64_t from_data_total, uint64_t to_data_total,
+				uint64_t from_packet_total, uint64_t to_packet_total, uint64_t from_data_total_dropped,
+				uint64_t to_data_total_dropped, uint64_t from_packet_total_dropped, uint64_t to_packet_total_dropped);
+#endif /* ECM_DB_H_ */
diff --git a/qca-nss-ecm/ecm_db/ecm_db_connection.c b/qca-nss-ecm/ecm_db/ecm_db_connection.c
new file mode 100644
index 0000000..fd68f23
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_connection.c
@@ -0,0 +1,3842 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2022, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <linux/random.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <net/ip6_route.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_DB_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_classifier_default.h"
+#include "ecm_db.h"
+
+/*
+ * Magic number
+ */
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+#define ECM_DB_CLASSIFIER_TYPE_ASSIGNMENT_MAGIC 0xAEF4
+#endif
+
+/*
+ * Global list.
+ * All instances are inserted into global list - this allows easy iteration of all instances of a particular type.
+ * The list is doubly linked for fast removal.  The list is in no particular order.
+ */
+struct ecm_db_connection_instance *ecm_db_connections = NULL;
+
+/*
+ * Connection hash table
+ */
+#define ECM_DB_CONNECTION_HASH_SLOTS 32768
+static struct ecm_db_connection_instance **ecm_db_connection_table;
+						/* Slots of the connection hash table */
+static int *ecm_db_connection_table_lengths;
+						/* Tracks how long each chain is */
+static int ecm_db_connection_count = 0;		/* Number of connections allocated */
+
+/*
+ * Connection serial number hash table
+ */
+#define ECM_DB_CONNECTION_SERIAL_HASH_SLOTS 32768
+struct ecm_db_connection_instance **ecm_db_connection_serial_table;
+						/* Slots of the connection serial hash table */
+int *ecm_db_connection_serial_table_lengths;
+						/* Tracks how long each chain is */
+
+static int ecm_db_connection_serial = 0;	/* Serial number - ensures each connection has a unique serial number.
+						 * Serial numbers are used mainly by classifiers that keep their own state
+						 * and can 'link' their state to the right connection using a serial number.
+						 * The serial number is also used as a soft linkage to other subsystems such as NA.
+						 */
+
+/*
+ * Simple stats
+ */
+#define ECM_DB_PROTOCOL_COUNT 256
+static int ecm_db_connection_count_by_protocol[ECM_DB_PROTOCOL_COUNT];	/* Each IP protocol has its own count */
+
+/*
+ * Connection state validity
+ * This counter is incremented whenever a general change is detected which requires re-generation of state for ALL connections.
+ */
+uint16_t ecm_db_connection_generation = 0;		/* Generation counter to detect when all connection state is considered stale and all must be re-generated */
+
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+/*
+ * Classifier TYPE assignment lists.
+ *
+ * For each type of classifier a list is kept of all connections assigned a classifier of that type.
+ * This permits a classifier type to rapidly retrieve all connections with classifiers assigned to it of that type.
+ *
+ * NOTE: This is in addition to the basic functionality whereby a connection keeps a list of classifier instances
+ * that are assigned to it in descending order of priority.
+ */
+
+/*
+ * struct ecm_db_connection_classifier_type_assignment_list
+ *	A list, one for each classifier type.
+ */
+struct ecm_db_connection_classifier_type_assignment_list {
+	struct ecm_db_connection_instance *type_assignments_list;
+							/* Lists of connections assigned to this type of classifier */
+	int32_t type_assignment_count;			/* Number of connections in the list */
+} ecm_db_connection_classifier_type_assignments[ECM_CLASSIFIER_TYPES];
+							/* Each classifier type has a list of connections that are assigned to classifier instances of that type */
+#endif
+
+/*
+ * _ecm_db_connection_count_get()
+ *	Return the connection count (lockless).
+ */
+int _ecm_db_connection_count_get(void)
+{
+	return ecm_db_connection_count;
+}
+
+/*
+ * ecm_db_connection_count_get()
+ *	Return the connection count
+ */
+int ecm_db_connection_count_get(void)
+{
+	int count;
+
+	spin_lock_bh(&ecm_db_lock);
+	count = ecm_db_connection_count;
+	spin_unlock_bh(&ecm_db_lock);
+	return count;
+}
+EXPORT_SYMBOL(ecm_db_connection_count_get);
+
+/*
+ * ecm_db_connection_count_by_protocol_get()
+ *	Return # connections for the given protocol
+ */
+int ecm_db_connection_count_by_protocol_get(int protocol)
+{
+	int count;
+
+	DEBUG_ASSERT((protocol >= 0) && (protocol < ECM_DB_PROTOCOL_COUNT), "Bad protocol: %d\n", protocol);
+	spin_lock_bh(&ecm_db_lock);
+	count = ecm_db_connection_count_by_protocol[protocol];
+	spin_unlock_bh(&ecm_db_lock);
+	return count;
+}
+EXPORT_SYMBOL(ecm_db_connection_count_by_protocol_get);
+
+/*
+ * ecm_db_connection_l2_encap_proto_set()
+ *	Sets the L2 encap protocol.
+ */
+void ecm_db_connection_l2_encap_proto_set(struct ecm_db_connection_instance *ci, uint16_t l2_encap_proto)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	ci->l2_encap_proto = l2_encap_proto;
+	spin_unlock_bh(&ecm_db_lock);
+}
+
+/*
+ * ecm_db_connection_l2_encap_proto_get()
+ *	Gets the L2 encap protocol.
+ */
+uint16_t ecm_db_connection_l2_encap_proto_get(struct ecm_db_connection_instance *ci)
+{
+	uint16_t proto;
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	proto = ci->l2_encap_proto;
+	spin_unlock_bh(&ecm_db_lock);
+
+	return proto;
+}
+
+/*
+ * ecm_db_connection_mark_set()
+ *	Sets the mark value of the connection.
+ */
+void ecm_db_connection_mark_set(struct ecm_db_connection_instance *ci, uint32_t mark)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	ci->mark = mark;
+	spin_unlock_bh(&ecm_db_lock);
+
+}
+
+/*
+ * ecm_db_connection_flag_set()
+ *	Sets the flag in connection instance.
+ */
+void ecm_db_connection_flag_set(struct ecm_db_connection_instance *ci, uint32_t flag)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	ci->flags |= flag;
+	spin_unlock_bh(&ecm_db_lock);
+}
+
+/*
+ * ecm_db_connection_mark_get()
+ *	Gets the mark value of the connection.
+ */
+uint32_t ecm_db_connection_mark_get(struct ecm_db_connection_instance *ci)
+{
+	uint16_t mark;
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	mark = ci->mark;
+	spin_unlock_bh(&ecm_db_lock);
+
+	return mark;
+}
+
+/*
+ * ecm_db_connection_front_end_get_and_ref()
+ *	Return ref to the front end instance of the connection
+ */
+struct ecm_front_end_connection_instance *ecm_db_connection_front_end_get_and_ref(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	ci->feci->ref(ci->feci);
+	return ci->feci;
+}
+EXPORT_SYMBOL(ecm_db_connection_front_end_get_and_ref);
+
+/*
+ * ecm_db_connection_defunct_callback()
+ *	Invoked by the expiration of the defunct_timer contained in a connection instance
+ */
+static void ecm_db_connection_defunct_callback(void *arg)
+{
+	int accel_mode;
+	bool ret;
+
+	struct ecm_db_connection_instance *ci = (struct ecm_db_connection_instance *)arg;
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	DEBUG_INFO("%px: defunct timer expired\n", ci);
+
+	ret = ci->defunct(ci->feci, &accel_mode);
+
+	/*
+	 * If the returned 'ret' is success, this means this callback succeeded to
+	 * defunct the connection and it can release the last reference.
+	 * If it fails, this means that another defunct process defuncted the connection
+	 * before this callback. In that case, we will check the accel_mode of the connection.
+	 * If the other call defuncted the connection successfully, it will set the accel_mode to
+	 * ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT_SHORT for s short amount of time to avoid
+	 * further accel/decel attempts. So, in this accel_mode, this callback shouldn't release the
+	 * last reference. It will be released by the ecm_db_connection_make_defunct() function.
+	 */
+	if (ret || (ECM_FRONT_END_ACCELERATION_FAILED(accel_mode) && (accel_mode != ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT_SHORT))) {
+		ecm_db_connection_deref(ci);
+	}
+}
+
+/*
+ * ecm_db_connection_elapsed_defunct_timer()
+ *	Returns the elapsed time of defunct timer.
+ * If the timer is already expired and not removed from the database, the
+ * function returns a negative value. The caller MUST handle this return value.
+ */
+int ecm_db_connection_elapsed_defunct_timer(struct ecm_db_connection_instance *ci)
+{
+	long int expires_in;
+	int elapsed;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	/*
+	 * Do some sanity checks.
+	 * If it is not in a timer group, which means already expired, or the
+	 * connection has not been fully created yet. Just return 0.
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	if (ci->defunct_timer.group == ECM_DB_TIMER_GROUPS_MAX) {
+		spin_unlock_bh(&ecm_db_lock);
+		return -1;
+	}
+
+	/*
+	 * Already expired, but not removed from the database completely.
+	 */
+	expires_in = (long int)(ci->defunct_timer.timeout - ecm_db_time);
+	if (expires_in < 0) {
+		spin_unlock_bh(&ecm_db_lock);
+		return -1;
+	}
+
+	elapsed = ecm_db_timer_groups[ci->defunct_timer.group].time - expires_in;
+	spin_unlock_bh(&ecm_db_lock);
+
+	return elapsed;
+}
+EXPORT_SYMBOL(ecm_db_connection_elapsed_defunct_timer);
+
+/*
+ * ecm_db_connection_defunct_timer_reset()
+ *	Set/change the timer group associated with a connection.  Returns false if the connection has become defunct and the new group cannot be set for that reason.
+ */
+bool ecm_db_connection_defunct_timer_reset(struct ecm_db_connection_instance *ci, ecm_db_timer_group_t tg)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	return ecm_db_timer_group_entry_reset(&ci->defunct_timer, tg);
+}
+EXPORT_SYMBOL(ecm_db_connection_defunct_timer_reset);
+
+/*
+ * ecm_db_connection_defunct_timer_touch()
+ *	Update the connections defunct timer to stop it timing out.  Returns false if the connection defunct timer has expired.
+ */
+bool ecm_db_connection_defunct_timer_touch(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	return ecm_db_timer_group_entry_touch(&ci->defunct_timer);
+}
+EXPORT_SYMBOL(ecm_db_connection_defunct_timer_touch);
+
+/*
+ * ecm_db_connection_defunct_timer_no_touch_set()
+ *	Set no touch flag in CI
+ */
+void ecm_db_connection_defunct_timer_no_touch_set(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%p: magic failed", ci);
+	ci->timer_no_touch = true;
+}
+
+/*
+ * ecm_db_connection_defunct_timer_no_touch_get()
+ *	Get no touch flag in CI
+ */
+bool ecm_db_connection_defunct_timer_no_touch_get(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%p: magic failed", ci);
+	return ci->timer_no_touch;
+}
+
+/*
+ * ecm_db_connection_timer_group_get()
+ *	Return the timer group id
+ */
+ecm_db_timer_group_t ecm_db_connection_timer_group_get(struct ecm_db_connection_instance *ci)
+{
+	ecm_db_timer_group_t tg;
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	tg = ci->defunct_timer.group;
+	spin_unlock_bh(&ecm_db_lock);
+	return tg;
+}
+EXPORT_SYMBOL(ecm_db_connection_timer_group_get);
+
+/*
+ * ecm_db_connection_make_defunct()
+ *	Make connection defunct.
+ */
+void ecm_db_connection_make_defunct(struct ecm_db_connection_instance *ci)
+{
+	int accel_mode;
+	bool ret;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	/*
+	 * If connection's defunct timer is already removed from the groups,
+	 * this means that the connection is timed out and already in defunct process.
+	 * So, let's not continue in this defunct process.
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	if (ci->defunct_timer.group == ECM_DB_TIMER_GROUPS_MAX) {
+		spin_unlock_bh(&ecm_db_lock);
+		return;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Call the frontend's defunct callback function and handle the return values.
+	 */
+	ret = ci->defunct(ci->feci, &accel_mode);
+
+	/*
+	 * If the defunct is success, first we should remove the timer and then release
+	 * the last reference. It is possible that while we are handling the defunct callback,
+	 * the timer was expired and removed from the list. So, we don't need to check the
+	 * return value of the timer removal function. Regardless of who removed the timer, we should
+	 * release the last reference.
+	 */
+	if (ret) {
+		ecm_db_timer_group_entry_remove(&ci->defunct_timer);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	/*
+	 * If defunct fails and the connection state is in one of the fail states, we should remove the timer
+	 * and release the last reference. In this case we should check the timer removal function's return value
+	 * to make sure that it is removed by us.
+	 */
+	if (ECM_FRONT_END_ACCELERATION_FAILED(accel_mode)) {
+		if (ecm_db_timer_group_entry_remove(&ci->defunct_timer)) {
+			ecm_db_connection_deref(ci);
+		}
+	}
+}
+EXPORT_SYMBOL(ecm_db_connection_make_defunct);
+
+/*
+ * ecm_db_connection_data_totals_update()
+ *	Update the total data (and packets) sent/received by the given host
+ */
+void ecm_db_connection_data_totals_update(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets)
+{
+	int32_t i;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+
+	if (is_from) {
+		/*
+		 * Update totals sent by the FROM side of connection
+		 */
+		ci->from_data_total += size;
+		ci->from_packet_total += packets;
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+		ci->mapping[ECM_DB_OBJ_DIR_FROM]->from_data_total += size;
+		ci->mapping[ECM_DB_OBJ_DIR_FROM]->host->from_data_total += size;
+		ci->node[ECM_DB_OBJ_DIR_FROM]->from_data_total += size;
+		ci->mapping[ECM_DB_OBJ_DIR_FROM]->from_packet_total += packets;
+		ci->mapping[ECM_DB_OBJ_DIR_FROM]->host->from_packet_total += packets;
+		ci->node[ECM_DB_OBJ_DIR_FROM]->from_packet_total += packets;
+
+		/*
+		 * Data from the host is essentially TO the interface on which the host is reachable
+		 */
+		for (i = ci->interface_first[ECM_DB_OBJ_DIR_FROM]; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+			ci->interfaces[ECM_DB_OBJ_DIR_FROM][i]->to_data_total += size;
+			ci->interfaces[ECM_DB_OBJ_DIR_FROM][i]->to_packet_total += packets;
+		}
+
+		/*
+		 * Update totals sent TO the other side of the connection
+		 */
+		ci->mapping[ECM_DB_OBJ_DIR_TO]->to_data_total += size;
+		ci->mapping[ECM_DB_OBJ_DIR_TO]->host->to_data_total += size;
+		ci->node[ECM_DB_OBJ_DIR_TO]->to_data_total += size;
+		ci->mapping[ECM_DB_OBJ_DIR_TO]->to_packet_total += packets;
+		ci->mapping[ECM_DB_OBJ_DIR_TO]->host->to_packet_total += packets;
+		ci->node[ECM_DB_OBJ_DIR_TO]->to_packet_total += packets;
+
+		/*
+		 * Sending to the other side means FROM the interface we reach that host
+		 */
+		for (i = ci->interface_first[ECM_DB_OBJ_DIR_TO]; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+			ci->interfaces[ECM_DB_OBJ_DIR_TO][i]->from_data_total += size;
+			ci->interfaces[ECM_DB_OBJ_DIR_TO][i]->from_packet_total += packets;
+		}
+#endif
+		spin_unlock_bh(&ecm_db_lock);
+		return;
+	}
+
+	/*
+	 * Update totals sent by the TO side of this connection
+	 */
+	ci->to_data_total += size;
+	ci->to_packet_total += packets;
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	ci->mapping[ECM_DB_OBJ_DIR_TO]->from_data_total += size;
+	ci->mapping[ECM_DB_OBJ_DIR_TO]->host->from_data_total += size;
+	ci->node[ECM_DB_OBJ_DIR_TO]->from_data_total += size;
+	ci->mapping[ECM_DB_OBJ_DIR_TO]->from_packet_total += packets;
+	ci->mapping[ECM_DB_OBJ_DIR_TO]->host->from_packet_total += packets;
+	ci->node[ECM_DB_OBJ_DIR_TO]->from_packet_total += packets;
+
+	/*
+	 * Data from the host is essentially TO the interface on which the host is reachable
+	 */
+	for (i = ci->interface_first[ECM_DB_OBJ_DIR_TO]; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+		ci->interfaces[ECM_DB_OBJ_DIR_TO][i]->to_data_total += size;
+		ci->interfaces[ECM_DB_OBJ_DIR_TO][i]->to_packet_total += packets;
+	}
+
+	/*
+	 * Update totals sent TO the other side of the connection
+	 */
+	ci->mapping[ECM_DB_OBJ_DIR_FROM]->to_data_total += size;
+	ci->mapping[ECM_DB_OBJ_DIR_FROM]->host->to_data_total += size;
+	ci->node[ECM_DB_OBJ_DIR_FROM]->to_data_total += size;
+	ci->mapping[ECM_DB_OBJ_DIR_FROM]->to_packet_total += packets;
+	ci->mapping[ECM_DB_OBJ_DIR_FROM]->host->to_packet_total += packets;
+	ci->node[ECM_DB_OBJ_DIR_FROM]->to_packet_total += packets;
+
+	/*
+	 * Sending to the other side means FROM the interface we reach that host
+	 */
+	for (i = ci->interface_first[ECM_DB_OBJ_DIR_FROM]; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+		ci->interfaces[ECM_DB_OBJ_DIR_FROM][i]->from_data_total += size;
+		ci->interfaces[ECM_DB_OBJ_DIR_FROM][i]->from_packet_total += packets;
+	}
+#endif
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_connection_data_totals_update);
+
+/*
+ * ecm_db_connection_data_totals_update_dropped()
+ *	Update the total data (and packets) sent by the given host but which we dropped
+ */
+void ecm_db_connection_data_totals_update_dropped(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets)
+{
+	int32_t i;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	if (is_from) {
+		/*
+		 * Update dropped totals sent by the FROM side
+		 */
+		spin_lock_bh(&ecm_db_lock);
+		ci->from_data_total_dropped += size;
+		ci->from_packet_total_dropped += packets;
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+		ci->mapping[ECM_DB_OBJ_DIR_FROM]->from_data_total_dropped += size;
+		ci->mapping[ECM_DB_OBJ_DIR_FROM]->host->from_data_total_dropped += size;
+		ci->node[ECM_DB_OBJ_DIR_FROM]->from_data_total_dropped += size;
+		ci->mapping[ECM_DB_OBJ_DIR_FROM]->from_packet_total_dropped += packets;
+		ci->mapping[ECM_DB_OBJ_DIR_FROM]->host->from_packet_total_dropped += packets;
+		ci->node[ECM_DB_OBJ_DIR_FROM]->from_packet_total_dropped += packets;
+
+		/*
+		 * Data from the host is essentially TO the interface on which the host is reachable
+		 */
+		for (i = ci->interface_first[ECM_DB_OBJ_DIR_FROM]; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+			ci->interfaces[ECM_DB_OBJ_DIR_FROM][i]->to_data_total_dropped += size;
+			ci->interfaces[ECM_DB_OBJ_DIR_FROM][i]->to_packet_total_dropped += packets;
+		}
+#endif
+		spin_unlock_bh(&ecm_db_lock);
+		return;
+	}
+
+	/*
+	 * Update dropped totals sent by the TO side of this connection
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ci->to_data_total_dropped += size;
+	ci->to_packet_total_dropped += packets;
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	ci->mapping[ECM_DB_OBJ_DIR_TO]->from_data_total_dropped += size;
+	ci->mapping[ECM_DB_OBJ_DIR_TO]->host->from_data_total_dropped += size;
+	ci->node[ECM_DB_OBJ_DIR_TO]->from_data_total_dropped += size;
+	ci->mapping[ECM_DB_OBJ_DIR_TO]->from_packet_total_dropped += packets;
+	ci->mapping[ECM_DB_OBJ_DIR_TO]->host->from_packet_total_dropped += packets;
+	ci->node[ECM_DB_OBJ_DIR_TO]->from_packet_total_dropped += packets;
+
+	/*
+	 * Data from the host is essentially TO the interface on which the host is reachable
+	 */
+	for (i = ci->interface_first[ECM_DB_OBJ_DIR_TO]; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+		ci->interfaces[ECM_DB_OBJ_DIR_TO][i]->to_data_total_dropped += size;
+		ci->interfaces[ECM_DB_OBJ_DIR_TO][i]->to_packet_total_dropped += packets;
+	}
+#endif
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_connection_data_totals_update_dropped);
+
+/*
+ * ecm_db_connection_data_stats_get()
+ *	Return data stats for the instance
+ */
+void ecm_db_connection_data_stats_get(struct ecm_db_connection_instance *ci, uint64_t *from_data_total, uint64_t *to_data_total,
+						uint64_t *from_packet_total, uint64_t *to_packet_total,
+						uint64_t *from_data_total_dropped, uint64_t *to_data_total_dropped,
+						uint64_t *from_packet_total_dropped, uint64_t *to_packet_total_dropped)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	if (from_data_total) {
+		*from_data_total = ci->from_data_total;
+	}
+	if (to_data_total) {
+		*to_data_total = ci->to_data_total;
+	}
+	if (from_packet_total) {
+		*from_packet_total = ci->from_packet_total;
+	}
+	if (to_packet_total) {
+		*to_packet_total = ci->to_packet_total;
+	}
+	if (from_data_total_dropped) {
+		*from_data_total_dropped = ci->from_data_total_dropped;
+	}
+	if (to_data_total_dropped) {
+		*to_data_total_dropped = ci->to_data_total_dropped;
+	}
+	if (from_packet_total_dropped) {
+		*from_packet_total_dropped = ci->from_packet_total_dropped;
+	}
+	if (to_packet_total_dropped) {
+		*to_packet_total_dropped = ci->to_packet_total_dropped;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_connection_data_stats_get);
+
+/*
+ * ecm_db_connection_serial_get()
+ *	Return serial
+ */
+uint32_t ecm_db_connection_serial_get(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	return ci->serial;
+}
+EXPORT_SYMBOL(ecm_db_connection_serial_get);
+
+/*
+ * ecm_db_connection_address_get()
+ *	Return ip address address
+ */
+void ecm_db_connection_address_get(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir, ip_addr_t addr)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	DEBUG_CHECK_MAGIC(ci->mapping[dir], ECM_DB_MAPPING_INSTANCE_MAGIC, "%px: magic failed", ci->mapping[dir]);
+	DEBUG_CHECK_MAGIC(ci->mapping[dir]->host, ECM_DB_HOST_INSTANCE_MAGIC, "%px: magic failed", ci->mapping[dir]->host);
+	ECM_IP_ADDR_COPY(addr, ci->mapping[dir]->host->address);
+}
+EXPORT_SYMBOL(ecm_db_connection_address_get);
+
+/*
+ * ecm_db_connection_port_get()
+ *	Return port
+ */
+int ecm_db_connection_port_get(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	DEBUG_CHECK_MAGIC(ci->mapping[dir], ECM_DB_MAPPING_INSTANCE_MAGIC, "%px: magic failed", ci->mapping[dir]);
+	return ci->mapping[dir]->port;
+}
+EXPORT_SYMBOL(ecm_db_connection_port_get);
+
+/*
+ * ecm_db_connection_node_address_get()
+ *	Return address of the node used when sending packets to the specified side.
+ */
+void ecm_db_connection_node_address_get(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir, uint8_t *address_buffer)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	memcpy(address_buffer, ci->node[dir]->address, ETH_ALEN);
+}
+EXPORT_SYMBOL(ecm_db_connection_node_address_get);
+
+/*
+ * ecm_db_connection_iface_name_get()
+ *	Return name of interface on which the specified side may be reached
+ */
+void ecm_db_connection_iface_name_get(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir, char *name_buffer)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	strlcpy(name_buffer, ci->node[dir]->iface->name, IFNAMSIZ);
+}
+EXPORT_SYMBOL(ecm_db_connection_iface_name_get);
+
+/*
+ * ecm_db_connection_iface_mtu_get()
+ *	Return MTU of interface on which the specified side may be reached
+ */
+int ecm_db_connection_iface_mtu_get(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir)
+{
+	int mtu;
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	spin_lock_bh(&ecm_db_lock);
+	mtu = ci->node[dir]->iface->mtu;
+	spin_unlock_bh(&ecm_db_lock);
+	return mtu;
+}
+EXPORT_SYMBOL(ecm_db_connection_iface_mtu_get);
+
+/*
+ * ecm_db_connection_iface_type_get()
+ *	Return type of interface on which the specified side may be reached
+ */
+ecm_db_iface_type_t ecm_db_connection_iface_type_get(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir)
+{
+	ecm_db_iface_type_t type;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	spin_lock_bh(&ecm_db_lock);
+	type = ci->node[dir]->iface->type;
+	spin_unlock_bh(&ecm_db_lock);
+	return type;
+}
+EXPORT_SYMBOL(ecm_db_connection_iface_type_get);
+
+/*
+ * ecm_db_connection_regeneration_occurrances_get()
+ *	Get the number of regeneration occurrances that have occurred since the connection was created.
+ */
+uint16_t ecm_db_connection_regeneration_occurrances_get(struct ecm_db_connection_instance *ci)
+{
+	uint16_t occurances;
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	occurances = ci->regen_occurances;
+	spin_unlock_bh(&ecm_db_lock);
+	return occurances;
+}
+EXPORT_SYMBOL(ecm_db_connection_regeneration_occurrances_get);
+
+/*
+ * ecm_db_connection_regeneration_completed()
+ *	Re-generation was completed successfully
+ */
+void ecm_db_connection_regeneration_completed(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+
+	DEBUG_ASSERT(ci->regen_in_progress, "%px: Bad call", ci);
+	DEBUG_ASSERT(ci->regen_required > 0, "%px: Bad call", ci);
+
+	/*
+	 * Decrement the required counter by 1.
+	 * This may mean that regeneration is still required due to another change occuring _during_ re-generation.
+	 */
+	ci->regen_required--;
+	ci->regen_in_progress = false;
+	ci->regen_success++;
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_connection_regeneration_completed);
+
+/*
+ * ecm_db_connection_regeneration_failed()
+ *	Re-generation failed
+ */
+void ecm_db_connection_regeneration_failed(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+
+	DEBUG_ASSERT(ci->regen_in_progress, "%px: Bad call", ci);
+	DEBUG_ASSERT(ci->regen_required > 0, "%px: Bad call", ci);
+
+	/*
+	 * Re-generation is no longer in progress BUT we leave the regen
+	 * counter as it is so as to indicate re-generation is still needed
+	 */
+	ci->regen_in_progress = false;
+	ci->regen_fail++;
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_connection_regeneration_failed);
+
+/*
+ * ecm_db_connection_regeneration_required_check()
+ *	Returns true if the connection needs to be re-generated.
+ *
+ * If re-generation is needed this will mark the connection to indicate that re-generation is needed AND in progress.
+ * If the return code is TRUE the caller MUST handle the re-generation.
+ * Upon re-generation completion you must call ecm_db_connection_regeneration_completed() or ecm_db_connection_regeneration_failed().
+ */
+bool ecm_db_connection_regeneration_required_check(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	/*
+	 * Check the global generation counter for changes
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	if (ci->generation != ecm_db_connection_generation) {
+		/*
+		 * Re-generation is needed
+		 */
+		ci->regen_occurances++;
+		ci->regen_required++;
+
+		/*
+		 * Record that we have seen this change
+		 */
+		ci->generation = ecm_db_connection_generation;
+	}
+
+	/*
+	 * If re-generation is in progress then something is handling re-generation already
+	 * so we tell the caller that it cannot handle re-generation.
+	 */
+	if (ci->regen_in_progress) {
+		spin_unlock_bh(&ecm_db_lock);
+		return false;
+	}
+
+	/*
+	 * Is re-generation required?
+	 */
+	if (ci->regen_required == 0) {
+		spin_unlock_bh(&ecm_db_lock);
+		return false;
+	}
+
+	/*
+	 * Flag that re-generation is in progress and tell the caller to handle re-generation
+	 */
+	ci->regen_in_progress = true;
+	spin_unlock_bh(&ecm_db_lock);
+	return true;
+}
+EXPORT_SYMBOL(ecm_db_connection_regeneration_required_check);
+
+/*
+ * ecm_db_connection_regeneration_required_peek()
+ *	Returns true if the connection needs to be regenerated.
+ *
+ * NOTE: The caller MUST NOT handle re-generation, the caller may use this indication
+ * to determine the sanity of the connection state and whether acceleration is permitted.
+ */
+bool ecm_db_connection_regeneration_required_peek(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+
+	/*
+	 * Check the global generation counter for changes (record any change now)
+	 */
+	if (ci->generation != ecm_db_connection_generation) {
+		/*
+		 * Re-generation is needed, flag the connection as needing re-generation now.
+		 */
+		ci->regen_occurances++;
+		ci->regen_required++;
+
+		/*
+		 * Record that we have seen this change
+		 */
+		ci->generation = ecm_db_connection_generation;
+	}
+	if (ci->regen_required == 0) {
+		spin_unlock_bh(&ecm_db_lock);
+		return false;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return true;
+}
+EXPORT_SYMBOL(ecm_db_connection_regeneration_required_peek);
+
+/*
+ * ecm_db_connection_regeneration_needed()
+ *	Cause a specific connection to require re-generation
+ *
+ * NOTE: This only flags that re-generation is needed.
+ * The connection will typically be re-generated when ecm_db_connection_regeneration_required_check() is invoked.
+ */
+void ecm_db_connection_regeneration_needed(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	ci->regen_occurances++;
+	ci->regen_required++;
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_connection_regeneration_needed);
+
+/*
+ * ecm_db_regeneration_needed()
+ *	Bump the global generation index to cause a re-generation of all connections state.
+ */
+void ecm_db_regeneration_needed(void)
+{
+	spin_lock_bh(&ecm_db_lock);
+	ecm_db_connection_generation++;
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_regeneration_needed);
+
+/*
+ * ecm_db_connection_regenerate()
+ *	Re-generate a specific connection
+ */
+void ecm_db_connection_regenerate(struct ecm_db_connection_instance *ci)
+{
+	struct ecm_front_end_connection_instance *feci;
+
+	DEBUG_TRACE("Regenerate connection: %px\n", ci);
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	/*
+	 * Notify front end to regenerate a connection.
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	feci->regenerate(feci, ci);
+	feci->deref(feci);
+}
+EXPORT_SYMBOL(ecm_db_connection_regenerate);
+
+/*
+ * ecm_db_connection_direction_get()
+ *	Return direction of the connection.
+ *
+ * NOTE: an EGRESS connection means that packets being sent to mapping_to should have qos applied.
+ * INGRESS means that packets being sent to mapping[ECM_DB_OBJ_DIR_FROM] should have qos applied.
+ */
+ecm_db_direction_t ecm_db_connection_direction_get(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	return ci->direction;
+}
+EXPORT_SYMBOL(ecm_db_connection_direction_get);
+
+/*
+ * ecm_db_connection_is_routed_get()
+ *	Return whether connection is a routed path or not
+ */
+bool ecm_db_connection_is_routed_get(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	return ci->is_routed;
+}
+EXPORT_SYMBOL(ecm_db_connection_is_routed_get);
+
+/*
+ * ecm_db_connection_protocol_get()
+ *	Return protocol of connection
+ */
+int ecm_db_connection_protocol_get(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	return ci->protocol;
+}
+EXPORT_SYMBOL(ecm_db_connection_protocol_get);
+
+/*
+ * ecm_db_connection_ip_version_get()
+ *	Return IP version of connection
+ */
+int ecm_db_connection_ip_version_get(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	return ci->ip_version;
+}
+EXPORT_SYMBOL(ecm_db_connection_ip_version_get);
+
+/*
+ * ecm_db_connection_is_pppoe_bridged_get()
+ *	Return whether connection is pppoe bridged or not
+ */
+bool ecm_db_connection_is_pppoe_bridged_get(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	return ci->flags & ECM_DB_CONNECTION_FLAGS_PPPOE_BRIDGE;
+}
+
+/*
+ * ecm_db_connection_defunct_timer_remove_and_set()
+ *	Move the connection to a new timer group.
+ *
+ * Before setting the new group, check if the timer group is set. If it is set,
+ * remove it first from the current group.
+ *
+ */
+void ecm_db_connection_defunct_timer_remove_and_set(struct ecm_db_connection_instance *ci, ecm_db_timer_group_t tg)
+{
+	struct ecm_db_timer_group_entry *tge;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	DEBUG_TRACE("%px: ecm_db_connection_defunct_timer_remove_and_set\n", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	tge = &ci->defunct_timer;
+	if (tge->group == tg) {
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("%px: timer group is aslready equal to %d\n", ci, tg);
+		return;
+	}
+
+	if (tge->group != ECM_DB_TIMER_GROUPS_MAX) {
+		_ecm_db_timer_group_entry_remove(tge);
+	}
+
+	/*
+	 * Set new group
+	 */
+	_ecm_db_timer_group_entry_set(tge, tg);
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("%px: New timer group is: %d\n", ci, tge->group);
+}
+EXPORT_SYMBOL(ecm_db_connection_defunct_timer_remove_and_set);
+
+/*
+ * _ecm_db_connection_ref()
+ */
+void _ecm_db_connection_ref(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	ci->refs++;
+	DEBUG_TRACE("%px: connection ref %d\n", ci, ci->refs);
+	DEBUG_ASSERT(ci->refs > 0, "%px: ref wrap\n", ci);
+}
+
+/*
+ * ecm_db_connection_ref()
+ */
+void ecm_db_connection_ref(struct ecm_db_connection_instance *ci)
+{
+	spin_lock_bh(&ecm_db_lock);
+	_ecm_db_connection_ref(ci);
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_connection_ref);
+
+/*
+ * ecm_db_connections_get_and_ref_first()
+ *	Obtain a ref to the first connection instance, if any
+ */
+struct ecm_db_connection_instance *ecm_db_connections_get_and_ref_first(void)
+{
+	struct ecm_db_connection_instance *ci;
+	spin_lock_bh(&ecm_db_lock);
+	ci = ecm_db_connections;
+	if (ci) {
+		_ecm_db_connection_ref(ci);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return ci;
+}
+EXPORT_SYMBOL(ecm_db_connections_get_and_ref_first);
+
+/*
+ * ecm_db_connection_get_and_ref_next()
+ *	Return the next connection in the list given a connection
+ */
+struct ecm_db_connection_instance *ecm_db_connection_get_and_ref_next(struct ecm_db_connection_instance *ci)
+{
+	struct ecm_db_connection_instance *cin;
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	spin_lock_bh(&ecm_db_lock);
+	cin = ci->next;
+	if (cin) {
+		_ecm_db_connection_ref(cin);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return cin;
+}
+EXPORT_SYMBOL(ecm_db_connection_get_and_ref_next);
+
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+/*
+ * _ecm_db_classifier_type_assignment_remove()
+ *	Remove the connection from the classifier type assignment list (of the given type)
+ */
+static void _ecm_db_classifier_type_assignment_remove(struct ecm_db_connection_instance *ci, ecm_classifier_type_t ca_type)
+{
+	struct ecm_db_connection_classifier_type_assignment *ta;
+	struct ecm_db_connection_classifier_type_assignment_list *tal;
+
+	DEBUG_ASSERT(spin_is_locked(&ecm_db_lock), "%px: lock is not held\n", ci);
+
+	DEBUG_TRACE("%px: Classifier type assignment remove: %d\n", ci, ca_type);
+	ta = &ci->type_assignment[ca_type];
+	DEBUG_CHECK_MAGIC(ta, ECM_DB_CLASSIFIER_TYPE_ASSIGNMENT_MAGIC, "%px: magic failed, ci: %px\n", ta, ci);
+	DEBUG_ASSERT(ta->iteration_count == 0, "%px: iteration count: %d, type: %d\n", ci, ta->iteration_count, ca_type);
+
+	if (ta->next) {
+		struct ecm_db_connection_classifier_type_assignment *tan = &ta->next->type_assignment[ca_type];
+		DEBUG_ASSERT(tan->prev == ci, "Bad list, expecting: %px, got: %px\n", ci, tan->prev);
+		tan->prev = ta->prev;
+	}
+
+	tal = &ecm_db_connection_classifier_type_assignments[ca_type];
+	if (ta->prev) {
+		struct ecm_db_connection_classifier_type_assignment *tap = &ta->prev->type_assignment[ca_type];
+		DEBUG_ASSERT(tap->next == ci, "Bad list, expecting: %px, got: %px\n", ci, tap->next);
+		tap->next = ta->next;
+	} else {
+		/*
+		 * Set new head of list
+		 */
+		DEBUG_ASSERT(tal->type_assignments_list == ci, "Bad head, expecting %px, got %px, type: %d\n", ci, tal->type_assignments_list, ca_type);
+		tal->type_assignments_list = ta->next;
+	}
+	ta->next = NULL;
+	ta->prev = NULL;
+	ta->pending_unassign = false;
+
+	/*
+	 * Decrement assignment count
+	 */
+	tal->type_assignment_count--;
+	DEBUG_ASSERT(tal->type_assignment_count >= 0, "Bad type assignment count: %d, type: %d\n", tal->type_assignment_count, ca_type);
+
+	DEBUG_CLEAR_MAGIC(ta);
+}
+#endif
+
+/*
+ * _ecm_db_connection_classifier_unassign()
+ *	Unassign a classifier and remove the classifier type
+ *
+ * The default classifier cannot be unassigned.
+ */
+static inline void _ecm_db_connection_classifier_unassign(struct ecm_db_connection_instance *ci, struct ecm_classifier_instance *cci, ecm_classifier_type_t ca_type)
+{
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+	struct ecm_db_connection_classifier_type_assignment *ta;
+#endif
+	DEBUG_ASSERT(spin_is_locked(&ecm_db_lock), "%px: lock is not held\n", ci);
+
+	/*
+	 * Clear the assignment.
+	 */
+	ci->assignments_by_type[ca_type] = NULL;
+
+	/*
+	 * Link out of assignments list
+	 */
+	if (cci->ca_prev) {
+		cci->ca_prev->ca_next = cci->ca_next;
+	} else {
+		DEBUG_ASSERT(ci->assignments == cci, "%px: Bad assigmnment list, expecting: %px, got: %px", ci, cci, ci->assignments);
+		ci->assignments = cci->ca_next;
+	}
+	if (cci->ca_next) {
+		cci->ca_next->ca_prev = cci->ca_prev;
+	}
+	cci->ca_next = NULL;
+	cci->ca_prev = NULL;
+
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+	/*
+	 * Remove from the classifier type assignment list
+	 */
+	ta = &ci->type_assignment[ca_type];
+	DEBUG_CHECK_MAGIC(ta, ECM_DB_CLASSIFIER_TYPE_ASSIGNMENT_MAGIC, "%px: magic failed, ci: %px", ta, ci);
+	if (ta->iteration_count > 0) {
+		/*
+		 * The list entry is being iterated outside of db lock being held.
+		 * We cannot remove this entry since it would mess up iteration.
+		 * Set the pending flag to be actioned another time
+		 */
+		ta->pending_unassign = true;
+		return;
+	}
+
+	/*
+	 * Remove the list entry
+	 */
+	DEBUG_INFO("%px: Remove type assignment: %d\n", ci, ca_type);
+	_ecm_db_classifier_type_assignment_remove(ci, ca_type);
+#endif
+	cci->deref(cci);
+}
+
+/*
+ * ecm_db_connection_deref()
+ *	Release reference to connection.  Connection is removed from database on final deref and destroyed.
+ */
+int ecm_db_connection_deref(struct ecm_db_connection_instance *ci)
+{
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+	ecm_classifier_type_t ca_type;
+#endif
+	int32_t i;
+	int32_t dir;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	ci->refs--;
+	DEBUG_TRACE("%px: connection deref %d\n", ci, ci->refs);
+	DEBUG_ASSERT(ci->refs >= 0, "%px: ref wrap\n", ci);
+
+	if (ci->refs > 0) {
+		int refs = ci->refs;
+		spin_unlock_bh(&ecm_db_lock);
+		return refs;
+	}
+
+#ifdef ECM_MULTICAST_ENABLE
+	/*
+	 * For multicast connections, we need to deref the
+	 * associated tuple instance as well
+	 */
+	if (ci->ti) {
+		_ecm_db_multicast_tuple_instance_deref(ci->ti);
+	}
+#endif
+	/*
+	 * Remove from database if inserted
+	 */
+	if (!ci->flags & ECM_DB_CONNECTION_FLAGS_INSERTED) {
+		spin_unlock_bh(&ecm_db_lock);
+	} else {
+		struct ecm_db_listener_instance *li;
+#ifdef ECM_DB_XREF_ENABLE
+		struct ecm_db_iface_instance *iface[ECM_DB_OBJ_DIR_MAX];
+#endif
+
+		/*
+		 * Remove it from the connection hash table
+		 */
+		if (!ci->hash_prev) {
+			DEBUG_ASSERT(ecm_db_connection_table[ci->hash_index] == ci, "%px: hash table bad\n", ci);
+			ecm_db_connection_table[ci->hash_index] = ci->hash_next;
+		} else {
+			ci->hash_prev->hash_next = ci->hash_next;
+		}
+		if (ci->hash_next) {
+			ci->hash_next->hash_prev = ci->hash_prev;
+		}
+		ci->hash_prev = NULL;
+		ci->hash_next = NULL;
+		ecm_db_connection_table_lengths[ci->hash_index]--;
+		DEBUG_ASSERT(ecm_db_connection_table_lengths[ci->hash_index] >= 0, "%px: invalid table len %d\n", ci, ecm_db_connection_table_lengths[ci->hash_index]);
+
+		/*
+		 * Remove it from the connection serial hash table
+		 */
+		if (!ci->serial_hash_prev) {
+			DEBUG_ASSERT(ecm_db_connection_serial_table[ci->serial_hash_index] == ci, "%px: hash table bad\n", ci);
+			ecm_db_connection_serial_table[ci->serial_hash_index] = ci->serial_hash_next;
+		} else {
+			ci->serial_hash_prev->serial_hash_next = ci->serial_hash_next;
+		}
+		if (ci->serial_hash_next) {
+			ci->serial_hash_next->serial_hash_prev = ci->serial_hash_prev;
+		}
+		ci->serial_hash_prev = NULL;
+		ci->serial_hash_next = NULL;
+		ecm_db_connection_serial_table_lengths[ci->serial_hash_index]--;
+		DEBUG_ASSERT(ecm_db_connection_serial_table_lengths[ci->serial_hash_index] >= 0, "%px: invalid table len %d\n", ci, ecm_db_connection_serial_table_lengths[ci->serial_hash_index]);
+
+		/*
+		 * Remove from the global list
+		 */
+		if (!ci->prev) {
+			DEBUG_ASSERT(ecm_db_connections == ci, "%px: conn table bad\n", ci);
+			ecm_db_connections = ci->next;
+		} else {
+			ci->prev->next = ci->next;
+		}
+		if (ci->next) {
+			ci->next->prev = ci->prev;
+		}
+		ci->prev = NULL;
+		ci->next = NULL;
+
+#ifdef ECM_DB_XREF_ENABLE
+		/*
+		 * Remove connection from the mappings' connection list
+		 */
+		for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+			if (!ci->mapping_prev[dir]) {
+				DEBUG_ASSERT(ci->mapping[dir]->connections[dir] == ci, "%px: %s conn table bad\n", ci, ecm_db_obj_dir_strings[dir]);
+				ci->mapping[dir]->connections[dir] = ci->mapping_next[dir];
+			} else {
+				ci->mapping_prev[dir]->mapping_next[dir] = ci->mapping_next[dir];
+			}
+			if (ci->mapping_next[dir]) {
+				ci->mapping_next[dir]->mapping_prev[dir] = ci->mapping_prev[dir];
+			}
+			ci->mapping_prev[dir] = NULL;
+			ci->mapping_next[dir] = NULL;
+		}
+
+		/*
+		 * Remove connection from the ifaces' connection list
+		 * GGG TODO Deprecated. Interface lists will be used instead. To be deleted.
+		 */
+		for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+			iface[dir] = ci->node[dir]->iface;
+			if (!ci->iface_prev[dir]) {
+				DEBUG_ASSERT(iface[dir]->connections[dir] == ci,
+					     "%px: iface %s conn table bad\n",
+					     ci, ecm_db_obj_dir_strings[dir]);
+				iface[dir]->connections[dir] = ci->iface_next[dir];
+			} else {
+				ci->iface_prev[dir]->iface_next[dir] = ci->iface_next[dir];
+			}
+			if (ci->iface_next[dir]) {
+				ci->iface_next[dir]->iface_prev[dir] = ci->iface_prev[dir];
+			}
+			ci->iface_prev[dir] = NULL;
+			ci->iface_next[dir] = NULL;
+		}
+
+		/*
+		 * Remove connection from its nodes' connection list
+		 */
+		for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+			if (!ci->node_prev[dir]) {
+				DEBUG_ASSERT(ci->node[dir]->connections[dir] == ci,
+					     "%px: %s node conn table bad, got: %px\n",
+					     ci, ecm_db_obj_dir_strings[dir], ci->node[dir]->connections[dir]);
+				ci->node[dir]->connections[dir] = ci->node_next[dir];
+			} else {
+				ci->node_prev[dir]->node_next[dir] = ci->node_next[dir];
+			}
+			if (ci->node_next[dir]) {
+				ci->node_next[dir]->node_prev[dir] = ci->node_prev[dir];
+			}
+			ci->node_prev[dir] = NULL;
+			ci->node_next[dir] = NULL;
+			ci->node[dir]->connections_count[dir]--;
+			DEBUG_ASSERT(ci->node[dir]->connections_count[dir] >= 0, "%px: %s node bad count\n", ci, ecm_db_obj_dir_strings[dir]);
+		}
+#endif
+
+		/*
+		 * Update the counters in the mappings
+		 */
+		if (ci->protocol == IPPROTO_UDP) {
+			for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+				ci->mapping[dir]->udp_count[dir]--;
+			}
+		} else if (ci->protocol == IPPROTO_TCP) {
+			for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+				ci->mapping[dir]->tcp_count[dir]--;
+			}
+		}
+
+		for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+			ci->mapping[dir]->conn_count[dir]--;
+		}
+
+		/*
+		 * Assert that the defunt timer has been detached
+		 */
+		DEBUG_ASSERT(ci->defunct_timer.group == ECM_DB_TIMER_GROUPS_MAX, "%px: unexpected timer group %d\n", ci, ci->defunct_timer.group);
+
+		/*
+		 * Decrement protocol counter stats
+		 */
+		ecm_db_connection_count_by_protocol[ci->protocol]--;
+		DEBUG_ASSERT(ecm_db_connection_count_by_protocol[ci->protocol] >= 0, "%px: Invalid protocol count %d\n", ci, ecm_db_connection_count_by_protocol[ci->protocol]);
+
+		spin_unlock_bh(&ecm_db_lock);
+
+		/*
+		 * Throw removed event to listeners
+		 */
+		DEBUG_TRACE("%px: Throw connection removed event\n", ci);
+		li = ecm_db_listeners_get_and_ref_first();
+		while (li) {
+			struct ecm_db_listener_instance *lin;
+			if (li->connection_removed) {
+				li->connection_removed(li->arg, ci);
+			}
+
+			/*
+			 * Get next listener
+			 */
+			lin = ecm_db_listener_get_and_ref_next(li);
+			ecm_db_listener_deref(li);
+			li = lin;
+		}
+	}
+
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+	/*
+	 * Unlink from the "assignments by classifier type" lists.
+	 *
+	 * This is done whether the connection is inserted into the database or not - this is because
+	 * classifier assignments take place before adding into the db.
+	 *
+	 * NOTE: We know that the ci is not being iterated in any of these lists because otherwise
+	 * ci would be being held as part of iteration and so we would not be here!
+	 * Equally we know that if the assignments_by_type[] element is non-null then it must also be in the relevant list too.
+	 *
+	 * Default classifier is not in the classifier type assignement list, so we should start the loop index
+	 * with the first assigned classifier type.
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	for (ca_type = ECM_CLASSIFIER_TYPE_DEFAULT + 1; ca_type < ECM_CLASSIFIER_TYPES; ++ca_type) {
+		struct ecm_classifier_instance *cci = ci->assignments_by_type[ca_type];
+		if (!cci) {
+			/*
+			 * No assignment of this type, so would not be in the classifier type assignments list
+			 */
+			continue;
+		}
+		_ecm_db_connection_classifier_unassign(ci, cci, ca_type);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+#endif
+
+	/*
+	 * Throw final event
+	 */
+	if (ci->final) {
+		ci->final(ci->arg);
+	}
+
+	/*
+	 * Release instances to the objects referenced by the connection
+	 */
+	while (ci->assignments) {
+		struct ecm_classifier_instance *classi = ci->assignments;
+		ci->assignments = classi->ca_next;
+		classi->deref(classi);
+	}
+
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		if (ci->mapping[dir]) {
+			ecm_db_mapping_deref(ci->mapping[dir]);
+		}
+	}
+
+	if (ci->feci) {
+		ci->feci->deref(ci->feci);
+	}
+
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		if (ci->node[dir]) {
+			ecm_db_node_deref(ci->node[dir]);
+		}
+	}
+
+	/*
+	 * Remove references to the interfaces in our heirarchy lists
+	 */
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		for (i = ci->interface_first[dir]; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+			DEBUG_TRACE("%px: %s interface %d remove: %px\n", ci, ecm_db_obj_dir_strings[dir], i, ci->interfaces[dir][i]);
+			ecm_db_iface_deref(ci->interfaces[dir][i]);
+		}
+	}
+
+#ifdef ECM_MULTICAST_ENABLE
+	/*
+	 * Remove references to the multicast interfaces of this connection.
+	 */
+	ecm_db_multicast_connection_to_interfaces_clear(ci);
+#endif
+	/*
+	 * We can now destroy the instance
+	 */
+	DEBUG_CLEAR_MAGIC(ci);
+	kfree(ci);
+
+	/*
+	 * Decrease global connection count
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ecm_db_connection_count--;
+	DEBUG_ASSERT(ecm_db_connection_count >= 0, "%px: connection count wrap\n", ci);
+	spin_unlock_bh(&ecm_db_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_db_connection_deref);
+
+/*
+ * ecm_db_connection_defunct_all()
+ *	Make defunct ALL connections.
+ *
+ * This API is typically used in shutdown situations commanded by the user.
+ * NOTE: Ensure all front ends are stopped to avoid further connections being created while this is running.
+ */
+void ecm_db_connection_defunct_all(void)
+{
+	struct ecm_db_connection_instance *ci;
+
+	DEBUG_INFO("Defuncting all\n");
+
+	/*
+	 * Iterate all connections
+	 */
+	ci = ecm_db_connections_get_and_ref_first();
+	while (ci) {
+		struct ecm_db_connection_instance *cin;
+
+		DEBUG_TRACE("%px: defunct\n", ci);
+		ecm_db_connection_make_defunct(ci);
+
+		cin = ecm_db_connection_get_and_ref_next(ci);
+		ecm_db_connection_deref(ci);
+		ci = cin;
+	}
+	DEBUG_INFO("Defuncting complete\n");
+}
+EXPORT_SYMBOL(ecm_db_connection_defunct_all);
+
+/*
+ * ecm_db_connection_defunct_by_classifier()
+ *	Make defunct based on masked fields
+ */
+void ecm_db_connection_defunct_by_classifier(int ip_ver, ip_addr_t src_addr_mask, uint16_t src_port_mask,
+					     ip_addr_t dest_addr_mask, uint16_t dest_port_mask,
+					     int proto_mask, bool is_routed, ecm_classifier_type_t ca_type)
+{
+	struct ecm_db_connection_instance *ci;
+	int cnt = 0;
+	char *direction = NULL;
+
+	/*
+	 * Iterate all connections
+	 */
+	ci = ecm_db_connections_get_and_ref_first();
+	while (ci) {
+		struct ecm_db_connection_instance *cin;
+		struct ecm_classifier_instance *eci;
+		ip_addr_t sip;
+		ip_addr_t dip;
+		uint16_t sport, dport;
+		int proto;
+
+		DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+		eci = ecm_db_connection_assigned_classifier_find_and_ref(ci, ca_type);
+		if (!eci) {
+			goto next_ci;
+		}
+		eci->deref(eci);
+
+		/*
+		 *  Ignore connection with wrong version
+		 */
+		if (ip_ver != ECM_DB_IP_VERSION_IGNORE && (ecm_db_connection_ip_version_get(ci) != ip_ver)) {
+			goto next_ci;
+		}
+
+		/*
+		 * Skip routed connection for bridge flow
+		 * Skip bridge connection for routed flow
+		 */
+		if (is_routed != ecm_db_connection_is_routed_get(ci)) {
+			goto next_ci;
+		}
+
+		/*
+		 * Check protocol if specified
+		 */
+		proto = ecm_db_connection_protocol_get(ci);
+		if (!ECM_PROTO_MASK_MATCH(proto, proto_mask)) {
+			goto next_ci;
+		}
+
+		/*
+		 * A : PCI < ------- br-home ----------bridging----------------br-wan ---->PC2
+		 *
+		 * B : PCI < ------- br-home ----------Routing----------------br-wan ---->PC2
+		 *
+		 *							DNAT
+		 * C : PCI < ------- br-home ----------Routing----------------br-wan ----> PC2
+		 *							SNAT
+		 * D : PCI < ------- br-home ----------Routing----------------br-wan ----> PC2
+		 */
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, sip);
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dip);
+		sport = ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM);
+		dport = ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO);
+
+		/*
+		 * 1. For topology A, B, C, D  if drop rule is added in br-home or br-wan
+		 * 2. For topoloy  A, B  if drop rule is added in br-wan
+		 * Match in flow direction
+		 */
+		if (ECM_IP_ADDR_MASK_MATCH(sip, src_addr_mask) &&
+		    ECM_IP_ADDR_MASK_MATCH(dip, dest_addr_mask) &&
+		    ECM_PORT_MASK_MATCH(sport, src_port_mask) &&
+		    ECM_PORT_MASK_MATCH(dport, dest_port_mask)) {
+			direction = "flow";
+			goto defunct_conn;
+		}
+
+		/*
+		 * 1. For topology A, B, C, D  if drop rule is added in br-home or br-wan
+		 * 2. For topoloy  A, B  if drop rule is added in br-wan
+		 * Match in reverse direction
+		 */
+		if (ECM_IP_ADDR_MASK_MATCH(dip, src_addr_mask) &&
+		    ECM_IP_ADDR_MASK_MATCH(sip, dest_addr_mask) &&
+		    ECM_PORT_MASK_MATCH(dport, src_port_mask) &&
+		    ECM_PORT_MASK_MATCH(sport, dest_port_mask)) {
+			direction = "reverse";
+			goto defunct_conn;
+		}
+
+		/*
+		 * There is no NATing in case of bridging
+		 */
+		if (!is_routed) {
+			goto next_ci;
+		}
+
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM_NAT, sip);
+		ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO_NAT, dip);
+		sport = ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM_NAT);
+		dport = ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO_NAT);
+
+		/*
+		 * 1. For topoloy  C, D  if drop rule is added in br-wan
+		 * Match in flow direction
+		 */
+		if (ECM_IP_ADDR_MASK_MATCH(sip, src_addr_mask) &&
+		    ECM_IP_ADDR_MASK_MATCH(dip, dest_addr_mask) &&
+		    ECM_PORT_MASK_MATCH(sport, src_port_mask) &&
+		    ECM_PORT_MASK_MATCH(dport, dest_port_mask)) {
+			direction = "flow (nat)";
+			goto defunct_conn;
+		}
+
+		/*
+		 * 1. For topoloy  C, D  if drop rule is added in br-wan
+		 * Match in reverse direction
+		 */
+		if (ECM_IP_ADDR_MASK_MATCH(dip, src_addr_mask) &&
+		    ECM_IP_ADDR_MASK_MATCH(sip, dest_addr_mask) &&
+		    ECM_PORT_MASK_MATCH(dport, src_port_mask) &&
+		    ECM_PORT_MASK_MATCH(sport, dest_port_mask)) {
+			direction = "reverse (nat)";
+			goto defunct_conn;
+		}
+
+		goto next_ci;
+
+defunct_conn:
+		cnt++;
+		if (ECM_IP_ADDR_IS_V4(src_addr_mask)) {
+			DEBUG_TRACE("%px: Defunct CI masked 5 tuple match(%s) src=" ECM_IP_ADDR_DOT_FMT " sport=%d dest="
+					ECM_IP_ADDR_DOT_FMT ", dport=%d, proto=%d cnt=%d\n", ci, direction,
+					ECM_IP_ADDR_TO_DOT(sip), sport, ECM_IP_ADDR_TO_DOT(dip), dport, proto, cnt);
+		} else {
+			DEBUG_TRACE("%px: Defunct CI masked 5 tuple match(%s) src=" ECM_IP_ADDR_OCTAL_FMT " sport=%d dest="
+					ECM_IP_ADDR_OCTAL_FMT ", dport=%d, proto=%d, cnt=%d\n", ci, direction,
+					ECM_IP_ADDR_TO_OCTAL(sip), sport, ECM_IP_ADDR_TO_OCTAL(dip), dport, proto, cnt);
+		}
+
+		ecm_db_connection_make_defunct(ci);
+
+next_ci:
+		cin = ecm_db_connection_get_and_ref_next(ci);
+		ecm_db_connection_deref(ci);
+		ci = cin;
+	}
+
+	if (ECM_IP_ADDR_IS_V4(src_addr_mask)) {
+		DEBUG_TRACE("%px: Defunct request by masked 5 tuple src_mask=" ECM_IP_ADDR_DOT_FMT " sport_mask=%d, dest_mask="
+				ECM_IP_ADDR_DOT_FMT " dport_mask=%d, proto_mask=%d, cnt=%d\n", ci,
+				ECM_IP_ADDR_TO_DOT(src_addr_mask), src_port_mask, ECM_IP_ADDR_TO_DOT(dest_addr_mask),
+				dest_port_mask, proto_mask, cnt);
+	} else {
+		DEBUG_TRACE("%px: Defunct request by masked 5 tuple src_mask=" ECM_IP_ADDR_OCTAL_FMT " sport_mask=%d dest_mask="
+				ECM_IP_ADDR_OCTAL_FMT " dport_mask=%d, proto_mask=%d cnt=%d\n", ci,
+				ECM_IP_ADDR_TO_OCTAL(src_addr_mask), src_port_mask,
+				ECM_IP_ADDR_TO_OCTAL(dest_addr_mask), dest_port_mask, proto_mask, cnt);
+	}
+}
+
+/*
+ * ecm_db_connection_defunct_by_port()
+ *	 Make defunct based on source or destination port.
+ */
+void ecm_db_connection_defunct_by_port(int port, ecm_db_obj_dir_t dir)
+{
+	struct ecm_db_connection_instance *ci;
+
+	DEBUG_INFO("Defuncting all matching connections by port %d\n", port);
+
+	/*
+	 * Iterate all connections
+	 */
+	ci = ecm_db_connections_get_and_ref_first();
+	while (ci) {
+		struct ecm_db_connection_instance *cin;
+		DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+		/*
+		 * Flush the connection matching with given port address and flow direction
+		 */
+		if (port == htons(ecm_db_connection_port_get(ci, dir))) {
+			DEBUG_TRACE("%px: defunct\n", ci);
+			ecm_db_connection_make_defunct(ci);
+		}
+
+		cin = ecm_db_connection_get_and_ref_next(ci);
+		ecm_db_connection_deref(ci);
+		ci = cin;
+	}
+	DEBUG_INFO("Port based Defuncting complete\n");
+}
+EXPORT_SYMBOL(ecm_db_connection_defunct_by_port);
+
+/*
+ * ecm_db_connection_defunct_by_protocol()
+ * 	Make defunct based on protocol.
+ */
+void ecm_db_connection_defunct_by_protocol(int protocol)
+{
+	struct ecm_db_connection_instance *ci;
+
+	DEBUG_INFO("Defuncting all matching connections by protocol %d\n", protocol);
+
+	/*
+	 * Iterate all connections
+	 */
+	ci = ecm_db_connections_get_and_ref_first();
+	while (ci) {
+		struct ecm_db_connection_instance *cin;
+		DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+		/*
+		 * Flush the connection matching with given protocol
+		 */
+		if (protocol == ecm_db_connection_protocol_get(ci)) {
+			DEBUG_TRACE("%px: defunct\n", ci);
+			ecm_db_connection_make_defunct(ci);
+		}
+
+		cin = ecm_db_connection_get_and_ref_next(ci);
+		ecm_db_connection_deref(ci);
+		ci = cin;
+	}
+	DEBUG_INFO("Protocol based defuncting complete\n");
+}
+EXPORT_SYMBOL(ecm_db_connection_defunct_by_protocol);
+
+/*
+ * ecm_db_connection_defunct_ip_version()
+ *	Make defunct based on the IP version (IPv4 or IPv6).
+ */
+void ecm_db_connection_defunct_ip_version(int ip_version)
+{
+	struct ecm_db_connection_instance *ci;
+
+	DEBUG_ASSERT(ip_version == 4 || ip_version == 6, "Wrong ip_version: %d\n", ip_version);
+
+	DEBUG_INFO("Defuncting IPv%d connections\n", ip_version);
+
+	/*
+	 * Iterate all connections
+	 */
+	ci = ecm_db_connections_get_and_ref_first();
+	while (ci) {
+		struct ecm_db_connection_instance *cin;
+
+		if (ci->ip_version == ip_version) {
+			DEBUG_TRACE("%px: defunct\n", ci);
+			ecm_db_connection_make_defunct(ci);
+		}
+
+		cin = ecm_db_connection_get_and_ref_next(ci);
+		ecm_db_connection_deref(ci);
+		ci = cin;
+	}
+	DEBUG_INFO("Defuncting complete for IPv%d connections\n", ip_version);
+}
+
+/*
+ * ecm_db_connection_generate_hash_index()
+ * 	Calculate the hash index.
+ *
+ * Note: The hash we produce is symmetric - i.e. we can swap the "from" and "to"
+ * details without generating a different hash index!
+ */
+static inline ecm_db_connection_hash_t ecm_db_connection_generate_hash_index(ip_addr_t host1_addr, uint32_t host1_port, ip_addr_t host2_addr, uint32_t host2_port, int protocol)
+{
+	uint32_t hah1;
+	uint32_t hah2;
+	uint32_t ht1;
+	uint32_t hash_val;
+
+	/*
+	 * The hash function only uses both host 1 address/port, host 2 address/port
+	 * and protocol fields.
+	 */
+	ECM_IP_ADDR_HASH(hah1, host1_addr);
+	ECM_IP_ADDR_HASH(hah2, host2_addr);
+	ht1 = (u32)hah1 + host1_port + hah2 + host2_port + (uint32_t)protocol;
+	hash_val = (uint32_t)jhash_1word(ht1, ecm_db_jhash_rnd);
+	return (ecm_db_connection_hash_t)(hash_val & (ECM_DB_CONNECTION_HASH_SLOTS - 1));
+}
+
+/*
+ * ecm_db_connection_generate_serial_hash_index()
+ * 	Calculate the serial hash index.
+ */
+static inline ecm_db_connection_serial_hash_t ecm_db_connection_generate_serial_hash_index(uint32_t serial)
+{
+	uint32_t hash_val;
+	hash_val = (uint32_t)jhash_1word(serial, ecm_db_jhash_rnd);
+
+	return (ecm_db_connection_serial_hash_t)(hash_val & (ECM_DB_CONNECTION_SERIAL_HASH_SLOTS - 1));
+}
+
+/*
+ * ecm_db_connection_find_and_ref_chain()
+ *	Given a hash chain index locate the connection
+ */
+static struct ecm_db_connection_instance *ecm_db_connection_find_and_ref_chain(ecm_db_connection_hash_t hash_index,
+											ip_addr_t host1_addr, ip_addr_t host2_addr,
+											int protocol, int host1_port, int host2_port)
+{
+	struct ecm_db_connection_instance *ci;
+
+	/*
+	 * Iterate the chain looking for a connection with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ci = ecm_db_connection_table[hash_index];
+	while (ci) {
+		/*
+		 * The use of unlikely() is liberally used because under fast-hit scenarios the connection would always be at the start of a chain
+		 */
+		if (unlikely(ci->protocol != protocol)) {
+			goto try_next;
+		}
+
+		if (unlikely(!ECM_IP_ADDR_MATCH(host1_addr, ci->mapping[ECM_DB_OBJ_DIR_FROM]->host->address))) {
+			goto try_reverse;
+		}
+
+		if (unlikely(host1_port != ci->mapping[ECM_DB_OBJ_DIR_FROM]->port)) {
+			goto try_reverse;
+		}
+
+		if (unlikely(!ECM_IP_ADDR_MATCH(host2_addr, ci->mapping[ECM_DB_OBJ_DIR_TO]->host->address))) {
+			goto try_reverse;
+		}
+
+		if (unlikely(host2_port != ci->mapping[ECM_DB_OBJ_DIR_TO]->port)) {
+			goto try_reverse;
+		}
+
+		goto connection_found;
+
+try_reverse:
+		if (unlikely(!ECM_IP_ADDR_MATCH(host1_addr, ci->mapping[ECM_DB_OBJ_DIR_TO]->host->address))) {
+			goto try_next;
+		}
+
+		if (unlikely(host1_port != ci->mapping[ECM_DB_OBJ_DIR_TO]->port)) {
+			goto try_next;
+		}
+
+		if (unlikely(!ECM_IP_ADDR_MATCH(host2_addr, ci->mapping[ECM_DB_OBJ_DIR_FROM]->host->address))) {
+			goto try_next;
+		}
+
+		if (unlikely(host2_port != ci->mapping[ECM_DB_OBJ_DIR_FROM]->port)) {
+			goto try_next;
+		}
+
+		goto connection_found;
+
+try_next:
+		ci = ci->hash_next;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Connection not found in hash chain\n");
+	return NULL;
+
+connection_found:
+	_ecm_db_connection_ref(ci);
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Connection found %px\n", ci);
+	return ci;
+}
+
+/*
+ * ecm_db_connection_find_and_ref()
+ *	Locate a connection instance based on addressing, protocol and optional port information.
+ *
+ * NOTE: For non-port based protocols then ports are expected to be -(protocol).
+ */
+struct ecm_db_connection_instance *ecm_db_connection_find_and_ref(ip_addr_t host1_addr, ip_addr_t host2_addr, int protocol, int host1_port, int host2_port)
+{
+	ecm_db_connection_hash_t hash_index;
+
+	DEBUG_TRACE("Lookup connection " ECM_IP_ADDR_OCTAL_FMT ":%d <> " ECM_IP_ADDR_OCTAL_FMT ":%d protocol %d\n", ECM_IP_ADDR_TO_OCTAL(host1_addr), host1_port, ECM_IP_ADDR_TO_OCTAL(host2_addr), host2_port, protocol);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_connection_generate_hash_index(host1_addr, host1_port, host2_addr, host2_port, protocol);
+	return ecm_db_connection_find_and_ref_chain(hash_index, host1_addr, host2_addr, protocol, host1_port, host2_port);
+}
+EXPORT_SYMBOL(ecm_db_connection_find_and_ref);
+
+/*
+ * ecm_db_connection_serial_find_and_ref()
+ *	Locate a connection instance based on serial if it still exists
+ */
+struct ecm_db_connection_instance *ecm_db_connection_serial_find_and_ref(uint32_t serial)
+{
+	ecm_db_connection_serial_hash_t serial_hash_index;
+	struct ecm_db_connection_instance *ci;
+
+	DEBUG_TRACE("Lookup connection serial: %u\n", serial);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	serial_hash_index = ecm_db_connection_generate_serial_hash_index(serial);
+
+	/*
+	 * Iterate the chain looking for a connection with matching serial
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ci = ecm_db_connection_serial_table[serial_hash_index];
+	while (ci) {
+		/*
+		 * The use of likely() is used because under fast-hit scenarios the connection would always be at the start of a chain
+		 */
+		if (likely(ci->serial == serial)) {
+			_ecm_db_connection_ref(ci);
+			spin_unlock_bh(&ecm_db_lock);
+			DEBUG_TRACE("Connection found %px\n", ci);
+			return ci;
+		}
+
+		ci = ci->serial_hash_next;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Connection not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_connection_serial_find_and_ref);
+
+/*
+ * ecm_db_connection_node_get_and_ref()
+ *	Return node reference
+ */
+struct ecm_db_node_instance *ecm_db_connection_node_get_and_ref(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir)
+{
+	struct ecm_db_node_instance *ni;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	ni = ci->node[dir];
+	_ecm_db_node_ref(ni);
+	spin_unlock_bh(&ecm_db_lock);
+	return ni;
+}
+EXPORT_SYMBOL(ecm_db_connection_node_get_and_ref);
+
+/*
+ * ecm_db_connection_mapping_get_and_ref_next()
+ *	Return reference to next connection in the mapping chain in the specified direction.
+ */
+struct ecm_db_connection_instance *ecm_db_connection_mapping_get_and_ref_next(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir)
+{
+	struct ecm_db_connection_instance *nci;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	nci = ci->mapping_next[dir];
+	if (nci) {
+		_ecm_db_connection_ref(nci);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	return nci;
+}
+EXPORT_SYMBOL(ecm_db_connection_mapping_get_and_ref_next);
+
+/*
+ * ecm_db_connection_iface_get_and_ref_next()
+ *	Return reference to next connection in iface chain in the specified direction.
+ */
+struct ecm_db_connection_instance *ecm_db_connection_iface_get_and_ref_next(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir)
+{
+	struct ecm_db_connection_instance *nci;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	nci = ci->iface_next[dir];
+	if (nci) {
+		_ecm_db_connection_ref(nci);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	return nci;
+}
+EXPORT_SYMBOL(ecm_db_connection_iface_get_and_ref_next);
+
+/*
+ * ecm_db_connection_mapping_get_and_ref()
+ * 	Return a reference to the mapping of the connection in the specified direction.
+ */
+struct ecm_db_mapping_instance *ecm_db_connection_mapping_get_and_ref(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir)
+{
+	struct ecm_db_mapping_instance *mi;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	mi = ci->mapping[dir];
+	_ecm_db_mapping_ref(mi);
+	spin_unlock_bh(&ecm_db_lock);
+	return mi;
+}
+EXPORT_SYMBOL(ecm_db_connection_mapping_get_and_ref);
+
+/*
+ * ecm_db_connection_classifier_assign()
+ *	Assign a classifier to the connection assigned classifier list.
+ *
+ * This adds the classifier in the ci->assignments list in ascending priority order according to the classifier type.
+ * Only assigned classifiers are in this list, allowing fast retrival of current assignments, avoiding the need to skip over unassigned classifiers.
+ * Because there is only one of each type of classifier the classifier is also recorded in an array, the position in which is its type value.
+ * This allows fast lookup based on type too.
+ * Further, the connection is recorded in the classifier type assignment array too, this permits iterating of all connections that are assigned to a TYPE of classifier.
+ */
+void ecm_db_connection_classifier_assign(struct ecm_db_connection_instance *ci, struct ecm_classifier_instance *new_ca)
+{
+	struct ecm_classifier_instance *ca;
+	struct ecm_classifier_instance *ca_prev;
+	ecm_classifier_type_t new_ca_type;
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+	struct ecm_db_connection_classifier_type_assignment *ta;
+	struct ecm_db_connection_classifier_type_assignment_list *tal;
+#endif
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	/*
+	 * Get the type (which is also used as the priority)
+	 */
+	new_ca_type = new_ca->type_get(new_ca);
+
+	/*
+	 * Connection holds ref to the classifier
+	 */
+	new_ca->ref(new_ca);
+
+	/*
+	 * Find place to insert the classifier
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ca = ci->assignments;
+	ca_prev = NULL;
+	while (ca) {
+		ecm_classifier_type_t ca_type;
+		ca_type = ca->type_get(ca);
+
+		/*
+		 * If new ca is less important that the current assigned classifier insert here
+		 */
+		if (new_ca_type < ca_type) {
+			break;
+		}
+		ca_prev = ca;
+		ca = ca->ca_next;
+	}
+
+	/*
+	 * Insert new_ca before ca and after ca_prev.
+	 */
+	new_ca->ca_prev = ca_prev;
+	if (ca_prev) {
+		ca_prev->ca_next = new_ca;
+	} else {
+		DEBUG_ASSERT(ci->assignments == ca, "%px: Bad assigmnment list, expecting: %px, got: %px\n", ci, ca, ci->assignments);
+		ci->assignments = new_ca;
+	}
+
+	new_ca->ca_next = ca;
+	if (ca) {
+		ca->ca_prev = new_ca;
+	}
+
+	/*
+	 * Insert based on type too
+	 */
+	DEBUG_ASSERT(ci->assignments_by_type[new_ca_type] == NULL, "%px: Only one of each type: %d may be registered, new: %px, existing, %px\n",
+			ci, new_ca_type, new_ca, ci->assignments_by_type[new_ca_type]);
+	ci->assignments_by_type[new_ca_type] = new_ca;
+
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+	/*
+	 * Default classifier will not be added to the classifier type assignment list.
+	 * Only assigned classifiers can be added.
+	 */
+	if (new_ca_type == ECM_CLASSIFIER_TYPE_DEFAULT) {
+		spin_unlock_bh(&ecm_db_lock);
+		return;
+	}
+
+	/*
+	 * Add the connection into the type assignment list too.
+	 */
+	ta = &ci->type_assignment[new_ca_type];
+	if (ta->pending_unassign) {
+		/*
+		 * The connection is pending unassignment / removal from list, but since it has been
+		 * re-assigned to the same type of classifier we can just clear the flag and avoid the removal.
+		 * NOTE: pending_unassign is only ever true if the iteration count is non-zero i.e. iteration is in progress.
+		 */
+		DEBUG_CHECK_MAGIC(ta, ECM_DB_CLASSIFIER_TYPE_ASSIGNMENT_MAGIC, "%px: magic failed, ci: %px", ta, ci);
+		DEBUG_ASSERT(ta->iteration_count != 0, "%px: Bad pending_unassign: type: %d, Iteration count zero\n", ci, new_ca_type);
+		ta->pending_unassign = false;
+		spin_unlock_bh(&ecm_db_lock);
+		return;
+	}
+
+	/*
+	 * iteration_count should be zero as there should not be a duplicate assignment of the same type.
+	 * This is because if iteration_count was non-zero then pending_unassign should have been true.
+	 */
+	DEBUG_ASSERT(ta->iteration_count == 0, "%px: Type: %d, Iteration count not zero: %d\n", ci, new_ca_type, ta->iteration_count);
+
+	/*
+	 * Insert the connection into the classifier type assignment list, at the head
+	 */
+	tal = &ecm_db_connection_classifier_type_assignments[new_ca_type];
+	ta->next = tal->type_assignments_list;
+	ta->prev = NULL;
+
+	/*
+	 * If there is an existing head, it is no longer the head
+	 */
+	if (tal->type_assignments_list) {
+		struct ecm_db_connection_classifier_type_assignment *talh;
+		talh = &tal->type_assignments_list->type_assignment[new_ca_type];
+		talh->prev = ci;
+	}
+
+	/*
+	 * Set new head
+	 */
+	tal->type_assignments_list = ci;
+
+	/*
+	 * Set magic
+	 */
+	DEBUG_SET_MAGIC(ta, ECM_DB_CLASSIFIER_TYPE_ASSIGNMENT_MAGIC);
+
+	/*
+	 * Increment assignment count
+	 */
+	tal->type_assignment_count++;
+	DEBUG_ASSERT(tal->type_assignment_count > 0, "Bad iteration count: %d\n", tal->type_assignment_count);
+#endif
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_connection_classifier_assign);
+
+/*
+ * ecm_db_connection_classifier_assignments_get_and_ref()
+ *	Populate the given array with references to the currently assigned classifiers.
+ *
+ * This function returns the number of assignments starting from [0].
+ * [0] is the lowest priority classifier, [return_val - 1] is the highest priority.
+ * Release each classifier when you are done, for convenience use ecm_db_connection_assignments_release().
+ *
+ * NOTE: The array also contains the default classifier too which of course will always be at [0]
+ *
+ * WARNING: The array MUST be of size ECM_CLASSIFIER_TYPES.
+ */
+int ecm_db_connection_classifier_assignments_get_and_ref(struct ecm_db_connection_instance *ci, struct ecm_classifier_instance *assignments[])
+{
+	int aci_count;
+	struct ecm_classifier_instance *aci;
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	aci_count = 0;
+	spin_lock_bh(&ecm_db_lock);
+	aci = ci->assignments;
+	while (aci) {
+		aci->ref(aci);
+		assignments[aci_count++] = aci;
+		aci = aci->ca_next;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_ASSERT(aci_count >= 1, "%px: Must have at least default classifier!\n", ci);
+	return aci_count;
+}
+EXPORT_SYMBOL(ecm_db_connection_classifier_assignments_get_and_ref);
+
+/*
+ * ecm_db_connection_assignments_release()
+ * 	Release references to classifiers in the assignments array
+ */
+void ecm_db_connection_assignments_release(int assignment_count, struct ecm_classifier_instance *assignments[])
+{
+	int i;
+	for (i = 0; i < assignment_count; ++i) {
+		struct ecm_classifier_instance *aci = assignments[i];
+		if (aci) {
+			aci->deref(aci);
+		}
+	}
+}
+EXPORT_SYMBOL(ecm_db_connection_assignments_release);
+
+/*
+ * ecm_db_connection_assigned_classifier_find_and_ref()
+ *	Return a ref to classifier of the requested type, if found
+ */
+struct ecm_classifier_instance *ecm_db_connection_assigned_classifier_find_and_ref(struct ecm_db_connection_instance *ci, ecm_classifier_type_t type)
+{
+	struct ecm_classifier_instance *ca;
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+	spin_lock_bh(&ecm_db_lock);
+	ca = ci->assignments_by_type[type];
+	if (ca) {
+		ca->ref(ca);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return ca;
+}
+EXPORT_SYMBOL(ecm_db_connection_assigned_classifier_find_and_ref);
+
+/*
+ * ecm_db_connection_classifier_unassign()
+ *	Unassign a classifier
+ *
+ * The default classifier cannot be unassigned.
+ */
+void ecm_db_connection_classifier_unassign(struct ecm_db_connection_instance *ci, struct ecm_classifier_instance *cci)
+{
+	ecm_classifier_type_t ca_type;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	/*
+	 * Get the type
+	 */
+	ca_type = cci->type_get(cci);
+	DEBUG_ASSERT(ca_type != ECM_CLASSIFIER_TYPE_DEFAULT, "%px: Cannot unassign default", ci);
+
+	if (ca_type >= ECM_CLASSIFIER_TYPES) {
+		DEBUG_WARN("%px: ca_type: %d is higher than the max classifier type number: %d\n", ci, ca_type, (ECM_CLASSIFIER_TYPES - 1));
+		return;
+	}
+
+	DEBUG_TRACE("%px: Unassign type: %d, classifier: %px\n", ci, ca_type, cci);
+
+	/*
+	 * NOTE: It is possible that in SMP this classifier has already been unassigned.
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	if (ci->assignments_by_type[ca_type] == NULL) {
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("%px: Classifier type: %d already unassigned\n", ci, ca_type);
+		return;
+	}
+	_ecm_db_connection_classifier_unassign(ci, cci, ca_type);
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_connection_classifier_unassign);
+
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+/*
+ * ecm_db_connection_by_classifier_type_assignment_get_and_ref_first()
+ *	Return a reference to the first connection for which a classifier of the given type is associated with
+ *
+ * WARNING: YOU MUST NOT USE ecm_db_connection_deref() to release the references taken using this API.
+ * YOU MUST use ecm_db_connection_by_classifier_type_assignment_deref(), this ensures type assignment list integrity.
+ */
+struct ecm_db_connection_instance *ecm_db_connection_by_classifier_type_assignment_get_and_ref_first(ecm_classifier_type_t ca_type)
+{
+	struct ecm_db_connection_classifier_type_assignment_list *tal;
+	struct ecm_db_connection_instance *ci;
+
+	DEBUG_ASSERT(ca_type < ECM_CLASSIFIER_TYPES, "Bad type: %d\n", ca_type);
+
+	DEBUG_TRACE("Get and ref first connection assigned with classifier type: %d\n", ca_type);
+
+	tal = &ecm_db_connection_classifier_type_assignments[ca_type];
+	spin_lock_bh(&ecm_db_lock);
+	ci = tal->type_assignments_list;
+	while (ci) {
+		struct ecm_db_connection_classifier_type_assignment *ta;
+		ta = &ci->type_assignment[ca_type];
+		DEBUG_CHECK_MAGIC(ta, ECM_DB_CLASSIFIER_TYPE_ASSIGNMENT_MAGIC, "%px: magic failed, ci: %px", ta, ci);
+
+		if (ta->pending_unassign) {
+			DEBUG_TRACE("Skip %px, pending unassign for type: %d\n", ci, ca_type);
+			ci = ta->next;
+			continue;
+		}
+
+		/*
+		 * Take reference to this connection.
+		 * NOTE: Hold both the connection and the assignment entry so that when we unlock both the connection
+		 * and the type assignment list entry maintains integrity.
+		 */
+		_ecm_db_connection_ref(ci);
+		ta->iteration_count++;
+		DEBUG_ASSERT(ta->iteration_count > 0, "Bad Iteration count: %d for type: %d, connection: %px\n", ta->iteration_count, ca_type, ci);
+		spin_unlock_bh(&ecm_db_lock);
+		return ci;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_connection_by_classifier_type_assignment_get_and_ref_first);
+
+/*
+ * ecm_db_connection_by_classifier_type_assignment_get_and_ref_next()
+ *	Return a reference to the next connection for which a classifier of the given type is associated with.
+ *
+ * WARNING: YOU MUST NOT USE ecm_db_connection_deref() to release the references taken using this API.
+ * YOU MUST use ecm_db_connection_by_classifier_type_assignment_deref(), this ensures type assignment list integrity.
+ */
+struct ecm_db_connection_instance *ecm_db_connection_by_classifier_type_assignment_get_and_ref_next(struct ecm_db_connection_instance *ci, ecm_classifier_type_t ca_type)
+{
+	struct ecm_db_connection_classifier_type_assignment *ta;
+	struct ecm_db_connection_instance *cin;
+
+	DEBUG_ASSERT(ca_type < ECM_CLASSIFIER_TYPES, "Bad type: %d\n", ca_type);
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	DEBUG_TRACE("Get and ref next connection assigned with classifier type: %d and ci: %px\n", ca_type, ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	ta = &ci->type_assignment[ca_type];
+	cin = ta->next;
+	while (cin) {
+		struct ecm_db_connection_classifier_type_assignment *tan;
+
+		tan = &cin->type_assignment[ca_type];
+		DEBUG_CHECK_MAGIC(tan, ECM_DB_CLASSIFIER_TYPE_ASSIGNMENT_MAGIC, "%px: magic failed, ci: %px", tan, cin);
+
+		if (tan->pending_unassign) {
+			DEBUG_TRACE("Skip %px, pending unassign for type: %d\n", cin, ca_type);
+			cin = tan->next;
+			continue;
+		}
+
+		/*
+		 * Take reference to this connection.
+		 * NOTE: Hold both the connection and the assignment entry so that when we unlock both the connection
+		 * and the type assignment list entry maintains integrity.
+		 */
+		_ecm_db_connection_ref(cin);
+		tan->iteration_count++;
+		DEBUG_ASSERT(tan->iteration_count > 0, "Bad Iteration count: %d for type: %d, connection: %px\n", tan->iteration_count, ca_type, cin);
+		spin_unlock_bh(&ecm_db_lock);
+		return cin;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_connection_by_classifier_type_assignment_get_and_ref_next);
+
+/*
+ * ecm_db_connection_by_classifier_type_assignment_deref()
+ *	Release a reference to a connection while iterating a classifier type assignment list
+ */
+void ecm_db_connection_by_classifier_type_assignment_deref(struct ecm_db_connection_instance *ci, ecm_classifier_type_t ca_type)
+{
+	struct ecm_db_connection_classifier_type_assignment_list *tal;
+	struct ecm_db_connection_classifier_type_assignment *ta;
+
+	DEBUG_ASSERT(ca_type < ECM_CLASSIFIER_TYPES, "Bad type: %d\n", ca_type);
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	tal = &ecm_db_connection_classifier_type_assignments[ca_type];
+
+	/*
+	 * Drop the iteration count
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ta = &ci->type_assignment[ca_type];
+	DEBUG_CHECK_MAGIC(ta, ECM_DB_CLASSIFIER_TYPE_ASSIGNMENT_MAGIC, "%px: magic failed, ci: %px", ta, ci);
+	ta->iteration_count--;
+	DEBUG_ASSERT(ta->iteration_count >= 0, "Bad Iteration count: %d for type: %d, connection: %px\n", ta->iteration_count, ca_type, ci);
+
+	/*
+	 * If there are no more iterations on-going and this is pending unassign then we can remove it from the assignments list
+	 */
+	if (ta->pending_unassign && (ta->iteration_count == 0)) {
+		DEBUG_INFO("%px: Remove type assignment: %d\n", ci, ca_type);
+		_ecm_db_classifier_type_assignment_remove(ci, ca_type);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	ecm_db_connection_deref(ci);
+}
+EXPORT_SYMBOL(ecm_db_connection_by_classifier_type_assignment_deref);
+
+/*
+ * ecm_db_connection_make_defunct_by_assignment_type()
+ *	Make defunct all connections that are currently assigned to a classifier of the given type
+ */
+void ecm_db_connection_make_defunct_by_assignment_type(ecm_classifier_type_t ca_type)
+{
+	struct ecm_db_connection_instance *ci;
+
+	DEBUG_INFO("Make defunct all assigned to type: %d\n", ca_type);
+
+	ci = ecm_db_connection_by_classifier_type_assignment_get_and_ref_first(ca_type);
+	while (ci) {
+		struct ecm_db_connection_instance *cin;
+
+		DEBUG_TRACE("%px: Make defunct: %d\n", ci, ca_type);
+		ecm_db_connection_make_defunct(ci);
+
+		cin = ecm_db_connection_by_classifier_type_assignment_get_and_ref_next(ci, ca_type);
+		ecm_db_connection_by_classifier_type_assignment_deref(ci, ca_type);
+		ci = cin;
+	}
+}
+EXPORT_SYMBOL(ecm_db_connection_make_defunct_by_assignment_type);
+
+/*
+ * ecm_db_connection_regenerate_by_assignment_type()
+ *	Cause regeneration all connections that are currently assigned to a classifier of the given type
+ */
+void ecm_db_connection_regenerate_by_assignment_type(ecm_classifier_type_t ca_type)
+{
+	struct ecm_db_connection_instance *ci;
+
+	DEBUG_INFO("Regenerate all assigned to type: %d\n", ca_type);
+
+	ci = ecm_db_connection_by_classifier_type_assignment_get_and_ref_first(ca_type);
+	while (ci) {
+		struct ecm_db_connection_instance *cin;
+
+		DEBUG_TRACE("%px: Re-generate: %d\n", ci, ca_type);
+		ecm_db_connection_regenerate(ci);
+
+		cin = ecm_db_connection_by_classifier_type_assignment_get_and_ref_next(ci, ca_type);
+		ecm_db_connection_by_classifier_type_assignment_deref(ci, ca_type);
+		ci = cin;
+	}
+}
+EXPORT_SYMBOL(ecm_db_connection_regenerate_by_assignment_type);
+#endif
+
+/*
+ * ecm_db_connection_interfaces_get_and_ref()
+ *	Return the interface heirarchy in the specified direction which this connection is established.
+ *
+ * 'interfaces' MUST be an array as large as ECM_DB_IFACE_HEIRARCHY_MAX.
+ * Returns either ECM_DB_IFACE_HEIRARCHY_MAX if there are no interfaces / error.
+ * Returns the index into the interfaces[] of the first interface (so "for (i = <ret val>, i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i)" works)
+ *
+ * Each interface is referenced on return, be sure to release them individually or use ecm_db_connection_interfaces_deref() instead.
+ */
+int32_t ecm_db_connection_interfaces_get_and_ref(struct ecm_db_connection_instance *ci,
+						 struct ecm_db_iface_instance *interfaces[],
+						 ecm_db_obj_dir_t dir)
+{
+	int32_t n;
+	int32_t i;
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	n = ci->interface_first[dir];
+	for (i = n; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+		interfaces[i] = ci->interfaces[dir][i];
+		_ecm_db_iface_ref(interfaces[i]);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return n;
+}
+EXPORT_SYMBOL(ecm_db_connection_interfaces_get_and_ref);
+
+/*
+ * ecm_db_connection_interfaces_deref()
+ *	Release all interfaces in the given interfaces heirarchy array.
+ *
+ * 'first' is the number returned by one of the ecm_db_connection_xx_interfaces_get_and_ref().
+ * You should NOT have released any references to any of the interfaces in the array youself, this releases them all.
+ */
+void ecm_db_connection_interfaces_deref(struct ecm_db_iface_instance *interfaces[], int32_t first)
+{
+	int32_t i;
+	DEBUG_ASSERT((first >= 0) && (first <= ECM_DB_IFACE_HEIRARCHY_MAX), "Bad first: %d\n", first);
+
+	for (i = first; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+		ecm_db_iface_deref(interfaces[i]);
+	}
+}
+EXPORT_SYMBOL(ecm_db_connection_interfaces_deref);
+
+/*
+ * ecm_db_connection_interfaces_reset()
+ *	Reset the interfaces heirarchy in the specified direction with a new set of interfaces
+ *
+ * NOTE: This will mark the list as set even if you specify no list as a replacement.
+ * This is deliberate - it's stating that there is no list :-)
+ */
+void ecm_db_connection_interfaces_reset(struct ecm_db_connection_instance *ci,
+					struct ecm_db_iface_instance *interfaces[],
+					int32_t new_first, ecm_db_obj_dir_t dir)
+{
+	struct ecm_db_iface_instance *old[ECM_DB_IFACE_HEIRARCHY_MAX];
+	int32_t old_first;
+	int32_t i;
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	/*
+	 * Iterate the from interface list, removing the old and adding in the new
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	for (i = 0; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+		/*
+		 * Put any previous interface into the old list
+		 */
+		old[i] = ci->interfaces[dir][i];
+		ci->interfaces[dir][i] = NULL;
+		if (i < new_first) {
+			continue;
+		}
+		ci->interfaces[dir][i] = interfaces[i];
+		_ecm_db_iface_ref(ci->interfaces[dir][i]);
+	}
+
+	/*
+	 * Get old first and update to new first
+	 */
+	old_first = ci->interface_first[dir];
+	ci->interface_first[dir] = new_first;
+	ci->interface_set[dir] = true;
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Release old
+	 */
+	ecm_db_connection_interfaces_deref(old, old_first);
+}
+EXPORT_SYMBOL(ecm_db_connection_interfaces_reset);
+
+/*
+ * ecm_db_connection_interfaces_get_count()
+ *	Return the number of interfaces in the list
+ */
+int32_t ecm_db_connection_interfaces_get_count(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir)
+{
+	int32_t first;
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+	spin_lock_bh(&ecm_db_lock);
+	first = ci->interface_first[dir];
+	spin_unlock_bh(&ecm_db_lock);
+	return ECM_DB_IFACE_HEIRARCHY_MAX - first;
+}
+EXPORT_SYMBOL(ecm_db_connection_interfaces_get_count);
+
+/*
+ * ecm_db_connection_interfaces_set_check()
+ *	Returns true if the interface list has been set - even if set to an empty list!
+ */
+bool ecm_db_connection_interfaces_set_check(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir)
+{
+	bool set;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+	spin_lock_bh(&ecm_db_lock);
+	set = ci->interface_set[dir];
+	spin_unlock_bh(&ecm_db_lock);
+	return set;
+}
+EXPORT_SYMBOL(ecm_db_connection_interfaces_set_check);
+
+/*
+ * ecm_db_connection_interfaces_clear()
+ *	Clear down the interfaces list, marking the list as not set
+ */
+void ecm_db_connection_interfaces_clear(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir)
+{
+	struct ecm_db_iface_instance *discard[ECM_DB_IFACE_HEIRARCHY_MAX];
+	int32_t discard_first;
+	int32_t i;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	for (i = ci->interface_first[dir]; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+		discard[i] = ci->interfaces[dir][i];
+	}
+
+	discard_first = ci->interface_first[dir];
+	ci->interface_set[dir] = false;
+	ci->interface_first[dir] = ECM_DB_IFACE_HEIRARCHY_MAX;
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Release previous
+	 */
+	ecm_db_connection_interfaces_deref(discard, discard_first);
+}
+EXPORT_SYMBOL(ecm_db_connection_interfaces_clear);
+
+/*
+ * ecm_db_connection_add()
+ *	Add the connection into the database.
+ *
+ * NOTE: The parameters are DIRECTIONAL in terms of which mapping established the connection.
+ * NOTE: Dir confirms if this is an egressing or ingressing connection.
+ * This applies to firewalling front ends mostly. If INGRESS then mapping[ECM_DB_OBJ_DIR_FROM] is the WAN side.
+ * If EGRESS then mapping[ECM_DB_OBJ_DIR_TO] is the WAN side.
+ */
+void ecm_db_connection_add(struct ecm_db_connection_instance *ci,
+							struct ecm_db_mapping_instance *mapping[],
+							struct ecm_db_node_instance *node[],
+							int ip_version,
+							int protocol, ecm_db_direction_t ecm_dir,
+							ecm_db_connection_final_callback_t final,
+							ecm_db_connection_defunct_callback_t defunct,
+							ecm_db_timer_group_t tg, bool is_routed,
+							void *arg)
+{
+	ecm_db_connection_hash_t hash_index;
+	ecm_db_connection_serial_hash_t serial_hash_index;
+	struct ecm_db_listener_instance *li;
+	int dir;
+#ifdef ECM_DB_XREF_ENABLE
+	struct ecm_db_iface_instance *iface[ECM_DB_OBJ_DIR_MAX];
+#endif
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		DEBUG_CHECK_MAGIC(mapping[dir], ECM_DB_MAPPING_INSTANCE_MAGIC, "%px: %s mapping magic failed \n", mapping[dir], ecm_db_obj_dir_strings[dir]);
+		DEBUG_CHECK_MAGIC(node[dir], ECM_DB_NODE_INSTANCE_MAGIC, "%px: %s node magic failed\n", node[dir], ecm_db_obj_dir_strings[dir]);
+	}
+	DEBUG_ASSERT((protocol >= 0) && (protocol <= 255), "%px: invalid protocol number %d\n", ci, protocol);
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_ASSERT(!(ci->flags & ECM_DB_CONNECTION_FLAGS_INSERTED), "%px: inserted\n", ci);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record owner arg and callbacks
+	 */
+	ci->final = final;
+	ci->defunct = defunct;
+	ci->arg = arg;
+
+#ifdef ECM_MULTICAST_ENABLE
+	ci->ti = NULL;
+#endif
+
+	/*
+	 * Ensure default classifier has been assigned this is a must to ensure minimum level of classification
+	 */
+	DEBUG_ASSERT(ci->assignments_by_type[ECM_CLASSIFIER_TYPE_DEFAULT], "%px: No default classifier assigned\n", ci);
+
+	/*
+	 * Connection takes references to the mappings and nodes
+	 */
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		ecm_db_mapping_ref(mapping[dir]);
+		ci->mapping[dir] = mapping[dir];
+
+		ecm_db_node_ref(node[dir]);
+		ci->node[dir] = node[dir];
+	}
+
+	/*
+	 * Set the protocol and routed flag
+	 */
+	ci->ip_version = ip_version;
+	ci->protocol = protocol;
+	ci->is_routed = is_routed;
+
+	/*
+	 * Set direction of connection
+	 */
+	ci->direction = ecm_dir;
+
+	/*
+	 * Identify which hash chain this connection will go into
+	 */
+	hash_index = ecm_db_connection_generate_hash_index(mapping[ECM_DB_OBJ_DIR_FROM]->host->address,
+							   mapping[ECM_DB_OBJ_DIR_FROM]->port,
+							   mapping[ECM_DB_OBJ_DIR_TO]->host->address,
+							   mapping[ECM_DB_OBJ_DIR_TO]->port, protocol);
+	ci->hash_index = hash_index;
+
+	/*
+	 * Identify which serial hash chain this connection will go into
+	 */
+	serial_hash_index = ecm_db_connection_generate_serial_hash_index(ci->serial);
+	ci->serial_hash_index = serial_hash_index;
+
+	/*
+	 * Now we need to lock
+	 */
+	spin_lock_bh(&ecm_db_lock);
+
+	/*
+	 * Increment protocol counter stats
+	 */
+	ecm_db_connection_count_by_protocol[protocol]++;
+	DEBUG_ASSERT(ecm_db_connection_count_by_protocol[protocol] > 0, "%px: Invalid protocol count %d\n", ci, ecm_db_connection_count_by_protocol[protocol]);
+
+	/*
+	 * Set time
+	 */
+	ci->time_added = ecm_db_time;
+
+	/*
+	 * Add connection into the global list
+	 */
+	ci->prev = NULL;
+	ci->next = ecm_db_connections;
+	if (ecm_db_connections) {
+		ecm_db_connections->prev = ci;
+	}
+	ecm_db_connections = ci;
+
+	/*
+	 * Add this connection into the connections hash table
+	 */
+	ci->flags |= ECM_DB_CONNECTION_FLAGS_INSERTED;
+
+	/*
+	 * Insert connection into the connections hash table
+	 */
+	ci->hash_next = ecm_db_connection_table[hash_index];
+	if (ecm_db_connection_table[hash_index]) {
+		ecm_db_connection_table[hash_index]->hash_prev = ci;
+	}
+	ecm_db_connection_table[hash_index] = ci;
+	ecm_db_connection_table_lengths[hash_index]++;
+	DEBUG_ASSERT(ecm_db_connection_table_lengths[hash_index] > 0, "%px: invalid table len %d\n", ci, ecm_db_connection_table_lengths[hash_index]);
+
+	/*
+	 * Insert connection into the connections serial hash table
+	 */
+	ci->serial_hash_next = ecm_db_connection_serial_table[serial_hash_index];
+	if (ecm_db_connection_serial_table[serial_hash_index]) {
+		ecm_db_connection_serial_table[serial_hash_index]->serial_hash_prev = ci;
+	}
+	ecm_db_connection_serial_table[serial_hash_index] = ci;
+	ecm_db_connection_serial_table_lengths[serial_hash_index]++;
+	DEBUG_ASSERT(ecm_db_connection_serial_table_lengths[serial_hash_index] > 0, "%px: invalid table len %d\n", ci, ecm_db_connection_serial_table_lengths[serial_hash_index]);
+
+#ifdef ECM_DB_XREF_ENABLE
+	/*
+	 * Add this connection into the nodes.
+	 */
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		ci->node_prev[dir] = NULL;
+		ci->node_next[dir] = node[dir]->connections[dir];
+		if (node[dir]->connections[dir]) {
+			node[dir]->connections[dir]->node_prev[dir] = ci;
+		}
+		node[dir]->connections[dir] = ci;
+		node[dir]->connections_count[dir]++;
+		DEBUG_ASSERT(node[dir]->connections_count[dir] > 0, "%px: invalid count for %s node connections\n", ci, ecm_db_obj_dir_strings[dir]);
+	}
+
+	/*
+	 * Add this connection into the mappings
+	 */
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		ci->mapping_prev[dir] = NULL;
+		ci->mapping_next[dir] = mapping[dir]->connections[dir];
+		if (mapping[dir]->connections[dir]) {
+			mapping[dir]->connections[dir]->mapping_prev[dir] = ci;
+		}
+		mapping[dir]->connections[dir] = ci;
+	}
+
+	/*
+	 * Add this connection into the ifaces list of connections
+	 * NOTE: There is no need to ref the iface because it will exist for as long as this connection exists
+	 * due to the heirarchy of dependencies being kept by the database.
+	 */
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		iface[dir] = node[dir]->iface;
+		ci->iface_prev[dir] = NULL;
+		ci->iface_next[dir] = iface[dir]->connections[dir];
+		if (iface[dir]->connections[dir]) {
+			iface[dir]->connections[dir]->iface_prev[dir] = ci;
+		}
+		iface[dir]->connections[dir] = ci;
+	}
+#endif
+
+	/*
+	 * NOTE: The interface heirarchy lists are deliberately left empty - these are completed
+	 * by the front end if it is appropriate to do so.
+	 */
+
+	/*
+	 * Update the counters in the mapping
+	 */
+	if (protocol == IPPROTO_UDP) {
+		for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+			mapping[dir]->udp_count[dir]++;
+		}
+	} else if (protocol == IPPROTO_TCP) {
+		for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+			mapping[dir]->tcp_count[dir]++;
+		}
+	}
+
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		mapping[dir]->conn_count[dir]++;
+	}
+
+	/*
+	 * Set the generation number to match global
+	 */
+	ci->generation = ecm_db_connection_generation;
+
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Throw add event to the listeners
+	 */
+	DEBUG_TRACE("%px: Throw connection added event\n", ci);
+	li = ecm_db_listeners_get_and_ref_first();
+	while (li) {
+		struct ecm_db_listener_instance *lin;
+		if (li->connection_added) {
+			li->connection_added(li->arg, ci);
+		}
+
+		/*
+		 * Get next listener
+		 */
+		lin = ecm_db_listener_get_and_ref_next(li);
+		ecm_db_listener_deref(li);
+		li = lin;
+	}
+
+	/*
+	 * Set timer group. 'ref' the connection to ensure it persists for the timer.
+	 */
+	ecm_db_connection_ref(ci);
+	ecm_db_timer_group_entry_set(&ci->defunct_timer, tg);
+}
+EXPORT_SYMBOL(ecm_db_connection_add);
+
+/*
+ * ecm_db_connection_heirarchy_state_get()
+ *	Output state for an interface heirarchy list.
+ */
+int ecm_db_connection_heirarchy_state_get(struct ecm_state_file_instance *sfi, struct ecm_db_iface_instance *interfaces[], int32_t first_interface)
+{
+	int result;
+	int count;
+	int i;
+	int j;
+
+	count = ECM_DB_IFACE_HEIRARCHY_MAX - first_interface;
+	if ((result = ecm_state_write(sfi, "interface_count", "%d", count))) {
+		return result;
+	}
+
+	/*
+	 * Iterate the interface heirarchy list and output the information
+	 */
+	for (i = first_interface, j = 0; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i, ++j) {
+		struct ecm_db_iface_instance *ii = interfaces[i];
+		DEBUG_TRACE("Output interface @ %d: %px\n", i, ii);
+
+		if ((result = ecm_state_prefix_index_add(sfi, j))) {
+			return result;
+		}
+		result = ii->state_get(ii, sfi);
+		if (result) {
+			return result;
+		}
+		if ((result = ecm_state_prefix_remove(sfi))) {
+			return result;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * ecm_db_connection_state_get()
+ *	Prepare a connection message
+ */
+int ecm_db_connection_state_get(struct ecm_state_file_instance *sfi, struct ecm_db_connection_instance *ci)
+{
+	int result;
+	long int expires_in;
+	int sport;
+	int sport_nat;
+	char snode_address[ECM_MAC_ADDR_STR_BUFF_SIZE];
+	char snode_address_nat[ECM_MAC_ADDR_STR_BUFF_SIZE];
+	char sip_address[ECM_IP_ADDR_STR_BUFF_SIZE];
+	char sip_address_nat[ECM_IP_ADDR_STR_BUFF_SIZE];
+	char dnode_address[ECM_MAC_ADDR_STR_BUFF_SIZE];
+	char dnode_address_nat[ECM_MAC_ADDR_STR_BUFF_SIZE];
+	int dport;
+	int dport_nat;
+	char dip_address[ECM_IP_ADDR_STR_BUFF_SIZE];
+	char dip_address_nat[ECM_IP_ADDR_STR_BUFF_SIZE];
+	ecm_db_direction_t direction;
+	int ip_version;
+	int protocol;
+	bool is_routed;
+	uint32_t regen_success;
+	uint32_t regen_fail;
+	uint16_t regen_required;
+	uint16_t regen_occurances;
+	bool regen_in_progress;
+	uint16_t generation;
+	uint16_t global_generation;
+	uint32_t time_added;
+	uint32_t serial;
+	uint64_t from_data_total;
+	uint64_t to_data_total;
+	uint64_t from_packet_total;
+	uint64_t to_packet_total;
+	uint64_t from_data_total_dropped;
+	uint64_t to_data_total_dropped;
+	uint64_t from_packet_total_dropped;
+	uint64_t to_packet_total_dropped;
+	struct ecm_db_host_instance *hi;
+	struct ecm_db_node_instance *ni;
+	int aci_index;
+	int aci_count;
+	ip_addr_t __attribute__((unused)) group_ip;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int32_t first_interface;
+	struct ecm_db_iface_instance *interfaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+
+	DEBUG_TRACE("Prep conn msg for %px\n", ci);
+
+	/*
+	 * Identify expiration
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	if (ci->defunct_timer.group == ECM_DB_TIMER_GROUPS_MAX) {
+		expires_in = -1;
+	} else {
+		expires_in = (long int)(ci->defunct_timer.timeout - ecm_db_time);
+		if (expires_in <= 0) {
+			expires_in = 0;
+		}
+	}
+
+	regen_success = ci->regen_success;
+	regen_fail = ci->regen_fail;
+	regen_required = ci->regen_required;
+	regen_occurances = ci->regen_occurances;
+	regen_in_progress = ci->regen_in_progress;
+	generation = ci->generation;
+	global_generation = ecm_db_connection_generation;
+
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Extract information from the connection for inclusion into the message
+	 */
+	sport = ci->mapping[ECM_DB_OBJ_DIR_FROM]->port;
+	sport_nat = ci->mapping[ECM_DB_OBJ_DIR_FROM_NAT]->port;
+	dport = ci->mapping[ECM_DB_OBJ_DIR_TO]->port;
+	dport_nat = ci->mapping[ECM_DB_OBJ_DIR_TO_NAT]->port;
+
+	hi = ci->mapping[ECM_DB_OBJ_DIR_TO]->host;
+	ecm_ip_addr_to_string(dip_address, hi->address);
+	ni = ci->node[ECM_DB_OBJ_DIR_TO];
+	snprintf(dnode_address, sizeof(dnode_address), "%pM", ni->address);
+	hi = ci->mapping[ECM_DB_OBJ_DIR_TO_NAT]->host;
+	ecm_ip_addr_to_string(dip_address_nat, hi->address);
+
+	hi = ci->mapping[ECM_DB_OBJ_DIR_FROM]->host;
+	ecm_ip_addr_to_string(sip_address, hi->address);
+	ni = ci->node[ECM_DB_OBJ_DIR_FROM];
+	snprintf(snode_address, sizeof(snode_address), "%pM", ni->address);
+	hi = ci->mapping[ECM_DB_OBJ_DIR_FROM_NAT]->host;
+	ecm_ip_addr_to_string(sip_address_nat, hi->address);
+
+	ni = ci->node[ECM_DB_OBJ_DIR_TO_NAT];
+	snprintf(dnode_address_nat, sizeof(dnode_address_nat), "%pM", ni->address);
+
+	ni = ci->node[ECM_DB_OBJ_DIR_FROM_NAT];
+	snprintf(snode_address_nat, sizeof(snode_address_nat), "%pM", ni->address);
+
+	direction = ci->direction;
+	ip_version = ci->ip_version;
+	protocol = ci->protocol;
+	is_routed = ci->is_routed;
+	time_added = ci->time_added;
+	serial = ci->serial;
+	ecm_db_connection_data_stats_get(ci, &from_data_total, &to_data_total,
+			&from_packet_total, &to_packet_total,
+			&from_data_total_dropped, &to_data_total_dropped,
+			&from_packet_total_dropped, &to_packet_total_dropped);
+
+	if ((result = ecm_state_prefix_add(sfi, "conn"))) {
+		return result;
+	}
+	if ((result = ecm_state_prefix_index_add(sfi, serial))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "serial", "%u", serial))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "sip_address", "%s", sip_address))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "sip_address_nat", "%s", sip_address_nat))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "sport", "%d", sport))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "sport_nat", "%d", sport_nat))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "snode_address", "%s", snode_address))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "snode_address_nat", "%s", snode_address_nat))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "dip_address", "%s", dip_address))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "dip_address_nat", "%s", dip_address_nat))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "dport", "%d", dport))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "dport_nat", "%d", dport_nat))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "dnode_address", "%s", dnode_address))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "dnode_address_nat", "%s", dnode_address_nat))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "ip_version", "%d", ip_version))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "protocol", "%d", protocol))) {
+		return result;
+	}
+
+	if (ecm_db_connection_is_pppoe_bridged_get(ci)) {
+		/*
+		 * PPPoE session ID is set in sport and dport.
+		 */
+		if ((result = ecm_state_write(sfi, "pppoe_session_id", "%u", sport))) {
+			return result;
+		}
+	}
+
+	if ((result = ecm_state_write(sfi, "is_routed", "%d", is_routed))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "expires", "%ld", expires_in))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "direction", "%d", direction))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "time_added", "%u", time_added))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "regen_success", "%u", regen_success))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "regen_fail", "%u", regen_fail))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "regen_required", "%u", regen_required))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "regen_occurances", "%u", regen_occurances))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "regen_in_progress", "%u", regen_in_progress))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "generation", "%u/%u", generation, global_generation))) {
+		return result;
+	}
+
+	/*
+	 * NOTE: These advanced stats are not conditional compiled.
+	 * Connections always contain these stats
+	 */
+	if ((result = ecm_db_adv_stats_state_write(sfi, from_data_total, to_data_total,
+			from_packet_total, to_packet_total, from_data_total_dropped,
+			to_data_total_dropped, from_packet_total_dropped,
+			to_packet_total_dropped))) {
+		return result;
+	}
+
+	if ((result = ecm_state_prefix_add(sfi, "from_interfaces"))) {
+		return result;
+	}
+	first_interface = ecm_db_connection_interfaces_get_and_ref(ci, interfaces, ECM_DB_OBJ_DIR_FROM);
+	result = ecm_db_connection_heirarchy_state_get(sfi, interfaces, first_interface);
+	ecm_db_connection_interfaces_deref(interfaces, first_interface);
+	if (result) {
+		return result;
+	}
+	if ((result = ecm_state_prefix_remove(sfi))) {
+		return result;
+	}
+
+#ifdef ECM_MULTICAST_ENABLE
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, group_ip);
+	if (ecm_ip_addr_is_multicast(group_ip)) {
+		if ((result = ecm_state_prefix_add(sfi, "to_mc_interfaces"))) {
+			return result;
+		}
+
+		if ((result = ecm_db_multicast_to_interfaces_xml_state_get(ci, sfi))) {
+			return result;
+		}
+
+		if ((result = ecm_state_prefix_remove(sfi))) {
+			return result;
+		}
+	}
+	else {
+		if ((result = ecm_state_prefix_add(sfi, "to_interfaces"))) {
+			return result;
+		}
+
+		first_interface = ecm_db_connection_interfaces_get_and_ref(ci, interfaces, ECM_DB_OBJ_DIR_TO);
+		result = ecm_db_connection_heirarchy_state_get(sfi, interfaces, first_interface);
+		ecm_db_connection_interfaces_deref(interfaces, first_interface);
+		if (result) {
+			return result;
+		}
+
+		if ((result = ecm_state_prefix_remove(sfi))) {
+			return result;
+		}
+	}
+#else
+	if ((result = ecm_state_prefix_add(sfi, "to_interfaces"))) {
+		return result;
+	}
+	first_interface = ecm_db_connection_interfaces_get_and_ref(ci, interfaces, ECM_DB_OBJ_DIR_TO);
+	result = ecm_db_connection_heirarchy_state_get(sfi, interfaces, first_interface);
+	ecm_db_connection_interfaces_deref(interfaces, first_interface);
+	if (result) {
+		return result;
+	}
+	if ((result = ecm_state_prefix_remove(sfi))) {
+		return result;
+	}
+#endif
+
+	if ((result = ecm_state_prefix_add(sfi, "from_nat_interfaces"))) {
+		return result;
+	}
+	first_interface = ecm_db_connection_interfaces_get_and_ref(ci, interfaces, ECM_DB_OBJ_DIR_FROM_NAT);
+	result = ecm_db_connection_heirarchy_state_get(sfi, interfaces, first_interface);
+	ecm_db_connection_interfaces_deref(interfaces, first_interface);
+	if (result) {
+		return result;
+	}
+	if ((result = ecm_state_prefix_remove(sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_prefix_add(sfi, "to_nat_interfaces"))) {
+		return result;
+	}
+	first_interface = ecm_db_connection_interfaces_get_and_ref(ci, interfaces, ECM_DB_OBJ_DIR_TO_NAT);
+	result = ecm_db_connection_heirarchy_state_get(sfi, interfaces, first_interface);
+	ecm_db_connection_interfaces_deref(interfaces, first_interface);
+	if (result) {
+		return result;
+	}
+	if ((result = ecm_state_prefix_remove(sfi))) {
+		return result;
+	}
+
+	/*
+	 * Output front end state
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	result = feci->state_get(feci, sfi);
+	feci->deref(feci);
+	if (result) {
+		return result;
+	}
+
+	if ((result = ecm_state_prefix_add(sfi, "classifiers"))) {
+		return result;
+	}
+
+	/*
+	 * Grab references to the assigned classifiers so we can produce state for them
+	 */
+	aci_count = ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+
+	/*
+	 * Iterate the assigned classifiers and provide a state record for each
+	 */
+	for (aci_index = 0; aci_index < aci_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+
+		aci = assignments[aci_index];
+		result = aci->state_get(aci, sfi);
+		if (result) {
+			ecm_db_connection_assignments_release(aci_count, assignments);
+			return result;
+		}
+	}
+
+	ecm_db_connection_assignments_release(aci_count, assignments);
+
+	if ((result = ecm_state_prefix_remove(sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_prefix_remove(sfi))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+EXPORT_SYMBOL(ecm_db_connection_state_get);
+
+/*
+ * ecmECM_DB_CONNECTION_HASH_SLOTS_lengths_get()
+ *	Return hash table length
+ */
+int ecm_db_connection_hash_table_lengths_get(int index)
+{
+	int length;
+
+	DEBUG_ASSERT((index >= 0) && (index < ECM_DB_CONNECTION_HASH_SLOTS), "Bad protocol: %d\n", index);
+	spin_lock_bh(&ecm_db_lock);
+	length = ecm_db_connection_table_lengths[index];
+	spin_unlock_bh(&ecm_db_lock);
+	return length;
+}
+EXPORT_SYMBOL(ecm_db_connection_hash_table_lengths_get);
+
+/*
+ * ecm_db_connection_hash_index_get_next()
+ * Given a hash index, return the next one OR return -1 for no more hash indicies to return.
+ */
+int ecm_db_connection_hash_index_get_next(int index)
+{
+	index++;
+	if (index >= ECM_DB_CONNECTION_SERIAL_HASH_SLOTS) {
+		return -1;
+	}
+	return index;
+}
+EXPORT_SYMBOL(ecm_db_connection_hash_index_get_next);
+
+/*
+ * ecm_db_connection_hash_index_get_first()
+ * Return first hash index
+ */
+int ecm_db_connection_hash_index_get_first(void)
+{
+	return 0;
+}
+EXPORT_SYMBOL(ecm_db_connection_hash_index_get_first);
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_db_protocol_get_next()
+ * Given a number, return the next one OR return -1 for no more protocol numbers to return.
+ */
+int ecm_db_protocol_get_next(int protocol)
+{
+	protocol++;
+	if (protocol >= ECM_DB_PROTOCOL_COUNT) {
+		return -1;
+	}
+	return protocol;
+}
+EXPORT_SYMBOL(ecm_db_protocol_get_next);
+
+/*
+ * ecm_db_protocol_get_first()
+ * Return first protocol number
+ */
+int ecm_db_protocol_get_first(void)
+{
+	return 0;
+}
+EXPORT_SYMBOL(ecm_db_protocol_get_first);
+#endif
+
+/*
+ * ecm_db_connection_alloc()
+ *	Allocate a connection instance
+ */
+struct ecm_db_connection_instance *ecm_db_connection_alloc(void)
+{
+	struct ecm_db_connection_instance *ci;
+	int __attribute__((unused)) i;
+	unsigned int conn_count;
+
+	/*
+	 * If we have exceeded the conntrack connection limit then do not allocate new instance.
+	 */
+	conn_count = (unsigned int)ecm_db_connection_count_get();
+	if (conn_count >= nf_conntrack_max) {
+		DEBUG_WARN("ECM Connection count limit reached: db: %u, ct: %u\n", conn_count, nf_conntrack_max);
+		return NULL;
+	}
+
+	/*
+	 * Allocate the connection
+	 */
+	ci = (struct ecm_db_connection_instance *)kzalloc(sizeof(struct ecm_db_connection_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!ci) {
+		DEBUG_WARN("Connection alloc failed\n");
+		return NULL;
+	}
+
+	/*
+	 * Initialise the defunct timer entry
+	 */
+	ecm_db_timer_group_entry_init(&ci->defunct_timer, ecm_db_connection_defunct_callback, ci);
+
+	/*
+	 * Refs is 1 for the creator of the connection
+	 */
+	ci->refs = 1;
+	DEBUG_SET_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC);
+
+	/*
+	 * Initialise the interfaces from/to lists.
+	 * Interfaces are added from end of array.
+	 */
+	ci->interface_first[ECM_DB_OBJ_DIR_FROM] = ECM_DB_IFACE_HEIRARCHY_MAX;
+	ci->interface_first[ECM_DB_OBJ_DIR_TO] = ECM_DB_IFACE_HEIRARCHY_MAX;
+	ci->interface_first[ECM_DB_OBJ_DIR_FROM_NAT] = ECM_DB_IFACE_HEIRARCHY_MAX;
+	ci->interface_first[ECM_DB_OBJ_DIR_TO_NAT] = ECM_DB_IFACE_HEIRARCHY_MAX;
+
+#ifdef ECM_MULTICAST_ENABLE
+	for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; ++i) {
+		ci->to_mcast_interface_first[i] = ECM_DB_IFACE_HEIRARCHY_MAX;
+	}
+#endif
+	/*
+	 * If the master thread is terminating then we cannot create new instances
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	if (ecm_db_terminate_pending) {
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_WARN("Thread terminating\n");
+		kfree(ci);
+		return NULL;
+	}
+
+	/*
+	 * Assign runtime unique serial
+	 */
+	ci->serial = ecm_db_connection_serial++;
+
+	ecm_db_connection_count++;
+	DEBUG_ASSERT(ecm_db_connection_count > 0, "%px: connection count wrap\n", ci);
+	spin_unlock_bh(&ecm_db_lock);
+
+	DEBUG_TRACE("Connection created %px\n", ci);
+	return ci;
+}
+EXPORT_SYMBOL(ecm_db_connection_alloc);
+
+/*
+ * ecm_db_connection_ipv6_from_ct_get_and_ref()
+ *	Return, if any, a connection given a ct
+ */
+struct ecm_db_connection_instance *ecm_db_connection_ipv6_from_ct_get_and_ref(struct nf_conn *ct)
+{
+	struct nf_conntrack_tuple orig_tuple;
+	struct nf_conntrack_tuple reply_tuple;
+	ip_addr_t host1_addr;
+	ip_addr_t host2_addr;
+	int host1_port;
+	int host2_port;
+	int protocol;
+
+	/*
+	 * Look up the associated connection for this conntrack connection
+	 */
+	orig_tuple = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple;
+	reply_tuple = ct->tuplehash[IP_CT_DIR_REPLY].tuple;
+	ECM_NIN6_ADDR_TO_IP_ADDR(host1_addr, orig_tuple.src.u3.in6);
+	ECM_NIN6_ADDR_TO_IP_ADDR(host2_addr, reply_tuple.src.u3.in6);
+	protocol = orig_tuple.dst.protonum;
+	switch (protocol) {
+	case IPPROTO_TCP:
+		host1_port = ntohs(orig_tuple.src.u.tcp.port);
+		host2_port = ntohs(reply_tuple.src.u.tcp.port);
+		break;
+	case IPPROTO_UDP:
+		host1_port = ntohs(orig_tuple.src.u.udp.port);
+		host2_port = ntohs(reply_tuple.src.u.udp.port);
+		break;
+	case IPPROTO_IPIP:
+	case IPPROTO_GRE:
+		host1_port = 0;
+		host2_port = 0;
+		break;
+	default:
+		host1_port = -protocol;
+		host2_port = -protocol;
+	}
+
+	DEBUG_TRACE("%px: lookup src: " ECM_IP_ADDR_OCTAL_FMT ":%d, "
+		    "dest: " ECM_IP_ADDR_OCTAL_FMT ":%d, "
+		    "protocol %d\n",
+		    ct,
+		    ECM_IP_ADDR_TO_OCTAL(host1_addr),
+		    host1_port,
+		    ECM_IP_ADDR_TO_OCTAL(host2_addr),
+		    host2_port,
+		    protocol);
+
+	return ecm_db_connection_find_and_ref(host1_addr,
+					      host2_addr,
+					      protocol,
+					      host1_port,
+					      host2_port);
+}
+
+/*
+ * ecm_db_connection_ipv4_from_ct_get_and_ref()
+ *	Return, if any, a connection given a ct
+ */
+struct ecm_db_connection_instance *ecm_db_connection_ipv4_from_ct_get_and_ref(struct nf_conn *ct)
+{
+	struct nf_conntrack_tuple orig_tuple;
+	struct nf_conntrack_tuple reply_tuple;
+	ip_addr_t host1_addr;
+	ip_addr_t host2_addr;
+	int host1_port;
+	int host2_port;
+	int protocol;
+
+	/*
+	 * Look up the associated connection for this conntrack connection
+	 */
+	orig_tuple = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple;
+	reply_tuple = ct->tuplehash[IP_CT_DIR_REPLY].tuple;
+	ECM_NIN4_ADDR_TO_IP_ADDR(host1_addr, orig_tuple.src.u3.ip);
+	ECM_NIN4_ADDR_TO_IP_ADDR(host2_addr, reply_tuple.src.u3.ip);
+	protocol = orig_tuple.dst.protonum;
+	switch (protocol) {
+	case IPPROTO_TCP:
+		host1_port = ntohs(orig_tuple.src.u.tcp.port);
+		host2_port = ntohs(reply_tuple.src.u.tcp.port);
+		break;
+	case IPPROTO_UDP:
+		host1_port = ntohs(orig_tuple.src.u.udp.port);
+		host2_port = ntohs(reply_tuple.src.u.udp.port);
+		break;
+	case IPPROTO_IPV6:
+	case IPPROTO_ESP:
+	case IPPROTO_GRE:
+		host1_port = 0;
+		host2_port = 0;
+		break;
+	default:
+		host1_port = -protocol;
+		host2_port = -protocol;
+	}
+
+	DEBUG_TRACE("%px: lookup src: " ECM_IP_ADDR_DOT_FMT ":%d, "
+		    "dest: " ECM_IP_ADDR_DOT_FMT ":%d, "
+		    "protocol %d\n",
+		    ct,
+		    ECM_IP_ADDR_TO_DOT(host1_addr),
+		    host1_port,
+		    ECM_IP_ADDR_TO_DOT(host2_addr),
+		    host2_port,
+		    protocol);
+
+	return ecm_db_connection_find_and_ref(host1_addr,
+					      host2_addr,
+					      protocol,
+					      host1_port,
+					      host2_port);
+}
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+/*
+ * ecm_db_connection_from_ovs_flow_get_and_ref()
+ *	Look-up a connection based on OVS flow 5-tuple information.
+ */
+struct ecm_db_connection_instance *ecm_db_connection_from_ovs_flow_get_and_ref(struct ovsmgr_dp_flow *flow)
+{
+	ip_addr_t src_addr;
+	ip_addr_t dst_addr;
+	int src_port;
+	int dst_port;
+	int protocol;
+
+	/*
+	 * Look up the associated connection for this OVS flow
+	 */
+	protocol = flow->tuple.protocol;
+	src_port = ntohs(flow->tuple.src_port);
+	dst_port = ntohs(flow->tuple.dst_port);
+
+	if (flow->tuple.ip_version == 4) {
+		ECM_NIN4_ADDR_TO_IP_ADDR(src_addr, flow->tuple.ipv4.src);
+		ECM_NIN4_ADDR_TO_IP_ADDR(dst_addr, flow->tuple.ipv4.dst);
+		DEBUG_TRACE("%px: OVS IPv4 flow lookup src: " ECM_IP_ADDR_DOT_FMT ":%d, "
+			    "dest: " ECM_IP_ADDR_DOT_FMT ":%d, "
+			    "protocol %d\n",
+			    flow,
+			    ECM_IP_ADDR_TO_DOT(src_addr),
+			    src_port,
+			    ECM_IP_ADDR_TO_DOT(dst_addr),
+			    dst_port,
+			    protocol);
+	} else if (flow->tuple.ip_version == 6) {
+		ECM_NIN6_ADDR_TO_IP_ADDR(src_addr, flow->tuple.ipv6.src);
+		ECM_NIN6_ADDR_TO_IP_ADDR(dst_addr, flow->tuple.ipv6.dst);
+		DEBUG_TRACE("%px: OVS IPv6 flow lookup src: " ECM_IP_ADDR_OCTAL_FMT ":%d, "
+			    "dest: " ECM_IP_ADDR_OCTAL_FMT ":%d, "
+			    "protocol %d\n",
+			    flow,
+			    ECM_IP_ADDR_TO_OCTAL(src_addr),
+			    src_port,
+			    ECM_IP_ADDR_TO_OCTAL(dst_addr),
+			    dst_port,
+			    protocol);
+	} else {
+		DEBUG_WARN("%px: Invalid IP version: %d\n", flow, flow->tuple.ip_version);
+		return NULL;
+	}
+
+	return ecm_db_connection_find_and_ref(src_addr,
+					      dst_addr,
+					      protocol,
+					      src_port,
+					      dst_port);
+}
+#endif
+
+/*
+ * ecm_db_connection_decel_v4()
+ *	Decelerate IPv4 connection.
+ *
+ * Big endian parameters apart from protocol
+ */
+bool ecm_db_connection_decel_v4(__be32 src_ip, int src_port,
+				__be32 dest_ip, int dest_port, int protocol)
+{
+	ip_addr_t ecm_src_ip;
+	ip_addr_t ecm_dest_ip;
+	struct ecm_db_connection_instance *ci;
+
+	/*
+	 * Look up ECM connection from the given tuple
+	 */
+	src_port = ntohs(src_port);
+	dest_port = ntohs(dest_port);
+	ECM_NIN4_ADDR_TO_IP_ADDR(ecm_src_ip, src_ip);
+	ECM_NIN4_ADDR_TO_IP_ADDR(ecm_dest_ip, dest_ip);
+
+	ci = ecm_db_connection_find_and_ref(ecm_src_ip, ecm_dest_ip, protocol, src_port, dest_port);
+	if (!ci) {
+		DEBUG_WARN("Decel v4 Connection lookup failed."
+				" Received connection tuple information: \n"
+				"Protocol: %d\n"
+				"src: " ECM_IP_ADDR_DOT_FMT ":%d\n"
+				"dest: " ECM_IP_ADDR_DOT_FMT ":%d\n",
+				protocol,
+				ECM_IP_ADDR_TO_DOT(ecm_src_ip), src_port,
+				ECM_IP_ADDR_TO_DOT(ecm_dest_ip), dest_port);
+		return false;
+	}
+
+	DEBUG_TRACE("Decel v4, connection tuple information: \n"
+			"Protocol: %d\n"
+			"src: " ECM_IP_ADDR_DOT_FMT ":%d\n"
+			"dest: " ECM_IP_ADDR_DOT_FMT ":%d\n",
+			protocol,
+			ECM_IP_ADDR_TO_DOT(ecm_src_ip), src_port,
+			ECM_IP_ADDR_TO_DOT(ecm_dest_ip), dest_port);
+
+	/*
+	 * Defunct the connection.
+	 */
+	ecm_db_connection_make_defunct(ci);
+	ecm_db_connection_deref(ci);
+	return true;
+}
+
+/*
+ * ecm_db_connection_decel_v6()
+ *	Decelerate IPv6 connection.
+ *
+ * Big endian parameters apart from protocol
+ *
+ * NOTE: If IPv6 is not supported in ECM this function must still exist as a stub to avoid compilation problems for registrants.
+ */
+bool ecm_db_connection_decel_v6(struct in6_addr *src_ip, int src_port,
+				struct in6_addr *dest_ip, int dest_port, int protocol)
+{
+#ifdef ECM_IPV6_ENABLE
+	struct in6_addr in6;
+	ip_addr_t ecm_src_ip;
+	ip_addr_t ecm_dest_ip;
+	struct ecm_db_connection_instance *ci;
+
+	/*
+	 * Look up ECM connection from the given tuple
+	 */
+	src_port = ntohs(src_port);
+	dest_port = ntohs(dest_port);
+	in6 = *src_ip;
+	ECM_NIN6_ADDR_TO_IP_ADDR(ecm_src_ip, in6);
+	in6 = *dest_ip;
+	ECM_NIN6_ADDR_TO_IP_ADDR(ecm_dest_ip, in6);
+
+	ci = ecm_db_connection_find_and_ref(ecm_src_ip, ecm_dest_ip, protocol, src_port, dest_port);
+	if (!ci) {
+		DEBUG_WARN("Decel v6, Connection lookup failed."
+				" Received connection tuple information: \n"
+				"Protocol: %d\n"
+				"src: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+				"dest: " ECM_IP_ADDR_OCTAL_FMT ":%d\n",
+				protocol,
+				ECM_IP_ADDR_TO_OCTAL(ecm_src_ip), src_port,
+				ECM_IP_ADDR_TO_OCTAL(ecm_dest_ip), dest_port);
+		return false;
+	}
+
+
+	DEBUG_TRACE("Decel v6, connection tuple information: \n"
+			"Protocol: %d\n"
+			"src: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"dest: " ECM_IP_ADDR_OCTAL_FMT ":%d\n",
+			protocol,
+			ECM_IP_ADDR_TO_OCTAL(ecm_src_ip), src_port,
+			ECM_IP_ADDR_TO_OCTAL(ecm_dest_ip), dest_port);
+
+	/*
+	 * Defunct the connection.
+	 */
+	ecm_db_connection_make_defunct(ci);
+	ecm_db_connection_deref(ci);
+	return true;
+#endif
+	return false;
+}
+
+/*
+ * ecm_db_front_end_instance_ref_and_set()
+ *	Refs and sets the front end instance of connection.
+ */
+void ecm_db_front_end_instance_ref_and_set(struct ecm_db_connection_instance *ci, struct ecm_front_end_connection_instance *feci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	feci->ref(feci);
+	ci->feci = feci;
+}
+EXPORT_SYMBOL(ecm_db_front_end_instance_ref_and_set);
+
+/*
+ * ecm_db_get_connection_counts_simple()
+ *	Return total of connections for each simple protocol (tcp, udp, other).  Primarily for use by the luci-bwc service.
+ */
+static ssize_t ecm_db_get_connection_counts_simple(struct file *file,
+						char __user *user_buf,
+						size_t sz, loff_t *ppos)
+{
+	int tcp_count;
+	int udp_count;
+	int other_count;
+	int total_count;
+	int ret;
+	char *buf;
+
+	buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!buf) {
+		return -ENOMEM;
+	}
+
+	/*
+	 * Get snapshot of the protocol counts
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	tcp_count = ecm_db_connection_count_by_protocol[IPPROTO_TCP];
+	udp_count = ecm_db_connection_count_by_protocol[IPPROTO_UDP];
+	total_count = ecm_db_connection_count;
+	other_count = total_count - (tcp_count + udp_count);
+	spin_unlock_bh(&ecm_db_lock);
+
+	ret = snprintf(buf, (ssize_t)PAGE_SIZE, "tcp %d udp %d other %d total %d\n", tcp_count, udp_count, other_count, total_count);
+	if (ret < 0) {
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	ret = simple_read_from_buffer(user_buf, sz, ppos, buf, ret);
+	kfree(buf);
+	return ret;
+}
+
+/*
+ * File operations for simple connection counts.
+ */
+static struct file_operations ecm_db_connection_count_simple_fops = {
+	.read = ecm_db_get_connection_counts_simple,
+};
+
+/*
+ * ecm_db_connection_init()
+ */
+bool ecm_db_connection_init(struct dentry *dentry)
+{
+	if (!debugfs_create_u32("connection_count", S_IRUGO, dentry,
+					(u32 *)&ecm_db_connection_count)) {
+		DEBUG_ERROR("Failed to create ecm db connection count file in debugfs\n");
+		return false;
+	}
+
+	if (!debugfs_create_file("connection_count_simple", S_IRUGO, dentry,
+					NULL, &ecm_db_connection_count_simple_fops)) {
+		DEBUG_ERROR("Failed to create ecm db connection count simple file in debugfs\n");
+		return false;
+	}
+
+	ecm_db_connection_table = vzalloc(sizeof(struct ecm_db_connection_instance *) * ECM_DB_CONNECTION_HASH_SLOTS);
+	if (!ecm_db_connection_table) {
+		DEBUG_ERROR("Failed to allocate virtual memory for ecm_db_connection_table\n");
+		return false;
+	}
+
+	ecm_db_connection_table_lengths = vzalloc(sizeof(int) * ECM_DB_CONNECTION_HASH_SLOTS);
+	if (!ecm_db_connection_table_lengths) {
+		DEBUG_ERROR("Failed to allocate virtual memory for ecm_db_connection_table_lengths\n");
+		vfree(ecm_db_connection_table);
+		return false;
+	}
+
+	ecm_db_connection_serial_table = vzalloc(sizeof(struct ecm_db_connection_instance *) * ECM_DB_CONNECTION_SERIAL_HASH_SLOTS);
+	if (!ecm_db_connection_serial_table) {
+		DEBUG_ERROR("Failed to allocate virtual memory for ecm_db_connection_serial_table\n");
+		vfree(ecm_db_connection_table_lengths);
+		vfree(ecm_db_connection_table);
+		return false;
+	}
+
+	ecm_db_connection_serial_table_lengths = vzalloc(sizeof(int) * ECM_DB_CONNECTION_SERIAL_HASH_SLOTS);
+	if (!ecm_db_connection_serial_table_lengths) {
+		DEBUG_ERROR("Failed to allocate virtual memory for ecm_db_connection_serial_table_lengths\n");
+		vfree(ecm_db_connection_serial_table);
+		vfree(ecm_db_connection_table_lengths);
+		vfree(ecm_db_connection_table);
+		return false;
+	}
+
+	/*
+	 * Reset connection by protocol counters
+	 */
+	memset(ecm_db_connection_count_by_protocol, 0, sizeof(ecm_db_connection_count_by_protocol));
+
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+	/*
+	 * Reset classifier type assignment lists
+	 */
+	memset(ecm_db_connection_classifier_type_assignments, 0, sizeof(ecm_db_connection_classifier_type_assignments));
+#endif
+	return true;
+}
+
+/*
+ * ecm_db_connection_exit()
+ */
+void ecm_db_connection_exit(void)
+{
+	vfree(ecm_db_connection_serial_table_lengths);
+	vfree(ecm_db_connection_serial_table);
+	vfree(ecm_db_connection_table_lengths);
+	vfree(ecm_db_connection_table);
+}
diff --git a/qca-nss-ecm/ecm_db/ecm_db_connection.h b/qca-nss-ecm/ecm_db/ecm_db_connection.h
new file mode 100644
index 0000000..50453e6
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_connection.h
@@ -0,0 +1,389 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <net/netfilter/nf_conntrack.h>
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+#include <ovsmgr.h>
+#endif
+
+/*
+ * Magic number
+ */
+#define ECM_DB_CONNECTION_INSTANCE_MAGIC 0xff23
+
+typedef uint32_t ecm_db_connection_hash_t;
+typedef uint32_t ecm_db_connection_serial_hash_t;
+
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+/*
+ * struct ecm_db_connection_classifier_type_assignment
+ *	List linkage
+ */
+struct ecm_db_connection_classifier_type_assignment {
+	struct ecm_db_connection_instance *next;	/* Next connection assigned to a classifier of this type */
+	struct ecm_db_connection_instance *prev;	/* Previous connection assigned to a classifier of this type */
+	int iteration_count;				/* >0 if something is examining this list entry and it may not be unlinked.  The connection will persist. */
+	bool pending_unassign;				/* True when the connection has been unassigned from the type, when iteration_count drops to 0 it may be removed from the list */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+#endif
+
+/*
+ * struct ecm_db_connection_instance
+ */
+struct ecm_db_connection_instance {
+	struct ecm_db_connection_instance *next;		/* Next instance in global list */
+	struct ecm_db_connection_instance *prev;		/* Previous instance in global list */
+
+	struct ecm_db_connection_instance *hash_next;		/* Next connection in chain */
+	struct ecm_db_connection_instance *hash_prev;		/* Previous connection in chain */
+	ecm_db_connection_hash_t hash_index;			/* The hash table slot whose chain of connections this is inserted into */
+
+	struct ecm_db_connection_instance *serial_hash_next;	/* Next connection in serial hash chain */
+	struct ecm_db_connection_instance *serial_hash_prev;	/* Previous connection in serial hash chain */
+	ecm_db_connection_hash_t serial_hash_index;		/* The hash table slot whose chain of connections this is inserted into */
+
+	uint32_t time_added;					/* RO: DB time stamp when the connection was added into the database */
+
+	int ip_version;						/* RO: The version of IP protocol this connection was established for */
+	int protocol;						/* RO: Protocol of the connection */
+	ecm_db_direction_t direction;				/* RO: 'Direction' of connection establishment. */
+	bool is_routed;						/* RO: True when connection is routed, false when not */
+	bool timer_no_touch;					/* RO: Do no update timer when this flag is set */
+	uint16_t l2_encap_proto;				/* L2 encap protocol of the flow of this connection */
+	uint32_t mark;						/* The result value of mark classifier on this connection */
+
+	/*
+	 * Connection endpoint mapping
+	 * NOTE: For non-NAT connections mapping[ECM_DB_OBJ_DIR_FROM_NAT] and mapping[ECM_DB_OBJ_DIR_TO_NAT]
+	 * would be identical to the endpoint mappings.
+	 */
+	struct ecm_db_mapping_instance *mapping[ECM_DB_OBJ_DIR_MAX];	/* The connection was established on this mapping in the specified direction */
+
+	/*
+	 * From / To Node (NAT and non-NAT).
+	 * Connections keep references to the nodes upon which they operate.
+	 * Gut feeling would tell us this is unusual since it should be the case that
+	 * the HOST refer to the node, e.g. IP address to a MAC address.
+	 * However there are some 'interesting' usage models where the same IP address may appear
+	 * from different nodes / MAC addresses because of this the unique element here is the connection
+	 * and so we record the node information directly here.
+	 */
+	struct ecm_db_node_instance *node[ECM_DB_OBJ_DIR_MAX];	/* Node which this connection was established in the specified direction */
+
+#ifdef ECM_DB_XREF_ENABLE
+	/*
+	 * The connection has references to the mappings (both nat and non-nat) as required above.
+	 * Also mappings keep lists of connections made to/from them so that they may be iterated
+	 * to determine associated connections in each direction/situation (e.g. "defuncting all connections made to/from a mapping").
+	 */
+	struct ecm_db_connection_instance *mapping_next[ECM_DB_OBJ_DIR_MAX];	/* Next connection made on the same mapping in the specified direction */
+	struct ecm_db_connection_instance *mapping_prev[ECM_DB_OBJ_DIR_MAX];	/* Previous connection made on the same mapping in the specified direction */
+
+	/*
+	 * Connection endpoint interface
+	 * NOTE: For non-NAT connections from/to would be identical to the endpoint interface.
+	 * GGG TODO Deprecated - use interface lists instead.
+	 * To be removed when interface heirarchies are implemented to provide the same functionality.
+	 */
+	struct ecm_db_connection_instance *iface_next[ECM_DB_OBJ_DIR_MAX];	/* Next connection made on the same interface with the specified direction*/
+	struct ecm_db_connection_instance *iface_prev[ECM_DB_OBJ_DIR_MAX];	/* Previous connection made on the same interface with the specified direction */
+
+	/*
+	 * As well as keeping a reference to the node which this connection uses the nodes
+	 * also keep lists of connections made from/to them.
+	 */
+	struct ecm_db_connection_instance *node_next[ECM_DB_OBJ_DIR_MAX];	/* Next connection in the nodes specified direction list */
+	struct ecm_db_connection_instance *node_prev[ECM_DB_OBJ_DIR_MAX];	/* Prev connection in the nodes specified direction list */
+#endif
+	/*
+	 * From / To interfaces list
+	 * From NAT / To NAT interfaces list
+	 * GGG TODO Not sure if NAT interface lists are necessary or appropriate or practical.
+	 * Needs to be assessed if it gives any clear benefit and possibly remove these if not.
+	 */
+	struct ecm_db_iface_instance *interfaces[ECM_DB_OBJ_DIR_MAX][ECM_DB_IFACE_HEIRARCHY_MAX];
+								/* The outermost to innnermost interface this connection is using in the specified direction
+								 * which is defined in the first dimension of the array.
+								 * Relationships are recorded from [ECM_DB_IFACE_HEIRARCHY_MAX - 1] to [0]
+								 */
+	int32_t interface_first[ECM_DB_OBJ_DIR_MAX];	/* The index of the first interface in the list */
+	bool interface_set[ECM_DB_OBJ_DIR_MAX];		/* True when a list has been set - even if there is NO list, it's still deliberately set that way. */
+
+#ifdef ECM_MULTICAST_ENABLE
+	/*
+	 * Destination Multicast interfaces list
+	 */
+	struct ecm_db_iface_instance *to_mcast_interfaces;
+								/* The outermost to innnermost interfaces this connection is using in multicast path.
+								 * The size of the buffer allocated for the to_mcast_interfaces heirarchies is as large as
+								 * sizeof(struct ecm_db_iface_instance *) * ECM_DB_MULTICAST_IF_MAX * ECM_DB_IFACE_HEIRARCHY_MAX. */
+	int32_t to_mcast_interface_first[ECM_DB_MULTICAST_IF_MAX];
+								/* The indexes of the first interfaces in the destinaiton interface list */
+	struct ecm_db_multicast_tuple_instance *ti; 		/* Multicast Connection instance */
+	bool to_mcast_interfaces_set;				/* Flag to indicate if the destination interface list is currently empty or not */
+#endif
+	/*
+	 * Time values in seconds
+	 */
+	struct ecm_db_timer_group_entry defunct_timer;		/* Used to defunct the connection on inactivity */
+
+	/*
+	 * Byte and packet counts
+	 */
+	uint64_t from_data_total;				/* Totals of data as sent by the 'from' side of this connection */
+	uint64_t to_data_total;					/* Totals of data as sent by the 'to' side of this connection */
+	uint64_t from_packet_total;				/* Totals of packets as sent by the 'from' side of this connection */
+	uint64_t to_packet_total;				/* Totals of packets as sent by the 'to' side of this connection */
+	uint64_t from_data_total_dropped;			/* Total data sent by the 'from' side that we purposely dropped - the 'to' side has not seen this data */
+	uint64_t to_data_total_dropped;				/* Total data sent by the 'to' side that we purposely dropped - the 'from' side has not seen this data */
+	uint64_t from_packet_total_dropped;			/* Total packets sent by the 'from' side that we purposely dropped - the 'to' side has not seen this data */
+	uint64_t to_packet_total_dropped;			/* Total packets sent by the 'to' side that we purposely dropped - the 'from' side has not seen this data */
+
+	/*
+	 * Classifiers attached to this connection
+	 */
+	struct ecm_classifier_instance *assignments;		/* A list of all classifiers that are still assigned to this connection.
+								 * When a connection is created, one instance of every type of classifier is assigned to the connection.
+								 * Classifiers are added in ascending order of priority - so the most important processes a packet last.
+								 * Classifiers may drop out of this list (become unassigned) at any time.
+								 */
+	struct ecm_classifier_instance *assignments_by_type[ECM_CLASSIFIER_TYPES];
+								/* All assignments are also recorded in this array, since there can be only one of each type, this array allows
+								 * rapid retrieval of a classifier type, saving having to iterate the assignments list.
+								 */
+
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+	struct ecm_db_connection_classifier_type_assignment type_assignment[ECM_CLASSIFIER_TYPES];
+								/*
+								 * Each classifier TYPE has a list of connections that are assigned to it.
+								 * This permits a classifier TYPE to rapidly retrieve all connections associated with it.
+								 */
+#endif
+
+	/*
+	 * Re-generation.
+	 * When system or classifier state changes, affected connections may need to have their state re-generated.
+	 * This ensures that a connection does not continue to operate on stale state which could affect the sanity of acceleration rules.
+	 * A connection needs to be re-generated when its regen_required is > 0.
+	 * When a re-generation is completed successfully the counter is decremented.
+	 * The counter ensures that any further changes of state while re-generation is under way is not missed.
+	 * While a connection needs re-generation (regen_required > 0), acceleration should not be permitted.
+	 * It may not always be practical to flag individual connections for re-generation (time consuming with large numbers of connections).
+	 * The "generation" is a numerical counter comparison against the global "ecm_db_connection_generation".
+	 * This ecm_db_connection_generation can be incremented causing a numerical difference between the connections counter and this global.
+	 * This is enough to flag that a re-generation is needed.
+	 * Further, it is possible that re-generation may be required DURING a rule construction.  Since constructing a rule
+	 * can require lengthy non-atomic processes there needs to be a way to ensure that changes during construction of a rule are caught.
+	 * The regen_occurances is a counter that is incremented whenever regen_required is also incremented.
+	 * However it is never decremented.  This permits the caller to obtain this count before a non-atomic procedure and then afterwards.
+	 * If there is any change in the counter value there is a change of generation!  And the operation should be aborted.
+	 */
+	bool regen_in_progress;					/* The connection is under regeneration right now and is used to provide atomic re-generation in SMP */
+	uint16_t regen_required;				/* The connection needs to be re-generated when > 0 */
+	uint16_t regen_occurances;				/* Total number of regens required */
+	uint16_t generation;					/* Used to detect when a re-evaluation of this connection is necessary by comparing with ecm_db_connection_generation */
+	uint32_t regen_success;					/* Tracks how many times re-generation was successfully completed */
+	uint32_t regen_fail;					/* Tracks how many times re-generation failed */
+
+	struct ecm_front_end_connection_instance *feci;		/* Front end instance specific to this connection */
+
+	ecm_db_connection_defunct_callback_t defunct;		/* Callback to be called when connection has become defunct */
+	ecm_db_connection_final_callback_t final;		/* Callback to owner when object is destroyed */
+	void *arg;						/* Argument returned to owner in callbacks */
+
+	uint32_t serial;					/* RO: Serial number for the connection - unique for run lifetime */
+	uint32_t flags;
+	int refs;						/* Integer to trap we never go negative */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+/*
+ * Connection flags
+ */
+#define ECM_DB_CONNECTION_FLAGS_INSERTED 0x1			/* Connection is inserted into connection database tables */
+#define ECM_DB_CONNECTION_FLAGS_PPPOE_BRIDGE 0x2		/* Connection is PPPoE bridge entry */
+
+int _ecm_db_connection_count_get(void);
+
+int ecm_db_connection_count_get(void);
+int ecm_db_connection_count_by_protocol_get(int protocol);
+struct ecm_front_end_connection_instance *ecm_db_connection_front_end_get_and_ref(struct ecm_db_connection_instance *ci);
+
+int ecm_db_connection_elapsed_defunct_timer(struct ecm_db_connection_instance *ci);
+bool ecm_db_connection_defunct_timer_reset(struct ecm_db_connection_instance *ci, ecm_db_timer_group_t tg);
+bool ecm_db_connection_defunct_timer_touch(struct ecm_db_connection_instance *ci);
+void ecm_db_connection_defunct_timer_no_touch_set(struct ecm_db_connection_instance *ci);
+bool ecm_db_connection_defunct_timer_no_touch_get(struct ecm_db_connection_instance *ci);
+ecm_db_timer_group_t ecm_db_connection_timer_group_get(struct ecm_db_connection_instance *ci);
+void ecm_db_connection_defunct_timer_remove_and_set(struct ecm_db_connection_instance *ci, ecm_db_timer_group_t tg);
+void ecm_db_connection_make_defunct(struct ecm_db_connection_instance *ci);
+void ecm_db_connection_data_totals_update(struct ecm_db_connection_instance *ci,
+					  bool is_from, uint64_t size, uint64_t packets);
+void ecm_db_connection_data_totals_update_dropped(struct ecm_db_connection_instance *ci,
+						  bool is_from, uint64_t size, uint64_t packets);
+void ecm_db_connection_data_stats_get(struct ecm_db_connection_instance *ci,
+				      uint64_t *from_data_total, uint64_t *to_data_total,
+				      uint64_t *from_packet_total, uint64_t *to_packet_total,
+				      uint64_t *from_data_total_dropped, uint64_t *to_data_total_dropped,
+				      uint64_t *from_packet_total_dropped, uint64_t *to_packet_total_dropped);
+
+uint32_t ecm_db_connection_serial_get(struct ecm_db_connection_instance *ci);
+
+void ecm_db_connection_address_get(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir, ip_addr_t addr);
+
+int ecm_db_connection_port_get(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir);
+
+void ecm_db_connection_node_address_get(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir, uint8_t *address_buffer);
+
+void ecm_db_connection_iface_name_get(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir, char *name_buffer);
+
+int ecm_db_connection_iface_mtu_get(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir);
+
+ecm_db_iface_type_t ecm_db_connection_iface_type_get(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir);
+
+uint16_t ecm_db_connection_regeneration_occurrances_get(struct ecm_db_connection_instance *ci);
+void ecm_db_connection_regeneration_completed(struct ecm_db_connection_instance *ci);
+void ecm_db_connection_regeneration_failed(struct ecm_db_connection_instance *ci);
+bool ecm_db_connection_regeneration_required_check(struct ecm_db_connection_instance *ci);
+bool ecm_db_connection_regeneration_required_peek(struct ecm_db_connection_instance *ci);
+void ecm_db_connection_regeneration_needed(struct ecm_db_connection_instance *ci);
+void ecm_db_regeneration_needed(void);
+void ecm_db_connection_regenerate(struct ecm_db_connection_instance *ci);
+
+ecm_db_direction_t ecm_db_connection_direction_get(struct ecm_db_connection_instance *ci);
+
+int ecm_db_connection_protocol_get(struct ecm_db_connection_instance *ci);
+int ecm_db_connection_ip_version_get(struct ecm_db_connection_instance *ci);
+bool ecm_db_connection_is_routed_get(struct ecm_db_connection_instance *ci);
+bool ecm_db_connection_is_pppoe_bridged_get(struct ecm_db_connection_instance *ci);
+
+void _ecm_db_connection_ref(struct ecm_db_connection_instance *ci);
+void ecm_db_connection_ref(struct ecm_db_connection_instance *ci);
+int ecm_db_connection_deref(struct ecm_db_connection_instance *ci);
+
+struct ecm_db_connection_instance *ecm_db_connections_get_and_ref_first(void);
+struct ecm_db_connection_instance *ecm_db_connection_get_and_ref_next(struct ecm_db_connection_instance *ci);
+
+void ecm_db_connection_defunct_all(void);
+void ecm_db_connection_defunct_by_port(int port, ecm_db_obj_dir_t dir);
+void ecm_db_connection_defunct_by_protocol(int protocol);
+void ecm_db_connection_defunct_ip_version(int ip_version);
+
+struct ecm_db_connection_instance *ecm_db_connection_serial_find_and_ref(uint32_t serial);
+struct ecm_db_connection_instance *ecm_db_connection_find_and_ref(ip_addr_t host1_addr,
+								  ip_addr_t host2_addr,
+								  int protocol,
+								  int host1_port,
+								  int host2_port);
+
+struct ecm_db_node_instance *ecm_db_connection_node_get_and_ref(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir);
+
+struct ecm_db_mapping_instance *ecm_db_connection_mapping_get_and_ref(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir);
+
+struct ecm_db_connection_instance *ecm_db_connection_iface_get_and_ref_next(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir);
+
+struct ecm_db_connection_instance *ecm_db_connection_mapping_get_and_ref_next(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir);
+
+void ecm_db_connection_interfaces_deref(struct ecm_db_iface_instance *interfaces[], int32_t first);
+
+void ecm_db_connection_interfaces_reset(struct ecm_db_connection_instance *ci,
+					struct ecm_db_iface_instance *interfaces[], int32_t new_first, ecm_db_obj_dir_t dir);
+
+void ecm_db_connection_interfaces_clear(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir);
+
+bool ecm_db_connection_interfaces_set_check(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir);
+
+int32_t ecm_db_connection_interfaces_get_count(struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir);
+
+int32_t ecm_db_connection_interfaces_get_and_ref(struct ecm_db_connection_instance *ci,
+						 struct ecm_db_iface_instance *interfaces[],
+						 ecm_db_obj_dir_t dir);
+
+void ecm_db_connection_classifier_assign(struct ecm_db_connection_instance *ci,
+					 struct ecm_classifier_instance *new_ca);
+int ecm_db_connection_classifier_assignments_get_and_ref(struct ecm_db_connection_instance *ci,
+							 struct ecm_classifier_instance *assignments[]);
+void ecm_db_connection_classifier_unassign(struct ecm_db_connection_instance *ci,
+					   struct ecm_classifier_instance *cci);
+void ecm_db_connection_assignments_release(int assignment_count,
+					   struct ecm_classifier_instance *assignments[]);
+struct ecm_classifier_instance *
+ecm_db_connection_assigned_classifier_find_and_ref(struct ecm_db_connection_instance *ci,
+						   ecm_classifier_type_t type);
+
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+struct ecm_db_connection_instance *
+ecm_db_connection_by_classifier_type_assignment_get_and_ref_first(ecm_classifier_type_t ca_type);
+struct ecm_db_connection_instance *
+ecm_db_connection_by_classifier_type_assignment_get_and_ref_next(struct ecm_db_connection_instance *ci,
+								 ecm_classifier_type_t ca_type);
+void ecm_db_connection_by_classifier_type_assignment_deref(struct ecm_db_connection_instance *ci,
+							   ecm_classifier_type_t ca_type);
+void ecm_db_connection_regenerate_by_assignment_type(ecm_classifier_type_t ca_type);
+void ecm_db_connection_make_defunct_by_assignment_type(ecm_classifier_type_t ca_type);
+#endif
+
+struct ecm_db_connection_instance *ecm_db_connection_alloc(void);
+void ecm_db_connection_add(struct ecm_db_connection_instance *ci,
+			   struct ecm_db_mapping_instance *mapping[],
+			   struct ecm_db_node_instance *node[],
+			   int ip_version, int protocol, ecm_db_direction_t dir,
+			   ecm_db_connection_final_callback_t final,
+			   ecm_db_connection_defunct_callback_t defunct,
+			   ecm_db_timer_group_t tg, bool is_routed, void *arg);
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+int ecm_db_connection_heirarchy_state_get(struct ecm_state_file_instance *sfi,
+					  struct ecm_db_iface_instance *interfaces[],
+					  int32_t first_interface);
+int ecm_db_connection_state_get(struct ecm_state_file_instance *sfi,
+				struct ecm_db_connection_instance *ci);
+int ecm_db_connection_hash_table_lengths_get(int index);
+int ecm_db_connection_hash_index_get_next(int index);
+int ecm_db_connection_hash_index_get_first(void);
+int ecm_db_protocol_get_next(int protocol);
+int ecm_db_protocol_get_first(void);
+#endif
+
+struct ecm_db_connection_instance *ecm_db_connection_ipv4_from_ct_get_and_ref(struct nf_conn *ct);
+struct ecm_db_connection_instance *ecm_db_connection_ipv6_from_ct_get_and_ref(struct nf_conn *ct);
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+struct ecm_db_connection_instance *ecm_db_connection_from_ovs_flow_get_and_ref(struct ovsmgr_dp_flow *flow);
+#endif
+bool ecm_db_connection_decel_v4(__be32 src_ip, int src_port,
+				__be32 dest_ip, int dest_port, int protocol);
+bool ecm_db_connection_decel_v6(struct in6_addr *src_ip, int src_port,
+				struct in6_addr *dest_ip, int dest_port, int protocol);
+void ecm_db_front_end_instance_ref_and_set(struct ecm_db_connection_instance *ci,
+					   struct ecm_front_end_connection_instance *feci);
+
+void ecm_db_connection_flag_set(struct ecm_db_connection_instance *ci, uint32_t flag);
+
+void ecm_db_connection_l2_encap_proto_set(struct ecm_db_connection_instance *ci, uint16_t l2_encap_proto);
+uint16_t ecm_db_connection_l2_encap_proto_get(struct ecm_db_connection_instance *ci);
+void ecm_db_connection_mark_set(struct ecm_db_connection_instance *ci, uint32_t mark);
+uint32_t ecm_db_connection_mark_get(struct ecm_db_connection_instance *ci);
+
+void ecm_db_connection_defunct_by_classifier(int ip_ver, ip_addr_t src_addr, uint16_t src_port, ip_addr_t dest_addr,
+						uint16_t dest_port, int proto, bool is_routed, ecm_classifier_type_t ca_type);
+
+bool ecm_db_connection_init(struct dentry *dentry);
+void ecm_db_connection_exit(void);
diff --git a/qca-nss-ecm/ecm_db/ecm_db_host.c b/qca-nss-ecm/ecm_db/ecm_db_host.c
new file mode 100644
index 0000000..8820576
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_host.c
@@ -0,0 +1,803 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <linux/random.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <net/ip6_route.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_DB_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_classifier_default.h"
+#include "ecm_db.h"
+
+/*
+ * Global list.
+ * All instances are inserted into global list - this allows easy iteration of all instances of a particular type.
+ * The list is doubly linked for fast removal.  The list is in no particular order.
+ */
+struct ecm_db_host_instance *ecm_db_hosts;
+
+/*
+ * Host hash table
+ */
+#define ECM_DB_HOST_HASH_SLOTS 32768
+static struct ecm_db_host_instance **ecm_db_host_table;	/* Slots of the host hash table */
+static int *ecm_db_host_table_lengths;			/* Tracks how long each chain is */
+
+static int ecm_db_host_count = 0;	/* Number of hosts allocated */
+
+/*
+ * ecm_db_host_generate_hash_index()
+ *	Calculate the hash index.
+ */
+static inline ecm_db_host_hash_t ecm_db_host_generate_hash_index(ip_addr_t address)
+{
+	uint32_t tuple;
+	uint32_t hash_val;
+
+	ECM_IP_ADDR_HASH(tuple, address);
+	hash_val = (uint32_t)jhash_1word(tuple, ecm_db_jhash_rnd);
+	return (ecm_db_host_hash_t)(hash_val & (ECM_DB_HOST_HASH_SLOTS - 1));
+}
+
+/*
+ * _ecm_db_host_count_get()
+ *	Return the host count (lockless).
+ */
+int _ecm_db_host_count_get(void)
+{
+	return ecm_db_host_count;
+}
+
+/*
+ * _ecm_db_host_ref()
+ */
+void _ecm_db_host_ref(struct ecm_db_host_instance *hi)
+{
+	DEBUG_CHECK_MAGIC(hi, ECM_DB_HOST_INSTANCE_MAGIC, "%px: magic failed\n", hi);
+	hi->refs++;
+	DEBUG_TRACE("%px: host ref %d\n", hi, hi->refs);
+	DEBUG_ASSERT(hi->refs > 0, "%px: ref wrap\n", hi);
+}
+
+/*
+ * ecm_db_host_ref()
+ */
+void ecm_db_host_ref(struct ecm_db_host_instance *hi)
+{
+	spin_lock_bh(&ecm_db_lock);
+	_ecm_db_host_ref(hi);
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_host_ref);
+
+/*
+ * ecm_db_hosts_get_and_ref_first()
+ *	Obtain a ref to the first host instance, if any
+ */
+struct ecm_db_host_instance *ecm_db_hosts_get_and_ref_first(void)
+{
+	struct ecm_db_host_instance *hi;
+	spin_lock_bh(&ecm_db_lock);
+	hi = ecm_db_hosts;
+	if (hi) {
+		_ecm_db_host_ref(hi);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return hi;
+}
+EXPORT_SYMBOL(ecm_db_hosts_get_and_ref_first);
+
+/*
+ * ecm_db_host_get_and_ref_next()
+ *	Return the next host in the list given a host
+ */
+struct ecm_db_host_instance *ecm_db_host_get_and_ref_next(struct ecm_db_host_instance *hi)
+{
+	struct ecm_db_host_instance *hin;
+	DEBUG_CHECK_MAGIC(hi, ECM_DB_HOST_INSTANCE_MAGIC, "%px: magic failed", hi);
+	spin_lock_bh(&ecm_db_lock);
+	hin = hi->next;
+	if (hin) {
+		_ecm_db_host_ref(hin);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return hin;
+}
+EXPORT_SYMBOL(ecm_db_host_get_and_ref_next);
+
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+/*
+ * ecm_db_host_data_stats_get()
+ *	Return data stats for the instance
+ */
+void ecm_db_host_data_stats_get(struct ecm_db_host_instance *hi, uint64_t *from_data_total, uint64_t *to_data_total,
+						uint64_t *from_packet_total, uint64_t *to_packet_total,
+						uint64_t *from_data_total_dropped, uint64_t *to_data_total_dropped,
+						uint64_t *from_packet_total_dropped, uint64_t *to_packet_total_dropped)
+{
+	DEBUG_CHECK_MAGIC(hi, ECM_DB_HOST_INSTANCE_MAGIC, "%px: magic failed", hi);
+	spin_lock_bh(&ecm_db_lock);
+	if (from_data_total) {
+		*from_data_total = hi->from_data_total;
+	}
+	if (to_data_total) {
+		*to_data_total = hi->to_data_total;
+	}
+	if (from_packet_total) {
+		*from_packet_total = hi->from_packet_total;
+	}
+	if (to_packet_total) {
+		*to_packet_total = hi->to_packet_total;
+	}
+	if (from_data_total_dropped) {
+		*from_data_total_dropped = hi->from_data_total_dropped;
+	}
+	if (to_data_total_dropped) {
+		*to_data_total_dropped = hi->to_data_total_dropped;
+	}
+	if (from_packet_total_dropped) {
+		*from_packet_total_dropped = hi->from_packet_total_dropped;
+	}
+	if (to_packet_total_dropped) {
+		*to_packet_total_dropped = hi->to_packet_total_dropped;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_host_data_stats_get);
+#endif
+
+/*
+ * ecm_db_host_address_get()
+ *	Return address of host
+ */
+void ecm_db_host_address_get(struct ecm_db_host_instance *hi, ip_addr_t addr)
+{
+	DEBUG_CHECK_MAGIC(hi, ECM_DB_HOST_INSTANCE_MAGIC, "%px: magic failed", hi);
+	ECM_IP_ADDR_COPY(addr, hi->address);
+}
+EXPORT_SYMBOL(ecm_db_host_address_get);
+
+/*
+ * ecm_db_host_on_link_get()
+ *	Return on link status of host
+ */
+bool ecm_db_host_on_link_get(struct ecm_db_host_instance *hi)
+{
+	DEBUG_CHECK_MAGIC(hi, ECM_DB_HOST_INSTANCE_MAGIC, "%px: magic failed", hi);
+	return hi->on_link;
+}
+EXPORT_SYMBOL(ecm_db_host_on_link_get);
+
+/*
+ * ecm_db_host_deref()
+ *	Release a ref to a host instance, possibly causing removal from the database and destruction of the instance
+ */
+int ecm_db_host_deref(struct ecm_db_host_instance *hi)
+{
+	DEBUG_CHECK_MAGIC(hi, ECM_DB_HOST_INSTANCE_MAGIC, "%px: magic failed\n", hi);
+
+	spin_lock_bh(&ecm_db_lock);
+	hi->refs--;
+	DEBUG_TRACE("%px: host deref %d\n", hi, hi->refs);
+	DEBUG_ASSERT(hi->refs >= 0, "%px: ref wrap\n", hi);
+
+	if (hi->refs > 0) {
+		int refs = hi->refs;
+		spin_unlock_bh(&ecm_db_lock);
+		return refs;
+	}
+
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((hi->mappings == NULL) && (hi->mapping_count == 0), "%px: mappings not null\n", hi);
+#endif
+
+	/*
+	 * Remove from database if inserted
+	 */
+	if (!hi->flags & ECM_DB_HOST_FLAGS_INSERTED) {
+		spin_unlock_bh(&ecm_db_lock);
+	} else {
+		struct ecm_db_listener_instance *li;
+
+		/*
+		 * Remove from the global list
+		 */
+		if (!hi->prev) {
+			DEBUG_ASSERT(ecm_db_hosts == hi, "%px: host table bad\n", hi);
+			ecm_db_hosts = hi->next;
+		} else {
+			hi->prev->next = hi->next;
+		}
+		if (hi->next) {
+			hi->next->prev = hi->prev;
+		}
+		hi->prev = NULL;
+		hi->next = NULL;
+
+		/*
+		 * Unlink it from the host hash table
+		 */
+		if (!hi->hash_prev) {
+			DEBUG_ASSERT(ecm_db_host_table[hi->hash_index] == hi, "%px: hash table bad\n", hi);
+			ecm_db_host_table[hi->hash_index] = hi->hash_next;
+		} else {
+			hi->hash_prev->hash_next = hi->hash_next;
+		}
+		if (hi->hash_next) {
+			hi->hash_next->hash_prev = hi->hash_prev;
+		}
+		hi->hash_next = NULL;
+		hi->hash_prev = NULL;
+		ecm_db_host_table_lengths[hi->hash_index]--;
+		DEBUG_ASSERT(ecm_db_host_table_lengths[hi->hash_index] >= 0, "%px: invalid table len %d\n", hi, ecm_db_host_table_lengths[hi->hash_index]);
+
+		spin_unlock_bh(&ecm_db_lock);
+
+		/*
+		 * Throw removed event to listeners
+		 */
+		DEBUG_TRACE("%px: Throw host removed event\n", hi);
+		li = ecm_db_listeners_get_and_ref_first();
+		while (li) {
+			struct ecm_db_listener_instance *lin;
+			if (li->host_removed) {
+				li->host_removed(li->arg, hi);
+			}
+
+			/*
+			 * Get next listener
+			 */
+			lin = ecm_db_listener_get_and_ref_next(li);
+			ecm_db_listener_deref(li);
+			li = lin;
+		}
+	}
+
+	/*
+	 * Throw final event
+	 */
+	if (hi->final) {
+		hi->final(hi->arg);
+	}
+
+	/*
+	 * We can now destroy the instance
+	 */
+	DEBUG_CLEAR_MAGIC(hi);
+	kfree(hi);
+
+	/*
+	 * Decrease global host count
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ecm_db_host_count--;
+	DEBUG_ASSERT(ecm_db_host_count >= 0, "%px: host count wrap\n", hi);
+	spin_unlock_bh(&ecm_db_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_db_host_deref);
+
+/*
+ * ecm_db_host_find_and_ref()
+ *	Lookup and return a host reference if any
+ */
+struct ecm_db_host_instance *ecm_db_host_find_and_ref(ip_addr_t address)
+{
+	ecm_db_host_hash_t hash_index;
+	struct ecm_db_host_instance *hi;
+
+	DEBUG_TRACE("Lookup host with addr " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(address));
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_host_generate_hash_index(address);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	hi = ecm_db_host_table[hash_index];
+	while (hi) {
+		if (!ECM_IP_ADDR_MATCH(hi->address, address)) {
+			hi = hi->hash_next;
+			continue;
+		}
+
+		_ecm_db_host_ref(hi);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("host found %px\n", hi);
+		return hi;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Host not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_host_find_and_ref);
+
+#ifdef ECM_DB_XREF_ENABLE
+/*
+ * ecm_db_host_mappings_get_and_ref_first()
+ *	Return a reference to the first mapping of this host
+ */
+static struct ecm_db_mapping_instance *ecm_db_host_mappings_get_and_ref_first(struct ecm_db_host_instance *hi)
+{
+	struct ecm_db_mapping_instance *mi = NULL;
+
+	DEBUG_CHECK_MAGIC(hi, ECM_DB_HOST_INSTANCE_MAGIC, "%p: magic failed", hi);
+
+	spin_lock_bh(&ecm_db_lock);
+	mi = hi->mappings;
+	if (mi) {
+		_ecm_db_mapping_ref(mi);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	return mi;
+}
+
+/*
+ * ecm_db_host_mapping_get_and_ref_next()
+ *	Return the next host mapping in the list given a mapping
+ */
+static struct ecm_db_mapping_instance *ecm_db_host_mapping_get_and_ref_next(struct ecm_db_mapping_instance *mi)
+{
+	struct ecm_db_mapping_instance *nmi = NULL;
+
+	DEBUG_CHECK_MAGIC(mi, ECM_DB_MAPPING_INSTANCE_MAGIC, "%p: magic failed", mi);
+
+	spin_lock_bh(&ecm_db_lock);
+	nmi = mi->mapping_next;
+	if (nmi) {
+		_ecm_db_mapping_ref(nmi);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	return nmi;
+}
+
+/*
+ * ecm_db_host_connections_defunct_by_dir()
+ *	Defunct the connections associated with the IP address in the given direction.
+ */
+void ecm_db_host_connections_defunct_by_dir(ip_addr_t addr, ecm_db_obj_dir_t dir)
+{
+	struct ecm_db_host_instance *hi;
+	struct ecm_db_mapping_instance *mi;
+
+	hi = ecm_db_host_find_and_ref(addr);
+	if (!hi) {
+		DEBUG_WARN("Unable to find host instance\n");
+		return;
+	}
+
+	DEBUG_CHECK_MAGIC(hi, ECM_DB_HOST_INSTANCE_MAGIC, "%px: magic failed\n", hi);
+
+	mi = ecm_db_host_mappings_get_and_ref_first(hi);
+	while (mi) {
+		struct ecm_db_connection_instance *ci;
+		struct ecm_db_mapping_instance *min;
+
+		ci = ecm_db_mapping_connections_get_and_ref_first(mi, dir);
+		while (ci) {
+			struct ecm_db_connection_instance *cin;
+			DEBUG_TRACE("%px: defunct %d\n", ci, ci->serial);
+			ecm_db_connection_make_defunct(ci);
+
+			cin = ecm_db_connection_mapping_get_and_ref_next(ci, dir);
+			ecm_db_connection_deref(ci);
+			ci = cin;
+		}
+
+		min = ecm_db_host_mapping_get_and_ref_next(mi);
+		ecm_db_mapping_deref(mi);
+		mi = min;
+	}
+
+	if (ECM_IP_ADDR_IS_V4(addr)) {
+		DEBUG_INFO("%px: Defuncting connections %s " ECM_IP_ADDR_DOT_FMT "\n",
+			   hi, ecm_db_obj_dir_strings[dir], ECM_IP_ADDR_TO_DOT(addr));
+	} else {
+		DEBUG_INFO("%px: Defuncting connections %s " ECM_IP_ADDR_OCTAL_FMT "\n",
+			   hi, ecm_db_obj_dir_strings[dir], ECM_IP_ADDR_TO_OCTAL(addr));
+	}
+}
+
+/*
+ * ecm_db_host_connections_defunct_by_src_and_dest()
+ *	Defunct the connections with the given source and destination IP addresses.
+ */
+void ecm_db_host_connections_defunct_by_src_and_dest(ip_addr_t src_addr, ip_addr_t dest_addr)
+{
+	struct ecm_db_host_instance *src_hi;
+	struct ecm_db_mapping_instance *src_mi;
+
+	src_hi = ecm_db_host_find_and_ref(src_addr);
+	if (!src_hi) {
+		DEBUG_WARN("Unable to find host instance\n");
+		return;
+	}
+
+	DEBUG_CHECK_MAGIC(src_hi, ECM_DB_HOST_INSTANCE_MAGIC, "%px: magic failed\n", src_hi);
+
+	src_mi = ecm_db_host_mappings_get_and_ref_first(src_hi);
+	while (src_mi) {
+		struct ecm_db_connection_instance *ci;
+		struct ecm_db_mapping_instance *src_min;
+
+		ci = ecm_db_mapping_connections_get_and_ref_first(src_mi, ECM_DB_OBJ_DIR_FROM);
+		while (ci) {
+			struct ecm_db_connection_instance *cin;
+			ip_addr_t dst_ip;
+
+			ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+
+			if (ECM_IP_ADDR_MATCH(dest_addr, dst_ip)) {
+				DEBUG_TRACE("%px: defunct %d\n", ci, ci->serial);
+				ecm_db_connection_make_defunct(ci);
+			}
+
+			cin = ecm_db_connection_mapping_get_and_ref_next(ci, ECM_DB_OBJ_DIR_FROM);
+			ecm_db_connection_deref(ci);
+			ci = cin;
+		}
+
+		src_min = ecm_db_host_mapping_get_and_ref_next(src_mi);
+		ecm_db_mapping_deref(src_mi);
+		src_mi = src_min;
+	}
+
+	if (ECM_IP_ADDR_IS_V4(src_addr)) {
+		DEBUG_INFO("%px: Defuncting connections from " ECM_IP_ADDR_DOT_FMT "to " ECM_IP_ADDR_DOT_FMT "\n",
+			   src_hi, ECM_IP_ADDR_TO_DOT(src_addr), ECM_IP_ADDR_TO_DOT(dest_addr));
+	} else {
+		DEBUG_INFO("%px: Defuncting connections from " ECM_IP_ADDR_OCTAL_FMT "to " ECM_IP_ADDR_OCTAL_FMT "\n",
+			   src_hi, ECM_IP_ADDR_TO_OCTAL(src_addr), ECM_IP_ADDR_TO_OCTAL(dest_addr));
+	}
+}
+
+/*
+ * ecm_db_host_mapping_count_get()
+ *	Return the number of mappings to this host
+ */
+int ecm_db_host_mapping_count_get(struct ecm_db_host_instance *hi)
+{
+	int count;
+
+	DEBUG_CHECK_MAGIC(hi, ECM_DB_HOST_INSTANCE_MAGIC, "%px: magic failed\n", hi);
+
+	spin_lock_bh(&ecm_db_lock);
+	count = hi->mapping_count;
+	spin_unlock_bh(&ecm_db_lock);
+	return count;
+}
+EXPORT_SYMBOL(ecm_db_host_mapping_count_get);
+#endif
+
+/*
+ * ecm_db_host_add()
+ *	Add a host instance into the database
+ */
+void ecm_db_host_add(struct ecm_db_host_instance *hi, ip_addr_t address, bool on_link, ecm_db_host_final_callback_t final, void *arg)
+{
+	ecm_db_host_hash_t hash_index;
+	struct ecm_db_listener_instance *li;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(hi, ECM_DB_HOST_INSTANCE_MAGIC, "%px: magic failed\n", hi);
+	DEBUG_ASSERT(!(hi->flags & ECM_DB_HOST_FLAGS_INSERTED), "%px: inserted\n", hi);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((hi->mappings == NULL) && (hi->mapping_count == 0), "%px: mappings not null\n", hi);
+#endif
+	spin_unlock_bh(&ecm_db_lock);
+
+	hi->arg = arg;
+	hi->final = final;
+	ECM_IP_ADDR_COPY(hi->address, address);
+	hi->on_link = on_link;
+
+	/*
+	 * Compute hash index into which host will be added
+	 */
+	hash_index = ecm_db_host_generate_hash_index(address);
+	hi->hash_index = hash_index;
+
+	/*
+	 * Add into the global list
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	hi->flags |= ECM_DB_HOST_FLAGS_INSERTED;
+	hi->prev = NULL;
+	hi->next = ecm_db_hosts;
+	if (ecm_db_hosts) {
+		ecm_db_hosts->prev = hi;
+	}
+	ecm_db_hosts = hi;
+
+	/*
+	 * Add host into the hash table
+	 */
+	hi->hash_prev = NULL;
+	hi->hash_next = ecm_db_host_table[hash_index];
+	if (ecm_db_host_table[hash_index]) {
+		ecm_db_host_table[hash_index]->hash_prev = hi;
+	}
+	ecm_db_host_table[hash_index] = hi;
+	ecm_db_host_table_lengths[hash_index]++;
+	DEBUG_ASSERT(ecm_db_host_table_lengths[hash_index] > 0, "%px: invalid table len %d\n", hi, ecm_db_host_table_lengths[hash_index]);
+
+	/*
+	 * Set time of add
+	 */
+	hi->time_added = ecm_db_time;
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Throw add event to the listeners
+	 */
+	DEBUG_TRACE("%px: Throw host added event\n", hi);
+	li = ecm_db_listeners_get_and_ref_first();
+	while (li) {
+		struct ecm_db_listener_instance *lin;
+		if (li->host_added) {
+			li->host_added(li->arg, hi);
+		}
+
+		/*
+		 * Get next listener
+		 */
+		lin = ecm_db_listener_get_and_ref_next(li);
+		ecm_db_listener_deref(li);
+		li = lin;
+	}
+}
+EXPORT_SYMBOL(ecm_db_host_add);
+
+/*
+ * ecm_db_host_state_get()
+ *	Prepare a host message
+ */
+int ecm_db_host_state_get(struct ecm_state_file_instance *sfi, struct ecm_db_host_instance *hi)
+{
+	int result;
+	char address[ECM_IP_ADDR_STR_BUFF_SIZE];
+#ifdef ECM_DB_XREF_ENABLE
+	int mapping_count;
+#endif
+	uint32_t time_added;
+	bool on_link;
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	uint64_t from_data_total;
+	uint64_t to_data_total;
+	uint64_t from_packet_total;
+	uint64_t to_packet_total;
+	uint64_t from_data_total_dropped;
+	uint64_t to_data_total_dropped;
+	uint64_t from_packet_total_dropped;
+	uint64_t to_packet_total_dropped;
+#endif
+
+	DEBUG_TRACE("Prep host msg for %px\n", hi);
+
+	/*
+	 * Create a small xml stats element for our host.
+	 * Extract information from the host for inclusion into the message
+	 */
+#ifdef ECM_DB_XREF_ENABLE
+	mapping_count = ecm_db_host_mapping_count_get(hi);
+#endif
+	ecm_ip_addr_to_string(address, hi->address);
+	time_added = hi->time_added;
+	on_link = hi->on_link;
+
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	ecm_db_host_data_stats_get(hi, &from_data_total, &to_data_total,
+			&from_packet_total, &to_packet_total,
+			&from_data_total_dropped, &to_data_total_dropped,
+			&from_packet_total_dropped, &to_packet_total_dropped);
+#endif
+
+	if ((result = ecm_state_prefix_add(sfi, "host"))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "address", "%s", address))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "time_added", "%u", time_added))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "on_link", "%d", on_link))) {
+		return result;
+	}
+
+#ifdef ECM_DB_XREF_ENABLE
+	if ((result = ecm_state_write(sfi, "mappings", "%d", mapping_count))) {
+		return result;
+	}
+#endif
+
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	if ((result = ecm_db_adv_stats_state_write(sfi, from_data_total, to_data_total,
+			from_packet_total, to_packet_total, from_data_total_dropped,
+			to_data_total_dropped, from_packet_total_dropped,
+			to_packet_total_dropped))) {
+		return result;
+	}
+#endif
+
+	return ecm_state_prefix_remove(sfi);
+}
+EXPORT_SYMBOL(ecm_db_host_state_get);
+
+/*
+ * ecm_db_host_hash_table_lengths_get()
+ *	Return hash table length
+ */
+int ecm_db_host_hash_table_lengths_get(int index)
+{
+	int length;
+
+	DEBUG_ASSERT((index >= 0) && (index < ECM_DB_HOST_HASH_SLOTS), "Bad protocol: %d\n", index);
+	spin_lock_bh(&ecm_db_lock);
+	length = ecm_db_host_table_lengths[index];
+	spin_unlock_bh(&ecm_db_lock);
+	return length;
+}
+EXPORT_SYMBOL(ecm_db_host_hash_table_lengths_get);
+
+/*
+ * ecm_db_host_hash_index_get_next()
+ * Given a hash index, return the next one OR return -1 for no more hash indicies to return.
+ */
+int ecm_db_host_hash_index_get_next(int index)
+{
+	index++;
+	if (index >= ECM_DB_HOST_HASH_SLOTS) {
+		return -1;
+	}
+	return index;
+}
+EXPORT_SYMBOL(ecm_db_host_hash_index_get_next);
+
+/*
+ * ecm_db_host_hash_index_get_first()
+ * Return first hash index
+ */
+int ecm_db_host_hash_index_get_first(void)
+{
+	return 0;
+}
+EXPORT_SYMBOL(ecm_db_host_hash_index_get_first);
+
+/*
+ * ecm_db_host_alloc()
+ *	Allocate a host instance
+ */
+struct ecm_db_host_instance *ecm_db_host_alloc(void)
+{
+	struct ecm_db_host_instance *hi;
+	hi = (struct ecm_db_host_instance *)kzalloc(sizeof(struct ecm_db_host_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!hi) {
+		DEBUG_WARN("Alloc failed\n");
+		return NULL;
+	}
+
+	hi->refs = 1;
+	DEBUG_SET_MAGIC(hi, ECM_DB_HOST_INSTANCE_MAGIC);
+
+	/*
+	 * Alloc operation must be atomic to ensure thread and module can be held
+	 */
+	spin_lock_bh(&ecm_db_lock);
+
+	/*
+	 * If the event processing thread is terminating then we cannot create new instances
+	 */
+	if (ecm_db_terminate_pending) {
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_WARN("Thread terminating\n");
+		kfree(hi);
+		return NULL;
+	}
+
+	ecm_db_host_count++;
+	spin_unlock_bh(&ecm_db_lock);
+
+	DEBUG_TRACE("Host created %px\n", hi);
+	return hi;
+}
+EXPORT_SYMBOL(ecm_db_host_alloc);
+
+/*
+ * ecm_db_host_init()
+ */
+bool ecm_db_host_init(struct dentry *dentry)
+{
+
+	if (!debugfs_create_u32("host_count", S_IRUGO, dentry,
+					(u32 *)&ecm_db_host_count)) {
+		DEBUG_ERROR("Failed to create ecm db host count file in debugfs\n");
+		return false;;
+	}
+
+	ecm_db_host_table = vzalloc(sizeof(struct ecm_db_host_instance *) * ECM_DB_HOST_HASH_SLOTS);
+	if (!ecm_db_host_table) {
+		DEBUG_ERROR("Failed to allocate virtual memory for ecm_db_host_table\n");
+		return false;
+	}
+
+	ecm_db_host_table_lengths = vzalloc(sizeof(int) * ECM_DB_HOST_HASH_SLOTS);
+	if (!ecm_db_host_table_lengths) {
+		DEBUG_ERROR("Failed to allocate virtual memory for ecm_db_host_table_lengths\n");
+		vfree(ecm_db_host_table);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * ecm_db_host_exit()
+ */
+void ecm_db_host_exit(void)
+{
+	vfree(ecm_db_host_table_lengths);
+	vfree(ecm_db_host_table);
+}
diff --git a/qca-nss-ecm/ecm_db/ecm_db_host.h b/qca-nss-ecm/ecm_db/ecm_db_host.h
new file mode 100644
index 0000000..81f62ec
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_host.h
@@ -0,0 +1,104 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * Magic number
+ */
+#define ECM_DB_HOST_INSTANCE_MAGIC 0x2873
+
+typedef uint32_t ecm_db_host_hash_t;
+
+/*
+ * Host flags
+ */
+#define ECM_DB_HOST_FLAGS_INSERTED 1			/* Host is inserted into connection database tables */
+
+/*
+ * struct ecm_db_host_instance
+ */
+struct ecm_db_host_instance {
+	struct ecm_db_host_instance *next;		/* Next instance in global list */
+	struct ecm_db_host_instance *prev;		/* Previous instance in global list */
+	struct ecm_db_host_instance *hash_next;		/* Next host in the chain of hosts */
+	struct ecm_db_host_instance *hash_prev;		/* previous host in the chain of hosts */
+	ip_addr_t address;				/* RO: IPv4/v6 Address of this host */
+	bool on_link;					/* RO: false when this host is reached via a gateway */
+	uint32_t time_added;				/* RO: DB time stamp when the host was added into the database */
+
+#ifdef ECM_DB_XREF_ENABLE
+	/*
+	 * Normally the mapping refers to the host it requires.
+	 * However the host also keeps a list of all mappings that are associated with it.
+	 */
+	struct ecm_db_mapping_instance *mappings;	/* Mappings made on this host */
+	int mapping_count;				/* Number of mappings in the mapping list */
+#endif
+
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	uint64_t from_data_total;			/* Total of data sent by this host */
+	uint64_t to_data_total;				/* Total of data sent to this host */
+	uint64_t from_packet_total;			/* Total of packets sent by this host */
+	uint64_t to_packet_total;			/* Total of packets sent to this host */
+	uint64_t from_data_total_dropped;
+	uint64_t to_data_total_dropped;
+	uint64_t from_packet_total_dropped;
+	uint64_t to_packet_total_dropped;
+#endif
+
+	ecm_db_host_final_callback_t final;		/* Callback to owner when object is destroyed */
+	void *arg;					/* Argument returned to owner in callbacks */
+	uint32_t flags;
+	int refs;					/* Integer to trap we never go negative */
+	ecm_db_host_hash_t hash_index;
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+int _ecm_db_host_count_get(void);
+
+void _ecm_db_host_ref(struct ecm_db_host_instance *hi);
+void ecm_db_host_ref(struct ecm_db_host_instance *hi);
+int ecm_db_host_deref(struct ecm_db_host_instance *hi);
+
+void ecm_db_host_address_get(struct ecm_db_host_instance *hi, ip_addr_t addr);
+bool ecm_db_host_on_link_get(struct ecm_db_host_instance *hi);
+
+struct ecm_db_host_instance *ecm_db_host_find_and_ref(ip_addr_t address);
+struct ecm_db_host_instance *ecm_db_hosts_get_and_ref_first(void);
+struct ecm_db_host_instance *ecm_db_host_get_and_ref_next(struct ecm_db_host_instance *hi);
+
+#ifdef ECM_DB_XREF_ENABLE
+int ecm_db_host_mapping_count_get(struct ecm_db_host_instance *hi);
+void ecm_db_host_connections_defunct_by_dir(ip_addr_t addr, ecm_db_obj_dir_t dir);
+void ecm_db_host_connections_defunct_by_src_and_dest(ip_addr_t src_addr, ip_addr_t dest_addr);
+#endif
+
+struct ecm_db_host_instance *ecm_db_host_alloc(void);
+void ecm_db_host_add(struct ecm_db_host_instance *hi,
+		     ip_addr_t address,
+		     bool on_link,
+		     ecm_db_host_final_callback_t final, void *arg);
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+int ecm_db_host_state_get(struct ecm_state_file_instance *sfi, struct ecm_db_host_instance *hi);
+int ecm_db_host_hash_table_lengths_get(int index);
+int ecm_db_host_hash_index_get_next(int index);
+int ecm_db_host_hash_index_get_first(void);
+#endif
+
+bool ecm_db_host_init(struct dentry *dentry);
+void ecm_db_host_exit(void);
diff --git a/qca-nss-ecm/ecm_db/ecm_db_iface.c b/qca-nss-ecm/ecm_db/ecm_db_iface.c
new file mode 100644
index 0000000..53c254c
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_iface.c
@@ -0,0 +1,3698 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <linux/random.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <net/ip6_route.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_DB_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_classifier_default.h"
+#include "ecm_db.h"
+
+/*
+ * Global list.
+ * All instances are inserted into global list - this allows easy iteration of all instances of a particular type.
+ * The list is doubly linked for fast removal.  The list is in no particular order.
+ */
+struct ecm_db_iface_instance *ecm_db_interfaces = NULL;
+
+/*
+ * Interface hash table
+ */
+#define ECM_DB_IFACE_HASH_SLOTS 8
+static struct ecm_db_iface_instance *ecm_db_iface_table[ECM_DB_IFACE_HASH_SLOTS];
+                                                        /* Slots of the interface hash table */
+static int ecm_db_iface_table_lengths[ECM_DB_IFACE_HASH_SLOTS];
+                                                        /* Tracks how long each chain is */
+#define ECM_DB_IFACE_ID_HASH_SLOTS 8
+static struct ecm_db_iface_instance *ecm_db_iface_id_table[ECM_DB_IFACE_ID_HASH_SLOTS];
+                                                        /* Slots of the interface id hash table */
+static int ecm_db_iface_id_table_lengths[ECM_DB_IFACE_ID_HASH_SLOTS];
+                                                        /* Tracks how long each chain is */
+static int ecm_db_iface_count = 0;			/* Number of interfaces allocated */
+
+/*
+ * Interface flags
+ */
+#define ECM_DB_IFACE_FLAGS_INSERTED 1			/* Interface is inserted into connection database tables */
+
+/*
+ * ecm_db_interface_type_names[]
+ *	Array that maps the interface type to a string
+ */
+static char *ecm_db_interface_type_names[ECM_DB_IFACE_TYPE_COUNT] = {
+	"ETHERNET",
+	"PPPoE",
+	"LINK-AGGREGATION",
+	"VLAN",
+	"BRIDGE",
+	"LOOPBACK",
+	"IPSEC_TUNNEL",
+	"UNKNOWN",
+	"SIT",
+	"TUNIPIP6",
+	"PPPoL2TPV2",
+	"PPTP",
+	"MAP_T",
+	"GRE_TUN",
+	"GRE_TAP",
+	"RAWIP",
+	"OVPN",
+	"VxLAN",
+	"OVS_BRIDGE",
+	"MACVLAN"
+};
+
+/*
+ * _ecm_db_iface_count_get()
+ *	Return the iface count (lockless).
+ */
+int _ecm_db_iface_count_get(void)
+{
+	return ecm_db_iface_count;
+}
+
+/*
+ * ecm_db_interface_type_to_string()
+ *	Return a string buffer containing the type name of the interface
+ */
+char *ecm_db_interface_type_to_string(ecm_db_iface_type_t type)
+{
+	DEBUG_ASSERT((type >= 0) && (type < ECM_DB_IFACE_TYPE_COUNT), "Invalid type: %d\n", type);
+	return ecm_db_interface_type_names[(int)type];
+}
+EXPORT_SYMBOL(ecm_db_interface_type_to_string);
+
+/*
+ * ecm_db_iface_type_get()
+ *	Return type of interface
+ */
+ecm_db_iface_type_t ecm_db_iface_type_get(struct ecm_db_iface_instance *ii)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	return ii->type;
+}
+EXPORT_SYMBOL(ecm_db_iface_type_get);
+
+/*
+ * ecm_db_iface_id_generate_hash_index()
+ *	Calculate the hash index based on interface identifier.
+ */
+static inline ecm_db_iface_id_hash_t ecm_db_iface_id_generate_hash_index(int32_t interface_id)
+{
+	uint32_t hash_val;
+
+	hash_val = (uint32_t)jhash_1word((uint32_t)interface_id, ecm_db_jhash_rnd);
+	return (ecm_db_iface_id_hash_t)(hash_val & (ECM_DB_IFACE_ID_HASH_SLOTS - 1));
+}
+
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+/*
+ * ecm_db_iface_data_stats_get()
+ *	Return data stats for the instance
+ */
+static void ecm_db_iface_data_stats_get(struct ecm_db_iface_instance *ii, uint64_t *from_data_total, uint64_t *to_data_total,
+						uint64_t *from_packet_total, uint64_t *to_packet_total,
+						uint64_t *from_data_total_dropped, uint64_t *to_data_total_dropped,
+						uint64_t *from_packet_total_dropped, uint64_t *to_packet_total_dropped)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	spin_lock_bh(&ecm_db_lock);
+	if (from_data_total) {
+		*from_data_total = ii->from_data_total;
+	}
+	if (to_data_total) {
+		*to_data_total = ii->to_data_total;
+	}
+	if (from_packet_total) {
+		*from_packet_total = ii->from_packet_total;
+	}
+	if (to_packet_total) {
+		*to_packet_total = ii->to_packet_total;
+	}
+	if (from_data_total_dropped) {
+		*from_data_total_dropped = ii->from_data_total_dropped;
+	}
+	if (to_data_total_dropped) {
+		*to_data_total_dropped = ii->to_data_total_dropped;
+	}
+	if (from_packet_total_dropped) {
+		*from_packet_total_dropped = ii->from_packet_total_dropped;
+	}
+	if (to_packet_total_dropped) {
+		*to_packet_total_dropped = ii->to_packet_total_dropped;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+}
+#endif
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_db_iface_state_get_base()
+ *	Get the basic state for an interface object
+ */
+static int ecm_db_iface_state_get_base(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+#ifdef ECM_DB_XREF_ENABLE
+	int node_count;
+#endif
+	uint32_t time_added;
+	int32_t interface_identifier;
+	int32_t ae_interface_identifier;
+	char name[IFNAMSIZ];
+	int32_t mtu;
+	ecm_db_iface_type_t type;
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	uint64_t from_data_total;
+	uint64_t to_data_total;
+	uint64_t from_packet_total;
+	uint64_t to_packet_total;
+	uint64_t from_data_total_dropped;
+	uint64_t to_data_total_dropped;
+	uint64_t from_packet_total_dropped;
+	uint64_t to_packet_total_dropped;
+#endif
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	DEBUG_TRACE("%px: Open iface msg\n", ii);
+
+	if ((result = ecm_state_prefix_add(sfi, "iface"))) {
+		return result;
+	}
+
+#ifdef ECM_DB_XREF_ENABLE
+	node_count = ecm_db_iface_node_count_get(ii);
+#endif
+	time_added = ii->time_added;
+	type = ii->type;
+	interface_identifier = ii->interface_identifier;
+	ae_interface_identifier = ii->ae_interface_identifier;
+	spin_lock_bh(&ecm_db_lock);
+	strlcpy(name, ii->name, IFNAMSIZ);
+	mtu = ii->mtu;
+	spin_unlock_bh(&ecm_db_lock);
+
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	ecm_db_iface_data_stats_get(ii, &from_data_total, &to_data_total,
+			&from_packet_total, &to_packet_total,
+			&from_data_total_dropped, &to_data_total_dropped,
+			&from_packet_total_dropped, &to_packet_total_dropped);
+
+	if ((result = ecm_db_adv_stats_state_write(sfi, from_data_total, to_data_total,
+			from_packet_total, to_packet_total, from_data_total_dropped,
+			to_data_total_dropped, from_packet_total_dropped,
+			to_packet_total_dropped))) {
+		return result;
+	}
+#endif
+
+	if ((result = ecm_state_write(sfi, "type", "%d", type))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "name", "%s", name))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "time_added", "%u", time_added))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "mtu", "%d", mtu))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "interface_identifier", "%d", interface_identifier))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "ae_interface_identifier", "%d", ae_interface_identifier))) {
+		return result;
+	}
+
+#ifdef ECM_DB_XREF_ENABLE
+	if ((result = ecm_state_write(sfi, "nodes", "%d", node_count))) {
+		return result;
+	}
+#endif
+
+	return ecm_state_prefix_remove(sfi);
+}
+
+/*
+ * ecm_db_iface_ethernet_state_get()
+ * 	Return interface type specific state
+ */
+static int ecm_db_iface_ethernet_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	uint8_t address[ETH_ALEN];
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	memcpy(address, ii->type_info.ethernet.address, ETH_ALEN);
+	spin_unlock_bh(&ecm_db_lock);
+
+	if ((result = ecm_state_prefix_add(sfi, "ethernet"))) {
+		return result;
+	}
+
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "address", "%pM", address))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+
+#ifdef ECM_INTERFACE_BOND_ENABLE
+/*
+ * ecm_db_iface_lag_state_get()
+ * 	Return interface type specific state
+ */
+static int ecm_db_iface_lag_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	uint8_t address[ETH_ALEN];
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	memcpy(address, ii->type_info.lag.address, ETH_ALEN);
+	spin_unlock_bh(&ecm_db_lock);
+
+	if ((result = ecm_state_prefix_add(sfi, "lag"))) {
+		return result;
+	}
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "address", "%pM", address))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+/*
+ * ecm_db_iface_bridge_state_get()
+ * 	Return interface type specific state
+ */
+static int ecm_db_iface_bridge_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	uint8_t address[ETH_ALEN];
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	memcpy(address, ii->type_info.bridge.address, ETH_ALEN);
+	spin_unlock_bh(&ecm_db_lock);
+
+	if ((result = ecm_state_prefix_add(sfi, "bridge"))) {
+		return result;
+	}
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "address", "%pM", address))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+/*
+ * ecm_db_iface_macvlan_state_get()
+ * 	Return interface type specific state
+ */
+static int ecm_db_iface_macvlan_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	uint8_t address[ETH_ALEN];
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	memcpy(address, ii->type_info.macvlan.address, ETH_ALEN);
+	spin_unlock_bh(&ecm_db_lock);
+
+	if ((result = ecm_state_prefix_add(sfi, "macvlan"))) {
+		return result;
+	}
+
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		goto done;
+	}
+
+	if ((result = ecm_state_write(sfi, "address", "%pM", address))) {
+		goto done;
+	}
+
+done:
+	ecm_state_prefix_remove(sfi);
+	return result;
+}
+#endif
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+/*
+ * ecm_db_iface_ovs_bridge_state_get()
+ * 	Return interface type specific state
+ */
+static int ecm_db_iface_ovs_bridge_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	uint8_t address[ETH_ALEN];
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	memcpy(address, ii->type_info.ovsb.address, ETH_ALEN);
+	spin_unlock_bh(&ecm_db_lock);
+
+	if ((result = ecm_state_prefix_add(sfi, "ovs_bridge"))) {
+		return result;
+	}
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "address", "%pM", address))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+/*
+ * ecm_db_iface_vlan_state_get()
+ * 	Return interface type specific state
+ */
+static int ecm_db_iface_vlan_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	uint8_t address[ETH_ALEN];
+	uint16_t vlan_tag;
+	uint16_t vlan_tpid;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	memcpy(address, ii->type_info.vlan.address, ETH_ALEN);
+	vlan_tag = ii->type_info.vlan.vlan_tag;
+	vlan_tpid = ii->type_info.vlan.vlan_tpid;
+	spin_unlock_bh(&ecm_db_lock);
+
+	if ((result = ecm_state_prefix_add(sfi, "vlan"))) {
+		return result;
+	}
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "address", "%pM", address))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "tag", "%x", vlan_tag))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "tpid", "%x", vlan_tpid))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+/*
+ * ecm_db_iface_pppoe_state_get()
+ * 	Return interface type specific state
+ */
+static int ecm_db_iface_pppoe_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	uint16_t pppoe_session_id;
+	uint8_t remote_mac[ETH_ALEN];
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	pppoe_session_id = ii->type_info.pppoe.pppoe_session_id;
+	memcpy(remote_mac, ii->type_info.pppoe.remote_mac, ETH_ALEN);
+	spin_unlock_bh(&ecm_db_lock);
+
+	if ((result = ecm_state_prefix_add(sfi, "pppoe"))) {
+		return result;
+	}
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "remote_mac", "%pM", remote_mac))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "session_id", "%u", pppoe_session_id))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+/*
+ * ecm_db_iface_map_t_state_get()
+ *	Return interface type specific state
+ */
+static int ecm_db_iface_map_t_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	int32_t if_index;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	if_index = ii->type_info.map_t.if_index;
+	spin_unlock_bh(&ecm_db_lock);
+
+	if ((result = ecm_state_prefix_add(sfi, "map_t"))) {
+		return result;
+	}
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "if_index", "%d", if_index))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+/*
+ * ecm_db_iface_gre_tun_state_get
+ * 	Return interface type specific state
+ */
+static int ecm_db_iface_gre_tun_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	int32_t if_index;
+	ip_addr_t local_ip, remote_ip;
+	char local_ipaddress[ECM_IP_ADDR_STR_BUFF_SIZE];
+	char remote_ipaddress[ECM_IP_ADDR_STR_BUFF_SIZE];
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	if_index = ii->type_info.gre_tun.if_index;
+	memcpy(local_ip, ii->type_info.gre_tun.local_ip, sizeof(ip_addr_t));
+	memcpy(remote_ip, ii->type_info.gre_tun.remote_ip, sizeof(ip_addr_t));
+	spin_unlock_bh(&ecm_db_lock);
+
+	ecm_ip_addr_to_string(local_ipaddress, local_ip);
+	ecm_ip_addr_to_string(remote_ipaddress, remote_ip);
+
+	if ((result = ecm_state_prefix_add(sfi, "gre_tun"))) {
+		return result;
+	}
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "if_index", "%d", if_index))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "local_ip", "%s", local_ipaddress))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "remote_ip", "%s", remote_ipaddress))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+
+/*
+ * ecm_db_iface_pppol2tpv2_state_get()
+ *	Return interface type specific state
+ */
+static int ecm_db_iface_pppol2tpv2_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	struct ecm_db_interface_info_pppol2tpv2 type_info;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	memcpy(&type_info, &ii->type_info, sizeof(struct ecm_db_interface_info_pppol2tpv2));
+	spin_unlock_bh(&ecm_db_lock);
+
+	if ((result = ecm_state_prefix_add(sfi, "pppol2tpv2"))) {
+		return result;
+	}
+
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "local_tunnel_id", "%u", type_info.l2tp.tunnel.tunnel_id))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "local_session_id", "%u", type_info.l2tp.session.session_id))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "peer_tunnnel_id", "%u", type_info.l2tp.tunnel.peer_tunnel_id))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "peer_session_id", "%u", type_info.l2tp.session.peer_session_id))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+
+#endif
+
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+/*
+ * ecm_db_iface_pptp_state_get()
+ *	Return interface type specific state
+ */
+static int ecm_db_iface_pptp_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	struct ecm_db_interface_info_pptp type_info;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	memcpy(&type_info, &ii->type_info, sizeof(struct ecm_db_interface_info_pptp));
+	spin_unlock_bh(&ecm_db_lock);
+
+	result = ecm_state_prefix_add(sfi, "pptp");
+	if (result) {
+		return result;
+	}
+
+	result = ecm_db_iface_state_get_base(ii, sfi);
+	if (result) {
+		return result;
+	}
+
+	result = ecm_state_write(sfi, "local_call_id", "%u", type_info.src_call_id);
+	if (result) {
+		return result;
+	}
+
+	result = ecm_state_write(sfi, "peer_call_id", "%u", type_info.dst_call_id);
+	if (result) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+/*
+ * ecm_db_iface_unknown_state_get()
+ * 	Return interface type specific state
+ */
+static int ecm_db_iface_unknown_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	uint32_t os_specific_ident;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	os_specific_ident = ii->type_info.unknown.os_specific_ident;
+	spin_unlock_bh(&ecm_db_lock);
+
+	if ((result = ecm_state_prefix_add(sfi, "pppoe"))) {
+		return result;
+	}
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "os_specific_ident", "%u", os_specific_ident))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+
+/*
+ * ecm_db_iface_loopback_state_get()
+ * 	Return interface type specific state
+ */
+static int ecm_db_iface_loopback_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	uint32_t os_specific_ident;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	os_specific_ident = ii->type_info.loopback.os_specific_ident;
+	spin_unlock_bh(&ecm_db_lock);
+
+	if ((result = ecm_state_prefix_add(sfi, "loopback"))) {
+		return result;
+	}
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "os_specific_ident", "%u", os_specific_ident))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+/*
+ * ecm_db_iface_ipsec_tunnel_state_get()
+ * 	Return interface type specific state
+ *
+ * GGG TODO Output state on ipsec tunnel specific data
+ */
+static int ecm_db_iface_ipsec_tunnel_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	uint32_t os_specific_ident;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	os_specific_ident = ii->type_info.ipsec_tunnel.os_specific_ident;
+	spin_unlock_bh(&ecm_db_lock);
+
+	if ((result = ecm_state_prefix_add(sfi, "ipsec"))) {
+		return result;
+	}
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "os_specific_ident", "%u", os_specific_ident))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+#ifdef ECM_INTERFACE_TUNIPIP6_ENABLE
+#ifdef ECM_IPV6_ENABLE
+/*
+ * ecm_db_iface_tunipip6_state_get()
+ * 	Return interface type specific state
+ */
+static int ecm_db_iface_tunipip6_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+
+	/*
+	 * TODO: tunipip6 specific information needs to be added.
+	 */
+	if ((result = ecm_state_prefix_add(sfi, "tunipip6"))) {
+		return result;
+	}
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+#endif
+
+#ifdef ECM_INTERFACE_SIT_ENABLE
+/*
+ * ecm_db_iface_sit_state_get()
+ * 	Return interface type specific state
+ */
+static int ecm_db_iface_sit_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+
+	/*
+	 * TODO: SIT (6rd) specific information needs to be added.
+	 */
+	if ((result = ecm_state_prefix_add(sfi, "sit"))) {
+		return result;
+	}
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+#ifdef ECM_INTERFACE_RAWIP_ENABLE
+/*
+ * ecm_db_iface_rawip_state_get()
+ * 	Return interface type specific state
+ */
+static int ecm_db_iface_rawip_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	uint8_t address[ETH_ALEN];
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	memcpy(address, ii->type_info.rawip.address, ETH_ALEN);
+	spin_unlock_bh(&ecm_db_lock);
+
+	if ((result = ecm_state_prefix_add(sfi, "rawip"))) {
+		return result;
+	}
+
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "address", "%pM", address))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+/*
+ * ecm_db_iface_ovpn_state_get()
+ *	Return OVPN interface state
+ */
+static int ecm_db_iface_ovpn_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	struct ecm_db_interface_info_ovpn type_info;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	memcpy(&type_info, &ii->type_info, sizeof(struct ecm_db_interface_info_ovpn));
+	spin_unlock_bh(&ecm_db_lock);
+
+	result = ecm_state_prefix_add(sfi, "ovpn");
+	if (result) {
+		return result;
+	}
+
+	result = ecm_db_iface_state_get_base(ii, sfi);
+	if (result) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "tun_ifnum", "%u", type_info.tun_ifnum))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+/*
+ * ecm_db_iface_vxlan_state_get()
+ *	Return interface type specific state
+ */
+static int ecm_db_iface_vxlan_state_get(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	uint32_t vni;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+	vni = ii->type_info.vxlan.vni;
+	spin_unlock_bh(&ecm_db_lock);
+
+	if ((result = ecm_state_prefix_add(sfi, "vxlan"))) {
+		return result;
+	}
+
+	if ((result = ecm_db_iface_state_get_base(ii, sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "vni", "%d", vni))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+/*
+ * ecm_db_iface_state_get()
+ *	Obtain state for the interface.
+ *
+ * State specific to the interface type will be returned.
+ */
+int ecm_db_iface_state_get(struct ecm_state_file_instance *sfi, struct ecm_db_iface_instance *ii)
+{
+	int result;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+
+	if ((result = ecm_state_prefix_add(sfi, "iface"))) {
+		return result;
+	}
+
+	if ((result = ii->state_get(ii, sfi))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+
+}
+EXPORT_SYMBOL(ecm_db_iface_state_get);
+
+/*
+ * ecm_db_iface_hash_table_lengths_get()
+ *	Return hash table length
+ */
+int ecm_db_iface_hash_table_lengths_get(int index)
+{
+	int length;
+
+	DEBUG_ASSERT((index >= 0) && (index < ECM_DB_IFACE_HASH_SLOTS), "Bad protocol: %d\n", index);
+	spin_lock_bh(&ecm_db_lock);
+	length = ecm_db_iface_table_lengths[index];
+	spin_unlock_bh(&ecm_db_lock);
+	return length;
+}
+EXPORT_SYMBOL(ecm_db_iface_hash_table_lengths_get);
+
+/*
+ * ecm_db_iface_hash_index_get_next()
+ * Given a hash index, return the next one OR return -1 for no more hash indicies to return.
+ */
+int ecm_db_iface_hash_index_get_next(int index)
+{
+	index++;
+	if (index >= ECM_DB_IFACE_HASH_SLOTS) {
+		return -1;
+	}
+	return index;
+}
+EXPORT_SYMBOL(ecm_db_iface_hash_index_get_next);
+
+/*
+ * ecm_db_iface_hash_index_get_first()
+ * Return first hash index
+ */
+int ecm_db_iface_hash_index_get_first(void)
+{
+	return 0;
+}
+EXPORT_SYMBOL(ecm_db_iface_hash_index_get_first);
+#endif
+
+/*
+ * _ecm_db_iface_ref()
+ */
+void _ecm_db_iface_ref(struct ecm_db_iface_instance *ii)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	ii->refs++;
+	DEBUG_TRACE("%px: iface ref %d\n", ii, ii->refs);
+	DEBUG_ASSERT(ii->refs > 0, "%px: ref wrap\n", ii);
+}
+
+/*
+ * ecm_db_iface_ref()
+ */
+void ecm_db_iface_ref(struct ecm_db_iface_instance *ii)
+{
+	spin_lock_bh(&ecm_db_lock);
+	_ecm_db_iface_ref(ii);
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_iface_ref);
+
+/*
+ * ecm_db_iface_deref()
+ *	Deref a interface instance, removing it from the database on the last ref release
+ */
+int ecm_db_iface_deref(struct ecm_db_iface_instance *ii)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+
+	/*
+	 * Decrement reference count
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii->refs--;
+	DEBUG_TRACE("%px: iface deref %d\n", ii, ii->refs);
+	DEBUG_ASSERT(ii->refs >= 0, "%px: ref wrap\n", ii);
+
+	if (ii->refs > 0) {
+		int refs = ii->refs;
+		spin_unlock_bh(&ecm_db_lock);
+		return refs;
+	}
+
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+
+	/*
+	 * Remove from database if inserted
+	 */
+	if (!ii->flags & ECM_DB_IFACE_FLAGS_INSERTED) {
+		spin_unlock_bh(&ecm_db_lock);
+	} else {
+		struct ecm_db_listener_instance *li;
+
+		/*
+		 * Remove from the global list
+		 */
+		if (!ii->prev) {
+			DEBUG_ASSERT(ecm_db_interfaces == ii, "%px: interface table bad\n", ii);
+			ecm_db_interfaces = ii->next;
+		} else {
+			ii->prev->next = ii->next;
+		}
+		if (ii->next) {
+			ii->next->prev = ii->prev;
+		}
+		ii->prev = NULL;
+		ii->next = NULL;
+
+		/*
+		 * Link out of hash table
+		 */
+		if (!ii->hash_prev) {
+			DEBUG_ASSERT(ecm_db_iface_table[ii->hash_index] == ii, "%px: hash table bad got %px for hash index %u\n", ii, ecm_db_iface_table[ii->hash_index], ii->hash_index);
+			ecm_db_iface_table[ii->hash_index] = ii->hash_next;
+		} else {
+			ii->hash_prev->hash_next = ii->hash_next;
+		}
+		if (ii->hash_next) {
+			ii->hash_next->hash_prev = ii->hash_prev;
+		}
+		ii->hash_next = NULL;
+		ii->hash_prev = NULL;
+		ecm_db_iface_table_lengths[ii->hash_index]--;
+		DEBUG_ASSERT(ecm_db_iface_table_lengths[ii->hash_index] >= 0, "%px: invalid table len %d\n", ii, ecm_db_iface_table_lengths[ii->hash_index]);
+
+		/*
+		 * Link out of interface identifier hash table
+		 */
+		if (!ii->iface_id_hash_prev) {
+			DEBUG_ASSERT(ecm_db_iface_id_table[ii->iface_id_hash_index] == ii, "%px: hash table bad got %px for hash index %u\n", ii, ecm_db_iface_id_table[ii->iface_id_hash_index], ii->iface_id_hash_index);
+			ecm_db_iface_id_table[ii->iface_id_hash_index] = ii->iface_id_hash_next;
+		} else {
+			ii->iface_id_hash_prev->iface_id_hash_next = ii->iface_id_hash_next;
+		}
+		if (ii->iface_id_hash_next) {
+			ii->iface_id_hash_next->iface_id_hash_prev = ii->iface_id_hash_prev;
+		}
+		ii->iface_id_hash_next = NULL;
+		ii->iface_id_hash_prev = NULL;
+		ecm_db_iface_id_table_lengths[ii->iface_id_hash_index]--;
+		DEBUG_ASSERT(ecm_db_iface_id_table_lengths[ii->iface_id_hash_index] >= 0, "%px: invalid table len %d\n", ii, ecm_db_iface_id_table_lengths[ii->iface_id_hash_index]);
+		spin_unlock_bh(&ecm_db_lock);
+
+		/*
+		 * Throw removed event to listeners
+		 */
+		DEBUG_TRACE("%px: Throw iface removed event\n", ii);
+		li = ecm_db_listeners_get_and_ref_first();
+		while (li) {
+			struct ecm_db_listener_instance *lin;
+			if (li->iface_removed) {
+				li->iface_removed(li->arg, ii);
+			}
+
+			/*
+			 * Get next listener
+			 */
+			lin = ecm_db_listener_get_and_ref_next(li);
+			ecm_db_listener_deref(li);
+			li = lin;
+		}
+	}
+
+	/*
+	 * Throw final event
+	 */
+	if (ii->final) {
+		ii->final(ii->arg);
+	}
+
+	/*
+	 * We can now destroy the instance
+	 */
+	DEBUG_CLEAR_MAGIC(ii);
+	kfree(ii);
+
+	/*
+	 * Decrease global interface count
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ecm_db_iface_count--;
+	DEBUG_ASSERT(ecm_db_iface_count >= 0, "%px: iface count wrap\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_db_iface_deref);
+
+/*
+ * ecm_db_iface_ae_interface_identifier_get()
+ *	Return the accel engine interface number of this ecm interface
+ */
+int32_t ecm_db_iface_ae_interface_identifier_get(struct ecm_db_iface_instance *ii)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	return ii->ae_interface_identifier;
+}
+EXPORT_SYMBOL(ecm_db_iface_ae_interface_identifier_get);
+
+/*
+ * ecm_db_iface_ae_interface_identifier_set()
+ *	Sets accel engine  interface number of this ecm interface
+ */
+void ecm_db_iface_ae_interface_identifier_set(struct ecm_db_iface_instance *ii, uint32_t num)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	ii->ae_interface_identifier = num;
+}
+EXPORT_SYMBOL(ecm_db_iface_ae_interface_identifier_set);
+
+/*
+ * ecm_db_iface_interface_identifier_get()
+ *	Return the interface number of this ecm interface
+ */
+int32_t ecm_db_iface_interface_identifier_get(struct ecm_db_iface_instance *ii)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	return ii->interface_identifier;
+}
+EXPORT_SYMBOL(ecm_db_iface_interface_identifier_get);
+
+/*
+ * ecm_db_iface_interface_name_get()
+ *	Return the interface name of this ecm interface
+ *
+ * name_buffer should be at least of size IFNAMSIZ
+ */
+void ecm_db_iface_interface_name_get(struct ecm_db_iface_instance *ii, char *name_buffer)
+{
+	DEBUG_CHECK_MAGIC(ii,
+		ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	strlcpy(name_buffer, ii->name, IFNAMSIZ);
+}
+EXPORT_SYMBOL(ecm_db_iface_interface_name_get);
+
+/*
+ * ecm_db_iface_mtu_reset()
+ *	Reset the mtu
+ */
+int32_t ecm_db_iface_mtu_reset(struct ecm_db_iface_instance *ii, int32_t mtu)
+{
+	int32_t mtu_old;
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	spin_lock_bh(&ecm_db_lock);
+	mtu_old = ii->mtu;
+	ii->mtu = mtu;
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_INFO("%px: Mtu change from %d to %d\n", ii, mtu_old, mtu);
+
+	return mtu_old;
+}
+EXPORT_SYMBOL(ecm_db_iface_mtu_reset);
+
+/*
+ * ecm_db_interfaces_get_and_ref_first()
+ *	Obtain a ref to the first iface instance, if any
+ */
+struct ecm_db_iface_instance *ecm_db_interfaces_get_and_ref_first(void)
+{
+	struct ecm_db_iface_instance *ii;
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_interfaces;
+	if (ii) {
+		_ecm_db_iface_ref(ii);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return ii;
+}
+EXPORT_SYMBOL(ecm_db_interfaces_get_and_ref_first);
+
+/*
+ * ecm_db_interface_get_and_ref_next()
+ *	Return the next iface in the list given a iface
+ */
+struct ecm_db_iface_instance *ecm_db_interface_get_and_ref_next(struct ecm_db_iface_instance *ii)
+{
+	struct ecm_db_iface_instance *iin;
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	spin_lock_bh(&ecm_db_lock);
+	iin = ii->next;
+	if (iin) {
+		_ecm_db_iface_ref(iin);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return iin;
+}
+EXPORT_SYMBOL(ecm_db_interface_get_and_ref_next);
+
+#ifdef ECM_INTERFACE_SIT_ENABLE
+/*
+ * ecm_db_iface_generate_hash_index_sit()
+ * 	Calculate the hash index.
+ */
+static inline ecm_db_iface_hash_t ecm_db_iface_generate_hash_index_sit(ip_addr_t saddr, ip_addr_t daddr)
+{
+	uint32_t tuple1;
+	uint32_t tuple2;
+	uint32_t hash_val;
+
+	ECM_IP_ADDR_HASH(tuple1, saddr);
+	ECM_IP_ADDR_HASH(tuple2, daddr);
+	hash_val = (uint32_t)jhash_2words(tuple1, tuple2, ecm_db_jhash_rnd);
+	return (ecm_db_iface_hash_t)(hash_val & (ECM_DB_IFACE_HASH_SLOTS - 1));
+}
+#endif
+
+#ifdef ECM_INTERFACE_TUNIPIP6_ENABLE
+#ifdef ECM_IPV6_ENABLE
+/*
+ * ecm_db_iface_generate_hash_index_tunipip6()
+ * 	Calculate the hash index.
+ */
+static inline ecm_db_iface_hash_t ecm_db_iface_generate_hash_index_tunipip6(ip_addr_t saddr, ip_addr_t daddr)
+{
+	uint32_t tuple1;
+	uint32_t tuple2;
+	uint32_t hash_val;
+
+	ECM_IP_ADDR_HASH(tuple1, saddr);
+	ECM_IP_ADDR_HASH(tuple2, daddr);
+	hash_val = (uint32_t)jhash_2words(tuple1, tuple2, ecm_db_jhash_rnd);
+	return (ecm_db_iface_hash_t)(hash_val & (ECM_DB_IFACE_HASH_SLOTS - 1));
+}
+#endif
+#endif
+
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+/*
+ * ecm_db_iface_generate_hash_index_ovpn()
+ * 	Calculate the hash index.
+ */
+static inline ecm_db_iface_hash_t ecm_db_iface_generate_hash_index_ovpn(int32_t tun_ifnum)
+{
+	uint32_t hash_val;
+
+	hash_val = (uint32_t)jhash_1word((uint32_t)tun_ifnum, ecm_db_jhash_rnd);
+	return (ecm_db_iface_hash_t)(hash_val & (ECM_DB_IFACE_HASH_SLOTS - 1));
+}
+#endif
+
+/*
+ * ecm_db_iface_generate_hash_index_ethernet()
+ * 	Calculate the hash index.
+ */
+static inline ecm_db_iface_hash_t ecm_db_iface_generate_hash_index_ethernet(uint8_t *address)
+{
+	uint32_t hash_val;
+	hash_val = (uint32_t)jhash(address, 6, ecm_db_jhash_rnd);
+	return (ecm_db_iface_hash_t)(hash_val & (ECM_DB_IFACE_HASH_SLOTS - 1));
+}
+
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+/*
+ * ecm_db_iface_generate_hash_index_pppoe()
+ * 	Calculate the hash index.
+ */
+static inline ecm_db_iface_hash_t ecm_db_iface_generate_hash_index_pppoe(uint16_t pppoe_session_id)
+{
+	uint32_t hash_val;
+	hash_val = (uint32_t)jhash_1word((uint32_t)pppoe_session_id, ecm_db_jhash_rnd);
+	return (ecm_db_iface_hash_t)(hash_val & (ECM_DB_IFACE_HASH_SLOTS - 1));
+}
+#endif
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+/*
+ * ecm_db_iface_generate_hash_index_pppol2tpv2()
+ *	Calculate the hash index.
+ */
+static inline ecm_db_iface_hash_t ecm_db_iface_generate_hash_index_pppol2tpv2(uint32_t pppol2tpv2_tunnel_id, uint32_t pppol2tpv2_session_id)
+{
+	uint32_t hash_val;
+	hash_val = (uint32_t)jhash_2words(pppol2tpv2_tunnel_id, pppol2tpv2_session_id, ecm_db_jhash_rnd);
+	return (ecm_db_iface_hash_t)(hash_val & (ECM_DB_IFACE_HASH_SLOTS - 1));
+}
+
+#endif
+
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+/*
+ * ecm_db_iface_generate_hash_index_pptp()
+ *	Calculate the hash index.
+ */
+static inline ecm_db_iface_hash_t ecm_db_iface_generate_hash_index_pptp(uint16_t pptp_src_call_id, uint16_t pptp_dst_call_id)
+{
+	uint32_t hash_val;
+	hash_val = (uint32_t)jhash_2words(pptp_src_call_id, pptp_dst_call_id, ecm_db_jhash_rnd);
+	return (ecm_db_iface_hash_t)(hash_val & (ECM_DB_IFACE_HASH_SLOTS - 1));
+}
+#endif
+
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+/*
+ * ecm_db_iface_generate_hash_index_map_t()
+ *	Calculate the hash index.
+ */
+static inline ecm_db_iface_hash_t ecm_db_iface_generate_hash_index_map_t(int if_index)
+{
+	uint32_t hash_val;
+	hash_val = (uint32_t)jhash_1word(if_index, ecm_db_jhash_rnd);
+	return (ecm_db_iface_hash_t)(hash_val & (ECM_DB_IFACE_HASH_SLOTS - 1));
+}
+#endif
+
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+/*
+ * ecm_db_iface_generate_hash_index_gre_tun()
+ * 	Calculate the hash index.
+ */
+static inline ecm_db_iface_hash_t ecm_db_iface_generate_hash_index_gre_tun(int if_index)
+{
+	uint32_t hash_val;
+	hash_val = (uint32_t)jhash_1word(if_index, ecm_db_jhash_rnd);
+	return (ecm_db_iface_hash_t)(hash_val & (ECM_DB_IFACE_HASH_SLOTS - 1));
+}
+#endif
+
+/*
+ * ecm_db_iface_generate_hash_index_unknown()
+ * 	Calculate the hash index.
+ */
+static inline ecm_db_iface_hash_t ecm_db_iface_generate_hash_index_unknown(uint32_t os_specific_ident)
+{
+	uint32_t hash_val;
+	hash_val = (uint32_t)jhash_1word(os_specific_ident, ecm_db_jhash_rnd);
+	return (ecm_db_iface_hash_t)(hash_val & (ECM_DB_IFACE_HASH_SLOTS - 1));
+}
+
+/*
+ * ecm_db_iface_generate_hash_index_loopback()
+ * 	Calculate the hash index.
+ */
+static inline ecm_db_iface_hash_t ecm_db_iface_generate_hash_index_loopback(uint32_t os_specific_ident)
+{
+	uint32_t hash_val;
+	hash_val = (uint32_t)jhash_1word(os_specific_ident, ecm_db_jhash_rnd);
+	return (ecm_db_iface_hash_t)(hash_val & (ECM_DB_IFACE_HASH_SLOTS - 1));
+}
+
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+/*
+ * ecm_db_iface_generate_hash_index_ipsec_tunnel()
+ * 	Calculate the hash index.
+ * GGG TODO Flesh this out using actual tunnel endpoint keys
+ */
+static inline ecm_db_iface_hash_t ecm_db_iface_generate_hash_index_ipsec_tunnel(uint32_t os_specific_ident)
+{
+	uint32_t hash_val;
+	hash_val = (uint32_t)jhash_1word(os_specific_ident, ecm_db_jhash_rnd);
+	return (ecm_db_iface_hash_t)(hash_val & (ECM_DB_IFACE_HASH_SLOTS - 1));
+}
+#endif
+
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+/*
+ * ecm_db_iface_generate_hash_index_vxlan()
+ *	Calculate the hash index based on VxLAN network identifier and interface type.
+ */
+static inline ecm_db_iface_hash_t ecm_db_iface_generate_hash_index_vxlan(uint32_t vni, uint32_t if_type)
+{
+	uint32_t hash_val;
+	hash_val = (uint32_t)jhash_2words(vni, if_type, ecm_db_jhash_rnd);
+	return (ecm_db_iface_hash_t)(hash_val & (ECM_DB_IFACE_HASH_SLOTS - 1));
+}
+#endif
+
+/*
+ * ecm_db_iface_ethernet_address_get()
+ *	Obtain the ethernet address for an ethernet interface
+ */
+void ecm_db_iface_ethernet_address_get(struct ecm_db_iface_instance *ii, uint8_t *address)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	DEBUG_ASSERT(ii->type == ECM_DB_IFACE_TYPE_ETHERNET, "%px: Bad type, expected ethernet, actual: %d\n", ii, ii->type);
+	spin_lock_bh(&ecm_db_lock);
+	ether_addr_copy(address, ii->type_info.ethernet.address);
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_iface_ethernet_address_get);
+
+/*
+ * ecm_db_iface_bridge_address_get()
+ *	Obtain the ethernet address for a bridge interface
+ */
+void ecm_db_iface_bridge_address_get(struct ecm_db_iface_instance *ii, uint8_t *address)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	DEBUG_ASSERT(ii->type == ECM_DB_IFACE_TYPE_BRIDGE, "%px: Bad type, expected bridge, actual: %d\n", ii, ii->type);
+	spin_lock_bh(&ecm_db_lock);
+	ether_addr_copy(address, ii->type_info.bridge.address);
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_iface_bridge_address_get);
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+/*
+ * ecm_db_iface_ovs_bridge_address_get()
+ *	Obtain the ethernet address for a ovs bridge interface
+ */
+void ecm_db_iface_ovs_bridge_address_get(struct ecm_db_iface_instance *ii, uint8_t *address)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	DEBUG_ASSERT(ii->type == ECM_DB_IFACE_TYPE_OVS_BRIDGE, "%px: Bad type, expected ovs bridge, actual: %d\n", ii, ii->type);
+	spin_lock_bh(&ecm_db_lock);
+	ether_addr_copy(address, ii->type_info.ovsb.address);
+	spin_unlock_bh(&ecm_db_lock);
+}
+#endif
+
+#ifdef ECM_INTERFACE_BOND_ENABLE
+/*
+ * ecm_db_iface_lag_address_get()
+ *	Obtain the ethernet address for a LAG interface
+ */
+void ecm_db_iface_lag_address_get(struct ecm_db_iface_instance *ii, uint8_t *address)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	DEBUG_ASSERT(ii->type == ECM_DB_IFACE_TYPE_LAG, "%px: Bad type, expected LAG, actual: %d\n", ii, ii->type);
+	spin_lock_bh(&ecm_db_lock);
+	ether_addr_copy(address, ii->type_info.lag.address);
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_iface_lag_address_get);
+#endif
+
+/*
+ * _ecm_db_iface_identifier_hash_table_insert_entry()
+ *	Calculate the hash index based on updated interface_identifier, and
+ *	re-insert into interface identifier chain.
+ *
+ *	Note: Must take ecm_db_lock before calling this.
+ */
+static void _ecm_db_iface_identifier_hash_table_insert_entry(struct ecm_db_iface_instance *ii, int32_t interface_identifier)
+{
+	ecm_db_iface_id_hash_t iface_id_hash_index;
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	iface_id_hash_index = ecm_db_iface_id_generate_hash_index(interface_identifier);
+	ii->iface_id_hash_index = iface_id_hash_index;
+
+	/*
+	 * Insert into interface identifier chain
+	 */
+	ii->iface_id_hash_next = ecm_db_iface_id_table[iface_id_hash_index];
+	if (ecm_db_iface_id_table[iface_id_hash_index]) {
+		ecm_db_iface_id_table[iface_id_hash_index]->iface_id_hash_prev = ii;
+	}
+
+	ecm_db_iface_id_table[iface_id_hash_index] = ii;
+	ecm_db_iface_id_table_lengths[iface_id_hash_index]++;
+	DEBUG_ASSERT(ecm_db_iface_id_table_lengths[iface_id_hash_index] > 0, "%px: invalid iface id table len %d\n", ii, ecm_db_iface_id_table_lengths[iface_id_hash_index]);
+}
+
+/*
+ * _ecm_db_iface_identifier_hash_table_remove_entry()
+ * 	Remove an entry of a given interface instance from interface identifier chain.
+ *
+ *	Note: Must take ecm_db_lock before calling this.
+ */
+static void _ecm_db_iface_identifier_hash_table_remove_entry(struct ecm_db_iface_instance *ii)
+{
+	/*
+	 * Remove from database if inserted
+	 */
+	if (!ii->flags & ECM_DB_IFACE_FLAGS_INSERTED) {
+		return;
+	}
+
+	/*
+	 * Link out of interface identifier hash table
+	 */
+	if (!ii->iface_id_hash_prev) {
+		DEBUG_ASSERT(ecm_db_iface_id_table[ii->iface_id_hash_index] == ii, "%px: hash table bad got %px for hash index %u\n", ii, ecm_db_iface_id_table[ii->iface_id_hash_index], ii->iface_id_hash_index);
+		ecm_db_iface_id_table[ii->iface_id_hash_index] = ii->iface_id_hash_next;
+	} else {
+		ii->iface_id_hash_prev->iface_id_hash_next = ii->iface_id_hash_next;
+	}
+
+	if (ii->iface_id_hash_next) {
+		ii->iface_id_hash_next->iface_id_hash_prev = ii->iface_id_hash_prev;
+	}
+
+	ii->iface_id_hash_next = NULL;
+	ii->iface_id_hash_prev = NULL;
+	ecm_db_iface_id_table_lengths[ii->iface_id_hash_index]--;
+	DEBUG_ASSERT(ecm_db_iface_id_table_lengths[ii->iface_id_hash_index] >= 0, "%px: invalid table len %d\n", ii, ecm_db_iface_id_table_lengths[ii->iface_id_hash_index]);
+}
+
+/*
+ * ecm_db_iface_identifier_hash_table_entry_check_and_update()
+ * 	Update the hash table entry of interface identifier hash table.
+ * 	First remove the 'ii' from curent hash index position, re-calculate new hash and re-insert
+ * 	the 'ii' at new hash index position into interface identifier hash table.
+ */
+void ecm_db_iface_identifier_hash_table_entry_check_and_update(struct ecm_db_iface_instance *ii, int32_t new_interface_identifier)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	spin_lock_bh(&ecm_db_lock);
+	if (ii->interface_identifier == new_interface_identifier) {
+		spin_unlock_bh(&ecm_db_lock);
+		return;
+	}
+
+	DEBUG_TRACE("%px: interface ifindex has changed Old %d, New %d \n", ii, ii->interface_identifier, new_interface_identifier);
+	_ecm_db_iface_identifier_hash_table_remove_entry(ii);
+	ii->interface_identifier = new_interface_identifier;
+	_ecm_db_iface_identifier_hash_table_insert_entry(ii, new_interface_identifier);
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_iface_identifier_hash_table_entry_check_and_update);
+
+/*
+ * ecm_db_iface_find_and_ref_by_interface_identifier()
+ *	Return an interface based on a hlos interface identifier
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_by_interface_identifier(int32_t interface_id)
+{
+	ecm_db_iface_id_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup database iface with interface_id %d\n", interface_id);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_id_generate_hash_index(interface_id);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_id_table[hash_index];
+	while (ii) {
+		if (ii->interface_identifier == interface_id) {
+			_ecm_db_iface_ref(ii);
+			spin_unlock_bh(&ecm_db_lock);
+			DEBUG_TRACE("iface found %px\n", ii);
+			return ii;
+		}
+
+		/*
+		 * Try next
+		 */
+		ii = ii->iface_id_hash_next;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_by_interface_identifier);
+
+/*
+ * ecm_db_iface_ifidx_find_and_ref_ethernet()
+ *	Return an interface based on a MAC address and interface hlos interface identifier
+ */
+struct ecm_db_iface_instance *ecm_db_iface_ifidx_find_and_ref_ethernet(uint8_t *address, int32_t ifidx)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup ethernet iface with addr %pM\n", address);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ethernet(address);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_ETHERNET)
+		    || memcmp(ii->type_info.ethernet.address, address, ETH_ALEN)
+		    || ii->interface_identifier != ifidx) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_ifidx_find_and_ref_ethernet);
+
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+/*
+ * ecm_db_iface_vlan_info_get()
+ *	Get vlan interface specific information
+ */
+void ecm_db_iface_vlan_info_get(struct ecm_db_iface_instance *ii, struct ecm_db_interface_info_vlan *vlan_info)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	DEBUG_ASSERT(ii->type == ECM_DB_IFACE_TYPE_VLAN, "%px: Bad type, expected vlan, actual: %d\n", ii, ii->type);
+	spin_lock_bh(&ecm_db_lock);
+	ether_addr_copy(vlan_info->address, ii->type_info.vlan.address);
+	vlan_info->vlan_tag = ii->type_info.vlan.vlan_tag;
+	vlan_info->vlan_tpid = ii->type_info.vlan.vlan_tpid;
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_iface_vlan_info_get);
+
+/*
+ * ecm_db_iface_find_and_ref_vlan()
+ *	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_vlan(uint8_t *address, uint16_t vlan_tag, uint16_t vlan_tpid)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup vlan iface with addr %pM, vlan tag: %x vlan tpid: %x\n", address, vlan_tag, vlan_tpid);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ethernet(address);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_VLAN) || (ii->type_info.vlan.vlan_tag != vlan_tag)
+				|| (ii->type_info.vlan.vlan_tpid != vlan_tpid)
+				|| memcmp(ii->type_info.vlan.address, address, ETH_ALEN)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_vlan);
+#endif
+
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+/*
+ * ecm_db_iface_find_and_ref_macvlan()
+ *	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_macvlan(uint8_t *address)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup macvlan iface with addr %pM\n", address);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ethernet(address);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_MACVLAN) || !ether_addr_equal(ii->type_info.macvlan.address, address)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+
+/*
+ * ecm_db_iface_macvlan_address_get()
+ *	Obtain the ethernet address for a macvlan interface
+ */
+void ecm_db_iface_macvlan_address_get(struct ecm_db_iface_instance *ii, uint8_t *address)
+{
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	DEBUG_ASSERT(ii->type == ECM_DB_IFACE_TYPE_MACVLAN, "%px: Bad type, expected macvlan, actual: %d\n", ii, ii->type);
+	ether_addr_copy(address, ii->type_info.macvlan.address);
+	spin_unlock_bh(&ecm_db_lock);
+}
+#endif
+
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+/*
+ * ecm_db_iface_find_and_ref_vxlan()
+ *	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_vxlan(uint32_t vni, uint32_t type)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup vxlan iface with vxlan id: %d & if_type: %d\n", vni, type);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_vxlan(vni, type);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_VXLAN)
+			|| (ii->type_info.vxlan.vni != vni)
+			|| (ii->type_info.vxlan.if_type != type)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+#endif
+
+/*
+ * ecm_db_iface_find_and_ref_bridge()
+ *	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_bridge(uint8_t *address, int32_t if_num)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup bridge iface with addr %pM\n", address);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ethernet(address);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_BRIDGE)
+			|| memcmp(ii->type_info.bridge.address, address, ETH_ALEN)
+			|| ii->interface_identifier != if_num) {
+
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_bridge);
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+/*
+ * ecm_db_iface_find_and_ref_ovs_bridge()
+ *	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_ovs_bridge(uint8_t *address, int32_t if_num)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup OVS bridge iface with addr %pM\n", address);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ethernet(address);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_OVS_BRIDGE)
+			|| memcmp(ii->type_info.ovsb.address, address, ETH_ALEN)
+			|| (ii->interface_identifier != if_num)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+#endif
+
+#ifdef ECM_INTERFACE_BOND_ENABLE
+/*
+ * ecm_db_iface_find_and_ref_lag()
+ *	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_lag(uint8_t *address)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup lag iface with addr %pM\n", address);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ethernet(address);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_LAG) || memcmp(ii->type_info.lag.address, address, ETH_ALEN)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_lag);
+#endif
+
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+/*
+ * ecm_db_iface_pppoe_session_info_get()
+ *	Get pppoe interface specific information
+ */
+void ecm_db_iface_pppoe_session_info_get(struct ecm_db_iface_instance *ii, struct ecm_db_interface_info_pppoe *pppoe_info)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	DEBUG_ASSERT(ii->type == ECM_DB_IFACE_TYPE_PPPOE, "%px: Bad type, expected pppoe, actual: %d\n", ii, ii->type);
+	spin_lock_bh(&ecm_db_lock);
+	ether_addr_copy(pppoe_info->remote_mac, ii->type_info.pppoe.remote_mac);
+	pppoe_info->pppoe_session_id = ii->type_info.pppoe.pppoe_session_id;
+	spin_unlock_bh(&ecm_db_lock);
+}
+
+EXPORT_SYMBOL(ecm_db_iface_pppoe_session_info_get);
+
+/*
+ * ecm_db_iface_find_and_ref_pppoe()
+ *	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_pppoe(uint16_t pppoe_session_id, uint8_t *remote_mac)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup pppoe iface with addr %x\n", pppoe_session_id);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_pppoe(pppoe_session_id);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_PPPOE)
+				|| (ii->type_info.pppoe.pppoe_session_id != pppoe_session_id)
+				|| memcmp(ii->type_info.pppoe.remote_mac, remote_mac, ETH_ALEN)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_pppoe);
+#endif
+
+/*
+ * ecm_db_iface_update_ae_interface_identifier()
+ *	update ae_interface_identifier in iface instance.
+ */
+void ecm_db_iface_update_ae_interface_identifier(struct ecm_db_iface_instance *ii, int32_t ae_interface_identifier)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+
+	spin_lock_bh(&ecm_db_lock);
+	if (ii->ae_interface_identifier == ae_interface_identifier) {
+		spin_unlock_bh(&ecm_db_lock);
+		return;
+	}
+	ii->ae_interface_identifier = ae_interface_identifier;
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_iface_update_ae_interface_identifier);
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+/*
+ * ecm_db_iface_pppol2tpv2_session_info_get
+ *	get l2tpv2 specific info
+ */
+void ecm_db_iface_pppol2tpv2_session_info_get(struct ecm_db_iface_instance *ii, struct ecm_db_interface_info_pppol2tpv2 *pppol2tpv2_info)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	DEBUG_ASSERT(ii->type == ECM_DB_IFACE_TYPE_PPPOL2TPV2, "%px: Bad type, expected pppol2tpv2, actual: %d\n", ii, ii->type);
+	spin_lock_bh(&ecm_db_lock);
+	memcpy(pppol2tpv2_info, &ii->type_info.pppol2tpv2, sizeof(struct ecm_db_interface_info_pppol2tpv2));
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_iface_pppol2tpv2_session_info_get);
+
+/*
+ * ecm_db_iface_find_and_ref_pppol2tpv2()
+ *	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_pppol2tpv2(uint32_t pppol2tpv2_tunnel_id, uint32_t pppol2tpv2_session_id)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_pppol2tpv2(pppol2tpv2_tunnel_id, pppol2tpv2_session_id);
+
+	DEBUG_TRACE("Lookup pppol2tpv2 iface with local_tunnel_id = %d, local_session_id = %d, hash = 0x%x\n", pppol2tpv2_tunnel_id,
+									pppol2tpv2_session_id, hash_index);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_PPPOL2TPV2)
+				|| (ii->type_info.pppol2tpv2.l2tp.session.session_id != pppol2tpv2_session_id)
+				|| (ii->type_info.pppol2tpv2.l2tp.tunnel.tunnel_id != pppol2tpv2_tunnel_id)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_pppol2tpv2);
+
+#endif
+
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+/*
+ * ecm_db_iface_pptp_session_info_get
+ *	get pptp specific info
+ */
+void ecm_db_iface_pptp_session_info_get(struct ecm_db_iface_instance *ii, struct ecm_db_interface_info_pptp *pptp_info)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	DEBUG_ASSERT(ii->type == ECM_DB_IFACE_TYPE_PPTP, "%px: Bad type, expected pptp, actual: %d\n", ii, ii->type);
+	spin_lock_bh(&ecm_db_lock);
+	memcpy(pptp_info, &ii->type_info.pptp, sizeof(struct ecm_db_interface_info_pptp));
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_iface_pptp_session_info_get);
+
+/*
+ * ecm_db_iface_find_and_ref_pptp()
+ *	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_pptp(uint32_t pptp_src_call_id, uint32_t pptp_dst_call_id, int32_t ae_interface_num)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_pptp(pptp_src_call_id, pptp_dst_call_id);
+
+	DEBUG_TRACE("Lookup pptp iface with local_call_id = %d, remote_call_id = %d, hash = 0x%x\n", pptp_src_call_id,
+									pptp_dst_call_id, hash_index);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_PPTP)
+				|| (ii->type_info.pptp.src_call_id != pptp_src_call_id)
+				|| (ii->type_info.pptp.dst_call_id != pptp_dst_call_id)
+				|| (ii->ae_interface_identifier != ae_interface_num)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_pptp);
+#endif
+
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+/*
+ * ecm_db_iface_map_t_info_get
+ *	get map_t specific info
+ */
+void ecm_db_iface_map_t_info_get(struct ecm_db_iface_instance *ii, struct ecm_db_interface_info_map_t *map_t_info)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	DEBUG_ASSERT(ii->type == ECM_DB_IFACE_TYPE_MAP_T, "%px: Bad type, expected map_t, actual: %d\n", ii, ii->type);
+	spin_lock_bh(&ecm_db_lock);
+	memcpy(map_t_info, &ii->type_info.map_t, sizeof(struct ecm_db_interface_info_map_t));
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_iface_map_t_info_get);
+
+/*
+ * ecm_db_iface_find_and_ref_map_t()
+ *	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_map_t(int if_index, int32_t ae_interface_num)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup map_t iface with if_index = %d\n", if_index);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_map_t(if_index);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_MAP_T)
+				|| (ii->type_info.map_t.if_index != if_index)
+				|| (ii->ae_interface_identifier != ae_interface_num)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("%px: iface found\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_map_t);
+
+#endif
+
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+/*
+ * ecm_db_iface_gre_tun_info_get
+ * 	Get gre specific info
+ */
+void ecm_db_iface_gre_tun_info_get(struct ecm_db_iface_instance *ii, struct ecm_db_interface_info_gre_tun *gre_tun_info)
+{
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+	DEBUG_ASSERT(ii->type == ECM_DB_IFACE_TYPE_GRE_TUN, "%px: Bad type, expected gre, actual: %d\
+			n", ii, ii->type);
+	spin_lock_bh(&ecm_db_lock);
+	memcpy(gre_tun_info, &ii->type_info.gre_tun, sizeof(struct ecm_db_interface_info_gre_tun));
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_iface_gre_tun_info_get);
+
+/*
+ * ecm_db_iface_find_and_ref_gre()
+ * 	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_gre_tun(int if_index, int32_t ae_interface_num)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup gre iface with if_index = %d\n", if_index);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_gre_tun(if_index);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_GRE_TUN)
+				|| (ii->type_info.gre_tun.if_index != if_index)
+				|| (ii->ae_interface_identifier != ae_interface_num)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("%px: iface found\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_gre_tun);
+
+#endif
+/*
+ * ecm_db_iface_find_and_ref_unknown()
+ *	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_unknown(uint32_t os_specific_ident)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup unknown iface with addr %x (%u)\n", os_specific_ident, os_specific_ident);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_unknown(os_specific_ident);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_UNKNOWN) || (ii->type_info.unknown.os_specific_ident != os_specific_ident)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_unknown);
+
+/*
+ * ecm_db_iface_find_and_ref_loopback()
+ *	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_loopback(uint32_t os_specific_ident)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup loopback iface with addr %x (%u)\n", os_specific_ident, os_specific_ident);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_loopback(os_specific_ident);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_LOOPBACK) || (ii->type_info.loopback.os_specific_ident != os_specific_ident)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_loopback);
+
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+/*
+ * ecm_db_iface_find_and_ref_ipsec_tunnel()
+ *	Lookup and return a iface reference if any.
+ * GGG TODO Flesh this out using tunnel endpoint keys
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_ipsec_tunnel(uint32_t os_specific_ident, int32_t ae_interface_num)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup ipsec_tunnel iface with addr %x (%u)\n", os_specific_ident, os_specific_ident);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ipsec_tunnel(os_specific_ident);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_IPSEC_TUNNEL)
+				|| (ii->type_info.ipsec_tunnel.os_specific_ident != os_specific_ident)
+				|| (ii->ae_interface_identifier != ae_interface_num)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_ipsec_tunnel);
+#endif
+
+#ifdef ECM_INTERFACE_SIT_ENABLE
+/*
+ * ecm_db_iface_find_and_ref_sit()
+ *	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_sit(ip_addr_t saddr, ip_addr_t daddr, int32_t ae_interface_num)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup sit (6-in-4) iface with saddr: " ECM_IP_ADDR_OCTAL_FMT ", daddr: " ECM_IP_ADDR_OCTAL_FMT "\n",
+			ECM_IP_ADDR_TO_OCTAL(saddr), ECM_IP_ADDR_TO_OCTAL(daddr));
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_sit(saddr, daddr);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_SIT)
+				|| !ECM_IP_ADDR_MATCH(ii->type_info.sit.saddr, saddr)
+				|| !ECM_IP_ADDR_MATCH(ii->type_info.sit.daddr, daddr)
+				|| (ii->ae_interface_identifier != ae_interface_num)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_sit);
+#endif
+
+#ifdef ECM_INTERFACE_TUNIPIP6_ENABLE
+#ifdef ECM_IPV6_ENABLE
+/*
+ * ecm_db_iface_find_and_ref_tunipip6()
+ *	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_tunipip6(ip_addr_t saddr, ip_addr_t daddr, int32_t ae_interface_num)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup TUNIPIP6 iface with saddr: " ECM_IP_ADDR_OCTAL_FMT ", daddr: " ECM_IP_ADDR_OCTAL_FMT "\n",
+			ECM_IP_ADDR_TO_OCTAL(saddr), ECM_IP_ADDR_TO_OCTAL(daddr));
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_tunipip6(saddr, daddr);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_TUNIPIP6)
+			|| !ECM_IP_ADDR_MATCH(ii->type_info.tunipip6.saddr, saddr)
+			|| !ECM_IP_ADDR_MATCH(ii->type_info.tunipip6.daddr, daddr)
+			|| (ii->ae_interface_identifier != ae_interface_num)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_tunipip6);
+#endif
+#endif
+
+#ifdef ECM_INTERFACE_RAWIP_ENABLE
+/*
+ * ecm_db_iface_find_and_ref_rawip()
+ *	Lookup and return a iface reference if any
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_rawip(uint8_t *address)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup RAWIP iface with addr %pM\n", address);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 * We can use the same hash function of ethernet interface.
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ethernet(address);
+
+	/*
+	 * Iterate the chain looking for an iface with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_RAWIP)
+		    || memcmp(ii->type_info.rawip.address, address, ETH_ALEN)) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("%px: RAWIP iface found\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("RAWIP iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_rawip);
+#endif
+
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+/*
+ * ecm_db_iface_find_and_ref_ovpn()
+ *	Lookup and return OVPN iface reference
+ */
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_ovpn(int32_t tun_ifnum)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Lookup OVPN iface with ifnum: %d\n", tun_ifnum);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ovpn(tun_ifnum);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii = ecm_db_iface_table[hash_index];
+	while (ii) {
+		if ((ii->type != ECM_DB_IFACE_TYPE_OVPN)
+				|| ii->type_info.ovpn.tun_ifnum != tun_ifnum) {
+			ii = ii->hash_next;
+			continue;
+		}
+
+		_ecm_db_iface_ref(ii);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("iface found %px\n", ii);
+		return ii;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Iface not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_iface_find_and_ref_ovpn);
+#endif
+
+#ifdef ECM_DB_XREF_ENABLE
+/*
+ * ecm_db_iface_connections_get_and_ref_first()
+ *	Return a reference to the first connection made for this iface on the specified direction.
+ */
+struct ecm_db_connection_instance *
+ecm_db_iface_connections_get_and_ref_first(struct ecm_db_iface_instance *ii,
+					   ecm_db_obj_dir_t dir)
+{
+	struct ecm_db_connection_instance *ci;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+
+	spin_lock_bh(&ecm_db_lock);
+	ci = ii->connections[dir];
+	if (ci) {
+		_ecm_db_connection_ref(ci);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	return ci;
+}
+EXPORT_SYMBOL(ecm_db_iface_connections_get_and_ref_first);
+
+/*
+ * ecm_db_iface_nodes_get_and_ref_first()
+ *	Return a reference to the first node made from this iface
+ */
+struct ecm_db_node_instance *ecm_db_iface_nodes_get_and_ref_first(struct ecm_db_iface_instance *ii)
+{
+	struct ecm_db_node_instance *ni;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed", ii);
+
+	spin_lock_bh(&ecm_db_lock);
+	ni = ii->nodes;
+	if (ni) {
+		_ecm_db_node_ref(ni);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	return ni;
+}
+EXPORT_SYMBOL(ecm_db_iface_nodes_get_and_ref_first);
+
+/*
+ * ecm_db_iface_node_count_get()
+ *	Return the number of nodes to this iface
+ */
+int ecm_db_iface_node_count_get(struct ecm_db_iface_instance *ii)
+{
+	int count;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+
+	spin_lock_bh(&ecm_db_lock);
+	count = ii->node_count;
+	spin_unlock_bh(&ecm_db_lock);
+	return count;
+}
+EXPORT_SYMBOL(ecm_db_iface_node_count_get);
+#endif
+
+/*
+ * ecm_db_iface_add_to_db()
+ *	Adds the created iface to the database lists.
+ */
+static inline void ecm_db_iface_add_to_db(struct ecm_db_iface_instance *ii,  ecm_db_iface_hash_t hash_index)
+{
+	ecm_db_iface_id_hash_t iface_id_hash_index;
+	struct ecm_db_listener_instance *li;
+
+	ii->hash_index = hash_index;
+
+	iface_id_hash_index = ecm_db_iface_id_generate_hash_index(ii->interface_identifier);
+	ii->iface_id_hash_index = iface_id_hash_index;
+
+	/*
+	 * Add into the global list
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ii->flags |= ECM_DB_IFACE_FLAGS_INSERTED;
+	ii->prev = NULL;
+	ii->next = ecm_db_interfaces;
+	if (ecm_db_interfaces) {
+		ecm_db_interfaces->prev = ii;
+	}
+	ecm_db_interfaces = ii;
+
+	/*
+	 * Insert into chain
+	 */
+	ii->hash_prev = NULL;
+	ii->hash_next = ecm_db_iface_table[hash_index];
+	if (ecm_db_iface_table[hash_index]) {
+		ecm_db_iface_table[hash_index]->hash_prev = ii;
+	}
+	ecm_db_iface_table[hash_index] = ii;
+	ecm_db_iface_table_lengths[hash_index]++;
+	DEBUG_ASSERT(ecm_db_iface_table_lengths[hash_index] > 0, "%px: invalid table len %d\n", ii, ecm_db_iface_table_lengths[hash_index]);
+
+	DEBUG_INFO("%px: interface inserted at hash index %u, hash prev is %px, type: %d\n", ii, ii->hash_index, ii->hash_prev, ii->type);
+
+	/*
+	 * Insert into interface identifier chain
+	 */
+	ii->iface_id_hash_prev = NULL;
+	ii->iface_id_hash_next = ecm_db_iface_id_table[iface_id_hash_index];
+	if (ecm_db_iface_id_table[iface_id_hash_index]) {
+		ecm_db_iface_id_table[iface_id_hash_index]->iface_id_hash_prev = ii;
+	}
+	ecm_db_iface_id_table[iface_id_hash_index] = ii;
+	ecm_db_iface_id_table_lengths[iface_id_hash_index]++;
+	DEBUG_ASSERT(ecm_db_iface_id_table_lengths[iface_id_hash_index] > 0, "%px: invalid iface id table len %d\n", ii, ecm_db_iface_id_table_lengths[iface_id_hash_index]);
+
+	/*
+	 * Set time of addition
+	 */
+	ii->time_added = ecm_db_time;
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Throw add event to the listeners
+	 */
+	DEBUG_TRACE("%px: Throw iface added event\n", ii);
+	li = ecm_db_listeners_get_and_ref_first();
+	while (li) {
+		struct ecm_db_listener_instance *lin;
+		if (li->iface_added) {
+			li->iface_added(li->arg, ii);
+		}
+
+		/*
+		 * Get next listener
+		 */
+		lin = ecm_db_listener_get_and_ref_next(li);
+		ecm_db_listener_deref(li);
+		li = lin;
+	}
+}
+
+/*
+ * ecm_db_iface_add_ethernet()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_ethernet(struct ecm_db_iface_instance *ii, uint8_t *address, char *name, int32_t mtu,
+					int32_t interface_identifier, int32_t ae_interface_identifier,
+					ecm_db_iface_final_callback_t final, void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_ethernet *type_info;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	DEBUG_ASSERT(address, "%px: address null\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_ETHERNET;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_ethernet_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.ethernet;
+	memcpy(type_info->address, address, ETH_ALEN);
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ethernet(address);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+
+}
+EXPORT_SYMBOL(ecm_db_iface_add_ethernet);
+
+#ifdef ECM_INTERFACE_BOND_ENABLE
+/*
+ * ecm_db_iface_add_lag()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_lag(struct ecm_db_iface_instance *ii, uint8_t *address, char *name, int32_t mtu,
+					int32_t interface_identifier, int32_t ae_interface_identifier,
+					ecm_db_iface_final_callback_t final, void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_lag *type_info;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	DEBUG_ASSERT(address, "%px: address null\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_LAG;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_lag_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.lag;
+	memcpy(type_info->address, address, ETH_ALEN);
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ethernet(address);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+EXPORT_SYMBOL(ecm_db_iface_add_lag);
+#endif
+
+/*
+ * ecm_db_iface_add_bridge()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_bridge(struct ecm_db_iface_instance *ii, uint8_t *address, char *name, int32_t mtu,
+					int32_t interface_identifier, int32_t ae_interface_identifier,
+					ecm_db_iface_final_callback_t final, void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_bridge *type_info;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	DEBUG_ASSERT(address, "%px: address null\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_BRIDGE;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_bridge_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.bridge;
+	memcpy(type_info->address, address, ETH_ALEN);
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ethernet(address);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+EXPORT_SYMBOL(ecm_db_iface_add_bridge);
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+/*
+ * ecm_db_iface_add_ovs_bridge()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_ovs_bridge(struct ecm_db_iface_instance *ii, uint8_t *address, char *name, int32_t mtu,
+					int32_t interface_identifier, int32_t ae_interface_identifier,
+					ecm_db_iface_final_callback_t final, void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_ovs_bridge *type_info;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	DEBUG_ASSERT(address, "%px: address null\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_OVS_BRIDGE;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_ovs_bridge_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.ovsb;
+	memcpy(type_info->address, address, ETH_ALEN);
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ethernet(address);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+#endif
+
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+/*
+ * ecm_db_iface_add_macvlan()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_macvlan(struct ecm_db_iface_instance *ii, uint8_t *address, char *name, int32_t mtu,
+					int32_t interface_identifier, int32_t ae_interface_identifier,
+					ecm_db_iface_final_callback_t final, void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_macvlan *type_info;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	DEBUG_ASSERT(address, "%px: address null\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_MACVLAN;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_macvlan_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.macvlan;
+	ether_addr_copy(type_info->address, address);
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ethernet(address);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+#endif
+
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+/*
+ * ecm_db_iface_add_vlan()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_vlan(struct ecm_db_iface_instance *ii, uint8_t *address, uint16_t vlan_tag, uint16_t vlan_tpid, char *name, int32_t mtu,
+					int32_t interface_identifier, int32_t ae_interface_identifier,
+					ecm_db_iface_final_callback_t final, void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_vlan *type_info;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	DEBUG_ASSERT(address, "%px: address null\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_VLAN;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_vlan_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.vlan;
+	type_info->vlan_tag = vlan_tag;
+	type_info->vlan_tpid = vlan_tpid;
+	memcpy(type_info->address, address, ETH_ALEN);
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ethernet(address);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+EXPORT_SYMBOL(ecm_db_iface_add_vlan);
+#endif
+
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+/*
+ * ecm_db_iface_add_map_t()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_map_t(struct ecm_db_iface_instance *ii, struct ecm_db_interface_info_map_t *map_t_info,
+					char *name, int32_t mtu, int32_t interface_identifier,
+					int32_t ae_interface_identifier, ecm_db_iface_final_callback_t final,
+					void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_map_t *type_info;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_MAP_T;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_map_t_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.map_t;
+	memcpy(type_info, map_t_info, sizeof(struct ecm_db_interface_info_map_t));
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_map_t(type_info->if_index);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+EXPORT_SYMBOL(ecm_db_iface_add_map_t);
+#endif
+
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+/*
+ * ecm_db_iface_add_gre_tun()
+ * 	Add a iface instance into the database
+ */
+void ecm_db_iface_add_gre_tun(struct ecm_db_iface_instance *ii, struct ecm_db_interface_info_gre_tun *gre_tun_info,
+				char *name, int32_t mtu, int32_t interface_identifier,
+				int32_t ae_interface_identifier, ecm_db_iface_final_callback_t final,
+				void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_gre_tun *type_info;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_GRE_TUN;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_gre_tun_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.gre_tun;
+	memcpy(type_info, gre_tun_info, sizeof(struct ecm_db_interface_info_gre_tun));
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_gre_tun(type_info->if_index);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+EXPORT_SYMBOL(ecm_db_iface_add_gre_tun);
+#endif
+
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+/*
+ * ecm_db_iface_add_pppoe()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_pppoe(struct ecm_db_iface_instance *ii, uint16_t pppoe_session_id, uint8_t *remote_mac,
+					char *name, int32_t mtu, int32_t interface_identifier,
+					int32_t ae_interface_identifier, ecm_db_iface_final_callback_t final,
+					void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_pppoe *type_info;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_PPPOE;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_pppoe_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.pppoe;
+	type_info->pppoe_session_id = pppoe_session_id;
+	memcpy(type_info->remote_mac, remote_mac, ETH_ALEN);
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_pppoe(pppoe_session_id);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+EXPORT_SYMBOL(ecm_db_iface_add_pppoe);
+#endif
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+/*
+ * ecm_db_iface_add_pppol2tpv2()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_pppol2tpv2(struct ecm_db_iface_instance *ii, struct ecm_db_interface_info_pppol2tpv2 *pppol2tpv2_info,
+					char *name, int32_t mtu, int32_t interface_identifier,
+					int32_t ae_interface_identifier, ecm_db_iface_final_callback_t final,
+					void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_pppol2tpv2 *type_info;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_PPPOL2TPV2;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_pppol2tpv2_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.pppol2tpv2;
+	memcpy(type_info, pppol2tpv2_info, sizeof(struct ecm_db_interface_info_pppol2tpv2));
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_pppol2tpv2(type_info->l2tp.tunnel.tunnel_id,
+							  type_info->l2tp.session.session_id);
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+EXPORT_SYMBOL(ecm_db_iface_add_pppol2tpv2);
+
+#endif
+
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+/*
+ * ecm_db_iface_add_pptp()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_pptp(struct ecm_db_iface_instance *ii, struct ecm_db_interface_info_pptp *pptp_info,
+					char *name, int32_t mtu, int32_t interface_identifier,
+					int32_t ae_interface_identifier, ecm_db_iface_final_callback_t final,
+					void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_pptp *type_info;
+
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	spin_lock_bh(&ecm_db_lock);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_PPTP;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_pptp_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.pptp;
+	memcpy(type_info, pptp_info, sizeof(struct ecm_db_interface_info_pptp));
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_pptp(type_info->src_call_id,
+							  type_info->dst_call_id);
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+EXPORT_SYMBOL(ecm_db_iface_add_pptp);
+#endif
+
+/*
+ * ecm_db_iface_add_unknown()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_unknown(struct ecm_db_iface_instance *ii, uint32_t os_specific_ident, char *name, int32_t mtu,
+					int32_t interface_identifier, int32_t ae_interface_identifier,
+					ecm_db_iface_final_callback_t final, void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_unknown *type_info;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_UNKNOWN;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_unknown_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.unknown;
+	type_info->os_specific_ident = os_specific_ident;
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_unknown(os_specific_ident);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+EXPORT_SYMBOL(ecm_db_iface_add_unknown);
+
+/*
+ * ecm_db_iface_add_loopback()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_loopback(struct ecm_db_iface_instance *ii, uint32_t os_specific_ident, char *name, int32_t mtu,
+					int32_t interface_identifier, int32_t ae_interface_identifier,
+					ecm_db_iface_final_callback_t final, void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_loopback *type_info;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_LOOPBACK;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_loopback_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.loopback;
+	type_info->os_specific_ident = os_specific_ident;
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_loopback(os_specific_ident);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+EXPORT_SYMBOL(ecm_db_iface_add_loopback);
+
+#ifdef ECM_INTERFACE_SIT_ENABLE
+/*
+ * ecm_db_iface_sit_daddr_is_null()
+ *	The sit addr is null or not
+ */
+bool ecm_db_iface_sit_daddr_is_null(struct ecm_db_iface_instance *ii)
+{
+	return ii->type_info.sit.daddr[0] == 0;
+}
+EXPORT_SYMBOL(ecm_db_iface_sit_daddr_is_null);
+
+/*
+ * ecm_db_iface_add_sit()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_sit(struct ecm_db_iface_instance *ii, struct ecm_db_interface_info_sit *type_info, char *name, int32_t mtu,
+					int32_t interface_identifier, int32_t ae_interface_identifier,
+					ecm_db_iface_final_callback_t final, void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_SIT;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_sit_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info to be copied
+	 */
+	ii->type_info.sit = *type_info;
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_sit(type_info->saddr, type_info->daddr);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+EXPORT_SYMBOL(ecm_db_iface_add_sit);
+#endif
+
+#ifdef ECM_INTERFACE_TUNIPIP6_ENABLE
+#ifdef ECM_IPV6_ENABLE
+/*
+ * ecm_db_iface_add_tunipip6()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_tunipip6(struct ecm_db_iface_instance *ii, struct ecm_db_interface_info_tunipip6 *type_info, char *name, int32_t mtu,
+					int32_t interface_identifier, int32_t ae_interface_identifier,
+					ecm_db_iface_final_callback_t final, void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_TUNIPIP6;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_tunipip6_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info to be copied
+	 */
+	ii->type_info.tunipip6 = *type_info;
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_tunipip6(type_info->saddr, type_info->daddr);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+EXPORT_SYMBOL(ecm_db_iface_add_tunipip6);
+#endif
+#endif
+
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+/*
+ * ecm_db_iface_add_ipsec_tunnel()
+ *	Add a iface instance into the database
+ *
+ * GGG TODO This needs to take ipsec tunnel endpoint information etc. something very appropriate for ipsec tunnels, anyhow.
+ */
+void ecm_db_iface_add_ipsec_tunnel(struct ecm_db_iface_instance *ii, uint32_t os_specific_ident, char *name, int32_t mtu,
+					int32_t interface_identifier, int32_t ae_interface_identifier,
+					ecm_db_iface_final_callback_t final, void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_ipsec_tunnel *type_info;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_IPSEC_TUNNEL;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_ipsec_tunnel_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.ipsec_tunnel;
+	type_info->os_specific_ident = os_specific_ident;
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ipsec_tunnel(os_specific_ident);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+EXPORT_SYMBOL(ecm_db_iface_add_ipsec_tunnel);
+#endif
+
+#ifdef ECM_INTERFACE_RAWIP_ENABLE
+/*
+ * ecm_db_iface_add_rawip()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_rawip(struct ecm_db_iface_instance *ii, uint8_t *address, char *name, int32_t mtu,
+					int32_t interface_identifier, int32_t ae_interface_identifier,
+					ecm_db_iface_final_callback_t final, void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_rawip *type_info;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	DEBUG_ASSERT(address, "%px: address null\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_RAWIP;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_rawip_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.rawip;
+	memcpy(type_info->address, address, ETH_ALEN);
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ethernet(address);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+EXPORT_SYMBOL(ecm_db_iface_add_rawip);
+#endif
+
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+/*
+ * ecm_db_iface_add_ovpn()
+ *	Add OVPN interface instance into the database
+ */
+void ecm_db_iface_add_ovpn(struct ecm_db_iface_instance *ii,
+				struct ecm_db_interface_info_ovpn *type_info, char *name,
+				int32_t mtu, int32_t interface_identifier,
+				ecm_db_iface_final_callback_t final, void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_OVPN;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_ovpn_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = type_info->tun_ifnum;
+
+	/*
+	 * Type specific info to be copied
+	 */
+	ii->type_info.ovpn = *type_info;
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_ovpn(type_info->tun_ifnum);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+EXPORT_SYMBOL(ecm_db_iface_add_ovpn);
+#endif
+
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+/*
+ * ecm_db_iface_add_vxlan()
+ *	Add a iface instance into the database
+ */
+void ecm_db_iface_add_vxlan(struct ecm_db_iface_instance *ii, uint32_t vni, uint32_t if_type,
+					char *name, int32_t mtu, int32_t interface_identifier,
+					int32_t ae_interface_identifier,
+					ecm_db_iface_final_callback_t final, void *arg)
+{
+	ecm_db_iface_hash_t hash_index;
+	struct ecm_db_interface_info_vxlan *type_info;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT((ii->nodes == NULL) && (ii->node_count == 0), "%px: nodes not null\n", ii);
+#endif
+	DEBUG_ASSERT(!(ii->flags & ECM_DB_IFACE_FLAGS_INSERTED), "%px: inserted\n", ii);
+	DEBUG_ASSERT(name, "%px: no name given\n", ii);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Record general info
+	 */
+	ii->type = ECM_DB_IFACE_TYPE_VXLAN;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ii->state_get = ecm_db_iface_vxlan_state_get;
+#endif
+	ii->arg = arg;
+	ii->final = final;
+	strlcpy(ii->name, name, IFNAMSIZ);
+	ii->mtu = mtu;
+	ii->interface_identifier = interface_identifier;
+	ii->ae_interface_identifier = ae_interface_identifier;
+
+	/*
+	 * Type specific info
+	 */
+	type_info = &ii->type_info.vxlan;
+	type_info->vni = vni;
+	type_info->if_type = if_type;
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_iface_generate_hash_index_vxlan(vni, if_type);
+
+	ecm_db_iface_add_to_db(ii, hash_index);
+}
+#endif
+
+/*
+ * ecm_db_iface_alloc()
+ *	Allocate a iface instance
+ */
+struct ecm_db_iface_instance *ecm_db_iface_alloc(void)
+{
+	struct ecm_db_iface_instance *ii;
+
+	ii = (struct ecm_db_iface_instance *)kzalloc(sizeof(struct ecm_db_iface_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!ii) {
+		DEBUG_WARN("Alloc failed\n");
+		return NULL;
+	}
+
+	ii->refs = 1;
+	DEBUG_SET_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC);
+
+	/*
+	 * Alloc operation must be atomic to ensure thread and module can be held
+	 */
+	spin_lock_bh(&ecm_db_lock);
+
+	/*
+	 * If the event processing thread is terminating then we cannot create new instances
+	 */
+	if (ecm_db_terminate_pending) {
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_WARN("Thread terminating\n");
+		kfree(ii);
+		return NULL;
+	}
+
+	ecm_db_iface_count++;
+	spin_unlock_bh(&ecm_db_lock);
+
+	DEBUG_TRACE("iface created %px\n", ii);
+	return ii;
+}
+EXPORT_SYMBOL(ecm_db_iface_alloc);
+
+/*
+ * ecm_db_iface_init()
+ */
+bool ecm_db_iface_init(struct dentry *dentry)
+{
+	if (!debugfs_create_u32("iface_count", S_IRUGO, dentry,
+					(u32 *)&ecm_db_iface_count)) {
+		DEBUG_ERROR("Failed to create ecm db iface count file in debugfs\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-ecm/ecm_db/ecm_db_iface.h b/qca-nss-ecm/ecm_db/ecm_db_iface.h
new file mode 100644
index 0000000..32f8252
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_iface.h
@@ -0,0 +1,385 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * Maximum MTU value which can be set in ECM's connection rules.
+ */
+#define ECM_DB_IFACE_MTU_MAX 65535
+
+/*
+ * Magic number
+ */
+#define ECM_DB_IFACE_INSTANCE_MAGIC 0xAEF1
+
+typedef uint32_t ecm_db_iface_hash_t;
+typedef uint32_t ecm_db_iface_id_hash_t;
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_db_iface_state_get_method_t
+ *	Used to obtain interface state
+ */
+typedef int (*ecm_db_iface_state_get_method_t)(struct ecm_db_iface_instance *ii, struct ecm_state_file_instance *sfi);
+#endif
+
+/*
+ * struct ecm_db_iface_instance
+ */
+struct ecm_db_iface_instance {
+	struct ecm_db_iface_instance *next;		/* Next instance in global list */
+	struct ecm_db_iface_instance *prev;		/* Previous instance in global list */
+	struct ecm_db_iface_instance *hash_next;	/* Next Interface in the chain of Interfaces */
+	struct ecm_db_iface_instance *hash_prev;	/* previous Interface in the chain of Interfaces */
+	ecm_db_iface_type_t type;			/* RO: Type of interface */
+	uint32_t time_added;				/* RO: DB time stamp when the Interface was added into the database */
+
+	int32_t interface_identifier;			/* RO: The operating system dependent identifier of this interface */
+	int32_t ae_interface_identifier;		/* RO: The accel engine identifier of this interface */
+	char name[IFNAMSIZ];				/* Name of interface */
+	int32_t mtu;					/* Interface MTU */
+
+	struct ecm_db_iface_instance *iface_id_hash_next;	/* Next interface in the chain of interface id table */
+	struct ecm_db_iface_instance *iface_id_hash_prev;	/* Previous interface in the chain of interface id table */
+	ecm_db_iface_id_hash_t iface_id_hash_index;		/* Hash index value of chains */
+
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	uint64_t from_data_total;			/* Total of data sent by this Interface */
+	uint64_t to_data_total;				/* Total of data sent to this Interface */
+	uint64_t from_packet_total;			/* Total of packets sent by this Interface */
+	uint64_t to_packet_total;			/* Total of packets sent to this Interface */
+	uint64_t from_data_total_dropped;
+	uint64_t to_data_total_dropped;
+	uint64_t from_packet_total_dropped;
+	uint64_t to_packet_total_dropped;
+#endif
+
+#ifdef ECM_DB_XREF_ENABLE
+	/*
+	 * For convenience interfaces keep lists of connections that have been established
+	 * from them and to them.
+	 * In fact the same connection could be listed as from & to on the same interface (think: WLAN<>WLAN AP function)
+	 * Interfaces keep this information for rapid iteration of connections e.g. when an interface 'goes down' we
+	 * can defunct all associated connections or destroy any accel engine rules.
+	 */
+	struct ecm_db_connection_instance *connections[ECM_DB_OBJ_DIR_MAX];
+							/* list of connections made on this interface */
+
+	/*
+	 * Normally only the node refers to the interfaces which it is reachable upon.
+	 * The interface  also keeps a list of all nodes that can be reached.
+	 */
+	struct ecm_db_node_instance *nodes;				/* Nodes associated with this Interface */
+	int node_count;							/* Number of Nodes in the nodes list */
+#endif
+
+	/*
+	 * Interface specific information.
+	 * type identifies which information is applicable.
+	 */
+	union {
+		struct ecm_db_interface_info_ethernet ethernet;		/* type == ECM_DB_IFACE_TYPE_ETHERNET */
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan;			/* type == ECM_DB_IFACE_TYPE_VLAN */
+#endif
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+		struct ecm_db_interface_info_macvlan macvlan;		/* type == ECM_DB_IFACE_TYPE_MACVLAN */
+#endif
+#ifdef ECM_INTERFACE_BOND_ENABLE
+		struct ecm_db_interface_info_lag lag;			/* type == ECM_DB_IFACE_TYPE_LAG */
+#endif
+		struct ecm_db_interface_info_bridge bridge;		/* type == ECM_DB_IFACE_TYPE_BRIDGE */
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+		struct ecm_db_interface_info_pppoe pppoe;		/* type == ECM_DB_IFACE_TYPE_PPPOE */
+#endif
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+		struct ecm_db_interface_info_pppol2tpv2 pppol2tpv2;	/* type == ECM_DB_IFACE_TYPE_PPPOL2TPV2 */
+#endif
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+		struct ecm_db_interface_info_pptp pptp;			/* type == ECM_DB_IFACE_TYPE_PPTP */
+#endif
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+		struct ecm_db_interface_info_map_t map_t;		/* type == ECM_DB_IFACE_TYPE_MAP_T */
+#endif
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+		struct ecm_db_interface_info_gre_tun gre_tun;		/* type == ECM_DB_IFACE_TYPE_GRE_TUN */
+#endif
+		struct ecm_db_interface_info_unknown unknown;		/* type == ECM_DB_IFACE_TYPE_UNKNOWN */
+		struct ecm_db_interface_info_loopback loopback;		/* type == ECM_DB_IFACE_TYPE_LOOPBACK */
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+		struct ecm_db_interface_info_ipsec_tunnel ipsec_tunnel;	/* type == ECM_DB_IFACE_TYPE_IPSEC_TUNNEL */
+#endif
+#ifdef ECM_INTERFACE_SIT_ENABLE
+		struct ecm_db_interface_info_sit sit;			/* type == ECM_DB_IFACE_TYPE_SIT (6-in-4) */
+#endif
+#ifdef ECM_INTERFACE_TUNIPIP6_ENABLE
+#ifdef ECM_IPV6_ENABLE
+		struct ecm_db_interface_info_tunipip6 tunipip6;		/* type == ECM_DB_IFACE_TYPE_TUNIPIP6 (IPIP v6 Tunnel i.e. TUNNEL6) */
+#endif
+#endif
+#ifdef ECM_INTERFACE_RAWIP_ENABLE
+		struct ecm_db_interface_info_rawip rawip;		/* type ECM_DB_IFACE_TYPE_RAWIP */
+#endif
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+		struct ecm_db_interface_info_ovpn ovpn;			/* type == ECM_DB_IFACE_TYPE_OVPN (OpenVPN tunnel - data channel offload interface) */
+#endif
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+		struct ecm_db_interface_info_vxlan vxlan;			/* type == ECM_DB_IFACE_TYPE_VXLAN */
+#endif
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+		struct ecm_db_interface_info_ovs_bridge ovsb;			/* type == ECM_DB_IFACE_TYPE_OVS_BRIDGE */
+#endif
+	} type_info;
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ecm_db_iface_state_get_method_t state_get;	/* Type specific method to return state */
+#endif
+
+	ecm_db_iface_final_callback_t final;		/* Callback to owner when object is destroyed */
+	void *arg;					/* Argument returned to owner in callbacks */
+	uint32_t flags;
+	int refs;					/* Integer to trap we never go negative */
+	ecm_db_iface_hash_t hash_index;
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+int _ecm_db_iface_count_get(void);
+
+void _ecm_db_iface_ref(struct ecm_db_iface_instance *ii);
+void ecm_db_iface_ref(struct ecm_db_iface_instance *ii);
+int ecm_db_iface_deref(struct ecm_db_iface_instance *ii);
+
+int32_t ecm_db_iface_mtu_reset(struct ecm_db_iface_instance *ii, int32_t mtu);
+
+void ecm_db_iface_identifier_hash_table_entry_check_and_update(struct ecm_db_iface_instance *ii,
+							       int32_t new_interface_identifier);
+int32_t ecm_db_iface_ae_interface_identifier_get(struct ecm_db_iface_instance *ii);
+void ecm_db_iface_ae_interface_identifier_set(struct ecm_db_iface_instance *ii, uint32_t num);
+void ecm_db_iface_update_ae_interface_identifier(struct ecm_db_iface_instance *ii,
+						 int32_t ae_interface_identifier);
+
+int32_t ecm_db_iface_interface_identifier_get(struct ecm_db_iface_instance *ii);
+void ecm_db_iface_interface_name_get(struct ecm_db_iface_instance *ii, char *name_buffer);
+
+void ecm_db_iface_ethernet_address_get(struct ecm_db_iface_instance *ii, uint8_t *address);
+void ecm_db_iface_bridge_address_get(struct ecm_db_iface_instance *ii, uint8_t *address);
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+void ecm_db_iface_ovs_bridge_address_get(struct ecm_db_iface_instance *ii, uint8_t *address);
+#endif
+
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+void ecm_db_iface_pppoe_session_info_get(struct ecm_db_iface_instance *ii,
+					 struct ecm_db_interface_info_pppoe *pppoe_info);
+#endif
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+void ecm_db_iface_vlan_info_get(struct ecm_db_iface_instance *ii,
+				struct ecm_db_interface_info_vlan *vlan_info);
+#endif
+
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_by_interface_identifier(int32_t interface_id);
+struct ecm_db_iface_instance *ecm_db_iface_ifidx_find_and_ref_ethernet(uint8_t *address, int32_t idx);
+
+#ifdef ECM_INTERFACE_RAWIP_ENABLE
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_rawip(uint8_t *address);
+#endif
+
+#ifdef ECM_INTERFACE_BOND_ENABLE
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_lag(uint8_t *address);
+void ecm_db_iface_add_lag(struct ecm_db_iface_instance *ii,
+			  uint8_t *address, char *name, int32_t mtu,
+			  int32_t interface_identifier, int32_t ae_interface_identifier,
+			  ecm_db_iface_final_callback_t final, void *arg);
+void ecm_db_iface_lag_address_get(struct ecm_db_iface_instance *ii, uint8_t *address);
+#endif
+
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_vlan(uint8_t *address,
+							     uint16_t vlan_tag,
+							     uint16_t vlan_tpid);
+void ecm_db_iface_add_vlan(struct ecm_db_iface_instance *ii,
+			   uint8_t *address, uint16_t vlan_tag, uint16_t vlan_tpid,
+			   char *name, int32_t mtu, int32_t interface_identifier,
+			   int32_t ae_interface_identifier,
+			   ecm_db_iface_final_callback_t final, void *arg);
+#endif
+
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_bridge(uint8_t *address, int32_t if_num);
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_macvlan(uint8_t *address);
+void ecm_db_iface_macvlan_address_get(struct ecm_db_iface_instance *ii, uint8_t *address);
+#endif
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_ovs_bridge(uint8_t *address, int32_t if_num);
+#endif
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_unknown(uint32_t os_specific_ident);
+
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_pppoe(uint16_t pppoe_session_id, uint8_t *remote_mac);
+void ecm_db_iface_add_pppoe(struct ecm_db_iface_instance *ii,
+			    uint16_t pppoe_session_id, uint8_t *remote_mac, char *name,
+			    int32_t mtu, int32_t interface_identifier, int32_t ae_interface_identifier,
+			    ecm_db_iface_final_callback_t final, void *arg);
+#endif
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+void ecm_db_iface_pppol2tpv2_session_info_get(struct ecm_db_iface_instance *ii,
+					      struct ecm_db_interface_info_pppol2tpv2 *pppol2tpv2_info);
+struct ecm_db_iface_instance *
+ecm_db_iface_find_and_ref_pppol2tpv2(uint32_t pppol2tpv2_tunnel_id,
+				     uint32_t pppol2tpv2_session_id);
+void ecm_db_iface_add_pppol2tpv2(struct ecm_db_iface_instance *ii,
+				 struct ecm_db_interface_info_pppol2tpv2 *pppol2tpv2_info,
+				 char *name, int32_t mtu, int32_t interface_identifier,
+				 int32_t ae_interface_identifier,
+				 ecm_db_iface_final_callback_t final, void *arg);
+#endif
+
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_map_t(int if_index, int32_t ae_interface_num);
+void ecm_db_iface_add_map_t(struct ecm_db_iface_instance *ii,
+			    struct ecm_db_interface_info_map_t *map_t_info, char *name,
+			    int32_t mtu, int32_t interface_identifier, int32_t ae_interface_identifier,
+			    ecm_db_iface_final_callback_t final, void *arg);
+#endif
+
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_gre_tun(int if_index, int32_t ae_interface_num);
+void ecm_db_iface_gre_tun_info_get(struct ecm_db_iface_instance *ii, struct ecm_db_interface_info_gre_tun *gre_tun_info);
+void ecm_db_iface_add_gre_tun(struct ecm_db_iface_instance *ii,
+				struct ecm_db_interface_info_gre_tun *gre_tun_info, char *name,
+				int32_t mtu, int32_t interface_identifier, int32_t ae_interface_identifier,
+				ecm_db_iface_final_callback_t final, void *arg);
+#endif
+
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_pptp(uint32_t pptp_src_call_id,
+							     uint32_t pptp_dst_call_id,
+							     int32_t ae_interface_num);
+void ecm_db_iface_pptp_session_info_get(struct ecm_db_iface_instance *ii,
+					struct ecm_db_interface_info_pptp *pptp_info);
+void ecm_db_iface_add_pptp(struct ecm_db_iface_instance *ii,
+			   struct ecm_db_interface_info_pptp *pptp_info, char *name,
+			   int32_t mtu, int32_t interface_identifier,
+			   int32_t ae_interface_identifier,
+			   ecm_db_iface_final_callback_t final, void *arg);
+#endif
+
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_loopback(uint32_t os_specific_ident);
+
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_ipsec_tunnel(uint32_t os_specific_ident, int32_t ae_interface_num);
+void ecm_db_iface_add_ipsec_tunnel(struct ecm_db_iface_instance *ii,
+				   uint32_t os_specific_ident, char *name, int32_t mtu,
+				   int32_t interface_identifier, int32_t ae_interface_identifier,
+				   ecm_db_iface_final_callback_t final, void *arg);
+#endif
+
+#ifdef ECM_INTERFACE_SIT_ENABLE
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_sit(ip_addr_t saddr,
+							    ip_addr_t daddr,
+							    int32_t ae_interface_num);
+bool ecm_db_iface_sit_daddr_is_null(struct ecm_db_iface_instance *ii);
+void ecm_db_iface_add_sit(struct ecm_db_iface_instance *ii,
+			  struct ecm_db_interface_info_sit *type_info, char *name,
+			  int32_t mtu, int32_t interface_identifier,
+			  int32_t ae_interface_identifier, ecm_db_iface_final_callback_t final, void *arg);
+#endif
+#ifdef ECM_INTERFACE_TUNIPIP6_ENABLE
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_tunipip6(ip_addr_t saddr,
+								 ip_addr_t daddr,
+								 int32_t ae_interface_num);
+void ecm_db_iface_add_tunipip6(struct ecm_db_iface_instance *ii,
+				struct ecm_db_interface_info_tunipip6 *type_info, char *name,
+				int32_t mtu, int32_t interface_identifier,
+				int32_t ae_interface_identifier, ecm_db_iface_final_callback_t final, void *arg);
+#endif
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_ovpn(int32_t tun_ifnum);
+void ecm_db_iface_add_ovpn(struct ecm_db_iface_instance *ii,
+				struct ecm_db_interface_info_ovpn *type_info, char *name,
+				int32_t mtu, int32_t interface_identifier,
+				ecm_db_iface_final_callback_t final, void *arg);
+#endif
+
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+struct ecm_db_iface_instance *ecm_db_iface_find_and_ref_vxlan(uint32_t vni, uint32_t if_type);
+void ecm_db_iface_add_vxlan(struct ecm_db_iface_instance *ii,
+			   uint32_t vni, uint32_t if_type, char *name,
+			   int32_t mtu, int32_t interface_identifier,
+			   int32_t ae_interface_identifier,
+			   ecm_db_iface_final_callback_t final, void *arg);
+#endif
+
+struct ecm_db_iface_instance *ecm_db_interfaces_get_and_ref_first(void);
+struct ecm_db_iface_instance *ecm_db_interface_get_and_ref_next(struct ecm_db_iface_instance *ii);
+
+#ifdef ECM_DB_XREF_ENABLE
+int ecm_db_iface_node_count_get(struct ecm_db_iface_instance *ii);
+struct ecm_db_node_instance *ecm_db_iface_nodes_get_and_ref_first(struct ecm_db_iface_instance *ii);
+struct ecm_db_connection_instance *
+ecm_db_iface_connections_get_and_ref_first(struct ecm_db_iface_instance *ii,
+					   ecm_db_obj_dir_t dir);
+#endif
+
+struct ecm_db_iface_instance *ecm_db_iface_alloc(void);
+
+void ecm_db_iface_add_ethernet(struct ecm_db_iface_instance *ii,
+				uint8_t *address, char *name, int32_t mtu, int32_t interface_identifier,
+				int32_t ae_interface_identifier, ecm_db_iface_final_callback_t final, void *arg);
+
+void ecm_db_iface_add_bridge(struct ecm_db_iface_instance *ii,
+				uint8_t *address, char *name, int32_t mtu, int32_t interface_identifier,
+				int32_t ae_interface_identifier, ecm_db_iface_final_callback_t final, void *arg);
+
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+void ecm_db_iface_add_macvlan(struct ecm_db_iface_instance *ii,
+				uint8_t *address, char *name, int32_t mtu, int32_t interface_identifier,
+				int32_t ae_interface_identifier, ecm_db_iface_final_callback_t final, void *arg);
+#endif
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+void ecm_db_iface_add_ovs_bridge(struct ecm_db_iface_instance *ii,
+				uint8_t *address, char *name, int32_t mtu, int32_t interface_identifier,
+				int32_t ae_interface_identifier, ecm_db_iface_final_callback_t final, void *arg);
+#endif
+
+void ecm_db_iface_add_unknown(struct ecm_db_iface_instance *ii,
+				uint32_t os_specific_ident, char *name, int32_t mtu, int32_t interface_identifier,
+				int32_t ae_interface_identifier, ecm_db_iface_final_callback_t final, void *arg);
+
+void ecm_db_iface_add_loopback(struct ecm_db_iface_instance *ii,
+				uint32_t os_specific_ident, char *name, int32_t mtu, int32_t interface_identifier,
+				int32_t ae_interface_identifier, ecm_db_iface_final_callback_t final, void *arg);
+
+#ifdef ECM_INTERFACE_RAWIP_ENABLE
+void ecm_db_iface_add_rawip(struct ecm_db_iface_instance *ii,
+				uint8_t *address, char *name, int32_t mtu, int32_t interface_identifier,
+				int32_t ae_interface_identifier, ecm_db_iface_final_callback_t final, void *arg);
+#endif
+
+char *ecm_db_interface_type_to_string(ecm_db_iface_type_t type);
+
+ecm_db_iface_type_t ecm_db_iface_type_get(struct ecm_db_iface_instance *ii);
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+int ecm_db_iface_state_get(struct ecm_state_file_instance *sfi, struct ecm_db_iface_instance *ii);
+int ecm_db_iface_hash_table_lengths_get(int index);
+int ecm_db_iface_hash_index_get_next(int index);
+int ecm_db_iface_hash_index_get_first(void);
+#endif
+
+bool ecm_db_iface_init(struct dentry *dentry);
diff --git a/qca-nss-ecm/ecm_db/ecm_db_listener.c b/qca-nss-ecm/ecm_db/ecm_db_listener.c
new file mode 100644
index 0000000..7baf613
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_listener.c
@@ -0,0 +1,280 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <linux/random.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <net/ip6_route.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_DB_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_classifier_default.h"
+#include "ecm_db.h"
+
+/*
+ * Magic number.
+ */
+#define ECM_DB_LISTENER_INSTANCE_MAGIC 0x9876
+
+/*
+ * Listeners
+ */
+static int ecm_db_listeners_count = 0;			/* Number of listeners allocated */
+static struct ecm_db_listener_instance *ecm_db_listeners = NULL;
+							/* Event listeners */
+
+/*
+ * _ecm_db_listener_ref()
+ */
+static void _ecm_db_listener_ref(struct ecm_db_listener_instance *li)
+{
+	DEBUG_CHECK_MAGIC(li, ECM_DB_LISTENER_INSTANCE_MAGIC, "%px: magic failed", li);
+	li->refs++;
+	DEBUG_ASSERT(li->refs > 0, "%px: ref wrap\n", li);
+}
+
+/*
+ * ecm_db_listener_ref()
+ */
+void ecm_db_listener_ref(struct ecm_db_listener_instance *li)
+{
+	spin_lock_bh(&ecm_db_lock);
+	_ecm_db_listener_ref(li);
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_listener_ref);
+
+/*
+ * ecm_db_listeners_get_and_ref_first()
+ *	Obtain a ref to the first listener instance, if any
+ */
+struct ecm_db_listener_instance *ecm_db_listeners_get_and_ref_first(void)
+{
+	struct ecm_db_listener_instance *li;
+	spin_lock_bh(&ecm_db_lock);
+	li = ecm_db_listeners;
+	if (li) {
+		_ecm_db_listener_ref(li);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return li;
+}
+
+/*
+ * ecm_db_listener_get_and_ref_next()
+ *	Return the next listener in the list given a listener
+ */
+struct ecm_db_listener_instance *ecm_db_listener_get_and_ref_next(struct ecm_db_listener_instance *li)
+{
+	struct ecm_db_listener_instance *lin;
+	DEBUG_CHECK_MAGIC(li, ECM_DB_LISTENER_INSTANCE_MAGIC, "%px: magic failed", li);
+	spin_lock_bh(&ecm_db_lock);
+	lin = li->next;
+	if (lin) {
+		_ecm_db_listener_ref(lin);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return lin;
+}
+
+/*
+ * ecm_db_listener_deref()
+ *	Release reference to listener.
+ *
+ * On final reference release listener shall be removed from the database.
+ */
+int ecm_db_listener_deref(struct ecm_db_listener_instance *li)
+{
+	struct ecm_db_listener_instance *cli;
+	struct ecm_db_listener_instance **cli_prev;
+
+	DEBUG_CHECK_MAGIC(li, ECM_DB_LISTENER_INSTANCE_MAGIC, "%px: magic failed", li);
+
+	spin_lock_bh(&ecm_db_lock);
+	li->refs--;
+	DEBUG_ASSERT(li->refs >= 0, "%px: ref wrap\n", li);
+	if (li->refs > 0) {
+		int refs;
+		refs = li->refs;
+		spin_unlock_bh(&ecm_db_lock);
+		return refs;
+	}
+
+	/*
+	 * Instance is to be removed and destroyed.
+	 * Link the listener out of the listener list.
+	 */
+	cli = ecm_db_listeners;
+	cli_prev = &ecm_db_listeners;
+	while (cli) {
+		if (cli == li) {
+			*cli_prev = cli->next;
+			break;
+		}
+		cli_prev = &cli->next;
+		cli = cli->next;
+	}
+	DEBUG_ASSERT(cli, "%px: not found\n", li);
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Invoke final callback
+	 */
+	if (li->final) {
+		li->final(li->arg);
+	}
+	DEBUG_CLEAR_MAGIC(li);
+	kfree(li);
+
+	/*
+	 * Decrease global listener count
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ecm_db_listeners_count--;
+	DEBUG_ASSERT(ecm_db_listeners_count >= 0, "%px: listener count wrap\n", li);
+	spin_unlock_bh(&ecm_db_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_db_listener_deref);
+
+/*
+ * ecm_db_listener_add()
+ *	Add a listener instance into the database.
+ */
+void ecm_db_listener_add(struct ecm_db_listener_instance *li,
+							ecm_db_iface_listener_added_callback_t iface_added,
+							ecm_db_iface_listener_removed_callback_t iface_removed,
+							ecm_db_node_listener_added_callback_t node_added,
+							ecm_db_node_listener_removed_callback_t node_removed,
+							ecm_db_host_listener_added_callback_t host_added,
+							ecm_db_host_listener_removed_callback_t host_removed,
+							ecm_db_mapping_listener_added_callback_t mapping_added,
+							ecm_db_mapping_listener_removed_callback_t mapping_removed,
+							ecm_db_connection_listener_added_callback_t connection_added,
+							ecm_db_connection_listener_removed_callback_t connection_removed,
+							ecm_db_listener_final_callback_t final,
+							void *arg)
+{
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(li, ECM_DB_LISTENER_INSTANCE_MAGIC, "%px: magic failed\n", li);
+	DEBUG_ASSERT(!(li->flags & ECM_DB_LISTENER_FLAGS_INSERTED), "%px: inserted\n", li);
+	spin_unlock_bh(&ecm_db_lock);
+
+	li->arg = arg;
+	li->final = final;
+	li->iface_added = iface_added;
+	li->iface_removed = iface_removed;
+	li->node_added = node_added;
+	li->node_removed = node_removed;
+	li->host_added = host_added;
+	li->host_removed = host_removed;
+	li->mapping_added = mapping_added;
+	li->mapping_removed = mapping_removed;
+	li->connection_added = connection_added;
+	li->connection_removed = connection_removed;
+
+	/*
+	 * Add instance into listener list
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	li->flags |= ECM_DB_LISTENER_FLAGS_INSERTED;
+	li->next = ecm_db_listeners;
+	ecm_db_listeners = li;
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_listener_add);
+
+/*
+ * ecm_db_listener_alloc()
+ *	Allocate a listener instance
+ */
+struct ecm_db_listener_instance *ecm_db_listener_alloc(void)
+{
+	struct ecm_db_listener_instance *li;
+
+	li = (struct ecm_db_listener_instance *)kzalloc(sizeof(struct ecm_db_listener_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!li) {
+		DEBUG_WARN("Alloc failed\n");
+		return NULL;
+	}
+
+	li->refs = 1;
+	DEBUG_SET_MAGIC(li, ECM_DB_LISTENER_INSTANCE_MAGIC);
+
+	/*
+	 * Alloc operation must be atomic to ensure thread and module can be held
+	 */
+	spin_lock_bh(&ecm_db_lock);
+
+	/*
+	 * If the event processing thread is terminating then we cannot create new instances
+	 */
+	if (ecm_db_terminate_pending) {
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_WARN("Thread terminating\n");
+		kfree(li);
+		return NULL;
+	}
+
+	ecm_db_listeners_count++;
+	DEBUG_ASSERT(ecm_db_listeners_count > 0, "%px: listener count wrap\n", li);
+	spin_unlock_bh(&ecm_db_lock);
+
+	DEBUG_TRACE("Listener created %px\n", li);
+	return li;
+}
+EXPORT_SYMBOL(ecm_db_listener_alloc);
diff --git a/qca-nss-ecm/ecm_db/ecm_db_listener.h b/qca-nss-ecm/ecm_db/ecm_db_listener.h
new file mode 100644
index 0000000..cfd87d8
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_listener.h
@@ -0,0 +1,68 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * struct ecm_db_listener_instance
+ *	listener instances
+ */
+struct ecm_db_listener_instance {
+	struct ecm_db_listener_instance *next;
+	struct ecm_db_listener_instance *event_next;
+	uint32_t flags;
+	void *arg;
+	int refs;							/* Integer to trap we never go negative */
+	ecm_db_mapping_final_callback_t final;				/* Final callback for this instance */
+
+	ecm_db_iface_listener_added_callback_t iface_added;
+	ecm_db_iface_listener_removed_callback_t iface_removed;
+	ecm_db_node_listener_added_callback_t node_added;
+	ecm_db_node_listener_removed_callback_t node_removed;
+	ecm_db_host_listener_added_callback_t host_added;
+	ecm_db_host_listener_removed_callback_t host_removed;
+	ecm_db_mapping_listener_added_callback_t mapping_added;
+	ecm_db_mapping_listener_removed_callback_t mapping_removed;
+	ecm_db_connection_listener_added_callback_t connection_added;
+	ecm_db_connection_listener_removed_callback_t connection_removed;
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+/*
+ * Listener flags
+ */
+#define ECM_DB_LISTENER_FLAGS_INSERTED 1			/* Is inserted into database */
+
+void ecm_db_listener_ref(struct ecm_db_listener_instance *li);
+int ecm_db_listener_deref(struct ecm_db_listener_instance *li);
+
+struct ecm_db_listener_instance *ecm_db_listener_alloc(void);
+
+void ecm_db_listener_add(struct ecm_db_listener_instance *li,
+			 ecm_db_iface_listener_added_callback_t iface_added,
+			 ecm_db_iface_listener_removed_callback_t iface_removed,
+			 ecm_db_node_listener_added_callback_t node_added,
+			 ecm_db_node_listener_removed_callback_t node_removed,
+			 ecm_db_host_listener_added_callback_t host_added,
+			 ecm_db_host_listener_removed_callback_t host_removed,
+			 ecm_db_mapping_listener_added_callback_t mapping_added,
+			 ecm_db_mapping_listener_removed_callback_t mapping_removed,
+			 ecm_db_connection_listener_added_callback_t connection_added,
+			 ecm_db_connection_listener_removed_callback_t connection_removed,
+			 ecm_db_listener_final_callback_t final, void *arg);
+
+struct ecm_db_listener_instance *ecm_db_listeners_get_and_ref_first(void);
+struct ecm_db_listener_instance *ecm_db_listener_get_and_ref_next(struct ecm_db_listener_instance *li);
diff --git a/qca-nss-ecm/ecm_db/ecm_db_mapping.c b/qca-nss-ecm/ecm_db/ecm_db_mapping.c
new file mode 100644
index 0000000..1d06ef4
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_mapping.c
@@ -0,0 +1,839 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <linux/random.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <net/ip6_route.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_DB_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_classifier_default.h"
+#include "ecm_db.h"
+
+/*
+ * Global list.
+ * All instances are inserted into global list - this allows easy iteration of all instances of a particular type.
+ * The list is doubly linked for fast removal.  The list is in no particular order.
+ */
+struct ecm_db_mapping_instance *ecm_db_mappings = NULL;
+
+/*
+ * Mapping hash table
+ */
+#define ECM_DB_MAPPING_HASH_SLOTS 32768
+static struct ecm_db_mapping_instance **ecm_db_mapping_table;
+							/* Slots of the mapping hash table */
+static int *ecm_db_mapping_table_lengths;
+							/* Tracks how long each chain is */
+static int ecm_db_mapping_count = 0;			/* Number of mappings allocated */
+
+/*
+ * Mapping flags
+ */
+#define ECM_DB_MAPPING_FLAGS_INSERTED 1	/* Mapping is inserted into connection database tables */
+
+/*
+ * ecm_db_mapping_generate_hash_index()
+ * 	Calculate the hash index.
+ */
+static inline ecm_db_mapping_hash_t ecm_db_mapping_generate_hash_index(ip_addr_t address, uint32_t port)
+{
+	uint32_t tuple;
+	uint32_t hash_val;
+
+	ECM_IP_ADDR_HASH(tuple, address);
+	hash_val = (uint32_t)jhash_2words(tuple, port, ecm_db_jhash_rnd);
+	return (ecm_db_mapping_hash_t)(hash_val & (ECM_DB_MAPPING_HASH_SLOTS - 1));
+}
+
+/*
+ * _ecm_db_mapping_count_get()
+ *	Return the mapping count (lockless).
+ */
+int _ecm_db_mapping_count_get(void)
+{
+	return ecm_db_mapping_count;
+}
+
+/*
+ * _ecm_db_mapping_ref()
+ */
+void _ecm_db_mapping_ref(struct ecm_db_mapping_instance *mi)
+{
+	DEBUG_CHECK_MAGIC(mi, ECM_DB_MAPPING_INSTANCE_MAGIC, "%px: magic failed\n", mi);
+	mi->refs++;
+	DEBUG_TRACE("%px: mapping ref %d\n", mi, mi->refs);
+	DEBUG_ASSERT(mi->refs > 0, "%px: ref wrap\n", mi);
+}
+
+/*
+ * ecm_db_mapping_ref()
+ */
+void ecm_db_mapping_ref(struct ecm_db_mapping_instance *mi)
+{
+	spin_lock_bh(&ecm_db_lock);
+	_ecm_db_mapping_ref(mi);
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_mapping_ref);
+
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+/*
+ * ecm_db_mapping_data_stats_get()
+ *	Return data stats for the instance
+ */
+void ecm_db_mapping_data_stats_get(struct ecm_db_mapping_instance *mi, uint64_t *from_data_total, uint64_t *to_data_total,
+						uint64_t *from_packet_total, uint64_t *to_packet_total,
+						uint64_t *from_data_total_dropped, uint64_t *to_data_total_dropped,
+						uint64_t *from_packet_total_dropped, uint64_t *to_packet_total_dropped)
+{
+	DEBUG_CHECK_MAGIC(mi, ECM_DB_MAPPING_INSTANCE_MAGIC, "%px: magic failed", mi);
+	spin_lock_bh(&ecm_db_lock);
+	if (from_data_total) {
+		*from_data_total = mi->from_data_total;
+	}
+	if (to_data_total) {
+		*to_data_total = mi->to_data_total;
+	}
+	if (from_packet_total) {
+		*from_packet_total = mi->from_packet_total;
+	}
+	if (to_packet_total) {
+		*to_packet_total = mi->to_packet_total;
+	}
+	if (from_data_total_dropped) {
+		*from_data_total_dropped = mi->from_data_total_dropped;
+	}
+	if (to_data_total_dropped) {
+		*to_data_total_dropped = mi->to_data_total_dropped;
+	}
+	if (from_packet_total_dropped) {
+		*from_packet_total_dropped = mi->from_packet_total_dropped;
+	}
+	if (to_packet_total_dropped) {
+		*to_packet_total_dropped = mi->to_packet_total_dropped;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_mapping_data_stats_get);
+#endif
+
+/*
+ * ecm_db_mapping_state_get()
+ *	Prepare a mapping message
+ */
+int ecm_db_mapping_state_get(struct ecm_state_file_instance *sfi, struct ecm_db_mapping_instance *mi)
+{
+	int result;
+	int port;
+	char address[ECM_IP_ADDR_STR_BUFF_SIZE];
+	int tcp_count[ECM_DB_OBJ_DIR_MAX];
+	int udp_count[ECM_DB_OBJ_DIR_MAX];
+	int conn_count[ECM_DB_OBJ_DIR_MAX];
+	uint32_t time_added;
+	struct ecm_db_host_instance *hi;
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	uint64_t from_data_total;
+	uint64_t to_data_total;
+	uint64_t from_packet_total;
+	uint64_t to_packet_total;
+	uint64_t from_data_total_dropped;
+	uint64_t to_data_total_dropped;
+	uint64_t from_packet_total_dropped;
+	uint64_t to_packet_total_dropped;
+#endif
+	DEBUG_CHECK_MAGIC(mi, ECM_DB_MAPPING_INSTANCE_MAGIC, "%px: magic failed", mi);
+
+	DEBUG_TRACE("Prep mapping msg for %px\n", mi);
+
+	/*
+	 * Create a small xml stats element for our mapping.
+	 * Extract information from the mapping for inclusion into the message
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	memcpy(tcp_count, mi->tcp_count, sizeof(tcp_count));
+	memcpy(udp_count, mi->udp_count, sizeof(udp_count));
+	memcpy(conn_count, mi->conn_count, sizeof(conn_count));
+	spin_unlock_bh(&ecm_db_lock);
+
+	port = mi->port;
+	time_added = mi->time_added;
+	hi = mi->host;
+	ecm_ip_addr_to_string(address, hi->address);
+
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	ecm_db_mapping_data_stats_get(mi, &from_data_total, &to_data_total,
+			&from_packet_total, &to_packet_total,
+			&from_data_total_dropped, &to_data_total_dropped,
+			&from_packet_total_dropped, &to_packet_total_dropped);
+#endif
+
+	if ((result = ecm_state_prefix_add(sfi, "mapping"))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "port", "%d", port))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "from", "%d", conn_count[ECM_DB_OBJ_DIR_FROM]))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "to", "%d", conn_count[ECM_DB_OBJ_DIR_TO]))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "tcp_from", "%d", tcp_count[ECM_DB_OBJ_DIR_FROM]))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "tcp_to", "%d", tcp_count[ECM_DB_OBJ_DIR_TO]))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "udp_from", "%d", udp_count[ECM_DB_OBJ_DIR_FROM]))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "udp_to", "%d", udp_count[ECM_DB_OBJ_DIR_TO]))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "nat_from", "%d", conn_count[ECM_DB_OBJ_DIR_FROM_NAT]))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "nat_to", "%d", conn_count[ECM_DB_OBJ_DIR_TO_NAT]))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "tcp_nat_from", "%d", tcp_count[ECM_DB_OBJ_DIR_FROM_NAT]))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "tcp_nat_to", "%d", tcp_count[ECM_DB_OBJ_DIR_TO_NAT]))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "udp_nat_from", "%d", udp_count[ECM_DB_OBJ_DIR_FROM_NAT]))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "udp_nat_to", "%d", udp_count[ECM_DB_OBJ_DIR_TO_NAT]))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "address", "%s", address))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "time_added", "%u", time_added))) {
+		return result;
+	}
+
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	if ((result = ecm_db_adv_stats_state_write(sfi, from_data_total, to_data_total,
+			from_packet_total, to_packet_total, from_data_total_dropped,
+			to_data_total_dropped, from_packet_total_dropped,
+			to_packet_total_dropped))) {
+		return result;
+	}
+#endif
+
+	return ecm_state_prefix_remove(sfi);
+}
+EXPORT_SYMBOL(ecm_db_mapping_state_get);
+
+/*
+ * ecm_db_mapping_adress_get()
+ *	Return address
+ */
+void ecm_db_mapping_adress_get(struct ecm_db_mapping_instance *mi, ip_addr_t addr)
+{
+	DEBUG_CHECK_MAGIC(mi, ECM_DB_MAPPING_INSTANCE_MAGIC, "%px: magic failed", mi);
+	ECM_IP_ADDR_COPY(addr, mi->host->address);
+}
+EXPORT_SYMBOL(ecm_db_mapping_adress_get);
+
+/*
+ * ecm_db_mapping_port_get()
+ *	Return port
+ */
+int ecm_db_mapping_port_get(struct ecm_db_mapping_instance *mi)
+{
+	DEBUG_CHECK_MAGIC(mi, ECM_DB_MAPPING_INSTANCE_MAGIC, "%px: magic failed", mi);
+	return mi->port;
+}
+EXPORT_SYMBOL(ecm_db_mapping_port_get);
+
+/*
+ * ecm_db_mappings_get_and_ref_first()
+ *	Obtain a ref to the first mapping instance, if any
+ */
+struct ecm_db_mapping_instance *ecm_db_mappings_get_and_ref_first(void)
+{
+	struct ecm_db_mapping_instance *mi;
+	spin_lock_bh(&ecm_db_lock);
+	mi = ecm_db_mappings;
+	if (mi) {
+		_ecm_db_mapping_ref(mi);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return mi;
+}
+EXPORT_SYMBOL(ecm_db_mappings_get_and_ref_first);
+
+/*
+ * ecm_db_mapping_get_and_ref_next()
+ *	Return the next mapping in the list given a mapping
+ */
+struct ecm_db_mapping_instance *ecm_db_mapping_get_and_ref_next(struct ecm_db_mapping_instance *mi)
+{
+	struct ecm_db_mapping_instance *min;
+	DEBUG_CHECK_MAGIC(mi, ECM_DB_MAPPING_INSTANCE_MAGIC, "%px: magic failed", mi);
+	spin_lock_bh(&ecm_db_lock);
+	min = mi->next;
+	if (min) {
+		_ecm_db_mapping_ref(min);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return min;
+}
+EXPORT_SYMBOL(ecm_db_mapping_get_and_ref_next);
+
+/*
+ * ecm_db_mapping_deref()
+ *	Release ref to mapping, possibly removing it from the database and destroying it.
+ */
+int ecm_db_mapping_deref(struct ecm_db_mapping_instance *mi)
+{
+#if (DEBUG_LEVEL >= 1)
+	int dir;
+#endif
+	DEBUG_CHECK_MAGIC(mi, ECM_DB_MAPPING_INSTANCE_MAGIC, "%px: magic failed\n", mi);
+
+	spin_lock_bh(&ecm_db_lock);
+	mi->refs--;
+	DEBUG_TRACE("%px: mapping deref %d\n", mi, mi->refs);
+	DEBUG_ASSERT(mi->refs >= 0, "%px: ref wrap\n", mi);
+
+	if (mi->refs > 0) {
+		int refs = mi->refs;
+		spin_unlock_bh(&ecm_db_lock);
+		return refs;
+	}
+
+#if (DEBUG_LEVEL >= 1)
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		DEBUG_ASSERT(!mi->tcp_count[dir] && !mi->udp_count[dir] && !mi->conn_count[dir], "%px: %s not zero: %d, %d, %d\n",
+			     mi, ecm_db_obj_dir_strings[dir], mi->tcp_count[dir], mi->udp_count[dir], mi->conn_count[dir]);
+#ifdef ECM_DB_XREF_ENABLE
+		DEBUG_ASSERT(!mi->connections[dir], "%px: %s not null: %px\n", mi, ecm_db_obj_dir_strings[dir], mi->connections[dir]);
+#endif
+	}
+#endif
+	/*
+	 * Remove from database if inserted
+	 */
+	if (!mi->flags & ECM_DB_MAPPING_FLAGS_INSERTED) {
+		spin_unlock_bh(&ecm_db_lock);
+	} else {
+		struct ecm_db_listener_instance *li;
+
+		/*
+		 * Remove from the global list
+		 */
+		if (!mi->prev) {
+			DEBUG_ASSERT(ecm_db_mappings == mi, "%px: mapping table bad\n", mi);
+			ecm_db_mappings = mi->next;
+		} else {
+			mi->prev->next = mi->next;
+		}
+		if (mi->next) {
+			mi->next->prev = mi->prev;
+		}
+		mi->prev = NULL;
+		mi->next = NULL;
+
+		/*
+		 * Unlink it from the mapping hash table
+		 */
+		if (!mi->hash_prev) {
+			DEBUG_ASSERT(ecm_db_mapping_table[mi->hash_index] == mi, "%px: hash table bad\n", mi);
+			ecm_db_mapping_table[mi->hash_index] = mi->hash_next;
+		} else {
+			mi->hash_prev->hash_next = mi->hash_next;
+		}
+		if (mi->hash_next) {
+			mi->hash_next->hash_prev = mi->hash_prev;
+		}
+		mi->hash_next = NULL;
+		mi->hash_prev = NULL;
+		ecm_db_mapping_table_lengths[mi->hash_index]--;
+		DEBUG_ASSERT(ecm_db_mapping_table_lengths[mi->hash_index] >= 0, "%px: invalid table len %d\n", mi, ecm_db_mapping_table_lengths[mi->hash_index]);
+
+#ifdef ECM_DB_XREF_ENABLE
+		/*
+		 * Unlink it from the host mapping list
+		 */
+		if (!mi->mapping_prev) {
+			DEBUG_ASSERT(mi->host->mappings == mi, "%px: mapping table bad\n", mi);
+			mi->host->mappings = mi->mapping_next;
+		} else {
+			mi->mapping_prev->mapping_next = mi->mapping_next;
+		}
+		if (mi->mapping_next) {
+			mi->mapping_next->mapping_prev = mi->mapping_prev;
+		}
+		mi->mapping_next = NULL;
+		mi->mapping_prev = NULL;
+
+		mi->host->mapping_count--;
+#endif
+		spin_unlock_bh(&ecm_db_lock);
+
+		/*
+		 * Throw removed event to listeners
+		 */
+		DEBUG_TRACE("%px: Throw mapping removed event\n", mi);
+		li = ecm_db_listeners_get_and_ref_first();
+		while (li) {
+			struct ecm_db_listener_instance *lin;
+			if (li->mapping_removed) {
+				li->mapping_removed(li->arg, mi);
+			}
+
+			/*
+			 * Get next listener
+			 */
+			lin = ecm_db_listener_get_and_ref_next(li);
+			ecm_db_listener_deref(li);
+			li = lin;
+		}
+	}
+
+	/*
+	 * Throw final event
+	 */
+	if (mi->final) {
+		mi->final(mi->arg);
+	}
+
+	/*
+	 * Now release the host instance if the mapping had one
+	 */
+	if (mi->host) {
+		ecm_db_host_deref(mi->host);
+	}
+
+	/*
+	 * We can now destroy the instance
+	 */
+	DEBUG_CLEAR_MAGIC(mi);
+	kfree(mi);
+
+	/*
+	 * Decrease global mapping count
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ecm_db_mapping_count--;
+	DEBUG_ASSERT(ecm_db_mapping_count >= 0, "%px: mapping count wrap\n", mi);
+	spin_unlock_bh(&ecm_db_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_db_mapping_deref);
+
+/*
+ * ecm_db_mapping_find_and_ref()
+ *	Lookup and return a mapping reference if any.
+ *
+ * NOTE: For non-port based protocols the ports are expected to be -(protocol)
+ */
+struct ecm_db_mapping_instance *ecm_db_mapping_find_and_ref(ip_addr_t address, int port)
+{
+	ecm_db_mapping_hash_t hash_index;
+	struct ecm_db_mapping_instance *mi;
+
+	DEBUG_TRACE("Lookup mapping with addr " ECM_IP_ADDR_OCTAL_FMT " and port %d\n", ECM_IP_ADDR_TO_OCTAL(address), port);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_mapping_generate_hash_index(address, port);
+
+	/*
+	 * Iterate the chain looking for a mapping with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	mi = ecm_db_mapping_table[hash_index];
+	while (mi) {
+		if (mi->port != port) {
+			mi = mi->hash_next;
+			continue;
+		}
+
+		if (!ECM_IP_ADDR_MATCH(mi->host->address, address)) {
+			mi = mi->hash_next;
+			continue;
+		}
+
+		_ecm_db_mapping_ref(mi);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("Mapping found %px\n", mi);
+		return mi;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Mapping not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_mapping_find_and_ref);
+
+#ifdef ECM_DB_XREF_ENABLE
+/*
+ * ecm_db_mapping_connections_get_and_ref_first()
+ *	Return a reference to the first connection made on this mapping in the specified direction.
+ */
+struct ecm_db_connection_instance *ecm_db_mapping_connections_get_and_ref_first(struct ecm_db_mapping_instance *mi, ecm_db_obj_dir_t dir)
+{
+	struct ecm_db_connection_instance *ci;
+
+	DEBUG_CHECK_MAGIC(mi, ECM_DB_MAPPING_INSTANCE_MAGIC, "%px: magic failed", mi);
+
+	spin_lock_bh(&ecm_db_lock);
+	ci = mi->connections[dir];
+	if (ci) {
+		_ecm_db_connection_ref(ci);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	return ci;
+}
+EXPORT_SYMBOL(ecm_db_mapping_connections_get_and_ref_first);
+#endif
+
+/*
+ * ecm_db_mapping_host_get_and_ref()
+ */
+struct ecm_db_host_instance *ecm_db_mapping_host_get_and_ref(struct ecm_db_mapping_instance *mi)
+{
+	DEBUG_CHECK_MAGIC(mi, ECM_DB_MAPPING_INSTANCE_MAGIC, "%px: magic failed\n", mi);
+
+	spin_lock_bh(&ecm_db_lock);
+	_ecm_db_host_ref(mi->host);
+	spin_unlock_bh(&ecm_db_lock);
+	return mi->host;
+}
+EXPORT_SYMBOL(ecm_db_mapping_host_get_and_ref);
+
+/*
+ * ecm_db_mapping_connections_total_count_get()
+ *	Return the total number of connections (NAT and non-NAT) this mapping has
+ */
+int ecm_db_mapping_connections_total_count_get(struct ecm_db_mapping_instance *mi)
+{
+	int count;
+
+	DEBUG_CHECK_MAGIC(mi, ECM_DB_MAPPING_INSTANCE_MAGIC, "%px: magic failed\n", mi);
+
+	spin_lock_bh(&ecm_db_lock);
+	count = mi->conn_count[ECM_DB_OBJ_DIR_FROM] +
+		mi->conn_count[ECM_DB_OBJ_DIR_TO] +
+		mi->conn_count[ECM_DB_OBJ_DIR_FROM_NAT] +
+		mi->conn_count[ECM_DB_OBJ_DIR_TO_NAT];
+
+	DEBUG_ASSERT(count >= 0, "%px: Count overflow from: %d, to: %d, nat_from: %d, nat_to: %d\n",
+		     mi, mi->conn_count[ECM_DB_OBJ_DIR_FROM], mi->conn_count[ECM_DB_OBJ_DIR_TO],
+		     mi->conn_count[ECM_DB_OBJ_DIR_FROM_NAT], mi->conn_count[ECM_DB_OBJ_DIR_TO_NAT]);
+	spin_unlock_bh(&ecm_db_lock);
+	return count;
+}
+EXPORT_SYMBOL(ecm_db_mapping_connections_total_count_get);
+
+/*
+ * ecm_db_mapping_add()
+ *	Add a mapping instance into the database
+ *
+ * NOTE: The mapping will take a reference to the host instance.
+ */
+void ecm_db_mapping_add(struct ecm_db_mapping_instance *mi, struct ecm_db_host_instance *hi, int port,
+						ecm_db_mapping_final_callback_t final, void *arg)
+{
+	ecm_db_mapping_hash_t hash_index;
+	struct ecm_db_listener_instance *li;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(mi, ECM_DB_MAPPING_INSTANCE_MAGIC, "%px: magic failed\n", mi);
+	DEBUG_CHECK_MAGIC(hi, ECM_DB_HOST_INSTANCE_MAGIC, "%px: magic failed\n", hi);
+	DEBUG_ASSERT(!(mi->flags & ECM_DB_MAPPING_FLAGS_INSERTED), "%px: inserted\n", mi);
+	DEBUG_ASSERT((hi->flags & ECM_DB_HOST_FLAGS_INSERTED), "%px: not inserted\n", hi);
+	DEBUG_ASSERT(!mi->tcp_count[ECM_DB_OBJ_DIR_FROM] && !mi->tcp_count[ECM_DB_OBJ_DIR_TO] &&
+		     !mi->udp_count[ECM_DB_OBJ_DIR_FROM] && !mi->udp_count[ECM_DB_OBJ_DIR_TO],
+		     "%px: protocol count errors\n", mi);
+#ifdef ECM_DB_XREF_ENABLE
+	DEBUG_ASSERT(mi->connections[ECM_DB_OBJ_DIR_FROM] == NULL, "%px: connections not null\n", mi);
+	DEBUG_ASSERT(mi->connections[ECM_DB_OBJ_DIR_TO] == NULL, "%px: connections not null\n", mi);
+	DEBUG_ASSERT(!mi->conn_count[ECM_DB_OBJ_DIR_FROM] && !mi->conn_count[ECM_DB_OBJ_DIR_TO] &&
+		     !mi->conn_count[ECM_DB_OBJ_DIR_FROM_NAT] && !mi->conn_count[ECM_DB_OBJ_DIR_TO_NAT],
+		     "%px: connection count errors\n", mi);
+#endif
+	spin_unlock_bh(&ecm_db_lock);
+
+	mi->arg = arg;
+	mi->final = final;
+
+	/*
+	 * Compute hash table position for insertion
+	 */
+	hash_index = ecm_db_mapping_generate_hash_index(hi->address, port);
+	mi->hash_index = hash_index;
+
+	/*
+	 * Record port
+	 */
+	mi->port = port;
+
+	/*
+	 * Mapping takes a ref to the host
+	 */
+	ecm_db_host_ref(hi);
+	mi->host = hi;
+
+	/*
+	 * Set time
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	mi->time_added = ecm_db_time;
+
+	/*
+	 * Record the mapping is inserted
+	 */
+	mi->flags |= ECM_DB_MAPPING_FLAGS_INSERTED;
+
+	/*
+	 * Add into the global list
+	 */
+	mi->prev = NULL;
+	mi->next = ecm_db_mappings;
+	if (ecm_db_mappings) {
+		ecm_db_mappings->prev = mi;
+	}
+	ecm_db_mappings = mi;
+
+	/*
+	 * Insert mapping into the mappings hash table
+	 */
+	mi->hash_prev = NULL;
+	mi->hash_next = ecm_db_mapping_table[hash_index];
+	if (ecm_db_mapping_table[hash_index]) {
+		ecm_db_mapping_table[hash_index]->hash_prev = mi;
+	}
+	ecm_db_mapping_table[hash_index] = mi;
+	ecm_db_mapping_table_lengths[hash_index]++;
+	DEBUG_ASSERT(ecm_db_mapping_table_lengths[hash_index] > 0, "%px: invalid table len %d\n", hi, ecm_db_mapping_table_lengths[hash_index]);
+
+#ifdef ECM_DB_XREF_ENABLE
+	/*
+	 * Insert mapping into the host mapping list
+	 */
+	mi->mapping_prev = NULL;
+	mi->mapping_next = hi->mappings;
+	if (hi->mappings) {
+		hi->mappings->mapping_prev = mi;
+	}
+	hi->mappings = mi;
+	hi->mapping_count++;
+#endif
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Throw add event to the listeners
+	 */
+	DEBUG_TRACE("%px: Throw mapping added event\n", mi);
+	li = ecm_db_listeners_get_and_ref_first();
+	while (li) {
+		struct ecm_db_listener_instance *lin;
+		if (li->mapping_added) {
+			li->mapping_added(li->arg, mi);
+		}
+
+		/*
+		 * Get next listener
+		 */
+		lin = ecm_db_listener_get_and_ref_next(li);
+		ecm_db_listener_deref(li);
+		li = lin;
+	}
+}
+EXPORT_SYMBOL(ecm_db_mapping_add);
+
+/*
+ * ecm_db_mapping_hash_table_lengths_get()
+ *	Return hash table length
+ */
+int ecm_db_mapping_hash_table_lengths_get(int index)
+{
+	int length;
+
+	DEBUG_ASSERT((index >= 0) && (index < ECM_DB_MAPPING_HASH_SLOTS), "Bad protocol: %d\n", index);
+	spin_lock_bh(&ecm_db_lock);
+	length = ecm_db_mapping_table_lengths[index];
+	spin_unlock_bh(&ecm_db_lock);
+	return length;
+}
+EXPORT_SYMBOL(ecm_db_mapping_hash_table_lengths_get);
+
+/*
+ * ecm_db_mapping_hash_index_get_next()
+ * Given a hash index, return the next one OR return -1 for no more hash indicies to return.
+ */
+int ecm_db_mapping_hash_index_get_next(int index)
+{
+	index++;
+	if (index >= ECM_DB_MAPPING_HASH_SLOTS) {
+		return -1;
+	}
+	return index;
+}
+EXPORT_SYMBOL(ecm_db_mapping_hash_index_get_next);
+
+/*
+ * ecm_db_mapping_hash_index_get_first()
+ * Return first hash index
+ */
+int ecm_db_mapping_hash_index_get_first(void)
+{
+	return 0;
+}
+EXPORT_SYMBOL(ecm_db_mapping_hash_index_get_first);
+
+/*
+ * ecm_db_mapping_alloc()
+ *	Allocate a mapping instance
+ */
+struct ecm_db_mapping_instance *ecm_db_mapping_alloc(void)
+{
+	struct ecm_db_mapping_instance *mi;
+
+	mi = (struct ecm_db_mapping_instance *)kzalloc(sizeof(struct ecm_db_mapping_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!mi) {
+		DEBUG_WARN("Alloc failed\n");
+		return NULL;
+	}
+
+	mi->refs = 1;
+	DEBUG_SET_MAGIC(mi, ECM_DB_MAPPING_INSTANCE_MAGIC);
+
+	/*
+	 * Alloc operation must be atomic to ensure thread and module can be held
+	 */
+	spin_lock_bh(&ecm_db_lock);
+
+	/*
+	 * If the event processing thread is terminating then we cannot create new instances
+	 */
+	if (ecm_db_terminate_pending) {
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_WARN("Thread terminating\n");
+		kfree(mi);
+		return NULL;
+	}
+
+	ecm_db_mapping_count++;
+	spin_unlock_bh(&ecm_db_lock);
+
+	DEBUG_TRACE("Mapping created %px\n", mi);
+	return mi;
+}
+EXPORT_SYMBOL(ecm_db_mapping_alloc);
+
+/*
+ * ecm_db_mapping_init()
+ */
+bool ecm_db_mapping_init(struct dentry *dentry)
+{
+	if (!debugfs_create_u32("mapping_count", S_IRUGO, dentry,
+					(u32 *)&ecm_db_mapping_count)) {
+		DEBUG_ERROR("Failed to create ecm db mapping count file in debugfs\n");
+		return false;
+	}
+
+	ecm_db_mapping_table = vzalloc(sizeof(struct ecm_db_mapping_instance *) * ECM_DB_MAPPING_HASH_SLOTS);
+	if (!ecm_db_mapping_table) {
+		DEBUG_ERROR("Failed to allocate virtual memory for ecm_db_mapping_table\n");
+		return false;
+	}
+
+	ecm_db_mapping_table_lengths = vzalloc(sizeof(int) * ECM_DB_MAPPING_HASH_SLOTS);
+	if (!ecm_db_mapping_table_lengths) {
+		DEBUG_ERROR("Failed to allocate virtual memory for ecm_db_mapping_table_lengths\n");
+		vfree(ecm_db_mapping_table);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * ecm_db_mapping_exit()
+ */
+void ecm_db_mapping_exit(void)
+{
+	vfree(ecm_db_mapping_table_lengths);
+	vfree(ecm_db_mapping_table);
+}
diff --git a/qca-nss-ecm/ecm_db/ecm_db_mapping.h b/qca-nss-ecm/ecm_db/ecm_db_mapping.h
new file mode 100644
index 0000000..9d6326e
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_mapping.h
@@ -0,0 +1,114 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * Magic number
+ */
+#define ECM_DB_MAPPING_INSTANCE_MAGIC 0x8765
+
+typedef uint32_t ecm_db_mapping_hash_t;
+
+/*
+ * struct ecm_db_mapping_instance
+ */
+struct ecm_db_mapping_instance {
+	struct ecm_db_mapping_instance *next;				/* Next instance in global list */
+	struct ecm_db_mapping_instance *prev;				/* Previous instance in global list */
+
+	struct ecm_db_mapping_instance *hash_next;			/* Next mapping in the chain of mappings */
+	struct ecm_db_mapping_instance *hash_prev;			/* previous mapping in the chain of mappings */
+
+	uint32_t time_added;						/* RO: DB time stamp when the connection was added into the database */
+	struct ecm_db_host_instance *host;				/* The host to which this mapping relates */
+	int port;							/* RO: The port number on the host - only applicable for mapping protocols that are port based */
+
+#ifdef ECM_DB_XREF_ENABLE
+	/*
+	 * For convenience mappings keep lists of connections that have been established from them and to them.
+	 * In fact the same connection could be listed as from & to on the same interface (think: WLAN<>WLAN AP function)
+	 * Mappings keep this information for rapid iteration of connections e.g. given a mapping we
+	 * can defunct all associated connections or destroy any accel engine rules.
+	 */
+	struct ecm_db_connection_instance *connections[ECM_DB_OBJ_DIR_MAX];	/* list of connections made on this host mapping in the specified direction*/
+
+	/*
+	 * While a mapping refers to the host it requires.
+	 * The host also keeps a list of all mappings that are associated with it, this is that list linkage.
+	 */
+	struct ecm_db_mapping_instance *mapping_next;			/* Next mapping in the list of mappings for the host */
+	struct ecm_db_mapping_instance *mapping_prev;			/* previous mapping in the list of mappings for the host */
+#endif
+
+	/*
+	 * Connection counts
+	 */
+	int tcp_count[ECM_DB_OBJ_DIR_MAX];	/* Number of TCP connections made in the specified direction */
+	int udp_count[ECM_DB_OBJ_DIR_MAX];	/* Number of UDP connections made in the specified direction */
+	int conn_count[ECM_DB_OBJ_DIR_MAX];	/* Number of connections made in the specified direction */
+
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	/*
+	 * Data totals
+	 */
+	uint64_t from_data_total;					/* Total of data sent by this mapping */
+	uint64_t to_data_total;						/* Total of data sent to this mapping */
+	uint64_t from_packet_total;					/* Total of packets sent by this mapping */
+	uint64_t to_packet_total;					/* Total of packets sent to this mapping */
+	uint64_t from_data_total_dropped;
+	uint64_t to_data_total_dropped;
+	uint64_t from_packet_total_dropped;
+	uint64_t to_packet_total_dropped;
+#endif
+
+	ecm_db_mapping_final_callback_t final;				/* Callback to owner when object is destroyed */
+	void *arg;							/* Argument returned to owner in callbacks */
+	uint32_t flags;
+	int refs;							/* Integer to trap we never go negative */
+	ecm_db_mapping_hash_t hash_index;
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+int _ecm_db_mapping_count_get(void);
+
+void _ecm_db_mapping_ref(struct ecm_db_mapping_instance *mi);
+void ecm_db_mapping_ref(struct ecm_db_mapping_instance *mi);
+int ecm_db_mapping_deref(struct ecm_db_mapping_instance *mi);
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+int ecm_db_mapping_state_get(struct ecm_state_file_instance *sfi, struct ecm_db_mapping_instance *mi);
+int ecm_db_mapping_hash_table_lengths_get(int index);
+int ecm_db_mapping_hash_index_get_next(int index);
+int ecm_db_mapping_hash_index_get_first(void);
+#endif
+
+void ecm_db_mapping_adress_get(struct ecm_db_mapping_instance *mi, ip_addr_t addr);
+int ecm_db_mapping_port_get(struct ecm_db_mapping_instance *mi);
+
+int ecm_db_mapping_connections_total_count_get(struct ecm_db_mapping_instance *mi);
+struct ecm_db_host_instance *ecm_db_mapping_host_get_and_ref(struct ecm_db_mapping_instance *mi);
+struct ecm_db_mapping_instance *ecm_db_mapping_find_and_ref(ip_addr_t address, int port);
+struct ecm_db_mapping_instance *ecm_db_mappings_get_and_ref_first(void);
+struct ecm_db_mapping_instance *ecm_db_mapping_get_and_ref_next(struct ecm_db_mapping_instance *mi);
+
+struct ecm_db_connection_instance *ecm_db_mapping_connections_get_and_ref_first(struct ecm_db_mapping_instance *mi, ecm_db_obj_dir_t dir);
+
+struct ecm_db_mapping_instance *ecm_db_mapping_alloc(void);
+void ecm_db_mapping_add(struct ecm_db_mapping_instance *mi, struct ecm_db_host_instance *hi, int port, ecm_db_mapping_final_callback_t final, void *arg);
+
+bool ecm_db_mapping_init(struct dentry *dentry);
+void ecm_db_mapping_exit(void);
diff --git a/qca-nss-ecm/ecm_db/ecm_db_multicast.c b/qca-nss-ecm/ecm_db/ecm_db_multicast.c
new file mode 100644
index 0000000..61d1c05
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_multicast.c
@@ -0,0 +1,1161 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <linux/random.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <net/ip6_route.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_DB_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_classifier_default.h"
+#include "ecm_db.h"
+
+#ifdef ECM_MULTICAST_ENABLE
+#define ECM_DB_MULTICAST_INSTANCE_MAGIC 0xc34a
+
+#define ECM_DB_MULTICAST_TUPLE_INSTANCE_HASH_SLOTS 16
+
+typedef uint32_t ecm_db_multicast_tuple_instance_hash_t;
+
+/*
+ * struct ecm_db_multicast_tuple_instance
+ * 	Tuple information for an accelerated multicast connection.
+ * 	This tuple information is further used to find an attached
+ * 	connection for the multicast flow.
+ */
+struct ecm_db_multicast_tuple_instance {
+	struct ecm_db_multicast_tuple_instance *next;	/* Next instance in global list */
+	struct ecm_db_multicast_tuple_instance *prev;	/* Previous instance in global list */
+	struct ecm_db_connection_instance *ci;	/* Pointer to the DB Connection Instance */
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+	struct vlan_hdr ovs_ingress_vlan;	/* Ingress vlan tag for ovs bridge. */
+#endif
+	uint16_t src_port;	/* RO: IPv4/v6 Source Port */
+	uint16_t dst_port;	/* RO: IPv4/v6 Destination Port */
+	ip_addr_t src_ip;	/* RO: IPv4/v6 Source Address */
+	ip_addr_t grp_ip;	/* RO: IPv4/v6 Multicast Group Address */
+	uint32_t flags;		/* Flags for this instance node */
+	uint32_t hash_index;	/* Hash index of this node */
+	int proto;		/* RO: Protocol */
+	struct net_device *l2_br_dev;		/* Bridge device for L2-only flows */
+	struct net_device *l3_br_dev;		/* Bridge device for L3-only flows */
+	int refs;		/* Integer to trap we never go negative */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;		/* Magic value for debug */
+#endif
+};
+
+/*
+ * Multicast connection tuple table
+ * 	This table is used to lookup a complete tuple for multicast connections
+ * 	using the multicast group address
+ */
+static struct ecm_db_multicast_tuple_instance *ecm_db_multicast_tuple_instance_table[ECM_DB_MULTICAST_TUPLE_INSTANCE_HASH_SLOTS];
+
+/*
+ * ecm_db_multicast_connection_data_totals_update()
+ *	Update the total bytes and packets sent/received by the multicast connection
+ *	TODO: This function is almost similar to unicast connection_data_totals_update() except few
+ *	      lines of code. The next merge should have a common logic for both unicast and multicast.
+ */
+void ecm_db_multicast_connection_data_totals_update(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets)
+{
+	int32_t i;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+
+	if (is_from) {
+		/*
+		 * Update totals sent by the FROM side of connection
+		 */
+		ci->from_data_total += size;
+		ci->from_packet_total += packets;
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+		ci->mapping[ECM_DB_OBJ_DIR_FROM]->from_data_total += size;
+		ci->mapping[ECM_DB_OBJ_DIR_FROM]->host->from_data_total += size;
+		ci->node[ECM_DB_OBJ_DIR_FROM]->from_data_total += size;
+		ci->mapping[ECM_DB_OBJ_DIR_FROM]->from_packet_total += packets;
+		ci->mapping[ECM_DB_OBJ_DIR_FROM]->host->from_packet_total += packets;
+		ci->node[ECM_DB_OBJ_DIR_FROM]->from_packet_total += packets;
+
+		/*
+		 * Data from the host is essentially TO the interface on which the host is reachable
+		 */
+		for (i = ci->interface_first[ECM_DB_OBJ_DIR_FROM]; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+			ci->interfaces[ECM_DB_OBJ_DIR_FROM][i]->to_data_total += size;
+			ci->interfaces[ECM_DB_OBJ_DIR_FROM][i]->to_packet_total += packets;
+		}
+
+		/*
+		 * Update totals sent TO the other side of the connection
+		 */
+		ci->mapping[ECM_DB_OBJ_DIR_TO]->to_data_total += size;
+		ci->mapping[ECM_DB_OBJ_DIR_TO]->host->to_data_total += size;
+		ci->node[ECM_DB_OBJ_DIR_TO]->to_data_total += size;
+		ci->mapping[ECM_DB_OBJ_DIR_TO]->to_packet_total += packets;
+		ci->mapping[ECM_DB_OBJ_DIR_TO]->host->to_packet_total += packets;
+		ci->node[ECM_DB_OBJ_DIR_TO]->to_packet_total += packets;
+#endif
+		spin_unlock_bh(&ecm_db_lock);
+		return;
+	}
+
+	/*
+	 * Update totals sent by the TO side of this connection
+	 */
+	ci->to_data_total += size;
+	ci->to_packet_total += packets;
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	ci->mapping[ECM_DB_OBJ_DIR_TO]->from_data_total += size;
+	ci->mapping[ECM_DB_OBJ_DIR_TO]->host->from_data_total += size;
+	ci->node[ECM_DB_OBJ_DIR_TO]->from_data_total += size;
+	ci->mapping[ECM_DB_OBJ_DIR_TO]->from_packet_total += packets;
+	ci->mapping[ECM_DB_OBJ_DIR_TO]->host->from_packet_total += packets;
+	ci->node[ECM_DB_OBJ_DIR_TO]->from_packet_total += packets;
+
+	/*
+	 * Update totals sent TO the other side of the connection
+	 */
+	ci->mapping[ECM_DB_OBJ_DIR_FROM]->to_data_total += size;
+	ci->mapping[ECM_DB_OBJ_DIR_FROM]->host->to_data_total += size;
+	ci->node[ECM_DB_OBJ_DIR_FROM]->to_data_total += size;
+	ci->mapping[ECM_DB_OBJ_DIR_FROM]->to_packet_total += packets;
+	ci->mapping[ECM_DB_OBJ_DIR_FROM]->host->to_packet_total += packets;
+	ci->node[ECM_DB_OBJ_DIR_FROM]->to_packet_total += packets;
+
+	/*
+	 * Sending to the other side means FROM the interface we reach that host
+	 */
+	for (i = ci->interface_first[ECM_DB_OBJ_DIR_FROM]; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+		ci->interfaces[ECM_DB_OBJ_DIR_FROM][i]->from_data_total += size;
+		ci->interfaces[ECM_DB_OBJ_DIR_FROM][i]->from_packet_total += packets;
+	}
+#endif
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_multicast_connection_data_totals_update);
+
+/*
+ * ecm_db_multicast_connection_interface_heirarchy_stats_update()
+ * 	Traverse through the multicast destination interface heirarchy and update the stats (data and packets).
+ */
+void ecm_db_multicast_connection_interface_heirarchy_stats_update(struct ecm_db_connection_instance *ci, uint64_t size, uint64_t packets)
+{
+	struct ecm_db_iface_instance *to_mc_ifaces;
+	struct ecm_db_iface_instance *ii;
+	struct ecm_db_iface_instance **ifaces;
+	struct ecm_db_iface_instance *ii_temp;
+	int32_t *to_mc_ifaces_first;
+	int heirarchy_index;
+	int ret;
+
+	ret = ecm_db_multicast_connection_to_interfaces_get_and_ref_all(ci, &to_mc_ifaces, &to_mc_ifaces_first);
+	if (ret == 0) {
+		DEBUG_WARN("%px: no interfaces in to_multicast_interfaces list!\n", ci);
+		return;
+	}
+
+	spin_lock_bh(&ecm_db_lock);
+	for (heirarchy_index = 0; heirarchy_index < ECM_DB_MULTICAST_IF_MAX; heirarchy_index++) {
+
+		if (to_mc_ifaces_first[heirarchy_index] < ECM_DB_IFACE_HEIRARCHY_MAX) {
+			ii_temp = ecm_db_multicast_if_heirarchy_get(to_mc_ifaces, heirarchy_index);
+			ii_temp = ecm_db_multicast_if_instance_get_at_index(ii_temp, ECM_DB_IFACE_HEIRARCHY_MAX - 1);
+			ifaces = (struct ecm_db_iface_instance **)ii_temp;
+			ii = *ifaces;
+			ii->to_data_total += size;
+			ii->to_packet_total += packets;
+		}
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	ecm_db_multicast_connection_to_interfaces_deref_all(to_mc_ifaces, to_mc_ifaces_first);
+}
+EXPORT_SYMBOL(ecm_db_multicast_connection_interface_heirarchy_stats_update);
+
+/*
+ * _ecm_db_multicast_tuple_instance_deref()
+ * 	Deref the reference count or
+ * 	Free the tuple_instance struct, when the multicast connection dies
+ */
+int _ecm_db_multicast_tuple_instance_deref(struct ecm_db_multicast_tuple_instance *ti)
+{
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed", ti);
+	ti->refs--;
+	DEBUG_TRACE("%px: ti deref %d\n", ti, ti->refs);
+	DEBUG_ASSERT(ti->refs >= 0, "%px: ref wrap\n", ti);
+
+	if (ti->refs > 0) {
+		return ti->refs;
+	}
+
+	if (ti->flags & ECM_DB_MULTICAST_TUPLE_INSTANCE_FLAGS_INSERTED) {
+		if (!ti->prev) {
+			DEBUG_ASSERT(ecm_db_multicast_tuple_instance_table[ti->hash_index] == ti, "%px: hash table bad\n", ti);
+			ecm_db_multicast_tuple_instance_table[ti->hash_index] = ti->next;
+		} else {
+			ti->prev->next = ti->next;
+		}
+
+		if (ti->next) {
+			ti->next->prev = ti->prev;
+		}
+	}
+
+	if (ti->l2_br_dev) {
+		dev_put(ti->l2_br_dev);
+	}
+
+	if (ti->l3_br_dev) {
+		dev_put(ti->l3_br_dev);
+	}
+
+	DEBUG_CLEAR_MAGIC(ti);
+	kfree(ti);
+
+	return 0;
+}
+
+/*
+ * ecm_db_multicast_generate_hash_index()
+ * 	Calculate the hash index given a multicast group address.
+ */
+static inline ecm_db_multicast_tuple_instance_hash_t ecm_db_multicast_generate_hash_index(ip_addr_t address)
+{
+	uint32_t temp;
+	uint32_t hash_val;
+
+	if (ECM_IP_ADDR_IS_V4(address)){
+		temp = (uint32_t)address[0];
+	} else {
+		temp = (uint32_t)address[3];
+	}
+
+	hash_val = (uint32_t)jhash_1word(temp, ecm_db_jhash_rnd);
+
+	return (ecm_db_multicast_tuple_instance_hash_t)(hash_val & (ECM_DB_MULTICAST_TUPLE_INSTANCE_HASH_SLOTS - 1));
+}
+
+/*
+ * ecm_db_multicast_connection_to_interfaces_reset()
+ *	Reset the 'to' interfaces heirarchy with a new set of destination interfaces for
+ *	the multicast connection
+ */
+int ecm_db_multicast_connection_to_interfaces_reset(struct ecm_db_connection_instance *ci, struct ecm_db_iface_instance *interfaces, int32_t *new_first)
+{
+	struct ecm_db_iface_instance *ii_temp;
+	struct ecm_db_iface_instance *ii_single;
+	struct ecm_db_iface_instance **ifaces;
+	struct ecm_db_iface_instance *ii_db;
+	struct ecm_db_iface_instance *ii_db_single;
+	struct ecm_db_iface_instance **ifaces_db;
+	int32_t *nf_p;
+	int32_t heirarchy_index;
+	int32_t i;
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	/*
+	 * First remove all old interface hierarchies if any hierarchy
+	 * uphold in the ci->to_mcast_interfaces.
+	 */
+	ecm_db_multicast_connection_to_interfaces_clear(ci);
+
+	ci->to_mcast_interfaces = (struct ecm_db_iface_instance *)kzalloc(ECM_DB_TO_MCAST_INTERFACES_SIZE, GFP_ATOMIC | __GFP_NOWARN);
+	if (!ci->to_mcast_interfaces) {
+		DEBUG_WARN("%px: Memory is not available for to_mcast_interfaces\n", ci);
+		return -1;
+	}
+
+	/*
+	 * Iterate the to interface list and add the new interface hierarchies
+	 */
+	spin_lock_bh(&ecm_db_lock);
+
+	for (heirarchy_index = 0; heirarchy_index < ECM_DB_MULTICAST_IF_MAX; heirarchy_index++) {
+		ii_temp = ecm_db_multicast_if_heirarchy_get(interfaces, heirarchy_index);
+		nf_p = ecm_db_multicast_if_first_get_at_index(new_first, heirarchy_index);
+
+		if (*nf_p == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			continue;
+		}
+
+		for (i = *nf_p; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+
+			/*
+			 * Store valid dest interface list into DB connection
+			 */
+			ii_single = ecm_db_multicast_if_instance_get_at_index(ii_temp, i);
+			ifaces = (struct ecm_db_iface_instance **)ii_single;
+
+			ii_db = ecm_db_multicast_if_heirarchy_get(ci->to_mcast_interfaces, heirarchy_index);
+			ii_db_single = ecm_db_multicast_if_instance_get_at_index(ii_db, i);
+			ifaces_db = (struct ecm_db_iface_instance **)ii_db_single;
+
+			*ifaces_db = *ifaces;
+			_ecm_db_iface_ref(*ifaces_db);
+		}
+	}
+
+	/*
+	 * Update the first indices
+	 */
+	for (heirarchy_index = 0; heirarchy_index < ECM_DB_MULTICAST_IF_MAX; heirarchy_index++) {
+		nf_p = ecm_db_multicast_if_first_get_at_index(new_first, heirarchy_index);
+		ci->to_mcast_interface_first[heirarchy_index] = *nf_p;
+	}
+
+	ci->to_mcast_interfaces_set = true;
+	spin_unlock_bh(&ecm_db_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_db_multicast_connection_to_interfaces_reset);
+
+/*
+ *  ecm_db_multicast_connection_to_interfaces_update()
+ *  	Merge the latest valid multicast destination interfaces into DB Connection
+ *  	instance. The new list holds the updated list of interfaces for the multicast
+ *  	connection, due to JOIN updates.
+ */
+void ecm_db_multicast_connection_to_interfaces_update(struct ecm_db_connection_instance *ci,
+			struct ecm_db_iface_instance *interfaces, int32_t *mc_join_first, int32_t *mc_join_valid_idx)
+{
+	struct ecm_db_iface_instance *ii_temp;
+	struct ecm_db_iface_instance *ii_single;
+	struct ecm_db_iface_instance **ifaces;
+	struct ecm_db_iface_instance *ii_db;
+	struct ecm_db_iface_instance *ii_db_single;
+	struct ecm_db_iface_instance **ifaces_db;
+	int32_t *join_first;
+	int32_t *join_idx;
+	int heirarchy_index;
+	int32_t if_index;
+	int32_t i;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	/*
+	 * Iterate the to interface list, adding in the new
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	for (heirarchy_index = 0, if_index = 0; heirarchy_index < ECM_DB_MULTICAST_IF_MAX; heirarchy_index++) {
+		ii_temp = ecm_db_multicast_if_heirarchy_get(interfaces, if_index);
+		join_first = ecm_db_multicast_if_first_get_at_index(mc_join_first, if_index);
+		join_idx = ecm_db_multicast_if_num_get_at_index(mc_join_valid_idx, heirarchy_index);
+
+		if (*join_idx == 0) {
+
+			/*
+			 * No update for the interface at this index
+			 */
+			continue;
+		}
+
+		/*
+		 * This interface has joined the group. Add it to the list.
+		 */
+		if (*join_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			if_index++;
+			continue;
+		}
+
+		ci->to_mcast_interface_first[heirarchy_index] = *join_first;
+		for (i = *join_first; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+
+			/*
+			 * Store valid dest interface list into DB connection
+			 */
+			ii_single = ecm_db_multicast_if_instance_get_at_index(ii_temp, i);
+			ifaces = (struct ecm_db_iface_instance **)ii_single;
+			ii_db = ecm_db_multicast_if_heirarchy_get(ci->to_mcast_interfaces, heirarchy_index);
+			ii_db_single = ecm_db_multicast_if_instance_get_at_index(ii_db, i);
+			ifaces_db = (struct ecm_db_iface_instance **)ii_db_single;
+			*ifaces_db = *ifaces;
+			_ecm_db_iface_ref(*ifaces_db);
+		}
+		if_index++;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return;
+}
+EXPORT_SYMBOL(ecm_db_multicast_connection_to_interfaces_update);
+
+/*
+ *  _ecm_db_multicast_tuple_instance_ref()
+ * 	Increment tuple reference count by one
+ */
+static void _ecm_db_multicast_tuple_instance_ref(struct ecm_db_multicast_tuple_instance *ti)
+{
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed", ti);
+	ti->refs++;
+	DEBUG_TRACE("%px: ti ref %d\n", ti, ti->refs);
+	DEBUG_ASSERT(ti->refs > 0, "%px: ref wrap\n", ti)
+}
+
+/*
+ * ecm_db_multicast_alloc_connection()
+ * 	Allocate memory for the connection structure.
+ */
+struct ecm_db_multicast_tuple_instance *ecm_db_multicast_tuple_instance_alloc(ip_addr_t origin, ip_addr_t group, uint16_t src_port, uint16_t dst_port)
+{
+	struct ecm_db_multicast_tuple_instance *ti;
+	ti = (struct ecm_db_multicast_tuple_instance *)kzalloc(sizeof(struct ecm_db_multicast_tuple_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!ti) {
+		DEBUG_WARN("ti: Alloc failed\n");
+		return NULL;
+	}
+	ti->src_port = src_port;
+	ti->dst_port = dst_port;
+	ECM_IP_ADDR_COPY(ti->src_ip, origin);
+	ECM_IP_ADDR_COPY(ti->grp_ip, group);
+	ti->proto = IPPROTO_UDP;
+	ti->hash_index = ecm_db_multicast_generate_hash_index(group);
+	ti->flags = 0;
+	ti->refs = 1;
+	ti->next = NULL;
+	ti->prev = NULL;
+	ti->l2_br_dev = NULL;
+	ti->l3_br_dev = NULL;
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+	ti->ovs_ingress_vlan.h_vlan_TCI = 0;
+	ti->ovs_ingress_vlan.h_vlan_encapsulated_proto = 0;
+#endif
+	DEBUG_SET_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC);
+
+	return ti;
+}
+EXPORT_SYMBOL(ecm_db_multicast_tuple_instance_alloc);
+
+/*
+ * ecm_db_multicast_connection_find_and_ref()
+ * 	Called by MFC event update to fetch connection from the table
+ * 	This function takes a ref count for both tuple_instance and 'ci'
+ *	Call ecm_db_multicast_connection_deref function for deref both
+ *	'ti' and 'ci'
+ */
+struct ecm_db_multicast_tuple_instance *ecm_db_multicast_connection_find_and_ref(ip_addr_t origin, ip_addr_t group)
+{
+	ecm_db_multicast_tuple_instance_hash_t hash_index;
+	struct ecm_db_multicast_tuple_instance *ti;
+
+	/*
+	 * Compute the hash chain index
+	 */
+	hash_index = ecm_db_multicast_generate_hash_index(group);
+
+	spin_lock_bh(&ecm_db_lock);
+	ti = ecm_db_multicast_tuple_instance_table[hash_index];
+
+	/*
+	 * Traverse through the list and find the ti
+	 */
+	while (ti) {
+		if (!(ECM_IP_ADDR_MATCH(ti->src_ip, origin) && ECM_IP_ADDR_MATCH(ti->grp_ip, group))) {
+			ti = ti->next;
+			continue;
+		}
+
+		_ecm_db_multicast_tuple_instance_ref(ti);
+		_ecm_db_connection_ref(ti->ci);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("multicast tuple instance found %px\n", ti);
+		return ti;
+	}
+
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("multicast tuple instance not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_multicast_connection_find_and_ref);
+
+/*
+ * ecm_db_multicast_tuple_instance_deref()
+ * 	Deref the reference count or
+ * 	Free the tuple_instance struct, when the multicast connection dies
+ */
+int ecm_db_multicast_tuple_instance_deref(struct ecm_db_multicast_tuple_instance *ti)
+{
+	int refs;
+	spin_lock_bh(&ecm_db_lock);
+	refs = _ecm_db_multicast_tuple_instance_deref(ti);
+	spin_unlock_bh(&ecm_db_lock);
+	return refs;
+}
+EXPORT_SYMBOL(ecm_db_multicast_tuple_instance_deref);
+
+/*
+ * ecm_db_multicast_connection_deref()
+ * 	Deref both 'ti' and 'ci'
+ * 	call this function after ecm_db_multicast_connection_find_and_ref()
+ */
+void ecm_db_multicast_connection_deref(struct ecm_db_multicast_tuple_instance *ti)
+{
+	struct ecm_db_connection_instance *ci;
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed", ti);
+
+	ci = ti->ci;
+	ecm_db_multicast_tuple_instance_deref(ti);
+	ecm_db_connection_deref(ci);
+
+}
+EXPORT_SYMBOL(ecm_db_multicast_connection_deref);
+
+/*
+ * ecm_db_multicast_tuple_instance_add()
+ * 	Add the tuple instance into the hash table. Also, attach the tuple instance
+ * 	with connection instance.
+ *
+ * 	Note: This function takes a reference count and caller has to also call
+ * 	ecm_db_multicast_tuple_instance_deref() after this function.
+ */
+void ecm_db_multicast_tuple_instance_add(struct ecm_db_multicast_tuple_instance *ti, struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed", ti);
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_ASSERT(!(ti->flags & ECM_DB_MULTICAST_TUPLE_INSTANCE_FLAGS_INSERTED), "%px: inserted\n", ti);
+
+	/*
+	 * Attach the multicast tuple instance with the connection instance
+	 */
+	ci->ti = ti;
+	ti->ci = ci;
+
+	/*
+	 * Take a local reference to ti
+	 */
+	_ecm_db_multicast_tuple_instance_ref(ti);
+	ti->next = ecm_db_multicast_tuple_instance_table[ti->hash_index];
+	if (ecm_db_multicast_tuple_instance_table[ti->hash_index]) {
+		ecm_db_multicast_tuple_instance_table[ti->hash_index]->prev = ti;
+	}
+
+	ecm_db_multicast_tuple_instance_table[ti->hash_index] = ti;
+
+	ti->flags |= ECM_DB_MULTICAST_TUPLE_INSTANCE_FLAGS_INSERTED;
+	spin_unlock_bh(&ecm_db_lock);
+
+}
+EXPORT_SYMBOL(ecm_db_multicast_tuple_instance_add);
+
+/*
+ * ecm_db_multicast_connection_get_and_ref_first()
+ * 	Return the first tuple instance from the table when given a group
+ * 	Also take a ref count for 'ci', once done call ecm_db_multicast_connection_deref()
+ * 	to deref both 'ti' and 'ci'
+ */
+struct ecm_db_multicast_tuple_instance *ecm_db_multicast_connection_get_and_ref_first(ip_addr_t group)
+{
+	ecm_db_multicast_tuple_instance_hash_t hash_index;
+	struct ecm_db_multicast_tuple_instance *ti;
+
+	hash_index = ecm_db_multicast_generate_hash_index(group);
+
+	spin_lock_bh(&ecm_db_lock);
+	ti = ecm_db_multicast_tuple_instance_table[hash_index];
+	if (ti) {
+		_ecm_db_multicast_tuple_instance_ref(ti);
+		_ecm_db_connection_ref(ti->ci);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	return ti;
+}
+EXPORT_SYMBOL(ecm_db_multicast_connection_get_and_ref_first);
+
+/*
+ * ecm_db_multicast_connection_get_and_ref_next()
+ * 	Return the next tuple instance node and
+ * 	take a ref count for 'ci', once done call ecm_db_multicast_connection_deref()
+ * 	to deref both 'ti' and 'ci'
+ */
+struct ecm_db_multicast_tuple_instance *ecm_db_multicast_connection_get_and_ref_next(struct ecm_db_multicast_tuple_instance *ti)
+{
+	struct ecm_db_multicast_tuple_instance *tin;
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed", ti);
+	spin_lock_bh(&ecm_db_lock);
+	tin = ti->next;
+	if (tin) {
+		_ecm_db_multicast_tuple_instance_ref(tin);
+		_ecm_db_connection_ref(tin->ci);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return tin;
+}
+EXPORT_SYMBOL(ecm_db_multicast_connection_get_and_ref_next);
+
+/*
+ * ecm_db_multicast_tuple_instance_source_ip_get()
+ * 	This function return the source IP for a connection object
+ */
+void ecm_db_multicast_tuple_instance_source_ip_get(struct ecm_db_multicast_tuple_instance *ti, ip_addr_t origin)
+{
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed", ti);
+	ECM_IP_ADDR_COPY(origin, ti->src_ip);
+}
+EXPORT_SYMBOL(ecm_db_multicast_tuple_instance_source_ip_get);
+
+/*
+ * ecm_db_multicast_tuple_instance_group_ip_get()
+ * 	This function return the group IP for a connection object
+ */
+void ecm_db_multicast_tuple_instance_group_ip_get(struct ecm_db_multicast_tuple_instance *ti, ip_addr_t group)
+{
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed", ti);
+	ECM_IP_ADDR_COPY(group, ti->grp_ip);
+}
+EXPORT_SYMBOL(ecm_db_multicast_tuple_instance_group_ip_get);
+
+/*
+ * ecm_db_multicast_tuple_instance_flags_get()
+ * 	Return flags related to Multicast connection
+ */
+uint32_t ecm_db_multicast_tuple_instance_flags_get(struct ecm_db_multicast_tuple_instance *ti)
+{
+	uint32_t flags;
+
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed\n", ti);
+	spin_lock_bh(&ecm_db_lock);
+	flags = ti->flags;
+	spin_unlock_bh(&ecm_db_lock);
+	return flags;
+}
+EXPORT_SYMBOL(ecm_db_multicast_tuple_instance_flags_get);
+
+/*
+ * ecm_db_multicast_tuple_instance_flags_set()
+ * 	Set the multicast connection flags
+ */
+void ecm_db_multicast_tuple_instance_flags_set(struct ecm_db_multicast_tuple_instance *ti, uint32_t flags)
+{
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed\n", ti);
+
+	spin_lock_bh(&ecm_db_lock);
+	ti->flags |= flags;
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_multicast_tuple_instance_flags_set);
+
+/*
+ * ecm_db_multicast_tuple_instance_flags_clear()
+ * 	Clear the multicast connection flags
+ */
+void ecm_db_multicast_tuple_instance_flags_clear(struct ecm_db_multicast_tuple_instance *ti, uint32_t flags)
+{
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed\n", ti);
+
+	spin_lock_bh(&ecm_db_lock);
+	ti->flags &= ~flags;
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_multicast_tuple_instance_flags_clear);
+
+/*
+ * ecm_db_multicast_tuple_instance_set_and_hold_l2_br_dev()
+ * 	Save bridge device for L2 multicast flow
+ */
+void ecm_db_multicast_tuple_instance_set_and_hold_l2_br_dev(struct ecm_db_multicast_tuple_instance *ti, struct net_device *l2_br_dev)
+{
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed\n", ti);
+
+	DEBUG_ASSERT(l2_br_dev, "Invalid argument received. Expected a l2_br_dev");
+
+	spin_lock_bh(&ecm_db_lock);
+	ti->l2_br_dev = l2_br_dev;
+	dev_hold(ti->l2_br_dev);
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_multicast_tuple_instance_set_and_hold_l2_br_dev);
+
+/*
+ * ecm_db_multicast_tuple_instance_set_and_hold_l3_br_dev()
+ * 	Save bridge device for L3 multicast flow
+ */
+void ecm_db_multicast_tuple_instance_set_and_hold_l3_br_dev(struct ecm_db_multicast_tuple_instance *ti, struct net_device *l3_br_dev)
+{
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed\n", ti);
+
+	DEBUG_ASSERT(l3_br_dev, "Invalid argument received. Expected a l3_br_dev");
+
+	spin_lock_bh(&ecm_db_lock);
+	ti->l3_br_dev = l3_br_dev;
+	dev_hold(ti->l3_br_dev);
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_multicast_tuple_instance_set_and_hold_l3_br_dev);
+
+/*
+ * ecm_db_multicast_tuple_instance_get_l2_br_dev()
+ * 	Return bridge device for L2 multicast flow
+ */
+struct net_device *ecm_db_multicast_tuple_instance_get_l2_br_dev(struct ecm_db_multicast_tuple_instance *ti)
+{
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed\n", ti);
+	return ti->l2_br_dev;
+}
+EXPORT_SYMBOL(ecm_db_multicast_tuple_instance_get_l2_br_dev);
+
+/*
+ * ecm_db_multicast_tuple_instance_get_l3_br_dev()
+ * 	Return bridge device for L3 multicast flow
+ */
+struct net_device *ecm_db_multicast_tuple_instance_get_l3_br_dev(struct ecm_db_multicast_tuple_instance *ti)
+{
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed\n", ti);
+	return ti->l3_br_dev;
+}
+EXPORT_SYMBOL(ecm_db_multicast_tuple_instance_get_l3_br_dev);
+
+/*
+ * ecm_db_multicast_connection_to_interfaces_get_and_ref_all()
+ *	Return the list of multicast destination interface heirarchies to which this connection is established.
+ *	The function returns the heirarchies using the 'interface' pointer passed to it. It also returns the first
+ *	index in the interface heirarchy for each of the heirarchies using the 'ifaces_first' pointer.
+ *
+ * NOTE: This function allocates the memory for the destination interface heirachy. This memory is expected to be
+ * freed only by making a call to ecm_db_multicast_connection_interfaces_deref_all().
+ *
+ * The size of the buffer allocated for the heirarchies and pointed to by 'interfaces' is as large as
+ * sizeof(struct ecm_db_iface_instance *) * ECM_DB_MULTICAST_IF_MAX * ECM_DB_IFACE_HEIRARCHY_MAX.
+ * Returns the number of interface heirarchies in the list as a return value.
+ *
+ * Each interface is referenced on return, be sure to release them using ecm_db_multicast_connection_interfaces_deref_all().
+ */
+int32_t ecm_db_multicast_connection_to_interfaces_get_and_ref_all(struct ecm_db_connection_instance *ci,
+						struct ecm_db_iface_instance **interfaces, int32_t **ifaces_first)
+{
+	struct ecm_db_iface_instance *heirarchy_base;
+	struct ecm_db_iface_instance *heirarchy_temp;
+	struct ecm_db_iface_instance *ii_single;
+	struct ecm_db_iface_instance **ifaces;
+	struct ecm_db_iface_instance *ii_db;
+	struct ecm_db_iface_instance *ii_db_single;
+	struct ecm_db_iface_instance **ifaces_db;
+	int32_t *ii_first_base;
+	int32_t *ii_first;
+	int32_t heirarchy_index;
+	int32_t ii_index;
+	int32_t if_count = 0;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	heirarchy_base = (struct ecm_db_iface_instance *)kzalloc(ECM_DB_TO_MCAST_INTERFACES_SIZE, GFP_ATOMIC | __GFP_NOWARN);
+	if (!heirarchy_base) {
+		DEBUG_WARN("%px: No memory for interface hierarchies \n", ci);
+		return if_count;
+	}
+
+	ii_first_base = (int32_t *)kzalloc(sizeof(int32_t *) * ECM_DB_MULTICAST_IF_MAX, GFP_ATOMIC | __GFP_NOWARN);
+	if (!ii_first_base) {
+		DEBUG_WARN("%px: No memory for first interface \n", ci);
+		kfree(heirarchy_base);
+		return if_count;
+	}
+
+	spin_lock_bh(&ecm_db_lock);
+	if (!ci->to_mcast_interfaces_set) {
+		spin_unlock_bh(&ecm_db_lock);
+		kfree(ii_first_base);
+		kfree(heirarchy_base);
+		return if_count;
+	}
+
+	for (heirarchy_index = 0; heirarchy_index < ECM_DB_MULTICAST_IF_MAX; heirarchy_index++) {
+
+		heirarchy_temp = ecm_db_multicast_if_heirarchy_get(heirarchy_base, heirarchy_index);
+
+		if (ci->to_mcast_interface_first[heirarchy_index] < ECM_DB_IFACE_HEIRARCHY_MAX) {
+			if_count++;
+		}
+
+		for (ii_index = ci->to_mcast_interface_first[heirarchy_index]; ii_index < ECM_DB_IFACE_HEIRARCHY_MAX; ++ii_index) {
+			ii_db = ecm_db_multicast_if_heirarchy_get(ci->to_mcast_interfaces, heirarchy_index);
+			ii_db_single = ecm_db_multicast_if_instance_get_at_index(ii_db, ii_index);
+			ifaces_db = (struct ecm_db_iface_instance **)ii_db_single;
+
+			/*
+			 * Take a reference count
+			 */
+			_ecm_db_iface_ref(*ifaces_db);
+
+			ii_single = ecm_db_multicast_if_instance_get_at_index(heirarchy_temp, ii_index);
+			ifaces = (struct ecm_db_iface_instance **)ii_single;
+			*ifaces = *ifaces_db;
+		}
+
+		ii_first = ecm_db_multicast_if_first_get_at_index(ii_first_base, heirarchy_index);
+		*ii_first = ci->to_mcast_interface_first[heirarchy_index];
+	}
+
+	*interfaces = heirarchy_base;
+	*ifaces_first = ii_first_base;
+
+	spin_unlock_bh(&ecm_db_lock);
+	return if_count;
+}
+EXPORT_SYMBOL(ecm_db_multicast_connection_to_interfaces_get_and_ref_all);
+
+/*
+ * ecm_db_multicast_connection_to_interfaces_set_check()
+ *	Returns true if the multicast destination interfaces list has been set.
+ */
+bool ecm_db_multicast_connection_to_interfaces_set_check(struct ecm_db_connection_instance *ci)
+{
+	bool set;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+	spin_lock_bh(&ecm_db_lock);
+	set = ci->to_mcast_interfaces_set;
+	spin_unlock_bh(&ecm_db_lock);
+	return set;
+}
+EXPORT_SYMBOL(ecm_db_multicast_connection_to_interfaces_set_check);
+
+/*
+ * ecm_db_multicast_connection_to_interfaces_set_clear()
+ *	Clear the to_mcast_interfaces_set flag if the multicast destination interfaces list has been freed.
+ */
+static void  _ecm_db_multicast_connection_to_interfaces_set_clear(struct ecm_db_connection_instance *ci)
+{
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+	ci->to_mcast_interfaces_set = false;
+}
+
+/*
+ * ecm_db_multicast_connection_get_from_tuple()
+ * 	Return the connection instance
+ */
+struct ecm_db_connection_instance *ecm_db_multicast_connection_get_from_tuple(struct ecm_db_multicast_tuple_instance *ti)
+{
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed", ti);
+	DEBUG_ASSERT(ti->ci, "%px: Bad multicast connection instance \n", ti);
+
+	return ti->ci;
+}
+EXPORT_SYMBOL(ecm_db_multicast_connection_get_from_tuple);
+
+/*
+ * ecm_db_multicast_connection_to_interfaces_deref_all()
+ * 	Deref all destination multicast interface heirarchies at once
+ */
+void ecm_db_multicast_connection_to_interfaces_deref_all(struct ecm_db_iface_instance *interfaces, int32_t *ifaces_first)
+{
+	struct ecm_db_iface_instance *ifaces_single;
+	struct ecm_db_iface_instance *ii_temp[ECM_DB_IFACE_HEIRARCHY_MAX];
+	int32_t *to_first;
+	int heirarchy_index;
+	DEBUG_ASSERT(interfaces, "Bad memory, multicast interfaces list has been already freed\n");
+	DEBUG_ASSERT(ifaces_first, "Bad memory, multicast interfaces first has been already freed\n");
+
+	for (heirarchy_index = 0; heirarchy_index < ECM_DB_MULTICAST_IF_MAX; heirarchy_index++) {
+		to_first = ecm_db_multicast_if_first_get_at_index(ifaces_first, heirarchy_index);
+		if (*to_first < ECM_DB_IFACE_HEIRARCHY_MAX) {
+			ifaces_single = ecm_db_multicast_if_heirarchy_get(interfaces, heirarchy_index);
+			ecm_db_multicast_copy_if_heirarchy(ii_temp, ifaces_single);
+			ecm_db_connection_interfaces_deref(ii_temp, *to_first);
+		}
+	}
+
+	/*
+	 * Free the temporary memory allocated by ecm_db_multicast_connection_to_interfaces_get_and_ref_all()
+	 */
+	kfree(interfaces);
+	kfree(ifaces_first);
+
+}
+EXPORT_SYMBOL(ecm_db_multicast_connection_to_interfaces_deref_all);
+
+/*
+ * _ecm_db_multicast_connection_to_interface_first_is_valid()
+ * 	Check if destnation interfaces first list uphold a valid interface
+ * 	first or all entries have discarded.
+ */
+static bool _ecm_db_multicast_connection_to_interface_first_is_valid(int32_t ifaces_first[])
+{
+	int heirarchy_index;
+
+	for (heirarchy_index = 0; heirarchy_index < ECM_DB_MULTICAST_IF_MAX; heirarchy_index++) {
+		if (ifaces_first[heirarchy_index] < ECM_DB_IFACE_HEIRARCHY_MAX) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+/*
+ * ecm_db_multicast_connection_to_interfaces_clear_at_index()
+ * 	Dereference and clear a interface heirarchy at 'index' position
+ */
+void ecm_db_multicast_connection_to_interfaces_clear_at_index(struct ecm_db_connection_instance *ci, uint32_t index)
+{
+	struct ecm_db_iface_instance *discard[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *ifaces_db_single;
+	int32_t discard_first;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	/*
+	 * Invalid Index Value
+	 */
+	DEBUG_ASSERT((index < ECM_DB_MULTICAST_IF_MAX), "%px: Invalid index for multicast interface heirarchies list %u\n", ci, index);
+
+	spin_lock_bh(&ecm_db_lock);
+	if (ci->to_mcast_interface_first[index] == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		spin_unlock_bh(&ecm_db_lock);
+		return;
+	}
+
+	ifaces_db_single = ecm_db_multicast_if_heirarchy_get(ci->to_mcast_interfaces, index);
+	ecm_db_multicast_copy_if_heirarchy(discard, ifaces_db_single);
+
+	discard_first = ci->to_mcast_interface_first[index];
+	ci->to_mcast_interface_first[index] = ECM_DB_IFACE_HEIRARCHY_MAX;
+
+	/*
+	 * If this is the only valid interface hierarchy left in the list of destination
+	 * interface hierarchies then clear the ci->to_mcast_interfaces_set flag here before
+	 * deleting this.
+	 */
+	if (!_ecm_db_multicast_connection_to_interface_first_is_valid(ci->to_mcast_interface_first)) {
+		ci->to_mcast_interfaces_set = false;
+	}
+
+	spin_unlock_bh(&ecm_db_lock);
+
+	ecm_db_connection_interfaces_deref(discard, discard_first);
+}
+EXPORT_SYMBOL(ecm_db_multicast_connection_to_interfaces_clear_at_index);
+
+/*
+ * ecm_db_multicast_connection_to_interfaces_get_count()
+ * 	Get the number of to interfaces for a connection
+ */
+int ecm_db_multicast_connection_to_interfaces_get_count(struct ecm_db_connection_instance *ci)
+{
+	int heirarchy_index, count = 0;
+
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	for (heirarchy_index = 0; heirarchy_index < ECM_DB_MULTICAST_IF_MAX; heirarchy_index++) {
+		if (ci->to_mcast_interface_first[heirarchy_index] < ECM_DB_IFACE_HEIRARCHY_MAX) {
+			count++;
+		}
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	return count;
+}
+EXPORT_SYMBOL(ecm_db_multicast_connection_to_interfaces_get_count);
+
+/*
+ * ecm_db_multicast_connection_to_interfaces_clear()
+ * 	Deref and clear all destination multicast interface heirarchies
+ */
+void ecm_db_multicast_connection_to_interfaces_clear(struct ecm_db_connection_instance *ci)
+{
+	int heirarchy_index;
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci);
+
+	spin_lock_bh(&ecm_db_lock);
+	if (!ci->to_mcast_interfaces) {
+		spin_unlock_bh(&ecm_db_lock);
+		return;
+	}
+
+	_ecm_db_multicast_connection_to_interfaces_set_clear(ci);
+	spin_unlock_bh(&ecm_db_lock);
+
+	for (heirarchy_index = 0; heirarchy_index < ECM_DB_MULTICAST_IF_MAX; heirarchy_index++) {
+		ecm_db_multicast_connection_to_interfaces_clear_at_index(ci, heirarchy_index);
+	}
+
+	spin_lock_bh(&ecm_db_lock);
+	kfree(ci->to_mcast_interfaces);
+	ci->to_mcast_interfaces = NULL;
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_multicast_connection_to_interfaces_clear);
+
+/*
+ * ecm_db_multicast_to_interfaces_xml_state_get()
+ *	Obtain XML state for the multicast destination interfaces list
+ */
+int ecm_db_multicast_to_interfaces_xml_state_get(struct ecm_db_connection_instance *ci, struct ecm_state_file_instance *sfi)
+{
+	struct ecm_db_iface_instance *mc_ifaces;
+	struct ecm_db_iface_instance *mc_ifaces_single[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *ii_temp;
+	int32_t *mc_ifaces_first;
+	int32_t *ifaces_first;
+	int32_t heirarchy_index;
+	int ret;
+
+	ret = ecm_db_multicast_connection_to_interfaces_get_and_ref_all(ci, &mc_ifaces, &mc_ifaces_first);
+	if (ret == 0) {
+		return ret;
+	}
+
+	for (heirarchy_index = 0; heirarchy_index < ECM_DB_MULTICAST_IF_MAX; heirarchy_index++) {
+
+		ii_temp = ecm_db_multicast_if_heirarchy_get(mc_ifaces, heirarchy_index);
+		ecm_db_multicast_copy_if_heirarchy(mc_ifaces_single, ii_temp);
+		ifaces_first = ecm_db_multicast_if_first_get_at_index(mc_ifaces_first, heirarchy_index);
+
+		if (ci->to_mcast_interface_first[heirarchy_index] < ECM_DB_IFACE_HEIRARCHY_MAX) {
+			ret = ecm_db_connection_heirarchy_state_get(sfi, mc_ifaces_single, *ifaces_first);
+			if (ret) {
+				ecm_db_multicast_connection_to_interfaces_deref_all(mc_ifaces, mc_ifaces_first);
+				return ret;
+			}
+
+		}
+	}
+	ecm_db_multicast_connection_to_interfaces_deref_all(mc_ifaces, mc_ifaces_first);
+
+	return ret;
+}
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+/*
+ * ecm_db_multicast_ovs_verify_to_list()
+ * 	Verify the 'to' interface list with OVS classifier.
+ */
+bool ecm_db_multicast_ovs_verify_to_list(struct ecm_db_connection_instance *ci, struct ecm_classifier_process_response *aci_pr)
+{
+	struct ecm_classifier_instance *aci;
+	bool is_defunct = false;
+
+	/*
+	 * Get the OVS classifier instance from the connection.
+	 */
+	aci = ecm_db_connection_assigned_classifier_find_and_ref(ci, ECM_CLASSIFIER_TYPE_OVS);
+	if (!aci) {
+		DEBUG_WARN("%px: no OVS classifier\n", ci);
+		return is_defunct;
+	}
+
+	aci->process(aci, ECM_TRACKER_SENDER_MAX, NULL, NULL, aci_pr);
+	if (aci_pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_MCAST_DENY_ACCEL) {
+		is_defunct = true;
+	}
+
+	aci->deref(aci);
+	return is_defunct;
+}
+
+/*
+ * ecm_db_multicast_tuple_set_ovs_ingress_vlan()
+ * 	Set ingress VLAN tag for OVS ports.
+ */
+void ecm_db_multicast_tuple_set_ovs_ingress_vlan(struct ecm_db_multicast_tuple_instance *ti, uint32_t *ingress_vlan_tag)
+{
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed", ti);
+
+	ti->ovs_ingress_vlan.h_vlan_TCI = ingress_vlan_tag[0] & 0xffff;
+	ti->ovs_ingress_vlan.h_vlan_encapsulated_proto = (ingress_vlan_tag[0] >> 16) & 0xffff;
+}
+
+/*
+ * ecm_db_multicast_tuple_get_ovs_ingress_vlan()
+ * 	Get ingress VLAN tag for OVS ports.
+ */
+struct vlan_hdr ecm_db_multicast_tuple_get_ovs_ingress_vlan(struct ecm_db_multicast_tuple_instance *ti)
+{
+	DEBUG_CHECK_MAGIC(ti, ECM_DB_MULTICAST_INSTANCE_MAGIC, "%px: magic failed", ti);
+
+	return ti->ovs_ingress_vlan;
+}
+#endif
+#endif
+
+/*
+ * ecm_db_multicast_connection_to_interfaces_leave()
+ * 	Remove 'to' interfaces from the connection if it has left the group.
+ */
+void ecm_db_multicast_connection_to_interfaces_leave(struct ecm_db_connection_instance *ci, struct ecm_multicast_if_update *mc_update)
+{
+	int i;
+
+	if (!mc_update->if_leave_cnt) {
+		return;
+	}
+
+	for (i = 0; i < ECM_DB_MULTICAST_IF_MAX && mc_update->if_leave_cnt; i++) {
+		/*
+		 * Is this entry marked? If yes, then the corresponding entry
+		 * in the 'to_mcast_interfaces' array in the ci has left the
+		 * connection.
+		 */
+		if (!mc_update->if_leave_idx[i]) {
+			continue;
+		}
+
+		/*
+		 * Release the interface heirarchy for this
+		 * interface since it has left the group
+		 */
+		ecm_db_multicast_connection_to_interfaces_clear_at_index(ci, i);
+		mc_update->if_leave_cnt--;
+	}
+}
+#endif
diff --git a/qca-nss-ecm/ecm_db/ecm_db_multicast.h b/qca-nss-ecm/ecm_db/ecm_db_multicast.h
new file mode 100644
index 0000000..1b3e319
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_multicast.h
@@ -0,0 +1,73 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifdef ECM_MULTICAST_ENABLE
+struct ecm_db_multicast_tuple_instance *
+ecm_db_multicast_tuple_instance_alloc(ip_addr_t origin,
+				      ip_addr_t group,
+				      uint16_t src_port,
+				      uint16_t dst_port);
+int ecm_db_multicast_tuple_instance_deref(struct ecm_db_multicast_tuple_instance *ti);
+void ecm_db_multicast_connection_deref(struct ecm_db_multicast_tuple_instance *ti);
+void ecm_db_multicast_tuple_instance_add(struct ecm_db_multicast_tuple_instance *ti,
+					 struct ecm_db_connection_instance *ci);
+struct ecm_db_multicast_tuple_instance *ecm_db_multicast_connection_find_and_ref(ip_addr_t origin,
+										 ip_addr_t group);
+struct ecm_db_multicast_tuple_instance *ecm_db_multicast_connection_get_and_ref_first(ip_addr_t group);
+struct ecm_db_multicast_tuple_instance *ecm_db_multicast_connection_get_and_ref_next(struct ecm_db_multicast_tuple_instance *ti);
+void ecm_db_multicast_tuple_instance_source_ip_get(struct ecm_db_multicast_tuple_instance *ti, ip_addr_t origin);
+void ecm_db_multicast_tuple_instance_group_ip_get(struct ecm_db_multicast_tuple_instance *ti, ip_addr_t group);
+uint32_t ecm_db_multicast_tuple_instance_flags_get(struct ecm_db_multicast_tuple_instance *ti);
+void ecm_db_multicast_tuple_instance_flags_set(struct ecm_db_multicast_tuple_instance *ti, uint32_t flags);
+void ecm_db_multicast_tuple_instance_flags_clear(struct ecm_db_multicast_tuple_instance *ti, uint32_t flags);
+void ecm_db_multicast_tuple_instance_set_and_hold_l2_br_dev(struct ecm_db_multicast_tuple_instance *ti, struct net_device *l2_br_dev);
+void ecm_db_multicast_tuple_instance_set_and_hold_l3_br_dev(struct ecm_db_multicast_tuple_instance *ti, struct net_device *l3_br_dev);
+struct net_device *ecm_db_multicast_tuple_instance_get_l2_br_dev(struct ecm_db_multicast_tuple_instance *ti);
+struct net_device *ecm_db_multicast_tuple_instance_get_l3_br_dev(struct ecm_db_multicast_tuple_instance *ti);
+
+struct ecm_db_connection_instance *ecm_db_multicast_connection_get_from_tuple(struct ecm_db_multicast_tuple_instance *ti);
+void ecm_db_multicast_connection_to_interfaces_deref_all(struct ecm_db_iface_instance *interfaces, int32_t *ifaces_first);
+void ecm_db_multicast_connection_to_interfaces_clear(struct ecm_db_connection_instance *ci);
+int32_t ecm_db_multicast_connection_to_interfaces_get_and_ref_all(struct ecm_db_connection_instance *ci,
+								  struct ecm_db_iface_instance **interfaces,
+								  int32_t **to_ifaces_first);
+int ecm_db_multicast_connection_to_interfaces_reset(struct ecm_db_connection_instance *ci,
+						    struct ecm_db_iface_instance *interfaces,
+						    int32_t *new_first);
+void ecm_db_multicast_connection_to_interfaces_update(struct ecm_db_connection_instance *ci,
+						      struct ecm_db_iface_instance *interfaces,
+						      int32_t *new_first, int *join_valid_idx);
+void ecm_db_multicast_connection_data_totals_update(struct ecm_db_connection_instance *ci,
+						    bool is_from, uint64_t size, uint64_t packets);
+void ecm_db_multicast_connection_to_interfaces_clear_at_index(struct ecm_db_connection_instance *ci,
+							      uint32_t index);
+void ecm_db_multicast_connection_data_totals_update(struct ecm_db_connection_instance *ci,
+						    bool is_from, uint64_t size, uint64_t packets);
+void ecm_db_multicast_connection_interface_heirarchy_stats_update(struct ecm_db_connection_instance *ci,
+								  uint64_t size, uint64_t packets);
+bool ecm_db_multicast_connection_to_interfaces_set_check(struct ecm_db_connection_instance *ci);
+int _ecm_db_multicast_tuple_instance_deref(struct ecm_db_multicast_tuple_instance *ti);
+int ecm_db_multicast_to_interfaces_xml_state_get(struct ecm_db_connection_instance *ci, struct ecm_state_file_instance *sfi);
+int ecm_db_multicast_connection_to_interfaces_get_count(struct ecm_db_connection_instance *ci);
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+bool ecm_db_multicast_ovs_verify_to_list(struct ecm_db_connection_instance *ci, struct ecm_classifier_process_response *aci_pr);
+void ecm_db_multicast_tuple_set_ovs_ingress_vlan(struct ecm_db_multicast_tuple_instance *ti, uint32_t *ingress_vlan_tag);
+struct vlan_hdr ecm_db_multicast_tuple_get_ovs_ingress_vlan(struct ecm_db_multicast_tuple_instance *ti);
+#endif
+#endif
+void ecm_db_multicast_connection_to_interfaces_leave(struct ecm_db_connection_instance *ci, struct ecm_multicast_if_update *mc_update);
+#endif
diff --git a/qca-nss-ecm/ecm_db/ecm_db_node.c b/qca-nss-ecm/ecm_db/ecm_db_node.c
new file mode 100644
index 0000000..18d6aba
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_node.c
@@ -0,0 +1,1230 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <linux/random.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <net/ip6_route.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_DB_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_classifier_default.h"
+#include "ecm_db.h"
+
+/*
+ * Global list.
+ * All instances are inserted into global list - this allows easy iteration of all instances of a particular type.
+ * The list is doubly linked for fast removal.  The list is in no particular order.
+ */
+struct ecm_db_node_instance *ecm_db_nodes = NULL;
+
+/*
+ * Node hash table
+ */
+#define ECM_DB_NODE_HASH_SLOTS 32768
+static struct ecm_db_node_instance **ecm_db_node_table;
+							/* Slots of the node hash table */
+static int *ecm_db_node_table_lengths;
+							/* Tracks how long each chain is */
+static int ecm_db_node_count = 0;			/* Number of nodes allocated */
+
+/*
+ * Node flags
+ */
+#define ECM_DB_NODE_FLAGS_INSERTED 1			/* Node is inserted into connection database tables */
+
+/*
+ * ecm_db_node_generate_hash_index()
+ * 	Calculate the hash index.
+ */
+static inline ecm_db_node_hash_t ecm_db_node_generate_hash_index(uint8_t *address)
+{
+	uint32_t hash_val;
+
+	hash_val = (uint32_t)jhash(address, 6, ecm_db_jhash_rnd);
+	hash_val &= (ECM_DB_NODE_HASH_SLOTS - 1);
+
+	return (ecm_db_node_hash_t)hash_val;
+}
+
+/*
+ * _ecm_db_node_count_get()
+ *	Return the node count (lockless).
+ */
+int _ecm_db_node_count_get(void)
+{
+	return ecm_db_node_count;
+}
+
+/*
+ * _ecm_db_node_ref()
+ */
+void _ecm_db_node_ref(struct ecm_db_node_instance *ni)
+{
+	DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed\n", ni);
+	ni->refs++;
+	DEBUG_TRACE("%px: node ref %d\n", ni, ni->refs);
+	DEBUG_ASSERT(ni->refs > 0, "%px: ref wrap\n", ni);
+}
+
+/*
+ * ecm_db_node_ref()
+ */
+void ecm_db_node_ref(struct ecm_db_node_instance *ni)
+{
+	spin_lock_bh(&ecm_db_lock);
+	_ecm_db_node_ref(ni);
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_node_ref);
+
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+/*
+ * ecm_db_node_data_stats_get()
+ *	Return data stats for the instance
+ */
+void ecm_db_node_data_stats_get(struct ecm_db_node_instance *ni, uint64_t *from_data_total, uint64_t *to_data_total,
+						uint64_t *from_packet_total, uint64_t *to_packet_total,
+						uint64_t *from_data_total_dropped, uint64_t *to_data_total_dropped,
+						uint64_t *from_packet_total_dropped, uint64_t *to_packet_total_dropped)
+{
+	DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed", ni);
+	spin_lock_bh(&ecm_db_lock);
+	if (from_data_total) {
+		*from_data_total = ni->from_data_total;
+	}
+	if (to_data_total) {
+		*to_data_total = ni->to_data_total;
+	}
+	if (from_packet_total) {
+		*from_packet_total = ni->from_packet_total;
+	}
+	if (to_packet_total) {
+		*to_packet_total = ni->to_packet_total;
+	}
+	if (from_data_total_dropped) {
+		*from_data_total_dropped = ni->from_data_total_dropped;
+	}
+	if (to_data_total_dropped) {
+		*to_data_total_dropped = ni->to_data_total_dropped;
+	}
+	if (from_packet_total_dropped) {
+		*from_packet_total_dropped = ni->from_packet_total_dropped;
+	}
+	if (to_packet_total_dropped) {
+		*to_packet_total_dropped = ni->to_packet_total_dropped;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_node_data_stats_get);
+#endif
+
+/*
+ * ecm_db_node_adress_get()
+ *	Return address
+ */
+void ecm_db_node_adress_get(struct ecm_db_node_instance *ni, uint8_t *address_buffer)
+{
+	DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed", ni);
+	memcpy(address_buffer, ni->address, ETH_ALEN);
+}
+EXPORT_SYMBOL(ecm_db_node_adress_get);
+
+/*
+ * ecm_db_nodes_get_and_ref_first()
+ *	Obtain a ref to the first node instance, if any
+ */
+struct ecm_db_node_instance *ecm_db_nodes_get_and_ref_first(void)
+{
+	struct ecm_db_node_instance *ni;
+	spin_lock_bh(&ecm_db_lock);
+	ni = ecm_db_nodes;
+	if (ni) {
+		_ecm_db_node_ref(ni);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return ni;
+}
+EXPORT_SYMBOL(ecm_db_nodes_get_and_ref_first);
+
+/*
+ * ecm_db_node_get_and_ref_next()
+ *	Return the next node in the list given a node
+ */
+struct ecm_db_node_instance *ecm_db_node_get_and_ref_next(struct ecm_db_node_instance *ni)
+{
+	struct ecm_db_node_instance *nin;
+	DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed", ni);
+	spin_lock_bh(&ecm_db_lock);
+	nin = ni->next;
+	if (nin) {
+		_ecm_db_node_ref(nin);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return nin;
+}
+EXPORT_SYMBOL(ecm_db_node_get_and_ref_next);
+
+/*
+ * ecm_db_node_deref()
+ *	Deref a node.  Removing it on the last ref and destroying it.
+ */
+int ecm_db_node_deref(struct ecm_db_node_instance *ni)
+{
+#if (DEBUG_LEVEL >= 1)
+	int dir;
+#endif
+	DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed\n", ni);
+
+	spin_lock_bh(&ecm_db_lock);
+	ni->refs--;
+	DEBUG_TRACE("%px: node deref %d\n", ni, ni->refs);
+	DEBUG_ASSERT(ni->refs >= 0, "%px: ref wrap\n", ni);
+
+	if (ni->refs > 0) {
+		int refs = ni->refs;
+		spin_unlock_bh(&ecm_db_lock);
+		return refs;
+	}
+
+#ifdef ECM_DB_XREF_ENABLE
+#if (DEBUG_LEVEL >= 1)
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		DEBUG_ASSERT((ni->connections[dir] == NULL) && (ni->connections_count[dir] == 0), "%px: %s connections not null\n", ni, ecm_db_obj_dir_strings[dir]);
+	}
+#endif
+#endif
+
+	/*
+	 * Remove from database if inserted
+	 */
+	if (!ni->flags & ECM_DB_NODE_FLAGS_INSERTED) {
+		spin_unlock_bh(&ecm_db_lock);
+	} else {
+		struct ecm_db_listener_instance *li;
+
+		/*
+		 * Remove from the global list
+		 */
+		if (!ni->prev) {
+			DEBUG_ASSERT(ecm_db_nodes == ni, "%px: node table bad\n", ni);
+			ecm_db_nodes = ni->next;
+		} else {
+			ni->prev->next = ni->next;
+		}
+		if (ni->next) {
+			ni->next->prev = ni->prev;
+		}
+		ni->prev = NULL;
+		ni->next = NULL;
+
+		/*
+		 * Link out of hash table
+		 */
+		if (!ni->hash_prev) {
+			DEBUG_ASSERT(ecm_db_node_table[ni->hash_index] == ni, "%px: hash table bad\n", ni);
+			ecm_db_node_table[ni->hash_index] = ni->hash_next;
+		} else {
+			ni->hash_prev->hash_next = ni->hash_next;
+		}
+		if (ni->hash_next) {
+			ni->hash_next->hash_prev = ni->hash_prev;
+		}
+		ni->hash_next = NULL;
+		ni->hash_prev = NULL;
+		ecm_db_node_table_lengths[ni->hash_index]--;
+		DEBUG_ASSERT(ecm_db_node_table_lengths[ni->hash_index] >= 0, "%px: invalid table len %d\n", ni, ecm_db_node_table_lengths[ni->hash_index]);
+
+#ifdef ECM_DB_XREF_ENABLE
+		/*
+		 * Unlink it from the iface node list
+		 */
+		if (!ni->node_prev) {
+			DEBUG_ASSERT(ni->iface->nodes == ni, "%px: nodes table bad\n", ni);
+			ni->iface->nodes = ni->node_next;
+		} else {
+			ni->node_prev->node_next = ni->node_next;
+		}
+		if (ni->node_next) {
+			ni->node_next->node_prev = ni->node_prev;
+		}
+		ni->node_next = NULL;
+		ni->node_prev = NULL;
+		ni->iface->node_count--;
+#endif
+
+		spin_unlock_bh(&ecm_db_lock);
+
+		/*
+		 * Throw removed event to listeners
+		 */
+		DEBUG_TRACE("%px: Throw node removed event\n", ni);
+		li = ecm_db_listeners_get_and_ref_first();
+		while (li) {
+			struct ecm_db_listener_instance *lin;
+			if (li->node_removed) {
+				li->node_removed(li->arg, ni);
+			}
+
+			/*
+			 * Get next listener
+			 */
+			lin = ecm_db_listener_get_and_ref_next(li);
+			ecm_db_listener_deref(li);
+			li = lin;
+		}
+	}
+
+	/*
+	 * Throw final event
+	 */
+	if (ni->final) {
+		ni->final(ni->arg);
+	}
+
+	/*
+	 * Now release the iface instance if the node had one
+	 */
+	if (ni->iface) {
+		ecm_db_iface_deref(ni->iface);
+	}
+
+	/*
+	 * We can now destroy the instance
+	 */
+	DEBUG_CLEAR_MAGIC(ni);
+	kfree(ni);
+
+	/*
+	 * Decrease global node count
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ecm_db_node_count--;
+	DEBUG_ASSERT(ecm_db_node_count >= 0, "%px: node count wrap\n", ni);
+	spin_unlock_bh(&ecm_db_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_db_node_deref);
+
+/*
+ * ecm_db_node_is_mac_addr_equal()
+ *	Compares the node's mac address with the given mac address.
+ */
+bool ecm_db_node_is_mac_addr_equal(struct ecm_db_node_instance *ni, uint8_t *address)
+{
+	DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed", ni);
+
+	if (ecm_mac_addr_equal(ni->address, address)) {
+		return false;
+	}
+
+	return true;
+}
+EXPORT_SYMBOL(ecm_db_node_is_mac_addr_equal);
+
+/*
+ * ecm_db_node_find_and_ref()
+ *	Lookup and return a node reference if any
+ */
+struct ecm_db_node_instance *ecm_db_node_find_and_ref(uint8_t *address, struct ecm_db_iface_instance *ii)
+{
+	ecm_db_node_hash_t hash_index;
+	struct ecm_db_node_instance *ni;
+
+	DEBUG_TRACE("Lookup node with addr %pMi and iface %px\n", address, ii);
+
+	/*
+	 * Compute the hash chain index and prepare to walk the chain
+	 */
+	hash_index = ecm_db_node_generate_hash_index(address);
+
+	/*
+	 * Iterate the chain looking for a host with matching details
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ni = ecm_db_node_table[hash_index];
+	while (ni) {
+		if (memcmp(ni->address, address, ETH_ALEN)) {
+			ni = ni->hash_next;
+			continue;
+		}
+
+		if (ni->iface != ii) {
+			ni = ni->hash_next;
+			continue;
+		}
+
+		_ecm_db_node_ref(ni);
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_TRACE("node found %px\n", ni);
+		return ni;
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Node not found\n");
+	return NULL;
+}
+EXPORT_SYMBOL(ecm_db_node_find_and_ref);
+
+/*
+ * ecm_db_node_chain_get_and_ref_first()
+ *	Gets and refs the first node in the chain of that mac address.
+ */
+struct ecm_db_node_instance *ecm_db_node_chain_get_and_ref_first(uint8_t *address)
+{
+	ecm_db_node_hash_t hash_index;
+	struct ecm_db_node_instance *ni;
+
+	DEBUG_TRACE("Get the first node with addr %pMi in the chain\n", address);
+
+	/*
+	 * Compute the hash chain index.
+	 */
+	hash_index = ecm_db_node_generate_hash_index(address);
+
+	spin_lock_bh(&ecm_db_lock);
+	ni = ecm_db_node_table[hash_index];
+	if (ni) {
+		_ecm_db_node_ref(ni);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+
+	return ni;
+}
+EXPORT_SYMBOL(ecm_db_node_chain_get_and_ref_first);
+
+/*
+ * ecm_db_node_chain_get_and_ref_next()
+ *	Gets and refs the next node in the chain..
+ */
+struct ecm_db_node_instance *ecm_db_node_chain_get_and_ref_next(struct ecm_db_node_instance *ni)
+{
+	struct ecm_db_node_instance *nin;
+	DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed", ni);
+
+	spin_lock_bh(&ecm_db_lock);
+	nin = ni->hash_next;
+	if (nin) {
+		_ecm_db_node_ref(nin);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return nin;
+}
+EXPORT_SYMBOL(ecm_db_node_chain_get_and_ref_next);
+
+/*
+ * ecm_db_node_iface_get_and_ref()
+ */
+struct ecm_db_iface_instance *ecm_db_node_iface_get_and_ref(struct ecm_db_node_instance *ni)
+{
+	DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed\n", ni);
+
+	spin_lock_bh(&ecm_db_lock);
+	_ecm_db_iface_ref(ni->iface);
+	spin_unlock_bh(&ecm_db_lock);
+	return ni->iface;
+}
+EXPORT_SYMBOL(ecm_db_node_iface_get_and_ref);
+
+/*
+ * ecm_db_node_add()
+ *	Add a node instance into the database
+ */
+void ecm_db_node_add(struct ecm_db_node_instance *ni, struct ecm_db_iface_instance *ii, uint8_t *address,
+					ecm_db_node_final_callback_t final, void *arg)
+{
+#if (DEBUG_LEVEL >= 1)
+	int dir;
+#endif
+	ecm_db_node_hash_t hash_index;
+	struct ecm_db_listener_instance *li;
+
+	spin_lock_bh(&ecm_db_lock);
+	DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed\n", ni);
+	DEBUG_CHECK_MAGIC(ii, ECM_DB_IFACE_INSTANCE_MAGIC, "%px: magic failed\n", ii);
+	DEBUG_ASSERT(address, "%px: address null\n", ni);
+	DEBUG_ASSERT((ni->iface == NULL), "%px: iface not null\n", ni);
+	DEBUG_ASSERT(!(ni->flags & ECM_DB_NODE_FLAGS_INSERTED), "%px: inserted\n", ni);
+#ifdef ECM_DB_XREF_ENABLE
+#if (DEBUG_LEVEL >= 1)
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		DEBUG_ASSERT((ni->connections[dir] == NULL) && (ni->connections_count[dir] == 0), "%px: %s connections not null\n", ni, ecm_db_obj_dir_strings[dir]);
+	}
+#endif
+#endif
+	spin_unlock_bh(&ecm_db_lock);
+
+	memcpy(ni->address, address, ETH_ALEN);
+	ni->arg = arg;
+	ni->final = final;
+
+	/*
+	 * Compute hash chain for insertion
+	 */
+	hash_index = ecm_db_node_generate_hash_index(address);
+	ni->hash_index = hash_index;
+
+	/*
+	 * Node takes a ref to the iface
+	 */
+	ecm_db_iface_ref(ii);
+	ni->iface = ii;
+
+	/*
+	 * Add into the global list
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	ni->flags |= ECM_DB_NODE_FLAGS_INSERTED;
+	ni->prev = NULL;
+	ni->next = ecm_db_nodes;
+	if (ecm_db_nodes) {
+		ecm_db_nodes->prev = ni;
+	}
+	ecm_db_nodes = ni;
+
+	/*
+	 * Insert into the hash chain
+	 */
+	ni->hash_prev = NULL;
+	ni->hash_next = ecm_db_node_table[hash_index];
+	if (ecm_db_node_table[hash_index]) {
+		ecm_db_node_table[hash_index]->hash_prev = ni;
+	}
+	ecm_db_node_table[hash_index] = ni;
+	ecm_db_node_table_lengths[hash_index]++;
+	DEBUG_ASSERT(ecm_db_node_table_lengths[hash_index] > 0, "%px: invalid table len %d\n", ni, ecm_db_node_table_lengths[hash_index]);
+
+	/*
+	 * Set time of add
+	 */
+	ni->time_added = ecm_db_time;
+
+#ifdef ECM_DB_XREF_ENABLE
+	/*
+	 * Insert node into the iface nodes list
+	 */
+	ni->node_prev = NULL;
+	ni->node_next = ii->nodes;
+	if (ii->nodes) {
+		ii->nodes->node_prev = ni;
+	}
+	ii->nodes = ni;
+	ii->node_count++;
+#endif
+	spin_unlock_bh(&ecm_db_lock);
+
+	/*
+	 * Throw add event to the listeners
+	 */
+	DEBUG_TRACE("%px: Throw node added event\n", ni);
+	li = ecm_db_listeners_get_and_ref_first();
+	while (li) {
+		struct ecm_db_listener_instance *lin;
+		if (li->node_added) {
+			li->node_added(li->arg, ni);
+		}
+
+		/*
+		 * Get next listener
+		 */
+		lin = ecm_db_listener_get_and_ref_next(li);
+		ecm_db_listener_deref(li);
+		li = lin;
+	}
+}
+EXPORT_SYMBOL(ecm_db_node_add);
+
+/*
+ * ecm_db_node_state_get()
+ *	Prepare a node message
+ */
+int ecm_db_node_state_get(struct ecm_state_file_instance *sfi, struct ecm_db_node_instance *ni)
+{
+	int result;
+	char address[ECM_MAC_ADDR_STR_BUFF_SIZE];
+#ifdef ECM_DB_XREF_ENABLE
+	int dir;
+	int connections_count[ECM_DB_OBJ_DIR_MAX];
+#endif
+	uint32_t time_added;
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	uint64_t from_data_total;
+	uint64_t to_data_total;
+	uint64_t from_packet_total;
+	uint64_t to_packet_total;
+	uint64_t from_data_total_dropped;
+	uint64_t to_data_total_dropped;
+	uint64_t from_packet_total_dropped;
+	uint64_t to_packet_total_dropped;
+#endif
+
+	DEBUG_TRACE("Prep node msg for %px\n", ni);
+
+	/*
+	 * Create a small xml stats block for our managed node, like:
+	 * <node address="" hosts="" time_added="" from_data_total="" to_data_total="" />
+	 *
+	 * Extract information from the node for inclusion into the message
+	 */
+#ifdef ECM_DB_XREF_ENABLE
+	spin_lock_bh(&ecm_db_lock);
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		connections_count[dir] = ni->connections_count[dir];
+	}
+	spin_unlock_bh(&ecm_db_lock);
+#endif
+	time_added = ni->time_added;
+	snprintf(address, sizeof(address), "%pM", ni->address);
+
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	ecm_db_node_data_stats_get(ni, &from_data_total, &to_data_total,
+			&from_packet_total, &to_packet_total,
+			&from_data_total_dropped, &to_data_total_dropped,
+			&from_packet_total_dropped, &to_packet_total_dropped);
+
+#endif
+
+	if ((result = ecm_state_prefix_add(sfi, "node"))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "address", "%s", address))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "time_added", "%u", time_added))) {
+		return result;
+	}
+#ifdef ECM_DB_XREF_ENABLE
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		/*
+		 * ECM_DB_NODE_CONN_COUNT_STR_SIZE is the size of "FROM_NAT_connections_count"
+		 * string which can be the max length of these strings
+		 */
+		char name[ECM_DB_NODE_CONN_COUNT_STR_SIZE];
+		snprintf(name, ECM_DB_NODE_CONN_COUNT_STR_SIZE, "%s_connections_count", ecm_db_obj_dir_strings[dir]);
+		if ((result = ecm_state_write(sfi, name, "%d", connections_count[dir]))) {
+			return result;
+		}
+	}
+#endif
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	if ((result = ecm_db_adv_stats_state_write(sfi, from_data_total, to_data_total,
+			from_packet_total, to_packet_total, from_data_total_dropped,
+			to_data_total_dropped, from_packet_total_dropped,
+			to_packet_total_dropped))) {
+		return result;
+	}
+#endif
+	return ecm_state_prefix_remove(sfi);
+}
+EXPORT_SYMBOL(ecm_db_node_state_get);
+
+/*
+ * ecm_db_node_hash_table_lengths_get()
+ *	Return hash table length
+ */
+int ecm_db_node_hash_table_lengths_get(int index)
+{
+	int length;
+
+	DEBUG_ASSERT((index >= 0) && (index < ECM_DB_NODE_HASH_SLOTS), "Bad protocol: %d\n", index);
+	spin_lock_bh(&ecm_db_lock);
+	length = ecm_db_node_table_lengths[index];
+	spin_unlock_bh(&ecm_db_lock);
+	return length;
+}
+EXPORT_SYMBOL(ecm_db_node_hash_table_lengths_get);
+
+/*
+ * ecm_db_node_hash_index_get_next()
+ * Given a hash index, return the next one OR return -1 for no more hash indicies to return.
+ */
+int ecm_db_node_hash_index_get_next(int index)
+{
+	index++;
+	if (index >= ECM_DB_NODE_HASH_SLOTS) {
+		return -1;
+	}
+	return index;
+}
+EXPORT_SYMBOL(ecm_db_node_hash_index_get_next);
+
+/*
+ * ecm_db_node_hash_index_get_first()
+ * Return first hash index
+ */
+int ecm_db_node_hash_index_get_first(void)
+{
+	return 0;
+}
+EXPORT_SYMBOL(ecm_db_node_hash_index_get_first);
+
+/*
+ * ecm_db_node_get_connections_count()
+ *	Returns the connections count on the node in the given direction.
+ */
+int ecm_db_node_get_connections_count(struct ecm_db_node_instance *ni, ecm_db_obj_dir_t dir)
+{
+	DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed\n", ni);
+
+	return ni->connections_count[dir];
+}
+
+/*
+ * ecm_db_node_alloc()
+ *	Allocate a node instance
+ */
+struct ecm_db_node_instance *ecm_db_node_alloc(void)
+{
+	struct ecm_db_node_instance *ni;
+
+	ni = (struct ecm_db_node_instance *)kzalloc(sizeof(struct ecm_db_node_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!ni) {
+		DEBUG_WARN("Alloc failed\n");
+		return NULL;
+	}
+
+	ni->refs = 1;
+	DEBUG_SET_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC);
+
+	/*
+	 * Alloc operation must be atomic to ensure thread and module can be held
+	 */
+	spin_lock_bh(&ecm_db_lock);
+
+	/*
+	 * If the event processing thread is terminating then we cannot create new instances
+	 */
+	if (ecm_db_terminate_pending) {
+		spin_unlock_bh(&ecm_db_lock);
+		DEBUG_WARN("Thread terminating\n");
+		kfree(ni);
+		return NULL;
+	}
+
+	ecm_db_node_count++;
+	spin_unlock_bh(&ecm_db_lock);
+
+	DEBUG_TRACE("Node created %px\n", ni);
+	return ni;
+}
+EXPORT_SYMBOL(ecm_db_node_alloc);
+
+#ifdef ECM_DB_XREF_ENABLE
+/*
+ * ecm_db_node_connections_get_and_ref_first()
+ *	Obtain a ref to the first connection instance of node on this direction, if any
+ */
+static inline struct ecm_db_connection_instance *
+ecm_db_node_connections_get_and_ref_first(struct ecm_db_node_instance *node,
+					  ecm_db_obj_dir_t dir)
+{
+	struct ecm_db_connection_instance *ci;
+	DEBUG_CHECK_MAGIC(node, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed", node);
+	spin_lock_bh(&ecm_db_lock);
+	ci = node->connections[dir];
+	if (ci) {
+		_ecm_db_connection_ref(ci);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return ci;
+}
+
+/*
+ * ecm_db_node_connection_get_and_ref_next()
+ *	Return the next connection in the specified direction of given a connection
+ */
+static inline struct ecm_db_connection_instance *
+ecm_db_node_connection_get_and_ref_next(struct ecm_db_connection_instance *ci,
+					ecm_db_obj_dir_t dir)
+{
+	struct ecm_db_connection_instance *cin;
+	DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+	spin_lock_bh(&ecm_db_lock);
+	cin = ci->node_next[dir];
+	if (cin) {
+		_ecm_db_connection_ref(cin);
+	}
+	spin_unlock_bh(&ecm_db_lock);
+	return cin;
+}
+
+/*
+ * ecm_db_should_keep_connection()
+ *	check if any classifier believes this connection should
+ *	be kept
+ */
+static bool ecm_db_should_keep_connection(
+	struct ecm_db_connection_instance *ci, uint8_t *mac)
+{
+	bool should_keep_connection = false;
+	int assignment_count;
+	int aci_index;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+
+	assignment_count =
+		ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+		aci = assignments[aci_index];
+		if (aci->should_keep_connection &&
+			aci->should_keep_connection(aci, mac)) {
+			should_keep_connection = true;
+			break;
+		}
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	return should_keep_connection;
+}
+
+/*
+ * ecm_db_traverse_node_connection_list_and_defunct()
+ *	traverse a node in the specified direction and calls ecm_db_connection_make_defunct()
+ *	for each entry.  If ip_version is valid (non-zero), then defunct the
+ *	connections matching version.
+ */
+void ecm_db_traverse_node_connection_list_and_defunct(
+	struct ecm_db_node_instance *node, ecm_db_obj_dir_t dir, int ip_version)
+{
+	struct ecm_db_connection_instance *ci = NULL;
+
+	/*
+	 * Iterate all from connections
+	 */
+	ci = ecm_db_node_connections_get_and_ref_first(node, dir);
+	while (ci) {
+		struct ecm_db_connection_instance *cin;
+
+		if (!ecm_db_should_keep_connection(ci, node->address)) {
+			if (ip_version != ECM_DB_IP_VERSION_IGNORE && (ecm_db_connection_ip_version_get(ci) != ip_version)) {
+				DEBUG_TRACE("%px: keeping connection, ip_version mismatch %d\n", ci, ci->serial);
+				goto keep_node_conn;
+			}
+
+			DEBUG_TRACE("%px: defunct %d\n", ci, ci->serial);
+			ecm_db_connection_make_defunct(ci);
+		} else {
+			DEBUG_TRACE("%px: keeping connection %d\n", ci, ci->serial);
+		}
+keep_node_conn:
+		cin = ecm_db_node_connection_get_and_ref_next(ci, dir);
+		ecm_db_connection_deref(ci);
+		ci = cin;
+	}
+	DEBUG_INFO("%px: Defuncting from node connection list complete\n", node);
+}
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+
+/*
+ * ecm_db_node_ovs_connections_masked_defunct()
+ *	Destroy connections created on the node
+ */
+void ecm_db_node_ovs_connections_masked_defunct(int ip_ver, uint8_t *src_mac, bool src_mac_check, ip_addr_t src_addr_mask,
+							uint16_t src_port_mask, uint8_t *dest_mac, bool dest_mac_check,
+							ip_addr_t dest_addr_mask, uint16_t dest_port_mask,
+							int proto_mask, ecm_db_obj_dir_t dir, bool is_routed)
+{
+	struct ecm_db_node_instance *ni;
+	uint8_t smac[ETH_ALEN], dmac[ETH_ALEN];
+	uint8_t *mac;
+	ip_addr_t sip, dip;
+	uint16_t sport, dport;
+	int proto;
+	int cnt = 0;
+	char *direction = NULL;
+
+	mac = (dir == ECM_DB_OBJ_DIR_FROM) ? src_mac : dest_mac;
+
+	ni = ecm_db_node_chain_get_and_ref_first(mac);
+	if (!ni) {
+		DEBUG_WARN("Unable to find first instance node\n");
+		return;
+	}
+
+	/*
+	 * Iterate through all node instances
+	 */
+	while (ni) {
+		struct ecm_db_connection_instance *ci;
+		struct ecm_db_node_instance *nni;
+
+		DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed", ni);
+
+		if (!ecm_db_node_is_mac_addr_equal(ni, mac)) {
+			nni = ecm_db_node_chain_get_and_ref_next(ni);
+			ecm_db_node_deref(ni);
+			ni = nni;
+			continue;
+		}
+
+		ci = ecm_db_node_connections_get_and_ref_first(ni, dir);
+		while (ci) {
+			struct ecm_db_connection_instance *cin;
+
+			DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", ci);
+
+			/*
+			 * Skip routed CI for brided flows
+			 * Skip bridged CI for routed flows
+			 */
+			if (is_routed != ecm_db_connection_is_routed_get(ci)) {
+				goto next_ci;
+			}
+
+			/*
+			 * Check IP version
+			 */
+			if (ip_ver != ECM_DB_IP_VERSION_IGNORE && (ecm_db_connection_ip_version_get(ci) != ip_ver)) {
+				goto next_ci;
+			}
+
+			/*
+			 * Check protocol if specified
+			 */
+			proto = ecm_db_connection_protocol_get(ci);
+			if (!ECM_PROTO_MASK_MATCH(proto, proto_mask)) {
+				goto next_ci;
+			}
+
+			/*
+			 * A : PCI < ------- br-home ----------bridging----------------br-wan ---->PC2
+			 *
+			 * B : PCI < ------- br-home ----------Routing----------------br-wan ---->PC2
+			 *
+			 *							DNAT
+			 * C : PCI < ------- br-home ----------Routing----------------br-wan ----> PC2
+			 *							SNAT
+			 * D : PCI < ------- br-home ----------Routing----------------br-wan ----> PC2
+			 *
+			 */
+			ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, smac);
+			ecm_db_connection_node_address_get(ci,  ECM_DB_OBJ_DIR_TO, dmac);
+			ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, sip);
+			ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dip);
+			sport = ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM);
+			dport = ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO);
+
+			/*
+			 * 1. For topology A, B, C, D  if drop rule is added in br-home or br-wan
+			 * 2. For topoloy  A, B  if drop rule is added in br-wan
+			 * Match in flow direction
+			 */
+
+			if ((!src_mac_check || ECM_MAC_ADDR_MATCH(smac, src_mac)) &&
+			    (!dest_mac_check || ECM_MAC_ADDR_MATCH(dmac, dest_mac)) &&
+			    ECM_IP_ADDR_MASK_MATCH(sip, src_addr_mask) &&
+			    ECM_IP_ADDR_MASK_MATCH(dip, dest_addr_mask) &&
+			    ECM_PORT_MASK_MATCH(sport, src_port_mask) &&
+			    ECM_PORT_MASK_MATCH(dport, dest_port_mask)) {
+				direction = "flow";
+				goto defunct_conn;
+			}
+			/*
+			 * 1. For topology A, B, C, D  if drop rule is added in br-home or br-wan
+			 * 2. For topoloy  A, B  if drop rule is added in br-wan
+			 * Match in reverse direction
+			 */
+			if ((!src_mac_check || ECM_MAC_ADDR_MATCH(dmac, src_mac)) &&
+			    (!dest_mac_check || ECM_MAC_ADDR_MATCH(smac, dest_mac)) &&
+			    ECM_IP_ADDR_MASK_MATCH(dip, src_addr_mask) &&
+			    ECM_IP_ADDR_MASK_MATCH(sip, dest_addr_mask) &&
+			    ECM_PORT_MASK_MATCH(dport, src_port_mask) &&
+			    ECM_PORT_MASK_MATCH(sport, dest_port_mask)) {
+				direction = "reverse";
+				goto defunct_conn;
+			}
+
+			/*
+			 * There is no NATing in case of bridging
+			 */
+			if (!is_routed) {
+				goto next_ci;
+			}
+
+			ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM_NAT, smac);
+			ecm_db_connection_node_address_get(ci,  ECM_DB_OBJ_DIR_TO_NAT, dmac);
+			ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM_NAT, sip);
+			ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO_NAT, dip);
+			sport = ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM_NAT);
+			dport = ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO_NAT);
+
+			/*
+			 * 1. For topoloy  C, D  if drop rule is added in br-wan
+			 * Match in flow direction
+			 */
+			if ((!src_mac_check || ECM_MAC_ADDR_MATCH(smac, src_mac)) &&
+			    (!dest_mac_check || ECM_MAC_ADDR_MATCH(dmac, dest_mac)) &&
+			    ECM_IP_ADDR_MASK_MATCH(sip, src_addr_mask) &&
+			    ECM_IP_ADDR_MASK_MATCH(dip, dest_addr_mask) &&
+			    ECM_PORT_MASK_MATCH(sport, src_port_mask) &&
+			    ECM_PORT_MASK_MATCH(dport, dest_port_mask)) {
+				direction = "flow (nat)";
+				goto defunct_conn;
+			}
+
+			/*
+			 * 1. For topoloy  C, D  if drop rule is added in br-wan
+			 * Match in reverse direction
+			 */
+			if ((!src_mac_check || ECM_MAC_ADDR_MATCH(dmac, src_mac)) &&
+			    (!dest_mac_check || ECM_MAC_ADDR_MATCH(smac, dest_mac)) &&
+			    ECM_IP_ADDR_MASK_MATCH(dip, src_addr_mask) &&
+			    ECM_IP_ADDR_MASK_MATCH(sip, dest_addr_mask) &&
+			    ECM_PORT_MASK_MATCH(dport, src_port_mask) &&
+			    ECM_PORT_MASK_MATCH(sport, dest_port_mask)) {
+				direction = "reverse (nat)";
+				goto defunct_conn;
+			}
+
+			goto next_ci;
+
+defunct_conn:
+			cnt++;
+
+			DEBUG_TRACE("%px: Defuncting 7 tuple %s connection\n", ci, is_routed ? "routed" : "bridged");
+			if (ECM_IP_ADDR_IS_V4(src_addr_mask)) {
+				DEBUG_TRACE("%px: Defunct CI masked 7 tuple match(%s) smac=%pM(%d) src=" ECM_IP_ADDR_DOT_FMT " sport=%d "
+					    "dmac=%pM(%d) dest=" ECM_IP_ADDR_DOT_FMT ", dport=%d, proto=%d cnt=%d\n", ci, direction, smac,
+					    src_mac_check, ECM_IP_ADDR_TO_DOT(sip), sport, dmac, dest_mac_check,
+					    ECM_IP_ADDR_TO_DOT(dip), dport, proto, cnt);
+			} else {
+				DEBUG_TRACE("%px: Defunct CI masked 7 tuple match(%s) src=%pM(%d)" ECM_IP_ADDR_OCTAL_FMT " sport=%d "
+					    "dmac=%pM(%d) dest=" ECM_IP_ADDR_OCTAL_FMT ", dport=%d, proto=%d, cnt=%d\n", ci, direction,
+					    smac, src_mac_check, ECM_IP_ADDR_TO_OCTAL(sip), sport, dmac, dest_mac_check,
+					    ECM_IP_ADDR_TO_OCTAL(dip), dport, proto, cnt);
+			}
+
+			ecm_db_connection_make_defunct(ci);
+next_ci:
+			cin = ecm_db_node_connection_get_and_ref_next(ci, dir);
+
+			ecm_db_connection_deref(ci);
+			ci = cin;
+		}
+
+		ecm_db_node_deref(ni);
+		break;
+	}
+
+	DEBUG_TRACE("Completed OVS 7 tuple %s connections (cnt=%d) masked defunct\n",  is_routed ? "routed" : "bridged", cnt);
+
+	if (ECM_IP_ADDR_IS_V4(src_addr_mask)) {
+		DEBUG_TRACE("Defunct request by masked 7 tuple smac_mask=%pM(%d) src_mask=" ECM_IP_ADDR_DOT_FMT " sport_mask=%d, "
+			    "dmac_mask=%pM(%d) dest_mask=" ECM_IP_ADDR_DOT_FMT " dport_mask=%d, proto_mask=%d\n",  src_mac,
+			    src_mac_check, ECM_IP_ADDR_TO_DOT(src_addr_mask), src_port_mask, dest_mac, dest_mac_check,
+			    ECM_IP_ADDR_TO_DOT(dest_addr_mask), dest_port_mask, proto_mask);
+	} else {
+		DEBUG_TRACE("Defunct request by masked 7 tuple smac_mask=%pM(%d) src_mask=" ECM_IP_ADDR_OCTAL_FMT " sport_mask=%d "
+			    "dmac_mask=%pM(%d) dest_mask=" ECM_IP_ADDR_OCTAL_FMT " dport_mask=%d, proto_mask=%d cnt=%d\n",
+			    src_mac, src_mac_check, ECM_IP_ADDR_TO_OCTAL(src_addr_mask), src_port_mask, dest_mac, dest_mac_check,
+			    ECM_IP_ADDR_TO_OCTAL(dest_addr_mask), dest_port_mask, proto_mask, cnt);
+	}
+
+}
+
+/*
+ * ecm_db_node_ovs_routed_connections_defunct()
+ *	Destroy the routed connections created on the node in the given
+ *	direction which is related to the ovs_br interface.
+ */
+void ecm_db_node_ovs_routed_connections_defunct(uint8_t *node_mac, struct net_device *ovs_br, int ip_version, ecm_db_obj_dir_t dir)
+{
+	struct ecm_db_iface_instance *ii;
+	struct ecm_db_node_instance *ni;
+	struct ecm_db_connection_instance *ci;
+
+	ii =  ecm_db_iface_find_and_ref_by_interface_identifier(ovs_br->ifindex);
+	if (!ii) {
+		DEBUG_WARN("%px: Unable to find OVS bridge iface instance\n", ovs_br);
+		return;
+	}
+
+	/*
+	 * Find the node instance which has the node_mac and related to the ovs_br.
+	 * Nodes are stored in the database with their related interface instances.
+	 */
+	ni = ecm_db_node_find_and_ref(node_mac, ii);
+	if(!ni) {
+		DEBUG_WARN("%px: Unable to find node instance related to %pM and %s\n", ovs_br, node_mac, ovs_br->name);
+		ecm_db_iface_deref(ii);
+		return;
+	}
+
+	/*
+	 * Iterate all routed connections on this node in the dir direction.
+	 */
+	ci = ecm_db_node_connections_get_and_ref_first(ni, dir);
+	while (ci) {
+		struct ecm_db_connection_instance *cin;
+
+		if (ecm_db_connection_is_routed_get(ci) && (ecm_db_connection_ip_version_get(ci) == ip_version)) {
+			DEBUG_TRACE("%px: Defuncting connection %p\n", ovs_br, ci);
+			ecm_db_connection_make_defunct(ci);
+		}
+
+		cin = ecm_db_node_connection_get_and_ref_next(ci, dir);
+		ecm_db_connection_deref(ci);
+		ci = cin;
+	}
+
+	ecm_db_node_deref(ni);
+	ecm_db_iface_deref(ii);
+
+	DEBUG_TRACE("%px: Completed OVS routed connection defunct\n", ovs_br);
+}
+
+/*
+ * ecm_db_traverse_snode_dnode_connection_list_and_defunct()
+ *	Defunct connections between node1 (sni) and node2 (which has dmac address)
+ */
+void ecm_db_traverse_snode_dnode_connection_list_and_defunct(
+	struct ecm_db_node_instance *sni, uint8_t *dmac, int ip_version, ecm_db_obj_dir_t dir)
+{
+	struct ecm_db_connection_instance *ci = NULL;
+
+	if (dir != ECM_DB_OBJ_DIR_FROM && dir != ECM_DB_OBJ_DIR_TO) {
+		DEBUG_WARN("Direction is incorrect: %d\n", dir);
+		return;
+	}
+
+	/*
+	 * Iterate all connection instances which are sent or received from
+	 * given node instannce (sni).
+	 */
+	ci = ecm_db_node_connections_get_and_ref_first(sni, dir);
+	while (ci) {
+		struct ecm_db_connection_instance *cin;
+		struct ecm_db_node_instance *dni;
+
+		/*
+		 * Find the connection instance which match given MAC address (dmac)
+		 */
+		if (dir == ECM_DB_OBJ_DIR_FROM) {
+			/*
+			 * Direction is FROM, then sni is source node.
+			 * find the node in TO direction.
+			 */
+			dni = ci->node[ECM_DB_OBJ_DIR_TO];
+		} else {
+			/*
+			 * Direction is TO, then sni is destination node.
+			 * find the node in FROM direction.
+			 */
+			dni = ci->node[ECM_DB_OBJ_DIR_FROM];
+		}
+
+		/*
+		 * if the MAC address of node (dni) match MAC address (dmac)
+		 * then delete the connection instance.
+		 */
+		if (ecm_db_node_is_mac_addr_equal(dni, dmac)) {
+			if (ip_version != ECM_DB_IP_VERSION_IGNORE && (ecm_db_connection_ip_version_get(ci) != ip_version)) {
+				DEBUG_TRACE("%px: keeping connection, ip_version mismatch %d\n", ci, ci->serial);
+				goto keep_sni_conn;
+			}
+
+			DEBUG_TRACE("%px: defunct %d\n", ci, ci->serial);
+			ecm_db_connection_make_defunct(ci);
+		}
+keep_sni_conn:
+		cin = ecm_db_node_connection_get_and_ref_next(ci, dir);
+		ecm_db_connection_deref(ci);
+		ci = cin;
+	}
+	DEBUG_INFO("%px: Defuncting from node connection list complete\n", sni);
+}
+#endif
+#endif
+
+/*
+ * ecm_db_node_init()
+ */
+bool ecm_db_node_init(struct dentry *dentry)
+{
+	if (!debugfs_create_u32("node_count", S_IRUGO, dentry,
+					(u32 *)&ecm_db_node_count)) {
+		DEBUG_ERROR("Failed to create ecm db node count file in debugfs\n");
+		return false;
+	}
+
+	ecm_db_node_table = vzalloc(sizeof(struct ecm_db_node_instance *) * ECM_DB_NODE_HASH_SLOTS);
+	if (!ecm_db_node_table) {
+		DEBUG_ERROR("Failed to allocate virtual memory for ecm_db_node_table\n");
+		return false;
+	}
+
+	ecm_db_node_table_lengths = vzalloc(sizeof(int) * ECM_DB_NODE_HASH_SLOTS);
+	if (!ecm_db_node_table_lengths) {
+		DEBUG_ERROR("Failed to allocate virtual memory for ecm_db_node_table_lengths\n");
+		vfree(ecm_db_node_table);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * ecm_db_node_exit()
+ */
+void ecm_db_node_exit(void)
+{
+	vfree(ecm_db_node_table_lengths);
+	vfree(ecm_db_node_table);
+}
diff --git a/qca-nss-ecm/ecm_db/ecm_db_node.h b/qca-nss-ecm/ecm_db/ecm_db_node.h
new file mode 100644
index 0000000..1661ccd
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_node.h
@@ -0,0 +1,139 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * Magic number
+ */
+#define ECM_DB_NODE_INSTANCE_MAGIC 0x3312
+
+/*
+ * Max size of directional connection count string printed
+ * on the dump output.
+ */
+#define ECM_DB_NODE_CONN_COUNT_STR_SIZE 27
+
+typedef uint32_t ecm_db_node_hash_t;
+
+/*
+ * struct ecm_db_node_instance
+ */
+struct ecm_db_node_instance {
+	struct ecm_db_node_instance *next;		/* Next instance in global list */
+	struct ecm_db_node_instance *prev;		/* Previous instance in global list */
+	struct ecm_db_node_instance *hash_next;		/* Next node in the chain of nodes */
+	struct ecm_db_node_instance *hash_prev;		/* previous node in the chain of nodes */
+	uint8_t address[ETH_ALEN];			/* RO: MAC Address of this node */
+
+#ifdef ECM_DB_XREF_ENABLE
+	/*
+	 * For convenience nodes keep lists of connections that have been established from them and to them.
+	 * In fact the same connection could be listed as from & to on the same interface (think: WLAN<>WLAN AP function)
+	 * Nodes keep this information for rapid iteration of connections e.g. when a node 'goes down' we
+	 * can defunct all associated connections or destroy any accel engine rules.
+	 */
+	struct ecm_db_connection_instance *connections[ECM_DB_OBJ_DIR_MAX];
+								/* list of connections made on this node */
+	int connections_count[ECM_DB_OBJ_DIR_MAX];		/* Number of connections on this node with the direction specified in the index*/
+
+	/*
+	 * Nodes reachable from an interface are stored in a linked list maintained by that interface.
+	 * This is so, given an interface, you can examine all nodes reachable from it.
+	 */
+	struct ecm_db_node_instance *node_next;				/* The next node within the same iface nodes list */
+	struct ecm_db_node_instance *node_prev;				/* The previous node within the same iface nodes list */
+#endif
+
+	uint32_t time_added;				/* RO: DB time stamp when the node was added into the database */
+
+#ifdef ECM_DB_ADVANCED_STATS_ENABLE
+	uint64_t from_data_total;			/* Total of data sent by this node */
+	uint64_t to_data_total;				/* Total of data sent to this node */
+	uint64_t from_packet_total;			/* Total of packets sent by this node */
+	uint64_t to_packet_total;			/* Total of packets sent to this node */
+	uint64_t from_data_total_dropped;
+	uint64_t to_data_total_dropped;
+	uint64_t from_packet_total_dropped;
+	uint64_t to_packet_total_dropped;
+#endif
+	struct ecm_db_iface_instance *iface;		/* The interface to which this node relates */
+
+	ecm_db_node_final_callback_t final;		/* Callback to owner when object is destroyed */
+	void *arg;					/* Argument returned to owner in callbacks */
+	uint8_t flags;
+	int refs;					/* Integer to trap we never go negative */
+	ecm_db_node_hash_t hash_index;
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+int _ecm_db_node_count_get(void);
+
+void _ecm_db_node_ref(struct ecm_db_node_instance *ni);
+void ecm_db_node_ref(struct ecm_db_node_instance *ni);
+int ecm_db_node_deref(struct ecm_db_node_instance *ni);
+
+#ifdef ECM_DB_XREF_ENABLE
+void ecm_db_traverse_node_connection_list_and_defunct(struct ecm_db_node_instance *node, ecm_db_obj_dir_t dir, int ip_version);
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+void ecm_db_node_ovs_routed_connections_defunct(uint8_t *node_mac,
+						struct net_device *ovs_br,
+						int ip_version,
+						ecm_db_obj_dir_t dir);
+void ecm_db_traverse_snode_dnode_connection_list_and_defunct(
+	struct ecm_db_node_instance *sni, uint8_t *dmac, int ip_version, ecm_db_obj_dir_t dir);
+#endif
+#endif
+
+void ecm_db_node_adress_get(struct ecm_db_node_instance *ni, uint8_t *address_buffer);
+
+struct ecm_db_iface_instance *ecm_db_node_iface_get_and_ref(struct ecm_db_node_instance *ni);
+struct ecm_db_node_instance *ecm_db_node_find_and_ref(uint8_t *address, struct ecm_db_iface_instance *ii);
+
+bool ecm_db_node_is_mac_addr_equal(struct ecm_db_node_instance *ni, uint8_t *address);
+
+struct ecm_db_node_instance *ecm_db_nodes_get_and_ref_first(void);
+struct ecm_db_node_instance *ecm_db_node_get_and_ref_next(struct ecm_db_node_instance *ni);
+
+struct ecm_db_node_instance *ecm_db_node_chain_get_and_ref_first(uint8_t *address);
+struct ecm_db_node_instance *ecm_db_node_chain_get_and_ref_next(struct ecm_db_node_instance *ni);
+
+struct ecm_db_node_instance *ecm_db_node_alloc(void);
+void ecm_db_node_add(struct ecm_db_node_instance *ni,
+		     struct ecm_db_iface_instance *ii,
+		     uint8_t *address,
+		     ecm_db_node_final_callback_t final, void *arg);
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+int ecm_db_node_state_get(struct ecm_state_file_instance *sfi, struct ecm_db_node_instance *ni);
+int ecm_db_node_hash_table_lengths_get(int index);
+int ecm_db_node_hash_index_get_next(int index);
+int ecm_db_node_hash_index_get_first(void);
+#endif
+
+int ecm_db_node_get_connections_count(struct ecm_db_node_instance *ni, ecm_db_obj_dir_t dir);
+
+void ecm_db_node_ovs_connections_masked_defunct(int ip_ver, uint8_t *src_mac, bool src_mac_check, ip_addr_t src_addr_mask,
+							uint16_t src_port_mask, uint8_t *dest_mac, bool dest_mac_check,
+							ip_addr_t dest_addr_mask, uint16_t dest_port_mask,
+							int proto_mask, ecm_db_obj_dir_t dir, bool is_routed);
+
+bool ecm_db_node_init(struct dentry *dentry);
+void ecm_db_node_exit(void);
diff --git a/qca-nss-ecm/ecm_db/ecm_db_timer.c b/qca-nss-ecm/ecm_db/ecm_db_timer.c
new file mode 100644
index 0000000..c3c8e39
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_timer.c
@@ -0,0 +1,525 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <linux/random.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <net/ip6_route.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_DB_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_classifier_default.h"
+#include "ecm_db.h"
+
+/*
+ * Check the configured HZ value.
+ */
+#if HZ > 100000
+#error "Bad HZ value"
+#endif
+
+/*
+ * Timers and cleanup
+ */
+uint32_t ecm_db_time = 0;					/* Time in seconds since start */
+								/* Timer groups */
+static struct timer_list ecm_db_timer;				/* Timer to drive timer groups */
+
+struct ecm_db_timer_group ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_MAX];
+
+/*
+ * _ecm_db_timer_group_entry_remove()
+ *	Remove the entry from its timer group, returns false if the entry has already expired.
+ */
+bool _ecm_db_timer_group_entry_remove(struct ecm_db_timer_group_entry *tge)
+{
+	struct ecm_db_timer_group *timer_group;
+
+	/*
+	 * If not in a timer group then it is already removed
+	 */
+	if (tge->group == ECM_DB_TIMER_GROUPS_MAX) {
+		return false;
+	}
+
+	/*
+	 * Remove the connection from its current group
+	 */
+	timer_group = &ecm_db_timer_groups[tge->group];
+
+	/*
+	 * Somewhere in the list?
+	 */
+	if (tge->prev) {
+		tge->prev->next = tge->next;
+	} else {
+		/*
+		 * First in the group
+		 */
+		DEBUG_ASSERT(timer_group->head == tge, "%px: bad head, expecting %px, got %px\n", timer_group, tge, timer_group->head);
+		timer_group->head = tge->next;
+	}
+
+	if (tge->next) {
+		tge->next->prev = tge->prev;
+	} else {
+		/*
+		 * No next so this must be the last item - we need to adjust the tail pointer
+		 */
+		DEBUG_ASSERT(timer_group->tail == tge, "%px: bad tail, expecting %px got %px\n", timer_group, tge, timer_group->tail);
+		timer_group->tail = tge->prev;
+	}
+
+	/*
+	 * No longer a part of a timer group
+	 */
+	tge->group = ECM_DB_TIMER_GROUPS_MAX;
+	return true;
+}
+
+/*
+ * ecm_db_timer_group_entry_remove()
+ *	Remove the connection from its timer group, returns false if the entry has already expired.
+ */
+bool ecm_db_timer_group_entry_remove(struct ecm_db_timer_group_entry *tge)
+{
+	bool res;
+	spin_lock_bh(&ecm_db_lock);
+	res = _ecm_db_timer_group_entry_remove(tge);
+	spin_unlock_bh(&ecm_db_lock);
+	return res;
+}
+EXPORT_SYMBOL(ecm_db_timer_group_entry_remove);
+
+/*
+ * _ecm_db_timer_group_entry_set()
+ *	Set the timer group to which this entry will be a member
+ */
+void _ecm_db_timer_group_entry_set(struct ecm_db_timer_group_entry *tge, ecm_db_timer_group_t tg)
+{
+	struct ecm_db_timer_group *timer_group;
+
+	DEBUG_ASSERT(tge->group == ECM_DB_TIMER_GROUPS_MAX, "%px: already set\n", tge);
+
+	/*
+	 * Set group
+	 */
+	tge->group = tg;
+	timer_group = &ecm_db_timer_groups[tge->group];
+	tge->timeout = timer_group->time + ecm_db_time;
+
+	/*
+	 * Insert into a timer group at the head (as this is now touched)
+	 */
+	tge->prev = NULL;
+	tge->next = timer_group->head;
+	if (!timer_group->head) {
+		/*
+		 * As there is no head there is also no tail so we need to set that
+		 */
+		timer_group->tail = tge;
+	} else {
+		/*
+		 * As there is a head already there must be a tail.  Since we insert before
+		 * the current head we don't adjust the tail.
+		 */
+		timer_group->head->prev = tge;
+	}
+	timer_group->head = tge;
+}
+
+/*
+ * ecm_db_timer_group_entry_reset()
+ *	Re-set the timer group to which this entry will be a member.
+ *
+ * Returns false if the timer cannot be reset because it has expired
+ */
+bool ecm_db_timer_group_entry_reset(struct ecm_db_timer_group_entry *tge, ecm_db_timer_group_t tg)
+{
+	spin_lock_bh(&ecm_db_lock);
+
+	/*
+	 * Remove it from its current group, if any
+	 */
+	if (!_ecm_db_timer_group_entry_remove(tge)) {
+		spin_unlock_bh(&ecm_db_lock);
+		return false;
+	}
+
+	/*
+	 * Set new group
+	 */
+	_ecm_db_timer_group_entry_set(tge, tg);
+	spin_unlock_bh(&ecm_db_lock);
+	return true;
+}
+EXPORT_SYMBOL(ecm_db_timer_group_entry_reset);
+
+/*
+ * ecm_db_timer_group_entry_set()
+ *	Set the timer group to which this entry will be a member
+ */
+void ecm_db_timer_group_entry_set(struct ecm_db_timer_group_entry *tge, ecm_db_timer_group_t tg)
+{
+	spin_lock_bh(&ecm_db_lock);
+	_ecm_db_timer_group_entry_set(tge, tg);
+	spin_unlock_bh(&ecm_db_lock);
+}
+EXPORT_SYMBOL(ecm_db_timer_group_entry_set);
+
+/*
+ * ecm_db_timer_group_entry_init()
+ *	Initialise a timer entry ready for setting
+ */
+void ecm_db_timer_group_entry_init(struct ecm_db_timer_group_entry *tge, ecm_db_timer_group_entry_callback_t fn, void *arg)
+{
+	memset(tge, 0, sizeof(struct ecm_db_timer_group_entry));
+	tge->group = ECM_DB_TIMER_GROUPS_MAX;
+	tge->arg = arg;
+	tge->fn = fn;
+}
+EXPORT_SYMBOL(ecm_db_timer_group_entry_init);
+
+/*
+ * ecm_db_timer_group_entry_touch()
+ *	Update the timeout, if the timer is not running this has no effect.
+ * It returns false if the timer is not running.
+ */
+bool ecm_db_timer_group_entry_touch(struct ecm_db_timer_group_entry *tge)
+{
+	struct ecm_db_timer_group *timer_group;
+
+	spin_lock_bh(&ecm_db_lock);
+
+	/*
+	 * If not in a timer group then do nothing
+	 */
+	if (tge->group == ECM_DB_TIMER_GROUPS_MAX) {
+		spin_unlock_bh(&ecm_db_lock);
+		return false;
+	}
+
+	/*
+	 * Update time to live
+	 */
+	timer_group = &ecm_db_timer_groups[tge->group];
+
+	/*
+	 * Link out of its current position.
+	 */
+	if (!tge->prev) {
+		/*
+		 * Already at the head, just update the time
+		 */
+		tge->timeout = timer_group->time + ecm_db_time;
+		spin_unlock_bh(&ecm_db_lock);
+		return true;
+	}
+
+	/*
+	 * tge->prev is not null, so:
+	 * 1) it is in a timer list
+	 * 2) is not at the head of the list
+	 * 3) there is a head already (so more than one item on the list)
+	 * 4) there is a prev pointer.
+	 * Somewhere in the group list - unlink it.
+	 */
+	tge->prev->next = tge->next;
+
+	if (tge->next) {
+		tge->next->prev = tge->prev;
+	} else {
+		/*
+		 * Since there is no next this must be the tail
+		 */
+		DEBUG_ASSERT(timer_group->tail == tge, "%px: bad tail, expecting %px got %px\n", timer_group, tge, timer_group->tail);
+		timer_group->tail = tge->prev;
+	}
+
+	/*
+	 * Link in to head.
+	 */
+	tge->timeout = timer_group->time + ecm_db_time;
+	tge->prev = NULL;
+	tge->next = timer_group->head;
+	timer_group->head->prev = tge;
+	timer_group->head = tge;
+	spin_unlock_bh(&ecm_db_lock);
+	return true;
+}
+EXPORT_SYMBOL(ecm_db_timer_group_entry_touch);
+
+/*
+ * ecm_db_timer_groups_check()
+ *	Check for expired group entries, returns the number that have expired
+ */
+static uint32_t ecm_db_timer_groups_check(uint32_t time_now)
+{
+	ecm_db_timer_group_t i;
+	uint32_t expired = 0;
+
+	DEBUG_TRACE("Timer groups check start %u\n", time_now);
+
+	/*
+	 * Examine all timer groups for expired entries.
+	 */
+	for (i = 0; i < ECM_DB_TIMER_GROUPS_MAX; ++i) {
+		struct ecm_db_timer_group *timer_group;
+
+		/*
+		 * The group tail tracks the oldest entry so that is what we examine.
+		 */
+		timer_group = &ecm_db_timer_groups[i];
+		spin_lock_bh(&ecm_db_lock);
+		while (timer_group->tail) {
+			struct ecm_db_timer_group_entry *tge;
+
+			tge = timer_group->tail;
+			if (tge->timeout > time_now) {
+				/*
+				 * Not expired - and no further will be as they are in order
+				 */
+				break;
+			}
+
+			/*
+			 * Has expired - remove the entry from the list and invoke the callback
+			 * NOTE: We know the entry is at the tail of the group
+			 */
+			if (tge->prev) {
+				tge->prev->next = NULL;
+			} else {
+				/*
+				 * First in the group
+				 */
+				DEBUG_ASSERT(timer_group->head == tge, "%px: bad head, expecting %px got %px\n", timer_group, tge, timer_group->head);
+				timer_group->head = NULL;
+			}
+			timer_group->tail = tge->prev;
+			tge->group = ECM_DB_TIMER_GROUPS_MAX;
+			spin_unlock_bh(&ecm_db_lock);
+			expired++;
+			DEBUG_TRACE("%px: Expired\n", tge);
+			tge->fn(tge->arg);
+			spin_lock_bh(&ecm_db_lock);
+		}
+		spin_unlock_bh(&ecm_db_lock);
+	}
+
+	spin_lock_bh(&ecm_db_lock);
+	time_now = ecm_db_time;
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Timer groups check end %u, expired count %u\n", time_now, expired);
+	return expired;
+}
+
+/*
+ * ecm_db_time_get()
+ *	Return database time, in seconds since the database started.
+ */
+uint32_t ecm_db_time_get(void)
+{
+	uint32_t time_now;
+	spin_lock_bh(&ecm_db_lock);
+	time_now = ecm_db_time;
+	spin_unlock_bh(&ecm_db_lock);
+	return time_now;
+}
+EXPORT_SYMBOL(ecm_db_time_get);
+
+/*
+ * ecm_db_timer_callback()
+ *	Manage expiration of connections
+ * NOTE: This is softirq context
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0))
+static void ecm_db_timer_callback(unsigned long data)
+#else
+static void ecm_db_timer_callback(struct timer_list *tm)
+#endif
+{
+	uint32_t timer;
+
+	/*
+	 * Increment timer.
+	 */
+	spin_lock_bh(&ecm_db_lock);
+	timer = ++ecm_db_time;
+	spin_unlock_bh(&ecm_db_lock);
+	DEBUG_TRACE("Garbage timer tick %d\n", timer);
+
+	/*
+	 * Check timer groups
+	 */
+	ecm_db_timer_groups_check(timer);
+
+	/*
+	 * Set the timer for the next second
+	 */
+	ecm_db_timer.expires += HZ;
+	if (ecm_db_timer.expires <= jiffies) {
+		DEBUG_WARN("losing time %lu, jiffies = %lu\n", ecm_db_timer.expires, jiffies);
+		ecm_db_timer.expires = jiffies + HZ;
+	}
+	add_timer(&ecm_db_timer);
+}
+
+/*
+ * ecm_db_timer_init()
+ */
+void ecm_db_timer_init(void)
+{
+	DEBUG_INFO("ECM database timer init\n");
+
+	/*
+	 * Set a timer to manage cleanup of expired connections
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0))
+	init_timer(&ecm_db_timer);
+	ecm_db_timer.function = ecm_db_timer_callback;
+	ecm_db_timer.data = 0;
+#else
+	timer_setup(&ecm_db_timer, ecm_db_timer_callback, 0);
+#endif
+	ecm_db_timer.expires = jiffies + HZ;
+	add_timer(&ecm_db_timer);
+
+	/*
+	 * Initialise timer groups with time values
+	 */
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CLASSIFIER_DETERMINE_GENERIC_TIMEOUT].time = ECM_DB_CLASSIFIER_DETERMINE_GENERIC_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CLASSIFIER_DETERMINE_GENERIC_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CLASSIFIER_DETERMINE_GENERIC_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_GENERIC_TIMEOUT].time = ECM_DB_CONNECTION_GENERIC_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_GENERIC_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_GENERIC_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_IGMP_TIMEOUT].time = ECM_DB_CONNECTION_IGMP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_IGMP_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_IGMP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_UDP_GENERIC_TIMEOUT].time = ECM_DB_CONNECTION_UDP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_UDP_GENERIC_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_UDP_GENERIC_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_UDP_WKP_TIMEOUT].time = ECM_DB_CONNECTION_UDP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_UDP_WKP_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_UDP_WKP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_ICMP_TIMEOUT].time = ECM_DB_CONNECTION_ICMP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_ICMP_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_ICMP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_TCP_SHORT_TIMEOUT].time = ECM_DB_CONNECTION_TCP_SHORT_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_TCP_SHORT_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_TCP_SHORT_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_TCP_RESET_TIMEOUT].time = ECM_DB_CONNECTION_TCP_RST_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_TCP_RESET_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_TCP_RESET_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_TCP_CLOSED_TIMEOUT].time = ECM_DB_CONNECTION_TCP_CLOSED_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_TCP_CLOSED_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_TCP_CLOSED_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_TCP_LONG_TIMEOUT].time = ECM_DB_CONNECTION_TCP_LONG_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_TCP_LONG_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_TCP_LONG_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_PPTP_DATA_TIMEOUT].time = ECM_DB_CONNECTION_PPTP_DATA_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_PPTP_DATA_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_PPTP_DATA_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_RTCP_TIMEOUT].time = ECM_DB_CONNECTION_RTCP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_RTCP_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_RTCP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_RTSP_TIMEOUT].time = ECM_DB_CONNECTION_TCP_LONG_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_RTSP_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_RTSP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_RTSP_FAST_TIMEOUT].time = ECM_DB_CONNECTION_RTSP_FAST_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_RTSP_FAST_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_RTSP_FAST_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_RTSP_SLOW_TIMEOUT].time = ECM_DB_CONNECTION_RTSP_SLOW_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_RTSP_SLOW_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_RTSP_SLOW_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_DNS_TIMEOUT].time = ECM_DB_CONNECTION_DNS_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_DNS_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_DNS_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_FTP_TIMEOUT].time = ECM_DB_CONNECTION_FTP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_FTP_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_FTP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_BITTORRENT_TIMEOUT].time = ECM_DB_CONNECTION_BITTORRENT_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_BITTORRENT_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_BITTORRENT_TIMEOUT;
+
+	/*
+	 * H323 timeout value is 8 hours (8h * 60m * 60s == 28800 seconds).
+	 */
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_H323_TIMEOUT].time = ECM_DB_CONNECTION_H323_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_H323_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_H323_TIMEOUT;
+
+	/*
+	 * IKE Timeout (seconds) = 15 hours
+	 */
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_IKE_TIMEOUT].time = ECM_DB_CONNECTION_IKE_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_IKE_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_IKE_TIMEOUT;
+
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_ESP_TIMEOUT].time = ECM_DB_CONNECTION_ESP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_ESP_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_ESP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_ESP_PENDING_TIMEOUT].time = ECM_DB_CONNECTION_ESP_PENDING_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_ESP_PENDING_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_ESP_PENDING_TIMEOUT;
+
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_SDP_TIMEOUT].time = ECM_DB_CONNECTION_SDP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_SDP_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_SDP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_SIP_TIMEOUT].time = ECM_DB_CONNECTION_SIP_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_SIP_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_SIP_TIMEOUT;
+
+	/*
+	 * Defunct re-try timeout (5 seconds)
+	 */
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_DEFUNCT_RETRY_TIMEOUT].time = ECM_DB_CONNECTION_DEFUNCT_RETRY_TIMEOUT;
+	ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_CONNECTION_DEFUNCT_RETRY_TIMEOUT].tg = ECM_DB_TIMER_GROUPS_CONNECTION_DEFUNCT_RETRY_TIMEOUT;
+}
+
+/*
+ * ecm_db_timer_exit()
+ */
+void ecm_db_timer_exit(void)
+{
+	DEBUG_INFO("ECM database timer exit\n");
+
+	/*
+	 * Destroy garbage timer
+	 * Timer must be cancelled outside of holding db lock - if the
+	 * timer callback runs on another CPU we would deadlock
+	 * as we would wait for the callback to finish and it would wait
+	 * indefinately for the lock to be released!
+	 */
+	del_timer_sync(&ecm_db_timer);
+}
diff --git a/qca-nss-ecm/ecm_db/ecm_db_timer.h b/qca-nss-ecm/ecm_db/ecm_db_timer.h
new file mode 100644
index 0000000..cde056a
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_timer.h
@@ -0,0 +1,54 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * Timers and cleanup
+ */
+extern uint32_t ecm_db_time;	/* Time in seconds since start */
+
+/*
+ * struct ecm_db_timer_group
+ *	A timer group - all group members within the same group have the same TTL reset value.
+ *
+ * Expiry of entries occurs from tail to head.
+ */
+struct ecm_db_timer_group {
+	struct ecm_db_timer_group_entry *head;		/* Most recently used entry in this timer group */
+	struct ecm_db_timer_group_entry *tail;		/* Least recently used entry in this timer group. */
+	uint32_t time;					/* Time in seconds a group entry will be given to live when 'touched' */
+	ecm_db_timer_group_t tg;			/* RO: The group id */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+extern struct ecm_db_timer_group ecm_db_timer_groups[ECM_DB_TIMER_GROUPS_MAX];
+
+uint32_t ecm_db_time_get(void);
+void ecm_db_timer_group_entry_init(struct ecm_db_timer_group_entry *tge, ecm_db_timer_group_entry_callback_t fn, void *arg);
+
+void _ecm_db_timer_group_entry_set(struct ecm_db_timer_group_entry *tge, ecm_db_timer_group_t tg);
+void ecm_db_timer_group_entry_set(struct ecm_db_timer_group_entry *tge, ecm_db_timer_group_t tg);
+
+bool ecm_db_timer_group_entry_reset(struct ecm_db_timer_group_entry *tge, ecm_db_timer_group_t tg);
+
+bool _ecm_db_timer_group_entry_remove(struct ecm_db_timer_group_entry *tge);
+bool ecm_db_timer_group_entry_remove(struct ecm_db_timer_group_entry *tge);
+
+bool ecm_db_timer_group_entry_touch(struct ecm_db_timer_group_entry *tge);
+
+void ecm_db_timer_init(void);
+void ecm_db_timer_exit(void);
diff --git a/qca-nss-ecm/ecm_db/ecm_db_types.h b/qca-nss-ecm/ecm_db/ecm_db_types.h
new file mode 100644
index 0000000..afdbebe
--- /dev/null
+++ b/qca-nss-ecm/ecm_db/ecm_db_types.h
@@ -0,0 +1,512 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014,2015,2017-2020 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * Listener
+ * Listeners are entities that monitor database events
+ */
+struct ecm_db_listener_instance;
+typedef void (*ecm_db_listener_final_callback_t)(void *arg);		/* Finaliser callback */
+
+/*
+ * Interface
+ * An interface represents an interface of this device to which nodes may be reached
+ */
+struct ecm_db_iface_instance;
+
+/*
+ * Node
+ * A node instance is the ethernet representation of the host, i.e. the mac address to send packets to when reaching the host
+ */
+struct ecm_db_node_instance;
+
+/*
+ * Host
+ * A host instance identifies a node by IP address
+ */
+struct ecm_db_host_instance;
+
+/*
+ * Host owner events
+ */
+typedef void (*ecm_db_host_final_callback_t)(void *arg);		/* Finaliser callback */
+
+/*
+ * Host listener events
+ */
+typedef void (*ecm_db_host_listener_added_callback_t)(void *arg, struct ecm_db_host_instance *hi);		/* Added callback */
+typedef void (*ecm_db_host_listener_removed_callback_t)(void *arg, struct ecm_db_host_instance *hi);		/* Removed callback */
+
+/*
+ * Mapping
+ * A mapping defines a port number.  Non-port based protocols will use -1 so they will all share to the same mapping instance.
+ */
+struct ecm_db_mapping_instance;
+
+/*
+ * Mapping owner events
+ */
+typedef void (*ecm_db_mapping_final_callback_t)(void *arg);		/* Finaliser callback */
+
+/*
+ * Mapping listener events
+ */
+typedef void (*ecm_db_mapping_listener_added_callback_t)(void *arg, struct ecm_db_mapping_instance *mi);		/* Added callback */
+typedef void (*ecm_db_mapping_listener_removed_callback_t)(void *arg, struct ecm_db_mapping_instance *mi);	/* Removed callback */
+
+/*
+ * Node
+ */
+typedef void (*ecm_db_node_final_callback_t)(void *arg);		/* Finaliser callback */
+typedef void (*ecm_db_node_listener_added_callback_t)(void *arg, struct ecm_db_node_instance *ni);		/* Added callback */
+typedef void (*ecm_db_node_listener_removed_callback_t)(void *arg, struct ecm_db_node_instance *ni);		/* Removed callback */
+
+/*
+ * Interface
+ */
+typedef void (*ecm_db_iface_final_callback_t)(void *arg);		/* Finaliser callback */
+typedef void (*ecm_db_iface_listener_added_callback_t)(void *arg, struct ecm_db_iface_instance *ii);		/* Added callback */
+typedef void (*ecm_db_iface_listener_removed_callback_t)(void *arg, struct ecm_db_iface_instance *ii);		/* Removed callback */
+
+/*
+ * Time out values - in seconds - used to configure timer groups
+ */
+#define ECM_DB_CLASSIFIER_DETERMINE_GENERIC_TIMEOUT 5
+#define ECM_DB_CONNECTION_GENERIC_TIMEOUT 240
+#define ECM_DB_CONNECTION_TCP_RST_TIMEOUT 240
+#define ECM_DB_CONNECTION_TCP_SHORT_TIMEOUT 240
+#define ECM_DB_CONNECTION_TCP_CLOSED_TIMEOUT 10
+#define ECM_DB_CONNECTION_TCP_LONG_TIMEOUT 3600
+#define ECM_DB_CONNECTION_UDP_TIMEOUT 300
+#define ECM_DB_CONNECTION_IGMP_TIMEOUT 240
+#define ECM_DB_CONNECTION_ICMP_TIMEOUT 60
+#define ECM_DB_CONNECTION_PPTP_DATA_TIMEOUT 300
+#define ECM_DB_CONNECTION_RTCP_TIMEOUT 1800
+#define ECM_DB_CONNECTION_RTSP_FAST_TIMEOUT 5
+#define ECM_DB_CONNECTION_RTSP_SLOW_TIMEOUT 120
+#define ECM_DB_CONNECTION_DNS_TIMEOUT 30
+#define ECM_DB_CONNECTION_FTP_TIMEOUT 60
+#define ECM_DB_CONNECTION_H323_TIMEOUT 28800
+#define ECM_DB_CONNECTION_IKE_TIMEOUT 54000
+#define ECM_DB_CONNECTION_ESP_TIMEOUT 7800
+#define ECM_DB_CONNECTION_ESP_PENDING_TIMEOUT 3
+#define ECM_DB_CONNECTION_SDP_TIMEOUT 120
+#define ECM_DB_CONNECTION_SIP_TIMEOUT 28800
+#define ECM_DB_CONNECTION_BITTORRENT_TIMEOUT 120
+#define ECM_DB_CONNECTION_DEFUNCT_RETRY_TIMEOUT 5
+
+/*
+ * ECM database object direction.
+ */
+enum ecm_db_obj_dir {
+	ECM_DB_OBJ_DIR_FROM,
+	ECM_DB_OBJ_DIR_TO,
+	ECM_DB_OBJ_DIR_FROM_NAT,
+	ECM_DB_OBJ_DIR_TO_NAT,
+	ECM_DB_OBJ_DIR_MAX
+};
+typedef enum ecm_db_obj_dir ecm_db_obj_dir_t;
+
+/*
+ * Extern decleration of common array that maps
+ * the object direction to a string.
+ */
+extern char *ecm_db_obj_dir_strings[ECM_DB_OBJ_DIR_MAX];
+
+/*
+ * Timer groups.
+ * WARNING: Only connections may use a connection timer group as these are subject to reaping.
+ */
+enum ecm_db_timer_groups {
+	ECM_DB_TIMER_GROUPS_CLASSIFIER_DETERMINE_GENERIC_TIMEOUT = 0,
+								/* Generic timeout for a classifier in determine phase */
+	ECM_DB_TIMER_GROUPS_CONNECTION_GENERIC_TIMEOUT,		/* Generic timeout for a connection */
+	ECM_DB_TIMER_GROUPS_CONNECTION_UDP_GENERIC_TIMEOUT,	/* Standard UDP Timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_UDP_WKP_TIMEOUT,		/* Standard UDP Timeout for all connections where at least one port is < 1024 */
+	ECM_DB_TIMER_GROUPS_CONNECTION_ICMP_TIMEOUT,		/* Standard ICMP Timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_TCP_SHORT_TIMEOUT,	/* TCP Short timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_TCP_RESET_TIMEOUT,	/* TCP Reset timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_TCP_CLOSED_TIMEOUT,	/* TCP Closed timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_TCP_LONG_TIMEOUT,	/* TCP Long timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_PPTP_DATA_TIMEOUT,	/* PPTP Tunnel Data timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_RTCP_TIMEOUT,		/* RTCP timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_RTSP_TIMEOUT,		/* RTSP connection timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_RTSP_FAST_TIMEOUT,	/* RTSP fast static NAT connection timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_RTSP_SLOW_TIMEOUT,	/* RTSP slow static NAT connection timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_DNS_TIMEOUT,		/* DNS timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_FTP_TIMEOUT,		/* FTP connection timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_H323_TIMEOUT,		/* H323 timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_IKE_TIMEOUT,		/* IKE timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_ESP_TIMEOUT,		/* ESP timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_ESP_PENDING_TIMEOUT,	/* ESP Pending connection timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_SDP_TIMEOUT,		/* SDP timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_SIP_TIMEOUT,		/* SIP timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_IGMP_TIMEOUT,		/* IGMP timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_BITTORRENT_TIMEOUT,	/* Bittorrent connections timeout */
+	ECM_DB_TIMER_GROUPS_CONNECTION_DEFUNCT_RETRY_TIMEOUT,	/* Defunct retry timeout */
+	ECM_DB_TIMER_GROUPS_MAX					/* Always the last one */
+};
+typedef enum ecm_db_timer_groups ecm_db_timer_group_t;
+typedef void (*ecm_db_timer_group_entry_callback_t)(void *arg);	/* Timer entry has expired */
+
+/*
+ * Ignore IP version check in connection instance
+ */
+#define ECM_DB_IP_VERSION_IGNORE 0
+
+#ifdef ECM_MULTICAST_ENABLE
+
+struct ecm_db_multicast_tuple_instance;
+
+/*
+ * Need to set this flag when Multicast is attached to ci and added to tuple hash table
+ */
+#define ECM_DB_MULTICAST_TUPLE_INSTANCE_FLAGS_INSERTED 0x1
+
+/*
+ *  This flag is used to find out whether a bridge device is present or not in a
+ *  multicast destination interface list, struct ecm_db_multicast_connection_instance
+ *  flags field use this flag.
+ */
+#define ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG 0x10
+
+/*
+ *  Maximum number of destination interfaces for
+ *  a multicast connection
+ */
+#define ECM_DB_MULTICAST_IF_MAX 16
+
+/*
+ * struct ecm_multicast_if_update
+ * 	This is used for storing processed updates to the destination
+ * 	interface list of a multicast connection. The updates are
+ * 	received from multicast routing or bridge snooper due to IGMP
+ * 	join or leave events
+ */
+struct ecm_multicast_if_update {
+	uint32_t if_join_cnt;
+	uint32_t if_join_idx[ECM_DB_MULTICAST_IF_MAX];
+	uint32_t join_dev[ECM_DB_MULTICAST_IF_MAX];
+	uint32_t if_leave_cnt;
+	uint32_t if_leave_idx[ECM_DB_MULTICAST_IF_MAX];
+};
+#endif
+
+/*
+ * struct ecm_db_timer_group_entry
+ *	Time entry structure used to request timer service
+ * WARNING: Do NOT inspect any of these fields - they are for exclusive use of the DB timer code.  Use the API's to control the timer and inspect its state.
+ */
+struct ecm_db_timer_group_entry {
+	struct ecm_db_timer_group_entry *next;			/* Link to the next entry in the timer group chain */
+	struct ecm_db_timer_group_entry *prev;			/* Link to the previous entry in the timer group chain */
+	uint32_t timeout;					/* Time this entry expires providing the timer group is not the ECM_DB_TIMER_GROUPS_MAX */
+	ecm_db_timer_group_t group;				/* The timer group to which this entry belongs, if this is ECM_DB_TIMER_GROUPS_MAX then the timer is not running */
+	void *arg;						/* Argument returned in callback */
+	ecm_db_timer_group_entry_callback_t fn;			/* Function called when timer expires */
+};
+
+/*
+ * Connection
+ * A connection links two mappings (hence two hosts).  This forms a channel of communication between two hosts.
+ */
+struct ecm_db_connection_instance;
+
+enum ecm_db_directions {
+	ECM_DB_DIRECTION_EGRESS_NAT,			/* LAN->WAN NAT */
+	ECM_DB_DIRECTION_INGRESS_NAT,			/* WAN->LAN NAT */
+	ECM_DB_DIRECTION_NON_NAT,			/* NET<>NET */
+	ECM_DB_DIRECTION_BRIDGED,			/* BRIDGED */
+};
+typedef enum ecm_db_directions ecm_db_direction_t;
+
+/*
+ * Connection listener events
+ */
+typedef void (*ecm_db_connection_listener_added_callback_t)(void *arg, struct ecm_db_connection_instance *ci);	/* Connection added callback */
+typedef void (*ecm_db_connection_listener_removed_callback_t)(void *arg, struct ecm_db_connection_instance *ci);	/* Connection removed callback */
+
+/*
+ * Connection creator events
+ */
+typedef void (*ecm_db_connection_final_callback_t)(void *arg);		/* Finaliser callback */
+
+/*
+ * Connection defunct event
+ */
+typedef bool (*ecm_db_connection_defunct_callback_t)(void *arg, int *accel_mode);	/* Defunct callback */
+
+/*
+ * Device Type for IPSec Tunnel devices
+ */
+#define ECM_ARPHRD_IPSEC_TUNNEL_TYPE 31			/* GGG Should be part of the kernel as a general ARPHRD_XYZ but is not */
+
+/*
+ * Interface types
+ */
+enum ecm_db_iface_types {
+	ECM_DB_IFACE_TYPE_ETHERNET = 0,			/* Interface is an ethernet type */
+	ECM_DB_IFACE_TYPE_PPPOE,			/* Interface is a PPPoE interface (a specific form of PPP that we recognise in the ECM) */
+	ECM_DB_IFACE_TYPE_LAG,				/* Interface is a Link Aggregated interface */
+	ECM_DB_IFACE_TYPE_VLAN,				/* Interface is a VLAN interface (802.1Q) */
+	ECM_DB_IFACE_TYPE_BRIDGE,			/* Interface is a bridge interface */
+	ECM_DB_IFACE_TYPE_LOOPBACK,			/* Interface is a loopback interface */
+	ECM_DB_IFACE_TYPE_IPSEC_TUNNEL,			/* Interface is a IPSec tunnel interface */
+	ECM_DB_IFACE_TYPE_UNKNOWN,			/* Interface is unknown to the ECM */
+	ECM_DB_IFACE_TYPE_SIT,				/* IPv6 in IPv4 tunnel (SIT) interface */
+	ECM_DB_IFACE_TYPE_TUNIPIP6,			/* IPIP6 Tunnel (TUNNEL6) interface */
+	ECM_DB_IFACE_TYPE_PPPOL2TPV2,			/* Interface is a PPPoL2TPV2 interface (a specific form of PPP that we recognise in the ECM) */
+	ECM_DB_IFACE_TYPE_PPTP,				/* Interface is a PPTP interface */
+	ECM_DB_IFACE_TYPE_MAP_T,			/* Interface is a MAP-T interface */
+	ECM_DB_IFACE_TYPE_GRE_TUN,			/* Interface is a GRE TUN tunnel interface */
+	ECM_DB_IFACE_TYPE_GRE_TAP,			/* Interface is a GRE TAP tunnel interface */
+	ECM_DB_IFACE_TYPE_RAWIP,			/* Interface is a RAWIP interface */
+	ECM_DB_IFACE_TYPE_OVPN,				/* Interface is a OVPN interface */
+	ECM_DB_IFACE_TYPE_VXLAN,			/* Interface is a VxLAN interface */
+	ECM_DB_IFACE_TYPE_OVS_BRIDGE,			/* Interface is a OpenvSwitch bridge interface */
+	ECM_DB_IFACE_TYPE_MACVLAN,			/* Interface is a MACVLAN interface */
+	ECM_DB_IFACE_TYPE_COUNT,			/* Number of interface types */
+};
+typedef enum ecm_db_iface_types ecm_db_iface_type_t;
+
+/*
+ * Interface information as stored in the ECM db for known types of interface
+ */
+struct ecm_db_interface_info_ethernet {			/* type == ECM_DB_IFACE_TYPE_ETHERNET */
+	uint8_t address[ETH_ALEN];			/* MAC Address of this Interface */
+};
+
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+struct ecm_db_interface_info_vxlan {			/* type == ECM_DB_IFACE_TYPE_VXLAN */
+	uint32_t vni;					/* VxLAN network identifier */
+	uint32_t if_type;				/* VxLAN interface type */
+};
+#endif
+
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+struct ecm_db_interface_info_vlan {			/* type == ECM_DB_IFACE_TYPE_VLAN */
+	uint8_t address[ETH_ALEN];			/* MAC Address of this Interface */
+	uint16_t vlan_tpid;				/* VLAN tag protocol id */
+	uint16_t vlan_tag;				/* VLAN tag of this interface */
+};
+#endif
+
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+struct ecm_db_interface_info_macvlan {			/* type == ECM_DB_IFACE_TYPE_MACVLAN */
+	uint8_t address[ETH_ALEN];			/* MAC Address of this Interface */
+};
+#endif
+
+#ifdef ECM_INTERFACE_BOND_ENABLE
+struct ecm_db_interface_info_lag {			/* type == ECM_DB_IFACE_TYPE_LAG */
+	uint8_t address[ETH_ALEN];			/* MAC Address of this Interface */
+};
+#endif
+
+struct ecm_db_interface_info_bridge {			/* type == ECM_DB_IFACE_TYPE_BRIDGE */
+	uint8_t address[ETH_ALEN];			/* MAC Address of this Interface */
+};
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+struct ecm_db_interface_info_ovs_bridge {		/* type == ECM_DB_IFACE_TYPE_OVS_BRIDGE */
+	uint8_t address[ETH_ALEN];			/* MAC Address of this Interface */
+};
+#endif
+
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+struct ecm_db_interface_info_pppoe {			/* type == ECM_DB_IFACE_TYPE_PPPOE */
+	uint16_t pppoe_session_id;			/* PPPoE session ID on this interface, when applicable */
+	uint8_t remote_mac[ETH_ALEN];			/* MAC Address of the PPPoE concentrator */
+};
+#endif
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+struct ecm_db_interface_info_pppol2tpv2 {                  /* type == ECM_DB_IFACE_TYPE_PPPOL2TPV2 */
+	struct {
+		struct {
+			uint32_t tunnel_id;
+			uint32_t peer_tunnel_id;
+		} tunnel;
+		struct {
+			uint32_t session_id;
+			uint32_t peer_session_id;
+		} session;
+	} l2tp;
+
+	struct {
+		uint16_t sport, dport;
+	} udp;
+
+	struct {
+		uint32_t  saddr, daddr;
+	} ip;
+};
+
+#endif
+
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+struct ecm_db_interface_info_pptp {
+	uint32_t src_ip;
+	uint32_t dst_ip;
+	uint16_t src_call_id;
+	uint16_t dst_call_id;
+};
+#endif
+
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+struct ecm_db_interface_info_map_t {                  /* type == ECM_DB_IFACE_TYPE_MAP_T */
+	int32_t if_index;
+};
+#endif
+
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+struct ecm_db_interface_info_gre_tun {			/* type == ECM_DB_IFACE_TYPE_GRE_TUN */
+	int32_t if_index;
+	ip_addr_t local_ip;
+	ip_addr_t remote_ip;
+};
+#endif
+
+struct ecm_db_interface_info_unknown {			/* type == ECM_DB_IFACE_TYPE_UNKNOWN */
+	uint32_t os_specific_ident;			/* Operating system specific identifier (known only by front end) */
+};
+
+struct ecm_db_interface_info_loopback {			/* type == ECM_DB_IFACE_TYPE_LOOPBACK */
+	uint32_t os_specific_ident;			/* Operating system specific identifier (known only by front end) */
+};
+
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+struct ecm_db_interface_info_ipsec_tunnel {		/* type == ECM_DB_IFACE_TYPE_IPSEC_TUNNEL */
+	uint32_t os_specific_ident;			/* Operating system specific identifier (known only by front end) */
+	// GGG TODO Flesh this out with tunnel endpoint addressing detal
+};
+#endif
+
+#ifdef ECM_INTERFACE_SIT_ENABLE
+struct ecm_db_interface_info_sit {			/* type == ECM_DB_IFACE_TYPE_SIT */
+	ip_addr_t saddr;				/* Tunnel source address */
+	ip_addr_t daddr;				/* Tunnel destination addresss */
+	uint8_t  tos;					/* Tunnel tos field */
+	uint8_t  ttl;					/* Tunnel ttl field */
+};
+#endif
+
+#ifdef ECM_INTERFACE_TUNIPIP6_ENABLE
+struct ecm_db_interface_info_tunipip6 {			/* type == ECM_DB_IFACE_TYPE_TUNIPIP6 */
+	ip_addr_t saddr;				/* Tunnel source address */
+	ip_addr_t daddr;				/* Tunnel destination address */
+	uint32_t flowlabel;				/* Tunnel ipv6 flowlabel */
+	uint32_t flags;					/* Tunnel additional flags */
+	uint8_t  hop_limit;				/* Tunnel ipv6 hop limit */
+};
+#endif
+
+#ifdef ECM_INTERFACE_RAWIP_ENABLE
+struct ecm_db_interface_info_rawip {			/* type == ECM_DB_IFACE_TYPE_RAWIP */
+	uint8_t address[ETH_ALEN];			/* TODO: Random MAC Address generated by kernel */
+};
+#endif
+
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+struct ecm_db_interface_info_ovpn {			/* type == ECM_DB_IFACE_TYPE_OVPN */
+	int32_t tun_ifnum;				/* Tunnel interface number */
+};
+#endif
+
+/*
+ * Interface Heirarchy
+ * Each connection instance keeps four lists of interfaces.
+ * These lists record the 'interface heirarchy' in the from or to direction for the connection for both NAT and non-NAT.
+ * For example, a connection that is 'from' a vlan might have two interfaces in its 'from' heirarchy:
+ * The raw interface, e.g. eth0 and the vlan interface perhaps eth0.1.
+ * NOTE: Commonly referred to as "inner to outermost" interfaces.
+ * For a connection the ci->mi->hi->ni->ii records the interfaces that the connection 'sees' for the from/to paths.  I.e. Innermost.
+ * But heirarchy lists record the path from the ii to the actual outward facing interface - well, as far as is possible to detect.
+ * A heirarchy list is recorded in reverse so in the example here it would list eth0 followed by eth0.1.
+ * Therefore the first interface in the list is the outermost interface, which is for acceleration, hopefully an accel engine supported interface.
+ * Lists have a finite size.
+ */
+#define ECM_DB_IFACE_HEIRARCHY_MAX 9 /* This is the number of interfaces allowed in a heirarchy */
+
+#ifdef ECM_MULTICAST_ENABLE
+/*
+ * Buffer size for multicast destination interface list
+ */
+#define ECM_DB_TO_MCAST_INTERFACES_SIZE (sizeof(struct ecm_db_iface_instance *) * ECM_DB_MULTICAST_IF_MAX * ECM_DB_IFACE_HEIRARCHY_MAX)
+
+/*
+ * ecm_db_multicast_if_heirarchy_get()
+ * 	Returns the address of next heirarchy row from base address of the current heirarchy.
+ */
+static inline struct ecm_db_iface_instance *ecm_db_multicast_if_heirarchy_get(struct ecm_db_iface_instance *heirarchy_base, uint32_t index)
+{
+	unsigned long *heirarchy_instance = (unsigned long *)heirarchy_base;
+	DEBUG_ASSERT(heirarchy_instance, "Bad memory, multicast interfaces list has been already freed\n");
+	DEBUG_ASSERT((index <= ECM_DB_MULTICAST_IF_MAX), "Bad index %u\n", index);
+	return (struct ecm_db_iface_instance *)(heirarchy_instance + (index * ECM_DB_IFACE_HEIRARCHY_MAX));
+}
+
+/*
+ * ecm_db_multicast_if_instance_get_at_index()
+ *	Returns a single interface instance pointer from heirarchy at position index.
+ */
+static inline struct ecm_db_iface_instance *ecm_db_multicast_if_instance_get_at_index(struct ecm_db_iface_instance *heirarchy_start, uint32_t index)
+{
+	unsigned long *iface_instance = (unsigned long *)heirarchy_start;
+	DEBUG_ASSERT(iface_instance, "Bad memory, multicast interfaces list has been already freed\n");
+	DEBUG_ASSERT((index <= ECM_DB_IFACE_HEIRARCHY_MAX), "Bad first %u\n", index);
+	return (struct ecm_db_iface_instance *)(iface_instance + index);
+}
+
+/*
+ * ecm_db_multicast_if_first_get_at_index()
+ *	Returns a index of the first interface in the list at index position.
+ */
+static inline int32_t *ecm_db_multicast_if_first_get_at_index(int32_t *if_first, uint32_t index)
+{
+	DEBUG_ASSERT(if_first, "Bad memory, multicast interfaces first has been already freed\n");
+	DEBUG_ASSERT((index <= ECM_DB_MULTICAST_IF_MAX), "Bad first %u\n", index);
+	return (if_first + index);
+}
+
+/*
+ * ecm_db_multicast_if_num_get_at_index()
+ *	Returns a pointer to 'if_index' entry in an array at index position.
+ */
+static inline int32_t *ecm_db_multicast_if_num_get_at_index(int32_t *if_num, uint32_t index)
+{
+	DEBUG_ASSERT(if_num, "Bad memory, ifindex list has been already freed\n");
+	return (if_num + index);
+}
+
+/*
+ * ecm_db_multicast_copy_if_heirarchy()
+ * 	Copy a heirarchy into an array of pointers starting from the heirarchy.
+ */
+static inline void ecm_db_multicast_copy_if_heirarchy(struct ecm_db_iface_instance *if_hr[], struct ecm_db_iface_instance *heirarchy_start)
+{
+	unsigned long *iface_instance = (unsigned long *)heirarchy_start;
+	struct ecm_db_iface_instance **heirarchy;
+	int i;
+
+	DEBUG_ASSERT(iface_instance, "Bad memory, multicast interfaces list has been already freed\n");
+
+        for (i = 0; i < ECM_DB_IFACE_HEIRARCHY_MAX; i++) {
+		heirarchy = (struct ecm_db_iface_instance **)iface_instance;
+                if_hr[i] = *heirarchy;
+                iface_instance = iface_instance + 1;
+        }
+}
+#endif
diff --git a/qca-nss-ecm/ecm_init.c b/qca-nss-ecm/ecm_init.c
new file mode 100644
index 0000000..f80645b
--- /dev/null
+++ b/qca-nss-ecm/ecm_init.c
@@ -0,0 +1,392 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2016, 2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/debugfs.h>
+#include <linux/inet.h>
+#include <linux/etherdevice.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/ip.h>
+#include <net/ipv6.h>
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_INIT_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_db.h"
+#include "ecm_front_end_ipv4.h"
+#ifdef ECM_IPV6_ENABLE
+#include "ecm_front_end_ipv6.h"
+#endif
+#include "ecm_front_end_common.h"
+#include "ecm_conntrack_notifier.h"
+
+enum ecm_front_end_type selected_front_end;
+
+int front_end_selection;
+module_param(front_end_selection, int, 0);
+MODULE_PARM_DESC(front_end_selection, "Select front end for ECM");
+
+struct dentry *ecm_dentry;	/* Dentry object for top level ecm debugfs directory */
+
+extern int ecm_db_init(struct dentry *dentry);
+extern void ecm_db_connection_defunct_all(void);
+extern void ecm_db_exit(void);
+
+extern int ecm_classifier_default_init(struct dentry *dentry);
+extern void ecm_classifier_default_exit(void);
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+extern int ecm_classifier_ovs_init(struct dentry *dentry);
+extern void ecm_classifier_ovs_exit(void);
+#endif
+
+#ifdef ECM_CLASSIFIER_MARK_ENABLE
+extern int ecm_classifier_mark_init(struct dentry *dentry);
+extern void ecm_classifier_mark_exit(void);
+#endif
+
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+extern int ecm_classifier_nl_rules_init(struct dentry *dentry);
+extern void ecm_classifier_nl_rules_exit(void);
+#endif
+
+#ifdef ECM_CLASSIFIER_HYFI_ENABLE
+extern int ecm_classifier_hyfi_rules_init(struct dentry *dentry);
+extern void ecm_classifier_hyfi_rules_exit(void);
+#endif
+
+extern int ecm_interface_init(void);
+extern void ecm_interface_exit(void);
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+extern int ecm_classifier_dscp_init(struct dentry *dentry);
+extern void ecm_classifier_dscp_exit(void);
+#endif
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+extern int ecm_state_init(struct dentry *dentry);
+extern void ecm_state_exit(void);
+#endif
+
+#ifdef ECM_CLASSIFIER_PCC_ENABLE
+extern int ecm_classifier_pcc_init(struct dentry *dentry);
+extern void ecm_classifier_pcc_exit(void);
+#endif
+
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+extern int ecm_classifier_emesh_init(struct dentry *dentry);
+extern void ecm_classifier_emesh_exit(void);
+#endif
+#ifdef ECM_CLASSIFIER_MSCS_ENABLE
+extern int ecm_classifier_mscs_init(struct dentry *dentry);
+extern void ecm_classifier_mscs_exit(void);
+#endif
+
+/*
+ * ecm_init()
+ */
+static int __init ecm_init(void)
+{
+	int ret;
+
+	printk(KERN_INFO "ECM init\n");
+
+	selected_front_end = ecm_front_end_type_select();
+	if (selected_front_end == ECM_FRONT_END_TYPE_MAX) {
+		DEBUG_ERROR("Front-end couldn't be selected\n");
+		return -1;
+	}
+
+	ecm_dentry = debugfs_create_dir("ecm", NULL);
+	if (!ecm_dentry) {
+		DEBUG_ERROR("Failed to create ecm directory in debugfs\n");
+		return -1;
+	}
+
+	ret = ecm_db_init(ecm_dentry);
+	if (0 != ret) {
+		goto err_db;
+	}
+
+	ret = ecm_classifier_default_init(ecm_dentry);
+	if (0 != ret) {
+		goto err_cls_default;
+	}
+
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+	ret = ecm_classifier_nl_rules_init(ecm_dentry);
+	if (0 != ret) {
+		goto err_cls_nl;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_HYFI_ENABLE
+	ret = ecm_classifier_hyfi_rules_init(ecm_dentry);
+	if (0 != ret) {
+		goto err_cls_hyfi;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+	ret = ecm_classifier_dscp_init(ecm_dentry);
+	if (0 != ret) {
+		goto err_cls_dscp;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_PCC_ENABLE
+	ret = ecm_classifier_pcc_init(ecm_dentry);
+	if (0 != ret) {
+		goto err_cls_pcc;
+	}
+#endif
+#ifdef ECM_CLASSIFIER_MARK_ENABLE
+	ret = ecm_classifier_mark_init(ecm_dentry);
+	if (0 != ret) {
+		goto err_cls_mark;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+	ret = ecm_classifier_ovs_init(ecm_dentry);
+	if (0 != ret) {
+		goto err_cls_ovs;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+	ret = ecm_classifier_emesh_init(ecm_dentry);
+	if (0 != ret) {
+		goto err_cls_emesh;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_MSCS_ENABLE
+	ret = ecm_classifier_mscs_init(ecm_dentry);
+	if (0 != ret) {
+		goto err_cls_mscs;
+	}
+#endif
+
+	ret = ecm_interface_init();
+	if (0 != ret) {
+		goto err_iface;
+	}
+
+#ifdef ECM_INTERFACE_BOND_ENABLE
+	ret = ecm_front_end_bond_notifier_init(ecm_dentry);
+	if (0 != ret) {
+		goto err_bond;
+	}
+#endif
+
+	ret = ecm_front_end_ipv4_init(ecm_dentry);
+	if (0 != ret) {
+		goto err_fe_ipv4;
+	}
+
+#ifdef ECM_IPV6_ENABLE
+	ret = ecm_front_end_ipv6_init(ecm_dentry);
+	if (0 != ret) {
+		goto err_fe_ipv6;
+	}
+#endif
+
+	ret = ecm_conntrack_notifier_init(ecm_dentry);
+	if (0 != ret) {
+		goto err_ct;
+	}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ret = ecm_state_init(ecm_dentry);
+	if (0 != ret) {
+		goto err_state;
+	}
+#endif
+
+	ecm_front_end_common_sysctl_register();
+
+	printk(KERN_INFO "ECM init complete\n");
+	return 0;
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+err_state:
+	ecm_conntrack_notifier_exit();
+#endif
+err_ct:
+#ifdef ECM_IPV6_ENABLE
+	ecm_front_end_ipv6_exit();
+err_fe_ipv6:
+#endif
+	ecm_front_end_ipv4_exit();
+err_fe_ipv4:
+#ifdef ECM_INTERFACE_BOND_ENABLE
+	ecm_front_end_bond_notifier_exit();
+err_bond:
+#endif
+	ecm_interface_exit();
+err_iface:
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+	ecm_classifier_emesh_exit();
+err_cls_emesh:
+#endif
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+	ecm_classifier_ovs_exit();
+err_cls_ovs:
+#endif
+#ifdef ECM_CLASSIFIER_MARK_ENABLE
+	ecm_classifier_mark_exit();
+err_cls_mark:
+#endif
+#ifdef ECM_CLASSIFIER_PCC_ENABLE
+	ecm_classifier_pcc_exit();
+err_cls_pcc:
+#endif
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+	ecm_classifier_dscp_exit();
+err_cls_dscp:
+#endif
+#ifdef ECM_CLASSIFIER_HYFI_ENABLE
+	ecm_classifier_hyfi_rules_exit();
+err_cls_hyfi:
+#endif
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+	ecm_classifier_nl_rules_exit();
+err_cls_nl:
+#endif
+#ifdef ECM_CLASSIFIER_MSCS_ENABLE
+	ecm_classifier_mscs_exit();
+err_cls_mscs:
+#endif
+	ecm_classifier_default_exit();
+err_cls_default:
+	ecm_db_exit();
+err_db:
+	debugfs_remove_recursive(ecm_dentry);
+
+	printk(KERN_INFO "ECM init failed: %d\n", ret);
+	return ret;
+}
+
+/*
+ * ecm_exit()
+ */
+static void __exit ecm_exit(void)
+{
+	printk(KERN_INFO "ECM exit\n");
+
+	/* call stop on anything that requires a prepare-to-exit signal */
+	DEBUG_INFO("stop conntrack notifier\n");
+	ecm_conntrack_notifier_stop(1);
+	DEBUG_INFO("stop front_end_ipv4\n");
+	ecm_front_end_ipv4_stop(1);
+#ifdef ECM_IPV6_ENABLE
+	DEBUG_INFO("stop front_end_ipv6\n");
+	ecm_front_end_ipv6_stop(1);
+#endif
+#ifdef ECM_INTERFACE_BOND_ENABLE
+	DEBUG_INFO("stop bond notifier\n");
+	ecm_front_end_bond_notifier_stop(1);
+#endif
+	DEBUG_INFO("defunct all db connections\n");
+	ecm_db_connection_defunct_all();
+
+	/* now call exit on each module */
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	DEBUG_INFO("stop state\n");
+	ecm_state_exit();
+#endif
+	DEBUG_INFO("exit conntrack notifier\n");
+	ecm_conntrack_notifier_exit();
+	DEBUG_INFO("exit front_end_ipv4\n");
+	ecm_front_end_ipv4_exit();
+#ifdef ECM_IPV6_ENABLE
+	DEBUG_INFO("exit front_end_ipv6\n");
+	ecm_front_end_ipv6_exit();
+#endif
+#ifdef ECM_INTERFACE_BOND_ENABLE
+	DEBUG_INFO("exit bond notifier\n");
+	ecm_front_end_bond_notifier_exit();
+#endif
+	DEBUG_INFO("exit interface\n");
+	ecm_interface_exit();
+
+#ifdef ECM_CLASSIFIER_PCC_ENABLE
+	DEBUG_INFO("exit pcc classifier\n");
+	ecm_classifier_pcc_exit();
+#endif
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+	DEBUG_INFO("exit dscp classifier\n");
+	ecm_classifier_dscp_exit();
+#endif
+#ifdef ECM_CLASSIFIER_HYFI_ENABLE
+	DEBUG_INFO("exit hyfi classifier\n");
+	ecm_classifier_hyfi_rules_exit();
+#endif
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+	DEBUG_INFO("exit nl classifier\n");
+	ecm_classifier_nl_rules_exit();
+#endif
+#ifdef ECM_CLASSIFIER_MARK_ENABLE
+	DEBUG_INFO("exit mark classifier\n");
+	ecm_classifier_mark_exit();
+#endif
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+	DEBUG_INFO("exit ovs classifier\n");
+	ecm_classifier_ovs_exit();
+#endif
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+	DEBUG_INFO("exit emesh classifier\n");
+	ecm_classifier_emesh_exit();
+#endif
+#ifdef ECM_CLASSIFIER_MSCS_ENABLE
+	DEBUG_INFO("exit mscs classifier\n");
+	ecm_classifier_mscs_exit();
+#endif
+	DEBUG_INFO("exit default classifier\n");
+	ecm_classifier_default_exit();
+	DEBUG_INFO("exit db\n");
+	ecm_db_exit();
+
+	if (ecm_dentry != NULL) {
+		DEBUG_INFO("remove ecm debugfs\n");
+		debugfs_remove_recursive(ecm_dentry);
+	}
+
+	ecm_front_end_common_sysctl_unregister();
+
+	printk(KERN_INFO "ECM exit complete\n");
+}
+
+module_init(ecm_init)
+module_exit(ecm_exit)
+
+MODULE_DESCRIPTION("ECM Core");
+MODULE_LICENSE("Dual BSD/GPL");
+
diff --git a/qca-nss-ecm/ecm_interface.c b/qca-nss-ecm/ecm_interface.c
new file mode 100644
index 0000000..52bd11b
--- /dev/null
+++ b/qca-nss-ecm/ecm_interface.c
@@ -0,0 +1,8387 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/ip6_route.h>
+#include <net/ip6_fib.h>
+#include <net/ipv6.h>
+#include <net/route.h>
+#include <net/ip_fib.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <net/addrconf.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <linux/inet.h>
+#include <linux/in6.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/kernel.h>
+#include <linux/netlink.h>
+#include <linux/rtnetlink.h>
+#include <linux/socket.h>
+#include <linux/wireless.h>
+#include <net/gre.h>
+
+#if defined(ECM_DB_XREF_ENABLE) && defined(ECM_BAND_STEERING_ENABLE)
+#include <linux/if_bridge.h>
+#endif
+#include <linux/inetdevice.h>
+#if defined(ECM_INTERFACE_TUNIPIP6_ENABLE) || defined(ECM_INTERFACE_SIT_ENABLE)
+#include <net/ip_tunnels.h>
+#endif
+#include <net/ip6_tunnel.h>
+#include <net/addrconf.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <linux/netfilter_ipv6/ip6_tables.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+#ifdef ECM_INTERFACE_PPP_ENABLE
+#include <linux/if_pppox.h>
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+#include <linux/if_pppol2tp.h>
+#endif
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+#include <linux/netfilter/nf_conntrack_proto_gre.h>
+#endif
+#endif
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+#include <nat46-core.h>
+#endif
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+#include <net/vxlan.h>
+#endif
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+#include <ovsmgr.h>
+#endif
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+#include <linux/if_macvlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_INTERFACE_DEBUG_LEVEL
+
+#ifdef ECM_MULTICAST_ENABLE
+#include <mc_ecm.h>
+#endif
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_front_end_ipv4.h"
+#ifdef ECM_IPV6_ENABLE
+#include "ecm_front_end_ipv6.h"
+#endif
+#include "ecm_interface.h"
+#include "exports/ecm_interface_ipsec.h"
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+#include "ecm_interface_ovpn.h"
+#endif
+
+/*
+ * Wifi event handler structure.
+ */
+struct ecm_interface_wifi_event {
+	struct task_struct *thread;
+	struct socket *sock;
+};
+
+static struct ecm_interface_wifi_event __ewn;
+
+#ifdef ECM_INTERFACE_IPSEC_GLUE_LAYER_SUPPORT_ENABLE
+/*
+ * Get ipsecmgr tunnel netdevice method
+ */
+static struct ecm_interface_ipsec_callback ecm_interface_ipsec_cb;
+#endif
+
+/*
+ * Locking - concurrency control
+ */
+static DEFINE_SPINLOCK(ecm_interface_lock);			/* Protect against SMP access between netfilter, events and private threaded function. */
+
+/*
+ * Management thread control
+ */
+static bool ecm_interface_terminate_pending = false;		/* True when the user has signalled we should quit */
+
+/*
+ * Source interface check flag.
+ *	If it is enabled, the acceleration engine will check the flow's interface to see
+ *	whether it matches with the rule's source interface or not.
+ */
+int ecm_interface_src_check;
+
+#if defined(CONFIG_NET_CLS_ACT) && defined(ECM_CLASSIFIER_DSCP_IGS)
+/*
+ * IGS enabled flag.
+ *	If it is enabled, the acceleration engine will deny the acceleration for the new
+ *	connnection, if the egress interface has ingress qdisc enabled over it.
+ */
+int ecm_interface_igs_enabled;
+#endif
+
+static struct ctl_table_header *ecm_interface_ctl_table_header;	/* Sysctl table header */
+
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+/*
+ * Callback structure to support OVPN offload.
+ */
+static struct ecm_interface_ovpn ovpn;
+
+/*
+ * ecm_interface_ovpn_register
+ */
+int ecm_interface_ovpn_register(struct ecm_interface_ovpn *ovpn_cb)
+{
+	spin_lock_bh(&ecm_interface_lock);
+	if (ovpn.ovpn_update_route) {
+		spin_unlock_bh(&ecm_interface_lock);
+		DEBUG_ERROR("OVPN callbacks are registered\n");
+		return -1;
+	}
+
+	ovpn.ovpn_update_route = ovpn_cb->ovpn_update_route;
+	ovpn.ovpn_get_ifnum = ovpn_cb->ovpn_get_ifnum;
+	spin_unlock_bh(&ecm_interface_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_interface_ovpn_register);
+
+/*
+ * ecm_interface_ovpn_unregister
+ */
+void ecm_interface_ovpn_unregister(void)
+{
+	spin_lock_bh(&ecm_interface_lock);
+	ovpn.ovpn_update_route = NULL;
+	ovpn.ovpn_get_ifnum = NULL;
+	spin_unlock_bh(&ecm_interface_lock);
+}
+EXPORT_SYMBOL(ecm_interface_ovpn_unregister);
+
+/*
+ * ecm_interface_ovpn_get_ifnum
+ */
+static int ecm_interface_ovpn_get_ifnum(struct net_device *dev, struct sk_buff *skb, struct net_device **tun_dev)
+{
+	int ret = -1;
+
+	DEBUG_TRACE("Calling registered function to get OVPN ifnum.\n");
+
+	spin_lock_bh(&ecm_interface_lock);
+	if (likely(ovpn.ovpn_get_ifnum)) {
+		ret = ovpn.ovpn_get_ifnum(dev, skb, tun_dev);
+	}
+	spin_unlock_bh(&ecm_interface_lock);
+
+	return ret;
+}
+
+/*
+ * ecm_interface_ovpn_update_route
+ */
+static void ecm_interface_ovpn_update_route(struct net_device *dev, uint32_t *from_addr, uint32_t *to_addr, int version)
+{
+	DEBUG_TRACE("Calling registered function to update OVPN route entry.\n");
+
+	spin_lock_bh(&ecm_interface_lock);
+	if (likely(ovpn.ovpn_update_route)) {
+		ovpn.ovpn_update_route(dev, from_addr, to_addr, version);
+	}
+	spin_unlock_bh(&ecm_interface_lock);
+}
+#endif
+
+/*
+ * ecm_interface_get_and_hold_ipsec_tun_netdev()
+ * 	Returns the nss tunnel interface net_dev
+ */
+struct net_device *ecm_interface_get_and_hold_ipsec_tun_netdev(struct net_device *dev, struct sk_buff *skb, int32_t *interface_type)
+{
+	struct net_device *ipsec_dev = NULL;
+#ifdef ECM_INTERFACE_IPSEC_GLUE_LAYER_SUPPORT_ENABLE
+	spin_lock_bh(&ecm_interface_lock);
+	if (!ecm_interface_ipsec_cb.tunnel_get_and_hold) {
+		spin_unlock_bh(&ecm_interface_lock);
+		DEBUG_WARN("IPSec glue module is not loaded yet\n");
+		return NULL;
+	}
+
+	ipsec_dev = ecm_interface_ipsec_cb.tunnel_get_and_hold(dev, skb, interface_type);
+	spin_unlock_bh(&ecm_interface_lock);
+#endif
+	return ipsec_dev;
+}
+
+/*
+ * ecm_interface_get_and_hold_dev_master()
+ *	Returns the master device of a net device if any.
+ */
+struct net_device *ecm_interface_get_and_hold_dev_master(struct net_device *dev)
+{
+	struct net_device *master;
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+	if (ecm_interface_is_ovs_bridge_port(dev)) {
+		master = ovsmgr_dev_get_master(dev);
+		if (!master) {
+			return NULL;
+		}
+
+		dev_hold(master);
+		return master;
+	}
+#endif
+	rcu_read_lock();
+	master = netdev_master_upper_dev_get_rcu(dev);
+	if (!master) {
+		rcu_read_unlock();
+		return NULL;
+	}
+	dev_hold(master);
+	rcu_read_unlock();
+
+	return master;
+}
+EXPORT_SYMBOL(ecm_interface_get_and_hold_dev_master);
+
+/*
+ * ecm_interface_vlan_real_dev()
+ *	Return immediate VLAN net device or Physical device pointer
+ */
+static inline struct net_device *ecm_interface_vlan_real_dev(struct net_device *vlan_dev)
+{
+	return vlan_dev_next_dev(vlan_dev);
+}
+
+/*
+ * ecm_interface_dev_find_by_local_addr_ipv4()
+ *	Return a hold to the device for the given local IP address. Returns NULL on failure.
+ */
+static struct net_device *ecm_interface_dev_find_by_local_addr_ipv4(ip_addr_t addr)
+{
+	__be32 be_addr;
+	struct net_device *dev;
+
+	ECM_IP_ADDR_TO_NIN4_ADDR(be_addr, addr);
+	dev = ip_dev_find(&init_net, be_addr);
+	return dev;
+}
+
+#ifdef ECM_IPV6_ENABLE
+/*
+ * ecm_interface_dev_find_by_local_addr_ipv6()
+ *	Return a hold to the device for the given local IP address.  Returns NULL on failure.
+ */
+static struct net_device *ecm_interface_dev_find_by_local_addr_ipv6(ip_addr_t addr)
+{
+	struct in6_addr addr6;
+	struct net_device *dev;
+
+	ECM_IP_ADDR_TO_NIN6_ADDR(addr6, addr);
+	dev = (struct net_device *)ipv6_dev_find(&init_net, &addr6, 1);
+	return dev;
+}
+#endif
+
+/*
+ * ecm_interface_dev_find_by_local_addr()
+ *	Return the device on which the local address resides.
+ *
+ * Returns a hold to the device or NULL on failure.
+ */
+struct net_device *ecm_interface_dev_find_by_local_addr(ip_addr_t addr)
+{
+	char __attribute__((unused)) addr_str[40];
+
+	DEBUG_ECM_IP_ADDR_TO_STRING(addr_str, addr);
+	DEBUG_TRACE("Locate dev for: %s\n", addr_str);
+
+	if (ECM_IP_ADDR_IS_V4(addr)) {
+		return ecm_interface_dev_find_by_local_addr_ipv4(addr);
+	}
+
+#ifdef ECM_IPV6_ENABLE
+	return ecm_interface_dev_find_by_local_addr_ipv6(addr);
+#else
+	return NULL;
+#endif
+}
+EXPORT_SYMBOL(ecm_interface_dev_find_by_local_addr);
+
+/*
+ * ecm_interface_dev_find_by_addr()
+ *	Return the net device on which the given IP address resides.  Returns NULL on faiure.
+ *
+ * NOTE: The device may be the device upon which has a default gateway to reach the address.
+ * from_local_addr is true when the device was found by a local address search.
+ */
+struct net_device *ecm_interface_dev_find_by_addr(ip_addr_t addr, bool *from_local_addr)
+{
+	char __attribute__((unused)) addr_str[40];
+	struct ecm_interface_route ecm_rt;
+	struct net_device *dev;
+	struct dst_entry *dst;
+
+	DEBUG_ECM_IP_ADDR_TO_STRING(addr_str, addr);
+
+	/*
+	 * Is the address a local IP?
+	 */
+	DEBUG_TRACE("find net device for address: %s\n", addr_str);
+	dev = ecm_interface_dev_find_by_local_addr(addr);
+	if (dev) {
+		 *from_local_addr = true;
+		DEBUG_TRACE("addr: %s is local: %px (%s)\n", addr_str, dev, dev->name);
+		return dev;
+	}
+
+	DEBUG_TRACE("addr: %s is not local\n", addr_str);
+
+	/*
+	 * Try a route to the address instead
+	 * NOTE: This will locate a route entry in the route destination *cache*.
+	 */
+	if (!ecm_interface_find_route_by_addr(addr, &ecm_rt)) {
+		DEBUG_WARN("addr: %s - no dev locatable\n", addr_str);
+		return NULL;
+	}
+
+	*from_local_addr = false;
+	dst = ecm_rt.dst;
+	dev = dst->dev;
+	dev_hold(dev);
+	ecm_interface_route_release(&ecm_rt);
+	DEBUG_TRACE("dest_addr: %s uses dev: %px(%s)\n", addr_str, dev, dev->name);
+	return dev;
+}
+EXPORT_SYMBOL(ecm_interface_dev_find_by_addr);
+
+#ifdef ECM_IPV6_ENABLE
+/*
+ * ecm_interface_mac_addr_get_ipv6()
+ *	Return mac for an IPv6 address
+ *
+ * GGG TODO Need to make sure this also works for local IP addresses too.
+ */
+static bool ecm_interface_mac_addr_get_ipv6(ip_addr_t addr, uint8_t *mac_addr, bool *on_link, ip_addr_t gw_addr)
+{
+	struct in6_addr daddr;
+	struct ecm_interface_route ecm_rt;
+	struct neighbour *neigh;
+	struct rt6_info *rt;
+	struct dst_entry *dst;
+
+	/*
+	 * Get the MAC address that corresponds to IP address given.
+	 * We look up the rt6_info entries and, from its neighbour structure, obtain the hardware address.
+	 * This means we will also work if the neighbours are routers too.
+	 */
+	ECM_IP_ADDR_TO_NIN6_ADDR(daddr, addr);
+	if (!ecm_interface_find_route_by_addr(addr, &ecm_rt)) {
+		*on_link = false;
+		return false;
+	}
+	DEBUG_ASSERT(!ecm_rt.v4_route, "Did not locate a v6 route!\n");
+
+	/*
+	 * Is this destination on link or off-link via a gateway?
+	 */
+	rt = ecm_rt.rt.rtv6;
+	if (!ECM_IP_ADDR_MATCH(rt->rt6i_dst.addr.in6_u.u6_addr32, rt->rt6i_gateway.in6_u.u6_addr32) || (rt->rt6i_flags & RTF_GATEWAY)) {
+		*on_link = false;
+		ECM_NIN6_ADDR_TO_IP_ADDR(gw_addr, rt->rt6i_gateway)
+	} else {
+		*on_link = true;
+	}
+
+	rcu_read_lock();
+	dst = ecm_rt.dst;
+
+	neigh = dst_neigh_lookup(dst, &daddr);
+	if (!neigh) {
+		neigh = neigh_lookup(&nd_tbl, &daddr, dst->dev);
+	}
+
+	if (!neigh) {
+		rcu_read_unlock();
+		ecm_interface_route_release(&ecm_rt);
+		DEBUG_WARN("No neigh reference\n");
+		return false;
+	}
+	if (!(neigh->nud_state & NUD_VALID)) {
+		rcu_read_unlock();
+		neigh_release(neigh);
+		ecm_interface_route_release(&ecm_rt);
+		DEBUG_WARN("NUD invalid\n");
+		return false;
+	}
+	if (!neigh->dev) {
+		rcu_read_unlock();
+		neigh_release(neigh);
+		ecm_interface_route_release(&ecm_rt);
+		DEBUG_WARN("Neigh dev invalid\n");
+		return false;
+	}
+
+	/*
+	 * If neigh->dev is a loopback then addr is a local address in which case we take the MAC from given device
+	 */
+	if (neigh->dev->flags & IFF_LOOPBACK) {
+		// GGG TODO Create an equivalent logic to that for ipv4, maybe need to create an ip6_dev_find()?
+		DEBUG_TRACE("local address " ECM_IP_ADDR_OCTAL_FMT " (found loopback)\n", ECM_IP_ADDR_TO_OCTAL(addr));
+		eth_zero_addr(mac_addr);
+	} else {
+		ether_addr_copy(mac_addr, neigh->ha);
+	}
+	rcu_read_unlock();
+	neigh_release(neigh);
+	ecm_interface_route_release(&ecm_rt);
+
+	DEBUG_TRACE(ECM_IP_ADDR_OCTAL_FMT " maps to %pM\n", ECM_IP_ADDR_TO_OCTAL(addr), mac_addr);
+	return true;
+}
+
+/*
+ * ecm_interface_find_gateway_ipv6()
+ *	Finds the ipv6 gateway ip address of a given ipv6 address.
+ */
+static bool ecm_interface_find_gateway_ipv6(ip_addr_t addr, ip_addr_t gw_addr)
+{
+	struct ecm_interface_route ecm_rt;
+	struct rt6_info *rt;
+
+	/*
+	 * Find the ipv6 route of the given ip address to look up
+	 * whether we have a gateway to reach to that ip address or not.
+	 */
+	if (!ecm_interface_find_route_by_addr(addr, &ecm_rt)) {
+		return false;
+	}
+	DEBUG_ASSERT(!ecm_rt.v4_route, "Did not locate a v6 route!\n");
+	DEBUG_TRACE("Found route\n");
+
+	/*
+	 * Is this destination reachable via a gateway?
+	 */
+	rt = ecm_rt.rt.rtv6;
+	if (ECM_IP_ADDR_MATCH(rt->rt6i_dst.addr.in6_u.u6_addr32, rt->rt6i_gateway.in6_u.u6_addr32) && !(rt->rt6i_flags & RTF_GATEWAY)) {
+		ecm_interface_route_release(&ecm_rt);
+		return false;
+	}
+
+	ECM_NIN6_ADDR_TO_IP_ADDR(gw_addr, rt->rt6i_gateway)
+	ecm_interface_route_release(&ecm_rt);
+	return true;
+}
+#endif
+
+/*
+ * ecm_interface_find_gateway_ipv4()
+ *	Finds the ipv4 gateway address of a given ipv4 address.
+ */
+static bool ecm_interface_find_gateway_ipv4(ip_addr_t addr, ip_addr_t gw_addr)
+{
+	struct ecm_interface_route ecm_rt;
+	struct rtable *rt;
+
+	/*
+	 * Find the ipv4 route of the given ip address to look up
+	 * whether we have a gateway to reach to that ip address or not.
+	 */
+	if (!ecm_interface_find_route_by_addr(addr, &ecm_rt)) {
+		return false;
+	}
+	DEBUG_ASSERT(ecm_rt.v4_route, "Did not locate a v4 route!\n");
+	DEBUG_TRACE("Found route\n");
+
+	/*
+	 * Is this destination reachable via a gateway?
+	 */
+	rt = ecm_rt.rt.rtv4;
+	if (!rt->rt_uses_gateway && !(rt->rt_flags & RTF_GATEWAY)) {
+		ecm_interface_route_release(&ecm_rt);
+		return false;
+	}
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0))
+	ECM_NIN4_ADDR_TO_IP_ADDR(gw_addr, rt->rt_gateway)
+#else
+	ECM_NIN4_ADDR_TO_IP_ADDR(gw_addr, rt->rt_gw4)
+#endif
+	ecm_interface_route_release(&ecm_rt);
+	return true;
+}
+
+/*
+ * ecm_interface_find_gateway()
+ *	Finds the gateway ip address of a given ECM ip address type.
+ */
+bool ecm_interface_find_gateway(ip_addr_t addr, ip_addr_t gw_addr)
+{
+	if (ECM_IP_ADDR_IS_V4(addr)) {
+		return ecm_interface_find_gateway_ipv4(addr, gw_addr);
+	}
+
+#ifdef ECM_IPV6_ENABLE
+	return ecm_interface_find_gateway_ipv6(addr, gw_addr);
+#else
+	return false;
+#endif
+}
+EXPORT_SYMBOL(ecm_interface_find_gateway);
+
+/*
+ * ecm_interface_mac_addr_get_ipv4()
+ *	Return mac for an IPv4 address
+ */
+static bool ecm_interface_mac_addr_get_ipv4(ip_addr_t addr, uint8_t *mac_addr, bool *on_link, ip_addr_t gw_addr)
+{
+	struct neighbour *neigh;
+	struct ecm_interface_route ecm_rt;
+	struct rtable *rt;
+	struct dst_entry *dst;
+	__be32 ipv4_addr;
+
+	/*
+	 * Get the MAC address that corresponds to IP address given.
+	 * We look up the rtable entries and, from its neighbour structure, obtain the hardware address.
+	 * This means we will also work if the neighbours are routers too.
+	 * We also locate the MAC if the address is a local host address.
+	 */
+	ECM_IP_ADDR_TO_NIN4_ADDR(ipv4_addr, addr);
+	if (!ecm_interface_find_route_by_addr(addr, &ecm_rt)) {
+		*on_link = false;
+		return false;
+	}
+	DEBUG_ASSERT(ecm_rt.v4_route, "Did not locate a v4 route!\n");
+	DEBUG_TRACE("Found route\n");
+
+	/*
+	 * Is this destination on link or off-link via a gateway?
+	 */
+	rt = ecm_rt.rt.rtv4;
+	if (rt->rt_uses_gateway || (rt->rt_flags & RTF_GATEWAY)) {
+		*on_link = false;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0))
+		ECM_NIN4_ADDR_TO_IP_ADDR(gw_addr, rt->rt_gateway)
+#else
+		ECM_NIN4_ADDR_TO_IP_ADDR(gw_addr, rt->rt_gw4)
+#endif
+	} else {
+		*on_link = true;
+	}
+
+	/*
+	 * Get the neighbour entry for the address
+	 */
+	rcu_read_lock();
+	dst = ecm_rt.dst;
+
+	neigh = dst_neigh_lookup(dst, &ipv4_addr);
+	if (!neigh) {
+		neigh = neigh_lookup(&arp_tbl, &ipv4_addr, dst->dev);
+	}
+	if (!neigh) {
+		rcu_read_unlock();
+		ecm_interface_route_release(&ecm_rt);
+		DEBUG_WARN("no neigh\n");
+		return false;
+	}
+	if (!(neigh->nud_state & NUD_VALID)) {
+		rcu_read_unlock();
+		neigh_release(neigh);
+		ecm_interface_route_release(&ecm_rt);
+		DEBUG_WARN("neigh nud state is not valid\n");
+		return false;
+	}
+	if (!neigh->dev) {
+		rcu_read_unlock();
+		neigh_release(neigh);
+		ecm_interface_route_release(&ecm_rt);
+		DEBUG_WARN("neigh has no device\n");
+		return false;
+	}
+
+	/*
+	 * If the device is loopback this will be because the address is a local address
+	 * In this case locate the device that has this local address and get its mac.
+	 */
+	if (neigh->dev->type == ARPHRD_LOOPBACK) {
+		struct net_device *dev;
+
+		DEBUG_TRACE("%pI4 finds loopback device, dev: %px (%s)\n", &ipv4_addr, neigh->dev, neigh->dev->name);
+		rcu_read_unlock();
+		neigh_release(neigh);
+		ecm_interface_route_release(&ecm_rt);
+
+		/*
+		 * Lookup the device that has this IP address assigned
+		 */
+		dev = ip_dev_find(&init_net, ipv4_addr);
+		if (!dev) {
+			DEBUG_WARN("Unable to locate dev for: %pI4\n", &ipv4_addr);
+			return false;
+		}
+		memcpy(mac_addr, dev->dev_addr, (size_t)dev->addr_len);
+		DEBUG_TRACE("is local addr: %pI4, mac: %pM, dev ifindex: %d, dev: %px (%s), dev_type: %d\n",
+				&ipv4_addr, mac_addr, dev->ifindex, dev, dev->name, dev->type);
+		dev_put(dev);
+		return true;
+	}
+
+	if (!(neigh->dev->flags & IFF_NOARP)) {
+		ether_addr_copy(mac_addr, neigh->ha);
+	} else {
+		DEBUG_TRACE("non-arp device: %px (%s, type: %d) to reach %pI4\n", neigh->dev, neigh->dev->name, neigh->dev->type, &ipv4_addr);
+		eth_zero_addr(mac_addr);
+	}
+	DEBUG_TRACE("addr: %pI4, mac: %pM, iif: %d, neigh dev ifindex: %d, dev: %px (%s), dev_type: %d\n",
+			&ipv4_addr, mac_addr, rt->rt_iif, neigh->dev->ifindex, neigh->dev, neigh->dev->name, neigh->dev->type);
+
+	rcu_read_unlock();
+	neigh_release(neigh);
+	ecm_interface_route_release(&ecm_rt);
+	return true;
+}
+
+/*
+ * ecm_interface_mac_addr_get()
+ *	Return the mac address for the given IP address.  Returns false on failure.
+ */
+bool ecm_interface_mac_addr_get(ip_addr_t addr, uint8_t *mac_addr, bool *on_link, ip_addr_t gw_addr)
+{
+	if (ECM_IP_ADDR_IS_V4(addr)) {
+		return ecm_interface_mac_addr_get_ipv4(addr, mac_addr, on_link, gw_addr);
+	}
+
+#ifdef ECM_IPV6_ENABLE
+	return ecm_interface_mac_addr_get_ipv6(addr, mac_addr, on_link, gw_addr);
+#else
+	return false;
+#endif
+}
+EXPORT_SYMBOL(ecm_interface_mac_addr_get);
+
+#ifdef ECM_IPV6_ENABLE
+/*
+ * ecm_interface_mac_addr_get_ipv6_no_route()
+ *	Finds the mac address of a node from its ip address reachable via
+ * the given device. It looks up the mac address in the neighbour entries.
+ * It doesn't do any route lookup to find the dst entry.
+ */
+static bool ecm_interface_mac_addr_get_ipv6_no_route(struct net_device *dev, ip_addr_t addr, uint8_t *mac_addr)
+{
+	struct in6_addr daddr;
+	struct neighbour *neigh;
+	struct net_device *local_dev;
+
+	memset(mac_addr, 0, ETH_ALEN);
+
+	/*
+	 * Get the MAC address that corresponds to IP address given.
+	 */
+	ECM_IP_ADDR_TO_NIN6_ADDR(daddr, addr);
+	local_dev = ipv6_dev_find(&init_net, &daddr, 1);
+	if (local_dev) {
+		DEBUG_TRACE("%pi6 is a local address\n", &daddr);
+		memcpy(mac_addr, dev->dev_addr, ETH_ALEN);
+		dev_put(local_dev);
+		return true;
+	}
+
+	rcu_read_lock();
+	neigh = neigh_lookup(&nd_tbl, &daddr, dev);
+	if (!neigh) {
+		rcu_read_unlock();
+		DEBUG_WARN("No neigh reference\n");
+		return false;
+	}
+	if (!(neigh->nud_state & NUD_VALID)) {
+		neigh_release(neigh);
+		rcu_read_unlock();
+		DEBUG_WARN("NUD invalid\n");
+		return false;
+	}
+	if (!neigh->dev) {
+		neigh_release(neigh);
+		rcu_read_unlock();
+		DEBUG_WARN("Neigh dev invalid\n");
+		return false;
+	}
+
+	if (neigh->dev->flags & IFF_NOARP) {
+		neigh_release(neigh);
+		rcu_read_unlock();
+		DEBUG_TRACE("dest MAC is zero: %pM\n", mac_addr);
+		return true;
+	}
+
+	memcpy(mac_addr, neigh->ha, (size_t)neigh->dev->addr_len);
+	neigh_release(neigh);
+	rcu_read_unlock();
+	DEBUG_TRACE(ECM_IP_ADDR_OCTAL_FMT " maps to %pM\n", ECM_IP_ADDR_TO_OCTAL(addr), mac_addr);
+	return true;
+}
+#endif
+
+/*
+ * ecm_interface_mac_addr_get_ipv4_no_route()
+ *	Finds the mac address of a node from its ip address reachable via
+ * the given device. It looks up the mac address in the neighbour entries.
+ * It doesn't do any route lookup to find the dst entry.
+ */
+static bool ecm_interface_mac_addr_get_ipv4_no_route(struct net_device *dev, ip_addr_t ip_addr, uint8_t *mac_addr)
+{
+	struct neighbour *neigh;
+	__be32 be_addr;
+	struct net_device *local_dev;
+
+	memset(mac_addr, 0, ETH_ALEN);
+
+	ECM_IP_ADDR_TO_NIN4_ADDR(be_addr, ip_addr);
+	local_dev = ip_dev_find(&init_net, be_addr);
+	if (local_dev) {
+		DEBUG_TRACE("%pI4n is a local address\n", &be_addr);
+		memcpy(mac_addr, dev->dev_addr, ETH_ALEN);
+		dev_put(local_dev);
+		return true;
+	}
+
+	rcu_read_lock();
+	neigh = neigh_lookup(&arp_tbl, &be_addr, dev);
+	if (!neigh) {
+		rcu_read_unlock();
+		DEBUG_WARN("no neigh\n");
+		return false;
+	}
+	if (!(neigh->nud_state & NUD_VALID)) {
+		neigh_release(neigh);
+		rcu_read_unlock();
+		DEBUG_WARN("neigh nud state is not valid\n");
+		return false;
+	}
+	if (!neigh->dev) {
+		neigh_release(neigh);
+		rcu_read_unlock();
+		DEBUG_WARN("neigh has no device\n");
+		return false;
+	}
+
+	if (neigh->dev->flags & IFF_NOARP) {
+		neigh_release(neigh);
+		rcu_read_unlock();
+		DEBUG_TRACE("dest MAC is zero: %pM\n", mac_addr);
+		return true;
+	}
+
+	memcpy(mac_addr, neigh->ha, (size_t)neigh->dev->addr_len);
+	neigh_release(neigh);
+	rcu_read_unlock();
+	DEBUG_TRACE("dest MAC: %pM\n", mac_addr);
+	return true;
+
+}
+
+/*
+ * ecm_interface_mac_addr_get_no_route()
+ *	Return the mac address for the given IP address reacahble via the given device.
+ * Return false on failure, true on success.
+ */
+bool ecm_interface_mac_addr_get_no_route(struct net_device *dev, ip_addr_t addr, uint8_t *mac_addr)
+{
+	if (ECM_IP_ADDR_IS_V4(addr)) {
+		return ecm_interface_mac_addr_get_ipv4_no_route(dev, addr, mac_addr);
+	}
+
+#ifdef ECM_IPV6_ENABLE
+	return ecm_interface_mac_addr_get_ipv6_no_route(dev, addr, mac_addr);
+#else
+	return false;
+#endif
+}
+EXPORT_SYMBOL(ecm_interface_mac_addr_get_no_route);
+
+#ifdef ECM_MULTICAST_ENABLE
+
+/*
+ * ecm_interface_multicast_dest_list_find_if()
+ * 	Searches for a given device in a list of interface indices
+ *
+ * 	dev		Pointer to the net device to search for
+ * 	max_if		Number of valid interfaces in the destination interface list
+ * 	dest_if_list	The destination interface list
+ */
+static bool ecm_interface_multicast_dest_list_find_if(struct net_device *dev, uint8_t max_if, uint32_t *dest_if_list)
+{
+	struct net_device *dest_dev = NULL;
+	uint32_t *dst_if_index;
+	int index;
+
+	for (index = 0; index < max_if; index++) {
+		dst_if_index = ecm_db_multicast_if_first_get_at_index(dest_if_list, index);
+		dest_dev = dev_get_by_index(&init_net, *dst_if_index);
+		if (!dest_dev) {
+			DEBUG_WARN("Found invalid if_index %d at index %d\n", *dst_if_index, index);
+			continue;
+		}
+
+		if (dest_dev == dev) {
+			dev_put(dest_dev);
+			return true;
+		}
+
+		dev_put(dest_dev);
+	}
+
+	return false;
+}
+
+/*
+ * ecm_interface_multicast_check_for_br_dev()
+ * 	Find a bridge dev is present or not in an
+ * 	array of Ifindexs
+ */
+bool ecm_interface_multicast_check_for_br_dev(uint32_t dest_if[], uint8_t max_if)
+{
+	struct net_device *br_dev;
+	int i;
+
+	for (i = 0; i < max_if; i++) {
+		br_dev = dev_get_by_index(&init_net, dest_if[i]);
+		if (!br_dev) {
+			/*
+			 * Interface got deleted; but is yet to be updated in MFC table
+			 */
+			DEBUG_WARN("Could not find a valid netdev here\n");
+			continue;
+		}
+
+		if (ecm_front_end_is_bridge_device(br_dev)
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			|| ecm_front_end_is_ovs_bridge_device(br_dev)
+#endif
+				) {
+			dev_put(br_dev);
+			return true;
+		}
+		dev_put(br_dev);
+	}
+	return false;
+}
+EXPORT_SYMBOL(ecm_interface_multicast_check_for_br_dev);
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+/*
+ * ecm_interface_multicast_check_for_ovs_br_dev()
+ * 	Check if OVS bridge dev exists in given list of interfaces.
+ */
+bool ecm_interface_multicast_check_for_ovs_br_dev(uint32_t dest_if[], uint8_t max_if)
+{
+	int i;
+
+	for (i = 0; i < max_if; i++) {
+		struct net_device *br_dev;
+
+		br_dev = dev_get_by_index(&init_net, dest_if[i]);
+		if (!br_dev) {
+			/*
+			 * Interface got deleted; but is yet to be updated in MFC table
+			 */
+			DEBUG_WARN("Could not find a valid netdev for interface: %d\n", dest_if[i]);
+			continue;
+		}
+
+		if (ecm_front_end_is_ovs_bridge_device(br_dev)) {
+			dev_put(br_dev);
+			return true;
+		}
+		dev_put(br_dev);
+	}
+	return false;
+}
+#endif
+
+/*
+ * ecm_interface_multicast_is_iface_type()
+ *	Checks if interface of type exist in mc_if_index
+ */
+bool ecm_interface_multicast_is_iface_type(int32_t mc_if_index[], int32_t max_if_index, unsigned short type)
+{
+	int32_t i;
+	struct net_device *dev;
+
+	for (i = 0; i < max_if_index; i++) {
+
+		if (!mc_if_index[i]) {
+			break;
+		}
+
+		dev = dev_get_by_index(&init_net, mc_if_index[i]);
+		if (!dev) {
+			DEBUG_WARN("Could not find a valid interface with index = %d\n", mc_if_index[i]);
+			continue;
+		}
+
+		if (dev->type == type) {
+			DEBUG_TRACE("Interface dev = %s of type %u\n", dev->name,  type);
+			dev_put(dev);
+			return true;
+		}
+
+		dev_put(dev);
+	}
+
+	return false;
+}
+
+/*
+ * ecm_interface_multicast_filter_src_interface()
+ * 	Filter the source interface from the list.
+ */
+int32_t ecm_interface_multicast_filter_src_interface(struct ecm_db_connection_instance *ci, uint32_t *mc_dst_if_index)
+{
+	struct ecm_db_iface_instance *ii;
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	ecm_db_iface_type_t ii_type;
+	int32_t from_ifaces_first;
+	int32_t from_iface_identifier;
+	int32_t if_index = ECM_DB_IFACE_HEIRARCHY_MAX;
+
+	/*
+	 * Get the interface lists of the connection, we must have at least one interface in the list to continue
+	 */
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		return if_index;
+	}
+
+	ii = from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1];
+	ii_type = ecm_db_iface_type_get(ii);
+	if ((ii_type == ECM_DB_IFACE_TYPE_BRIDGE) || (ii_type == ECM_DB_IFACE_TYPE_OVS_BRIDGE)) {
+		ii = from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 2];
+	}
+
+	from_iface_identifier = ecm_db_iface_interface_identifier_get(ii);
+	if_index = ecm_interface_multicast_check_for_src_ifindex(mc_dst_if_index, ECM_DB_IFACE_HEIRARCHY_MAX, from_iface_identifier);
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+	return if_index;
+}
+
+/*
+ * ecm_interface_multicast_check_for_src_if_index()
+ * 	Find if a source netdev ifindex is matching with list of
+ * 	multicast destination netdev ifindex. If find a match then
+ *	returns a new list of destination netdev ifindex excluding
+ *	the ifindex of source netdev.
+ */
+int32_t ecm_interface_multicast_check_for_src_ifindex(int32_t mc_if_index[], int32_t max_if_index, int32_t if_num)
+{
+	int32_t i;
+	int32_t valid_index;
+
+	for (i = 0, valid_index = 0; i < max_if_index; i++) {
+		if (mc_if_index[i] == 0) {
+			break;
+		}
+
+		if (mc_if_index[i] != if_num) {
+			mc_if_index[valid_index] = mc_if_index[i];
+			valid_index++;
+			continue;
+		}
+	}
+
+	return valid_index;
+}
+EXPORT_SYMBOL(ecm_interface_multicast_check_for_src_ifindex);
+#endif
+
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+/*
+ * ecm_interface_vxlan_type_get()
+ *	Function to get VxLAN interface type i.e. inner/outer.
+ *	Returns 0 for outer and 1 for inner.
+ */
+uint32_t ecm_interface_vxlan_type_get(struct sk_buff *skb)
+{
+	ip_addr_t saddr;
+	struct net_device *local_dev;
+
+	if (!skb) {
+		return -1;
+	}
+
+	switch (ntohs(skb->protocol)) {
+	case ETH_P_IP:
+		ECM_NIN4_ADDR_TO_IP_ADDR(saddr, ip_hdr(skb)->saddr);
+		break;
+	case ETH_P_IPV6:
+		ECM_NIN6_ADDR_TO_IP_ADDR(saddr, ipv6_hdr(skb)->saddr);
+		break;
+	default:
+		DEBUG_WARN("%px: Unknown skb protocol.\n", skb);
+		return -1;
+	}
+
+	local_dev = ecm_interface_dev_find_by_local_addr(saddr);
+	if (local_dev) {
+		dev_put(local_dev);
+		DEBUG_TRACE("%px: VxLAN outer interface type.\n", skb);
+		return 0;
+	}
+	DEBUG_TRACE("%px: VxLAN inner interface type.\n", skb);
+	return 1;
+}
+#endif
+
+/*
+ * ecm_interface_addr_find_route_by_addr_ipv4()
+ *	Return the route for the given IP address.  Returns NULL on failure.
+ */
+static bool ecm_interface_find_route_by_addr_ipv4(ip_addr_t addr, struct ecm_interface_route *ecm_rt)
+{
+	__be32 be_addr;
+
+	/*
+	 * Get a route to the given IP address, this will allow us to also find the interface
+	 * it is using to communicate with that IP address.
+	 */
+	ECM_IP_ADDR_TO_NIN4_ADDR(be_addr, addr);
+	ecm_rt->rt.rtv4 = ip_route_output(&init_net, be_addr, 0, 0, 0);
+	if (IS_ERR(ecm_rt->rt.rtv4)) {
+		DEBUG_TRACE("No output route to: %pI4n\n", &be_addr);
+		return false;
+	}
+	DEBUG_TRACE("Output route to: %pI4n is: %px\n", &be_addr, ecm_rt->rt.rtv4);
+	ecm_rt->dst = (struct dst_entry *)ecm_rt->rt.rtv4;
+	ecm_rt->v4_route = true;
+	return true;
+}
+
+#ifdef ECM_IPV6_ENABLE
+struct rt6_info *ecm_interface_ipv6_route_lookup(struct net *netf, struct in6_addr *addr)
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0))
+	return rt6_lookup(netf, addr, NULL, 0, 0);
+#else
+	return rt6_lookup(netf, addr, NULL, 0, NULL, 0);
+#endif
+}
+
+/*
+ * ecm_interface_addr_find_route_by_addr_ipv6()
+ *	Return the route for the given IP address.  Returns NULL on failure.
+ */
+static bool ecm_interface_find_route_by_addr_ipv6(ip_addr_t addr, struct ecm_interface_route *ecm_rt)
+{
+	struct in6_addr naddr;
+
+	ECM_IP_ADDR_TO_NIN6_ADDR(naddr, addr);
+
+	/*
+	 * Get a route to the given IP address, this will allow us to also find the interface
+	 * it is using to communicate with that IP address.
+	 */
+	ecm_rt->rt.rtv6 = ecm_interface_ipv6_route_lookup(&init_net, &naddr);
+	if (!ecm_rt->rt.rtv6) {
+		DEBUG_TRACE("No output route to: " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr));
+		return NULL;
+	}
+	DEBUG_TRACE("Output route to: " ECM_IP_ADDR_OCTAL_FMT " is: %px\n", ECM_IP_ADDR_TO_OCTAL(addr), ecm_rt->rt.rtv6);
+	ecm_rt->dst = (struct dst_entry *)ecm_rt->rt.rtv6;
+	ecm_rt->v4_route = false;
+	return true;
+}
+#endif
+
+/*
+ * ecm_interface_addr_find_route_by_addr()
+ *	Return the route (in the given parameter) for the given IP address.  Returns false on failure.
+ *
+ * Route is the device on which the addr is reachable, which may be loopback for local addresses.
+ *
+ * Returns true if the route was able to be located.  The route must be released using ecm_interface_route_release().
+ */
+bool ecm_interface_find_route_by_addr(ip_addr_t addr, struct ecm_interface_route *ecm_rt)
+{
+	char __attribute__((unused)) addr_str[40];
+
+	DEBUG_ECM_IP_ADDR_TO_STRING(addr_str, addr);
+	DEBUG_TRACE("Locate route to: %s\n", addr_str);
+
+	if (ECM_IP_ADDR_IS_V4(addr)) {
+		return ecm_interface_find_route_by_addr_ipv4(addr, ecm_rt);
+	}
+
+#ifdef ECM_IPV6_ENABLE
+	return ecm_interface_find_route_by_addr_ipv6(addr, ecm_rt);
+#else
+	return false;
+#endif
+}
+EXPORT_SYMBOL(ecm_interface_find_route_by_addr);
+
+/*
+ * ecm_interface_route_release()
+ *	Release an ecm route
+ */
+void ecm_interface_route_release(struct ecm_interface_route *rt)
+{
+	dst_release(rt->dst);
+}
+EXPORT_SYMBOL(ecm_interface_route_release);
+
+#ifdef ECM_IPV6_ENABLE
+/*
+ * ecm_interface_send_neighbour_solicitation()
+ *	Issue an IPv6 Neighbour soliciation request.
+ */
+void ecm_interface_send_neighbour_solicitation(struct net_device *dev, ip_addr_t addr)
+{
+	struct in6_addr dst_addr, src_addr;
+	struct in6_addr mc_dst_addr;
+	struct rt6_info *rt6i;
+	struct neighbour *neigh;
+	struct net *netf = dev_net(dev);
+	int ret;
+
+	/*
+	 * Find source and destination addresses in Linux format. We need
+	 * mcast destination address as well.
+	 */
+	ECM_IP_ADDR_TO_NIN6_ADDR(dst_addr, addr);
+	addrconf_addr_solict_mult(&dst_addr, &mc_dst_addr);
+	ret = ipv6_dev_get_saddr(netf, dev, &mc_dst_addr, 0, &src_addr);
+
+	/*
+	 * Find the route entry
+	 */
+	rt6i = ecm_interface_ipv6_route_lookup(netf, &dst_addr);
+	if (!rt6i) {
+		DEBUG_TRACE("IPv6 Route lookup failure for destination IPv6 address " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr));
+		return;
+	}
+
+	/*
+	 * Find the neighbor entry
+	 */
+	neigh = rt6i->dst.ops->neigh_lookup(&rt6i->dst, NULL, &dst_addr);
+	if (IS_ERR(neigh)) {
+		DEBUG_TRACE("Neighbour lookup failure for destination IPv6 address " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr));
+		dst_release(&rt6i->dst);
+		return;
+	}
+
+	/*
+	 * Issue a Neighbour soliciation request
+	 */
+	DEBUG_TRACE("Issue Neighbour solicitation request\n");
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0))
+	ndisc_send_ns(dev, &dst_addr, &mc_dst_addr, &src_addr);
+#else
+	ndisc_send_ns(dev, &dst_addr, &mc_dst_addr, &src_addr, 0);
+#endif
+	neigh_release(neigh);
+	dst_release(&rt6i->dst);
+}
+EXPORT_SYMBOL(ecm_interface_send_neighbour_solicitation);
+#endif
+
+/*
+ * ecm_interface_send_arp_request()
+ *	Issue and ARP request.
+ */
+void ecm_interface_send_arp_request(struct net_device *dest_dev, ip_addr_t dest_addr, bool on_link, ip_addr_t gw_addr)
+{
+	/*
+	 * Possible ARP does not know the address yet
+	 */
+	struct neighbour *neigh;
+	__be32 ipv4_addr;
+
+	/*
+	 * Convert the ECM IP address type to network order IPv4 address.
+	 */
+	ECM_IP_ADDR_TO_NIN4_ADDR(ipv4_addr, dest_addr);
+
+	/*
+	 * If we have a GW for this address, then we have to send ARP request to the GW
+	 */
+	if (!on_link && !ECM_IP_ADDR_IS_NULL(gw_addr)) {
+		ECM_IP_ADDR_TO_NIN4_ADDR(ipv4_addr, gw_addr);
+	}
+
+	/*
+	 * If we don't have this neighbor, create it before sending the arp request,
+	 * so that when we receive the arp reply we update the neigh entry.
+	 */
+	neigh = neigh_lookup(&arp_tbl, &ipv4_addr, dest_dev);
+	if (!neigh) {
+		neigh = neigh_create(&arp_tbl, &ipv4_addr, dest_dev);
+		if (IS_ERR(neigh)) {
+			DEBUG_WARN("Unable to create ARP request neigh for %pI4\n", &ipv4_addr);
+			return;
+		}
+	}
+
+	DEBUG_TRACE("Send ARP for %pI4\n", &ipv4_addr);
+	neigh_event_send(neigh, NULL);
+	neigh_release(neigh);
+}
+EXPORT_SYMBOL(ecm_interface_send_arp_request);
+
+/*
+ * ecm_interface_ipv4_neigh_get()
+ * 	Returns neighbour reference for a given IP address which must be released when you are done with it.
+ *
+ * Returns NULL on fail.
+ */
+struct neighbour *ecm_interface_ipv4_neigh_get(ip_addr_t addr)
+{
+	struct neighbour *neigh;
+	struct rtable *rt;
+	struct dst_entry *dst;
+	__be32 ipv4_addr;
+
+	ECM_IP_ADDR_TO_NIN4_ADDR(ipv4_addr, addr);
+	rt = ip_route_output(&init_net, ipv4_addr, 0, 0, 0);
+	if (IS_ERR(rt)) {
+		return NULL;
+	}
+	dst = (struct dst_entry *)rt;
+	neigh = dst_neigh_lookup(dst, &ipv4_addr);
+	ip_rt_put(rt);
+	return neigh;
+}
+
+#ifdef ECM_IPV6_ENABLE
+/*
+ * ecm_interface_ipv6_neigh_get()
+ * 	Returns neighbour reference for a given IP address which must be released when you are done with it.
+ *
+ * Returns NULL on fail.
+ */
+struct neighbour *ecm_interface_ipv6_neigh_get(ip_addr_t addr)
+{
+	struct neighbour *neigh;
+	struct rt6_info *rt;
+	struct dst_entry *dst;
+	struct in6_addr ipv6_addr;
+
+	ECM_IP_ADDR_TO_NIN6_ADDR(ipv6_addr, addr);
+
+	rt = ecm_interface_ipv6_route_lookup(&init_net, &ipv6_addr);
+	if (!rt) {
+		return NULL;
+	}
+	dst = (struct dst_entry *)rt;
+	neigh = dst_neigh_lookup(dst, &ipv6_addr);
+	dst_release(dst);
+	return neigh;
+}
+#endif
+
+/*
+ * ecm_interface_is_pptp()
+ *	skip pptp tunnel encapsulated traffic
+ *
+ * ECM does not handle PPTP,
+ * this function detects packets of that type so they can be skipped over to improve their throughput.
+ */
+bool ecm_interface_is_pptp(struct sk_buff *skb, const struct net_device *out)
+{
+	struct net_device *in;
+
+	/*
+	 * skip first pass of l2tp/pptp tunnel encapsulated traffic
+	 */
+	if (out->type == ARPHRD_PPP) {
+		if (out->priv_flags_ext & IFF_EXT_PPP_PPTP) {
+			return true;
+		}
+	}
+
+	in = dev_get_by_index(&init_net, skb->skb_iif);
+	if (!in) {
+		return true;
+	}
+
+	if (in->type == ARPHRD_PPP) {
+		if (in->priv_flags_ext & IFF_EXT_PPP_PPTP) {
+			dev_put(in);
+			return true;
+		}
+	}
+
+	dev_put(in);
+	return false;
+}
+
+/*
+ * ecm_interface_is_l2tp_packet_by_version()
+ *	Check version of l2tp tunnel encapsulated traffic
+ *
+ * ECM does not handle l2tp,
+ * this function detects packets of that type so they can be skipped over to improve their throughput.
+ */
+bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct net_device *out, int ver)
+{
+	uint32_t flag = 0;
+	struct net_device *in;
+
+	switch (ver) {
+	case 2:
+		flag = IFF_EXT_PPP_L2TPV2;
+		break;
+	case 3:
+		flag = IFF_EXT_PPP_L2TPV3;
+		break;
+	default:
+		break;
+	}
+
+	/*
+	 * skip first pass of l2tp/pptp tunnel encapsulated traffic
+	 */
+	if (out->priv_flags_ext & flag) {
+		return true;
+	}
+
+	in = dev_get_by_index(&init_net, skb->skb_iif);
+	if (!in) {
+		return true;
+	}
+
+	if (in->priv_flags_ext & flag) {
+		dev_put(in);
+		return true;
+	}
+
+	dev_put(in);
+	return false;
+}
+
+/*
+ * ecm_interface_is_l2tp_pptp()
+ *	skip l2tp/pptp tunnel encapsulated traffic
+ *
+ * ECM does not handle L2TP or PPTP encapsulated packets,
+ * this function detects packets of that type so they can be skipped over to improve their throughput.
+ */
+bool ecm_interface_is_l2tp_pptp(struct sk_buff *skb, const struct net_device *out)
+{
+	struct net_device *in;
+
+	/*
+	 * skip first pass of l2tp/pptp tunnel encapsulated traffic
+	 */
+	if (out->priv_flags_ext & (IFF_EXT_PPP_L2TPV2 | IFF_EXT_PPP_L2TPV3 |
+			       IFF_EXT_PPP_PPTP)) {
+		return true;
+	}
+
+	in = dev_get_by_index(&init_net, skb->skb_iif);
+	if (!in) {
+		return true;
+	}
+
+	if (in->priv_flags_ext & (IFF_EXT_PPP_L2TPV2 | IFF_EXT_PPP_L2TPV3 |
+			      IFF_EXT_PPP_PPTP)) {
+		dev_put(in);
+		return true;
+	}
+
+	dev_put(in);
+	return false;
+}
+
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+/*
+ * ecm_interface_vlan_interface_establish()
+ *	Returns a reference to a iface of the VLAN type, possibly creating one if necessary.
+ * Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_vlan_interface_establish(struct ecm_db_interface_info_vlan *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish VLAN iface: %s with address: %pM, vlan tag: %u, vlan_tpid: %x MTU: %d, if num: %d, accel engine if id: %d\n",
+			dev_name, type_info->address, type_info->vlan_tag, type_info->vlan_tpid, mtu, dev_interface_num, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_vlan(type_info->address, type_info->vlan_tag, type_info->vlan_tpid);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_vlan(type_info->address, type_info->vlan_tag, type_info->vlan_tpid);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+	ecm_db_iface_add_vlan(nii, type_info->address, type_info->vlan_tag, type_info->vlan_tpid, dev_name,
+			mtu, dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: vlan iface established\n", nii);
+	return nii;
+}
+#endif
+
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+/*
+ * ecm_interface_macvlan_interface_establish()
+ *	Returns a reference to a iface of the MACVLAN type, possibly creating one if necessary.
+ * Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_macvlan_interface_establish(struct ecm_db_interface_info_macvlan *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish MACVLAN iface: %s with address: %pM, MTU: %d, if num: %d, accel engine if id: %d\n",
+			dev_name, type_info->address, mtu, dev_interface_num, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_macvlan(type_info->address);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_macvlan(type_info->address);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+	ecm_db_iface_add_macvlan(nii, type_info->address, dev_name,
+			mtu, dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: MACVLAN iface established\n", nii);
+	return nii;
+}
+#endif
+
+#if defined(ECM_INTERFACE_OVS_BRIDGE_ENABLE) && defined(ECM_MULTICAST_ENABLE)
+/*
+ * ecm_interface_multicast_ovs_to_interface_get_and_ref()
+ *	Populate ov_ ports/bridge device from multicast 'to' list.
+ *	Returns the number of ovs port count.
+ */
+int ecm_interface_multicast_ovs_to_interface_get_and_ref(struct ecm_db_connection_instance *ci, struct net_device **to_ovs_port,
+							struct net_device **to_ovs_brdev)
+{
+	struct net_device *dev;
+	struct ecm_db_iface_instance *to_mc_ifaces;
+	int32_t *to_mc_ifaces_first, *to_iface_first, if_cnt, i;
+	int ovs_port_cnt = 0;
+
+	if_cnt = ecm_db_multicast_connection_to_interfaces_get_and_ref_all(ci, &to_mc_ifaces, &to_mc_ifaces_first);
+	if (!if_cnt) {
+		DEBUG_WARN("%px: Not able to find 'to' interfaces", ci);
+		return 0;
+	}
+
+	/*
+	 * The 'to' interfaces ports can be part of different OVS bridges.
+	 * ovs-br1-(eth0, eth1, eth2)
+	 * ovs-br2-(eth3)
+	 * ovs-br3 (eth4, eth5)
+	 *
+	 * to_ovs_port: eth0, eth1, eth2, eth3. eth4. eth5
+	 * to_ovs_brdev: ovs-br1, ovs-br1, ovs-br1, ovs-br2, ovs-br3, ovs-br3
+	 */
+	for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+		struct ecm_db_iface_instance *ii_temp;
+		int32_t j;
+
+		/*
+		 * Find interface list, skip if invalid.
+		 */
+		to_iface_first = ecm_db_multicast_if_first_get_at_index(to_mc_ifaces_first, i);
+		if (*to_iface_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			continue;
+		}
+
+		/*
+		 * We need to find 'to' multicast port to
+		 * update the OVS statistics.
+		 */
+		ii_temp = ecm_db_multicast_if_heirarchy_get(to_mc_ifaces, i);
+		for (j = ECM_DB_IFACE_HEIRARCHY_MAX - 1; j >= *to_iface_first; j--) {
+			struct net_device *br_dev;
+			struct ecm_db_iface_instance **ifaces;
+			struct ecm_db_iface_instance *to_iface;
+			struct ecm_db_iface_instance *ii_single;
+
+			ii_single = ecm_db_multicast_if_instance_get_at_index(ii_temp, j);
+			ifaces = (struct ecm_db_iface_instance **)ii_single;
+			to_iface = *ifaces;
+			dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(to_iface));
+			if (unlikely(!dev)) {
+				DEBUG_WARN("%px: Failed to get net device with %d index\n", ci, j);
+				continue;
+			}
+
+			if (!ecm_interface_is_ovs_bridge_port(dev)) {
+				DEBUG_TRACE("%px: %s_dev: %s at %d index is not an OVS bridge port\n", ci, ecm_db_obj_dir_strings[ECM_DB_OBJ_DIR_TO], dev->name, j);
+				dev_put(dev);
+				continue;
+			}
+
+			br_dev = ovsmgr_dev_get_master(dev);
+			DEBUG_ASSERT(br_dev, "%px: master dev for the OVS port:%s is NULL\n", ci, dev->name);
+			to_ovs_port[ovs_port_cnt] = dev;
+			to_ovs_brdev[ovs_port_cnt] = br_dev;
+			DEBUG_TRACE("%px: %s_dev: %s at %d index is an OVS bridge port. OVS bridge: %s\n", ci, ecm_db_obj_dir_strings[ECM_DB_OBJ_DIR_TO], dev->name, j, br_dev->name);
+			ovs_port_cnt++;
+			break;
+		}
+	}
+
+	ecm_db_multicast_connection_to_interfaces_deref_all(to_mc_ifaces, to_mc_ifaces_first);
+	return ovs_port_cnt;
+}
+#endif
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+/*
+ * ecm_interface_is_ovs_bridge_port()
+ *	Returns true if dev is OpenVswitch (OVS) bridge port.
+ */
+bool ecm_interface_is_ovs_bridge_port(const struct net_device *dev)
+{
+	/*
+	 * Check if dev is OVS bridge port.
+	 */
+	return !!(dev->priv_flags & IFF_OVS_DATAPATH);
+}
+#endif
+
+/*
+ * ecm_interface_bridge_interface_establish()
+ *	Returns a reference to a iface of the BRIDGE type, possibly creating one if necessary.
+ * Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_bridge_interface_establish(struct ecm_db_interface_info_bridge *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish BRIDGE iface: %s with address: %pM, MTU: %d, if num: %d, accel engine if id: %d\n",
+			dev_name, type_info->address, mtu, dev_interface_num, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_bridge(type_info->address, dev_interface_num);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_bridge(type_info->address, dev_interface_num);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+	ecm_db_iface_add_bridge(nii, type_info->address, dev_name,
+			mtu, dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: bridge iface established\n", nii);
+	return nii;
+}
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+/*
+ * ecm_interface_ovs_bridge_interface_establish()
+ *	Returns a reference to a iface of the OVS BRIDGE type, possibly creating one if necessary.
+ * Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_ovs_bridge_interface_establish(struct ecm_db_interface_info_ovs_bridge *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish OVS BRIDGE iface: %s with address: %pM, MTU: %d, if num: %d, accel engine if id: %d\n",
+			dev_name, type_info->address, mtu, dev_interface_num, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_ovs_bridge(type_info->address, dev_interface_num);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_ovs_bridge(type_info->address, dev_interface_num);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+	ecm_db_iface_add_ovs_bridge(nii, type_info->address, dev_name,
+			mtu, dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: OVS bridge iface established\n", nii);
+	return nii;
+}
+#endif
+
+#ifdef ECM_INTERFACE_BOND_ENABLE
+/*
+ * ecm_interface_lag_interface_establish()
+ *	Returns a reference to a iface of the LAG type, possibly creating one if necessary.
+ * Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_lag_interface_establish(struct ecm_db_interface_info_lag *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish LAG iface: %s with address: %pM, MTU: %d, if num: %d, accel engine if id: %d\n",
+			dev_name, type_info->address, mtu, dev_interface_num, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_lag(type_info->address);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_lag(type_info->address);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+	ecm_db_iface_add_lag(nii, type_info->address, dev_name,
+			mtu, dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: lag iface established\n", nii);
+	return nii;
+}
+#endif
+
+/*
+ * ecm_interface_ethernet_interface_establish()
+ *	Returns a reference to a iface of the ETHERNET type, possibly creating one if necessary.
+ * Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_ethernet_interface_establish(struct ecm_db_interface_info_ethernet *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish ETHERNET iface: %s with address: %pM, MTU: %d, if num: %d, accel engine if id: %d\n",
+			dev_name, type_info->address, mtu, dev_interface_num, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_ifidx_find_and_ref_ethernet(type_info->address, dev_interface_num);
+
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		/*
+		 * Update the accel engine interface identifier, just in case it was changed.
+		 */
+		ecm_db_iface_ae_interface_identifier_set(ii, ae_interface_num);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_ifidx_find_and_ref_ethernet(type_info->address, dev_interface_num);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+	ecm_db_iface_add_ethernet(nii, type_info->address, dev_name,
+			mtu, dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: ethernet iface established\n", nii);
+	return nii;
+}
+
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+/*
+ * ecm_interface_pppoe_interface_establish()
+ *	Returns a reference to a iface of the PPPoE type, possibly creating one if necessary.
+ * Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_pppoe_interface_establish(struct ecm_db_interface_info_pppoe *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish PPPoE iface: %s with session id: %u, remote mac: %pM, MTU: %d, if num: %d, accel engine if id: %d\n",
+			dev_name, type_info->pppoe_session_id, type_info->remote_mac, mtu, dev_interface_num, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_pppoe(type_info->pppoe_session_id, type_info->remote_mac);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_pppoe(type_info->pppoe_session_id, type_info->remote_mac);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+	ecm_db_iface_add_pppoe(nii, type_info->pppoe_session_id, type_info->remote_mac, dev_name,
+			mtu, dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: pppoe iface established\n", nii);
+	return nii;
+}
+#endif
+
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+/*
+ * ecm_interface_map_t_interface_establish()
+ *	Returns a reference to a iface of the PPPoE type, possibly creating one if necessary.
+ * Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_map_t_interface_establish(struct ecm_db_interface_info_map_t *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Establish MAP-T iface: %s   MTU: %d, if num: %d, accel engine if id: %d\n",
+			dev_name, mtu, dev_interface_num, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_map_t(type_info->if_index, ae_interface_num);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_map_t(type_info->if_index, ae_interface_num);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+	ecm_db_iface_add_map_t(nii, type_info, dev_name,
+			mtu, dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: map_t iface established\n", nii);
+	return nii;
+}
+#endif
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+/*
+ * ecm_interface_pppol2tpv2_interface_establish()
+ *	Returns a reference to a iface of the PPPoL2TPV2 type, possibly creating one if necessary.
+ *	Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_pppol2tpv2_interface_establish(struct ecm_db_interface_info_pppol2tpv2 *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish PPPol2tp iface: %s with tunnel id=%u session id %u\n", dev_name, type_info->l2tp.tunnel.tunnel_id,
+				type_info->l2tp.session.session_id);
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_pppol2tpv2(type_info->l2tp.tunnel.tunnel_id, type_info->l2tp.session.session_id);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		ecm_db_iface_update_ae_interface_identifier(ii, ae_interface_num);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_pppol2tpv2(type_info->l2tp.tunnel.tunnel_id, type_info->l2tp.session.session_id);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		ecm_db_iface_update_ae_interface_identifier(ii, ae_interface_num);
+		return ii;
+	}
+
+	ecm_db_iface_add_pppol2tpv2(nii, type_info, dev_name, mtu, dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: pppol2tpv2 iface established\n", nii);
+	return nii;
+}
+
+#endif
+
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+/*
+ * ecm_interface_pptp_interface_establish()
+ *	Returns a reference to a iface of the PPTP type, possibly creating one if necessary.
+ *	Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_pptp_interface_establish(struct ecm_db_interface_info_pptp *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish PPTP iface: %s with local call id %u peer call id %u\n", dev_name, type_info->src_call_id,
+				type_info->dst_call_id);
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_pptp(type_info->src_call_id, type_info->dst_call_id, ae_interface_num);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		ecm_db_iface_update_ae_interface_identifier(ii, ae_interface_num);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_pptp(type_info->src_call_id, type_info->dst_call_id, ae_interface_num);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		ecm_db_iface_update_ae_interface_identifier(ii, ae_interface_num);
+		return ii;
+	}
+
+	ecm_db_iface_add_pptp(nii, type_info, dev_name, mtu, dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: pptp iface established\n", nii);
+	return nii;
+}
+#endif
+
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+/*
+ * ecm_interface_gre_tun_interface_establish()
+ *	Returns a reference to a iface of the gre type, possibly creating one if necessary.
+ *	Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_gre_tun_interface_establish(struct ecm_db_interface_info_gre_tun *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_TRACE("Establish GRE TUN iface: %s   MTU: %d, if num: %d, accel engine if id: %d\n",
+			dev_name, mtu, dev_interface_num, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_gre_tun(type_info->if_index, ae_interface_num);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_gre_tun(type_info->if_index, ae_interface_num);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+	ecm_db_iface_add_gre_tun(nii, type_info, dev_name,
+			mtu, dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: gre iface established\n", nii);
+	return nii;
+}
+#endif
+
+/*
+ * ecm_interface_unknown_interface_establish()
+ *	Returns a reference to a iface of the UNKNOWN type, possibly creating one if necessary.
+ * Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_unknown_interface_establish(struct ecm_db_interface_info_unknown *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish UNKNOWN iface: %s with os_specific_ident: %u, MTU: %d, if num: %d, accel engine if id: %d\n",
+			dev_name, type_info->os_specific_ident, mtu, dev_interface_num, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_unknown(type_info->os_specific_ident);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_unknown(type_info->os_specific_ident);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+	ecm_db_iface_add_unknown(nii, type_info->os_specific_ident, dev_name,
+			mtu, dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: unknown iface established\n", nii);
+	return nii;
+}
+
+/*
+ * ecm_interface_loopback_interface_establish()
+ *	Returns a reference to a iface of the LOOPBACK type, possibly creating one if necessary.
+ * Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_loopback_interface_establish(struct ecm_db_interface_info_loopback *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish LOOPBACK iface: %s with os_specific_ident: %u, MTU: %d, if num: %d, accel engine if id: %d\n",
+			dev_name, type_info->os_specific_ident, mtu, dev_interface_num, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_loopback(type_info->os_specific_ident);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_loopback(type_info->os_specific_ident);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+	ecm_db_iface_add_loopback(nii, type_info->os_specific_ident, dev_name,
+			mtu, dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: loopback iface established\n", nii);
+	return nii;
+}
+
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+/*
+ * ecm_interface_ipsec_tunnel_interface_establish()
+ *	Returns a reference to a iface of the IPSEC_TUNNEL type, possibly creating one if necessary.
+ * Returns NULL on failure or a reference to interface.
+ *
+ * NOTE: GGG TODO THIS NEEDS TO TAKE A PROPER APPROACH TO IPSEC TUNNELS USING ENDPOINT ADDRESSING AS THE TYPE INFO KEYS
+ */
+static struct ecm_db_iface_instance *ecm_interface_ipsec_tunnel_interface_establish(struct ecm_db_interface_info_ipsec_tunnel *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish IPSEC_TUNNEL iface: %s with os_specific_ident: %u, MTU: %d, if num: %d, accel engine if id: %d\n",
+			dev_name, type_info->os_specific_ident, mtu, dev_interface_num, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_ipsec_tunnel(type_info->os_specific_ident, ae_interface_num);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_ipsec_tunnel(type_info->os_specific_ident, ae_interface_num);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+	ecm_db_iface_add_ipsec_tunnel(nii, type_info->os_specific_ident, dev_name,
+			mtu, dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: ipsec_tunnel iface established\n", nii);
+	return nii;
+}
+#endif
+
+#ifdef ECM_INTERFACE_SIT_ENABLE
+#ifdef CONFIG_IPV6_SIT_6RD
+/*
+ * ecm_interface_sit_interface_establish()
+ *	Returns a reference to a iface of the SIT type, possibly creating one if necessary.
+ * Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_sit_interface_establish(struct ecm_db_interface_info_sit *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish SIT iface: %s with saddr: " ECM_IP_ADDR_OCTAL_FMT ", daddr: " ECM_IP_ADDR_OCTAL_FMT ", MTU: %d, if num: %d, accel engine if id: %d\n",
+			dev_name, ECM_IP_ADDR_TO_OCTAL(type_info->saddr), ECM_IP_ADDR_TO_OCTAL(type_info->daddr), mtu, dev_interface_num, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_sit(type_info->saddr, type_info->daddr, ae_interface_num);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_sit(type_info->saddr, type_info->daddr, ae_interface_num);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+	ecm_db_iface_add_sit(nii, type_info, dev_name, mtu, dev_interface_num,
+			ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: sit iface established\n", nii);
+	return nii;
+}
+#endif
+#endif
+
+#ifdef ECM_INTERFACE_TUNIPIP6_ENABLE
+#ifdef ECM_IPV6_ENABLE
+/*
+ * ecm_interface_tunipip6_interface_establish()
+ *	Returns a reference to a iface of the TUNIPIP6 type, possibly creating one if necessary.
+ * Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_tunipip6_interface_establish(struct ecm_db_interface_info_tunipip6 *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish TUNIPIP6 iface: %s with saddr: " ECM_IP_ADDR_OCTAL_FMT ", daddr: " ECM_IP_ADDR_OCTAL_FMT ", MTU: %d, if num: %d, accel engine if id: %d\n",
+			dev_name, ECM_IP_ADDR_TO_OCTAL(type_info->saddr), ECM_IP_ADDR_TO_OCTAL(type_info->daddr), mtu, dev_interface_num, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_tunipip6(type_info->saddr, type_info->daddr, ae_interface_num);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_tunipip6(type_info->saddr, type_info->daddr, ae_interface_num);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+	ecm_db_iface_add_tunipip6(nii, type_info, dev_name, mtu, dev_interface_num,
+			ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: tunipip6 iface established\n", nii);
+	return nii;
+}
+#endif
+#endif
+
+#ifdef ECM_INTERFACE_RAWIP_ENABLE
+/*
+ * ecm_interface_rawip_interface_establish()
+ *	Returns a reference to a iface of the RAWIP type, possibly creating one if necessary.
+ * Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_rawip_interface_establish(struct ecm_db_interface_info_rawip *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish RAWIP iface: %s with address: %pM, MTU: %d, if num: %d, accel engine if id: %d\n",
+			dev_name, type_info->address, mtu, dev_interface_num, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_rawip(type_info->address);
+	if (ii) {
+		DEBUG_TRACE("%px: RAWIP iface already established\n", ii);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish RAWIP iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_rawip(type_info->address);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+	ecm_db_iface_add_rawip(nii, type_info->address, dev_name,
+			mtu, dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: RAWIP iface established\n", nii);
+	return nii;
+}
+#endif
+
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+/*
+ * ecm_interface_ovpn_interface_establish()
+ *	Returns reference to iface of the OVPN type.
+ */
+static struct ecm_db_iface_instance *ecm_interface_ovpn_interface_establish(struct ecm_db_interface_info_ovpn *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish OVPN iface: %s with ae_interface_num : %d, MTU: %d, if num: %d\n",
+			dev_name, type_info->tun_ifnum, mtu, dev_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_ovpn(type_info->tun_ifnum);
+	if (ii) {
+		DEBUG_TRACE("%px: iface established\n", ii);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_ovpn(type_info->tun_ifnum);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		return ii;
+	}
+
+	ecm_db_iface_add_ovpn(nii, type_info, dev_name, mtu, dev_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: ovpn iface established\n", nii);
+	return nii;
+}
+#endif
+
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+/*
+ * ecm_interface_vxlan_interface_establish()
+ *	Returns a reference to a iface of the VxLAN type, possibly creating one if necessary.
+ * Returns NULL on failure or a reference to interface.
+ */
+static struct ecm_db_iface_instance *ecm_interface_vxlan_interface_establish(struct ecm_db_interface_info_vxlan *type_info,
+							char *dev_name, int32_t dev_interface_num, int32_t ae_interface_num, int32_t mtu)
+{
+	struct ecm_db_iface_instance *nii;
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Establish VxLAN iface: %s with vxlan id: %u, MTU: %d, if num: %d, if_type: %d, accel engine if id: %d\n",
+			dev_name, type_info->vni, mtu, dev_interface_num, type_info->if_type, ae_interface_num);
+
+	/*
+	 * Locate the iface
+	 */
+	ii = ecm_db_iface_find_and_ref_vxlan(type_info->vni, type_info->if_type);
+	if (ii) {
+		DEBUG_TRACE("%px: vxlan iface established\n", ii);
+		/*
+		 * Update the accel engine interface identifier, just in case it was changed.
+		 */
+		ecm_db_iface_update_ae_interface_identifier(ii, ae_interface_num);
+		return ii;
+	}
+
+	/*
+	 * No iface - create one
+	 */
+	nii = ecm_db_iface_alloc();
+	if (!nii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Add iface into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_interface_lock);
+	ii = ecm_db_iface_find_and_ref_vxlan(type_info->vni, type_info->if_type);
+	if (ii) {
+		spin_unlock_bh(&ecm_interface_lock);
+		ecm_db_iface_deref(nii);
+		ecm_db_iface_update_ae_interface_identifier(ii, ae_interface_num);
+		DEBUG_TRACE("%px: vxlan iface established\n", ii);
+		return ii;
+	}
+	ecm_db_iface_add_vxlan(nii, type_info->vni, type_info->if_type, dev_name, mtu,
+			dev_interface_num, ae_interface_num, NULL, nii);
+	spin_unlock_bh(&ecm_interface_lock);
+
+	DEBUG_TRACE("%px: vxlan iface established\n", nii);
+	return nii;
+}
+#endif
+
+/*
+ * ecm_interface_tunnel_mtu_update()
+ *	Update mtu if the flow is a tunneled packet.
+ */
+bool ecm_interface_tunnel_mtu_update(ip_addr_t saddr, ip_addr_t daddr, ecm_db_iface_type_t type, int32_t *mtu)
+{
+	struct net_device *src_dev;
+	struct net_device *dest_dev;
+	bool ret = true;
+
+	/*
+	 * Check if source IP is local address
+	 */
+	src_dev = ecm_interface_dev_find_by_local_addr(saddr);
+	dest_dev = ecm_interface_dev_find_by_local_addr(daddr);
+
+	switch (type) {
+
+	case ECM_DB_IFACE_TYPE_OVPN:
+		if (src_dev) {
+			*mtu = src_dev->mtu;
+		} else if (dest_dev) {
+			*mtu = dest_dev->mtu;
+		} else {
+			return false;
+		}
+		break;
+
+	case ECM_DB_IFACE_TYPE_PPTP:
+	case ECM_DB_IFACE_TYPE_PPPOL2TPV2:
+	case ECM_DB_IFACE_TYPE_GRE_TUN:
+	case ECM_DB_IFACE_TYPE_GRE_TAP:
+	case ECM_DB_IFACE_TYPE_VXLAN:
+	case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+		if (src_dev) {
+			*mtu = src_dev->mtu;
+		} else {
+			ret = false;
+			goto done;
+		}
+		break;
+
+	default:
+		ret = false;
+		DEBUG_WARN("Tunnel type doesn't need to update MTU value\n");
+		break;
+	}
+
+done:
+	if (src_dev) {
+		dev_put(src_dev);
+	}
+
+	if (dest_dev) {
+		dev_put(dest_dev);
+	}
+
+	return ret;
+}
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+/*
+ * ecm_interface_ovs_bridge_port_dev_get_and_ref()
+ * 	Looks up the slave port in the bridge devices port list.
+ */
+static struct net_device *ecm_interface_ovs_bridge_port_dev_get_and_ref(struct sk_buff *skb, struct net_device *br_dev,
+								ip_addr_t src_ip, ip_addr_t dst_ip, int ip_version,
+								int protocol, bool is_routed, uint8_t *smac,
+								uint8_t *dmac, __be16 *layer4hdr,
+								struct ecm_front_end_ovs_params *op)
+{
+	struct ovsmgr_dp_flow flow;
+	struct ovsmgr_dp_flow return_flow;
+	struct net_device *dev;
+
+	memset(&flow, 0, sizeof(flow));
+
+	flow.indev = br_dev;
+	flow.outdev = NULL;
+	flow.tuple.ip_version = ip_version;
+	flow.tuple.protocol = protocol;
+	flow.is_routed = is_routed;
+
+	if (!smac) {
+		ether_addr_copy(flow.smac, br_dev->dev_addr);
+	}
+
+	ether_addr_copy(flow.dmac, dmac);
+
+	/*
+	 * Consider a routing flow
+	 * eth1-ovsbr1----->ovsbr2-eth2
+	 * The 2 ovs data path rules should look like the following,
+	 * 1. ingress port:eth1, egress_port:ovsbr1
+	 * 2. ingress_port:ovsbr2, egress_port:eth2
+	 *
+	 * Copy the multicast mac address, if src_ip is multicast.
+	 * During multicast 'from' hierarchy creation, the ECM
+	 * copies the source MAC as multicast MAC as the
+	 * reverse direction rule is not present in the ovs
+	 * data path rule set.
+	 */
+	if (ecm_ip_addr_is_multicast(src_ip)) {
+		struct ethhdr *skb_eth_hdr;
+
+		skb_eth_hdr = eth_hdr(skb);
+		ether_addr_copy(flow.smac, dmac);
+		ether_addr_copy(flow.dmac, skb_eth_hdr->h_dest);
+
+		if (protocol == IPPROTO_UDP) {
+			struct udphdr *udp_hdr = (struct udphdr *)layer4hdr;
+
+			flow.tuple.src_port = udp_hdr->source;
+			flow.tuple.dst_port = udp_hdr->dest;
+		} else {
+			DEBUG_WARN("%px: Protocol is not UDP\n", skb);
+			return NULL;
+		}
+
+		if (ip_version == 4) {
+			ECM_IP_ADDR_TO_NIN4_ADDR(flow.tuple.ipv4.src, dst_ip);
+			ECM_IP_ADDR_TO_NIN4_ADDR(flow.tuple.ipv4.dst, src_ip);
+			DEBUG_TRACE("%px: br_dev: %s, src_addr: %pI4, dest_addr: %pI4, ip_version: %d, protocol: %d (sp:%d, dp:%d) (smac:%pM, dmac:%pM)\n",
+					skb, br_dev->name, &flow.tuple.ipv4.src, &flow.tuple.ipv4.dst,
+					ip_version, protocol, flow.tuple.src_port, flow.tuple.dst_port, flow.smac, flow.dmac);
+		} else {
+			ECM_IP_ADDR_TO_NIN6_ADDR(flow.tuple.ipv6.src, dst_ip);
+			ECM_IP_ADDR_TO_NIN6_ADDR(flow.tuple.ipv6.dst, src_ip);
+			DEBUG_TRACE("%px: br_dev: %s, src_addr: %pI6, dest_addr: %pI6, ip_version: %d, protocol: %d (sp:%d, dp:%d) (smac:%pM, dmac:%pM)\n",
+					skb, br_dev->name, &flow.tuple.ipv6.src, &flow.tuple.ipv6.dst,
+					ip_version, protocol, flow.tuple.src_port, flow.tuple.dst_port, flow.smac, flow.dmac);
+		}
+
+		goto port_find;
+	}
+
+	/*
+	 * OVS parameters are not passed explicitly for the following cases:
+	 * 1. IPv6 flows
+	 * 2. IPv4/IPv6 non-ported flows
+	 * 3. Multicast flows.
+	 * 4. SFE flows
+	 */
+	if (!op) {
+		if (protocol == IPPROTO_TCP) {
+			struct tcphdr *tcp_hdr = (struct tcphdr *)layer4hdr;
+
+			flow.tuple.src_port = tcp_hdr->source;
+			flow.tuple.dst_port = tcp_hdr->dest;
+		} else if (protocol == IPPROTO_UDP) {
+			struct udphdr *udp_hdr = (struct udphdr *)layer4hdr;
+
+			flow.tuple.src_port = udp_hdr->source;
+			flow.tuple.dst_port = udp_hdr->dest;
+		} else {
+			DEBUG_WARN("%px: Protocol is not udp/tcp\n", skb);
+			return NULL;
+		}
+
+		if (ip_version == 4) {
+			ECM_IP_ADDR_TO_NIN4_ADDR(flow.tuple.ipv4.src, src_ip);
+			ECM_IP_ADDR_TO_NIN4_ADDR(flow.tuple.ipv4.dst, dst_ip);
+			DEBUG_TRACE("%px: br_dev: %s, src_addr: %pI4, dest_addr: %pI4, ip_version: %d, protocol: %d (sp:%d, dp:%d) (smac:%pM, dmac:%pM)\n",
+					skb, br_dev->name, &flow.tuple.ipv4.src, &flow.tuple.ipv4.dst,
+					ip_version, protocol, flow.tuple.src_port, flow.tuple.dst_port, flow.smac, flow.dmac);
+		} else {
+			ECM_IP_ADDR_TO_NIN6_ADDR(flow.tuple.ipv6.src, src_ip);
+			ECM_IP_ADDR_TO_NIN6_ADDR(flow.tuple.ipv6.dst, dst_ip);
+			DEBUG_TRACE("%px: br_dev: %s, src_addr: %pI6, dest_addr: %pI6, ip_version: %d, protocol: %d (sp:%d, dp:%d) (smac:%pM, dmac:%pM)\n",
+					skb, br_dev->name, &flow.tuple.ipv6.src, &flow.tuple.ipv6.dst,
+					ip_version, protocol, flow.tuple.src_port, flow.tuple.dst_port, flow.smac, flow.dmac);
+		}
+
+		goto port_find;
+	}
+
+	/*
+	 * We use OVS params for IPv4 NSS unicast flows.
+	 */
+	if ((protocol == IPPROTO_TCP) || (protocol == IPPROTO_UDP)) {
+		flow.tuple.src_port = htons(op->src_port);
+		flow.tuple.dst_port = htons(op->dest_port);
+	} else {
+		DEBUG_WARN("%px: Protocol is not udp/tcp\n", skb);
+		return NULL;
+	}
+
+	if (ip_version == 4) {
+		ECM_IP_ADDR_TO_NIN4_ADDR(flow.tuple.ipv4.src, op->src_ip);
+		ECM_IP_ADDR_TO_NIN4_ADDR(flow.tuple.ipv4.dst, op->dest_ip);
+		DEBUG_TRACE("%px: br_dev: %s, src_addr: %pI4, dest_addr: %pI4, ip_version: %d, protocol: %d (sp:%d, dp:%d) (smac:%pM, dmac:%pM)\n",
+				skb, br_dev->name, &flow.tuple.ipv4.src, &flow.tuple.ipv4.dst,
+				ip_version, protocol, flow.tuple.src_port, flow.tuple.dst_port, flow.smac, flow.dmac);
+	} else {
+		ECM_IP_ADDR_TO_NIN6_ADDR(flow.tuple.ipv6.src, op->src_ip);
+		ECM_IP_ADDR_TO_NIN6_ADDR(flow.tuple.ipv6.dst, op->dest_ip);
+		DEBUG_TRACE("%px: br_dev: %s, src_addr: %pI6, dest_addr: %pI6, ip_version: %d, protocol: %d (sp:%d, dp:%d) (smac:%pM, dmac:%pM)\n",
+				skb, br_dev->name, &flow.tuple.ipv6.src, &flow.tuple.ipv6.dst,
+				ip_version, protocol, flow.tuple.src_port, flow.tuple.dst_port, flow.smac, flow.dmac);
+	}
+
+port_find:
+	dev = ovsmgr_port_find(skb, br_dev, &flow);
+	if (dev) {
+		DEBUG_TRACE("OVS egress port dev: %s\n", dev->name);
+		dev_hold(dev);
+		return dev;
+	}
+
+	/*
+	 * Handle Multicast flows separately.
+	 */
+	if (ecm_ip_addr_is_multicast(src_ip)) {
+		dev = ovsmgr_port_find_by_mac(skb, br_dev, &flow);
+		if (!dev) {
+			DEBUG_WARN("%px: Couldn't find OVS bridge port for Multicast flow.\n", skb);
+			return NULL;
+		}
+
+		dev_hold(dev);
+		return dev;
+	}
+
+	/*
+	 * Find by MAC addresses using return flow
+	 */
+	return_flow.indev = NULL;
+	return_flow.outdev = br_dev;
+	return_flow.tuple.ip_version = flow.tuple.ip_version;
+	return_flow.tuple.protocol = flow.tuple.protocol;
+	return_flow.is_routed = flow.is_routed;
+
+	ether_addr_copy(return_flow.smac, flow.dmac);
+	ether_addr_copy(return_flow.dmac, flow.smac);
+	return_flow.tuple.src_port = flow.tuple.dst_port;
+	return_flow.tuple.dst_port = flow.tuple.src_port;
+	if (ip_version == 4) {
+		return_flow.tuple.ipv4.src = flow.tuple.ipv4.dst;
+		return_flow.tuple.ipv4.dst = flow.tuple.ipv4.src;
+		DEBUG_TRACE("%px: br_dev = %s, src_addr: %pI4, dest_addr: %pI4, ip_version: %d, protocol: %d (sp:%d, dp:%d) (smac:%pM, dmac:%pM)\n",
+				skb, br_dev->name, &return_flow.tuple.ipv4.src,
+				&return_flow.tuple.ipv4.dst, return_flow.tuple.ip_version,
+				return_flow.tuple.protocol, return_flow.tuple.src_port, return_flow.tuple.dst_port,
+				return_flow.smac, return_flow.dmac);
+	} else {
+		memcpy(&return_flow.tuple.ipv6.src, &flow.tuple.ipv6.dst, sizeof(return_flow.tuple.ipv6.src));
+		memcpy(&return_flow.tuple.ipv6.dst, &flow.tuple.ipv6.src, sizeof(return_flow.tuple.ipv6.dst));
+		DEBUG_TRACE("%px: br_dev = %s, src_addr: %pI6, dest_addr: %pI6, ip_version: %d, protocol: %d (sp:%d, dp:%d) (smac:%pM, dmac:%pM)\n",
+				skb, br_dev->name, &return_flow.tuple.ipv4.src,
+				&return_flow.tuple.ipv4.dst, return_flow.tuple.ip_version,
+				return_flow.tuple.protocol, return_flow.tuple.src_port, return_flow.tuple.dst_port,
+				return_flow.smac, return_flow.dmac);
+	}
+
+	dev = ovsmgr_port_find_by_mac(skb, br_dev, &return_flow);
+	if (!dev) {
+		DEBUG_WARN("%px: Couldn't find OVS bridge port\n", skb);
+		return NULL;
+	}
+
+	dev_hold(dev);
+	return dev;
+}
+#endif
+
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+/*
+ * ecm_interface_macvlan_mode_is_valid()
+ * 	Check if the macvlan interface allowed for acceleration.
+ */
+static bool ecm_interface_macvlan_mode_is_valid(struct net_device *dev)
+{
+	enum macvlan_mode mode = macvlan_get_mode(dev);
+
+	/*
+	 * Allow acceleration for only "Private" mode.
+	 */
+	if (mode == MACVLAN_MODE_PRIVATE) {
+		return true;
+	}
+
+	DEBUG_WARN("%px: MACVLAN dev: %s, MACVLAN mode: %d is not supported for acceleration\n", dev,
+			dev->name, mode);
+	return false;
+}
+#endif
+
+/*
+ * ecm_interface_establish_and_ref()
+ *	Establish an interface instance for the given interface detail.
+ */
+struct ecm_db_iface_instance *ecm_interface_establish_and_ref(struct ecm_front_end_connection_instance *feci,
+								struct net_device *dev, struct sk_buff *skb)
+{
+	int32_t dev_interface_num;
+	char *dev_name;
+	int32_t dev_type;
+	int32_t dev_mtu;
+	int32_t ae_interface_num;
+	struct ecm_db_iface_instance *ii;
+	int32_t interface_type __attribute__((unused));
+	union {
+		struct ecm_db_interface_info_ethernet ethernet;		/* type == ECM_DB_IFACE_TYPE_ETHERNET */
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan;			/* type == ECM_DB_IFACE_TYPE_VLAN */
+#endif
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+		struct ecm_db_interface_info_macvlan macvlan;		/* type == ECM_DB_IFACE_TYPE_MACVLAN */
+#endif
+#ifdef ECM_INTERFACE_BOND_ENABLE
+		struct ecm_db_interface_info_lag lag;			/* type == ECM_DB_IFACE_TYPE_LAG */
+#endif
+		struct ecm_db_interface_info_bridge bridge;		/* type == ECM_DB_IFACE_TYPE_BRIDGE */
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+		struct ecm_db_interface_info_pppoe pppoe;		/* type == ECM_DB_IFACE_TYPE_PPPOE */
+#endif
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+		struct ecm_db_interface_info_pppol2tpv2 pppol2tpv2;		/* type == ECM_DB_IFACE_TYPE_PPPOL2TPV2 */
+#endif
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+		struct ecm_db_interface_info_pptp pptp;			/* type == ECM_DB_IFACE_TYPE_PPTP */
+#endif
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+		struct ecm_db_interface_info_map_t map_t;		/* type == ECM_DB_IFACE_TYPE_MAP_T */
+#endif
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+		struct ecm_db_interface_info_gre_tun gre_tun;			/* type == ECM_DB_IFACE_TYPE_GRE */
+#endif
+		struct ecm_db_interface_info_unknown unknown;		/* type == ECM_DB_IFACE_TYPE_UNKNOWN */
+		struct ecm_db_interface_info_loopback loopback;		/* type == ECM_DB_IFACE_TYPE_LOOPBACK */
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+		struct ecm_db_interface_info_ipsec_tunnel ipsec_tunnel;	/* type == ECM_DB_IFACE_TYPE_IPSEC_TUNNEL */
+#endif
+#ifdef ECM_INTERFACE_SIT_ENABLE
+		struct ecm_db_interface_info_sit sit;			/* type == ECM_DB_IFACE_TYPE_SIT */
+#endif
+#ifdef ECM_INTERFACE_TUNIPIP6_ENABLE
+#ifdef ECM_IPV6_ENABLE
+		struct ecm_db_interface_info_tunipip6 tunipip6;		/* type == ECM_DB_IFACE_TYPE_TUNIPIP6 */
+#endif
+#endif
+#ifdef ECM_INTERFACE_RAWIP_ENABLE
+		struct ecm_db_interface_info_rawip rawip;		/* type == ECM_DB_IFACE_TYPE_RAWIP */
+#endif
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+		struct ecm_db_interface_info_ovpn ovpn;			/* type == ECM_DB_IFACE_TYPE_OVPN */
+#endif
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+		struct ecm_db_interface_info_vxlan vxlan;		/* type == ECM_DB_IFACE_TYPE_VXLAN */
+#endif
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+		struct ecm_db_interface_info_ovs_bridge ovsb;		/* type == ECM_DB_IFACE_TYPE_OVS_BRIDGE */
+#endif
+	} type_info;
+
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+	struct ip_tunnel *gre4_tunnel;
+	struct ip6_tnl *gre6_tunnel;
+#endif
+#ifdef ECM_INTERFACE_PPP_ENABLE
+	int channel_count;
+	struct ppp_channel *ppp_chan[1];
+	int channel_protocol;
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+	int protocol = IPPROTO_IP;
+	struct pptp_opt opt;
+	struct iphdr *v4_hdr = NULL;
+	if (skb) {
+		v4_hdr = ip_hdr(skb);
+		protocol = v4_hdr->protocol;
+	}
+#endif
+#endif
+	/*
+	 * Get basic information about the given device
+	 */
+	dev_interface_num = dev->ifindex;
+	dev_name = dev->name;
+	dev_type = dev->type;
+	dev_mtu = dev->mtu;
+
+	/*
+	 * Does the accel engine recognise this interface?
+	 */
+	ae_interface_num = feci->ae_interface_number_by_dev_get(dev);
+
+	DEBUG_TRACE("%px: Establish interface instance for device: %px is type: %d, name: %s, ifindex: %d, ae_if: %d, mtu: %d\n",
+			feci, dev, dev_type, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+
+	/*
+	 * Extract from the device more type-specific information
+	 */
+	if (dev_type == ARPHRD_ETHER) {
+
+		/*
+		 * If MAC address is zeros, do nothing.
+		 */
+		if (is_zero_ether_addr(dev->dev_addr)) {
+			DEBUG_WARN("%px: Net device %px MAC address is all zeros\n", feci, dev);
+			return NULL;
+		}
+
+		/*
+		 * Ethernet - but what sub type?
+		 */
+
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		/*
+		 * VLAN?
+		 */
+		if (is_vlan_dev(dev)) {
+			/*
+			 * VLAN master
+			 * GGG No locking needed here, ASSUMPTION is that real_dev is held for as long as we have dev.
+			 */
+			ether_addr_copy(type_info.vlan.address, dev->dev_addr);
+			type_info.vlan.vlan_tag = vlan_dev_vlan_id(dev);
+			type_info.vlan.vlan_tpid = ntohs(vlan_dev_vlan_proto(dev));
+			DEBUG_TRACE("%px: Net device: %px is VLAN, mac: %pM, vlan_id: %x vlan_tpid: %x\n",
+					feci, dev, type_info.vlan.address, type_info.vlan.vlan_tag, type_info.vlan.vlan_tpid);
+
+			/*
+			 * Establish this type of interface
+			 */
+			ii = ecm_interface_vlan_interface_establish(&type_info.vlan, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+			goto identifier_update;
+		}
+#endif
+
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+		/*
+		 * MACVLAN?
+		 */
+		if (netif_is_macvlan(dev)) {
+			if (ecm_interface_macvlan_mode_is_valid(dev)) {
+				ether_addr_copy(type_info.macvlan.address, dev->dev_addr);
+				DEBUG_TRACE("%px: Net device: %px is MACVLAN, mac: %pM\n",
+						feci, dev, type_info.macvlan.address);
+
+				/*
+				 * Establish this type of interface
+				 */
+				ii = ecm_interface_macvlan_interface_establish(&type_info.macvlan, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+				goto identifier_update;
+			}
+
+			DEBUG_WARN("%px: Net device %px MACVLAN mode is not supported.\n", feci, dev);
+			return NULL;
+		}
+#endif
+
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+		/*
+		 * VxLAN?
+		 */
+		if (netif_is_vxlan(dev)) {
+			u32 vni;
+			struct vxlan_dev *vxlan_tun;
+			ip_addr_t vxlan_saddr, vxlan_daddr;
+
+			/*
+			 * VxLAN
+			 */
+			vxlan_tun = netdev_priv(dev);
+			vni = vxlan_get_vni(vxlan_tun);
+			DEBUG_TRACE("%px: Net device: %px is VxLAN, mac: %pM, vni: %d\n",
+					feci, dev, dev->dev_addr, vni);
+			interface_type = ecm_interface_vxlan_type_get(skb);
+			ae_interface_num = feci->ae_interface_number_by_dev_type_get(dev, interface_type);
+			DEBUG_TRACE("%px: VxLAN netdevice interface ae_interface_num: %d, interface_type: %d\n",
+					feci, ae_interface_num, interface_type);
+
+			type_info.vxlan.vni = vni;
+			type_info.vxlan.if_type = interface_type;
+
+			/*
+			 * Copy IP addresses from skb
+			 */
+			if (ip_hdr(skb)->version == IPVERSION) {
+				ECM_NIN4_ADDR_TO_IP_ADDR(vxlan_saddr, ip_hdr(skb)->saddr);
+				ECM_NIN4_ADDR_TO_IP_ADDR(vxlan_daddr, ip_hdr(skb)->daddr);
+			} else {
+				ECM_NIN6_ADDR_TO_IP_ADDR(vxlan_saddr, ipv6_hdr(skb)->saddr);
+				ECM_NIN6_ADDR_TO_IP_ADDR(vxlan_daddr, ipv6_hdr(skb)->daddr);
+			}
+
+			if (ecm_interface_tunnel_mtu_update(vxlan_saddr, vxlan_daddr,
+						ECM_DB_IFACE_TYPE_VXLAN, &dev_mtu)) {
+				DEBUG_TRACE("%px: VxLAN netdevice mtu updated: %d\n", feci, dev_mtu);
+			}
+
+			/*
+			 * Establish this type of interface
+			 */
+			ii = ecm_interface_vxlan_interface_establish(&type_info.vxlan, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+			goto identifier_update;
+		}
+#endif
+
+		/*
+		 * BRIDGE?
+		 */
+		if (ecm_front_end_is_bridge_device(dev)) {
+			/*
+			 * Bridge
+			 */
+			ether_addr_copy(type_info.bridge.address, dev->dev_addr);
+
+			DEBUG_TRACE("%px: Net device: %px is BRIDGE, mac: %pM\n",
+					feci, dev, type_info.bridge.address);
+
+			/*
+			 * Establish this type of interface
+			 */
+			ii = ecm_interface_bridge_interface_establish(&type_info.bridge, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+			goto identifier_update;
+		}
+
+		/*
+		 * OVS BRIDGE?
+		 */
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+		if (ovsmgr_is_ovs_master(dev)) {
+			/*
+			 * OVS Bridge
+			 */
+			ether_addr_copy(type_info.ovsb.address, dev->dev_addr);
+
+			DEBUG_TRACE("%px: Net device: %px is OVS BRIDGE, mac: %pM\n",
+					feci, dev, type_info.ovsb.address);
+
+			/*
+			 * Establish this type of interface
+			 */
+			ii = ecm_interface_ovs_bridge_interface_establish(&type_info.ovsb, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+			goto identifier_update;
+		}
+#endif
+
+#ifdef ECM_INTERFACE_BOND_ENABLE
+		/*
+		 * LAG?
+		 */
+		if (ecm_front_end_is_lag_master(dev)) {
+			/*
+			 * Link aggregation
+			 */
+			ether_addr_copy(type_info.lag.address, dev->dev_addr);
+
+			DEBUG_TRACE("%px: Net device: %px is LAG, mac: %pM\n",
+					feci, dev, type_info.lag.address);
+
+			/*
+			 * Establish this type of interface
+			 */
+			ii = ecm_interface_lag_interface_establish(&type_info.lag, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+			goto identifier_update;
+		}
+#endif
+
+#ifdef ECM_INTERFACE_GRE_TAP_ENABLE
+		/*
+		 * GRE TAP?
+		 */
+		if (dev->priv_flags_ext & (IFF_EXT_GRE_V4_TAP | IFF_EXT_GRE_V6_TAP)) {
+			interface_type = feci->ae_interface_type_get(feci, dev);
+			ae_interface_num = feci->ae_interface_number_by_dev_type_get(dev, interface_type);
+
+			/*
+			 * GRE TAP interface is handled as ethernet interface, however it is possible
+			 * that the acceleration engine may not be ready yet to handle the connection.
+			 * In this case the acceleration engine interface is not found for this type and
+			 * we should wait until it is ready.
+			 */
+			if (ae_interface_num < 0) {
+				DEBUG_TRACE("%px: GRE TAP interface is not ready yet. Interface type: %d\n", feci, interface_type);
+				return NULL;
+			}
+		}
+#endif
+		/*
+		 * ETHERNET!
+		 * Just plain ethernet it seems
+		 */
+		ether_addr_copy(type_info.ethernet.address, dev->dev_addr);
+		DEBUG_TRACE("%px: Net device: %px is ETHERNET, mac: %pM\n",
+				feci, dev, type_info.ethernet.address);
+
+		/*
+		 * Establish this type of interface
+		 */
+		ii = ecm_interface_ethernet_interface_establish(&type_info.ethernet, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+
+identifier_update:
+		if (ii) {
+			/*
+			 * An interface identifier/ifindex can be change after network restart. Below
+			 * functtion will check interface_identifier present in 'ii' with new dev_interface_num.
+			 * If differ then update new ifindex and update the interface identifier hash table.
+			 */
+			ecm_db_iface_identifier_hash_table_entry_check_and_update(ii, dev_interface_num);
+		}
+
+		return ii;
+	}
+
+	/*
+	 * LOOPBACK?
+	 */
+	if (dev_type == ARPHRD_LOOPBACK) {
+		DEBUG_TRACE("%px: Net device: %px is LOOPBACK type: %d\n", feci, dev, dev_type);
+		type_info.loopback.os_specific_ident = dev_interface_num;
+		ii = ecm_interface_loopback_interface_establish(&type_info.loopback, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+		return ii;
+	}
+
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+	/*
+	 * IPSEC?
+	 */
+	if (dev_type == ECM_ARPHRD_IPSEC_TUNNEL_TYPE) {
+
+#ifdef ECM_INTERFACE_IPSEC_GLUE_LAYER_SUPPORT_ENABLE
+		struct net_device *ipsec_dev;
+		ip_addr_t saddr, daddr;
+
+		DEBUG_TRACE("Net device: %px is IPSec tunnel type: %d\n", dev, dev_type);
+
+		ipsec_dev = ecm_interface_get_and_hold_ipsec_tun_netdev(dev, skb, &interface_type);
+		if (!ipsec_dev) {
+			DEBUG_WARN("Failed to find NSS IPSec dev for: %s and type: %d\n", dev->name, dev_type);
+			return NULL;
+		}
+
+		ae_interface_num = feci->ae_interface_number_by_dev_type_get(ipsec_dev, interface_type);
+		if (ae_interface_num < 0) {
+			DEBUG_TRACE("IPSec interface %s is not ready yet\n", ipsec_dev->name);
+			dev_put(ipsec_dev);
+			return NULL;
+		}
+		dev_put(ipsec_dev);
+
+		/*
+		 * Copy IP addresses from skb
+		 */
+		if (ip_hdr(skb)->version == IPVERSION) {
+			ECM_NIN4_ADDR_TO_IP_ADDR(saddr, ip_hdr(skb)->saddr);
+			ECM_NIN4_ADDR_TO_IP_ADDR(daddr, ip_hdr(skb)->daddr);
+		} else {
+			ECM_NIN6_ADDR_TO_IP_ADDR(saddr, ipv6_hdr(skb)->saddr);
+			ECM_NIN6_ADDR_TO_IP_ADDR(daddr, ipv6_hdr(skb)->daddr);
+		}
+
+		ecm_interface_tunnel_mtu_update(saddr, daddr, ECM_DB_IFACE_TYPE_IPSEC_TUNNEL, &dev_mtu);
+#endif
+		type_info.ipsec_tunnel.os_specific_ident = dev_interface_num;
+
+		/*
+		 * Override the MTU size in the decap direction in case of IPSec tunnel.
+		 * This will apply to IPsec->WAN rule.
+		 * TODO: Move this override to accelerate function.
+		 */
+		if (ip_hdr(skb)->version == IPVERSION) {
+			if ((ip_hdr(skb)->protocol == IPPROTO_ESP) ||
+			    ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
+			     (udp_hdr(skb)->dest == htons(4500)))) {
+				dev_mtu = ECM_DB_IFACE_MTU_MAX;
+			}
+		} else {
+			if (ipv6_hdr(skb)->nexthdr == IPPROTO_ESP) {
+				dev_mtu = ECM_DB_IFACE_MTU_MAX;
+			}
+		}
+
+		ii = ecm_interface_ipsec_tunnel_interface_establish(&type_info.ipsec_tunnel, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+		if (ii) {
+			ecm_db_iface_identifier_hash_table_entry_check_and_update(ii, dev_interface_num);
+		}
+		return ii;
+	}
+#endif
+
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+	if (dev_type == ARPHRD_NONE) {
+		if (is_map_t_dev(dev)) {
+			type_info.map_t.if_index = dev_interface_num;
+			interface_type = feci->ae_interface_type_get(feci, dev);
+			ae_interface_num = feci->ae_interface_number_by_dev_type_get(dev, interface_type);
+
+			if (ae_interface_num < 0) {
+				DEBUG_TRACE("%px: MAP-T interface is not ready yet\n", feci);
+				return NULL;
+			}
+
+			ii = ecm_interface_map_t_interface_establish(&type_info.map_t, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+			return ii;
+		}
+
+	}
+#endif
+
+#ifdef ECM_INTERFACE_SIT_ENABLE
+#ifdef CONFIG_IPV6_SIT_6RD
+	/*
+	 * SIT (6-in-4)?
+	 */
+	if (dev_type == ARPHRD_SIT) {
+		struct ip_tunnel *tunnel;
+		struct ip_tunnel_6rd_parm *ip6rd;
+		const struct iphdr  *tiph;
+
+		DEBUG_TRACE("%px: Net device: %px is SIT (6-in-4) type: %d\n", feci, dev, dev_type);
+
+		tunnel = (struct ip_tunnel*)netdev_priv(dev);
+		ip6rd =  &tunnel->ip6rd;
+
+		/*
+		 * Get the Tunnel device IP header info
+		 */
+		tiph = &tunnel->parms.iph ;
+
+		ECM_NIN4_ADDR_TO_IP_ADDR(type_info.sit.saddr, tiph->saddr);
+		ECM_NIN4_ADDR_TO_IP_ADDR(type_info.sit.daddr, tiph->daddr);
+		type_info.sit.ttl = tiph->ttl;
+		type_info.sit.tos = tiph->tos;
+
+		interface_type = feci->ae_interface_type_get(feci, dev);
+		ae_interface_num = feci->ae_interface_number_by_dev_type_get(dev, interface_type);
+
+		ii = ecm_interface_sit_interface_establish(&type_info.sit, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+		return ii;
+	}
+#endif
+#endif
+
+#ifdef ECM_INTERFACE_TUNIPIP6_ENABLE
+#ifdef ECM_IPV6_ENABLE
+	/*
+	 * IPIP6 Tunnel?
+	 */
+	if (dev_type == ARPHRD_TUNNEL6) {
+		struct ip6_tnl *tunnel;
+		struct flowi6 *fl6;
+
+		DEBUG_TRACE("%px: Net device: %px is TUNIPIP6 type: %d\n", feci, dev, dev_type);
+
+		/*
+		 * Get the tunnel device flow information (discover the output path of the tunnel)
+		 */
+		tunnel = (struct ip6_tnl *)netdev_priv(dev);
+		fl6 = &tunnel->fl.u.ip6;
+
+		ECM_NIN6_ADDR_TO_IP_ADDR(type_info.tunipip6.saddr, fl6->saddr);
+		ECM_NIN6_ADDR_TO_IP_ADDR(type_info.tunipip6.daddr, fl6->daddr);
+		type_info.tunipip6.hop_limit = tunnel->parms.hop_limit;
+		type_info.tunipip6.flags = ntohl(tunnel->parms.flags);
+		type_info.tunipip6.flowlabel = fl6->flowlabel;  /* flow Label In kernel is stored in big endian format */
+
+		interface_type = feci->ae_interface_type_get(feci, dev);
+		ae_interface_num = feci->ae_interface_number_by_dev_type_get(dev, interface_type);
+
+		if (ae_interface_num < 0) {
+			DEBUG_TRACE("%px: TUNIPIP6 interface is not ready yet\n", feci);
+			return NULL;
+		}
+
+		ii = ecm_interface_tunipip6_interface_establish(&type_info.tunipip6, dev_name,
+								dev_interface_num, ae_interface_num, dev_mtu);
+		return ii;
+	}
+#endif
+#endif
+
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+	if ((dev_type == ARPHRD_IPGRE) || (dev_type == ARPHRD_IP6GRE)) {
+		type_info.gre_tun.if_index = dev_interface_num;
+		if (dev_type == ARPHRD_IPGRE) {
+			gre4_tunnel = netdev_priv(dev);
+			if (!gre4_tunnel) {
+				DEBUG_WARN("%px: failed to obtain node address for host. GREv4 tunnel not ready\n", feci);
+				return NULL;
+			}
+			ECM_NIN4_ADDR_TO_IP_ADDR(type_info.gre_tun.local_ip, gre4_tunnel->parms.iph.saddr);
+			ECM_NIN4_ADDR_TO_IP_ADDR(type_info.gre_tun.remote_ip, gre4_tunnel->parms.iph.daddr);
+		} else {
+			gre6_tunnel = netdev_priv(dev);
+			if (!gre6_tunnel) {
+				DEBUG_WARN("%px: failed to obtain node address for host. GREv6 tunnel not ready\n", feci);
+				return NULL;
+			}
+			ECM_NIN6_ADDR_TO_IP_ADDR(type_info.gre_tun.local_ip, gre6_tunnel->parms.laddr);
+			ECM_NIN6_ADDR_TO_IP_ADDR(type_info.gre_tun.remote_ip, gre6_tunnel->parms.raddr);
+		}
+
+		interface_type = feci->ae_interface_type_get(feci, dev);
+		ae_interface_num = feci->ae_interface_number_by_dev_type_get(dev, interface_type);
+		if (ae_interface_num < 0) {
+			DEBUG_TRACE("%px: GRE TUN interface is not ready yet. Interface type: %d\n", feci, interface_type);
+			return NULL;
+		}
+
+		ii = ecm_interface_gre_tun_interface_establish(&type_info.gre_tun, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+		if (ii) {
+			/*
+			 * The ifindex of a virtual netdevice like a GRE tunnel session can change if it is destroyed
+			 * and comes up again. Detect if the ifindex has changed and update it if required
+			 */
+			ecm_db_iface_identifier_hash_table_entry_check_and_update(ii, dev_interface_num);
+		}
+		return ii;
+	}
+#endif
+
+#ifdef ECM_INTERFACE_RAWIP_ENABLE
+	/*
+	 * RAWIP type?
+	 */
+	if (dev_type == ARPHRD_RAWIP) {
+		/*
+		 * Copy netdev address to the type info.
+		 */
+		ether_addr_copy(type_info.rawip.address, dev->dev_addr);
+                DEBUG_TRACE("%px: Net device: %px is RAWIP, MAC addr: %pM\n",
+                               feci, dev, type_info.rawip.address);
+
+                /*
+                 * Establish this type of interface
+                 */
+                ii = ecm_interface_rawip_interface_establish(&type_info.rawip, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+		return ii;
+	}
+#endif
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+	/*
+	 * OVPN Tunnel?
+	 */
+	if ((dev_type == ARPHRD_NONE) && (dev->priv_flags_ext & IFF_EXT_TUN_TAP)) {
+		struct net_device *tun_dev = NULL;
+		ip_addr_t saddr, daddr;
+
+		DEBUG_TRACE("Net device: %px is OVPN type: %d\n", dev, dev_type);
+
+		ae_interface_num = ecm_interface_ovpn_get_ifnum(dev, skb, &tun_dev);
+		if ((ae_interface_num <= 0) || !tun_dev) {
+			DEBUG_WARN("%px: Couldn't get OVPN acceleration interface number\n", dev);
+			return NULL;
+		}
+
+		type_info.ovpn.tun_ifnum = ae_interface_num;
+
+		/*
+		 * Copy IP addresses from skb
+		 */
+		if (ip_hdr(skb)->version == IPVERSION) {
+			ECM_NIN4_ADDR_TO_IP_ADDR(saddr, ip_hdr(skb)->saddr);
+			ECM_NIN4_ADDR_TO_IP_ADDR(daddr, ip_hdr(skb)->daddr);
+		} else {
+			ECM_NIN6_ADDR_TO_IP_ADDR(saddr, ipv6_hdr(skb)->saddr);
+			ECM_NIN6_ADDR_TO_IP_ADDR(daddr, ipv6_hdr(skb)->daddr);
+		}
+
+		ecm_interface_tunnel_mtu_update(saddr, daddr, ECM_DB_IFACE_TYPE_OVPN, &dev_mtu);
+		ii = ecm_interface_ovpn_interface_establish(&type_info.ovpn, tun_dev->name, tun_dev->ifindex, dev_mtu);
+		return ii;
+	}
+#endif
+	/*
+	 * If this is NOT PPP then it is unknown to the ecm
+	 */
+	if (dev_type != ARPHRD_PPP) {
+		DEBUG_TRACE("%px: Net device: %px is UNKNOWN type: %d\n", feci, dev, dev_type);
+		type_info.unknown.os_specific_ident = dev_interface_num;
+
+		/*
+		 * Establish this type of interface
+		 */
+		ii = ecm_interface_unknown_interface_establish(&type_info.unknown, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+		return ii;
+	}
+
+#ifndef ECM_INTERFACE_PPP_ENABLE
+	/*
+	 * PPP Support is NOT provided for.
+	 * Interface is therefore unknown
+	 */
+	DEBUG_TRACE("%px: Net device: %px is UNKNOWN (PPP Unsupported) type: %d\n", feci, dev, dev_type);
+	type_info.unknown.os_specific_ident = dev_interface_num;
+
+	/*
+	 * Establish this type of interface
+	 */
+	ii = ecm_interface_unknown_interface_establish(&type_info.unknown, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+	return ii;
+#else
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+	/*
+	 * ppp_xmit lock is held by linux kernel for l2tp packet in transmit
+	 * direction. we need to check for l2tp packet and avoid calls to
+	 * ppp_is_multilink() and ppp_hold_channels() which acquire same lock
+	 */
+
+	if ((dev->priv_flags_ext & IFF_EXT_PPP_L2TPV2) && ppp_is_xmit_locked(dev)) {
+		if (skb && (skb->skb_iif == dev->ifindex)) {
+			struct pppol2tp_common_addr info;
+
+			if (__ppp_is_multilink(dev) > 0) {
+				DEBUG_TRACE("%px: Net device: %px is MULTILINK PPP - Unknown to the ECM\n", feci, dev);
+				type_info.unknown.os_specific_ident = dev_interface_num;
+
+				/*
+				 * Establish this type of interface
+				 */
+				ii = ecm_interface_unknown_interface_establish(&type_info.unknown, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+				return ii;
+			}
+			channel_count = __ppp_hold_channels(dev, ppp_chan, 1);
+			if (channel_count != 1) {
+				DEBUG_TRACE("%px: Net device: %px PPP has %d channels - ECM cannot handle this (interface becomes Unknown type)\n",
+					    feci, dev, channel_count);
+				type_info.unknown.os_specific_ident = dev_interface_num;
+
+				/*
+				 * Establish this type of interface
+				 */
+				ii = ecm_interface_unknown_interface_establish(&type_info.unknown, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+				return ii;
+			}
+
+			if (pppol2tp_channel_addressing_get(ppp_chan[0], &info)) {
+				ppp_release_channels(ppp_chan, 1);
+				return NULL;
+			}
+
+			type_info.pppol2tpv2.l2tp.tunnel.tunnel_id = info.local_tunnel_id;
+			type_info.pppol2tpv2.l2tp.tunnel.peer_tunnel_id = info.remote_tunnel_id;
+			type_info.pppol2tpv2.l2tp.session.session_id = info.local_session_id;
+			type_info.pppol2tpv2.l2tp.session.peer_session_id = info.remote_session_id;
+			type_info.pppol2tpv2.udp.sport = ntohs(info.local_addr.sin_port);
+			type_info.pppol2tpv2.udp.dport = ntohs(info.remote_addr.sin_port);
+			type_info.pppol2tpv2.ip.saddr = ntohl(info.local_addr.sin_addr.s_addr);
+			type_info.pppol2tpv2.ip.daddr = ntohl(info.remote_addr.sin_addr.s_addr);
+
+			/*
+			 * Release the channel.  Note that next_dev is still (correctly) held.
+			 */
+			ppp_release_channels(ppp_chan, 1);
+
+			DEBUG_TRACE("%px: Net device: %px PPPo2L2TP session: %d,n", feci, dev, type_info.pppol2tpv2.l2tp.session.peer_session_id);
+
+			/*
+			 * Establish this type of interface
+			 */
+			ii = ecm_interface_pppol2tpv2_interface_establish(&type_info.pppol2tpv2, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+			return ii;
+		}
+	}
+#endif
+
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+	if ((protocol == IPPROTO_GRE) && skb && v4_hdr && (dev->priv_flags_ext & IFF_EXT_PPP_PPTP)) {
+		struct gre_base_hdr *gre_hdr;
+		uint16_t proto;
+		int ret;
+
+		skb_pull(skb, sizeof(struct iphdr));
+		gre_hdr = (struct gre_base_hdr *)(skb->data);
+		proto = ntohs(gre_hdr->protocol);
+		if ((gre_hdr->flags & GRE_VERSION) == ECM_GRE_VERSION_1) {
+			ecm_gre_hdr_pptp *hdr = (ecm_gre_hdr_pptp *)gre_hdr;
+
+			ret = pptp_session_find(&opt, hdr->call_id, v4_hdr->daddr);
+			if (ret < 0) {
+				skb_push(skb, sizeof(struct iphdr));
+				DEBUG_WARN("%px: PPTP session info not found\n", feci);
+				return NULL;
+			}
+
+			/*
+			 * Get PPTP session info
+			 */
+			type_info.pptp.src_call_id = opt.src_addr.call_id;
+			type_info.pptp.dst_call_id = opt.dst_addr.call_id;
+			type_info.pptp.src_ip = ntohl(opt.src_addr.sin_addr.s_addr);
+			type_info.pptp.dst_ip = ntohl(opt.dst_addr.sin_addr.s_addr);
+
+			skb_push(skb, sizeof(struct iphdr));
+
+			interface_type = feci->ae_interface_type_get(feci, dev);
+			ae_interface_num = feci->ae_interface_number_by_dev_type_get(dev, interface_type);
+
+			/*
+			 * Establish this type of interface
+			 */
+			ii = ecm_interface_pptp_interface_establish(&type_info.pptp, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+			if (ii) {
+				/*
+				 * The ifindex of a virtual netdevice like a PPTP session can change if it is destroyed
+				 * and comes up again. Detect if the ifindex has changed and update it if required
+				 */
+				ecm_db_iface_identifier_hash_table_entry_check_and_update(ii, dev_interface_num);
+			}
+			return ii;
+		}
+
+		skb_push(skb, sizeof(struct iphdr));
+
+		DEBUG_TRACE("%px: Unknown GRE protocol\n", feci);
+		type_info.unknown.os_specific_ident = dev_interface_num;
+
+		/*
+		 * Establish this type of interface
+		 */
+		ii = ecm_interface_unknown_interface_establish(&type_info.unknown, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+		return ii;
+	}
+#endif
+	/*
+	 * PPP - but what is the channel type?
+	 * First: If this is multi-link then we do not support it
+	 */
+	if (ppp_is_multilink(dev) > 0) {
+		DEBUG_TRACE("%px: Net device: %px is MULTILINK PPP - Unknown to the ECM\n", feci, dev);
+		type_info.unknown.os_specific_ident = dev_interface_num;
+
+		/*
+		 * Establish this type of interface
+		 */
+		ii = ecm_interface_unknown_interface_establish(&type_info.unknown, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+		return ii;
+	}
+
+	DEBUG_TRACE("%px: Net device: %px is PPP\n", feci, dev);
+
+	/*
+	 * Get the PPP channel and then enquire what kind of channel it is
+	 * NOTE: Not multilink so only one channel to get.
+	 */
+	channel_count = ppp_hold_channels(dev, ppp_chan, 1);
+	if (channel_count != 1) {
+		DEBUG_TRACE("%px: Net device: %px PPP has %d channels - ECM cannot handle this (interface becomes Unknown type)\n",
+				feci, dev, channel_count);
+		type_info.unknown.os_specific_ident = dev_interface_num;
+
+		/*
+		 * Establish this type of interface
+		 */
+		ii = ecm_interface_unknown_interface_establish(&type_info.unknown, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+		return ii;
+	}
+
+	/*
+	 * Get channel protocol type
+	 * NOTE: Not all PPP channels support channel specific methods.
+	 */
+	channel_protocol = ppp_channel_get_protocol(ppp_chan[0]);
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+	if (channel_protocol == PX_PROTO_OL2TP) {
+		struct pppol2tp_common_addr info;
+
+		if (pppol2tp_channel_addressing_get(ppp_chan[0], &info)) {
+			ppp_release_channels(ppp_chan, 1);
+			return NULL;
+		}
+
+		type_info.pppol2tpv2.l2tp.tunnel.tunnel_id = info.local_tunnel_id;
+		type_info.pppol2tpv2.l2tp.tunnel.peer_tunnel_id = info.remote_tunnel_id;
+		type_info.pppol2tpv2.l2tp.session.session_id = info.local_session_id;
+		type_info.pppol2tpv2.l2tp.session.peer_session_id = info.remote_session_id;
+		type_info.pppol2tpv2.udp.sport = ntohs(info.local_addr.sin_port);
+		type_info.pppol2tpv2.udp.dport = ntohs(info.remote_addr.sin_port);
+		type_info.pppol2tpv2.ip.saddr = ntohl(info.local_addr.sin_addr.s_addr);
+		type_info.pppol2tpv2.ip.daddr = ntohl(info.remote_addr.sin_addr.s_addr);
+
+		/*
+		 * Release the channel.  Note that next_dev is still (correctly) held.
+		 */
+		ppp_release_channels(ppp_chan, 1);
+
+		DEBUG_TRACE("%px: Net device: %px PPPo2L2TP session: %d,n", feci, dev, type_info.pppol2tpv2.l2tp.session.peer_session_id);
+
+		/*
+		 * Establish this type of interface
+		 */
+		ii = ecm_interface_pppol2tpv2_interface_establish(&type_info.pppol2tpv2, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+		return ii;
+	}
+#endif
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+	if (channel_protocol == PX_PROTO_OE) {
+		struct pppoe_opt addressing;
+
+		/*
+		 * PPPoE channel
+		 */
+		DEBUG_TRACE("%px: Net device: %px PPP channel is PPPoE\n", feci, dev);
+
+		/*
+		 * Get PPPoE session information and the underlying device it is using.
+		 */
+		if (pppoe_channel_addressing_get(ppp_chan[0], &addressing)) {
+			DEBUG_WARN("%px: failed to get PPPoE addressing info\n", feci);
+			ppp_release_channels(ppp_chan, 1);
+			return NULL;
+		}
+
+		type_info.pppoe.pppoe_session_id = (uint16_t)ntohs((uint16_t)addressing.pa.sid);
+		memcpy(type_info.pppoe.remote_mac, addressing.pa.remote, ETH_ALEN);
+		dev_put(addressing.dev);
+
+		/*
+		 * Release the channel.  Note that next_dev is still (correctly) held.
+		 */
+		ppp_release_channels(ppp_chan, 1);
+
+		DEBUG_TRACE("%px: Net device: %px PPPoE session: %x, remote mac: %pM\n",
+			    feci, dev, type_info.pppoe.pppoe_session_id, type_info.pppoe.remote_mac);
+
+		/*
+		 * Establish this type of interface
+		 */
+		ii = ecm_interface_pppoe_interface_establish(&type_info.pppoe, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+		return ii;
+	}
+#endif
+
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+	if (channel_protocol == PX_PROTO_PPTP) {
+
+		pptp_channel_addressing_get(&opt, ppp_chan[0]);
+
+		/*
+		 * Get PPTP session info
+		 */
+		type_info.pptp.src_call_id = opt.src_addr.call_id;
+		type_info.pptp.dst_call_id = opt.dst_addr.call_id;
+		type_info.pptp.src_ip = ntohl(opt.src_addr.sin_addr.s_addr);
+		type_info.pptp.dst_ip = ntohl(opt.dst_addr.sin_addr.s_addr);
+
+		DEBUG_TRACE("%px: Net device: %px PPTP source call id: %d\n", feci, dev, type_info.pptp.src_call_id);
+		ppp_release_channels(ppp_chan, 1);
+
+		interface_type = feci->ae_interface_type_get(feci, dev);
+		ae_interface_num = feci->ae_interface_number_by_dev_type_get(dev, interface_type);
+
+		/*
+		 * Establish this type of interface
+		 */
+		ii = ecm_interface_pptp_interface_establish(&type_info.pptp, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+		if (ii) {
+			/*
+			 * The ifindex of a virtual netdevice like a PPTP session can change if it is destroyed
+			 * and comes up again. Detect if the ifindex has changed and update it if required
+			 */
+			ecm_db_iface_identifier_hash_table_entry_check_and_update(ii, dev_interface_num);
+		}
+		return ii;
+	}
+#endif
+	DEBUG_TRACE("%px: Net device: %px PPP channel protocol: %d - Unknown to the ECM\n", feci, dev, channel_protocol);
+	type_info.unknown.os_specific_ident = dev_interface_num;
+
+	/*
+	 * Release the channel
+	 */
+	ppp_release_channels(ppp_chan, 1);
+
+	/*
+	 * Establish this type of interface
+	 */
+	ii = ecm_interface_unknown_interface_establish(&type_info.unknown, dev_name, dev_interface_num, ae_interface_num, dev_mtu);
+	return ii;
+#endif
+}
+EXPORT_SYMBOL(ecm_interface_establish_and_ref);
+
+#ifdef ECM_MULTICAST_ENABLE
+/*
+ * ecm_interface_multicast_heirarchy_construct_single()
+ * 	Create and return an interface heirarchy for a single interface for a multicast connection
+ *
+ * 	src_addr	IP source address
+ * 	dest_addr	IP Destination address/Group Address
+ * 	interface	Pointer to a single multicast interface heirarchy
+ *	given_dest_dev	Netdev pointer for destination interface
+ *	br_slave_dev	Netdev pointer to a bridge slave device. It could be NULL in case of pure
+ *			routed flow without any bridge interface in destination dev list.
+ *	skb             sk_buff
+ */
+static uint32_t ecm_interface_multicast_heirarchy_construct_single(struct ecm_front_end_connection_instance *feci, ip_addr_t src_addr,
+								   ip_addr_t dest_addr, struct ecm_db_iface_instance *interface,
+								   struct net_device *given_dest_dev, struct net_device *br_slave_dev,
+								   uint8_t *src_node_addr, bool is_routed, __be16 *layer4hdr, struct sk_buff *skb)
+{
+	struct ecm_db_iface_instance *to_list_single[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance **ifaces;
+	struct ecm_db_iface_instance *ii_temp;
+	struct net_device *dest_dev;
+	int32_t current_interface_index;
+	int32_t interfaces_cnt = 0;
+        int32_t dest_dev_type;
+
+	dest_dev = given_dest_dev;
+	dev_hold(dest_dev);
+	dest_dev_type = dest_dev->type;
+	current_interface_index = ECM_DB_IFACE_HEIRARCHY_MAX;
+
+	while (current_interface_index > 0) {
+		struct ecm_db_iface_instance *ii;
+		struct net_device *next_dev;
+
+		/*
+		 * Get the ecm db interface instance for the device at hand
+		 */
+		ii = ecm_interface_establish_and_ref(feci, dest_dev, skb);
+		interfaces_cnt++;
+
+		/*
+		 * If the interface could not be established then we abort
+		 */
+		if (!ii) {
+			DEBUG_WARN("Failed to establish interface: %px, name: %s\n", dest_dev, dest_dev->name);
+			goto fail;
+		}
+
+		/*
+		 * Record the interface instance into the *ifaces
+		 */
+		current_interface_index--;
+		ii_temp = ecm_db_multicast_if_instance_get_at_index(interface, current_interface_index);
+		ifaces = (struct ecm_db_iface_instance **)ii_temp;
+		*ifaces = ii;
+
+		/*
+		 * Now we have to figure out what the next device will be (in the transmission path)
+		 */
+		do {
+#ifdef ECM_INTERFACE_PPP_ENABLE
+			int channel_count;
+			struct ppp_channel *ppp_chan[1];
+			int channel_protocol;
+			struct pppoe_opt addressing;
+#endif
+			DEBUG_TRACE("Net device: %px is type: %d, name: %s\n", dest_dev, dest_dev_type, dest_dev->name);
+			next_dev = NULL;
+
+			if (dest_dev_type == ARPHRD_ETHER) {
+				/*
+				 * Ethernet - but what sub type?
+				 */
+
+				/*
+				 * VLAN?
+				 */
+				if (is_vlan_dev(dest_dev)) {
+					/*
+					 * VLAN master
+					 * No locking needed here, ASSUMPTION is that real_dev is held for as long as we have dev.
+					 */
+					next_dev = ecm_interface_vlan_real_dev(dest_dev);
+					dev_hold(next_dev);
+					DEBUG_TRACE("Net device: %px is VLAN, slave dev: %px (%s)\n",
+							dest_dev, next_dev, next_dev->name);
+					break;
+				}
+
+				/*
+				 * LINUX_BRIDGE/OVS_BRIDGE?
+				 */
+				if (ecm_front_end_is_bridge_device(dest_dev)
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+					|| ecm_front_end_is_ovs_bridge_device(dest_dev)
+#endif
+				   ) {
+					if (!br_slave_dev) {
+						goto fail;
+					}
+
+					if (!ecm_front_end_is_bridge_port(br_slave_dev)
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+					&& !ecm_interface_is_ovs_bridge_port(br_slave_dev)
+#endif
+					) {
+						DEBUG_ASSERT(NULL, "%px: expected only bridge slave here\n", interface);
+						goto fail;
+					}
+
+					next_dev = br_slave_dev;
+					DEBUG_TRACE("Net device: %px is BRIDGE, next_dev: %px (%s)\n", dest_dev, next_dev, next_dev->name);
+					dev_hold(next_dev);
+					break;
+				}
+
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+				/*
+				 * MAC-VLAN?
+				 */
+				if (netif_is_macvlan(dest_dev)) {
+					if (ecm_interface_macvlan_mode_is_valid(dest_dev)) {
+						next_dev = macvlan_dev_real_dev(dest_dev);
+						dev_hold(next_dev);
+						DEBUG_TRACE("%px: Net device: %px is MAC-VLAN, slave dev: %px (%s)\n",
+								feci, dest_dev, next_dev, next_dev->name);
+						break;
+					}
+				}
+#endif
+
+#ifdef ECM_INTERFACE_BOND_ENABLE
+				/*
+				 * LAG?
+				 */
+				if (ecm_front_end_is_lag_master(dest_dev)) {
+					/*
+					 * Link aggregation
+					 * Figure out which slave device of the link aggregation will be used to reach the destination.
+					 */
+					uint32_t src_addr_32 = 0;
+					uint32_t dest_addr_32 = 0;
+					struct in6_addr src_addr6;
+					struct in6_addr dest_addr6;
+					uint8_t src_mac_addr[ETH_ALEN];
+					uint8_t dest_mac_addr[ETH_ALEN];
+
+					memset(src_mac_addr, 0, ETH_ALEN);
+					memset(dest_mac_addr, 0, ETH_ALEN);
+
+					if (ECM_IP_ADDR_IS_V4(src_addr)) {
+						ECM_IP_ADDR_TO_NIN4_ADDR(src_addr_32, src_addr);
+						ECM_IP_ADDR_TO_NIN4_ADDR(dest_addr_32, dest_addr);
+					}
+
+					if (!is_routed) {
+						memcpy(src_mac_addr, src_node_addr, ETH_ALEN);
+					} else {
+						struct net_device *dest_dev_master;
+
+						/*
+						 * Use appropriate source MAC address for routed packets
+						 */
+						dest_dev_master = ecm_interface_get_and_hold_dev_master(dest_dev);
+						if (dest_dev_master) {
+							memcpy(src_mac_addr, dest_dev_master->dev_addr, ETH_ALEN);
+							dev_put(dest_dev_master);
+						} else {
+							memcpy(src_mac_addr, dest_dev->dev_addr, ETH_ALEN);
+						}
+					}
+
+					/*
+					 * Create Destination MAC address using IP multicast destination address
+					 */
+					ecm_translate_multicast_mac(dest_addr, dest_mac_addr);
+
+					if (ECM_IP_ADDR_IS_V4(src_addr)) {
+						next_dev = bond_get_tx_dev(NULL, src_mac_addr, dest_mac_addr,
+									   &src_addr_32, &dest_addr_32,
+									   htons((uint16_t)ETH_P_IP), dest_dev, layer4hdr);
+					} else {
+						ECM_IP_ADDR_TO_NIN6_ADDR(src_addr6, src_addr);
+						ECM_IP_ADDR_TO_NIN6_ADDR(dest_addr6, dest_addr);
+						next_dev = bond_get_tx_dev(NULL, src_mac_addr, dest_mac_addr,
+									   src_addr6.s6_addr, dest_addr6.s6_addr,
+									   htons((uint16_t)ETH_P_IPV6), dest_dev, layer4hdr);
+					}
+
+					if (!(next_dev && netif_carrier_ok(next_dev))) {
+						DEBUG_WARN("Unable to obtain LAG output slave device\n");
+						goto fail;
+					}
+
+					dev_hold(next_dev);
+					DEBUG_TRACE("Net device: %px is LAG, slave dev: %px (%s)\n", dest_dev, next_dev, next_dev->name);
+					break;
+				}
+#endif
+
+				/*
+				 * ETHERNET!
+				 * Just plain ethernet it seems.
+				 */
+				DEBUG_TRACE("Net device: %px is ETHERNET\n", dest_dev);
+				break;
+			}
+
+			/*
+			 * LOOPBACK?
+			 */
+			if (dest_dev_type == ARPHRD_LOOPBACK) {
+				DEBUG_TRACE("Net device: %px is LOOPBACK type: %d\n", dest_dev, dest_dev_type);
+				break;
+			}
+
+			/*
+			 * IPSEC?
+			 */
+			if (dest_dev_type == ECM_ARPHRD_IPSEC_TUNNEL_TYPE) {
+				DEBUG_TRACE("Net device: %px is IPSec tunnel type: %d\n", dest_dev, dest_dev_type);
+				/*
+				 * TODO Figure out the next device the tunnel is using...
+				 */
+				break;
+			}
+
+			/*
+			 * SIT (6-in-4)?
+			 */
+			if (dest_dev_type == ARPHRD_SIT) {
+				DEBUG_TRACE("Net device: %px is SIT (6-in-4) type: %d\n", dest_dev, dest_dev_type);
+				/*
+				 * TODO Figure out the next device the tunnel is using...
+				 */
+				break;
+			}
+
+			/*
+			 * IPIP6 Tunnel?
+			 */
+			if (dest_dev_type == ARPHRD_TUNNEL6) {
+				DEBUG_TRACE("Net device: %px is TUNIPIP6 type: %d\n", dest_dev, dest_dev_type);
+				/*
+				 * TODO Figure out the next device the tunnel is using...
+				 */
+				break;
+			}
+
+			/*
+			 * If this is NOT PPP then it is unknown to the ecm and we cannot figure out it's next device.
+			 */
+			if (dest_dev_type != ARPHRD_PPP) {
+				DEBUG_TRACE("Net device: %px is UNKNOWN type: %d\n", dest_dev, dest_dev_type);
+				break;
+			}
+
+#ifndef ECM_INTERFACE_PPP_ENABLE
+			DEBUG_TRACE("Net device: %px is UNKNOWN (PPP Unsupported) type: %d\n", dest_dev, dest_dev_type);
+#else
+			/*
+			 * PPP - but what is the channel type?
+			 * First: If this is multi-link then we do not support it
+			 */
+			if (ppp_is_multilink(dest_dev) > 0) {
+				DEBUG_TRACE("Net device: %px is MULTILINK PPP - Unknown to the ECM\n", dest_dev);
+				break;
+			}
+
+			DEBUG_TRACE("Net device: %px is PPP\n", dest_dev);
+
+			/*
+			 * Get the PPP channel and then enquire what kind of channel it is
+			 * NOTE: Not multilink so only one channel to get.
+			 */
+			channel_count = ppp_hold_channels(dest_dev, ppp_chan, 1);
+			if (channel_count != 1) {
+				DEBUG_TRACE("Net device: %px PPP has %d channels - Unknown to the ECM\n",
+						dest_dev, channel_count);
+				break;
+			}
+
+			/*
+			 * Get channel protocol type
+			 * NOTE: Not all PPP channels support channel specific methods.
+			 */
+			channel_protocol = ppp_channel_get_protocol(ppp_chan[0]);
+			if (channel_protocol != PX_PROTO_OE) {
+				DEBUG_TRACE("Net device: %px PPP channel protocol: %d - Unknown to the ECM\n",
+						dest_dev, channel_protocol);
+
+				/*
+				 * Release the channel
+				 */
+				ppp_release_channels(ppp_chan, 1);
+
+				break;
+			}
+
+			/*
+			 * PPPoE channel
+			 */
+			DEBUG_TRACE("Net device: %px PPP channel is PPPoE\n", dest_dev);
+
+			/*
+			 * Get PPPoE session information and the underlying device it is using.
+			 */
+			if (pppoe_channel_addressing_get(ppp_chan[0], &addressing)) {
+				DEBUG_WARN("%px: failed to get PPPoE addressing info\n", dest_dev);
+				ppp_release_channels(ppp_chan, 1);
+				break;
+			}
+
+			/*
+			 * Copy the dev hold into this, we will release the hold later
+			 */
+			next_dev = addressing.dev;
+
+			/*
+			 * Release the channel.  Note that next_dev is still (correctly) held.
+			 */
+			ppp_release_channels(ppp_chan, 1);
+#endif
+		} while (false);
+
+		/*
+		 * No longer need dest_dev as it may become next_dev
+		 */
+		dev_put(dest_dev);
+
+		/*
+		 * Check out the next_dev, if any
+		 */
+		if (!next_dev) {
+			int32_t i __attribute__((unused));
+			DEBUG_INFO("Completed interface heirarchy construct with first interface @: %d\n", current_interface_index);
+#if DEBUG_LEVEL > 1
+			ecm_db_multicast_copy_if_heirarchy(to_list_single, interface);
+			for (i = current_interface_index; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+				DEBUG_TRACE("\tInterface @ %d: %px, type: %d, name: %s\n", \
+						i, to_list_single[i], ecm_db_iface_type_get(to_list_single[i]), \
+						ecm_db_interface_type_to_string(ecm_db_iface_type_get(to_list_single[i])));
+			}
+#endif
+			return current_interface_index;
+		}
+
+		/*
+		 * dest_dev becomes next_dev
+		 */
+		dest_dev = next_dev;
+		dest_dev_type = dest_dev->type;
+	}
+
+fail:
+	dev_put(dest_dev);
+
+	ecm_db_multicast_copy_if_heirarchy(to_list_single, interface);
+	ecm_db_connection_interfaces_deref(to_list_single, current_interface_index);
+	return ECM_DB_IFACE_HEIRARCHY_MAX;
+}
+
+/*
+ * ecm_interface_hierarchy_delete()
+ * 	Delete hierarchy of the requested interfaces.
+ */
+static inline void ecm_interface_hierarchy_delete(struct ecm_db_iface_instance *interfaces,
+							uint32_t *interface_first_base,
+							int valid_if)
+{
+	struct ecm_db_iface_instance *to_list_single[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *ifaces;
+	int i;
+
+	for (i = 0; i < valid_if; i++) {
+		ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i);
+		ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces);
+		ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]);
+	}
+}
+
+/*
+ * ecm_interface_multicast_heirarchy_construct_routed()
+ * 	Create destination interface heirarchy for a routed multicast connectiona
+ *
+ *	interfaces	Pointer to the 2-D array of multicast interface heirarchies
+ *	in_dev		Pointer to the source netdev
+ *	packet_src_addr	Source IP of the multicast flow
+ *	packet_dest_addr Group(dest) IP of the multicast flow
+ *	max_dst		Maximum number of netdev joined the multicast group
+ *	dst_if_index_base An array of if index joined the multicast group
+ *	interface_first_base An array of the index of the first interface in the list
+ */
+int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_connection_instance *feci,
+								struct ecm_db_iface_instance *interfaces,
+								struct net_device *in_dev,
+								ip_addr_t packet_src_addr,
+								ip_addr_t packet_dest_addr, uint8_t max_if,
+								uint32_t *dst_if_index_base,
+								uint32_t *interface_first_base, bool mfc_update,
+								__be16 *layer4hdr, struct sk_buff *skb)
+{
+	struct ecm_db_iface_instance *ifaces;
+	struct net_device *dest_dev = NULL;
+	struct net_device *br_dev_src = NULL;
+	uint32_t *dst_if_index;
+	uint32_t *interface_first;
+	uint32_t br_if;
+	uint32_t valid_if;
+	int32_t if_num;
+	int32_t dest_dev_type;
+	int if_index;
+	int ii_cnt;
+	int total_ii_count = 0;
+	bool src_dev_is_bridge = false, dest_dev_is_br_dev_src = false;
+
+	DEBUG_TRACE("Construct interface heirarchy for dest_addr: " ECM_IP_ADDR_DOT_FMT " src_addr: " ECM_IP_ADDR_DOT_FMT "total destination ifs %d\n",
+			ECM_IP_ADDR_TO_DOT(packet_dest_addr), ECM_IP_ADDR_TO_DOT(packet_src_addr), max_if);
+
+	/*
+	 * Check if the source net_dev is a bridge slave.
+	 *
+	 * TODO: We are already considering ingress bridge device and
+	 * adding it to dst_dev in ecm_nss_multicast_ipv4_connection_process().
+	 * Check if this can be removed.
+	 */
+	if (in_dev && !mfc_update) {
+		if (ecm_front_end_is_bridge_port(in_dev)
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+				|| ecm_interface_is_ovs_bridge_port(in_dev)
+#endif
+		   ) {
+			br_dev_src = ecm_interface_get_and_hold_dev_master(in_dev);
+			DEBUG_ASSERT(br_dev_src, "Expected a master\n");
+
+			/*
+			 * Source netdev is part of a bridge. First make sure that this bridge
+			 * is not already part of the dest_if list given by MFC. If not, we
+			 * include the bridge in the dest if list to check for any bridge
+			 * slaves interested in the group.
+			 */
+			if (!ecm_interface_multicast_dest_list_find_if(br_dev_src, max_if, dst_if_index_base)) {
+
+				src_dev_is_bridge = true;
+
+				/*
+				 * Increase the max_if by one. This will enable us to query MCS
+				 * for any bridge slaves that may be interested in the group.
+				 */
+				max_if++;
+			}
+		}
+	}
+
+	ii_cnt = 0;
+	br_if = if_num = 0;
+
+	/*
+	 * This loop is for creating the destination interface hierarchy list.
+	 * We take the destination interface array we got from MFC (in form of ifindex array)
+	 * as input for this.
+	 */
+	for (if_index = 0, valid_if = 0; if_index < max_if; if_index++) {
+		dst_if_index = ecm_db_multicast_if_first_get_at_index(dst_if_index_base, if_index);
+		if (*dst_if_index == ECM_INTERFACE_LOOPBACK_DEV_INDEX) {
+			continue;
+		}
+
+		dest_dev_is_br_dev_src = false;
+		dest_dev = dev_get_by_index(&init_net, *dst_if_index);
+		if (!dest_dev) {
+			if (!src_dev_is_bridge) {
+				/*
+				 * If already constructed any interface heirarchies before hitting
+				 * this error condition then Deref all interface heirarchies.
+				 */
+				if (valid_if > 0) {
+					ecm_interface_hierarchy_delete(interfaces, interface_first_base, valid_if);
+				}
+
+				goto fail1;
+			}
+
+			dest_dev = br_dev_src;
+
+			/*
+			 * In some cases when WAN interface is added to bridge and traffic is downstream,
+			 * the bridge device is part of the destination list from MFC, and at the same time
+			 * 'src_dev_is_bridge' will be true as well. In such cases we will need to release
+			 * the hold on the bridge device separately for dest_dev and br_dev_src.
+			 * Setting this flag to true indicates that this is not the case,
+			 * and that releasing the hold once is enough
+			 */
+			dest_dev_is_br_dev_src = true;
+		}
+
+		dest_dev_type = dest_dev->type;
+		if (ecm_front_end_is_bridge_device(dest_dev)
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			|| ecm_front_end_is_ovs_bridge_device(dest_dev)
+#endif
+		   ) {
+			struct net_device *mc_br_slave_dev = NULL;
+			uint32_t mc_max_dst = ECM_DB_MULTICAST_IF_MAX;
+			uint32_t mc_dst_if_index[ECM_DB_MULTICAST_IF_MAX];
+
+			if (ECM_IP_ADDR_IS_V4(packet_src_addr)) {
+				if_num = mc_bridge_ipv4_get_if(dest_dev, htonl((packet_src_addr[0])), htonl(packet_dest_addr[0]), mc_max_dst, mc_dst_if_index);
+			} else {
+#ifdef ECM_IPV6_ENABLE
+				struct in6_addr origin6;
+				struct in6_addr group6;
+				ECM_IP_ADDR_TO_NIN6_ADDR(origin6, packet_src_addr);
+				ECM_IP_ADDR_TO_NIN6_ADDR(group6, packet_dest_addr);
+				if_num = mc_bridge_ipv6_get_if(dest_dev, &origin6, &group6, mc_max_dst, mc_dst_if_index);
+#else
+				DEBUG_WARN("IPv6 support not enabled\n");
+				if_num = -1;
+#endif
+			}
+
+			if ((if_num < 0) || (if_num > ECM_DB_MULTICAST_IF_MAX)) {
+				DEBUG_WARN("MCS is not ready\n");
+
+				/*
+				 * If already constructed any interface heirarchies before hitting
+				 * this error condition then Deref all interface heirarchies.
+				 */
+				if (valid_if > 0) {
+					ecm_interface_hierarchy_delete(interfaces, interface_first_base, valid_if);
+				}
+
+				goto fail2;
+			}
+
+			if (in_dev && !mfc_update) {
+				if_num = ecm_interface_multicast_check_for_src_ifindex(mc_dst_if_index, if_num, in_dev->ifindex);
+			}
+
+			for (br_if = 0; br_if < if_num; br_if++) {
+				int total_if = valid_if + br_if;
+
+				mc_br_slave_dev = dev_get_by_index(&init_net, mc_dst_if_index[br_if]);
+				if (!mc_br_slave_dev) {
+					continue;
+				}
+
+				if (total_if > ECM_DB_MULTICAST_IF_MAX) {
+					ecm_interface_hierarchy_delete(interfaces, interface_first_base, total_if);
+					dev_put(mc_br_slave_dev);
+					goto fail2;
+				}
+
+				ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, total_if);
+				/*
+				 * Construct a single interface heirarchy of a multicast dev.
+				 */
+				ii_cnt = ecm_interface_multicast_heirarchy_construct_single(feci, packet_src_addr, packet_dest_addr, ifaces, dest_dev, mc_br_slave_dev, NULL, true, layer4hdr, skb);
+				if (ii_cnt == ECM_DB_IFACE_HEIRARCHY_MAX) {
+
+					/*
+					 * If already constructed any interface heirarchies before hitting
+					 * this error condition then Deref all interface heirarchies.
+					 */
+					if (total_if > 0) {
+						ecm_interface_hierarchy_delete(interfaces, interface_first_base, total_if);
+					}
+
+					dev_put(mc_br_slave_dev);
+					goto fail2;
+				}
+
+				interface_first = ecm_db_multicast_if_first_get_at_index(interface_first_base, total_if);
+				*interface_first = ii_cnt;
+				total_ii_count += ii_cnt;
+				dev_put(mc_br_slave_dev);
+			}
+
+			valid_if += br_if;
+		} else {
+
+			DEBUG_ASSERT(valid_if < ECM_DB_MULTICAST_IF_MAX, "Bad array index size %d\n", valid_if);
+			ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, valid_if);
+			/*
+			 * Construct a single interface heirarchy of a multicast dev.
+			 */
+			ii_cnt = ecm_interface_multicast_heirarchy_construct_single(feci, packet_src_addr, packet_dest_addr, ifaces, dest_dev, NULL, NULL, true, layer4hdr, skb);
+			if (ii_cnt == ECM_DB_IFACE_HEIRARCHY_MAX) {
+
+				/*
+				 * If already constructed any interface heirarchies before hitting
+				 * this error condition then Deref all interface heirarchies.
+				 */
+				if (valid_if > 0) {
+					ecm_interface_hierarchy_delete(interfaces, interface_first_base, valid_if);
+				}
+
+				goto fail2;
+			}
+
+			interface_first = ecm_db_multicast_if_first_get_at_index(interface_first_base, valid_if);
+			*interface_first = ii_cnt;
+			total_ii_count += ii_cnt;
+			valid_if++;
+		}
+
+		if (!dest_dev_is_br_dev_src) {
+			dev_put(dest_dev);
+		}
+	}
+
+	if (br_dev_src) {
+		dev_put(br_dev_src);
+	}
+
+	return total_ii_count;
+
+fail2:
+	if (!dest_dev_is_br_dev_src) {
+		dev_put(dest_dev);
+	}
+
+fail1:
+	if (br_dev_src) {
+		dev_put(br_dev_src);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_interface_multicast_heirarchy_construct_routed);
+
+/*
+ * ecm_interface_multicast_heirarchy_construct_bridged()
+ * 	This function called when the Hyfi bridge snooper has IGMP/IMLD updates, this function
+ * 	creates destination interface heirarchy for a bridged multicast connection.
+ *
+ *	interfaces	Pointer to the 2-D array of multicast interface heirarchies
+ *	dest_dev	Pointer to the destination dev, here dest_dev is always a bridge type
+ *	packet_src_addr	Source IP of the multicast flow
+ *	packet_dest_addr Group(dest) IP of the multicast flow
+ *	mc_max_dst	Maximum number of bridge slaves joined the multicast group
+ *	mc_dst_if_index_base An array of if index joined the multicast group
+ *	interface_first_base An array of the index of the first interface in the list
+ */
+int32_t ecm_interface_multicast_heirarchy_construct_bridged(struct ecm_front_end_connection_instance *feci,
+						     struct ecm_db_iface_instance *interfaces, struct net_device *dest_dev,
+						     ip_addr_t packet_src_addr, ip_addr_t packet_dest_addr, uint8_t mc_max_dst,
+						     int *mc_dst_if_index_base, uint32_t *interface_first_base, uint8_t *src_node_addr,
+						     __be16 *layer4hdr, struct sk_buff *skb)
+{
+	struct ecm_db_iface_instance *to_list_single[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *ifaces;
+	struct net_device *mc_br_slave_dev = NULL;
+	uint32_t *interface_first;
+	int *mc_dst_if_index;
+	int valid_if;
+	int ii_cnt = 0;
+        int br_if;
+        int total_ii_cnt = 0;
+
+	/*
+	 * Go through the newly joined interface index one by one and
+	 * create an interface heirarchy for each valid interface.
+	 */
+	for (br_if = 0, valid_if = 0; br_if < mc_max_dst; br_if++) {
+		mc_dst_if_index = (int *)ecm_db_multicast_if_num_get_at_index(mc_dst_if_index_base, br_if);
+		mc_br_slave_dev = dev_get_by_index(&init_net, *mc_dst_if_index);
+		if (!mc_br_slave_dev) {
+
+			/*
+			 * If already constructed any interface heirarchies before hitting
+			 * this error condition then Deref all interface heirarchies.
+			 */
+			if (valid_if > 0) {
+				int i;
+				for (i = 0; i < valid_if; i++) {
+					ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i);
+					ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces);
+					ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]);
+				}
+			}
+
+			/*
+			 * If valid netdev not found, Return 0
+			 */
+			return 0;
+		}
+
+		if (valid_if > ECM_DB_MULTICAST_IF_MAX) {
+			int i;
+
+			/*
+			 * If already constructed any interface heirarchies before hitting
+			 * this error condition then Deref all interface heirarchies.
+			 */
+			for (i = 0; i < valid_if; i++) {
+				ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i);
+				ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces);
+				ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]);
+			}
+
+			dev_put(mc_br_slave_dev);
+			return 0;
+		}
+
+		ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, valid_if);
+
+		/*
+		 * Construct a single interface heirarchy of a multicast dev.
+		 */
+		ii_cnt = ecm_interface_multicast_heirarchy_construct_single(feci, packet_src_addr, packet_dest_addr, ifaces, dest_dev, mc_br_slave_dev, src_node_addr, false, layer4hdr, skb);
+		if (ii_cnt == ECM_DB_IFACE_HEIRARCHY_MAX) {
+
+			/*
+			 * If already constructed any interface heirarchies before hitting
+			 * this error condition then Deref all interface heirarchies.
+			 */
+			if (valid_if > 0) {
+			int i;
+				for (i = 0; i < valid_if; i++) {
+					ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i);
+					ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces);
+					ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]);
+				}
+			}
+
+			dev_put(mc_br_slave_dev);
+			return 0;
+		}
+
+		interface_first = ecm_db_multicast_if_first_get_at_index(interface_first_base, valid_if);
+		*interface_first = ii_cnt;
+		total_ii_cnt += ii_cnt;
+		valid_if++;
+		dev_put(mc_br_slave_dev);
+	}
+
+	return valid_if;
+}
+EXPORT_SYMBOL(ecm_interface_multicast_heirarchy_construct_bridged);
+
+/*
+ * ecm_interface_multicast_get_next_node_mac_address()
+ *	Get the MAC address of the next node for multicast flows
+ *
+ * TODO: This function will be removed when the multicast flow code
+ * is fixed to use the new interface hierarchy construction model.
+ *
+ */
+static bool ecm_interface_multicast_get_next_node_mac_address(
+	ip_addr_t dest_addr, struct net_device *dest_dev, int ip_version,
+	uint8_t *mac_addr)
+{
+	bool on_link;
+	ip_addr_t gw_addr = ECM_IP_ADDR_NULL;
+
+	if (!ecm_interface_mac_addr_get(dest_addr, mac_addr, &on_link, gw_addr)) {
+		if (ip_version == 4) {
+			DEBUG_WARN("Unable to obtain MAC address for " ECM_IP_ADDR_DOT_FMT "\n",
+				ECM_IP_ADDR_TO_DOT(dest_addr));
+			ecm_interface_send_arp_request(dest_dev, dest_addr, on_link, gw_addr);
+		}
+#ifdef ECM_IPV6_ENABLE
+		if (ip_version == 6) {
+			DEBUG_WARN("Unable to obtain MAC address for " ECM_IP_ADDR_OCTAL_FMT "\n",
+				ECM_IP_ADDR_TO_OCTAL(dest_addr));
+			ecm_interface_send_neighbour_solicitation(dest_dev, dest_addr);
+		}
+#endif
+		return false;
+	}
+
+	return true;
+}
+#endif
+
+/*
+ * ecm_interface_get_next_node_mac_address()
+ *	Get the MAC address of the next node
+ */
+static bool ecm_interface_get_next_node_mac_address(ip_addr_t dest_addr,
+					struct net_device *dest_dev,
+					int ip_version, uint8_t *mac_addr)
+{
+	ip_addr_t gw_addr = ECM_IP_ADDR_NULL;
+	bool on_link = true;
+
+	if (ecm_interface_mac_addr_get_no_route(dest_dev, dest_addr, mac_addr)) {
+		return true;
+	}
+
+	/*
+	 * MAC address look up failed. The host IP address may not be in the
+	 * neighbour table. So, let's send an ARP or neighbour solicitation
+	 * request to this host IP address, so in the subsequent lookups it can be
+	 * found.
+	 *
+	 * If we have a gateway address, try one more time with that address.
+	 * If it fails, send the request with the current dest_addr or
+	 * found gateway address.
+	 */
+	if (ecm_interface_find_gateway(dest_addr, gw_addr)) {
+		on_link = false;
+		if (ecm_interface_mac_addr_get_no_route(dest_dev, gw_addr, mac_addr)) {
+			DEBUG_TRACE("Found the mac address for the gateway\n");
+			return true;
+		}
+	}
+
+	if (ip_version == 4) {
+		DEBUG_WARN("Unable to obtain MAC address for " ECM_IP_ADDR_DOT_FMT " send ARP request\n",
+				ECM_IP_ADDR_TO_DOT(dest_addr));
+		ecm_interface_send_arp_request(dest_dev, dest_addr, on_link, gw_addr);
+	}
+
+#ifdef ECM_IPV6_ENABLE
+	if (ip_version == 6) {
+		DEBUG_WARN("Unable to obtain MAC address for " ECM_IP_ADDR_OCTAL_FMT  " send solicitation request\n",
+				ECM_IP_ADDR_TO_OCTAL(dest_addr));
+		ecm_interface_send_neighbour_solicitation(dest_dev, dest_addr);
+	}
+#endif
+
+	return false;
+}
+
+/*
+ * ecm_interface_should_update_egress_device_bridged()
+ *	Determine if the egress port should be re-evaluated in the bridged case
+ *
+ * This will be done if:
+ * - The egress port is the one provided from the front-end
+ * - The egress port is not a bridge, but is a slave of the bridge
+ * - Not routed
+ *
+ * If these conditions hold, this function will hold a reference to the bridge
+ * port and return it to the caller.  Otherwise no reference will be held and
+ * it will return NULL.
+ */
+static struct net_device *ecm_interface_should_update_egress_device_bridged(
+	struct net_device *given_dest_dev, struct net_device *dest_dev,
+	bool is_routed)
+{
+	struct net_device *bridge;
+
+	/*
+	 * Determine if we should attempt to fetch the bridge device
+	 */
+	if (!given_dest_dev || is_routed || (dest_dev != given_dest_dev) ||
+		ecm_front_end_is_bridge_device(given_dest_dev))
+		return NULL;
+
+	bridge = ecm_interface_get_and_hold_dev_master(given_dest_dev);
+
+	if (!bridge)
+		return NULL;
+
+	if (!ecm_front_end_is_bridge_device(bridge)) {
+		/*
+		 * Master is not a bridge - free the reference and return
+		 */
+		dev_put(bridge);
+		return NULL;
+	}
+
+	/*
+	 * Reference is held to bridge and must be freed by caller
+	 */
+	return bridge;
+}
+
+static inline bool ecm_interface_is_tunnel_endpoint(struct sk_buff *skb, struct net_device *dev, int ip_version, int protocol)
+{
+	if (ip_version == 4) {
+		if (protocol == IPPROTO_IPV6) {
+			return true;
+		}
+
+		if (protocol == IPPROTO_UDP && udp_hdr(skb)->dest == htons(4500)) {
+			return true;
+		}
+	}
+
+	if (ip_version == 6 && protocol == IPPROTO_IPIP) {
+		return true;
+	}
+
+	if (protocol == IPPROTO_GRE || protocol == IPPROTO_ESP) {
+		return true;
+	}
+
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+	if (dev->type == ARPHRD_NONE && dev->priv_flags_ext & IFF_EXT_TUN_TAP) {
+		return true;
+	}
+#endif
+
+	return false;
+}
+
+/*
+ * ecm_interface_heirarchy_construct()
+ *	Construct an interface heirarchy.
+ *
+ * Using the given addressing, locate the interface heirarchy used to emit packets to that destination.
+ * This is the heirarchy of interfaces a packet would transit to emit from the device.
+ *
+ * We will use the given src/dest devices when is_routed is false.
+ * When is_routed is true we will use the construct and the other devices (which is the src device of the
+ * construct device) whcih were obtained from the skb's route field and passed to this function..
+ *
+ * For example, with this network arrangement:
+ *
+ * PPPoE--VLAN--BRIDGE--BRIDGE_PORT(LAG_MASTER)--LAG_SLAVE_0--10.22.33.11
+ *
+ * Given the packet_dest_addr IP address 10.22.33.11 this will create an interface heirarchy (in interracfes[]) of:
+ * LAG_SLAVE_0 @ [ECM_DB_IFACE_HEIRARCHY_MAX - 5]
+ * LAG_MASTER @ [ECM_DB_IFACE_HEIRARCHY_MAX - 4]
+ * BRIDGE @ [ECM_DB_IFACE_HEIRARCHY_MAX - 3]
+ * VLAN @ [ECM_DB_IFACE_HEIRARCHY_MAX - 2]
+ * PPPOE @ [ECM_DB_IFACE_HEIRARCHY_MAX - 1]
+ * The value returned is (ECM_DB_IFACE_HEIRARCHY_MAX - 5)
+ *
+ * IMPORTANT: This function will return any known interfaces in the database, when interfaces do not exist in the database
+ * they will be created and added automatically to the database.
+ */
+int32_t ecm_interface_heirarchy_construct(struct ecm_front_end_connection_instance *feci,
+						struct ecm_db_iface_instance *interfaces[],
+						struct net_device *const_if, struct net_device *other_if,
+						ip_addr_t lookup_src_addr,
+						ip_addr_t lookup_dest_addr,
+						ip_addr_t real_dest_addr,
+						int ip_version, int packet_protocol,
+						struct net_device *given_dest_dev,
+						bool is_routed, struct net_device *given_src_dev,
+						uint8_t *dest_node_addr, uint8_t *src_node_addr,
+						__be16 *layer4hdr, struct sk_buff *skb,
+						struct ecm_front_end_ovs_params *op)
+{
+	int protocol;
+	ip_addr_t src_addr;
+	ip_addr_t dest_addr;
+	struct net_device *dest_dev;
+	char *dest_dev_name;
+	int32_t dest_dev_type;
+	struct net_device *src_dev;
+	char *src_dev_name;
+	int32_t src_dev_type;
+	int32_t current_interface_index;
+	bool from_local_addr;
+	bool next_dest_addr_valid;
+	bool next_dest_node_addr_valid = false;
+	ip_addr_t next_dest_addr;
+	uint8_t next_dest_node_addr[ETH_ALEN] = {0};
+	struct net_device *bridge;
+	struct net_device *top_dev = NULL;
+	uint32_t serial = ecm_db_connection_serial_get(feci->ci);
+
+	/*
+	 * Get a big endian of the IPv4 address we have been given as our starting point.
+	 */
+	protocol = packet_protocol;
+	ECM_IP_ADDR_COPY(src_addr, lookup_src_addr);
+	ECM_IP_ADDR_COPY(dest_addr, lookup_dest_addr);
+
+	if (ip_version == 4) {
+		DEBUG_TRACE("%px: Construct interface heirarchy for from src_addr: " ECM_IP_ADDR_DOT_FMT " to dest_addr: " ECM_IP_ADDR_DOT_FMT ", protocol: %d (serial %u)\n",
+				feci, ECM_IP_ADDR_TO_DOT(src_addr), ECM_IP_ADDR_TO_DOT(dest_addr), protocol,
+				serial);
+#ifdef ECM_IPV6_ENABLE
+	} else if (ip_version == 6) {
+		DEBUG_TRACE("%px: Construct interface heirarchy for from src_addr: " ECM_IP_ADDR_OCTAL_FMT " to dest_addr: " ECM_IP_ADDR_OCTAL_FMT ", protocol: %d (serial %u)\n",
+				feci, ECM_IP_ADDR_TO_OCTAL(src_addr), ECM_IP_ADDR_TO_OCTAL(dest_addr), protocol,
+				serial);
+#endif
+	} else {
+		DEBUG_WARN("%px: Wrong IP protocol: %d\n", feci, ip_version);
+		return ECM_DB_IFACE_HEIRARCHY_MAX;
+	}
+
+	/*
+	 * Get device to reach the given destination address.
+	 * If the heirarchy is for a routed connection we must use the devices obtained from the skb's route information..
+	 * If the heirarchy is NOT for a routed connection we try the given_dest_dev.
+	 */
+	from_local_addr = false;
+	if (!is_routed) {
+		dest_dev = given_dest_dev;
+		dev_hold(dest_dev);
+	} else {
+		dest_dev = ecm_interface_dev_find_by_local_addr(dest_addr);
+		if (dest_dev) {
+			from_local_addr = true;
+		} else {
+			dest_dev = const_if;
+			dev_hold(dest_dev);
+		}
+	}
+
+	/*
+	 * If the address is a local address and protocol is an IP tunnel
+	 * then this connection is a tunnel endpoint made to this device.
+	 * In which case we circumvent all proper procedure and just hack the devices to make stuff work.
+	 *
+	 * TODO THIS MUST BE FIXED - WE MUST USE THE INTERFACE HIERARCHY FOR ITS INTENDED PURPOSE TO
+	 * PARSE THE DEVICES AND WORK OUT THE PROPER INTERFACES INVOLVED.
+	 * E.G. IF WE TRIED TO RUN A TUNNEL OVER A VLAN OR QINQ THIS WILL BREAK AS WE DON'T DISCOVER THAT HIERARCHY
+	 */
+	if (dest_dev && from_local_addr) {
+		if (ecm_interface_is_tunnel_endpoint(skb, given_dest_dev, ip_version, protocol)) {
+			dev_put(dest_dev);
+			dest_dev = given_dest_dev;
+			if (dest_dev) {
+				dev_hold(dest_dev);
+				if (ip_version == 4) {
+					DEBUG_TRACE("%px: HACK: %s tunnel packet with dest_addr: " ECM_IP_ADDR_DOT_FMT " uses dev: %px(%s)\n", feci, "IPV4", ECM_IP_ADDR_TO_DOT(dest_addr), dest_dev, dest_dev->name);
+				} else {
+					DEBUG_TRACE("%px: HACK: %s tunnel packet with dest_addr: " ECM_IP_ADDR_OCTAL_FMT " uses dev: %px(%s)\n", feci, "IPV6", ECM_IP_ADDR_TO_OCTAL(dest_addr), dest_dev, dest_dev->name);
+				}
+			}
+		}
+	}
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+
+	/*
+	 * if the address is a local address and indev=l2tp.
+	 */
+	if ((given_src_dev->type == ARPHRD_PPP) && (given_src_dev->priv_flags_ext & IFF_EXT_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) {
+		if (!dst_xfrm(skb_dst(skb)) || (dest_dev->type != ECM_ARPHRD_IPSEC_TUNNEL_TYPE)) {
+			dev_put(dest_dev);
+			dest_dev = given_dest_dev;
+			if (dest_dev) {
+				dev_hold(dest_dev);
+				DEBUG_TRACE("%px: l2tp packet tunnel packet with dest_addr: " ECM_IP_ADDR_OCTAL_FMT " uses dev: %px(%s)\n", feci, ECM_IP_ADDR_TO_OCTAL(dest_addr), dest_dev, dest_dev->name);
+			}
+		}
+	}
+#endif
+
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+	/*
+	 * if the address is a local address and indev=PPTP.
+	 */
+	if (protocol == IPPROTO_GRE && given_dest_dev && (given_dest_dev->priv_flags_ext & IFF_EXT_PPP_PPTP)){
+		dev_put(dest_dev);
+		dest_dev = given_dest_dev;
+		if (dest_dev) {
+			dev_hold(dest_dev);
+			DEBUG_TRACE("%px: PPTP packet tunnel packet with dest_addr: " ECM_IP_ADDR_OCTAL_FMT " uses dev: %px(%s)\n", feci, ECM_IP_ADDR_TO_OCTAL(dest_addr), dest_dev, dest_dev->name);
+		}
+	}
+#endif
+
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+	/*
+	 * if the address is a local address and indev=VxLAN.
+	 */
+	if (from_local_addr &&
+	    given_dest_dev &&
+	    (given_dest_dev->type == ARPHRD_ETHER) &&
+	    (netif_is_vxlan(given_dest_dev))) {
+		dev_put(dest_dev);
+		dest_dev = given_dest_dev;
+		if (dest_dev) {
+			dev_hold(dest_dev);
+			DEBUG_TRACE("%px: VxLAN tunnel packet with dest_addr: " ECM_IP_ADDR_OCTAL_FMT " uses dev: %px(%s)\n", feci, ECM_IP_ADDR_TO_OCTAL(dest_addr), dest_dev, dest_dev->name);
+		}
+	}
+#endif
+
+	if (!dest_dev) {
+		DEBUG_WARN("%px: dest_addr: " ECM_IP_ADDR_OCTAL_FMT " - cannot locate device\n", feci, ECM_IP_ADDR_TO_OCTAL(dest_addr));
+		return ECM_DB_IFACE_HEIRARCHY_MAX;
+	}
+	dest_dev_name = dest_dev->name;
+	dest_dev_type = dest_dev->type;
+
+	/*
+	 * Get device to reach the given source address.
+	 * If the heirarchy is for a routed connection we must use the devices obtained from the skb's route information..
+	 * If the heirarchy is NOT for a routed connection we try the given_src_dev.
+	 */
+	from_local_addr = false;
+	if (!is_routed) {
+		src_dev = given_src_dev;
+		dev_hold(src_dev);
+	} else {
+		src_dev = ecm_interface_dev_find_by_local_addr(src_addr);
+		if (src_dev) {
+			from_local_addr = true;
+		} else {
+			src_dev = other_if;
+			dev_hold(src_dev);
+		}
+	}
+
+	/*
+	 * If the address is a local address and protocol is an IP tunnel
+	 * then this connection is a tunnel endpoint made to this device.
+	 * In which case we circumvent all proper procedure and just hack the devices to make stuff work.
+	 *
+	 * TODO THIS MUST BE FIXED - WE MUST USE THE INTERFACE HIERARCHY FOR ITS INTENDED PURPOSE TO
+	 * PARSE THE DEVICES AND WORK OUT THE PROPER INTERFACES INVOLVED.
+	 * E.G. IF WE TRIED TO RUN A TUNNEL OVER A VLAN OR QINQ THIS WILL BREAK AS WE DON'T DISCOVER THAT HIERARCHY
+	 */
+	if (src_dev && from_local_addr) {
+		if (ecm_interface_is_tunnel_endpoint(skb, given_src_dev, ip_version, protocol)) {
+			dev_put(src_dev);
+			src_dev = given_src_dev;
+			if (src_dev) {
+				dev_hold(src_dev);
+				if (ip_version == 4) {
+					DEBUG_TRACE("%px: HACK: %s tunnel packet with src_addr: " ECM_IP_ADDR_DOT_FMT " uses dev: %px(%s)\n", feci, "IPV4", ECM_IP_ADDR_TO_DOT(src_addr), src_dev, src_dev->name);
+				} else {
+					DEBUG_TRACE("%px: HACK: %s tunnel packet with src_addr: " ECM_IP_ADDR_OCTAL_FMT " uses dev: %px(%s)\n", feci, "IPV6", ECM_IP_ADDR_TO_OCTAL(src_addr), src_dev, src_dev->name);
+				}
+			}
+		}
+	}
+
+	if (!src_dev) {
+		DEBUG_WARN("%px: src_addr: " ECM_IP_ADDR_OCTAL_FMT " - cannot locate device\n", feci, ECM_IP_ADDR_TO_OCTAL(src_addr));
+		dev_put(dest_dev);
+		return ECM_DB_IFACE_HEIRARCHY_MAX;
+	}
+	src_dev_name = src_dev->name;
+	src_dev_type = src_dev->type;
+
+	/*
+	 * Check if source and dest dev are same.
+	 */
+	if (src_dev == dest_dev) {
+		bool skip = false;
+
+		DEBUG_TRACE("%px: Protocol is :%d source dev and dest dev are same\n", feci, protocol);
+
+		switch (ip_version) {
+		case 4:
+			if ((protocol == IPPROTO_IPV6) || (protocol == IPPROTO_ESP)) {
+				skip = true;
+				break;
+			}
+
+			if ((protocol == IPPROTO_UDP) && (udp_hdr(skb)->dest == htons(4500))) {
+				skip = true;
+				break;
+			}
+
+			break;
+
+		case 6:
+			if ((protocol == IPPROTO_IPIP) || (protocol == IPPROTO_ESP)) {
+				skip = true;
+				break;
+			}
+
+			break;
+
+		default:
+			DEBUG_WARN("%px: IP version = %d, Protocol = %d: Corrupted packet entered ecm\n", feci, ip_version, protocol);
+			skip = true;
+			break;
+		}
+
+		if (skip) {
+			/*
+			 * This happens from the input hook
+			 * We do not want to create a connection entry for this
+			 * TODO YES WE DO.
+			 * TODO THIS CONCERNS ME AS THIS SHOULD BE CAUGHT MUCH
+			 * EARLIER IN THE FRONT END IF POSSIBLE TO AVOID PERFORMANCE PENALTIES.
+			 * WE HAVE DONE A TREMENDOUS AMOUT OF WORK TO GET TO THIS POINT.
+			 * WE WILL ABORT HERE AND THIS WILL BE REPEATED FOR EVERY PACKET.
+			 * IN KEEPING WITH THE ECM DESIGN IT IS BETTER TO CREATE A CONNECTION AND RECORD IN THE HIERARCHY
+			 * ENOUGH INFORMATION TO ENSURE THAT ACCELERATION IS NOT BROKEN / DOES NOT OCCUR AT ALL.
+			 * THAT WAY WE DO A HEAVYWEIGHT ESTABLISHING OF A CONNECTION ONCE AND NEVER AGAIN...
+			 */
+			dev_put(src_dev);
+			dev_put(dest_dev);
+			return ECM_DB_IFACE_HEIRARCHY_MAX;
+		}
+	}
+
+	bridge = ecm_interface_should_update_egress_device_bridged(
+		given_dest_dev, dest_dev, is_routed);
+
+	if (bridge) {
+		struct net_device *new_dest_dev;
+		new_dest_dev = br_port_dev_get(bridge, dest_node_addr, skb, serial);
+		if (new_dest_dev) {
+			dev_put(dest_dev);
+			if (new_dest_dev != given_dest_dev) {
+				DEBUG_INFO("%px: Adjusted port for %pM is %s (given was %s)\n",
+					feci, dest_node_addr, new_dest_dev->name,
+					given_dest_dev->name);
+
+				dest_dev = new_dest_dev;
+				dest_dev_name = dest_dev->name;
+				dest_dev_type = dest_dev->type;
+			}
+		}
+		dev_put(bridge);
+	}
+
+	next_dest_addr_valid = true;
+	ECM_IP_ADDR_COPY(next_dest_addr, dest_addr);
+
+	/*
+	 * Iterate until we are done or get to the max number of interfaces we can record.
+	 * NOTE: current_interface_index tracks the position of the first interface position in interfaces[]
+	 * because we add from the end first_interface grows downwards.
+	 */
+	current_interface_index = ECM_DB_IFACE_HEIRARCHY_MAX;
+	while (current_interface_index > 0) {
+		struct ecm_db_iface_instance *ii;
+		struct net_device *next_dev;
+		/*
+		 * Get the ecm db interface instance for the device at hand
+		 */
+		ii = ecm_interface_establish_and_ref(feci, dest_dev, skb);
+
+		/*
+		 * If the interface could not be established then we abort
+		 */
+		if (!ii) {
+			DEBUG_WARN("%px: Failed to establish interface: %px, name: %s\n", feci, dest_dev, dest_dev_name);
+			dev_put(src_dev);
+			dev_put(dest_dev);
+
+			/*
+			 * Release the interfaces heirarchy we constructed to this point.
+			 */
+			ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+			return ECM_DB_IFACE_HEIRARCHY_MAX;
+		}
+
+		/*
+		 * Record the interface instance into the interfaces[]
+		 */
+		current_interface_index--;
+		interfaces[current_interface_index] = ii;
+
+		/*
+		 * Now we have to figure out what the next device will be (in the transmission path) the skb
+		 * will use to emit to the destination address.
+		 */
+		do {
+#ifdef ECM_INTERFACE_PPP_ENABLE
+			int channel_count;
+			struct ppp_channel *ppp_chan[1];
+			int channel_protocol;
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			struct pppoe_opt addressing;
+#endif
+#endif
+
+			DEBUG_TRACE("%px: Net device: %px is type: %d, name: %s\n", feci, dest_dev, dest_dev_type, dest_dev_name);
+			next_dev = NULL;
+
+			if (dest_dev_type == ARPHRD_ETHER) {
+				/*
+				 * Ethernet - but what sub type?
+				 */
+
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+				/*
+				 * VLAN?
+				 */
+				if (is_vlan_dev(dest_dev)) {
+					/*
+					 * VLAN master
+					 * No locking needed here, ASSUMPTION is that real_dev is held for as long as we have dev.
+					 */
+					next_dev = ecm_interface_vlan_real_dev(dest_dev);
+					dev_hold(next_dev);
+					DEBUG_TRACE("%px: Net device: %px is VLAN, slave dev: %px (%s)\n",
+							feci, dest_dev, next_dev, next_dev->name);
+					if (current_interface_index == (ECM_DB_IFACE_HEIRARCHY_MAX - 1)) {
+						top_dev = dest_dev;
+					}
+					break;
+				}
+#endif
+
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+				/*
+				 * MAC-VLAN?
+				 */
+				if (netif_is_macvlan(dest_dev)) {
+					if (ecm_interface_macvlan_mode_is_valid(dest_dev)) {
+						next_dev = macvlan_dev_real_dev(dest_dev);
+						dev_hold(next_dev);
+						DEBUG_TRACE("%px: Net device: %px is MAC-VLAN, slave dev: %px (%s)\n",
+								feci, dest_dev, next_dev, next_dev->name);
+
+						/*
+						 * We need to take the master_dev's MAC address during
+						 * NSS rule push. During VLAN/MACVLAN the master_dev for the
+						 * physical interface will be set to NULL but still we need the
+						 * VLAN/MACVLAN dev's MAC address while pushing the rule. We identify
+						 * the same using top_dev variable.
+						 */
+						if (current_interface_index == (ECM_DB_IFACE_HEIRARCHY_MAX - 1)) {
+							top_dev = dest_dev;
+						}
+						break;
+					}
+
+					DEBUG_WARN("%px: Net device %px MACVLAN mode is not supported.\n", feci, dest_dev);
+					goto done;
+				}
+#endif
+
+				/*
+				 * BRIDGE?
+				 */
+				if (ecm_front_end_is_bridge_device(dest_dev)) {
+					/*
+					 * Bridge
+					 * Figure out which port device the skb will go to using the dest_addr.
+					 */
+					uint8_t mac_addr[ETH_ALEN];
+
+					if (next_dest_node_addr_valid) {
+						memcpy(mac_addr, next_dest_node_addr, ETH_ALEN);
+					} else if (!next_dest_addr_valid) {
+						dev_put(src_dev);
+						dev_put(dest_dev);
+
+						/*
+						 * Release the interfaces heirarchy we constructed to this point.
+						 */
+						ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+						return ECM_DB_IFACE_HEIRARCHY_MAX;
+					} else {
+						ip_addr_t look_up_addr;
+						struct net_device *tmp_dev;
+						ECM_IP_ADDR_COPY(look_up_addr, dest_addr);
+						/*
+						 * If this is a local IP address, this means the interface hierarchy is being created for
+						 * TO_NAT or FROM_NAT direction. In these cases, since the IP address is a local IP address,
+						 * MAC lookup will find the local interface's MAC address which cannot be used for the slave port
+						 * look up in the forwarding database. So, we use the src_ip address for MAC look up.
+						 * For TO_NAT direction, src_ip address is the sender host's IP address. For FROM_NAT direction
+						 * src_ip address is the destination host's IP address.
+						 * FROM_NAT ---- > HOST (src_ip)
+						 * TO_NAT <----- HOST (src_ip)
+						 */
+						tmp_dev = ecm_interface_dev_find_by_local_addr(dest_addr);
+						if (tmp_dev) {
+							ECM_IP_ADDR_COPY(look_up_addr, src_addr);
+							dev_put(tmp_dev);
+						}
+
+						if (!ecm_interface_get_next_node_mac_address(look_up_addr, dest_dev, ip_version, mac_addr)) {
+							DEBUG_WARN("%px: Unable to find the host MAC address connected to the Linux bridge\n", feci);
+							goto done;
+						}
+					}
+
+					next_dev = br_port_dev_get(dest_dev,
+						mac_addr, skb, serial);
+
+					if (!next_dev) {
+						DEBUG_WARN("%px: Unable to obtain output port for: %pM\n", feci, mac_addr);
+						goto done;
+					}
+
+					DEBUG_TRACE("%px: Net device: %px is BRIDGE, next_dev: %px (%s)\n", feci, dest_dev, next_dev, next_dev->name);
+
+					if (current_interface_index == (ECM_DB_IFACE_HEIRARCHY_MAX - 1)) {
+						top_dev = dest_dev;
+					}
+					break;
+				}
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+				if (ovsmgr_is_ovs_master(dest_dev)) {
+					ip_addr_t look_up_addr;
+					uint8_t mac_addr[ETH_ALEN];
+					struct net_device *tmp_dev;
+					ECM_IP_ADDR_COPY(look_up_addr, dest_addr);
+
+					/*
+					 * If this is a local IP address, this means the interface hierarchy is being created for
+					 * TO_NAT or FROM_NAT direction. In these cases, since the IP address is a local IP address,
+					 * MAC lookup will find the local interface's MAC address which cannot be used for the slave port
+					 * look up in the forwarding database. So, we use the src_ip address for MAC look up.
+					 * For TO_NAT direction, src_ip address is the sender host's IP address. For FROM_NAT direction
+					 * src_ip address is the destination host's IP address.
+					 * FROM_NAT ---- > HOST (src_ip)
+					 * TO_NAT <----- HOST (src_ip)
+					 */
+					tmp_dev = ecm_interface_dev_find_by_local_addr(dest_addr);
+					if (tmp_dev) {
+						ECM_IP_ADDR_COPY(look_up_addr, src_addr);
+						dev_put(tmp_dev);
+					}
+
+					if (!ecm_interface_get_next_node_mac_address(look_up_addr, dest_dev, ip_version, mac_addr)) {
+						DEBUG_WARN("%px: Unable to find the host MAC address connected to the OVS bridge\n", feci);
+						goto done;
+					}
+
+					next_dev = ecm_interface_ovs_bridge_port_dev_get_and_ref(skb, dest_dev, src_addr, dest_addr, ip_version, protocol,
+											 is_routed, src_node_addr, mac_addr, layer4hdr, op);
+					if (!next_dev) {
+						DEBUG_WARN("%px: Unable to obtain OVS output port for: %pM\n", feci, mac_addr);
+						goto done;
+					}
+
+					DEBUG_TRACE("%px: Net device: %px is OVS BRIDGE, next_dev: %px (%s)\n", feci, dest_dev, next_dev, next_dev->name);
+
+					if (current_interface_index == (ECM_DB_IFACE_HEIRARCHY_MAX - 1)) {
+						top_dev = dest_dev;
+					}
+					break;
+				}
+#endif
+
+#ifdef ECM_INTERFACE_BOND_ENABLE
+				/*
+				 * LAG?
+				 */
+				if (ecm_front_end_is_lag_master(dest_dev)) {
+					/*
+					 * Link aggregation
+					 * Figure out whiich slave device of the link aggregation will be used to reach the destination.
+					 */
+					uint32_t src_addr_32 = 0;
+					uint32_t dest_addr_32 = 0;
+					struct in6_addr src_addr6;
+					struct in6_addr dest_addr6;
+					uint8_t src_mac_addr[ETH_ALEN];
+					uint8_t dest_mac_addr[ETH_ALEN];
+
+					memset(src_mac_addr, 0, ETH_ALEN);
+					memset(dest_mac_addr, 0, ETH_ALEN);
+
+					if (ip_version == 4) {
+						ECM_IP_ADDR_TO_NIN4_ADDR(src_addr_32, src_addr);
+						ECM_IP_ADDR_TO_NIN4_ADDR(dest_addr_32, real_dest_addr);
+					}
+
+					if (!is_routed) {
+						memcpy(src_mac_addr, src_node_addr, ETH_ALEN);
+						memcpy(dest_mac_addr, dest_node_addr, ETH_ALEN);
+					} else {
+						struct net_device *master_dev;
+
+						/*
+						 * Use appropriate source MAC address for routed packets and
+						 * find proper interface to find the destination mac address and
+						 * from which to issue ARP or neighbour solicitation packet.
+						 */
+						master_dev = ecm_interface_get_and_hold_dev_master(dest_dev);
+						if (master_dev) {
+							memcpy(src_mac_addr, master_dev->dev_addr, ETH_ALEN);
+						} else {
+							master_dev = dest_dev;
+							if (top_dev) {
+								master_dev = top_dev;
+							}
+							memcpy(src_mac_addr, master_dev->dev_addr, ETH_ALEN);
+							dev_hold(master_dev);
+						}
+
+						/*
+						 * Determine destination MAC address for this routed packet
+						 */
+						if (next_dest_node_addr_valid) {
+							memcpy(dest_mac_addr, next_dest_node_addr, ETH_ALEN);
+						} else if (!next_dest_addr_valid) {
+							dev_put(src_dev);
+							dev_put(dest_dev);
+							dev_put(master_dev);
+							ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+							return ECM_DB_IFACE_HEIRARCHY_MAX;
+						} else {
+							if (!ecm_interface_mac_addr_get_no_route(master_dev, dest_addr, dest_mac_addr)) {
+								ip_addr_t gw_addr = ECM_IP_ADDR_NULL;
+								/*
+								 * Try one more time with gateway ip address if it exists.
+								 */
+								if (!ecm_interface_find_gateway(dest_addr, gw_addr)) {
+									goto lag_fail;
+								}
+
+								if (ip_version == 4) {
+									DEBUG_TRACE("%px: Have a gw address " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(gw_addr));
+								}
+#ifdef ECM_IPV6_ENABLE
+
+								if (ip_version == 6) {
+									DEBUG_TRACE("%px: Have a gw address " ECM_IP_ADDR_OCTAL_FMT "\n", feci, ECM_IP_ADDR_TO_OCTAL(gw_addr));
+								}
+#endif
+								if (ecm_interface_mac_addr_get_no_route(master_dev, gw_addr, dest_mac_addr)) {
+									DEBUG_TRACE("%px: Found the mac address for gateway\n", feci);
+									dev_put(master_dev);
+									goto lag_success;
+								}
+
+								if (ip_version == 4) {
+									ecm_interface_send_arp_request(master_dev, dest_addr, false, gw_addr);
+
+									DEBUG_WARN("%px: Unable to obtain any MAC address for " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(dest_addr));
+								}
+#ifdef ECM_IPV6_ENABLE
+								/*
+								 * If there is a gw on the link, send the neighbor solicitation
+								 * message to that address.
+								 */
+								if (!ECM_IP_ADDR_IS_NULL(gw_addr)) {
+									ECM_IP_ADDR_COPY(dest_addr, gw_addr);
+								}
+
+								if (ip_version == 6) {
+									ecm_interface_send_neighbour_solicitation(master_dev, dest_addr);
+
+									DEBUG_WARN("%px: Unable to obtain any MAC address for " ECM_IP_ADDR_OCTAL_FMT "\n", feci, ECM_IP_ADDR_TO_OCTAL(dest_addr));
+								}
+#endif
+lag_fail:
+								dev_put(src_dev);
+								dev_put(dest_dev);
+								dev_put(master_dev);
+
+								ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+								return ECM_DB_IFACE_HEIRARCHY_MAX;
+							}
+						}
+						dev_put(master_dev);
+					}
+lag_success:
+					if (ip_version == 4) {
+						next_dev = bond_get_tx_dev(NULL, src_mac_addr, dest_mac_addr,
+										&src_addr_32, &dest_addr_32,
+										htons((uint16_t)ETH_P_IP), dest_dev, layer4hdr);
+					} else if (ip_version == 6) {
+						ECM_IP_ADDR_TO_NIN6_ADDR(src_addr6, src_addr);
+						ECM_IP_ADDR_TO_NIN6_ADDR(dest_addr6, real_dest_addr);
+						next_dev = bond_get_tx_dev(NULL, src_mac_addr, dest_mac_addr,
+									   src_addr6.s6_addr, dest_addr6.s6_addr,
+									   htons((uint16_t)ETH_P_IPV6), dest_dev, layer4hdr);
+					}
+
+					if (next_dev && netif_carrier_ok(next_dev)) {
+						dev_hold(next_dev);
+					} else {
+						DEBUG_WARN("%px: Unable to obtain LAG output slave device\n", feci);
+						dev_put(src_dev);
+						dev_put(dest_dev);
+
+						/*
+						 * Release the interfaces heirarchy we constructed to this point.
+						 */
+						ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+						return ECM_DB_IFACE_HEIRARCHY_MAX;
+					}
+
+					DEBUG_TRACE("%px: Net device: %px is LAG, slave dev: %px (%s)\n", feci, dest_dev, next_dev, next_dev->name);
+					break;
+				}
+#endif
+
+				/*
+				 * ETHERNET!
+				 * Just plain ethernet it seems.
+				 */
+				DEBUG_TRACE("%px: Net device: %px is ETHERNET\n", feci, dest_dev);
+				break;
+			}
+
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+			/*
+			 * GRE Tunnel?
+			 */
+			if ((dest_dev_type == ARPHRD_IPGRE) || (dest_dev_type == ARPHRD_IP6GRE)) {
+				DEBUG_TRACE("%px: Net device: %px is GRE Tunnel type: %d\n", feci, dest_dev, dest_dev_type);
+				break;
+			}
+#endif
+
+			/*
+			 * LOOPBACK?
+			 */
+			if (dest_dev_type == ARPHRD_LOOPBACK) {
+				DEBUG_TRACE("%px: Net device: %px is LOOPBACK type: %d\n", feci, dest_dev, dest_dev_type);
+				break;
+			}
+
+			/*
+			 * IPSEC?
+			 */
+			if (dest_dev_type == ECM_ARPHRD_IPSEC_TUNNEL_TYPE) {
+				DEBUG_TRACE("%px: Net device: %px is IPSec tunnel type: %d\n", feci, dest_dev, dest_dev_type);
+				/* TODO Figure out the next device the tunnel is using... */
+				break;
+			}
+
+			/*
+			 * SIT (6-in-4)?
+			 */
+			if (dest_dev_type == ARPHRD_SIT) {
+				DEBUG_TRACE("%px: Net device: %px is SIT (6-in-4) type: %d\n", feci, dest_dev, dest_dev_type);
+				/* TODO Figure out the next device the tunnel is using... */
+				break;
+			}
+
+			/*
+			 * IPIP6 Tunnel?
+			 */
+			if (dest_dev_type == ARPHRD_TUNNEL6) {
+				DEBUG_TRACE("%px: Net device: %px is TUNIPIP6 type: %d\n", feci, dest_dev, dest_dev_type);
+				/* TODO Figure out the next device the tunnel is using... */
+				break;
+			}
+
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+			/*
+			 * MAP-T xlate ?
+			 */
+			if (dest_dev_type == ARPHRD_NONE) {
+				if (is_map_t_dev(dest_dev)) {
+					DEBUG_TRACE("%px: Net device: %px is MAP-T type: %d\n", feci, dest_dev, dest_dev_type);
+					break;
+				}
+			}
+#endif
+
+#ifdef ECM_INTERFACE_RAWIP_ENABLE
+			/*
+			 * RAWIP?
+			 * If it is RAWIP type, there is no next device.
+			 */
+			if (dest_dev_type == ARPHRD_RAWIP) {
+				DEBUG_TRACE("%px: Net device: %px is RAWIP type: %d\n", feci, dest_dev, dest_dev_type);
+				break;
+			}
+#endif
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+			/*
+			 * OVPN ?
+			 */
+			if ((dest_dev_type == ARPHRD_NONE) && (dest_dev->priv_flags_ext & IFF_EXT_TUN_TAP)) {
+				DEBUG_TRACE("Net device: %px is OVPN, device name: %s\n", dest_dev, dest_dev->name);
+				break;
+			}
+#endif
+			/*
+			 * If this is NOT PPP then it is unknown to the ecm and we cannot figure out it's next device.
+			 */
+			if (dest_dev_type != ARPHRD_PPP) {
+				DEBUG_TRACE("%px: Net device: %px is UNKNOWN type: %d\n", feci, dest_dev, dest_dev_type);
+				break;
+			}
+
+#ifndef ECM_INTERFACE_PPP_ENABLE
+			DEBUG_TRACE("%px: Net device: %px is UNKNOWN (PPP Unsupported) type: %d\n", feci, dest_dev, dest_dev_type);
+#else
+			DEBUG_TRACE("%px: Net device: %px is PPP\n", feci, dest_dev);
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+			if ((given_src_dev->priv_flags_ext & IFF_EXT_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) {
+				if (skb->skb_iif == dest_dev->ifindex) {
+					DEBUG_TRACE("%px: Net device: %px PPP channel is PPPoL2TPV2\n", feci, dest_dev);
+					break;
+				}
+			}
+#endif
+
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+			if (protocol == IPPROTO_GRE && dest_dev && (dest_dev->priv_flags_ext & IFF_EXT_PPP_PPTP)) {
+				DEBUG_TRACE("%px: Net device: %px PPP channel is PPTP\n", feci, dest_dev);
+				break;
+			}
+#endif
+			/*
+			 * PPP - but what is the channel type?
+			 * First: If this is multi-link then we do not support it
+			 */
+			if (ppp_is_multilink(dest_dev) > 0) {
+				DEBUG_TRACE("%px: Net device: %px is MULTILINK PPP - Unknown to the ECM\n", feci, dest_dev);
+				break;
+			}
+
+			/*
+			 * Get the PPP channel and then enquire what kind of channel it is
+			 * NOTE: Not multilink so only one channel to get.
+			 */
+			channel_count = ppp_hold_channels(dest_dev, ppp_chan, 1);
+			if (channel_count != 1) {
+				DEBUG_TRACE("%px: Net device: %px PPP has %d channels - Unknown to the ECM\n",
+						feci, dest_dev, channel_count);
+				break;
+			}
+
+			/*
+			 * Get channel protocol type
+			 * NOTE: Not all PPP channels support channel specific methods.
+			 */
+			channel_protocol = ppp_channel_get_protocol(ppp_chan[0]);
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+			if (channel_protocol == PX_PROTO_OL2TP) {
+
+				/*
+				 * PPPoL2TPV2 channel
+				 */
+				ppp_release_channels(ppp_chan, 1);
+				DEBUG_TRACE("%px: Net device: %px PPP channel is PPPoL2TPV2\n", feci, dest_dev);
+
+				/*
+				 * Release the channel.  Note that next_dev not held.
+				 */
+				break;
+			}
+#endif
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			if (channel_protocol == PX_PROTO_OE) {
+				/*
+				 * PPPoE channel
+				 */
+				DEBUG_TRACE("%px: Net device: %px PPP channel is PPPoE\n", feci, dest_dev);
+
+				/*
+				 * Get PPPoE session information and the underlying device it is using.
+				 */
+				if (pppoe_channel_addressing_get(ppp_chan[0], &addressing)) {
+					DEBUG_WARN("%px: failed to get PPPoE addressing info\n", feci);
+					ppp_release_channels(ppp_chan, 1);
+					break;
+				}
+
+				/*
+				 * Copy the dev hold into this, we will release the hold later
+				 */
+				next_dev = addressing.dev;
+				next_dest_addr_valid = false;
+				next_dest_node_addr_valid = true;
+				memcpy(next_dest_node_addr, addressing.pa.remote, ETH_ALEN);
+
+				/*
+				 * Release the channel.  Note that next_dev is still (correctly) held.
+				 */
+				ppp_release_channels(ppp_chan, 1);
+				break;
+			}
+#endif
+
+			DEBUG_TRACE("%px: Net device: %px PPP channel protocol: %d - Unknown to the ECM\n",
+				    feci, dest_dev, channel_protocol);
+
+			/*
+			 * Release the channel
+			 */
+			ppp_release_channels(ppp_chan, 1);
+
+#endif
+		} while (false);
+
+		/*
+		 * No longer need dest_dev as it may become next_dev
+		 */
+		dev_put(dest_dev);
+
+		/*
+		 * Check out the next_dev, if any
+		 */
+		if (!next_dev) {
+			int32_t i __attribute__((unused));
+			DEBUG_INFO("%px: Completed interface heirarchy construct with first interface @: %d\n", feci, current_interface_index);
+#if DEBUG_LEVEL > 1
+			for (i = current_interface_index; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+				DEBUG_TRACE("\t%px: Interface @ %d: %px, type: %d, name: %s\n",
+						feci, i, interfaces[i], ecm_db_iface_type_get(interfaces[i]), ecm_db_interface_type_to_string(ecm_db_iface_type_get(interfaces[i])));
+
+			}
+#endif
+
+			/*
+			 * Release src_dev now
+			 */
+			dev_put(src_dev);
+			return current_interface_index;
+		}
+
+		/*
+		 * dest_dev becomes next_dev
+		 */
+		dest_dev = next_dev;
+		dest_dev_name = dest_dev->name;
+		dest_dev_type = dest_dev->type;
+	}
+
+	DEBUG_WARN("%px: Too many interfaces: %d\n", feci, current_interface_index);
+	DEBUG_ASSERT(current_interface_index == 0, "%px: Bad logic handling current_interface_index: %d\n", feci, current_interface_index);
+
+done:
+	dev_put(src_dev);
+	dev_put(dest_dev);
+
+	/*
+	 * Release the interfaces heirarchy we constructed to this point.
+	 */
+	ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+	return ECM_DB_IFACE_HEIRARCHY_MAX;
+}
+EXPORT_SYMBOL(ecm_interface_heirarchy_construct);
+
+#ifdef ECM_MULTICAST_ENABLE
+/*
+ * ecm_interface_multicast_from_heirarchy_construct()
+ *	Construct an interface heirarchy.
+ *
+ * TODO: This function will be removed later and ecm_interface_heirarchy_construct() function
+ *	 will be used when the multicast code is fixed to use the new interface hierarchy
+ *	 construction model which uses the skb's route information instead of doing
+ *	 the route lookup based on the IP addresses.
+ *
+ * Using the given addressing, locate the interface heirarchy used to emit packets to that destination.
+ * This is the heirarchy of interfaces a packet would transit to emit from the device.
+ *
+ * We will use the given src/dest devices when is_routed is false.
+ * When is_routed is true we will try routing tables first, failing back to any given.
+ *
+ * For example, with this network arrangement:
+ *
+ * PPPoE--VLAN--BRIDGE--BRIDGE_PORT(LAG_MASTER)--LAG_SLAVE_0--10.22.33.11
+ *
+ * Given the packet_dest_addr IP address 10.22.33.11 this will create an interface heirarchy (in interracfes[]) of:
+ * LAG_SLAVE_0 @ [ECM_DB_IFACE_HEIRARCHY_MAX - 5]
+ * LAG_MASTER @ [ECM_DB_IFACE_HEIRARCHY_MAX - 4]
+ * BRIDGE @ [ECM_DB_IFACE_HEIRARCHY_MAX - 3]
+ * VLAN @ [ECM_DB_IFACE_HEIRARCHY_MAX - 2]
+ * PPPOE @ [ECM_DB_IFACE_HEIRARCHY_MAX - 1]
+ * The value returned is (ECM_DB_IFACE_HEIRARCHY_MAX - 5)
+ *
+ * IMPORTANT: This function will return any known interfaces in the database, when interfaces do not exist in the database
+ * they will be created and added automatically to the database.
+ */
+int32_t ecm_interface_multicast_from_heirarchy_construct(struct ecm_front_end_connection_instance *feci,
+						struct ecm_db_iface_instance *interfaces[],
+						ip_addr_t packet_src_addr,
+						ip_addr_t packet_dest_addr,
+						int ip_version, int packet_protocol,
+						struct net_device *given_dest_dev,
+						bool is_routed, struct net_device *given_src_dev,
+						uint8_t *dest_node_addr, uint8_t *src_node_addr,
+						__be16 *layer4hdr, struct sk_buff *skb)
+{
+	int protocol;
+	ip_addr_t src_addr;
+	ip_addr_t dest_addr;
+	struct net_device *dest_dev;
+	char *dest_dev_name;
+	int32_t dest_dev_type;
+	struct net_device *src_dev;
+	char *src_dev_name;
+	int32_t src_dev_type;
+	int32_t current_interface_index;
+	bool from_local_addr;
+	bool next_dest_addr_valid;
+	bool next_dest_node_addr_valid = false;
+	ip_addr_t next_dest_addr;
+	uint8_t next_dest_node_addr[ETH_ALEN] = {0};
+	struct net_device *bridge;
+	uint32_t serial = ecm_db_connection_serial_get(feci->ci);
+
+	/*
+	 * Get a big endian of the IPv4 address we have been given as our starting point.
+	 */
+	protocol = packet_protocol;
+	ECM_IP_ADDR_COPY(src_addr, packet_src_addr);
+	ECM_IP_ADDR_COPY(dest_addr, packet_dest_addr);
+
+	if (ip_version == 4) {
+		DEBUG_TRACE("Construct interface heirarchy for from src_addr: " ECM_IP_ADDR_DOT_FMT " to dest_addr: " ECM_IP_ADDR_DOT_FMT ", protocol: %d (serial %u)\n",
+				ECM_IP_ADDR_TO_DOT(src_addr), ECM_IP_ADDR_TO_DOT(dest_addr), protocol,
+				serial);
+#ifdef ECM_IPV6_ENABLE
+	} else if (ip_version == 6) {
+		DEBUG_TRACE("Construct interface heirarchy for from src_addr: " ECM_IP_ADDR_OCTAL_FMT " to dest_addr: " ECM_IP_ADDR_OCTAL_FMT ", protocol: %d (serial %u)\n",
+				ECM_IP_ADDR_TO_OCTAL(src_addr), ECM_IP_ADDR_TO_OCTAL(dest_addr), protocol,
+				serial);
+#endif
+	} else {
+		DEBUG_WARN("Wrong IP protocol: %d\n", ip_version);
+		return ECM_DB_IFACE_HEIRARCHY_MAX;
+	}
+
+	/*
+	 * Get device to reach the given destination address.
+	 * If the heirarchy is for a routed connection we must try route lookup first, falling back to any given_dest_dev.
+	 * If the heirarchy is NOT for a routed connection we try the given_dest_dev first, followed by routed lookup.
+	 */
+	from_local_addr = false;
+	if (is_routed) {
+		dest_dev = ecm_interface_dev_find_by_addr(dest_addr, &from_local_addr);
+		if (!dest_dev && given_dest_dev) {
+			/*
+			 * Fall back to any given
+			 */
+			dest_dev = given_dest_dev;
+			dev_hold(dest_dev);
+		}
+	} else if (given_dest_dev) {
+		dest_dev = given_dest_dev;
+		dev_hold(dest_dev);
+	} else {
+		/*
+		 * Fall back to routed look up
+		 */
+		dest_dev = ecm_interface_dev_find_by_addr(dest_addr, &from_local_addr);
+	}
+
+	/*
+	 * GGG ALERT: If the address is a local address and protocol is an IP tunnel
+	 * then this connection is a tunnel endpoint made to this device.
+	 * In which case we circumvent all proper procedure and just hack the devices to make stuff work.
+	 * GGG TODO THIS MUST BE FIXED - WE MUST USE THE INTERFACE HIERARCHY FOR ITS INTENDED PURPOSE TO
+	 * PARSE THE DEVICES AND WORK OUT THE PROPER INTERFACES INVOLVED.
+	 * E.G. IF WE TRIED TO RUN A TUNNEL OVER A VLAN OR QINQ THIS WILL BREAK AS WE DON'T DISCOVER THAT HIERARCHY
+	 */
+	if (dest_dev && from_local_addr) {
+		if (((ip_version == 4) && (protocol == IPPROTO_IPV6)) ||
+				((ip_version == 6) && (protocol == IPPROTO_IPIP))) {
+			dev_put(dest_dev);
+			dest_dev = given_dest_dev;
+			if (dest_dev) {
+				dev_hold(dest_dev);
+				if (ip_version == 4) {
+					DEBUG_TRACE("HACK: %s tunnel packet with dest_addr: " ECM_IP_ADDR_DOT_FMT " uses dev: %px(%s)\n", "IPV6", ECM_IP_ADDR_TO_DOT(dest_addr), dest_dev, dest_dev->name);
+				} else {
+					DEBUG_TRACE("HACK: %s tunnel packet with dest_addr: " ECM_IP_ADDR_OCTAL_FMT " uses dev: %px(%s)\n", "IPIP", ECM_IP_ADDR_TO_OCTAL(dest_addr), dest_dev, dest_dev->name);
+				}
+			}
+		}
+	}
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+	/*
+	 * if the address is a local address and indev=l2tp.
+	 */
+	if ((given_src_dev->type == ARPHRD_PPP) && (given_src_dev->priv_flags_ext & IFF_EXT_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) {
+		if (!dst_xfrm(skb_dst(skb)) || (dest_dev->type != ECM_ARPHRD_IPSEC_TUNNEL_TYPE)) {
+			dev_put(dest_dev);
+			dest_dev = given_dest_dev;
+			if (dest_dev) {
+				dev_hold(dest_dev);
+				DEBUG_TRACE("l2tp packet tunnel packet with dest_addr: " ECM_IP_ADDR_OCTAL_FMT " uses dev: %px(%s)\n", ECM_IP_ADDR_TO_OCTAL(dest_addr), dest_dev, dest_dev->name);
+			}
+		}
+	}
+#endif
+
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+	/*
+	 * if the address is a local address and indev=PPTP.
+	 */
+	if (protocol == IPPROTO_GRE && given_dest_dev && given_dest_dev->type == ARPHRD_PPP) {
+		dev_put(dest_dev);
+		dest_dev = given_dest_dev;
+		if (dest_dev) {
+			dev_hold(dest_dev);
+			DEBUG_TRACE("PPTP packet tunnel packet with dest_addr: " ECM_IP_ADDR_OCTAL_FMT " uses dev: %px(%s)\n", ECM_IP_ADDR_TO_OCTAL(dest_addr), dest_dev, dest_dev->name);
+		}
+	}
+#endif
+
+	if (!dest_dev) {
+		DEBUG_WARN("dest_addr: " ECM_IP_ADDR_OCTAL_FMT " - cannot locate device\n", ECM_IP_ADDR_TO_OCTAL(dest_addr));
+		return ECM_DB_IFACE_HEIRARCHY_MAX;
+	}
+	dest_dev_name = dest_dev->name;
+	dest_dev_type = dest_dev->type;
+
+	/*
+	 * Get device to reach the given source address.
+	 * If the heirarchy is for a routed connection we must try route lookup first, falling back to any given_src_dev.
+	 * If the heirarchy is NOT for a routed connection we try the given_src_dev first, followed by routed lookup.
+	 */
+	from_local_addr = false;
+	if (is_routed) {
+		src_dev = ecm_interface_dev_find_by_addr(src_addr, &from_local_addr);
+		if (!src_dev && given_src_dev) {
+			/*
+			 * Fall back to any given
+			 */
+			src_dev = given_src_dev;
+			dev_hold(src_dev);
+		}
+	} else if (given_src_dev) {
+		src_dev = given_src_dev;
+		dev_hold(src_dev);
+	} else {
+		/*
+		 * Fall back to routed look up
+		 */
+		src_dev = ecm_interface_dev_find_by_addr(src_addr, &from_local_addr);
+	}
+
+	/*
+	 * GGG ALERT: If the address is a local address and protocol is an IP tunnel
+	 * then this connection is a tunnel endpoint made to this device.
+	 * In which case we circumvent all proper procedure and just hack the devices to make stuff work.
+	 * GGG TODO THIS MUST BE FIXED - WE MUST USE THE INTERFACE HIERARCHY FOR ITS INTENDED PURPOSE TO
+	 * PARSE THE DEVICES AND WORK OUT THE PROPER INTERFACES INVOLVED.
+	 * E.G. IF WE TRIED TO RUN A TUNNEL OVER A VLAN OR QINQ THIS WILL BREAK AS WE DON'T DISCOVER THAT HIERARCHY
+	 */
+	if (src_dev && from_local_addr) {
+		if (((ip_version == 4) && (protocol == IPPROTO_IPV6)) ||
+				((ip_version == 6) && (protocol == IPPROTO_IPIP))) {
+			dev_put(src_dev);
+			src_dev = given_src_dev;
+			if (src_dev) {
+				dev_hold(src_dev);
+				if (ip_version == 4) {
+					DEBUG_TRACE("HACK: %s tunnel packet with src_addr: " ECM_IP_ADDR_DOT_FMT " uses dev: %px(%s)\n", "IPV6", ECM_IP_ADDR_TO_DOT(src_addr), src_dev, src_dev->name);
+				} else {
+					DEBUG_TRACE("HACK: %s tunnel packet with src_addr: " ECM_IP_ADDR_OCTAL_FMT " uses dev: %px(%s)\n", "IPIP", ECM_IP_ADDR_TO_OCTAL(src_addr), src_dev, src_dev->name);
+				}
+			}
+		}
+	}
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+	/*
+	 * if the address is a local address and indev=l2tp.
+	 */
+	if (skb && skb->sk && (skb->sk->sk_protocol == IPPROTO_UDP) && (udp_sk(skb->sk)->encap_type == UDP_ENCAP_L2TPINUDP)) {
+		if (dest_dev != given_src_dev) {
+			dev_put(src_dev);
+			src_dev = given_src_dev;
+			if (src_dev) {
+				dev_hold(src_dev);
+				DEBUG_TRACE("l2tp tunnel packet with src_addr: " ECM_IP_ADDR_OCTAL_FMT " uses dev: %px(%s)\n", ECM_IP_ADDR_TO_OCTAL(src_addr), src_dev, src_dev->name);
+			}
+		}
+	}
+#endif
+
+	if (!src_dev) {
+		DEBUG_WARN("src_addr: " ECM_IP_ADDR_OCTAL_FMT " - cannot locate device\n", ECM_IP_ADDR_TO_OCTAL(src_addr));
+		dev_put(dest_dev);
+		return ECM_DB_IFACE_HEIRARCHY_MAX;
+	}
+	src_dev_name = src_dev->name;
+	src_dev_type = src_dev->type;
+
+	/*
+	 * Check if source and dest dev are same.
+	 * For the forwarded flows which involve tunnels this will happen when called from input hook.
+	 */
+	if (src_dev == dest_dev) {
+		DEBUG_TRACE("Protocol is :%d source dev and dest dev are same\n", protocol);
+		if (((ip_version == 4) && ((protocol == IPPROTO_IPV6) || (protocol == IPPROTO_ESP)))
+				|| ((ip_version == 6) && (protocol == IPPROTO_IPIP))) {
+			/*
+			 * This happens from the input hook
+			 * We do not want to create a connection entry for this
+			 * GGG TODO YES WE DO.
+			 * GGG TODO THIS CONCERNS ME AS THIS SHOULD BE CAUGHT MUCH
+			 * EARLIER IN THE FRONT END IF POSSIBLE TO AVOID PERFORMANCE PENALTIES.
+			 * WE HAVE DONE A TREMENDOUS AMOUT OF WORK TO GET TO THIS POINT.
+			 * WE WILL ABORT HERE AND THIS WILL BE REPEATED FOR EVERY PACKET.
+			 * IN KEEPING WITH THE ECM DESIGN IT IS BETTER TO CREATE A CONNECTION AND RECORD IN THE HIERARCHY
+			 * ENOUGH INFORMATION TO ENSURE THAT ACCELERATION IS NOT BROKEN / DOES NOT OCCUR AT ALL.
+			 * THAT WAY WE DO A HEAVYWEIGHT ESTABLISHING OF A CONNECTION ONCE AND NEVER AGAIN...
+			 */
+			dev_put(src_dev);
+			dev_put(dest_dev);
+			return ECM_DB_IFACE_HEIRARCHY_MAX;
+		}
+	}
+
+	bridge = ecm_interface_should_update_egress_device_bridged(
+		given_dest_dev, dest_dev, is_routed);
+
+	if (bridge) {
+		struct net_device *new_dest_dev;
+		new_dest_dev = br_port_dev_get(bridge, dest_node_addr, skb, serial);
+		if (new_dest_dev) {
+			dev_put(dest_dev);
+			if (new_dest_dev != given_dest_dev) {
+				DEBUG_INFO("Adjusted port for %pM is %s (given was %s)\n",
+					dest_node_addr, new_dest_dev->name,
+					given_dest_dev->name);
+
+				dest_dev = new_dest_dev;
+				dest_dev_name = dest_dev->name;
+				dest_dev_type = dest_dev->type;
+			}
+		}
+		dev_put(bridge);
+	}
+
+	next_dest_addr_valid = true;
+	next_dest_node_addr_valid = false;
+	ECM_IP_ADDR_COPY(next_dest_addr, dest_addr);
+
+	/*
+	 * Iterate until we are done or get to the max number of interfaces we can record.
+	 * NOTE: current_interface_index tracks the position of the first interface position in interfaces[]
+	 * because we add from the end first_interface grows downwards.
+	 */
+	current_interface_index = ECM_DB_IFACE_HEIRARCHY_MAX;
+	while (current_interface_index > 0) {
+		struct ecm_db_iface_instance *ii;
+		struct net_device *next_dev;
+		/*
+		 * Get the ecm db interface instance for the device at hand
+		 */
+		ii = ecm_interface_establish_and_ref(feci, dest_dev, skb);
+
+		/*
+		 * If the interface could not be established then we abort
+		 */
+		if (!ii) {
+			DEBUG_WARN("Failed to establish interface: %px, name: %s\n", dest_dev, dest_dev_name);
+			dev_put(src_dev);
+			dev_put(dest_dev);
+
+			/*
+			 * Release the interfaces heirarchy we constructed to this point.
+			 */
+			ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+			return ECM_DB_IFACE_HEIRARCHY_MAX;
+		}
+
+		/*
+		 * Record the interface instance into the interfaces[]
+		 */
+		current_interface_index--;
+		interfaces[current_interface_index] = ii;
+
+		/*
+		 * Now we have to figure out what the next device will be (in the transmission path) the skb
+		 * will use to emit to the destination address.
+		 */
+		do {
+#ifdef ECM_INTERFACE_PPP_ENABLE
+			int channel_count;
+			struct ppp_channel *ppp_chan[1];
+			int channel_protocol;
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			struct pppoe_opt addressing;
+#endif
+#endif
+
+			DEBUG_TRACE("Net device: %px is type: %d, name: %s\n", dest_dev, dest_dev_type, dest_dev_name);
+			next_dev = NULL;
+
+			if (dest_dev_type == ARPHRD_ETHER) {
+				/*
+				 * Ethernet - but what sub type?
+				 */
+
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+				/*
+				 * VLAN?
+				 */
+				if (is_vlan_dev(dest_dev)) {
+					/*
+					 * VLAN master
+					 * No locking needed here, ASSUMPTION is that real_dev is held for as long as we have dev.
+					 */
+					next_dev = ecm_interface_vlan_real_dev(dest_dev);
+					dev_hold(next_dev);
+					DEBUG_TRACE("Net device: %px is VLAN, slave dev: %px (%s)\n",
+							dest_dev, next_dev, next_dev->name);
+					break;
+				}
+#endif
+
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+				/*
+				 * MAC-VLAN?
+				 */
+				if (netif_is_macvlan(dest_dev)) {
+					if (ecm_interface_macvlan_mode_is_valid(dest_dev)) {
+						next_dev = macvlan_dev_real_dev(dest_dev);
+						dev_hold(next_dev);
+						DEBUG_TRACE("%px: Net device: %px is MAC-VLAN, slave dev: %px (%s)\n",
+								feci, dest_dev, next_dev, next_dev->name);
+						break;
+					}
+				}
+#endif
+
+				/*
+				 * BRIDGE?
+				 */
+				if (ecm_front_end_is_bridge_device(dest_dev)) {
+					/*
+					 * Bridge
+					 * Figure out which port device the skb will go to using the dest_addr.
+					 */
+					uint8_t mac_addr[ETH_ALEN];
+
+					if (next_dest_node_addr_valid) {
+						memcpy(mac_addr, next_dest_node_addr, ETH_ALEN);
+					} else if (!next_dest_addr_valid) {
+						dev_put(src_dev);
+						dev_put(dest_dev);
+
+						/*
+						 * Release the interfaces heirarchy we constructed to this point.
+						 */
+						ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+						return ECM_DB_IFACE_HEIRARCHY_MAX;
+					} else {
+						if (!ecm_interface_multicast_get_next_node_mac_address(next_dest_addr, dest_dev, ip_version, mac_addr)) {
+							dev_put(src_dev);
+							dev_put(dest_dev);
+
+							/*
+							 * Release the interfaces heirarchy we constructed to this point.
+							 */
+							ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+							return ECM_DB_IFACE_HEIRARCHY_MAX;
+						}
+					}
+					next_dev = br_port_dev_get(dest_dev,
+						mac_addr, skb, serial);
+					if (!next_dev) {
+						DEBUG_WARN("Unable to obtain output port for: %pM\n", mac_addr);
+						dev_put(src_dev);
+						dev_put(dest_dev);
+
+						/*
+						 * Release the interfaces heirarchy we constructed to this point.
+						 */
+						ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+						return ECM_DB_IFACE_HEIRARCHY_MAX;
+					}
+					DEBUG_TRACE("Net device: %px is BRIDGE, next_dev: %px (%s)\n", dest_dev, next_dev, next_dev->name);
+					break;
+				}
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+				/*
+				 * OVS_BRIDGE?
+				 */
+				if (ecm_front_end_is_ovs_bridge_device(dest_dev)) {
+					/*
+					 * Bridge
+					 * Figure out which port device the skb will go to using the dest_addr.
+					 */
+					uint8_t mac_addr[ETH_ALEN];
+
+					if (!ecm_interface_multicast_get_next_node_mac_address(next_dest_addr, dest_dev, ip_version, mac_addr)) {
+						dev_put(src_dev);
+						dev_put(dest_dev);
+
+						/*
+						 * Release the interfaces hierarchy we constructed to this point.
+						 */
+						ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+						return ECM_DB_IFACE_HEIRARCHY_MAX;
+					}
+					next_dev = ecm_interface_ovs_bridge_port_dev_get_and_ref(skb, dest_dev, src_addr, dest_addr, ip_version, protocol,
+											 is_routed, src_node_addr, mac_addr, layer4hdr, NULL);
+					if (!next_dev) {
+						DEBUG_WARN("Unable to obtain output port for: %pM\n", mac_addr);
+						dev_put(src_dev);
+						dev_put(dest_dev);
+
+						/*
+						 * Release the interfaces hierarchy we constructed to this point.
+						 */
+						ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+						return ECM_DB_IFACE_HEIRARCHY_MAX;
+					}
+					DEBUG_TRACE("Net device: %px is BRIDGE, next_dev: %px (%s)\n", dest_dev, next_dev, next_dev->name);
+					break;
+				}
+#endif
+
+#ifdef ECM_INTERFACE_BOND_ENABLE
+				/*
+				 * LAG?
+				 */
+				if (ecm_front_end_is_lag_master(dest_dev)) {
+					/*
+					 * Link aggregation
+					 * Figure out whiich slave device of the link aggregation will be used to reach the destination.
+					 */
+					bool dest_on_link = false;
+					ip_addr_t dest_gw_addr = ECM_IP_ADDR_NULL;
+					uint32_t src_addr_32 = 0;
+					uint32_t dest_addr_32 = 0;
+					struct in6_addr src_addr6;
+					struct in6_addr dest_addr6;
+					uint8_t src_mac_addr[ETH_ALEN];
+					uint8_t dest_mac_addr[ETH_ALEN];
+					struct net_device *master_dev = NULL;
+
+					memset(src_mac_addr, 0, ETH_ALEN);
+					memset(dest_mac_addr, 0, ETH_ALEN);
+
+					if (ip_version == 4) {
+						ECM_IP_ADDR_TO_NIN4_ADDR(src_addr_32, src_addr);
+						ECM_IP_ADDR_TO_NIN4_ADDR(dest_addr_32, dest_addr);
+					}
+
+					if (!is_routed) {
+						memcpy(src_mac_addr, src_node_addr, ETH_ALEN);
+						memcpy(dest_mac_addr, dest_node_addr, ETH_ALEN);
+					} else {
+						struct net_device *dest_dev_master;
+
+						/*
+						 * Use appropriate source MAC address for routed packets
+						 */
+						dest_dev_master = ecm_interface_get_and_hold_dev_master(dest_dev);
+						if (dest_dev_master) {
+							memcpy(src_mac_addr, dest_dev_master->dev_addr, ETH_ALEN);
+						} else {
+							memcpy(src_mac_addr, dest_dev->dev_addr, ETH_ALEN);
+						}
+
+						/*
+						 * Determine destination MAC address for this routed packet
+						 */
+						if (next_dest_node_addr_valid) {
+							memcpy(dest_mac_addr, next_dest_node_addr, ETH_ALEN);
+						} else if (!next_dest_addr_valid) {
+							dev_put(src_dev);
+							dev_put(dest_dev);
+							if (dest_dev_master) {
+								dev_put(dest_dev_master);
+							}
+
+							ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+							return ECM_DB_IFACE_HEIRARCHY_MAX;
+						} else {
+							if (!ecm_interface_mac_addr_get(dest_addr, dest_mac_addr,
+										&dest_on_link, dest_gw_addr)) {
+
+								/*
+								 * Find proper interfce from which to issue ARP
+								 * or neighbour solicitation packet.
+								 */
+								if (dest_dev_master) {
+									master_dev = dest_dev_master;
+								} else {
+									master_dev = dest_dev;
+								}
+
+								dev_hold(master_dev);
+
+								if (dest_dev_master) {
+									dev_put(dest_dev_master);
+								}
+
+								if (ip_version == 4) {
+									DEBUG_WARN("Unable to obtain MAC address for " ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(dest_addr));
+									ecm_interface_send_arp_request(dest_dev, dest_addr, dest_on_link, dest_gw_addr);
+								}
+#ifdef ECM_IPV6_ENABLE
+								/*
+								 * If there is a gw on the link, send the neighbor solicitation
+								 * message to that address.
+								 */
+								if (!ECM_IP_ADDR_IS_NULL(dest_gw_addr)) {
+									ECM_IP_ADDR_COPY(dest_addr, dest_gw_addr);
+								}
+
+								if (ip_version == 6) {
+									DEBUG_WARN("Unable to obtain MAC address for " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(dest_addr));
+									ecm_interface_send_neighbour_solicitation(master_dev, dest_addr);
+								}
+#endif
+								dev_put(src_dev);
+								dev_put(dest_dev);
+								dev_put(master_dev);
+								ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+								return ECM_DB_IFACE_HEIRARCHY_MAX;
+							}
+						}
+
+						if (dest_dev_master) {
+							dev_put(dest_dev_master);
+						}
+					}
+
+					if (ip_version == 4) {
+						next_dev = bond_get_tx_dev(NULL, src_mac_addr, dest_mac_addr,
+										&src_addr_32, &dest_addr_32,
+										htons((uint16_t)ETH_P_IP), dest_dev, layer4hdr);
+					} else if (ip_version == 6) {
+						ECM_IP_ADDR_TO_NIN6_ADDR(src_addr6, src_addr);
+						ECM_IP_ADDR_TO_NIN6_ADDR(dest_addr6, dest_addr);
+						next_dev = bond_get_tx_dev(NULL, src_mac_addr, dest_mac_addr,
+									   src_addr6.s6_addr, dest_addr6.s6_addr,
+									   htons((uint16_t)ETH_P_IPV6), dest_dev, layer4hdr);
+					}
+
+					if (next_dev && netif_carrier_ok(next_dev)) {
+						dev_hold(next_dev);
+					} else {
+						DEBUG_WARN("Unable to obtain LAG output slave device\n");
+						dev_put(src_dev);
+						dev_put(dest_dev);
+
+						/*
+						 * Release the interfaces heirarchy we constructed to this point.
+						 */
+						ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+						return ECM_DB_IFACE_HEIRARCHY_MAX;
+					}
+
+					DEBUG_TRACE("Net device: %px is LAG, slave dev: %px (%s)\n", dest_dev, next_dev, next_dev->name);
+					break;
+				}
+#endif
+
+				/*
+				 * ETHERNET!
+				 * Just plain ethernet it seems.
+				 */
+				DEBUG_TRACE("Net device: %px is ETHERNET\n", dest_dev);
+				break;
+			}
+
+			/*
+			 * LOOPBACK?
+			 */
+			if (dest_dev_type == ARPHRD_LOOPBACK) {
+				DEBUG_TRACE("Net device: %px is LOOPBACK type: %d\n", dest_dev, dest_dev_type);
+				break;
+			}
+
+			/*
+			 * IPSEC?
+			 */
+			if (dest_dev_type == ECM_ARPHRD_IPSEC_TUNNEL_TYPE) {
+				DEBUG_TRACE("Net device: %px is IPSec tunnel type: %d\n", dest_dev, dest_dev_type);
+				/* TODO Figure out the next device the tunnel is using... */
+				break;
+			}
+
+			/*
+			 * SIT (6-in-4)?
+			 */
+			if (dest_dev_type == ARPHRD_SIT) {
+				DEBUG_TRACE("Net device: %px is SIT (6-in-4) type: %d\n", dest_dev, dest_dev_type);
+				/* TODO Figure out the next device the tunnel is using... */
+				break;
+			}
+
+			/*
+			 * IPIP6 Tunnel?
+			 */
+			if (dest_dev_type == ARPHRD_TUNNEL6) {
+				DEBUG_TRACE("Net device: %px is TUNIPIP6 type: %d\n", dest_dev, dest_dev_type);
+				/* TODO Figure out the next device the tunnel is using... */
+				break;
+			}
+
+			/*
+			 * If this is NOT PPP then it is unknown to the ecm and we cannot figure out it's next device.
+			 */
+			if (dest_dev_type != ARPHRD_PPP) {
+				DEBUG_TRACE("Net device: %px is UNKNOWN type: %d\n", dest_dev, dest_dev_type);
+				break;
+			}
+
+#ifndef ECM_INTERFACE_PPP_ENABLE
+			DEBUG_TRACE("Net device: %px is UNKNOWN (PPP Unsupported) type: %d\n", dest_dev, dest_dev_type);
+#else
+			DEBUG_TRACE("Net device: %px is PPP\n", dest_dev);
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+			if ((given_src_dev->priv_flags_ext & IFF_EXT_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) {
+				if (skb->skb_iif == dest_dev->ifindex) {
+					DEBUG_TRACE("Net device: %px PPP channel is PPPoL2TPV2\n", dest_dev);
+					break;
+				}
+			}
+#endif
+
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+			if (protocol == IPPROTO_GRE && dest_dev && dest_dev->type == ARPHRD_PPP) {
+				DEBUG_TRACE("Net device: %px PPP channel is PPTP\n", dest_dev);
+				break;
+			}
+#endif
+			/*
+			 * PPP - but what is the channel type?
+			 * First: If this is multi-link then we do not support it
+			 */
+			if (ppp_is_multilink(dest_dev) > 0) {
+				DEBUG_TRACE("Net device: %px is MULTILINK PPP - Unknown to the ECM\n", dest_dev);
+				break;
+			}
+
+			/*
+			 * Get the PPP channel and then enquire what kind of channel it is
+			 * NOTE: Not multilink so only one channel to get.
+			 */
+			channel_count = ppp_hold_channels(dest_dev, ppp_chan, 1);
+			if (channel_count != 1) {
+				DEBUG_TRACE("Net device: %px PPP has %d channels - Unknown to the ECM\n",
+						dest_dev, channel_count);
+				break;
+			}
+
+			/*
+			 * Get channel protocol type
+			 * NOTE: Not all PPP channels support channel specific methods.
+			 */
+			channel_protocol = ppp_channel_get_protocol(ppp_chan[0]);
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+			if (channel_protocol == PX_PROTO_OL2TP) {
+
+				/*
+				 * PPPoL2TPV2 channel
+				 */
+				ppp_release_channels(ppp_chan, 1);
+				DEBUG_TRACE("Net device: %px PPP channel is PPPoL2TPV2\n", dest_dev);
+
+				/*
+				 * Release the channel.  Note that next_dev not held.
+				 */
+				break;
+			}
+#endif
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			if (channel_protocol == PX_PROTO_OE) {
+				/*
+				 * PPPoE channel
+				 */
+				DEBUG_TRACE("Net device: %px PPP channel is PPPoE\n", dest_dev);
+
+				/*
+				 * Get PPPoE session information and the underlying device it is using.
+				 */
+				if (pppoe_channel_addressing_get(ppp_chan[0], &addressing)) {
+					DEBUG_WARN("%px: failed to get PPPoE addressing info\n", dest_dev);
+					ppp_release_channels(ppp_chan, 1);
+					break;
+				}
+
+				/*
+				 * Copy the dev hold into this, we will release the hold later
+				 */
+				next_dev = addressing.dev;
+				next_dest_addr_valid = false;
+				next_dest_node_addr_valid = true;
+				memcpy(next_dest_node_addr, addressing.pa.remote, ETH_ALEN);
+
+				/*
+				 * Release the channel.  Note that next_dev is still (correctly) held.
+				 */
+				ppp_release_channels(ppp_chan, 1);
+				break;
+			}
+#endif
+
+			DEBUG_TRACE("Net device: %px PPP channel protocol: %d - Unknown to the ECM\n",
+				    dest_dev, channel_protocol);
+
+			/*
+			 * Release the channel
+			 */
+			ppp_release_channels(ppp_chan, 1);
+
+#endif
+		} while (false);
+
+		/*
+		 * No longer need dest_dev as it may become next_dev
+		 */
+		dev_put(dest_dev);
+
+		/*
+		 * Check out the next_dev, if any
+		 */
+		if (!next_dev) {
+			int32_t i __attribute__((unused));
+			DEBUG_INFO("Completed interface heirarchy construct with first interface @: %d\n", current_interface_index);
+#if DEBUG_LEVEL > 1
+			for (i = current_interface_index; i < ECM_DB_IFACE_HEIRARCHY_MAX; ++i) {
+				DEBUG_TRACE("\tInterface @ %d: %px, type: %d, name: %s\n",
+						i, interfaces[i], ecm_db_iface_type_get(interfaces[i]), ecm_db_interface_type_to_string(ecm_db_iface_type_get(interfaces[i])));
+
+			}
+#endif
+
+			/*
+			 * Release src_dev now
+			 */
+			dev_put(src_dev);
+			return current_interface_index;
+		}
+
+		/*
+		 * dest_dev becomes next_dev
+		 */
+		dest_dev = next_dev;
+		dest_dev_name = dest_dev->name;
+		dest_dev_type = dest_dev->type;
+	}
+
+	DEBUG_WARN("Too many interfaces: %d\n", current_interface_index);
+	DEBUG_ASSERT(current_interface_index == 0, "Bad logic handling current_interface_index: %d\n", current_interface_index);
+	dev_put(src_dev);
+	dev_put(dest_dev);
+
+	/*
+	 * Release the interfaces heirarchy we constructed to this point.
+	 */
+	ecm_db_connection_interfaces_deref(interfaces, current_interface_index);
+	return ECM_DB_IFACE_HEIRARCHY_MAX;
+}
+EXPORT_SYMBOL(ecm_interface_multicast_from_heirarchy_construct);
+#endif
+
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+static void ecm_interface_ovpn_stats_update(struct net_device *dev, ip_addr_t from_addr, ip_addr_t to_addr)
+{
+	struct in6_addr from_addr6, to_addr6;
+
+	if (ECM_IP_ADDR_IS_V4(from_addr)) {
+		__be32 ip_from_addr, ip_to_addr;
+
+		DEBUG_TRACE("IPv4 Address: " ECM_IP_ADDR_DOT_FMT " : " ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(from_addr), ECM_IP_ADDR_TO_DOT(to_addr));
+		ECM_IP_ADDR_TO_NIN4_ADDR(ip_from_addr, from_addr);
+		ECM_IP_ADDR_TO_NIN4_ADDR(ip_to_addr, to_addr);
+		ecm_interface_ovpn_update_route(dev, &ip_from_addr, &ip_to_addr, 4);
+		return;
+	}
+
+	DEBUG_TRACE("IPv6 Address: " ECM_IP_ADDR_OCTAL_FMT " : " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(from_addr), ECM_IP_ADDR_TO_OCTAL(to_addr));
+	ECM_IP_ADDR_TO_NIN6_ADDR(from_addr6, from_addr);
+	ECM_IP_ADDR_TO_NIN6_ADDR(to_addr6, to_addr);
+	ecm_interface_ovpn_update_route(dev, (uint32_t *)&from_addr6, (uint32_t *)&to_addr6, 6);
+}
+#endif
+
+/*
+ * ecm_interface_list_stats_update()
+ *	Given an interface list, walk the interfaces and update the stats for certain types.
+ */
+static void ecm_interface_list_stats_update(int iface_list_first, struct ecm_db_iface_instance *iface_list[],
+					uint8_t *mac_addr, bool is_mcast_to_if, uint32_t tx_packets, uint32_t tx_bytes, uint32_t rx_packets,
+					uint32_t rx_bytes, bool is_ported, struct ecm_db_connection_instance *ci, ecm_db_obj_dir_t dir)
+{
+	int list_index;
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+	bool update_mcast_rx_stats = false;
+#endif
+
+	uint32_t stats_bitmap = ci->feci->get_stats_bitmap(ci->feci, dir);
+
+	for (list_index = iface_list_first; (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+		struct net_device *dev;
+		struct rtnl_link_stats64 stats;
+
+		ii = iface_list[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("list_index: %d, ii: %px, type: %d (%s)\n", list_index, ii, ii_type, ii_name);
+
+		/*
+		 * Locate real device in system
+		 */
+		dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+		if (!dev) {
+			DEBUG_WARN("Could not locate interface\n");
+			continue;
+		}
+		DEBUG_TRACE("found dev: %px (%s)\n", dev, dev->name);
+
+		if (likely(!is_mcast_to_if)) {
+
+			/*
+			 * Skip bridge forwarding table update if SFE L2 feature is disabled and the flow is route+bridge
+			 */
+			if (ci->feci->accel_engine == ECM_FRONT_END_ENGINE_SFE) {
+				if (ci->is_routed && !(stats_bitmap & BIT(ECM_DB_IFACE_TYPE_BRIDGE))) {
+					goto skip_bridge_refresh;
+				}
+			}
+
+			/*
+			 * Refresh the bridge forward table entry if the port is a bridge port.
+			 * Refresh if the ci is a 3-tuple PPPoE bridge flow.
+			 * Note: A bridge port can be of different interface type, e.g VLAN, ethernet.
+			 * This check, therefore, should be performed for all interface types.
+			 */
+			if ((is_ported || ecm_db_connection_is_pppoe_bridged_get(ci)) &&
+				is_valid_ether_addr(mac_addr) && ecm_front_end_is_bridge_port(dev) && rx_packets) {
+
+				DEBUG_TRACE("Update bridge fdb entry for mac: %pM\n", mac_addr);
+				/*
+				 * Update the existing fdb entry's timestamp only.
+				 */
+				br_fdb_entry_refresh(dev, mac_addr, 0);
+			}
+		}
+
+skip_bridge_refresh:
+
+		memset(&stats, 0, sizeof(stats));
+
+		/*
+		 * Update stats for interfaces supported by both NSS and SFE
+		 */
+		switch (ii_type) {
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+		case ECM_DB_IFACE_TYPE_MACVLAN:
+			DEBUG_INFO("MACVLAN\n");
+
+			if (ci->feci->accel_engine == ECM_FRONT_END_ENGINE_SFE) {
+				if (!(stats_bitmap & BIT(ECM_DB_IFACE_TYPE_MACVLAN))) {
+					dev_put(dev);
+					continue;
+				}
+			}
+
+			stats.rx_packets = rx_packets;
+			stats.rx_bytes = rx_bytes;
+			stats.tx_packets = tx_packets;
+			stats.tx_bytes = tx_bytes;
+#ifdef ECM_MULTICAST_ENABLE
+			/*
+			 * Update multicast rx statistics only for
+			 * 'from' interface.
+			 */
+			update_mcast_rx_stats = (!is_mcast_to_if &&
+						ecm_db_multicast_connection_to_interfaces_set_check(ci));
+#endif
+			macvlan_offload_stats_update(dev, &stats, update_mcast_rx_stats);
+
+			/*
+			 * Continue updating stats for other interface.
+			 */
+			dev_put(dev);
+			continue;
+#endif
+
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_INFO("BRIDGE\n");
+			if (ci->feci->accel_engine == ECM_FRONT_END_ENGINE_SFE) {
+				if (!(stats_bitmap & BIT(ECM_DB_IFACE_TYPE_BRIDGE))) {
+					dev_put(dev);
+					continue;
+				}
+			}
+
+			stats.rx_packets = rx_packets;
+			stats.rx_bytes = rx_bytes;
+			stats.tx_packets = tx_packets;
+			stats.tx_bytes = tx_bytes;
+			br_dev_update_stats(dev, &stats);
+			dev_put(dev);
+			continue;
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+			DEBUG_INFO("OVS BRIDGE\n");
+			if (ci->feci->accel_engine == ECM_FRONT_END_ENGINE_SFE) {
+				if (!(stats_bitmap & BIT(ECM_DB_IFACE_TYPE_OVS_BRIDGE))) {
+					dev_put(dev);
+					continue;
+				}
+			}
+			ovsmgr_bridge_interface_stats_update(dev, rx_packets, rx_bytes, tx_packets, tx_bytes);
+			dev_put(dev);
+			continue;
+#endif
+
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		case ECM_DB_IFACE_TYPE_VLAN:
+			DEBUG_INFO("VLAN\n");
+			/*
+			 * Update vlan device with stats from SFE AE only when
+			 * SFE's l2_feature_support is enabled.
+			 */
+			if (ci->feci->accel_engine == ECM_FRONT_END_ENGINE_SFE) {
+				if (!(stats_bitmap & BIT(ECM_DB_IFACE_TYPE_VLAN))) {
+					dev_put(dev);
+					continue;
+				}
+			}
+			stats.rx_packets = rx_packets;
+			stats.rx_bytes = rx_bytes;
+			stats.tx_packets = tx_packets;
+			stats.tx_bytes = tx_bytes;
+			__vlan_dev_update_accel_stats(dev, &stats);
+			dev_put(dev);
+			continue;
+#endif
+
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+		case ECM_DB_IFACE_TYPE_PPPOE:
+			DEBUG_INFO("PPPOE\n");
+			if (ci->feci->accel_engine == ECM_FRONT_END_ENGINE_SFE) {
+				if (!(stats_bitmap & BIT(ECM_DB_IFACE_TYPE_PPPOE))) {
+					dev_put(dev);
+					continue;
+				}
+			}
+			ppp_update_stats(dev, rx_packets, rx_bytes, tx_packets, tx_bytes, 0, 0, 0, 0);
+			dev_put(dev);
+			continue;
+#endif
+
+		default:
+			break;
+		}
+
+		/*
+		 * Update stats for the interfaces supported by only the NSS acceleration engine.
+		 */
+		if (ci->feci->accel_engine != ECM_FRONT_END_ENGINE_NSS ) {
+			DEBUG_TRACE("Invalid stats update for iface type=%d\n", ii_type);
+			dev_put(dev);
+			continue;
+		}
+
+		switch (ii_type) {
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+		case ECM_DB_IFACE_TYPE_OVPN: {
+			ip_addr_t from_addr, to_addr;
+
+			DEBUG_INFO("OVPN\n");
+			ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, from_addr);
+			ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, to_addr);
+			ecm_interface_ovpn_stats_update(dev, from_addr, to_addr);
+		}
+		break;
+#endif
+		default:
+			/*
+			 * TODO: Extend it accordingly
+			 */
+			break;
+		}
+		dev_put(dev);
+	}
+}
+
+/*
+ * ecm_interface_stats_update()
+ *	Using the interface lists for the given connection, update the interface statistics for each.
+ *
+ * 'from' here is wrt the connection 'from' side.  Likewise with 'to'.
+ * TX is wrt what the interface has transmitted.  RX is what the interface has received.
+ */
+void ecm_interface_stats_update(struct ecm_db_connection_instance *ci,
+						uint32_t from_tx_packets, uint32_t from_tx_bytes, uint32_t from_rx_packets, uint32_t from_rx_bytes,
+						uint32_t to_tx_packets, uint32_t to_tx_bytes, uint32_t to_rx_packets, uint32_t to_rx_bytes)
+{
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	int from_ifaces_first;
+	int to_ifaces_first;
+	uint8_t mac_addr[ETH_ALEN];
+	bool is_ported = false;
+	uint8_t protocol = ecm_db_connection_protocol_get(ci);
+
+	/*
+	 * Set is_ported flag based on protocol.
+	 */
+	if ((protocol == IPPROTO_UDP) || (protocol == IPPROTO_TCP)) {
+		is_ported = true;
+	}
+
+	/*
+	 * Iterate the 'from' side interfaces and update statistics and state for the real HLOS interfaces
+	 * from_tx_packets / bytes: the amount transmitted by the 'from' interface
+	 * from_rx_packets / bytes: the amount received by the 'from' interface
+	 */
+	DEBUG_INFO("%px: Update from interface stats\n", ci);
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, mac_addr);
+	ecm_interface_list_stats_update(from_ifaces_first, from_ifaces, mac_addr, false, from_tx_packets, from_tx_bytes, from_rx_packets, from_rx_bytes, is_ported, ci, ECM_DB_OBJ_DIR_FROM);
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+
+	/*
+	 * Iterate the 'to' side interfaces and update statistics and state for the real HLOS interfaces
+	 * to_tx_packets / bytes: the amount transmitted by the 'to' interface
+	 * to_rx_packets / bytes: the amount received by the 'to' interface
+	 */
+	DEBUG_INFO("%px: Update to interface stats\n", ci);
+	to_ifaces_first = ecm_db_connection_interfaces_get_and_ref(ci, to_ifaces, ECM_DB_OBJ_DIR_TO);
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, mac_addr);
+	ecm_interface_list_stats_update(to_ifaces_first, to_ifaces, mac_addr, false, to_tx_packets, to_tx_bytes, to_rx_packets, to_rx_bytes, is_ported, ci, ECM_DB_OBJ_DIR_TO);
+	ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+}
+EXPORT_SYMBOL(ecm_interface_stats_update);
+
+#ifdef ECM_MULTICAST_ENABLE
+/*
+ * ecm_interface_multicast_stats_update()
+ *	Using the interface lists for the given connection, update the interface statistics for each.
+ *
+ * 'from interface' here is the connection 'from' side.  Likewise with 'to interface'.
+ * TX is wrt what the interface has transmitted.  RX is what the interface has received.
+ */
+void ecm_interface_multicast_stats_update(struct ecm_db_connection_instance *ci, uint32_t from_tx_packets, uint32_t from_tx_bytes,
+				   uint32_t from_rx_packets, uint32_t from_rx_bytes, uint32_t to_tx_packets, uint32_t to_tx_bytes,
+				   uint32_t to_rx_packets, uint32_t to_rx_bytes)
+{
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *to_list_single[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *to_ifaces;
+	struct ecm_db_iface_instance *ii_temp;
+	int from_ifaces_first;
+	int *to_ifaces_first;
+	int if_index;
+	int ret;
+	uint8_t mac_addr[ETH_ALEN];
+	bool is_ported = false;
+	uint8_t protocol = ecm_db_connection_protocol_get(ci);
+
+	/*
+	 * Set is_ported flag based on protocol
+	 */
+	if (protocol == IPPROTO_UDP) {
+		is_ported = true;
+	}
+
+	/*
+	 * Iterate the 'from' side interfaces and update statistics and state for the real HLOS interfaces
+	 * from_tx_packets / bytes: the amount transmitted by the 'from' interface
+	 * from_rx_packets / bytes: the amount received by the 'from' interface
+	 */
+	DEBUG_INFO("%px: Update from interface stats\n", ci);
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, mac_addr);
+	ecm_interface_list_stats_update(from_ifaces_first, from_ifaces, mac_addr, false, 0, 0, from_rx_packets, from_rx_bytes, is_ported, ci, ECM_DB_OBJ_DIR_FROM);
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+
+	/*
+	 * Iterate the 'to' side interfaces and update statistics and state for the real HLOS interfaces
+	 * to_tx_packets / bytes: the amount transmitted by the 'to' interface
+	 * to_rx_packets / bytes: the amount received by the 'to' interface
+	 */
+	DEBUG_INFO("%px: Update to interface stats\n", ci);
+
+	/*
+	 * This function allocates the memory for temporary destination interface heirarchies.
+	 * This memory needs to be free at the end.
+	 */
+	ret = ecm_db_multicast_connection_to_interfaces_get_and_ref_all(ci, &to_ifaces, &to_ifaces_first);
+	if (ret == 0) {
+		DEBUG_WARN("%px: Get and ref to all multicast detination interface heirarchies failed\n", ci);
+		return;
+	}
+
+	for (if_index = 0; if_index < ECM_DB_MULTICAST_IF_MAX; if_index++) {
+		if (to_ifaces_first[if_index] < ECM_DB_IFACE_HEIRARCHY_MAX) {
+			ii_temp = ecm_db_multicast_if_heirarchy_get(to_ifaces, if_index);
+			ecm_db_multicast_copy_if_heirarchy(to_list_single, ii_temp);
+			ecm_interface_list_stats_update(to_ifaces_first[if_index], to_list_single, mac_addr, true, from_tx_packets, from_tx_bytes, 0, 0, is_ported, ci, ECM_DB_OBJ_DIR_TO);
+		}
+	}
+
+	ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+}
+EXPORT_SYMBOL(ecm_interface_multicast_stats_update);
+#endif
+
+/*
+ * ecm_interface_regenerate_connections()
+ *	Cause regeneration of all connections that are using the specified interface.
+ */
+static void ecm_interface_regenerate_connections(struct ecm_db_iface_instance *ii)
+{
+#ifdef ECM_DB_XREF_ENABLE
+	int dir;
+	struct ecm_db_connection_instance *ci[ECM_DB_OBJ_DIR_MAX];
+	struct ecm_db_connection_instance *ci_mcast __attribute__ ((unused));
+#endif
+	char name[IFNAMSIZ];
+
+	ecm_db_iface_interface_name_get(ii, name);
+	DEBUG_TRACE("Regenerate connections using interface: %px (%s)\n", ii, name);
+
+#ifndef ECM_DB_XREF_ENABLE
+	/*
+	 * An interface has changed, re-generate the connections to ensure all state is updated.
+	 */
+	ecm_db_regeneration_needed();
+#else
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		ci[dir] = ecm_db_iface_connections_get_and_ref_first(ii, dir);
+	}
+
+	/*
+	 * If the interface has NO connections then we re-generate all.
+	 */
+	if (!ci[ECM_DB_OBJ_DIR_FROM] && !ci[ECM_DB_OBJ_DIR_TO] && !ci[ECM_DB_OBJ_DIR_FROM_NAT] && !ci[ECM_DB_OBJ_DIR_TO_NAT]) {
+		ecm_db_regeneration_needed();
+		DEBUG_TRACE("%px: Regenerate (ALL) COMPLETE\n", ii);
+		return;
+	}
+
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		/*
+		 * Re-generate all connections associated with this interface
+		 */
+		DEBUG_TRACE("%px: Regenerate %s direction connections\n", ii, ecm_db_obj_dir_strings[dir]);
+		while (ci[dir]) {
+			struct ecm_db_connection_instance *cin;
+			cin = ecm_db_connection_iface_get_and_ref_next(ci[dir], dir);
+
+			DEBUG_TRACE("%px: Regenerate: %px", ii, ci[dir]);
+			ecm_db_connection_regenerate(ci[dir]);
+			ecm_db_connection_deref(ci[dir]);
+			ci[dir] = cin;
+		}
+	}
+
+#ifdef ECM_MULTICAST_ENABLE
+	/*
+	 * Multicasts would not have recorded in the lists above.
+	 * Our only way to re-gen those is to iterate all multicasts.
+	 * GGG TODO This will be optimised in a future release.
+	 */
+	ci_mcast = ecm_db_connections_get_and_ref_first();
+	while (ci_mcast) {
+		struct ecm_db_connection_instance *cin;
+
+		/*
+		 * Multicast and NOT flagged for re-gen?
+		 */
+		if (ecm_db_multicast_connection_to_interfaces_set_check(ci_mcast)
+				&& ecm_db_connection_regeneration_required_peek(ci_mcast)) {
+			ecm_db_connection_regenerate(ci_mcast);
+		}
+
+		cin = ecm_db_connection_get_and_ref_next(ci_mcast);
+		ecm_db_connection_deref(ci_mcast);
+		ci_mcast = cin;
+	}
+#endif
+
+#endif
+	DEBUG_TRACE("%px: Regenerate COMPLETE\n", ii);
+}
+
+/*
+ * ecm_interface_dev_regenerate_connections()
+ *	Cause regeneration of all connections that are using the specified interface.
+ */
+void ecm_interface_dev_regenerate_connections(struct net_device *dev)
+{
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("Regenerate connections for: %px (%s)\n", dev, dev->name);
+
+	/*
+	 * If the interface is known to us then we will get it returned by this
+	 * function and process it accordingly.
+	 */
+	ii = ecm_db_iface_find_and_ref_by_interface_identifier(dev->ifindex);
+	if (!ii) {
+		DEBUG_WARN("%px: No interface instance could be established for this dev\n", dev);
+		return;
+	}
+	ecm_interface_regenerate_connections(ii);
+	DEBUG_TRACE("%px: Regenerate for %px: COMPLETE\n", dev, ii);
+	ecm_db_iface_deref(ii);
+}
+
+/*
+ * ecm_interface_defunct_connections()
+ *	Cause defunct of all connections that are using the specified interface.
+ */
+static void ecm_interface_defunct_connections(struct ecm_db_iface_instance *ii)
+{
+#ifndef ECM_DB_XREF_ENABLE
+	ecm_db_connection_defunct_all();
+#else
+	int dir;
+	struct ecm_db_connection_instance *ci[ECM_DB_OBJ_DIR_MAX];
+	struct ecm_db_connection_instance *ci_mcast __attribute__ ((unused));
+	char name[IFNAMSIZ];
+
+	ecm_db_iface_interface_name_get(ii, name);
+	DEBUG_TRACE("defunct connections using interface: %px (%s)\n", ii, name);
+
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		ci[dir] = ecm_db_iface_connections_get_and_ref_first(ii, dir);
+	}
+
+	/*
+	 * Defunct ALL if all the four connection instances are NULL
+	 */
+	if (!ci[ECM_DB_OBJ_DIR_FROM] && !ci[ECM_DB_OBJ_DIR_TO] &&
+			!ci[ECM_DB_OBJ_DIR_FROM_NAT] && !ci[ECM_DB_OBJ_DIR_TO_NAT]) {
+		ecm_db_connection_defunct_all();
+		DEBUG_TRACE("%px: Defunct (ALL) COMPLETE\n", ii);
+		return;
+	}
+
+	/*
+	 * Defunct all connections associated with this interface
+	 */
+	for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) {
+		DEBUG_TRACE("%px: Defunct %s direction connections\n", ii, ecm_db_obj_dir_strings[dir]);
+		while (ci[dir]) {
+			struct ecm_db_connection_instance *cin;
+			cin = ecm_db_connection_iface_get_and_ref_next(ci[dir], dir);
+
+			DEBUG_TRACE("%px: Defunct: %px", ii, ci[dir]);
+			ecm_db_connection_make_defunct(ci[dir]);
+			ecm_db_connection_deref(ci[dir]);
+			ci[dir] = cin;
+		}
+	}
+#endif
+	DEBUG_TRACE("%px: Defunct COMPLETE\n", ii);
+}
+
+/*
+ * ecm_interface_dev_defunct_connections()
+ *	Cause defunct of all connections that are using the specified interface.
+ */
+void ecm_interface_dev_defunct_connections(struct net_device *dev)
+{
+	struct ecm_db_iface_instance *ii;
+
+	DEBUG_INFO("defunct connections for: %px (%s)\n", dev, dev->name);
+
+	/*
+	 * Filter interface instances matching dev and defunct connections
+	 */
+	ii = ecm_db_interfaces_get_and_ref_first();
+	while (ii) {
+		struct ecm_db_iface_instance *iin;
+
+		/*
+		 * Defunct connections if ii is representing dev.
+		 */
+		if (dev->ifindex == ecm_db_iface_interface_identifier_get(ii)) {
+			ecm_interface_defunct_connections(ii);
+			DEBUG_TRACE("%px: defunct for %px: COMPLETE\n", dev, ii);
+		}
+
+		/*
+		 * Find next interface in the list
+		 */
+		iin = ecm_db_interface_get_and_ref_next(ii);
+		ecm_db_iface_deref(ii);
+		ii = iin;
+	}
+}
+
+/*
+ * ecm_interface_mtu_change()
+ *	MTU of interface has changed
+ */
+static void ecm_interface_mtu_change(struct net_device *dev)
+{
+	int mtu;
+	struct ecm_db_iface_instance *ii;
+
+	mtu = dev->mtu;
+	DEBUG_INFO("%px (%s): MTU Change to: %d\n", dev, dev->name, mtu);
+
+	/*
+	 * Filter interface instances matching dev and regenerate connections
+	 */
+	ii = ecm_db_interfaces_get_and_ref_first();
+	while (ii) {
+		struct ecm_db_iface_instance *iin;
+
+		/*
+		 * Defunct connections if ii is representing dev, otherwise
+		 * skip to the next ii.
+		 */
+		if (dev->ifindex != ecm_db_iface_interface_identifier_get(ii)) {
+			goto next;
+		}
+
+		/*
+		 * Change the mtu
+		 */
+		ecm_db_iface_mtu_reset(ii, mtu);
+
+		if (!netif_is_bond_slave(dev)) {
+			ecm_interface_regenerate_connections(ii);
+		} else {
+			struct net_device *master = NULL;
+			master = ecm_interface_get_and_hold_dev_master(dev);
+			DEBUG_ASSERT(master, "Expected a master\n");
+			ecm_interface_dev_regenerate_connections(master);
+			dev_put(master);
+		}
+
+		DEBUG_TRACE("%px: Regenerate for (%s) belong to iface %px COMPLETE\n", dev, dev->name, ii);
+next:
+		iin = ecm_db_interface_get_and_ref_next(ii);
+		ecm_db_iface_deref(ii);
+		ii = iin;
+	}
+}
+
+/*
+ * ecm_interface_netdev_notifier_callback()
+ * 	Netdevice notifier callback to inform us of change of state of a netdevice
+ */
+static int ecm_interface_netdev_notifier_callback(struct notifier_block *this, unsigned long event, void *ptr)
+{
+	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
+	struct net_device *master = NULL;
+
+	DEBUG_INFO("Net device notifier for: %px, name: %s, event: %lx\n", dev, dev->name, event);
+
+	switch (event) {
+	case NETDEV_DOWN:
+		DEBUG_INFO("Net device: %px, DOWN\n", dev);
+		if (netif_is_bond_slave(dev)) {
+			master = ecm_interface_get_and_hold_dev_master(dev);
+			DEBUG_ASSERT(master, "Expected a master\n");
+			ecm_interface_dev_defunct_connections(master);
+			dev_put(master);
+		} else {
+			ecm_interface_dev_defunct_connections(dev);
+		}
+		break;
+
+	case NETDEV_CHANGE:
+		DEBUG_INFO("Net device: %px, CHANGE\n", dev);
+		if (!netif_carrier_ok(dev)) {
+			DEBUG_INFO("Net device: %px, CARRIER BAD\n", dev);
+			if (netif_is_bond_slave(dev)) {
+				master = ecm_interface_get_and_hold_dev_master(dev);
+				DEBUG_ASSERT(master, "Expected a master.\n");
+				ecm_interface_dev_defunct_connections(master);
+				dev_put(master);
+			} else {
+				ecm_interface_dev_defunct_connections(dev);
+			}
+		}
+		break;
+
+	case NETDEV_CHANGEMTU:
+		DEBUG_INFO("Net device: %px, MTU CHANGE\n", dev);
+		ecm_interface_mtu_change(dev);
+		break;
+
+	default:
+		DEBUG_TRACE("Net device: %px, UNHANDLED: %lx\n", dev, event);
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * ecm_interface_node_connections_defunct()
+ *	Defunct the connections on this node.
+ */
+void ecm_interface_node_connections_defunct(uint8_t *mac, int ip_version)
+{
+	struct ecm_db_node_instance *ni = NULL;
+
+	if (unlikely(!mac)) {
+		DEBUG_WARN("mac address is null\n");
+		return;
+	}
+
+	/*
+	 * Disable frontend processing until defunct function call is completed.
+	 */
+	ecm_front_end_ipv4_stop(1);
+#ifdef ECM_IPV6_ENABLE
+	ecm_front_end_ipv6_stop(1);
+#endif
+	ni = ecm_db_node_chain_get_and_ref_first(mac);
+	while (ni) {
+		struct ecm_db_node_instance *nin;
+
+		if (ecm_db_node_is_mac_addr_equal(ni, mac)) {
+			int dir;
+			/*
+			 * FROM and TO directions are enough to destroy all the connections.
+			 * FROM_NAT and TO_NAT have the same list of connections.
+			 */
+			for (dir = 0; dir <= ECM_DB_OBJ_DIR_TO; dir++) {
+				/*
+				 * If there is connection on this node, call the defunct function.
+				 */
+				if (ecm_db_node_get_connections_count(ni, dir)) {
+					ecm_db_traverse_node_connection_list_and_defunct(ni, dir, ip_version);
+				}
+			}
+		}
+
+		/*
+		 * Get next node in the chain
+		 */
+		nin = ecm_db_node_chain_get_and_ref_next(ni);
+		ecm_db_node_deref(ni);
+		ni = nin;
+	}
+
+	/*
+	 * Re-enable frontend processing.
+	 */
+	ecm_front_end_ipv4_stop(0);
+#ifdef ECM_IPV6_ENABLE
+	ecm_front_end_ipv6_stop(0);
+#endif
+}
+EXPORT_SYMBOL(ecm_interface_node_connections_defunct);
+
+/*
+ * struct notifier_block ecm_interface_netdev_notifier
+ *	Registration for net device changes of state.
+ */
+static struct notifier_block ecm_interface_netdev_notifier __read_mostly = {
+	.notifier_call		= ecm_interface_netdev_notifier_callback,
+};
+
+#if defined(ECM_DB_XREF_ENABLE) && defined(ECM_BAND_STEERING_ENABLE)
+/*
+ * ecm_interfae_node_br_fdb_notify_event()
+ *	This is a callback for "bridge fdb update event. It is called
+ *	When a MAC address is moved to another interface.
+ *
+ */
+static int ecm_interface_node_br_fdb_notify_event(struct notifier_block *nb,
+					       unsigned long event,
+					       void *data)
+{
+	struct br_fdb_event *fe = (struct br_fdb_event *)data;
+
+	/*
+	 * Check if original and current devs are not NULL.
+	 */
+	if (!fe->orig_dev || !fe->dev) {
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * If the old and new devs are the same, we don't need to handle this event.
+	 */
+	if (fe->orig_dev == fe->dev) {
+		return NOTIFY_DONE;
+	}
+
+	DEBUG_TRACE("%px: FDB notify event for moved MAC addr: %pM\n", fe, fe->addr);
+	ecm_interface_node_connections_defunct(fe->addr, ECM_DB_IP_VERSION_IGNORE);
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block ecm_interface_node_br_fdb_update_nb = {
+	.notifier_call = ecm_interface_node_br_fdb_notify_event,
+};
+
+/*
+ * ecm_interface_node_br_fdb_delete_event()
+ *	Callback for FDB delete/ageing timeout events.
+ */
+static int ecm_interface_node_br_fdb_delete_event(struct notifier_block *nb,
+					       unsigned long event,
+					       void *data)
+{
+	struct br_fdb_event *fe = (struct br_fdb_event *)data;
+
+	if ((event != BR_FDB_EVENT_DEL) || fe->is_local) {
+		DEBUG_WARN("%px: local fdb or not deleting event, ignore\n", fe);
+		return NOTIFY_DONE;
+	}
+
+	DEBUG_TRACE("%px: FDB delete event for MAC addr: %pM\n", fe, fe->addr);
+	ecm_interface_node_connections_defunct(fe->addr, ECM_DB_IP_VERSION_IGNORE);
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block ecm_interface_node_br_fdb_delete_nb = {
+	.notifier_call = ecm_interface_node_br_fdb_delete_event,
+};
+#endif
+
+#ifdef ECM_MULTICAST_ENABLE
+/*
+ * ecm_interface_multicast_find_outdated_iface_instances()
+ *
+ *	Called in the case of Routing/Bridging Multicast update events.
+ *
+ *	This function takes a list of ifindex for the connection which was received
+ *	from MFC or bridge snooper, compares it against the existing list of interfaces
+ *	in the DB connection, and extracts the list of those interfaces that have left
+ *	the multicast group.
+ *
+ * 	ci		A DB connection instance.
+ * 	mc_updates	Part of return Information. The function will mark the index of those
+ * 			interfaces in the DB connection 'to_mcast_interfaces' array that have
+ * 			left the group, in the mc_updates->if_leave_idx array. The caller uses this
+ * 			information to delete those outdated interface heirarchies from the
+ * 			connection.
+ * 	is_bridged	True if the function called due to bridge multicast snooper update event.
+ * 	dst_dev		Holds the netdevice ifindex number of the new list of interfaces as reported
+ * 			by the update from MFC or Bridge snooper.
+ *	max_to_dev	Size of the array 'dst_dev'
+ *
+ *	Return true if outdated interfaces found
+ */
+static bool ecm_interface_multicast_find_outdated_iface_instances(struct ecm_db_connection_instance *ci, struct ecm_multicast_if_update *mc_updates,
+						   uint32_t flags, bool is_br_snooper, uint32_t *mc_dst_if_index, uint32_t max_to_dev,
+						   struct net_device *brdev)
+{
+	struct ecm_db_iface_instance *mc_ifaces;
+	struct ecm_db_iface_instance *ii_temp;
+	struct ecm_db_iface_instance *ii_single;
+	struct ecm_db_iface_instance **ifaces;
+	struct ecm_db_iface_instance *to_iface;
+	int32_t *to_iface_first;
+	int32_t *mc_ifaces_first;
+	uint32_t *dst_if_index;
+	ecm_db_iface_type_t ii_type;
+	int32_t heirarchy_index;
+	int32_t if_index;
+	int32_t if_cnt = 0;
+	int found = 0;
+	int ii;
+	int ret;
+	int32_t ifaces_identifier;
+
+	ret = ecm_db_multicast_connection_to_interfaces_get_and_ref_all(ci, &mc_ifaces, &mc_ifaces_first);
+	if (ret == 0) {
+		DEBUG_WARN("%px: multicast interfaces ref fail!\n", ci);
+		return false;
+	}
+
+	/*
+	 * Loop through the current interface list in the DB
+	 * connection 'to_mcast_interfaces' array
+	 */
+	for (heirarchy_index = 0; heirarchy_index < ECM_DB_MULTICAST_IF_MAX; heirarchy_index++) {
+		found = 0;
+		to_iface_first = ecm_db_multicast_if_first_get_at_index(mc_ifaces_first, heirarchy_index);
+
+		/*
+		 * Invalid interface entry, skip
+		 */
+		if (*to_iface_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			continue;
+		}
+
+		ii_temp = ecm_db_multicast_if_heirarchy_get(mc_ifaces, heirarchy_index);
+		ii_single = ecm_db_multicast_if_instance_get_at_index(ii_temp, ECM_DB_IFACE_HEIRARCHY_MAX - 1);
+		ifaces = (struct ecm_db_iface_instance **)ii_single;
+		to_iface = *ifaces;
+		ii_type = ecm_db_iface_type_get(to_iface);
+
+		if ((ii_type == ECM_DB_IFACE_TYPE_BRIDGE) || (ii_type == ECM_DB_IFACE_TYPE_OVS_BRIDGE)) {
+			/*
+			 * If the update was received from MFC, do not consider entries in the
+			 * interface list that are part of a bridge/ovs_bridge. The bridge/ovs_bridge entries will be
+			 * taken care by the Bridge Snooper Callback
+			 *
+			 * TODO: Check if an assert is needed for the flag
+			 * ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG to be set, if is_br_snooper is false.
+			 */
+			if (!is_br_snooper && (flags & ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG)) {
+				continue;
+			}
+
+			/*
+			 * If update was received from Bridge snooper.
+			 * Check for the correct bridge interface in the 'to' list
+			 * as ECM support multibridge multicast.
+			 */
+			if (is_br_snooper) {
+				struct net_device *to_dev;
+
+				to_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(to_iface));
+				if (to_dev) {
+					if (to_dev->ifindex != brdev->ifindex) {
+						dev_put(to_dev);
+						continue;
+					}
+					dev_put(to_dev);
+				}
+			}
+		} else if (is_br_snooper) {
+			/*
+			 * If the update was received from bridge snooper, do not consider entries in the
+			 * interface list that are not part of a bridge or ovs bridge.
+			 */
+			continue;
+		}
+
+		/*
+		 * Try to find a match in the newly received interface list, for any of
+		 * the interface instance in the heirarchy. If found, it means that this
+		 * interface has not left the group. If not found, it means that this
+		 * interface has left the group.
+		 */
+		for (ii = ECM_DB_IFACE_HEIRARCHY_MAX - 1; ii >= *to_iface_first; ii--) {
+			ii_single = ecm_db_multicast_if_instance_get_at_index(ii_temp, ii);
+			ifaces = (struct ecm_db_iface_instance **)ii_single;
+			to_iface = *ifaces;
+
+			ii_type = ecm_db_iface_type_get(to_iface);
+			ifaces_identifier = ecm_db_iface_interface_identifier_get(to_iface);
+			for (if_index = 0; if_index < max_to_dev; if_index++) {
+				dst_if_index = ecm_db_multicast_if_num_get_at_index(mc_dst_if_index, if_index);
+				if (*dst_if_index == ifaces_identifier) {
+					found = 1;
+					break;
+				}
+			}
+			if (found) {
+				break;
+			}
+		}
+
+		/*
+		 * We did not find a match for the interface in the present list. So mark
+		 * if as one that has left the group.
+		 */
+		if (!found) {
+			if_cnt++;
+			mc_updates->if_leave_idx[heirarchy_index] = 1;
+		}
+	}
+
+	ecm_db_multicast_connection_to_interfaces_deref_all(mc_ifaces, mc_ifaces_first);
+	mc_updates->if_leave_cnt = if_cnt;
+	return (if_cnt > 0);
+}
+
+/*
+ * ecm_interface_multicast_find_new_iface_instances()
+ *
+ *	Called in the case of Routing/Bridging Multicast update events.
+ *
+ *	This function takes a list of ifindex for the connection which was received
+ *	from MFC or bridge snooper, compares it against the existing list of interfaces
+ *	in the DB connection, and extracts the list of the new joinees for the multicast
+ *	group.
+ *
+ * 	ci		A DB connection instance.
+ * 	mc_updates	Part of return Information. The function will mark the index of those
+ * 			interfaces in the 'dst_dev' array that have joined the group, in the
+ * 			mc_updates->if_join_idx array. The caller uses this information to add the new
+ * 			interface heirarchies into the connection.
+ * 	dst_dev		Holds the netdevice ifindex number of the new list of interfaces as reported
+ * 			by the update from MFC or Bridge snooper.
+ *	max_to_dev	Size of the array 'dst_dev'
+ *
+ *	Return true if new joinees found
+ */
+static bool ecm_interface_multicast_find_new_iface_instances(struct ecm_db_connection_instance *ci,
+					struct ecm_multicast_if_update *mc_updates, uint32_t *mc_dst_if_index, uint32_t max_to_dev)
+{
+	struct ecm_db_iface_instance *mc_ifaces;
+	struct ecm_db_iface_instance *ii_temp;
+	struct ecm_db_iface_instance *ii_single;
+	struct ecm_db_iface_instance **ifaces;
+	int32_t *mc_ifaces_first;
+	int32_t *to_list_first;
+	int32_t heirarchy_index;
+	int32_t if_index;
+	int32_t if_cnt = 0;
+	int found = 0;
+	int ii;
+	int ret;
+	uint32_t *dst_if_index;
+	int32_t ifaces_identifier;
+	struct ecm_db_iface_instance *to_list;
+
+	ret = ecm_db_multicast_connection_to_interfaces_get_and_ref_all(ci, &mc_ifaces, &mc_ifaces_first);
+	if (ret == 0) {
+		DEBUG_WARN("%px: multicast interfaces ref fail!\n", ci);
+		return false;
+	}
+
+	/*
+	 * Loop through the new interface list 'dst_dev'
+	 */
+	for (if_index = 0; if_index < max_to_dev; if_index++) {
+		found = 0;
+		dst_if_index = ecm_db_multicast_if_num_get_at_index(mc_dst_if_index, if_index);
+		if (*dst_if_index == 0) {
+			continue;
+		}
+
+		for (heirarchy_index = 0; heirarchy_index < ECM_DB_MULTICAST_IF_MAX ; heirarchy_index++) {
+			to_list_first = ecm_db_multicast_if_first_get_at_index(mc_ifaces_first, heirarchy_index);
+
+			/*
+			 * Invalid interface entry, skip
+			 */
+			if (*to_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+				continue;
+			}
+
+			ii_temp = ecm_db_multicast_if_heirarchy_get(mc_ifaces, heirarchy_index);
+
+			/*
+			 * Try to find a match for this ifindex (dst_dev[if_index]), in any of the
+			 * interface instance in the heirarchy. If not found, it means that this
+			 * ifindex has joined the group. If found, it means that this ifindex was
+			 * already part of the list of destination interfaces.
+			 */
+			for (ii = ECM_DB_IFACE_HEIRARCHY_MAX - 1; ii >= *to_list_first; ii--) {
+				ii_single = ecm_db_multicast_if_instance_get_at_index(ii_temp, ii);
+				ifaces = (struct ecm_db_iface_instance **)ii_single;
+				to_list = *ifaces;
+				ifaces_identifier = ecm_db_iface_interface_identifier_get(to_list);
+				if (*dst_if_index == ifaces_identifier) {
+					found =  1;
+					break;
+				}
+			}
+
+			if (found) {
+				break;
+			}
+		}
+
+		/*
+		 * We did not find a match for the interface in the present list. So mark
+		 * it as one that has joined the group.
+		 */
+		if (!found) {
+
+			/*
+			 * Store the if index of the new joinee
+			 */
+			mc_updates->join_dev[if_cnt] = *dst_if_index;
+
+			/*
+			 * Identify a new vacant slot in the 'to_mcast_interfaces' to place
+			 * the new interface
+			 */
+			for (heirarchy_index = 0; heirarchy_index < ECM_DB_MULTICAST_IF_MAX ; heirarchy_index++) {
+				to_list_first = ecm_db_multicast_if_first_get_at_index(mc_ifaces_first, heirarchy_index);
+				if (*to_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+					mc_updates->if_join_idx[heirarchy_index] = 1;
+					break;
+				}
+			}
+
+			if_cnt++;
+		}
+	}
+
+	ecm_db_multicast_connection_to_interfaces_deref_all(mc_ifaces, mc_ifaces_first);
+	mc_updates->if_join_cnt = if_cnt;
+
+	return (if_cnt > 0);
+}
+
+/*
+ * ecm_interface_multicast_find_updates_to_iface_list()
+ * 	Process IGMP/MLD updates either from MFC or bridge snooper. Identity the interfaces
+ * 	that have left the group and new interfaces that have joined the group.
+ *
+ * The function returns true if there was any update necessary to the current destination
+ * interface list
+ */
+bool ecm_interface_multicast_find_updates_to_iface_list(struct ecm_db_connection_instance *ci, struct ecm_multicast_if_update *mc_updates,
+						uint32_t flags, bool is_br_snooper, uint32_t *mc_dst_if_index, uint32_t max_to_dev,
+						struct net_device *brdev)
+{
+	bool join;
+	bool leave;
+
+	/*
+	 * Find destination interfaces that have left the group
+	 */
+	leave = ecm_interface_multicast_find_outdated_iface_instances(ci, mc_updates, flags, is_br_snooper, mc_dst_if_index, max_to_dev, brdev);
+
+	/*
+	 * Find new destination interfaces that have joined the group
+	 */
+	join = ecm_interface_multicast_find_new_iface_instances(ci, mc_updates, mc_dst_if_index, max_to_dev);
+
+	return (leave || join);
+}
+EXPORT_SYMBOL(ecm_interface_multicast_find_updates_to_iface_list);
+#endif
+
+#ifdef ECM_DB_XREF_ENABLE
+/*
+ * ecm_interface_neigh_mac_update_notify_event()
+ *	Neighbour mac address change handler.
+ */
+static int ecm_interface_neigh_mac_update_notify_event(struct notifier_block *nb,
+						       unsigned long val,
+						       void *data)
+{
+	struct neigh_mac_update *nmu = (struct neigh_mac_update *)data;
+
+	/*
+	 * If the old and new mac addresses are equal, do nothing.
+	 * This case shouldn't happen.
+	 */
+	if (!ecm_mac_addr_equal(nmu->old_mac, nmu->update_mac)) {
+		DEBUG_TRACE("old and new mac addresses are equal: %pM\n", nmu->old_mac);
+		return NOTIFY_DONE;
+	}
+
+	/*
+	 * If the old mac is zero, do nothing. When a host joins the arp table first
+	 * time, its old mac comes as zero. We shouldn't handle this case, because
+	 * there is not any connection in ECM db with zero mac.
+	 */
+	if (is_zero_ether_addr(nmu->old_mac)) {
+		DEBUG_WARN("old mac is zero\n");
+		return NOTIFY_DONE;
+	}
+
+	DEBUG_TRACE("old mac: %pM new mac: %pM\n", nmu->old_mac, nmu->update_mac);
+
+	DEBUG_INFO("neigh mac update notify for node %pM\n", nmu->old_mac);
+	ecm_interface_node_connections_defunct((uint8_t *)nmu->old_mac, ECM_DB_IP_VERSION_IGNORE);
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * struct notifier_block ecm_interface_neigh_mac_update_nb
+ *	Registration for neighbour mac address update.
+ */
+static struct notifier_block ecm_interface_neigh_mac_update_nb = {
+	.notifier_call = ecm_interface_neigh_mac_update_notify_event,
+};
+#endif
+
+/*
+ * ecm_interface_wifi_event_iwevent
+ *	wireless event handler
+ */
+static int ecm_interface_wifi_event_iwevent(int ifindex, unsigned char *buf, size_t len)
+{
+	struct iw_event iwe_buf, *iwe = &iwe_buf;
+	char *pos, *end;
+
+	pos = buf;
+	end = buf + len;
+	while (pos + IW_EV_LCP_LEN <= end) {
+
+		/*
+		 * Copy the base data structure to get iwe->len
+		 */
+		memcpy(&iwe_buf, pos, IW_EV_LCP_LEN);
+
+		/*
+		 * Check that len is valid and that we have that much in the buffer.
+		 *
+		 */
+		if (iwe->len < IW_EV_LCP_LEN) {
+			return -1;
+		}
+
+		if ((iwe->len > sizeof (struct iw_event)) || (iwe->len + pos) > end) {
+			return -1;
+		}
+
+		/*
+		 * Do the copy again with the full length.
+		 */
+		memcpy(&iwe_buf, pos, iwe->len);
+
+		if (iwe->cmd == IWEVREGISTERED) {
+			DEBUG_INFO("STA %pM joining\n", (uint8_t *)iwe->u.addr.sa_data);
+		} else if (iwe->cmd == IWEVEXPIRED) {
+			DEBUG_INFO("STA %pM leaving\n", (uint8_t *)iwe->u.addr.sa_data);
+			ecm_interface_node_connections_defunct((uint8_t *)iwe->u.addr.sa_data, ECM_DB_IP_VERSION_IGNORE);
+		} else {
+			DEBUG_INFO("iwe->cmd is %d for STA %pM\n", iwe->cmd, (unsigned char *) iwe->u.addr.sa_data);
+		}
+
+		pos += iwe->len;
+	}
+
+	return 0;
+}
+
+/*
+ * ecm_interface_wifi_event_newlink
+ *	Link event handler
+ */
+static int ecm_interface_wifi_event_newlink(struct ifinfomsg *ifi, unsigned char *buf, size_t len)
+{
+	struct rtattr *attr;
+	int attrlen, rta_len;
+
+	DEBUG_TRACE("Event from interface %d\n", ifi->ifi_index);
+
+	attrlen = len;
+	attr = (struct rtattr *) buf;
+	rta_len = RTA_ALIGN(sizeof(struct rtattr));
+
+	while (RTA_OK(attr, attrlen)) {
+		if (attr->rta_type == IFLA_WIRELESS) {
+			ecm_interface_wifi_event_iwevent(ifi->ifi_index, ((char *) attr) + rta_len, attr->rta_len - rta_len);
+		}
+		attr = RTA_NEXT(attr, attrlen);
+	}
+
+	return 0;
+}
+
+/*
+ * ecm_interface_wifi_event_handler
+ *	Netlink event handler
+ */
+static int ecm_interface_wifi_event_handler(unsigned char *buf, int len)
+{
+	struct nlmsghdr *nlh;
+	struct ifinfomsg *ifi;
+	int left;
+
+	nlh = (struct nlmsghdr *) buf;
+	left = len;
+
+	while (NLMSG_OK(nlh, left)) {
+		switch (nlh->nlmsg_type) {
+		case RTM_NEWLINK:
+		case RTM_DELLINK:
+			if (NLMSG_PAYLOAD(nlh, 0) < sizeof(struct ifinfomsg)) {
+				DEBUG_INFO("invalid netlink message\n");
+				break;
+			}
+
+			ifi = NLMSG_DATA(nlh);
+			DEBUG_INFO("ifi->ifi_family: %d\n", ifi->ifi_family);
+			if (ifi->ifi_family != AF_BRIDGE) {
+				ecm_interface_wifi_event_newlink(ifi, (u8 *)ifi + NLMSG_ALIGN(sizeof(struct ifinfomsg)),
+					NLMSG_PAYLOAD(nlh, sizeof(struct ifinfomsg)));
+			}
+			break;
+		}
+
+		nlh = NLMSG_NEXT(nlh, left);
+	}
+
+	return 0;
+}
+
+/*
+ * ecm_interface_wifi_event_rx
+ *	Receive netlink message from socket
+ */
+static int ecm_interface_wifi_event_rx(struct socket *sock, struct sockaddr_nl *addr, unsigned char *buf, int len)
+{
+	struct msghdr msg;
+	struct iovec  iov;
+	mm_segment_t oldfs;
+	int size;
+
+	iov.iov_base = buf;
+	iov.iov_len  = len;
+
+	msg.msg_flags = 0;
+	msg.msg_name  = addr;
+	msg.msg_namelen = sizeof(struct sockaddr_nl);
+	msg.msg_control = NULL;
+	msg.msg_controllen = 0;
+	iov_iter_init(&msg.msg_iter, READ, &iov, 1, 1);
+	oldfs = get_fs();
+	set_fs(KERNEL_DS);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0))
+	size = sock_recvmsg(sock, &msg, len, msg.msg_flags);
+#else
+	size = sock_recvmsg(sock, &msg, msg.msg_flags);
+#endif
+	set_fs(oldfs);
+
+	return size;
+}
+
+/*
+ * ecm_interface_wifi_event_thread
+ */
+static void ecm_interface_wifi_event_thread(void)
+{
+	int err;
+	int size;
+	struct sockaddr_nl saddr;
+	unsigned char buf[512];
+	int len = sizeof(buf);
+
+	kernel_sigaction(SIGKILL, SIG_DFL);
+	err = sock_create(AF_NETLINK, SOCK_RAW, NETLINK_ROUTE, &__ewn.sock);
+	if (err < 0) {
+		DEBUG_ERROR("failed to create sock\n");
+		goto exit1;
+	}
+
+	memset(&saddr, 0, sizeof(saddr));
+	saddr.nl_family = AF_NETLINK;
+	saddr.nl_groups = RTNLGRP_LINK;
+	saddr.nl_pid    = current->pid;
+
+	err = __ewn.sock->ops->bind(__ewn.sock, (struct sockaddr *)&saddr, sizeof(struct sockaddr));
+	if (err < 0) {
+		DEBUG_ERROR("failed to bind sock\n");
+		goto exit2;
+	}
+
+	DEBUG_INFO("ecm_interface_wifi_event thread started\n");
+	while (!kthread_should_stop()) {
+		size = ecm_interface_wifi_event_rx(__ewn.sock, &saddr, buf, len);
+		DEBUG_TRACE("got a netlink msg with len %d\n", size);
+
+		if (signal_pending(current))
+			break;
+
+		if (size < 0) {
+			DEBUG_WARN("netlink rx error\n");
+		} else {
+			ecm_interface_wifi_event_handler(buf, size);
+		}
+	}
+
+	DEBUG_INFO("ecm_interface_wifi_event thread stopped\n");
+exit2:
+	sock_release(__ewn.sock);
+exit1:
+	__ewn.sock = NULL;
+
+	return;
+}
+
+/*
+ * ecm_interface_wifi_event_start()
+ */
+int ecm_interface_wifi_event_start(void)
+{
+	if (__ewn.thread) {
+		return 0;
+	}
+
+	__ewn.thread = kthread_run((void *)ecm_interface_wifi_event_thread, NULL, "ECM_wifi_event");
+	if (IS_ERR(__ewn.thread)) {
+		DEBUG_ERROR("Unable to start kernel thread\n");
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+/*
+ * ecm_interface_wifi_event_stop()
+ */
+int ecm_interface_wifi_event_stop(void)
+{
+	int err;
+
+	if (__ewn.thread == NULL) {
+		return 0;
+	}
+
+	DEBUG_INFO("kill ecm_interface_wifi_event thread\n");
+
+	send_sig(SIGKILL, __ewn.thread, 1);
+	err = kthread_stop(__ewn.thread);
+	__ewn.thread = NULL;
+
+	return err;
+}
+
+#if defined(CONFIG_NET_CLS_ACT) && defined(ECM_CLASSIFIER_DSCP_IGS)
+/*
+ * ecm_interface_igs_enabled_handler()
+ * 	IGS enabled check sysctl node handler.
+ */
+static int ecm_interface_igs_enabled_handler(struct ctl_table *ctl, int write, void __user *buffer,
+		 size_t *lenp, loff_t *ppos)
+{
+	int ret;
+	int current_value;
+
+	/*
+	 * Take the current value
+	 */
+	current_value = ecm_interface_igs_enabled;
+
+	/*
+	 * Write the variable with user input
+	 */
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret || (!write)) {
+		return ret;
+	}
+
+	/*
+	 * If the IGS feature is not supported in the selected frontend,
+	 * just return.
+	 */
+	if (!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_IGS)) {
+		DEBUG_WARN("IGS is not supported by front-end\n");
+		return -EINVAL;
+	}
+
+	if ((ecm_interface_igs_enabled != 1) && (ecm_interface_igs_enabled != 0)) {
+		DEBUG_WARN("Invalid input. Valid values 0/1\n");
+		ecm_interface_igs_enabled = current_value;
+		return -EINVAL;
+	}
+	return 0;
+}
+#endif
+
+/*
+ * ecm_interface_src_check_handler()
+ *	Source interface check sysctl node handler.
+ */
+static int ecm_interface_src_check_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret;
+	int current_value;
+
+	/*
+	 * Take the current value
+	 */
+	current_value = ecm_interface_src_check;
+
+	/*
+	 * Write the variable with user input
+	 */
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret || (!write)) {
+		return ret;
+	}
+
+	/*
+	 * If the src iface check feature is not supported in the selected frontend,
+	 * just return.
+	 */
+	if (!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_SRC_IF_CHECK)) {
+		DEBUG_WARN("Source interface check is not supported by front-end\n");
+		return -EINVAL;
+	}
+
+	if ((ecm_interface_src_check != 1) && (ecm_interface_src_check != 0)) {
+		DEBUG_WARN("Invalid input. Valid values 0/1\n");
+		ecm_interface_src_check = current_value;
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static struct ctl_table ecm_interface_table[] = {
+	{
+		.procname		= "src_interface_check",
+		.data			= &ecm_interface_src_check,
+		.maxlen			= sizeof(int),
+		.mode			= 0644,
+		.proc_handler		= &ecm_interface_src_check_handler,
+	},
+#if defined(CONFIG_NET_CLS_ACT) && defined(ECM_CLASSIFIER_DSCP_IGS)
+	{
+		.procname		= "igs_enabled",
+		.data			= &ecm_interface_igs_enabled,
+		.maxlen			= sizeof(int),
+		.mode			= 0644,
+		.proc_handler		= &ecm_interface_igs_enabled_handler,
+	},
+#endif
+	{ }
+};
+
+static struct ctl_table ecm_interface_root_dir[] = {
+	{
+		.procname		= "ecm",
+		.mode			= 0555,
+		.child			= ecm_interface_table,
+	},
+	{ }
+};
+
+static struct ctl_table ecm_interface_root[] = {
+	{
+		.procname		= "net",
+		.mode			= 0555,
+		.child			= ecm_interface_root_dir,
+	},
+	{ }
+};
+
+#ifdef ECM_INTERFACE_IPSEC_GLUE_LAYER_SUPPORT_ENABLE
+/*
+ * ecm_interface_ipsec_register_callbacks()
+ *	Register callbacks
+ */
+void ecm_interface_ipsec_register_callbacks(struct ecm_interface_ipsec_callback *cb)
+{
+	spin_lock_bh(&ecm_interface_lock);
+	memcpy(&ecm_interface_ipsec_cb, cb, sizeof(struct ecm_interface_ipsec_callback));
+	spin_unlock_bh(&ecm_interface_lock);
+}
+EXPORT_SYMBOL(ecm_interface_ipsec_register_callbacks);
+
+/*
+ * ecm_interface_ipsec_unregister_callbacks
+ *	Unregister callbacks
+ */
+void ecm_interface_ipsec_unregister_callbacks(void)
+{
+	spin_lock_bh(&ecm_interface_lock);
+	memset(&ecm_interface_ipsec_cb, 0, sizeof(struct ecm_interface_ipsec_callback));
+	spin_unlock_bh(&ecm_interface_lock);
+}
+EXPORT_SYMBOL(ecm_interface_ipsec_unregister_callbacks);
+
+#endif
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+
+/*
+ * ecm_interface_ovs_defunct_masked_tuple()
+ *	Make defunct based on masked fields
+ */
+static void ecm_interface_ovs_defunct_masked_tuple(struct ovsmgr_dp_flow *flow)
+{
+	ip_addr_t src_addr;
+	ip_addr_t dest_addr;
+	bool is_routed = false;
+
+	bool smac_valid = !is_zero_ether_addr(flow->smac);
+	bool dmac_valid = !is_zero_ether_addr(flow->dmac);
+
+	if (flow->tuple.ip_version == 4) {
+		ECM_NIN4_ADDR_TO_IP_ADDR(src_addr, flow->tuple.ipv4.src);
+		ECM_NIN4_ADDR_TO_IP_ADDR(dest_addr, flow->tuple.ipv4.dst);
+	} else {
+		ECM_NIN6_ADDR_TO_IP_ADDR(src_addr, flow->tuple.ipv6.src);
+		ECM_NIN6_ADDR_TO_IP_ADDR(dest_addr, flow->tuple.ipv6.dst);
+	}
+
+	if (netif_is_ovs_master(flow->indev) || netif_is_ovs_master(flow->outdev)) {
+		is_routed = true;
+	}
+
+	/*
+	 * This function attempts to defunct connections which match
+	 * given OVS flow.  Some of the parameters in flow are masked so the
+	 * logic used here is to match:
+	 *  if (A & B == A), where B is flow parameter and A is CI parameter.
+	 *  A, B can be MAC, IP, port, protocol.
+	 *
+	 * OVS datapath flow can be routed or bridged flow.  To identify bridge vs routed
+	 * flow->{indev/outdev} is checked if it is OVS bridge interface and smac/dmac is
+	 * matching interface MAC address.  Otherwise flow is considered to be bridge flows.
+	 *
+	 * This function and the underlying functions (called functions) implement above logic
+	 * to match parameters.  SMAC/DMAC is expected to be non-zero, if they are 0 (any) then
+	 * rest of the parameters are used to filter out ECM connections using OVS classifier Hash bucket.
+	 * Otherwise node list is used to identify the connections originated from it and they are defunct.
+	 * In this implementation, worst case is SMAC and DMAC are 0 and all OVS connections need to be
+	 * parsed.
+	 *
+	 * Below is the sequence of checks and how ECM connections are filtered:
+	 *
+	 * 1. if SMAC and DMAC are invalid, defunct flows by masked matching (ip_version, sip, sport, protocol, dip, dport)
+	 *
+	 * 2. SMAC is valid (non zero) && outdev is OVS bridge:  defunction connections originated from nodes matching smac.
+	 *		a. Check if outdev is OVS bridge interface and dmac is matching bridge MAC.
+	 *		   If yes then defunct connections by matching {ip_version, sip, dip, protocol, sport, dport},
+	 *		   dmac in CI is ignored (any destination node address).
+	 *
+	 * 3. DMAC is valid (non-zero) && indev is OVS bridge: - defunction connections originated to nodes matching dmac.
+	 *		a. Check if indev is OVS bridge interface and smac is matching bridge MAC.
+	 *		   If yes then defunct connections by matching {ip_version, ip, dip, protocol, sport, dport},
+	 *		   smac in CI is ignored (any destination node address).
+	 *
+	 * 4. if either indev OR outdev is ovs_bridge: Then defunct connections through OVS classifier hash bucket by matching:
+	 *	            {ip_version, sip, dip, protocol, sport, dport}
+	 *
+	 * 5. if SMAC is valid : Then delete bridge flows originating from SMAC by matching:
+	 *		   {ip_version, dmac, sip, dip, protocol, sport, dport}
+	 *
+	 * 6. if DMAC is valid : Then delete bridge flows originating to DMAC by matching:
+	 *		   {ip_version, smac, sip, dip, protocol, sport, dport}
+	 *
+	 * 7. If any of the above conndition is not true:  defunct flows by masked matching (ip_version, sip, sport, protocol, dip, dport)
+	 */
+
+	/*
+	 * case 1:  Defunct by classifier if smac and dmac are invalid
+	 */
+	if (!smac_valid && !dmac_valid) {
+		goto classify_defunct;
+	}
+
+	/*
+	 * case 2: If outdev is ovs_br, find all connection FROM smac and MATCH
+	 */
+	if (smac_valid && netif_is_ovs_master(flow->outdev)) {
+		if (unlikely(dmac_valid && !ECM_MAC_ADDR_MATCH(flow->outdev->dev_addr, flow->dmac))) {
+			DEBUG_WARN("%px: Defunct routed connections FROM %pM to the %s (OVS bridge) Failed\n", flow, flow->smac,
+								flow->outdev->name);
+			return;
+		}
+
+		DEBUG_TRACE("%px: Defunct routed connections by masked 7 tuple FROM %pM to the %s (OVS bridge)\n", flow,
+							flow->smac, flow->outdev->name);
+
+		ecm_db_node_ovs_connections_masked_defunct(flow->tuple.ip_version, flow->smac, true, src_addr,
+							   ntohs(flow->tuple.src_port), flow->dmac, false, dest_addr,
+							   ntohs(flow->tuple.dst_port), flow->tuple.protocol,
+							   ECM_DB_OBJ_DIR_FROM, true);
+		return;
+	}
+
+	/*
+	 * case 3: If indev is ovs_br, find all connection from TO  dmac and match.
+	 */
+	if (dmac_valid && netif_is_ovs_master(flow->indev)) {
+		if (unlikely(smac_valid && !ECM_MAC_ADDR_MATCH(flow->indev->dev_addr, flow->smac))) {
+			DEBUG_WARN("%px: Defunct routed connections TO %pM from %s (OVS bridge), Failed\n", flow,
+				   flow->dmac, flow->indev->name);
+			return;
+		}
+
+		DEBUG_TRACE("%px: Defunct routed the connections by masked 7 tuple TO %pM from %s (OVS bridge)\n", flow,
+			    flow->dmac, flow->indev->name);
+
+		ecm_db_node_ovs_connections_masked_defunct(flow->tuple.ip_version, flow->smac, false, src_addr,
+							   ntohs(flow->tuple.src_port), flow->dmac, true, dest_addr,
+							   ntohs(flow->tuple.dst_port), flow->tuple.protocol,
+							   ECM_DB_OBJ_DIR_TO, true);
+
+		return;
+	}
+
+	/*
+	 * case 4: If smac or dmac is not valid and either of indev or outdev is ovs-bridge device, defunct by 5 tuple
+	 */
+	if (is_routed) {
+		goto classify_defunct;
+	}
+
+	/*
+	 * case 5: if smac is valid, match bridged connection FROM SMAC
+	 */
+	if (smac_valid) {
+		DEBUG_TRACE("%px: Defunct Bridged flows by masked  7 tuple (smac valid) indev = %s, outdev = %s, smac:%pM, dmac:%pM, "
+								"proto=%d, sport=%d, dport=%d\n",
+					flow, flow->indev->name, flow->outdev->name, flow->smac, flow->dmac,
+					flow->tuple.protocol, ntohs(flow->tuple.src_port), ntohs(flow->tuple.dst_port));
+
+		ecm_db_node_ovs_connections_masked_defunct(flow->tuple.ip_version, flow->smac, true, src_addr,
+							   ntohs(flow->tuple.src_port), flow->dmac,
+							   dmac_valid, dest_addr,
+							   ntohs(flow->tuple.dst_port), flow->tuple.protocol,
+							   ECM_DB_OBJ_DIR_FROM, false);
+		return;
+	}
+
+	/*
+	 * case 6: if dmac is valid, match bridged connection TO DMAC
+	 */
+	if (dmac_valid) {
+		DEBUG_TRACE("%px: Defunct Bridged flows by masked 7 tuple (dmac valid) indev = %s, outdev = %s, smac:%pM, dmac:%pM, "
+								"proto=%d, sport=%d, dport=%d\n",
+					flow, flow->indev->name, flow->outdev->name, flow->smac, flow->dmac,
+					flow->tuple.protocol, ntohs(flow->tuple.src_port), ntohs(flow->tuple.dst_port));
+
+		ecm_db_node_ovs_connections_masked_defunct(flow->tuple.ip_version, flow->smac, false, src_addr,
+							   ntohs(flow->tuple.src_port), flow->dmac, true,  dest_addr,
+							   ntohs(flow->tuple.dst_port), flow->tuple.protocol,
+							   ECM_DB_OBJ_DIR_TO, false);
+
+		return;
+	}
+
+classify_defunct:
+
+	/*
+	 * case 7: If dmac and smac are NULL, defunct connections by matching 5 tuple info
+	 */
+	DEBUG_TRACE("%px: Defunct flows by 5 tuple (smac & dmac invalid) indev = %s, outdev = %s, smac:%pM, dmac:%pM, "
+					     "proto=%d, sport=%d, dport=%d is_routed=%d\n",
+				flow, flow->indev->name, flow->outdev->name, flow->smac, flow->dmac,
+				flow->tuple.protocol, ntohs(flow->tuple.src_port), ntohs(flow->tuple.dst_port), is_routed);
+
+	ecm_db_connection_defunct_by_classifier(flow->tuple.ip_version, src_addr, ntohs(flow->tuple.src_port), dest_addr,
+						ntohs(flow->tuple.dst_port), flow->tuple.protocol, is_routed, ECM_CLASSIFIER_TYPE_OVS);
+
+}
+
+/*
+ * ecm_interface_ovs_flow_defunct_connections()
+ *	This event can be triggered when the OVS flow is deleted due to flow timeout.
+ *	Defunct the connections based on the OVS flow information.
+ */
+static void ecm_interface_ovs_flow_defunct_connections(struct ovsmgr_dp_flow *flow)
+{
+	ip_addr_t src_ip = ECM_IP_ADDR_NULL;
+	ip_addr_t dest_ip = ECM_IP_ADDR_NULL;
+
+	/*
+	 * Delete by flow rule.
+	 */
+
+	if (flow->tuple.ip_version == 4) {
+		DEBUG_TRACE("IPv4: Src: %pI4:%d protocol: %d Dst: %pI4:%d\n",
+			   &flow->tuple.ipv4.src, ntohs(flow->tuple.src_port),
+			   flow->tuple.protocol,
+			   &flow->tuple.ipv4.dst, ntohs(flow->tuple.dst_port));
+
+		if (flow->tuple.ipv4.src) {
+			ECM_NIN4_ADDR_TO_IP_ADDR(src_ip, flow->tuple.ipv4.src);
+		}
+
+		if (flow->tuple.ipv4.dst) {
+			ECM_NIN4_ADDR_TO_IP_ADDR(dest_ip, flow->tuple.ipv4.dst);
+		}
+	} else if (flow->tuple.ip_version == 6) {
+		DEBUG_TRACE("IPv6: Src: %pI6:%d protocol: %d Dst: %pI6:%d\n",
+			   &flow->tuple.ipv6.src, ntohs(flow->tuple.src_port),
+			   flow->tuple.protocol,
+			   &flow->tuple.ipv6.dst, ntohs(flow->tuple.dst_port));
+		ECM_NIN6_ADDR_TO_IP_ADDR(src_ip, flow->tuple.ipv6.src);
+		ECM_NIN6_ADDR_TO_IP_ADDR(dest_ip, flow->tuple.ipv6.dst);
+	} else {
+		DEBUG_WARN("%px: Unsupported IP version: %d\n", flow, flow->tuple.ip_version);
+		return;
+	}
+
+	/*
+	 * For multicast flows, ovs manager will set source ip
+	 * as 0.0.0.0, we need to get the 'ci' from multicast
+	 * destination ip
+	 */
+	if (ecm_ip_addr_is_multicast(dest_ip)) {
+#ifdef ECM_MULTICAST_ENABLE
+		ip_addr_t grp_ip;
+		struct ecm_db_connection_instance *ci;
+		struct ecm_db_multicast_tuple_instance *ti;
+
+		/*
+		 * Get the for the group in the tuple_instance table. As OVS
+		 * does not support "source specific multicast" there can be
+		 * only one tuple entry for a group.
+		 */
+		ti = ecm_db_multicast_connection_get_and_ref_first(dest_ip);
+		if (!ti) {
+			DEBUG_WARN("%px: no multicast tuple entry found\n", flow);
+			return;
+		}
+
+		/*
+		 * Force destruction of the connection by making it defunct
+		 */
+		while (ti) {
+			struct ecm_db_multicast_tuple_instance *ti_next;
+
+			ecm_db_multicast_tuple_instance_group_ip_get(ti, grp_ip);
+			if (ECM_IP_ADDR_MATCH(grp_ip, dest_ip)) {
+				ci = ecm_db_multicast_connection_get_from_tuple(ti);
+				ecm_db_connection_make_defunct(ci);
+			}
+			ti_next = ecm_db_multicast_connection_get_and_ref_next(ti);
+			ecm_db_multicast_connection_deref(ti);
+			ti = ti_next;
+		}
+#endif
+		return;
+	}
+
+	/*
+	 * For unicast if 5-tuple is not valid, then delete the flows by
+	 * {smac/dmac and indev/outdev}
+	 */
+	if ((flow->tuple.protocol == IPPROTO_TCP || flow->tuple.protocol == IPPROTO_UDP) &&
+			flow->tuple.src_port && flow->tuple.dst_port &&
+			!ECM_IP_ADDR_IS_NULL(src_ip) && !ECM_IP_ADDR_IS_NULL(dest_ip)) {
+		struct ecm_db_connection_instance *ci;
+
+		/*
+		 * Delete the flows by using 5 tuple
+		 */
+		DEBUG_TRACE("%px: Delete flow by 5 tuple: indev = %s, outdev = %s, smac:%pM, dmac:%pM, "
+					"proto=%d, sport=%d, dport=%d\n",
+					flow, flow->indev->name, flow->outdev->name, flow->smac, flow->dmac,
+					flow->tuple.protocol, ntohs(flow->tuple.src_port), ntohs(flow->tuple.dst_port));
+
+		/*
+		 * Delete the flows by using 5-tuple parameters.
+		 */
+		ci = ecm_db_connection_from_ovs_flow_get_and_ref(flow);
+		if (!ci) {
+			DEBUG_WARN("%px: OVS flow not found in ECM database, Try to match by mask\n", flow);
+			goto no_ci;
+		}
+		DEBUG_INFO("%px: Connection defunct %px\n", flow, ci);
+
+		/*
+		 * Force destruction of the connection by making it defunct
+		 */
+		ecm_db_connection_make_defunct(ci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+no_ci:
+
+	/*
+	 * if all tuple values are 0, defunct by interface
+	 */
+	if (unlikely(is_zero_ether_addr(flow->smac) && is_zero_ether_addr(flow->dmac))) {
+		bool sip_valid, dip_valid;
+
+		if (flow->tuple.ip_version == 4) {
+			sip_valid = !!flow->tuple.ipv4.src;
+			dip_valid = !!flow->tuple.ipv4.dst;
+		} else {
+			sip_valid = !ipv6_addr_any((const struct in6_addr *)&flow->tuple.ipv6.src);
+			dip_valid = !ipv6_addr_any((const struct in6_addr *)&flow->tuple.ipv6.dst);
+		}
+
+		if (sip_valid || dip_valid || flow->tuple.src_port || flow->tuple.dst_port || flow->tuple.protocol) {
+			goto defunct_by_masked_tuple;
+		}
+
+		if (flow->indev && !netif_is_ovs_master(flow->indev)) {
+			DEBUG_TRACE("%px: Defunct all flows by indev=%s\n", flow, flow->indev->name);
+			ecm_interface_dev_defunct_connections(flow->indev);
+		}
+
+		if (flow->outdev && !netif_is_ovs_master(flow->outdev)) {
+			DEBUG_TRACE("%px: Defunct all flows by outdev=%s\n", flow, flow->outdev->name);
+			ecm_interface_dev_defunct_connections(flow->outdev);
+		}
+
+		DEBUG_TRACE("%px: Delete flow is called with all tuple 0\n", flow);
+		return;
+	}
+
+defunct_by_masked_tuple:
+
+	DEBUG_TRACE("%px: Delete flow by 5 or 7 tuple masks: indev = %s, outdev = %s, smac:%pM, dmac:%pM, "
+		    "proto=%d, sport=%d, dport=%d\n",
+		    flow, flow->indev->name, flow->outdev->name, flow->smac, flow->dmac,
+		    flow->tuple.protocol, ntohs(flow->tuple.src_port), ntohs(flow->tuple.dst_port));
+
+	ecm_interface_ovs_defunct_masked_tuple(flow);
+}
+
+#ifdef ECM_MULTICAST_ENABLE
+/*
+ * ecm_interface_multicast_ovs_flow_update_connections()
+ *	Update the connections based on the OVS flow information.
+ *
+ *	This event is triggered by OVS when a new OVS port joins an
+ *	already existing OVS multicast flow. We rely on this event rather
+ *	than the MCS update event when an OVS port joins an existing flow.
+ *	This is because when the MCS event is received, the OVS may not
+ *	have yet updated its flow entry to add the new port,
+ *	so ECM will not be able to query OVS to validate the new flow entry
+ */
+static void ecm_interface_multicast_ovs_flow_update_connections(struct ovsmgr_dp_flow *flow)
+{
+	ip_addr_t ip_dest_addr;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_db_multicast_tuple_instance *ti;
+	struct ecm_front_end_connection_instance *feci;
+	struct net_device *brdev;
+
+	if (flow->tuple.ip_version == 4) {
+		ECM_NIN4_ADDR_TO_IP_ADDR(ip_dest_addr, flow->tuple.ipv4.dst);
+		DEBUG_TRACE("IPv4: Src: %pI4:%d protocol: %d Dst: %pI4:%d\n",
+			   &flow->tuple.ipv4.src, flow->tuple.src_port,
+			   flow->tuple.protocol,
+			   &flow->tuple.ipv4.dst, flow->tuple.dst_port);
+	} else if (flow->tuple.ip_version == 6) {
+		ECM_NIN6_ADDR_TO_IP_ADDR(ip_dest_addr, flow->tuple.ipv6.dst);
+		DEBUG_TRACE("IPv6: Src: %pI6:%d protocol: %d Dst: %pI6:%d\n",
+			   &flow->tuple.ipv6.src, flow->tuple.src_port,
+			   flow->tuple.protocol,
+			   &flow->tuple.ipv6.dst, flow->tuple.dst_port);
+	} else {
+		DEBUG_WARN("%px: Unsupported IP version: %d\n", flow, flow->tuple.ip_version);
+		return;
+	}
+
+	if (!ecm_ip_addr_is_multicast(ip_dest_addr)) {
+		DEBUG_WARN("%px: Change notification is supported only for multicast flows\n", flow);
+		return;
+	}
+
+	/*
+	 * Get the OVS bridge device.
+	 */
+	if (ecm_front_end_is_ovs_bridge_device(flow->outdev)) {
+		brdev = flow->outdev;
+	} else if (ecm_interface_is_ovs_bridge_port(flow->outdev)) {
+		brdev = ovsmgr_dev_get_master(flow->outdev);
+		if (!brdev) {
+			DEBUG_WARN("%px: Master device for OVS port: %s is NULL!\n", flow, flow->outdev->name);
+			return;
+		}
+	} else {
+		DEBUG_WARN("%px: egress port: %s is neither OVS bridge nor OVS port\n", flow, flow->outdev->name);
+		return;
+	}
+
+	/*
+	 * Get the first entry for the group in the tuple_instance table,
+	 */
+	ti = ecm_db_multicast_connection_get_and_ref_first(ip_dest_addr);
+	if (!ti) {
+		DEBUG_WARN("%px: no multicast tuple entry found\n", flow);
+		return;
+	}
+
+	ci = ecm_db_multicast_connection_get_from_tuple(ti);
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+	/*
+	 * The source IP address in the OVS flow passed to us is always found
+	 * to be NULL. So, update the all multicast connections for this group address.
+	 */
+	if (feci->multicast_update) {
+		feci->multicast_update(ip_dest_addr, brdev);
+	}
+
+	feci->deref(feci);
+	ecm_db_multicast_connection_deref(ti);
+}
+#endif
+
+/*
+ * ecm_interface_ovs_notifier_callback()
+ * 	Netdevice notifier callback to inform us of change of state of a netdevice
+ */
+static int ecm_interface_ovs_notifier_callback(struct notifier_block *nb, unsigned long event, void *data)
+{
+	struct ovsmgr_notifiers_info *ovs_info = (struct ovsmgr_notifiers_info *)data;
+	struct ovsmgr_dp_port_info *port;
+
+	DEBUG_INFO("OVS notifier event: %lu\n", event);
+
+	switch(event) {
+	case OVSMGR_DP_PORT_DEL:
+		port = ovs_info->port;
+		ecm_interface_dev_defunct_connections(port->dev);
+		break;
+	case OVSMGR_DP_FLOW_DEL:
+		ecm_interface_ovs_flow_defunct_connections(ovs_info->flow);
+		break;
+	case OVSMGR_DP_FLOW_TBL_FLUSH:
+		ecm_db_connection_defunct_all();
+		break;
+	case OVSMGR_DP_FLOW_CHANGE:
+#ifdef ECM_MULTICAST_ENABLE
+		ecm_interface_multicast_ovs_flow_update_connections(ovs_info->flow);
+#endif
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+/*
+ * struct notifier_block ecm_interface_ovs_notifier
+ *	Registration for OVS events
+ */
+static struct notifier_block ecm_interface_ovs_notifier __read_mostly = {
+	.notifier_call = ecm_interface_ovs_notifier_callback,
+};
+#endif
+
+/*
+ * ecm_interface_init()
+ */
+int ecm_interface_init(void)
+{
+	int result;
+	DEBUG_INFO("ECM Interface init\n");
+
+	/*
+	 * Register sysctl table.
+	 */
+	ecm_interface_ctl_table_header = register_sysctl_table(ecm_interface_root);
+
+	result = register_netdevice_notifier(&ecm_interface_netdev_notifier);
+	if (result != 0) {
+		DEBUG_ERROR("Failed to register netdevice notifier %d\n", result);
+		unregister_sysctl_table(ecm_interface_ctl_table_header);
+		return result;
+	}
+#if defined(ECM_DB_XREF_ENABLE) && defined(ECM_BAND_STEERING_ENABLE)
+	/*
+	 * If the bridge feature is supported in the selected frontend,
+	 * register the  FDB event handlers.
+	 */
+	if (ecm_front_end_is_feature_supported(ECM_FE_FEATURE_BRIDGE)) {
+		br_fdb_update_register_notify(&ecm_interface_node_br_fdb_update_nb);
+		br_fdb_register_notify(&ecm_interface_node_br_fdb_delete_nb);
+	}
+#endif
+#ifdef ECM_DB_XREF_ENABLE
+	neigh_mac_update_register_notify(&ecm_interface_neigh_mac_update_nb);
+#endif
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+	ovsmgr_notifier_register(&ecm_interface_ovs_notifier);
+#endif
+	ecm_interface_wifi_event_start();
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_interface_init);
+
+/*
+ * ecm_interface_exit()
+ */
+void ecm_interface_exit(void)
+{
+	DEBUG_INFO("ECM Interface exit\n");
+
+	spin_lock_bh(&ecm_interface_lock);
+	ecm_interface_terminate_pending  = true;
+	spin_unlock_bh(&ecm_interface_lock);
+
+	unregister_netdevice_notifier(&ecm_interface_netdev_notifier);
+#ifdef ECM_DB_XREF_ENABLE
+	neigh_mac_update_unregister_notify(&ecm_interface_neigh_mac_update_nb);
+#endif
+
+#if defined(ECM_DB_XREF_ENABLE) && defined(ECM_BAND_STEERING_ENABLE)
+	/*
+	 * If the bridge feature is supported in the selected frontend,
+	 * unregister the  FDB event handlers.
+	 */
+	if (ecm_front_end_is_feature_supported(ECM_FE_FEATURE_BRIDGE)) {
+		br_fdb_update_unregister_notify(&ecm_interface_node_br_fdb_update_nb);
+		br_fdb_unregister_notify(&ecm_interface_node_br_fdb_delete_nb);
+	}
+#endif
+	ecm_interface_wifi_event_stop();
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+	ovsmgr_notifier_unregister(&ecm_interface_ovs_notifier);
+#endif
+	/*
+	 * Unregister sysctl table.
+	 */
+	if (ecm_interface_ctl_table_header) {
+		unregister_sysctl_table(ecm_interface_ctl_table_header);
+	}
+}
+EXPORT_SYMBOL(ecm_interface_exit);
diff --git a/qca-nss-ecm/ecm_interface.h b/qca-nss-ecm/ecm_interface.h
new file mode 100644
index 0000000..5357d01
--- /dev/null
+++ b/qca-nss-ecm/ecm_interface.h
@@ -0,0 +1,122 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern int ecm_interface_src_check;	/* Source interface check flag */
+#if defined(CONFIG_NET_CLS_ACT) && defined(ECM_CLASSIFIER_DSCP_IGS)
+extern int ecm_interface_igs_enabled;	/* IGS enabled check flag */
+#endif
+
+/*
+ * struct ecm_interface_route
+ *	An ecm route supports either v4 or v6 routing information
+ */
+struct ecm_interface_route {
+	struct dst_entry *dst;			/* Both ipv4 and v6 have a common dst entry. It is an overlay pointer of rtv4 or rtv6 */
+	union {
+		struct rtable *rtv4;		/* IPv4 route */
+		struct rt6_info *rtv6;		/* IPv6 route */
+	} rt;
+	bool v4_route;				/* True when a v4 route, false when v6 */
+};
+
+/*
+ *  Netdev Index value for a Loopback device
+ */
+#define ECM_INTERFACE_LOOPBACK_DEV_INDEX 1
+
+/*
+ * IPSec Core and Interface Definition
+ */
+#define ECM_INTERFACE_IPSEC_DEFAULT_CORE 0x2
+#define ECM_INTERFACE_IPSEC_CORE_OFFSET 24
+
+/*
+ * External defined functions
+ */
+extern struct net_device *bond_get_tx_dev(struct sk_buff *skb, uint8_t *src_mac,
+					  uint8_t *dst_mac, void *src,
+					  void *dst, uint16_t protocol,
+					  struct net_device *bond_dev,
+					  __be16 *layer4hdr);
+bool ecm_interface_mac_addr_get_no_route(struct net_device *dev, ip_addr_t ip_addr, uint8_t *mac_addr);
+bool ecm_interface_mac_addr_get(ip_addr_t addr, uint8_t *mac_addr, bool *on_link, ip_addr_t gw_addr);
+bool ecm_interface_find_route_by_addr(ip_addr_t addr, struct ecm_interface_route *ecm_rt);
+void ecm_interface_route_release(struct ecm_interface_route *rt);
+#ifdef ECM_IPV6_ENABLE
+struct neighbour *ecm_interface_ipv6_neigh_get(ip_addr_t addr);
+void ecm_interface_send_neighbour_solicitation(struct net_device *dev, ip_addr_t addr);
+#endif
+void ecm_interface_send_arp_request(struct net_device *dest_dev, ip_addr_t dest_addr, bool on_link, ip_addr_t gw_addr);
+struct neighbour *ecm_interface_ipv4_neigh_get(ip_addr_t addr);
+bool ecm_interface_is_pptp(struct sk_buff *skb, const struct net_device *out);
+bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct net_device *out, int ver);
+bool ecm_interface_is_l2tp_pptp(struct sk_buff *skb, const struct net_device *out);
+struct ecm_db_iface_instance *ecm_interface_establish_and_ref(struct ecm_front_end_connection_instance *feci, struct net_device *dev, struct sk_buff *skb);
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+bool ecm_interface_is_ovs_bridge_port(const struct net_device *dev);
+#endif
+#ifdef ECM_MULTICAST_ENABLE
+int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_connection_instance *feci, struct ecm_db_iface_instance *interfaces, struct net_device *in_dev, ip_addr_t packet_src_addr, ip_addr_t packet_dest_addr, uint8_t maxvif, uint32_t *dst_dev, uint32_t *to_interface_first, bool mfc_update, __be16 *layer4hdr, struct sk_buff *skb);
+
+int32_t ecm_interface_multicast_heirarchy_construct_bridged(struct ecm_front_end_connection_instance *feci, struct ecm_db_iface_instance *interfaces, struct net_device *br_dev, ip_addr_t src_addr, ip_addr_t dest_addr, uint8_t mc_max_dst, int32_t *mc_dst_dev, uint32_t *to_interface_first, uint8_t *src_node_addr, __be16 *layer4hdr, struct sk_buff *skb);
+
+void ecm_interface_multicast_stats_update(struct ecm_db_connection_instance *ci, uint32_t from_tx_packets, uint32_t from_tx_bytes, uint32_t from_rx_packets, uint32_t from_rx_bytes, uint32_t to_tx_packets, uint32_t to_tx_bytes, uint32_t to_rx_packets, uint32_t to_rx_bytes);
+
+bool ecm_interface_multicast_find_updates_to_iface_list(struct ecm_db_connection_instance *ci, struct ecm_multicast_if_update *, uint32_t flags, bool is_br_snooper, uint32_t *dst_dev, uint32_t max_to_dev, struct net_device *brdev);
+
+bool ecm_interface_multicast_check_for_br_dev(uint32_t dest_if[], uint8_t max_if);
+bool ecm_interface_multicast_is_iface_type(int32_t mc_if_index[], int32_t max_if_index, unsigned short type);
+
+int32_t ecm_interface_multicast_check_for_src_ifindex(int32_t mc_if_index[], int32_t max_if_index, int32_t if_num);
+int32_t ecm_interface_multicast_from_heirarchy_construct(struct ecm_front_end_connection_instance *feci,
+					struct ecm_db_iface_instance *interfaces[],
+					ip_addr_t packet_src_addr, ip_addr_t packet_dest_addr,
+					int ip_version, int packet_protocol,
+					struct net_device *given_dest_dev, bool is_routed,
+					struct net_device *given_src_dev,
+					uint8_t *dest_node_addr, uint8_t *src_node_addr,
+					__be16 *layer4hdr, struct sk_buff *skb);
+int32_t ecm_interface_multicast_filter_src_interface(struct ecm_db_connection_instance *ci, uint32_t *mc_dst_if_index);
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+bool ecm_interface_multicast_check_for_ovs_br_dev(uint32_t dest_if[], uint8_t max_if);
+int ecm_interface_multicast_ovs_to_interface_get_and_ref(struct ecm_db_connection_instance *ci,
+					struct net_device **to_ovs_port,
+					struct net_device **to_ovs_brdev);
+#endif
+#endif
+
+int32_t ecm_interface_heirarchy_construct(struct ecm_front_end_connection_instance *feci,
+						struct ecm_db_iface_instance *interfaces[],
+						struct net_device *const_if, struct net_device *other_if,
+						ip_addr_t lookup_src_addr,
+						ip_addr_t lookup_dest_addr,
+						ip_addr_t real_dest_addr,
+						int ip_version, int packet_protocol,
+						struct net_device *given_dest_dev,
+						bool is_routed, struct net_device *given_src_dev,
+						uint8_t *dest_node_addr, uint8_t *src_node_addr,
+						__be16 *layer4hdr, struct sk_buff *skb, struct ecm_front_end_ovs_params *op);
+void ecm_interface_stats_update(struct ecm_db_connection_instance *ci, uint32_t from_tx_packets, uint32_t from_tx_bytes, uint32_t from_rx_packets, uint32_t from_rx_bytes, uint32_t to_tx_packets, uint32_t to_tx_bytes, uint32_t to_rx_packets, uint32_t to_rx_bytes);
+struct net_device *ecm_interface_dev_find_by_addr(ip_addr_t addr, bool *from_local_addr);
+
+struct net_device *ecm_interface_get_and_hold_dev_master(struct net_device *dev);
+void ecm_interface_dev_regenerate_connections(struct net_device *dev);
+struct net_device *ecm_interface_dev_find_by_local_addr(ip_addr_t addr);
+bool ecm_interface_find_gateway(ip_addr_t addr, ip_addr_t gw_addr);
+void ecm_interface_dev_defunct_connections(struct net_device *dev);
+void ecm_interface_node_connections_defunct(uint8_t *mac, int ip_version);
+bool ecm_interface_tunnel_mtu_update(ip_addr_t saddr, ip_addr_t daddr, ecm_db_iface_type_t type, int32_t *mtu);
+struct net_device *ecm_interface_get_and_hold_ipsec_tun_netdev(struct net_device *dev, struct sk_buff *skb, int32_t *interface_type);
diff --git a/qca-nss-ecm/ecm_notifier.c b/qca-nss-ecm/ecm_notifier.c
new file mode 100644
index 0000000..bb314c8
--- /dev/null
+++ b/qca-nss-ecm/ecm_notifier.c
@@ -0,0 +1,287 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <net/ip.h>
+#include <linux/inet.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/atomic.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NOTIFIER_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_db.h"
+
+#include "ecm_notifier_pvt.h"
+#include "exports/ecm_notifier.h"
+
+static atomic_t ecm_notifier_count;
+static ATOMIC_NOTIFIER_HEAD(ecm_notifier_connection);
+
+/*
+ * ecm_notifier_ci_to_data()
+ * 	Convert ci to ecm_notifier_connection_data.
+ *
+ * This function holds reference to devices (data->from_dev & data->to_dev).
+ */
+static bool ecm_notifier_ci_to_data(struct ecm_db_connection_instance *ci, struct ecm_notifier_connection_data *data)
+{
+	ip_addr_t src_ip;
+	ip_addr_t dst_ip;
+	int32_t first_index;
+	struct ecm_db_iface_instance *interfaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+
+	first_index = ecm_db_connection_interfaces_get_and_ref(ci, interfaces, ECM_DB_OBJ_DIR_FROM);
+	if (first_index == ECM_DB_IFACE_HEIRARCHY_MAX) {\
+		DEBUG_WARN("%px: Failed to get 'from' ifaces index\n", ci);
+		return false;
+	}
+	data->from_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(interfaces[first_index]));
+	if (!data->from_dev) {
+		DEBUG_WARN("%px: Could not locate 'from' interface\n", ci);
+		return false;
+	}
+	ecm_db_connection_interfaces_deref(interfaces, first_index);
+
+	first_index = ecm_db_connection_interfaces_get_and_ref(ci, interfaces, ECM_DB_OBJ_DIR_TO);
+	if (first_index == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Failed to get 'to' ifaces index\n", ci);
+		dev_put(data->from_dev);
+		return false;
+	}
+	data->to_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(interfaces[first_index]));
+	if (!data->to_dev) {
+		DEBUG_WARN("%px: Could not locate 'to' interface\n", ci);
+		dev_put(data->from_dev);
+		return false;
+	}
+	ecm_db_connection_interfaces_deref(interfaces, first_index);
+
+	data->tuple.ip_ver = ecm_db_connection_ip_version_get(ci);
+	data->tuple.protocol = ecm_db_connection_protocol_get(ci);
+	data->tuple.src_port = ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM);
+	data->tuple.dst_port = ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO);
+
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, dst_ip);
+
+	switch (data->tuple.ip_ver) {
+	case 4:
+		ECM_IP_ADDR_TO_HIN4_ADDR(data->tuple.src.in.s_addr, src_ip);
+		ECM_IP_ADDR_TO_HIN4_ADDR(data->tuple.dest.in.s_addr, dst_ip);
+		break;
+
+	case 6:
+		ECM_IP_ADDR_TO_HIN6_ADDR(data->tuple.src.in6, src_ip);
+		ECM_IP_ADDR_TO_HIN6_ADDR(data->tuple.dest.in6, dst_ip);
+		break;
+
+	default:
+		/*
+		 * Shouldn't come here.
+		 */
+		DEBUG_ERROR("%px: Invalid protocol\n", ci);
+		dev_put(data->from_dev);
+		dev_put(data->to_dev);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * ecm_notifier_connection_added()
+ * 	Send ECM connection added event to notifier chain.
+ */
+void ecm_notifier_connection_added(void *arg, struct ecm_db_connection_instance *ci)
+{
+	struct ecm_notifier_connection_data data = {0};
+
+	if (!atomic_read(&ecm_notifier_count)) {
+		DEBUG_TRACE("%px: No notifier has registered for event\n", ci);
+		return;
+	}
+
+	/*
+	 * Module has registered for events.
+	 */
+	if (!ecm_notifier_ci_to_data(ci, &data)) {
+		DEBUG_WARN("%px: Failed to get data from connection instance\n", ci);
+		return;
+	}
+
+	atomic_notifier_call_chain(&ecm_notifier_connection, ECM_NOTIFIER_ACTION_CONNECTION_ADDED, (void*)&data);
+
+	dev_put(data.from_dev);
+	dev_put(data.to_dev);
+}
+
+/*
+ * ecm_notifier_connection_removed()
+ * 	Send ECM connection removed event to notifier chain.
+ */
+void ecm_notifier_connection_removed(void *arg, struct ecm_db_connection_instance *ci)
+{
+	struct ecm_notifier_connection_data data = {0};
+
+	if (!atomic_read(&ecm_notifier_count)) {
+		DEBUG_TRACE("%px: No notifier has registered for event\n", ci);
+		return;
+	}
+
+	/*
+	 * Module has registered for events.
+	 */
+	if (!ecm_notifier_ci_to_data(ci, &data)) {
+		DEBUG_WARN("%px: Failed to get data from connection instance\n", ci);
+		return;
+	}
+
+	atomic_notifier_call_chain(&ecm_notifier_connection, ECM_NOTIFIER_ACTION_CONNECTION_REMOVED, (void*)&data);
+
+	dev_put(data.from_dev);
+	dev_put(data.to_dev);
+}
+
+/*
+ * ecm_notifier_register_connection_notify()
+ * 	Register for ECM connection events.
+ */
+int ecm_notifier_register_connection_notify(struct notifier_block *nb)
+{
+	/*
+	 * Currently atomic_notifier_chain_register does not return error and assumed to be always success.
+	 * so, incrmenting ecm_notifier_count at beginning.
+	 */
+	atomic_inc(&ecm_notifier_count);
+
+	return atomic_notifier_chain_register(&ecm_notifier_connection, nb);
+}
+EXPORT_SYMBOL(ecm_notifier_register_connection_notify);
+
+/*
+ * ecm_notifier_unregister_connection_notify()
+ * 	Unregister for ECM connection events.
+ */
+int ecm_notifier_unregister_connection_notify(struct notifier_block *nb)
+{
+	atomic_dec(&ecm_notifier_count);
+
+	return atomic_notifier_chain_unregister(&ecm_notifier_connection, nb);
+}
+EXPORT_SYMBOL(ecm_notifier_unregister_connection_notify);
+
+/*
+ * ecm_notifier_connection_state_fetch()
+ * 	Returns the current state for given connection tuple.
+ */
+enum ecm_notifier_connection_state ecm_notifier_connection_state_get(struct ecm_notifier_connection_tuple *conn)
+{
+	struct ecm_front_end_connection_instance *feci;
+	ecm_front_end_acceleration_mode_t accel_state;
+	struct ecm_db_connection_instance *ci;
+	int host1_port = conn->src_port;
+	int host2_port = conn->dst_port;
+	int protocol = conn->protocol;
+	ip_addr_t host1_addr;
+	ip_addr_t host2_addr;
+
+	DEBUG_ASSERT(conn, "Connection tuple is NULL\n");
+
+        switch (conn->ip_ver) {
+        case 4:
+                ECM_HIN4_ADDR_TO_IP_ADDR(host1_addr, conn->src.in.s_addr);
+                ECM_HIN4_ADDR_TO_IP_ADDR(host2_addr, conn->dest.in.s_addr);
+		DEBUG_TRACE("%px: lookup src: " ECM_IP_ADDR_DOT_FMT ":%d, "
+				"dest: " ECM_IP_ADDR_DOT_FMT ":%d, "
+				"protocol %d\n",
+				conn,
+				ECM_IP_ADDR_TO_DOT(host1_addr),
+				host1_port,
+				ECM_IP_ADDR_TO_DOT(host2_addr),
+				host2_port,
+				protocol);
+                break;
+
+        case 6:
+                ECM_HIN6_ADDR_TO_IP_ADDR(host1_addr, conn->src.in6);
+                ECM_HIN6_ADDR_TO_IP_ADDR(host2_addr, conn->dest.in6);
+		DEBUG_TRACE("%px: lookup src: " ECM_IP_ADDR_OCTAL_FMT ":%d, "
+				"dest: " ECM_IP_ADDR_OCTAL_FMT ":%d, "
+				"protocol %d\n",
+				conn,
+				ECM_IP_ADDR_TO_OCTAL(host1_addr),
+				host1_port,
+				ECM_IP_ADDR_TO_OCTAL(host2_addr),
+				host2_port,
+				protocol);
+                break;
+
+        default:
+                return ECM_NOTIFIER_CONNECTION_STATE_INVALID;
+        }
+
+	ci = ecm_db_connection_find_and_ref(host1_addr, host2_addr, protocol, host1_port, host2_port);
+	if (!ci) {
+		DEBUG_TRACE("%px: database connection not found\n", conn);
+		return ECM_NOTIFIER_CONNECTION_STATE_INVALID;
+	}
+
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	if (!feci) {
+		DEBUG_TRACE("%px: failed to find front end connection instance\n", ci);
+		ecm_db_connection_deref(ci);
+		return ECM_NOTIFIER_CONNECTION_STATE_INVALID;
+	}
+
+	accel_state = feci->accel_state_get(feci);
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+
+	switch (accel_state) {
+	case ECM_FRONT_END_ACCELERATION_MODE_ACCEL:
+		return ECM_NOTIFIER_CONNECTION_STATE_ACCEL;
+
+	case ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING:
+		return ECM_NOTIFIER_CONNECTION_STATE_ACCEL_PENDING;
+
+	case ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING:
+		return ECM_NOTIFIER_CONNECTION_STATE_DECEL_PENDING;
+
+	case ECM_FRONT_END_ACCELERATION_MODE_DECEL:
+		return ECM_NOTIFIER_CONNECTION_STATE_DECEL;
+
+	default:
+		DEBUG_TRACE("%px: Marking other state as failed\n", conn);
+		break;
+	}
+
+	return ECM_NOTIFIER_CONNECTION_STATE_FAILED;
+}
+EXPORT_SYMBOL(ecm_notifier_connection_state_get);
diff --git a/qca-nss-ecm/ecm_notifier_pvt.h b/qca-nss-ecm/ecm_notifier_pvt.h
new file mode 100644
index 0000000..00a50d3
--- /dev/null
+++ b/qca-nss-ecm/ecm_notifier_pvt.h
@@ -0,0 +1,18 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+void ecm_notifier_connection_removed(void *arg, struct ecm_db_connection_instance *ci);
+void ecm_notifier_connection_added(void *arg, struct ecm_db_connection_instance *ci);
diff --git a/qca-nss-ecm/ecm_state.c b/qca-nss-ecm/ecm_state.c
new file mode 100644
index 0000000..f1a43d1
--- /dev/null
+++ b/qca-nss-ecm/ecm_state.c
@@ -0,0 +1,943 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2020-2021, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/module.h>
+#include <linux/kthread.h>
+#include <linux/string.h>
+#include <linux/debugfs.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <linux/inet.h>
+#include <linux/ipv6.h>
+#include <linux/netfilter_bridge.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_STATE_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_classifier_default.h"
+#include "ecm_db.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_STATE_FILE_INSTANCE_MAGIC 0xB3FE
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_state_dentry;
+
+/*
+ * Locking of the state - concurrency control
+ */
+static DEFINE_SPINLOCK(ecm_state_lock);					/* Protect the table from SMP access. */
+
+/*
+ * Character device stuff - used to communicate status back to user space
+ */
+static int ecm_state_dev_major_id = 0;			/* Major ID of registered char dev from which we can dump out state to userspace */
+
+/*
+ * Buffer sizes
+ */
+#define ECM_STATE_FILE_PREFIX_SIZE 128
+#define ECM_STATE_FILE_PREFIX_LEVELS_MAX 10
+#define ECM_STATE_FILE_BUFFER_SIZE 32768
+
+/*
+ * Output selection flags
+ */
+#define ECM_STATE_FILE_OUTPUT_CONNECTIONS 1
+#define ECM_STATE_FILE_OUTPUT_MAPPINGS 2
+#define ECM_STATE_FILE_OUTPUT_HOSTS 4
+#define ECM_STATE_FILE_OUTPUT_NODES 8
+#define ECM_STATE_FILE_OUTPUT_INTERFACES 16
+#define ECM_STATE_FILE_OUTPUT_CONNECTIONS_CHAIN 32
+#define ECM_STATE_FILE_OUTPUT_MAPPINGS_CHAIN 64
+#define ECM_STATE_FILE_OUTPUT_HOSTS_CHAIN 128
+#define ECM_STATE_FILE_OUTPUT_NODES_CHAIN 256
+#define ECM_STATE_FILE_OUTPUT_INTERFACES_CHAIN 512
+#define ECM_STATE_FILE_OUTPUT_PROTOCOL_COUNTS 1024
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+#define ECM_STATE_FILE_OUTPUT_CLASSIFIER_TYPE_ASSIGNMENTS 2048
+#endif
+
+/*
+ * struct ecm_state_file_instance
+ *	Structure used as state per open instance of our db state file
+ */
+struct ecm_state_file_instance {
+	int output_mask;				/* The content types wanted by the user */
+	struct ecm_db_connection_instance *ci;		/* All connections list iterator */
+	struct ecm_db_mapping_instance *mi;		/* All mappings list iterator */
+	struct ecm_db_host_instance *hi;		/* All hosts list iterator */
+	struct ecm_db_node_instance *ni;		/* All nodes list iterator */
+	struct ecm_db_iface_instance *ii;		/* All interfaces list iterator */
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+	struct ecm_db_connection_instance *classifier_type_assignments[ECM_CLASSIFIER_TYPES];
+							/* Classifier type connection assignments iterator, one for each classifier type */
+#endif
+	int connection_hash_index;			/* Connection hash table lengths iterator */
+	int mapping_hash_index;				/* Mapping hash table lengths iterator */
+	int host_hash_index;				/* Host hash table lengths iterator */
+	int node_hash_index;				/* Node hash table lengths iterator */
+	int iface_hash_index;				/* Interface hash table lengths iterator */
+	int protocol;					/* Protocol connection count iterator */
+
+	char prefix[ECM_STATE_FILE_PREFIX_SIZE];	/* This is the prefix added to every message written */
+	int prefix_levels[ECM_STATE_FILE_PREFIX_LEVELS_MAX];
+							/* How many nested prefixes supported */
+	int prefix_level;				/* Prefix nest level */
+
+	char msg[ECM_STATE_FILE_BUFFER_SIZE];		/* The message written / being returned to the reader */
+	char *msgp;					/* Points into the msg buffer as we output it to the reader piece by piece */
+	int msg_len;					/* Length of the msg buffer still to be written out */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+static int ecm_state_file_output_mask = ECM_STATE_FILE_OUTPUT_CONNECTIONS;
+							/* Bit mask specifies which data to output in the state file */
+
+/*
+ * ecm_state_write_reset()
+ *	Reset the msg buffer, specifying a new initial prefix
+ *
+ * Returns 0 on success
+ */
+int ecm_state_write_reset(struct ecm_state_file_instance *sfi, char *prefix)
+{
+	int result;
+
+	DEBUG_CHECK_MAGIC(sfi, ECM_STATE_FILE_INSTANCE_MAGIC, "%px: magic failed", sfi);
+	sfi->msgp = sfi->msg;
+	sfi->msg_len = 0;
+
+	result = snprintf(sfi->prefix, ECM_STATE_FILE_PREFIX_SIZE, "%s", prefix);
+	if ((result < 0) || (result >= ECM_STATE_FILE_PREFIX_SIZE)) {
+		return -1;
+	}
+	sfi->prefix_level = 0;
+	sfi->prefix_levels[sfi->prefix_level] = result;
+	return 0;
+}
+
+/*
+ * ecm_state_prefix_add()
+ *	Add another level to the prefix
+ *
+ * Returns 0 on success
+ */
+int ecm_state_prefix_add(struct ecm_state_file_instance *sfi, char *prefix)
+{
+	int pxsz;
+	int pxremain;
+	int result;
+
+	DEBUG_CHECK_MAGIC(sfi, ECM_STATE_FILE_INSTANCE_MAGIC, "%px: magic failed", sfi);
+
+	pxsz = sfi->prefix_levels[sfi->prefix_level];
+	pxremain = ECM_STATE_FILE_PREFIX_SIZE - pxsz;
+	result = snprintf(sfi->prefix + pxsz, pxremain, ".%s", prefix);
+	if ((result < 0) || (result >= pxremain)) {
+		return -1;
+	}
+
+	sfi->prefix_level++;
+	DEBUG_ASSERT(sfi->prefix_level < ECM_STATE_FILE_PREFIX_LEVELS_MAX, "Bad prefix handling\n");
+	sfi->prefix_levels[sfi->prefix_level] = pxsz + result;
+	return 0;
+}
+
+/*
+ * ecm_state_prefix_index_add()
+ *	Add another level (numeric) to the prefix
+ *
+ * Returns 0 on success
+ */
+int ecm_state_prefix_index_add(struct ecm_state_file_instance *sfi, uint32_t index)
+{
+	int pxsz;
+	int pxremain;
+	int result;
+
+	DEBUG_CHECK_MAGIC(sfi, ECM_STATE_FILE_INSTANCE_MAGIC, "%px: magic failed", sfi);
+
+	pxsz = sfi->prefix_levels[sfi->prefix_level];
+	pxremain = ECM_STATE_FILE_PREFIX_SIZE - pxsz;
+	result = snprintf(sfi->prefix + pxsz, pxremain, ".%u", index);
+	if ((result < 0) || (result >= pxremain)) {
+		return -1;
+	}
+
+	sfi->prefix_level++;
+	DEBUG_ASSERT(sfi->prefix_level < ECM_STATE_FILE_PREFIX_LEVELS_MAX, "Bad prefix handling\n");
+	sfi->prefix_levels[sfi->prefix_level] = pxsz + result;
+	return 0;
+}
+
+/*
+ * ecm_state_prefix_remove()
+ *	Remove level from the prefix
+ *
+ * Returns 0 on success
+ */
+int ecm_state_prefix_remove(struct ecm_state_file_instance *sfi)
+{
+	int pxsz;
+
+	DEBUG_CHECK_MAGIC(sfi, ECM_STATE_FILE_INSTANCE_MAGIC, "%px: magic failed", sfi);
+
+	sfi->prefix_level--;
+	DEBUG_ASSERT(sfi->prefix_level >= 0, "Bad prefix handling\n");
+	pxsz = sfi->prefix_levels[sfi->prefix_level];
+	sfi->prefix[pxsz] = 0;
+	return 0;
+}
+
+/*
+ * ecm_state_write()
+ *	Write out to the message buffer, prefix is added automatically.
+ *
+ * Returns 0 on success
+ */
+int ecm_state_write(struct ecm_state_file_instance *sfi, char *name, char *fmt, ...)
+{
+	int remain;
+	char *ptr;
+	int result;
+	va_list args;
+
+	DEBUG_CHECK_MAGIC(sfi, ECM_STATE_FILE_INSTANCE_MAGIC, "%px: magic failed", sfi);
+
+	remain = ECM_STATE_FILE_BUFFER_SIZE - sfi->msg_len;
+	ptr = sfi->msg + sfi->msg_len;
+	result = snprintf(ptr, remain, "%s.%s=", sfi->prefix, name);
+	if ((result < 0) || (result >= remain)) {
+		return -1;
+	}
+
+	sfi->msg_len += result;
+	remain -= result;
+	ptr += result;
+
+	va_start(args, fmt);
+	result = vsnprintf(ptr, remain, fmt, args);
+	va_end(args);
+	if ((result < 0) || (result >= remain)) {
+		return -2;
+	}
+
+	sfi->msg_len += result;
+	remain -= result;
+	ptr += result;
+
+	result = snprintf(ptr, remain, "\n");
+	if ((result < 0) || (result >= remain)) {
+		return -3;
+	}
+
+	sfi->msg_len += result;
+	return 0;
+}
+
+/*
+ * ecm_state_char_dev_conn_msg_prep()
+ *	Prepare a connection message
+ */
+static bool ecm_state_char_dev_conn_msg_prep(struct ecm_state_file_instance *sfi)
+{
+	int result;
+
+	DEBUG_TRACE("%px: Prep conn msg for %px\n", sfi, sfi->ci);
+
+	if ((result = ecm_state_write_reset(sfi, "conns"))) {
+		return result;
+	}
+	return ecm_db_connection_state_get(sfi, sfi->ci);
+}
+
+/*
+ * ecm_state_char_dev_mapping_msg_prep()
+ *	Prepare a mapping message
+ */
+static bool ecm_state_char_dev_mapping_msg_prep(struct ecm_state_file_instance *sfi)
+{
+	int result;
+
+	DEBUG_TRACE("%px: Prep mapping msg for %px\n", sfi, sfi->mi);
+
+	if ((result = ecm_state_write_reset(sfi, "mappings"))) {
+		return result;
+	}
+	return ecm_db_mapping_state_get(sfi, sfi->mi);
+}
+
+/*
+ * ecm_state_char_dev_host_msg_prep()
+ *	Prepare a host message
+ */
+static bool ecm_state_char_dev_host_msg_prep(struct ecm_state_file_instance *sfi)
+{
+	int result;
+
+	DEBUG_TRACE("%px: Prep host msg for %px\n", sfi, sfi->hi);
+
+	if ((result = ecm_state_write_reset(sfi, "hosts"))) {
+		return result;
+	}
+
+	return ecm_db_host_state_get(sfi, sfi->hi);
+}
+
+/*
+ * ecm_state_char_dev_node_msg_prep()
+ *	Prepare a node message
+ */
+static bool ecm_state_char_dev_node_msg_prep(struct ecm_state_file_instance *sfi)
+{
+	int result;
+
+	DEBUG_TRACE("%px: Prep node msg for %px\n", sfi, sfi->ni);
+
+	if ((result = ecm_state_write_reset(sfi, "nodes"))) {
+		return result;
+	}
+
+	return ecm_db_node_state_get(sfi, sfi->ni);
+}
+
+/*
+ * ecm_state_char_dev_iface_msg_prep()
+ *	Prepare an interface message
+ */
+static int ecm_state_char_dev_iface_msg_prep(struct ecm_state_file_instance *sfi)
+{
+	int result;
+
+	DEBUG_TRACE("%px: Prep iface msg for %px\n", sfi, sfi->ii);
+
+	if ((result = ecm_state_write_reset(sfi, "ifaces"))) {
+		return result;
+	}
+	return ecm_db_iface_state_get(sfi, sfi->ii);
+}
+
+/*
+ * ecm_state_char_dev_conn_chain_msg_prep()
+ *	Generate an conn hash table chain message
+ */
+static bool ecm_state_char_dev_conn_chain_msg_prep(struct ecm_state_file_instance *sfi)
+{
+	int result;
+	int chain_len;
+	DEBUG_TRACE("%px: Prep conn chain msg\n", sfi);
+
+	/*
+	 * Get hash table chain length
+	 */
+	chain_len = ecm_db_connection_hash_table_lengths_get(sfi->connection_hash_index);
+
+	if ((result = ecm_state_write_reset(sfi, "conn_chain"))) {
+		return result;
+	}
+	if ((result = ecm_state_prefix_index_add(sfi, sfi->connection_hash_index))) {
+		return result;
+	}
+	return ecm_state_write(sfi, "length", "%d", chain_len);
+}
+
+/*
+ * ecm_state_char_dev_mapping_chain_msg_prep()
+ *	Generate an mapping hash table chain message
+ */
+static bool ecm_state_char_dev_mapping_chain_msg_prep(struct ecm_state_file_instance *sfi)
+{
+	int result;
+	int chain_len;
+	DEBUG_TRACE("%px: Prep mapping chain msg\n", sfi);
+
+	/*
+	 * Get hash table chain length
+	 */
+	chain_len = ecm_db_mapping_hash_table_lengths_get(sfi->mapping_hash_index);
+
+	if ((result = ecm_state_write_reset(sfi, "mapping_chain"))) {
+		return result;
+	}
+	if ((result = ecm_state_prefix_index_add(sfi, sfi->mapping_hash_index))) {
+		return result;
+	}
+	return ecm_state_write(sfi, "length", "%d", chain_len);
+}
+
+/*
+ * ecm_state_char_dev_host_chain_msg_prep()
+ *	Generate an host hash table chain message
+ */
+static bool ecm_state_char_dev_host_chain_msg_prep(struct ecm_state_file_instance *sfi)
+{
+	int result;
+	int chain_len;
+	DEBUG_TRACE("%px: Prep host chain msg\n", sfi);
+
+	/*
+	 * Get hash table chain length
+	 */
+	chain_len = ecm_db_host_hash_table_lengths_get(sfi->host_hash_index);
+
+	if ((result = ecm_state_write_reset(sfi, "host_chain"))) {
+		return result;
+	}
+	if ((result = ecm_state_prefix_index_add(sfi, sfi->host_hash_index))) {
+		return result;
+	}
+	return ecm_state_write(sfi, "length", "%d", chain_len);
+}
+
+/*
+ * ecm_state_char_dev_node_chain_msg_prep()
+ *	Generate an node hash table chain message
+ */
+static bool ecm_state_char_dev_node_chain_msg_prep(struct ecm_state_file_instance *sfi)
+{
+	int result;
+	int chain_len;
+	DEBUG_TRACE("%px: Prep node chain msg\n", sfi);
+
+	/*
+	 * Get hash table chain length
+	 */
+	chain_len = ecm_db_node_hash_table_lengths_get(sfi->node_hash_index);
+
+	if ((result = ecm_state_write_reset(sfi, "node_chain"))) {
+		return result;
+	}
+	if ((result = ecm_state_prefix_index_add(sfi, sfi->node_hash_index))) {
+		return result;
+	}
+	return ecm_state_write(sfi, "length", "%d", chain_len);
+}
+
+/*
+ * ecm_state_char_dev_iface_chain_msg_prep()
+ *	Generate an interface hash table chain message
+ */
+static bool ecm_state_char_dev_iface_chain_msg_prep(struct ecm_state_file_instance *sfi)
+{
+	int result;
+	int chain_len;
+	DEBUG_TRACE("%px: Prep iface chain msg\n", sfi);
+
+	/*
+	 * Get hash table chain length
+	 */
+	chain_len = ecm_db_iface_hash_table_lengths_get(sfi->iface_hash_index);
+
+	if ((result = ecm_state_write_reset(sfi, "iface_chain"))) {
+		return result;
+	}
+	if ((result = ecm_state_prefix_index_add(sfi, sfi->iface_hash_index))) {
+		return result;
+	}
+	return ecm_state_write(sfi, "length", "%d", chain_len);
+}
+
+/*
+ * ecm_state_char_dev_protocol_count_msg_prep()
+ *	Generate a protocol usage message
+ */
+static bool ecm_state_char_dev_protocol_count_msg_prep(struct ecm_state_file_instance *sfi)
+{
+	int result;
+	int count;
+	DEBUG_TRACE("%px: Prep protocol msg\n", sfi);
+
+	/*
+	 * Get protocol connection total count
+	 */
+	count = ecm_db_connection_count_by_protocol_get(sfi->protocol);
+
+	if ((result = ecm_state_write_reset(sfi, "protocol"))) {
+		return result;
+	}
+	if ((result = ecm_state_prefix_index_add(sfi, sfi->protocol))) {
+		return result;
+	}
+	return ecm_state_write(sfi, "connections", "%d", count);
+}
+
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+/*
+ * ecm_state_char_dev_cta_msg_prep()
+ *	Generate a classifier type assignment message
+ */
+static int ecm_state_char_dev_cta_msg_prep(struct ecm_state_file_instance *sfi, ecm_classifier_type_t ca_type)
+{
+	struct ecm_db_connection_instance *ci;
+	int result;
+
+	DEBUG_TRACE("%px: Prep classifier type assignment msg: %d\n", sfi, ca_type);
+
+	ci = sfi->classifier_type_assignments[ca_type];
+	if (!ci) {
+		return 0;
+	}
+
+	if ((result = ecm_state_write_reset(sfi, "cta"))) {
+		return result;
+	}
+	if ((result = ecm_state_prefix_index_add(sfi, ca_type))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "conn.serial", "%u", ecm_db_connection_serial_get(ci)))) {
+		return result;
+	}
+
+	/*
+	 * Prep next connection for when we are called again, releasing this one.
+	 */
+	sfi->classifier_type_assignments[ca_type] = ecm_db_connection_by_classifier_type_assignment_get_and_ref_next(ci, ca_type);
+	ecm_db_connection_by_classifier_type_assignment_deref(ci, ca_type);
+	return 0;
+}
+
+/*
+ * ecm_state_file_classifier_type_assignments_release()
+ *	Releases any uniterated classifier assignments
+ */
+static void ecm_state_file_classifier_type_assignments_release(struct ecm_state_file_instance *sfi)
+{
+	ecm_classifier_type_t ca_type;
+
+	for (ca_type = 0; ca_type < ECM_CLASSIFIER_TYPES; ++ca_type) {
+		struct ecm_db_connection_instance *ci;
+
+		ci = sfi->classifier_type_assignments[ca_type];
+		if (!ci) {
+			continue;
+		}
+
+		ecm_db_connection_by_classifier_type_assignment_deref(ci, ca_type);
+	}
+}
+#endif
+
+/*
+ * ecm_state_char_device_open()
+ *	Opens the special char device file which we use to dump our state.
+ */
+static int ecm_state_char_device_open(struct inode *inode, struct file *file)
+{
+	struct ecm_state_file_instance *sfi;
+
+	DEBUG_INFO("State open\n");
+
+	/*
+	 * Allocate state information for the reading
+	 */
+	DEBUG_ASSERT(file->private_data == NULL, "unexpected double open: %px?\n", file->private_data);
+
+	sfi = (struct ecm_state_file_instance *)kzalloc(sizeof(struct ecm_state_file_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!sfi) {
+		return -ENOMEM;
+	}
+	DEBUG_SET_MAGIC(sfi, ECM_STATE_FILE_INSTANCE_MAGIC);
+	file->private_data = sfi;
+
+	/*
+	 * Snapshot output mask for this file
+	 */
+	spin_lock_bh(&ecm_state_lock);
+	sfi->output_mask = ecm_state_file_output_mask;
+	spin_unlock_bh(&ecm_state_lock);
+
+	/*
+	 * Get the first indicies for hash and protocol stats should they be needed.
+	 * NOTE: There are no references held here so it does not matter to get them all even if they are not wanted.
+	 */
+	sfi->connection_hash_index = ecm_db_connection_hash_index_get_first();
+	sfi->mapping_hash_index = ecm_db_mapping_hash_index_get_first();
+	sfi->host_hash_index = ecm_db_host_hash_index_get_first();
+	sfi->node_hash_index = ecm_db_node_hash_index_get_first();
+	sfi->iface_hash_index = ecm_db_iface_hash_index_get_first();
+	sfi->protocol = ecm_db_protocol_get_first();
+
+	/*
+	 * Take references to each object list that we are going to generate state for.
+	 */
+	if (sfi->output_mask & ECM_STATE_FILE_OUTPUT_CONNECTIONS) {
+		sfi->ci = ecm_db_connections_get_and_ref_first();
+	}
+	if (sfi->output_mask & ECM_STATE_FILE_OUTPUT_MAPPINGS) {
+		sfi->mi = ecm_db_mappings_get_and_ref_first();
+	}
+	if (sfi->output_mask & ECM_STATE_FILE_OUTPUT_HOSTS) {
+		sfi->hi = ecm_db_hosts_get_and_ref_first();
+	}
+	if (sfi->output_mask & ECM_STATE_FILE_OUTPUT_NODES) {
+		sfi->ni = ecm_db_nodes_get_and_ref_first();
+	}
+	if (sfi->output_mask & ECM_STATE_FILE_OUTPUT_INTERFACES) {
+		sfi->ii = ecm_db_interfaces_get_and_ref_first();
+	}
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+	if (sfi->output_mask & ECM_STATE_FILE_OUTPUT_CLASSIFIER_TYPE_ASSIGNMENTS) {
+		ecm_classifier_type_t ca_type;
+
+		/*
+		 * Iterate all classifier type assignments.
+		 * Hold the head of each list to start us off on our iterating process.
+		 */
+		for (ca_type = 0; ca_type < ECM_CLASSIFIER_TYPES; ++ca_type) {
+			sfi->classifier_type_assignments[ca_type] = ecm_db_connection_by_classifier_type_assignment_get_and_ref_first(ca_type);
+		}
+	}
+#endif
+
+	DEBUG_INFO("State opened %px\n", sfi);
+
+	return 0;
+}
+
+/*
+ * ecm_state_char_device_release()
+ *	Called when a process closes the device file.
+ */
+static int ecm_state_char_device_release(struct inode *inode, struct file *file)
+{
+	struct ecm_state_file_instance *sfi;
+
+	sfi = (struct ecm_state_file_instance *)file->private_data;
+	DEBUG_CHECK_MAGIC(sfi, ECM_STATE_FILE_INSTANCE_MAGIC, "%px: magic failed", sfi);
+	DEBUG_INFO("%px: State close\n", sfi);
+
+	/*
+	 * Release any references held
+	 */
+	if (sfi->ci) {
+		ecm_db_connection_deref(sfi->ci);
+	}
+	if (sfi->mi) {
+		ecm_db_mapping_deref(sfi->mi);
+	}
+	if (sfi->hi) {
+		ecm_db_host_deref(sfi->hi);
+	}
+	if (sfi->ni) {
+		ecm_db_node_deref(sfi->ni);
+	}
+	if (sfi->ii) {
+		ecm_db_iface_deref(sfi->ii);
+	}
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+	ecm_state_file_classifier_type_assignments_release(sfi);
+#endif
+
+	DEBUG_CLEAR_MAGIC(sfi);
+	kfree(sfi);
+
+	return 0;
+}
+
+/*
+ * ecm_state_char_device_read()
+ *	Called to read the state
+ */
+static ssize_t ecm_state_char_device_read(struct file *file,	/* see include/linux/fs.h   */
+			   char *buffer,				/* buffer to fill with data */
+			   size_t length,				/* length of the buffer     */
+			   loff_t *offset)				/* Doesn't apply - this is a char file */
+{
+	struct ecm_state_file_instance *sfi;
+	int bytes_read = 0;						/* Number of bytes actually written to the buffer */
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+	ecm_classifier_type_t ca_type;
+#endif
+
+	sfi = (struct ecm_state_file_instance *)file->private_data;
+	DEBUG_CHECK_MAGIC(sfi, ECM_STATE_FILE_INSTANCE_MAGIC, "%px: magic failed", sfi);
+	DEBUG_TRACE("%px: State read up to length %d bytes\n", sfi, (int)length);
+
+	/*
+	 * If there is still some message remaining to be output then complete that first
+	 */
+	if (sfi->msg_len) {
+		goto char_device_read_output;
+	}
+
+	if (sfi->ci) {
+		struct ecm_db_connection_instance *cin;
+		if (ecm_state_char_dev_conn_msg_prep(sfi)) {
+			return -EIO;
+		}
+
+		/*
+		 * Next connection for when we return
+		 */
+		cin = ecm_db_connection_get_and_ref_next(sfi->ci);
+		ecm_db_connection_deref(sfi->ci);
+		sfi->ci = cin;
+
+		goto char_device_read_output;
+	}
+
+	if (sfi->mi) {
+		struct ecm_db_mapping_instance *min;
+		if (ecm_state_char_dev_mapping_msg_prep(sfi)) {
+			return -EIO;
+		}
+
+		/*
+		 * Next mapping for when we return
+		 */
+		min = ecm_db_mapping_get_and_ref_next(sfi->mi);
+		ecm_db_mapping_deref(sfi->mi);
+		sfi->mi = min;
+
+		goto char_device_read_output;
+	}
+
+	if (sfi->hi) {
+		struct ecm_db_host_instance *hin;
+		if (ecm_state_char_dev_host_msg_prep(sfi)) {
+			return -EIO;
+		}
+
+		/*
+		 * Next host for when we return
+		 */
+		hin = ecm_db_host_get_and_ref_next(sfi->hi);
+		ecm_db_host_deref(sfi->hi);
+		sfi->hi = hin;
+
+		goto char_device_read_output;
+	}
+
+	if (sfi->ni) {
+		struct ecm_db_node_instance *nin;
+		if (ecm_state_char_dev_node_msg_prep(sfi)) {
+			return -EIO;
+		}
+
+		/*
+		 * Next node for when we return
+		 */
+		nin = ecm_db_node_get_and_ref_next(sfi->ni);
+		ecm_db_node_deref(sfi->ni);
+		sfi->ni = nin;
+
+		goto char_device_read_output;
+	}
+
+	if (sfi->ii) {
+		struct ecm_db_iface_instance *iin;
+		if (ecm_state_char_dev_iface_msg_prep(sfi)) {
+			return -EIO;
+		}
+
+		/*
+		 * Next iface for when we return
+		 */
+		iin = ecm_db_interface_get_and_ref_next(sfi->ii);
+		ecm_db_iface_deref(sfi->ii);
+		sfi->ii = iin;
+
+		goto char_device_read_output;
+	}
+
+	if ((sfi->output_mask & ECM_STATE_FILE_OUTPUT_CONNECTIONS_CHAIN) && (sfi->connection_hash_index >= 0)) {
+		if (ecm_state_char_dev_conn_chain_msg_prep(sfi)) {
+			return -EIO;
+		}
+		sfi->connection_hash_index = ecm_db_connection_hash_index_get_next(sfi->connection_hash_index);
+		goto char_device_read_output;
+	}
+
+	if ((sfi->output_mask & ECM_STATE_FILE_OUTPUT_MAPPINGS_CHAIN) && (sfi->mapping_hash_index >= 0)) {
+		if (ecm_state_char_dev_mapping_chain_msg_prep(sfi)) {
+			return -EIO;
+		}
+		sfi->mapping_hash_index = ecm_db_mapping_hash_index_get_next(sfi->mapping_hash_index);
+		goto char_device_read_output;
+	}
+
+	if ((sfi->output_mask & ECM_STATE_FILE_OUTPUT_HOSTS_CHAIN) && (sfi->host_hash_index >= 0)) {
+		if (ecm_state_char_dev_host_chain_msg_prep(sfi)) {
+			return -EIO;
+		}
+		sfi->host_hash_index = ecm_db_host_hash_index_get_next(sfi->host_hash_index);
+		goto char_device_read_output;
+	}
+
+	if ((sfi->output_mask & ECM_STATE_FILE_OUTPUT_NODES_CHAIN) && (sfi->node_hash_index >= 0)) {
+		if (ecm_state_char_dev_node_chain_msg_prep(sfi)) {
+			return -EIO;
+		}
+		sfi->node_hash_index = ecm_db_node_hash_index_get_next(sfi->node_hash_index);
+		goto char_device_read_output;
+	}
+
+	if ((sfi->output_mask & ECM_STATE_FILE_OUTPUT_INTERFACES_CHAIN) && (sfi->iface_hash_index >= 0)) {
+		if (ecm_state_char_dev_iface_chain_msg_prep(sfi)) {
+			return -EIO;
+		}
+		sfi->iface_hash_index = ecm_db_iface_hash_index_get_next(sfi->iface_hash_index);
+		goto char_device_read_output;
+	}
+
+	if ((sfi->output_mask & ECM_STATE_FILE_OUTPUT_PROTOCOL_COUNTS) && (sfi->protocol >= 0)) {
+		if (ecm_state_char_dev_protocol_count_msg_prep(sfi)) {
+			return -EIO;
+		}
+		sfi->protocol = ecm_db_protocol_get_next(sfi->protocol);
+		goto char_device_read_output;
+	}
+
+#ifdef ECM_DB_CTA_TRACK_ENABLE
+	for (ca_type = 0; ca_type < ECM_CLASSIFIER_TYPES; ++ca_type) {
+		if (!sfi->classifier_type_assignments[ca_type]) continue;
+		if (ecm_state_char_dev_cta_msg_prep(sfi, ca_type)) {
+			return -EIO;
+		}
+		goto char_device_read_output;
+	}
+#endif
+
+	/*
+	 * EOF
+	 */
+	return 0;
+
+char_device_read_output:
+
+	/*
+	 * If supplied buffer is small we limit what we output
+	 */
+	bytes_read = sfi->msg_len;
+	if (bytes_read > length) {
+		bytes_read = length;
+	}
+	if (copy_to_user(buffer, sfi->msgp, bytes_read)) {
+		return -EIO;
+	}
+	sfi->msg_len -= bytes_read;
+	sfi->msgp += bytes_read;
+
+	DEBUG_TRACE("State read done, bytes_read %d bytes\n", bytes_read);
+
+	/*
+	 * Most read functions return the number of bytes put into the buffer
+	 */
+	return bytes_read;
+}
+
+/*
+ * ecm_state_char_device_write()
+ */
+static ssize_t ecm_state_char_device_write(struct file *filp, const char *buff, size_t len, loff_t * off)
+{
+	return -EINVAL;
+}
+
+/*
+ * File operations used in the char device
+ *	NOTE: The char device is a simple file that allows us to dump our connection tracking state
+ */
+static struct file_operations ecm_state_fops = {
+	.read = ecm_state_char_device_read,
+	.write = ecm_state_char_device_write,
+	.open = ecm_state_char_device_open,
+	.release = ecm_state_char_device_release
+};
+
+/*
+ * ecm_state_init()
+ */
+int ecm_state_init(struct dentry *dentry)
+{
+	int result = -1;
+	DEBUG_INFO("ECM State init\n");
+
+	ecm_state_dentry = debugfs_create_dir("ecm_state", dentry);
+	if (!ecm_state_dentry) {
+		DEBUG_ERROR("Failed to create ecm state directory in debugfs\n");
+		return -1;
+	}
+
+	if (!debugfs_create_u32("state_dev_major", S_IRUGO, ecm_state_dentry,
+					(u32 *)&ecm_state_dev_major_id)) {
+		DEBUG_ERROR("Failed to create ecm state dev major file in debugfs\n");
+		goto init_cleanup;
+	}
+
+	if (!debugfs_create_u32("state_file_output_mask", S_IRUGO | S_IWUSR, ecm_state_dentry,
+					(u32 *)&ecm_state_file_output_mask)) {
+		DEBUG_ERROR("Failed to create ecm state output mask file in debugfs\n");
+		goto init_cleanup;
+	}
+
+	/*
+	 * Register a char device that we will use to provide a dump of our state
+	 */
+	result = register_chrdev(0, "ecm_state", &ecm_state_fops);
+	if (result < 0) {
+                DEBUG_ERROR("Failed to register chrdev %d\n", result);
+		goto init_cleanup;
+	}
+	ecm_state_dev_major_id = result;
+	DEBUG_TRACE("registered chr dev major id assigned %d\n", ecm_state_dev_major_id);
+
+	return 0;
+
+init_cleanup:
+
+	debugfs_remove_recursive(ecm_state_dentry);
+	return result;
+}
+
+/*
+ * ecm_state_exit()
+ */
+void ecm_state_exit(void)
+{
+	DEBUG_INFO("ECM State exit\n");
+
+	unregister_chrdev(ecm_state_dev_major_id, "ecm_state");
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_state_dentry) {
+		debugfs_remove_recursive(ecm_state_dentry);
+	}
+}
diff --git a/qca-nss-ecm/ecm_state.h b/qca-nss-ecm/ecm_state.h
new file mode 100644
index 0000000..5fbf250
--- /dev/null
+++ b/qca-nss-ecm/ecm_state.h
@@ -0,0 +1,26 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2021, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+struct ecm_state_file_instance;
+
+int ecm_state_write_reset(struct ecm_state_file_instance *sfi, char *prefix);
+
+int ecm_state_prefix_add(struct ecm_state_file_instance *sfi, char *prefix);
+int ecm_state_prefix_index_add(struct ecm_state_file_instance *sfi, uint32_t index);
+int ecm_state_prefix_remove(struct ecm_state_file_instance *sfi);
+
+int ecm_state_write(struct ecm_state_file_instance *sfi, char *name, char *fmt, ...);
+
diff --git a/qca-nss-ecm/ecm_tracker.c b/qca-nss-ecm/ecm_tracker.c
new file mode 100644
index 0000000..31e9e87
--- /dev/null
+++ b/qca-nss-ecm/ecm_tracker.c
@@ -0,0 +1,1203 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, 2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/sysctl.h>
+#include <linux/kthread.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_TRACKER_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+int ecm_tracker_data_total = 0;				/* Data total for all skb list instances */
+int ecm_tracker_data_buffer_total = 0;			/* Data buffer total allocated for all skb list instances */
+int ecm_tracker_data_limit = ECM_TRACKER_GLOBAL_DATA_LIMIT_DEFAULT;
+int ecm_tracker_data_buffer_limit = ECM_TRACKER_GLOBAL_DATA_BUFFER_LIMIT_DEFAULT;
+							/* Tracked limit for data across all instances */
+static DEFINE_SPINLOCK(ecm_tracker_lock);		/* Global lock for the tracker globals */
+#endif
+
+struct ecm_tracker_ip_protocols;
+
+typedef bool (*ecm_tracker_ip_header_helper_method_t)(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr);
+							/* A header helper method is used to inspect a protocol header, determine if it is valid, its size etc. and where any next header will be esp. important for IPv6 */
+
+/*
+ * Forward references for the header helpers
+ */
+static bool ecm_tracker_ip_header_helper_tcp(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr);
+static bool ecm_tracker_ip_header_helper_udp(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr);
+static bool ecm_tracker_ip_header_helper_icmp(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr);
+static bool ecm_tracker_ip_header_helper_unknown(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr);
+static bool ecm_tracker_ip_header_helper_gre(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr);
+#ifdef ECM_IPV6_ENABLE
+static bool ecm_tracker_ip_header_helper_ipv6_generic(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr);
+static bool ecm_tracker_ip_header_helper_ipv6_fragment(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr);
+static bool ecm_tracker_ip_header_helper_ah(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr);
+static bool ecm_tracker_ip_header_helper_ipv6_icmp(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr);
+#endif
+
+/*
+ * struct ecm_tracker_ip_protocols_known[]
+ *	A list of protocols known to the tracker and which it will record the location of in its ecm_tracker_ip_header.
+ *
+ * This is especially important for IPv6 which can have multiple headers in its packet.
+ */
+static struct ecm_tracker_ip_protocols {
+	uint8_t ip_protocol;					/* The IP protocol we want to detect and record its information */
+	ecm_tracker_ip_protocol_type_t ecm_ip_protocol;		/* The ECM Tracker protocol identifier equivalent */
+	char *name;						/* Visual name of the protocol */
+	ecm_tracker_ip_header_helper_method_t header_helper;	/* A function used to help process the header, e.g. its size etc. When a NULL helper is located, header processing stops. */
+} ecm_tracker_ip_protocols_known[256] =
+{
+#ifdef ECM_IPV6_ENABLE
+	{0, ECM_TRACKER_IP_PROTOCOL_TYPE_IPV6_HBH, "ipv6_hbh", ecm_tracker_ip_header_helper_ipv6_generic},
+#else
+	{0, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "0", ecm_tracker_ip_header_helper_unknown},
+#endif
+	{1, ECM_TRACKER_IP_PROTOCOL_TYPE_ICMP, "icmp", ecm_tracker_ip_header_helper_icmp},
+	{2, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "2", ecm_tracker_ip_header_helper_unknown},
+	{3, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "3", ecm_tracker_ip_header_helper_unknown},
+	{4, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "4", ecm_tracker_ip_header_helper_unknown},
+	{5, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "5", ecm_tracker_ip_header_helper_unknown},
+	{6, ECM_TRACKER_IP_PROTOCOL_TYPE_TCP, "tcp", ecm_tracker_ip_header_helper_tcp},
+	{7, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "7", ecm_tracker_ip_header_helper_unknown},
+	{8, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "8", ecm_tracker_ip_header_helper_unknown},
+	{9, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "9", ecm_tracker_ip_header_helper_unknown},
+	{10, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "10", ecm_tracker_ip_header_helper_unknown},
+	{11, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "11", ecm_tracker_ip_header_helper_unknown},
+	{12, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "12", ecm_tracker_ip_header_helper_unknown},
+	{13, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "13", ecm_tracker_ip_header_helper_unknown},
+	{14, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "14", ecm_tracker_ip_header_helper_unknown},
+	{15, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "15", ecm_tracker_ip_header_helper_unknown},
+	{16, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "16", ecm_tracker_ip_header_helper_unknown},
+	{17, ECM_TRACKER_IP_PROTOCOL_TYPE_UDP, "udp", ecm_tracker_ip_header_helper_udp},
+	{18, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "18", ecm_tracker_ip_header_helper_unknown},
+	{19, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "19", ecm_tracker_ip_header_helper_unknown},
+	{20, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "20", ecm_tracker_ip_header_helper_unknown},
+	{21, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "21", ecm_tracker_ip_header_helper_unknown},
+	{22, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "22", ecm_tracker_ip_header_helper_unknown},
+	{23, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "23", ecm_tracker_ip_header_helper_unknown},
+	{24, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "24", ecm_tracker_ip_header_helper_unknown},
+	{25, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "25", ecm_tracker_ip_header_helper_unknown},
+	{26, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "26", ecm_tracker_ip_header_helper_unknown},
+	{27, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "27", ecm_tracker_ip_header_helper_unknown},
+	{28, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "28", ecm_tracker_ip_header_helper_unknown},
+	{29, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "29", ecm_tracker_ip_header_helper_unknown},
+	{30, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "30", ecm_tracker_ip_header_helper_unknown},
+	{31, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "31", ecm_tracker_ip_header_helper_unknown},
+	{32, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "32", ecm_tracker_ip_header_helper_unknown},
+	{33, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "33", ecm_tracker_ip_header_helper_unknown},
+	{34, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "34", ecm_tracker_ip_header_helper_unknown},
+	{35, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "35", ecm_tracker_ip_header_helper_unknown},
+	{36, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "36", ecm_tracker_ip_header_helper_unknown},
+	{37, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "37", ecm_tracker_ip_header_helper_unknown},
+	{38, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "38", ecm_tracker_ip_header_helper_unknown},
+	{39, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "39", ecm_tracker_ip_header_helper_unknown},
+	{40, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "40", ecm_tracker_ip_header_helper_unknown},
+	{41, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "41", ecm_tracker_ip_header_helper_unknown},
+	{42, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "42", ecm_tracker_ip_header_helper_unknown},
+#ifdef ECM_IPV6_ENABLE
+	{43, ECM_TRACKER_IP_PROTOCOL_TYPE_IPV6_ROUTING, "ipv6_routing", ecm_tracker_ip_header_helper_ipv6_generic},
+	{44, ECM_TRACKER_IP_PROTOCOL_TYPE_IPV6_FRAGMENT, "ipv6_fragment", ecm_tracker_ip_header_helper_ipv6_fragment},
+#else
+	{43, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "43", ecm_tracker_ip_header_helper_unknown},
+	{44, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "44", ecm_tracker_ip_header_helper_unknown},
+#endif
+	{45, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "45", ecm_tracker_ip_header_helper_unknown},
+	{46, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "46", ecm_tracker_ip_header_helper_unknown},
+	{47, ECM_TRACKER_IP_PROTOCOL_TYPE_GRE, "gre", ecm_tracker_ip_header_helper_gre},
+	{48, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "48", ecm_tracker_ip_header_helper_unknown},
+	{49, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "49", ecm_tracker_ip_header_helper_unknown},
+	{50, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "50", ecm_tracker_ip_header_helper_unknown},
+#ifdef ECM_IPV6_ENABLE
+	{51, ECM_TRACKER_IP_PROTOCOL_TYPE_AH, "ah", ecm_tracker_ip_header_helper_ah},
+#else
+	{51, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "51", ecm_tracker_ip_header_helper_unknown},
+#endif
+	{52, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "52", ecm_tracker_ip_header_helper_unknown},
+	{53, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "53", ecm_tracker_ip_header_helper_unknown},
+	{54, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "54", ecm_tracker_ip_header_helper_unknown},
+	{55, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "55", ecm_tracker_ip_header_helper_unknown},
+#ifdef ECM_IPV6_ENABLE
+	{56, ECM_TRACKER_IP_PROTOCOL_TYPE_IPV6_ICMP, "ipv6_icmp", ecm_tracker_ip_header_helper_ipv6_icmp},
+#else
+	{56, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "56", ecm_tracker_ip_header_helper_unknown},
+#endif
+	{57, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "57", ecm_tracker_ip_header_helper_unknown},
+	{58, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "58", ecm_tracker_ip_header_helper_unknown},
+	{59, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "59", ecm_tracker_ip_header_helper_unknown},
+#ifdef ECM_IPV6_ENABLE
+	{60, ECM_TRACKER_IP_PROTOCOL_TYPE_IPV6_DO, "ipv6_do", ecm_tracker_ip_header_helper_ipv6_generic},
+#else
+	{60, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "60", ecm_tracker_ip_header_helper_unknown},
+#endif
+	{61, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "61", ecm_tracker_ip_header_helper_unknown},
+	{62, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "62", ecm_tracker_ip_header_helper_unknown},
+	{63, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "63", ecm_tracker_ip_header_helper_unknown},
+	{64, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "64", ecm_tracker_ip_header_helper_unknown},
+	{65, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "65", ecm_tracker_ip_header_helper_unknown},
+	{66, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "66", ecm_tracker_ip_header_helper_unknown},
+	{67, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "67", ecm_tracker_ip_header_helper_unknown},
+	{68, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "68", ecm_tracker_ip_header_helper_unknown},
+	{69, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "69", ecm_tracker_ip_header_helper_unknown},
+	{70, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "70", ecm_tracker_ip_header_helper_unknown},
+	{71, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "71", ecm_tracker_ip_header_helper_unknown},
+	{72, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "72", ecm_tracker_ip_header_helper_unknown},
+	{73, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "73", ecm_tracker_ip_header_helper_unknown},
+	{74, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "74", ecm_tracker_ip_header_helper_unknown},
+	{75, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "75", ecm_tracker_ip_header_helper_unknown},
+	{76, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "76", ecm_tracker_ip_header_helper_unknown},
+	{77, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "77", ecm_tracker_ip_header_helper_unknown},
+	{78, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "78", ecm_tracker_ip_header_helper_unknown},
+	{79, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "79", ecm_tracker_ip_header_helper_unknown},
+	{80, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "80", ecm_tracker_ip_header_helper_unknown},
+	{81, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "81", ecm_tracker_ip_header_helper_unknown},
+	{82, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "82", ecm_tracker_ip_header_helper_unknown},
+	{83, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "83", ecm_tracker_ip_header_helper_unknown},
+	{84, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "84", ecm_tracker_ip_header_helper_unknown},
+	{85, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "85", ecm_tracker_ip_header_helper_unknown},
+	{86, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "86", ecm_tracker_ip_header_helper_unknown},
+	{87, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "87", ecm_tracker_ip_header_helper_unknown},
+	{88, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "88", ecm_tracker_ip_header_helper_unknown},
+	{89, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "89", ecm_tracker_ip_header_helper_unknown},
+	{90, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "90", ecm_tracker_ip_header_helper_unknown},
+	{91, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "91", ecm_tracker_ip_header_helper_unknown},
+	{92, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "92", ecm_tracker_ip_header_helper_unknown},
+	{93, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "93", ecm_tracker_ip_header_helper_unknown},
+	{94, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "94", ecm_tracker_ip_header_helper_unknown},
+	{95, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "95", ecm_tracker_ip_header_helper_unknown},
+	{96, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "96", ecm_tracker_ip_header_helper_unknown},
+	{97, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "97", ecm_tracker_ip_header_helper_unknown},
+	{98, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "98", ecm_tracker_ip_header_helper_unknown},
+	{99, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "99", ecm_tracker_ip_header_helper_unknown},
+	{100, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "100", ecm_tracker_ip_header_helper_unknown},
+	{101, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "101", ecm_tracker_ip_header_helper_unknown},
+	{102, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "102", ecm_tracker_ip_header_helper_unknown},
+	{103, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "103", ecm_tracker_ip_header_helper_unknown},
+	{104, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "104", ecm_tracker_ip_header_helper_unknown},
+	{105, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "105", ecm_tracker_ip_header_helper_unknown},
+	{106, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "106", ecm_tracker_ip_header_helper_unknown},
+	{107, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "107", ecm_tracker_ip_header_helper_unknown},
+	{108, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "108", ecm_tracker_ip_header_helper_unknown},
+	{109, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "109", ecm_tracker_ip_header_helper_unknown},
+	{110, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "110", ecm_tracker_ip_header_helper_unknown},
+	{111, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "111", ecm_tracker_ip_header_helper_unknown},
+	{112, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "112", ecm_tracker_ip_header_helper_unknown},
+	{113, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "113", ecm_tracker_ip_header_helper_unknown},
+	{114, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "114", ecm_tracker_ip_header_helper_unknown},
+	{115, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "115", ecm_tracker_ip_header_helper_unknown},
+	{116, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "116", ecm_tracker_ip_header_helper_unknown},
+	{117, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "117", ecm_tracker_ip_header_helper_unknown},
+	{118, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "118", ecm_tracker_ip_header_helper_unknown},
+	{119, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "119", ecm_tracker_ip_header_helper_unknown},
+	{120, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "120", ecm_tracker_ip_header_helper_unknown},
+	{121, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "121", ecm_tracker_ip_header_helper_unknown},
+	{122, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "122", ecm_tracker_ip_header_helper_unknown},
+	{123, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "123", ecm_tracker_ip_header_helper_unknown},
+	{124, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "124", ecm_tracker_ip_header_helper_unknown},
+	{125, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "125", ecm_tracker_ip_header_helper_unknown},
+	{126, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "126", ecm_tracker_ip_header_helper_unknown},
+	{127, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "127", ecm_tracker_ip_header_helper_unknown},
+	{128, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "128", ecm_tracker_ip_header_helper_unknown},
+	{129, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "129", ecm_tracker_ip_header_helper_unknown},
+	{130, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "130", ecm_tracker_ip_header_helper_unknown},
+	{131, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "131", ecm_tracker_ip_header_helper_unknown},
+	{132, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "132", ecm_tracker_ip_header_helper_unknown},
+	{133, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "133", ecm_tracker_ip_header_helper_unknown},
+	{134, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "134", ecm_tracker_ip_header_helper_unknown},
+	{135, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "135", ecm_tracker_ip_header_helper_unknown},
+	{136, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "136", ecm_tracker_ip_header_helper_unknown},
+	{137, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "137", ecm_tracker_ip_header_helper_unknown},
+	{138, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "138", ecm_tracker_ip_header_helper_unknown},
+	{139, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "139", ecm_tracker_ip_header_helper_unknown},
+	{140, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "140", ecm_tracker_ip_header_helper_unknown},
+	{141, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "141", ecm_tracker_ip_header_helper_unknown},
+	{142, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "142", ecm_tracker_ip_header_helper_unknown},
+	{143, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "143", ecm_tracker_ip_header_helper_unknown},
+	{144, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "144", ecm_tracker_ip_header_helper_unknown},
+	{145, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "145", ecm_tracker_ip_header_helper_unknown},
+	{146, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "146", ecm_tracker_ip_header_helper_unknown},
+	{147, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "147", ecm_tracker_ip_header_helper_unknown},
+	{148, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "148", ecm_tracker_ip_header_helper_unknown},
+	{149, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "149", ecm_tracker_ip_header_helper_unknown},
+	{150, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "150", ecm_tracker_ip_header_helper_unknown},
+	{151, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "151", ecm_tracker_ip_header_helper_unknown},
+	{152, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "152", ecm_tracker_ip_header_helper_unknown},
+	{153, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "153", ecm_tracker_ip_header_helper_unknown},
+	{154, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "154", ecm_tracker_ip_header_helper_unknown},
+	{155, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "155", ecm_tracker_ip_header_helper_unknown},
+	{156, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "156", ecm_tracker_ip_header_helper_unknown},
+	{157, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "157", ecm_tracker_ip_header_helper_unknown},
+	{158, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "158", ecm_tracker_ip_header_helper_unknown},
+	{159, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "159", ecm_tracker_ip_header_helper_unknown},
+	{160, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "160", ecm_tracker_ip_header_helper_unknown},
+	{161, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "161", ecm_tracker_ip_header_helper_unknown},
+	{162, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "162", ecm_tracker_ip_header_helper_unknown},
+	{163, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "163", ecm_tracker_ip_header_helper_unknown},
+	{164, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "164", ecm_tracker_ip_header_helper_unknown},
+	{165, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "165", ecm_tracker_ip_header_helper_unknown},
+	{166, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "166", ecm_tracker_ip_header_helper_unknown},
+	{167, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "167", ecm_tracker_ip_header_helper_unknown},
+	{168, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "168", ecm_tracker_ip_header_helper_unknown},
+	{169, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "169", ecm_tracker_ip_header_helper_unknown},
+	{170, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "170", ecm_tracker_ip_header_helper_unknown},
+	{171, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "171", ecm_tracker_ip_header_helper_unknown},
+	{172, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "172", ecm_tracker_ip_header_helper_unknown},
+	{173, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "173", ecm_tracker_ip_header_helper_unknown},
+	{174, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "174", ecm_tracker_ip_header_helper_unknown},
+	{175, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "175", ecm_tracker_ip_header_helper_unknown},
+	{176, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "176", ecm_tracker_ip_header_helper_unknown},
+	{177, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "177", ecm_tracker_ip_header_helper_unknown},
+	{178, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "178", ecm_tracker_ip_header_helper_unknown},
+	{179, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "179", ecm_tracker_ip_header_helper_unknown},
+	{180, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "180", ecm_tracker_ip_header_helper_unknown},
+	{181, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "181", ecm_tracker_ip_header_helper_unknown},
+	{182, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "182", ecm_tracker_ip_header_helper_unknown},
+	{183, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "183", ecm_tracker_ip_header_helper_unknown},
+	{184, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "184", ecm_tracker_ip_header_helper_unknown},
+	{185, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "185", ecm_tracker_ip_header_helper_unknown},
+	{186, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "186", ecm_tracker_ip_header_helper_unknown},
+	{187, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "187", ecm_tracker_ip_header_helper_unknown},
+	{188, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "188", ecm_tracker_ip_header_helper_unknown},
+	{189, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "189", ecm_tracker_ip_header_helper_unknown},
+	{190, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "190", ecm_tracker_ip_header_helper_unknown},
+	{191, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "191", ecm_tracker_ip_header_helper_unknown},
+	{192, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "192", ecm_tracker_ip_header_helper_unknown},
+	{193, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "193", ecm_tracker_ip_header_helper_unknown},
+	{194, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "194", ecm_tracker_ip_header_helper_unknown},
+	{195, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "195", ecm_tracker_ip_header_helper_unknown},
+	{196, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "196", ecm_tracker_ip_header_helper_unknown},
+	{197, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "197", ecm_tracker_ip_header_helper_unknown},
+	{198, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "198", ecm_tracker_ip_header_helper_unknown},
+	{199, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "199", ecm_tracker_ip_header_helper_unknown},
+	{200, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "200", ecm_tracker_ip_header_helper_unknown},
+	{201, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "201", ecm_tracker_ip_header_helper_unknown},
+	{202, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "202", ecm_tracker_ip_header_helper_unknown},
+	{203, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "203", ecm_tracker_ip_header_helper_unknown},
+	{204, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "204", ecm_tracker_ip_header_helper_unknown},
+	{205, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "205", ecm_tracker_ip_header_helper_unknown},
+	{206, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "206", ecm_tracker_ip_header_helper_unknown},
+	{207, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "207", ecm_tracker_ip_header_helper_unknown},
+	{208, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "208", ecm_tracker_ip_header_helper_unknown},
+	{209, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "209", ecm_tracker_ip_header_helper_unknown},
+	{210, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "210", ecm_tracker_ip_header_helper_unknown},
+	{211, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "211", ecm_tracker_ip_header_helper_unknown},
+	{212, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "212", ecm_tracker_ip_header_helper_unknown},
+	{213, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "213", ecm_tracker_ip_header_helper_unknown},
+	{214, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "214", ecm_tracker_ip_header_helper_unknown},
+	{215, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "215", ecm_tracker_ip_header_helper_unknown},
+	{216, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "216", ecm_tracker_ip_header_helper_unknown},
+	{217, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "217", ecm_tracker_ip_header_helper_unknown},
+	{218, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "218", ecm_tracker_ip_header_helper_unknown},
+	{219, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "219", ecm_tracker_ip_header_helper_unknown},
+	{220, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "220", ecm_tracker_ip_header_helper_unknown},
+	{221, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "221", ecm_tracker_ip_header_helper_unknown},
+	{222, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "222", ecm_tracker_ip_header_helper_unknown},
+	{223, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "223", ecm_tracker_ip_header_helper_unknown},
+	{224, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "224", ecm_tracker_ip_header_helper_unknown},
+	{225, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "225", ecm_tracker_ip_header_helper_unknown},
+	{226, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "226", ecm_tracker_ip_header_helper_unknown},
+	{227, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "227", ecm_tracker_ip_header_helper_unknown},
+	{228, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "228", ecm_tracker_ip_header_helper_unknown},
+	{229, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "229", ecm_tracker_ip_header_helper_unknown},
+	{230, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "230", ecm_tracker_ip_header_helper_unknown},
+	{231, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "231", ecm_tracker_ip_header_helper_unknown},
+	{232, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "232", ecm_tracker_ip_header_helper_unknown},
+	{233, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "233", ecm_tracker_ip_header_helper_unknown},
+	{234, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "234", ecm_tracker_ip_header_helper_unknown},
+	{235, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "235", ecm_tracker_ip_header_helper_unknown},
+	{236, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "236", ecm_tracker_ip_header_helper_unknown},
+	{237, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "237", ecm_tracker_ip_header_helper_unknown},
+	{238, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "238", ecm_tracker_ip_header_helper_unknown},
+	{239, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "239", ecm_tracker_ip_header_helper_unknown},
+	{240, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "240", ecm_tracker_ip_header_helper_unknown},
+	{241, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "241", ecm_tracker_ip_header_helper_unknown},
+	{242, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "242", ecm_tracker_ip_header_helper_unknown},
+	{243, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "243", ecm_tracker_ip_header_helper_unknown},
+	{244, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "244", ecm_tracker_ip_header_helper_unknown},
+	{245, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "245", ecm_tracker_ip_header_helper_unknown},
+	{246, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "246", ecm_tracker_ip_header_helper_unknown},
+	{247, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "247", ecm_tracker_ip_header_helper_unknown},
+	{248, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "248", ecm_tracker_ip_header_helper_unknown},
+	{249, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "249", ecm_tracker_ip_header_helper_unknown},
+	{250, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "250", ecm_tracker_ip_header_helper_unknown},
+	{251, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "251", ecm_tracker_ip_header_helper_unknown},
+	{252, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "252", ecm_tracker_ip_header_helper_unknown},
+	{253, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "253", ecm_tracker_ip_header_helper_unknown},
+	{254, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "254", ecm_tracker_ip_header_helper_unknown},
+	{255, ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN, "255", ecm_tracker_ip_header_helper_unknown}
+};
+
+static char *ecm_tracker_sender_state_strings[] = {
+	"Unknown",
+	"Establishing",
+	"Established",
+	"Closing",
+	"Closed",
+	"Fault"
+};
+
+static char *ecm_tracker_connection_state_strings[] = {
+	"Establishing",
+	"Established",
+	"Closing",
+	"Closed",
+	"Fault"
+};
+
+/*
+ * ecm_tracker_ip_check_header_and_read()
+ *	Check that we have a complete network-level IP header, check it and return true if so.
+ */
+bool ecm_tracker_ip_check_header_and_read(struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb)
+{
+	struct iphdr *v4_hdr = NULL;
+	uint16_t remain;
+#ifdef ECM_IPV6_ENABLE
+	struct ipv6hdr *v6_hdr = NULL;
+	int16_t this_header;
+	int16_t prev_header;
+	uint32_t offset;
+#endif
+
+	memset(ip_hdr, 0, sizeof(*ip_hdr));
+
+	ip_hdr->skb = skb;
+
+	/*
+	 * What version of IP header are we dealing with?
+	 */
+	v4_hdr = skb_header_pointer(skb, 0, sizeof(struct iphdr), &ip_hdr->h.v4_hdr);
+	if (v4_hdr && (v4_hdr->version == 4)) {
+		DEBUG_TRACE("%px: skb: %px is ipv4\n", ip_hdr, skb);
+		ip_hdr->is_v4 = true;
+		goto version_check_done;
+	}
+
+#ifdef ECM_IPV6_ENABLE
+	/*
+	 * Try V6
+	 */
+	DEBUG_TRACE("skb: %px contains no v4 header\n", skb);
+	v6_hdr = skb_header_pointer(skb, 0, sizeof(struct ipv6hdr), &ip_hdr->h.v6_hdr);
+	if (!v6_hdr || (v6_hdr->version != 6)) {
+		DEBUG_TRACE("skb: %px contains no v6 header\n", skb);
+		return false;
+	}
+	DEBUG_TRACE("%px: skb: %px is ipv6\n", ip_hdr, skb);
+	ip_hdr->is_v4 = false;
+#else
+	DEBUG_TRACE("skb: %px Other IP header versions unsupported\n", skb);
+	return false;
+#endif
+
+version_check_done:
+	if (ip_hdr->is_v4) {
+		uint8_t protocol;
+		int16_t next_unused;
+		ecm_tracker_ip_protocol_type_t ecm_ip_protocol;
+		struct ecm_tracker_ip_protocols *etip;
+		struct ecm_tracker_ip_protocol_header *etiph;
+
+		DEBUG_TRACE("%px: skb: %px ipv4\n", ip_hdr, skb);
+
+		/*
+		 * Process IPv4
+		 */
+		ECM_NIN4_ADDR_TO_IP_ADDR(ip_hdr->src_addr, v4_hdr->saddr);
+		ECM_NIN4_ADDR_TO_IP_ADDR(ip_hdr->dest_addr, v4_hdr->daddr);
+		ip_hdr->ip_header_length = v4_hdr->ihl;
+		ip_hdr->ip_header_length <<= 2;
+		if (ip_hdr->ip_header_length < 20) {
+			DEBUG_WARN("%px: v4 invalid ip hdr len %d\n", skb, ip_hdr->ip_header_length);
+			return false;
+		}
+		ip_hdr->total_length = ntohs(v4_hdr->tot_len);
+		if (skb->len < ip_hdr->total_length) {
+			DEBUG_WARN("%px: v4 invalid total len: %u skb len: %u\n", skb, ip_hdr->total_length, skb->len);
+			return false;
+		}
+		remain = ip_hdr->total_length - ip_hdr->ip_header_length;
+
+		/*
+		 * Fragmented?
+		 */
+		ip_hdr->fragmented = (ntohs(v4_hdr->frag_off) & 0x3fff)? true : false;
+
+		/*
+		 * DSCP value is the 6 most significant bits of tos field, so left shifting
+		 * the tos value by 2 gives the DSCP value.
+		 */
+		ip_hdr->dscp = v4_hdr->tos >> 2;
+
+		/*
+		 * DS field
+		 */
+		ip_hdr->ds = ipv4_get_dsfield(v4_hdr);
+
+		/*
+		 * TTL field
+		 */
+		ip_hdr->ttl = v4_hdr->ttl;
+
+		/*
+		 * Get the protocol and where the header info will be stored
+		 */
+		protocol = v4_hdr->protocol;
+		ip_hdr->protocol = (int)v4_hdr->protocol;
+		etip = &ecm_tracker_ip_protocols_known[protocol];	/* Get header helper */
+		ecm_ip_protocol = etip->ecm_ip_protocol;
+		etiph = &ip_hdr->headers[ecm_ip_protocol];		/* Get where the header detail is stored in ip_hdr->headers[] */
+
+		DEBUG_TRACE("%px: v4 skb: %px, len: %d, ip_header_length: %u, total_length: %u, remain: %u, fragmented: %04x, protocol: %u, ecm_ip_protocol: %d src_addr: "
+				ECM_IP_ADDR_DOT_FMT ", dest addr: " ECM_IP_ADDR_DOT_FMT "\n",
+				ip_hdr,
+				skb,
+				skb->len,
+				ip_hdr->ip_header_length,
+				ip_hdr->total_length,
+				remain,
+				ip_hdr->fragmented,
+				ip_hdr->protocol,
+				ecm_ip_protocol,
+				ECM_IP_ADDR_TO_DOT(ip_hdr->src_addr),
+				ECM_IP_ADDR_TO_DOT(ip_hdr->dest_addr));
+
+		/*
+		 * Populate protocol detail
+		 * IPv4 can only have one.
+		 */
+		if (!etip->header_helper(
+				etip,
+				etiph,
+				ip_hdr,
+				skb,
+				(uint8_t)ip_hdr->protocol,
+				ecm_ip_protocol,
+				ip_hdr->ip_header_length,
+				remain,
+				&next_unused)) {
+			DEBUG_WARN("%px: v4 header helper failed for: %u\n", skb, protocol);
+			return false;
+		}
+
+		return true;
+	}
+
+#ifndef ECM_IPV6_ENABLE
+	return false;
+#else
+	/*
+	 * IPv6
+	 */
+	ECM_NIN6_ADDR_TO_IP_ADDR(ip_hdr->src_addr, v6_hdr->saddr);
+	ECM_NIN6_ADDR_TO_IP_ADDR(ip_hdr->dest_addr, v6_hdr->daddr);
+	ip_hdr->ip_header_length = 40;
+	remain = ntohs(v6_hdr->payload_len);
+	ip_hdr->total_length = remain + 40;
+	if (skb->len < ip_hdr->total_length) {
+		DEBUG_WARN("%px: v6 invalid total len: %u skb len: %u\n", skb, ip_hdr->total_length, skb->len);
+		return false;
+	}
+
+	/*
+	 * In IPv6 header, the version-class-flow_label is organized as:
+	 * version: u8:4
+	 * priority: u8:4
+	 * flow_lbl[3]
+	 *
+	 * Version(31-28), CLASS(27-20), FLOW(19-0)
+	 *
+	 * The dscp value is the most 6 significant bit of traffic-class field. Its 4-bits
+	 * belong to the priority field of the IPv6 header, the other 2-bits belong to the
+	 * flow_lbl[0]. So, to calculate the dscp value, we need to right shift the priority by 2 and OR
+	 * it with flow_lbl[0]'s most 2 significant bits.
+	 *
+	 * ECM_TRACKER_IPV6_FLOW_LBL_PRIORITY_MASK 0xC0
+	 * ECM_TRACKER_IPV6_FLOW_LBL_PRIORITY_SHIFT 6
+	 * ECM_TRACKER_IPV6_PRIORITY_SHIFT 2
+	 */
+	ip_hdr->dscp = (v6_hdr->priority << ECM_TRACKER_IPV6_PRIORITY_SHIFT) |
+			((v6_hdr->flow_lbl[0] & ECM_TRACKER_IPV6_FLOW_LBL_PRIORITY_MASK) >> ECM_TRACKER_IPV6_FLOW_LBL_PRIORITY_SHIFT);
+
+	/*
+	 * DS field
+	 */
+	ip_hdr->ds = ipv6_get_dsfield(v6_hdr);
+
+	/*
+	 * hop_limit field
+	 */
+	ip_hdr->ttl = v6_hdr->hop_limit;
+
+	/*
+	 * Process headers until we run out of space, error, or we get the no next header marker for v6 (protocol 59).
+	 */
+	offset = 40;
+	this_header = (int16_t)v6_hdr->nexthdr;
+	prev_header = this_header;
+	while ((remain > 0) && (this_header >= 0) && (this_header != 59)) {
+		struct ecm_tracker_ip_protocols *etip;
+		struct ecm_tracker_ip_protocol_header *etiph;
+		ecm_tracker_ip_protocol_type_t ecm_ip_protocol;
+		int16_t next_header;
+
+		etip = &ecm_tracker_ip_protocols_known[this_header];	/* Get header helper */
+		ecm_ip_protocol = etip->ecm_ip_protocol;
+		etiph = &ip_hdr->headers[ecm_ip_protocol];		/* Get where the header detail is stored in ip_hdr->headers[] */
+
+		/*
+		 * If this IP header has already been seen then we abort
+		 */
+		if (etiph->size) {
+			DEBUG_WARN("v6 skb: %px, protocol: %d already seen at offset: %u, size: %u\n",
+					skb, this_header, etiph->offset, etiph->size);
+			return false;
+		}
+		if (!etip->header_helper(
+				etip,
+				etiph,
+				ip_hdr,
+				skb,
+				(uint8_t)this_header,
+				ecm_ip_protocol,
+				offset,
+				remain,
+				&next_header)) {
+			DEBUG_WARN("%px: v6 header helper failed for: %d\n", skb, this_header);
+			return false;
+		}
+
+		offset += etiph->size;
+		DEBUG_ASSERT(remain >= etiph->size, "v6 remain: %u goes negative after header size: %u", remain, etiph->size);
+		remain -= etiph->size;
+
+		prev_header = this_header;
+		this_header = next_header;
+	}
+
+	/*
+	 * Generally the last protocol seen is the upper layer protocol
+	 */
+	ip_hdr->protocol = (int)prev_header;
+
+	return true;
+#endif
+}
+EXPORT_SYMBOL(ecm_tracker_ip_check_header_and_read);
+
+#ifdef ECM_IPV6_ENABLE
+/*
+ * ecm_tracker_ip_header_helper_ipv6_generic()
+ *	Interpret a Generic IPv6 extension header
+ */
+static bool ecm_tracker_ip_header_helper_ipv6_generic(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr,
+						struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr)
+{
+	struct ipv6_gen_hdr {
+		uint8_t next_protocol;
+		uint8_t header_ext_len;
+	} gen_header_buffer;
+	struct ipv6_gen_hdr *gen_header;
+	uint16_t hdr_size;
+
+	/*
+	 * At least 8 bytes
+	 */
+	if (remain < 8) {
+		return false;
+	}
+
+	gen_header = skb_header_pointer(skb, offset, sizeof(struct ipv6_gen_hdr), &gen_header_buffer);
+	if (!gen_header) {
+		return false;
+	}
+	hdr_size = gen_header->header_ext_len;
+	hdr_size <<= 3;
+	hdr_size += 8;
+	if (remain < hdr_size) {
+		DEBUG_WARN("IPv6 extension: %px packet remain: %u too small for tcp header: %u\n", skb, remain, hdr_size);
+		return false;
+	}
+	if (unlikely(ip_hdr->total_length < (offset + hdr_size))) {
+		DEBUG_WARN("TCP packet %px too short (total_length: %u, require: %u)\n", skb, ip_hdr->total_length, offset + hdr_size);
+		return false;
+	}
+
+	etiph->protocol_number = protocol;
+	etiph->header_size = hdr_size;
+	etiph->size = hdr_size;
+	etiph->offset = offset;
+
+	*next_hdr = (int16_t)gen_header->next_protocol;
+	return true;
+}
+
+/*
+ * ecm_tracker_ip_header_helper_ipv6_fragment()
+ *	Interpret a Generic IPv6 fragment header
+ */
+static bool ecm_tracker_ip_header_helper_ipv6_fragment(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr,
+							struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr)
+{
+	struct ipv6_gen_hdr {
+		uint8_t next_protocol;
+		uint8_t reserved;
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+		__be16 frag_off;
+#endif
+	} gen_header_buffer;
+	struct ipv6_gen_hdr *gen_header;
+
+	/*
+	 * At least 8 bytes
+	 */
+	if (remain < 8) {
+		return false;
+	}
+
+	gen_header = skb_header_pointer(skb, offset, sizeof(struct ipv6_gen_hdr), &gen_header_buffer);
+	if (!gen_header) {
+		return false;
+	}
+	if (unlikely(ip_hdr->total_length < (offset + 8))) {
+		DEBUG_WARN("TCP packet %px too short (total_length: %u, require: %u)\n", skb, ip_hdr->total_length, offset + 8);
+		return false;
+	}
+
+	/*
+	 * The very presence of a fragmemt header says it's fragmented
+	 */
+	ip_hdr->fragmented = true;
+
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+	/*
+	 * In general, any IPv6 packet with fragment header is a fragment
+	 * packet.
+	 * But, packet with dummy fragment header is an exception to this case
+	 * and represent a complete IPv6 packet.
+	 * So, below is a check to identify the presence of dummy fragment
+	 * header, and if present, unset the fragment flag.
+	 */
+	if ((gen_header->frag_off & htons(IP6_OFFSET | IP6_MF)) == 0) {
+		DEBUG_TRACE("Pkt has dummy header\n");
+		ip_hdr->fragmented = false;
+	}
+#endif
+
+	etiph->protocol_number = protocol;
+	etiph->header_size = 8;
+	etiph->size = 8;
+	etiph->offset = offset;
+
+	*next_hdr = (int16_t)gen_header->next_protocol;
+	return true;
+}
+
+/*
+ * ecm_tracker_ip_header_helper_ah()
+ *	Interpret an Authentication Header
+ */
+static bool ecm_tracker_ip_header_helper_ah(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr,
+						struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr)
+{
+	struct ah_gen_hdr {
+		uint8_t next_protocol;
+		uint8_t header_len;
+	} gen_header_buffer;
+	struct ah_gen_hdr *gen_header;
+	uint16_t hdr_size;
+
+	/*
+	 * At least 8 bytes
+	 */
+	if (remain < 8) {
+		return false;
+	}
+
+	gen_header = skb_header_pointer(skb, offset, sizeof(struct ah_gen_hdr), &gen_header_buffer);
+	if (!gen_header) {
+		return false;
+	}
+
+	hdr_size = gen_header->header_len + 2;
+	hdr_size <<= 2;
+
+	if (!ip_hdr->is_v4) {
+		/*
+		 * hdr_size needs to be a multiple of 8 in a v6 frame
+		 */
+		if (hdr_size % 8) {
+			DEBUG_WARN("AH packet %px not multiple of 8 for v6 frame: %u\n", skb, hdr_size);
+			return false;
+		}
+	}
+
+	if (remain < hdr_size) {
+		DEBUG_WARN("AH packet %px too short (total_length: %u, require: %u)\n", skb, ip_hdr->total_length, offset + hdr_size);
+		return false;
+	}
+	if (unlikely(ip_hdr->total_length < (offset + hdr_size))) {
+		DEBUG_WARN("AH packet %px too short (total_length: %u, require: %u)\n", skb, ip_hdr->total_length, offset + hdr_size);
+		return false;
+	}
+
+	/*
+	 * What header follows this one?
+	 */
+	*next_hdr = gen_header->next_protocol;
+
+	etiph->protocol_number = protocol;
+	etiph->header_size = hdr_size;
+	etiph->size = hdr_size;
+	etiph->offset = offset;
+	return true;
+}
+
+/*
+ * ecm_tracker_ip_header_helper_ipv6_icmp()
+ *	Interpret a ICMP V6 header
+ */
+static bool ecm_tracker_ip_header_helper_ipv6_icmp(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr,
+						struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr)
+{
+	if (remain < 4) {
+		DEBUG_WARN("v6 icmp: %px too small: %u\n", skb, remain);
+		return false;
+	}
+
+	etiph->protocol_number = protocol;
+	etiph->header_size = 4;
+	etiph->size = remain;
+	etiph->offset = offset;
+
+	/*
+	 * There is no header following a V6 ICMP header
+	 */
+	*next_hdr = -1;
+	return true;
+}
+
+#endif
+
+/*
+ * ecm_tracker_ip_header_helper_tcp()
+ *	Interpret a TCP header
+ */
+static bool ecm_tracker_ip_header_helper_tcp(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr,
+						struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr)
+{
+	struct tcphdr tcp_header_buffer;
+	struct tcphdr *tcp_header;
+	uint16_t hdr_size;
+
+	DEBUG_ASSERT((protocol == IPPROTO_TCP) && (ecm_ip_protocol == ECM_TRACKER_IP_PROTOCOL_TYPE_TCP), "Bad protocol: %u or ecm_ip_protocol: %d", protocol, ecm_ip_protocol);
+
+	if (remain < 20) {
+		return false;
+	}
+
+	tcp_header = skb_header_pointer(skb, offset, sizeof(struct tcphdr), &tcp_header_buffer);
+	if (!tcp_header) {
+		return false;
+	}
+	hdr_size = tcp_header->doff;
+	hdr_size <<= 2;
+	if (hdr_size < 20) {
+		return false;
+	}
+	if (remain < hdr_size) {
+		DEBUG_WARN("TCP packet: %px packet remain: %u too small for tcp header: %u\n", skb, remain, hdr_size);
+		return false;
+	}
+	if (unlikely(ip_hdr->total_length < (offset + hdr_size))) {
+		DEBUG_WARN("TCP packet %px too short (total_length: %u, require: %u)\n", skb, ip_hdr->total_length, offset + hdr_size);
+		return false;
+	}
+
+	etiph->protocol_number = protocol;
+	etiph->header_size = hdr_size;
+	etiph->size = remain;
+	etiph->offset = offset;
+
+	/*
+	 * There is no header following a TCP header
+	 */
+	*next_hdr = -1;
+	return true;
+}
+
+/*
+ * ecm_tracker_ip_header_helper_gre()
+ *	Interpret a GRE header
+ */
+static bool ecm_tracker_ip_header_helper_gre(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr,
+						struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr)
+{
+	uint32_t gre_hdr_buffer;
+	uint32_t *gre_hdr_ptr;
+	uint32_t gre_hdr;
+	uint16_t hdr_size;
+
+	DEBUG_ASSERT((protocol == IPPROTO_GRE) && (ecm_ip_protocol == ECM_TRACKER_IP_PROTOCOL_TYPE_GRE), "Bad protocol: %u or ecm_ip_protocol: %d", protocol, ecm_ip_protocol);
+
+	if (remain < 4) {
+		return false;
+	}
+
+	gre_hdr_ptr = skb_header_pointer(skb, offset, sizeof(gre_hdr_buffer), &gre_hdr_buffer);
+	if (!gre_hdr_ptr) {
+		return false;
+	}
+	gre_hdr = ntohl(*gre_hdr_ptr);
+	hdr_size = 4;
+	if (gre_hdr & 0x80000000) {
+		/*
+		 * Checksum
+		 */
+		hdr_size += 4;
+	}
+	if (gre_hdr & 0x20000000) {
+		/*
+		 * Key
+		 */
+		hdr_size += 4;
+	}
+	if (gre_hdr & 0x10000000) {
+		/*
+		 * Sequence
+		 */
+		hdr_size += 4;
+	}
+	if (remain < hdr_size) {
+		DEBUG_WARN("GRE packet: %px packet remain: %u too small for tcp header: %u\n", skb, remain, hdr_size);
+		return false;
+	}
+	if (unlikely(ip_hdr->total_length < (offset + hdr_size))) {
+		DEBUG_WARN("GRE packet %px too short (total_length: %u, require: %u)\n", skb, ip_hdr->total_length, offset + hdr_size);
+		return false;
+	}
+
+	etiph->protocol_number = protocol;
+	etiph->header_size = hdr_size;
+	etiph->size = remain;
+	etiph->offset = offset;
+
+	/*
+	 * There is no header following a GRE header
+	 */
+	*next_hdr = -1;
+	return true;
+}
+
+/*
+ * ecm_tracker_ip_header_helper_udp()
+ *	Interpret a UDP header
+ */
+static bool ecm_tracker_ip_header_helper_udp(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr,
+						struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr)
+{
+	DEBUG_ASSERT((protocol == IPPROTO_UDP) && (ecm_ip_protocol == ECM_TRACKER_IP_PROTOCOL_TYPE_UDP), "Bad protocol: %u or ecm_ip_protocol: %d", protocol, ecm_ip_protocol);
+
+	DEBUG_TRACE("udp helper skb: %px, protocol: %u, ecm_ip_proto: %d, offset: %u, remain: %u\n", skb, protocol, ecm_ip_protocol, offset, remain);
+	if (remain < 8) {
+		DEBUG_TRACE("not enough UDP header: %u\n", remain);
+		return false;
+	}
+
+	etiph->protocol_number = protocol;
+	etiph->header_size = 8;
+	etiph->size = remain;
+	etiph->offset = offset;
+
+	/*
+	 * There is no header following a UDP header
+	 */
+	*next_hdr = -1;
+	return true;
+}
+
+/*
+ * ecm_tracker_ip_header_helper_unknown()
+ *	Interpret a unknown header
+ */
+static bool ecm_tracker_ip_header_helper_unknown(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr,
+							struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr)
+{
+	/*
+	 * There is no header following an unknown header
+	 */
+	*next_hdr = -1;
+	etiph->protocol_number = protocol;
+	etiph->header_size = remain;
+	etiph->size = remain;
+	etiph->offset = offset;
+	return true;
+}
+
+/*
+ * ecm_tracker_ip_header_helper_icmp()
+ *	Interpret a ICMP V4 header
+ */
+static bool ecm_tracker_ip_header_helper_icmp(struct ecm_tracker_ip_protocols *etip, struct ecm_tracker_ip_protocol_header *etiph, struct ecm_tracker_ip_header *ip_hdr,
+						struct sk_buff *skb, uint8_t protocol, ecm_tracker_ip_protocol_type_t ecm_ip_protocol, uint32_t offset, uint32_t remain, int16_t *next_hdr)
+{
+	struct icmphdr icmp_header_buffer;
+	struct icmphdr *icmp_header;
+
+	DEBUG_ASSERT((protocol == IPPROTO_ICMP) && (ecm_ip_protocol == ECM_TRACKER_IP_PROTOCOL_TYPE_ICMP), "Bad protocol: %u or ecm_ip_protocol: %d", protocol, ecm_ip_protocol);
+
+	if (remain < 8) {
+		return false;
+	}
+
+	icmp_header = skb_header_pointer(skb, offset, sizeof(struct icmphdr), &icmp_header_buffer);
+	if (!icmp_header) {
+		return false;
+	}
+	switch(icmp_header->type) {
+	case ICMP_SOURCE_QUENCH:
+	case ICMP_REDIRECT:
+	case ICMP_TIME_EXCEEDED:
+	case ICMP_DEST_UNREACH:
+		/*
+		 * Should be at least our 8 bytes and minimum 20 bytes for an IP header.
+		 * NOTE: We are not looking at options that extend this header!
+		 */
+		if (remain < 28) {
+			DEBUG_WARN("icmp skb: %px type: %u too small: %u\n", skb, icmp_header->type, remain);
+			return false;
+		}
+		etiph->header_size = 8;
+		etiph->size = remain;
+		break;
+
+	case ICMP_ADDRESS:
+	case ICMP_ADDRESSREPLY:
+	case ICMP_TIMESTAMP:
+		if (remain < 12) {
+			DEBUG_WARN("icmp skb: %px type: %u too small: %u\n", skb, icmp_header->type, remain);
+			return false;
+		}
+		etiph->header_size = 12;
+		etiph->size = remain;
+		break;
+	case ICMP_TIMESTAMPREPLY:
+		if (remain < 20) {
+			DEBUG_WARN("icmp skb: %px type: %u too small: %u\n", skb, icmp_header->type, remain);
+			return false;
+		}
+		etiph->header_size = 20;
+		etiph->size = remain;
+		break;
+	case ICMP_PARAMETERPROB:
+	case ICMP_INFO_REQUEST:
+	case ICMP_INFO_REPLY:
+	default:
+		etiph->header_size = 8;
+		etiph->size = remain;
+	}
+	etiph->protocol_number = protocol;
+	etiph->offset = offset;
+
+	/*
+	 * There is no header following a ICMP header
+	 */
+	*next_hdr = -1;
+	return true;
+}
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+/*
+ * ecm_tracker_data_limit_set()
+ *	Set global tracked data limit
+ */
+void ecm_tracker_data_limit_set(uint32_t limit)
+{
+	int data_limit = (int)limit;
+	DEBUG_ASSERT(data_limit > 0, "Invalid limit %d\n", data_limit);
+	spin_lock_bh(&ecm_tracker_lock);
+	ecm_tracker_data_limit = data_limit;
+	spin_unlock_bh(&ecm_tracker_lock);
+}
+EXPORT_SYMBOL(ecm_tracker_data_limit_set);
+
+/*
+ * ecm_tracker_data_limit_get()
+ *	Return global tracked data limit
+ */
+uint32_t ecm_tracker_data_limit_get(void)
+{
+	uint32_t data_total;
+	spin_lock_bh(&ecm_tracker_lock);
+	data_total = (uint32_t)ecm_tracker_data_limit;
+	spin_unlock_bh(&ecm_tracker_lock);
+	return data_total;
+}
+EXPORT_SYMBOL(ecm_tracker_data_limit_get);
+
+/*
+ * ecm_tracker_data_total_get()
+ *	Return global tracked data quantity
+ */
+uint32_t ecm_tracker_data_total_get(void)
+{
+	uint32_t data_total;
+	spin_lock_bh(&ecm_tracker_lock);
+	data_total = (uint32_t)ecm_tracker_data_total;
+	spin_unlock_bh(&ecm_tracker_lock);
+	return data_total;
+}
+EXPORT_SYMBOL(ecm_tracker_data_total_get);
+
+/*
+ * ecm_tracker_data_buffer_total_get()
+ *	Return global tracked data buffer size
+ */
+uint32_t ecm_tracker_data_buffer_total_get(void)
+{
+	uint32_t data_buffer_total;
+	spin_lock_bh(&ecm_tracker_lock);
+	data_buffer_total = (uint32_t)ecm_tracker_data_buffer_total;
+	spin_unlock_bh(&ecm_tracker_lock);
+	return data_buffer_total;
+}
+EXPORT_SYMBOL(ecm_tracker_data_buffer_total_get);
+
+/*
+ * ecm_tracker_data_total_increase()
+ *	Increase global tracked data quantity
+ *
+ * If this function returns false then the increase has been denied and tracking of that data should not occur.
+ * Therefore call this function BEFORE tracking the actual data.
+ */
+bool ecm_tracker_data_total_increase(uint32_t n, uint32_t data_buffer_size)
+{
+	spin_lock_bh(&ecm_tracker_lock);
+
+	/*
+	 * Would we exceed our global limit?
+	 */
+	DEBUG_ASSERT((ecm_tracker_data_total + (int)n) > 0, "bad total\n");
+	if (((ecm_tracker_data_buffer_total + data_buffer_size)  > ecm_tracker_data_buffer_limit)
+			|| ((ecm_tracker_data_total + n) > ecm_tracker_data_limit)) {
+		spin_unlock_bh(&ecm_tracker_lock);
+		return false;
+	}
+	ecm_tracker_data_buffer_total += data_buffer_size;
+	ecm_tracker_data_total += (int)n;
+	spin_unlock_bh(&ecm_tracker_lock);
+	return true;
+}
+EXPORT_SYMBOL(ecm_tracker_data_total_increase);
+
+/*
+ * ecm_tracker_data_total_decrease()
+ *	Decrease global tracked data quantity
+ */
+void ecm_tracker_data_total_decrease(uint32_t n, uint32_t data_buffer_size)
+{
+	spin_lock_bh(&ecm_tracker_lock);
+	ecm_tracker_data_total -= (int)n;
+	ecm_tracker_data_buffer_total -= data_buffer_size;
+	DEBUG_ASSERT(ecm_tracker_data_total >= 0, "bad total\n");
+	DEBUG_ASSERT(ecm_tracker_data_buffer_total >= 0, "bad total\n");
+	spin_unlock_bh(&ecm_tracker_lock);
+}
+EXPORT_SYMBOL(ecm_tracker_data_total_decrease);
+#endif
+
+/*
+ * ecm_tracker_module_get()
+ *	Take a reference to the module
+ */
+void ecm_tracker_module_get(void)
+{
+	try_module_get(THIS_MODULE);
+}
+EXPORT_SYMBOL(ecm_tracker_module_get);
+
+/*
+ * ecm_tracker_module_put()
+ *	Release a reference to the module
+ */
+void ecm_tracker_module_put(void)
+{
+	module_put(THIS_MODULE);
+}
+EXPORT_SYMBOL(ecm_tracker_module_put);
+
+/*
+ * ecm_tracker_sender_state_to_string()
+ *	Convert a sender state to a string equivalent
+ */
+const char *ecm_tracker_sender_state_to_string(enum ecm_tracker_sender_states s)
+{
+	return ecm_tracker_sender_state_strings[s];
+}
+EXPORT_SYMBOL(ecm_tracker_sender_state_to_string);
+
+/*
+ * ecm_tracker_connection_state_to_string()
+ *	Convert a connection state to its string equivalent
+ */
+const char *ecm_tracker_connection_state_to_string(enum ecm_tracker_connection_states s)
+{
+	return ecm_tracker_connection_state_strings[s];
+}
+EXPORT_SYMBOL(ecm_tracker_connection_state_to_string);
diff --git a/qca-nss-ecm/ecm_tracker.h b/qca-nss-ecm/ecm_tracker.h
new file mode 100644
index 0000000..9293d6e
--- /dev/null
+++ b/qca-nss-ecm/ecm_tracker.h
@@ -0,0 +1,234 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+struct ecm_tracker_instance;
+
+/*
+ * Data tracking data limits - system global and per-connection - defaults.
+ */
+#define ECM_TRACKER_GLOBAL_DATA_LIMIT_DEFAULT (1024 * 1024 * 8)
+#define ECM_TRACKER_GLOBAL_DATA_BUFFER_LIMIT_DEFAULT (1024 * 1024 * 64)
+#define ECM_TRACKER_CONNECTION_TRACKING_LIMIT_DEFAULT (1024 * 1024)
+#define ECM_TRACKER_CONNECTION_TRACKING_LIMIT_MAX ECM_TRACKER_GLOBAL_DATA_LIMIT_DEFAULT
+
+/*
+ * Definitions for IPv6 version-class-flow_label field.
+ */
+#define ECM_TRACKER_IPV6_FLOW_LBL_PRIORITY_MASK 0xC0
+#define ECM_TRACKER_IPV6_FLOW_LBL_PRIORITY_SHIFT 6
+#define ECM_TRACKER_IPV6_PRIORITY_SHIFT 2
+
+enum ecm_tracker_sender_types {
+	ECM_TRACKER_SENDER_TYPE_SRC = 0,		/* Sender of tracked data is the source of the connection (who established the connection) */
+	ECM_TRACKER_SENDER_TYPE_DEST = 1,	/* Sender of tracked data is the destination of the connection (to whom connection was established) */
+	ECM_TRACKER_SENDER_MAX,			/* MUST BE LAST */
+};
+typedef enum ecm_tracker_sender_types ecm_tracker_sender_type_t;
+
+/*
+ * enum ecm_tracker_sender_states
+ *	Notional states of senders of a tracker
+ *
+ * Order is important here - don't change them as logic depends on their numerical value.
+ */
+enum ecm_tracker_sender_states {
+	ECM_TRACKER_SENDER_STATE_UNKNOWN = 0,		/* Endpoint has not sent any packets yet */
+	ECM_TRACKER_SENDER_STATE_ESTABLISHING,		/* Endpoint has not yet given any indication it is established */
+	ECM_TRACKER_SENDER_STATE_ESTABLISHED,		/* Endpoint has indicated that it is established */
+	ECM_TRACKER_SENDER_STATE_CLOSING,		/* Endpoint has indicated that it wants to close down its side of the connection */
+	ECM_TRACKER_SENDER_STATE_CLOSED,		/* Endpoint has closed, connection remains to service any late packets */
+	ECM_TRACKER_SENDER_STATE_FAULT,			/* Endpoint experienced a fault */
+	ECM_TRACKER_SENDER_STATE_MAX,			/* MUST BE LAST */
+};
+typedef enum ecm_tracker_sender_states ecm_tracker_sender_state_t;
+
+/*
+ * ecm_tracker_sender_state_to_string[]
+ *	Convert a sender state to a string
+ */
+const char *
+ecm_tracker_sender_state_to_string(enum ecm_tracker_sender_states);
+
+/*
+ * enum ecm_tracker_connection_states
+ *	Notional states of connection being monitored by the tracker
+ *
+ * Order is important here - don't change them as logic depends on their numerical value.
+ */
+enum ecm_tracker_connection_states {
+	ECM_TRACKER_CONNECTION_STATE_ESTABLISHING = 0,	/* Not yet given any indication it is established */
+	ECM_TRACKER_CONNECTION_STATE_ESTABLISHED,	/* It is established */
+	ECM_TRACKER_CONNECTION_STATE_CLOSING,		/* Connection has begun process of closing */
+	ECM_TRACKER_CONNECTION_STATE_CLOSED,		/* Has closed, connection remains to service any late packets */
+	ECM_TRACKER_CONNECTION_STATE_FAULT,		/* Experienced a fault */
+	ECM_TRACKER_CONNECTION_STATE_MAX,		/* MUST BE LAST */
+};
+typedef enum ecm_tracker_connection_states ecm_tracker_connection_state_t;
+
+/*
+ * ecm_tracker_connection_state_to_string
+ *	Convert a connection state to a string
+ */
+const char *ecm_tracker_connection_state_to_string(enum ecm_tracker_connection_states);
+
+/*
+ * enum ecm_tracker_ip_protocol_types
+ *	A list of protocol types that can be recorded in the ecm_ip_header
+ *
+ * This is especially useful for IPv6 where the ip header can contain many sub headers.
+ * But it is also useful for IPv4 where you might have IP following a GRE header, for example.
+ * An ECM IP header may record only ONE of each type of header, if more are found the header is considered invalid.
+ *
+ * These constants are used to index into the ecm_tracker_ip_header.headers[]
+ */
+enum ecm_tracker_ip_protocol_types {
+	ECM_TRACKER_IP_PROTOCOL_TYPE_UNKNOWN,		/* A protocol that is unrecognised */
+	ECM_TRACKER_IP_PROTOCOL_TYPE_ICMP,
+	ECM_TRACKER_IP_PROTOCOL_TYPE_UDP,
+	ECM_TRACKER_IP_PROTOCOL_TYPE_TCP,
+	ECM_TRACKER_IP_PROTOCOL_TYPE_GRE,
+#ifdef ECM_IPV6_ENABLE
+	ECM_TRACKER_IP_PROTOCOL_TYPE_IPV6_ROUTING,
+	ECM_TRACKER_IP_PROTOCOL_TYPE_IPV6_FRAGMENT,
+	ECM_TRACKER_IP_PROTOCOL_TYPE_AH,
+	ECM_TRACKER_IP_PROTOCOL_TYPE_IPV6_ICMP,
+	ECM_TRACKER_IP_PROTOCOL_TYPE_IPV6_DO,
+	ECM_TRACKER_IP_PROTOCOL_TYPE_IPV6_HBH,		/* IPv6 hop-by-hop header */
+#endif
+	ECM_TRACKER_IP_PROTOCOL_TYPE_COUNT		/* Must be last, do not use */
+};
+typedef enum ecm_tracker_ip_protocol_types ecm_tracker_ip_protocol_type_t;
+
+/*
+ * struct ecm_tracker_ip_protocol_header
+ *	Records a protocol header as stored within an IP datagram
+ */
+struct ecm_tracker_ip_protocol_header {
+	uint8_t protocol_number;		/* IP protocol number */
+	uint16_t header_size;			/* Size of the protocol header */
+	uint16_t size;				/* Size of the header_size + its payload */
+	uint16_t offset;			/* Offset from the start of the skb where this header is located */
+};
+
+/*
+ * struct ecm_tracker_ip_header
+ *	An IP header in the ECM can deal with V4 and V6 headers.
+ *
+ * WARNING: An ecm_ip_header is ONLY VALID while the skb from which it was initialised remains untouched.
+ */
+struct ecm_tracker_ip_header {
+	/*
+	 * h is a union of IP version headers.
+	 * These are ONLY used as buffers where skb_header_pointer() needs them to perform a skb_copy_bits() operation.
+	 * WARNING: You should NOT rely on the content of these structures because skb_header_pointer() may not have used them!
+	 * Use the actual fields below instead.
+	 */
+	union {
+		struct iphdr v4_hdr;
+#ifdef ECM_IPV6_ENABLE
+		struct ipv6hdr v6_hdr;
+#endif
+	} h;
+
+	struct sk_buff *skb;		/* COPY of POINTER to the skb this header relates to.  This ecm_tracker_ip_header is ONLY VALID for as long as the skb it relates to remains UNTOUCHED */
+	bool is_v4;			/* True when v4, else v6 */
+	ip_addr_t src_addr;		/* ECM ip address equivalent */
+	ip_addr_t dest_addr;		/* ECM ip address equivalent */
+	int protocol;			/* The upper layer transport protocol */
+	bool fragmented;		/* True when fragmented */
+	uint8_t dscp;			/* DSCP field from the packet */
+	uint8_t ds;			/* DS field from packet */
+	uint8_t ttl;			/* v4 TTL or v6 hop limit */
+	uint32_t ip_header_length;	/* Length of the IP header plus any variable sized intrinsically attached options */
+	uint32_t total_length;		/* total length of IP header including all extensions and payload.  For v4 this is total_len, for v6 this is payload_len + size of the IP 6 header */
+	uint32_t payload_length;	/* total_length - ip_header_length */
+	struct ecm_tracker_ip_protocol_header headers[ECM_TRACKER_IP_PROTOCOL_TYPE_COUNT];
+					/* Use one of the ECM_TRACKER_IP_PROTOCOL_TYPE_XYZ constants to index into this to locate the header you want to inspect.  If the size is zero then the header was not found. */
+};
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+typedef int32_t (*ecm_tracker_datagram_count_get_method_t)(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender);
+													/* Return number of available datagrams sent by the sender */
+typedef void (*ecm_tracker_datagram_discard_method_t)(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, int32_t n);
+													/* Discard n number of datagrams at the head of the datagram list that were sent by the sender */
+typedef int32_t (*ecm_tracker_datagram_size_get_method_t)(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, int32_t i);
+													/* Return size in bytes of datagram at index i that was sent by the sender  */
+typedef int (*ecm_tracker_datagram_read_method_t)(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, int32_t i, int32_t offset, int32_t size, void *buffer);
+													/* Read size bytes from datagram at index i into the buffer */
+typedef bool (*ecm_tracker_datagram_add_method_t)(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, struct sk_buff *skb);
+													/* Add (append) the datagram into the tracker */
+typedef void (*ecm_tracker_discard_all_method_t)(struct ecm_tracker_instance *ti);
+													/* Discard all tracked data */
+typedef int32_t (*ecm_tracker_data_total_get_method_t)(struct ecm_tracker_instance *ti);
+													/* Return number of bytes of tracked data in total */
+typedef int32_t (*ecm_tracker_data_limit_get_method_t)(struct ecm_tracker_instance *ti);
+													/* Return the limit on the number of bytes we can track */
+typedef void (*ecm_tracker_data_limit_set_method_t)(struct ecm_tracker_instance *ti, int32_t data_limit);
+													/* Set the limit on the number of bytes we can track */
+#endif
+typedef void (*ecm_tracker_ref_method_t)(struct ecm_tracker_instance *ti);
+typedef int (*ecm_tracker_deref_method_t)(struct ecm_tracker_instance *ti);
+
+typedef void (*ecm_tracker_state_update_method_t)(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb);
+													/* Update state of the sender */
+typedef void (*ecm_tracker_state_get_method_t)(struct ecm_tracker_instance *ti, ecm_tracker_sender_state_t *src_state, ecm_tracker_sender_state_t *dest_state, ecm_tracker_connection_state_t *state, ecm_db_timer_group_t *tg);
+													/* State of the connection */
+#ifdef ECM_STATE_OUTPUT_ENABLE
+typedef int (*ecm_tracker_state_get_callback_t)(struct ecm_tracker_instance *ti, struct ecm_state_file_instance *sfi);
+											/*
+											 * Get state output.
+											 * Returns zero on success.
+											 */
+#endif
+
+/*
+ * struct ecm_tracker_instance
+ *	Base class of all trackers
+ *
+ * ALL trackers must implement these features in addition to their own.
+ * ALL trackers must be castable to a type of this, i.e. this structure must be the first element of their own data type.
+ */
+struct ecm_tracker_instance {
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	ecm_tracker_data_total_get_method_t data_total_get;
+	ecm_tracker_data_limit_get_method_t data_limit_get;
+	ecm_tracker_data_limit_set_method_t data_limit_set;
+	ecm_tracker_datagram_count_get_method_t datagram_count_get;
+	ecm_tracker_datagram_discard_method_t datagram_discard;
+	ecm_tracker_datagram_size_get_method_t datagram_size_get;
+	ecm_tracker_datagram_read_method_t datagram_read;
+	ecm_tracker_datagram_add_method_t datagram_add;
+	ecm_tracker_discard_all_method_t discard_all;
+#endif
+	ecm_tracker_state_update_method_t state_update;
+	ecm_tracker_state_get_method_t state_get;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ecm_tracker_state_get_callback_t state_text_get;		/* Return text containing its state */
+#endif
+	ecm_tracker_ref_method_t ref;
+	ecm_tracker_deref_method_t deref;
+};
+
+bool ecm_tracker_ip_check_header_and_read(struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb);
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+uint32_t ecm_tracker_data_limit_get(void);
+void ecm_tracker_data_limit_set(uint32_t limit);
+uint32_t ecm_tracker_data_total_get(void);
+uint32_t ecm_tracker_data_buffer_total_get(void);
+bool ecm_tracker_data_total_increase(uint32_t n, uint32_t data_bufer_size);
+void ecm_tracker_data_total_decrease(uint32_t n, uint32_t data_bufer_size);
+#endif
+
diff --git a/qca-nss-ecm/ecm_tracker_datagram.c b/qca-nss-ecm/ecm_tracker_datagram.c
new file mode 100644
index 0000000..9c04d73
--- /dev/null
+++ b/qca-nss-ecm/ecm_tracker_datagram.c
@@ -0,0 +1,784 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/sysctl.h>
+#include <linux/kthread.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_TRACKER_DATAGRAM_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_tracker_datagram.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC 0x3AbC
+
+/*
+ * struct ecm_tracker_datagram_internal_instance
+ */
+struct ecm_tracker_datagram_internal_instance {
+	struct ecm_tracker_datagram_instance datagram_base;	/* MUST BE FIRST FIELD */
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	/*
+	 * skb-next and skb->prev pointers are leveraged for these lists
+	 */
+	struct sk_buff *src_recvd_order;	/* sk buff list as sent by src */
+	struct sk_buff *src_recvd_order_last;	/* Last skb send - for fast appending of new buffers */
+	int32_t src_count;			/* Count of datagrams in list */
+	int32_t src_bytes_total;		/* Total bytes in all received datagrams */
+
+	struct sk_buff *dest_recvd_order;	/* sk buff list as sent by dest */
+	struct sk_buff *dest_recvd_order_last;	/* Last skb send - for fast appending of new buffers */
+	int32_t dest_count;			/* Count of datagrams in list */
+	int32_t dest_bytes_total;		/* Total bytes in all received datagrams */
+
+	int32_t data_limit;			/* Limit for tracked data */
+#endif
+
+	ecm_tracker_sender_state_t sender_state[ECM_TRACKER_SENDER_MAX];
+						/* State of each sender */
+
+	spinlock_t lock;			/* lock */
+
+	int refs;				/* Integer to trap we never go negative */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+int ecm_tracker_datagram_count = 0;		/* Counts the number of DATAGRAM data trackers right now */
+static DEFINE_SPINLOCK(ecm_tracker_datagram_lock);		/* Global lock for the tracker globals */
+
+/*
+ * ecm_trracker_datagram_connection_state_matrix[][]
+ *	Matrix to convert from/to states to connection state
+ */
+static ecm_tracker_connection_state_t ecm_tracker_datagram_connection_state_matrix[ECM_TRACKER_SENDER_STATE_MAX][ECM_TRACKER_SENDER_STATE_MAX] =
+{	/* 			Unknown						Establishing					Established					Closing					Closed					Fault */
+	/* Unknown */		{ECM_TRACKER_CONNECTION_STATE_ESTABLISHING,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHING,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHED,	ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT},
+	/* Establishing */	{ECM_TRACKER_CONNECTION_STATE_ESTABLISHING,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHING,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHED,	ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT},
+	/* Established */	{ECM_TRACKER_CONNECTION_STATE_ESTABLISHED,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHED,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHED,	ECM_TRACKER_CONNECTION_STATE_CLOSING,	ECM_TRACKER_CONNECTION_STATE_CLOSING,	ECM_TRACKER_CONNECTION_STATE_FAULT},
+	/* Closing */		{ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_CLOSING,		ECM_TRACKER_CONNECTION_STATE_CLOSING,	ECM_TRACKER_CONNECTION_STATE_CLOSING,	ECM_TRACKER_CONNECTION_STATE_FAULT},
+	/* Closed */		{ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_CLOSING,		ECM_TRACKER_CONNECTION_STATE_CLOSING,	ECM_TRACKER_CONNECTION_STATE_CLOSED, 	ECM_TRACKER_CONNECTION_STATE_FAULT},
+	/* Fault */		{ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT},
+};
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+/*
+ * ecm_tracker_datagram_datagram_discard()
+ *	Discard n number of datagrams at the head of the datagram list that were sent to the target
+ */
+static void ecm_tracker_datagram_datagram_discard(struct ecm_tracker_datagram_internal_instance *dtii, ecm_tracker_sender_type_t sender, int32_t n)
+{
+	DEBUG_CHECK_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC, "%px: magic failed", dtii);
+
+	DEBUG_TRACE("%px: discard %u datagrams for %d\n", dtii, n, sender);
+
+	/*
+	 * Which list?
+	 */
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		/*
+		 * iterate n times and discard the buffers
+		 */
+		while (n) {
+			struct sk_buff *skb;
+
+			spin_lock_bh(&dtii->lock);
+
+			skb = dtii->src_recvd_order;
+			DEBUG_ASSERT(skb, "%px: bad list\n", dtii);
+
+			dtii->src_recvd_order = skb->next;
+			if (!dtii->src_recvd_order) {
+				DEBUG_ASSERT(dtii->src_recvd_order_last == skb, "%px: bad list\n", dtii);
+				dtii->src_recvd_order_last = NULL;
+			} else {
+				dtii->src_recvd_order->prev = NULL;
+			}
+
+			dtii->src_count--;
+			DEBUG_ASSERT(dtii->src_count >= 0, "%px: bad total\n", dtii);
+			dtii->src_bytes_total -= skb->truesize;
+			ecm_tracker_data_total_decrease(skb->len, skb->truesize);
+			DEBUG_ASSERT(dtii->src_bytes_total >= 0, "%px: bad bytes total\n", dtii);
+
+			spin_unlock_bh(&dtii->lock);
+			kfree_skb(skb);
+
+			n--;
+		}
+		return;
+	}
+
+	/*
+	 * iterate n times and discard the buffers
+	 */
+	while (n) {
+		struct sk_buff *skb;
+
+		spin_lock_bh(&dtii->lock);
+
+		skb = dtii->dest_recvd_order;
+		DEBUG_ASSERT(skb, "%px: bad list\n", dtii);
+
+		dtii->dest_recvd_order = skb->next;
+		if (!dtii->dest_recvd_order) {
+			DEBUG_ASSERT(dtii->dest_recvd_order_last == skb, "%px: bad list\n", dtii);
+			dtii->dest_recvd_order_last = NULL;
+		} else {
+			dtii->dest_recvd_order->prev = NULL;
+		}
+
+		dtii->dest_count--;
+		DEBUG_ASSERT(dtii->dest_count >= 0, "%px: bad total\n", dtii);
+		dtii->dest_bytes_total -= skb->truesize;
+		ecm_tracker_data_total_decrease(skb->len, skb->truesize);
+		DEBUG_ASSERT(dtii->dest_bytes_total >= 0, "%px: bad bytes total\n", dtii);
+
+		spin_unlock_bh(&dtii->lock);
+		kfree_skb(skb);
+
+		n--;
+	}
+}
+
+/*
+ * ecm_tracker_datagram_discard_all()
+ *	Discard all tracked data
+ */
+static void ecm_tracker_datagram_discard_all(struct ecm_tracker_datagram_internal_instance *dtii)
+{
+	int32_t src_count;
+	int32_t dest_count;
+	DEBUG_CHECK_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC, "%px: magic failed", dtii);
+
+	spin_lock_bh(&dtii->lock);
+	src_count = dtii->src_count;
+	dest_count = dtii->dest_count;
+	spin_unlock_bh(&dtii->lock);
+
+	/*
+	 * Destroy all datagrams
+	 */
+	DEBUG_TRACE("%px: destroy all (src count: %d, dest_count: %d)\n", dtii, src_count, dest_count);
+	ecm_tracker_datagram_datagram_discard(dtii, ECM_TRACKER_SENDER_TYPE_SRC, src_count);
+	ecm_tracker_datagram_datagram_discard(dtii, ECM_TRACKER_SENDER_TYPE_DEST, dest_count);
+}
+EXPORT_SYMBOL(ecm_tracker_datagram_discard_all);
+
+/*
+ * ecm_tracker_datagram_discard_all_callback()
+ *	Discard all tracked data
+ */
+static void ecm_tracker_datagram_discard_all_callback(struct ecm_tracker_instance *ti)
+{
+	struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)ti;
+	ecm_tracker_datagram_discard_all(dtii);
+}
+#endif
+
+/*
+ * ecm_tracker_datagram_ref()
+ */
+static void ecm_tracker_datagram_ref(struct ecm_tracker_datagram_internal_instance *dtii)
+{
+
+	DEBUG_CHECK_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC, "%px: magic failed", dtii);
+
+	spin_lock_bh(&dtii->lock);
+
+	dtii->refs++;
+	DEBUG_ASSERT(dtii->refs > 0, "%px: ref wrap", dtii);
+	DEBUG_TRACE("%px: ref %d\n", dtii, dtii->refs);
+
+	spin_unlock_bh(&dtii->lock);
+}
+
+/*
+ * ecm_tracker_datagram_ref_callback()
+ */
+static void ecm_tracker_datagram_ref_callback(struct ecm_tracker_instance *ti)
+{
+	struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)ti;
+	ecm_tracker_datagram_ref(dtii);
+}
+
+/*
+ * ecm_tracker_datagram_deref()
+ */
+static int ecm_tracker_datagram_deref(struct ecm_tracker_datagram_internal_instance *dtii)
+{
+
+	int refs;
+	DEBUG_CHECK_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC, "%px: magic failed", dtii);
+
+	spin_lock_bh(&dtii->lock);
+	dtii->refs--;
+	refs = dtii->refs;
+	DEBUG_ASSERT(dtii->refs >= 0, "%px: ref wrap", dtii);
+	DEBUG_TRACE("%px: deref %d\n", dtii, dtii->refs);
+
+	if (dtii->refs > 0) {
+		spin_unlock_bh(&dtii->lock);
+		return refs;
+	}
+	spin_unlock_bh(&dtii->lock);
+
+	DEBUG_TRACE("%px: final\n", dtii);
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	/*
+	 * Destroy all datagrams
+	 */
+	ecm_tracker_datagram_datagram_discard(dtii, ECM_TRACKER_SENDER_TYPE_SRC, dtii->src_count);
+	ecm_tracker_datagram_datagram_discard(dtii, ECM_TRACKER_SENDER_TYPE_DEST, dtii->dest_count);
+#endif
+
+	spin_lock_bh(&ecm_tracker_datagram_lock);
+	ecm_tracker_datagram_count--;
+	DEBUG_ASSERT(ecm_tracker_datagram_count >= 0, "%px: tracker count wrap", dtii);
+	spin_unlock_bh(&ecm_tracker_datagram_lock);
+
+	DEBUG_INFO("%px: Udp tracker final\n", dtii);
+	DEBUG_CLEAR_MAGIC(dtii);
+	kfree(dtii);
+
+	return 0;
+}
+
+/*
+ * _ecm_tracker_datagram_deref_callback()
+ */
+static int ecm_tracker_datagram_deref_callback(struct ecm_tracker_instance *ti)
+{
+	struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)ti;
+	return ecm_tracker_datagram_deref(dtii);
+}
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+/*
+ * ecm_tracker_datagram_datagram_count_get()
+ *	Return number of available datagrams sent to the specified target
+ */
+static int32_t ecm_tracker_datagram_datagram_count_get(struct ecm_tracker_datagram_internal_instance *dtii, ecm_tracker_sender_type_t sender)
+{
+	int32_t count;
+
+	DEBUG_CHECK_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC, "%px: magic failed", dtii);
+
+	/*
+	 * Which list?
+	 */
+	spin_lock_bh(&dtii->lock);
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		count = dtii->src_count;
+	} else {
+		count = dtii->dest_count;
+	}
+	spin_unlock_bh(&dtii->lock);
+
+	DEBUG_TRACE("%px: datagram count get for %d is %d\n", dtii, sender, count);
+
+	return count;
+}
+
+/*
+ * ecm_tracker_datagram_datagram_count_get_callback()
+ *	Return number of available datagrams sent to the specified target
+ */
+static int32_t ecm_tracker_datagram_datagram_count_get_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender)
+{
+	struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)ti;
+	return ecm_tracker_datagram_datagram_count_get(dtii, sender);
+}
+
+/*
+ * ecm_tracker_datagram_datagram_discard_callback()
+ *	Discard n number of datagrams at the head of the datagram list that were sent to the target
+ */
+static void ecm_tracker_datagram_datagram_discard_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, int32_t n)
+{
+	struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)ti;
+
+	ecm_tracker_datagram_datagram_discard(dtii, sender, n);
+}
+
+/*
+ * ecm_tracker_datagram_datagram_size_get()
+ *	Return size in bytes of datagram at index i that was sent to the target
+ */
+static int32_t ecm_tracker_datagram_datagram_size_get(struct ecm_tracker_datagram_instance *uti, ecm_tracker_sender_type_t sender, int32_t i)
+{
+	struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)uti;
+
+	int32_t size;
+	struct sk_buff *skb;
+	DEBUG_CHECK_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC, "%px: magic failed", dtii);
+
+	/*
+	 * Which list?
+	 */
+	spin_lock_bh(&dtii->lock);
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		skb = dtii->src_recvd_order;
+	} else {
+		skb = dtii->dest_recvd_order;
+	}
+
+	/*
+	 * Iterate to the i'th datagram
+	 */
+	while (i) {
+		DEBUG_ASSERT(skb, "%px: index bad\n", dtii);
+		skb = skb->next;
+		i--;
+	}
+	DEBUG_ASSERT(skb, "%px: index bad\n", dtii);
+	size = skb->len;
+	spin_unlock_bh(&dtii->lock);
+	return size;
+}
+EXPORT_SYMBOL(ecm_tracker_datagram_datagram_size_get);
+
+/*
+ * ecm_tracker_datagram_datagram_size_get_callback()
+ *	Return size in bytes of datagram at index i that was sent to the target
+ */
+static int32_t ecm_tracker_datagram_datagram_size_get_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, int32_t i)
+{
+	struct ecm_tracker_datagram_instance *uti = (struct ecm_tracker_datagram_instance *)ti;
+
+	return ecm_tracker_datagram_datagram_size_get(uti, sender, i);
+}
+
+/*
+ * ecm_tracker_datagram_datagram_read()
+ *	Read size bytes from datagram at index i into the buffer
+ */
+static int ecm_tracker_datagram_datagram_read(struct ecm_tracker_datagram_instance *uti, ecm_tracker_sender_type_t sender, int32_t i, int32_t offset, int32_t size, void *buffer)
+{
+	struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)uti;
+	int res;
+	struct sk_buff *skb;
+	DEBUG_CHECK_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC, "%px: magic failed", dtii);
+	DEBUG_TRACE("%px: datagram %d read at offset %d for %d bytes for %d\n", dtii, i, offset, size, sender);
+
+	/*
+	 * Which list?
+	 */
+	spin_lock_bh(&dtii->lock);
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		skb = dtii->src_recvd_order;
+	} else {
+		skb = dtii->dest_recvd_order;
+	}
+
+	/*
+	 * Iterate to the i'th datagram
+	 */
+	while (i) {
+		DEBUG_ASSERT(skb, "%px: index bad\n", dtii);
+		skb = skb->next;
+		i--;
+	}
+	DEBUG_ASSERT(skb, "%px: index bad\n", dtii);
+
+	/*
+	 * Perform read
+	 */
+	res = skb_copy_bits(skb, offset, buffer, (unsigned int)size);
+
+	spin_unlock_bh(&dtii->lock);
+
+	return res;
+}
+EXPORT_SYMBOL(ecm_tracker_datagram_datagram_read);
+
+/*
+ * ecm_tracker_datagram_datagram_read_callback()
+ *	Read size bytes from datagram at index i into the buffer
+ */
+static int ecm_tracker_datagram_datagram_read_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, int32_t i, int32_t offset, int32_t size, void *buffer)
+{
+	struct ecm_tracker_datagram_instance *uti = (struct ecm_tracker_datagram_instance *)ti;
+
+	return ecm_tracker_datagram_datagram_read(uti, sender, i, offset, size, buffer);
+}
+
+/*
+ * ecm_tracker_datagram_datagram_add()
+ *	Append the datagram onto the tracker queue for the given target
+ */
+static bool ecm_tracker_datagram_datagram_add(struct ecm_tracker_datagram_instance *uti, ecm_tracker_sender_type_t sender, struct sk_buff *skb)
+{
+	struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)uti;
+	struct sk_buff *skbc;
+	DEBUG_CHECK_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC, "%px: magic failed", dtii);
+	DEBUG_TRACE("%px: datagram %px add for %d\n", dtii, skb, sender);
+
+	/*
+	 * Clone the packet
+	 */
+	skbc = skb_clone(skb, GFP_ATOMIC | __GFP_NOWARN);
+	if (!skbc) {
+		DEBUG_WARN("%px: Failed to clone packet %px\n", dtii, skb);
+		return false;
+	}
+	DEBUG_TRACE("%px: cloned %px to %px\n", dtii, skb, skbc);
+
+	/*
+	 * Are we within instance limit?
+	 */
+	spin_lock_bh(&dtii->lock);
+	DEBUG_ASSERT((dtii->src_bytes_total + dtii->dest_bytes_total + skbc->truesize) > 0, "%px: bad total\n", dtii);
+	if ((dtii->src_bytes_total + dtii->dest_bytes_total + skbc->truesize) > dtii->data_limit) {
+		DEBUG_TRACE("%px: over limit\n", dtii);
+		spin_unlock_bh(&dtii->lock);
+		kfree_skb(skbc);
+		return false;
+	}
+
+	/*
+	 * Within global limit?
+	 */
+	if (!ecm_tracker_data_total_increase(skbc->len, skbc->truesize)) {
+		DEBUG_TRACE("%px: over global limit\n", dtii);
+		spin_unlock_bh(&dtii->lock);
+		kfree_skb(skbc);
+		return false;
+	}
+
+	/*
+	 * Which list?
+	 */
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		skbc->next = NULL;
+		skbc->prev = dtii->src_recvd_order_last;
+		dtii->src_recvd_order_last = skbc;
+		if (skbc->prev) {
+			skbc->prev->next = skbc;
+		} else {
+			DEBUG_ASSERT(dtii->src_recvd_order == NULL, "%px: bad list\n", dtii);
+			dtii->src_recvd_order = skbc;
+		}
+
+		dtii->src_count++;
+		DEBUG_ASSERT(dtii->src_count > 0, "%px: bad total\n", dtii);
+		dtii->src_bytes_total += skbc->truesize;
+		spin_unlock_bh(&dtii->lock);
+		return true;
+	}
+
+	skbc->next = NULL;
+	skbc->prev = dtii->dest_recvd_order_last;
+	dtii->dest_recvd_order_last = skbc;
+	if (skbc->prev) {
+		skbc->prev->next = skbc;
+	} else {
+		DEBUG_ASSERT(dtii->dest_recvd_order == NULL, "%px: bad list\n", dtii);
+		dtii->dest_recvd_order = skbc;
+	}
+
+	dtii->dest_count++;
+	DEBUG_ASSERT(dtii->dest_count > 0, "%px: bad total\n", dtii);
+	dtii->dest_bytes_total += skbc->truesize;
+	spin_unlock_bh(&dtii->lock);
+	return true;
+}
+EXPORT_SYMBOL(ecm_tracker_datagram_datagram_add);
+
+/*
+ * _ecm_tracker_datagram_datagram_add_callback()
+ *	Append the datagram onto the tracker queue for the given target
+ */
+static bool ecm_tracker_datagram_datagram_add_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, struct sk_buff *skb)
+{
+	struct ecm_tracker_datagram_instance *uti = (struct ecm_tracker_datagram_instance *)ti;
+	return ecm_tracker_datagram_datagram_add(uti, sender, skb);
+}
+
+/*
+ * ecm_tracker_datagram_data_total_get_callback()
+ *	Return total tracked data
+ */
+static int32_t ecm_tracker_datagram_data_total_get_callback(struct ecm_tracker_instance *ti)
+{
+	struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)ti;
+	int32_t data_total;
+
+	DEBUG_CHECK_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC, "%px: magic failed", dtii);
+
+	spin_lock_bh(&dtii->lock);
+	data_total = dtii->src_bytes_total + dtii->dest_bytes_total;
+	spin_unlock_bh(&dtii->lock);
+
+	return data_total;
+}
+
+/*
+ * ecm_tracker_datagram_data_limit_get_callback()
+ *	Return tracked data limit
+ */
+static int32_t ecm_tracker_datagram_data_limit_get_callback(struct ecm_tracker_instance *ti)
+{
+	struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)ti;
+	int32_t data_limit;
+
+	DEBUG_CHECK_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC, "%px: magic failed", dtii);
+
+	spin_lock_bh(&dtii->lock);
+	data_limit = dtii->data_limit;
+	spin_unlock_bh(&dtii->lock);
+
+	return data_limit;
+}
+
+/*
+ * ecm_tracker_datagram_data_limit_set_callback()
+ *	Set tracked data limit
+ */
+static void ecm_tracker_datagram_data_limit_set_callback(struct ecm_tracker_instance *ti, int32_t data_limit)
+{
+	struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)ti;
+	DEBUG_CHECK_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC, "%px: magic failed", dtii);
+
+	spin_lock_bh(&dtii->lock);
+	dtii->data_limit = data_limit;
+	spin_unlock_bh(&dtii->lock);
+}
+#endif
+
+/*
+ * ecm_tracker_datagram_state_update_callback()
+ * 	Update connection state based on the knowledge we have and the skb given
+ */
+static void ecm_tracker_datagram_state_update_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb)
+{
+	struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)ti;
+	DEBUG_CHECK_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC, "%px: magic failed", dtii);
+
+	/*
+	 * As long as a sender has seen data then we consider the sender established
+	 */
+	spin_lock_bh(&dtii->lock);
+	dtii->sender_state[sender] = ECM_TRACKER_SENDER_STATE_ESTABLISHED;
+	spin_unlock_bh(&dtii->lock);
+}
+
+/*
+ * ecm_tracker_datagram_state_get_callback()
+ * 	Get state
+ */
+static void ecm_tracker_datagram_state_get_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_state_t *src_state,
+					ecm_tracker_sender_state_t *dest_state, ecm_tracker_connection_state_t *state, ecm_db_timer_group_t *tg)
+{
+	struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)ti;
+	DEBUG_CHECK_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC, "%px: magic failed", dtii);
+	spin_lock_bh(&dtii->lock);
+	*src_state = dtii->sender_state[ECM_TRACKER_SENDER_TYPE_SRC];
+	*dest_state = dtii->sender_state[ECM_TRACKER_SENDER_TYPE_DEST];
+	spin_unlock_bh(&dtii->lock);
+	*state = ecm_tracker_datagram_connection_state_matrix[*src_state][*dest_state];
+	*tg = ECM_DB_TIMER_GROUPS_CONNECTION_GENERIC_TIMEOUT;
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_tracker_datagram_state_text_get_callback()
+ *	Return state
+ */
+static int ecm_tracker_datagram_state_text_get_callback(struct ecm_tracker_instance *ti, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)ti;
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	int32_t src_count;
+	int32_t src_bytes_total;
+	int32_t dest_count;
+	int32_t dest_bytes_total;
+	int32_t data_limit;
+#endif
+	ecm_tracker_sender_state_t sender_state[ECM_TRACKER_SENDER_MAX];
+	ecm_tracker_connection_state_t connection_state;
+
+	DEBUG_CHECK_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC, "%px: magic failed", dtii);
+
+	if ((result = ecm_state_prefix_add(sfi, "tracker_datagram"))) {
+		return result;
+	}
+
+	/*
+	 * Capture state
+	 */
+	spin_lock_bh(&dtii->lock);
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	src_count = dtii->src_count;
+	src_bytes_total = dtii->src_bytes_total;
+	dest_count = dtii->dest_count;
+	dest_bytes_total = dtii->dest_bytes_total;
+	data_limit = dtii->data_limit;
+#endif
+	sender_state[ECM_TRACKER_SENDER_TYPE_SRC] = dtii->sender_state[ECM_TRACKER_SENDER_TYPE_SRC];
+	sender_state[ECM_TRACKER_SENDER_TYPE_DEST] = dtii->sender_state[ECM_TRACKER_SENDER_TYPE_DEST];
+	spin_unlock_bh(&dtii->lock);
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	if ((result = ecm_state_write(sfi, "src_count", "%d", src_count))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "src_bytes_total", "%d", src_bytes_total))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "dest_count", "%d", dest_count))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "dest_bytes_total", "%d", dest_bytes_total))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "data_limit", "%d", data_limit))) {
+		return result;
+	}
+#endif
+
+	connection_state = ecm_tracker_datagram_connection_state_matrix[sender_state[ECM_TRACKER_SENDER_TYPE_SRC]][sender_state[ECM_TRACKER_SENDER_TYPE_DEST]];
+	if ((result = ecm_state_write(sfi, "timer_group", "%d", ECM_DB_TIMER_GROUPS_CONNECTION_GENERIC_TIMEOUT))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "src_sender_state", "%s", ecm_tracker_sender_state_to_string(sender_state[ECM_TRACKER_SENDER_TYPE_SRC])))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "dest_sender_state", "%s", ecm_tracker_sender_state_to_string(sender_state[ECM_TRACKER_SENDER_TYPE_DEST])))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "connection_state", "%s", ecm_tracker_connection_state_to_string(connection_state)))) {
+		return result;
+	}
+
+ 	return ecm_state_prefix_remove(sfi);
+
+}
+#endif
+
+/*
+ * ecm_tracker_datagram_init()
+ *	Initialise the two host addresses that define the two directions we track data for
+ */
+void ecm_tracker_datagram_init(struct ecm_tracker_datagram_instance *uti, int32_t data_limit)
+{
+	struct ecm_tracker_datagram_internal_instance *dtii = (struct ecm_tracker_datagram_internal_instance *)uti;
+	DEBUG_CHECK_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC, "%px: magic failed", dtii);
+	DEBUG_TRACE("%px: init tracker\n", uti);
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	spin_lock_bh(&dtii->lock);
+	dtii->data_limit = data_limit;
+	spin_unlock_bh(&dtii->lock);
+#endif
+}
+EXPORT_SYMBOL(ecm_tracker_datagram_init);
+
+/*
+ * ecm_tracker_datagram_alloc()
+ */
+struct ecm_tracker_datagram_instance *ecm_tracker_datagram_alloc(void)
+{
+	struct ecm_tracker_datagram_internal_instance *dtii;
+
+	dtii = (struct ecm_tracker_datagram_internal_instance *)kzalloc(sizeof(struct ecm_tracker_datagram_internal_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!dtii) {
+		DEBUG_WARN("Failed to allocate datagram tracker instance\n");
+		return NULL;
+	}
+
+	dtii->datagram_base.base.ref = ecm_tracker_datagram_ref_callback;
+	dtii->datagram_base.base.deref = ecm_tracker_datagram_deref_callback;
+	dtii->datagram_base.base.state_update = ecm_tracker_datagram_state_update_callback;
+	dtii->datagram_base.base.state_get = ecm_tracker_datagram_state_get_callback;
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	dtii->datagram_base.base.datagram_count_get = ecm_tracker_datagram_datagram_count_get_callback;
+	dtii->datagram_base.base.datagram_discard = ecm_tracker_datagram_datagram_discard_callback;
+	dtii->datagram_base.base.datagram_read = ecm_tracker_datagram_datagram_read_callback;
+	dtii->datagram_base.base.datagram_size_get = ecm_tracker_datagram_datagram_size_get_callback;
+	dtii->datagram_base.base.datagram_add = ecm_tracker_datagram_datagram_add_callback;
+	dtii->datagram_base.base.discard_all = ecm_tracker_datagram_discard_all_callback;
+	dtii->datagram_base.base.data_total_get = ecm_tracker_datagram_data_total_get_callback;
+	dtii->datagram_base.base.data_limit_get = ecm_tracker_datagram_data_limit_get_callback;
+	dtii->datagram_base.base.data_limit_set = ecm_tracker_datagram_data_limit_set_callback;
+#endif
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	dtii->datagram_base.base.state_text_get = ecm_tracker_datagram_state_text_get_callback;
+#endif
+
+	// GGG TODO IMPLEMENT METHODS SPECIFIC TO WORKING WITH datagram e.g. reading without worrying about the datagram header content
+
+	spin_lock_init(&dtii->lock);
+
+	dtii->refs = 1;
+	DEBUG_SET_MAGIC(dtii, ECM_TRACKER_DATAGRAM_INSTANCE_MAGIC);
+
+	spin_lock_bh(&ecm_tracker_datagram_lock);
+	ecm_tracker_datagram_count++;
+	DEBUG_ASSERT(ecm_tracker_datagram_count > 0, "%px: datagram tracker count wrap\n", dtii);
+	spin_unlock_bh(&ecm_tracker_datagram_lock);
+
+	DEBUG_TRACE("DATAGRAM tracker created %px\n", dtii);
+	return (struct ecm_tracker_datagram_instance *)dtii;
+}
+EXPORT_SYMBOL(ecm_tracker_datagram_alloc);
diff --git a/qca-nss-ecm/ecm_tracker_datagram.h b/qca-nss-ecm/ecm_tracker_datagram.h
new file mode 100644
index 0000000..5340544
--- /dev/null
+++ b/qca-nss-ecm/ecm_tracker_datagram.h
@@ -0,0 +1,24 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+
+struct ecm_tracker_datagram_instance {
+	struct ecm_tracker_instance base;		/* MUST BE FIRST */
+};
+
+
+void ecm_tracker_datagram_init(struct ecm_tracker_datagram_instance *dti, int32_t data_limit);
+struct ecm_tracker_datagram_instance *ecm_tracker_datagram_alloc(void);
diff --git a/qca-nss-ecm/ecm_tracker_tcp.c b/qca-nss-ecm/ecm_tracker_tcp.c
new file mode 100644
index 0000000..b62af45
--- /dev/null
+++ b/qca-nss-ecm/ecm_tracker_tcp.c
@@ -0,0 +1,2529 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, 2020, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/sysctl.h>
+#include <linux/kthread.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_TRACKER_TCP_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_tracker_tcp.h"
+
+/*
+ * TCP control flags.
+ */
+#define TCF_FIN 0x01
+#define TCF_SYN 0x02
+#define TCF_RST 0x04
+#define TCF_PSH 0x08
+#define TCF_ACK 0x10
+#define TCF_URG 0x20
+
+/*
+ * Extract a byte tcp flags field from a union tcp_word_hdr.
+ */
+#define ECM_TRACKER_TCP_WORD_HDR_TO_FLAGS(word_hdr) ((ntohl(word_hdr->words[3]) >> 16) & 0xff)
+
+/*
+ * Valid TCP flag combinations.
+ */
+#define ECM_TRACKER_TCP_VALID_FLAGS_MAX ((TCF_URG | TCF_ACK | TCF_PSH | TCF_RST | TCF_SYN | TCF_FIN) + 1)
+
+static uint32_t ecm_tracker_tcp_valid_flags[ECM_TRACKER_TCP_VALID_FLAGS_MAX] = {
+	[TCF_FIN | TCF_RST | TCF_ACK] = 1,
+	[TCF_FIN | TCF_PSH | TCF_ACK] = 1,
+	[TCF_FIN | TCF_PSH | TCF_ACK | TCF_URG] = 1,
+	[TCF_FIN | TCF_ACK] = 1,
+	[TCF_FIN | TCF_ACK | TCF_URG] = 1,
+	[TCF_SYN] = 1,
+	[TCF_SYN | TCF_ACK] = 1,
+	[TCF_RST] = 1,
+	[TCF_RST | TCF_PSH | TCF_ACK] = 1,
+	[TCF_RST | TCF_ACK] = 1,
+	[TCF_PSH | TCF_ACK] = 1,
+	[TCF_PSH | TCF_ACK | TCF_URG] = 1,
+	[TCF_ACK] = 1,
+	[TCF_ACK | TCF_URG] = 1,
+};
+
+/*
+ * Magic numbers
+ */
+#define ECM_TRACKER_TCP_INSTANCE_MAGIC 0x5129
+#define ECM_TRACKER_TCP_SKB_CB_MAGIC 0x4398
+#define ECM_TRACKER_TCP_READER_INSTANCE_MAGIC 0x1123
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+/*
+ * struct ecm_tracker_tcp_skb_cb_format
+ *	Map of the cb[] array within our cached buffers - we use that area for our tracking
+ */
+struct ecm_tracker_tcp_skb_cb_format {
+	struct sk_buff *next;		/* Next sk buff in the recvd_order list */
+	struct sk_buff *prev;		/* Previous sk buff in the recvd_order  */
+	uint32_t seq_no;		/* Sequence number of the first readable DATA BYTE in this buffer.  There may be others but they may be old. */
+	uint32_t num_seqs;		/* Number of DATA BYTES/sequences, i.e. the number of sequences from seq_no. */
+	uint32_t offset;		/* Offset from skb->data to seq_no (i.e. header size we must skip to get to data) */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+/*
+ * struct ecm_tracker_tcp_host_data
+ *	data tracking for a host
+ */
+struct ecm_tracker_tcp_host_data {
+	uint16_t mss;					/* MSS as sent by that host in a SYN packet */
+	bool mss_seen;					/* true if the mss was from a SYN packet rather than an assigned default */
+
+	uint32_t seq_no;				/* Sequence number of the first data byte we are tracking */
+	uint32_t num_seqs;				/* Number of sequences from first */
+	bool seq_no_valid;				/* True when our sequencing is valid */
+
+	/*
+	 * All skbuffs are added into the recvd order list in addition to POSSIBLY being added into the in_order or future lists as well.
+	 * NOTE: Buffers in recv_order list make use of the [cb]->next and [cb]->prev.
+	 */
+	struct sk_buff *recvd_order;			/* skbuffs inserted in order of reception */
+	struct sk_buff *recvd_order_last;		/* skbuffs inserted in order of reception - tracks last insertion point for speed of appending */
+	int32_t recvd_bytes_total;			/* Current total of bytes of all buffers received */
+	int32_t recvd_count;				/* Current total buffers received */
+
+	/*
+	 * Buffers that have useful in-sequence-order data are added into this list
+	 * NOTE: These lists make use of sk_buff->next and sk_buff->prev because:
+	 * 1. An skb cannot be in in_order and future at the same time.
+	 * 2. It's faster to work with these pointers - which is important when sliding over lists for reading etc..
+	 */
+	struct sk_buff *in_order;			/* A list of skb's tracked in our recvd_order list in sequence space order that we can read from.
+							 * NOTE: An skb is added into both the recvd_order AND, if applicable, this list.
+							 */
+	struct sk_buff *in_order_last;			/* Fast appending of in-order data buffers */
+	int32_t in_order_count;				/* The number of skb's in the in order list */
+
+	struct sk_buff *future;				/* A list of skb's that are in the "future" (sequence space wise) and need more sequence space
+							 * received to join the 'gap' allowing their use.
+							 */
+
+};
+#endif
+
+/*
+ * struct ecm_tracker_tcp_sender_state
+ *	Connection state of each sender
+ */
+struct ecm_tracker_tcp_sender_state {
+	ecm_tracker_sender_state_t state;		/* State of the sender */
+	uint32_t syn_seq;				/* Sequence number of the syn (ISN): used to detect when peer has ack'd the syn, transitioned this sender to established. */
+	uint32_t fin_seq;				/* Sequence number of the fin: used to detect when peer has ack'd the fin, transitioned this sender to closed. */
+};
+
+/*
+ * struct ecm_tracker_tcp_internal_instance
+ */
+struct ecm_tracker_tcp_internal_instance  {
+	struct ecm_tracker_tcp_instance tcp_base;					/* MUST BE FIRST FIELD */
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	struct ecm_tracker_tcp_host_data sender_data[ECM_TRACKER_SENDER_MAX];		/* Data tracked sent by the src of the connection */
+#endif
+	struct ecm_tracker_tcp_sender_state sender_states[ECM_TRACKER_SENDER_MAX];	/* Sender states */
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	int32_t data_limit;								/* Limit for tracked data */
+#endif
+	int refs;									/* Integer to trap we never go negative */
+	spinlock_t lock;
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+/*
+ * struct ecm_tracker_tcp_reader_instance
+ *	Reader.
+ */
+struct ecm_tracker_tcp_reader_instance {
+	struct ecm_tracker_tcp_internal_instance *ttii;	/* Reference to the internal tracker instance */
+	struct ecm_tracker_tcp_host_data *data;		/* Host data this reader is using */
+
+	/*
+	 * Tracking current position
+	 */
+	uint32_t offset;				/* Logical offset from a start of 0 - i.e. from start of tracker data.
+							 * NOTE: When bytes are discarded the offset is NOT adjusted to reflect discarded bytes, i.e. they are not shifted left.
+							 * It remains as it is so that external notions of positions remain correct - especially when setting positions.
+							 */
+
+	uint32_t discarded;				/* Tracks the amount of data that has been discarded so far so that we don't try to discard them again.
+							 * This is important because offset is never modified when bytes are discarded.
+							 */
+	/*
+	 * The real work is done by the segment tracking variables that follow.
+	 * These 'slide' over the available segments and always represent actual data and positions within a segment.
+	 */
+	uint32_t segment_offset;			/* Offset from the start of the segment at which the next read will occur (header offset + data already advanced over in this segment) */
+	uint32_t segment_remain;			/* Data bytes remaining to be read in this segment given the read pointer */
+	struct sk_buff *segment;			/* Current segment skb */
+	struct ecm_tracker_tcp_skb_cb_format *segment_dcb;
+							/* The private cb area of the current segment, cached for convenience */
+
+	int refs;					/* Integer to trap we never go negative */
+	spinlock_t lock;
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+#endif
+
+/*
+ * ecm_tracker_tcp_timer_group_from_state[]
+ *	Given a prevailing connection state return the appropriate timer group.
+ *
+ * Different states have different timeouts, for example, established state is the longest timeout.
+ * Using these timeouts ensures efficient resource uses and avoids connections hanging around when it is unnecessary.
+ */
+static ecm_db_timer_group_t ecm_tracker_tcp_timer_group_from_state[] = {
+							ECM_DB_TIMER_GROUPS_CONNECTION_TCP_SHORT_TIMEOUT,	/* ECM_TRACKER_CONNECTION_STATE_ESTABLISHING */
+							ECM_DB_TIMER_GROUPS_CONNECTION_TCP_LONG_TIMEOUT,	/* ECM_TRACKER_CONNECTION_STATE_ESTABLISHED */
+							ECM_DB_TIMER_GROUPS_CONNECTION_TCP_SHORT_TIMEOUT,	/* ECM_TRACKER_CONNECTION_STATE_CLOSING */
+							ECM_DB_TIMER_GROUPS_CONNECTION_TCP_CLOSED_TIMEOUT,	/* ECM_TRACKER_CONNECTION_STATE_CLOSED */
+							ECM_DB_TIMER_GROUPS_CONNECTION_TCP_RESET_TIMEOUT,	/* ECM_TRACKER_CONNECTION_STATE_FAULT */
+							};
+int ecm_tracker_tcp_count = 0;		/* Counts the number of TCP data trackers right now */
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+int ecm_tracker_tcp_reader_count = 0;	/* Counts the number of TCP readers right now */
+#endif
+static  DEFINE_SPINLOCK(ecm_tracker_tcp_lock);	/* Global lock for the tracker globals */
+
+/*
+ * ecm_tracker_tcp_connection_state_matrix[][]
+ *	Matrix to convert from/to states to connection state
+ */
+static ecm_tracker_connection_state_t ecm_tracker_tcp_connection_state_matrix[ECM_TRACKER_SENDER_STATE_MAX][ECM_TRACKER_SENDER_STATE_MAX] =
+{	/* 			Unknown						Establishing					Established					Closing					Closed					Fault */
+	/* Unknown */		{ECM_TRACKER_CONNECTION_STATE_ESTABLISHING,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHING,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHED,	ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT},
+	/* Establishing */	{ECM_TRACKER_CONNECTION_STATE_ESTABLISHING,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHING,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHING,	ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT},
+	/* Established */	{ECM_TRACKER_CONNECTION_STATE_ESTABLISHED,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHING,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHED,	ECM_TRACKER_CONNECTION_STATE_CLOSING,	ECM_TRACKER_CONNECTION_STATE_CLOSING,	ECM_TRACKER_CONNECTION_STATE_FAULT},
+	/* Closing */		{ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_CLOSING,		ECM_TRACKER_CONNECTION_STATE_CLOSING,	ECM_TRACKER_CONNECTION_STATE_CLOSING,	ECM_TRACKER_CONNECTION_STATE_FAULT},
+	/* Closed */		{ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_CLOSING,		ECM_TRACKER_CONNECTION_STATE_CLOSING,	ECM_TRACKER_CONNECTION_STATE_CLOSED, 	ECM_TRACKER_CONNECTION_STATE_FAULT},
+	/* Fault */		{ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT},
+};
+
+/*
+ * ecm_tracker_tcp_check_header_and_read()
+ *	Check that we have a complete transport-level header, check it and return it if it's okay.
+ */
+struct tcphdr *ecm_tracker_tcp_check_header_and_read(struct sk_buff *skb, struct ecm_tracker_ip_header *ip_hdr, struct tcphdr *port_buffer)
+{
+	struct tcphdr *hdr;
+	union tcp_word_hdr *word_hdr;
+	uint16_t tcp_hdr_len;
+	uint32_t tcp_flags;
+	struct ecm_tracker_ip_protocol_header *header;
+
+	/*
+	 * Is there a TCP header?
+	 */
+	header = &ip_hdr->headers[ECM_TRACKER_IP_PROTOCOL_TYPE_TCP];
+	if (header->size == 0) {
+		DEBUG_WARN("No TCP header %px\n", skb);
+		return NULL;
+	}
+	hdr = (struct tcphdr *)skb_header_pointer(skb, header->offset, sizeof(*port_buffer), port_buffer);
+	if (unlikely(!hdr)) {
+		DEBUG_WARN("Cant read TCP header %px\n", skb);
+		return NULL;
+	}
+	word_hdr = (union tcp_word_hdr *)hdr;
+
+	/*
+	 * Check that we have all of the TCP data we're supposed to have
+	 */
+	tcp_hdr_len = (uint16_t)hdr->doff;
+	tcp_hdr_len <<= 2;
+	if (unlikely(tcp_hdr_len < 20)) {
+		DEBUG_WARN("Packet %px TCP header to short %u\n", skb, tcp_hdr_len);
+		return NULL;
+	}
+
+	if (unlikely(ip_hdr->total_length < (header->offset + header->size))) {
+		DEBUG_WARN("TCP packet %px too short (ip_total_len = %u, size needed=%u)\n", skb, ip_hdr->total_length, header->offset + header->size);
+		return NULL;
+	}
+
+	/*
+	 * Validate flags
+	 */
+	tcp_flags = ECM_TRACKER_TCP_WORD_HDR_TO_FLAGS(word_hdr);
+	DEBUG_TRACE("%px: TCP flags = 0x%04x\n", skb, (unsigned)tcp_flags);
+	if (unlikely(!ecm_tracker_tcp_valid_flags[tcp_flags & 0x3f])) {
+		DEBUG_WARN("%px: Invalid flags 0x%x", skb, (unsigned)tcp_flags);
+		return NULL;
+	}
+
+	return hdr;
+}
+EXPORT_SYMBOL(ecm_tracker_tcp_check_header_and_read);
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+/*
+ * ecm_tracker_tcp_bytes_discard()
+ *	Discard n bytes from the available in_order bytes
+ */
+static void ecm_tracker_tcp_bytes_discard(struct ecm_tracker_tcp_internal_instance *ttii, struct ecm_tracker_tcp_host_data *data, uint32_t n)
+{
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+
+	/*
+	 * Advance sequence space by 'n'.  This may allow throwing of datagrams.
+	 */
+	spin_lock_bh(&ttii->lock);
+	DEBUG_ASSERT(n <= data->num_seqs, "%px: discard invalid %u, available %u\n", ttii, n, data->num_seqs);
+	data->num_seqs -= n;
+	data->seq_no += n;
+	DEBUG_TRACE("%px: Discard %u, New seq space for %px, seq_no: %u, num_seqs: %u\n", ttii, n, data, data->seq_no, data->num_seqs);
+	spin_unlock_bh(&ttii->lock);
+
+	while (n) {
+		struct ecm_tracker_tcp_skb_cb_format *skb_cb;
+		struct sk_buff *skb;
+
+		/*
+		 * Examine the buffer at the head of the in order data list
+		 */
+		spin_lock_bh(&ttii->lock);
+		skb = data->in_order;
+		DEBUG_ASSERT(skb, "%px: data list invalid\n", ttii);
+
+		skb_cb = (struct ecm_tracker_tcp_skb_cb_format *)skb->cb;
+		DEBUG_CHECK_MAGIC(skb_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid cb magic %px\n", ttii, skb_cb);
+
+		if (n < skb_cb->num_seqs) {
+			/*
+			 * skb has more sequences in it than we are discarding.  Simply advance the sequence space by n
+			 */
+			skb_cb->seq_no += n;
+			skb_cb->offset += n;
+			skb_cb->num_seqs -= n;
+			DEBUG_TRACE("%px: PARTIAL BUFFER DISCARD SEQ: %u, NUM SEQ: %u, OFFSET: %u\n", ttii, skb_cb->seq_no, skb_cb->num_seqs, skb_cb->offset);
+			spin_unlock_bh(&ttii->lock);
+			return;
+		}
+
+		/*
+		 * Remove skb from the recvd_order list (it may be anywhere in this list)
+		 */
+		if (!skb_cb->next) {
+			DEBUG_ASSERT(data->recvd_order_last == skb, "%px: bad list\n", ttii);
+			data->recvd_order_last = skb_cb->prev;
+		} else {
+			struct ecm_tracker_tcp_skb_cb_format *next_cb;
+			next_cb = (struct ecm_tracker_tcp_skb_cb_format *)skb_cb->next->cb;
+			DEBUG_CHECK_MAGIC(next_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid cb magic %px\n", ttii, next_cb);
+			next_cb->prev = skb_cb->prev;
+		}
+		if (!skb_cb->prev) {
+			DEBUG_ASSERT(data->recvd_order == skb, "%px: bad list\n", ttii);
+			data->recvd_order = skb_cb->next;
+		} else {
+			struct ecm_tracker_tcp_skb_cb_format *prev_cb;
+			prev_cb = (struct ecm_tracker_tcp_skb_cb_format *)skb_cb->prev->cb;
+			DEBUG_CHECK_MAGIC(prev_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid cb magic %px\n", ttii, prev_cb);
+			prev_cb->next = skb_cb->next;
+		}
+
+		/*
+		 * Buffer is to be discarded in its entirety
+		 * Link it out of the in_order list - this datagram will be at the head of the list
+		 */
+		data->in_order = skb->next;
+		if (data->in_order) {
+			data->in_order->prev = NULL;
+		} else {
+			DEBUG_ASSERT(data->in_order_last == skb, "%px: bad list\n", ttii);
+			data->in_order_last = NULL;
+		}
+
+		/*
+		 * Update our stats
+		 */
+		data->in_order_count--;
+		DEBUG_ASSERT(data->in_order_count >= 0, "%px: bad in order count\n", ttii);
+		data->recvd_count--;
+		DEBUG_ASSERT(data->recvd_count >= 0, "%px: bad count\n", ttii);
+		data->recvd_bytes_total -= skb->truesize;
+		DEBUG_ASSERT(data->recvd_bytes_total >= 0, "%px: bad bytes count\n", ttii);
+		ecm_tracker_data_total_decrease(skb->len, skb->truesize);
+
+		/*
+		 * Decrement n by the number of segments we are discarding in this segment
+		 */
+		n -= skb_cb->num_seqs;
+		DEBUG_TRACE("%px: BUFFER DISCARD %px, size: %u, new head: %px end: %px, discard remain: %u, in order count: %d\n", ttii, skb, skb_cb->num_seqs, data->in_order, data->in_order_last, n, data->in_order_count);
+		spin_unlock_bh(&ttii->lock);
+
+		dev_kfree_skb_any(skb);
+	}
+}
+
+/*
+ * ecm_tracker_tcp_bytes_discard_callback()
+ *	Discard n bytes from the available stream bytes
+ */
+static void ecm_tracker_tcp_bytes_discard_callback(struct ecm_tracker_tcp_instance *tti, ecm_tracker_sender_type_t sender, uint32_t n)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)tti;
+	struct ecm_tracker_tcp_host_data *data;
+
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+	DEBUG_ASSERT((sender >= 0) && (sender <= 1), "%px: invalid sender %d\n", ttii, sender);
+
+	/*
+	 * Which list?
+	 */
+	data = &ttii->sender_data[sender];
+	ecm_tracker_tcp_bytes_discard(ttii, data, n);
+}
+
+/*
+ * ecm_tracker_tcp_datagram_discard_callback()
+ *	Discard n number of datagrams from the in_order list
+ *
+ * NOTE: This discards from the in_order list - this means that any data in the future list cannot be destroyed by this method.
+ */
+static void ecm_tracker_tcp_datagram_discard_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, int32_t n)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)ti;
+	struct ecm_tracker_tcp_host_data *data;
+	struct sk_buff *skb;
+	uint32_t seqs_discard;
+
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+	DEBUG_ASSERT((sender >= 0) && (sender <= 1), "%px: invalid sender %d\n", ttii, sender);
+
+	/*
+	 * Which list?
+	 */
+	data = &ttii->sender_data[sender];
+
+	/*
+	 * Get the number of sequences in n datagrams
+	 */
+	seqs_discard = 0;
+	spin_lock_bh(&ttii->lock);
+	skb = data->in_order;
+	while (n) {
+		struct ecm_tracker_tcp_skb_cb_format *skb_cb;
+
+		skb_cb = (struct ecm_tracker_tcp_skb_cb_format *)skb->cb;
+		DEBUG_CHECK_MAGIC(skb_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid cb magic %px\n", ttii, skb);
+		seqs_discard += skb_cb->num_seqs;
+		skb = skb->next;
+		n--;
+	}
+	spin_unlock_bh(&ttii->lock);
+
+	/*
+	 * Now simply discard bytes to the tune of seqs_discard!
+	 */
+	ecm_tracker_tcp_bytes_discard(ttii, data, seqs_discard);
+}
+
+/*
+ * _ecm_tracker_tcp_discard_all()
+ *	Discard all tracked data
+ *
+ * NOTE: Calling this will erase all data within the tracker - including any future unsequenced data.  FOR BOTH SENDERS.
+ * Sequence space tracking shall pick up again on the next tracked data packets.
+ * Don't call this function often (slow) - usually you call it when your classifier has determined responsibility for a connection and
+ * it no longer needs any data - and will not, typically, track any further data either.
+ */
+static void _ecm_tracker_tcp_discard_all(struct ecm_tracker_tcp_internal_instance *ttii)
+{
+	int s;
+
+	DEBUG_TRACE("%px: destroy all\n", ttii);
+	for (s = 0; s < ECM_TRACKER_SENDER_MAX; ++s) {
+		struct ecm_tracker_tcp_host_data *data;
+
+		/*
+		 * Get sender data
+		 */
+		data = &ttii->sender_data[s];
+
+		/*
+		 * Discard all in the recvd_order list
+		 */
+		while (data->recvd_count) {
+			struct ecm_tracker_tcp_skb_cb_format *skb_cb;
+			struct sk_buff *skb;
+
+			/*
+			 * Get private region of skb that maintains the recvd_order list pointers
+			 */
+			skb = data->recvd_order;
+			skb_cb = (struct ecm_tracker_tcp_skb_cb_format *)skb->cb;
+			DEBUG_CHECK_MAGIC(skb_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid cb magic %px\n", ttii, skb);
+
+			/*
+			 * Remove the skb from the recvd_order list
+			 * NOTE: We don't have to maintain recvd_order_last or any list prev pointers its because we are discarding the lot!
+			 */
+			data->recvd_order = skb_cb->next;
+			data->recvd_count--;
+
+			/*
+			 * Destroy
+			 */
+			ecm_tracker_data_total_decrease(skb->len, skb->truesize);
+			dev_kfree_skb_any(skb);
+		}
+		DEBUG_ASSERT(data->recvd_order == NULL, "%px: recvd_count not match recvd_order length: %px\n", ttii, data->recvd_order);
+		data->recvd_order_last = NULL;
+		data->recvd_bytes_total = 0;
+		data->in_order = NULL;
+		data->in_order_last = NULL;
+		data->in_order_count = 0;
+		data->future = NULL;
+
+		/*
+		 * Invalidate the sequence space
+		 */
+		data->seq_no_valid = false;
+	}
+}
+
+/*
+ * ecm_tracker_tcp_discard_all_callback()
+ *	Discard all tracked data
+ *
+ * NOTE: Calling this will erase all data within the tracker - including any future unsequenced data.  FOR BOTH SENDERS.
+ * Sequence space tracking shall pick up again on the next tracked data packets.
+ * Don't call this function often (slow) - usually you call it when your classifier has determined responsibility for a connection and
+ * it no longer needs any data - and will not, typically, track any further data either.
+ */
+static void ecm_tracker_tcp_discard_all_callback(struct ecm_tracker_instance *ti)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)ti;
+
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+	spin_lock_bh(&ttii->lock);
+	_ecm_tracker_tcp_discard_all(ttii);
+	spin_unlock_bh(&ttii->lock);
+}
+#endif
+
+/*
+ * ecm_tracker_tcp_ref_callback()
+ */
+void ecm_tracker_tcp_ref_callback(struct ecm_tracker_instance *ti)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)ti;
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+
+	spin_lock_bh(&ttii->lock);
+
+	ttii->refs++;
+	DEBUG_ASSERT(ttii->refs > 0, "%px: ref wrap", ttii);
+	DEBUG_TRACE("%px: ref %d\n", ttii, ttii->refs);
+
+	spin_unlock_bh(&ttii->lock);
+}
+
+/*
+ * ecm_tracker_tcp_deref_callback()
+ */
+int ecm_tracker_tcp_deref_callback(struct ecm_tracker_instance *ti)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)ti;
+	int refs;
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+
+	spin_lock_bh(&ttii->lock);
+	ttii->refs--;
+	refs = ttii->refs;
+	DEBUG_ASSERT(ttii->refs >= 0, "%px: ref wrap", ttii);
+	DEBUG_TRACE("%px: deref %d\n", ttii, ttii->refs);
+
+	if (ttii->refs > 0) {
+		spin_unlock_bh(&ttii->lock);
+		return refs;
+	}
+
+	DEBUG_TRACE("%px: final\n", ttii);
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	_ecm_tracker_tcp_discard_all(ttii);
+#endif
+	spin_unlock_bh(&ttii->lock);
+
+	spin_lock_bh(&ecm_tracker_tcp_lock);
+	ecm_tracker_tcp_count--;
+	DEBUG_ASSERT(ecm_tracker_tcp_count >= 0, "%px: tracker count wrap", ttii);
+	spin_unlock_bh(&ecm_tracker_tcp_lock);
+
+	DEBUG_INFO("%px: TCP tracker final\n", ttii);
+	DEBUG_CLEAR_MAGIC(ttii);
+	kfree(ttii);
+
+	return 0;
+}
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+/*
+ * ecm_tracker_tcp_datagram_count_get_callback()
+ *	Return number of available datagrams sent to the specified target in the in_order list
+ */
+static int32_t ecm_tracker_tcp_datagram_count_get_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)ti;
+	int32_t count;
+
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+	DEBUG_ASSERT((sender >= 0) && (sender <= 1), "%px: invalid sender %d\n", ttii, sender);
+
+	/*
+	 * Which list?
+	 */
+	spin_lock_bh(&ttii->lock);
+	count = ttii->sender_data[sender].in_order_count;
+	spin_unlock_bh(&ttii->lock);
+	DEBUG_TRACE("%px: datagram count get for %d is %d\n", ttii, sender, count);
+
+	return count;
+}
+
+/*
+ * ecm_tracker_tcp_datagram_size_get_callback()
+ *	Return size in bytes of in_order datagram at index i that was sent by the sender
+ */
+static int32_t ecm_tracker_tcp_datagram_size_get_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, int32_t i)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)ti;
+	int32_t size;
+	struct sk_buff *skb;
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+	DEBUG_ASSERT((sender >= 0) && (sender <= 1), "%px: invalid sender %d\n", ttii, sender);
+
+	DEBUG_TRACE("%px: get datagram size at %u for %d\n", ttii, i, sender);
+
+	/*
+	 * Which list?
+	 */
+	spin_lock_bh(&ttii->lock);
+	skb = ttii->sender_data[sender].in_order;
+
+	/*
+	 * Iterate to the i'th datagram
+	 */
+	while (i) {
+		DEBUG_ASSERT(skb, "%px: index bad\n", ttii);
+		skb = skb->next;
+		i--;
+	}
+	DEBUG_ASSERT(skb, "%px: index bad\n", ttii);
+
+	/*
+	 * Get size
+	 */
+	size = skb->len;
+	spin_unlock_bh(&ttii->lock);
+
+	DEBUG_TRACE("%px: datagram size is %d\n", ttii, size);
+	return size;
+}
+
+/*
+ * ecm_tracker_tcp_datagram_read_callback()
+ *	Read size bytes from the i'th in_order datagram
+ */
+static int ecm_tracker_tcp_datagram_read_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, int32_t i, int32_t offset, int32_t size, void *buffer)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)ti;
+	int res;
+	struct sk_buff *skb;
+
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+	DEBUG_TRACE("%px: datagram %d read at offset %d for %d bytes for %d\n", ttii, i, offset, size, sender);
+	DEBUG_ASSERT((sender >= 0) && (sender <= 1), "%px: invalid sender %d\n", ttii, sender);
+
+	/*
+	 * Which list?
+	 */
+	spin_lock_bh(&ttii->lock);
+	skb = ttii->sender_data[sender].in_order;
+
+	/*
+	 * Iterate to the i'th datagram
+	 */
+	while (i) {
+		DEBUG_ASSERT(skb, "%px: index bad\n", ttii);
+		skb = skb->next;
+		i--;
+	}
+	DEBUG_ASSERT(skb, "%px: index bad\n", ttii);
+
+	/*
+	 * Perform read
+	 */
+	res = skb_copy_bits(skb, offset, buffer, (unsigned int)size);
+	spin_unlock_bh(&ttii->lock);
+
+	return res;
+}
+
+/*
+ * _ecm_tracker_tcp_data_future_replay()
+ *	Replay packets in the future data list to see if any are now in sequence.
+ *
+ * NOTE: 'Future' is a misnomer here because the arrival of data may have actually cause some future data
+ * to now be old, example:
+ * SPACE:    --------------CCCCCCCC-------
+ * FUTURE:   ------------------------FFF--
+ * NEW:      ----------------------NNNNNN
+ * As you can see the future data is now rendered old by the arrival of sequences
+ *
+ * NOTE: The future data list may also contain duplicate future data - we weren't that fussy when we inserted the segment into the future list.
+ */
+static void _ecm_tracker_tcp_data_future_replay(struct ecm_tracker_tcp_internal_instance *ttii,
+									struct ecm_tracker_tcp_host_data *data)
+{
+	while (data->future) {
+		struct ecm_tracker_tcp_skb_cb_format *skb_cb;
+		struct sk_buff *skb;
+		int32_t in_sequence;
+		int32_t new_seqs;
+		int32_t offset;
+
+		/*
+		 * Get our private area of future buffer
+		 */
+		skb = data->future;
+		skb_cb = (struct ecm_tracker_tcp_skb_cb_format *)skb->cb;
+		DEBUG_CHECK_MAGIC(skb_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid cb magic %px\n", ttii, skb_cb);
+
+		/*
+		 * Identify the sequence space
+		 */
+		in_sequence = (int32_t)(skb_cb->seq_no - (data->seq_no + data->num_seqs));
+		new_seqs = (int32_t)(skb_cb->num_seqs + in_sequence);
+		offset = -in_sequence;
+		DEBUG_TRACE("%px: FUTURE REPLAY %px: in_sequence: %d, new_seqs: %d, offset: %d\n", ttii, skb, in_sequence, new_seqs, offset);
+
+		/*
+		 * Is the segment still in the future?
+		 */
+		if (in_sequence > 0) {
+			/*
+			 * Still awaiting sequences until this segment becomes valid.
+			 * We are done
+		 	 */
+			DEBUG_TRACE("%px: FUTURE REPLAY FUTURE SEQ: %u LEN:%u\n", ttii, skb_cb->seq_no, skb_cb->num_seqs);
+			break;
+		}
+
+		/*
+		 * Whatever happens now we are definately linking this skb out of the futures list
+		 */
+		data->future = skb->next;
+		if (data->future) {
+			data->future->prev = NULL;
+		}
+
+		/*
+		 * Does the segment contain only old data?
+		 */
+		if (new_seqs <= 0) {
+			/*
+			 * all old - skb needs to be discarded
+			 */
+			DEBUG_TRACE("%px: FUTURE REPLAY OLD SEQ: %u LEN:%u, new future head: %px\n", ttii, skb_cb->seq_no, skb_cb->num_seqs, data->future);
+
+			/*
+			 * Remove skb from the recvd_order list (it may be anywhere in this list)
+			 */
+			if (!skb_cb->next) {
+				DEBUG_ASSERT(data->recvd_order_last == skb, "%px: bad list\n", ttii);
+				data->recvd_order_last = skb_cb->prev;
+			} else {
+				struct ecm_tracker_tcp_skb_cb_format *next_cb;
+				next_cb = (struct ecm_tracker_tcp_skb_cb_format *)skb_cb->next->cb;
+				DEBUG_CHECK_MAGIC(next_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid cb magic %px\n", ttii, next_cb);
+				next_cb->prev = skb_cb->prev;
+			}
+			if (!skb_cb->prev) {
+				DEBUG_ASSERT(data->recvd_order == skb, "%px: bad list\n", ttii);
+				data->recvd_order = skb_cb->next;
+			} else {
+				struct ecm_tracker_tcp_skb_cb_format *prev_cb;
+				prev_cb = (struct ecm_tracker_tcp_skb_cb_format *)skb_cb->prev->cb;
+				DEBUG_CHECK_MAGIC(prev_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid cb magic %px\n", ttii, prev_cb);
+				prev_cb->next = skb_cb->next;
+			}
+
+			/*
+			 * Update stats
+			 */
+			data->recvd_count--;
+			DEBUG_ASSERT(data->recvd_count >= 0, "%px: bad count\n", ttii);
+			data->recvd_bytes_total -= skb->truesize;
+			ecm_tracker_data_total_decrease(skb->len, skb->truesize);
+			DEBUG_ASSERT(data->recvd_bytes_total >= 0, "%px: bad bytes count\n", ttii);
+
+			/*
+			 * Release skb containing obsoleted data
+			 */
+			dev_kfree_skb_any(skb);
+			continue;
+		}
+
+		/*
+		 * We are dealing with new or some new/old data.
+		 */
+		DEBUG_ASSERT(offset >= 0, "%px: alg bad, offset negative at %d\n", ttii, offset);
+
+		/*
+		 * Initialise the private cb space
+		 * The sequence space recorded here is READABLE space i.e. any old/dup is removed
+		 */
+		skb_cb->seq_no += offset;				/* Advance sequence space to new data sequences */
+		skb_cb->num_seqs = (uint32_t)new_seqs;
+		skb_cb->offset += offset;				/* Add new offset to existing offset */
+
+		/*
+		 * Insert the skb onto the end of the data list - it must be the end because the data here is considered in order
+		 */
+		skb->next = NULL;
+		skb->prev = data->in_order_last;
+		data->in_order_last = skb;
+		if (skb->prev) {
+			skb->prev->next = skb;
+		} else {
+			/*
+			 * If there is no data_end then skb is at the head of the list
+			 */
+			DEBUG_ASSERT(data->in_order == NULL, "%px: bad data_end, data points to %px\n", ttii, data->in_order);
+			data->in_order = skb;
+		}
+		data->in_order_count++;
+		DEBUG_ASSERT(data->in_order_count > 0, "%px: invalid in_order count %d for data %px\n", ttii, data->in_order_count, data);
+
+		/*
+		 * Update our contiguous space pointer
+		 */
+		data->num_seqs += (uint32_t)new_seqs;
+
+		DEBUG_TRACE("%px: FUTURE REPLAY IN SEQ:%u LEN:%u.  Inserted between %px and %px.  SEQ SPACE: %u, len %u, in_order_count %d\n", ttii, skb_cb->seq_no, skb_cb->num_seqs, skb_cb->prev,
+				skb_cb->next, data->seq_no, data->num_seqs, data->in_order_count);
+	}
+
+	DEBUG_TRACE("%px: FUTURE REPLAY COMPLETE\n", ttii);
+}
+
+/*
+ * _ecm_tracker_tcp_stream_segment_add()
+ *	Add skb buff into our stream tracking lists if appropriate.
+ *
+ * Must pass a validly formed tcp segment to this function.
+ * Returns true when the segment is to be recorded in the recvd_order list.
+ */
+static bool _ecm_tracker_tcp_stream_segment_add(struct ecm_tracker_tcp_internal_instance *ttii,
+									struct ecm_tracker_tcp_host_data *data,
+									struct ecm_tracker_ip_header *ip_hdr, struct ecm_tracker_ip_protocol_header *ecm_tcp_header,
+									struct tcphdr *tcp_hdr, struct sk_buff *skb,
+									struct ecm_tracker_tcp_skb_cb_format *skb_cb)
+{
+	uint16_t data_offset;
+	uint16_t data_len;
+	uint32_t seq;
+	uint32_t num_seqs;
+	int32_t in_sequence;
+	int32_t new_seqs;
+	int32_t offset;
+
+	/*
+	 * We should have been passed a valid cb area
+	 */
+	DEBUG_CHECK_MAGIC(skb_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: skb bad cb magic\n", ttii);
+
+	/*
+	 * Reset? ignore
+	 */
+	if (unlikely(tcp_hdr->rst)) {
+		DEBUG_TRACE("%px: reset seen - ignoring\n", ttii);
+		return false;
+	}
+
+	/*
+	 * Figure out the data length in this TCP segment.
+	 */
+	DEBUG_ASSERT((ecm_tcp_header->offset + ecm_tcp_header->size) <= ip_hdr->total_length, "%px: invalid hdrs\n", ttii);
+	data_offset = ecm_tcp_header->offset + ecm_tcp_header->header_size;
+	data_len = ecm_tcp_header->size - ecm_tcp_header->header_size;
+	DEBUG_TRACE("%px: data offset: %u, data_len = %u\n", ttii, data_offset, data_len);
+
+	/*
+	 * Set sequence number of first byte of data in the header.
+	 * NOTE: If the syn flag is set then this is sequenced like a data byte
+	 */
+	seq = ntohl(tcp_hdr->seq);
+
+	/*
+	 * If SYN or FIN are set then we have one sequence
+	 */
+	if (unlikely(tcp_hdr->syn)) {
+		/*
+		 * First actual byte of data has the next sequence number
+		 */
+		seq++;
+	}
+
+	/*
+	 * If our sequence space is not yet validated then we take the sequence number of this packet
+	 * to validate our sequence numbering
+	 */
+	if (unlikely(!data->seq_no_valid)) {
+		DEBUG_ASSERT(data->in_order == NULL, "%px: in_order not null %px\n", ttii, data->in_order);
+		DEBUG_ASSERT(data->in_order_last == NULL, "%px: in_order_last not null %px\n", ttii, data->in_order_last);
+		DEBUG_ASSERT(data->in_order_count == 0, "%px: in_order_count not 0: %d\n", ttii, data->in_order_count);
+
+		/*
+		 * Sequence numbers are not valid at the moment so this segment is where we start from
+		 */
+		data->seq_no = seq;
+		data->num_seqs = 0;
+		data->seq_no_valid = true;
+
+		DEBUG_TRACE("%px: FIRST SEQ:%u\n", ttii, seq);
+	}
+
+	/*
+	 * Do we have any data?
+	 */
+	if (data_len == 0) {
+		return false;
+	}
+
+	/*
+	 * Examine the data sequence space:
+	 * It contains in sequence new data - USE NEW.
+	 * It is old data - IGNORE
+	 * It is duplicate - IGNORE
+	 * It contains some old, duplicate, new - IGNORE OLD and DUPLICATE.  USE NEW.
+	 * It contains some future - ADD TO FUTURES LIST
+	 * Sequence space possibilities:
+	 * SEQ SPACE:     0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz
+	 * CURRENT SPACE: -----------------CCCCCCCCCCCCCCCCCC---------------------------
+	 * NEW:           -----------------------------------NNN------------------------
+	 * ALL OLD:       ----------OOOOOOO---------------------------------------------
+	 * DUPLICATE:     -----------------DDDDDDD--------------------------------------
+	 * OLD/DUP/NEW:   --------------OOODDDDDDDDDDDDDDDDDDNNNNNNNNNNN----------------
+	 * FUTURE:        ------------------------------------F-------------------------
+	 */
+
+	/*
+	 * Number of sequences is now the data length
+	 */
+	num_seqs = data_len;
+
+	/*
+	 * Is the segment in sequence?
+	 * Sequence space scenarios:
+	 * data->seq	data->num_seqs		seq	num_seqs	in_sequence	new_seqs	Offset	Result?
+	 * 100		20			120	30		0		30		0	In sequence 30 bytes, new data is from the first data byte in skb
+	 * 100		20			121	30		1		31		-1	Future, new_seqs is irrelevant here, offset irrelevant
+	 * 100		20			119	30		-1		29		1	1 DUP, 29 new, offset to new data is 1
+	 * 100		20			100	30		-20		10		20	20 DUP, 10 new, offset to new data is 20
+	 * 100		20			99	30		-21		9		21	21 DUP, 9 new, offset to new data is 21
+	 * 100		20			90	30		-30		0		30	Nothing new, offset irrelevant
+	 * 100		20			70	30		-50		-20		50	Nothing new, offset irrelevant
+	 */
+	in_sequence = (int32_t)(seq - (data->seq_no + data->num_seqs));
+	new_seqs = (int32_t)(num_seqs + in_sequence);
+	offset = -in_sequence;
+	DEBUG_TRACE("%px: in_sequence: %d, new_seqs: %d, offset: %d\n", ttii, in_sequence, new_seqs, offset);
+
+	/*
+	 * Does the segment contain only old data?
+	 */
+	if (new_seqs <= 0) {
+		/*
+		 * all old
+		 */
+		DEBUG_TRACE("%px: OLD SEQ: %u LEN:%u\n", ttii, seq, num_seqs);
+		return false;
+	}
+
+	/*
+	 * Is the segment in the future?
+	 */
+	if (unlikely(in_sequence > 0)) {
+		/*
+		 * Packet contains sequences in the future
+		 */
+		struct sk_buff *nskb;
+		struct sk_buff *pskb;
+
+		/*
+		 * Initialise the private cb space
+		 * Note that sequence space here may duplicate other future data but that will be corrected when future data is sorted out.
+		 */
+		skb_cb->seq_no = seq;
+		skb_cb->num_seqs = num_seqs;
+		skb_cb->offset = data_offset;
+		DEBUG_INFO("%px: FUTURE SEQ: %u LEN:%u\n", ttii, seq, num_seqs);
+
+		/*
+		 * Insert the segment into the future list in order of sequence number
+		 */
+		nskb = data->future;
+		pskb = NULL;
+		while (nskb) {
+			struct ecm_tracker_tcp_skb_cb_format *nskb_cb;
+			nskb_cb = (struct ecm_tracker_tcp_skb_cb_format *)nskb->cb;
+			DEBUG_CHECK_MAGIC(nskb_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid cb magic %px\n", ttii, nskb_cb);
+			DEBUG_TRACE("%px: seq: %u, nskb_cb->seq: %u\n", ttii, seq, nskb_cb->seq_no);
+			if (seq <= nskb_cb->seq_no) {
+				break;
+			}
+			pskb = nskb;
+			nskb = nskb->next;
+		}
+		DEBUG_TRACE("%px: Insert after %px and before %px\n", ttii, pskb, nskb);
+
+		/*
+		 * Insert skb between pskb and nskb in the futures list
+		 */
+		skb->next = nskb;
+		skb->prev = pskb;
+		if (nskb) {
+			nskb->prev = skb;
+		}
+		if (pskb) {
+			pskb->next = skb;
+		} else {
+			/*
+			 * Head of the list
+			 */
+			DEBUG_ASSERT(data->future == nskb, "%px: invalid future list %px != %px\n", ttii, data->future, nskb);
+			data->future = skb;
+		}
+
+		DEBUG_TRACE("%px: FUTURE SEQ:%u LEN:%u.  Inserted after %px and before %px\n", ttii, seq, num_seqs, pskb, nskb);
+		return true;
+	}
+
+	/*
+	 * We are dealing with new or some new/old data.
+	 */
+	DEBUG_ASSERT(offset >= 0, "%px: alg bad, offset negative at %d\n", ttii, offset);
+
+	/*
+	 * Initialise the private cb space
+	 * The sequence space recorded here is READABLE space i.e. any old/dup is removed
+	 */
+	skb_cb->seq_no = seq + offset;
+	skb_cb->num_seqs = (uint32_t)new_seqs;
+	skb_cb->offset = data_offset + offset;
+
+	/*
+	 * Insert the skb onto the end of the data list - it must be the end because the data here is considered in order
+	 */
+	skb->next = NULL;
+	skb->prev = data->in_order_last;
+	data->in_order_last = skb;
+	if (skb->prev) {
+		skb->prev->next = skb;
+	} else {
+		/*
+		 * If there is no data_end then skb is at the head of the list
+		 */
+		DEBUG_ASSERT(data->in_order == NULL, "%px: bad data_end, data points to %px\n", ttii, data->in_order);
+		data->in_order = skb;
+	}
+	data->in_order_count++;
+	DEBUG_ASSERT(data->in_order_count > 0, "%px: invalid in_order count %d for data %px\n", ttii, data->in_order_count, data);
+
+	/*
+	 * Update our contiguous space pointers
+	 */
+	data->num_seqs += (uint32_t)new_seqs;
+
+	DEBUG_TRACE("%px: IN SEQ:%u LEN:%u.  Inserted between %px and %px.  SEQ SPACE starts at: %u, len %u, in_order_count %d\n",
+			ttii, skb_cb->seq_no, skb_cb->num_seqs, skb_cb->prev, skb_cb->next, data->seq_no, data->num_seqs, data->in_order_count);
+
+	/*
+	 * Do we have any future data?  It's likely we won't as it is rare for packets to arrive out of sequence in this way.
+	 */
+	if (likely(!data->future)) {
+		return true;
+	}
+
+	/*
+	 * We now need to process future data - the reception of seqences here may now release some
+	 */
+	_ecm_tracker_tcp_data_future_replay(ttii, data);
+	return true;
+}
+
+/*
+ * ecm_tracker_tcp_extract_mss()
+ *	Read the MSS from the options block of the tcp header
+ */
+static bool ecm_tracker_tcp_extract_mss(struct sk_buff *skb, uint16_t *mss, struct ecm_tracker_ip_protocol_header *ecm_tcp_header)
+{
+	struct tcp_options_received opt_rx;
+
+	/*
+	 * Set he transport header offset (tcp) - unlikely not to be set BUT we don't take the chance
+	 */
+	skb_set_transport_header(skb, ecm_tcp_header->offset);
+
+	/*
+	 * Parse the TCP header options
+	 */
+	memset(&opt_rx, 0, sizeof(opt_rx));
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	tcp_parse_options(skb, &opt_rx, 0, NULL);
+#else
+	tcp_parse_options(dev_net(skb->dev), skb, &opt_rx, 0, NULL);
+#endif
+	/*
+	 * Was there an MSS?
+	 */
+	if (!opt_rx.mss_clamp) {
+		DEBUG_WARN("No mss clamp in skb %px\n", skb);
+		return false;
+	}
+
+	DEBUG_INFO("MSS clamp seen in %px as %u\n", skb, opt_rx.mss_clamp);
+	*mss = opt_rx.mss_clamp;
+
+	return true;
+}
+
+/*
+ * ecm_tracker_tcp_segment_add_callback()
+ *	Append the segment onto the tracker queue for the given target
+ */
+static bool ecm_tracker_tcp_segment_add_callback(struct ecm_tracker_tcp_instance *tti, ecm_tracker_sender_type_t sender,
+								struct ecm_tracker_ip_header *ip_hdr, struct ecm_tracker_ip_protocol_header *ecm_tcp_header,
+								struct tcphdr *tcp_hdr, struct sk_buff *skb)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)tti;
+	struct sk_buff *skbc;
+	struct ecm_tracker_tcp_host_data *data;
+	struct ecm_tracker_tcp_skb_cb_format *skbc_cb;
+
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+	DEBUG_ASSERT((sender >= 0) && (sender <= 1), "%px: invalid sender %d\n", ttii, sender);
+	DEBUG_ASSERT(ecm_tcp_header->protocol_number == IPPROTO_TCP, "%px: invalid sender %u\n", ttii, ecm_tcp_header->protocol_number);
+	DEBUG_TRACE("%px: segment %px add for %d\n", ttii, skb, sender);
+
+	/*
+	 * Clone the packet
+	 */
+	skbc = skb_clone(skb, GFP_ATOMIC | __GFP_NOWARN);
+	if (!skbc) {
+		DEBUG_WARN("%px: Failed to clone packet %px\n", ttii, skb);
+		return false;
+	}
+
+	DEBUG_TRACE("%px: cloned %px to %px\n", ttii, skb, skbc);
+
+	/*
+	 * Get the private cb area and initialise it.
+	 * ALL SEGMENTS HAVE TO HAVE ONE.
+	 */
+	skbc_cb = (struct ecm_tracker_tcp_skb_cb_format *)skbc->cb;
+	DEBUG_SET_MAGIC(skbc_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC);
+
+	spin_lock_bh(&ttii->lock);
+
+	/*
+	 * Are we within instance limit?
+	 */
+	DEBUG_ASSERT((ttii->sender_data[ECM_TRACKER_SENDER_TYPE_SRC].recvd_bytes_total + ttii->sender_data[ECM_TRACKER_SENDER_TYPE_DEST].recvd_bytes_total + skbc->truesize) > 0, "%px: bad total\n", ttii);
+	if ((ttii->sender_data[ECM_TRACKER_SENDER_TYPE_SRC].recvd_bytes_total + ttii->sender_data[ECM_TRACKER_SENDER_TYPE_DEST].recvd_bytes_total + skbc->truesize) > ttii->data_limit) {
+		DEBUG_TRACE("%px: over limit\n", ttii);
+		spin_unlock_bh(&ttii->lock);
+		dev_kfree_skb_any(skbc);
+		return false;
+	}
+
+	/*
+	 * Within global limit?
+	 */
+	if (!ecm_tracker_data_total_increase(skbc->len, skbc->truesize)) {
+		DEBUG_TRACE("%px: over global limit\n", ttii);
+		spin_unlock_bh(&ttii->lock);
+		dev_kfree_skb_any(skbc);
+		return false;
+	}
+
+	/*
+	 * Which list?
+	 */
+	data = &ttii->sender_data[sender];
+
+	/*
+	 * Do we have the MSS for this host?  Unlikely as most streams we would have seen the SYN already and retrieved the MSS.
+	 */
+	if (unlikely(tcp_hdr->syn) && unlikely(!data->mss_seen)) {
+		uint16_t mss;
+		if (ecm_tracker_tcp_extract_mss(skbc, &mss, ecm_tcp_header)) {
+			data->mss = mss;
+			data->mss_seen = true;
+			DEBUG_TRACE("%px: Seen mss as %u for %px\n", ttii, mss, data);
+		}
+	}
+
+	/*
+	 * If sequence tracking is enabled but the segment is not wanted then we simply discard it
+	 */
+	if (!_ecm_tracker_tcp_stream_segment_add(ttii, data, ip_hdr, ecm_tcp_header, tcp_hdr, skbc, skbc_cb)) {
+		spin_unlock_bh(&ttii->lock);
+		ecm_tracker_data_total_decrease(skbc->len, skbc->truesize);
+		dev_kfree_skb_any(skbc);
+
+		/*
+		 * Return true - there is nothing wrong with the datagram we just don't want this datagram but we will still
+		 * allow it to pass and still want to account for it in the connection stats
+		 */
+		return true;
+	}
+
+	/*
+	 * Store the packet in the reception order list.
+	 * NOTE: When sequence tracking is not enabled we want to store things as they are received no matter what.
+	 * When we are sequence tracking we only store the skb when the segment has been added successfully
+	 */
+	skbc_cb->next = NULL;
+	skbc_cb->prev = data->recvd_order_last;
+	data->recvd_order_last = skbc;
+	if (!skbc_cb->prev) {
+		DEBUG_ASSERT(data->recvd_order == NULL, "%px: bad list\n", ttii);
+		data->recvd_order = skbc;
+	} else {
+		struct ecm_tracker_tcp_skb_cb_format *prev_cb;
+		prev_cb = (struct ecm_tracker_tcp_skb_cb_format *)skbc_cb->prev->cb;
+		DEBUG_CHECK_MAGIC(prev_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid cb magic %px\n", ttii, prev_cb);
+		prev_cb->next = skbc;
+	}
+
+	/*
+	 * Update stats
+	 */
+	data->recvd_count++;
+	DEBUG_ASSERT(data->recvd_count > 0, "%px: bad count\n", ttii);
+	data->recvd_bytes_total += skbc->truesize;
+	DEBUG_TRACE("%px: Segment %px added between %px and %px. recvd total %u, bytes total %u\n",
+			ttii, skbc, skbc->prev, skbc->next, data->recvd_count, data->recvd_bytes_total);
+	spin_unlock_bh(&ttii->lock);
+	return true;
+}
+
+/*
+ * ecm_tracker_tcp_datagram_add_callback()
+ *	Append the datagram onto the tracker queue for the given target
+ */
+static bool ecm_tracker_tcp_datagram_add_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, struct sk_buff *skb)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)ti;
+	struct sk_buff *skbc;
+	struct ecm_tracker_tcp_skb_cb_format *skbc_cb;
+	struct ecm_tracker_ip_header ip_hdr;
+	struct ecm_tracker_ip_protocol_header *ecm_tcp_header;
+	struct tcphdr tcp_hdr_buff;
+	struct tcphdr *tcp_hdr;
+	struct ecm_tracker_tcp_host_data *data;
+
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+	DEBUG_ASSERT((sender >= 0) && (sender <= 1), "%px: invalid sender %d\n", ttii, sender);
+	DEBUG_TRACE("%px: datagram %px add for sender: %d\n", ttii, skb, sender);
+
+	/*
+	 * Clone the packet
+	 */
+	skbc = skb_clone(skb, GFP_ATOMIC | __GFP_NOWARN);
+	if (!skbc) {
+		DEBUG_WARN("%px: Failed to clone packet %px\n", ttii, skb);
+		return false;
+	}
+
+	DEBUG_TRACE("%px: cloned %px to %px\n", ttii, skb, skbc);
+
+	/*
+	 * Get the private cb area and initialise it.
+	 * ALL SEGMENTS HAVE TO HAVE ONE.
+	 */
+	skbc_cb = (struct ecm_tracker_tcp_skb_cb_format *)skbc->cb;
+	DEBUG_SET_MAGIC(skbc_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC);
+
+	/*
+	 * Obtain the IP header from the skb
+	 */
+	if (!ecm_tracker_ip_check_header_and_read(&ip_hdr, skb)) {
+		DEBUG_WARN("%px: no ip_hdr for %px\n", ttii, skbc);
+		dev_kfree_skb_any(skbc);
+		return false;
+	}
+
+	/*
+	 * Extract the TCP header
+	 */
+	tcp_hdr = ecm_tracker_tcp_check_header_and_read(skbc, &ip_hdr, &tcp_hdr_buff);
+	if (!tcp_hdr) {
+		DEBUG_WARN("%px: invalid tcp header %px\n", ttii, skbc);
+		dev_kfree_skb_any(skbc);
+		return false;
+	}
+	ecm_tcp_header = &ip_hdr.headers[ECM_TRACKER_IP_PROTOCOL_TYPE_TCP];
+
+	spin_lock_bh(&ttii->lock);
+
+	/*
+	 * Are we within instance limit?
+	 */
+	DEBUG_ASSERT((ttii->sender_data[ECM_TRACKER_SENDER_TYPE_SRC].recvd_bytes_total + ttii->sender_data[ECM_TRACKER_SENDER_TYPE_DEST].recvd_bytes_total + skbc->truesize) > 0, "%px: bad total\n", ttii);
+	if ((ttii->sender_data[ECM_TRACKER_SENDER_TYPE_SRC].recvd_bytes_total + ttii->sender_data[ECM_TRACKER_SENDER_TYPE_DEST].recvd_bytes_total + skbc->truesize) > ttii->data_limit) {
+		DEBUG_TRACE("%px: over limit: SRC recvd_bytes_total: %u, DEST recvd_bytes_total: %u, skb true_size: %u, limit: %u\n",
+				ttii,
+				ttii->sender_data[ECM_TRACKER_SENDER_TYPE_SRC].recvd_bytes_total,
+				ttii->sender_data[ECM_TRACKER_SENDER_TYPE_DEST].recvd_bytes_total,
+				skbc->truesize,
+				ttii->data_limit);
+		spin_unlock_bh(&ttii->lock);
+		dev_kfree_skb_any(skbc);
+		return false;
+	}
+
+	/*
+	 * Within global limit?
+	 */
+	if (!ecm_tracker_data_total_increase(skbc->len, skbc->truesize)) {
+		DEBUG_TRACE("%px: over global limit\n", ttii);
+		spin_unlock_bh(&ttii->lock);
+		dev_kfree_skb_any(skbc);
+		return false;
+	}
+
+	/*
+	 * Which list?
+	 */
+	data = &ttii->sender_data[sender];
+
+	/*
+	 * Do we have the MSS for this host?  Unlikely as most streams we would have seen the SYN already and retrieved the MSS.
+	 */
+	if (unlikely(tcp_hdr->syn) && unlikely(!data->mss_seen)) {
+		uint16_t mss;
+		if (ecm_tracker_tcp_extract_mss(skbc, &mss, ecm_tcp_header)) {
+			data->mss = mss;
+			data->mss_seen = true;
+			DEBUG_TRACE("%px: Seen mss as %u for %px\n", ttii, mss, data);
+		}
+	}
+
+	/*
+	 * If sequence tracking is enabled but the segment is not wanted then we simply discard it
+	 */
+	if (!_ecm_tracker_tcp_stream_segment_add(ttii, data, &ip_hdr, ecm_tcp_header, tcp_hdr, skbc, skbc_cb)) {
+		spin_unlock_bh(&ttii->lock);
+		ecm_tracker_data_total_decrease(skbc->len, skbc->truesize);
+		dev_kfree_skb_any(skbc);
+
+		/*
+		 * Return true - there is nothing wrong with the datagram we just don't want this datagram but we will still
+		 * allow it to pass and still want to account for it in the connection stats
+		 */
+		return true;
+	}
+
+	/*
+	 * Store the packet in the reception order list.
+	 * NOTE: When sequence tracking is not enabled we want to store things as they are received no matter what.
+	 * When we are sequence tracking we only store the skb when the segment has been added successfully
+	 */
+	skbc_cb->next = NULL;
+	skbc_cb->prev = data->recvd_order_last;
+	data->recvd_order_last = skbc;
+	if (!skbc_cb->prev) {
+		DEBUG_ASSERT(data->recvd_order == NULL, "%px: bad list\n", ttii);
+		data->recvd_order = skbc;
+	} else {
+		struct ecm_tracker_tcp_skb_cb_format *prev_cb;
+		prev_cb = (struct ecm_tracker_tcp_skb_cb_format *)skbc_cb->prev->cb;
+		DEBUG_CHECK_MAGIC(prev_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid cb magic %px\n", ttii, prev_cb);
+		prev_cb->next = skbc;
+	}
+
+	/*
+	 * Update stats
+	 */
+	data->recvd_count++;
+	DEBUG_ASSERT(data->recvd_count > 0, "%px: bad count\n", ttii);
+	data->recvd_bytes_total += skbc->truesize;
+	DEBUG_TRACE("%px: Segment %px added between %px and %px.  recvd total %u, bytes total %u\n",
+			ttii, skbc, skbc->prev, skbc->next, data->recvd_count, data->recvd_bytes_total);
+	spin_unlock_bh(&ttii->lock);
+	return true;
+}
+
+/*
+ * ecm_tracker_tcp_bytes_avail_get_callback()
+ *	Return number of bytes available to read
+ */
+static uint32_t ecm_tracker_tcp_bytes_avail_get_callback(struct ecm_tracker_tcp_instance *tti, ecm_tracker_sender_type_t sender)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)tti;
+	struct ecm_tracker_tcp_host_data *data;
+	uint32_t bytes_avail;
+
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+	DEBUG_ASSERT((sender >= 0) && (sender <= 1), "%px: invalid sender %d\n", ttii, sender);
+
+	/*
+	 * Which list?
+	 */
+	data = &ttii->sender_data[sender];
+
+	/*
+	 * The number of available bytes is our sequence space
+	 */
+	spin_lock_bh(&ttii->lock);
+	bytes_avail = data->num_seqs;
+	spin_unlock_bh(&ttii->lock);
+
+	DEBUG_TRACE("%px: get bytes available for %d: %u\n", ttii, sender, bytes_avail);
+	return bytes_avail;
+}
+
+/*
+ * ecm_tracker_tcp_bytes_read_callback()
+ *	Read a number of bytes
+ */
+static int ecm_tracker_tcp_bytes_read_callback(struct ecm_tracker_tcp_instance *tti, ecm_tracker_sender_type_t sender, uint32_t offset, uint32_t size, void *buffer)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)tti;
+	struct ecm_tracker_tcp_host_data *data;
+	uint32_t read_start_seq;
+	uint32_t seq_offset;
+	uint32_t seg_seq_avail;
+	struct sk_buff *skb;
+	int res;
+	uint8_t *p;
+	struct ecm_tracker_tcp_skb_cb_format *skb_cb;
+
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+	DEBUG_ASSERT((sender >= 0) && (sender <= 1), "%px: invalid sender %d\n", ttii, sender);
+
+	/*
+	 * Which list?
+	 */
+	data = &ttii->sender_data[sender];
+
+	/*
+	 * Compute the sequence to start reading at given the offset
+	 */
+	spin_lock_bh(&ttii->lock);
+	DEBUG_ASSERT((offset + size) <= data->num_seqs, "%px: attempt to read %u bytes from offset %u.  Available bytes is %u\n", ttii, size, offset, data->num_seqs);
+	read_start_seq = data->seq_no + offset;
+	DEBUG_TRACE("%px: seq: %u, num_seqs: %u, offset: %u, size: %u, read_start_seq: %u\n", ttii, data->seq_no, data->num_seqs, offset, size, read_start_seq);
+
+	/*
+	 * Identify which skb in our sequence space seq_start begins at
+	 */
+	skb = data->in_order;
+	while (skb) {
+		uint32_t next_seg_seq;
+
+		skb_cb = (struct ecm_tracker_tcp_skb_cb_format *)skb->cb;
+		DEBUG_CHECK_MAGIC(skb_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid cb magic %px\n", ttii, skb_cb);
+
+		/*
+		 * Get the sequence number of the start of the next segment
+		 */
+		next_seg_seq = skb_cb->seq_no + skb_cb->num_seqs;
+
+		/*
+		 * If the point at which we start reading is at or greater then the next segment sequence then we need to advance onto that
+		 * i.e. skb does not contain the sequences we need
+		 */
+		if (read_start_seq >= next_seg_seq) {
+			DEBUG_TRACE("%px: skip skb %px, we start at %u and this segment ends at %u\n", ttii, skb, read_start_seq, next_seg_seq - 1);
+			skb = skb->next;
+			continue;
+		}
+
+		/*
+		 * We start reading at this skb
+		 */
+		DEBUG_TRACE("%px: skb to start reading from is at %px, seq_no of this is %u\n", ttii, skb, skb_cb->seq_no);
+		break;
+	}
+
+	DEBUG_ASSERT(skb, "%px: no read start could be found\n", ttii);
+
+	/*
+	 * Finally perform read
+	 */
+
+	/*
+	 * We may need to apply an offset to the first skb to get to our seq_start point
+	 */
+	seq_offset = read_start_seq - skb_cb->seq_no;
+	seg_seq_avail = skb_cb->num_seqs - seq_offset;
+	DEBUG_TRACE("%px: seq_offset: %u, avail: %u, want %u bytes\n", ttii, seq_offset, seg_seq_avail, size);
+	if (seg_seq_avail > size) {
+		seg_seq_avail = size;
+	}
+
+	/*
+	 * Read that data.
+	 */
+	p = (uint8_t *)buffer;
+	res = skb_copy_bits(skb, skb_cb->offset + seq_offset, p, seg_seq_avail);
+	if (res < 0) {
+		spin_unlock_bh(&ttii->lock);
+		return res;
+	}
+	p += seg_seq_avail;
+	size -= seg_seq_avail;
+
+	/*
+	 * Read bytes
+	 */
+	while (size) {
+		uint32_t read_seq;
+
+		skb = skb->next;
+		DEBUG_ASSERT(skb, "%px: size %u not zero but no skb\n", ttii, size);
+
+		skb_cb = (struct ecm_tracker_tcp_skb_cb_format *)skb->cb;
+		DEBUG_CHECK_MAGIC(skb_cb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid cb magic %px\n", ttii, skb_cb);
+
+		/*
+		 * Read available bytes from this segment.
+		 * No offset here as it's linear all the way from this point on.
+		 */
+		read_seq = skb_cb->num_seqs;
+		if (read_seq > size) {
+			read_seq = size;
+		}
+
+		DEBUG_TRACE("%px: Read %u sequences from seq_no %u\n", ttii, read_seq, skb_cb->seq_no);
+
+		res = skb_copy_bits(skb, skb_cb->offset, p, read_seq);
+		if (res < 0) {
+			spin_unlock_bh(&ttii->lock);
+			return res;
+		}
+		p += read_seq;
+		size -= read_seq;
+	}
+
+	spin_unlock_bh(&ttii->lock);
+	return 0;
+}
+
+/*
+ * ecm_tracker_tcp_mss_get_callback()
+ *	Get the MSS as sent BY the given target i.e. the MSS the other party is allowed to send
+ *
+ * Returns true if the MSS was seen in a SYN or false is system default
+ */
+static bool ecm_tracker_tcp_mss_get_callback(struct ecm_tracker_tcp_instance *tti, ecm_tracker_sender_type_t sender, uint16_t *mss)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)tti;
+	struct ecm_tracker_tcp_host_data *data;
+	bool res;
+
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+	DEBUG_ASSERT((sender >= 0) && (sender <= 1), "%px: invalid sender %d\n", ttii, sender);
+
+	/*
+	 * Which list?
+	 */
+	data = &ttii->sender_data[sender];
+
+	spin_lock_bh(&ttii->lock);
+	*mss = data->mss;
+	res = data->mss_seen;
+	spin_unlock_bh(&ttii->lock);
+
+	DEBUG_TRACE("%px: get mss for %d: %u, seen? %u\n", ttii, sender, *mss, res);
+
+	return res;
+}
+
+/*
+ * ecm_tracker_tcp_data_total_get_callback()
+ *	Return total tracked data
+ */
+static int32_t ecm_tracker_tcp_data_total_get_callback(struct ecm_tracker_instance *ti)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)ti;
+	int32_t data_total;
+
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+
+	spin_lock_bh(&ttii->lock);
+	data_total = ttii->sender_data[ECM_TRACKER_SENDER_TYPE_SRC].recvd_bytes_total + ttii->sender_data[ECM_TRACKER_SENDER_TYPE_DEST].recvd_bytes_total;
+	spin_unlock_bh(&ttii->lock);
+
+	return data_total;
+}
+
+/*
+ * ecm_tracker_tcp_data_limit_get_callback()
+ *	Get tracked data limit
+ */
+static int32_t ecm_tracker_tcp_data_limit_get_callback(struct ecm_tracker_instance *ti)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)ti;
+	int32_t data_limit;
+
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+
+	spin_lock_bh(&ttii->lock);
+	data_limit = ttii->data_limit;
+	spin_unlock_bh(&ttii->lock);
+
+	return data_limit;
+}
+
+/*
+ * ecm_tracker_tcp_data_limit_set_callback()
+ *	Set tracked data limit
+ */
+static void ecm_tracker_tcp_data_limit_set_callback(struct ecm_tracker_instance *ti, int32_t data_limit)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)ti;
+
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+
+	spin_lock_bh(&ttii->lock);
+	ttii->data_limit = data_limit;
+	spin_unlock_bh(&ttii->lock);
+}
+#endif
+
+/*
+ * ecm_tracker_tcp_state_update_callback()
+ * 	Update connection state based on the knowledge we have and the skb given
+ */
+static void ecm_tracker_tcp_state_update_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)ti;
+	struct tcphdr tcp_hdr_buff;
+	struct tcphdr *tcp_hdr;
+	struct ecm_tracker_tcp_sender_state *sender_state;
+	struct ecm_tracker_tcp_sender_state *peer_state;
+
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+
+	/*
+	 * Get refereces to states
+	 */
+	DEBUG_ASSERT((sender >= 0) && (sender <= 1), "%px: invalid sender %d\n", ttii, sender);
+	sender_state = &ttii->sender_states[sender];
+	peer_state = &ttii->sender_states[!sender];
+
+	/*
+	 * Get tcp header
+	 */
+	tcp_hdr = ecm_tracker_tcp_check_header_and_read(skb, ip_hdr, &tcp_hdr_buff);
+	if (unlikely(!tcp_hdr)) {
+		DEBUG_WARN("%px: no tcp_hdr for %px\n", ttii, skb);
+		spin_lock_bh(&ttii->lock);
+		sender_state->state = ECM_TRACKER_SENDER_STATE_FAULT;
+		peer_state->state = ECM_TRACKER_SENDER_STATE_FAULT;
+		spin_unlock_bh(&ttii->lock);
+		return;
+	}
+
+	/*
+	 * If either side reports a reset this is catastrophic for the connection
+	 */
+	if (unlikely(tcp_hdr->rst)) {
+		DEBUG_INFO("%px: RESET\n", ttii);
+		spin_lock_bh(&ttii->lock);
+		sender_state->state = ECM_TRACKER_SENDER_STATE_FAULT;
+		peer_state->state = ECM_TRACKER_SENDER_STATE_FAULT;
+		spin_unlock_bh(&ttii->lock);
+		return;
+	}
+
+	/*
+	 * Likely ack is set - this constitutes the mainstay of a TCP connection
+	 * The sending of an ack may put the other side of the connection into a different state
+	 */
+	spin_lock_bh(&ttii->lock);
+	if (likely(tcp_hdr->ack)) {
+		ecm_tracker_sender_state_t peer_state_current = peer_state->state;
+		uint32_t ack_seq = ntohl(tcp_hdr->ack_seq);
+
+		switch (peer_state_current) {
+		case ECM_TRACKER_SENDER_STATE_UNKNOWN: {
+			/*
+			 * Looks like we came into this connection mid-flow.
+			 * Flag that the peer is established which is all we can infer right now and
+			 * initialise the peers SYN sequence for further analysis of sequence space.
+			 */
+			peer_state->state = ECM_TRACKER_SENDER_STATE_ESTABLISHED;
+			peer_state->syn_seq = (ack_seq - 1);		/* -1 is because the ACK has ack'd our ficticious SYN */
+			DEBUG_INFO("%px: From unkown to established, ack_seq: %u, syn_seq: %u\n", ttii, ack_seq, peer_state->syn_seq);
+			break;
+		}
+		case ECM_TRACKER_SENDER_STATE_ESTABLISHING: {
+			int32_t ackd;
+			uint32_t syn_seq;
+
+			syn_seq = peer_state->syn_seq;
+			ackd = (int32_t)(ack_seq - syn_seq);
+			DEBUG_TRACE("%px: ack %u for syn_seq %u? ackd = %d\n", ttii, ack_seq, syn_seq, ackd);
+
+			if (ackd <= 0) {
+				DEBUG_TRACE("%px: No change\n", ttii);
+			} else {
+				DEBUG_INFO("%px: Established\n", ttii);
+				peer_state->state = ECM_TRACKER_SENDER_STATE_ESTABLISHED;
+			}
+			break;
+		}
+		case ECM_TRACKER_SENDER_STATE_CLOSING: {
+			int32_t ackd;
+			uint32_t fin_seq;
+
+			fin_seq = peer_state->fin_seq;
+			ackd = (int32_t)(ack_seq - fin_seq);
+			DEBUG_TRACE("%px: ack %u for fin_seq %u? ackd = %d\n", ttii, ack_seq, fin_seq, ackd);
+
+			if (ackd <= 0) {
+				DEBUG_TRACE("%px: No change\n", ttii);
+			} else {
+				DEBUG_TRACE("%px: Closed\n", ttii);
+				peer_state->state = ECM_TRACKER_SENDER_STATE_CLOSED;
+			}
+			break;
+		}
+		case ECM_TRACKER_SENDER_STATE_ESTABLISHED:
+		case ECM_TRACKER_SENDER_STATE_CLOSED:
+		case ECM_TRACKER_SENDER_STATE_FAULT:
+			/*
+			 * No change
+			 */
+			break;
+		default:
+			DEBUG_ASSERT(false, "%px: unhandled state: %d\n", ttii, peer_state_current);
+		}
+	}
+
+	/*
+	 * Handle control flags sent by the sender (SYN & FIN)
+	 * Handle SYN first because, in sequence space, SYN is first.
+	 */
+	if (tcp_hdr->syn) {
+		ecm_tracker_sender_state_t sender_state_current = sender_state->state;
+		uint32_t seq = ntohl(tcp_hdr->seq);
+
+		switch (sender_state_current) {
+		case ECM_TRACKER_SENDER_STATE_UNKNOWN:
+			sender_state->state = ECM_TRACKER_SENDER_STATE_ESTABLISHING;
+			sender_state->syn_seq = seq;		/* Seq is the sequence number of the SYN */
+			DEBUG_INFO("%px: From unkown to establishing, syn_seq: %u\n", ttii, sender_state->syn_seq);
+			break;
+		case ECM_TRACKER_SENDER_STATE_CLOSING:
+		case ECM_TRACKER_SENDER_STATE_CLOSED:
+			/*
+			 * SYN after seeing a FIN?  FAULT!
+			 */
+			sender_state->state = ECM_TRACKER_SENDER_STATE_FAULT;
+			DEBUG_INFO("%px: SYN after FIN - fault\n", ttii);
+			break;
+		case ECM_TRACKER_SENDER_STATE_ESTABLISHED:
+			/*
+			 * SYN when established is just a duplicate down to syn/ack timing subtleties
+			 */
+		case ECM_TRACKER_SENDER_STATE_ESTABLISHING:
+		case ECM_TRACKER_SENDER_STATE_FAULT:
+			/*
+			 * No change
+			 */
+			break;
+		default:
+			DEBUG_ASSERT(false, "%px: unhandled state: %d\n", ttii, sender_state_current);
+		}
+	}
+
+	if (tcp_hdr->fin) {
+		ecm_tracker_sender_state_t sender_state_current = sender_state->state;
+		uint32_t seq = ntohl(tcp_hdr->seq);
+
+		switch (sender_state_current) {
+		case ECM_TRACKER_SENDER_STATE_UNKNOWN:
+			/*
+			 * Looks like we joined mid-flow.
+			 * Have to set up both SYN and FIN.
+			 * NOTE: It's possible that SYN is in the same packet as FIN, account for that in the seq numbers
+			 */
+			sender_state->state = ECM_TRACKER_SENDER_STATE_CLOSING;
+			if (tcp_hdr->syn) {
+				sender_state->syn_seq = seq;
+				sender_state->fin_seq = seq + 1;
+			} else {
+				sender_state->fin_seq = seq;		/* seq is the FIN sequence */
+				sender_state->syn_seq = seq - 1;	/* Make a guess at what the SYN was */
+			}
+			DEBUG_INFO("%px: From unkown to closing, syn_seq: %u, fin_seq: %u\n", ttii, sender_state->syn_seq, sender_state->fin_seq);
+			break;
+		case ECM_TRACKER_SENDER_STATE_ESTABLISHED:
+			/*
+			 * Connection becomes closing.
+			 */
+			sender_state->state = ECM_TRACKER_SENDER_STATE_CLOSING;
+			sender_state->fin_seq = seq;
+			DEBUG_INFO("%px: From established to closing, fin_seq: %u\n", ttii, sender_state->fin_seq);
+			break;
+		case ECM_TRACKER_SENDER_STATE_ESTABLISHING: {
+			int32_t newer;
+
+			/*
+			 * FIN while waiting for SYN to be acknowledged is possible but only if it
+			 * it is in the same packet or later sequence space
+			 */
+			newer = (int32_t)(seq - sender_state->syn_seq);
+			if (!tcp_hdr->syn || (newer <= 0)) {
+				DEBUG_INFO("%px: From establishing to fault - odd FIN seen, syn: %u, syn_seq: %u, newer: %d\n",
+						ttii, tcp_hdr->syn, sender_state->syn_seq, newer);
+				sender_state->state = ECM_TRACKER_SENDER_STATE_FAULT;
+			} else {
+				uint32_t fin_seq = seq;
+				if (tcp_hdr->syn) {
+					fin_seq++;
+				}
+				sender_state->state = ECM_TRACKER_SENDER_STATE_CLOSING;
+				DEBUG_INFO("%px: From establishing to closing, syn: %u, syn_seq: %u, fin_seq: %u\n",
+						ttii, tcp_hdr->syn, sender_state->syn_seq, sender_state->fin_seq);
+			}
+			break;
+		}
+		case ECM_TRACKER_SENDER_STATE_CLOSING:
+		case ECM_TRACKER_SENDER_STATE_CLOSED:
+		case ECM_TRACKER_SENDER_STATE_FAULT:
+			/*
+			 * No change
+			 */
+			break;
+		default:
+			DEBUG_ASSERT(false, "%px: unhandled state: %d\n", ttii, sender_state_current);
+		}
+	}
+
+	spin_unlock_bh(&ttii->lock);
+}
+
+/*
+ * ecm_tracker_tcp_state_get_callback()
+ * 	Get state
+ */
+static void ecm_tracker_tcp_state_get_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_state_t *src_state,
+					ecm_tracker_sender_state_t *dest_state, ecm_tracker_connection_state_t *state, ecm_db_timer_group_t *tg)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)ti;
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+	spin_lock_bh(&ttii->lock);
+	*src_state = ttii->sender_states[ECM_TRACKER_SENDER_TYPE_SRC].state;
+	*dest_state = ttii->sender_states[ECM_TRACKER_SENDER_TYPE_DEST].state;
+	spin_unlock_bh(&ttii->lock);
+	*state = ecm_tracker_tcp_connection_state_matrix[*src_state][*dest_state];
+	*tg = ecm_tracker_tcp_timer_group_from_state[*state];
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_tracker_tcp_sender_state_get()
+ *	Return state
+ */
+static int ecm_tracker_tcp_sender_state_get(struct ecm_state_file_instance *sfi, ecm_tracker_sender_type_t sender,
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+						struct ecm_tracker_tcp_host_data *data,
+#endif
+						struct ecm_tracker_tcp_sender_state *state)
+{
+	int result;
+
+	if ((result = ecm_state_write(sfi, "state", "%s", ecm_tracker_sender_state_to_string(state->state)))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "syn_seq", "%u", state->syn_seq))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "fin_seq", "%u", state->fin_seq))) {
+		return result;
+	}
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	if ((result = ecm_state_write(sfi, "mss_seen", "%s", (data->mss_seen)? "yes" : "no"))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "mss", "%u", data->mss))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "seq_no", "%u", data->seq_no))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "num_seqs", "%u", data->num_seqs))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "seq_valid", "%s", (data->seq_no_valid)? "yes" : "no"))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "bytes_total", "%d", data->recvd_bytes_total))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "buffers_total", "%d", data->recvd_count))) {
+		return result;
+	}
+#endif
+	return 0;
+}
+
+/*
+ * ecm_tracker_tcp_state_text_get_callback()
+ *	Return state
+ */
+static int ecm_tracker_tcp_state_text_get_callback(struct ecm_tracker_instance *ti, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)ti;
+	struct ecm_tracker_tcp_sender_state sender_states[ECM_TRACKER_SENDER_MAX];
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	struct ecm_tracker_tcp_host_data sender_data[ECM_TRACKER_SENDER_MAX];
+	int32_t data_limit;
+#endif
+	ecm_tracker_connection_state_t connection_state;
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+
+	if ((result = ecm_state_prefix_add(sfi, "tracker_tcp"))) {
+		return result;
+	}
+
+	/*
+	 * Capture state
+	 */
+	spin_lock_bh(&ttii->lock);
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	data_limit = ttii->data_limit;
+	sender_data[ECM_TRACKER_SENDER_TYPE_SRC] = ttii->sender_data[ECM_TRACKER_SENDER_TYPE_SRC];
+	sender_data[ECM_TRACKER_SENDER_TYPE_DEST] = ttii->sender_data[ECM_TRACKER_SENDER_TYPE_DEST];
+#endif
+	sender_states[ECM_TRACKER_SENDER_TYPE_SRC] = ttii->sender_states[ECM_TRACKER_SENDER_TYPE_SRC];
+	sender_states[ECM_TRACKER_SENDER_TYPE_DEST] = ttii->sender_states[ECM_TRACKER_SENDER_TYPE_DEST];
+	spin_unlock_bh(&ttii->lock);
+	connection_state = ecm_tracker_tcp_connection_state_matrix[sender_states[ECM_TRACKER_SENDER_TYPE_SRC].state][sender_states[ECM_TRACKER_SENDER_TYPE_DEST].state];
+
+	if ((result = ecm_state_write(sfi, "connection_state", "%s", ecm_tracker_connection_state_to_string(connection_state)))) {
+		return result;
+	}
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	if ((result = ecm_state_write(sfi, "data_limit", "%d", data_limit))) {
+		return result;
+	}
+#endif
+
+	if ((result = ecm_state_prefix_add(sfi, "senders"))) {
+		return result;
+	}
+
+	/*
+	 * Output src sender
+	 */
+	if ((result = ecm_state_prefix_add(sfi, "src"))) {
+		return result;
+	}
+	if ((result = ecm_tracker_tcp_sender_state_get(sfi,
+			ECM_TRACKER_SENDER_TYPE_SRC,
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+			&sender_data[ECM_TRACKER_SENDER_TYPE_SRC],
+#endif
+			&sender_states[ECM_TRACKER_SENDER_TYPE_SRC]))) {
+		return result;
+	}
+	if ((result = ecm_state_prefix_remove(sfi))) {
+		return result;
+	}
+
+	/*
+	 * Output dest sender
+	 */
+	if ((result = ecm_state_prefix_add(sfi, "dest"))) {
+		return result;
+	}
+	if ((result = ecm_tracker_tcp_sender_state_get(sfi,
+			ECM_TRACKER_SENDER_TYPE_DEST,
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+			&sender_data[ECM_TRACKER_SENDER_TYPE_DEST],
+#endif
+			&sender_states[ECM_TRACKER_SENDER_TYPE_DEST]))) {
+		return result;
+	}
+	if ((result = ecm_state_prefix_remove(sfi))) {
+		return result;
+	}
+
+	if ((result = ecm_state_prefix_remove(sfi))) {
+		return result;
+	}
+
+ 	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+/*
+ * ecm_tracker_tcp_init()
+ *	Initialise the instance
+ */
+void ecm_tracker_tcp_init(struct ecm_tracker_tcp_instance *tti, int32_t data_limit, uint16_t mss_src_default, uint16_t mss_dest_default)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)tti;
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+	DEBUG_TRACE("%px: init host addresses src mss: %d, dest mss: %d\n", ttii, mss_src_default, mss_dest_default);
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	spin_lock_bh(&ttii->lock);
+	ttii->data_limit = data_limit;
+	ttii->sender_data[ECM_TRACKER_SENDER_TYPE_SRC].mss = mss_src_default;
+	ttii->sender_data[ECM_TRACKER_SENDER_TYPE_DEST].mss = mss_dest_default;
+	spin_unlock_bh(&ttii->lock);
+#endif
+}
+EXPORT_SYMBOL(ecm_tracker_tcp_init);
+
+/*
+ * ecm_tracker_tcp_alloc()
+ */
+struct ecm_tracker_tcp_instance *ecm_tracker_tcp_alloc(void)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii;
+
+	ttii = (struct ecm_tracker_tcp_internal_instance *)kzalloc(sizeof(struct ecm_tracker_tcp_internal_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!ttii) {
+		DEBUG_WARN("Failed to allocate tcp tracker instance\n");
+		return NULL;
+	}
+
+	ttii->tcp_base.base.ref = ecm_tracker_tcp_ref_callback;
+	ttii->tcp_base.base.deref = ecm_tracker_tcp_deref_callback;
+	ttii->tcp_base.base.state_update = ecm_tracker_tcp_state_update_callback;
+	ttii->tcp_base.base.state_get = ecm_tracker_tcp_state_get_callback;
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	ttii->tcp_base.base.datagram_count_get = ecm_tracker_tcp_datagram_count_get_callback;
+	ttii->tcp_base.base.datagram_discard = ecm_tracker_tcp_datagram_discard_callback;
+	ttii->tcp_base.base.datagram_read = ecm_tracker_tcp_datagram_read_callback;
+	ttii->tcp_base.base.datagram_size_get = ecm_tracker_tcp_datagram_size_get_callback;
+	ttii->tcp_base.base.datagram_add = ecm_tracker_tcp_datagram_add_callback;
+	ttii->tcp_base.base.discard_all = ecm_tracker_tcp_discard_all_callback;
+	ttii->tcp_base.base.data_total_get = ecm_tracker_tcp_data_total_get_callback;
+	ttii->tcp_base.base.data_limit_get = ecm_tracker_tcp_data_limit_get_callback;
+	ttii->tcp_base.base.data_limit_set = ecm_tracker_tcp_data_limit_set_callback;
+
+	ttii->tcp_base.bytes_avail_get = ecm_tracker_tcp_bytes_avail_get_callback;
+	ttii->tcp_base.bytes_read = ecm_tracker_tcp_bytes_read_callback;
+	ttii->tcp_base.bytes_discard = ecm_tracker_tcp_bytes_discard_callback;
+	ttii->tcp_base.mss_get = ecm_tracker_tcp_mss_get_callback;
+	ttii->tcp_base.segment_add = ecm_tracker_tcp_segment_add_callback;
+#endif
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ttii->tcp_base.base.state_text_get = ecm_tracker_tcp_state_text_get_callback;
+#endif
+
+	spin_lock_init(&ttii->lock);
+
+	ttii->refs = 1;
+	DEBUG_SET_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC);
+
+	spin_lock_bh(&ecm_tracker_tcp_lock);
+	ecm_tracker_tcp_count++;
+	DEBUG_ASSERT(ecm_tracker_tcp_count > 0, "%px: tcp tracker count wrap\n", ttii);
+	spin_unlock_bh(&ecm_tracker_tcp_lock);
+
+	DEBUG_TRACE("TCP tracker created %px\n", ttii);
+	return (struct ecm_tracker_tcp_instance *)ttii;
+}
+EXPORT_SYMBOL(ecm_tracker_tcp_alloc);
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+/*
+ * ecm_tracker_tcp_reader_fwd_read_u8()
+ *	Read a byte, advancing the read position
+ */
+uint8_t ecm_tracker_tcp_reader_fwd_read_u8(struct ecm_tracker_tcp_reader_instance *tri)
+{
+	uint8_t b;
+
+	DEBUG_CHECK_MAGIC(tri, ECM_TRACKER_TCP_READER_INSTANCE_MAGIC, "%px: magic failed", tri);
+
+	spin_lock_bh(&tri->lock);
+	spin_lock_bh(&tri->ttii->lock);
+
+	/*
+	 * Do we need to advance onto the next segment?  Unlikely as most segments contain a lot more than 1 byte of data.
+	 */
+	if (unlikely(tri->segment_remain == 0)) {
+		if (likely(tri->segment)) {
+			tri->segment = tri->segment->next;
+		} else {
+			/*
+			 * Initialise segment to allow the walking of the in_order list
+			 */
+			tri->segment = tri->data->in_order;
+		}
+		DEBUG_ASSERT(tri->segment, "%px: attempt to read past end of stream\n", tri);
+
+		tri->segment_dcb = (struct ecm_tracker_tcp_skb_cb_format *)tri->segment->cb;
+		DEBUG_CHECK_MAGIC(tri->segment_dcb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid magic for cb %px\n", tri, tri->segment_dcb);
+
+		tri->segment_remain = tri->segment_dcb->num_seqs;
+		tri->segment_offset = tri->segment_dcb->offset;
+
+		DEBUG_TRACE("%px: Advance to next segment %px, segment remain: %u, segment offset: %u\n",
+				tri, tri->segment, tri->segment_remain, tri->segment_offset);
+		DEBUG_ASSERT(tri->segment_remain, "%px: Next segment has no data\n", tri);
+	}
+
+	/*
+	 * Read byte
+	 */
+	skb_copy_bits(tri->segment, tri->segment_offset, &b, 1);
+	tri->segment_offset++;
+	tri->segment_remain--;
+	tri->offset++;
+
+	spin_unlock_bh(&tri->ttii->lock);
+	spin_unlock_bh(&tri->lock);
+
+	return b;
+}
+EXPORT_SYMBOL(ecm_tracker_tcp_reader_fwd_read_u8);
+
+/*
+ * _ecm_tracker_tcp_reader_retreat()
+ *	Retreat reading position by number of bytes.
+ *
+ * This function CANNOT advance.
+ */
+static void _ecm_tracker_tcp_reader_retreat(struct ecm_tracker_tcp_reader_instance *tri, uint32_t retreatment)
+{
+	while (retreatment) {
+		uint32_t seg_prior_data;
+
+		/*
+		 * Identify how much DATA precedes our current tri->segment_offset.
+		 * This tells us how much data we can retreat over before having to move onto the prior segment
+		 */
+		seg_prior_data = tri->segment_offset - tri->segment_dcb->offset;
+		DEBUG_TRACE("%px: Retreat %u, data_offs %u\n", tri, retreatment, seg_prior_data);
+
+		/*
+		 * Is there enough prior data in the current segment to satisfy the retreat?
+		 */
+		if (retreatment <= seg_prior_data) {
+			tri->segment_remain += retreatment;
+			tri->segment_offset -= retreatment;
+			DEBUG_TRACE("%px: retreat completed seg_remain %u, seg offset %u\n", tri, tri->segment_remain, tri->segment_offset);
+			return;
+		}
+
+		retreatment -= seg_prior_data;
+
+		/*
+		 * Move onto previous actual segment
+		 */
+		tri->segment = tri->segment->prev;
+		DEBUG_ASSERT(tri->segment, "%px: attempt to read past start of stream\n", tri);
+
+		tri->segment_dcb = (struct ecm_tracker_tcp_skb_cb_format *)tri->segment->cb;
+		DEBUG_CHECK_MAGIC(tri->segment_dcb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid magic for cb %px\n", tri, tri->segment_dcb);
+
+		/*
+		 * Position at the end of the previous segment
+		 */
+		tri->segment_remain = 0;
+		tri->segment_offset = tri->segment_dcb->num_seqs + tri->segment_dcb->offset;
+
+		DEBUG_TRACE("%px: advanvcement now %u this seg_remain %u, this seg_offset %u\n",
+				tri, retreatment, tri->segment_remain, tri->segment_offset);
+	}
+}
+
+/*
+ * ecm_tracker_tcp_reader_retreat()
+ *	Retreat reading position by number of bytes
+ */
+void ecm_tracker_tcp_reader_retreat(struct ecm_tracker_tcp_reader_instance *tri, uint32_t retreatment)
+{
+	DEBUG_CHECK_MAGIC(tri, ECM_TRACKER_TCP_READER_INSTANCE_MAGIC, "%px: magic failed", tri);
+
+	spin_lock_bh(&tri->lock);
+	spin_lock_bh(&tri->ttii->lock);
+
+	DEBUG_ASSERT(tri->segment, "%px: segment pointer invalid\n", tri);
+	_ecm_tracker_tcp_reader_retreat(tri, retreatment);
+	tri->offset -= retreatment;
+
+	spin_unlock_bh(&tri->ttii->lock);
+	spin_unlock_bh(&tri->lock);
+}
+EXPORT_SYMBOL(ecm_tracker_tcp_reader_retreat);
+
+/*
+ * _ecm_tracker_tcp_reader_advance()
+ *	Advance reading position by number of bytes.
+ *
+ * This function CANNOT retreat.
+ */
+static void _ecm_tracker_tcp_reader_advance(struct ecm_tracker_tcp_reader_instance *tri, uint32_t advancement)
+{
+	while (advancement) {
+		DEBUG_TRACE("%px: Advance %u\n", tri, advancement);
+		if (advancement <= tri->segment_remain) {
+			tri->segment_remain -= advancement;
+			tri->segment_offset += advancement;
+			DEBUG_TRACE("%px: advanvce completed seg_remain %u, seg offset %u\n", tri, tri->segment_remain, tri->segment_offset);
+			return;
+		}
+
+		advancement -= tri->segment_remain;
+
+		/*
+		 * Move onto next actual segment
+		 */
+		if (likely(tri->segment)) {
+			tri->segment = tri->segment->next;
+		} else {
+			/*
+			 * Initialise segment to allow the walking of the in_order list
+			 */
+			tri->segment = tri->data->in_order;
+		}
+		DEBUG_ASSERT(tri->segment, "%px: attempt to read past end of stream\n", tri);
+
+		tri->segment_dcb = (struct ecm_tracker_tcp_skb_cb_format *)tri->segment->cb;
+		DEBUG_CHECK_MAGIC(tri->segment_dcb, ECM_TRACKER_TCP_SKB_CB_MAGIC, "%px: invalid magic for cb %px\n", tri, tri->segment_dcb);
+
+		tri->segment_remain = tri->segment_dcb->num_seqs;
+		tri->segment_offset = tri->segment_dcb->offset;
+
+		DEBUG_TRACE("%px: advanvcement now %u this seg_remain %u, this seg_offset %u\n",
+				tri, advancement, tri->segment_remain, tri->segment_offset);
+	}
+}
+
+/*
+ * ecm_tracker_tcp_reader_advance()
+ *	Advance reading position by number of bytes
+ */
+void ecm_tracker_tcp_reader_advance(struct ecm_tracker_tcp_reader_instance *tri, uint32_t advancement)
+{
+	DEBUG_CHECK_MAGIC(tri, ECM_TRACKER_TCP_READER_INSTANCE_MAGIC, "%px: magic failed", tri);
+
+	spin_lock_bh(&tri->lock);
+	spin_lock_bh(&tri->ttii->lock);
+
+	_ecm_tracker_tcp_reader_advance(tri, advancement);
+	tri->offset += advancement;
+
+	spin_unlock_bh(&tri->ttii->lock);
+	spin_unlock_bh(&tri->lock);
+}
+EXPORT_SYMBOL(ecm_tracker_tcp_reader_advance);
+
+/*
+ * ecm_tracker_tcp_reader_position_get()
+ *	Return the current reading position
+ *
+ * NOTE: position is always referenced from the ORIGINAL 0, EVEN AFTER discarding bytes.
+ * For example, calling:
+ * _position_set(50)
+ * _discard_preceding()
+ * _position_get() WILL RETURN 50
+ * I.e. positions are not shifted left by a discarded operation.
+ * This is so that once a stream is parsed and positions known, data can be discarded without
+ * having to recalculate all notions of positions.
+ */
+uint32_t ecm_tracker_tcp_reader_position_get(struct ecm_tracker_tcp_reader_instance *tri)
+{
+	uint32_t pos;
+
+	DEBUG_CHECK_MAGIC(tri, ECM_TRACKER_TCP_READER_INSTANCE_MAGIC, "%px: magic failed", tri);
+
+	spin_lock_bh(&tri->lock);
+	pos = tri->offset;
+	spin_unlock_bh(&tri->lock);
+	return pos;
+}
+EXPORT_SYMBOL(ecm_tracker_tcp_reader_position_get);
+
+/*
+ * ecm_tracker_tcp_reader_remain_get()
+ *	Return the available bytes to be read from the current position
+ */
+uint32_t ecm_tracker_tcp_reader_remain_get(struct ecm_tracker_tcp_reader_instance *tri)
+{
+	uint32_t remain;
+
+	DEBUG_CHECK_MAGIC(tri, ECM_TRACKER_TCP_READER_INSTANCE_MAGIC, "%px: magic failed", tri);
+
+	spin_lock_bh(&tri->lock);
+	spin_lock_bh(&tri->ttii->lock);
+	remain = tri->data->num_seqs - (tri->offset - tri->discarded);
+	spin_unlock_bh(&tri->ttii->lock);
+	spin_unlock_bh(&tri->lock);
+	return remain;
+}
+EXPORT_SYMBOL(ecm_tracker_tcp_reader_remain_get);
+
+/*
+ * ecm_tracker_tcp_reader_position_set()
+ *	Set the reading position as an offset from the start
+ */
+void ecm_tracker_tcp_reader_position_set(struct ecm_tracker_tcp_reader_instance *tri, uint32_t offset)
+{
+	int32_t delta;
+
+	DEBUG_CHECK_MAGIC(tri, ECM_TRACKER_TCP_READER_INSTANCE_MAGIC, "%px: magic failed", tri);
+
+	DEBUG_TRACE("%px: Position set %u\n", tri, offset);
+
+	spin_lock_bh(&tri->lock);
+	spin_lock_bh(&tri->ttii->lock);
+
+	/*
+	 * Is this a retreat or an advance?
+	 */
+	delta = (int32_t)(offset - tri->offset);
+	DEBUG_TRACE("%px: Position set delta %d\n", tri, delta);
+	if (delta <= 0) {
+		_ecm_tracker_tcp_reader_retreat(tri, -delta);
+	} else {
+		_ecm_tracker_tcp_reader_advance(tri, delta);
+	}
+	tri->offset = offset;
+
+	spin_unlock_bh(&tri->ttii->lock);
+	spin_unlock_bh(&tri->lock);
+}
+EXPORT_SYMBOL(ecm_tracker_tcp_reader_position_set);
+
+/*
+ * ecm_tracker_tcp_reader_discard_preceding()
+ *	Discard bytes from beginning of available data before the reader position
+ *
+ * NOTE: After discarding you DO NOT have to modify your notions of positions i.e. position X is still position X to you.
+ * Obviously deleted positions are no longer valid but positions that have not been discarded remain valid.
+ */
+void ecm_tracker_tcp_reader_discard_preceding(struct ecm_tracker_tcp_reader_instance *tri)
+{
+	uint32_t discard;
+
+	DEBUG_CHECK_MAGIC(tri, ECM_TRACKER_TCP_READER_INSTANCE_MAGIC, "%px: magic failed", tri);
+
+	/*
+	 * Discard all bytes preceding our offset
+	 */
+	spin_lock_bh(&tri->lock);
+	discard = tri->offset - tri->discarded;
+	tri->discarded += discard;
+
+	/*
+	 * If the reader position is at the end of a segment then the tri->segment is going to be ripped from
+	 * under the reader.
+	 */
+	if (!tri->segment_remain) {
+		/*
+		 * By setting the segment to null we effectively cause a re-init of the tri->segment on the next operation
+		 */
+		DEBUG_TRACE("%px: Discarding when segment_remain is 0 - causing re-init of tri->segment on next oper\n", tri);
+		tri->segment = NULL;
+	}
+
+	spin_unlock_bh(&tri->lock);
+
+	/*
+	 * Discard the actual bytes in the tracker
+	 */
+	DEBUG_TRACE("%px: discard_preceding %u bytes\n", tri, discard);
+	ecm_tracker_tcp_bytes_discard(tri->ttii, tri->data, discard);
+}
+EXPORT_SYMBOL(ecm_tracker_tcp_reader_discard_preceding);
+
+/*
+ * ecm_tracker_tcp_reader_init()
+ */
+void ecm_tracker_tcp_reader_init(struct ecm_tracker_tcp_reader_instance *tri, struct ecm_tracker_tcp_instance *tti, ecm_tracker_sender_type_t sender)
+{
+	struct ecm_tracker_tcp_internal_instance *ttii = (struct ecm_tracker_tcp_internal_instance *)tti;
+	struct ecm_tracker_tcp_host_data *data;
+
+	DEBUG_CHECK_MAGIC(tri, ECM_TRACKER_TCP_READER_INSTANCE_MAGIC, "%px: magic failed", tri);
+	DEBUG_CHECK_MAGIC(ttii, ECM_TRACKER_TCP_INSTANCE_MAGIC, "%px: magic failed", ttii);
+	DEBUG_ASSERT((sender >= 0) && (sender <= 1), "%px: invalid sender %d\n", tri, sender);
+
+	/*
+	 * Take a reference to the tcp tracker
+	 */
+	((struct ecm_tracker_instance *)tti)->ref((struct ecm_tracker_instance *)tti);
+
+	/*
+	 * Get a pointer to the host data
+	 */
+	data = &ttii->sender_data[sender];
+
+	/*
+	 * take a copy of the ttii and data pointers for quick reference later on during reading
+	 */
+	tri->ttii = ttii;
+	tri->data = data;
+
+	DEBUG_TRACE("%px: Init reader for %px (%d): data %px.  \n", tri, ttii, sender, data);
+}
+EXPORT_SYMBOL(ecm_tracker_tcp_reader_init);
+
+/*
+ * ecm_tracker_tcp_reader_ref()
+ */
+void ecm_tracker_tcp_reader_ref(struct ecm_tracker_tcp_reader_instance *tri)
+{
+	DEBUG_CHECK_MAGIC(tri, ECM_TRACKER_TCP_READER_INSTANCE_MAGIC, "%px: magic failed", tri);
+
+	spin_lock_bh(&tri->lock);
+
+	tri->refs++;
+	DEBUG_ASSERT(tri->refs > 0, "%px: ref wrap", tri);
+	DEBUG_TRACE("%px: ref %d\n", tri, tri->refs);
+
+	spin_unlock_bh(&tri->lock);
+}
+EXPORT_SYMBOL(ecm_tracker_tcp_reader_ref);
+
+/*
+ * ecm_tracker_tcp_reader_deref()
+ */
+int ecm_tracker_tcp_reader_deref(struct ecm_tracker_tcp_reader_instance *tri)
+{
+	int refs;
+	DEBUG_CHECK_MAGIC(tri, ECM_TRACKER_TCP_READER_INSTANCE_MAGIC, "%px: magic failed", tri);
+
+	spin_lock_bh(&tri->lock);
+	tri->refs--;
+	refs = tri->refs;
+	DEBUG_ASSERT(tri->refs >= 0, "%px: ref wrap", tri);
+	DEBUG_TRACE("%px: deref %d\n", tri, tri->refs);
+
+	if (tri->refs > 0) {
+		spin_unlock_bh(&tri->lock);
+		return refs;
+	}
+	spin_unlock_bh(&tri->lock);
+
+	DEBUG_TRACE("%px: final\n", tri);
+
+	/*
+	 * Release the reference to the tcp tracker
+	 */
+	((struct ecm_tracker_instance *)tri->ttii)->deref((struct ecm_tracker_instance *)tri->ttii);
+
+	spin_lock_bh(&ecm_tracker_tcp_lock);
+	ecm_tracker_tcp_reader_count--;
+	DEBUG_ASSERT(ecm_tracker_tcp_reader_count >= 0, "%px: tracker count wrap", tri);
+	spin_unlock_bh(&ecm_tracker_tcp_lock);
+
+	DEBUG_INFO("%px: TCP Reader final\n", tri);
+	DEBUG_CLEAR_MAGIC(tri);
+	kfree(tri);
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_tracker_tcp_reader_deref);
+
+/*
+ * ecm_tracker_tcp_reader_alloc()
+ */
+struct ecm_tracker_tcp_reader_instance *ecm_tracker_tcp_reader_alloc(void)
+{
+	struct ecm_tracker_tcp_reader_instance *tri;
+
+	tri = (struct ecm_tracker_tcp_reader_instance *)kzalloc(sizeof(struct ecm_tracker_tcp_reader_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!tri) {
+		DEBUG_WARN("Failed to allocate tcp reader instance\n");
+		return NULL;
+	}
+
+	spin_lock_init(&tri->lock);
+	tri->refs = 1;
+	DEBUG_SET_MAGIC(tri, ECM_TRACKER_TCP_READER_INSTANCE_MAGIC);
+
+	spin_lock_bh(&ecm_tracker_tcp_lock);
+	ecm_tracker_tcp_reader_count++;
+	DEBUG_ASSERT(ecm_tracker_tcp_reader_count > 0, "%px: tcp tracker reader count wrap\n", tri);
+	spin_unlock_bh(&ecm_tracker_tcp_lock);
+
+	DEBUG_TRACE("TCP reader created %px\n", tri);
+	return tri;
+}
+EXPORT_SYMBOL(ecm_tracker_tcp_reader_alloc);
+#endif
diff --git a/qca-nss-ecm/ecm_tracker_tcp.h b/qca-nss-ecm/ecm_tracker_tcp.h
new file mode 100644
index 0000000..4956b90
--- /dev/null
+++ b/qca-nss-ecm/ecm_tracker_tcp.h
@@ -0,0 +1,76 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+struct ecm_tracker_tcp_instance;
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+typedef uint32_t (*ecm_tracker_tcp_bytes_avail_get_method_t)(struct ecm_tracker_tcp_instance *tti, ecm_tracker_sender_type_t sender);
+									/* Return number of bytes available to read */
+typedef int (*ecm_tracker_tcp_bytes_read_method_t)(struct ecm_tracker_tcp_instance *tti, ecm_tracker_sender_type_t sender, uint32_t offset, uint32_t size, void *buffer);
+									/* Read a number of bytes */
+typedef void (*ecm_tracker_tcp_bytes_discard_method_t)(struct ecm_tracker_tcp_instance *tti, ecm_tracker_sender_type_t sender, uint32_t n);
+									/* Discard n bytes from the available stream bytes */
+typedef bool (*ecm_tracker_tcp_mss_get_method_t)(struct ecm_tracker_tcp_instance *tti, ecm_tracker_sender_type_t sender, uint16_t *mss);
+									/* Get the MSS as sent BY the given target i.e. the MSS the other party is allowed to send */
+typedef bool (*ecm_tracker_tcp_segment_add_method_t)(struct ecm_tracker_tcp_instance *tti, ecm_tracker_sender_type_t sender,
+								struct ecm_tracker_ip_header *ip_hdr, struct ecm_tracker_ip_protocol_header *ecm_tcp_header, struct tcphdr *tcp_hdr, struct sk_buff *skb);
+									/* Add a pre-checked segment */
+#endif
+
+struct ecm_tracker_tcp_instance {
+	struct ecm_tracker_instance base;				/* MUST BE FIRST FIELD */
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	ecm_tracker_tcp_bytes_avail_get_method_t bytes_avail_get;	/* Return number of bytes available to read */
+	ecm_tracker_tcp_bytes_read_method_t bytes_read;			/* Read a number of bytes */
+	ecm_tracker_tcp_bytes_discard_method_t bytes_discard;		/* Discard n number of bytes from the beginning of the stream */
+	ecm_tracker_tcp_mss_get_method_t mss_get;			/* Get the MSS as sent BY the given target i.e. the maximum number of */
+	ecm_tracker_tcp_segment_add_method_t segment_add;		/* Add a prechecked MSS segment */
+#endif
+};
+
+/*
+ * TCP tracker
+ *	Records the two streams of bytes sent in either direction over a TCP connection
+ */
+struct tcphdr *ecm_tracker_tcp_check_header_and_read(struct sk_buff *skb, struct ecm_tracker_ip_header *ip_hdr, struct tcphdr *port_buffer);
+void ecm_tracker_tcp_init(struct ecm_tracker_tcp_instance *tti, int32_t data_limit, uint16_t src_mss_default, uint16_t dest_mss_default);
+struct ecm_tracker_tcp_instance *ecm_tracker_tcp_alloc(void);
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+/*
+ * TCP Reader
+ *	Faster reading of a stream of bytes.
+ * The stream MUST NOT BE EMPTY and the stream MUST NOT have any data discarded from it for the duration of the reader.
+ * It is fine for additional data to be added to the stream during reader use.
+ * You must operate the reader within the byte space you know to be available for reading.
+ *
+ * When reading blocks of data it is better to use the tracker bytes_read() method instead.
+ */
+struct ecm_tracker_tcp_reader_instance;
+void ecm_tracker_tcp_reader_discard_preceding(struct ecm_tracker_tcp_reader_instance *tri);
+void ecm_tracker_tcp_reader_advance(struct ecm_tracker_tcp_reader_instance *tri, uint32_t advancement);
+void ecm_tracker_tcp_reader_position_set(struct ecm_tracker_tcp_reader_instance *tri, uint32_t offset);
+void ecm_tracker_tcp_reader_init(struct ecm_tracker_tcp_reader_instance *tri, struct ecm_tracker_tcp_instance *tti, ecm_tracker_sender_type_t sender);
+uint8_t ecm_tracker_tcp_reader_fwd_read_u8(struct ecm_tracker_tcp_reader_instance *tri);
+void ecm_tracker_tcp_reader_ref(struct ecm_tracker_tcp_reader_instance *tri);
+int ecm_tracker_tcp_reader_deref(struct ecm_tracker_tcp_reader_instance *tri);
+struct ecm_tracker_tcp_reader_instance *ecm_tracker_tcp_reader_alloc(void);
+uint32_t ecm_tracker_tcp_reader_remain_get(struct ecm_tracker_tcp_reader_instance *tri);
+uint32_t ecm_tracker_tcp_reader_position_get(struct ecm_tracker_tcp_reader_instance *tri);
+void ecm_tracker_tcp_reader_retreat(struct ecm_tracker_tcp_reader_instance *tri, uint32_t retreatment);
+#endif
+
diff --git a/qca-nss-ecm/ecm_tracker_udp.c b/qca-nss-ecm/ecm_tracker_udp.c
new file mode 100644
index 0000000..2d047b4
--- /dev/null
+++ b/qca-nss-ecm/ecm_tracker_udp.c
@@ -0,0 +1,981 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/sysctl.h>
+#include <linux/kthread.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_TRACKER_UDP_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_tracker_udp.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_TRACKER_UDP_INSTANCE_MAGIC 0x7765
+#define ECM_TRACKER_UDP_SKB_CB_MAGIC 0xAAAB
+
+/*
+ * Useful constants
+ */
+#define ECM_TRACKER_UDP_HEADER_SIZE 8		/* UDP header is always 8 bytes RFC 768 Page 1 */
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+/*
+ * struct ecm_tracker_udp_skb_cb_format
+ *	Map of the cb[] array within our cached buffers - we use that area for our tracking
+ */
+struct ecm_tracker_udp_skb_cb_format {
+	uint32_t data_offset;			/* Offset in skb data to the actual datagram data - i.e. omitting headers */
+	uint32_t data_size;			/* Size of data */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+#endif
+
+/*
+ * struct ecm_tracker_udp_internal_instance
+ */
+struct ecm_tracker_udp_internal_instance {
+	struct ecm_tracker_udp_instance udp_base;			/* MUST BE FIRST FIELD */
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	/*
+	 * skb-next and skb->prev pointers are leveraged for these lists
+	 */
+	struct sk_buff *src_recvd_order;	/* sk buff list as sent by src */
+	struct sk_buff *src_recvd_order_last;	/* Last skb send - for fast appending of new buffers */
+	int32_t src_count;			/* Count of datagrams in list */
+	int32_t src_bytes_total;		/* Total bytes in all received datagrams */
+
+	struct sk_buff *dest_recvd_order;	/* sk buff list as sent by dest */
+	struct sk_buff *dest_recvd_order_last;	/* Last skb send - for fast appending of new buffers */
+	int32_t dest_count;			/* Count of datagrams in list */
+	int32_t dest_bytes_total;		/* Total bytes in all received datagrams */
+
+	int32_t data_limit;			/* Limit for tracked data */
+#endif
+
+	ecm_tracker_sender_state_t sender_state[ECM_TRACKER_SENDER_MAX];
+						/* State of each sender */
+	ecm_db_timer_group_t timer_group;	/* Recommended timer group for connection that is using this tracker */
+
+	spinlock_t lock;			/* lock */
+
+	int refs;				/* Integer to trap we never go negative */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+int ecm_tracker_udp_count = 0;		/* Counts the number of UDP data trackers right now */
+static DEFINE_SPINLOCK(ecm_tracker_udp_lock);		/* Global lock for the tracker globals */
+
+/*
+ * ecm_trracker_udp_connection_state_matrix[][]
+ *	Matrix to convert from/to states to connection state
+ */
+static ecm_tracker_connection_state_t ecm_tracker_udp_connection_state_matrix[ECM_TRACKER_SENDER_STATE_MAX][ECM_TRACKER_SENDER_STATE_MAX] =
+{	/* 			Unknown						Establishing					Established					Closing					Closed					Fault */
+	/* Unknown */		{ECM_TRACKER_CONNECTION_STATE_ESTABLISHING,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHING,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHED,	ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT},
+	/* Establishing */	{ECM_TRACKER_CONNECTION_STATE_ESTABLISHING,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHING,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHED,	ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT},
+	/* Established */	{ECM_TRACKER_CONNECTION_STATE_ESTABLISHED,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHED,	ECM_TRACKER_CONNECTION_STATE_ESTABLISHED,	ECM_TRACKER_CONNECTION_STATE_CLOSING,	ECM_TRACKER_CONNECTION_STATE_CLOSING,	ECM_TRACKER_CONNECTION_STATE_FAULT},
+	/* Closing */		{ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_CLOSING,		ECM_TRACKER_CONNECTION_STATE_CLOSING,	ECM_TRACKER_CONNECTION_STATE_CLOSING,	ECM_TRACKER_CONNECTION_STATE_FAULT},
+	/* Closed */		{ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_CLOSING,		ECM_TRACKER_CONNECTION_STATE_CLOSING,	ECM_TRACKER_CONNECTION_STATE_CLOSED, 	ECM_TRACKER_CONNECTION_STATE_FAULT},
+	/* Fault */		{ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_FAULT,		ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT,	ECM_TRACKER_CONNECTION_STATE_FAULT},
+};
+
+/*
+ * ecm_tracker_udp_check_header_and_read()
+ *	Check for validly sized header and read the udp protocol header
+ */
+struct udphdr *ecm_tracker_udp_check_header_and_read(struct sk_buff *skb, struct ecm_tracker_ip_header *ip_hdr, struct udphdr *port_buffer)
+{
+	struct ecm_tracker_ip_protocol_header *header;
+
+	/*
+	 * Is there a UDP header?
+	 */
+	header = &ip_hdr->headers[ECM_TRACKER_IP_PROTOCOL_TYPE_UDP];
+	if (header->header_size != ECM_TRACKER_UDP_HEADER_SIZE) {
+		DEBUG_WARN("Skb: %px, UDP header size bad %u\n", skb, header->header_size);
+		return NULL;
+	}
+
+	return skb_header_pointer(skb, header->offset, sizeof(*port_buffer), port_buffer);
+}
+EXPORT_SYMBOL(ecm_tracker_udp_check_header_and_read);
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+/*
+ * ecm_tracker_udp_datagram_discard()
+ *	Discard n number of datagrams at the head of the datagram list that were sent to the target
+ */
+static void ecm_tracker_udp_datagram_discard(struct ecm_tracker_udp_internal_instance *utii, ecm_tracker_sender_type_t sender, int32_t n)
+{
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+
+	DEBUG_TRACE("%px: discard %u datagrams for %d\n", utii, n, sender);
+
+	/*
+	 * Which list?
+	 */
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		/*
+		 * iterate n times and discard the buffers
+		 */
+		while (n) {
+			struct sk_buff *skb;
+
+			spin_lock_bh(&utii->lock);
+
+			skb = utii->src_recvd_order;
+			DEBUG_ASSERT(skb, "%px: bad list\n", utii);
+
+			utii->src_recvd_order = skb->next;
+			if (!utii->src_recvd_order) {
+				DEBUG_ASSERT(utii->src_recvd_order_last == skb, "%px: bad list\n", utii);
+				utii->src_recvd_order_last = NULL;
+			} else {
+				utii->src_recvd_order->prev = NULL;
+			}
+
+			utii->src_count--;
+			DEBUG_ASSERT(utii->src_count >= 0, "%px: bad total\n", utii);
+			utii->src_bytes_total -= skb->truesize;
+			ecm_tracker_data_total_decrease(skb->len, skb->truesize);
+			DEBUG_ASSERT(utii->src_bytes_total >= 0, "%px: bad bytes total\n", utii);
+
+			spin_unlock_bh(&utii->lock);
+			kfree_skb(skb);
+
+			n--;
+		}
+		return;
+	}
+
+	/*
+	 * iterate n times and discard the buffers
+	 */
+	while (n) {
+		struct sk_buff *skb;
+
+		spin_lock_bh(&utii->lock);
+
+		skb = utii->dest_recvd_order;
+		DEBUG_ASSERT(skb, "%px: bad list\n", utii);
+
+		utii->dest_recvd_order = skb->next;
+		if (!utii->dest_recvd_order) {
+			DEBUG_ASSERT(utii->dest_recvd_order_last == skb, "%px: bad list\n", utii);
+			utii->dest_recvd_order_last = NULL;
+		} else {
+			utii->dest_recvd_order->prev = NULL;
+		}
+
+		utii->dest_count--;
+		DEBUG_ASSERT(utii->dest_count >= 0, "%px: bad total\n", utii);
+		utii->dest_bytes_total -= skb->truesize;
+		ecm_tracker_data_total_decrease(skb->len, skb->truesize);
+		DEBUG_ASSERT(utii->dest_bytes_total >= 0, "%px: bad bytes total\n", utii);
+
+		spin_unlock_bh(&utii->lock);
+		kfree_skb(skb);
+
+		n--;
+	}
+}
+
+/*
+ * ecm_tracker_udp_discard_all()
+ *	Discard all tracked data
+ */
+void ecm_tracker_udp_discard_all(struct ecm_tracker_udp_internal_instance *utii)
+{
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+
+	/*
+	 * Destroy all datagrams
+	 */
+	DEBUG_TRACE("%px: destroy all\n", utii);
+	ecm_tracker_udp_datagram_discard(utii, ECM_TRACKER_SENDER_TYPE_SRC, utii->src_count);
+	ecm_tracker_udp_datagram_discard(utii, ECM_TRACKER_SENDER_TYPE_DEST, utii->dest_count);
+}
+
+/*
+ * ecm_tracker_udp_discard_all_callback()
+ *	Discard all tracked data
+ */
+static void ecm_tracker_udp_discard_all_callback(struct ecm_tracker_instance *ti)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)ti;
+	ecm_tracker_udp_discard_all(utii);
+}
+#endif
+
+/*
+ * ecm_tracker_udp_ref()
+ */
+static void ecm_tracker_udp_ref(struct ecm_tracker_udp_internal_instance *utii)
+{
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+
+	spin_lock_bh(&utii->lock);
+
+	utii->refs++;
+	DEBUG_ASSERT(utii->refs > 0, "%px: ref wrap", utii);
+	DEBUG_TRACE("%px: ref %d\n", utii, utii->refs);
+
+	spin_unlock_bh(&utii->lock);
+}
+
+/*
+ * ecm_tracker_udp_ref_callback()
+ */
+void ecm_tracker_udp_ref_callback(struct ecm_tracker_instance *ti)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)ti;
+	ecm_tracker_udp_ref(utii);
+}
+
+/*
+ * ecm_tracker_udp_deref()
+ */
+static int ecm_tracker_udp_deref(struct ecm_tracker_udp_internal_instance *utii)
+{
+	int refs;
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+
+	spin_lock_bh(&utii->lock);
+	utii->refs--;
+	refs = utii->refs;
+	DEBUG_ASSERT(utii->refs >= 0, "%px: ref wrap", utii);
+	DEBUG_TRACE("%px: deref %d\n", utii, utii->refs);
+
+	if (utii->refs > 0) {
+		spin_unlock_bh(&utii->lock);
+		return refs;
+	}
+	spin_unlock_bh(&utii->lock);
+
+	DEBUG_TRACE("%px: final\n", utii);
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	/*
+	 * Destroy all datagrams
+	 */
+	ecm_tracker_udp_datagram_discard(utii, ECM_TRACKER_SENDER_TYPE_SRC, utii->src_count);
+	ecm_tracker_udp_datagram_discard(utii, ECM_TRACKER_SENDER_TYPE_DEST, utii->dest_count);
+#endif
+
+	spin_lock_bh(&ecm_tracker_udp_lock);
+	ecm_tracker_udp_count--;
+	DEBUG_ASSERT(ecm_tracker_udp_count >= 0, "%px: tracker count wrap", utii);
+	spin_unlock_bh(&ecm_tracker_udp_lock);
+
+	DEBUG_INFO("%px: Udp tracker final\n", utii);
+	DEBUG_CLEAR_MAGIC(utii);
+	kfree(utii);
+
+	return 0;
+}
+
+/*
+ * _ecm_tracker_udp_deref_callback()
+ */
+int ecm_tracker_udp_deref_callback(struct ecm_tracker_instance *ti)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)ti;
+	return ecm_tracker_udp_deref(utii);
+}
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+/*
+ * ecm_tracker_udp_datagram_count_get()
+ *	Return number of available datagrams sent to the specified target
+ */
+static int32_t ecm_tracker_udp_datagram_count_get(struct ecm_tracker_udp_internal_instance *utii, ecm_tracker_sender_type_t sender)
+{
+	int32_t count;
+
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+
+	/*
+	 * Which list?
+	 */
+	spin_lock_bh(&utii->lock);
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		count = utii->src_count;
+	} else {
+		count = utii->dest_count;
+	}
+	spin_unlock_bh(&utii->lock);
+
+	DEBUG_TRACE("%px: datagram count get for %d is %d\n", utii, sender, count);
+
+	return count;
+}
+
+/*
+ * ecm_tracker_udp_datagram_count_get_callback()
+ *	Return number of available datagrams sent to the specified target
+ */
+static int32_t ecm_tracker_udp_datagram_count_get_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)ti;
+	return ecm_tracker_udp_datagram_count_get(utii, sender);
+}
+
+/*
+ * ecm_tracker_udp_datagram_discard_callback()
+ *	Discard n number of datagrams at the head of the datagram list that were sent to the target
+ */
+static void ecm_tracker_udp_datagram_discard_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, int32_t n)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)ti;
+
+	ecm_tracker_udp_datagram_discard(utii, sender, n);
+}
+
+/*
+ * ecm_tracker_udp_datagram_size_get()
+ *	Return size in bytes of datagram at index i that was sent to the target
+ */
+int32_t ecm_tracker_udp_datagram_size_get(struct ecm_tracker_udp_instance *uti, ecm_tracker_sender_type_t sender, int32_t i)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)uti;
+	int32_t size;
+	struct sk_buff *skb;
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+
+	/*
+	 * Which list?
+	 */
+	spin_lock_bh(&utii->lock);
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		skb = utii->src_recvd_order;
+	} else {
+		skb = utii->dest_recvd_order;
+	}
+
+	/*
+	 * Iterate to the i'th datagram
+	 */
+	while (i) {
+		DEBUG_ASSERT(skb, "%px: index bad\n", utii);
+		skb = skb->next;
+		i--;
+	}
+	DEBUG_ASSERT(skb, "%px: index bad\n", utii);
+
+	size = skb->len;
+
+	spin_unlock_bh(&utii->lock);
+	return size;
+}
+
+/*
+ * ecm_tracker_udp_datagram_size_get_callback()
+ *	Return size in bytes of datagram at index i that was sent to the target
+ */
+static int32_t ecm_tracker_udp_datagram_size_get_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, int32_t i)
+{
+	struct ecm_tracker_udp_instance *uti = (struct ecm_tracker_udp_instance *)ti;
+
+	return ecm_tracker_udp_datagram_size_get(uti, sender, i);
+}
+
+/*
+ * ecm_tracker_udp_datagram_read()
+ *	Read size bytes from datagram at index i into the buffer
+ */
+int ecm_tracker_udp_datagram_read(struct ecm_tracker_udp_instance *uti, ecm_tracker_sender_type_t sender, int32_t i, int32_t offset, int32_t size, void *buffer)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)uti;
+	int res;
+	struct sk_buff *skb;
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+	DEBUG_TRACE("%px: datagram %d read at offset %d for %d bytes for %d\n", utii, i, offset, size, sender);
+
+	/*
+	 * Which list?
+	 */
+	spin_lock_bh(&utii->lock);
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		skb = utii->src_recvd_order;
+	} else {
+		skb = utii->dest_recvd_order;
+	}
+
+	/*
+	 * Iterate to the i'th datagram
+	 */
+	while (i) {
+		DEBUG_ASSERT(skb, "%px: index bad\n", utii);
+		skb = skb->next;
+		i--;
+	}
+	DEBUG_ASSERT(skb, "%px: index bad\n", utii);
+
+	/*
+	 * Perform read
+	 */
+	res = skb_copy_bits(skb, offset, buffer, (unsigned int)size);
+
+	spin_unlock_bh(&utii->lock);
+
+	return res;
+}
+
+/*
+ * ecm_tracker_udp_datagram_read_callback()
+ *	Read size bytes from datagram at index i into the buffer
+ */
+static int ecm_tracker_udp_datagram_read_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, int32_t i, int32_t offset, int32_t size, void *buffer)
+{
+	struct ecm_tracker_udp_instance *uti = (struct ecm_tracker_udp_instance *)ti;
+
+	return ecm_tracker_udp_datagram_read(uti, sender, i, offset, size, buffer);
+}
+
+/*
+ * ecm_tracker_udp_data_total_get_callback()
+ *	Return total tracked data
+ */
+static int32_t ecm_tracker_udp_data_total_get_callback(struct ecm_tracker_instance *ti)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)ti;
+	int32_t data_total;
+
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+
+	spin_lock_bh(&utii->lock);
+	data_total = utii->src_bytes_total + utii->dest_bytes_total;
+	spin_unlock_bh(&utii->lock);
+
+	return data_total;
+}
+
+/*
+ * ecm_tracker_udp_data_limit_get_callback()
+ *	Return tracked data limit
+ */
+static int32_t ecm_tracker_udp_data_limit_get_callback(struct ecm_tracker_instance *ti)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)ti;
+	int32_t data_limit;
+
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+
+	spin_lock_bh(&utii->lock);
+	data_limit = utii->data_limit;
+	spin_unlock_bh(&utii->lock);
+
+	return data_limit;
+}
+
+/*
+ * ecm_tracker_udp_data_limit_set_callback()
+ *	Set tracked data limit
+ */
+static void ecm_tracker_udp_data_limit_set_callback(struct ecm_tracker_instance *ti, int32_t data_limit)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)ti;
+
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+
+	spin_lock_bh(&utii->lock);
+	utii->data_limit = data_limit;
+	spin_unlock_bh(&utii->lock);
+}
+
+/*
+ * ecm_tracker_udp_datagram_add()
+ *	Append the datagram onto the tracker queue for the given target
+ */
+static bool ecm_tracker_udp_datagram_add(struct ecm_tracker_udp_internal_instance *utii, ecm_tracker_sender_type_t sender,
+								struct ecm_tracker_ip_header *ip_hdr, struct ecm_tracker_ip_protocol_header *ecm_udp_header,
+								struct udphdr *udp_header, struct sk_buff *skb)
+{
+	struct sk_buff *skbc;
+	struct ecm_tracker_udp_skb_cb_format *skbc_cb;
+
+	DEBUG_TRACE("%px: datagram %px add for %d, ip_hdr_len %u, total len: %u, offset: %u, size: %u\n",
+			utii, skb, sender, ip_hdr->ip_header_length, ip_hdr->total_length,
+			ecm_udp_header->offset, ecm_udp_header->size);
+
+	/*
+	 * Clone the packet
+	 */
+	skbc = skb_clone(skb, GFP_ATOMIC | __GFP_NOWARN);
+	if (!skbc) {
+		DEBUG_WARN("%px: Failed to clone packet %px\n", utii, skb);
+		return false;
+	}
+
+	DEBUG_TRACE("%px: cloned %px to %px\n", utii, skb, skbc);
+
+	/*
+	 * Get the private cb area and initialise it.
+	 * ALL DATAGRAMS HAVE TO HAVE ONE.
+	 */
+	skbc_cb = (struct ecm_tracker_udp_skb_cb_format *)skbc->cb;
+	DEBUG_SET_MAGIC(skbc_cb, ECM_TRACKER_UDP_SKB_CB_MAGIC);
+	skbc_cb->data_offset = ecm_udp_header->offset + ecm_udp_header->header_size;
+	if (ip_hdr->total_length < (ecm_udp_header->offset + ecm_udp_header->size)) {
+		DEBUG_WARN("%px: Invalid headers\n", utii);
+		kfree_skb(skbc);
+		return false;
+	}
+	skbc_cb->data_size = ecm_udp_header->size - ecm_udp_header->header_size;
+
+	/*
+	 * Are we within instance limit?
+	 */
+	spin_lock_bh(&utii->lock);
+	DEBUG_ASSERT((utii->src_bytes_total + utii->dest_bytes_total + skbc->truesize) > 0, "%px: bad total\n", utii);
+	if ((utii->src_bytes_total + utii->dest_bytes_total + skbc->truesize) > utii->data_limit) {
+		DEBUG_TRACE("%px: over limit\n", utii);
+		spin_unlock_bh(&utii->lock);
+		kfree_skb(skbc);
+		return false;
+	}
+
+	/*
+	 * Within global limit?
+	 */
+	if (!ecm_tracker_data_total_increase(skbc->len, skbc->truesize)) {
+		DEBUG_TRACE("%px: over global limit\n", utii);
+		spin_unlock_bh(&utii->lock);
+		kfree_skb(skbc);
+		return false;
+	}
+
+	/*
+	 * Which list to insert the datagram in to?
+	 */
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		skbc->next = NULL;
+		skbc->prev = utii->src_recvd_order_last;
+		utii->src_recvd_order_last = skbc;
+		if (skbc->prev) {
+			skbc->prev->next = skbc;
+		} else {
+			DEBUG_ASSERT(utii->src_recvd_order == NULL, "%px: bad list\n", utii);
+			utii->src_recvd_order = skbc;
+		}
+
+		utii->src_count++;
+		DEBUG_ASSERT(utii->src_count > 0, "%px: bad total\n", utii);
+		utii->src_bytes_total += skbc->truesize;
+		spin_unlock_bh(&utii->lock);
+		return true;
+	}
+
+	skbc->next = NULL;
+	skbc->prev = utii->dest_recvd_order_last;
+	utii->dest_recvd_order_last = skbc;
+	if (skbc->prev) {
+		skbc->prev->next = skbc;
+	} else {
+		DEBUG_ASSERT(utii->dest_recvd_order == NULL, "%px: bad list\n", utii);
+		utii->dest_recvd_order = skbc;
+	}
+
+	utii->dest_count++;
+	DEBUG_ASSERT(utii->dest_count > 0, "%px: bad total\n", utii);
+	utii->dest_bytes_total += skbc->truesize;
+	spin_unlock_bh(&utii->lock);
+	return true;
+}
+
+/*
+ * _ecm_tracker_udp_datagram_add_callback()
+ *	Append the datagram onto the tracker queue for the given target
+ */
+static bool ecm_tracker_udp_datagram_add_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, struct sk_buff *skb)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)ti;
+	struct ecm_tracker_ip_header ip_hdr;
+	struct ecm_tracker_ip_protocol_header *ecm_udp_header;
+	struct udphdr *udp_header;
+	struct udphdr udp_header_buffer;
+
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+
+	/*
+	 * Obtain the IP header from the skb
+	 */
+	if (!ecm_tracker_ip_check_header_and_read(&ip_hdr, skb)) {
+		DEBUG_WARN("%px: no ip_hdr for %px\n", utii, skb);
+		return false;
+	}
+
+	/*
+	 * Get UDP header
+	 */
+	udp_header = ecm_tracker_udp_check_header_and_read(skb, &ip_hdr, &udp_header_buffer);
+	if (!udp_header) {
+		DEBUG_WARN("%px: not/invalid udp %d\n", utii, ip_hdr.protocol);
+		return false;
+	}
+	ecm_udp_header = &ip_hdr.headers[ECM_TRACKER_IP_PROTOCOL_TYPE_UDP];
+
+	return ecm_tracker_udp_datagram_add(utii, sender, &ip_hdr, ecm_udp_header, udp_header, skb);
+}
+
+/*
+ * ecm_tracker_udp_datagram_add_checked_callback()
+ *	Add a pre-checked datagram
+ */
+static bool ecm_tracker_udp_datagram_add_checked_callback(struct ecm_tracker_udp_instance *uti, ecm_tracker_sender_type_t sender,
+								struct ecm_tracker_ip_header *ip_hdr, struct ecm_tracker_ip_protocol_header *ecm_udp_header,
+								struct udphdr *udp_header, struct sk_buff *skb)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)uti;
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+	return ecm_tracker_udp_datagram_add(utii, sender, ip_hdr, ecm_udp_header, udp_header, skb);
+}
+
+/*
+ * ecm_tracker_udp_data_read_callback()
+ *	Return size bytes of datagram data at index i that was sent to the target
+ */
+static int ecm_tracker_udp_data_read_callback(struct ecm_tracker_udp_instance *uti, ecm_tracker_sender_type_t sender, int32_t i,
+								int32_t offset, int32_t size, void *buffer)
+
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)uti;
+	int res;
+	struct sk_buff *skb;
+	struct ecm_tracker_udp_skb_cb_format *skb_cb;
+
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+	DEBUG_TRACE("%px: datagram data %d read at offset %d for %d bytes for %d\n", utii, i, offset, size, sender);
+
+	/*
+	 * Which list?
+	 */
+	spin_lock_bh(&utii->lock);
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		skb = utii->src_recvd_order;
+	} else {
+		skb = utii->dest_recvd_order;
+	}
+
+	/*
+	 * Iterate to the i'th datagram
+	 */
+	while (i) {
+		DEBUG_ASSERT(skb, "%px: index bad\n", utii);
+		skb = skb->next;
+		i--;
+	}
+	DEBUG_ASSERT(skb, "%px: index bad\n", utii);
+
+	/*
+	 * Perform read of data excluding headers
+	 */
+	skb_cb = (struct ecm_tracker_udp_skb_cb_format *)skb->cb;
+	DEBUG_CHECK_MAGIC(skb_cb, ECM_TRACKER_UDP_SKB_CB_MAGIC, "%px: invalid cb magic %px\n", utii, skb);
+	offset += skb_cb->data_offset;
+	DEBUG_ASSERT(size <= skb_cb->data_size, "%px: size %d too large for skb %px at %u\n", utii, size, skb, skb_cb->data_size);
+	res = skb_copy_bits(skb, offset, buffer, (unsigned int)size);
+
+	spin_unlock_bh(&utii->lock);
+
+	return res;
+}
+
+/*
+ * ecm_tracker_udp_data_size_get_callback()
+ *	Read size in bytes of data at index i into the buffer
+ */
+static int32_t ecm_tracker_udp_data_size_get_callback(struct ecm_tracker_udp_instance *uti, ecm_tracker_sender_type_t sender, int32_t i)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)uti;
+	int32_t size;
+	struct sk_buff *skb;
+	struct ecm_tracker_udp_skb_cb_format *skb_cb;
+
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+	DEBUG_TRACE("%px: datagram %u data size get for %d\n", utii, i, sender);
+
+	/*
+	 * Which list?
+	 */
+	spin_lock_bh(&utii->lock);
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		skb = utii->src_recvd_order;
+	} else {
+		skb = utii->dest_recvd_order;
+	}
+
+	/*
+	 * Iterate to the i'th datagram
+	 */
+	while (i) {
+		DEBUG_ASSERT(skb, "%px: index bad\n", utii);
+		skb = skb->next;
+		i--;
+	}
+	DEBUG_ASSERT(skb, "%px: index bad\n", utii);
+
+	/*
+	 * Perform read of data excluding headers
+	 */
+	skb_cb = (struct ecm_tracker_udp_skb_cb_format *)skb->cb;
+	DEBUG_CHECK_MAGIC(skb_cb, ECM_TRACKER_UDP_SKB_CB_MAGIC, "%px: invalid cb magic %px\n", utii, skb);
+	size = skb_cb->data_size;
+	spin_unlock_bh(&utii->lock);
+
+	return size;
+}
+#endif
+
+/*
+ * ecm_tracker_udp_state_update_callback()
+ * 	Update connection state based on the knowledge we have and the skb given
+ */
+static void ecm_tracker_udp_state_update_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_type_t sender, struct ecm_tracker_ip_header *ip_hdr, struct sk_buff *skb)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)ti;
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+
+	/*
+	 * As long as a sender has seen data then we consider the sender established
+	 */
+	spin_lock_bh(&utii->lock);
+	utii->sender_state[sender] = ECM_TRACKER_SENDER_STATE_ESTABLISHED;
+	spin_unlock_bh(&utii->lock);
+}
+
+/*
+ * ecm_tracker_udp_state_get_callback()
+ * 	Get state
+ */
+static void ecm_tracker_udp_state_get_callback(struct ecm_tracker_instance *ti, ecm_tracker_sender_state_t *src_state,
+					ecm_tracker_sender_state_t *dest_state, ecm_tracker_connection_state_t *state, ecm_db_timer_group_t *tg)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)ti;
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+	spin_lock_bh(&utii->lock);
+	*src_state = utii->sender_state[ECM_TRACKER_SENDER_TYPE_SRC];
+	*dest_state = utii->sender_state[ECM_TRACKER_SENDER_TYPE_DEST];
+	*tg = utii->timer_group;
+	spin_unlock_bh(&utii->lock);
+	*state = ecm_tracker_udp_connection_state_matrix[*src_state][*dest_state];
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_tracker_udp_state_text_get_callback()
+ *	Return state
+ */
+static int ecm_tracker_udp_state_text_get_callback(struct ecm_tracker_instance *ti, struct ecm_state_file_instance *sfi)
+{
+	int result;
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)ti;
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	int32_t src_count;
+	int32_t src_bytes_total;
+	int32_t dest_count;
+	int32_t dest_bytes_total;
+	int32_t data_limit;
+#endif
+	ecm_db_timer_group_t timer_group;
+	ecm_tracker_sender_state_t sender_state[ECM_TRACKER_SENDER_MAX];
+	ecm_tracker_connection_state_t connection_state;
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+
+	if ((result = ecm_state_prefix_add(sfi, "tracker_udp"))) {
+		return result;
+	}
+
+	/*
+	 * Capture state
+	 */
+	spin_lock_bh(&utii->lock);
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	src_count = utii->src_count;
+	src_bytes_total = utii->src_bytes_total;
+	dest_count = utii->dest_count;
+	dest_bytes_total = utii->dest_bytes_total;
+	data_limit = utii->data_limit;
+#endif
+	sender_state[ECM_TRACKER_SENDER_TYPE_SRC] = utii->sender_state[ECM_TRACKER_SENDER_TYPE_SRC];
+	sender_state[ECM_TRACKER_SENDER_TYPE_DEST] = utii->sender_state[ECM_TRACKER_SENDER_TYPE_DEST];
+	timer_group = utii->timer_group;
+	spin_unlock_bh(&utii->lock);
+	connection_state = ecm_tracker_udp_connection_state_matrix[sender_state[ECM_TRACKER_SENDER_TYPE_SRC]][sender_state[ECM_TRACKER_SENDER_TYPE_DEST]];
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	if ((result = ecm_state_write(sfi, "src_count", "%d", src_count))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "src_bytes_total", "%d", src_bytes_total))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "dest_count", "%d", dest_count))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "dest_bytes_total", "%d", dest_bytes_total))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "data_limit", "%d", data_limit))) {
+		return result;
+	}
+#endif
+
+	connection_state = ecm_tracker_udp_connection_state_matrix[sender_state[ECM_TRACKER_SENDER_TYPE_SRC]][sender_state[ECM_TRACKER_SENDER_TYPE_DEST]];
+	if ((result = ecm_state_write(sfi, "timer_group", "%d", ECM_DB_TIMER_GROUPS_CONNECTION_GENERIC_TIMEOUT))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "src_sender_state", "%s", ecm_tracker_sender_state_to_string(sender_state[ECM_TRACKER_SENDER_TYPE_SRC])))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "dest_sender_state", "%s", ecm_tracker_sender_state_to_string(sender_state[ECM_TRACKER_SENDER_TYPE_DEST])))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "connection_state", "%s", ecm_tracker_connection_state_to_string(connection_state)))) {
+		return result;
+	}
+
+ 	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+/*
+ * ecm_tracker_udp_init()
+ *	Initialise the two host addresses that define the two directions we track data for
+ */
+void ecm_tracker_udp_init(struct ecm_tracker_udp_instance *uti, int32_t data_limit, int src_port, int dest_port)
+{
+	struct ecm_tracker_udp_internal_instance *utii = (struct ecm_tracker_udp_internal_instance *)uti;
+	DEBUG_CHECK_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC, "%px: magic failed", utii);
+	DEBUG_TRACE("%px: init udp tracker\n", utii);
+
+	spin_lock_bh(&utii->lock);
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	utii->data_limit = data_limit;
+#endif
+	if ((src_port < 1024) || (dest_port < 1024)) {
+		/*
+		 * Because UDP connections can be reaped we assign well known ports to the WKP timer group.
+		 * The WKP group is not reaped thus preserving connections involving known services.
+		 * NOTE: Classifiers are still free to change the group as they see fit.
+		 */
+		utii->timer_group = ECM_DB_TIMER_GROUPS_CONNECTION_UDP_WKP_TIMEOUT;
+		spin_unlock_bh(&utii->lock);
+		return;
+	}
+	utii->timer_group = ECM_DB_TIMER_GROUPS_CONNECTION_UDP_GENERIC_TIMEOUT;
+	spin_unlock_bh(&utii->lock);
+}
+EXPORT_SYMBOL(ecm_tracker_udp_init);
+
+/*
+ * ecm_tracker_udp_alloc()
+ */
+struct ecm_tracker_udp_instance *ecm_tracker_udp_alloc(void)
+{
+	struct ecm_tracker_udp_internal_instance *utii;
+
+	utii = (struct ecm_tracker_udp_internal_instance *)kzalloc(sizeof(struct ecm_tracker_udp_internal_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!utii) {
+		DEBUG_WARN("Failed to allocate udp tracker instance\n");
+		return NULL;
+	}
+
+	utii->udp_base.base.ref = ecm_tracker_udp_ref_callback;
+	utii->udp_base.base.deref = ecm_tracker_udp_deref_callback;
+	utii->udp_base.base.state_update = ecm_tracker_udp_state_update_callback;
+	utii->udp_base.base.state_get = ecm_tracker_udp_state_get_callback;
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	utii->udp_base.base.datagram_count_get = ecm_tracker_udp_datagram_count_get_callback;
+	utii->udp_base.base.datagram_discard = ecm_tracker_udp_datagram_discard_callback;
+	utii->udp_base.base.datagram_read = ecm_tracker_udp_datagram_read_callback;
+	utii->udp_base.base.datagram_size_get = ecm_tracker_udp_datagram_size_get_callback;
+	utii->udp_base.base.datagram_add = ecm_tracker_udp_datagram_add_callback;
+	utii->udp_base.base.discard_all = ecm_tracker_udp_discard_all_callback;
+	utii->udp_base.base.data_total_get = ecm_tracker_udp_data_total_get_callback;
+	utii->udp_base.base.data_limit_get = ecm_tracker_udp_data_limit_get_callback;
+	utii->udp_base.base.data_limit_set = ecm_tracker_udp_data_limit_set_callback;
+
+	utii->udp_base.data_read = ecm_tracker_udp_data_read_callback;
+	utii->udp_base.data_size_get = ecm_tracker_udp_data_size_get_callback;
+	utii->udp_base.datagram_add = ecm_tracker_udp_datagram_add_checked_callback;
+#endif
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	utii->udp_base.base.state_text_get = ecm_tracker_udp_state_text_get_callback;
+#endif
+
+	spin_lock_init(&utii->lock);
+
+	utii->refs = 1;
+	DEBUG_SET_MAGIC(utii, ECM_TRACKER_UDP_INSTANCE_MAGIC);
+
+	spin_lock_bh(&ecm_tracker_udp_lock);
+	ecm_tracker_udp_count++;
+	DEBUG_ASSERT(ecm_tracker_udp_count > 0, "%px: udp tracker count wrap\n", utii);
+	spin_unlock_bh(&ecm_tracker_udp_lock);
+
+	DEBUG_TRACE("UDP tracker created %px\n", utii);
+	return (struct ecm_tracker_udp_instance *)utii;
+}
+EXPORT_SYMBOL(ecm_tracker_udp_alloc);
diff --git a/qca-nss-ecm/ecm_tracker_udp.h b/qca-nss-ecm/ecm_tracker_udp.h
new file mode 100644
index 0000000..c13a5d4
--- /dev/null
+++ b/qca-nss-ecm/ecm_tracker_udp.h
@@ -0,0 +1,43 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+struct ecm_tracker_udp_instance;
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+typedef int32_t (*ecm_tracker_udp_data_size_get_method_t)(struct ecm_tracker_udp_instance *uti, ecm_tracker_sender_type_t sender, int32_t i);
+										/* Return size in bytes of datagram data at index i that was sent by the sender */
+typedef int (*ecm_tracker_udp_data_read_method_t)(struct ecm_tracker_udp_instance *uti, ecm_tracker_sender_type_t sender, int32_t i, int32_t offset, int32_t size, void *buffer);
+										/* Read size bytes of data at index i into the buffer */
+typedef bool (*ecm_tracker_udp_datagram_add_method_t)(struct ecm_tracker_udp_instance *uti, ecm_tracker_sender_type_t sender, struct ecm_tracker_ip_header *ip_hdr, struct ecm_tracker_ip_protocol_header *ecm_udp_header, struct udphdr *udp_header, struct sk_buff *skb);
+										/* Add a pre-checked UDP datagram */
+#endif
+
+struct ecm_tracker_udp_instance {
+	struct ecm_tracker_instance base;					/* MUST BE FIRST FIELD */
+
+#ifdef ECM_TRACKER_DPI_SUPPORT_ENABLE
+	ecm_tracker_udp_data_read_method_t data_read;				/* Read data from a UDP datagram (headers not considered) */
+	ecm_tracker_udp_data_size_get_method_t data_size_get;			/* Get data size of datagram (headers not considered) */
+	ecm_tracker_udp_datagram_add_method_t datagram_add;			/* Add a pre-checked UDP datagram */
+#endif
+};
+
+
+struct udphdr *ecm_tracker_udp_check_header_and_read(struct sk_buff *skb, struct ecm_tracker_ip_header *ip_hdr, struct udphdr *port_buffer);
+
+void ecm_tracker_udp_init(struct ecm_tracker_udp_instance *uti, int32_t data_limit, int src_port, int dest_port);
+struct ecm_tracker_udp_instance *ecm_tracker_udp_alloc(void);
+
diff --git a/qca-nss-ecm/ecm_types.h b/qca-nss-ecm/ecm_types.h
new file mode 100644
index 0000000..3777688
--- /dev/null
+++ b/qca-nss-ecm/ecm_types.h
@@ -0,0 +1,492 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2015, 2019-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#ifndef ECM_TYPES_H_
+#define ECM_TYPES_H_
+
+#include <linux/printk.h>
+
+/*
+ * Common ECM macro to handle the kernel macro name change from kernel version 4.9 and above.
+ * GRE_VERSION_1701 and GRE_VERSION_PPTP macros in kernel version <  4.9 needs to be converted
+ * to big endian since GRE_VERSION with which it compares is in big endian
+ */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0))
+#define ECM_GRE_VERSION_0   __cpu_to_be16(GRE_VERSION_1701)
+#define ECM_GRE_VERSION_1   __cpu_to_be16(GRE_VERSION_PPTP)
+typedef struct gre_hdr_pptp ecm_gre_hdr_pptp;
+#else
+#define ECM_GRE_VERSION_0   GRE_VERSION_0
+#define ECM_GRE_VERSION_1   GRE_VERSION_1
+typedef struct pptp_gre_header ecm_gre_hdr_pptp;
+#endif
+
+/*
+ * Flow/Return direction types.
+ */
+enum ecm_conn_dir {
+	ECM_CONN_DIR_FLOW,
+	ECM_CONN_DIR_RETURN,
+	ECM_CONN_DIR_MAX
+};
+
+/*
+ * Rule update types.
+ */
+enum ecm_rule_update_type {
+	ECM_RULE_UPDATE_TYPE_CONNMARK,
+	ECM_RULE_UPDATE_TYPE_MAX
+};
+
+/*
+ * The ECM IP address is an array of 4 32 bit numbers.
+ * This is enough to record both an IPv6 address aswell as an IPv4 address.
+ * IPv4 addresses are stored encoded in an IPv6 as the usual ::FFFF:x:y/96
+ * We store IP addresses in host order format and NOT network order which is different to Linux network internals.
+ */
+typedef uint32_t ip_addr_t[4];
+
+/*
+ * 32/64 bits pointer type
+ */
+#ifdef __LP64__
+typedef uint64_t ecm_ptr_t;
+#else
+typedef uint32_t ecm_ptr_t;
+#endif
+
+#define ECM_IP_ADDR_OCTAL_FMT "%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x"
+#define ECM_IP_ADDR_DOT_FMT "%u.%u.%u.%u"
+
+#define ECM_IP_ADDR_TO_OCTAL(ipaddrt) ((uint16_t *)ipaddrt)[7], ((uint16_t *)ipaddrt)[6], ((uint16_t *)ipaddrt)[5], ((uint16_t *)ipaddrt)[4], ((uint16_t *)ipaddrt)[3], ((uint16_t *)ipaddrt)[2], ((uint16_t *)ipaddrt)[1], ((uint16_t *)ipaddrt)[0]
+
+#define ECM_IP_ADDR_TO_DOT(ipaddrt) ((uint8_t *)ipaddrt)[3], ((uint8_t *)ipaddrt)[2], ((uint8_t *)ipaddrt)[1], ((uint8_t *)ipaddrt)[0]
+
+#define ECM_IP_ADDR_MATCH(a, b) \
+	((a[0] == b[0]) && (a[1] == b[1]) && (a[2] == b[2]) && (a[3] == b[3]))
+
+#define ECM_IP_ADDR_MASK_MATCH(addr, mask) \
+	(((addr[0] & mask[0]) == mask[0]) && ((addr[1] & mask[1]) == mask[1]) && \
+	((addr[2] & mask[2]) == mask[2]) && ((addr[3] & mask[3]) == mask[3]))
+
+#define ECM_PORT_MASK_MATCH(port, mask)  ((port & mask) == mask)
+#define ECM_PROTO_MASK_MATCH(proto, mask)  ((proto & mask) == mask)
+
+#define ECM_MAC_ADDR_MATCH(a, b) \
+	((((uint16_t *)a)[0] == (((uint16_t *)b)[0])) && \
+	(((uint16_t *)a)[1] == (((uint16_t *)b)[1])) && \
+	(((uint16_t *)a)[2] == (((uint16_t *)b)[2])))
+
+#define ECM_IP_ADDR_IS_V4(a) \
+	((a[1] == 0x0000ffff) && !a[2] && !a[3])
+
+#define ECM_IP_ADDR_IS_NULL(a) \
+	((a[0] | a[1] | a[2] | a[3]) == 0)
+
+#define ECM_IP_ADDR_NULL {0, 0, 0, 0}
+
+#define ECM_MAC_ADDR_STR_BUFF_SIZE		18	/* This is the size of a string in the format of aa:bb:cc:dd:ee:ff */
+#define ECM_IP_ADDR_STR_BUFF_SIZE		40	/* This is the size of a string in the format of aaaa:bbbb:cccc:0000:1111:dddd:eeee:ffff */
+#define ECM_IP_ADDR_DOT_FMT_STR_BUFF_SIZE	16	/* This is the size of a string in the format of 192.168.100.200 */
+
+/*
+ * Type checking functions for various forms of IP address
+ * Placing these in a macro, enables the compiler to check
+ * that the caller is doing the right thing.
+ */
+static inline void ecm_type_check_ecm_ip_addr(ip_addr_t ipaddr){}
+static inline void ecm_type_check_linux_ipv4(__be32 ipaddr){}
+static inline void ecm_type_check_ae_ipv4(uint32_t addr){}
+static inline void ecm_type_check_linux_ipv6(struct in6_addr in6){}
+static inline void ecm_type_check_ae_ipv6(uint32_t ip6[4]){}
+
+/*
+ * This macro copies ip_addr_t's
+ * It's usually quicker than a memcpy().
+ */
+#define __ECM_IP_ADDR_COPY_NO_CHECK(d, s) \
+	{ \
+		d[0] = s[0]; \
+		d[1] = s[1]; \
+		d[2] = s[2]; \
+		d[3] = s[3]; \
+	}
+
+#define ECM_IP_ADDR_COPY(d,s) \
+	{ \
+		ecm_type_check_ecm_ip_addr(d); \
+		ecm_type_check_ecm_ip_addr(s); \
+		__ECM_IP_ADDR_COPY_NO_CHECK(d,s); \
+	}
+
+#define ECM_IP_ADDR_HASH(h, a) \
+	{ \
+		ecm_type_check_ecm_ip_addr(a); \
+		h = a[0] ^ a[1] ^ a[2] ^ a[3]; \
+	}
+
+/*
+ * This macro converts from Linux IPv4 address (network order) to ECM ip_addr_t
+ */
+#define ECM_NIN4_ADDR_TO_IP_ADDR(ipaddrt, nin4) \
+	{ \
+		ecm_type_check_ecm_ip_addr(ipaddrt); \
+		ecm_type_check_linux_ipv4(nin4); \
+		ipaddrt[0] = ntohl(nin4); \
+		ipaddrt[1] = 0x0000ffff; \
+		ipaddrt[2] = 0x00000000; \
+		ipaddrt[3] = 0x00000000; \
+	}
+
+/*
+ * This macro converts from ECM ip_addr_t to Linux network IPv4 address
+ */
+#define ECM_IP_ADDR_TO_NIN4_ADDR(nin4, ipaddrt) \
+	{ \
+		nin4 = 0; \
+		ecm_type_check_linux_ipv4(nin4); \
+		ecm_type_check_ecm_ip_addr(ipaddrt); \
+		DEBUG_ASSERT(!ipaddrt[3] && !ipaddrt[2] && (ipaddrt[1] == 0x0000ffff), "Not IPv4 address: " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(ipaddrt)); \
+		nin4 = htonl(ipaddrt[0]); \
+	}
+
+/*
+ * This macro converts from Linux IPv4 address (host order) to ECM ip_addr_t
+ */
+#define ECM_HIN4_ADDR_TO_IP_ADDR(ipaddrt, hin4) \
+	{ \
+		ecm_type_check_linux_ipv4(hin4); \
+		ecm_type_check_ecm_ip_addr(ipaddrt); \
+		ipaddrt[0] = hin4; \
+		ipaddrt[1] = 0x0000ffff; \
+		ipaddrt[2] = 0x00000000; \
+		ipaddrt[3] = 0x00000000; \
+	}
+
+/*
+ * This macro converts from ECM ip_addr_t to Linux Host IPv4 address
+ */
+#define ECM_IP_ADDR_TO_HIN4_ADDR(hin4, ipaddrt) \
+	{ \
+		ecm_type_check_linux_ipv4(hin4); \
+		ecm_type_check_ecm_ip_addr(ipaddrt); \
+		DEBUG_ASSERT(!ipaddrt[3] && !ipaddrt[2] && (ipaddrt[1] == 0x0000ffff), "Not IPv4 address: " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(ipaddrt)); \
+		hin4 = ipaddrt[0]; \
+	}
+
+#define ECM_LINUX6_TO_IP_ADDR(d,s) \
+	{ \
+		ecm_type_check_ecm_ip_addr(d); \
+		ecm_type_check_ae_ipv6(s); \
+		__ECM_IP_ADDR_COPY_NO_CHECK(d,s); \
+	}
+
+#define ECM_IP_ADDR_TO_LINUX6(d,s) \
+	{ \
+		ecm_type_check_ae_ipv6(d); \
+		ecm_type_check_ecm_ip_addr(s); \
+		__ECM_IP_ADDR_COPY_NO_CHECK(d,s); \
+	}
+
+/*
+ * This macro converts from Linux IPv6 address (network order) to ECM ip_addr_t
+ */
+#define ECM_NIN6_ADDR_TO_IP_ADDR(ipaddrt, nin6) \
+	{ \
+		ecm_type_check_ecm_ip_addr(ipaddrt); \
+		ecm_type_check_linux_ipv6(nin6); \
+		ipaddrt[0] = ntohl(nin6.in6_u.u6_addr32[3]); \
+		ipaddrt[1] = ntohl(nin6.in6_u.u6_addr32[2]); \
+		ipaddrt[2] = ntohl(nin6.in6_u.u6_addr32[1]); \
+		ipaddrt[3] = ntohl(nin6.in6_u.u6_addr32[0]); \
+	}
+
+/*
+ * This macro converts from ECM ip_addr_t to Linux IPv6 address (network order)
+ */
+#define ECM_IP_ADDR_TO_NIN6_ADDR(nin6, ipaddrt) \
+	{ \
+		ecm_type_check_linux_ipv6(nin6); \
+		ecm_type_check_ecm_ip_addr(ipaddrt); \
+		nin6.in6_u.u6_addr32[3] = htonl(ipaddrt[0]); \
+		nin6.in6_u.u6_addr32[2] = htonl(ipaddrt[1]); \
+		nin6.in6_u.u6_addr32[1] = htonl(ipaddrt[2]); \
+		nin6.in6_u.u6_addr32[0] = htonl(ipaddrt[3]); \
+	}
+
+/*
+ * This macro converts from Linux IPv6 address (host order) to ECM ip_addr_t
+ */
+#define ECM_HIN6_ADDR_TO_IP_ADDR(ipaddrt, hin6) \
+	{ \
+		ecm_type_check_ecm_ip_addr(ipaddrt); \
+		ecm_type_check_linux_ipv6(hin6); \
+		ipaddrt[0] = hin6.in6_u.u6_addr32[3]; \
+		ipaddrt[1] = hin6.in6_u.u6_addr32[2]; \
+		ipaddrt[2] = hin6.in6_u.u6_addr32[1]; \
+		ipaddrt[3] = hin6.in6_u.u6_addr32[0]; \
+	}
+
+/*
+ * This macro converts from ECM ip_addr_t to Linux IPv6 address (host order)
+ */
+#define ECM_IP_ADDR_TO_HIN6_ADDR(hin6, ipaddrt) \
+	{ \
+		ecm_type_check_linux_ipv6(hin6); \
+		ecm_type_check_ecm_ip_addr(ipaddrt); \
+		hin6.in6_u.u6_addr32[0] = ipaddrt[3]; \
+		hin6.in6_u.u6_addr32[1] = ipaddrt[2]; \
+		hin6.in6_u.u6_addr32[2] = ipaddrt[1]; \
+		hin6.in6_u.u6_addr32[3] = ipaddrt[0]; \
+	}
+
+/*
+ * ecm_mac_addr_equal()
+ *	Compares two MAC addresses.
+ */
+static inline bool ecm_mac_addr_equal(const u8 *addr1, const u8 *addr2)
+{
+	return !ether_addr_equal(addr1, addr2);
+}
+
+/*
+ * ecm_ip_addr_is_non_unicast()
+ *	Returns true if the IP address is not unicast
+ */
+static inline bool ecm_ip_addr_is_non_unicast(ip_addr_t addr)
+{
+	uint32_t v4_addr = addr[0];
+
+#ifdef ECM_IPV6_ENABLE
+	if (!ECM_IP_ADDR_IS_V4(addr)) {
+		/*
+		 * IPv6
+		 * ff00::0/8 are multicast
+		 */
+		if (ECM_IP_ADDR_IS_NULL(addr) || ((addr[3] & 0xff000000) == 0xff000000)) {
+			return true;
+		}
+		return false;
+	}
+#endif
+
+	if (ECM_IP_ADDR_IS_NULL(addr) || ((v4_addr & 0xe0000000) == 0xe0000000)) {
+		return true;
+	}
+	return false;
+}
+
+/*
+ * ecm_ip_addr_is_multicast()
+ *	Returns true if the IP address is multicast
+ */
+static inline bool ecm_ip_addr_is_multicast(ip_addr_t addr)
+{
+	uint32_t v4_addr = addr[0];
+
+#ifdef ECM_IPV6_ENABLE
+	if (!ECM_IP_ADDR_IS_V4(addr)) {
+		/*
+		 * IPv6
+		 * ff00::0/8 are multicast
+		 */
+		if (((addr[3] & 0xff000000) == 0xff000000)) {
+			return true;
+		}
+		return false;
+	}
+#endif
+
+	if (((v4_addr & 0xf0000000) == 0xe0000000)) {
+		return true;
+	}
+	return false;
+}
+
+#ifdef ECM_MULTICAST_ENABLE
+/*
+ * ecm_translate_multicast_mac()
+ * 	Create the multicast MAC address given a multicast IP address
+ */
+static inline void ecm_translate_multicast_mac(ip_addr_t addr, unsigned char multicast_mac[])
+{
+	uint32_t ip_addr = addr[0];
+
+	if (ECM_IP_ADDR_IS_V4(addr)) {
+		multicast_mac[0] = 0x01;
+		multicast_mac[1] = 0x00;
+		multicast_mac[2] = 0x5e;
+		multicast_mac[3] = (ip_addr & 0x7f0000) >> 16;
+		multicast_mac[4] = (ip_addr & 0xff00) >> 8;
+		multicast_mac[5] = (ip_addr & 0xff);
+		return;
+	}
+
+	multicast_mac[0] = 0x33;
+	multicast_mac[1] = 0x33;
+	multicast_mac[2] = (ip_addr & 0xff000000) >> 24;
+	multicast_mac[3] = (ip_addr & 0xff0000) >> 16;
+	multicast_mac[4] = (ip_addr & 0xff00) >> 8;
+	multicast_mac[5] = (ip_addr & 0xff);
+}
+#endif
+
+/*
+ * ecm_ip_addr_in_range()
+ *	Tests if a is >= s && <= e
+ */
+static inline bool ecm_ip_addr_in_range(ip_addr_t a, ip_addr_t s, ip_addr_t e)
+{
+	if (a[3] > s[3]) goto test_end;
+	if (a[3] < s[3]) return false;
+	/* a[3] == s[3] */
+	if (a[2] > s[2]) goto test_end;
+	if (a[2] < s[2]) return false;
+	/* a[2] == s[2] */
+	if (a[1] > s[1]) goto test_end;
+	if (a[1] < s[1]) return false;
+	/* a[1] == s[1] */
+	if (a[0] > s[0]) goto test_end;
+	if (a[0] < s[0]) return false;
+	/* a[0] == s[0] */
+
+test_end:
+	;
+	if (a[3] > e[3]) return false;
+	if (a[3] < e[3]) return true;
+	/* a[3] == e[3] */
+	if (a[2] > e[2]) return false;
+	if (a[2] < e[2]) return true;
+	/* a[2] == e[2] */
+	if (a[1] > e[1]) return false;
+	if (a[1] < e[1]) return true;
+	/* a[1] == e[1] */
+	if (a[0] > e[0]) return false;
+	/* a[0] <= e[0] */
+	return true;
+}
+
+/*
+ * ecm_ip_addr_to_string()
+ *	Converts the given address to a string either as octal or dotted format
+ *
+ * Supplied buffer should be at least 40 bytes long.
+ */
+static inline void ecm_ip_addr_to_string(char *str, ip_addr_t a)
+{
+#ifdef ECM_IPV6_ENABLE
+	if (!ECM_IP_ADDR_IS_V4(a)) {
+		snprintf(str, ECM_IP_ADDR_STR_BUFF_SIZE, ECM_IP_ADDR_OCTAL_FMT, ECM_IP_ADDR_TO_OCTAL(a));
+		return;
+	}
+#endif
+
+	snprintf(str, ECM_IP_ADDR_DOT_FMT_STR_BUFF_SIZE, ECM_IP_ADDR_DOT_FMT, ECM_IP_ADDR_TO_DOT(a));
+}
+
+/*
+ * ecm_string_to_ip_addr()
+ *	Convert a string IP address to its ECM ip_addr_t representation
+ */
+static inline bool ecm_string_to_ip_addr(ip_addr_t addr, char *ip_str)
+{
+	struct in6_addr dbuf;
+	uint8_t *dptr = dbuf.s6_addr;
+	if (in4_pton(ip_str, -1, dptr, '\0', NULL) > 0) {
+		/*
+		 * IPv4
+		 */
+		ECM_NIN4_ADDR_TO_IP_ADDR(addr, dbuf.s6_addr[0]);
+		return true;
+	}
+#ifdef ECM_IPV6_ENABLE
+	if (in6_pton(ip_str, -1, dptr, '\0', NULL) > 0) {
+		/*
+		 * IPv6
+		 */
+		ECM_NIN6_ADDR_TO_IP_ADDR(addr, dbuf);
+		return true;
+	}
+#endif
+	return false;
+}
+
+/*
+ * The following are debug macros used throughout the ECM.
+ * Each file that #includes this file MUST have a:
+ *
+ * #define DEBUG_LEVEL X
+ *
+ * before the inclusion of this file.
+ * X is:
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ * NOTE: But X is usually provided by a -D preprocessor defined in the Makefile
+ */
+#if (DEBUG_LEVEL < 1)
+#define DEBUG_ASSERT(s, ...)
+#define DEBUG_ERROR(s, ...)
+#define DEBUG_ERROR_RATELIMITED(s, ...)
+#define DEBUG_CHECK_MAGIC(i, m, s, ...)
+#define DEBUG_SET_MAGIC(i, m)
+#define DEBUG_CLEAR_MAGIC(i)
+#define DEBUG_ECM_IP_ADDR_TO_STRING(addr_str, addr)
+#else
+#define DEBUG_ASSERT(c, s, ...) if (!(c)) { pr_emerg("ASSERT: %s:%d:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__); BUG(); }
+#define DEBUG_ERROR(s, ...) pr_err("%s:%d:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define DEBUG_ERROR_RATELIMITED(s, ...) pr_err_ratelimited("%s:%d:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define DEBUG_CHECK_MAGIC(i, m, s, ...) if (i->magic != m) { DEBUG_ASSERT(false, s, ##__VA_ARGS__); }
+#define DEBUG_SET_MAGIC(i, m) i->magic = m
+#define DEBUG_CLEAR_MAGIC(i) i->magic = 0
+#define DEBUG_ECM_IP_ADDR_TO_STRING(addr_str, addr) ecm_ip_addr_to_string(addr_str, addr);
+#endif
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define DEBUG_WARN(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define DEBUG_INFO(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define DEBUG_TRACE(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#if (DEBUG_LEVEL < 2)
+#define DEBUG_WARN(s, ...)
+#else
+#define DEBUG_WARN(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (DEBUG_LEVEL < 3)
+#define DEBUG_INFO(s, ...)
+#else
+#define DEBUG_INFO(s, ...) pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (DEBUG_LEVEL < 4)
+#define DEBUG_TRACE(s, ...)
+#else
+#define DEBUG_TRACE(s, ...) pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif
+#endif
diff --git a/qca-nss-ecm/examples/ecm_ae_select.c b/qca-nss-ecm/examples/ecm_ae_select.c
new file mode 100644
index 0000000..7c33afb
--- /dev/null
+++ b/qca-nss-ecm/examples/ecm_ae_select.c
@@ -0,0 +1,104 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/skbuff.h>
+#include <linux/ctype.h>
+#include <linux/etherdevice.h>
+
+#include "ecm_ae_classifier_public.h"
+
+/*
+ * This is the module which selects the underlying acceleration engine
+ * based ont eh 5-tuple and type of the flow. The flow can be multicast, routed,
+ * bridged, ported/non-ported.
+ */
+
+/*
+ * ecm_ae_select()
+ *	Selects the acceleration engine based on the given flow information.
+ */
+ecm_ae_classifier_result_t ecm_ae_select(struct ecm_ae_classifier_info *info)
+{
+	pr_debug("%px: Acceleration engine selection\n", info);
+
+	/*
+	 * Multicast flows can be accelerated by NSS only.
+	 */
+	if (info->flag & ECM_AE_CLASSIFIER_FLOW_MULTICAST) {
+		return ECM_AE_CLASSIFIER_RESULT_NSS;
+	}
+
+	/*
+	 * Non-ported flows can be accelerated by NSS only.
+	 */
+	if (info->protocol != IPPROTO_TCP && info->protocol != IPPROTO_UDP) {
+		return ECM_AE_CLASSIFIER_RESULT_NSS;
+	}
+
+	/*
+	 * Let's accelerate all other routed flows by SFE.
+	 */
+	if (info->flag & ECM_AE_CLASSIFIER_FLOW_ROUTED) {
+		return ECM_AE_CLASSIFIER_RESULT_SFE;
+	}
+
+	/*
+	 * Let's accelerate all bridge flows by NSS.
+	 */
+	return ECM_AE_CLASSIFIER_RESULT_NSS;
+}
+
+static struct ecm_ae_classifier_ops ae_ops = {
+	.ae_get = ecm_ae_select
+};
+
+/*
+ * ecm_ae_select_init()
+ */
+static int __init ecm_ae_select_init(void)
+{
+	pr_info("ECM AE Select INIT\n");
+
+	/*
+	 * Register the callbacks.
+	 */
+	ecm_ae_classifier_ops_register(&ae_ops);
+
+	return 0;
+}
+
+/*
+ * ecm_ae_select_exit()
+ */
+static void __exit ecm_ae_select_exit(void)
+{
+	pr_info("ECM AE Select EXIT\n");
+
+	/*
+	 * Unregister the callbacks.
+	 */
+	ecm_ae_classifier_ops_unregister();
+}
+
+module_init(ecm_ae_select_init)
+module_exit(ecm_ae_select_exit)
+
+MODULE_DESCRIPTION("ECM Acceleration Engine Selection Module");
+#ifdef MODULE_LICENSE
+MODULE_LICENSE("Dual BSD/GPL");
+#endif
diff --git a/qca-nss-ecm/examples/ecm_mark_test.c b/qca-nss-ecm/examples/ecm_mark_test.c
new file mode 100644
index 0000000..467fb58
--- /dev/null
+++ b/qca-nss-ecm/examples/ecm_mark_test.c
@@ -0,0 +1,135 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/skbuff.h>
+#include <linux/ctype.h>
+#include <linux/if_pppox.h>
+
+#include "ecm_classifier_mark_public.h"
+
+/*
+ * This is a test module for the ECM's mark CLassifier.
+ * It is just extracting the PPPoE session ID from the skb and returns
+ * it to the caller. The test module also receives IPv4 and IPv6 sync messages
+ * from the classifer which includes the PPPoE session ID.
+ */
+
+/*
+ * ecm_mark_test_sync_to_ipv6()
+ *	IPv6 sync callback function registered with ECM.
+ */
+static void ecm_mark_test_sync_to_ipv6(uint32_t mark,
+				       struct in6_addr *src_ip, int src_port,
+				       struct in6_addr *dest_ip, int dest_port,
+				       int protocol)
+{
+	pr_info("ecm_mark_test_sync_to_ipv6, mark: %d\n", (uint16_t)mark);
+
+	/*
+	 * Do whatever you wnat with this PPPoE session ID.
+	 */
+}
+
+/*
+ * ecm_mark_test_sync_to_ipv4()
+ *	IPv4 sync callback function registered with ECM.
+ */
+static void ecm_mark_test_sync_to_ipv4(uint32_t mark,
+				       __be32 src_ip, int src_port,
+				       __be32 dest_ip, int dest_port,
+				       int protocol)
+{
+	pr_info("ecm_mark_test_sync_to_ipv4, mark: %d\n", (uint16_t)mark);
+
+	/*
+	 * Do whatever you wnat with this PPPoE session ID.
+	 */
+}
+
+/*
+ * ecm_mark_test_get_mark()
+ *	Mark get callback function registered with ECM.
+ */
+static ecm_classifier_mark_result_t ecm_mark_test_get_mark(struct sk_buff *skb, uint32_t *mark)
+{
+	struct pppoe_hdr *ph;
+
+	/*
+	 * If the protocol is not something we care about, we are not relevant to this packet.
+	 * In this test module we inspect only the PPPoE session packets.
+	 */
+	if (ntohs(skb->protocol) != ETH_P_PPP_SES) {
+		pr_info("ETH_P_PPP_SES: %d skb->protocol: %d\n", ETH_P_PPP_SES, ntohs(skb->protocol));
+		return ECM_CLASSIFIER_MARK_RESULT_NOT_RELEVANT;
+	}
+
+	ph = pppoe_hdr(skb);
+	pr_info("PPPoE session ID: %x\n", ntohs(ph->sid));
+	*mark = ntohs(ph->sid);
+
+	/*
+	 * Inspection is success.
+	 */
+	return ECM_CLASSIFIER_MARK_RESULT_SUCCESS;
+}
+
+/*
+ * ecm_mark_test_init()
+ */
+static int __init ecm_mark_test_init(void)
+{
+	int res;
+
+	pr_info("ECM MARK Test INIT\n");
+
+	/*
+	 * Register the callbacks with the ECM mark classifier.
+	 */
+	res = ecm_classifier_mark_register_callbacks(ECM_CLASSIFIER_MARK_TYPE_L2_ENCAP,
+					       ecm_mark_test_get_mark,
+					       ecm_mark_test_sync_to_ipv4,
+					       ecm_mark_test_sync_to_ipv6);
+	if (res < 0) {
+		pr_warn("Failed to register callbacks for L2_ENCAP type\n");
+		return res;
+	}
+
+	return 0;
+}
+
+/*
+ * ecm_mark_test_exit()
+ */
+static void __exit ecm_mark_test_exit(void)
+{
+	pr_info("ECM MARK Test EXIT\n");
+
+	/*
+	 * Unregister the callbacks.
+	 */
+	ecm_classifier_mark_unregister_callbacks(ECM_CLASSIFIER_MARK_TYPE_L2_ENCAP);
+}
+
+module_init(ecm_mark_test_init)
+module_exit(ecm_mark_test_exit)
+
+MODULE_DESCRIPTION("ECM MARK Test");
+#ifdef MODULE_LICENSE
+MODULE_LICENSE("Dual BSD/GPL");
+#endif
+
diff --git a/qca-nss-ecm/examples/ecm_ovs.c b/qca-nss-ecm/examples/ecm_ovs.c
new file mode 100644
index 0000000..788bec0
--- /dev/null
+++ b/qca-nss-ecm/examples/ecm_ovs.c
@@ -0,0 +1,218 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019-2020, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/skbuff.h>
+#include <linux/ctype.h>
+#include <linux/etherdevice.h>
+
+#include <ovsmgr.h>
+#include "ecm_classifier_ovs_public.h"
+
+/*
+ * This is a test module for the ECM's ovs CLassifier.
+ * It is extracting the VLAN information based on the flow information.
+ */
+
+/*
+ * ecm_ovs_dump_flow()
+ * 	Show OVS flow contents
+ */
+static void ecm_ovs_dump_flow(struct ovsmgr_dp_flow *flow)
+{
+	pr_debug("OVS DP Flow:\n");
+	if (flow->indev) {
+		pr_debug("\tindev: %s\n", flow->indev->name);
+	} else {
+		pr_debug("\tindev: NULL\n");
+	}
+
+	if (flow->outdev) {
+		pr_debug("\toutdev: %s\n", flow->outdev->name);
+	} else {
+		pr_debug("\toutdev: NULL\n");
+	}
+
+	pr_debug("\tSMAC: %pM\n", &flow->smac);
+	pr_debug("\tSMAC: %pM\n", &flow->dmac);
+	pr_debug("\tingress_vlan: %d:%x\n", flow->ingress_vlan.h_vlan_TCI, flow->ingress_vlan.h_vlan_encapsulated_proto);
+	pr_debug("\tTuple: V: %d, P: %d, SP: %d, DP: %d\n", flow->tuple.ip_version, flow->tuple.protocol,
+			flow->tuple.src_port, flow->tuple.dst_port);
+
+	if (flow->tuple.ip_version == 4) {
+		pr_debug("\t\tSIP: %pI4, DIP: %pI4\n", &flow->tuple.ipv4.src, &flow->tuple.ipv4.dst);
+	} else {
+		pr_debug("\t\tSIP: %pI6, DIP: %pI6\n", &flow->tuple.ipv6.src, &flow->tuple.ipv6.dst);
+	}
+}
+
+/*
+ * ecm_ovs_get_ovs()
+ *	OVS get callback function registered with ECM.
+ */
+static ecm_classifier_ovs_result_t ecm_ovs_process(struct ovsmgr_dp_flow *flow, struct sk_buff *skb, struct ecm_classifier_ovs_process_response *resp)
+{
+	struct ovsmgr_flow_info ofi;
+	enum ovsmgr_flow_status status;
+
+	pr_debug("ecm_ovs_process\n");
+
+	memset((void *)&ofi, 0, sizeof(ofi));
+	ecm_ovs_dump_flow(flow);
+
+	status = ovsmgr_flow_info_get(flow, skb, &ofi);
+	if ((status == OVSMGR_FLOW_STATUS_DENY_ACCEL) || (status == OVSMGR_FLOW_STATUS_UNKNOWN)) {
+		pr_debug("%px: Deny accelerating the flow\n", flow);
+		return ECM_CLASSIFIER_OVS_RESULT_DENY_ACCEL;
+	}
+
+	if (status == OVSMGR_FLOW_STATUS_DENY_ACCEL_EGRESS) {
+		pr_debug("%px: Deny accelerating the flow, egress %s is not allowed\n", flow, flow->outdev->name);
+		return ECM_CLASSIFIER_OVS_RESULT_DENY_ACCEL_EGRESS;
+	}
+
+	/*
+	 * get return DSCP value for bridge flow
+	 */
+	if (!flow->is_routed) {
+		struct ovsmgr_flow_info return_ofi;
+		struct ovsmgr_dp_flow return_flow;
+		enum ovsmgr_flow_status return_status;
+
+		memset((void *)&return_ofi, 0, sizeof(return_ofi));
+
+		/*
+		 * Create return flow
+		 */
+		return_flow.indev = flow->outdev;
+		return_flow.outdev = flow->indev;
+		return_flow.tuple.ip_version = flow->tuple.ip_version;
+		return_flow.tuple.protocol = flow->tuple.protocol;
+
+		ether_addr_copy(return_flow.smac, flow->dmac);
+		ether_addr_copy(return_flow.dmac, flow->smac);
+		return_flow.ingress_vlan.h_vlan_TCI = ofi.egress[0].h_vlan_TCI;
+		return_flow.ingress_vlan.h_vlan_encapsulated_proto = ofi.egress[0].h_vlan_encapsulated_proto;
+		return_flow.tuple.src_port = flow->tuple.dst_port;
+		return_flow.tuple.dst_port = flow->tuple.src_port;
+
+		if (return_flow.tuple.ip_version == 4) {
+			return_flow.tuple.ipv4.src = flow->tuple.ipv4.dst;
+			return_flow.tuple.ipv4.dst = flow->tuple.ipv4.src;
+		} else {
+			memcpy(&return_flow.tuple.ipv6.src, &flow->tuple.ipv6.dst, sizeof(return_flow.tuple.ipv6.src));
+			memcpy(&return_flow.tuple.ipv6.dst, &flow->tuple.ipv6.src, sizeof(return_flow.tuple.ipv6.dst));
+		}
+
+		resp->flow_dscp = ofi.dscp;
+		ecm_ovs_dump_flow(&return_flow);
+
+		return_status = ovsmgr_flow_info_get(&return_flow, skb, &return_ofi);
+		if ((return_status == OVSMGR_FLOW_STATUS_DENY_ACCEL) || (return_status == OVSMGR_FLOW_STATUS_UNKNOWN)) {
+			pr_info("%px: Deny accelerating the return flow\n", &return_flow);
+			goto process_flow;
+		}
+
+		resp->return_dscp = return_ofi.dscp;
+	}
+
+process_flow:
+	resp->dscp = ofi.dscp;
+	switch (status) {
+	case OVSMGR_FLOW_STATUS_ALLOW_VLAN_ACCEL:
+	case OVSMGR_FLOW_STATUS_ALLOW_VLAN_QINQ_ACCEL:
+		pr_debug("%px: Accelerate, VLAN data is valid\n", flow);
+		/*
+		 * Outer ingress VLAN
+		 */
+		resp->ingress_vlan[0].h_vlan_TCI = ofi.ingress[0].h_vlan_TCI;
+		resp->ingress_vlan[0].h_vlan_encapsulated_proto = ofi.ingress[0].h_vlan_encapsulated_proto;
+
+		/*
+		 * Outer egress VLAN
+		 */
+		resp->egress_vlan[0].h_vlan_TCI = ofi.egress[0].h_vlan_TCI;
+		resp->egress_vlan[0].h_vlan_encapsulated_proto = ofi.egress[0].h_vlan_encapsulated_proto;
+
+		if (status == OVSMGR_FLOW_STATUS_ALLOW_VLAN_QINQ_ACCEL) {
+			/*
+			 * Inner ingress VLAN
+			 */
+			resp->ingress_vlan[1].h_vlan_TCI = ofi.ingress[1].h_vlan_TCI;
+			resp->ingress_vlan[1].h_vlan_encapsulated_proto = ofi.ingress[1].h_vlan_encapsulated_proto;
+
+			/*
+			 * Inner egress VLAN
+			 */
+			resp->egress_vlan[1].h_vlan_TCI = ofi.egress[1].h_vlan_TCI;
+			resp->egress_vlan[1].h_vlan_encapsulated_proto = ofi.egress[1].h_vlan_encapsulated_proto;
+
+			return ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_QINQ_ACCEL;
+		}
+		return ECM_CLASSIFIER_OVS_RESULT_ALLOW_VLAN_ACCEL;
+	case OVSMGR_FLOW_STATUS_ALLOW_ACCEL:
+		return ECM_CLASSIFIER_OVS_RESULT_ALLOW_ACCEL;
+	default:
+		return ECM_CLASSIFIER_OVS_RESULT_DENY_ACCEL;
+	}
+}
+
+static struct ecm_classifier_ovs_callbacks callbacks = {
+	.ovs_process = ecm_ovs_process,
+};
+
+/*
+ * ecm_ovs_init()
+ */
+static int __init ecm_ovs_init(void)
+{
+	int res;
+
+	pr_info("ECM OVS Test INIT\n");
+
+	/*
+	 * Register the callbacks with the ECM ovs classifier.
+	 */
+	res = ecm_classifier_ovs_register_callbacks(&callbacks);
+	if (res < 0) {
+		pr_warn("Failed to register callbacks for OVS classifier\n");
+		return res;
+	}
+
+	return 0;
+}
+
+/*
+ * ecm_ovs_exit()
+ */
+static void __exit ecm_ovs_exit(void)
+{
+	pr_info("ECM OVS Test EXIT\n");
+
+	/*
+	 * Unregister the callbacks.
+	 */
+	ecm_classifier_ovs_unregister_callbacks();
+}
+
+module_init(ecm_ovs_init)
+module_exit(ecm_ovs_exit)
+
+MODULE_DESCRIPTION("ECM OVS Test");
+#ifdef MODULE_LICENSE
+MODULE_LICENSE("Dual BSD/GPL");
+#endif
diff --git a/qca-nss-ecm/examples/ecm_pcc_test.c b/qca-nss-ecm/examples/ecm_pcc_test.c
new file mode 100644
index 0000000..2737729
--- /dev/null
+++ b/qca-nss-ecm/examples/ecm_pcc_test.c
@@ -0,0 +1,1118 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2018, 2021, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/module.h>
+#include <linux/of.h>
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/sysctl.h>
+#include <linux/debugfs.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <asm/unaligned.h>
+#include <linux/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/etherdevice.h>
+
+#include "ecm_classifier_pcc_public.h"
+
+#define MAC_FMT "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx"
+
+#define RULE_FIELDS 13
+
+/*
+ * With feature_flags_support parameter enabled, registrant can provide
+ * additional feature requests (like mirroring) to ECM.
+ * It is disabled by default.
+ */
+bool feature_flags_support = false;
+module_param(feature_flags_support, bool, S_IRUGO);
+MODULE_PARM_DESC(feature_flags_support, "Enable feature flags support");
+
+/*
+ * DebugFS entry object.
+ */
+static struct dentry *ecm_pcc_test_dentry;
+
+/*
+ * Registration
+ */
+struct ecm_classifier_pcc_registrant *ecm_pcc_test_registrant = NULL;
+
+/*
+ * ecm_pcc_test_mirror_info
+ *	Descriptor for mirror feature.
+ */
+struct ecm_pcc_test_mirror_info {
+	char tuple_mirror_dev[IFNAMSIZ];
+	char tuple_ret_mirror_dev[IFNAMSIZ];
+};
+
+/*
+ * Rule table
+ */
+struct ecm_pcc_test_rule {
+	struct list_head list;
+	char name[50];
+	ecm_classifier_pcc_result_t accel;
+	unsigned int proto;
+	uint8_t src_mac[ETH_ALEN];
+	uint8_t dest_mac[ETH_ALEN];
+	int src_port;
+	int dest_port;
+	struct in6_addr src_addr;
+	struct in6_addr dest_addr;
+	unsigned int ipv;
+	unsigned int feature_flags;
+	struct ecm_pcc_test_mirror_info mirror_info;
+};
+LIST_HEAD(ecm_pcc_test_rules);
+DEFINE_SPINLOCK(ecm_pcc_test_rules_lock);
+
+/*
+ * ecm_pcc_test_registrant_ref()
+ *	Invoked when an additional hold is kept upon the registrant
+ */
+static void ecm_pcc_test_registrant_ref(struct ecm_classifier_pcc_registrant *r)
+{
+	int remain;
+
+	/*
+	 * Increment the ref count by 1.
+	 * This causes the registrant structure to remain in existance until
+	 * released (deref).
+	 * By definition the caller of this method has a hold on the registrant
+	 * already so it cannot 'go away'.
+	 * This is because either:
+	 * 1. The caller itself has been passed it in a function parameter;
+	 * 2. It has its own explicit hold.
+	 */
+	remain = atomic_inc_return(&r->ref_count);
+	if (remain <= 0)
+		pr_info("REFERENCE COUNT WRAP!\n");
+	else
+		pr_info("ECM PCC Registrant ref: %d\n", remain);
+}
+
+/*
+ * ecm_pcc_test_registrant_deref()
+ *	Caller is releasing its hold upon the registrant.
+ */
+static void
+ecm_pcc_test_registrant_deref(struct ecm_classifier_pcc_registrant *r)
+{
+	int remain;
+	struct ecm_pcc_test_rule *tmp = NULL;
+	struct list_head *pos, *q;
+
+	/*
+	 * Decrement the reference count
+	 */
+	remain = atomic_dec_return(&r->ref_count);
+	if (remain > 0) {
+		/*
+		 * Something still holds a reference
+		 */
+		pr_info("ECM PCC Registrant deref: %d\n", remain);
+		return;
+	}
+
+	/*
+	 * Last hold upon the registrant is released and so we can now
+	 * destroy it.
+	 */
+	if (remain < 0)
+		pr_info("REFERENCE COUNT WRAP!\n");
+
+	spin_lock_bh(&ecm_pcc_test_rules_lock);
+	list_for_each_safe(pos, q , &ecm_pcc_test_rules) {
+		tmp = list_entry(pos, struct ecm_pcc_test_rule, list);
+		list_del(pos);
+		kfree(tmp);
+	}
+	spin_unlock_bh(&ecm_pcc_test_rules_lock);
+
+	pr_info("ECM PCC Registrant DESTROYED\n");
+	kfree(r);
+}
+
+/*
+ * __ecm_pcc_test_rule_find()
+ *	Return matching rule
+ */
+static struct
+ecm_pcc_test_rule *__ecm_pcc_test_rule_find(unsigned int proto,
+					    uint8_t *src_mac,
+					    uint8_t *dest_mac,
+					    struct in6_addr *src_addr,
+					    struct in6_addr *dest_addr,
+					    int src_port, int dest_port,
+					    bool *is_reverse)
+{
+	struct ecm_pcc_test_rule *rule = NULL;
+
+	list_for_each_entry(rule , &ecm_pcc_test_rules, list) {
+		if (rule->proto != proto)
+			continue;
+
+		if (rule->src_port != src_port)
+			goto try_reverse;
+		if (rule->dest_port != dest_port)
+			goto try_reverse;
+		if (!ipv6_addr_equal(&rule->src_addr, src_addr))
+			goto try_reverse;
+		if (!ipv6_addr_equal(&rule->dest_addr, dest_addr))
+			goto try_reverse;
+
+		return rule;
+
+try_reverse:
+
+		if (rule->src_port != dest_port)
+			continue;
+		if (rule->dest_port != src_port)
+			continue;
+		if (!ipv6_addr_equal(&rule->src_addr, dest_addr))
+			continue;
+		if (!ipv6_addr_equal(&rule->dest_addr, src_addr))
+			continue;
+
+		if (is_reverse) {
+			*is_reverse = true;
+		}
+
+		return rule;
+	}
+	return NULL;
+}
+
+/*
+ * ecm_pcc_test_fill_mirror_info()
+ *	Fill mirror feature related information.
+ */
+static int ecm_pcc_test_fill_mirror_info(struct ecm_pcc_test_rule *rule,
+		struct ecm_classifier_pcc_info *cinfo, bool is_reverse)
+{
+	struct net_device *tuple_mirror_netdev = NULL, *tuple_ret_mirror_netdev = NULL;
+
+	/*
+	 * Get the name of the mirror device from the rule and fetch
+	 * its netdevice structure.
+	 */
+	if (strlen(rule->mirror_info.tuple_mirror_dev)) {
+		tuple_mirror_netdev = dev_get_by_name(&init_net, rule->mirror_info.tuple_mirror_dev);
+		if (!tuple_mirror_netdev) {
+			pr_warn("Cannot find flow mirror device (%s)\n", rule->mirror_info.tuple_mirror_dev);
+			return -1;
+		}
+		pr_info("Tuple mirror device: %s\n", tuple_mirror_netdev->name);
+		dev_put(tuple_mirror_netdev);
+	}
+
+	if (strlen(rule->mirror_info.tuple_ret_mirror_dev)) {
+		tuple_ret_mirror_netdev = dev_get_by_name(&init_net, rule->mirror_info.tuple_ret_mirror_dev);
+		if (!tuple_ret_mirror_netdev) {
+			pr_warn("Cannot find return mirror device (%s)\n", rule->mirror_info.tuple_ret_mirror_dev);
+			return -1;
+		}
+		pr_info("Tuple return mirror device: %s\n", tuple_ret_mirror_netdev->name);
+		dev_put(tuple_ret_mirror_netdev);
+	}
+
+	/*
+	 * Pass mirror netdevices of both direction to ECM.
+	 */
+	if (!is_reverse) {
+		cinfo->mirror.tuple_mirror_dev = tuple_mirror_netdev;
+		cinfo->mirror.tuple_ret_mirror_dev = tuple_ret_mirror_netdev;
+	} else {
+		cinfo->mirror.tuple_mirror_dev = tuple_ret_mirror_netdev;
+		cinfo->mirror.tuple_ret_mirror_dev = tuple_mirror_netdev;
+	}
+
+	return 0;
+}
+
+/*
+ * ecm_pcc_test_get_accel_info_v4()
+ *	Invoked by the ECM to query if the given connection may be accelerated
+ *	and to get the set of features to be enabled on it.
+ */
+static ecm_classifier_pcc_result_t
+ecm_pcc_test_get_accel_info_v4(struct ecm_classifier_pcc_registrant *r,
+			      uint8_t *src_mac, __be32 src_ip, int src_port,
+			      uint8_t *dest_mac, __be32 dest_ip, int dest_port,
+			      int protocol, struct ecm_classifier_pcc_info *cinfo)
+{
+	struct ecm_pcc_test_rule *rule;
+	ecm_classifier_pcc_result_t accel;
+	struct in6_addr src_addr = IN6ADDR_ANY_INIT;
+	struct in6_addr dest_addr = IN6ADDR_ANY_INIT;
+	unsigned int feature_flags;
+	bool is_reverse = false;
+
+	src_addr.s6_addr32[0] = src_ip;
+	dest_addr.s6_addr32[0] = dest_ip;
+
+	if (!cinfo) {
+		pr_err("Invalid input parameter\n");
+		return ECM_CLASSIFIER_PCC_RESULT_NOT_YET;
+	}
+
+	spin_lock_bh(&ecm_pcc_test_rules_lock);
+	rule = __ecm_pcc_test_rule_find(protocol, src_mac, dest_mac,
+			&src_addr, &dest_addr,
+			src_port, dest_port, &is_reverse);
+	if (!rule) {
+		spin_unlock_bh(&ecm_pcc_test_rules_lock);
+		pr_info("Rule not found\n");
+		return ECM_CLASSIFIER_PCC_RESULT_NOT_YET;
+	}
+	accel = rule->accel;
+	feature_flags= rule->feature_flags;
+
+	/*
+	 * Check if mirror feature is enabled on the rule.
+	 * if enabled, then pass mirror netdevs for both the direction
+	 * to ECM.
+	 */
+	if (feature_flags & ECM_CLASSIFIER_PCC_FEATURE_MIRROR) {
+		if (ecm_pcc_test_fill_mirror_info(rule, cinfo, is_reverse)) {
+			spin_unlock_bh(&ecm_pcc_test_rules_lock);
+			return ECM_CLASSIFIER_PCC_RESULT_NOT_YET;
+		}
+	}
+
+	spin_unlock_bh(&ecm_pcc_test_rules_lock);
+
+	cinfo->feature_flags = feature_flags;
+	return accel;
+}
+
+/*
+ * ecm_pcc_test_get_accel_info_v6()
+ *	Invoked by the ECM to query if the given connection may be accelerated
+ *	and to get the set of features to be enabled on it.
+ */
+static ecm_classifier_pcc_result_t
+ecm_pcc_test_get_accel_info_v6(struct ecm_classifier_pcc_registrant *r,
+			      uint8_t *src_mac, struct in6_addr *src_addr,
+			      int src_port, uint8_t *dest_mac,
+			      struct in6_addr *dest_addr, int dest_port,
+			      int protocol, struct ecm_classifier_pcc_info *cinfo)
+{
+	struct ecm_pcc_test_rule *rule;
+	ecm_classifier_pcc_result_t accel;
+	unsigned int feature_flags;
+	bool is_reverse = false;
+
+	if (!cinfo) {
+		pr_err("Invalid input parameter\n");
+		return ECM_CLASSIFIER_PCC_RESULT_NOT_YET;
+	}
+
+	spin_lock_bh(&ecm_pcc_test_rules_lock);
+	rule = __ecm_pcc_test_rule_find(protocol, src_mac, dest_mac,
+			src_addr, dest_addr,
+			src_port, dest_port, &is_reverse);
+	if (!rule) {
+		spin_unlock_bh(&ecm_pcc_test_rules_lock);
+		return ECM_CLASSIFIER_PCC_RESULT_NOT_YET;
+	}
+	accel = rule->accel;
+	feature_flags= rule->feature_flags;
+
+	/*
+	 * Check if mirror feature is enabled on the rule.
+	 * if enabled, then pass mirror netdevs for both the direction
+	 * to ECM.
+	 */
+	if (feature_flags & ECM_CLASSIFIER_PCC_FEATURE_MIRROR) {
+		if (ecm_pcc_test_fill_mirror_info(rule, cinfo, is_reverse)) {
+			spin_unlock_bh(&ecm_pcc_test_rules_lock);
+			return ECM_CLASSIFIER_PCC_RESULT_NOT_YET;
+		}
+	}
+
+	spin_unlock_bh(&ecm_pcc_test_rules_lock);
+
+	cinfo->feature_flags = feature_flags;
+	return accel;
+}
+
+/*
+ * ecm_pcc_test_okay_to_accel_v4()
+ *	Invoked by the ECM to query if the given connection may be accelerated
+ */
+static ecm_classifier_pcc_result_t
+ecm_pcc_test_okay_to_accel_v4(struct ecm_classifier_pcc_registrant *r,
+			      uint8_t *src_mac, __be32 src_ip, int src_port,
+			      uint8_t *dest_mac, __be32 dest_ip, int dest_port,
+			      int protocol)
+{
+	struct ecm_pcc_test_rule *rule;
+	ecm_classifier_pcc_result_t accel;
+	struct in6_addr src_addr = IN6ADDR_ANY_INIT;
+	struct in6_addr dest_addr = IN6ADDR_ANY_INIT;
+
+	src_addr.s6_addr32[0] = src_ip;
+	dest_addr.s6_addr32[0] = dest_ip;
+
+	spin_lock_bh(&ecm_pcc_test_rules_lock);
+	rule = __ecm_pcc_test_rule_find(protocol, src_mac, dest_mac,
+			&src_addr, &dest_addr,
+			src_port, dest_port, NULL);
+	if (!rule) {
+		spin_unlock_bh(&ecm_pcc_test_rules_lock);
+		return ECM_CLASSIFIER_PCC_RESULT_NOT_YET;
+	}
+	accel = rule->accel;
+	spin_unlock_bh(&ecm_pcc_test_rules_lock);
+
+	return accel;
+}
+
+/*
+ * ecm_pcc_test_okay_to_accel_v6()
+ *	Invoked by the ECM to query if the given connection may be accelerated
+ */
+static ecm_classifier_pcc_result_t
+ecm_pcc_test_okay_to_accel_v6(struct ecm_classifier_pcc_registrant *r,
+			      uint8_t *src_mac, struct in6_addr *src_addr,
+			      int src_port, uint8_t *dest_mac,
+			      struct in6_addr *dest_addr, int dest_port,
+			      int protocol)
+{
+	struct ecm_pcc_test_rule *rule;
+	ecm_classifier_pcc_result_t accel;
+
+	spin_lock_bh(&ecm_pcc_test_rules_lock);
+	rule = __ecm_pcc_test_rule_find(protocol, src_mac, dest_mac,
+			src_addr, dest_addr,
+			src_port, dest_port, NULL);
+	if (!rule) {
+		spin_unlock_bh(&ecm_pcc_test_rules_lock);
+		return ECM_CLASSIFIER_PCC_RESULT_NOT_YET;
+	}
+	accel = rule->accel;
+	spin_unlock_bh(&ecm_pcc_test_rules_lock);
+	return accel;
+}
+
+/*
+ * ecm_pcc_test_unregister_get_unregister()
+ */
+static int ecm_pcc_test_unregister_get_unregister(void *data, u64 *val)
+{
+	*val = 0;
+	return 0;
+}
+
+/*
+ * ecm_pcc_test_unregister_set_unregister()
+ */
+static int ecm_pcc_test_unregister_set_unregister(void *data, u64 val)
+{
+	if (ecm_pcc_test_registrant) {
+		pr_info("ECM PCC Test unregister\n");
+		ecm_classifier_pcc_unregister_begin(ecm_pcc_test_registrant);
+		ecm_pcc_test_registrant = NULL;
+	}
+	return 0;
+}
+
+/*
+ * ecm_pcc_test_str_to_ip()
+ *	Convert string IP to in6_addr.  Return 4 for IPv4 or 6 for IPv6.
+	Return something else in error.
+ *
+ * NOTE: When string is IPv4 the lower 32 bit word of the in6 address
+ * contains the address. Network order.
+ */
+static unsigned int ecm_pcc_test_str_to_ip(char *ip_str, struct in6_addr *addr)
+{
+	uint8_t *ptr = (uint8_t *)(addr->s6_addr);
+
+	/*
+	 * IPv4 address in addr->s6_addr32[0]
+	 */
+	if (in4_pton(ip_str, -1, ptr, '\0', NULL) > 0)
+		return 4;
+
+	/*
+	 * IPv6
+	 */
+	if (in6_pton(ip_str, -1, ptr, '\0', NULL) > 0)
+		return 6;
+
+	return 0;
+}
+
+/*
+ * ecm_pcc_test_decel()
+ *	Decelerate the flow.
+ */
+static void ecm_pcc_test_decel(unsigned int proto,
+		uint8_t *src_mac, uint8_t *dest_mac,
+		struct in6_addr *src_addr, struct in6_addr *dest_addr,
+		int src_port, int dest_port,
+		unsigned int ipv)
+{
+	bool ret;
+
+	if (ipv == 4) {
+		ret = ecm_classifier_pcc_decel_v4(src_mac,
+						src_addr->s6_addr32[0],
+						src_port, dest_mac,
+						dest_addr->s6_addr32[0],
+						dest_port, proto);
+	} else {
+		ret = ecm_classifier_pcc_decel_v6(src_mac, src_addr, src_port,
+						dest_mac, dest_addr, dest_port,
+						proto);
+	}
+
+	if (!ret) {
+		pr_warn("Decel operation failed, ret: %d\n", ret);
+	}
+}
+
+/*
+ * ecm_pcc_test_deny_accel()
+ *	Deny acceleration
+ */
+static void ecm_pcc_test_deny_accel(unsigned int proto,
+		uint8_t *src_mac, uint8_t *dest_mac,
+		struct in6_addr *src_addr, struct in6_addr *dest_addr,
+		int src_port, int dest_port,
+		unsigned int ipv)
+{
+	if (ipv == 4)
+		ecm_classifier_pcc_deny_accel_v4(src_mac,
+						src_addr->s6_addr32[0],
+						src_port, dest_mac,
+						dest_addr->s6_addr32[0],
+						dest_port, proto);
+	else
+		ecm_classifier_pcc_deny_accel_v6(src_mac, src_addr, src_port,
+						dest_mac, dest_addr, dest_port,
+						proto);
+}
+
+/*
+ * ecm_pcc_test_permit_accel()
+ *	Permit acceleration
+ */
+static void ecm_pcc_test_permit_accel(unsigned int proto,
+		uint8_t *src_mac, uint8_t *dest_mac,
+		struct in6_addr *src_addr, struct in6_addr *dest_addr,
+		int src_port, int dest_port,
+		unsigned int ipv)
+{
+	if (ipv == 4)
+		ecm_classifier_pcc_permit_accel_v4(src_mac,
+						src_addr->s6_addr32[0],
+						src_port, dest_mac,
+						dest_addr->s6_addr32[0],
+						dest_port, proto);
+	else
+		ecm_classifier_pcc_permit_accel_v6(src_mac, src_addr, src_port,
+						dest_mac, dest_addr, dest_port,
+						proto);
+
+}
+
+/*
+ * ecm_pcc_test_update_rule()
+ *	Update a rule, return 0 on failure. If change in accel this will
+ *	inform ECM.
+ */
+static unsigned int ecm_pcc_test_update_rule(char *name,
+				ecm_classifier_pcc_result_t accel,
+				unsigned int proto,
+				uint8_t *src_mac, uint8_t *dest_mac,
+				struct in6_addr *src_addr,
+				struct in6_addr *dest_addr,
+				int src_port, int dest_port, unsigned int feature_flags,
+				char *tuple_mirror_dev, char *tuple_ret_mirror_dev)
+{
+	unsigned int ipv, o_feature_flags;
+	struct ecm_pcc_test_rule *rule;
+	ecm_classifier_pcc_result_t oaccel;
+
+	spin_lock_bh(&ecm_pcc_test_rules_lock);
+	rule = __ecm_pcc_test_rule_find(proto, src_mac, dest_mac,
+			src_addr, dest_addr, src_port, dest_port, NULL);
+	if (!rule) {
+		spin_unlock_bh(&ecm_pcc_test_rules_lock);
+		return 0;
+	}
+	ipv = rule->ipv;
+	oaccel = rule->accel;
+	o_feature_flags = rule->feature_flags;
+	rule->accel = accel;
+	rule->feature_flags = feature_flags;
+	strcpy(rule->name, name);
+	strlcpy(rule->mirror_info.tuple_mirror_dev, tuple_mirror_dev, IFNAMSIZ);
+	strlcpy(rule->mirror_info.tuple_ret_mirror_dev, tuple_ret_mirror_dev, IFNAMSIZ);
+	spin_unlock_bh(&ecm_pcc_test_rules_lock);
+
+	if (feature_flags_support) {
+		/*
+		 * To have things simple, for now the per field check on the old
+		 * and new rule to figure out whether the rule has actually changed
+		 * or not is being avoided.
+		 *
+		 * If the old or new rule has the mirror flag set, then decelerate
+		 * the connection to have in effect the updated values.
+		 */
+		if ((o_feature_flags & ECM_CLASSIFIER_PCC_FEATURE_MIRROR) ||
+			(feature_flags & ECM_CLASSIFIER_PCC_FEATURE_MIRROR)) {
+			ecm_pcc_test_decel(proto, src_mac, dest_mac,
+					src_addr, dest_addr, src_port, dest_port, ipv);
+			return 1;
+		}
+	}
+
+	if (oaccel == accel)
+		return 1;
+
+	if (accel == ECM_CLASSIFIER_PCC_RESULT_DENIED)
+		ecm_pcc_test_deny_accel(proto, src_mac, dest_mac,
+			src_addr, dest_addr, src_port, dest_port, ipv);
+	else
+		ecm_pcc_test_permit_accel(proto, src_mac, dest_mac,
+			src_addr, dest_addr, src_port, dest_port, ipv);
+
+	return 1;
+}
+
+/*
+ * ecm_pcc_test_delete_rule()
+ *	Delete a rule, return 0 on failure.  If deleted connection rule denied
+ *	accel this will permit accel.
+ */
+static unsigned int ecm_pcc_test_delete_rule(char *name,
+				ecm_classifier_pcc_result_t accel,
+				unsigned int proto,
+				uint8_t *src_mac, uint8_t *dest_mac,
+				struct in6_addr *src_addr,
+				struct in6_addr *dest_addr,
+				int src_port, int dest_port)
+{
+	unsigned int ipv, feature_flags;
+	struct ecm_pcc_test_rule *rule;
+
+	spin_lock_bh(&ecm_pcc_test_rules_lock);
+	rule = __ecm_pcc_test_rule_find(proto, src_mac, dest_mac,
+			src_addr, dest_addr, src_port, dest_port, NULL);
+	if (!rule) {
+		spin_unlock_bh(&ecm_pcc_test_rules_lock);
+		return 0;
+	}
+	ipv = rule->ipv;
+	accel = rule->accel;
+	feature_flags = rule->feature_flags;
+	list_del(&rule->list);
+	spin_unlock_bh(&ecm_pcc_test_rules_lock);
+	kfree(rule);
+
+	if (feature_flags_support) {
+		/*
+		 * If mirror flag is set in the rule, then decelerate the
+		 * existing connection, since the rule is getting deleted.
+		 * The new acceleration decision for this flow should be
+		 * taken by the get_accel_info_v4/v6 APIs.
+		 */
+		if (feature_flags & ECM_CLASSIFIER_PCC_FEATURE_MIRROR) {
+			ecm_pcc_test_decel(proto, src_mac, dest_mac,
+					src_addr, dest_addr, src_port, dest_port, ipv);
+			return 1;
+		}
+	}
+
+	if (accel == ECM_CLASSIFIER_PCC_RESULT_DENIED)
+		ecm_pcc_test_permit_accel(proto, src_mac, dest_mac,
+			src_addr, dest_addr, src_port, dest_port, ipv);
+
+	return 1;
+}
+
+/*
+ * ecm_pcc_test_add_rule()
+ *	Add a new rule, return 0 on failure.  Given accel the ecm is informed
+ *	of permit/deny accel status.
+ */
+static unsigned int ecm_pcc_test_add_rule(char *name,
+				ecm_classifier_pcc_result_t accel,
+				unsigned int proto,
+				uint8_t *src_mac, uint8_t *dest_mac,
+				struct in6_addr *src_addr,
+				struct in6_addr *dest_addr,
+				int src_port, int dest_port,
+				unsigned int ipv, unsigned int feature_flags,
+				char *tuple_mirror_dev, char *tuple_ret_mirror_dev)
+{
+	struct ecm_pcc_test_rule *new_rule;
+	new_rule = kzalloc(sizeof(struct ecm_pcc_test_rule), GFP_ATOMIC);
+	if (!new_rule)
+		return 0;
+
+	strcpy(new_rule->name, name);
+	new_rule->accel = accel;
+	new_rule->proto = proto;
+	new_rule->src_port = src_port;
+	new_rule->dest_port = dest_port;
+	ether_addr_copy(new_rule->src_mac, src_mac);
+	ether_addr_copy(new_rule->dest_mac, dest_mac);
+	new_rule->src_addr = *src_addr;
+	new_rule->dest_addr = *dest_addr;
+	new_rule->ipv = ipv;
+	new_rule->feature_flags = feature_flags;
+	strlcpy(new_rule->mirror_info.tuple_mirror_dev, tuple_mirror_dev, IFNAMSIZ);
+	strlcpy(new_rule->mirror_info.tuple_ret_mirror_dev, tuple_ret_mirror_dev, IFNAMSIZ);
+	INIT_LIST_HEAD(&new_rule->list);
+
+	spin_lock_bh(&ecm_pcc_test_rules_lock);
+	list_add(&new_rule->list, &ecm_pcc_test_rules);
+	spin_unlock_bh(&ecm_pcc_test_rules_lock);
+
+	if (feature_flags_support) {
+		/*
+		 * Return as we don't want to set the accel permit state to
+		 * permit or deny. We want our registrant's callback to be get
+		 * called so that it can fetch the mirror netdev and pass it to
+		 * ECM.
+		 */
+		if (feature_flags & ECM_CLASSIFIER_PCC_FEATURE_MIRROR) {
+			return 1;
+		}
+	}
+
+	if (accel == ECM_CLASSIFIER_PCC_RESULT_DENIED)
+		ecm_pcc_test_deny_accel(proto, src_mac, dest_mac,
+			src_addr, dest_addr, src_port, dest_port, ipv);
+	else
+		ecm_pcc_test_permit_accel(proto, src_mac, dest_mac,
+			src_addr, dest_addr, src_port, dest_port, ipv);
+
+	return 1;
+}
+
+/*
+ * ecm_pcc_test_rule_write()
+ *	Write a rule
+ */
+static ssize_t ecm_pcc_test_rule_write(struct file *file,
+		const char __user *user_buf, size_t count, loff_t *ppos)
+{
+	char *rule_buf;
+	int field_count;
+	char *field_ptr;
+	char *fields[RULE_FIELDS];
+	char name[50];
+	char tuple_mirror_dev[IFNAMSIZ] = {0};
+	char tuple_ret_mirror_dev[IFNAMSIZ] = {0};
+	uint8_t src_mac[ETH_ALEN];
+	uint8_t dest_mac[ETH_ALEN];
+	unsigned int oper;
+	unsigned int feature_flags;
+	ecm_classifier_pcc_result_t accel;
+	unsigned int proto;
+	int src_port;
+	int dest_port;
+	struct in6_addr src_addr = IN6ADDR_ANY_INIT;
+	struct in6_addr dest_addr = IN6ADDR_ANY_INIT;
+	unsigned int ipv;
+
+	/*
+	 * buf is formed as:
+	 * [0]    [1]                 [2]                           [3]     [4]       [5]        [6]        [7]        [8]         [9]         [10]            [11]               [12]
+	 * <name>/<0=del,1=add,2=upd>/<1=denied, 2=accel_permitted>/<proto>/<src_mac>/<src_addr>/<src_port>/<dest mac>/<dest_addr>/<dest_port>/<feature_flags>/<tuple_mirror_dev>/<tuple_ret_mirror_dev>
+	 * e.g.:
+	 * echo "my_rule/1/2/6/00:12:12:34:56:78/192.168.1.33/1234/00:12:12:34:56:22/10.10.10.10/80/1/mirror.0/mirror.1" > /sys/kernel/debug/ecm_pcc_test/rule
+	 * cat /sys/kernel/debug/ecm_pcc_test/rule (shows all rules)
+	 */
+	rule_buf = kzalloc(count + 1, GFP_ATOMIC);
+	if (!rule_buf)
+		return -EINVAL;
+
+	memcpy(rule_buf, user_buf, count);
+
+	/*
+	 * Split the buffer into its fields
+	 */
+	field_count = 0;
+	field_ptr = rule_buf;
+	fields[field_count] = strsep(&field_ptr, "/");
+	while (fields[field_count] != NULL) {
+		pr_info("Field %d: %s\n", field_count, fields[field_count]);
+		field_count++;
+		if (field_count == RULE_FIELDS)
+			break;
+
+		fields[field_count] = strsep(&field_ptr, "/ \n");
+	}
+
+	if (field_count != RULE_FIELDS) {
+		pr_info("Invalid field count %d\n", field_count);
+		kfree(rule_buf);
+		return -EINVAL;
+	}
+
+	/*
+	 * Convert fields
+	 */
+	strncpy(name, fields[0], sizeof(name));
+	name[sizeof(name) - 1] = 0;
+	if (sscanf(fields[1], "%u", &oper) != 1)
+		goto sscanf_read_error;
+
+	if (sscanf(fields[2], "%d", (int *)&accel) != 1)
+		goto sscanf_read_error;
+
+	switch (accel) {
+	case ECM_CLASSIFIER_PCC_RESULT_DENIED:
+	case ECM_CLASSIFIER_PCC_RESULT_PERMITTED:
+		break;
+	default:
+		pr_info("Bad accel: %u\n", accel);
+		kfree(rule_buf);
+		return -EINVAL;
+	}
+
+	if (sscanf(fields[3], "%u", &proto) != 1)
+		goto sscanf_read_error;
+
+	if (sscanf(fields[6], "%d", &src_port) != 1)
+		goto sscanf_read_error;
+
+	src_port = htons(src_port);
+
+	if (sscanf(fields[9], "%d", &dest_port) != 1)
+		goto sscanf_read_error;
+
+	if (sscanf(fields[10], "%u", &feature_flags) != 1) {
+		goto sscanf_read_error;
+	}
+
+	strlcpy(tuple_mirror_dev, fields[11], IFNAMSIZ);
+
+	strlcpy(tuple_ret_mirror_dev, fields[12], IFNAMSIZ);
+
+	dest_port = htons(dest_port);
+
+	if (sscanf(fields[4], MAC_FMT, src_mac, src_mac + 1, src_mac + 2,
+		src_mac + 3, src_mac + 4, src_mac + 5) != 6)
+		goto sscanf_read_error;
+
+	if (sscanf(fields[7], MAC_FMT, dest_mac, dest_mac + 1, dest_mac + 2,
+			dest_mac + 3, dest_mac + 4, dest_mac + 5) != 6)
+		goto sscanf_read_error;
+
+	ipv = ecm_pcc_test_str_to_ip(fields[5], &src_addr);
+	if (ipv != ecm_pcc_test_str_to_ip(fields[8], &dest_addr)) {
+		pr_info("Conflicting IP address types\n");
+		kfree(rule_buf);
+		return -EINVAL;
+	}
+	kfree(rule_buf);
+
+	pr_info("name: %s\n"
+			"oper: %u\n"
+			"accel: %d\n"
+			"proto: %u\n"
+			"%pM\n"
+			"%pI6:%d\n"
+			"%pM\n"
+			"%pI6:%d\n"
+			"ipv: %u\n"
+			"feature_flags: %0x\n"
+			"tuple_mirror_dev: %s\n"
+			"tuple_ret_mirror_dev: %s\n",
+			name,
+			oper,
+			(int)accel,
+			proto,
+			src_mac,
+			&src_addr,
+			ntohs(src_port),
+			dest_mac,
+			&dest_addr,
+			ntohs(dest_port),
+			ipv,
+			feature_flags,
+			tuple_mirror_dev,
+			tuple_ret_mirror_dev
+			);
+
+	if (oper == 0) {
+		pr_info("Delete\n");
+		if (!ecm_pcc_test_delete_rule(name, accel, proto, src_mac,
+						dest_mac, &src_addr, &dest_addr,
+						src_port, dest_port))
+			return -EINVAL;
+
+	} else if (oper == 1) {
+		pr_info("Add\n");
+		if (!ecm_pcc_test_add_rule(name, accel, proto, src_mac,
+						dest_mac, &src_addr, &dest_addr,
+						src_port, dest_port, ipv,
+						feature_flags, tuple_mirror_dev,
+						tuple_ret_mirror_dev))
+			return -EINVAL;
+
+	} else if (oper == 2) {
+		pr_info("Update\n");
+		if (!ecm_pcc_test_update_rule(name, accel, proto, src_mac,
+						dest_mac, &src_addr, &dest_addr,
+						src_port, dest_port, feature_flags,
+						tuple_mirror_dev, tuple_ret_mirror_dev))
+			return -EINVAL;
+
+	} else {
+		pr_info("Unknown operation: %u\n", oper);
+		return -EINVAL;
+	}
+
+	return count;
+
+sscanf_read_error:
+	pr_info("sscanf read error\n");
+	kfree(rule_buf);
+	return -EINVAL;
+}
+
+/*
+ * ecm_pcc_test_rule_seq_show()
+ */
+static int ecm_pcc_test_rule_seq_show(struct seq_file *m, void *v)
+{
+	struct ecm_pcc_test_rule *rule;
+
+	rule = list_entry(v, struct ecm_pcc_test_rule, list);
+
+	seq_printf(m, "RULE:\n"
+			"\tname: %s\n"
+			"\taccel: %d\n"
+			"\tproto: %u\n"
+			"\t"
+			"%pM\n"
+			"\t%pI6:%u\n"
+			"\t"
+			"%pM\n"
+			"\t%pI6:%d\n"
+			"\tipv: %u\n"
+			"\tfeature_flags: %u\n",
+			rule->name,
+			(int)(rule->accel),
+			rule->proto,
+			rule->src_mac,
+			&rule->src_addr,
+			ntohs(rule->src_port),
+			rule->dest_mac,
+			&rule->dest_addr,
+			ntohs(rule->dest_port),
+			rule->ipv,
+			rule->feature_flags
+			);
+
+	if (feature_flags_support) {
+		if (rule->feature_flags & ECM_CLASSIFIER_PCC_FEATURE_MIRROR) {
+			if (strlen(rule->mirror_info.tuple_mirror_dev)) {
+				seq_printf(m, "mirror_tuple_dev: %s\n",
+						rule->mirror_info.tuple_mirror_dev);
+			}
+			if (strlen(rule->mirror_info.tuple_ret_mirror_dev)) {
+				seq_printf(m, "mirror_ret_tuple_dev: %s\n",
+						rule->mirror_info.tuple_ret_mirror_dev);
+			}
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * ecm_pcc_test_rule_seq_stop()
+ */
+static void ecm_pcc_test_rule_seq_stop(struct seq_file *p, void *v)
+{
+	spin_unlock_bh(&ecm_pcc_test_rules_lock);
+}
+
+/*
+ * ecm_pcc_test_rule_seq_start()
+ */
+static void *ecm_pcc_test_rule_seq_start(struct seq_file *m, loff_t *_pos)
+{
+	spin_lock_bh(&ecm_pcc_test_rules_lock);
+	return seq_list_start(&ecm_pcc_test_rules, *_pos);
+}
+
+/*
+ * ecm_pcc_test_rule_seq_next()
+ */
+static void *ecm_pcc_test_rule_seq_next(struct seq_file *p, void *v,
+					loff_t *pos)
+{
+	return seq_list_next(v, &ecm_pcc_test_rules, pos);
+}
+
+/*
+ * DebugFS attributes.
+ */
+DEFINE_SIMPLE_ATTRIBUTE(ecm_pcc_test_unregister_fops,
+			ecm_pcc_test_unregister_get_unregister,
+			ecm_pcc_test_unregister_set_unregister, "%llu\n");
+
+static const struct seq_operations ecm_pcc_test_rule_seq_ops = {
+	.start = ecm_pcc_test_rule_seq_start,
+	.next  = ecm_pcc_test_rule_seq_next,
+	.stop  = ecm_pcc_test_rule_seq_stop,
+	.show  = ecm_pcc_test_rule_seq_show,
+};
+
+/*
+ * ecm_pcc_test_rule_open()
+ */
+static int ecm_pcc_test_rule_open(struct inode *inode, struct file *file)
+{
+	return seq_open(file, &ecm_pcc_test_rule_seq_ops);
+}
+
+/*
+ * ecm_pcc_test_rule_release()
+ */
+static int ecm_pcc_test_rule_release(struct inode *inode, struct file *file)
+{
+	return seq_release(inode, file);
+}
+
+static const struct file_operations ecm_pcc_test_rule_fops = {
+	.owner		= THIS_MODULE,
+	.open		= ecm_pcc_test_rule_open,
+	.write		= ecm_pcc_test_rule_write,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= ecm_pcc_test_rule_release,
+};
+
+/*
+ * ecm_pcc_test_init()
+ */
+static int __init ecm_pcc_test_init(void)
+{
+	int result;
+
+	pr_info("ECM PCC Test INIT\n");
+
+	/*
+	 * Create entries in DebugFS for control functions
+	 */
+	ecm_pcc_test_dentry = debugfs_create_dir("ecm_pcc_test", NULL);
+	if (!ecm_pcc_test_dentry) {
+		pr_info("Failed to create PCC directory entry\n");
+		return -1;
+	}
+	if (!debugfs_create_file("unregister",
+			S_IRUGO | S_IWUSR, ecm_pcc_test_dentry,
+			NULL, &ecm_pcc_test_unregister_fops)) {
+		pr_info("Failed to create ecm_pcc_test_unregister_fops\n");
+		debugfs_remove_recursive(ecm_pcc_test_dentry);
+		return -2;
+	}
+	if (!debugfs_create_file("rule",
+			S_IRUGO | S_IWUSR, ecm_pcc_test_dentry,
+			NULL, &ecm_pcc_test_rule_fops)) {
+		pr_info("Failed to create ecm_pcc_test_rule_fops\n");
+		debugfs_remove_recursive(ecm_pcc_test_dentry);
+		return -3;
+	}
+
+	/*
+	 * Create our registrant structure
+	 */
+	ecm_pcc_test_registrant = (struct ecm_classifier_pcc_registrant *)
+			kzalloc(sizeof(struct ecm_classifier_pcc_registrant),
+				GFP_ATOMIC | __GFP_NOWARN);
+	if (!ecm_pcc_test_registrant) {
+		pr_info("ECM PCC Failed to alloc registrant\n");
+		debugfs_remove_recursive(ecm_pcc_test_dentry);
+		return -4;
+	}
+	ecm_pcc_test_registrant->version = 1;
+	ecm_pcc_test_registrant->this_module = THIS_MODULE;
+	ecm_pcc_test_registrant->ref = ecm_pcc_test_registrant_ref;
+	ecm_pcc_test_registrant->deref = ecm_pcc_test_registrant_deref;
+
+	/*
+	 * If feature flag support is not enabled then fill
+	 * okay_to_accel_v4/okay_to_accel_v6 callbacks instead
+	 * of get_accel_info_v4/get_accel_info_v6 callbacks in the
+	 * registrant's descriptor.
+	 */
+	if (!feature_flags_support) {
+		ecm_pcc_test_registrant->okay_to_accel_v4 =
+			ecm_pcc_test_okay_to_accel_v4;
+		ecm_pcc_test_registrant->okay_to_accel_v6 =
+			ecm_pcc_test_okay_to_accel_v6;
+	} else {
+		ecm_pcc_test_registrant->get_accel_info_v4 =
+			ecm_pcc_test_get_accel_info_v4;
+		ecm_pcc_test_registrant->get_accel_info_v6 =
+			ecm_pcc_test_get_accel_info_v6;
+	}
+
+	/*
+	 * Register with the PCC Classifier. ECM classifier will take a ref for
+	 * registrant.
+	 */
+	result = ecm_classifier_pcc_register(ecm_pcc_test_registrant);
+	if (result != 0) {
+		pr_info("ECM PCC registrant failed to register: %d\n", result);
+		kfree(ecm_pcc_test_registrant);
+		debugfs_remove_recursive(ecm_pcc_test_dentry);
+		return -5;
+	}
+
+	pr_info("ECM PCC registrant REGISTERED\n");
+
+	return 0;
+}
+
+/*
+ * ecm_pcc_test_exit()
+ */
+static void __exit ecm_pcc_test_exit(void)
+{
+	pr_info("ECM PCC Test EXIT\n");
+	debugfs_remove_recursive(ecm_pcc_test_dentry);
+}
+
+module_init(ecm_pcc_test_init)
+module_exit(ecm_pcc_test_exit)
+
+MODULE_DESCRIPTION("ECM PCC Test");
+#ifdef MODULE_LICENSE
+MODULE_LICENSE("Dual BSD/GPL");
+#endif
+
diff --git a/qca-nss-ecm/examples/ecm_sfe_l2.c b/qca-nss-ecm/examples/ecm_sfe_l2.c
new file mode 100644
index 0000000..dd64653
--- /dev/null
+++ b/qca-nss-ecm/examples/ecm_sfe_l2.c
@@ -0,0 +1,1085 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/module.h>
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/debugfs.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <linux/etherdevice.h>
+#include <linux/inet.h>
+
+#include "exports/ecm_sfe_common_public.h"
+
+/*
+ * Global WAN interface name parameter.
+ */
+char wan_name[IFNAMSIZ];
+int wan_name_len;
+
+/*
+ * DebugFS entry object.
+ */
+static struct dentry *ecm_sfe_l2_dentry;
+
+/*
+ * Policy rule directions.
+ */
+enum ecm_sfe_l2_policy_rule_dir {
+	ECM_SFE_L2_POLICY_RULE_EGRESS = 1,
+	ECM_SFE_L2_POLICY_RULE_INGRESS,
+	ECM_SFE_L2_POLICY_RULE_EGRESS_INGRESS,
+};
+
+/*
+ * Policy rule commands.
+ */
+enum ecm_sfe_l2_policy_rule_cmd {
+	ECM_SFE_L2_POLICY_RULE_ADD = 1,
+	ECM_SFE_L2_POLICY_RULE_DEL,
+	ECM_SFE_L2_POLICY_RULE_FLUSH_ALL
+};
+
+/*
+ *  ECM tuple directions.
+ */
+enum ecm_sfe_l2_tuple_dir {
+	ECM_SFE_L2_TUPLE_DIR_ORIGINAL,
+	ECM_SFE_L2_TUPLE_DIR_REPLY,
+};
+
+/*
+ * Defunct by 5-tuple command option types.
+ */
+enum ecm_sfe_l2_defunct_by_5tuple_options {
+	ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_IP_VERSION,
+	ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_SIP,
+	ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_SPORT,
+	ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_DIP,
+	ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_DPORT,
+	ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_PROTOCOL,
+	ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_MAX,
+};
+
+/*
+ * Policy rule structure
+ */
+struct ecm_sfe_l2_policy_rule {
+	struct list_head list;
+	int protocol;
+	int src_port;
+	int dest_port;
+	uint32_t src_addr[4];
+	uint32_t dest_addr[4];
+	int ip_ver;
+	enum ecm_sfe_l2_policy_rule_dir direction;
+};
+
+LIST_HEAD(ecm_sfe_l2_policy_rules);
+DEFINE_SPINLOCK(ecm_sfe_l2_policy_rules_lock);
+
+/*
+ * ecm_sfe_l2_policy_rule_find()
+ *	Finds a policy rule with the given parameters.
+ */
+static struct ecm_sfe_l2_policy_rule *ecm_sfe_l2_policy_rule_find(int ip_ver, uint32_t *sip_addr, int sport,
+								  uint32_t *dip_addr, int dport,
+								  int protocol)
+{
+	struct ecm_sfe_l2_policy_rule *rule = NULL;
+
+	list_for_each_entry(rule , &ecm_sfe_l2_policy_rules, list) {
+		if (rule->ip_ver != ip_ver)
+			continue;
+
+		if (rule->protocol && (rule->protocol != protocol))
+			continue;
+
+		if (rule->dest_port && (rule->dest_port != dport))
+			continue;
+
+		if (rule->src_port && (rule->src_port != sport))
+			continue;
+
+		if (ip_ver == 4) {
+			if (rule->dest_addr[0] && (rule->dest_addr[0] != dip_addr[0]))
+				continue;
+		} else {
+			if (rule->dest_addr[0] && memcmp(rule->dest_addr, dip_addr, sizeof(uint32_t) * 4))
+				continue;
+		}
+
+		if (ip_ver == 4) {
+			if (rule->src_addr[0] && (rule->src_addr[0] != sip_addr[0]))
+				continue;
+		} else {
+			if (rule->src_addr[0] && memcmp(rule->src_addr, sip_addr, sizeof(uint32_t) * 4))
+				continue;
+		}
+
+		return rule;
+	}
+	return NULL;
+}
+
+/*
+ * ecm_sfe_l2_connection_check_with_policy_rules()
+ *	Checks the ECM tuple with the policy rules in our rules list and
+ *	set the L2 acceleration accordingly, if there is a match.
+ */
+static uint32_t ecm_sfe_l2_connection_check_with_policy_rules(struct ecm_sfe_common_tuple *tuple, enum ecm_sfe_l2_tuple_dir tuple_dir)
+{
+	struct ecm_sfe_l2_policy_rule *rule = NULL;
+	enum ecm_sfe_l2_policy_rule_dir direction;
+	uint32_t l2_accel_bits = (ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED | ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED);
+
+	if (tuple_dir == ECM_SFE_L2_TUPLE_DIR_ORIGINAL) {
+		spin_lock_bh(&ecm_sfe_l2_policy_rules_lock);
+		rule = ecm_sfe_l2_policy_rule_find(tuple->ip_ver, tuple->src_addr, tuple->src_port,
+						   tuple->dest_addr, tuple->dest_port, tuple->protocol);
+		if (!rule) {
+			spin_unlock_bh(&ecm_sfe_l2_policy_rules_lock);
+			pr_warn("No rule with this tuple\n");
+			goto done;
+		}
+		direction = rule->direction;
+		spin_unlock_bh(&ecm_sfe_l2_policy_rules_lock);
+
+		if (direction == ECM_SFE_L2_POLICY_RULE_EGRESS) {
+			pr_debug("flow side should be L3 interface\n");
+			l2_accel_bits &= ~ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED;
+		} else if (direction == ECM_SFE_L2_POLICY_RULE_INGRESS) {
+			pr_debug("return side should be L3 interface\n");
+			l2_accel_bits &= ~ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED;
+		}
+	} else if (tuple_dir == ECM_SFE_L2_TUPLE_DIR_REPLY) {
+		spin_lock_bh(&ecm_sfe_l2_policy_rules_lock);
+		rule = ecm_sfe_l2_policy_rule_find(tuple->ip_ver, tuple->dest_addr, tuple->dest_port,
+						   tuple->src_addr, tuple->src_port, tuple->protocol);
+
+		if (!rule) {
+			spin_unlock_bh(&ecm_sfe_l2_policy_rules_lock);
+			pr_warn("No rule with this tuple\n");
+			goto done;
+		}
+		direction = rule->direction;
+		spin_unlock_bh(&ecm_sfe_l2_policy_rules_lock);
+
+		if (direction == ECM_SFE_L2_POLICY_RULE_EGRESS) {
+			pr_debug("return side should be L3 interface\n");
+			l2_accel_bits &= ~ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED;
+		} else if (direction == ECM_SFE_L2_POLICY_RULE_INGRESS) {
+			pr_debug("flow side should be L3 interface\n");
+			l2_accel_bits &= ~ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED;
+		}
+	} else {
+		pr_err("unknow tuple_dir: %d\n", tuple_dir);
+		goto done;
+	}
+
+	if (direction == ECM_SFE_L2_POLICY_RULE_EGRESS_INGRESS) {
+		pr_debug("both sides should be L3 interface\n");
+		l2_accel_bits &= ~ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED;
+		l2_accel_bits &= ~ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED;
+	}
+done:
+	return l2_accel_bits;
+}
+
+/*
+ * ecm_sfe_l2_accel_check_callback()
+ *	L2 acceleration check function callback.
+ */
+uint32_t ecm_sfe_l2_accel_check_callback(struct ecm_sfe_common_tuple *tuple)
+{
+	struct net_device *flow_dev;
+	struct net_device *return_dev;
+	struct net_device *wan_dev;
+	uint32_t l2_accel_bits = (ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED | ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED);
+
+	if (strlen(wan_name) == 0) {
+		pr_debug("WAN interface is not set in the debugfs\n");
+		goto done;
+	}
+
+	wan_dev =  dev_get_by_name(&init_net, wan_name);
+	if (!wan_dev) {
+		pr_debug("WAN interface: %s couldn't be found\n", wan_name);
+		goto done;
+	}
+
+	flow_dev = dev_get_by_index(&init_net, tuple->src_ifindex);
+	if (!flow_dev) {
+		pr_debug("flow netdevice couldn't be found with index: %d\n", tuple->src_ifindex);
+		dev_put(wan_dev);
+		goto done;
+	}
+
+	return_dev = dev_get_by_index(&init_net, tuple->dest_ifindex);
+	if (!return_dev) {
+		pr_debug("return netdevice couldn't be found with index: %d\n", tuple->dest_ifindex);
+		dev_put(wan_dev);
+		dev_put(flow_dev);
+		goto done;
+	}
+
+	if (wan_dev == return_dev) {
+		/*
+		 * Check the tuple with the policy rules in the ORIGINAL direction of the tuple.
+		 */
+		l2_accel_bits = ecm_sfe_l2_connection_check_with_policy_rules(tuple, ECM_SFE_L2_TUPLE_DIR_ORIGINAL);
+	} else if (wan_dev == flow_dev) {
+		/*
+		 * Check the tuple with the policy rules in the REPLY direction of the tuple.
+		 */
+		l2_accel_bits = ecm_sfe_l2_connection_check_with_policy_rules(tuple, ECM_SFE_L2_TUPLE_DIR_REPLY);
+	}
+	dev_put(wan_dev);
+	dev_put(flow_dev);
+	dev_put(return_dev);
+
+done:
+	return l2_accel_bits;
+}
+
+/*
+ * ecm_sfe_l2_flush_policy_rules()
+ *	Flushes all the policy rules.
+ */
+static void ecm_sfe_l2_flush_policy_rules(void)
+{
+	struct ecm_sfe_l2_policy_rule *rule;
+	struct ecm_sfe_l2_policy_rule *tmp;
+
+	spin_lock_bh(&ecm_sfe_l2_policy_rules_lock);
+	list_for_each_entry_safe(rule , tmp, &ecm_sfe_l2_policy_rules, list) {
+		list_del(&rule->list);
+		spin_unlock_bh(&ecm_sfe_l2_policy_rules_lock);
+		kfree(rule);
+		spin_lock_bh(&ecm_sfe_l2_policy_rules_lock);
+	}
+	spin_unlock_bh(&ecm_sfe_l2_policy_rules_lock);
+}
+
+/*
+ * ecm_sfe_l2_delete_policy_rule()
+ *	Deletes a policy rule with the given parameters.
+ */
+static bool ecm_sfe_l2_delete_policy_rule(int ip_ver, uint32_t *sip_addr, int sport, uint32_t *dip_addr, int dport, int protocol)
+{
+	struct ecm_sfe_l2_policy_rule *rule;
+
+	spin_lock_bh(&ecm_sfe_l2_policy_rules_lock);
+	rule = ecm_sfe_l2_policy_rule_find(ip_ver, sip_addr, sport, dip_addr, dport, protocol);
+	if (!rule) {
+		spin_unlock_bh(&ecm_sfe_l2_policy_rules_lock);
+		pr_warn("rule cannot be found in the list\n");
+		return false;
+	}
+	list_del(&rule->list);
+	spin_unlock_bh(&ecm_sfe_l2_policy_rules_lock);
+	kfree(rule);
+
+	pr_info("rule deleted\n");
+	return true;
+}
+
+/*
+ * ecm_sfe_l2_add_policy_rule()
+ *	Adds a policy rule with the given parameters.
+ */
+static bool ecm_sfe_l2_add_policy_rule(int ip_ver, uint32_t *sip_addr, int sport, uint32_t *dip_addr, int dport, int protocol, enum ecm_sfe_l2_policy_rule_dir direction)
+{
+	struct ecm_sfe_l2_policy_rule *rule;
+
+	spin_lock_bh(&ecm_sfe_l2_policy_rules_lock);
+	rule = ecm_sfe_l2_policy_rule_find(ip_ver, sip_addr, sport, dip_addr, dport, protocol);
+	if (rule) {
+		if (rule->direction != direction) {
+			pr_info("Update direction of the rule from %d to %d\n", rule->direction, direction);
+			rule->direction = direction;
+		}
+		spin_unlock_bh(&ecm_sfe_l2_policy_rules_lock);
+		pr_warn("rule is already present\n");
+		return true;
+	}
+	spin_unlock_bh(&ecm_sfe_l2_policy_rules_lock);
+
+	rule = kzalloc(sizeof(struct ecm_sfe_l2_policy_rule), GFP_ATOMIC);
+	if (!rule) {
+		pr_warn("alloc failed for new rule\n");
+		return false;
+	}
+
+	rule->ip_ver = ip_ver;
+	rule->protocol = protocol;
+	rule->src_port = sport;
+	rule->dest_port = dport;
+	memcpy(rule->src_addr, sip_addr, sizeof(uint32_t) * 4);
+	memcpy(rule->dest_addr, dip_addr, sizeof(uint32_t) * 4);
+	rule->direction = direction;
+
+	INIT_LIST_HEAD(&rule->list);
+
+	spin_lock_bh(&ecm_sfe_l2_policy_rules_lock);
+	list_add(&rule->list, &ecm_sfe_l2_policy_rules);
+	spin_unlock_bh(&ecm_sfe_l2_policy_rules_lock);
+
+	pr_info("rule added\n");
+	return true;
+}
+
+/*
+ * ecm_sfe_l2_policy_rule_write()
+ *	Adds a policy rule to the rule table.
+ *
+ * Policy rule must include cmd, ip_ver and direction. It can also include src/dest IP and ports, protocol.
+ * cmd and ip_ver MUST be the first 2 options in the command.
+ */
+static ssize_t ecm_sfe_l2_policy_rule_write(struct file *file,
+		const char __user *user_buf, size_t count, loff_t *offset)
+{
+	char *cmd_buf;
+	char *fields;
+	char *token;
+	char *option, *value;
+	int cmd = 0;		/* must be present in the rule */
+	int ip_ver = 0;	/* must be present in the rule */
+	uint32_t sip_addr[4] = {0};
+	uint32_t dip_addr[4] = {0};
+	int sport = 0;
+	int dport = 0;
+	int protocol = 0;
+	int direction = 0;	/* must be present in the rule */
+
+	/*
+	 * Command is formed as:
+	 * echo "cmd=1 ip_ver=4 dport=443 protocol=6 direction=1" > /sys/kernel/debug/ecm_sfe_l2/policy_rules
+	 *
+	 * cmd: 1 is to add, 2 is to delete a rule.
+	 * direction: 1 is egress, 2 is ingress, 3 is both
+	 */
+	cmd_buf = kzalloc(count + 1, GFP_ATOMIC);
+	if (!cmd_buf) {
+		pr_warn("unable to allocate memory for cmd buffer\n");
+		return -ENOMEM;
+	}
+
+	count = simple_write_to_buffer(cmd_buf, count, offset, user_buf, count);
+
+	/*
+	 * Split the buffer into tokens
+	 */
+	fields = cmd_buf;
+	while ((token = strsep(&fields, " "))) {
+		pr_info("\ntoken: %s\n", token);
+
+		option = strsep(&token, "=");
+		value = token;
+
+		pr_info("\t\toption: %s\n", option);
+		pr_info("\t\tvalue: %s\n", value);
+
+		if (!strcmp(option, "cmd")) {
+			if (sscanf(value, "%d", &cmd)) {
+				if (cmd != ECM_SFE_L2_POLICY_RULE_ADD && cmd != ECM_SFE_L2_POLICY_RULE_DEL &&
+					cmd != ECM_SFE_L2_POLICY_RULE_FLUSH_ALL) {
+					pr_err("invalid cmd value: %d\n", cmd);
+					goto fail;
+				}
+				continue;
+			}
+			pr_warn("cannot read value\n");
+			goto fail;
+		}
+
+		if (!strcmp(option, "ip_ver")) {
+			if (sscanf(value, "%d", &ip_ver)) {
+				if (ip_ver != 4 && ip_ver != 6) {
+					pr_err("invalid ip_ver: %d\n", ip_ver);
+					goto fail;
+				}
+				continue;
+			}
+			pr_warn("cannot read value\n");
+			goto fail;
+		}
+
+		if (!strcmp(option, "protocol")) {
+			if (sscanf(value, "%d", &protocol)) {
+				continue;
+			}
+			pr_warn("cannot read value\n");
+			goto fail;
+		}
+
+		if (!strcmp(option, "sport")) {
+			if (sscanf(value, "%d", &sport)) {
+				continue;
+			}
+			pr_warn("cannot read value\n");
+			goto fail;
+		}
+
+		if (!strcmp(option, "dport")) {
+			if (sscanf(value, "%d", &dport)) {
+				continue;
+			}
+			pr_warn("cannot read value\n");
+			goto fail;
+		}
+
+		if (!strcmp(option, "direction")) {
+			if (cmd == ECM_SFE_L2_POLICY_RULE_DEL) {
+				pr_err("direction is not allowed in delete command\n");
+				goto fail;
+			}
+
+			if (sscanf(value, "%d", &direction)) {
+				if (direction != ECM_SFE_L2_POLICY_RULE_EGRESS
+					&& direction != ECM_SFE_L2_POLICY_RULE_INGRESS
+					&& direction != ECM_SFE_L2_POLICY_RULE_EGRESS_INGRESS) {
+
+					pr_err("invalid direction: %d\n", direction);
+					goto fail;
+				}
+				continue;
+			}
+			pr_warn("cannot read value\n");
+			goto fail;
+		}
+
+		if (!strcmp(option, "sip")) {
+			if (ip_ver == 4) {
+				if (!in4_pton(value, -1, (uint8_t *)&sip_addr[0], -1, NULL)) {
+					pr_err("invalid source IP V4 value: %s\n", value);
+					goto fail;
+				}
+			} else if (ip_ver ==6) {
+				if (!in6_pton(value, -1, (uint8_t *)sip_addr, -1, NULL)) {
+					pr_err("invalid source IP V6 value: %s\n", value);
+					goto fail;
+				}
+			} else {
+				pr_err("ip_ver hasn't been set yet\n");
+				goto fail;
+			}
+			continue;
+		}
+
+		if (!strcmp(option, "dip")) {
+			if (ip_ver == 4) {
+				if (!in4_pton(value, -1, (uint8_t *)&dip_addr[0], -1, NULL)) {
+					pr_err("invalid destination IP V4 value: %s\n", value);
+					goto fail;
+				}
+			} else if (ip_ver == 6) {
+				if (!in6_pton(value, -1, (uint8_t *)dip_addr, -1, NULL)) {
+					pr_err("invalid destination IP V6 value: %s\n", value);
+					goto fail;
+				}
+			} else {
+				pr_err("ip_ver hasn't been set yet\n");
+				goto fail;
+			}
+			continue;
+		}
+
+		pr_warn("unrecognized option: %s\n", option);
+		goto fail;
+	}
+
+	kfree(cmd_buf);
+
+	if (cmd == ECM_SFE_L2_POLICY_RULE_ADD) {
+		if (!ecm_sfe_l2_add_policy_rule(ip_ver, sip_addr, sport, dip_addr, dport, protocol, direction)) {
+			pr_err("Add policy rule failed\n");
+			return -ENOMEM;
+		}
+	} else if (cmd == ECM_SFE_L2_POLICY_RULE_DEL) {
+		if (!ecm_sfe_l2_delete_policy_rule(ip_ver, sip_addr, sport, dip_addr, dport, protocol)) {
+			pr_err("Delete policy rule failed\n");
+			return -ENOMEM;
+		}
+	} else if (cmd == ECM_SFE_L2_POLICY_RULE_FLUSH_ALL) {
+		ecm_sfe_l2_flush_policy_rules();
+	}
+
+	return count;
+fail:
+	kfree(cmd_buf);
+	return -EINVAL;
+}
+
+/*
+ * ecm_sfe_l2_policy_rule_seq_show()
+ */
+static int ecm_sfe_l2_policy_rule_seq_show(struct seq_file *m, void *v)
+{
+	struct ecm_sfe_l2_policy_rule *rule;
+
+	rule = list_entry(v, struct ecm_sfe_l2_policy_rule, list);
+
+	if (rule->ip_ver == 4) {
+		seq_printf(m,	"ip_ver: %d"
+				"\tprotocol: %d"
+				"\tsip_addr: %pI4"
+				"\tdip_addr: %pI4"
+				"\tsport: %d"
+				"\tdport: %d"
+				"\tdirection: %d\n",
+				rule->ip_ver,
+				rule->protocol,
+				&rule->src_addr[0],
+				&rule->dest_addr[0],
+				rule->src_port,
+				rule->dest_port,
+				rule->direction);
+	} else {
+		struct in6_addr saddr;
+		struct in6_addr daddr;
+
+		memcpy(&saddr.s6_addr32, rule->src_addr, sizeof(uint32_t) * 4);
+		memcpy(&daddr.s6_addr32, rule->dest_addr, sizeof(uint32_t) * 4);
+
+		seq_printf(m,	"ip_ver: %d"
+				"\tprotocol: %d"
+				"\tsip_addr: %pI6"
+				"\tdip_addr: %pI6"
+				"\tsport: %d"
+				"\tdport: %d"
+				"\tdirection: %d\n",
+				rule->ip_ver,
+				rule->protocol,
+				&saddr,
+				&daddr,
+				rule->src_port,
+				rule->dest_port,
+				rule->direction);
+	}
+
+	return 0;
+}
+
+/*
+ * ecm_sfe_l2_policy_rule_seq_stop()
+ */
+static void ecm_sfe_l2_policy_rule_seq_stop(struct seq_file *p, void *v)
+{
+	spin_unlock_bh(&ecm_sfe_l2_policy_rules_lock);
+}
+
+/*
+ * ecm_sfe_l2_policy_rule_seq_next()
+ */
+static void *ecm_sfe_l2_policy_rule_seq_next(struct seq_file *p, void *v,
+					loff_t *pos)
+{
+	return seq_list_next(v, &ecm_sfe_l2_policy_rules, pos);
+}
+
+/*
+ * ecm_sfe_l2_policy_rule_seq_start()
+ */
+static void *ecm_sfe_l2_policy_rule_seq_start(struct seq_file *m, loff_t *_pos)
+{
+	spin_lock_bh(&ecm_sfe_l2_policy_rules_lock);
+	return seq_list_start(&ecm_sfe_l2_policy_rules, *_pos);
+}
+
+static const struct seq_operations ecm_sfe_l2_policy_rule_seq_ops = {
+	.start = ecm_sfe_l2_policy_rule_seq_start,
+	.next  = ecm_sfe_l2_policy_rule_seq_next,
+	.stop  = ecm_sfe_l2_policy_rule_seq_stop,
+	.show  = ecm_sfe_l2_policy_rule_seq_show,
+};
+
+/*
+ * ecm_sfe_l2_policy_rule_open()
+ */
+static int ecm_sfe_l2_policy_rule_open(struct inode *inode, struct file *file)
+{
+	return seq_open(file, &ecm_sfe_l2_policy_rule_seq_ops);
+}
+
+/*
+ * File operations for policy rules add/delete/list operations.
+ */
+static const struct file_operations ecm_sfe_l2_policy_rule_fops = {
+	.owner		= THIS_MODULE,
+	.open		= ecm_sfe_l2_policy_rule_open,
+	.write		= ecm_sfe_l2_policy_rule_write,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= seq_release,
+};
+
+/*
+ * ecm_sfe_l2_defunct_by_5tuple_write()
+ *	Writes the defunct by 5-tuple command to the debugfs node.
+ */
+static ssize_t ecm_sfe_l2_defunct_by_5tuple_write(struct file *f, const char *user_buf,
+					  size_t count, loff_t *offset)
+{
+	int ret = -EINVAL;
+	char *cmd_buf;
+	int field_count;
+	char *fields_ptr;
+	char *fields[ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_MAX];
+	char *option, *value;
+	int ip_ver;
+	uint32_t sip_addr_v4;
+	uint32_t dip_addr_v4;
+	struct in6_addr sip_addr_v6;
+	struct in6_addr dip_addr_v6;
+	int sport, dport;
+	int protocol;
+	bool defunct_result;
+
+	/*
+	 * Command is formed as for IPv4 and IPv6 5-tuples as below respectively.
+	 *
+	 * echo "ip_ver=4 sip=192.168.1.100 sport=443 dip=192.168.2.100 dport=1000 protocol=6" > /sys/kernel/debug/ecm_sfe_l2/defunct_by_5tuple
+	 * echo “ip_ver=6 sip=2aaa::100 sport=443 dip=3bbb::200 dport=1000 protocol=6” > /sys/kernel/debug/ecm_sfe_l2/defunct_by_5tuple
+	 *
+	 * The order of the options MUST be as above and it MUST contain all the 5-tuple fields and the ip_ver.
+	 */
+	cmd_buf = kzalloc(count + 1, GFP_ATOMIC);
+	if (!cmd_buf) {
+		pr_warn("unable to allocate memory for cmd buffer\n");
+		return -ENOMEM;
+	}
+
+	count = simple_write_to_buffer(cmd_buf, count, offset, user_buf, count);
+
+	/*
+	 * Split the buffer into its fields
+	 */
+	field_count = 0;
+	fields_ptr = cmd_buf;
+	fields[field_count] = strsep(&fields_ptr, " ");
+	while (fields[field_count] != NULL) {
+		pr_info("Field %d: %s\n", field_count, fields[field_count]);
+		field_count++;
+		if (field_count == ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_MAX)
+			break;
+
+		fields[field_count] = strsep(&fields_ptr, " ");
+	}
+
+	if (field_count != ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_MAX) {
+		kfree(cmd_buf);
+		pr_err("Invalid field count %d\n", field_count);
+		return -EINVAL;
+	}
+
+	/*
+	 * IP version (ip_ver) field validation.
+	 */
+	option = strsep(&fields[ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_IP_VERSION], "=");
+	if (!option || strcmp(option, "ip_ver")) {
+		pr_err("invalid IP version option name: %s\n", option);
+		goto fail;
+	}
+	value = fields[ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_IP_VERSION];
+	if (!sscanf(value, "%d", &ip_ver)) {
+		pr_err("Unable to read IP version value %s\n", value);
+		goto fail;
+	}
+	if (ip_ver != 4 && ip_ver != 6) {
+		pr_err("invalid IP version: %d\n", ip_ver);
+		goto fail;
+	}
+
+	/*
+	 * Source IP (sip) field validation.
+	 */
+	option = strsep(&fields[ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_SIP], "=");
+	if (!option || strcmp(option, "sip")) {
+		pr_err("invalid source IP option name: %s\n", option);
+		goto fail;
+	}
+	value = fields[ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_SIP];
+
+	if (ip_ver == 4) {
+		if (!in4_pton(value, -1, (uint8_t *)&sip_addr_v4, -1, NULL)) {
+			pr_err("invalid source IP V4 value: %s\n", value);
+			goto fail;
+		}
+	} else {
+		if (!in6_pton(value, -1, (uint8_t *)sip_addr_v6.s6_addr, -1, NULL)) {
+			pr_err("invalid source IP V6 value: %s\n", value);
+			goto fail;
+		}
+	}
+
+	/*
+	 * Source port (sport) field validadtion.
+	 */
+	option = strsep(&fields[ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_SPORT], "=");
+	if (!option || strcmp(option, "sport")) {
+		pr_err("invalid source port option name: %s\n", option);
+		goto fail;
+	}
+	value = fields[ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_SPORT];
+	if (!sscanf(value, "%d", &sport)) {
+		pr_err("Unable to read source port value %s\n", value);
+		goto fail;
+	}
+
+	/*
+	 * Destination IP (dip) field validation.
+	 */
+	option = strsep(&fields[ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_DIP], "=");
+	if (!option || strcmp(option, "dip")) {
+		pr_err("invalid destination IP option name: %s\n", option);
+		goto fail;
+	}
+	value = fields[ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_DIP];
+
+	if (ip_ver == 4) {
+		if (!in4_pton(value, -1, (uint8_t *)&dip_addr_v4, -1, NULL)) {
+			pr_err("invalid destination IP V4 value: %s\n", value);
+			goto fail;
+		}
+	} else {
+		if (!in6_pton(value, -1, (uint8_t *)dip_addr_v6.s6_addr, -1, NULL)) {
+			pr_err("invalid destination IP V6 value: %s\n", value);
+			goto fail;
+		}
+	}
+
+	/*
+	 * Destination port (dport) field validadtion.
+	 */
+	option = strsep(&fields[ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_DPORT], "=");
+	if (!option || strcmp(option, "dport")) {
+		pr_err("invalid destination port option name: %s\n", option);
+		goto fail;
+	}
+	value = fields[ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_DPORT];
+	if (!sscanf(value, "%d", &dport)) {
+		pr_err("Unable to read destination port value %s\n", value);
+		goto fail;
+	}
+
+	/*
+	 * Protocol field validadtion.
+	 */
+	option = strsep(&fields[ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_PROTOCOL], "=");
+	if (!option || strcmp(option, "protocol")) {
+		pr_err("invalid protocol option name: %s\n", option);
+		goto fail;
+	}
+	value = fields[ECM_SFE_L2_DEFUNCT_BY_5TUPLE_OPTION_PROTOCOL];
+	if (!sscanf(value, "%d", &protocol)) {
+		pr_err("Unable to read protocol value %s\n", value);
+		goto fail;
+	}
+
+	/*
+	 * Call 5-tuple defunct functions.
+	 */
+	if (ip_ver == 4) {
+		pr_debug("sip: %pI4 sport: %d dip: %pI4 dport: %d protocol: %d\n", &sip_addr_v4, sport, &dip_addr_v4, dport, protocol);
+		defunct_result = ecm_sfe_common_defunct_ipv4_connection(sip_addr_v4, htons(sport), dip_addr_v4, htons(dport), protocol);
+	} else {
+		pr_debug("sip: %pI6 sport: %d dip: %pI6 dport: %d protocol: %d\n", &sip_addr_v6, sport, &dip_addr_v6, dport, protocol);
+		defunct_result = ecm_sfe_common_defunct_ipv6_connection(&sip_addr_v6, htons(sport), &dip_addr_v6, htons(dport), protocol);
+	}
+
+	if (!defunct_result) {
+		pr_warn("No connection found with this 5-tuple\n");
+	}
+
+	ret = count;
+fail:
+	kfree(cmd_buf);
+
+	return ret;
+}
+
+/*
+ * File operations for defunct by 5-tuple operations.
+ */
+static struct file_operations ecm_sfe_l2_defunct_by_5tuple_fops = {
+	.owner = THIS_MODULE,
+	.write = ecm_sfe_l2_defunct_by_5tuple_write,
+};
+
+/*
+ * ecm_sfe_l2_defunct_by_port_write()
+ *	Writes the defunct by port command to the debugfs node.
+ */
+static ssize_t ecm_sfe_l2_defunct_by_port_write(struct file *f, const char *user_buf,
+					  size_t count, loff_t *offset)
+{
+	char *cmd_buf;
+	char *fields;
+	char *option, *value;
+	int port;
+	int direction;
+
+	/*
+	 * Command is formed as:
+	 *
+	 * echo “sport=443” > /sys/kernel/debug/ecm_sfe_l2/defunct_by_port
+	 * echo “dport=443” > /sys/kernel/debug/ecm_sfe_l2/defunct_by_port
+	 */
+	cmd_buf = kzalloc(count + 1, GFP_ATOMIC);
+	if (!cmd_buf) {
+		pr_warn("unable to allocate memory for cmd buffer\n");
+		return -ENOMEM;
+	}
+
+	count = simple_write_to_buffer(cmd_buf, count, offset, user_buf, count);
+
+	/*
+	 * Split the buffer into its fields
+	 */
+	fields = cmd_buf;
+	option = strsep(&fields, "=");
+	if (!strcmp(option, "sport")) {
+		direction = 0;
+	} else if (!strcmp(option, "dport")) {
+		direction = 1;
+	} else {
+		pr_err("invalid option name: %s\n", option);
+		kfree(cmd_buf);
+		return -EINVAL;
+	}
+
+	value = fields;
+	if (!sscanf(value, "%d", &port)) {
+		pr_err("Unable to read port value %s\n", value);
+		kfree(cmd_buf);
+		return -EINVAL;
+	}
+	pr_debug("option: %s value: %d\n", option, port);
+
+	kfree(cmd_buf);
+
+	/*
+	 * Call port based defunct function.
+	 */
+	ecm_sfe_common_defunct_by_port(port, direction, wan_name);
+
+	return count;
+}
+
+/*
+ * File operations for defunct by port operations.
+ */
+static struct file_operations ecm_sfe_l2_defunct_by_port_fops = {
+	.owner = THIS_MODULE,
+	.write = ecm_sfe_l2_defunct_by_port_write,
+};
+
+/*
+ * ecm_sfe_l2_defunct_by_protocol_write()
+ *	Writes the defunct by protocol command to the debugfs node.
+ */
+static ssize_t ecm_sfe_l2_defunct_by_protocol_write(struct file *f, const char *user_buf,
+					  size_t count, loff_t *offset)
+{
+	char *cmd_buf;
+	char *fields;
+	char *option, *value;
+	int protocol;
+
+	/*
+	 * Command is formed as:
+	 *
+	 * echo “protocol=6” > /sys/kernel/debug/ecm_sfe_l2/defunct_by_protocol
+	 */
+	cmd_buf = kzalloc(count + 1, GFP_ATOMIC);
+	if (!cmd_buf) {
+		pr_warn("unable to allocate memory for cmd buffer\n");
+		return -ENOMEM;
+	}
+
+	count = simple_write_to_buffer(cmd_buf, count, offset, user_buf, count);
+
+	/*
+	 * Split the buffer into its fields
+	 */
+	fields = cmd_buf;
+	option = strsep(&fields, "=");
+	if (strcmp(option, "protocol")) {
+		pr_err("invalid option name: %s\n", option);
+		kfree(cmd_buf);
+		return -EINVAL;
+	}
+
+	value = fields;
+	if (!sscanf(value, "%d", &protocol)) {
+		pr_err("Unable to read protocol value %s\n", value);
+		kfree(cmd_buf);
+		return -EINVAL;
+	}
+	pr_debug("option: %s value: %d\n", option, protocol);
+
+	kfree(cmd_buf);
+
+	/*
+	 * Defunct the connections which has this protocol number.
+	 */
+	ecm_sfe_common_defunct_by_protocol(protocol);
+
+	return count;
+}
+
+/*
+ * File operations for defunct by protocol operations.
+ */
+static struct file_operations ecm_sfe_l2_defunct_by_protocol_fops = {
+	.owner = THIS_MODULE,
+	.write = ecm_sfe_l2_defunct_by_protocol_write,
+};
+
+/*
+ * ecm_sfe_l2_wan_name_read()
+ *	Reads the WAN interface name from the debugfs node wan_name
+ */
+static ssize_t ecm_sfe_l2_wan_name_read(struct file *f, char *buffer,
+					 size_t len, loff_t *offset)
+{
+	return simple_read_from_buffer(buffer, len, offset, wan_name, wan_name_len);
+}
+
+/*
+ * ecm_sfe_l2_wan_name_write()
+ *	Writes the WAN interface name to the debugfs node wan_name
+ */
+static ssize_t ecm_sfe_l2_wan_name_write(struct file *f, const char *buffer,
+					  size_t len, loff_t *offset)
+{
+	ssize_t ret;
+
+	if (len > IFNAMSIZ) {
+		pr_err("WAN interface name is too long\n");
+		return -EINVAL;
+	}
+
+	ret = simple_write_to_buffer(wan_name, IFNAMSIZ, offset, buffer, len);
+	if (ret < 0) {
+		pr_err("WAN interface name cannot be written\n");
+		return ret;
+	}
+
+	wan_name[ret - 1] = '\0';
+	wan_name_len = ret;
+
+	return ret;
+}
+
+/*
+ * File operations for wan interface name.
+ */
+static struct file_operations ecm_sfe_l2_wan_name_fops = {
+	.owner = THIS_MODULE,
+	.write = ecm_sfe_l2_wan_name_write,
+	.read = ecm_sfe_l2_wan_name_read,
+};
+
+struct ecm_sfe_common_callbacks sfe_cbs = {
+	.l2_accel_check = ecm_sfe_l2_accel_check_callback,	/**< Callback to decide if L2 acceleration is wanted for the flow. */
+};
+
+/*
+ * ecm_sfe_l2_init()
+ */
+static int __init ecm_sfe_l2_init(void)
+{
+	pr_debug("ECM SFE L2 module INIT\n");
+
+	/*
+	 * Create entries in DebugFS for control functions
+	 */
+	ecm_sfe_l2_dentry = debugfs_create_dir("ecm_sfe_l2", NULL);
+	if (!ecm_sfe_l2_dentry) {
+		pr_info("Failed to create SFE L2 directory entry\n");
+		return -1;
+	}
+
+	if (!debugfs_create_file("wan_name", S_IWUSR, ecm_sfe_l2_dentry,
+					NULL, &ecm_sfe_l2_wan_name_fops)) {
+		pr_debug("Failed to create ecm wan interface file in debugfs\n");
+		debugfs_remove_recursive(ecm_sfe_l2_dentry);
+		return -1;
+	}
+
+	if (!debugfs_create_file("policy_rules", S_IWUSR, ecm_sfe_l2_dentry,
+					NULL, &ecm_sfe_l2_policy_rule_fops)) {
+		pr_debug("Failed to create ecm SFE L2 policy rules file in debugfs\n");
+		debugfs_remove_recursive(ecm_sfe_l2_dentry);
+		return -1;
+	}
+
+	if (!debugfs_create_file("defunct_by_protocol", S_IWUSR, ecm_sfe_l2_dentry,
+					NULL, &ecm_sfe_l2_defunct_by_protocol_fops)) {
+		pr_debug("Failed to create ecm defunct by protocol file in debugfs\n");
+		debugfs_remove_recursive(ecm_sfe_l2_dentry);
+		return -1;
+	}
+
+	if (!debugfs_create_file("defunct_by_5tuple", S_IWUSR, ecm_sfe_l2_dentry,
+					NULL, &ecm_sfe_l2_defunct_by_5tuple_fops)) {
+		pr_debug("Failed to create ecm defunct by 5tuple file in debugfs\n");
+		debugfs_remove_recursive(ecm_sfe_l2_dentry);
+		return -1;
+	}
+
+	if (!debugfs_create_file("defunct_by_port", S_IWUSR, ecm_sfe_l2_dentry,
+					NULL, &ecm_sfe_l2_defunct_by_port_fops)) {
+		pr_debug("Failed to create ecm defunct by port file in debugfs\n");
+		debugfs_remove_recursive(ecm_sfe_l2_dentry);
+		return -1;
+	}
+
+	if (ecm_sfe_common_callbacks_register(&sfe_cbs)) {
+		pr_debug("Failed to register callbacks\n");
+		debugfs_remove_recursive(ecm_sfe_l2_dentry);
+		return -1;
+	}
+	return 0;
+}
+
+/*
+ * ecm_sfe_l2_exit()
+ */
+static void __exit ecm_sfe_l2_exit(void)
+{
+	pr_debug("ECM SFE L2 check module EXIT\n");
+
+	ecm_sfe_common_callbacks_unregister();
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	debugfs_remove_recursive(ecm_sfe_l2_dentry);
+}
+
+module_init(ecm_sfe_l2_init)
+module_exit(ecm_sfe_l2_exit)
+
+MODULE_DESCRIPTION("ECM SFE L2 Module");
+#ifdef MODULE_LICENSE
+MODULE_LICENSE("Dual BSD/GPL");
+#endif
diff --git a/qca-nss-ecm/exports/ecm_ae_classifier_public.h b/qca-nss-ecm/exports/ecm_ae_classifier_public.h
new file mode 100644
index 0000000..0372c52
--- /dev/null
+++ b/qca-nss-ecm/exports/ecm_ae_classifier_public.h
@@ -0,0 +1,70 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __ECM_AE_CLASSIFIER_PUBLIC_H__
+#define __ECM_AE_CLASSIFIER_PUBLIC_H__
+
+#define ECM_AE_CLASSIFIER_FLOW_ROUTED		(1 << 0)
+#define ECM_AE_CLASSIFIER_FLOW_MULTICAST	(1 << 1)
+
+/*
+ * ECM acceleration engine types.
+ *	External AE classifier returns these types to ECM per flow.
+ */
+typedef enum ecm_ae_classifier_result {
+	ECM_AE_CLASSIFIER_RESULT_NSS,		/* Accelerate the flow in NSS */
+	ECM_AE_CLASSIFIER_RESULT_SFE,		/* Accelerate the flow in SFE */
+	ECM_AE_CLASSIFIER_RESULT_NONE,		/* Do not accelerate the flow */
+	ECM_AE_CLASSIFIER_RESULT_NOT_YET,	/* Acceleration engine hasn't been decided yet */
+} ecm_ae_classifier_result_t;
+
+/*
+ * Data structure which is filled and passed to external module
+ * for the acceleration engine decision.
+ */
+struct ecm_ae_classifier_info {
+	union {
+		__be32 v4_addr;			/* IPv4 address in host order */
+		struct in6_addr v6_addr;	/* IPv6 address in host order */
+	} src;
+	union {
+		__be32 v4_addr;			/* IPv4 address in host order */
+		struct in6_addr v6_addr;	/* IPv6 address in host order */
+	} dest;
+	uint16_t dst_port;		/* Destination port in host order*/
+	uint16_t src_port;		/* Source port port in host order*/
+	uint8_t protocol;		/* Next protocol header number */
+	uint8_t ip_ver;			/* IP version 4 or 6 */
+	uint16_t flag;			/* Flow type flag */
+};
+
+typedef ecm_ae_classifier_result_t (*ecm_ae_classifier_get_t)(struct ecm_ae_classifier_info *info);
+
+/*
+ * ecm_ae_classifier_ops
+ */
+struct ecm_ae_classifier_ops {
+	ecm_ae_classifier_get_t ae_get;
+};
+
+bool ecm_ae_classifier_decelerate_v4_connection(__be32 src_ip, int src_port,
+						__be32 dest_ip, int dest_port, int protocol);
+bool ecm_ae_classifier_decelerate_v6_connection(struct in6_addr src_ip, int src_port,
+						struct in6_addr dest_ip, int dest_port, int protocol);
+
+void ecm_ae_classifier_ops_register(struct ecm_ae_classifier_ops *ops);
+void ecm_ae_classifier_ops_unregister(void);
+#endif /* __ECM_AE_CLASSIFIER_PUBLIC_H__ */
diff --git a/qca-nss-ecm/exports/ecm_classifier_emesh_public.h b/qca-nss-ecm/exports/ecm_classifier_emesh_public.h
new file mode 100644
index 0000000..c39b5e1
--- /dev/null
+++ b/qca-nss-ecm/exports/ecm_classifier_emesh_public.h
@@ -0,0 +1,34 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __ECM_CLASSIFIER_EMESH_PUBLIC_H__
+#define __ECM_CLASSIFIER_EMESH_PUBLIC_H__
+
+/*
+ * Mesh latency config update callback function to which MSCS client will register
+ */
+typedef int (*ecm_classifier_emesh_callback_t)(uint8_t dest_mac[],
+		uint32_t service_interval_dl, uint32_t burst_size_dl,
+		uint32_t service_interval_ul, uint32_t burst_size_ul,
+		uint16_t priority, uint8_t add_or_sub);
+
+struct ecm_classifier_emesh_callbacks {
+	ecm_classifier_emesh_callback_t update_peer_mesh_latency_params;
+};
+
+int ecm_classifier_emesh_latency_config_callback_register(struct ecm_classifier_emesh_callbacks *mesh_cb);
+void ecm_classifier_emesh_latency_config_callback_unregister(void);
+#endif /* __ECM_CLASSIFIER_EMESH_PUBLIC_H__ */
diff --git a/qca-nss-ecm/exports/ecm_classifier_mscs_public.h b/qca-nss-ecm/exports/ecm_classifier_mscs_public.h
new file mode 100644
index 0000000..e2c145f
--- /dev/null
+++ b/qca-nss-ecm/exports/ecm_classifier_mscs_public.h
@@ -0,0 +1,43 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020-2021, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __ECM_CLASSIFIER_MSCS_PUBLIC_H__
+#define __ECM_CLASSIFIER_MSCS_PUBLIC_H__
+
+#define ECM_CLASSIFIER_MSCS_INVALID_QOS_TAG 0xF
+
+/*
+ * MSCS Priority update result vased on WiFi MSCS peer lookup
+ */
+enum ecm_classifier_mscs_results {
+	ECM_CLASSIFIER_MSCS_RESULT_UPDATE_PRIORITY,		/* MSCS priority update allowed */
+	ECM_CLASSIFIER_MSCS_RESULT_UPDATE_INVALID_TAG,
+	ECM_CLASSIFIER_MSCS_RESULT_DENY_PRIORITY,		/* MSCS priority not allowed for flow and return direction */
+};
+typedef enum ecm_classifier_mscs_results ecm_classifier_mscs_result_t;
+
+/*
+ * Callback function to which MSCS client will register
+ */
+typedef int (*ecm_classifier_mscs_process_callback_t)(uint8_t src_mac[], uint8_t dst_mac[], struct sk_buff* skb);
+
+struct ecm_classifier_mscs_callbacks {
+	ecm_classifier_mscs_process_callback_t get_peer_priority;
+};
+
+int ecm_classifier_mscs_callback_register(struct ecm_classifier_mscs_callbacks *mscs_cb);
+void ecm_classifier_mscs_callback_unregister(void);
+#endif /* __ECM_CLASSIFIER_MSCS_PUBLIC_H__ */
diff --git a/qca-nss-ecm/exports/ecm_interface_ipsec.h b/qca-nss-ecm/exports/ecm_interface_ipsec.h
new file mode 100644
index 0000000..936cc31
--- /dev/null
+++ b/qca-nss-ecm/exports/ecm_interface_ipsec.h
@@ -0,0 +1,26 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018-2019 The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#ifndef __ECM_INTERFACE_IPSEC_H__
+#define __ECM_INTERFACE_IPSEC_H__
+
+struct ecm_interface_ipsec_callback{
+   struct net_device *(*tunnel_get_and_hold)(struct net_device *dev, struct sk_buff *skb, int *if_type);
+};
+
+void ecm_interface_ipsec_register_callbacks(struct ecm_interface_ipsec_callback *cb);
+void ecm_interface_ipsec_unregister_callbacks(void);
+
+#endif
diff --git a/qca-nss-ecm/exports/ecm_interface_ovpn.h b/qca-nss-ecm/exports/ecm_interface_ovpn.h
new file mode 100644
index 0000000..b8784dd
--- /dev/null
+++ b/qca-nss-ecm/exports/ecm_interface_ovpn.h
@@ -0,0 +1,34 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __ECM_INTERFACE_OVPN_H__
+#define __ECM_INTERFACE_OVPN_H__
+
+typedef void (*ecm_interface_ovpn_update_route_method_t)(struct net_device *dev, uint32_t *from_addr, uint32_t *to_addr, int version);
+typedef int32_t (*ecm_interface_ovpn_get_ifnum_method_t)(struct net_device *dev, struct sk_buff *skb, struct net_device **tun_dev);
+
+/*
+ * ecm_interface_ovpn
+ *	OVPN interface for supporting acceleration.
+ */
+struct ecm_interface_ovpn {
+	ecm_interface_ovpn_update_route_method_t ovpn_update_route;	/* Update OVPN route status. */
+	ecm_interface_ovpn_get_ifnum_method_t ovpn_get_ifnum;		/* Get nss interface number for OVPN tunnel traffic. */
+};
+
+int ecm_interface_ovpn_register(struct ecm_interface_ovpn *ovpn);
+void ecm_interface_ovpn_unregister(void);
+#endif /* __ECM_INTERFACE_OVPN_H__ */
diff --git a/qca-nss-ecm/exports/ecm_notifier.h b/qca-nss-ecm/exports/ecm_notifier.h
new file mode 100644
index 0000000..fd31a76
--- /dev/null
+++ b/qca-nss-ecm/exports/ecm_notifier.h
@@ -0,0 +1,76 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __ECM_NOTIFIER_H__
+#define __ECM_NOTIFIER_H__
+
+/*
+ * ecm_connection_tuple
+ * 	ECM connection tuple.
+ */
+struct ecm_notifier_connection_tuple {
+		union {
+			struct in_addr in;	/* IPv4 address in host order */
+			struct in6_addr in6;	/* IPv6 address in host order */
+		} src;
+		union {
+			struct in_addr in;	/* IPv4 address in host order */
+			struct in6_addr in6;	/* IPv6 address in host order */
+		} dest;
+		uint16_t dst_port;		/* Destination port in host order*/
+		uint16_t src_port;		/* Source port port in host order*/
+		uint8_t protocol;		/* Next protocol header number */
+		uint8_t ip_ver;			/* IP version 4 or 6 */
+};
+
+/*
+ * ecm_connection_state
+ * 	State of the connection in ECM.
+ */
+enum ecm_notifier_connection_state {
+	ECM_NOTIFIER_CONNECTION_STATE_ACCEL,		/* Connection rule is pushed to NSS */
+	ECM_NOTIFIER_CONNECTION_STATE_ACCEL_PENDING,	/* Connection is in the process of being accelerated to NSS */
+	ECM_NOTIFIER_CONNECTION_STATE_DECEL,		/* Connection rule is not pushed to NSS */
+	ECM_NOTIFIER_CONNECTION_STATE_DECEL_PENDING,	/* Connection is in the process of being decelerated to NSS */
+	ECM_NOTIFIER_CONNECTION_STATE_FAILED,		/* Connection is failed to accelerated */
+	ECM_NOTIFIER_CONNECTION_STATE_INVALID,		/* Connection is not present in ECM DB */
+	ECM_NOTIFIER_CONNECTION_STATE_MAX
+};
+
+/*
+ * ecm_notifier_connection_data
+ * 	Event data for a connection notification.
+ */
+struct ecm_notifier_connection_data {
+	struct net_device *to_dev;			/* First device in ECM 'to' iface hierarchy */
+	struct net_device *from_dev;			/* First device in ECM 'from' iface hierarchy */
+	struct ecm_notifier_connection_tuple tuple;	/* Connection tuple information */
+};
+
+/*
+ * ecm_notifier_action
+ * 	Notifier action for all ECM events.
+ */
+enum ecm_notifier_action {
+	ECM_NOTIFIER_ACTION_CONNECTION_ADDED,
+	ECM_NOTIFIER_ACTION_CONNECTION_REMOVED,
+	ECM_NOTIFIER_ACTION_MAX
+};
+
+extern int ecm_notifier_register_connection_notify(struct notifier_block *nb);
+extern int ecm_notifier_unregister_connection_notify(struct notifier_block *nb);
+extern enum ecm_notifier_connection_state ecm_notifier_connection_state_get(struct ecm_notifier_connection_tuple *conn);
+#endif
diff --git a/qca-nss-ecm/exports/ecm_sfe_common_public.h b/qca-nss-ecm/exports/ecm_sfe_common_public.h
new file mode 100644
index 0000000..41f6b6e
--- /dev/null
+++ b/qca-nss-ecm/exports/ecm_sfe_common_public.h
@@ -0,0 +1,136 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file ecm_fe_common_public.h
+ *	ECM SFE frontend public APIs and data structures.
+ */
+
+#ifndef __ECM_SFE_COMMON_PUBLIC_H__
+#define __ECM_SFE_COMMON_PUBLIC_H__
+
+/**
+ * @addtogroup ecm_sfe_common_subsystem
+ * @{
+ */
+
+#define ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED (1 << 0)	/**< L2 acceleration is allowed on the flow interface. */
+#define ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED (1 << 1)	/**< L2 acceleration is allowed on the return interface. */
+
+/**
+ * SFE common 5-tuple for external use.
+ */
+struct ecm_sfe_common_tuple {
+	uint32_t src_addr[4];	/**< Source IP in host order. */
+	uint32_t dest_addr[4];	/**< Destination IP in host order. */
+
+	uint16_t src_port;	/**< Source port port in host order. */
+	uint16_t dest_port;	/**< Destination port in host order. */
+	uint32_t src_ifindex;	/**< Source L2 interface index */
+	uint32_t dest_ifindex;	/**< Destination L2 interface index */
+	uint8_t protocol;	/**< Next protocol header number. */
+	uint8_t ip_ver;		/**< IP version 4 or 6. */
+};
+
+/**
+ * Callback to which SFE clients will register and return bitmap of values that indicate L2 acceleration for each direction.
+ */
+typedef uint32_t (*ecm_sfe_common_l2_accel_check_callback_t)(struct ecm_sfe_common_tuple *tuple);
+
+/**
+ * Data structure for SFE common callbacks.
+ */
+struct ecm_sfe_common_callbacks {
+	ecm_sfe_common_l2_accel_check_callback_t l2_accel_check;	/**< Callback to decide if L2 acceleration is wanted for the flow. */
+};
+
+/**
+ * Defuncts an IPv4 5-tuple connection.
+ *
+ * @param	src_ip		The source IP address.
+ * @param	src_port	The source port.
+ * @param	dest_ip		The destination IP address.
+ * @param	dest_port	The destination port.
+ * @param	protocol	The protocol.
+ *
+ * @return
+ * True if defuncted; false if not.
+ */
+bool ecm_sfe_common_defunct_ipv4_connection(__be32 src_ip, int src_port,
+						__be32 dest_ip, int dest_port, int protocol);
+
+/**
+ * Defuncts an IPv6 5-tuple connection.
+ *
+ * @param	src_ip		The source IP address.
+ * @param	src_port	The source port.
+ * @param	dest_ip		The destination IP address.
+ * @param	dest_port	The destination port.
+ * @param	protocol	The protocol.
+ *
+ * @return
+ * True if defuncted; false if not.
+ */
+bool ecm_sfe_common_defunct_ipv6_connection(struct in6_addr *src_ip, int src_port,
+						struct in6_addr *dest_ip, int dest_port, int protocol);
+
+/**
+ * Defuncts all the connections with this protocol type.
+ *
+ * @param protocol Protocol type.
+ *
+ * @return
+ * None.
+ */
+void ecm_sfe_common_defunct_by_protocol(int protocol);
+
+/**
+ * Defuncts all the connections with this port number in the correct direction.
+ *
+ * @param	port		The port number.
+ * @param	direction 	The direction of the port (source (1) or destination (2))
+ * @param	wan_name	The WAN port interface name.
+ *
+ * @return
+ * None.
+ */
+void ecm_sfe_common_defunct_by_port(int port, int direction, char *wan_name);
+
+/**
+ * Registers a client for SFE common callbacks.
+ *
+ * @param sfe_cb SFE common callback pointer.
+ *
+ * @return
+ * 0 if success, error value if fails.
+ */
+int ecm_sfe_common_callbacks_register(struct ecm_sfe_common_callbacks *sfe_cb);
+
+/**
+ * Unregisters a client from SFE common callbacks.
+ *
+ * @return
+ * None.
+ */
+void ecm_sfe_common_callbacks_unregister(void);
+
+/**
+ * @}
+ */
+
+#endif /* __ECM_SFE_COMMON_PUBLIC_H__ */
diff --git a/qca-nss-ecm/frontends/cmn/ecm_ae_classifier.c b/qca-nss-ecm/frontends/cmn/ecm_ae_classifier.c
new file mode 100644
index 0000000..7be9e9b
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_ae_classifier.c
@@ -0,0 +1,142 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021 The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/in6.h>
+#include <linux/inet.h>
+#include <linux/etherdevice.h>
+#include <linux/ip.h>
+#include <linux/ipv6.h>
+#include <linux/tcp.h>
+#include <linux/udp.h>
+#include <asm/cmpxchg.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_AE_CLASSIFIER_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_interface.h"
+#include "ecm_ipv4.h"
+#include "ecm_ipv6.h"
+
+DEFINE_SPINLOCK(ecm_ae_classifier_lock);
+
+/*
+ * ecm_ae_classifier_dummy_get()
+ *	Dummy acceleration engine get function.
+ */
+ecm_ae_classifier_result_t ecm_ae_classifier_dummy_get(struct ecm_ae_classifier_info *info)
+{
+	DEBUG_TRACE("%px: Dummy acceleration engine get is called\n", info);
+
+	return ECM_AE_CLASSIFIER_RESULT_NOT_YET;
+}
+
+/*
+ * Acceleration engine operations object
+ */
+struct ecm_ae_classifier_ops ae_ops = {
+	.ae_get = ecm_ae_classifier_dummy_get
+};
+
+/*
+ * ecm_ae_classifier_select_info_fill()
+ *	Fills the AE selction info object.
+ */
+void ecm_ae_classifier_select_info_fill(ip_addr_t src_ip, ip_addr_t dest_ip,
+					int sport, int dport, int protocol, int ip_version,
+					bool is_routed, bool is_multicast,
+					struct ecm_ae_classifier_info *info)
+{
+	if (ip_version == 4) {
+		ECM_IP_ADDR_TO_NIN4_ADDR(info->src.v4_addr, src_ip);
+		ECM_IP_ADDR_TO_NIN4_ADDR(info->dest.v4_addr, dest_ip);
+	} else {
+		ECM_IP_ADDR_TO_NIN6_ADDR(info->src.v6_addr, src_ip);
+		ECM_IP_ADDR_TO_NIN6_ADDR(info->dest.v6_addr, dest_ip);
+	}
+
+	info->src_port = sport;
+	info->dst_port = dport;
+	info->protocol = protocol;
+	info->flag = 0;
+
+	if (is_routed) {
+		info->flag |= ECM_AE_CLASSIFIER_FLOW_ROUTED;
+	}
+
+	if (is_multicast) {
+		info->flag |= ECM_AE_CLASSIFIER_FLOW_MULTICAST;
+	}
+}
+
+/*
+ * ecm_ae_classifier_decelerate_v4_connection()
+ *	Decelerates an IPv4 connection
+ */
+bool ecm_ae_classifier_decelerate_v4_connection(__be32 src_ip, int src_port,
+						__be32 dest_ip, int dest_port, int protocol)
+{
+	return ecm_db_connection_decel_v4(src_ip, src_port, dest_ip, dest_port, protocol);
+}
+EXPORT_SYMBOL(ecm_ae_classifier_decelerate_v4_connection);
+
+/*
+ * ecm_ae_classifier_decelerate_v6_connection()
+ *	Decelerates an IPv6 connection
+ */
+bool ecm_ae_classifier_decelerate_v6_connection(struct in6_addr src_ip, int src_port,
+						struct in6_addr dest_ip, int dest_port, int protocol)
+{
+	return ecm_db_connection_decel_v6(&src_ip, src_port, &dest_ip, dest_port, protocol);
+}
+EXPORT_SYMBOL(ecm_ae_classifier_decelerate_v6_connection);
+
+/*
+ * ecm_ae_classifier_ops_register
+ */
+void ecm_ae_classifier_ops_register(struct ecm_ae_classifier_ops *ops)
+{
+	xchg(&ae_ops.ae_get, ops->ae_get);
+}
+EXPORT_SYMBOL(ecm_ae_classifier_ops_register);
+
+/*
+ * ecm_ae_classifier_ops_unregister
+ */
+void ecm_ae_classifier_ops_unregister(void)
+{
+	xchg(&ae_ops.ae_get, ecm_ae_classifier_dummy_get);
+	synchronize_net();
+}
+EXPORT_SYMBOL(ecm_ae_classifier_ops_unregister);
diff --git a/qca-nss-ecm/frontends/cmn/ecm_ae_classifier.h b/qca-nss-ecm/frontends/cmn/ecm_ae_classifier.h
new file mode 100644
index 0000000..01c5022
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_ae_classifier.h
@@ -0,0 +1,22 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021 The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern struct ecm_ae_classifier_ops ae_ops;	/* Acceleration engine operations object */
+
+extern void ecm_ae_classifier_select_info_fill(ip_addr_t src_ip, ip_addr_t dest_ip,
+					int sport, int dport, int protocol, int ip_version,
+					bool is_routed, bool is_multicast,
+					struct ecm_ae_classifier_info *info);
diff --git a/qca-nss-ecm/frontends/cmn/ecm_bond_notifier.c b/qca-nss-ecm/frontends/cmn/ecm_bond_notifier.c
new file mode 100644
index 0000000..ca7fb45
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_bond_notifier.c
@@ -0,0 +1,283 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2017, 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * ecm_bond_notifier.c
+ * 	Bonding notifier functionality.
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/debugfs.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/bonding.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_BOND_NOTIFIER_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+
+/*
+ * Locking of the classifier - concurrency control
+ */
+static DEFINE_SPINLOCK(ecm_bond_notifier_lock);             /* Protect against SMP access between netfilter, events and private threaded function. */
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_bond_notifier_dentry;
+
+/*
+ * General operational control
+ */
+static int ecm_bond_notifier_stopped = 0;                   /* When non-zero further traffic will not be processed */
+
+/*
+ * ecm_bond_notifier_bond_cb
+ *	Bond driver notifier
+ */
+static struct bond_cb ecm_bond_notifier_bond_cb;
+
+/*
+ * ecm_bond_notifier_bond_link_down()
+ *	Callback when a link goes down on a LAG slave
+ */
+static void ecm_bond_notifier_bond_link_down(struct net_device *slave_dev)
+{
+	struct net_device *master;
+
+	/*
+	 * If operations have stopped then do not process event
+	 */
+	spin_lock_bh(&ecm_bond_notifier_lock);
+	if (unlikely(ecm_bond_notifier_stopped)) {
+		spin_unlock_bh(&ecm_bond_notifier_lock);
+		DEBUG_WARN("Ignoring bond link down event - stopped\n");
+		return;
+	}
+	spin_unlock_bh(&ecm_bond_notifier_lock);
+
+	/*
+	 * A net device that is a LAG slave has lost link.
+	 * Due to the heiarchical nature of network topologies, this can
+	 * change the packet transmit path for any connection that is using
+	 * a device that it sitting "higher" in the heirarchy. Regenerate all
+	 * connections using the LAG master.
+	 */
+
+	master = ecm_interface_get_and_hold_dev_master(slave_dev);
+	if (!master) {
+		DEBUG_WARN("No master dev\n");
+		return;
+	}
+	ecm_interface_dev_defunct_connections(master);
+	dev_put(master);
+}
+
+/*
+ * ecm_bond_notifier_bond_link_up()
+ *	Callback when a device is enslaved by a LAG master device
+ */
+static void ecm_bond_notifier_bond_link_up(struct net_device *slave_dev)
+{
+	struct net_device *master;
+
+	/*
+	 * If operations have stopped then do not process event
+	 */
+	spin_lock_bh(&ecm_bond_notifier_lock);
+	if (unlikely(ecm_bond_notifier_stopped)) {
+		spin_unlock_bh(&ecm_bond_notifier_lock);
+		DEBUG_WARN("Ignoring bond enslave event - stopped\n");
+		return;
+	}
+	spin_unlock_bh(&ecm_bond_notifier_lock);
+
+	/*
+	 * Tricky to handle, this one.
+	 * A net device that is a LAG slave has become active.
+	 * Due to the heiarchical nature of network topologies, this can change the packet transmit path
+	 * for any connection that is using a device that it sitting "higher" in the heirarchy.
+	 * Regenerate all connections using the LAG master.
+	 */
+
+	master = ecm_interface_get_and_hold_dev_master(slave_dev);
+	if (!master) {
+		DEBUG_WARN("No master dev\n");
+		return;
+	}
+	ecm_interface_dev_defunct_connections(master);
+	dev_put(master);
+}
+
+/*
+ * ecm_bond_notifier_bond_delete_by_slave()
+ *	Callback when defunct a LAG slave
+ */
+static void ecm_bond_notifier_bond_delete_by_slave(struct net_device *slave_dev)
+{
+	struct net_device *master;
+
+	/*
+	 * If operations have stopped then do not process event
+	 */
+	spin_lock_bh(&ecm_bond_notifier_lock);
+	if (unlikely(ecm_bond_notifier_stopped)) {
+		spin_unlock_bh(&ecm_bond_notifier_lock);
+		DEBUG_WARN("Ignoring bond defunct event - stopped\n");
+		return;
+	}
+	spin_unlock_bh(&ecm_bond_notifier_lock);
+
+	/*
+	 * A net device that is a LAG slave has to
+	 * defunct all the connection.
+	 * Due to the heiarchical nature of network topologies, this can
+	 * change the packet transmit path for any connection that is using
+	 * a device that it sitting "higher" in the heirarchy.
+	 */
+	master = ecm_interface_get_and_hold_dev_master(slave_dev);
+	if (!master) {
+		DEBUG_WARN("Failed to find 'master' for the slave:%s\n", slave_dev->name);
+		return;
+	}
+
+	ecm_interface_dev_defunct_connections(master);
+	dev_put(master);
+}
+
+/*
+ * ecm_bond_notifier_bond_delete_by_mac()
+ *     This is a call back to delete all the rules with the mac address
+ */
+static void ecm_bond_notifier_bond_delete_by_mac(uint8_t *mac)
+{
+	DEBUG_INFO("Bond notifier for node %pM\n", mac);
+
+	ecm_interface_node_connections_defunct(mac, ECM_DB_IP_VERSION_IGNORE);
+}
+
+void ecm_bond_notifier_stop(int num)
+{
+	ecm_bond_notifier_stopped = num;
+}
+EXPORT_SYMBOL(ecm_bond_notifier_stop);
+
+/*
+ * ecm_bond_notifier_init()
+ */
+int ecm_bond_notifier_init(struct dentry *dentry)
+{
+	DEBUG_INFO("ECM Bonding Notifier init\n");
+
+	ecm_bond_notifier_dentry = debugfs_create_dir("ecm_bond_notifier", dentry);
+	if (!ecm_bond_notifier_dentry) {
+		DEBUG_ERROR("Failed to create ecm bond notifier directory in debugfs\n");
+		return -1;
+	}
+
+	if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_bond_notifier_dentry,
+					(u32 *)&ecm_bond_notifier_stopped)) {
+		DEBUG_ERROR("Failed to create ecm bond notifier stopped file in debugfs\n");
+		debugfs_remove_recursive(ecm_bond_notifier_dentry);
+		return -1;
+	}
+
+	/*
+	 * Register Link Aggregation callbacks with the bonding driver
+	 */
+	ecm_bond_notifier_bond_cb.bond_cb_link_up = ecm_bond_notifier_bond_link_up;
+	ecm_bond_notifier_bond_cb.bond_cb_link_down = ecm_bond_notifier_bond_link_down;
+	ecm_bond_notifier_bond_cb.bond_cb_delete_by_slave = ecm_bond_notifier_bond_delete_by_slave;
+	ecm_bond_notifier_bond_cb.bond_cb_delete_by_mac = ecm_bond_notifier_bond_delete_by_mac;
+	bond_register_cb(&ecm_bond_notifier_bond_cb);
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_bond_notifier_init);
+
+/*
+ * ecm_bond_notifier_exit()
+ */
+void ecm_bond_notifier_exit(void)
+{
+	DEBUG_INFO("ECM Bonding Notifier exit\n");
+
+	/*
+	 * Unregister from the bond driver
+	 */
+	bond_unregister_cb();
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_bond_notifier_dentry) {
+		debugfs_remove_recursive(ecm_bond_notifier_dentry);
+	}
+}
+EXPORT_SYMBOL(ecm_bond_notifier_exit);
diff --git a/qca-nss-ecm/frontends/cmn/ecm_bond_notifier.h b/qca-nss-ecm/frontends/cmn/ecm_bond_notifier.h
new file mode 100644
index 0000000..d3df616
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_bond_notifier.h
@@ -0,0 +1,26 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __ECM_BOND_NOTIFIER_H
+#define __ECM_BOND_NOTIFIER_H
+
+extern void ecm_bond_notifier_stop(int num);
+extern int ecm_bond_notifier_init(struct dentry *dentry);
+extern void ecm_bond_notifier_exit(void);
+
+#endif  /* __ECM_BOND_NOTIFIER_H */
diff --git a/qca-nss-ecm/frontends/cmn/ecm_ipv4.c b/qca-nss-ecm/frontends/cmn/ecm_ipv4.c
new file mode 100644
index 0000000..e5ceae4
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_ipv4.c
@@ -0,0 +1,2044 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/ip_tunnels.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <net/addrconf.h>
+#include <net/xfrm.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/ppp_defs.h>
+#include <linux/mroute.h>
+
+#include <net/ip6_tunnel.h>
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+#include <net/vxlan.h>
+#endif
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <linux/netfilter/nf_conntrack_zones_common.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/nf_conntrack_timeout.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_IPV4_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+#include "ecm_classifier_nl.h"
+#endif
+#include "ecm_interface.h"
+#include "ecm_front_end_common.h"
+#include "ecm_front_end_ipv4.h"
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+#include <ovsmgr.h>
+#endif
+#include "ecm_ported_ipv4.h"
+#include "ecm_non_ported_ipv4.h"
+#include "ecm_multicast_ipv4.h"
+
+/*
+ * Locking of the classifier - concurrency control for file global parameters.
+ * NOTE: It is safe to take this lock WHILE HOLDING a feci->lock.  The reverse is NOT SAFE.
+ */
+DEFINE_SPINLOCK(ecm_ipv4_lock);			/* Protect against SMP access between netfilter, events and private threaded function. */
+
+/*
+ * Management thread control
+ */
+bool ecm_ipv4_terminate_pending = false;		/* True when the user has signalled we should quit */
+
+/*
+ * ecm_ipv4_node_establish_and_ref()
+ *	Returns a reference to a node, possibly creating one if necessary.
+ *
+ * The given_node_addr will be used if provided.
+ *
+ * Returns NULL on failure.
+ */
+struct ecm_db_node_instance *ecm_ipv4_node_establish_and_ref(struct ecm_front_end_connection_instance *feci,
+							struct net_device *dev, ip_addr_t addr,
+							struct ecm_db_iface_instance *interface_list[], int32_t interface_list_first,
+							uint8_t *given_node_addr, struct sk_buff *skb)
+{
+	struct ecm_db_node_instance *ni;
+	struct ecm_db_node_instance *nni;
+	struct ecm_db_iface_instance *ii;
+	int i;
+	bool done;
+	uint8_t node_addr[ETH_ALEN];
+#if defined(ECM_INTERFACE_L2TPV2_ENABLE) || defined(ECM_INTERFACE_PPTP_ENABLE)
+	ip_addr_t local_ip, remote_ip;
+#endif
+
+#if defined(ECM_INTERFACE_VXLAN_ENABLE) || defined(ECM_INTERFACE_L2TPV2_ENABLE) || defined(ECM_INTERFACE_PPTP_ENABLE)
+	struct net_device *local_dev;
+#endif
+
+#if defined(ECM_INTERFACE_MAP_T_ENABLE) || defined(ECM_INTERFACE_GRE_TUN_ENABLE) || defined(ECM_XFRM_ENABLE)
+	struct net_device *in;
+#endif
+
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+	struct ip_tunnel *gre4_tunnel;
+	struct ip6_tnl *gre6_tunnel;
+	ip_addr_t local_gre_tun_ip;
+#endif
+
+	DEBUG_INFO("%px: Establish node for " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(addr));
+
+	/*
+	 * The node is the datalink address, typically a MAC address.
+	 * However the node address to use is not always obvious and depends on the interfaces involved.
+	 * For example if the interface is PPPoE then we use the MAC of the PPPoE server as we cannot use normal ARP resolution.
+	 * Not all hosts have a node address, where there is none, a suitable alternative should be located and is typically based on 'addr'
+	 * or some other datalink session information.
+	 * It should be, at a minimum, something that ties the host with the interface.
+	 *
+	 * Iterate from 'inner' to 'outer' interfaces - discover what the node is.
+	 */
+	memset(node_addr, 0, ETH_ALEN);
+	done = false;
+	if (given_node_addr) {
+		memcpy(node_addr, given_node_addr, ETH_ALEN);
+		done = true;
+		DEBUG_TRACE("%px: Using given node address: %pM\n", feci, node_addr);
+	}
+
+	for (i = ECM_DB_IFACE_HEIRARCHY_MAX - 1; (!done) && (i >= interface_list_first); i--) {
+		ecm_db_iface_type_t type;
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+		struct ecm_db_interface_info_pppoe pppoe_info;
+#endif
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+		struct ecm_db_interface_info_pppol2tpv2 pppol2tpv2_info;
+#endif
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+		struct ecm_db_interface_info_pptp pptp_info;
+#endif
+		type = ecm_db_iface_type_get(interface_list[i]);
+		DEBUG_INFO("%px: Lookup node address, interface @ %d is type: %d\n", feci, i, type);
+
+		switch (type) {
+
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * Node address is the address of the remote PPPoE server
+			 */
+			ecm_db_iface_pppoe_session_info_get(interface_list[i], &pppoe_info);
+			memcpy(node_addr, pppoe_info.remote_mac, ETH_ALEN);
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("%px:PPPoE interface unsupported\n", feci);
+			return NULL;
+#endif
+
+		case ECM_DB_IFACE_TYPE_SIT:
+		case ECM_DB_IFACE_TYPE_TUNIPIP6:
+			done = true;
+			break;
+
+		case ECM_DB_IFACE_TYPE_PPPOL2TPV2:
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+			ecm_db_iface_pppol2tpv2_session_info_get(interface_list[i], &pppol2tpv2_info);
+			ECM_HIN4_ADDR_TO_IP_ADDR(local_ip, pppol2tpv2_info.ip.saddr);
+			ECM_HIN4_ADDR_TO_IP_ADDR(remote_ip, pppol2tpv2_info.ip.daddr);
+			DEBUG_TRACE("%px: local=" ECM_IP_ADDR_DOT_FMT " remote=" ECM_IP_ADDR_DOT_FMT " addr=" ECM_IP_ADDR_DOT_FMT "\n", feci,
+			       ECM_IP_ADDR_TO_DOT(local_ip), ECM_IP_ADDR_TO_DOT(remote_ip), ECM_IP_ADDR_TO_DOT(addr));
+
+			local_dev = ecm_interface_dev_find_by_local_addr(local_ip);
+			if (!local_dev) {
+				DEBUG_WARN("%px: Failed to find local netdevice of l2tp tunnel for " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(local_ip));
+				return NULL;
+			}
+
+			DEBUG_TRACE("%px: local_dev found is %s\n", feci, local_dev->name);
+
+			if (local_dev->type == ARPHRD_PPP) {
+#ifndef ECM_INTERFACE_PPPOE_ENABLE
+				DEBUG_TRACE("%px: l2tp over netdevice %s unsupported\n", feci, local_dev->name);
+				dev_put(local_dev);
+				return NULL;
+#else
+				struct ppp_channel *ppp_chan[1];
+				struct pppoe_opt addressing;
+				int px_proto;
+
+				if (ppp_hold_channels(local_dev, ppp_chan, 1) != 1) {
+					DEBUG_WARN("%px: l2tpv2 over netdevice %s unsupported; could not hold ppp channels\n", feci, local_dev->name);
+					dev_put(local_dev);
+					return NULL;
+				}
+
+				px_proto = ppp_channel_get_protocol(ppp_chan[0]);
+				if (px_proto != PX_PROTO_OE) {
+					DEBUG_WARN("%px: l2tpv2 over PPP protocol %d unsupported\n", feci, px_proto);
+					ppp_release_channels(ppp_chan, 1);
+					dev_put(local_dev);
+					return NULL;
+				}
+
+				if (pppoe_channel_addressing_get(ppp_chan[0], &addressing)) {
+					DEBUG_WARN("%px: failed to get PPPoE addressing info\n", feci);
+					ppp_release_channels(ppp_chan, 1);
+					dev_put(local_dev);
+					return NULL;
+				}
+
+				DEBUG_TRACE("%px: Obtained mac address for %s remote address " ECM_IP_ADDR_OCTAL_FMT "\n", feci, addressing.dev->name, ECM_IP_ADDR_TO_OCTAL(addr));
+				memcpy(node_addr, addressing.dev->dev_addr, ETH_ALEN);
+				dev_put(addressing.dev);
+				ppp_release_channels(ppp_chan, 1);
+				dev_put(local_dev);
+				done = true;
+				break;
+#endif
+			}
+
+			if (ECM_IP_ADDR_MATCH(local_ip, addr)) {
+				if (unlikely(!ecm_interface_mac_addr_get_no_route(local_dev, local_ip, node_addr))) {
+					DEBUG_WARN("%px: failed to obtain node address for " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(local_ip));
+					dev_put(local_dev);
+					return NULL;
+				}
+
+			} else {
+				if (unlikely(!ecm_interface_mac_addr_get_no_route(local_dev, remote_ip, node_addr))) {
+					DEBUG_WARN("%px: failed to obtain node address for host " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(remote_ip));
+					dev_put(local_dev);
+					return NULL;
+				}
+			}
+
+			dev_put(local_dev);
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("%px: PPPoL2TPV2 interface unsupported\n", feci);
+			return NULL;
+#endif
+
+		case ECM_DB_IFACE_TYPE_PPTP:
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+			ecm_db_iface_pptp_session_info_get(interface_list[i], &pptp_info);
+			ECM_HIN4_ADDR_TO_IP_ADDR(local_ip, pptp_info.src_ip);
+			ECM_HIN4_ADDR_TO_IP_ADDR(remote_ip, pptp_info.dst_ip);
+			DEBUG_TRACE("%px: local=" ECM_IP_ADDR_DOT_FMT " remote=" ECM_IP_ADDR_DOT_FMT " addr=" ECM_IP_ADDR_DOT_FMT "\n", feci,
+			       ECM_IP_ADDR_TO_DOT(local_ip), ECM_IP_ADDR_TO_DOT(remote_ip), ECM_IP_ADDR_TO_DOT(addr));
+
+			local_dev = ecm_interface_dev_find_by_local_addr(local_ip);
+
+			if (!local_dev) {
+				DEBUG_WARN("%px: Failed to find local netdevice of pptp tunnel for " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(local_ip));
+				return NULL;
+			}
+
+			DEBUG_TRACE("%px: local_dev found is %s\n", feci, local_dev->name);
+
+			if (ECM_IP_ADDR_MATCH(local_ip, addr)) {
+				if (unlikely(!ecm_interface_mac_addr_get_no_route(local_dev, local_ip, node_addr))) {
+					DEBUG_WARN("%px: failed to obtain node address for " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(local_ip));
+					dev_put(local_dev);
+					return NULL;
+				}
+
+			} else {
+				if (unlikely(!ecm_interface_mac_addr_get_no_route(local_dev, remote_ip, node_addr))) {
+					ip_addr_t gw_addr = ECM_IP_ADDR_NULL;
+
+					if (!ecm_interface_find_gateway(remote_ip, gw_addr)) {
+						DEBUG_WARN("%px: failed to obtain Gateway address for host " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(remote_ip));
+						dev_put(local_dev);
+						return NULL;
+					}
+
+					if (ECM_IP_ADDR_MATCH(gw_addr, remote_ip)) {
+						DEBUG_WARN("%px: host ip address match with gw address " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(remote_ip));
+						dev_put(local_dev);
+						return NULL;
+					}
+
+					if (!ecm_interface_mac_addr_get_no_route(local_dev, gw_addr, node_addr)) {
+						DEBUG_WARN("%px: failed to obtain node address for host " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(gw_addr));
+						dev_put(local_dev);
+						return NULL;
+					}
+				}
+			}
+
+			dev_put(local_dev);
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("%px: PPTP interface unsupported\n", feci);
+			return NULL;
+#endif
+
+		case ECM_DB_IFACE_TYPE_MAP_T:
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+			in = dev_get_by_index(&init_net, skb->skb_iif);
+			if (!in) {
+				DEBUG_WARN("%px: failed to obtain node address for host " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(addr));
+				return NULL;
+			}
+			memcpy(node_addr, in->dev_addr, ETH_ALEN);
+			dev_put(in);
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("%px: MAP-T interface unsupported\n", feci);
+			return NULL;
+#endif
+
+		case ECM_DB_IFACE_TYPE_GRE_TUN:
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+			in = dev_get_by_index(&init_net, skb->skb_iif);
+			if (!in) {
+				DEBUG_WARN("%px: failed to obtain node address for host " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(addr));
+				return NULL;
+			}
+
+			switch(in->type) {
+			case ARPHRD_IPGRE:
+				gre4_tunnel = netdev_priv(in);
+				if (!gre4_tunnel) {
+					dev_put(in);
+					DEBUG_WARN("%px: failed to obtain node address for host. GREv4 tunnel not initialized\n", feci);
+					return NULL;
+				}
+				ECM_NIN4_ADDR_TO_IP_ADDR(local_gre_tun_ip, gre4_tunnel->parms.iph.saddr);
+				dev_put(in);
+				in = ecm_interface_dev_find_by_local_addr(local_gre_tun_ip);
+				if (!in) {
+					DEBUG_WARN("%px: failed to obtain node address for host " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(local_gre_tun_ip));
+					return NULL;
+				}
+				break;
+
+			case ARPHRD_IP6GRE:
+				gre6_tunnel = netdev_priv(in);
+				if (!gre6_tunnel) {
+					dev_put(in);
+					DEBUG_WARN("%px: failed to obtain node address for host. GREv6 tunnel not initialized\n", feci);
+					return NULL;
+				}
+				ECM_NIN6_ADDR_TO_IP_ADDR(local_gre_tun_ip, gre6_tunnel->parms.laddr);
+				dev_put(in);
+				in = ecm_interface_dev_find_by_local_addr(local_gre_tun_ip);
+				if (!in) {
+					DEBUG_WARN("%px: failed to obtain node address for host " ECM_IP_ADDR_OCTAL_FMT "\n", feci, ECM_IP_ADDR_TO_OCTAL(local_gre_tun_ip));
+					return NULL;
+				}
+				break;
+
+			default:
+				DEBUG_TRACE("%px: establish node with physical netdev: %s\n", feci, in->name);
+			}
+			memcpy(node_addr, in->dev_addr, ETH_ALEN);
+			dev_put(in);
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("%px: GRE Tunnel interface unsupported\n", feci);
+			return NULL;
+#endif
+
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			/*
+			 * VLAN handled same along with ethernet, lag, bridge etc.
+			 */
+#else
+			DEBUG_TRACE("%px: VLAN interface unsupported\n", feci);
+			return NULL;
+#endif
+
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_XFRM_ENABLE
+			if (dst_xfrm(skb_dst(skb))) {
+				ether_addr_copy(node_addr, dev->dev_addr);
+				done = true;
+				break;
+			}
+
+			if (secpath_exists(skb)) {
+				in = dev_get_by_index(&init_net, skb->skb_iif);
+				if (!in) {
+					DEBUG_WARN("%px: failed to obtain node address for host " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(addr));
+					return NULL;
+				}
+
+				ether_addr_copy(node_addr, in->dev_addr);
+				dev_put(in);
+				done = true;
+				break;
+			}
+#if __has_attribute(__fallthrough__)
+			__attribute__((__fallthrough__));
+#endif
+#endif
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+		case ECM_DB_IFACE_TYPE_LAG:
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#endif
+			if (!ecm_interface_mac_addr_get_no_route(dev, addr, node_addr)) {
+				ip_addr_t gw_addr = ECM_IP_ADDR_NULL;
+				bool on_link = true;
+
+				/*
+				 * Check if we have a gateway address. If yes, first we will try to get the MAC address
+				 * of that gateway. If it fails, we will send ARP request to that address
+				 * to find the node MAC address while processing the subsequent packets.
+				 */
+				if (ecm_interface_find_gateway(addr, gw_addr)) {
+					DEBUG_TRACE("%px: Have a gw address " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(gw_addr));
+					if (ecm_interface_mac_addr_get_no_route(dev, gw_addr, node_addr)) {
+						DEBUG_TRACE("%px: Found the mac address for gateway\n", feci);
+						goto done;
+					}
+					on_link = false;
+				}
+
+				/*
+				 * If dev is a bridge port, we should use the bridge device for the ARP request.
+				 */
+				if (!ecm_front_end_is_bridge_port(dev)) {
+					ecm_interface_send_arp_request(dev, addr, on_link, gw_addr);
+				} else {
+					struct net_device *master;
+					master = ecm_interface_get_and_hold_dev_master(dev);
+					DEBUG_ASSERT(master, "%px: Expected a master\n", feci);
+					ecm_interface_send_arp_request(master, addr, on_link, gw_addr);
+					dev_put(master);
+				}
+
+				DEBUG_WARN("%px: failed to obtain any node address for host " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(addr));
+
+				/*
+				 * Unable to get node address at this time.
+				 */
+				return NULL;
+			}
+done:
+			if (is_multicast_ether_addr(node_addr)) {
+				DEBUG_TRACE("%px: multicast node address for host " ECM_IP_ADDR_DOT_FMT ", node_addr: %pM\n", feci, ECM_IP_ADDR_TO_DOT(addr), node_addr);
+				return NULL;
+			}
+
+			/*
+			 * Because we are iterating from inner to outer interface, this interface is the
+			 * innermost one that has a node address - take this one.
+			 */
+			done = true;
+			break;
+		case ECM_DB_IFACE_TYPE_RAWIP:
+#ifdef ECM_INTERFACE_RAWIP_ENABLE
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("%px: RAWIP interface unsupported\n", feci);
+			return NULL;
+#endif
+		case ECM_DB_IFACE_TYPE_OVPN:
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("%px: OVPN interface unsupported\n", feci);
+			return NULL;
+#endif
+		case ECM_DB_IFACE_TYPE_VXLAN:
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+			local_dev = ecm_interface_dev_find_by_local_addr(addr);
+			if (!local_dev) {
+				DEBUG_WARN("%px: Failed to find local netdevice of VxLAN tunnel for " ECM_IP_ADDR_DOT_FMT "\n",
+						feci, ECM_IP_ADDR_TO_DOT(addr));
+				return NULL;
+			}
+
+			if (!ecm_interface_mac_addr_get_no_route(local_dev, addr, node_addr)) {
+				DEBUG_WARN("%px: Couldn't find mac address for local dev\n", feci);
+				dev_put(local_dev);
+				return NULL;
+			}
+			DEBUG_TRACE("%px: Found the mac address for local dev\n", feci);
+			dev_put(local_dev);
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("%px: VXLAN interface unsupported\n", feci);
+			return NULL;
+#endif
+		default:
+			/*
+			 * Don't know how to handle these.
+			 * Just copy some part of the address for now, but keep iterating the interface list
+			 * in the hope something recognisable will be seen!
+			 * GGG TODO We really need to roll out support for all interface types we can deal with ASAP :-(
+			 */
+			memcpy(node_addr, (uint8_t *)addr, ETH_ALEN);
+		}
+	}
+	if (!done) {
+		DEBUG_WARN("%px: Failed to establish node for " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(addr));
+		return NULL;
+	}
+
+	/*
+	 *  Establish iface
+	 */
+	ii = ecm_interface_establish_and_ref(feci, dev, skb);
+	if (!ii) {
+		DEBUG_WARN("%px: Failed to establish iface\n", feci);
+		return NULL;
+	}
+
+	/*
+	 * Locate the node
+	 */
+	ni = ecm_db_node_find_and_ref(node_addr, ii);
+	if (ni) {
+		DEBUG_TRACE("%px: node established: %px\n", feci, ni);
+		ecm_db_iface_deref(ii);
+		return ni;
+	}
+
+	/*
+	 * No node - create one
+	 */
+	nni = ecm_db_node_alloc();
+	if (!nni) {
+		DEBUG_WARN("%px: Failed to establish node\n", feci);
+		ecm_db_iface_deref(ii);
+		return NULL;
+	}
+
+	/*
+	 * Add node into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_ipv4_lock);
+	ni = ecm_db_node_find_and_ref(node_addr, ii);
+	if (ni) {
+		spin_unlock_bh(&ecm_ipv4_lock);
+		ecm_db_node_deref(nni);
+		ecm_db_iface_deref(ii);
+		return ni;
+	}
+
+	ecm_db_node_add(nni, ii, node_addr, NULL, nni);
+	spin_unlock_bh(&ecm_ipv4_lock);
+
+	/*
+	 * Don't need iface instance now
+	 */
+	ecm_db_iface_deref(ii);
+
+	DEBUG_TRACE("%px: node (%px) established, node address: %pM\n", feci, nni, node_addr);
+	return nni;
+}
+
+/*
+ * ecm_ipv4_host_establish_and_ref()
+ *	Returns a reference to a host, possibly creating one if necessary.
+ *
+ * Returns NULL on failure.
+ */
+struct ecm_db_host_instance *ecm_ipv4_host_establish_and_ref(ip_addr_t addr)
+{
+	struct ecm_db_host_instance *hi;
+	struct ecm_db_host_instance *nhi;
+
+	DEBUG_INFO("Establish host for " ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(addr));
+
+	/*
+	 * Locate the host
+	 */
+	hi = ecm_db_host_find_and_ref(addr);
+	if (hi) {
+		DEBUG_TRACE("%px: host established\n", hi);
+		return hi;
+	}
+
+	/*
+	 * No host - create one
+	 */
+	nhi = ecm_db_host_alloc();
+	if (!nhi) {
+		DEBUG_WARN("Failed to establish host\n");
+		return NULL;
+	}
+
+	/*
+	 * Add host into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_ipv4_lock);
+	hi = ecm_db_host_find_and_ref(addr);
+	if (hi) {
+		spin_unlock_bh(&ecm_ipv4_lock);
+		ecm_db_host_deref(nhi);
+		return hi;
+	}
+
+	ecm_db_host_add(nhi, addr, true, NULL, nhi);
+
+	spin_unlock_bh(&ecm_ipv4_lock);
+
+	DEBUG_TRACE("%px: host established\n", nhi);
+	return nhi;
+}
+
+/*
+ * ecm_ipv4_mapping_establish_and_ref()
+ *	Returns a reference to a mapping, possibly creating one if necessary.
+ *
+ * Returns NULL on failure.
+ */
+struct ecm_db_mapping_instance *ecm_ipv4_mapping_establish_and_ref(ip_addr_t addr, int port)
+{
+	struct ecm_db_mapping_instance *mi;
+	struct ecm_db_mapping_instance *nmi;
+	struct ecm_db_host_instance *hi;
+
+	DEBUG_INFO("Establish mapping for " ECM_IP_ADDR_DOT_FMT ":%d\n", ECM_IP_ADDR_TO_DOT(addr), port);
+
+	/*
+	 * Locate the mapping
+	 */
+	mi = ecm_db_mapping_find_and_ref(addr, port);
+	if (mi) {
+		DEBUG_TRACE("%px: mapping established\n", mi);
+		return mi;
+	}
+
+	/*
+	 * No mapping - establish host existence
+	 */
+	hi = ecm_ipv4_host_establish_and_ref(addr);
+	if (!hi) {
+		DEBUG_WARN("Failed to establish host\n");
+		return NULL;
+	}
+
+	/*
+	 * Create mapping instance
+	 */
+	nmi = ecm_db_mapping_alloc();
+	if (!nmi) {
+		ecm_db_host_deref(hi);
+		DEBUG_WARN("Failed to establish mapping\n");
+		return NULL;
+	}
+
+	/*
+	 * Add mapping into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_ipv4_lock);
+	mi = ecm_db_mapping_find_and_ref(addr, port);
+	if (mi) {
+		spin_unlock_bh(&ecm_ipv4_lock);
+		ecm_db_mapping_deref(nmi);
+		ecm_db_host_deref(hi);
+		return mi;
+	}
+
+	ecm_db_mapping_add(nmi, hi, port, NULL, nmi);
+
+	spin_unlock_bh(&ecm_ipv4_lock);
+
+	/*
+	 * Don't need the host instance now - the mapping maintains a reference to it now.
+	 */
+	ecm_db_host_deref(hi);
+
+	/*
+	 * Return the mapping instance
+	 */
+	DEBUG_INFO("%px: mapping established\n", nmi);
+	return nmi;
+}
+
+/*
+ * ecm_ipv4_connection_regenerate()
+ *	Re-generate a connection.
+ *
+ * Re-generating a connection involves re-evaluating the interface lists in case interface heirarchies have changed.
+ * It also involves the possible triggering of classifier re-evaluation but only if all currently assigned
+ * classifiers permit this operation.
+ */
+void ecm_ipv4_connection_regenerate(struct ecm_db_connection_instance *ci, ecm_tracker_sender_type_t sender,
+							struct net_device *out_dev, struct net_device *out_dev_nat,
+							struct net_device *in_dev, struct net_device *in_dev_nat,
+							__be16 *layer4hdr, struct sk_buff *skb)
+{
+	int i;
+	bool reclassify_allowed;
+	int32_t to_list_first;
+	struct ecm_db_iface_instance *to_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+	int32_t to_nat_list_first;
+	struct ecm_db_iface_instance *to_nat_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+	int32_t from_list_first;
+	struct ecm_db_iface_instance *from_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+	int32_t from_nat_list_first;
+	struct ecm_db_iface_instance *from_nat_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+	ip_addr_t ip_src_addr;
+	ip_addr_t ip_dest_addr;
+	ip_addr_t ip_src_addr_nat;
+	ip_addr_t ip_dest_addr_nat;
+	int protocol;
+	bool is_routed;
+	uint8_t src_node_addr[ETH_ALEN];
+	uint8_t dest_node_addr[ETH_ALEN];
+	uint8_t src_node_addr_nat[ETH_ALEN];
+	uint8_t dest_node_addr_nat[ETH_ALEN];
+	int assignment_count;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_front_end_interface_construct_instance efeici;
+	 ecm_db_direction_t ecm_dir;
+	struct ecm_front_end_ovs_params *from_ovs_params = NULL;
+	struct ecm_front_end_ovs_params *to_ovs_params = NULL;
+	struct ecm_front_end_ovs_params *from_nat_ovs_params = NULL;
+	struct ecm_front_end_ovs_params *to_nat_ovs_params = NULL;
+
+	DEBUG_INFO("%px: re-gen needed\n", ci);
+
+	/*
+	 * We may need to swap the devices around depending on who the sender of the packet that triggered the re-gen is
+	 */
+	if (sender == ECM_TRACKER_SENDER_TYPE_DEST) {
+		struct net_device *tmp_dev;
+
+		/*
+		 * This is a packet sent by the destination of the connection, i.e. it is a packet issued by the 'from' side of the connection.
+		 */
+		DEBUG_TRACE("%px: Re-gen swap devs\n", ci);
+		tmp_dev = out_dev;
+		out_dev = in_dev;
+		in_dev = tmp_dev;
+
+		tmp_dev = out_dev_nat;
+		out_dev_nat = in_dev_nat;
+		in_dev_nat = tmp_dev;
+	}
+
+	/*
+	 * Update the interface lists - these may have changed, e.g. LAG path change etc.
+	 * NOTE: We never have to change the usual mapping->host->node_iface arrangements for each side of the connection (to/from sides)
+	 * This is because if these interfaces change then the connection is dead anyway.
+	 * But a LAG slave might change the heirarchy the connection is using but the LAG master is still sane.
+	 * If any of the new interface heirarchies cannot be created then simply set empty-lists as this will deny
+	 * acceleration and ensure that a bad rule cannot be created.
+	 * IMPORTANT: The 'sender' defines who has sent the packet that triggered this re-generation
+	 */
+	protocol = ecm_db_connection_protocol_get(ci);
+
+	is_routed = ecm_db_connection_is_routed_get(ci);
+	ecm_dir = ecm_db_connection_direction_get(ci);
+
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, ip_src_addr);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM_NAT, ip_src_addr_nat);
+
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, ip_dest_addr);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO_NAT, ip_dest_addr_nat);
+
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_node_addr);
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM_NAT, src_node_addr_nat);
+
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, dest_node_addr);
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO_NAT, dest_node_addr_nat);
+
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+	if (!ecm_front_end_ipv4_interface_construct_set_and_hold(skb, sender, ecm_dir, is_routed,
+							in_dev, out_dev,
+							ip_src_addr, ip_src_addr_nat,
+							ip_dest_addr, ip_dest_addr_nat,
+							&efeici)) {
+
+		DEBUG_WARN("ECM front end ipv4 interface construct set failed for regeneration\n");
+		goto ecm_ipv4_retry_regen;
+	}
+
+	if ((protocol == IPPROTO_TCP) || (protocol == IPPROTO_UDP)) {
+		int src_port, src_port_nat, dest_port, dest_port_nat;
+		struct ecm_front_end_ovs_params ovs_params[ECM_DB_OBJ_DIR_MAX];
+
+		src_port = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+		src_port_nat = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM_NAT);
+		dest_port = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+		dest_port_nat = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT);
+
+		ecm_front_end_fill_ovs_params(ovs_params,
+				      ip_src_addr, ip_src_addr_nat,
+				      ip_dest_addr, ip_dest_addr_nat,
+				      src_port, src_port_nat,
+				      dest_port, dest_port_nat, ecm_dir);
+
+		from_ovs_params = &ovs_params[ECM_DB_OBJ_DIR_FROM];
+		to_ovs_params = &ovs_params[ECM_DB_OBJ_DIR_TO];
+		from_nat_ovs_params = &ovs_params[ECM_DB_OBJ_DIR_FROM_NAT];
+		to_nat_ovs_params = &ovs_params[ECM_DB_OBJ_DIR_TO_NAT];
+	}
+
+	DEBUG_TRACE("%px: Update the 'from' interface heirarchy list\n", ci);
+	from_list_first = ecm_interface_heirarchy_construct(feci, from_list, efeici.from_dev, efeici.from_other_dev, ip_dest_addr, efeici.from_mac_lookup_ip_addr, ip_src_addr, 4, protocol, in_dev, is_routed, in_dev, src_node_addr, dest_node_addr, layer4hdr, skb, from_ovs_params);
+	if (from_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		ecm_front_end_ipv4_interface_construct_netdev_put(&efeici);
+		goto ecm_ipv4_retry_regen;
+	}
+
+	ecm_db_connection_interfaces_reset(ci, from_list, from_list_first, ECM_DB_OBJ_DIR_FROM);
+	ecm_db_connection_interfaces_deref(from_list, from_list_first);
+
+	DEBUG_TRACE("%px: Update the 'from NAT' interface heirarchy list\n", ci);
+	if ((protocol == IPPROTO_IPV6) || (protocol == IPPROTO_ESP)) {
+		from_nat_list_first = ecm_interface_heirarchy_construct(feci, from_nat_list, efeici.from_nat_dev, efeici.from_nat_other_dev, ip_dest_addr, efeici.from_nat_mac_lookup_ip_addr, ip_src_addr_nat, 4, protocol, in_dev, is_routed, in_dev, src_node_addr_nat, dest_node_addr_nat, layer4hdr, skb, from_nat_ovs_params);
+	} else {
+		from_nat_list_first = ecm_interface_heirarchy_construct(feci, from_nat_list, efeici.from_nat_dev, efeici.from_nat_other_dev, ip_dest_addr, efeici.from_nat_mac_lookup_ip_addr, ip_src_addr_nat, 4, protocol, in_dev_nat, is_routed, in_dev_nat, src_node_addr_nat, dest_node_addr_nat, layer4hdr, skb, from_nat_ovs_params);
+	}
+
+	if (from_nat_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		ecm_front_end_ipv4_interface_construct_netdev_put(&efeici);
+		goto ecm_ipv4_retry_regen;
+	}
+
+	ecm_db_connection_interfaces_reset(ci, from_nat_list, from_nat_list_first, ECM_DB_OBJ_DIR_FROM_NAT);
+	ecm_db_connection_interfaces_deref(from_nat_list, from_nat_list_first);
+
+	DEBUG_TRACE("%px: Update the 'to' interface heirarchy list\n", ci);
+	to_list_first = ecm_interface_heirarchy_construct(feci, to_list, efeici.to_dev, efeici.to_other_dev, ip_src_addr, efeici.to_mac_lookup_ip_addr, ip_dest_addr, 4, protocol, out_dev, is_routed, in_dev, dest_node_addr, src_node_addr, layer4hdr, skb, to_ovs_params);
+	if (to_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		ecm_front_end_ipv4_interface_construct_netdev_put(&efeici);
+		goto ecm_ipv4_retry_regen;
+	}
+
+	ecm_db_connection_interfaces_reset(ci, to_list, to_list_first, ECM_DB_OBJ_DIR_TO);
+	ecm_db_connection_interfaces_deref(to_list, to_list_first);
+
+	DEBUG_TRACE("%px: Update the 'to NAT' interface heirarchy list\n", ci);
+	to_nat_list_first = ecm_interface_heirarchy_construct(feci, to_nat_list, efeici.to_nat_dev, efeici.to_nat_other_dev, ip_src_addr, efeici.to_nat_mac_lookup_ip_addr, ip_dest_addr_nat, 4, protocol, out_dev_nat, is_routed, in_dev, dest_node_addr_nat, src_node_addr_nat, layer4hdr, skb, to_nat_ovs_params);
+	if (to_nat_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		ecm_front_end_ipv4_interface_construct_netdev_put(&efeici);
+		goto ecm_ipv4_retry_regen;
+	}
+
+	ecm_front_end_ipv4_interface_construct_netdev_put(&efeici);
+
+	feci->deref(feci);
+	ecm_db_connection_interfaces_reset(ci, to_nat_list, to_nat_list_first, ECM_DB_OBJ_DIR_TO_NAT);
+	ecm_db_connection_interfaces_deref(to_nat_list, to_nat_list_first);
+
+	/*
+	 * Get list of assigned classifiers to reclassify.
+	 * Remember: This also includes our default classifier too.
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+
+	/*
+	 * All of the assigned classifiers must permit reclassification.
+	 */
+	reclassify_allowed = true;
+	for (i = 0; i < assignment_count; ++i) {
+		DEBUG_TRACE("%px: Calling to reclassify: %px, type: %d\n", ci, assignments[i], assignments[i]->type_get(assignments[i]));
+		if (!assignments[i]->reclassify_allowed(assignments[i])) {
+			DEBUG_TRACE("%px: reclassify denied: %px, by type: %d\n", ci, assignments[i], assignments[i]->type_get(assignments[i]));
+			reclassify_allowed = false;
+			break;
+		}
+	}
+
+	/*
+	 * Now we action any classifier re-classify
+	 */
+	if (!reclassify_allowed) {
+		/*
+		 * Regeneration came to a successful conclusion even though reclassification was denied
+		 */
+		DEBUG_WARN("%px: re-classify denied\n", ci);
+		goto ecm_ipv4_regen_done;
+	}
+
+	/*
+	 * Reclassify
+	 */
+	DEBUG_INFO("%px: reclassify\n", ci);
+	if (!ecm_classifier_reclassify(ci, assignment_count, assignments)) {
+		/*
+		 * We could not set up the classifiers to reclassify, it is safer to fail out and try again next time
+		 */
+		DEBUG_WARN("%px: Regeneration: reclassify failed\n", ci);
+		goto ecm_ipv4_regen_done;
+	}
+	DEBUG_INFO("%px: reclassify success\n", ci);
+
+ecm_ipv4_regen_done:
+
+	/*
+	 * Release the assignments
+	 */
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Re-generation of state is successful.
+	 */
+	ecm_db_connection_regeneration_completed(ci);
+
+	return;
+
+ecm_ipv4_retry_regen:
+	feci->deref(feci);
+	ecm_db_connection_regeneration_failed(ci);
+	return;
+}
+
+/*
+ * ecm_ipv4_ip_process()
+ *	Process IP datagram skb
+ */
+unsigned int ecm_ipv4_ip_process(struct net_device *out_dev, struct net_device *in_dev,
+							uint8_t *src_node_addr, uint8_t *dest_node_addr,
+							bool can_accel, bool is_routed, bool is_l2_encap, struct sk_buff *skb, uint16_t l2_encap_proto)
+{
+	struct ecm_tracker_ip_header ip_hdr;
+        struct nf_conn *ct;
+        enum ip_conntrack_info ctinfo;
+	struct nf_conntrack_tuple orig_tuple;
+	struct nf_conntrack_tuple reply_tuple;
+	ecm_db_direction_t ecm_dir;
+	ecm_tracker_sender_type_t sender;
+	ip_addr_t ip_src_addr;
+	ip_addr_t ip_dest_addr;
+	ip_addr_t ip_src_addr_nat;
+	ip_addr_t ip_dest_addr_nat;
+	struct net_device *out_dev_nat;
+	struct net_device *in_dev_nat;
+	uint8_t *src_node_addr_nat;
+	uint8_t *dest_node_addr_nat;
+	uint8_t protonum;
+
+	/*
+	 * Obtain the IP header from the skb
+	 */
+	if (!ecm_tracker_ip_check_header_and_read(&ip_hdr, skb)) {
+		DEBUG_WARN("Invalid ip header in skb %px\n", skb);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Process only IPv4 packets
+	 */
+	if (!ip_hdr.is_v4) {
+		DEBUG_TRACE("Not an IPv4 packet, skb %px\n", skb);
+		return NF_ACCEPT;
+	}
+
+	if (ip_hdr.fragmented) {
+		DEBUG_TRACE("skb %px is fragmented\n", skb);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Extract information, if we have conntrack then use that info as far as we can.
+	 */
+        ct = nf_ct_get(skb, &ctinfo);
+	if (unlikely(!ct)) {
+		DEBUG_TRACE("%px: no ct\n", skb);
+		ECM_IP_ADDR_TO_NIN4_ADDR(orig_tuple.src.u3.ip, ip_hdr.src_addr);
+		ECM_IP_ADDR_TO_NIN4_ADDR(orig_tuple.dst.u3.ip, ip_hdr.dest_addr);
+		orig_tuple.dst.protonum = ip_hdr.protocol;
+		reply_tuple.src.u3.ip = orig_tuple.dst.u3.ip;
+		reply_tuple.dst.u3.ip = orig_tuple.src.u3.ip;
+		sender = ECM_TRACKER_SENDER_TYPE_SRC;
+	} else {
+		/*
+		 * Do not process the packet, if the conntrack is in dying state.
+		 */
+		if (unlikely(test_bit(IPS_DYING_BIT, &ct->status))) {
+			DEBUG_WARN("%px: ct: %px is in dying state\n", skb, ct);
+			return NF_ACCEPT;
+		}
+
+		/*
+		 * Fake untracked conntrack objects were removed on 4.12 kernel version
+		 * and onwards.
+		 * So, for the newer kernels, instead of comparing the ct with the percpu
+		 * fake conntrack, we can check the ct status.
+		 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
+		if (unlikely(ct == nf_ct_untracked_get())) {
+#else
+		if (unlikely(ctinfo == IP_CT_UNTRACKED)) {
+#endif
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+			/*
+			 * If the conntrack connection is set as untracked,
+			 * ECM will accept and process only VxLAN outer flows,
+			 * otherwise such flows will not be processed by ECM.
+			 *
+			 * E.g. In the following network arramgement,
+			 * Eth1 ---> Bridge ---> VxLAN0(Bridge Port) ---> Eth0(WAN)
+			 * The packets from VxLAN0 to Eth0 will be routed.
+			 *
+			 * netif_is_vxlan API is used to identify the VxLAN device &
+			 * is_routed flag is used to identify the outer flow.
+			 */
+			if (is_routed && netif_is_vxlan(in_dev)) {
+				DEBUG_TRACE("%px: Untracked CT for VxLAN\n", skb);
+				ECM_IP_ADDR_TO_NIN4_ADDR(orig_tuple.src.u3.ip, ip_hdr.src_addr);
+				ECM_IP_ADDR_TO_NIN4_ADDR(orig_tuple.dst.u3.ip, ip_hdr.dest_addr);
+				orig_tuple.dst.protonum = ip_hdr.protocol;
+				reply_tuple.src.u3.ip = orig_tuple.dst.u3.ip;
+				reply_tuple.dst.u3.ip = orig_tuple.src.u3.ip;
+				sender = ECM_TRACKER_SENDER_TYPE_SRC;
+				ct = NULL;
+				goto vxlan_done;
+			}
+#endif
+			DEBUG_TRACE("%px: ct: untracked\n", skb);
+			return NF_ACCEPT;
+		}
+
+		/*
+		 * If the conntrack connection is using a helper (i.e. Application Layer Gateway)
+		 * then acceleration is denied (connection needs assistance from HLOS to function)
+		 */
+		if (nfct_help(ct)) {
+			DEBUG_TRACE("%px: Connection has helper\n", ct);
+			can_accel = false;
+		}
+
+		/*
+		 * Extract conntrack connection information
+		 */
+		DEBUG_TRACE("%px: ct: %px, ctinfo: %x\n", skb, ct, ctinfo);
+		orig_tuple = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple;
+		reply_tuple = ct->tuplehash[IP_CT_DIR_REPLY].tuple;
+		if (IP_CT_DIR_ORIGINAL == CTINFO2DIR(ctinfo)) {
+			sender = ECM_TRACKER_SENDER_TYPE_SRC;
+		} else {
+			sender = ECM_TRACKER_SENDER_TYPE_DEST;
+		}
+
+		/*
+		 * Is this a related connection?
+		 */
+		if ((ctinfo == IP_CT_RELATED) || (ctinfo == IP_CT_RELATED_REPLY)) {
+			/*
+			 * ct is related to the packet at hand.
+			 * We can use the IP src/dest information and the direction information.
+			 * We cannot use the protocol information from the ct (typically the packet at hand is ICMP error that is related to the ct we have here).
+			 */
+			orig_tuple.dst.protonum = ip_hdr.protocol;
+			DEBUG_TRACE("%px: related ct, actual protocol: %u\n", skb, orig_tuple.dst.protonum);
+		}
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+vxlan_done:
+		;
+#endif
+	}
+
+	/*
+	 * Check if we can accelerate the GRE protocol.
+	 */
+	if (ip_hdr.protocol == IPPROTO_GRE) {
+		if (!ecm_front_end_gre_proto_is_accel_allowed(in_dev, out_dev, skb, &orig_tuple, 4)) {
+			DEBUG_WARN("%px: GRE protocol is not allowed\n", skb);
+			return NF_ACCEPT;
+		}
+	}
+
+	/*
+	 * Check for a multicast Destination address here.
+	 */
+	ECM_NIN4_ADDR_TO_IP_ADDR(ip_dest_addr, orig_tuple.dst.u3.ip);
+	if (ecm_ip_addr_is_multicast(ip_dest_addr)) {
+#ifdef ECM_MULTICAST_ENABLE
+		if (unlikely(ecm_front_end_ipv4_mc_stopped)) {
+			DEBUG_TRACE("%px: Multicast disabled by ecm_front_end_ipv4_mc_stopped = %d\n", skb, ecm_front_end_ipv4_mc_stopped);
+			return NF_ACCEPT;
+		}
+
+		if (unlikely(!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_MULTICAST))) {
+			DEBUG_TRACE("%px: Multicast ipv4 acceleration is not supported on the selected frontend\n", skb);
+			return NF_ACCEPT;
+		}
+
+		DEBUG_TRACE("%px: CMN Multicast, Processing\n", skb);
+		return ecm_multicast_ipv4_connection_process(out_dev, in_dev, src_node_addr, dest_node_addr,
+									can_accel, is_routed, skb, &ip_hdr, ct, sender,
+									&orig_tuple, &reply_tuple);
+#else
+		return NF_ACCEPT;
+#endif
+	}
+
+	/*
+	 * Work out if this packet involves NAT or not.
+	 * If it does involve NAT then work out if this is an ingressing or egressing packet.
+	 */
+	if (orig_tuple.src.u3.ip != reply_tuple.dst.u3.ip) {
+		/*
+		 * Egressing NAT
+		 */
+		ecm_dir = ECM_DB_DIRECTION_EGRESS_NAT;
+	} else if (orig_tuple.dst.u3.ip != reply_tuple.src.u3.ip) {
+		/*
+		 * Ingressing NAT
+		 */
+		ecm_dir = ECM_DB_DIRECTION_INGRESS_NAT;
+	} else if (is_routed) {
+		/*
+		 * Non-NAT
+		 */
+		ecm_dir = ECM_DB_DIRECTION_NON_NAT;
+	} else {
+		/*
+		 * Bridged
+		 */
+		ecm_dir = ECM_DB_DIRECTION_BRIDGED;
+	}
+
+	/*
+	 * Is ecm_dir consistent with is_routed flag?
+	 * In SNAT and hairpin NAT scenario, while accessing the LAN side server with its private
+	 * IP address from another client in the same LAN, the packets come through the bridge post routing hook
+	 * have the WAN interface IP address as the SNAT address. Then in the above ecm_dir calculation,
+	 * it is calculated as ECM_DB_DIRECTION_EGRESS_NAT. So, we shouldn't accelerate the flow this time
+	 * and wait for the packet to pass through the post routing hook.
+	 *
+	 */
+	if (!is_routed && (ecm_dir != ECM_DB_DIRECTION_BRIDGED)) {
+		DEBUG_TRACE("Packet comes from bridge post routing hook but ecm_dir is not bridge\n");
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * If PPPoE bridged flows are to be handled with 3-tuple rule, set protocol to IPPROTO_RAW.
+	 */
+	protonum = orig_tuple.dst.protonum;
+#ifdef ECM_FRONT_END_NSS_ENABLE
+	if (unlikely(!is_routed && (l2_encap_proto == ETH_P_PPP_SES))) {
+		/*
+		 * Check if PPPoE bridge acceleration is 3-tuple based.
+		 */
+		if (nss_pppoe_get_br_accel_mode() == NSS_PPPOE_BR_ACCEL_MODE_EN_3T) {
+			DEBUG_TRACE("3-tuple acceleration is enabled for PPPoE bridged flows\n");
+			protonum = IPPROTO_RAW;
+		}
+	}
+#endif
+	DEBUG_TRACE("IP Packet ORIGINAL src: %pI4 ORIGINAL dst: %pI4 protocol: %u, sender: %d ecm_dir: %d\n",
+			&orig_tuple.src.u3.ip, &orig_tuple.dst.u3.ip, protonum, sender, ecm_dir);
+
+	/*
+	 * Get IP addressing information.  This same logic is applied when extracting port information too.
+	 * This is tricky to do as what we are after is src and destination addressing that is non-nat but we also need the nat information too.
+	 * INGRESS connections have their conntrack information reversed!
+	 * We have to keep in mind the connection direction AND the packet direction in order to be able to work out what is what.
+	 *
+	 * ip_src_addr and ip_dest_addr MUST always be the NON-NAT endpoint addresses and reflect PACKET direction and not connection direction 'dir'.
+	 *
+	 * Examples 1 through 4 cater for NAT and NON-NAT in the INGRESS or EGRESS cases.
+	 *
+	 * Example 1:
+	 * An 'original' direction packet to an egress connection from br-lan:192.168.0.133:12345 to eth0:80.132.221.34:80 via NAT'ing router mapping eth0:10.10.10.30:33333 looks like:
+	 *	orig_tuple->src == 192.168.0.133:12345		This becomes ip_src_addr
+	 *	orig_tuple->dst == 80.132.221.34:80		This becomes ip_dest_addr
+	 *	reply_tuple->src == 80.132.221.34:80		This becomes ip_dest_addr_nat
+	 *	reply_tuple->dest == 10.10.10.30:33333		This becomes ip_src_addr_nat
+	 *
+	 *	in_dev would be br-lan - i.e. the device of ip_src_addr
+	 *	out_dev would be eth0 - i.e. the device of ip_dest_addr
+	 *	in_dev_nat would be eth0 - i.e. out_dev, the device of ip_src_addr_nat
+	 *	out_dev_nat would be eth0 - i.e. out_dev, the device of ip_dest_addr_nat
+	 *
+	 *	From a Node address perspective we are at position X in the following topology:
+	 *	LAN_PC======BR-LAN___ETH0====X====WAN_PC
+	 *
+	 *	src_node_addr refers to node address of of ip_src_addr_nat
+	 *	src_node_addr_nat is set to src_node_addr
+	 *	src_node_addr is then set to NULL as there is no node address available here for ip_src_addr
+	 *
+	 *	dest_node_addr refers to node address of ip_dest_addr
+	 *	dest_node_addr_nat is the node of ip_dest_addr_nat which is the same as dest_node_addr
+	 *
+	 * Example 2:
+	 * However an 'original' direction packet to an ingress connection from eth0:80.132.221.34:3321 to a LAN host (e.g. via DMZ) br-lan@192.168.0.133:12345 via NAT'ing router mapping eth0:10.10.10.30:12345 looks like:
+	 *	orig_tuple->src == 80.132.221.34:3321		This becomes ip_src_addr
+	 *	orig_tuple->dst == 10.10.10.30:12345		This becomes ip_dest_addr_nat
+	 *	reply_tuple->src == 192.168.0.133:12345		This becomes ip_dest_addr
+	 *	reply_tuple->dest == 80.132.221.34:3321		This becomes ip_src_addr_nat
+	 *
+	 *	in_dev would be eth0 - i.e. the device of ip_src_addr
+	 *	out_dev would be br-lan - i.e. the device of ip_dest_addr
+	 *	in_dev_nat would be eth0 - i.e. in_dev, the device of ip_src_addr_nat
+	 *	out_dev_nat would be eth0 - i.e. in_dev, the device of ip_dest_addr_nat
+	 *
+	 *	From a Node address perspective we are at position X in the following topology:
+	 *	LAN_PC===X===BR-LAN___ETH0========WAN_PC
+	 *
+	 *	src_node_addr refers to node address of br-lan which is not useful
+	 *	src_node_addr_nat AND src_node_addr become NULL
+	 *
+	 *	dest_node_addr refers to node address of ip_dest_addr
+	 *	dest_node_addr_nat is set to NULL
+	 *
+	 * When dealing with reply packets this confuses things even more.  Reply packets to the above two examples are as follows:
+	 *
+	 * Example 3:
+	 * A 'reply' direction packet to the egress connection above:
+	 *	orig_tuple->src == 192.168.0.133:12345		This becomes ip_dest_addr
+	 *	orig_tuple->dst == 80.132.221.34:80		This becomes ip_src_addr
+	 *	reply_tuple->src == 80.132.221.34:80		This becomes ip_src_addr_nat
+	 *	reply_tuple->dest == 10.10.10.30:33333		This becomes ip_dest_addr_nat
+	 *
+	 *	in_dev would be eth0 - i.e. the device of ip_src_addr
+	 *	out_dev would be br-lan - i.e. the device of ip_dest_addr
+	 *	in_dev_nat would be eth0 - i.e. in_dev, the device of ip_src_addr_nat
+	 *	out_dev_nat would be eth0 - i.e. in_dev, the device of ip_dest_addr_nat
+	 *
+	 *	From a Node address perspective we are at position X in the following topology:
+	 *	LAN_PC===X===BR-LAN___ETH0========WAN_PC
+	 *
+	 *	src_node_addr refers to node address of br-lan which is not useful
+	 *	src_node_addr_nat AND src_node_addr become NULL
+	 *
+	 *	dest_node_addr refers to node address of ip_dest_addr
+	 *	dest_node_addr_nat is set to NULL
+	 *
+	 * Example 4:
+	 * A 'reply' direction packet to the ingress connection above:
+	 *	orig_tuple->src == 80.132.221.34:3321		This becomes ip_dest_addr
+	 *	orig_tuple->dst == 10.10.10.30:12345		This becomes ip_src_addr_nat
+	 *	reply_tuple->src == 192.168.0.133:12345		This becomes ip_src_addr
+	 *	reply_tuple->dest == 80.132.221.34:3321		This becomes ip_dest_addr_nat
+	 *
+	 *	in_dev would be br-lan - i.e. the device of ip_src_addr
+	 *	out_dev would be eth0 - i.e. the device of ip_dest_addr
+	 *	in_dev_nat would be eth0 - i.e. out_dev, the device of ip_src_addr_nat
+	 *	out_dev_nat would be eth0 - i.e. out_dev, the device of ip_dest_addr_nat
+	 *
+	 *	From a Node address perspective we are at position X in the following topology:
+	 *	LAN_PC======BR-LAN___ETH0====X====WAN_PC
+	 *
+	 *	src_node_addr refers to node address of ip_src_addr_nat
+	 *	src_node_addr_nat is set to src_node_addr
+	 *	src_node_addr becomes NULL
+	 *
+	 *	dest_node_addr refers to node address of ip_dest_addr
+	 *	dest_node_addr_nat is set to dest_node_addr also.
+	 *
+	 * The following examples are for BRIDGED cases:
+	 *
+	 * Example 5:
+	 * An 'original' direction packet to an bridged connection from eth1:192.168.0.133:12345 to eth2:192.168.0.244:80 looks like:
+	 *	orig_tuple->src == 192.168.0.133:12345		This becomes ip_src_addr
+	 *	orig_tuple->dst == 192.168.0.244:80		This becomes ip_dest_addr
+	 *	reply_tuple->src == 192.168.0.244:80		This becomes ip_dest_addr_nat
+	 *	reply_tuple->dest == 192.168.0.133:12345	This becomes ip_src_addr_nat
+	 *
+	 *	in_dev would be eth1 - i.e. the device of ip_src_addr
+	 *	out_dev would be eth2 - i.e. the device of ip_dest_addr
+	 *	in_dev_nat would be eth1 - i.e. in_dev, the device of ip_src_addr_nat
+	 *	out_dev_nat would be eth2 - i.e. out_dev, the device of ip_dest_addr_nat
+	 *
+	 *	From a Node address perspective we are at position X in the following topology:
+	 *	LAN PC======ETH1___ETH2====X====LAN PC
+	 *
+	 *	src_node_addr refers to node address of ip_src_addr
+	 *	src_node_addr_nat is set to src_node_addr
+	 *
+	 *	dest_node_addr refers to node address of ip_dest_addr
+	 *	dest_node_addr_nat is set to dest_node_addr
+	 *
+	 * Example 6:
+	 * An 'reply' direction packet to the bridged connection above:
+	 *	orig_tuple->src == 192.168.0.133:12345		This becomes ip_dest_addr
+	 *	orig_tuple->dst == 192.168.0.244:80		This becomes ip_src_addr
+	 *	reply_tuple->src == 192.168.0.244:80		This becomes ip_src_addr_nat
+	 *	reply_tuple->dest == 192.168.0.133:12345	This becomes ip_dest_addr_nat
+	 *
+	 *	in_dev would be eth2 - i.e. the device of ip_src_addr
+	 *	out_dev would be eth1 - i.e. the device of ip_dest_addr
+	 *	in_dev_nat would be eth2 - i.e. in_dev, the device of ip_src_addr_nat
+	 *	out_dev_nat would be eth1 - i.e. out_dev, the device of ip_dest_addr_nat
+	 *
+	 *	From a Node address perspective we are at position X in the following topology:
+	 *	LAN PC===X===ETH1___ETH2========LAN PC
+	 *
+	 *	src_node_addr refers to node address of ip_src_addr
+	 *	src_node_addr_nat is set to src_node_addr
+	 *
+	 *	dest_node_addr refers to node address of ip_dest_addr
+	 *	dest_node_addr_nat is set to dest_node_addr
+	 */
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		if ((ecm_dir == ECM_DB_DIRECTION_EGRESS_NAT) || (ecm_dir == ECM_DB_DIRECTION_NON_NAT)) {
+			/*
+			 * Example 1
+			 */
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_src_addr, orig_tuple.src.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_dest_addr, orig_tuple.dst.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_dest_addr_nat, reply_tuple.src.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_src_addr_nat, reply_tuple.dst.u3.ip);
+
+			in_dev_nat = out_dev;
+			out_dev_nat = out_dev;
+
+			src_node_addr_nat = src_node_addr;
+			src_node_addr = NULL;
+
+			dest_node_addr_nat = dest_node_addr;
+		} else if (ecm_dir == ECM_DB_DIRECTION_INGRESS_NAT) {
+			/*
+			 * Example 2
+			 */
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_src_addr, orig_tuple.src.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_dest_addr_nat, orig_tuple.dst.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_dest_addr, reply_tuple.src.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_src_addr_nat, reply_tuple.dst.u3.ip);
+
+			in_dev_nat = in_dev;
+			out_dev_nat = in_dev;
+
+			src_node_addr = NULL;
+			src_node_addr_nat = NULL;
+
+			dest_node_addr_nat = NULL;
+		} else if (ecm_dir == ECM_DB_DIRECTION_BRIDGED) {
+			/*
+			 * Example 5
+			 */
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_src_addr, orig_tuple.src.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_dest_addr, orig_tuple.dst.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_dest_addr_nat, reply_tuple.src.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_src_addr_nat, reply_tuple.dst.u3.ip);
+
+			in_dev_nat = in_dev;
+			out_dev_nat = out_dev;
+
+			src_node_addr_nat = src_node_addr;
+
+			dest_node_addr_nat = dest_node_addr;
+		} else {
+			DEBUG_ASSERT(false, "Unhandled ecm_dir: %d\n", ecm_dir);
+		}
+	} else {
+		if ((ecm_dir == ECM_DB_DIRECTION_EGRESS_NAT) || (ecm_dir == ECM_DB_DIRECTION_NON_NAT)) {
+			/*
+			 * Example 3
+			 */
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_dest_addr, orig_tuple.src.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_src_addr, orig_tuple.dst.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_src_addr_nat, reply_tuple.src.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_dest_addr_nat, reply_tuple.dst.u3.ip);
+
+			in_dev_nat  = in_dev;
+			out_dev_nat = in_dev;
+
+			src_node_addr = NULL;
+			src_node_addr_nat = NULL;
+
+			dest_node_addr_nat = NULL;
+		} else if (ecm_dir == ECM_DB_DIRECTION_INGRESS_NAT) {
+			/*
+			 * Example 4
+			 */
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_dest_addr, orig_tuple.src.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_src_addr_nat, orig_tuple.dst.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_src_addr, reply_tuple.src.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_dest_addr_nat, reply_tuple.dst.u3.ip);
+
+			in_dev_nat = out_dev;
+			out_dev_nat = out_dev;
+
+			src_node_addr_nat = src_node_addr;
+			src_node_addr = NULL;
+
+			dest_node_addr_nat = dest_node_addr;
+		} else if (ecm_dir == ECM_DB_DIRECTION_BRIDGED) {
+			/*
+			 * Example 6
+			 */
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_dest_addr, orig_tuple.src.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_src_addr, orig_tuple.dst.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_src_addr_nat, reply_tuple.src.u3.ip);
+			ECM_NIN4_ADDR_TO_IP_ADDR(ip_dest_addr_nat, reply_tuple.dst.u3.ip);
+
+			in_dev_nat  = in_dev;
+			out_dev_nat = out_dev;
+
+			src_node_addr_nat = src_node_addr;
+
+			dest_node_addr_nat = dest_node_addr;
+		} else {
+			DEBUG_ASSERT(false, "Unhandled ecm_dir: %d\n", ecm_dir);
+		}
+	}
+
+	/*
+	 * Non-unicast source or destination packets are ignored
+	 * NOTE: Only need to check the non-nat src/dest addresses here.
+	 */
+	if (unlikely(ecm_ip_addr_is_non_unicast(ip_dest_addr))) {
+		DEBUG_TRACE("skb %px non-unicast daddr " ECM_IP_ADDR_DOT_FMT "\n", skb, ECM_IP_ADDR_TO_DOT(ip_dest_addr));
+		return NF_ACCEPT;
+	}
+	if (unlikely(ecm_ip_addr_is_non_unicast(ip_src_addr))) {
+		DEBUG_TRACE("skb %px non-unicast saddr " ECM_IP_ADDR_DOT_FMT "\n", skb, ECM_IP_ADDR_TO_DOT(ip_src_addr));
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Process IP specific protocol
+	 * TCP and UDP are the most likliest protocols.
+	 */
+	if (likely(protonum == IPPROTO_TCP) || likely(protonum == IPPROTO_UDP)) {
+		return ecm_ported_ipv4_process(out_dev, out_dev_nat,
+				in_dev, in_dev_nat,
+				src_node_addr, src_node_addr_nat,
+				dest_node_addr, dest_node_addr_nat,
+				can_accel, is_routed, is_l2_encap, skb,
+				&ip_hdr,
+				ct, sender, ecm_dir,
+				&orig_tuple, &reply_tuple,
+				ip_src_addr, ip_dest_addr, ip_src_addr_nat, ip_dest_addr_nat, l2_encap_proto);
+	}
+#ifdef ECM_NON_PORTED_SUPPORT_ENABLE
+	if (unlikely(!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_NON_PORTED))) {
+		DEBUG_TRACE("%px: Non-ported ipv4 acceleration is not supported on the selected frontend\n", skb);
+		return NF_ACCEPT;
+	}
+
+	return ecm_non_ported_ipv4_process(out_dev, out_dev_nat,
+				in_dev, in_dev_nat,
+				src_node_addr, src_node_addr_nat,
+				dest_node_addr, dest_node_addr_nat,
+				can_accel, is_routed, is_l2_encap, skb,
+				&ip_hdr,
+				ct, sender, ecm_dir,
+				&orig_tuple, &reply_tuple,
+				ip_src_addr, ip_dest_addr, ip_src_addr_nat, ip_dest_addr_nat, l2_encap_proto);
+#else
+	return NF_ACCEPT;
+#endif
+}
+
+/*
+ * ecm_ipv4_post_routing_hook()
+ *	Called for IP packets that are going out to interfaces after IP routing stage.
+ */
+static unsigned int ecm_ipv4_post_routing_hook(void *priv,
+				struct sk_buff *skb,
+				const struct nf_hook_state *nhs)
+{
+	struct net_device *out = nhs->out;
+	struct net_device *in;
+	bool can_accel = true;
+	unsigned int result;
+
+	DEBUG_TRACE("%px: IPv4 CMN Routing: %s\n", out, out->name);
+
+	/*
+	 * If operations have stopped then do not process packets
+	 */
+	spin_lock_bh(&ecm_ipv4_lock);
+	if (unlikely(ecm_front_end_ipv4_stopped)) {
+		spin_unlock_bh(&ecm_ipv4_lock);
+		DEBUG_TRACE("Front end stopped\n");
+		return NF_ACCEPT;
+	}
+	spin_unlock_bh(&ecm_ipv4_lock);
+
+	/*
+	 * Don't process broadcast or multicast
+	 */
+	if (skb->pkt_type == PACKET_BROADCAST) {
+		DEBUG_TRACE("Broadcast, ignoring: %px\n", skb);
+		return NF_ACCEPT;
+	}
+
+#ifndef ECM_INTERFACE_PPTP_ENABLE
+	/*
+	 * skip pptp because we don't accelerate them
+	 */
+	if (ecm_interface_is_pptp(skb, out)) {
+		return NF_ACCEPT;
+	}
+#endif
+
+#ifndef ECM_INTERFACE_L2TPV2_ENABLE
+	/*
+	 * skip l2tpv2 because we don't accelerate them
+	 */
+	if (ecm_interface_is_l2tp_packet_by_version(skb, out, 2)) {
+		return NF_ACCEPT;
+	}
+#endif
+
+	/*
+	 * skip l2tpv3 because we don't accelerate them
+	 */
+	if (ecm_interface_is_l2tp_packet_by_version(skb, out, 3)) {
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Identify interface from where this packet came
+	 */
+	in = dev_get_by_index(&init_net, skb->skb_iif);
+	if (unlikely(!in)) {
+		/*
+		 * Locally sourced packets are not processed in ECM.
+		 */
+		return NF_ACCEPT;
+	}
+
+#ifndef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+	/*
+	 * skip OpenVSwitch flows because we don't accelerate them
+	 */
+	if (netif_is_ovs_master(out) || netif_is_ovs_master(in)) {
+		dev_put(in);
+		return NF_ACCEPT;
+	}
+#endif
+
+	DEBUG_TRACE("CMN Post routing process skb %px, out: %px (%s), in: %px (%s)\n", skb, out, out->name, in, in->name);
+	result = ecm_ipv4_ip_process((struct net_device *)out, in, NULL, NULL,
+							can_accel, true, false, skb, 0);
+	dev_put(in);
+	return result;
+}
+
+/*
+ * ecm_ipv4_pppoe_bridge_process()
+ *	Called for PPPoE session packets that are going
+ *	out to one of the bridge physical interfaces.
+ */
+static unsigned int ecm_ipv4_pppoe_bridge_process(struct net_device *out,
+						     struct net_device *in,
+						     struct ethhdr *skb_eth_hdr,
+						     bool can_accel,
+						     struct sk_buff *skb)
+{
+	struct ecm_tracker_ip_header ip_hdr;
+	unsigned int result = NF_ACCEPT;
+	struct pppoe_hdr *ph = pppoe_hdr(skb);
+	uint16_t ppp_proto = *(uint16_t *)ph->tag;
+	uint32_t encap_header_len = 0;
+
+	ppp_proto = ntohs(ppp_proto);
+	if (ppp_proto != PPP_IP) {
+		return NF_ACCEPT;
+	}
+
+	encap_header_len = ecm_front_end_l2_encap_header_len(ntohs(skb->protocol));
+	ecm_front_end_pull_l2_encap_header(skb, encap_header_len);
+	skb->protocol = htons(ETH_P_IP);
+
+	if (!ecm_tracker_ip_check_header_and_read(&ip_hdr, skb)) {
+		DEBUG_WARN("Invalid ip header in skb %px\n", skb);
+		goto skip_ipv4_process;
+	}
+
+	/*
+	 * Return if destination IP address is multicast address.
+	 */
+	if (ecm_ip_addr_is_multicast(ip_hdr.dest_addr)) {
+		DEBUG_WARN("Multicast acceleration is not support in PPPoE bridge %px\n", skb);
+		goto skip_ipv4_process;
+	}
+
+	result = ecm_ipv4_ip_process(out, in, skb_eth_hdr->h_source,
+					 skb_eth_hdr->h_dest, can_accel,
+					 false, true, skb, ETH_P_PPP_SES);
+skip_ipv4_process:
+	ecm_front_end_push_l2_encap_header(skb, encap_header_len);
+	skb->protocol = htons(ETH_P_PPP_SES);
+
+	return result;
+}
+
+/*
+ * ecm_ipv4_bridge_post_routing_hook()
+ *	Called for packets that are going out to one of the bridge physical interfaces.
+ *
+ * These may have come from another bridged interface or from a non-bridged interface.
+ * Conntrack information may be available or not if this skb is bridged.
+ */
+static unsigned int ecm_ipv4_bridge_post_routing_hook(void *priv,
+					struct sk_buff *skb,
+					const struct nf_hook_state *nhs)
+{
+	struct net_device *out = nhs->out;
+	struct ethhdr *skb_eth_hdr;
+	uint16_t eth_type;
+	struct net_device *bridge;
+	struct net_device *in;
+	bool can_accel = true;
+	unsigned int result = NF_ACCEPT;
+
+	DEBUG_TRACE("%px: IPv4 CMN Bridge: %s\n", out, out->name);
+
+	/*
+	 * If operations have stopped then do not process packets
+	 */
+	spin_lock_bh(&ecm_ipv4_lock);
+	if (unlikely(ecm_front_end_ipv4_stopped)) {
+		spin_unlock_bh(&ecm_ipv4_lock);
+		DEBUG_TRACE("Front end stopped\n");
+		return NF_ACCEPT;
+	}
+	spin_unlock_bh(&ecm_ipv4_lock);
+
+	/*
+	 * Don't process broadcast or multicast
+	 */
+	if (skb->pkt_type == PACKET_BROADCAST) {
+		DEBUG_TRACE("Broadcast, ignoring: %px\n", skb);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * skip l2tp/pptp because we don't accelerate them
+	 */
+	if (ecm_interface_is_l2tp_pptp(skb, out)) {
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Check packet is an IP Ethernet packet
+	 */
+	skb_eth_hdr = eth_hdr(skb);
+	if (!skb_eth_hdr) {
+		DEBUG_TRACE("%px: Not Eth\n", skb);
+		return NF_ACCEPT;
+	}
+	eth_type = ntohs(skb_eth_hdr->h_proto);
+	if (unlikely((eth_type != 0x0800) && (eth_type != ETH_P_PPP_SES))) {
+		DEBUG_TRACE("%px: Not IP/PPPoE session: %d\n", skb, eth_type);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Identify interface from where this packet came.
+	 * There are three scenarios to consider here:
+	 * 1. Packet came from a local source.
+	 *	Ignore - local is not handled.
+	 * 2. Packet came from a routed path.
+	 *	Ignore - it was handled in INET post routing.
+	 * 3. Packet is bridged from another port.
+	 *	Process.
+	 *
+	 * Begin by identifying case 1.
+	 * NOTE: We are given 'out' (which we implicitly know is a bridge port) so out interface's master is the 'bridge'.
+	 */
+	bridge = ecm_interface_get_and_hold_dev_master((struct net_device *)out);
+	DEBUG_ASSERT(bridge, "Expected bridge\n");
+	in = dev_get_by_index(&init_net, skb->skb_iif);
+	if  (!in) {
+		/*
+		 * Case 1.
+		 */
+		DEBUG_TRACE("Local traffic: %px, ignoring traffic to bridge: %px (%s) \n", skb, bridge, bridge->name);
+		dev_put(bridge);
+		return NF_ACCEPT;
+	}
+	dev_put(in);
+
+	/*
+	 * Case 2:
+	 *	For routed packets the skb will have the src mac matching the bridge mac.
+	 * Case 3:
+	 *	If the packet was not local (case 1) or routed (case 2) then
+	 *	we process. There is an exception to case 2: when hairpin mode
+	 *	is enabled, we process.
+	 */
+
+	/*
+	 * Pass in NULL (for skb) and 0 for cookie since doing FDB lookup only
+	 */
+	in = br_port_dev_get(bridge, skb_eth_hdr->h_source, NULL, 0);
+	if (!in) {
+		DEBUG_TRACE("skb: %px, no in device for bridge: %px (%s)\n", skb, bridge, bridge->name);
+		dev_put(bridge);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * This flag needs to be checked in slave port(eth0/ath0)
+	 * and not on master interface(br-lan). Hairpin flag can be
+	 * enabled/disabled for ports individually.
+	 */
+	if (in == out) {
+		if (!br_is_hairpin_enabled(in)) {
+			DEBUG_TRACE("skb: %px, bridge: %px (%s), ignoring"
+					"the packet, hairpin not enabled"
+					"on port %px (%s)\n", skb, bridge,
+					bridge->name, out, out->name);
+			goto skip_ipv4_bridge_flow;
+		}
+		DEBUG_TRACE("skb: %px, bridge: %px (%s), hairpin enabled on port"
+				"%px (%s)\n", skb, bridge, bridge->name, out, out->name);
+	}
+
+	/*
+	 * Case 2: Routed trafffic would be handled by the INET post routing.
+	 */
+	if (!ecm_mac_addr_equal(skb_eth_hdr->h_source, bridge->dev_addr)) {
+		DEBUG_TRACE("skb: %px, Ignoring routed packet to bridge: %px (%s)\n", skb, bridge, bridge->name);
+		goto skip_ipv4_bridge_flow;
+	}
+
+	if (!is_multicast_ether_addr(skb_eth_hdr->h_dest)) {
+		/*
+		 * Process the packet, if we have this mac address in the fdb table.
+		 * TODO: For the kernel versions later than 3.6.x, the API needs vlan id.
+		 * 	 For now, we are passing 0, but this needs to be handled later.
+		 */
+		if (!br_fdb_has_entry((struct net_device *)out, skb_eth_hdr->h_dest, 0)) {
+			DEBUG_WARN("skb: %px, No fdb entry for this mac address %pM in the bridge: %px (%s)\n",
+					skb, skb_eth_hdr->h_dest, bridge, bridge->name);
+			goto skip_ipv4_bridge_flow;
+		}
+	}
+	DEBUG_TRACE("CMN Bridge process skb: %px, bridge: %px (%s), In: %px (%s), Out: %px (%s)\n",
+			skb, bridge, bridge->name, in, in->name, out, out->name);
+
+	if (unlikely(eth_type == ETH_P_PPP_SES)) {
+
+#ifdef ECM_FRONT_END_NSS_ENABLE
+		/*
+		 * Check if PPPoE bridge acceleration is disabled.
+		 */
+		if (nss_pppoe_get_br_accel_mode() == NSS_PPPOE_BR_ACCEL_MODE_DIS) {
+			DEBUG_TRACE("skb: %px, PPPoE bridge flow acceleration is disabled\n", skb);
+			goto skip_ipv4_bridge_flow;
+		}
+#endif
+
+		result = ecm_ipv4_pppoe_bridge_process((struct net_device *)out, in, skb_eth_hdr, can_accel, skb);
+		goto skip_ipv4_bridge_flow;
+	}
+	result = ecm_ipv4_ip_process((struct net_device *)out, in,
+				skb_eth_hdr->h_source, skb_eth_hdr->h_dest, can_accel, false, false, skb, 0);
+skip_ipv4_bridge_flow:
+	dev_put(in);
+	dev_put(bridge);
+	return result;
+}
+
+/*
+ * struct nf_hook_ops ecm_ipv4_netfilter_routing_hooks[]
+ *	Hooks into netfilter routing packet monitoring points.
+ */
+static struct nf_hook_ops ecm_ipv4_netfilter_routing_hooks[] __read_mostly = {
+	/*
+	 * Post routing hook is used to monitor packets going to interfaces that are NOT bridged in some way, e.g. packets to the WAN.
+	 */
+	{
+		.hook           = ecm_ipv4_post_routing_hook,
+		.pf             = PF_INET,
+		.hooknum        = NF_INET_POST_ROUTING,
+		.priority       = NF_IP_PRI_NAT_SRC + 1,
+	},
+};
+
+/*
+ * struct nf_hook_ops ecm_ipv4_netfilter_bridge_hooks[]
+ *	Hooks into netfilter bridge packet monitoring points.
+ */
+static struct nf_hook_ops ecm_ipv4_netfilter_bridge_hooks[] __read_mostly = {
+	/*
+	 * The bridge post routing hook monitors packets going to interfaces that are part of a bridge arrangement.
+	 * For example Wireles LAN (WLAN) and Wired LAN (LAN).
+	 */
+	{
+		.hook		= ecm_ipv4_bridge_post_routing_hook,
+		.pf		= PF_BRIDGE,
+		.hooknum	= NF_BR_POST_ROUTING,
+		.priority	= NF_BR_PRI_FILTER_OTHER,
+	},
+};
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+/*
+ * ecm_ipv4_ovs_dp_process()
+ *      Process OVS IPv4 bridged packets.
+ */
+unsigned int ecm_ipv4_ovs_dp_process(struct sk_buff *skb, struct net_device *out)
+{
+	struct ethhdr *skb_eth_hdr;
+	bool can_accel = true;
+	struct net_device *in;
+
+	/*
+	 * If operations have stopped then do not process packets
+	 */
+	spin_lock_bh(&ecm_ipv4_lock);
+	if (unlikely(ecm_front_end_ipv4_stopped)) {
+		spin_unlock_bh(&ecm_ipv4_lock);
+		DEBUG_TRACE("Front end stopped\n");
+		return 1;
+	}
+	spin_unlock_bh(&ecm_ipv4_lock);
+
+	/*
+	 * Don't process broadcast.
+	 */
+	if (skb->pkt_type == PACKET_BROADCAST) {
+		DEBUG_TRACE("Broadcast, ignoring: %px\n", skb);
+		return 1;
+	}
+
+	/*
+	 * Don't process multicast packet if frontend does not support it
+	 */
+	if (skb->pkt_type == PACKET_MULTICAST) {
+		if (!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_MULTICAST)) {
+			DEBUG_TRACE("Frontend does not support mcast, ignoring: %px\n", skb);
+			return 1;
+		}
+	}
+
+	if (skb->protocol != ntohs(ETH_P_IP)) {
+		DEBUG_WARN("%px: Wrong skb protocol: %d", skb, skb->protocol);
+		return 1;
+	}
+
+	skb_eth_hdr = eth_hdr(skb);
+	if (!skb_eth_hdr) {
+		DEBUG_WARN("%px: Not Eth\n", skb);
+		return 1;
+	}
+
+	in = dev_get_by_index(&init_net, skb->skb_iif);
+	if (!in) {
+		DEBUG_WARN("%px: No in device\n", skb);
+		return 1;
+	}
+
+	DEBUG_TRACE("%px: in: %s out: %s skb->protocol: %x\n", skb, in->name, out->name, skb->protocol);
+
+	if (netif_is_ovs_master(in)) {
+		if (!ecm_mac_addr_equal(skb_eth_hdr->h_dest, in->dev_addr)) {
+			DEBUG_TRACE("%px: in is bridge and mac address equals to packet dest, flow is routed, ignore \n", skb);
+			dev_put(in);
+			return 1;
+		}
+	}
+
+	if (netif_is_ovs_master(out)) {
+		if (!ecm_mac_addr_equal(skb_eth_hdr->h_source, out->dev_addr)) {
+			DEBUG_TRACE("%px: out is bridge and mac address equals to packet source, flow is routed, ignore \n", skb);
+			dev_put(in);
+			return 1;
+		}
+	}
+
+	ecm_ipv4_ip_process((struct net_device *)out, in,
+			skb_eth_hdr->h_source, skb_eth_hdr->h_dest, can_accel, false, false, skb, ETH_P_IP);
+
+	dev_put(in);
+
+	return 0;
+}
+
+static struct ovsmgr_dp_hook_ops ecm_ipv4_dp_hooks = {
+	.protocol = 4,
+	.hook_num = OVSMGR_DP_HOOK_POST_FLOW_PROC,
+	.hook = ecm_ipv4_ovs_dp_process,
+};
+#endif
+
+/*
+ * ecm_ipv4_init()
+ */
+int ecm_ipv4_init(struct dentry *dentry)
+{
+	int result;
+
+	DEBUG_INFO("ECM CMN IPv4 init\n");
+
+#ifdef ECM_FRONT_END_NSS_ENABLE
+	result = ecm_nss_ipv4_init(dentry);
+	if (result < 0) {
+		DEBUG_ERROR("Can't initialize NSS ipv4\n");
+		return result;
+	}
+#endif
+	result = ecm_sfe_ipv4_init(dentry);
+	if (result < 0) {
+		DEBUG_ERROR("Can't initialize SFE ipv4\n");
+		goto sfe_ipv4_failed;
+	}
+
+	/*
+	 * Register netfilter routing hooks
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	result = nf_register_hooks(ecm_ipv4_netfilter_routing_hooks, ARRAY_SIZE(ecm_ipv4_netfilter_routing_hooks));
+#else
+	result = nf_register_net_hooks(&init_net, ecm_ipv4_netfilter_routing_hooks, ARRAY_SIZE(ecm_ipv4_netfilter_routing_hooks));
+#endif
+	if (result < 0) {
+		DEBUG_ERROR("Can't register common netfilter routing hooks.\n");
+		goto nf_register_failed_1;
+	}
+
+	/*
+	 * Register netfilter bridge hooks, if the frontend type supports it. SFE only mode doesn't support it.
+	 */
+	if (ecm_front_end_is_feature_supported(ECM_FE_FEATURE_BRIDGE)) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+		result = nf_register_hooks(ecm_ipv4_netfilter_bridge_hooks, ARRAY_SIZE(ecm_ipv4_netfilter_bridge_hooks));
+#else
+		result = nf_register_net_hooks(&init_net, ecm_ipv4_netfilter_bridge_hooks, ARRAY_SIZE(ecm_ipv4_netfilter_bridge_hooks));
+#endif
+		if (result < 0) {
+			DEBUG_ERROR("Can't register common netfilter bridge hooks.\n");
+			goto nf_register_failed_2;
+		}
+	}
+
+	/*
+	 * Register OVS bridge DP hookup when AE frontend supports bridge processing
+	 */
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+	if (ecm_front_end_is_feature_supported(ECM_FE_FEATURE_OVS_BRIDGE)) {
+		ovsmgr_dp_hook_register(&ecm_ipv4_dp_hooks);
+	}
+#endif
+
+	return 0;
+
+nf_register_failed_2:
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	nf_unregister_hooks(ecm_ipv4_netfilter_routing_hooks, ARRAY_SIZE(ecm_ipv4_netfilter_routing_hooks));
+#else
+	nf_unregister_net_hooks(&init_net, ecm_ipv4_netfilter_routing_hooks, ARRAY_SIZE(ecm_ipv4_netfilter_routing_hooks));
+#endif
+nf_register_failed_1:
+	ecm_sfe_ipv4_exit();
+
+sfe_ipv4_failed:
+#ifdef ECM_FRONT_END_NSS_ENABLE
+	ecm_nss_ipv4_exit();
+#endif
+	return result;
+}
+
+/*
+ * ecm_ipv4_exit()
+ */
+void ecm_ipv4_exit(void)
+{
+	DEBUG_INFO("ECM CMN IPv4 Module exit\n");
+
+	spin_lock_bh(&ecm_ipv4_lock);
+	ecm_ipv4_terminate_pending = true;
+	spin_unlock_bh(&ecm_ipv4_lock);
+
+	/*
+	 * Unregister the netfilter bridge hooks, if the frontend type supports it. SFE only mode doesn't support it.
+	 */
+	if (ecm_front_end_is_feature_supported(ECM_FE_FEATURE_BRIDGE)) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+		nf_unregister_hooks(ecm_ipv4_netfilter_bridge_hooks, ARRAY_SIZE(ecm_ipv4_netfilter_bridge_hooks));
+#else
+		nf_unregister_net_hooks(&init_net, ecm_ipv4_netfilter_bridge_hooks, ARRAY_SIZE(ecm_ipv4_netfilter_bridge_hooks));
+#endif
+	}
+
+	/*
+	 * Unregister the netfilter routing hooks.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	nf_unregister_hooks(ecm_ipv4_netfilter_routing_hooks, ARRAY_SIZE(ecm_ipv4_netfilter_routing_hooks));
+#else
+	nf_unregister_net_hooks(&init_net, ecm_ipv4_netfilter_routing_hooks, ARRAY_SIZE(ecm_ipv4_netfilter_routing_hooks));
+#endif
+
+	/*
+	 * Unregister OVS bridge DP hook
+	 */
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+	if (ecm_front_end_is_feature_supported(ECM_FE_FEATURE_OVS_BRIDGE)) {
+		ovsmgr_dp_hook_unregister(&ecm_ipv4_dp_hooks);
+	}
+#endif
+
+	ecm_sfe_ipv4_exit();
+#ifdef ECM_FRONT_END_NSS_ENABLE
+	ecm_nss_ipv4_exit();
+#endif
+}
diff --git a/qca-nss-ecm/frontends/cmn/ecm_ipv4.h b/qca-nss-ecm/frontends/cmn/ecm_ipv4.h
new file mode 100644
index 0000000..3a7424a
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_ipv4.h
@@ -0,0 +1,42 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2016, 2020-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * Locking of the classifier - concurrency control for file global parameters.
+ * NOTE: It is safe to take this lock WHILE HOLDING a feci->lock.  The reverse is NOT SAFE.
+ */
+extern spinlock_t ecm_ipv4_lock;			/* Protect against SMP access between netfilter, events and private threaded function. */
+
+/*
+ * Management thread control
+ */
+extern bool ecm_ipv4_terminate_pending;		/* True when the user has signalled we should quit */
+
+extern unsigned int ecm_ipv4_ip_process(struct net_device *out_dev, struct net_device *in_dev,
+							uint8_t *src_node_addr, uint8_t *dest_node_addr,
+							bool can_accel, bool is_routed, bool is_l2_encap, struct sk_buff *skb, uint16_t l2_encap_proto);
+extern void ecm_ipv4_connection_regenerate(struct ecm_db_connection_instance *ci, ecm_tracker_sender_type_t sender,
+							struct net_device *out_dev, struct net_device *out_dev_nat,
+							struct net_device *in_dev, struct net_device *in_dev_nat,
+							__be16 *layer4hdr, struct sk_buff *skb);
+extern struct ecm_db_node_instance *ecm_ipv4_node_establish_and_ref(struct ecm_front_end_connection_instance *feci,
+							struct net_device *dev, ip_addr_t addr,
+							struct ecm_db_iface_instance *interface_list[], int32_t interface_list_first,
+							uint8_t *given_node_addr, struct sk_buff *skb);
+extern struct ecm_db_host_instance *ecm_ipv4_host_establish_and_ref(ip_addr_t addr);
+extern struct ecm_db_mapping_instance *ecm_ipv4_mapping_establish_and_ref(ip_addr_t addr, int port);
+extern int ecm_ipv4_init(struct dentry *dentry);
+extern void ecm_ipv4_exit(void);
diff --git a/qca-nss-ecm/frontends/cmn/ecm_ipv6.c b/qca-nss-ecm/frontends/cmn/ecm_ipv6.c
new file mode 100644
index 0000000..fc37eb8
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_ipv6.c
@@ -0,0 +1,1793 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/debugfs.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/ip_tunnels.h>
+#include <net/ip6_route.h>
+#include <net/ip6_fib.h>
+#include <net/addrconf.h>
+#include <net/ipv6.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <net/xfrm.h>
+#include <linux/inet.h>
+#include <linux/in6.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/ppp_defs.h>
+#include <linux/mroute6.h>
+#include <linux/vmalloc.h>
+
+#include <net/ip6_tunnel.h>
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv6.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+#include <net/vxlan.h>
+#endif
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <linux/netfilter/nf_conntrack_zones_common.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/nf_conntrack_timeout.h>
+#include <net/netfilter/ipv6/nf_conntrack_ipv6.h>
+#include <net/netfilter/ipv6/nf_defrag_ipv6.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_IPV6_DEBUG_LEVEL
+
+#ifdef ECM_MULTICAST_ENABLE
+#include <mc_ecm.h>
+#endif
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+#include "ecm_classifier_nl.h"
+#endif
+#include "ecm_interface.h"
+#include "ecm_front_end_common.h"
+#include "ecm_front_end_ipv6.h"
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+#include <ovsmgr.h>
+#endif
+#include "ecm_ported_ipv6.h"
+#include "ecm_non_ported_ipv6.h"
+#include "ecm_multicast_ipv6.h"
+
+/*
+ * Locking of the classifier - concurrency control for file global parameters.
+ * NOTE: It is safe to take this lock WHILE HOLDING a feci->lock.  The reverse is NOT SAFE.
+ */
+DEFINE_SPINLOCK(ecm_ipv6_lock);			/* Protect against SMP access between netfilter, events and private threaded function. */
+
+/*
+ * Management thread control
+ */
+bool ecm_ipv6_terminate_pending = false;		/* True when the user has signalled we should quit */
+
+/*
+ * ecm_ipv6_node_establish_and_ref()
+ *	Returns a reference to a node, possibly creating one if necessary.
+ *
+ * The given_node_addr will be used if provided.
+ *
+ * Returns NULL on failure.
+ */
+struct ecm_db_node_instance *ecm_ipv6_node_establish_and_ref(struct ecm_front_end_connection_instance *feci,
+							struct net_device *dev, ip_addr_t addr,
+							struct ecm_db_iface_instance *interface_list[], int32_t interface_list_first,
+							uint8_t *given_node_addr, struct sk_buff *skb)
+{
+	struct ecm_db_node_instance *ni;
+	struct ecm_db_node_instance *nni;
+	struct ecm_db_iface_instance *ii;
+	int i;
+	bool done;
+	uint8_t node_addr[ETH_ALEN];
+
+#if defined(ECM_INTERFACE_L2TPV2_ENABLE) || defined(ECM_INTERFACE_PPTP_ENABLE)
+	ip_addr_t remote_ip, local_ip;
+#endif
+
+#if defined(ECM_INTERFACE_VXLAN_ENABLE) || defined(ECM_INTERFACE_L2TPV2_ENABLE) || defined(ECM_INTERFACE_PPTP_ENABLE)
+	struct net_device *local_dev;
+#endif
+
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+	struct inet6_dev *ip6_inetdev;
+#endif
+
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+	struct net_device *out_dev;
+#endif
+
+#if defined(ECM_INTERFACE_GRE_TUN_ENABLE) || defined(ECM_XFRM_ENABLE)
+	struct net_device *in;
+#endif
+
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+	struct ip_tunnel *gre4_tunnel;
+	struct ip6_tnl *gre6_tunnel;
+	ip_addr_t local_gre_tun_ip;
+#endif
+
+#if defined(ECM_INTERFACE_L2TPV2_ENABLE) || defined(ECM_INTERFACE_MAP_T_ENABLE)
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+	struct ppp_channel *ppp_chan[1];
+	struct pppoe_opt addressing;
+	int px_proto;
+#endif
+#endif
+
+	DEBUG_INFO("%px: Establish node for " ECM_IP_ADDR_OCTAL_FMT "\n", feci, ECM_IP_ADDR_TO_OCTAL(addr));
+
+	/*
+	 * The node is the datalink address, typically a MAC address.
+	 * However the node address to use is not always obvious and depends on the interfaces involved.
+	 * For example if the interface is PPPoE then we use the MAC of the PPPoE server as we cannot use normal ARP resolution.
+	 * Not all hosts have a node address, where there is none, a suitable alternative should be located and is typically based on 'addr'
+	 * or some other datalink session information.
+	 * It should be, at a minimum, something that ties the host with the interface.
+	 *
+	 * Iterate from 'inner' to 'outer' interfaces - discover what the node is.
+	 */
+	memset(node_addr, 0, ETH_ALEN);
+	done = false;
+	if (given_node_addr) {
+		memcpy(node_addr, given_node_addr, ETH_ALEN);
+		done = true;
+		DEBUG_TRACE("%px: Using given node address: %pM\n", feci, node_addr);
+	}
+	for (i = ECM_DB_IFACE_HEIRARCHY_MAX - 1; (!done) && (i >= interface_list_first); i--) {
+		ecm_db_iface_type_t type;
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+		struct ecm_db_interface_info_pppoe pppoe_info;
+#endif
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+		struct ecm_db_interface_info_pppol2tpv2 pppol2tpv2_info;
+#endif
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+		struct ecm_db_interface_info_pptp pptp_info;
+#endif
+		type = ecm_db_iface_type_get(interface_list[i]);
+		DEBUG_INFO("%px: Lookup node address, interface @ %d is type: %d\n", feci, i, type);
+
+		switch (type) {
+
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * Node address is the address of the remote PPPoE server
+			 */
+			ecm_db_iface_pppoe_session_info_get(interface_list[i], &pppoe_info);
+			memcpy(node_addr, pppoe_info.remote_mac, ETH_ALEN);
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("%px: PPPoE interface unsupported\n", feci);
+			return NULL;
+#endif
+
+		case ECM_DB_IFACE_TYPE_SIT:
+		case ECM_DB_IFACE_TYPE_TUNIPIP6:
+			done = true;
+			break;
+
+		case ECM_DB_IFACE_TYPE_PPPOL2TPV2:
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+			ecm_db_iface_pppol2tpv2_session_info_get(interface_list[i], &pppol2tpv2_info);
+			ECM_HIN4_ADDR_TO_IP_ADDR(local_ip, pppol2tpv2_info.ip.saddr);
+			ECM_HIN4_ADDR_TO_IP_ADDR(remote_ip, pppol2tpv2_info.ip.daddr);
+
+			DEBUG_TRACE("%px: local=" ECM_IP_ADDR_OCTAL_FMT " remote=" ECM_IP_ADDR_OCTAL_FMT " addr=" ECM_IP_ADDR_OCTAL_FMT "\n", feci,
+			       ECM_IP_ADDR_TO_OCTAL(local_ip), ECM_IP_ADDR_TO_OCTAL(remote_ip), ECM_IP_ADDR_TO_OCTAL(addr));
+
+			local_dev = ecm_interface_dev_find_by_local_addr(local_ip);
+
+			if (!local_dev) {
+				DEBUG_WARN("%px: Failed to find local netdevice of l2tp tunnel for " ECM_IP_ADDR_OCTAL_FMT "\n", feci, ECM_IP_ADDR_TO_OCTAL(local_ip));
+				return NULL;
+			}
+
+			DEBUG_TRACE("%px: local_dev found is %s\n", feci, local_dev->name);
+
+			if (local_dev->type == ARPHRD_PPP) {
+#ifndef ECM_INTERFACE_PPPOE_ENABLE
+				DEBUG_TRACE("%px: l2tpv2 over pppoe unsupported\n", feci);
+				dev_put(local_dev);
+				return NULL;
+#else
+				if (ppp_hold_channels(local_dev, ppp_chan, 1) != 1) {
+					DEBUG_WARN("%px: l2tpv2 over netdevice %s unsupported; could not hold ppp channels\n", feci, local_dev->name);
+					dev_put(local_dev);
+					return NULL;
+				}
+
+				px_proto = ppp_channel_get_protocol(ppp_chan[0]);
+				if (px_proto != PX_PROTO_OE) {
+					DEBUG_WARN("%px: l2tpv2 over PPP protocol %d unsupported\n", feci, px_proto);
+					ppp_release_channels(ppp_chan, 1);
+					dev_put(local_dev);
+					return NULL;
+				}
+
+				if (pppoe_channel_addressing_get(ppp_chan[0], &addressing)) {
+					DEBUG_WARN("%px: failed to get PPPoE addressing info\n", feci);
+					ppp_release_channels(ppp_chan, 1);
+					dev_put(local_dev);
+					return NULL;
+				}
+
+				DEBUG_TRACE("%px: Obtained mac address for %s remote address " ECM_IP_ADDR_OCTAL_FMT "\n", feci, addressing.dev->name, ECM_IP_ADDR_TO_OCTAL(addr));
+				memcpy(node_addr, addressing.dev->dev_addr, ETH_ALEN);
+				dev_put(addressing.dev);
+				ppp_release_channels(ppp_chan, 1);
+				dev_put(local_dev);
+				done = true;
+				break;
+#endif
+			}
+
+			if (unlikely(!ecm_interface_mac_addr_get_no_route(local_dev, remote_ip, node_addr))) {
+				DEBUG_WARN("%px: Failed to obtain mac for host " ECM_IP_ADDR_OCTAL_FMT "\n", feci, ECM_IP_ADDR_TO_OCTAL(addr));
+				dev_put(local_dev);
+				return NULL;
+			}
+
+			dev_put(local_dev);
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("%px: PPPoL2TPV2 interface unsupported\n", feci);
+			return NULL;
+#endif
+		case ECM_DB_IFACE_TYPE_PPTP:
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+			ecm_db_iface_pptp_session_info_get(interface_list[i], &pptp_info);
+			ECM_HIN4_ADDR_TO_IP_ADDR(local_ip, pptp_info.src_ip);
+			ECM_HIN4_ADDR_TO_IP_ADDR(remote_ip, pptp_info.dst_ip);
+			DEBUG_TRACE("%px: local=" ECM_IP_ADDR_DOT_FMT " remote=" ECM_IP_ADDR_DOT_FMT " addr=" ECM_IP_ADDR_DOT_FMT "\n", feci,
+			       ECM_IP_ADDR_TO_DOT(local_ip), ECM_IP_ADDR_TO_DOT(remote_ip), ECM_IP_ADDR_TO_DOT(addr));
+
+			local_dev = ecm_interface_dev_find_by_local_addr(local_ip);
+
+			if (!local_dev) {
+				DEBUG_WARN("%px: Failed to find local netdevice of pptp tunnel for " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(local_ip));
+				return NULL;
+			}
+
+			DEBUG_TRACE("%px: local_dev found is %s\n", feci, local_dev->name);
+
+			if (ECM_IP_ADDR_MATCH(local_ip, addr)) {
+				if (unlikely(!ecm_interface_mac_addr_get_no_route(local_dev, local_ip, node_addr))) {
+					DEBUG_WARN("%px: failed to obtain node address for " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(local_ip));
+					dev_put(local_dev);
+					return NULL;
+				}
+
+			} else {
+				if (unlikely(!ecm_interface_mac_addr_get_no_route(local_dev, remote_ip, node_addr))) {
+					ip_addr_t gw_addr = ECM_IP_ADDR_NULL;
+
+					if (!ecm_interface_find_gateway(remote_ip, gw_addr)) {
+						DEBUG_WARN("%px: failed to obtain Gateway address for host " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(remote_ip));
+						dev_put(local_dev);
+						return NULL;
+					}
+
+					if (ECM_IP_ADDR_MATCH(gw_addr, remote_ip)) {
+						DEBUG_TRACE("%px: host ip address match with gw address " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(remote_ip));
+						dev_put(local_dev);
+						return NULL;
+					}
+
+					if (!ecm_interface_mac_addr_get_no_route(local_dev, gw_addr, node_addr)) {
+						DEBUG_WARN("%px: failed to obtain node address for host " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(gw_addr));
+						dev_put(local_dev);
+						return NULL;
+					}
+				}
+			}
+
+			dev_put(local_dev);
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("%px: PPTP interface unsupported\n", feci);
+			return NULL;
+#endif
+		case ECM_DB_IFACE_TYPE_MAP_T:
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+			ip6_inetdev = ip6_dst_idev(skb_dst(skb));
+			if (!ip6_inetdev) {
+				DEBUG_WARN("%px: Failed to obtain mac address for MAP-T address " ECM_IP_ADDR_OCTAL_FMT "\n", feci, ECM_IP_ADDR_TO_OCTAL(addr));
+				return NULL;
+			}
+
+			if (ip6_inetdev->dev->type != ARPHRD_PPP) {
+				DEBUG_TRACE("%px: obtained mac address for %s MAP-T address " ECM_IP_ADDR_OCTAL_FMT "\n", feci, ip6_inetdev->dev->name, ECM_IP_ADDR_TO_OCTAL(addr));
+				memcpy(node_addr, ip6_inetdev->dev->dev_addr, ETH_ALEN);
+				done = true;
+				break;
+			}
+
+#ifndef ECM_INTERFACE_PPPOE_ENABLE
+			DEBUG_TRACE("%px: MAP-T over netdevice %s unsupported\n", feci, ip6_inetdev->dev->name);
+			return NULL;
+#else
+			if (ppp_hold_channels(ip6_inetdev->dev, ppp_chan, 1) != 1) {
+				DEBUG_WARN("%px: MAP-T over netdevice %s unsupported; could not hold ppp channels\n", feci, ip6_inetdev->dev->name);
+				return NULL;
+			}
+
+			px_proto = ppp_channel_get_protocol(ppp_chan[0]);
+			if (px_proto != PX_PROTO_OE) {
+				DEBUG_WARN("%px: MAP-T over PPP protocol %d unsupported\n", feci, px_proto);
+				ppp_release_channels(ppp_chan, 1);
+				return NULL;
+			}
+
+			if (pppoe_channel_addressing_get(ppp_chan[0], &addressing)) {
+				DEBUG_WARN("%px: failed to get PPPoE addressing info\n", feci);
+				ppp_release_channels(ppp_chan, 1);
+				return NULL;
+			}
+
+			DEBUG_TRACE("%px: Obtained mac address for %s MAP-T address " ECM_IP_ADDR_OCTAL_FMT "\n", feci, addressing.dev->name, ECM_IP_ADDR_TO_OCTAL(addr));
+			memcpy(node_addr, addressing.dev->dev_addr, ETH_ALEN);
+			dev_put(addressing.dev);
+			ppp_release_channels(ppp_chan, 1);
+			done = true;
+			break;
+#endif
+
+#else
+			DEBUG_TRACE("%px: MAP-T interface unsupported\n", feci);
+			return NULL;
+#endif
+
+		case ECM_DB_IFACE_TYPE_GRE_TUN:
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+			in = dev_get_by_index(&init_net, skb->skb_iif);
+			if (!in) {
+				DEBUG_WARN("%px: failed to obtain node address for host " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(addr));
+				return NULL;
+			}
+
+			switch(in->type) {
+			case ARPHRD_IPGRE:
+				gre4_tunnel = netdev_priv(in);
+				if (!gre4_tunnel) {
+					dev_put(in);
+					DEBUG_WARN("%px: failed to obtain node address for host. GREv4 tunnel not initialized\n", feci);
+					return NULL;
+				}
+				ECM_NIN4_ADDR_TO_IP_ADDR(local_gre_tun_ip, gre4_tunnel->parms.iph.saddr);
+				dev_put(in);
+				in = ecm_interface_dev_find_by_local_addr(local_gre_tun_ip);
+				if (!in) {
+					DEBUG_WARN("%px: failed to obtain node address for host " ECM_IP_ADDR_DOT_FMT "\n", feci, ECM_IP_ADDR_TO_DOT(local_gre_tun_ip));
+					return NULL;
+				}
+				break;
+
+			case ARPHRD_IP6GRE:
+				gre6_tunnel = netdev_priv(in);
+				if (!gre6_tunnel) {
+					dev_put(in);
+					DEBUG_WARN("%px: failed to obtain node address for host. GREv4 tunnel not initialized\n", feci);
+					return NULL;
+				}
+				ECM_NIN6_ADDR_TO_IP_ADDR(local_gre_tun_ip, gre6_tunnel->parms.laddr);
+				dev_put(in);
+				in = ecm_interface_dev_find_by_local_addr(local_gre_tun_ip);
+				if (!in) {
+					DEBUG_WARN("%px: failed to obtain node address for host " ECM_IP_ADDR_OCTAL_FMT "\n", feci, ECM_IP_ADDR_TO_OCTAL(local_gre_tun_ip));
+					return NULL;
+				}
+				break;
+
+			default:
+				DEBUG_TRACE("%px: establish node with physical netdev: %s\n", feci, in->name);
+			}
+			memcpy(node_addr, in->dev_addr, ETH_ALEN);
+			dev_put(in);
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("%px: GRE interface unsupported\n", feci);
+			return NULL;
+#endif
+
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			/*
+			 * VLAN handled same along with bridge etc.
+			 */
+#else
+			DEBUG_TRACE("%px: VLAN interface unsupported\n", feci);
+			return NULL;
+#endif
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_XFRM_ENABLE
+			if (dst_xfrm(skb_dst(skb))) {
+				ether_addr_copy(node_addr, dev->dev_addr);
+				done = true;
+				break;
+			}
+
+			if (secpath_exists(skb)) {
+				in = dev_get_by_index(&init_net, skb->skb_iif);
+				if (!in) {
+					DEBUG_WARN("%px: failed to obtain node address for host " ECM_IP_ADDR_OCTAL_FMT "\n", feci, ECM_IP_ADDR_TO_OCTAL(addr));
+					return NULL;
+				}
+
+				ether_addr_copy(node_addr, in->dev_addr);
+				dev_put(in);
+				done = true;
+				break;
+			}
+#if __has_attribute(__fallthrough__)
+			__attribute__((__fallthrough__));
+#endif
+#endif
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+		case ECM_DB_IFACE_TYPE_LAG:
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#endif
+			if (!ecm_interface_mac_addr_get_no_route(dev, addr, node_addr)) {
+				ip_addr_t gw_addr = ECM_IP_ADDR_NULL;
+
+				/*
+				 * Try one more time with gateway ip address if it exists.
+				 */
+				if (!ecm_interface_find_gateway(addr, gw_addr)) {
+					DEBUG_WARN("%px: Node establish failed, there is no gateway address for 2nd mac lookup try\n", feci);
+					return NULL;
+				}
+
+				/*
+				 * The found gateway address can be all zeros,
+				 * so in this case use the host address.
+				 */
+				if (ECM_IP_ADDR_IS_NULL(gw_addr)) {
+					DEBUG_TRACE("%px: GW address is found as zeros, so use host IP\n", feci);
+					ECM_IP_ADDR_COPY(gw_addr, addr);
+				} else {
+					DEBUG_TRACE("%px: Have a gw address " ECM_IP_ADDR_OCTAL_FMT "\n", feci, ECM_IP_ADDR_TO_OCTAL(gw_addr));
+				}
+
+				if (ecm_interface_mac_addr_get_no_route(dev, gw_addr, node_addr)) {
+					DEBUG_TRACE("%px: Found the mac address for gateway\n", feci);
+					goto done;
+				}
+
+				if (ecm_front_end_is_bridge_port(dev)) {
+					struct net_device *master;
+					master = ecm_interface_get_and_hold_dev_master(dev);
+					DEBUG_ASSERT(master, "%px: Expected a master\n", feci);
+					ecm_interface_send_neighbour_solicitation(master, gw_addr);
+					dev_put(master);
+				} else {
+					ecm_interface_send_neighbour_solicitation(dev, gw_addr);
+				}
+
+				DEBUG_WARN("%px: Failed to obtain mac for host " ECM_IP_ADDR_OCTAL_FMT " gw: " ECM_IP_ADDR_OCTAL_FMT "\n", feci,
+					    ECM_IP_ADDR_TO_OCTAL(addr), ECM_IP_ADDR_TO_OCTAL(gw_addr));
+				return NULL;
+			}
+done:
+			if (is_multicast_ether_addr(node_addr)) {
+				DEBUG_TRACE("%px: multicast node address for host " ECM_IP_ADDR_OCTAL_FMT ", node_addr: %pM\n", feci, ECM_IP_ADDR_TO_OCTAL(addr), node_addr);
+				return NULL;
+			}
+
+			done = true;
+			break;
+		case ECM_DB_IFACE_TYPE_RAWIP:
+#ifdef ECM_INTERFACE_RAWIP_ENABLE
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("%px: RAWIP interface unsupported\n", feci);
+			return NULL;
+#endif
+		case ECM_DB_IFACE_TYPE_OVPN:
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+			out_dev = skb_dst(skb)->dev;
+
+			/*
+			 * There is no MAC address for TUN/TAP device.
+			 * Return if skb->dst is TUN/TAP device.
+			 */
+			if (!out_dev || out_dev->priv_flags_ext & IFF_EXT_TUN_TAP) {
+				DEBUG_WARN("%px: failed to update node_addr dev = %s, out_dev = %s, node address for host " ECM_IP_ADDR_OCTAL_FMT "\n", feci,
+						dev->name, out_dev->name, ECM_IP_ADDR_TO_OCTAL(addr));
+				return NULL;
+			}
+			memcpy(node_addr, out_dev->dev_addr, ETH_ALEN);
+
+			DEBUG_TRACE("%px: dev = %s, out_dev = %s, node address for host " ECM_IP_ADDR_OCTAL_FMT ", node_addr: %pM\n", feci,
+				dev->name, out_dev->name, ECM_IP_ADDR_TO_OCTAL(addr), node_addr);
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("%px: OVPN interface unsupported\n", feci);
+			return NULL;
+#endif
+		case ECM_DB_IFACE_TYPE_VXLAN:
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+			local_dev = ecm_interface_dev_find_by_local_addr(addr);
+			if (!local_dev) {
+				DEBUG_WARN("%px: Failed to find local netdevice of VxLAN tunnel for " ECM_IP_ADDR_OCTAL_FMT "\n",
+						feci, ECM_IP_ADDR_TO_OCTAL(addr));
+				return NULL;
+			}
+
+			if (!ecm_interface_mac_addr_get_no_route(local_dev, addr, node_addr)) {
+				DEBUG_WARN("%px: Couldn't find mac address for local dev\n", feci);
+				dev_put(local_dev);
+				return NULL;
+			}
+			DEBUG_TRACE("%px: Found the mac address for local dev\n", feci);
+			dev_put(local_dev);
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("%px: VXLAN interface unsupported\n", feci);
+			return NULL;
+#endif
+		default:
+			/*
+			 * Don't know how to handle these.
+			 * Just copy some part of the address for now, but keep iterating the interface list
+			 * in the hope something recognisable will be seen!
+			 * GGG TODO We really need to roll out support for all interface types we can deal with ASAP :-(
+			 */
+			memcpy(node_addr, (uint8_t *)addr, ETH_ALEN);
+		}
+	}
+	if (!done) {
+		DEBUG_WARN("%px: Failed to establish node for " ECM_IP_ADDR_OCTAL_FMT "\n", feci, ECM_IP_ADDR_TO_OCTAL(addr));
+		return NULL;
+	}
+
+	/*
+	 * Establish iface
+	 */
+	ii = ecm_interface_establish_and_ref(feci, dev, skb);
+	if (!ii) {
+		DEBUG_WARN("%px: Failed to establish iface\n", feci);
+		return NULL;
+	}
+
+	/*
+	 * Locate the node
+	 */
+	ni = ecm_db_node_find_and_ref(node_addr, ii);
+	if (ni) {
+		DEBUG_TRACE("%px: node established %px\n", feci, ni);
+		ecm_db_iface_deref(ii);
+		return ni;
+	}
+
+	/*
+	 * No node - create one
+	 */
+	nni = ecm_db_node_alloc();
+	if (!nni) {
+		DEBUG_WARN("%px: Failed to establish node\n", feci);
+		ecm_db_iface_deref(ii);
+		return NULL;
+	}
+
+	/*
+	 * Add node into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_ipv6_lock);
+	ni = ecm_db_node_find_and_ref(node_addr, ii);
+	if (ni) {
+		spin_unlock_bh(&ecm_ipv6_lock);
+		ecm_db_node_deref(nni);
+		ecm_db_iface_deref(ii);
+		return ni;
+	}
+
+	ecm_db_node_add(nni, ii, node_addr, NULL, nni);
+	spin_unlock_bh(&ecm_ipv6_lock);
+
+	/*
+	 * Don't need iface instance now
+	 */
+	ecm_db_iface_deref(ii);
+
+	DEBUG_TRACE("%px: node %px established\n", feci, nni);
+	return nni;
+}
+
+/*
+ * ecm_ipv6_host_establish_and_ref()
+ *	Returns a reference to a host, possibly creating one if necessary.
+ *
+ * Returns NULL on failure.
+ */
+struct ecm_db_host_instance *ecm_ipv6_host_establish_and_ref(ip_addr_t addr)
+{
+	struct ecm_db_host_instance *hi;
+	struct ecm_db_host_instance *nhi;
+
+	DEBUG_INFO("Establish host for " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr));
+
+	/*
+	 * Locate the host
+	 */
+	hi = ecm_db_host_find_and_ref(addr);
+	if (hi) {
+		DEBUG_TRACE("%px: host established\n", hi);
+		return hi;
+	}
+
+	/*
+	 * No host - create one
+	 */
+	nhi = ecm_db_host_alloc();
+	if (!nhi) {
+		DEBUG_WARN("Failed to establish host\n");
+		return NULL;
+	}
+
+	/*
+	 * Add host into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_ipv6_lock);
+	hi = ecm_db_host_find_and_ref(addr);
+	if (hi) {
+		spin_unlock_bh(&ecm_ipv6_lock);
+		ecm_db_host_deref(nhi);
+		return hi;
+	}
+
+	ecm_db_host_add(nhi, addr, true, NULL, nhi);
+
+	spin_unlock_bh(&ecm_ipv6_lock);
+
+	DEBUG_TRACE("%px: host established\n", nhi);
+	return nhi;
+}
+
+/*
+ * ecm_ipv6_mapping_establish_and_ref()
+ *	Returns a reference to a mapping, possibly creating one if necessary.
+ *
+ * Returns NULL on failure.
+ */
+struct ecm_db_mapping_instance *ecm_ipv6_mapping_establish_and_ref(ip_addr_t addr, int port)
+{
+	struct ecm_db_mapping_instance *mi;
+	struct ecm_db_mapping_instance *nmi;
+	struct ecm_db_host_instance *hi;
+
+	DEBUG_INFO("Establish mapping for " ECM_IP_ADDR_OCTAL_FMT ":%u\n", ECM_IP_ADDR_TO_OCTAL(addr), port);
+
+	/*
+	 * Locate the mapping
+	 */
+	mi = ecm_db_mapping_find_and_ref(addr, port);
+	if (mi) {
+		DEBUG_TRACE("%px: mapping established\n", mi);
+		return mi;
+	}
+
+	/*
+	 * No mapping - establish host existence
+	 */
+	hi = ecm_ipv6_host_establish_and_ref(addr);
+	if (!hi) {
+		DEBUG_WARN("Failed to establish host\n");
+		return NULL;
+	}
+
+	/*
+	 * Create mapping instance
+	 */
+	nmi = ecm_db_mapping_alloc();
+	if (!nmi) {
+		ecm_db_host_deref(hi);
+		DEBUG_WARN("Failed to establish mapping\n");
+		return NULL;
+	}
+
+	/*
+	 * Add mapping into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_ipv6_lock);
+	mi = ecm_db_mapping_find_and_ref(addr, port);
+	if (mi) {
+		spin_unlock_bh(&ecm_ipv6_lock);
+		ecm_db_mapping_deref(nmi);
+		ecm_db_host_deref(hi);
+		return mi;
+	}
+
+	ecm_db_mapping_add(nmi, hi, port, NULL, nmi);
+
+	spin_unlock_bh(&ecm_ipv6_lock);
+
+	/*
+	 * Don't need the host instance now - the mapping maintains a reference to it now.
+	 */
+	ecm_db_host_deref(hi);
+
+	/*
+	 * Return the mapping instance
+	 */
+	DEBUG_INFO("%px: mapping established\n", nmi);
+	return nmi;
+}
+
+/*
+ * ecm_ipv6_connection_regenerate()
+ *	Re-generate a connection.
+ *
+ * Re-generating a connection involves re-evaluating the interface lists in case interface heirarchies have changed.
+ * It also involves the possible triggering of classifier re-evaluation but only if all currently assigned
+ * classifiers permit this operation.
+ */
+void ecm_ipv6_connection_regenerate(struct ecm_db_connection_instance *ci, ecm_tracker_sender_type_t sender,
+							struct net_device *out_dev, struct net_device *in_dev, __be16 *layer4hdr,
+							struct sk_buff *skb)
+{
+	int i;
+	bool reclassify_allowed;
+	int32_t to_list_first;
+	struct ecm_db_iface_instance *to_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+	int32_t from_list_first;
+	struct ecm_db_iface_instance *from_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+	ip_addr_t ip_src_addr;
+	ip_addr_t ip_dest_addr;
+	int protocol;
+	bool is_routed;
+	uint8_t src_node_addr[ETH_ALEN];
+	uint8_t dest_node_addr[ETH_ALEN];
+	int assignment_count;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_front_end_interface_construct_instance efeici;
+	ecm_db_direction_t ecm_dir;
+	struct ecm_front_end_ovs_params *from_ovs_params = NULL;
+	struct ecm_front_end_ovs_params *to_ovs_params = NULL;
+
+	DEBUG_INFO("%px: re-gen needed\n", ci);
+
+	/*
+	 * We may need to swap the devices around depending on who the sender of the packet that triggered the re-gen is
+	 */
+	if (sender == ECM_TRACKER_SENDER_TYPE_DEST) {
+		struct net_device *tmp_dev;
+
+		/*
+		 * This is a packet sent by the destination of the connection, i.e. it is a packet issued by the 'from' side of the connection.
+		 */
+		DEBUG_TRACE("%px: Re-gen swap devs\n", ci);
+		tmp_dev = out_dev;
+		out_dev = in_dev;
+		in_dev = tmp_dev;
+	}
+
+	/*
+	 * Update the interface lists - these may have changed, e.g. LAG path change etc.
+	 * NOTE: We never have to change the usual mapping->host->node_iface arrangements for each side of the connection (to/from sides)
+	 * This is because if these interfaces change then the connection is dead anyway.
+	 * But a LAG slave might change the heirarchy the connection is using but the LAG master is still sane.
+	 * If any of the new interface heirarchies cannot be created then simply set empty-lists as this will deny
+	 * acceleration and ensure that a bad rule cannot be created.
+	 * IMPORTANT: The 'sender' defines who has sent the packet that triggered this re-generation
+	 */
+	protocol = ecm_db_connection_protocol_get(ci);
+
+	is_routed = ecm_db_connection_is_routed_get(ci);
+	ecm_dir = ecm_db_connection_direction_get(ci);
+
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, ip_src_addr);
+
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, ip_dest_addr);
+
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_node_addr);
+
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, dest_node_addr);
+
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+	if (!ecm_front_end_ipv6_interface_construct_set_and_hold(skb, sender, ecm_dir, is_routed,
+							in_dev, out_dev,
+							ip_src_addr, ip_dest_addr,
+							&efeici)) {
+
+		DEBUG_WARN("ECM front end ipv6 interface construct set failed for regeneration\n");
+		goto ecm_ipv6_retry_regen;
+	}
+
+	if ((protocol == IPPROTO_TCP) || (protocol == IPPROTO_UDP)) {
+		int src_port, dest_port;
+		struct ecm_front_end_ovs_params ovs_params[ECM_DB_OBJ_DIR_MAX];
+
+		src_port = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+		dest_port = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+		/*
+		 * For IPv6 there is no NAT address or port numbers,
+		 * so we use the same IP address and port numbers from the
+		 * from and to host for those fields.
+		 */
+		ecm_front_end_fill_ovs_params(ovs_params,
+				      ip_src_addr, ip_src_addr,
+				      ip_dest_addr, ip_dest_addr,
+				      src_port, src_port,
+				      dest_port, dest_port, ecm_dir);
+
+		from_ovs_params = &ovs_params[ECM_DB_OBJ_DIR_FROM];
+		to_ovs_params = &ovs_params[ECM_DB_OBJ_DIR_TO];
+	}
+
+	DEBUG_TRACE("%px: Update the 'from' interface heirarchy list\n", ci);
+	from_list_first = ecm_interface_heirarchy_construct(feci, from_list, efeici.from_dev, efeici.from_other_dev, ip_dest_addr, efeici.from_mac_lookup_ip_addr, ip_src_addr, 6, protocol, in_dev, is_routed, in_dev, src_node_addr, dest_node_addr, layer4hdr, skb, from_ovs_params);
+	if (from_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		ecm_front_end_ipv6_interface_construct_netdev_put(&efeici);
+		goto ecm_ipv6_retry_regen;
+	}
+
+	ecm_db_connection_interfaces_reset(ci, from_list, from_list_first, ECM_DB_OBJ_DIR_FROM);
+	ecm_db_connection_interfaces_deref(from_list, from_list_first);
+
+	DEBUG_TRACE("%px: Update the 'to' interface heirarchy list\n", ci);
+	to_list_first = ecm_interface_heirarchy_construct(feci, to_list, efeici.to_dev, efeici.to_other_dev, ip_src_addr, efeici.to_mac_lookup_ip_addr, ip_dest_addr, 6, protocol, out_dev, is_routed, in_dev, dest_node_addr, src_node_addr, layer4hdr, skb, to_ovs_params);
+	if (to_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		ecm_front_end_ipv6_interface_construct_netdev_put(&efeici);
+		goto ecm_ipv6_retry_regen;
+	}
+
+	ecm_front_end_ipv6_interface_construct_netdev_put(&efeici);
+
+	feci->deref(feci);
+	ecm_db_connection_interfaces_reset(ci, to_list, to_list_first, ECM_DB_OBJ_DIR_TO);
+	ecm_db_connection_interfaces_deref(to_list, to_list_first);
+
+	/*
+	 * Get list of assigned classifiers to reclassify.
+	 * Remember: This also includes our default classifier too.
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+
+	/*
+	 * All of the assigned classifiers must permit reclassification.
+	 */
+	reclassify_allowed = true;
+	for (i = 0; i < assignment_count; ++i) {
+		DEBUG_TRACE("%px: Calling to reclassify: %px, type: %d\n", ci, assignments[i], assignments[i]->type_get(assignments[i]));
+		if (!assignments[i]->reclassify_allowed(assignments[i])) {
+			DEBUG_TRACE("%px: reclassify denied: %px, by type: %d\n", ci, assignments[i], assignments[i]->type_get(assignments[i]));
+			reclassify_allowed = false;
+			break;
+		}
+	}
+
+	if (!reclassify_allowed) {
+		/*
+		 * Regeneration came to a successful conclusion even though reclassification was denied
+		 */
+		DEBUG_WARN("%px: re-classify denied\n", ci);
+		goto ecm_ipv6_regen_done;
+	}
+
+	/*
+	 * Reclassify
+	 */
+	DEBUG_INFO("%px: reclassify\n", ci);
+	if (!ecm_classifier_reclassify(ci, assignment_count, assignments)) {
+		/*
+		 * We could not set up the classifiers to reclassify, it is safer to fail out and try again next time
+		 */
+		DEBUG_WARN("%px: Regeneration: reclassify failed\n", ci);
+		goto ecm_ipv6_regen_done;
+	}
+	DEBUG_INFO("%px: reclassify success\n", ci);
+
+ecm_ipv6_regen_done:
+
+	/*
+	 * Release the assignments
+	 */
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Re-generation of state is successful.
+	 */
+	ecm_db_connection_regeneration_completed(ci);
+
+	return;
+
+ecm_ipv6_retry_regen:
+	feci->deref(feci);
+	ecm_db_connection_regeneration_failed(ci);
+	return;
+}
+
+/*
+ * ecm_ipv6_ip_process()
+ *	Process IP datagram skb
+ */
+unsigned int ecm_ipv6_ip_process(struct net_device *out_dev, struct net_device *in_dev,
+							uint8_t *src_node_addr, uint8_t *dest_node_addr,
+							bool can_accel, bool is_routed, bool is_l2_encap,
+							struct sk_buff *skb, uint16_t l2_encap_proto)
+{
+	struct ecm_tracker_ip_header ip_hdr;
+	struct nf_conn *ct;
+	enum ip_conntrack_info ctinfo;
+	struct nf_conntrack_tuple orig_tuple;
+	struct nf_conntrack_tuple reply_tuple;
+	ecm_tracker_sender_type_t sender;
+	ecm_db_direction_t ecm_dir = ECM_DB_DIRECTION_EGRESS_NAT;
+	ip_addr_t ip_src_addr;
+	ip_addr_t ip_dest_addr;
+	uint8_t protonum;
+
+	/*
+	 * Obtain the IP header from the skb
+	 */
+	if (!ecm_tracker_ip_check_header_and_read(&ip_hdr, skb)) {
+		DEBUG_WARN("Invalid ip header in skb %px\n", skb);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Process only IPv6 packets
+	 */
+	if (ip_hdr.is_v4) {
+		DEBUG_TRACE("Not an IPv6 packet, skb %px\n", skb);
+		return NF_ACCEPT;
+	}
+
+	if (ip_hdr.fragmented) {
+		DEBUG_TRACE("skb %px is fragmented\n", skb);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Extract information, if we have conntrack then use that info as far as we can.
+	 */
+	ct = nf_ct_get(skb, &ctinfo);
+	if (unlikely(!ct)) {
+		DEBUG_TRACE("%px: no ct\n", skb);
+		ECM_IP_ADDR_TO_NIN6_ADDR(orig_tuple.src.u3.in6, ip_hdr.src_addr);
+		ECM_IP_ADDR_TO_NIN6_ADDR(orig_tuple.dst.u3.in6, ip_hdr.dest_addr);
+		orig_tuple.dst.protonum = ip_hdr.protocol;
+		ECM_IP_ADDR_TO_NIN6_ADDR(reply_tuple.src.u3.in6, ip_hdr.dest_addr);
+		ECM_IP_ADDR_TO_NIN6_ADDR(reply_tuple.dst.u3.in6, ip_hdr.src_addr);
+		sender = ECM_TRACKER_SENDER_TYPE_SRC;
+	} else {
+		/*
+		 * Do not process the packet, if the conntrack is in dying state.
+		 */
+		if (unlikely(test_bit(IPS_DYING_BIT, &ct->status))) {
+			DEBUG_WARN("%px: ct: %px is in dying state\n", skb, ct);
+			return NF_ACCEPT;
+		}
+
+		/*
+		 * Fake untracked conntrack objects were removed on 4.12 kernel version
+		 * and onwards.
+		 * So, for the newer kernels, instead of comparing the ct with the percpu
+		 * fake conntrack, we can check the ct status.
+		 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
+		if (unlikely(ct == nf_ct_untracked_get())) {
+#else
+		if (unlikely(ctinfo == IP_CT_UNTRACKED)) {
+#endif
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+			/*
+			 * If the conntrack connection is set as untracked,
+			 * ECM will accept and process only VxLAN outer flows,
+			 * otherwise such flows will not be processed by ECM.
+			 *
+			 * E.g. In the following network arramgement,
+			 * Eth1 ---> Bridge ---> VxLAN0(Bridge Port) ---> Eth0(WAN)
+			 * The packets from VxLAN0 to Eth0 will be routed.
+			 *
+			 * netif_is_vxlan API is used to identify the VxLAN device &
+			 * is_routed flag is used to identify the outer flow.
+			 */
+			if (is_routed && netif_is_vxlan(in_dev)) {
+				DEBUG_TRACE("%px: Untracked CT for VxLAN\n", skb);
+				ECM_IP_ADDR_TO_NIN6_ADDR(orig_tuple.src.u3.in6, ip_hdr.src_addr);
+				ECM_IP_ADDR_TO_NIN6_ADDR(orig_tuple.dst.u3.in6, ip_hdr.dest_addr);
+				orig_tuple.dst.protonum = ip_hdr.protocol;
+				ECM_IP_ADDR_TO_NIN6_ADDR(reply_tuple.src.u3.in6, ip_hdr.dest_addr);
+				ECM_IP_ADDR_TO_NIN6_ADDR(reply_tuple.dst.u3.in6, ip_hdr.src_addr);
+				sender = ECM_TRACKER_SENDER_TYPE_SRC;
+				ct = NULL;
+				goto vxlan_done;
+			}
+#endif
+			DEBUG_TRACE("%px: ct: untracked\n", skb);
+			return NF_ACCEPT;
+		}
+
+		/*
+		 * If the conntrack connection is using a helper (i.e. Application Layer Gateway)
+		 * then acceleration is denied (connection needs assistance from HLOS to function)
+		 */
+		if (nfct_help(ct)) {
+			DEBUG_TRACE("%px: Connection has helper\n", ct);
+			can_accel = false;
+		}
+
+		/*
+		 * Extract conntrack connection information
+		 */
+		DEBUG_TRACE("%px: ct: %px, ctinfo: %x\n", skb, ct, ctinfo);
+		orig_tuple = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple;
+		reply_tuple = ct->tuplehash[IP_CT_DIR_REPLY].tuple;
+		if (IP_CT_DIR_ORIGINAL == CTINFO2DIR(ctinfo)) {
+			sender = ECM_TRACKER_SENDER_TYPE_SRC;
+		} else {
+			sender = ECM_TRACKER_SENDER_TYPE_DEST;
+		}
+
+		/*
+		 * Is this a related connection?
+		 */
+		if ((ctinfo == IP_CT_RELATED) || (ctinfo == IP_CT_RELATED_REPLY)) {
+			/*
+			 * ct is related to the packet at hand.
+			 * We can use the IP src/dest information and the direction information.
+			 * We cannot use the protocol information from the ct (typically the packet at hand is ICMP error that is related to the ct we have here).
+			 */
+			orig_tuple.dst.protonum = ip_hdr.protocol;
+			DEBUG_TRACE("%px: related ct, actual protocol: %u\n", skb, orig_tuple.dst.protonum);
+		}
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+vxlan_done:
+		;
+#endif
+	}
+
+	/*
+	 * Check if we can accelerate the GRE protocol.
+	 */
+	if (ip_hdr.protocol == IPPROTO_GRE) {
+		if (!ecm_front_end_gre_proto_is_accel_allowed(in_dev, out_dev, skb, &orig_tuple, 6)) {
+			DEBUG_WARN("%px: GRE protocol is not allowed\n", skb);
+			return NF_ACCEPT;
+		}
+	}
+
+	/*
+	 * Check for a multicast Destination address here.
+	 */
+	ECM_NIN6_ADDR_TO_IP_ADDR(ip_dest_addr, orig_tuple.dst.u3.in6);
+	if (ecm_ip_addr_is_multicast(ip_dest_addr)) {
+		DEBUG_TRACE("skb %px multicast daddr " ECM_IP_ADDR_OCTAL_FMT "\n", skb, ECM_IP_ADDR_TO_OCTAL(ip_dest_addr));
+#ifdef ECM_MULTICAST_ENABLE
+		if (unlikely(ecm_front_end_ipv6_mc_stopped)) {
+			DEBUG_TRACE("%px: Multicast disabled by ecm_front_end_ipv6_mc_stopped = %d\n", skb, ecm_front_end_ipv6_mc_stopped);
+			return NF_ACCEPT;
+		}
+
+		if (unlikely(!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_MULTICAST))) {
+			DEBUG_TRACE("%px: Multicast ipv6 acceleration is not supported on selected frontend\n", skb);
+			return NF_ACCEPT;
+		}
+
+		return ecm_multicast_ipv6_connection_process(out_dev, in_dev, src_node_addr, dest_node_addr,
+				can_accel, is_routed, skb, &ip_hdr, ct, sender,
+				&orig_tuple, &reply_tuple);
+#else
+		return NF_ACCEPT;
+#endif
+	}
+
+	/*
+	 * Work out if this packet involves routing or not.
+	 */
+	if (is_routed) {
+		/*
+		 * Non-NAT only supported for IPv6
+		 */
+		ecm_dir = ECM_DB_DIRECTION_NON_NAT;
+	} else {
+		/*
+		 * Bridged
+		 */
+		ecm_dir = ECM_DB_DIRECTION_BRIDGED;
+	}
+
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		if (ecm_dir == ECM_DB_DIRECTION_NON_NAT) {
+			ECM_NIN6_ADDR_TO_IP_ADDR(ip_src_addr, orig_tuple.src.u3.in6);
+			ECM_NIN6_ADDR_TO_IP_ADDR(ip_dest_addr, orig_tuple.dst.u3.in6);
+
+			src_node_addr = NULL;
+		} else if (ecm_dir == ECM_DB_DIRECTION_BRIDGED) {
+			ECM_NIN6_ADDR_TO_IP_ADDR(ip_src_addr, orig_tuple.src.u3.in6);
+			ECM_NIN6_ADDR_TO_IP_ADDR(ip_dest_addr, orig_tuple.dst.u3.in6);
+		} else {
+			DEBUG_ASSERT(false, "Unhandled ecm_dir: %d\n", ecm_dir);
+		}
+	} else {
+		if (ecm_dir == ECM_DB_DIRECTION_NON_NAT) {
+			ECM_NIN6_ADDR_TO_IP_ADDR(ip_dest_addr, orig_tuple.src.u3.in6);
+			ECM_NIN6_ADDR_TO_IP_ADDR(ip_src_addr, orig_tuple.dst.u3.in6);
+
+			src_node_addr = NULL;
+		} else if (ecm_dir == ECM_DB_DIRECTION_BRIDGED) {
+			ECM_NIN6_ADDR_TO_IP_ADDR(ip_dest_addr, orig_tuple.src.u3.in6);
+			ECM_NIN6_ADDR_TO_IP_ADDR(ip_src_addr, orig_tuple.dst.u3.in6);
+		} else {
+			DEBUG_ASSERT(false, "Unhandled ecm_dir: %d\n", ecm_dir);
+		}
+	}
+
+	/*
+	 * If PPPoE bridged flows are to be handled with 3-tuple rule, set protocol to IPPROTO_RAW.
+	 */
+	protonum = orig_tuple.dst.protonum;
+#ifdef ECM_FRONT_END_NSS_ENABLE
+	if (unlikely(!is_routed && (l2_encap_proto == ETH_P_PPP_SES))) {
+		/*
+		 * Check if PPPoE bridge acceleration is 3-tuple based.
+		 */
+		if (nss_pppoe_get_br_accel_mode() == NSS_PPPOE_BR_ACCEL_MODE_EN_3T) {
+			DEBUG_TRACE("3-tuple acceleration is enabled for PPPoE bridged flows\n");
+			protonum = IPPROTO_RAW;
+		}
+	}
+#endif
+	DEBUG_TRACE("IP Packet src: " ECM_IP_ADDR_OCTAL_FMT "dst: " ECM_IP_ADDR_OCTAL_FMT " protocol: %u, sender: %d ecm_dir: %d\n",
+			ECM_IP_ADDR_TO_OCTAL(ip_src_addr),
+			ECM_IP_ADDR_TO_OCTAL(ip_dest_addr),
+			protonum, sender, ecm_dir);
+	/*
+	 * Non-unicast source or destination packets are ignored
+	 * NOTE: Only need to check the non-nat src/dest addresses here.
+	 */
+	if (unlikely(ecm_ip_addr_is_non_unicast(ip_dest_addr))) {
+		DEBUG_TRACE("skb %px non-unicast daddr " ECM_IP_ADDR_OCTAL_FMT "\n", skb, ECM_IP_ADDR_TO_OCTAL(ip_dest_addr));
+		return NF_ACCEPT;
+	}
+	if (unlikely(ecm_ip_addr_is_non_unicast(ip_src_addr))) {
+		DEBUG_TRACE("skb %px non-unicast saddr " ECM_IP_ADDR_OCTAL_FMT "\n", skb, ECM_IP_ADDR_TO_OCTAL(ip_src_addr));
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Process IP specific protocol
+	 * TCP and UDP are the most likliest protocols.
+	 */
+	if (likely(protonum == IPPROTO_TCP) || likely(protonum == IPPROTO_UDP)) {
+		return ecm_ported_ipv6_process(out_dev, in_dev,
+				src_node_addr,
+				dest_node_addr,
+				can_accel, is_routed, is_l2_encap, skb,
+				&ip_hdr,
+				ct, sender, ecm_dir,
+				&orig_tuple, &reply_tuple,
+				ip_src_addr, ip_dest_addr, l2_encap_proto);
+	}
+#ifdef ECM_NON_PORTED_SUPPORT_ENABLE
+	if (unlikely(!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_NON_PORTED))) {
+		DEBUG_TRACE("%px: Non-ported ipv6 acceleration is not supported on the selected frontend\n", skb);
+		return NF_ACCEPT;
+	}
+
+	return ecm_non_ported_ipv6_process(out_dev, in_dev,
+			src_node_addr,
+			dest_node_addr,
+			can_accel, is_routed, is_l2_encap, skb,
+			&ip_hdr,
+			ct, sender, ecm_dir,
+			&orig_tuple, &reply_tuple,
+			ip_src_addr, ip_dest_addr, l2_encap_proto);
+#else
+	return NF_ACCEPT;
+#endif
+}
+
+/*
+ * ecm_ipv6_post_routing_hook()
+ *	Called for IP packets that are going out to interfaces after IP routing stage.
+ */
+static unsigned int ecm_ipv6_post_routing_hook(void *priv,
+				struct sk_buff *skb,
+				const struct nf_hook_state *nhs)
+{
+	struct net_device *out = nhs->out;
+	struct net_device *in;
+	bool can_accel = true;
+	unsigned int result;
+
+	DEBUG_TRACE("%px: Routing: %s\n", out, out->name);
+
+	/*
+	 * If operations have stopped then do not process packets
+	 */
+	spin_lock_bh(&ecm_ipv6_lock);
+	if (unlikely(ecm_front_end_ipv6_stopped)) {
+		spin_unlock_bh(&ecm_ipv6_lock);
+		DEBUG_TRACE("Front end stopped\n");
+		return NF_ACCEPT;
+	}
+	spin_unlock_bh(&ecm_ipv6_lock);
+
+	/*
+	 * Don't process broadcast or multicast
+	 */
+	if (skb->pkt_type == PACKET_BROADCAST) {
+		DEBUG_TRACE("Broadcast, ignoring: %px\n", skb);
+		return NF_ACCEPT;
+	}
+
+#ifndef ECM_INTERFACE_PPTP_ENABLE
+	/*
+	 * skip pptp because we don't accelerate them
+	 */
+	if (ecm_interface_is_pptp(skb, out)) {
+		return NF_ACCEPT;
+	}
+#endif
+
+#ifndef ECM_INTERFACE_L2TPV2_ENABLE
+	/*
+	 * skip l2tpv2 because we don't accelerate them
+	 */
+	if (ecm_interface_is_l2tp_packet_by_version(skb, out, 2)) {
+		return NF_ACCEPT;
+	}
+#endif
+
+	/*
+	 * skip l2tpv3 because we don't accelerate them
+	 */
+	if (ecm_interface_is_l2tp_packet_by_version(skb, out, 3)) {
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Identify interface from where this packet came
+	 */
+	in = dev_get_by_index(&init_net, skb->skb_iif);
+	if (unlikely(!in)) {
+		/*
+		 * Locally sourced packets are not processed in ECM.
+		 */
+		return NF_ACCEPT;
+	}
+
+#ifndef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+	/*
+	 * skip OpenVSwitch flows because we don't accelerate them
+	 */
+	if (netif_is_ovs_master(out) || netif_is_ovs_master(in)) {
+		dev_put(in);
+		return NF_ACCEPT;
+	}
+#endif
+
+	DEBUG_TRACE("Post routing process skb %px, out: %px, in: %px\n", skb, out, in);
+	result = ecm_ipv6_ip_process((struct net_device *)out, in, NULL, NULL, can_accel, true, false, skb, 0);
+	dev_put(in);
+	return result;
+}
+
+/*
+ * ecm_ipv6_pppoe_bridge_process()
+ *	Called for PPPoE session packets that are going
+ *	out to one of the bridge physical interfaces.
+ */
+static unsigned int ecm_ipv6_pppoe_bridge_process(struct net_device *out,
+						     struct net_device *in,
+						     struct ethhdr *skb_eth_hdr,
+						     bool can_accel,
+						     struct sk_buff *skb)
+{
+	struct ecm_tracker_ip_header ip_hdr;
+	unsigned int result = NF_ACCEPT;
+	struct pppoe_hdr *ph = pppoe_hdr(skb);
+	uint16_t ppp_proto = *(uint16_t *)ph->tag;
+	uint32_t encap_header_len = 0;
+
+	ppp_proto = ntohs(ppp_proto);
+	if (ppp_proto != PPP_IPV6) {
+		return NF_ACCEPT;
+	}
+
+	encap_header_len = ecm_front_end_l2_encap_header_len(ntohs(skb->protocol));
+	ecm_front_end_pull_l2_encap_header(skb, encap_header_len);
+	skb->protocol = htons(ETH_P_IPV6);
+
+	if (!ecm_tracker_ip_check_header_and_read(&ip_hdr, skb)) {
+		DEBUG_WARN("Invalid ip header in skb %px\n", skb);
+		goto skip_ipv6_process;
+	}
+
+	/*
+	 * Return if destination IP address is multicast address.
+	 */
+	if (ecm_ip_addr_is_multicast(ip_hdr.dest_addr)) {
+		DEBUG_WARN("Multicast acceleration is not support in PPPoE bridge %px\n", skb);
+		goto skip_ipv6_process;
+	}
+
+	result = ecm_ipv6_ip_process(out, in, skb_eth_hdr->h_source,
+					 skb_eth_hdr->h_dest, can_accel,
+					 false, true, skb, ETH_P_PPP_SES);
+skip_ipv6_process:
+	ecm_front_end_push_l2_encap_header(skb, encap_header_len);
+	skb->protocol = htons(ETH_P_PPP_SES);
+
+	return result;
+}
+
+/*
+ * ecm_ipv6_bridge_post_routing_hook()
+ *	Called for packets that are going out to one of the bridge physical interfaces.
+ *
+ * These may have come from another bridged interface or from a non-bridged interface.
+ * Conntrack information may be available or not if this skb is bridged.
+ */
+static unsigned int ecm_ipv6_bridge_post_routing_hook(void *priv,
+					struct sk_buff *skb,
+					const struct nf_hook_state *nhs)
+{
+	struct net_device *out = nhs->out;
+	struct ethhdr *skb_eth_hdr;
+	uint16_t eth_type;
+	struct net_device *bridge;
+	struct net_device *in;
+	bool can_accel = true;
+	unsigned int result = NF_ACCEPT;
+
+	DEBUG_TRACE("%px: IPv6 CMN Bridge: %s\n", out, out->name);
+
+	/*
+	 * If operations have stopped then do not process packets
+	 */
+	spin_lock_bh(&ecm_ipv6_lock);
+	if (unlikely(ecm_front_end_ipv6_stopped)) {
+		spin_unlock_bh(&ecm_ipv6_lock);
+		DEBUG_TRACE("Front end stopped\n");
+		return NF_ACCEPT;
+	}
+	spin_unlock_bh(&ecm_ipv6_lock);
+
+	/*
+	 * Don't process broadcast or multicast
+	 */
+	if (skb->pkt_type == PACKET_BROADCAST) {
+		DEBUG_TRACE("Broadcast, ignoring: %px\n", skb);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * skip l2tp/pptp because we don't accelerate them
+	 */
+	if (ecm_interface_is_l2tp_pptp(skb, out)) {
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Check packet is an IP Ethernet packet
+	 */
+	skb_eth_hdr = eth_hdr(skb);
+	if (!skb_eth_hdr) {
+		DEBUG_TRACE("%px: Not Eth\n", skb);
+		return NF_ACCEPT;
+	}
+	eth_type = ntohs(skb_eth_hdr->h_proto);
+	if (unlikely((eth_type != 0x86DD) && (eth_type != ETH_P_PPP_SES))) {
+		DEBUG_TRACE("%px: Not IP/PPPoE session\n", skb);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Identify interface from where this packet came.
+	 * There are three scenarios to consider here:
+	 * 1. Packet came from a local source.
+	 *	Ignore - local is not handled.
+	 * 2. Packet came from a routed path.
+	 *	Ignore - it was handled in INET post routing.
+	 * 3. Packet is bridged from another port.
+	 *	Process.
+	 *
+	 * Begin by identifying case 1.
+	 * NOTE: We are given 'out' (which we implicitly know is a bridge port) so out interface's master is the 'bridge'.
+	 */
+	bridge = ecm_interface_get_and_hold_dev_master((struct net_device *)out);
+	DEBUG_ASSERT(bridge, "Expected bridge\n");
+	in = dev_get_by_index(&init_net, skb->skb_iif);
+	if (!in) {
+		/*
+		 * Case 1.
+		 */
+		DEBUG_TRACE("Local traffic: %px, ignoring traffic to bridge: %px (%s) \n", skb, bridge, bridge->name);
+		dev_put(bridge);
+		return NF_ACCEPT;
+	}
+	dev_put(in);
+
+	/*
+	 * Case 2:
+	 *	For routed packets the skb will have the src mac matching the bridge mac.
+	 * Case 3:
+	 *	If the packet was not local (case 1) or routed (case 2) then
+	 *	we process. There is an exception to case 2: when hairpin mode
+	 *	is enabled, we process.
+	 */
+
+	/*
+	 * Pass in NULL (for skb) and 0 for cookie since doing FDB lookup only
+	 */
+	in = br_port_dev_get(bridge, skb_eth_hdr->h_source, NULL, 0);
+	if (!in) {
+		DEBUG_TRACE("skb: %px, no in device for bridge: %px (%s)\n", skb, bridge, bridge->name);
+		dev_put(bridge);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * This flag needs to be checked in slave port(eth0/ath0)
+	 * and not on master interface(br-lan). Hairpin flag can be
+	 * enabled/disabled for ports individually.
+	 */
+	if (in == out) {
+		if (!br_is_hairpin_enabled(in)) {
+			DEBUG_TRACE("skb: %px, bridge: %px (%s), ignoring"
+					"the packet, hairpin not enabled"
+					"on port %px (%s)\n", skb, bridge,
+					bridge->name, out, out->name);
+			goto skip_ipv6_bridge_flow;
+		}
+		DEBUG_TRACE("skb: %px, bridge: %px (%s), hairpin enabled on port"
+				"%px (%s)\n", skb, bridge, bridge->name, out, out->name);
+	}
+
+	/*
+	 * Case 2: Routed trafffic would be handled by the INET post routing.
+	 */
+	if (!ecm_mac_addr_equal(skb_eth_hdr->h_source, bridge->dev_addr)) {
+		DEBUG_TRACE("skb: %px, Ignoring routed packet to bridge: %px (%s)\n", skb, bridge, bridge->name);
+		goto skip_ipv6_bridge_flow;
+	}
+
+	if (!is_multicast_ether_addr(skb_eth_hdr->h_dest)) {
+		/*
+		 * Process the packet, if we have this mac address in the fdb table.
+		 * TODO: For the kernel versions later than 3.6.x, the API needs vlan id.
+		 * 	 For now, we are passing 0, but this needs to be handled later.
+		 */
+		if (!br_fdb_has_entry((struct net_device *)out, skb_eth_hdr->h_dest, 0)) {
+			DEBUG_WARN("skb: %px, No fdb entry for this mac address %pM in the bridge: %px (%s)\n",
+					skb, skb_eth_hdr->h_dest, bridge, bridge->name);
+			goto skip_ipv6_bridge_flow;
+		}
+	}
+
+	DEBUG_TRACE("Bridge process skb: %px, bridge: %px (%s), In: %px (%s), Out: %px (%s)\n",
+			skb, bridge, bridge->name, in, in->name, out, out->name);
+
+	if (unlikely(eth_type == ETH_P_PPP_SES)) {
+
+#ifdef ECM_FRONT_END_NSS_ENABLE
+		/*
+		 * Check if PPPoE bridge acceleration is disabled.
+		 */
+		if (nss_pppoe_get_br_accel_mode() == NSS_PPPOE_BR_ACCEL_MODE_DIS) {
+			DEBUG_TRACE("skb: %px, PPPoE bridge flow acceleration is disabled\n", skb);
+			goto skip_ipv6_bridge_flow;
+		}
+#endif
+
+		result = ecm_ipv6_pppoe_bridge_process((struct net_device *)out, in, skb_eth_hdr, can_accel, skb);
+		goto skip_ipv6_bridge_flow;
+	}
+	result = ecm_ipv6_ip_process((struct net_device *)out, in,
+							skb_eth_hdr->h_source, skb_eth_hdr->h_dest, can_accel, false, false, skb, 0);
+skip_ipv6_bridge_flow:
+	dev_put(in);
+	dev_put(bridge);
+	return result;
+}
+
+/*
+ * struct nf_hook_ops ecm_ipv6_netfilter_routing_hooks[]
+ *	Hooks into netfilter routing packet monitoring points.
+ */
+static struct nf_hook_ops ecm_ipv6_netfilter_routing_hooks[] __read_mostly = {
+	/*
+	 * Post routing hook is used to monitor packets going to interfaces that are NOT bridged in some way, e.g. packets to the WAN.
+	 */
+	{
+		.hook           = ecm_ipv6_post_routing_hook,
+		.pf             = PF_INET6,
+		.hooknum        = NF_INET_POST_ROUTING,
+		.priority       = NF_IP6_PRI_NAT_SRC + 1,
+	},
+};
+
+/*
+ * struct nf_hook_ops ecm_ipv6_netfilter_bridge_hooks[]
+ *	Hooks into netfilter bridge packet monitoring points.
+ */
+static struct nf_hook_ops ecm_ipv6_netfilter_bridge_hooks[] __read_mostly = {
+	/*
+	 * The bridge post routing hook monitors packets going to interfaces that are part of a bridge arrangement.
+	 * For example Wireles LAN (WLAN) and Wired LAN (LAN).
+	 */
+	{
+		.hook		= ecm_ipv6_bridge_post_routing_hook,
+		.pf		= PF_BRIDGE,
+		.hooknum	= NF_BR_POST_ROUTING,
+		.priority	= NF_BR_PRI_FILTER_OTHER,
+	},
+};
+
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+/*
+ * ecm_ipv6_ovs_dp_process()
+ *      Process OVS IPv6 bridged packets.
+ */
+unsigned int ecm_ipv6_ovs_dp_process(struct sk_buff *skb, struct net_device *out)
+{
+	struct ethhdr *skb_eth_hdr;
+	bool can_accel = true;
+	struct net_device *in;
+
+	/*
+	 * If operations have stopped then do not process packets
+	 */
+	spin_lock_bh(&ecm_ipv6_lock);
+	if (unlikely(ecm_front_end_ipv6_stopped)) {
+		spin_unlock_bh(&ecm_ipv6_lock);
+		DEBUG_TRACE("Front end stopped\n");
+		return 1;
+	}
+	spin_unlock_bh(&ecm_ipv6_lock);
+
+	/*
+	 * Don't process broadcast.
+	 */
+	if (skb->pkt_type == PACKET_BROADCAST) {
+		DEBUG_TRACE("Broadcast, ignoring: %px\n", skb);
+		return 1;
+	}
+
+	/*
+	 * Don't process multicast packets if Frontend does not support mcast acceleration
+	 */
+	if (skb->pkt_type == PACKET_MULTICAST) {
+		if (!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_MULTICAST)) {
+			DEBUG_TRACE("Broadcast, ignoring: %px\n", skb);
+			return 1;
+		}
+	}
+
+	if (skb->protocol != ntohs(ETH_P_IPV6)) {
+		DEBUG_WARN("%px: Wrong skb protocol: %d", skb, skb->protocol);
+		return 1;
+	}
+
+	skb_eth_hdr = eth_hdr(skb);
+	if (!skb_eth_hdr) {
+		DEBUG_WARN("%px: Not Eth\n", skb);
+		return 1;
+	}
+
+	in = dev_get_by_index(&init_net, skb->skb_iif);
+	if (!in) {
+		DEBUG_WARN("%px: No in device\n", skb);
+		return 1;
+	}
+
+	DEBUG_TRACE("%px: in: %s out: %s skb->protocol: %x\n", skb, in->name, out->name, skb->protocol);
+
+	if (netif_is_ovs_master(in)) {
+		if (!ecm_mac_addr_equal(skb_eth_hdr->h_dest, in->dev_addr)) {
+			DEBUG_TRACE("%px: in is bridge and mac address equals to packet dest, flow is routed, ignore \n", skb);
+			dev_put(in);
+			return 1;
+		}
+	}
+
+	if (netif_is_ovs_master(out)) {
+		if (!ecm_mac_addr_equal(skb_eth_hdr->h_source, out->dev_addr)) {
+			DEBUG_TRACE("%px: out is bridge and mac address equals to packet source, flow is routed, ignore \n", skb);
+			dev_put(in);
+			return 1;
+		}
+	}
+
+	ecm_ipv6_ip_process((struct net_device *)out, in,
+			skb_eth_hdr->h_source, skb_eth_hdr->h_dest, can_accel, false, false, skb, ETH_P_IPV6);
+	dev_put(in);
+
+	return 0;
+}
+
+static struct ovsmgr_dp_hook_ops ecm_ipv6_dp_hooks = {
+	.protocol = 6,
+	.hook_num = OVSMGR_DP_HOOK_POST_FLOW_PROC,
+	.hook = ecm_ipv6_ovs_dp_process,
+};
+#endif
+
+/*
+ * ecm_ipv6_init()
+ */
+int ecm_ipv6_init(struct dentry *dentry)
+{
+	int result;
+
+	DEBUG_INFO("ECM CMN IPv6 init\n");
+
+#ifdef ECM_FRONT_END_NSS_ENABLE
+	result = ecm_nss_ipv6_init(dentry);
+	if (result < 0) {
+		DEBUG_ERROR("Can't initialize NSS ipv6\n");
+		return result;
+	}
+#endif
+	result = ecm_sfe_ipv6_init(dentry);
+	if (result < 0) {
+		DEBUG_ERROR("Can't initialize SFE ipv6\n");
+		goto sfe_ipv6_failed;
+	}
+
+	/*
+	 * Register netfilter routing hooks
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	result = nf_register_hooks(ecm_ipv6_netfilter_routing_hooks, ARRAY_SIZE(ecm_ipv6_netfilter_routing_hooks));
+#else
+	result = nf_register_net_hooks(&init_net, ecm_ipv6_netfilter_routing_hooks, ARRAY_SIZE(ecm_ipv6_netfilter_routing_hooks));
+#endif
+	if (result < 0) {
+		DEBUG_ERROR("Can't register common netfilter routing hooks.\n");
+		goto nf_register_failed_1;
+	}
+
+	/*
+	 * Register netfilter bridge hooks, if the frontend type supports it. SFE only mode doesn't support it.
+	 */
+	if (ecm_front_end_is_feature_supported(ECM_FE_FEATURE_BRIDGE)) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+		result = nf_register_hooks(ecm_ipv6_netfilter_bridge_hooks, ARRAY_SIZE(ecm_ipv6_netfilter_bridge_hooks));
+#else
+		result = nf_register_net_hooks(&init_net, ecm_ipv6_netfilter_bridge_hooks, ARRAY_SIZE(ecm_ipv6_netfilter_bridge_hooks));
+#endif
+		if (result < 0) {
+			DEBUG_ERROR("Can't register common netfilter bridge hooks.\n");
+			goto nf_register_failed_2;
+		}
+	}
+
+	/*
+	 * Register Ovs Bridge DP hooks for frontends that supports bridge acceleration
+	 */
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+	if (ecm_front_end_is_feature_supported(ECM_FE_FEATURE_OVS_BRIDGE)) {
+		ovsmgr_dp_hook_register(&ecm_ipv6_dp_hooks);
+	}
+#endif
+	return 0;
+
+nf_register_failed_2:
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	nf_unregister_hooks(ecm_ipv6_netfilter_routing_hooks, ARRAY_SIZE(ecm_ipv6_netfilter_routing_hooks));
+#else
+	nf_unregister_net_hooks(&init_net, ecm_ipv6_netfilter_routing_hooks, ARRAY_SIZE(ecm_ipv6_netfilter_routing_hooks));
+#endif
+nf_register_failed_1:
+	ecm_sfe_ipv6_exit();
+
+sfe_ipv6_failed:
+#ifdef ECM_FRONT_END_NSS_ENABLE
+	ecm_nss_ipv6_exit();
+#endif
+	return result;
+}
+
+/*
+ * ecm_ipv6_exit()
+ */
+void ecm_ipv6_exit(void)
+{
+	DEBUG_INFO("ECM CMN IPv6 Module exit\n");
+
+	spin_lock_bh(&ecm_ipv6_lock);
+	ecm_ipv6_terminate_pending = true;
+	spin_unlock_bh(&ecm_ipv6_lock);
+
+	/*
+	 * Unregister netfilter bridge hooks, if the frontend type supports it. SFE only mode doesn't support it.
+	 */
+	if (ecm_front_end_is_feature_supported(ECM_FE_FEATURE_BRIDGE)) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+		nf_unregister_hooks(ecm_ipv6_netfilter_bridge_hooks, ARRAY_SIZE(ecm_ipv6_netfilter_bridge_hooks));
+#else
+		nf_unregister_net_hooks(&init_net, ecm_ipv6_netfilter_bridge_hooks, ARRAY_SIZE(ecm_ipv6_netfilter_bridge_hooks));
+#endif
+	}
+
+	/*
+	 * Unregister the netfilter routing hooks.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	nf_unregister_hooks(ecm_ipv6_netfilter_routing_hooks, ARRAY_SIZE(ecm_ipv6_netfilter_routing_hooks));
+#else
+	nf_unregister_net_hooks(&init_net, ecm_ipv6_netfilter_routing_hooks, ARRAY_SIZE(ecm_ipv6_netfilter_routing_hooks));
+#endif
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+	if (ecm_front_end_is_feature_supported(ECM_FE_FEATURE_OVS_BRIDGE)) {
+		ovsmgr_dp_hook_unregister(&ecm_ipv6_dp_hooks);
+	}
+#endif
+	ecm_sfe_ipv6_exit();
+#ifdef ECM_FRONT_END_NSS_ENABLE
+	ecm_nss_ipv6_exit();
+#endif
+}
diff --git a/qca-nss-ecm/frontends/cmn/ecm_ipv6.h b/qca-nss-ecm/frontends/cmn/ecm_ipv6.h
new file mode 100644
index 0000000..20df114
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_ipv6.h
@@ -0,0 +1,41 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2016, 2020-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * Locking of the classifier - concurrency control for file global parameters.
+ * NOTE: It is safe to take this lock WHILE HOLDING a feci->lock.  The reverse is NOT SAFE.
+ */
+extern spinlock_t ecm_ipv6_lock;			/* Protect against SMP access between netfilter, events and private threaded function. */
+
+/*
+ * Management thread control
+ */
+extern bool ecm_ipv6_terminate_pending;		/* True when the user has signalled we should quit */
+
+extern unsigned int ecm_ipv6_ip_process(struct net_device *out_dev, struct net_device *in_dev,
+							uint8_t *src_node_addr, uint8_t *dest_node_addr,
+							bool can_accel, bool is_routed, bool is_l2_encap,
+							struct sk_buff *skb, uint16_t l2_encap_proto);
+extern void ecm_ipv6_connection_regenerate(struct ecm_db_connection_instance *ci, ecm_tracker_sender_type_t sender,
+							struct net_device *out_dev, struct net_device *in_dev, __be16 *layer4hdr, struct sk_buff *skb);
+extern struct ecm_db_node_instance *ecm_ipv6_node_establish_and_ref(struct ecm_front_end_connection_instance *feci,
+							struct net_device *dev, ip_addr_t addr,
+							struct ecm_db_iface_instance *interface_list[], int32_t interface_list_first,
+							uint8_t *given_node_addr, struct sk_buff *skb);
+extern struct ecm_db_host_instance *ecm_ipv6_host_establish_and_ref(ip_addr_t addr);
+extern struct ecm_db_mapping_instance *ecm_ipv6_mapping_establish_and_ref(ip_addr_t addr, int port);
+extern int ecm_ipv6_init(struct dentry *dentry);
+extern void ecm_ipv6_exit(void);
diff --git a/qca-nss-ecm/frontends/cmn/ecm_multicast_ipv4.c b/qca-nss-ecm/frontends/cmn/ecm_multicast_ipv4.c
new file mode 100644
index 0000000..ea91eda
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_multicast_ipv4.c
@@ -0,0 +1,1600 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/sysctl.h>
+#include <linux/kthread.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/pkt_sched.h>
+#include <linux/debugfs.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/addrconf.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/mroute.h>
+#include <linux/vmalloc.h>
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+#include <net/vxlan.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_MULTICAST_IPV4_DEBUG_LEVEL
+
+#ifdef ECM_FRONT_END_NSS_ENABLE
+#include <nss_api_if.h>
+#endif
+
+#include <mc_ecm.h>
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#ifdef ECM_FRONT_END_NSS_ENABLE
+#include "ecm_nss_ipv4.h"
+#include "ecm_nss_multicast_ipv4.h"
+#include "ecm_nss_common.h"
+#endif
+#include "ecm_front_end_common.h"
+#include "ecm_ipv4.h"
+#include "ecm_ae_classifier_public.h"
+#include "ecm_ae_classifier.h"
+
+/*
+ * ecm_multicast_connection_to_interface_heirarchy_construct()
+ * 	Create destination interface heirarchy for a routed/bridge multicast connection
+ */
+static int32_t ecm_multicast_connection_to_interface_heirarchy_construct(struct ecm_front_end_connection_instance *feci,
+								      struct ecm_db_iface_instance *interfaces, ip_addr_t ip_src_addr, ip_addr_t ip_dest_addr,
+								      struct net_device *in_dev, struct net_device *brdev, uint8_t max_if, uint32_t *dst_dev,
+								      uint32_t *to_list_first, uint8_t *src_node_addr, bool is_routed,
+								      __be16 *layer4hdr, struct sk_buff *skb)
+{
+	int interface_instance_cnt;
+	if (is_routed) {
+		interface_instance_cnt = ecm_interface_multicast_heirarchy_construct_routed(feci, interfaces, in_dev, ip_src_addr, ip_dest_addr, max_if, dst_dev, to_list_first, false, layer4hdr, skb);
+	} else {
+		interface_instance_cnt = ecm_interface_multicast_heirarchy_construct_bridged(feci, interfaces, brdev, ip_src_addr, ip_dest_addr, max_if, dst_dev, to_list_first, src_node_addr, layer4hdr, skb);
+	}
+
+	return interface_instance_cnt;
+}
+
+/*
+ * ecm_multicast_ipv4_connection_regenerate()
+ *	Re-generate a connection.
+ *
+ * Re-generating a connection involves re-evaluating the interface lists in case interface heirarchies have changed.
+ * It also involves the possible triggering of classifier re-evaluation but only if all currently assigned
+ * classifiers permit this operation.
+ */
+static void ecm_multicast_ipv4_connection_regenerate(struct ecm_db_connection_instance *ci, ecm_tracker_sender_type_t sender,
+							struct net_device *out_dev, struct net_device *in_dev, struct net_device *in_dev_nat)
+{
+	int i;
+	bool reclassify_allowed;
+	struct ecm_db_iface_instance *from_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+	int32_t from_list_first;
+	struct ecm_db_iface_instance *from_nat_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+	int32_t from_nat_list_first;
+	ip_addr_t ip_src_addr;
+	ip_addr_t ip_dest_addr;
+	ip_addr_t ip_src_addr_nat;
+	int protocol;
+	bool is_routed;
+	uint8_t src_node_addr[ETH_ALEN];
+	uint8_t dest_node_addr[ETH_ALEN];
+	uint8_t src_node_addr_nat[ETH_ALEN];
+	int assignment_count;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	struct ecm_front_end_connection_instance *feci;
+	__be16 layer4hdr[2] = {0, 0};
+	__be16 port = 0;
+
+	/*
+	 * Update the interface lists - these may have changed, e.g. LAG path change etc.
+	 * NOTE: We never have to change the usual mapping->host->node_iface arrangements for each side of the connection (to/from sides)
+	 * This is because if these interfaces change then the connection is dead anyway.
+	 * But a LAG slave might change the heirarchy the connection is using but the LAG master is still sane.
+	 * If any of the new interface heirarchies cannot be created then simply set empty-lists as this will deny
+	 * acceleration and ensure that a bad rule cannot be created.
+	 * IMPORTANT: The 'sender' defines who has sent the packet that triggered this re-generation
+	 */
+	protocol = ecm_db_connection_protocol_get(ci);
+
+	is_routed = ecm_db_connection_is_routed_get(ci);
+
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, ip_src_addr);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM_NAT, ip_src_addr_nat);
+
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, ip_dest_addr);
+
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_node_addr);
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM_NAT, src_node_addr_nat);
+
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, dest_node_addr);
+
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+	port = (__be16)(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+	layer4hdr[0] = htons(port);
+	port = (__be16)(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO));
+	layer4hdr[1] = htons(port);
+
+	DEBUG_TRACE("%px: Update the 'from' interface heirarchy list\n", ci);
+	from_list_first = ecm_interface_multicast_from_heirarchy_construct(feci, from_list, ip_dest_addr, ip_src_addr, 4, protocol, in_dev, is_routed, in_dev, src_node_addr, dest_node_addr, layer4hdr, NULL);
+	if (from_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		goto ecm_multicast_ipv4_retry_regen;
+	}
+
+	ecm_db_connection_interfaces_reset(ci, from_list, from_list_first, ECM_DB_OBJ_DIR_FROM);
+	ecm_db_connection_interfaces_deref(from_list, from_list_first);
+
+	DEBUG_TRACE("%px: Update the 'from NAT' interface heirarchy list\n", ci);
+	from_nat_list_first = ecm_interface_multicast_from_heirarchy_construct(feci, from_nat_list, ip_dest_addr, ip_src_addr_nat, 4, protocol, in_dev_nat, is_routed, in_dev_nat, src_node_addr_nat, dest_node_addr, layer4hdr, NULL);
+	if (from_nat_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		goto ecm_multicast_ipv4_retry_regen;
+	}
+
+	ecm_db_connection_interfaces_reset(ci, from_nat_list, from_nat_list_first, ECM_DB_OBJ_DIR_FROM_NAT);
+	ecm_db_connection_interfaces_deref(from_nat_list, from_nat_list_first);
+
+	feci->deref(feci);
+
+	/*
+	 * Get list of assigned classifiers to reclassify.
+	 * Remember: This also includes our default classifier too.
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+
+	/*
+	 * All of the assigned classifiers must permit reclassification.
+	 */
+	reclassify_allowed = true;
+	for (i = 0; i < assignment_count; ++i) {
+		DEBUG_TRACE("%px: Calling to reclassify: %px, type: %d\n", ci, assignments[i], assignments[i]->type_get(assignments[i]));
+		if (!assignments[i]->reclassify_allowed(assignments[i])) {
+			DEBUG_TRACE("%px: reclassify denied: %px, by type: %d\n", ci, assignments[i], assignments[i]->type_get(assignments[i]));
+			reclassify_allowed = false;
+			break;
+		}
+	}
+
+	/*
+	 * Now we action any classifier re-classify
+	 */
+	if (!reclassify_allowed) {
+		/*
+		 * Regeneration came to a successful conclusion even though reclassification was denied
+		 */
+		DEBUG_WARN("%px: re-classify denied\n", ci);
+		goto ecm_multicast_ipv4_regen_done;
+	}
+
+	/*
+	 * Reclassify
+	 */
+	DEBUG_INFO("%px: reclassify\n", ci);
+	if (!ecm_classifier_reclassify(ci, assignment_count, assignments)) {
+		/*
+		 * We could not set up the classifiers to reclassify, it is safer to fail out and try again next time
+		 */
+		DEBUG_WARN("%px: Regeneration: reclassify failed\n", ci);
+		goto ecm_multicast_ipv4_regen_done;
+	}
+	DEBUG_INFO("%px: reclassify success\n", ci);
+
+ecm_multicast_ipv4_regen_done:
+
+	/*
+	 * Release the assignments
+	 */
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Re-generation of state is successful.
+	 */
+	ecm_db_connection_regeneration_completed(ci);
+
+	return;
+
+ecm_multicast_ipv4_retry_regen:
+	feci->deref(feci);
+	ecm_db_connection_regeneration_failed(ci);
+	return;
+}
+
+/*
+ * ecm_multicast_ipv4_node_establish_and_ref()
+ *	Returns a reference to a node, possibly creating one if necessary.
+ *
+ * The given_node_addr will be used if provided.
+ *
+ * Returns NULL on failure.
+ *
+ * TODO: This function will be removed later and the one in the ecm_ipv4.c file will be used
+ *	instead of this one when the multicast code is fixed to use the new interface hierarchy
+ *	construction model.
+ */
+static struct ecm_db_node_instance *ecm_multicast_ipv4_node_establish_and_ref(struct ecm_front_end_connection_instance *feci,
+							struct net_device *dev, ip_addr_t addr,
+							struct ecm_db_iface_instance *interface_list[], int32_t interface_list_first,
+							uint8_t *given_node_addr, struct sk_buff *skb)
+{
+	struct ecm_db_node_instance *ni;
+	struct ecm_db_node_instance *nni;
+	struct ecm_db_iface_instance *ii;
+	int i;
+	bool done;
+	uint8_t node_addr[ETH_ALEN];
+#if defined(ECM_INTERFACE_L2TPV2_ENABLE) || defined(ECM_INTERFACE_PPTP_ENABLE)
+	ip_addr_t local_ip, remote_ip;
+#endif
+
+	DEBUG_INFO("Establish node for " ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(addr));
+
+	/*
+	 * The node is the datalink address, typically a MAC address.
+	 * However the node address to use is not always obvious and depends on the interfaces involved.
+	 * For example if the interface is PPPoE then we use the MAC of the PPPoE server as we cannot use normal ARP resolution.
+	 * Not all hosts have a node address, where there is none, a suitable alternative should be located and is typically based on 'addr'
+	 * or some other datalink session information.
+	 * It should be, at a minimum, something that ties the host with the interface.
+	 *
+	 * Iterate from 'inner' to 'outer' interfaces - discover what the node is.
+	 */
+	memset(node_addr, 0, ETH_ALEN);
+	done = false;
+	if (given_node_addr) {
+		memcpy(node_addr, given_node_addr, ETH_ALEN);
+		done = true;
+		DEBUG_TRACE("Using given node address: %pM\n", node_addr);
+	}
+
+	for (i = ECM_DB_IFACE_HEIRARCHY_MAX - 1; (!done) && (i >= interface_list_first); i--) {
+		ecm_db_iface_type_t type;
+		ip_addr_t gw_addr = ECM_IP_ADDR_NULL;
+		bool on_link = false;
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+		struct ecm_db_interface_info_pppoe pppoe_info;
+#endif
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+		struct ecm_db_interface_info_pppol2tpv2 pppol2tpv2_info;
+#endif
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+		struct ecm_db_interface_info_pptp pptp_info;
+#endif
+		type = ecm_db_iface_type_get(interface_list[i]);
+		DEBUG_INFO("Lookup node address, interface @ %d is type: %d\n", i, type);
+
+		switch (type) {
+
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * Node address is the address of the remote PPPoE server
+			 */
+			ecm_db_iface_pppoe_session_info_get(interface_list[i], &pppoe_info);
+			memcpy(node_addr, pppoe_info.remote_mac, ETH_ALEN);
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("PPPoE interface unsupported\n");
+			return NULL;
+#endif
+
+		case ECM_DB_IFACE_TYPE_SIT:
+		case ECM_DB_IFACE_TYPE_TUNIPIP6:
+			done = true;
+			break;
+
+		case ECM_DB_IFACE_TYPE_PPPOL2TPV2:
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+			ecm_db_iface_pppol2tpv2_session_info_get(interface_list[i], &pppol2tpv2_info);
+			ECM_HIN4_ADDR_TO_IP_ADDR(local_ip, pppol2tpv2_info.ip.saddr);
+			ECM_HIN4_ADDR_TO_IP_ADDR(remote_ip, pppol2tpv2_info.ip.daddr);
+			if (ECM_IP_ADDR_MATCH(local_ip, addr)) {
+				if (unlikely(!ecm_interface_mac_addr_get(local_ip, node_addr, &on_link, gw_addr))) {
+					DEBUG_TRACE("failed to obtain node address for " ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(local_ip));
+					return NULL;
+				}
+
+			} else {
+				if (unlikely(!ecm_interface_mac_addr_get(remote_ip, node_addr, &on_link, gw_addr))) {
+					DEBUG_TRACE("failed to obtain node address for host " ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(remote_ip));
+					return NULL;
+				}
+			}
+
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("PPPoL2TPV2 interface unsupported\n");
+			return NULL;
+#endif
+
+		case ECM_DB_IFACE_TYPE_PPTP:
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+			ecm_db_iface_pptp_session_info_get(interface_list[i], &pptp_info);
+			ECM_HIN4_ADDR_TO_IP_ADDR(local_ip, pptp_info.src_ip);
+			ECM_HIN4_ADDR_TO_IP_ADDR(remote_ip, pptp_info.dst_ip);
+			if (ECM_IP_ADDR_MATCH(local_ip, addr)) {
+				if (unlikely(!ecm_interface_mac_addr_get(local_ip, node_addr, &on_link, gw_addr))) {
+					DEBUG_TRACE("failed to obtain node address for " ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(local_ip));
+					return NULL;
+				}
+
+			} else {
+				if (unlikely(!ecm_interface_mac_addr_get(remote_ip, node_addr, &on_link, gw_addr))) {
+					DEBUG_TRACE("failed to obtain node address for host " ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(remote_ip));
+					return NULL;
+				}
+			}
+
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("PPTP interface unsupported\n");
+			return NULL;
+#endif
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			/*
+			 * VLAN handled same along with ethernet, lag, bridge etc.
+			 */
+#else
+			DEBUG_TRACE("VLAN interface unsupported\n");
+			return NULL;
+#endif
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+		case ECM_DB_IFACE_TYPE_LAG:
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#endif
+			if (!ecm_interface_mac_addr_get(addr, node_addr, &on_link, gw_addr)) {
+				DEBUG_TRACE("failed to obtain node address for host " ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(addr));
+				ecm_interface_send_arp_request(dev, addr, on_link, gw_addr);
+
+				/*
+				 * Unable to get node address at this time.
+				 */
+				return NULL;
+			}
+
+			if (is_multicast_ether_addr(node_addr)) {
+				DEBUG_TRACE("multicast node address for host " ECM_IP_ADDR_DOT_FMT ", node_addr: %pM\n", ECM_IP_ADDR_TO_DOT(addr), node_addr);
+				return NULL;
+			}
+
+			/*
+			 * Because we are iterating from inner to outer interface, this interface is the
+			 * innermost one that has a node address - take this one.
+			 */
+			done = true;
+			break;
+		default:
+			/*
+			 * Don't know how to handle these.
+			 * Just copy some part of the address for now, but keep iterating the interface list
+			 * in the hope something recognisable will be seen!
+			 * GGG TODO We really need to roll out support for all interface types we can deal with ASAP :-(
+			 */
+			memcpy(node_addr, (uint8_t *)addr, ETH_ALEN);
+		}
+	}
+	if (!done) {
+		DEBUG_INFO("Failed to establish node for " ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(addr));
+		return NULL;
+	}
+
+	/*
+	 * Establish iface
+	 */
+	ii = ecm_interface_establish_and_ref(feci, dev, skb);
+	if (!ii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Locate the node
+	 */
+	ni = ecm_db_node_find_and_ref(node_addr, ii);
+	if (ni) {
+		DEBUG_TRACE("%px: node established\n", ni);
+		ecm_db_iface_deref(ii);
+		return ni;
+	}
+
+	/*
+	 * No node - create one
+	 */
+	nni = ecm_db_node_alloc();
+	if (!nni) {
+		DEBUG_WARN("Failed to establish node\n");
+		ecm_db_iface_deref(ii);
+		return NULL;
+	}
+
+	/*
+	 * Add node into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_ipv4_lock);
+	ni = ecm_db_node_find_and_ref(node_addr, ii);
+	if (ni) {
+		spin_unlock_bh(&ecm_ipv4_lock);
+		ecm_db_node_deref(nni);
+		ecm_db_iface_deref(ii);
+		return ni;
+	}
+
+	ecm_db_node_add(nni, ii, node_addr, NULL, nni);
+	spin_unlock_bh(&ecm_ipv4_lock);
+
+	/*
+	 * Don't need iface instance now
+	 */
+	ecm_db_iface_deref(ii);
+
+	DEBUG_TRACE("%px: node established\n", nni);
+	return nni;
+}
+
+/*
+ * ecm_multicast_ipv4_connection_process()
+ *	Process a UDP multicast flow
+ */
+unsigned int ecm_multicast_ipv4_connection_process(struct net_device *out_dev,
+							struct net_device *in_dev,
+							uint8_t *src_node_addr,
+							uint8_t *dest_node_addr,
+							bool can_accel, bool is_routed, struct sk_buff *skb,
+							struct ecm_tracker_ip_header *iph,
+							struct nf_conn *ct, ecm_tracker_sender_type_t sender,
+							struct nf_conntrack_tuple *orig_tuple, struct nf_conntrack_tuple *reply_tuple)
+{
+	int vif, if_cnt;
+	uint32_t dst_dev[ECM_DB_MULTICAST_IF_MAX];
+	struct udphdr *udp_hdr;
+	struct udphdr udp_hdr_buff;
+	int src_port;
+	int dest_port;
+	int src_port_nat = 0;
+	struct net_device *in_dev_nat = NULL;
+	struct net_device *out_dev_master = NULL;
+	struct ecm_db_multicast_tuple_instance *tuple_instance;
+	struct ecm_db_connection_instance *ci;
+	ip_addr_t match_addr;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	ecm_db_direction_t ecm_dir = ECM_DB_DIRECTION_INGRESS_NAT;
+	ecm_db_timer_group_t ci_orig_timer_group;
+	struct ecm_classifier_process_response prevalent_pr;
+	ip_addr_t ip_src_addr;
+	ip_addr_t ip_dest_addr;
+	ip_addr_t ip_src_addr_nat;
+	__be32 ip_src;
+	__be32 ip_grp;
+	bool br_dev_found_in_mfc = false;
+	int protocol = (int)orig_tuple->dst.protonum;
+	__be16 *layer4hdr = NULL;
+
+	if (protocol != IPPROTO_UDP) {
+		DEBUG_WARN("Invalid Protocol %d in skb %px\n", protocol, skb);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Extract UDP header to obtain port information
+	 */
+	udp_hdr = ecm_tracker_udp_check_header_and_read(skb, iph, &udp_hdr_buff);
+	if (unlikely(!udp_hdr)) {
+		DEBUG_WARN("Invalid UDP header in skb %px\n", skb);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Return if source dev is any tunnel type
+	 * TODO: Add support for multicast over tunnels
+	 *
+	 * Acceleration for multicast packet which is sent to
+	 * or received from VxLAN tunnel net device should be skipped.
+	 */
+	if ((in_dev->type == ECM_ARPHRD_IPSEC_TUNNEL_TYPE) ||
+	    (in_dev->type == ARPHRD_SIT) || (in_dev->type == ARPHRD_PPP) ||
+	    (in_dev->type == ARPHRD_TUNNEL6) ||
+	    (netif_is_vxlan(in_dev)) || (netif_is_vxlan(out_dev))) {
+		DEBUG_TRACE("in_dev: %px, in_type: %d, out_dev: %px, out_type: %d",
+				in_dev, in_dev->type, out_dev, out_dev->type);
+		return NF_ACCEPT;
+	}
+
+	layer4hdr = (__be16*)udp_hdr;
+	/*
+	 * Now extract information, if we have conntrack then use that (which would already be in the tuples)
+	 */
+	if (unlikely(!ct)) {
+		orig_tuple->src.u.udp.port = udp_hdr->source;
+		orig_tuple->dst.u.udp.port = udp_hdr->dest;
+		reply_tuple->src.u.udp.port = udp_hdr->dest;
+		reply_tuple->dst.u.udp.port = udp_hdr->source;
+	}
+
+	ECM_NIN4_ADDR_TO_IP_ADDR(ip_src_addr, orig_tuple->src.u3.ip);
+	ECM_NIN4_ADDR_TO_IP_ADDR(ip_dest_addr, orig_tuple->dst.u3.ip);
+	ECM_NIN4_ADDR_TO_IP_ADDR(ip_src_addr_nat, reply_tuple->dst.u3.ip);
+
+	ECM_IP_ADDR_TO_NIN4_ADDR(ip_src, ip_src_addr);
+	ECM_IP_ADDR_TO_NIN4_ADDR(ip_grp, ip_dest_addr);
+
+	/*
+	 * Extract Port numbers
+	 */
+	src_port = ntohs(orig_tuple->src.u.udp.port);
+	dest_port = ntohs(orig_tuple->dst.u.udp.port);
+	src_port_nat = ntohs(reply_tuple->dst.u.udp.port);
+
+	/*
+	 * Initialize in_dev_nat to default in_dev.
+	 */
+	in_dev_nat = in_dev;
+
+	/*
+	 * Query MFC/Bridge to access the destination interface list.
+	 */
+	memset(dst_dev, 0, sizeof(dst_dev));
+	if_cnt =  ipmr_find_mfc_entry(&init_net, ip_src, ip_grp, ECM_DB_MULTICAST_IF_MAX, dst_dev);
+
+	/*
+	 * Skip PPP acceleration
+	 */
+	if (ecm_interface_multicast_is_iface_type(dst_dev, if_cnt, ARPHRD_PPP)) {
+		DEBUG_TRACE("%px: Packet is of type PPP; skip it\n", skb);
+		return NF_ACCEPT;
+	}
+
+	if (is_routed) {
+		/*
+		 * This is a routed flow, hence look for a valid MFC rule
+		 */
+		if (if_cnt <= 0) {
+			DEBUG_WARN("Not found a valid vif count %d\n", if_cnt);
+			return NF_ACCEPT;
+		}
+	}
+
+	/*
+	 * For "bridge + route" scenario, we can receive packet from both bridge and route hook.
+	 * If MFC returns valid interface count (if_cnt), then we need to check for "bridge + route"
+	 * scenario.
+	 */
+	if (if_cnt > 0) {
+		is_routed = true;
+
+		/*
+		 * Check for the presence of a bridge device in the destination
+		 * interface list given to us by MFC
+		 */
+		br_dev_found_in_mfc = ecm_interface_multicast_check_for_br_dev(dst_dev, if_cnt);
+
+		/*
+		 * We are processing a routed multicast flow.
+		 * Check if the source interface is a bridge device. If this is the case,
+		 * this flow could be a "bridge + route" flow.
+		 * So, we query the bridge device as well for possible joinees
+		 */
+		if (ecm_front_end_is_bridge_device(in_dev)
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+				|| ecm_front_end_is_ovs_bridge_device(in_dev)
+#endif
+		   ) {
+			int32_t if_cnt_bridge;
+			uint32_t dst_dev_bridge[ECM_DB_MULTICAST_IF_MAX];
+
+			memset(dst_dev_bridge, 0, sizeof(dst_dev_bridge));
+			if_cnt_bridge = mc_bridge_ipv4_get_if(in_dev, ip_src, ip_grp, ECM_DB_MULTICAST_IF_MAX, dst_dev_bridge);
+			if (if_cnt_bridge <= 0) {
+				DEBUG_WARN("No bridge ports have joined multicast group\n");
+				goto process_packet;
+			}
+
+			/*
+			 * Check for max interface limit.
+			 */
+			if (if_cnt == ECM_DB_MULTICAST_IF_MAX) {
+				DEBUG_WARN("Interface count reached max limit: %d. Could not handle the connection", if_cnt);
+				goto done;
+			}
+
+			/*
+			 * Update the dst_dev with in_dev as it is a bridge + route case
+			 */
+			dst_dev[if_cnt++] = in_dev->ifindex;
+			br_dev_found_in_mfc = true;
+		}
+
+		goto process_packet;
+	}
+
+	/*
+	 * Packet flow is pure bridge. Try to query the snooper for the destination
+	 * interface list
+	 */
+	out_dev_master =  ecm_interface_get_and_hold_dev_master(out_dev);
+	DEBUG_ASSERT(out_dev_master, "Expected a master\n");
+	if_cnt = mc_bridge_ipv4_get_if(out_dev_master, ip_src, ip_grp, ECM_DB_MULTICAST_IF_MAX, dst_dev);
+	if (if_cnt <= 0) {
+		DEBUG_WARN("Not found a valid MCS if count %d\n", if_cnt);
+		goto done;
+	}
+
+	/*
+	 * The source interface could have joined the group as well.
+	 * In such cases, the destination interface list returned by
+	 * the snooper would include the source interface as well.
+	 * We need to filter the source interface from the list in such cases.
+	 */
+	if_cnt = ecm_interface_multicast_check_for_src_ifindex(dst_dev, if_cnt, in_dev->ifindex);
+	if (if_cnt <= 0) {
+		DEBUG_WARN("Not found a valid MCS if count %d\n", if_cnt);
+		goto done;
+	}
+
+process_packet:
+	/*
+	 * Work out if this packet involves NAT or not.
+	 * If it does involve NAT then work out if this is an ingressing or egressing packet.
+	 */
+	if (!ECM_IP_ADDR_MATCH(ip_src_addr, ip_src_addr_nat)) {
+		int nat_if_found = 0;
+		bool from_local_addr;
+
+		/*
+		 * Egressing NAT
+		 */
+		in_dev_nat = ecm_interface_dev_find_by_addr(ip_src_addr_nat, &from_local_addr);
+		if (!in_dev_nat) {
+			goto done;
+		}
+
+		/*
+		 * Try to find the egress NAT interface in the list of destination
+		 * interfaces
+		 */
+		for (vif = 0; vif < if_cnt; vif++) {
+			if (dst_dev[vif] == in_dev_nat->ifindex) {
+				nat_if_found = 1;
+				break;
+			}
+		}
+		dev_put(in_dev_nat);
+
+		/*
+		 * We have not found the NAT interface in the MFC destination interface
+		 * list for a NAT flow, which should not happen.
+		 */
+		if (!nat_if_found) {
+			goto done;
+		}
+	}
+
+	DEBUG_TRACE("MCAST UDP src: " ECM_IP_ADDR_DOT_FMT ":%d, dest: " ECM_IP_ADDR_DOT_FMT ":%d, dir %d\n",
+			ECM_IP_ADDR_TO_DOT(ip_src_addr), src_port, ECM_IP_ADDR_TO_DOT(ip_dest_addr), dest_port, ecm_dir);
+
+	/*
+	 * Look up a connection
+	 */
+	ci = ecm_db_connection_find_and_ref(ip_src_addr, ip_dest_addr, protocol, src_port, dest_port);
+
+	if (unlikely(!ci)) {
+		struct ecm_db_mapping_instance *mi[ECM_DB_OBJ_DIR_MAX];
+		struct ecm_db_node_instance *ni[ECM_DB_OBJ_DIR_MAX];
+		struct ecm_classifier_default_instance *dci;
+		struct ecm_front_end_connection_instance *feci;
+		struct ecm_db_connection_instance *nci;
+		struct ecm_db_iface_instance *from_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+		struct ecm_db_iface_instance *to_list;
+		struct ecm_db_iface_instance *to_list_single;
+		struct ecm_db_iface_instance *to_list_temp[ECM_DB_IFACE_HEIRARCHY_MAX];
+		struct ecm_db_iface_instance *from_nat_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+		ecm_classifier_type_t classifier_type;
+		int32_t from_list_first;
+		int32_t interface_idx_cnt = 0;
+		int32_t from_nat_list_first;
+		int32_t *to_list_first;
+		int32_t *to_first;
+		int ret;
+		uint8_t dest_mac_addr[ETH_ALEN];
+		enum ecm_front_end_type fe_type;
+		ecm_ae_classifier_result_t ae_result;
+		ecm_db_connection_defunct_callback_t defunct_callback;
+
+		DEBUG_TRACE("New UDP connection from " ECM_IP_ADDR_DOT_FMT ":%u to " ECM_IP_ADDR_DOT_FMT ":%u\n", ECM_IP_ADDR_TO_DOT(ip_src_addr), \
+				src_port, ECM_IP_ADDR_TO_DOT(ip_dest_addr), dest_port);
+
+		/*
+		 * Before we attempt to create the connection are we being terminated?
+		 */
+		spin_lock_bh(&ecm_ipv4_lock);
+		if (ecm_ipv4_terminate_pending) {
+			spin_unlock_bh(&ecm_ipv4_lock);
+			DEBUG_WARN("Terminating\n");
+
+			/*
+			 * As we are terminating we just allow the packet to pass - it's no longer our concern
+			 */
+			goto done;
+		}
+		spin_unlock_bh(&ecm_ipv4_lock);
+
+		/*
+		 * Connection must have a front end instance associated with it
+		 */
+		fe_type = ecm_front_end_type_get();
+		switch (fe_type) {
+#if defined(ECM_FRONT_END_NSS_ENABLE) && defined(ECM_FRONT_END_SFE_ENABLE)
+		case ECM_FRONT_END_TYPE_HYBRID:
+		{
+			ecm_ae_classifier_get_t ae_get;
+			struct ecm_ae_classifier_info ae_info;
+
+
+			ecm_ae_classifier_select_info_fill(ip_src_addr, ip_dest_addr,
+							  src_port, dest_port, protocol, 4,
+							  is_routed, true,
+							  &ae_info);
+			rcu_read_lock();
+			ae_get = rcu_dereference(ae_ops.ae_get);
+			ae_result = ae_get(&ae_info);
+			rcu_read_unlock();
+
+			DEBUG_TRACE("front end type hybrid, ae_result: %d\n", ae_result);
+			break;
+		}
+#endif
+#ifdef ECM_FRONT_END_NSS_ENABLE
+		case ECM_FRONT_END_TYPE_NSS:
+			DEBUG_TRACE("front end type NSS, ae_result: %d\n", ae_result);
+			ae_result = ECM_AE_CLASSIFIER_RESULT_NSS;
+			break;
+#endif
+#ifdef ECM_FRONT_END_SFE_ENABLE
+		case ECM_FRONT_END_TYPE_SFE:
+			/*
+			 * Fall through. Not supporting multicast acceleration yet.
+			 */
+#endif
+		default:
+			DEBUG_WARN("front end type: %d is not supported\n", fe_type);
+			goto done;
+		}
+
+		/*
+		 * Check the ae_result.
+		 * 1. If NSS, allocate NSS ipv4 multicast connection instance
+		 * 2. If NONE, allocate NSS ipv4 multicast connection instance with can_accel flag is set to false.
+		 *    By doing this ECM will not ask again and again to the external module. If external module wants to
+		 *    accelerate this flow later, the flow needs to be defuncted first.
+		 * 3. If NOT_YET, the connection will not be allocated in the database and the next flow will be asked again
+		 *    to the external module.
+		 * 4. If any other type is returned, ASSERT.
+		 */
+		switch (ae_result) {
+#ifdef ECM_FRONT_END_NSS_ENABLE
+		case ECM_AE_CLASSIFIER_RESULT_NSS:
+			defunct_callback = ecm_nss_multicast_ipv4_connection_defunct_callback;
+			feci = (struct ecm_front_end_connection_instance *)ecm_nss_multicast_ipv4_connection_instance_alloc(can_accel, &nci);
+			break;
+
+		case ECM_AE_CLASSIFIER_RESULT_NONE:
+			defunct_callback = ecm_nss_multicast_ipv4_connection_defunct_callback;
+			feci = (struct ecm_front_end_connection_instance *)ecm_nss_multicast_ipv4_connection_instance_alloc(false, &nci);
+			break;
+#endif
+		case ECM_AE_CLASSIFIER_RESULT_NOT_YET:
+			goto done;
+
+		default:
+			DEBUG_ASSERT(NULL, "unexpected ae_result: %d\n", ae_result);
+		}
+
+		if (!feci) {
+			DEBUG_WARN("Failed to allocate front end\n");
+			goto done;
+		}
+
+		/*
+		 * Create a tuple instance
+		 */
+		tuple_instance = ecm_db_multicast_tuple_instance_alloc(ip_src_addr, ip_dest_addr, src_port, dest_port);
+		if (!tuple_instance) {
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			DEBUG_WARN("Failed to allocate tuple instance\n");
+			goto done;
+		}
+
+		/*
+		 * Create Destination MAC address using IP multicast destination address
+		 */
+		ecm_translate_multicast_mac(ip_dest_addr, dest_mac_addr);
+
+		/*
+		 * Get the src and destination mappings.
+		 * For this we also need the interface lists which we also set upon the new connection while we are at it.
+		 */
+		DEBUG_TRACE("%px: Create the 'from' interface heirarchy list\n", nci);
+		from_list_first = ecm_interface_multicast_from_heirarchy_construct(feci, from_list, ip_dest_addr, ip_src_addr, 4, protocol, in_dev, is_routed, in_dev, src_node_addr, dest_node_addr, layer4hdr, skb);
+		if (from_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			DEBUG_WARN("Failed to obtain 'from' heirarchy list\n");
+			goto done;
+		}
+		ecm_db_connection_interfaces_reset(nci, from_list, from_list_first, ECM_DB_OBJ_DIR_FROM);
+
+		DEBUG_TRACE("%px: Establish source node\n", nci);
+		ni[ECM_DB_OBJ_DIR_FROM] = ecm_multicast_ipv4_node_establish_and_ref(feci, in_dev, ip_src_addr, from_list, from_list_first, src_node_addr, skb);
+		ecm_db_connection_interfaces_deref(from_list, from_list_first);
+		if (!ni[ECM_DB_OBJ_DIR_FROM]) {
+			DEBUG_WARN("%px: Failed to establish source node\n", nci);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			goto done;
+		}
+
+		DEBUG_TRACE("%px: Create source mapping\n", nci);
+		mi[ECM_DB_OBJ_DIR_FROM] = ecm_ipv4_mapping_establish_and_ref(ip_src_addr, src_port);
+		if (!mi[ECM_DB_OBJ_DIR_FROM]) {
+			DEBUG_WARN("%px: Failed to establish src mapping\n", nci);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			goto done;
+		}
+
+		to_list = (struct ecm_db_iface_instance *)kzalloc(ECM_DB_TO_MCAST_INTERFACES_SIZE, GFP_ATOMIC | __GFP_NOWARN);
+		if (!to_list) {
+			DEBUG_WARN("%px: Failed to alloc memory for multicast dest interface hierarchies\n", nci);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			goto done;
+		}
+
+		to_list_first = (int32_t *)kzalloc(sizeof(int32_t *) * ECM_DB_MULTICAST_IF_MAX, GFP_ATOMIC | __GFP_NOWARN);
+		if (!to_list_first) {
+			DEBUG_WARN("%px: Failed to alloc memory for multicast dest interfaces first list\n", nci);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			kfree(to_list);
+			goto done;
+		}
+
+		/*
+		 * Create the multicast 'to' interface heirarchy
+		 */
+		DEBUG_TRACE("%px: Create the multicast  'to' interface heirarchy list\n", nci);
+		for (vif = 0; vif < ECM_DB_MULTICAST_IF_MAX; vif++) {
+			to_first = ecm_db_multicast_if_first_get_at_index(to_list_first, vif);
+			*to_first = ECM_DB_IFACE_HEIRARCHY_MAX;
+		}
+
+		interface_idx_cnt = ecm_multicast_connection_to_interface_heirarchy_construct(feci, to_list, ip_src_addr, ip_dest_addr, in_dev,
+												  out_dev_master, if_cnt, dst_dev, to_list_first,
+												  src_node_addr, is_routed, layer4hdr, skb);
+		if (interface_idx_cnt == 0) {
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			kfree(to_list);
+			kfree(to_list_first);
+			DEBUG_WARN("%px: Failed to obtain mutlicast 'to' heirarchy list\n", nci);
+			goto done;
+		}
+		ret = ecm_db_multicast_connection_to_interfaces_reset(nci, to_list, to_list_first);
+		if (ret < 0) {
+			for (vif = 0; vif < ECM_DB_MULTICAST_IF_MAX; vif++) {
+				to_list_single = ecm_db_multicast_if_heirarchy_get(to_list, vif);
+				ecm_db_multicast_copy_if_heirarchy(to_list_temp, to_list_single);
+				to_first = ecm_db_multicast_if_first_get_at_index(to_list_first, vif);
+				ecm_db_connection_interfaces_deref(to_list_temp, *to_first);
+			}
+
+			feci->deref(feci);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			kfree(to_list);
+			kfree(to_list_first);
+			DEBUG_WARN("%px: Failed to obtain mutlicast 'to' heirarchy list\n", nci);
+			goto done;
+		}
+
+		DEBUG_TRACE("%px: Create destination node\n", nci);
+		ecm_db_multicast_copy_if_heirarchy(to_list_temp, to_list);
+		ni[ECM_DB_OBJ_DIR_TO] = ecm_multicast_ipv4_node_establish_and_ref(feci, out_dev, ip_dest_addr, to_list_temp, *to_list_first, dest_mac_addr, skb);
+
+		/*
+		 * De-ref the Multicast destination interface list
+		 */
+		for (vif = 0; vif < ECM_DB_MULTICAST_IF_MAX; vif++) {
+			to_list_single = ecm_db_multicast_if_heirarchy_get(to_list, vif);
+			ecm_db_multicast_copy_if_heirarchy(to_list_temp, to_list_single);
+			to_first = ecm_db_multicast_if_first_get_at_index(to_list_first, vif);
+			ecm_db_connection_interfaces_deref(to_list_temp, *to_first);
+		}
+
+		if (!ni[ECM_DB_OBJ_DIR_TO]) {
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			kfree(to_list);
+			kfree(to_list_first);
+			DEBUG_WARN("Failed to establish destination node\n");
+			goto done;
+		}
+		ni[ECM_DB_OBJ_DIR_TO_NAT] = ni[ECM_DB_OBJ_DIR_TO];
+
+		DEBUG_TRACE("%px: Create destination mapping\n", nci);
+		mi[ECM_DB_OBJ_DIR_TO] = ecm_ipv4_mapping_establish_and_ref(ip_dest_addr, dest_port);
+		if (!mi[ECM_DB_OBJ_DIR_TO]) {
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			kfree(to_list);
+			kfree(to_list_first);
+			DEBUG_WARN("Failed to establish dst mapping\n");
+			goto done;
+		}
+		mi[ECM_DB_OBJ_DIR_TO_NAT] = mi[ECM_DB_OBJ_DIR_TO];
+
+		DEBUG_TRACE("%px: Create the 'from NAT' interface heirarchy list\n", nci);
+		from_nat_list_first = ecm_interface_multicast_from_heirarchy_construct(feci, from_nat_list, ip_dest_addr, ip_src_addr_nat, 4, protocol, in_dev_nat, is_routed, in_dev_nat, src_node_addr, dest_node_addr, layer4hdr, skb);
+		if (from_nat_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			kfree(to_list);
+			kfree(to_list_first);
+			DEBUG_WARN("Failed to obtain 'from NAT' heirarchy list\n");
+			goto done;
+		}
+		ecm_db_connection_interfaces_reset(nci, from_nat_list, from_nat_list_first, ECM_DB_OBJ_DIR_FROM_NAT);
+
+		ni[ECM_DB_OBJ_DIR_FROM_NAT] = ecm_multicast_ipv4_node_establish_and_ref(feci, in_dev_nat, ip_src_addr_nat, from_nat_list, from_nat_list_first, src_node_addr, skb);
+		ecm_db_connection_interfaces_deref(from_nat_list, from_nat_list_first);
+		if (!ni[ECM_DB_OBJ_DIR_FROM_NAT]) {
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			kfree(to_list);
+			kfree(to_list_first);
+			DEBUG_WARN("Failed to obtain 'from NAT' node\n");
+			goto done;
+		}
+
+		DEBUG_TRACE("%px: Create from NAT mapping\n", nci);
+		mi[ECM_DB_OBJ_DIR_FROM_NAT] = ecm_ipv4_mapping_establish_and_ref(ip_src_addr_nat, src_port_nat);
+
+		if (!mi[ECM_DB_OBJ_DIR_FROM_NAT]) {
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM_NAT]);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			kfree(to_list);
+			kfree(to_list_first);
+			DEBUG_WARN("Failed to establish from nat mapping\n");
+			goto done;
+		}
+
+		/*
+		 * Every connection also needs a default classifier
+		 */
+		dci = ecm_classifier_default_instance_alloc(nci, protocol, ecm_dir, src_port, dest_port);
+		if (!dci) {
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM_NAT]);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM_NAT]);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			kfree(to_list);
+			kfree(to_list_first);
+			DEBUG_WARN("Failed to allocate default classifier\n");
+			goto done;
+		}
+		ecm_db_connection_classifier_assign(nci, (struct ecm_classifier_instance *)dci);
+
+		/*
+		 * Every connection starts with a full complement of classifiers assigned.
+		 * NOTE: Default classifier is a special case considered previously
+		 */
+		for (classifier_type = ECM_CLASSIFIER_TYPE_DEFAULT + 1; classifier_type < ECM_CLASSIFIER_TYPES; ++classifier_type) {
+			struct ecm_classifier_instance *aci = ecm_classifier_assign_classifier(nci, classifier_type);
+			if (aci) {
+				aci->deref(aci);
+			} else {
+				dci->base.deref((struct ecm_classifier_instance *)dci);
+				ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+				ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+				ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM_NAT]);
+				ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+				ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM_NAT]);
+				ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+				feci->deref(feci);
+				ecm_db_connection_deref(nci);
+				ecm_db_multicast_tuple_instance_deref(tuple_instance);
+				kfree(to_list);
+				kfree(to_list_first);
+				DEBUG_WARN("Failed to allocate classifiers assignments\n");
+				goto done;
+			}
+		}
+
+		ecm_db_front_end_instance_ref_and_set(nci, feci);
+
+		/*
+		 * Now add the connection into the database.
+		 * NOTE: In an SMP situation such as ours there is a possibility that more than one packet for the same
+		 * connection is being processed simultaneously.
+		 * We *could* end up creating more than one connection instance for the same actual connection.
+		 * To guard against this we now perform a mutex'd lookup of the connection + add once more - another cpu may have created it before us.
+		 */
+		spin_lock_bh(&ecm_ipv4_lock);
+		ci = ecm_db_connection_find_and_ref(ip_src_addr, ip_dest_addr, protocol, src_port, dest_port);
+		if (ci) {
+			/*
+			 * Another cpu created the same connection before us - use the one we just found
+			 */
+			spin_unlock_bh(&ecm_ipv4_lock);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			ecm_db_connection_deref(nci);
+		} else {
+			struct ecm_tracker_instance *ti;
+			ecm_db_timer_group_t tg;
+			ecm_tracker_sender_state_t src_state;
+			ecm_tracker_sender_state_t dest_state;
+			ecm_tracker_connection_state_t state;
+
+			/*
+			 * Ask tracker for timer group to set the connection to initially.
+			 */
+			ti = dci->tracker_get_and_ref(dci);
+			ti->state_get(ti, &src_state, &dest_state, &state, &tg);
+			ti->deref(ti);
+
+			/*
+			 * Add the new connection we created into the database
+			 * NOTE: assign to a short timer group for now - it is the assigned classifiers responsibility to do this
+			 */
+			ecm_db_connection_add(nci, mi, ni,
+					4, protocol, ecm_dir,
+					NULL /* final callback */,
+					defunct_callback,
+					tg, is_routed, nci);
+
+			/*
+			 * Add the tuple instance and attach it with connection instance
+			 */
+			ecm_db_multicast_tuple_instance_add(tuple_instance, nci);
+			spin_unlock_bh(&ecm_ipv4_lock);
+
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			ci = nci;
+
+			/*
+			 * Update the outdev_master in tuple_instance
+			 * Dereference: ecm_db_connection_deref()
+			 */
+			if (!is_routed) {
+				ecm_db_multicast_tuple_instance_set_and_hold_l2_br_dev(tuple_instance, out_dev_master);
+			}
+
+			DEBUG_INFO("%px: New UDP multicast connection created\n", ci);
+		}
+
+		/*
+		 * No longer need referenecs to the objects we created
+		 */
+		dci->base.deref((struct ecm_classifier_instance *)dci);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM_NAT]);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM_NAT]);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+		feci->deref(feci);
+		kfree(to_list);
+		kfree(to_list_first);
+	} else {
+		bool is_dest_interface_list_empty, routed;
+
+		is_dest_interface_list_empty = ecm_db_multicast_connection_to_interfaces_set_check(ci);
+		routed = ecm_db_connection_is_routed_get(ci);
+
+		/*
+		 * Check if there was an update to the 'routed' status for an existing flow.
+		 * This can happen if the flow is a bridge+route flow, and the MFC rule was not added
+		 * at the time the flow was originally created when the packet was processed by
+		 * the bridge hook. In this case, we defunct the flow to re-create it again
+		 */
+		if (routed != is_routed) {
+			ecm_db_connection_make_defunct(ci);
+			ecm_db_connection_deref(ci);
+			goto done;
+		}
+
+		/*
+		 * At this point the feci->accel_mode is DECEL because the MC connection has expired
+		 * and we had received a callback from MFC which had freed the multicast destination
+		 * interface heirarchy. In this case, we reconstruct the multicast destination interface
+		 * heirarchy and re-accelerate the connection.
+		 */
+		if (!is_dest_interface_list_empty) {
+			struct ecm_db_iface_instance *to_list;
+			struct ecm_db_iface_instance *to_list_temp[ECM_DB_IFACE_HEIRARCHY_MAX];
+			struct ecm_db_iface_instance *to_list_single;
+			int32_t *to_list_first;
+			int32_t *to_first;
+			int32_t i, interface_idx_cnt;
+			int ret;
+			struct ecm_front_end_connection_instance *feci;
+
+			to_list = (struct ecm_db_iface_instance *)kzalloc(ECM_DB_TO_MCAST_INTERFACES_SIZE, GFP_ATOMIC | __GFP_NOWARN);
+			if (!to_list) {
+				ecm_db_connection_deref(ci);
+				goto done;
+			}
+
+			to_list_first = (int32_t *)kzalloc(sizeof(int32_t *) * ECM_DB_MULTICAST_IF_MAX, GFP_ATOMIC | __GFP_NOWARN);
+			if (!to_list_first) {
+				ecm_db_connection_deref(ci);
+				kfree(to_list);
+				goto done;
+			}
+
+			/*
+			 * Reconstruct the multicast destination interface heirarchy.
+			 */
+			for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++ ) {
+				to_first = ecm_db_multicast_if_first_get_at_index(to_list_first, i);
+				*to_first = ECM_DB_IFACE_HEIRARCHY_MAX;
+			}
+
+			feci = ecm_db_connection_front_end_get_and_ref(ci);
+			interface_idx_cnt = ecm_multicast_connection_to_interface_heirarchy_construct(feci, to_list, ip_src_addr, ip_dest_addr, in_dev,
+					out_dev_master, if_cnt, dst_dev, to_list_first,
+					src_node_addr, is_routed, (__be16 *)&udp_hdr, skb);
+			feci->deref(feci);
+			if (interface_idx_cnt == 0) {
+				DEBUG_WARN("Failed to reconstruct 'to mc' heirarchy list\n");
+				ecm_db_connection_deref(ci);
+				kfree(to_list);
+				kfree(to_list_first);
+				goto done;
+			}
+
+			ret = ecm_db_multicast_connection_to_interfaces_reset(ci, to_list, to_list_first);
+
+			/*
+			 * De-ref the destination interface list
+			 */
+			for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+				to_list_single = ecm_db_multicast_if_heirarchy_get(to_list, i);
+				ecm_db_multicast_copy_if_heirarchy(to_list_temp, to_list_single);
+				to_first = ecm_db_multicast_if_first_get_at_index(to_list_first, i);
+				ecm_db_connection_interfaces_deref(to_list_temp, *to_first);
+			}
+
+			kfree(to_list);
+			kfree(to_list_first);
+
+			/*
+			 * If ret is less than zero than connection reset could not find memory for
+			 * to_mcast_interfaces. Deref the CI and retrun.
+			 */
+			if (ret < 0) {
+				ecm_db_connection_deref(ci);
+				goto done;
+			}
+		}
+	}
+
+	/*
+	 * if a bridge dev is present in the MFC destination then set the
+	 * ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG in tuple_instance
+	 */
+	if (br_dev_found_in_mfc) {
+		struct ecm_db_multicast_tuple_instance *tuple_instance;
+		tuple_instance = ecm_db_multicast_connection_find_and_ref(ip_src_addr, ip_dest_addr);
+		if (!tuple_instance) {
+			ecm_db_connection_deref(ci);
+			goto done;
+		}
+
+		ecm_db_multicast_tuple_instance_flags_set(tuple_instance, ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG);
+		ecm_db_multicast_connection_deref(tuple_instance);
+	}
+
+#if defined(CONFIG_NET_CLS_ACT) && defined(ECM_CLASSIFIER_DSCP_IGS) && defined(ECM_FRONT_END_NSS_ENABLE)
+	/*
+	 * Check if IGS feature is enabled or not.
+	 */
+	if (unlikely(ecm_interface_igs_enabled)) {
+		struct ecm_front_end_connection_instance *feci = ecm_db_connection_front_end_get_and_ref(ci);
+		if (feci->accel_engine == ECM_FRONT_END_ENGINE_NSS) {
+			if (!ecm_nss_common_igs_acceleration_is_allowed(feci, skb)) {
+				DEBUG_WARN("%px: Multicast IPv4 IGS acceleration denied.\n", ci);
+				feci->deref(feci);
+				ecm_db_connection_deref(ci);
+				goto done;
+			}
+		}
+		feci->deref(feci);
+	}
+#endif
+
+	/*
+	 * Keep connection alive as we have seen activity
+	 */
+	if (!ecm_db_connection_defunct_timer_touch(ci)) {
+		ecm_db_connection_deref(ci);
+		goto done;
+	}
+
+	/*
+	 * Identify which side of the connection is sending
+	 */
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, match_addr);
+	if (ECM_IP_ADDR_MATCH(ip_src_addr, match_addr)) {
+		sender = ECM_TRACKER_SENDER_TYPE_SRC;
+	} else {
+		sender = ECM_TRACKER_SENDER_TYPE_DEST;
+	}
+
+	/*
+	 * Do we need to action generation change?
+	 */
+	if (unlikely(ecm_db_connection_regeneration_required_check(ci))) {
+		ecm_multicast_ipv4_connection_regenerate(ci, sender, out_dev, in_dev, in_dev_nat);
+	}
+
+	/*
+	 * Iterate the assignments and call to process!
+	 * Policy implemented:
+	 * 1. Classifiers that say they are not relevant are unassigned and not actioned further.
+	 * 2. Any drop command from any classifier is honoured.
+	 * 3. All classifiers must action acceleration for accel to be honoured, any classifiers not sure of their relevance will stop acceleration.
+	 * 4. Only the highest priority classifier, that actions it, will have its qos tag honoured.
+	 * 5. Only the highest priority classifier, that actions it, will have its timer group honoured.
+	 */
+	DEBUG_TRACE("%px: process begin, skb: %px\n", ci, skb);
+	prevalent_pr.drop = false;
+	prevalent_pr.flow_qos_tag = skb->priority;
+	prevalent_pr.return_qos_tag = skb->priority;
+	prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+	prevalent_pr.timer_group = ci_orig_timer_group = ecm_db_connection_timer_group_get(ci);
+	prevalent_pr.process_actions = 0;
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_process_response aci_pr;
+		struct ecm_classifier_instance *aci;
+
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: process: %px, type: %d\n", ci, aci, aci->type_get(aci));
+		aci->process(aci, sender, iph, skb, &aci_pr);
+		DEBUG_TRACE("%px: aci_pr: process actions: %x, became relevant: %u, relevance: %d, drop: %d, "
+				"flow_qos_tag: %u, return_qos_tag: %u, accel_mode: %x, timer_group: %d\n",
+				ci, aci_pr.process_actions, aci_pr.became_relevant, aci_pr.relevance, aci_pr.drop,
+				aci_pr.flow_qos_tag, aci_pr.return_qos_tag, aci_pr.accel_mode, aci_pr.timer_group);
+
+		if (aci_pr.relevance == ECM_CLASSIFIER_RELEVANCE_NO) {
+			ecm_classifier_type_t aci_type;
+
+			/*
+			 * This classifier can be unassigned - PROVIDED it is not the default classifier
+			 */
+			aci_type = aci->type_get(aci);
+			if (aci_type == ECM_CLASSIFIER_TYPE_DEFAULT) {
+				continue;
+			}
+
+			DEBUG_INFO("%px: Classifier not relevant, unassign: %d", ci, aci_type);
+			ecm_db_connection_classifier_unassign(ci, aci);
+			continue;
+		}
+
+		/*
+		 * Yes or Maybe relevant.
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DROP) {
+			/*
+			 * Drop command from any classifier is actioned.
+			 */
+			DEBUG_TRACE("%px: wants drop: %px, type: %d, skb: %px\n", ci, aci, aci->type_get(aci), skb);
+			prevalent_pr.drop |= aci_pr.drop;
+		}
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+		/*
+		 * We do not accelerate if flow verification with OVS fails.
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_MCAST_DENY_ACCEL) {
+			DEBUG_TRACE("%px: wants deny acceleration: %px, type: %d, skb: %px\n", ci, aci, aci->type_get(aci), skb);
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_MCAST_DENY_ACCEL;
+		}
+#endif
+
+		/*
+		 * Accel mode permission
+		 */
+		if (aci_pr.relevance == ECM_CLASSIFIER_RELEVANCE_MAYBE) {
+			/*
+			 * Classifier not sure of its relevance - cannot accel yet
+			 */
+			DEBUG_TRACE("%px: accel denied by maybe: %px, type: %d\n", ci, aci, aci->type_get(aci));
+			prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+		} else {
+			if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE) {
+				if (aci_pr.accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_NO) {
+					DEBUG_TRACE("%px: accel denied: %px, type: %d\n", ci, aci, aci->type_get(aci));
+					prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+				}
+				/* else yes or don't care about accel */
+			}
+		}
+
+		/*
+		 * Timer group (the last classifier i.e. the highest priority one) will 'win'
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP) {
+			DEBUG_TRACE("%px: timer group: %px, type: %d, group: %d\n", ci, aci, aci->type_get(aci), aci_pr.timer_group);
+			prevalent_pr.timer_group = aci_pr.timer_group;
+		}
+
+		/*
+		 * Qos tag (the last classifier i.e. the highest priority one) will 'win'
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, flow qos tag: %u, return qos tag: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.flow_qos_tag, aci_pr.return_qos_tag);
+			prevalent_pr.flow_qos_tag = aci_pr.flow_qos_tag;
+			prevalent_pr.return_qos_tag = aci_pr.return_qos_tag;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG;
+		}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+#ifdef ECM_CLASSIFIER_DSCP_IGS
+		/*
+		 * Ingress QoS tag
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, ingress flow qos tag: %u, ingress return qos tag: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.igs_flow_qos_tag, aci_pr.igs_return_qos_tag);
+			prevalent_pr.igs_flow_qos_tag = aci_pr.igs_flow_qos_tag;
+			prevalent_pr.igs_return_qos_tag = aci_pr.igs_return_qos_tag;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG;
+		}
+#endif
+		/*
+		 * If any classifier denied DSCP remarking then that overrides every classifier
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, DSCP remark denied\n",
+					ci, aci, aci->type_get(aci));
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY;
+			prevalent_pr.process_actions &= ~ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+		}
+
+		/*
+		 * DSCP remark action, but only if it has not been denied by any classifier
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+			if (!(prevalent_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY)) {
+				DEBUG_TRACE("%px: aci: %px, type: %d, DSCP remark wanted, flow_dscp: %u, return dscp: %u\n",
+						ci, aci, aci->type_get(aci), aci_pr.flow_dscp, aci_pr.return_dscp);
+				prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+				prevalent_pr.flow_dscp = aci_pr.flow_dscp;
+				prevalent_pr.return_dscp = aci_pr.return_dscp;
+			}
+		}
+#endif
+
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+		/*
+		 * E-Mesh Service Prioritization is Valid
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, E-Mesh Service Prioritization is valid\n",
+					ci, aci, aci->type_get(aci));
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW;
+		}
+#endif
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG) {
+			int i;
+
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG;
+
+			/*
+			 * Set primary ingress VLAN tag
+			 */
+			prevalent_pr.ingress_vlan_tag[0] = aci_pr.ingress_vlan_tag[0];
+
+			for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+				prevalent_pr.egress_mc_vlan_tag[i][0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+				prevalent_pr.egress_mc_vlan_tag[i][1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+
+				/*
+				 * Set primary egress VLAN tag
+				 */
+				if (aci_pr.egress_mc_vlan_tag[i][0] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+					prevalent_pr.egress_mc_vlan_tag[i][0] = aci_pr.egress_mc_vlan_tag[i][0];
+				}
+			}
+		}
+
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG) {
+			int i;
+
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG;
+
+			/*
+			 * Set secondary ingress VLAN tag
+			 */
+			prevalent_pr.ingress_vlan_tag[1] = aci_pr.ingress_vlan_tag[1];
+
+			for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+				/*
+				 * Set secondary egress VLAN tag
+				 */
+				if (aci_pr.egress_mc_vlan_tag[i][1] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+					prevalent_pr.egress_mc_vlan_tag[i][1] = aci_pr.egress_mc_vlan_tag[i][1];
+				}
+			}
+		}
+#endif
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Change timer group?
+	 */
+	if (ci_orig_timer_group != prevalent_pr.timer_group) {
+		DEBUG_TRACE("%px: change timer group from: %d to: %d\n", ci, ci_orig_timer_group, prevalent_pr.timer_group);
+		ecm_db_connection_defunct_timer_reset(ci, prevalent_pr.timer_group);
+	}
+
+	/*
+	 * Drop?
+	 */
+	if (prevalent_pr.drop) {
+		DEBUG_TRACE("%px: drop: %px\n", ci, skb);
+		ecm_db_connection_data_totals_update_dropped(ci, (sender == ECM_TRACKER_SENDER_TYPE_SRC)? true : false, skb->len, 1);
+		ecm_db_connection_deref(ci);
+		goto done;
+	}
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+	/*
+	 * Defunct the connection if OVS classifer return deny acceleration.
+	 */
+	if (prevalent_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_MCAST_DENY_ACCEL) {
+		ecm_db_connection_make_defunct(ci);
+		ecm_db_connection_deref(ci);
+		goto done;
+	}
+#endif
+	ecm_db_multicast_connection_data_totals_update(ci, false, skb->len, 1);
+
+	/*
+	 * Accelerate?
+	 */
+	if (prevalent_pr.accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL) {
+		struct ecm_front_end_connection_instance *feci;
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+		feci->accelerate(feci, &prevalent_pr, false, NULL, NULL);
+		feci->deref(feci);
+	}
+	ecm_db_connection_deref(ci);
+
+done:
+	if (out_dev_master) {
+		dev_put(out_dev_master);
+	}
+	return NF_ACCEPT;
+}
diff --git a/qca-nss-ecm/frontends/cmn/ecm_multicast_ipv4.h b/qca-nss-ecm/frontends/cmn/ecm_multicast_ipv4.h
new file mode 100644
index 0000000..29c4697
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_multicast_ipv4.h
@@ -0,0 +1,24 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern unsigned int ecm_multicast_ipv4_connection_process(struct net_device *out_dev,
+							struct net_device *in_dev,
+							uint8_t *src_node_addr,
+							uint8_t *dest_node_addr,
+							bool can_accel, bool is_routed, struct sk_buff *skb,
+							struct ecm_tracker_ip_header *iph,
+							struct nf_conn *ct, ecm_tracker_sender_type_t sender,
+							struct nf_conntrack_tuple *orig_tuple, struct nf_conntrack_tuple *reply_tuple);
diff --git a/qca-nss-ecm/frontends/cmn/ecm_multicast_ipv6.c b/qca-nss-ecm/frontends/cmn/ecm_multicast_ipv6.c
new file mode 100644
index 0000000..e25318c
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_multicast_ipv6.c
@@ -0,0 +1,1455 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/debugfs.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/ip6_route.h>
+#include <net/ip6_fib.h>
+#include <net/addrconf.h>
+#include <net/ipv6.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in6.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/ppp_defs.h>
+#include <linux/mroute6.h>
+#include <linux/vmalloc.h>
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv6.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv6/nf_conntrack_ipv6.h>
+#include <net/netfilter/ipv6/nf_defrag_ipv6.h>
+#include <net/vxlan.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_MULTICAST_IPV6_DEBUG_LEVEL
+
+#include <nss_api_if.h>
+#include <mc_ecm.h>
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#include "ecm_nss_ipv6.h"
+#include "ecm_nss_multicast_ipv6.h"
+#include "ecm_nss_common.h"
+#include "ecm_front_end_common.h"
+#include "ecm_ipv6.h"
+#include "ecm_ae_classifier_public.h"
+#include "ecm_ae_classifier.h"
+
+/*
+ * ecm_multicast_ipv6_interface_heirarchy_construct()
+ *   Create destination multicast interface heirachy for Route/Bridge connection flow
+ */
+static int ecm_multicast_ipv6_interface_heirarchy_construct(struct ecm_front_end_connection_instance *feci,
+								struct ecm_db_iface_instance *interfaces, struct net_device *in_dev,
+								struct net_device *brdev, ip_addr_t packet_src_addr, ip_addr_t packet_dest_addr, uint8_t max_if,
+								uint32_t *dst_dev, int32_t *to_interface_first, uint8_t *src_node_addr, bool is_routed,
+								struct sk_buff *skb)
+{
+	int32_t iface_instance_cnt;
+
+	if (is_routed) {
+		iface_instance_cnt = ecm_interface_multicast_heirarchy_construct_routed(feci, interfaces, in_dev, packet_src_addr,
+											packet_dest_addr, max_if, dst_dev, to_interface_first,
+											false, NULL, skb);
+	} else {
+		iface_instance_cnt = ecm_interface_multicast_heirarchy_construct_bridged(feci, interfaces, brdev,
+											 packet_src_addr, packet_dest_addr, max_if,
+											 dst_dev, to_interface_first, src_node_addr, NULL, skb);
+	}
+	return iface_instance_cnt;
+}
+
+/*
+ * ecm_multicast_ipv6_connection_regenerate()
+ *	Re-generate a connection.
+ *
+ * Re-generating a connection involves re-evaluating the interface lists in case interface heirarchies have changed.
+ * It also involves the possible triggering of classifier re-evaluation but only if all currently assigned
+ * classifiers permit this operation.
+ */
+static void ecm_multicast_ipv6_connection_regenerate(struct ecm_db_connection_instance *ci, ecm_tracker_sender_type_t sender,
+							struct net_device *out_dev, struct net_device *in_dev)
+{
+	int i;
+	bool reclassify_allowed;
+	struct ecm_db_iface_instance *from_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+	int32_t from_list_first;
+	ip_addr_t ip_src_addr;
+	ip_addr_t ip_dest_addr;
+	int protocol;
+	bool is_routed;
+	uint8_t src_node_addr[ETH_ALEN];
+	uint8_t dest_node_addr[ETH_ALEN];
+	int assignment_count;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	struct ecm_front_end_connection_instance *feci;
+	__be16 layer4hdr[2] = {0, 0};
+	__be16 port = 0;
+
+	/*
+	 * Update the interface lists - these may have changed, e.g. LAG path change etc.
+	 * NOTE: We never have to change the usual mapping->host->node_iface arrangements for each side of the connection (to/from sides)
+	 * This is because if these interfaces change then the connection is dead anyway.
+	 * But a LAG slave might change the heirarchy the connection is using but the LAG master is still sane.
+	 * If any of the new interface heirarchies cannot be created then simply set empty-lists as this will deny
+	 * acceleration and ensure that a bad rule cannot be created.
+	 * IMPORTANT: The 'sender' defines who has sent the packet that triggered this re-generation
+	 */
+	protocol = ecm_db_connection_protocol_get(ci);
+	is_routed = ecm_db_connection_is_routed_get(ci);
+
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, ip_src_addr);
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_TO, ip_dest_addr);
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_node_addr);
+	ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_TO, dest_node_addr);
+
+	port = (__be16)(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+	layer4hdr[0] = htons(port);
+	port = (__be16)(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO));
+	layer4hdr[1] = htons(port);
+
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+	DEBUG_TRACE("%px: Update the 'from' interface heirarchy list\n", ci);
+	from_list_first = ecm_interface_multicast_from_heirarchy_construct(feci, from_list, ip_dest_addr, ip_src_addr, 6, protocol, in_dev, is_routed, in_dev, src_node_addr, dest_node_addr, layer4hdr, NULL);
+	if (from_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		goto ecm_multicast_ipv6_retry_regen;
+	}
+
+	ecm_db_connection_interfaces_reset(ci, from_list, from_list_first, ECM_DB_OBJ_DIR_FROM);
+	ecm_db_connection_interfaces_deref(from_list, from_list_first);
+
+	feci->deref(feci);
+
+	/*
+	 * Get list of assigned classifiers to reclassify.
+	 * Remember: This also includes our default classifier too.
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+
+	/*
+	 * All of the assigned classifiers must permit reclassification.
+	 */
+	reclassify_allowed = true;
+	for (i = 0; i < assignment_count; ++i) {
+		DEBUG_TRACE("%px: Calling to reclassify: %px, type: %d\n", ci, assignments[i], assignments[i]->type_get(assignments[i]));
+		if (!assignments[i]->reclassify_allowed(assignments[i])) {
+			DEBUG_TRACE("%px: reclassify denied: %px, by type: %d\n", ci, assignments[i], assignments[i]->type_get(assignments[i]));
+			reclassify_allowed = false;
+			break;
+		}
+	}
+
+	/*
+	 * Now we action any classifier re-classify
+	 */
+	if (!reclassify_allowed) {
+		/*
+		 * Regeneration came to a successful conclusion even though reclassification was denied
+		 */
+		DEBUG_WARN("%px: re-classify denied\n", ci);
+		goto ecm_multicast_ipv6_regen_done;
+	}
+
+	/*
+	 * Reclassify
+	 */
+	DEBUG_INFO("%px: reclassify\n", ci);
+	if (!ecm_classifier_reclassify(ci, assignment_count, assignments)) {
+		/*
+		 * We could not set up the classifiers to reclassify, it is safer to fail out and try again next time
+		 */
+		DEBUG_WARN("%px: Regeneration: reclassify failed\n", ci);
+		goto ecm_multicast_ipv6_regen_done;
+	}
+	DEBUG_INFO("%px: reclassify success\n", ci);
+
+ecm_multicast_ipv6_regen_done:
+
+	/*
+	 * Release the assignments
+	 */
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Re-generation of state is successful.
+	 */
+	ecm_db_connection_regeneration_completed(ci);
+
+	return;
+
+ecm_multicast_ipv6_retry_regen:
+	feci->deref(feci);
+	ecm_db_connection_regeneration_failed(ci);
+	return;
+}
+
+/*
+ * ecm_multicast_ipv6_node_establish_and_ref()
+ *	Returns a reference to a node, possibly creating one if necessary.
+ *
+ * The given_node_addr will be used if provided.
+ *
+ * Returns NULL on failure.
+ *
+ * TODO: This function should be removed and the one in the ecm_ipv6.c file should be used
+ *	instead of this one when the multicast code is fixed to use the new interface hierarchy
+ *	construction model.
+ */
+static struct ecm_db_node_instance *ecm_multicast_ipv6_node_establish_and_ref(struct ecm_front_end_connection_instance *feci,
+							struct net_device *dev, ip_addr_t addr,
+							struct ecm_db_iface_instance *interface_list[], int32_t interface_list_first,
+							uint8_t *given_node_addr, struct sk_buff *skb)
+{
+	struct ecm_db_node_instance *ni;
+	struct ecm_db_node_instance *nni;
+	struct ecm_db_iface_instance *ii;
+	int i;
+	bool done;
+	uint8_t node_addr[ETH_ALEN];
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+	ip_addr_t remote_ip;
+#endif
+
+	DEBUG_INFO("Establish node for " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr));
+
+	/*
+	 * The node is the datalink address, typically a MAC address.
+	 * However the node address to use is not always obvious and depends on the interfaces involved.
+	 * For example if the interface is PPPoE then we use the MAC of the PPPoE server as we cannot use normal ARP resolution.
+	 * Not all hosts have a node address, where there is none, a suitable alternative should be located and is typically based on 'addr'
+	 * or some other datalink session information.
+	 * It should be, at a minimum, something that ties the host with the interface.
+	 *
+	 * Iterate from 'inner' to 'outer' interfaces - discover what the node is.
+	 */
+	memset(node_addr, 0, ETH_ALEN);
+	done = false;
+	if (given_node_addr) {
+		memcpy(node_addr, given_node_addr, ETH_ALEN);
+		done = true;
+		DEBUG_TRACE("Using given node address: %pM\n", node_addr);
+	}
+	for (i = ECM_DB_IFACE_HEIRARCHY_MAX - 1; (!done) && (i >= interface_list_first); i--) {
+		ecm_db_iface_type_t type;
+		ip_addr_t gw_addr = ECM_IP_ADDR_NULL;
+		bool on_link = false;
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+		struct ecm_db_interface_info_pppoe pppoe_info;
+#endif
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+		struct ecm_db_interface_info_pppol2tpv2 pppol2tpv2_info;
+#endif
+		type = ecm_db_iface_type_get(interface_list[i]);
+		DEBUG_INFO("Lookup node address, interface @ %d is type: %d\n", i, type);
+
+		switch (type) {
+
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * Node address is the address of the remote PPPoE server
+			 */
+			ecm_db_iface_pppoe_session_info_get(interface_list[i], &pppoe_info);
+			memcpy(node_addr, pppoe_info.remote_mac, ETH_ALEN);
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("PPPoE interface unsupported\n");
+			return NULL;
+#endif
+
+		case ECM_DB_IFACE_TYPE_SIT:
+		case ECM_DB_IFACE_TYPE_TUNIPIP6:
+			done = true;
+			break;
+
+		case ECM_DB_IFACE_TYPE_PPPOL2TPV2:
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+			ecm_db_iface_pppol2tpv2_session_info_get(interface_list[i], &pppol2tpv2_info);
+			ECM_HIN4_ADDR_TO_IP_ADDR(remote_ip, pppol2tpv2_info.ip.daddr);
+			if (unlikely(!ecm_interface_mac_addr_get(remote_ip, node_addr, &on_link, gw_addr))) {
+				DEBUG_TRACE("Failed to obtain mac for host " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr));
+				return NULL;
+			}
+			done = true;
+			break;
+#else
+			DEBUG_TRACE("PPPoL2TPV2 interface unsupported\n");
+			return NULL;
+#endif
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			/*
+			 * VLAN handled same along with bridge etc.
+			 */
+#else
+			DEBUG_TRACE("VLAN interface unsupported\n");
+			return NULL;
+#endif
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+		case ECM_DB_IFACE_TYPE_LAG:
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#endif
+			if (!ecm_interface_mac_addr_get(addr, node_addr, &on_link, gw_addr)) {
+				DEBUG_TRACE("Failed to obtain mac for host " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr));
+
+				/*
+				 * If there is a gw_addr found during the lookup, use that address
+				 * for neighbour solicitation request.
+				 */
+				if (!ECM_IP_ADDR_IS_NULL(gw_addr)) {
+					ECM_IP_ADDR_COPY(addr, gw_addr);
+				}
+
+				if (ecm_front_end_is_bridge_port(dev)) {
+					struct net_device *master;
+					master = ecm_interface_get_and_hold_dev_master(dev);
+					DEBUG_ASSERT(master, "Expected a master\n");
+					ecm_interface_send_neighbour_solicitation(master, addr);
+					dev_put(master);
+				} else {
+					ecm_interface_send_neighbour_solicitation(dev, addr);
+				}
+				return NULL;
+			}
+			if (is_multicast_ether_addr(node_addr)) {
+				DEBUG_TRACE("multicast node address for host " ECM_IP_ADDR_OCTAL_FMT ", node_addr: %pM\n", ECM_IP_ADDR_TO_OCTAL(addr), node_addr);
+				return NULL;
+			}
+
+			done = true;
+			break;
+		default:
+			/*
+			 * Don't know how to handle these.
+			 * Just copy some part of the address for now, but keep iterating the interface list
+			 * in the hope something recognisable will be seen!
+			 * GGG TODO We really need to roll out support for all interface types we can deal with ASAP :-(
+			 */
+			memcpy(node_addr, (uint8_t *)addr, ETH_ALEN);
+		}
+	}
+	if (!done) {
+		DEBUG_INFO("Failed to establish node for " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr));
+		return NULL;
+	}
+
+	/*
+	 * Establish iface
+	 */
+	ii = ecm_interface_establish_and_ref(feci, dev, skb);
+	if (!ii) {
+		DEBUG_WARN("Failed to establish iface\n");
+		return NULL;
+	}
+
+	/*
+	 * Locate the node
+	 */
+	ni = ecm_db_node_find_and_ref(node_addr, ii);
+	if (ni) {
+		DEBUG_TRACE("%px: node established\n", ni);
+		ecm_db_iface_deref(ii);
+		return ni;
+	}
+
+	/*
+	 * No node - create one
+	 */
+	nni = ecm_db_node_alloc();
+	if (!nni) {
+		DEBUG_WARN("Failed to establish node\n");
+		ecm_db_iface_deref(ii);
+		return NULL;
+	}
+
+	/*
+	 * Add node into the database, atomically to avoid races creating the same thing
+	 */
+	spin_lock_bh(&ecm_ipv6_lock);
+	ni = ecm_db_node_find_and_ref(node_addr, ii);
+	if (ni) {
+		spin_unlock_bh(&ecm_ipv6_lock);
+		ecm_db_node_deref(nni);
+		ecm_db_iface_deref(ii);
+		return ni;
+	}
+
+	ecm_db_node_add(nni, ii, node_addr, NULL, nni);
+	spin_unlock_bh(&ecm_ipv6_lock);
+
+	/*
+	 * Don't need iface instance now
+	 */
+	ecm_db_iface_deref(ii);
+
+	DEBUG_TRACE("%px: node established\n", nni);
+	return nni;
+}
+
+/*
+ * ecm_multicast_ipv6_connection_process()
+ *	Process a UDP Multicast packet
+ */
+unsigned int ecm_multicast_ipv6_connection_process(struct net_device *out_dev,
+							struct net_device *in_dev,
+							uint8_t *src_node_addr,
+							uint8_t *dest_node_addr,
+							bool can_accel, bool is_routed, struct sk_buff *skb,
+							struct ecm_tracker_ip_header *iph,
+							struct nf_conn *ct, ecm_tracker_sender_type_t sender,
+							struct nf_conntrack_tuple *orig_tuple, struct nf_conntrack_tuple *reply_tuple)
+{
+	struct udphdr *udp_hdr;
+	struct udphdr udp_hdr_buff;
+	struct in6_addr origin6;
+	struct in6_addr group6;
+	struct ecm_db_multicast_tuple_instance *tuple_instance;
+	int src_port;
+	int dest_port;
+	struct ecm_db_connection_instance *ci;
+	ecm_db_direction_t ecm_dir = ECM_DB_DIRECTION_NON_NAT;
+	ip_addr_t match_addr;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int32_t mc_if_cnt;
+	int assignment_count;
+	ecm_db_timer_group_t ci_orig_timer_group;
+	struct ecm_classifier_process_response prevalent_pr;
+	ip_addr_t ip_src_addr;
+	ip_addr_t ip_dest_addr;
+	uint32_t mc_dest_if[ECM_DB_MULTICAST_IF_MAX];
+	bool br_dev_found_in_mfc = false;
+	int protocol = (int)orig_tuple->dst.protonum;
+	__be16 *layer4hdr = NULL;
+	struct net_device *out_dev_master = NULL;
+
+	if (protocol != IPPROTO_UDP) {
+		DEBUG_WARN("Invalid Protocol %d in skb %px\n", protocol, skb);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Extract UDP header to obtain port information
+	 */
+	udp_hdr = ecm_tracker_udp_check_header_and_read(skb, iph, &udp_hdr_buff);
+	if (unlikely(!udp_hdr)) {
+		DEBUG_WARN("Invalid UDP header in skb %px\n", skb);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Return if source dev is any tunnel type
+	 *
+	 * Acceleration for multicast packet which is sent to
+	 * or received from VxLAN tunnel net device should be skipped.
+	 */
+	if ((in_dev->type == ECM_ARPHRD_IPSEC_TUNNEL_TYPE) ||
+	    (in_dev->type == ARPHRD_SIT) || (in_dev->type == ARPHRD_PPP) ||
+	    (in_dev->type == ARPHRD_TUNNEL6) ||
+	    (netif_is_vxlan(in_dev)) || (netif_is_vxlan(out_dev))) {
+		DEBUG_TRACE("in_dev: %px, in_type: %d, out_dev: %px, out_type: %d",
+				in_dev, in_dev->type, out_dev, out_dev->type);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Now extract information, if we have conntrack then use that (which would already be in the tuples)
+	 */
+	if (unlikely(!ct)) {
+		orig_tuple->src.u.udp.port = udp_hdr->source;
+		orig_tuple->dst.u.udp.port = udp_hdr->dest;
+		reply_tuple->src.u.udp.port = udp_hdr->dest;
+		reply_tuple->dst.u.udp.port = udp_hdr->source;
+	}
+
+	layer4hdr = (__be16*)udp_hdr;
+	/*
+	 * Extract transport port information
+	 * Refer to the ecm_ipv6_process() for information on how we extract this information.
+	 */
+	src_port = ntohs(orig_tuple->src.u.udp.port);
+	dest_port = ntohs(orig_tuple->dst.u.udp.port);
+
+	ECM_NIN6_ADDR_TO_IP_ADDR(ip_src_addr, orig_tuple->src.u3.in6);
+	ECM_NIN6_ADDR_TO_IP_ADDR(ip_dest_addr, orig_tuple->dst.u3.in6);
+
+	/*
+	 * Query MFC/Bridge Snooper to access the destination interface list.
+	 */
+	ECM_IP_ADDR_TO_NIN6_ADDR(origin6, ip_src_addr);
+	ECM_IP_ADDR_TO_NIN6_ADDR(group6, ip_dest_addr);
+
+	memset(mc_dest_if, 0, sizeof(mc_dest_if));
+
+	mc_if_cnt =  ip6mr_find_mfc_entry(&init_net, &origin6, &group6, ECM_DB_MULTICAST_IF_MAX, mc_dest_if);
+
+	/*
+	 * Skip PPP interface
+	 */
+	if (ecm_interface_multicast_is_iface_type(mc_dest_if, mc_if_cnt, ARPHRD_PPP)) {
+		DEBUG_TRACE("%px: Packet is of type PPP; skip it\n", skb);
+		return NF_ACCEPT;
+	}
+
+	if (is_routed) {
+		/*
+		 * This is a routed flow, hence look for a valid MFC rule
+		 */
+		if (mc_if_cnt <= 0){
+			DEBUG_WARN("Not found a valid vif count %d\n", mc_if_cnt);
+			return NF_ACCEPT;
+		}
+	}
+
+	/*
+	 * For "bridge + route" scenario, we can receive packet from both bridge and route hook.
+	 * If MFC returns valid interface count (mc_if_cnt), then we need to check for "bridge + route"
+	 * scenario.
+	 */
+	if (mc_if_cnt > 0) {
+		is_routed = true;
+
+		/*
+		 * Check for the presence of a bridge device in the destination
+		 * interface list given to us by MFC
+		 */
+		br_dev_found_in_mfc = ecm_interface_multicast_check_for_br_dev(mc_dest_if, mc_if_cnt);
+
+		/*
+		 * We are processing a routed multicast flow.
+		 * Check if the source interface is a bridge device. If this is the case,
+		 * this flow could be a "bridge + route" flow.
+		 * So, we query the bridge device as well for possible joinees
+		 */
+		if (ecm_front_end_is_bridge_device(in_dev)
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+				|| ecm_front_end_is_ovs_bridge_device(in_dev)
+#endif
+		   ) {
+			int32_t mc_if_cnt_bridge;
+			uint32_t dst_dev_bridge[ECM_DB_MULTICAST_IF_MAX];
+
+			memset(dst_dev_bridge, 0, sizeof(dst_dev_bridge));
+			mc_if_cnt_bridge = mc_bridge_ipv6_get_if(in_dev, &origin6, &group6, ECM_DB_MULTICAST_IF_MAX, dst_dev_bridge);
+			if (mc_if_cnt_bridge <= 0) {
+				DEBUG_WARN("%px: No bridge ports have joined multicast group\n", ci);
+				goto process_packet;
+			}
+
+			/*
+			 * Check for max interface limit.
+			 */
+			if (mc_if_cnt == ECM_DB_MULTICAST_IF_MAX) {
+				DEBUG_WARN("Interface count reached max limit: %d. Could not handle the connection", mc_if_cnt);
+				goto done;
+			}
+
+			/*
+			 * Update the dst_dev with in_dev as it is a bridge + route case
+			 */
+			mc_dest_if[mc_if_cnt++] = in_dev->ifindex;
+			br_dev_found_in_mfc = true;
+		}
+
+		goto process_packet;
+	}
+
+	/*
+	 * Packet flow is pure bridge. Try to query the snooper for the destination
+	 * interface list
+	 */
+	out_dev_master =  ecm_interface_get_and_hold_dev_master(out_dev);
+	DEBUG_ASSERT(out_dev_master, "Expected a master\n");
+	mc_if_cnt = mc_bridge_ipv6_get_if(out_dev_master, &origin6, &group6, ECM_DB_MULTICAST_IF_MAX, mc_dest_if);
+	if (mc_if_cnt <= 0) {
+		DEBUG_WARN("Not found a valid MCS if count %d\n", mc_if_cnt);
+		goto done;
+	}
+
+	/*
+	 * The source interface could have joined the group as well.
+	 * In such cases, the destination interface list returned by
+	 * the snooper would include the source interface as well.
+	 * We need to filter the source interface from the list in such cases.
+	 */
+	mc_if_cnt = ecm_interface_multicast_check_for_src_ifindex(mc_dest_if, mc_if_cnt, in_dev->ifindex);
+	if (mc_if_cnt <= 0) {
+		DEBUG_WARN("Not found a valid MCS if count %d\n", mc_if_cnt);
+		goto done;
+	}
+
+process_packet:
+	DEBUG_TRACE("UDP src: " ECM_IP_ADDR_OCTAL_FMT ":%d, dest: " ECM_IP_ADDR_OCTAL_FMT ":%d\n",
+			ECM_IP_ADDR_TO_OCTAL(ip_src_addr), src_port, ECM_IP_ADDR_TO_OCTAL(ip_dest_addr), dest_port);
+
+	/*
+	 * Look up a connection
+	 */
+	ci = ecm_db_connection_find_and_ref(ip_src_addr, ip_dest_addr, IPPROTO_UDP, src_port, dest_port);
+
+	/*
+	 * If there is no existing connection then create a new one.
+	 */
+	if (unlikely(!ci)) {
+		struct ecm_db_mapping_instance *mi[ECM_DB_OBJ_DIR_MAX];
+		struct ecm_db_node_instance *ni[ECM_DB_OBJ_DIR_MAX];
+		struct ecm_classifier_default_instance *dci;
+		struct ecm_front_end_connection_instance *feci;
+		struct ecm_db_connection_instance *nci;
+		struct ecm_db_iface_instance *from_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+		struct ecm_db_iface_instance *to_list;
+		struct ecm_db_iface_instance *to_list_single;
+		struct ecm_db_iface_instance *to_list_temp[ECM_DB_IFACE_HEIRARCHY_MAX];
+		ecm_classifier_type_t classifier_type;
+		int32_t *to_list_first;
+		int32_t *to_first;
+		int32_t from_list_first;
+		int32_t interface_idx_cnt = 0;
+		int vif;
+		int ret;
+		char dest_mac_addr[6];
+		enum ecm_front_end_type fe_type;
+		ecm_ae_classifier_result_t ae_result;
+		ecm_db_connection_defunct_callback_t defunct_callback;
+
+		DEBUG_TRACE("New UDP connection from " ECM_IP_ADDR_OCTAL_FMT ":%u to " ECM_IP_ADDR_OCTAL_FMT ":%u\n",
+				ECM_IP_ADDR_TO_OCTAL(ip_src_addr), src_port, ECM_IP_ADDR_TO_OCTAL(ip_dest_addr), dest_port);
+
+		/*
+		 * Before we attempt to create the connection are we being terminated?
+		 */
+		spin_lock_bh(&ecm_ipv6_lock);
+		if (ecm_ipv6_terminate_pending) {
+			spin_unlock_bh(&ecm_ipv6_lock);
+			DEBUG_WARN("Terminating\n");
+
+			/*
+			 * As we are terminating we just allow the packet to pass - it's no longer our concern
+			 */
+			goto done;
+		}
+		spin_unlock_bh(&ecm_ipv6_lock);
+
+		/*
+		 * Connection must have a front end instance associated with it
+		 */
+		fe_type = ecm_front_end_type_get();
+		switch (fe_type) {
+#if defined(ECM_FRONT_END_NSS_ENABLE) && defined(ECM_FRONT_END_SFE_ENABLE)
+		case ECM_FRONT_END_TYPE_HYBRID:
+		{
+			ecm_ae_classifier_get_t ae_get;
+			struct ecm_ae_classifier_info ae_info;
+
+			ecm_ae_classifier_select_info_fill(ip_src_addr, ip_dest_addr,
+							  src_port, dest_port, protocol, 6,
+							  is_routed, true,
+							  &ae_info);
+
+			rcu_read_lock();
+			ae_get = rcu_dereference(ae_ops.ae_get);
+			ae_result = ae_get(&ae_info);
+			rcu_read_unlock();
+
+			DEBUG_TRACE("front end type hybrid, ae_result: %d\n", ae_result);
+			break;
+		}
+#endif
+#ifdef ECM_FRONT_END_NSS_ENABLE
+		case ECM_FRONT_END_TYPE_NSS:
+			DEBUG_TRACE("front end type NSS, ae_result: %d\n", ae_result);
+			ae_result = ECM_AE_CLASSIFIER_RESULT_NSS;
+			break;
+#endif
+#ifdef ECM_FRONT_END_SFE_ENABLE
+		case ECM_FRONT_END_TYPE_SFE:
+			/*
+			 * Fall through. Not supporting multicast acceleration yet.
+			 */
+#endif
+		default:
+			DEBUG_WARN("front end type: %d is not supported\n", fe_type);
+			goto done;
+		}
+
+		/*
+		 * Check the ae_result.
+		 * 1. If NSS, allocate NSS ipv6 multicast connection instance
+		 * 2. If NONE, allocate NSS ipv6 multicast connection instance with can_accel flag is set to false.
+		 *    By doing this ECM will not ask again and again to the external module. If external module wants to
+		 *    accelerate this flow later, the flow needs to be defuncted first.
+		 * 3. If NOT_YET, the connection will not be allocated in the database and the next flow will be asked again
+		 *    to the external module.
+		 * 4. If any other type is returned, ASSERT.
+		 */
+		switch (ae_result) {
+#ifdef ECM_FRONT_END_NSS_ENABLE
+		case ECM_AE_CLASSIFIER_RESULT_NSS:
+			defunct_callback = ecm_nss_multicast_ipv6_connection_defunct_callback;
+			feci = (struct ecm_front_end_connection_instance *)ecm_nss_multicast_ipv6_connection_instance_alloc(can_accel, &nci);
+			break;
+
+		case ECM_AE_CLASSIFIER_RESULT_NONE:
+			defunct_callback = ecm_nss_multicast_ipv6_connection_defunct_callback;
+			feci = (struct ecm_front_end_connection_instance *)ecm_nss_multicast_ipv6_connection_instance_alloc(false, &nci);
+			break;
+#endif
+		case ECM_AE_CLASSIFIER_RESULT_NOT_YET:
+			goto done;
+
+		default:
+			DEBUG_ASSERT(NULL, "unexpected ae_result: %d\n", ae_result);
+		}
+
+		if (!feci) {
+			DEBUG_WARN("Failed to allocate front end\n");
+			goto done;
+		}
+
+		/*
+		 * Create a tuple instance
+		 */
+		tuple_instance = ecm_db_multicast_tuple_instance_alloc(ip_src_addr, ip_dest_addr, src_port, dest_port);
+		if (!tuple_instance) {
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			DEBUG_WARN("Failed to allocate tuple instance\n");
+			goto done;
+		}
+		/*
+		 * Create Destination MAC address using IP multicast destination address
+		 */
+		ecm_translate_multicast_mac(ip_dest_addr, dest_mac_addr);
+
+		/*
+		 * Get the src and destination mappings
+		 * For this we also need the interface lists which we also set upon the new connection while we are at it.
+		 * GGG TODO rework terms of "src/dest" - these need to be named consistently as from/to as per database terms.
+		 * GGG TODO The empty list checks should not be needed, mapping_establish_and_ref() should fail out if there is no list anyway.
+		 */
+		DEBUG_TRACE("%px: Create the 'from' interface heirarchy list\n", nci);
+		from_list_first = ecm_interface_multicast_from_heirarchy_construct(feci, from_list, ip_dest_addr, ip_src_addr, 6, IPPROTO_UDP, in_dev, is_routed, in_dev, src_node_addr, dest_node_addr, layer4hdr, skb);
+		if (from_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			DEBUG_WARN("Failed to obtain 'from' heirarchy list\n");
+			goto done;
+		}
+		ecm_db_connection_interfaces_reset(nci, from_list, from_list_first, ECM_DB_OBJ_DIR_FROM);
+
+		DEBUG_TRACE("%px: Create source node\n", nci);
+		ni[ECM_DB_OBJ_DIR_FROM] = ecm_multicast_ipv6_node_establish_and_ref(feci, in_dev, ip_src_addr, from_list, from_list_first, src_node_addr, skb);
+		ecm_db_connection_interfaces_deref(from_list, from_list_first);
+		if (!ni[ECM_DB_OBJ_DIR_FROM]) {
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			DEBUG_WARN("Failed to establish source node\n");
+			goto done;
+		}
+		ni[ECM_DB_OBJ_DIR_FROM_NAT] = ni[ECM_DB_OBJ_DIR_FROM];
+
+		DEBUG_TRACE("%px: Create source mapping\n", nci);
+		mi[ECM_DB_OBJ_DIR_FROM] = ecm_ipv6_mapping_establish_and_ref(ip_src_addr, src_port);
+		if (!mi[ECM_DB_OBJ_DIR_FROM]) {
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			DEBUG_WARN("Failed to establish src mapping\n");
+			goto done;
+		}
+		mi[ECM_DB_OBJ_DIR_FROM_NAT] = mi[ECM_DB_OBJ_DIR_FROM];
+
+		DEBUG_TRACE("%px: Create the 'to' interface heirarchy list\n", nci);
+
+		to_list = (struct ecm_db_iface_instance *)kzalloc(ECM_DB_TO_MCAST_INTERFACES_SIZE, GFP_ATOMIC | __GFP_NOWARN);
+		if (!to_list) {
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			goto done;
+		}
+
+		to_list_first = (int32_t *)kzalloc(sizeof(int32_t *) * ECM_DB_MULTICAST_IF_MAX, GFP_ATOMIC | __GFP_NOWARN);
+		if (!to_list_first) {
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			kfree(to_list);
+			goto done;
+		}
+
+		/*
+		 * Create the multicast 'to' interface heirarchy
+		 */
+		DEBUG_TRACE("%px: Create the multicast  'to' interface heirarchy list\n", nci);
+		for (vif = 0; vif < ECM_DB_MULTICAST_IF_MAX; vif++) {
+			to_first = ecm_db_multicast_if_first_get_at_index(to_list_first, vif);
+			*to_first = ECM_DB_IFACE_HEIRARCHY_MAX;
+		}
+
+		interface_idx_cnt = ecm_multicast_ipv6_interface_heirarchy_construct(feci, to_list, in_dev, out_dev_master, ip_src_addr,
+										ip_dest_addr, mc_if_cnt, mc_dest_if, to_list_first, src_node_addr,  is_routed, skb);
+		if (interface_idx_cnt == 0) {
+			DEBUG_WARN("Failed to obtain 'to' heirarchy list\n");
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			kfree(to_list);
+			kfree(to_list_first);
+			goto done;
+		}
+
+		ret = ecm_db_multicast_connection_to_interfaces_reset(nci, to_list, to_list_first);
+		if (ret < 0) {
+			for (vif = 0; vif < ECM_DB_MULTICAST_IF_MAX; vif++) {
+				to_list_single = ecm_db_multicast_if_heirarchy_get(to_list, vif);
+				ecm_db_multicast_copy_if_heirarchy(to_list_temp, to_list_single);
+				to_first = ecm_db_multicast_if_first_get_at_index(to_list_first, vif);
+				ecm_db_connection_interfaces_deref(to_list_temp, *to_first);
+			}
+
+			feci->deref(feci);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			kfree(to_list);
+			kfree(to_list_first);
+			DEBUG_WARN("Failed to obtain 'to' heirarchy list\n");
+			goto done;
+		}
+
+		/*
+		 * De-ref the destination interface list
+		 */
+		for (vif = 0; vif < ECM_DB_MULTICAST_IF_MAX; vif++) {
+			to_list_single = ecm_db_multicast_if_heirarchy_get(to_list, vif);
+			ecm_db_multicast_copy_if_heirarchy(to_list_temp, to_list_single);
+			to_first = ecm_db_multicast_if_first_get_at_index(to_list_first, vif);
+			ecm_db_connection_interfaces_deref(to_list_temp, *to_first);
+		}
+
+		DEBUG_TRACE("%px: Create dest node\n", nci);
+		ecm_db_multicast_copy_if_heirarchy(to_list_temp, to_list);
+		ni[ECM_DB_OBJ_DIR_TO] = ecm_multicast_ipv6_node_establish_and_ref(feci, out_dev, ip_dest_addr, to_list_temp, *to_list_first, dest_mac_addr, skb);
+		if (!ni[ECM_DB_OBJ_DIR_TO]) {
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			kfree(to_list);
+			kfree(to_list_first);
+			DEBUG_WARN("Failed to establish dest node\n");
+			goto done;
+		}
+		ni[ECM_DB_OBJ_DIR_TO_NAT] = ni[ECM_DB_OBJ_DIR_TO];
+
+		DEBUG_TRACE("%px: Create dest mapping\n", nci);
+		mi[ECM_DB_OBJ_DIR_TO] = ecm_ipv6_mapping_establish_and_ref(ip_dest_addr, dest_port);
+		if (!mi[ECM_DB_OBJ_DIR_TO]) {
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			kfree(to_list);
+			kfree(to_list_first);
+			DEBUG_WARN("Failed to establish dest mapping\n");
+			goto done;
+		}
+		mi[ECM_DB_OBJ_DIR_TO_NAT] = mi[ECM_DB_OBJ_DIR_TO];
+
+		/*
+		 * Every connection also needs a default classifier
+		 */
+		dci = ecm_classifier_default_instance_alloc(nci, IPPROTO_UDP, ecm_dir, src_port, dest_port);
+		if (!dci) {
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+			ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+			ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+			feci->deref(feci);
+			ecm_db_connection_deref(nci);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			kfree(to_list);
+			kfree(to_list_first);
+			DEBUG_WARN("Failed to allocate default classifier\n");
+			goto done;
+		}
+		ecm_db_connection_classifier_assign(nci, (struct ecm_classifier_instance *)dci);
+
+		/*
+		 * Every connection starts with a full complement of classifiers assigned.
+		 * NOTE: Default classifier is a special case considered previously
+		 */
+		for (classifier_type = ECM_CLASSIFIER_TYPE_DEFAULT + 1; classifier_type < ECM_CLASSIFIER_TYPES; ++classifier_type) {
+			struct ecm_classifier_instance *aci = ecm_classifier_assign_classifier(nci, classifier_type);
+			if (aci) {
+				aci->deref(aci);
+			} else {
+				dci->base.deref((struct ecm_classifier_instance *)dci);
+				ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+				ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+				ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+				ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+				feci->deref(feci);
+				ecm_db_connection_deref(nci);
+				ecm_db_multicast_tuple_instance_deref(tuple_instance);
+				kfree(to_list);
+				kfree(to_list_first);
+				DEBUG_WARN("Failed to allocate classifiers assignments\n");
+				goto done;
+			}
+		}
+
+		ecm_db_front_end_instance_ref_and_set(nci, feci);
+
+		/*
+		 * Now add the connection into the database.
+		 * NOTE: In an SMP situation such as ours there is a possibility that more than one packet for the same
+		 * connection is being processed simultaneously.
+		 * We *could* end up creating more than one connection instance for the same actual connection.
+		 * To guard against this we now perform a mutex'd lookup of the connection + add once more - another cpu may have created it before us.
+		 */
+		spin_lock_bh(&ecm_ipv6_lock);
+		ci = ecm_db_connection_find_and_ref(ip_src_addr, ip_dest_addr, IPPROTO_UDP, src_port, dest_port);
+		if (ci) {
+			/*
+			 * Another cpu created the same connection before us - use the one we just found
+			 */
+			spin_unlock_bh(&ecm_ipv6_lock);
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			ecm_db_connection_deref(nci);
+		} else {
+			struct ecm_tracker_instance *ti;
+			ecm_db_timer_group_t tg;
+			ecm_tracker_sender_state_t src_state;
+			ecm_tracker_sender_state_t dest_state;
+			ecm_tracker_connection_state_t state;
+
+			/*
+			 * Ask tracker for timer group to set the connection to initially.
+			 */
+			ti = dci->tracker_get_and_ref(dci);
+			ti->state_get(ti, &src_state, &dest_state, &state, &tg);
+			ti->deref(ti);
+
+			/*
+			 * Add the new connection we created into the database
+			 * NOTE: assign to a short timer group for now - it is the assigned classifiers responsibility to do this
+			 */
+			ecm_db_connection_add(nci, mi, ni,
+					6, IPPROTO_UDP, ecm_dir,
+					NULL /* final callback */,
+					defunct_callback,
+					tg, is_routed, nci);
+
+			/*
+			 * Add the tuple instance and attach it with connection instance
+			 */
+			ecm_db_multicast_tuple_instance_add(tuple_instance, nci);
+			spin_unlock_bh(&ecm_ipv6_lock);
+
+			ecm_db_multicast_tuple_instance_deref(tuple_instance);
+			ci = nci;
+			/*
+			 * Update the outdev_master in CI
+			 * Dereference: ecm_db_connection_deref()
+			 */
+			if (!is_routed) {
+				ecm_db_multicast_tuple_instance_set_and_hold_l2_br_dev(tuple_instance, out_dev_master);
+			}
+			DEBUG_INFO("%px: New UDP connection created\n", ci);
+		}
+
+		/*
+		 * No longer need referenecs to the objects we created
+		 */
+		dci->base.deref((struct ecm_classifier_instance *)dci);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+		feci->deref(feci);
+		kfree(to_list);
+		kfree(to_list_first);
+
+	} else {
+		bool is_dest_interface_list_empty, routed;
+
+		is_dest_interface_list_empty = ecm_db_multicast_connection_to_interfaces_set_check(ci);
+		routed = ecm_db_connection_is_routed_get(ci);
+
+		/*
+		 * Check if there was an update to the 'routed' status for an existing flow.
+		 * This can happen if the flow is a bridge+route flow, and the MFC rule was not added
+		 * at the time the flow was originally created when the packet was processed by the
+		 * bridge hook. In this case, we defunct the flow to re-create it again.
+		 */
+		if (routed != is_routed) {
+			ecm_db_connection_make_defunct(ci);
+			ecm_db_connection_deref(ci);
+			goto done;
+		}
+
+		/*
+		 * At this point the feci->accel_mode is DECEL because the
+		 * MC connection has expired and we had received a callback from MFC which had freed the
+		 * multicast destination interface heirarchy. In this case, we reconstruct the multicast
+		 * destination interface heirarchy and re-accelerate the connection.
+		 */
+		if (!is_dest_interface_list_empty) {
+			struct ecm_db_iface_instance *to_list;
+			struct ecm_db_iface_instance *to_list_temp[ECM_DB_IFACE_HEIRARCHY_MAX];
+			struct ecm_db_iface_instance *to_list_single;
+			int32_t *to_list_first;
+			int32_t *to_first;
+			int32_t i, interface_idx_cnt;
+			int ret;
+			struct ecm_front_end_connection_instance *feci;
+
+			to_list = (struct ecm_db_iface_instance *)kzalloc(ECM_DB_TO_MCAST_INTERFACES_SIZE, GFP_ATOMIC | __GFP_NOWARN);
+			if (!to_list) {
+				ecm_db_connection_deref(ci);
+				goto done;
+			}
+
+			to_list_first = (int32_t *)kzalloc(sizeof(int32_t *) * ECM_DB_MULTICAST_IF_MAX, GFP_ATOMIC | __GFP_NOWARN);
+			if (!to_list_first) {
+				ecm_db_connection_deref(ci);
+				kfree(to_list);
+				goto done;
+			}
+
+			for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+				to_first = ecm_db_multicast_if_first_get_at_index(to_list_first, i);
+				*to_first = ECM_DB_IFACE_HEIRARCHY_MAX;
+			}
+
+			feci = ecm_db_connection_front_end_get_and_ref(ci);
+			interface_idx_cnt = ecm_multicast_ipv6_interface_heirarchy_construct(feci, to_list, in_dev, out_dev_master,\
+					ip_src_addr, ip_dest_addr, mc_if_cnt,\
+					mc_dest_if, to_list_first, src_node_addr,
+					is_routed, skb);
+			feci->deref(feci);
+			if (interface_idx_cnt == 0) {
+				DEBUG_WARN("Failed to reconstruct 'to mc' heirarchy list\n");
+				ecm_db_connection_deref(ci);
+				kfree(to_list);
+				kfree(to_list_first);
+				goto done;
+			}
+
+			ret = ecm_db_multicast_connection_to_interfaces_reset(ci, to_list, to_list_first);
+
+			/*
+			 * De-ref the destination interface list
+			 */
+			for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+				to_list_single = ecm_db_multicast_if_heirarchy_get(to_list, i);
+				ecm_db_multicast_copy_if_heirarchy(to_list_temp, to_list_single);
+				to_first = ecm_db_multicast_if_first_get_at_index(to_list_first, i);
+				ecm_db_connection_interfaces_deref(to_list_temp, *to_first);
+			}
+
+			kfree(to_list);
+			kfree(to_list_first);
+
+			/*
+			 * If ret is less than zero than connection reset could not find memory for
+			 * to_mcast_interfaces. Deref the CI and retrun.
+			 */
+			if (ret < 0) {
+				ecm_db_connection_deref(ci);
+				goto done;
+			}
+		}
+	}
+
+	/*
+	 * if a bridge dev is present in the MFC destination then set the
+	 * ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG in tuple_instance
+	 */
+	if (br_dev_found_in_mfc) {
+		struct ecm_db_multicast_tuple_instance *tuple_instance;
+		tuple_instance = ecm_db_multicast_connection_find_and_ref(ip_src_addr, ip_dest_addr);
+		if (!tuple_instance) {
+			ecm_db_connection_deref(ci);
+			goto done;
+		}
+
+		ecm_db_multicast_tuple_instance_flags_set(tuple_instance, ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG);
+		ecm_db_multicast_connection_deref(tuple_instance);
+	}
+
+#if defined(CONFIG_NET_CLS_ACT) && defined(ECM_CLASSIFIER_DSCP_IGS) && defined(ECM_FRONT_END_NSS_ENABLE)
+	/*
+	 * Check if IGS feature is enabled or not.
+	 */
+	if (unlikely(ecm_interface_igs_enabled)) {
+		struct ecm_front_end_connection_instance *feci = ecm_db_connection_front_end_get_and_ref(ci);
+		if (feci->accel_engine == ECM_FRONT_END_ENGINE_NSS) {
+			if (!ecm_nss_common_igs_acceleration_is_allowed(feci, skb)) {
+				DEBUG_WARN("%px: Multicast IPv6 IGS acceleration denied.\n", ci);
+				feci->deref(feci);
+				ecm_db_connection_deref(ci);
+				goto done;
+			}
+		}
+		feci->deref(feci);
+	}
+#endif
+
+	/*
+	 * Keep connection alive as we have seen activity
+	 */
+	if (!ecm_db_connection_defunct_timer_touch(ci)) {
+		ecm_db_connection_deref(ci);
+		goto done;
+	}
+
+	/*
+	 * Identify which side of the connection is sending
+	 */
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, match_addr);
+	if (ECM_IP_ADDR_MATCH(ip_src_addr, match_addr)) {
+		sender = ECM_TRACKER_SENDER_TYPE_SRC;
+	} else {
+		sender = ECM_TRACKER_SENDER_TYPE_DEST;
+	}
+
+	/*
+	 * Do we need to action generation change?
+	 */
+	if (unlikely(ecm_db_connection_regeneration_required_check(ci))) {
+		ecm_multicast_ipv6_connection_regenerate(ci, sender, out_dev, in_dev);
+	}
+
+	/*
+	 * Iterate the assignments and call to process!
+	 * Policy implemented:
+	 * 1. Classifiers that say they are not relevant are unassigned and not actioned further.
+	 * 2. Any drop command from any classifier is honoured.
+	 * 3. All classifiers must action acceleration for accel to be honoured, any classifiers not sure of their relevance will stop acceleration.
+	 * 4. Only the highest priority classifier, that actions it, will have its qos tag honoured.
+	 * 5. Only the highest priority classifier, that actions it, will have its timer group honoured.
+	 */
+	DEBUG_TRACE("%px: process begin, skb: %px\n", ci, skb);
+	prevalent_pr.drop = false;
+	prevalent_pr.flow_qos_tag = skb->priority;
+	prevalent_pr.return_qos_tag = skb->priority;
+	prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+	prevalent_pr.timer_group = ci_orig_timer_group = ecm_db_connection_timer_group_get(ci);
+	prevalent_pr.process_actions = 0;
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_process_response aci_pr;
+		struct ecm_classifier_instance *aci;
+
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: process: %px, type: %d\n", ci, aci, aci->type_get(aci));
+		aci->process(aci, sender, iph, skb, &aci_pr);
+		DEBUG_TRACE("%px: aci_pr: process actions: %x, became relevant: %u, relevance: %d, drop: %d, "
+				"flow_qos_tag: %u, return_qos_tag: %u, accel_mode: %x, timer_group: %d\n",
+				ci, aci_pr.process_actions, aci_pr.became_relevant, aci_pr.relevance, aci_pr.drop,
+				aci_pr.flow_qos_tag, aci_pr.return_qos_tag, aci_pr.accel_mode, aci_pr.timer_group);
+
+		if (aci_pr.relevance == ECM_CLASSIFIER_RELEVANCE_NO) {
+			ecm_classifier_type_t aci_type;
+
+			/*
+			 * This classifier can be unassigned - PROVIDED it is not the default classifier
+			 */
+			aci_type = aci->type_get(aci);
+			if (aci_type == ECM_CLASSIFIER_TYPE_DEFAULT) {
+				continue;
+			}
+
+			DEBUG_INFO("%px: Classifier not relevant, unassign: %d", ci, aci_type);
+			ecm_db_connection_classifier_unassign(ci, aci);
+			continue;
+		}
+
+		/*
+		 * Yes or Maybe relevant.
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DROP) {
+			/*
+			 * Drop command from any classifier is actioned.
+			 */
+			DEBUG_TRACE("%px: wants drop: %px, type: %d, skb: %px\n", ci, aci, aci->type_get(aci), skb);
+			prevalent_pr.drop |= aci_pr.drop;
+		}
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_MCAST_DENY_ACCEL) {
+			/*
+			 * We do not accelerate if flow verification with OVS fails.
+			 */
+			DEBUG_TRACE("%px: wants deny acceleration: %px, type: %d, skb: %px\n", ci, aci, aci->type_get(aci), skb);
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_MCAST_DENY_ACCEL;
+		}
+#endif
+
+		/*
+		 * Accel mode permission
+		 */
+		if (aci_pr.relevance == ECM_CLASSIFIER_RELEVANCE_MAYBE) {
+			/*
+			 * Classifier not sure of its relevance - cannot accel yet
+			 */
+			DEBUG_TRACE("%px: accel denied by maybe: %px, type: %d\n", ci, aci, aci->type_get(aci));
+			prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+		} else {
+			if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE) {
+				if (aci_pr.accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_NO) {
+					DEBUG_TRACE("%px: accel denied: %px, type: %d\n", ci, aci, aci->type_get(aci));
+					prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+				}
+				/* else yes or don't care about accel */
+			}
+		}
+
+		/*
+		 * Timer group (the last classifier i.e. the highest priority one) will 'win'
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP) {
+			DEBUG_TRACE("%px: timer group: %px, type: %d, group: %d\n", ci, aci, aci->type_get(aci), aci_pr.timer_group);
+			prevalent_pr.timer_group = aci_pr.timer_group;
+		}
+
+		/*
+		 * Qos tag (the last classifier i.e. the highest priority one) will 'win'
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, flow qos tag: %u, return qos tag: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.flow_qos_tag, aci_pr.return_qos_tag);
+			prevalent_pr.flow_qos_tag = aci_pr.flow_qos_tag;
+			prevalent_pr.return_qos_tag = aci_pr.return_qos_tag;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG;
+		}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+#ifdef ECM_CLASSIFIER_DSCP_IGS
+		/*
+		 * Ingress QoS tag
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, ingress flow qos tag: %u, ingress return qos tag: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.igs_flow_qos_tag, aci_pr.igs_return_qos_tag);
+			prevalent_pr.igs_flow_qos_tag = aci_pr.igs_flow_qos_tag;
+			prevalent_pr.igs_return_qos_tag = aci_pr.igs_return_qos_tag;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG;
+		}
+#endif
+		/*
+		 * If any classifier denied DSCP remarking then that overrides every classifier
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, DSCP remark denied\n",
+					ci, aci, aci->type_get(aci));
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY;
+			prevalent_pr.process_actions &= ~ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+		}
+
+		/*
+		 * DSCP remark action, but only if it has not been denied by any classifier
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+			if (!(prevalent_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY)) {
+				DEBUG_TRACE("%px: aci: %px, type: %d, DSCP remark wanted, flow_dscp: %u, return dscp: %u\n",
+						ci, aci, aci->type_get(aci), aci_pr.flow_dscp, aci_pr.return_dscp);
+				prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+				prevalent_pr.flow_dscp = aci_pr.flow_dscp;
+				prevalent_pr.return_dscp = aci_pr.return_dscp;
+			}
+		}
+#endif
+
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+		/*
+		 * E-Mesh Service Prioritization is Valid
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, E-Mesh Service Prioritization is valid\n",
+					ci, aci, aci->type_get(aci));
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW;
+		}
+#endif
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG) {
+			int i;
+
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG;
+
+			/*
+			 * Set primary ingress VLAN tag
+			 */
+			prevalent_pr.ingress_vlan_tag[0] = aci_pr.ingress_vlan_tag[0];
+
+			for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+				prevalent_pr.egress_mc_vlan_tag[i][0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+				prevalent_pr.egress_mc_vlan_tag[i][1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+
+				/*
+				 * Set primary egress VLAN tag
+				 */
+				if (aci_pr.egress_mc_vlan_tag[i][0] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+					prevalent_pr.egress_mc_vlan_tag[i][0] = aci_pr.egress_mc_vlan_tag[i][0];
+				}
+			}
+		}
+
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG) {
+			int i;
+
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG;
+
+			/*
+			 * Set secondary ingress VLAN tag
+			 */
+			prevalent_pr.ingress_vlan_tag[1] = aci_pr.ingress_vlan_tag[1];
+
+			for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+				/*
+				 * Set secondary egress VLAN tag
+				 */
+				if (aci_pr.egress_mc_vlan_tag[i][1] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+					prevalent_pr.egress_mc_vlan_tag[i][1] = aci_pr.egress_mc_vlan_tag[i][1];
+				}
+			}
+		}
+#endif
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Change timer group?
+	 */
+	if (ci_orig_timer_group != prevalent_pr.timer_group) {
+		DEBUG_TRACE("%px: change timer group from: %d to: %d\n", ci, ci_orig_timer_group, prevalent_pr.timer_group);
+		ecm_db_connection_defunct_timer_reset(ci, prevalent_pr.timer_group);
+	}
+
+	/*
+	 * Drop?
+	 */
+	if (prevalent_pr.drop) {
+		DEBUG_TRACE("%px: drop: %px\n", ci, skb);
+		ecm_db_connection_data_totals_update_dropped(ci, (sender == ECM_TRACKER_SENDER_TYPE_SRC)? true : false, skb->len, 1);
+		ecm_db_connection_deref(ci);
+		goto done;
+	}
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+	/*
+	 * Defunct the connection if OVS classifer return deny acceleration.
+	 */
+	if (prevalent_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_MCAST_DENY_ACCEL) {
+		ecm_db_connection_make_defunct(ci);
+		ecm_db_connection_deref(ci);
+		goto done;
+	}
+#endif
+	ecm_db_connection_data_totals_update(ci, (sender == ECM_TRACKER_SENDER_TYPE_SRC)? true : false, skb->len, 1);
+
+	/*
+	 * Assign qos tag
+	 * GGG TODO Should we use sender to identify whether to use flow or return qos tag?
+	 */
+	skb->priority = prevalent_pr.flow_qos_tag;
+	DEBUG_TRACE("%px: skb priority: %u\n", ci, skb->priority);
+
+	/*
+	 * Accelerate?
+	 */
+	if (prevalent_pr.accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL) {
+		struct ecm_front_end_connection_instance *feci;
+		DEBUG_TRACE("%px: accel\n", ci);
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+		feci->accelerate(feci, &prevalent_pr, false, NULL, NULL);
+		feci->deref(feci);
+	}
+	ecm_db_connection_deref(ci);
+
+done:
+	if (out_dev_master) {
+		dev_put(out_dev_master);
+	}
+	return NF_ACCEPT;
+}
diff --git a/qca-nss-ecm/frontends/cmn/ecm_multicast_ipv6.h b/qca-nss-ecm/frontends/cmn/ecm_multicast_ipv6.h
new file mode 100644
index 0000000..2c688c8
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_multicast_ipv6.h
@@ -0,0 +1,24 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern unsigned int ecm_multicast_ipv6_connection_process(struct net_device *out_dev,
+							struct net_device *in_dev,
+							uint8_t *src_node_addr,
+							uint8_t *dest_node_addr,
+							bool can_accel, bool is_routed, struct sk_buff *skb,
+							struct ecm_tracker_ip_header *iph,
+							struct nf_conn *ct, ecm_tracker_sender_type_t sender,
+							struct nf_conntrack_tuple *orig_tuple, struct nf_conntrack_tuple *reply_tuple);
diff --git a/qca-nss-ecm/frontends/cmn/ecm_non_ported_ipv4.c b/qca-nss-ecm/frontends/cmn/ecm_non_ported_ipv4.c
new file mode 100644
index 0000000..c28f770
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_non_ported_ipv4.c
@@ -0,0 +1,842 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <net/addrconf.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_NON_PORTED_IPV4_DEBUG_LEVEL
+
+#ifdef ECM_FRONT_END_NSS_ENABLE
+#include <nss_api_if.h>
+#endif
+#ifdef ECM_FRONT_END_SFE_ENABLE
+#include <sfe_api.h>
+#endif
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#ifdef ECM_FRONT_END_NSS_ENABLE
+#include "ecm_nss_non_ported_ipv4.h"
+#include "ecm_nss_ipv4.h"
+#include "ecm_nss_common.h"
+#endif
+#ifdef ECM_FRONT_END_SFE_ENABLE
+#include "ecm_sfe_non_ported_ipv4.h"
+#include "ecm_sfe_ipv4.h"
+#include "ecm_sfe_common.h"
+#endif
+#include "ecm_front_end_common.h"
+#include "ecm_ipv4.h"
+#include "ecm_ae_classifier_public.h"
+#include "ecm_ae_classifier.h"
+
+/*
+ * ecm_non_ported_ipv4_is_protocol_supported()
+ *	Return true if IPv4 protocol is supported in non-ported acceleration.
+ */
+static inline bool ecm_non_ported_ipv4_is_protocol_supported(int protocol)
+{
+	switch (protocol) {
+	case IPPROTO_IPV6:
+	case IPPROTO_ESP:
+#if defined(ECM_INTERFACE_PPTP_ENABLE) || defined(ECM_INTERFACE_GRE_TAP_ENABLE) || defined(ECM_INTERFACE_GRE_TUN_ENABLE)
+	case IPPROTO_GRE:
+#endif
+	case IPPROTO_RAW:
+		return true;
+	}
+	return false;
+}
+
+/*
+ * ecm_non_ported_ipv4_process()
+ *	Process a protocol that does not have port based identifiers
+ */
+unsigned int ecm_non_ported_ipv4_process(struct net_device *out_dev, struct net_device *out_dev_nat,
+							struct net_device *in_dev, struct net_device *in_dev_nat,
+							uint8_t *src_node_addr, uint8_t *src_node_addr_nat,
+							uint8_t *dest_node_addr, uint8_t *dest_node_addr_nat,
+							bool can_accel, bool is_routed, bool is_l2_encap, struct sk_buff *skb,
+							struct ecm_tracker_ip_header *ip_hdr,
+							struct nf_conn *ct, ecm_tracker_sender_type_t sender, ecm_db_direction_t ecm_dir,
+							struct nf_conntrack_tuple *orig_tuple, struct nf_conntrack_tuple *reply_tuple,
+							ip_addr_t ip_src_addr, ip_addr_t ip_dest_addr, ip_addr_t ip_src_addr_nat, ip_addr_t ip_dest_addr_nat,
+							uint16_t l2_encap_proto)
+{
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	int protocol;
+	int src_port;
+	int src_port_nat;
+	int dest_port;
+	int dest_port_nat;
+	ip_addr_t match_addr;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	ecm_db_timer_group_t ci_orig_timer_group;
+	struct ecm_classifier_process_response prevalent_pr;
+	bool pppoe_bridged = false;
+
+	/*
+	 * Look up a connection.
+	 */
+	protocol = (int)orig_tuple->dst.protonum;
+	src_port = 0;
+	src_port_nat = 0;
+	dest_port = 0;
+	dest_port_nat = 0;
+
+	/*
+	 * We are not yet supporting PPPOE bridge for SFE.
+	 * TODO: Revisit when we want to add that support.
+	 */
+#ifdef ECM_FRONT_END_NSS_ENABLE
+	if (unlikely(!is_routed &&
+			(l2_encap_proto == ETH_P_PPP_SES) &&
+			(nss_pppoe_get_br_accel_mode() == NSS_PPPOE_BR_ACCEL_MODE_EN_3T))) {
+		struct pppoe_hdr *ph;
+		uint32_t l2_encap_len = ecm_front_end_l2_encap_header_len(l2_encap_proto);
+
+		/*
+		 * Get PPPoE session id from skb.
+		 */
+		ecm_front_end_push_l2_encap_header(skb, l2_encap_len);
+		ph = pppoe_hdr(skb);
+		DEBUG_TRACE("PPPoE session ID: %x\n", ntohs(ph->sid));
+		src_port = ntohs(ph->sid);
+		protocol = IPPROTO_RAW;
+		src_port_nat = src_port;
+		dest_port = src_port;
+		dest_port_nat = src_port;
+		ecm_front_end_pull_l2_encap_header(skb, l2_encap_len);
+		pppoe_bridged = true;
+	}
+#endif
+
+	if(!ecm_non_ported_ipv4_is_protocol_supported(protocol)) {
+		DEBUG_TRACE("Unsupported non-ported protocol: %d, do not process.\n", protocol);
+		return NF_ACCEPT;
+	}
+
+	DEBUG_TRACE("Non ported src: " ECM_IP_ADDR_DOT_FMT "(" ECM_IP_ADDR_DOT_FMT "), dest: " ECM_IP_ADDR_DOT_FMT "(" ECM_IP_ADDR_DOT_FMT "), dir %d\n",
+				ECM_IP_ADDR_TO_DOT(ip_src_addr), ECM_IP_ADDR_TO_DOT(ip_src_addr_nat), ECM_IP_ADDR_TO_DOT(ip_dest_addr),
+				ECM_IP_ADDR_TO_DOT(ip_dest_addr_nat), ecm_dir);
+
+	ci = ecm_db_connection_find_and_ref(ip_src_addr, ip_dest_addr, protocol, src_port, dest_port);
+
+	/*
+	 * If there is no existing connection then create a new one.
+	 */
+	if (unlikely(!ci)) {
+		struct ecm_db_mapping_instance *mi[ECM_DB_OBJ_DIR_MAX];
+		struct ecm_db_node_instance *ni[ECM_DB_OBJ_DIR_MAX];
+		struct ecm_classifier_default_instance *dci;
+		struct ecm_db_connection_instance *nci;
+		ecm_classifier_type_t classifier_type;
+		int32_t to_list_first;
+		struct ecm_db_iface_instance *to_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+		int32_t to_nat_list_first;
+		struct ecm_db_iface_instance *to_nat_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+		int32_t from_list_first;
+		struct ecm_db_iface_instance *from_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+		int32_t from_nat_list_first;
+		struct ecm_db_iface_instance *from_nat_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+		struct ecm_front_end_interface_construct_instance efeici;
+		enum ecm_front_end_type fe_type;
+		ecm_ae_classifier_result_t ae_result;
+		ecm_db_connection_defunct_callback_t defunct_callback;
+
+		DEBUG_INFO("New non-ported connection from " ECM_IP_ADDR_DOT_FMT ":%u to " ECM_IP_ADDR_DOT_FMT ":%u protocol: %d\n",
+				ECM_IP_ADDR_TO_DOT(ip_src_addr), src_port, ECM_IP_ADDR_TO_DOT(ip_dest_addr), dest_port, protocol);
+
+		/*
+		 * Before we attempt to create the connection are we being terminated?
+		 */
+		spin_lock_bh(&ecm_ipv4_lock);
+		if (ecm_ipv4_terminate_pending) {
+			spin_unlock_bh(&ecm_ipv4_lock);
+			DEBUG_WARN("Terminating\n");
+
+			/*
+			 * As we are terminating we just allow the packet to pass - it's no longer our concern
+			 */
+			return NF_ACCEPT;
+		}
+		spin_unlock_bh(&ecm_ipv4_lock);
+
+		/*
+		 * Connection must have a front end instance associated with it
+		 */
+		fe_type = ecm_front_end_type_get();
+		switch (fe_type) {
+#if defined(ECM_FRONT_END_NSS_ENABLE) && defined(ECM_FRONT_END_SFE_ENABLE)
+		case ECM_FRONT_END_TYPE_HYBRID:
+		{
+			ecm_ae_classifier_get_t ae_get;
+			struct ecm_ae_classifier_info ae_info;
+
+			ecm_ae_classifier_select_info_fill(ip_src_addr, ip_dest_addr,
+							  src_port, dest_port, protocol, 4,
+							  is_routed, false,
+							  &ae_info);
+
+			rcu_read_lock();
+			ae_get = rcu_dereference(ae_ops.ae_get);
+			ae_result = ae_get(&ae_info);
+			rcu_read_unlock();
+
+			DEBUG_TRACE("front end type hybrid, ae_result: %d\n", ae_result);
+			break;
+		}
+#endif
+#ifdef ECM_FRONT_END_NSS_ENABLE
+		case ECM_FRONT_END_TYPE_NSS:
+			ae_result = ECM_AE_CLASSIFIER_RESULT_NSS;
+			DEBUG_TRACE("front end type NSS, ae_result: %d\n", ae_result);
+			break;
+#endif
+#ifdef ECM_FRONT_END_SFE_ENABLE
+		case ECM_FRONT_END_TYPE_SFE:
+			ae_result = ECM_AE_CLASSIFIER_RESULT_SFE;
+			DEBUG_TRACE("front end type SFE, ae_result: %d\n", ae_result);
+			break;
+#endif
+		default:
+			DEBUG_WARN("front end type: %d is not supported\n", fe_type);
+			return NF_ACCEPT;
+		}
+
+		/*
+		 * Check the ae_result.
+		 * 1. If NSS, allocate NSS ipv4 non-ported connection instance
+		 * 2. If NONE, allocate NSS ipv4 non-ported connection instance with can_accel flag is set to false.
+		 *    By doing this ECM will not ask again and again to the external module. If external module wants to
+		 *    accelerate this flow later, the flow needs to be defuncted first.
+		 * 3. If NOT_YET, the connection will not be allocated in the database and the next flow will be asked again
+		 *    to the external module.
+		 * 4. If any other type is returned, ASSERT.
+		 */
+		switch (ae_result) {
+#ifdef ECM_FRONT_END_NSS_ENABLE
+		case ECM_AE_CLASSIFIER_RESULT_NSS:
+			if (!ecm_nss_feature_check(skb, ip_hdr)) {
+				DEBUG_WARN("Unsupported feature found for NSS acceleration\n");
+				return NF_ACCEPT;
+			}
+			defunct_callback = ecm_nss_non_ported_ipv4_connection_defunct_callback;
+			feci = (struct ecm_front_end_connection_instance *)ecm_nss_non_ported_ipv4_connection_instance_alloc(can_accel, protocol, &nci);
+			break;
+
+		case ECM_AE_CLASSIFIER_RESULT_NONE:
+			defunct_callback = ecm_nss_non_ported_ipv4_connection_defunct_callback;
+			feci = (struct ecm_front_end_connection_instance *)ecm_nss_non_ported_ipv4_connection_instance_alloc(false, protocol, &nci);
+			break;
+#endif
+#ifdef ECM_FRONT_END_SFE_ENABLE
+		case ECM_AE_CLASSIFIER_RESULT_SFE:
+			defunct_callback = ecm_sfe_non_ported_ipv4_connection_defunct_callback;
+			feci = (struct ecm_front_end_connection_instance *)ecm_sfe_non_ported_ipv4_connection_instance_alloc(can_accel, protocol, &nci);
+			break;
+#endif
+		case ECM_AE_CLASSIFIER_RESULT_NOT_YET:
+			return NF_ACCEPT;
+
+		default:
+			DEBUG_ASSERT(NULL, "unexpected ae_result: %d\n", ae_result);
+		}
+
+		if (!feci) {
+			DEBUG_WARN("Failed to allocate front end\n");
+			return NF_ACCEPT;
+		}
+
+		if (!ecm_front_end_ipv4_interface_construct_set_and_hold(skb, sender, ecm_dir, is_routed,
+							in_dev, out_dev,
+							ip_src_addr, ip_src_addr_nat,
+							ip_dest_addr, ip_dest_addr_nat,
+							&efeici)) {
+			DEBUG_WARN("ECM front end ipv4 interface construct set failed for routed traffic\n");
+			goto fail_1;
+		}
+
+		/*
+		 * Get the src and destination mappings.
+		 * For this we also need the interface lists which we also set upon the new connection while we are at it.
+		 * GGG TODO rework terms of "src/dest" - these need to be named consistently as from/to as per database terms.
+		 * GGG TODO The empty list checks should not be needed, mapping_establish_and_ref() should fail out if there is no list anyway.
+		 */
+		DEBUG_TRACE("%px: Create the 'from' interface heirarchy list\n", nci);
+		from_list_first = ecm_interface_heirarchy_construct(feci, from_list, efeici.from_dev, efeici.from_other_dev, ip_dest_addr, efeici.from_mac_lookup_ip_addr, ip_src_addr, 4, protocol, in_dev, is_routed, in_dev, src_node_addr, dest_node_addr, NULL, skb, NULL);
+		if (from_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			DEBUG_WARN("Failed to obtain 'from' heirarchy list\n");
+			goto fail_2;
+		}
+		ecm_db_connection_interfaces_reset(nci, from_list, from_list_first, ECM_DB_OBJ_DIR_FROM);
+
+		DEBUG_TRACE("%px: Create source node\n", nci);
+		ni[ECM_DB_OBJ_DIR_FROM] = ecm_ipv4_node_establish_and_ref(feci, efeici.from_dev, efeici.from_mac_lookup_ip_addr, from_list, from_list_first, src_node_addr, skb);
+		ecm_db_connection_interfaces_deref(from_list, from_list_first);
+		if (!ni[ECM_DB_OBJ_DIR_FROM]) {
+			DEBUG_WARN("Failed to establish source node\n");
+			goto fail_2;
+		}
+
+		DEBUG_TRACE("%px: Create source mapping\n", nci);
+		mi[ECM_DB_OBJ_DIR_FROM] = ecm_ipv4_mapping_establish_and_ref(ip_src_addr, src_port);
+		if (!mi[ECM_DB_OBJ_DIR_FROM]) {
+			DEBUG_WARN("Failed to establish src mapping\n");
+			goto fail_3;
+		}
+
+		DEBUG_TRACE("%px: Create the 'to' interface heirarchy list\n", nci);
+		to_list_first = ecm_interface_heirarchy_construct(feci, to_list, efeici.to_dev, efeici.to_other_dev, ip_src_addr, efeici.to_mac_lookup_ip_addr, ip_dest_addr, 4, protocol, out_dev, is_routed, in_dev, dest_node_addr, src_node_addr, NULL, skb, NULL);
+		if (to_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			DEBUG_WARN("Failed to obtain 'to' heirarchy list\n");
+			goto fail_4;
+		}
+		ecm_db_connection_interfaces_reset(nci, to_list, to_list_first, ECM_DB_OBJ_DIR_TO);
+
+		DEBUG_TRACE("%px: Create dest node\n", nci);
+		ni[ECM_DB_OBJ_DIR_TO] = ecm_ipv4_node_establish_and_ref(feci, efeici.to_dev, efeici.to_mac_lookup_ip_addr, to_list, to_list_first, dest_node_addr, skb);
+		ecm_db_connection_interfaces_deref(to_list, to_list_first);
+		if (!ni[ECM_DB_OBJ_DIR_TO]) {
+			DEBUG_WARN("Failed to establish dest node\n");
+			goto fail_4;
+		}
+
+		DEBUG_TRACE("%px: Create dest mapping\n", nci);
+		mi[ECM_DB_OBJ_DIR_TO] = ecm_ipv4_mapping_establish_and_ref(ip_dest_addr, dest_port);
+		if (!mi[ECM_DB_OBJ_DIR_TO]) {
+			DEBUG_WARN("Failed to establish dest mapping\n");
+			goto fail_5;
+		}
+
+		/*
+		 * Get the src and destination NAT mappings
+		 * For this we also need the interface lists which we also set upon the new connection while we are at it.
+		 * GGG TODO rework terms of "src/dest" - these need to be named consistently as from/to as per database terms.
+		 * GGG TODO The empty list checks should not be needed, mapping_establish_and_ref() should fail out if there is no list anyway.
+		 */
+
+		/*
+		 * NOTE: For SIT tunnels use the in_dev instead of in_dev_nat
+		 */
+		DEBUG_TRACE("%px: Create the 'from NAT' interface heirarchy list\n", nci);
+		if ((protocol == IPPROTO_IPV6) || (protocol == IPPROTO_ESP)) {
+			from_nat_list_first = ecm_interface_heirarchy_construct(feci, from_nat_list, efeici.from_nat_dev, efeici.from_nat_other_dev, ip_dest_addr, efeici.from_nat_mac_lookup_ip_addr, ip_src_addr_nat, 4, protocol, in_dev, is_routed, in_dev, src_node_addr_nat, dest_node_addr_nat, NULL, skb, NULL);
+		} else {
+			from_nat_list_first = ecm_interface_heirarchy_construct(feci, from_nat_list, efeici.from_nat_dev, efeici.from_nat_other_dev, ip_dest_addr, efeici.from_nat_mac_lookup_ip_addr, ip_src_addr_nat, 4, protocol, in_dev_nat, is_routed, in_dev, src_node_addr_nat, dest_node_addr_nat, NULL, skb, NULL);
+		}
+
+		if (from_nat_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			DEBUG_WARN("Failed to obtain 'from NAT' heirarchy list\n");
+			goto fail_6;
+		}
+		ecm_db_connection_interfaces_reset(nci, from_nat_list, from_nat_list_first, ECM_DB_OBJ_DIR_FROM_NAT);
+
+		DEBUG_TRACE("%px: Create source nat node\n", nci);
+		ni[ECM_DB_OBJ_DIR_FROM_NAT] = ecm_ipv4_node_establish_and_ref(feci, efeici.from_nat_dev, efeici.from_nat_mac_lookup_ip_addr, from_nat_list, from_nat_list_first, src_node_addr_nat, skb);
+		ecm_db_connection_interfaces_deref(from_nat_list, from_nat_list_first);
+		if (!ni[ECM_DB_OBJ_DIR_FROM_NAT]) {
+			DEBUG_WARN("Failed to establish source nat node\n");
+			goto fail_6;
+		}
+
+		mi[ECM_DB_OBJ_DIR_FROM_NAT] = ecm_ipv4_mapping_establish_and_ref(ip_src_addr_nat, src_port_nat);
+		if (!mi[ECM_DB_OBJ_DIR_FROM_NAT]) {
+			DEBUG_WARN("Failed to establish src nat mapping\n");
+			goto fail_7;
+		}
+
+		DEBUG_TRACE("%px: Create the 'to NAT' interface heirarchy list\n", nci);
+		to_nat_list_first = ecm_interface_heirarchy_construct(feci, to_nat_list, efeici.to_nat_dev, efeici.to_nat_other_dev, ip_src_addr, efeici.to_nat_mac_lookup_ip_addr, ip_dest_addr_nat, 4, protocol, out_dev_nat, is_routed, in_dev, dest_node_addr_nat, src_node_addr_nat, NULL, skb, NULL);
+		if (to_nat_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			DEBUG_WARN("Failed to obtain 'to NAT' heirarchy list\n");
+			goto fail_8;
+		}
+		ecm_db_connection_interfaces_reset(nci, to_nat_list, to_nat_list_first, ECM_DB_OBJ_DIR_TO_NAT);
+
+		DEBUG_TRACE("%px: Create dest nat node\n", nci);
+		ni[ECM_DB_OBJ_DIR_TO_NAT] = ecm_ipv4_node_establish_and_ref(feci, efeici.to_nat_dev, efeici.to_nat_mac_lookup_ip_addr, to_nat_list, to_nat_list_first, dest_node_addr_nat, skb);
+
+		ecm_db_connection_interfaces_deref(to_nat_list, to_nat_list_first);
+		if (!ni[ECM_DB_OBJ_DIR_TO_NAT]) {
+			DEBUG_WARN("Failed to establish dest nat node\n");
+			goto fail_8;
+		}
+
+		mi[ECM_DB_OBJ_DIR_TO_NAT] = ecm_ipv4_mapping_establish_and_ref(ip_dest_addr_nat, dest_port_nat);
+		if (!mi[ECM_DB_OBJ_DIR_TO_NAT]) {
+			DEBUG_WARN("Failed to establish dest mapping\n");
+			goto fail_9;
+		}
+
+		/*
+		 * Every connection also needs a default classifier
+		 */
+		dci = ecm_classifier_default_instance_alloc(nci, protocol, ecm_dir, src_port, dest_port);
+		if (!dci) {
+			DEBUG_WARN("Failed to allocate default classifier\n");
+			goto fail_10;
+		}
+		ecm_db_connection_classifier_assign(nci, (struct ecm_classifier_instance *)dci);
+
+		/*
+		 * Every connection starts with a full complement of classifiers assigned.
+		 * NOTE: Default classifier is a special case considered previously
+		 */
+		for (classifier_type = ECM_CLASSIFIER_TYPE_DEFAULT + 1; classifier_type < ECM_CLASSIFIER_TYPES; ++classifier_type) {
+			struct ecm_classifier_instance *aci = ecm_classifier_assign_classifier(nci, classifier_type);
+			if (aci) {
+				aci->deref(aci);
+			} else {
+				DEBUG_WARN("Failed to allocate classifiers assignments\n");
+				goto fail_11;
+			}
+		}
+
+		ecm_db_front_end_instance_ref_and_set(nci, feci);
+
+		ecm_db_connection_l2_encap_proto_set(nci, l2_encap_proto);
+
+		/*
+		 * Now add the connection into the database.
+		 * NOTE: In an SMP situation such as ours there is a possibility that more than one packet for the same
+		 * connection is being processed simultaneously.
+		 * We *could* end up creating more than one connection instance for the same actual connection.
+		 * To guard against this we now perform a mutex'd lookup of the connection + add once more - another cpu may have created it before us.
+		 */
+		spin_lock_bh(&ecm_ipv4_lock);
+		ci = ecm_db_connection_find_and_ref(ip_src_addr, ip_dest_addr, protocol, src_port, dest_port);
+		if (ci) {
+			/*
+			 * Another cpu created the same connection before us - use the one we just found
+			 */
+			spin_unlock_bh(&ecm_ipv4_lock);
+			ecm_db_connection_deref(nci);
+		} else {
+			struct ecm_tracker_instance *ti;
+			ecm_db_timer_group_t tg;
+			ecm_tracker_sender_state_t src_state;
+			ecm_tracker_sender_state_t dest_state;
+			ecm_tracker_connection_state_t state;
+
+			/*
+			 * Ask tracker for timer group to set the connection to initially.
+			 */
+			ti = dci->tracker_get_and_ref(dci);
+			ti->state_get(ti, &src_state, &dest_state, &state, &tg);
+			ti->deref(ti);
+
+			/*
+			 * Add the new connection we created into the database
+			 * NOTE: assign to a short timer group for now - it is the assigned classifiers responsibility to do this
+			 */
+			ecm_db_connection_add(nci, mi, ni,
+					4, protocol, ecm_dir,
+					NULL /* final callback */,
+					defunct_callback,
+					tg, is_routed, nci);
+
+			spin_unlock_bh(&ecm_ipv4_lock);
+
+			ci = nci;
+			DEBUG_INFO("%px: New Non-ported protocol %d connection created\n", ci, protocol);
+		}
+
+		if (pppoe_bridged) {
+			ecm_db_connection_flag_set(ci, ECM_DB_CONNECTION_FLAGS_PPPOE_BRIDGE);
+		}
+
+		/*
+		 * No longer need referenecs to the objects we created
+		 */
+		dci->base.deref((struct ecm_classifier_instance *)dci);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO_NAT]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO_NAT]);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM_NAT]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM_NAT]);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+		ecm_front_end_ipv4_interface_construct_netdev_put(&efeici);
+		feci->deref(feci);
+
+		goto done;
+fail_11:
+		dci->base.deref((struct ecm_classifier_instance *)dci);
+fail_10:
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO_NAT]);
+fail_9:
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO_NAT]);
+fail_8:
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM_NAT]);
+fail_7:
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM_NAT]);
+fail_6:
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+fail_5:
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+fail_4:
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+fail_3:
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+fail_2:
+		ecm_front_end_ipv4_interface_construct_netdev_put(&efeici);
+fail_1:
+		feci->deref(feci);
+		ecm_db_connection_deref(nci);
+		return NF_ACCEPT;
+done:
+		;
+	}
+
+#if defined(CONFIG_NET_CLS_ACT) && defined(ECM_CLASSIFIER_DSCP_IGS) && defined(ECM_FRONT_END_NSS_ENABLE)
+	/*
+	 * Check if IGS feature is enabled or not.
+	 */
+	if (unlikely(ecm_interface_igs_enabled)) {
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+		if (feci->accel_engine == ECM_FRONT_END_ENGINE_NSS) {
+			if (!ecm_nss_common_igs_acceleration_is_allowed(feci, skb)) {
+				DEBUG_WARN("%px: Non-ported IPv4 IGS acceleration denied\n", ci);
+				feci->deref(feci);
+				ecm_db_connection_deref(ci);
+				return NF_ACCEPT;
+			}
+		}
+		feci->deref(feci);
+	}
+#endif
+
+	/*
+	 * Keep connection alive as we have seen activity
+	 */
+	if (!ecm_db_connection_defunct_timer_touch(ci)) {
+		ecm_db_connection_deref(ci);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Identify which side of the connection is sending.
+	 * NOTE: This may be different than what sender is at the moment
+	 * given the connection we have located.
+	 */
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, match_addr);
+	if (ECM_IP_ADDR_MATCH(ip_src_addr, match_addr)) {
+		sender = ECM_TRACKER_SENDER_TYPE_SRC;
+	} else {
+		sender = ECM_TRACKER_SENDER_TYPE_DEST;
+	}
+
+	/*
+	 * Do we need to action generation change?
+	 */
+	if (unlikely(ecm_db_connection_regeneration_required_check(ci))) {
+		ecm_ipv4_connection_regenerate(ci, sender, out_dev, out_dev_nat, in_dev, in_dev_nat, NULL, skb);
+	}
+
+	/*
+	 * Increment the slow path packet counter.
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	spin_lock_bh(&feci->lock);
+	feci->stats.slow_path_packets++;
+	spin_unlock_bh(&feci->lock);
+	feci->deref(feci);
+
+	/*
+	 * Iterate the assignments and call to process!
+	 * Policy implemented:
+	 * 1. Classifiers that say they are not relevant are unassigned and not actioned further.
+	 * 2. Any drop command from any classifier is honoured.
+	 * 3. Accel is never allowed for non-ported type connections.
+	 * 4. Only the highest priority classifier, that actions it, will have its qos tag honoured.
+	 * 5. Only the highest priority classifier, that actions it, will have its timer group honoured.
+	 */
+	DEBUG_TRACE("%px: process begin, skb: %px\n", ci, skb);
+	prevalent_pr.process_actions = 0;
+	prevalent_pr.drop = false;
+	prevalent_pr.flow_qos_tag = skb->priority;
+	prevalent_pr.return_qos_tag = skb->priority;
+	prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+	prevalent_pr.timer_group = ci_orig_timer_group = ecm_db_connection_timer_group_get(ci);
+
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_process_response aci_pr;
+		struct ecm_classifier_instance *aci;
+
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: process: %px, type: %d\n", ci, aci, aci->type_get(aci));
+		aci->process(aci, sender, ip_hdr, skb, &aci_pr);
+		DEBUG_TRACE("%px: aci_pr: process actions: %x, became relevant: %u, relevance: %d, drop: %d, "
+				"flow_qos_tag: %u, return_qos_tag: %u, accel_mode: %x, timer_group: %d\n",
+				ci, aci_pr.process_actions, aci_pr.became_relevant, aci_pr.relevance, aci_pr.drop,
+				aci_pr.flow_qos_tag, aci_pr.return_qos_tag, aci_pr.accel_mode, aci_pr.timer_group);
+
+		if (aci_pr.relevance == ECM_CLASSIFIER_RELEVANCE_NO) {
+			ecm_classifier_type_t aci_type;
+
+			/*
+			 * This classifier can be unassigned - PROVIDED it is not the default classifier
+			 */
+			aci_type = aci->type_get(aci);
+			if (aci_type == ECM_CLASSIFIER_TYPE_DEFAULT) {
+				continue;
+			}
+
+			DEBUG_INFO("%px: Classifier not relevant, unassign: %d", ci, aci_type);
+			ecm_db_connection_classifier_unassign(ci, aci);
+			continue;
+		}
+
+		/*
+		 * Yes or Maybe relevant.
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DROP) {
+			/*
+			 * Drop command from any classifier is actioned.
+			 */
+			DEBUG_TRACE("%px: wants drop: %px, type: %d, skb: %px\n", ci, aci, aci->type_get(aci), skb);
+			prevalent_pr.drop |= aci_pr.drop;
+		}
+
+		/*
+		 * Accel mode permission
+		 */
+		if (aci_pr.relevance == ECM_CLASSIFIER_RELEVANCE_MAYBE) {
+			/*
+			 * Classifier not sure of its relevance - cannot accel yet
+			 */
+			DEBUG_TRACE("%px: accel denied by maybe: %px, type: %d\n", ci, aci, aci->type_get(aci));
+			prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+		} else {
+			if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE) {
+				if (aci_pr.accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_NO) {
+					DEBUG_TRACE("%px: accel denied: %px, type: %d\n", ci, aci, aci->type_get(aci));
+					prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+				}
+				/* else yes or don't care about accel */
+			}
+		}
+
+		/*
+		 * Timer group (the last classifier i.e. the highest priority one) will 'win'
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP) {
+			DEBUG_TRACE("%px: timer group: %px, type: %d, group: %d\n", ci, aci, aci->type_get(aci), aci_pr.timer_group);
+			prevalent_pr.timer_group = aci_pr.timer_group;
+		}
+
+		/*
+		 * Qos tag (the last classifier i.e. the highest priority one) will 'win'
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, flow qos tag: %u, return qos tag: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.flow_qos_tag, aci_pr.return_qos_tag);
+			prevalent_pr.flow_qos_tag = aci_pr.flow_qos_tag;
+			prevalent_pr.return_qos_tag = aci_pr.return_qos_tag;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG;
+		}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+#ifdef ECM_CLASSIFIER_DSCP_IGS
+		/*
+		 * Ingress QoS tag
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, ingress flow qos tag: %u, ingress return qos tag: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.igs_flow_qos_tag, aci_pr.igs_return_qos_tag);
+			prevalent_pr.igs_flow_qos_tag = aci_pr.igs_flow_qos_tag;
+			prevalent_pr.igs_return_qos_tag = aci_pr.igs_return_qos_tag;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG;
+		}
+#endif
+		/*
+		 * If any classifier denied DSCP remarking then that overrides every classifier
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, DSCP remark denied\n",
+					ci, aci, aci->type_get(aci));
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY;
+			prevalent_pr.process_actions &= ~ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+		}
+
+		/*
+		 * DSCP remark action, but only if it has not been denied by any classifier
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+			if (!(prevalent_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY)) {
+				DEBUG_TRACE("%px: aci: %px, type: %d, DSCP remark wanted, flow_dscp: %u, return dscp: %u\n",
+						ci, aci, aci->type_get(aci), aci_pr.flow_dscp, aci_pr.return_dscp);
+				prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+				prevalent_pr.flow_dscp = aci_pr.flow_dscp;
+				prevalent_pr.return_dscp = aci_pr.return_dscp;
+			}
+		}
+
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_MARK) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, flow mark: %u, return mark: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.flow_mark, aci_pr.return_mark);
+			prevalent_pr.flow_mark = aci_pr.flow_mark;
+			prevalent_pr.return_mark = aci_pr.return_mark;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_MARK;
+		}
+#endif
+
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+		/*
+		 * E-Mesh Service Prioritization is Valid
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, E-Mesh Service Prioritization is valid\n",
+					ci, aci, aci->type_get(aci));
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW;
+		}
+#endif
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Change timer group?
+	 */
+	if (ci_orig_timer_group != prevalent_pr.timer_group) {
+		DEBUG_TRACE("%px: change timer group from: %d to: %d\n", ci, ci_orig_timer_group, prevalent_pr.timer_group);
+		ecm_db_connection_defunct_timer_reset(ci, prevalent_pr.timer_group);
+	}
+
+	/*
+	 * Drop?
+	 */
+	if (prevalent_pr.drop) {
+		DEBUG_TRACE("%px: drop: %px\n", ci, skb);
+		ecm_db_connection_data_totals_update_dropped(ci, (sender == ECM_TRACKER_SENDER_TYPE_SRC)? true : false, skb->len, 1);
+		ecm_db_connection_deref(ci);
+		return NF_ACCEPT;
+	}
+	ecm_db_connection_data_totals_update(ci, (sender == ECM_TRACKER_SENDER_TYPE_SRC)? true : false, skb->len, 1);
+
+	/*
+	 * Assign qos tag
+	 * GGG TODO Should we use sender to identify whether to use flow or return qos tag?
+	 */
+	skb->priority = prevalent_pr.flow_qos_tag;
+	DEBUG_TRACE("%px: skb priority: %u\n", ci, skb->priority);
+
+#ifdef ECM_INTERFACE_SIT_ENABLE
+#ifdef CONFIG_IPV6_SIT_6RD
+	/*
+	 * SIT tunnel acceleration needs create a rule to the acceleration engine if the
+	 *	tunnel's dest ip address is empty,it will get dest ip and the embedded ipv6's dest ip
+	 *	address in the packet and send them to the nss firmware to accelerate the
+	 *	traffic on the tun6rd interface.
+	 */
+	if (protocol == IPPROTO_IPV6
+			&& prevalent_pr.accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL) {
+		DEBUG_TRACE("%px: accel\n", ci);
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+#ifdef ECM_FRONT_END_NSS_ENABLE
+		if (feci->accel_engine == ECM_FRONT_END_ENGINE_NSS) {
+			ecm_nss_non_ported_ipv4_sit_set_peer((struct ecm_nss_non_ported_ipv4_connection_instance *)feci, skb);
+		}
+#endif
+
+#ifdef ECM_FRONT_END_SFE_ENABLE
+		if (feci->accel_engine == ECM_FRONT_END_ENGINE_SFE) {
+			ecm_sfe_non_ported_ipv4_sit_set_peer((struct ecm_sfe_non_ported_ipv4_connection_instance *)feci, skb);
+		}
+#endif
+
+		feci->deref(feci);
+	}
+#endif
+#endif
+	/*
+	 * Accelerate?
+	 */
+	if (prevalent_pr.accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL) {
+		DEBUG_TRACE("%px: accel\n", ci);
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+		feci->accelerate(feci, &prevalent_pr, is_l2_encap, ct, skb);
+		feci->deref(feci);
+	}
+	ecm_db_connection_deref(ci);
+
+	return NF_ACCEPT;
+}
diff --git a/qca-nss-ecm/frontends/cmn/ecm_non_ported_ipv4.h b/qca-nss-ecm/frontends/cmn/ecm_non_ported_ipv4.h
new file mode 100644
index 0000000..ad79878
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_non_ported_ipv4.h
@@ -0,0 +1,26 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern unsigned int ecm_non_ported_ipv4_process(struct net_device *out_dev, struct net_device *out_dev_nat,
+							struct net_device *in_dev, struct net_device *in_dev_nat,
+							uint8_t *src_node_addr, uint8_t *src_node_addr_nat,
+							uint8_t *dest_node_addr, uint8_t *dest_node_addr_nat,
+							bool can_accel, bool is_routed, bool is_l2_encap, struct sk_buff *skb,
+							struct ecm_tracker_ip_header *ip_hdr,
+							struct nf_conn *ct, ecm_tracker_sender_type_t sender, ecm_db_direction_t ecm_dir,
+							struct nf_conntrack_tuple *orig_tuple, struct nf_conntrack_tuple *reply_tuple,
+							ip_addr_t ip_src_addr, ip_addr_t ip_dest_addr, ip_addr_t ip_src_addr_nat, ip_addr_t ip_dest_addr_nat,
+							uint16_t l2_encap_proto);
diff --git a/qca-nss-ecm/frontends/cmn/ecm_non_ported_ipv6.c b/qca-nss-ecm/frontends/cmn/ecm_non_ported_ipv6.c
new file mode 100644
index 0000000..ba50952
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_non_ported_ipv6.c
@@ -0,0 +1,744 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/debugfs.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/ip6_route.h>
+#include <net/ip6_fib.h>
+#include <net/addrconf.h>
+#include <net/ipv6.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in6.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv6.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv6/nf_conntrack_ipv6.h>
+#include <net/netfilter/ipv6/nf_defrag_ipv6.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_NON_PORTED_IPV6_DEBUG_LEVEL
+
+#ifdef ECM_FRONT_END_NSS_ENABLE
+#include <nss_api_if.h>
+#endif
+
+#ifdef ECM_FRONT_END_SFE_ENABLE
+#include <sfe_api.h>
+#endif
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#ifdef ECM_FRONT_END_NSS_ENABLE
+#include "ecm_nss_non_ported_ipv6.h"
+#include "ecm_nss_ipv6.h"
+#include "ecm_nss_common.h"
+#endif
+#ifdef ECM_FRONT_END_SFE_ENABLE
+#include "ecm_sfe_non_ported_ipv6.h"
+#include "ecm_sfe_ipv6.h"
+#include "ecm_sfe_common.h"
+#endif
+#include "ecm_front_end_common.h"
+#include "ecm_ipv6.h"
+#include "ecm_ae_classifier_public.h"
+#include "ecm_ae_classifier.h"
+
+/*
+ * ecm_non_ported_ipv6_is_protocol_supported()
+ *	Return true if IPv6 protocol is supported in non-ported acceleration.
+ */
+static inline bool ecm_non_ported_ipv6_is_protocol_supported(int protocol)
+{
+	switch (protocol) {
+	case IPPROTO_IPIP:
+	case IPPROTO_ESP:
+#if defined(ECM_INTERFACE_GRE_TAP_ENABLE) || defined(ECM_INTERFACE_GRE_TUN_ENABLE)
+	case IPPROTO_GRE:
+#endif
+	case IPPROTO_RAW:
+		return true;
+	}
+	return false;
+}
+
+/*
+ * ecm_non_ported_ipv6_process()
+ *	Process a protocol that does not have port based identifiers
+ */
+unsigned int ecm_non_ported_ipv6_process(struct net_device *out_dev,
+							struct net_device *in_dev,
+							uint8_t *src_node_addr,
+							uint8_t *dest_node_addr,
+							bool can_accel, bool is_routed, bool is_l2_encap, struct sk_buff *skb,
+							struct ecm_tracker_ip_header *ip_hdr,
+							struct nf_conn *ct, ecm_tracker_sender_type_t sender, ecm_db_direction_t ecm_dir,
+							struct nf_conntrack_tuple *orig_tuple, struct nf_conntrack_tuple *reply_tuple,
+							ip_addr_t ip_src_addr, ip_addr_t ip_dest_addr, uint16_t l2_encap_proto)
+{
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	int protocol;
+	int src_port;
+	int dest_port;
+	ip_addr_t match_addr;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	ecm_db_timer_group_t ci_orig_timer_group;
+	struct ecm_classifier_process_response prevalent_pr;
+	bool pppoe_bridged = false;
+
+	/*
+	 * Look up a connection.
+	 */
+	protocol = (int)orig_tuple->dst.protonum;
+	src_port = 0;
+	dest_port = 0;
+
+	/*
+	 * We are not yet supporting PPPOE bridge for SFE.
+	 * TODO: Revisit when we want to add that support.
+	 */
+#ifdef ECM_FRONT_END_NSS_ENABLE
+	if (unlikely(!is_routed &&
+			(l2_encap_proto == ETH_P_PPP_SES) &&
+			(nss_pppoe_get_br_accel_mode() == NSS_PPPOE_BR_ACCEL_MODE_EN_3T))) {
+		struct pppoe_hdr *ph;
+		uint32_t l2_encap_len = ecm_front_end_l2_encap_header_len(l2_encap_proto);
+
+		/*
+		 * Get PPPoE session id from skb.
+		 */
+		ecm_front_end_push_l2_encap_header(skb, l2_encap_len);
+		ph = pppoe_hdr(skb);
+		DEBUG_TRACE("PPPoE session ID: %x\n", ntohs(ph->sid));
+		src_port = ntohs(ph->sid);
+		protocol = IPPROTO_RAW;
+		dest_port = src_port;
+		ecm_front_end_pull_l2_encap_header(skb, l2_encap_len);
+		pppoe_bridged = true;
+	}
+#endif
+
+	if(!ecm_non_ported_ipv6_is_protocol_supported(protocol)) {
+		DEBUG_TRACE("Unsupported non-ported protocol: %d, do not process.\n", protocol);
+		return NF_ACCEPT;
+	}
+
+	DEBUG_TRACE("Non-ported protocol src: " ECM_IP_ADDR_OCTAL_FMT ", dest: " ECM_IP_ADDR_OCTAL_FMT "\n",
+				ECM_IP_ADDR_TO_OCTAL(ip_src_addr), ECM_IP_ADDR_TO_OCTAL(ip_dest_addr));
+
+	ci = ecm_db_connection_find_and_ref(ip_src_addr, ip_dest_addr, protocol, src_port, dest_port);
+
+	/*
+	 * If there is no existing connection then create a new one.
+	 */
+	if (unlikely(!ci)) {
+		struct ecm_db_mapping_instance *mi[ECM_DB_OBJ_DIR_MAX];
+		struct ecm_db_node_instance *ni[ECM_DB_OBJ_DIR_MAX];
+		struct ecm_classifier_default_instance *dci;
+		struct ecm_db_connection_instance *nci;
+		ecm_classifier_type_t classifier_type;
+		int32_t to_list_first;
+		struct ecm_db_iface_instance *to_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+		int32_t from_list_first;
+		struct ecm_db_iface_instance *from_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+		struct ecm_front_end_interface_construct_instance efeici;
+		enum ecm_front_end_type fe_type;
+		ecm_ae_classifier_result_t ae_result;
+		ecm_db_connection_defunct_callback_t defunct_callback;
+
+		DEBUG_INFO("New connection from " ECM_IP_ADDR_OCTAL_FMT " to " ECM_IP_ADDR_OCTAL_FMT "\n",
+				ECM_IP_ADDR_TO_OCTAL(ip_src_addr), ECM_IP_ADDR_TO_OCTAL(ip_dest_addr));
+
+		/*
+		 * Before we attempt to create the connection are we being terminated?
+		 */
+		spin_lock_bh(&ecm_ipv6_lock);
+		if (ecm_ipv6_terminate_pending) {
+			spin_unlock_bh(&ecm_ipv6_lock);
+			DEBUG_WARN("Terminating\n");
+
+			/*
+			 * As we are terminating we just allow the packet to pass - it's no longer our concern
+			 */
+			return NF_ACCEPT;
+		}
+		spin_unlock_bh(&ecm_ipv6_lock);
+
+		/*
+		 * Connection must have a front end instance associated with it
+		 */
+		fe_type = ecm_front_end_type_get();
+		switch (fe_type) {
+#if defined(ECM_FRONT_END_NSS_ENABLE) && defined(ECM_FRONT_END_SFE_ENABLE)
+		case ECM_FRONT_END_TYPE_HYBRID:
+		{
+			ecm_ae_classifier_get_t ae_get;
+			struct ecm_ae_classifier_info ae_info;
+
+			/*
+			 * Check the return type of the external callback.
+			 * 1. If NSS, allocate NSS ipv6 non-ported connection instance
+			 * 2. If NONE, allocate NSS ipv6 non-ported connection instance with can_accel flag is set to false.
+			 *    By doing this ECM will not ask again and again to the external module. If external module wants to
+			 *    accelerate this flow later, the flow needs to be defuncted first.
+			 * 3. If NOT_YET, the connection will not be allocated in the database and the next flow will be asked again
+			 *    to the external module.
+			 * 4. If any other type is returned, ASSERT.
+			 */
+			ecm_ae_classifier_select_info_fill(ip_src_addr, ip_dest_addr,
+							  src_port, dest_port, protocol, 6,
+							  is_routed, false,
+							  &ae_info);
+
+			rcu_read_lock();
+			ae_get = rcu_dereference(ae_ops.ae_get);
+			ae_result = ae_get(&ae_info);
+			rcu_read_unlock();
+
+			DEBUG_TRACE("front end type hybrid, ae_result: %d\n", ae_result);
+			break;
+		}
+#endif
+#ifdef ECM_FRONT_END_NSS_ENABLE
+		case ECM_FRONT_END_TYPE_NSS:
+			ae_result = ECM_AE_CLASSIFIER_RESULT_NSS;
+			DEBUG_TRACE("front end type NSS, ae_result: %d\n", ae_result);
+			break;
+#endif
+#ifdef ECM_FRONT_END_SFE_ENABLE
+		case ECM_FRONT_END_TYPE_SFE:
+			ae_result = ECM_AE_CLASSIFIER_RESULT_SFE;
+			DEBUG_TRACE("front end type SFE, ae_result: %d\n", ae_result);
+			break;
+#endif
+		default:
+			DEBUG_WARN("front end type: %d is not supported\n", fe_type);
+			return NF_ACCEPT;
+		}
+
+		/*
+		 * Check the ae_result.
+		 * 1. If NSS, allocate NSS ipv6 non-ported connection instance
+		 * 2. If NONE, allocate NSS ipv6 non-ported connection instance with can_accel flag is set to false.
+		 *    By doing this ECM will not ask again and again to the external module. If external module wants to
+		 *    accelerate this flow later, the flow needs to be defuncted first.
+		 * 3. If NOT_YET, the connection will not be allocated in the database and the next flow will be asked again
+		 *    to the external module.
+		 * 4. If any other type is returned, ASSERT.
+		 */
+		switch (ae_result) {
+#ifdef ECM_FRONT_END_NSS_ENABLE
+		case ECM_AE_CLASSIFIER_RESULT_NSS:
+			if (!ecm_nss_feature_check(skb, ip_hdr)) {
+				DEBUG_WARN("Unsupported feature found for NSS acceleration\n");
+				return NF_ACCEPT;
+			}
+			defunct_callback = ecm_nss_non_ported_ipv6_connection_defunct_callback;
+			feci = (struct ecm_front_end_connection_instance *)ecm_nss_non_ported_ipv6_connection_instance_alloc(can_accel, protocol, &nci);
+			break;
+
+		case ECM_AE_CLASSIFIER_RESULT_NONE:
+			defunct_callback = ecm_nss_non_ported_ipv6_connection_defunct_callback;
+			feci = (struct ecm_front_end_connection_instance *)ecm_nss_non_ported_ipv6_connection_instance_alloc(false, protocol, &nci);
+			break;
+#endif
+#ifdef ECM_FRONT_END_SFE_ENABLE
+		case ECM_AE_CLASSIFIER_RESULT_SFE:
+			defunct_callback = ecm_sfe_non_ported_ipv6_connection_defunct_callback;
+			feci = (struct ecm_front_end_connection_instance *)ecm_sfe_non_ported_ipv6_connection_instance_alloc(can_accel, protocol, &nci);
+			break;
+#endif
+		case ECM_AE_CLASSIFIER_RESULT_NOT_YET:
+			return NF_ACCEPT;
+
+		default:
+			DEBUG_ASSERT(NULL, "unexpected ae_result: %d\n", ae_result);
+		}
+
+		if (!feci) {
+			DEBUG_WARN("Failed to allocate front end\n");
+			return NF_ACCEPT;
+		}
+
+		if (!ecm_front_end_ipv6_interface_construct_set_and_hold(skb, sender, ecm_dir, is_routed,
+							in_dev, out_dev,
+							ip_src_addr, ip_dest_addr,
+							&efeici)) {
+			DEBUG_WARN("ECM front end ipv6 interface construct set failed\n");
+			goto fail_1;
+		}
+
+		/*
+		 * Get the src and destination mappings
+		 * For this we also need the interface lists which we also set upon the new connection while we are at it.
+		 * GGG TODO rework terms of "src/dest" - these need to be named consistently as from/to as per database terms.
+		 * GGG TODO The empty list checks should not be needed, mapping_establish_and_ref() should fail out if there is no list anyway.
+		 */
+		DEBUG_TRACE("%px: Create the 'from' interface heirarchy list\n", nci);
+		from_list_first = ecm_interface_heirarchy_construct(feci, from_list, efeici.from_dev, efeici.from_other_dev, ip_dest_addr, efeici.from_mac_lookup_ip_addr, ip_src_addr, 6, protocol, in_dev, is_routed, in_dev, src_node_addr, dest_node_addr, NULL, skb, NULL);
+		if (from_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			DEBUG_WARN("Failed to obtain 'from' heirarchy list\n");
+			goto fail_2;
+		}
+		ecm_db_connection_interfaces_reset(nci, from_list, from_list_first, ECM_DB_OBJ_DIR_FROM);
+
+		DEBUG_TRACE("%px: Create source node\n", nci);
+		ni[ECM_DB_OBJ_DIR_FROM] = ecm_ipv6_node_establish_and_ref(feci, efeici.from_dev, efeici.from_mac_lookup_ip_addr, from_list, from_list_first, src_node_addr, skb);
+		ecm_db_connection_interfaces_deref(from_list, from_list_first);
+		if (!ni[ECM_DB_OBJ_DIR_FROM]) {
+			DEBUG_WARN("Failed to establish source node\n");
+			goto fail_2;
+		}
+		ni[ECM_DB_OBJ_DIR_FROM_NAT] = ni[ECM_DB_OBJ_DIR_FROM];
+
+		DEBUG_TRACE("%px: Create source mapping\n", nci);
+		mi[ECM_DB_OBJ_DIR_FROM] = ecm_ipv6_mapping_establish_and_ref(ip_src_addr, src_port);
+		if (!mi[ECM_DB_OBJ_DIR_FROM]) {
+			DEBUG_WARN("Failed to establish src mapping\n");
+			goto fail_3;
+		}
+		mi[ECM_DB_OBJ_DIR_FROM_NAT] = mi[ECM_DB_OBJ_DIR_FROM];
+
+		DEBUG_TRACE("%px: Create the 'to' interface heirarchy list\n", nci);
+		to_list_first = ecm_interface_heirarchy_construct(feci, to_list, efeici.to_dev, efeici.to_other_dev, ip_src_addr, efeici.to_mac_lookup_ip_addr, ip_dest_addr, 6, protocol, out_dev, is_routed, in_dev, dest_node_addr, src_node_addr, NULL, skb, NULL);
+		if (to_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			DEBUG_WARN("Failed to obtain 'to' heirarchy list\n");
+			goto fail_4;
+		}
+		ecm_db_connection_interfaces_reset(nci, to_list, to_list_first, ECM_DB_OBJ_DIR_TO);
+
+		DEBUG_TRACE("%px: Create dest node\n", nci);
+		ni[ECM_DB_OBJ_DIR_TO] = ecm_ipv6_node_establish_and_ref(feci, efeici.to_dev, efeici.to_mac_lookup_ip_addr, to_list, to_list_first, dest_node_addr, skb);
+		ecm_db_connection_interfaces_deref(to_list, to_list_first);
+		if (!ni[ECM_DB_OBJ_DIR_TO]) {
+			DEBUG_WARN("Failed to establish dest node\n");
+			goto fail_4;
+		}
+		ni[ECM_DB_OBJ_DIR_TO_NAT] = ni[ECM_DB_OBJ_DIR_TO];
+
+		DEBUG_TRACE("%px: Create dest mapping\n", nci);
+		mi[ECM_DB_OBJ_DIR_TO] = ecm_ipv6_mapping_establish_and_ref(ip_dest_addr, dest_port);
+		if (!mi[ECM_DB_OBJ_DIR_TO]) {
+			DEBUG_WARN("Failed to establish dest mapping\n");
+			goto fail_5;
+		}
+		mi[ECM_DB_OBJ_DIR_TO_NAT] = mi[ECM_DB_OBJ_DIR_TO];
+
+		/*
+		 * Every connection also needs a default classifier
+		 */
+		dci = ecm_classifier_default_instance_alloc(nci, protocol, ecm_dir, src_port, dest_port);
+		if (!dci) {
+			DEBUG_WARN("Failed to allocate default classifier\n");
+			goto fail_6;
+		}
+		ecm_db_connection_classifier_assign(nci, (struct ecm_classifier_instance *)dci);
+
+		/*
+		 * Every connection starts with a full complement of classifiers assigned.
+		 * NOTE: Default classifier is a special case considered previously
+		 */
+		for (classifier_type = ECM_CLASSIFIER_TYPE_DEFAULT + 1; classifier_type < ECM_CLASSIFIER_TYPES; ++classifier_type) {
+			struct ecm_classifier_instance *aci = ecm_classifier_assign_classifier(nci, classifier_type);
+			if (aci) {
+				aci->deref(aci);
+			} else {
+				DEBUG_WARN("Failed to allocate classifiers assignments\n");
+				goto fail_7;
+			}
+		}
+
+		ecm_db_front_end_instance_ref_and_set(nci, feci);
+
+		ecm_db_connection_l2_encap_proto_set(nci, l2_encap_proto);
+
+		/*
+		 * Now add the connection into the database.
+		 * NOTE: In an SMP situation such as ours there is a possibility that more than one packet for the same
+		 * connection is being processed simultaneously.
+		 * We *could* end up creating more than one connection instance for the same actual connection.
+		 * To guard against this we now perform a mutex'd lookup of the connection + add once more - another cpu may have created it before us.
+		 */
+		spin_lock_bh(&ecm_ipv6_lock);
+		ci = ecm_db_connection_find_and_ref(ip_src_addr, ip_dest_addr, protocol, src_port, dest_port);
+		if (ci) {
+			/*
+			 * Another cpu created the same connection before us - use the one we just found
+			 */
+			spin_unlock_bh(&ecm_ipv6_lock);
+			ecm_db_connection_deref(nci);
+		} else {
+			struct ecm_tracker_instance *ti;
+			ecm_db_timer_group_t tg;
+			ecm_tracker_sender_state_t src_state;
+			ecm_tracker_sender_state_t dest_state;
+			ecm_tracker_connection_state_t state;
+
+			/*
+			 * Ask tracker for timer group to set the connection to initially.
+			 */
+			ti = dci->tracker_get_and_ref(dci);
+			ti->state_get(ti, &src_state, &dest_state, &state, &tg);
+			ti->deref(ti);
+
+			/*
+			 * Add the new connection we created into the database
+			 * NOTE: assign to a short timer group for now - it is the assigned classifiers responsibility to do this
+			 */
+			ecm_db_connection_add(nci, mi, ni,
+					6, protocol, ecm_dir,
+					NULL /* final callback */,
+					defunct_callback,
+					tg, is_routed, nci);
+
+			spin_unlock_bh(&ecm_ipv6_lock);
+
+			ci = nci;
+			DEBUG_INFO("%px: New Non-ported protocol %d connection created\n", ci, protocol);
+		}
+
+		if (pppoe_bridged) {
+			ecm_db_connection_flag_set(ci, ECM_DB_CONNECTION_FLAGS_PPPOE_BRIDGE);
+		}
+
+		/*
+		 * No longer need referenecs to the objects we created
+		 */
+		dci->base.deref((struct ecm_classifier_instance *)dci);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+		ecm_front_end_ipv6_interface_construct_netdev_put(&efeici);
+		feci->deref(feci);
+
+		goto done;
+fail_7:
+		dci->base.deref((struct ecm_classifier_instance *)dci);
+fail_6:
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+fail_5:
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+fail_4:
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+fail_3:
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+fail_2:
+		ecm_front_end_ipv6_interface_construct_netdev_put(&efeici);
+fail_1:
+		feci->deref(feci);
+		ecm_db_connection_deref(nci);
+		return NF_ACCEPT;
+done:
+		;
+	}
+
+#if defined(CONFIG_NET_CLS_ACT) && defined(ECM_CLASSIFIER_DSCP_IGS) && defined(ECM_FRONT_END_NSS_ENABLE)
+	/*
+	 * Check if IGS feature is enabled or not.
+	 */
+	if (unlikely(ecm_interface_igs_enabled)) {
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+		if (feci->accel_engine == ECM_FRONT_END_ENGINE_NSS) {
+			if (!ecm_nss_common_igs_acceleration_is_allowed(feci, skb)) {
+				DEBUG_WARN("%px: Non-ported IPv6 IGS acceleration denied\n", ci);
+				feci->deref(feci);
+				ecm_db_connection_deref(ci);
+				return NF_ACCEPT;
+			}
+		}
+		feci->deref(feci);
+	}
+#endif
+
+	/*
+	 * Keep connection alive as we have seen activity
+	 */
+	if (!ecm_db_connection_defunct_timer_touch(ci)) {
+		ecm_db_connection_deref(ci);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Identify which side of the connection is sending
+	 * NOTE: This may be different than what sender is at the moment
+	 * given the connection we have located.
+	 */
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, match_addr);
+	if (ECM_IP_ADDR_MATCH(ip_src_addr, match_addr)) {
+		sender = ECM_TRACKER_SENDER_TYPE_SRC;
+	} else {
+		sender = ECM_TRACKER_SENDER_TYPE_DEST;
+	}
+
+	/*
+	 * Do we need to action generation change?
+	 */
+	if (unlikely(ecm_db_connection_regeneration_required_check(ci))) {
+		ecm_ipv6_connection_regenerate(ci, sender, out_dev, in_dev, NULL, skb);
+	}
+
+	/*
+	 * Increment the slow path packet counter.
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	spin_lock_bh(&feci->lock);
+	feci->stats.slow_path_packets++;
+	spin_unlock_bh(&feci->lock);
+	feci->deref(feci);
+
+	/*
+	 * Iterate the assignments and call to process!
+	 * Policy implemented:
+	 * 1. Classifiers that say they are not relevant are unassigned and not actioned further.
+	 * 2. Any drop command from any classifier is honoured.
+	 * 3. Accel is never allowed for non-ported type connections.
+	 * 4. Only the highest priority classifier, that actions it, will have its qos tag honoured.
+	 * 5. Only the highest priority classifier, that actions it, will have its timer group honoured.
+	 */
+	DEBUG_TRACE("%px: process begin, skb: %px\n", ci, skb);
+	prevalent_pr.process_actions = 0;
+	prevalent_pr.drop = false;
+	prevalent_pr.flow_qos_tag = skb->priority;
+	prevalent_pr.return_qos_tag = skb->priority;
+	prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+	prevalent_pr.timer_group = ci_orig_timer_group = ecm_db_connection_timer_group_get(ci);
+
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_process_response aci_pr;
+		struct ecm_classifier_instance *aci;
+
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: process: %px, type: %d\n", ci, aci, aci->type_get(aci));
+		aci->process(aci, sender, ip_hdr, skb, &aci_pr);
+		DEBUG_TRACE("%px: aci_pr: process actions: %x, became relevant: %u, relevance: %d, drop: %d, "
+				"flow_qos_tag: %u, return_qos_tag: %u, accel_mode: %x, timer_group: %d\n",
+				ci, aci_pr.process_actions, aci_pr.became_relevant, aci_pr.relevance, aci_pr.drop,
+				aci_pr.flow_qos_tag, aci_pr.return_qos_tag, aci_pr.accel_mode, aci_pr.timer_group);
+
+		if (aci_pr.relevance == ECM_CLASSIFIER_RELEVANCE_NO) {
+			ecm_classifier_type_t aci_type;
+
+			/*
+			 * This classifier can be unassigned - PROVIDED it is not the default classifier
+			 */
+			aci_type = aci->type_get(aci);
+			if (aci_type == ECM_CLASSIFIER_TYPE_DEFAULT) {
+				continue;
+			}
+
+			DEBUG_INFO("%px: Classifier not relevant, unassign: %d", ci, aci_type);
+			ecm_db_connection_classifier_unassign(ci, aci);
+			continue;
+		}
+
+		/*
+		 * Yes or Maybe relevant.
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DROP) {
+			/*
+			 * Drop command from any classifier is actioned.
+			 */
+			DEBUG_TRACE("%px: wants drop: %px, type: %d, skb: %px\n", ci, aci, aci->type_get(aci), skb);
+			prevalent_pr.drop |= aci_pr.drop;
+		}
+
+		/*
+		 * Accel mode permission
+		 */
+		if (aci_pr.relevance == ECM_CLASSIFIER_RELEVANCE_MAYBE) {
+			/*
+			 * Classifier not sure of its relevance - cannot accel yet
+			 */
+			DEBUG_TRACE("%px: accel denied by maybe: %px, type: %d\n", ci, aci, aci->type_get(aci));
+			prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+		} else {
+			if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE) {
+				if (aci_pr.accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_NO) {
+					DEBUG_TRACE("%px: accel denied: %px, type: %d\n", ci, aci, aci->type_get(aci));
+					prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+				}
+				/* else yes or don't care about accel */
+			}
+		}
+
+		/*
+		 * Timer group (the last classifier i.e. the highest priority one) will 'win'
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP) {
+			DEBUG_TRACE("%px: timer group: %px, type: %d, group: %d\n", ci, aci, aci->type_get(aci), aci_pr.timer_group);
+			prevalent_pr.timer_group = aci_pr.timer_group;
+		}
+
+		/*
+		 * Qos tag (the last classifier i.e. the highest priority one) will 'win'
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, flow qos tag: %u, return qos tag: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.flow_qos_tag, aci_pr.return_qos_tag);
+			prevalent_pr.flow_qos_tag = aci_pr.flow_qos_tag;
+			prevalent_pr.return_qos_tag = aci_pr.return_qos_tag;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG;
+		}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+#ifdef ECM_CLASSIFIER_DSCP_IGS
+		/*
+		 * Ingress QoS tag
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, ingress flow qos tag: %u, ingress return qos tag: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.igs_flow_qos_tag, aci_pr.igs_return_qos_tag);
+			prevalent_pr.igs_flow_qos_tag = aci_pr.igs_flow_qos_tag;
+			prevalent_pr.igs_return_qos_tag = aci_pr.igs_return_qos_tag;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG;
+		}
+#endif
+		/*
+		 * If any classifier denied DSCP remarking then that overrides every classifier
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, DSCP remark denied\n",
+					ci, aci, aci->type_get(aci));
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY;
+			prevalent_pr.process_actions &= ~ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+		}
+
+		/*
+		 * DSCP remark action, but only if it has not been denied by any classifier
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+			if (!(prevalent_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY)) {
+				DEBUG_TRACE("%px: aci: %px, type: %d, DSCP remark wanted, flow_dscp: %u, return dscp: %u\n",
+						ci, aci, aci->type_get(aci), aci_pr.flow_dscp, aci_pr.return_dscp);
+				prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+				prevalent_pr.flow_dscp = aci_pr.flow_dscp;
+				prevalent_pr.return_dscp = aci_pr.return_dscp;
+			}
+		}
+
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_MARK) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, flow mark: %u, return mark: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.flow_mark, aci_pr.return_mark);
+			prevalent_pr.flow_mark = aci_pr.flow_mark;
+			prevalent_pr.return_mark = aci_pr.return_mark;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_MARK;
+		}
+#endif
+
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+		/*
+		 * E-Mesh Service Prioritization is Valid
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, E-Mesh Service Prioritization is valid\n",
+					ci, aci, aci->type_get(aci));
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW;
+		}
+#endif
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Change timer group?
+	 */
+	if (ci_orig_timer_group != prevalent_pr.timer_group) {
+		DEBUG_TRACE("%px: change timer group from: %d to: %d\n", ci, ci_orig_timer_group, prevalent_pr.timer_group);
+		ecm_db_connection_defunct_timer_reset(ci, prevalent_pr.timer_group);
+	}
+
+	/*
+	 * Drop?
+	 */
+	if (prevalent_pr.drop) {
+		DEBUG_TRACE("%px: drop: %px\n", ci, skb);
+		ecm_db_connection_data_totals_update_dropped(ci, (sender == ECM_TRACKER_SENDER_TYPE_SRC)? true : false, skb->len, 1);
+		ecm_db_connection_deref(ci);
+		return NF_ACCEPT;
+	}
+	ecm_db_connection_data_totals_update(ci, (sender == ECM_TRACKER_SENDER_TYPE_SRC)? true : false, skb->len, 1);
+
+	/*
+	 * Assign qos tag
+	 * GGG TODO Should we use sender to identify whether to use flow or return qos tag?
+	 */
+	skb->priority = prevalent_pr.flow_qos_tag;
+	DEBUG_TRACE("%px: skb priority: %u\n", ci, skb->priority);
+
+	/*
+	 * Accelerate?
+	 */
+	if (prevalent_pr.accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL) {
+		DEBUG_TRACE("%px: accel\n", ci);
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+		feci->accelerate(feci, &prevalent_pr, is_l2_encap, ct, skb);
+		feci->deref(feci);
+	}
+	ecm_db_connection_deref(ci);
+
+	return NF_ACCEPT;
+}
diff --git a/qca-nss-ecm/frontends/cmn/ecm_non_ported_ipv6.h b/qca-nss-ecm/frontends/cmn/ecm_non_ported_ipv6.h
new file mode 100644
index 0000000..fbaa10d
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_non_ported_ipv6.h
@@ -0,0 +1,25 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern unsigned int ecm_non_ported_ipv6_process(struct net_device *out_dev,
+							struct net_device *in_dev,
+							uint8_t *src_node_addr,
+							uint8_t *dest_node_addr,
+							bool can_accel, bool is_routed, bool is_l2_encap, struct sk_buff *skb,
+							struct ecm_tracker_ip_header *ip_hdr,
+							struct nf_conn *ct, ecm_tracker_sender_type_t sender, ecm_db_direction_t ecm_dir,
+							struct nf_conntrack_tuple *orig_tuple, struct nf_conntrack_tuple *reply_tuple,
+							ip_addr_t ip_src_addr, ip_addr_t ip_dest_addr, uint16_t l2_encap_proto);
diff --git a/qca-nss-ecm/frontends/cmn/ecm_ported_ipv4.c b/qca-nss-ecm/frontends/cmn/ecm_ported_ipv4.c
new file mode 100644
index 0000000..faeab93
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_ported_ipv4.c
@@ -0,0 +1,1099 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/debugfs.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <net/addrconf.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#ifdef ECM_FRONT_END_SFE_ENABLE
+#include <sfe_api.h>
+#endif
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+#include <net/vxlan.h>
+#endif
+#include <linux/netfilter/nf_conntrack_tftp.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_PORTED_IPV4_DEBUG_LEVEL
+
+#ifdef ECM_FRONT_END_NSS_ENABLE
+#include <nss_api_if.h>
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+#include "nss_ipsec_cmn.h"
+#endif
+#endif
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#ifdef ECM_FRONT_END_SFE_ENABLE
+#include "ecm_sfe_ported_ipv4.h"
+#include "ecm_sfe_common.h"
+#endif
+#ifdef ECM_FRONT_END_NSS_ENABLE
+#include "ecm_nss_ported_ipv4.h"
+#include "ecm_nss_ipv4.h"
+#include "ecm_nss_common.h"
+#endif
+#include "ecm_front_end_common.h"
+#include "ecm_ipv4.h"
+#include "ecm_ae_classifier_public.h"
+#include "ecm_ae_classifier.h"
+
+/*
+ * ecm_ported_ipv4_process()
+ *	Process a ported packet
+ */
+unsigned int ecm_ported_ipv4_process(struct net_device *out_dev, struct net_device *out_dev_nat,
+							struct net_device *in_dev, struct net_device *in_dev_nat,
+							uint8_t *src_node_addr, uint8_t *src_node_addr_nat,
+							uint8_t *dest_node_addr, uint8_t *dest_node_addr_nat,
+							bool can_accel, bool is_routed, bool is_l2_encap, struct sk_buff *skb,
+							struct ecm_tracker_ip_header *iph,
+							struct nf_conn *ct, ecm_tracker_sender_type_t sender, ecm_db_direction_t ecm_dir,
+							struct nf_conntrack_tuple *orig_tuple, struct nf_conntrack_tuple *reply_tuple,
+							ip_addr_t ip_src_addr, ip_addr_t ip_dest_addr,
+							ip_addr_t ip_src_addr_nat, ip_addr_t ip_dest_addr_nat, uint16_t l2_encap_proto)
+{
+	struct tcphdr *tcp_hdr;
+	struct tcphdr tcp_hdr_buff;
+	struct udphdr *udp_hdr;
+	struct udphdr udp_hdr_buff;
+	int src_port;
+	int src_port_nat;
+	int dest_port;
+	int dest_port_nat;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci = NULL;
+	ip_addr_t match_addr;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	ecm_db_timer_group_t ci_orig_timer_group;
+	struct ecm_classifier_process_response prevalent_pr;
+	int protocol = (int)orig_tuple->dst.protonum;
+	__be16 *layer4hdr = NULL;
+
+	if (protocol == IPPROTO_TCP) {
+
+		if (likely(ct)) {
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+			/*
+			 * Set the DSCP conntrack extension. These values will be
+			 * used in the DSCP classifier for setting them quickly in the
+			 * classifier response.
+			 */
+			ecm_front_end_tcp_set_dscp_ext(ct, iph, skb, sender);
+#endif
+			/*
+			 * Unconfirmed connection may be dropped by Linux at the final step,
+			 * So we don't allow acceleration for the unconfirmed connections.
+			 */
+			if (!nf_ct_is_confirmed(ct)) {
+				DEBUG_WARN("%px: Unconfirmed TCP connection\n", ct);
+				return NF_ACCEPT;
+			}
+
+			/*
+			 * Don't try to manage a non-established connection.
+			 */
+			if (!test_bit(IPS_ASSURED_BIT, &ct->status)) {
+				DEBUG_WARN("%px: Non-established TCP connection\n", ct);
+				return NF_ACCEPT;
+			}
+		}
+
+		/*
+		 * Extract TCP header to obtain port information
+		 */
+		tcp_hdr = ecm_tracker_tcp_check_header_and_read(skb, iph, &tcp_hdr_buff);
+		if (unlikely(!tcp_hdr)) {
+			DEBUG_WARN("TCP packet header %px\n", skb);
+			return NF_ACCEPT;
+		}
+
+		layer4hdr = (__be16 *)tcp_hdr;
+
+		/*
+		 * Now extract information, if we have conntrack then use that (which would already be in the tuples)
+		 */
+		if (unlikely(!ct)) {
+			orig_tuple->src.u.tcp.port = tcp_hdr->source;
+			orig_tuple->dst.u.tcp.port = tcp_hdr->dest;
+			reply_tuple->src.u.tcp.port = tcp_hdr->dest;
+			reply_tuple->dst.u.tcp.port = tcp_hdr->source;
+		}
+
+		/*
+		 * Extract transport port information
+		 * Refer to the ecm_ipv4_process() for information on how we extract this information.
+		 */
+		if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+			if ((ecm_dir == ECM_DB_DIRECTION_EGRESS_NAT) || (ecm_dir == ECM_DB_DIRECTION_NON_NAT)) {
+				src_port = ntohs(orig_tuple->src.u.tcp.port);
+				dest_port = ntohs(orig_tuple->dst.u.tcp.port);
+				dest_port_nat = ntohs(reply_tuple->src.u.tcp.port);
+				src_port_nat = ntohs(reply_tuple->dst.u.tcp.port);
+			} else if (ecm_dir == ECM_DB_DIRECTION_INGRESS_NAT) {
+				src_port = ntohs(orig_tuple->src.u.tcp.port);
+				dest_port_nat = ntohs(orig_tuple->dst.u.tcp.port);
+				dest_port = ntohs(reply_tuple->src.u.tcp.port);
+				src_port_nat = ntohs(reply_tuple->dst.u.tcp.port);
+			} else if (ecm_dir == ECM_DB_DIRECTION_BRIDGED) {
+				src_port = ntohs(orig_tuple->src.u.tcp.port);
+				dest_port = ntohs(orig_tuple->dst.u.tcp.port);
+				dest_port_nat = ntohs(reply_tuple->src.u.tcp.port);
+				src_port_nat = ntohs(reply_tuple->dst.u.tcp.port);
+			} else {
+				DEBUG_ASSERT(false, "Unhandled ecm_dir: %d\n", ecm_dir);
+			}
+		} else {
+			if ((ecm_dir == ECM_DB_DIRECTION_EGRESS_NAT) || (ecm_dir == ECM_DB_DIRECTION_NON_NAT)) {
+				dest_port = ntohs(orig_tuple->src.u.tcp.port);
+				src_port = ntohs(orig_tuple->dst.u.tcp.port);
+				src_port_nat = ntohs(reply_tuple->src.u.tcp.port);
+				dest_port_nat = ntohs(reply_tuple->dst.u.tcp.port);
+			} else if (ecm_dir == ECM_DB_DIRECTION_INGRESS_NAT) {
+				dest_port = ntohs(orig_tuple->src.u.tcp.port);
+				src_port_nat = ntohs(orig_tuple->dst.u.tcp.port);
+				src_port = ntohs(reply_tuple->src.u.tcp.port);
+				dest_port_nat = ntohs(reply_tuple->dst.u.tcp.port);
+			} else if (ecm_dir == ECM_DB_DIRECTION_BRIDGED) {
+				dest_port = ntohs(orig_tuple->src.u.tcp.port);
+				src_port = ntohs(orig_tuple->dst.u.tcp.port);
+				src_port_nat = ntohs(reply_tuple->src.u.tcp.port);
+				dest_port_nat = ntohs(reply_tuple->dst.u.tcp.port);
+			} else {
+				DEBUG_ASSERT(false, "Unhandled ecm_dir: %d\n", ecm_dir);
+			}
+		}
+
+		DEBUG_TRACE("TCP src: " ECM_IP_ADDR_DOT_FMT "(" ECM_IP_ADDR_DOT_FMT "):%d(%d), dest: " ECM_IP_ADDR_DOT_FMT "(" ECM_IP_ADDR_DOT_FMT "):%d(%d), dir %d\n",
+				ECM_IP_ADDR_TO_DOT(ip_src_addr), ECM_IP_ADDR_TO_DOT(ip_src_addr_nat), src_port, src_port_nat, ECM_IP_ADDR_TO_DOT(ip_dest_addr),
+				ECM_IP_ADDR_TO_DOT(ip_dest_addr_nat), dest_port, dest_port_nat, ecm_dir);
+	} else if (protocol == IPPROTO_UDP) {
+		/*
+		 * Unconfirmed connection may be dropped by Linux at the final step,
+		 * So we don't allow acceleration for the unconfirmed connections.
+		 */
+		if (likely(ct) && !nf_ct_is_confirmed(ct)) {
+			DEBUG_WARN("%px: Unconfirmed UDP connection\n", ct);
+			return NF_ACCEPT;
+		}
+
+		/*
+		 * Extract UDP header to obtain port information
+		 */
+		udp_hdr = ecm_tracker_udp_check_header_and_read(skb, iph, &udp_hdr_buff);
+		if (unlikely(!udp_hdr)) {
+			DEBUG_WARN("Invalid UDP header in skb %px\n", skb);
+			return NF_ACCEPT;
+		}
+
+		layer4hdr = (__be16 *)udp_hdr;
+
+		/*
+		 * Now extract information, if we have conntrack then use that (which would already be in the tuples)
+		 */
+		if (unlikely(!ct)) {
+			orig_tuple->src.u.udp.port = udp_hdr->source;
+			orig_tuple->dst.u.udp.port = udp_hdr->dest;
+			reply_tuple->src.u.udp.port = udp_hdr->dest;
+			reply_tuple->dst.u.udp.port = udp_hdr->source;
+		}
+
+		/*
+		 * Extract transport port information
+		 * Refer to the ecm_ipv4_process() for information on how we extract this information.
+		 */
+		if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+			if ((ecm_dir == ECM_DB_DIRECTION_EGRESS_NAT) || (ecm_dir == ECM_DB_DIRECTION_NON_NAT)) {
+				src_port = ntohs(orig_tuple->src.u.udp.port);
+				dest_port = ntohs(orig_tuple->dst.u.udp.port);
+				dest_port_nat = ntohs(reply_tuple->src.u.udp.port);
+				src_port_nat = ntohs(reply_tuple->dst.u.udp.port);
+			} else if (ecm_dir == ECM_DB_DIRECTION_INGRESS_NAT) {
+				src_port = ntohs(orig_tuple->src.u.udp.port);
+				dest_port_nat = ntohs(orig_tuple->dst.u.udp.port);
+				dest_port = ntohs(reply_tuple->src.u.udp.port);
+				src_port_nat = ntohs(reply_tuple->dst.u.udp.port);
+			} else if (ecm_dir == ECM_DB_DIRECTION_BRIDGED) {
+				src_port = ntohs(orig_tuple->src.u.udp.port);
+				dest_port = ntohs(orig_tuple->dst.u.udp.port);
+				dest_port_nat = ntohs(reply_tuple->src.u.udp.port);
+				src_port_nat = ntohs(reply_tuple->dst.u.udp.port);
+			} else {
+				DEBUG_ASSERT(false, "Unhandled ecm_dir: %d\n", ecm_dir);
+			}
+		} else {
+			if ((ecm_dir == ECM_DB_DIRECTION_EGRESS_NAT) || (ecm_dir == ECM_DB_DIRECTION_NON_NAT)) {
+				dest_port = ntohs(orig_tuple->src.u.udp.port);
+				src_port = ntohs(orig_tuple->dst.u.udp.port);
+				src_port_nat = ntohs(reply_tuple->src.u.udp.port);
+				dest_port_nat = ntohs(reply_tuple->dst.u.udp.port);
+			} else if (ecm_dir == ECM_DB_DIRECTION_INGRESS_NAT) {
+				dest_port = ntohs(orig_tuple->src.u.udp.port);
+				src_port_nat = ntohs(orig_tuple->dst.u.udp.port);
+				src_port = ntohs(reply_tuple->src.u.udp.port);
+				dest_port_nat = ntohs(reply_tuple->dst.u.udp.port);
+			} else if (ecm_dir == ECM_DB_DIRECTION_BRIDGED) {
+				dest_port = ntohs(orig_tuple->src.u.udp.port);
+				src_port = ntohs(orig_tuple->dst.u.udp.port);
+				src_port_nat = ntohs(reply_tuple->src.u.udp.port);
+				dest_port_nat = ntohs(reply_tuple->dst.u.udp.port);
+			} else {
+				DEBUG_ASSERT(false, "Unhandled ecm_dir: %d\n", ecm_dir);
+			}
+		}
+
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+		if ((netif_is_vxlan(in_dev) || netif_is_vxlan(out_dev)) && is_routed) {
+			DEBUG_TRACE("VxLAN outer connection, make src and dest idents same\n");
+			src_port = src_port_nat = dest_port;
+		}
+#endif
+		if (ct && nfct_help(ct) && (dest_port == TFTP_PORT)) {
+			DEBUG_TRACE("%px: Connection has helper but protocol is TFTP, it can be accelerated\n", ct);
+			can_accel = true;
+		}
+
+		DEBUG_TRACE("UDP src: " ECM_IP_ADDR_DOT_FMT "(" ECM_IP_ADDR_DOT_FMT "):%d(%d), dest: " ECM_IP_ADDR_DOT_FMT "(" ECM_IP_ADDR_DOT_FMT "):%d(%d), dir %d\n",
+				ECM_IP_ADDR_TO_DOT(ip_src_addr), ECM_IP_ADDR_TO_DOT(ip_src_addr_nat), src_port, src_port_nat, ECM_IP_ADDR_TO_DOT(ip_dest_addr),
+				ECM_IP_ADDR_TO_DOT(ip_dest_addr_nat), dest_port, dest_port_nat, ecm_dir);
+	} else {
+		DEBUG_WARN("Wrong protocol: %d\n", protocol);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Look up a connection
+	 */
+	ci = ecm_db_connection_find_and_ref(ip_src_addr, ip_dest_addr, protocol, src_port, dest_port);
+
+	/*
+	 * If there is no existing connection then create a new one.
+	 */
+	if (unlikely(!ci)) {
+		struct ecm_db_mapping_instance *mi[ECM_DB_OBJ_DIR_MAX];
+		struct ecm_db_node_instance *ni[ECM_DB_OBJ_DIR_MAX];
+		struct ecm_classifier_default_instance *dci;
+		struct ecm_db_connection_instance *nci;
+		ecm_classifier_type_t classifier_type;
+		int32_t to_list_first;
+		struct ecm_db_iface_instance *to_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+		int32_t to_nat_list_first;
+		struct ecm_db_iface_instance *to_nat_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+		int32_t from_list_first;
+		struct ecm_db_iface_instance *from_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+		int32_t from_nat_list_first;
+		struct ecm_db_iface_instance *from_nat_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+		struct ecm_front_end_interface_construct_instance efeici;
+		struct ecm_front_end_ovs_params ovs_params[ECM_DB_OBJ_DIR_MAX];
+		enum ecm_front_end_type fe_type;
+		ecm_ae_classifier_result_t ae_result;
+		ecm_db_connection_defunct_callback_t defunct_callback;
+
+		DEBUG_INFO("New ported connection from " ECM_IP_ADDR_DOT_FMT ":%u to " ECM_IP_ADDR_DOT_FMT ":%u protocol: %d\n",
+				ECM_IP_ADDR_TO_DOT(ip_src_addr), src_port, ECM_IP_ADDR_TO_DOT(ip_dest_addr), dest_port, protocol);
+
+		/*
+		 * Before we attempt to create the connection are we being terminated?
+		 */
+		spin_lock_bh(&ecm_ipv4_lock);
+		if (ecm_ipv4_terminate_pending) {
+			spin_unlock_bh(&ecm_ipv4_lock);
+			DEBUG_WARN("Terminating\n");
+
+			/*
+			 * As we are terminating we just allow the packet to pass - it's no longer our concern
+			 */
+			return NF_ACCEPT;
+		}
+		spin_unlock_bh(&ecm_ipv4_lock);
+
+		/*
+		 * Does this connection have a conntrack entry?
+		 */
+		if (ct) {
+			if (protocol == IPPROTO_TCP) {
+				/*
+				 * No point in establishing a connection for one that is closing
+				 */
+				spin_lock_bh(&ct->lock);
+				if (ct->proto.tcp.state >= TCP_CONNTRACK_FIN_WAIT && ct->proto.tcp.state <= TCP_CONNTRACK_CLOSE) {
+					spin_unlock_bh(&ct->lock);
+					DEBUG_TRACE("%px: Connection in termination state %#X\n", ct, ct->proto.tcp.state);
+					return NF_ACCEPT;
+				}
+				spin_unlock_bh(&ct->lock);
+			}
+		}
+
+		/*
+		 * Connection must have a front end instance associated with it
+		 */
+		fe_type = ecm_front_end_type_get();
+		switch (fe_type) {
+#if defined(ECM_FRONT_END_NSS_ENABLE) && defined(ECM_FRONT_END_SFE_ENABLE)
+		case ECM_FRONT_END_TYPE_HYBRID:
+		{
+			ecm_ae_classifier_get_t ae_get;
+			struct ecm_ae_classifier_info ae_info;
+
+			ecm_ae_classifier_select_info_fill(ip_src_addr, ip_dest_addr,
+							  src_port, dest_port, protocol, 4,
+							  is_routed, false,
+							  &ae_info);
+
+			rcu_read_lock();
+			ae_get = rcu_dereference(ae_ops.ae_get);
+			ae_result = ae_get(&ae_info);
+			rcu_read_unlock();
+
+			DEBUG_TRACE("front end type hybrid, ae_result: %d\n", ae_result);
+			break;
+		}
+#endif
+#ifdef ECM_FRONT_END_NSS_ENABLE
+		case ECM_FRONT_END_TYPE_NSS:
+			DEBUG_TRACE("front end type NSS, ae_result: %d\n", ae_result);
+			ae_result = ECM_AE_CLASSIFIER_RESULT_NSS;
+			break;
+#endif
+#ifdef ECM_FRONT_END_SFE_ENABLE
+		case ECM_FRONT_END_TYPE_SFE:
+			ae_result = ECM_AE_CLASSIFIER_RESULT_SFE;
+			DEBUG_TRACE("front end type SFE, ae_result: %d\n", ae_result);
+			break;
+#endif
+		default:
+			DEBUG_WARN("front end type: %d is not supported\n", fe_type);
+			return NF_ACCEPT;
+		}
+
+		/*
+		 * Check the ae_result.
+		 * 1. If NSS, allocate NSS ipv4 ported connection instance
+		 * 2. If SFE, allocate SFE ipv4 ported connection instance
+		 * 3. If NONE, allocate ported connection instance based on the is_routed flag.
+		 *    If it is set allocate SFE ipv4 ported connection instance with can_accel flag is set to false, otherwise
+		 *    allocate NSS ipv4 ported connection instance with can_accel flag is set to false.
+		 *    By doing this ECM will not ask again and again to the external module. If external module wants to
+		 *    accelerate this flow later, the flow needs to be defuncted first.
+		 * 4. If NOT_YET, the connection will not be allocated in the database and the next flow will be asked again
+		 *    to the external module.
+		 * 5. If any other type is returned, ASSERT.
+		 *
+		 * As an example here, we accelerate the routed flows on SFE, bridge flows on NSS.
+		 */
+		switch(ae_result) {
+#ifdef ECM_FRONT_END_NSS_ENABLE
+		case ECM_AE_CLASSIFIER_RESULT_NSS:
+			if (!ecm_nss_feature_check(skb, iph)) {
+				DEBUG_WARN("Unsupported feature found for NSS acceleration\n");
+				return NF_ACCEPT;
+			}
+			feci = (struct ecm_front_end_connection_instance *)ecm_nss_ported_ipv4_connection_instance_alloc(can_accel, protocol, &nci);
+			defunct_callback = ecm_nss_ported_ipv4_connection_defunct_callback;
+			break;
+#endif
+#ifdef ECM_FRONT_END_SFE_ENABLE
+		case ECM_AE_CLASSIFIER_RESULT_SFE:
+			if (!ecm_sfe_feature_check(skb, iph, is_routed)) {
+				DEBUG_WARN("Unsupported feature found for SFE acceleration\n");
+				return NF_ACCEPT;
+			}
+
+			feci = (struct ecm_front_end_connection_instance *)ecm_sfe_ported_ipv4_connection_instance_alloc(can_accel, protocol, &nci);
+			defunct_callback = ecm_sfe_ported_ipv4_connection_defunct_callback;
+			break;
+#endif
+#if defined(ECM_FRONT_END_NSS_ENABLE) && defined(ECM_FRONT_END_SFE_ENABLE)
+		case ECM_AE_CLASSIFIER_RESULT_NONE:
+			if (is_routed) {
+				feci = (struct ecm_front_end_connection_instance *)ecm_sfe_ported_ipv4_connection_instance_alloc(false, protocol, &nci);
+				defunct_callback = ecm_sfe_ported_ipv4_connection_defunct_callback;
+			} else {
+				feci = (struct ecm_front_end_connection_instance *)ecm_nss_ported_ipv4_connection_instance_alloc(false, protocol, &nci);
+				defunct_callback = ecm_nss_ported_ipv4_connection_defunct_callback;
+			}
+			break;
+#endif
+		case ECM_AE_CLASSIFIER_RESULT_NOT_YET:
+			return NF_ACCEPT;
+
+		default:
+			DEBUG_ASSERT(NULL, "unexpected ae_result: %d\n", ae_result);
+		}
+
+		if (!feci) {
+			DEBUG_WARN("Failed to allocate front end\n");
+			return NF_ACCEPT;
+		}
+
+		if (!ecm_front_end_ipv4_interface_construct_set_and_hold(skb, sender, ecm_dir, is_routed,
+							in_dev, out_dev,
+							ip_src_addr, ip_src_addr_nat,
+							ip_dest_addr, ip_dest_addr_nat,
+							&efeici)) {
+
+			DEBUG_WARN("ECM front end ipv4 interface construct set failed for routed traffic\n");
+			goto fail_1;
+		}
+
+		ecm_front_end_fill_ovs_params(ovs_params,
+					      ip_src_addr, ip_src_addr_nat,
+					      ip_dest_addr, ip_dest_addr_nat,
+					      src_port, src_port_nat,
+					      dest_port, dest_port_nat, ecm_dir);
+
+		/*
+		 * Get the src and destination mappings.
+		 * For this we also need the interface lists which we also set upon the new connection while we are at it.
+		 * GGG TODO rework terms of "src/dest" - these need to be named consistently as from/to as per database terms.
+		 * GGG TODO The empty list checks should not be needed, mapping_establish_and_ref() should fail out if there is no list anyway.
+		 */
+		DEBUG_TRACE("%px: Create the 'from' interface heirarchy list\n", nci);
+		from_list_first = ecm_interface_heirarchy_construct(feci, from_list, efeici.from_dev, efeici.from_other_dev, ip_dest_addr, efeici.from_mac_lookup_ip_addr, ip_src_addr, 4, protocol, in_dev, is_routed, in_dev, src_node_addr, dest_node_addr, layer4hdr, skb, &ovs_params[ECM_DB_OBJ_DIR_FROM]);
+		if (from_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			DEBUG_WARN("Failed to obtain 'from' heirarchy list\n");
+			goto fail_2;
+		}
+		ecm_db_connection_interfaces_reset(nci, from_list, from_list_first, ECM_DB_OBJ_DIR_FROM);
+
+		DEBUG_TRACE("%px: Create source node\n", nci);
+		ni[ECM_DB_OBJ_DIR_FROM] = ecm_ipv4_node_establish_and_ref(feci, efeici.from_dev, efeici.from_mac_lookup_ip_addr, from_list, from_list_first, src_node_addr, skb);
+		ecm_db_connection_interfaces_deref(from_list, from_list_first);
+		if (!ni[ECM_DB_OBJ_DIR_FROM]) {
+			DEBUG_WARN("Failed to establish source node\n");
+			goto fail_2;
+		}
+
+		DEBUG_TRACE("%px: Create source mapping\n", nci);
+		mi[ECM_DB_OBJ_DIR_FROM] = ecm_ipv4_mapping_establish_and_ref(ip_src_addr, src_port);
+		if (!mi[ECM_DB_OBJ_DIR_FROM]) {
+			DEBUG_WARN("Failed to establish src mapping\n");
+			goto fail_3;
+		}
+
+		DEBUG_TRACE("%px: Create the 'to' interface heirarchy list\n", nci);
+		to_list_first = ecm_interface_heirarchy_construct(feci, to_list, efeici.to_dev, efeici.to_other_dev, ip_src_addr, efeici.to_mac_lookup_ip_addr, ip_dest_addr, 4, protocol, out_dev, is_routed, in_dev, dest_node_addr, src_node_addr, layer4hdr, skb, &ovs_params[ECM_DB_OBJ_DIR_TO]);
+		if (to_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			DEBUG_WARN("Failed to obtain 'to' heirarchy list\n");
+			goto fail_4;
+		}
+		ecm_db_connection_interfaces_reset(nci, to_list, to_list_first, ECM_DB_OBJ_DIR_TO);
+
+		DEBUG_TRACE("%px: Create dest node\n", nci);
+		ni[ECM_DB_OBJ_DIR_TO] = ecm_ipv4_node_establish_and_ref(feci, efeici.to_dev, efeici.to_mac_lookup_ip_addr, to_list, to_list_first, dest_node_addr, skb);
+		ecm_db_connection_interfaces_deref(to_list, to_list_first);
+		if (!ni[ECM_DB_OBJ_DIR_TO]) {
+			DEBUG_WARN("Failed to establish dest node\n");
+			goto fail_4;
+		}
+
+		DEBUG_TRACE("%px: Create dest mapping\n", nci);
+		mi[ECM_DB_OBJ_DIR_TO] = ecm_ipv4_mapping_establish_and_ref(ip_dest_addr, dest_port);
+		if (!mi[ECM_DB_OBJ_DIR_TO]) {
+			DEBUG_WARN("Failed to establish dest mapping\n");
+			goto fail_5;
+		}
+
+		/*
+		 * Get the src and destination NAT mappings
+		 * For this we also need the interface lists which we also set upon the new connection while we are at it.
+		 * GGG TODO rework terms of "src/dest" - these need to be named consistently as from/to as per database terms.
+		 * GGG TODO The empty list checks should not be needed, mapping_establish_and_ref() should fail out if there is no list anyway.
+		 */
+		DEBUG_TRACE("%px: Create the 'from NAT' interface heirarchy list\n", nci);
+		if ((in_dev->type == ECM_ARPHRD_IPSEC_TUNNEL_TYPE) && (protocol == IPPROTO_UDP) && (dest_port == 4500)) {
+			from_nat_list_first = ecm_interface_heirarchy_construct(feci, from_nat_list, efeici.from_nat_dev, efeici.from_nat_other_dev, ip_dest_addr, efeici.from_nat_mac_lookup_ip_addr, ip_src_addr_nat, 4, protocol, in_dev, is_routed, in_dev, src_node_addr_nat, dest_node_addr_nat, layer4hdr, skb, &ovs_params[ECM_DB_OBJ_DIR_FROM_NAT]);
+		} else {
+			from_nat_list_first = ecm_interface_heirarchy_construct(feci, from_nat_list, efeici.from_nat_dev, efeici.from_nat_other_dev, ip_dest_addr, efeici.from_nat_mac_lookup_ip_addr, ip_src_addr_nat, 4, protocol, in_dev_nat, is_routed, in_dev_nat, src_node_addr_nat, dest_node_addr_nat, layer4hdr, skb, &ovs_params[ECM_DB_OBJ_DIR_FROM_NAT]);
+		}
+
+		if (from_nat_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			DEBUG_WARN("Failed to obtain 'from NAT' heirarchy list\n");
+			goto fail_6;
+		}
+		ecm_db_connection_interfaces_reset(nci, from_nat_list, from_nat_list_first, ECM_DB_OBJ_DIR_FROM_NAT);
+
+		DEBUG_TRACE("%px: Create source nat node\n", nci);
+		ni[ECM_DB_OBJ_DIR_FROM_NAT] = ecm_ipv4_node_establish_and_ref(feci, efeici.from_nat_dev, efeici.from_nat_mac_lookup_ip_addr, from_nat_list, from_nat_list_first, src_node_addr_nat, skb);
+		ecm_db_connection_interfaces_deref(from_nat_list, from_nat_list_first);
+		if (!ni[ECM_DB_OBJ_DIR_FROM_NAT]) {
+			DEBUG_WARN("Failed to establish source nat node\n");
+			goto fail_6;
+		}
+
+		mi[ECM_DB_OBJ_DIR_FROM_NAT] = ecm_ipv4_mapping_establish_and_ref(ip_src_addr_nat, src_port_nat);
+		if (!mi[ECM_DB_OBJ_DIR_FROM_NAT]) {
+			DEBUG_WARN("Failed to establish src nat mapping\n");
+			goto fail_7;
+		}
+
+		DEBUG_TRACE("%px: Create the 'to NAT' interface heirarchy list\n", nci);
+		to_nat_list_first = ecm_interface_heirarchy_construct(feci, to_nat_list, efeici.to_nat_dev, efeici.to_nat_other_dev, ip_src_addr, efeici.to_nat_mac_lookup_ip_addr, ip_dest_addr_nat, 4, protocol, out_dev_nat, is_routed, in_dev, dest_node_addr_nat, src_node_addr_nat, layer4hdr, skb, &ovs_params[ECM_DB_OBJ_DIR_TO_NAT]);
+		if (to_nat_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			DEBUG_WARN("Failed to obtain 'to NAT' heirarchy list\n");
+			goto fail_8;
+		}
+		ecm_db_connection_interfaces_reset(nci, to_nat_list, to_nat_list_first, ECM_DB_OBJ_DIR_TO_NAT);
+
+		DEBUG_TRACE("%px: Create dest nat node\n", nci);
+		ni[ECM_DB_OBJ_DIR_TO_NAT] = ecm_ipv4_node_establish_and_ref(feci, efeici.to_nat_dev, efeici.to_nat_mac_lookup_ip_addr, to_nat_list, to_nat_list_first, dest_node_addr_nat, skb);
+
+		ecm_db_connection_interfaces_deref(to_nat_list, to_nat_list_first);
+		if (!ni[ECM_DB_OBJ_DIR_TO_NAT]) {
+			DEBUG_WARN("Failed to establish dest nat node\n");
+			goto fail_8;
+		}
+
+		mi[ECM_DB_OBJ_DIR_TO_NAT] = ecm_ipv4_mapping_establish_and_ref(ip_dest_addr_nat, dest_port_nat);
+		if (!mi[ECM_DB_OBJ_DIR_TO_NAT]) {
+			DEBUG_WARN("Failed to establish dest mapping\n");
+			goto fail_9;
+		}
+
+		/*
+		 * Every connection also needs a default classifier which is considered 'special' to be assigned
+		 */
+		dci = ecm_classifier_default_instance_alloc(nci, protocol, ecm_dir, src_port, dest_port);
+		if (!dci) {
+			DEBUG_WARN("Failed to allocate default classifier\n");
+			goto fail_10;
+		}
+		ecm_db_connection_classifier_assign(nci, (struct ecm_classifier_instance *)dci);
+
+		/*
+		 * Every connection starts with a full complement of classifiers assigned.
+		 * NOTE: Default classifier is a special case considered previously
+		 */
+		for (classifier_type = ECM_CLASSIFIER_TYPE_DEFAULT + 1; classifier_type < ECM_CLASSIFIER_TYPES; ++classifier_type) {
+			struct ecm_classifier_instance *aci = ecm_classifier_assign_classifier(nci, classifier_type);
+			if (aci) {
+				aci->deref(aci);
+			} else {
+				DEBUG_WARN("Failed to allocate classifiers assignments\n");
+				goto fail_11;
+			}
+		}
+
+		ecm_db_front_end_instance_ref_and_set(nci, feci);
+
+		ecm_db_connection_l2_encap_proto_set(nci, l2_encap_proto);
+
+		/*
+		 * Now add the connection into the database.
+		 * NOTE: In an SMP situation such as ours there is a possibility that more than one packet for the same
+		 * connection is being processed simultaneously.
+		 * We *could* end up creating more than one connection instance for the same actual connection.
+		 * To guard against this we now perform a mutex'd lookup of the connection + add once more - another cpu may have created it before us.
+		 */
+		spin_lock_bh(&ecm_ipv4_lock);
+		ci = ecm_db_connection_find_and_ref(ip_src_addr, ip_dest_addr, protocol, src_port, dest_port);
+		if (ci) {
+			/*
+			 * Another cpu created the same connection before us - use the one we just found
+			 */
+			spin_unlock_bh(&ecm_ipv4_lock);
+			ecm_db_connection_deref(nci);
+		} else {
+			ecm_db_timer_group_t tg;
+			ecm_tracker_sender_state_t src_state;
+			ecm_tracker_sender_state_t dest_state;
+			ecm_tracker_connection_state_t state;
+			struct ecm_tracker_instance *ti;
+
+			/*
+			 * Ask tracker for timer group to set the connection to initially.
+			 */
+			ti = dci->tracker_get_and_ref(dci);
+			ti->state_get(ti, &src_state, &dest_state, &state, &tg);
+			ti->deref(ti);
+
+			/*
+			 * Add the new connection we created into the database
+			 * NOTE: assign to a short timer group for now - it is the assigned classifiers responsibility to do this
+			 */
+			ecm_db_connection_add(nci, mi, ni,
+					4, protocol, ecm_dir,
+					NULL /* final callback */,
+					defunct_callback,
+					tg, is_routed, nci);
+
+			spin_unlock_bh(&ecm_ipv4_lock);
+
+			ci = nci;
+			DEBUG_INFO("%px: New ported connection created\n", ci);
+		}
+
+		/*
+		 * No longer need referenecs to the objects we created
+		 */
+		dci->base.deref((struct ecm_classifier_instance *)dci);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO_NAT]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO_NAT]);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM_NAT]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM_NAT]);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+		ecm_front_end_ipv4_interface_construct_netdev_put(&efeici);
+		feci->deref(feci);
+
+		goto done;
+fail_11:
+		dci->base.deref((struct ecm_classifier_instance *)dci);
+fail_10:
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO_NAT]);
+fail_9:
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO_NAT]);
+fail_8:
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM_NAT]);
+fail_7:
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM_NAT]);
+fail_6:
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+fail_5:
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+fail_4:
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+fail_3:
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+fail_2:
+		ecm_front_end_ipv4_interface_construct_netdev_put(&efeici);
+fail_1:
+		feci->deref(feci);
+		ecm_db_connection_deref(nci);
+		return NF_ACCEPT;
+done:
+		;
+	}
+
+	/*
+	 * Bridged traffic goes through the IP post routing hook as well after it
+	 * finishes the bridge post routing hook. In that case, ecm_dir will become
+	 * as Non-Nat since the is_routed flag is true. But the is_routed flag of the connection
+	 * was set as false while the packet was going throught the bridge post routing
+	 * hook. So, we need to check if the is_routed flag and ecm_dir matches the routed
+	 * flow condition. If it doesn't, do not process the flow.
+	 */
+	if (!ecm_db_connection_is_routed_get(ci) && (ecm_dir == ECM_DB_DIRECTION_NON_NAT)) {
+		DEBUG_TRACE("%px: ignore route hook path for bridged packet\n", ci);
+		ecm_db_connection_deref(ci);
+		return NF_ACCEPT;
+	}
+
+#if defined(CONFIG_NET_CLS_ACT) && defined(ECM_CLASSIFIER_DSCP_IGS) && defined(ECM_FRONT_END_NSS_ENABLE)
+	/*
+	 * Check if IGS feature is enabled or not.
+	 */
+	if (unlikely(ecm_interface_igs_enabled)) {
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+		if (feci->accel_engine == ECM_FRONT_END_ENGINE_NSS) {
+			if (!ecm_nss_common_igs_acceleration_is_allowed(feci, skb)) {
+				DEBUG_WARN("%px: IPv4 IGS acceleration denied\n", ci);
+				feci->deref(feci);
+				ecm_db_connection_deref(ci);
+				return NF_ACCEPT;
+			}
+		}
+		feci->deref(feci);
+	}
+#endif
+
+	/*
+	 * Identify which side of the connection is sending.
+	 * NOTE: This may be different than what sender is at the moment
+	 * given the connection we have located.
+	 */
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, match_addr);
+	if (ECM_IP_ADDR_MATCH(ip_src_addr, match_addr)) {
+		sender = ECM_TRACKER_SENDER_TYPE_SRC;
+	} else {
+		sender = ECM_TRACKER_SENDER_TYPE_DEST;
+	}
+
+	/*
+	 * In nat reflection scenarios SNAT rule is getting applied on the packet after packet
+	 * passed through bridge post routing hook
+	 *
+	 * Example
+	 * Consider following scenario where both WLAN PC and eth1 are part of same bridge
+	 * 192.168.1.3(WLAN PC)<-->192.168.1.1(DUT br-lan)---> 192.168.1.4(Eth1 PC)
+	 * When a DNAT is applied it is observed that following NAT rules are appended in iptables
+	 *
+	 * -A nat_reflection_out -s 192.168.1.0/24 -d 192.168.1.4/32 -p tcp -m tcp --dport 3389 -m comment --comment "wan" -j SNAT
+	 *		 --to-source 192.168.1.1
+	 * -A nat_reflection_out -s 192.168.1.0/24 -d 192.168.1.4/32 -p udp -m udp --dport 3389 -m comment --comment "wan" -j SNAT
+	 *		 --to-source 192.168.1.1
+	 *
+	 * This Shows that SNAT is getting applied on bridged packet also. However it is observed that
+	 * the SNAT is updated in ct after the packet has crossed this function through bridge hook.
+	 *
+	 * Hence Flushing the connection that was already created earlier if the ip_src_addr_nat value changes for same tuple in
+	 * subsequent packets
+	 */
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM_NAT, match_addr);
+	if (!ECM_IP_ADDR_MATCH(ip_src_addr_nat, match_addr) && ct && (sender == ECM_TRACKER_SENDER_TYPE_SRC)) {
+		/*
+		 * Force destruction of the connection my making it defunct
+		 */
+		ecm_db_connection_make_defunct(ci);
+		ecm_db_connection_deref(ci);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Return if timer no touch is set
+	 */
+	if (ecm_db_connection_defunct_timer_no_touch_get(ci)) {
+		DEBUG_TRACE("%px: No touch timer is set for this ci\n", ci);
+		if (protocol == IPPROTO_TCP) {
+			if (tcp_hdr->syn) {
+				DEBUG_TRACE("%px: TCP SYN Flag is seen in No Touch timer state, defunct connection\n", ci);
+				ecm_db_connection_make_defunct(ci);
+			}
+		}
+		ecm_db_connection_deref(ci);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Keep connection alive as we have seen activity
+	 */
+	if (!ecm_db_connection_defunct_timer_touch(ci)) {
+		ecm_db_connection_deref(ci);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Do we need to action generation change?
+	 */
+	if (unlikely(ecm_db_connection_regeneration_required_check(ci))) {
+		ecm_ipv4_connection_regenerate(ci, sender, out_dev, out_dev_nat, in_dev, in_dev_nat, layer4hdr, skb);
+	}
+
+	/*
+	 * Increment the slow path packet counter.
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	spin_lock_bh(&feci->lock);
+	feci->stats.slow_path_packets++;
+	spin_unlock_bh(&feci->lock);
+	feci->deref(feci);
+
+	/*
+	 * Iterate the assignments and call to process!
+	 * Policy implemented:
+	 * 1. Classifiers that say they are not relevant are unassigned and not actioned further.
+	 * 2. Any drop command from any classifier is honoured.
+	 * 3. All classifiers must action acceleration for accel to be honoured, any classifiers not sure of their relevance will stop acceleration.
+	 * 4. Only the highest priority classifier, that actions it, will have its qos tag honoured.
+	 * 5. Only the highest priority classifier, that actions it, will have its timer group honoured.
+	 */
+	DEBUG_TRACE("%px: process begin, skb: %px\n", ci, skb);
+	prevalent_pr.process_actions = 0;
+	prevalent_pr.drop = false;
+	prevalent_pr.flow_qos_tag = skb->priority;
+	prevalent_pr.return_qos_tag = skb->priority;
+	prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+	prevalent_pr.timer_group = ci_orig_timer_group = ecm_db_connection_timer_group_get(ci);
+
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_process_response aci_pr;
+		struct ecm_classifier_instance *aci;
+
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: process: %px, type: %d\n", ci, aci, aci->type_get(aci));
+		aci->process(aci, sender, iph, skb, &aci_pr);
+		DEBUG_TRACE("%px: aci_pr: process actions: %x, became relevant: %u, relevance: %d, drop: %d, "
+				"flow_qos_tag: %u, return_qos_tag: %u, accel_mode: %x, timer_group: %d\n",
+				ci, aci_pr.process_actions, aci_pr.became_relevant, aci_pr.relevance, aci_pr.drop,
+				aci_pr.flow_qos_tag, aci_pr.return_qos_tag, aci_pr.accel_mode, aci_pr.timer_group);
+
+		if (aci_pr.relevance == ECM_CLASSIFIER_RELEVANCE_NO) {
+			ecm_classifier_type_t aci_type;
+
+			/*
+			 * This classifier can be unassigned - PROVIDED it is not the default classifier
+			 */
+			aci_type = aci->type_get(aci);
+			if (aci_type == ECM_CLASSIFIER_TYPE_DEFAULT) {
+				continue;
+			}
+
+			DEBUG_INFO("%px: Classifier not relevant, unassign: %d", ci, aci_type);
+			ecm_db_connection_classifier_unassign(ci, aci);
+			continue;
+		}
+
+		/*
+		 * Yes or Maybe relevant.
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DROP) {
+			/*
+			 * Drop command from any classifier is actioned.
+			 */
+			DEBUG_TRACE("%px: wants drop: %px, type: %d, skb: %px\n", ci, aci, aci->type_get(aci), skb);
+			prevalent_pr.drop |= aci_pr.drop;
+		}
+
+		/*
+		 * Accel mode permission
+		 */
+		if (aci_pr.relevance == ECM_CLASSIFIER_RELEVANCE_MAYBE) {
+			/*
+			 * Classifier not sure of its relevance - cannot accel yet
+			 */
+			DEBUG_TRACE("%px: accel denied by maybe: %px, type: %d\n", ci, aci, aci->type_get(aci));
+			prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+		} else {
+			if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE) {
+				if (aci_pr.accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_NO) {
+					DEBUG_TRACE("%px: accel denied: %px, type: %d\n", ci, aci, aci->type_get(aci));
+					prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+				}
+				/* else yes or don't care about accel */
+			}
+		}
+
+		/*
+		 * Timer group (the last classifier i.e. the highest priority one) will 'win'
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP) {
+			DEBUG_TRACE("%px: timer group: %px, type: %d, group: %d\n", ci, aci, aci->type_get(aci), aci_pr.timer_group);
+			prevalent_pr.timer_group = aci_pr.timer_group;
+		}
+
+		/*
+		 * Timer group no touch action is set when classifier identified
+		 * that the connection should be defunct when timer group
+		 * expires, do not update timer group when the packets matching
+		 * this connection are received later.
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP_NO_TOUCH) {
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP_NO_TOUCH;
+		}
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, ingress vlan tags 0: %u, egress vlan tags 0: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.ingress_vlan_tag[0], aci_pr.egress_vlan_tag[0]);
+			prevalent_pr.ingress_vlan_tag[0] = aci_pr.ingress_vlan_tag[0];
+			prevalent_pr.egress_vlan_tag[0] = aci_pr.egress_vlan_tag[0];
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG;
+		}
+
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, ingress vlan tags 1: %u, egress vlan tags 1: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.ingress_vlan_tag[1], aci_pr.egress_vlan_tag[1]);
+			prevalent_pr.ingress_vlan_tag[1] = aci_pr.ingress_vlan_tag[1];
+			prevalent_pr.egress_vlan_tag[1] = aci_pr.egress_vlan_tag[1];
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG;
+		}
+#endif
+
+		/*
+		 * Qos tag (the last classifier i.e. the highest priority one) will 'win'
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, flow qos tag: %u, return qos tag: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.flow_qos_tag, aci_pr.return_qos_tag);
+			prevalent_pr.flow_qos_tag = aci_pr.flow_qos_tag;
+			prevalent_pr.return_qos_tag = aci_pr.return_qos_tag;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG;
+		}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+#ifdef ECM_CLASSIFIER_DSCP_IGS
+		/*
+		 * Ingress QoS tag
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, ingress flow qos tag: %u, ingress return qos tag: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.igs_flow_qos_tag, aci_pr.igs_return_qos_tag);
+			prevalent_pr.igs_flow_qos_tag = aci_pr.igs_flow_qos_tag;
+			prevalent_pr.igs_return_qos_tag = aci_pr.igs_return_qos_tag;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG;
+		}
+#endif
+		/*
+		 * If any classifier denied DSCP remarking then that overrides every classifier
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, DSCP remark denied\n",
+					ci, aci, aci->type_get(aci));
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY;
+			prevalent_pr.process_actions &= ~ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+		}
+
+		/*
+		 * DSCP remark action, but only if it has not been denied by any classifier
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+			if (!(prevalent_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY)) {
+				DEBUG_TRACE("%px: aci: %px, type: %d, DSCP remark wanted, flow_dscp: %u, return dscp: %u\n",
+						ci, aci, aci->type_get(aci), aci_pr.flow_dscp, aci_pr.return_dscp);
+				prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+				prevalent_pr.flow_dscp = aci_pr.flow_dscp;
+				prevalent_pr.return_dscp = aci_pr.return_dscp;
+			}
+		}
+
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_MARK) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, flow mark: %u, return mark: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.flow_mark, aci_pr.return_mark);
+			prevalent_pr.flow_mark = aci_pr.flow_mark;
+			prevalent_pr.return_mark = aci_pr.return_mark;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_MARK;
+		}
+#endif
+
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+		/*
+		 * E-Mesh Service Prioritization is Valid
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, E-Mesh Service Prioritization is valid\n",
+					ci, aci, aci->type_get(aci));
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW;
+		}
+#endif
+
+#ifdef ECM_CLASSIFIER_PCC_ENABLE
+		/*
+		 * Mirror flag
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_MIRROR_ENABLED) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, flow_mirror_ifindex: %d"
+					" return_mirror_ifindex: %d\n",
+					ci, aci, aci->type_get(aci),
+					aci_pr.flow_mirror_ifindex,
+					aci_pr.return_mirror_ifindex);
+			prevalent_pr.flow_mirror_ifindex = aci_pr.flow_mirror_ifindex;
+			prevalent_pr.return_mirror_ifindex = aci_pr.return_mirror_ifindex;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_MIRROR_ENABLED;
+		}
+#endif
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Set timer no touch
+	 */
+	if (prevalent_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP_NO_TOUCH) {
+		ecm_db_connection_defunct_timer_no_touch_set(ci);
+	}
+
+	/*
+	 * Change timer group?
+	 */
+	if (ci_orig_timer_group != prevalent_pr.timer_group) {
+		DEBUG_TRACE("%px: change timer group from: %d to: %d\n", ci, ci_orig_timer_group, prevalent_pr.timer_group);
+		ecm_db_connection_defunct_timer_reset(ci, prevalent_pr.timer_group);
+	}
+
+	/*
+	 * Drop?
+	 */
+	if (prevalent_pr.drop) {
+		DEBUG_TRACE("%px: drop: %px\n", ci, skb);
+		ecm_db_connection_data_totals_update_dropped(ci, (sender == ECM_TRACKER_SENDER_TYPE_SRC)? true : false, skb->len, 1);
+		ecm_db_connection_deref(ci);
+		return NF_ACCEPT;
+	}
+	ecm_db_connection_data_totals_update(ci, (sender == ECM_TRACKER_SENDER_TYPE_SRC)? true : false, skb->len, 1);
+
+	/*
+	 * Assign qos tag
+	 * GGG TODO Should we use sender to identify whether to use flow or return qos tag?
+	 */
+	skb->priority = prevalent_pr.flow_qos_tag;
+	DEBUG_TRACE("%px: skb priority: %u\n", ci, skb->priority);
+
+	/*
+	 * Accelerate?
+	 */
+	if (prevalent_pr.accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL) {
+		DEBUG_TRACE("%px: accel\n", ci);
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+		feci->accelerate(feci, &prevalent_pr, is_l2_encap, ct, skb);
+		feci->deref(feci);
+	}
+	ecm_db_connection_deref(ci);
+
+	return NF_ACCEPT;
+}
diff --git a/qca-nss-ecm/frontends/cmn/ecm_ported_ipv4.h b/qca-nss-ecm/frontends/cmn/ecm_ported_ipv4.h
new file mode 100644
index 0000000..f7d835c
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_ported_ipv4.h
@@ -0,0 +1,26 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern unsigned int ecm_ported_ipv4_process(struct net_device *out_dev, struct net_device *out_dev_nat,
+							struct net_device *in_dev, struct net_device *in_dev_nat,
+							uint8_t *src_node_addr, uint8_t *src_node_addr_nat,
+							uint8_t *dest_node_addr, uint8_t *dest_node_addr_nat,
+							bool can_accel, bool is_routed, bool is_l2_encap, struct sk_buff *skb,
+							struct ecm_tracker_ip_header *iph,
+							struct nf_conn *ct, ecm_tracker_sender_type_t sender, ecm_db_direction_t ecm_dir,
+							struct nf_conntrack_tuple *orig_tuple, struct nf_conntrack_tuple *reply_tuple,
+							ip_addr_t ip_src_addr, ip_addr_t ip_dest_addr, ip_addr_t ip_src_addr_nat,
+							ip_addr_t ip_dest_addr_nat, uint16_t l2_encap_proto);
diff --git a/qca-nss-ecm/frontends/cmn/ecm_ported_ipv6.c b/qca-nss-ecm/frontends/cmn/ecm_ported_ipv6.c
new file mode 100644
index 0000000..742a3a5
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_ported_ipv6.c
@@ -0,0 +1,971 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/debugfs.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/ip6_route.h>
+#include <net/ip6_fib.h>
+#include <net/addrconf.h>
+#include <net/ipv6.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in6.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv6.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv6/nf_conntrack_ipv6.h>
+#include <net/netfilter/ipv6/nf_defrag_ipv6.h>
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+#include <net/vxlan.h>
+#endif
+#include <linux/netfilter/nf_conntrack_tftp.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_PORTED_IPV6_DEBUG_LEVEL
+
+#ifdef ECM_FRONT_END_NSS_ENABLE
+#include <nss_api_if.h>
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+#include "nss_ipsec_cmn.h"
+#endif
+#endif
+
+#ifdef ECM_FRONT_END_SFE_ENABLE
+#include <sfe_api.h>
+#endif
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#ifdef ECM_FRONT_END_SFE_ENABLE
+#include "ecm_sfe_ported_ipv6.h"
+#include "ecm_sfe_common.h"
+#endif
+#ifdef ECM_FRONT_END_NSS_ENABLE
+#include "ecm_nss_ported_ipv6.h"
+#include "ecm_nss_ipv6.h"
+#include "ecm_nss_common.h"
+#endif
+#include "ecm_front_end_common.h"
+#include "ecm_ipv6.h"
+#include "ecm_ae_classifier_public.h"
+#include "ecm_ae_classifier.h"
+
+/*
+ * ecm_ported_ipv6_process()
+ *	Process a ported packet
+ */
+unsigned int ecm_ported_ipv6_process(struct net_device *out_dev,
+							struct net_device *in_dev,
+							uint8_t *src_node_addr,
+							uint8_t *dest_node_addr,
+							bool can_accel,  bool is_routed, bool is_l2_encap, struct sk_buff *skb,
+							struct ecm_tracker_ip_header *iph,
+							struct nf_conn *ct, ecm_tracker_sender_type_t sender, ecm_db_direction_t ecm_dir,
+							struct nf_conntrack_tuple *orig_tuple, struct nf_conntrack_tuple *reply_tuple,
+							ip_addr_t ip_src_addr, ip_addr_t ip_dest_addr, uint16_t l2_encap_proto)
+{
+	struct tcphdr *tcp_hdr;
+	struct tcphdr tcp_hdr_buff;
+	struct udphdr *udp_hdr;
+	struct udphdr udp_hdr_buff;
+	int src_port;
+	int dest_port;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci = NULL;
+	ip_addr_t match_addr;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	ecm_db_timer_group_t ci_orig_timer_group;
+	struct ecm_classifier_process_response prevalent_pr;
+	int protocol = (int)orig_tuple->dst.protonum;
+	__be16 *layer4hdr = NULL;
+
+	if (protocol == IPPROTO_TCP) {
+
+		if (likely(ct)) {
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+			/*
+			 * Set the DSCP conntrack extension. These values will be
+			 * used in the DSCP classifier for setting them quickly in the
+			 * classifier response.
+			 */
+			ecm_front_end_tcp_set_dscp_ext(ct, iph, skb, sender);
+#endif
+			/*
+			 * Unconfirmed connection may be dropped by Linux at the final step,
+			 * So we don't allow acceleration for the unconfirmed connections.
+			 */
+			if (!nf_ct_is_confirmed(ct)) {
+				DEBUG_WARN("%px: Unconfirmed TCP connection\n", ct);
+				return NF_ACCEPT;
+			}
+
+			/*
+			 * Don't try to manage a non-established connection.
+			 */
+			if (!test_bit(IPS_ASSURED_BIT, &ct->status)) {
+				DEBUG_WARN("%px: Non-established TCP connection\n", ct);
+				return NF_ACCEPT;
+			}
+		}
+
+		/*
+		 * Extract TCP header to obtain port information
+		 */
+		tcp_hdr = ecm_tracker_tcp_check_header_and_read(skb, iph, &tcp_hdr_buff);
+		if (unlikely(!tcp_hdr)) {
+			DEBUG_WARN("TCP packet header %px\n", skb);
+			return NF_ACCEPT;
+		}
+
+		layer4hdr = (__be16*)tcp_hdr;
+		/*
+		 * Now extract information, if we have conntrack then use that (which would already be in the tuples)
+		 */
+		if (unlikely(!ct)) {
+			orig_tuple->src.u.tcp.port = tcp_hdr->source;
+			orig_tuple->dst.u.tcp.port = tcp_hdr->dest;
+			reply_tuple->src.u.tcp.port = tcp_hdr->dest;
+			reply_tuple->dst.u.tcp.port = tcp_hdr->source;
+		}
+
+		/*
+		 * Extract transport port information
+		 * Refer to the ecm_ipv6_process() for information on how we extract this information.
+		 */
+		if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+			switch(ecm_dir) {
+			case ECM_DB_DIRECTION_NON_NAT:
+			case ECM_DB_DIRECTION_BRIDGED:
+				src_port = ntohs(orig_tuple->src.u.tcp.port);
+				dest_port = ntohs(orig_tuple->dst.u.tcp.port);
+				break;
+			default:
+				DEBUG_ASSERT(false, "Unhandled ecm_dir: %d\n", ecm_dir);
+			}
+		} else {
+			switch(ecm_dir) {
+			case ECM_DB_DIRECTION_NON_NAT:
+			case ECM_DB_DIRECTION_BRIDGED:
+				dest_port = ntohs(orig_tuple->src.u.tcp.port);
+				src_port = ntohs(orig_tuple->dst.u.tcp.port);
+				break;
+			default:
+				DEBUG_ASSERT(false, "Unhandled ecm_dir: %d\n", ecm_dir);
+			}
+		}
+
+		DEBUG_TRACE("TCP src: " ECM_IP_ADDR_OCTAL_FMT ":%d, dest: " ECM_IP_ADDR_OCTAL_FMT ":%d, dir %d\n",
+				ECM_IP_ADDR_TO_OCTAL(ip_src_addr), src_port, ECM_IP_ADDR_TO_OCTAL(ip_dest_addr), dest_port, ecm_dir);
+	} else if (protocol == IPPROTO_UDP) {
+		/*
+		 * Unconfirmed connection may be dropped by Linux at the final step,
+		 * So we don't allow acceleration for the unconfirmed connections.
+		 */
+		if (likely(ct) && !nf_ct_is_confirmed(ct)) {
+			DEBUG_WARN("%px: Unconfirmed UDP connection\n", ct);
+			return NF_ACCEPT;
+		}
+
+		/*
+		 * Extract UDP header to obtain port information
+		 */
+		udp_hdr = ecm_tracker_udp_check_header_and_read(skb, iph, &udp_hdr_buff);
+		if (unlikely(!udp_hdr)) {
+			DEBUG_WARN("Invalid UDP header in skb %px\n", skb);
+			return NF_ACCEPT;
+		}
+
+		layer4hdr = (__be16*)udp_hdr;
+
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+		/*
+		 * Deny acceleration for L2TP-over-UDP tunnel
+		 */
+		if ((in_dev->priv_flags_ext & IFF_EXT_PPP_L2TPV2) && ppp_is_xmit_locked(in_dev)) {
+			DEBUG_TRACE("Skip packets for L2TP tunnel in skb %px\n", skb);
+			can_accel = false;
+		}
+#endif
+		/*
+		 * Now extract information, if we have conntrack then use that (which would already be in the tuples)
+		 */
+		if (unlikely(!ct)) {
+			orig_tuple->src.u.udp.port = udp_hdr->source;
+			orig_tuple->dst.u.udp.port = udp_hdr->dest;
+			reply_tuple->src.u.udp.port = udp_hdr->dest;
+			reply_tuple->dst.u.udp.port = udp_hdr->source;
+		}
+
+		/*
+		 * Extract transport port information
+		 * Refer to the ecm_ipv6_process() for information on how we extract this information.
+		 */
+		if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+			switch(ecm_dir) {
+			case ECM_DB_DIRECTION_NON_NAT:
+			case ECM_DB_DIRECTION_BRIDGED:
+				src_port = ntohs(orig_tuple->src.u.udp.port);
+				dest_port = ntohs(orig_tuple->dst.u.udp.port);
+				break;
+			default:
+				DEBUG_ASSERT(false, "Unhandled ecm_dir: %d\n", ecm_dir);
+			}
+		} else {
+			switch(ecm_dir) {
+			case ECM_DB_DIRECTION_NON_NAT:
+			case ECM_DB_DIRECTION_BRIDGED:
+				dest_port = ntohs(orig_tuple->src.u.udp.port);
+				src_port = ntohs(orig_tuple->dst.u.udp.port);
+				break;
+			default:
+				DEBUG_ASSERT(false, "Unhandled ecm_dir: %d\n", ecm_dir);
+			}
+		}
+
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+		if ((netif_is_vxlan(in_dev) || netif_is_vxlan(out_dev)) && is_routed) {
+			DEBUG_TRACE("VxLAN outer connection, make src and dest idents same.\n");
+			src_port = dest_port;
+		}
+#endif
+		if (ct && nfct_help(ct) && (dest_port == TFTP_PORT)) {
+			DEBUG_TRACE("%px: Connection has helper but protocol is TFTP, it can be accelerated\n", ct);
+			can_accel = true;
+		}
+
+		DEBUG_TRACE("UDP src: " ECM_IP_ADDR_OCTAL_FMT ":%d, dest: " ECM_IP_ADDR_OCTAL_FMT ":%d, dir %d\n",
+				ECM_IP_ADDR_TO_OCTAL(ip_src_addr), src_port, ECM_IP_ADDR_TO_OCTAL(ip_dest_addr), dest_port, ecm_dir);
+	} else {
+		DEBUG_WARN("Wrong protocol: %d\n", protocol);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Look up a connection
+	 */
+	ci = ecm_db_connection_find_and_ref(ip_src_addr, ip_dest_addr, protocol, src_port, dest_port);
+
+	/*
+	 * If there is no existing connection then create a new one.
+	 */
+	if (unlikely(!ci)) {
+		struct ecm_db_mapping_instance *mi[ECM_DB_OBJ_DIR_MAX];
+		struct ecm_db_node_instance *ni[ECM_DB_OBJ_DIR_MAX];
+		struct ecm_classifier_default_instance *dci;
+		struct ecm_db_connection_instance *nci;
+		ecm_classifier_type_t classifier_type;
+		int32_t to_list_first;
+		struct ecm_db_iface_instance *to_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+		int32_t from_list_first;
+		struct ecm_db_iface_instance *from_list[ECM_DB_IFACE_HEIRARCHY_MAX];
+		struct ecm_front_end_interface_construct_instance efeici;
+		struct ecm_front_end_ovs_params ovs_params[ECM_DB_OBJ_DIR_MAX];
+		enum ecm_front_end_type fe_type;
+		ecm_ae_classifier_result_t ae_result;
+		ecm_db_connection_defunct_callback_t defunct_callback;
+
+		DEBUG_INFO("New Ported connection from " ECM_IP_ADDR_OCTAL_FMT ":%u to " ECM_IP_ADDR_OCTAL_FMT ":%u\n",
+				ECM_IP_ADDR_TO_OCTAL(ip_src_addr), src_port, ECM_IP_ADDR_TO_OCTAL(ip_dest_addr), dest_port);
+
+		/*
+		 * Before we attempt to create the connection are we being terminated?
+		 */
+		spin_lock_bh(&ecm_ipv6_lock);
+		if (ecm_ipv6_terminate_pending) {
+			spin_unlock_bh(&ecm_ipv6_lock);
+			DEBUG_WARN("Terminating\n");
+
+			/*
+			 * As we are terminating we just allow the packet to pass - it's no longer our concern
+			 */
+			return NF_ACCEPT;
+		}
+		spin_unlock_bh(&ecm_ipv6_lock);
+
+		/*
+		 * Does this connection have a conntrack entry?
+		 */
+		if (ct) {
+			if (protocol == IPPROTO_TCP) {
+				/*
+				 * No point in establishing a connection for one that is closing
+				 */
+				spin_lock_bh(&ct->lock);
+				if (ct->proto.tcp.state >= TCP_CONNTRACK_FIN_WAIT && ct->proto.tcp.state <= TCP_CONNTRACK_CLOSE) {
+					spin_unlock_bh(&ct->lock);
+					DEBUG_TRACE("%px: Connection in termination state %#X\n", ct, ct->proto.tcp.state);
+					return NF_ACCEPT;
+				}
+				spin_unlock_bh(&ct->lock);
+			}
+		}
+
+		/*
+		 * Connection must have a front end instance associated with it
+		 */
+		fe_type = ecm_front_end_type_get();
+		switch (fe_type) {
+#if defined(ECM_FRONT_END_NSS_ENABLE) && defined(ECM_FRONT_END_SFE_ENABLE)
+		case ECM_FRONT_END_TYPE_HYBRID:
+		{
+			ecm_ae_classifier_get_t ae_get;
+			struct ecm_ae_classifier_info ae_info;
+
+			ecm_ae_classifier_select_info_fill(ip_src_addr, ip_dest_addr,
+							  src_port, dest_port, protocol, 6,
+							  is_routed, false,
+							  &ae_info);
+
+			rcu_read_lock();
+			ae_get = rcu_dereference(ae_ops.ae_get);
+			ae_result = ae_get(&ae_info);
+			rcu_read_unlock();
+
+			DEBUG_TRACE("front end type hybrid, ae_result: %d\n", ae_result);
+			break;
+		}
+#endif
+#ifdef ECM_FRONT_END_NSS_ENABLE
+		case ECM_FRONT_END_TYPE_NSS:
+			DEBUG_TRACE("front end type NSS, ae_result: %d\n", ae_result);
+			ae_result = ECM_AE_CLASSIFIER_RESULT_NSS;
+			break;
+#endif
+#ifdef ECM_FRONT_END_SFE_ENABLE
+		case ECM_FRONT_END_TYPE_SFE:
+			ae_result = ECM_AE_CLASSIFIER_RESULT_SFE;
+			DEBUG_TRACE("front end type SFE, ae_result: %d\n", ae_result);
+			break;
+#endif
+		default:
+			DEBUG_WARN("front end type: %d is not supported\n", fe_type);
+			return NF_ACCEPT;
+		}
+
+		/*
+		 * Check the ae_result.
+		 * 1. If NSS, allocate NSS ipv6 ported connection instance
+		 * 2. If SFE, allocate SFE ipv6 ported connection instance
+		 * 3. If NONE, allocate ported connection instance beased on the is_routed flag.
+		 *    If it is set allocate SFE ipv6 ported connection instance with can_accel flag is set to false, otherwise
+		 *    allocate NSS ipv6 ported connection instance with can_accel flag is set to false.
+		 *    By doing this ECM will not ask again and again to the external module. If external module wants to
+		 *    accelerate this flow later, the flow needs to be defuncted first.
+		 * 4. If NOT_YET, the connection will not be allocated in the database and the next flow will be asked again
+		 *    to the external module.
+		 * 5. If any other type is returned, ASSERT.
+		 *
+		 * As an example here, we accelerate the routed flows on SFE, bridge flows on NSS.
+		 */
+		switch (ae_result) {
+#ifdef ECM_FRONT_END_NSS_ENABLE
+		case ECM_AE_CLASSIFIER_RESULT_NSS:
+			if (!ecm_nss_feature_check(skb, iph)) {
+				DEBUG_WARN("Unsupported feature found for NSS acceleration\n");
+				return NF_ACCEPT;
+			}
+			feci = (struct ecm_front_end_connection_instance *)ecm_nss_ported_ipv6_connection_instance_alloc(can_accel, protocol, &nci);
+			defunct_callback = ecm_nss_ported_ipv6_connection_defunct_callback;
+			break;
+#endif
+#ifdef ECM_FRONT_END_SFE_ENABLE
+		case ECM_AE_CLASSIFIER_RESULT_SFE:
+			if (!ecm_sfe_feature_check(skb, iph, is_routed)) {
+				DEBUG_WARN("Unsupported feature found for SFE acceleration\n");
+				return NF_ACCEPT;
+			}
+			feci = (struct ecm_front_end_connection_instance *)ecm_sfe_ported_ipv6_connection_instance_alloc(can_accel, protocol, &nci);
+			defunct_callback = ecm_sfe_ported_ipv6_connection_defunct_callback;
+			break;
+#endif
+#if defined(ECM_FRONT_END_NSS_ENABLE) && defined(ECM_FRONT_END_SFE_ENABLE)
+		case ECM_AE_CLASSIFIER_RESULT_NONE:
+			if (is_routed) {
+				feci = (struct ecm_front_end_connection_instance *)ecm_sfe_ported_ipv6_connection_instance_alloc(false, protocol, &nci);
+				defunct_callback = ecm_sfe_ported_ipv6_connection_defunct_callback;
+			} else {
+				feci = (struct ecm_front_end_connection_instance *)ecm_nss_ported_ipv6_connection_instance_alloc(false, protocol, &nci);
+				defunct_callback = ecm_nss_ported_ipv6_connection_defunct_callback;
+			}
+			break;
+#endif
+		case ECM_AE_CLASSIFIER_RESULT_NOT_YET:
+			return NF_ACCEPT;
+
+		default:
+			DEBUG_ASSERT(NULL, "unexpected ae_result: %d\n", ae_result);
+		}
+
+		if (!feci) {
+			DEBUG_WARN("Failed to allocate front end\n");
+			return NF_ACCEPT;
+		}
+
+		if (!ecm_front_end_ipv6_interface_construct_set_and_hold(skb, sender, ecm_dir, is_routed,
+							in_dev, out_dev,
+							ip_src_addr, ip_dest_addr,
+							&efeici)) {
+			DEBUG_WARN("ECM front end ipv6 interface construct set failed\n");
+			goto fail_1;
+		}
+
+		/*
+		 * For IPv6 there is no NAT address or port numbers,
+		 * so we use the same IP address and port numbers from the
+		 * from and to host for those fields.
+		 */
+		ecm_front_end_fill_ovs_params(ovs_params,
+					      ip_src_addr, ip_src_addr,
+					      ip_dest_addr, ip_dest_addr,
+					      src_port, src_port,
+					      dest_port, dest_port, ecm_dir);
+
+		/*
+		 * Get the src and destination mappings
+		 * For this we also need the interface lists which we also set upon the new connection while we are at it.
+		 * GGG TODO rework terms of "src/dest" - these need to be named consistently as from/to as per database terms.
+		 * GGG TODO The empty list checks should not be needed, mapping_establish_and_ref() should fail out if there is no list anyway.
+		 */
+		DEBUG_TRACE("%px: Create the 'from' interface heirarchy list\n", nci);
+		from_list_first = ecm_interface_heirarchy_construct(feci, from_list, efeici.from_dev, efeici.from_other_dev, ip_dest_addr, efeici.from_mac_lookup_ip_addr, ip_src_addr, 6, protocol, in_dev, is_routed, in_dev, src_node_addr, dest_node_addr, layer4hdr, skb, &ovs_params[ECM_DB_OBJ_DIR_FROM]);
+		if (from_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			DEBUG_WARN("Failed to obtain 'from' heirarchy list\n");
+			goto fail_2;
+		}
+		ecm_db_connection_interfaces_reset(nci, from_list, from_list_first, ECM_DB_OBJ_DIR_FROM);
+
+		DEBUG_TRACE("%px: Create source node\n", nci);
+		ni[ECM_DB_OBJ_DIR_FROM] = ecm_ipv6_node_establish_and_ref(feci, efeici.from_dev, efeici.from_mac_lookup_ip_addr, from_list, from_list_first, src_node_addr, skb);
+		ecm_db_connection_interfaces_deref(from_list, from_list_first);
+		if (!ni[ECM_DB_OBJ_DIR_FROM]) {
+			DEBUG_WARN("Failed to establish source node\n");
+			goto fail_2;
+		}
+		ni[ECM_DB_OBJ_DIR_FROM_NAT] = ni[ECM_DB_OBJ_DIR_FROM];
+
+		DEBUG_TRACE("%px: Create source mapping\n", nci);
+		mi[ECM_DB_OBJ_DIR_FROM] = ecm_ipv6_mapping_establish_and_ref(ip_src_addr, src_port);
+		if (!mi[ECM_DB_OBJ_DIR_FROM]) {
+			DEBUG_WARN("Failed to establish src mapping\n");
+			goto fail_3;
+		}
+		mi[ECM_DB_OBJ_DIR_FROM_NAT] = mi[ECM_DB_OBJ_DIR_FROM];
+
+		DEBUG_TRACE("%px: Create the 'to' interface heirarchy list\n", nci);
+		to_list_first = ecm_interface_heirarchy_construct(feci, to_list, efeici.to_dev, efeici.to_other_dev, ip_src_addr, efeici.to_mac_lookup_ip_addr, ip_dest_addr, 6, protocol, out_dev, is_routed, in_dev, dest_node_addr, src_node_addr, layer4hdr, skb, &ovs_params[ECM_DB_OBJ_DIR_TO]);
+		if (to_list_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			DEBUG_WARN("Failed to obtain 'to' heirarchy list\n");
+			goto fail_4;
+		}
+		ecm_db_connection_interfaces_reset(nci, to_list, to_list_first, ECM_DB_OBJ_DIR_TO);
+
+		DEBUG_TRACE("%px: Create dest node\n", nci);
+		ni[ECM_DB_OBJ_DIR_TO] = ecm_ipv6_node_establish_and_ref(feci, efeici.to_dev, efeici.to_mac_lookup_ip_addr, to_list, to_list_first, dest_node_addr, skb);
+		ecm_db_connection_interfaces_deref(to_list, to_list_first);
+		if (!ni[ECM_DB_OBJ_DIR_TO]) {
+			DEBUG_WARN("Failed to establish dest node\n");
+			goto fail_4;
+		}
+		ni[ECM_DB_OBJ_DIR_TO_NAT] = ni[ECM_DB_OBJ_DIR_TO];
+
+		DEBUG_TRACE("%px: Create dest mapping\n", nci);
+		mi[ECM_DB_OBJ_DIR_TO] = ecm_ipv6_mapping_establish_and_ref(ip_dest_addr, dest_port);
+		if (!mi[ECM_DB_OBJ_DIR_TO]) {
+			DEBUG_WARN("Failed to establish dest mapping\n");
+			goto fail_5;
+		}
+		mi[ECM_DB_OBJ_DIR_TO_NAT] = mi[ECM_DB_OBJ_DIR_TO];
+
+		/*
+		 * Every connection also needs a default classifier which is considered 'special'
+		 */
+		dci = ecm_classifier_default_instance_alloc(nci, protocol, ecm_dir, src_port, dest_port);
+		if (!dci) {
+			DEBUG_WARN("Failed to allocate default classifier\n");
+			goto fail_6;
+		}
+		ecm_db_connection_classifier_assign(nci, (struct ecm_classifier_instance *)dci);
+
+		/*
+		 * Every connection starts with a full complement of classifiers assigned.
+		 * NOTE: Default classifier is a special case considered previously
+		 */
+		for (classifier_type = ECM_CLASSIFIER_TYPE_DEFAULT + 1; classifier_type < ECM_CLASSIFIER_TYPES; ++classifier_type) {
+			struct ecm_classifier_instance *aci = ecm_classifier_assign_classifier(nci, classifier_type);
+			if (aci) {
+				aci->deref(aci);
+			} else {
+				DEBUG_WARN("Failed to allocate classifiers assignments\n");
+				goto fail_7;
+			}
+		}
+
+		ecm_db_front_end_instance_ref_and_set(nci, feci);
+
+		ecm_db_connection_l2_encap_proto_set(nci, l2_encap_proto);
+
+		/*
+		 * Now add the connection into the database.
+		 * NOTE: In an SMP situation such as ours there is a possibility that more than one packet for the same
+		 * connection is being processed simultaneously.
+		 * We *could* end up creating more than one connection instance for the same actual connection.
+		 * To guard against this we now perform a mutex'd lookup of the connection + add once more - another cpu may have created it before us.
+		 */
+		spin_lock_bh(&ecm_ipv6_lock);
+		ci = ecm_db_connection_find_and_ref(ip_src_addr, ip_dest_addr, protocol, src_port, dest_port);
+		if (ci) {
+			/*
+			 * Another cpu created the same connection before us - use the one we just found
+			 */
+			spin_unlock_bh(&ecm_ipv6_lock);
+			ecm_db_connection_deref(nci);
+		} else {
+			ecm_db_timer_group_t tg;
+			ecm_tracker_sender_state_t src_state;
+			ecm_tracker_sender_state_t dest_state;
+			ecm_tracker_connection_state_t state;
+			struct ecm_tracker_instance *ti;
+
+			/*
+			 * Ask tracker for timer group to set the connection to initially.
+			 */
+			ti = dci->tracker_get_and_ref(dci);
+			ti->state_get(ti, &src_state, &dest_state, &state, &tg);
+			ti->deref(ti);
+
+			/*
+			 * Add the new connection we created into the database
+			 * NOTE: assign to a short timer group for now - it is the assigned classifiers responsibility to do this
+			 */
+			ecm_db_connection_add(nci, mi, ni,
+					6, protocol, ecm_dir,
+					NULL /* final callback */,
+					defunct_callback,
+					tg, is_routed, nci);
+
+			spin_unlock_bh(&ecm_ipv6_lock);
+
+			ci = nci;
+			DEBUG_INFO("%px: New ported connection created\n", ci);
+		}
+
+		/*
+		 * No longer need referenecs to the objects we created
+		 */
+		dci->base.deref((struct ecm_classifier_instance *)dci);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+		ecm_front_end_ipv6_interface_construct_netdev_put(&efeici);
+		feci->deref(feci);
+
+		goto done;
+fail_7:
+		dci->base.deref((struct ecm_classifier_instance *)dci);
+fail_6:
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_TO]);
+fail_5:
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_TO]);
+fail_4:
+		ecm_db_mapping_deref(mi[ECM_DB_OBJ_DIR_FROM]);
+fail_3:
+		ecm_db_node_deref(ni[ECM_DB_OBJ_DIR_FROM]);
+fail_2:
+		ecm_front_end_ipv6_interface_construct_netdev_put(&efeici);
+fail_1:
+		feci->deref(feci);
+		ecm_db_connection_deref(nci);
+		return NF_ACCEPT;
+done:
+		;
+	}
+
+	/*
+	 * Bridged traffic goes through the IP post routing hook as well after it
+	 * finishes the bridge post routing hook. In that case, ecm_dir will become
+	 * as Non-Nat since the is_routed flag is true. But the is_routed flag of the connection
+	 * was set as false while the packet was going throught the bridge post routing
+	 * hook. So, we need to check if the is_routed flag and ecm_dir matches the routed
+	 * flow condition. If it doesn't, do not process the flow.
+	 */
+	if (!ecm_db_connection_is_routed_get(ci) && (ecm_dir == ECM_DB_DIRECTION_NON_NAT)) {
+		DEBUG_TRACE("%px: ignore route hook path for bridged packet\n", ci);
+		ecm_db_connection_deref(ci);
+		return NF_ACCEPT;
+	}
+
+#if defined(CONFIG_NET_CLS_ACT) && defined(ECM_CLASSIFIER_DSCP_IGS) && defined(ECM_FRONT_END_NSS_ENABLE)
+	/*
+	 * Check if IGS feature is enabled or not.
+	 */
+	if (unlikely(ecm_interface_igs_enabled)) {
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+		if (feci->accel_engine == ECM_FRONT_END_ENGINE_NSS) {
+			if (!ecm_nss_common_igs_acceleration_is_allowed(feci, skb)) {
+				DEBUG_WARN("%px: IPv6 IGS acceleration denied\n", ci);
+				feci->deref(feci);
+				ecm_db_connection_deref(ci);
+				return NF_ACCEPT;
+			}
+		}
+		feci->deref(feci);
+	}
+#endif
+
+	/*
+	 * Return if timer no touch is set
+	 */
+	if (ecm_db_connection_defunct_timer_no_touch_get(ci)) {
+		DEBUG_TRACE("%px: No touch timer is set for this ci\n", ci);
+		if (protocol == IPPROTO_TCP) {
+			if (tcp_hdr->syn) {
+				DEBUG_TRACE("%px: TCP SYN Flag is seen in No Touch timer state, defunct connection\n", ci);
+				ecm_db_connection_make_defunct(ci);
+			}
+		}
+		ecm_db_connection_deref(ci);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Keep connection alive as we have seen activity
+	 */
+	if (!ecm_db_connection_defunct_timer_touch(ci)) {
+		ecm_db_connection_deref(ci);
+		return NF_ACCEPT;
+	}
+
+	/*
+	 * Identify which side of the connection is sending
+	 * NOTE: This may be different than what sender is at the moment
+	 * given the connection we have located.
+	 */
+	ecm_db_connection_address_get(ci, ECM_DB_OBJ_DIR_FROM, match_addr);
+	if (ECM_IP_ADDR_MATCH(ip_src_addr, match_addr)) {
+		sender = ECM_TRACKER_SENDER_TYPE_SRC;
+	} else {
+		sender = ECM_TRACKER_SENDER_TYPE_DEST;
+	}
+
+	/*
+	 * Do we need to action generation change?
+	 */
+	if (unlikely(ecm_db_connection_regeneration_required_check(ci))) {
+		ecm_ipv6_connection_regenerate(ci, sender, out_dev, in_dev, layer4hdr, skb);
+	}
+
+	/*
+	 * Increment the slow path packet counter.
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	spin_lock_bh(&feci->lock);
+	feci->stats.slow_path_packets++;
+	spin_unlock_bh(&feci->lock);
+	feci->deref(feci);
+
+	/*
+	 * Iterate the assignments and call to process!
+	 * Policy implemented:
+	 * 1. Classifiers that say they are not relevant are unassigned and not actioned further.
+	 * 2. Any drop command from any classifier is honoured.
+	 * 3. All classifiers must action acceleration for accel to be honoured, any classifiers not sure of their relevance will stop acceleration.
+	 * 4. Only the highest priority classifier, that actions it, will have its qos tag honoured.
+	 * 5. Only the highest priority classifier, that actions it, will have its timer group honoured.
+	 */
+	DEBUG_TRACE("%px: process begin, skb: %px\n", ci, skb);
+	prevalent_pr.process_actions = 0;
+	prevalent_pr.drop = false;
+	prevalent_pr.flow_qos_tag = skb->priority;
+	prevalent_pr.return_qos_tag = skb->priority;
+	prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL;
+	prevalent_pr.timer_group = ci_orig_timer_group = ecm_db_connection_timer_group_get(ci);
+
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_process_response aci_pr;
+		struct ecm_classifier_instance *aci;
+
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: process: %px, type: %d\n", ci, aci, aci->type_get(aci));
+		aci->process(aci, sender, iph, skb, &aci_pr);
+		DEBUG_TRACE("%px: aci_pr: process actions: %x, became relevant: %u, relevance: %d, drop: %d, "
+				"flow_qos_tag: %u, return_qos_tag: %u, accel_mode: %x, timer_group: %d\n",
+				ci, aci_pr.process_actions, aci_pr.became_relevant, aci_pr.relevance, aci_pr.drop,
+				aci_pr.flow_qos_tag, aci_pr.return_qos_tag, aci_pr.accel_mode, aci_pr.timer_group);
+
+		if (aci_pr.relevance == ECM_CLASSIFIER_RELEVANCE_NO) {
+			ecm_classifier_type_t aci_type;
+
+			/*
+			 * This classifier can be unassigned - PROVIDED it is not the default classifier
+			 */
+			aci_type = aci->type_get(aci);
+			if (aci_type == ECM_CLASSIFIER_TYPE_DEFAULT) {
+				continue;
+			}
+
+			DEBUG_INFO("%px: Classifier not relevant, unassign: %d", ci, aci_type);
+			ecm_db_connection_classifier_unassign(ci, aci);
+			continue;
+		}
+
+		/*
+		 * Yes or Maybe relevant.
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DROP) {
+			/*
+			 * Drop command from any classifier is actioned.
+			 */
+			DEBUG_TRACE("%px: wants drop: %px, type: %d, skb: %px\n", ci, aci, aci->type_get(aci), skb);
+			prevalent_pr.drop |= aci_pr.drop;
+		}
+
+		/*
+		 * Accel mode permission
+		 */
+		if (aci_pr.relevance == ECM_CLASSIFIER_RELEVANCE_MAYBE) {
+			/*
+			 * Classifier not sure of its relevance - cannot accel yet
+			 */
+			DEBUG_TRACE("%px: accel denied by maybe: %px, type: %d\n", ci, aci, aci->type_get(aci));
+			prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+		} else {
+			if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_ACCEL_MODE) {
+				if (aci_pr.accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_NO) {
+					DEBUG_TRACE("%px: accel denied: %px, type: %d\n", ci, aci, aci->type_get(aci));
+					prevalent_pr.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO;
+				}
+				/* else yes or don't care about accel */
+			}
+		}
+
+		/*
+		 * Timer group (the last classifier i.e. the highest priority one) will 'win'
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP) {
+			DEBUG_TRACE("%px: timer group: %px, type: %d, group: %d\n", ci, aci, aci->type_get(aci), aci_pr.timer_group);
+			prevalent_pr.timer_group = aci_pr.timer_group;
+		}
+
+		/*
+		 * Timer group no touch action is set when classifier identified
+		 * that the connection should be defunct when timer group
+		 * expires, do not update timer group when the packets matching
+		 * this connection are received later.
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP_NO_TOUCH) {
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP_NO_TOUCH;
+		}
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, ingress vlan tags 0: %u, egress vlan tags 0: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.ingress_vlan_tag[0], aci_pr.egress_vlan_tag[0]);
+			prevalent_pr.ingress_vlan_tag[0] = aci_pr.ingress_vlan_tag[0];
+			prevalent_pr.egress_vlan_tag[0] = aci_pr.egress_vlan_tag[0];
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG;
+		}
+
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, ingress vlan tags 1: %u, egress vlan tags 1: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.ingress_vlan_tag[1], aci_pr.egress_vlan_tag[1]);
+			prevalent_pr.ingress_vlan_tag[1] = aci_pr.ingress_vlan_tag[1];
+			prevalent_pr.egress_vlan_tag[1] = aci_pr.egress_vlan_tag[1];
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG;
+		}
+#endif
+
+		/*
+		 * Qos tag (the last classifier i.e. the highest priority one) will 'win'
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, flow qos tag: %u, return qos tag: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.flow_qos_tag, aci_pr.return_qos_tag);
+			prevalent_pr.flow_qos_tag = aci_pr.flow_qos_tag;
+			prevalent_pr.return_qos_tag = aci_pr.return_qos_tag;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG;
+		}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+#ifdef ECM_CLASSIFIER_DSCP_IGS
+		/*
+		 * Ingress QoS tag
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, ingress flow qos tag: %u, ingress return qos tag: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.igs_flow_qos_tag, aci_pr.igs_return_qos_tag);
+			prevalent_pr.igs_flow_qos_tag = aci_pr.igs_flow_qos_tag;
+			prevalent_pr.igs_return_qos_tag = aci_pr.igs_return_qos_tag;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG;
+		}
+#endif
+		/*
+		 * If any classifier denied DSCP remarking then that overrides every classifier
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, DSCP remark denied\n",
+					ci, aci, aci->type_get(aci));
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY;
+			prevalent_pr.process_actions &= ~ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+		}
+
+		/*
+		 * DSCP remark action, but only if it has not been denied by any classifier
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+			if (!(prevalent_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP_DENY)) {
+				DEBUG_TRACE("%px: aci: %px, type: %d, DSCP remark wanted, flow_dscp: %u, return dscp: %u\n",
+						ci, aci, aci->type_get(aci), aci_pr.flow_dscp, aci_pr.return_dscp);
+				prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_DSCP;
+				prevalent_pr.flow_dscp = aci_pr.flow_dscp;
+				prevalent_pr.return_dscp = aci_pr.return_dscp;
+			}
+		}
+
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_MARK) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, flow mark: %u, return mark: %u\n",
+					ci, aci, aci->type_get(aci), aci_pr.flow_mark, aci_pr.return_mark);
+			prevalent_pr.flow_mark = aci_pr.flow_mark;
+			prevalent_pr.return_mark = aci_pr.return_mark;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_MARK;
+		}
+#endif
+
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+		/*
+		 * E-Mesh Service Prioritization is Valid
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, E-Mesh Service Prioritization is valid\n",
+					ci, aci, aci->type_get(aci));
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW;
+		}
+#endif
+
+#ifdef ECM_CLASSIFIER_PCC_ENABLE
+		/*
+		 * Mirror flag
+		 */
+		if (aci_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_MIRROR_ENABLED) {
+			DEBUG_TRACE("%px: aci: %px, type: %d, flow_mirror_ifindex: %d"
+					" return_mirror_ifindex: %d\n",
+					ci, aci, aci->type_get(aci),
+					aci_pr.flow_mirror_ifindex,
+					aci_pr.return_mirror_ifindex);
+			prevalent_pr.flow_mirror_ifindex = aci_pr.flow_mirror_ifindex;
+			prevalent_pr.return_mirror_ifindex = aci_pr.return_mirror_ifindex;
+			prevalent_pr.process_actions |= ECM_CLASSIFIER_PROCESS_ACTION_MIRROR_ENABLED;
+		}
+#endif
+
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Set timer no touch
+	 */
+	if (prevalent_pr.process_actions & ECM_CLASSIFIER_PROCESS_ACTION_TIMER_GROUP_NO_TOUCH) {
+		ecm_db_connection_defunct_timer_no_touch_set(ci);
+	}
+
+	/*
+	 * Change timer group?
+	 */
+	if (ci_orig_timer_group != prevalent_pr.timer_group) {
+		DEBUG_TRACE("%px: change timer group from: %d to: %d\n", ci, ci_orig_timer_group, prevalent_pr.timer_group);
+		ecm_db_connection_defunct_timer_reset(ci, prevalent_pr.timer_group);
+	}
+
+	/*
+	 * Drop?
+	 */
+	if (prevalent_pr.drop) {
+		DEBUG_TRACE("%px: drop: %px\n", ci, skb);
+		ecm_db_connection_data_totals_update_dropped(ci, (sender == ECM_TRACKER_SENDER_TYPE_SRC)? true : false, skb->len, 1);
+		ecm_db_connection_deref(ci);
+		return NF_ACCEPT;
+	}
+	ecm_db_connection_data_totals_update(ci, (sender == ECM_TRACKER_SENDER_TYPE_SRC)? true : false, skb->len, 1);
+
+	/*
+	 * Assign qos tag
+	 * GGG TODO Should we use sender to identify whether to use flow or return qos tag?
+	 */
+	skb->priority = prevalent_pr.flow_qos_tag;
+	DEBUG_TRACE("%px: skb priority: %u\n", ci, skb->priority);
+
+	/*
+	 * Accelerate?
+	 */
+	if (prevalent_pr.accel_mode == ECM_CLASSIFIER_ACCELERATION_MODE_ACCEL) {
+		DEBUG_TRACE("%px: accel\n", ci);
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+		feci->accelerate(feci, &prevalent_pr, is_l2_encap, ct, skb);
+		feci->deref(feci);
+	}
+	ecm_db_connection_deref(ci);
+
+	return NF_ACCEPT;
+}
diff --git a/qca-nss-ecm/frontends/cmn/ecm_ported_ipv6.h b/qca-nss-ecm/frontends/cmn/ecm_ported_ipv6.h
new file mode 100644
index 0000000..4e0e631
--- /dev/null
+++ b/qca-nss-ecm/frontends/cmn/ecm_ported_ipv6.h
@@ -0,0 +1,25 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern unsigned int ecm_ported_ipv6_process(struct net_device *out_dev,
+							struct net_device *in_dev,
+							uint8_t *src_node_addr,
+							uint8_t *dest_node_addr,
+							bool can_accel, bool is_routed, bool is_l2_encap, struct sk_buff *skb,
+							struct ecm_tracker_ip_header *iph,
+							struct nf_conn *ct, ecm_tracker_sender_type_t sender, ecm_db_direction_t ecm_dir,
+							struct nf_conntrack_tuple *orig_tuple, struct nf_conntrack_tuple *reply_tuple,
+							ip_addr_t ip_src_addr, ip_addr_t ip_dest_addr, uint16_t l2_encap_proto);
diff --git a/qca-nss-ecm/frontends/ecm_front_end_common.c b/qca-nss-ecm/frontends/ecm_front_end_common.c
new file mode 100644
index 0000000..f6b5300
--- /dev/null
+++ b/qca-nss-ecm/frontends/ecm_front_end_common.c
@@ -0,0 +1,620 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2016, 2020-2022, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/debugfs.h>
+#include <linux/inet.h>
+#include <linux/etherdevice.h>
+#include <linux/inetdevice.h>
+#include <linux/sysctl.h>
+#include <net/netfilter/nf_conntrack.h>
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+#include <linux/netfilter/xt_dscp.h>
+#include <net/netfilter/nf_conntrack_dscpremark_ext.h>
+#endif
+#include <net/ip.h>
+#include <net/ipv6.h>
+#include <net/addrconf.h>
+#include <net/gre.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_FRONT_END_COMMON_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_front_end_common.h"
+#include "ecm_interface.h"
+
+/*
+ * Sysctl table header
+ */
+static struct ctl_table_header *ecm_front_end_ctl_tbl_hdr;
+
+/*
+ * Flag to limit the number of DB connections at any point to the maximum number
+ * that can be accelerated by NSS. This may need to be enabled for low memory
+ * platforms to control memory allocated by ECM databases.
+ */
+unsigned int ecm_front_end_conn_limit = 0;
+
+/*
+ * Predefined frontend and feature support map.
+ */
+uint32_t ecm_fe_feature_list[ECM_FRONT_END_TYPE_MAX] = {
+	0, 			/* Auto: This type will never be selected */
+
+	ECM_FE_FEATURE_NSS | ECM_FE_FEATURE_NON_PORTED | ECM_FE_FEATURE_BRIDGE |
+	ECM_FE_FEATURE_MULTICAST | ECM_FE_FEATURE_BONDING | ECM_FE_FEATURE_IGS |
+	ECM_FE_FEATURE_SRC_IF_CHECK | ECM_FE_FEATURE_CONN_LIMIT |
+	ECM_FE_FEATURE_DSCP_ACTION | ECM_FE_FEATURE_XFRM | ECM_FE_FEATURE_OVS_BRIDGE |
+	ECM_FE_FEATURE_OVS_VLAN,
+				/* NSS type */
+
+	ECM_FE_FEATURE_SFE | ECM_FE_FEATURE_NON_PORTED | ECM_FE_FEATURE_CONN_LIMIT |	/* SFE type */
+	ECM_FE_FEATURE_OVS_BRIDGE | ECM_FE_FEATURE_OVS_VLAN | ECM_FE_FEATURE_BRIDGE |
+	ECM_FE_FEATURE_BONDING | ECM_FE_FEATURE_SRC_IF_CHECK,
+
+	ECM_FE_FEATURE_NSS | ECM_FE_FEATURE_SFE | ECM_FE_FEATURE_NON_PORTED | ECM_FE_FEATURE_BRIDGE |
+	ECM_FE_FEATURE_MULTICAST | ECM_FE_FEATURE_BONDING | ECM_FE_FEATURE_IGS |
+	ECM_FE_FEATURE_SRC_IF_CHECK | ECM_FE_FEATURE_CONN_LIMIT |
+	ECM_FE_FEATURE_DSCP_ACTION | ECM_FE_FEATURE_XFRM | ECM_FE_FEATURE_OVS_BRIDGE |
+	ECM_FE_FEATURE_OVS_VLAN,
+				/* Hybrid type */
+};
+
+/*
+ * ecm_front_end_is_feature_supported()
+ *	Checks if the given feature is supported in the selected frontend.
+ */
+bool ecm_front_end_is_feature_supported(enum ecm_fe_feature feature)
+{
+	enum ecm_front_end_type type = ecm_front_end_type_get();
+
+	return !!(ecm_fe_feature_list[type] & feature);
+}
+
+#ifdef ECM_INTERFACE_BOND_ENABLE
+/*
+ * ecm_front_end_bond_notifier_stop()
+ */
+void ecm_front_end_bond_notifier_stop(int num)
+{
+	if (ecm_front_end_is_feature_supported(ECM_FE_FEATURE_BONDING)) {
+		ecm_bond_notifier_stop(num);
+	}
+}
+
+/*
+ * ecm_front_end_bond_notifier_init()
+ */
+int ecm_front_end_bond_notifier_init(struct dentry *dentry)
+{
+	if (ecm_front_end_is_feature_supported(ECM_FE_FEATURE_BONDING)) {
+		return ecm_bond_notifier_init(dentry);
+	}
+
+	return 0;
+}
+
+/*
+ * ecm_front_end_bond_notifier_exit()
+ */
+void ecm_front_end_bond_notifier_exit(void)
+{
+	if (ecm_front_end_is_feature_supported(ECM_FE_FEATURE_BONDING)) {
+		ecm_bond_notifier_exit();
+	}
+}
+#endif
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_front_end_common_connection_state_get()
+ *	Return state of the front end instance.
+ */
+int ecm_front_end_common_connection_state_get(struct ecm_front_end_connection_instance *feci,
+					     struct ecm_state_file_instance *sfi,
+					     char *conn_type)
+{
+	int result;
+	bool can_accel;
+	ecm_front_end_acceleration_mode_t accel_mode;
+	struct ecm_front_end_connection_mode_stats stats;
+
+	spin_lock_bh(&feci->lock);
+	can_accel = feci->can_accel;
+	accel_mode = feci->accel_mode;
+	memcpy(&stats, &feci->stats, sizeof(struct ecm_front_end_connection_mode_stats));
+	spin_unlock_bh(&feci->lock);
+
+	if ((result = ecm_state_prefix_add(sfi, conn_type))) {
+		return result;
+	}
+
+	if ((result = ecm_state_write(sfi, "can_accel", "%d", can_accel))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "accel_mode", "%d", accel_mode))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "decelerate_pending", "%d", stats.decelerate_pending))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "flush_happened_total", "%d", stats.flush_happened_total))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "no_action_seen_total", "%d", stats.no_action_seen_total))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "no_action_seen", "%d", stats.no_action_seen))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "no_action_seen_limit", "%d", stats.no_action_seen_limit))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "driver_fail_total", "%d", stats.driver_fail_total))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "driver_fail", "%d", stats.driver_fail))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "driver_fail_limit", "%d", stats.driver_fail_limit))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "ae_nack_total", "%d", stats.ae_nack_total))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "ae_nack", "%d", stats.ae_nack))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "ae_nack_limit", "%d", stats.ae_nack_limit))) {
+		return result;
+	}
+	if ((result = ecm_state_write(sfi, "slow_path_packets", "%llu", stats.slow_path_packets))) {
+		return result;
+	}
+
+	return ecm_state_prefix_remove(sfi);
+}
+#endif
+
+/*
+ * ecm_front_end_gre_proto_is_accel_allowed()
+ * 	Handle the following GRE cases:
+ *
+ * 1. PPTP locally terminated - allow acceleration
+ * 2. PPTP pass through - do not allow acceleration
+ * 3. GRE V4 or V6 TAP - allow acceleration
+ * 4. GRE V4 or V6 TUN - allow acceleration
+ * 5. NVGRE locally terminated - do not allow acceleration
+ * 6. NVGRE pass through - do not allow acceleration
+ * 7. GRE pass through - allow acceleration
+ */
+bool ecm_front_end_gre_proto_is_accel_allowed(struct net_device *indev,
+							     struct net_device *outdev,
+							     struct sk_buff *skb,
+							     struct nf_conntrack_tuple *tuple,
+							     int ip_version)
+{
+	struct net_device *dev;
+	struct gre_base_hdr *greh;
+
+	skb_pull(skb, sizeof(struct iphdr));
+	greh = (struct gre_base_hdr *)(skb->data);
+	skb_push(skb, sizeof(struct iphdr));
+
+	if ((greh->flags & GRE_VERSION) == ECM_GRE_VERSION_1) {
+		/*
+		 * Case 1: PPTP locally terminated
+		 */
+		if (ecm_interface_is_pptp(skb, outdev)) {
+			DEBUG_TRACE("%px: PPTP GRE locally terminated - allow acceleration\n", skb);
+			return true;
+		}
+
+		/*
+		 * Case 2: PPTP pass through
+		 */
+		DEBUG_TRACE("%px: PPTP GRE pass through - do not allow acceleration\n", skb);
+		return false;
+	}
+
+	if ((greh->flags & GRE_VERSION) != ECM_GRE_VERSION_0) {
+		DEBUG_WARN("%px: Unknown GRE version - do not allow acceleration\n", skb);
+		return false;
+	}
+
+	/*
+	 * Case 3: GRE V4 or V6 TAP
+	 */
+	if ((indev->priv_flags_ext & (IFF_EXT_GRE_V4_TAP | IFF_EXT_GRE_V6_TAP))
+		|| (outdev->priv_flags_ext & (IFF_EXT_GRE_V4_TAP | IFF_EXT_GRE_V6_TAP))) {
+#ifdef ECM_INTERFACE_GRE_TAP_ENABLE
+		DEBUG_TRACE("%px: GRE IPv%d TAP flow - allow acceleration\n", skb, ip_version);
+		return true;
+#else
+		DEBUG_TRACE("%px: GRE IPv%d TAP feature is disabled - do not allow acceleration\n", skb, ip_version);
+		return false;
+#endif
+	}
+
+	/*
+	 * Case 4: GRE V4 or V6 TUN
+	 */
+	if ((indev->type == ARPHRD_IPGRE) || (outdev->type == ARPHRD_IPGRE)
+		|| (indev->type == ARPHRD_IP6GRE) || (outdev->type == ARPHRD_IP6GRE)) {
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+		DEBUG_TRACE("%px: GRE IPv%d TUN flow - allow acceleration\n", skb, ip_version);
+		return true;
+#else
+		DEBUG_TRACE("%px: GRE IPv%d TUN feature is disabled - do not allow acceleration\n", skb, ip_version);
+		return false;
+#endif
+	}
+
+	/*
+	 * Case 5: NVGRE locally terminated
+	 *
+	 * Check both source and dest interface.
+	 * If either is locally terminated, we cannot accelerate.
+	 */
+	if (ip_version == 4) {
+		dev = ip_dev_find(&init_net, tuple->src.u3.ip);
+		if (dev) {
+			/*
+			 * Source IP address is local
+			 */
+			dev_put(dev);
+			DEBUG_TRACE("%px: NVGRE locally terminated (src) - do not allow acceleration\n", skb);
+			return false;
+		}
+
+		dev = ip_dev_find(&init_net, tuple->dst.u3.ip);
+		if (dev) {
+			/*
+			 * Destination IP address is local
+			 */
+			dev_put(dev);
+			DEBUG_TRACE("%px: NVGRE locally terminated (dest) - do not allow acceleration\n", skb);
+			return false;
+		}
+	} else {
+#ifdef ECM_IPV6_ENABLE
+		dev = ipv6_dev_find(&init_net, &(tuple->src.u3.in6), 1);
+		if (dev) {
+			/*
+			 * Source IP address is local
+			 */
+			dev_put(dev);
+			DEBUG_TRACE("%px: NVGRE locally terminated (src) - do not allow acceleration\n", skb);
+			return false;
+		}
+
+		dev = ipv6_dev_find(&init_net, &(tuple->dst.u3.in6), 1);
+		if (dev) {
+			/*
+			 * Destination IP address is local
+			 */
+			dev_put(dev);
+			DEBUG_TRACE("%px: NVGRE locally terminated (dest) - do not allow acceleration\n", skb);
+			return false;
+		}
+#else
+			DEBUG_TRACE("%px: IPv6 support not enabled\n", skb);
+			return false;
+#endif
+	}
+
+	/*
+	 * Case 6: NVGRE pass through
+	 */
+	if (greh->flags & GRE_KEY) {
+		DEBUG_TRACE("%px: NVGRE pass through - do not allow acceleration\n", skb);
+		return false;
+	}
+
+	/*
+	 * Case 7: GRE pass through
+	 */
+	DEBUG_TRACE("%px: GRE IPv%d pass through - allow acceleration\n", skb, ip_version);
+	return true;
+}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+/*
+ * ecm_front_end_tcp_set_dscp_ext()
+ *	Sets the DSCP remark extension.
+ */
+void ecm_front_end_tcp_set_dscp_ext(struct nf_conn *ct,
+					      struct ecm_tracker_ip_header *iph,
+					      struct sk_buff *skb,
+					      ecm_tracker_sender_type_t sender)
+{
+	struct nf_ct_dscpremark_ext *dscpcte;
+
+	/*
+	 * Extract the priority and DSCP from skb during the TCP handshake
+	 * and store into ct extension for each direction.
+	 */
+	spin_lock_bh(&ct->lock);
+	dscpcte = nf_ct_dscpremark_ext_find(ct);
+	if (dscpcte && ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED) {
+		if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+			dscpcte->flow_priority = skb->priority;
+			dscpcte->flow_mark = skb->mark;
+			dscpcte->flow_dscp = iph->ds >> XT_DSCP_SHIFT;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,4,0)
+			dscpcte->flow_set_flags = NF_CT_DSCPREMARK_EXT_PRIO | NF_CT_DSCPREMARK_EXT_DSCP | NF_CT_DSCPREMARK_EXT_MARK;
+			DEBUG_TRACE("%px: sender: %d flow priority: %d flow dscp: %d flow_mark: %d flow_set_flags: 0x%x\n",
+				    ct, sender, dscpcte->flow_priority, dscpcte->flow_dscp, dscpcte->flow_mark, dscpcte->flow_set_flags);
+#endif
+		} else {
+			dscpcte->reply_priority =  skb->priority;
+			dscpcte->reply_mark =  skb->mark;
+			dscpcte->reply_dscp = iph->ds >> XT_DSCP_SHIFT;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,4,0)
+			dscpcte->return_set_flags = NF_CT_DSCPREMARK_EXT_PRIO | NF_CT_DSCPREMARK_EXT_DSCP | NF_CT_DSCPREMARK_EXT_MARK;
+			DEBUG_TRACE("%px: sender: %d reply priority: %d reply dscp: %d reply_mark: %d return_set_flags: 0x%x\n",
+				    ct, sender, dscpcte->reply_priority, dscpcte->reply_dscp, dscpcte->reply_mark, dscpcte->return_set_flags);
+#endif
+		}
+	}
+	spin_unlock_bh(&ct->lock);
+}
+#endif
+
+/*
+ * ecm_front_end_fill_ovs_params()
+ *	Set the OVS flow lookup parameters.
+ *
+ */
+void ecm_front_end_fill_ovs_params(struct ecm_front_end_ovs_params ovs_params[],
+					ip_addr_t ip_src_addr, ip_addr_t ip_src_addr_nat,
+					ip_addr_t ip_dest_addr, ip_addr_t ip_dest_addr_nat,
+					int src_port, int src_port_nat,
+					int dest_port, int dest_port_nat, ecm_db_direction_t ecm_dir)
+{
+	DEBUG_INFO("ip_src_addr " ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(ip_src_addr));
+	DEBUG_INFO("ip_src_addr_nat " ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(ip_src_addr_nat));
+	DEBUG_INFO("ip_dest_addr " ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(ip_dest_addr));
+	DEBUG_INFO("ip_dest_addr_nat " ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(ip_dest_addr_nat));
+	DEBUG_INFO("src_port: %d, src_port_nat: %d, dest_port:%d, dest_port_nat:%d\n", src_port, src_port_nat, dest_port, dest_port_nat);
+
+	/*
+	 * A routed flow can go through ECM in 4 different NAT cases.
+	 *
+	 * 1. SNAT:
+	 * PC1 -------------> eth1-ovs-br1--->ovs-br2-eth2 -------------> PC2
+	 *			FROM		TO
+	 *					TO_NAT
+	 *					FROM_NAT
+	 *
+	 * ip_src_addr				ip_src_addr_nat		ip_dest_addr/ip_dest_addr_nat
+	 *
+	 *
+	 * 2. DNAT:
+	 * PC1 <------------- eth1-ovs-br1<---ovs-br2-eth2 <------------- PC2
+	 *			TO		FROM
+	 *					FROM_NAT
+	 *					TO_NAT
+	 *
+	 * ip_dest_addr				ip_dest_addr_nat	ip_src_addr/ip_src_addr_nat
+	 *
+	 *
+	 * 3. Non-NAT - Egress:
+	 * PC1 -------------> eth1-ovs-br1--->ovs-br2-eth2 -------------> PC2
+	 *			FROM		TO
+	 *			FROM_NAT	TO_NAT
+	 *
+	 * ip_src_addr/ip_src_addr_nat					ip_dest_addr/ip_dest_addr_nat
+	 *
+	 *
+	 * 4. Non-NAT - Ingress:
+	 * PC1 <------------- eth1-ovs-br1<---ovs-br2-eth2 <------------- PC2
+	 *			TO		FROM
+	 *			TO_NAT		FROM_NAT
+	 *
+	 * ip_dest_addr/ip_dest_addr_nat				ip_src_addr/ip_src_addr_nat
+	 */
+
+	/*
+	 * To look-up the FROM and TO ports, in all NAT cases we use the same IP/port combinations.
+	 */
+	ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_FROM].src_ip, ip_dest_addr_nat);
+	ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_FROM].dest_ip, ip_src_addr);
+	ovs_params[ECM_DB_OBJ_DIR_FROM].src_port = dest_port_nat;
+	ovs_params[ECM_DB_OBJ_DIR_FROM].dest_port = src_port;
+
+	ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_TO].src_ip, ip_src_addr_nat);
+	ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_TO].dest_ip, ip_dest_addr);
+	ovs_params[ECM_DB_OBJ_DIR_TO].src_port = src_port_nat;
+	ovs_params[ECM_DB_OBJ_DIR_TO].dest_port = dest_port;
+
+	if (ecm_dir == ECM_DB_DIRECTION_EGRESS_NAT) {
+		/*
+		 * For SNAT case (EGRESS_NAT), we use specific IP/port combinations to look-up
+		 * the FROM_NAT and TO_NAT ports.
+		 */
+		ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_FROM_NAT].src_ip, ip_src_addr_nat);
+		ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_FROM_NAT].dest_ip, ip_dest_addr_nat);
+		ovs_params[ECM_DB_OBJ_DIR_FROM_NAT].src_port = src_port_nat;
+		ovs_params[ECM_DB_OBJ_DIR_FROM_NAT].dest_port = dest_port_nat;
+
+		ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_TO_NAT].src_ip, ip_src_addr_nat);
+		ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_TO_NAT].dest_ip, ip_dest_addr_nat);
+		ovs_params[ECM_DB_OBJ_DIR_TO_NAT].src_port = src_port_nat;
+		ovs_params[ECM_DB_OBJ_DIR_TO_NAT].dest_port = dest_port_nat;
+	} else if (ecm_dir == ECM_DB_DIRECTION_INGRESS_NAT) {
+		/*
+		 * For DNAT case (INGRESS_NAT), we use specific IP/port combinations to look-up
+		 * the FROM_NAT and TO_NAT ports.
+		 */
+		ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_FROM_NAT].src_ip, ip_dest_addr_nat);
+		ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_FROM_NAT].dest_ip, ip_src_addr_nat);
+		ovs_params[ECM_DB_OBJ_DIR_FROM_NAT].src_port = dest_port_nat;
+		ovs_params[ECM_DB_OBJ_DIR_FROM_NAT].dest_port = src_port_nat;
+
+		ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_TO_NAT].src_ip, ip_dest_addr_nat);
+		ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_TO_NAT].dest_ip, ip_src_addr_nat);
+		ovs_params[ECM_DB_OBJ_DIR_TO_NAT].src_port = dest_port_nat;
+		ovs_params[ECM_DB_OBJ_DIR_TO_NAT].dest_port = src_port_nat;
+	} else {
+		/*
+		 * For Non-NAT case, we use the same IP/port combinations of FROM and TO to look-up
+		 * the FROM_NAT and TO_NAT ports.
+		 */
+		ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_FROM_NAT].src_ip, ip_dest_addr_nat);
+		ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_FROM_NAT].dest_ip, ip_src_addr);
+		ovs_params[ECM_DB_OBJ_DIR_FROM_NAT].src_port = dest_port_nat;
+		ovs_params[ECM_DB_OBJ_DIR_FROM_NAT].dest_port = src_port;
+
+		ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_TO_NAT].src_ip, ip_src_addr_nat);
+		ECM_IP_ADDR_COPY(ovs_params[ECM_DB_OBJ_DIR_TO_NAT].dest_ip, ip_dest_addr);
+		ovs_params[ECM_DB_OBJ_DIR_TO_NAT].src_port = src_port_nat;
+		ovs_params[ECM_DB_OBJ_DIR_TO_NAT].dest_port = dest_port;
+	}
+}
+
+/*
+ * ecm_front_end_get_slow_packet_count()
+ *	Gets the slow path packet count for the given connection.
+ */
+uint64_t ecm_front_end_get_slow_packet_count(struct ecm_front_end_connection_instance *feci)
+{
+	uint64_t slow_pkts;
+
+	spin_lock_bh(&feci->lock);
+	slow_pkts = feci->stats.slow_path_packets;
+	spin_unlock_bh(&feci->lock);
+	return slow_pkts;
+}
+
+/*
+ * ecm_front_end_db_conn_limit_handler()
+ *	Database connection limit sysctl node handler.
+ */
+int ecm_front_end_db_conn_limit_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret;
+	int current_value;
+
+	/*
+	 * Take the current value
+	 */
+	current_value = ecm_front_end_conn_limit;
+
+	/*
+	 * Write the variable with user input
+	 */
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret || (!write)) {
+		/*
+		 * Return failure.
+		 */
+		return ret;
+	}
+
+	if ((ecm_front_end_conn_limit != 0) &&
+			(ecm_front_end_conn_limit != 1)) {
+		DEBUG_WARN("Invalid input. Valid values 0/1\n");
+		ecm_front_end_conn_limit = current_value;
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static struct ctl_table ecm_front_end_sysctl_tbl[] = {
+	{
+		.procname	= "front_end_conn_limit",
+		.data		= &ecm_front_end_conn_limit,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &ecm_front_end_db_conn_limit_handler,
+	},
+	{}
+};
+
+static struct ctl_table ecm_front_end_common_root[] = {
+	{
+		.procname	= "ecm",
+		.mode		= 0555,
+		.child		= ecm_front_end_sysctl_tbl,
+	},
+	{ }
+};
+
+static struct ctl_table ecm_front_end_common_root_dir[] = {
+	{
+		.procname		= "net",
+		.mode			= 0555,
+		.child			= ecm_front_end_common_root,
+	},
+	{ }
+};
+
+/*
+ * ecm_front_end_common_sysctl_register()
+ *	Function to register sysctl node during front end init
+ */
+void ecm_front_end_common_sysctl_register()
+{
+	/*
+	 * Register sysctl table.
+	 */
+	ecm_front_end_ctl_tbl_hdr = register_sysctl_table(ecm_front_end_common_root_dir);
+#ifdef ECM_FRONT_END_SFE_ENABLE
+	if (ecm_front_end_ctl_tbl_hdr) {
+		ecm_sfe_sysctl_tbl_init();
+	}
+#endif
+}
+
+/*
+ * ecm_front_end_common_sysctl_unregister()
+ *	Function to unregister sysctl node during front end exit
+ */
+void ecm_front_end_common_sysctl_unregister()
+{
+	/*
+	 * Unregister sysctl table.
+	 */
+	if (ecm_front_end_ctl_tbl_hdr) {
+#ifdef ECM_FRONT_END_SFE_ENABLE
+		ecm_sfe_sysctl_tbl_exit();
+#endif
+		unregister_sysctl_table(ecm_front_end_ctl_tbl_hdr);
+	}
+}
diff --git a/qca-nss-ecm/frontends/ecm_front_end_ipv4.c b/qca-nss-ecm/frontends/ecm_front_end_ipv4.c
new file mode 100644
index 0000000..2d72164
--- /dev/null
+++ b/qca-nss-ecm/frontends/ecm_front_end_ipv4.c
@@ -0,0 +1,395 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2016, 2020-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/debugfs.h>
+#include <linux/inet.h>
+#include <linux/etherdevice.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/ip.h>
+#include <net/ipv6.h>
+#include <net/route.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_FRONT_END_IPV4_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_front_end_ipv4.h"
+#include "ecm_interface.h"
+#include "ecm_ipv4.h"
+
+/*
+ * General operational control
+ */
+int ecm_front_end_ipv4_stopped = 0;	/* When non-zero further traffic will not be processed */
+
+/*
+ * ecm_front_end_ipv4_interface_construct_ip_addr_set()
+ *	Sets the IP addresses.
+ *
+ * Sets the ip address fields of the ecm_front_end_interface_construct_instance
+ * with the given ip addresses.
+ */
+static void ecm_front_end_ipv4_interface_construct_ip_addr_set(struct ecm_front_end_interface_construct_instance *efeici,
+							ip_addr_t from_mac_lookup, ip_addr_t to_mac_lookup,
+							ip_addr_t from_nat_mac_lookup, ip_addr_t to_nat_mac_lookup)
+{
+	ECM_IP_ADDR_COPY(efeici->from_mac_lookup_ip_addr, from_mac_lookup);
+	ECM_IP_ADDR_COPY(efeici->to_mac_lookup_ip_addr, to_mac_lookup);
+	ECM_IP_ADDR_COPY(efeici->from_nat_mac_lookup_ip_addr, from_nat_mac_lookup);
+	ECM_IP_ADDR_COPY(efeici->to_nat_mac_lookup_ip_addr, to_nat_mac_lookup);
+}
+
+/*
+ * ecm_front_end_ipv4_interface_construct_netdev_set()
+ *	Sets the net devices.
+ *
+ * Sets the net device fields of the ecm_front_end_interface_construct_instance
+ * with the given net devices.
+ */
+static void ecm_front_end_ipv4_interface_construct_netdev_set(struct ecm_front_end_interface_construct_instance *efeici,
+							struct net_device *from, struct net_device *from_other,
+							struct net_device *to, struct net_device *to_other,
+							struct net_device *from_nat, struct net_device *from_nat_other,
+							struct net_device *to_nat, struct net_device *to_nat_other)
+{
+	efeici->from_dev = from;
+	efeici->from_other_dev = from_other;
+	efeici->to_dev = to;
+	efeici->to_other_dev = to_other;
+	efeici->from_nat_dev = from_nat;
+	efeici->from_nat_other_dev = from_nat_other;
+	efeici->to_nat_dev = to_nat;
+	efeici->to_nat_other_dev = to_nat_other;
+}
+
+/*
+ * ecm_front_end_ipv4_interface_construct_netdev_put()
+ *	Release the references of the net devices.
+ */
+void ecm_front_end_ipv4_interface_construct_netdev_put(struct ecm_front_end_interface_construct_instance *efeici)
+{
+	dev_put(efeici->from_dev);
+	dev_put(efeici->from_other_dev);
+	dev_put(efeici->to_dev);
+	dev_put(efeici->to_other_dev);
+	dev_put(efeici->from_nat_dev);
+	dev_put(efeici->from_nat_other_dev);
+	dev_put(efeici->to_nat_dev);
+	dev_put(efeici->to_nat_other_dev);
+}
+
+/*
+ * ecm_front_end_ipv4_interface_construct_netdev_hold()
+ *	Holds the references of the netdevices.
+ */
+void ecm_front_end_ipv4_interface_construct_netdev_hold(struct ecm_front_end_interface_construct_instance *efeici)
+{
+	dev_hold(efeici->from_dev);
+	dev_hold(efeici->from_other_dev);
+	dev_hold(efeici->to_dev);
+	dev_hold(efeici->to_other_dev);
+	dev_hold(efeici->from_nat_dev);
+	dev_hold(efeici->from_nat_other_dev);
+	dev_hold(efeici->to_nat_dev);
+	dev_hold(efeici->to_nat_other_dev);
+}
+
+/*
+ * ecm_front_end_ipv4_interface_construct_set_and_hold()
+ *	Sets the IPv4 ECM front end interface construct instance,
+ *	and holds the net devices.
+ */
+bool ecm_front_end_ipv4_interface_construct_set_and_hold(struct sk_buff *skb, ecm_tracker_sender_type_t sender, ecm_db_direction_t ecm_dir, bool is_routed,
+							struct net_device *in_dev, struct net_device *out_dev,
+							ip_addr_t ip_src_addr, ip_addr_t ip_src_addr_nat,
+							ip_addr_t ip_dest_addr, ip_addr_t ip_dest_addr_nat,
+							struct ecm_front_end_interface_construct_instance *efeici)
+{
+	struct dst_entry *dst = skb_dst(skb);
+	struct rtable *rt = (struct rtable *)dst;
+	struct net_device *rt_iif_dev = NULL;
+	ip_addr_t rt_dst_addr;
+	struct net_device *from = NULL;
+	struct net_device *from_other = NULL;
+	struct net_device *to = NULL;
+	struct net_device *to_other = NULL;
+	struct net_device *from_nat = NULL;
+	struct net_device *from_nat_other = NULL;
+	struct net_device *to_nat = NULL;
+	struct net_device *to_nat_other = NULL;
+	struct net_device *dst_dev = NULL;
+	ip_addr_t from_mac_lookup;
+	ip_addr_t to_mac_lookup;
+	ip_addr_t from_nat_mac_lookup;
+	ip_addr_t to_nat_mac_lookup;
+	bool gateway = false;
+	bool dst_dev_override = false;
+
+	/*
+	 * Set the rt_dst_addr with the destination IP address by default.
+	 * If there is a gateway IP address, this will be overwritten with the gateway IP address.
+	 */
+	ECM_IP_ADDR_COPY(rt_dst_addr, ip_dest_addr);
+
+	if (!is_routed) {
+		/*
+		 * Bridged
+		 */
+		from = in_dev;
+		from_other = in_dev;
+		to = out_dev;
+		to_other = out_dev;
+	} else {
+		__be32 rt_gw4;
+
+		if (!rt) {
+			DEBUG_WARN("rtable is NULL\n");
+			return false;
+		}
+
+		/*
+		 * If the flow is routed, extract the route information from the skb.
+		 * Print the extracted information for debug purpose.
+		 */
+		rt_iif_dev = dev_get_by_index(&init_net, skb->skb_iif);
+		if (!rt_iif_dev) {
+			DEBUG_WARN("No rt_iif dev\n");
+			return false;
+		}
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 2, 0))
+		rt_gw4 = rt->rt_gateway;
+#else
+		rt_gw4 = rt->rt_gw4;
+#endif
+		dst_dev = dst->dev;
+
+#ifdef ECM_XFRM_ENABLE
+		/*
+		 * If the dst is an xfrm dst, then override the dst_dev.
+		*/
+		if (dst_xfrm(dst)) {
+			int32_t if_type;
+			struct net_device *xfrm_dst_dev = ecm_interface_get_and_hold_ipsec_tun_netdev(NULL, skb, &if_type);
+			/*
+			 * If we reach here and are unable to find the tunnel netdevice,
+			 * then return failure.
+			 */
+			if (!xfrm_dst_dev) {
+				return false;
+			}
+
+			dst_dev = xfrm_dst_dev;
+			dst_dev_override = true;
+		}
+
+#endif
+		DEBUG_TRACE("dst->dev: %s dst_dev: %s\n", dst->dev->name, dst_dev->name);
+		DEBUG_TRACE("%px: rt gateway: %pI4\n", rt, &rt_gw4);
+
+		DEBUG_INFO("ip_src_addr" ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(ip_src_addr));
+		DEBUG_INFO("ip_src_addr_nat" ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(ip_src_addr_nat));
+		DEBUG_INFO("ip_dest_addr" ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(ip_dest_addr));
+		DEBUG_INFO("ip_dest_addr_nat" ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(ip_dest_addr_nat));
+
+		if (rt->rt_uses_gateway || (rt->rt_flags & RTF_GATEWAY)) {
+			/*
+			 * Overwrite the rt_dst_addr with the gateway IP address. The destination host is
+			 * behind a gateway.
+			 */
+			DEBUG_TRACE("Gateway address will be looked up overwrite the rt_dst_addr\n");
+			ECM_NIN4_ADDR_TO_IP_ADDR(rt_dst_addr, rt_gw4)
+			gateway = true;
+		}
+
+		DEBUG_INFO("rt_dst_addr" ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(rt_dst_addr));
+
+		/*
+		 * Initialize the interfaces with defaults.
+		 * rt_iif_dev is the interface which the packet comes in to the system,
+		 * dst->dev is the interface which the packet goes out from the system.
+		 */
+		from = rt_iif_dev;
+		from_other = dst_dev;
+		to = dst_dev;
+		to_other = rt_iif_dev;
+	}
+
+	/*
+	 * Just in case the is_routed flag comes as 0, but the ecm_dir is different than
+	 * bridge flow, we check the netdevices here before setting the efeici fields.
+	 *
+	 * TODO: Why ecm_dir comes as non-bridge flow, even though the is_routed flag is bridged?
+	 */
+	if (ecm_dir != ECM_DB_DIRECTION_BRIDGED) {
+		if (!dst || !dst_dev || !rt_iif_dev) {
+			DEBUG_WARN("Traffic is not bridged but the netdevs are not valid\n");
+			if (rt_iif_dev) {
+				dev_put(rt_iif_dev);
+			}
+			if (dst_dev_override) {
+				dev_put(dst_dev);
+			}
+			return false;
+		}
+	}
+
+	/*
+	 * Initialize the mac lookup ip addresses with defaults.
+	 */
+	ECM_IP_ADDR_COPY(from_mac_lookup, ip_src_addr);
+	ECM_IP_ADDR_COPY(to_mac_lookup, rt_dst_addr);
+	ECM_IP_ADDR_COPY(from_nat_mac_lookup, ip_src_addr_nat);
+
+	/*
+	 * If we have a gateway IP address we should use it for the
+	 * to_nat_mac_lookup IP address.
+	 * Note that in hairpin NAT the destination IP address and the destination
+	 * NAT IP addresses are different than each other. Because of this we cannot
+	 * use the rt_dst_addr for to_nat_mac_lookup as well. In a normal routing
+	 * traffic they are equal.
+	 */
+	if (gateway) {
+		ECM_IP_ADDR_COPY(to_nat_mac_lookup, rt_dst_addr);
+	} else {
+		ECM_IP_ADDR_COPY(to_nat_mac_lookup, ip_dest_addr_nat);
+	}
+
+	/*
+	 * Based on the flow and connection direction, set the NAT'd net devices.
+	 * The above IP address settings are valid for each flow and connection direction case.
+	 */
+	if (sender == ECM_TRACKER_SENDER_TYPE_SRC) {
+		if (ecm_dir == ECM_DB_DIRECTION_EGRESS_NAT) {
+			from_nat = dst_dev;
+			from_nat_other = rt_iif_dev;
+			to_nat = dst_dev;
+			to_nat_other = rt_iif_dev;
+		} else if (ecm_dir == ECM_DB_DIRECTION_NON_NAT) {
+			from_nat = rt_iif_dev;
+			from_nat_other = dst_dev;
+			to_nat = dst_dev;
+			to_nat_other = rt_iif_dev;
+		} else if (ecm_dir == ECM_DB_DIRECTION_INGRESS_NAT) {
+			from_nat = rt_iif_dev;
+			from_nat_other = dst_dev;
+			to_nat = rt_iif_dev;
+			to_nat_other = dst_dev;
+		} else if (ecm_dir == ECM_DB_DIRECTION_BRIDGED) {
+			from_nat = in_dev;
+			from_nat_other = in_dev;
+			to_nat = out_dev;
+			to_nat_other = out_dev;
+		} else {
+			DEBUG_ASSERT(false, "Unhandled ecm_dir: %d\n", ecm_dir);
+		}
+	} else {
+		if (ecm_dir == ECM_DB_DIRECTION_EGRESS_NAT) {
+			from_nat = rt_iif_dev;
+			from_nat_other = dst_dev;
+			to_nat = rt_iif_dev;
+			to_nat_other = dst_dev;
+		} else if (ecm_dir == ECM_DB_DIRECTION_NON_NAT) {
+			from_nat = rt_iif_dev;
+			from_nat_other = dst_dev;
+			to_nat = dst_dev;
+			to_nat_other = rt_iif_dev;
+		} else if (ecm_dir == ECM_DB_DIRECTION_INGRESS_NAT) {
+			from_nat = dst_dev;
+			from_nat_other = rt_iif_dev;
+			to_nat = dst_dev;
+			to_nat_other = rt_iif_dev;
+		} else if (ecm_dir == ECM_DB_DIRECTION_BRIDGED) {
+			from_nat = in_dev;
+			from_nat_other = in_dev;
+			to_nat = out_dev;
+			to_nat_other = out_dev;
+		} else {
+			DEBUG_ASSERT(false, "Unhandled ecm_dir: %d\n", ecm_dir);
+		}
+	}
+
+	ecm_front_end_ipv4_interface_construct_netdev_set(efeici, from, from_other,
+								to, to_other,
+								from_nat, from_nat_other,
+								to_nat, to_nat_other);
+
+	ecm_front_end_ipv4_interface_construct_netdev_hold(efeici);
+
+	ecm_front_end_ipv4_interface_construct_ip_addr_set(efeici, from_mac_lookup, to_mac_lookup,
+								from_nat_mac_lookup, to_nat_mac_lookup);
+
+	if (dst_dev_override) {
+		dev_put(dst_dev);
+	}
+
+	/*
+	 * Release the iff_dev which was hold by the dev_get_by_index() call.
+	 */
+	if (rt_iif_dev) {
+		dev_put(rt_iif_dev);
+	}
+
+	return true;
+}
+
+/*
+ * ecm_front_end_ipv4_stop()
+ */
+void ecm_front_end_ipv4_stop(int num)
+{
+	ecm_front_end_ipv4_stopped = num;
+}
+
+/*
+ * ecm_front_end_ipv4_init()
+ */
+int ecm_front_end_ipv4_init(struct dentry *dentry)
+{
+	if (!debugfs_create_u32("front_end_ipv4_stop", S_IRUGO | S_IWUSR, dentry,
+					(u32 *)&ecm_front_end_ipv4_stopped)) {
+		DEBUG_ERROR("Failed to create ecm front end ipv4 stop file in debugfs\n");
+		return -1;
+	}
+
+	return ecm_ipv4_init(dentry);
+}
+
+/*
+ * ecm_front_end_ipv4_exit()
+ */
+void ecm_front_end_ipv4_exit(void)
+{
+	ecm_ipv4_exit();
+}
diff --git a/qca-nss-ecm/frontends/ecm_front_end_ipv6.c b/qca-nss-ecm/frontends/ecm_front_end_ipv6.c
new file mode 100644
index 0000000..844e341
--- /dev/null
+++ b/qca-nss-ecm/frontends/ecm_front_end_ipv6.c
@@ -0,0 +1,274 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2017, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/debugfs.h>
+#include <linux/inet.h>
+#include <linux/etherdevice.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/ip.h>
+#include <net/ipv6.h>
+#include <net/ip6_route.h>
+#include <net/route.h>
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_FRONT_END_IPV6_DEBUG_LEVEL
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_front_end_ipv6.h"
+#include "ecm_interface.h"
+#include "ecm_ipv6.h"
+
+/*
+ * General operational control
+ */
+int ecm_front_end_ipv6_stopped = 0;	/* When non-zero further traffic will not be processed */
+
+/*
+ * ecm_front_end_ipv6_interface_construct_ip_addr_set()
+ *	Sets the IP addresses.
+ *
+ * Sets the ip address fields of the ecm_front_end_interface_construct_instance
+ * with the given ip addresses.
+ */
+static void ecm_front_end_ipv6_interface_construct_ip_addr_set(struct ecm_front_end_interface_construct_instance *efeici,
+							ip_addr_t from_mac_lookup, ip_addr_t to_mac_lookup)
+{
+	ECM_IP_ADDR_COPY(efeici->from_mac_lookup_ip_addr, from_mac_lookup);
+	ECM_IP_ADDR_COPY(efeici->to_mac_lookup_ip_addr, to_mac_lookup);
+}
+
+/*
+ * ecm_front_end_ipv6_interface_construct_netdev_set()
+ *	Sets the net devices.
+ *
+ * Sets the net device fields of the ecm_front_end_interface_construct_instance
+ * with the given net devices.
+ */
+static void ecm_front_end_ipv6_interface_construct_netdev_set(struct ecm_front_end_interface_construct_instance *efeici,
+							struct net_device *from, struct net_device *from_other,
+							struct net_device *to, struct net_device *to_other)
+{
+	efeici->from_dev = from;
+	efeici->from_other_dev = from_other;
+	efeici->to_dev = to;
+	efeici->to_other_dev = to_other;
+}
+
+/*
+ * ecm_front_end_ipv6_interface_construct_netdev_put()
+ *	Release the references of the net devices.
+ */
+void ecm_front_end_ipv6_interface_construct_netdev_put(struct ecm_front_end_interface_construct_instance *efeici)
+{
+	dev_put(efeici->from_dev);
+	dev_put(efeici->from_other_dev);
+	dev_put(efeici->to_dev);
+	dev_put(efeici->to_other_dev);
+}
+
+/*
+ * ecm_front_end_ipv6_interface_construct_netdev_hold()
+ *	Holds the references of the netdevices.
+ */
+void ecm_front_end_ipv6_interface_construct_netdev_hold(struct ecm_front_end_interface_construct_instance *efeici)
+{
+	dev_hold(efeici->from_dev);
+	dev_hold(efeici->from_other_dev);
+	dev_hold(efeici->to_dev);
+	dev_hold(efeici->to_other_dev);
+}
+
+/*
+ * ecm_front_end_ipv6_interface_construct_set_and_hold()
+ *	Sets the IPv6 ECM front end interface construct instance,
+ *	and holds the net devices.
+ */
+bool ecm_front_end_ipv6_interface_construct_set_and_hold(struct sk_buff *skb, ecm_tracker_sender_type_t sender, ecm_db_direction_t ecm_dir, bool is_routed,
+							struct net_device *in_dev, struct net_device *out_dev,
+							ip_addr_t ip_src_addr, ip_addr_t ip_dest_addr,
+							struct ecm_front_end_interface_construct_instance *efeici)
+{
+	struct dst_entry *dst = skb_dst(skb);
+	struct rt6_info *rt = (struct rt6_info *)dst;
+	ip_addr_t rt_dst_addr;
+	struct net_device *rt_iif_dev = NULL;
+	struct net_device *from = NULL;
+	struct net_device *from_other = NULL;
+	struct net_device *to = NULL;
+	struct net_device *to_other = NULL;
+	struct net_device *dst_dev = NULL;
+	ip_addr_t from_mac_lookup;
+	ip_addr_t to_mac_lookup;
+	bool dst_dev_override = false;
+
+	/*
+	 * Set the rt_dst_addr with the destination IP address by default.
+	 */
+	ECM_IP_ADDR_COPY(rt_dst_addr, ip_dest_addr);
+
+	if (!is_routed) {
+		/*
+		 * Bridged
+		 */
+		from = in_dev;
+		from_other = in_dev;
+		to = out_dev;
+		to_other = out_dev;
+
+		ECM_IP_ADDR_COPY(from_mac_lookup, ip_src_addr);
+		ECM_IP_ADDR_COPY(to_mac_lookup, ip_dest_addr);
+	} else {
+		/*
+		 * Routed
+		 */
+		if (!rt) {
+			DEBUG_WARN("rt6_info is NULL\n");
+			return false;
+		}
+
+		/*
+		 * If the flow is routed, extract the route information from the skb.
+		 * Print the extracted information for debug purpose.
+		 */
+		rt_iif_dev = dev_get_by_index(&init_net, skb->skb_iif);
+		if (!rt_iif_dev) {
+			DEBUG_WARN("No rt_iif dev\n");
+			return false;
+		}
+
+		dst_dev = dst->dev;
+
+#ifdef ECM_XFRM_ENABLE
+		/*
+		 * If the dst is an xfrm dst, then override the dst_dev.
+		*/
+		if (dst_xfrm(dst)) {
+			int32_t if_type;
+			struct net_device *xfrm_dst_dev = ecm_interface_get_and_hold_ipsec_tun_netdev(NULL, skb, &if_type);
+			/*
+			 * If we reach here and are unable to find the tunnel netdevice,
+			 * then return failure.
+			 */
+			if (!xfrm_dst_dev) {
+				return false;
+			}
+
+			dst_dev = xfrm_dst_dev;
+			dst_dev_override = true;
+		}
+
+#endif
+		DEBUG_TRACE("in_dev: %s\n", in_dev->name);
+		DEBUG_TRACE("out_dev: %s\n", out_dev->name);
+		DEBUG_TRACE("dst->dev: %s dst_dev: %s\n", dst_dev->name, dst_dev->name);
+		DEBUG_TRACE("rt_iif_dev: %s\n", rt_iif_dev->name);
+		DEBUG_TRACE("%px: rt6i_dst.addr: %pi6\n", rt, &rt->rt6i_dst.addr);
+		DEBUG_TRACE("%px: rt6i_src.addr: %pi6\n", rt, &rt->rt6i_src.addr);
+		DEBUG_TRACE("%px: rt6i_gateway: %pi6\n", rt, &rt->rt6i_gateway);
+		DEBUG_TRACE("%px: rt6i_idev: %s\n", rt, rt->rt6i_idev->dev->name);
+		DEBUG_TRACE("%px: skb->dev: %s\n", rt, skb->dev->name);
+
+		DEBUG_INFO("ip_src_addr: " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(ip_src_addr));
+		DEBUG_INFO("ip_dest_addr: " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(ip_dest_addr));
+
+		/*
+		 * If the destination host is behind a gateway, use the gateway address as destination
+		 * for routed connections.
+		 */
+		if (!ECM_IP_ADDR_MATCH(rt->rt6i_dst.addr.in6_u.u6_addr32, rt->rt6i_gateway.in6_u.u6_addr32) || (rt->rt6i_flags & RTF_GATEWAY)) {
+			if (!ECM_IP_ADDR_IS_NULL(rt->rt6i_gateway.in6_u.u6_addr32)) {
+				ECM_NIN6_ADDR_TO_IP_ADDR(rt_dst_addr, rt->rt6i_gateway);
+			}
+		}
+
+		from = rt_iif_dev;
+		from_other = dst_dev;
+		to = dst_dev;
+		to_other = rt_iif_dev;
+
+		ECM_IP_ADDR_COPY(from_mac_lookup, ip_src_addr);
+		ECM_IP_ADDR_COPY(to_mac_lookup, rt_dst_addr);
+	}
+
+	ecm_front_end_ipv6_interface_construct_netdev_set(efeici, from, from_other,
+								to, to_other);
+
+	ecm_front_end_ipv6_interface_construct_netdev_hold(efeici);
+
+	ecm_front_end_ipv6_interface_construct_ip_addr_set(efeici, from_mac_lookup, to_mac_lookup);
+
+	if (dst_dev_override) {
+		dev_put(dst_dev);
+	}
+
+	/*
+	 * Release the iff_dev which was hold by the dev_get_by_index() call.
+	 */
+	if (rt_iif_dev) {
+		dev_put(rt_iif_dev);
+	}
+
+	return true;
+}
+
+/*
+ * ecm_front_end_ipv6_stop()
+ */
+void ecm_front_end_ipv6_stop(int num)
+{
+	ecm_front_end_ipv6_stopped = num;
+}
+
+/*
+ * ecm_front_end_ipv6_init()
+ */
+int ecm_front_end_ipv6_init(struct dentry *dentry)
+{
+	if (!debugfs_create_u32("front_end_ipv6_stop", S_IRUGO | S_IWUSR, dentry,
+					(u32 *)&ecm_front_end_ipv6_stopped)) {
+		DEBUG_ERROR("Failed to create ecm front end ipv6 stop file in debugfs\n");
+		return -1;
+	}
+
+	return ecm_ipv6_init(dentry);
+}
+
+/*
+ * ecm_front_end_ipv6_exit()
+ */
+void ecm_front_end_ipv6_exit(void)
+{
+	ecm_ipv6_exit();
+}
diff --git a/qca-nss-ecm/frontends/include/ecm_front_end_common.h b/qca-nss-ecm/frontends/include/ecm_front_end_common.h
new file mode 100644
index 0000000..0c70a1d
--- /dev/null
+++ b/qca-nss-ecm/frontends/include/ecm_front_end_common.h
@@ -0,0 +1,317 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2016, 2019-2021, The Linux Foundation.  All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __ECM_FRONT_END_COMMON_H
+#define __ECM_FRONT_END_COMMON_H
+
+#include <linux/if_pppox.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include "ecm_bond_notifier.h"
+
+#define ECM_FRONT_END_SYSCTL_PATH "/net/ecm"
+
+/*
+ * Flag to limit the number of DB connections at any point to the maximum number
+ * that can be accelerated by NSS. This may need to be enabled for low memory
+ * platforms to control memory allocated by ECM databases.
+ */
+extern unsigned int ecm_front_end_conn_limit;
+
+/*
+ * ecm_front_end_l2_encap_header_len()
+ *      Return length of encapsulating L2 header
+ */
+static inline uint32_t ecm_front_end_l2_encap_header_len(uint16_t protocol)
+{
+	switch (protocol) {
+	case ETH_P_PPP_SES:
+		return PPPOE_SES_HLEN;
+	default:
+		return 0;
+	}
+}
+
+/*
+ * ecm_front_end_pull_l2_encap_header()
+ *      Pull encapsulating L2 header
+ */
+static inline void ecm_front_end_pull_l2_encap_header(struct sk_buff *skb, uint32_t len)
+{
+	skb->data += len;
+	skb->network_header += len;
+}
+
+/*
+ * ecm_front_end_push_l2_encap_header()
+ *      Push encapsulating L2 header
+ */
+static inline void ecm_front_end_push_l2_encap_header(struct sk_buff *skb, uint32_t len)
+{
+	skb->data -= len;
+	skb->network_header -= len;
+}
+
+/*
+ * ecm_front_end_acceleration_rejected()
+ *      Check if the acceleration of a flow could be rejected quickly.
+ */
+static inline bool ecm_front_end_acceleration_rejected(struct sk_buff *skb)
+{
+	struct nf_conn *ct;
+	enum ip_conntrack_info ctinfo;
+	struct nf_conn_counter *acct;
+
+	ct = nf_ct_get(skb, &ctinfo);
+	if (unlikely(!ct)) {
+		/*
+		 * Maybe bridged traffic, no decision here.
+		 */
+		return false;
+	}
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
+	if (unlikely(nf_ct_is_untracked(ct))) {
+#else
+	if (unlikely(ctinfo == IP_CT_UNTRACKED)) {
+#endif
+		/*
+		 * Untracked traffic certainly can't be accelerated.
+		 */
+		return true;
+	}
+
+	acct = nf_conn_acct_find(ct)->counter;
+	if (acct) {
+		long long packets = atomic64_read(&acct[CTINFO2DIR(ctinfo)].packets);
+		if ((packets > 0xff) && (packets & 0xff)) {
+			/*
+			 * Connection hits slow path at least 256 times, so it must be not able to accelerate.
+			 * But we also give it a chance to walk through ECM every 256 packets
+			 */
+			return true;
+		}
+	}
+
+	return false;
+}
+
+/*
+ * ecm_front_end_flow_and_return_directions_get()
+ *	Gets the flow and return flows directions respect to conntrack entry.
+ */
+static inline void ecm_front_end_flow_and_return_directions_get(struct nf_conn *ct, ip_addr_t flow_ip, int ip_version, int *flow_dir, int *return_dir)
+{
+	ip_addr_t ct_src_ip;
+
+	if (ip_version == 4) {
+		uint32_t flow_ip_32;
+		uint32_t ct_src_ip_32;
+		ECM_NIN4_ADDR_TO_IP_ADDR(ct_src_ip, ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3.ip);
+
+		/*
+		 * Print the IP addresses for debug purpose.
+		 */
+		ECM_IP_ADDR_TO_HIN4_ADDR(flow_ip_32, flow_ip);
+		ECM_IP_ADDR_TO_HIN4_ADDR(ct_src_ip_32, ct_src_ip);
+		DEBUG_TRACE("flow_ip: %pI4h ct_src_ip: %pI4h\n", &flow_ip_32, &ct_src_ip_32);
+	} else if (ip_version == 6) {
+		ECM_NIN6_ADDR_TO_IP_ADDR(ct_src_ip, ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3.in6);
+
+		/*
+		 * Print the IP addresses for debug purpose.
+		 */
+		DEBUG_TRACE("flow_ip: " ECM_IP_ADDR_OCTAL_FMT " ct_src_ip: " ECM_IP_ADDR_OCTAL_FMT "\n",
+				ECM_IP_ADDR_TO_OCTAL(flow_ip), ECM_IP_ADDR_TO_OCTAL(ct_src_ip));
+	} else {
+		DEBUG_ASSERT(NULL, "Invalid ip version");
+	}
+
+	if (ECM_IP_ADDR_MATCH(ct_src_ip, flow_ip)) {
+		*flow_dir = IP_CT_DIR_ORIGINAL;
+		*return_dir = IP_CT_DIR_REPLY;
+		DEBUG_TRACE("flow_ip and ct_src_ip match\n");
+	} else {
+		*flow_dir = IP_CT_DIR_REPLY;
+		*return_dir = IP_CT_DIR_ORIGINAL;
+		DEBUG_TRACE("flow_ip and ct_src_ip do not match\n");
+	}
+
+	DEBUG_TRACE("flow_dir: %d return_dir: %d\n", *flow_dir, *return_dir);
+}
+
+/*
+ * ecm_front_end_common_connection_defunct_check()
+ *	Checks if the connection can be defuncted.
+ * The return value indicates that the caller is allowed to send a defunct message.
+ */
+static inline bool ecm_front_end_common_connection_defunct_check(struct ecm_front_end_connection_instance *feci)
+{
+	DEBUG_ASSERT(spin_is_locked(&feci->lock), "%px: feci lock is not held\n", feci);
+
+	/*
+	 * If we have not completed the destroy failure handling, do nothing.
+	 */
+	if (feci->destroy_fail_handle_pending) {
+		return false;
+	}
+
+	/*
+	 * If connection has already become defunct, do nothing.
+	 */
+	if (feci->is_defunct) {
+		return false;
+	}
+	feci->is_defunct = true;
+
+	/*
+	 * If the connection is already in one of the fail modes, do nothing, keep the current accel_mode.
+	 */
+	if (ECM_FRONT_END_ACCELERATION_FAILED(feci->accel_mode)) {
+		return false;
+	}
+
+	/*
+	 * If the connection is decel then ensure it will not attempt accel while defunct.
+	 */
+	if (feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_DECEL) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT;
+		return false;
+	 }
+
+	/*
+	 * If the connection is decel pending then decel operation is in progress anyway.
+	 */
+	if (feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING) {
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * ecm_front_end_common_connection_decelerate_accel_mode_check()
+ *	Checks the accel mode of the connection to see it is ok for deceleration.
+ * The return value indicates that the caller is allowed to send a decelerate message.
+ */
+static inline bool ecm_front_end_common_connection_decelerate_accel_mode_check(struct ecm_front_end_connection_instance *feci)
+{
+	DEBUG_ASSERT(spin_is_locked(&feci->lock), "%px: feci lock is not held\n", feci);
+
+	/*
+	 * If decelerate is in error or already pending then ignore
+	 */
+	if (feci->stats.decelerate_pending) {
+		return false;
+	}
+
+	/*
+	 * If acceleration is pending then we cannot decelerate right now or we will race with it
+	 * Set a decelerate pending flag that will be actioned when the acceleration command is complete.
+	 */
+	if (feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING) {
+		feci->stats.decelerate_pending = true;
+		return false;
+	}
+
+	/*
+	 * Can only decelerate if accelerated
+	 * NOTE: This will also deny accel when the connection is in fail condition too.
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_ACCEL) {
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * ecm_front_end_destroy_failure_handle()
+ *	Destroy request failure handler.
+ */
+static inline bool ecm_front_end_destroy_failure_handle(struct ecm_front_end_connection_instance *feci)
+{
+
+	spin_lock_bh(&feci->lock);
+	feci->stats.driver_fail_total++;
+	feci->stats.driver_fail++;
+	if (feci->stats.driver_fail >= feci->stats.driver_fail_limit) {
+		/*
+		 * Reached to the driver failure limit. ECM no longer allows
+		 * re-trying deceleration.
+		 */
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DRIVER;
+		spin_unlock_bh(&feci->lock);
+		DEBUG_WARN("%px: Decel failed - driver fail limit\n", feci);
+		return true;
+	}
+
+	/*
+	 * Destroy request failed. The accelerated connection couldn't be destroyed
+	 * in the acceleration engine. Revert back the accel_mode, unset the is_defunct
+	 * flag just in case this request has come through the defunct process.
+	 */
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_ACCEL;
+	feci->is_defunct = false;
+	feci->destroy_fail_handle_pending = true;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Set the defunct timer to a smaller timeout value so that the connection will be
+	 * tried to be defuncted again, when the timeout expires (its value is 5 seconds).
+	 */
+	ecm_db_connection_defunct_timer_remove_and_set(feci->ci, ECM_DB_TIMER_GROUPS_CONNECTION_DEFUNCT_RETRY_TIMEOUT);
+
+	spin_lock_bh(&feci->lock);
+	feci->destroy_fail_handle_pending = false;
+	spin_unlock_bh(&feci->lock);
+
+	return false;
+}
+
+extern void ecm_front_end_bond_notifier_stop(int num);
+extern int ecm_front_end_bond_notifier_init(struct dentry *dentry);
+extern void ecm_front_end_bond_notifier_exit(void);
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+extern int ecm_front_end_common_connection_state_get(struct ecm_front_end_connection_instance *feci,
+						    struct ecm_state_file_instance *sfi,
+						    char *conn_type);
+#endif
+extern bool ecm_front_end_gre_proto_is_accel_allowed(struct net_device *indev,
+						      struct net_device *outdev,
+						      struct sk_buff *skb,
+						      struct nf_conntrack_tuple *tuple,
+						      int ip_version);
+extern uint64_t ecm_front_end_get_slow_packet_count(struct ecm_front_end_connection_instance *feci);
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+void ecm_front_end_tcp_set_dscp_ext(struct nf_conn *ct,
+					      struct ecm_tracker_ip_header *iph,
+					      struct sk_buff *skb,
+					      ecm_tracker_sender_type_t sender);
+#endif
+void ecm_front_end_fill_ovs_params(struct ecm_front_end_ovs_params ovs_params[],
+					ip_addr_t ip_src_addr, ip_addr_t ip_src_addr_nat,
+					ip_addr_t ip_dest_addr, ip_addr_t ip_dest_addr_nat,
+					int src_port, int src_port_nat,
+					int dest_port, int dest_port_nat, ecm_db_direction_t ecm_dir);
+void ecm_front_end_common_sysctl_register(void);
+void ecm_front_end_common_sysctl_unregister(void);
+int ecm_sfe_sysctl_tbl_init(void);
+void ecm_sfe_sysctl_tbl_exit(void);
+
+#endif  /* __ECM_FRONT_END_COMMON_H */
diff --git a/qca-nss-ecm/frontends/include/ecm_front_end_ipv4.h b/qca-nss-ecm/frontends/include/ecm_front_end_ipv4.h
new file mode 100644
index 0000000..0315701
--- /dev/null
+++ b/qca-nss-ecm/frontends/include/ecm_front_end_ipv4.h
@@ -0,0 +1,76 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2016, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern int ecm_front_end_ipv4_stopped;	/* When non-zero further traffic will not be processed */
+
+#ifdef ECM_MULTICAST_ENABLE
+extern int ecm_front_end_ipv4_mc_stopped;	/* When non-zero further traffic will not be processed */
+#endif
+
+#ifdef ECM_FRONT_END_NSS_ENABLE
+#include "ecm_nss_ipv4.h"
+#else
+static inline int ecm_nss_ipv4_init(struct dentry *dentry)
+{
+	/*
+	 * Just return if nss front end is not enabled
+	 */
+	return 0;
+}
+
+static inline void ecm_nss_ipv4_exit(void)
+{
+	/*
+	 * Just return if nss front end is not enabled
+	 */
+	return;
+}
+#endif
+
+#ifdef ECM_FRONT_END_SFE_ENABLE
+#include "ecm_sfe_ipv4.h"
+#else
+static inline int ecm_sfe_ipv4_init(struct dentry *dentry)
+{
+	/*
+	 * Just return if sfe front end is not enabled
+	 */
+	return 0;
+}
+
+static inline void ecm_sfe_ipv4_exit(void)
+{
+	/*
+	 * Just return if sfe front end is not enabled
+	 */
+	return;
+}
+#endif
+
+/*
+ * IPv4 rule sync reasons.
+ */
+enum ecm_front_end_ipv4_rule_sync_reason {
+	ECM_FRONT_END_IPV4_RULE_SYNC_REASON_STATS = 0,	/* Sync is to synchronize stats */
+	ECM_FRONT_END_IPV4_RULE_SYNC_REASON_FLUSH,	/* Sync is to flush a cache entry */
+	ECM_FRONT_END_IPV4_RULE_SYNC_REASON_EVICT,	/*Sync is to evict a cache entry */
+	ECM_FRONT_END_IPV4_RULE_SYNC_REASON_DESTROY	/* Sync is to destroy a cache entry */
+};
+
+extern void ecm_front_end_ipv4_stop(int num);
+extern int ecm_front_end_ipv4_init(struct dentry *dentry);
+extern void ecm_front_end_ipv4_exit(void);
+
diff --git a/qca-nss-ecm/frontends/include/ecm_front_end_ipv6.h b/qca-nss-ecm/frontends/include/ecm_front_end_ipv6.h
new file mode 100644
index 0000000..d79a16e
--- /dev/null
+++ b/qca-nss-ecm/frontends/include/ecm_front_end_ipv6.h
@@ -0,0 +1,77 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2016, 2020-2021, The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern int ecm_front_end_ipv6_stopped;	/* When non-zero further traffic will not be processed */
+
+#ifdef ECM_MULTICAST_ENABLE
+extern int ecm_front_end_ipv6_mc_stopped;	/* When non-zero further traffic will not be processed */
+#endif
+
+
+#if defined(ECM_FRONT_END_NSS_ENABLE) && defined(ECM_IPV6_ENABLE)
+#include "ecm_nss_ipv6.h"
+#else
+static inline int ecm_nss_ipv6_init(struct dentry *dentry)
+{
+	/*
+	 * Just return if nss front end is not enabled
+	 */
+	return 0;
+}
+
+static inline void ecm_nss_ipv6_exit(void)
+{
+	/*
+	 * Just return if nss front end is not enabled
+	 */
+	return;
+}
+#endif
+
+#ifdef ECM_FRONT_END_SFE_ENABLE
+#include "ecm_sfe_ipv6.h"
+#else
+static inline int ecm_sfe_ipv6_init(struct dentry *dentry)
+{
+	/*
+	 * Just return if sfe front end is not enabled
+	 */
+	return 0;
+}
+
+static inline void ecm_sfe_ipv6_exit(void)
+{
+	/*
+	 * Just return if sfe front end is not enabled
+	 */
+	return;
+}
+#endif
+
+/*
+ * IPv6 rule sync reasons.
+ */
+enum ecm_front_end_ipv6_rule_sync_reason {
+	ECM_FRONT_END_IPV6_RULE_SYNC_REASON_STATS = 0,	/* Sync is to synchronize stats */
+	ECM_FRONT_END_IPV6_RULE_SYNC_REASON_FLUSH,	/* Sync is to flush a cache entry */
+	ECM_FRONT_END_IPV6_RULE_SYNC_REASON_EVICT,	/*Sync is to evict a cache entry */
+	ECM_FRONT_END_IPV6_RULE_SYNC_REASON_DESTROY	/* Sync is to destroy a cache entry */
+};
+
+extern void ecm_front_end_ipv6_stop(int num);
+extern int ecm_front_end_ipv6_init(struct dentry *dentry);
+extern void ecm_front_end_ipv6_exit(void);
+
diff --git a/qca-nss-ecm/frontends/include/ecm_front_end_types.h b/qca-nss-ecm/frontends/include/ecm_front_end_types.h
new file mode 100644
index 0000000..2dcf3c1
--- /dev/null
+++ b/qca-nss-ecm/frontends/include/ecm_front_end_types.h
@@ -0,0 +1,343 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <net/netfilter/nf_conntrack.h>
+
+#include "ecm_ae_classifier_public.h"
+
+/*
+ * Constant used with constructing acceleration rules.
+ */
+#define ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED 0xFFF
+
+/*
+ * Bridge device macros
+ */
+#define ecm_front_end_is_bridge_port(dev) (dev && (dev->priv_flags & IFF_BRIDGE_PORT))
+#define ecm_front_end_is_bridge_device(dev) (dev->priv_flags & IFF_EBRIDGE)
+#define ecm_front_end_is_ovs_bridge_device(dev) (dev->priv_flags & IFF_OPENVSWITCH)
+
+#ifdef ECM_INTERFACE_BOND_ENABLE
+/*
+ * LAN Aggregation device macros
+ */
+#define ecm_front_end_is_lag_master(dev) ((dev->flags & IFF_MASTER)	\
+							 && (dev->priv_flags & IFF_BONDING))
+#define ecm_front_end_is_lag_slave(dev)	((dev->flags & IFF_SLAVE)	\
+							 && (dev->priv_flags & IFF_BONDING))
+#endif
+
+/*
+ * Front end engine types which the frontend
+ * isntance is created for.
+ */
+enum ecm_front_end_engine {
+	ECM_FRONT_END_ENGINE_NSS,
+	ECM_FRONT_END_ENGINE_SFE,
+	ECM_FRONT_END_ENGINE_MAX
+};
+
+/*
+ * ECM kernel module parameter "front_end_selection" is used to determine
+ * which front end should be selected. Its possible values are 0, 1 and 2.
+ * They are mapped to following definition.
+ * ECM_FRONT_END_TYPE_AUTO: select NSS front end if hardware support it,
+ *			    otherwise select SFE front end.
+ * ECM_FRONT_END_TYPE_NSS: select NSS front end if hardware support it,
+ *			   otherwise abort initailization.
+ * ECM_FRONT_END_TYPE_SFE: select SFE front end.
+ * ECM_FRONT_END_TYPE_HYBRID: Both NSS and SFE can be selected.
+ */
+enum ecm_front_end_type {
+	ECM_FRONT_END_TYPE_AUTO,
+	ECM_FRONT_END_TYPE_NSS,
+	ECM_FRONT_END_TYPE_SFE,
+	ECM_FRONT_END_TYPE_HYBRID,
+	ECM_FRONT_END_TYPE_MAX
+};
+
+/*
+ * Features supported in ECM's frontends.
+ */
+enum ecm_fe_feature {
+	ECM_FE_FEATURE_NSS 		= (1 << 0),
+	ECM_FE_FEATURE_SFE 		= (1 << 1),
+	ECM_FE_FEATURE_NON_PORTED 	= (1 << 2),
+	ECM_FE_FEATURE_BRIDGE		= (1 << 3),
+	ECM_FE_FEATURE_MULTICAST	= (1 << 4),
+	ECM_FE_FEATURE_BONDING		= (1 << 5),
+	ECM_FE_FEATURE_IGS		= (1 << 6),
+	ECM_FE_FEATURE_SRC_IF_CHECK	= (1 << 7),
+	ECM_FE_FEATURE_CONN_LIMIT	= (1 << 8),
+	ECM_FE_FEATURE_DSCP_ACTION	= (1 << 9),
+	ECM_FE_FEATURE_XFRM		= (1 << 10),
+	ECM_FE_FEATURE_OVS_BRIDGE		= (1 << 11),
+	ECM_FE_FEATURE_OVS_VLAN		= (1 << 12),
+};
+
+/*
+ * Global variable for the selected front-end type.
+ * It is set once in the module init function.
+ */
+extern enum ecm_front_end_type selected_front_end;
+
+/*
+ * enum ecm_front_end_acceleration_modes
+ *	Acceleration mode of a connection as tracked by the front end.
+ *
+ * Typically when classifiers permit acceleration the front end will then accelerate the connection.
+ * These states indicate the front end record of acceleration mode for the connection.
+ * An acceleration mode less than zero indicates a connection that cannot be accelerated, maybe due to error.
+ */
+enum ecm_front_end_acceleration_modes {
+	ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT_SHORT = -8,/* Acceleration has failed for a short time due to the connection has become defunct and waiting for the removal */
+	ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT = -7,	/* Acceleration has permanently failed due to the connection has become defunct */
+	ECM_FRONT_END_ACCELERATION_MODE_FAIL_DECEL = -6,	/* Acceleration has permanently failed due to deceleration malfunction */
+	ECM_FRONT_END_ACCELERATION_MODE_FAIL_NO_ACTION = -5,	/* Acceleration has permanently failed due to too many offloads that were rejected without any packets being offloaded */
+	ECM_FRONT_END_ACCELERATION_MODE_FAIL_ACCEL_ENGINE = -4,	/* Acceleration has permanently failed due to too many accel engine NAK's */
+	ECM_FRONT_END_ACCELERATION_MODE_FAIL_DRIVER = -3,	/* Acceleration has permanently failed due to too many driver interaction failures */
+	ECM_FRONT_END_ACCELERATION_MODE_FAIL_RULE = -2,		/* Acceleration has permanently failed due to bad rule data */
+	ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED = -1,	/* Acceleration has permanently failed due to can_accel denying accel */
+	ECM_FRONT_END_ACCELERATION_MODE_DECEL = 0,		/* Connection is not accelerated */
+	ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING,		/* Connection is in the process of being accelerated */
+	ECM_FRONT_END_ACCELERATION_MODE_ACCEL,			/* Connection is accelerated */
+	ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING,		/* Connection is in the process of being decelerated */
+};
+typedef enum ecm_front_end_acceleration_modes ecm_front_end_acceleration_mode_t;
+
+#define ECM_FRONT_END_ACCELERATION_NOT_POSSIBLE(accel_mode) ((accel_mode < 0) || (accel_mode == ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING))
+#define ECM_FRONT_END_ACCELERATION_POSSIBLE(accel_mode) (accel_mode >= 0)
+#define ECM_FRONT_END_ACCELERATION_FAILED(accel_mode) (accel_mode < 0)
+
+/*
+ * Front end methods
+ */
+struct ecm_front_end_connection_instance;
+typedef void (*ecm_front_end_connection_accelerate_method_t)(struct ecm_front_end_connection_instance *feci,
+                                                                        struct ecm_classifier_process_response *pr, bool is_l2_encap,
+                                                                        struct nf_conn *ct, struct sk_buff *skb);
+
+typedef bool (*ecm_front_end_connection_decelerate_method_t)(struct ecm_front_end_connection_instance *feci);
+typedef ecm_front_end_acceleration_mode_t (*ecm_front_end_connection_accel_state_get_method_t)(struct ecm_front_end_connection_instance *feci);
+typedef void (*ecm_front_end_connection_ref_method_t)(struct ecm_front_end_connection_instance *feci);
+typedef int (*ecm_front_end_connection_deref_callback_t)(struct ecm_front_end_connection_instance *feci);
+typedef void (*ecm_front_end_connection_action_seen_method_t)(struct ecm_front_end_connection_instance *feci);
+typedef void (*ecm_front_end_connection_accel_ceased_method_t)(struct ecm_front_end_connection_instance *feci);
+#ifdef ECM_STATE_OUTPUT_ENABLE
+typedef int (*ecm_front_end_connection_state_get_callback_t)(struct ecm_front_end_connection_instance *feci, struct ecm_state_file_instance *sfi);
+											/*
+											 * Get state output.  Return 0 on success.
+											 */
+#endif
+typedef int32_t (*ecm_front_end_connection_ae_interface_number_by_dev_get_method_t)(struct net_device *dev);
+typedef int32_t (*ecm_front_end_connection_ae_interface_number_by_dev_type_get_method_t)(struct net_device *dev, uint32_t type);
+typedef int32_t (*ecm_front_end_connection_ae_interface_type_get_method_t)(struct ecm_front_end_connection_instance *feci, struct net_device *dev);
+typedef void (*ecm_front_end_connection_regenerate_method_t)(struct ecm_front_end_connection_instance *feci, struct ecm_db_connection_instance *ci);
+typedef void (*ecm_front_end_connection_multicast_update_method_t)(ip_addr_t ip_grp_addr, struct net_device *brdev);
+
+typedef void (*ecm_front_end_connection_set_stats_bitmap_t)(struct ecm_front_end_connection_instance *feci, ecm_db_obj_dir_t dir, uint8_t bit);
+typedef uint32_t (*ecm_front_end_connection_get_stats_bitmap_t)(struct ecm_front_end_connection_instance *feci, ecm_db_obj_dir_t dir);
+typedef void (*ecm_front_end_connection_update_rule_t)(struct ecm_front_end_connection_instance *feci, enum ecm_rule_update_type type, void *arg);
+
+/*
+ * Acceleration limiting modes.
+ *	Used to apply limiting to accelerated connections.
+ */
+#define ECM_FRONT_END_ACCEL_LIMIT_MODE_UNLIMITED 0x00	/* No limits on acceleration rule creation */
+#define ECM_FRONT_END_ACCEL_LIMIT_MODE_FIXED 0x01	/* Fixed upper limit for connection acceleration based on information from driver */
+
+/*
+ * Accel/decel mode statistics data structure.
+ */
+struct ecm_front_end_connection_mode_stats {
+	bool decelerate_pending;		/* Decel was attempted during pending accel - will be actioned when accel is done */
+	bool flush_happened;			/* A flush message was received from accel engine before we received an ACK or NACK. (Accel engine Messaging sequence/ordering workaround) */
+	uint32_t flush_happened_total;		/* Total of times we see flush_happened */
+	uint32_t no_action_seen_total;		/* Total of times acceleration was ended by the accel engine itself without any offload action */
+	uint32_t no_action_seen;		/* Count of times consecutive  acceleration was ended by the accel engine itself without any offload action */
+	uint32_t no_action_seen_limit;		/* Limit on consecutive no-action at which point offload permanently fails out */
+	uint32_t driver_fail_total;		/* Total times driver failed to send our command */
+	uint32_t driver_fail;			/* Count of consecutive times driver failed to send our command, when this reaches driver_fail_limit acceleration will permanently fail */
+	uint32_t driver_fail_limit;		/* Limit on drivers consecutive fails at which point offload permanently fails out */
+	uint32_t ae_nack_total;		/* Total times accel engine NAK's an accel command */
+	uint32_t ae_nack;			/* Count of consecutive times driver failed to ack */
+	uint32_t ae_nack_limit;		/* Limit on consecutive nacks at which point offload permanently fails out */
+	uint64_t slow_path_packets;		/* The number of slow packets before the acceleration starts */
+	unsigned long cmd_time_begun;		/* Time captured when an accel or decel request begun */
+	unsigned long cmd_time_completed;	/* Time captured when request finished */
+};
+
+/*
+ * Connection front end instance
+ *	Each new connection requires it to also have one of these to maintain front end specific information and operations
+ */
+struct ecm_front_end_connection_instance {
+	ecm_front_end_connection_ref_method_t ref;				/* Ref the instance */
+	ecm_front_end_connection_deref_callback_t deref;			/* Deref the instance */
+	ecm_front_end_connection_accelerate_method_t accelerate;		/* accelerate a connection */
+	ecm_front_end_connection_decelerate_method_t decelerate;		/* Decelerate a connection */
+	ecm_front_end_connection_accel_state_get_method_t accel_state_get;	/* Get the acceleration state */
+	ecm_front_end_connection_action_seen_method_t action_seen;		/* Acceleration action has occurred */
+	ecm_front_end_connection_accel_ceased_method_t accel_ceased;		/* Acceleration has stopped */
+	ecm_front_end_connection_ae_interface_number_by_dev_get_method_t ae_interface_number_by_dev_get;
+										/* Get the acceleration engine interface number from the dev instance */
+	ecm_front_end_connection_ae_interface_number_by_dev_type_get_method_t ae_interface_number_by_dev_type_get;
+										/* Get the acceleration engine interface number from the dev instance and type */
+	ecm_front_end_connection_ae_interface_type_get_method_t ae_interface_type_get;
+										/* Get the acceleration engine interface type */
+	ecm_front_end_connection_regenerate_method_t regenerate;
+										/* regenerate a connection */
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	ecm_front_end_connection_state_get_callback_t state_get;		/* Obtain state for this object */
+#endif
+	ecm_front_end_connection_multicast_update_method_t multicast_update;	/* Update existing multicast connection */
+
+	ecm_front_end_connection_set_stats_bitmap_t set_stats_bitmap;		/* Set bitmap of interface types to be updated during sync */
+	ecm_front_end_connection_get_stats_bitmap_t get_stats_bitmap;		/* Get bitmap of interface types to be updated during sync */
+	ecm_front_end_connection_update_rule_t update_rule;			/* Updates the frontend specific data */
+
+	enum ecm_front_end_engine accel_engine;	/* Acceleration engine type */
+
+	/*
+	 * Accel/decel mode statistics.
+	 */
+	struct ecm_front_end_connection_mode_stats stats;
+
+	/*
+	 * Common control items to all front end instances
+	 */
+	int ip_version;						/* RO: The version of IP protocol this instance was established for */
+	int protocol;						/* RO: The protocol this instance was established for */
+	struct ecm_db_connection_instance *ci;			/* RO: The connection instance relating to this instance. */
+	bool can_accel;						/* RO: True when the connection can be accelerated */
+	bool is_defunct;					/* True if the connection has become defunct */
+	bool destroy_fail_handle_pending;			/* Set while handling the connection destroy failure */
+	ecm_front_end_acceleration_mode_t accel_mode;		/* Indicates the type of acceleration being applied to a connection, if any. */
+	spinlock_t lock;					/* Lock for structure data */
+	int refs;						/* Integer to trap we never go negative */
+
+};
+
+/*
+ * Front end's interface construction structure.
+ */
+struct ecm_front_end_interface_construct_instance {
+	struct net_device *from_dev;
+	struct net_device *from_other_dev;
+	struct net_device *to_dev;
+	struct net_device *to_other_dev;
+	struct net_device *from_nat_dev;
+	struct net_device *from_nat_other_dev;
+	struct net_device *to_nat_dev;
+	struct net_device *to_nat_other_dev;
+
+	ip_addr_t from_mac_lookup_ip_addr;
+	ip_addr_t to_mac_lookup_ip_addr;
+	ip_addr_t from_nat_mac_lookup_ip_addr;
+	ip_addr_t to_nat_mac_lookup_ip_addr;
+};
+
+struct ecm_front_end_ovs_params {
+	ip_addr_t src_ip;
+	ip_addr_t dest_ip;
+	int src_port;
+	int dest_port;
+};
+
+extern void ecm_front_end_ipv6_interface_construct_netdev_put(struct ecm_front_end_interface_construct_instance *efeici);
+extern void ecm_front_end_ipv6_interface_construct_netdev_hold(struct ecm_front_end_interface_construct_instance *efeici);
+extern bool ecm_front_end_ipv6_interface_construct_set_and_hold(struct sk_buff *skb, ecm_tracker_sender_type_t sender, ecm_db_direction_t ecm_dir, bool is_routed,
+							struct net_device *in_dev, struct net_device *out_dev,
+							ip_addr_t ip_src_addr, ip_addr_t ip_dest_addr,
+							struct ecm_front_end_interface_construct_instance *efeici);
+
+extern void ecm_front_end_ipv4_interface_construct_netdev_put(struct ecm_front_end_interface_construct_instance *efeici);
+extern void ecm_front_end_ipv4_interface_construct_netdev_hold(struct ecm_front_end_interface_construct_instance *efeici);
+extern bool ecm_front_end_ipv4_interface_construct_set_and_hold(struct sk_buff *skb, ecm_tracker_sender_type_t sender, ecm_db_direction_t ecm_dir, bool is_routed,
+							struct net_device *in_dev, struct net_device *out_dev,
+							ip_addr_t ip_src_addr, ip_addr_t ip_src_addr_nat,
+							ip_addr_t ip_dest_addr, ip_addr_t ip_dest_addr_nat,
+							struct ecm_front_end_interface_construct_instance *efeici);
+void ecm_front_end_ipv4_fill_ovs_params(struct ecm_front_end_ovs_params ovs_params[], ip_addr_t ip_src_addr, ip_addr_t ip_src_addr_nat, ip_addr_t ip_dest_addr,
+					ip_addr_t ip_dest_addr_nat, int src_port, int src_port_nat, int dest_port, int dest_port_nat);
+
+bool ecm_front_end_is_feature_supported(enum ecm_fe_feature feature);
+
+/*
+ * ecm_front_end_type_get()
+ *	Returns the selcted fornt-end type.
+ */
+static inline enum ecm_front_end_type ecm_front_end_type_get(void)
+{
+	return selected_front_end;
+}
+
+/*
+ * ecm_front_end_type_select()
+ * 	Detects and sets which front end to run
+ *
+ * User can select front end explicitly by passing 1(nss) or 2(sfe)
+ * to kernel module parameter "front_end_selection". Or let ECM make
+ * the decision by passing 0(auto). "auto" is also the default mode if
+ * user didn't specify parameter "front_end_selection".
+ *
+ * In automatic selection mode, we prefer to select NSS front end if
+ * hardware support it, then SFE front end.
+ *
+ * We check device tree to see if NSS is supported by hardware.
+ * Currenly all ipq8064, ipq8062 and ipq807x  ipq60xx platforms support NSS.
+ * Since SFE is a pure software acceleration engine, so all platforms
+ * support it.
+ */
+static inline enum ecm_front_end_type ecm_front_end_type_select(void)
+{
+	bool nss_supported = false;
+	extern int front_end_selection;
+
+#ifdef ECM_FRONT_END_NSS_ENABLE
+#ifdef CONFIG_OF
+	nss_supported = of_machine_is_compatible("qcom,ipq8064") ||
+				of_machine_is_compatible("qcom,ipq8062") ||
+				of_machine_is_compatible("qcom,ipq807x") ||
+				of_machine_is_compatible("qcom,ipq8074") ||
+				of_machine_is_compatible("qcom,ipq6018") ||
+				of_machine_is_compatible("qcom,ipq5018");
+#else
+	nss_supported = true;
+#endif
+#endif
+
+	if (nss_supported && ((front_end_selection == ECM_FRONT_END_TYPE_AUTO) ||
+			      (front_end_selection == ECM_FRONT_END_TYPE_NSS))) {
+		return ECM_FRONT_END_TYPE_NSS;
+	}
+
+	if ((front_end_selection == ECM_FRONT_END_TYPE_AUTO) ||
+	    (front_end_selection == ECM_FRONT_END_TYPE_SFE)) {
+		return ECM_FRONT_END_TYPE_SFE;
+	}
+
+	if (nss_supported && (front_end_selection == ECM_FRONT_END_TYPE_HYBRID)) {
+		return ECM_FRONT_END_TYPE_HYBRID;
+	}
+
+	return ECM_FRONT_END_TYPE_MAX;
+}
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_common.c b/qca-nss-ecm/frontends/nss/ecm_nss_common.c
new file mode 100644
index 0000000..cd3dd5b
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_common.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/inet.h>
+#include <linux/etherdevice.h>
+
+#define DEBUG_LEVEL ECM_NSS_COMMON_DEBUG_LEVEL
+
+#include <nss_api_if.h>
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_interface.h"
+#include "ecm_nss_common.h"
+#include "ecm_front_end_common.h"
+#include "ecm_nss_ipv6.h"
+#include "ecm_nss_ipv4.h"
+
+#ifdef ECM_IPV6_ENABLE
+/*
+ * ecm_nss_ipv6_is_conn_limit_reached()
+ *	Connection limit is reached or not ?
+ */
+bool ecm_nss_ipv6_is_conn_limit_reached(void)
+{
+
+#if !defined(ECM_FRONT_END_CONN_LIMIT_ENABLE)
+	return false;
+#endif
+
+	if (likely(!((ecm_front_end_is_feature_supported(ECM_FE_FEATURE_CONN_LIMIT)) && ecm_front_end_conn_limit))) {
+		return false;
+	}
+
+	if (ecm_nss_ipv6_accelerated_count == nss_ipv6_max_conn_count()) {
+		DEBUG_INFO("ECM DB connection limit %d reached, for NSS frontend \
+			   new flows cannot be accelerated.\n",
+			   ecm_nss_ipv6_accelerated_count);
+		return true;
+	}
+
+	return false;
+}
+#endif
+
+/*
+ * ecm_nss_ipv4_is_conn_limit_reached()
+ *	Connection limit is reached or not ?
+ */
+bool ecm_nss_ipv4_is_conn_limit_reached(void)
+{
+
+#if !defined(ECM_FRONT_END_CONN_LIMIT_ENABLE)
+	return false;
+#endif
+
+	if (likely(!((ecm_front_end_is_feature_supported(ECM_FE_FEATURE_CONN_LIMIT)) && ecm_front_end_conn_limit))) {
+		return false;
+	}
+
+	if (ecm_nss_ipv4_accelerated_count == nss_ipv4_max_conn_count()) {
+		DEBUG_INFO("ECM DB connection limit %d reached, for NSS frontend \
+			   new flows cannot be accelerated.\n",
+			   ecm_nss_ipv4_accelerated_count);
+		return true;
+	}
+
+	return false;
+}
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_common.h b/qca-nss-ecm/frontends/nss/ecm_nss_common.h
new file mode 100644
index 0000000..3f3dda2
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_common.h
@@ -0,0 +1,483 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2018-2021, The Linux Foundation.  All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+#include <nat46-core.h>
+#endif
+
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+#ifdef ECM_INTERFACE_IPSEC_GLUE_LAYER_SUPPORT_ENABLE
+#include "nss_ipsec_cmn.h"
+#else
+#include "nss_ipsec.h"
+#endif
+#endif
+
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+#include <net/vxlan.h>
+#endif
+
+#include <net/xfrm.h>
+
+/*
+ * This macro converts ECM ip_addr_t to NSS IPv6 address
+ */
+#define ECM_IP_ADDR_TO_NSS_IPV6_ADDR(nss6, ipaddrt) \
+	{ \
+		ecm_type_check_ae_ipv6(nss6); \
+		ecm_type_check_ecm_ip_addr(ipaddrt); \
+		nss6[0] = ipaddrt[3]; \
+		nss6[1] = ipaddrt[2]; \
+		nss6[2] = ipaddrt[1]; \
+		nss6[3] = ipaddrt[0]; \
+	}
+
+/*
+ * This macro converts NSS IPv6 address to ECM ip_addr_t
+ */
+#define ECM_NSS_IPV6_ADDR_TO_IP_ADDR(ipaddrt, nss6) \
+	{ \
+		ecm_type_check_ecm_ip_addr(ipaddrt); \
+		ecm_type_check_ae_ipv6(nss6); \
+		ipaddrt[0] = nss6[3]; \
+		ipaddrt[1] = nss6[2]; \
+		ipaddrt[2] = nss6[1]; \
+		ipaddrt[3] = nss6[0]; \
+	}
+
+/*
+ * ecm_nss_common_get_interface_number_by_dev()
+ *	Returns the acceleration engine interface number based on the net_device object.
+ */
+static inline int32_t ecm_nss_common_get_interface_number_by_dev(struct net_device *dev)
+{
+	/*
+	 * nss_interface_num for all IPsec tunnels will always be the one specific to acceleration engine.
+	 */
+	if (dev->type == ECM_ARPHRD_IPSEC_TUNNEL_TYPE) {
+		return NSS_IPSEC_CMN_INTERFACE;
+	}
+
+#ifdef ECM_INTERFACE_RAWIP_ENABLE
+	if (dev->type == ARPHRD_RAWIP) {
+		return nss_rmnet_rx_get_ifnum(dev);
+	}
+#endif
+
+	return nss_cmn_get_interface_number_by_dev(dev);
+}
+
+/*
+ * ecm_nss_common_get_interface_number_by_dev_type()
+ *	Returns the acceleration engine interface number based on the net_device object and type.
+ */
+static inline int32_t ecm_nss_common_get_interface_number_by_dev_type(struct net_device *dev, uint32_t type)
+{
+	/*
+	 * nss_interface_num for all IPsec tunnels will always be the one specific to acceleration engine.
+	 */
+	if ((dev->type == ECM_ARPHRD_IPSEC_TUNNEL_TYPE) && !type) {
+		return NSS_IPSEC_CMN_INTERFACE;
+	}
+
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+	/*
+	 * Find VxLAN dev type based on type, 0 for outer & 1 for inner.
+	 */
+	if (netif_is_vxlan(dev)) {
+		if (!type) {
+			return NSS_VXLAN_INTERFACE;
+		}
+		type = NSS_DYNAMIC_INTERFACE_TYPE_VXLAN_INNER;
+	}
+#endif
+
+	return nss_cmn_get_interface_number_by_dev_and_type(dev, type);
+}
+
+/*
+ * ecm_nss_common_connection_regenerate()
+ *	Re-generate a specific connection in NSS front end
+ */
+static inline void ecm_nss_common_connection_regenerate(struct ecm_front_end_connection_instance *feci, struct ecm_db_connection_instance *ci)
+{
+	/*
+	 * Flag the connection as needing re-generation.
+	 * Re-generation occurs when we next see traffic OR an acceleration engine sync for this connection.
+	 * Refer to front end protocol specific process() functions.
+	 */
+	ecm_db_connection_regeneration_needed(ci);
+}
+
+/*
+ * ecm_nss_common_get_interface_type()
+ *	Gets the NSS interface type based on some features.
+ *
+ * TODO: For now the feature is the IP version and the net device type. It can be changed
+ * in the future for other needs.
+ */
+static inline int32_t ecm_nss_common_get_interface_type(struct ecm_front_end_connection_instance *feci, struct net_device *dev)
+{
+	switch (dev->type) {
+	case ARPHRD_SIT:
+#ifdef ECM_INTERFACE_SIT_ENABLE
+		if (feci->ip_version == 4) {
+			return NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_OUTER;
+		}
+
+		if (feci->ip_version == 6) {
+			return NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_INNER;
+		}
+#endif
+		break;
+
+#ifdef ECM_INTERFACE_TUNIPIP6_ENABLE
+	case ARPHRD_TUNNEL6:
+		if (feci->ip_version == 4) {
+			return NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_INNER;
+		}
+
+		if (feci->ip_version == 6) {
+			return NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_OUTER;
+		}
+#endif
+		break;
+
+#ifdef ECM_INTERFACE_GRE_TAP_ENABLE
+	case ARPHRD_ETHER:
+		/*
+		 * If device is not GRETAP then return NONE.
+		 */
+		if (!(dev->priv_flags_ext & (IFF_EXT_GRE_V4_TAP | IFF_EXT_GRE_V6_TAP))) {
+			break;
+		}
+#if __has_attribute(__fallthrough__)
+		__attribute__((__fallthrough__));
+#endif
+#endif
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+	case ARPHRD_IPGRE:
+	case ARPHRD_IP6GRE:
+#endif
+#if defined(ECM_INTERFACE_GRE_TAP_ENABLE) || defined(ECM_INTERFACE_GRE_TUN_ENABLE)
+		if (feci->protocol == IPPROTO_GRE) {
+			return NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER;
+		}
+
+		return NSS_DYNAMIC_INTERFACE_TYPE_GRE_INNER;
+#endif
+	case ARPHRD_NONE:
+#ifdef ECM_INTERFACE_MAP_T_ENABLE
+		if (is_map_t_dev(dev)) {
+			if (feci->ip_version == 4) {
+				return NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_INNER;
+			}
+
+			if (feci->ip_version == 6) {
+				return NSS_DYNAMIC_INTERFACE_TYPE_MAP_T_OUTER;
+			}
+		}
+#endif
+		break;
+	case ARPHRD_PPP:
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+		if (dev->priv_flags_ext & IFF_EXT_PPP_PPTP) {
+			if (feci->protocol == IPPROTO_GRE) {
+				return NSS_DYNAMIC_INTERFACE_TYPE_PPTP_OUTER;
+			}
+
+			return NSS_DYNAMIC_INTERFACE_TYPE_PPTP_INNER;
+		}
+#endif
+		break;
+	default:
+		break;
+	}
+
+	/*
+	 * By default.
+	 */
+	return NSS_DYNAMIC_INTERFACE_TYPE_NONE;
+}
+
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+/*
+ * ecm_nss_common_ipsec_get_ifnum()
+ *     Get ipsec specific interface number appended with coreid
+ */
+static inline int32_t ecm_nss_common_ipsec_get_ifnum(int32_t ifnum)
+{
+#ifdef ECM_INTERFACE_IPSEC_GLUE_LAYER_SUPPORT_ENABLE
+	return nss_ipsec_cmn_get_ifnum_with_coreid(ifnum);
+#else
+	return nss_ipsec_get_ifnum(ifnum);
+#endif
+}
+#endif
+
+#if defined(CONFIG_NET_CLS_ACT) && defined(ECM_CLASSIFIER_DSCP_IGS)
+/*
+ * ecm_nss_common_igs_acceleration_is_allowed()
+ *	Return true, if flow acceleration is allowed for an IGS interface.
+ */
+static inline bool ecm_nss_common_igs_acceleration_is_allowed(struct ecm_front_end_connection_instance *feci,
+		struct sk_buff *skb)
+{
+	struct net_device *to_dev;
+	struct ecm_db_iface_instance *to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	enum ip_conntrack_info ctinfo;
+	int to_ifaces_first;
+	uint32_t list_index;
+	bool do_accel = true;
+
+	/*
+	 * Get the interface lists of the connection and check if any interface in the list
+	 * has ingress qdisc attached to it.
+	 */
+	to_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, to_ifaces, ECM_DB_OBJ_DIR_TO);
+	if (to_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in to_interfaces list!\n", feci);
+		return false;
+	}
+
+	/*
+	 * Reject the flow acceleration if the egress device has ingress qdisc
+	 * attached to it. At these interfaces, the acceleration is only allowed
+	 * when any packet is recieved over them (so that we can able to get the
+	 * correct ingress qostag values from it and fill them in the acceleration rules).
+	 */
+	for (list_index = to_ifaces_first; list_index < ECM_DB_IFACE_HEIRARCHY_MAX; list_index++) {
+		struct ecm_db_iface_instance *ii;
+
+		ii = to_ifaces[list_index];
+		to_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+		if (unlikely(!to_dev)) {
+			DEBUG_TRACE("%px: No valid device found for %d index.\n",
+					feci, ecm_db_iface_interface_identifier_get(ii));
+			continue;
+		}
+
+		/*
+		 * Check whether ingress qdisc is attached to the egress device or not.
+		 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0))
+		if (likely(!(to_dev->ingress_cl_list))) {
+#else
+		if (likely(!(to_dev->miniq_ingress))) {
+#endif
+			dev_put(to_dev);
+			continue;
+		}
+
+		/*
+		 * Reject the connection if both side packets are not yet seen.
+		 */
+		nf_ct_get(skb, &ctinfo);
+		if ((ctinfo != IP_CT_ESTABLISHED) &&
+				(ctinfo != IP_CT_ESTABLISHED_REPLY)) {
+			DEBUG_INFO("%px: New flow at ingress device, "
+					"rejecting the acceleration.\n", feci);
+
+			/*
+			 * Deny the acceleration as both side packets are not yet seen.
+			 */
+			do_accel = false;
+		}
+		dev_put(to_dev);
+		break;
+	}
+
+	/*
+	 * Release the resources.
+	 */
+	ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+	return do_accel;
+}
+#endif
+
+/*
+ * ecm_nss_common_is_xfrm_flow()
+ *	Check if the flow is an xfrm flow.
+ */
+static inline bool ecm_nss_common_is_xfrm_flow(struct sk_buff *skb, struct ecm_tracker_ip_header *ip_hdr)
+{
+#ifdef CONFIG_XFRM
+	struct dst_entry *dst;
+	struct net *net;
+
+	net = dev_net(skb->dev);
+	if (likely(!net->xfrm.policy_count[XFRM_POLICY_OUT])) {
+		return false;
+	}
+
+	/*
+	 * Packet seen after output transformation. We use the IPCB(skb) to check
+	 * for this condition. No custom code should mangle the IPCB: skb->cb area,
+	 * while the packet is traversing through the INET layer.
+	 */
+	if (ip_hdr->is_v4) {
+		if ((IPCB(skb)->flags & IPSKB_XFRM_TRANSFORMED)) {
+			DEBUG_TRACE("%px: Packet has undergone xfrm transformation\n", skb);
+			return true;
+		}
+	} else if (IP6CB(skb)->flags & IP6SKB_XFRM_TRANSFORMED) {
+		DEBUG_TRACE("%px: Packet has undergone xfrm transformation\n", skb);
+		return true;
+	}
+
+	if (ip_hdr->protocol == IPPROTO_ESP) {
+		DEBUG_TRACE("%px: ESP Passthrough packet\n", skb);
+		return false;
+	}
+
+	/*
+	 * skb's sp is set for decapsulated packet
+	 */
+	if (secpath_exists(skb)) {
+		DEBUG_TRACE("%px: Packet has undergone xfrm decapsulation((%d)\n", skb, ip_hdr->protocol);
+		return true;
+	}
+
+	/*
+	 * dst->xfrm is valid for lan to wan plain packet
+	 */
+	dst = skb_dst(skb);
+	if (dst && dst->xfrm) {
+		DEBUG_TRACE("%px: Plain text packet destined for xfrm(%d)\n", skb, ip_hdr->protocol);
+		return true;
+	}
+#endif
+	return false;
+}
+
+#ifdef ECM_CLASSIFIER_PCC_ENABLE
+/*
+ * ecm_nss_common_fill_mirror_info()
+ *	Fill Mirror information.
+ */
+static inline bool ecm_nss_common_fill_mirror_info(struct ecm_classifier_process_response *pr,
+		nss_if_num_t *flow_mirror_ifnum, nss_if_num_t *return_mirror_ifnum)
+{
+	struct net_device *mirror_dev;
+
+	/*
+	 * Initialize both mirror interfaces to invalid.
+	 */
+	*flow_mirror_ifnum = -1;
+	*return_mirror_ifnum = -1;
+
+	if (pr->flow_mirror_ifindex > 0) {
+		mirror_dev = dev_get_by_index(&init_net, pr->flow_mirror_ifindex);
+		if (!mirror_dev) {
+			DEBUG_ERROR("Invalid mirror flow index number: %d\n", pr->flow_mirror_ifindex);
+			return false;
+		}
+
+		*flow_mirror_ifnum = ecm_nss_common_get_interface_number_by_dev_type(mirror_dev,
+				NSS_DYNAMIC_INTERFACE_TYPE_MIRROR);
+		if (*flow_mirror_ifnum < 0) {
+			DEBUG_ERROR("Invalid mirror interface: %s\n", mirror_dev->name);
+			dev_put(mirror_dev);
+			return false;
+		}
+		dev_put(mirror_dev);
+	}
+
+	if (pr->return_mirror_ifindex > 0) {
+		mirror_dev = dev_get_by_index(&init_net, pr->return_mirror_ifindex);
+		if (!mirror_dev) {
+			DEBUG_ERROR("Invalid mirror return index number: %d\n", pr->return_mirror_ifindex);
+			return false;
+		}
+
+		*return_mirror_ifnum = ecm_nss_common_get_interface_number_by_dev_type(mirror_dev,
+				NSS_DYNAMIC_INTERFACE_TYPE_MIRROR);
+		if (*return_mirror_ifnum < 0) {
+			DEBUG_ERROR("Invalid mirror interface: %s\n", mirror_dev->name);
+			dev_put(mirror_dev);
+			return false;
+		}
+		dev_put(mirror_dev);
+	}
+
+	return true;
+}
+#endif
+
+bool ecm_nss_ipv6_is_conn_limit_reached(void);
+bool ecm_nss_ipv4_is_conn_limit_reached(void);
+
+/*
+ * ecm_nss_feature_check()
+ *	Check some specific features for NSS acceleration
+ */
+static inline bool ecm_nss_feature_check(struct sk_buff *skb, struct ecm_tracker_ip_header *ip_hdr)
+{
+	/*
+	 * If the DSCP value of the packet maps to the NOT accel action type,
+	 * do not accelerate the packet and let it go through the
+	 * slow path.
+	 */
+	if (ip_hdr->protocol == IPPROTO_UDP) {
+		uint8_t action = ip_hdr->is_v4 ?
+			nss_ipv4_dscp_action_get(ip_hdr->dscp) : nss_ipv6_dscp_action_get(ip_hdr->dscp);
+		if (action == NSS_IPV4_DSCP_MAP_ACTION_DONT_ACCEL || action == NSS_IPV6_DSCP_MAP_ACTION_DONT_ACCEL) {
+			DEBUG_TRACE("%px: dscp: %d maps to action not accel type, skip acceleration\n", skb, ip_hdr->dscp);
+			return false;
+		}
+	}
+
+	if (ecm_nss_common_is_xfrm_flow(skb, ip_hdr)) {
+#ifdef ECM_XFRM_ENABLE
+		struct net_device *ipsec_dev;
+		int32_t interface_type;
+
+		/*
+		* Check if the transformation for this flow
+		 * is done by NSS. If yes, then only try to accelerate.
+		 */
+		ipsec_dev = ecm_interface_get_and_hold_ipsec_tun_netdev(NULL, skb, &interface_type);
+		if (!ipsec_dev) {
+			DEBUG_TRACE("%px xfrm flow not managed by NSS; skip it\n", skb);
+			return false;
+		}
+		dev_put(ipsec_dev);
+#else
+		DEBUG_TRACE("%px xfrm flow, but accel is disabled; skip it\n", skb);
+		return false;
+#endif
+	}
+
+	return true;
+}
+
+/*
+ * ecm_nss_common_dummy_get_stats_bitmap()
+ */
+static inline uint32_t ecm_nss_common_dummy_get_stats_bitmap(struct ecm_front_end_connection_instance *feci, ecm_db_obj_dir_t dir)
+{
+	return 0;
+}
+
+/*
+ * ecm_nss_common_dummy_set_stats_bitmap()
+ */
+static inline void ecm_nss_common_dummy_set_stats_bitmap(struct ecm_front_end_connection_instance *feci, ecm_db_obj_dir_t dir, uint8_t bit)
+{
+
+}
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_ipv4.c b/qca-nss-ecm/frontends/nss/ecm_nss_ipv4.c
new file mode 100644
index 0000000..0fee3e8
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_ipv4.c
@@ -0,0 +1,1160 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <net/addrconf.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/ppp_defs.h>
+#include <linux/mroute.h>
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+#include <net/vxlan.h>
+#endif
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <linux/netfilter/nf_conntrack_zones_common.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/nf_conntrack_timeout.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_IPV4_DEBUG_LEVEL
+
+#include <nss_api_if.h>
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+#include "ecm_classifier_nl.h"
+#endif
+#include "ecm_interface.h"
+#include "ecm_nss_ported_ipv4.h"
+#ifdef ECM_MULTICAST_ENABLE
+#include "ecm_nss_multicast_ipv4.h"
+#endif
+#ifdef ECM_NON_PORTED_SUPPORT_ENABLE
+#include "ecm_nss_non_ported_ipv4.h"
+#endif
+#include "ecm_nss_common.h"
+#include "ecm_front_end_common.h"
+#include "ecm_front_end_ipv4.h"
+#include "ecm_ipv4.h"
+
+#define ECM_NSS_IPV4_STATS_SYNC_PERIOD msecs_to_jiffies(1000)
+#define ECM_NSS_IPV4_STATS_SYNC_UDELAY 4000	/* Delay for 4 ms */
+
+int ecm_nss_ipv4_no_action_limit_default = 250;		/* Default no-action limit. */
+int ecm_nss_ipv4_driver_fail_limit_default = 250;		/* Default driver fail limit. */
+int ecm_nss_ipv4_nack_limit_default = 250;			/* Default nack limit. */
+int ecm_nss_ipv4_accelerated_count = 0;			/* Total offloads */
+int ecm_nss_ipv4_pending_accel_count = 0;			/* Total pending offloads issued to the NSS / awaiting completion */
+int ecm_nss_ipv4_pending_decel_count = 0;			/* Total pending deceleration requests issued to the NSS / awaiting completion */
+int ecm_nss_ipv4_vlan_passthrough_enable = 0;		/* VLAN passthrough feature enable or disable flag */
+
+/*
+ * Limiting the acceleration of connections.
+ *
+ * By default there is no acceleration limiting.
+ * This means that when ECM has more connections (that can be accelerated) than the acceleration
+ * engine will allow the ECM will continue to try to accelerate.
+ * In this scenario the acceleration engine will begin removal of existing rules to make way for new ones.
+ * When the accel_limit_mode is set to FIXED ECM will not permit more rules to be issued than the engine will allow.
+ */
+uint32_t ecm_nss_ipv4_accel_limit_mode = ECM_FRONT_END_ACCEL_LIMIT_MODE_UNLIMITED;
+
+/*
+ * Locking of the classifier - concurrency control for file global parameters.
+ * NOTE: It is safe to take this lock WHILE HOLDING a feci->lock.  The reverse is NOT SAFE.
+ */
+DEFINE_SPINLOCK(ecm_nss_ipv4_lock);			/* Protect against SMP access between netfilter, events and private threaded function. */
+
+/*
+ * NSS driver linkage
+ */
+struct nss_ctx_instance *ecm_nss_ipv4_nss_ipv4_mgr = NULL;
+
+static unsigned long ecm_nss_ipv4_accel_cmd_time_avg_samples = 0;	/* Sum of time taken for the set of accel command samples, used to compute average time for an accel command to complete */
+static unsigned long ecm_nss_ipv4_accel_cmd_time_avg_set = 1;	/* How many samples in the set */
+static unsigned long ecm_nss_ipv4_decel_cmd_time_avg_samples = 0;	/* Sum of time taken for the set of accel command samples, used to compute average time for an accel command to complete */
+static unsigned long ecm_nss_ipv4_decel_cmd_time_avg_set = 1;	/* How many samples in the set */
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_nss_ipv4_dentry;
+
+/*
+ * Workqueue for the connection sync
+ */
+struct workqueue_struct *ecm_nss_ipv4_workqueue;
+struct delayed_work ecm_nss_ipv4_work;
+struct nss_ipv4_msg *ecm_nss_ipv4_sync_req_msg;
+static unsigned long int ecm_nss_ipv4_next_req_time;
+static unsigned long int ecm_nss_ipv4_roll_check_jiffies;
+static unsigned long int ecm_nss_ipv4_stats_request_success = 0;	/* Number of success stats request */
+static unsigned long int ecm_nss_ipv4_stats_request_fail = 0;		/* Number of failed stats request */
+static unsigned long int ecm_nss_ipv4_stats_request_nack = 0;		/* Number of NACK'd stats request */
+
+/*
+ * ecm_nss_ipv4_accel_done_time_update()
+ *	Record how long the command took to complete, updating average samples
+ */
+void ecm_nss_ipv4_accel_done_time_update(struct ecm_front_end_connection_instance *feci)
+{
+	unsigned long delta;
+
+	/*
+	 * How long did it take the command to complete?
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_completed = jiffies;
+	delta = feci->stats.cmd_time_completed - feci->stats.cmd_time_begun;
+	spin_unlock_bh(&feci->lock);
+
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_ipv4_accel_cmd_time_avg_samples += delta;
+	ecm_nss_ipv4_accel_cmd_time_avg_set++;
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+}
+
+/*
+ * ecm_nss_ipv4_deccel_done_time_update()
+ *	Record how long the command took to complete, updating average samples
+ */
+void ecm_nss_ipv4_decel_done_time_update(struct ecm_front_end_connection_instance *feci)
+{
+	unsigned long delta;
+
+	/*
+	 * How long did it take the command to complete?
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_completed = jiffies;
+	delta = feci->stats.cmd_time_completed - feci->stats.cmd_time_begun;
+	spin_unlock_bh(&feci->lock);
+
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_ipv4_decel_cmd_time_avg_samples += delta;
+	ecm_nss_ipv4_decel_cmd_time_avg_set++;
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+}
+
+/*
+ * ecm_nss_ipv4_process_one_conn_sync_msg()
+ *	Process one connection sync message.
+ */
+static inline void ecm_nss_ipv4_process_one_conn_sync_msg(struct nss_ipv4_conn_sync *sync)
+{
+	struct nf_conntrack_tuple_hash *h;
+	struct nf_conntrack_tuple tuple;
+	struct nf_conn *ct;
+	struct nf_conn_counter *acct;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct neighbour *neigh;
+	ip_addr_t flow_ip;
+	ip_addr_t return_ip_xlate;
+	ip_addr_t return_ip;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	int flow_ident;
+	int return_ident_xlate;
+	struct ecm_classifier_rule_sync class_sync;
+	int flow_dir;
+	int return_dir;
+	unsigned long int delta_jiffies;
+	int elapsed;
+
+	/*
+	 * Look up ecm connection with a view to synchronising the connection, classifier and data tracker.
+	 * Note that we use _xlate versions for destination - for egressing connections this would be the wan IP address,
+	 * but for ingressing this would be the LAN side (non-nat'ed) address and is what we need for lookup of our connection.
+	 */
+	DEBUG_INFO("%px: NSS Sync, lookup connection using\n"
+			"Protocol: %d\n" \
+			"src_addr: %pI4h:%d\n" \
+			"dest_addr: %pI4h:%d\n",
+			sync,
+			(int)sync->protocol,
+			&sync->flow_ip, (int)sync->flow_ident,
+			&sync->return_ip_xlate, (int)sync->return_ident_xlate);
+
+	ECM_HIN4_ADDR_TO_IP_ADDR(flow_ip, sync->flow_ip);
+	ECM_HIN4_ADDR_TO_IP_ADDR(return_ip_xlate, sync->return_ip_xlate);
+	ECM_HIN4_ADDR_TO_IP_ADDR(return_ip, sync->return_ip);
+	flow_ident = (int)sync->flow_ident;
+	return_ident_xlate = (int)sync->return_ident_xlate;
+
+	/*
+	 * GRE connections such as PPTP-GRE are stored into the db using a 3 tuple based hash.
+	 * So we ignore the port information here when trying to lookup the connection
+	 */
+	if (sync->protocol == IPPROTO_GRE) {
+		flow_ident = 0;
+		return_ident_xlate = 0;
+	}
+#ifdef ECM_MULTICAST_ENABLE
+	/*
+	 * Check for multicast flow
+	 */
+	if (ecm_ip_addr_is_multicast(return_ip)) {
+		ci = ecm_db_connection_find_and_ref(flow_ip, return_ip, sync->protocol, flow_ident, (int)sync->return_ident);
+	} else {
+		ci = ecm_db_connection_find_and_ref(flow_ip, return_ip_xlate, sync->protocol, flow_ident, return_ident_xlate);
+	}
+#else
+	ci = ecm_db_connection_find_and_ref(flow_ip, return_ip_xlate, sync->protocol, flow_ident, return_ident_xlate);
+#endif
+	if (!ci) {
+		DEBUG_TRACE("%px: NSS Sync: no connection\n", sync);
+		return;
+	}
+
+	DEBUG_TRACE("%px: Sync conn %px\n", sync, ci);
+
+	/*
+	 * Copy the sync data to the classifier sync structure to
+	 * update the classifiers' stats.
+	 */
+	class_sync.tx_packet_count[ECM_CONN_DIR_FLOW] = sync->flow_tx_packet_count;
+	class_sync.tx_byte_count[ECM_CONN_DIR_FLOW] = sync->flow_tx_byte_count;
+	class_sync.rx_packet_count[ECM_CONN_DIR_FLOW] = sync->flow_rx_packet_count;
+	class_sync.rx_byte_count[ECM_CONN_DIR_FLOW] = sync->flow_rx_byte_count;
+	class_sync.tx_packet_count[ECM_CONN_DIR_RETURN] = sync->return_tx_packet_count;
+	class_sync.tx_byte_count[ECM_CONN_DIR_RETURN] = sync->return_tx_byte_count;
+	class_sync.rx_packet_count[ECM_CONN_DIR_RETURN] = sync->return_rx_packet_count;
+	class_sync.rx_byte_count[ECM_CONN_DIR_RETURN] = sync->return_rx_byte_count;
+	class_sync.reason = sync->reason;
+
+	/*
+	 * Sync assigned classifiers
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: sync to: %px, type: %d\n", ci, aci, aci->type_get(aci));
+		aci->sync_to_v4(aci, &class_sync);
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Get the elapsed time since the last sync and add this elapsed time
+	 * to the conntrack's timeout while updating it. If the return value is
+	 * a negative value which means the timer is not in a valid state, just
+	 * return here and do not update the defunct timer and the conntrack.
+	 */
+	elapsed = ecm_db_connection_elapsed_defunct_timer(ci);
+	if (elapsed < 0) {
+		ecm_db_connection_deref(ci);
+		return;
+	}
+	DEBUG_TRACE("%px: elapsed: %d\n", ci, elapsed);
+	delta_jiffies = elapsed * HZ;
+
+	/*
+	 * Keep connection alive and updated
+	 */
+	if (!ecm_db_connection_defunct_timer_touch(ci)) {
+		ecm_db_connection_deref(ci);
+		goto sync_conntrack;
+	}
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+	if (sync->flow_tx_packet_count || sync->return_tx_packet_count) {
+		DEBUG_TRACE("%px: flow_rx_packet_count: %u, flow_rx_byte_count: %u, return_rx_packet_count: %u, return_rx_byte_count: %u\n",
+				ci, sync->flow_rx_packet_count, sync->flow_rx_byte_count, sync->return_rx_packet_count, sync->return_rx_byte_count);
+		DEBUG_TRACE("%px: flow_tx_packet_count: %u, flow_tx_byte_count: %u, return_tx_packet_count: %u, return_tx_byte_count: %u\n",
+				ci, sync->flow_tx_packet_count, sync->flow_tx_byte_count, sync->return_tx_packet_count, sync->return_tx_byte_count);
+#ifdef ECM_MULTICAST_ENABLE
+		if (ecm_ip_addr_is_multicast(return_ip)) {
+			/*
+			 * The amount of data *sent* by the ECM multicast connection 'from' side is the amount the NSS has *received* in the 'flow' direction.
+			 */
+			ecm_db_multicast_connection_data_totals_update(ci, true, sync->flow_rx_byte_count, sync->flow_rx_packet_count);
+			ecm_db_multicast_connection_data_totals_update(ci, false, sync->return_rx_byte_count, sync->return_rx_packet_count);
+			ecm_db_multicast_connection_interface_heirarchy_stats_update(ci, sync->flow_rx_byte_count, sync->flow_rx_packet_count);
+
+			/*
+			 * As packets have been accelerated we have seen some action.
+			 */
+			feci->action_seen(feci);
+
+			/*
+			 * Update interface statistics
+			 */
+			ecm_interface_multicast_stats_update(ci, sync->flow_tx_packet_count, sync->flow_tx_byte_count, sync->flow_rx_packet_count, sync->flow_rx_byte_count,
+										sync->return_tx_packet_count, sync->return_tx_byte_count, sync->return_rx_packet_count, sync->return_rx_byte_count);
+			/*
+			 * Update IP multicast routing cache stats
+			 */
+			ipmr_mfc_stats_update(&init_net, htonl(flow_ip[0]), htonl(return_ip[0]), sync->flow_rx_packet_count,
+										 sync->flow_rx_byte_count, sync->flow_rx_packet_count, sync->flow_rx_byte_count);
+		} else {
+			/*
+			 * The amount of data *sent* by the ECM connection 'from' side is the amount the NSS has *received* in the 'flow' direction.
+			 */
+			ecm_db_connection_data_totals_update(ci, true, sync->flow_rx_byte_count, sync->flow_rx_packet_count);
+
+			/*
+			 * The amount of data *sent* by the ECM connection 'to' side is the amount the NSS has *received* in the 'return' direction.
+			 */
+			ecm_db_connection_data_totals_update(ci, false, sync->return_rx_byte_count, sync->return_rx_packet_count);
+
+			/*
+			 * As packets have been accelerated we have seen some action.
+			 */
+			feci->action_seen(feci);
+
+			/*
+			 * Update interface statistics
+			 */
+			ecm_interface_stats_update(ci, sync->flow_tx_packet_count, sync->flow_tx_byte_count, sync->flow_rx_packet_count, sync->flow_rx_byte_count,
+							sync->return_tx_packet_count, sync->return_tx_byte_count, sync->return_rx_packet_count, sync->return_rx_byte_count);
+		}
+
+#else
+		/*
+		 * The amount of data *sent* by the ECM connection 'from' side is the amount the NSS has *received* in the 'flow' direction.
+		 */
+		ecm_db_connection_data_totals_update(ci, true, sync->flow_rx_byte_count, sync->flow_rx_packet_count);
+
+		/*
+		 * The amount of data *sent* by the ECM connection 'to' side is the amount the NSS has *received* in the 'return' direction.
+		 */
+		ecm_db_connection_data_totals_update(ci, false, sync->return_rx_byte_count, sync->return_rx_packet_count);
+
+		/*
+		 * As packets have been accelerated we have seen some action.
+		 */
+		feci->action_seen(feci);
+
+		/*
+		 * Update interface statistics
+		 */
+		ecm_interface_stats_update(ci, sync->flow_tx_packet_count, sync->flow_tx_byte_count, sync->flow_rx_packet_count, sync->flow_rx_byte_count,
+						sync->return_tx_packet_count, sync->return_tx_byte_count, sync->return_rx_packet_count, sync->return_rx_byte_count);
+#endif
+	}
+
+	switch(sync->reason) {
+	case NSS_IPV4_RULE_SYNC_REASON_DESTROY:
+		/*
+		 * This is the final sync from the NSS for a connection whose acceleration was
+		 * terminated by the ecm.
+		 * NOTE: We take no action here since that is performed by the destroy message ack.
+		 */
+		DEBUG_INFO("%px: ECM initiated final sync seen: %d\n", ci, sync->reason);
+		break;
+	case NSS_IPV4_RULE_SYNC_REASON_FLUSH:
+	case NSS_IPV4_RULE_SYNC_REASON_EVICT:
+		/*
+		 * NSS has ended acceleration without instruction from the ECM.
+		 */
+		DEBUG_INFO("%px: NSS Initiated final sync seen: %d cause:%d\n", ci, sync->reason, sync->cause);
+
+		/*
+		 * NSS Decelerated the connection
+		 */
+		feci->accel_ceased(feci);
+		break;
+	default:
+		if (ecm_db_connection_is_routed_get(ci)) {
+			/*
+			 * Update the neighbour entry for source IP address
+			 */
+			neigh = ecm_interface_ipv4_neigh_get(flow_ip);
+			if (!neigh) {
+				DEBUG_WARN("Neighbour entry for %pI4h not found\n", &sync->flow_ip);
+			} else {
+				if (sync->flow_tx_packet_count) {
+					DEBUG_TRACE("Neighbour entry event send for %pI4h: %px\n", &sync->flow_ip, neigh);
+					neigh_event_send(neigh, NULL);
+				}
+
+				neigh_release(neigh);
+			}
+
+#ifdef ECM_MULTICAST_ENABLE
+			/*
+			 * Update the neighbour entry for destination IP address
+			 */
+			if (!ecm_ip_addr_is_multicast(return_ip)) {
+				neigh = ecm_interface_ipv4_neigh_get(return_ip);
+				if (!neigh) {
+					DEBUG_WARN("Neighbour entry for %pI4h not found\n", &sync->return_ip);
+				} else {
+					if (sync->return_tx_packet_count) {
+						DEBUG_TRACE("Neighbour entry event send for %pI4h: %px\n", &sync->return_ip, neigh);
+						neigh_event_send(neigh, NULL);
+					}
+
+					neigh_release(neigh);
+				}
+			}
+#else
+			/*
+			 * Update the neighbour entry for destination IP address
+			 */
+			neigh = ecm_interface_ipv4_neigh_get(return_ip);
+			if (!neigh) {
+				DEBUG_WARN("Neighbour entry for %pI4h not found\n", &sync->return_ip);
+			} else {
+				if (sync->return_tx_packet_count) {
+					DEBUG_TRACE("Neighbour entry event send for %pI4h: %px\n", &sync->return_ip, neigh);
+					neigh_event_send(neigh, NULL);
+				}
+
+				neigh_release(neigh);
+			}
+#endif
+		}
+	}
+
+	/*
+	 * If connection should be re-generated then we need to force a deceleration
+	 */
+	if (unlikely(ecm_db_connection_regeneration_required_peek(ci))) {
+		DEBUG_TRACE("%px: Connection generation changing, terminating acceleration", ci);
+		feci->decelerate(feci);
+	}
+
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+
+sync_conntrack:
+	;
+
+	/*
+	 * Create a tuple so as to be able to look up a conntrack connection
+	 */
+	memset(&tuple, 0, sizeof(tuple));
+	tuple.src.u3.ip = htonl(sync->flow_ip);
+	tuple.src.u.all = (__be16)htons(sync->flow_ident);
+	tuple.src.l3num = AF_INET;
+
+	tuple.dst.u3.ip = htonl(sync->return_ip);
+	tuple.dst.dir = IP_CT_DIR_ORIGINAL;
+	tuple.dst.protonum = (uint8_t)sync->protocol;
+	tuple.dst.u.all = (__be16)htons(sync->return_ident);
+
+	DEBUG_TRACE("Conntrack sync, lookup conntrack connection using\n"
+			"Protocol: %d\n"
+			"src_addr: %pI4:%d\n"
+			"dest_addr: %pI4:%d\n",
+			(int)tuple.dst.protonum,
+			&tuple.src.u3.ip, (int)(ntohs(tuple.src.u.all)),
+			&tuple.dst.u3.ip, (int)(ntohs(tuple.dst.u.all)));
+
+	/*
+	 * Look up conntrack connection
+	 */
+	h = nf_conntrack_find_get(&init_net, &nf_ct_zone_dflt, &tuple);
+	if (!h) {
+		DEBUG_WARN("%px: NSS Sync: no conntrack connection\n", sync);
+		return;
+	}
+
+	ct = nf_ct_tuplehash_to_ctrack(h);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0))
+	NF_CT_ASSERT(ct->timeout.data == (unsigned long)ct);
+#endif
+	DEBUG_TRACE("%px: NSS Sync: conntrack connection\n", ct);
+
+	ecm_front_end_flow_and_return_directions_get(ct, flow_ip, 4, &flow_dir, &return_dir);
+
+	/*
+	 * Only update if this is not a fixed timeout
+	 * delta_jiffies is the elapsed time since the last sync of this connection.
+	 */
+	if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) {
+		spin_lock_bh(&ct->lock);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0))
+		ct->timeout.expires += delta_jiffies;
+#else
+		ct->timeout += delta_jiffies;
+#endif
+		spin_unlock_bh(&ct->lock);
+	}
+
+	acct = nf_conn_acct_find(ct)->counter;
+	if (acct) {
+		spin_lock_bh(&ct->lock);
+		atomic64_add(sync->flow_rx_packet_count, &acct[flow_dir].packets);
+		atomic64_add(sync->flow_rx_byte_count, &acct[flow_dir].bytes);
+
+		atomic64_add(sync->return_rx_packet_count, &acct[return_dir].packets);
+		atomic64_add(sync->return_rx_byte_count, &acct[return_dir].bytes);
+		spin_unlock_bh(&ct->lock);
+	}
+
+	switch (sync->protocol) {
+	case IPPROTO_TCP:
+		spin_lock_bh(&ct->lock);
+		if (ct->proto.tcp.seen[flow_dir].td_maxwin < sync->flow_max_window) {
+			ct->proto.tcp.seen[flow_dir].td_maxwin = sync->flow_max_window;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[flow_dir].td_end - sync->flow_end) < 0) {
+			ct->proto.tcp.seen[flow_dir].td_end = sync->flow_end;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[flow_dir].td_maxend - sync->flow_max_end) < 0) {
+			ct->proto.tcp.seen[flow_dir].td_maxend = sync->flow_max_end;
+		}
+		if (ct->proto.tcp.seen[return_dir].td_maxwin < sync->return_max_window) {
+			ct->proto.tcp.seen[return_dir].td_maxwin = sync->return_max_window;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[return_dir].td_end - sync->return_end) < 0) {
+			ct->proto.tcp.seen[return_dir].td_end = sync->return_end;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[return_dir].td_maxend - sync->return_max_end) < 0) {
+			ct->proto.tcp.seen[return_dir].td_maxend = sync->return_max_end;
+		}
+		spin_unlock_bh(&ct->lock);
+		break;
+	case IPPROTO_UDP:
+		/*
+		 * In Linux connection track, UDP flow has two timeout values:
+		 * /proc/sys/net/netfilter/nf_conntrack_udp_timeout:
+		 * 	this is for uni-direction UDP flow, normally its value is 60 seconds
+		 * /proc/sys/net/netfilter/nf_conntrack_udp_timeout_stream:
+		 * 	this is for bi-direction UDP flow, normally its value is 180 seconds
+		 *
+		 * Linux will update timer of UDP flow to stream timeout once it seen packets
+		 * in reply direction. But if flow is accelerated by NSS or SFE, Linux won't
+		 * see any packets. So we have to do the same thing in our stats sync message.
+		 */
+		if (!test_bit(IPS_ASSURED_BIT, &ct->status) && acct) {
+			u_int64_t reply_pkts = atomic64_read(&acct[IP_CT_DIR_REPLY].packets);
+
+			if (reply_pkts != 0) {
+				struct nf_conntrack_l4proto *l4proto __maybe_unused;
+				unsigned int *timeouts;
+
+				set_bit(IPS_SEEN_REPLY_BIT, &ct->status);
+				set_bit(IPS_ASSURED_BIT, &ct->status);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0))
+				l4proto = __nf_ct_l4proto_find(AF_INET, IPPROTO_UDP);
+				timeouts = nf_ct_timeout_lookup(&init_net, ct, l4proto);
+
+				spin_lock_bh(&ct->lock);
+				ct->timeout.expires = jiffies + timeouts[UDP_CT_REPLIED];
+				spin_unlock_bh(&ct->lock);
+#else
+				timeouts = nf_ct_timeout_lookup(ct);
+				if (!timeouts) {
+					timeouts = udp_get_timeouts(nf_ct_net(ct));
+				}
+
+				spin_lock_bh(&ct->lock);
+				ct->timeout = jiffies + timeouts[UDP_CT_REPLIED];
+				spin_unlock_bh(&ct->lock);
+#endif
+			}
+		}
+		break;
+	}
+
+	/*
+	 * Release connection
+	 */
+	nf_ct_put(ct);
+}
+
+/*
+ * ecm_nss_ipv4_net_dev_callback()
+ *	Callback handler from the NSS.
+ */
+static void ecm_nss_ipv4_net_dev_callback(void *app_data, struct nss_ipv4_msg *nim)
+{
+	struct nss_ipv4_conn_sync *sync;
+
+	/*
+	 * Only respond to sync messages
+	 */
+	if (nim->cm.type != NSS_IPV4_RX_CONN_STATS_SYNC_MSG) {
+		return;
+	}
+	sync = &nim->msg.conn_stats;
+	ecm_nss_ipv4_process_one_conn_sync_msg(sync);
+}
+
+/*
+ * ecm_nss_ipv4_connection_sync_many_callback()
+ *	Callback for conn_sync_many request message
+ */
+static void ecm_nss_ipv4_connection_sync_many_callback(void *app_data, struct nss_ipv4_msg *nim)
+{
+	struct nss_ipv4_conn_sync_many_msg *nicsm = &nim->msg.conn_stats_many;
+	int i;
+
+	/*
+	 * If ECM is terminating, don't process this final stats
+	 */
+	if (ecm_ipv4_terminate_pending) {
+		return;
+	}
+
+	if (nim->cm.response == NSS_CMN_RESPONSE_ACK) {
+		for (i = 0; i < nicsm->count; i++) {
+			ecm_nss_ipv4_process_one_conn_sync_msg(&nicsm->conn_sync[i]);
+		}
+		ecm_nss_ipv4_sync_req_msg->msg.conn_stats_many.index = nicsm->next;
+	} else {
+		/*
+		 * We get a NACK from FW, which should not happen, restart the request
+		 */
+		DEBUG_WARN("IPv4 conn stats request failed, restarting\n");
+		ecm_nss_ipv4_stats_request_nack++;
+		ecm_nss_ipv4_sync_req_msg->msg.conn_stats_many.index = 0;
+	}
+	queue_delayed_work(ecm_nss_ipv4_workqueue, &ecm_nss_ipv4_work, 0);
+}
+
+/*
+ * ecm_nss_ipv4_stats_sync_req_work()
+ *      Schedule delayed work to process connection stats and request next sync
+ */
+static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work)
+{
+	/*
+	 * Prepare a nss_ipv4_msg with CONN_STATS_SYNC_MANY request
+	 */
+	struct nss_ipv4_conn_sync_many_msg *nicsm_req = &ecm_nss_ipv4_sync_req_msg->msg.conn_stats_many;
+	nss_tx_status_t nss_tx_status;
+	int retry = 3;
+	unsigned long int current_jiffies;
+
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	if (ecm_nss_ipv4_accelerated_count == 0) {
+		spin_unlock_bh(&ecm_nss_ipv4_lock);
+		DEBUG_TRACE("There is no accelerated IPv4 connection\n");
+		goto reschedule;
+	}
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY);
+
+	/*
+	 * If index is 0, we are starting a new round, but if we still have time remain
+	 * in this round, sleep until it ends
+	 */
+	if (nicsm_req->index == 0) {
+		current_jiffies = jiffies;
+
+		if (time_is_after_jiffies(ecm_nss_ipv4_roll_check_jiffies))  {
+			ecm_nss_ipv4_next_req_time = jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD;
+		}
+
+		if (time_after(ecm_nss_ipv4_next_req_time, current_jiffies)) {
+			msleep(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies));
+		}
+		ecm_nss_ipv4_roll_check_jiffies = jiffies;
+		ecm_nss_ipv4_next_req_time = ecm_nss_ipv4_roll_check_jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD;
+	}
+
+	while (retry) {
+		if (ecm_ipv4_terminate_pending) {
+			return;
+		}
+		nss_tx_status = nss_ipv4_tx_with_size(ecm_nss_ipv4_nss_ipv4_mgr, ecm_nss_ipv4_sync_req_msg, PAGE_SIZE);
+		if (nss_tx_status == NSS_TX_SUCCESS) {
+			ecm_nss_ipv4_stats_request_success++;
+			return;
+		}
+		ecm_nss_ipv4_stats_request_fail++;
+		retry--;
+		DEBUG_TRACE("TX_NOT_OKAY, try again later\n");
+		usleep_range(100, 200);
+	}
+
+reschedule:
+	/*
+	 * TX failed after retries, reschedule ourselves with fresh start
+	 */
+	nicsm_req->count = 0;
+	nicsm_req->index = 0;
+	queue_delayed_work(ecm_nss_ipv4_workqueue, &ecm_nss_ipv4_work, ECM_NSS_IPV4_STATS_SYNC_PERIOD);
+}
+
+/*
+ * ecm_nss_ipv4_get_accel_limit_mode()
+ */
+static int ecm_nss_ipv4_get_accel_limit_mode(void *data, u64 *val)
+{
+	*val = ecm_nss_ipv4_accel_limit_mode;
+
+	return 0;
+}
+
+/*
+ * ecm_nss_ipv4_set_accel_limit_mode()
+ */
+static int ecm_nss_ipv4_set_accel_limit_mode(void *data, u64 val)
+{
+	DEBUG_TRACE("ecm_nss_ipv4_accel_limit_mode = %x\n", (int)val);
+
+	/*
+	 * Check that only valid bits are set.
+	 * It's fine for no bits to be set as that suggests no modes are wanted.
+	 */
+	if (val && (val ^ (ECM_FRONT_END_ACCEL_LIMIT_MODE_FIXED | ECM_FRONT_END_ACCEL_LIMIT_MODE_UNLIMITED))) {
+		DEBUG_WARN("ecm_nss_ipv4_accel_limit_mode = %x bad\n", (int)val);
+		return -EINVAL;
+	}
+
+	ecm_nss_ipv4_accel_limit_mode = (int)val;
+
+	return 0;
+}
+
+/*
+ * Debugfs attribute for accel limit mode.
+ */
+DEFINE_SIMPLE_ATTRIBUTE(ecm_nss_ipv4_accel_limit_mode_fops, ecm_nss_ipv4_get_accel_limit_mode, ecm_nss_ipv4_set_accel_limit_mode, "%llu\n");
+/*
+ * ecm_nss_ipv4_get_accel_cmd_avg_millis()
+ */
+static ssize_t ecm_nss_ipv4_get_accel_cmd_avg_millis(struct file *file,
+								char __user *user_buf,
+								size_t sz, loff_t *ppos)
+{
+	unsigned long set;
+	unsigned long samples;
+	unsigned long avg;
+	char *buf;
+	int ret;
+
+	buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!buf) {
+		return -ENOMEM;
+	}
+
+	/*
+	 * Operate under our locks.
+	 * Compute the average of the samples taken and seed the next set of samples with the result of this one.
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	samples = ecm_nss_ipv4_accel_cmd_time_avg_samples;
+	set = ecm_nss_ipv4_accel_cmd_time_avg_set;
+	ecm_nss_ipv4_accel_cmd_time_avg_samples /= ecm_nss_ipv4_accel_cmd_time_avg_set;
+	ecm_nss_ipv4_accel_cmd_time_avg_set = 1;
+	avg = ecm_nss_ipv4_accel_cmd_time_avg_samples;
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	/*
+	 * Convert average jiffies to milliseconds
+	 */
+	avg *= 1000;
+	avg /= HZ;
+
+	ret = snprintf(buf, (ssize_t)PAGE_SIZE, "avg=%lu\tsamples=%lu\tset_size=%lu\n", avg, samples, set);
+	if (ret < 0) {
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	ret = simple_read_from_buffer(user_buf, sz, ppos, buf, ret);
+	kfree(buf);
+	return ret;
+}
+
+/*
+ * File operations for accel command average time.
+ */
+static struct file_operations ecm_nss_ipv4_accel_cmd_avg_millis_fops = {
+	.read = ecm_nss_ipv4_get_accel_cmd_avg_millis,
+};
+
+/*
+ * ecm_nss_ipv4_get_decel_average_millis()
+ */
+static ssize_t ecm_nss_ipv4_get_decel_cmd_avg_millis(struct file *file,
+								char __user *user_buf,
+								size_t sz, loff_t *ppos)
+{
+	unsigned long set;
+	unsigned long samples;
+	unsigned long avg;
+	char *buf;
+	int ret;
+
+	buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!buf) {
+		return -ENOMEM;
+	}
+
+	/*
+	 * Operate under our locks.
+	 * Compute the average of the samples taken and seed the next set of samples with the result of this one.
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	samples = ecm_nss_ipv4_decel_cmd_time_avg_samples;
+	set = ecm_nss_ipv4_decel_cmd_time_avg_set;
+	ecm_nss_ipv4_decel_cmd_time_avg_samples /= ecm_nss_ipv4_decel_cmd_time_avg_set;
+	ecm_nss_ipv4_decel_cmd_time_avg_set = 1;
+	avg = ecm_nss_ipv4_decel_cmd_time_avg_samples;
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	/*
+	 * Convert average jiffies to milliseconds
+	 */
+	avg *= 1000;
+	avg /= HZ;
+
+	ret = snprintf(buf, (ssize_t)PAGE_SIZE, "avg=%lu\tsamples=%lu\tset_size=%lu\n", avg, samples, set);
+	if (ret < 0) {
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	ret = simple_read_from_buffer(user_buf, sz, ppos, buf, ret);
+	kfree(buf);
+	return ret;
+}
+
+/*
+ * File operations for decel command average time.
+ */
+static struct file_operations ecm_nss_ipv4_decel_cmd_avg_millis_fops = {
+	.read = ecm_nss_ipv4_get_decel_cmd_avg_millis,
+};
+
+/*
+ * ecm_nss_ipv4_get_stats_request_counter()
+ */
+static ssize_t ecm_nss_ipv4_get_stats_request_counter(struct file *file,
+								char __user *user_buf,
+								size_t sz, loff_t *ppos)
+{
+	char *buf;
+	int ret;
+
+	buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!buf) {
+		return -ENOMEM;
+	}
+
+	ret = snprintf(buf, (ssize_t)PAGE_SIZE, "success=%lu\tfail=%lu\tnack=%lu\t\n",
+			ecm_nss_ipv4_stats_request_success, ecm_nss_ipv4_stats_request_fail,
+			ecm_nss_ipv4_stats_request_nack);
+	if (ret < 0) {
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	ret = simple_read_from_buffer(user_buf, sz, ppos, buf, ret);
+	kfree(buf);
+	return ret;
+}
+
+/*
+ * File operations for decel command average time.
+ */
+static struct file_operations ecm_nss_ipv4_stats_request_counter_fops = {
+	.read = ecm_nss_ipv4_get_stats_request_counter,
+};
+
+/*
+ * ecm_nss_ipv4_sync_queue_init
+ *	Initialize the workqueue for ipv4 stats sync
+ */
+static bool ecm_nss_ipv4_sync_queue_init(void)
+{
+	struct nss_ipv4_conn_sync_many_msg *nicsm;
+
+	/*
+	 * Setup the connection sync msg/work/workqueue
+	 */
+	ecm_nss_ipv4_sync_req_msg = kzalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!ecm_nss_ipv4_sync_req_msg) {
+		return false;
+	}
+
+	/*
+	 * Register the conn_sync_many message callback
+	 */
+	nss_ipv4_conn_sync_many_notify_register(ecm_nss_ipv4_connection_sync_many_callback);
+
+	nss_ipv4_msg_init(ecm_nss_ipv4_sync_req_msg, NSS_IPV4_RX_INTERFACE,
+		NSS_IPV4_TX_CONN_STATS_SYNC_MANY_MSG,
+		sizeof(struct nss_ipv4_conn_sync_many_msg) ,
+		NULL,
+		NULL);
+
+	nicsm = &ecm_nss_ipv4_sync_req_msg->msg.conn_stats_many;
+
+	/*
+	 * Start with index 0 and calculate the size of the conn stats array
+	 */
+	nicsm->index = 0;
+	nicsm->size = PAGE_SIZE;
+
+	ecm_nss_ipv4_workqueue = create_singlethread_workqueue("ecm_nss_ipv4_workqueue");
+	if (!ecm_nss_ipv4_workqueue) {
+		nss_ipv4_conn_sync_many_notify_unregister();
+		kfree(ecm_nss_ipv4_sync_req_msg);
+		return false;
+	}
+	INIT_DELAYED_WORK(&ecm_nss_ipv4_work, ecm_nss_ipv4_stats_sync_req_work);
+	queue_delayed_work(ecm_nss_ipv4_workqueue, &ecm_nss_ipv4_work, ECM_NSS_IPV4_STATS_SYNC_PERIOD);
+
+	return true;
+}
+
+/*
+ * ecm_nss_ipv4_sync_queue_exit
+ *	 the workqueue for ipv4 stats sync
+ */
+static void ecm_nss_ipv4_sync_queue_exit(void)
+{
+	/*
+	 * Unregister the conn_sync_many message callback
+	 * Otherwise nss will call our callback which does not exist anymore
+	 */
+	nss_ipv4_conn_sync_many_notify_unregister();
+
+	/*
+	 * Cancel the conn sync req work and destroy workqueue
+	 */
+	cancel_delayed_work_sync(&ecm_nss_ipv4_work);
+	destroy_workqueue(ecm_nss_ipv4_workqueue);
+	kfree(ecm_nss_ipv4_sync_req_msg);
+}
+
+/*
+ * ecm_nss_ipv4_init()
+ */
+int ecm_nss_ipv4_init(struct dentry *dentry)
+{
+	int result = -1;
+
+	if (!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_NSS)) {
+		DEBUG_INFO("NSS IPv4 is disabled\n");
+		return 0;
+	}
+
+	DEBUG_INFO("ECM NSS IPv4 init\n");
+
+	ecm_nss_ipv4_dentry = debugfs_create_dir("ecm_nss_ipv4", dentry);
+	if (!ecm_nss_ipv4_dentry) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 directory in debugfs\n");
+		return result;
+	}
+
+	if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry,
+					(u32 *)&ecm_nss_ipv4_no_action_limit_default)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 no_action_limit_default file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry,
+					(u32 *)&ecm_nss_ipv4_driver_fail_limit_default)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 driver_fail_limit_default file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry,
+					(u32 *)&ecm_nss_ipv4_nack_limit_default)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 nack_limit_default file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv4_dentry,
+					(u32 *)&ecm_nss_ipv4_accelerated_count)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 accelerated_count file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv4_dentry,
+					(u32 *)&ecm_nss_ipv4_pending_accel_count)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 pending_accel_count file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv4_dentry,
+					(u32 *)&ecm_nss_ipv4_pending_decel_count)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 pending_decel_count file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry,
+					NULL, &ecm_nss_ipv4_accel_limit_mode_fops)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 accel_limit_mode file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_file("accel_cmd_avg_millis", S_IRUGO, ecm_nss_ipv4_dentry,
+					NULL, &ecm_nss_ipv4_accel_cmd_avg_millis_fops)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 accel_cmd_avg_millis file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_file("decel_cmd_avg_millis", S_IRUGO, ecm_nss_ipv4_dentry,
+					NULL, &ecm_nss_ipv4_decel_cmd_avg_millis_fops)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 decel_cmd_avg_millis file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!ecm_nss_ported_ipv4_debugfs_init(ecm_nss_ipv4_dentry)) {
+		DEBUG_ERROR("Failed to create ecm ported files in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_file("stats_request_counter", S_IRUGO, ecm_nss_ipv4_dentry,
+					NULL, &ecm_nss_ipv4_stats_request_counter_fops)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 stats request counter file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry,
+					(u32 *)&ecm_nss_ipv4_vlan_passthrough_enable)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 vlan passthrough file in debugfs\n");
+		goto task_cleanup;
+	}
+
+#ifdef ECM_NON_PORTED_SUPPORT_ENABLE
+	if (!ecm_nss_non_ported_ipv4_debugfs_init(ecm_nss_ipv4_dentry)) {
+		DEBUG_ERROR("Failed to create ecm non-ported files in debugfs\n");
+		goto task_cleanup;
+	}
+#endif
+
+#ifdef ECM_MULTICAST_ENABLE
+	if (!ecm_nss_multicast_ipv4_debugfs_init(ecm_nss_ipv4_dentry)) {
+		DEBUG_ERROR("Failed to create ecm multicast files in debugfs\n");
+		goto task_cleanup;
+	}
+#endif
+	/*
+	 * Register this module with the Linux NSS Network driver.
+	 * Notify manager should be registered before the netfilter hooks. Because there
+	 * is a possibility that the ECM can try to send acceleration messages to the
+	 * acceleration engine without having an acceleration engine manager.
+	 */
+	ecm_nss_ipv4_nss_ipv4_mgr = nss_ipv4_notify_register(ecm_nss_ipv4_net_dev_callback, NULL);
+
+#ifdef ECM_MULTICAST_ENABLE
+	result = ecm_nss_multicast_ipv4_init(ecm_nss_ipv4_dentry);
+	if (result < 0) {
+		DEBUG_ERROR("Failed to init ecm ipv4 multicast frontend\n");
+		goto task_cleanup_1;
+	}
+#endif
+
+	if (!ecm_nss_ipv4_sync_queue_init()) {
+		DEBUG_ERROR("Failed to create ecm ipv4 connection sync workqueue\n");
+		goto task_cleanup_2;
+	}
+
+	return 0;
+
+task_cleanup_2:
+#ifdef ECM_MULTICAST_ENABLE
+	ecm_nss_multicast_ipv4_exit();
+task_cleanup_1:
+#endif
+	nss_ipv4_notify_unregister();
+
+task_cleanup:
+	debugfs_remove_recursive(ecm_nss_ipv4_dentry);
+	return result;
+}
+
+/*
+ * ecm_nss_ipv4_exit()
+ */
+void ecm_nss_ipv4_exit(void)
+{
+	if (!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_NSS)) {
+		DEBUG_INFO("NSS IPv4 is disabled\n");
+		return;
+	}
+
+	DEBUG_INFO("ECM NSS IPv4 Module exit\n");
+
+	/*
+	 * Unregister from the Linux NSS Network driver
+	 */
+	nss_ipv4_notify_unregister();
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_nss_ipv4_dentry) {
+		debugfs_remove_recursive(ecm_nss_ipv4_dentry);
+	}
+
+#ifdef ECM_MULTICAST_ENABLE
+	ecm_nss_multicast_ipv4_exit();
+#endif
+
+	/*
+	 * Clean up the stats sync queue/work
+	 */
+	ecm_nss_ipv4_sync_queue_exit();
+}
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_ipv4.h b/qca-nss-ecm/frontends/nss/ecm_nss_ipv4.h
new file mode 100644
index 0000000..f993336
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_ipv4.h
@@ -0,0 +1,170 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2016, 2020 The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <nss_api_if.h>
+
+extern int ecm_nss_ipv4_no_action_limit_default;		/* Default no-action limit. */
+extern int ecm_nss_ipv4_driver_fail_limit_default;		/* Default driver fail limit. */
+extern int ecm_nss_ipv4_nack_limit_default;			/* Default nack limit. */
+extern int ecm_nss_ipv4_accelerated_count;			/* Total offloads */
+extern int ecm_nss_ipv4_pending_accel_count;			/* Total pending offloads issued to the NSS / awaiting completion */
+extern int ecm_nss_ipv4_pending_decel_count;			/* Total pending deceleration requests issued to the NSS / awaiting completion */
+
+/*
+ * Limiting the acceleration of connections.
+ *
+ * By default there is no acceleration limiting.
+ * This means that when ECM has more connections (that can be accelerated) than the acceleration
+ * engine will allow the ECM will continue to try to accelerate.
+ * In this scenario the acceleration engine will begin removal of existing rules to make way for new ones.
+ * When the accel_limit_mode is set to FIXED ECM will not permit more rules to be issued than the engine will allow.
+ */
+extern uint32_t ecm_nss_ipv4_accel_limit_mode;
+
+/*
+ * Flag to enable/disable bridge VLAN passthrough feature.
+ * By default this feature is disabled.
+ */
+extern int ecm_nss_ipv4_vlan_passthrough_enable;
+
+/*
+ * Locking of the classifier - concurrency control for file global parameters.
+ * NOTE: It is safe to take this lock WHILE HOLDING a feci->lock.  The reverse is NOT SAFE.
+ */
+extern spinlock_t ecm_nss_ipv4_lock;			/* Protect against SMP access between netfilter, events and private threaded function. */
+
+/*
+ * NSS driver linkage
+ */
+extern struct nss_ctx_instance *ecm_nss_ipv4_nss_ipv4_mgr;
+
+/*
+ * ecm_nss_ipv4_accel_pending_set()
+ *	Set pending acceleration for the connection object.
+ *
+ * Return false if the acceleration is not permitted or is already in progress.
+ */
+static inline bool ecm_nss_ipv4_accel_pending_set(struct ecm_front_end_connection_instance *feci)
+{
+	DEBUG_INFO("%px: Accel conn: %px\n", feci, feci->ci);
+
+	/*
+	 * If re-generation is required then we cannot permit acceleration
+	 */
+	if (ecm_db_connection_regeneration_required_peek(feci->ci)) {
+		DEBUG_TRACE("%px: accel %px failed - regen required\n", feci, feci->ci);
+		return false;
+	}
+
+	/*
+	 * Is connection acceleration permanently failed?
+	 */
+	spin_lock_bh(&feci->lock);
+	if (ECM_FRONT_END_ACCELERATION_FAILED(feci->accel_mode)) {
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: accel %px failed\n", feci, feci->ci);
+		return false;
+	}
+
+	/*
+	 * If acceleration mode is anything other than "not accelerated" then ignore.
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_DECEL) {
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: Ignoring wrong mode accel for conn: %px\n", feci, feci->ci);
+		return false;
+	}
+
+	/*
+	 * Do we have a fixed upper limit for acceleration?
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	if (ecm_nss_ipv4_accel_limit_mode & ECM_FRONT_END_ACCEL_LIMIT_MODE_FIXED) {
+		if ((ecm_nss_ipv4_pending_accel_count + ecm_nss_ipv4_accelerated_count) >= nss_ipv4_max_conn_count()) {
+			spin_unlock_bh(&ecm_nss_ipv4_lock);
+			spin_unlock_bh(&feci->lock);
+			DEBUG_INFO("%px: Accel limit reached, accel denied: %px\n", feci, feci->ci);
+			return false;
+		}
+	}
+
+	/*
+	 * Okay to accelerate
+	 */
+	ecm_nss_ipv4_pending_accel_count++;
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	/*
+	 * Okay connection can be set to pending acceleration
+	 */
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+	return true;
+}
+
+/*
+ * _ecm_nss_ipv4_accel_pending_clear()
+ *	Clear pending acceleration for the connection object, setting it to the desired state.
+ *
+ * Returns true if "decelerate was pending".
+ *
+ * The feci->lock AND ecm_nss_ipv4_lock must be held on entry.
+ */
+static inline bool _ecm_nss_ipv4_accel_pending_clear(struct ecm_front_end_connection_instance *feci, ecm_front_end_acceleration_mode_t mode)
+{
+	bool decel_pending;
+
+	/*
+	 * Set the mode away from its accel pending state.
+	 */
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Accel mode unexpected: %d\n", feci, feci->accel_mode);
+	feci->accel_mode = mode;
+
+	/*
+	 * Clear decelerate pending flag.
+	 * This flag is only set when we are ACCEL_PENDING -
+	 * and we are moving from that to the given mode anyway.
+	 */
+	decel_pending = feci->stats.decelerate_pending;
+	feci->stats.decelerate_pending = false;
+
+	/*
+	 * Decrement pending counter
+	 */
+	ecm_nss_ipv4_pending_accel_count--;
+	DEBUG_ASSERT(ecm_nss_ipv4_pending_accel_count >= 0, "Accel pending underflow\n");
+	return decel_pending;
+}
+
+/*
+ * ecm_nss_ipv4_accel_pending_clear()
+ *	Clear pending acceleration for the connection object, setting it to the desired state.
+ */
+static inline bool ecm_nss_ipv4_accel_pending_clear(struct ecm_front_end_connection_instance *feci, ecm_front_end_acceleration_mode_t mode)
+{
+	bool decel_pending;
+	spin_lock_bh(&feci->lock);
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	decel_pending = _ecm_nss_ipv4_accel_pending_clear(feci, mode);
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+	spin_unlock_bh(&feci->lock);
+	return decel_pending;
+}
+
+extern void ecm_nss_ipv4_accel_done_time_update(struct ecm_front_end_connection_instance *feci);
+extern void ecm_nss_ipv4_decel_done_time_update(struct ecm_front_end_connection_instance *feci);
+extern int ecm_nss_ipv4_init(struct dentry *dentry);
+extern void ecm_nss_ipv4_exit(void);
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_ipv6.c b/qca-nss-ecm/frontends/nss/ecm_nss_ipv6.c
new file mode 100644
index 0000000..9a5feee
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_ipv6.c
@@ -0,0 +1,1137 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/debugfs.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/ip6_route.h>
+#include <net/ip6_fib.h>
+#include <net/addrconf.h>
+#include <net/ipv6.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in6.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/ppp_defs.h>
+#include <linux/mroute6.h>
+#include <linux/vmalloc.h>
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv6.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+#include <net/vxlan.h>
+#endif
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <linux/netfilter/nf_conntrack_zones_common.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/nf_conntrack_timeout.h>
+#include <net/netfilter/ipv6/nf_conntrack_ipv6.h>
+#include <net/netfilter/ipv6/nf_defrag_ipv6.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_IPV6_DEBUG_LEVEL
+
+#include <nss_api_if.h>
+#ifdef ECM_MULTICAST_ENABLE
+#include <mc_ecm.h>
+#endif
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+#include "ecm_classifier_nl.h"
+#endif
+#include "ecm_interface.h"
+#include "ecm_nss_common.h"
+#include "ecm_nss_ported_ipv6.h"
+#ifdef ECM_MULTICAST_ENABLE
+#include "ecm_nss_multicast_ipv6.h"
+#endif
+#ifdef ECM_NON_PORTED_SUPPORT_ENABLE
+#include "ecm_nss_non_ported_ipv6.h"
+#endif
+#include "ecm_front_end_common.h"
+#include "ecm_front_end_ipv6.h"
+#include "ecm_ipv6.h"
+
+#define ECM_NSS_IPV6_STATS_SYNC_PERIOD msecs_to_jiffies(1000)
+#define ECM_NSS_IPV6_STATS_SYNC_UDELAY 4000	/* Delay for 4ms */
+
+int ecm_nss_ipv6_no_action_limit_default = 250;		/* Default no-action limit. */
+int ecm_nss_ipv6_driver_fail_limit_default = 250;		/* Default driver fail limit. */
+int ecm_nss_ipv6_nack_limit_default = 250;			/* Default nack limit. */
+int ecm_nss_ipv6_accelerated_count = 0;			/* Total offloads */
+int ecm_nss_ipv6_pending_accel_count = 0;			/* Total pending offloads issued to the NSS / awaiting completion */
+int ecm_nss_ipv6_pending_decel_count = 0;			/* Total pending deceleration requests issued to the NSS / awaiting completion */
+int ecm_nss_ipv6_vlan_passthrough_enable = 0;		/* VLAN passthrough feature enable or disable flag */
+
+/*
+ * Limiting the acceleration of connections.
+ *
+ * By default there is no acceleration limiting.
+ * This means that when ECM has more connections (that can be accelerated) than the acceleration
+ * engine will allow the ECM will continue to try to accelerate.
+ * In this scenario the acceleration engine will begin removal of existing rules to make way for new ones.
+ * When the accel_limit_mode is set to FIXED ECM will not permit more rules to be issued than the engine will allow.
+ */
+uint32_t ecm_nss_ipv6_accel_limit_mode = ECM_FRONT_END_ACCEL_LIMIT_MODE_UNLIMITED;
+
+/*
+ * Locking of the classifier - concurrency control for file global parameters.
+ * NOTE: It is safe to take this lock WHILE HOLDING a feci->lock.  The reverse is NOT SAFE.
+ */
+DEFINE_SPINLOCK(ecm_nss_ipv6_lock);			/* Protect against SMP access between netfilter, events and private threaded function. */
+
+/*
+ * Workqueue for the connection sync
+ */
+struct workqueue_struct *ecm_nss_ipv6_workqueue;
+struct delayed_work ecm_nss_ipv6_work;
+struct nss_ipv6_msg *ecm_nss_ipv6_sync_req_msg;
+static unsigned long int ecm_nss_ipv6_next_req_time;
+static unsigned long int ecm_nss_ipv6_roll_check_jiffies;
+static unsigned long int ecm_nss_ipv6_stats_request_success = 0;	/* Number of success stats request */
+static unsigned long int ecm_nss_ipv6_stats_request_fail = 0;		/* Number of failed stats request */
+static unsigned long int ecm_nss_ipv6_stats_request_nack = 0;		/* Number of NACK'd stats request */
+
+/*
+ * NSS driver linkage
+ */
+struct nss_ctx_instance *ecm_nss_ipv6_nss_ipv6_mgr = NULL;
+
+static unsigned long ecm_nss_ipv6_accel_cmd_time_avg_samples = 0;	/* Sum of time taken for the set of accel command samples, used to compute average time for an accel command to complete */
+static unsigned long ecm_nss_ipv6_accel_cmd_time_avg_set = 1;	/* How many samples in the set */
+static unsigned long ecm_nss_ipv6_decel_cmd_time_avg_samples = 0;	/* Sum of time taken for the set of accel command samples, used to compute average time for an accel command to complete */
+static unsigned long ecm_nss_ipv6_decel_cmd_time_avg_set = 1;	/* How many samples in the set */
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_nss_ipv6_dentry;
+
+/*
+ * ecm_nss_ipv6_accel_done_time_update()
+ *	Record how long the command took to complete, updating average samples
+ */
+void ecm_nss_ipv6_accel_done_time_update(struct ecm_front_end_connection_instance *feci)
+{
+	unsigned long delta;
+
+	/*
+	 * How long did it take the command to complete?
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_completed = jiffies;
+	delta = feci->stats.cmd_time_completed - feci->stats.cmd_time_begun;
+	spin_unlock_bh(&feci->lock);
+
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_ipv6_accel_cmd_time_avg_samples += delta;
+	ecm_nss_ipv6_accel_cmd_time_avg_set++;
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+}
+
+/*
+ * ecm_nss_ipv6_deccel_done_time_update()
+ *	Record how long the command took to complete, updating average samples
+ */
+void ecm_nss_ipv6_decel_done_time_update(struct ecm_front_end_connection_instance *feci)
+{
+	unsigned long delta;
+
+	/*
+	 * How long did it take the command to complete?
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_completed = jiffies;
+	delta = feci->stats.cmd_time_completed - feci->stats.cmd_time_begun;
+	spin_unlock_bh(&feci->lock);
+
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_ipv6_decel_cmd_time_avg_samples += delta;
+	ecm_nss_ipv6_decel_cmd_time_avg_set++;
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+}
+
+/*
+ * ecm_nss_ipv6_process_one_conn_sync_msg()
+ *	Process one connection sync message.
+ */
+static inline void ecm_nss_ipv6_process_one_conn_sync_msg(struct nss_ipv6_conn_sync *sync)
+{
+	struct nf_conntrack_tuple_hash *h;
+	struct nf_conntrack_tuple tuple;
+	struct nf_conn *ct;
+	struct nf_conn_counter *acct;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct neighbour *neigh;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	ip_addr_t flow_ip;
+	ip_addr_t return_ip;
+	struct in6_addr group6 __attribute__((unused));
+	struct in6_addr origin6 __attribute__((unused));
+	struct ecm_classifier_rule_sync class_sync;
+	int flow_dir;
+	int return_dir;
+	unsigned long int delta_jiffies;
+	int elapsed;
+
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(flow_ip, sync->flow_ip);
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(return_ip, sync->return_ip);
+
+	/*
+	 * Look up ecm connection with a view to synchronising the connection, classifier and data tracker.
+	 * Note that we use _xlate versions for destination - for egressing connections this would be the wan IP address,
+	 * but for ingressing this would be the LAN side (non-nat'ed) address and is what we need for lookup of our connection.
+	 */
+	DEBUG_INFO("%px: NSS Sync, lookup connection using\n" \
+			"Protocol: %d\n" \
+			"src_addr: " ECM_IP_ADDR_OCTAL_FMT ":%d\n" \
+			"dest_addr: " ECM_IP_ADDR_OCTAL_FMT ":%d\n",
+			sync,
+			(int)sync->protocol,
+			ECM_IP_ADDR_TO_OCTAL(flow_ip), (int)sync->flow_ident,
+			ECM_IP_ADDR_TO_OCTAL(return_ip), (int)sync->return_ident);
+
+	ci = ecm_db_connection_find_and_ref(flow_ip, return_ip, sync->protocol, (int)sync->flow_ident, (int)sync->return_ident);
+	if (!ci) {
+		DEBUG_TRACE("%px: NSS Sync: no connection\n", sync);
+		return;
+	}
+
+	DEBUG_TRACE("%px: Sync conn %px\n", sync, ci);
+
+	/*
+	 * Copy the sync data to the classifier sync structure to
+	 * update the classifiers' stats.
+	 */
+	class_sync.tx_packet_count[ECM_CONN_DIR_FLOW] = sync->flow_tx_packet_count;
+	class_sync.tx_byte_count[ECM_CONN_DIR_FLOW] = sync->flow_tx_byte_count;
+	class_sync.rx_packet_count[ECM_CONN_DIR_FLOW] = sync->flow_rx_packet_count;
+	class_sync.rx_byte_count[ECM_CONN_DIR_FLOW] = sync->flow_rx_byte_count;
+	class_sync.tx_packet_count[ECM_CONN_DIR_RETURN] = sync->return_tx_packet_count;
+	class_sync.tx_byte_count[ECM_CONN_DIR_RETURN] = sync->return_tx_byte_count;
+	class_sync.rx_packet_count[ECM_CONN_DIR_RETURN] = sync->return_rx_packet_count;
+	class_sync.rx_byte_count[ECM_CONN_DIR_RETURN] = sync->return_rx_byte_count;
+	class_sync.reason = sync->reason;
+
+	/*
+	 * Sync assigned classifiers
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: sync to: %px, type: %d\n", ci, aci, aci->type_get(aci));
+		aci->sync_to_v6(aci, &class_sync);
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Get the elapsed time since the last sync and add this elapsed time
+	 * to the conntrack's timeout while updating it. If the return value is
+	 * a negative value which means the timer is not in a valid state, just
+	 * return here and do not update the defunct timer and the conntrack.
+	 */
+	elapsed = ecm_db_connection_elapsed_defunct_timer(ci);
+	if (elapsed < 0) {
+		ecm_db_connection_deref(ci);
+		return;
+	}
+	delta_jiffies = elapsed * HZ;
+
+	/*
+	 * Keep connection alive and updated
+	 */
+	if (!ecm_db_connection_defunct_timer_touch(ci)) {
+		ecm_db_connection_deref(ci);
+		goto sync_conntrack;
+	}
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+	if (sync->flow_tx_packet_count || sync->return_tx_packet_count) {
+		DEBUG_TRACE("%px: flow_rx_packet_count: %u, flow_rx_byte_count: %u, return_rx_packet_count: %u, , return_rx_byte_count: %u\n",
+				ci, sync->flow_rx_packet_count, sync->flow_rx_byte_count, sync->return_rx_packet_count, sync->return_rx_byte_count);
+		DEBUG_TRACE("%px: flow_tx_packet_count: %u, flow_tx_byte_count: %u, return_tx_packet_count: %u, return_tx_byte_count: %u\n",
+				ci, sync->flow_tx_packet_count, sync->flow_tx_byte_count, sync->return_tx_packet_count, sync->return_tx_byte_count);
+#ifdef ECM_MULTICAST_ENABLE
+		if (ecm_ip_addr_is_multicast(return_ip)) {
+			/*
+			 * The amount of data *sent* by the ECM multicast connection 'from' side is the amount the NSS has *received* in the 'flow' direction.
+			 */
+			ecm_db_multicast_connection_data_totals_update(ci, true, sync->flow_rx_byte_count, sync->flow_rx_packet_count);
+			ecm_db_multicast_connection_data_totals_update(ci, true, sync->return_rx_byte_count, sync->return_rx_packet_count);
+			ecm_db_multicast_connection_interface_heirarchy_stats_update(ci, sync->flow_rx_byte_count, sync->flow_rx_packet_count);
+
+			/*
+			 * Update interface statistics
+			 */
+			ecm_interface_multicast_stats_update(ci, sync->flow_tx_packet_count, sync->flow_tx_byte_count, sync->flow_rx_packet_count, sync->flow_rx_byte_count,
+										sync->return_tx_packet_count, sync->return_tx_byte_count, sync->return_rx_packet_count, sync->return_rx_byte_count);
+
+			ECM_IP_ADDR_TO_NIN6_ADDR(origin6, flow_ip);
+			ECM_IP_ADDR_TO_NIN6_ADDR(group6, return_ip);
+
+			/*
+			 * Update IP multicast routing cache stats
+			 */
+			ip6mr_mfc_stats_update(&init_net, &origin6, &group6, sync->flow_rx_packet_count,
+								 sync->flow_rx_byte_count, sync->flow_rx_packet_count, sync->flow_rx_byte_count);
+		} else {
+
+			/*
+			 * The amount of data *sent* by the ECM connection 'from' side is the amount the NSS has *received* in the 'flow' direction.
+			 */
+			ecm_db_connection_data_totals_update(ci, true, sync->flow_rx_byte_count, sync->flow_rx_packet_count);
+
+			/*
+			 * The amount of data *sent* by the ECM connection 'to' side is the amount the NSS has *received* in the 'return' direction.
+			 */
+			ecm_db_connection_data_totals_update(ci, false, sync->return_rx_byte_count, sync->return_rx_packet_count);
+
+			/*
+			 * Update interface statistics
+			 */
+			ecm_interface_stats_update(ci, sync->flow_tx_packet_count, sync->flow_tx_byte_count, sync->flow_rx_packet_count, sync->flow_rx_byte_count,
+						sync->return_tx_packet_count, sync->return_tx_byte_count, sync->return_rx_packet_count, sync->return_rx_byte_count);
+		}
+
+		/*
+		 * As packets have been accelerated we have seen some action.
+		 */
+		feci->action_seen(feci);
+#else
+		/*
+		 * The amount of data *sent* by the ECM connection 'from' side is the amount the NSS has *received* in the 'flow' direction.
+		 */
+		ecm_db_connection_data_totals_update(ci, true, sync->flow_rx_byte_count, sync->flow_rx_packet_count);
+
+		/*
+		 * The amount of data *sent* by the ECM connection 'to' side is the amount the NSS has *received* in the 'return' direction.
+		 */
+		ecm_db_connection_data_totals_update(ci, false, sync->return_rx_byte_count, sync->return_rx_packet_count);
+
+		/*
+		 * As packets have been accelerated we have seen some action.
+		 */
+		feci->action_seen(feci);
+
+		/*
+		 * Update interface statistics
+		 */
+		ecm_interface_stats_update(ci, sync->flow_tx_packet_count, sync->flow_tx_byte_count, sync->flow_rx_packet_count, sync->flow_rx_byte_count,
+						sync->return_tx_packet_count, sync->return_tx_byte_count, sync->return_rx_packet_count, sync->return_rx_byte_count);
+#endif
+	}
+
+	switch(sync->reason) {
+	case NSS_IPV6_RULE_SYNC_REASON_DESTROY:
+		/*
+		 * This is the final sync from the NSS for a connection whose acceleration was
+		 * terminated by the ecm.
+		 * NOTE: We take no action here since that is performed by the destroy message ack.
+		 */
+		DEBUG_INFO("%px: ECM initiated final sync seen: %d\n", ci, sync->reason);
+		break;
+	case NSS_IPV6_RULE_SYNC_REASON_FLUSH:
+	case NSS_IPV6_RULE_SYNC_REASON_EVICT:
+		/*
+		 * NSS has ended acceleration without instruction from the ECM.
+		 */
+		DEBUG_INFO("%px: NSS Initiated final sync seen: %d\n", ci, sync->reason);
+
+		/*
+		 * NSS Decelerated the connection
+		 */
+		feci->accel_ceased(feci);
+		break;
+	default:
+		if (ecm_db_connection_is_routed_get(ci)) {
+			/*
+			 * Update the neighbour entry for source IP address
+			 */
+			neigh = ecm_interface_ipv6_neigh_get(flow_ip);
+			if (!neigh) {
+				DEBUG_WARN("Neighbour entry for " ECM_IP_ADDR_OCTAL_FMT " not found\n", ECM_IP_ADDR_TO_OCTAL(flow_ip));
+			} else {
+				if (sync->flow_tx_packet_count) {
+					DEBUG_TRACE("Neighbour entry event send for " ECM_IP_ADDR_OCTAL_FMT ": %px\n", ECM_IP_ADDR_TO_OCTAL(flow_ip), neigh);
+					neigh_event_send(neigh, NULL);
+				}
+
+				neigh_release(neigh);
+			}
+
+#ifdef ECM_MULTICAST_ENABLE
+			/*
+			 * Update the neighbour entry for destination IP address
+			 */
+			if (!ecm_ip_addr_is_multicast(return_ip)) {
+				neigh = ecm_interface_ipv6_neigh_get(return_ip);
+				if (!neigh) {
+					DEBUG_WARN("Neighbour entry for " ECM_IP_ADDR_OCTAL_FMT " not found\n", ECM_IP_ADDR_TO_OCTAL(return_ip));
+				} else {
+					if (sync->return_tx_packet_count) {
+						DEBUG_TRACE("Neighbour entry event send for " ECM_IP_ADDR_OCTAL_FMT ": %px\n", ECM_IP_ADDR_TO_OCTAL(return_ip), neigh);
+						neigh_event_send(neigh, NULL);
+					}
+
+					neigh_release(neigh);
+				}
+			}
+#else
+			/*
+			 * Update the neighbour entry for destination IP address
+			 */
+			neigh = ecm_interface_ipv6_neigh_get(return_ip);
+			if (!neigh) {
+				DEBUG_WARN("Neighbour entry for " ECM_IP_ADDR_OCTAL_FMT " not found\n", ECM_IP_ADDR_TO_OCTAL(return_ip));
+			} else {
+				if (sync->return_tx_packet_count) {
+					DEBUG_TRACE("Neighbour entry event send for " ECM_IP_ADDR_OCTAL_FMT ": %px\n", ECM_IP_ADDR_TO_OCTAL(return_ip), neigh);
+					neigh_event_send(neigh, NULL);
+				}
+
+				neigh_release(neigh);
+			}
+#endif
+		}
+	}
+
+	/*
+	 * If connection should be re-generated then we need to force a deceleration
+	 */
+	if (unlikely(ecm_db_connection_regeneration_required_peek(ci))) {
+		DEBUG_TRACE("%px: Connection generation changing, terminating acceleration", ci);
+		feci->decelerate(feci);
+	}
+
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+
+sync_conntrack:
+	;
+
+	/*
+	 * Create a tuple so as to be able to look up a conntrack connection
+	 */
+	memset(&tuple, 0, sizeof(tuple));
+	ECM_IP_ADDR_TO_NIN6_ADDR(tuple.src.u3.in6, flow_ip)
+	tuple.src.u.all = (__be16)htons(sync->flow_ident);
+	tuple.src.l3num = AF_INET6;
+
+	ECM_IP_ADDR_TO_NIN6_ADDR(tuple.dst.u3.in6, return_ip);
+	tuple.dst.dir = IP_CT_DIR_ORIGINAL;
+	tuple.dst.protonum = (uint8_t)sync->protocol;
+	tuple.dst.u.all = (__be16)htons(sync->return_ident);
+
+	DEBUG_TRACE("Conntrack sync, lookup conntrack connection using\n"
+			"Protocol: %d\n"
+			"src_addr: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"dest_addr: " ECM_IP_ADDR_OCTAL_FMT ":%d\n",
+			(int)tuple.dst.protonum,
+			ECM_IP_ADDR_TO_OCTAL(flow_ip), (int)ntohs(tuple.src.u.all),
+			ECM_IP_ADDR_TO_OCTAL(return_ip), (int)ntohs(tuple.dst.u.all));
+
+	/*
+	 * Look up conntrack connection
+	 */
+	h = nf_conntrack_find_get(&init_net, &nf_ct_zone_dflt, &tuple);
+	if (!h) {
+		DEBUG_WARN("%px: NSS Sync: no conntrack connection\n", sync);
+		return;
+	}
+
+	ct = nf_ct_tuplehash_to_ctrack(h);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0))
+	NF_CT_ASSERT(ct->timeout.data == (unsigned long)ct);
+#endif
+	DEBUG_TRACE("%px: NSS Sync: conntrack connection\n", ct);
+
+	ecm_front_end_flow_and_return_directions_get(ct, flow_ip, 6, &flow_dir, &return_dir);
+
+	/*
+	 * Only update if this is not a fixed timeout
+	 * delta_jiffies is the elapsed time since the last sync of this connection.
+	 */
+	if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) {
+		spin_lock_bh(&ct->lock);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0))
+		ct->timeout.expires += delta_jiffies;
+#else
+		ct->timeout += delta_jiffies;
+#endif
+		spin_unlock_bh(&ct->lock);
+	}
+
+	acct = nf_conn_acct_find(ct)->counter;
+	if (acct) {
+		spin_lock_bh(&ct->lock);
+		atomic64_add(sync->flow_rx_packet_count, &acct[flow_dir].packets);
+		atomic64_add(sync->flow_rx_byte_count, &acct[flow_dir].bytes);
+
+		atomic64_add(sync->return_rx_packet_count, &acct[return_dir].packets);
+		atomic64_add(sync->return_rx_byte_count, &acct[return_dir].bytes);
+		spin_unlock_bh(&ct->lock);
+	}
+
+	switch (sync->protocol) {
+	case IPPROTO_TCP:
+		spin_lock_bh(&ct->lock);
+		if (ct->proto.tcp.seen[flow_dir].td_maxwin < sync->flow_max_window) {
+			ct->proto.tcp.seen[flow_dir].td_maxwin = sync->flow_max_window;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[flow_dir].td_end - sync->flow_end) < 0) {
+			ct->proto.tcp.seen[flow_dir].td_end = sync->flow_end;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[flow_dir].td_maxend - sync->flow_max_end) < 0) {
+			ct->proto.tcp.seen[flow_dir].td_maxend = sync->flow_max_end;
+		}
+		if (ct->proto.tcp.seen[return_dir].td_maxwin < sync->return_max_window) {
+			ct->proto.tcp.seen[return_dir].td_maxwin = sync->return_max_window;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[return_dir].td_end - sync->return_end) < 0) {
+			ct->proto.tcp.seen[return_dir].td_end = sync->return_end;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[return_dir].td_maxend - sync->return_max_end) < 0) {
+			ct->proto.tcp.seen[return_dir].td_maxend = sync->return_max_end;
+		}
+		spin_unlock_bh(&ct->lock);
+		break;
+	case IPPROTO_UDP:
+		/*
+		 * In Linux connection track, UDP flow has two timeout values:
+		 * /proc/sys/net/netfilter/nf_conntrack_udp_timeout:
+		 * 	this is for uni-direction UDP flow, normally its value is 60 seconds
+		 * /proc/sys/net/netfilter/nf_conntrack_udp_timeout_stream:
+		 * 	this is for bi-direction UDP flow, normally its value is 180 seconds
+		 *
+		 * Linux will update timer of UDP flow to stream timeout once it seen packets
+		 * in reply direction. But if flow is accelerated by NSS or SFE, Linux won't
+		 * see any packets. So we have to do the same thing in our stats sync message.
+		 */
+		if (!test_bit(IPS_ASSURED_BIT, &ct->status) && acct) {
+			u_int64_t reply_pkts = atomic64_read(&acct[IP_CT_DIR_REPLY].packets);
+
+			if (reply_pkts != 0) {
+				struct nf_conntrack_l4proto *l4proto __maybe_unused;
+				unsigned int *timeouts;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0))
+				l4proto = __nf_ct_l4proto_find(AF_INET6, IPPROTO_UDP);
+				timeouts = nf_ct_timeout_lookup(&init_net, ct, l4proto);
+
+				spin_lock_bh(&ct->lock);
+				ct->timeout.expires = jiffies + timeouts[UDP_CT_REPLIED];
+				spin_unlock_bh(&ct->lock);
+#else
+				timeouts = nf_ct_timeout_lookup(ct);
+				if (!timeouts) {
+					timeouts = udp_get_timeouts(nf_ct_net(ct));
+				}
+
+				spin_lock_bh(&ct->lock);
+				ct->timeout = jiffies + timeouts[UDP_CT_REPLIED];
+				spin_unlock_bh(&ct->lock);
+#endif
+			}
+		}
+		break;
+	}
+
+	/*
+	 * Release connection
+	 */
+	nf_ct_put(ct);
+}
+
+/*
+ * ecm_nss_ipv6_net_dev_callback()
+ *	Callback handler from the NSS.
+ */
+static void ecm_nss_ipv6_net_dev_callback(void *app_data, struct nss_ipv6_msg *nim)
+{
+	struct nss_ipv6_conn_sync *sync;
+	/*
+	 * Only respond to sync messages
+	 */
+	if (nim->cm.type != NSS_IPV6_RX_CONN_STATS_SYNC_MSG) {
+		return;
+	}
+	sync = &nim->msg.conn_stats;
+	ecm_nss_ipv6_process_one_conn_sync_msg(sync);
+}
+
+/*
+ * ecm_nss_ipv6_connection_sync_many_callback()
+ *	Callback for conn_sync_many request message
+ */
+static void ecm_nss_ipv6_connection_sync_many_callback(void *app_data, struct nss_ipv6_msg *nim)
+{
+	struct nss_ipv6_conn_sync_many_msg *nicsm = &nim->msg.conn_stats_many;
+	int i;
+
+	/*
+	 * If ECM is terminating, don't process this last stats
+	 */
+	if (ecm_ipv6_terminate_pending) {
+		return;
+	}
+
+	if (nim->cm.response == NSS_CMN_RESPONSE_ACK) {
+		for (i = 0; i < nicsm->count; i++) {
+			ecm_nss_ipv6_process_one_conn_sync_msg(&nicsm->conn_sync[i]);
+		}
+		ecm_nss_ipv6_sync_req_msg->msg.conn_stats_many.index = nicsm->next;
+	} else {
+		/*
+		 * We get a NACK from FW, which should not happen, restart the request
+		 */
+		DEBUG_WARN("IPv6 conn stats request failed, restarting\n");
+		ecm_nss_ipv6_stats_request_nack++;
+		ecm_nss_ipv6_sync_req_msg->msg.conn_stats_many.index = 0;
+	}
+	queue_delayed_work(ecm_nss_ipv6_workqueue, &ecm_nss_ipv6_work, 0);
+}
+
+/*
+ * ecm_nss_ipv6_stats_sync_req_work()
+ *	Schedule delayed work to process connection stats and request next sync
+ */
+static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work)
+{
+	/*
+	 * Prepare a nss_ipv6_msg with CONN_STATS_SYNC_MANY request
+	 */
+	struct nss_ipv6_conn_sync_many_msg *nicsm_req = &ecm_nss_ipv6_sync_req_msg->msg.conn_stats_many;
+	nss_tx_status_t nss_tx_status;
+	int retry = 3;
+	unsigned long int current_jiffies;
+
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	if (ecm_nss_ipv6_accelerated_count == 0) {
+		spin_unlock_bh(&ecm_nss_ipv6_lock);
+		DEBUG_TRACE("There is no accelerated IPv6 connection\n");
+		goto reschedule;
+	}
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY);
+
+	/*
+	 * If index is 0, we are starting a new round, but if we still have time remain
+	 * in this round, sleep until it ends
+	 */
+	if (nicsm_req->index == 0) {
+		current_jiffies = jiffies;
+
+		if (time_is_after_jiffies(ecm_nss_ipv6_roll_check_jiffies))  {
+			ecm_nss_ipv6_next_req_time = jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD;
+		}
+
+		if (time_after(ecm_nss_ipv6_next_req_time, current_jiffies)) {
+			msleep(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies));
+		}
+		ecm_nss_ipv6_roll_check_jiffies = jiffies;
+		ecm_nss_ipv6_next_req_time = ecm_nss_ipv6_roll_check_jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD;
+	}
+
+	while (retry) {
+		if (ecm_ipv6_terminate_pending) {
+			return;
+		}
+		nss_tx_status = nss_ipv6_tx_with_size(ecm_nss_ipv6_nss_ipv6_mgr, ecm_nss_ipv6_sync_req_msg, PAGE_SIZE);
+		if (nss_tx_status == NSS_TX_SUCCESS) {
+			ecm_nss_ipv6_stats_request_success++;
+			return;
+		}
+		ecm_nss_ipv6_stats_request_fail++;
+		retry--;
+		DEBUG_TRACE("TX_NOT_OKAY, try again later\n");
+		usleep_range(100, 200);
+	}
+
+reschedule:
+	/*
+	 * TX failed after retries, reschedule ourselves with fresh start
+	 */
+	nicsm_req->count = 0;
+	nicsm_req->index = 0;
+	queue_delayed_work(ecm_nss_ipv6_workqueue, &ecm_nss_ipv6_work, ECM_NSS_IPV6_STATS_SYNC_PERIOD);
+}
+
+/*
+ * ecm_nss_ipv6_get_accel_limit_mode()
+ */
+static int ecm_nss_ipv6_get_accel_limit_mode(void *data, u64 *val)
+{
+	*val = ecm_nss_ipv6_accel_limit_mode;
+
+	return 0;
+}
+
+/*
+ * ecm_nss_ipv6_set_accel_limit_mode()
+ */
+static int ecm_nss_ipv6_set_accel_limit_mode(void *data, u64 val)
+{
+	DEBUG_TRACE("ecm_nss_ipv6_accel_limit_mode = %x\n", (int)val);
+
+	/*
+	 * Check that only valid bits are set.
+	 * It's fine for no bits to be set as that suggests no modes are wanted.
+	 */
+	if (val && (val ^ (ECM_FRONT_END_ACCEL_LIMIT_MODE_FIXED | ECM_FRONT_END_ACCEL_LIMIT_MODE_UNLIMITED))) {
+		DEBUG_WARN("ecm_nss_ipv6_accel_limit_mode = %x bad\n", (int)val);
+		return -EINVAL;
+	}
+
+	ecm_nss_ipv6_accel_limit_mode = (int)val;
+
+	return 0;
+}
+
+/*
+ * Debugfs attribute for accel limit mode.
+ */
+DEFINE_SIMPLE_ATTRIBUTE(ecm_nss_ipv6_accel_limit_mode_fops, ecm_nss_ipv6_get_accel_limit_mode, ecm_nss_ipv6_set_accel_limit_mode, "%llu\n");
+
+/*
+ * ecm_nss_ipv6_get_accel_cmd_average_millis()
+ */
+static ssize_t ecm_nss_ipv6_get_accel_cmd_avg_millis(struct file *file,
+								char __user *user_buf,
+								size_t sz, loff_t *ppos)
+{
+	unsigned long set;
+	unsigned long samples;
+	unsigned long avg;
+	char *buf;
+	int ret;
+
+	buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!buf) {
+		return -ENOMEM;
+	}
+
+	/*
+	 * Operate under our locks.
+	 * Compute the average of the samples taken and seed the next set of samples with the result of this one.
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	samples = ecm_nss_ipv6_accel_cmd_time_avg_samples;
+	set = ecm_nss_ipv6_accel_cmd_time_avg_set;
+	ecm_nss_ipv6_accel_cmd_time_avg_samples /= ecm_nss_ipv6_accel_cmd_time_avg_set;
+	ecm_nss_ipv6_accel_cmd_time_avg_set = 1;
+	avg = ecm_nss_ipv6_accel_cmd_time_avg_samples;
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	/*
+	 * Convert average jiffies to milliseconds
+	 */
+	avg *= 1000;
+	avg /= HZ;
+
+	ret = snprintf(buf, (ssize_t)PAGE_SIZE, "avg=%lu\tsamples=%lu\tset_size=%lu\n", avg, samples, set);
+	if (ret < 0) {
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	ret = simple_read_from_buffer(user_buf, sz, ppos, buf, ret);
+	kfree(buf);
+	return ret;
+}
+
+/*
+ * File operations for accel command average time.
+ */
+static struct file_operations ecm_nss_ipv6_accel_cmd_avg_millis_fops = {
+	.read = ecm_nss_ipv6_get_accel_cmd_avg_millis,
+};
+
+/*
+ * ecm_nss_ipv6_get_decel_cmd_average_millis()
+ */
+static ssize_t ecm_nss_ipv6_get_decel_cmd_avg_millis(struct file *file,
+								char __user *user_buf,
+								size_t sz, loff_t *ppos)
+{
+	unsigned long set;
+	unsigned long samples;
+	unsigned long avg;
+	char *buf;
+	int ret;
+
+	buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!buf) {
+		return -ENOMEM;
+	}
+
+	/*
+	 * Operate under our locks.
+	 * Compute the average of the samples taken and seed the next set of samples with the result of this one.
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	samples = ecm_nss_ipv6_decel_cmd_time_avg_samples;
+	set = ecm_nss_ipv6_decel_cmd_time_avg_set;
+	ecm_nss_ipv6_decel_cmd_time_avg_samples /= ecm_nss_ipv6_decel_cmd_time_avg_set;
+	ecm_nss_ipv6_decel_cmd_time_avg_set = 1;
+	avg = ecm_nss_ipv6_decel_cmd_time_avg_samples;
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	/*
+	 * Convert average jiffies to milliseconds
+	 */
+	avg *= 1000;
+	avg /= HZ;
+
+	ret = snprintf(buf, (ssize_t)PAGE_SIZE, "avg=%lu\tsamples=%lu\tset_size=%lu\n", avg, samples, set);
+	if (ret < 0) {
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	ret = simple_read_from_buffer(user_buf, sz, ppos, buf, ret);
+	kfree(buf);
+	return ret;
+}
+
+/*
+ * File operations for decel command average time.
+ */
+static struct file_operations ecm_nss_ipv6_decel_cmd_avg_millis_fops = {
+	.read = ecm_nss_ipv6_get_decel_cmd_avg_millis,
+};
+
+/*
+ * ecm_nss_ipv6_get_stats_request_counter()
+ */
+static ssize_t ecm_nss_ipv6_get_stats_request_counter(struct file *file,
+								char __user *user_buf,
+								size_t sz, loff_t *ppos)
+{
+	char *buf;
+	int ret;
+
+	buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!buf) {
+		return -ENOMEM;
+	}
+
+	ret = snprintf(buf, (ssize_t)PAGE_SIZE, "success=%lu\tfail=%lu\tnack=%lu\t\n",
+			ecm_nss_ipv6_stats_request_success, ecm_nss_ipv6_stats_request_fail,
+			ecm_nss_ipv6_stats_request_nack);
+	if (ret < 0) {
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	ret = simple_read_from_buffer(user_buf, sz, ppos, buf, ret);
+	kfree(buf);
+	return ret;
+}
+
+/*
+ * File operations for decel command average time.
+ */
+static struct file_operations ecm_nss_ipv6_stats_request_counter_fops = {
+	.read = ecm_nss_ipv6_get_stats_request_counter,
+};
+
+/*
+ * ecm_nss_ipv6_sync_queue_init
+ *	Initialize the workqueue for ipv6 stats sync
+ */
+static bool ecm_nss_ipv6_sync_queue_init(void)
+{
+	struct nss_ipv6_conn_sync_many_msg *nicsm;
+
+	/*
+	 * Setup the connection sync msg/work/workqueue
+	 */
+	ecm_nss_ipv6_sync_req_msg = kzalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!ecm_nss_ipv6_sync_req_msg) {
+		return false;
+	}
+
+	/*
+	 * Register the conn_sync_many message callback
+	 */
+	nss_ipv6_conn_sync_many_notify_register(ecm_nss_ipv6_connection_sync_many_callback);
+
+	nss_ipv6_msg_init(ecm_nss_ipv6_sync_req_msg, NSS_IPV6_RX_INTERFACE,
+		NSS_IPV6_TX_CONN_STATS_SYNC_MANY_MSG,
+		sizeof(struct nss_ipv6_conn_sync_many_msg),
+		ecm_nss_ipv6_connection_sync_many_callback,
+		NULL);
+
+	nicsm = &ecm_nss_ipv6_sync_req_msg->msg.conn_stats_many;
+
+	/*
+	 * Start with index 0 and calculate the size of the conn stats array
+	 */
+	nicsm->index = 0;
+	nicsm->size = PAGE_SIZE;
+
+	ecm_nss_ipv6_workqueue = create_singlethread_workqueue("ecm_nss_ipv6_workqueue");
+	if (!ecm_nss_ipv6_workqueue) {
+		nss_ipv6_conn_sync_many_notify_unregister();
+		kfree(ecm_nss_ipv6_sync_req_msg);
+		return false;
+	}
+	INIT_DELAYED_WORK(&ecm_nss_ipv6_work, ecm_nss_ipv6_stats_sync_req_work);
+	queue_delayed_work(ecm_nss_ipv6_workqueue, &ecm_nss_ipv6_work, ECM_NSS_IPV6_STATS_SYNC_PERIOD);
+
+	return true;
+}
+
+/*
+ * ecm_nss_ipv6_sync_queue_exit
+ *	 the workqueue for ipv6 stats sync
+ */
+static void ecm_nss_ipv6_sync_queue_exit(void)
+{
+	/*
+	 * Unregister the conn_sync_many message callback
+	 * Otherwise nss will call our callback which does not exist anymore
+	 */
+	nss_ipv6_conn_sync_many_notify_unregister();
+
+	/*
+	 * Cancel the conn sync req work and destroy workqueue
+	 */
+	cancel_delayed_work_sync(&ecm_nss_ipv6_work);
+	destroy_workqueue(ecm_nss_ipv6_workqueue);
+	kfree(ecm_nss_ipv6_sync_req_msg);
+}
+
+/*
+ * ecm_nss_ipv6_init()
+ */
+int ecm_nss_ipv6_init(struct dentry *dentry)
+{
+	int result = -1;
+
+	if (!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_NSS)) {
+		DEBUG_INFO("NSS IPv6 is disabled\n");
+		return 0;
+	}
+
+	DEBUG_INFO("ECM NSS IPv6 init\n");
+
+	ecm_nss_ipv6_dentry = debugfs_create_dir("ecm_nss_ipv6", dentry);
+	if (!ecm_nss_ipv6_dentry) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 directory in debugfs\n");
+		return result;
+	}
+
+	if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry,
+					(u32 *)&ecm_nss_ipv6_no_action_limit_default)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 no_action_limit_default file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry,
+					(u32 *)&ecm_nss_ipv6_driver_fail_limit_default)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 driver_fail_limit_default file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry,
+					(u32 *)&ecm_nss_ipv6_nack_limit_default)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 nack_limit_default file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv6_dentry,
+					(u32 *)&ecm_nss_ipv6_accelerated_count)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 accelerated_count file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv6_dentry,
+					(u32 *)&ecm_nss_ipv6_pending_accel_count)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 pending_accel_count file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv6_dentry,
+					(u32 *)&ecm_nss_ipv6_pending_decel_count)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 pending_decel_count file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry,
+					NULL, &ecm_nss_ipv6_accel_limit_mode_fops)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 accel_limit_mode file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_file("accel_cmd_avg_millis", S_IRUGO, ecm_nss_ipv6_dentry,
+					NULL, &ecm_nss_ipv6_accel_cmd_avg_millis_fops)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 accel_cmd_avg_millis file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_file("decel_cmd_avg_millis", S_IRUGO, ecm_nss_ipv6_dentry,
+					NULL, &ecm_nss_ipv6_decel_cmd_avg_millis_fops)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 decel_cmd_avg_millis file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!ecm_nss_ported_ipv6_debugfs_init(ecm_nss_ipv6_dentry)) {
+		DEBUG_ERROR("Failed to create ecm ported files in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_file("stats_request_counter", S_IRUGO, ecm_nss_ipv6_dentry,
+					NULL, &ecm_nss_ipv6_stats_request_counter_fops)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 stats_request_counter file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry,
+					(u32 *)&ecm_nss_ipv6_vlan_passthrough_enable)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 vlan passthrough file in debugfs\n");
+		goto task_cleanup;
+	}
+
+#ifdef ECM_NON_PORTED_SUPPORT_ENABLE
+	if (!ecm_nss_non_ported_ipv6_debugfs_init(ecm_nss_ipv6_dentry)) {
+		DEBUG_ERROR("Failed to create ecm non-ported files in debugfs\n");
+		goto task_cleanup;
+	}
+#endif
+
+#ifdef ECM_MULTICAST_ENABLE
+	if (!ecm_nss_multicast_ipv6_debugfs_init(ecm_nss_ipv6_dentry)) {
+		DEBUG_ERROR("Failed to create ecm multicast files in debugfs\n");
+		goto task_cleanup;
+	}
+#endif
+	/*
+	 * Register this module with the Linux NSS Network driver.
+	 * Notify manager should be registered before the netfilter hooks. Because there
+	 * is a possibility that the ECM can try to send acceleration messages to the
+	 * acceleration engine without having an acceleration engine manager.
+	 */
+	ecm_nss_ipv6_nss_ipv6_mgr = nss_ipv6_notify_register(ecm_nss_ipv6_net_dev_callback, NULL);
+
+#ifdef ECM_MULTICAST_ENABLE
+	result = ecm_nss_multicast_ipv6_init(ecm_nss_ipv6_dentry);
+	if (result < 0) {
+		DEBUG_ERROR("Failed to init ecm ipv6 multicast frontend\n");
+		goto task_cleanup_1;
+	}
+#endif
+
+	if (!ecm_nss_ipv6_sync_queue_init()) {
+		DEBUG_ERROR("Failed to create ecm ipv6 connection sync workqueue\n");
+		goto task_cleanup_2;
+	}
+
+	return 0;
+
+task_cleanup_2:
+#ifdef ECM_MULTICAST_ENABLE
+	ecm_nss_multicast_ipv6_exit();
+task_cleanup_1:
+#endif
+	nss_ipv6_notify_unregister();
+
+task_cleanup:
+	debugfs_remove_recursive(ecm_nss_ipv6_dentry);
+	return result;
+}
+
+/*
+ * ecm_nss_ipv6_exit()
+ */
+void ecm_nss_ipv6_exit(void)
+{
+	if (!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_NSS)) {
+		DEBUG_INFO("NSS IPv6 is disabled\n");
+		return;
+	}
+
+	DEBUG_INFO("ECM NSS IPv6 Module exit\n");
+
+	/*
+	 * Unregister from the Linux NSS Network driver
+	 */
+	nss_ipv6_notify_unregister();
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_nss_ipv6_dentry) {
+		debugfs_remove_recursive(ecm_nss_ipv6_dentry);
+	}
+
+#ifdef ECM_MULTICAST_ENABLE
+	ecm_nss_multicast_ipv6_exit();
+#endif
+
+	/*
+	 * Clean up the stats sync queue/work
+	 */
+	ecm_nss_ipv6_sync_queue_exit();
+}
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_ipv6.h b/qca-nss-ecm/frontends/nss/ecm_nss_ipv6.h
new file mode 100644
index 0000000..1a5d729
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_ipv6.h
@@ -0,0 +1,170 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2016, 2020 The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <nss_api_if.h>
+
+extern int ecm_nss_ipv6_no_action_limit_default;		/* Default no-action limit. */
+extern int ecm_nss_ipv6_driver_fail_limit_default;		/* Default driver fail limit. */
+extern int ecm_nss_ipv6_nack_limit_default;			/* Default nack limit. */
+extern int ecm_nss_ipv6_accelerated_count;			/* Total offloads */
+extern int ecm_nss_ipv6_pending_accel_count;			/* Total pending offloads issued to the NSS / awaiting completion */
+extern int ecm_nss_ipv6_pending_decel_count;			/* Total pending deceleration requests issued to the NSS / awaiting completion */
+
+/*
+ * Limiting the acceleration of connections.
+ *
+ * By default there is no acceleration limiting.
+ * This means that when ECM has more connections (that can be accelerated) than the acceleration
+ * engine will allow the ECM will continue to try to accelerate.
+ * In this scenario the acceleration engine will begin removal of existing rules to make way for new ones.
+ * When the accel_limit_mode is set to FIXED ECM will not permit more rules to be issued than the engine will allow.
+ */
+extern uint32_t ecm_nss_ipv6_accel_limit_mode;
+
+/*
+ * Flag to enable/disable bridge VLAN passthrough feature.
+ * By default this feature is disabled.
+ */
+extern int ecm_nss_ipv6_vlan_passthrough_enable;
+
+/*
+ * Locking of the classifier - concurrency control for file global parameters.
+ * NOTE: It is safe to take this lock WHILE HOLDING a feci->lock.  The reverse is NOT SAFE.
+ */
+extern spinlock_t ecm_nss_ipv6_lock;			/* Protect against SMP access between netfilter, events and private threaded function. */
+
+/*
+ * NSS driver linkage
+ */
+extern struct nss_ctx_instance *ecm_nss_ipv6_nss_ipv6_mgr;
+
+/*
+ * ecm_nss_ipv6_accel_pending_set()
+ *	Set pending acceleration for the connection object.
+ *
+ * Return false if the acceleration is not permitted or is already in progress.
+ */
+static inline bool ecm_nss_ipv6_accel_pending_set(struct ecm_front_end_connection_instance *feci)
+{
+	DEBUG_INFO("%px: Accel conn: %px\n", feci, feci->ci);
+
+	/*
+	 * If re-generation is required then we cannot permit acceleration
+	 */
+	if (ecm_db_connection_regeneration_required_peek(feci->ci)) {
+		DEBUG_TRACE("%px: accel %px failed - regen required\n", feci, feci->ci);
+		return false;
+	}
+
+	/*
+	 * Is connection acceleration permanently failed?
+	 */
+	spin_lock_bh(&feci->lock);
+	if (ECM_FRONT_END_ACCELERATION_FAILED(feci->accel_mode)) {
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: accel %px failed\n", feci, feci->ci);
+		return false;
+	}
+
+	/*
+	 * If acceleration mode is anything other than "not accelerated" then ignore.
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_DECEL) {
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: Ignoring wrong mode accel for conn: %px\n", feci, feci->ci);
+		return false;
+	}
+
+	/*
+	 * Do we have a fixed upper limit for acceleration?
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	if (ecm_nss_ipv6_accel_limit_mode & ECM_FRONT_END_ACCEL_LIMIT_MODE_FIXED) {
+		if ((ecm_nss_ipv6_pending_accel_count + ecm_nss_ipv6_accelerated_count) >= nss_ipv6_max_conn_count()) {
+			spin_unlock_bh(&ecm_nss_ipv6_lock);
+			spin_unlock_bh(&feci->lock);
+			DEBUG_INFO("%px: Accel limit reached, accel denied: %px\n", feci, feci->ci);
+			return false;
+		}
+	}
+
+	/*
+	 * Okay to accelerate
+	 */
+	ecm_nss_ipv6_pending_accel_count++;
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	/*
+	 * Okay connection can be set to pending acceleration
+	 */
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+	return true;
+}
+
+/*
+ * _ecm_nss_ipv6_accel_pending_clear()
+ *	Clear pending acceleration for the connection object, setting it to the desired state.
+ *
+ * Returns true if "decelerate was pending".
+ *
+ * The feci->lock AND ecm_nss_ipv6_lock must be held on entry.
+ */
+static inline bool _ecm_nss_ipv6_accel_pending_clear(struct ecm_front_end_connection_instance *feci, ecm_front_end_acceleration_mode_t mode)
+{
+	bool decel_pending;
+
+	/*
+	 * Set the mode away from its accel pending state.
+	 */
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Accel mode unexpected: %d\n", feci, feci->accel_mode);
+	feci->accel_mode = mode;
+
+	/*
+	 * Clear decelerate pending flag.
+	 * This flag is only set when we are ACCEL_PENDING -
+	 * and we are moving from that to the given mode anyway.
+	 */
+	decel_pending = feci->stats.decelerate_pending;
+	feci->stats.decelerate_pending = false;
+
+	/*
+	 * Decrement pending counter
+	 */
+	ecm_nss_ipv6_pending_accel_count--;
+	DEBUG_ASSERT(ecm_nss_ipv6_pending_accel_count >= 0, "Accel pending underflow\n");
+	return decel_pending;
+}
+
+/*
+ * ecm_nss_ipv6_accel_pending_clear()
+ *	Clear pending acceleration for the connection object, setting it to the desired state.
+ */
+static inline bool ecm_nss_ipv6_accel_pending_clear(struct ecm_front_end_connection_instance *feci, ecm_front_end_acceleration_mode_t mode)
+{
+	bool decel_pending;
+	spin_lock_bh(&feci->lock);
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	decel_pending = _ecm_nss_ipv6_accel_pending_clear(feci, mode);
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+	spin_unlock_bh(&feci->lock);
+	return decel_pending;
+}
+
+extern void ecm_nss_ipv6_accel_done_time_update(struct ecm_front_end_connection_instance *feci);
+extern void ecm_nss_ipv6_decel_done_time_update(struct ecm_front_end_connection_instance *feci);
+extern int ecm_nss_ipv6_init(struct dentry *dentry);
+extern void ecm_nss_ipv6_exit(void);
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_multicast_ipv4.c b/qca-nss-ecm/frontends/nss/ecm_nss_multicast_ipv4.c
new file mode 100644
index 0000000..7591331
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_multicast_ipv4.c
@@ -0,0 +1,2795 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2022, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/sysctl.h>
+#include <linux/kthread.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/pkt_sched.h>
+#include <linux/debugfs.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/addrconf.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/mroute.h>
+#include <linux/vmalloc.h>
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+#include <net/vxlan.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * General operational control
+ */
+int ecm_front_end_ipv4_mc_stopped = 0;	/* When non-zero further traffic will not be processed */
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_MULTICAST_IPV4_DEBUG_LEVEL
+
+#include <nss_api_if.h>
+#include <mc_ecm.h>
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#include "ecm_nss_ipv4.h"
+#include "ecm_nss_multicast_ipv4.h"
+#include "ecm_nss_common.h"
+#include "ecm_front_end_common.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_NSS_MULTICAST_IPV4_CONNECTION_INSTANCE_MAGIC 0xED12
+
+/*
+ * struct ecm_nss_ipv4_multicast_connection_instance
+ *	A connection specific front end instance for MULTICAST connections
+ */
+struct ecm_nss_multicast_ipv4_connection_instance {
+	struct ecm_front_end_connection_instance base;		/* Base class */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+static int ecm_nss_multicast_ipv4_accelerated_count = 0;
+						/* Array of Number of TCP and UDP connections currently offloaded */
+
+/*
+ * ecm_nss_multicast_ipv4_connection_update_callback()
+ * 	Callback for handling Ack/Nack for update accelerate rules
+ */
+static void ecm_nss_multicast_ipv4_connection_update_callback(void *app_data, struct nss_ipv4_msg *nim)
+{
+	struct nss_ipv4_mc_rule_create_msg *nircm = &nim->msg.mc_rule_create;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_nss_multicast_ipv4_connection_instance *nmci;
+
+	/*TODO: If the response is NACK then decelerate the flow and flushes all rules */
+	DEBUG_TRACE("%px: update callback, response received from FW : %u\n", nim, nim->cm.response);
+
+	/*
+	 * Is this a response to a create message?
+	 */
+	if (nim->cm.type != NSS_IPV4_TX_CREATE_MC_RULE_MSG) {
+		DEBUG_ERROR("%px: multicast update callback with improper type: %d, serial: %u\n", nim, nim->cm.type, serial);
+		return;
+	}
+
+	/*
+	 * Is this a response to a update rule message?
+	 */
+	if ( !(nircm->rule_flags & NSS_IPV4_MC_RULE_CREATE_FLAG_MC_UPDATE)) {
+		DEBUG_ERROR("%px: multicast update callback with improper type: %d, serial: %u\n", nim, nim->cm.type, serial);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: multicast update callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	nmci = (struct ecm_nss_multicast_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: Update accelerate response for connection: %px, serial: %u\n", nmci, feci->ci, serial);
+	DEBUG_TRACE("%px: valid_flags: %x\n", nmci, nircm->valid_flags);
+	DEBUG_TRACE("%px: flow_ip: %pI4h:%d\n", nmci, &nircm->tuple.flow_ip, nircm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: %pI4h:%d\n", nmci, &nircm->tuple.return_ip, nircm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", nmci, nircm->tuple.protocol);
+
+	/*
+	 * Release the connection.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+	return;
+}
+
+/*
+ * ecm_nss_multicast_ipv4_connection_create_callback()
+ * 	callback for handling create ack/nack calls for multicast create commands.
+ */
+static void ecm_nss_multicast_ipv4_connection_create_callback(void *app_data, struct nss_ipv4_msg *nim)
+{
+	struct nss_ipv4_mc_rule_create_msg *__attribute__((unused))nircm = &nim->msg.mc_rule_create;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_nss_multicast_ipv4_connection_instance *nmci;
+	ecm_front_end_acceleration_mode_t result_mode;
+	bool is_defunct = false;
+
+	/*
+	 * Is this a response to a create message?
+	 */
+	if (nim->cm.type != NSS_IPV4_TX_CREATE_MC_RULE_MSG) {
+		DEBUG_ERROR("%px: udp create callback with improper type: %d, serial: %u\n", nim, nim->cm.type, serial);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: create callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	nmci = (struct ecm_nss_multicast_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: accelerate response for connection: %px, serial: %u\n", nmci, feci->ci, serial);
+	DEBUG_TRACE("%px: valid_flags: %x\n", nmci, nircm->valid_flags);
+	DEBUG_TRACE("%px: flow_ip: %pI4h:%d\n", nmci, &nircm->tuple.flow_ip, nircm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: %pI4h:%d\n", nmci, &nircm->tuple.return_ip, nircm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", nmci, nircm->tuple.protocol);
+
+	/*
+	 * Handle the creation result code.
+	 */
+	DEBUG_TRACE("%px: response: %d\n", nmci, nim->cm.response);
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		/*
+		 * Creation command failed (specific reason ignored).
+		 */
+		DEBUG_TRACE("%px: accel nack: %d\n", nmci, nim->cm.error);
+		spin_lock_bh(&feci->lock);
+		DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+		nmci->base.stats.ae_nack++;
+		nmci->base.stats.ae_nack_total++;
+		if (nmci->base.stats.ae_nack >= nmci->base.stats.ae_nack_limit) {
+			/*
+			 * Too many NSS rejections
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_ACCEL_ENGINE;
+		} else {
+			/*
+			 * Revert to decelerated
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+		}
+
+		/*
+		 * If connection is now defunct then set mode to ensure no further accel attempts occur
+		 */
+		if (feci->is_defunct) {
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT;
+		}
+
+		spin_lock_bh(&ecm_nss_ipv4_lock);
+		_ecm_nss_ipv4_accel_pending_clear(feci, result_mode);
+		spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+
+	/*
+	 * If a flush occured before we got the ACK then our acceleration was effectively cancelled on us
+	 * GGG TODO This is a workaround for a NSS message OOO quirk, this should eventually be removed.
+	 */
+	if (nmci->base.stats.flush_happened) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+		nmci->base.stats.flush_happened = false;
+
+		/*
+		 * We are decelerated, clear any pending flag as that is meaningless now.
+		 */
+		nmci->base.stats.decelerate_pending = false;
+
+		/*
+		 * Increement the no-action counter.  Our connectin was decelerated on us with no action occurring.
+		 */
+		nmci->base.stats.no_action_seen++;
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	/*
+	 * Create succeeded
+	 */
+
+	/*
+	 * Clear any nack count
+	 */
+	nmci->base.stats.ae_nack = 0;
+
+	/*
+	 * Clear the "accelerate pending" state and move to "accelerated" state bumping
+	 * the accelerated counters to match our new state.
+	 *
+	 * Decelerate may have been attempted while we were accel pending.
+	 * If decelerate is pending then we need to begin deceleration :-(
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+
+	ecm_nss_multicast_ipv4_accelerated_count++;	/* Protocol specific counter */
+	ecm_nss_ipv4_accelerated_count++;		/* General running counter */
+
+	if (!_ecm_nss_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_ACCEL)) {
+		/*
+		 * Increement the no-action counter, this is reset if offload action is seen
+		 */
+		nmci->base.stats.no_action_seen++;
+
+		spin_unlock_bh(&ecm_nss_ipv4_lock);
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_INFO("%px: Decelerate was pending\n", ci);
+
+	/*
+	 * Check if the pending decelerate was done with the defunct process.
+	 * If it was, set the is_defunct flag of the feci to false for re-try.
+	 */
+	if (feci->is_defunct) {
+		is_defunct = feci->is_defunct;
+		feci->is_defunct = false;
+	}
+
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * If the pending decelerate was done through defunct process, we should
+	 * re-try it here with the same defunct function, because the purpose of that
+	 * process is to remove the connection from the database as well after decelerating it.
+	 */
+	if (is_defunct) {
+		ecm_db_connection_make_defunct(ci);
+	} else {
+		feci->decelerate(feci);
+	}
+
+	/*
+	 * Release the connection.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_nss_multicast_ipv4_connection_update_accelerate()
+ * 	Push destination interface list updates for a multicast connection
+ * 	to NSS
+ *
+ * 	This function receives a list of interfaces that have either left or joined the connection,
+ * 	and sends a 'multicast update' command to NSS to inform about these interface state changes.
+ */
+static int ecm_nss_multicast_ipv4_connection_update_accelerate(struct ecm_front_end_connection_instance *feci,
+							       struct ecm_multicast_if_update *rp,
+							       struct ecm_classifier_process_response *pr)
+{
+	struct ecm_nss_multicast_ipv4_connection_instance *nmci = (struct ecm_nss_multicast_ipv4_connection_instance *)feci;
+	uint16_t regen_occurrances;
+	struct ecm_db_iface_instance *to_ifaces;
+	struct ecm_db_iface_instance *ii_temp;
+	struct ecm_db_iface_instance *ii_single;
+	struct ecm_db_iface_instance **ifaces;
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *from_nss_iface;
+	struct nss_ipv4_mc_rule_create_msg *create;
+	struct nss_ipv4_msg *nim;
+	ip_addr_t addr;
+	int32_t *to_ifaces_first;
+	int32_t *to_ii_first;
+	int32_t vif;
+	int32_t ret;
+	int32_t valid_vif_idx = 0;
+	int32_t from_ifaces_first;
+	int32_t to_nss_iface_id = 0;
+	int32_t from_nss_iface_id = 0;
+	uint8_t to_nss_iface_address[ETH_ALEN];
+	nss_tx_status_t nss_tx_status;
+	int32_t list_index;
+	int32_t to_mtu = 0;
+	int from_iface_bridge_identifier = 0;
+	int to_iface_bridge_identifier = 0;
+	int32_t interface_type_counts[ECM_DB_IFACE_TYPE_COUNT];
+	bool rule_invalid;
+	uint8_t dest_mac[ETH_ALEN];
+
+	DEBUG_INFO("%px: Accel conn: %px\n", nmci, feci->ci);
+
+	/*
+	 * Get the re-generation occurrance counter of the connection.
+	 * We compare it again at the end - to ensure that the rule construction has seen no generation
+	 * changes during rule creation.
+	 */
+	regen_occurrances = ecm_db_connection_regeneration_occurrances_get(feci->ci);
+
+	nim = (struct nss_ipv4_msg *)kzalloc(sizeof(struct nss_ipv4_msg), GFP_ATOMIC | __GFP_NOWARN);
+	if (!nim) {
+		return -1;
+	}
+
+	nss_ipv4_msg_init(nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_CREATE_MC_RULE_MSG,
+			sizeof(struct nss_ipv4_mc_rule_create_msg),
+			ecm_nss_multicast_ipv4_connection_update_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	create = &nim->msg.mc_rule_create;
+
+	/*
+	 * Construct an accel command.
+	 */
+	ret = ecm_db_multicast_connection_to_interfaces_get_and_ref_all(feci->ci, &to_ifaces, &to_ifaces_first);
+	if (ret == 0) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in to_interfaces list!\n", nmci);
+		kfree(nim);
+		return -1;
+	}
+
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in from_interfaces list!\n", nmci);
+		ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+		kfree(nim);
+		return -1;
+	}
+
+	create->ingress_vlan_tag[0] =   ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	create->ingress_vlan_tag[1] =   ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+
+	/*
+	 * Set the source NSS interface identifier
+	 */
+	from_nss_iface = from_ifaces[from_ifaces_first];
+	from_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(from_nss_iface);
+	if (from_nss_iface_id < 0) {
+                DEBUG_TRACE("%px: from_nss_iface_id: %d\n", nmci, from_nss_iface_id);
+		spin_lock_bh(&feci->lock);
+		if (feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL) {
+			feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_NO_ACTION;
+		}
+		spin_unlock_bh(&feci->lock);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+		kfree(nim);
+		return -1;
+        }
+
+	create->src_interface_num = from_nss_iface_id;
+	from_nss_iface = from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1];
+	from_iface_bridge_identifier = ecm_db_iface_interface_identifier_get(from_nss_iface);
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+
+	/*
+	 * Now examine the TO / DEST heirarchy list to construct the destination interface
+	 * information
+	 */
+	DEBUG_TRACE("%px: Examine to/dest heirarchy list\n", nmci);
+	rule_invalid = false;
+
+	/*
+	 * Loop through the list of interface updates
+	 */
+	for (vif = 0; vif < ECM_DB_MULTICAST_IF_MAX; vif++) {
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		create->if_rule[vif].egress_vlan_tag[0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+		create->if_rule[vif].egress_vlan_tag[1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+#endif
+
+		/*
+		 * If there is no state change for an interface at this index,
+		 * then ignore
+		 */
+		if (!(rp->if_join_idx[vif] || rp->if_leave_idx[vif])) {
+			continue;
+		}
+
+		ii_temp = ecm_db_multicast_if_heirarchy_get(to_ifaces, vif);
+
+		/*
+		 * We have an update for this interface. Construct the interface information
+		 */
+		to_nss_iface_id = -1;
+		memset(interface_type_counts, 0, sizeof(interface_type_counts));
+		to_ii_first = ecm_db_multicast_if_first_get_at_index(to_ifaces_first, vif);
+
+		for (list_index = *to_ii_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+			struct ecm_db_iface_instance *ii;
+			ecm_db_iface_type_t ii_type;
+			char *ii_name;
+
+			ii_single = ecm_db_multicast_if_instance_get_at_index(ii_temp, list_index);
+			ifaces = (struct ecm_db_iface_instance **)ii_single;
+			ii = *ifaces;
+			ii_type = ecm_db_iface_type_get(ii);
+			ii_name = ecm_db_interface_type_to_string(ii_type);
+			DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", nmci, list_index, ii, ii_type, ii_name);
+
+			/*
+			 * Extract information from this interface type if it is applicable to the rule.
+			 * Conflicting information may cause accel to be unsupported.
+			 */
+			switch (ii_type) {
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+				struct ecm_db_interface_info_vlan vlan_info;
+#endif
+
+			case ECM_DB_IFACE_TYPE_BRIDGE:
+				DEBUG_TRACE("%px: Bridge\n", nmci);
+				if (interface_type_counts[ii_type] != 0) {
+
+					/*
+					 * Cannot cascade bridges
+					 */
+					rule_invalid = true;
+					DEBUG_TRACE("%px: Bridge - ignore additional\n", nmci);
+					break;
+				}
+				ecm_db_iface_bridge_address_get(ii, to_nss_iface_address);
+				to_iface_bridge_identifier = ecm_db_iface_interface_identifier_get(ii);
+				DEBUG_TRACE("%px: Bridge - mac: %pM\n", nmci, to_nss_iface_address);
+				break;
+			case ECM_DB_IFACE_TYPE_ETHERNET:
+				 DEBUG_TRACE("%px: Ethernet\n", nmci);
+				if (interface_type_counts[ii_type] != 0) {
+					/*
+					 * Ignore additional mac addresses, these are usually as a result of address propagation
+					 * from bridges down to ports etc.
+					 */
+					DEBUG_TRACE("%px: Ethernet - ignore additional\n", nmci);
+					break;
+				}
+
+				/*
+				 * Can only handle one MAC, the first outermost mac.
+				 */
+				ecm_db_iface_ethernet_address_get(ii, to_nss_iface_address);
+				to_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+				to_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(ii);
+				if (to_nss_iface_id < 0) {
+					DEBUG_TRACE("%px: to_nss_iface_id: %d\n", nmci, to_nss_iface_id);
+					ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+					kfree(nim);
+					return -1;
+			        }
+
+				DEBUG_TRACE("%px: Ethernet - mac: %pM\n", nmci, to_nss_iface_address);
+				break;
+			case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+				/*
+				 * More than one PPPoE in the list is not valid!
+				 */
+				if (interface_type_counts[ii_type] != 0) {
+					DEBUG_TRACE("%px: PPPoE - additional unsupported\n", nmci);
+					rule_invalid = true;
+					break;
+				}
+
+				/*
+				 * Set the PPPoE rule creation structure.
+				 */
+				create->if_rule[valid_vif_idx].pppoe_if_num = ecm_db_iface_ae_interface_identifier_get(ii);
+				if (create->if_rule[valid_vif_idx].pppoe_if_num < 0) {
+					DEBUG_TRACE("%px: PPPoE - acceleration engine interface (%d) is not valid\n",
+							nmci, create->if_rule[valid_vif_idx].pppoe_if_num);
+					rule_invalid = true;
+					break;
+				}
+				create->if_rule[valid_vif_idx].valid_flags |= NSS_IPV4_MC_RULE_CREATE_IF_FLAG_PPPOE_VALID;
+				DEBUG_TRACE("%px: PPPoE - exist pppoe_if_num: %d\n", nmci,
+							create->if_rule[valid_vif_idx].pppoe_if_num);
+#else
+				DEBUG_TRACE("%px: PPPoE - unsupported\n", nmci);
+				rule_invalid = true;
+#endif
+				break;
+			case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+				DEBUG_TRACE("%px: VLAN\n", nmci);
+				if (interface_type_counts[ii_type] > 1) {
+					/*
+					 * Can only support two vlans
+					 */
+					rule_invalid = true;
+					DEBUG_TRACE("%px: VLAN - additional unsupported\n", nmci);
+					break;
+				}
+				ecm_db_iface_vlan_info_get(ii, &vlan_info);
+				create->if_rule[valid_vif_idx].egress_vlan_tag[interface_type_counts[ii_type]] = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+				/*
+				 * If we have not yet got an ethernet mac then take this one (very unlikely as mac should have been propagated to the slave (outer) device
+				 */
+				if (interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET] == 0) {
+					memcpy(to_nss_iface_address, vlan_info.address, ETH_ALEN);
+					interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+					DEBUG_TRACE("%px: VLAN use mac: %pM\n", nmci, to_nss_iface_address);
+				}
+				create->if_rule[valid_vif_idx].valid_flags |= NSS_IPV4_MC_RULE_CREATE_IF_FLAG_VLAN_VALID;
+				DEBUG_TRACE("%px: vlan tag: %x\n", nmci, create->if_rule[valid_vif_idx].egress_vlan_tag[interface_type_counts[ii_type]]);
+#else
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - unsupported\n", nmci);
+#endif
+				break;
+			default:
+				DEBUG_TRACE("%px: Ignoring: %d (%s)\n", nmci, ii_type, ii_name);
+			}
+
+			/*
+			 * Seen an interface of this type
+			 */
+			interface_type_counts[ii_type]++;
+		}
+
+		if (rule_invalid) {
+			DEBUG_WARN("%px: to/dest Rule invalid\n", nmci);
+			ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+			kfree(nim);
+			return -1;
+		}
+
+		/*
+		 * Is this a valid interface?
+		 */
+		if (to_nss_iface_id != -1) {
+			bool is_bridge;
+			create->if_rule[valid_vif_idx].if_num = to_nss_iface_id;
+			create->if_rule[valid_vif_idx].if_mtu = to_mtu;
+			if (rp->if_join_idx[vif]) {
+				/*
+				 * The interface has joined the group
+				 */
+				create->if_rule[valid_vif_idx].rule_flags |= NSS_IPV4_MC_RULE_CREATE_IF_FLAG_JOIN;
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+				if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG) {
+					/*
+					 * Set primary egress VLAN tag
+					 */
+					if (pr->egress_mc_vlan_tag[vif][0] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+						create->if_rule[valid_vif_idx].egress_vlan_tag[0] = pr->egress_mc_vlan_tag[vif][0];
+						create->if_rule[valid_vif_idx].valid_flags |= NSS_IPV4_MC_RULE_CREATE_IF_FLAG_VLAN_VALID;
+
+						/*
+						 * Set secondary egress VLAN tag
+						 */
+						if (pr->egress_mc_vlan_tag[vif][1] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+							create->if_rule[valid_vif_idx].egress_vlan_tag[1] = pr->egress_mc_vlan_tag[vif][1];
+						}
+					}
+
+				}
+#endif
+			} else if (rp->if_leave_idx[vif]) {
+				/*
+				 * The interface has left the group
+				 */
+				create->if_rule[valid_vif_idx].rule_flags |= NSS_IPV4_MC_RULE_CREATE_IF_FLAG_LEAVE;
+			}
+
+			is_bridge = !ecm_db_connection_is_routed_get(feci->ci);
+
+			/*
+			 * Do not set the ROUTED flag for pure bridged interfaces
+			 */
+			if (is_bridge) {
+				uint8_t from_nss_iface_address[ETH_ALEN];
+				ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, (uint8_t *)from_nss_iface_address);
+				memcpy(create->if_rule[valid_vif_idx].if_mac, from_nss_iface_address, ETH_ALEN);
+				create->if_rule[valid_vif_idx].rule_flags |= NSS_IPV4_MC_RULE_CREATE_IF_FLAG_BRIDGE_FLOW;
+			} else {
+				create->if_rule[valid_vif_idx].rule_flags |= NSS_IPV4_MC_RULE_CREATE_IF_FLAG_ROUTED_FLOW;
+				memcpy(create->if_rule[valid_vif_idx].if_mac, to_nss_iface_address, ETH_ALEN);
+			}
+
+			valid_vif_idx++;
+		}
+	}
+
+	/*
+	 * Set number of interface updates in the update rule
+	 */
+	create->if_count = valid_vif_idx;
+
+	/*
+	 * Set the UPDATE flag
+	 */
+	create->rule_flags |= NSS_IPV4_MC_RULE_CREATE_FLAG_MC_UPDATE;
+
+	/*
+	 * Set protocol
+	 */
+	create->tuple.protocol = IPPROTO_UDP;
+
+	/*
+	 * The src_ip is where the connection established from
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(create->tuple.flow_ip, addr);
+
+	/*
+	 * The destination address is what the destination IP is translated to as it is forwarded to the next interface.
+	 * For egress this would yield the normal wan host and for ingress this would correctly NAT back to the LAN host
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(create->tuple.return_ip, addr);
+
+	/*
+	 * Same approach as above for port information
+	 */
+	create->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	create->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	/*
+	 * Destination Node(MAC) address. This address will be same for all to side intefaces
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, dest_mac);
+	memcpy(create->dest_mac, dest_mac, ETH_ALEN);
+
+	ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+
+	for (vif = 0; vif < valid_vif_idx ; vif++) {
+		DEBUG_TRACE("ACCEL UPDATE %px: UDP Accelerate connection %px\n"
+				"Rule flag: %x\n"
+				"Vif: %d\n"
+				"Protocol: %d\n"
+				"to_mtu: %u\n"
+				"from_ip: %pI4h:%d\n"
+				"to_ip: %pI4h:%d\n"
+				"to_mac: %pM\n"
+				"dest_iface_num: %u\n"
+				"out_vlan[0] %x\n"
+				"out_vlan[1] %x\n",
+				nmci,
+				feci->ci,
+				create->if_rule[vif].rule_flags,
+				vif,
+				create->tuple.protocol,
+				create->if_rule[vif].if_mtu,
+				&create->tuple.flow_ip, create->tuple.flow_ident,
+				&create->tuple.return_ip, create->tuple.return_ident,
+				create->if_rule[vif].if_mac,
+				create->if_rule[vif].if_num,
+				create->if_rule[vif].egress_vlan_tag[0],
+				create->if_rule[vif].egress_vlan_tag[1]);
+
+	}
+
+	/*
+	 * Now that the rule has been constructed we re-compare the generation occurrance counter.
+	 * If there has been a change then we abort because the rule may have been created using
+	 * unstable data - especially if another thread has begun regeneration of the connection state.
+	 * NOTE: This does not prevent a regen from being flagged immediately after this line of code either,
+	 * or while the acceleration rule is in flight to the nss.
+	 * This is only to check for consistency of rule state - not that the state is stale.
+	 */
+	if (regen_occurrances != ecm_db_connection_regeneration_occurrances_get(feci->ci)) {
+		DEBUG_INFO("%px: connection:%px regen occurred - aborting accel rule.\n", feci, feci->ci);
+		kfree(nim);
+		return -1;
+	}
+
+	/*
+	 * Ref the connection before issuing an NSS rule
+	 * This ensures that when the NSS responds to the command - which may even be immediately -
+	 * the callback function can trust the correct ref was taken for its purpose.
+	 * NOTE: remember that this will also implicitly hold the feci.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Call the rule create function
+	 */
+	nss_tx_status = nss_ipv4_tx(ecm_nss_ipv4_nss_ipv4_mgr, nim);
+	if (nss_tx_status == NSS_TX_SUCCESS) {
+		spin_lock_bh(&feci->lock);
+		nmci->base.stats.driver_fail = 0;		/* Reset */
+		spin_unlock_bh(&feci->lock);
+		kfree(nim);
+		return 0;
+	}
+
+	/*
+	 * Revert accel mode if necessary
+	 */
+	DEBUG_WARN("%px: ACCEL UPDATE attempt failed\n", nmci);
+
+	/*
+	 * Release that ref!
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	kfree(nim);
+
+	/*
+	 * TX failed
+	 */
+	spin_lock_bh(&feci->lock);
+	nmci->base.stats.driver_fail_total++;
+	nmci->base.stats.driver_fail++;
+	if (nmci->base.stats.driver_fail >= nmci->base.stats.driver_fail_limit) {
+		DEBUG_WARN("%px: Accel failed - driver fail limit\n", nmci);
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DRIVER;
+	}
+	spin_unlock_bh(&feci->lock);
+	return -1;
+}
+
+/*
+ * ecm_nss_multicast_ipv4_connection_accelerate()
+ * 	Accelerate a multicast UDP connection
+ */
+static void ecm_nss_multicast_ipv4_connection_accelerate(struct ecm_front_end_connection_instance *feci,
+                                                                        struct ecm_classifier_process_response *pr, bool is_l2_encap,
+                                                                        struct nf_conn *ct, struct sk_buff *skb)
+{
+	struct ecm_nss_multicast_ipv4_connection_instance *nmci = (struct ecm_nss_multicast_ipv4_connection_instance *)feci;
+	uint16_t regen_occurrances;
+	struct ecm_db_iface_instance *to_ifaces;
+	struct ecm_db_iface_instance *ii_temp;
+	struct ecm_db_iface_instance *ii_single;
+	struct ecm_db_iface_instance **ifaces;
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *from_nss_iface;
+	struct ecm_db_iface_instance *from_nat_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct nss_ipv4_mc_rule_create_msg *create;
+	struct nss_ipv4_msg *nim;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int32_t *to_ifaces_first;
+	int32_t *to_ii_first;
+	int32_t from_ifaces_first;
+	int32_t from_nss_iface_id;
+	uint32_t from_nat_ifaces_first;
+	int32_t to_nss_iface_id;
+	int32_t from_nat_ifaces_identifier = 0;
+	uint8_t to_nss_iface_address[ETH_ALEN];
+	ip_addr_t addr;
+	int from_iface_bridge_identifier = 0;
+	int to_iface_bridge_identifier = 0;
+	int aci_index;
+	int vif;
+	int ret;
+	int assignment_count;
+	nss_tx_status_t nss_tx_status;
+	int32_t list_index;
+	int32_t valid_vif_idx = 0;
+	int32_t interface_type_counts[ECM_DB_IFACE_TYPE_COUNT];
+	uint8_t dest_mac[ETH_ALEN];
+	bool rule_invalid;
+	ecm_front_end_acceleration_mode_t result_mode;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	/*
+	 * Get the re-generation occurrance counter of the connection.
+	 * We compare it again at the end - to ensure that the rule construction has seen no generation
+	 * changes during rule creation.
+	 */
+	regen_occurrances = ecm_db_connection_regeneration_occurrances_get(feci->ci);
+
+	/*
+	 * Can this connection be accelerated at all?
+	 */
+	if (!ecm_nss_ipv4_accel_pending_set(feci)) {
+		DEBUG_TRACE("%px: Acceleration denied: %px\n", feci, feci->ci);
+		return;
+	}
+
+	/*
+	 * Construct an accel command.
+	 * Initialise Multicast create structure.
+	 * NOTE: We leverage the app_data void pointer to be our 32 bit connection serial number.
+	 * When we get it back we re-cast it to a uint32 and do a faster connection lookup.
+	 */
+	nim = (struct nss_ipv4_msg *)kzalloc(sizeof(struct nss_ipv4_msg), GFP_ATOMIC | __GFP_NOWARN);
+	if (!nim) {
+		return;
+	}
+
+	nss_ipv4_msg_init(nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_CREATE_MC_RULE_MSG,
+			sizeof(struct nss_ipv4_mc_rule_create_msg),
+			 ecm_nss_multicast_ipv4_connection_create_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	create = &nim->msg.mc_rule_create;
+
+	/*
+	 * Populate the multicast creation structure
+	 */
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in from_interfaces list!\n", nmci);
+		kfree(nim);
+		return;
+	}
+
+	create->ingress_vlan_tag[0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	create->ingress_vlan_tag[1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	from_nss_iface = from_ifaces[from_ifaces_first];
+	from_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(from_nss_iface);
+	if (from_nss_iface_id < 0) {
+                DEBUG_TRACE("%px: from_nss_iface_id: %d\n", nmci, from_nss_iface_id);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		kfree(nim);
+		return;
+        }
+
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = from_ifaces_first; list_index < ECM_DB_IFACE_HEIRARCHY_MAX; list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+
+		ii = from_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", nmci, list_index, ii, ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			struct ecm_db_interface_info_vlan vlan_info;
+#endif
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", nmci);
+			from_iface_bridge_identifier = ecm_db_iface_interface_identifier_get(ii);
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", nmci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", nmci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			create->ingress_vlan_tag[interface_type_counts[ii_type]] = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+			create->valid_flags |= NSS_IPV4_MC_RULE_CREATE_FLAG_INGRESS_VLAN_VALID;
+			DEBUG_TRACE("%px: vlan tag: %x\n", nmci, create->ingress_vlan_tag[interface_type_counts[ii_type]]);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", nmci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", nmci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * Set the PPPoE rule creation structure.
+			 */
+			create->valid_flags |= NSS_IPV4_MC_RULE_CREATE_FLAG_INGRESS_PPPOE;
+			DEBUG_TRACE("%px: PPPoE - ingress interface is valid\n", nmci);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", nmci, ii_type, ii_name);
+		}
+		interface_type_counts[ii_type]++;
+	}
+
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+
+	ret = ecm_db_multicast_connection_to_interfaces_get_and_ref_all(feci->ci, &to_ifaces, &to_ifaces_first);
+	if (!ret) {
+		DEBUG_WARN("%px: Accel attempt failed - no multicast interfaces in to_interfaces list!\n", nmci);
+		kfree(nim);
+		return;
+	}
+
+	from_nat_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, from_nat_ifaces, ECM_DB_OBJ_DIR_FROM_NAT);
+	from_nat_ifaces_identifier = ecm_db_iface_interface_identifier_get(from_nat_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1]);
+	ecm_db_connection_interfaces_deref(from_nat_ifaces, from_nat_ifaces_first);
+	rule_invalid = false;
+
+	/*
+	 * Now examine the TO / DEST heirarchy list to construct the destination part of the rule
+	 */
+	DEBUG_TRACE("%px: Examine to/dest heirarchy list\n", nmci);
+	for (vif = 0; vif < ECM_DB_MULTICAST_IF_MAX; vif++) {
+		int32_t found_nat_ii_match = 0;
+		int32_t to_mtu = 0;
+
+		to_nss_iface_id = -1;
+
+		create->if_rule[vif].egress_vlan_tag[0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+		create->if_rule[vif].egress_vlan_tag[1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+
+		ii_temp = ecm_db_multicast_if_heirarchy_get(to_ifaces, vif);
+		to_ii_first = ecm_db_multicast_if_first_get_at_index(to_ifaces_first, vif);
+		memset(interface_type_counts, 0, sizeof(interface_type_counts));
+
+		for (list_index = *to_ii_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+			struct ecm_db_iface_instance *ii;
+			int32_t ii_identifier;
+			ecm_db_iface_type_t ii_type;
+			char *ii_name;
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			struct ecm_db_interface_info_vlan vlan_info;
+			struct net_device *vlan_out_dev = NULL;
+			uint32_t vlan_prio = 0;
+#endif
+
+			ii_single = ecm_db_multicast_if_instance_get_at_index(ii_temp, list_index);
+			ifaces = (struct ecm_db_iface_instance **)ii_single;
+			ii = *ifaces;
+			ii_type = ecm_db_iface_type_get(ii);
+			ii_name = ecm_db_interface_type_to_string(ii_type);
+			ii_identifier = ecm_db_iface_interface_identifier_get(ii);
+
+			/*
+			 * Find match for NAT interface in Multicast destination interface list.
+			 * If found match, set the found_nat_ii_match flag here.
+			 */
+			if (ii_identifier == from_nat_ifaces_identifier) {
+				found_nat_ii_match = 1;
+			}
+
+			DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", nmci, list_index, ii, ii_type, ii_name);
+
+			/*
+			 * Extract information from this interface type if it is applicable to the rule.
+			 * Conflicting information may cause accel to be unsupported.
+			 */
+			switch (ii_type) {
+			case ECM_DB_IFACE_TYPE_BRIDGE:
+
+				/*
+				 * TODO: Find and set the bridge/route flag for this interface
+				 */
+				DEBUG_TRACE("%px: Bridge\n", nmci);
+				if (interface_type_counts[ii_type] != 0) {
+					/*
+					 * Cannot cascade bridges
+					 */
+					rule_invalid = true;
+					DEBUG_TRACE("%px: Bridge - ignore additional\n", nmci);
+					break;
+				}
+				ecm_db_iface_bridge_address_get(ii, to_nss_iface_address);
+				to_iface_bridge_identifier = ecm_db_iface_interface_identifier_get(ii);
+				DEBUG_TRACE("%px: Bridge - mac: %pM\n", nmci, to_nss_iface_address);
+				break;
+			case ECM_DB_IFACE_TYPE_ETHERNET:
+				DEBUG_TRACE("%px: Ethernet\n", nmci);
+				if (interface_type_counts[ii_type] != 0) {
+					/*
+					 * Ignore additional mac addresses, these are usually as a result of address propagation
+					 * from bridges down to ports etc.
+					 */
+					DEBUG_TRACE("%px: Ethernet - ignore additional\n", nmci);
+					break;
+				}
+
+				/*
+				 * Can only handle one MAC, the first outermost mac.
+				 */
+				ecm_db_iface_ethernet_address_get(ii, to_nss_iface_address);
+				to_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+				to_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(ii);
+				if (to_nss_iface_id < 0) {
+					DEBUG_TRACE("%px: to_nss_iface_id: %d\n", nmci, to_nss_iface_id);
+					ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+					kfree(nim);
+					return;
+			        }
+				DEBUG_TRACE("%px: Ethernet - mac: %pM, mtu %d\n", nmci, to_nss_iface_address, to_mtu);
+				break;
+			case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+				/*
+				 * More than one PPPoE in the list is not valid!
+				 */
+				if (interface_type_counts[ii_type] != 0) {
+					DEBUG_TRACE("%px: PPPoE - additional unsupported\n", nmci);
+					rule_invalid = true;
+					break;
+				}
+
+				/*
+				 * Set the PPPoE rule creation structure.
+				 */
+				create->if_rule[valid_vif_idx].pppoe_if_num = ecm_db_iface_ae_interface_identifier_get(ii);
+				if (create->if_rule[valid_vif_idx].pppoe_if_num < 0) {
+					DEBUG_TRACE("%px: PPPoE - acceleration engine interface (%d) is not valid\n",
+							nmci, create->if_rule[valid_vif_idx].pppoe_if_num);
+					rule_invalid = true;
+					break;
+				}
+				create->if_rule[valid_vif_idx].valid_flags |= NSS_IPV4_MC_RULE_CREATE_IF_FLAG_PPPOE_VALID;
+				DEBUG_TRACE("%px: PPPoE - exist if_num: %d\n", nmci,
+							create->if_rule[valid_vif_idx].pppoe_if_num);
+#else
+				DEBUG_TRACE("%px: PPPoE - unsupported\n", nmci);
+				rule_invalid = true;
+#endif
+				break;
+			case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+				DEBUG_TRACE("%px: VLAN\n", nmci);
+				if (interface_type_counts[ii_type] > 1) {
+					/*
+					 * Can only support two vlans
+					 */
+					rule_invalid = true;
+					DEBUG_TRACE("%px: VLAN - additional unsupported\n", nmci);
+					break;
+				}
+
+				ecm_db_iface_vlan_info_get(ii, &vlan_info);
+				create->if_rule[valid_vif_idx].egress_vlan_tag[interface_type_counts[ii_type]] = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+				vlan_out_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+				if (vlan_out_dev) {
+					vlan_prio = vlan_dev_get_egress_qos_mask(vlan_out_dev, pr->flow_qos_tag);
+					create->if_rule[valid_vif_idx].egress_vlan_tag[interface_type_counts[ii_type]] |= vlan_prio;
+					dev_put(vlan_out_dev);
+					vlan_out_dev = NULL;
+				}
+
+				/*
+				 * If we have not yet got an ethernet mac then take this one (very unlikely as mac should have been propagated to the slave (outer) device
+				 */
+				if (interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET] == 0) {
+					memcpy(to_nss_iface_address, vlan_info.address, ETH_ALEN);
+					interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+					DEBUG_TRACE("%px: VLAN use mac: %pM\n", nmci, to_nss_iface_address);
+				}
+				create->if_rule[valid_vif_idx].valid_flags |= NSS_IPV4_MC_RULE_CREATE_IF_FLAG_VLAN_VALID;
+				DEBUG_TRACE("%px: vlan tag: %x\n", nmci, create->if_rule[vif].egress_vlan_tag[interface_type_counts[ii_type]]);
+#else
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - unsupported\n", nmci);
+#endif
+				break;
+			default:
+				DEBUG_TRACE("%px: Ignoring: %d (%s)\n", nmci, ii_type, ii_name);
+			}
+
+			/*
+			 * Seen an interface of this type
+			 */
+			interface_type_counts[ii_type]++;
+		}
+
+		if (rule_invalid) {
+			DEBUG_WARN("%px: to/dest Rule invalid\n", nmci);
+			ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+			kfree(nim);
+			return;
+		}
+
+		/*
+		 * Populate the interface details for a valid interface in the multicast destination
+		 * interface list.
+		 */
+		if (to_nss_iface_id != -1) {
+			uint32_t xlate_src_ip, src_ip;
+			bool is_bridge;
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM_NAT, addr);
+			ECM_IP_ADDR_TO_HIN4_ADDR(xlate_src_ip, addr);
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, addr);
+			ECM_IP_ADDR_TO_HIN4_ADDR(src_ip, addr);
+
+			/*
+			 * Set a rule for NAT if found_nat_ii_match flag is set
+			 * and source IP of packet is not matching with host IP address.
+			 */
+			if (found_nat_ii_match && (xlate_src_ip != src_ip)) {
+				create->if_rule[valid_vif_idx].xlate_src_ip = xlate_src_ip;
+				create->if_rule[valid_vif_idx].xlate_src_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM_NAT);
+				create->if_rule[valid_vif_idx].valid_flags |= NSS_IPV4_MC_RULE_CREATE_IF_FLAG_NAT_VALID;
+			} else {
+				create->if_rule[valid_vif_idx].xlate_src_ip = src_ip;
+				create->if_rule[valid_vif_idx].xlate_src_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+			}
+			create->if_rule[valid_vif_idx].rule_flags |= NSS_IPV4_MC_RULE_CREATE_IF_FLAG_JOIN;
+			create->if_rule[valid_vif_idx].if_num = to_nss_iface_id;
+			create->if_rule[valid_vif_idx].if_mtu = to_mtu;
+			is_bridge = !ecm_db_connection_is_routed_get(feci->ci);
+
+			/*
+			 * Identify if the destination interface blongs to pure bridge or routed flow.
+			 */
+			if (is_bridge) {
+				uint8_t from_nss_iface_address[ETH_ALEN];
+				ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, (uint8_t *)from_nss_iface_address);
+				memcpy(create->if_rule[valid_vif_idx].if_mac, from_nss_iface_address, ETH_ALEN);
+				create->if_rule[valid_vif_idx].rule_flags |= NSS_IPV4_MC_RULE_CREATE_IF_FLAG_BRIDGE_FLOW;
+			} else {
+				memcpy(create->if_rule[valid_vif_idx].if_mac, to_nss_iface_address, ETH_ALEN);
+				create->if_rule[valid_vif_idx].rule_flags |= NSS_IPV4_MC_RULE_CREATE_IF_FLAG_ROUTED_FLOW;
+			}
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+			if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG) {
+				/*
+				 * Set primary egress VLAN tag
+				 */
+				if (pr->egress_mc_vlan_tag[vif][0] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+					create->if_rule[valid_vif_idx].egress_vlan_tag[0] = pr->egress_mc_vlan_tag[vif][0];
+					create->if_rule[valid_vif_idx].valid_flags |= NSS_IPV4_MC_RULE_CREATE_IF_FLAG_VLAN_VALID;
+
+					/*
+					 * Set secondary egress VLAN tag
+					 */
+					if (pr->egress_mc_vlan_tag[vif][1] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+						create->if_rule[valid_vif_idx].egress_vlan_tag[1] = pr->egress_mc_vlan_tag[vif][1];
+					}
+				}
+			}
+#endif
+			valid_vif_idx++;
+		}
+	}
+
+	create->if_count = valid_vif_idx;
+	create->src_interface_num = from_nss_iface_id;
+
+	/*
+	 * Set up the flow qos tags
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+		create->qos_tag = (uint32_t)pr->flow_qos_tag;
+		create->valid_flags |= NSS_IPV4_MC_RULE_CREATE_FLAG_QOS_VALID;
+	}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+#ifdef ECM_CLASSIFIER_DSCP_IGS
+	/*
+	 * Set up ingress shaper flow qos tags.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG) {
+		create->igs_qos_tag = (uint16_t)pr->igs_flow_qos_tag;
+		create->valid_flags |= NSS_IPV4_MC_RULE_CREATE_FLAG_IGS_VALID;
+	}
+#endif
+	/*
+	 * DSCP information?
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+			create->egress_dscp = pr->flow_dscp;
+			create->valid_flags |= NSS_IPV4_MC_RULE_CREATE_FLAG_DSCP_MARKING_VALID;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+	/*
+	 * Mark the rule as E-MESH Service Prioritization valid.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW) {
+		create->rule_flags |= NSS_IPV4_MC_RULE_CREATE_FLAG_MC_EMESH_SP;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG) {
+		/*
+		 * Set ingress VLAN tag
+		 */
+		if (pr->ingress_vlan_tag[0] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+			create->ingress_vlan_tag[0] = pr->ingress_vlan_tag[0];
+			create->valid_flags |= NSS_IPV4_MC_RULE_CREATE_FLAG_INGRESS_VLAN_VALID;
+			ecm_db_multicast_tuple_set_ovs_ingress_vlan(feci->ci->ti, pr->ingress_vlan_tag);
+		}
+	}
+#endif
+
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, dest_mac);
+	memcpy(create->dest_mac, dest_mac, ETH_ALEN);
+
+	/*
+	 * Set protocol
+	 */
+	create->tuple.protocol = IPPROTO_UDP;
+
+	/*
+	 * The src_ip is where the connection established from
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(create->tuple.flow_ip, addr);
+
+	/*
+	 * The destination address is what the destination IP is translated to as it is forwarded to the next interface.
+	 * For egress this would yield the normal wan host and for ingress this would correctly NAT back to the LAN host
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(create->tuple.return_ip, addr);
+
+	/*
+	 * Same approach as above for port information
+	 */
+	create->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	create->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	/*
+	 * Sync our creation command from the assigned classifiers to get specific additional creation rules.
+	 * NOTE: These are called in ascending order of priority and so the last classifier (highest) shall
+	 * override any preceding classifiers.
+	 * This also gives the classifiers a chance to see that acceleration is being attempted.
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(feci->ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+		struct ecm_classifier_rule_create ecrc;
+		/*
+		 * NOTE: The current classifiers do not sync anything to the underlying accel engines.
+		 * In the future, if any of the classifiers wants to pass any parameter, these parameters
+		 * should be received via this object and copied to the accel engine's create object (nircm).
+		*/
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: sync from: %px, type: %d\n", nmci, aci, aci->type_get(aci));
+		aci->sync_from_v4(aci, &ecrc);
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Release the interface lists
+	 */
+	ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+
+	for (vif = 0; vif < valid_vif_idx ; vif++) {
+		DEBUG_TRACE("%px: UDP Accelerate connection %px\n"
+			"Vif: %d\n"
+			"Protocol: %d\n"
+			"to_mtu: %u\n"
+			"from_ip: %pI4h:%d\n"
+			"to_ip: %pI4h:%d\n"
+			"xlate_ip: %pI4h:%d\n"
+			"to_mac: %pM\n"
+			"dest_iface_num: %u\n"
+			"in_vlan[0] %x\n"
+			"in_vlan[1] %x\n"
+			"out_vlan[0] %x\n"
+			"out_vlan[1] %x\n",
+			nmci,
+			feci->ci,
+			vif,
+			create->tuple.protocol,
+			create->if_rule[vif].if_mtu,
+			&create->tuple.flow_ip, create->tuple.flow_ident,
+			&create->tuple.return_ip, create->tuple.return_ident,
+			&create->if_rule[vif].xlate_src_ip, create->if_rule[vif].xlate_src_ident,
+			create->if_rule[vif].if_mac,
+			create->if_rule[vif].if_num,
+			create->ingress_vlan_tag[0],
+			create->ingress_vlan_tag[1],
+			create->if_rule[vif].egress_vlan_tag[0],
+			create->if_rule[vif].egress_vlan_tag[1]);
+	}
+
+	/*
+	 * Now that the rule has been constructed we re-compare the generation occurrance counter.
+	 * If there has been a change then we abort because the rule may have been created using
+	 * unstable data - especially if another thread has begun regeneration of the connection state.
+	 * NOTE: This does not prevent a regen from being flagged immediately after this line of code either,
+	 * or while the acceleration rule is in flight to the nss.
+	 * This is only to check for consistency of rule state - not that the state is stale.
+	 * Remember that the connection is marked as "accel pending state" so if a regen is flagged immediately
+	 * after this check passes, the connection will be decelerated and refreshed very quickly.
+	 */
+	if (regen_occurrances != ecm_db_connection_regeneration_occurrances_get(feci->ci)) {
+		DEBUG_INFO("%px: connection:%px regen occurred - aborting accel rule.\n", feci, feci->ci);
+		ecm_nss_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		kfree(nim);
+		return;
+	}
+
+	/*
+	 * Ref the connection before issuing an NSS rule
+	 * This ensures that when the NSS responds to the command - which may even be immediately -
+	 * the callback function can trust the correct ref was taken for its purpose.
+	 * NOTE: remember that this will also implicitly hold the feci.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Call the rule create function
+	 */
+	nss_tx_status = nss_ipv4_tx(ecm_nss_ipv4_nss_ipv4_mgr, nim);
+	if (nss_tx_status == NSS_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		nmci->base.stats.driver_fail = 0; /* Reset */
+		spin_unlock_bh(&feci->lock);
+		kfree(nim);
+		return;
+	}
+
+	/*
+	 * Release that ref!
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * TX failed
+	 */
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: accel mode unexpected: %d\n", nmci, feci->accel_mode);
+	nmci->base.stats.driver_fail_total++;
+	nmci->base.stats.driver_fail++;
+	if (feci->stats.driver_fail >= feci->stats.driver_fail_limit) {
+		DEBUG_WARN("%px: Accel failed - driver fail limit\n", nmci);
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DRIVER;
+	} else {
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	_ecm_nss_ipv4_accel_pending_clear(feci, result_mode);
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	spin_unlock_bh(&feci->lock);
+
+	kfree(nim);
+
+	return;
+}
+
+/*
+ * ecm_nss_multicast_ipv4_connection_destroy_callback()
+ *	Callback for handling destroy ack/nack calls.
+ */
+static void ecm_nss_multicast_ipv4_connection_destroy_callback(void *app_data, struct nss_ipv4_msg *nim)
+{
+	struct nss_ipv4_rule_destroy_msg * __attribute__((unused))nirdm = &nim->msg.rule_destroy;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_nss_multicast_ipv4_connection_instance *nmci;
+
+	/*
+	 * Is this a response to a destroy message?
+	 */
+	if (nim->cm.type != NSS_IPV4_TX_DESTROY_RULE_MSG) {
+		DEBUG_ERROR("%px: ported destroy callback with improper type: %d\n", nim, nim->cm.type);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: destroy callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	nmci = (struct ecm_nss_multicast_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_nss_ipv4_decel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: decelerate response for connection: %px\n", nmci, feci->ci);
+	DEBUG_TRACE("%px: flow_ip: %pI4h:%d\n", nmci, &nirdm->tuple.flow_ip, nirdm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: %pI4h:%d\n", nmci, &nirdm->tuple.return_ip, nirdm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", nmci, nirdm->tuple.protocol);
+
+	/*
+	 * Drop decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_ipv4_pending_decel_count--;
+	DEBUG_ASSERT(ecm_nss_ipv4_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If decel is not still pending then it's possible that the NSS ended acceleration by some other reason e.g. flush
+	 * In which case we cannot rely on the response we get here.
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING) {
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connections.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_TRACE("%px: response: %d\n", nmci, nim->cm.response);
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DECEL;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	/*
+	 * If connection became defunct then set mode so that no further accel/decel attempts occur.
+	 */
+	if (feci->is_defunct) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT_SHORT;
+	}
+
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Mcast acceleration ends
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_multicast_ipv4_accelerated_count--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_nss_multicast_ipv4_accelerated_count >= 0, "Bad udp accel counter\n");
+	ecm_nss_ipv4_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_nss_ipv4_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	/*
+	 * Release the connections.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_nss_multicast_ipv4_connection_decelerate_msg_send()
+ *	Prepares and sends a decelerate message to acceleration engine.
+ */
+static bool ecm_nss_multicast_ipv4_connection_decelerate_msg_send(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_multicast_ipv4_connection_instance *nmci = (struct ecm_nss_multicast_ipv4_connection_instance *)feci;
+	struct nss_ipv4_msg nim;
+	struct nss_ipv4_rule_destroy_msg *nirdm;
+	ip_addr_t src_addr;
+	ip_addr_t group_addr;
+	nss_tx_status_t nss_tx_status;
+	bool ret;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	/*
+	 * Increment the decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_ipv4_pending_decel_count++;
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	/*
+	 * Prepare deceleration message
+	 */
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_DESTROY_RULE_MSG,
+			sizeof(struct nss_ipv4_rule_destroy_msg),
+			ecm_nss_multicast_ipv4_connection_destroy_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nirdm = &nim.msg.rule_destroy;
+	nirdm->tuple.protocol = (int32_t)ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * Get addressing information
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, src_addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(nirdm->tuple.flow_ip, src_addr);
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, group_addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(nirdm->tuple.return_ip, group_addr);
+	nirdm->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nirdm->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	DEBUG_INFO("%px: Mcast Connection %px decelerate\n"
+			"protocol: %d\n"
+			"src_ip: %pI4:%d\n"
+			"dest_ip: %pI4:%d\n",
+			nmci, feci->ci, nirdm->tuple.protocol,
+			&nirdm->tuple.flow_ip, nirdm->tuple.flow_ident,
+			&nirdm->tuple.return_ip, nirdm->tuple.return_ident);
+
+	/*
+	 * Right place to free multicast destination interfaces list.
+	 */
+	ecm_db_multicast_connection_to_interfaces_clear(feci->ci);
+
+	/*
+	 * Take a ref to the feci->ci so that it will persist until we get a response from the NSS.
+	 * NOTE: This will implicitly hold the feci too.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Destroy the NSS connection cache entry.
+	 */
+	nss_tx_status = nss_ipv4_tx(ecm_nss_ipv4_nss_ipv4_mgr, &nim);
+	if (nss_tx_status == NSS_TX_SUCCESS) {
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;			/* Reset */
+		spin_unlock_bh(&feci->lock);
+		return true;
+	}
+
+	/*
+	 * TX failed
+	 */
+	ret = ecm_front_end_destroy_failure_handle(feci);
+
+	/*
+	 * Release the ref take, NSS driver did not accept our command.
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * Could not send the request, decrement the decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_ipv4_pending_decel_count--;
+	DEBUG_ASSERT(ecm_nss_ipv4_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	return ret;
+}
+
+/*
+ * ecm_nss_multicast_ipv4_connection_decelerate()
+ *     Decelerate a connection
+ */
+static bool ecm_nss_multicast_ipv4_connection_decelerate(struct ecm_front_end_connection_instance *feci)
+{
+	/*
+	 * Check if accel mode is OK for the deceleration.
+	 */
+	spin_lock_bh(&feci->lock);
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	return ecm_nss_multicast_ipv4_connection_decelerate_msg_send(feci);
+}
+
+/*
+ * ecm_nss_multicast_ipv4_connection_defunct_callback()
+ *	Callback to be called when a Mcast connection has become defunct.
+ */
+bool ecm_nss_multicast_ipv4_connection_defunct_callback(void *arg, int *accel_mode)
+{
+	bool ret;
+	struct ecm_front_end_connection_instance *feci = (struct ecm_front_end_connection_instance *)arg;
+	struct ecm_nss_multicast_ipv4_connection_instance *nmci = (struct ecm_nss_multicast_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	spin_lock_bh(&feci->lock);
+	/*
+	 * Check if the connection can be defuncted.
+	 */
+	if (!ecm_front_end_common_connection_defunct_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+
+	/*
+	 * If none of the cases matched above, this means the connection is in the
+	 * accel mode, so we force a deceleration.
+	 * NOTE: If the mode is accel pending then the decel will be actioned when that is completed.
+	 */
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * If none of the cases matched above, this means the connection is in the
+	 * accel mode, so we force a deceleration.
+	 * NOTE: If the mode is accel pending then the decel will be actioned when that is completed.
+	 */
+	ret = ecm_nss_multicast_ipv4_connection_decelerate_msg_send(feci);
+
+	/*
+	 * Copy the accel_mode which is returned from the decelerate message function. This value
+	 * will be used in the caller to decide releasing the final reference of the connection.
+	 * But if this function reaches to here, the caller care about the ret. If ret is true,
+	 * the reference will be released regardless of the accel_mode. If ret is false, accel_mode
+	 * will be in the ACCEL state (for destroy re-try) and this state will not be used in the
+	 * caller's decision. It looks for ACCEL_FAIL states.
+	 */
+	spin_lock_bh(&feci->lock);
+	*accel_mode = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+
+	return ret;
+}
+
+/*
+ * ecm_nss_multicast_ipv4_connection_accel_state_get()
+ *	Get acceleration state
+ */
+static ecm_front_end_acceleration_mode_t ecm_nss_multicast_ipv4_connection_accel_state_get(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_multicast_ipv4_connection_instance *nmci = (struct ecm_nss_multicast_ipv4_connection_instance *)feci;
+	ecm_front_end_acceleration_mode_t state;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+	spin_lock_bh(&feci->lock);
+	state = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+	return state;
+}
+
+/*
+ * ecm_nss_multicast_ipv4_connection_action_seen()
+ *	Acceleration action / activity has been seen for this connection.
+ *
+ * NOTE: Call the action_seen() method when the NSS has demonstrated that it has offloaded some data for a connection.
+ */
+static void ecm_nss_multicast_ipv4_connection_action_seen(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_multicast_ipv4_connection_instance *nmci = (struct ecm_nss_multicast_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+	DEBUG_INFO("%px: Action seen\n", nmci);
+	spin_lock_bh(&feci->lock);
+	feci->stats.no_action_seen = 0;
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_nss_multicast_ipv4_connection_accel_ceased()
+ *	NSS has indicated that acceleration has stopped.
+ *
+ * NOTE: This is called in response to an NSS self-initiated termination of acceleration.
+ * This must NOT be called because the ECM terminated the acceleration.
+ */
+static void ecm_nss_multicast_ipv4_connection_accel_ceased(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_multicast_ipv4_connection_instance *nmci = (struct ecm_nss_multicast_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+	DEBUG_INFO("%px: accel ceased\n", nmci);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If we are in accel-pending state then the NSS has issued a flush out-of-order
+	 * with the ACK/NACK we are actually waiting for.
+	 * To work around this we record a "flush has already happened" and will action it when we finally get that ACK/NACK.
+	 * GGG TODO This should eventually be removed when the NSS honours messaging sequence.
+	 */
+	if (feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING) {
+		feci->stats.flush_happened = true;
+		feci->stats.flush_happened_total++;
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If connection is no longer accelerated by the time we get here just ignore the command
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_ACCEL) {
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If the no_action_seen counter was not reset then acceleration ended without any offload action
+	 */
+	if (feci->stats.no_action_seen) {
+		feci->stats.no_action_seen_total++;
+	}
+
+	/*
+	 * If the no_action_seen indicates successive cessations of acceleration without any offload action occuring
+	 * then we fail out this connection
+	 */
+	if (feci->stats.no_action_seen >= feci->stats.no_action_seen_limit) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_NO_ACTION;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Mcast acceleration ends
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_multicast_ipv4_accelerated_count--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_nss_multicast_ipv4_accelerated_count >= 0, "Bad Mcast accel counter\n");
+	ecm_nss_ipv4_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_nss_ipv4_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+}
+
+/*
+ * ecm_nss_multicast_ipv4_connection_ref()
+ *	Ref a connection front end instance
+ */
+static void ecm_nss_multicast_ipv4_connection_ref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_multicast_ipv4_connection_instance *nmci = (struct ecm_nss_multicast_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+	spin_lock_bh(&feci->lock);
+	feci->refs++;
+	DEBUG_TRACE("%px: nmci ref %d\n", feci, feci->refs);
+	DEBUG_ASSERT(feci->refs > 0, "%px: ref wrap\n", feci);
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_nss_multicast_ipv4_connection_deref()
+ *	Deref a connection front end instance
+ */
+static int ecm_nss_multicast_ipv4_connection_deref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_multicast_ipv4_connection_instance *nmci = (struct ecm_nss_multicast_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	spin_lock_bh(&feci->lock);
+	feci->refs--;
+	DEBUG_ASSERT(feci->refs >= 0, "%px: ref wrap\n", feci);
+
+	if (feci->refs > 0) {
+		int refs = feci->refs;
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: nmci deref %d\n", nmci, refs);
+		return refs;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * We can now destroy the instance
+	 */
+	DEBUG_TRACE("%px: nmci final\n", nmci);
+	DEBUG_CLEAR_MAGIC(nmci);
+	kfree(nmci);
+	return 0;
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_nss_multicast_ipv4_connection_state_get()
+ *	Return state of this multicast front end instance
+ */
+static int ecm_nss_multicast_ipv4_connection_state_get(struct ecm_front_end_connection_instance *feci, struct ecm_state_file_instance *sfi)
+{
+	struct ecm_nss_multicast_ipv4_connection_instance *nmci = (struct ecm_nss_multicast_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	return ecm_front_end_common_connection_state_get(feci, sfi, "nss_v4.multicast");
+}
+#endif
+
+/*
+ * ecm_nss_multicast_ipv4_bridge_update_connections()
+ * 	Update NSS with new multicast egress ports.
+ */
+static void ecm_nss_multicast_ipv4_bridge_update_connections(ip_addr_t dest_ip, struct net_device *brdev)
+{
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_db_multicast_tuple_instance *ti;
+	struct ecm_db_multicast_tuple_instance *ti_next;
+	struct ecm_multicast_if_update mc_update;
+	struct ecm_db_connection_instance *ci;
+	ip_addr_t grp_ip;
+	ip_addr_t src_ip;
+	int i, ret;
+	uint32_t mc_dst_dev[ECM_DB_MULTICAST_IF_MAX];
+	int32_t if_num;
+	uint32_t mc_flags = 0;
+	bool if_update;
+	bool is_routed;
+	struct net_device *l2_br_dev, *l3_br_dev;
+
+	ti = ecm_db_multicast_connection_get_and_ref_first(dest_ip);
+	if (!ti) {
+		DEBUG_WARN("no multicast tuple entry found. Group IP: " ECM_IP_ADDR_OCTAL_FMT , ECM_IP_ADDR_TO_OCTAL(dest_ip));
+		return;
+	}
+
+	while (ti) {
+		struct ecm_classifier_process_response aci_pr;
+
+		memset(&aci_pr, 0, sizeof(aci_pr));
+
+		/*
+		 * Get the group IP address stored in tuple_instance and match this with
+		 * the group IP received from MCS update callback.
+		 */
+		ecm_db_multicast_tuple_instance_group_ip_get(ti, grp_ip);
+		if (!ECM_IP_ADDR_MATCH(grp_ip, dest_ip)) {
+			goto find_next_tuple;
+		}
+
+		/*
+		 * Get the source IP address for this entry for the group
+		 */
+		ecm_db_multicast_tuple_instance_source_ip_get(ti, src_ip);
+
+		/*
+		 * Before querying mcs, clear the destination interface list, as we get
+		 * the interface list for each unique source IP.
+		 *
+		 * Query bridge snooper for the destination list when given the group and source
+		 * if, 	if_num < 0   mc_bridge_ipv4_get_if has encountered with some error, check for next existing tuple.
+		 * 	if_num == 0   All slaves have left the group. Deacel the flow.
+		 * 	if_num > 0   An interface has either left or joined the group. Process the leave/join interface request.
+		 */
+		memset(mc_dst_dev, 0, sizeof(mc_dst_dev));
+		if_num = mc_bridge_ipv4_get_if(brdev, htonl(src_ip[0]), htonl(dest_ip[0]), ECM_DB_MULTICAST_IF_MAX, mc_dst_dev);
+		if (if_num < 0) {
+			/*
+			 * This may a valid case when all the interfaces have left a multicast group.
+			 * In this case the MCS will return if_num 0, But we may have an oudated
+			 * interface in multicast interface hierarchy list. At next step we have to
+			 * check whether the DB instance is present or not.
+			 */
+			DEBUG_TRACE("No valid bridge slaves for the group/source\n");
+			goto find_next_tuple;
+		}
+
+		/*
+		 * Get a DB connection instance for the 5-tuple
+		 */
+		ci = ecm_db_multicast_connection_get_from_tuple(ti);
+		DEBUG_TRACE("MCS-cb: src_ip = 0x%x, dest_ip = 0x%x, Num if = %d\n", src_ip[0], dest_ip[0], if_num);
+		is_routed = ecm_db_connection_is_routed_get(ci);
+
+		/*
+		 * The source interface could have joined the group as well.
+		 * In such cases, the destination interface list returned by
+		 * the snooper would include the source interface as well.
+		 * We need to filter the source interface from the list in such cases.
+		 */
+		if (if_num > 0) {
+			if_num = ecm_interface_multicast_filter_src_interface(ci, mc_dst_dev);
+			if (if_num == ECM_DB_IFACE_HEIRARCHY_MAX) {
+				DEBUG_WARN("%px: MCS Snooper Update: no interfaces in from_interfaces list!\n", ci);
+				goto find_next_tuple;
+			}
+		}
+
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+		/*
+		 * All bridge slaves have left the group. If flow is pure bridge, decel the connection and return.
+		 * If flow is routed, let MFC callback handle this.
+		 *
+		 * If there are no routed interfaces, then decelerate. Else
+		 * we first send an update message to the firmware for the
+		 * interface that have left, before issuing a decelerate
+		 * at a later point via the MFC callback. This is because
+		 * there might be a few seconds delay before MFC issues
+		 * the delete callback
+		 *
+		 */
+		if (!is_routed) {
+			/*
+			 * L2-only multicast: Update the flow only if the flow's bridge device matches the bridge device passed by MCS.
+			 */
+			if (!if_num) {
+				/*
+				 * Decelerate the flow since there is no active ports left
+				 */
+				feci->decelerate(feci);
+				feci->deref(feci);
+				goto find_next_tuple;
+			}
+
+			/*
+			 * Decelerate the flow if the bridge device from the MCS update does not match the bridge with which flow was created.
+			 */
+			l2_br_dev = ecm_db_multicast_tuple_instance_get_l2_br_dev(ti);
+			if (!l2_br_dev) {
+				DEBUG_WARN("Not found a valid l2_br_dev in ti for bridged mc flow");
+				feci->deref(feci);
+				goto find_next_tuple;
+			}
+
+			if (l2_br_dev != brdev) {
+				DEBUG_WARN("L2 bridge device does not match the MCS update. l2_br_dev:%s brdev:%s", l2_br_dev->name, brdev->name);
+				feci->deref(feci);
+				goto find_next_tuple;
+			}
+		} else {
+			/*
+			 * Check whether the bridge for which we are processing an update,
+			 * is part of the the routed destination interface list for the flow.
+			 * The flow could be one of the below
+			 *
+			 * a. WAN (upstream) <-> br-lan (downstream)
+			 * b. WAN (upstream) <-> br-lan1(downstream), br-lan2 (downstream)
+			 */
+			int i;
+			__be32 ip_src;
+			__be32 ip_grp;
+			uint32_t dst_if_cnt;
+			uint32_t dst_dev[ECM_DB_MULTICAST_IF_MAX];
+
+			/*
+			 * If l3_br_dev is NULL then the we only need to check the ipmr destination list.
+			 */
+			l3_br_dev = ecm_db_multicast_tuple_instance_get_l3_br_dev(ti);
+			if (!l3_br_dev) {
+				goto process_ipmr_entry;
+			}
+
+			/*
+			 * 'brdev' is already part of the multicast interface list, no need to check ipmr entry.
+			 */
+			if (l3_br_dev == brdev) {
+				goto process_packet;
+			}
+
+process_ipmr_entry:
+			memset(dst_dev, 0, sizeof(dst_dev));
+			ECM_IP_ADDR_TO_NIN4_ADDR(ip_src, src_ip);
+			ECM_IP_ADDR_TO_NIN4_ADDR(ip_grp, grp_ip);
+			dst_if_cnt =  ipmr_find_mfc_entry(&init_net, ip_src, ip_grp, ECM_DB_MULTICAST_IF_MAX, dst_dev);
+			if (dst_if_cnt < 0) {
+				/*
+				 * Decelerate the flow since there is no active ports left
+				 */
+				DEBUG_WARN("Not found a valid vif count %d\n", dst_if_cnt);
+				feci->decelerate(feci);
+				feci->deref(feci);
+				goto find_next_tuple;
+			}
+
+			/*
+			 * Update should be allowed for the connection only if 'brdev' is part of ipmr destination interface list.
+			 */
+			for (i = 0; i < dst_if_cnt; i++) {
+				if (dst_dev[i] == brdev->ifindex)
+					goto process_packet;
+			}
+
+			DEBUG_WARN("brdev: %s is neither part of mcproxy configuration nor same as ingress bridge port device.\n", brdev->name);
+			feci->deref(feci);
+			goto find_next_tuple;
+		}
+
+process_packet:
+		/*
+		 * Find out changes to the destination interfaces hierarchy
+		 * of the connection. We try to find out the interfaces that
+		 * have joined new, and the existing interfaces in the list
+		 * that have left seperately.
+		 */
+		memset(&mc_update, 0, sizeof(mc_update));
+		spin_lock_bh(&ecm_nss_ipv4_lock);
+		if_update = ecm_interface_multicast_find_updates_to_iface_list(ci, &mc_update, mc_flags, true, mc_dst_dev, if_num, brdev);
+		spin_unlock_bh(&ecm_nss_ipv4_lock);
+		if (!if_update) {
+			/*
+			 * No updates to this multicast flow. Move on to the next
+			 * flow for the same group
+			 */
+			goto find_next_tuple;
+		}
+
+		DEBUG_TRACE("BRIDGE UPDATE callback ===> leave_cnt %d, join_cnt %d\n", mc_update.if_leave_cnt, mc_update.if_join_cnt);
+
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+		/*
+		 * Do we have any new interfaces that have joined?
+		 */
+		if (mc_update.if_join_cnt) {
+			struct ecm_db_iface_instance *to_list;
+			int32_t to_list_first[ECM_DB_MULTICAST_IF_MAX];
+			uint32_t if_cnt;
+			uint8_t src_node_addr[ETH_ALEN];
+			uint32_t tuple_instance_flags;
+			__be16 layer4hdr[2] = {0, 0};
+			__be16 port = 0;
+
+			to_list = (struct ecm_db_iface_instance *)kzalloc(ECM_DB_TO_MCAST_INTERFACES_SIZE, GFP_ATOMIC | __GFP_NOWARN);
+			if (!to_list) {
+				feci->deref(feci);
+				goto find_next_tuple;
+			}
+
+			/*
+			 * Initialize the hierarchy's indices for the 'to_list'
+			 * which will hold the interface hierarchies for the new joinees
+			 */
+			for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+				to_list_first[i] = ECM_DB_IFACE_HEIRARCHY_MAX;
+			}
+
+			ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_node_addr);
+
+			/*
+			 * Create the interface hierarchy list for the new interfaces. We append this list later to
+			 * the existing list of destination interfaces.
+			 */
+			port = (__be16)(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+			layer4hdr[0] = htons(port);
+			port = (__be16)(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO));
+			layer4hdr[1] = htons(port);
+
+			if_cnt = ecm_interface_multicast_heirarchy_construct_bridged(feci, to_list, brdev, src_ip, dest_ip, mc_update.if_join_cnt, mc_update.join_dev, to_list_first, src_node_addr, layer4hdr, NULL);
+			if (!if_cnt) {
+				DEBUG_WARN("Failed to obtain 'to_mcast_update' hierarchy list\n");
+				feci->decelerate(feci);
+				feci->deref(feci);
+				kfree(to_list);
+				goto find_next_tuple;
+			}
+
+			/*
+			 * Append the interface hierarchy array of the new joinees to the existing destination list
+			 */
+			ecm_db_multicast_connection_to_interfaces_update(ci, to_list, to_list_first, mc_update.if_join_idx);
+
+			/*
+			 * In Routed + Bridge mode, if there is a group leave request arrives for the last
+			 * slave of the bridge then MFC will clear ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG
+			 * in tuple_instance. If the bridge slave joins again then we need to set the flag again
+			 * in tuple_instance here.
+			 */
+			tuple_instance_flags = ecm_db_multicast_tuple_instance_flags_get(ti);
+			if (is_routed && !(tuple_instance_flags & ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG)) {
+				ecm_db_multicast_tuple_instance_flags_set(ti, ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG);
+			}
+
+			/*
+			 * De-ref the updated destination interface list
+			 */
+			for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+				if (mc_update.if_join_idx[i]) {
+					struct ecm_db_iface_instance *to_list_single;
+					struct ecm_db_iface_instance *to_list_temp[ECM_DB_IFACE_HEIRARCHY_MAX];
+
+					to_list_single = ecm_db_multicast_if_heirarchy_get(to_list, i);
+					ecm_db_multicast_copy_if_heirarchy(to_list_temp, to_list_single);
+					ecm_db_connection_interfaces_deref(to_list_temp, to_list_first[i]);
+				}
+			}
+
+			kfree(to_list);
+		} else if (mc_update.if_leave_cnt) {
+			/*
+			 * If these are the last interface set leaving the to interface
+			 * list of the connection, then decelerate the connection
+			 */
+			int mc_to_interface_count = ecm_db_multicast_connection_to_interfaces_get_count(ci);
+
+			if (mc_update.if_leave_cnt == mc_to_interface_count) {
+				DEBUG_INFO("%px: Decelerating the flow as there are no to interfaces in the multicast group: 0x%x\n", feci, dest_ip[0]);
+				feci->decelerate(feci);
+				feci->deref(feci);
+				goto find_next_tuple;
+			}
+		}
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+		/*
+		 * Verify the 'to' interface list with OVS classifier.
+		 */
+		if (ecm_front_end_is_ovs_bridge_device(brdev) &&
+			ecm_db_multicast_ovs_verify_to_list(ci, &aci_pr)) {
+			/*
+			 * We defunct the flow when the OVS returns "DENY_ACCEL" for the port.
+			 * This can happen when the first port has joined on an OVS bridge
+			 * on a flow that already exists. In this case, OVS needs to see the
+			 * packet to update the flow. So we defunct the existing rule.
+			 */
+			DEBUG_WARN("%px: Verification of the ovs 'to_list' has failed. Hence, defunct the connection: %px\n", feci, feci->ci);
+			ecm_db_connection_make_defunct(ci);
+			feci->deref(feci);
+			goto find_next_tuple;
+		}
+#endif
+		/*
+		 * Push the updates to NSS
+		 */
+		DEBUG_TRACE("%px: Update accel\n", ci);
+		if ((feci->accel_mode <= ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED) ||
+				(feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_ACCEL)) {
+			DEBUG_TRACE("%px: Ignoring wrong mode accel for conn: %px\n", feci, feci->ci);
+			feci->deref(feci);
+			goto find_next_tuple;
+		}
+
+		/*
+		 * Update the new rules in FW. If returns error decelerate the connection
+		 * and flush all ECM rules.
+		 */
+		ret = ecm_nss_multicast_ipv4_connection_update_accelerate(feci, &mc_update, &aci_pr);
+		if (ret < 0) {
+			feci->decelerate(feci);
+			feci->deref(feci);
+			goto find_next_tuple;
+		}
+
+		feci->deref(feci);
+
+		/*
+		 * Release the interfaces that may have left the connection
+		 */
+		ecm_db_multicast_connection_to_interfaces_leave(ci, &mc_update);
+
+find_next_tuple:
+		ti_next = ecm_db_multicast_connection_get_and_ref_next(ti);
+		ecm_db_multicast_connection_deref(ti);
+		ti = ti_next;
+	}
+}
+
+/*
+ * ecm_nss_multicast_ipv4_connection_instance_alloc()
+ *	Create a front end instance specific for Mcast connection
+ */
+struct ecm_nss_multicast_ipv4_connection_instance *ecm_nss_multicast_ipv4_connection_instance_alloc(
+								bool can_accel,
+								struct ecm_db_connection_instance **nci)
+{
+	struct ecm_nss_multicast_ipv4_connection_instance *nmci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_db_connection_instance *ci;
+
+	if (ecm_nss_ipv4_is_conn_limit_reached()) {
+		DEBUG_TRACE("Reached connection limit\n");
+		return NULL;
+	}
+
+	/*
+	 * Now allocate the new connection
+	 */
+	*nci = ecm_db_connection_alloc();
+	if (!*nci) {
+		DEBUG_WARN("Failed to allocate connection\n");
+		return NULL;
+	}
+
+	ci = *nci;
+
+	nmci = (struct ecm_nss_multicast_ipv4_connection_instance *)kzalloc(sizeof(struct ecm_nss_multicast_ipv4_connection_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!nmci) {
+		DEBUG_WARN("Mcast Front end alloc failed\n");
+		ecm_db_connection_deref(ci);
+		return NULL;
+	}
+
+	/*
+	 * Refs is 1 for the creator of the connection
+	 */
+	feci = (struct ecm_front_end_connection_instance *)nmci;
+	feci->refs = 1;
+	DEBUG_SET_MAGIC(nmci, ECM_NSS_MULTICAST_IPV4_CONNECTION_INSTANCE_MAGIC);
+	spin_lock_init(&feci->lock);
+
+	feci->can_accel = can_accel;
+	feci->accel_mode = (can_accel)? ECM_FRONT_END_ACCELERATION_MODE_DECEL : ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED;
+	feci->accel_engine = ECM_FRONT_END_ENGINE_NSS;
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	feci->stats.no_action_seen_limit = ecm_nss_ipv4_no_action_limit_default;
+	feci->stats.driver_fail_limit = ecm_nss_ipv4_driver_fail_limit_default;
+	feci->stats.ae_nack_limit = ecm_nss_ipv4_nack_limit_default;
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	/*
+	 * Copy reference to connection - no need to ref ci as ci maintains a ref to this instance instead (this instance persists for as long as ci does)
+	 */
+	feci->ci = ci;
+
+	feci->ip_version = 4;
+
+	/*
+	 * Populate the methods and callbacks
+	 */
+	feci->ref = ecm_nss_multicast_ipv4_connection_ref;
+	feci->deref = ecm_nss_multicast_ipv4_connection_deref;
+	feci->accelerate = ecm_nss_multicast_ipv4_connection_accelerate;
+	feci->decelerate = ecm_nss_multicast_ipv4_connection_decelerate;
+	feci->accel_state_get = ecm_nss_multicast_ipv4_connection_accel_state_get;
+	feci->action_seen = ecm_nss_multicast_ipv4_connection_action_seen;
+	feci->accel_ceased = ecm_nss_multicast_ipv4_connection_accel_ceased;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	feci->state_get = ecm_nss_multicast_ipv4_connection_state_get;
+#endif
+	feci->ae_interface_number_by_dev_get = ecm_nss_common_get_interface_number_by_dev;
+	feci->ae_interface_number_by_dev_type_get = ecm_nss_common_get_interface_number_by_dev_type;
+	feci->ae_interface_type_get = ecm_nss_common_get_interface_type;
+	feci->regenerate = ecm_nss_common_connection_regenerate;
+	feci->multicast_update = ecm_nss_multicast_ipv4_bridge_update_connections;
+
+	feci->get_stats_bitmap = ecm_nss_common_dummy_get_stats_bitmap;
+	feci->set_stats_bitmap = ecm_nss_common_dummy_set_stats_bitmap;
+
+	return nmci;
+}
+
+/*
+ * ecm_nss_multicast_ipv4_get_accelerated_count()
+ */
+ssize_t ecm_nss_multicast_ipv4_get_accelerated_count(struct device *dev,
+				  struct device_attribute *attr,
+				  char *buf)
+{
+	ssize_t count;
+	int num;
+
+	/*
+	 * Operate under our locks
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	num = ecm_nss_multicast_ipv4_accelerated_count;
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%d\n", num);
+	return count;
+}
+
+/*
+ * ecm_br_multicast_update_event_callback()
+ * 	Callback received from bridge multicast snooper module in the
+ * 	following events:
+ * 	a.) Updates to a muticast group due to IGMP JOIN/LEAVE.
+ *
+ * 	group: IP multicast group address
+ * 	brdev: bridge netdevice
+ *
+ * This function does the following:
+ * a.) Lookup the tuple_instance table to find any flows through the bridge for the group
+ * b.) Query the MCS bridge using the source and group address, to receive a list
+ *     of bridge slaves for the flow
+ * c.) Process the updates by matching the received bridge slave list with existing
+ *     destination interfaces heirarchy for the CI, and decide whether to delete an
+ *     exiting interface heirarchy or add a new heirarchy.
+ */
+static void ecm_br_multicast_update_event_callback(struct net_device *brdev, uint32_t group)
+{
+	ip_addr_t dest_ip;
+
+	DEBUG_TRACE("ecm_br_multicast_update_event_callback 0x%x, brdev: %s\n", group, brdev->name);
+
+	ECM_HIN4_ADDR_TO_IP_ADDR(dest_ip, htonl(group));
+	ecm_nss_multicast_ipv4_bridge_update_connections(dest_ip, brdev);
+}
+
+/*
+ * ecm_mfc_update_event_callback()
+ * 	Callback called by Linux kernel multicast routing module in the
+ * 	following events:
+ * 	a.) Updates to destination interface lists for a multicast route due to
+ * 	    IGMP JOIN/LEAVE
+ * 	b.) Multicast route delete event
+ *
+ * 	group: IP multicast group address
+ *	origin: IP source for the multicast route
+ *	to_dev_idx[]: Array of ifindex for destination interfaces for the route
+ *	max_to_dev: size of the array
+ *	op: UPDATE or DELETE event
+ *
+ * This function does the following:
+ * a.) Lookup the tuple_instance table to find any accelerated flows for the group/source,
+ *     and access their CI
+ * b.) Process the updates by matching the received destination interface list with existing
+ *     destination interfaces heirarchy for the CI, and decide whether to delete an
+ *     exiting interface heirarchy or add a new heirarchy.
+ */
+static void ecm_mfc_update_event_callback(__be32 group, __be32 origin, uint32_t max_to_dev, uint32_t to_dev_idx[], uint8_t op)
+{
+	struct ecm_db_connection_instance *ci;
+	struct ecm_db_multicast_tuple_instance *tuple_instance;
+	struct ecm_db_multicast_tuple_instance *tuple_instance_next;
+	struct ecm_multicast_if_update mc_update;
+	int32_t vif_cnt;
+	ip_addr_t src_ip;
+	ip_addr_t dest_ip;
+	ip_addr_t src_addr;
+	ip_addr_t grp_addr;
+	uint32_t tuple_instance_flags = 0;
+	__be16 layer4hdr[2] = {0, 0};
+	__be16 port = 0;
+
+	ECM_HIN4_ADDR_TO_IP_ADDR(src_ip, htonl(origin));
+	ECM_HIN4_ADDR_TO_IP_ADDR(dest_ip, htonl(group));
+
+	DEBUG_TRACE("origin : group " ECM_IP_ADDR_DOT_FMT ":" ECM_IP_ADDR_DOT_FMT "\n", ECM_IP_ADDR_TO_DOT(src_ip), ECM_IP_ADDR_TO_DOT(dest_ip));
+
+	/*
+	 * Access the 5-tuple information from the tuple_instance table, using the
+	 * source and group addresses
+	 */
+	tuple_instance = ecm_db_multicast_connection_find_and_ref(src_ip, dest_ip);
+	if (!tuple_instance) {
+		DEBUG_TRACE("MFC_EVENT: Tuple info is not found\n");
+		return;
+	}
+
+	switch (op) {
+	case IPMR_MFC_EVENT_UPDATE:
+	{
+		struct ecm_front_end_connection_instance *feci;
+		struct ecm_db_iface_instance *to_list;
+		struct ecm_db_iface_instance *to_list_single;
+		struct ecm_db_iface_instance *to_list_temp[ECM_DB_IFACE_HEIRARCHY_MAX];
+		uint32_t to_list_first[ECM_DB_MULTICAST_IF_MAX];
+		uint32_t i, ret;
+		uint32_t mc_flag = 0;
+		bool if_update = false;
+		bool found_br_dev = false;
+
+		/*
+		 * Find the connections belongs to the same source and group address and
+		 * apply the updates received from event handler
+		 */
+		while (tuple_instance) {
+			struct ecm_classifier_process_response aci_pr;
+
+			memset(&aci_pr, 0, sizeof(aci_pr));
+
+			/*
+			 * Get the source/group IP address for this multicast tuple and match
+			 * with the source and group IP received from the event handler. If
+			 * there is not match found jumps to the next multicast tuple.
+			 */
+			ecm_db_multicast_tuple_instance_source_ip_get(tuple_instance, src_addr);
+			ecm_db_multicast_tuple_instance_group_ip_get(tuple_instance, grp_addr);
+			if (!(ECM_IP_ADDR_MATCH(src_addr, src_ip) && ECM_IP_ADDR_MATCH(grp_addr, dest_ip))) {
+				DEBUG_TRACE("%px: Multicast tuple not matched, try next multicast tuple %d\n", tuple_instance, op);
+				goto find_next_tuple;
+			}
+
+			/*
+			 * Get the DB connection instance using the tuple_instance, ref to 'ci'
+			 * has been already taken by ecm_db_multicast_connection_find_and_ref()
+			 */
+			ci = ecm_db_multicast_connection_get_from_tuple(tuple_instance);
+			DEBUG_TRACE("%px: update the multicast flow: %px\n", ci, tuple_instance);
+
+			/*
+			 * Check if this multicast connection has a bridge
+			 * device in multicast destination interface list.
+			 */
+			tuple_instance_flags = ecm_db_multicast_tuple_instance_flags_get(tuple_instance);
+			if ((tuple_instance_flags & ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG)) {
+				mc_flag |= ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG;
+			}
+
+			memset(&mc_update, 0, sizeof(mc_update));
+			spin_lock_bh(&ecm_nss_ipv4_lock);
+
+			/*
+			 * Find out if any change in destination interfaces heirarchy
+			 * list. We try to find out the interfaces that
+			 * have joined new, and the existing interfaces in the list
+			 * that have left seperately.
+			 */
+			if_update = ecm_interface_multicast_find_updates_to_iface_list(ci, &mc_update, mc_flag, false, to_dev_idx, max_to_dev, NULL);
+			if (!if_update) {
+				spin_unlock_bh(&ecm_nss_ipv4_lock);
+				DEBUG_TRACE("%px: no update, check next multicast tuple: %px\n", ci, tuple_instance);
+				goto find_next_tuple;
+			}
+
+			found_br_dev = ecm_interface_multicast_check_for_br_dev(to_dev_idx, max_to_dev);
+			if (!found_br_dev) {
+				ecm_db_multicast_tuple_instance_flags_clear(tuple_instance, ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG);
+			}
+
+			spin_unlock_bh(&ecm_nss_ipv4_lock);
+			DEBUG_TRACE("%px: MFC update callback leave_cnt %d, join_cnt %d\n", ci, mc_update.if_leave_cnt, mc_update.if_join_cnt);
+
+			feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+			/*
+			 * Do we have any new interfaces that have joined?
+			 */
+			if (mc_update.if_join_cnt > 0) {
+				to_list = (struct ecm_db_iface_instance *)kzalloc(ECM_DB_TO_MCAST_INTERFACES_SIZE, GFP_ATOMIC | __GFP_NOWARN);
+				if (!to_list) {
+					feci->deref(feci);
+					goto find_next_tuple;
+				}
+
+				/*
+				 * Initialize the heirarchy's indices for the 'to_list'
+				 * which will hold the interface heirarchies for the new joinees
+				 */
+				for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+					to_list_first[i] = ECM_DB_IFACE_HEIRARCHY_MAX;
+				}
+
+				/*
+				 * Create the interface heirarchy list for the new interfaces. We append this list later to
+				 * the existing list of destination interfaces.
+				 */
+				port = (__be16)(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_FROM));
+				layer4hdr[0] = htons(port);
+				port = (__be16)(ecm_db_connection_port_get(ci, ECM_DB_OBJ_DIR_TO));
+				layer4hdr[1] = htons(port);
+
+				vif_cnt = ecm_interface_multicast_heirarchy_construct_routed(feci, to_list, NULL, src_ip, dest_ip, mc_update.if_join_cnt, mc_update.join_dev, to_list_first, true, layer4hdr, NULL);
+				if (vif_cnt == 0) {
+					DEBUG_WARN("Failed to obtain 'to_mcast_update' heirarchy list\n");
+					feci->decelerate(feci);
+					feci->deref(feci);
+					kfree(to_list);
+					goto find_next_tuple;
+				}
+
+				/*
+				 * Append the interface heirarchy array of the new joinees to the existing destination list
+				 */
+				ecm_db_multicast_connection_to_interfaces_update(ci, to_list, to_list_first, mc_update.if_join_idx);
+
+				/*
+				 * De-ref the updated destination interface list
+				 */
+				for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+					if (mc_update.if_join_idx[i]) {
+						to_list_single = ecm_db_multicast_if_heirarchy_get(to_list, i);
+						ecm_db_multicast_copy_if_heirarchy(to_list_temp, to_list_single);
+						ecm_db_connection_interfaces_deref(to_list_temp, to_list_first[i]);
+					}
+				}
+
+				kfree(to_list);
+			}
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+			/*
+			 * Verify the 'to' interface list with OVS classifier.
+			 */
+			if (ecm_interface_multicast_check_for_ovs_br_dev(to_dev_idx, max_to_dev) &&
+				ecm_db_multicast_ovs_verify_to_list(ci, &aci_pr)) {
+				/*
+				 * We defunct the flow when the OVS returns "DENY_ACCEL" for the port.
+				 * This can happen when the first port has joined on an OVS bridge
+				 * on a flow that already exists. In this case, OVS needs to see the
+				 * packet to update the flow. So we defunct the existing rule.
+				 */
+				DEBUG_TRACE("%px: Verification of the ovs 'to_list' has failed. Hence, defunct the connection: %px\n", feci, feci->ci);
+				ecm_db_connection_make_defunct(ci);
+				feci->deref(feci);
+				goto find_next_tuple;
+			}
+#endif
+			/*
+			 * Push the updates to NSS
+			 */
+			DEBUG_TRACE("%px: Update accel %px\n", ci, tuple_instance);
+			if ((feci->accel_mode <= ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED) ||
+					(feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_ACCEL)) {
+				DEBUG_TRACE("%px: Ignoring wrong mode accel for conn: %px\n", feci, feci->ci);
+				feci->deref(feci);
+				goto find_next_tuple;
+			}
+
+			/*
+			 * Update the new rules in FW. If returns error decelerate the connection
+			 * and flush Multicast rule.
+			 */
+			ret = ecm_nss_multicast_ipv4_connection_update_accelerate(feci, &mc_update, &aci_pr);
+			if (ret < 0) {
+				feci->decelerate(feci);
+				feci->deref(feci);
+				goto find_next_tuple;
+			}
+
+			feci->deref(feci);
+
+			/*
+			 * Release the interfaces that may have left the connection
+			 */
+			ecm_db_multicast_connection_to_interfaces_leave(ci, &mc_update);
+
+find_next_tuple:
+			/*
+			 * Move on to the next flow for the same source and group
+			 */
+			tuple_instance_next = ecm_db_multicast_connection_get_and_ref_next(tuple_instance);
+			ecm_db_multicast_connection_deref(tuple_instance);
+			tuple_instance = tuple_instance_next;
+		}
+		break;
+	}
+	case IPMR_MFC_EVENT_DELETE:
+	{
+		struct ecm_front_end_connection_instance *feci;
+
+		/*
+		 * MFC reports that the multicast connection has died.
+		 * Find the connections belongs to the same source/group address,
+		 * Decelerate connections and free the frontend instance
+		 */
+		while (tuple_instance) {
+			/*
+			 * Get the source/group IP address for this multicast tuple and match
+			 * with the source and group IP received from the event handler. If
+			 * there is not match found jumps to the next multicast tuple.
+			 */
+			ecm_db_multicast_tuple_instance_source_ip_get(tuple_instance, src_addr);
+			ecm_db_multicast_tuple_instance_group_ip_get(tuple_instance, grp_addr);
+			if (!(ECM_IP_ADDR_MATCH(src_addr, src_ip) && ECM_IP_ADDR_MATCH(grp_addr, dest_ip))) {
+				DEBUG_TRACE("%px: Multicast tuple not matched, try next tuple %d\n", tuple_instance, op);
+				tuple_instance_next = ecm_db_multicast_connection_get_and_ref_next(tuple_instance);
+				ecm_db_multicast_connection_deref(tuple_instance);
+				tuple_instance = tuple_instance_next;
+				continue;
+			}
+
+			/*
+			 * Get the DB connection instance using the tuple_instance, ref to 'ci'
+			 * has been already taken by ecm_db_multicast_connection_find_and_ref()
+			 */
+			ci = ecm_db_multicast_connection_get_from_tuple(tuple_instance);
+			DEBUG_TRACE("%px:%d delete the multicast flow: %px\n", ci, op, tuple_instance);
+
+			/*
+			 * Get the front end instance
+			 */
+			feci = ecm_db_connection_front_end_get_and_ref(ci);
+			feci->decelerate(feci);
+			feci->deref(feci);
+
+			/*
+			 * Move on to the next flow for the same source and group
+			 */
+			tuple_instance_next = ecm_db_multicast_connection_get_and_ref_next(tuple_instance);
+			ecm_db_multicast_connection_deref(tuple_instance);
+			tuple_instance = tuple_instance_next;
+		}
+		break;
+	}
+	default:
+		DEBUG_TRACE("Wrong op, shouldn't be here\n");
+		break;
+	}
+
+	return;
+}
+
+/*
+ * ecm_nss_multicast_ipv4_debugfs_init()
+ */
+bool ecm_nss_multicast_ipv4_debugfs_init(struct dentry *dentry)
+{
+	struct dentry *multicast_dentry;
+
+	multicast_dentry = debugfs_create_u32("multicast_accelerated_count", S_IRUGO, dentry,
+						&ecm_nss_multicast_ipv4_accelerated_count);
+	if (!multicast_dentry) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 multicast_accelerated_count file in debugfs\n");
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * ecm_nss_multicast_ipv4_stop()
+ */
+void ecm_nss_multicast_ipv4_stop(int num)
+{
+	ecm_front_end_ipv4_mc_stopped = num;
+}
+
+/*
+ * ecm_nss_multicast_ipv4_init()
+ * 	Register the callbacks for MCS snooper and MFC update
+ */
+int ecm_nss_multicast_ipv4_init(struct dentry *dentry)
+{
+	if (!debugfs_create_u32("ecm_nss_multicast_ipv4_stop", S_IRUGO | S_IWUSR, dentry,
+					(u32 *)&ecm_front_end_ipv4_mc_stopped)) {
+		DEBUG_ERROR("Failed to create ecm front end ipv4 mc stop file in debugfs\n");
+		return -1;
+	}
+
+	/*
+	 * Register multicast update callback to MCS snooper
+	 */
+	mc_bridge_ipv4_update_callback_register(ecm_br_multicast_update_event_callback);
+
+	/*
+	 * Register multicast update callbacks to MFC
+	 */
+	ipmr_register_mfc_event_offload_callback(ecm_mfc_update_event_callback);
+	return 0;
+}
+
+/*
+ * ecm_nss_multicast_ipv4_exit()
+ * 	De-register the callbacks for MCS snooper and MFC update
+ */
+void ecm_nss_multicast_ipv4_exit(void)
+{
+	/*
+	 * De-register multicast update callbacks to
+	 * MFC and MCS snooper
+	 */
+	ipmr_unregister_mfc_event_offload_callback();
+	mc_bridge_ipv4_update_callback_deregister();
+}
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_multicast_ipv4.h b/qca-nss-ecm/frontends/nss/ecm_nss_multicast_ipv4.h
new file mode 100644
index 0000000..124b313
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_multicast_ipv4.h
@@ -0,0 +1,25 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern struct ecm_nss_multicast_ipv4_connection_instance *ecm_nss_multicast_ipv4_connection_instance_alloc(
+								bool can_accel,
+								struct ecm_db_connection_instance **nci);
+extern bool ecm_nss_multicast_ipv4_connection_defunct_callback(void *arg, int *accel_mode);
+extern bool ecm_nss_multicast_ipv4_debugfs_init(struct dentry *dentry);
+
+extern int ecm_nss_multicast_ipv4_init(struct dentry *dentry);
+
+extern void ecm_nss_multicast_ipv4_exit(void);
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_multicast_ipv6.c b/qca-nss-ecm/frontends/nss/ecm_nss_multicast_ipv6.c
new file mode 100644
index 0000000..91d3a9d
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_multicast_ipv6.c
@@ -0,0 +1,2731 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2022 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/debugfs.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/ip6_route.h>
+#include <net/ip6_fib.h>
+#include <net/addrconf.h>
+#include <net/ipv6.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in6.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/ppp_defs.h>
+#include <linux/mroute6.h>
+#include <linux/vmalloc.h>
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv6.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv6/nf_conntrack_ipv6.h>
+#include <net/netfilter/ipv6/nf_defrag_ipv6.h>
+#include <net/vxlan.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_MULTICAST_IPV6_DEBUG_LEVEL
+
+#include <nss_api_if.h>
+#include <mc_ecm.h>
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#include "ecm_nss_ipv6.h"
+#include "ecm_nss_multicast_ipv6.h"
+#include "ecm_nss_common.h"
+#include "ecm_front_end_common.h"
+
+/*
+ * General operational control
+ */
+int ecm_front_end_ipv6_mc_stopped = 0;	/* When non-zero further traffic will not be processed */
+
+/*
+ * Magic numbers
+ */
+#define ECM_NSS_MULTICAST_IPV6_CONNECTION_INSTANCE_MAGIC 0xED13
+
+/*
+ * struct ecm_nss_ipv6_multicast_connection_instance
+ *	A connection specific front end instance for MULTICAST connections
+ */
+struct ecm_nss_multicast_ipv6_connection_instance {
+	struct ecm_front_end_connection_instance base;		/* Base class */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+static int ecm_nss_multicast_ipv6_accelerated_count = 0;
+						/* Number of IPv6 multicast connections currently offloaded */
+
+/*
+ * ecm_nss_multicast_ipv6_connection_update_callback()
+ * 	Callback for handling Ack/Nack for update accelerate rules.
+ */
+static void ecm_nss_multicast_ipv6_connection_update_callback(void *app_data, struct nss_ipv6_msg *nim)
+{
+	struct nss_ipv6_mc_rule_create_msg *nircm = &nim->msg.mc_rule_create;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_nss_multicast_ipv6_connection_instance *nmci;
+	ip_addr_t flow_ip;
+	ip_addr_t return_ip;
+
+	/*TODO: If the response is NACK then decelerate the flow and flushes all rules */
+	DEBUG_TRACE("%px: update callback, response received from FW : %u\n", nim, nim->cm.response);
+
+	/*
+	 * Is this a response to a create message?
+	 */
+	if (nim->cm.type != NSS_IPV6_TX_CREATE_MC_RULE_MSG) {
+		DEBUG_ERROR("%px: multicast update callback with improper type: %d, serial: %u\n", nim, nim->cm.type, serial);
+		return;
+	}
+
+	/*
+	 * Is this a response to a update rule message?
+	 */
+	if ( !(nircm->rule_flags & NSS_IPV6_MC_RULE_CREATE_FLAG_MC_UPDATE)) {
+		DEBUG_ERROR("%px: multicast update callback with improper type: %d, serial: %u\n", nim, nim->cm.type, serial);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: multicast update callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	nmci = (struct ecm_nss_multicast_ipv6_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(flow_ip, nircm->tuple.flow_ip);
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(return_ip, nircm->tuple.return_ip);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: Update accelerate response for connection: %px, serial: %u\n", nmci, feci->ci, serial);
+	DEBUG_TRACE("%px: valid_flags: %x\n", nmci, nircm->valid_flags);
+	DEBUG_TRACE("%px: flow_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", nmci, ECM_IP_ADDR_TO_OCTAL(flow_ip), nircm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", nmci, ECM_IP_ADDR_TO_OCTAL(return_ip), nircm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", nmci, nircm->tuple.protocol);
+
+	/*
+	 * Release the connection.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+	return;
+}
+
+/*
+ * ecm_nss_multicast_ipv6_connection_create_callback()
+ * 	callback for handling create ack/nack calls for multicast create commands.
+ */
+static void ecm_nss_multicast_ipv6_connection_create_callback(void *app_data, struct nss_ipv6_msg *nim)
+{
+	struct nss_ipv6_mc_rule_create_msg *__attribute__((unused))nircm = &nim->msg.mc_rule_create;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_nss_multicast_ipv6_connection_instance *nmci;
+	ip_addr_t flow_ip;
+	ip_addr_t return_ip;
+	ecm_front_end_acceleration_mode_t result_mode;
+	bool is_defunct = false;
+
+	/*
+	 * Is this a response to a create message?
+	 */
+	if (nim->cm.type != NSS_IPV6_TX_CREATE_MC_RULE_MSG) {
+		DEBUG_ERROR("%px: udp create callback with improper type: %d, serial: %u\n", nim, nim->cm.type, serial);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: create callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	nmci = (struct ecm_nss_multicast_ipv6_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(flow_ip, nircm->tuple.flow_ip);
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(return_ip, nircm->tuple.return_ip);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: accelerate response for connection: %px, serial: %u\n", nmci, feci->ci, serial);
+	DEBUG_TRACE("%px: rule_flags: %x, valid_flags: %x\n", nmci, nircm->rule_flags, nircm->valid_flags);
+	DEBUG_TRACE("%px: flow_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", nmci, ECM_IP_ADDR_TO_OCTAL(flow_ip), nircm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", nmci, ECM_IP_ADDR_TO_OCTAL(return_ip), nircm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", nmci, nircm->tuple.protocol);
+
+	/*
+	 * Handle the creation result code.
+	 */
+	DEBUG_TRACE("%px: response: %d\n", nmci, nim->cm.response);
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		/*
+		 * Creation command failed (specific reason ignored).
+		 */
+		DEBUG_TRACE("%px: accel nack: %d\n", nmci, nim->cm.error);
+		spin_lock_bh(&feci->lock);
+		DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+		feci->stats.ae_nack++;
+		feci->stats.ae_nack_total++;
+		if (nmci->base.stats.ae_nack >= nmci->base.stats.ae_nack_limit) {
+			/*
+			 * Too many NSS rejections
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_ACCEL_ENGINE;
+		} else {
+			/*
+			 * Revert to decelerated
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+		}
+
+		/*
+		 * If connection is now defunct then set mode to ensure no further accel attempts occur
+		 */
+		if (feci->is_defunct) {
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT;
+		}
+		spin_lock_bh(&ecm_nss_ipv6_lock);
+		_ecm_nss_ipv6_accel_pending_clear(feci, result_mode);
+		spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+
+	/*
+	 * If a flush occured before we got the ACK then our acceleration was effectively cancelled on us
+	 * GGG TODO This is a workaround for a NSS message OOO quirk, this should eventually be removed.
+	 */
+	if (nmci->base.stats.flush_happened) {
+		nmci->base.stats.flush_happened = false;
+
+		/*
+		 * Increement the no-action counter.  Our connectin was decelerated on us with no action occurring.
+		 */
+		nmci->base.stats.no_action_seen++;
+		spin_lock_bh(&ecm_nss_ipv6_lock);
+		_ecm_nss_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	/*
+	 * Create succeeded
+	 */
+
+	/*
+	 * Clear any nack count
+	 */
+	nmci->base.stats.ae_nack = 0;
+
+	/*
+	 * Clear the "accelerate pending" state and move to "accelerated" state bumping
+	 * the accelerated counters to match our new state.
+	 *
+	 * Decelerate may have been attempted while we were accel pending.
+	 * If decelerate is pending then we need to begin deceleration :-(
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+
+	ecm_nss_multicast_ipv6_accelerated_count++;	/* Protocol specific counter */
+	ecm_nss_ipv6_accelerated_count++;		/* General running counter */
+
+	if (!_ecm_nss_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_ACCEL)) {
+		/*
+		 * Increement the no-action counter, this is reset if offload action is seen
+		 */
+		nmci->base.stats.no_action_seen++;
+
+		spin_unlock_bh(&ecm_nss_ipv6_lock);
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_INFO("%px: Decelerate was pending\n", ci);
+
+	/*
+	 * Check if the pending decelerate was done with the defunct process.
+	 * If it was, set the is_defunct flag of the feci to false for re-try.
+	 */
+	if (feci->is_defunct) {
+		is_defunct = feci->is_defunct;
+		feci->is_defunct = false;
+	}
+
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * If the pending decelerate was done through defunct process, we should
+	 * re-try it here with the same defunct function, because the purpose of that
+	 * process is to remove the connection from the database as well after decelerating it.
+	 */
+	if (is_defunct) {
+		ecm_db_connection_make_defunct(ci);
+	} else {
+		feci->decelerate(feci);
+	}
+
+	/*
+	 * Release the connection.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_nss_multicast_ipv6_connection_update_accelerate()
+ * 	Push destination interface list updates for a multicast connection
+ * 	to NSS
+ *
+ * 	This function receives a list of interfaces that have either left or joined the connection,
+ * 	and sends a 'multicast update' command to NSS to inform about these interface state changes.
+ */
+static int ecm_nss_multicast_ipv6_connection_update_accelerate(struct ecm_front_end_connection_instance *feci,
+							       struct ecm_multicast_if_update *rp,
+							       struct ecm_classifier_process_response *pr)
+{
+	struct ecm_nss_multicast_ipv6_connection_instance *nmci = (struct ecm_nss_multicast_ipv6_connection_instance *)feci;
+	uint16_t regen_occurrances;
+	struct ecm_db_iface_instance *to_ifaces;
+	struct ecm_db_iface_instance *ii_temp;
+	struct ecm_db_iface_instance *ii_single;
+	struct ecm_db_iface_instance **ifaces;
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *from_nss_iface;
+	int32_t *to_ifaces_first;
+	int32_t *to_ii_first;
+	struct nss_ipv6_msg *nim;
+	struct nss_ipv6_mc_rule_create_msg *create;
+	ip_addr_t addr;
+	int32_t ret, vif;
+	int32_t valid_vif_idx = 0;
+	int32_t from_ifaces_first;
+	int32_t to_nss_iface_id = 0;
+	int32_t from_nss_iface_id = 0;
+	uint8_t to_nss_iface_address[ETH_ALEN];
+	nss_tx_status_t nss_tx_status;
+	int32_t list_index;
+	int32_t to_mtu = 0;
+	int32_t interface_type_counts[ECM_DB_IFACE_TYPE_COUNT];
+	bool rule_invalid;
+	uint8_t dest_mac[ETH_ALEN];
+	int from_iface_identifier = 0;
+	int to_iface_bridge_identifier = 0;
+
+	DEBUG_INFO("%px: UPDATE Accel conn: %px\n", nmci, feci->ci);
+
+	/*
+	 * Get the re-generation occurrance counter of the connection.
+	 * We compare it again at the end - to ensure that the rule construction has seen no generation
+	 * changes during rule creation.
+	 */
+	regen_occurrances = ecm_db_connection_regeneration_occurrances_get(feci->ci);
+
+	nim = (struct nss_ipv6_msg *)kzalloc(sizeof(struct nss_ipv6_msg), GFP_ATOMIC | __GFP_NOWARN);
+	if (!nim) {
+		return -1;
+	}
+
+	nss_ipv6_msg_init(nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_CREATE_MC_RULE_MSG,
+			sizeof(struct nss_ipv6_mc_rule_create_msg),
+			ecm_nss_multicast_ipv6_connection_update_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	create = &nim->msg.mc_rule_create;
+
+	/*
+	 * Construct an accel command.
+	 */
+	ret = ecm_db_multicast_connection_to_interfaces_get_and_ref_all(feci->ci, &to_ifaces, &to_ifaces_first);
+	if (ret == 0) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in to_interfaces list!\n", nmci);
+		kfree(nim);
+		return -1;
+	}
+
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in from_interfaces list!\n", nmci);
+		ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+		kfree(nim);
+		return -1;
+	}
+
+	create->ingress_vlan_tag[0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	create->ingress_vlan_tag[1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+
+	/*
+	 * Set the source NSS interface identifier
+	 */
+	from_nss_iface = from_ifaces[from_ifaces_first];
+	from_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(from_nss_iface);
+	if (from_nss_iface_id < 0) {
+                DEBUG_TRACE("%px: from_nss_iface_id: %d\n", nmci, from_nss_iface_id);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+		kfree(nim);
+		return -1;
+        }
+
+	create->src_interface_num = from_nss_iface_id;
+	from_nss_iface = from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1];
+	from_iface_identifier = ecm_db_iface_interface_identifier_get(from_nss_iface);
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+
+	/*
+	 * Now examine the TO / DEST heirarchy list to construct the destination interface
+	 * information
+	 */
+	DEBUG_TRACE("%px: Examine to/dest heirarchy list\n", nmci);
+	rule_invalid = false;
+
+	/*
+	 * Loop through the list of interface updates
+	 */
+	for (vif = 0; vif < ECM_DB_MULTICAST_IF_MAX; vif++) {
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		create->if_rule[vif].egress_vlan_tag[0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+		create->if_rule[vif].egress_vlan_tag[1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+#endif
+		/*
+		 * If there is no state change for an interface at this index,
+		 * then ignore
+		 */
+		if (!(rp->if_join_idx[vif] || rp->if_leave_idx[vif])) {
+			continue;
+		}
+
+		ii_temp = ecm_db_multicast_if_heirarchy_get(to_ifaces, vif);
+
+		/*
+		 * We have an update for this interface. Construct the interface information
+		 */
+		to_nss_iface_id = -1;
+		memset(interface_type_counts, 0, sizeof(interface_type_counts));
+		to_ii_first = ecm_db_multicast_if_first_get_at_index(to_ifaces_first, vif);
+
+		for (list_index = *to_ii_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+			struct ecm_db_iface_instance *ii;
+			ecm_db_iface_type_t ii_type;
+			char *ii_name;
+
+			ii_single = ecm_db_multicast_if_instance_get_at_index(ii_temp, list_index);
+			ifaces = (struct ecm_db_iface_instance **)ii_single;
+			ii = *ifaces;
+			ii_type = ecm_db_iface_type_get(ii);
+			ii_name = ecm_db_interface_type_to_string(ii_type);
+			DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", nmci, list_index, ii, ii_type, ii_name);
+
+			/*
+			 * Extract information from this interface type if it is applicable to the rule.
+			 * Conflicting information may cause accel to be unsupported.
+			 */
+			switch (ii_type) {
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+				struct ecm_db_interface_info_vlan vlan_info;
+#endif
+
+			case ECM_DB_IFACE_TYPE_BRIDGE:
+				DEBUG_TRACE("%px: Bridge\n", nmci);
+				if (interface_type_counts[ii_type] != 0) {
+					/*
+					 * Cannot cascade bridges
+					 */
+					rule_invalid = true;
+					DEBUG_TRACE("%px: Bridge - ignore additional\n", nmci);
+					break;
+				}
+
+				ecm_db_iface_bridge_address_get(ii, to_nss_iface_address);
+				to_iface_bridge_identifier = ecm_db_iface_interface_identifier_get(ii);
+				DEBUG_TRACE("%px: Bridge - mac: %pM\n", nmci, to_nss_iface_address);
+				break;
+			case ECM_DB_IFACE_TYPE_ETHERNET:
+				 DEBUG_TRACE("%px: Ethernet\n", nmci);
+				if (interface_type_counts[ii_type] != 0) {
+
+					/*
+					 * Ignore additional mac addresses, these are usually as a result of address propagation
+					 * from bridges down to ports etc. */
+
+					DEBUG_TRACE("%px: Ethernet - ignore additional\n", nmci);
+					break;
+				}
+
+				/*
+				 * Can only handle one MAC, the first outermost mac.
+				 */
+				ecm_db_iface_ethernet_address_get(ii, to_nss_iface_address);
+				to_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+				to_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(ii);
+				if (to_nss_iface_id < 0) {
+					DEBUG_TRACE("%px: to_nss_iface_id: %d\n", nmci, to_nss_iface_id);
+					ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+					kfree(nim);
+					return -1;
+			        }
+
+				DEBUG_TRACE("%px: Ethernet - mac: %pM\n", nmci, to_nss_iface_address);
+				break;
+			case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+				/*
+				 * More than one PPPoE in the list is not valid!
+				 */
+				if (interface_type_counts[ii_type] != 0) {
+					DEBUG_TRACE("%px: PPPoE - additional unsupported\n", nmci);
+					rule_invalid = true;
+					break;
+				}
+
+				/*
+				 * Set the PPPoE rule creation structure.
+				 */
+				create->if_rule[valid_vif_idx].pppoe_if_num = ecm_db_iface_ae_interface_identifier_get(ii);
+				if (create->if_rule[valid_vif_idx].pppoe_if_num < 0) {
+					DEBUG_TRACE("%px: PPPoE - acceleration engine interface (%d) is not valid\n",
+							nmci, create->if_rule[valid_vif_idx].pppoe_if_num);
+					rule_invalid = true;
+					break;
+				}
+				create->if_rule[valid_vif_idx].valid_flags |= NSS_IPV6_MC_RULE_CREATE_IF_FLAG_PPPOE_VALID;
+				DEBUG_TRACE("%px: PPPoE - exist pppoe_if_num: %d\n", nmci,
+							create->if_rule[valid_vif_idx].pppoe_if_num);
+#else
+				DEBUG_TRACE("%px: PPPoE - unsupported\n", nmci);
+				rule_invalid = true;
+#endif
+				break;
+			case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+				DEBUG_TRACE("%px: VLAN\n", nmci);
+				if (interface_type_counts[ii_type] > 1) {
+
+					/*
+					 * Can only support two vlans
+					 */
+					rule_invalid = true;
+					DEBUG_TRACE("%px: VLAN - additional unsupported\n", nmci);
+					break;
+				}
+				ecm_db_iface_vlan_info_get(ii, &vlan_info);
+				create->if_rule[valid_vif_idx].egress_vlan_tag[interface_type_counts[ii_type]] = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+				/*
+				 * If we have not yet got an ethernet mac then take this one (very unlikely as mac should have been propagated to the slave (outer) device
+				 */
+				if (interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET] == 0) {
+					memcpy(to_nss_iface_address, vlan_info.address, ETH_ALEN);
+					interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+					DEBUG_TRACE("%px: VLAN use mac: %pM\n", nmci, to_nss_iface_address);
+				}
+				create->if_rule[valid_vif_idx].valid_flags |= NSS_IPV6_MC_RULE_CREATE_IF_FLAG_VLAN_VALID;
+				DEBUG_TRACE("%px: vlan tag: %x\n", nmci, create->if_rule[valid_vif_idx].egress_vlan_tag[interface_type_counts[ii_type]]);
+#else
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - unsupported\n", nmci);
+#endif
+				break;
+			default:
+				DEBUG_TRACE("%px: Ignoring: %d (%s)\n", nmci, ii_type, ii_name);
+			}
+
+			/*
+			 * Seen an interface of this type
+			 */
+			interface_type_counts[ii_type]++;
+		}
+
+		if (rule_invalid) {
+			DEBUG_WARN("%px: to/dest Rule invalid\n", nmci);
+			ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+			kfree(nim);
+			return -1;
+		}
+
+		/*
+		 * Is this a valid interface?
+		 */
+		if (to_nss_iface_id != -1) {
+			bool is_bridge;
+			create->if_rule[valid_vif_idx].if_num = to_nss_iface_id;
+			create->if_rule[valid_vif_idx].if_mtu = to_mtu;
+			if (rp->if_join_idx[vif]) {
+
+				/*
+				 * The interface has joined the group
+				 */
+				create->if_rule[valid_vif_idx].rule_flags |= NSS_IPV6_MC_RULE_CREATE_IF_FLAG_JOIN;
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+				if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG) {
+					/*
+					 * Set primary egress VLAN tag
+					 */
+					if (pr->egress_mc_vlan_tag[vif][0] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+						create->if_rule[valid_vif_idx].egress_vlan_tag[0] = pr->egress_mc_vlan_tag[vif][0];
+						create->if_rule[valid_vif_idx].valid_flags |= NSS_IPV6_MC_RULE_CREATE_IF_FLAG_VLAN_VALID;
+
+						/*
+						 * Set secondary egress VLAN tag
+						 */
+						if (pr->egress_mc_vlan_tag[vif][1] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+							create->if_rule[valid_vif_idx].egress_vlan_tag[1] = pr->egress_mc_vlan_tag[vif][1];
+						}
+					}
+				}
+#endif
+			} else if (rp->if_leave_idx[vif]) {
+
+				/*
+				 * The interface has left the group
+				 */
+				create->if_rule[valid_vif_idx].rule_flags |= NSS_IPV6_MC_RULE_CREATE_IF_FLAG_LEAVE;
+			}
+
+			is_bridge = !ecm_db_connection_is_routed_get(feci->ci);
+
+			/*
+			 * Do not set the ROUTED flag for pure bridged interfaces
+			 */
+			if (is_bridge) {
+				uint8_t from_nss_iface_address[ETH_ALEN];
+				ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, (uint8_t *)from_nss_iface_address);
+				memcpy(create->if_rule[valid_vif_idx].if_mac, from_nss_iface_address, ETH_ALEN);
+				create->if_rule[valid_vif_idx].rule_flags |= NSS_IPV6_MC_RULE_CREATE_IF_FLAG_BRIDGE_FLOW;
+			} else {
+				memcpy(create->if_rule[valid_vif_idx].if_mac, to_nss_iface_address, ETH_ALEN);
+				create->if_rule[valid_vif_idx].rule_flags |= NSS_IPV6_MC_RULE_CREATE_IF_FLAG_ROUTED_FLOW;
+			}
+
+			valid_vif_idx++;
+		}
+	}
+
+	/*
+	 * Set number of interface updates in the update rule
+	 */
+	create->if_count = valid_vif_idx;
+
+	/*
+	 * Set the UPDATE flag
+	 */
+	create->rule_flags |= NSS_IPV6_MC_RULE_CREATE_FLAG_MC_UPDATE;
+
+	/*
+	 * Set protocol
+	 */
+	create->tuple.protocol = IPPROTO_UDP;
+
+	/*
+	 * The src_ip is where the connection established from
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, addr);
+	ECM_IP_ADDR_TO_NSS_IPV6_ADDR(create->tuple.flow_ip, addr);
+
+	/*
+	 * The destination address is what the destination IP is translated to as it is forwarded to the next interface.
+	 * For egress this would yield the normal wan host and for ingress this would correctly NAT back to the LAN host
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, addr);
+	ECM_IP_ADDR_TO_NSS_IPV6_ADDR(create->tuple.return_ip, addr);
+
+	/*
+	 * Same approach as above for port information
+	 */
+	create->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	create->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	/*
+	 * Destination Node(MAC) address. This address will be same for all to side intefaces
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, dest_mac);
+	memcpy(create->dest_mac, dest_mac, ETH_ALEN);
+
+	ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+
+	for (vif = 0; vif < valid_vif_idx ; vif++) {
+		DEBUG_TRACE("ACCEL UPDATE %px: UDP Accelerate connection %px\n"
+				"Rule flag: %x\n"
+				"Vif: %d\n"
+				"Protocol: %d\n"
+				"from_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+				"to_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+				"to_mtu: %u\n"
+				"to_mac: %pM\n"
+				"dest_iface_num: %u\n"
+				"out_vlan[0] %x\n"
+				"out_vlan[1] %x\n",
+				nmci,
+				feci->ci,
+				create->if_rule[vif].rule_flags,
+				vif,
+				create->tuple.protocol,
+				ECM_IP_ADDR_TO_OCTAL(create->tuple.flow_ip), create->tuple.flow_ident,
+				ECM_IP_ADDR_TO_OCTAL(create->tuple.return_ip), create->tuple.return_ident,
+				create->if_rule[vif].if_mtu,
+				create->if_rule[vif].if_mac,
+				create->if_rule[vif].if_num,
+				create->if_rule[vif].egress_vlan_tag[0],
+				create->if_rule[vif].egress_vlan_tag[1]);
+
+	}
+
+	/*
+	 * Now that the rule has been constructed we re-compare the generation occurrance counter.
+	 * If there has been a change then we abort because the rule may have been created using
+	 * unstable data - especially if another thread has begun regeneration of the connection state.
+	 * NOTE: This does not prevent a regen from being flagged immediately after this line of code either,
+	 * or while the acceleration rule is in flight to the nss.
+	 * This is only to check for consistency of rule state - not that the state is stale.
+	 */
+	if (regen_occurrances != ecm_db_connection_regeneration_occurrances_get(feci->ci)) {
+		DEBUG_INFO("%px: connection:%px regen occurred - aborting accel rule.\n", feci, feci->ci);
+		kfree(nim);
+		return -1;
+	}
+
+	/*
+	 * Ref the connection before issuing an NSS rule
+	 * This ensures that when the NSS responds to the command - which may even be immediately -
+	 * the callback function can trust the correct ref was taken for its purpose.
+	 * NOTE: remember that this will also implicitly hold the feci.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Call the rule create function
+	 */
+	nss_tx_status = nss_ipv6_tx(ecm_nss_ipv6_nss_ipv6_mgr, nim);
+	if (nss_tx_status == NSS_TX_SUCCESS) {
+		spin_lock_bh(&feci->lock);
+		nmci->base.stats.driver_fail = 0;		/* Reset */
+		spin_unlock_bh(&feci->lock);
+		kfree(nim);
+		return 0;
+	}
+
+	/*
+	 * Revert accel mode if necessary
+	 */
+	DEBUG_WARN("%px: ACCEL UPDATE attempt failed\n", nmci);
+
+	/*
+	 * Release that ref!
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	kfree(nim);
+
+	/*
+	 * TX failed
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.driver_fail_total++;
+	feci->stats.driver_fail++;
+	if (nmci->base.stats.driver_fail >= nmci->base.stats.driver_fail_limit) {
+		DEBUG_WARN("%px: Accel failed - driver fail limit\n", nmci);
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DRIVER;
+	}
+	spin_unlock_bh(&feci->lock);
+	return -1;
+}
+
+/*
+ * ecm_nss_multicast_ipv6_connection_accelerate()
+ * 	Accelerate a multicast UDP connection
+ */
+static void ecm_nss_multicast_ipv6_connection_accelerate(struct ecm_front_end_connection_instance *feci,
+                                                                        struct ecm_classifier_process_response *pr, bool is_l2_encap,
+                                                                        struct nf_conn *ct, struct sk_buff *skb)
+{
+	struct ecm_nss_multicast_ipv6_connection_instance *nmci = (struct ecm_nss_multicast_ipv6_connection_instance *)feci;
+	uint16_t regen_occurrances;
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *from_nss_iface;
+	int32_t from_ifaces_first;
+	struct ecm_db_iface_instance *to_ifaces;
+	struct ecm_db_iface_instance *ii_temp;
+	struct ecm_db_iface_instance *ii_single;
+	struct ecm_db_iface_instance **ifaces;
+	struct nss_ipv6_msg *nim;
+	int32_t *to_ifaces_first;
+	int32_t *to_ii_first;
+	int32_t from_nss_iface_id;
+	int32_t to_nss_iface_id;
+	uint8_t to_nss_iface_address[ETH_ALEN];
+	ip_addr_t addr;
+	struct nss_ipv6_mc_rule_create_msg *create;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int32_t vif, ret;
+	int assignment_count;
+	int from_iface_identifier = 0;
+	int to_iface_bridge_identifier = 0;
+	nss_tx_status_t nss_tx_status;
+	int32_t list_index;
+	int32_t valid_vif_idx = 0;
+	int32_t interface_type_counts[ECM_DB_IFACE_TYPE_COUNT];
+	uint8_t dest_mac[ETH_ALEN];
+	bool rule_invalid;
+	ecm_front_end_acceleration_mode_t result_mode;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	/*
+	 * Get the re-generation occurrance counter of the connection.
+	 * We compare it again at the end - to ensure that the rule construction has seen no generation
+	 * changes during rule creation.
+	 */
+	regen_occurrances = ecm_db_connection_regeneration_occurrances_get(feci->ci);
+
+	/*
+	 * Can this connection be accelerated at all?
+	 */
+	if (!ecm_nss_ipv6_accel_pending_set(feci)) {
+		DEBUG_TRACE("%px: Acceleration denied: %px\n", feci, feci->ci);
+		return;
+	}
+
+	/*
+	 * Construct an accel command.
+	 * Initialise Multicast create structure.
+	 * NOTE: We leverage the app_data void pointer to be our 32 bit connection serial number.
+	 * When we get it back we re-cast it to a uint32 and do a faster connection lookup.
+	 */
+	nim = (struct nss_ipv6_msg *)kzalloc(sizeof(struct nss_ipv6_msg), GFP_ATOMIC | __GFP_NOWARN);
+	if (!nim) {
+		return;
+	}
+
+	nss_ipv6_msg_init(nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_CREATE_MC_RULE_MSG,
+			sizeof(struct nss_ipv6_mc_rule_create_msg),
+			 ecm_nss_multicast_ipv6_connection_create_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	create = &nim->msg.mc_rule_create;
+
+	/*
+	 * Populate the multicast creation structure
+	 */
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in from_interfaces list!\n", nmci);
+		kfree(nim);
+		return;
+	}
+
+	create->ingress_vlan_tag[0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	create->ingress_vlan_tag[1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	from_nss_iface = from_ifaces[from_ifaces_first];
+	from_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(from_nss_iface);
+
+	if (from_nss_iface_id < 0) {
+		DEBUG_TRACE("%px: from_nss_iface_id: %d\n", nmci, from_nss_iface_id);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		kfree(nim);
+		return;
+	}
+
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = from_ifaces_first; list_index < ECM_DB_IFACE_HEIRARCHY_MAX; list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+
+		ii = from_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", nmci, list_index, ii, ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			struct ecm_db_interface_info_vlan vlan_info;
+#endif
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", nmci);
+			from_iface_identifier = ecm_db_iface_interface_identifier_get(ii);
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", nmci);
+			if (interface_type_counts[ii_type] > 1) {
+
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", nmci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			create->ingress_vlan_tag[interface_type_counts[ii_type]] = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+			create->valid_flags |= NSS_IPV6_MC_RULE_CREATE_FLAG_INGRESS_VLAN_VALID;
+			DEBUG_TRACE("%px: vlan tag: %x\n", nmci, create->ingress_vlan_tag[interface_type_counts[ii_type]]);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", nmci);
+#endif
+			break;
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", nmci, ii_type, ii_name);
+		}
+		interface_type_counts[ii_type]++;
+	}
+
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+
+	ret = ecm_db_multicast_connection_to_interfaces_get_and_ref_all(feci->ci, &to_ifaces, &to_ifaces_first);
+	if (!ret) {
+		DEBUG_WARN("%px: Accel attempt failed - no multicast interfaces in to_interfaces list!\n", nmci);
+		kfree(nim);
+		return;
+	}
+
+	/*
+	 * Now examine the TO / DEST heirarchy list to construct the destination part of the rule
+	 */
+	DEBUG_TRACE("%px: Examine to/dest heirarchy list\n", nmci);
+	rule_invalid = false;
+	for (vif = 0; vif < ECM_DB_MULTICAST_IF_MAX; vif++) {
+		int32_t to_mtu = 0;
+		to_nss_iface_id = -1;
+
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		create->if_rule[vif].egress_vlan_tag[0] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+		create->if_rule[vif].egress_vlan_tag[1] = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+#endif
+
+		ii_temp = ecm_db_multicast_if_heirarchy_get(to_ifaces, vif);
+		to_ii_first = ecm_db_multicast_if_first_get_at_index(to_ifaces_first, vif);
+		memset(interface_type_counts, 0, sizeof(interface_type_counts));
+
+		for (list_index = *to_ii_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+			struct ecm_db_iface_instance *ii;
+			ecm_db_iface_type_t ii_type;
+			char *ii_name;
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			struct ecm_db_interface_info_vlan vlan_info;
+			struct net_device *vlan_out_dev = NULL;
+			uint32_t vlan_prio = 0;
+#endif
+
+			ii_single = ecm_db_multicast_if_instance_get_at_index(ii_temp, list_index);
+			ifaces = (struct ecm_db_iface_instance **)ii_single;
+			ii = *ifaces;
+			ii_type = ecm_db_iface_type_get(ii);
+			ii_name = ecm_db_interface_type_to_string(ii_type);
+
+			DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", nmci, list_index, ii, ii_type, ii_name);
+
+			/*
+			 * Extract information from this interface type if it is applicable to the rule.
+			 * Conflicting information may cause accel to be unsupported.
+			 */
+			switch (ii_type) {
+			case ECM_DB_IFACE_TYPE_BRIDGE:
+
+				/*
+				 * TODO: Find and set the bridge/route flag for this interface
+				 */
+				DEBUG_TRACE("%px: Bridge\n", nmci);
+				if (interface_type_counts[ii_type] != 0) {
+
+					/*
+					 * Cannot cascade bridges
+					 */
+					rule_invalid = true;
+					DEBUG_TRACE("%px: Bridge - ignore additional\n", nmci);
+					break;
+				}
+				ecm_db_iface_bridge_address_get(ii, to_nss_iface_address);
+				to_iface_bridge_identifier = ecm_db_iface_interface_identifier_get(ii);
+				DEBUG_TRACE("%px: Bridge - mac: %pM\n", nmci, to_nss_iface_address);
+				break;
+			case ECM_DB_IFACE_TYPE_ETHERNET:
+				DEBUG_TRACE("%px: Ethernet\n", nmci);
+				if (interface_type_counts[ii_type] != 0) {
+
+					/*
+					 * Ignore additional mac addresses, these are usually as a result of address propagation
+					 * from bridges down to ports etc.
+					 */
+					DEBUG_TRACE("%px: Ethernet - ignore additional\n", nmci);
+					break;
+				}
+
+				/*
+				 * Can only handle one MAC, the first outermost mac.
+				 */
+				ecm_db_iface_ethernet_address_get(ii, to_nss_iface_address);
+				to_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+				to_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(ii);
+				if (to_nss_iface_id < 0) {
+					DEBUG_TRACE("%px: to_nss_iface_id: %d\n", nmci, to_nss_iface_id);
+					ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+					kfree(nim);
+					return;
+			        }
+
+				DEBUG_TRACE("%px: Ethernet - mac: %pM\n", nmci, to_nss_iface_address);
+				break;
+			case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+				/*
+				 * More than one PPPoE in the list is not valid!
+				 */
+				if (interface_type_counts[ii_type] != 0) {
+					DEBUG_TRACE("%px: PPPoE - additional unsupported\n", nmci);
+					rule_invalid = true;
+					break;
+				}
+
+				/*
+				 * Set the PPPoE rule creation structure.
+				 */
+				create->if_rule[valid_vif_idx].pppoe_if_num = ecm_db_iface_ae_interface_identifier_get(ii);
+				if (create->if_rule[valid_vif_idx].pppoe_if_num < 0) {
+					DEBUG_TRACE("%px: PPPoE - acceleration engine interface (%d) is not valid\n",
+							nmci, create->if_rule[valid_vif_idx].pppoe_if_num);
+					rule_invalid = true;
+					break;
+				}
+				create->if_rule[valid_vif_idx].valid_flags |= NSS_IPV6_MC_RULE_CREATE_IF_FLAG_PPPOE_VALID;
+				DEBUG_TRACE("%px: PPPoE - exist if_num: %d\n", nmci,
+							create->if_rule[valid_vif_idx].pppoe_if_num);
+#else
+				DEBUG_TRACE("%px: PPPoE - unsupported\n", nmci);
+				rule_invalid = true;
+#endif
+				break;
+			case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+				DEBUG_TRACE("%px: VLAN\n", nmci);
+				if (interface_type_counts[ii_type] > 1) {
+					/*
+					 * Can only support two vlans
+					 */
+					rule_invalid = true;
+					DEBUG_TRACE("%px: VLAN - additional unsupported\n", nmci);
+					break;
+				}
+
+				ecm_db_iface_vlan_info_get(ii, &vlan_info);
+				create->if_rule[valid_vif_idx].egress_vlan_tag[interface_type_counts[ii_type]] = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+				vlan_out_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+				if (vlan_out_dev) {
+					vlan_prio = vlan_dev_get_egress_qos_mask(vlan_out_dev, pr->flow_qos_tag);
+					create->if_rule[valid_vif_idx].egress_vlan_tag[interface_type_counts[ii_type]] |= vlan_prio;
+					dev_put(vlan_out_dev);
+					vlan_out_dev = NULL;
+				}
+
+				/*
+				 * If we have not yet got an ethernet mac then take this one (very unlikely as mac should have been propagated to the slave (outer) device
+				 */
+				if (interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET] == 0) {
+					memcpy(to_nss_iface_address, vlan_info.address, ETH_ALEN);
+					interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+					DEBUG_TRACE("%px: VLAN use mac: %pM\n", nmci, to_nss_iface_address);
+				}
+				create->if_rule[valid_vif_idx].valid_flags |= NSS_IPV6_MC_RULE_CREATE_IF_FLAG_VLAN_VALID;
+				DEBUG_TRACE("%px: vlan tag: %x\n", nmci, create->if_rule[vif].egress_vlan_tag[interface_type_counts[ii_type]]);
+#else
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - unsupported\n", nmci);
+#endif
+				break;
+			default:
+				DEBUG_TRACE("%px: Ignoring: %d (%s)\n", nmci, ii_type, ii_name);
+			}
+
+			/*
+			 * Seen an interface of this type
+			 */
+			interface_type_counts[ii_type]++;
+		}
+
+		if (rule_invalid) {
+			DEBUG_WARN("%px: to/dest Rule invalid\n", nmci);
+			ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+			kfree(nim);
+			return;
+		}
+
+		/*
+		 * Populate the interface details for a valid interface in the multicast destination
+		 * interface list.
+		 */
+		if (to_nss_iface_id != -1) {
+			bool is_bridge;
+			create->if_rule[valid_vif_idx].rule_flags |= NSS_IPV6_MC_RULE_CREATE_IF_FLAG_JOIN;
+			create->if_rule[valid_vif_idx].if_num = to_nss_iface_id;
+			create->if_rule[valid_vif_idx].if_mtu = to_mtu;
+
+			is_bridge = !ecm_db_connection_is_routed_get(feci->ci);
+
+			/*
+			 * Identify if the destination interface blongs to pure bridge or routed flow.
+			 */
+			if (is_bridge) {
+				uint8_t from_nss_iface_address[ETH_ALEN];
+				ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, (uint8_t *)from_nss_iface_address);
+				memcpy(create->if_rule[valid_vif_idx].if_mac, from_nss_iface_address, ETH_ALEN);
+				create->if_rule[valid_vif_idx].rule_flags |= NSS_IPV6_MC_RULE_CREATE_IF_FLAG_BRIDGE_FLOW;
+			} else {
+				memcpy(create->if_rule[valid_vif_idx].if_mac, to_nss_iface_address, ETH_ALEN);
+				create->if_rule[valid_vif_idx].rule_flags |= NSS_IPV6_MC_RULE_CREATE_IF_FLAG_ROUTED_FLOW;
+			}
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+			if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG) {
+				/*
+				 * Set primary egress VLAN tag
+				 */
+				if (pr->egress_mc_vlan_tag[vif][0] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+					create->if_rule[valid_vif_idx].egress_vlan_tag[0] = pr->egress_mc_vlan_tag[vif][0];
+					create->if_rule[valid_vif_idx].valid_flags |= NSS_IPV6_MC_RULE_CREATE_IF_FLAG_VLAN_VALID;
+
+					/*
+					 * Set secondary egress VLAN tag
+					 */
+					if (pr->egress_mc_vlan_tag[vif][1] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+						create->if_rule[valid_vif_idx].egress_vlan_tag[1] = pr->egress_mc_vlan_tag[vif][1];
+					}
+				}
+			}
+#endif
+			valid_vif_idx++;
+		}
+	}
+
+	create->if_count = valid_vif_idx;
+	create->src_interface_num = from_nss_iface_id;
+
+	/*
+	 * Set up the flow qos tags
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+		create->qos_tag = (uint32_t)pr->flow_qos_tag;
+		create->valid_flags |= NSS_IPV6_MC_RULE_CREATE_FLAG_QOS_VALID;
+	}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+#ifdef ECM_CLASSIFIER_DSCP_IGS
+	/*
+	 * Set up ingress shaper flow qos tags.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG) {
+		create->igs_qos_tag = (uint16_t)pr->igs_flow_qos_tag;
+		create->valid_flags |= NSS_IPV6_MC_RULE_CREATE_FLAG_IGS_VALID;
+	}
+#endif
+	/*
+	 * DSCP information?
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+			create->egress_dscp = pr->flow_dscp;
+			create->valid_flags |= NSS_IPV6_MC_RULE_CREATE_FLAG_DSCP_MARKING_VALID;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+	/*
+	 * Mark the rule as E-MESH Service Prioritization valid.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW) {
+		create->rule_flags |= NSS_IPV6_MC_RULE_CREATE_FLAG_MC_EMESH_SP;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG) {
+		/*
+		 * Set ingress VLAN tag
+		 */
+		if (pr->ingress_vlan_tag[0] != ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) {
+			create->ingress_vlan_tag[0] = pr->ingress_vlan_tag[0];
+			create->valid_flags |= NSS_IPV6_MC_RULE_CREATE_FLAG_INGRESS_VLAN_VALID;
+			ecm_db_multicast_tuple_set_ovs_ingress_vlan(feci->ci->ti, pr->ingress_vlan_tag);
+		}
+	}
+#endif
+
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, dest_mac);
+	memcpy(create->dest_mac, dest_mac, ETH_ALEN);
+
+	/*
+	 * Set protocol
+	 */
+	create->tuple.protocol = IPPROTO_UDP;
+
+	/*
+	 * The src_ip is where the connection established from
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, addr);
+	ECM_IP_ADDR_TO_NSS_IPV6_ADDR(create->tuple.flow_ip, addr);
+
+	/*
+	 * The destination address is what the destination IP is translated to as it is forwarded to the next interface.
+	 * For egress this would yield the normal wan host and for ingress this would correctly NAT back to the LAN host
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, addr);
+	ECM_IP_ADDR_TO_NSS_IPV6_ADDR(create->tuple.return_ip, addr);
+
+	/*
+	 * Same approach as above for port information
+	 */
+	create->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	create->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	/*
+	 * Sync our creation command from the assigned classifiers to get specific additional creation rules.
+	 * NOTE: These are called in ascending order of priority and so the last classifier (highest) shall
+	 * override any preceding classifiers.
+	 * This also gives the classifiers a chance to see that acceleration is being attempted.
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(feci->ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+		struct ecm_classifier_rule_create ecrc;
+		/*
+		 * NOTE: The current classifiers do not sync anything to the underlying accel engines.
+		 * In the future, if any of the classifiers wants to pass any parameter, these parameters
+		 * should be received via this object and copied to the accel engine's create object (nircm).
+		*/
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: sync from: %px, type: %d\n", nmci, aci, aci->type_get(aci));
+		aci->sync_from_v6(aci, &ecrc);
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Release the interface lists
+	 */
+	ecm_db_multicast_connection_to_interfaces_deref_all(to_ifaces, to_ifaces_first);
+
+	for (vif = 0; vif < valid_vif_idx ; vif++){
+		DEBUG_TRACE("%px: UDP Accelerate connection %px\n"
+			"Vif: %d\n"
+			"Protocol: %d\n"
+			"to_mtu: %u\n"
+			"from_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"to_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"to_mac: %pM\n"
+			"dest_iface_num: %u\n"
+			"in_vlan[0] %x\n"
+			"in_vlan[1] %x\n"
+			"out_vlan[0] %x\n"
+			"out_vlan[1] %x\n",
+			nmci,
+			feci->ci,
+			vif,
+			create->tuple.protocol,
+			create->if_rule[vif].if_mtu,
+			ECM_IP_ADDR_TO_OCTAL(create->tuple.flow_ip), create->tuple.flow_ident,
+			ECM_IP_ADDR_TO_OCTAL(create->tuple.return_ip), create->tuple.return_ident,
+			create->if_rule[vif].if_mac,
+			create->if_rule[vif].if_num,
+			create->ingress_vlan_tag[0],
+			create->ingress_vlan_tag[1],
+			create->if_rule[vif].egress_vlan_tag[0],
+			create->if_rule[vif].egress_vlan_tag[1]);
+	}
+
+	/*
+	 * Now that the rule has been constructed we re-compare the generation occurrance counter.
+	 * If there has been a change then we abort because the rule may have been created using
+	 * unstable data - especially if another thread has begun regeneration of the connection state.
+	 * NOTE: This does not prevent a regen from being flagged immediately after this line of code either,
+	 * or while the acceleration rule is in flight to the nss.
+	 * This is only to check for consistency of rule state - not that the state is stale.
+	 * Remember that the connection is marked as "accel pending state" so if a regen is flagged immediately
+	 * after this check passes, the connection will be decelerated and refreshed very quickly.
+	 */
+	if (regen_occurrances != ecm_db_connection_regeneration_occurrances_get(feci->ci)) {
+		DEBUG_INFO("%px: connection:%px regen occurred - aborting accel rule.\n", feci, feci->ci);
+		ecm_nss_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		kfree(nim);
+		return;
+	}
+
+	/*
+	 * Ref the connection before issuing an NSS rule
+	 * This ensures that when the NSS responds to the command - which may even be immediately -
+	 * the callback function can trust the correct ref was taken for its purpose.
+	 * NOTE: remember that this will also implicitly hold the feci.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Call the rule create function
+	 */
+	nss_tx_status = nss_ipv6_tx(ecm_nss_ipv6_nss_ipv6_mgr, nim);
+	if (nss_tx_status == NSS_TX_SUCCESS) {
+
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		nmci->base.stats.driver_fail = 0;	/* Reset */
+		spin_unlock_bh(&feci->lock);
+		kfree(nim);
+		return;
+	}
+
+	/*
+	 * Release that ref!
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * TX failed
+	 */
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: accel mode unexpected: %d\n", nmci, feci->accel_mode);
+	feci->stats.driver_fail_total++;
+	feci->stats.driver_fail++;
+	if (feci->stats.driver_fail >= feci->stats.driver_fail_limit) {
+		DEBUG_WARN("%px: Accel failed - driver fail limit\n", nmci);
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DRIVER;
+	} else {
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	_ecm_nss_ipv6_accel_pending_clear(feci, result_mode);
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	spin_unlock_bh(&feci->lock);
+	kfree(nim);
+	return;
+}
+
+/*
+ * ecm_nss_multicast_ipv6_connection_destroy_callback()
+ *	Callback for handling destroy ack/nack calls.
+ */
+static void ecm_nss_multicast_ipv6_connection_destroy_callback(void *app_data, struct nss_ipv6_msg *nim)
+{
+	struct nss_ipv6_rule_destroy_msg *nirdm = &nim->msg.rule_destroy;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_nss_multicast_ipv6_connection_instance *nmci;
+	ip_addr_t flow_ip;
+	ip_addr_t return_ip;
+
+	/*
+	 * Is this a response to a destroy message?
+	 */
+	if (nim->cm.type != NSS_IPV6_TX_DESTROY_RULE_MSG) {
+		DEBUG_ERROR("%px: multicast destroy callback with improper type: %d\n", nim, nim->cm.type);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: destroy callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	nmci = (struct ecm_nss_multicast_ipv6_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(flow_ip, nirdm->tuple.flow_ip);
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(return_ip, nirdm->tuple.return_ip);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_nss_ipv6_decel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: decelerate response for connection: %px\n", nmci, feci->ci);
+	DEBUG_TRACE("%px: flow_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", nmci, ECM_IP_ADDR_TO_OCTAL(flow_ip), nirdm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", nmci, ECM_IP_ADDR_TO_OCTAL(return_ip), nirdm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", nmci, nirdm->tuple.protocol);
+
+	/*
+	 * Drop decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_ipv6_pending_decel_count--;
+	DEBUG_ASSERT(ecm_nss_ipv6_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If decel is not still pending then it's possible that the NSS ended acceleration by some other reason e.g. flush
+	 * In which case we cannot rely on the response we get here.
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING) {
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connections.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_TRACE("%px: response: %d\n", nmci, nim->cm.response);
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DECEL;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	/*
+	 * If connection became defunct then set mode so that no further accel/decel attempts occur.
+	 */
+	if (feci->is_defunct) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT_SHORT;
+	}
+
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Multicast acceleration ends
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_multicast_ipv6_accelerated_count--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_nss_multicast_ipv6_accelerated_count >= 0, "Bad udp accel counter\n");
+	ecm_nss_ipv6_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_nss_ipv6_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	/*
+	 * Release the connections.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_nss_multicast_ipv6_connection_decelerate_msg_send()
+ *	Prepares and sends a decelerate message to acceleration engine.
+ */
+static bool ecm_nss_multicast_ipv6_connection_decelerate_msg_send(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_multicast_ipv6_connection_instance *nmci = (struct ecm_nss_multicast_ipv6_connection_instance *)feci;
+	struct nss_ipv6_msg nim;
+	struct nss_ipv6_rule_destroy_msg *nirdm;
+	ip_addr_t src_ip;
+	ip_addr_t dest_ip;
+	nss_tx_status_t nss_tx_status;
+	bool ret;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	/*
+	 * Increment the decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_ipv6_pending_decel_count++;
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	/*
+	 * Prepare deceleration message
+	 */
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_DESTROY_RULE_MSG,
+			sizeof(struct nss_ipv6_rule_destroy_msg),
+			ecm_nss_multicast_ipv6_connection_destroy_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nirdm = &nim.msg.rule_destroy;
+	nirdm->tuple.protocol = (int32_t)ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * Get addressing information
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	ECM_IP_ADDR_TO_NSS_IPV6_ADDR(nirdm->tuple.flow_ip, src_ip);
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, dest_ip);
+	ECM_IP_ADDR_TO_NSS_IPV6_ADDR(nirdm->tuple.return_ip, dest_ip);
+	nirdm->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nirdm->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	DEBUG_INFO("%px: Mcast Connection %px decelerate\n"
+			"src_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"dest_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n",
+			nmci, feci->ci,
+			ECM_IP_ADDR_TO_OCTAL(src_ip), nirdm->tuple.flow_ident,
+			ECM_IP_ADDR_TO_OCTAL(dest_ip), nirdm->tuple.return_ident);
+
+	/*
+	 * Right place to free the multicast destination interfaces list.
+	 */
+	ecm_db_multicast_connection_to_interfaces_clear(feci->ci);
+
+	/*
+	 * Take a ref to the feci->ci so that it will persist until we get a response from the NSS.
+	 * NOTE: This will implicitly hold the feci too.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Destroy the NSS connection cache entry.
+	 */
+	nss_tx_status = nss_ipv6_tx(ecm_nss_ipv6_nss_ipv6_mgr, &nim);
+	if (nss_tx_status == NSS_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;
+		spin_unlock_bh(&feci->lock);
+		return true;
+	}
+
+	/*
+	 * TX failed
+	 */
+	ret = ecm_front_end_destroy_failure_handle(feci);
+
+	/*
+	 * Release the ref take, NSS driver did not accept our command.
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * Could not send the request, decrement the decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_ipv6_pending_decel_count--;
+	DEBUG_ASSERT(ecm_nss_ipv6_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	return ret;
+}
+
+/*
+ * ecm_nss_multicast_ipv6_connection_decelerate()
+ *     Decelerate a connection
+ */
+static bool ecm_nss_multicast_ipv6_connection_decelerate(struct ecm_front_end_connection_instance *feci)
+{
+	/*
+	 * Check if accel mode is OK for the deceleration.
+	 */
+	spin_lock_bh(&feci->lock);
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	return ecm_nss_multicast_ipv6_connection_decelerate_msg_send(feci);
+}
+
+/*
+ * ecm_nss_multicast_ipv6_connection_defunct_callback()
+ *	Callback to be called when a Mcast connection has become defunct.
+ */
+bool ecm_nss_multicast_ipv6_connection_defunct_callback(void *arg, int *accel_mode)
+{
+	bool ret;
+	struct ecm_front_end_connection_instance *feci = (struct ecm_front_end_connection_instance *)arg;
+	struct ecm_nss_multicast_ipv6_connection_instance *nmci = (struct ecm_nss_multicast_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	spin_lock_bh(&feci->lock);
+	/*
+	 * Check if the connection can be defuncted.
+	 */
+	if (!ecm_front_end_common_connection_defunct_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+
+	/*
+	 * If none of the cases matched above, this means the connection is in the
+	 * accel mode, so we force a deceleration.
+	 * NOTE: If the mode is accel pending then the decel will be actioned when that is completed.
+	 */
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	ret = ecm_nss_multicast_ipv6_connection_decelerate_msg_send(feci);
+
+	/*
+	 * Copy the accel_mode which is returned from the decelerate message function. This value
+	 * will be used in the caller to decide releasing the final reference of the connection.
+	 * But if this function reaches to here, the caller care about the ret. If ret is true,
+	 * the reference will be released regardless of the accel_mode. If ret is false, accel_mode
+	 * will be in the ACCEL state (for destroy re-try) and this state will not be used in the
+	 * caller's decision. It looks for ACCEL_FAIL states.
+	 */
+	spin_lock_bh(&feci->lock);
+	*accel_mode = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+
+	return ret;
+}
+
+/*
+ * ecm_nss_multicast_ipv6_connection_accel_state_get()
+ *	Get acceleration state
+ */
+static ecm_front_end_acceleration_mode_t ecm_nss_multicast_ipv6_connection_accel_state_get(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_multicast_ipv6_connection_instance *nmci = (struct ecm_nss_multicast_ipv6_connection_instance *)feci;
+	ecm_front_end_acceleration_mode_t state;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+	spin_lock_bh(&feci->lock);
+	state = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+	return state;
+}
+
+/*
+ * ecm_nss_multicast_ipv6_connection_action_seen()
+ *	Acceleration action / activity has been seen for this connection.
+ *
+ * NOTE: Call the action_seen() method when the NSS has demonstrated that it has offloaded some data for a connection.
+ */
+static void ecm_nss_multicast_ipv6_connection_action_seen(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_multicast_ipv6_connection_instance *nmci = (struct ecm_nss_multicast_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+	DEBUG_INFO("%px: Action seen\n", nmci);
+	spin_lock_bh(&feci->lock);
+	feci->stats.no_action_seen = 0;
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_nss_multicast_ipv6_connection_accel_ceased()
+ *	NSS has indicated that acceleration has stopped.
+ *
+ * NOTE: This is called in response to an NSS self-initiated termination of acceleration.
+ * This must NOT be called because the ECM terminated the acceleration.
+ */
+static void ecm_nss_multicast_ipv6_connection_accel_ceased(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_multicast_ipv6_connection_instance *nmci = (struct ecm_nss_multicast_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+	DEBUG_INFO("%px: accel ceased\n", nmci);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If we are in accel-pending state then the NSS has issued a flush out-of-order
+	 * with the ACK/NACK we are actually waiting for.
+	 * To work around this we record a "flush has already happened" and will action it when we finally get that ACK/NACK.
+	 * GGG TODO This should eventually be removed when the NSS honours messaging sequence.
+	 */
+	if (feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING) {
+		feci->stats.flush_happened = true;
+		feci->stats.flush_happened_total++;
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If connection is no longer accelerated by the time we get here just ignore the command
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_ACCEL) {
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If the no_action_seen counter was not reset then acceleration ended without any offload action
+	 */
+	if (feci->stats.no_action_seen) {
+		feci->stats.no_action_seen_total++;
+	}
+
+	/*
+	 * If the no_action_seen indicates successive cessations of acceleration without any offload action occuring
+	 * then we fail out this connection
+	 */
+	if (feci->stats.no_action_seen >= feci->stats.no_action_seen_limit) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_NO_ACTION;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Mcast acceleration ends
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_multicast_ipv6_accelerated_count--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_nss_multicast_ipv6_accelerated_count >= 0, "Bad Mcast accel counter\n");
+	ecm_nss_ipv6_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_nss_ipv6_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+}
+
+/*
+ * ecm_nss_multicast_ipv6_connection_ref()
+ *	Ref a connection front end instance
+ */
+static void ecm_nss_multicast_ipv6_connection_ref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_multicast_ipv6_connection_instance *nmci = (struct ecm_nss_multicast_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+	spin_lock_bh(&feci->lock);
+	feci->refs++;
+	DEBUG_TRACE("%px: nmci ref %d\n", nmci, feci->refs);
+	DEBUG_ASSERT(feci->refs > 0, "%px: ref wrap\n", nmci);
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_nss_multicast_ipv6_connection_deref()
+ *	Deref a connection front end instance
+ */
+static int ecm_nss_multicast_ipv6_connection_deref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_multicast_ipv6_connection_instance *nmci = (struct ecm_nss_multicast_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	spin_lock_bh(&feci->lock);
+	feci->refs--;
+	DEBUG_ASSERT(feci->refs >= 0, "%px: ref wrap\n", nmci);
+
+	if (feci->refs > 0) {
+		int refs = feci->refs;
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: nmci deref %d\n", nmci, refs);
+		return refs;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * We can now destroy the instance
+	 */
+	DEBUG_TRACE("%px: nmci final\n", nmci);
+	DEBUG_CLEAR_MAGIC(nmci);
+	kfree(nmci);
+
+	return 0;
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_nss_multicast_ipv6_connection_state_get()
+ *	Return state of this multicast front end instance
+ */
+static int ecm_nss_multicast_ipv6_connection_state_get(struct ecm_front_end_connection_instance *feci, struct ecm_state_file_instance *sfi)
+{
+	struct ecm_nss_multicast_ipv6_connection_instance *nmci = (struct ecm_nss_multicast_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nmci, ECM_NSS_MULTICAST_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nmci);
+
+	return ecm_front_end_common_connection_state_get(feci, sfi, "nss_v6.multicast");
+}
+#endif
+
+/*
+ * ecm_nss_multicast_ipv6_bridge_update_connections()
+ * 	Update NSS with new multicast egress ports.
+ */
+static void ecm_nss_multicast_ipv6_bridge_update_connections(ip_addr_t dest_ip, struct net_device *brdev)
+{
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_db_multicast_tuple_instance *ti;
+	struct ecm_db_multicast_tuple_instance *ti_next;
+	struct ecm_multicast_if_update mc_sync;
+	struct ecm_db_connection_instance *ci;
+	struct in6_addr group6;
+	struct in6_addr origin6;
+	ip_addr_t grp_ip;
+	ip_addr_t src_ip;
+	int i, ret;
+	int32_t if_num;
+	uint32_t mc_dst_dev[ECM_DB_MULTICAST_IF_MAX];
+	bool mc_update;
+	bool is_routed;
+	struct net_device *l2_br_dev, *l3_br_dev;
+
+	ECM_IP_ADDR_TO_NIN6_ADDR(group6, dest_ip);
+	ti = ecm_db_multicast_connection_get_and_ref_first(dest_ip);
+	if (!ti) {
+		DEBUG_WARN("no multicast tuple entry found. Group IP: " ECM_IP_ADDR_OCTAL_FMT , ECM_IP_ADDR_TO_OCTAL(dest_ip));
+		return;
+	}
+
+	while (ti) {
+		struct ecm_classifier_process_response aci_pr;
+
+		memset(&aci_pr, 0, sizeof(aci_pr));
+
+		/*
+		 * We now have a 5-tuple which has been accelerated. Query the MCS bridge to receive a list
+		 * of interfaces left or joined a group for a source.
+		 */
+		memset(mc_dst_dev, 0, sizeof(mc_dst_dev));
+
+		/*
+		 * Get the group IP address stored in tuple_instance and match this with
+		 * the group IP received from MCS update callback.
+		 */
+		ecm_db_multicast_tuple_instance_group_ip_get(ti, grp_ip);
+		if (!ECM_IP_ADDR_MATCH(grp_ip, dest_ip)) {
+			goto find_next_tuple;
+		}
+
+		/*
+		 * Get the source IP address for this entry for the group
+		 */
+		ecm_db_multicast_tuple_instance_source_ip_get(ti, src_ip);
+		ECM_IP_ADDR_TO_NIN6_ADDR(origin6, src_ip);
+
+		/*
+		 * Query bridge snooper for the destination list when given the group and source
+		 * if, 	if_num < 0   mc_bridge_ipv6_get_if has encountered with some error, check for next tuple.
+		 * 	if_num == 0  All slaves have left the group. Deacel the flow.
+		 * 	if_num > 0   An interface leave/Join the group. Process the leave/join interface request.
+		 */
+		if_num = mc_bridge_ipv6_get_if (brdev, &origin6, &group6, ECM_DB_MULTICAST_IF_MAX, mc_dst_dev);
+		if (if_num < 0) {
+			/*
+			 * This may a valid case when all the interface has left a multicast group.
+			 * In this case the MCS will return if_num 0, But we may have an oudated
+			 * interface in multicast interface heirarchy list. At next step we have to
+			 * check whether the DB instance is present or not.
+			 */
+			DEBUG_TRACE("No valid bridge slaves for the group/source\n");
+			goto find_next_tuple;
+		}
+
+		/*
+		 * Get a DB connection instance for the 5-tuple
+		 */
+		ci = ecm_db_multicast_connection_get_from_tuple(ti);
+
+		/*
+		 * The source interface could have joined the group as well.
+		 * In such cases, the destination interface list returned by
+		 * the snooper would include the source interface as well.
+		 * We need to filter the source interface from the list in such cases.
+		 */
+		if (if_num > 0) {
+			if_num = ecm_interface_multicast_filter_src_interface(ci, mc_dst_dev);
+			if (if_num == ECM_DB_IFACE_HEIRARCHY_MAX) {
+				DEBUG_WARN("%px: MCS Snooper Update: no interfaces in from_interfaces list!\n", ci);
+				goto find_next_tuple;
+			}
+		}
+
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+		/*
+		 * All bridge slaves has left the group. If flow is pure bridge, Deacel the connection and return
+		 * If flow is routed, let MFC callback handle this.
+		 *
+		 * If there are no routed interfaces, then decelerate. Else
+		 * we first send an update message to the firmware for the
+		 * interface that have left, before issuing a decelerate
+		 * at a later point via the MFC callback. This is because
+		 * there might be a few seconds delay before MFC issues
+		 * the delete callback
+		 */
+		is_routed = ecm_db_connection_is_routed_get(ci);
+		if (!is_routed) {
+			/*
+			 * L2-only multicast: Update the flow only if the flow's bridge device matches the bridge device passed by MCS.
+			 */
+			if (!if_num) {
+				/*
+				 * Decelerate the flow since there is no active ports left
+				 */
+				feci->decelerate(feci);
+				feci->deref(feci);
+				goto find_next_tuple;
+			}
+
+			/*
+			 * Decelerate the flow if the bridge device from the MCS update does not match the bridge with which flow was created.
+			 */
+			l2_br_dev = ecm_db_multicast_tuple_instance_get_l2_br_dev(ti);
+			if (!l2_br_dev) {
+				DEBUG_WARN("Not found a valid l2_br_dev in ti for bridged mc flow");
+				feci->deref(feci);
+				goto find_next_tuple;
+			}
+
+			if (l2_br_dev != brdev) {
+				DEBUG_WARN("L2 bridge device does not match the MCS update. l2_br_dev:%s brdev:%s", l2_br_dev->name, brdev->name);
+				feci->deref(feci);
+				goto find_next_tuple;
+			}
+		} else {
+			/*
+			 * Check whether the bridge for which we are processing an update,
+			 * is part of the the routed destination interface list for the flow.
+			 * The flow could be one of the below
+			 *
+			 * a. WAN (upstream) <-> br-lan (downstream)
+			 * b. WAN (upstream) <-> br-lan1(downstream), br-lan2 (downstream)
+			 */
+			int i;
+			struct in6_addr ip_src;
+			struct in6_addr ip_grp;
+			uint32_t dst_if_cnt;
+			uint32_t dst_dev[ECM_DB_MULTICAST_IF_MAX];
+
+			/*
+			 * If l3_br_dev is NULL then the we only need to check the ipmr destination list.
+			 */
+			l3_br_dev = ecm_db_multicast_tuple_instance_get_l3_br_dev(ti);
+			if (!l3_br_dev) {
+				goto process_ipmr_entry;
+			}
+
+			/*
+			 * 'brdev' is already part of the multicast interface list, no need to check ipmr entry.
+			 */
+			if (l3_br_dev == brdev) {
+				goto process_packet;
+			}
+
+process_ipmr_entry:
+			memset(dst_dev, 0, sizeof(dst_dev));
+			ECM_IP_ADDR_TO_NIN6_ADDR(ip_src, src_ip);
+			ECM_IP_ADDR_TO_NIN6_ADDR(ip_grp, grp_ip);
+			dst_if_cnt =  ip6mr_find_mfc_entry(&init_net, &ip_src, &ip_grp, ECM_DB_MULTICAST_IF_MAX, dst_dev);
+			if (dst_if_cnt < 0) {
+				/*
+				 * Decelerate the flow since there is no active ports left
+				 */
+				DEBUG_WARN("Not found a valid vif count %d\n", dst_if_cnt);
+				feci->decelerate(feci);
+				feci->deref(feci);
+				goto find_next_tuple;
+			}
+
+			/*
+			 * Update should be allowed for the connection only if 'brdev' is part of ipmr destination interface list.
+			 */
+			for (i = 0; i < dst_if_cnt; i++) {
+				if (dst_dev[i] == brdev->ifindex)
+					goto process_packet;
+			}
+
+			DEBUG_WARN("brdev: %s is neither part of mcproxy configuration nor same as ingress bridge port device.\n", brdev->name);
+			feci->deref(feci);
+			goto find_next_tuple;
+		}
+
+process_packet:
+		/*
+		 * Find out changes to the destination interfaces heirarchy
+		 * of the connection. We try to find out the interfaces that
+		 * have joined new, and the existing interfaces in the list
+		 * that have left seperately.
+		 */
+		memset(&mc_sync, 0, sizeof(mc_sync));
+		spin_lock_bh(&ecm_nss_ipv6_lock);
+		mc_update = ecm_interface_multicast_find_updates_to_iface_list(ci, &mc_sync, 0, true, mc_dst_dev, if_num, brdev);
+		spin_unlock_bh(&ecm_nss_ipv6_lock);
+		if (!mc_update) {
+			/*
+			 * No updates to this multicast flow. Move on to the next
+			 * flow for the same group
+			 */
+			goto find_next_tuple;
+		}
+
+		DEBUG_TRACE("BRIDGE UPDATE callback ===> leave_cnt %d, join_cnt %d\n", mc_sync.if_leave_cnt, mc_sync.if_join_cnt);
+		feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+		/*
+		 * Do we have any new interfaces that have joined?
+		 */
+		if (mc_sync.if_join_cnt) {
+			struct ecm_db_iface_instance *to_list;
+			uint8_t src_node_addr[ETH_ALEN];
+			int32_t if_cnt, to_list_first[ECM_DB_MULTICAST_IF_MAX];
+			uint32_t tuple_instance_flags;
+
+			to_list = (struct ecm_db_iface_instance *)kzalloc(ECM_DB_TO_MCAST_INTERFACES_SIZE, GFP_ATOMIC | __GFP_NOWARN);
+			if (!to_list) {
+				feci->deref(feci);
+				goto find_next_tuple;
+			}
+
+			/*
+			 * Initialize the heirarchy's indices for the 'to_list'
+			 * which will hold the interface heirarchies for the new joinees
+			 */
+			for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+				to_list_first[i] = ECM_DB_IFACE_HEIRARCHY_MAX;
+			}
+
+			ecm_db_connection_node_address_get(ci, ECM_DB_OBJ_DIR_FROM, src_node_addr);
+
+			/*
+			 * Create the interface heirarchy list for the new interfaces. We append this list later to
+			 * the existing list of destination interfaces.
+			 */
+			if_cnt = ecm_interface_multicast_heirarchy_construct_bridged(feci, to_list, brdev, src_ip, dest_ip, mc_sync.if_join_cnt, mc_sync.join_dev, to_list_first, src_node_addr, NULL, NULL);
+			if (!if_cnt) {
+				DEBUG_WARN("Failed to obtain 'to_mcast_update' heirarchy list\n");
+				feci->decelerate(feci);
+				feci->deref(feci);
+				kfree(to_list);
+				goto find_next_tuple;
+			}
+
+			/*
+			 * Append the interface heirarchy array of the new joinees to the existing destination list
+			 */
+			ecm_db_multicast_connection_to_interfaces_update(ci, to_list, to_list_first, mc_sync.if_join_idx);
+
+			/*
+			 * In Routed + Bridge mode, if there is a group leave request arrives for the last
+			 * slave of the bridge then MFC will clear ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG
+			 * in tuple_instance. If the bridge slave joins again then we need to set the flag again
+			 * in tuple_instance here.
+			 */
+			tuple_instance_flags = ecm_db_multicast_tuple_instance_flags_get(ti);
+			if (is_routed && !(tuple_instance_flags & ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG)) {
+				ecm_db_multicast_tuple_instance_flags_set(ti, ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG);
+			}
+
+			/*
+			 * De-ref the updated destination interface list
+			 */
+			for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+				if (mc_sync.if_join_idx[i]) {
+					struct ecm_db_iface_instance *to_list_single;
+					struct ecm_db_iface_instance *to_list_temp[ECM_DB_IFACE_HEIRARCHY_MAX];
+
+					to_list_single = ecm_db_multicast_if_heirarchy_get(to_list, i);
+					ecm_db_multicast_copy_if_heirarchy(to_list_temp, to_list_single);
+					ecm_db_connection_interfaces_deref(to_list_temp, to_list_first[i]);
+				}
+			}
+			kfree(to_list);
+		} else if (mc_sync.if_leave_cnt) {
+			/*
+			 * If these are the last interface set leaving the to interface
+			 * list of the connection, then decelerate the connection
+			 */
+			int mc_to_interface_count = ecm_db_multicast_connection_to_interfaces_get_count(ci);
+
+			if (mc_sync.if_leave_cnt == mc_to_interface_count) {
+				feci->decelerate(feci);
+				feci->deref(feci);
+				DEBUG_INFO("%px: Decelerating the flow as there are no to interfaces in the multicast group: " ECM_IP_ADDR_OCTAL_FMT , feci, ECM_IP_ADDR_TO_OCTAL(dest_ip));
+				goto find_next_tuple;
+			}
+		}
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+		/*
+		 * Verify the 'to' interface list with OVS classifier.
+		 */
+		if (ecm_front_end_is_ovs_bridge_device(brdev) &&
+			ecm_db_multicast_ovs_verify_to_list(ci, &aci_pr)) {
+			/*
+			 * We defunct the flow when the OVS returns "DENY_ACCEL" for the port.
+			 * This can happen when the first port has joined on an OVS bridge
+			 * on a flow that already exists. In this case, OVS needs to see the
+			 * packet to update the flow. So we defunct the existing rule.
+			 */
+			DEBUG_WARN("%px: Verification of the ovs 'to_list' has failed. Hence, defunct the connection: %px\n", feci, feci->ci);
+			ecm_db_connection_make_defunct(ci);
+			feci->deref(feci);
+			goto find_next_tuple;
+		}
+#endif
+		/*
+		 * Push the updates to NSS
+		 */
+		DEBUG_TRACE("%px: Update accel\n", ci);
+		if ((feci->accel_mode <= ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED) ||
+				(feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_ACCEL)) {
+			DEBUG_TRACE("%px: Ignoring wrong mode accel for conn: %px\n", feci, feci->ci);
+			feci->deref(feci);
+			goto find_next_tuple;
+		}
+
+		ret = ecm_nss_multicast_ipv6_connection_update_accelerate(feci, &mc_sync, &aci_pr);
+		if (ret < 0) {
+			feci->decelerate(feci);
+			feci->deref(feci);
+			goto find_next_tuple;
+		}
+
+		feci->deref(feci);
+
+		/*
+		 * Release the interfaces that may have left the connection
+		 */
+		ecm_db_multicast_connection_to_interfaces_leave(ci, &mc_sync);
+
+find_next_tuple:
+		ti_next = ecm_db_multicast_connection_get_and_ref_next(ti);
+		ecm_db_multicast_connection_deref(ti);
+		ti = ti_next;
+	}
+
+}
+
+/*
+ * ecm_nss_multicast_ipv6_connection_instance_alloc()
+ *	Create a front end instance specific for Mcast connection
+ */
+struct ecm_nss_multicast_ipv6_connection_instance *ecm_nss_multicast_ipv6_connection_instance_alloc(
+								bool can_accel,
+								struct ecm_db_connection_instance **nci)
+{
+	struct ecm_nss_multicast_ipv6_connection_instance *nmci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_db_connection_instance *ci;
+
+	if (ecm_nss_ipv6_is_conn_limit_reached()) {
+		DEBUG_TRACE("Reached connection limit\n");
+		return NULL;
+	}
+
+	/*
+	 * Now allocate the new connection
+	 */
+	*nci = ecm_db_connection_alloc();
+	if (!*nci) {
+		DEBUG_WARN("Failed to allocate connection\n");
+		return NULL;
+	}
+
+	ci = *nci;
+
+	nmci = (struct ecm_nss_multicast_ipv6_connection_instance *)kzalloc(sizeof(struct ecm_nss_multicast_ipv6_connection_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!nmci) {
+		DEBUG_WARN("Mcast Front end alloc failed\n");
+		ecm_db_connection_deref(ci);
+		return NULL;
+	}
+
+	/*
+	 * Refs is 1 for the creator of the connection
+	 */
+	feci = (struct ecm_front_end_connection_instance *)nmci;
+	feci->refs = 1;
+	DEBUG_SET_MAGIC(nmci, ECM_NSS_MULTICAST_IPV6_CONNECTION_INSTANCE_MAGIC);
+	spin_lock_init(&feci->lock);
+
+	feci->can_accel = can_accel;
+	feci->accel_mode = (can_accel) ? ECM_FRONT_END_ACCELERATION_MODE_DECEL : ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED;
+	feci->accel_engine = ECM_FRONT_END_ENGINE_NSS;
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	feci->stats.no_action_seen_limit = ecm_nss_ipv6_no_action_limit_default;
+	feci->stats.driver_fail_limit = ecm_nss_ipv6_driver_fail_limit_default;
+	feci->stats.ae_nack_limit = ecm_nss_ipv6_nack_limit_default;
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	/*
+	 * Copy reference to connection - no need to ref ci as ci maintains a ref to this instance instead (this instance persists for as long as ci does)
+	 */
+	feci->ci = ci;
+
+	feci->ip_version = 6;
+
+	/*
+	 * Populate the methods and callbacks
+	 */
+	feci->ref = ecm_nss_multicast_ipv6_connection_ref;
+	feci->deref = ecm_nss_multicast_ipv6_connection_deref;
+	feci->accelerate = ecm_nss_multicast_ipv6_connection_accelerate;
+	feci->decelerate = ecm_nss_multicast_ipv6_connection_decelerate;
+	feci->accel_state_get = ecm_nss_multicast_ipv6_connection_accel_state_get;
+	feci->action_seen = ecm_nss_multicast_ipv6_connection_action_seen;
+	feci->accel_ceased = ecm_nss_multicast_ipv6_connection_accel_ceased;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	feci->state_get = ecm_nss_multicast_ipv6_connection_state_get;
+#endif
+	feci->ae_interface_number_by_dev_get = ecm_nss_common_get_interface_number_by_dev;
+	feci->ae_interface_number_by_dev_type_get = ecm_nss_common_get_interface_number_by_dev_type;
+	feci->ae_interface_type_get = ecm_nss_common_get_interface_type;
+	feci->regenerate = ecm_nss_common_connection_regenerate;
+	feci->multicast_update = ecm_nss_multicast_ipv6_bridge_update_connections;
+
+	feci->get_stats_bitmap = ecm_nss_common_dummy_get_stats_bitmap;
+	feci->set_stats_bitmap = ecm_nss_common_dummy_set_stats_bitmap;
+
+	return nmci;
+}
+
+/*
+ * ecm_nss_multicast_ipv6_br_update_event_callback()
+ * 	Callback received from bridge multicast snooper module in the
+ * 	following events:
+ * 	a.) Updates to a muticast group due to IGMP JOIN/LEAVE.
+ *
+ * 	group: IP multicast group address
+ * 	brdev: bridge netdevice
+ *
+ * This function does the following:
+ * a.) Lookup the tuple_instance table to find any flows through the bridge for the group
+ * b.) Query the MCS bridge using the source and group address, to receive a list
+ *     of bridge slaves for the flow
+ * c.) Process the updates by matching the received bridge slave list with existing
+ *     destination interfaces heirarchy for the CI, and decide whether to delete an
+ *     exiting interface heirarchy or add a new heirarchy.
+ */
+static void ecm_nss_multicast_ipv6_br_update_event_callback(struct net_device *brdev, struct in6_addr *group)
+{
+	ip_addr_t dest_ip;
+	struct in6_addr group6;
+
+	memcpy(&group6, group, sizeof(struct in6_addr));
+	ECM_NIN6_ADDR_TO_IP_ADDR(dest_ip, group6);
+
+	DEBUG_TRACE("IP dst: " ECM_IP_ADDR_OCTAL_FMT , ECM_IP_ADDR_TO_OCTAL(dest_ip));
+
+	ecm_nss_multicast_ipv6_bridge_update_connections(dest_ip, brdev);
+}
+
+/*
+ * ecm_nss_multicast_ipv6_mfc_update_event_callback()
+ * 	Callback called by Linux kernel multicast routing module in the
+ * 	following events:
+ * 	a.) Updates to destination interface lists for a multicast route due to
+ * 	    IGMP JOIN/LEAVE
+ * 	b.) Multicast route delete event
+ *
+ * 	group: IP multicast group address
+ *	origin: IP source for the multicast route
+ *	to_dev_idx[]: Array of ifindex for destination interfaces for the route
+ *	max_to_dev: size of the array
+ *	op: UPDATE or DELETE event
+ *
+ * This function does the following:
+ * a.) Lookup the tuple_instance table to find any accelerated flows for the group/source,
+ *     and access their CI
+ * b.) Process the updates by matching the received destination interface list with existing
+ *     destination interfaces heirarchy for the CI, and decide whether to delete an
+ *     exiting interface heirarchy or add a new heirarchy.
+ */
+static void ecm_nss_multicast_ipv6_mfc_update_event_callback(struct in6_addr *group, struct in6_addr *origin, uint32_t max_to_dev, uint32_t to_dev_idx[], uint8_t op)
+{
+	struct ecm_db_connection_instance *ci;
+	struct ecm_db_multicast_tuple_instance *tuple_instance;
+	struct ecm_db_multicast_tuple_instance *tuple_instance_next;
+	struct ecm_multicast_if_update mc_sync;
+	struct in6_addr origin6;
+	struct in6_addr group6;
+	int32_t vif_cnt;
+	ip_addr_t src_ip;
+	ip_addr_t dest_ip;
+	ip_addr_t src_addr;
+	ip_addr_t grp_addr;
+
+	memcpy(&origin6, origin, sizeof(ip_addr_t));
+	memcpy(&group6, group, sizeof(ip_addr_t));
+
+	ECM_NIN6_ADDR_TO_IP_ADDR(src_ip, origin6);
+	ECM_NIN6_ADDR_TO_IP_ADDR(dest_ip, group6);
+
+	DEBUG_TRACE("IP Packet src: " ECM_IP_ADDR_OCTAL_FMT "dst: " ECM_IP_ADDR_OCTAL_FMT ,
+			                                ECM_IP_ADDR_TO_OCTAL(src_ip),ECM_IP_ADDR_TO_OCTAL(dest_ip));
+
+	/*
+	 * Access the 5-tuple information from the tuple_instance table, using the
+	 * source and group addresses
+	 */
+	tuple_instance = ecm_db_multicast_connection_find_and_ref(src_ip, dest_ip);
+	if (!tuple_instance) {
+		DEBUG_TRACE("MFC_EVENT: Port info is not found\n");
+		return;
+	}
+
+	switch (op) {
+	case IP6MR_MFC_EVENT_UPDATE:
+	{
+		struct ecm_front_end_connection_instance *feci;
+		struct ecm_db_iface_instance *to_list;
+		struct ecm_db_iface_instance *to_list_single;
+		struct ecm_db_iface_instance *to_list_temp[ECM_DB_IFACE_HEIRARCHY_MAX];
+		uint32_t to_list_first[ECM_DB_MULTICAST_IF_MAX];
+		uint32_t i, ret;
+		uint32_t mc_flags = 0;
+		uint32_t tuple_instance_flag = 0;
+		bool br_present_in_dest_dev_list = false;
+		bool mc_update = false;
+
+		/*
+		 * Find the connections belongs to the same source and group address and
+		 * apply the updates received from event handler
+		 */
+		while (tuple_instance) {
+			struct ecm_classifier_process_response aci_pr;
+
+			memset(&aci_pr, 0, sizeof(aci_pr));
+			/*
+			 * Get the source/group IP address for this multicast tuple and match
+			 * with the source and group IP received from the event handler. If
+			 * there is not match found jumps to the next multicast tuple.
+			 */
+			ecm_db_multicast_tuple_instance_source_ip_get(tuple_instance, src_addr);
+			ecm_db_multicast_tuple_instance_group_ip_get(tuple_instance, grp_addr);
+			if (!(ECM_IP_ADDR_MATCH(src_addr, src_ip) && ECM_IP_ADDR_MATCH(grp_addr, dest_ip))) {
+				DEBUG_TRACE("%px: Multicast tuple not matched, try next multicast tuple %d\n", tuple_instance, op);
+				tuple_instance_next = ecm_db_multicast_connection_get_and_ref_next(tuple_instance);
+				ecm_db_multicast_connection_deref(tuple_instance);
+				tuple_instance = tuple_instance_next;
+				continue;
+			}
+
+			/*
+			 * Get the DB connection instance using the tuple_instance, ref to 'ci'
+			 * has been already taken by ecm_db_multicast_connection_find_and_ref()
+			 */
+			ci = ecm_db_multicast_connection_get_from_tuple(tuple_instance);
+			DEBUG_TRACE("%px: update the multicast flow: %px\n", ci, tuple_instance);
+
+			/*
+			 * Check if this multicast connection has a bridge
+			 * device in multicast destination interface list.
+			 */
+			tuple_instance_flag = ecm_db_multicast_tuple_instance_flags_get(tuple_instance);
+			if (tuple_instance_flag & ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG) {
+				mc_flags |= ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG;
+			}
+
+			memset(&mc_sync, 0, sizeof(mc_sync));
+			spin_lock_bh(&ecm_nss_ipv6_lock);
+
+			/*
+			 * Find out changes to the destination interfaces heirarchy
+			 * of the connection. We try to find out the interfaces that
+			 * have joined new, and the existing interfaces in the list
+			 * that have left seperately.
+			 */
+			mc_update = ecm_interface_multicast_find_updates_to_iface_list(ci, &mc_sync, mc_flags, false, to_dev_idx, max_to_dev, NULL);
+			if (!mc_update) {
+				DEBUG_TRACE("%px: no update, check next multicast tuple: %px\n", ci, tuple_instance);
+				spin_unlock_bh(&ecm_nss_ipv6_lock);
+				tuple_instance_next = ecm_db_multicast_connection_get_and_ref_next(tuple_instance);
+				ecm_db_multicast_connection_deref(tuple_instance);
+				tuple_instance = tuple_instance_next;
+				continue;
+			}
+
+			br_present_in_dest_dev_list = ecm_interface_multicast_check_for_br_dev(to_dev_idx, max_to_dev);
+			if (!br_present_in_dest_dev_list) {
+				ecm_db_multicast_tuple_instance_flags_clear(tuple_instance, ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG);
+			}
+
+			spin_unlock_bh(&ecm_nss_ipv6_lock);
+			DEBUG_TRACE("%px: MFC update callback leave_cnt %d, join_cnt %d\n", ci, mc_sync.if_leave_cnt, mc_sync.if_join_cnt);
+
+			feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+			/*
+			 * Do we have any new interfaces that have joined?
+			 */
+			if (mc_sync.if_join_cnt > 0) {
+				to_list = (struct ecm_db_iface_instance *)kzalloc(ECM_DB_TO_MCAST_INTERFACES_SIZE, GFP_ATOMIC | __GFP_NOWARN);
+				if (!to_list) {
+					feci->deref(feci);
+					ecm_db_multicast_connection_deref(tuple_instance);
+					return;
+				}
+
+				/*
+				 * Initialize the heirarchy's indices for the 'to_list'
+				 * which will hold the interface heirarchies for the new joinees
+				 */
+				for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+					to_list_first[i] = ECM_DB_IFACE_HEIRARCHY_MAX;
+				}
+
+				/*
+				 * Create the interface heirarchy list for the new interfaces. We append this list later to
+				 * the existing list of destination interfaces.
+				 */
+				vif_cnt = ecm_interface_multicast_heirarchy_construct_routed(feci, to_list, NULL, src_ip, dest_ip, mc_sync.if_join_cnt, mc_sync.join_dev, to_list_first, true, NULL, NULL);
+				if (vif_cnt == 0) {
+					DEBUG_WARN("Failed to obtain 'to_mcast_update' heirarchy list\n");
+					feci->decelerate(feci);
+					feci->deref(feci);
+					ecm_db_multicast_connection_deref(tuple_instance);
+					kfree(to_list);
+					return;
+				}
+
+				/*
+				 * Append the interface heirarchy array of the new joinees to the existing destination list
+				 */
+				ecm_db_multicast_connection_to_interfaces_update(ci, to_list, to_list_first, mc_sync.if_join_idx);
+
+				/*
+				 * De-ref the updated destination interface list
+				 */
+				for (i = 0; i < ECM_DB_MULTICAST_IF_MAX; i++) {
+					if (mc_sync.if_join_idx[i]) {
+						to_list_single = ecm_db_multicast_if_heirarchy_get(to_list, i);
+						ecm_db_multicast_copy_if_heirarchy(to_list_temp, to_list_single);
+						ecm_db_connection_interfaces_deref(to_list_temp, to_list_first[i]);
+					}
+				}
+				kfree(to_list);
+			}
+
+			if (br_present_in_dest_dev_list && !(tuple_instance_flag & ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG)) {
+				ecm_db_multicast_tuple_instance_flags_set(tuple_instance, ECM_DB_MULTICAST_CONNECTION_BRIDGE_DEV_SET_FLAG);
+			}
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+			/*
+			 * Verify the 'to' interface list with OVS classifier.
+			 */
+			if (ecm_interface_multicast_check_for_ovs_br_dev(to_dev_idx, max_to_dev) &&
+				ecm_db_multicast_ovs_verify_to_list(ci, &aci_pr)) {
+				/*
+				 * We defunct the flow when the OVS returns "DENY_ACCEL" for the port.
+				 * This can happen when the first port has joined on an OVS bridge
+				 * on a flow that already exists. In this case, OVS needs to see the
+				 * packet to update the flow. So we defunct the existing rule.
+				 */
+				DEBUG_TRACE("%px: Verification of the ovs 'to_list' has failed. Hence, defunct the connection: %px\n", feci, feci->ci);
+				ecm_db_connection_make_defunct(ci);
+				feci->deref(feci);
+				ecm_db_multicast_connection_deref(tuple_instance);
+				return;
+			}
+#endif
+			/*
+			 * Push the updates to NSS
+			 */
+			DEBUG_TRACE("%px: Update accel %px\n", ci, tuple_instance);
+			if ((feci->accel_mode <= ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED) ||
+					(feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_ACCEL)) {
+				DEBUG_TRACE("%px: Ignoring wrong mode accel for conn: %px\n", feci, feci->ci);
+				feci->deref(feci);
+				ecm_db_multicast_connection_deref(tuple_instance);
+				return;
+			}
+
+			/*
+			 * Update the new rules in FW. If returns error decelerate the connection
+			 * and flush the Multicast rules.
+			 */
+			ret = ecm_nss_multicast_ipv6_connection_update_accelerate(feci, &mc_sync, &aci_pr);
+			if (ret < 0) {
+				feci->decelerate(feci);
+				feci->deref(feci);
+				ecm_db_multicast_connection_deref(tuple_instance);
+				return;
+			}
+
+			feci->deref(feci);
+
+			/*
+			 * Release the interfaces that may have left the connection
+			 */
+			ecm_db_multicast_connection_to_interfaces_leave(ci, &mc_sync);
+
+			/*
+			 * Move on to the next flow for the same source and group
+			 */
+			tuple_instance_next = ecm_db_multicast_connection_get_and_ref_next(tuple_instance);
+			ecm_db_multicast_connection_deref(tuple_instance);
+			tuple_instance = tuple_instance_next;
+		}
+		break;
+	}
+	case IP6MR_MFC_EVENT_DELETE:
+	{
+		struct ecm_front_end_connection_instance *feci;
+
+		/*
+		 * MFC reports that the multicast connection has died.
+		 * Find the connections belongs to the same source/group address,
+		 * Decelerate connections and free the frontend instance
+		 */
+		while (tuple_instance) {
+			/*
+			 * Get the source/group IP address for this multicast tuple and match
+			 * with the source and group IP received from the event handler. If
+			 * there is not match found jumps to the next multicast tuple.
+			 */
+			ecm_db_multicast_tuple_instance_source_ip_get(tuple_instance, src_addr);
+			ecm_db_multicast_tuple_instance_group_ip_get(tuple_instance, grp_addr);
+			if (!(ECM_IP_ADDR_MATCH(src_addr, src_ip) && ECM_IP_ADDR_MATCH(grp_addr, dest_ip))) {
+				DEBUG_TRACE("%px:Multicast tuple not matched, try next tuple %d\n", tuple_instance, op);
+				tuple_instance_next = ecm_db_multicast_connection_get_and_ref_next(tuple_instance);
+				ecm_db_multicast_connection_deref(tuple_instance);
+				tuple_instance = tuple_instance_next;
+				continue;
+			}
+
+			/*
+			 * Get the DB connection instance using the tuple_instance, ref to 'ci'
+			 * has been already taken by ecm_db_multicast_connection_find_and_ref()
+			 */
+			ci = ecm_db_multicast_connection_get_from_tuple(tuple_instance);
+			DEBUG_TRACE("%px:%d delete the multicast flow: %px\n", ci, op, tuple_instance);
+
+			/*
+			 * Get the front end instance
+			 */
+			feci = ecm_db_connection_front_end_get_and_ref(ci);
+			feci->decelerate(feci);
+			feci->deref(feci);
+
+			/*
+			 * Move on to the next flow for the same source and group
+			 */
+			tuple_instance_next = ecm_db_multicast_connection_get_and_ref_next(tuple_instance);
+			ecm_db_multicast_connection_deref(tuple_instance);
+			tuple_instance = tuple_instance_next;
+		}
+		break;
+	}
+	default:
+		DEBUG_TRACE("Wrong op, shouldn't be here\n");
+		break;
+	}
+
+	return;
+}
+
+/*
+ * ecm_nss_multicast_ipv6_debugfs_init()
+ */
+bool ecm_nss_multicast_ipv6_debugfs_init(struct dentry *dentry)
+{
+	struct dentry *multicast_dentry;
+
+	multicast_dentry = debugfs_create_u32("multicast_accelerated_count", S_IRUGO, dentry,
+						&ecm_nss_multicast_ipv6_accelerated_count);
+	if (!multicast_dentry) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 multicast_accelerated_count file in debugfs\n");
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * ecm_nss_multicast_ipv6_stop()
+ */
+void ecm_nss_multicast_ipv6_stop(int num)
+{
+	ecm_front_end_ipv6_mc_stopped = num;
+}
+
+/*
+ * ecm_nss_multicast_ipv6_init()
+ * 	Register the callbacks for MCS snooper and MFC update
+ */
+int ecm_nss_multicast_ipv6_init(struct dentry *dentry)
+{
+	if (!debugfs_create_u32("ecm_nss_multicast_ipv6_stop", S_IRUGO | S_IWUSR, dentry,
+					(u32 *)&ecm_front_end_ipv6_mc_stopped)) {
+		DEBUG_ERROR("Failed to create ecm front end ipv6 mc stop file in debugfs\n");
+		return -1;
+	}
+
+	/*
+	 * Register multicast update callback to MCS snooper
+	 */
+	mc_bridge_ipv6_update_callback_register(ecm_nss_multicast_ipv6_br_update_event_callback);
+
+	/*
+	 * Register multicast update callbacks to MFC
+	 */
+	ip6mr_register_mfc_event_offload_callback(ecm_nss_multicast_ipv6_mfc_update_event_callback);
+	return 0;
+}
+
+/*
+ * ecm_nss_multicast_ipv6_exit()
+ * 	De-register the callbacks for MCS snooper and MFC update
+ */
+void ecm_nss_multicast_ipv6_exit(void)
+{
+	/*
+	 * De-register multicast update callbacks to
+	 * MFC and MCS snooper
+	 */
+	ip6mr_unregister_mfc_event_offload_callback();
+	mc_bridge_ipv6_update_callback_deregister();
+}
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_multicast_ipv6.h b/qca-nss-ecm/frontends/nss/ecm_nss_multicast_ipv6.h
new file mode 100644
index 0000000..c242649
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_multicast_ipv6.h
@@ -0,0 +1,25 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern struct ecm_nss_multicast_ipv6_connection_instance *ecm_nss_multicast_ipv6_connection_instance_alloc(
+								bool can_accel,
+								struct ecm_db_connection_instance **nci);
+extern bool ecm_nss_multicast_ipv6_connection_defunct_callback(void *arg, int *accel_mode);
+extern bool ecm_nss_multicast_ipv6_debugfs_init(struct dentry *dentry);
+
+extern int ecm_nss_multicast_ipv6_init(struct dentry *dentry);
+
+extern void ecm_nss_multicast_ipv6_exit(void);
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_non_ported_ipv4.c b/qca-nss-ecm/frontends/nss/ecm_nss_non_ported_ipv4.c
new file mode 100644
index 0000000..ec4f365
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_non_ported_ipv4.c
@@ -0,0 +1,1950 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <net/addrconf.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_NON_PORTED_IPV4_DEBUG_LEVEL
+
+#include <nss_api_if.h>
+
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+#include "nss_ipsec_cmn.h"
+#endif
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#include "ecm_nss_non_ported_ipv4.h"
+#include "ecm_nss_ipv4.h"
+#include "ecm_nss_common.h"
+#include "ecm_front_end_common.h"
+
+/*
+ * Magic number
+ */
+#define ECM_NSS_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC 0xEC34
+
+/*
+ * struct ecm_nss_non_ported_ipv4_connection_instance
+ *	A connection specific front end instance for Non-Ported connections
+ */
+struct ecm_nss_non_ported_ipv4_connection_instance {
+	struct ecm_front_end_connection_instance base;		/* Base class */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+static int ecm_nss_non_ported_ipv4_accelerated_count = 0;		/* Number of Non-Ported connections currently offloaded */
+
+#ifdef ECM_INTERFACE_SIT_ENABLE
+#ifdef CONFIG_IPV6_SIT_6RD
+/*
+ * ecm_nss_non_ported_ipv4_sit_set_peer()
+ *	It will set the tunnel's peer when the tunnel is a remote any tunnel.
+ */
+void ecm_nss_non_ported_ipv4_sit_set_peer(struct ecm_nss_non_ported_ipv4_connection_instance *nnpci, struct sk_buff *skb)
+{
+	struct nss_tun6rd_msg tun6rdmsg;
+	struct nss_tun6rd_set_peer_msg *tun6rdpeer;
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *from_nss_iface;
+	int32_t from_ifaces_first;
+	const struct ipv6hdr *iph6;
+	int32_t interface_number;
+	ecm_db_iface_type_t ii_type;
+	ip_addr_t addr;
+	nss_tx_status_t nss_tx_status;
+	struct net_device *dev;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(nnpci->base.ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in from_interfaces list!\n", nnpci);
+		return;
+	}
+
+	from_nss_iface = from_ifaces[from_ifaces_first];
+	ii_type = ecm_db_iface_type_get(from_nss_iface);
+
+	/*
+	 * We handle SIT tunnel only here
+	 */
+	if (ii_type != ECM_DB_IFACE_TYPE_SIT) {
+		DEBUG_WARN("%px: This interface is not the sit tunnel\n", nnpci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		return;
+	}
+
+	/*
+	 * We catch these packets in the tunnel which destination ip address is null
+	 */
+	if (!ecm_db_iface_sit_daddr_is_null(from_nss_iface)) {
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		return;
+	}
+	ecm_db_connection_address_get(nnpci->base.ci, ECM_DB_OBJ_DIR_TO, addr);
+
+	/*
+	 * This message is sent to the NSS through the INNER interface, but we are now in the process
+	 * context of OUTER interface. To get the INNER interface number from the NSS, we use the
+	 * actual net device object and the INNER interface type.
+	 */
+	interface_number = ecm_db_iface_interface_identifier_get(from_nss_iface);
+	dev = dev_get_by_index(&init_net, (uint32_t)interface_number);
+	if (!dev) {
+		DEBUG_WARN("%px: Unable to find the net device with interface index %d\n", nnpci, interface_number);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		return;
+	}
+
+	interface_number = ecm_nss_common_get_interface_number_by_dev_type(dev, NSS_DYNAMIC_INTERFACE_TYPE_TUN6RD_INNER);
+	dev_put(dev);
+
+	nss_tun6rd_msg_init(&tun6rdmsg, (uint16_t)interface_number, NSS_TUN6RD_ADD_UPDATE_PEER,
+			sizeof(struct nss_tun6rd_set_peer_msg), NULL, NULL);
+
+	tun6rdpeer = &tun6rdmsg.msg.peer;
+	ECM_IP_ADDR_TO_HIN4_ADDR(tun6rdpeer->dest, addr);
+	iph6 = (struct ipv6hdr *)skb_inner_network_header(skb);
+	memcpy(tun6rdpeer->ipv6_address, &iph6->daddr, sizeof(struct in6_addr));
+
+	nss_tx_status = nss_tun6rd_tx(nss_tun6rd_get_context(), &tun6rdmsg);
+	if (nss_tx_status != NSS_TX_SUCCESS) {
+		/*
+		 * Nothing to do when faild to xmit the message.
+		 */
+		DEBUG_WARN("SIT Accelerate set rule failed\n");
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		return;
+	}
+	DEBUG_TRACE("%px: SIT[%d] set peer\n"
+		   "ipv4 destination address:%x\n"
+		   "ipv6 destination address::"ECM_IP_ADDR_OCTAL_FMT"\n",
+		nnpci, interface_number, tun6rdpeer->dest, ECM_IP_ADDR_TO_OCTAL(tun6rdpeer->ipv6_address));
+
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+}
+#endif
+#endif
+
+/*
+ * ecm_nss_non_ported_ipv4_connection_callback()
+ *	Callback for handling create ack/nack calls.
+ */
+static void ecm_nss_non_ported_ipv4_connection_callback(void *app_data, struct nss_ipv4_msg *nim)
+{
+	struct nss_ipv4_rule_create_msg *__attribute__((unused))nircm = &nim->msg.rule_create;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_nss_non_ported_ipv4_connection_instance *nnpci;
+	ecm_front_end_acceleration_mode_t result_mode;
+	bool is_defunct = false;
+
+	/*
+	 * Is this a response to a create message?
+	 */
+	if (nim->cm.type != NSS_IPV4_TX_CREATE_RULE_MSG) {
+		DEBUG_ERROR("%px: non_ported create callback with improper type: %d, serial: %u\n", nim, nim->cm.type, serial);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: create callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	nnpci = (struct ecm_nss_non_ported_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_nss_ipv4_accel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: accelerate response for connection: %px, serial: %u\n", nnpci, feci->ci, serial);
+	DEBUG_TRACE("%px: rule_flags: %x, valid_flags: %x\n", nnpci, nircm->rule_flags, nircm->valid_flags);
+	DEBUG_TRACE("%px: flow_ip: %pI4h:%d\n", nnpci, &nircm->tuple.flow_ip, nircm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: %pI4h:%d\n", nnpci, &nircm->tuple.return_ip, nircm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", nnpci, nircm->tuple.protocol);
+
+	/*
+	 * Handle the creation result code.
+	 */
+	DEBUG_TRACE("%px: response: %d\n", nnpci, nim->cm.response);
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		/*
+		 * Creation command failed (specific reason ignored).
+		 */
+		DEBUG_TRACE("%px: accel nack: %d\n", nnpci, nim->cm.error);
+		spin_lock_bh(&feci->lock);
+		DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+		feci->stats.ae_nack++;
+		feci->stats.ae_nack_total++;
+		if (feci->stats.ae_nack >= feci->stats.ae_nack_limit) {
+			/*
+			 * Too many NSS rejections
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_ACCEL_ENGINE;
+		} else {
+			/*
+			 * Revert to decelerated
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+		}
+
+		/*
+		 * If connection is now defunct then set mode to ensure no further accel attempts occur
+		 */
+		if (feci->is_defunct) {
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT;
+		}
+
+		spin_lock_bh(&ecm_nss_ipv4_lock);
+		_ecm_nss_ipv4_accel_pending_clear(feci, result_mode);
+		spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+
+	/*
+	 * If a flush occured before we got the ACK then our acceleration was effectively cancelled on us
+	 * GGG TODO This is a workaround for a NSS message OOO quirk, this should eventually be removed.
+	 */
+	if (feci->stats.flush_happened) {
+		feci->stats.flush_happened = false;
+
+		/*
+		 * Increment the no-action counter.  Our connection was decelerated on us with no action occurring.
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_lock_bh(&ecm_nss_ipv4_lock);
+		_ecm_nss_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	/*
+	 * Create succeeded
+	 */
+
+	/*
+	 * Clear any nack count
+	 */
+	feci->stats.ae_nack = 0;
+
+	/*
+	 * Clear the "accelerate pending" state and move to "accelerated" state bumping
+	 * the accelerated counters to match our new state.
+	 *
+	 * Decelerate may have been attempted while we were "pending accel" and
+	 * this function will return true if that was the case.
+	 * If decelerate was pending then we need to begin deceleration :-(
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+
+	ecm_nss_non_ported_ipv4_accelerated_count++;	/* Protocol specific counter */
+	ecm_nss_ipv4_accelerated_count++;		/* General running counter */
+
+	if (!_ecm_nss_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_ACCEL)) {
+		/*
+		 * Increment the no-action counter, this is reset if offload action is seen
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_unlock_bh(&ecm_nss_ipv4_lock);
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_INFO("%px: Decelerate was pending\n", ci);
+
+	/*
+	 * Check if the pending decelerate was done with the defunct process.
+	 * If it was, set the is_defunct flag of the feci to false for re-try.
+	 */
+	if (feci->is_defunct) {
+		is_defunct = feci->is_defunct;
+		feci->is_defunct = false;
+	}
+
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * If the pending decelerate was done through defunct process, we should
+	 * re-try it here with the same defunct function, because the purpose of that
+	 * process is to remove the connection from the database as well after decelerating it.
+	 */
+	if (is_defunct) {
+		ecm_db_connection_make_defunct(ci);
+	} else {
+		feci->decelerate(feci);
+	}
+
+	/*
+	 * Release the connection.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_nss_non_ported_ipv4_connection_accelerate()
+ *	Accelerate a connection
+ *
+ * GGG TODO Refactor this function into a single function that np, udp and tcp
+ * can all use and reduce the amount of code!
+ */
+static void ecm_nss_non_ported_ipv4_connection_accelerate(struct ecm_front_end_connection_instance *feci,
+                                                                        struct ecm_classifier_process_response *pr, bool is_l2_encap,
+                                                                        struct nf_conn *ct, struct sk_buff *skb)
+{
+	struct ecm_nss_non_ported_ipv4_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv4_connection_instance *)feci;
+	uint16_t regen_occurrances;
+	int32_t from_ifaces_first;
+	int32_t to_ifaces_first;
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *from_nss_iface;
+	struct ecm_db_iface_instance *to_nss_iface;
+	int32_t from_nss_iface_id;
+	int32_t to_nss_iface_id;
+	uint8_t from_nss_iface_address[ETH_ALEN];
+	uint8_t to_nss_iface_address[ETH_ALEN];
+	ip_addr_t addr;
+#if defined(ECM_INTERFACE_L2TPV2_ENABLE) ||  defined(ECM_INTERFACE_PPTP_ENABLE) || defined(ECM_INTERFACE_GRE_TAP_ENABLE) || defined(ECM_INTERFACE_GRE_TUN_ENABLE)
+	struct net_device *dev __attribute__((unused));
+#endif
+	struct nss_ipv4_msg *nim;
+	struct nss_ipv4_rule_create_msg *nircm;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	nss_tx_status_t nss_tx_status;
+	int32_t list_index;
+	int32_t interface_type_counts[ECM_DB_IFACE_TYPE_COUNT];
+	bool rule_invalid;
+	uint8_t dest_mac_xlate[ETH_ALEN];
+	ecm_db_direction_t ecm_dir;
+	ecm_front_end_acceleration_mode_t result_mode;
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+	struct ecm_db_interface_info_pptp pptp_info;
+#endif
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	/*
+	 * Get the re-generation occurrance counter of the connection.
+	 * We compare it again at the end - to ensure that the rule construction has seen no generation
+	 * changes during rule creation.
+	 */
+	regen_occurrances = ecm_db_connection_regeneration_occurrances_get(feci->ci);
+
+	/*
+	 * Test if acceleration is permitted
+	 */
+	if (!ecm_nss_ipv4_accel_pending_set(feci)) {
+		DEBUG_TRACE("%px: Acceleration not permitted: %px\n", feci, feci->ci);
+		return;
+	}
+
+	nim = (struct nss_ipv4_msg *)kzalloc(sizeof(struct nss_ipv4_msg), GFP_ATOMIC | __GFP_NOWARN);
+	if (!nim) {
+		DEBUG_WARN("%px: no memory for nss ipv4 message structure instance: %px\n", feci, feci->ci);
+		ecm_nss_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		return;
+	}
+
+	/*
+	 * Okay construct an accel command.
+	 * Initialise creation structure.
+	 * NOTE: We leverage the app_data void pointer to be our 32 bit connection serial number.
+	 * When we get it back we re-cast it to a uint32 and do a faster connection lookup.
+	 */
+	nss_ipv4_msg_init(nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_CREATE_RULE_MSG,
+			sizeof(struct nss_ipv4_rule_create_msg),
+			ecm_nss_non_ported_ipv4_connection_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nircm = &nim->msg.rule_create;
+	nircm->valid_flags = 0;
+	nircm->rule_flags = 0;
+
+	/*
+	 * Initialize VLAN tag information
+	 */
+	nircm->vlan_primary_rule.ingress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_primary_rule.egress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.ingress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.egress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+
+	/*
+	 * Get the interface lists of the connection, we must have at least one interface in the list to continue
+	 */
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in from_interfaces list!\n", nnpci);
+		goto non_ported_accel_bad_rule;
+	}
+
+	to_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, to_ifaces, ECM_DB_OBJ_DIR_TO);
+	if (to_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in to_interfaces list!\n", nnpci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * First interface in each must be a known nss interface
+	 */
+	from_nss_iface = from_ifaces[from_ifaces_first];
+	to_nss_iface = to_ifaces[to_ifaces_first];
+	from_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(from_nss_iface);
+	to_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(to_nss_iface);
+	if ((from_nss_iface_id < 0) || (to_nss_iface_id < 0)) {
+		DEBUG_TRACE("%px: from_nss_iface_id: %d, to_nss_iface_id: %d\n", nnpci, from_nss_iface_id, to_nss_iface_id);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * Get NSS interface ID of the top interface in heirarchy
+	 */
+	from_nss_iface = from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1];
+	to_nss_iface = to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1];
+	nircm->nexthop_rule.flow_nexthop = ecm_db_iface_ae_interface_identifier_get(from_nss_iface);
+	nircm->nexthop_rule.return_nexthop = ecm_db_iface_ae_interface_identifier_get(to_nss_iface);
+
+	/*
+	 * New rule being created
+	 */
+	nircm->valid_flags |= NSS_IPV4_RULE_CREATE_CONN_VALID;
+
+	/*
+	 * Set Nexthop interface number valid flag
+	 */
+	nircm->valid_flags |= NSS_IPV4_RULE_CREATE_NEXTHOP_VALID;
+
+	/*
+	 * Set interface numbers involved in accelerating this connection.
+	 * These are the outer facing addresses from the heirarchy interface lists we got above.
+	 * These may be overridden later if we detect special interface types e.g. ipsec.
+	 */
+	nircm->conn_rule.flow_interface_num = from_nss_iface_id;
+	nircm->conn_rule.return_interface_num = to_nss_iface_id;
+
+	/*
+	 * Set up the flow and return qos tags
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+		nircm->qos_rule.flow_qos_tag = (uint32_t)pr->flow_qos_tag;
+		nircm->qos_rule.return_qos_tag = (uint32_t)pr->return_qos_tag;
+		nircm->valid_flags |= NSS_IPV4_RULE_CREATE_QOS_VALID;
+	}
+
+#if defined(ECM_CLASSIFIER_DSCP_ENABLE) && defined(ECM_CLASSIFIER_DSCP_IGS)
+	/*
+	 * Set up ingress shaper qostag values.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG) {
+		nircm->igs_rule.igs_flow_qos_tag = (uint16_t)pr->igs_flow_qos_tag;
+		nircm->igs_rule.igs_return_qos_tag = (uint16_t)pr->igs_return_qos_tag;
+		nircm->valid_flags |= NSS_IPV4_RULE_CREATE_IGS_VALID;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+	/*
+	 * Mark the rule as E-MESH Service Prioritization valid.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW) {
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_EMESH_SP;
+	}
+#endif
+
+	/*
+	 * Set the mtu values. These values will be overwritten if the flow is
+	 * a specific tunnel type.
+	 */
+	nircm->conn_rule.flow_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nircm->conn_rule.return_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	/*
+	 * Set the port information. These ports can be overwritten by the PPTP protocol values,
+	 * if the flow belongs to a PPTP tunnel.
+	 */
+	nircm->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nircm->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT);
+	nircm->conn_rule.flow_ident_xlate = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM_NAT);
+	nircm->conn_rule.return_ident_xlate = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	/*
+	 * We know that each outward facing interface is known to the NSS and so this connection could be accelerated.
+	 * However the lists may also specify other interesting details that must be included in the creation command,
+	 * for example, ethernet MAC, VLAN tagging or PPPoE session information.
+	 * We get this information by walking from the outer to the innermost interface for each list and examine the interface types.
+	 *
+	 * Start with the 'from' (src) side.
+	 * NOTE: The lists may contain a complex heirarchy of similar type of interface e.g. multiple vlans or tunnels within tunnels.
+	 * This NSS cannot handle that - there is no way to describe this in the rule - if we see multiple types that would conflict we have to abort.
+	 */
+	DEBUG_TRACE("%px: Examine from/src heirarchy list\n", nnpci);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = from_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_in_dev = NULL;
+#endif
+#if defined(ECM_INTERFACE_GRE_TAP_ENABLE) ||  defined(ECM_INTERFACE_GRE_TUN_ENABLE) || defined(ECM_INTERFACE_PPTP_ENABLE)
+		ip_addr_t saddr;
+		ip_addr_t daddr;
+#endif
+		ii = from_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", nnpci, list_index, ii, ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			ecm_db_iface_bridge_address_get(ii, from_nss_iface_address);
+			if (is_valid_ether_addr(from_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV4_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", nnpci, from_nss_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, from_nss_iface_address);
+			if (is_valid_ether_addr(from_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV4_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", nnpci, from_nss_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", nnpci);
+				break;
+			}
+
+#ifdef ECM_INTERFACE_GRE_TAP_ENABLE
+			dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (dev) {
+				if (dev->priv_flags_ext & IFF_EXT_GRE_V4_TAP) {
+					/*
+					 * Clear QOS_VALID to prevent outer rule from overwriting
+					 * inner flow's QoS classification.
+					 */
+					if (ecm_nss_common_get_interface_type(feci, dev) == NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER) {
+						nircm->valid_flags &= ~NSS_IPV4_RULE_CREATE_QOS_VALID;
+					}
+
+					ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, saddr);
+					ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, daddr);
+					if (!ecm_interface_tunnel_mtu_update(saddr, daddr, ECM_DB_IFACE_TYPE_GRE_TAP, &(nircm->conn_rule.flow_mtu))) {
+						rule_invalid = true;
+						DEBUG_WARN("%px: Unable to get mtu value for the GRE TAP interface\n", nnpci);
+					}
+
+				}
+				dev_put(dev);
+			}
+#endif
+
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, from_nss_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", nnpci, from_nss_iface_address);
+			break;
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+		case ECM_DB_IFACE_TYPE_GRE_TUN:
+			/*
+			 * Clear QOS_VALID to prevent outer rule from overwriting
+			 * inner flow's QoS classification.
+			 */
+			dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (dev) {
+				if (ecm_nss_common_get_interface_type(feci, dev) == NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER) {
+					nircm->valid_flags &= ~NSS_IPV4_RULE_CREATE_QOS_VALID;
+				}
+				dev_put(dev);
+			}
+
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, saddr);
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, daddr);
+			if (!ecm_interface_tunnel_mtu_update(saddr, daddr, ECM_DB_IFACE_TYPE_GRE_TUN, &(nircm->conn_rule.flow_mtu))) {
+				rule_invalid = true;
+				DEBUG_WARN("%px: Unable to get mtu value for the GRE TUN interface\n", nnpci);
+			}
+			break;
+#endif
+
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", nnpci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * Set the PPPoE rule creation structure.
+			 */
+			nircm->pppoe_rule.flow_if_num = ecm_db_iface_ae_interface_identifier_get(ii);
+			if (nircm->pppoe_rule.flow_if_num < 0) {
+				DEBUG_TRACE("%px: PPPoE - acceleration engine flow interface (%d) is not valid\n",
+						nnpci, nircm->pppoe_rule.flow_if_num);
+				rule_invalid = true;
+				break;
+			}
+			nircm->pppoe_rule.flow_if_exist = 1;
+			nircm->valid_flags |= NSS_IPV4_RULE_CREATE_PPPOE_VALID;
+
+			DEBUG_TRACE("%px: PPPoE - exist: %d flow_if_num: %d\n", nnpci,
+					nircm->pppoe_rule.flow_if_exist,
+					nircm->pppoe_rule.flow_if_num);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", nnpci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", nnpci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_in_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_in_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_in_dev, pr->return_qos_tag);
+				dev_put(vlan_in_dev);
+				vlan_in_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.ingress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.ingress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= NSS_IPV4_RULE_CREATE_VLAN_VALID;
+
+			/*
+			 * If we have not yet got an ethernet mac then take this one (very unlikely as mac should have been propagated to the slave (outer) device
+			 */
+			memcpy(from_nss_iface_address, vlan_info.address, ETH_ALEN);
+			if (is_valid_ether_addr(from_nss_iface_address)) {
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", nnpci, from_nss_iface_address);
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+				memcpy(nircm->src_mac_rule.flow_src_mac, from_nss_iface_address, ETH_ALEN);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV4_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID;
+			}
+			DEBUG_TRACE("%px: vlan tag: %x\n", nnpci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", nnpci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", nnpci);
+				break;
+			}
+
+			nircm->conn_rule.flow_interface_num = ecm_nss_common_ipsec_get_ifnum(from_nss_iface_id);
+			nircm->nexthop_rule.flow_nexthop = ecm_nss_common_ipsec_get_ifnum(nircm->nexthop_rule.flow_nexthop);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", nnpci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_PPTP:
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, saddr);
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, daddr);
+			if (!ecm_interface_tunnel_mtu_update(saddr, daddr, ECM_DB_IFACE_TYPE_PPTP, &(nircm->conn_rule.flow_mtu))) {
+				rule_invalid = true;
+				DEBUG_WARN("%px: Unable to get mtu value for the PPTP interface\n", nnpci);
+				break;
+			}
+
+			ecm_db_iface_pptp_session_info_get(ii, &pptp_info);
+
+			nircm->tuple.flow_ident = pptp_info.src_call_id;
+			nircm->tuple.return_ident = pptp_info.dst_call_id;
+			nircm->conn_rule.flow_ident_xlate = pptp_info.src_call_id;
+			nircm->conn_rule.return_ident_xlate = pptp_info.dst_call_id;
+
+			nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_NO_SRC_IDENT;
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: PPTP - unsupported\n", nnpci);
+#endif
+			break;
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", nnpci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+
+	if (rule_invalid) {
+		DEBUG_WARN("%px: from/src Rule invalid\n", nnpci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * Now examine the TO / DEST heirarchy list to construct the destination part of the rule
+	 */
+	DEBUG_TRACE("%px: Examine to/dest heirarchy list\n", nnpci);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = to_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_out_dev = NULL;
+#endif
+
+		ii = to_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", nnpci, list_index, ii, ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			ecm_db_iface_bridge_address_get(ii, to_nss_iface_address);
+			if (is_valid_ether_addr(to_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV4_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", nnpci, to_nss_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, to_nss_iface_address);
+			if (is_valid_ether_addr(to_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV4_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", nnpci, to_nss_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", nnpci);
+				break;
+			}
+
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, to_nss_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", nnpci, to_nss_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", nnpci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * Set the PPPoE rule creation structure.
+			 */
+			nircm->pppoe_rule.return_if_num = ecm_db_iface_ae_interface_identifier_get(ii);
+			if (nircm->pppoe_rule.return_if_num < 0) {
+				DEBUG_TRACE("%px: PPPoE - acceleration engine return interface (%d) is not valid\n",
+						nnpci, nircm->pppoe_rule.return_if_num);
+				rule_invalid = true;
+				break;
+			}
+			nircm->pppoe_rule.return_if_exist = 1;
+			nircm->valid_flags |= NSS_IPV4_RULE_CREATE_PPPOE_VALID;
+
+			DEBUG_TRACE("%px: PPPoE - exist: %d return_if_num: %d\n", nnpci,
+					nircm->pppoe_rule.return_if_exist,
+					nircm->pppoe_rule.return_if_num);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", nnpci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", nnpci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_out_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_out_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_out_dev, pr->flow_qos_tag);
+				dev_put(vlan_out_dev);
+				vlan_out_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.egress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.egress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= NSS_IPV4_RULE_CREATE_VLAN_VALID;
+
+			/*
+			 * If we have not yet got an ethernet mac then take this one (very unlikely as mac should have been propagated to the slave (outer) device
+			 */
+			memcpy(to_nss_iface_address, vlan_info.address, ETH_ALEN);
+			if (is_valid_ether_addr(to_nss_iface_address)) {
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", nnpci, to_nss_iface_address);
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+				memcpy(nircm->src_mac_rule.return_src_mac, to_nss_iface_address, ETH_ALEN);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV4_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: vlan tag: %x\n", nnpci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", nnpci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", nnpci);
+				break;
+			}
+
+			nircm->conn_rule.return_interface_num = ecm_nss_common_ipsec_get_ifnum(to_nss_iface_id);
+			nircm->nexthop_rule.return_nexthop = ecm_nss_common_ipsec_get_ifnum(nircm->nexthop_rule.return_nexthop);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", nnpci);
+#endif
+			break;
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", nnpci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+
+	if (rule_invalid) {
+		DEBUG_WARN("%px: to/dest Rule invalid\n", nnpci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * Routed or bridged?
+	 */
+	if (ecm_db_connection_is_routed_get(feci->ci)) {
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_ROUTED;
+	} else {
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_BRIDGE_FLOW;
+		if (is_l2_encap) {
+			nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_L2_ENCAP;
+		}
+	}
+
+	if (ecm_interface_src_check || ecm_db_connection_is_pppoe_bridged_get(feci->ci)) {
+		DEBUG_INFO("%px: Source interface check flag is enabled\n", nnpci);
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_SRC_INTERFACE_CHECK;
+	}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+	/*
+	 * DSCP information?
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+		nircm->dscp_rule.flow_dscp = pr->flow_dscp;
+		nircm->dscp_rule.return_dscp = pr->return_dscp;
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_DSCP_MARKING;
+		nircm->valid_flags |= NSS_IPV4_RULE_CREATE_DSCP_MARKING_VALID;
+	}
+#endif
+	/*
+	 * Set protocol
+	 */
+	nircm->tuple.protocol = (int32_t)ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * The flow_ip is where the connection established from
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(nircm->tuple.flow_ip, addr);
+
+	/*
+	 * The return_ip is where the connection is established to, however, in the case of ingress
+	 * the return_ip would be the routers WAN IP - i.e. the NAT'ed version.
+	 * Getting the NAT'ed version here works for ingress or egress packets, for egress
+	 * the NAT'ed version would be the same as the normal address
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(nircm->tuple.return_ip, addr);
+
+	/*
+	 * When the packet is forwarded to the next interface get the address the source IP of the
+	 * packet should be translated to.  For egress this is the NAT'ed from address.
+	 * This also works for ingress as the NAT'ed version of the WAN host would be the same as non-NAT'ed
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM_NAT, addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(nircm->conn_rule.flow_ip_xlate, addr);
+
+	/*
+	 * The destination address is what the destination IP is translated to as it is forwarded to the next interface.
+	 * For egress this would yield the normal wan host and for ingress this would correctly NAT back to the LAN host
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(nircm->conn_rule.return_ip_xlate, addr);
+
+	/*
+	 * Get mac addresses.
+	 * The src_mac is the mac address of the node that established the connection.
+	 * This will work whether the from_node is LAN (egress) or WAN (ingress).
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, (uint8_t *)nircm->conn_rule.flow_mac);
+
+	/*
+	 * The dest_mac is more complex.  For egress it is the node address of the 'to' side of the connection.
+	 * For ingress it is the node adress of the NAT'ed 'to' IP.
+	 * Essentially it is the MAC of node associated with create.dest_ip and this is "to nat" side.
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, (uint8_t *)nircm->conn_rule.return_mac);
+
+	/*
+	 * The dest_mac_xlate is the mac address to replace the pkt.dst_mac when a packet is sent to->from
+	 * For bridged connections this does not change.
+	 * For routed connections this is the mac of the 'to' node side of the connection.
+	 */
+	if (ecm_db_connection_is_routed_get(feci->ci)) {
+		ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, dest_mac_xlate);
+	} else {
+		/*
+		 * Bridge flows preserve the MAC addressing
+		 */
+		memcpy(dest_mac_xlate, (uint8_t *)nircm->conn_rule.return_mac, ETH_ALEN);
+	}
+
+	/*
+	 * Refer to the Example 2 and 3 in ecm_nss_ipv4_ip_process() function for egress
+	 * and ingress NAT'ed cases. In these cases, the destination node is the one which has the
+	 * ip_dest_addr. So, above we get the mac address of this host and use that mac address
+	 * for the destination node address in NAT'ed cases.
+	 */
+	ecm_dir = ecm_db_connection_direction_get(feci->ci);
+	if ((ecm_dir == ECM_DB_DIRECTION_INGRESS_NAT) || (ecm_dir == ECM_DB_DIRECTION_EGRESS_NAT)) {
+		memcpy(nircm->conn_rule.return_mac, dest_mac_xlate, ETH_ALEN);
+	}
+
+	/*
+	 * Sync our creation command from the assigned classifiers to get specific additional creation rules.
+	 * NOTE: These are called in ascending order of priority and so the last classifier (highest) shall
+	 * override any preceding classifiers.
+	 * This also gives the classifiers a chance to see that acceleration is being attempted.
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(feci->ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+		struct ecm_classifier_rule_create ecrc;
+		/*
+		 * NOTE: The current classifiers do not sync anything to the underlying accel engines.
+		 * In the future, if any of the classifiers wants to pass any parameter, these parameters
+		 * should be received via this object and copied to the accel engine's create object (nircm).
+		*/
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: sync from: %px, type: %d\n", nnpci, aci, aci->type_get(aci));
+		aci->sync_from_v4(aci, &ecrc);
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Release the interface lists
+	 */
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+	ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+
+	DEBUG_INFO("%px: Non-Ported Accelerate connection %px\n"
+			"Protocol: %d\n"
+			"from_mtu: %u\n"
+			"to_mtu: %u\n"
+			"from_ip: %pI4h:%d\n"
+			"to_ip: %pI4h:%d\n"
+			"from_ip_xlate: %pI4h:%d\n"
+			"to_ip_xlate: %pI4h:%d\n"
+			"from_mac: %pM\n"
+			"to_mac: %pM\n"
+			"src_iface_num: %u\n"
+			"dest_iface_num: %u\n"
+			"src_nexthop_num: %u\n"
+			"dest_nexthop_num: %u\n"
+			"ingress_inner_vlan_tag: %u\n"
+			"egress_inner_vlan_tag: %u\n"
+			"ingress_outer_vlan_tag: %u\n"
+			"egress_outer_vlan_tag: %u\n"
+			"rule_flags: %x\n"
+			"valid_flags: %x\n"
+			"pppoe_return_if_exist: %u\n"
+			"pppoe_return_if_num: %u\n"
+			"pppoe_flow_if_exist: %u\n"
+			"pppoe_flow_if_num: %u\n"
+			"flow_qos_tag: %x (%u)\n"
+			"return_qos_tag: %x (%u)\n"
+			"igs_flow_qos_tag: %x (%u)\n"
+			"igs_return_qos_tag: %x (%u)\n"
+			"flow_dscp: %x\n"
+			"return_dscp: %x\n",
+			nnpci,
+			feci->ci,
+			nircm->tuple.protocol,
+			nircm->conn_rule.flow_mtu,
+			nircm->conn_rule.return_mtu,
+			&nircm->tuple.flow_ip, nircm->tuple.flow_ident,
+			&nircm->tuple.return_ip, nircm->tuple.return_ident,
+			&nircm->conn_rule.flow_ip_xlate, nircm->conn_rule.flow_ident_xlate,
+			&nircm->conn_rule.return_ip_xlate, nircm->conn_rule.return_ident_xlate,
+			nircm->conn_rule.flow_mac,
+			nircm->conn_rule.return_mac,
+			nircm->conn_rule.flow_interface_num,
+			nircm->conn_rule.return_interface_num,
+			nircm->nexthop_rule.flow_nexthop,
+			nircm->nexthop_rule.return_nexthop,
+			nircm->vlan_primary_rule.ingress_vlan_tag,
+			nircm->vlan_primary_rule.egress_vlan_tag,
+			nircm->vlan_secondary_rule.ingress_vlan_tag,
+			nircm->vlan_secondary_rule.egress_vlan_tag,
+			nircm->rule_flags,
+			nircm->valid_flags,
+			nircm->pppoe_rule.return_if_exist,
+			nircm->pppoe_rule.return_if_num,
+			nircm->pppoe_rule.flow_if_exist,
+			nircm->pppoe_rule.flow_if_num,
+			nircm->qos_rule.flow_qos_tag, nircm->qos_rule.flow_qos_tag,
+			nircm->qos_rule.return_qos_tag, nircm->qos_rule.return_qos_tag,
+			nircm->igs_rule.igs_flow_qos_tag, nircm->igs_rule.igs_flow_qos_tag,
+			nircm->igs_rule.igs_return_qos_tag, nircm->igs_rule.igs_return_qos_tag,
+			nircm->dscp_rule.flow_dscp,
+			nircm->dscp_rule.return_dscp);
+
+	/*
+	 * Now that the rule has been constructed we re-compare the generation occurrance counter.
+	 * If there has been a change then we abort because the rule may have been created using
+	 * unstable data - especially if another thread has begun regeneration of the connection state.
+	 * NOTE: This does not prevent a regen from being flagged immediately after this line of code either,
+	 * or while the acceleration rule is in flight to the nss.
+	 * This is only to check for consistency of rule state - not that the state is stale.
+	 * Remember that the connection is marked as "accel pending state" so if a regen is flagged immediately
+	 * after this check passes, the connection will be decelerated and refreshed very quickly.
+	 */
+	if (regen_occurrances != ecm_db_connection_regeneration_occurrances_get(feci->ci)) {
+		DEBUG_INFO("%px: connection:%px regen occurred - aborting accel rule.\n", feci, feci->ci);
+		ecm_nss_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		kfree(nim);
+		return;
+	}
+
+	/*
+	 * Ref the connection before issuing an NSS rule
+	 * This ensures that when the NSS responds to the command - which may even be immediately -
+	 * the callback function can trust the correct ref was taken for its purpose.
+	 * NOTE: remember that this will also implicitly hold the feci.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Call the rule create function
+	 */
+	nss_tx_status = nss_ipv4_tx(ecm_nss_ipv4_nss_ipv4_mgr, nim);
+	if (nss_tx_status == NSS_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;
+		spin_unlock_bh(&feci->lock);
+		kfree(nim);
+		return;
+	}
+
+	kfree(nim);
+
+	/*
+	 * Release that ref!
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * TX failed
+	 */
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Accel mode unexpected: %d\n", nnpci, feci->accel_mode);
+	feci->stats.driver_fail_total++;
+	feci->stats.driver_fail++;
+	if (feci->stats.driver_fail >= feci->stats.driver_fail_limit) {
+		DEBUG_WARN("%px: Accel failed - driver fail limit\n", nnpci);
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DRIVER;
+	} else {
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	_ecm_nss_ipv4_accel_pending_clear(feci, result_mode);
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	spin_unlock_bh(&feci->lock);
+	return;
+
+non_ported_accel_bad_rule:
+	;
+
+	kfree(nim);
+	/*
+	 * Jump to here when rule data is bad and an offload command cannot be constructed
+	 */
+	DEBUG_WARN("%px: Accel failed - bad rule\n", nnpci);
+	ecm_nss_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_FAIL_RULE);
+}
+
+/*
+ * ecm_nss_non_ported_ipv4_connection_destroy_callback()
+ *	Callback for handling destroy ack/nack calls.
+ */
+static void ecm_nss_non_ported_ipv4_connection_destroy_callback(void *app_data, struct nss_ipv4_msg *nim)
+{
+	struct nss_ipv4_rule_destroy_msg *__attribute__((unused))nirdm = &nim->msg.rule_destroy;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_nss_non_ported_ipv4_connection_instance *nnpci;
+
+	/*
+	 * Is this a response to a destroy message?
+	 */
+	if (nim->cm.type != NSS_IPV4_TX_DESTROY_RULE_MSG) {
+		DEBUG_ERROR("%px: non-ported destroy callback with improper type: %d\n", nim, nim->cm.type);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: destroy callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	nnpci = (struct ecm_nss_non_ported_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_nss_ipv4_decel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: decelerate response for connection: %px\n", nnpci, feci->ci);
+	DEBUG_TRACE("%px: flow_ip: %pI4h:%d\n", nnpci, &nirdm->tuple.flow_ip, nirdm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: %pI4h:%d\n", nnpci, &nirdm->tuple.return_ip, nirdm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", nnpci, nirdm->tuple.protocol);
+
+	/*
+	 * Drop decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_ipv4_pending_decel_count--;
+	DEBUG_ASSERT(ecm_nss_ipv4_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If decel is not still pending then it's possible that the NSS ended acceleration by some other reason e.g. flush
+	 * In which case we cannot rely on the response we get here.
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING) {
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connections.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_TRACE("%px: response: %d\n", nnpci, nim->cm.response);
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DECEL;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	/*
+	 * If connection became defunct then set mode so that no further accel/decel attempts occur.
+	 */
+	if (feci->is_defunct) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT_SHORT;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Non-Ported acceleration ends
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_non_ported_ipv4_accelerated_count--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_nss_non_ported_ipv4_accelerated_count >= 0, "Bad non-ported accel counter\n");
+	ecm_nss_ipv4_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_nss_ipv4_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	/*
+	 * Release the connections.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_nss_non_ported_ipv4_connection_decelerate_msg_send()
+ *	Prepares and sends a decelerate message to acceleration engine.
+ */
+static bool ecm_nss_non_ported_ipv4_connection_decelerate_msg_send(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_non_ported_ipv4_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv4_connection_instance *)feci;
+	struct nss_ipv4_msg nim;
+	struct nss_ipv4_rule_destroy_msg *nirdm;
+	ip_addr_t addr;
+	nss_tx_status_t nss_tx_status;
+	bool ret;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	/*
+	 * Increment the decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_ipv4_pending_decel_count++;
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	/*
+	 * Prepare deceleration message
+	 */
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_DESTROY_RULE_MSG,
+			sizeof(struct nss_ipv4_rule_destroy_msg),
+			ecm_nss_non_ported_ipv4_connection_destroy_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nirdm = &nim.msg.rule_destroy;
+	nirdm->tuple.protocol = (int32_t)ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * Get addressing information
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(nirdm->tuple.flow_ip, addr);
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(nirdm->tuple.return_ip, addr);
+	nirdm->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nirdm->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT);
+
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+	if (nirdm->tuple.protocol == IPPROTO_GRE) {
+		struct ecm_db_interface_info_pptp pptp_info;
+		struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+		int32_t from_ifaces_first;
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+
+		/*
+		 * Get the interface lists of the connection, we must have at least one interface in the list to continue
+		 */
+		from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+		if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			DEBUG_WARN("%px: Decel attempt failed - no interfaces in from_interfaces list!\n", nnpci);
+			spin_lock_bh(&feci->lock);
+			spin_unlock_bh(&feci->lock);
+			return false;
+		}
+
+		ii = from_ifaces[from_ifaces_first];
+		ii_type = ecm_db_iface_type_get(ii);
+		DEBUG_TRACE("%px: iface_first: %d, ii: %px, type: %d (%s)\n", nnpci, from_ifaces_first, ii, ii_type, ecm_db_interface_type_to_string(ii_type));
+
+		/*
+		 * For PPTP flows, use PPTP local/peer call-id in place of L4 ports
+		 */
+		if (ECM_DB_IFACE_TYPE_PPTP == ii_type) {
+			ecm_db_iface_pptp_session_info_get(ii, &pptp_info);
+			nirdm->tuple.flow_ident = pptp_info.src_call_id;
+			nirdm->tuple.return_ident = pptp_info.dst_call_id;
+		}
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+	}
+#endif
+	DEBUG_INFO("%px: Non-Ported Connection %px decelerate\n"
+			"protocol: %d\n"
+			"src_ip: %pI4:%d\n"
+			"dest_ip: %pI4:%d\n",
+			nnpci, feci->ci, nirdm->tuple.protocol,
+			&nirdm->tuple.flow_ip, nirdm->tuple.flow_ident,
+			&nirdm->tuple.return_ip, nirdm->tuple.return_ident);
+
+	/*
+	 * Take a ref to the feci->ci so that it will persist until we get a response from the NSS.
+	 * NOTE: This will implicitly hold the feci too.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Destroy the NSS connection cache entry.
+	 */
+	nss_tx_status = nss_ipv4_tx(ecm_nss_ipv4_nss_ipv4_mgr, &nim);
+	if (nss_tx_status == NSS_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;			/* Reset */
+		ret = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return true;
+	}
+
+	/*
+	 * TX failed
+	 */
+	ret = ecm_front_end_destroy_failure_handle(feci);
+
+	/*
+	 * Release the ref take, NSS driver did not accept our command.
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * Could not send the request, decrement the decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_ipv4_pending_decel_count--;
+	DEBUG_ASSERT(ecm_nss_ipv4_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	return ret;
+}
+
+/*
+ * ecm_nss_non_ported_ipv4_connection_decelerate()
+ *     Decelerate a connection
+ */
+static bool ecm_nss_non_ported_ipv4_connection_decelerate(struct ecm_front_end_connection_instance *feci)
+{
+	/*
+	 * Check if accel mode is OK for the deceleration.
+	 */
+	spin_lock_bh(&feci->lock);
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	return ecm_nss_non_ported_ipv4_connection_decelerate_msg_send(feci);
+}
+
+/*
+ * ecm_nss_non_ported_ipv4_connection_defunct_callback()
+ *	Callback to be called when a non-ported connection has become defunct.
+ */
+bool ecm_nss_non_ported_ipv4_connection_defunct_callback(void *arg, int *accel_mode)
+{
+	bool ret;
+	struct ecm_front_end_connection_instance *feci = (struct ecm_front_end_connection_instance *)arg;
+	struct ecm_nss_non_ported_ipv4_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	spin_lock_bh(&feci->lock);
+	/*
+	 * Check if the connection can be defuncted.
+	 */
+	if (!ecm_front_end_common_connection_defunct_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+
+	/*
+	 * If none of the cases matched above, this means the connection is in the
+	 * accel mode, so we force a deceleration.
+	 * NOTE: If the mode is accel pending then the decel will be actioned when that is completed.
+	 */
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	ret = ecm_nss_non_ported_ipv4_connection_decelerate_msg_send(feci);
+
+	/*
+	 * Copy the accel_mode which is returned from the decelerate message function. This value
+	 * will be used in the caller to decide releasing the final reference of the connection.
+	 * But if this function reaches to here, the caller care about the ret. If ret is true,
+	 * the reference will be released regardless of the accel_mode. If ret is false, accel_mode
+	 * will be in the ACCEL state (for destroy re-try) and this state will not be used in the
+	 * caller's decision. It looks for ACCEL_FAIL states.
+	 */
+	spin_lock_bh(&feci->lock);
+	*accel_mode = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+
+	return ret;
+}
+
+/*
+ * ecm_nss_non_ported_ipv4_connection_accel_state_get()
+ *	Get acceleration state
+ */
+static ecm_front_end_acceleration_mode_t ecm_nss_non_ported_ipv4_connection_accel_state_get(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_non_ported_ipv4_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv4_connection_instance *)feci;
+	ecm_front_end_acceleration_mode_t state;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	spin_lock_bh(&feci->lock);
+	state = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+	return state;
+}
+
+/*
+ * ecm_nss_non_ported_ipv4_connection_action_seen()
+ *	Acceleration action / activity has been seen for this connection.
+ *
+ * NOTE: Call the action_seen() method when the NSS has demonstrated that it has offloaded some data for a connection.
+ */
+static void ecm_nss_non_ported_ipv4_connection_action_seen(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_non_ported_ipv4_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	DEBUG_INFO("%px: Action seen\n", nnpci);
+	spin_lock_bh(&feci->lock);
+	feci->stats.no_action_seen = 0;
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_nss_non_ported_ipv4_connection_accel_ceased()
+ *	NSS has indicated that acceleration has stopped.
+ *
+ * NOTE: This is called in response to an NSS self-initiated termination of acceleration.
+ * This must NOT be called because the ECM terminated the acceleration.
+ */
+static void ecm_nss_non_ported_ipv4_connection_accel_ceased(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_non_ported_ipv4_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	DEBUG_INFO("%px: accel ceased\n", nnpci);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If we are in accel-pending state then the NSS has issued a flush out-of-order
+	 * with the ACK/NACK we are actually waiting for.
+	 * To work around this we record a "flush has already happened" and will action it when we finally get that ACK/NACK.
+	 * GGG TODO This should eventually be removed when the NSS honours messaging sequence.
+	 */
+	if (feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING) {
+		feci->stats.flush_happened = true;
+		feci->stats.flush_happened_total++;
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If connection is no longer accelerated by the time we get here just ignore the command
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_ACCEL) {
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If the no_action_seen counter was not reset then acceleration ended without any offload action
+	 */
+	if (feci->stats.no_action_seen) {
+		feci->stats.no_action_seen_total++;
+	}
+
+	/*
+	 * If the no_action_seen indicates successive cessations of acceleration without any offload action occuring
+	 * then we fail out this connection
+	 */
+	if (feci->stats.no_action_seen >= feci->stats.no_action_seen_limit) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_NO_ACTION;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Non-Ported acceleration ends
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_non_ported_ipv4_accelerated_count--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_nss_non_ported_ipv4_accelerated_count >= 0, "Bad non-ported accel counter\n");
+	ecm_nss_ipv4_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_nss_ipv4_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+}
+
+/*
+ * ecm_nss_non_ported_ipv4_connection_ref()
+ *	Ref a connection front end instance
+ */
+static void ecm_nss_non_ported_ipv4_connection_ref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_non_ported_ipv4_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	spin_lock_bh(&feci->lock);
+	feci->refs++;
+	DEBUG_TRACE("%px: nnpci ref %d\n", nnpci, feci->refs);
+	DEBUG_ASSERT(feci->refs > 0, "%px: ref wrap\n", nnpci);
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_nss_non_ported_ipv4_connection_deref()
+ *	Deref a connection front end instance
+ */
+static int ecm_nss_non_ported_ipv4_connection_deref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_non_ported_ipv4_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	spin_lock_bh(&feci->lock);
+	feci->refs--;
+	DEBUG_ASSERT(feci->refs >= 0, "%px: ref wrap\n", nnpci);
+
+	if (feci->refs > 0) {
+		int refs = feci->refs;
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: nnpci deref %d\n", nnpci, refs);
+		return refs;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * We can now destroy the instance
+	 */
+	DEBUG_TRACE("%px: nnpci final\n", nnpci);
+	DEBUG_CLEAR_MAGIC(nnpci);
+	kfree(nnpci);
+
+	return 0;
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_nss_non_ported_ipv4_connection_state_get()
+ *	Return the state of this Non ported front end instance
+ */
+static int ecm_nss_non_ported_ipv4_connection_state_get(struct ecm_front_end_connection_instance *feci, struct ecm_state_file_instance *sfi)
+{
+	struct ecm_nss_non_ported_ipv4_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	return ecm_front_end_common_connection_state_get(feci, sfi, "nss_v4.non_ported");
+}
+#endif
+
+/*
+ * ecm_nss_non_ported_ipv4_connection_instance_alloc()
+ *	Create a front end instance specific for non-ported connection
+ */
+struct ecm_nss_non_ported_ipv4_connection_instance *ecm_nss_non_ported_ipv4_connection_instance_alloc(bool can_accel,
+								int protocol,
+								struct ecm_db_connection_instance **nci)
+{
+	struct ecm_nss_non_ported_ipv4_connection_instance *nnpci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_db_connection_instance *ci;
+
+	if (ecm_nss_ipv4_is_conn_limit_reached()) {
+		DEBUG_TRACE("Reached connection limit\n");
+		return NULL;
+	}
+
+	/*
+	 * Now allocate the new connection
+	 */
+	*nci = ecm_db_connection_alloc();
+	if (!*nci) {
+		DEBUG_WARN("Failed to allocate connection\n");
+		return NULL;
+	}
+
+	ci = *nci;
+
+	nnpci = (struct ecm_nss_non_ported_ipv4_connection_instance *)kzalloc(sizeof(struct ecm_nss_non_ported_ipv4_connection_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!nnpci) {
+		DEBUG_WARN("Non-Ported Front end alloc failed\n");
+		ecm_db_connection_deref(ci);
+		return NULL;
+	}
+
+	/*
+	 * Refs is 1 for the creator of the connection
+	 */
+	feci = (struct ecm_front_end_connection_instance *)nnpci;
+	feci->refs = 1;
+	DEBUG_SET_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC);
+	spin_lock_init(&feci->lock);
+
+	feci->can_accel = can_accel;
+	feci->accel_mode = (can_accel)? ECM_FRONT_END_ACCELERATION_MODE_DECEL : ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED;
+	feci->accel_engine = ECM_FRONT_END_ENGINE_NSS;
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	feci->stats.no_action_seen_limit = ecm_nss_ipv4_no_action_limit_default;
+	feci->stats.driver_fail_limit = ecm_nss_ipv4_driver_fail_limit_default;
+	feci->stats.ae_nack_limit = ecm_nss_ipv4_nack_limit_default;
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	/*
+	 * Copy reference to connection - no need to ref ci as ci maintains a ref to this instance instead (this instance persists for as long as ci does)
+	 */
+	feci->ci = ci;
+
+	feci->ip_version = 4;
+
+	feci->protocol = protocol;
+
+	/*
+	 * Populate the methods and callbacks
+	 */
+	feci->ref = ecm_nss_non_ported_ipv4_connection_ref;
+	feci->deref = ecm_nss_non_ported_ipv4_connection_deref;
+	feci->accelerate = ecm_nss_non_ported_ipv4_connection_accelerate;
+	feci->decelerate = ecm_nss_non_ported_ipv4_connection_decelerate;
+	feci->accel_state_get = ecm_nss_non_ported_ipv4_connection_accel_state_get;
+	feci->action_seen = ecm_nss_non_ported_ipv4_connection_action_seen;
+	feci->accel_ceased = ecm_nss_non_ported_ipv4_connection_accel_ceased;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	feci->state_get = ecm_nss_non_ported_ipv4_connection_state_get;
+#endif
+	feci->ae_interface_number_by_dev_get = ecm_nss_common_get_interface_number_by_dev;
+	feci->ae_interface_number_by_dev_type_get = ecm_nss_common_get_interface_number_by_dev_type;
+	feci->ae_interface_type_get = ecm_nss_common_get_interface_type;
+	feci->regenerate = ecm_nss_common_connection_regenerate;
+
+	feci->get_stats_bitmap = ecm_nss_common_dummy_get_stats_bitmap;
+	feci->set_stats_bitmap = ecm_nss_common_dummy_set_stats_bitmap;
+
+	return nnpci;
+}
+
+/*
+ * ecm_nss_non_ported_ipv4_debugfs_init()
+ */
+bool ecm_nss_non_ported_ipv4_debugfs_init(struct dentry *dentry)
+{
+	if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry,
+					(u32 *)&ecm_nss_non_ported_ipv4_accelerated_count)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 non_ported_accelerated_count file in debugfs\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_non_ported_ipv4.h b/qca-nss-ecm/frontends/nss/ecm_nss_non_ported_ipv4.h
new file mode 100644
index 0000000..f391bf2
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_non_ported_ipv4.h
@@ -0,0 +1,23 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern bool ecm_nss_non_ported_ipv4_debugfs_init(struct dentry *dentry);
+
+extern struct ecm_nss_non_ported_ipv4_connection_instance *ecm_nss_non_ported_ipv4_connection_instance_alloc(
+								bool can_accel, int protocol,
+								struct ecm_db_connection_instance **nci);
+extern bool ecm_nss_non_ported_ipv4_connection_defunct_callback(void *arg, int *accel_mode);
+extern void ecm_nss_non_ported_ipv4_sit_set_peer(struct ecm_nss_non_ported_ipv4_connection_instance *nnpci, struct sk_buff *skb);
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_non_ported_ipv6.c b/qca-nss-ecm/frontends/nss/ecm_nss_non_ported_ipv6.c
new file mode 100644
index 0000000..13e0cc5
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_non_ported_ipv6.c
@@ -0,0 +1,1778 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/debugfs.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/ip6_route.h>
+#include <net/ip6_fib.h>
+#include <net/addrconf.h>
+#include <net/ipv6.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in6.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv6.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv6/nf_conntrack_ipv6.h>
+#include <net/netfilter/ipv6/nf_defrag_ipv6.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_NON_PORTED_IPV6_DEBUG_LEVEL
+
+#include <nss_api_if.h>
+
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+#include "nss_ipsec_cmn.h"
+#endif
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#include "ecm_nss_non_ported_ipv6.h"
+#include "ecm_nss_ipv6.h"
+#include "ecm_nss_common.h"
+#include "ecm_front_end_common.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_NSS_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC 0xEC34
+
+/*
+ * struct ecm_nss_non_ported_ipv6_connection_instance
+ *	A connection specific front end instance for Non-Ported connections
+ */
+struct ecm_nss_non_ported_ipv6_connection_instance {
+	struct ecm_front_end_connection_instance base;		/* Base class */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+static int ecm_nss_non_ported_ipv6_accelerated_count = 0;		/* Number of Non-Ported connections currently offloaded */
+
+/*
+ * ecm_nss_non_ported_ipv6_connection_callback()
+ *	Callback for handling create ack/nack calls.
+ */
+static void ecm_nss_non_ported_ipv6_connection_callback(void *app_data, struct nss_ipv6_msg *nim)
+{
+	struct nss_ipv6_rule_create_msg *nircm = &nim->msg.rule_create;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_nss_non_ported_ipv6_connection_instance *nnpci;
+	ip_addr_t flow_ip;
+	ip_addr_t return_ip;
+	ecm_front_end_acceleration_mode_t result_mode;
+	bool is_defunct = false;
+
+	/*
+	 * Is this a response to a create message?
+	 */
+	if (nim->cm.type != NSS_IPV6_TX_CREATE_RULE_MSG) {
+		DEBUG_ERROR("%px: non_ported create callback with improper type: %d, serial: %u\n", nim, nim->cm.type, serial);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: create callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	nnpci = (struct ecm_nss_non_ported_ipv6_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(flow_ip, nircm->tuple.flow_ip);
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(return_ip, nircm->tuple.return_ip);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_nss_ipv6_accel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: accelerate response for connection: %px, serial: %u\n", nnpci, feci->ci, serial);
+	DEBUG_TRACE("%px: rule_flags: %x, valid_flags: %x\n", nnpci, nircm->rule_flags, nircm->valid_flags);
+	DEBUG_TRACE("%px: flow_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", nnpci, ECM_IP_ADDR_TO_OCTAL(flow_ip), nircm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", nnpci, ECM_IP_ADDR_TO_OCTAL(return_ip), nircm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", nnpci, nircm->tuple.protocol);
+
+	/*
+	 * Handle the creation result code.
+	 */
+	DEBUG_TRACE("%px: response: %d\n", nnpci, nim->cm.response);
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		/*
+		 * Creation command failed (specific reason ignored).
+		 */
+		DEBUG_TRACE("%px: accel nack: %d\n", nnpci, nim->cm.error);
+		spin_lock_bh(&feci->lock);
+		DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+		feci->stats.ae_nack++;
+		feci->stats.ae_nack_total++;
+		if (feci->stats.ae_nack >= feci->stats.ae_nack_limit) {
+			/*
+			 * Too many NSS rejections
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_ACCEL_ENGINE;
+		} else {
+			/*
+			 * Revert to decelerated
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+		}
+
+		/*
+		 * TODO: Why is this differnt than IPv4?
+		 * Clear any decelerate pending flag since we aren't accelerated anyway we can just clear this whether it is set or not
+		 */
+		feci->stats.decelerate_pending = false;
+
+		/*
+		 * If connection is now defunct then set mode to ensure no further accel attempts occur
+		 */
+		if (feci->is_defunct) {
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT;
+		}
+
+		spin_lock_bh(&ecm_nss_ipv6_lock);
+		_ecm_nss_ipv6_accel_pending_clear(feci, result_mode);
+		spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+
+	/*
+	 * If a flush occured before we got the ACK then our acceleration was effectively cancelled on us
+	 * GGG TODO This is a workaround for a NSS message OOO quirk, this should eventually be removed.
+	 */
+	if (feci->stats.flush_happened) {
+		feci->stats.flush_happened = false;
+
+		/*
+		 * Increment the no-action counter.  Our connectin was decelerated on us with no action occurring.
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_lock_bh(&ecm_nss_ipv6_lock);
+		_ecm_nss_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	/*
+	 * Create succeeded
+	 */
+
+	/*
+	 * Clear any nack count
+	 */
+	feci->stats.ae_nack = 0;
+
+	/*
+	 * Clear the "accelerate pending" state and move to "accelerated" state bumping
+	 * the accelerated counters to match our new state.
+	 *
+	 * Decelerate may have been attempted while we were "pending accel" and
+	 * this function will return true if that was the case.
+	 * If decelerate was pending then we need to begin deceleration :-(
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+
+	ecm_nss_non_ported_ipv6_accelerated_count++;	/* Protocol specific counter */
+	ecm_nss_ipv6_accelerated_count++;				/* General running counter */
+
+	if (!_ecm_nss_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_ACCEL)) {
+		/*
+		 * Increment the no-action counter, this is reset if offload action is seen
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_unlock_bh(&ecm_nss_ipv6_lock);
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_INFO("%px: Decelerate was pending\n", ci);
+
+	/*
+	 * Check if the pending decelerate was done with the defunct process.
+	 * If it was, set the is_defunct flag of the feci to false for re-try.
+	 */
+	if (feci->is_defunct) {
+		is_defunct = feci->is_defunct;
+		feci->is_defunct = false;
+	}
+
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * If the pending decelerate was done through defunct process, we should
+	 * re-try it here with the same defunct function, because the purpose of that
+	 * process is to remove the connection from the database as well after decelerating it.
+	 */
+	if (is_defunct) {
+		ecm_db_connection_make_defunct(ci);
+	} else {
+		feci->decelerate(feci);
+	}
+
+	/*
+	 * Release the connection.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_nss_non_ported_ipv6_connection_accelerate()
+ *	Accelerate a connection
+ *
+ * GGG TODO Refactor this function into a single function that np, udp and tcp
+ * can all use and reduce the amount of code!
+ */
+static void ecm_nss_non_ported_ipv6_connection_accelerate(struct ecm_front_end_connection_instance *feci,
+                                                                        struct ecm_classifier_process_response *pr, bool is_l2_encap,
+                                                                        struct nf_conn *ct, struct sk_buff *skb)
+{
+	struct ecm_nss_non_ported_ipv6_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv6_connection_instance *)feci;
+	uint16_t regen_occurrances;
+	int32_t from_ifaces_first;
+	int32_t to_ifaces_first;
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *from_nss_iface;
+	struct ecm_db_iface_instance *to_nss_iface;
+	int32_t from_nss_iface_id;
+	int32_t to_nss_iface_id;
+	uint8_t from_nss_iface_address[ETH_ALEN];
+	uint8_t to_nss_iface_address[ETH_ALEN];
+	struct nss_ipv6_msg *nim;
+	struct nss_ipv6_rule_create_msg *nircm;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	nss_tx_status_t nss_tx_status;
+	int32_t list_index;
+	int32_t interface_type_counts[ECM_DB_IFACE_TYPE_COUNT];
+	bool rule_invalid;
+	ip_addr_t src_ip;
+	ip_addr_t dest_ip;
+	ecm_front_end_acceleration_mode_t result_mode;
+#if defined(ECM_INTERFACE_GRE_TAP_ENABLE) || defined(ECM_INTERFACE_GRE_TUN_ENABLE)
+	struct net_device *dev;
+#endif
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	/*
+	 * Get the re-generation occurrance counter of the connection.
+	 * We compare it again at the end - to ensure that the rule construction has seen no generation
+	 * changes during rule creation.
+	 */
+	regen_occurrances = ecm_db_connection_regeneration_occurrances_get(feci->ci);
+
+	/*
+	 * Test if acceleration is permitted
+	 */
+	if (!ecm_nss_ipv6_accel_pending_set(feci)) {
+		DEBUG_TRACE("%px: Acceleration not permitted: %px\n", feci, feci->ci);
+		return;
+	}
+
+	nim = (struct nss_ipv6_msg *)kzalloc(sizeof(struct nss_ipv6_msg), GFP_ATOMIC | __GFP_NOWARN);
+	if (!nim) {
+		DEBUG_WARN("%px: no memory for nss ipv6 message structure instance: %px\n", feci, feci->ci);
+		ecm_nss_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		return;
+	}
+
+	/*
+	 * Okay construct an accel command.
+	 * Initialise creation structure.
+	 * NOTE: We leverage the app_data void pointer to be our 32 bit connection serial number.
+	 * When we get it back we re-cast it to a uint32 and do a faster connection lookup.
+	 */
+	nss_ipv6_msg_init(nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_CREATE_RULE_MSG,
+			sizeof(struct nss_ipv6_rule_create_msg),
+			ecm_nss_non_ported_ipv6_connection_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nircm = &nim->msg.rule_create;
+	nircm->valid_flags = 0;
+	nircm->rule_flags = 0;
+
+	/*
+	 * Initialize VLAN tag information
+	 */
+	nircm->vlan_primary_rule.ingress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_primary_rule.egress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.ingress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.egress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+
+	/*
+	 * Get the interface lists of the connection, we must have at least one interface in the list to continue
+	 */
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in from_interfaces list!\n", nnpci);
+		goto non_ported_accel_bad_rule;
+	}
+
+	to_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, to_ifaces, ECM_DB_OBJ_DIR_TO);
+	if (to_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in to_interfaces list!\n", nnpci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * First interface in each must be a known nss interface
+	 */
+	from_nss_iface = from_ifaces[from_ifaces_first];
+	to_nss_iface = to_ifaces[to_ifaces_first];
+	from_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(from_nss_iface);
+	to_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(to_nss_iface);
+	if ((from_nss_iface_id < 0) || (to_nss_iface_id < 0)) {
+		DEBUG_TRACE("%px: from_nss_iface_id: %d, to_nss_iface_id: %d\n", nnpci, from_nss_iface_id, to_nss_iface_id);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * Get NSS interface ID of the top interface in heirarchy
+	 */
+	from_nss_iface = from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1];
+	to_nss_iface = to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1];
+	nircm->nexthop_rule.flow_nexthop = ecm_db_iface_ae_interface_identifier_get(from_nss_iface);
+	nircm->nexthop_rule.return_nexthop = ecm_db_iface_ae_interface_identifier_get(to_nss_iface);
+
+	/*
+	 * New rule being created
+	 */
+	nircm->valid_flags |= NSS_IPV6_RULE_CREATE_CONN_VALID;
+
+	/*
+	 * Set Nexthop interface number valid flag
+	 */
+	nircm->valid_flags |= NSS_IPV6_RULE_CREATE_NEXTHOP_VALID;
+
+	/*
+	 * Set interface numbers involved in accelerating this connection.
+	 * These are the outer facing addresses from the heirarchy interface lists we got above.
+	 * These may be overridden later if we detect special interface types e.g. ipsec.
+	 */
+	nircm->conn_rule.flow_interface_num = from_nss_iface_id;
+	nircm->conn_rule.return_interface_num = to_nss_iface_id;
+
+	/*
+	 * Set up the flow and return qos tags
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+		nircm->qos_rule.flow_qos_tag = (uint32_t)pr->flow_qos_tag;
+		nircm->qos_rule.return_qos_tag = (uint32_t)pr->return_qos_tag;
+		nircm->valid_flags |= NSS_IPV6_RULE_CREATE_QOS_VALID;
+	}
+
+#if defined(ECM_CLASSIFIER_DSCP_ENABLE) && defined(ECM_CLASSIFIER_DSCP_IGS)
+	/*
+	 * Set up ingress shaper qostag values.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG) {
+		nircm->igs_rule.igs_flow_qos_tag = (uint16_t)pr->igs_flow_qos_tag;
+		nircm->igs_rule.igs_return_qos_tag = (uint16_t)pr->igs_return_qos_tag;
+		nircm->valid_flags |= NSS_IPV6_RULE_CREATE_IGS_VALID;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+	/*
+	 * Mark the rule as E-MESH Service Prioritization valid.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW) {
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_EMESH_SP;
+	}
+#endif
+
+	/*
+	 * Set the mtu values. These values will be overwritten if the flow is
+	 * a specific tunnel type.
+	 */
+	nircm->conn_rule.flow_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nircm->conn_rule.return_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	/*
+	 * We know that each outward facing interface is known to the NSS and so this connection could be accelerated.
+	 * However the lists may also specify other interesting details that must be included in the creation command,
+	 * for example, ethernet MAC, VLAN tagging or PPPoE session information.
+	 * We get this information by walking from the outer to the innermost interface for each list and examine the interface types.
+	 *
+	 * Start with the 'from' (src) side.
+	 * NOTE: The lists may contain a complex heirarchy of similar type of interface e.g. multiple vlans or tunnels within tunnels.
+	 * This NSS cannot handle that - there is no way to describe this in the rule - if we see multiple types that would conflict we have to abort.
+	 */
+	DEBUG_TRACE("%px: Examine from/src heirarchy list\n", nnpci);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = from_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_in_dev = NULL;
+#endif
+#if defined(ECM_INTERFACE_GRE_TAP_ENABLE) || defined(ECM_INTERFACE_GRE_TUN_ENABLE)
+		ip_addr_t saddr;
+		ip_addr_t daddr;
+#endif
+		ii = from_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", nnpci, list_index, ii, ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			ecm_db_iface_bridge_address_get(ii, from_nss_iface_address);
+			if (is_valid_ether_addr(from_nss_iface_address)) {
+				memcpy(nircm->src_mac_rule.flow_src_mac, from_nss_iface_address, ETH_ALEN);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV6_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", nnpci, from_nss_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, from_nss_iface_address);
+			if (is_valid_ether_addr(from_nss_iface_address)) {
+				memcpy(nircm->src_mac_rule.flow_src_mac, from_nss_iface_address, ETH_ALEN);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV6_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", nnpci, from_nss_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", nnpci);
+				break;
+			}
+
+#ifdef ECM_INTERFACE_GRE_TAP_ENABLE
+			dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (dev) {
+				if (dev->priv_flags_ext & IFF_EXT_GRE_V6_TAP) {
+					/*
+					 * Clear QOS_VALID to prevent outer rule from overwriting
+					 * inner flow's QoS classification.
+					 */
+					if (ecm_nss_common_get_interface_type(feci, dev) == NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER) {
+						nircm->valid_flags &= ~NSS_IPV6_RULE_CREATE_QOS_VALID;
+					}
+
+					ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, saddr);
+					ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, daddr);
+					if (!ecm_interface_tunnel_mtu_update(saddr, daddr, ECM_DB_IFACE_TYPE_GRE_TAP, &(nircm->conn_rule.flow_mtu))) {
+						rule_invalid = true;
+						DEBUG_WARN("%px: Unable to get mtu value for the GRE TAP interface\n", nnpci);
+					}
+				}
+				dev_put(dev);
+			}
+#endif
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, from_nss_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", nnpci, from_nss_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_GRE_TUN:
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+			/*
+			 * Clear QOS_VALID to prevent outer rule from overwriting
+			 * inner flow's QoS classification.
+			 */
+			dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (dev) {
+				if (ecm_nss_common_get_interface_type(feci, dev) == NSS_DYNAMIC_INTERFACE_TYPE_GRE_OUTER) {
+					nircm->valid_flags &= ~NSS_IPV6_RULE_CREATE_QOS_VALID;
+				}
+				dev_put(dev);
+			}
+
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, saddr);
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, daddr);
+			if (!ecm_interface_tunnel_mtu_update(saddr, daddr, ECM_DB_IFACE_TYPE_GRE_TUN, &(nircm->conn_rule.flow_mtu))) {
+				rule_invalid = true;
+				DEBUG_WARN("%px: Unable to get mtu value for the GRE TUN interface\n", nnpci);
+			}
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", nnpci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * Set the PPPoE rule creation structure.
+			 */
+			nircm->pppoe_rule.flow_if_num = ecm_db_iface_ae_interface_identifier_get(ii);
+			if (nircm->pppoe_rule.flow_if_num < 0) {
+				DEBUG_TRACE("%px: PPPoE - acceleration engine flow interface (%d) is not valid\n",
+						nnpci, nircm->pppoe_rule.flow_if_num);
+				rule_invalid = true;
+				break;
+			}
+			nircm->pppoe_rule.flow_if_exist = 1;
+			nircm->valid_flags |= NSS_IPV6_RULE_CREATE_PPPOE_VALID;
+
+			DEBUG_TRACE("%px: PPPoE - exist: %d flow_if_num: %d\n", nnpci,
+					nircm->pppoe_rule.flow_if_exist,
+					nircm->pppoe_rule.flow_if_num);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", nnpci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", nnpci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_in_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_in_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_in_dev, pr->return_qos_tag);
+				dev_put(vlan_in_dev);
+				vlan_in_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.ingress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.ingress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= NSS_IPV6_RULE_CREATE_VLAN_VALID;
+
+			/*
+			 * If we have not yet got an ethernet mac then take this one (very unlikely as mac should have been propagated to the slave (outer) device
+			 */
+			memcpy(from_nss_iface_address, vlan_info.address, ETH_ALEN);
+			if (is_valid_ether_addr(from_nss_iface_address)) {
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", nnpci, from_nss_iface_address);
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+				memcpy(nircm->src_mac_rule.flow_src_mac, from_nss_iface_address, ETH_ALEN);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV6_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: vlan tag: %x\n", nnpci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", nnpci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", nnpci);
+				break;
+			}
+
+			nircm->conn_rule.flow_interface_num = ecm_nss_common_ipsec_get_ifnum(from_nss_iface_id);
+			nircm->nexthop_rule.flow_nexthop = ecm_nss_common_ipsec_get_ifnum(nircm->nexthop_rule.flow_nexthop);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", nnpci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_TUNIPIP6:
+#ifdef ECM_INTERFACE_TUNIPIP6_ENABLE
+			/*
+			 * Clear QOS_VALID to prevent outer rule from overwriting
+			 * inner flow's QoS classification.
+			 */
+			dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (dev) {
+				if (ecm_nss_common_get_interface_type(feci, dev) == NSS_DYNAMIC_INTERFACE_TYPE_TUNIPIP6_OUTER) {
+						nircm->valid_flags &= ~NSS_IPV6_RULE_CREATE_QOS_VALID;
+				}
+				dev_put(dev);
+			}
+#endif
+			break;
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", nnpci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+
+	if (rule_invalid) {
+		DEBUG_WARN("%px: from/src Rule invalid\n", nnpci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * Now examine the TO / DEST heirarchy list to construct the destination part of the rule
+	 */
+	DEBUG_TRACE("%px: Examine to/dest heirarchy list\n", nnpci);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = to_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_out_dev = NULL;
+#endif
+
+		ii = to_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", nnpci, list_index, ii, ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			ecm_db_iface_bridge_address_get(ii, to_nss_iface_address);
+			if (is_valid_ether_addr(to_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV6_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", nnpci, to_nss_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, to_nss_iface_address);
+			if (is_valid_ether_addr(to_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV6_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", nnpci, to_nss_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", nnpci);
+				break;
+			}
+
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, to_nss_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", nnpci, to_nss_iface_address);
+			break;
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", nnpci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * Set the PPPoE rule creation structure.
+			 */
+			nircm->pppoe_rule.return_if_num = ecm_db_iface_ae_interface_identifier_get(ii);
+			if (nircm->pppoe_rule.return_if_num < 0) {
+				DEBUG_TRACE("%px: PPPoE - acceleration engine return interface (%d) is not valid\n",
+						nnpci, nircm->pppoe_rule.return_if_num);
+				rule_invalid = true;
+				break;
+			}
+			nircm->pppoe_rule.return_if_exist = 1;
+			nircm->valid_flags |= NSS_IPV6_RULE_CREATE_PPPOE_VALID;
+
+			DEBUG_TRACE("%px: PPPoE - exist: %d return_if_num: %d\n", nnpci,
+					nircm->pppoe_rule.return_if_exist,
+					nircm->pppoe_rule.return_if_num);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", nnpci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", nnpci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_out_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_out_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_out_dev, pr->flow_qos_tag);
+				dev_put(vlan_out_dev);
+				vlan_out_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.egress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.egress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= NSS_IPV6_RULE_CREATE_VLAN_VALID;
+
+			/*
+			 * If we have not yet got an ethernet mac then take this one (very unlikely as mac should have been propagated to the slave (outer) device
+			 */
+			memcpy(to_nss_iface_address, vlan_info.address, ETH_ALEN);
+			if (is_valid_ether_addr(to_nss_iface_address)) {
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", nnpci, to_nss_iface_address);
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+				memcpy(nircm->src_mac_rule.return_src_mac, to_nss_iface_address, ETH_ALEN);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV6_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: vlan tag: %x\n", nnpci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", nnpci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", nnpci);
+				break;
+			}
+
+			nircm->conn_rule.return_interface_num = ecm_nss_common_ipsec_get_ifnum(to_nss_iface_id);
+			nircm->nexthop_rule.return_nexthop = ecm_nss_common_ipsec_get_ifnum(nircm->nexthop_rule.return_nexthop);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", nnpci);
+#endif
+			break;
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", nnpci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+
+	if (rule_invalid) {
+		DEBUG_WARN("%px: to/dest Rule invalid\n", nnpci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * Routed or bridged?
+	 */
+	if (ecm_db_connection_is_routed_get(feci->ci)) {
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_ROUTED;
+	} else {
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_BRIDGE_FLOW;
+		if (is_l2_encap) {
+			nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_L2_ENCAP;
+		}
+	}
+
+	if (ecm_interface_src_check || ecm_db_connection_is_pppoe_bridged_get(feci->ci)) {
+		DEBUG_INFO("%px: Source interface check flag is enabled\n", nnpci);
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_SRC_INTERFACE_CHECK;
+	}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+	/*
+	 * DSCP information?
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+		nircm->dscp_rule.flow_dscp = pr->flow_dscp;
+		nircm->dscp_rule.return_dscp = pr->return_dscp;
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_DSCP_MARKING;
+		nircm->valid_flags |= NSS_IPV6_RULE_CREATE_DSCP_MARKING_VALID;
+	}
+#endif
+	/*
+	 * Set protocol
+	 */
+	nircm->tuple.protocol = (int32_t)ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * The flow_ip is where the connection established from
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	ECM_IP_ADDR_TO_NSS_IPV6_ADDR(nircm->tuple.flow_ip, src_ip);
+
+	/*
+	 * The return_ip is where the connection is established to
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, dest_ip);
+	ECM_IP_ADDR_TO_NSS_IPV6_ADDR(nircm->tuple.return_ip, dest_ip);
+
+	/*
+	 * Same approach as above for port information
+	 */
+	nircm->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nircm->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT);
+
+	/*
+	 * Get mac addresses.
+	 * The src_mac is the mac address of the node that established the connection.
+	 * This will work whether the from_node is LAN (egress) or WAN (ingress).
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, (uint8_t *)nircm->conn_rule.flow_mac);
+
+	/*
+	 * The dest_mac is the mac address of the node that the connection is esatblished to.
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, (uint8_t *)nircm->conn_rule.return_mac);
+
+	/*
+	 * Sync our creation command from the assigned classifiers to get specific additional creation rules.
+	 * NOTE: These are called in ascending order of priority and so the last classifier (highest) shall
+	 * override any preceding classifiers.
+	 * This also gives the classifiers a chance to see that acceleration is being attempted.
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(feci->ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+		struct ecm_classifier_rule_create ecrc;
+		/*
+		 * NOTE: The current classifiers do not sync anything to the underlying accel engines.
+		 * In the future, if any of the classifiers wants to pass any parameter, these parameters
+		 * should be received via this object and copied to the accel engine's create object (nircm).
+		*/
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: sync from: %px, type: %d\n", nnpci, aci, aci->type_get(aci));
+		aci->sync_from_v6(aci, &ecrc);
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Release the interface lists
+	 */
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+	ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+
+	DEBUG_INFO("%px: NON_PORTED Accelerate connection %px\n"
+			"Protocol: %d\n"
+			"from_mtu: %u\n"
+			"to_mtu: %u\n"
+			"from_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"to_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"from_mac: %pM\n"
+			"to_mac: %pM\n"
+			"src_iface_num: %u\n"
+			"dest_iface_num: %u\n"
+			"src_nexthop_num: %u\n"
+			"dest_nexthop_num: %u\n"
+			"ingress_inner_vlan_tag: %u\n"
+			"egress_inner_vlan_tag: %u\n"
+			"ingress_outer_vlan_tag: %u\n"
+			"egress_outer_vlan_tag: %u\n"
+			"rule_flags: %x\n"
+			"valid_flags: %x\n"
+			"pppoe_return_if_exist: %u\n"
+			"pppoe_return_if_num: %u\n"
+			"pppoe_flow_if_exist: %u\n"
+			"pppoe_flow_if_num: %u\n"
+			"flow_qos_tag: %x (%u)\n"
+			"return_qos_tag: %x (%u)\n"
+			"igs_flow_qos_tag: %x (%u)\n"
+			"igs_return_qos_tag: %x (%u)\n"
+			"flow_dscp: %x\n"
+			"return_dscp: %x\n",
+			nnpci,
+			feci->ci,
+			nircm->tuple.protocol,
+			nircm->conn_rule.flow_mtu,
+			nircm->conn_rule.return_mtu,
+			ECM_IP_ADDR_TO_OCTAL(src_ip), nircm->tuple.flow_ident,
+			ECM_IP_ADDR_TO_OCTAL(dest_ip), nircm->tuple.return_ident,
+			nircm->conn_rule.flow_mac,
+			nircm->conn_rule.return_mac,
+			nircm->conn_rule.flow_interface_num,
+			nircm->conn_rule.return_interface_num,
+			nircm->nexthop_rule.flow_nexthop,
+			nircm->nexthop_rule.return_nexthop,
+			nircm->vlan_primary_rule.ingress_vlan_tag,
+			nircm->vlan_primary_rule.egress_vlan_tag,
+			nircm->vlan_secondary_rule.ingress_vlan_tag,
+			nircm->vlan_secondary_rule.egress_vlan_tag,
+			nircm->rule_flags,
+			nircm->valid_flags,
+			nircm->pppoe_rule.return_if_exist,
+			nircm->pppoe_rule.return_if_num,
+			nircm->pppoe_rule.flow_if_exist,
+			nircm->pppoe_rule.flow_if_num,
+			nircm->qos_rule.flow_qos_tag, nircm->qos_rule.flow_qos_tag,
+			nircm->qos_rule.return_qos_tag, nircm->qos_rule.return_qos_tag,
+			nircm->igs_rule.igs_flow_qos_tag, nircm->igs_rule.igs_flow_qos_tag,
+			nircm->igs_rule.igs_return_qos_tag, nircm->igs_rule.igs_return_qos_tag,
+			nircm->dscp_rule.flow_dscp,
+			nircm->dscp_rule.return_dscp);
+
+	/*
+	 * Now that the rule has been constructed we re-compare the generation occurrance counter.
+	 * If there has been a change then we abort because the rule may have been created using
+	 * unstable data - especially if another thread has begun regeneration of the connection state.
+	 * NOTE: This does not prevent a regen from being flagged immediately after this line of code either,
+	 * or while the acceleration rule is in flight to the nss.
+	 * This is only to check for consistency of rule state - not that the state is stale.
+	 * Remember that the connection is marked as "accel pending state" so if a regen is flagged immediately
+	 * after this check passes, the connection will be decelerated and refreshed very quickly.
+	 */
+	if (regen_occurrances != ecm_db_connection_regeneration_occurrances_get(feci->ci)) {
+		DEBUG_INFO("%px: connection:%px regen occurred - aborting accel rule.\n", feci, feci->ci);
+		ecm_nss_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		kfree(nim);
+		return;
+	}
+
+	/*
+	 * Ref the connection before issuing an NSS rule
+	 * This ensures that when the NSS responds to the command - which may even be immediately -
+	 * the callback function can trust the correct ref was taken for its purpose.
+	 * NOTE: remember that this will also implicitly hold the feci.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Call the rule create function
+	 */
+	nss_tx_status = nss_ipv6_tx(ecm_nss_ipv6_nss_ipv6_mgr, nim);
+	if (nss_tx_status == NSS_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;
+		spin_unlock_bh(&feci->lock);
+		kfree(nim);
+		return;
+	}
+
+	kfree(nim);
+
+	/*
+	 * Release that ref!
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * TX failed
+	 */
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Accel mode unexpected: %d\n", nnpci, feci->accel_mode);
+	feci->stats.driver_fail_total++;
+	feci->stats.driver_fail++;
+	if (feci->stats.driver_fail >= feci->stats.driver_fail_limit) {
+		DEBUG_WARN("%px: Accel failed - driver fail limit\n", nnpci);
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DRIVER;
+	} else {
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	_ecm_nss_ipv6_accel_pending_clear(feci, result_mode);
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	spin_unlock_bh(&feci->lock);
+	return;
+
+non_ported_accel_bad_rule:
+	;
+
+	kfree(nim);
+	/*
+	 * Jump to here when rule data is bad and an offload command cannot be constructed
+	 */
+	DEBUG_WARN("%px: Accel failed - bad rule\n", nnpci);
+	ecm_nss_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_FAIL_RULE);
+}
+
+/*
+ * ecm_nss_non_ported_ipv6_connection_destroy_callback()
+ *	Callback for handling destroy ack/nack calls.
+ */
+static void ecm_nss_non_ported_ipv6_connection_destroy_callback(void *app_data, struct nss_ipv6_msg *nim)
+{
+	struct nss_ipv6_rule_destroy_msg *nirdm = &nim->msg.rule_destroy;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_nss_non_ported_ipv6_connection_instance *nnpci;
+	ip_addr_t flow_ip;
+	ip_addr_t return_ip;
+
+	/*
+	 * Is this a response to a destroy message?
+	 */
+	if (nim->cm.type != NSS_IPV6_TX_DESTROY_RULE_MSG) {
+		DEBUG_ERROR("%px: non_ported destroy callback with improper type: %d\n", nim, nim->cm.type);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: destroy callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	nnpci = (struct ecm_nss_non_ported_ipv6_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(flow_ip, nirdm->tuple.flow_ip);
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(return_ip, nirdm->tuple.return_ip);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_nss_ipv6_decel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: decelerate response for connection: %px\n", nnpci, feci->ci);
+	DEBUG_TRACE("%px: flow_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", nnpci, ECM_IP_ADDR_TO_OCTAL(flow_ip), nirdm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", nnpci, ECM_IP_ADDR_TO_OCTAL(return_ip), nirdm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", nnpci, nirdm->tuple.protocol);
+
+	/*
+	 * Drop decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_ipv6_pending_decel_count--;
+	DEBUG_ASSERT(ecm_nss_ipv6_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If decel is not still pending then it's possible that the NSS ended acceleration by some other reason e.g. flush
+	 * In which case we cannot rely on the response we get here.
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING) {
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connections.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_TRACE("%px: response: %d\n", nnpci, nim->cm.response);
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DECEL;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	/*
+	 * If connection became defunct then set mode so that no further accel/decel attempts occur.
+	 */
+	if (feci->is_defunct) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT_SHORT;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * NON_PORTED acceleration ends
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_non_ported_ipv6_accelerated_count--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_nss_non_ported_ipv6_accelerated_count >= 0, "Bad non_ported accel counter\n");
+	ecm_nss_ipv6_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_nss_ipv6_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	/*
+	 * Release the connections.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_nss_non_ported_ipv6_connection_decelerate_msg_send()
+ *	Prepares and sends a decelerate message to acceleration engine.
+ */
+static bool ecm_nss_non_ported_ipv6_connection_decelerate_msg_send(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_non_ported_ipv6_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv6_connection_instance *)feci;
+	struct nss_ipv6_msg nim;
+	struct nss_ipv6_rule_destroy_msg *nirdm;
+	ip_addr_t src_ip;
+	ip_addr_t dest_ip;
+	nss_tx_status_t nss_tx_status;
+	bool ret;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	/*
+	 * Increment the decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_ipv6_pending_decel_count++;
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	/*
+	 * Prepare deceleration message
+	 */
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_DESTROY_RULE_MSG,
+			sizeof(struct nss_ipv6_rule_destroy_msg),
+			ecm_nss_non_ported_ipv6_connection_destroy_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nirdm = &nim.msg.rule_destroy;
+	nirdm->tuple.protocol = (int32_t)ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * Get addressing information
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	ECM_IP_ADDR_TO_NSS_IPV6_ADDR(nirdm->tuple.flow_ip, src_ip);
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, dest_ip);
+	ECM_IP_ADDR_TO_NSS_IPV6_ADDR(nirdm->tuple.return_ip, dest_ip);
+	nirdm->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nirdm->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT);
+
+	DEBUG_INFO("%px: NON_PORTED Connection %px decelerate\n"
+			"src_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"dest_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n",
+			nnpci, feci->ci,
+			ECM_IP_ADDR_TO_OCTAL(src_ip), nirdm->tuple.flow_ident,
+			ECM_IP_ADDR_TO_OCTAL(dest_ip), nirdm->tuple.return_ident);
+
+	/*
+	 * Take a ref to the feci->ci so that it will persist until we get a response from the NSS.
+	 * NOTE: This will implicitly hold the feci too.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Destroy the NSS connection cache entry.
+	 */
+	nss_tx_status = nss_ipv6_tx(ecm_nss_ipv6_nss_ipv6_mgr, &nim);
+	if (nss_tx_status == NSS_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;
+		spin_unlock_bh(&feci->lock);
+		return true;
+	}
+
+	/*
+	 * TX failed
+	 */
+	ret = ecm_front_end_destroy_failure_handle(feci);
+
+	/*
+	 * Release the ref take, NSS driver did not accept our command.
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * Could not send the request, decrement the decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_ipv6_pending_decel_count--;
+	DEBUG_ASSERT(ecm_nss_ipv6_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	return ret;
+}
+
+/*
+ * ecm_nss_non_ported_ipv6_connection_decelerate()
+ *     Decelerate a connection
+ */
+static bool ecm_nss_non_ported_ipv6_connection_decelerate(struct ecm_front_end_connection_instance *feci)
+{
+	/*
+	 * Check if accel mode is OK for the deceleration.
+	 */
+	spin_lock_bh(&feci->lock);
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	return ecm_nss_non_ported_ipv6_connection_decelerate_msg_send(feci);
+}
+
+/*
+ * ecm_nss_non_ported_ipv6_connection_defunct_callback()
+ *	Callback to be called when a non-ported connection has become defunct.
+ */
+bool ecm_nss_non_ported_ipv6_connection_defunct_callback(void *arg, int *accel_mode)
+{
+	bool ret;
+	struct ecm_front_end_connection_instance *feci = (struct ecm_front_end_connection_instance *)arg;
+	struct ecm_nss_non_ported_ipv6_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	spin_lock_bh(&feci->lock);
+	/*
+	 * Check if the connection can be defuncted.
+	 */
+	if (!ecm_front_end_common_connection_defunct_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+
+	/*
+	 * If none of the cases matched above, this means the connection is in the
+	 * accel mode, so we force a deceleration.
+	 * NOTE: If the mode is accel pending then the decel will be actioned when that is completed.
+	 */
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	ret = ecm_nss_non_ported_ipv6_connection_decelerate_msg_send(feci);
+
+	/*
+	 * Copy the accel_mode which is returned from the decelerate message function. This value
+	 * will be used in the caller to decide releasing the final reference of the connection.
+	 * But if this function reaches to here, the caller care about the ret. If ret is true,
+	 * the reference will be released regardless of the accel_mode. If ret is false, accel_mode
+	 * will be in the ACCEL state (for destroy re-try) and this state will not be used in the
+	 * caller's decision. It looks for ACCEL_FAIL states.
+	 */
+	spin_lock_bh(&feci->lock);
+	*accel_mode = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+
+	return ret;
+}
+
+/*
+ * ecm_nss_non_ported_ipv6_connection_accel_state_get()
+ *	Get acceleration state
+ */
+static ecm_front_end_acceleration_mode_t ecm_nss_non_ported_ipv6_connection_accel_state_get(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_non_ported_ipv6_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv6_connection_instance *)feci;
+	ecm_front_end_acceleration_mode_t state;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	spin_lock_bh(&feci->lock);
+	state = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+	return state;
+}
+
+/*
+ * ecm_nss_non_ported_ipv6_connection_action_seen()
+ *	Acceleration action / activity has been seen for this connection.
+ *
+ * NOTE: Call the action_seen() method when the NSS has demonstrated that it has offloaded some data for a connection.
+ */
+static void ecm_nss_non_ported_ipv6_connection_action_seen(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_non_ported_ipv6_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	DEBUG_INFO("%px: Action seen\n", nnpci);
+	spin_lock_bh(&feci->lock);
+	feci->stats.no_action_seen = 0;
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_nss_non_ported_ipv6_connection_accel_ceased()
+ *	NSS has indicated that acceleration has stopped.
+ *
+ * NOTE: This is called in response to an NSS self-initiated termination of acceleration.
+ * This must NOT be called because the ECM terminated the acceleration.
+ */
+static void ecm_nss_non_ported_ipv6_connection_accel_ceased(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_non_ported_ipv6_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	DEBUG_INFO("%px: accel ceased\n", nnpci);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If we are in accel-pending state then the NSS has issued a flush out-of-order
+	 * with the ACK/NACK we are actually waiting for.
+	 * To work around this we record a "flush has already happened" and will action it when we finally get that ACK/NACK.
+	 * GGG TODO This should eventually be removed when the NSS honours messaging sequence.
+	 */
+	if (feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING) {
+		feci->stats.flush_happened = true;
+		feci->stats.flush_happened_total++;
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If connection is no longer accelerated by the time we get here just ignore the command
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_ACCEL) {
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If the no_action_seen counter was not reset then acceleration ended without any offload action
+	 */
+	if (feci->stats.no_action_seen) {
+		feci->stats.no_action_seen_total++;
+	}
+
+	/*
+	 * If the no_action_seen indicates successive cessations of acceleration without any offload action occuring
+	 * then we fail out this connection
+	 */
+	if (feci->stats.no_action_seen >= feci->stats.no_action_seen_limit) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_NO_ACTION;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Non-Ported acceleration ends
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_non_ported_ipv6_accelerated_count--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_nss_non_ported_ipv6_accelerated_count >= 0, "Bad non-ported accel counter\n");
+	ecm_nss_ipv6_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_nss_ipv6_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+}
+
+/*
+ * ecm_nss_non_ported_ipv6_connection_ref()
+ *	Ref a connection front end instance
+ */
+static void ecm_nss_non_ported_ipv6_connection_ref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_non_ported_ipv6_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	spin_lock_bh(&feci->lock);
+	feci->refs++;
+	DEBUG_TRACE("%px: nnpci ref %d\n", nnpci, feci->refs);
+	DEBUG_ASSERT(feci->refs > 0, "%px: ref wrap\n", nnpci);
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_nss_non_ported_ipv6_connection_deref()
+ *	Deref a connection front end instance
+ */
+static int ecm_nss_non_ported_ipv6_connection_deref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_non_ported_ipv6_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	spin_lock_bh(&feci->lock);
+	feci->refs--;
+	DEBUG_ASSERT(feci->refs >= 0, "%px: ref wrap\n", nnpci);
+
+	if (feci->refs > 0) {
+		int refs = feci->refs;
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: nnpci deref %d\n", nnpci, refs);
+		return refs;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * We can now destroy the instance
+	 */
+	DEBUG_TRACE("%px: nnpci final\n", nnpci);
+	DEBUG_CLEAR_MAGIC(nnpci);
+	kfree(nnpci);
+
+	return 0;
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_nss_non_ported_ipv6_connection_state_get()
+ *	Return the state of this Non ported front end instance
+ */
+static int ecm_nss_non_ported_ipv6_connection_state_get(struct ecm_front_end_connection_instance *feci, struct ecm_state_file_instance *sfi)
+{
+	struct ecm_nss_non_ported_ipv6_connection_instance *nnpci = (struct ecm_nss_non_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	return ecm_front_end_common_connection_state_get(feci, sfi, "nss_v6.non_ported");
+}
+#endif
+
+/*
+ * ecm_nss_non_ported_ipv6_connection_instance_alloc()
+ *	Create a front end instance specific for non-ported connection
+ */
+struct ecm_nss_non_ported_ipv6_connection_instance *ecm_nss_non_ported_ipv6_connection_instance_alloc(
+									bool can_accel, int protocol,
+								struct ecm_db_connection_instance **nci)
+{
+	struct ecm_nss_non_ported_ipv6_connection_instance *nnpci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_db_connection_instance *ci;
+
+	if (ecm_nss_ipv6_is_conn_limit_reached()) {
+		DEBUG_TRACE("Reached connection limit\n");
+		return NULL;
+	}
+
+	/*
+	 * Now allocate the new connection
+	 */
+	*nci = ecm_db_connection_alloc();
+	if (!*nci) {
+		DEBUG_WARN("Failed to allocate connection\n");
+		return NULL;
+	}
+
+	ci = *nci;
+
+	nnpci = (struct ecm_nss_non_ported_ipv6_connection_instance *)kzalloc(sizeof(struct ecm_nss_non_ported_ipv6_connection_instance), GFP_ATOMIC | __GFP_NOWARN);
+
+	if (!nnpci) {
+		DEBUG_WARN("Non-Ported Front end alloc failed\n");
+		ecm_db_connection_deref(ci);
+		return NULL;
+	}
+
+	/*
+	 * Refs is 1 for the creator of the connection
+	 */
+	feci = (struct ecm_front_end_connection_instance *)nnpci;
+	feci->refs = 1;
+	DEBUG_SET_MAGIC(nnpci, ECM_NSS_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC);
+	spin_lock_init(&feci->lock);
+
+	feci->can_accel = can_accel;
+	feci->accel_mode = (can_accel) ? ECM_FRONT_END_ACCELERATION_MODE_DECEL : ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED;
+	feci->accel_engine = ECM_FRONT_END_ENGINE_NSS;
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	feci->stats.no_action_seen_limit = ecm_nss_ipv6_no_action_limit_default;
+	feci->stats.driver_fail_limit = ecm_nss_ipv6_driver_fail_limit_default;
+	feci->stats.ae_nack_limit = ecm_nss_ipv6_nack_limit_default;
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	/*
+	 * Copy reference to connection - no need to ref ci as ci maintains a ref to this instance instead (this instance persists for as long as ci does)
+	 */
+	feci->ci = ci;
+
+	feci->ip_version = 6;
+
+	feci->protocol = protocol;
+
+	/*
+	 * Populate the methods and callbacks
+	 */
+	feci->ref = ecm_nss_non_ported_ipv6_connection_ref;
+	feci->deref = ecm_nss_non_ported_ipv6_connection_deref;
+	feci->accelerate = ecm_nss_non_ported_ipv6_connection_accelerate;
+	feci->decelerate = ecm_nss_non_ported_ipv6_connection_decelerate;
+	feci->accel_state_get = ecm_nss_non_ported_ipv6_connection_accel_state_get;
+	feci->action_seen = ecm_nss_non_ported_ipv6_connection_action_seen;
+	feci->accel_ceased = ecm_nss_non_ported_ipv6_connection_accel_ceased;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	feci->state_get = ecm_nss_non_ported_ipv6_connection_state_get;
+#endif
+	feci->ae_interface_number_by_dev_get = ecm_nss_common_get_interface_number_by_dev;
+	feci->ae_interface_number_by_dev_type_get = ecm_nss_common_get_interface_number_by_dev_type;
+	feci->ae_interface_type_get = ecm_nss_common_get_interface_type;
+	feci->regenerate = ecm_nss_common_connection_regenerate;
+
+	feci->get_stats_bitmap = ecm_nss_common_dummy_get_stats_bitmap;
+	feci->set_stats_bitmap = ecm_nss_common_dummy_set_stats_bitmap;
+
+	return nnpci;
+}
+
+/*
+ * ecm_nss_non_ported_ipv6_debugfs_init()
+ */
+bool ecm_nss_non_ported_ipv6_debugfs_init(struct dentry *dentry)
+{
+	if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry,
+					(u32 *)&ecm_nss_non_ported_ipv6_accelerated_count)) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 non_ported_accelerated_count file in debugfs\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_non_ported_ipv6.h b/qca-nss-ecm/frontends/nss/ecm_nss_non_ported_ipv6.h
new file mode 100644
index 0000000..851b55a
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_non_ported_ipv6.h
@@ -0,0 +1,23 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern bool ecm_nss_non_ported_ipv6_debugfs_init(struct dentry *dentry);
+
+extern struct ecm_nss_non_ported_ipv6_connection_instance *ecm_nss_non_ported_ipv6_connection_instance_alloc(
+								bool can_accel,
+								int protocol,
+								struct ecm_db_connection_instance **nci);
+extern bool ecm_nss_non_ported_ipv6_connection_defunct_callback(void *arg, int *accel_mode);
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_ported_ipv4.c b/qca-nss-ecm/frontends/nss/ecm_nss_ported_ipv4.c
new file mode 100644
index 0000000..6375b6b
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_ported_ipv4.c
@@ -0,0 +1,2030 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/debugfs.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <net/addrconf.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+#include <net/vxlan.h>
+#endif
+#include <linux/netfilter/nf_conntrack_tftp.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_PORTED_IPV4_DEBUG_LEVEL
+
+#include <nss_api_if.h>
+
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+#include "nss_ipsec_cmn.h"
+#endif
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#include "ecm_nss_ported_ipv4.h"
+#include "ecm_nss_ipv4.h"
+#include "ecm_nss_common.h"
+#include "ecm_front_end_common.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_NSS_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC 0xEB12
+
+/*
+ * Protocol type that ported file supports.
+ */
+enum ecm_nss_ported_ipv4_proto_types {
+	ECM_NSS_PORTED_IPV4_PROTO_TCP = 0,
+	ECM_NSS_PORTED_IPV4_PROTO_UDP,
+	ECM_NSS_PORTED_IPV4_PROTO_MAX
+
+};
+
+/*
+ * struct ecm_nss_ipv4_ported_connection_instance
+ *	A connection specific front end instance for PORTED connections
+ */
+struct ecm_nss_ported_ipv4_connection_instance {
+	struct ecm_front_end_connection_instance base;		/* Base class */
+	uint8_t ported_accelerated_count_index;			/* Index value of accelerated count array (UDP or TCP) */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+static int ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_MAX] = {0};
+						/* Array of Number of TCP and UDP connections currently offloaded */
+
+/*
+ * Expose what should be a static flag in the TCP connection tracker.
+ */
+#ifdef ECM_OPENWRT_SUPPORT
+extern int nf_ct_tcp_no_window_check;
+#endif
+extern int nf_ct_tcp_be_liberal;
+
+/*
+ * ecm_nss_ported_ipv4_connection_callback()
+ *	Callback for handling create ack/nack calls.
+ */
+static void ecm_nss_ported_ipv4_connection_callback(void *app_data, struct nss_ipv4_msg *nim)
+{
+	struct nss_ipv4_rule_create_msg * __attribute__((unused)) nircm = &nim->msg.rule_create;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_nss_ported_ipv4_connection_instance *npci;
+	ecm_front_end_acceleration_mode_t result_mode;
+	bool is_defunct = false;
+
+	/*
+	 * Is this a response to a create message?
+	 */
+	if (nim->cm.type != NSS_IPV4_TX_CREATE_RULE_MSG) {
+		DEBUG_ERROR("%px: ported create callback with improper type: %d, serial: %u\n", nim, nim->cm.type, serial);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: create callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	npci = (struct ecm_nss_ported_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_nss_ipv4_accel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: accelerate response for connection: %px, serial: %u\n", npci, feci->ci, serial);
+	DEBUG_TRACE("%px: rule_flags: %x, valid_flags: %x\n", npci, nircm->rule_flags, nircm->valid_flags);
+	DEBUG_TRACE("%px: flow_ip: %pI4h:%d\n", npci, &nircm->tuple.flow_ip, nircm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: %pI4h:%d\n", npci, &nircm->tuple.return_ip, nircm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", npci, nircm->tuple.protocol);
+
+	/*
+	 * Handle the creation result code.
+	 */
+	DEBUG_TRACE("%px: response: %d\n", npci, nim->cm.response);
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		/*
+		 * Creation command failed (specific reason ignored).
+		 */
+		DEBUG_TRACE("%px: accel nack: %d\n", npci, nim->cm.error);
+		spin_lock_bh(&feci->lock);
+		DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+		feci->stats.ae_nack++;
+		feci->stats.ae_nack_total++;
+		if (feci->stats.ae_nack >= feci->stats.ae_nack_limit) {
+			/*
+			 * Too many NSS rejections
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_ACCEL_ENGINE;
+		} else {
+			/*
+			 * Revert to decelerated
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+		}
+
+		/*
+		 * If connection is now defunct then set mode to ensure no further accel attempts occur
+		 */
+		if (feci->is_defunct) {
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT;
+		}
+
+		spin_lock_bh(&ecm_nss_ipv4_lock);
+		_ecm_nss_ipv4_accel_pending_clear(feci, result_mode);
+		spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+
+	/*
+	 * If a flush occured before we got the ACK then our acceleration was effectively cancelled on us
+	 * GGG TODO This is a workaround for a NSS message OOO quirk, this should eventually be removed.
+	 */
+	if (feci->stats.flush_happened) {
+		feci->stats.flush_happened = false;
+
+		/*
+		 * Increment the no-action counter.  Our connection was decelerated on us with no action occurring.
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_lock_bh(&ecm_nss_ipv4_lock);
+		_ecm_nss_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	/*
+	 * Create succeeded
+	 */
+
+	/*
+	 * Clear any nack count
+	 */
+	feci->stats.ae_nack = 0;
+
+	/*
+	 * Clear the "accelerate pending" state and move to "accelerated" state bumping
+	 * the accelerated counters to match our new state.
+	 *
+	 * Decelerate may have been attempted while we were "pending accel" and
+	 * this function will return true if that was the case.
+	 * If decelerate was pending then we need to begin deceleration :-(
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+
+	ecm_nss_ported_ipv4_accelerated_count[npci->ported_accelerated_count_index]++;	/* Protocol specific counter */
+	ecm_nss_ipv4_accelerated_count++;		/* General running counter */
+
+	if (!_ecm_nss_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_ACCEL)) {
+		/*
+		 * Increment the no-action counter, this is reset if offload action is seen
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_unlock_bh(&ecm_nss_ipv4_lock);
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_INFO("%px: Decelerate was pending\n", ci);
+
+	/*
+	 * Check if the pending decelerate was done with the defunct process.
+	 * If it was, set the is_defunct flag of the feci to false for re-try.
+	 */
+	if (feci->is_defunct) {
+		is_defunct = feci->is_defunct;
+		feci->is_defunct = false;
+	}
+
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * If the pending decelerate was done through defunct process, we should
+	 * re-try it here with the same defunct function, because the purpose of that
+	 * process is to remove the connection from the database as well after decelerating it.
+	 */
+	if (is_defunct) {
+		ecm_db_connection_make_defunct(ci);
+	} else {
+		feci->decelerate(feci);
+	}
+
+	/*
+	 * Release the connection.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_nss_ported_ipv4_connection_accelerate()
+ *	Accelerate a connection
+ */
+static void ecm_nss_ported_ipv4_connection_accelerate(struct ecm_front_end_connection_instance *feci,
+									struct ecm_classifier_process_response *pr, bool is_l2_encap,
+									struct nf_conn *ct, struct sk_buff *skb)
+{
+	struct ecm_nss_ported_ipv4_connection_instance *npci = (struct ecm_nss_ported_ipv4_connection_instance *)feci;
+	uint16_t regen_occurrances;
+	int protocol;
+	int32_t from_ifaces_first;
+	int32_t to_ifaces_first;
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *from_nss_iface;
+	struct ecm_db_iface_instance *to_nss_iface;
+	int32_t from_nss_iface_id;
+	int32_t to_nss_iface_id;
+	uint8_t from_nss_iface_address[ETH_ALEN];
+	uint8_t to_nss_iface_address[ETH_ALEN];
+	ip_addr_t addr;
+	struct nss_ipv4_msg *nim;
+	struct nss_ipv4_rule_create_msg *nircm;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	nss_tx_status_t nss_tx_status;
+	int32_t list_index;
+	int32_t interface_type_counts[ECM_DB_IFACE_TYPE_COUNT];
+	bool rule_invalid;
+	uint8_t dest_mac_xlate[ETH_ALEN];
+	ecm_db_direction_t ecm_dir;
+	ecm_front_end_acceleration_mode_t result_mode;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	/*
+	 * Get the re-generation occurrance counter of the connection.
+	 * We compare it again at the end - to ensure that the rule construction has seen no generation
+	 * changes during rule creation.
+	 */
+	regen_occurrances = ecm_db_connection_regeneration_occurrances_get(feci->ci);
+
+	/*
+	 * Test if acceleration is permitted
+	 */
+	if (!ecm_nss_ipv4_accel_pending_set(feci)) {
+		DEBUG_TRACE("%px: Acceleration not permitted: %px\n", feci, feci->ci);
+		return;
+	}
+
+	nim = (struct nss_ipv4_msg *)kzalloc(sizeof(struct nss_ipv4_msg), GFP_ATOMIC | __GFP_NOWARN);
+	if (!nim) {
+		DEBUG_WARN("%px: no memory for nss ipv4 message structure instance: %px\n", feci, feci->ci);
+		ecm_nss_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		return;
+	}
+
+	/*
+	 * Okay construct an accel command.
+	 * Initialise creation structure.
+	 * NOTE: We leverage the app_data void pointer to be our 32 bit connection serial number.
+	 * When we get it back we re-cast it to a uint32 and do a faster connection lookup.
+	 */
+	nss_ipv4_msg_init(nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_CREATE_RULE_MSG,
+			sizeof(struct nss_ipv4_rule_create_msg),
+			ecm_nss_ported_ipv4_connection_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nircm = &nim->msg.rule_create;
+	nircm->valid_flags = 0;
+	nircm->rule_flags = 0;
+
+	/*
+	 * Initialize VLAN tag information
+	 */
+	nircm->vlan_primary_rule.ingress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_primary_rule.egress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.ingress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.egress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+
+	/*
+	 * Get the interface lists of the connection, we must have at least one interface in the list to continue
+	 */
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in from_interfaces list!\n", feci);
+		goto ported_accel_bad_rule;
+	}
+
+	to_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, to_ifaces, ECM_DB_OBJ_DIR_TO);
+	if (to_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in to_interfaces list!\n", npci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * First interface in each must be a known nss interface
+	 */
+	from_nss_iface = from_ifaces[from_ifaces_first];
+	to_nss_iface = to_ifaces[to_ifaces_first];
+	from_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(from_nss_iface);
+	to_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(to_nss_iface);
+	if ((from_nss_iface_id < 0) || (to_nss_iface_id < 0)) {
+		DEBUG_TRACE("%px: from_nss_iface_id: %d, to_nss_iface_id: %d\n", npci, from_nss_iface_id, to_nss_iface_id);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * Get NSS interface ID of the top interface in heirarchy
+	 */
+	from_nss_iface = from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1];
+	to_nss_iface = to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1];
+	nircm->nexthop_rule.flow_nexthop = ecm_db_iface_ae_interface_identifier_get(from_nss_iface);
+	nircm->nexthop_rule.return_nexthop = ecm_db_iface_ae_interface_identifier_get(to_nss_iface);
+
+	/*
+	 * New rule being created
+	 */
+	nircm->valid_flags |= NSS_IPV4_RULE_CREATE_CONN_VALID;
+
+	/*
+	 * Set Nexthop interface number valid flag
+	 */
+	nircm->valid_flags |= NSS_IPV4_RULE_CREATE_NEXTHOP_VALID;
+
+	/*
+	 * Set interface numbers involved in accelerating this connection.
+	 * These are the outer facing addresses from the heirarchy interface lists we got above.
+	 * These may be overridden later if we detect special interface types e.g. ipsec.
+	 */
+	nircm->conn_rule.flow_interface_num = from_nss_iface_id;
+	nircm->conn_rule.return_interface_num = to_nss_iface_id;
+
+	/*
+	 * Set the mtu values. These values will be overwritten if the flow is
+	 * a specific tunnel type.
+	 */
+	nircm->conn_rule.flow_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nircm->conn_rule.return_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	/*
+	 * We know that each outward facing interface is known to the NSS and so this connection could be accelerated.
+	 * However the lists may also specify other interesting details that must be included in the creation command,
+	 * for example, ethernet MAC, VLAN tagging or PPPoE session information.
+	 * We get this information by walking from the outer to the innermost interface for each list and examine the interface types.
+	 *
+	 * Start with the 'from' (src) side.
+	 * NOTE: The lists may contain a complex heirarchy of similar type of interface e.g. multiple vlans or tunnels within tunnels.
+	 * This NSS cannot handle that - there is no way to describe this in the rule - if we see multiple types that would conflict we have to abort.
+	 */
+	DEBUG_TRACE("%px: Examine from/src heirarchy list\n", npci);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = from_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_in_dev = NULL;
+#endif
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+		ip_addr_t saddr;
+		ip_addr_t daddr;
+#endif
+		ii = from_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", npci, list_index, ii, ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			ecm_db_iface_bridge_address_get(ii, from_nss_iface_address);
+			if (is_valid_ether_addr(from_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV4_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", npci, from_nss_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, from_nss_iface_address);
+			if (is_valid_ether_addr(from_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV4_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", npci, from_nss_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", npci);
+				break;
+			}
+
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, from_nss_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", npci, from_nss_iface_address);
+			break;
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", npci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * Set the PPPoE rule creation structure.
+			 */
+			nircm->pppoe_rule.flow_if_num = ecm_db_iface_ae_interface_identifier_get(ii);
+			if (nircm->pppoe_rule.flow_if_num < 0) {
+				DEBUG_TRACE("%px: PPPoE - acceleration engine interface (%d) is not valid\n",
+						npci, nircm->pppoe_rule.flow_if_num);
+				rule_invalid = true;
+				break;
+			}
+			nircm->pppoe_rule.flow_if_exist = 1;
+			nircm->valid_flags |= NSS_IPV4_RULE_CREATE_PPPOE_VALID;
+
+			DEBUG_TRACE("%px: PPPoE - exist: %d flow_if_num: %d\n", npci,
+					nircm->pppoe_rule.flow_if_exist,
+					nircm->pppoe_rule.flow_if_num);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", npci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", npci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_in_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_in_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_in_dev, pr->return_qos_tag);
+				dev_put(vlan_in_dev);
+				vlan_in_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.ingress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.ingress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= NSS_IPV4_RULE_CREATE_VLAN_VALID;
+
+			/*
+			 * If we have not yet got an ethernet mac then take this one (very unlikely as mac should have been propagated to the slave (outer) device
+			 */
+			memcpy(from_nss_iface_address, vlan_info.address, ETH_ALEN);
+			if (is_valid_ether_addr(from_nss_iface_address)) {
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", npci, from_nss_iface_address);
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+				memcpy(nircm->src_mac_rule.flow_src_mac, from_nss_iface_address, ETH_ALEN);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV4_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID;
+			}
+			DEBUG_TRACE("%px: vlan tag: %x\n", npci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", npci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_MACVLAN:
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+			ecm_db_iface_macvlan_address_get(ii, from_nss_iface_address);
+			if (is_valid_ether_addr(from_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV4_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: Macvlan - mac: %pM\n", npci, from_nss_iface_address);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: MACVLAN - unsupported\n", npci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", npci);
+				break;
+			}
+
+			nircm->conn_rule.flow_interface_num = ecm_nss_common_ipsec_get_ifnum(from_nss_iface_id);
+			nircm->nexthop_rule.flow_nexthop = ecm_nss_common_ipsec_get_ifnum(nircm->nexthop_rule.flow_nexthop);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", npci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_PPPOL2TPV2:
+#ifdef ECM_INTERFACE_L2TPV2_ENABLE
+			/*
+			 * l2tp packets from lan to wan gets routed twice.
+			 *	1. eth1-->br-lan to l2tp
+			 *	2. l2tp ---> eth0.
+			 * we need to push nss rule for both. Requirement
+			 * mandidates multiple session per tunnel and all tunnel
+			 * packets has same 5 tuple info. So need to create a
+			 * special static l2tp interface with nss to identify
+			 * packets from wan side. So l2tp--->eth0 rule to be
+			 * pushed with this static interface.
+			 */
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, saddr);
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, daddr);
+			if (ecm_interface_tunnel_mtu_update(saddr, daddr, ECM_DB_IFACE_TYPE_PPPOL2TPV2, &(nircm->conn_rule.flow_mtu))) {
+				nircm->conn_rule.return_mtu = nircm->conn_rule.flow_mtu;
+				nircm->conn_rule.flow_interface_num = NSS_L2TPV2_INTERFACE;
+			}
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: L2TPV2 - unsupported\n", npci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_OVPN:
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+			DEBUG_TRACE("%px: OVPN interface\n", npci);
+			nircm->conn_rule.flow_interface_num = nss_qvpn_ifnum_with_core_id(from_nss_iface_id);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: OVPN - unsupported\n", npci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VXLAN:
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+			DEBUG_TRACE("%px: From VXLAN interface\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can support only one VxLAN interface.
+				 */
+				DEBUG_WARN("%px: VxLAN - ignore additional\n", npci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * For VxLAN device, a 5-tuple connection rule is added with the same src and dest ports in both the directions.
+			 * Source interface is a VxLAN interface for the routed flow which is the case for VxLAN->IPsec or VxLAN->WAN rule.
+			 * Override the flow MTU to MAX, to avoid fragmentation for flows coming in from WAN.
+			 * Note: These rules are always expected to be pushed only in tunnel to WAN direction.
+			 */
+			if (ecm_db_connection_is_routed_get(feci->ci)) {
+				nircm->conn_rule.flow_mtu = ECM_DB_IFACE_MTU_MAX;
+				nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_NO_SRC_IDENT;
+			}
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VXLAN - unsupported\n", npci);
+#endif
+			break;
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", npci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+
+	if (rule_invalid) {
+		DEBUG_WARN("%px: from/src Rule invalid\n", npci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * Now examine the TO / DEST heirarchy list to construct the destination part of the rule
+	 */
+	DEBUG_TRACE("%px: Examine to/dest heirarchy list\n", npci);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = to_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_out_dev = NULL;
+#endif
+
+		ii = to_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", npci, list_index, ii, ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			ecm_db_iface_bridge_address_get(ii, to_nss_iface_address);
+			if (is_valid_ether_addr(to_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV4_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", npci, to_nss_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, to_nss_iface_address);
+			if (is_valid_ether_addr(to_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV4_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", npci, to_nss_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", npci);
+				break;
+			}
+
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, to_nss_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", npci, to_nss_iface_address);
+			break;
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", npci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * Set the PPPoE rule creation structure.
+			 */
+			nircm->pppoe_rule.return_if_num = ecm_db_iface_ae_interface_identifier_get(ii);
+			if (nircm->pppoe_rule.return_if_num < 0) {
+				DEBUG_TRACE("%px: PPPoE - acceleration engine interface (%d) is not valid\n",
+						npci, nircm->pppoe_rule.return_if_num);
+				rule_invalid = true;
+				break;
+			}
+			nircm->pppoe_rule.return_if_exist = 1;
+			nircm->valid_flags |= NSS_IPV4_RULE_CREATE_PPPOE_VALID;
+
+			DEBUG_TRACE("%px: PPPoE - exist: %d return_if_num: %d\n", npci,
+					nircm->pppoe_rule.return_if_exist,
+					nircm->pppoe_rule.return_if_num);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", npci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", npci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_out_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_out_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_out_dev, pr->flow_qos_tag);
+				dev_put(vlan_out_dev);
+				vlan_out_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.egress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.egress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= NSS_IPV4_RULE_CREATE_VLAN_VALID;
+
+			/*
+			 * If we have not yet got an ethernet mac then take this one (very unlikely as mac should have been propagated to the slave (outer) device
+			 */
+			memcpy(to_nss_iface_address, vlan_info.address, ETH_ALEN);
+			if (is_valid_ether_addr(to_nss_iface_address)) {
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", npci, to_nss_iface_address);
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+				memcpy(nircm->src_mac_rule.return_src_mac, to_nss_iface_address, ETH_ALEN);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV4_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: vlan tag: %x\n", npci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", npci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_MACVLAN:
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+			ecm_db_iface_macvlan_address_get(ii, to_nss_iface_address);
+			if (is_valid_ether_addr(to_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV4_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= NSS_IPV4_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: Macvlan - mac: %pM\n", npci, to_nss_iface_address);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: MACVLAN - unsupported\n", npci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", npci);
+				break;
+			}
+
+			nircm->conn_rule.return_interface_num = ecm_nss_common_ipsec_get_ifnum(to_nss_iface_id);
+			nircm->nexthop_rule.return_nexthop = ecm_nss_common_ipsec_get_ifnum(nircm->nexthop_rule.return_nexthop);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", npci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_OVPN:
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+			DEBUG_TRACE("%px: OVPN interface\n", npci);
+			nircm->conn_rule.return_interface_num = nss_qvpn_ifnum_with_core_id(to_nss_iface_id);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: OVPN - unsupported\n", npci);
+#endif
+			break;
+
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", npci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+
+	if (rule_invalid) {
+		DEBUG_WARN("%px: to/dest Rule invalid\n", npci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * Routed or bridged?
+	 */
+	if (ecm_db_connection_is_routed_get(feci->ci)) {
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_ROUTED;
+	} else {
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_BRIDGE_FLOW;
+		if (is_l2_encap) {
+			nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_L2_ENCAP;
+		}
+	}
+
+	if (ecm_interface_src_check) {
+		DEBUG_INFO("%px: Source interface check flag is enabled\n", npci);
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_SRC_INTERFACE_CHECK;
+	}
+
+	/*
+	 * Set up the flow and return qos tags
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+		nircm->qos_rule.flow_qos_tag = (uint32_t)pr->flow_qos_tag;
+		nircm->qos_rule.return_qos_tag = (uint32_t)pr->return_qos_tag;
+		nircm->valid_flags |= NSS_IPV4_RULE_CREATE_QOS_VALID;
+	}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+#ifdef ECM_CLASSIFIER_DSCP_IGS
+	/*
+	 * Set up ingress shaper qostag values.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG) {
+		nircm->igs_rule.igs_flow_qos_tag = (uint16_t)pr->igs_flow_qos_tag;
+		nircm->igs_rule.igs_return_qos_tag = (uint16_t)pr->igs_return_qos_tag;
+		nircm->valid_flags |= NSS_IPV4_RULE_CREATE_IGS_VALID;
+	}
+#endif
+	/*
+	 * DSCP information?
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+		nircm->dscp_rule.flow_dscp = pr->flow_dscp;
+		nircm->dscp_rule.return_dscp = pr->return_dscp;
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_DSCP_MARKING;
+		nircm->valid_flags |= NSS_IPV4_RULE_CREATE_DSCP_MARKING_VALID;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+	/*
+	 * Mark the rule as E-MESH Service Prioritization valid.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW) {
+		nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_EMESH_SP;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_PCC_ENABLE
+	/*
+	 * Set up the interfaces for mirroring.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_MIRROR_ENABLED) {
+		if (!ecm_nss_common_fill_mirror_info(pr, &nircm->mirror_rule.flow_ifnum,
+					 &nircm->mirror_rule.return_ifnum)) {
+			DEBUG_WARN("Invalid Mirror interface information\n");
+			ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+			ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+			goto ported_accel_bad_rule;
+		}
+
+		if (nircm->mirror_rule.flow_ifnum != -1) {
+			nircm->mirror_rule.valid |= NSS_IPV4_MIRROR_FLOW_VALID;
+		}
+
+		if (nircm->mirror_rule.return_ifnum != -1) {
+			nircm->mirror_rule.valid |= NSS_IPV4_MIRROR_RETURN_VALID;
+		}
+
+		nircm->valid_flags |= NSS_IPV4_RULE_CREATE_MIRROR_VALID;
+	}
+#endif
+
+	if (ecm_nss_ipv4_vlan_passthrough_enable && !ecm_db_connection_is_routed_get(feci->ci) &&
+	   (nircm->vlan_primary_rule.ingress_vlan_tag == ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) &&
+	   (nircm->vlan_primary_rule.egress_vlan_tag == ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED)) {
+		int vlan_present = 0;
+		vlan_present = skb_vlan_tag_present(skb);
+		if (vlan_present) {
+			uint32_t vlan_value;
+			vlan_value = (ETH_P_8021Q << 16) | skb_vlan_tag_get(skb);
+			nircm->vlan_primary_rule.ingress_vlan_tag = vlan_value;
+			nircm->vlan_primary_rule.egress_vlan_tag = vlan_value;
+			nircm->valid_flags |= NSS_IPV4_RULE_CREATE_VLAN_VALID;
+		}
+	}
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+		/*
+		 * Copy the both primary and secondary (if exist) VLAN tags.
+		 */
+		if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG) {
+			nircm->vlan_primary_rule.ingress_vlan_tag = pr->ingress_vlan_tag[0];
+			nircm->vlan_primary_rule.egress_vlan_tag = pr->egress_vlan_tag[0];
+			nircm->valid_flags |= NSS_IPV4_RULE_CREATE_VLAN_VALID;
+		}
+
+		if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG) {
+			nircm->vlan_secondary_rule.ingress_vlan_tag = pr->ingress_vlan_tag[1];
+			nircm->vlan_secondary_rule.egress_vlan_tag = pr->egress_vlan_tag[1];
+		}
+#endif
+
+	protocol = ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * Set protocol
+	 */
+	nircm->tuple.protocol = (int32_t)protocol;
+
+	/*
+	 * The flow_ip is where the connection established from
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, addr);
+
+	ECM_IP_ADDR_TO_HIN4_ADDR(nircm->tuple.flow_ip, addr);
+
+	/*
+	 * The return_ip is where the connection is established to, however, in the case of ingress
+	 * the return_ip would be the routers WAN IP - i.e. the NAT'ed version.
+	 * Getting the NAT'ed version here works for ingress or egress packets, for egress
+	 * the NAT'ed version would be the same as the normal address
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, addr);
+
+	ECM_IP_ADDR_TO_HIN4_ADDR(nircm->tuple.return_ip, addr);
+
+	/*
+	 * When the packet is forwarded to the next interface get the address the source IP of the
+	 * packet should be translated to.  For egress this is the NAT'ed from address.
+	 * This also works for ingress as the NAT'ed version of the WAN host would be the same as non-NAT'ed
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM_NAT, addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(nircm->conn_rule.flow_ip_xlate, addr);
+
+	/*
+	 * The destination address is what the destination IP is translated to as it is forwarded to the next interface.
+	 * For egress this would yield the normal wan host and for ingress this would correctly NAT back to the LAN host
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(nircm->conn_rule.return_ip_xlate, addr);
+
+	/*
+	 * Same approach as above for port information
+	 */
+	nircm->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nircm->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT);
+	nircm->conn_rule.flow_ident_xlate = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM_NAT);
+	nircm->conn_rule.return_ident_xlate = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	/*
+	 * Get mac addresses.
+	 * The src_mac is the mac address of the node that established the connection.
+	 * This will work whether the from_node is LAN (egress) or WAN (ingress).
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, (uint8_t *)nircm->conn_rule.flow_mac);
+
+	/*
+	 * The dest_mac is more complex.  For egress it is the node address of the 'to' side of the connection.
+	 * For ingress it is the node adress of the NAT'ed 'to' IP.
+	 * Essentially it is the MAC of node associated with create.dest_ip and this is "to nat" side.
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, (uint8_t *)nircm->conn_rule.return_mac);
+
+	/*
+	 * The dest_mac_xlate is the mac address to replace the pkt.dst_mac when a packet is sent to->from
+	 * For bridged connections this does not change.
+	 * For routed connections this is the mac of the 'to' node side of the connection.
+	 */
+	if (ecm_db_connection_is_routed_get(feci->ci)) {
+		ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, dest_mac_xlate);
+	} else {
+		/*
+		 * Bridge flows preserve the MAC addressing
+		 */
+		memcpy(dest_mac_xlate, (uint8_t *)nircm->conn_rule.return_mac, ETH_ALEN);
+	}
+
+	/*
+	 * Refer to the Example 2 and 3 in ecm_nss_ipv4_ip_process() function for egress
+	 * and ingress NAT'ed cases. In these cases, the destination node is the one which has the
+	 * ip_dest_addr. So, above we get the mac address of this host and use that mac address
+	 * for the destination node address in NAT'ed cases.
+	 */
+	ecm_dir = ecm_db_connection_direction_get(feci->ci);
+	if ((ecm_dir == ECM_DB_DIRECTION_INGRESS_NAT) || (ecm_dir == ECM_DB_DIRECTION_EGRESS_NAT)) {
+		memcpy(nircm->conn_rule.return_mac, dest_mac_xlate, ETH_ALEN);
+	}
+
+	if (protocol == IPPROTO_TCP) {
+		/*
+		 * Need window scaling and remarking information if available
+		 * Start by looking up the conntrack connection
+		 */
+		if (!ct) {
+			/*
+			 * No conntrack so no need to check window sequence space
+			 */
+			DEBUG_TRACE("%px: TCP Accel no ct from conn %px to get window data\n", npci, feci->ci);
+			nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_NO_SEQ_CHECK;
+		} else {
+			int flow_dir;
+			int return_dir;
+
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, addr);
+			ecm_front_end_flow_and_return_directions_get(ct, addr, 4, &flow_dir, &return_dir);
+
+			DEBUG_TRACE("%px: TCP Accel Get window data from ct %px for conn %px\n", npci, ct, feci->ci);
+			spin_lock_bh(&ct->lock);
+			nircm->tcp_rule.flow_window_scale = ct->proto.tcp.seen[flow_dir].td_scale;
+			nircm->tcp_rule.flow_max_window = ct->proto.tcp.seen[flow_dir].td_maxwin;
+			nircm->tcp_rule.flow_end = ct->proto.tcp.seen[flow_dir].td_end;
+			nircm->tcp_rule.flow_max_end = ct->proto.tcp.seen[flow_dir].td_maxend;
+			nircm->tcp_rule.return_window_scale = ct->proto.tcp.seen[return_dir].td_scale;
+			nircm->tcp_rule.return_max_window = ct->proto.tcp.seen[return_dir].td_maxwin;
+			nircm->tcp_rule.return_end = ct->proto.tcp.seen[return_dir].td_end;
+			nircm->tcp_rule.return_max_end = ct->proto.tcp.seen[return_dir].td_maxend;
+#ifdef ECM_OPENWRT_SUPPORT
+			if (nf_ct_tcp_be_liberal || nf_ct_tcp_no_window_check
+#else
+			if (nf_ct_tcp_be_liberal
+#endif
+					|| (ct->proto.tcp.seen[flow_dir].flags & IP_CT_TCP_FLAG_BE_LIBERAL)
+					|| (ct->proto.tcp.seen[return_dir].flags & IP_CT_TCP_FLAG_BE_LIBERAL)) {
+				nircm->rule_flags |= NSS_IPV4_RULE_CREATE_FLAG_NO_SEQ_CHECK;
+			}
+			spin_unlock_bh(&ct->lock);
+		}
+
+		nircm->valid_flags |= NSS_IPV4_RULE_CREATE_TCP_VALID;
+	}
+
+	/*
+	 * Sync our creation command from the assigned classifiers to get specific additional creation rules.
+	 * NOTE: These are called in ascending order of priority and so the last classifier (highest) shall
+	 * override any preceding classifiers.
+	 * This also gives the classifiers a chance to see that acceleration is being attempted.
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(feci->ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+		struct ecm_classifier_rule_create ecrc;
+		/*
+		 * NOTE: The current classifiers do not sync anything to the underlying accel engines.
+		 * In the future, if any of the classifiers wants to pass any parameter, these parameters
+		 * should be received via this object and copied to the accel engine's create object (nircm).
+		 */
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+		ecrc.skb = skb;
+#endif
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: sync from: %px, type: %d\n", npci, aci, aci->type_get(aci));
+		aci->sync_from_v4(aci, &ecrc);
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Release the interface lists
+	 */
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+	ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+
+	DEBUG_INFO("%px: Ported Accelerate connection %px\n"
+			"Protocol: %d\n"
+			"from_mtu: %u\n"
+			"to_mtu: %u\n"
+			"from_ip: %pI4h:%d\n"
+			"to_ip: %pI4h:%d\n"
+			"from_ip_xlate: %pI4h:%d\n"
+			"to_ip_xlate: %pI4h:%d\n"
+			"from_mac: %pM\n"
+			"to_mac: %pM\n"
+			"src_iface_num: %u\n"
+			"dest_iface_num: %u\n"
+			"src_nexthop_num: %u\n"
+			"dest_nexthop_num: %u\n"
+			"ingress_inner_vlan_tag: %x\n"
+			"egress_inner_vlan_tag: %x\n"
+			"ingress_outer_vlan_tag: %x\n"
+			"egress_outer_vlan_tag: %x\n"
+			"rule_flags: %x\n"
+			"valid_flags: %x\n"
+			"pppoe_return_if_exist: %u\n"
+			"pppoe_return_if_num: %u\n"
+			"pppoe_flow_if_exist: %u\n"
+			"pppoe_flow_if_num: %u\n"
+			"flow_qos_tag: %x (%u)\n"
+			"return_qos_tag: %x (%u)\n"
+			"igs_flow_qos_tag: %x (%u)\n"
+			"igs_return_qos_tag: %x (%u)\n"
+			"flow_window_scale: %u\n"
+			"flow_max_window: %u\n"
+			"flow_end: %u\n"
+			"flow_max_end: %u\n"
+			"return_window_scale: %u\n"
+			"return_max_window: %u\n"
+			"return_end: %u\n"
+			"return_max_end: %u\n"
+			"flow_dscp: %x\n"
+			"return_dscp: %x\n",
+			npci,
+			feci->ci,
+			nircm->tuple.protocol,
+			nircm->conn_rule.flow_mtu,
+			nircm->conn_rule.return_mtu,
+			&nircm->tuple.flow_ip, nircm->tuple.flow_ident,
+			&nircm->tuple.return_ip, nircm->tuple.return_ident,
+			&nircm->conn_rule.flow_ip_xlate, nircm->conn_rule.flow_ident_xlate,
+			&nircm->conn_rule.return_ip_xlate, nircm->conn_rule.return_ident_xlate,
+			nircm->conn_rule.flow_mac,
+			nircm->conn_rule.return_mac,
+			nircm->conn_rule.flow_interface_num,
+			nircm->conn_rule.return_interface_num,
+			nircm->nexthop_rule.flow_nexthop,
+			nircm->nexthop_rule.return_nexthop,
+			nircm->vlan_primary_rule.ingress_vlan_tag,
+			nircm->vlan_primary_rule.egress_vlan_tag,
+			nircm->vlan_secondary_rule.ingress_vlan_tag,
+			nircm->vlan_secondary_rule.egress_vlan_tag,
+			nircm->rule_flags,
+			nircm->valid_flags,
+			nircm->pppoe_rule.return_if_exist,
+			nircm->pppoe_rule.return_if_num,
+			nircm->pppoe_rule.flow_if_exist,
+			nircm->pppoe_rule.flow_if_num,
+			nircm->qos_rule.flow_qos_tag, nircm->qos_rule.flow_qos_tag,
+			nircm->qos_rule.return_qos_tag, nircm->qos_rule.return_qos_tag,
+			nircm->igs_rule.igs_flow_qos_tag, nircm->igs_rule.igs_flow_qos_tag,
+			nircm->igs_rule.igs_return_qos_tag, nircm->igs_rule.igs_return_qos_tag,
+			nircm->tcp_rule.flow_window_scale,
+			nircm->tcp_rule.flow_max_window,
+			nircm->tcp_rule.flow_end,
+			nircm->tcp_rule.flow_max_end,
+			nircm->tcp_rule.return_window_scale,
+			nircm->tcp_rule.return_max_window,
+			nircm->tcp_rule.return_end,
+			nircm->tcp_rule.return_max_end,
+			nircm->dscp_rule.flow_dscp,
+			nircm->dscp_rule.return_dscp);
+
+	if (protocol == IPPROTO_TCP) {
+
+		DEBUG_INFO("flow_window_scale: %u\n"
+			"flow_max_window: %u\n"
+			"flow_end: %u\n"
+			"flow_max_end: %u\n"
+			"return_window_scale: %u\n"
+			"return_max_window: %u\n"
+			"return_end: %u\n"
+			"return_max_end: %u\n",
+			nircm->tcp_rule.flow_window_scale,
+			nircm->tcp_rule.flow_max_window,
+			nircm->tcp_rule.flow_end,
+			nircm->tcp_rule.flow_max_end,
+			nircm->tcp_rule.return_window_scale,
+			nircm->tcp_rule.return_max_window,
+			nircm->tcp_rule.return_end,
+			nircm->tcp_rule.return_max_end);
+	}
+
+	/*
+	 * Now that the rule has been constructed we re-compare the generation occurrance counter.
+	 * If there has been a change then we abort because the rule may have been created using
+	 * unstable data - especially if another thread has begun regeneration of the connection state.
+	 * NOTE: This does not prevent a regen from being flagged immediately after this line of code either,
+	 * or while the acceleration rule is in flight to the nss.
+	 * This is only to check for consistency of rule state - not that the state is stale.
+	 * Remember that the connection is marked as "accel pending state" so if a regen is flagged immediately
+	 * after this check passes, the connection will be decelerated and refreshed very quickly.
+	 */
+	if (regen_occurrances != ecm_db_connection_regeneration_occurrances_get(feci->ci)) {
+		DEBUG_INFO("%px: connection:%px regen occurred - aborting accel rule.\n", feci, feci->ci);
+		ecm_nss_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		kfree(nim);
+		return;
+	}
+
+	/*
+	 * Ref the connection before issuing an NSS rule
+	 * This ensures that when the NSS responds to the command - which may even be immediately -
+	 * the callback function can trust the correct ref was taken for its purpose.
+	 * NOTE: remember that this will also implicitly hold the feci.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Call the rule create function
+	 */
+	nss_tx_status = nss_ipv4_tx(ecm_nss_ipv4_nss_ipv4_mgr, nim);
+	if (nss_tx_status == NSS_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;
+		spin_unlock_bh(&feci->lock);
+		kfree(nim);
+		return;
+	}
+
+	kfree(nim);
+
+	/*
+	 * Release that ref!
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * TX failed
+	 */
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Accel mode unexpected: %d\n", feci, feci->accel_mode);
+	feci->stats.driver_fail_total++;
+	feci->stats.driver_fail++;
+	if (feci->stats.driver_fail >= feci->stats.driver_fail_limit) {
+		DEBUG_WARN("%px: Accel failed - driver fail limit\n", npci);
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DRIVER;
+	} else {
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	_ecm_nss_ipv4_accel_pending_clear(feci, result_mode);
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	spin_unlock_bh(&feci->lock);
+	return;
+
+ported_accel_bad_rule:
+	;
+
+	kfree(nim);
+
+	/*
+	 * Jump to here when rule data is bad and an offload command cannot be constructed
+	 */
+	DEBUG_WARN("%px: Accel failed - bad rule\n", npci);
+	ecm_nss_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_FAIL_RULE);
+}
+
+/*
+ * ecm_nss_ported_ipv4_connection_destroy_callback()
+ *	Callback for handling destroy ack/nack calls.
+ */
+static void ecm_nss_ported_ipv4_connection_destroy_callback(void *app_data, struct nss_ipv4_msg *nim)
+{
+	struct nss_ipv4_rule_destroy_msg * __attribute__((unused))nirdm = &nim->msg.rule_destroy;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_nss_ported_ipv4_connection_instance *npci;
+
+	/*
+	 * Is this a response to a destroy message?
+	 */
+	if (nim->cm.type != NSS_IPV4_TX_DESTROY_RULE_MSG) {
+		DEBUG_ERROR("%px: ported destroy callback with improper type: %d\n", nim, nim->cm.type);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: destroy callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	npci = (struct ecm_nss_ported_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_nss_ipv4_decel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: decelerate response for connection: %px\n", npci, feci->ci);
+	DEBUG_TRACE("%px: flow_ip: %pI4h:%d\n", npci, &nirdm->tuple.flow_ip, nirdm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: %pI4h:%d\n", npci, &nirdm->tuple.return_ip, nirdm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", npci, nirdm->tuple.protocol);
+
+	/*
+	 * Drop decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_ipv4_pending_decel_count--;
+	DEBUG_ASSERT(ecm_nss_ipv4_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If decel is not still pending then it's possible that the NSS ended acceleration by some other reason e.g. flush
+	 * In which case we cannot rely on the response we get here.
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING) {
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connections.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_TRACE("%px: response: %d\n", npci, nim->cm.response);
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DECEL;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	/*
+	 * If connection became defunct then set mode so that no further accel/decel attempts occur.
+	 */
+	if (feci->is_defunct) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT_SHORT;
+	}
+
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Ported acceleration ends
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_ported_ipv4_accelerated_count[npci->ported_accelerated_count_index]--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_nss_ported_ipv4_accelerated_count[npci->ported_accelerated_count_index] >= 0, "Bad udp accel counter\n");
+	ecm_nss_ipv4_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_nss_ipv4_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	/*
+	 * Release the connections.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_nss_ported_ipv4_connection_decelerate_msg_send()
+ *	Prepares and sends a decelerate message to acceleration engine.
+ */
+static bool ecm_nss_ported_ipv4_connection_decelerate_msg_send(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_ported_ipv4_connection_instance *npci = (struct ecm_nss_ported_ipv4_connection_instance *)feci;
+	struct nss_ipv4_msg nim;
+	struct nss_ipv4_rule_destroy_msg *nirdm;
+	ip_addr_t addr;
+	nss_tx_status_t nss_tx_status;
+	bool ret;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	/*
+	 * Increment the decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_ipv4_pending_decel_count++;
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	/*
+	 * Prepare deceleration message
+	 */
+	nss_ipv4_msg_init(&nim, NSS_IPV4_RX_INTERFACE, NSS_IPV4_TX_DESTROY_RULE_MSG,
+			sizeof(struct nss_ipv4_rule_destroy_msg),
+			ecm_nss_ported_ipv4_connection_destroy_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nirdm = &nim.msg.rule_destroy;
+	nirdm->tuple.protocol = (int32_t)ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * Get addressing information
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(nirdm->tuple.flow_ip, addr);
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, addr);
+	ECM_IP_ADDR_TO_HIN4_ADDR(nirdm->tuple.return_ip, addr);
+	nirdm->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nirdm->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT);
+
+	DEBUG_INFO("%px: Ported Connection %px decelerate\n"
+			"protocol: %d\n"
+			"src_ip: %pI4:%d\n"
+			"dest_ip: %pI4:%d\n",
+			npci, feci->ci, nirdm->tuple.protocol,
+			&nirdm->tuple.flow_ip, nirdm->tuple.flow_ident,
+			&nirdm->tuple.return_ip, nirdm->tuple.return_ident);
+
+	/*
+	 * Take a ref to the feci->ci so that it will persist until we get a response from the NSS.
+	 * NOTE: This will implicitly hold the feci too.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Destroy the NSS connection cache entry.
+	 */
+	nss_tx_status = nss_ipv4_tx(ecm_nss_ipv4_nss_ipv4_mgr, &nim);
+	if (nss_tx_status == NSS_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;
+		spin_unlock_bh(&feci->lock);
+		return true;
+	}
+
+	/*
+	 * TX failed
+	 */
+	ret = ecm_front_end_destroy_failure_handle(feci);
+
+	/*
+	 * Release the ref take, NSS driver did not accept our command.
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * Could not send the request, decrement the decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_ipv4_pending_decel_count--;
+	DEBUG_ASSERT(ecm_nss_ipv4_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+	return ret;
+}
+
+/*
+ * ecm_nss_ported_ipv4_connection_decelerate()
+ *     Decelerate a connection
+ */
+static bool ecm_nss_ported_ipv4_connection_decelerate(struct ecm_front_end_connection_instance *feci)
+{
+	/*
+	 * Check if accel mode is OK for the deceleration.
+	 */
+	spin_lock_bh(&feci->lock);
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+	return ecm_nss_ported_ipv4_connection_decelerate_msg_send(feci);
+}
+
+/*
+ * ecm_nss_ported_ipv4_connection_defunct_callback()
+ *	Callback to be called when a ported connection has become defunct.
+ */
+bool ecm_nss_ported_ipv4_connection_defunct_callback(void *arg, int *accel_mode)
+{
+	bool ret;
+	struct ecm_front_end_connection_instance *feci = (struct ecm_front_end_connection_instance *)arg;
+	struct ecm_nss_ported_ipv4_connection_instance *npci = (struct ecm_nss_ported_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	spin_lock_bh(&feci->lock);
+	/*
+	 * Check if the connection can be defuncted.
+	 */
+	if (!ecm_front_end_common_connection_defunct_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * If none of the cases matched above, this means the connection is in the
+	 * accel mode, so we force a deceleration.
+	 * NOTE: If the mode is accel pending then the decel will be actioned when that is completed.
+	 */
+	ret = ecm_nss_ported_ipv4_connection_decelerate_msg_send(feci);
+
+	/*
+	 * Copy the accel_mode returned from the decelerate message function. This value
+	 * will be used in the caller to decide releasing the final reference of the connection.
+	 * But if this function reaches to here, the caller care about the ret. If ret is true,
+	 * the reference will be release regardless of the accel_mode. If ret is false, accel_mode
+	 * will be in the ACCEL state and this state will not be used in the caller's decision. It looks for
+	 * ACCEL_FAIL states.
+	 */
+	spin_lock_bh(&feci->lock);
+	*accel_mode = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+
+	return ret;
+}
+
+/*
+ * ecm_nss_ported_ipv4_connection_accel_state_get()
+ *	Get acceleration state
+ */
+static ecm_front_end_acceleration_mode_t ecm_nss_ported_ipv4_connection_accel_state_get(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_ported_ipv4_connection_instance *npci = (struct ecm_nss_ported_ipv4_connection_instance *)feci;
+	ecm_front_end_acceleration_mode_t state;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	spin_lock_bh(&feci->lock);
+	state = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+	return state;
+}
+
+/*
+ * ecm_nss_ported_ipv4_connection_action_seen()
+ *	Acceleration action / activity has been seen for this connection.
+ *
+ * NOTE: Call the action_seen() method when the NSS has demonstrated that it has offloaded some data for a connection.
+ */
+static void ecm_nss_ported_ipv4_connection_action_seen(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_ported_ipv4_connection_instance *npci = (struct ecm_nss_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	DEBUG_INFO("%px: Action seen\n", npci);
+	spin_lock_bh(&feci->lock);
+	feci->stats.no_action_seen = 0;
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_nss_ported_ipv4_connection_accel_ceased()
+ *	NSS has indicated that acceleration has stopped.
+ *
+ * NOTE: This is called in response to an NSS self-initiated termination of acceleration.
+ * This must NOT be called because the ECM terminated the acceleration.
+ */
+static void ecm_nss_ported_ipv4_connection_accel_ceased(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_ported_ipv4_connection_instance *npci = (struct ecm_nss_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	DEBUG_INFO("%px: accel ceased\n", npci);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If we are in accel-pending state then the NSS has issued a flush out-of-order
+	 * with the ACK/NACK we are actually waiting for.
+	 * To work around this we record a "flush has already happened" and will action it when we finally get that ACK/NACK.
+	 * GGG TODO This should eventually be removed when the NSS honours messaging sequence.
+	 */
+	if (feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING) {
+		feci->stats.flush_happened = true;
+		feci->stats.flush_happened_total++;
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If connection is no longer accelerated by the time we get here just ignore the command
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_ACCEL) {
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If the no_action_seen counter was not reset then acceleration ended without any offload action
+	 */
+	if (feci->stats.no_action_seen) {
+		feci->stats.no_action_seen_total++;
+	}
+
+	/*
+	 * If the no_action_seen indicates successive cessations of acceleration without any offload action occuring
+	 * then we fail out this connection
+	 */
+	if (feci->stats.no_action_seen >= feci->stats.no_action_seen_limit) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_NO_ACTION;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Ported acceleration ends
+	 */
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	ecm_nss_ported_ipv4_accelerated_count[npci->ported_accelerated_count_index]--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_nss_ported_ipv4_accelerated_count[npci->ported_accelerated_count_index] >= 0, "Bad ported accel counter\n");
+	ecm_nss_ipv4_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_nss_ipv4_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+}
+
+/*
+ * ecm_nss_ported_ipv4_connection_ref()
+ *	Ref a connection front end instance
+ */
+static void ecm_nss_ported_ipv4_connection_ref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_ported_ipv4_connection_instance *npci = (struct ecm_nss_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	spin_lock_bh(&feci->lock);
+	feci->refs++;
+	DEBUG_TRACE("%px: npci ref %d\n", feci, feci->refs);
+	DEBUG_ASSERT(feci->refs > 0, "%px: ref wrap\n", feci);
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_nss_ported_ipv4_connection_deref()
+ *	Deref a connection front end instance
+ */
+static int ecm_nss_ported_ipv4_connection_deref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_ported_ipv4_connection_instance *npci = (struct ecm_nss_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	spin_lock_bh(&feci->lock);
+	feci->refs--;
+	DEBUG_ASSERT(feci->refs >= 0, "%px: ref wrap\n", feci);
+
+	if (feci->refs > 0) {
+		int refs = feci->refs;
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: npci deref %d\n", npci, refs);
+		return refs;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * We can now destroy the instance
+	 */
+	DEBUG_TRACE("%px: npci final\n", npci);
+	DEBUG_CLEAR_MAGIC(npci);
+	kfree(npci);
+	return 0;
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_nss_ported_ipv4_connection_state_get()
+ *	Return state of this ported front end instance
+ */
+static int ecm_nss_ported_ipv4_connection_state_get(struct ecm_front_end_connection_instance *feci, struct ecm_state_file_instance *sfi)
+{
+	struct ecm_nss_ported_ipv4_connection_instance *npci = (struct ecm_nss_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	return ecm_front_end_common_connection_state_get(feci, sfi, "nss_v4.ported");
+}
+#endif
+
+/*
+ * ecm_nss_ported_ipv4_connection_instance_alloc()
+ *	Create a front end instance specific for ported connection
+ */
+struct ecm_nss_ported_ipv4_connection_instance *ecm_nss_ported_ipv4_connection_instance_alloc(
+								bool can_accel,
+								int protocol,
+								struct ecm_db_connection_instance **nci)
+{
+	struct ecm_nss_ported_ipv4_connection_instance *npci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_db_connection_instance *ci;
+
+	if (ecm_nss_ipv4_is_conn_limit_reached()) {
+		DEBUG_TRACE("Reached connection limit\n");
+		return NULL;
+	}
+
+	/*
+	 * Now allocate the new connection
+	 */
+	*nci = ecm_db_connection_alloc();
+	if (!*nci) {
+		DEBUG_WARN("Failed to allocate connection\n");
+		return NULL;
+	}
+
+	ci = *nci;
+
+	npci = (struct ecm_nss_ported_ipv4_connection_instance *)kzalloc(sizeof(struct ecm_nss_ported_ipv4_connection_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!npci) {
+		ecm_db_connection_deref(ci);
+		DEBUG_WARN("Ported Front end alloc failed\n");
+		return NULL;
+	}
+
+	/*
+	 * Refs is 1 for the creator of the connection
+	 */
+	feci = (struct ecm_front_end_connection_instance *)npci;
+	feci->refs = 1;
+	DEBUG_SET_MAGIC(npci, ECM_NSS_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC);
+	spin_lock_init(&feci->lock);
+
+	feci->can_accel = can_accel;
+	feci->accel_mode = (can_accel)? ECM_FRONT_END_ACCELERATION_MODE_DECEL : ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED;
+	feci->accel_engine = ECM_FRONT_END_ENGINE_NSS;
+	spin_lock_bh(&ecm_nss_ipv4_lock);
+	feci->stats.no_action_seen_limit = ecm_nss_ipv4_no_action_limit_default;
+	feci->stats.driver_fail_limit = ecm_nss_ipv4_driver_fail_limit_default;
+	feci->stats.ae_nack_limit = ecm_nss_ipv4_nack_limit_default;
+	spin_unlock_bh(&ecm_nss_ipv4_lock);
+
+	/*
+	 * Copy reference to connection - no need to ref ci as ci maintains a ref to this instance instead (this instance persists for as long as ci does)
+	 */
+	feci->ci = ci;
+
+	feci->ip_version = 4;
+
+	feci->protocol = protocol;
+
+	/*
+	 * Populate the methods and callbacks
+	 */
+	feci->ref = ecm_nss_ported_ipv4_connection_ref;
+	feci->deref = ecm_nss_ported_ipv4_connection_deref;
+	feci->accelerate = ecm_nss_ported_ipv4_connection_accelerate;
+	feci->decelerate = ecm_nss_ported_ipv4_connection_decelerate;
+	feci->accel_state_get = ecm_nss_ported_ipv4_connection_accel_state_get;
+	feci->action_seen = ecm_nss_ported_ipv4_connection_action_seen;
+	feci->accel_ceased = ecm_nss_ported_ipv4_connection_accel_ceased;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	feci->state_get = ecm_nss_ported_ipv4_connection_state_get;
+#endif
+	feci->ae_interface_number_by_dev_get = ecm_nss_common_get_interface_number_by_dev;
+	feci->ae_interface_number_by_dev_type_get = ecm_nss_common_get_interface_number_by_dev_type;
+	feci->ae_interface_type_get = ecm_nss_common_get_interface_type;
+	feci->regenerate = ecm_nss_common_connection_regenerate;
+
+	feci->get_stats_bitmap = ecm_nss_common_dummy_get_stats_bitmap;
+	feci->set_stats_bitmap = ecm_nss_common_dummy_set_stats_bitmap;
+
+	if (protocol == IPPROTO_TCP) {
+		npci->ported_accelerated_count_index = ECM_NSS_PORTED_IPV4_PROTO_TCP;
+	} else if (protocol == IPPROTO_UDP) {
+		npci->ported_accelerated_count_index = ECM_NSS_PORTED_IPV4_PROTO_UDP;
+	} else {
+		DEBUG_WARN("%px: Wrong protocol: %d\n", npci, protocol);
+		DEBUG_CLEAR_MAGIC(npci);
+		kfree(npci);
+		ecm_db_connection_deref(ci);
+		return NULL;
+	}
+
+	return npci;
+}
+
+/*
+ * ecm_nss_ported_ipv4_debugfs_init()
+ */
+bool ecm_nss_ported_ipv4_debugfs_init(struct dentry *dentry)
+{
+	struct dentry *udp_dentry;
+
+	udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry,
+						&ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_UDP]);
+	if (!udp_dentry) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 udp_accelerated_count file in debugfs\n");
+		return false;
+	}
+
+	if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry,
+					&ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP])) {
+		DEBUG_ERROR("Failed to create ecm nss ipv4 tcp_accelerated_count file in debugfs\n");
+		debugfs_remove(udp_dentry);
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_ported_ipv4.h b/qca-nss-ecm/frontends/nss/ecm_nss_ported_ipv4.h
new file mode 100644
index 0000000..656bd65
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_ported_ipv4.h
@@ -0,0 +1,23 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern bool ecm_nss_ported_ipv4_debugfs_init(struct dentry *dentry);
+
+extern struct ecm_nss_ported_ipv4_connection_instance *ecm_nss_ported_ipv4_connection_instance_alloc(
+								bool can_accel,
+								int protocol,
+								struct ecm_db_connection_instance **nci);
+extern bool ecm_nss_ported_ipv4_connection_defunct_callback(void *arg, int *accel_mode);
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_ported_ipv6.c b/qca-nss-ecm/frontends/nss/ecm_nss_ported_ipv6.c
new file mode 100644
index 0000000..1be8a58
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_ported_ipv6.c
@@ -0,0 +1,1945 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/debugfs.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/ip6_route.h>
+#include <net/ip6_fib.h>
+#include <net/addrconf.h>
+#include <net/ipv6.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in6.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv6.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv6/nf_conntrack_ipv6.h>
+#include <net/netfilter/ipv6/nf_defrag_ipv6.h>
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+#include <net/vxlan.h>
+#endif
+#include <linux/netfilter/nf_conntrack_tftp.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_NSS_PORTED_IPV6_DEBUG_LEVEL
+
+#include <nss_api_if.h>
+
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+#include "nss_ipsec_cmn.h"
+#endif
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#include "ecm_nss_ported_ipv6.h"
+#include "ecm_nss_ipv6.h"
+#include "ecm_nss_common.h"
+#include "ecm_front_end_common.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_NSS_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC 0xEB12
+
+/*
+ * Protocol type that ported file supports.
+ */
+enum ecm_nss_ported_ipv6_proto_types {
+	ECM_NSS_PORTED_IPV6_PROTO_TCP = 0,
+	ECM_NSS_PORTED_IPV6_PROTO_UDP,
+	ECM_NSS_PORTED_IPV6_PROTO_MAX
+
+};
+
+/*
+ * struct ecm_nss_ipv6_ported_connection_instance
+ *	A connection specific front end instance for PORTED connections
+ */
+struct ecm_nss_ported_ipv6_connection_instance {
+	struct ecm_front_end_connection_instance base;		/* Base class */
+	uint8_t ported_accelerated_count_index;			/* Index value of accelerated count array (UDP or TCP) */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+static int ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_MAX] = {0};
+						/* Array of Number of TCP and UDP connections currently offloaded */
+
+/*
+ * Expose what should be a static flag in the TCP connection tracker.
+ */
+#ifdef ECM_OPENWRT_SUPPORT
+extern int nf_ct_tcp_no_window_check;
+#endif
+extern int nf_ct_tcp_be_liberal;
+
+/*
+ * ecm_nss_ported_ipv6_connection_callback()
+ *	Callback for handling create ack/nack calls.
+ */
+static void ecm_nss_ported_ipv6_connection_callback(void *app_data, struct nss_ipv6_msg *nim)
+{
+	struct nss_ipv6_rule_create_msg *nircm = &nim->msg.rule_create;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_nss_ported_ipv6_connection_instance *npci;
+	ip_addr_t flow_ip;
+	ip_addr_t return_ip;
+	ecm_front_end_acceleration_mode_t result_mode;
+	bool is_defunct = false;
+
+	/*
+	 * Is this a response to a create message?
+	 */
+	if (nim->cm.type != NSS_IPV6_TX_CREATE_RULE_MSG) {
+		DEBUG_ERROR("%px: ported create callback with improper type: %d, serial: %u\n", nim, nim->cm.type, serial);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: create callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	npci = (struct ecm_nss_ported_ipv6_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(flow_ip, nircm->tuple.flow_ip);
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(return_ip, nircm->tuple.return_ip);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_nss_ipv6_accel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: accelerate response for connection: %px, serial: %u\n", npci, feci->ci, serial);
+	DEBUG_TRACE("%px: rule_flags: %x, valid_flags: %x\n", npci, nircm->rule_flags, nircm->valid_flags);
+	DEBUG_TRACE("%px: flow_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", npci, ECM_IP_ADDR_TO_OCTAL(flow_ip), nircm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", npci, ECM_IP_ADDR_TO_OCTAL(return_ip), nircm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", npci, nircm->tuple.protocol);
+
+	/*
+	 * Handle the creation result code.
+	 */
+	DEBUG_TRACE("%px: response: %d\n", npci, nim->cm.response);
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		/*
+		 * Creation command failed (specific reason ignored).
+		 */
+		DEBUG_TRACE("%px: accel nack: %d\n", npci, nim->cm.error);
+		spin_lock_bh(&feci->lock);
+		DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+		feci->stats.ae_nack++;
+		feci->stats.ae_nack_total++;
+		if (feci->stats.ae_nack >= feci->stats.ae_nack_limit) {
+			/*
+			 * Too many NSS rejections
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_ACCEL_ENGINE;
+		} else {
+			/*
+			 * Revert to decelerated
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+		}
+
+		/*
+		 * If connection is now defunct then set mode to ensure no further accel attempts occur
+		 */
+		if (feci->is_defunct) {
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT;
+		}
+
+		spin_lock_bh(&ecm_nss_ipv6_lock);
+		_ecm_nss_ipv6_accel_pending_clear(feci, result_mode);
+		spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+
+	/*
+	 * If a flush occured before we got the ACK then our acceleration was effectively cancelled on us
+	 * GGG TODO This is a workaround for a NSS message OOO quirk, this should eventually be removed.
+	 */
+	if (feci->stats.flush_happened) {
+		feci->stats.flush_happened = false;
+
+		/*
+		 * Increment the no-action counter.  Our connection was decelerated on us with no action occurring.
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_lock_bh(&ecm_nss_ipv6_lock);
+		_ecm_nss_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	/*
+	 * Create succeeded
+	 */
+
+	/*
+	 * Clear any nack count
+	 */
+	feci->stats.ae_nack = 0;
+
+	/*
+	 * Clear the "accelerate pending" state and move to "accelerated" state bumping
+	 * the accelerated counters to match our new state.
+	 *
+	 * Decelerate may have been attempted while we were "pending accel" and
+	 * this function will return true if that was the case.
+	 * If decelerate was pending then we need to begin deceleration :-(
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+
+	ecm_nss_ported_ipv6_accelerated_count[npci->ported_accelerated_count_index]++;	/* Protocol specific counter */
+	ecm_nss_ipv6_accelerated_count++;		/* General running counter */
+
+	if (!_ecm_nss_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_ACCEL)) {
+		/*
+		 * Increment the no-action counter, this is reset if offload action is seen
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_unlock_bh(&ecm_nss_ipv6_lock);
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_INFO("%px: Decelerate was pending\n", ci);
+
+	/*
+	 * Check if the pending decelerate was done with the defunct process.
+	 * If it was, set the is_defunct flag of the feci to false for re-try.
+	 */
+	if (feci->is_defunct) {
+		is_defunct = feci->is_defunct;
+		feci->is_defunct = false;
+	}
+
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * If the pending decelerate was done through defunct process, we should
+	 * re-try it here with the same defunct function, because the purpose of that
+	 * process is to remove the connection from the database as well after decelerating it.
+	 */
+	if (is_defunct) {
+		ecm_db_connection_make_defunct(ci);
+	} else {
+		feci->decelerate(feci);
+	}
+
+	/*
+	 * Release the connection.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_nss_ported_ipv6_connection_accelerate()
+ *	Accelerate a connection
+ */
+static void ecm_nss_ported_ipv6_connection_accelerate(struct ecm_front_end_connection_instance *feci,
+                                                                        struct ecm_classifier_process_response *pr, bool is_l2_encap,
+                                                                        struct nf_conn *ct, struct sk_buff *skb)
+{
+	struct ecm_nss_ported_ipv6_connection_instance *npci = (struct ecm_nss_ported_ipv6_connection_instance *)feci;
+	uint16_t regen_occurrances;
+	int protocol;
+	int32_t from_ifaces_first;
+	int32_t to_ifaces_first;
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *from_nss_iface;
+	struct ecm_db_iface_instance *to_nss_iface;
+	int32_t from_nss_iface_id;
+	int32_t to_nss_iface_id;
+	uint8_t from_nss_iface_address[ETH_ALEN];
+	uint8_t to_nss_iface_address[ETH_ALEN];
+	struct nss_ipv6_msg *nim;
+	struct nss_ipv6_rule_create_msg *nircm;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	nss_tx_status_t nss_tx_status;
+	int32_t list_index;
+	int32_t interface_type_counts[ECM_DB_IFACE_TYPE_COUNT];
+	bool rule_invalid;
+	ip_addr_t src_ip;
+	ip_addr_t dest_ip;
+	ecm_front_end_acceleration_mode_t result_mode;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	/*
+	 * Get the re-generation occurrance counter of the connection.
+	 * We compare it again at the end - to ensure that the rule construction has seen no generation
+	 * changes during rule creation.
+	 */
+	regen_occurrances = ecm_db_connection_regeneration_occurrances_get(feci->ci);
+
+	/*
+	 * Test if acceleration is permitted
+	 */
+	if (!ecm_nss_ipv6_accel_pending_set(feci)) {
+		DEBUG_TRACE("%px: Acceleration not permitted: %px\n", feci, feci->ci);
+		return;
+	}
+
+	nim = (struct nss_ipv6_msg *)kzalloc(sizeof(struct nss_ipv6_msg), GFP_ATOMIC | __GFP_NOWARN);
+	if (!nim) {
+		DEBUG_WARN("%px: no memory for nss ipv6 message structure instance: %px\n", feci, feci->ci);
+		ecm_nss_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		return;
+	}
+
+	/*
+	 * Okay construct an accel command.
+	 * Initialise creation structure.
+	 * NOTE: We leverage the app_data void pointer to be our 32 bit connection serial number.
+	 * When we get it back we re-cast it to a uint32 and do a faster connection lookup.
+	 */
+	nss_ipv6_msg_init(nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_CREATE_RULE_MSG,
+			sizeof(struct nss_ipv6_rule_create_msg),
+			ecm_nss_ported_ipv6_connection_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nircm = &nim->msg.rule_create;
+	nircm->valid_flags = 0;
+	nircm->rule_flags = 0;
+
+	/*
+	 * Initialize VLAN tag information
+	 */
+	nircm->vlan_primary_rule.ingress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_primary_rule.egress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.ingress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.egress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+
+	/*
+	 * Get the interface lists of the connection, we must have at least one interface in the list to continue
+	 */
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in from_interfaces list!\n", npci);
+		goto ported_accel_bad_rule;
+	}
+
+	to_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, to_ifaces, ECM_DB_OBJ_DIR_TO);
+	if (to_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in to_interfaces list!\n", npci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * First interface in each must be a known nss interface
+	 */
+	from_nss_iface = from_ifaces[from_ifaces_first];
+	to_nss_iface = to_ifaces[to_ifaces_first];
+	from_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(from_nss_iface);
+	to_nss_iface_id = ecm_db_iface_ae_interface_identifier_get(to_nss_iface);
+	if ((from_nss_iface_id < 0) || (to_nss_iface_id < 0)) {
+		DEBUG_TRACE("%px: from_nss_iface_id: %d, to_nss_iface_id: %d\n", npci, from_nss_iface_id, to_nss_iface_id);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * Get NSS interface ID of the top interface in heirarchy
+	 */
+	from_nss_iface = from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1];
+	to_nss_iface = to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1];
+	nircm->nexthop_rule.flow_nexthop = ecm_db_iface_ae_interface_identifier_get(from_nss_iface);
+	nircm->nexthop_rule.return_nexthop = ecm_db_iface_ae_interface_identifier_get(to_nss_iface);
+
+	/*
+	 * New rule being created
+	 */
+	nircm->valid_flags |= NSS_IPV6_RULE_CREATE_CONN_VALID;
+
+	/*
+	 * Set Nexthop interface number valid flag
+	 */
+	nircm->valid_flags |= NSS_IPV6_RULE_CREATE_NEXTHOP_VALID;
+
+	/*
+	 * Set interface numbers involved in accelerating this connection.
+	 * These are the outer facing addresses from the heirarchy interface lists we got above.
+	 * These may be overridden later if we detect special interface types e.g. ipsec.
+	 */
+	nircm->conn_rule.flow_interface_num = from_nss_iface_id;
+	nircm->conn_rule.return_interface_num = to_nss_iface_id;
+
+	/*
+	 * We know that each outward facing interface is known to the NSS and so this connection could be accelerated.
+	 * However the lists may also specify other interesting details that must be included in the creation command,
+	 * for example, ethernet MAC, VLAN tagging or PPPoE session information.
+	 * We get this information by walking from the outer to the innermost interface for each list and examine the interface types.
+	 *
+	 * Start with the 'from' (src) side.
+	 * NOTE: The lists may contain a complex heirarchy of similar type of interface e.g. multiple vlans or tunnels within tunnels.
+	 * This NSS cannot handle that - there is no way to describe this in the rule - if we see multiple types that would conflict we have to abort.
+	 */
+	DEBUG_TRACE("%px: Examine from/src heirarchy list\n", npci);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = from_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_in_dev = NULL;
+#endif
+
+		ii = from_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", npci, list_index, ii, ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			ecm_db_iface_bridge_address_get(ii, from_nss_iface_address);
+			if (is_valid_ether_addr(from_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV6_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", npci, from_nss_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, from_nss_iface_address);
+			if (is_valid_ether_addr(from_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV6_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", npci, from_nss_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", npci);
+				break;
+			}
+
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, from_nss_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", npci, from_nss_iface_address);
+			break;
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", npci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * Set the PPPoE rule creation structure.
+			 */
+			nircm->pppoe_rule.flow_if_num = ecm_db_iface_ae_interface_identifier_get(ii);
+			if (nircm->pppoe_rule.flow_if_num < 0) {
+				DEBUG_TRACE("%px: PPPoE - acceleration engine flow interface (%d) is not valid\n",
+						npci, nircm->pppoe_rule.flow_if_num);
+				rule_invalid = true;
+				break;
+			}
+			nircm->pppoe_rule.flow_if_exist = 1;
+			nircm->valid_flags |= NSS_IPV6_RULE_CREATE_PPPOE_VALID;
+
+			DEBUG_TRACE("%px: PPPoE - exist: %d flow_if_num: %d\n", npci,
+					nircm->pppoe_rule.flow_if_exist,
+					nircm->pppoe_rule.flow_if_num);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", npci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", npci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_in_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_in_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_in_dev, pr->return_qos_tag);
+				dev_put(vlan_in_dev);
+				vlan_in_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.ingress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.ingress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= NSS_IPV6_RULE_CREATE_VLAN_VALID;
+
+			/*
+			 * If we have not yet got an ethernet mac then take this one (very unlikely as mac should have been propagated to the slave (outer) device
+			 */
+			memcpy(from_nss_iface_address, vlan_info.address, ETH_ALEN);
+			if (is_valid_ether_addr(from_nss_iface_address)) {
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", npci, from_nss_iface_address);
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+				memcpy(nircm->src_mac_rule.flow_src_mac, from_nss_iface_address, ETH_ALEN);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV6_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: vlan tag: %x\n", npci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", npci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_MACVLAN:
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+			ecm_db_iface_macvlan_address_get(ii, from_nss_iface_address);
+			if (is_valid_ether_addr(from_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV6_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: Macvlan - mac: %pM\n", npci, from_nss_iface_address);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: MACVLAN - unsupported\n", npci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", npci);
+				break;
+			}
+
+			nircm->conn_rule.flow_interface_num = ecm_nss_common_ipsec_get_ifnum(from_nss_iface_id);
+			nircm->nexthop_rule.flow_nexthop = ecm_nss_common_ipsec_get_ifnum(nircm->nexthop_rule.flow_nexthop);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", npci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_OVPN:
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+			DEBUG_TRACE("%px: OVPN interface\n", npci);
+			nircm->conn_rule.flow_interface_num = nss_qvpn_ifnum_with_core_id(from_nss_iface_id);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: OVPN - unsupported\n", npci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VXLAN:
+#ifdef ECM_INTERFACE_VXLAN_ENABLE
+			DEBUG_TRACE("%px: From VXLAN interface\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can support only one VxLAN interface.
+				 */
+				DEBUG_WARN("%px: VxLAN - ignore additional\n", npci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * For VxLAN device, a 5-tuple connection rule is added with the same src and dest ports in both the directions.
+			 * Source interface is a VxLAN interface for the routed flow which is the case for VxLAN->IPsec or VxLAN->WAN rule.
+			 * Override the flow MTU to MAX, to avoid fragmentation for flows coming in from WAN.
+			 * Note: These rules are always expected to be pushed only in tunnel to WAN direction.
+			 */
+			if (ecm_db_connection_is_routed_get(feci->ci)) {
+				nircm->conn_rule.flow_mtu = ECM_DB_IFACE_MTU_MAX;
+				nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_NO_SRC_IDENT;
+			}
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VXLAN - unsupported\n", npci);
+#endif
+			break;
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", npci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+
+	if (rule_invalid) {
+		DEBUG_WARN("%px: from/src Rule invalid\n", npci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * Now examine the TO / DEST heirarchy list to construct the destination part of the rule
+	 */
+	DEBUG_TRACE("%px: Examine to/dest heirarchy list\n", npci);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = to_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_out_dev = NULL;
+#endif
+
+		ii = to_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", npci, list_index, ii, ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			ecm_db_iface_bridge_address_get(ii, to_nss_iface_address);
+			if (is_valid_ether_addr(to_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV6_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", npci, to_nss_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, to_nss_iface_address);
+			if (is_valid_ether_addr(to_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV6_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", npci, to_nss_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", npci);
+				break;
+			}
+
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, to_nss_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", npci, to_nss_iface_address);
+			break;
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", npci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * Set the PPPoE rule creation structure.
+			 */
+			nircm->pppoe_rule.return_if_num = ecm_db_iface_ae_interface_identifier_get(ii);
+			if (nircm->pppoe_rule.return_if_num < 0) {
+				DEBUG_TRACE("%px: PPPoE - acceleration engine return interface (%d) is not valid\n",
+						npci, nircm->pppoe_rule.return_if_num);
+				rule_invalid = true;
+				break;
+			}
+			nircm->pppoe_rule.return_if_exist = 1;
+			nircm->valid_flags |= NSS_IPV6_RULE_CREATE_PPPOE_VALID;
+
+			DEBUG_TRACE("%px: PPPoE - exist: %d return_if_num: %d\n", npci,
+					nircm->pppoe_rule.return_if_exist,
+					nircm->pppoe_rule.return_if_num);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", npci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", npci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_out_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_out_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_out_dev, pr->flow_qos_tag);
+				dev_put(vlan_out_dev);
+				vlan_out_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.egress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.egress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= NSS_IPV6_RULE_CREATE_VLAN_VALID;
+
+			/*
+			 * If we have not yet got an ethernet mac then take this one (very unlikely as mac should have been propagated to the slave (outer) device
+			 */
+			memcpy(to_nss_iface_address, vlan_info.address, ETH_ALEN);
+			if (is_valid_ether_addr(to_nss_iface_address)) {
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", npci, to_nss_iface_address);
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+				memcpy(nircm->src_mac_rule.return_src_mac, to_nss_iface_address, ETH_ALEN);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV6_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: vlan tag: %x\n", npci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", npci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_MACVLAN:
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+			ecm_db_iface_macvlan_address_get(ii, to_nss_iface_address);
+			if (is_valid_ether_addr(to_nss_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_nss_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= NSS_IPV6_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= NSS_IPV6_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: Macvlan - mac: %pM\n", npci, to_nss_iface_address);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: MACVLAN - unsupported\n", npci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", npci);
+				break;
+			}
+
+			nircm->conn_rule.return_interface_num = ecm_nss_common_ipsec_get_ifnum(to_nss_iface_id);
+			nircm->nexthop_rule.return_nexthop = ecm_nss_common_ipsec_get_ifnum(nircm->nexthop_rule.return_nexthop);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", npci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_OVPN:
+#ifdef ECM_INTERFACE_OVPN_ENABLE
+			DEBUG_TRACE("%px: OVPN interface\n", npci);
+			nircm->conn_rule.return_interface_num = nss_qvpn_ifnum_with_core_id(to_nss_iface_id);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: OVPN - unsupported\n", npci);
+#endif
+			break;
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", npci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+
+	if (rule_invalid) {
+		DEBUG_WARN("%px: to/dest Rule invalid\n", npci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * Routed or bridged?
+	 */
+	if (ecm_db_connection_is_routed_get(feci->ci)) {
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_ROUTED;
+	} else {
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_BRIDGE_FLOW;
+		if (is_l2_encap) {
+			nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_L2_ENCAP;
+		}
+	}
+
+	if (ecm_interface_src_check) {
+		DEBUG_INFO("%px: Source interface check flag is enabled\n", npci);
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_SRC_INTERFACE_CHECK;
+	}
+
+	/*
+	 * Set up the flow and return qos tags
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+		nircm->qos_rule.flow_qos_tag = (uint32_t)pr->flow_qos_tag;
+		nircm->qos_rule.return_qos_tag = (uint32_t)pr->return_qos_tag;
+		nircm->valid_flags |= NSS_IPV6_RULE_CREATE_QOS_VALID;
+	}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+#ifdef ECM_CLASSIFIER_DSCP_IGS
+	/*
+	 * Set up ingress shaper qostag values.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_IGS_QOS_TAG) {
+		nircm->igs_rule.igs_flow_qos_tag = (uint16_t)pr->igs_flow_qos_tag;
+		nircm->igs_rule.igs_return_qos_tag = (uint16_t)pr->igs_return_qos_tag;
+		nircm->valid_flags |= NSS_IPV6_RULE_CREATE_IGS_VALID;
+	}
+#endif
+	/*
+	 * DSCP information?
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+		nircm->dscp_rule.flow_dscp = pr->flow_dscp;
+		nircm->dscp_rule.return_dscp = pr->return_dscp;
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_DSCP_MARKING;
+		nircm->valid_flags |= NSS_IPV6_RULE_CREATE_DSCP_MARKING_VALID;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+	/*
+	 * Mark the rule as E-MESH Service Prioritization valid.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_EMESH_SP_FLOW) {
+		nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_EMESH_SP;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_PCC_ENABLE
+	/*
+	 * Set up the interfaces for mirroring.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_MIRROR_ENABLED) {
+		if (!ecm_nss_common_fill_mirror_info(pr, &nircm->mirror_rule.flow_ifnum,
+					 &nircm->mirror_rule.return_ifnum)) {
+			DEBUG_WARN("Invalid Mirror interface information\n");
+			ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+			ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+			goto ported_accel_bad_rule;
+		}
+
+		if (nircm->mirror_rule.flow_ifnum != -1) {
+			nircm->mirror_rule.valid |= NSS_IPV6_MIRROR_FLOW_VALID;
+		}
+
+		if (nircm->mirror_rule.return_ifnum != -1) {
+			nircm->mirror_rule.valid |= NSS_IPV6_MIRROR_RETURN_VALID;
+		}
+
+		nircm->valid_flags |= NSS_IPV6_RULE_CREATE_MIRROR_VALID;
+	}
+#endif
+
+	if (ecm_nss_ipv6_vlan_passthrough_enable && !ecm_db_connection_is_routed_get(feci->ci) &&
+	   (nircm->vlan_primary_rule.ingress_vlan_tag == ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED) &&
+	   (nircm->vlan_primary_rule.egress_vlan_tag == ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED)) {
+		int vlan_present = 0;
+		vlan_present = skb_vlan_tag_present(skb);
+		if (vlan_present) {
+			uint32_t vlan_value;
+			vlan_value = (ETH_P_8021Q << 16) | skb_vlan_tag_get(skb);
+			nircm->vlan_primary_rule.ingress_vlan_tag = vlan_value;
+			nircm->vlan_primary_rule.egress_vlan_tag = vlan_value;
+			nircm->valid_flags |= NSS_IPV6_RULE_CREATE_VLAN_VALID;
+		}
+	}
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+		/*
+		 * Copy the both primary and secondary (if exist) VLAN tags.
+		 */
+		if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG) {
+			nircm->vlan_primary_rule.ingress_vlan_tag = pr->ingress_vlan_tag[0];
+			nircm->vlan_primary_rule.egress_vlan_tag = pr->egress_vlan_tag[0];
+			nircm->valid_flags |= NSS_IPV6_RULE_CREATE_VLAN_VALID;
+		}
+
+		if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG) {
+			nircm->vlan_secondary_rule.ingress_vlan_tag = pr->ingress_vlan_tag[1];
+			nircm->vlan_secondary_rule.egress_vlan_tag = pr->egress_vlan_tag[1];
+		}
+#endif
+	protocol = ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * Set protocol
+	 */
+	nircm->tuple.protocol = (int32_t)protocol;
+
+	/*
+	 * The flow_ip is where the connection established from
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	ECM_IP_ADDR_TO_NSS_IPV6_ADDR(nircm->tuple.flow_ip, src_ip);
+
+	/*
+	 * The dest_ip is where the connection is established to
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, dest_ip);
+	ECM_IP_ADDR_TO_NSS_IPV6_ADDR(nircm->tuple.return_ip, dest_ip);
+
+	/*
+	 * Same approach as above for port information
+	 */
+	nircm->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nircm->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	/*
+	 * Get mac addresses.
+	 * The src_mac is the mac address of the node that established the connection.
+	 * This will work whether the from_node is LAN (egress) or WAN (ingress).
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, (uint8_t *)nircm->conn_rule.flow_mac);
+
+	/*
+	 * The dest_mac is more complex.  For egress it is the node address of the 'to' side of the connection.
+	 * For ingress it is the node adress of the NAT'ed 'to' IP.
+	 * Essentially it is the MAC of node associated with create.dest_ip and this is "to nat" side.
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, (uint8_t *)nircm->conn_rule.return_mac);
+
+	/*
+	 * Get MTU information
+	 */
+	nircm->conn_rule.flow_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nircm->conn_rule.return_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	if (protocol == IPPROTO_TCP) {
+		/*
+		 * Need window scaling information from conntrack if available
+		 * Start by looking up the conntrack connection
+		 */
+		if (!ct) {
+			/*
+			 * No conntrack so no need to check window sequence space
+			 */
+			DEBUG_TRACE("%px: TCP Accel no ct from conn %px to get window data\n", npci, feci->ci);
+			nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_NO_SEQ_CHECK;
+		} else {
+			int flow_dir;
+			int return_dir;
+
+			ecm_front_end_flow_and_return_directions_get(ct, src_ip, 6, &flow_dir, &return_dir);
+
+			DEBUG_TRACE("%px: TCP Accel Get window data from ct %px for conn %px\n", npci, ct, feci->ci);
+			spin_lock_bh(&ct->lock);
+			nircm->tcp_rule.flow_window_scale = ct->proto.tcp.seen[flow_dir].td_scale;
+			nircm->tcp_rule.flow_max_window = ct->proto.tcp.seen[flow_dir].td_maxwin;
+			nircm->tcp_rule.flow_end = ct->proto.tcp.seen[flow_dir].td_end;
+			nircm->tcp_rule.flow_max_end = ct->proto.tcp.seen[flow_dir].td_maxend;
+			nircm->tcp_rule.return_window_scale = ct->proto.tcp.seen[return_dir].td_scale;
+			nircm->tcp_rule.return_max_window = ct->proto.tcp.seen[return_dir].td_maxwin;
+			nircm->tcp_rule.return_end = ct->proto.tcp.seen[return_dir].td_end;
+			nircm->tcp_rule.return_max_end = ct->proto.tcp.seen[return_dir].td_maxend;
+#ifdef ECM_OPENWRT_SUPPORT
+			if (nf_ct_tcp_be_liberal || nf_ct_tcp_no_window_check
+#else
+			if (nf_ct_tcp_be_liberal
+#endif
+					|| (ct->proto.tcp.seen[flow_dir].flags & IP_CT_TCP_FLAG_BE_LIBERAL)
+					|| (ct->proto.tcp.seen[return_dir].flags & IP_CT_TCP_FLAG_BE_LIBERAL)) {
+				nircm->rule_flags |= NSS_IPV6_RULE_CREATE_FLAG_NO_SEQ_CHECK;
+			}
+			spin_unlock_bh(&ct->lock);
+		}
+
+		nircm->valid_flags |= NSS_IPV6_RULE_CREATE_TCP_VALID;
+	}
+
+	/*
+	 * Sync our creation command from the assigned classifiers to get specific additional creation rules.
+	 * NOTE: These are called in ascending order of priority and so the last classifier (highest) shall
+	 * override any preceding classifiers.
+	 * This also gives the classifiers a chance to see that acceleration is being attempted.
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(feci->ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+		struct ecm_classifier_rule_create ecrc;
+		/*
+		 * NOTE: The current classifiers do not sync anything to the underlying accel engines.
+		 * In the future, if any of the classifiers wants to pass any parameter, these parameters
+		 * should be received via this object and copied to the accel engine's create object (nircm).
+		*/
+#ifdef ECM_CLASSIFIER_EMESH_ENABLE
+		ecrc.skb = skb;
+#endif
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: sync from: %px, type: %d\n", npci, aci, aci->type_get(aci));
+		aci->sync_from_v6(aci, &ecrc);
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Release the interface lists
+	 */
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+	ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+
+	DEBUG_INFO("%px: Ported Accelerate connection %px\n"
+			"Protocol: %d\n"
+			"from_mtu: %u\n"
+			"to_mtu: %u\n"
+			"from_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"to_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"from_mac: %pM\n"
+			"to_mac: %pM\n"
+			"src_iface_num: %u\n"
+			"dest_iface_num: %u\n"
+			"src_nexthop_num: %u\n"
+			"dest_nexthop_num: %u\n"
+			"ingress_inner_vlan_tag: %x\n"
+			"egress_inner_vlan_tag: %x\n"
+			"ingress_outer_vlan_tag: %x\n"
+			"egress_outer_vlan_tag: %x\n"
+			"rule_flags: %x\n"
+			"valid_flags: %x\n"
+			"pppoe_return_if_exist: %u\n"
+			"pppoe_return_if_num: %u\n"
+			"pppoe_flow_if_exist: %u\n"
+			"pppoe_flow_if_num: %u\n"
+			"flow_qos_tag: %x (%u)\n"
+			"return_qos_tag: %x (%u)\n"
+			"igs_flow_qos_tag: %x (%u)\n"
+			"igs_return_qos_tag: %x (%u)\n"
+			"flow_dscp: %x\n"
+			"return_dscp: %x\n",
+			npci,
+			feci->ci,
+			nircm->tuple.protocol,
+			nircm->conn_rule.flow_mtu,
+			nircm->conn_rule.return_mtu,
+			ECM_IP_ADDR_TO_OCTAL(src_ip), nircm->tuple.flow_ident,
+			ECM_IP_ADDR_TO_OCTAL(dest_ip), nircm->tuple.return_ident,
+			nircm->conn_rule.flow_mac,
+			nircm->conn_rule.return_mac,
+			nircm->conn_rule.flow_interface_num,
+			nircm->conn_rule.return_interface_num,
+			nircm->nexthop_rule.flow_nexthop,
+			nircm->nexthop_rule.return_nexthop,
+			nircm->vlan_primary_rule.ingress_vlan_tag,
+			nircm->vlan_primary_rule.egress_vlan_tag,
+			nircm->vlan_secondary_rule.ingress_vlan_tag,
+			nircm->vlan_secondary_rule.egress_vlan_tag,
+			nircm->rule_flags,
+			nircm->valid_flags,
+			nircm->pppoe_rule.return_if_exist,
+			nircm->pppoe_rule.return_if_num,
+			nircm->pppoe_rule.flow_if_exist,
+			nircm->pppoe_rule.flow_if_num,
+			nircm->qos_rule.flow_qos_tag, nircm->qos_rule.flow_qos_tag,
+			nircm->qos_rule.return_qos_tag, nircm->qos_rule.return_qos_tag,
+			nircm->igs_rule.igs_flow_qos_tag, nircm->igs_rule.igs_flow_qos_tag,
+			nircm->igs_rule.igs_return_qos_tag, nircm->igs_rule.igs_return_qos_tag,
+			nircm->dscp_rule.flow_dscp,
+			nircm->dscp_rule.return_dscp);
+
+	if (protocol == IPPROTO_TCP) {
+		DEBUG_INFO("flow_window_scale: %u\n"
+			"flow_max_window: %u\n"
+			"flow_end: %u\n"
+			"flow_max_end: %u\n"
+			"return_window_scale: %u\n"
+			"return_max_window: %u\n"
+			"return_end: %u\n"
+			"return_max_end: %u\n",
+			nircm->tcp_rule.flow_window_scale,
+			nircm->tcp_rule.flow_max_window,
+			nircm->tcp_rule.flow_end,
+			nircm->tcp_rule.flow_max_end,
+			nircm->tcp_rule.return_window_scale,
+			nircm->tcp_rule.return_max_window,
+			nircm->tcp_rule.return_end,
+			nircm->tcp_rule.return_max_end);
+	}
+
+	/*
+	 * Now that the rule has been constructed we re-compare the generation occurrance counter.
+	 * If there has been a change then we abort because the rule may have been created using
+	 * unstable data - especially if another thread has begun regeneration of the connection state.
+	 * NOTE: This does not prevent a regen from being flagged immediately after this line of code either,
+	 * or while the acceleration rule is in flight to the nss.
+	 * This is only to check for consistency of rule state - not that the state is stale.
+	 * Remember that the connection is marked as "accel pending state" so if a regen is flagged immediately
+	 * after this check passes, the connection will be decelerated and refreshed very quickly.
+	 */
+	if (regen_occurrances != ecm_db_connection_regeneration_occurrances_get(feci->ci)) {
+		DEBUG_INFO("%px: connection:%px regen occurred - aborting accel rule.\n", feci, feci->ci);
+		ecm_nss_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		kfree(nim);
+		return;
+	}
+
+	/*
+	 * Ref the connection before issuing an NSS rule
+	 * This ensures that when the NSS responds to the command - which may even be immediately -
+	 * the callback function can trust the correct ref was taken for its purpose.
+	 * NOTE: remember that this will also implicitly hold the feci.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Call the rule create function
+	 */
+	nss_tx_status = nss_ipv6_tx(ecm_nss_ipv6_nss_ipv6_mgr, nim);
+	if (nss_tx_status == NSS_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;
+		spin_unlock_bh(&feci->lock);
+		kfree(nim);
+		return;
+	}
+
+	kfree(nim);
+
+	/*
+	 * Release that ref!
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * TX failed
+	 */
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Accel mode unexpected: %d\n", npci, feci->accel_mode);
+	feci->stats.driver_fail_total++;
+	feci->stats.driver_fail++;
+	if (feci->stats.driver_fail >= feci->stats.driver_fail_limit) {
+		DEBUG_WARN("%px: Accel failed - driver fail limit\n", npci);
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DRIVER;
+	} else {
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	_ecm_nss_ipv6_accel_pending_clear(feci, result_mode);
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	spin_unlock_bh(&feci->lock);
+	return;
+
+ported_accel_bad_rule:
+	;
+
+	kfree(nim);
+
+	/*
+	 * Jump to here when rule data is bad and an offload command cannot be constructed
+	 */
+	DEBUG_WARN("%px: Accel failed - bad rule\n", npci);
+	ecm_nss_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_FAIL_RULE);
+}
+
+/*
+ * ecm_nss_ported_ipv6_connection_destroy_callback()
+ *	Callback for handling destroy ack/nack calls.
+ */
+static void ecm_nss_ported_ipv6_connection_destroy_callback(void *app_data, struct nss_ipv6_msg *nim)
+{
+	struct nss_ipv6_rule_destroy_msg *nirdm = &nim->msg.rule_destroy;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_nss_ported_ipv6_connection_instance *npci;
+	ip_addr_t flow_ip;
+	ip_addr_t return_ip;
+
+	/*
+	 * Is this a response to a destroy message?
+	 */
+	if (nim->cm.type != NSS_IPV6_TX_DESTROY_RULE_MSG) {
+		DEBUG_ERROR("%px: ported destroy callback with improper type: %d\n", nim, nim->cm.type);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: destroy callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	npci = (struct ecm_nss_ported_ipv6_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(flow_ip, nirdm->tuple.flow_ip);
+	ECM_NSS_IPV6_ADDR_TO_IP_ADDR(return_ip, nirdm->tuple.return_ip);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_nss_ipv6_decel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: decelerate response for connection: %px\n", npci, feci->ci);
+	DEBUG_TRACE("%px: flow_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", npci, ECM_IP_ADDR_TO_OCTAL(flow_ip), nirdm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", npci, ECM_IP_ADDR_TO_OCTAL(return_ip), nirdm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", npci, nirdm->tuple.protocol);
+
+	/*
+	 * Drop decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_ipv6_pending_decel_count--;
+	DEBUG_ASSERT(ecm_nss_ipv6_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If decel is not still pending then it's possible that the NSS ended acceleration by some other reason e.g. flush
+	 * In which case we cannot rely on the response we get here.
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING) {
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connections.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_TRACE("%px: response: %d\n", npci, nim->cm.response);
+	if (nim->cm.response != NSS_CMN_RESPONSE_ACK) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DECEL;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	/*
+	 * If connection became defunct then set mode so that no further accel/decel attempts occur.
+	 */
+	if (feci->is_defunct) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT_SHORT;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Ported acceleration ends
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_ported_ipv6_accelerated_count[npci->ported_accelerated_count_index]--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_nss_ported_ipv6_accelerated_count[npci->ported_accelerated_count_index] >= 0, "Bad udp accel counter\n");
+	ecm_nss_ipv6_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_nss_ipv6_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	/*
+	 * Release the connections.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_nss_ported_ipv6_connection_decelerate_msg_send()
+ *	Prepares and sends a decelerate message to acceleration engine.
+ */
+static bool ecm_nss_ported_ipv6_connection_decelerate_msg_send(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_ported_ipv6_connection_instance *npci = (struct ecm_nss_ported_ipv6_connection_instance *)feci;
+	struct nss_ipv6_msg nim;
+	struct nss_ipv6_rule_destroy_msg *nirdm;
+	ip_addr_t src_ip;
+	ip_addr_t dest_ip;
+	nss_tx_status_t nss_tx_status;
+	bool ret;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	/*
+	 * Increment the decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_ipv6_pending_decel_count++;
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	/*
+	 * Prepare deceleration message
+	 */
+	nss_ipv6_msg_init(&nim, NSS_IPV6_RX_INTERFACE, NSS_IPV6_TX_DESTROY_RULE_MSG,
+			sizeof(struct nss_ipv6_rule_destroy_msg),
+			ecm_nss_ported_ipv6_connection_destroy_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nirdm = &nim.msg.rule_destroy;
+	nirdm->tuple.protocol = (int32_t)ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * Get addressing information
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	ECM_IP_ADDR_TO_NSS_IPV6_ADDR(nirdm->tuple.flow_ip, src_ip);
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, dest_ip);
+	ECM_IP_ADDR_TO_NSS_IPV6_ADDR(nirdm->tuple.return_ip, dest_ip);
+	nirdm->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nirdm->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	DEBUG_INFO("%px: Ported Connection %px decelerate\n"
+			"protocol: %d\n"
+			"src_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"dest_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n",
+			npci, feci->ci, nirdm->tuple.protocol,
+			ECM_IP_ADDR_TO_OCTAL(src_ip), nirdm->tuple.flow_ident,
+			ECM_IP_ADDR_TO_OCTAL(dest_ip), nirdm->tuple.return_ident);
+
+	/*
+	 * Take a ref to the feci->ci so that it will persist until we get a response from the NSS.
+	 * NOTE: This will implicitly hold the feci too.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Destroy the NSS connection cache entry.
+	 */
+	nss_tx_status = nss_ipv6_tx(ecm_nss_ipv6_nss_ipv6_mgr, &nim);
+	if (nss_tx_status == NSS_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;
+		spin_unlock_bh(&feci->lock);
+		return true;
+	}
+
+	/*
+	 * TX failed
+	 */
+	ret = ecm_front_end_destroy_failure_handle(feci);
+
+	/*
+	 * Release the ref take, NSS driver did not accept our command.
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * Could not send the request, decrement the decel pending counter
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_ipv6_pending_decel_count--;
+	DEBUG_ASSERT(ecm_nss_ipv6_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	return ret;
+}
+
+/*
+ * ecm_nss_ported_ipv6_connection_decelerate()
+ *     Decelerate a connection
+ */
+static bool ecm_nss_ported_ipv6_connection_decelerate(struct ecm_front_end_connection_instance *feci)
+{
+	/*
+	 * Check if accel mode is OK for the deceleration.
+	 */
+	spin_lock_bh(&feci->lock);
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	return ecm_nss_ported_ipv6_connection_decelerate_msg_send(feci);
+}
+
+/*
+ * ecm_nss_ported_ipv6_connection_defunct_callback()
+ *	Callback to be called when a ported connection has become defunct.
+ */
+bool ecm_nss_ported_ipv6_connection_defunct_callback(void *arg, int *accel_mode)
+{
+	bool ret;
+	struct ecm_front_end_connection_instance *feci = (struct ecm_front_end_connection_instance *)arg;
+	struct ecm_nss_ported_ipv6_connection_instance *npci = (struct ecm_nss_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	spin_lock_bh(&feci->lock);
+	/*
+	 * Check if the connection can be defuncted.
+	 */
+	if (!ecm_front_end_common_connection_defunct_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+
+	/*
+	 * If none of the cases matched above, this means the connection is in the
+	 * accel mode, so we force a deceleration.
+	 * NOTE: If the mode is accel pending then the decel will be actioned when that is completed.
+	 */
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	ret = ecm_nss_ported_ipv6_connection_decelerate_msg_send(feci);
+
+	/*
+	 * Copy the accel_mode which is returned from the decelerate message function. This value
+	 * will be used in the caller to decide releasing the final reference of the connection.
+	 * But if this function reaches to here, the caller care about the ret. If ret is true,
+	 * the reference will be released regardless of the accel_mode. If ret is false, accel_mode
+	 * will be in the ACCEL state (for destroy re-try) and this state will not be used in the
+	 * caller's decision. It looks for ACCEL_FAIL states.
+	 */
+	spin_lock_bh(&feci->lock);
+	*accel_mode = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+
+	return ret;
+}
+
+/*
+ * ecm_nss_ported_ipv6_connection_accel_state_get()
+ *	Get acceleration state
+ */
+static ecm_front_end_acceleration_mode_t ecm_nss_ported_ipv6_connection_accel_state_get(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_ported_ipv6_connection_instance *npci = (struct ecm_nss_ported_ipv6_connection_instance *)feci;
+	ecm_front_end_acceleration_mode_t state;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	spin_lock_bh(&feci->lock);
+	state = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+	return state;
+}
+
+/*
+ * ecm_nss_ported_ipv6_connection_action_seen()
+ *	Acceleration action / activity has been seen for this connection.
+ *
+ * NOTE: Call the action_seen() method when the NSS has demonstrated that it has offloaded some data for a connection.
+ */
+static void ecm_nss_ported_ipv6_connection_action_seen(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_ported_ipv6_connection_instance *npci = (struct ecm_nss_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	DEBUG_INFO("%px: Action seen\n", npci);
+	spin_lock_bh(&feci->lock);
+	feci->stats.no_action_seen = 0;
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_nss_ported_ipv6_connection_accel_ceased()
+ *	NSS has indicated that acceleration has stopped.
+ *
+ * NOTE: This is called in response to an NSS self-initiated termination of acceleration.
+ * This must NOT be called because the ECM terminated the acceleration.
+ */
+static void ecm_nss_ported_ipv6_connection_accel_ceased(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_ported_ipv6_connection_instance *npci = (struct ecm_nss_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	DEBUG_INFO("%px: accel ceased\n", npci);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If we are in accel-pending state then the NSS has issued a flush out-of-order
+	 * with the ACK/NACK we are actually waiting for.
+	 * To work around this we record a "flush has already happened" and will action it when we finally get that ACK/NACK.
+	 * GGG TODO This should eventually be removed when the NSS honours messaging sequence.
+	 */
+	if (feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING) {
+		feci->stats.flush_happened = true;
+		feci->stats.flush_happened_total++;
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If connection is no longer accelerated by the time we get here just ignore the command
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_ACCEL) {
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If the no_action_seen counter was not reset then acceleration ended without any offload action
+	 */
+	if (feci->stats.no_action_seen) {
+		feci->stats.no_action_seen_total++;
+	}
+
+	/*
+	 * If the no_action_seen indicates successive cessations of acceleration without any offload action occuring
+	 * then we fail out this connection
+	 */
+	if (feci->stats.no_action_seen >= feci->stats.no_action_seen_limit) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_NO_ACTION;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Ported acceleration ends
+	 */
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	ecm_nss_ported_ipv6_accelerated_count[npci->ported_accelerated_count_index]--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_nss_ported_ipv6_accelerated_count[npci->ported_accelerated_count_index] >= 0, "Bad ported accel counter\n");
+	ecm_nss_ipv6_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_nss_ipv6_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+}
+
+/*
+ * ecm_nss_ported_ipv6_connection_ref()
+ *	Ref a connection front end instance
+ */
+static void ecm_nss_ported_ipv6_connection_ref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_ported_ipv6_connection_instance *npci = (struct ecm_nss_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	spin_lock_bh(&feci->lock);
+	feci->refs++;
+	DEBUG_TRACE("%px: npci ref %d\n", npci, feci->refs);
+	DEBUG_ASSERT(feci->refs > 0, "%px: ref wrap\n", npci);
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_nss_ported_ipv6_connection_deref()
+ *	Deref a connection front end instance
+ */
+static int ecm_nss_ported_ipv6_connection_deref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_nss_ported_ipv6_connection_instance *npci = (struct ecm_nss_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	spin_lock_bh(&feci->lock);
+	feci->refs--;
+	DEBUG_ASSERT(feci->refs >= 0, "%px: ref wrap\n", npci);
+
+	if (feci->refs > 0) {
+		int refs = feci->refs;
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: npci deref %d\n", npci, refs);
+		return refs;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * We can now destroy the instance
+	 */
+	DEBUG_TRACE("%px: npci final\n", npci);
+	DEBUG_CLEAR_MAGIC(npci);
+	kfree(npci);
+
+	return 0;
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_nss_ported_ipv6_connection_state_get()
+ *	Return the state of this ported front end instance
+ */
+static int ecm_nss_ported_ipv6_connection_state_get(struct ecm_front_end_connection_instance *feci, struct ecm_state_file_instance *sfi)
+{
+	struct ecm_nss_ported_ipv6_connection_instance *npci = (struct ecm_nss_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_NSS_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	return ecm_front_end_common_connection_state_get(feci, sfi, "nss_v6.ported");
+}
+#endif
+
+/*
+ * ecm_nss_ported_ipv6_connection_instance_alloc()
+ *	Create a front end instance specific for ported connection
+ */
+struct ecm_nss_ported_ipv6_connection_instance *ecm_nss_ported_ipv6_connection_instance_alloc(
+								bool can_accel,
+								int protocol,
+								struct ecm_db_connection_instance **nci)
+{
+	struct ecm_nss_ported_ipv6_connection_instance *npci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_db_connection_instance *ci;
+
+	if (ecm_nss_ipv6_is_conn_limit_reached()) {
+		DEBUG_TRACE("Reached connection limit\n");
+		return NULL;
+	}
+
+	/*
+	 * Now allocate the new connection
+	 */
+	*nci = ecm_db_connection_alloc();
+	if (!*nci) {
+		DEBUG_WARN("Failed to allocate connection\n");
+		return NULL;
+	}
+
+	ci = *nci;
+
+	npci = (struct ecm_nss_ported_ipv6_connection_instance *)kzalloc(sizeof(struct ecm_nss_ported_ipv6_connection_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!npci) {
+		DEBUG_WARN("Ported Front end alloc failed\n");
+		ecm_db_connection_deref(ci);
+		return NULL;
+	}
+
+	/*
+	 * Refs is 1 for the creator of the connection
+	 */
+	feci = (struct ecm_front_end_connection_instance *)npci;
+	feci->refs = 1;
+	DEBUG_SET_MAGIC(npci, ECM_NSS_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC);
+	spin_lock_init(&feci->lock);
+
+	feci->can_accel = can_accel;
+	feci->accel_mode = (can_accel) ? ECM_FRONT_END_ACCELERATION_MODE_DECEL : ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED;
+	feci->accel_engine = ECM_FRONT_END_ENGINE_NSS;
+	spin_lock_bh(&ecm_nss_ipv6_lock);
+	feci->stats.no_action_seen_limit = ecm_nss_ipv6_no_action_limit_default;
+	feci->stats.driver_fail_limit = ecm_nss_ipv6_driver_fail_limit_default;
+	feci->stats.ae_nack_limit = ecm_nss_ipv6_nack_limit_default;
+	spin_unlock_bh(&ecm_nss_ipv6_lock);
+
+	/*
+	 * Copy reference to connection - no need to ref ci as ci maintains a ref to this instance instead (this instance persists for as long as ci does)
+	 */
+	feci->ci = ci;
+
+	feci->ip_version = 6;
+
+	feci->protocol = protocol;
+
+	/*
+	 * Populate the methods and callbacks
+	 */
+	feci->ref = ecm_nss_ported_ipv6_connection_ref;
+	feci->deref = ecm_nss_ported_ipv6_connection_deref;
+	feci->accelerate = ecm_nss_ported_ipv6_connection_accelerate;
+	feci->decelerate = ecm_nss_ported_ipv6_connection_decelerate;
+	feci->accel_state_get = ecm_nss_ported_ipv6_connection_accel_state_get;
+	feci->action_seen = ecm_nss_ported_ipv6_connection_action_seen;
+	feci->accel_ceased = ecm_nss_ported_ipv6_connection_accel_ceased;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	feci->state_get = ecm_nss_ported_ipv6_connection_state_get;
+#endif
+	feci->ae_interface_number_by_dev_get = ecm_nss_common_get_interface_number_by_dev;
+	feci->ae_interface_number_by_dev_type_get = ecm_nss_common_get_interface_number_by_dev_type;
+	feci->ae_interface_type_get = ecm_nss_common_get_interface_type;
+	feci->regenerate = ecm_nss_common_connection_regenerate;
+
+	feci->get_stats_bitmap = ecm_nss_common_dummy_get_stats_bitmap;
+	feci->set_stats_bitmap = ecm_nss_common_dummy_set_stats_bitmap;
+
+	if (protocol == IPPROTO_TCP) {
+		npci->ported_accelerated_count_index = ECM_NSS_PORTED_IPV6_PROTO_TCP;
+	} else if (protocol == IPPROTO_UDP) {
+		npci->ported_accelerated_count_index = ECM_NSS_PORTED_IPV6_PROTO_UDP;
+	} else {
+		DEBUG_WARN("%px: Wrong protocol: %d\n", npci, protocol);
+		DEBUG_CLEAR_MAGIC(npci);
+		ecm_db_connection_deref(ci);
+		kfree(npci);
+		return NULL;
+	}
+
+	return npci;
+}
+
+/*
+ * ecm_nss_ported_ipv6_debugfs_init()
+ */
+bool ecm_nss_ported_ipv6_debugfs_init(struct dentry *dentry)
+{
+	struct dentry *udp_dentry;
+
+	udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry,
+						&ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_UDP]);
+	if (!udp_dentry) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 udp_accelerated_count file in debugfs\n");
+		return false;
+	}
+
+	if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry,
+					&ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP])) {
+		DEBUG_ERROR("Failed to create ecm nss ipv6 tcp_accelerated_count file in debugfs\n");
+		debugfs_remove(udp_dentry);
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-ecm/frontends/nss/ecm_nss_ported_ipv6.h b/qca-nss-ecm/frontends/nss/ecm_nss_ported_ipv6.h
new file mode 100644
index 0000000..8d0c77e
--- /dev/null
+++ b/qca-nss-ecm/frontends/nss/ecm_nss_ported_ipv6.h
@@ -0,0 +1,23 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern bool ecm_nss_ported_ipv6_debugfs_init(struct dentry *dentry);
+
+extern struct ecm_nss_ported_ipv6_connection_instance *ecm_nss_ported_ipv6_connection_instance_alloc(
+								bool can_accel,
+								int protocol,
+								struct ecm_db_connection_instance **nci);
+extern bool ecm_nss_ported_ipv6_connection_defunct_callback(void *arg, int *accel_mode);
diff --git a/qca-nss-ecm/frontends/sfe/ecm_sfe_common.c b/qca-nss-ecm/frontends/sfe/ecm_sfe_common.c
new file mode 100644
index 0000000..6cb1473
--- /dev/null
+++ b/qca-nss-ecm/frontends/sfe/ecm_sfe_common.c
@@ -0,0 +1,513 @@
+/*
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/inet.h>
+#include <net/ipv6.h>
+#include <linux/etherdevice.h>
+#include <net/sch_generic.h>
+#define DEBUG_LEVEL ECM_SFE_COMMON_DEBUG_LEVEL
+
+#include <sfe_api.h>
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_interface.h"
+#include "ecm_front_end_common.h"
+#include "ecm_sfe_ipv4.h"
+#include "ecm_sfe_ipv6.h"
+#include "ecm_sfe_common.h"
+#include "exports/ecm_sfe_common_public.h"
+
+
+/*
+ * Callback object to support SFE frontend interaction with external code
+ */
+struct ecm_sfe_common_callbacks ecm_sfe_cb;
+
+/*
+ * Sysctl table
+ */
+static struct ctl_table_header *ecm_sfe_ctl_tbl_hdr;
+
+static bool ecm_sfe_fast_xmit_enable = true;
+
+/*
+ * ecm_sfe_common_get_stats_bitmap()
+ *	Get bit map
+*/
+uint32_t ecm_sfe_common_get_stats_bitmap(struct ecm_sfe_common_fe_info *fe_info, ecm_db_obj_dir_t dir)
+{
+	switch (dir) {
+	case ECM_DB_OBJ_DIR_FROM:
+		return fe_info->from_stats_bitmap;
+
+	case ECM_DB_OBJ_DIR_TO:
+		return fe_info->to_stats_bitmap;
+
+	default:
+		DEBUG_WARN("Direction not handled dir=%d for get stats bitmap\n", dir);
+		break;
+	}
+
+	return 0;
+}
+
+/*
+ * ecm_sfe_common_set_stats_bitmap()
+ *	Set bit map
+ */
+void ecm_sfe_common_set_stats_bitmap(struct ecm_sfe_common_fe_info *fe_info, ecm_db_obj_dir_t dir, uint8_t bit)
+{
+	switch (dir) {
+	case ECM_DB_OBJ_DIR_FROM:
+		fe_info->from_stats_bitmap |= BIT(bit);
+		break;
+
+	case ECM_DB_OBJ_DIR_TO:
+		fe_info->to_stats_bitmap |= BIT(bit);
+		break;
+	default:
+		DEBUG_WARN("Direction not handled dir=%d for set stats bitmap\n", dir);
+		break;
+	}
+}
+
+/*
+ * ecm_sfe_common_is_l2_iface_supported()
+ *	Check if full offload can be supported in SFE engine for the given L2 interface and interface type
+ */
+bool ecm_sfe_common_is_l2_iface_supported(ecm_db_iface_type_t ii_type, int cur_heirarchy_index, int first_heirarchy_index)
+{
+	/*
+	 * If extended feature is not supported, we dont need to check interface heirarchy.
+	 */
+	if (!sfe_is_l2_feature_enabled()) {
+		DEBUG_TRACE("There is no support for extended features\n");
+		return false;
+	}
+
+	switch (ii_type) {
+	case ECM_DB_IFACE_TYPE_BRIDGE:
+	case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+
+		/*
+		 * Below checks ensure that bridge slave interface is not a subinterce and top interface is bridge interface.
+		 * This means that we support only ethX-br-lan in the herirarchy.
+		 * We can remove all these checks if all l2 features are supported.
+		 */
+
+		if (cur_heirarchy_index != (ECM_DB_IFACE_HEIRARCHY_MAX - 1)) {
+			DEBUG_TRACE("Top interface is not bridge, current index=%d\n", cur_heirarchy_index);
+			goto fail;
+		}
+		return true;
+
+	case ECM_DB_IFACE_TYPE_MACVLAN:
+		return true;
+
+	default:
+		break;
+	}
+
+fail:
+	return false;
+}
+
+/*
+ * ecm_sfe_common_fast_xmit_check()
+ *	Check the fast transmit feasibility.
+ *
+ * It only check device related attribute:
+ */
+bool ecm_sfe_common_fast_xmit_check(s32 interface_num)
+{
+	struct net_device *dev;
+	struct netdev_queue *txq;
+	int i;
+	struct Qdisc *q;
+#if defined(CONFIG_NET_CLS_ACT) && defined(CONFIG_NET_EGRESS)
+	struct mini_Qdisc *miniq;
+#endif
+	/*
+	 * Return failure if user has disabled SFE fast_xmit
+	 */
+	if (!ecm_sfe_fast_xmit_enable) {
+		return false;
+	}
+
+	dev = dev_get_by_index(&init_net, interface_num);
+	if (!dev) {
+		DEBUG_INFO("device-ifindex[%d] is not present\n", interface_num);
+		return false;
+	}
+
+	BUG_ON(!rcu_read_lock_bh_held());
+
+	/*
+	 * It assume that the qdisc attribute won't change after traffic
+	 * running, if the qdisc changed, we need flush all of the rule.
+	 */
+	for (i = 0; i < dev->real_num_tx_queues; i++) {
+		txq = netdev_get_tx_queue(dev, i);
+		q = rcu_dereference_bh(txq->qdisc);
+		if (q->enqueue) {
+			DEBUG_INFO("Qdisc is present for device[%s]\n", dev->name);
+			dev_put(dev);
+			return false;
+		}
+	}
+
+#if defined(CONFIG_NET_CLS_ACT) && defined(CONFIG_NET_EGRESS)
+	miniq = rcu_dereference_bh(dev->miniq_egress);
+	if (miniq) {
+		DEBUG_INFO("Egress needed\n");
+		dev_put(dev);
+		return false;
+	}
+#endif
+
+	dev_put(dev);
+
+	return true;
+}
+
+/*
+ * ecm_sfe_fast_xmit_enable_handler()
+ *	Fast transmit sysctl node handler.
+ */
+int ecm_sfe_fast_xmit_enable_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+	int ret;
+
+	/*
+	 * Write the variable with user input
+	 */
+	ret = proc_dointvec(ctl, write, buffer, lenp, ppos);
+	if (ret || (!write)) {
+		return ret;
+	}
+
+	if ((ecm_sfe_fast_xmit_enable != 0) && (ecm_sfe_fast_xmit_enable != 1)) {
+		DEBUG_WARN("Invalid input. Valid values 0/1\n");
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+/*
+ * ecm_sfe_ipv4_is_conn_limit_reached()
+ *	Connection limit is reached or not ?
+ */
+bool ecm_sfe_ipv4_is_conn_limit_reached(void)
+{
+
+#if !defined(ECM_FRONT_END_CONN_LIMIT_ENABLE)
+	return false;
+#endif
+
+	if (likely(!((ecm_front_end_is_feature_supported(ECM_FE_FEATURE_CONN_LIMIT)) && ecm_front_end_conn_limit))) {
+		return false;
+	}
+
+	if (ecm_sfe_ipv4_accelerated_count == sfe_ipv4_max_conn_count()) {
+		DEBUG_INFO("ECM DB connection limit %d reached, for SFE frontend \
+			   new flows cannot be accelerated.\n",
+			   ecm_sfe_ipv4_accelerated_count);
+		return true;
+	}
+
+	return false;
+}
+
+#ifdef ECM_IPV6_ENABLE
+/*
+ * ecm_sfe_ipv6_is_conn_limit_reached()
+ *	Connection limit is reached or not ?
+ */
+bool ecm_sfe_ipv6_is_conn_limit_reached(void)
+{
+
+#if !defined(ECM_FRONT_END_CONN_LIMIT_ENABLE)
+	return false;
+#endif
+
+	if (likely(!((ecm_front_end_is_feature_supported(ECM_FE_FEATURE_CONN_LIMIT)) && ecm_front_end_conn_limit))) {
+		return false;
+	}
+
+	if (ecm_sfe_ipv6_accelerated_count == sfe_ipv6_max_conn_count()) {
+		DEBUG_INFO("ECM DB connection limit %d reached, for SFE frontend \
+			   new flows cannot be accelerated.\n",
+			   ecm_sfe_ipv6_accelerated_count);
+		return true;
+	}
+
+	return false;
+}
+
+#endif
+
+static struct ctl_table ecm_sfe_sysctl_tbl[] = {
+	{
+		.procname	= "sfe_fast_xmit_enable",
+		.data		= &ecm_sfe_fast_xmit_enable,
+		.maxlen		= sizeof(int),
+		.mode		= 0644,
+		.proc_handler	= &ecm_sfe_fast_xmit_enable_handler,
+	},
+	{}
+};
+
+/*
+ * ecm_sfe_sysctl_tbl_init()
+ * 	Register sysctl for SFE
+ */
+int ecm_sfe_sysctl_tbl_init()
+{
+	ecm_sfe_ctl_tbl_hdr = register_sysctl(ECM_FRONT_END_SYSCTL_PATH, ecm_sfe_sysctl_tbl);
+	if (!ecm_sfe_ctl_tbl_hdr) {
+		DEBUG_WARN("Unable to register ecm_sfe_sysctl_tbl");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * ecm_sfe_sysctl_tbl_exit()
+ * 	Unregister sysctl for SFE
+ */
+void ecm_sfe_sysctl_tbl_exit()
+{
+	if (ecm_sfe_ctl_tbl_hdr) {
+		unregister_sysctl_table(ecm_sfe_ctl_tbl_hdr);
+	}
+}
+
+/*
+ * ecm_sfe_common_init_fe_info()
+ *	Initialize common fe info
+ */
+void ecm_sfe_common_init_fe_info(struct ecm_sfe_common_fe_info *info)
+{
+	info->from_stats_bitmap = 0;
+	info->to_stats_bitmap = 0;
+}
+
+/*
+ * ecm_sfe_common_update_rule()
+ *	Updates the frontend specifc data.
+ *
+ * Currently, only updates the mark values of the connection and updates the SFE AE.
+ */
+void ecm_sfe_common_update_rule(struct ecm_front_end_connection_instance *feci, enum ecm_rule_update_type type, void *arg)
+{
+
+	switch (type) {
+	case ECM_RULE_UPDATE_TYPE_CONNMARK:
+	{
+		struct nf_conn *ct = (struct nf_conn *)arg;
+		struct sfe_connection_mark mark;
+		ip_addr_t src_addr;
+		ip_addr_t dest_addr;
+		int aci_index;
+		int assignment_count;
+		struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+
+		if (feci->accel_state_get(feci) != ECM_FRONT_END_ACCELERATION_MODE_ACCEL) {
+			DEBUG_WARN("%px: connection is not in accelerated mode\n", feci);
+			return;
+		}
+
+		/*
+		 * Get connection information
+		 */
+		mark.protocol = (int32_t)ecm_db_connection_protocol_get(feci->ci);
+		mark.src_port = htons(ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM));
+		mark.dest_port = htons(ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT));
+		ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, src_addr);
+		ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, dest_addr);
+		mark.mark = ct->mark;
+
+		DEBUG_TRACE("%px: Update the mark value for the SFE connection\n", feci);
+
+		if (feci->ip_version == 4) {
+			ECM_IP_ADDR_TO_NIN4_ADDR(mark.src_ip[0], src_addr);
+			ECM_IP_ADDR_TO_NIN4_ADDR(mark.dest_ip[0], dest_addr);
+			sfe_ipv4_mark_rule_update(&mark);
+			DEBUG_TRACE("%px: src_ip: %pI4 dest_ip: %pI4 src_port: %d dest_port: %d protocol: %d\n",
+				    feci, &mark.src_ip[0], &mark.dest_ip[0],
+				    ntohs(mark.src_port), ntohs(mark.dest_port), mark.protocol);
+		} else {
+			ECM_IP_ADDR_TO_SFE_IPV6_ADDR(mark.src_ip, src_addr);
+			ECM_IP_ADDR_TO_SFE_IPV6_ADDR(mark.dest_ip, dest_addr);
+			sfe_ipv6_mark_rule_update(&mark);
+			DEBUG_TRACE("%px: src_ip: " ECM_IP_ADDR_OCTAL_FMT "dest_ip: " ECM_IP_ADDR_OCTAL_FMT
+				    " src_port: %d dest_port: %d protocol: %d\n",
+				    feci, ECM_IP_ADDR_TO_OCTAL(src_addr), ECM_IP_ADDR_TO_OCTAL(dest_addr),
+				    ntohs(mark.src_port), ntohs(mark.dest_port), mark.protocol);
+		}
+
+		/*
+		 * Get the assigned classifiers and call their update callbacks. If they are interested in this type of
+		 * update, they will handle the event.
+		 */
+		assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(feci->ci, assignments);
+		for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+			struct ecm_classifier_instance *aci;
+			aci = assignments[aci_index];
+			if (aci->update) {
+				aci->update(aci, type, ct);
+			}
+		}
+		ecm_db_connection_assignments_release(assignment_count, assignments);
+
+		break;
+	}
+	default:
+		DEBUG_WARN("%px: unsupported update rule type: %d\n", feci, type);
+		break;
+	}
+}
+
+/*
+ * ecm_sfe_common_tuple_set()
+ *	Sets the SFE common tuple object with the ECM connection rule paramaters.
+ *
+ * This tuple object will be used by external module to make decision on L2 acceleration.
+ */
+void ecm_sfe_common_tuple_set(struct ecm_front_end_connection_instance *feci,
+			      int32_t from_iface_id, int32_t to_iface_id,
+			      struct ecm_sfe_common_tuple *tuple)
+{
+	ip_addr_t saddr;
+	ip_addr_t daddr;
+
+	tuple->protocol = ecm_db_connection_protocol_get(feci->ci);
+	tuple->ip_ver = feci->ip_version;
+
+	tuple->src_port = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+        tuple->dest_port = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	tuple->src_ifindex = from_iface_id;
+	tuple->dest_ifindex = to_iface_id;
+
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, saddr);
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, daddr);
+
+	if (feci->ip_version == 4) {
+		ECM_IP_ADDR_TO_NIN4_ADDR(tuple->src_addr[0], saddr);
+		ECM_IP_ADDR_TO_NIN4_ADDR(tuple->dest_addr[0], daddr);
+	} else {
+		ECM_IP_ADDR_TO_SFE_IPV6_ADDR(tuple->src_addr, saddr);
+		ECM_IP_ADDR_TO_SFE_IPV6_ADDR(tuple->dest_addr, daddr);
+	}
+}
+
+/*
+ * ecm_sfe_common_defunct_ipv4_connection()
+ *	Defunct an IPv4 5-tuple connection.
+ */
+bool ecm_sfe_common_defunct_ipv4_connection(__be32 src_ip, int src_port,
+					    __be32 dest_ip, int dest_port, int protocol)
+{
+	return ecm_db_connection_decel_v4(src_ip, src_port, dest_ip, dest_port, protocol);
+}
+EXPORT_SYMBOL(ecm_sfe_common_defunct_ipv4_connection);
+
+/*
+ * ecm_sfe_common_defunct_ipv6_connection()
+ *	Defunct an IPv6 5-tuple connection.
+ */
+bool ecm_sfe_common_defunct_ipv6_connection(struct in6_addr *src_ip, int src_port,
+					    struct in6_addr *dest_ip, int dest_port, int protocol)
+{
+	return ecm_db_connection_decel_v6(src_ip, src_port, dest_ip, dest_port, protocol);
+}
+EXPORT_SYMBOL(ecm_sfe_common_defunct_ipv6_connection);
+
+/*
+ * ecm_sfe_common_defunct_by_protocol()
+ *	Defunct the connections by the protocol type (e.g:TCP, UDP)
+ */
+void ecm_sfe_common_defunct_by_protocol(int protocol)
+{
+	ecm_db_connection_defunct_by_protocol(protocol);
+}
+EXPORT_SYMBOL(ecm_sfe_common_defunct_by_protocol);
+
+/*
+ * ecm_sfe_common_defunct_by_port()
+ *	Defunct the connections associated with this port in the direction
+ * relative to the ECM's connection direction as well.
+ *
+ * TODO:
+ *	For now, all the connections from/to this port number are defuncted.
+ *	Directional defunct can be implemented later, but there is a trade of here:
+ *	For each connection in the database, the connection's from/to interfaces will
+ *	be checked with the wan_name and direction will be determined and then the connection
+ *	will be defuncted if there is a match with this port number. This process may be heavier
+ *	than defuncting all the connections from/to this port number. So, the direction and  wan_name
+ *	are optional for this API for now.
+ */
+void ecm_sfe_common_defunct_by_port(int port, int direction, char *wan_name)
+{
+	ecm_db_connection_defunct_by_port(htons(port), ECM_DB_OBJ_DIR_FROM);
+	ecm_db_connection_defunct_by_port(htons(port), ECM_DB_OBJ_DIR_TO);
+}
+EXPORT_SYMBOL(ecm_sfe_common_defunct_by_port);
+
+/*
+ * ecm_sfe_common_callbacks_register()
+ *	Registers SFE common callbacks.
+ */
+int ecm_sfe_common_callbacks_register(struct ecm_sfe_common_callbacks *sfe_cb)
+{
+	if (!sfe_cb || !sfe_cb->l2_accel_check) {
+		DEBUG_ERROR("SFE L2 acceleration check callback is NULL\n");
+		return -EINVAL;
+	}
+
+	rcu_assign_pointer(ecm_sfe_cb.l2_accel_check, sfe_cb->l2_accel_check);
+	synchronize_rcu();
+
+	return 0;
+}
+EXPORT_SYMBOL(ecm_sfe_common_callbacks_register);
+
+/*
+ * ecm_sfe_common_callbacks_unregister()
+ *	Unregisters SFE common callbacks.
+ */
+void ecm_sfe_common_callbacks_unregister(void)
+{
+	rcu_assign_pointer(ecm_sfe_cb.l2_accel_check, NULL);
+	synchronize_rcu();
+}
+EXPORT_SYMBOL(ecm_sfe_common_callbacks_unregister);
diff --git a/qca-nss-ecm/frontends/sfe/ecm_sfe_common.h b/qca-nss-ecm/frontends/sfe/ecm_sfe_common.h
new file mode 100644
index 0000000..54625f3
--- /dev/null
+++ b/qca-nss-ecm/frontends/sfe/ecm_sfe_common.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "ecm_sfe_common_public.h"
+
+/*
+ * Export the callback object for frontend usage.
+ */
+extern struct ecm_sfe_common_callbacks ecm_sfe_cb;
+
+#ifdef CONFIG_XFRM
+/*
+ * Which type of ipsec process traffic need.
+ */
+enum ecm_sfe_ipsec_state {
+	ECM_SFE_IPSEC_STATE_NONE = 0,
+	ECM_SFE_IPSEC_STATE_TO_ENCRYPT,
+	ECM_SFE_IPSEC_STATE_WAS_DECRYPTED
+};
+#endif
+
+/*
+ * This macro converts ECM ip_addr_t to SFE IPv6 address
+ */
+#define ECM_IP_ADDR_TO_SFE_IPV6_ADDR(sfe6, ipaddrt) \
+	{ \
+		ecm_type_check_ae_ipv6(sfe6); \
+		ecm_type_check_ecm_ip_addr(ipaddrt); \
+		sfe6[0] = htonl(ipaddrt[3]); \
+		sfe6[1] = htonl(ipaddrt[2]); \
+		sfe6[2] = htonl(ipaddrt[1]); \
+		sfe6[3] = htonl(ipaddrt[0]); \
+	}
+
+/*
+ * This macro converts SFE IPv6 address to ECM ip_addr_t
+ */
+#define ECM_SFE_IPV6_ADDR_TO_IP_ADDR(ipaddrt, sfe6) \
+	{ \
+		ecm_type_check_ecm_ip_addr(ipaddrt); \
+		ecm_type_check_ae_ipv6(sfe6); \
+		ipaddrt[0] = ntohl(sfe6[3]); \
+		ipaddrt[1] = ntohl(sfe6[2]); \
+		ipaddrt[2] = ntohl(sfe6[1]); \
+		ipaddrt[3] = ntohl(sfe6[0]); \
+	}
+
+/*
+ * Common information
+ */
+struct ecm_sfe_common_fe_info {
+	uint32_t from_stats_bitmap;	/* Bitmap of L2 features enabled for from direction */
+	uint32_t to_stats_bitmap;	/* Bitmap of L2 features enabled for to direction */
+};
+
+/*
+ * ecm_sfe_feature_check()
+ *	Check some specific features for SFE acceleration
+ */
+static inline bool ecm_sfe_feature_check(struct sk_buff *skb, struct ecm_tracker_ip_header *ip_hdr, bool is_routed)
+{
+	if (!is_routed && !sfe_is_l2_feature_enabled()) {
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * ecm_sfe_common_get_interface_number_by_dev()
+ *	Returns the acceleration engine interface number based on the net_device object.
+ */
+static inline int32_t ecm_sfe_common_get_interface_number_by_dev(struct net_device *dev)
+{
+	/*
+	 * sfe_interface_num for all IPsec tunnels will always be the one specific to acceleration engine.
+	 */
+	if (dev->type == ECM_ARPHRD_IPSEC_TUNNEL_TYPE) {
+		return SFE_SPECIAL_INTERFACE_IPSEC;
+	}
+
+	return dev->ifindex;
+}
+
+/*
+ * ecm_sfe_common_get_interface_number_by_dev_type()
+ *	Returns the acceleration engine interface number based on the net_device object and type.
+ */
+static inline int32_t ecm_sfe_common_get_interface_number_by_dev_type(struct net_device *dev, uint32_t type)
+{
+
+	return ecm_sfe_common_get_interface_number_by_dev(dev);
+}
+
+/*
+ * ecm_sfe_common_connection_regenerate()
+ *	Re-generate a specific connection in SFE front end
+ */
+static inline void ecm_sfe_common_connection_regenerate(struct ecm_front_end_connection_instance *feci, struct ecm_db_connection_instance *ci)
+{
+	/*
+	 * Flag the connection as needing re-generation.
+	 * Re-generation occurs when we next see traffic OR an acceleration engine sync for this connection.
+	 * Refer to front end protocol specific process() functions.
+	 */
+	ecm_db_connection_regeneration_needed(ci);
+
+	/*
+	 * If the connection is accelerated then force deceleration.
+	 * Under normal circumstances deceleration would occur on the next sync received,
+	 * however, there is a situation where a sync may not occur if, say, a cable has been pulled.
+	 * The acceleration engine would see no further traffic to trigger sending a sync and so
+	 * re-generation would not occur.
+	 * The connection would stall and no-regeneration would happen leaving the connection in bad state.
+	 * NOTE: We can just call decelerate() upon the front end - if its not accelerated this will have no effect.
+	 */
+	feci->decelerate(feci);
+}
+
+/*
+ * ecm_sfe_common_get_interface_type()
+ *	Gets the SFE interface type based on some features.
+ *
+ * NOTE: There is no type for SFE now. This function is implemented just to
+ * use it for the feci callback.
+ */
+static inline int32_t ecm_sfe_common_get_interface_type(struct ecm_front_end_connection_instance *feci, struct net_device *dev)
+{
+	/*
+	 * By default return 0. SFE driver doesn't have any interface type.
+	 */
+	return 0;
+}
+
+bool ecm_sfe_common_fast_xmit_check(s32 interface_num);
+bool ecm_sfe_ipv4_is_conn_limit_reached(void);
+bool ecm_sfe_ipv6_is_conn_limit_reached(void);
+bool ecm_sfe_common_is_l2_iface_supported(ecm_db_iface_type_t ii_type, int cur_heirarchy_index, int first_heirarchy_index);
+
+void ecm_sfe_common_init_fe_info(struct ecm_sfe_common_fe_info *info);
+uint32_t ecm_sfe_common_get_stats_bitmap(struct ecm_sfe_common_fe_info *fe_info, ecm_db_obj_dir_t dir);
+void ecm_sfe_common_set_stats_bitmap(struct ecm_sfe_common_fe_info *fe_info, ecm_db_obj_dir_t dir, uint8_t bit);
+void ecm_sfe_common_update_rule(struct ecm_front_end_connection_instance *feci, enum ecm_rule_update_type type, void *arg);
+void ecm_sfe_common_tuple_set(struct ecm_front_end_connection_instance *feci,
+			      int32_t from_iface_id, int32_t to_iface_id,
+			      struct ecm_sfe_common_tuple *tuple);
diff --git a/qca-nss-ecm/frontends/sfe/ecm_sfe_ipv4.c b/qca-nss-ecm/frontends/sfe/ecm_sfe_ipv4.c
new file mode 100644
index 0000000..262b495
--- /dev/null
+++ b/qca-nss-ecm/frontends/sfe/ecm_sfe_ipv4.c
@@ -0,0 +1,812 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/ppp_defs.h>
+#include <linux/mroute.h>
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <linux/netfilter/nf_conntrack_zones_common.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/nf_conntrack_timeout.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_SFE_IPV4_DEBUG_LEVEL
+
+#include <sfe_api.h>
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+#include "ecm_classifier_nl.h"
+#endif
+#include "ecm_interface.h"
+#include "ecm_sfe_ported_ipv4.h"
+#include "ecm_front_end_common.h"
+#include "ecm_front_end_ipv4.h"
+
+int ecm_sfe_ipv4_no_action_limit_default = 250;		/* Default no-action limit. */
+int ecm_sfe_ipv4_driver_fail_limit_default = 250;		/* Default driver fail limit. */
+int ecm_sfe_ipv4_nack_limit_default = 250;			/* Default nack limit. */
+int ecm_sfe_ipv4_accelerated_count = 0;			/* Total offloads */
+int ecm_sfe_ipv4_pending_accel_count = 0;			/* Total pending offloads issued to the SFE / awaiting completion */
+int ecm_sfe_ipv4_pending_decel_count = 0;			/* Total pending deceleration requests issued to the SFE / awaiting completion */
+
+/*
+ * Limiting the acceleration of connections.
+ *
+ * By default there is no acceleration limiting.
+ * This means that when ECM has more connections (that can be accelerated) than the acceleration
+ * engine will allow the ECM will continue to try to accelerate.
+ * In this scenario the acceleration engine will begin removal of existing rules to make way for new ones.
+ * When the accel_limit_mode is set to FIXED ECM will not permit more rules to be issued than the engine will allow.
+ */
+uint32_t ecm_sfe_ipv4_accel_limit_mode = ECM_FRONT_END_ACCEL_LIMIT_MODE_UNLIMITED;
+
+/*
+ * Locking of the classifier - concurrency control for file global parameters.
+ * NOTE: It is safe to take this lock WHILE HOLDING a feci->lock.  The reverse is NOT SAFE.
+ */
+DEFINE_SPINLOCK(ecm_sfe_ipv4_lock);			/* Protect against SMP access between netfilter, events and private threaded function. */
+
+/*
+ * SFE driver linkage
+ */
+struct sfe_ctx_instance *ecm_sfe_ipv4_mgr = NULL;
+
+static unsigned long ecm_sfe_ipv4_accel_cmd_time_avg_samples = 0;	/* Sum of time taken for the set of accel command samples, used to compute average time for an accel command to complete */
+static unsigned long ecm_sfe_ipv4_accel_cmd_time_avg_set = 1;	/* How many samples in the set */
+static unsigned long ecm_sfe_ipv4_decel_cmd_time_avg_samples = 0;	/* Sum of time taken for the set of accel command samples, used to compute average time for an accel command to complete */
+static unsigned long ecm_sfe_ipv4_decel_cmd_time_avg_set = 1;	/* How many samples in the set */
+
+#ifdef CONFIG_XFRM
+static int ecm_sfe_ipv4_reject_acceleration_for_ipsec;		/* Don't accelerate IPSEC traffic */
+#endif
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_sfe_ipv4_dentry;
+
+/*
+ * ecm_sfe_ipv4_accel_done_time_update()
+ *	Record how long the command took to complete, updating average samples
+ */
+void ecm_sfe_ipv4_accel_done_time_update(struct ecm_front_end_connection_instance *feci)
+{
+	unsigned long delta;
+
+	/*
+	 * How long did it take the command to complete?
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_completed = jiffies;
+	delta = feci->stats.cmd_time_completed - feci->stats.cmd_time_begun;
+	spin_unlock_bh(&feci->lock);
+
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	ecm_sfe_ipv4_accel_cmd_time_avg_samples += delta;
+	ecm_sfe_ipv4_accel_cmd_time_avg_set++;
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+}
+
+/*
+ * ecm_sfe_ipv4_deccel_done_time_update()
+ *	Record how long the command took to complete, updating average samples
+ */
+void ecm_sfe_ipv4_decel_done_time_update(struct ecm_front_end_connection_instance *feci)
+{
+	unsigned long delta;
+
+	/*
+	 * How long did it take the command to complete?
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_completed = jiffies;
+	delta = feci->stats.cmd_time_completed - feci->stats.cmd_time_begun;
+	spin_unlock_bh(&feci->lock);
+
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	ecm_sfe_ipv4_decel_cmd_time_avg_samples += delta;
+	ecm_sfe_ipv4_decel_cmd_time_avg_set++;
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+}
+
+/*
+ * ecm_sfe_ipv4_stats_sync_callback()
+ *	Callback handler from the SFE.
+ */
+static void ecm_sfe_ipv4_stats_sync_callback(void *app_data, struct sfe_ipv4_msg *nim)
+{
+	struct sfe_ipv4_conn_sync *sync;
+	struct nf_conntrack_tuple_hash *h;
+	struct nf_conntrack_tuple tuple;
+	struct nf_conn *ct;
+	struct nf_conn_counter *acct;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct neighbour *neigh;
+	ip_addr_t flow_ip;
+	ip_addr_t return_ip_xlate;
+	ip_addr_t return_ip;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	struct ecm_classifier_rule_sync class_sync;
+	int flow_dir;
+	int return_dir;
+	int flow_ident;
+	int return_ident_xlate;
+
+	/*
+	 * Only respond to sync messages
+	 */
+	if (nim->cm.type != SFE_RX_CONN_STATS_SYNC_MSG) {
+		DEBUG_TRACE("Ignoring nim: %px - not sync: %d", nim, nim->cm.type);
+		return;
+	}
+	sync = &nim->msg.conn_stats;
+
+	/*
+	 * Look up ecm connection with a view to synchronising the connection, classifier and data tracker.
+	 * Note that we use _xlate versions for destination - for egressing connections this would be the wan IP address,
+	 * but for ingressing this would be the LAN side (non-nat'ed) address and is what we need for lookup of our connection.
+	 */
+	DEBUG_INFO("%px: SFE Sync, lookup connection using\n"
+			"Protocol: %d\n" \
+			"src_addr: %pI4n:%d\n" \
+			"dest_addr: %pI4n:%d\n",
+			sync,
+			(int)sync->protocol,
+			&sync->flow_ip, (int)sync->flow_ident,
+			&sync->return_ip_xlate, (int)sync->return_ident_xlate);
+
+	ECM_NIN4_ADDR_TO_IP_ADDR(flow_ip, sync->flow_ip);
+	ECM_NIN4_ADDR_TO_IP_ADDR(return_ip_xlate, sync->return_ip_xlate);
+	ECM_NIN4_ADDR_TO_IP_ADDR(return_ip, sync->return_ip);
+	flow_ident = (int)sync->flow_ident;
+	return_ident_xlate = (int)sync->return_ident_xlate;
+
+	/*
+	 * GRE connections such as PPTP-GRE are stored into the db using a 3 tuple based hash.
+	 * So we ignore the port information here when trying to lookup the connection
+	 */
+	if (sync->protocol == IPPROTO_GRE) {
+		flow_ident = 0;
+		return_ident_xlate = 0;
+	}
+
+	ci = ecm_db_connection_find_and_ref(flow_ip, return_ip_xlate, sync->protocol, ntohs(flow_ident), ntohs(return_ident_xlate));
+
+	if (!ci) {
+		DEBUG_TRACE("%px: SFE Sync: no connection\n", sync);
+		goto sync_conntrack;
+	}
+	DEBUG_TRACE("%px: Sync conn %px\n", sync, ci);
+
+	/*
+	 * Copy the sync data to the classifier sync structure to
+	 * update the classifiers' stats.
+	 */
+	class_sync.tx_packet_count[ECM_CONN_DIR_FLOW] = sync->flow_tx_packet_count;
+	class_sync.tx_byte_count[ECM_CONN_DIR_FLOW] = sync->flow_tx_byte_count;
+	class_sync.rx_packet_count[ECM_CONN_DIR_FLOW] = sync->flow_rx_packet_count;
+	class_sync.rx_byte_count[ECM_CONN_DIR_FLOW] = sync->flow_rx_byte_count;
+	class_sync.tx_packet_count[ECM_CONN_DIR_RETURN] = sync->return_tx_packet_count;
+	class_sync.tx_byte_count[ECM_CONN_DIR_RETURN] = sync->return_tx_byte_count;
+	class_sync.rx_packet_count[ECM_CONN_DIR_RETURN] = sync->return_rx_packet_count;
+	class_sync.rx_byte_count[ECM_CONN_DIR_RETURN] = sync->return_rx_byte_count;
+	class_sync.reason = sync->reason;
+
+	/*
+	 * Sync assigned classifiers
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: sync to: %px, type: %d\n", ci, aci, aci->type_get(aci));
+		aci->sync_to_v4(aci, &class_sync);
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Keep connection alive and updated
+	 */
+	if (!ecm_db_connection_defunct_timer_touch(ci)) {
+		ecm_db_connection_deref(ci);
+		goto sync_conntrack;
+	}
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+	if (sync->flow_tx_packet_count || sync->return_tx_packet_count) {
+		DEBUG_TRACE("%px: flow_rx_packet_count: %u, flow_rx_byte_count: %u, return_rx_packet_count: %u, return_rx_byte_count: %u\n",
+				ci, sync->flow_rx_packet_count, sync->flow_rx_byte_count, sync->return_rx_packet_count, sync->return_rx_byte_count);
+		DEBUG_TRACE("%px: flow_tx_packet_count: %u, flow_tx_byte_count: %u, return_tx_packet_count: %u, return_tx_byte_count: %u\n",
+				ci, sync->flow_tx_packet_count, sync->flow_tx_byte_count, sync->return_tx_packet_count, sync->return_tx_byte_count);
+		/*
+		 * The amount of data *sent* by the ECM connection 'from' side is the amount the SFE has *received* in the 'flow' direction.
+		 */
+		ecm_db_connection_data_totals_update(ci, true, sync->flow_rx_byte_count, sync->flow_rx_packet_count);
+
+		/*
+		 * The amount of data *sent* by the ECM connection 'to' side is the amount the SFE has *received* in the 'return' direction.
+		 */
+		ecm_db_connection_data_totals_update(ci, false, sync->return_rx_byte_count, sync->return_rx_packet_count);
+
+		/*
+		 * As packets have been accelerated we have seen some action.
+		 */
+		feci->action_seen(feci);
+
+		/*
+		 * Update interface stats
+		 */
+		ecm_interface_stats_update(ci, sync->flow_tx_packet_count, sync->flow_tx_byte_count, sync->flow_rx_packet_count,
+				sync->flow_rx_byte_count, sync->return_tx_packet_count, sync->return_tx_byte_count, sync->return_rx_packet_count, sync->return_rx_byte_count);
+	}
+
+	switch(sync->reason) {
+	case SFE_RULE_SYNC_REASON_DESTROY:
+		/*
+		 * This is the final sync from the SFE for a connection whose acceleration was
+		 * terminated by the ecm.
+		 * NOTE: We take no action here since that is performed by the destroy message ack.
+		 */
+		DEBUG_INFO("%px: ECM initiated final sync seen: %d\n", ci, sync->reason);
+
+		/*
+		 * If there is no tx/rx packets to update the other linux subsystems, we shouldn't continue
+		 * for the sync message which comes as a final sync for the ECM initiated destroy request.
+		 * Because this means the connection is not active for sometime and adding this delta time
+		 * to the conntrack timeout will update it eventhough there is no traffic for this connection.
+		 */
+		if (!sync->flow_tx_packet_count && !sync->return_tx_packet_count) {
+			feci->deref(feci);
+			ecm_db_connection_deref(ci);
+			return;
+		}
+		break;
+	case SFE_RULE_SYNC_REASON_FLUSH:
+	case SFE_RULE_SYNC_REASON_EVICT:
+		/*
+		 * SFE has ended acceleration without instruction from the ECM.
+		 */
+		DEBUG_INFO("%px: SFE Initiated final sync seen: %d cause:%d\n", ci, sync->reason, sync->cause);
+
+		/*
+		 * SFE Decelerated the connection
+		 */
+		feci->accel_ceased(feci);
+		break;
+	default:
+		if (ecm_db_connection_is_routed_get(ci)) {
+			/*
+			 * Update the neighbour entry for source IP address
+			 */
+			neigh = ecm_interface_ipv4_neigh_get(flow_ip);
+			if (!neigh) {
+				DEBUG_WARN("Neighbour entry for %pI4n not found\n", &sync->flow_ip);
+			} else {
+				if (sync->flow_tx_packet_count) {
+					DEBUG_TRACE("Neighbour entry event send for %pI4n: %px\n", &sync->flow_ip, neigh);
+					neigh_event_send(neigh, NULL);
+				}
+
+				neigh_release(neigh);
+			}
+
+			/*
+			 * Update the neighbour entry for destination IP address
+			 */
+			neigh = ecm_interface_ipv4_neigh_get(return_ip);
+			if (!neigh) {
+				DEBUG_WARN("Neighbour entry for %pI4n not found\n", &sync->return_ip);
+			} else {
+				if (sync->return_tx_packet_count) {
+					DEBUG_TRACE("Neighbour entry event send for %pI4n: %px\n", &sync->return_ip, neigh);
+					neigh_event_send(neigh, NULL);
+				}
+
+				neigh_release(neigh);
+			}
+		}
+	}
+
+	/*
+	 * If connection should be re-generated then we need to force a deceleration
+	 */
+	if (unlikely(ecm_db_connection_regeneration_required_peek(ci))) {
+		DEBUG_TRACE("%px: Connection generation changing, terminating acceleration", ci);
+		feci->decelerate(feci);
+	}
+
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+
+sync_conntrack:
+	;
+
+	/*
+	 * Create a tuple so as to be able to look up a conntrack connection
+	 */
+	memset(&tuple, 0, sizeof(tuple));
+	tuple.src.u3.ip = sync->flow_ip;
+	tuple.src.u.all = sync->flow_ident;
+	tuple.src.l3num = AF_INET;
+
+	tuple.dst.u3.ip = sync->return_ip;
+	tuple.dst.dir = IP_CT_DIR_ORIGINAL;
+	tuple.dst.protonum = (uint8_t)sync->protocol;
+	tuple.dst.u.all = sync->return_ident;
+
+	DEBUG_TRACE("Conntrack sync, lookup conntrack connection using\n"
+			"Protocol: %d\n"
+			"src_addr: %pI4:%d\n"
+			"dest_addr: %pI4:%d\n",
+			(int)tuple.dst.protonum,
+			&tuple.src.u3.ip, (int)(ntohs(tuple.src.u.all)),
+			&tuple.dst.u3.ip, (int)(ntohs(tuple.dst.u.all)));
+
+	/*
+	 * Look up conntrack connection
+	 */
+	h = nf_conntrack_find_get(&init_net, &nf_ct_zone_dflt, &tuple);
+	if (!h) {
+		DEBUG_WARN("%px: SFE Sync: no conntrack connection\n", sync);
+		return;
+	}
+
+	ct = nf_ct_tuplehash_to_ctrack(h);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0))
+	NF_CT_ASSERT(ct->timeout.data == (unsigned long)ct);
+#endif
+	DEBUG_TRACE("%px: SFE Sync: conntrack connection\n", ct);
+
+	ecm_front_end_flow_and_return_directions_get(ct, flow_ip, 4, &flow_dir, &return_dir);
+
+	/*
+	 * Only update if this is not a fixed timeout
+	 */
+	if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) {
+		unsigned long int delta_jiffies;
+
+		/*
+		 * Convert ms ticks from the SFE to jiffies. We know that inc_ticks is small
+		 * and we expect HZ to be small too so we can multiply without worrying about
+		 * wrap-around problems.  We add a rounding constant to ensure that the different
+		 * time bases don't cause truncation errors.
+		 */
+		delta_jiffies = ((sync->inc_ticks * HZ) + (MSEC_PER_SEC / 2)) / MSEC_PER_SEC;
+
+		spin_lock_bh(&ct->lock);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0))
+		ct->timeout.expires += delta_jiffies;
+#else
+		ct->timeout += delta_jiffies;
+#endif
+		spin_unlock_bh(&ct->lock);
+	}
+
+	acct = nf_conn_acct_find(ct)->counter;
+	if (acct) {
+		spin_lock_bh(&ct->lock);
+		atomic64_add(sync->flow_rx_packet_count, &acct[flow_dir].packets);
+		atomic64_add(sync->flow_rx_byte_count, &acct[flow_dir].bytes);
+
+		atomic64_add(sync->return_rx_packet_count, &acct[return_dir].packets);
+		atomic64_add(sync->return_rx_byte_count, &acct[return_dir].bytes);
+		spin_unlock_bh(&ct->lock);
+	}
+
+	switch (sync->protocol) {
+	case IPPROTO_TCP:
+		spin_lock_bh(&ct->lock);
+		if (ct->proto.tcp.seen[flow_dir].td_maxwin < sync->flow_max_window) {
+			ct->proto.tcp.seen[flow_dir].td_maxwin = sync->flow_max_window;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[flow_dir].td_end - sync->flow_end) < 0) {
+			ct->proto.tcp.seen[flow_dir].td_end = sync->flow_end;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[flow_dir].td_maxend - sync->flow_max_end) < 0) {
+			ct->proto.tcp.seen[flow_dir].td_maxend = sync->flow_max_end;
+		}
+		if (ct->proto.tcp.seen[return_dir].td_maxwin < sync->return_max_window) {
+			ct->proto.tcp.seen[return_dir].td_maxwin = sync->return_max_window;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[return_dir].td_end - sync->return_end) < 0) {
+			ct->proto.tcp.seen[return_dir].td_end = sync->return_end;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[return_dir].td_maxend - sync->return_max_end) < 0) {
+			ct->proto.tcp.seen[return_dir].td_maxend = sync->return_max_end;
+		}
+		spin_unlock_bh(&ct->lock);
+		break;
+	case IPPROTO_UDP:
+		/*
+		 * In Linux connection track, UDP flow has two timeout values:
+		 * /proc/sys/net/netfilter/nf_conntrack_udp_timeout:
+		 * 	this is for uni-direction UDP flow, normally its value is 60 seconds
+		 * /proc/sys/net/netfilter/nf_conntrack_udp_timeout_stream:
+		 * 	this is for bi-direction UDP flow, normally its value is 180 seconds
+		 *
+		 * Linux will update timer of UDP flow to stream timeout once it seen packets
+		 * in reply direction. But if flow is accelerated by NSS or SFE, Linux won't
+		 * see any packets. So we have to do the same thing in our stats sync message.
+		 */
+		if (!test_bit(IPS_ASSURED_BIT, &ct->status) && acct) {
+			u_int64_t reply_pkts = atomic64_read(&acct[IP_CT_DIR_REPLY].packets);
+
+			if (reply_pkts != 0) {
+				struct nf_conntrack_l4proto *l4proto __maybe_unused;
+				unsigned int *timeouts;
+
+				set_bit(IPS_SEEN_REPLY_BIT, &ct->status);
+				set_bit(IPS_ASSURED_BIT, &ct->status);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0))
+				l4proto = __nf_ct_l4proto_find(AF_INET, IPPROTO_UDP);
+				timeouts = nf_ct_timeout_lookup(&init_net, ct, l4proto);
+
+				spin_lock_bh(&ct->lock);
+				ct->timeout.expires = jiffies + timeouts[UDP_CT_REPLIED];
+				spin_unlock_bh(&ct->lock);
+#else
+				timeouts = nf_ct_timeout_lookup(ct);
+				if (!timeouts) {
+					timeouts = udp_get_timeouts(nf_ct_net(ct));
+				}
+
+				spin_lock_bh(&ct->lock);
+				ct->timeout = jiffies + timeouts[UDP_CT_REPLIED];
+				spin_unlock_bh(&ct->lock);
+#endif
+			}
+		}
+		break;
+	}
+
+	/*
+	 * Release connection
+	 */
+	nf_ct_put(ct);
+}
+
+/*
+ * ecm_sfe_ipv4_get_accel_limit_mode()
+ */
+static int ecm_sfe_ipv4_get_accel_limit_mode(void *data, u64 *val)
+{
+	*val = ecm_sfe_ipv4_accel_limit_mode;
+
+	return 0;
+}
+
+/*
+ * ecm_sfe_ipv4_set_accel_limit_mode()
+ */
+static int ecm_sfe_ipv4_set_accel_limit_mode(void *data, u64 val)
+{
+	DEBUG_TRACE("ecm_sfe_ipv4_accel_limit_mode = %x\n", (int)val);
+
+	/*
+	 * Check that only valid bits are set.
+	 * It's fine for no bits to be set as that suggests no modes are wanted.
+	 */
+	if (val && (val ^ (ECM_FRONT_END_ACCEL_LIMIT_MODE_FIXED | ECM_FRONT_END_ACCEL_LIMIT_MODE_UNLIMITED))) {
+		DEBUG_WARN("ecm_sfe_ipv4_accel_limit_mode = %x bad\n", (int)val);
+		return -EINVAL;
+	}
+
+	ecm_sfe_ipv4_accel_limit_mode = (int)val;
+
+	return 0;
+}
+
+/*
+ * Debugfs attribute for accel limit mode.
+ */
+DEFINE_SIMPLE_ATTRIBUTE(ecm_sfe_ipv4_accel_limit_mode_fops, ecm_sfe_ipv4_get_accel_limit_mode, ecm_sfe_ipv4_set_accel_limit_mode, "%llu\n");
+
+/*
+ * ecm_sfe_ipv4_get_accel_cmd_avg_millis()
+ */
+static ssize_t ecm_sfe_ipv4_get_accel_cmd_avg_millis(struct file *file,
+								char __user *user_buf,
+								size_t sz, loff_t *ppos)
+{
+	unsigned long set;
+	unsigned long samples;
+	unsigned long avg;
+	char *buf;
+	int ret;
+
+	buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!buf) {
+		return -ENOMEM;
+	}
+
+	/*
+	 * Operate under our locks.
+	 * Compute the average of the samples taken and seed the next set of samples with the result of this one.
+	 */
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	samples = ecm_sfe_ipv4_accel_cmd_time_avg_samples;
+	set = ecm_sfe_ipv4_accel_cmd_time_avg_set;
+	ecm_sfe_ipv4_accel_cmd_time_avg_samples /= ecm_sfe_ipv4_accel_cmd_time_avg_set;
+	ecm_sfe_ipv4_accel_cmd_time_avg_set = 1;
+	avg = ecm_sfe_ipv4_accel_cmd_time_avg_samples;
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+	/*
+	 * Convert average jiffies to milliseconds
+	 */
+	avg *= 1000;
+	avg /= HZ;
+
+	ret = snprintf(buf, (ssize_t)PAGE_SIZE, "avg=%lu\tsamples=%lu\tset_size=%lu\n", avg, samples, set);
+	if (ret < 0) {
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	ret = simple_read_from_buffer(user_buf, sz, ppos, buf, ret);
+	kfree(buf);
+	return ret;
+}
+
+/*
+ * File operations for accel command average time.
+ */
+static struct file_operations ecm_sfe_ipv4_accel_cmd_avg_millis_fops = {
+	.read = ecm_sfe_ipv4_get_accel_cmd_avg_millis,
+};
+
+/*
+ * ecm_sfe_ipv4_get_decel_average_millis()
+ */
+static ssize_t ecm_sfe_ipv4_get_decel_cmd_avg_millis(struct file *file,
+								char __user *user_buf,
+								size_t sz, loff_t *ppos)
+{
+	unsigned long set;
+	unsigned long samples;
+	unsigned long avg;
+	char *buf;
+	int ret;
+
+	buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!buf) {
+		return -ENOMEM;
+	}
+
+	/*
+	 * Operate under our locks.
+	 * Compute the average of the samples taken and seed the next set of samples with the result of this one.
+	 */
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	samples = ecm_sfe_ipv4_decel_cmd_time_avg_samples;
+	set = ecm_sfe_ipv4_decel_cmd_time_avg_set;
+	ecm_sfe_ipv4_decel_cmd_time_avg_samples /= ecm_sfe_ipv4_decel_cmd_time_avg_set;
+	ecm_sfe_ipv4_decel_cmd_time_avg_set = 1;
+	avg = ecm_sfe_ipv4_decel_cmd_time_avg_samples;
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+	/*
+	 * Convert average jiffies to milliseconds
+	 */
+	avg *= 1000;
+	avg /= HZ;
+
+	ret = snprintf(buf, (ssize_t)PAGE_SIZE, "avg=%lu\tsamples=%lu\tset_size=%lu\n", avg, samples, set);
+	if (ret < 0) {
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	ret = simple_read_from_buffer(user_buf, sz, ppos, buf, ret);
+	kfree(buf);
+	return ret;
+}
+
+/*
+ * File operations for decel command average time.
+ */
+static struct file_operations ecm_sfe_ipv4_decel_cmd_avg_millis_fops = {
+	.read = ecm_sfe_ipv4_get_decel_cmd_avg_millis,
+};
+
+/*
+ * ecm_sfe_ipv4_init()
+ */
+int ecm_sfe_ipv4_init(struct dentry *dentry)
+{
+	int result = -1;
+
+	if (!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_SFE)) {
+		DEBUG_INFO("SFE IPv4 is disabled\n");
+		return 0;
+	}
+
+	DEBUG_INFO("ECM SFE IPv4 init\n");
+
+	ecm_sfe_ipv4_dentry = debugfs_create_dir("ecm_sfe_ipv4", dentry);
+	if (!ecm_sfe_ipv4_dentry) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv4 directory in debugfs\n");
+		return result;
+	}
+
+#ifdef CONFIG_XFRM
+	if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry,
+					(u32 *)&ecm_sfe_ipv4_reject_acceleration_for_ipsec)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv4 reject_acceleration_for_ipsec file in debugfs\n");
+		goto task_cleanup;
+	}
+#endif
+
+	if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry,
+					(u32 *)&ecm_sfe_ipv4_no_action_limit_default)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv4 no_action_limit_default file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry,
+					(u32 *)&ecm_sfe_ipv4_driver_fail_limit_default)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv4 driver_fail_limit_default file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry,
+					(u32 *)&ecm_sfe_ipv4_nack_limit_default)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv4 nack_limit_default file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv4_dentry,
+					(u32 *)&ecm_sfe_ipv4_accelerated_count)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv4 accelerated_count file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv4_dentry,
+					(u32 *)&ecm_sfe_ipv4_pending_accel_count)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_accel_count file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv4_dentry,
+					(u32 *)&ecm_sfe_ipv4_pending_decel_count)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_decel_count file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry,
+					NULL, &ecm_sfe_ipv4_accel_limit_mode_fops)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv4 accel_limit_mode file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_file("accel_cmd_avg_millis", S_IRUGO, ecm_sfe_ipv4_dentry,
+					NULL, &ecm_sfe_ipv4_accel_cmd_avg_millis_fops)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv4 accel_cmd_avg_millis file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_file("decel_cmd_avg_millis", S_IRUGO, ecm_sfe_ipv4_dentry,
+					NULL, &ecm_sfe_ipv4_decel_cmd_avg_millis_fops)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv4 decel_cmd_avg_millis file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!ecm_sfe_ported_ipv4_debugfs_init(ecm_sfe_ipv4_dentry)) {
+		DEBUG_ERROR("Failed to create ecm ported files in debugfs\n");
+		goto task_cleanup;
+	}
+
+	/*
+	 * Register this module with SFE.
+	 * Notify manager should be registered before the netfilter hooks. Because there
+	 * is a possibility that the ECM can try to send acceleration messages to the
+	 * acceleration engine without having an acceleration engine manager.
+	 */
+	ecm_sfe_ipv4_mgr = sfe_ipv4_notify_register(ecm_sfe_ipv4_stats_sync_callback, NULL);
+
+	return 0;
+
+task_cleanup:
+
+	debugfs_remove_recursive(ecm_sfe_ipv4_dentry);
+	return result;
+}
+EXPORT_SYMBOL(ecm_sfe_ipv4_init);
+
+/*
+ * ecm_sfe_ipv4_exit()
+ */
+void ecm_sfe_ipv4_exit(void)
+{
+	if (!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_SFE)) {
+		DEBUG_INFO("SFE IPv4 is disabled\n");
+		return;
+	}
+
+	DEBUG_INFO("ECM SFE IPv4 Module exit\n");
+
+	/*
+	 * Unregister from the SFE
+	 */
+	sfe_ipv4_notify_unregister();
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_sfe_ipv4_dentry) {
+		debugfs_remove_recursive(ecm_sfe_ipv4_dentry);
+	}
+}
+EXPORT_SYMBOL(ecm_sfe_ipv4_exit);
diff --git a/qca-nss-ecm/frontends/sfe/ecm_sfe_ipv4.h b/qca-nss-ecm/frontends/sfe/ecm_sfe_ipv4.h
new file mode 100644
index 0000000..bb86cf4
--- /dev/null
+++ b/qca-nss-ecm/frontends/sfe/ecm_sfe_ipv4.h
@@ -0,0 +1,164 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2016, 2020-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <sfe_api.h>
+
+extern int ecm_sfe_ipv4_no_action_limit_default;		/* Default no-action limit. */
+extern int ecm_sfe_ipv4_driver_fail_limit_default;		/* Default driver fail limit. */
+extern int ecm_sfe_ipv4_nack_limit_default;			/* Default nack limit. */
+extern int ecm_sfe_ipv4_accelerated_count;			/* Total offloads */
+extern int ecm_sfe_ipv4_pending_accel_count;			/* Total pending offloads issued to the SFE / awaiting completion */
+extern int ecm_sfe_ipv4_pending_decel_count;			/* Total pending deceleration requests issued to the SFE / awaiting completion */
+
+/*
+ * Limiting the acceleration of connections.
+ *
+ * By default there is no acceleration limiting.
+ * This means that when ECM has more connections (that can be accelerated) than the acceleration
+ * engine will allow the ECM will continue to try to accelerate.
+ * In this scenario the acceleration engine will begin removal of existing rules to make way for new ones.
+ * When the accel_limit_mode is set to FIXED ECM will not permit more rules to be issued than the engine will allow.
+ */
+extern uint32_t ecm_sfe_ipv4_accel_limit_mode;
+
+/*
+ * Locking of the classifier - concurrency control for file global parameters.
+ * NOTE: It is safe to take this lock WHILE HOLDING a feci->lock.  The reverse is NOT SAFE.
+ */
+extern spinlock_t ecm_sfe_ipv4_lock;			/* Protect against SMP access between netfilter, events and private threaded function. */
+
+/*
+ * SFE linkage
+ */
+extern struct sfe_ctx_instance *ecm_sfe_ipv4_mgr;
+
+/*
+ * ecm_sfe_ipv4_accel_pending_set()
+ *	Set pending acceleration for the connection object.
+ *
+ * Return false if the acceleration is not permitted or is already in progress.
+ */
+static inline bool ecm_sfe_ipv4_accel_pending_set(struct ecm_front_end_connection_instance *feci)
+{
+	DEBUG_INFO("%px: Accel conn: %px\n", feci, feci->ci);
+
+	/*
+	 * If re-generation is required then we cannot permit acceleration
+	 */
+	if (ecm_db_connection_regeneration_required_peek(feci->ci)) {
+		DEBUG_TRACE("%px: accel %px failed - regen required\n", feci, feci->ci);
+		return false;
+	}
+
+	/*
+	 * Is connection acceleration permanently failed?
+	 */
+	spin_lock_bh(&feci->lock);
+	if (ECM_FRONT_END_ACCELERATION_FAILED(feci->accel_mode)) {
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: accel %px failed\n", feci, feci->ci);
+		return false;
+	}
+
+	/*
+	 * If acceleration mode is anything other than "not accelerated" then ignore.
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_DECEL) {
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: Ignoring wrong mode accel for conn: %px\n", feci, feci->ci);
+		return false;
+	}
+
+	/*
+	 * Do we have a fixed upper limit for acceleration?
+	 */
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	if (ecm_sfe_ipv4_accel_limit_mode & ECM_FRONT_END_ACCEL_LIMIT_MODE_FIXED) {
+		if ((ecm_sfe_ipv4_pending_accel_count + ecm_sfe_ipv4_accelerated_count) >= sfe_ipv4_max_conn_count()) {
+			spin_unlock_bh(&ecm_sfe_ipv4_lock);
+			spin_unlock_bh(&feci->lock);
+			DEBUG_INFO("%px: Accel limit reached, accel denied: %px\n", feci, feci->ci);
+			return false;
+		}
+	}
+
+	/*
+	 * Okay to accelerate
+	 */
+	ecm_sfe_ipv4_pending_accel_count++;
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+	/*
+	 * Okay connection can be set to pending acceleration
+	 */
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+	return true;
+}
+
+/*
+ * _ecm_sfe_ipv4_accel_pending_clear()
+ *	Clear pending acceleration for the connection object, setting it to the desired state.
+ *
+ * Returns true if "decelerate was pending".
+ *
+ * The feci->lock AND ecm_sfe_ipv4_lock must be held on entry.
+ */
+static inline bool _ecm_sfe_ipv4_accel_pending_clear(struct ecm_front_end_connection_instance *feci, ecm_front_end_acceleration_mode_t mode)
+{
+	bool decel_pending;
+
+	/*
+	 * Set the mode away from its accel pending state.
+	 */
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Accel mode unexpected: %d\n", feci, feci->accel_mode);
+	feci->accel_mode = mode;
+
+	/*
+	 * Clear decelerate pending flag.
+	 * This flag is only set when we are ACCEL_PENDING -
+	 * and we are moving from that to the given mode anyway.
+	 */
+	decel_pending = feci->stats.decelerate_pending;
+	feci->stats.decelerate_pending = false;
+
+	/*
+	 * Decrement pending counter
+	 */
+	ecm_sfe_ipv4_pending_accel_count--;
+	DEBUG_ASSERT(ecm_sfe_ipv4_pending_accel_count >= 0, "Accel pending underflow\n");
+	return decel_pending;
+}
+
+/*
+ * ecm_sfe_ipv4_accel_pending_clear()
+ *	Clear pending acceleration for the connection object, setting it to the desired state.
+ */
+static inline bool ecm_sfe_ipv4_accel_pending_clear(struct ecm_front_end_connection_instance *feci, ecm_front_end_acceleration_mode_t mode)
+{
+	bool decel_pending;
+	spin_lock_bh(&feci->lock);
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	decel_pending = _ecm_sfe_ipv4_accel_pending_clear(feci, mode);
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+	spin_unlock_bh(&feci->lock);
+	return decel_pending;
+}
+
+extern void ecm_sfe_ipv4_accel_done_time_update(struct ecm_front_end_connection_instance *feci);
+extern void ecm_sfe_ipv4_decel_done_time_update(struct ecm_front_end_connection_instance *feci);
+extern int ecm_sfe_ipv4_init(struct dentry *dentry);
+extern void ecm_sfe_ipv4_exit(void);
diff --git a/qca-nss-ecm/frontends/sfe/ecm_sfe_ipv6.c b/qca-nss-ecm/frontends/sfe/ecm_sfe_ipv6.c
new file mode 100644
index 0000000..f41ef77
--- /dev/null
+++ b/qca-nss-ecm/frontends/sfe/ecm_sfe_ipv6.c
@@ -0,0 +1,803 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/debugfs.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/ip6_route.h>
+#include <net/ip6_fib.h>
+#include <net/addrconf.h>
+#include <net/ipv6.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in6.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/ppp_defs.h>
+#include <linux/mroute6.h>
+#include <linux/vmalloc.h>
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv6.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <linux/netfilter/nf_conntrack_zones_common.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/nf_conntrack_timeout.h>
+#include <net/netfilter/ipv6/nf_conntrack_ipv6.h>
+#include <net/netfilter/ipv6/nf_defrag_ipv6.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_SFE_IPV6_DEBUG_LEVEL
+
+#include <sfe_api.h>
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#ifdef ECM_CLASSIFIER_NL_ENABLE
+#include "ecm_classifier_nl.h"
+#endif
+#include "ecm_interface.h"
+#include "ecm_sfe_common.h"
+#include "ecm_sfe_ported_ipv6.h"
+#include "ecm_front_end_common.h"
+#include "ecm_front_end_ipv6.h"
+
+int ecm_sfe_ipv6_no_action_limit_default = 250;		/* Default no-action limit. */
+int ecm_sfe_ipv6_driver_fail_limit_default = 250;		/* Default driver fail limit. */
+int ecm_sfe_ipv6_nack_limit_default = 250;			/* Default nack limit. */
+int ecm_sfe_ipv6_accelerated_count = 0;			/* Total offloads */
+int ecm_sfe_ipv6_pending_accel_count = 0;			/* Total pending offloads issued to the SFE / awaiting completion */
+int ecm_sfe_ipv6_pending_decel_count = 0;			/* Total pending deceleration requests issued to the SFE / awaiting completion */
+
+/*
+ * Limiting the acceleration of connections.
+ *
+ * By default there is no acceleration limiting.
+ * This means that when ECM has more connections (that can be accelerated) than the acceleration
+ * engine will allow the ECM will continue to try to accelerate.
+ * In this scenario the acceleration engine will begin removal of existing rules to make way for new ones.
+ * When the accel_limit_mode is set to FIXED ECM will not permit more rules to be issued than the engine will allow.
+ */
+uint32_t ecm_sfe_ipv6_accel_limit_mode = ECM_FRONT_END_ACCEL_LIMIT_MODE_UNLIMITED;
+
+/*
+ * Locking of the classifier - concurrency control for file global parameters.
+ * NOTE: It is safe to take this lock WHILE HOLDING a feci->lock.  The reverse is NOT SAFE.
+ */
+DEFINE_SPINLOCK(ecm_sfe_ipv6_lock);			/* Protect against SMP access between netfilter, events and private threaded function. */
+
+/*
+ * SFE driver linkage
+ */
+struct sfe_ctx_instance *ecm_sfe_ipv6_mgr = NULL;
+
+static unsigned long ecm_sfe_ipv6_accel_cmd_time_avg_samples = 0;	/* Sum of time taken for the set of accel command samples, used to compute average time for an accel command to complete */
+static unsigned long ecm_sfe_ipv6_accel_cmd_time_avg_set = 1;	/* How many samples in the set */
+static unsigned long ecm_sfe_ipv6_decel_cmd_time_avg_samples = 0;	/* Sum of time taken for the set of accel command samples, used to compute average time for an accel command to complete */
+static unsigned long ecm_sfe_ipv6_decel_cmd_time_avg_set = 1;	/* How many samples in the set */
+
+#ifdef CONFIG_XFRM
+static int ecm_sfe_ipv6_reject_acceleration_for_ipsec;		/* Don't accelerate IPSEC traffic */
+#endif
+
+/*
+ * Debugfs dentry object.
+ */
+static struct dentry *ecm_sfe_ipv6_dentry;
+
+/*
+ * ecm_sfe_ipv6_accel_done_time_update()
+ *	Record how long the command took to complete, updating average samples
+ */
+void ecm_sfe_ipv6_accel_done_time_update(struct ecm_front_end_connection_instance *feci)
+{
+	unsigned long delta;
+
+	/*
+	 * How long did it take the command to complete?
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_completed = jiffies;
+	delta = feci->stats.cmd_time_completed - feci->stats.cmd_time_begun;
+	spin_unlock_bh(&feci->lock);
+
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	ecm_sfe_ipv6_accel_cmd_time_avg_samples += delta;
+	ecm_sfe_ipv6_accel_cmd_time_avg_set++;
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+}
+
+/*
+ * ecm_sfe_ipv6_deccel_done_time_update()
+ *	Record how long the command took to complete, updating average samples
+ */
+void ecm_sfe_ipv6_decel_done_time_update(struct ecm_front_end_connection_instance *feci)
+{
+	unsigned long delta;
+
+	/*
+	 * How long did it take the command to complete?
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_completed = jiffies;
+	delta = feci->stats.cmd_time_completed - feci->stats.cmd_time_begun;
+	spin_unlock_bh(&feci->lock);
+
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	ecm_sfe_ipv6_decel_cmd_time_avg_samples += delta;
+	ecm_sfe_ipv6_decel_cmd_time_avg_set++;
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+}
+
+/*
+ * ecm_sfe_ipv6_stats_sync_callback()
+ *	Callback handler from the SFE.
+ */
+static void ecm_sfe_ipv6_stats_sync_callback(void *app_data, struct sfe_ipv6_msg *nim)
+{
+	struct sfe_ipv6_conn_sync *sync;
+	struct nf_conntrack_tuple_hash *h;
+	struct nf_conntrack_tuple tuple;
+	struct nf_conn *ct;
+	struct nf_conn_counter *acct;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct neighbour *neigh;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	ip_addr_t flow_ip;
+	ip_addr_t return_ip;
+	struct in6_addr group6 __attribute__((unused));
+	struct in6_addr origin6 __attribute__((unused));
+	struct ecm_classifier_rule_sync class_sync;
+	int flow_dir;
+	int return_dir;
+
+	/*
+	 * Only respond to sync messages
+	 */
+	if (nim->cm.type != SFE_RX_CONN_STATS_SYNC_MSG) {
+		DEBUG_TRACE("Ignoring nim: %px - not sync: %d", nim, nim->cm.type);
+		return;
+	}
+	sync = &nim->msg.conn_stats;
+
+	ECM_SFE_IPV6_ADDR_TO_IP_ADDR(flow_ip, sync->flow_ip);
+	ECM_SFE_IPV6_ADDR_TO_IP_ADDR(return_ip, sync->return_ip);
+
+	/*
+	 * Look up ecm connection with a view to synchronising the connection, classifier and data tracker.
+	 * Note that we use _xlate versions for destination - for egressing connections this would be the wan IP address,
+	 * but for ingressing this would be the LAN side (non-nat'ed) address and is what we need for lookup of our connection.
+	 */
+	DEBUG_INFO("%px: SFE Sync, lookup connection using\n" \
+			"Protocol: %d\n" \
+			"src_addr: " ECM_IP_ADDR_OCTAL_FMT ":%d\n" \
+			"dest_addr: " ECM_IP_ADDR_OCTAL_FMT ":%d\n",
+			sync,
+			(int)sync->protocol,
+			ECM_IP_ADDR_TO_OCTAL(flow_ip), (int)sync->flow_ident,
+			ECM_IP_ADDR_TO_OCTAL(return_ip), (int)sync->return_ident);
+
+	ci = ecm_db_connection_find_and_ref(flow_ip, return_ip, sync->protocol, (int)ntohs(sync->flow_ident), (int)ntohs(sync->return_ident));
+	if (!ci) {
+		DEBUG_TRACE("%px: SFE Sync: no connection\n", sync);
+		goto sync_conntrack;
+	}
+	DEBUG_TRACE("%px: Sync conn %px\n", sync, ci);
+
+	/*
+	 * Copy the sync data to the classifier sync structure to
+	 * update the classifiers' stats.
+	 */
+	class_sync.tx_packet_count[ECM_CONN_DIR_FLOW] = sync->flow_tx_packet_count;
+	class_sync.tx_byte_count[ECM_CONN_DIR_FLOW] = sync->flow_tx_byte_count;
+	class_sync.rx_packet_count[ECM_CONN_DIR_FLOW] = sync->flow_rx_packet_count;
+	class_sync.rx_byte_count[ECM_CONN_DIR_FLOW] = sync->flow_rx_byte_count;
+	class_sync.tx_packet_count[ECM_CONN_DIR_RETURN] = sync->return_tx_packet_count;
+	class_sync.tx_byte_count[ECM_CONN_DIR_RETURN] = sync->return_tx_byte_count;
+	class_sync.rx_packet_count[ECM_CONN_DIR_RETURN] = sync->return_rx_packet_count;
+	class_sync.rx_byte_count[ECM_CONN_DIR_RETURN] = sync->return_rx_byte_count;
+	class_sync.reason = sync->reason;
+
+	/*
+	 * Sync assigned classifiers
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: sync to: %px, type: %d\n", ci, aci, aci->type_get(aci));
+		aci->sync_to_v6(aci, &class_sync);
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Keep connection alive and updated
+	 */
+	if (!ecm_db_connection_defunct_timer_touch(ci)) {
+		ecm_db_connection_deref(ci);
+		goto sync_conntrack;
+	}
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+
+	if (sync->flow_tx_packet_count || sync->return_tx_packet_count) {
+		DEBUG_TRACE("%px: flow_rx_packet_count: %u, flow_rx_byte_count: %u, return_rx_packet_count: %u, , return_rx_byte_count: %u\n",
+				ci, sync->flow_rx_packet_count, sync->flow_rx_byte_count, sync->return_rx_packet_count, sync->return_rx_byte_count);
+		DEBUG_TRACE("%px: flow_tx_packet_count: %u, flow_tx_byte_count: %u, return_tx_packet_count: %u, return_tx_byte_count: %u\n",
+				ci, sync->flow_tx_packet_count, sync->flow_tx_byte_count, sync->return_tx_packet_count, sync->return_tx_byte_count);
+		/*
+		 * The amount of data *sent* by the ECM connection 'from' side is the amount the SFE has *received* in the 'flow' direction.
+		 */
+		ecm_db_connection_data_totals_update(ci, true, sync->flow_rx_byte_count, sync->flow_rx_packet_count);
+
+		/*
+		 * The amount of data *sent* by the ECM connection 'to' side is the amount the SFE has *received* in the 'return' direction.
+		 */
+		ecm_db_connection_data_totals_update(ci, false, sync->return_rx_byte_count, sync->return_rx_packet_count);
+
+		/*
+		 * As packets have been accelerated we have seen some action.
+		 */
+		feci->action_seen(feci);
+
+		/*
+		 * Update interface stats.
+		 * This will update interface enabled for SFE frontend
+		 */
+		ecm_interface_stats_update(ci, sync->flow_tx_packet_count, sync->flow_tx_byte_count, sync->flow_rx_packet_count,
+				sync->flow_rx_byte_count, sync->return_tx_packet_count, sync->return_tx_byte_count, sync->return_rx_packet_count, sync->return_rx_byte_count);
+	}
+
+	switch(sync->reason) {
+	case SFE_RULE_SYNC_REASON_DESTROY:
+		/*
+		 * This is the final sync from the SFE for a connection whose acceleration was
+		 * terminated by the ecm.
+		 * NOTE: We take no action here since that is performed by the destroy message ack.
+		 */
+		DEBUG_INFO("%px: ECM initiated final sync seen: %d\n", ci, sync->reason);
+
+		/*
+		 * If there is no tx/rx packets to update the other linux subsystems, we shouldn't continue
+		 * for the sync message which comes as a final sync for the ECM initiated destroy request.
+		 * Because this means the connection is not active for sometime and adding this delta time
+		 * to the conntrack timeout will update it eventhough there is no traffic for this connection.
+		 */
+		if (!sync->flow_tx_packet_count && !sync->return_tx_packet_count) {
+			feci->deref(feci);
+			ecm_db_connection_deref(ci);
+			return;
+		}
+		break;
+	case SFE_RULE_SYNC_REASON_FLUSH:
+	case SFE_RULE_SYNC_REASON_EVICT:
+		/*
+		 * SFE has ended acceleration without instruction from the ECM.
+		 */
+		DEBUG_INFO("%px: SFE Initiated final sync seen: %d\n", ci, sync->reason);
+
+		/*
+		 * SFE Decelerated the connection
+		 */
+		feci->accel_ceased(feci);
+		break;
+	default:
+		if (ecm_db_connection_is_routed_get(ci)) {
+			/*
+			 * Update the neighbour entry for source IP address
+			 */
+			neigh = ecm_interface_ipv6_neigh_get(flow_ip);
+			if (!neigh) {
+				DEBUG_WARN("Neighbour entry for " ECM_IP_ADDR_OCTAL_FMT " not found\n", ECM_IP_ADDR_TO_OCTAL(flow_ip));
+			} else {
+				if (sync->flow_tx_packet_count) {
+					DEBUG_TRACE("Neighbour entry event send for " ECM_IP_ADDR_OCTAL_FMT ": %px\n", ECM_IP_ADDR_TO_OCTAL(flow_ip), neigh);
+					neigh_event_send(neigh, NULL);
+				}
+
+				neigh_release(neigh);
+			}
+
+			/*
+			 * Update the neighbour entry for destination IP address
+			 */
+			neigh = ecm_interface_ipv6_neigh_get(return_ip);
+			if (!neigh) {
+				DEBUG_WARN("Neighbour entry for " ECM_IP_ADDR_OCTAL_FMT " not found\n", ECM_IP_ADDR_TO_OCTAL(return_ip));
+			} else {
+				if (sync->return_tx_packet_count) {
+					DEBUG_TRACE("Neighbour entry event send for " ECM_IP_ADDR_OCTAL_FMT ": %px\n", ECM_IP_ADDR_TO_OCTAL(return_ip), neigh);
+					neigh_event_send(neigh, NULL);
+				}
+
+				neigh_release(neigh);
+			}
+		}
+	}
+
+	/*
+	 * If connection should be re-generated then we need to force a deceleration
+	 */
+	if (unlikely(ecm_db_connection_regeneration_required_peek(ci))) {
+		DEBUG_TRACE("%px: Connection generation changing, terminating acceleration", ci);
+		feci->decelerate(feci);
+	}
+
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+
+sync_conntrack:
+	;
+
+	/*
+	 * Create a tuple so as to be able to look up a conntrack connection
+	 */
+	memset(&tuple, 0, sizeof(tuple));
+	ECM_IP_ADDR_TO_NIN6_ADDR(tuple.src.u3.in6, flow_ip);
+	tuple.src.u.all = sync->flow_ident;
+	tuple.src.l3num = AF_INET6;
+
+	ECM_IP_ADDR_TO_NIN6_ADDR(tuple.dst.u3.in6, return_ip);
+	tuple.dst.dir = IP_CT_DIR_ORIGINAL;
+	tuple.dst.protonum = (uint8_t)sync->protocol;
+	tuple.dst.u.all = sync->return_ident;
+
+	DEBUG_TRACE("Conntrack sync, lookup conntrack connection using\n"
+			"Protocol: %d\n"
+			"src_addr: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"dest_addr: " ECM_IP_ADDR_OCTAL_FMT ":%d\n",
+			(int)tuple.dst.protonum,
+			ECM_IP_ADDR_TO_OCTAL(flow_ip), (int)ntohs(tuple.src.u.all),
+			ECM_IP_ADDR_TO_OCTAL(return_ip), (int)ntohs(tuple.dst.u.all));
+
+	/*
+	 * Look up conntrack connection
+	 */
+	h = nf_conntrack_find_get(&init_net, &nf_ct_zone_dflt, &tuple);
+	if (!h) {
+		DEBUG_WARN("%px: SFE Sync: no conntrack connection\n", sync);
+		return;
+	}
+
+	ct = nf_ct_tuplehash_to_ctrack(h);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0))
+	NF_CT_ASSERT(ct->timeout.data == (unsigned long)ct);
+#endif
+	DEBUG_TRACE("%px: SFE Sync: conntrack connection\n", ct);
+
+	ecm_front_end_flow_and_return_directions_get(ct, flow_ip, 6, &flow_dir, &return_dir);
+
+	/*
+	 * Only update if this is not a fixed timeout
+	 */
+	if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) {
+		unsigned long int delta_jiffies;
+
+		/*
+		 * Convert ms ticks from the SFE to jiffies. We know that inc_ticks is small
+		 * and we expect HZ to be small too so we can multiply without worrying about
+		 * wrap-around problems.  We add a rounding constant to ensure that the different
+		 * time bases don't cause truncation errors.
+		 */
+		delta_jiffies = ((sync->inc_ticks * HZ) + (MSEC_PER_SEC / 2)) / MSEC_PER_SEC;
+
+		spin_lock_bh(&ct->lock);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0))
+		ct->timeout.expires += delta_jiffies;
+#else
+		ct->timeout += delta_jiffies;
+#endif
+		spin_unlock_bh(&ct->lock);
+	}
+	acct = nf_conn_acct_find(ct)->counter;
+	if (acct) {
+		spin_lock_bh(&ct->lock);
+		atomic64_add(sync->flow_rx_packet_count, &acct[flow_dir].packets);
+		atomic64_add(sync->flow_rx_byte_count, &acct[flow_dir].bytes);
+
+		atomic64_add(sync->return_rx_packet_count, &acct[return_dir].packets);
+		atomic64_add(sync->return_rx_byte_count, &acct[return_dir].bytes);
+		spin_unlock_bh(&ct->lock);
+	}
+
+	switch (sync->protocol) {
+	case IPPROTO_TCP:
+		spin_lock_bh(&ct->lock);
+		if (ct->proto.tcp.seen[flow_dir].td_maxwin < sync->flow_max_window) {
+			ct->proto.tcp.seen[flow_dir].td_maxwin = sync->flow_max_window;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[flow_dir].td_end - sync->flow_end) < 0) {
+			ct->proto.tcp.seen[flow_dir].td_end = sync->flow_end;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[flow_dir].td_maxend - sync->flow_max_end) < 0) {
+			ct->proto.tcp.seen[flow_dir].td_maxend = sync->flow_max_end;
+		}
+		if (ct->proto.tcp.seen[return_dir].td_maxwin < sync->return_max_window) {
+			ct->proto.tcp.seen[return_dir].td_maxwin = sync->return_max_window;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[return_dir].td_end - sync->return_end) < 0) {
+			ct->proto.tcp.seen[return_dir].td_end = sync->return_end;
+		}
+		if ((int32_t)(ct->proto.tcp.seen[return_dir].td_maxend - sync->return_max_end) < 0) {
+			ct->proto.tcp.seen[return_dir].td_maxend = sync->return_max_end;
+		}
+		spin_unlock_bh(&ct->lock);
+		break;
+	case IPPROTO_UDP:
+		/*
+		 * In Linux connection track, UDP flow has two timeout values:
+		 * /proc/sys/net/netfilter/nf_conntrack_udp_timeout:
+		 * 	this is for uni-direction UDP flow, normally its value is 60 seconds
+		 * /proc/sys/net/netfilter/nf_conntrack_udp_timeout_stream:
+		 * 	this is for bi-direction UDP flow, normally its value is 180 seconds
+		 *
+		 * Linux will update timer of UDP flow to stream timeout once it seen packets
+		 * in reply direction. But if flow is accelerated by NSS or SFE, Linux won't
+		 * see any packets. So we have to do the same thing in our stats sync message.
+		 */
+		if (!test_bit(IPS_ASSURED_BIT, &ct->status) && acct) {
+			u_int64_t reply_pkts = atomic64_read(&acct[IP_CT_DIR_REPLY].packets);
+
+			if (reply_pkts != 0) {
+				struct nf_conntrack_l4proto *l4proto __maybe_unused;
+				unsigned int *timeouts;
+
+				set_bit(IPS_SEEN_REPLY_BIT, &ct->status);
+				set_bit(IPS_ASSURED_BIT, &ct->status);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0))
+				l4proto = __nf_ct_l4proto_find(AF_INET6, IPPROTO_UDP);
+				timeouts = nf_ct_timeout_lookup(&init_net, ct, l4proto);
+
+				spin_lock_bh(&ct->lock);
+				ct->timeout.expires = jiffies + timeouts[UDP_CT_REPLIED];
+				spin_unlock_bh(&ct->lock);
+#else
+				timeouts = nf_ct_timeout_lookup(ct);
+				if (!timeouts) {
+					timeouts = udp_get_timeouts(nf_ct_net(ct));
+				}
+
+				spin_lock_bh(&ct->lock);
+				ct->timeout = jiffies + timeouts[UDP_CT_REPLIED];
+				spin_unlock_bh(&ct->lock);
+#endif
+			}
+		}
+		break;
+	}
+
+	/*
+	 * Release connection
+	 */
+	nf_ct_put(ct);
+}
+
+/*
+ * ecm_sfe_ipv6_get_accel_limit_mode()
+ */
+static int ecm_sfe_ipv6_get_accel_limit_mode(void *data, u64 *val)
+{
+	*val = ecm_sfe_ipv6_accel_limit_mode;
+
+	return 0;
+}
+
+/*
+ * ecm_sfe_ipv6_set_accel_limit_mode()
+ */
+static int ecm_sfe_ipv6_set_accel_limit_mode(void *data, u64 val)
+{
+	DEBUG_TRACE("ecm_sfe_ipv6_accel_limit_mode = %x\n", (int)val);
+
+	/*
+	 * Check that only valid bits are set.
+	 * It's fine for no bits to be set as that suggests no modes are wanted.
+	 */
+	if (val && (val ^ (ECM_FRONT_END_ACCEL_LIMIT_MODE_FIXED | ECM_FRONT_END_ACCEL_LIMIT_MODE_UNLIMITED))) {
+		DEBUG_WARN("ecm_sfe_ipv6_accel_limit_mode = %x bad\n", (int)val);
+		return -EINVAL;
+	}
+
+	ecm_sfe_ipv6_accel_limit_mode = (int)val;
+
+	return 0;
+}
+
+/*
+ * Debugfs attribute for accel limit mode.
+ */
+DEFINE_SIMPLE_ATTRIBUTE(ecm_sfe_ipv6_accel_limit_mode_fops, ecm_sfe_ipv6_get_accel_limit_mode, ecm_sfe_ipv6_set_accel_limit_mode, "%llu\n");
+
+/*
+ * ecm_sfe_ipv6_get_accel_cmd_average_millis()
+ */
+static ssize_t ecm_sfe_ipv6_get_accel_cmd_avg_millis(struct file *file,
+								char __user *user_buf,
+								size_t sz, loff_t *ppos)
+{
+	unsigned long set;
+	unsigned long samples;
+	unsigned long avg;
+	char *buf;
+	int ret;
+
+	buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!buf) {
+		return -ENOMEM;
+	}
+
+	/*
+	 * Operate under our locks.
+	 * Compute the average of the samples taken and seed the next set of samples with the result of this one.
+	 */
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	samples = ecm_sfe_ipv6_accel_cmd_time_avg_samples;
+	set = ecm_sfe_ipv6_accel_cmd_time_avg_set;
+	ecm_sfe_ipv6_accel_cmd_time_avg_samples /= ecm_sfe_ipv6_accel_cmd_time_avg_set;
+	ecm_sfe_ipv6_accel_cmd_time_avg_set = 1;
+	avg = ecm_sfe_ipv6_accel_cmd_time_avg_samples;
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+	/*
+	 * Convert average jiffies to milliseconds
+	 */
+	avg *= 1000;
+	avg /= HZ;
+
+	ret = snprintf(buf, (ssize_t)PAGE_SIZE, "avg=%lu\tsamples=%lu\tset_size=%lu\n", avg, samples, set);
+	if (ret < 0) {
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	ret = simple_read_from_buffer(user_buf, sz, ppos, buf, ret);
+	kfree(buf);
+	return ret;
+}
+
+/*
+ * File operations for accel command average time.
+ */
+static struct file_operations ecm_sfe_ipv6_accel_cmd_avg_millis_fops = {
+	.read = ecm_sfe_ipv6_get_accel_cmd_avg_millis,
+};
+
+/*
+ * ecm_sfe_ipv6_get_decel_cmd_average_millis()
+ */
+static ssize_t ecm_sfe_ipv6_get_decel_cmd_avg_millis(struct file *file,
+								char __user *user_buf,
+								size_t sz, loff_t *ppos)
+{
+	unsigned long set;
+	unsigned long samples;
+	unsigned long avg;
+	char *buf;
+	int ret;
+
+	buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!buf) {
+		return -ENOMEM;
+	}
+
+	/*
+	 * Operate under our locks.
+	 * Compute the average of the samples taken and seed the next set of samples with the result of this one.
+	 */
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	samples = ecm_sfe_ipv6_decel_cmd_time_avg_samples;
+	set = ecm_sfe_ipv6_decel_cmd_time_avg_set;
+	ecm_sfe_ipv6_decel_cmd_time_avg_samples /= ecm_sfe_ipv6_decel_cmd_time_avg_set;
+	ecm_sfe_ipv6_decel_cmd_time_avg_set = 1;
+	avg = ecm_sfe_ipv6_decel_cmd_time_avg_samples;
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+	/*
+	 * Convert average jiffies to milliseconds
+	 */
+	avg *= 1000;
+	avg /= HZ;
+
+	ret = snprintf(buf, (ssize_t)PAGE_SIZE, "avg=%lu\tsamples=%lu\tset_size=%lu\n", avg, samples, set);
+	if (ret < 0) {
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	ret = simple_read_from_buffer(user_buf, sz, ppos, buf, ret);
+	kfree(buf);
+	return ret;
+}
+
+/*
+ * File operations for decel command average time.
+ */
+static struct file_operations ecm_sfe_ipv6_decel_cmd_avg_millis_fops = {
+	.read = ecm_sfe_ipv6_get_decel_cmd_avg_millis,
+};
+
+/*
+ * ecm_sfe_ipv6_init()
+ */
+int ecm_sfe_ipv6_init(struct dentry *dentry)
+{
+	int result = -1;
+
+	if (!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_SFE)) {
+		DEBUG_INFO("SFE IPv6 is disabled\n");
+		return 0;
+	}
+
+	DEBUG_INFO("ECM SFE IPv6 init\n");
+
+	ecm_sfe_ipv6_dentry = debugfs_create_dir("ecm_sfe_ipv6", dentry);
+	if (!ecm_sfe_ipv6_dentry) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv6 directory in debugfs\n");
+		return result;
+	}
+
+#ifdef CONFIG_XFRM
+	if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry,
+					(u32 *)&ecm_sfe_ipv6_reject_acceleration_for_ipsec)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv6 reject_acceleration_for_ipsec file in debugfs\n");
+		goto task_cleanup;
+	}
+#endif
+
+	if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry,
+					(u32 *)&ecm_sfe_ipv6_no_action_limit_default)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv6 no_action_limit_default file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry,
+					(u32 *)&ecm_sfe_ipv6_driver_fail_limit_default)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv6 driver_fail_limit_default file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry,
+					(u32 *)&ecm_sfe_ipv6_nack_limit_default)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv6 nack_limit_default file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv6_dentry,
+					(u32 *)&ecm_sfe_ipv6_accelerated_count)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv6 accelerated_count file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv6_dentry,
+					(u32 *)&ecm_sfe_ipv6_pending_accel_count)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_accel_count file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv6_dentry,
+					(u32 *)&ecm_sfe_ipv6_pending_decel_count)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_decel_count file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry,
+					NULL, &ecm_sfe_ipv6_accel_limit_mode_fops)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv6 accel_limit_mode file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_file("accel_cmd_avg_millis", S_IRUGO, ecm_sfe_ipv6_dentry,
+					NULL, &ecm_sfe_ipv6_accel_cmd_avg_millis_fops)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv6 accel_cmd_avg_millis file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!debugfs_create_file("decel_cmd_avg_millis", S_IRUGO, ecm_sfe_ipv6_dentry,
+					NULL, &ecm_sfe_ipv6_decel_cmd_avg_millis_fops)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv6 decel_cmd_avg_millis file in debugfs\n");
+		goto task_cleanup;
+	}
+
+	if (!ecm_sfe_ported_ipv6_debugfs_init(ecm_sfe_ipv6_dentry)) {
+		DEBUG_ERROR("Failed to create ecm ported files in debugfs\n");
+		goto task_cleanup;
+	}
+
+	/*
+	 * Register this module with the Linux SFE Network driver.
+	 * Notify manager should be registered before the netfilter hooks. Because there
+	 * is a possibility that the ECM can try to send acceleration messages to the
+	 * acceleration engine without having an acceleration engine manager.
+	 */
+	ecm_sfe_ipv6_mgr = sfe_ipv6_notify_register(ecm_sfe_ipv6_stats_sync_callback, NULL);
+
+	return 0;
+
+task_cleanup:
+
+	debugfs_remove_recursive(ecm_sfe_ipv6_dentry);
+	return result;
+}
+EXPORT_SYMBOL(ecm_sfe_ipv6_init);
+
+/*
+ * ecm_sfe_ipv6_exit()
+ */
+void ecm_sfe_ipv6_exit(void)
+{
+	if (!ecm_front_end_is_feature_supported(ECM_FE_FEATURE_SFE)) {
+		DEBUG_INFO("SFE IPv6 is disabled\n");
+		return;
+	}
+
+	DEBUG_INFO("ECM SFE IPv6 Module exit\n");
+
+	/*
+	 * Unregister from the Linux SFE Network driver
+	 */
+	sfe_ipv6_notify_unregister();
+
+	/*
+	 * Remove the debugfs files recursively.
+	 */
+	if (ecm_sfe_ipv6_dentry) {
+		debugfs_remove_recursive(ecm_sfe_ipv6_dentry);
+	}
+}
+EXPORT_SYMBOL(ecm_sfe_ipv6_exit);
diff --git a/qca-nss-ecm/frontends/sfe/ecm_sfe_ipv6.h b/qca-nss-ecm/frontends/sfe/ecm_sfe_ipv6.h
new file mode 100644
index 0000000..587e3f5
--- /dev/null
+++ b/qca-nss-ecm/frontends/sfe/ecm_sfe_ipv6.h
@@ -0,0 +1,164 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2016, 2020-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <sfe_api.h>
+
+extern int ecm_sfe_ipv6_no_action_limit_default;		/* Default no-action limit. */
+extern int ecm_sfe_ipv6_driver_fail_limit_default;		/* Default driver fail limit. */
+extern int ecm_sfe_ipv6_nack_limit_default;			/* Default nack limit. */
+extern int ecm_sfe_ipv6_accelerated_count;			/* Total offloads */
+extern int ecm_sfe_ipv6_pending_accel_count;			/* Total pending offloads issued to the SFE / awaiting completion */
+extern int ecm_sfe_ipv6_pending_decel_count;			/* Total pending deceleration requests issued to the SFE / awaiting completion */
+
+/*
+ * Limiting the acceleration of connections.
+ *
+ * By default there is no acceleration limiting.
+ * This means that when ECM has more connections (that can be accelerated) than the acceleration
+ * engine will allow the ECM will continue to try to accelerate.
+ * In this scenario the acceleration engine will begin removal of existing rules to make way for new ones.
+ * When the accel_limit_mode is set to FIXED ECM will not permit more rules to be issued than the engine will allow.
+ */
+extern uint32_t ecm_sfe_ipv6_accel_limit_mode;
+
+/*
+ * Locking of the classifier - concurrency control for file global parameters.
+ * NOTE: It is safe to take this lock WHILE HOLDING a feci->lock.  The reverse is NOT SAFE.
+ */
+extern spinlock_t ecm_sfe_ipv6_lock;			/* Protect against SMP access between netfilter, events and private threaded function. */
+
+/*
+ * SFE driver linkage
+ */
+extern struct sfe_ctx_instance *ecm_sfe_ipv6_mgr;
+
+/*
+ * ecm_sfe_ipv6_accel_pending_set()
+ *	Set pending acceleration for the connection object.
+ *
+ * Return false if the acceleration is not permitted or is already in progress.
+ */
+static inline bool ecm_sfe_ipv6_accel_pending_set(struct ecm_front_end_connection_instance *feci)
+{
+	DEBUG_INFO("%px: Accel conn: %px\n", feci, feci->ci);
+
+	/*
+	 * If re-generation is required then we cannot permit acceleration
+	 */
+	if (ecm_db_connection_regeneration_required_peek(feci->ci)) {
+		DEBUG_TRACE("%px: accel %px failed - regen required\n", feci, feci->ci);
+		return false;
+	}
+
+	/*
+	 * Is connection acceleration permanently failed?
+	 */
+	spin_lock_bh(&feci->lock);
+	if (ECM_FRONT_END_ACCELERATION_FAILED(feci->accel_mode)) {
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: accel %px failed\n", feci, feci->ci);
+		return false;
+	}
+
+	/*
+	 * If acceleration mode is anything other than "not accelerated" then ignore.
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_DECEL) {
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: Ignoring wrong mode accel for conn: %px\n", feci, feci->ci);
+		return false;
+	}
+
+	/*
+	 * Do we have a fixed upper limit for acceleration?
+	 */
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	if (ecm_sfe_ipv6_accel_limit_mode & ECM_FRONT_END_ACCEL_LIMIT_MODE_FIXED) {
+		if ((ecm_sfe_ipv6_pending_accel_count + ecm_sfe_ipv6_accelerated_count) >= sfe_ipv6_max_conn_count()) {
+			spin_unlock_bh(&ecm_sfe_ipv6_lock);
+			spin_unlock_bh(&feci->lock);
+			DEBUG_INFO("%px: Accel limit reached, accel denied: %px\n", feci, feci->ci);
+			return false;
+		}
+	}
+
+	/*
+	 * Okay to accelerate
+	 */
+	ecm_sfe_ipv6_pending_accel_count++;
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+	/*
+	 * Okay connection can be set to pending acceleration
+	 */
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+	return true;
+}
+
+/*
+ * _ecm_sfe_ipv6_accel_pending_clear()
+ *	Clear pending acceleration for the connection object, setting it to the desired state.
+ *
+ * Returns true if "decelerate was pending".
+ *
+ * The feci->lock AND ecm_sfe_ipv6_lock must be held on entry.
+ */
+static inline bool _ecm_sfe_ipv6_accel_pending_clear(struct ecm_front_end_connection_instance *feci, ecm_front_end_acceleration_mode_t mode)
+{
+	bool decel_pending;
+
+	/*
+	 * Set the mode away from its accel pending state.
+	 */
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Accel mode unexpected: %d\n", feci, feci->accel_mode);
+	feci->accel_mode = mode;
+
+	/*
+	 * Clear decelerate pending flag.
+	 * This flag is only set when we are ACCEL_PENDING -
+	 * and we are moving from that to the given mode anyway.
+	 */
+	decel_pending = feci->stats.decelerate_pending;
+	feci->stats.decelerate_pending = false;
+
+	/*
+	 * Decrement pending counter
+	 */
+	ecm_sfe_ipv6_pending_accel_count--;
+	DEBUG_ASSERT(ecm_sfe_ipv6_pending_accel_count >= 0, "Accel pending underflow\n");
+	return decel_pending;
+}
+
+/*
+ * ecm_sfe_ipv6_accel_pending_clear()
+ *	Clear pending acceleration for the connection object, setting it to the desired state.
+ */
+static inline bool ecm_sfe_ipv6_accel_pending_clear(struct ecm_front_end_connection_instance *feci, ecm_front_end_acceleration_mode_t mode)
+{
+	bool decel_pending;
+	spin_lock_bh(&feci->lock);
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	decel_pending = _ecm_sfe_ipv6_accel_pending_clear(feci, mode);
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+	spin_unlock_bh(&feci->lock);
+	return decel_pending;
+}
+
+extern void ecm_sfe_ipv6_accel_done_time_update(struct ecm_front_end_connection_instance *feci);
+extern void ecm_sfe_ipv6_decel_done_time_update(struct ecm_front_end_connection_instance *feci);
+extern int ecm_sfe_ipv6_init(struct dentry *dentry);
+extern void ecm_sfe_ipv6_exit(void);
diff --git a/qca-nss-ecm/frontends/sfe/ecm_sfe_non_ported_ipv4.c b/qca-nss-ecm/frontends/sfe/ecm_sfe_non_ported_ipv4.c
new file mode 100644
index 0000000..ab92a8a
--- /dev/null
+++ b/qca-nss-ecm/frontends/sfe/ecm_sfe_non_ported_ipv4.c
@@ -0,0 +1,1953 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/debugfs.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <net/addrconf.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_SFE_NON_PORTED_IPV4_DEBUG_LEVEL
+
+#include <sfe_api.h>
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#include "ecm_sfe_non_ported_ipv4.h"
+#include "ecm_sfe_ipv4.h"
+#include "ecm_sfe_common.h"
+#include "ecm_front_end_common.h"
+
+/*
+ * Magic number
+ */
+#define ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC 0xEC35
+
+/*
+ * struct ecm_sfe_non_ported_ipv4_connection_instance
+ *	A connection specific front end instance for Non-Ported connections
+ */
+struct ecm_sfe_non_ported_ipv4_connection_instance {
+	struct ecm_front_end_connection_instance base;		/* Base class */
+	struct ecm_sfe_common_fe_info fe_info;          	/* Front end information */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+static int ecm_sfe_non_ported_ipv4_accelerated_count = 0;		/* Number of Non-Ported connections currently offloaded */
+
+/*
+ * ecm_sfe_non_ported_ipv4_get_stats_bitmap()
+ *	Get bit map
+ */
+static uint32_t ecm_sfe_non_ported_ipv4_get_stats_bitmap(struct ecm_front_end_connection_instance *feci, ecm_db_obj_dir_t dir)
+{
+	struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	return ecm_sfe_common_get_stats_bitmap(&nnpci->fe_info, dir);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv4_set_stats_bitmap()
+ *	Set bit map
+ */
+static void ecm_sfe_non_ported_ipv4_set_stats_bitmap(struct ecm_front_end_connection_instance *feci, ecm_db_obj_dir_t dir, uint8_t bit)
+{
+	struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	ecm_sfe_common_set_stats_bitmap(&nnpci->fe_info, dir, bit);
+}
+
+#ifdef ECM_INTERFACE_SIT_ENABLE
+#ifdef CONFIG_IPV6_SIT_6RD
+/*
+ * ecm_sfe_non_ported_ipv4_sit_set_peer()
+ *	It will set the tunnel's peer when the tunnel is a remote any tunnel.
+ */
+void ecm_sfe_non_ported_ipv4_sit_set_peer(struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci, struct sk_buff *skb)
+{
+	struct sfe_tun6rd_msg tun6rdmsg;
+	struct sfe_tun6rd_set_peer_msg *tun6rdpeer;
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *from_sfe_iface;
+	int32_t from_ifaces_first;
+	const struct ipv6hdr *iph6;
+	uint16_t interface_number;
+	ecm_db_iface_type_t ii_type;
+	ip_addr_t addr;
+	sfe_tx_status_t sfe_tx_status;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(nnpci->base.ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in from_interfaces list!\n", nnpci);
+		return;
+	}
+
+	from_sfe_iface = from_ifaces[from_ifaces_first];
+	ii_type = ecm_db_iface_type_get(from_sfe_iface);
+
+	/*
+	 * We handle SIT tunnel only here
+	 */
+	if (ii_type != ECM_DB_IFACE_TYPE_SIT) {
+		DEBUG_WARN("%px: This interface is not the sit tunnel\n", nnpci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		return;
+	}
+
+	/*
+	 * We catch these packets in the tunnel which destination ip address is null
+	 */
+	if (!ecm_db_iface_sit_daddr_is_null(from_sfe_iface)) {
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		return;
+	}
+	ecm_db_connection_address_get(nnpci->base.ci, ECM_DB_OBJ_DIR_TO, addr);
+
+	interface_number = ecm_db_iface_ae_interface_identifier_get(from_sfe_iface);
+	sfe_tun6rd_msg_init(&tun6rdmsg, interface_number, SFE_TUN6RD_ADD_UPDATE_PEER,
+			sizeof(struct sfe_tun6rd_set_peer_msg), NULL, NULL);
+
+	tun6rdpeer = &tun6rdmsg.msg.peer;
+	ECM_IP_ADDR_TO_NIN4_ADDR(tun6rdpeer->dest, addr);
+	iph6 = (struct ipv6hdr *)skb_transport_header(skb);
+	memcpy(tun6rdpeer->ipv6_address,&iph6->daddr, sizeof(struct  in6_addr));
+
+	sfe_tx_status = sfe_tun6rd_tx(ecm_sfe_ipv4_mgr, &tun6rdmsg);
+	if (sfe_tx_status != SFE_TX_SUCCESS) {
+		/*
+		 * Nothing to do when faild to xmit the message.
+		 */
+		DEBUG_WARN("SIT Accelerate set rule failed\n");
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		return;
+	}
+	DEBUG_TRACE("%px: SIT[%d] set peer\n"
+		   "ipv4 destination address:%x\n"
+		   "ipv6 destination address::"ECM_IP_ADDR_OCTAL_FMT"\n",
+		nnpci, interface_number, tun6rdpeer->dest, ECM_IP_ADDR_TO_OCTAL(tun6rdpeer->ipv6_address));
+
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+}
+#endif
+
+#endif
+
+/*
+ * ecm_sfe_non_ported_ipv4_connection_callback()
+ *	Callback for handling create ack/nack calls.
+ */
+static void ecm_sfe_non_ported_ipv4_connection_callback(void *app_data, struct sfe_ipv4_msg *nim)
+{
+	struct sfe_ipv4_rule_create_msg *__attribute__((unused))nircm = &nim->msg.rule_create;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci;
+	ecm_front_end_acceleration_mode_t result_mode;
+	bool is_defunct = false;
+
+	/*
+	 * Is this a response to a create message?
+	 */
+	if (nim->cm.type != SFE_TX_CREATE_RULE_MSG) {
+		DEBUG_ERROR("%px: non_ported create callback with improper type: %d, serial: %u\n", nim, nim->cm.type, serial);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: create callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	nnpci = (struct ecm_sfe_non_ported_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_sfe_ipv4_accel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: accelerate response for connection: %px, serial: %u\n", nnpci, feci->ci, serial);
+	DEBUG_TRACE("%px: rule_flags: %x, valid_flags: %x\n", nnpci, nircm->rule_flags, nircm->valid_flags);
+	DEBUG_TRACE("%px: flow_ip: %pI4h:%d\n", nnpci, &nircm->tuple.flow_ip, nircm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: %pI4h:%d\n", nnpci, &nircm->tuple.return_ip, nircm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", nnpci, nircm->tuple.protocol);
+
+	/*
+	 * Handle the creation result code.
+	 */
+	DEBUG_TRACE("%px: response: %d\n", nnpci, nim->cm.response);
+	if (nim->cm.response != SFE_CMN_RESPONSE_ACK) {
+		/*
+		 * Creation command failed (specific reason ignored).
+		 */
+		DEBUG_TRACE("%px: accel nack: %d\n", nnpci, nim->cm.error);
+		spin_lock_bh(&feci->lock);
+		DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+		feci->stats.ae_nack++;
+		feci->stats.ae_nack_total++;
+		if (feci->stats.ae_nack >= feci->stats.ae_nack_limit) {
+			/*
+			 * Too many SFE rejections
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_ACCEL_ENGINE;
+		} else {
+			/*
+			 * Revert to decelerated
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+		}
+
+		/*
+		 * If connection is now defunct then set mode to ensure no further accel attempts occur
+		 */
+		if (feci->is_defunct) {
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT;
+		}
+
+		spin_lock_bh(&ecm_sfe_ipv4_lock);
+		_ecm_sfe_ipv4_accel_pending_clear(feci, result_mode);
+		spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+
+	/*
+	 * If a flush occured before we got the ACK then our acceleration was effectively cancelled on us
+	 * GGG TODO This is a workaround for a SFE message OOO quirk, this should eventually be removed.
+	 */
+	if (feci->stats.flush_happened) {
+		feci->stats.flush_happened = false;
+
+		/*
+		 * Increment the no-action counter.  Our connection was decelerated on us with no action occurring.
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_lock_bh(&ecm_sfe_ipv4_lock);
+		_ecm_sfe_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	/*
+	 * Create succeeded
+	 */
+
+	/*
+	 * Clear any nack count
+	 */
+	feci->stats.ae_nack = 0;
+
+	/*
+	 * Clear the "accelerate pending" state and move to "accelerated" state bumping
+	 * the accelerated counters to match our new state.
+	 *
+	 * Decelerate may have been attempted while we were "pending accel" and
+	 * this function will return true if that was the case.
+	 * If decelerate was pending then we need to begin deceleration :-(
+	 */
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+
+	ecm_sfe_non_ported_ipv4_accelerated_count++;	/* Protocol specific counter */
+	ecm_sfe_ipv4_accelerated_count++;		/* General running counter */
+
+	if (!_ecm_sfe_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_ACCEL)) {
+		/*
+		 * Increment the no-action counter, this is reset if offload action is seen
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_unlock_bh(&ecm_sfe_ipv4_lock);
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_INFO("%px: Decelerate was pending\n", ci);
+
+	/*
+	 * Check if the pending decelerate was done with the defunct process.
+	 * If it was, set the is_defunct flag of the feci to false for re-try.
+	 */
+	if (feci->is_defunct) {
+		is_defunct = feci->is_defunct;
+		feci->is_defunct = false;
+	}
+
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * If the pending decelerate was done through defunct process, we should
+	 * re-try it here with the same defunct function, because the purpose of that
+	 * process is to remove the connection from the database as well after decelerating it.
+	 */
+	if (is_defunct) {
+		ecm_db_connection_make_defunct(ci);
+	} else {
+		feci->decelerate(feci);
+	}
+
+	/*
+	 * Release the connection.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv4_connection_accelerate()
+ *	Accelerate a connection
+ *
+ * GGG TODO Refactor this function into a single function that np, udp and tcp
+ * can all use and reduce the amount of code!
+ */
+static void ecm_sfe_non_ported_ipv4_connection_accelerate(struct ecm_front_end_connection_instance *feci,
+                                                                        struct ecm_classifier_process_response *pr, bool is_l2_encap,
+                                                                        struct nf_conn *ct, struct sk_buff *skb)
+{
+	struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv4_connection_instance *)feci;
+	uint16_t regen_occurrances;
+	int32_t from_ifaces_first;
+	int32_t to_ifaces_first;
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *from_sfe_iface;
+	struct ecm_db_iface_instance *to_sfe_iface;
+	int32_t from_sfe_iface_id;
+	int32_t to_sfe_iface_id;
+	uint8_t from_sfe_iface_address[ETH_ALEN];
+	uint8_t to_sfe_iface_address[ETH_ALEN];
+	ip_addr_t addr;
+#if defined(ECM_INTERFACE_L2TPV2_ENABLE) ||  defined(ECM_INTERFACE_PPTP_ENABLE) || defined(ECM_INTERFACE_GRE_TAP_ENABLE) || defined(ECM_INTERFACE_GRE_TUN_ENABLE)
+	struct net_device *dev __attribute__((unused));
+#endif
+	struct sfe_ipv4_msg *nim;
+	struct sfe_ipv4_rule_create_msg *nircm;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	sfe_tx_status_t sfe_tx_status;
+	int32_t list_index;
+	int32_t interface_type_counts[ECM_DB_IFACE_TYPE_COUNT];
+	bool rule_invalid;
+	uint8_t dest_mac_xlate[ETH_ALEN];
+	ecm_db_direction_t ecm_dir;
+	ecm_front_end_acceleration_mode_t result_mode;
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+	struct ecm_db_interface_info_pptp pptp_info;
+#endif
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	/*
+	 * Get the re-generation occurrance counter of the connection.
+	 * We compare it again at the end - to ensure that the rule construction has seen no generation
+	 * changes during rule creation.
+	 */
+	regen_occurrances = ecm_db_connection_regeneration_occurrances_get(feci->ci);
+
+	/*
+	 * Test if acceleration is permitted
+	 */
+	if (!ecm_sfe_ipv4_accel_pending_set(feci)) {
+		DEBUG_TRACE("%px: Acceleration not permitted: %px\n", feci, feci->ci);
+		return;
+	}
+
+	nim = (struct sfe_ipv4_msg *)kzalloc(sizeof(struct sfe_ipv4_msg), GFP_ATOMIC | __GFP_NOWARN);
+	if (!nim) {
+		DEBUG_WARN("%px: no memory for sfe ipv4 message structure instance: %px\n", feci, feci->ci);
+		ecm_sfe_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		return;
+	}
+
+	/*
+	 * Okay construct an accel command.
+	 * Initialise creation structure.
+	 * NOTE: We leverage the app_data void pointer to be our 32 bit connection serial number.
+	 * When we get it back we re-cast it to a uint32 and do a faster connection lookup.
+	 */
+	sfe_ipv4_msg_init(nim, SFE_SPECIAL_INTERFACE_IPV4, SFE_TX_CREATE_RULE_MSG,
+			sizeof(struct sfe_ipv4_rule_create_msg),
+			ecm_sfe_non_ported_ipv4_connection_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nircm = &nim->msg.rule_create;
+	nircm->valid_flags = 0;
+	nircm->rule_flags = 0;
+
+	/*
+	 * Initialize VLAN tag information
+	 */
+	nircm->vlan_primary_rule.ingress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_primary_rule.egress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.ingress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.egress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+
+	/*
+	 * Get the interface lists of the connection, we must have at least one interface in the list to continue
+	 */
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in from_interfaces list!\n", nnpci);
+		goto non_ported_accel_bad_rule;
+	}
+
+	to_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, to_ifaces, ECM_DB_OBJ_DIR_TO);
+	if (to_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in to_interfaces list!\n", nnpci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * First interface in each must be a known sfe interface
+	 */
+	from_sfe_iface = from_ifaces[from_ifaces_first];
+	to_sfe_iface = to_ifaces[to_ifaces_first];
+	from_sfe_iface_id = ecm_db_iface_ae_interface_identifier_get(from_sfe_iface);
+	to_sfe_iface_id = ecm_db_iface_ae_interface_identifier_get(to_sfe_iface);
+	if ((from_sfe_iface_id < 0) || (to_sfe_iface_id < 0)) {
+		DEBUG_TRACE("%px: from_sfe_iface_id: %d, to_sfe_iface_id: %d\n", nnpci, from_sfe_iface_id, to_sfe_iface_id);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * Get SFE interface ID of the top interface in heirarchy
+	 */
+	from_sfe_iface = from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1];
+	to_sfe_iface = to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1];
+
+	nircm->conn_rule.flow_top_interface_num = ecm_db_iface_interface_identifier_get(from_sfe_iface);
+	nircm->conn_rule.return_top_interface_num = ecm_db_iface_interface_identifier_get(to_sfe_iface);
+
+	/*
+	 * New rule being created
+	 */
+	nircm->valid_flags |= SFE_RULE_CREATE_CONN_VALID;
+
+	/*
+	 * Set interface numbers involved in accelerating this connection.
+	 * These are the outer facing addresses from the heirarchy interface lists we got above.
+	 * These may be overridden later if we detect special interface types e.g. ipsec.
+	 */
+	nircm->conn_rule.flow_interface_num = from_sfe_iface_id;
+	nircm->conn_rule.return_interface_num = to_sfe_iface_id;
+
+	/*
+	 * Set the mtu values. These values will be overwritten if the flow is
+	 * a specific tunnel type.
+	 */
+	nircm->conn_rule.flow_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nircm->conn_rule.return_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	/*
+	 * Set the port information. These ports can be overwritten by the PPTP protocol values,
+	 * if the flow belongs to a PPTP tunnel.
+	 */
+	nircm->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nircm->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT);
+	nircm->conn_rule.flow_ident_xlate = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM_NAT);
+	nircm->conn_rule.return_ident_xlate = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	/*
+	 * We know that each outward facing interface is known to the SFE and so this connection could be accelerated.
+	 * However the lists may also specify other interesting details that must be included in the creation command,
+	 * for example, ethernet MAC, VLAN tagging or PPPoE session information.
+	 * We get this information by walking from the outer to the innermost interface for each list and examine the interface types.
+	 *
+	 * Start with the 'from' (src) side.
+	 * NOTE: The lists may contain a complex heirarchy of similar type of interface e.g. multiple vlans or tunnels within tunnels.
+	 * This SFE cannot handle that - there is no way to describe this in the rule - if we see multiple types that would conflict we have to abort.
+	 */
+	DEBUG_TRACE("%px: Examine from/src heirarchy list\n", nnpci);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = from_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+		struct ecm_db_interface_info_pppoe pppoe_info;
+#endif
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_in_dev = NULL;
+#endif
+#if defined(ECM_INTERFACE_GRE_TAP_ENABLE) ||  defined(ECM_INTERFACE_GRE_TUN_ENABLE) || defined(ECM_INTERFACE_PPTP_ENABLE)
+		ip_addr_t saddr;
+		ip_addr_t daddr;
+#endif
+		ii = from_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", nnpci, list_index, ii, ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_BRIDGE, list_index, from_ifaces_first)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_FROM, ECM_DB_IFACE_TYPE_BRIDGE);
+			}
+
+			ecm_db_iface_bridge_address_get(ii, from_sfe_iface_address);
+			if (is_valid_ether_addr(from_sfe_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_sfe_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+			}
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", nnpci, from_sfe_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, from_sfe_iface_address);
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", nnpci, from_sfe_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", nnpci);
+				break;
+			}
+
+#ifdef ECM_INTERFACE_GRE_TAP_ENABLE
+			dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (dev) {
+				if (dev->priv_flags_ext & IFF_EXT_GRE_V4_TAP) {
+					ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, saddr);
+					ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, daddr);
+					if (!ecm_interface_tunnel_mtu_update(saddr, daddr, ECM_DB_IFACE_TYPE_GRE_TAP, &(nircm->conn_rule.flow_mtu))) {
+						rule_invalid = true;
+						DEBUG_WARN("%px: Unable to get mtu value for the GRE TAP interface\n", nnpci);
+					}
+
+				}
+				dev_put(dev);
+			}
+#endif
+
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, from_sfe_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", nnpci, from_sfe_iface_address);
+			break;
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+		case ECM_DB_IFACE_TYPE_GRE_TUN:
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, saddr);
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, daddr);
+			if (!ecm_interface_tunnel_mtu_update(saddr, daddr, ECM_DB_IFACE_TYPE_GRE_TUN, &(nircm->conn_rule.flow_mtu))) {
+				rule_invalid = true;
+				DEBUG_WARN("%px: Unable to get mtu value for the GRE TUN interface\n", nnpci);
+			}
+			break;
+#endif
+
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", nnpci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * Copy pppoe session info to the creation structure.
+			 */
+			ecm_db_iface_pppoe_session_info_get(ii, &pppoe_info);
+			nircm->pppoe_rule.flow_pppoe_session_id = pppoe_info.pppoe_session_id;
+			memcpy(nircm->pppoe_rule.flow_pppoe_remote_mac, pppoe_info.remote_mac, ETH_ALEN);
+			nircm->valid_flags |= SFE_RULE_CREATE_PPPOE_DECAP_VALID;
+			nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+
+			DEBUG_TRACE("%px: PPPoE - session: %x, mac: %pM\n", nnpci,
+					nircm->pppoe_rule.flow_pppoe_session_id,
+					nircm->pppoe_rule.flow_pppoe_remote_mac);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", nnpci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", nnpci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_in_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_in_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_in_dev, pr->return_qos_tag);
+				dev_put(vlan_in_dev);
+				vlan_in_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.ingress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.ingress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= SFE_RULE_CREATE_VLAN_VALID;
+
+			/*
+			 * If we have not yet got an ethernet mac then take this one (very unlikely as
+			 * mac should have been propagated to the slave (outer) device
+			 */
+			memcpy(from_sfe_iface_address, vlan_info.address, ETH_ALEN);
+			if (is_valid_ether_addr(from_sfe_iface_address)) {
+				memcpy(nircm->conn_rule.flow_mac, from_sfe_iface_address, ETH_ALEN);
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", nnpci, from_sfe_iface_address);
+			}
+			DEBUG_TRACE("%px: vlan tag: %x\n", nnpci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", nnpci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", nnpci);
+				break;
+			}
+
+			/*
+			 * TO DO: IPSEC ifnum in ecm_sfe_common is not implemented yet.
+			 */
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", nnpci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_PPTP:
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, saddr);
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, daddr);
+			if (!ecm_interface_tunnel_mtu_update(saddr, daddr, ECM_DB_IFACE_TYPE_PPTP, &(nircm->conn_rule.flow_mtu))) {
+				rule_invalid = true;
+				DEBUG_WARN("%px: Unable to get mtu value for the PPTP interface\n", nnpci);
+				break;
+			}
+
+			ecm_db_iface_pptp_session_info_get(ii, &pptp_info);
+
+			nircm->tuple.flow_ident = htons(pptp_info.src_call_id);
+			nircm->tuple.return_ident = htons(pptp_info.dst_call_id);
+			nircm->conn_rule.flow_ident_xlate = htons(pptp_info.src_call_id);
+			nircm->conn_rule.return_ident_xlate = htons(pptp_info.dst_call_id);
+
+			/*
+			 * TO DO: NO NO SRC IDENT DEFINED.
+			 */
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: PPTP - unsupported\n", nnpci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_LAG:
+#ifdef ECM_INTERFACE_BOND_ENABLE
+			if (sfe_is_l2_feature_enabled()) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+				/*
+				 * LAG device gets its stats by summing up all stats of its
+				 * slaves (i.e. 'ethx' devices). Please see bond_get_stats()
+				 * in linux-5.4/drivers/net/bonding/bond_main.c.
+				 * So no need to call feci->set_stats_bitmap().
+				 */
+
+				ecm_db_iface_lag_address_get(ii, from_sfe_iface_address);
+				if (is_valid_ether_addr(from_sfe_iface_address)) {
+					ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_sfe_iface_address);
+					nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_FLOW_VALID;
+					nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+				}
+				DEBUG_TRACE("%px: LAG - mac: %pM\n", nnpci, from_sfe_iface_address);
+			}
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: LAG - unsupported\n", nnpci);
+#endif
+			break;
+
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", nnpci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+
+	if (rule_invalid) {
+		DEBUG_WARN("%px: from/src Rule invalid\n", nnpci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * Now examine the TO / DEST heirarchy list to construct the destination part of the rule
+	 */
+	DEBUG_TRACE("%px: Examine to/dest heirarchy list\n", nnpci);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = to_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+		struct ecm_db_interface_info_pppoe pppoe_info;
+#endif
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_out_dev = NULL;
+#endif
+
+		ii = to_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", nnpci, list_index, ii, ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_BRIDGE, list_index, to_ifaces_first)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_TO, ECM_DB_IFACE_TYPE_BRIDGE);
+			}
+
+			ecm_db_iface_bridge_address_get(ii, to_sfe_iface_address);
+			if (is_valid_ether_addr(to_sfe_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_sfe_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", nnpci, to_sfe_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, to_sfe_iface_address);
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", nnpci, to_sfe_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", nnpci);
+				break;
+			}
+
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, to_sfe_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", nnpci, to_sfe_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", nnpci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * Copy pppoe session info to the creation structure.
+			 */
+			ecm_db_iface_pppoe_session_info_get(ii, &pppoe_info);
+			nircm->pppoe_rule.return_pppoe_session_id = pppoe_info.pppoe_session_id;
+			memcpy(nircm->pppoe_rule.return_pppoe_remote_mac, pppoe_info.remote_mac, ETH_ALEN);
+			nircm->valid_flags |= SFE_RULE_CREATE_PPPOE_ENCAP_VALID;
+			nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+
+			DEBUG_TRACE("%px: PPPoE - session: %x, mac: %pM\n", nnpci,
+					nircm->pppoe_rule.return_pppoe_session_id,
+					nircm->pppoe_rule.return_pppoe_remote_mac);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", nnpci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", nnpci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_out_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_out_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_out_dev, pr->flow_qos_tag);
+				dev_put(vlan_out_dev);
+				vlan_out_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.egress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.egress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= SFE_RULE_CREATE_VLAN_VALID;
+
+			/*
+			 * If we have not yet got an ethernet mac then take this one (very unlikely as mac should have been propagated to the slave (outer) device
+			 */
+			memcpy(to_sfe_iface_address, vlan_info.address, ETH_ALEN);
+			if (is_valid_ether_addr(to_sfe_iface_address)) {
+				memcpy(nircm->conn_rule.return_mac, to_sfe_iface_address, ETH_ALEN);
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", nnpci, to_sfe_iface_address);
+			}
+
+			DEBUG_TRACE("%px: vlan tag: %x\n", nnpci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", nnpci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", nnpci);
+				break;
+			}
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", nnpci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_LAG:
+#ifdef ECM_INTERFACE_BOND_ENABLE
+			if (sfe_is_l2_feature_enabled()) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+				/*
+				 * LAG device gets its stats by summing up all stats of its
+				 * slaves (i.e. 'ethx' devices). Please see bond_get_stats()
+				 * in linux-5.4/drivers/net/bonding/bond_main.c.
+				 * So no need to call feci->set_stats_bitmap().
+				 */
+
+				ecm_db_iface_lag_address_get(ii, to_sfe_iface_address);
+				if (is_valid_ether_addr(to_sfe_iface_address)) {
+					ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_sfe_iface_address);
+					nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_RETURN_VALID;
+					nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+				}
+				DEBUG_TRACE("%px: LAG - mac: %pM\n", nnpci, to_sfe_iface_address);
+			}
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: LAG - unsupported\n", nnpci);
+#endif
+			break;
+
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", nnpci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+
+	if (rule_invalid) {
+		DEBUG_WARN("%px: to/dest Rule invalid\n", nnpci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * Routed or bridged?
+	 */
+	if (ecm_db_connection_is_routed_get(feci->ci)) {
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_ROUTED;
+	} else {
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_BRIDGE_FLOW;
+		if (is_l2_encap) {
+			nircm->rule_flags |= SFE_RULE_CREATE_FLAG_L2_ENCAP;
+		}
+	}
+
+	if (ecm_interface_src_check || ecm_db_connection_is_pppoe_bridged_get(feci->ci)) {
+		DEBUG_INFO("%px: Source interface check flag is enabled\n", nnpci);
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_FLOW_SRC_INTERFACE_CHECK;
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_RETURN_SRC_INTERFACE_CHECK;
+	}
+
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+		nircm->qos_rule.flow_qos_tag = (uint32_t)pr->flow_qos_tag;
+		nircm->qos_rule.return_qos_tag = (uint32_t)pr->return_qos_tag;
+		nircm->valid_flags |= SFE_RULE_CREATE_QOS_VALID;
+	}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+	/*
+	 * DSCP information?
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+		nircm->dscp_rule.flow_dscp = pr->flow_dscp;
+		nircm->dscp_rule.return_dscp = pr->return_dscp;
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_DSCP_MARKING;
+		nircm->valid_flags |= SFE_RULE_CREATE_DSCP_MARKING_VALID;
+	}
+
+	/*
+	 * Set up the flow and return mark.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_MARK) {
+		nircm->mark_rule.flow_mark = (uint32_t)pr->flow_mark;
+		nircm->mark_rule.return_mark = (uint32_t)pr->return_mark;
+		nircm->valid_flags |= SFE_RULE_CREATE_MARK_VALID;
+	}
+#endif
+	/*
+	 * Set protocol
+	 */
+	nircm->tuple.protocol = (int32_t)ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * The flow_ip is where the connection established from
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, addr);
+	ECM_IP_ADDR_TO_NIN4_ADDR(nircm->tuple.flow_ip, addr);
+
+	/*
+	 * The return_ip is where the connection is established to, however, in the case of ingress
+	 * the return_ip would be the routers WAN IP - i.e. the NAT'ed version.
+	 * Getting the NAT'ed version here works for ingress or egress packets, for egress
+	 * the NAT'ed version would be the same as the normal address
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, addr);
+	ECM_IP_ADDR_TO_NIN4_ADDR(nircm->tuple.return_ip, addr);
+
+	/*
+	 * When the packet is forwarded to the next interface get the address the source IP of the
+	 * packet should be translated to.  For egress this is the NAT'ed from address.
+	 * This also works for ingress as the NAT'ed version of the WAN host would be the same as non-NAT'ed
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM_NAT, addr);
+	ECM_IP_ADDR_TO_NIN4_ADDR(nircm->conn_rule.flow_ip_xlate, addr);
+
+	/*
+	 * The destination address is what the destination IP is translated to as it is forwarded to the next interface.
+	 * For egress this would yield the normal wan host and for ingress this would correctly NAT back to the LAN host
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, addr);
+	ECM_IP_ADDR_TO_NIN4_ADDR(nircm->conn_rule.return_ip_xlate, addr);
+
+	/*
+	 * Get mac addresses.
+	 * The src_mac is the mac address of the node that established the connection.
+	 * This will work whether the from_node is LAN (egress) or WAN (ingress).
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, (uint8_t *)nircm->conn_rule.flow_mac);
+
+	/*
+	 * The dest_mac is more complex.  For egress it is the node address of the 'to' side of the connection.
+	 * For ingress it is the node adress of the NAT'ed 'to' IP.
+	 * Essentially it is the MAC of node associated with create.dest_ip and this is "to nat" side.
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, (uint8_t *)nircm->conn_rule.return_mac);
+
+	/*
+	 * The dest_mac_xlate is the mac address to replace the pkt.dst_mac when a packet is sent to->from
+	 * For bridged connections this does not change.
+	 * For routed connections this is the mac of the 'to' node side of the connection.
+	 */
+	if (ecm_db_connection_is_routed_get(feci->ci)) {
+		ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, dest_mac_xlate);
+	} else {
+		/*
+		 * Bridge flows preserve the MAC addressing
+		 */
+		memcpy(dest_mac_xlate, (uint8_t *)nircm->conn_rule.return_mac, ETH_ALEN);
+	}
+
+	/*
+	 * Refer to the Example 2 and 3 in ecm_sfe_ipv4_ip_process() function for egress
+	 * and ingress NAT'ed cases. In these cases, the destination node is the one which has the
+	 * ip_dest_addr. So, above we get the mac address of this host and use that mac address
+	 * for the destination node address in NAT'ed cases.
+	 */
+	ecm_dir = ecm_db_connection_direction_get(feci->ci);
+	if ((ecm_dir == ECM_DB_DIRECTION_INGRESS_NAT) || (ecm_dir == ECM_DB_DIRECTION_EGRESS_NAT)) {
+		memcpy(nircm->conn_rule.return_mac, dest_mac_xlate, ETH_ALEN);
+	}
+
+	/*
+	 * Sync our creation command from the assigned classifiers to get specific additional creation rules.
+	 * NOTE: These are called in ascending order of priority and so the last classifier (highest) shall
+	 * override any preceding classifiers.
+	 * This also gives the classifiers a chance to see that acceleration is being attempted.
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(feci->ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+		struct ecm_classifier_rule_create ecrc;
+		/*
+		 * NOTE: The current classifiers do not sync anything to the underlying accel engines.
+		 * In the future, if any of the classifiers wants to pass any parameter, these parameters
+		 * should be received via this object and copied to the accel engine's create object (nircm).
+		*/
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: sync from: %px, type: %d\n", nnpci, aci, aci->type_get(aci));
+		aci->sync_from_v4(aci, &ecrc);
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Release the interface lists
+	 */
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+	ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+
+	DEBUG_INFO("%px: Non-Ported Accelerate connection %px\n"
+			"Protocol: %d\n"
+			"from_mtu: %u\n"
+			"to_mtu: %u\n"
+			"from_ip: %pI4h:%d\n"
+			"to_ip: %pI4h:%d\n"
+			"from_ip_xlate: %pI4h:%d\n"
+			"to_ip_xlate: %pI4h:%d\n"
+			"from_mac: %pM\n"
+			"to_mac: %pM\n"
+			"src_iface_num: %u\n"
+			"dest_iface_num: %u\n"
+			"ingress_inner_vlan_tag: %u\n"
+			"egress_inner_vlan_tag: %u\n"
+			"ingress_outer_vlan_tag: %u\n"
+			"egress_outer_vlan_tag: %u\n"
+			"rule_flags: %x\n"
+			"valid_flags: %x\n"
+			"flow_qos_tag: %x (%u)\n"
+			"return_qos_tag: %x (%u)\n"
+			"flow_dscp: %x\n"
+			"return_dscp: %x\n"
+			"flow_mark: %x\n"
+			"return_mark: %x\n",
+			nnpci,
+			feci->ci,
+			nircm->tuple.protocol,
+			nircm->conn_rule.flow_mtu,
+			nircm->conn_rule.return_mtu,
+			&nircm->tuple.flow_ip, nircm->tuple.flow_ident,
+			&nircm->tuple.return_ip, nircm->tuple.return_ident,
+			&nircm->conn_rule.flow_ip_xlate, nircm->conn_rule.flow_ident_xlate,
+			&nircm->conn_rule.return_ip_xlate, nircm->conn_rule.return_ident_xlate,
+			nircm->conn_rule.flow_mac,
+			nircm->conn_rule.return_mac,
+			nircm->conn_rule.flow_interface_num,
+			nircm->conn_rule.return_interface_num,
+			nircm->vlan_primary_rule.ingress_vlan_tag,
+			nircm->vlan_primary_rule.egress_vlan_tag,
+			nircm->vlan_secondary_rule.ingress_vlan_tag,
+			nircm->vlan_secondary_rule.egress_vlan_tag,
+			nircm->rule_flags,
+			nircm->valid_flags,
+			nircm->qos_rule.flow_qos_tag, nircm->qos_rule.flow_qos_tag,
+			nircm->qos_rule.return_qos_tag, nircm->qos_rule.return_qos_tag,
+			nircm->dscp_rule.flow_dscp,
+			nircm->dscp_rule.return_dscp,
+			nircm->mark_rule.flow_mark,
+			nircm->mark_rule.return_mark);
+
+	/*
+	 * Now that the rule has been constructed we re-compare the generation occurrance counter.
+	 * If there has been a change then we abort because the rule may have been created using
+	 * unstable data - especially if another thread has begun regeneration of the connection state.
+	 * NOTE: This does not prevent a regen from being flagged immediately after this line of code either,
+	 * or while the acceleration rule is in flight to the sfe.
+	 * This is only to check for consistency of rule state - not that the state is stale.
+	 * Remember that the connection is marked as "accel pending state" so if a regen is flagged immediately
+	 * after this check passes, the connection will be decelerated and refreshed very quickly.
+	 */
+	if (regen_occurrances != ecm_db_connection_regeneration_occurrances_get(feci->ci)) {
+		DEBUG_INFO("%px: connection:%px regen occurred - aborting accel rule.\n", feci, feci->ci);
+		ecm_sfe_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		kfree(nim);
+		return;
+	}
+
+	/*
+	 * Ref the connection before issuing an SFE rule
+	 * This ensures that when the SFE responds to the command - which may even be immediately -
+	 * the callback function can trust the correct ref was taken for its purpose.
+	 * NOTE: remember that this will also implicitly hold the feci.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Call the rule create function
+	 */
+	sfe_tx_status = sfe_ipv4_tx(ecm_sfe_ipv4_mgr, nim);
+	if (sfe_tx_status == SFE_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;
+		spin_unlock_bh(&feci->lock);
+		kfree(nim);
+		return;
+	}
+
+	kfree(nim);
+
+	/*
+	 * Release that ref!
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * TX failed
+	 */
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Accel mode unexpected: %d\n", nnpci, feci->accel_mode);
+	feci->stats.driver_fail_total++;
+	feci->stats.driver_fail++;
+	if (feci->stats.driver_fail >= feci->stats.driver_fail_limit) {
+		DEBUG_WARN("%px: Accel failed - driver fail limit\n", nnpci);
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DRIVER;
+	} else {
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	_ecm_sfe_ipv4_accel_pending_clear(feci, result_mode);
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+	spin_unlock_bh(&feci->lock);
+	return;
+
+non_ported_accel_bad_rule:
+	;
+
+	kfree(nim);
+	/*
+	 * Jump to here when rule data is bad and an offload command cannot be constructed
+	 */
+	DEBUG_WARN("%px: Accel failed - bad rule\n", nnpci);
+	ecm_sfe_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_FAIL_RULE);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv4_connection_destroy_callback()
+ *	Callback for handling destroy ack/nack calls.
+ */
+static void ecm_sfe_non_ported_ipv4_connection_destroy_callback(void *app_data, struct sfe_ipv4_msg *nim)
+{
+	struct sfe_ipv4_rule_destroy_msg *__attribute__((unused))nirdm = &nim->msg.rule_destroy;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci;
+
+	/*
+	 * Is this a response to a destroy message?
+	 */
+	if (nim->cm.type != SFE_TX_DESTROY_RULE_MSG) {
+		DEBUG_ERROR("%px: non-ported destroy callback with improper type: %d\n", nim, nim->cm.type);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: destroy callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	nnpci = (struct ecm_sfe_non_ported_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_sfe_ipv4_decel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: decelerate response for connection: %px\n", nnpci, feci->ci);
+	DEBUG_TRACE("%px: flow_ip: %pI4h:%d\n", nnpci, &nirdm->tuple.flow_ip, nirdm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: %pI4h:%d\n", nnpci, &nirdm->tuple.return_ip, nirdm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", nnpci, nirdm->tuple.protocol);
+
+	/*
+	 * Drop decel pending counter
+	 */
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	ecm_sfe_ipv4_pending_decel_count--;
+	DEBUG_ASSERT(ecm_sfe_ipv4_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If decel is not still pending then it's possible that the SFE ended acceleration by some other reason e.g. flush
+	 * In which case we cannot rely on the response we get here.
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING) {
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connections.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_TRACE("%px: response: %d\n", nnpci, nim->cm.response);
+	if (nim->cm.response != SFE_CMN_RESPONSE_ACK) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DECEL;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	/*
+	 * If connection became defunct then set mode so that no further accel/decel attempts occur.
+	 */
+	if (feci->is_defunct) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT_SHORT;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Non-Ported acceleration ends
+	 */
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	ecm_sfe_non_ported_ipv4_accelerated_count--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_sfe_non_ported_ipv4_accelerated_count >= 0, "Bad non-ported accel counter\n");
+	ecm_sfe_ipv4_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_sfe_ipv4_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+	/*
+	 * Release the connections.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv4_connection_decelerate_msg_send()
+ *	Prepares and sends a decelerate message to acceleration engine.
+ */
+static bool ecm_sfe_non_ported_ipv4_connection_decelerate_msg_send(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv4_connection_instance *)feci;
+	struct sfe_ipv4_msg nim;
+	struct sfe_ipv4_rule_destroy_msg *nirdm;
+	ip_addr_t addr;
+	sfe_tx_status_t sfe_tx_status;
+	bool ret;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	/*
+	 * Increment the decel pending counter
+	 */
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	ecm_sfe_ipv4_pending_decel_count++;
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+	/*
+	 * Prepare deceleration message
+	 */
+	sfe_ipv4_msg_init(&nim, SFE_SPECIAL_INTERFACE_IPV4, SFE_TX_DESTROY_RULE_MSG,
+			sizeof(struct sfe_ipv4_rule_destroy_msg),
+			ecm_sfe_non_ported_ipv4_connection_destroy_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nirdm = &nim.msg.rule_destroy;
+	nirdm->tuple.protocol = (int32_t)ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * Get addressing information
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, addr);
+	ECM_IP_ADDR_TO_NIN4_ADDR(nirdm->tuple.flow_ip, addr);
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, addr);
+	ECM_IP_ADDR_TO_NIN4_ADDR(nirdm->tuple.return_ip, addr);
+	nirdm->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nirdm->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT);
+
+#ifdef ECM_INTERFACE_PPTP_ENABLE
+	if (nirdm->tuple.protocol == IPPROTO_GRE) {
+		struct ecm_db_interface_info_pptp pptp_info;
+		struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+		int32_t from_ifaces_first;
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+
+		/*
+		 * Get the interface lists of the connection, we must have at least one interface in the list to continue
+		 */
+		from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+		if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+			DEBUG_WARN("%px: Decel attempt failed - no interfaces in from_interfaces list!\n", nnpci);
+			spin_lock_bh(&feci->lock);
+			spin_unlock_bh(&feci->lock);
+			return false;
+		}
+
+		ii = from_ifaces[from_ifaces_first];
+		ii_type = ecm_db_iface_type_get(ii);
+		DEBUG_TRACE("%px: iface_first: %d, ii: %px, type: %d (%s)\n", nnpci, from_ifaces_first, ii, ii_type, ecm_db_interface_type_to_string(ii_type));
+
+		/*
+		 * For PPTP flows, use PPTP local/peer call-id in place of L4 ports
+		 */
+		if (ECM_DB_IFACE_TYPE_PPTP == ii_type) {
+			ecm_db_iface_pptp_session_info_get(ii, &pptp_info);
+			nirdm->tuple.flow_ident = htons(pptp_info.src_call_id);
+			nirdm->tuple.return_ident = htons(pptp_info.dst_call_id);
+		}
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+	}
+#endif
+	DEBUG_INFO("%px: Non-Ported Connection %px decelerate\n"
+			"protocol: %d\n"
+			"src_ip: %pI4:%d\n"
+			"dest_ip: %pI4:%d\n",
+			nnpci, feci->ci, nirdm->tuple.protocol,
+			&nirdm->tuple.flow_ip, nirdm->tuple.flow_ident,
+			&nirdm->tuple.return_ip, nirdm->tuple.return_ident);
+
+	/*
+	 * Take a ref to the feci->ci so that it will persist until we get a response from the SFE.
+	 * NOTE: This will implicitly hold the feci too.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Destroy the SFE connection cache entry.
+	 */
+	sfe_tx_status = sfe_ipv4_tx(ecm_sfe_ipv4_mgr, &nim);
+	if (sfe_tx_status == SFE_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;			/* Reset */
+		ret = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return true;
+	}
+
+	/*
+	 * TX failed
+	 */
+	ret = ecm_front_end_destroy_failure_handle(feci);
+
+	/*
+	 * Release the ref take, SFE driver did not accept our command.
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * Could not send the request, decrement the decel pending counter
+	 */
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	ecm_sfe_ipv4_pending_decel_count--;
+	DEBUG_ASSERT(ecm_sfe_ipv4_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+	return ret;
+}
+
+/*
+ * ecm_sfe_non_ported_ipv4_connection_decelerate()
+ *     Decelerate a connection
+ */
+static bool ecm_sfe_non_ported_ipv4_connection_decelerate(struct ecm_front_end_connection_instance *feci)
+{
+	/*
+	 * Check if accel mode is OK for the deceleration.
+	 */
+	spin_lock_bh(&feci->lock);
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	return ecm_sfe_non_ported_ipv4_connection_decelerate_msg_send(feci);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv4_connection_defunct_callback()
+ *	Callback to be called when a non-ported connection has become defunct.
+ */
+bool ecm_sfe_non_ported_ipv4_connection_defunct_callback(void *arg, int *accel_mode)
+{
+	bool ret;
+	struct ecm_front_end_connection_instance *feci = (struct ecm_front_end_connection_instance *)arg;
+	struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	spin_lock_bh(&feci->lock);
+	/*
+	 * Check if the connection can be defuncted.
+	 */
+	if (!ecm_front_end_common_connection_defunct_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+
+	/*
+	 * If none of the cases matched above, this means the connection is in the
+	 * accel mode, so we force a deceleration.
+	 * NOTE: If the mode is accel pending then the decel will be actioned when that is completed.
+	 */
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	ret = ecm_sfe_non_ported_ipv4_connection_decelerate_msg_send(feci);
+
+	/*
+	 * Copy the accel_mode which is returned from the decelerate message function. This value
+	 * will be used in the caller to decide releasing the final reference of the connection.
+	 * But if this function reaches to here, the caller care about the ret. If ret is true,
+	 * the reference will be released regardless of the accel_mode. If ret is false, accel_mode
+	 * will be in the ACCEL state (for destroy re-try) and this state will not be used in the
+	 * caller's decision. It looks for ACCEL_FAIL states.
+	 */
+	spin_lock_bh(&feci->lock);
+	*accel_mode = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+
+	return ret;
+}
+
+/*
+ * ecm_sfe_non_ported_ipv4_connection_accel_state_get()
+ *	Get acceleration state
+ */
+static ecm_front_end_acceleration_mode_t ecm_sfe_non_ported_ipv4_connection_accel_state_get(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv4_connection_instance *)feci;
+	ecm_front_end_acceleration_mode_t state;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	spin_lock_bh(&feci->lock);
+	state = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+	return state;
+}
+
+/*
+ * ecm_sfe_non_ported_ipv4_connection_action_seen()
+ *	Acceleration action / activity has been seen for this connection.
+ *
+ * NOTE: Call the action_seen() method when the SFE has demonstrated that it has offloaded some data for a connection.
+ */
+static void ecm_sfe_non_ported_ipv4_connection_action_seen(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	DEBUG_INFO("%px: Action seen\n", nnpci);
+	spin_lock_bh(&feci->lock);
+	feci->stats.no_action_seen = 0;
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv4_connection_accel_ceased()
+ *	SFE has indicated that acceleration has stopped.
+ *
+ * NOTE: This is called in response to an SFE self-initiated termination of acceleration.
+ * This must NOT be called because the ECM terminated the acceleration.
+ */
+static void ecm_sfe_non_ported_ipv4_connection_accel_ceased(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	DEBUG_INFO("%px: accel ceased\n", nnpci);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If we are in accel-pending state then the SFE has issued a flush out-of-order
+	 * with the ACK/NACK we are actually waiting for.
+	 * To work around this we record a "flush has already happened" and will action it when we finally get that ACK/NACK.
+	 * GGG TODO This should eventually be removed when the SFE honours messaging sequence.
+	 */
+	if (feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING) {
+		feci->stats.flush_happened = true;
+		feci->stats.flush_happened_total++;
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If connection is no longer accelerated by the time we get here just ignore the command
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_ACCEL) {
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If the no_action_seen counter was not reset then acceleration ended without any offload action
+	 */
+	if (feci->stats.no_action_seen) {
+		feci->stats.no_action_seen_total++;
+	}
+
+	/*
+	 * If the no_action_seen indicates successive cessations of acceleration without any offload action occuring
+	 * then we fail out this connection
+	 */
+	if (feci->stats.no_action_seen >= feci->stats.no_action_seen_limit) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_NO_ACTION;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Non-Ported acceleration ends
+	 */
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	ecm_sfe_non_ported_ipv4_accelerated_count--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_sfe_non_ported_ipv4_accelerated_count >= 0, "Bad non-ported accel counter\n");
+	ecm_sfe_ipv4_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_sfe_ipv4_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv4_connection_ref()
+ *	Ref a connection front end instance
+ */
+static void ecm_sfe_non_ported_ipv4_connection_ref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	spin_lock_bh(&feci->lock);
+	feci->refs++;
+	DEBUG_TRACE("%px: nnpci ref %d\n", nnpci, feci->refs);
+	DEBUG_ASSERT(feci->refs > 0, "%px: ref wrap\n", nnpci);
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv4_connection_deref()
+ *	Deref a connection front end instance
+ */
+static int ecm_sfe_non_ported_ipv4_connection_deref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	spin_lock_bh(&feci->lock);
+	feci->refs--;
+	DEBUG_ASSERT(feci->refs >= 0, "%px: ref wrap\n", nnpci);
+
+	if (feci->refs > 0) {
+		int refs = feci->refs;
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: nnpci deref %d\n", nnpci, refs);
+		return refs;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * We can now destroy the instance
+	 */
+	DEBUG_TRACE("%px: nnpci final\n", nnpci);
+	DEBUG_CLEAR_MAGIC(nnpci);
+	kfree(nnpci);
+
+	return 0;
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_sfe_non_ported_ipv4_connection_state_get()
+ *	Return the state of this Non ported front end instance
+ */
+static int ecm_sfe_non_ported_ipv4_connection_state_get(struct ecm_front_end_connection_instance *feci, struct ecm_state_file_instance *sfi)
+{
+	struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	return ecm_front_end_common_connection_state_get(feci, sfi, "sfe_v4.non_ported");
+}
+#endif
+
+/*
+ * ecm_sfe_non_ported_ipv4_connection_instance_alloc()
+ *	Create a front end instance specific for non-ported connection
+ */
+struct ecm_sfe_non_ported_ipv4_connection_instance *ecm_sfe_non_ported_ipv4_connection_instance_alloc(bool can_accel,
+								int protocol,
+								struct ecm_db_connection_instance **nci)
+{
+	struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_db_connection_instance *ci;
+
+	if (ecm_sfe_ipv4_is_conn_limit_reached()) {
+		DEBUG_TRACE("Reached connection limit\n");
+		return NULL;
+	}
+
+	/*
+	 * Now allocate the new connection
+	 */
+	*nci = ecm_db_connection_alloc();
+	if (!*nci) {
+		DEBUG_WARN("Failed to allocate connection\n");
+		return NULL;
+	}
+
+	ci = *nci;
+
+	nnpci = (struct ecm_sfe_non_ported_ipv4_connection_instance *)kzalloc(sizeof(struct ecm_sfe_non_ported_ipv4_connection_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!nnpci) {
+		DEBUG_WARN("Non-Ported Front end alloc failed\n");
+		ecm_db_connection_deref(ci);
+		return NULL;
+	}
+
+	/*
+	 * Refs is 1 for the creator of the connection
+	 */
+	feci = (struct ecm_front_end_connection_instance *)nnpci;
+	feci->refs = 1;
+	DEBUG_SET_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC);
+	spin_lock_init(&feci->lock);
+
+	feci->can_accel = can_accel;
+	feci->accel_mode = (can_accel)? ECM_FRONT_END_ACCELERATION_MODE_DECEL : ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED;
+	feci->accel_engine = ECM_FRONT_END_ENGINE_SFE;
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	feci->stats.no_action_seen_limit = ecm_sfe_ipv4_no_action_limit_default;
+	feci->stats.driver_fail_limit = ecm_sfe_ipv4_driver_fail_limit_default;
+	feci->stats.ae_nack_limit = ecm_sfe_ipv4_nack_limit_default;
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+	/*
+	 * Copy reference to connection - no need to ref ci as ci maintains a ref to this instance instead (this instance persists for as long as ci does)
+	 */
+	feci->ci = ci;
+
+	feci->ip_version = 4;
+
+	feci->protocol = protocol;
+
+	/*
+	 * Populate the methods and callbacks
+	 */
+	feci->ref = ecm_sfe_non_ported_ipv4_connection_ref;
+	feci->deref = ecm_sfe_non_ported_ipv4_connection_deref;
+	feci->accelerate = ecm_sfe_non_ported_ipv4_connection_accelerate;
+	feci->decelerate = ecm_sfe_non_ported_ipv4_connection_decelerate;
+	feci->accel_state_get = ecm_sfe_non_ported_ipv4_connection_accel_state_get;
+	feci->action_seen = ecm_sfe_non_ported_ipv4_connection_action_seen;
+	feci->accel_ceased = ecm_sfe_non_ported_ipv4_connection_accel_ceased;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	feci->state_get = ecm_sfe_non_ported_ipv4_connection_state_get;
+#endif
+	feci->ae_interface_number_by_dev_get = ecm_sfe_common_get_interface_number_by_dev;
+	feci->ae_interface_number_by_dev_type_get = ecm_sfe_common_get_interface_number_by_dev_type;
+	feci->ae_interface_type_get = ecm_sfe_common_get_interface_type;
+	feci->regenerate = ecm_sfe_common_connection_regenerate;
+
+	ecm_sfe_common_init_fe_info(&nnpci->fe_info);
+
+	feci->get_stats_bitmap = ecm_sfe_non_ported_ipv4_get_stats_bitmap;
+	feci->set_stats_bitmap = ecm_sfe_non_ported_ipv4_set_stats_bitmap;
+	feci->update_rule = ecm_sfe_common_update_rule;
+
+	return nnpci;
+}
+
+/*
+ * ecm_sfe_non_ported_ipv4_debugfs_init()
+ */
+bool ecm_sfe_non_ported_ipv4_debugfs_init(struct dentry *dentry)
+{
+	if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry,
+					(u32 *)&ecm_sfe_non_ported_ipv4_accelerated_count)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv4 non_ported_accelerated_count file in debugfs\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-ecm/frontends/sfe/ecm_sfe_non_ported_ipv4.h b/qca-nss-ecm/frontends/sfe/ecm_sfe_non_ported_ipv4.h
new file mode 100644
index 0000000..c5a1a71
--- /dev/null
+++ b/qca-nss-ecm/frontends/sfe/ecm_sfe_non_ported_ipv4.h
@@ -0,0 +1,25 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015 The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern bool ecm_sfe_non_ported_ipv4_debugfs_init(struct dentry *dentry);
+
+extern struct ecm_sfe_non_ported_ipv4_connection_instance *ecm_sfe_non_ported_ipv4_connection_instance_alloc(
+								bool can_accel, int protocol,
+								struct ecm_db_connection_instance **nci);
+extern bool ecm_sfe_non_ported_ipv4_connection_defunct_callback(void *arg, int *accel_mode);
+extern void ecm_sfe_non_ported_ipv4_sit_set_peer(struct ecm_sfe_non_ported_ipv4_connection_instance *nnpci, struct sk_buff *skb);
diff --git a/qca-nss-ecm/frontends/sfe/ecm_sfe_non_ported_ipv6.c b/qca-nss-ecm/frontends/sfe/ecm_sfe_non_ported_ipv6.c
new file mode 100644
index 0000000..9c99fae
--- /dev/null
+++ b/qca-nss-ecm/frontends/sfe/ecm_sfe_non_ported_ipv6.c
@@ -0,0 +1,1802 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/debugfs.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/ip6_route.h>
+#include <net/ip6_fib.h>
+#include <net/addrconf.h>
+#include <net/ipv6.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in6.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv6.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv6/nf_conntrack_ipv6.h>
+#include <net/netfilter/ipv6/nf_defrag_ipv6.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_SFE_NON_PORTED_IPV6_DEBUG_LEVEL
+
+#include <sfe_api.h>
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#include "ecm_sfe_non_ported_ipv6.h"
+#include "ecm_sfe_ipv6.h"
+#include "ecm_sfe_common.h"
+#include "ecm_front_end_common.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_SFE_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC 0xEC35
+
+/*
+ * struct ecm_sfe_non_ported_ipv6_connection_instance
+ *	A connection specific front end instance for Non-Ported connections
+ */
+struct ecm_sfe_non_ported_ipv6_connection_instance {
+	struct ecm_front_end_connection_instance base;		/* Base class */
+	struct ecm_sfe_common_fe_info fe_info;			/* Front end information */
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+static int ecm_sfe_non_ported_ipv6_accelerated_count = 0;		/* Number of Non-Ported connections currently offloaded */
+
+/*
+ * ecm_non_sfe_ported_ipv6_get_stats_bitmap()
+ *	Get bit map
+ */
+static uint32_t ecm_sfe_non_ported_ipv6_get_stats_bitmap(struct ecm_front_end_connection_instance *feci, ecm_db_obj_dir_t dir)
+{
+	struct ecm_sfe_non_ported_ipv6_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv6_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	return ecm_sfe_common_get_stats_bitmap(&nnpci->fe_info, dir);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv6_set_stats_bitmap()
+ *	Set bit map
+ */
+static void ecm_sfe_non_ported_ipv6_set_stats_bitmap(struct ecm_front_end_connection_instance *feci, ecm_db_obj_dir_t dir, uint8_t bit)
+{
+	struct ecm_sfe_non_ported_ipv6_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv6_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	ecm_sfe_common_set_stats_bitmap(&nnpci->fe_info, dir, bit);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv6_connection_callback()
+ *	Callback for handling create ack/nack calls.
+ */
+static void ecm_sfe_non_ported_ipv6_connection_callback(void *app_data, struct sfe_ipv6_msg *nim)
+{
+	struct sfe_ipv6_rule_create_msg *nircm = &nim->msg.rule_create;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_sfe_non_ported_ipv6_connection_instance *nnpci;
+	ip_addr_t flow_ip;
+	ip_addr_t return_ip;
+	ecm_front_end_acceleration_mode_t result_mode;
+	bool is_defunct = false;
+
+	/*
+	 * Is this a response to a create message?
+	 */
+	if (nim->cm.type != SFE_TX_CREATE_RULE_MSG) {
+		DEBUG_ERROR("%px: non_ported create callback with improper type: %d, serial: %u\n", nim, nim->cm.type, serial);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: create callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	nnpci = (struct ecm_sfe_non_ported_ipv6_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	ECM_SFE_IPV6_ADDR_TO_IP_ADDR(flow_ip, nircm->tuple.flow_ip);
+	ECM_SFE_IPV6_ADDR_TO_IP_ADDR(return_ip, nircm->tuple.return_ip);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_sfe_ipv6_accel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: accelerate response for connection: %px, serial: %u\n", nnpci, feci->ci, serial);
+	DEBUG_TRACE("%px: rule_flags: %x, valid_flags: %x\n", nnpci, nircm->rule_flags, nircm->valid_flags);
+	DEBUG_TRACE("%px: flow_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", nnpci, ECM_IP_ADDR_TO_OCTAL(flow_ip), nircm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", nnpci, ECM_IP_ADDR_TO_OCTAL(return_ip), nircm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", nnpci, nircm->tuple.protocol);
+
+	/*
+	 * Handle the creation result code.
+	 */
+	DEBUG_TRACE("%px: response: %d\n", nnpci, nim->cm.response);
+	if (nim->cm.response != SFE_CMN_RESPONSE_ACK) {
+		/*
+		 * Creation command failed (specific reason ignored).
+		 */
+		DEBUG_TRACE("%px: accel nack: %d\n", nnpci, nim->cm.error);
+		spin_lock_bh(&feci->lock);
+		DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+		feci->stats.ae_nack++;
+		feci->stats.ae_nack_total++;
+		if (feci->stats.ae_nack >= feci->stats.ae_nack_limit) {
+			/*
+			 * Too many SFE rejections
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_ACCEL_ENGINE;
+		} else {
+			/*
+			 * Revert to decelerated
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+		}
+
+		/*
+		 * TODO: Why is this differnt than IPv4?
+		 * Clear any decelerate pending flag since we aren't accelerated anyway we can just clear this whether it is set or not
+		 */
+		feci->stats.decelerate_pending = false;
+
+		/*
+		 * If connection is now defunct then set mode to ensure no further accel attempts occur
+		 */
+		if (feci->is_defunct) {
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT;
+		}
+
+		spin_lock_bh(&ecm_sfe_ipv6_lock);
+		_ecm_sfe_ipv6_accel_pending_clear(feci, result_mode);
+		spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+
+	/*
+	 * If a flush occured before we got the ACK then our acceleration was effectively cancelled on us
+	 * GGG TODO This is a workaround for a SFE message OOO quirk, this should eventually be removed.
+	 */
+	if (feci->stats.flush_happened) {
+		feci->stats.flush_happened = false;
+
+		/*
+		 * Increment the no-action counter.  Our connectin was decelerated on us with no action occurring.
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_lock_bh(&ecm_sfe_ipv6_lock);
+		_ecm_sfe_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	/*
+	 * Create succeeded
+	 */
+
+	/*
+	 * Clear any nack count
+	 */
+	feci->stats.ae_nack = 0;
+
+	/*
+	 * Clear the "accelerate pending" state and move to "accelerated" state bumping
+	 * the accelerated counters to match our new state.
+	 *
+	 * Decelerate may have been attempted while we were "pending accel" and
+	 * this function will return true if that was the case.
+	 * If decelerate was pending then we need to begin deceleration :-(
+	 */
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+
+	ecm_sfe_non_ported_ipv6_accelerated_count++;	/* Protocol specific counter */
+	ecm_sfe_ipv6_accelerated_count++;				/* General running counter */
+
+	if (!_ecm_sfe_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_ACCEL)) {
+		/*
+		 * Increment the no-action counter, this is reset if offload action is seen
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_unlock_bh(&ecm_sfe_ipv6_lock);
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_INFO("%px: Decelerate was pending\n", ci);
+
+	/*
+	 * Check if the pending decelerate was done with the defunct process.
+	 * If it was, set the is_defunct flag of the feci to false for re-try.
+	 */
+	if (feci->is_defunct) {
+		is_defunct = feci->is_defunct;
+		feci->is_defunct = false;
+	}
+
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * If the pending decelerate was done through defunct process, we should
+	 * re-try it here with the same defunct function, because the purpose of that
+	 * process is to remove the connection from the database as well after decelerating it.
+	 */
+	if (is_defunct) {
+		ecm_db_connection_make_defunct(ci);
+	} else {
+		feci->decelerate(feci);
+	}
+
+	/*
+	 * Release the connection.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv6_connection_accelerate()
+ *	Accelerate a connection
+ *
+ * GGG TODO Refactor this function into a single function that np, udp and tcp
+ * can all use and reduce the amount of code!
+ */
+static void ecm_sfe_non_ported_ipv6_connection_accelerate(struct ecm_front_end_connection_instance *feci,
+                                                                        struct ecm_classifier_process_response *pr, bool is_l2_encap,
+                                                                        struct nf_conn *ct, struct sk_buff *skb)
+{
+	struct ecm_sfe_non_ported_ipv6_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv6_connection_instance *)feci;
+	uint16_t regen_occurrances;
+	int32_t from_ifaces_first;
+	int32_t to_ifaces_first;
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *from_sfe_iface;
+	struct ecm_db_iface_instance *to_sfe_iface;
+	int32_t from_sfe_iface_id;
+	int32_t to_sfe_iface_id;
+	uint8_t from_sfe_iface_address[ETH_ALEN];
+	uint8_t to_sfe_iface_address[ETH_ALEN];
+	struct sfe_ipv6_msg *nim;
+	struct sfe_ipv6_rule_create_msg *nircm;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	sfe_tx_status_t sfe_tx_status;
+	int32_t list_index;
+	int32_t interface_type_counts[ECM_DB_IFACE_TYPE_COUNT];
+	bool rule_invalid;
+	ip_addr_t src_ip;
+	ip_addr_t dest_ip;
+	ecm_front_end_acceleration_mode_t result_mode;
+#if defined(ECM_INTERFACE_GRE_TAP_ENABLE) || defined(ECM_INTERFACE_GRE_TUN_ENABLE)
+	struct net_device *dev;
+#endif
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	/*
+	 * Get the re-generation occurrance counter of the connection.
+	 * We compare it again at the end - to ensure that the rule construction has seen no generation
+	 * changes during rule creation.
+	 */
+	regen_occurrances = ecm_db_connection_regeneration_occurrances_get(feci->ci);
+
+	/*
+	 * Test if acceleration is permitted
+	 */
+	if (!ecm_sfe_ipv6_accel_pending_set(feci)) {
+		DEBUG_TRACE("%px: Acceleration not permitted: %px\n", feci, feci->ci);
+		return;
+	}
+
+	nim = (struct sfe_ipv6_msg *)kzalloc(sizeof(struct sfe_ipv6_msg), GFP_ATOMIC | __GFP_NOWARN);
+	if (!nim) {
+		DEBUG_WARN("%px: no memory for sfe ipv6 message structure instance: %px\n", feci, feci->ci);
+		ecm_sfe_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		return;
+	}
+
+	/*
+	 * Okay construct an accel command.
+	 * Initialise creation structure.
+	 * NOTE: We leverage the app_data void pointer to be our 32 bit connection serial number.
+	 * When we get it back we re-cast it to a uint32 and do a faster connection lookup.
+	 */
+	sfe_ipv6_msg_init(nim, SFE_SPECIAL_INTERFACE_IPV6, SFE_TX_CREATE_RULE_MSG,
+			sizeof(struct sfe_ipv6_rule_create_msg),
+			ecm_sfe_non_ported_ipv6_connection_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nircm = &nim->msg.rule_create;
+	nircm->valid_flags = 0;
+	nircm->rule_flags = 0;
+
+	/*
+	 * Initialize VLAN tag information
+	 */
+	nircm->vlan_primary_rule.ingress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_primary_rule.egress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.ingress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.egress_vlan_tag = ECM_FRONT_END_VLAN_ID_NOT_CONFIGURED;
+
+	/*
+	 * Get the interface lists of the connection, we must have at least one interface in the list to continue
+	 */
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in from_interfaces list!\n", nnpci);
+		goto non_ported_accel_bad_rule;
+	}
+
+	to_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, to_ifaces, ECM_DB_OBJ_DIR_TO);
+	if (to_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in to_interfaces list!\n", nnpci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * First interface in each must be a known sfe interface
+	 */
+	from_sfe_iface = from_ifaces[from_ifaces_first];
+	to_sfe_iface = to_ifaces[to_ifaces_first];
+	from_sfe_iface_id = ecm_db_iface_ae_interface_identifier_get(from_sfe_iface);
+	to_sfe_iface_id = ecm_db_iface_ae_interface_identifier_get(to_sfe_iface);
+	if ((from_sfe_iface_id < 0) || (to_sfe_iface_id < 0)) {
+		DEBUG_TRACE("%px: from_sfe_iface_id: %d, to_sfe_iface_id: %d\n", nnpci, from_sfe_iface_id, to_sfe_iface_id);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * Get SFE interface ID of the top interface in heirarchy
+	 */
+	from_sfe_iface = from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1];
+	to_sfe_iface = to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX - 1];
+	nircm->conn_rule.flow_top_interface_num = ecm_db_iface_interface_identifier_get(from_sfe_iface);
+	nircm->conn_rule.return_top_interface_num = ecm_db_iface_interface_identifier_get(to_sfe_iface);
+
+	/*
+	 * New rule being created
+	 */
+	nircm->valid_flags |= SFE_RULE_CREATE_CONN_VALID;
+
+	/*
+	 * Set interface numbers involved in accelerating this connection.
+	 * These are the outer facing addresses from the heirarchy interface lists we got above.
+	 * These may be overridden later if we detect special interface types e.g. ipsec.
+	 */
+	nircm->conn_rule.flow_interface_num = from_sfe_iface_id;
+	nircm->conn_rule.return_interface_num = to_sfe_iface_id;
+
+	/*
+	 * Set the mtu values. These values will be overwritten if the flow is
+	 * a specific tunnel type.
+	 */
+	nircm->conn_rule.flow_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nircm->conn_rule.return_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	/*
+	 * We know that each outward facing interface is known to the SFE and so this connection could be accelerated.
+	 * However the lists may also specify other interesting details that must be included in the creation command,
+	 * for example, ethernet MAC, VLAN tagging or PPPoE session information.
+	 * We get this information by walking from the outer to the innermost interface for each list and examine the interface types.
+	 *
+	 * Start with the 'from' (src) side.
+	 * NOTE: The lists may contain a complex heirarchy of similar type of interface e.g. multiple vlans or tunnels within tunnels.
+	 * This SFE cannot handle that - there is no way to describe this in the rule - if we see multiple types that would conflict we have to abort.
+	 */
+	DEBUG_TRACE("%px: Examine from/src heirarchy list\n", nnpci);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = from_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+		struct ecm_db_interface_info_pppoe pppoe_info;
+#endif
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_in_dev = NULL;
+#endif
+#if defined(ECM_INTERFACE_GRE_TAP_ENABLE) || defined(ECM_INTERFACE_GRE_TUN_ENABLE)
+		ip_addr_t saddr;
+		ip_addr_t daddr;
+#endif
+		ii = from_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", nnpci, list_index, ii, ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_BRIDGE, list_index, from_ifaces_first)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_FROM, ECM_DB_IFACE_TYPE_BRIDGE);
+			}
+
+			ecm_db_iface_bridge_address_get(ii, from_sfe_iface_address);
+			if (is_valid_ether_addr(from_sfe_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_sfe_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+			}
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", nnpci, from_sfe_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, from_sfe_iface_address);
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", nnpci, from_sfe_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", nnpci);
+				break;
+			}
+
+#ifdef ECM_INTERFACE_GRE_TAP_ENABLE
+			dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (dev) {
+				if (dev->priv_flags_ext & IFF_EXT_GRE_V6_TAP) {
+					ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, saddr);
+					ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, daddr);
+					if (!ecm_interface_tunnel_mtu_update(saddr, daddr, ECM_DB_IFACE_TYPE_GRE_TAP, &(nircm->conn_rule.flow_mtu))) {
+						rule_invalid = true;
+						DEBUG_WARN("%px: Unable to get mtu value for the GRE TAP interface\n", nnpci);
+					}
+				}
+				dev_put(dev);
+			}
+#endif
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, from_sfe_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", nnpci, from_sfe_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_GRE_TUN:
+#ifdef ECM_INTERFACE_GRE_TUN_ENABLE
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, saddr);
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, daddr);
+			if (!ecm_interface_tunnel_mtu_update(saddr, daddr, ECM_DB_IFACE_TYPE_GRE_TUN, &(nircm->conn_rule.flow_mtu))) {
+				rule_invalid = true;
+				DEBUG_WARN("%px: Unable to get mtu value for the GRE TUN interface\n", nnpci);
+			}
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", nnpci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * Copy pppoe session info to the creation structure.
+			 */
+			ecm_db_iface_pppoe_session_info_get(ii, &pppoe_info);
+			nircm->pppoe_rule.flow_pppoe_session_id = pppoe_info.pppoe_session_id;
+			memcpy(nircm->pppoe_rule.flow_pppoe_remote_mac, pppoe_info.remote_mac, ETH_ALEN);
+			nircm->valid_flags |= SFE_RULE_CREATE_PPPOE_DECAP_VALID;
+			nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+
+
+			DEBUG_TRACE("%px: PPPoE - session: %x, mac: %pM\n", nnpci,
+					nircm->pppoe_rule.flow_pppoe_session_id,
+					nircm->pppoe_rule.flow_pppoe_remote_mac);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", nnpci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", nnpci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_in_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_in_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_in_dev, pr->return_qos_tag);
+				dev_put(vlan_in_dev);
+				vlan_in_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.ingress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.ingress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= SFE_RULE_CREATE_VLAN_VALID;
+
+			if (sfe_is_l2_feature_enabled()) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_FROM, ECM_DB_IFACE_TYPE_VLAN);
+				if (is_valid_ether_addr(vlan_info.address)) {
+					ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, vlan_info.address);
+					nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_FLOW_VALID;
+					nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+				}
+			}
+			/*
+			 * If we have not yet got an ethernet mac then take this one (very unlikely as mac should have been propagated to the slave (outer) device
+			 */
+			memcpy(from_sfe_iface_address, vlan_info.address, ETH_ALEN);
+			if (is_valid_ether_addr(from_sfe_iface_address)) {
+				memcpy(nircm->conn_rule.flow_mac, from_sfe_iface_address, ETH_ALEN);
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", nnpci, from_sfe_iface_address);
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+			}
+
+			DEBUG_TRACE("%px: vlan tag: %x\n", nnpci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", nnpci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", nnpci);
+				break;
+			}
+
+			/*
+			 * TO DO: IPSEC ifnum in ecm_sfe_common is not implemented yet.
+			 */
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", nnpci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_LAG:
+#ifdef ECM_INTERFACE_BOND_ENABLE
+			if (sfe_is_l2_feature_enabled()) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+				/*
+				 * LAG device gets its stats by summing up all stats of its
+				 * slaves (i.e. 'ethx' devices). Please see bond_get_stats()
+				 * in linux-5.4/drivers/net/bonding/bond_main.c.
+				 * So no need to call feci->set_stats_bitmap().
+				 */
+
+				ecm_db_iface_lag_address_get(ii, from_sfe_iface_address);
+				if (is_valid_ether_addr(from_sfe_iface_address)) {
+					ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_sfe_iface_address);
+					nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_FLOW_VALID;
+					nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+				}
+				DEBUG_TRACE("%px: LAG - mac: %pM\n", nnpci, from_sfe_iface_address);
+			}
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: LAG - unsupported\n", nnpci);
+#endif
+			break;
+
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", nnpci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+
+	if (rule_invalid) {
+		DEBUG_WARN("%px: from/src Rule invalid\n", nnpci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * Now examine the TO / DEST heirarchy list to construct the destination part of the rule
+	 */
+	DEBUG_TRACE("%px: Examine to/dest heirarchy list\n", nnpci);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = to_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+		struct ecm_db_interface_info_pppoe pppoe_info;
+#endif
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_out_dev = NULL;
+#endif
+
+		ii = to_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px, type: %d (%s)\n", nnpci, list_index, ii, ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_BRIDGE, list_index, to_ifaces_first)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_TO, ECM_DB_IFACE_TYPE_BRIDGE);
+			}
+
+			ecm_db_iface_bridge_address_get(ii, to_sfe_iface_address);
+
+			if (is_valid_ether_addr(to_sfe_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_sfe_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+			}
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", nnpci, to_sfe_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", nnpci);
+				break;
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, to_sfe_iface_address);
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", nnpci, to_sfe_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", nnpci);
+				break;
+			}
+
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, to_sfe_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", nnpci, to_sfe_iface_address);
+			break;
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", nnpci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * Copy pppoe session info to the creation structure.
+			 */
+			ecm_db_iface_pppoe_session_info_get(ii, &pppoe_info);
+			nircm->pppoe_rule.return_pppoe_session_id = pppoe_info.pppoe_session_id;
+			memcpy(nircm->pppoe_rule.return_pppoe_remote_mac, pppoe_info.remote_mac, ETH_ALEN);
+			nircm->valid_flags |= SFE_RULE_CREATE_PPPOE_ENCAP_VALID;
+			nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+
+			DEBUG_TRACE("%px: PPPoE - session: %x, mac: %pM\n", nnpci,
+					nircm->pppoe_rule.return_pppoe_session_id,
+					nircm->pppoe_rule.return_pppoe_remote_mac);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", nnpci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", nnpci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_out_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_out_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_out_dev, pr->flow_qos_tag);
+				dev_put(vlan_out_dev);
+				vlan_out_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.egress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.egress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= SFE_RULE_CREATE_VLAN_VALID;
+
+			if (sfe_is_l2_feature_enabled()) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_TO, ECM_DB_IFACE_TYPE_VLAN);
+				if (is_valid_ether_addr(vlan_info.address)) {
+					ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, vlan_info.address);
+					nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_RETURN_VALID;
+					nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+				}
+			}
+			/*
+			 * If we have not yet got an ethernet mac then take this one (very unlikely as mac should have been propagated to the slave (outer) device
+			 */
+			memcpy(to_sfe_iface_address, vlan_info.address, ETH_ALEN);
+			if (is_valid_ether_addr(to_sfe_iface_address)) {
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", nnpci, to_sfe_iface_address);
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+				memcpy(nircm->conn_rule.return_mac, to_sfe_iface_address, ETH_ALEN);
+			}
+
+			DEBUG_TRACE("%px: vlan tag: %x\n", nnpci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", nnpci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", nnpci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", nnpci);
+				break;
+			}
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", nnpci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_LAG:
+#ifdef ECM_INTERFACE_BOND_ENABLE
+			if (sfe_is_l2_feature_enabled()) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+				/*
+				 * LAG device gets its stats by summing up all stats of its
+				 * slaves (i.e. 'ethx' devices). Please see bond_get_stats()
+				 * in linux-5.4/drivers/net/bonding/bond_main.c.
+				 * So no need to call feci->set_stats_bitmap().
+				 */
+
+				ecm_db_iface_lag_address_get(ii, to_sfe_iface_address);
+				if (is_valid_ether_addr(to_sfe_iface_address)) {
+					ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_sfe_iface_address);
+					nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_RETURN_VALID;
+					nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+				}
+				DEBUG_TRACE("%px: LAG - mac: %pM\n", nnpci, to_sfe_iface_address);
+			}
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: LAG - unsupported\n", nnpci);
+#endif
+			break;
+
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", nnpci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+
+	if (rule_invalid) {
+		DEBUG_WARN("%px: to/dest Rule invalid\n", nnpci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto non_ported_accel_bad_rule;
+	}
+
+	/*
+	 * Routed or bridged?
+	 */
+	if (ecm_db_connection_is_routed_get(feci->ci)) {
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_ROUTED;
+	} else {
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_BRIDGE_FLOW;
+		if (is_l2_encap) {
+			nircm->rule_flags |= SFE_RULE_CREATE_FLAG_L2_ENCAP;
+		}
+	}
+
+	/*
+	 * TODO: Add the src interface check flag here.
+	 */
+	if (ecm_interface_src_check || ecm_db_connection_is_pppoe_bridged_get(feci->ci)) {
+		DEBUG_INFO("%px: Source interface check flag is enabled\n", nnpci);
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_FLOW_SRC_INTERFACE_CHECK;
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_RETURN_SRC_INTERFACE_CHECK;
+	}
+
+	/*
+	 * Set up the flow and return qos tags
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+		nircm->qos_rule.flow_qos_tag = (uint32_t)pr->flow_qos_tag;
+		nircm->qos_rule.return_qos_tag = (uint32_t)pr->return_qos_tag;
+		nircm->valid_flags |= SFE_RULE_CREATE_QOS_VALID;
+	}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+	/*
+	 * DSCP information?
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+		nircm->dscp_rule.flow_dscp = pr->flow_dscp;
+		nircm->dscp_rule.return_dscp = pr->return_dscp;
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_DSCP_MARKING;
+		nircm->valid_flags |= SFE_RULE_CREATE_DSCP_MARKING_VALID;
+	}
+
+	/*
+	 * Set up the flow and return mark.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_MARK) {
+		nircm->mark_rule.flow_mark = (uint32_t)pr->flow_mark;
+		nircm->mark_rule.return_mark = (uint32_t)pr->return_mark;
+		nircm->valid_flags |= SFE_RULE_CREATE_MARK_VALID;
+	}
+#endif
+	/*
+	 * Set protocol
+	 */
+	nircm->tuple.protocol = (int32_t)ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * The flow_ip is where the connection established from
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	ECM_IP_ADDR_TO_SFE_IPV6_ADDR(nircm->tuple.flow_ip, src_ip);
+
+	/*
+	 * The return_ip is where the connection is established to
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, dest_ip);
+	ECM_IP_ADDR_TO_SFE_IPV6_ADDR(nircm->tuple.return_ip, dest_ip);
+
+	/*
+	 * Same approach as above for port information
+	 */
+	nircm->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nircm->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT);
+
+	/*
+	 * Get mac addresses.
+	 * The src_mac is the mac address of the node that established the connection.
+	 * This will work whether the from_node is LAN (egress) or WAN (ingress).
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, (uint8_t *)nircm->conn_rule.flow_mac);
+
+	/*
+	 * The dest_mac is the mac address of the node that the connection is esatblished to.
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, (uint8_t *)nircm->conn_rule.return_mac);
+
+	/*
+	 * Sync our creation command from the assigned classifiers to get specific additional creation rules.
+	 * NOTE: These are called in ascending order of priority and so the last classifier (highest) shall
+	 * override any preceding classifiers.
+	 * This also gives the classifiers a chance to see that acceleration is being attempted.
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(feci->ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+		struct ecm_classifier_rule_create ecrc;
+		/*
+		 * NOTE: The current classifiers do not sync anything to the underlying accel engines.
+		 * In the future, if any of the classifiers wants to pass any parameter, these parameters
+		 * should be received via this object and copied to the accel engine's create object (nircm).
+		*/
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: sync from: %px, type: %d\n", nnpci, aci, aci->type_get(aci));
+		aci->sync_from_v6(aci, &ecrc);
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Release the interface lists
+	 */
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+	ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+
+	DEBUG_INFO("%px: NON_PORTED Accelerate connection %px\n"
+			"Protocol: %d\n"
+			"from_mtu: %u\n"
+			"to_mtu: %u\n"
+			"from_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"to_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"from_mac: %pM\n"
+			"to_mac: %pM\n"
+			"src_iface_num: %u\n"
+			"dest_iface_num: %u\n"
+			"ingress_inner_vlan_tag: %u\n"
+			"egress_inner_vlan_tag: %u\n"
+			"ingress_outer_vlan_tag: %u\n"
+			"egress_outer_vlan_tag: %u\n"
+			"rule_flags: %x\n"
+			"valid_flags: %x\n"
+			"flow_qos_tag: %x (%u)\n"
+			"return_qos_tag: %x (%u)\n"
+			"flow_dscp: %x\n"
+			"return_dscp: %x\n"
+			"flow_mark: %x\n"
+			"return_mark: %x\n",
+			nnpci,
+			feci->ci,
+			nircm->tuple.protocol,
+			nircm->conn_rule.flow_mtu,
+			nircm->conn_rule.return_mtu,
+			ECM_IP_ADDR_TO_OCTAL(src_ip), nircm->tuple.flow_ident,
+			ECM_IP_ADDR_TO_OCTAL(dest_ip), nircm->tuple.return_ident,
+			nircm->conn_rule.flow_mac,
+			nircm->conn_rule.return_mac,
+			nircm->conn_rule.flow_interface_num,
+			nircm->conn_rule.return_interface_num,
+			nircm->vlan_primary_rule.ingress_vlan_tag,
+			nircm->vlan_primary_rule.egress_vlan_tag,
+			nircm->vlan_secondary_rule.ingress_vlan_tag,
+			nircm->vlan_secondary_rule.egress_vlan_tag,
+			nircm->rule_flags,
+			nircm->valid_flags,
+			nircm->qos_rule.flow_qos_tag, nircm->qos_rule.flow_qos_tag,
+			nircm->qos_rule.return_qos_tag, nircm->qos_rule.return_qos_tag,
+			nircm->dscp_rule.flow_dscp,
+			nircm->dscp_rule.return_dscp,
+			nircm->mark_rule.flow_mark,
+			nircm->mark_rule.return_mark);
+
+	/*
+	 * Now that the rule has been constructed we re-compare the generation occurrance counter.
+	 * If there has been a change then we abort because the rule may have been created using
+	 * unstable data - especially if another thread has begun regeneration of the connection state.
+	 * NOTE: This does not prevent a regen from being flagged immediately after this line of code either,
+	 * or while the acceleration rule is in flight to the sfe.
+	 * This is only to check for consistency of rule state - not that the state is stale.
+	 * Remember that the connection is marked as "accel pending state" so if a regen is flagged immediately
+	 * after this check passes, the connection will be decelerated and refreshed very quickly.
+	 */
+	if (regen_occurrances != ecm_db_connection_regeneration_occurrances_get(feci->ci)) {
+		DEBUG_INFO("%px: connection:%px regen occurred - aborting accel rule.\n", feci, feci->ci);
+		ecm_sfe_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		kfree(nim);
+		return;
+	}
+
+	/*
+	 * Ref the connection before issuing an SFE rule
+	 * This ensures that when the SFE responds to the command - which may even be immediately -
+	 * the callback function can trust the correct ref was taken for its purpose.
+	 * NOTE: remember that this will also implicitly hold the feci.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Call the rule create function
+	 */
+	sfe_tx_status = sfe_ipv6_tx(ecm_sfe_ipv6_mgr, nim);
+	if (sfe_tx_status == SFE_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;
+		spin_unlock_bh(&feci->lock);
+		kfree(nim);
+		return;
+	}
+
+	kfree(nim);
+
+	/*
+	 * Release that ref!
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * TX failed
+	 */
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Accel mode unexpected: %d\n", nnpci, feci->accel_mode);
+	feci->stats.driver_fail_total++;
+	feci->stats.driver_fail++;
+	if (feci->stats.driver_fail >= feci->stats.driver_fail_limit) {
+		DEBUG_WARN("%px: Accel failed - driver fail limit\n", nnpci);
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DRIVER;
+	} else {
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	_ecm_sfe_ipv6_accel_pending_clear(feci, result_mode);
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+	spin_unlock_bh(&feci->lock);
+	return;
+
+non_ported_accel_bad_rule:
+	;
+
+	kfree(nim);
+	/*
+	 * Jump to here when rule data is bad and an offload command cannot be constructed
+	 */
+	DEBUG_WARN("%px: Accel failed - bad rule\n", nnpci);
+	ecm_sfe_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_FAIL_RULE);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv6_connection_destroy_callback()
+ *	Callback for handling destroy ack/nack calls.
+ */
+static void ecm_sfe_non_ported_ipv6_connection_destroy_callback(void *app_data, struct sfe_ipv6_msg *nim)
+{
+	struct sfe_ipv6_rule_destroy_msg *nirdm = &nim->msg.rule_destroy;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_sfe_non_ported_ipv6_connection_instance *nnpci;
+	ip_addr_t flow_ip;
+	ip_addr_t return_ip;
+
+	/*
+	 * Is this a response to a destroy message?
+	 */
+	if (nim->cm.type != SFE_TX_DESTROY_RULE_MSG) {
+		DEBUG_ERROR("%px: non_ported destroy callback with improper type: %d\n", nim, nim->cm.type);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: destroy callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	nnpci = (struct ecm_sfe_non_ported_ipv6_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	ECM_SFE_IPV6_ADDR_TO_IP_ADDR(flow_ip, nirdm->tuple.flow_ip);
+	ECM_SFE_IPV6_ADDR_TO_IP_ADDR(return_ip, nirdm->tuple.return_ip);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_sfe_ipv6_decel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: decelerate response for connection: %px\n", nnpci, feci->ci);
+	DEBUG_TRACE("%px: flow_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", nnpci, ECM_IP_ADDR_TO_OCTAL(flow_ip), nirdm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", nnpci, ECM_IP_ADDR_TO_OCTAL(return_ip), nirdm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", nnpci, nirdm->tuple.protocol);
+
+	/*
+	 * Drop decel pending counter
+	 */
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	ecm_sfe_ipv6_pending_decel_count--;
+	DEBUG_ASSERT(ecm_sfe_ipv6_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If decel is not still pending then it's possible that the SFE ended acceleration by some other reason e.g. flush
+	 * In which case we cannot rely on the response we get here.
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING) {
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connections.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_TRACE("%px: response: %d\n", nnpci, nim->cm.response);
+	if (nim->cm.response != SFE_CMN_RESPONSE_ACK) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DECEL;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	/*
+	 * If connection became defunct then set mode so that no further accel/decel attempts occur.
+	 */
+	if (feci->is_defunct) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT_SHORT;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * NON_PORTED acceleration ends
+	 */
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	ecm_sfe_non_ported_ipv6_accelerated_count--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_sfe_non_ported_ipv6_accelerated_count >= 0, "Bad non_ported accel counter\n");
+	ecm_sfe_ipv6_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_sfe_ipv6_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+	/*
+	 * Release the connections.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv6_connection_decelerate_msg_send()
+ *	Prepares and sends a decelerate message to acceleration engine.
+ */
+static bool ecm_sfe_non_ported_ipv6_connection_decelerate_msg_send(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_non_ported_ipv6_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv6_connection_instance *)feci;
+	struct sfe_ipv6_msg nim;
+	struct sfe_ipv6_rule_destroy_msg *nirdm;
+	ip_addr_t src_ip;
+	ip_addr_t dest_ip;
+	sfe_tx_status_t sfe_tx_status;
+	bool ret;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	/*
+	 * Increment the decel pending counter
+	 */
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	ecm_sfe_ipv6_pending_decel_count++;
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+	/*
+	 * Prepare deceleration message
+	 */
+	sfe_ipv6_msg_init(&nim, SFE_SPECIAL_INTERFACE_IPV6, SFE_TX_DESTROY_RULE_MSG,
+			sizeof(struct sfe_ipv6_rule_destroy_msg),
+			ecm_sfe_non_ported_ipv6_connection_destroy_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nirdm = &nim.msg.rule_destroy;
+	nirdm->tuple.protocol = (int32_t)ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * Get addressing information
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	ECM_IP_ADDR_TO_SFE_IPV6_ADDR(nirdm->tuple.flow_ip, src_ip);
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, dest_ip);
+	ECM_IP_ADDR_TO_SFE_IPV6_ADDR(nirdm->tuple.return_ip, dest_ip);
+	nirdm->tuple.flow_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nirdm->tuple.return_ident = ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT);
+
+	DEBUG_INFO("%px: NON_PORTED Connection %px decelerate\n"
+			"src_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"dest_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n",
+			nnpci, feci->ci,
+			ECM_IP_ADDR_TO_OCTAL(src_ip), nirdm->tuple.flow_ident,
+			ECM_IP_ADDR_TO_OCTAL(dest_ip), nirdm->tuple.return_ident);
+
+	/*
+	 * Take a ref to the feci->ci so that it will persist until we get a response from the SFE.
+	 * NOTE: This will implicitly hold the feci too.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Destroy the SFE connection cache entry.
+	 */
+	sfe_tx_status = sfe_ipv6_tx(ecm_sfe_ipv6_mgr, &nim);
+	if (sfe_tx_status == SFE_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;
+		spin_unlock_bh(&feci->lock);
+		return true;
+	}
+
+	/*
+	 * TX failed
+	 */
+	ret = ecm_front_end_destroy_failure_handle(feci);
+
+	/*
+	 * Release the ref take, SFE driver did not accept our command.
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * Could not send the request, decrement the decel pending counter
+	 */
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	ecm_sfe_ipv6_pending_decel_count--;
+	DEBUG_ASSERT(ecm_sfe_ipv6_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+	return ret;
+}
+
+/*
+ * ecm_sfe_non_ported_ipv6_connection_decelerate()
+ *     Decelerate a connection
+ */
+static bool ecm_sfe_non_ported_ipv6_connection_decelerate(struct ecm_front_end_connection_instance *feci)
+{
+	/*
+	 * Check if accel mode is OK for the deceleration.
+	 */
+	spin_lock_bh(&feci->lock);
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	return ecm_sfe_non_ported_ipv6_connection_decelerate_msg_send(feci);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv6_connection_defunct_callback()
+ *	Callback to be called when a non-ported connection has become defunct.
+ */
+bool ecm_sfe_non_ported_ipv6_connection_defunct_callback(void *arg, int *accel_mode)
+{
+	bool ret;
+	struct ecm_front_end_connection_instance *feci = (struct ecm_front_end_connection_instance *)arg;
+	struct ecm_sfe_non_ported_ipv6_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	spin_lock_bh(&feci->lock);
+	/*
+	 * Check if the connection can be defuncted.
+	 */
+	if (!ecm_front_end_common_connection_defunct_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+
+	/*
+	 * If none of the cases matched above, this means the connection is in the
+	 * accel mode, so we force a deceleration.
+	 * NOTE: If the mode is accel pending then the decel will be actioned when that is completed.
+	 */
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	ret = ecm_sfe_non_ported_ipv6_connection_decelerate_msg_send(feci);
+
+	/*
+	 * Copy the accel_mode which is returned from the decelerate message function. This value
+	 * will be used in the caller to decide releasing the final reference of the connection.
+	 * But if this function reaches to here, the caller care about the ret. If ret is true,
+	 * the reference will be released regardless of the accel_mode. If ret is false, accel_mode
+	 * will be in the ACCEL state (for destroy re-try) and this state will not be used in the
+	 * caller's decision. It looks for ACCEL_FAIL states.
+	 */
+	spin_lock_bh(&feci->lock);
+	*accel_mode = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+
+	return ret;
+}
+
+/*
+ * ecm_sfe_non_ported_ipv6_connection_accel_state_get()
+ *	Get acceleration state
+ */
+static ecm_front_end_acceleration_mode_t ecm_sfe_non_ported_ipv6_connection_accel_state_get(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_non_ported_ipv6_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv6_connection_instance *)feci;
+	ecm_front_end_acceleration_mode_t state;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	spin_lock_bh(&feci->lock);
+	state = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+	return state;
+}
+
+/*
+ * ecm_sfe_non_ported_ipv6_connection_action_seen()
+ *	Acceleration action / activity has been seen for this connection.
+ *
+ * NOTE: Call the action_seen() method when the SFE has demonstrated that it has offloaded some data for a connection.
+ */
+static void ecm_sfe_non_ported_ipv6_connection_action_seen(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_non_ported_ipv6_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	DEBUG_INFO("%px: Action seen\n", nnpci);
+	spin_lock_bh(&feci->lock);
+	feci->stats.no_action_seen = 0;
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv6_connection_accel_ceased()
+ *	SFE has indicated that acceleration has stopped.
+ *
+ * NOTE: This is called in response to an SFE self-initiated termination of acceleration.
+ * This must NOT be called because the ECM terminated the acceleration.
+ */
+static void ecm_sfe_non_ported_ipv6_connection_accel_ceased(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_non_ported_ipv6_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	DEBUG_INFO("%px: accel ceased\n", nnpci);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If we are in accel-pending state then the SFE has issued a flush out-of-order
+	 * with the ACK/NACK we are actually waiting for.
+	 * To work around this we record a "flush has already happened" and will action it when we finally get that ACK/NACK.
+	 * GGG TODO This should eventually be removed when the SFE honours messaging sequence.
+	 */
+	if (feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING) {
+		feci->stats.flush_happened = true;
+		feci->stats.flush_happened_total++;
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If connection is no longer accelerated by the time we get here just ignore the command
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_ACCEL) {
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If the no_action_seen counter was not reset then acceleration ended without any offload action
+	 */
+	if (feci->stats.no_action_seen) {
+		feci->stats.no_action_seen_total++;
+	}
+
+	/*
+	 * If the no_action_seen indicates successive cessations of acceleration without any offload action occuring
+	 * then we fail out this connection
+	 */
+	if (feci->stats.no_action_seen >= feci->stats.no_action_seen_limit) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_NO_ACTION;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Non-Ported acceleration ends
+	 */
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	ecm_sfe_non_ported_ipv6_accelerated_count--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_sfe_non_ported_ipv6_accelerated_count >= 0, "Bad non-ported accel counter\n");
+	ecm_sfe_ipv6_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_sfe_ipv6_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv6_connection_ref()
+ *	Ref a connection front end instance
+ */
+static void ecm_sfe_non_ported_ipv6_connection_ref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_non_ported_ipv6_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+	spin_lock_bh(&feci->lock);
+	feci->refs++;
+	DEBUG_TRACE("%px: nnpci ref %d\n", nnpci, feci->refs);
+	DEBUG_ASSERT(feci->refs > 0, "%px: ref wrap\n", nnpci);
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_sfe_non_ported_ipv6_connection_deref()
+ *	Deref a connection front end instance
+ */
+static int ecm_sfe_non_ported_ipv6_connection_deref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_non_ported_ipv6_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	spin_lock_bh(&feci->lock);
+	feci->refs--;
+	DEBUG_ASSERT(feci->refs >= 0, "%px: ref wrap\n", nnpci);
+
+	if (feci->refs > 0) {
+		int refs = feci->refs;
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: nnpci deref %d\n", nnpci, refs);
+		return refs;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * We can now destroy the instance
+	 */
+	DEBUG_TRACE("%px: nnpci final\n", nnpci);
+	DEBUG_CLEAR_MAGIC(nnpci);
+	kfree(nnpci);
+
+	return 0;
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_sfe_non_ported_ipv6_connection_state_get()
+ *	Return the state of this Non ported front end instance
+ */
+static int ecm_sfe_non_ported_ipv6_connection_state_get(struct ecm_front_end_connection_instance *feci, struct ecm_state_file_instance *sfi)
+{
+	struct ecm_sfe_non_ported_ipv6_connection_instance *nnpci = (struct ecm_sfe_non_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", nnpci);
+
+	return ecm_front_end_common_connection_state_get(feci, sfi, "sfe_v6.non_ported");
+}
+#endif
+
+/*
+ * ecm_sfe_non_ported_ipv6_connection_instance_alloc()
+ *	Create a front end instance specific for non-ported connection
+ */
+struct ecm_sfe_non_ported_ipv6_connection_instance *ecm_sfe_non_ported_ipv6_connection_instance_alloc(bool can_accel,
+								int protocol,
+								struct ecm_db_connection_instance **nci)
+{
+	struct ecm_sfe_non_ported_ipv6_connection_instance *nnpci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_db_connection_instance *ci;
+
+	if (ecm_sfe_ipv6_is_conn_limit_reached()) {
+		DEBUG_TRACE("Reached connection limit\n");
+		return NULL;
+	}
+
+	/*
+	 * Now allocate the new connection
+	 */
+	*nci = ecm_db_connection_alloc();
+	if (!*nci) {
+		DEBUG_WARN("Failed to allocate connection\n");
+		return NULL;
+	}
+
+	ci = *nci;
+
+	nnpci = (struct ecm_sfe_non_ported_ipv6_connection_instance *)kzalloc(sizeof(struct ecm_sfe_non_ported_ipv6_connection_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!nnpci) {
+		DEBUG_WARN("Non-Ported Front end alloc failed\n");
+		ecm_db_connection_deref(ci);
+		return NULL;
+	}
+
+	/*
+	 * Refs is 1 for the creator of the connection
+	 */
+	feci = (struct ecm_front_end_connection_instance *)nnpci;
+	feci->refs = 1;
+	DEBUG_SET_MAGIC(nnpci, ECM_SFE_NON_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC);
+	spin_lock_init(&feci->lock);
+
+	feci->can_accel = can_accel;
+	feci->accel_mode = (can_accel) ? ECM_FRONT_END_ACCELERATION_MODE_DECEL : ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED;
+	feci->accel_engine = ECM_FRONT_END_ENGINE_SFE;
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	feci->stats.no_action_seen_limit = ecm_sfe_ipv6_no_action_limit_default;
+	feci->stats.driver_fail_limit = ecm_sfe_ipv6_driver_fail_limit_default;
+	feci->stats.ae_nack_limit = ecm_sfe_ipv6_nack_limit_default;
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+	/*
+	 * Copy reference to connection - no need to ref ci as ci maintains a ref to this instance instead (this instance persists for as long as ci does)
+	 */
+	feci->ci = ci;
+
+	feci->ip_version = 6;
+
+	feci->protocol = protocol;
+
+	/*
+	 * Populate the methods and callbacks
+	 */
+	feci->ref = ecm_sfe_non_ported_ipv6_connection_ref;
+	feci->deref = ecm_sfe_non_ported_ipv6_connection_deref;
+	feci->accelerate = ecm_sfe_non_ported_ipv6_connection_accelerate;
+	feci->decelerate = ecm_sfe_non_ported_ipv6_connection_decelerate;
+	feci->accel_state_get = ecm_sfe_non_ported_ipv6_connection_accel_state_get;
+	feci->action_seen = ecm_sfe_non_ported_ipv6_connection_action_seen;
+	feci->accel_ceased = ecm_sfe_non_ported_ipv6_connection_accel_ceased;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	feci->state_get = ecm_sfe_non_ported_ipv6_connection_state_get;
+#endif
+	feci->ae_interface_number_by_dev_get = ecm_sfe_common_get_interface_number_by_dev;
+	feci->ae_interface_number_by_dev_type_get = ecm_sfe_common_get_interface_number_by_dev_type;
+	feci->ae_interface_type_get = ecm_sfe_common_get_interface_type;
+	feci->regenerate = ecm_sfe_common_connection_regenerate;
+
+	ecm_sfe_common_init_fe_info(&nnpci->fe_info);
+
+	feci->get_stats_bitmap = ecm_sfe_non_ported_ipv6_get_stats_bitmap;
+	feci->set_stats_bitmap = ecm_sfe_non_ported_ipv6_set_stats_bitmap;
+	feci->update_rule = ecm_sfe_common_update_rule;
+
+
+	return nnpci;
+}
+
+/*
+ * ecm_sfe_non_ported_ipv6_debugfs_init()
+ */
+bool ecm_sfe_non_ported_ipv6_debugfs_init(struct dentry *dentry)
+{
+	if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry,
+					(u32 *)&ecm_sfe_non_ported_ipv6_accelerated_count)) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv6 non_ported_accelerated_count file in debugfs\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-ecm/frontends/sfe/ecm_sfe_non_ported_ipv6.h b/qca-nss-ecm/frontends/sfe/ecm_sfe_non_ported_ipv6.h
new file mode 100644
index 0000000..2179dea
--- /dev/null
+++ b/qca-nss-ecm/frontends/sfe/ecm_sfe_non_ported_ipv6.h
@@ -0,0 +1,24 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015 The Linux Foundation.  All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern bool ecm_sfe_non_ported_ipv6_debugfs_init(struct dentry *dentry);
+
+struct ecm_sfe_non_ported_ipv6_connection_instance *ecm_sfe_non_ported_ipv6_connection_instance_alloc(bool can_accel,
+								int protocol,
+								struct ecm_db_connection_instance **nci);
+extern bool ecm_sfe_non_ported_ipv6_connection_defunct_callback(void *arg, int *accel_mode);
diff --git a/qca-nss-ecm/frontends/sfe/ecm_sfe_ported_ipv4.c b/qca-nss-ecm/frontends/sfe/ecm_sfe_ported_ipv4.c
new file mode 100644
index 0000000..c3f5d73
--- /dev/null
+++ b/qca-nss-ecm/frontends/sfe/ecm_sfe_ported_ipv4.c
@@ -0,0 +1,2135 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/debugfs.h>
+#include <linux/string.h>
+#include <net/route.h>
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
+#include <net/netfilter/ipv4/nf_defrag_ipv4.h>
+#include <linux/netfilter/nf_conntrack_tftp.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_SFE_PORTED_IPV4_DEBUG_LEVEL
+
+#include <sfe_api.h>
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#include "ecm_sfe_ported_ipv4.h"
+#include "ecm_sfe_ipv4.h"
+#include "ecm_sfe_common.h"
+#include "ecm_front_end_common.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_SFE_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC 0xED56
+
+/*
+ * Protocol type that ported file supports.
+ */
+enum ecm_sfe_ported_ipv4_proto_types {
+	ECM_SFE_PORTED_IPV4_PROTO_TCP = 0,
+	ECM_SFE_PORTED_IPV4_PROTO_UDP,
+	ECM_SFE_PORTED_IPV4_PROTO_MAX
+
+};
+
+/*
+ * struct ecm_sfe_ipv4_ported_connection_instance
+ *	A connection specific front end instance for PORTED connections
+ */
+struct ecm_sfe_ported_ipv4_connection_instance {
+	struct ecm_front_end_connection_instance base;		/* Base class */
+	uint8_t ported_accelerated_count_index;			/* Index value of accelerated count array (UDP or TCP) */
+#ifdef CONFIG_XFRM
+	enum ecm_sfe_ipsec_state flow_ipsec_state;	/* Flow traffic need ipsec process or not */
+	enum ecm_sfe_ipsec_state return_ipsec_state;	/* Return traffic need ipsec process or not */
+#endif
+	struct ecm_sfe_common_fe_info fe_info;		/* Front end information */
+
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+static int ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_MAX] = {0};
+						/* Array of Number of TCP and UDP connections currently offloaded */
+
+/*
+ * Expose what should be a static flag in the TCP connection tracker.
+ */
+#ifdef ECM_OPENWRT_SUPPORT
+extern int nf_ct_tcp_no_window_check;
+#endif
+extern int nf_ct_tcp_be_liberal;
+
+/*
+ * ecm_sfe_ported_ipv4_get_stats_bitmap()
+ *	Get bit map
+ */
+static uint32_t ecm_sfe_ported_ipv4_get_stats_bitmap(struct ecm_front_end_connection_instance *feci, ecm_db_obj_dir_t dir)
+{
+	struct ecm_sfe_ported_ipv4_connection_instance *npci = (struct ecm_sfe_ported_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	return ecm_sfe_common_get_stats_bitmap(&npci->fe_info, dir);
+}
+
+/*
+ * ecm_sfe_ported_ipv4_set_stats_bitmap()
+ *	Set bit map
+ */
+static void ecm_sfe_ported_ipv4_set_stats_bitmap(struct ecm_front_end_connection_instance *feci, ecm_db_obj_dir_t dir, uint8_t bit)
+{
+	struct ecm_sfe_ported_ipv4_connection_instance *npci = (struct ecm_sfe_ported_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	ecm_sfe_common_set_stats_bitmap(&npci->fe_info, dir, bit);
+}
+
+/*
+ * ecm_sfe_ported_ipv4_connection_callback()
+ *	Callback for handling create ack/nack calls.
+ */
+static void ecm_sfe_ported_ipv4_connection_callback(void *app_data, struct sfe_ipv4_msg *nim)
+{
+	struct sfe_ipv4_rule_create_msg * __attribute__((unused)) nircm = &nim->msg.rule_create;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_sfe_ported_ipv4_connection_instance *npci;
+	ecm_front_end_acceleration_mode_t result_mode;
+	bool is_defunct = false;
+
+	/*
+	 * Is this a response to a create message?
+	 */
+	if (nim->cm.type != SFE_TX_CREATE_RULE_MSG) {
+		DEBUG_ERROR("%px: ported create callback with improper type: %d, serial: %u\n", nim, nim->cm.type, serial);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: create callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	npci = (struct ecm_sfe_ported_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_sfe_ipv4_accel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: accelerate response for connection: %px, serial: %u\n", npci, feci->ci, serial);
+	DEBUG_TRACE("%px: rule_flags: %x, valid_flags: %x\n", npci, nircm->rule_flags, nircm->valid_flags);
+	DEBUG_TRACE("%px: flow_ip: %pI4n:%d\n", npci, &nircm->tuple.flow_ip, nircm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: %pI4n:%d\n", npci, &nircm->tuple.return_ip, nircm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", npci, nircm->tuple.protocol);
+
+	/*
+	 * Handle the creation result code.
+	 */
+	DEBUG_TRACE("%px: response: %d\n", npci, nim->cm.response);
+	if (nim->cm.response != SFE_CMN_RESPONSE_ACK) {
+		/*
+		 * Creation command failed (specific reason ignored).
+		 */
+		DEBUG_TRACE("%px: accel nack: %d\n", npci, nim->cm.error);
+		spin_lock_bh(&feci->lock);
+		DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+		feci->stats.ae_nack++;
+		feci->stats.ae_nack_total++;
+		if (feci->stats.ae_nack >= feci->stats.ae_nack_limit) {
+			/*
+			 * Too many SFE rejections
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_ACCEL_ENGINE;
+		} else {
+			/*
+			 * Revert to decelerated
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+		}
+
+		/*
+		 * If connection is now defunct then set mode to ensure no further accel attempts occur
+		 */
+		if (feci->is_defunct) {
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT;
+		}
+
+		spin_lock_bh(&ecm_sfe_ipv4_lock);
+		_ecm_sfe_ipv4_accel_pending_clear(feci, result_mode);
+		spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+
+	/*
+	 * If a flush occured before we got the ACK then our acceleration was effectively cancelled on us
+	 * GGG TODO This is a workaround for a SFE message OOO quirk, this should eventually be removed.
+	 */
+	if (feci->stats.flush_happened) {
+		feci->stats.flush_happened = false;
+
+		/*
+		 * Increment the no-action counter.  Our connection was decelerated on us with no action occurring.
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_lock_bh(&ecm_sfe_ipv4_lock);
+		_ecm_sfe_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	/*
+	 * Create succeeded
+	 */
+
+	/*
+	 * Clear any nack count
+	 */
+	feci->stats.ae_nack = 0;
+
+	/*
+	 * Clear the "accelerate pending" state and move to "accelerated" state bumping
+	 * the accelerated counters to match our new state.
+	 *
+	 * Decelerate may have been attempted while we were "pending accel" and
+	 * this function will return true if that was the case.
+	 * If decelerate was pending then we need to begin deceleration :-(
+	 */
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+
+	ecm_sfe_ported_ipv4_accelerated_count[npci->ported_accelerated_count_index]++;	/* Protocol specific counter */
+	ecm_sfe_ipv4_accelerated_count++;		/* General running counter */
+
+	if (!_ecm_sfe_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_ACCEL)) {
+		/*
+		 * Increment the no-action counter, this is reset if offload action is seen
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_unlock_bh(&ecm_sfe_ipv4_lock);
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_INFO("%px: Decelerate was pending\n", ci);
+
+	/*
+	 * Check if the pending decelerate was done with the defunct process.
+	 * If it was, set the is_defunct flag of the feci to false for re-try.
+	 */
+	if (feci->is_defunct) {
+		is_defunct = feci->is_defunct;
+		feci->is_defunct = false;
+	}
+
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * If the pending decelerate was done through defunct process, we should
+	 * re-try it here with the same defunct function, because the purpose of that
+	 * process is to remove the connection from the database as well after decelerating it.
+	 */
+	if (is_defunct) {
+		ecm_db_connection_make_defunct(ci);
+	} else {
+		feci->decelerate(feci);
+	}
+
+	/*
+	 * Release the connection.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_sfe_ipv4_fast_xmit_set()
+ *	set the fast_xmit in the create message
+ */
+static void ecm_sfe_ipv4_fast_xmit_set(struct sfe_ipv4_rule_create_msg *msg)
+{
+	s32 interface_num;
+
+	rcu_read_lock_bh();
+
+	interface_num = msg->conn_rule.flow_top_interface_num;
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE) {
+		interface_num = msg->conn_rule.flow_interface_num;
+	}
+	if (ecm_sfe_common_fast_xmit_check(interface_num)) {
+		msg->rule_flags |= SFE_RULE_CREATE_FLAG_RETURN_TRANSMIT_FAST;
+	}
+
+	interface_num = msg->conn_rule.return_top_interface_num;
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE) {
+		interface_num = msg->conn_rule.return_interface_num;
+	}
+	if (ecm_sfe_common_fast_xmit_check(interface_num)) {
+		msg->rule_flags |= SFE_RULE_CREATE_FLAG_FLOW_TRANSMIT_FAST;
+	}
+
+	rcu_read_unlock_bh();
+}
+
+/*
+ * ecm_sfe_ported_ipv4_connection_accelerate()
+ *	Accelerate a connection
+ */
+static void ecm_sfe_ported_ipv4_connection_accelerate(struct ecm_front_end_connection_instance *feci,
+									struct ecm_classifier_process_response *pr, bool is_l2_encap,
+									struct nf_conn *ct, struct sk_buff *skb)
+{
+	struct ecm_sfe_ported_ipv4_connection_instance *npci = (struct ecm_sfe_ported_ipv4_connection_instance *)feci;
+	uint16_t regen_occurrances;
+	int protocol;
+	int32_t from_ifaces_first;
+	int32_t to_ifaces_first;
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *from_sfe_iface;
+	struct ecm_db_iface_instance *to_sfe_iface;
+	int32_t from_sfe_iface_id;
+	int32_t to_sfe_iface_id;
+	uint8_t from_sfe_iface_address[ETH_ALEN];
+	uint8_t to_sfe_iface_address[ETH_ALEN];
+	ip_addr_t addr;
+	struct sfe_ipv4_msg nim;
+	struct sfe_ipv4_rule_create_msg *nircm;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	sfe_tx_status_t sfe_tx_status;
+	int32_t list_index;
+	int32_t interface_type_counts[ECM_DB_IFACE_TYPE_COUNT];
+	bool rule_invalid;
+	uint8_t dest_mac_xlate[ETH_ALEN];
+	ecm_db_direction_t ecm_dir;
+	ecm_front_end_acceleration_mode_t result_mode;
+	uint32_t l2_accel_bits = (ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED | ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED);
+	ecm_sfe_common_l2_accel_check_callback_t l2_accel_check;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	/*
+	 * Get the re-generation occurrance counter of the connection.
+	 * We compare it again at the end - to ensure that the rule construction has seen no generation
+	 * changes during rule creation.
+	 */
+	regen_occurrances = ecm_db_connection_regeneration_occurrances_get(feci->ci);
+
+	/*
+	 * Test if acceleration is permitted
+	 */
+	if (!ecm_sfe_ipv4_accel_pending_set(feci)) {
+		DEBUG_TRACE("%px: Acceleration not permitted: %px skb=%px\n", feci, feci->ci, skb);
+		return;
+	}
+
+	/*
+	 * Okay construct an accel command.
+	 * Initialise creation structure.
+	 * NOTE: We leverage the app_data void pointer to be our 32 bit connection serial number.
+	 * When we get it back we re-cast it to a uint32 and do a faster connection lookup.
+	 */
+	memset(&nim, 0, sizeof(struct sfe_ipv4_msg));
+	sfe_ipv4_msg_init(&nim, SFE_SPECIAL_INTERFACE_IPV4, SFE_TX_CREATE_RULE_MSG,
+			sizeof(struct sfe_ipv4_rule_create_msg),
+			ecm_sfe_ported_ipv4_connection_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nircm = &nim.msg.rule_create;
+	nircm->valid_flags = 0;
+	nircm->rule_flags = 0;
+
+	/*
+	 * Initialize VLAN tag information
+	 */
+	nircm->vlan_primary_rule.ingress_vlan_tag = SFE_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_primary_rule.egress_vlan_tag = SFE_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.ingress_vlan_tag = SFE_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.egress_vlan_tag = SFE_VLAN_ID_NOT_CONFIGURED;
+
+	/*
+	 * Get the interface lists of the connection, we must have at least one interface in the list to continue
+	 */
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in from_interfaces list!\n", feci);
+		goto ported_accel_bad_rule;
+	}
+
+	to_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, to_ifaces, ECM_DB_OBJ_DIR_TO);
+	if (to_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in to_interfaces list!\n", npci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * First interface in each must be a known sfe interface
+	 */
+	from_sfe_iface = from_ifaces[from_ifaces_first];
+	to_sfe_iface = to_ifaces[to_ifaces_first];
+	from_sfe_iface_id = ecm_db_iface_ae_interface_identifier_get(from_sfe_iface);
+	to_sfe_iface_id = ecm_db_iface_ae_interface_identifier_get(to_sfe_iface);
+	if ((from_sfe_iface_id < 0) || (to_sfe_iface_id < 0)) {
+		DEBUG_TRACE("%px: from_sfe_iface_id: %d, to_sfe_iface_id: %d\n", npci, from_sfe_iface_id, to_sfe_iface_id);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * New rule being created
+	 */
+	nircm->valid_flags |= SFE_RULE_CREATE_CONN_VALID;
+
+	/*
+	 * Set interface numbers involved in accelerating this connection.
+	 * These are the outer facing addresses from the heirarchy interface lists we got above.
+	 * These may be overridden later if we detect special interface types e.g. ipsec.
+	 */
+	nircm->conn_rule.flow_interface_num = from_sfe_iface_id;
+	nircm->conn_rule.return_interface_num = to_sfe_iface_id;
+
+	/*
+	 * Check which side of the connection can support L2 acceleration.
+	 * The check is done only for the routed flows and if the L2 feature is enabled.
+	 */
+	if (sfe_is_l2_feature_enabled() && ecm_db_connection_is_routed_get(feci->ci)) {
+		rcu_read_lock();
+		l2_accel_check = rcu_dereference(ecm_sfe_cb.l2_accel_check);
+		if (l2_accel_check) {
+			struct ecm_sfe_common_tuple l2_accel_tuple;
+
+			ecm_sfe_common_tuple_set(feci, from_sfe_iface_id, to_sfe_iface_id, &l2_accel_tuple);
+
+			l2_accel_bits = l2_accel_check(&l2_accel_tuple);
+		}
+		rcu_read_unlock();
+	}
+
+	/*
+	 * Set interface numbers involved in accelerating this connection.
+	 * These are the inner facing addresses from the heirarchy interface lists we got above.
+	 */
+	nim.msg.rule_create.conn_rule.flow_top_interface_num = ecm_db_iface_interface_identifier_get(from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX-1]);
+	nim.msg.rule_create.conn_rule.return_top_interface_num = ecm_db_iface_interface_identifier_get(to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX-1]);
+
+	/*
+	 * We know that each outward facing interface is known to the SFE and so this connection could be accelerated.
+	 * However the lists may also specify other interesting details that must be included in the creation command,
+	 * for example, ethernet MAC, VLAN tagging or PPPoE session information.
+	 * We get this information by walking from the outer to the innermost interface for each list and examine the interface types.
+	 *
+	 * Start with the 'from' (src) side.
+	 * NOTE: The lists may contain a complex heirarchy of similar type of interface e.g. multiple vlans or tunnels within tunnels.
+	 * This SFE cannot handle that - there is no way to describe this in the rule - if we see multiple types that would conflict we have to abort.
+	 */
+	DEBUG_TRACE("%px: Examine from/src heirarchy list. skb=%px\n", npci, skb);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = from_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+		struct ecm_db_interface_info_pppoe pppoe_info;
+#endif
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_in_dev = NULL;
+#endif
+
+		ii = from_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px (%s %d %d), type: %d (%s)\n",
+				npci, list_index, ii,
+				ii->name, ii->interface_identifier, ii->ae_interface_identifier,
+				ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_BRIDGE, list_index, from_ifaces_first) && (l2_accel_bits & ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_FROM, ECM_DB_IFACE_TYPE_BRIDGE);
+			}
+
+			ecm_db_iface_bridge_address_get(ii, from_sfe_iface_address);
+			if (is_valid_ether_addr(from_sfe_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_sfe_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+			}
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", npci, from_sfe_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_OVS_BRIDGE, list_index, from_ifaces_first) && (l2_accel_bits & ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_FROM, ECM_DB_IFACE_TYPE_OVS_BRIDGE);
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, from_sfe_iface_address);
+			if (is_valid_ether_addr(from_sfe_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_sfe_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+			}
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", npci, from_sfe_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", npci);
+				break;
+			}
+
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, from_sfe_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", npci, from_sfe_iface_address);
+			break;
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", npci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * PPPoE is supported only when L2 feature flag is enabled
+			 */
+			if (!sfe_is_l2_feature_enabled()) {
+				DEBUG_TRACE("%px: PPPoE - unsupported\n", npci);
+				break;
+			}
+
+			/*
+			 * If external module decide that L2 acceleration is not allowed, we should return
+			 * without setting PPPoE parameters.
+			 */
+			if (!(l2_accel_bits & ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED)) {
+				DEBUG_TRACE("%px: L2 acceleration is not allowed for the PPPoE interface\n", npci);
+				break;
+			}
+
+			feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_FROM, ECM_DB_IFACE_TYPE_PPPOE);
+
+			/*
+			 * Copy pppoe session info to the creation structure.
+			 */
+			ecm_db_iface_pppoe_session_info_get(ii, &pppoe_info);
+
+			nircm->pppoe_rule.flow_pppoe_session_id = pppoe_info.pppoe_session_id;
+			memcpy(nircm->pppoe_rule.flow_pppoe_remote_mac, pppoe_info.remote_mac, ETH_ALEN);
+			nircm->valid_flags |= SFE_RULE_CREATE_PPPOE_DECAP_VALID;
+			nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+
+			DEBUG_TRACE("%px: PPPoE - session: %x, mac: %pM\n", npci,
+					nircm->pppoe_rule.flow_pppoe_session_id,
+					nircm->pppoe_rule.flow_pppoe_remote_mac);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", npci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", npci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_in_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_in_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_in_dev, pr->return_qos_tag);
+				dev_put(vlan_in_dev);
+				vlan_in_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.ingress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.ingress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= SFE_RULE_CREATE_VLAN_VALID;
+
+			if (sfe_is_l2_feature_enabled() && (l2_accel_bits & ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_FROM, ECM_DB_IFACE_TYPE_VLAN);
+
+				if (is_valid_ether_addr(vlan_info.address)) {
+					ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, vlan_info.address);
+					nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_FLOW_VALID;
+					nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+				}
+			}
+
+			/*
+			 * If we have not yet got an ethernet mac then take this one
+			 * (very unlikely as mac should have been propagated to the slave (outer) device)
+			 */
+			if (interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET] == 0) {
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", npci, vlan_info.address);
+			}
+			DEBUG_TRACE("%px: vlan tag: %x\n", npci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", npci);
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_MACVLAN:
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_MACVLAN, list_index, from_ifaces_first) && (l2_accel_bits & ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_FROM, ECM_DB_IFACE_TYPE_MACVLAN);
+			}
+
+			ecm_db_iface_macvlan_address_get(ii, from_sfe_iface_address);
+			ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_sfe_iface_address);
+			nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_FLOW_VALID;
+			nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+
+			DEBUG_TRACE("%px: Macvlan - mac: %pM\n", npci, from_sfe_iface_address);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: MACVLAN - unsupported\n", npci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", npci);
+				break;
+			}
+			nircm->conn_rule.flow_interface_num = SFE_SPECIAL_INTERFACE_IPSEC;
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", npci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_LAG:
+#ifdef ECM_INTERFACE_BOND_ENABLE
+			if (sfe_is_l2_feature_enabled() && (l2_accel_bits & ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+				/*
+				 * LAG device gets its stats by summing up all stats of its
+				 * slaves (i.e. 'ethx' devices). Please see bond_get_stats()
+				 * in linux-5.4/drivers/net/bonding/bond_main.c.
+				 * So no need to call feci->set_stats_bitmap().
+				 */
+
+				ecm_db_iface_lag_address_get(ii, from_sfe_iface_address);
+				if (is_valid_ether_addr(from_sfe_iface_address)) {
+					ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_sfe_iface_address);
+					nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_FLOW_VALID;
+					nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+				}
+				DEBUG_TRACE("%px: LAG - mac: %pM\n", npci, from_sfe_iface_address);
+			}
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: LAG - unsupported\n", npci);
+#endif
+			break;
+
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", npci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+	if (rule_invalid) {
+		DEBUG_WARN("%px: from/src Rule invalid\n", npci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * Now examine the TO / DEST heirarchy list to construct the destination part of the rule
+	 */
+	DEBUG_TRACE("%px: Examine to/dest heirarchy list\n", npci);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = to_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+		struct ecm_db_interface_info_pppoe pppoe_info;
+#endif
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_out_dev = NULL;
+#endif
+
+		ii = to_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px (%s %d %d), type: %d (%s)\n",
+				npci, list_index, ii,
+				ii->name, ii->interface_identifier, ii->ae_interface_identifier,
+				ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_BRIDGE, list_index, to_ifaces_first) && (l2_accel_bits & ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_TO, ECM_DB_IFACE_TYPE_BRIDGE);
+			}
+
+			ecm_db_iface_bridge_address_get(ii, to_sfe_iface_address);
+			if (is_valid_ether_addr(to_sfe_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_sfe_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+			}
+
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", npci, to_sfe_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_OVS_BRIDGE, list_index, to_ifaces_first) && (l2_accel_bits & ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_TO, ECM_DB_IFACE_TYPE_OVS_BRIDGE);
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, to_sfe_iface_address);
+			if (is_valid_ether_addr(to_sfe_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, to_sfe_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+			}
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", npci, to_sfe_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", npci);
+				break;
+			}
+
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, to_sfe_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", npci, to_sfe_iface_address);
+			break;
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", npci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * PPPoE is supported only when L2 feature flag is enabled
+			 */
+			if (!sfe_is_l2_feature_enabled()) {
+				DEBUG_TRACE("%px: PPPoE - unsupported\n", npci);
+				break;
+			}
+
+			/*
+			 * If external module decide that L2 acceleration is not allowed, we should return
+			 * without setting PPPoE parameters.
+			 */
+			if (!(l2_accel_bits & ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED)) {
+				DEBUG_TRACE("%px: L2 acceleration is not allowed for the PPPoE interface\n", npci);
+				break;
+			}
+
+			feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_TO, ECM_DB_IFACE_TYPE_PPPOE);
+
+			/*
+			 * Copy pppoe session info to the creation structure.
+			 */
+			ecm_db_iface_pppoe_session_info_get(ii, &pppoe_info);
+			nircm->pppoe_rule.return_pppoe_session_id = pppoe_info.pppoe_session_id;
+			memcpy(nircm->pppoe_rule.return_pppoe_remote_mac, pppoe_info.remote_mac, ETH_ALEN);
+			nircm->valid_flags |= SFE_RULE_CREATE_PPPOE_ENCAP_VALID;
+			nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+
+			DEBUG_TRACE("%px: PPPoE - session: %x, mac: %pM\n", npci,
+				    nircm->pppoe_rule.return_pppoe_session_id,
+				    nircm->pppoe_rule.return_pppoe_remote_mac);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", npci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", npci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_out_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_out_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_out_dev, pr->flow_qos_tag);
+				dev_put(vlan_out_dev);
+				vlan_out_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.egress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.egress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= SFE_RULE_CREATE_VLAN_VALID;
+
+			if (sfe_is_l2_feature_enabled() && (l2_accel_bits & ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_TO, ECM_DB_IFACE_TYPE_VLAN);
+
+				if (is_valid_ether_addr(vlan_info.address)) {
+					ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, vlan_info.address);
+					nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_RETURN_VALID;
+					nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+				}
+			}
+
+			/*
+			 * If we have not yet got an ethernet mac then take this one
+			 * (very unlikely as mac should have been propagated to the slave (outer) device)
+			 */
+			if (interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET] == 0) {
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", npci, vlan_info.address);
+			}
+			DEBUG_TRACE("%px: vlan tag: %x\n", npci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", npci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_MACVLAN:
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_MACVLAN, list_index, to_ifaces_first) && (l2_accel_bits & ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_TO, ECM_DB_IFACE_TYPE_MACVLAN);
+			}
+
+			ecm_db_iface_macvlan_address_get(ii, to_sfe_iface_address);
+			ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_sfe_iface_address);
+			nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_RETURN_VALID;
+			nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+
+			DEBUG_TRACE("%px: Macvlan - mac: %pM\n", npci, to_sfe_iface_address);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: MACVLAN - unsupported\n", npci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", npci);
+				break;
+			}
+			nircm->conn_rule.return_interface_num = SFE_SPECIAL_INTERFACE_IPSEC;
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", npci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_LAG:
+#ifdef ECM_INTERFACE_BOND_ENABLE
+			if (sfe_is_l2_feature_enabled() && (l2_accel_bits & ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+				/*
+				 * LAG device gets its stats by summing up all stats of its
+				 * slaves (i.e. 'ethx' devices). Please see bond_get_stats()
+				 * in linux-5.4/drivers/net/bonding/bond_main.c.
+				 * So no need to call feci->set_stats_bitmap().
+				 */
+
+				ecm_db_iface_lag_address_get(ii, to_sfe_iface_address);
+				if (is_valid_ether_addr(to_sfe_iface_address)) {
+					ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_sfe_iface_address);
+					nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_RETURN_VALID;
+					nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+				}
+				DEBUG_TRACE("%px: LAG - mac: %pM\n", npci, to_sfe_iface_address);
+			}
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: LAG - unsupported\n", npci);
+#endif
+			break;
+
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", npci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+	if (rule_invalid) {
+		DEBUG_WARN("%px: to/dest Rule invalid\n", npci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * Routed or bridged?
+	 */
+	if (ecm_db_connection_is_routed_get(feci->ci)) {
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_ROUTED;
+	} else {
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_BRIDGE_FLOW;
+		if (is_l2_encap) {
+			nircm->rule_flags |= SFE_RULE_CREATE_FLAG_L2_ENCAP;
+		}
+	}
+
+	if (ecm_interface_src_check) {
+		DEBUG_INFO("%px: Source interface check flag is enabled\n", npci);
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_FLOW_SRC_INTERFACE_CHECK;
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_RETURN_SRC_INTERFACE_CHECK;
+	}
+
+	/*
+	 * Enable source interface check without flushing the rule for this flow to re-inject the packet to
+	 * the network stack in SFE driver after the first pass of the packet coming with the L2 interface.
+	 * In the second pass, the packet will come to SFE with the L3 interface. If there are more than 3 interfaces
+	 * in the hierarchy, the packet will be re-injected to the stack until the flows input interface matches with the
+	 * rule's match_dev.
+	 */
+	if (!(l2_accel_bits & ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED)) {
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_FLOW_SRC_INTERFACE_CHECK;
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_FLOW_SRC_INTERFACE_CHECK_NO_FLUSH;
+	}
+
+	if (!(l2_accel_bits & ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED)) {
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_RETURN_SRC_INTERFACE_CHECK;
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_RETURN_SRC_INTERFACE_CHECK_NO_FLUSH;
+	}
+
+	/*
+	 * Set up the flow and return qos tags
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+		nircm->qos_rule.flow_qos_tag = (uint32_t)pr->flow_qos_tag;
+		nircm->qos_rule.return_qos_tag = (uint32_t)pr->return_qos_tag;
+		nircm->valid_flags |= SFE_RULE_CREATE_QOS_VALID;
+	}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+	/*
+	 * DSCP information?
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+		nircm->dscp_rule.flow_dscp = pr->flow_dscp;
+		nircm->dscp_rule.return_dscp = pr->return_dscp;
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_DSCP_MARKING;
+		nircm->valid_flags |= SFE_RULE_CREATE_DSCP_MARKING_VALID;
+	}
+
+	/*
+	 * Set up the flow and return mark.
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_MARK) {
+		nircm->mark_rule.flow_mark = (uint32_t)pr->flow_mark;
+		nircm->mark_rule.return_mark = (uint32_t)pr->return_mark;
+		nircm->valid_flags |= SFE_RULE_CREATE_MARK_VALID;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+	if (ecm_front_end_is_feature_supported(ECM_FE_FEATURE_OVS_VLAN)) {
+		/*
+		 * Copy the both primary and secondary (if exist) VLAN tags.
+		 */
+		if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG) {
+			nircm->vlan_primary_rule.ingress_vlan_tag = pr->ingress_vlan_tag[0];
+			nircm->vlan_primary_rule.egress_vlan_tag = pr->egress_vlan_tag[0];
+			nircm->valid_flags |= SFE_RULE_CREATE_VLAN_VALID;
+		}
+
+		if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG) {
+			nircm->vlan_secondary_rule.ingress_vlan_tag = pr->ingress_vlan_tag[1];
+			nircm->vlan_secondary_rule.egress_vlan_tag = pr->egress_vlan_tag[1];
+		}
+	}
+#endif
+
+#ifdef CONFIG_XFRM
+	nircm->direction_rule.flow_accel = (npci->flow_ipsec_state != ECM_SFE_IPSEC_STATE_TO_ENCRYPT);
+	nircm->direction_rule.return_accel = (npci->return_ipsec_state != ECM_SFE_IPSEC_STATE_TO_ENCRYPT);
+	if (!nircm->direction_rule.flow_accel || !nircm->direction_rule.return_accel) {
+		nircm->valid_flags |= SFE_RULE_CREATE_DIRECTION_VALID;
+	}
+#endif
+	protocol = ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * Set protocol
+	 */
+	nircm->tuple.protocol = (int32_t)protocol;
+
+	/*
+	 * The flow_ip is where the connection established from
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, addr);
+	ECM_IP_ADDR_TO_NIN4_ADDR(nircm->tuple.flow_ip, addr);
+
+	/*
+	 * The return_ip is where the connection is established to, however, in the case of ingress
+	 * the return_ip would be the routers WAN IP - i.e. the NAT'ed version.
+	 * Getting the NAT'ed version here works for ingress or egress packets, for egress
+	 * the NAT'ed version would be the same as the normal address
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, addr);
+	ECM_IP_ADDR_TO_NIN4_ADDR(nircm->tuple.return_ip, addr);
+
+	/*
+	 * When the packet is forwarded to the next interface get the address the source IP of the
+	 * packet should be translated to.  For egress this is the NAT'ed from address.
+	 * This also works for ingress as the NAT'ed version of the WAN host would be the same as non-NAT'ed
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM_NAT, addr);
+	ECM_IP_ADDR_TO_NIN4_ADDR(nircm->conn_rule.flow_ip_xlate, addr);
+
+	/*
+	 * The destination address is what the destination IP is translated to as it is forwarded to the next interface.
+	 * For egress this would yield the normal wan host and for ingress this would correctly NAT back to the LAN host
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, addr);
+	ECM_IP_ADDR_TO_NIN4_ADDR(nircm->conn_rule.return_ip_xlate, addr);
+
+	/*
+	 * Same approach as above for port information
+	 */
+	nircm->tuple.flow_ident = htons(ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM));
+	nircm->tuple.return_ident = htons(ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT));
+	nircm->conn_rule.flow_ident_xlate = htons(ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM_NAT));
+	nircm->conn_rule.return_ident_xlate = htons(ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO));
+
+	/*
+	 * Get mac addresses.
+	 * The src_mac is the mac address of the node that established the connection.
+	 * This will work whether the from_node is LAN (egress) or WAN (ingress).
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, (uint8_t *)nircm->conn_rule.flow_mac);
+
+	/*
+	 * The dest_mac is more complex.  For egress it is the node address of the 'to' side of the connection.
+	 * For ingress it is the node adress of the NAT'ed 'to' IP.
+	 * Essentially it is the MAC of node associated with create.dest_ip and this is "to nat" side.
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, (uint8_t *)nircm->conn_rule.return_mac);
+
+	/*
+	 * The dest_mac_xlate is the mac address to replace the pkt.dst_mac when a packet is sent to->from
+	 * For bridged connections this does not change.
+	 * For routed connections this is the mac of the 'to' node side of the connection.
+	 */
+	if (ecm_db_connection_is_routed_get(feci->ci)) {
+		ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, dest_mac_xlate);
+	} else {
+		/*
+		 * Bridge flows preserve the MAC addressing
+		 */
+		memcpy(dest_mac_xlate, (uint8_t *)nircm->conn_rule.return_mac, ETH_ALEN);
+	}
+
+	/*
+	 * Refer to the Example 2 and 3 in ecm_sfe_ipv4_ip_process() function for egress
+	 * and ingress NAT'ed cases. In these cases, the destination node is the one which has the
+	 * ip_dest_addr. So, above we get the mac address of this host and use that mac address
+	 * for the destination node address in NAT'ed cases.
+	 */
+	ecm_dir = ecm_db_connection_direction_get(feci->ci);
+	if ((ecm_dir == ECM_DB_DIRECTION_INGRESS_NAT) || (ecm_dir == ECM_DB_DIRECTION_EGRESS_NAT)) {
+		memcpy(nircm->conn_rule.return_mac, dest_mac_xlate, ETH_ALEN);
+	}
+
+	/*
+	 * Get MTU information
+	 */
+	nircm->conn_rule.flow_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nircm->conn_rule.return_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	if (protocol == IPPROTO_TCP) {
+		/*
+		 * Need window scaling and remarking information if available
+		 * Start by looking up the conntrack connection
+		 */
+		if (!ct) {
+			/*
+			 * No conntrack so no need to check window sequence space
+			 */
+			DEBUG_TRACE("%px: TCP Accel no ct from conn %px to get window data\n", npci, feci->ci);
+			nircm->rule_flags |= SFE_RULE_CREATE_FLAG_NO_SEQ_CHECK;
+		} else {
+			int flow_dir;
+			int return_dir;
+
+			ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, addr);
+			ecm_front_end_flow_and_return_directions_get(ct, addr, 4, &flow_dir, &return_dir);
+
+			DEBUG_TRACE("%px: TCP Accel Get window data from ct %px for conn %px\n", npci, ct, feci->ci);
+			spin_lock_bh(&ct->lock);
+			nircm->tcp_rule.flow_window_scale = ct->proto.tcp.seen[flow_dir].td_scale;
+			nircm->tcp_rule.flow_max_window = ct->proto.tcp.seen[flow_dir].td_maxwin;
+			nircm->tcp_rule.flow_end = ct->proto.tcp.seen[flow_dir].td_end;
+			nircm->tcp_rule.flow_max_end = ct->proto.tcp.seen[flow_dir].td_maxend;
+			nircm->tcp_rule.return_window_scale = ct->proto.tcp.seen[return_dir].td_scale;
+			nircm->tcp_rule.return_max_window = ct->proto.tcp.seen[return_dir].td_maxwin;
+			nircm->tcp_rule.return_end = ct->proto.tcp.seen[return_dir].td_end;
+			nircm->tcp_rule.return_max_end = ct->proto.tcp.seen[return_dir].td_maxend;
+#ifdef ECM_OPENWRT_SUPPORT
+			if (nf_ct_tcp_be_liberal || nf_ct_tcp_no_window_check
+#else
+			if (nf_ct_tcp_be_liberal
+#endif
+					|| (ct->proto.tcp.seen[flow_dir].flags & IP_CT_TCP_FLAG_BE_LIBERAL)
+					|| (ct->proto.tcp.seen[return_dir].flags & IP_CT_TCP_FLAG_BE_LIBERAL)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_NO_SEQ_CHECK;
+			} else {
+#ifdef CONFIG_XFRM
+				/*
+				 * TCP window check will fail if TCP is accelerated in one direction but not in another
+				 */
+				if (nircm->direction_rule.flow_accel != nircm->direction_rule.return_accel) {
+					spin_unlock_bh(&ct->lock);
+					DEBUG_WARN("Can't accelerate ipsec TCP flow in uni-direction because TCP window checking is on\n");
+					ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+					ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+					goto ported_accel_bad_rule;
+				}
+#endif
+			}
+			spin_unlock_bh(&ct->lock);
+		}
+
+		nircm->valid_flags |= SFE_RULE_CREATE_TCP_VALID;
+	}
+
+	/*
+	 * Sync our creation command from the assigned classifiers to get specific additional creation rules.
+	 * NOTE: These are called in ascending order of priority and so the last classifier (highest) shall
+	 * override any preceding classifiers.
+	 * This also gives the classifiers a chance to see that acceleration is being attempted.
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(feci->ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+		struct ecm_classifier_rule_create ecrc;
+		/*
+		 * NOTE: The current classifiers do not sync anything to the underlying accel engines.
+		 * In the future, if any of the classifiers wants to pass any parameter, these parameters
+		 * should be received via this object and copied to the accel engine's create object (nircm).
+		*/
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: sync from: %px, type: %d\n", npci, aci, aci->type_get(aci));
+		aci->sync_from_v4(aci, &ecrc);
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Release the interface lists
+	 */
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+	ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+
+	DEBUG_INFO("%px: Ported Accelerate connection %px\n"
+			"Protocol: %d\n"
+			"from_mtu: %u\n"
+			"to_mtu: %u\n"
+			"from_ip: %pI4n:%d\n"
+			"to_ip: %pI4n:%d\n"
+			"from_ip_xlate: %pI4n:%d\n"
+			"to_ip_xlate: %pI4n:%d\n"
+			"from_mac: %pM\n"
+			"to_mac: %pM\n"
+			"from_src_mac: %pM\n"
+			"to_src_mac: %pM\n"
+			"from_iface_num: %u\n"
+			"to_iface_num: %u\n"
+			"from_top_interface_num: %d\n"
+			"to_top_interface_num: %d\n"
+			"primary_ingress_vlan_tag: %x\n"
+			"primary_egress_vlan_tag: %x\n"
+			"secondary_ingress_vlan_tag: %x\n"
+			"secondary_egress_vlan_tag: %x\n"
+			"flags: rule=%x valid=%x src_mac_valid=%x\n"
+			"return_pppoe_session_id: %u\n"
+			"return_pppoe_remote_mac: %pM\n"
+			"flow_pppoe_session_id: %u\n"
+			"flow_pppoe_remote_mac: %pM\n"
+			"flow_qos_tag: %x (%u)\n"
+			"return_qos_tag: %x (%u)\n"
+			"flow_window_scale: %u\n"
+			"flow_max_window: %u\n"
+			"flow_end: %u\n"
+			"flow_max_end: %u\n"
+			"return_window_scale: %u\n"
+			"return_max_window: %u\n"
+			"return_end: %u\n"
+			"return_max_end: %u\n"
+			"flow_dscp: %x\n"
+			"return_dscp: %x\n"
+			"flow_mark:%x\n"
+			"return_mark:%x\n",
+			npci,
+			feci->ci,
+			nircm->tuple.protocol,
+			nircm->conn_rule.flow_mtu,
+			nircm->conn_rule.return_mtu,
+			&nircm->tuple.flow_ip, ntohs(nircm->tuple.flow_ident),
+			&nircm->tuple.return_ip, ntohs(nircm->tuple.return_ident),
+			&nircm->conn_rule.flow_ip_xlate, ntohs(nircm->conn_rule.flow_ident_xlate),
+			&nircm->conn_rule.return_ip_xlate, ntohs(nircm->conn_rule.return_ident_xlate),
+			nircm->conn_rule.flow_mac,
+			nircm->conn_rule.return_mac,
+			nircm->src_mac_rule.flow_src_mac,
+			nircm->src_mac_rule.return_src_mac,
+			nircm->conn_rule.flow_interface_num,
+			nircm->conn_rule.return_interface_num,
+			nircm->conn_rule.flow_top_interface_num,
+			nircm->conn_rule.return_top_interface_num,
+			nircm->vlan_primary_rule.ingress_vlan_tag,
+			nircm->vlan_primary_rule.egress_vlan_tag,
+			nircm->vlan_secondary_rule.ingress_vlan_tag,
+			nircm->vlan_secondary_rule.egress_vlan_tag,
+			nircm->rule_flags,
+			nircm->valid_flags,
+			nircm->src_mac_rule.mac_valid_flags,
+			nircm->pppoe_rule.return_pppoe_session_id,
+			nircm->pppoe_rule.return_pppoe_remote_mac,
+			nircm->pppoe_rule.flow_pppoe_session_id,
+			nircm->pppoe_rule.flow_pppoe_remote_mac,
+			nircm->qos_rule.flow_qos_tag, nircm->qos_rule.flow_qos_tag,
+			nircm->qos_rule.return_qos_tag, nircm->qos_rule.return_qos_tag,
+			nircm->tcp_rule.flow_window_scale,
+			nircm->tcp_rule.flow_max_window,
+			nircm->tcp_rule.flow_end,
+			nircm->tcp_rule.flow_max_end,
+			nircm->tcp_rule.return_window_scale,
+			nircm->tcp_rule.return_max_window,
+			nircm->tcp_rule.return_end,
+			nircm->tcp_rule.return_max_end,
+			nircm->dscp_rule.flow_dscp,
+			nircm->dscp_rule.return_dscp,
+			nircm->mark_rule.flow_mark,
+			nircm->mark_rule.return_mark);
+
+	if (protocol == IPPROTO_TCP) {
+
+		DEBUG_INFO("flow_window_scale: %u\n"
+			"flow_max_window: %u\n"
+			"flow_end: %u\n"
+			"flow_max_end: %u\n"
+			"return_window_scale: %u\n"
+			"return_max_window: %u\n"
+			"return_end: %u\n"
+			"return_max_end: %u\n",
+			nircm->tcp_rule.flow_window_scale,
+			nircm->tcp_rule.flow_max_window,
+			nircm->tcp_rule.flow_end,
+			nircm->tcp_rule.flow_max_end,
+			nircm->tcp_rule.return_window_scale,
+			nircm->tcp_rule.return_max_window,
+			nircm->tcp_rule.return_end,
+			nircm->tcp_rule.return_max_end);
+	}
+
+	/*
+	 * Now that the rule has been constructed we re-compare the generation occurrance counter.
+	 * If there has been a change then we abort because the rule may have been created using
+	 * unstable data - especially if another thread has begun regeneration of the connection state.
+	 * NOTE: This does not prevent a regen from being flagged immediately after this line of code either,
+	 * or while the acceleration rule is in flight to the nss.
+	 * This is only to check for consistency of rule state - not that the state is stale.
+	 * Remember that the connection is marked as "accel pending state" so if a regen is flagged immediately
+	 * after this check passes, the connection will be decelerated and refreshed very quickly.
+	 */
+	if (regen_occurrances != ecm_db_connection_regeneration_occurrances_get(feci->ci)) {
+		DEBUG_INFO("%px: connection:%px regen occurred - aborting accel rule.\n", feci, feci->ci);
+		ecm_sfe_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		return;
+	}
+
+	/*
+	 * Ref the connection before issuing an SFE rule
+	 * This ensures that when the SFE responds to the command - which may even be immediately -
+	 * the callback function can trust the correct ref was taken for its purpose.
+	 * NOTE: remember that this will also implicitly hold the feci.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Set fast xmit flags if connection can fast xmit
+	 */
+	ecm_sfe_ipv4_fast_xmit_set(nircm);
+
+	/*
+	 * Call the rule create function
+	 */
+	sfe_tx_status = sfe_ipv4_tx(ecm_sfe_ipv4_mgr, &nim);
+	if (sfe_tx_status == SFE_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * Release that ref!
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * TX failed
+	 */
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Accel mode unexpected: %d\n", feci, feci->accel_mode);
+	feci->stats.driver_fail_total++;
+	feci->stats.driver_fail++;
+	if (feci->stats.driver_fail >= feci->stats.driver_fail_limit) {
+		DEBUG_WARN("%px: Accel failed - driver fail limit\n", npci);
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DRIVER;
+	} else {
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	_ecm_sfe_ipv4_accel_pending_clear(feci, result_mode);
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+	spin_unlock_bh(&feci->lock);
+	return;
+
+ported_accel_bad_rule:
+	;
+
+	/*
+	 * Jump to here when rule data is bad and an offload command cannot be constructed
+	 */
+	DEBUG_WARN("%px: Accel failed - bad rule\n", npci);
+	ecm_sfe_ipv4_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_FAIL_RULE);
+}
+
+/*
+ * ecm_sfe_ported_ipv4_connection_destroy_callback()
+ *	Callback for handling destroy ack/nack calls.
+ */
+static void ecm_sfe_ported_ipv4_connection_destroy_callback(void *app_data, struct sfe_ipv4_msg *nim)
+{
+	struct sfe_ipv4_rule_destroy_msg * __attribute__((unused))nirdm = &nim->msg.rule_destroy;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_sfe_ported_ipv4_connection_instance *npci;
+
+	/*
+	 * Is this a response to a destroy message?
+	 */
+	if (nim->cm.type != SFE_TX_DESTROY_RULE_MSG) {
+		DEBUG_ERROR("%px: ported destroy callback with improper type: %d\n", nim, nim->cm.type);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: destroy callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	npci = (struct ecm_sfe_ported_ipv4_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_sfe_ipv4_decel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: decelerate response for connection: %px\n", npci, feci->ci);
+	DEBUG_TRACE("%px: flow_ip: %pI4n:%d\n", npci, &nirdm->tuple.flow_ip, nirdm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: %pI4n:%d\n", npci, &nirdm->tuple.return_ip, nirdm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", npci, nirdm->tuple.protocol);
+
+	/*
+	 * Drop decel pending counter
+	 */
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	ecm_sfe_ipv4_pending_decel_count--;
+	DEBUG_ASSERT(ecm_sfe_ipv4_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If decel is not still pending then it's possible that the SFE ended acceleration by some other reason e.g. flush
+	 * In which case we cannot rely on the response we get here.
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING) {
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connections.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_TRACE("%px: response: %d\n", npci, nim->cm.response);
+	if (nim->cm.response != SFE_CMN_RESPONSE_ACK) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DECEL;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	/*
+	 * If connection became defunct then set mode so that no further accel/decel attempts occur.
+	 */
+	if (feci->is_defunct) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT_SHORT;
+	}
+
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Ported acceleration ends
+	 */
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	ecm_sfe_ported_ipv4_accelerated_count[npci->ported_accelerated_count_index]--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_sfe_ported_ipv4_accelerated_count[npci->ported_accelerated_count_index] >= 0, "Bad udp accel counter\n");
+	ecm_sfe_ipv4_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_sfe_ipv4_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+	/*
+	 * Release the connections.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_sfe_ported_ipv4_connection_decelerate_msg_send()
+ *	Prepares and sends a decelerate message to acceleration engine.
+ */
+static bool ecm_sfe_ported_ipv4_connection_decelerate_msg_send(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_ported_ipv4_connection_instance *npci = (struct ecm_sfe_ported_ipv4_connection_instance *)feci;
+	struct sfe_ipv4_msg nim;
+	struct sfe_ipv4_rule_destroy_msg *nirdm;
+	ip_addr_t addr;
+	sfe_tx_status_t sfe_tx_status;
+	bool ret;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	/*
+	 * Increment the decel pending counter
+	 */
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	ecm_sfe_ipv4_pending_decel_count++;
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+	/*
+	 * Prepare deceleration message
+	 */
+	sfe_ipv4_msg_init(&nim, SFE_SPECIAL_INTERFACE_IPV4, SFE_TX_DESTROY_RULE_MSG,
+			sizeof(struct sfe_ipv4_rule_destroy_msg),
+			ecm_sfe_ported_ipv4_connection_destroy_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nirdm = &nim.msg.rule_destroy;
+	nirdm->tuple.protocol = (int32_t)ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * Get addressing information
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, addr);
+	ECM_IP_ADDR_TO_NIN4_ADDR(nirdm->tuple.flow_ip, addr);
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT, addr);
+	ECM_IP_ADDR_TO_NIN4_ADDR(nirdm->tuple.return_ip, addr);
+	nirdm->tuple.flow_ident = htons(ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM));
+	nirdm->tuple.return_ident = htons(ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO_NAT));
+
+	DEBUG_INFO("%px: Ported Connection %px decelerate\n"
+			"protocol: %d\n"
+			"src_ip: %pI4:%d\n"
+			"dest_ip: %pI4:%d\n",
+			npci, feci->ci, nirdm->tuple.protocol,
+			&nirdm->tuple.flow_ip, nirdm->tuple.flow_ident,
+			&nirdm->tuple.return_ip, nirdm->tuple.return_ident);
+
+	/*
+	 * Take a ref to the feci->ci so that it will persist until we get a response from the SFE.
+	 * NOTE: This will implicitly hold the feci too.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Destroy the SFE connection cache entry.
+	 */
+	sfe_tx_status = sfe_ipv4_tx(ecm_sfe_ipv4_mgr, &nim);
+	if (sfe_tx_status == SFE_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;
+		spin_unlock_bh(&feci->lock);
+		return true;
+	}
+
+	/*
+	 * TX failed
+	 */
+	ret = ecm_front_end_destroy_failure_handle(feci);
+
+	/*
+	 * Release the ref take, SFE driver did not accept our command.
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * Could not send the request, decrement the decel pending counter
+	 */
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	ecm_sfe_ipv4_pending_decel_count--;
+	DEBUG_ASSERT(ecm_sfe_ipv4_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+	return ret;
+}
+
+/*
+ * ecm_sfe_ported_ipv4_connection_decelerate()
+ *     Decelerate a connection
+ */
+static bool ecm_sfe_ported_ipv4_connection_decelerate(struct ecm_front_end_connection_instance *feci)
+{
+	/*
+	 * Check if accel mode is OK for the deceleration.
+	 */
+	spin_lock_bh(&feci->lock);
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	return ecm_sfe_ported_ipv4_connection_decelerate_msg_send(feci);
+}
+
+/*
+ * ecm_sfe_ported_ipv4_connection_defunct_callback()
+ *	Callback to be called when a ported connection has become defunct.
+ */
+bool ecm_sfe_ported_ipv4_connection_defunct_callback(void *arg, int *accel_mode)
+{
+	bool ret;
+	struct ecm_front_end_connection_instance *feci = (struct ecm_front_end_connection_instance *)arg;
+	struct ecm_sfe_ported_ipv4_connection_instance *npci = (struct ecm_sfe_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	spin_lock_bh(&feci->lock);
+	/*
+	 * Check if the connection can be defuncted.
+	 */
+	if (!ecm_front_end_common_connection_defunct_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+
+	/*
+	 * If none of the cases matched above, this means the connection is in the
+	 * accel mode, so we force a deceleration.
+	 * NOTE: If the mode is accel pending then the decel will be actioned when that is completed.
+	 */
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	ret = ecm_sfe_ported_ipv4_connection_decelerate_msg_send(feci);
+
+	/*
+	 * Copy the accel_mode which is returned from the decelerate message function. This value
+	 * will be used in the caller to decide releasing the final reference of the connection.
+	 * But if this function reaches to here, the caller care about the ret. If ret is true,
+	 * the reference will be released regardless of the accel_mode. If ret is false, accel_mode
+	 * will be in the ACCEL state (for destroy re-try) and this state will not be used in the
+	 * caller's decision. It looks for ACCEL_FAIL states.
+	 */
+	spin_lock_bh(&feci->lock);
+	*accel_mode = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+
+	return ret;
+}
+
+/*
+ * ecm_sfe_ported_ipv4_connection_accel_state_get()
+ *	Get acceleration state
+ */
+static ecm_front_end_acceleration_mode_t ecm_sfe_ported_ipv4_connection_accel_state_get(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_ported_ipv4_connection_instance *npci = (struct ecm_sfe_ported_ipv4_connection_instance *)feci;
+	ecm_front_end_acceleration_mode_t state;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	spin_lock_bh(&feci->lock);
+	state = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+	return state;
+}
+
+/*
+ * ecm_sfe_ported_ipv4_connection_action_seen()
+ *	Acceleration action / activity has been seen for this connection.
+ *
+ * NOTE: Call the action_seen() method when the SFE has demonstrated that it has offloaded some data for a connection.
+ */
+static void ecm_sfe_ported_ipv4_connection_action_seen(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_ported_ipv4_connection_instance *npci = (struct ecm_sfe_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	DEBUG_INFO("%px: Action seen\n", npci);
+	spin_lock_bh(&feci->lock);
+	feci->stats.no_action_seen = 0;
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_sfe_ported_ipv4_connection_accel_ceased()
+ *	SFE has indicated that acceleration has stopped.
+ *
+ * NOTE: This is called in response to an SFE self-initiated termination of acceleration.
+ * This must NOT be called because the ECM terminated the acceleration.
+ */
+static void ecm_sfe_ported_ipv4_connection_accel_ceased(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_ported_ipv4_connection_instance *npci = (struct ecm_sfe_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	DEBUG_INFO("%px: accel ceased\n", npci);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If we are in accel-pending state then the SFE has issued a flush out-of-order
+	 * with the ACK/NACK we are actually waiting for.
+	 * To work around this we record a "flush has already happened" and will action it when we finally get that ACK/NACK.
+	 * GGG TODO This should eventually be removed when the SFE honours messaging sequence.
+	 */
+	if (feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING) {
+		feci->stats.flush_happened = true;
+		feci->stats.flush_happened_total++;
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If connection is no longer accelerated by the time we get here just ignore the command
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_ACCEL) {
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If the no_action_seen counter was not reset then acceleration ended without any offload action
+	 */
+	if (feci->stats.no_action_seen) {
+		feci->stats.no_action_seen_total++;
+	}
+
+	/*
+	 * If the no_action_seen indicates successive cessations of acceleration without any offload action occuring
+	 * then we fail out this connection
+	 */
+	if (feci->stats.no_action_seen >= feci->stats.no_action_seen_limit) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_NO_ACTION;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Ported acceleration ends
+	 */
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	ecm_sfe_ported_ipv4_accelerated_count[npci->ported_accelerated_count_index]--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_sfe_ported_ipv4_accelerated_count[npci->ported_accelerated_count_index] >= 0, "Bad ported accel counter\n");
+	ecm_sfe_ipv4_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_sfe_ipv4_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+}
+
+/*
+ * ecm_sfe_ported_ipv4_connection_ref()
+ *	Ref a connection front end instance
+ */
+static void ecm_sfe_ported_ipv4_connection_ref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_ported_ipv4_connection_instance *npci = (struct ecm_sfe_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	spin_lock_bh(&feci->lock);
+	feci->refs++;
+	DEBUG_TRACE("%px: npci ref %d\n", feci, feci->refs);
+	DEBUG_ASSERT(feci->refs > 0, "%px: ref wrap\n", feci);
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_sfe_ported_ipv4_connection_deref()
+ *	Deref a connection front end instance
+ */
+static int ecm_sfe_ported_ipv4_connection_deref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_ported_ipv4_connection_instance *npci = (struct ecm_sfe_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	spin_lock_bh(&feci->lock);
+	feci->refs--;
+	DEBUG_ASSERT(feci->refs >= 0, "%px: ref wrap\n", feci);
+
+	if (feci->refs > 0) {
+		int refs = feci->refs;
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: npci deref %d\n", npci, refs);
+		return refs;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * We can now destroy the instance
+	 */
+	DEBUG_TRACE("%px: npci final\n", npci);
+	DEBUG_CLEAR_MAGIC(npci);
+	kfree(npci);
+	return 0;
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_sfe_ported_ipv4_connection_state_get()
+ *	Return state of this ported front end instance
+ */
+static int ecm_sfe_ported_ipv4_connection_state_get(struct ecm_front_end_connection_instance *feci, struct ecm_state_file_instance *sfi)
+{
+	struct ecm_sfe_ported_ipv4_connection_instance *npci = (struct ecm_sfe_ported_ipv4_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	return ecm_front_end_common_connection_state_get(feci, sfi, "sfe_v4.ported");
+}
+#endif
+
+/*
+ * ecm_sfe_ported_ipv4_connection_instance_alloc()
+ *	Create a front end instance specific for ported connection
+ */
+struct ecm_sfe_ported_ipv4_connection_instance *ecm_sfe_ported_ipv4_connection_instance_alloc(
+								bool can_accel,
+								int protocol,
+								struct ecm_db_connection_instance **nci)
+{
+	struct ecm_sfe_ported_ipv4_connection_instance *npci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_db_connection_instance *ci;
+
+	if (ecm_sfe_ipv4_is_conn_limit_reached()) {
+		DEBUG_TRACE("Reached connection limit\n");
+		return NULL;
+	}
+
+	/*
+	 * Now allocate the new connection
+	 */
+	*nci = ecm_db_connection_alloc();
+	if (!*nci) {
+		DEBUG_WARN("Failed to allocate connection\n");
+		return NULL;
+	}
+
+	ci = *nci;
+
+	npci = (struct ecm_sfe_ported_ipv4_connection_instance *)kzalloc(sizeof(struct ecm_sfe_ported_ipv4_connection_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!npci) {
+		DEBUG_WARN("Ported Front end alloc failed\n");
+		ecm_db_connection_deref(ci);
+		return NULL;
+	}
+
+	/*
+	 * Refs is 1 for the creator of the connection
+	 */
+	feci = (struct ecm_front_end_connection_instance *)npci;
+	feci->refs = 1;
+	DEBUG_SET_MAGIC(npci, ECM_SFE_PORTED_IPV4_CONNECTION_INSTANCE_MAGIC);
+	spin_lock_init(&feci->lock);
+
+	feci->can_accel = can_accel;
+	feci->accel_mode = (can_accel)? ECM_FRONT_END_ACCELERATION_MODE_DECEL : ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED;
+	feci->accel_engine = ECM_FRONT_END_ENGINE_SFE;
+	spin_lock_bh(&ecm_sfe_ipv4_lock);
+	feci->stats.no_action_seen_limit = ecm_sfe_ipv4_no_action_limit_default;
+	feci->stats.driver_fail_limit = ecm_sfe_ipv4_driver_fail_limit_default;
+	feci->stats.ae_nack_limit = ecm_sfe_ipv4_nack_limit_default;
+	spin_unlock_bh(&ecm_sfe_ipv4_lock);
+
+	/*
+	 * Copy reference to connection - no need to ref ci as ci maintains a ref to this instance instead (this instance persists for as long as ci does)
+	 */
+	feci->ci = ci;
+
+	feci->ip_version = 4;
+
+	/*
+	 * Populate the methods and callbacks
+	 */
+	feci->ref = ecm_sfe_ported_ipv4_connection_ref;
+	feci->deref = ecm_sfe_ported_ipv4_connection_deref;
+	feci->accelerate = ecm_sfe_ported_ipv4_connection_accelerate;
+	feci->decelerate = ecm_sfe_ported_ipv4_connection_decelerate;
+	feci->accel_state_get = ecm_sfe_ported_ipv4_connection_accel_state_get;
+	feci->action_seen = ecm_sfe_ported_ipv4_connection_action_seen;
+	feci->accel_ceased = ecm_sfe_ported_ipv4_connection_accel_ceased;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	feci->state_get = ecm_sfe_ported_ipv4_connection_state_get;
+#endif
+	feci->ae_interface_number_by_dev_get = ecm_sfe_common_get_interface_number_by_dev;
+	feci->ae_interface_number_by_dev_type_get = ecm_sfe_common_get_interface_number_by_dev_type;
+	feci->ae_interface_type_get = ecm_sfe_common_get_interface_type;
+	feci->regenerate = ecm_sfe_common_connection_regenerate;
+
+	ecm_sfe_common_init_fe_info(&npci->fe_info);
+
+	feci->get_stats_bitmap = ecm_sfe_ported_ipv4_get_stats_bitmap;
+	feci->set_stats_bitmap = ecm_sfe_ported_ipv4_set_stats_bitmap;
+	feci->update_rule = ecm_sfe_common_update_rule;
+
+	if (protocol == IPPROTO_TCP) {
+		npci->ported_accelerated_count_index = ECM_SFE_PORTED_IPV4_PROTO_TCP;
+	} else if (protocol == IPPROTO_UDP) {
+		npci->ported_accelerated_count_index = ECM_SFE_PORTED_IPV4_PROTO_UDP;
+	} else {
+		DEBUG_WARN("%px: Wrong protocol: %d\n", npci, protocol);
+		DEBUG_CLEAR_MAGIC(npci);
+		ecm_db_connection_deref(ci);
+		kfree(npci);
+		return NULL;
+	}
+
+	return npci;
+}
+
+/*
+ * ecm_sfe_ported_ipv4_debugfs_init()
+ */
+bool ecm_sfe_ported_ipv4_debugfs_init(struct dentry *dentry)
+{
+	struct dentry *udp_dentry;
+
+	udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry,
+						&ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_UDP]);
+	if (!udp_dentry) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv4 udp_accelerated_count file in debugfs\n");
+		return false;
+	}
+
+	if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry,
+					&ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_TCP])) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv4 tcp_accelerated_count file in debugfs\n");
+		debugfs_remove(udp_dentry);
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-ecm/frontends/sfe/ecm_sfe_ported_ipv4.h b/qca-nss-ecm/frontends/sfe/ecm_sfe_ported_ipv4.h
new file mode 100644
index 0000000..6268d6f
--- /dev/null
+++ b/qca-nss-ecm/frontends/sfe/ecm_sfe_ported_ipv4.h
@@ -0,0 +1,23 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern bool ecm_sfe_ported_ipv4_debugfs_init(struct dentry *dentry);
+
+extern struct ecm_sfe_ported_ipv4_connection_instance *ecm_sfe_ported_ipv4_connection_instance_alloc(
+								bool can_accel,
+								int protocol,
+								struct ecm_db_connection_instance **ci);
+extern bool ecm_sfe_ported_ipv4_connection_defunct_callback(void *arg, int *accel_mode);
diff --git a/qca-nss-ecm/frontends/sfe/ecm_sfe_ported_ipv6.c b/qca-nss-ecm/frontends/sfe/ecm_sfe_ported_ipv6.c
new file mode 100644
index 0000000..a01ee76
--- /dev/null
+++ b/qca-nss-ecm/frontends/sfe/ecm_sfe_ported_ipv6.c
@@ -0,0 +1,2080 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <linux/debugfs.h>
+#include <linux/kthread.h>
+#include <linux/pkt_sched.h>
+#include <linux/string.h>
+#include <net/ip6_route.h>
+#include <net/ip6_fib.h>
+#include <net/addrconf.h>
+#include <net/ipv6.h>
+#include <net/tcp.h>
+#include <asm/unaligned.h>
+#include <asm/uaccess.h>	/* for put_user */
+#include <net/ipv6.h>
+#include <linux/inet.h>
+#include <linux/in6.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/inetdevice.h>
+#include <linux/if_arp.h>
+#include <linux/netfilter_ipv6.h>
+#include <linux/netfilter_bridge.h>
+#include <linux/if_bridge.h>
+#include <net/arp.h>
+#include <net/netfilter/nf_conntrack.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack_l4proto.h>
+#include <net/netfilter/nf_conntrack_zones.h>
+#include <net/netfilter/nf_conntrack_core.h>
+#include <net/netfilter/ipv6/nf_conntrack_ipv6.h>
+#include <net/netfilter/ipv6/nf_defrag_ipv6.h>
+#include <linux/netfilter/nf_conntrack_tftp.h>
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+#include <linux/../../net/8021q/vlan.h>
+#include <linux/if_vlan.h>
+#endif
+
+/*
+ * Debug output levels
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL ECM_SFE_PORTED_IPV6_DEBUG_LEVEL
+
+#include <sfe_api.h>
+
+#include "ecm_types.h"
+#include "ecm_db_types.h"
+#include "ecm_state.h"
+#include "ecm_tracker.h"
+#include "ecm_classifier.h"
+#include "ecm_front_end_types.h"
+#include "ecm_tracker_datagram.h"
+#include "ecm_tracker_udp.h"
+#include "ecm_tracker_tcp.h"
+#include "ecm_db.h"
+#include "ecm_classifier_default.h"
+#include "ecm_interface.h"
+#include "ecm_sfe_ported_ipv6.h"
+#include "ecm_sfe_ipv6.h"
+#include "ecm_sfe_common.h"
+#include "ecm_front_end_common.h"
+
+/*
+ * Magic numbers
+ */
+#define ECM_SFE_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC 0xEB9A
+
+/*
+ * Protocol type that ported file supports.
+ */
+enum ecm_sfe_ported_ipv6_proto_types {
+	ECM_SFE_PORTED_IPV6_PROTO_TCP = 0,
+	ECM_SFE_PORTED_IPV6_PROTO_UDP,
+	ECM_SFE_PORTED_IPV6_PROTO_MAX
+
+};
+
+/*
+ * struct ecm_sfe_ipv6_ported_connection_instance
+ *	A connection specific front end instance for PORTED connections
+ */
+struct ecm_sfe_ported_ipv6_connection_instance {
+	struct ecm_front_end_connection_instance base;		/* Base class */
+	uint8_t ported_accelerated_count_index;			/* Index value of accelerated count array (UDP or TCP) */
+#ifdef CONFIG_XFRM
+	enum ecm_sfe_ipsec_state flow_ipsec_state;	/* Flow traffic need ipsec process or not */
+	enum ecm_sfe_ipsec_state return_ipsec_state;	/* Return traffic need ipsec process or not */
+#endif
+	struct ecm_sfe_common_fe_info fe_info;		/* Front end information */
+
+#if (DEBUG_LEVEL > 0)
+	uint16_t magic;
+#endif
+};
+
+static int ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_MAX] = {0};
+						/* Array of Number of TCP and UDP connections currently offloaded */
+
+/*
+ * Expose what should be a static flag in the TCP connection tracker.
+ */
+#ifdef ECM_OPENWRT_SUPPORT
+extern int nf_ct_tcp_no_window_check;
+#endif
+extern int nf_ct_tcp_be_liberal;
+
+/*
+ * ecm_sfe_ported_ipv6_get_stats_bitmap()
+ *	Get bit map
+ */
+static uint32_t ecm_sfe_ported_ipv6_get_stats_bitmap(struct ecm_front_end_connection_instance *feci, ecm_db_obj_dir_t dir)
+{
+	struct ecm_sfe_ported_ipv6_connection_instance *npci = (struct ecm_sfe_ported_ipv6_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	return ecm_sfe_common_get_stats_bitmap(&npci->fe_info, dir);
+}
+
+/*
+ * ecm_sfe_ported_ipv6_set_stats_bitmap()
+ *	Set bit map
+ */
+static void ecm_sfe_ported_ipv6_set_stats_bitmap(struct ecm_front_end_connection_instance *feci, ecm_db_obj_dir_t dir, uint8_t bit)
+{
+	struct ecm_sfe_ported_ipv6_connection_instance *npci = (struct ecm_sfe_ported_ipv6_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	ecm_sfe_common_set_stats_bitmap(&npci->fe_info, dir, bit);
+}
+
+/*
+ * ecm_sfe_ported_ipv6_connection_callback()
+ *	Callback for handling create ack/nack calls.
+ */
+static void ecm_sfe_ported_ipv6_connection_callback(void *app_data, struct sfe_ipv6_msg *nim)
+{
+	struct sfe_ipv6_rule_create_msg *nircm = &nim->msg.rule_create;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_sfe_ported_ipv6_connection_instance *npci;
+	ip_addr_t flow_ip;
+	ip_addr_t return_ip;
+	ecm_front_end_acceleration_mode_t result_mode;
+	bool is_defunct = false;
+
+	/*
+	 * Is this a response to a create message?
+	 */
+	if (nim->cm.type != SFE_TX_CREATE_RULE_MSG) {
+		DEBUG_ERROR("%px: ported create callback with improper type: %d, serial: %u\n", nim, nim->cm.type, serial);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: create callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	npci = (struct ecm_sfe_ported_ipv6_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	ECM_SFE_IPV6_ADDR_TO_IP_ADDR(flow_ip, nircm->tuple.flow_ip);
+	ECM_SFE_IPV6_ADDR_TO_IP_ADDR(return_ip, nircm->tuple.return_ip);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_sfe_ipv6_accel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: accelerate response for connection: %px, serial: %u\n", npci, feci->ci, serial);
+	DEBUG_TRACE("%px: rule_flags: %x, valid_flags: %x\n", npci, nircm->rule_flags, nircm->valid_flags);
+	DEBUG_TRACE("%px: flow_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", npci, ECM_IP_ADDR_TO_OCTAL(flow_ip), nircm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", npci, ECM_IP_ADDR_TO_OCTAL(return_ip), nircm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", npci, nircm->tuple.protocol);
+
+	/*
+	 * Handle the creation result code.
+	 */
+	DEBUG_TRACE("%px: response: %d\n", npci, nim->cm.response);
+	if (nim->cm.response != SFE_CMN_RESPONSE_ACK) {
+		/*
+		 * Creation command failed (specific reason ignored).
+		 */
+		DEBUG_TRACE("%px: accel nack: %d\n", npci, nim->cm.error);
+		spin_lock_bh(&feci->lock);
+		DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+		feci->stats.ae_nack++;
+		feci->stats.ae_nack_total++;
+		if (feci->stats.ae_nack >= feci->stats.ae_nack_limit) {
+			/*
+			 * Too many SFE rejections
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_ACCEL_ENGINE;
+		} else {
+			/*
+			 * Revert to decelerated
+			 */
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+		}
+
+		/*
+		 * If connection is now defunct then set mode to ensure no further accel attempts occur
+		 */
+		if (feci->is_defunct) {
+			result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT;
+		}
+
+		spin_lock_bh(&ecm_sfe_ipv6_lock);
+		_ecm_sfe_ipv6_accel_pending_clear(feci, result_mode);
+		spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Unexpected mode: %d\n", ci, feci->accel_mode);
+
+	/*
+	 * If a flush occured before we got the ACK then our acceleration was effectively cancelled on us
+	 * GGG TODO This is a workaround for a SFE message OOO quirk, this should eventually be removed.
+	 */
+	if (feci->stats.flush_happened) {
+		feci->stats.flush_happened = false;
+
+		/*
+		 * Increment the no-action counter.  Our connection was decelerated on us with no action occurring.
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_lock_bh(&ecm_sfe_ipv6_lock);
+		_ecm_sfe_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	/*
+	 * Create succeeded
+	 */
+
+	/*
+	 * Clear any nack count
+	 */
+	feci->stats.ae_nack = 0;
+
+	/*
+	 * Clear the "accelerate pending" state and move to "accelerated" state bumping
+	 * the accelerated counters to match our new state.
+	 *
+	 * Decelerate may have been attempted while we were "pending accel" and
+	 * this function will return true if that was the case.
+	 * If decelerate was pending then we need to begin deceleration :-(
+	 */
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+
+	ecm_sfe_ported_ipv6_accelerated_count[npci->ported_accelerated_count_index]++;	/* Protocol specific counter */
+	ecm_sfe_ipv6_accelerated_count++;		/* General running counter */
+
+	if (!_ecm_sfe_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_ACCEL)) {
+		/*
+		 * Increment the no-action counter, this is reset if offload action is seen
+		 */
+		feci->stats.no_action_seen++;
+
+		spin_unlock_bh(&ecm_sfe_ipv6_lock);
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connection.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_INFO("%px: Decelerate was pending\n", ci);
+
+	/*
+	 * Check if the pending decelerate was done with the defunct process.
+	 * If it was, set the is_defunct flag of the feci to false for re-try.
+	 */
+	if (feci->is_defunct) {
+		is_defunct = feci->is_defunct;
+		feci->is_defunct = false;
+	}
+
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * If the pending decelerate was done through defunct process, we should
+	 * re-try it here with the same defunct function, because the purpose of that
+	 * process is to remove the connection from the database as well after decelerating it.
+	 */
+	if (is_defunct) {
+		ecm_db_connection_make_defunct(ci);
+	} else {
+		feci->decelerate(feci);
+	}
+
+	/*
+	 * Release the connection.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_sfe_ipv6_fast_xmit_set()
+ *	set the fast_xmit in the create message
+ */
+static void ecm_sfe_ipv6_fast_xmit_set(struct sfe_ipv6_rule_create_msg *msg)
+{
+	s32 interface_num;
+
+	rcu_read_lock_bh();
+
+	interface_num = msg->conn_rule.flow_top_interface_num;
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE) {
+		interface_num = msg->conn_rule.flow_interface_num;
+	}
+	if (ecm_sfe_common_fast_xmit_check(interface_num)) {
+		msg->rule_flags |= SFE_RULE_CREATE_FLAG_RETURN_TRANSMIT_FAST;
+	}
+
+	interface_num = msg->conn_rule.return_top_interface_num;
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE) {
+		interface_num = msg->conn_rule.return_interface_num;
+	}
+	if (ecm_sfe_common_fast_xmit_check(interface_num)) {
+		msg->rule_flags |= SFE_RULE_CREATE_FLAG_FLOW_TRANSMIT_FAST;
+	}
+
+	rcu_read_unlock_bh();
+}
+
+/*
+ * ecm_sfe_ported_ipv6_connection_accelerate()
+ *	Accelerate a connection
+ */
+static void ecm_sfe_ported_ipv6_connection_accelerate(struct ecm_front_end_connection_instance *feci,
+									struct ecm_classifier_process_response *pr, bool is_l2_encap,
+									struct nf_conn *ct, struct sk_buff *skb)
+{
+	struct ecm_sfe_ported_ipv6_connection_instance *npci = (struct ecm_sfe_ported_ipv6_connection_instance *)feci;
+	uint16_t regen_occurrances;
+	int protocol;
+	int32_t from_ifaces_first;
+	int32_t to_ifaces_first;
+	struct ecm_db_iface_instance *from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX];
+	struct ecm_db_iface_instance *from_sfe_iface;
+	struct ecm_db_iface_instance *to_sfe_iface;
+	int32_t from_sfe_iface_id;
+	int32_t to_sfe_iface_id;
+	uint8_t from_sfe_iface_address[ETH_ALEN];
+	uint8_t to_sfe_iface_address[ETH_ALEN];
+	struct sfe_ipv6_msg nim;
+	struct sfe_ipv6_rule_create_msg *nircm;
+	struct ecm_classifier_instance *assignments[ECM_CLASSIFIER_TYPES];
+	int aci_index;
+	int assignment_count;
+	sfe_tx_status_t sfe_tx_status;
+	int32_t list_index;
+	int32_t interface_type_counts[ECM_DB_IFACE_TYPE_COUNT];
+	bool rule_invalid;
+	ip_addr_t src_ip;
+	ip_addr_t dest_ip;
+	ecm_front_end_acceleration_mode_t result_mode;
+	uint32_t l2_accel_bits = (ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED | ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED);
+	ecm_sfe_common_l2_accel_check_callback_t l2_accel_check;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	/*
+	 * Get the re-generation occurrance counter of the connection.
+	 * We compare it again at the end - to ensure that the rule construction has seen no generation
+	 * changes during rule creation.
+	 */
+	regen_occurrances = ecm_db_connection_regeneration_occurrances_get(feci->ci);
+
+	/*
+	 * Test if acceleration is permitted
+	 */
+	if (!ecm_sfe_ipv6_accel_pending_set(feci)) {
+		DEBUG_TRACE("%px: Acceleration not permitted: %px skb=%px\n", feci, feci->ci, skb);
+		return;
+	}
+
+	/*
+	 * Okay construct an accel command.
+	 * Initialise creation structure.
+	 * NOTE: We leverage the app_data void pointer to be our 32 bit connection serial number.
+	 * When we get it back we re-cast it to a uint32 and do a faster connection lookup.
+	 */
+	memset(&nim, 0, sizeof(struct sfe_ipv6_msg));
+	sfe_ipv6_msg_init(&nim, SFE_SPECIAL_INTERFACE_IPV6, SFE_TX_CREATE_RULE_MSG,
+			sizeof(struct sfe_ipv6_rule_create_msg),
+			ecm_sfe_ported_ipv6_connection_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nircm = &nim.msg.rule_create;
+	nircm->valid_flags = 0;
+	nircm->rule_flags = 0;
+
+	/*
+	 * Initialize VLAN tag information
+	 */
+	nircm->vlan_primary_rule.ingress_vlan_tag = SFE_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_primary_rule.egress_vlan_tag = SFE_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.ingress_vlan_tag = SFE_VLAN_ID_NOT_CONFIGURED;
+	nircm->vlan_secondary_rule.egress_vlan_tag = SFE_VLAN_ID_NOT_CONFIGURED;
+
+	/*
+	 * Get the interface lists of the connection, we must have at least one interface in the list to continue
+	 */
+	from_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, from_ifaces, ECM_DB_OBJ_DIR_FROM);
+	if (from_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in from_interfaces list!\n", npci);
+		goto ported_accel_bad_rule;
+	}
+
+	to_ifaces_first = ecm_db_connection_interfaces_get_and_ref(feci->ci, to_ifaces, ECM_DB_OBJ_DIR_TO);
+	if (to_ifaces_first == ECM_DB_IFACE_HEIRARCHY_MAX) {
+		DEBUG_WARN("%px: Accel attempt failed - no interfaces in to_interfaces list!\n", npci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * First interface in each must be a known sfe interface
+	 */
+	from_sfe_iface = from_ifaces[from_ifaces_first];
+	to_sfe_iface = to_ifaces[to_ifaces_first];
+	from_sfe_iface_id = ecm_db_iface_ae_interface_identifier_get(from_sfe_iface);
+	to_sfe_iface_id = ecm_db_iface_ae_interface_identifier_get(to_sfe_iface);
+	if ((from_sfe_iface_id < 0) || (to_sfe_iface_id < 0)) {
+		DEBUG_TRACE("%px: from_sfe_iface_id: %d, to_sfe_iface_id: %d\n", npci, from_sfe_iface_id, to_sfe_iface_id);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * New rule being created
+	 */
+	nircm->valid_flags |= SFE_RULE_CREATE_CONN_VALID;
+
+	/*
+	 * Set interface numbers involved in accelerating this connection.
+	 * These are the outer facing addresses from the heirarchy interface lists we got above.
+	 * These may be overridden later if we detect special interface types e.g. ipsec.
+	 */
+	nircm->conn_rule.flow_interface_num = from_sfe_iface_id;
+	nircm->conn_rule.return_interface_num = to_sfe_iface_id;
+
+	/*
+	 * Check which side of the connection can support L2 acceleration.
+	 * The check is done only for the routed flows and if the L2 feature is enabled.
+	 */
+	if (sfe_is_l2_feature_enabled() && ecm_db_connection_is_routed_get(feci->ci)) {
+		rcu_read_lock();
+		l2_accel_check = rcu_dereference(ecm_sfe_cb.l2_accel_check);
+		if (l2_accel_check) {
+			struct ecm_sfe_common_tuple l2_accel_tuple;
+
+			ecm_sfe_common_tuple_set(feci, from_sfe_iface_id, to_sfe_iface_id, &l2_accel_tuple);
+
+			l2_accel_bits = l2_accel_check(&l2_accel_tuple);
+		}
+		rcu_read_unlock();
+	}
+
+	/*
+	 * Set interface numbers involved in accelerating this connection.
+	 * These are the inner facing addresses from the heirarchy interface lists we got above.
+	 */
+	nim.msg.rule_create.conn_rule.flow_top_interface_num = ecm_db_iface_interface_identifier_get(from_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX-1]);
+	nim.msg.rule_create.conn_rule.return_top_interface_num = ecm_db_iface_interface_identifier_get(to_ifaces[ECM_DB_IFACE_HEIRARCHY_MAX-1]);
+
+	/*
+	 * We know that each outward facing interface is known to the SFE and so this connection could be accelerated.
+	 * However the lists may also specify other interesting details that must be included in the creation command,
+	 * for example, ethernet MAC, VLAN tagging or PPPoE session information.
+	 * We get this information by walking from the outer to the innermost interface for each list and examine the interface types.
+	 *
+	 * Start with the 'from' (src) side.
+	 * NOTE: The lists may contain a complex heirarchy of similar type of interface e.g. multiple vlans or tunnels within tunnels.
+	 * This SFE cannot handle that - there is no way to describe this in the rule - if we see multiple types that would conflict we have to abort.
+	 */
+	DEBUG_TRACE("%px: Examine from/src heirarchy list. skb=%px\n", npci, skb);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = from_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+		struct ecm_db_interface_info_pppoe pppoe_info;
+#endif
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_in_dev = NULL;
+#endif
+
+		ii = from_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px (%s %d %d), type: %d (%s)\n",
+				npci, list_index, ii,
+				ii->name, ii->interface_identifier, ii->ae_interface_identifier,
+				ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_BRIDGE, list_index, from_ifaces_first) && (l2_accel_bits & ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_FROM, ECM_DB_IFACE_TYPE_BRIDGE);
+			}
+
+			ecm_db_iface_bridge_address_get(ii, from_sfe_iface_address);
+			if (is_valid_ether_addr(from_sfe_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_sfe_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+			}
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", npci, from_sfe_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_OVS_BRIDGE, list_index, from_ifaces_first) && (l2_accel_bits & ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_FROM, ECM_DB_IFACE_TYPE_OVS_BRIDGE);
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, from_sfe_iface_address);
+			if (is_valid_ether_addr(from_sfe_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_sfe_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_FLOW_VALID;
+				nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+			}
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", npci, from_sfe_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", npci);
+				break;
+			}
+
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, from_sfe_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", npci, from_sfe_iface_address);
+			break;
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", npci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * PPPoE is supported only when L2 feature flag is enabled
+			 */
+			if (!sfe_is_l2_feature_enabled()) {
+				DEBUG_TRACE("%px: PPPoE - unsupported\n", npci);
+				break;
+			}
+
+			/*
+			 * If external module decide that L2 acceleration is not allowed, we should return
+			 * without setting PPPoE parameters.
+			 */
+			if (!(l2_accel_bits & ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED)) {
+				DEBUG_TRACE("%px: L2 acceleration is not allowed for the PPPoE interface\n", npci);
+				break;
+			}
+
+			feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_FROM, ECM_DB_IFACE_TYPE_PPPOE);
+
+			/*
+			 * Copy pppoe session info to the creation structure.
+			 */
+			ecm_db_iface_pppoe_session_info_get(ii, &pppoe_info);
+
+			nircm->pppoe_rule.flow_pppoe_session_id = pppoe_info.pppoe_session_id;
+			memcpy(nircm->pppoe_rule.flow_pppoe_remote_mac, pppoe_info.remote_mac, ETH_ALEN);
+			nircm->valid_flags |= SFE_RULE_CREATE_PPPOE_DECAP_VALID;
+			nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+
+			DEBUG_TRACE("%px: PPPoE - session: %x, mac: %pM\n", npci,
+					nircm->pppoe_rule.flow_pppoe_session_id,
+					nircm->pppoe_rule.flow_pppoe_remote_mac);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", npci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", npci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_in_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_in_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_in_dev, pr->return_qos_tag);
+				dev_put(vlan_in_dev);
+				vlan_in_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.ingress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.ingress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= SFE_RULE_CREATE_VLAN_VALID;
+
+			if (sfe_is_l2_feature_enabled() && (l2_accel_bits & ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_FROM, ECM_DB_IFACE_TYPE_VLAN);
+
+				if (is_valid_ether_addr(vlan_info.address)) {
+					ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, vlan_info.address);
+					nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_FLOW_VALID;
+					nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+				}
+			}
+
+			/*
+			 * If we have not yet got an ethernet mac then take this one
+			 * (very unlikely as mac should have been propagated to the slave (outer) device)
+			 */
+			if (interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET] == 0) {
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", npci, vlan_info.address);
+			}
+			DEBUG_TRACE("%px: vlan tag: %x\n", npci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", npci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_MACVLAN:
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_MACVLAN, list_index, from_ifaces_first) && (l2_accel_bits & ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_FROM, ECM_DB_IFACE_TYPE_MACVLAN);
+			}
+
+			ecm_db_iface_macvlan_address_get(ii, from_sfe_iface_address);
+			ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_sfe_iface_address);
+			nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_FLOW_VALID;
+			nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+
+			DEBUG_TRACE("%px: Macvlan - mac: %pM\n", npci, from_sfe_iface_address);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: MACVLAN - unsupported\n", npci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", npci);
+				break;
+			}
+			nircm->conn_rule.flow_interface_num = SFE_SPECIAL_INTERFACE_IPSEC;
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", npci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_LAG:
+#ifdef ECM_INTERFACE_BOND_ENABLE
+			if (sfe_is_l2_feature_enabled() && (l2_accel_bits & ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE;
+				/*
+				 * LAG device gets its stats by summing up all stats of its
+				 * slaves (i.e. 'ethx' devices). Please see bond_get_stats()
+				 * in linux-5.4/drivers/net/bonding/bond_main.c.
+				 * So no need to call feci->set_stats_bitmap().
+				 */
+
+				ecm_db_iface_lag_address_get(ii, from_sfe_iface_address);
+				if (is_valid_ether_addr(from_sfe_iface_address)) {
+					ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, from_sfe_iface_address);
+					nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_FLOW_VALID;
+					nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+				}
+				DEBUG_TRACE("%px: LAG - mac: %pM\n", npci, from_sfe_iface_address);
+			}
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: LAG - unsupported\n", npci);
+#endif
+			break;
+
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", npci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+	if (rule_invalid) {
+		DEBUG_WARN("%px: from/src Rule invalid\n", npci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * Now examine the TO / DEST heirarchy list to construct the destination part of the rule
+	 */
+	DEBUG_TRACE("%px: Examine to/dest heirarchy list\n", npci);
+	memset(interface_type_counts, 0, sizeof(interface_type_counts));
+	rule_invalid = false;
+	for (list_index = to_ifaces_first; !rule_invalid && (list_index < ECM_DB_IFACE_HEIRARCHY_MAX); list_index++) {
+		struct ecm_db_iface_instance *ii;
+		ecm_db_iface_type_t ii_type;
+		char *ii_name;
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+		struct ecm_db_interface_info_pppoe pppoe_info;
+#endif
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+		struct ecm_db_interface_info_vlan vlan_info;
+		uint32_t vlan_value = 0;
+		struct net_device *vlan_out_dev = NULL;
+#endif
+
+		ii = to_ifaces[list_index];
+		ii_type = ecm_db_iface_type_get(ii);
+		ii_name = ecm_db_interface_type_to_string(ii_type);
+		DEBUG_TRACE("%px: list_index: %d, ii: %px (%s %d %d), type: %d (%s)\n",
+				npci, list_index, ii,
+				ii->name, ii->interface_identifier, ii->ae_interface_identifier,
+				ii_type, ii_name);
+
+		/*
+		 * Extract information from this interface type if it is applicable to the rule.
+		 * Conflicting information may cause accel to be unsupported.
+		 */
+		switch (ii_type) {
+		case ECM_DB_IFACE_TYPE_BRIDGE:
+			DEBUG_TRACE("%px: Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_BRIDGE, list_index, to_ifaces_first) && (l2_accel_bits & ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_TO, ECM_DB_IFACE_TYPE_BRIDGE);
+			}
+
+			ecm_db_iface_bridge_address_get(ii, to_sfe_iface_address);
+
+			if (is_valid_ether_addr(to_sfe_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_sfe_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+			}
+			DEBUG_TRACE("%px: Bridge - mac: %pM\n", npci, to_sfe_iface_address);
+			break;
+
+		case ECM_DB_IFACE_TYPE_OVS_BRIDGE:
+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE
+			DEBUG_TRACE("%px: OVS Bridge\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Cannot cascade bridges
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: OVS Bridge - ignore additional\n", npci);
+				break;
+			}
+
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_OVS_BRIDGE, list_index, to_ifaces_first) && (l2_accel_bits & ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_TO, ECM_DB_IFACE_TYPE_OVS_BRIDGE);
+			}
+
+			ecm_db_iface_ovs_bridge_address_get(ii, to_sfe_iface_address);
+			if (is_valid_ether_addr(to_sfe_iface_address)) {
+				ether_addr_copy((uint8_t *)nircm->src_mac_rule.flow_src_mac, to_sfe_iface_address);
+				nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_RETURN_VALID;
+				nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+			}
+			DEBUG_TRACE("%px: OVS Bridge - mac: %pM\n", npci, to_sfe_iface_address);
+#else
+			rule_invalid = true;
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_ETHERNET:
+			DEBUG_TRACE("%px: Ethernet\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Ignore additional mac addresses, these are usually as a result of address propagation
+				 * from bridges down to ports etc.
+				 */
+				DEBUG_TRACE("%px: Ethernet - ignore additional\n", npci);
+				break;
+			}
+
+			/*
+			 * Can only handle one MAC, the first outermost mac.
+			 */
+			ecm_db_iface_ethernet_address_get(ii, to_sfe_iface_address);
+			DEBUG_TRACE("%px: Ethernet - mac: %pM\n", npci, to_sfe_iface_address);
+			break;
+		case ECM_DB_IFACE_TYPE_PPPOE:
+#ifdef ECM_INTERFACE_PPPOE_ENABLE
+			/*
+			 * More than one PPPoE in the list is not valid!
+			 */
+			if (interface_type_counts[ii_type] != 0) {
+				DEBUG_TRACE("%px: PPPoE - additional unsupported\n", npci);
+				rule_invalid = true;
+				break;
+			}
+
+			/*
+			 * PPPoE is supported only when L2 feature flag is enabled
+			 */
+			if (!sfe_is_l2_feature_enabled()) {
+				DEBUG_TRACE("%px: PPPoE - unsupported\n", npci);
+				break;
+			}
+
+			/*
+			 * If external module decide that L2 acceleration is not allowed, we should return
+			 * without setting PPPoE parameters.
+			 */
+			if (!(l2_accel_bits & ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED)) {
+				DEBUG_TRACE("%px: L2 acceleration is not allowed for the PPPoE interface\n", npci);
+				break;
+			}
+
+			feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_FROM, ECM_DB_IFACE_TYPE_PPPOE);
+
+			/*
+			 * Copy pppoe session info to the creation structure.
+			 */
+			ecm_db_iface_pppoe_session_info_get(ii, &pppoe_info);
+			nircm->pppoe_rule.return_pppoe_session_id = pppoe_info.pppoe_session_id;
+			memcpy(nircm->pppoe_rule.return_pppoe_remote_mac, pppoe_info.remote_mac, ETH_ALEN);
+			nircm->valid_flags |= SFE_RULE_CREATE_PPPOE_ENCAP_VALID;
+			nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+
+			DEBUG_TRACE("%px: PPPoE - session: %x, mac: %pM\n", npci,
+				    nircm->pppoe_rule.return_pppoe_session_id,
+				    nircm->pppoe_rule.return_pppoe_remote_mac);
+#else
+			rule_invalid = true;
+#endif
+			break;
+		case ECM_DB_IFACE_TYPE_VLAN:
+#ifdef ECM_INTERFACE_VLAN_ENABLE
+			DEBUG_TRACE("%px: VLAN\n", npci);
+			if (interface_type_counts[ii_type] > 1) {
+				/*
+				 * Can only support two vlans
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: VLAN - additional unsupported\n", npci);
+				break;
+			}
+			ecm_db_iface_vlan_info_get(ii, &vlan_info);
+			vlan_value = ((vlan_info.vlan_tpid << 16) | vlan_info.vlan_tag);
+
+			/*
+			 * Look up the vlan device and incorporate the vlan priority into the vlan_value
+			 */
+			vlan_out_dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii));
+			if (vlan_out_dev) {
+				vlan_value |= vlan_dev_get_egress_qos_mask(vlan_out_dev, pr->flow_qos_tag);
+				dev_put(vlan_out_dev);
+				vlan_out_dev = NULL;
+			}
+
+			/*
+			 * Primary or secondary (QinQ) VLAN?
+			 */
+			if (interface_type_counts[ii_type] == 0) {
+				nircm->vlan_primary_rule.egress_vlan_tag = vlan_value;
+			} else {
+				nircm->vlan_secondary_rule.egress_vlan_tag = vlan_value;
+			}
+			nircm->valid_flags |= SFE_RULE_CREATE_VLAN_VALID;
+
+			if (sfe_is_l2_feature_enabled() && (l2_accel_bits & ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_TO, ECM_DB_IFACE_TYPE_VLAN);
+
+				if (is_valid_ether_addr(vlan_info.address)) {
+					ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, vlan_info.address);
+					nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_RETURN_VALID;
+					nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+				}
+			}
+
+			/*
+			 * If we have not yet got an ethernet mac then take this one
+			 * (very unlikely as mac should have been propagated to the slave (outer) device)
+			 */
+			if (interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET] == 0) {
+				interface_type_counts[ECM_DB_IFACE_TYPE_ETHERNET]++;
+				DEBUG_TRACE("%px: VLAN use mac: %pM\n", npci, vlan_info.address);
+			}
+			DEBUG_TRACE("%px: vlan tag: %x\n", npci, vlan_value);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: VLAN - unsupported\n", npci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_MACVLAN:
+#ifdef ECM_INTERFACE_MACVLAN_ENABLE
+			if (ecm_sfe_common_is_l2_iface_supported(ECM_DB_IFACE_TYPE_MACVLAN, list_index, to_ifaces_first) && (l2_accel_bits & ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+				feci->set_stats_bitmap(feci, ECM_DB_OBJ_DIR_TO, ECM_DB_IFACE_TYPE_MACVLAN);
+			}
+
+			ecm_db_iface_macvlan_address_get(ii, to_sfe_iface_address);
+			ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_sfe_iface_address);
+			nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_RETURN_VALID;
+			nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+
+			DEBUG_TRACE("%px: Macvlan - mac: %pM\n", npci, to_sfe_iface_address);
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: MACVLAN - unsupported\n", npci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_IPSEC_TUNNEL:
+#ifdef ECM_INTERFACE_IPSEC_ENABLE
+			DEBUG_TRACE("%px: IPSEC\n", npci);
+			if (interface_type_counts[ii_type] != 0) {
+				/*
+				 * Can only support one ipsec
+				 */
+				rule_invalid = true;
+				DEBUG_TRACE("%px: IPSEC - additional unsupported\n", npci);
+				break;
+			}
+			nircm->conn_rule.return_interface_num = SFE_SPECIAL_INTERFACE_IPSEC;
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: IPSEC - unsupported\n", npci);
+#endif
+			break;
+
+		case ECM_DB_IFACE_TYPE_LAG:
+#ifdef ECM_INTERFACE_BOND_ENABLE
+			if (sfe_is_l2_feature_enabled() && (l2_accel_bits & ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE;
+				/*
+				 * LAG device gets its stats by summing up all stats of its
+				 * slaves (i.e. 'ethx' devices). Please see bond_get_stats()
+				 * in linux-5.4/drivers/net/bonding/bond_main.c.
+				 * So no need to call feci->set_stats_bitmap().
+				 */
+
+				ecm_db_iface_lag_address_get(ii, to_sfe_iface_address);
+				if (is_valid_ether_addr(to_sfe_iface_address)) {
+					ether_addr_copy((uint8_t *)nircm->src_mac_rule.return_src_mac, to_sfe_iface_address);
+					nircm->src_mac_rule.mac_valid_flags |= SFE_SRC_MAC_RETURN_VALID;
+					nircm->valid_flags |= SFE_RULE_CREATE_SRC_MAC_VALID;
+				}
+				DEBUG_TRACE("%px: LAG - mac: %pM\n", npci, to_sfe_iface_address);
+			}
+#else
+			rule_invalid = true;
+			DEBUG_TRACE("%px: LAG - unsupported\n", npci);
+#endif
+			break;
+
+		default:
+			DEBUG_TRACE("%px: Ignoring: %d (%s)\n", npci, ii_type, ii_name);
+		}
+
+		/*
+		 * Seen an interface of this type
+		 */
+		interface_type_counts[ii_type]++;
+	}
+	if (rule_invalid) {
+		DEBUG_WARN("%px: to/dest Rule invalid\n", npci);
+		ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+		ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+		goto ported_accel_bad_rule;
+	}
+
+	/*
+	 * Routed or bridged?
+	 */
+	if (ecm_db_connection_is_routed_get(feci->ci)) {
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_ROUTED;
+	} else {
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_BRIDGE_FLOW;
+		if (is_l2_encap) {
+			nircm->rule_flags |= SFE_RULE_CREATE_FLAG_L2_ENCAP;
+		}
+	}
+
+	if (ecm_interface_src_check) {
+		DEBUG_INFO("%px: Source interface check flag is enabled\n", npci);
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_FLOW_SRC_INTERFACE_CHECK;
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_RETURN_SRC_INTERFACE_CHECK;
+	}
+
+	/*
+	 * Enable source interface check without flushing the rule for this flow to re-inject the packet to
+	 * the network stack in SFE driver after the first pass of the packet coming with the L2 interface.
+	 * In the second pass, the packet will come to SFE with the L3 interface. If there are more than 3 interfaces
+	 * in the hierarchy, the packet will be re-injected to the stack until the flows input interface matches with the
+	 * rule's match_dev.
+	 */
+	if (!(l2_accel_bits & ECM_SFE_COMMON_FLOW_L2_ACCEL_ALLOWED)) {
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_FLOW_SRC_INTERFACE_CHECK;
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_FLOW_SRC_INTERFACE_CHECK_NO_FLUSH;
+	}
+
+	if (!(l2_accel_bits & ECM_SFE_COMMON_RETURN_L2_ACCEL_ALLOWED)) {
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_RETURN_SRC_INTERFACE_CHECK;
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_RETURN_SRC_INTERFACE_CHECK_NO_FLUSH;
+	}
+
+	/*
+	 * Set up the flow and return qos tags
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_QOS_TAG) {
+		nircm->qos_rule.flow_qos_tag = (uint32_t)pr->flow_qos_tag;
+		nircm->qos_rule.return_qos_tag = (uint32_t)pr->return_qos_tag;
+		nircm->valid_flags |= SFE_RULE_CREATE_QOS_VALID;
+	}
+
+#ifdef ECM_CLASSIFIER_DSCP_ENABLE
+	/*
+	 * DSCP information?
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_DSCP) {
+		nircm->dscp_rule.flow_dscp = pr->flow_dscp;
+		nircm->dscp_rule.return_dscp = pr->return_dscp;
+		nircm->rule_flags |= SFE_RULE_CREATE_FLAG_DSCP_MARKING;
+		nircm->valid_flags |= SFE_RULE_CREATE_DSCP_MARKING_VALID;
+	}
+
+	/*
+	 * Set up the flow and return mark
+	 */
+	if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_MARK) {
+		nircm->mark_rule.flow_mark = (uint32_t)pr->flow_mark;
+		nircm->mark_rule.return_mark = (uint32_t)pr->return_mark;
+		nircm->valid_flags |= SFE_RULE_CREATE_MARK_VALID;
+	}
+#endif
+
+#ifdef ECM_CLASSIFIER_OVS_ENABLE
+	if (ecm_front_end_is_feature_supported(ECM_FE_FEATURE_OVS_VLAN)) {
+		/*
+		 * Copy the both primary and secondary (if exist) VLAN tags.
+		 */
+		if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_TAG) {
+			nircm->vlan_primary_rule.ingress_vlan_tag = pr->ingress_vlan_tag[0];
+			nircm->vlan_primary_rule.egress_vlan_tag = pr->egress_vlan_tag[0];
+			nircm->valid_flags |= SFE_RULE_CREATE_VLAN_VALID;
+		}
+
+		if (pr->process_actions & ECM_CLASSIFIER_PROCESS_ACTION_OVS_VLAN_QINQ_TAG) {
+			nircm->vlan_secondary_rule.ingress_vlan_tag = pr->ingress_vlan_tag[1];
+			nircm->vlan_secondary_rule.egress_vlan_tag = pr->egress_vlan_tag[1];
+		}
+	}
+#endif
+
+#ifdef CONFIG_XFRM
+	nircm->direction_rule.flow_accel = (npci->flow_ipsec_state != ECM_SFE_IPSEC_STATE_TO_ENCRYPT);
+	nircm->direction_rule.return_accel = (npci->return_ipsec_state != ECM_SFE_IPSEC_STATE_TO_ENCRYPT);
+	if (!nircm->direction_rule.flow_accel || !nircm->direction_rule.return_accel) {
+		nircm->valid_flags |= SFE_RULE_CREATE_DIRECTION_VALID;
+	}
+#endif
+	protocol = ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * Set protocol
+	 */
+	nircm->tuple.protocol = (int32_t)protocol;
+
+	/*
+	 * The flow_ip is where the connection established from
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	ECM_IP_ADDR_TO_SFE_IPV6_ADDR(nircm->tuple.flow_ip, src_ip);
+
+	/*
+	 * The dest_ip is where the connection is established to
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, dest_ip);
+	ECM_IP_ADDR_TO_SFE_IPV6_ADDR(nircm->tuple.return_ip, dest_ip);
+
+	/*
+	 * Same approach as above for port information
+	 */
+	nircm->tuple.flow_ident = htons(ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM));
+	nircm->tuple.return_ident = htons(ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO));
+
+	/*
+	 * Get mac addresses.
+	 * The src_mac is the mac address of the node that established the connection.
+	 * This will work whether the from_node is LAN (egress) or WAN (ingress).
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, (uint8_t *)nircm->conn_rule.flow_mac);
+
+	/*
+	 * The dest_mac is more complex.  For egress it is the node address of the 'to' side of the connection.
+	 * For ingress it is the node adress of the NAT'ed 'to' IP.
+	 * Essentially it is the MAC of node associated with create.dest_ip and this is "to nat" side.
+	 */
+	ecm_db_connection_node_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, (uint8_t *)nircm->conn_rule.return_mac);
+
+	/*
+	 * Get MTU information
+	 */
+	nircm->conn_rule.flow_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_FROM);
+	nircm->conn_rule.return_mtu = (uint32_t)ecm_db_connection_iface_mtu_get(feci->ci, ECM_DB_OBJ_DIR_TO);
+
+	if (protocol == IPPROTO_TCP) {
+		/*
+		 * Need window scaling information from conntrack if available
+		 * Start by looking up the conntrack connection
+		 */
+		if (!ct) {
+			/*
+			 * No conntrack so no need to check window sequence space
+			 */
+			DEBUG_TRACE("%px: TCP Accel no ct from conn %px to get window data\n", npci, feci->ci);
+			nircm->rule_flags |= SFE_RULE_CREATE_FLAG_NO_SEQ_CHECK;
+		} else {
+			int flow_dir;
+			int return_dir;
+
+			ecm_front_end_flow_and_return_directions_get(ct, src_ip, 6, &flow_dir, &return_dir);
+
+			DEBUG_TRACE("%px: TCP Accel Get window data from ct %px for conn %px\n", npci, ct, feci->ci);
+			spin_lock_bh(&ct->lock);
+			nircm->tcp_rule.flow_window_scale = ct->proto.tcp.seen[flow_dir].td_scale;
+			nircm->tcp_rule.flow_max_window = ct->proto.tcp.seen[flow_dir].td_maxwin;
+			nircm->tcp_rule.flow_end = ct->proto.tcp.seen[flow_dir].td_end;
+			nircm->tcp_rule.flow_max_end = ct->proto.tcp.seen[flow_dir].td_maxend;
+			nircm->tcp_rule.return_window_scale = ct->proto.tcp.seen[return_dir].td_scale;
+			nircm->tcp_rule.return_max_window = ct->proto.tcp.seen[return_dir].td_maxwin;
+			nircm->tcp_rule.return_end = ct->proto.tcp.seen[return_dir].td_end;
+			nircm->tcp_rule.return_max_end = ct->proto.tcp.seen[return_dir].td_maxend;
+#ifdef ECM_OPENWRT_SUPPORT
+			if (nf_ct_tcp_be_liberal || nf_ct_tcp_no_window_check
+#else
+			if (nf_ct_tcp_be_liberal
+#endif
+					|| (ct->proto.tcp.seen[flow_dir].flags & IP_CT_TCP_FLAG_BE_LIBERAL)
+					|| (ct->proto.tcp.seen[return_dir].flags & IP_CT_TCP_FLAG_BE_LIBERAL)) {
+				nircm->rule_flags |= SFE_RULE_CREATE_FLAG_NO_SEQ_CHECK;
+			} else {
+#ifdef CONFIG_XFRM
+				/*
+				 * TCP window check will fail if TCP is accelerated in one direction but not in another
+				 */
+				if (nircm->direction_rule.flow_accel != nircm->direction_rule.return_accel) {
+					spin_unlock_bh(&ct->lock);
+					DEBUG_WARN("Can't accelerate ipsec TCP flow in uni-direction because TCP window checking is on\n");
+					ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+					ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+					goto ported_accel_bad_rule;
+				}
+#endif
+			}
+			spin_unlock_bh(&ct->lock);
+		}
+
+		nircm->valid_flags |= SFE_RULE_CREATE_TCP_VALID;
+	}
+
+	/*
+	 * Sync our creation command from the assigned classifiers to get specific additional creation rules.
+	 * NOTE: These are called in ascending order of priority and so the last classifier (highest) shall
+	 * override any preceding classifiers.
+	 * This also gives the classifiers a chance to see that acceleration is being attempted.
+	 */
+	assignment_count = ecm_db_connection_classifier_assignments_get_and_ref(feci->ci, assignments);
+	for (aci_index = 0; aci_index < assignment_count; ++aci_index) {
+		struct ecm_classifier_instance *aci;
+		struct ecm_classifier_rule_create ecrc;
+		/*
+		 * NOTE: The current classifiers do not sync anything to the underlying accel engines.
+		 * In the future, if any of the classifiers wants to pass any parameter, these parameters
+		 * should be received via this object and copied to the accel engine's create object (nircm).
+		*/
+		aci = assignments[aci_index];
+		DEBUG_TRACE("%px: sync from: %px, type: %d\n", npci, aci, aci->type_get(aci));
+		aci->sync_from_v6(aci, &ecrc);
+	}
+	ecm_db_connection_assignments_release(assignment_count, assignments);
+
+	/*
+	 * Release the interface lists
+	 */
+	ecm_db_connection_interfaces_deref(from_ifaces, from_ifaces_first);
+	ecm_db_connection_interfaces_deref(to_ifaces, to_ifaces_first);
+
+	DEBUG_INFO("%px: Ported Accelerate connection %px\n"
+			"Protocol: %d\n"
+			"from_mtu: %u\n"
+			"to_mtu: %u\n"
+			"from_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"to_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"from_mac: %pM\n"
+			"to_mac: %pM\n"
+			"from_src_mac: %pM\n"
+			"to_src_mac: %pM\n"
+			"from_iface_num: %u\n"
+			"to_iface_num: %u\n"
+			"from_top_interface_num: %d\n"
+			"to_top_interface_num: %d\n"
+			"primary_ingress_vlan_tag: %x\n"
+			"primary_egress_vlan_tag: %x\n"
+			"secondary_ingress_vlan_tag: %x\n"
+			"secondary_egress_vlan_tag: %x\n"
+			"flags: rule=%x valid=%x src_mac_valid=%x\n"
+			"return_pppoe_session_id: %u\n"
+			"return_pppoe_remote_mac: %pM\n"
+			"flow_pppoe_session_id: %u\n"
+			"flow_pppoe_remote_mac: %pM\n"
+			"flow_qos_tag: %x (%u)\n"
+			"return_qos_tag: %x (%u)\n"
+			"flow_dscp: %x\n"
+			"return_dscp: %x\n"
+			"flow_mark:%x\n"
+			"return_mark:%x\n",
+			npci,
+			feci->ci,
+			nircm->tuple.protocol,
+			nircm->conn_rule.flow_mtu,
+			nircm->conn_rule.return_mtu,
+			ECM_IP_ADDR_TO_OCTAL(src_ip), ntohs(nircm->tuple.flow_ident),
+			ECM_IP_ADDR_TO_OCTAL(dest_ip), ntohs(nircm->tuple.return_ident),
+			nircm->conn_rule.flow_mac,
+			nircm->conn_rule.return_mac,
+			nircm->src_mac_rule.flow_src_mac,
+			nircm->src_mac_rule.return_src_mac,
+			nircm->conn_rule.flow_interface_num,
+			nircm->conn_rule.return_interface_num,
+			nircm->conn_rule.flow_top_interface_num,
+			nircm->conn_rule.return_top_interface_num,
+			nircm->vlan_primary_rule.ingress_vlan_tag,
+			nircm->vlan_primary_rule.egress_vlan_tag,
+			nircm->vlan_secondary_rule.ingress_vlan_tag,
+			nircm->vlan_secondary_rule.egress_vlan_tag,
+			nircm->rule_flags,
+			nircm->valid_flags,
+			nircm->src_mac_rule.mac_valid_flags,
+			nircm->pppoe_rule.return_pppoe_session_id,
+			nircm->pppoe_rule.return_pppoe_remote_mac,
+			nircm->pppoe_rule.flow_pppoe_session_id,
+			nircm->pppoe_rule.flow_pppoe_remote_mac,
+			nircm->qos_rule.flow_qos_tag, nircm->qos_rule.flow_qos_tag,
+			nircm->qos_rule.return_qos_tag, nircm->qos_rule.return_qos_tag,
+			nircm->dscp_rule.flow_dscp,
+			nircm->dscp_rule.return_dscp,
+			nircm->mark_rule.flow_mark,
+			nircm->mark_rule.return_mark);
+
+	if (protocol == IPPROTO_TCP) {
+		DEBUG_INFO("flow_window_scale: %u\n"
+			"flow_max_window: %u\n"
+			"flow_end: %u\n"
+			"flow_max_end: %u\n"
+			"return_window_scale: %u\n"
+			"return_max_window: %u\n"
+			"return_end: %u\n"
+			"return_max_end: %u\n",
+			nircm->tcp_rule.flow_window_scale,
+			nircm->tcp_rule.flow_max_window,
+			nircm->tcp_rule.flow_end,
+			nircm->tcp_rule.flow_max_end,
+			nircm->tcp_rule.return_window_scale,
+			nircm->tcp_rule.return_max_window,
+			nircm->tcp_rule.return_end,
+			nircm->tcp_rule.return_max_end);
+	}
+
+	/*
+	 * Now that the rule has been constructed we re-compare the generation occurrance counter.
+	 * If there has been a change then we abort because the rule may have been created using
+	 * unstable data - especially if another thread has begun regeneration of the connection state.
+	 * NOTE: This does not prevent a regen from being flagged immediately after this line of code either,
+	 * or while the acceleration rule is in flight to the nss.
+	 * This is only to check for consistency of rule state - not that the state is stale.
+	 * Remember that the connection is marked as "accel pending state" so if a regen is flagged immediately
+	 * after this check passes, the connection will be decelerated and refreshed very quickly.
+	 */
+	if (regen_occurrances != ecm_db_connection_regeneration_occurrances_get(feci->ci)) {
+		DEBUG_INFO("%px: connection:%px regen occurred - aborting accel rule.\n", feci, feci->ci);
+		ecm_sfe_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_DECEL);
+		return;
+	}
+
+	/*
+	 * Ref the connection before issuing an SFE rule
+	 * This ensures that when the SFE responds to the command - which may even be immediately -
+	 * the callback function can trust the correct ref was taken for its purpose.
+	 * NOTE: remember that this will also implicitly hold the feci.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Set fast xmit flags if connection can fast xmit
+	 */
+	ecm_sfe_ipv6_fast_xmit_set(nircm);
+
+	/*
+	 * Call the rule create function
+	 */
+	sfe_tx_status = sfe_ipv6_tx(ecm_sfe_ipv6_mgr, &nim);
+	if (sfe_tx_status == SFE_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * Release that ref!
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * TX failed
+	 */
+	spin_lock_bh(&feci->lock);
+	DEBUG_ASSERT(feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING, "%px: Accel mode unexpected: %d\n", npci, feci->accel_mode);
+	feci->stats.driver_fail_total++;
+	feci->stats.driver_fail++;
+	if (feci->stats.driver_fail >= feci->stats.driver_fail_limit) {
+		DEBUG_WARN("%px: Accel failed - driver fail limit\n", npci);
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DRIVER;
+	} else {
+		result_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	_ecm_sfe_ipv6_accel_pending_clear(feci, result_mode);
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+	spin_unlock_bh(&feci->lock);
+	return;
+
+ported_accel_bad_rule:
+	;
+
+	/*
+	 * Jump to here when rule data is bad and an offload command cannot be constructed
+	 */
+	DEBUG_WARN("%px: Accel failed - bad rule\n", npci);
+	ecm_sfe_ipv6_accel_pending_clear(feci, ECM_FRONT_END_ACCELERATION_MODE_FAIL_RULE);
+}
+
+/*
+ * ecm_sfe_ported_ipv6_connection_destroy_callback()
+ *	Callback for handling destroy ack/nack calls.
+ */
+static void ecm_sfe_ported_ipv6_connection_destroy_callback(void *app_data, struct sfe_ipv6_msg *nim)
+{
+	struct sfe_ipv6_rule_destroy_msg *nirdm = &nim->msg.rule_destroy;
+	uint32_t serial = (uint32_t)(ecm_ptr_t)app_data;
+	struct ecm_db_connection_instance *ci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_sfe_ported_ipv6_connection_instance *npci;
+	ip_addr_t flow_ip;
+	ip_addr_t return_ip;
+
+	/*
+	 * Is this a response to a destroy message?
+	 */
+	if (nim->cm.type != SFE_TX_DESTROY_RULE_MSG) {
+		DEBUG_ERROR("%px: ported destroy callback with improper type: %d\n", nim, nim->cm.type);
+		return;
+	}
+
+	/*
+	 * Look up ecm connection so that we can update the status.
+	 */
+	ci = ecm_db_connection_serial_find_and_ref(serial);
+	if (!ci) {
+		DEBUG_TRACE("%px: destroy callback, connection not found, serial: %u\n", nim, serial);
+		return;
+	}
+
+	/*
+	 * Release ref held for this ack/nack response.
+	 * NOTE: It's okay to do this here, ci won't go away, because the ci is held as
+	 * a result of the ecm_db_connection_serial_find_and_ref()
+	 */
+	ecm_db_connection_deref(ci);
+
+	/*
+	 * Get the front end instance
+	 */
+	feci = ecm_db_connection_front_end_get_and_ref(ci);
+	npci = (struct ecm_sfe_ported_ipv6_connection_instance *)feci;
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	ECM_SFE_IPV6_ADDR_TO_IP_ADDR(flow_ip, nirdm->tuple.flow_ip);
+	ECM_SFE_IPV6_ADDR_TO_IP_ADDR(return_ip, nirdm->tuple.return_ip);
+
+	/*
+	 * Record command duration
+	 */
+	ecm_sfe_ipv6_decel_done_time_update(feci);
+
+	/*
+	 * Dump some useful trace information.
+	 */
+	DEBUG_TRACE("%px: decelerate response for connection: %px\n", npci, feci->ci);
+	DEBUG_TRACE("%px: flow_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", npci, ECM_IP_ADDR_TO_OCTAL(flow_ip), nirdm->tuple.flow_ident);
+	DEBUG_TRACE("%px: return_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n", npci, ECM_IP_ADDR_TO_OCTAL(return_ip), nirdm->tuple.return_ident);
+	DEBUG_TRACE("%px: protocol: %d\n", npci, nirdm->tuple.protocol);
+
+	/*
+	 * Drop decel pending counter
+	 */
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	ecm_sfe_ipv6_pending_decel_count--;
+	DEBUG_ASSERT(ecm_sfe_ipv6_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If decel is not still pending then it's possible that the SFE ended acceleration by some other reason e.g. flush
+	 * In which case we cannot rely on the response we get here.
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING) {
+		spin_unlock_bh(&feci->lock);
+
+		/*
+		 * Release the connections.
+		 */
+		feci->deref(feci);
+		ecm_db_connection_deref(ci);
+		return;
+	}
+
+	DEBUG_TRACE("%px: response: %d\n", npci, nim->cm.response);
+	if (nim->cm.response != SFE_CMN_RESPONSE_ACK) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DECEL;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+
+	/*
+	 * If connection became defunct then set mode so that no further accel/decel attempts occur.
+	 */
+	if (feci->is_defunct) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_DEFUNCT_SHORT;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Ported acceleration ends
+	 */
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	ecm_sfe_ported_ipv6_accelerated_count[npci->ported_accelerated_count_index]--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_sfe_ported_ipv6_accelerated_count[npci->ported_accelerated_count_index] >= 0, "Bad udp accel counter\n");
+	ecm_sfe_ipv6_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_sfe_ipv6_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+	/*
+	 * Release the connections.
+	 */
+	feci->deref(feci);
+	ecm_db_connection_deref(ci);
+}
+
+/*
+ * ecm_sfe_ported_ipv6_connection_decelerate_msg_send()
+ *	Prepares and sends a decelerate message to acceleration engine.
+ */
+static bool ecm_sfe_ported_ipv6_connection_decelerate_msg_send(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_ported_ipv6_connection_instance *npci = (struct ecm_sfe_ported_ipv6_connection_instance *)feci;
+	struct sfe_ipv6_msg nim;
+	struct sfe_ipv6_rule_destroy_msg *nirdm;
+	ip_addr_t src_ip;
+	ip_addr_t dest_ip;
+	sfe_tx_status_t sfe_tx_status;
+	bool ret;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	/*
+	 * Increment the decel pending counter
+	 */
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	ecm_sfe_ipv6_pending_decel_count++;
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+	/*
+	 * Prepare deceleration message
+	 */
+	sfe_ipv6_msg_init(&nim, SFE_SPECIAL_INTERFACE_IPV6, SFE_TX_DESTROY_RULE_MSG,
+			sizeof(struct sfe_ipv6_rule_destroy_msg),
+			ecm_sfe_ported_ipv6_connection_destroy_callback,
+			(void *)(ecm_ptr_t)ecm_db_connection_serial_get(feci->ci));
+
+	nirdm = &nim.msg.rule_destroy;
+	nirdm->tuple.protocol = (int32_t)ecm_db_connection_protocol_get(feci->ci);
+
+	/*
+	 * Get addressing information
+	 */
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_FROM, src_ip);
+	ECM_IP_ADDR_TO_SFE_IPV6_ADDR(nirdm->tuple.flow_ip, src_ip);
+	ecm_db_connection_address_get(feci->ci, ECM_DB_OBJ_DIR_TO, dest_ip);
+	ECM_IP_ADDR_TO_SFE_IPV6_ADDR(nirdm->tuple.return_ip, dest_ip);
+	nirdm->tuple.flow_ident = htons(ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_FROM));
+	nirdm->tuple.return_ident = htons(ecm_db_connection_port_get(feci->ci, ECM_DB_OBJ_DIR_TO));
+
+	DEBUG_INFO("%px: Ported Connection %px decelerate\n"
+			"protocol: %d\n"
+			"src_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n"
+			"dest_ip: " ECM_IP_ADDR_OCTAL_FMT ":%d\n",
+			npci, feci->ci, nirdm->tuple.protocol,
+			ECM_IP_ADDR_TO_OCTAL(src_ip), nirdm->tuple.flow_ident,
+			ECM_IP_ADDR_TO_OCTAL(dest_ip), nirdm->tuple.return_ident);
+
+	/*
+	 * Take a ref to the feci->ci so that it will persist until we get a response from the SFE.
+	 * NOTE: This will implicitly hold the feci too.
+	 */
+	ecm_db_connection_ref(feci->ci);
+
+	/*
+	 * We are about to issue the command, record the time of transmission
+	 */
+	spin_lock_bh(&feci->lock);
+	feci->stats.cmd_time_begun = jiffies;
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Destroy the SFE connection cache entry.
+	 */
+	sfe_tx_status = sfe_ipv6_tx(ecm_sfe_ipv6_mgr, &nim);
+	if (sfe_tx_status == SFE_TX_SUCCESS) {
+		/*
+		 * Reset the driver_fail count - transmission was okay here.
+		 */
+		spin_lock_bh(&feci->lock);
+		feci->stats.driver_fail = 0;
+		spin_unlock_bh(&feci->lock);
+		return true;
+	}
+
+	/*
+	 * TX failed
+	 */
+	ret = ecm_front_end_destroy_failure_handle(feci);
+
+	/*
+	 * Release the ref take, SFE driver did not accept our command.
+	 */
+	ecm_db_connection_deref(feci->ci);
+
+	/*
+	 * Could not send the request, decrement the decel pending counter
+	 */
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	ecm_sfe_ipv6_pending_decel_count--;
+	DEBUG_ASSERT(ecm_sfe_ipv6_pending_decel_count >= 0, "Bad decel pending counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+	return ret;
+}
+
+/*
+ * ecm_sfe_ported_ipv6_connection_decelerate()
+ *     Decelerate a connection
+ */
+static bool ecm_sfe_ported_ipv6_connection_decelerate(struct ecm_front_end_connection_instance *feci)
+{
+	/*
+	 * Check if accel mode is OK for the deceleration.
+	 */
+	spin_lock_bh(&feci->lock);
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	return ecm_sfe_ported_ipv6_connection_decelerate_msg_send(feci);
+}
+
+/*
+ * ecm_sfe_ported_ipv6_connection_defunct_callback()
+ *	Callback to be called when a ported connection has become defunct.
+ */
+bool ecm_sfe_ported_ipv6_connection_defunct_callback(void *arg, int *accel_mode)
+{
+	bool ret;
+	struct ecm_front_end_connection_instance *feci = (struct ecm_front_end_connection_instance *)arg;
+	struct ecm_sfe_ported_ipv6_connection_instance *npci = (struct ecm_sfe_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	spin_lock_bh(&feci->lock);
+	/*
+	 * Check if the connection can be defuncted.
+	 */
+	if (!ecm_front_end_common_connection_defunct_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+
+	/*
+	 * If none of the cases matched above, this means the connection is in the
+	 * accel mode, so we force a deceleration.
+	 * NOTE: If the mode is accel pending then the decel will be actioned when that is completed.
+	 */
+	if (!ecm_front_end_common_connection_decelerate_accel_mode_check(feci)) {
+		*accel_mode = feci->accel_mode;
+		spin_unlock_bh(&feci->lock);
+		return false;
+	}
+	feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL_PENDING;
+	spin_unlock_bh(&feci->lock);
+
+	ret = ecm_sfe_ported_ipv6_connection_decelerate_msg_send(feci);
+
+	/*
+	 * Copy the accel_mode which is returned from the decelerate message function. This value
+	 * will be used in the caller to decide releasing the final reference of the connection.
+	 * But if this function reaches to here, the caller care about the ret. If ret is true,
+	 * the reference will be released regardless of the accel_mode. If ret is false, accel_mode
+	 * will be in the ACCEL state (for destroy re-try) and this state will not be used in the
+	 * caller's decision. It looks for ACCEL_FAIL states.
+	 */
+	spin_lock_bh(&feci->lock);
+	*accel_mode = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+
+	return ret;
+}
+
+/*
+ * ecm_sfe_ported_ipv6_connection_accel_state_get()
+ *	Get acceleration state
+ */
+static ecm_front_end_acceleration_mode_t ecm_sfe_ported_ipv6_connection_accel_state_get(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_ported_ipv6_connection_instance *npci = (struct ecm_sfe_ported_ipv6_connection_instance *)feci;
+	ecm_front_end_acceleration_mode_t state;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	spin_lock_bh(&feci->lock);
+	state = feci->accel_mode;
+	spin_unlock_bh(&feci->lock);
+	return state;
+}
+
+/*
+ * ecm_sfe_ported_ipv6_connection_action_seen()
+ *	Acceleration action / activity has been seen for this connection.
+ *
+ * NOTE: Call the action_seen() method when the SFE has demonstrated that it has offloaded some data for a connection.
+ */
+static void ecm_sfe_ported_ipv6_connection_action_seen(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_ported_ipv6_connection_instance *npci = (struct ecm_sfe_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	DEBUG_INFO("%px: Action seen\n", npci);
+	spin_lock_bh(&feci->lock);
+	feci->stats.no_action_seen = 0;
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_sfe_ported_ipv6_connection_accel_ceased()
+ *	SFE has indicated that acceleration has stopped.
+ *
+ * NOTE: This is called in response to an SFE self-initiated termination of acceleration.
+ * This must NOT be called because the ECM terminated the acceleration.
+ */
+static void ecm_sfe_ported_ipv6_connection_accel_ceased(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_ported_ipv6_connection_instance *npci = (struct ecm_sfe_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	DEBUG_INFO("%px: accel ceased\n", npci);
+
+	spin_lock_bh(&feci->lock);
+
+	/*
+	 * If we are in accel-pending state then the SFE has issued a flush out-of-order
+	 * with the ACK/NACK we are actually waiting for.
+	 * To work around this we record a "flush has already happened" and will action it when we finally get that ACK/NACK.
+	 * GGG TODO This should eventually be removed when the SFE honours messaging sequence.
+	 */
+	if (feci->accel_mode == ECM_FRONT_END_ACCELERATION_MODE_ACCEL_PENDING) {
+		feci->stats.flush_happened = true;
+		feci->stats.flush_happened_total++;
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If connection is no longer accelerated by the time we get here just ignore the command
+	 */
+	if (feci->accel_mode != ECM_FRONT_END_ACCELERATION_MODE_ACCEL) {
+		spin_unlock_bh(&feci->lock);
+		return;
+	}
+
+	/*
+	 * If the no_action_seen counter was not reset then acceleration ended without any offload action
+	 */
+	if (feci->stats.no_action_seen) {
+		feci->stats.no_action_seen_total++;
+	}
+
+	/*
+	 * If the no_action_seen indicates successive cessations of acceleration without any offload action occuring
+	 * then we fail out this connection
+	 */
+	if (feci->stats.no_action_seen >= feci->stats.no_action_seen_limit) {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_FAIL_NO_ACTION;
+	} else {
+		feci->accel_mode = ECM_FRONT_END_ACCELERATION_MODE_DECEL;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * Ported acceleration ends
+	 */
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	ecm_sfe_ported_ipv6_accelerated_count[npci->ported_accelerated_count_index]--;	/* Protocol specific counter */
+	DEBUG_ASSERT(ecm_sfe_ported_ipv6_accelerated_count[npci->ported_accelerated_count_index] >= 0, "Bad ported accel counter\n");
+	ecm_sfe_ipv6_accelerated_count--;		/* General running counter */
+	DEBUG_ASSERT(ecm_sfe_ipv6_accelerated_count >= 0, "Bad accel counter\n");
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+}
+
+/*
+ * ecm_sfe_ported_ipv6_connection_ref()
+ *	Ref a connection front end instance
+ */
+static void ecm_sfe_ported_ipv6_connection_ref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_ported_ipv6_connection_instance *npci = (struct ecm_sfe_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+	spin_lock_bh(&feci->lock);
+	feci->refs++;
+	DEBUG_TRACE("%px: npci ref %d\n", npci, feci->refs);
+	DEBUG_ASSERT(feci->refs > 0, "%px: ref wrap\n", npci);
+	spin_unlock_bh(&feci->lock);
+}
+
+/*
+ * ecm_sfe_ported_ipv6_connection_deref()
+ *	Deref a connection front end instance
+ */
+static int ecm_sfe_ported_ipv6_connection_deref(struct ecm_front_end_connection_instance *feci)
+{
+	struct ecm_sfe_ported_ipv6_connection_instance *npci = (struct ecm_sfe_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	spin_lock_bh(&feci->lock);
+	feci->refs--;
+	DEBUG_ASSERT(feci->refs >= 0, "%px: ref wrap\n", npci);
+
+	if (feci->refs > 0) {
+		int refs = feci->refs;
+		spin_unlock_bh(&feci->lock);
+		DEBUG_TRACE("%px: npci deref %d\n", npci, refs);
+		return refs;
+	}
+	spin_unlock_bh(&feci->lock);
+
+	/*
+	 * We can now destroy the instance
+	 */
+	DEBUG_TRACE("%px: npci final\n", npci);
+	DEBUG_CLEAR_MAGIC(npci);
+	kfree(npci);
+
+	return 0;
+}
+
+#ifdef ECM_STATE_OUTPUT_ENABLE
+/*
+ * ecm_sfe_ported_ipv6_connection_state_get()
+ *	Return the state of this ported front end instance
+ */
+static int ecm_sfe_ported_ipv6_connection_state_get(struct ecm_front_end_connection_instance *feci, struct ecm_state_file_instance *sfi)
+{
+	struct ecm_sfe_ported_ipv6_connection_instance *npci = (struct ecm_sfe_ported_ipv6_connection_instance *)feci;
+
+	DEBUG_CHECK_MAGIC(npci, ECM_SFE_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC, "%px: magic failed", npci);
+
+	return ecm_front_end_common_connection_state_get(feci, sfi, "sfe_v6.ported");
+}
+#endif
+
+/*
+ * ecm_sfe_ported_ipv6_connection_instance_alloc()
+ *	Create a front end instance specific for ported connection
+ */
+struct ecm_sfe_ported_ipv6_connection_instance *ecm_sfe_ported_ipv6_connection_instance_alloc(
+								bool can_accel,
+								int protocol,
+								struct ecm_db_connection_instance **nci)
+{
+	struct ecm_sfe_ported_ipv6_connection_instance *npci;
+	struct ecm_front_end_connection_instance *feci;
+	struct ecm_db_connection_instance *ci;
+
+	if (ecm_sfe_ipv6_is_conn_limit_reached()) {
+		DEBUG_TRACE("Reached connection limit\n");
+		return NULL;
+	}
+
+	/*
+	 * Now allocate the new connection
+	 */
+	*nci = ecm_db_connection_alloc();
+	if (!*nci) {
+		DEBUG_WARN("Failed to allocate connection\n");
+		return NULL;
+	}
+
+	ci = *nci;
+
+	npci = (struct ecm_sfe_ported_ipv6_connection_instance *)kzalloc(sizeof(struct ecm_sfe_ported_ipv6_connection_instance), GFP_ATOMIC | __GFP_NOWARN);
+	if (!npci) {
+		DEBUG_WARN("Ported Front end alloc failed\n");
+		ecm_db_connection_deref(ci);
+		return NULL;
+	}
+
+	/*
+	 * Refs is 1 for the creator of the connection
+	 */
+	feci = (struct ecm_front_end_connection_instance *)npci;
+	feci->refs = 1;
+	DEBUG_SET_MAGIC(npci, ECM_SFE_PORTED_IPV6_CONNECTION_INSTANCE_MAGIC);
+	spin_lock_init(&feci->lock);
+
+	feci->can_accel = can_accel;
+	feci->accel_mode = (can_accel) ? ECM_FRONT_END_ACCELERATION_MODE_DECEL : ECM_FRONT_END_ACCELERATION_MODE_FAIL_DENIED;
+	feci->accel_engine = ECM_FRONT_END_ENGINE_SFE;
+	spin_lock_bh(&ecm_sfe_ipv6_lock);
+	feci->stats.no_action_seen_limit = ecm_sfe_ipv6_no_action_limit_default;
+	feci->stats.driver_fail_limit = ecm_sfe_ipv6_driver_fail_limit_default;
+	feci->stats.ae_nack_limit = ecm_sfe_ipv6_nack_limit_default;
+	spin_unlock_bh(&ecm_sfe_ipv6_lock);
+
+	/*
+	 * Copy reference to connection - no need to ref ci as ci maintains a ref to this instance instead (this instance persists for as long as ci does)
+	 */
+	feci->ci = ci;
+
+	feci->ip_version = 6;
+
+	/*
+	 * Populate the methods and callbacks
+	 */
+	feci->ref = ecm_sfe_ported_ipv6_connection_ref;
+	feci->deref = ecm_sfe_ported_ipv6_connection_deref;
+	feci->accelerate = ecm_sfe_ported_ipv6_connection_accelerate;
+	feci->decelerate = ecm_sfe_ported_ipv6_connection_decelerate;
+	feci->accel_state_get = ecm_sfe_ported_ipv6_connection_accel_state_get;
+	feci->action_seen = ecm_sfe_ported_ipv6_connection_action_seen;
+	feci->accel_ceased = ecm_sfe_ported_ipv6_connection_accel_ceased;
+#ifdef ECM_STATE_OUTPUT_ENABLE
+	feci->state_get = ecm_sfe_ported_ipv6_connection_state_get;
+#endif
+	feci->ae_interface_number_by_dev_get = ecm_sfe_common_get_interface_number_by_dev;
+	feci->ae_interface_number_by_dev_type_get = ecm_sfe_common_get_interface_number_by_dev_type;
+	feci->ae_interface_type_get = ecm_sfe_common_get_interface_type;
+	feci->regenerate = ecm_sfe_common_connection_regenerate;
+
+	ecm_sfe_common_init_fe_info(&npci->fe_info);
+
+	feci->get_stats_bitmap = ecm_sfe_ported_ipv6_get_stats_bitmap;
+	feci->set_stats_bitmap = ecm_sfe_ported_ipv6_set_stats_bitmap;
+	feci->update_rule = ecm_sfe_common_update_rule;
+
+	if (protocol == IPPROTO_TCP) {
+		npci->ported_accelerated_count_index = ECM_SFE_PORTED_IPV6_PROTO_TCP;
+	} else if (protocol == IPPROTO_UDP) {
+		npci->ported_accelerated_count_index = ECM_SFE_PORTED_IPV6_PROTO_UDP;
+	} else {
+		DEBUG_WARN("%px: Wrong protocol: %d\n", npci, protocol);
+		DEBUG_CLEAR_MAGIC(npci);
+		ecm_db_connection_deref(ci);
+		kfree(npci);
+		return NULL;
+	}
+
+	return npci;
+}
+
+/*
+ * ecm_sfe_ported_ipv6_debugfs_init()
+ */
+bool ecm_sfe_ported_ipv6_debugfs_init(struct dentry *dentry)
+{
+	struct dentry *udp_dentry;
+
+	udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry,
+						&ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_UDP]);
+	if (!udp_dentry) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv6 udp_accelerated_count file in debugfs\n");
+		return false;
+	}
+
+	if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry,
+					&ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_TCP])) {
+		DEBUG_ERROR("Failed to create ecm sfe ipv6 tcp_accelerated_count file in debugfs\n");
+		debugfs_remove(udp_dentry);
+		return false;
+	}
+
+	return true;
+}
diff --git a/qca-nss-ecm/frontends/sfe/ecm_sfe_ported_ipv6.h b/qca-nss-ecm/frontends/sfe/ecm_sfe_ported_ipv6.h
new file mode 100644
index 0000000..d0a40c7
--- /dev/null
+++ b/qca-nss-ecm/frontends/sfe/ecm_sfe_ported_ipv6.h
@@ -0,0 +1,23 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2015, 2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+extern bool ecm_sfe_ported_ipv6_debugfs_init(struct dentry *dentry);
+
+extern struct ecm_sfe_ported_ipv6_connection_instance *ecm_sfe_ported_ipv6_connection_instance_alloc(
+								bool can_accel,
+								int protocol,
+								struct ecm_db_connection_instance **nci);
+extern bool ecm_sfe_ported_ipv6_connection_defunct_callback(void *arg, int *accel_mode);
diff --git a/qca-nss-sfe/.gitignore b/qca-nss-sfe/.gitignore
new file mode 100644
index 0000000..7c731cd
--- /dev/null
+++ b/qca-nss-sfe/.gitignore
@@ -0,0 +1,14 @@
+
+# Ignore general build intermediate files
+*.o
+*.cmd
+*.ko
+*.mod.*
+*.mod
+Module.symvers
+modules.order
+.tmp_versions
+built-in.a
+
+# don't ignore .gitignore itself
+!.gitignore
diff --git a/qca-nss-sfe/Makefile b/qca-nss-sfe/Makefile
new file mode 100644
index 0000000..74137e0
--- /dev/null
+++ b/qca-nss-sfe/Makefile
@@ -0,0 +1,42 @@
+#
+# Makefile for Shortcut FE.
+#
+
+KERNELVERSION := $(word 1, $(subst ., ,$(KERNELVERSION))).$(word 2, $(subst ., ,$(KERNELVERSION)))
+
+SFE_BASE_OBJS := sfe.o sfe_init.o
+SFE_IPV4_OBJS := sfe_ipv4.o sfe_ipv4_udp.o sfe_ipv4_tcp.o sfe_ipv4_icmp.o
+SFE_IPV6_OBJS := sfe_ipv6.o sfe_ipv6_udp.o sfe_ipv6_tcp.o sfe_ipv6_icmp.o sfe_ipv6_tunipip6.o
+SFE_PPPOE_OBJS := sfe_pppoe.o
+
+
+ifeq ($(findstring 4.4, $(KERNELVERSION)),)
+  SFE_IPV4_OBJS += sfe_ipv4_gre.o
+  SFE_IPV6_OBJS += sfe_ipv6_gre.o
+  ccflags-y += -DSFE_GRE_TUN_ENABLE
+endif
+
+
+obj-m += qca-nss-sfe.o
+
+#
+# Base files
+#
+qca-nss-sfe-objs := $(SFE_BASE_OBJS)
+
+#
+# IPv4 files
+#
+qca-nss-sfe-objs += $(SFE_IPV4_OBJS)
+qca-nss-sfe-objs += $(SFE_PPPOE_OBJS)
+
+ifdef SFE_SUPPORT_IPV6
+qca-nss-sfe-objs += $(SFE_IPV6_OBJS)
+ccflags-y += -DSFE_SUPPORT_IPV6
+endif
+
+ifdef SFE_PROCESS_LOCAL_OUT
+ccflags-y += -DSFE_PROCESS_LOCAL_OUT
+endif
+
+ccflags-y += -Werror -Wall -I$(obj)/exports/
diff --git a/qca-nss-sfe/README b/qca-nss-sfe/README
new file mode 100644
index 0000000..1bf1cc2
--- /dev/null
+++ b/qca-nss-sfe/README
@@ -0,0 +1,122 @@
+Shortcut Forwarding Engine
+--------------------------
+
+Welcome to "Shortcut" :-)
+
+Here's a quick FAQ:
+
+
+Q) What is Shortcut?
+
+A) Shortcut is an in-Linux-kernel IP packet forwarding engine.  It's designed
+to offer very high speed IP packet forwarding based on IP connection tracking.
+It's dramatically faster than the standard netfilter-based NAT forwarding path
+but is designed to synchronise state back to netfilter/conntrack so that it
+doesn't need to deal with all of the complexities of special cases.
+
+
+Q) What versions of IP does it support?
+
+A) The current version only supports IPv4 but will be extended to support IPv6 in
+the future.
+
+
+Q) What transport protocols does it support?
+
+A) TCP and UDP.  It also knows enough about ICMP to spot ICMP error messages
+related to TCP and UDP and handle things accordingly.
+
+
+Q) Is there a design spec for this software?
+
+A) Not at the moment.  I'll write one when I get more time.  The code is
+intended to be a good tutorial though - it's very heavily commented.  If you
+find yourself reading something and not understanding it then I take that to
+mean I've probably not done a sufficently good job of explaining what it's
+doing in the comments.  Let me know - I will try to fix it :-)
+
+
+Q) Why was it written?
+
+A) It was written as a demonstration of what can be done to provide high
+performance forwarding inside the kernel.  There were two initial motivations:
+
+1) To provide a platform to enable research into how QoS analysis systems can
+offload work and avoid huge Linux overheads.
+
+2) To provide a tool to investigate the behaviour of various processors, SoCs
+and software sets so that we can characterize and design new network processor
+SoCs.
+
+
+Q) How much faster is it than the Linux kernel forwarding path?
+
+A) At the time of pushing this to github it's been tested on a QCA AP135.
+This has a Scorpion (QCA Scopion, not the QMC one :-)) SoC, QCA9550.  The
+SoC's processor is a MIPS74K running at 720 MHz and with a DDR2 memory
+subsystem that offers a peak of 600 MT/s (16-bit transfers).
+
+Running IPv4 NAT forwarding of UDP between the board's 2 GMAC ports and
+using a SmartBits 200 as a traffic generator Linux is able to forward 70k PPS.
+Once the SFE code is invoked this will increase to 350k PPS!
+
+There's also a slightly hacky mode which causes SFE to bypass the Linux
+bridge layer, but this isn't really ready for use because it doesn't have
+sufficient MAC address checks or integration of statistics back to the
+Ethernet bridge, but that runs at 436k PPS.
+
+
+Q) Are there any diagnostics?
+
+A) Yes, this is a research tool after all!  There's a complex way to do this
+that's more general purpose and a simple one - here's the simple one:
+
+	mknod /dev/sfe c 253 0
+
+The file /dev/sfe is an XML-ish output and provides details of all the
+network connections currently being offloaded.  It also reports the numbers
+of packets that took various "exception" paths within the code.  In addition
+it provides a summary of the number of connections, attempts to accelerate
+connections, cancel accelerations, etc.  It also reports the numbers of
+packets that were forwarded and not forwarded by the engine and has some
+stats on the effectiveness of the hashing algorithm it uses.
+
+
+Q) How does the code interact with Linux?
+
+A) There are four minor patches required to make this software run with
+Linux.  These are currently against a 3.3.8 or 3.4.0 kernel:
+
+* (net/core/dev.c) adds a hook to allow packets to be extracted out.
+
+* (net/netfilter/nf_conntrack_proto_tcp.c) exposes a state variable inside
+  netfilter that's necessary to enable TCP sequence and ACK checking within
+  the offload path.  Note that this specific patch is against the QCA QSDK
+  patched version of 3.3.8 - there's a slightly braindead "performance"
+  patch in that kernel, courtesy of the OpenWrt community that makes the
+  Linux forwarding path slightly faster at the expense of losing
+  functionality :-(
+
+* (net/Kconfig) adds the shortcut-fe option.
+
+* (net/Makefile) adds the shortcut-fe build support.
+
+Once these are applied and the module is loaded then everything else
+is automatic :-)  The patches are in this git repo.
+
+
+Q) Are any of the pieces reused from other projects?
+
+A) Yes!  Some of the forwarding concepts are reused from the Ubicom Network
+Accelerator that morphed into part of the Akronite NSS.  This code has all
+been substantially changed though to accomodate Linux's needs.
+
+There are also some pieces that I borrowed from the QCA "FastNAT" software
+written by Xiaoping Fan <xfan@qca.qualcomm.com>.  Xiaoping's code was the
+first actual demonstration within QCA that this in-kernel concept could yield
+signficant performance gains.
+
+
+Enjoy!
+Dave Hudson <dhudson@qti.qualcomm.com>
+
diff --git a/qca-nss-sfe/build.sh b/qca-nss-sfe/build.sh
new file mode 100755
index 0000000..2378401
--- /dev/null
+++ b/qca-nss-sfe/build.sh
@@ -0,0 +1,99 @@
+#!/bin/bash
+
+set -e
+set -o errtrace
+trap 'echo Fatal error: script $0 aborting at line $LINENO, command \"$BASH_COMMAND\" returned $?; exit 1' ERR
+
+PRODUCT_LIST="sirocco"
+
+NUM_JOBS=$(grep -c processor /proc/cpuinfo)
+
+MODULE_NAME="qca-nss-sfe"
+###################################################
+# Setup build toollchain
+###################################################
+sdk_top_dir=$(readlink -e $(dirname $0)/..)
+TOP_DIR=$(readlink -e ${sdk_top_dir}/..)
+
+#export ARCH and build related envs.
+source ${TOP_DIR}/sdk/build_scripts/setup_env.sh
+
+kernel_path=$(readlink -e ${sdk_top_dir}/../kernel)
+soc_type=ipq50xx
+extra_cflags="-DSFE_SUPPORT_IPV6"
+build_flags="SFE_SUPPORT_IPV6=y"
+
+##################################################
+# Build Kernel Module
+##################################################
+function BuildKModule() {
+    # make kernel module
+    echo "Build ${MODULE_NAME}"
+    ${CROSS_MAKE} -C ${kernel_path} M=${sdk_top_dir}/${MODULE_NAME} ${build_flags} EXTRA_CFLAGS=${extra_cflags} SoC=${soc_type} V=1
+
+}
+
+##################################################
+# Build & Install
+##################################################
+function BuildAndInstall() {
+    local product=$1
+    local eureka_src_path=$(readlink -e $2)
+    if [ -z ${eureka_src_path} ]; then
+      echo "eureka_src_path doesn't exist"
+      exit 1
+    fi
+
+    # clean previous build
+    find . -name "*.o" -delete
+    find . -name "*.cmd" -delete
+    find . -name "*.ko" -delete
+    find . -name "*.mod.*" -delete
+    find . -name "*.mod" -delete
+    find . -name Module.symvers -delete
+
+    # build module
+    BuildKModule
+
+    # install module
+    echo "Install ${MODULE_NAME}.ko"
+    local module_target_dir="$(GetModulePath ${eureka_src_path} ${product})"
+    mkdir -p ${module_target_dir}
+    cp -f ${MODULE_NAME}.ko ${module_target_dir}/.
+}
+
+function Usage() {
+    cat << EOF
+Usage:
+    $0 <product> <eureka_src_path>
+    Valid products: ${PRODUCT_LIST}
+EOF
+}
+
+function IsProductValid() {
+  local product
+  local ret=1
+
+  for product in ${PRODUCT_LIST}; do
+    if [ "${product}" == "$1" ]; then
+      ret=0
+      break
+    fi
+  done
+
+  return ${ret}
+}
+
+#########################
+####### Main Entry ######
+#########################
+if (( $# < 2 )); then
+  Usage
+else
+  if IsProductValid $1; then
+    BuildAndInstall $1 $2
+  else
+    echo "$1 is a invalid product"
+    Usage
+  fi
+fi
diff --git a/qca-nss-sfe/exports/sfe_api.h b/qca-nss-sfe/exports/sfe_api.h
new file mode 100644
index 0000000..1bcfedc
--- /dev/null
+++ b/qca-nss-sfe/exports/sfe_api.h
@@ -0,0 +1,628 @@
+/*
+ * sfe_api.h
+ *	 SFE exported function headers for SFE engine
+ *
+ * Copyright (c) 2015,2016, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __SFE_API_H
+#define __SFE_API_H
+
+#define SFE_MAX_VLAN_DEPTH 2
+#define SFE_VLAN_ID_NOT_CONFIGURED 0xfff
+
+#define SFE_SPECIAL_INTERFACE_BASE 0x7f00
+#define SFE_SPECIAL_INTERFACE_IPV4 (SFE_SPECIAL_INTERFACE_BASE + 1)
+#define SFE_SPECIAL_INTERFACE_IPV6 (SFE_SPECIAL_INTERFACE_BASE + 2)
+#define SFE_SPECIAL_INTERFACE_IPSEC (SFE_SPECIAL_INTERFACE_BASE + 3)
+#define SFE_SPECIAL_INTERFACE_L2TP (SFE_SPECIAL_INTERFACE_BASE + 4)
+#define SFE_SPECIAL_INTERFACE_PPTP (SFE_SPECIAL_INTERFACE_BASE + 5)
+
+/**
+ * Rule creation & rule update flags.
+ */
+#define SFE_RULE_CREATE_FLAG_NO_SEQ_CHECK (1<<0) /**< Do not perform TCP sequence number checks */
+#define SFE_RULE_CREATE_FLAG_BRIDGE_FLOW  (1<<1) /**< This is a pure bridge forwarding flow */
+#define SFE_RULE_CREATE_FLAG_ROUTED       (1<<2) /**< Rule is for a routed connection */
+#define SFE_RULE_CREATE_FLAG_DSCP_MARKING (1<<3) /**< Rule has for a DSCP marking configured*/
+#define SFE_RULE_CREATE_FLAG_VLAN_MARKING (1<<4) /**< Rule has for a VLAN marking configured*/
+#define SFE_RULE_UPDATE_FLAG_CHANGE_MTU   (1<<5) /**< Update MTU of connection interfaces */
+#define SFE_RULE_CREATE_FLAG_ICMP_NO_CME_FLUSH (1<<6)/**< Rule for not flushing CME on ICMP pkt */
+#define SFE_RULE_CREATE_FLAG_L2_ENCAP     (1<<7) /**< consists of an encapsulating protocol that carries an IPv4 payload within it. */
+#define SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE (1<<8) /**< Use flow interface number instead of top interface. */
+#define SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE (1<<9) /**< Use return interface number instead of top interface. */
+#define SFE_RULE_CREATE_FLAG_FLOW_SRC_INTERFACE_CHECK  (1<<10)  /**< Check source interface on the flow direction . */
+#define SFE_RULE_CREATE_FLAG_RETURN_SRC_INTERFACE_CHECK  (1<<11)  /**< Check source interface on the return direction . */
+#define SFE_RULE_CREATE_FLAG_FLOW_TRANSMIT_FAST (1<<12) /**< original flow transmit fast. */
+#define SFE_RULE_CREATE_FLAG_RETURN_TRANSMIT_FAST (1<<13) /**< return flow transmit fast. */
+#define SFE_RULE_CREATE_FLAG_FLOW_SRC_INTERFACE_CHECK_NO_FLUSH  (1<<14)  /**< Check source interface on the flow direction but do not flush the connection. */
+#define SFE_RULE_CREATE_FLAG_RETURN_SRC_INTERFACE_CHECK_NO_FLUSH  (1<<15)  /**< Check source interface on the return direction but do not flush the connection. */
+
+/**
+ * Rule creation validity flags.
+ */
+#define SFE_RULE_CREATE_CONN_VALID         (1<<0) /**< IPv4 Connection is valid */
+#define SFE_RULE_CREATE_TCP_VALID          (1<<1) /**< TCP Protocol fields are valid */
+#define SFE_RULE_CREATE_PPPOE_DECAP_VALID  (1<<2) /**< PPPoE Decap fields are valid */
+#define SFE_RULE_CREATE_PPPOE_ENCAP_VALID  (1<<3) /**< PPPoE Encap fields are valid */
+#define SFE_RULE_CREATE_QOS_VALID          (1<<4) /**< QoS fields are valid */
+#define SFE_RULE_CREATE_VLAN_VALID         (1<<5) /**< VLAN fields are valid */
+#define SFE_RULE_CREATE_DSCP_MARKING_VALID (1<<6) /**< DSCP marking fields are valid */
+#define SFE_RULE_CREATE_VLAN_MARKING_VALID (1<<7) /**< VLAN marking fields are valid */
+#define SFE_RULE_CREATE_DIRECTION_VALID    (1<<8) /**< specify acceleration directions */
+#define SFE_RULE_CREATE_SRC_MAC_VALID	   (1<<9) /**< Source MAC valid */
+#define SFE_RULE_CREATE_MARK_VALID         (1<<10) /**< SKB mark fields are valid */
+
+/*
+ * Source MAC address valid flags (to be used with mac_valid_flags field of sfe_ipv4_src_mac_rule structure)
+ */
+#define SFE_SRC_MAC_FLOW_VALID 0x01
+		/**< MAC address for the flow interface is valid. */
+#define SFE_SRC_MAC_RETURN_VALID 0x02
+		/**< MAC address for the return interface is valid. */
+
+/*
+ * 32/64 bits pointer type
+ */
+#ifdef __LP64__
+typedef uint64_t sfe_ptr_t;
+#else
+typedef uint32_t sfe_ptr_t;
+#endif
+
+typedef enum sfe_rule_sync_reason {
+	SFE_RULE_SYNC_REASON_STATS,	/* Sync is to synchronize stats */
+	SFE_RULE_SYNC_REASON_FLUSH,	/* Sync is to flush a entry */
+	SFE_RULE_SYNC_REASON_EVICT,	/* Sync is to evict a entry */
+	SFE_RULE_SYNC_REASON_DESTROY	/* Sync is to destroy a entry(requested by connection manager) */
+
+} sfe_rule_sync_reason_t;
+
+/**
+ * Tx command status
+ */
+typedef enum {
+	SFE_TX_SUCCESS = 0,	/**< Success */
+	SFE_TX_FAILURE,		/**< Command failure other than descriptor not available */
+	SFE_TX_FAILURE_QUEUE,	/**< Command failure due to descriptor not available */
+	SFE_TX_FAILURE_NOT_READY,	/**< Command failure due to SFE state uninitialized */
+	SFE_TX_FAILURE_TOO_LARGE,	/**< Command is too large to fit in one message */
+	SFE_TX_FAILURE_TOO_SHORT,	/**< Command/Packet is shorter than expected size */
+	SFE_TX_FAILURE_NOT_SUPPORTED,	/**< Command/Packet not accepted for forwarding */
+	SFE_TX_FAILURE_BAD_PARAM,	/**< Command failure due to bad parameters */
+	SFE_TX_FAILURE_NOT_ENABLED,	/**< Command failure due to SFE feature is not enabled */
+} sfe_tx_status_t;
+
+/**
+ * Common response types.
+ */
+enum sfe_cmn_response {
+	SFE_CMN_RESPONSE_ACK,		/**< Message Acknowledge */
+	SFE_CMN_RESPONSE_EVERSION,	/**< Message Version Error */
+	SFE_CMN_RESPONSE_EINTERFACE,	/**< Message Interface Error */
+	SFE_CMN_RESPONSE_ELENGTH,	/**< Message Length Error */
+	SFE_CMN_RESPONSE_EMSG,		/**< Message Error */
+	SFE_CMM_RESPONSE_NOTIFY,	/**< Message Independant of Request */
+	SFE_CMN_RESPONSE_LAST
+};
+
+/**
+ * IPv4 bridge/route rule messages
+ */
+enum sfe_message_types {
+	SFE_TX_CREATE_RULE_MSG,		/**< IPv4/6 create rule message */
+	SFE_TX_DESTROY_RULE_MSG,	/**< IPv4/6 destroy rule message */
+	SFE_RX_CONN_STATS_SYNC_MSG,	/**< IPv4/6 connection stats sync message */
+	SFE_TUN6RD_ADD_UPDATE_PEER,	/**< Add/update peer for 6rd tunnel */
+	SFE_MAX_MSG_TYPES,		/**< IPv4/6 message max type number */
+};
+
+/**
+ * Connection mark structure.
+ */
+struct sfe_connection_mark {
+	int protocol;		/**< Protocol number. */
+	__be32 src_ip[4];	/**< Source IP address. */
+	__be32 dest_ip[4];	/**< Destination IP address. */
+	__be16 src_port;	/**< Source port number. */
+	__be16 dest_port;	/**< Destination port number. */
+	u32 mark;		/**< Mark value to be updated. */
+};
+
+/**
+ * Common message structure
+ */
+struct sfe_cmn_msg {
+	u16 version;		/**< Version id for main message format */
+	u16 interface;		/**< Primary Key for all messages */
+	enum sfe_cmn_response response;	/**< Primary response */
+	u32 type;			/**< Decetralized request #, to be used to match response # */
+	u32 error;			/**< Decentralized specific error message, response == EMSG */
+	sfe_ptr_t cb;			/**< Place for callback pointer */
+	sfe_ptr_t app_data;		/**< Place for app data */
+	u32 len;			/**< What is the length of the message excluding this header */
+};
+
+/**
+ * Common 5 tuple structure
+ */
+struct sfe_ipv4_5tuple {
+	__be32 flow_ip;			/**< Flow IP address */
+	__be32 return_ip;		/**< Return IP address */
+	__be16 flow_ident;		/**< Flow ident (e.g. TCP/UDP port) */
+	__be16 return_ident;		/**< Return ident (e.g. TCP/UDP port) */
+	u8 protocol;		/**< Protocol number */
+	u8 reserved[3];		/**< Padded for alignment */
+};
+
+/**
+ * IPv4 connection rule structure.
+ */
+struct sfe_ipv4_connection_rule {
+	u8 flow_mac[6];		/**< Flow MAC address */
+	u8 return_mac[6];		/**< Return MAC address */
+	s32 flow_interface_num;	/**< Flow interface number */
+	s32 return_interface_num;	/**< Return interface number */
+	s32 flow_top_interface_num;	/* Top flow interface number */
+	s32 return_top_interface_num;/* Top return interface number */
+	u32 flow_mtu;		/**< Flow interface`s MTU */
+	u32 return_mtu;		/**< Return interface`s MTU */
+	__be32 flow_ip_xlate;		/**< Translated flow IP address */
+	__be32 return_ip_xlate;		/**< Translated return IP address */
+	__be16 flow_ident_xlate;	/**< Translated flow ident (e.g. port) */
+	__be16 return_ident_xlate;	/**< Translated return ident (e.g. port) */
+};
+
+/**
+ * TCP connection rule structure
+ */
+struct sfe_protocol_tcp_rule {
+	u32 flow_max_window;	/**< Flow direction's largest seen window */
+	u32 return_max_window;	/**< Return direction's largest seen window */
+	u32 flow_end;		/**< Flow direction's largest seen sequence + segment length */
+	u32 return_end;		/**< Return direction's largest seen sequence + segment length */
+	u32 flow_max_end;		/**< Flow direction's largest seen ack + max(1, win) */
+	u32 return_max_end;	/**< Return direction's largest seen ack + max(1, win) */
+	u8 flow_window_scale;	/**< Flow direction's window scaling factor */
+	u8 return_window_scale;	/**< Return direction's window scaling factor */
+	u16 reserved;		/**< Padded for alignment */
+};
+
+/**
+ * PPPoE connection rules structure
+ */
+struct sfe_pppoe_rule {
+	u16 flow_pppoe_session_id;		/**< Flow direction`s PPPoE session ID. */
+	u8 flow_pppoe_remote_mac[ETH_ALEN];	/**< Flow direction`s PPPoE Server MAC address */
+	u16 return_pppoe_session_id;	/**< Return direction's PPPoE session ID. */
+	u8 return_pppoe_remote_mac[ETH_ALEN];	/**< Return direction's PPPoE Server MAC address */
+};
+
+/**
+ * sfe_src_mac_rule
+ *	Information for source MAC address rules.
+ */
+struct sfe_src_mac_rule {
+	uint32_t mac_valid_flags;	/**< MAC address validity flags. */
+	uint16_t flow_src_mac[3];	/**< Source MAC address for the flow direction. */
+	uint16_t return_src_mac[3];	/**< Source MAC address for the return direction. */
+};
+
+/**
+ * QoS connection rule structure
+ */
+struct sfe_qos_rule {
+	u32 flow_qos_tag;		/**< QoS tag associated with this rule for flow direction */
+	u32 return_qos_tag;	/**< QoS tag associated with this rule for return direction */
+};
+
+struct sfe_mark_rule {
+	u32 flow_mark;		/**< skb mark associated with this rule for flow direction */
+	u32 return_mark;	/**< skb mark associated with this rule for return direction */
+};
+
+/**
+ * DSCP connection rule structure
+ */
+struct sfe_dscp_rule {
+	u8 flow_dscp;		/**< Egress DSCP value for flow direction */
+	u8 return_dscp;		/**< Egress DSCP value for return direction */
+	u8 reserved[2];		/**< Padded for alignment */
+};
+
+/**
+ * VLAN connection rule structure
+ */
+struct sfe_vlan_rule {
+	u32 ingress_vlan_tag;	/**< VLAN Tag for the ingress packets */
+	u32 egress_vlan_tag;	/**< VLAN Tag for egress packets */
+};
+
+/**
+ * Acceleration direction rule structure
+ * 	Sometimes we just want to accelerate traffic in one direction but not in another.
+ */
+struct sfe_acceleration_direction_rule {
+	u8 flow_accel;		/**< Accelerate in flow direction */
+	u8 return_accel;		/**< Accelerate in return direction */
+	u8 reserved[2];		/**< Padded for alignment */
+};
+
+/**
+ * The IPv4 rule create sub-message structure.
+ */
+struct sfe_ipv4_rule_create_msg {
+	/* Request */
+	u16 valid_flags;				/**< Bit flags associated with the validity of parameters */
+	u16 rule_flags;				/**< Bit flags associated with the rule */
+
+	struct sfe_ipv4_5tuple tuple;			/**< Holds values of the 5 tuple */
+
+	struct sfe_ipv4_connection_rule conn_rule;	/**< Basic connection specific data */
+	struct sfe_protocol_tcp_rule tcp_rule;		/**< TCP related accleration parameters */
+	struct sfe_pppoe_rule pppoe_rule;		/**< PPPoE related accleration parameters */
+	struct sfe_qos_rule qos_rule;			/**< QoS related accleration parameters */
+	struct sfe_src_mac_rule src_mac_rule;		/**< Src Mac rule */
+	struct sfe_mark_rule mark_rule;			/**< skb mark related accleration parameters */
+	struct sfe_dscp_rule dscp_rule;			/**< DSCP related accleration parameters */
+	struct sfe_vlan_rule vlan_primary_rule;		/**< Primary VLAN related accleration parameters */
+	struct sfe_vlan_rule vlan_secondary_rule;	/**< Secondary VLAN related accleration parameters */
+#ifdef CONFIG_XFRM
+	struct sfe_acceleration_direction_rule direction_rule;/* Direction related accleration parameters*/
+#endif
+	/* Response */
+	u32 index;					/**< Slot ID for cache stats to host OS */
+};
+
+/**
+ * The IPv4 rule destroy sub-message structure.
+ */
+struct sfe_ipv4_rule_destroy_msg {
+	struct sfe_ipv4_5tuple tuple;	/**< Holds values of the 5 tuple */
+};
+
+/**
+ * The SFE IPv4 rule sync structure.
+ */
+struct sfe_ipv4_conn_sync {
+	u32 index;			/**< Slot ID for cache stats to host OS */
+	u8 protocol;		/**< Protocol number */
+	__be32 flow_ip;			/**< Flow IP address */
+	__be32 flow_ip_xlate;		/**< Translated flow IP address */
+	__be16 flow_ident;		/**< Flow ident (e.g. port) */
+	__be16 flow_ident_xlate;	/**< Translated flow ident (e.g. port) */
+	u32 flow_max_window;	/**< Flow direction's largest seen window */
+	u32 flow_end;		/**< Flow direction's largest seen sequence + segment length */
+	u32 flow_max_end;		/**< Flow direction's largest seen ack + max(1, win) */
+	u32 flow_rx_packet_count;	/**< Flow interface's RX packet count */
+	u32 flow_rx_byte_count;	/**< Flow interface's RX byte count */
+	u32 flow_tx_packet_count;	/**< Flow interface's TX packet count */
+	u32 flow_tx_byte_count;	/**< Flow interface's TX byte count */
+	u16 flow_pppoe_session_id; /**< Flow interface`s PPPoE session ID. */
+	u16 flow_pppoe_remote_mac[3];
+					/**< Flow interface's PPPoE remote server MAC address if there is any */
+	__be32 return_ip;		/**< Return IP address */
+	__be32 return_ip_xlate;		/**< Translated return IP address */
+	__be16 return_ident;		/**< Return ident (e.g. port) */
+	__be16 return_ident_xlate;	/**< Translated return ident (e.g. port) */
+	u32 return_max_window;	/**< Return direction's largest seen window */
+	u32 return_end;		/**< Return direction's largest seen sequence + segment length */
+	u32 return_max_end;	/**< Return direction's largest seen ack + max(1, win) */
+	u32 return_rx_packet_count;
+					/**< Return interface's RX packet count */
+	u32 return_rx_byte_count;	/**< Return interface's RX byte count */
+	u32 return_tx_packet_count;
+					/**< Return interface's TX packet count */
+	u32 return_tx_byte_count;	/**< Return interface's TX byte count */
+	u16 return_pppoe_session_id;
+					/**< Return interface`s PPPoE session ID. */
+	u16 return_pppoe_remote_mac[3];
+					/**< Return interface's PPPoE remote server MAC address if there is any */
+	u32 inc_ticks;		/**< Number of ticks since the last sync */
+	u32 reason;		/**< Reason for the sync */
+
+	u8 flags;			/**< Bit flags associated with the rule */
+	u32 qos_tag;		/**< QoS Tag */
+	u32 cause;			/**< Flush Cause */
+};
+
+/*
+ * Message structure to send/receive IPv4 bridge/route commands
+ */
+struct sfe_ipv4_msg {
+	struct sfe_cmn_msg cm;		/**< Message Header */
+	union {
+		struct sfe_ipv4_rule_create_msg rule_create;	/**< Message: rule create */
+		struct sfe_ipv4_rule_destroy_msg rule_destroy;	/**< Message: rule destroy */
+		struct sfe_ipv4_conn_sync conn_stats;	/**< Message: connection stats sync */
+	} msg;
+};
+
+/**
+ * Callback to be called when IPv4 message is received
+ */
+typedef void (*sfe_ipv4_msg_callback_t)(void *app_data, struct sfe_ipv4_msg *msg);
+
+/**
+ * IPv6 5-tuple structure.
+ */
+struct sfe_ipv6_5tuple {
+	__be32 flow_ip[4];		/**< Flow IP address */
+	__be32 return_ip[4];		/**< Return IP address */
+	__be16 flow_ident;		/**< Flow ident (e.g. TCP/UDP port) */
+	__be16 return_ident;		/**< Return ident (e.g. TCP/UDP port) */
+	u8  protocol;		/**< Protocol number */
+	u8  reserved[3];		/**< Padded for alignment */
+};
+
+/**
+ * IPv6 connection rule structure.
+ */
+struct sfe_ipv6_connection_rule {
+	u8 flow_mac[6];		/**< Flow MAC address */
+	u8 return_mac[6];		/**< Return MAC address */
+	s32 flow_interface_num;	/**< Flow interface number */
+	s32 return_interface_num;	/**< Return interface number */
+	s32 flow_top_interface_num;	/* Top flow interface number */
+	s32 return_top_interface_num;/* Top return interface number */
+	u32 flow_mtu;		/**< Flow interface's MTU */
+	u32 return_mtu;		/**< Return interface's MTU */
+};
+
+/**
+ * The IPv6 rule create sub-message structure.
+ */
+struct sfe_ipv6_rule_create_msg {
+	/*
+	 * Request
+	 */
+	u16 valid_flags;				/**< Bit flags associated with the validity of parameters */
+	u16 rule_flags;				/**< Bit flags associated with the rule */
+	struct sfe_ipv6_5tuple tuple;			/**< Holds values of the 5 tuple */
+	struct sfe_ipv6_connection_rule conn_rule;	/**< Basic connection specific data */
+	struct sfe_protocol_tcp_rule tcp_rule;		/**< Protocol related accleration parameters */
+	struct sfe_pppoe_rule pppoe_rule;		/**< PPPoE related accleration parameters */
+	struct sfe_qos_rule qos_rule;			/**< QoS related accleration parameters */
+	struct sfe_src_mac_rule src_mac_rule;		/**< Src Mac rule */
+	struct sfe_mark_rule mark_rule;			/**< skb mark related accleration parameters */
+	struct sfe_dscp_rule dscp_rule;			/**< DSCP related accleration parameters */
+	struct sfe_vlan_rule vlan_primary_rule;		/**< VLAN related accleration parameters */
+	struct sfe_vlan_rule vlan_secondary_rule;	/**< VLAN related accleration parameters */
+#ifdef CONFIG_XFRM
+	struct sfe_acceleration_direction_rule direction_rule;/* Direction related accleration parameters*/
+#endif
+	/*
+	 * Response
+	 */
+	u32 index;					/**< Slot ID for cache stats to host OS */
+};
+
+/**
+ * The IPv6 rule destroy sub-message structure.
+ */
+struct sfe_ipv6_rule_destroy_msg {
+	struct sfe_ipv6_5tuple tuple;	/**< Holds values of the 5 tuple */
+};
+
+/**
+ * The SFE IPv6 rule sync structure.
+ */
+struct sfe_ipv6_conn_sync {
+	u32 index;			/**< Slot ID for cache stats to host OS */
+	u8 protocol;		/**< Protocol number */
+	__be32 flow_ip[4];		/**< Flow IP address */
+	__be16 flow_ident;		/**< Flow ident (e.g. port) */
+	u32 flow_max_window;	/**< Flow direction's largest seen window */
+	u32 flow_end;		/**< Flow direction's largest seen sequence + segment length */
+	u32 flow_max_end;		/**< Flow direction's largest seen ack + max(1, win) */
+	u32 flow_rx_packet_count;	/**< Flow interface's RX packet count */
+	u32 flow_rx_byte_count;	/**< Flow interface's RX byte count */
+	u32 flow_tx_packet_count;	/**< Flow interface's TX packet count */
+	u32 flow_tx_byte_count;	/**< Flow interface's TX byte count */
+	u16 flow_pppoe_session_id; /**< Flow interface`s PPPoE session ID. */
+	u16 flow_pppoe_remote_mac[3];
+					/**< Flow interface's PPPoE remote server MAC address if there is any */
+	__be32 return_ip[4];		/**< Return IP address */
+	__be16 return_ident;		/**< Return ident (e.g. port) */
+	u32 return_max_window;	/**< Return direction's largest seen window */
+	u32 return_end;		/**< Return direction's largest seen sequence + segment length */
+	u32 return_max_end;	/**< Return direction's largest seen ack + max(1, win) */
+	u32 return_rx_packet_count;
+					/**< Return interface's RX packet count */
+	u32 return_rx_byte_count;	/**< Return interface's RX byte count */
+	u32 return_tx_packet_count;
+					/**< Return interface's TX packet count */
+	u32 return_tx_byte_count;	/**< Return interface's TX byte count */
+	u16 return_pppoe_session_id;
+					/**< Return interface`s PPPoE session ID. */
+	u16 return_pppoe_remote_mac[3];
+					/**< Return interface's PPPoE remote server MAC address if there is any */
+	u32 inc_ticks;		/**< Number of ticks since the last sync */
+	u32 reason;		/**< Reason for the sync */
+	u8 flags;			/**< Bit flags associated with the rule */
+	u32 qos_tag;		/**< QoS Tag */
+	u32 cause;			/**< Flush cause associated with the rule */
+};
+
+/**
+ * Message structure to send/receive IPv6 bridge/route commands
+ */
+struct sfe_ipv6_msg {
+	struct sfe_cmn_msg cm;					/**< Message Header */
+	union {
+		struct sfe_ipv6_rule_create_msg rule_create;	/**< Message: rule create */
+		struct sfe_ipv6_rule_destroy_msg rule_destroy;	/**< Message: rule destroy */
+		struct sfe_ipv6_conn_sync conn_stats;		/**< Message: stats sync */
+	} msg;
+};
+
+/**
+ * Callback to be called when IPv6 message is received
+ */
+typedef void (*sfe_ipv6_msg_callback_t)(void *app_data, struct sfe_ipv6_msg *msg);
+
+/**
+ * 6rd tunnel peer addr.
+ */
+struct sfe_tun6rd_set_peer_msg {
+	__be32 ipv6_address[4];	/* The peer's ipv6 addr*/
+	__be32 dest;		/* The peer's ipv4 addr*/
+};
+
+/**
+ * Message structure to send/receive 6rd tunnel messages
+ */
+struct sfe_tun6rd_msg {
+	struct sfe_cmn_msg cm;					/* Message Header */
+	union {
+		struct sfe_tun6rd_set_peer_msg peer;		/* Message: add/update peer */
+	} msg;
+};
+
+/*
+ * SFE context instance.
+ */
+struct sfe_ctx_instance {
+	int not_used;
+};
+
+/*
+ * sfe_ipv4_max_conn_count()
+ * 	Return the maximum number of IPv4 connections that the sfe acceleration engine supports
+ *
+ * @return int The number of connections that can be accelerated by the sfe
+ */
+int sfe_ipv4_max_conn_count(void);
+
+/*
+ * sfe_ipv4_tx()
+ * 	Transmit an IPv4 message to the sfe
+ *
+ * @param sfe_ctx SFE. context
+ * @param msg The IPv4 message
+ *
+ * @return sfe_tx_status_t The status of the Tx operation
+ */
+extern sfe_tx_status_t sfe_ipv4_tx(struct sfe_ctx_instance *sfe_ctx, struct sfe_ipv4_msg *msg);
+
+/*
+ * sfe_ipv4_notify_register()
+ * 	Register a notifier callback for IPv4 messages from SFE
+ *
+ * @param cb The callback pointer
+ * @param app_data The application context for this message
+ *
+ * @return struct sfe_ctx_instance * The SFE. context
+ */
+extern struct sfe_ctx_instance *sfe_ipv4_notify_register(sfe_ipv4_msg_callback_t cb, void *app_data);
+
+/*
+ * sfe_ipv4_notify_unregister()
+ * 	Un-Register a notifier callback for IPv4 messages from SFE
+ */
+extern void sfe_ipv4_notify_unregister(void);
+
+/*
+ * sfe_ipv4_msg_init()
+ * 	IPv4 message init
+ */
+extern void sfe_ipv4_msg_init(struct sfe_ipv4_msg *nim, u16 if_num, u32 type, u32 len,
+			sfe_ipv4_msg_callback_t cb, void *app_data);
+
+/*
+ * sfe_ipv6_max_conn_count()
+ * 	Return the maximum number of IPv6 connections that the sfe acceleration engine supports
+ *
+ * @return int The number of connections that can be accelerated by the sfe
+ */
+int sfe_ipv6_max_conn_count(void);
+
+/*
+ * sfe_ipv6_tx()
+ * 	Transmit an IPv6 message to the sfe
+ *
+ * @param sfe_ctx SFE. context
+ * @param msg The IPv6 message
+ *
+ * @return sfe_tx_status_t The status of the Tx operation
+ */
+extern sfe_tx_status_t sfe_ipv6_tx(struct sfe_ctx_instance *sfe_ctx, struct sfe_ipv6_msg *msg);
+
+/*
+ * sfe_ipv6_notify_register()
+ * 	Register a notifier callback for IPv6 messages from SFE.
+ *
+ * @param cb The callback pointer
+ * @param app_data The application context for this message
+ *
+ * @return struct sfe_ctx_instance * The SFE. context
+ */
+extern struct sfe_ctx_instance *sfe_ipv6_notify_register(sfe_ipv6_msg_callback_t cb, void *app_data);
+
+/*
+ * sfe_ipv6_notify_unregister()
+ * Un-Register a notifier callback for IPv6 messages from SFE.
+ */
+extern void sfe_ipv6_notify_unregister(void);
+
+/*
+ * sfe_ipv6_msg_init()
+ * 	IPv6 message init
+ */
+extern void sfe_ipv6_msg_init(struct sfe_ipv6_msg *nim, u16 if_num, u32 type, u32 len,
+			sfe_ipv6_msg_callback_t cb, void *app_data);
+
+/*
+ * sfe_tun6rd_tx()
+ * 	Transmit a tun6rd message to sfe engine
+ */
+sfe_tx_status_t sfe_tun6rd_tx(struct sfe_ctx_instance *sfe_ctx, struct sfe_tun6rd_msg *msg);
+
+/*
+ * sfe_tun6rd_msg_init()
+ *      Initialize sfe_tun6rd msg.
+ */
+void sfe_tun6rd_msg_init(struct sfe_tun6rd_msg *ncm, u16 if_num, u32 type,  u32 len,
+			 void *cb, void *app_data);
+
+/*
+ *
+ * sfe_is_l2_feature_enabled()
+ *	l2 feature flag is enabled or disabled
+ */
+bool sfe_is_l2_feature_enabled(void);
+
+/**
+ * Updates mark values of an IPv4 connection.
+ *
+ * @param	mark		The mark object.
+ *
+ * @return
+ * None.
+ */
+void sfe_ipv4_mark_rule_update(struct sfe_connection_mark *mark);
+
+/**
+ * Updates mark values of an IPv6 connection.
+ *
+ * @param	mark		The mark object.
+ *
+ * @return
+ * None.
+ */
+void sfe_ipv6_mark_rule_update(struct sfe_connection_mark *mark);
+
+#endif /* __SFE_API_H */
diff --git a/qca-nss-sfe/sfe.c b/qca-nss-sfe/sfe.c
new file mode 100644
index 0000000..0195d41
--- /dev/null
+++ b/qca-nss-sfe/sfe.c
@@ -0,0 +1,1662 @@
+/*
+ * sfe.c
+ *     API for shortcut forwarding engine.
+ *
+ * Copyright (c) 2015,2016, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/sysfs.h>
+#include <linux/skbuff.h>
+#include <net/addrconf.h>
+#include <linux/inetdevice.h>
+#include <net/pkt_sched.h>
+#include <net/vxlan.h>
+#include <net/gre.h>
+
+#include "sfe_debug.h"
+#include "sfe_api.h"
+#include "sfe.h"
+#include "sfe_pppoe.h"
+#include "sfe_vlan.h"
+
+extern int max_ipv4_conn;
+extern int max_ipv6_conn;
+
+#define SFE_MESSAGE_VERSION 0x1
+#define sfe_ipv6_addr_copy(src, dest) memcpy((void *)(dest), (void *)(src), 16)
+#define sfe_ipv4_stopped(CTX) (rcu_dereference((CTX)->ipv4_stats_sync_cb) == NULL)
+#define sfe_ipv6_stopped(CTX) (rcu_dereference((CTX)->ipv6_stats_sync_cb) == NULL)
+
+typedef enum sfe_exception {
+	SFE_EXCEPTION_IPV4_MSG_UNKNOW,
+	SFE_EXCEPTION_IPV6_MSG_UNKNOW,
+	SFE_EXCEPTION_CONNECTION_INVALID,
+	SFE_EXCEPTION_NOT_SUPPORT_BRIDGE,
+	SFE_EXCEPTION_TCP_INVALID,
+	SFE_EXCEPTION_PROTOCOL_NOT_SUPPORT,
+	SFE_EXCEPTION_SRC_DEV_NOT_L3,
+	SFE_EXCEPTION_DEST_DEV_NOT_L3,
+	SFE_EXCEPTION_CFG_ERR,
+	SFE_EXCEPTION_CREATE_FAILED,
+	SFE_EXCEPTION_ENQUEUE_FAILED,
+	SFE_EXCEPTION_NOT_SUPPORT_6RD,
+	SFE_EXCEPTION_NO_SYNC_CB,
+	SFE_EXCEPTION_MAX
+} sfe_exception_t;
+
+static char *sfe_exception_events_string[SFE_EXCEPTION_MAX] = {
+	"IPV4_MSG_UNKNOW",
+	"IPV6_MSG_UNKNOW",
+	"CONNECTION_INVALID",
+	"NOT_SUPPORT_BRIDGE",
+	"TCP_INVALID",
+	"PROTOCOL_NOT_SUPPORT",
+	"SRC_DEV_NOT_L3",
+	"DEST_DEV_NOT_L3",
+	"CONFIG_ERROR",
+	"CREATE_FAILED",
+	"ENQUEUE_FAILED",
+	"NOT_SUPPORT_6RD",
+	"NO_SYNC_CB"
+};
+
+/*
+ * Message type of queued response message
+ */
+typedef enum {
+	SFE_MSG_TYPE_IPV4,
+	SFE_MSG_TYPE_IPV6
+} sfe_msg_types_t;
+
+/*
+ * Queued response message,
+ * will be sent back to caller in workqueue
+ */
+struct sfe_response_msg {
+	struct list_head node;
+	sfe_msg_types_t type;
+	void *msg[0];
+};
+
+/*
+ * SFE context instance, private for SFE
+ */
+struct sfe_ctx_instance_internal {
+	struct sfe_ctx_instance base;	/* Exported SFE context, is public to user of SFE*/
+
+	/*
+	 * Control state.
+	 */
+	struct kobject *sys_sfe;	/* Sysfs linkage */
+
+	struct list_head msg_queue;	/* Response message queue*/
+	spinlock_t lock;		/* Lock to protect message queue */
+
+	struct work_struct work;	/* Work to send response message back to caller*/
+
+	sfe_ipv4_msg_callback_t __rcu ipv4_stats_sync_cb;	/* Callback to call to sync ipv4 statistics */
+	void *ipv4_stats_sync_data;	/* Argument for above callback: ipv4_stats_sync_cb */
+
+	sfe_ipv6_msg_callback_t __rcu ipv6_stats_sync_cb;	/* Callback to call to sync ipv6 statistics */
+	void *ipv6_stats_sync_data;	/* Argument for above callback: ipv6_stats_sync_cb */
+
+	u32 exceptions[SFE_EXCEPTION_MAX];		/* Statistics for exception */
+
+	int32_t l2_feature_support;		/* L2 feature support */
+
+	/*
+	 * SFE Bypass Mode.
+	 * When enabled, SFE's shortcut path will be bypassed.
+	 * 0: Disabled.
+	 * 1: Bypass all packets.
+	 * 2: Bypass only packets with fwmark matches bypass_mark.
+	 */
+	int bypass_mode;
+	u32 bypass_mark;
+};
+
+static struct sfe_ctx_instance_internal __sfe_ctx;
+
+/*
+ * Convert public SFE context to internal context
+ */
+#define SFE_CTX_TO_PRIVATE(base) (struct sfe_ctx_instance_internal *)(base)
+/*
+ * Convert internal SFE context to public context
+ */
+#define SFE_CTX_TO_PUBLIC(intrv) (struct sfe_ctx_instance *)(intrv)
+
+/*
+ * sfe_incr_exceptions()
+ *	Increase an exception counter.
+ *
+ * TODO:  Merge sfe_ctx stats to ipv4 and ipv6 percpu stats.
+ */
+static inline void sfe_incr_exceptions(sfe_exception_t except)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+
+	spin_lock_bh(&sfe_ctx->lock);
+	sfe_ctx->exceptions[except]++;
+	spin_unlock_bh(&sfe_ctx->lock);
+}
+
+/*
+ * sfe_dev_is_layer_3_interface()
+ * 	Check if a network device is ipv4 or ipv6 layer 3 interface
+ *
+ * @param dev network device to check
+ * @param check_v4 check ipv4 layer 3 interface(which have ipv4 address) or ipv6 layer 3 interface(which have ipv6 address)
+ */
+inline bool sfe_dev_is_layer_3_interface(struct net_device *dev, bool check_v4)
+{
+	struct in_device *in4_dev;
+	struct inet6_dev *in6_dev;
+
+	BUG_ON(!dev);
+
+	if (likely(check_v4)) {
+		/*
+		 * Does our input device support IPv4 processing?
+		 */
+		in4_dev = (struct in_device *)dev->ip_ptr;
+		if (unlikely(!in4_dev)) {
+			return false;
+		}
+
+		/*
+		 * Does it have an IPv4 address?  If it doesn't then it could be MAP-T interface,
+		 * else we can't do anything interesting here!
+		 */
+		if (likely(in4_dev->ifa_list || (dev->priv_flags_ext & IFF_EXT_MAPT))) {
+			return true;
+		}
+		return false;
+	}
+
+	/*
+	 * Does our input device support IPv6 processing?
+	 */
+	in6_dev = (struct inet6_dev *)dev->ip6_ptr;
+	if (unlikely(!in6_dev)) {
+		return false;
+	}
+
+	/*
+	 * Does it have an IPv6 address?  If it doesn't then it could be MAP-T interface,
+	 * else we can't do anything interesting here!
+	 */
+	if (likely(!list_empty(&in6_dev->addr_list) || (dev->priv_flags_ext & IFF_EXT_MAPT))) {
+		return true;
+	}
+
+        if (dev->rtnl_link_ops && !strcmp(dev->rtnl_link_ops->kind, "ip6tnl")) {
+                return true;
+        }
+
+	return false;
+}
+
+/*
+ * sfe_routed_dev_allow()
+ *	check whether routed acceleration allowed
+ */
+static bool sfe_routed_dev_allow(struct net_device *dev, bool is_routed,  bool check_v4)
+{
+	if (!is_routed) {
+		return true;
+	}
+
+	if (sfe_dev_is_layer_3_interface(dev, check_v4)) {
+		return true;
+	}
+
+	/*
+	 * in case of GRE / vxlan, these dev does not have IP address
+	 * so l3 interface check will fail. allow rule creation between gre / vxlan
+	 * and wan dev for routed flow.
+	 */
+	if (netif_is_vxlan(dev)) {
+		return true;
+	}
+
+#ifdef SFE_GRE_TUN_ENABLE
+	if (netif_is_gretap(dev) || netif_is_gre(dev)) {
+		return true;
+	}
+
+	if (netif_is_ip6gre(dev) || netif_is_ip6gretap(dev)) {
+		return true;
+	}
+#endif
+
+	return false;
+}
+
+/* sfe_dev_has_hw_csum()
+ *	check whether device supports hardware checksum offload
+ */
+bool sfe_dev_has_hw_csum(struct net_device *dev)
+{
+	if (netif_is_vxlan(dev)) {
+		return false;
+	}
+
+#ifdef SFE_GRE_TUN_ENABLE
+	if (netif_is_gre(dev) || netif_is_gretap(dev)) {
+		return false;
+	}
+
+	if (netif_is_ip6gre(dev) || netif_is_ip6gretap(dev)) {
+		return false;
+	}
+#endif
+	/*
+	 * Tunnel MAP-E/DS-LITE and Tun6rd share the same Routing netlink operator
+	 * whose kind is "ip6tnl". The HW csum for these tunnel devices should be disabled.
+	*/
+	if (dev->rtnl_link_ops && !strcmp(dev->rtnl_link_ops->kind, "ip6tnl")) {
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * sfe_clean_response_msg_by_type()
+ * 	clean response message in queue when ECM exit
+ *
+ * @param sfe_ctx SFE context
+ * @param msg_type message type, ipv4 or ipv6
+ */
+static void sfe_clean_response_msg_by_type(struct sfe_ctx_instance_internal *sfe_ctx, sfe_msg_types_t msg_type)
+{
+	struct sfe_response_msg *response, *tmp;
+
+	if (!sfe_ctx) {
+		return;
+	}
+
+	spin_lock_bh(&sfe_ctx->lock);
+	list_for_each_entry_safe(response, tmp, &sfe_ctx->msg_queue, node) {
+		if (response->type == msg_type) {
+			list_del(&response->node);
+			/*
+			 * Free response message
+			 */
+			kfree(response);
+		}
+	}
+	spin_unlock_bh(&sfe_ctx->lock);
+
+}
+
+/*
+ * sfe_process_response_msg()
+ * 	Send all pending response message to ECM by calling callback function included in message
+ *
+ * @param work work structure
+ */
+static void sfe_process_response_msg(struct work_struct *work)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = container_of(work, struct sfe_ctx_instance_internal, work);
+	struct sfe_response_msg *response;
+
+	spin_lock_bh(&sfe_ctx->lock);
+	while ((response = list_first_entry_or_null(&sfe_ctx->msg_queue, struct sfe_response_msg, node))) {
+		list_del(&response->node);
+		spin_unlock_bh(&sfe_ctx->lock);
+		rcu_read_lock();
+
+		/*
+		 * Send response message back to caller
+		 */
+		if ((response->type == SFE_MSG_TYPE_IPV4) && !sfe_ipv4_stopped(sfe_ctx)) {
+			struct sfe_ipv4_msg *msg = (struct sfe_ipv4_msg *)response->msg;
+			sfe_ipv4_msg_callback_t callback = (sfe_ipv4_msg_callback_t)msg->cm.cb;
+			if (callback) {
+				callback((void *)msg->cm.app_data, msg);
+			}
+		} else if ((response->type == SFE_MSG_TYPE_IPV6) && !sfe_ipv6_stopped(sfe_ctx)) {
+			struct sfe_ipv6_msg *msg = (struct sfe_ipv6_msg *)response->msg;
+			sfe_ipv6_msg_callback_t callback = (sfe_ipv6_msg_callback_t)msg->cm.cb;
+			if (callback) {
+				callback((void *)msg->cm.app_data, msg);
+			}
+		}
+
+		rcu_read_unlock();
+		/*
+		 * Free response message
+		 */
+		kfree(response);
+		spin_lock_bh(&sfe_ctx->lock);
+	}
+	spin_unlock_bh(&sfe_ctx->lock);
+}
+
+/*
+ * sfe_alloc_response_msg()
+ * 	Alloc and construct new response message
+ *
+ * @param type message type
+ * @param msg used to construct response message if not NULL
+ *
+ * @return !NULL, success; NULL, failed
+ */
+static struct sfe_response_msg *
+sfe_alloc_response_msg(sfe_msg_types_t type, void *msg)
+{
+	struct sfe_response_msg *response;
+	int size;
+
+	switch (type) {
+	case SFE_MSG_TYPE_IPV4:
+		size = sizeof(struct sfe_ipv4_msg);
+		break;
+	case SFE_MSG_TYPE_IPV6:
+		size = sizeof(struct sfe_ipv6_msg);
+		break;
+	default:
+		DEBUG_ERROR("message type %d not supported\n", type);
+		return NULL;
+	}
+
+	response = (struct sfe_response_msg *)kzalloc(sizeof(struct sfe_response_msg) + size, GFP_ATOMIC);
+	if (!response) {
+		DEBUG_ERROR("allocate memory failed\n");
+		return NULL;
+	}
+
+	response->type = type;
+
+	if (msg) {
+		memcpy(response->msg, msg, size);
+	}
+
+	return response;
+}
+
+/*
+ * sfe_fast_xmit_check()
+ *	Check the fast transmit feasibility.
+ *
+ * This check the per direction's  attribute that could not go fast
+ * transmit
+ * xfrm packets, come from a local socket or need sk validation on the skb
+ */
+bool sfe_fast_xmit_check(struct sk_buff *skb, netdev_features_t features)
+{
+
+#ifdef CONFIG_SOCK_VALIDATE_XMIT
+	if (skb->sk && sk_fullsock(skb->sk) && skb->sk->sk_validate_xmit_skb) {
+		DEBUG_INFO("%px:need sk validation\n", skb);
+		return false;
+#ifdef CONFIG_TLS_DEVICE
+	} else if (skb->decrypted) {
+		DEBUG_INFO("%px:SK or decrypted\n", skb);
+		return false;
+#endif
+	}
+#endif
+	if (skb_vlan_tag_present(skb)) {
+		DEBUG_INFO("%px:Vlan is present\n", skb);
+		return false;
+	}
+
+	if (netif_needs_gso(skb, features)) {
+		DEBUG_INFO("%px:Need to be gso\n", skb);
+		return false;
+	}
+
+	if (skb_sec_path(skb)) {
+		DEBUG_INFO("%px:XFRM is present\n", skb);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * sfe_enqueue_msg()
+ * 	Queue response message
+ *
+ * @param sfe_ctx SFE context
+ * @param response response message to be queue
+ */
+static inline void sfe_enqueue_msg(struct sfe_ctx_instance_internal *sfe_ctx, struct sfe_response_msg *response)
+{
+	spin_lock_bh(&sfe_ctx->lock);
+	list_add_tail(&response->node, &sfe_ctx->msg_queue);
+	spin_unlock_bh(&sfe_ctx->lock);
+
+	schedule_work(&sfe_ctx->work);
+}
+
+/*
+ * sfe_cmn_msg_init()
+ *	Initialize the common message structure.
+ *
+ * @param ncm message to init
+ * @param if_num interface number related with this message
+ * @param type message type
+ * @param cb callback function to process repsonse of this message
+ * @param app_data argument for above callback function
+ */
+static void sfe_cmn_msg_init(struct sfe_cmn_msg *ncm, u16 if_num, u32 type,  u32 len, void *cb, void *app_data)
+{
+	ncm->interface = if_num;
+	ncm->version = SFE_MESSAGE_VERSION;
+	ncm->type = type;
+	ncm->len = len;
+	ncm->cb = (sfe_ptr_t)cb;
+	ncm->app_data = (sfe_ptr_t)app_data;
+}
+
+/*
+ * sfe_ipv4_stats_sync_callback()
+ *	Synchronize a connection's state.
+ *
+ * @param sis SFE statistics from SFE core engine
+ */
+static void sfe_ipv4_stats_sync_callback(struct sfe_connection_sync *sis)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+	struct sfe_ipv4_msg msg;
+	struct sfe_ipv4_conn_sync *sync_msg;
+	sfe_ipv4_msg_callback_t sync_cb;
+
+	rcu_read_lock();
+	sync_cb = rcu_dereference(sfe_ctx->ipv4_stats_sync_cb);
+	if (!sync_cb) {
+		rcu_read_unlock();
+		sfe_incr_exceptions(SFE_EXCEPTION_NO_SYNC_CB);
+		return;
+	}
+
+	sync_msg = &msg.msg.conn_stats;
+
+	memset(&msg, 0, sizeof(msg));
+	sfe_cmn_msg_init(&msg.cm, 0, SFE_RX_CONN_STATS_SYNC_MSG,
+			sizeof(struct sfe_ipv4_conn_sync), NULL, NULL);
+
+	/*
+	 * Fill connection specific information
+	 */
+	sync_msg->protocol = (u8)sis->protocol;
+	sync_msg->flow_ip = sis->src_ip.ip;
+	sync_msg->flow_ip_xlate = sis->src_ip_xlate.ip;
+	sync_msg->flow_ident = sis->src_port;
+	sync_msg->flow_ident_xlate = sis->src_port_xlate;
+
+	sync_msg->return_ip = sis->dest_ip.ip;
+	sync_msg->return_ip_xlate = sis->dest_ip_xlate.ip;
+	sync_msg->return_ident = sis->dest_port;
+	sync_msg->return_ident_xlate = sis->dest_port_xlate;
+
+	/*
+	 * Fill TCP protocol specific information
+	 */
+	if (sis->protocol == IPPROTO_TCP) {
+		sync_msg->flow_max_window = sis->src_td_max_window;
+		sync_msg->flow_end = sis->src_td_end;
+		sync_msg->flow_max_end = sis->src_td_max_end;
+
+		sync_msg->return_max_window = sis->dest_td_max_window;
+		sync_msg->return_end = sis->dest_td_end;
+		sync_msg->return_max_end = sis->dest_td_max_end;
+	}
+
+	/*
+	 * Fill statistics information
+	 */
+	sync_msg->flow_rx_packet_count = sis->src_new_packet_count;
+	sync_msg->flow_rx_byte_count = sis->src_new_byte_count;
+	sync_msg->flow_tx_packet_count = sis->dest_new_packet_count;
+	sync_msg->flow_tx_byte_count = sis->dest_new_byte_count;
+
+	sync_msg->return_rx_packet_count = sis->dest_new_packet_count;
+	sync_msg->return_rx_byte_count = sis->dest_new_byte_count;
+	sync_msg->return_tx_packet_count = sis->src_new_packet_count;
+	sync_msg->return_tx_byte_count = sis->src_new_byte_count;
+
+	/*
+	 * Fill expiration time to extend, in unit of msec
+	 */
+	sync_msg->inc_ticks = (((u32)sis->delta_jiffies) * MSEC_PER_SEC)/HZ;
+
+	/*
+	 * Fill other information
+	 */
+	switch (sis->reason) {
+	case SFE_SYNC_REASON_DESTROY:
+		sync_msg->reason = SFE_RULE_SYNC_REASON_DESTROY;
+		break;
+	case SFE_SYNC_REASON_FLUSH:
+		sync_msg->reason = SFE_RULE_SYNC_REASON_FLUSH;
+		break;
+	default:
+		sync_msg->reason = SFE_RULE_SYNC_REASON_STATS;
+		break;
+	}
+
+	/*
+	 * SFE sync calling is excuted in a timer, so we can redirect it to ECM directly.
+	 */
+	sync_cb(sfe_ctx->ipv4_stats_sync_data, &msg);
+	rcu_read_unlock();
+}
+
+/*
+ * sfe_recv_parse_l2()
+ *	Parse L2 headers
+ *
+ * Returns true if the packet is parsed and false otherwise.
+ */
+static bool sfe_recv_parse_l2(struct net_device *dev, struct sk_buff *skb, struct sfe_l2_info *l2_info)
+{
+	/*
+	 * l2_hdr_offset will not change as we parse more L2.5 headers
+	 * TODO: Move from storing offsets to storing pointers
+	 */
+	sfe_l2_hdr_offset_set(l2_info, ((skb->data - ETH_HLEN) - skb->head));
+
+	/*
+	 * VLAN parsing
+	 */
+	if (unlikely(!sfe_vlan_check_and_parse_tag(skb, l2_info))) {
+		return false;
+	}
+
+	/*
+	 * PPPoE parsing
+	 */
+	if (htons(ETH_P_PPP_SES) == skb->protocol) {
+		/*
+		 * Parse only PPPoE session packets
+		 * skb->data is pointing to PPPoE hdr
+		 */
+		if (!sfe_pppoe_parse_hdr(skb, l2_info)) {
+
+			/*
+			 * For exception from PPPoE return from here without modifying the skb->data
+			 * This includes non-IPv4/v6 cases also
+			 */
+			return false;
+		}
+
+		/*
+		 * Pull by L2 header size
+		 */
+		__skb_pull(skb, sfe_l2_hdr_size_get(l2_info));
+	}
+	return true;
+}
+
+/*
+ * sfe_recv_undo_parse_l2()
+ */
+static void sfe_recv_undo_parse_l2(struct net_device *dev, struct sk_buff *skb, struct sfe_l2_info *l2_info)
+{
+	/*
+	 * PPPoE undo
+	 */
+	__skb_push(skb, sfe_l2_hdr_size_get(l2_info));
+
+	/*
+	 * VLAN undo
+	 */
+	sfe_vlan_undo_parse(skb, l2_info);
+}
+
+/*
+ * sfe_create_ipv4_rule_msg()
+ * 	Convert create message format from ecm to sfe
+ *
+ * @param sfe_ctx SFE context
+ * @param msg The IPv4 message
+ *
+ * @return sfe_tx_status_t The status of the Tx operation
+ */
+sfe_tx_status_t sfe_create_ipv4_rule_msg(struct sfe_ctx_instance_internal *sfe_ctx, struct sfe_ipv4_msg *msg)
+{
+	struct net_device *src_dev = NULL;
+	struct net_device *dest_dev = NULL;
+	struct sfe_response_msg *response;
+	enum sfe_cmn_response ret = SFE_TX_SUCCESS;
+	bool is_routed = true;
+	bool cfg_err;
+
+	response = sfe_alloc_response_msg(SFE_MSG_TYPE_IPV4, msg);
+	if (!response) {
+		sfe_incr_exceptions(SFE_EXCEPTION_ENQUEUE_FAILED);
+		return SFE_TX_FAILURE_QUEUE;
+	}
+
+	if (!(msg->msg.rule_create.valid_flags & SFE_RULE_CREATE_CONN_VALID)) {
+		ret = SFE_CMN_RESPONSE_EMSG;
+		sfe_incr_exceptions(SFE_EXCEPTION_CONNECTION_INVALID);
+		goto failed_ret;
+	}
+
+	switch (msg->msg.rule_create.tuple.protocol) {
+	case IPPROTO_TCP:
+		if (!(msg->msg.rule_create.valid_flags & SFE_RULE_CREATE_TCP_VALID)) {
+			ret = SFE_CMN_RESPONSE_EMSG;
+			sfe_incr_exceptions(SFE_EXCEPTION_TCP_INVALID);
+			goto failed_ret;
+		}
+
+	case IPPROTO_UDP:
+		break;
+
+	case IPPROTO_GRE:
+		break;
+
+	default:
+		ret = SFE_CMN_RESPONSE_EMSG;
+		sfe_incr_exceptions(SFE_EXCEPTION_PROTOCOL_NOT_SUPPORT);
+		goto failed_ret;
+	}
+
+	/*
+	 * Bridge flows are accelerated if L2 feature is enabled.
+	 */
+	if (msg->msg.rule_create.rule_flags & SFE_RULE_CREATE_FLAG_BRIDGE_FLOW) {
+		if (!sfe_is_l2_feature_enabled()) {
+			ret = SFE_CMN_RESPONSE_EINTERFACE;
+			sfe_incr_exceptions(SFE_EXCEPTION_NOT_SUPPORT_BRIDGE);
+			goto failed_ret;
+		}
+
+		is_routed = false;
+	}
+
+	/*
+	 * Does our input device support IP processing?
+	 */
+	src_dev = dev_get_by_index(&init_net, msg->msg.rule_create.conn_rule.flow_top_interface_num);
+	if (!src_dev || !sfe_routed_dev_allow(src_dev, is_routed, true)) {
+		ret = SFE_CMN_RESPONSE_EINTERFACE;
+		sfe_incr_exceptions(SFE_EXCEPTION_SRC_DEV_NOT_L3);
+		goto failed_ret;
+	}
+
+	/*
+	 * Check whether L2 feature is disabled and rule flag is configured to use bottom interface
+	 */
+	cfg_err = (msg->msg.rule_create.rule_flags & SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE) && !sfe_is_l2_feature_enabled();
+	if (cfg_err) {
+		ret = SFE_CMN_RESPONSE_EMSG;
+		sfe_incr_exceptions(SFE_EXCEPTION_CFG_ERR);
+		goto failed_ret;
+	}
+
+	/*
+	 * Does our output device support IP processing?
+	 */
+	dest_dev = dev_get_by_index(&init_net, msg->msg.rule_create.conn_rule.return_top_interface_num);
+	if (!dest_dev || !sfe_routed_dev_allow(dest_dev, is_routed, true)) {
+		ret = SFE_CMN_RESPONSE_EINTERFACE;
+		sfe_incr_exceptions(SFE_EXCEPTION_DEST_DEV_NOT_L3);
+		goto failed_ret;
+	}
+
+	/*
+	 * Check whether L2 feature is disabled and rule flag is configured to use bottom interface
+	 */
+	cfg_err = (msg->msg.rule_create.rule_flags & SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE) && !sfe_is_l2_feature_enabled();
+	if (cfg_err) {
+		ret = SFE_CMN_RESPONSE_EMSG;
+		sfe_incr_exceptions(SFE_EXCEPTION_CFG_ERR);
+		goto failed_ret;
+	}
+
+	if (!sfe_ipv4_create_rule(&msg->msg.rule_create)) {
+		/* success */
+		ret = SFE_CMN_RESPONSE_ACK;
+	} else {
+		/* Failed */
+		ret = SFE_CMN_RESPONSE_EMSG;
+		sfe_incr_exceptions(SFE_EXCEPTION_CREATE_FAILED);
+	}
+
+	/*
+	 * Fall through
+	 */
+failed_ret:
+	if (src_dev) {
+		dev_put(src_dev);
+	}
+
+	if (dest_dev) {
+		dev_put(dest_dev);
+	}
+
+	/*
+	 * Try to queue response message
+	 */
+	((struct sfe_ipv4_msg *)response->msg)->cm.response = msg->cm.response = ret;
+	sfe_enqueue_msg(sfe_ctx, response);
+
+	return SFE_TX_SUCCESS;
+}
+
+/*
+ * sfe_destroy_ipv4_rule_msg()
+ * 	Convert destroy message format from ecm to sfe
+ *
+ * @param sfe_ctx SFE context
+ * @param msg The IPv4 message
+ *
+ * @return sfe_tx_status_t The status of the Tx operation
+ */
+sfe_tx_status_t sfe_destroy_ipv4_rule_msg(struct sfe_ctx_instance_internal *sfe_ctx, struct sfe_ipv4_msg *msg)
+{
+	struct sfe_response_msg *response;
+
+	response = sfe_alloc_response_msg(SFE_MSG_TYPE_IPV4, msg);
+	if (!response) {
+		sfe_incr_exceptions(SFE_EXCEPTION_ENQUEUE_FAILED);
+		return SFE_TX_FAILURE_QUEUE;
+	}
+
+	sfe_ipv4_destroy_rule(&msg->msg.rule_destroy);
+
+	/*
+	 * Try to queue response message
+	 */
+	((struct sfe_ipv4_msg *)response->msg)->cm.response = msg->cm.response = SFE_CMN_RESPONSE_ACK;
+	sfe_enqueue_msg(sfe_ctx, response);
+
+	return SFE_TX_SUCCESS;
+}
+
+/*
+ * sfe_ipv4_tx()
+ * 	Transmit an IPv4 message to the sfe
+ *
+ * @param sfe_ctx SFE context
+ * @param msg The IPv4 message
+ *
+ * @return sfe_tx_status_t The status of the Tx operation
+ */
+sfe_tx_status_t sfe_ipv4_tx(struct sfe_ctx_instance *sfe_ctx, struct sfe_ipv4_msg *msg)
+{
+	switch (msg->cm.type) {
+	case SFE_TX_CREATE_RULE_MSG:
+		return sfe_create_ipv4_rule_msg(SFE_CTX_TO_PRIVATE(sfe_ctx), msg);
+	case SFE_TX_DESTROY_RULE_MSG:
+		return sfe_destroy_ipv4_rule_msg(SFE_CTX_TO_PRIVATE(sfe_ctx), msg);
+	default:
+		sfe_incr_exceptions(SFE_EXCEPTION_IPV4_MSG_UNKNOW);
+		return SFE_TX_FAILURE_NOT_ENABLED;
+	}
+}
+EXPORT_SYMBOL(sfe_ipv4_tx);
+
+/*
+ * sfe_ipv4_msg_init()
+ *	Initialize IPv4 message.
+ */
+void sfe_ipv4_msg_init(struct sfe_ipv4_msg *nim, u16 if_num, u32 type, u32 len,
+			sfe_ipv4_msg_callback_t cb, void *app_data)
+{
+	sfe_cmn_msg_init(&nim->cm, if_num, type, len, (void *)cb, app_data);
+}
+EXPORT_SYMBOL(sfe_ipv4_msg_init);
+
+/*
+ * sfe_ipv4_max_conn_count()
+ * 	Return maximum number of entries SFE supported
+ */
+int sfe_ipv4_max_conn_count(void)
+{
+	return max_ipv4_conn;
+}
+EXPORT_SYMBOL(sfe_ipv4_max_conn_count);
+
+/*
+ * sfe_ipv4_notify_register()
+ * 	Register a notifier callback for IPv4 messages from SFE
+ *
+ * @param cb The callback pointer
+ * @param app_data The application context for this message
+ *
+ * @return struct sfe_ctx_instance * The SFE context
+ */
+struct sfe_ctx_instance *sfe_ipv4_notify_register(sfe_ipv4_msg_callback_t cb, void *app_data)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+
+	spin_lock_bh(&sfe_ctx->lock);
+	/*
+	 * Hook the shortcut sync callback.
+	 */
+	if (cb && !sfe_ctx->ipv4_stats_sync_cb) {
+		sfe_ipv4_register_sync_rule_callback(sfe_ipv4_stats_sync_callback);
+	}
+
+	rcu_assign_pointer(sfe_ctx->ipv4_stats_sync_cb, cb);
+	sfe_ctx->ipv4_stats_sync_data = app_data;
+
+	spin_unlock_bh(&sfe_ctx->lock);
+
+	return SFE_CTX_TO_PUBLIC(sfe_ctx);
+}
+EXPORT_SYMBOL(sfe_ipv4_notify_register);
+
+/*
+ * sfe_ipv4_notify_unregister()
+ * 	Un-Register a notifier callback for IPv4 messages from SFE
+ */
+void sfe_ipv4_notify_unregister(void)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+
+	spin_lock_bh(&sfe_ctx->lock);
+	/*
+	 * Unregister our sync callback.
+	 */
+	if (sfe_ctx->ipv4_stats_sync_cb) {
+		sfe_ipv4_register_sync_rule_callback(NULL);
+		rcu_assign_pointer(sfe_ctx->ipv4_stats_sync_cb, NULL);
+		sfe_ctx->ipv4_stats_sync_data = NULL;
+	}
+	spin_unlock_bh(&sfe_ctx->lock);
+
+	sfe_clean_response_msg_by_type(sfe_ctx, SFE_MSG_TYPE_IPV4);
+
+	return;
+}
+EXPORT_SYMBOL(sfe_ipv4_notify_unregister);
+
+/*
+ * sfe_ipv6_stats_sync_callback()
+ *	Synchronize a connection's state.
+ */
+static void sfe_ipv6_stats_sync_callback(struct sfe_connection_sync *sis)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+	struct sfe_ipv6_msg msg;
+	struct sfe_ipv6_conn_sync *sync_msg;
+	sfe_ipv6_msg_callback_t sync_cb;
+
+	rcu_read_lock();
+	sync_cb = rcu_dereference(sfe_ctx->ipv6_stats_sync_cb);
+	if (!sync_cb) {
+		rcu_read_unlock();
+		sfe_incr_exceptions(SFE_EXCEPTION_NO_SYNC_CB);
+		return;
+	}
+
+	sync_msg = &msg.msg.conn_stats;
+
+	memset(&msg, 0, sizeof(msg));
+	sfe_cmn_msg_init(&msg.cm, 0, SFE_RX_CONN_STATS_SYNC_MSG,
+			sizeof(struct sfe_ipv6_conn_sync), NULL, NULL);
+
+	/*
+	 * Fill connection specific information
+	 */
+	sync_msg->protocol = (u8)sis->protocol;
+	sfe_ipv6_addr_copy(sis->src_ip.ip6, sync_msg->flow_ip);
+	sync_msg->flow_ident = sis->src_port;
+
+	sfe_ipv6_addr_copy(sis->dest_ip.ip6, sync_msg->return_ip);
+	sync_msg->return_ident = sis->dest_port;
+
+	/*
+	 * Fill TCP protocol specific information
+	 */
+	if (sis->protocol == IPPROTO_TCP) {
+		sync_msg->flow_max_window = sis->src_td_max_window;
+		sync_msg->flow_end = sis->src_td_end;
+		sync_msg->flow_max_end = sis->src_td_max_end;
+
+		sync_msg->return_max_window = sis->dest_td_max_window;
+		sync_msg->return_end = sis->dest_td_end;
+		sync_msg->return_max_end = sis->dest_td_max_end;
+	}
+
+	/*
+	 * Fill statistics information
+	 */
+	sync_msg->flow_rx_packet_count = sis->src_new_packet_count;
+	sync_msg->flow_rx_byte_count = sis->src_new_byte_count;
+	sync_msg->flow_tx_packet_count = sis->dest_new_packet_count;
+	sync_msg->flow_tx_byte_count = sis->dest_new_byte_count;
+
+	sync_msg->return_rx_packet_count = sis->dest_new_packet_count;
+	sync_msg->return_rx_byte_count = sis->dest_new_byte_count;
+	sync_msg->return_tx_packet_count = sis->src_new_packet_count;
+	sync_msg->return_tx_byte_count = sis->src_new_byte_count;
+
+	/*
+	 * Fill expiration time to extend, in unit of msec
+	 */
+	sync_msg->inc_ticks = (((u32)sis->delta_jiffies) * MSEC_PER_SEC)/HZ;
+
+	/*
+	 * Fill other information
+	 */
+	switch (sis->reason) {
+	case SFE_SYNC_REASON_DESTROY:
+		sync_msg->reason = SFE_RULE_SYNC_REASON_DESTROY;
+		break;
+	case SFE_SYNC_REASON_FLUSH:
+		sync_msg->reason = SFE_RULE_SYNC_REASON_FLUSH;
+		break;
+	default:
+		sync_msg->reason = SFE_RULE_SYNC_REASON_STATS;
+		break;
+	}
+
+	/*
+	 * SFE sync calling is excuted in a timer, so we can redirect it to ECM directly.
+	 */
+	sync_cb(sfe_ctx->ipv6_stats_sync_data, &msg);
+	rcu_read_unlock();
+}
+
+/*
+ * sfe_create_ipv6_rule_msg()
+ * 	convert create message format from ecm to sfe
+ *
+ * @param sfe_ctx SFE context
+ * @param msg The IPv6 message
+ *
+ * @return sfe_tx_status_t The status of the Tx operation
+ */
+sfe_tx_status_t sfe_create_ipv6_rule_msg(struct sfe_ctx_instance_internal *sfe_ctx, struct sfe_ipv6_msg *msg)
+{
+	struct net_device *src_dev = NULL;
+	struct net_device *dest_dev = NULL;
+	struct sfe_response_msg *response;
+	enum sfe_cmn_response ret = SFE_TX_SUCCESS;
+	bool is_routed = true;
+	bool cfg_err;
+
+	response = sfe_alloc_response_msg(SFE_MSG_TYPE_IPV6, msg);
+	if (!response) {
+		sfe_incr_exceptions(SFE_EXCEPTION_ENQUEUE_FAILED);
+		return SFE_TX_FAILURE_QUEUE;
+	}
+
+	if (!(msg->msg.rule_create.valid_flags & SFE_RULE_CREATE_CONN_VALID)) {
+		ret = SFE_CMN_RESPONSE_EMSG;
+		sfe_incr_exceptions(SFE_EXCEPTION_CONNECTION_INVALID);
+		goto failed_ret;
+	}
+
+	/*
+	 * Bridge flows are accelerated if L2 feature is enabled.
+	 */
+	if (msg->msg.rule_create.rule_flags & SFE_RULE_CREATE_FLAG_BRIDGE_FLOW) {
+		if (!sfe_is_l2_feature_enabled()) {
+			ret = SFE_CMN_RESPONSE_EINTERFACE;
+			sfe_incr_exceptions(SFE_EXCEPTION_NOT_SUPPORT_BRIDGE);
+			goto failed_ret;
+		}
+		is_routed = false;
+	}
+
+	switch(msg->msg.rule_create.tuple.protocol) {
+
+	case IPPROTO_TCP:
+		if (!(msg->msg.rule_create.valid_flags & SFE_RULE_CREATE_TCP_VALID)) {
+			ret = SFE_CMN_RESPONSE_EMSG;
+			sfe_incr_exceptions(SFE_EXCEPTION_TCP_INVALID);
+			goto failed_ret;
+		}
+
+		break;
+
+	case IPPROTO_UDP:
+		break;
+
+	case IPPROTO_IPIP:
+		break;
+
+	case IPPROTO_GRE:
+		break;
+
+	default:
+		ret = SFE_CMN_RESPONSE_EMSG;
+		sfe_incr_exceptions(SFE_EXCEPTION_PROTOCOL_NOT_SUPPORT);
+		goto failed_ret;
+	}
+
+	/*
+	 * Does our input device support IP processing?
+	 */
+	src_dev = dev_get_by_index(&init_net, msg->msg.rule_create.conn_rule.flow_top_interface_num);
+	if (!src_dev || !sfe_routed_dev_allow(src_dev, is_routed, false)) {
+		ret = SFE_CMN_RESPONSE_EINTERFACE;
+		sfe_incr_exceptions(SFE_EXCEPTION_SRC_DEV_NOT_L3);
+		goto failed_ret;
+	}
+
+	/*
+	 * Check whether L2 feature is disabled and rule flag is configured to use bottom interface
+	 */
+	cfg_err = (msg->msg.rule_create.rule_flags & SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE) && !sfe_is_l2_feature_enabled();
+	if (cfg_err) {
+		ret = SFE_CMN_RESPONSE_EMSG;
+		sfe_incr_exceptions(SFE_EXCEPTION_CFG_ERR);
+		goto failed_ret;
+	}
+
+	/*
+	 * Does our output device support IP processing?
+	 */
+	dest_dev = dev_get_by_index(&init_net, msg->msg.rule_create.conn_rule.return_top_interface_num);
+	if (!dest_dev || !sfe_routed_dev_allow(dest_dev, is_routed, false)) {
+		ret = SFE_CMN_RESPONSE_EINTERFACE;
+		sfe_incr_exceptions(SFE_EXCEPTION_DEST_DEV_NOT_L3);
+		goto failed_ret;
+	}
+
+	/*
+	 * Check whether L2 feature is disabled and rule flag is configured to use bottom interface
+	 */
+	cfg_err = (msg->msg.rule_create.rule_flags & SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE) && !sfe_is_l2_feature_enabled();
+	if (cfg_err) {
+		ret = SFE_CMN_RESPONSE_EMSG;
+		sfe_incr_exceptions(SFE_EXCEPTION_CFG_ERR);
+		goto failed_ret;
+	}
+
+	if (!sfe_ipv6_create_rule(&msg->msg.rule_create)) {
+		/* success */
+		ret = SFE_CMN_RESPONSE_ACK;
+	} else {
+		/* Failed */
+		ret = SFE_CMN_RESPONSE_EMSG;
+		sfe_incr_exceptions(SFE_EXCEPTION_CREATE_FAILED);
+	}
+
+	/*
+	 * Fall through
+	 */
+failed_ret:
+	if (src_dev) {
+		dev_put(src_dev);
+	}
+
+	if (dest_dev) {
+		dev_put(dest_dev);
+	}
+
+	/*
+	 * Try to queue response message
+	 */
+	((struct sfe_ipv6_msg *)response->msg)->cm.response = msg->cm.response = ret;
+	sfe_enqueue_msg(sfe_ctx, response);
+
+	return SFE_TX_SUCCESS;
+}
+
+/*
+ * sfe_destroy_ipv6_rule_msg()
+ * 	Convert destroy message format from ecm to sfe
+ *
+ * @param sfe_ctx SFE context
+ * @param msg The IPv6 message
+ *
+ * @return sfe_tx_status_t The status of the Tx operation
+ */
+sfe_tx_status_t sfe_destroy_ipv6_rule_msg(struct sfe_ctx_instance_internal *sfe_ctx, struct sfe_ipv6_msg *msg)
+{
+	struct sfe_response_msg *response;
+
+	response = sfe_alloc_response_msg(SFE_MSG_TYPE_IPV6, msg);
+	if (!response) {
+		sfe_incr_exceptions(SFE_EXCEPTION_ENQUEUE_FAILED);
+		return SFE_TX_FAILURE_QUEUE;
+	}
+
+	sfe_ipv6_destroy_rule(&msg->msg.rule_destroy);
+
+	/*
+	 * Try to queue response message
+	 */
+	((struct sfe_ipv6_msg *)response->msg)->cm.response = msg->cm.response = SFE_CMN_RESPONSE_ACK;
+	sfe_enqueue_msg(sfe_ctx, response);
+
+	return SFE_TX_SUCCESS;
+}
+
+/*
+ * sfe_ipv6_tx()
+ * 	Transmit an IPv6 message to the sfe
+ *
+ * @param sfe_ctx SFE context
+ * @param msg The IPv6 message
+ *
+ * @return sfe_tx_status_t The status of the Tx operation
+ */
+sfe_tx_status_t sfe_ipv6_tx(struct sfe_ctx_instance *sfe_ctx, struct sfe_ipv6_msg *msg)
+{
+	switch (msg->cm.type) {
+	case SFE_TX_CREATE_RULE_MSG:
+		return sfe_create_ipv6_rule_msg(SFE_CTX_TO_PRIVATE(sfe_ctx), msg);
+	case SFE_TX_DESTROY_RULE_MSG:
+		return sfe_destroy_ipv6_rule_msg(SFE_CTX_TO_PRIVATE(sfe_ctx), msg);
+	default:
+		sfe_incr_exceptions(SFE_EXCEPTION_IPV6_MSG_UNKNOW);
+		return SFE_TX_FAILURE_NOT_ENABLED;
+	}
+}
+EXPORT_SYMBOL(sfe_ipv6_tx);
+
+/*
+ * sfe_ipv6_msg_init()
+ *	Initialize IPv6 message.
+ */
+void sfe_ipv6_msg_init(struct sfe_ipv6_msg *nim, u16 if_num, u32 type, u32 len,
+			sfe_ipv6_msg_callback_t cb, void *app_data)
+{
+	sfe_cmn_msg_init(&nim->cm, if_num, type, len, (void *)cb, app_data);
+}
+EXPORT_SYMBOL(sfe_ipv6_msg_init);
+
+/*
+ * sfe_ipv6_max_conn_count()
+ * 	Return maximum number of entries SFE supported
+ */
+int sfe_ipv6_max_conn_count(void)
+{
+	return max_ipv6_conn;
+}
+EXPORT_SYMBOL(sfe_ipv6_max_conn_count);
+
+/*
+ * sfe_ipv6_notify_register()
+ * 	Register a notifier callback for IPv6 messages from SFE
+ *
+ * @param cb The callback pointer
+ * @param app_data The application context for this message
+ *
+ * @return struct sfe_ctx_instance * The SFE context
+ */
+struct sfe_ctx_instance *sfe_ipv6_notify_register(sfe_ipv6_msg_callback_t cb, void *app_data)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+
+	spin_lock_bh(&sfe_ctx->lock);
+	/*
+	 * Hook the shortcut sync callback.
+	 */
+	if (cb && !sfe_ctx->ipv6_stats_sync_cb) {
+		sfe_ipv6_register_sync_rule_callback(sfe_ipv6_stats_sync_callback);
+	}
+
+	rcu_assign_pointer(sfe_ctx->ipv6_stats_sync_cb, cb);
+	sfe_ctx->ipv6_stats_sync_data = app_data;
+
+	spin_unlock_bh(&sfe_ctx->lock);
+
+	return SFE_CTX_TO_PUBLIC(sfe_ctx);
+}
+EXPORT_SYMBOL(sfe_ipv6_notify_register);
+
+/*
+ * sfe_ipv6_notify_unregister()
+ * 	Un-Register a notifier callback for IPv6 messages from SFE
+ */
+void sfe_ipv6_notify_unregister(void)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+
+	spin_lock_bh(&sfe_ctx->lock);
+	/*
+	 * Unregister our sync callback.
+	 */
+	if (sfe_ctx->ipv6_stats_sync_cb) {
+		sfe_ipv6_register_sync_rule_callback(NULL);
+		rcu_assign_pointer(sfe_ctx->ipv6_stats_sync_cb, NULL);
+		sfe_ctx->ipv6_stats_sync_data = NULL;
+	}
+	spin_unlock_bh(&sfe_ctx->lock);
+
+	sfe_clean_response_msg_by_type(sfe_ctx, SFE_MSG_TYPE_IPV6);
+
+	return;
+}
+EXPORT_SYMBOL(sfe_ipv6_notify_unregister);
+
+/*
+ * sfe_tun6rd_tx()
+ * 	Transmit a tun6rd message to sfe engine
+ */
+sfe_tx_status_t sfe_tun6rd_tx(struct sfe_ctx_instance *sfe_ctx, struct sfe_tun6rd_msg *msg)
+{
+	sfe_incr_exceptions(SFE_EXCEPTION_NOT_SUPPORT_6RD);
+	return SFE_TX_FAILURE_NOT_ENABLED;
+}
+EXPORT_SYMBOL(sfe_tun6rd_tx);
+
+/*
+ * sfe_tun6rd_msg_init()
+ *      Initialize sfe_tun6rd msg.
+ */
+void sfe_tun6rd_msg_init(struct sfe_tun6rd_msg *ncm, u16 if_num, u32 type,  u32 len, void *cb, void *app_data)
+{
+	sfe_cmn_msg_init(&ncm->cm, if_num, type, len, cb, app_data);
+}
+EXPORT_SYMBOL(sfe_tun6rd_msg_init);
+
+/*
+ * sfe_recv()
+ *	Handle packet receives.
+ *
+ * Returns 1 if the packet is forwarded or 0 if it isn't.
+ */
+int sfe_recv(struct sk_buff *skb)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+	struct net_device *dev;
+	struct sfe_l2_info l2_info;
+	int ret;
+
+	dev = skb->dev;
+
+	/*
+	 * Apply SFE Bypass Mode policy.
+	 */
+	if (unlikely(sfe_ctx->bypass_mode == 1)) {
+		return 0;
+	}
+	if (unlikely(sfe_ctx->bypass_mode == 2 && sfe_ctx->bypass_mark &&
+		     skb->mark == sfe_ctx->bypass_mark)) {
+		return 0;
+	}
+
+	/*
+	 * Setting parse flags to 0 since l2_info is passed for non L2.5 header case as well
+	 */
+	l2_info.parse_flags = 0;
+	l2_info.l2_hdr_size = 0;
+	l2_info.vlan_hdr_cnt = 0;
+
+#ifdef CONFIG_NET_CLS_ACT
+	/*
+	 * If ingress Qdisc configured, and packet not processed by ingress Qdisc yet
+	 * We can not accelerate this packet.
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+	if (dev->ingress_queue && !(skb->tc_verd & TC_NCLS)) {
+		return 0;
+	}
+#endif
+#endif
+
+	/*
+	 * If l2_feature is enabled, we need not check if src dev is L3 interface since bridge flow offload is supported.
+	 * If l2_feature is disabled, then we make sure src dev is L3 interface to avoid cost of rule lookup for L2 flows
+	 */
+	switch (ntohs(skb->protocol)) {
+	case ETH_P_IP:
+		if (likely(sfe_is_l2_feature_enabled()) || sfe_dev_is_layer_3_interface(dev, true)) {
+			return sfe_ipv4_recv(dev, skb, &l2_info, false);
+		}
+
+		DEBUG_TRACE("No IPv4 address for device: %s skb=%px\n", dev->name, skb);
+		return 0;
+
+	case ETH_P_IPV6:
+		if (likely(sfe_is_l2_feature_enabled()) || sfe_dev_is_layer_3_interface(dev, false)) {
+			return sfe_ipv6_recv(dev, skb, &l2_info, false);
+		}
+
+		DEBUG_TRACE("No IPv6 address for device: %s skb=%px\n", dev->name, skb);
+		return 0;
+
+	default:
+		break;
+	}
+
+	/*
+	 * Stop L2 processing if L2 feature is disabled.
+	 */
+	if (!sfe_is_l2_feature_enabled()) {
+		DEBUG_TRACE("Unsupported protocol %#x %s (L2 feature is disabled) skb=%px\n",
+				ntohs(skb->protocol), dev->name, skb);
+		return 0;
+	}
+
+	/*
+	 * Parse the L2 headers to find the L3 protocol and the L2 header offset
+	 */
+	if (unlikely(!sfe_recv_parse_l2(dev, skb, &l2_info))) {
+		DEBUG_TRACE("%px: Invalid L2.5 header format with protocol : %x\n", skb, ntohs(skb->protocol));
+		goto send_to_linux;
+	}
+
+	/*
+	 * Protocol in l2_info is expected to be in host byte order.
+	 * PPPoE is doing it in the sfe_pppoe_parse_hdr()
+	 */
+	if (likely(l2_info.protocol == ETH_P_IP)) {
+		ret = sfe_ipv4_recv(dev, skb, &l2_info, false);
+		if (unlikely(!ret)) {
+			goto send_to_linux;
+		}
+		return ret;
+	}
+
+	if (likely(l2_info.protocol == ETH_P_IPV6)) {
+		ret = sfe_ipv6_recv(dev, skb, &l2_info, false);
+		if (unlikely(!ret)) {
+			goto send_to_linux;
+		}
+		return ret;
+	}
+
+	DEBUG_TRACE("Non-IP(%x) %s skb=%px skb_vlan:%x/%x/%x skb_proto=%x\n",
+			l2_info.protocol, dev->name, skb,
+			ntohs(skb->vlan_proto), skb->vlan_tci, skb_vlan_tag_present(skb),
+		       	htons(skb->protocol));
+
+send_to_linux:
+	/*
+	 * Push the data back before sending to linux if -
+	 * a. There is any exception from IPV4/V6
+	 * b. If the next protocol is neither IPV4 nor IPV6
+	 */
+	sfe_recv_undo_parse_l2(dev, skb, &l2_info);
+
+	return 0;
+}
+
+/*
+ * sfe_get_exceptions()
+ *	Dump exception counters
+ */
+static ssize_t sfe_get_exceptions(struct device *dev,
+				     struct device_attribute *attr,
+				     char *buf)
+{
+	int idx, len;
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+
+	spin_lock_bh(&sfe_ctx->lock);
+	for (len = 0, idx = 0; idx < SFE_EXCEPTION_MAX; idx++) {
+		if (sfe_ctx->exceptions[idx]) {
+			len += snprintf(buf + len, (ssize_t)(PAGE_SIZE - len), "%s = %d\n", sfe_exception_events_string[idx], sfe_ctx->exceptions[idx]);
+		}
+	}
+	spin_unlock_bh(&sfe_ctx->lock);
+
+	return len;
+}
+
+/*
+ * sysfs attributes.
+ */
+static const struct device_attribute sfe_exceptions_attr =
+	__ATTR(exceptions, S_IRUGO, sfe_get_exceptions, NULL);
+
+/*
+ * sfe_is_l2_feature_enabled()
+ *	Check if l2 features flag feature is enabled or not. (VLAN, PPPOE, BRIDGE and tunnels)
+ *
+ * 32bit read is atomic. No need of locks.
+ */
+bool sfe_is_l2_feature_enabled()
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+	return (sfe_ctx->l2_feature_support == 1);
+}
+EXPORT_SYMBOL(sfe_is_l2_feature_enabled);
+
+/*
+ * sfe_get_l2_feature()
+ *	L2 feature is enabled/disabled
+ */
+ssize_t sfe_get_l2_feature(struct device *dev,
+				     struct device_attribute *attr,
+				     char *buf)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+	ssize_t len;
+
+	spin_lock_bh(&sfe_ctx->lock);
+	len = snprintf(buf, (ssize_t)(PAGE_SIZE), "L2 feature is %s\n", sfe_ctx->l2_feature_support ? "enabled" : "disabled");
+	spin_unlock_bh(&sfe_ctx->lock);
+	return len;
+}
+
+/*
+ * sfe_set_l2_feature()
+ *	Enable or disable l2 features flag.
+ */
+ssize_t sfe_set_l2_feature(struct device *dev, struct device_attribute *attr,
+                         const char *buf, size_t count)
+{
+        unsigned long val;
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+	int ret;
+        ret = sscanf(buf, "%lu", &val);
+
+	if (ret != 1) {
+		pr_err("Wrong input, %s\n", buf);
+		return -EINVAL;
+	}
+
+	if (val != 1 && val != 0) {
+		pr_err("Input should be either 1 or 0, (%s)\n", buf);
+		return -EINVAL;
+	}
+
+	spin_lock_bh(&sfe_ctx->lock);
+
+	if (sfe_ctx->l2_feature_support && val) {
+		spin_unlock_bh(&sfe_ctx->lock);
+		pr_err("L2 feature is already enabled\n");
+		return -EINVAL;
+	}
+
+	if (!sfe_ctx->l2_feature_support && !val) {
+		spin_unlock_bh(&sfe_ctx->lock);
+		pr_err("L2 feature is already disabled\n");
+		return -EINVAL;
+	}
+
+	sfe_ctx->l2_feature_support = val;
+	spin_unlock_bh(&sfe_ctx->lock);
+
+	return count;
+}
+
+static const struct device_attribute sfe_l2_feature_attr =
+	__ATTR(l2_feature,  0644, sfe_get_l2_feature, sfe_set_l2_feature);
+
+/*
+ * SFE Bypass Mode
+ */
+static ssize_t
+sfe_get_bypass_mode(struct device *dev,	struct device_attribute *attr,
+		    char *buf)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+	return snprintf(buf, (ssize_t)PAGE_SIZE, "%d\n", sfe_ctx->bypass_mode);
+}
+
+static ssize_t
+sfe_set_bypass_mode(struct device *dev,	struct device_attribute *attr,
+		    const char *buf, size_t count)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+	int ret;
+	int bypass_mode;
+
+	ret = kstrtou32(buf, 0, &bypass_mode);
+	if (ret) {
+		return ret;
+	}
+	if (bypass_mode > 2 || bypass_mode < 0) {
+		return -EINVAL;
+	}
+	sfe_ctx->bypass_mode = bypass_mode;
+	return count;
+}
+
+static const struct device_attribute sfe_bypass_mode_attr =
+	__ATTR(bypass_mode, S_IWUSR | S_IRUGO, sfe_get_bypass_mode,
+	       sfe_set_bypass_mode);
+
+static ssize_t
+sfe_get_bypass_mark(struct device *dev,	struct device_attribute *attr,
+		    char *buf)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+	return snprintf(buf, (ssize_t)PAGE_SIZE, "0x%x\n",
+			sfe_ctx->bypass_mark);
+}
+
+static ssize_t
+sfe_set_bypass_mark(struct device *dev,	struct device_attribute *attr,
+		    const char *buf, size_t count)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+	int ret;
+	int bypass_mark;
+
+	ret = kstrtou32(buf, 0, &bypass_mark);
+	if (ret) {
+		return ret;
+	}
+	sfe_ctx->bypass_mark = bypass_mark;
+	return count;
+}
+
+static const struct device_attribute sfe_bypass_mark_attr =
+	__ATTR(bypass_mark, S_IWUSR | S_IRUGO, sfe_get_bypass_mark,
+	       sfe_set_bypass_mark);
+
+/*
+ * sfe_init_if()
+ */
+int sfe_init_if(void)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+	int result = -1;
+
+	/*
+	 * L2 feature is enabled by default
+	 */
+	sfe_ctx->l2_feature_support = 1;
+
+	/*
+	 * Create sys/sfe
+	 */
+	sfe_ctx->sys_sfe = kobject_create_and_add("sfe", NULL);
+	if (!sfe_ctx->sys_sfe) {
+		DEBUG_ERROR("failed to register sfe\n");
+		goto exit1;
+	}
+
+	/*
+	 * Create sys/sfe/exceptions
+	 */
+	result = sysfs_create_file(sfe_ctx->sys_sfe, &sfe_exceptions_attr.attr);
+	if (result) {
+		DEBUG_ERROR("failed to register exceptions file: %d\n", result);
+		goto exit2;
+	}
+
+	result = sysfs_create_file(sfe_ctx->sys_sfe, &sfe_l2_feature_attr.attr);
+	if (result) {
+		DEBUG_ERROR("failed to register L2 feature flag sysfs file: %d\n", result);
+		goto exit2;
+	}
+
+	result = sysfs_create_file(sfe_ctx->sys_sfe,
+				   &sfe_bypass_mode_attr.attr);
+	if (result) {
+		DEBUG_ERROR("failed to register Bypass Mode sysfs file: %d\n",
+			    result);
+		goto exit2;
+	}
+	result = sysfs_create_file(sfe_ctx->sys_sfe,
+				   &sfe_bypass_mark_attr.attr);
+	if (result) {
+		DEBUG_ERROR("failed to register Bypass Mark sysfs file: %d\n",
+			    result);
+		goto exit2;
+	}
+
+	spin_lock_init(&sfe_ctx->lock);
+
+	INIT_LIST_HEAD(&sfe_ctx->msg_queue);
+	INIT_WORK(&sfe_ctx->work, sfe_process_response_msg);
+
+	/*
+	 * Hook the receive path in the network stack.
+	 */
+	BUG_ON(athrs_fast_nat_recv);
+	RCU_INIT_POINTER(athrs_fast_nat_recv, sfe_recv);
+
+	return 0;
+exit2:
+	kobject_put(sfe_ctx->sys_sfe);
+exit1:
+	return result;
+}
+
+/*
+ * sfe_exit_if()
+ */
+void sfe_exit_if(void)
+{
+	struct sfe_ctx_instance_internal *sfe_ctx = &__sfe_ctx;
+
+	/*
+	 * Unregister our receive callback.
+	 */
+	RCU_INIT_POINTER(athrs_fast_nat_recv, NULL);
+
+	/*
+	 * Wait for all callbacks to complete.
+	 */
+	rcu_barrier();
+
+	/*
+	 * Destroy all connections.
+	 */
+	sfe_ipv4_destroy_all_rules_for_dev(NULL);
+	sfe_ipv6_destroy_all_rules_for_dev(NULL);
+
+	/*
+	 * stop work queue, and flush all pending message in queue
+	 */
+	cancel_work_sync(&sfe_ctx->work);
+	sfe_process_response_msg(&sfe_ctx->work);
+
+	/*
+	 * Unregister our sync callback.
+	 */
+	sfe_ipv4_notify_unregister();
+	sfe_ipv6_notify_unregister();
+
+	kobject_put(sfe_ctx->sys_sfe);
+
+	return;
+}
diff --git a/qca-nss-sfe/sfe.h b/qca-nss-sfe/sfe.h
new file mode 100644
index 0000000..59203ad
--- /dev/null
+++ b/qca-nss-sfe/sfe.h
@@ -0,0 +1,330 @@
+/*
+ * sfe.h
+ *	Shortcut forwarding engine.
+ *
+ * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __SFE_H
+#define __SFE_H
+
+/*
+ * Maximum number of accelerated IPv4 or IPv6 connections
+ */
+#if defined(SFE_MEM_PROFILE_LOW)
+#define SFE_MAX_CONNECTION_NUM 512
+#elif defined(SFE_MEM_PROFILE_MEDIUM)
+#define SFE_MAX_CONNECTION_NUM 2048
+#else
+#define SFE_MAX_CONNECTION_NUM 4096
+#endif
+
+#define SFE_L2_PARSE_FLAGS_PPPOE_INGRESS 0x01	/* Indicates presence of a valid PPPoE header */
+
+/*
+ * IPv6 address structure
+ */
+struct sfe_ipv6_addr {
+	__be32 addr[4];
+};
+
+typedef union {
+	__be32			ip;
+	struct sfe_ipv6_addr	ip6[1];
+} sfe_ip_addr_t;
+
+typedef enum sfe_sync_reason {
+	SFE_SYNC_REASON_STATS,	/* Sync is to synchronize stats */
+	SFE_SYNC_REASON_FLUSH,	/* Sync is to flush a entry */
+	SFE_SYNC_REASON_DESTROY	/* Sync is to destroy a entry(requested by connection manager) */
+} sfe_sync_reason_t;
+
+/*
+ * VLAN header (aka VLAN tag)
+ */
+struct sfe_vlan_hdr {
+	u16 tpid;               /* Tag Protocol Identifier */
+	u16 tci;                /* Tag Control Information */
+};
+
+/*
+ * Structure used to store L2 information
+ */
+struct sfe_l2_info {
+	u16 parse_flags;	/* Flags indicating L2.5 headers presence */
+	u16 l2_hdr_offset;	/* Offset of L2 header */
+	u16 l2_hdr_size;	/* L2 header size */
+	u16 pppoe_hdr_offset;	/* PPPOE header offset */
+	u16 protocol;		/* L3 Protocol */
+	struct sfe_vlan_hdr vlan_hdr[SFE_MAX_VLAN_DEPTH];
+				/* VLAN tag(s) of ingress packet */
+	u8 vlan_hdr_cnt;        /* Number of VLAN tags in the ingress packet */
+};
+
+/*
+ * Structure used to sync connection stats/state back within the system.
+ *
+ * NOTE: The addresses here are NON-NAT addresses, i.e. the true endpoint addressing.
+ * 'src' is the creator of the connection.
+ */
+struct sfe_connection_sync {
+	struct net_device *src_dev;
+	struct net_device *dest_dev;
+	int is_v6;			/* Is it for ipv6? */
+	int protocol;			/* IP protocol number (IPPROTO_...) */
+	sfe_ip_addr_t src_ip;		/* Non-NAT source address, i.e. the creator of the connection */
+	sfe_ip_addr_t src_ip_xlate;	/* NATed source address */
+	__be16 src_port;		/* Non-NAT source port */
+	__be16 src_port_xlate;		/* NATed source port */
+	sfe_ip_addr_t dest_ip;		/* Non-NAT destination address, i.e. to whom the connection was created */
+	sfe_ip_addr_t dest_ip_xlate;	/* NATed destination address */
+	__be16 dest_port;		/* Non-NAT destination port */
+	__be16 dest_port_xlate;		/* NATed destination port */
+	u32 src_td_max_window;
+	u32 src_td_end;
+	u32 src_td_max_end;
+	u64 src_packet_count;
+	u64 src_byte_count;
+	u32 src_new_packet_count;
+	u32 src_new_byte_count;
+	u32 dest_td_max_window;
+	u32 dest_td_end;
+	u32 dest_td_max_end;
+	u64 dest_packet_count;
+	u64 dest_byte_count;
+	u32 dest_new_packet_count;
+	u32 dest_new_byte_count;
+	u32 reason;                     /* reason for stats sync message, i.e. destroy, flush, period sync */
+	u64 delta_jiffies;		/* Time to be added to the current timeout to keep the connection alive */
+};
+
+/*
+ * Expose the hook for the receive processing.
+ */
+extern int (*athrs_fast_nat_recv)(struct sk_buff *skb);
+
+/*
+ * Expose what should be a static flag in the TCP connection tracker.
+ */
+extern int nf_ct_tcp_no_window_check;
+
+/*
+ * Check the fast transmit feasibility.
+ */
+bool sfe_fast_xmit_check(struct sk_buff *skb, netdev_features_t features);
+
+/*
+ * This callback will be called in a timer
+ * at 100 times per second to sync stats back to
+ * Linux connection track.
+ *
+ * A RCU lock is taken to prevent this callback
+ * from unregistering.
+ */
+typedef void (*sfe_sync_rule_callback_t)(struct sfe_connection_sync *);
+
+/*
+ * IPv4 APIs used by connection manager
+ */
+int sfe_ipv4_recv(struct net_device *dev, struct sk_buff *skb, struct sfe_l2_info *l2_info, bool tun_outer);
+int sfe_ipv4_create_rule(struct sfe_ipv4_rule_create_msg *msg);
+void sfe_ipv4_destroy_rule(struct sfe_ipv4_rule_destroy_msg *msg);
+void sfe_ipv4_destroy_all_rules_for_dev(struct net_device *dev);
+void sfe_ipv4_register_sync_rule_callback(sfe_sync_rule_callback_t callback);
+void sfe_ipv4_update_rule(struct sfe_ipv4_rule_create_msg *msg);
+bool sfe_dev_has_hw_csum(struct net_device *dev);
+
+#ifdef SFE_SUPPORT_IPV6
+/*
+ * IPv6 APIs used by connection manager
+ */
+int sfe_ipv6_recv(struct net_device *dev, struct sk_buff *skb, struct sfe_l2_info *l2_info, bool tun_outer);
+int sfe_ipv6_create_rule(struct sfe_ipv6_rule_create_msg *msg);
+void sfe_ipv6_destroy_rule(struct sfe_ipv6_rule_destroy_msg *msg);
+void sfe_ipv6_destroy_all_rules_for_dev(struct net_device *dev);
+void sfe_ipv6_register_sync_rule_callback(sfe_sync_rule_callback_t callback);
+void sfe_ipv6_update_rule(struct sfe_ipv6_rule_create_msg *msg);
+#else
+static inline int sfe_ipv6_recv(struct net_device *dev, struct sk_buff *skb, struct sfe_l2_info *l2_info, bool tun_outer)
+{
+	return 0;
+}
+
+static inline int sfe_ipv6_create_rule(struct sfe_ipv6_rule_create_msg *msg)
+{
+	return 0;
+}
+
+static inline void sfe_ipv6_destroy_rule(struct sfe_ipv6_rule_destroy_msg *msg)
+{
+	return;
+}
+
+static inline void sfe_ipv6_destroy_all_rules_for_dev(struct net_device *dev)
+{
+	return;
+}
+
+static inline void sfe_ipv6_register_sync_rule_callback(sfe_sync_rule_callback_t callback)
+{
+	return;
+}
+
+static inline void sfe_ipv6_update_rule(struct sfe_ipv6_rule_create_msg *msg)
+{
+	return;
+}
+
+#endif
+
+/*
+ * sfe_ipv6_addr_equal()
+ *	compare ipv6 address
+ *
+ * return: 1, equal; 0, no equal
+ */
+static inline int sfe_ipv6_addr_equal(struct sfe_ipv6_addr *a,
+				      struct sfe_ipv6_addr *b)
+{
+	return a->addr[0] == b->addr[0] &&
+	       a->addr[1] == b->addr[1] &&
+	       a->addr[2] == b->addr[2] &&
+	       a->addr[3] == b->addr[3];
+}
+
+/*
+ * sfe_ipv4_addr_equal()
+ *	compare ipv4 address
+ *
+ * return: 1, equal; 0, no equal
+ */
+#define sfe_ipv4_addr_equal(a, b) ((u32)(a) == (u32)(b))
+
+/*
+ * sfe_addr_equal()
+ *	compare ipv4 or ipv6 address
+ *
+ * return: 1, equal; 0, no equal
+ */
+static inline int sfe_addr_equal(sfe_ip_addr_t *a,
+				 sfe_ip_addr_t *b, int is_v4)
+{
+	return is_v4 ? sfe_ipv4_addr_equal(a->ip, b->ip) : sfe_ipv6_addr_equal(a->ip6, b->ip6);
+}
+
+/*
+ * sfe_l2_parse_flag_set()
+ *	Set L2 parse flag
+ */
+static inline void sfe_l2_parse_flag_set(struct sfe_l2_info *l2_info, u16 flag)
+{
+	l2_info->parse_flags |= flag;
+}
+
+/*
+ * sfe_l2_parse_flag_get()
+ *	Get L2 parse flag
+ */
+static inline u16 sfe_l2_parse_flag_get(struct sfe_l2_info *l2_info)
+{
+	return l2_info->parse_flags;
+}
+
+/*
+ * sfe_l2_parse_flag_check()
+ *	Check L2 parse flag
+ */
+static inline bool sfe_l2_parse_flag_check(struct sfe_l2_info *l2_info, u16 flag)
+{
+	return !!(l2_info->parse_flags & flag);
+}
+
+/*
+ * sfe_l2_hdr_offset_get()
+ *	Get L2 header offset
+ */
+static inline u16 sfe_l2_hdr_offset_get(struct sfe_l2_info *l2_info)
+{
+	return l2_info->l2_hdr_offset;
+}
+
+/*
+ * sfe_l2_hdr_offset_set()
+ *	Set L2 header offset
+ */
+static inline void sfe_l2_hdr_offset_set(struct sfe_l2_info *l2_info, u16 offset)
+{
+	l2_info->l2_hdr_offset = offset;
+}
+
+/*
+ * sfe_l2_pppoe_hdr_offset_get()
+ *	Get L2 PPPoE header offset
+ */
+static inline u16 sfe_l2_pppoe_hdr_offset_get(struct sfe_l2_info *l2_info)
+{
+	return l2_info->pppoe_hdr_offset;
+}
+
+/*
+ * sfe_l2_pppoe_hdr_offset_set()
+ *	Set L2 PPPoE header offset
+ */
+static inline void sfe_l2_pppoe_hdr_offset_set(struct sfe_l2_info *l2_info, u16 offset)
+{
+	l2_info->pppoe_hdr_offset = offset;
+}
+
+/*
+ * sfe_l2_hdr_size_get()
+ *	Get L2 header size
+ */
+static inline u16 sfe_l2_hdr_size_get(struct sfe_l2_info *l2_info)
+{
+	return l2_info->l2_hdr_size;
+}
+
+/*
+ * sfe_l2_hdr_size_set()
+ *	Set L2 header size
+ */
+static inline void sfe_l2_hdr_size_set(struct sfe_l2_info *l2_info, u16 size)
+{
+	l2_info->l2_hdr_size = size;
+}
+
+/*
+ * sfe_l2_protocol_get()
+ *	Get L2 protocol
+ */
+static inline u16 sfe_l2_protocol_get(struct sfe_l2_info *l2_info)
+{
+	return l2_info->protocol;
+}
+
+/*
+ * sfe_l2_protocol_set()
+ *	Set L2 protocol
+ */
+static inline void sfe_l2_protocol_set(struct sfe_l2_info *l2_info, u16 proto)
+{
+	l2_info->protocol = proto;
+}
+
+int sfe_init_if(void);
+void sfe_exit_if(void);
+
+#endif /* __SFE_H */
diff --git a/qca-nss-sfe/sfe_debug.h b/qca-nss-sfe/sfe_debug.h
new file mode 100644
index 0000000..f029823
--- /dev/null
+++ b/qca-nss-sfe/sfe_debug.h
@@ -0,0 +1,72 @@
+
+/*
+ * sfe_debug.h
+ *	SFE debug macros.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * The following are debug macros used throughout the SFE.
+ *
+ * The DEBUG_LEVEL enables the followings based on its value,
+ * when dynamic debug option is disabled.
+ *
+ * 0 = OFF
+ * 1 = ASSERTS / ERRORS
+ * 2 = 1 + WARN
+ * 3 = 2 + INFO
+ * 4 = 3 + TRACE
+ */
+#define DEBUG_LEVEL 2
+
+#if (DEBUG_LEVEL < 1)
+#define DEBUG_ASSERT(s, ...)
+#define DEBUG_ERROR(s, ...)
+#else
+#define DEBUG_ASSERT(c, s, ...) if (!(c)) { pr_emerg("ASSERT: %s:%d:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__); BUG(); }
+#define DEBUG_ERROR(s, ...) pr_err("%s:%d:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define DEBUG_WARN(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define DEBUG_INFO(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define DEBUG_TRACE(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#else
+
+/*
+ * Statically compile messages at different levels
+ */
+#if (DEBUG_LEVEL < 2)
+#define DEBUG_WARN(s, ...)
+#else
+#define DEBUG_WARN(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (DEBUG_LEVEL < 3)
+#define DEBUG_INFO(s, ...)
+#else
+#define DEBUG_INFO(s, ...) pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+
+#if (DEBUG_LEVEL < 4)
+#define DEBUG_TRACE(s, ...)
+#else
+#define DEBUG_TRACE(s, ...) pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#endif
+#endif
diff --git a/qca-nss-sfe/sfe_flow_cookie.h b/qca-nss-sfe/sfe_flow_cookie.h
new file mode 100644
index 0000000..309f92e
--- /dev/null
+++ b/qca-nss-sfe/sfe_flow_cookie.h
@@ -0,0 +1,79 @@
+/*
+ * sfe_flow_cookie.h
+ *	Flow cookie related callbacks.
+ *
+ * Copyright (c) 2013-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+#define SFE_FLOW_COOKIE_SIZE 2048
+#define SFE_FLOW_COOKIE_MASK 0x7ff
+
+struct sfe_ipv4_connection_match;
+struct sfe_ipv6_connection_match;
+
+struct sfe_flow_cookie_entry {
+	struct sfe_ipv4_connection_match *match;
+	unsigned long last_clean_time;
+};
+
+struct sfe_ipv6_flow_cookie_entry {
+	struct sfe_ipv6_connection_match *match;
+	unsigned long last_clean_time;
+};
+
+typedef int (*flow_cookie_set_func_t)(u32 protocol, __be32 src_ip, __be16 src_port,
+				      __be32 dst_ip, __be16 dst_port, u16 flow_cookie);
+/*
+ * sfe_register_flow_cookie_cb
+ *	register a function in SFE to let SFE use this function to configure flow cookie for a flow
+ *
+ * Hardware driver which support flow cookie should register a callback function in SFE. Then SFE
+ * can use this function to configure flow cookie for a flow.
+ * return: 0, success; !=0, fail
+ */
+int sfe_register_flow_cookie_cb(flow_cookie_set_func_t cb);
+
+/*
+ * sfe_unregister_flow_cookie_cb
+ *	unregister function which is used to configure flow cookie for a flow
+ *
+ * return: 0, success; !=0, fail
+ */
+int sfe_unregister_flow_cookie_cb(flow_cookie_set_func_t cb);
+
+typedef int (*sfe_ipv6_flow_cookie_set_func_t)(u32 protocol, __be32 src_ip[4], __be16 src_port,
+						__be32 dst_ip[4], __be16 dst_port, u16 flow_cookie);
+
+/*
+ * sfe_ipv6_register_flow_cookie_cb
+ *	register a function in SFE to let SFE use this function to configure flow cookie for a flow
+ *
+ * Hardware driver which support flow cookie should register a callback function in SFE. Then SFE
+ * can use this function to configure flow cookie for a flow.
+ * return: 0, success; !=0, fail
+ */
+int sfe_ipv6_register_flow_cookie_cb(sfe_ipv6_flow_cookie_set_func_t cb);
+
+/*
+ * sfe_ipv6_unregister_flow_cookie_cb
+ *	unregister function which is used to configure flow cookie for a flow
+ *
+ * return: 0, success; !=0, fail
+ */
+int sfe_ipv6_unregister_flow_cookie_cb(sfe_ipv6_flow_cookie_set_func_t cb);
+
+#endif /*CONFIG_NF_FLOW_COOKIE*/
diff --git a/qca-nss-sfe/sfe_init.c b/qca-nss-sfe/sfe_init.c
new file mode 100644
index 0000000..8f9e150
--- /dev/null
+++ b/qca-nss-sfe/sfe_init.c
@@ -0,0 +1,104 @@
+/*
+ * sfe_init.c
+ *	Shortcut forwarding engine initialization.
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/sysfs.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <net/tcp.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+
+#include "sfe_api.h"
+#include "sfe.h"
+#include "sfe_ipv4.h"
+#include "sfe_ipv6.h"
+
+int max_ipv4_conn = SFE_MAX_CONNECTION_NUM;
+module_param(max_ipv4_conn, int, S_IRUGO);
+MODULE_PARM_DESC(max_ipv4_conn, "Max number of IPv4 connections");
+
+int max_ipv6_conn = SFE_MAX_CONNECTION_NUM;
+module_param(max_ipv6_conn, int, S_IRUGO);
+MODULE_PARM_DESC(max_ipv6_conn, "Max number of IPv6 connections");
+
+/*
+ * sfe_init()
+ *	Initialize SFE engine.
+ */
+static int __init sfe_init(void)
+{
+	/*
+	 * Initialize SFE IPv4 engine.
+	 */
+	if (sfe_ipv4_init()) {
+		goto fail0;
+	}
+
+#ifdef SFE_SUPPORT_IPV6
+
+	/*
+	 * Initialize SFE IPv6 engine.
+	 */
+	if (sfe_ipv6_init()) {
+		goto fail1;
+	}
+#endif
+
+	/*
+	 * Initialize SFE infrastructure and register SFE hook with Linux stack
+	 */
+	if (sfe_init_if()) {
+		goto fail2;
+	}
+
+	return 0;
+
+fail2:
+#ifdef SFE_SUPPORT_IPV6
+	sfe_ipv6_exit();
+fail1:
+#endif
+
+	sfe_ipv4_exit();
+
+fail0:
+
+	return -1;
+}
+
+/*
+ * sfe_exit()
+ */
+static void __exit sfe_exit(void)
+{
+
+	sfe_exit_if();
+
+#ifdef SFE_SUPPORT_IPV6
+	sfe_ipv6_exit();
+#endif
+	sfe_ipv4_exit();
+}
+
+module_init(sfe_init)
+module_exit(sfe_exit)
+
+MODULE_AUTHOR("Qualcomm Technologies");
+MODULE_DESCRIPTION("Shortcut Forwarding Engine");
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/qca-nss-sfe/sfe_ipv4.c b/qca-nss-sfe/sfe_ipv4.c
new file mode 100644
index 0000000..1fd2883
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv4.c
@@ -0,0 +1,2800 @@
+/*
+ * sfe_ipv4.c
+ *	Shortcut forwarding engine - IPv4 edition.
+ *
+ * Copyright (c) 2013-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/module.h>
+#include <linux/sysfs.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <net/tcp.h>
+#include <net/udp.h>
+#include <net/vxlan.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#include <linux/lockdep.h>
+#include <linux/refcount.h>
+#include <linux/netfilter.h>
+#include <linux/inetdevice.h>
+#include <linux/netfilter_ipv4.h>
+#include <net/protocol.h>
+#include <net/gre.h>
+
+#include "sfe_debug.h"
+#include "sfe_api.h"
+#include "sfe.h"
+#include "sfe_flow_cookie.h"
+#include "sfe_ipv4.h"
+#include "sfe_ipv4_udp.h"
+#include "sfe_ipv4_tcp.h"
+#include "sfe_ipv4_icmp.h"
+#include "sfe_pppoe.h"
+#include "sfe_ipv4_gre.h"
+
+static char *sfe_ipv4_exception_events_string[SFE_IPV4_EXCEPTION_EVENT_LAST] = {
+	"UDP_HEADER_INCOMPLETE",
+	"UDP_NO_CONNECTION",
+	"UDP_IP_OPTIONS_OR_INITIAL_FRAGMENT",
+	"UDP_SMALL_TTL",
+	"UDP_NEEDS_FRAGMENTATION",
+	"TCP_HEADER_INCOMPLETE",
+	"TCP_NO_CONNECTION_SLOW_FLAGS",
+	"TCP_NO_CONNECTION_FAST_FLAGS",
+	"TCP_IP_OPTIONS_OR_INITIAL_FRAGMENT",
+	"TCP_SMALL_TTL",
+	"TCP_NEEDS_FRAGMENTATION",
+	"TCP_FLAGS",
+	"TCP_SEQ_EXCEEDS_RIGHT_EDGE",
+	"TCP_SMALL_DATA_OFFS",
+	"TCP_BAD_SACK",
+	"TCP_BIG_DATA_OFFS",
+	"TCP_SEQ_BEFORE_LEFT_EDGE",
+	"TCP_ACK_EXCEEDS_RIGHT_EDGE",
+	"TCP_ACK_BEFORE_LEFT_EDGE",
+	"ICMP_HEADER_INCOMPLETE",
+	"ICMP_UNHANDLED_TYPE",
+	"ICMP_IPV4_HEADER_INCOMPLETE",
+	"ICMP_IPV4_NON_V4",
+	"ICMP_IPV4_IP_OPTIONS_INCOMPLETE",
+	"ICMP_IPV4_UDP_HEADER_INCOMPLETE",
+	"ICMP_IPV4_TCP_HEADER_INCOMPLETE",
+	"ICMP_IPV4_UNHANDLED_PROTOCOL",
+	"ICMP_NO_CONNECTION",
+	"ICMP_FLUSHED_CONNECTION",
+	"HEADER_INCOMPLETE",
+	"HEADER_CSUM_BAD",
+	"BAD_TOTAL_LENGTH",
+	"NON_V4",
+	"NON_INITIAL_FRAGMENT",
+	"DATAGRAM_INCOMPLETE",
+	"IP_OPTIONS_INCOMPLETE",
+	"UNHANDLED_PROTOCOL",
+	"NO_HEADROOM",
+	"INVALID_PPPOE_SESSION",
+	"INCORRECT_PPPOE_PARSING",
+	"PPPOE_NOT_SET_IN_CME",
+	"INGRESS_VLAN_TAG_MISMATCH",
+	"INVALID_SOURCE_INTERFACE",
+	"GRE_HEADER_INCOMPLETE",
+	"GRE_NO_CONNECTION",
+	"GRE_IP_OPTIONS_OR_INITIAL_FRAGMENT",
+	"GRE_SMALL_TTL",
+	"GRE_NEEDS_FRAGMENTATION"
+};
+
+static struct sfe_ipv4 __si;
+
+/*
+ * sfe_ipv4_gen_ip_csum()
+ *	Generate the IP checksum for an IPv4 header.
+ *
+ * Note that this function assumes that we have only 20 bytes of IP header.
+ */
+u16 sfe_ipv4_gen_ip_csum(struct iphdr *iph)
+{
+	u32 sum;
+	u16 *i = (u16 *)iph;
+
+	iph->check = 0;
+
+	/*
+	 * Generate the sum.
+	 */
+	sum = i[0] + i[1] + i[2] + i[3] + i[4] + i[5] + i[6] + i[7] + i[8] + i[9];
+
+	/*
+	 * Fold it to ones-complement form.
+	 */
+	sum = (sum & 0xffff) + (sum >> 16);
+	sum = (sum & 0xffff) + (sum >> 16);
+
+	return (u16)sum ^ 0xffff;
+}
+
+/*
+ * sfe_ipv4_get_connection_match_hash()
+ *	Generate the hash used in connection match lookups.
+ */
+static inline unsigned int sfe_ipv4_get_connection_match_hash(struct net_device *dev, u8 protocol,
+							      __be32 src_ip, __be16 src_port,
+							      __be32 dest_ip, __be16 dest_port)
+{
+	u32 hash =  ntohl(src_ip ^ dest_ip) ^ protocol ^ ntohs(src_port ^ dest_port);
+	return ((hash >> SFE_IPV4_CONNECTION_HASH_SHIFT) ^ hash) & SFE_IPV4_CONNECTION_HASH_MASK;
+}
+
+/*
+ * sfe_ipv4_find_connection_match_rcu()
+ *	Get the IPv4 flow match info that corresponds to a particular 5-tuple.
+ *
+ * On entry we must be holding the lock that protects the hash table.
+ */
+struct sfe_ipv4_connection_match *
+sfe_ipv4_find_connection_match_rcu(struct sfe_ipv4 *si, struct net_device *dev, u8 protocol,
+					__be32 src_ip, __be16 src_port,
+					__be32 dest_ip, __be16 dest_port)
+{
+	struct sfe_ipv4_connection_match *cm = NULL;
+	unsigned int conn_match_idx;
+	struct hlist_head *lhead;
+
+	WARN_ON_ONCE(!rcu_read_lock_held());
+
+	conn_match_idx = sfe_ipv4_get_connection_match_hash(dev, protocol, src_ip, src_port, dest_ip, dest_port);
+
+	lhead = &si->hlist_conn_match_hash_head[conn_match_idx];
+
+	hlist_for_each_entry_rcu(cm, lhead, hnode) {
+		if (cm->match_src_port != src_port
+			   || cm->match_dest_port != dest_port
+			   || cm->match_src_ip != src_ip
+			   || cm->match_dest_ip != dest_ip
+			   || cm->match_protocol != protocol) {
+			continue;
+		}
+
+		this_cpu_inc(si->stats_pcpu->connection_match_hash_hits64);
+
+		break;
+	}
+
+	return cm;
+}
+
+/*
+ * sfe_ipv4_connection_match_update_summary_stats()
+ *	Update the summary stats for a connection match entry.
+ *
+ * Stats are incremented atomically. So use atomic substraction to update summary
+ * stats.
+ */
+static inline void sfe_ipv4_connection_match_update_summary_stats(struct sfe_ipv4_connection_match *cm,
+						u32 *packets, u32 *bytes)
+{
+	u32 packet_count, byte_count;
+
+	packet_count = atomic_read(&cm->rx_packet_count);
+	cm->rx_packet_count64 += packet_count;
+	atomic_sub(packet_count, &cm->rx_packet_count);
+
+	byte_count = atomic_read(&cm->rx_byte_count);
+	cm->rx_byte_count64 += byte_count;
+	atomic_sub(byte_count, &cm->rx_byte_count);
+
+	*packets = packet_count;
+	*bytes = byte_count;
+}
+
+/*
+ * sfe_ipv4_connection_match_compute_translations()
+ *	Compute port and address translations for a connection match entry.
+ */
+static void sfe_ipv4_connection_match_compute_translations(struct sfe_ipv4_connection_match *cm)
+{
+	/*
+	 * Before we insert the entry look to see if this is tagged as doing address
+	 * translations.  If it is then work out the adjustment that we need to apply
+	 * to the transport checksum.
+	 */
+	if (cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_SRC) {
+		/*
+		 * Precompute an incremental checksum adjustment so we can
+		 * edit packets in this stream very quickly.  The algorithm is from RFC1624.
+		 */
+		u16 src_ip_hi = cm->match_src_ip >> 16;
+		u16 src_ip_lo = cm->match_src_ip & 0xffff;
+		u32 xlate_src_ip = ~cm->xlate_src_ip;
+		u16 xlate_src_ip_hi = xlate_src_ip >> 16;
+		u16 xlate_src_ip_lo = xlate_src_ip & 0xffff;
+		u16 xlate_src_port = ~cm->xlate_src_port;
+		u32 adj;
+
+		/*
+		 * When we compute this fold it down to a 16-bit offset
+		 * as that way we can avoid having to do a double
+		 * folding of the twos-complement result because the
+		 * addition of 2 16-bit values cannot cause a double
+		 * wrap-around!
+		 */
+		adj = src_ip_hi + src_ip_lo + cm->match_src_port
+		      + xlate_src_ip_hi + xlate_src_ip_lo + xlate_src_port;
+		adj = (adj & 0xffff) + (adj >> 16);
+		adj = (adj & 0xffff) + (adj >> 16);
+		cm->xlate_src_csum_adjustment = (u16)adj;
+
+	}
+
+	if (cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_DEST) {
+		/*
+		 * Precompute an incremental checksum adjustment so we can
+		 * edit packets in this stream very quickly.  The algorithm is from RFC1624.
+		 */
+		u16 dest_ip_hi = cm->match_dest_ip >> 16;
+		u16 dest_ip_lo = cm->match_dest_ip & 0xffff;
+		u32 xlate_dest_ip = ~cm->xlate_dest_ip;
+		u16 xlate_dest_ip_hi = xlate_dest_ip >> 16;
+		u16 xlate_dest_ip_lo = xlate_dest_ip & 0xffff;
+		u16 xlate_dest_port = ~cm->xlate_dest_port;
+		u32 adj;
+
+		/*
+		 * When we compute this fold it down to a 16-bit offset
+		 * as that way we can avoid having to do a double
+		 * folding of the twos-complement result because the
+		 * addition of 2 16-bit values cannot cause a double
+		 * wrap-around!
+		 */
+		adj = dest_ip_hi + dest_ip_lo + cm->match_dest_port
+		      + xlate_dest_ip_hi + xlate_dest_ip_lo + xlate_dest_port;
+		adj = (adj & 0xffff) + (adj >> 16);
+		adj = (adj & 0xffff) + (adj >> 16);
+		cm->xlate_dest_csum_adjustment = (u16)adj;
+	}
+
+	if (cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_SRC) {
+		u32 adj = ~cm->match_src_ip + cm->xlate_src_ip;
+		if (adj < cm->xlate_src_ip) {
+			adj++;
+		}
+
+		adj = (adj & 0xffff) + (adj >> 16);
+		adj = (adj & 0xffff) + (adj >> 16);
+		cm->xlate_src_partial_csum_adjustment = (u16)adj;
+	}
+
+	if (cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_DEST) {
+		u32 adj = ~cm->match_dest_ip + cm->xlate_dest_ip;
+		if (adj < cm->xlate_dest_ip) {
+			adj++;
+		}
+
+		adj = (adj & 0xffff) + (adj >> 16);
+		adj = (adj & 0xffff) + (adj >> 16);
+		cm->xlate_dest_partial_csum_adjustment = (u16)adj;
+	}
+
+}
+
+/*
+ * sfe_ipv4_update_summary_stats()
+ *	Update the summary stats.
+ */
+static void sfe_ipv4_update_summary_stats(struct sfe_ipv4 *si,  struct sfe_ipv4_stats *stats)
+{
+	int i = 0;
+
+	memset(stats, 0, sizeof(*stats));
+
+	for_each_possible_cpu(i) {
+		const struct sfe_ipv4_stats *s = per_cpu_ptr(si->stats_pcpu, i);
+
+		stats->connection_create_requests64 += s->connection_create_requests64;
+		stats->connection_create_collisions64 += s->connection_create_collisions64;
+		stats->connection_create_failures64 += s->connection_create_failures64;
+		stats->connection_destroy_requests64 += s->connection_destroy_requests64;
+		stats->connection_destroy_misses64 += s->connection_destroy_misses64;
+		stats->connection_match_hash_hits64 += s->connection_match_hash_hits64;
+		stats->connection_match_hash_reorders64 += s->connection_match_hash_reorders64;
+		stats->connection_flushes64 += s->connection_flushes64;
+		stats->packets_dropped64 += s->packets_dropped64;
+		stats->packets_forwarded64 += s->packets_forwarded64;
+		stats->packets_fast_xmited64 += s->packets_fast_xmited64;
+		stats->packets_not_forwarded64 += s->packets_not_forwarded64;
+		stats->pppoe_encap_packets_forwarded64 += s->pppoe_encap_packets_forwarded64;
+		stats->pppoe_decap_packets_forwarded64 += s->pppoe_decap_packets_forwarded64;
+		stats->pppoe_bridge_packets_forwarded64 += s->pppoe_bridge_packets_forwarded64;
+	}
+
+}
+
+/*
+ * sfe_ipv4_insert_connection_match()
+ *	Insert a connection match into the hash.
+ */
+static inline void sfe_ipv4_insert_connection_match(struct sfe_ipv4 *si,
+							     struct sfe_ipv4_connection_match *cm)
+{
+	unsigned int conn_match_idx
+		= sfe_ipv4_get_connection_match_hash(cm->match_dev, cm->match_protocol,
+						     cm->match_src_ip, cm->match_src_port,
+						     cm->match_dest_ip, cm->match_dest_port);
+
+	lockdep_assert_held(&si->lock);
+
+	hlist_add_head_rcu(&cm->hnode, &si->hlist_conn_match_hash_head[conn_match_idx]);
+#ifdef CONFIG_NF_FLOW_COOKIE
+	if (!si->flow_cookie_enable)
+		return;
+
+	/*
+	 * Configure hardware to put a flow cookie in packet of this flow,
+	 * then we can accelerate the lookup process when we received this packet.
+	 */
+	for (conn_match_idx = 1; conn_match_idx < SFE_FLOW_COOKIE_SIZE; conn_match_idx++) {
+		struct sfe_flow_cookie_entry *entry = &si->sfe_flow_cookie_table[conn_match_idx];
+
+		if ((NULL == entry->match) && time_is_before_jiffies(entry->last_clean_time + HZ)) {
+			flow_cookie_set_func_t func;
+
+			rcu_read_lock();
+			func = rcu_dereference(si->flow_cookie_set_func);
+			if (func) {
+				if (!func(cm->match_protocol, cm->match_src_ip, cm->match_src_port,
+					 cm->match_dest_ip, cm->match_dest_port, conn_match_idx)) {
+					entry->match = cm;
+					cm->flow_cookie = conn_match_idx;
+				}
+			}
+			rcu_read_unlock();
+
+			break;
+		}
+	}
+#endif
+}
+
+/*
+ * sfe_ipv4_remove_connection_match()
+ *	Remove a connection match object from the hash.
+ */
+static inline void sfe_ipv4_remove_connection_match(struct sfe_ipv4 *si, struct sfe_ipv4_connection_match *cm)
+{
+
+	lockdep_assert_held(&si->lock);
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+	if (si->flow_cookie_enable) {
+		/*
+		 * Tell hardware that we no longer need a flow cookie in packet of this flow
+		 */
+		unsigned int conn_match_idx;
+
+		for (conn_match_idx = 1; conn_match_idx < SFE_FLOW_COOKIE_SIZE; conn_match_idx++) {
+			struct sfe_flow_cookie_entry *entry = &si->sfe_flow_cookie_table[conn_match_idx];
+
+			if (cm == entry->match) {
+				flow_cookie_set_func_t func;
+
+				rcu_read_lock();
+				func = rcu_dereference(si->flow_cookie_set_func);
+				if (func) {
+					func(cm->match_protocol, cm->match_src_ip, cm->match_src_port,
+					     cm->match_dest_ip, cm->match_dest_port, 0);
+				}
+				rcu_read_unlock();
+
+				cm->flow_cookie = 0;
+				entry->match = NULL;
+				entry->last_clean_time = jiffies;
+				break;
+			}
+		}
+	}
+#endif
+
+	hlist_del_init_rcu(&cm->hnode);
+
+}
+
+/*
+ * sfe_ipv4_get_connection_hash()
+ *	Generate the hash used in connection lookups.
+ */
+static inline unsigned int sfe_ipv4_get_connection_hash(u8 protocol, __be32 src_ip, __be16 src_port,
+							__be32 dest_ip, __be16 dest_port)
+{
+	u32 hash = ntohl(src_ip ^ dest_ip) ^ protocol ^ ntohs(src_port ^ dest_port);
+	return ((hash >> SFE_IPV4_CONNECTION_HASH_SHIFT) ^ hash) & SFE_IPV4_CONNECTION_HASH_MASK;
+}
+
+/*
+ * sfe_ipv4_find_connection()
+ *	Get the IPv4 connection info that corresponds to a particular 5-tuple.
+ *
+ * On entry we must be holding the lock that protects the hash table.
+ */
+static inline struct sfe_ipv4_connection *sfe_ipv4_find_connection(struct sfe_ipv4 *si, u32 protocol,
+									    __be32 src_ip, __be16 src_port,
+									    __be32 dest_ip, __be16 dest_port)
+{
+	struct sfe_ipv4_connection *c;
+	unsigned int conn_idx = sfe_ipv4_get_connection_hash(protocol, src_ip, src_port, dest_ip, dest_port);
+
+	lockdep_assert_held(&si->lock);
+
+	c = si->conn_hash[conn_idx];
+
+	/*
+	 * Will need connection entry for next create/destroy metadata,
+	 * So no need to re-order entry for these requests
+	 */
+	while (c) {
+		if ((c->src_port == src_port)
+		    && (c->dest_port == dest_port)
+		    && (c->src_ip == src_ip)
+		    && (c->dest_ip == dest_ip)
+		    && (c->protocol == protocol)) {
+			return c;
+		}
+
+		c = c->next;
+	}
+
+	return NULL;
+}
+
+/*
+ * sfe_ipv4_insert_connection()
+ *	Insert a connection into the hash.
+ *
+ * On entry we must be holding the lock that protects the hash table.
+ */
+static void sfe_ipv4_insert_connection(struct sfe_ipv4 *si, struct sfe_ipv4_connection *c)
+{
+	struct sfe_ipv4_connection **hash_head;
+	struct sfe_ipv4_connection *prev_head;
+	unsigned int conn_idx;
+
+	lockdep_assert_held(&si->lock);
+
+	/*
+	 * Insert entry into the connection hash.
+	 */
+	conn_idx = sfe_ipv4_get_connection_hash(c->protocol, c->src_ip, c->src_port,
+						c->dest_ip, c->dest_port);
+	hash_head = &si->conn_hash[conn_idx];
+	prev_head = *hash_head;
+	c->prev = NULL;
+	if (prev_head) {
+		prev_head->prev = c;
+	}
+
+	c->next = prev_head;
+	*hash_head = c;
+
+	/*
+	 * Insert entry into the "all connections" list.
+	 */
+	if (si->all_connections_tail) {
+		c->all_connections_prev = si->all_connections_tail;
+		si->all_connections_tail->all_connections_next = c;
+	} else {
+		c->all_connections_prev = NULL;
+		si->all_connections_head = c;
+	}
+
+	si->all_connections_tail = c;
+	c->all_connections_next = NULL;
+	si->num_connections++;
+
+	/*
+	 * Insert the connection match objects too.
+	 */
+	sfe_ipv4_insert_connection_match(si, c->original_match);
+	sfe_ipv4_insert_connection_match(si, c->reply_match);
+}
+
+/*
+ * sfe_ipv4_remove_connection()
+ *	Remove a sfe_ipv4_connection object from the hash.
+ */
+bool sfe_ipv4_remove_connection(struct sfe_ipv4 *si, struct sfe_ipv4_connection *c)
+{
+	lockdep_assert_held(&si->lock);
+
+	if (c->removed) {
+		DEBUG_ERROR("%px: Connection has been removed already\n", c);
+		return false;
+	}
+
+	/*
+	 * Remove the connection match objects.
+	 */
+	sfe_ipv4_remove_connection_match(si, c->reply_match);
+	sfe_ipv4_remove_connection_match(si, c->original_match);
+
+	/*
+	 * Unlink the connection.
+	 */
+	if (c->prev) {
+		c->prev->next = c->next;
+	} else {
+		unsigned int conn_idx = sfe_ipv4_get_connection_hash(c->protocol, c->src_ip, c->src_port,
+								     c->dest_ip, c->dest_port);
+		si->conn_hash[conn_idx] = c->next;
+	}
+
+	if (c->next) {
+		c->next->prev = c->prev;
+	}
+
+	/*
+	 * Unlink connection from all_connections list
+	 */
+	if (c->all_connections_prev) {
+		c->all_connections_prev->all_connections_next = c->all_connections_next;
+	} else {
+		si->all_connections_head = c->all_connections_next;
+	}
+
+	if (c->all_connections_next) {
+		c->all_connections_next->all_connections_prev = c->all_connections_prev;
+	} else {
+		si->all_connections_tail = c->all_connections_prev;
+	}
+
+	/*
+	 * If I am the next sync connection, move the sync to my next or head.
+	 */
+	if (unlikely(si->wc_next == c)) {
+		si->wc_next = c->all_connections_next;
+	}
+
+	c->removed = true;
+	si->num_connections--;
+	return true;
+}
+
+/*
+ * sfe_ipv4_gen_sync_connection()
+ *	Sync a connection.
+ *
+ * On entry to this function we expect that the lock for the connection is either
+ * already held (while called from sfe_ipv4_periodic_sync() or isn't required
+ * (while called from sfe_ipv4_flush_connection())
+ */
+static void sfe_ipv4_gen_sync_connection(struct sfe_ipv4 *si, struct sfe_ipv4_connection *c,
+						  struct sfe_connection_sync *sis, sfe_sync_reason_t reason,
+						  u64 now_jiffies)
+{
+	struct sfe_ipv4_connection_match *original_cm;
+	struct sfe_ipv4_connection_match *reply_cm;
+	u32 packet_count, byte_count;
+
+	/*
+	 * Fill in the update message.
+	 */
+	sis->is_v6 = 0;
+	sis->protocol = c->protocol;
+	sis->src_ip.ip = c->src_ip;
+	sis->src_ip_xlate.ip = c->src_ip_xlate;
+	sis->dest_ip.ip = c->dest_ip;
+	sis->dest_ip_xlate.ip = c->dest_ip_xlate;
+	sis->src_port = c->src_port;
+	sis->src_port_xlate = c->src_port_xlate;
+	sis->dest_port = c->dest_port;
+	sis->dest_port_xlate = c->dest_port_xlate;
+
+	original_cm = c->original_match;
+	reply_cm = c->reply_match;
+	sis->src_td_max_window = original_cm->protocol_state.tcp.max_win;
+	sis->src_td_end = original_cm->protocol_state.tcp.end;
+	sis->src_td_max_end = original_cm->protocol_state.tcp.max_end;
+	sis->dest_td_max_window = reply_cm->protocol_state.tcp.max_win;
+	sis->dest_td_end = reply_cm->protocol_state.tcp.end;
+	sis->dest_td_max_end = reply_cm->protocol_state.tcp.max_end;
+
+	sfe_ipv4_connection_match_update_summary_stats(original_cm, &packet_count, &byte_count);
+	sis->src_new_packet_count = packet_count;
+	sis->src_new_byte_count = byte_count;
+
+	sfe_ipv4_connection_match_update_summary_stats(reply_cm, &packet_count, &byte_count);
+	sis->dest_new_packet_count = packet_count;
+	sis->dest_new_byte_count = byte_count;
+
+	sis->src_dev = original_cm->match_dev;
+	sis->src_packet_count = original_cm->rx_packet_count64;
+	sis->src_byte_count = original_cm->rx_byte_count64;
+
+	sis->dest_dev = reply_cm->match_dev;
+	sis->dest_packet_count = reply_cm->rx_packet_count64;
+	sis->dest_byte_count = reply_cm->rx_byte_count64;
+
+	sis->reason = reason;
+
+	/*
+	 * Get the time increment since our last sync.
+	 */
+	sis->delta_jiffies = now_jiffies - c->last_sync_jiffies;
+	c->last_sync_jiffies = now_jiffies;
+}
+
+/*
+ * sfe_ipv4_free_connection_rcu()
+ *	Called at RCU qs state to free the connection object.
+ */
+static void sfe_ipv4_free_connection_rcu(struct rcu_head *head)
+{
+	struct sfe_ipv4_connection *c;
+	struct udp_sock *up;
+	struct sock *sk;
+
+	/*
+	 * We dont need spin lock as the connection is already removed from link list
+	 */
+	c = container_of(head, struct sfe_ipv4_connection, rcu);
+
+	BUG_ON(!c->removed);
+
+	DEBUG_TRACE("%px: connecton has been deleted\n", c);
+
+	/*
+	 * Decrease the refcount taken in function sfe_ipv4_create_rule(),
+	 * during call of __udp4_lib_lookup()
+	 */
+	up = c->reply_match->up;
+	if (up) {
+		sk = (struct sock *)up;
+		sock_put(sk);
+	}
+
+	/*
+	 * Release our hold of the source and dest devices and free the memory
+	 * for our connection objects.
+	 */
+	dev_put(c->original_dev);
+	dev_put(c->reply_dev);
+	kfree(c->original_match);
+	kfree(c->reply_match);
+	kfree(c);
+}
+
+/*
+ * sfe_ipv4_sync_status()
+ *	update a connection status to its connection manager.
+ *
+ * si: the ipv4 context
+ * c: which connection to be notified
+ * reason: what kind of notification: flush, stats  or destroy
+ */
+void sfe_ipv4_sync_status(struct sfe_ipv4 *si,
+					       struct sfe_ipv4_connection *c,
+					       sfe_sync_reason_t reason)
+{
+	struct sfe_connection_sync sis;
+	u64 now_jiffies;
+	sfe_sync_rule_callback_t sync_rule_callback;
+
+	rcu_read_lock();
+	sync_rule_callback = rcu_dereference(si->sync_rule_callback);
+	if (!sync_rule_callback) {
+		rcu_read_unlock();
+		return;
+	}
+
+	/*
+	 * Generate a sync message and then sync.
+	 */
+	now_jiffies = get_jiffies_64();
+	sfe_ipv4_gen_sync_connection(si, c, &sis, reason, now_jiffies);
+	sync_rule_callback(&sis);
+
+	rcu_read_unlock();
+}
+
+/*
+ * sfe_ipv4_flush_connection()
+ *	Flush a connection and free all associated resources.
+ *
+ * We need to be called with bottom halves disabled locally as we need to acquire
+ * the connection hash lock and release it again.  In general we're actually called
+ * from within a BH and so we're fine, but we're also called when connections are
+ * torn down.
+ */
+void sfe_ipv4_flush_connection(struct sfe_ipv4 *si,
+					       struct sfe_ipv4_connection *c,
+					       sfe_sync_reason_t reason)
+{
+	BUG_ON(!c->removed);
+
+	this_cpu_inc(si->stats_pcpu->connection_flushes64);
+	sfe_ipv4_sync_status(si, c, reason);
+
+	/*
+	 * Release our hold of the source and dest devices and free the memory
+	 * for our connection objects.
+	 */
+	call_rcu(&c->rcu, sfe_ipv4_free_connection_rcu);
+}
+
+/*
+ * sfe_ipv4_exception_stats_inc()
+ *	Increment exception stats.
+ */
+void sfe_ipv4_exception_stats_inc(struct sfe_ipv4 *si, enum sfe_ipv4_exception_events reason)
+{
+       struct sfe_ipv4_stats *stats = this_cpu_ptr(si->stats_pcpu);
+       stats->exception_events64[reason]++;
+       stats->packets_not_forwarded64++;
+}
+
+/*
+ * sfe_ipv4_is_loal_ip()
+ *	Returns true if IP is local; returns false otherwise.
+ */
+static bool sfe_ipv4_is_local_ip(struct sfe_ipv4 *si, __be32 ip_addr)
+{
+	struct net_device *dev;
+
+	dev = ip_dev_find(&init_net, ip_addr);
+	if (dev) {
+		dev_put(dev);
+		return true;
+	}
+
+	return false;
+}
+
+/*
+ * sfe_ipv4_recv()
+ *	Handle packet receives and forwaring.
+ *
+ * Returns 1 if the packet is forwarded or 0 if it isn't.
+ */
+int sfe_ipv4_recv(struct net_device *dev, struct sk_buff *skb, struct sfe_l2_info *l2_info, bool tun_outer)
+{
+	struct sfe_ipv4 *si = &__si;
+	unsigned int len;
+	unsigned int tot_len;
+	unsigned int frag_off;
+	unsigned int ihl;
+	bool sync_on_find;
+	bool ip_options;
+	struct iphdr *iph;
+	u32 protocol;
+
+	/*
+	 * Check that we have space for an IP header here.
+	 */
+	len = skb->len;
+	if (unlikely(!pskb_may_pull(skb, sizeof(struct iphdr)))) {
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_HEADER_INCOMPLETE);
+		DEBUG_TRACE("len: %u is too short\n", len);
+		return 0;
+	}
+
+	/*
+	 * Validate ip csum if necessary. If ip_summed is set to CHECKSUM_UNNECESSARY, it is assumed
+	 * that the L3 checksum is validated by the Rx interface or the tunnel interface that has
+	 * generated the packet.
+	 */
+	iph = (struct iphdr *)skb->data;
+	if (unlikely(skb->ip_summed != CHECKSUM_UNNECESSARY) && (ip_fast_csum((u8 *)iph, iph->ihl))) {
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_HEADER_CSUM_BAD);
+
+		DEBUG_TRACE("Bad IPv4 header csum: 0x%x\n", iph->check);
+		return 0;
+	}
+
+	/*
+	 * Check that our "total length" is large enough for an IP header.
+	 */
+	tot_len = ntohs(iph->tot_len);
+	if (unlikely(tot_len < sizeof(struct iphdr))) {
+
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_BAD_TOTAL_LENGTH);
+		DEBUG_TRACE("tot_len: %u is too short\n", tot_len);
+		return 0;
+	}
+
+	/*
+	 * Is our IP version wrong?
+	 */
+	if (unlikely(iph->version != 4)) {
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_NON_V4);
+		DEBUG_TRACE("IP version: %u\n", iph->version);
+		return 0;
+	}
+
+	/*
+	 * Does our datagram fit inside the skb?
+	 */
+	if (unlikely(tot_len > len)) {
+		DEBUG_TRACE("tot_len: %u, exceeds len: %u\n", tot_len, len);
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_DATAGRAM_INCOMPLETE);
+		return 0;
+	}
+
+	/*
+	 * Do we have a non-initial fragment?
+	 */
+	frag_off = ntohs(iph->frag_off);
+	if (unlikely(frag_off & IP_OFFSET)) {
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_NON_INITIAL_FRAGMENT);
+		DEBUG_TRACE("non-initial fragment\n");
+		return 0;
+	}
+
+	/*
+	 * If we have a (first) fragment then mark it to cause any connection to flush.
+	 */
+	sync_on_find = unlikely(frag_off & IP_MF) ? true : false;
+
+	/*
+	 * Do we have any IP options?  That's definite a slow path!  If we do have IP
+	 * options we need to recheck our header size.
+	 */
+	ihl = iph->ihl << 2;
+	ip_options = unlikely(ihl != sizeof(struct iphdr)) ? true : false;
+	if (unlikely(ip_options)) {
+		if (unlikely(len < ihl)) {
+
+			DEBUG_TRACE("len: %u is too short for header of size: %u\n", len, ihl);
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_IP_OPTIONS_INCOMPLETE);
+			return 0;
+		}
+
+		sync_on_find = true;
+	}
+
+	protocol = iph->protocol;
+	if (IPPROTO_UDP == protocol) {
+		return sfe_ipv4_recv_udp(si, skb, dev, len, iph, ihl, sync_on_find, l2_info, tun_outer);
+	}
+
+	if (IPPROTO_TCP == protocol) {
+		return sfe_ipv4_recv_tcp(si, skb, dev, len, iph, ihl, sync_on_find, l2_info);
+	}
+
+	if (IPPROTO_ICMP == protocol) {
+		return sfe_ipv4_recv_icmp(si, skb, dev, len, iph, ihl);
+	}
+
+#ifdef SFE_GRE_TUN_ENABLE
+	if (IPPROTO_GRE == protocol) {
+		return sfe_ipv4_recv_gre(si, skb, dev, len, iph, ihl, sync_on_find, l2_info, tun_outer);
+	}
+#endif
+
+	sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_UNHANDLED_PROTOCOL);
+
+	DEBUG_TRACE("not UDP, TCP or ICMP: %u\n", protocol);
+	return 0;
+}
+
+static void
+sfe_ipv4_update_tcp_state(struct sfe_ipv4_connection *c,
+			  struct sfe_ipv4_rule_create_msg *msg)
+{
+	struct sfe_ipv4_connection_match *orig_cm;
+	struct sfe_ipv4_connection_match *repl_cm;
+	struct sfe_ipv4_tcp_connection_match *orig_tcp;
+	struct sfe_ipv4_tcp_connection_match *repl_tcp;
+
+	orig_cm = c->original_match;
+	repl_cm = c->reply_match;
+	orig_tcp = &orig_cm->protocol_state.tcp;
+	repl_tcp = &repl_cm->protocol_state.tcp;
+
+	/* update orig */
+	if (orig_tcp->max_win < msg->tcp_rule.flow_max_window) {
+		orig_tcp->max_win = msg->tcp_rule.flow_max_window;
+	}
+	if ((s32)(orig_tcp->end - msg->tcp_rule.flow_end) < 0) {
+		orig_tcp->end = msg->tcp_rule.flow_end;
+	}
+	if ((s32)(orig_tcp->max_end - msg->tcp_rule.flow_max_end) < 0) {
+		orig_tcp->max_end = msg->tcp_rule.flow_max_end;
+	}
+
+	/* update reply */
+	if (repl_tcp->max_win < msg->tcp_rule.return_max_window) {
+		repl_tcp->max_win = msg->tcp_rule.return_max_window;
+	}
+	if ((s32)(repl_tcp->end - msg->tcp_rule.return_end) < 0) {
+		repl_tcp->end = msg->tcp_rule.return_end;
+	}
+	if ((s32)(repl_tcp->max_end - msg->tcp_rule.return_max_end) < 0) {
+		repl_tcp->max_end = msg->tcp_rule.return_max_end;
+	}
+
+	/* update match flags */
+	orig_cm->flags &= ~SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK;
+	repl_cm->flags &= ~SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK;
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_NO_SEQ_CHECK) {
+
+		orig_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK;
+		repl_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK;
+	}
+}
+
+static void
+sfe_ipv4_update_protocol_state(struct sfe_ipv4_connection *c,
+			       struct sfe_ipv4_rule_create_msg *msg)
+{
+	switch (msg->tuple.protocol) {
+	case IPPROTO_TCP:
+		sfe_ipv4_update_tcp_state(c, msg);
+		break;
+	}
+}
+
+/*
+ * sfe_ipv4_match_entry_set_vlan()
+ */
+static void sfe_ipv4_match_entry_set_vlan(
+			struct sfe_ipv4_connection_match *cm,
+			u32 primary_ingress_vlan_tag,
+			u32 primary_egress_vlan_tag,
+			u32 secondary_ingress_vlan_tag,
+			u32 secondary_egress_vlan_tag)
+{
+	u16 tpid;
+	/*
+	 * Prevent stacking header counts when updating.
+	 */
+	cm->ingress_vlan_hdr_cnt = 0;
+	cm->egress_vlan_hdr_cnt = 0;
+	memset(cm->ingress_vlan_hdr, 0, sizeof(cm->ingress_vlan_hdr));
+	memset(cm->egress_vlan_hdr, 0, sizeof(cm->egress_vlan_hdr));
+
+	/*
+	 * vlan_hdr[0] corresponds to outer tag
+	 * vlan_hdr[1] corresponds to inner tag
+	 * Extract the vlan information (tpid and tci) from rule message
+	 */
+	if ((primary_ingress_vlan_tag & VLAN_VID_MASK) != SFE_VLAN_ID_NOT_CONFIGURED) {
+		tpid = (u16)(primary_ingress_vlan_tag >> 16);
+		cm->ingress_vlan_hdr[0].tpid = ntohs(tpid);
+		cm->ingress_vlan_hdr[0].tci = (u16)primary_ingress_vlan_tag;
+		cm->ingress_vlan_hdr_cnt++;
+	}
+
+	if ((secondary_ingress_vlan_tag & VLAN_VID_MASK) != SFE_VLAN_ID_NOT_CONFIGURED) {
+		tpid = (u16)(secondary_ingress_vlan_tag >> 16);
+		cm->ingress_vlan_hdr[1].tpid = ntohs(tpid);
+		cm->ingress_vlan_hdr[1].tci = (u16)secondary_ingress_vlan_tag;
+		cm->ingress_vlan_hdr_cnt++;
+	}
+
+	if ((primary_egress_vlan_tag & VLAN_VID_MASK) != SFE_VLAN_ID_NOT_CONFIGURED) {
+		tpid = (u16)(primary_egress_vlan_tag >> 16);
+		cm->egress_vlan_hdr[0].tpid = ntohs(tpid);
+		cm->egress_vlan_hdr[0].tci = (u16)primary_egress_vlan_tag;
+		cm->egress_vlan_hdr_cnt++;
+	}
+
+	if ((secondary_egress_vlan_tag & VLAN_VID_MASK) != SFE_VLAN_ID_NOT_CONFIGURED) {
+		tpid = (u16)(secondary_egress_vlan_tag >> 16);
+		cm->egress_vlan_hdr[1].tpid = ntohs(tpid);
+		cm->egress_vlan_hdr[1].tci = (u16)secondary_egress_vlan_tag;
+		cm->egress_vlan_hdr_cnt++;
+	}
+}
+
+void sfe_ipv4_update_rule(struct sfe_ipv4_rule_create_msg *msg)
+{
+	struct sfe_ipv4_connection *c;
+	struct sfe_ipv4 *si = &__si;
+
+	spin_lock_bh(&si->lock);
+
+	c = sfe_ipv4_find_connection(si,
+					      msg->tuple.protocol,
+					      msg->tuple.flow_ip,
+					      msg->tuple.flow_ident,
+					      msg->tuple.return_ip,
+					      msg->tuple.return_ident);
+	if (c != NULL) {
+		sfe_ipv4_update_protocol_state(c, msg);
+	}
+
+	spin_unlock_bh(&si->lock);
+}
+
+/*
+ * sfe_ipv4_mark_rule_update()
+ *      Updates the mark values of match entries.
+ */
+void sfe_ipv4_mark_rule_update(struct sfe_connection_mark *mark)
+{
+	struct sfe_ipv4_connection *c;
+	struct sfe_ipv4 *si = &__si;
+
+	spin_lock_bh(&si->lock);
+	c = sfe_ipv4_find_connection(si, mark->protocol,
+				     mark->src_ip[0],
+				     mark->src_port,
+				     mark->dest_ip[0],
+				     mark->dest_port);
+	if (!c) {
+		spin_unlock_bh(&si->lock);
+		DEBUG_WARN("%px: connection not found for mark update\n", mark);
+		return;
+	}
+	c->original_match->mark = mark->mark;
+	c->reply_match->mark = mark->mark;
+	spin_unlock_bh(&si->lock);
+	DEBUG_TRACE("%px: connection mark updated with %d\n", mark, mark->mark);
+}
+EXPORT_SYMBOL(sfe_ipv4_mark_rule_update);
+
+/*
+ * sfe_ipv4_xmit_eth_type_check()
+ *	Checking if MAC header has to be written.
+ */
+static inline bool sfe_ipv4_xmit_eth_type_check(struct net_device *dev, u32 cm_flags)
+{
+	if (!(dev->flags & IFF_NOARP)) {
+		return true;
+	}
+
+	/*
+	 * For PPPoE, since we are now supporting PPPoE encapsulation, we are writing L2 header.
+	 */
+	if (unlikely(cm_flags & SFE_IPV4_CONNECTION_MATCH_FLAG_PPPOE_ENCAP)) {
+		return true;
+	}
+
+	return false;
+}
+
+/*
+ * sfe_ipv4_create_rule()
+ *	Create a forwarding rule.
+ */
+int sfe_ipv4_create_rule(struct sfe_ipv4_rule_create_msg *msg)
+{
+	struct sfe_ipv4 *si = &__si;
+	struct sfe_ipv4_connection *c, *c_old;
+	struct sfe_ipv4_connection_match *original_cm;
+	struct sfe_ipv4_connection_match *reply_cm;
+	struct net_device *dest_dev;
+	struct net_device *src_dev;
+	struct sfe_ipv4_5tuple *tuple = &msg->tuple;
+	s32 flow_interface_num = msg->conn_rule.flow_top_interface_num;
+	s32 return_interface_num = msg->conn_rule.return_top_interface_num;
+	struct net *net;
+	struct sock *sk;
+	unsigned int src_if_idx;
+
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE) {
+		flow_interface_num = msg->conn_rule.flow_interface_num;
+	}
+
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE) {
+		return_interface_num = msg->conn_rule.return_interface_num;
+	}
+
+	src_dev = dev_get_by_index(&init_net, flow_interface_num);
+	if (!src_dev) {
+		DEBUG_WARN("%px: Unable to find src_dev corresponding to %d\n", msg,
+						flow_interface_num);
+		this_cpu_inc(si->stats_pcpu->connection_create_failures64);
+		return -EINVAL;
+	}
+
+	dest_dev = dev_get_by_index(&init_net, return_interface_num);
+	if (!dest_dev) {
+		DEBUG_WARN("%px: Unable to find dest_dev corresponding to %d\n", msg,
+						return_interface_num);
+		this_cpu_inc(si->stats_pcpu->connection_create_failures64);
+		dev_put(src_dev);
+		return -EINVAL;
+	}
+
+	if (unlikely((dest_dev->reg_state != NETREG_REGISTERED) ||
+		     (src_dev->reg_state != NETREG_REGISTERED))) {
+		dev_put(src_dev);
+		dev_put(dest_dev);
+		DEBUG_WARN("%px: src_dev=%s and dest_dev=%s are unregistered\n", msg,
+						src_dev->name, dest_dev->name);
+		this_cpu_inc(si->stats_pcpu->connection_create_failures64);
+		return -EINVAL;
+	}
+
+	/*
+	 * Allocate the various connection tracking objects.
+	 */
+	c = (struct sfe_ipv4_connection *)kzalloc(sizeof(struct sfe_ipv4_connection), GFP_ATOMIC);
+	if (unlikely(!c)) {
+		DEBUG_WARN("%px: memory allocation of connection entry failed\n", msg);
+		this_cpu_inc(si->stats_pcpu->connection_create_failures64);
+		dev_put(src_dev);
+		dev_put(dest_dev);
+		return -ENOMEM;
+	}
+
+	original_cm = (struct sfe_ipv4_connection_match *)kzalloc(sizeof(struct sfe_ipv4_connection_match), GFP_ATOMIC);
+	if (unlikely(!original_cm)) {
+		DEBUG_WARN("%px: memory allocation of connection match entry failed\n", msg);
+		this_cpu_inc(si->stats_pcpu->connection_create_failures64);
+		kfree(c);
+		dev_put(src_dev);
+		dev_put(dest_dev);
+		return -ENOMEM;
+	}
+
+	reply_cm = (struct sfe_ipv4_connection_match *)kzalloc(sizeof(struct sfe_ipv4_connection_match), GFP_ATOMIC);
+	if (unlikely(!reply_cm)) {
+		DEBUG_WARN("%px: memory allocation of connection match entry failed\n", msg);
+		this_cpu_inc(si->stats_pcpu->connection_create_failures64);
+		kfree(original_cm);
+		kfree(c);
+		dev_put(src_dev);
+		dev_put(dest_dev);
+		return -ENOMEM;
+	}
+
+	this_cpu_inc(si->stats_pcpu->connection_create_requests64);
+
+	spin_lock_bh(&si->lock);
+
+	/*
+	 * Check to see if there is already a flow that matches the rule we're
+	 * trying to create.  If there is then we can't create a new one.
+	 */
+	c_old = sfe_ipv4_find_connection(si,
+					msg->tuple.protocol,
+					msg->tuple.flow_ip,
+					msg->tuple.flow_ident,
+					msg->tuple.return_ip,
+					msg->tuple.return_ident);
+
+	if (c_old != NULL) {
+		this_cpu_inc(si->stats_pcpu->connection_create_collisions64);
+
+		/*
+		 * If we already have the flow then it's likely that this
+		 * request to create the connection rule contains more
+		 * up-to-date information. Check and update accordingly.
+		 */
+		sfe_ipv4_update_protocol_state(c, msg);
+		spin_unlock_bh(&si->lock);
+
+		kfree(reply_cm);
+		kfree(original_cm);
+		kfree(c);
+
+		dev_put(src_dev);
+		dev_put(dest_dev);
+
+		DEBUG_TRACE("%px: connection already exists -  p:%d\n"
+			    "  s: %s:%pM:%pI4:%u, d: %s:%pM:%pI4:%u\n",
+			    msg, tuple->protocol,
+			    src_dev->name, msg->conn_rule.flow_mac, &tuple->flow_ip, ntohs(tuple->flow_ident),
+			    dest_dev->name, msg->conn_rule.return_mac, &tuple->return_ip, ntohs(tuple->return_ident));
+
+		return -EADDRINUSE;
+	}
+
+	/*
+	 * Fill in the "original" direction connection matching object.
+	 * Note that the transmit MAC address is "dest_mac_xlate" because
+	 * we always know both ends of a connection by their translated
+	 * addresses and not their public addresses.
+	 */
+	original_cm->match_dev = src_dev;
+	original_cm->match_protocol = tuple->protocol;
+	original_cm->match_src_ip = tuple->flow_ip;
+	original_cm->match_src_port = netif_is_vxlan(src_dev) ? 0 : tuple->flow_ident;
+	original_cm->match_dest_ip = tuple->return_ip;
+	original_cm->match_dest_port = tuple->return_ident;
+
+	original_cm->xlate_src_ip = msg->conn_rule.flow_ip_xlate;
+	original_cm->xlate_src_port = msg->conn_rule.flow_ident_xlate;
+	original_cm->xlate_dest_ip = msg->conn_rule.return_ip_xlate;
+	original_cm->xlate_dest_port = msg->conn_rule.return_ident_xlate;
+
+	if (tuple->protocol == IPPROTO_GRE) {
+		/*
+		 * the PPTP is 4 tuple lookup.
+		 * During th rule lookup destination call id from packet
+		 * is matched against destination port in cm.
+		 */
+		original_cm->match_src_port = 0;
+		original_cm->xlate_src_port = 0;
+	}
+
+	original_cm->xmit_dev = dest_dev;
+	original_cm->xmit_dev_mtu = msg->conn_rule.return_mtu;
+
+	original_cm->connection = c;
+	original_cm->counter_match = reply_cm;
+
+	/*
+	 * UDP Socket is valid only in decap direction.
+	 */
+	RCU_INIT_POINTER(original_cm->up, NULL);
+
+	if (msg->valid_flags & SFE_RULE_CREATE_MARK_VALID) {
+		original_cm->mark = msg->mark_rule.flow_mark;
+		original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_MARK;
+	}
+	if (msg->valid_flags & SFE_RULE_CREATE_QOS_VALID) {
+		original_cm->priority =  msg->qos_rule.flow_qos_tag;
+		original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_PRIORITY_REMARK;
+	}
+	if (msg->valid_flags & SFE_RULE_CREATE_DSCP_MARKING_VALID) {
+		original_cm->dscp = msg->dscp_rule.flow_dscp << SFE_IPV4_DSCP_SHIFT;
+		original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_DSCP_REMARK;
+	}
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_BRIDGE_FLOW) {
+		original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_BRIDGE_FLOW;
+	}
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_FLOW_TRANSMIT_FAST) {
+		original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT_DEV_ADMISSION;
+	}
+
+	/*
+	 * Add VLAN rule to original_cm
+	 */
+	if (msg->valid_flags & SFE_RULE_CREATE_VLAN_VALID) {
+		struct sfe_vlan_rule *vlan_primary_rule = &msg->vlan_primary_rule;
+		struct sfe_vlan_rule *vlan_secondary_rule = &msg->vlan_secondary_rule;
+		sfe_ipv4_match_entry_set_vlan(original_cm,
+					     vlan_primary_rule->ingress_vlan_tag,
+					     vlan_primary_rule->egress_vlan_tag,
+					     vlan_secondary_rule->ingress_vlan_tag,
+					     vlan_secondary_rule->egress_vlan_tag);
+
+		if ((msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE) &&
+			original_cm->egress_vlan_hdr_cnt > 0) {
+			original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_INSERT_EGRESS_VLAN_TAG;
+			original_cm->l2_hdr_size += original_cm->egress_vlan_hdr_cnt * VLAN_HLEN;
+		}
+	}
+
+	if ((IPPROTO_GRE == tuple->protocol) && !sfe_ipv4_is_local_ip(si, original_cm->match_dest_ip)) {
+		original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_PASSTHROUGH;
+	}
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+	original_cm->flow_cookie = 0;
+#endif
+#ifdef CONFIG_XFRM
+	if (msg->valid_flags & SFE_RULE_CREATE_DIRECTION_VALID) {
+		original_cm->flow_accel = msg->direction_rule.flow_accel;
+	} else {
+		original_cm->flow_accel = 1;
+	}
+#endif
+	/*
+	 * If l2_features are disabled and flow uses l2 features such as macvlan/bridge/pppoe/vlan,
+	 * bottom interfaces are expected to be disabled in the flow rule and always top interfaces
+	 * are used. In such cases, do not use HW csum offload. csum offload is used only when we
+	 * are sending directly to the destination interface that supports it.
+	 */
+	if (likely(dest_dev->features & NETIF_F_HW_CSUM) && sfe_dev_has_hw_csum(dest_dev)) {
+		if ((msg->conn_rule.return_top_interface_num == msg->conn_rule.return_interface_num) ||
+			(msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE)) {
+
+			/*
+			 * Dont enable CSUM offload
+			 */
+#if 0
+			original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_CSUM_OFFLOAD;
+#endif
+		}
+	}
+
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_FLOW_SRC_INTERFACE_CHECK) {
+		original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK;
+	}
+
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_FLOW_SRC_INTERFACE_CHECK_NO_FLUSH) {
+		original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK_NO_FLUSH;
+	}
+
+	/*
+	 * Adding PPPoE parameters to original and reply entries based on the direction where
+	 * PPPoE header is valid in ECM rule.
+	 *
+	 * If PPPoE is valid in flow direction (from interface is PPPoE), then
+	 *	original cm will have PPPoE at ingress (strip PPPoE header)
+	 *	reply cm will have PPPoE at egress (add PPPoE header)
+	 *
+	 * If PPPoE is valid in return direction (to interface is PPPoE), then
+	 *	original cm will have PPPoE at egress (add PPPoE header)
+	 *	reply cm will have PPPoE at ingress (strip PPPoE header)
+	 */
+	if (msg->valid_flags & SFE_RULE_CREATE_PPPOE_DECAP_VALID) {
+		original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_PPPOE_DECAP;
+		original_cm->pppoe_session_id = msg->pppoe_rule.flow_pppoe_session_id;
+		ether_addr_copy(original_cm->pppoe_remote_mac, msg->pppoe_rule.flow_pppoe_remote_mac);
+
+		reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_PPPOE_ENCAP;
+		reply_cm->l2_hdr_size += SFE_PPPOE_SESSION_HEADER_SIZE;
+		reply_cm->pppoe_session_id = msg->pppoe_rule.flow_pppoe_session_id;
+		ether_addr_copy(reply_cm->pppoe_remote_mac, msg->pppoe_rule.flow_pppoe_remote_mac);
+	}
+
+	if (msg->valid_flags & SFE_RULE_CREATE_PPPOE_ENCAP_VALID) {
+		original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_PPPOE_ENCAP;
+		original_cm->l2_hdr_size += SFE_PPPOE_SESSION_HEADER_SIZE;
+		original_cm->pppoe_session_id = msg->pppoe_rule.return_pppoe_session_id;
+		ether_addr_copy(original_cm->pppoe_remote_mac, msg->pppoe_rule.return_pppoe_remote_mac);
+
+		reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_PPPOE_DECAP;
+		reply_cm->pppoe_session_id = msg->pppoe_rule.return_pppoe_session_id;
+		ether_addr_copy(reply_cm->pppoe_remote_mac, msg->pppoe_rule.return_pppoe_remote_mac);
+	}
+
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_RETURN_SRC_INTERFACE_CHECK) {
+		reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK;
+	}
+
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_RETURN_SRC_INTERFACE_CHECK_NO_FLUSH) {
+		reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK_NO_FLUSH;
+	}
+
+	/*
+	 * For the non-arp interface, we don't write L2 HDR.
+	 */
+	if (sfe_ipv4_xmit_eth_type_check(dest_dev, original_cm->flags)) {
+
+		/*
+		 * Check whether the rule has configured a specific source MAC address to use.
+		 * This is needed when virtual L3 interfaces such as br-lan, macvlan, vlan are used during egress
+		 */
+
+		if (msg->rule_flags & SFE_RULE_CREATE_FLAG_BRIDGE_FLOW) {
+			ether_addr_copy((u8 *)original_cm->xmit_src_mac, (u8 *)msg->conn_rule.flow_mac);
+		} else {
+			if ((msg->valid_flags & SFE_RULE_CREATE_SRC_MAC_VALID) &&
+			    (msg->src_mac_rule.mac_valid_flags & SFE_SRC_MAC_RETURN_VALID)) {
+				ether_addr_copy((u8 *)original_cm->xmit_src_mac, (u8 *)msg->src_mac_rule.return_src_mac);
+			} else {
+				ether_addr_copy((u8 *)original_cm->xmit_src_mac, (u8 *)dest_dev->dev_addr);
+			}
+		}
+
+		ether_addr_copy((u8 *)original_cm->xmit_dest_mac, (u8 *)msg->conn_rule.return_mac);
+
+		original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_L2_HDR;
+		original_cm->l2_hdr_size += ETH_HLEN;
+
+		/*
+		 * If our dev writes Ethernet headers then we can write a really fast
+		 * version.
+		 */
+		if (dest_dev->header_ops) {
+			if (dest_dev->header_ops->create == eth_header) {
+				original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR;
+			}
+		}
+	}
+
+	/*
+	 * Fill in the "reply" direction connection matching object.
+	 */
+	reply_cm->match_dev = dest_dev;
+	reply_cm->match_protocol = tuple->protocol;
+	reply_cm->match_src_ip = msg->conn_rule.return_ip_xlate;
+
+	/*
+	 * Keep source port as 0 for VxLAN tunnels.
+	 */
+	if (netif_is_vxlan(src_dev) || netif_is_vxlan(dest_dev)) {
+		reply_cm->match_src_port = 0;
+	} else {
+		reply_cm->match_src_port = msg->conn_rule.return_ident_xlate;
+	}
+
+	reply_cm->match_dest_ip = msg->conn_rule.flow_ip_xlate;
+	reply_cm->match_dest_port = msg->conn_rule.flow_ident_xlate;
+
+	reply_cm->xlate_src_ip = tuple->return_ip;
+	reply_cm->xlate_src_port = tuple->return_ident;
+	reply_cm->xlate_dest_ip = tuple->flow_ip;
+	reply_cm->xlate_dest_port = tuple->flow_ident;
+
+	if (tuple->protocol == IPPROTO_GRE) {
+		/*
+		 * the PPTP is 4 tuple lookup.
+		 * During th rule lookup destination call id from packet
+		 * is matched against destination port in cm.
+		 */
+		reply_cm->match_src_port = 0;
+		reply_cm->xlate_src_port = 0;
+	}
+
+	reply_cm->xmit_dev = src_dev;
+	reply_cm->xmit_dev_mtu = msg->conn_rule.flow_mtu;
+
+	reply_cm->connection = c;
+	reply_cm->counter_match = original_cm;
+
+	if (msg->valid_flags & SFE_RULE_CREATE_MARK_VALID) {
+		reply_cm->mark = msg->mark_rule.return_mark;
+		reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_MARK;
+	}
+	if (msg->valid_flags & SFE_RULE_CREATE_QOS_VALID) {
+		reply_cm->priority = msg->qos_rule.return_qos_tag;
+		reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_PRIORITY_REMARK;
+	}
+
+	if (msg->valid_flags & SFE_RULE_CREATE_DSCP_MARKING_VALID) {
+		reply_cm->dscp = msg->dscp_rule.return_dscp << SFE_IPV4_DSCP_SHIFT;
+		reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_DSCP_REMARK;
+	}
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_BRIDGE_FLOW) {
+		reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_BRIDGE_FLOW;
+	}
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_RETURN_TRANSMIT_FAST) {
+		reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT_DEV_ADMISSION;
+	}
+
+	if ((IPPROTO_GRE == tuple->protocol) && !sfe_ipv4_is_local_ip(si, reply_cm->match_dest_ip)) {
+		reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_PASSTHROUGH;
+	}
+
+	/*
+	 * Setup UDP Socket if found to be valid for decap.
+	 */
+	RCU_INIT_POINTER(reply_cm->up, NULL);
+	net = dev_net(reply_cm->match_dev);
+	src_if_idx = src_dev->ifindex;
+
+	rcu_read_lock();
+
+	/*
+	 * Look for the associated sock object.
+	 * __udp4_lib_lookup() holds a reference for this sock object,
+	 * which will be released in sfe_ipv4_free_connection_rcu()
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	sk = __udp4_lib_lookup(net, reply_cm->match_dest_ip, reply_cm->match_dest_port,
+			reply_cm->xlate_src_ip, reply_cm->xlate_src_port, src_if_idx, &udp_table);
+#else
+	sk = __udp4_lib_lookup(net, reply_cm->match_dest_ip, reply_cm->match_dest_port,
+			reply_cm->xlate_src_ip, reply_cm->xlate_src_port, src_if_idx, 0, &udp_table, NULL);
+#endif
+
+	rcu_read_unlock();
+
+	/*
+	 * We set the UDP sock pointer as valid only for decap direction.
+	 */
+	if (sk && udp_sk(sk)->encap_type) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+		if (!atomic_add_unless(&sk->sk_refcnt, 1, 0)) {
+#else
+		if (!refcount_inc_not_zero(&sk->sk_refcnt)) {
+#endif
+			spin_unlock_bh(&si->lock);
+			kfree(reply_cm);
+			kfree(original_cm);
+			kfree(c);
+
+			DEBUG_TRACE("%px: sfe: unable to take reference for socket(%px)  p:%d\n"
+				    "  s: %s:%pM:%pI4:%u, d: %s:%pM:%pI4:%u\n",
+				    msg, sk, tuple->protocol,
+				    src_dev->name, msg->conn_rule.flow_mac, &tuple->flow_ip, ntohs(tuple->flow_ident),
+				    dest_dev->name, msg->conn_rule.return_mac, &tuple->return_ip, ntohs(tuple->return_ident));
+
+			dev_put(src_dev);
+			dev_put(dest_dev);
+
+			return -ESHUTDOWN;
+		}
+
+		rcu_assign_pointer(reply_cm->up, udp_sk(sk));
+
+		DEBUG_INFO("%px: Sock(%px) lookup success with reply_cm direction\n", msg, sk);
+		DEBUG_INFO("%px: SFE connection -\n"
+			   "  s: %s:%pI4(%pI4):%u(%u)\n"
+			   "  d: %s:%pI4(%pI4):%u(%u)\n",
+			msg, reply_cm->match_dev->name, &reply_cm->match_src_ip, &reply_cm->xlate_src_ip,
+			ntohs(reply_cm->match_src_port), ntohs(reply_cm->xlate_src_port),
+			reply_cm->xmit_dev->name, &reply_cm->match_dest_ip, &reply_cm->xlate_dest_ip,
+			ntohs(reply_cm->match_dest_port), ntohs(reply_cm->xlate_dest_port));
+	}
+
+	/*
+	 * Add VLAN rule to reply_cm
+	 */
+	if (msg->valid_flags & SFE_RULE_CREATE_VLAN_VALID) {
+		struct sfe_vlan_rule *vlan_primary_rule = &msg->vlan_primary_rule;
+		struct sfe_vlan_rule *vlan_secondary_rule = &msg->vlan_secondary_rule;
+		sfe_ipv4_match_entry_set_vlan(reply_cm,
+					     vlan_primary_rule->egress_vlan_tag,
+					     vlan_primary_rule->ingress_vlan_tag,
+					     vlan_secondary_rule->egress_vlan_tag,
+					     vlan_secondary_rule->ingress_vlan_tag);
+
+		if ((msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE) &&
+			reply_cm->egress_vlan_hdr_cnt > 0) {
+			reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_INSERT_EGRESS_VLAN_TAG;
+			reply_cm->l2_hdr_size += reply_cm->egress_vlan_hdr_cnt * VLAN_HLEN;
+		}
+	}
+
+	/*
+	 * the net_protocol handler will be used only in decap path
+	 * for non passthrough case.
+	 */
+	original_cm->proto = NULL;
+	reply_cm->proto = NULL;
+
+#ifdef SFE_GRE_TUN_ENABLE
+	if ((IPPROTO_GRE == tuple->protocol) && !(reply_cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_PASSTHROUGH)) {
+		rcu_read_lock();
+		reply_cm->proto = rcu_dereference(inet_protos[IPPROTO_GRE]);
+		rcu_read_unlock();
+
+		if (unlikely(!reply_cm->proto)) {
+			kfree(reply_cm);
+			kfree(original_cm);
+			kfree(c);
+			dev_put(src_dev);
+			dev_put(dest_dev);
+			DEBUG_WARN("sfe: GRE proto handler is not registered\n");
+			return -EPERM;
+		}
+	}
+#endif
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+	reply_cm->flow_cookie = 0;
+#endif
+#ifdef CONFIG_XFRM
+	if (msg->valid_flags & SFE_RULE_CREATE_DIRECTION_VALID) {
+		reply_cm->flow_accel = msg->direction_rule.return_accel;
+	} else {
+		reply_cm->flow_accel = 1;
+	}
+
+#endif
+	/*
+	 * If l2_features are disabled and flow uses l2 features such as macvlan/bridge/pppoe/vlan,
+	 * bottom interfaces are expected to be disabled in the flow rule and always top interfaces
+	 * are used. In such cases, do not use HW csum offload. csum offload is used only when we
+	 * are sending directly to the destination interface that supports it.
+	 */
+	if (likely(src_dev->features & NETIF_F_HW_CSUM) && sfe_dev_has_hw_csum(src_dev)) {
+		if ((msg->conn_rule.flow_top_interface_num == msg->conn_rule.flow_interface_num) ||
+			(msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE)) {
+			/*
+			 * Dont enable CSUM offload
+			 */
+#if 0
+			 reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_CSUM_OFFLOAD;
+#endif
+		}
+	}
+
+	/*
+	 * For the non-arp interface, we don't write L2 HDR.
+	 */
+	if (sfe_ipv4_xmit_eth_type_check(src_dev, reply_cm->flags)) {
+
+		/*
+		 * Check whether the rule has configured a specific source MAC address to use.
+		 * This is needed when virtual L3 interfaces such as br-lan, macvlan, vlan are used during egress
+		 */
+
+		if (msg->rule_flags & SFE_RULE_CREATE_FLAG_BRIDGE_FLOW) {
+			ether_addr_copy((u8 *)reply_cm->xmit_src_mac, (u8 *)msg->conn_rule.return_mac);
+		} else {
+			if ((msg->valid_flags & SFE_RULE_CREATE_SRC_MAC_VALID) &&
+			    (msg->src_mac_rule.mac_valid_flags & SFE_SRC_MAC_FLOW_VALID)) {
+				ether_addr_copy((u8 *)reply_cm->xmit_src_mac, (u8 *)msg->src_mac_rule.flow_src_mac);
+			} else {
+				ether_addr_copy((u8 *)reply_cm->xmit_src_mac, (u8 *)src_dev->dev_addr);
+			}
+		}
+
+		ether_addr_copy((u8 *)reply_cm->xmit_dest_mac, (u8 *)msg->conn_rule.flow_mac);
+
+		reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_L2_HDR;
+		reply_cm->l2_hdr_size += ETH_HLEN;
+
+		/*
+		 * If our dev writes Ethernet headers then we can write a really fast
+		 * version.
+		 */
+		if (src_dev->header_ops) {
+			if (src_dev->header_ops->create == eth_header) {
+				reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR;
+			}
+		}
+	}
+
+	if ((tuple->return_ip != msg->conn_rule.return_ip_xlate) ||
+				(tuple->return_ident != msg->conn_rule.return_ident_xlate)) {
+		original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_DEST;
+		reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_SRC;
+	}
+
+	if ((tuple->flow_ip != msg->conn_rule.flow_ip_xlate) ||
+				(tuple->flow_ident != msg->conn_rule.flow_ident_xlate)) {
+		original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_SRC;
+		reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_DEST;
+	}
+
+	/*
+	 * Initialize the protocol-specific information that we track.
+	 */
+	switch (tuple->protocol) {
+	case IPPROTO_TCP:
+		original_cm->protocol_state.tcp.win_scale = msg->tcp_rule.flow_window_scale;
+		original_cm->protocol_state.tcp.max_win = msg->tcp_rule.flow_max_window ? msg->tcp_rule.flow_max_window : 1;
+		original_cm->protocol_state.tcp.end = msg->tcp_rule.flow_end;
+		original_cm->protocol_state.tcp.max_end = msg->tcp_rule.flow_max_end;
+
+		reply_cm->protocol_state.tcp.win_scale = msg->tcp_rule.return_window_scale;
+		reply_cm->protocol_state.tcp.max_win = msg->tcp_rule.return_max_window ? msg->tcp_rule.return_max_window : 1;
+		reply_cm->protocol_state.tcp.end = msg->tcp_rule.return_end;
+		reply_cm->protocol_state.tcp.max_end = msg->tcp_rule.return_max_end;
+
+		if (msg->rule_flags & SFE_RULE_CREATE_FLAG_NO_SEQ_CHECK) {
+			original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK;
+			reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK;
+		}
+		break;
+	}
+
+	/*
+	 * Fill in the ipv4_connection object.
+	 */
+	c->protocol = tuple->protocol;
+	c->src_ip = tuple->flow_ip;
+	c->src_ip_xlate =  msg->conn_rule.flow_ip_xlate;
+	c->src_port = tuple->flow_ident;
+	c->src_port_xlate = msg->conn_rule.flow_ident_xlate;
+	c->original_dev = src_dev;
+	c->original_match = original_cm;
+	c->dest_ip = tuple->return_ip;
+	c->dest_ip_xlate = msg->conn_rule.return_ip_xlate;
+	c->dest_port = tuple->return_ident;
+	c->dest_port_xlate = msg->conn_rule.return_ident_xlate;
+	c->reply_dev = dest_dev;
+	c->reply_match = reply_cm;
+	c->debug_read_seq = 0;
+	c->last_sync_jiffies = get_jiffies_64();
+	c->removed = false;
+
+	sfe_ipv4_connection_match_compute_translations(original_cm);
+	sfe_ipv4_connection_match_compute_translations(reply_cm);
+	sfe_ipv4_insert_connection(si, c);
+
+	spin_unlock_bh(&si->lock);
+
+	/*
+	 * We have everything we need!
+	 */
+	DEBUG_INFO("NEW connection - p: %d\n"
+		   "original_cm: match_dev=src_dev: %s %d %pM\n"
+		   " xmit_dev=dest_dev: %s %d %pM\n"
+		   " xmit_src_mac: %pM\n"
+		   " xmit_dest_mac: %pM\n"
+		   " flags: %x l2_hdr: %u\n"
+		   "flow_ip: %pI4:%u\n"
+		   "flow_ip_xlate: %pI4:%u\n"
+		   "flow_mac: %pM\n"
+		   "reply_cm: match_dev=dest_dev: %s %d %pM\n"
+		   " xmit_dev=src_dev: %s %d %pM\n"
+		   " xmit_src_mac: %pM\n"
+		   " xmit_dest_mac: %pM\n"
+		   " flags: %x l2_hdr: %u\n"
+		   "return_ip: %pI4:%u\n"
+		   "return_ip_xlate: %pI4:%u\n"
+		   "return_mac: %pM\n"
+		   "flags: valid=%x src_mac_valid=%x\n",
+		   tuple->protocol,
+		   original_cm->match_dev->name, original_cm->match_dev->ifindex, original_cm->match_dev->dev_addr,
+		   original_cm->xmit_dev->name, original_cm->xmit_dev->ifindex, original_cm->xmit_dev->dev_addr,
+		   original_cm->xmit_src_mac, original_cm->xmit_dest_mac, original_cm->flags, original_cm->l2_hdr_size,
+		   &tuple->flow_ip, ntohs(tuple->flow_ident),
+		   &msg->conn_rule.flow_ip_xlate, ntohs(msg->conn_rule.flow_ident_xlate),
+		   msg->conn_rule.flow_mac,
+		   reply_cm->match_dev->name, reply_cm->match_dev->ifindex, reply_cm->match_dev->dev_addr,
+		   reply_cm->xmit_dev->name, reply_cm->xmit_dev->ifindex, reply_cm->xmit_dev->dev_addr,
+		   reply_cm->xmit_src_mac, reply_cm->xmit_dest_mac, reply_cm->flags, reply_cm->l2_hdr_size,
+		   &tuple->return_ip, ntohs(tuple->return_ident),
+		   &msg->conn_rule.return_ip_xlate, ntohs(msg->conn_rule.return_ident_xlate),
+		   msg->conn_rule.return_mac,
+		   msg->valid_flags, msg->src_mac_rule.mac_valid_flags);
+
+	return 0;
+}
+
+/*
+ * sfe_ipv4_destroy_rule()
+ *	Destroy a forwarding rule.
+ */
+void sfe_ipv4_destroy_rule(struct sfe_ipv4_rule_destroy_msg *msg)
+{
+	struct sfe_ipv4 *si = &__si;
+	struct sfe_ipv4_connection *c;
+	bool ret;
+	struct sfe_ipv4_5tuple *tuple = &msg->tuple;
+
+	this_cpu_inc(si->stats_pcpu->connection_destroy_requests64);
+	spin_lock_bh(&si->lock);
+
+	/*
+	 * Check to see if we have a flow that matches the rule we're trying
+	 * to destroy.  If there isn't then we can't destroy it.
+	 */
+	c = sfe_ipv4_find_connection(si, tuple->protocol, tuple->flow_ip, tuple->flow_ident,
+					      tuple->return_ip, tuple->return_ident);
+	if (!c) {
+		spin_unlock_bh(&si->lock);
+		this_cpu_inc(si->stats_pcpu->connection_destroy_misses64);
+
+		DEBUG_TRACE("connection does not exist - p: %d, s: %pI4:%u, d: %pI4:%u\n",
+			    tuple->protocol, &tuple->flow_ip, ntohs(tuple->flow_ident),
+			    &tuple->return_ip, ntohs(tuple->return_ident));
+		return;
+	}
+
+	/*
+	 * Remove our connection details from the hash tables.
+	 */
+	ret = sfe_ipv4_remove_connection(si, c);
+	spin_unlock_bh(&si->lock);
+
+	if (ret) {
+		sfe_ipv4_flush_connection(si, c, SFE_SYNC_REASON_DESTROY);
+	}
+
+	DEBUG_INFO("connection destroyed - p: %d, s: %pI4:%u, d: %pI4:%u\n",
+		   tuple->protocol, &tuple->flow_ip, ntohs(tuple->flow_ident),
+		   &tuple->return_ip, ntohs(tuple->return_ident));
+}
+
+/*
+ * sfe_ipv4_register_sync_rule_callback()
+ *	Register a callback for rule synchronization.
+ */
+void sfe_ipv4_register_sync_rule_callback(sfe_sync_rule_callback_t sync_rule_callback)
+{
+	struct sfe_ipv4 *si = &__si;
+
+	spin_lock_bh(&si->lock);
+	rcu_assign_pointer(si->sync_rule_callback, sync_rule_callback);
+	spin_unlock_bh(&si->lock);
+}
+
+/*
+ * sfe_ipv4_get_debug_dev()
+ */
+static ssize_t sfe_ipv4_get_debug_dev(struct device *dev,
+				      struct device_attribute *attr,
+				      char *buf)
+{
+	struct sfe_ipv4 *si = &__si;
+	ssize_t count;
+	int num;
+
+	spin_lock_bh(&si->lock);
+	num = si->debug_dev;
+	spin_unlock_bh(&si->lock);
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%d\n", num);
+	return count;
+}
+
+/*
+ * sysfs attributes.
+ */
+static const struct device_attribute sfe_ipv4_debug_dev_attr =
+	__ATTR(debug_dev, S_IWUSR | S_IRUGO, sfe_ipv4_get_debug_dev, NULL);
+
+/*
+ * sfe_ipv4_destroy_all_rules_for_dev()
+ *	Destroy all connections that match a particular device.
+ *
+ * If we pass dev as NULL then this destroys all connections.
+ */
+void sfe_ipv4_destroy_all_rules_for_dev(struct net_device *dev)
+{
+	struct sfe_ipv4 *si = &__si;
+	struct sfe_ipv4_connection *c;
+	bool ret;
+
+another_round:
+	spin_lock_bh(&si->lock);
+
+	for (c = si->all_connections_head; c; c = c->all_connections_next) {
+		/*
+		 * Does this connection relate to the device we are destroying?
+		 */
+		if (!dev
+		    || (dev == c->original_dev)
+		    || (dev == c->reply_dev)) {
+			break;
+		}
+	}
+
+	if (c) {
+		ret = sfe_ipv4_remove_connection(si, c);
+	}
+
+	spin_unlock_bh(&si->lock);
+
+	if (c) {
+		if (ret) {
+			sfe_ipv4_flush_connection(si, c, SFE_SYNC_REASON_DESTROY);
+		}
+		goto another_round;
+	}
+}
+
+/*
+ * sfe_ipv4_periodic_sync()
+ */
+static void sfe_ipv4_periodic_sync(struct work_struct *work)
+{
+	struct sfe_ipv4 *si = container_of((struct delayed_work *)work, struct sfe_ipv4, sync_dwork);
+	u64 now_jiffies;
+	int quota;
+	sfe_sync_rule_callback_t sync_rule_callback;
+	struct sfe_ipv4_connection *c;
+
+	now_jiffies = get_jiffies_64();
+
+	rcu_read_lock();
+	sync_rule_callback = rcu_dereference(si->sync_rule_callback);
+	if (!sync_rule_callback) {
+		rcu_read_unlock();
+		goto done;
+	}
+
+	spin_lock_bh(&si->lock);
+
+	/*
+	 * If we have reached the end of the connection list, walk from
+	 * the connection head.
+	 */
+	c = si->wc_next;
+	if (unlikely(!c)) {
+		c = si->all_connections_head;
+	}
+
+	/*
+	 * Get an estimate of the number of connections to parse in this sync.
+	 */
+	quota = (si->num_connections + 63) / 64;
+
+	/*
+	 * Walk the "all connection" list and sync the connection state.
+	 */
+	while (likely(c && quota)) {
+		struct sfe_ipv4_connection_match *cm;
+		struct sfe_ipv4_connection_match *counter_cm;
+		struct sfe_connection_sync sis;
+
+		cm = c->original_match;
+		counter_cm = c->reply_match;
+
+		/*
+		 * Didn't receive packets in the original direction or reply
+		 * direction, move to the next connection.
+		 */
+		if ((!atomic_read(&cm->rx_packet_count)) && !(atomic_read(&counter_cm->rx_packet_count))) {
+			c = c->all_connections_next;
+			continue;
+		}
+
+		quota--;
+
+		sfe_ipv4_gen_sync_connection(si, c, &sis, SFE_SYNC_REASON_STATS, now_jiffies);
+
+		si->wc_next = c->all_connections_next;
+
+		/*
+		 * We don't want to be holding the lock when we sync!
+		 */
+		spin_unlock_bh(&si->lock);
+		sync_rule_callback(&sis);
+		spin_lock_bh(&si->lock);
+
+		/*
+		 * c must be set and used in the same lock/unlock window;
+		 * because c could be removed when we don't hold the lock,
+		 * so delay grabbing until after the callback and relock.
+		 */
+		c = si->wc_next;
+	}
+
+	/*
+	 * At the end of the sync, put the wc_next to the connection we left.
+	 */
+	si->wc_next = c;
+
+	spin_unlock_bh(&si->lock);
+	rcu_read_unlock();
+
+done:
+	schedule_delayed_work_on(si->work_cpu, (struct delayed_work *)work, ((HZ + 99) / 100));
+}
+
+#define CHAR_DEV_MSG_SIZE 768
+
+/*
+ * sfe_ipv4_debug_dev_read_start()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv4_debug_dev_read_start(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length,
+					  int *total_read, struct sfe_ipv4_debug_xml_write_state *ws)
+{
+	int bytes_read;
+
+	si->debug_read_seq++;
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "<sfe_ipv4>\n");
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	ws->state++;
+	return true;
+}
+
+/*
+ * sfe_ipv4_debug_dev_read_connections_start()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv4_debug_dev_read_connections_start(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length,
+						      int *total_read, struct sfe_ipv4_debug_xml_write_state *ws)
+{
+	int bytes_read;
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t<connections>\n");
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	ws->state++;
+	return true;
+}
+
+/*
+ * sfe_ipv4_debug_dev_read_connections_connection()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv4_debug_dev_read_connections_connection(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length,
+							   int *total_read, struct sfe_ipv4_debug_xml_write_state *ws)
+{
+	struct sfe_ipv4_connection *c;
+	struct sfe_ipv4_connection_match *original_cm;
+	struct sfe_ipv4_connection_match *reply_cm;
+	int bytes_read;
+	int protocol;
+	struct net_device *src_dev;
+	__be32 src_ip;
+	__be32 src_ip_xlate;
+	__be16 src_port;
+	__be16 src_port_xlate;
+	u64 src_rx_packets;
+	u64 src_rx_bytes;
+	struct net_device *dest_dev;
+	__be32 dest_ip;
+	__be32 dest_ip_xlate;
+	__be16 dest_port;
+	__be16 dest_port_xlate;
+	u64 dest_rx_packets;
+	u64 dest_rx_bytes;
+	u64 last_sync_jiffies;
+	u32 src_mark, dest_mark, src_priority, dest_priority, src_dscp, dest_dscp;
+	u32 packet, byte, original_cm_flags;
+	u16 pppoe_session_id;
+	u8 pppoe_remote_mac[ETH_ALEN];
+	u32 original_fast_xmit, reply_fast_xmit;
+#ifdef CONFIG_NF_FLOW_COOKIE
+	int src_flow_cookie, dst_flow_cookie;
+#endif
+
+	spin_lock_bh(&si->lock);
+
+	for (c = si->all_connections_head; c; c = c->all_connections_next) {
+		if (c->debug_read_seq < si->debug_read_seq) {
+			c->debug_read_seq = si->debug_read_seq;
+			break;
+		}
+	}
+
+	/*
+	 * If there were no connections then move to the next state.
+	 */
+	if (!c || c->removed) {
+		spin_unlock_bh(&si->lock);
+		ws->state++;
+		return true;
+	}
+
+	original_cm = c->original_match;
+	reply_cm = c->reply_match;
+
+	protocol = c->protocol;
+	src_dev = c->original_dev;
+	src_ip = c->src_ip;
+	src_ip_xlate = c->src_ip_xlate;
+	src_port = c->src_port;
+	src_port_xlate = c->src_port_xlate;
+	src_priority = original_cm->priority;
+	src_dscp = original_cm->dscp >> SFE_IPV4_DSCP_SHIFT;
+
+	sfe_ipv4_connection_match_update_summary_stats(original_cm, &packet, &byte);
+	sfe_ipv4_connection_match_update_summary_stats(reply_cm, &packet, &byte);
+
+	src_rx_packets = original_cm->rx_packet_count64;
+	src_rx_bytes = original_cm->rx_byte_count64;
+	src_mark = original_cm->mark;
+	original_fast_xmit = (original_cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT);
+	dest_dev = c->reply_dev;
+	dest_ip = c->dest_ip;
+	dest_ip_xlate = c->dest_ip_xlate;
+	dest_port = c->dest_port;
+	dest_port_xlate = c->dest_port_xlate;
+	dest_priority = reply_cm->priority;
+	dest_dscp = reply_cm->dscp >> SFE_IPV4_DSCP_SHIFT;
+	dest_rx_packets = reply_cm->rx_packet_count64;
+	dest_rx_bytes = reply_cm->rx_byte_count64;
+	dest_mark = reply_cm->mark;
+	reply_fast_xmit = (reply_cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT);
+	last_sync_jiffies = get_jiffies_64() - c->last_sync_jiffies;
+	original_cm_flags = original_cm->flags;
+	pppoe_session_id = original_cm->pppoe_session_id;
+	ether_addr_copy(pppoe_remote_mac, original_cm->pppoe_remote_mac);
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+	src_flow_cookie = original_cm->flow_cookie;
+	dst_flow_cookie = reply_cm->flow_cookie;
+#endif
+	spin_unlock_bh(&si->lock);
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t\t<connection "
+				"protocol=\"%u\" "
+				"src_dev=\"%s\" "
+				"src_ip=\"%pI4\" src_ip_xlate=\"%pI4\" "
+				"src_port=\"%u\" src_port_xlate=\"%u\" "
+				"src_priority=\"%u\" src_dscp=\"%u\" "
+				"src_rx_pkts=\"%llu\" src_rx_bytes=\"%llu\" "
+				"src_mark=\"%08x\" "
+				"src_fast_xmit=\"%s\" "
+				"dest_dev=\"%s\" "
+				"dest_ip=\"%pI4\" dest_ip_xlate=\"%pI4\" "
+				"dest_port=\"%u\" dest_port_xlate=\"%u\" "
+				"dest_priority=\"%u\" dest_dscp=\"%u\" "
+				"dest_rx_pkts=\"%llu\" dest_rx_bytes=\"%llu\" "
+				"dest_mark=\"%08x\" "
+				"reply_fast_xmit=\"%s\" "
+#ifdef CONFIG_NF_FLOW_COOKIE
+				"src_flow_cookie=\"%d\" dst_flow_cookie=\"%d\" "
+#endif
+				"last_sync=\"%llu\" ",
+				protocol,
+				src_dev->name,
+				&src_ip, &src_ip_xlate,
+				ntohs(src_port), ntohs(src_port_xlate),
+				src_priority, src_dscp,
+				src_rx_packets, src_rx_bytes,
+				src_mark,
+				original_fast_xmit ? "Yes" : "No",
+				dest_dev->name,
+				&dest_ip, &dest_ip_xlate,
+				ntohs(dest_port), ntohs(dest_port_xlate),
+				dest_priority, dest_dscp,
+				dest_rx_packets, dest_rx_bytes,
+				dest_mark,
+				reply_fast_xmit ? "Yes" : "No",
+#ifdef CONFIG_NF_FLOW_COOKIE
+				src_flow_cookie, dst_flow_cookie,
+#endif
+				last_sync_jiffies);
+
+	if (original_cm_flags &= (SFE_IPV4_CONNECTION_MATCH_FLAG_PPPOE_DECAP | SFE_IPV4_CONNECTION_MATCH_FLAG_PPPOE_ENCAP)) {
+		bytes_read += snprintf(msg + bytes_read, CHAR_DEV_MSG_SIZE, "pppoe_session_id=\"%u\" pppoe_server MAC=\"%pM\" ",
+				pppoe_session_id, pppoe_remote_mac);
+	}
+
+	bytes_read += snprintf(msg + bytes_read, CHAR_DEV_MSG_SIZE, "/>\n");
+
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	return true;
+}
+
+/*
+ * sfe_ipv4_debug_dev_read_connections_end()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv4_debug_dev_read_connections_end(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length,
+						    int *total_read, struct sfe_ipv4_debug_xml_write_state *ws)
+{
+	int bytes_read;
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t</connections>\n");
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	ws->state++;
+	return true;
+}
+
+/*
+ * sfe_ipv4_debug_dev_read_exceptions_start()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv4_debug_dev_read_exceptions_start(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length,
+						     int *total_read, struct sfe_ipv4_debug_xml_write_state *ws)
+{
+	int bytes_read;
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t<exceptions>\n");
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	ws->state++;
+	return true;
+}
+
+/*
+ * sfe_ipv4_debug_dev_read_exceptions_exception()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv4_debug_dev_read_exceptions_exception(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length,
+							 int *total_read, struct sfe_ipv4_debug_xml_write_state *ws)
+{
+	int i;
+	u64 val = 0;
+
+	for_each_possible_cpu(i) {
+		const struct sfe_ipv4_stats *s = per_cpu_ptr(si->stats_pcpu, i);
+		val += s->exception_events64[ws->iter_exception];
+	}
+
+	if (val) {
+		int bytes_read;
+
+		bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE,
+				      "\t\t<exception name=\"%s\" count=\"%llu\" />\n",
+				      sfe_ipv4_exception_events_string[ws->iter_exception],
+				      val);
+		if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+			return false;
+		}
+
+		*length -= bytes_read;
+		*total_read += bytes_read;
+	}
+
+	ws->iter_exception++;
+	if (ws->iter_exception >= SFE_IPV4_EXCEPTION_EVENT_LAST) {
+		ws->iter_exception = 0;
+		ws->state++;
+	}
+
+	return true;
+}
+
+/*
+ * sfe_ipv4_debug_dev_read_exceptions_end()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv4_debug_dev_read_exceptions_end(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length,
+						   int *total_read, struct sfe_ipv4_debug_xml_write_state *ws)
+{
+	int bytes_read;
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t</exceptions>\n");
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	ws->state++;
+	return true;
+}
+
+/*
+ * sfe_ipv4_debug_dev_read_stats()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv4_debug_dev_read_stats(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length,
+					  int *total_read, struct sfe_ipv4_debug_xml_write_state *ws)
+{
+	int bytes_read;
+	struct sfe_ipv4_stats stats;
+	unsigned int num_conn;
+
+	sfe_ipv4_update_summary_stats(si, &stats);
+
+	spin_lock_bh(&si->lock);
+	num_conn = si->num_connections;
+	spin_unlock_bh(&si->lock);
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t<stats "
+			      "num_connections=\"%u\" "
+			      "pkts_dropped=\"%llu\" "
+			      "pkts_fast_xmited=\"%llu\" "
+			      "pkts_forwarded=\"%llu\" pkts_not_forwarded=\"%llu\" "
+			      "create_requests=\"%llu\" create_collisions=\"%llu\" "
+			      "create_failures=\"%llu\" "
+			      "destroy_requests=\"%llu\" destroy_misses=\"%llu\" "
+			      "flushes=\"%llu\" "
+			      "hash_hits=\"%llu\" hash_reorders=\"%llu\" "
+			      "pppoe_encap_pkts_fwded=\"%llu\" "
+			      "pppoe_decap_pkts_fwded=\"%llu\" "
+			      "pppoe_bridge_pkts_fwded=\"%llu\" />\n",
+				num_conn,
+				stats.packets_dropped64,
+				stats.packets_fast_xmited64,
+				stats.packets_forwarded64,
+				stats.packets_not_forwarded64,
+				stats.connection_create_requests64,
+				stats.connection_create_collisions64,
+				stats.connection_create_failures64,
+				stats.connection_destroy_requests64,
+				stats.connection_destroy_misses64,
+				stats.connection_flushes64,
+				stats.connection_match_hash_hits64,
+				stats.connection_match_hash_reorders64,
+				stats.pppoe_encap_packets_forwarded64,
+				stats.pppoe_decap_packets_forwarded64,
+				stats.pppoe_bridge_packets_forwarded64);
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	ws->state++;
+	return true;
+}
+
+/*
+ * sfe_ipv4_debug_dev_read_end()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv4_debug_dev_read_end(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length,
+					int *total_read, struct sfe_ipv4_debug_xml_write_state *ws)
+{
+	int bytes_read;
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "</sfe_ipv4>\n");
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	ws->state++;
+	return true;
+}
+
+/*
+ * Array of write functions that write various XML elements that correspond to
+ * our XML output state machine.
+ */
+static sfe_ipv4_debug_xml_write_method_t sfe_ipv4_debug_xml_write_methods[SFE_IPV4_DEBUG_XML_STATE_DONE] = {
+	sfe_ipv4_debug_dev_read_start,
+	sfe_ipv4_debug_dev_read_connections_start,
+	sfe_ipv4_debug_dev_read_connections_connection,
+	sfe_ipv4_debug_dev_read_connections_end,
+	sfe_ipv4_debug_dev_read_exceptions_start,
+	sfe_ipv4_debug_dev_read_exceptions_exception,
+	sfe_ipv4_debug_dev_read_exceptions_end,
+	sfe_ipv4_debug_dev_read_stats,
+	sfe_ipv4_debug_dev_read_end,
+};
+
+/*
+ * sfe_ipv4_debug_dev_read()
+ *	Send info to userspace upon read request from user
+ */
+static ssize_t sfe_ipv4_debug_dev_read(struct file *filp, char *buffer, size_t length, loff_t *offset)
+{
+	char msg[CHAR_DEV_MSG_SIZE];
+	int total_read = 0;
+	struct sfe_ipv4_debug_xml_write_state *ws;
+	struct sfe_ipv4 *si = &__si;
+
+	ws = (struct sfe_ipv4_debug_xml_write_state *)filp->private_data;
+	while ((ws->state != SFE_IPV4_DEBUG_XML_STATE_DONE) && (length > CHAR_DEV_MSG_SIZE)) {
+		if ((sfe_ipv4_debug_xml_write_methods[ws->state])(si, buffer, msg, &length, &total_read, ws)) {
+			continue;
+		}
+	}
+
+	return total_read;
+}
+
+/*
+ * sfe_ipv4_debug_dev_open()
+ */
+static int sfe_ipv4_debug_dev_open(struct inode *inode, struct file *file)
+{
+	struct sfe_ipv4_debug_xml_write_state *ws;
+
+	ws = (struct sfe_ipv4_debug_xml_write_state *)file->private_data;
+	if (!ws) {
+		ws = kzalloc(sizeof(struct sfe_ipv4_debug_xml_write_state), GFP_KERNEL);
+		if (!ws) {
+			return -ENOMEM;
+		}
+
+		ws->state = SFE_IPV4_DEBUG_XML_STATE_START;
+		file->private_data = ws;
+	}
+
+	return 0;
+}
+
+/*
+ * sfe_ipv4_debug_dev_release()
+ */
+static int sfe_ipv4_debug_dev_release(struct inode *inode, struct file *file)
+{
+	struct sfe_ipv4_debug_xml_write_state *ws;
+
+	ws = (struct sfe_ipv4_debug_xml_write_state *)file->private_data;
+	if (ws) {
+		/*
+		 * We've finished with our output so free the write state.
+		 */
+		kfree(ws);
+		file->private_data = NULL;
+	}
+
+	return 0;
+}
+
+/*
+ * File operations used in the debug char device
+ */
+static struct file_operations sfe_ipv4_debug_dev_fops = {
+	.read = sfe_ipv4_debug_dev_read,
+	.open = sfe_ipv4_debug_dev_open,
+	.release = sfe_ipv4_debug_dev_release
+};
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+/*
+ * sfe_register_flow_cookie_cb
+ *	register a function in SFE to let SFE use this function to configure flow cookie for a flow
+ *
+ * Hardware driver which support flow cookie should register a callback function in SFE. Then SFE
+ * can use this function to configure flow cookie for a flow.
+ * return: 0, success; !=0, fail
+ */
+int sfe_register_flow_cookie_cb(flow_cookie_set_func_t cb)
+{
+	struct sfe_ipv4 *si = &__si;
+
+	BUG_ON(!cb);
+
+	if (si->flow_cookie_set_func) {
+		return -1;
+	}
+
+	rcu_assign_pointer(si->flow_cookie_set_func, cb);
+	return 0;
+}
+
+/*
+ * sfe_unregister_flow_cookie_cb
+ *	unregister function which is used to configure flow cookie for a flow
+ *
+ * return: 0, success; !=0, fail
+ */
+int sfe_unregister_flow_cookie_cb(flow_cookie_set_func_t cb)
+{
+	struct sfe_ipv4 *si = &__si;
+
+	RCU_INIT_POINTER(si->flow_cookie_set_func, NULL);
+	return 0;
+}
+
+/*
+ * sfe_ipv4_get_flow_cookie()
+ */
+static ssize_t sfe_ipv4_get_flow_cookie(struct device *dev,
+					struct device_attribute *attr,
+					char *buf)
+{
+	struct sfe_ipv4 *si = &__si;
+	return snprintf(buf, (ssize_t)PAGE_SIZE, "%d\n", si->flow_cookie_enable);
+}
+
+/*
+ * sfe_ipv4_set_flow_cookie()
+ */
+static ssize_t sfe_ipv4_set_flow_cookie(struct device *dev,
+					struct device_attribute *attr,
+					const char *buf, size_t size)
+{
+	struct sfe_ipv4 *si = &__si;
+	si->flow_cookie_enable = simple_strtol(buf, NULL, 0);
+
+	return size;
+}
+
+/*
+ * sysfs attributes.
+ */
+static const struct device_attribute sfe_ipv4_flow_cookie_attr =
+	__ATTR(flow_cookie_enable, S_IWUSR | S_IRUGO, sfe_ipv4_get_flow_cookie, sfe_ipv4_set_flow_cookie);
+#endif /*CONFIG_NF_FLOW_COOKIE*/
+
+/*
+ * sfe_ipv4_get_cpu()
+ */
+static ssize_t sfe_ipv4_get_cpu(struct device *dev,
+					struct device_attribute *attr,
+					char *buf)
+{
+	struct sfe_ipv4 *si = &__si;
+	return snprintf(buf, (ssize_t)PAGE_SIZE, "%d\n", si->work_cpu);
+}
+
+/*
+ * sfe_ipv4_set_cpu()
+ */
+static ssize_t sfe_ipv4_set_cpu(struct device *dev,
+					struct device_attribute *attr,
+					const char *buf, size_t size)
+{
+	struct sfe_ipv4 *si = &__si;
+	int work_cpu;
+	work_cpu = simple_strtol(buf, NULL, 0);
+	if ((work_cpu >= 0) && (work_cpu <= NR_CPUS)) {
+		si->work_cpu = work_cpu;
+	} else {
+		dev_err(dev, "%s is not in valid range[0,%d]", buf, NR_CPUS);
+	}
+	return size;
+}
+
+/*
+ * sysfs attributes.
+ */
+static const struct device_attribute sfe_ipv4_cpu_attr =
+	__ATTR(stats_work_cpu, S_IWUSR | S_IRUGO, sfe_ipv4_get_cpu, sfe_ipv4_set_cpu);
+
+/*
+ * DSCP rewrite table
+ */
+static ssize_t
+sfe_ipv4_get_dscp_rewrite_mark_to_match(struct device *dev,
+					struct device_attribute *attr,
+					char *buf)
+{
+	struct sfe_ipv4 *si = &__si;
+	return snprintf(buf, (ssize_t)PAGE_SIZE, "0x%x\n",
+			si->dscp_rewrite_mark_to_match);
+}
+
+static ssize_t
+sfe_ipv4_set_dscp_rewrite_mark_to_match(struct device *dev,
+					struct device_attribute *attr,
+					const char *buf, size_t size)
+{
+	struct sfe_ipv4 *si = &__si;
+	int ret;
+	u32 mark_to_match;
+
+	ret = kstrtou32(buf, 0, &mark_to_match);
+	if (ret)
+		return ret;
+	si->dscp_rewrite_mark_to_match = mark_to_match;
+	return size;
+}
+
+static const struct device_attribute sfe_ipv4_dscp_rewrite_mark_to_match_attr =
+	__ATTR(dscp_rewrite_mark_to_match, S_IWUSR | S_IRUGO,
+	       sfe_ipv4_get_dscp_rewrite_mark_to_match,
+	       sfe_ipv4_set_dscp_rewrite_mark_to_match);
+
+static ssize_t
+sfe_ipv4_get_dscp_rewrite_dscp_to_set(struct device *dev,
+				      struct device_attribute *attr,
+				      char *buf)
+{
+	struct sfe_ipv4 *si = &__si;
+	return snprintf(buf, (ssize_t)PAGE_SIZE, "0x%x\n",
+			si->dscp_rewrite_dscp_to_set >> SFE_IPV4_DSCP_SHIFT);
+}
+
+static ssize_t
+sfe_ipv4_set_dscp_rewrite_dscp_to_set(struct device *dev,
+				      struct device_attribute *attr,
+				      const char *buf, size_t size)
+{
+	struct sfe_ipv4 *si = &__si;
+	int ret;
+	u32 dscp_to_set;
+
+	ret = kstrtou32(buf, 0, &dscp_to_set);
+	if (ret)
+		return ret;
+	si->dscp_rewrite_dscp_to_set = dscp_to_set << SFE_IPV4_DSCP_SHIFT;
+	return size;
+}
+
+static const struct device_attribute sfe_ipv4_dscp_rewrite_dscp_to_set_attr =
+	__ATTR(dscp_rewrite_dscp_to_set, S_IWUSR | S_IRUGO,
+	       sfe_ipv4_get_dscp_rewrite_dscp_to_set,
+	       sfe_ipv4_set_dscp_rewrite_dscp_to_set);
+
+/*
+ * sfe_ipv4_conn_match_hash_init()
+ *	Initialize conn match hash lists
+ */
+static void sfe_ipv4_conn_match_hash_init(struct sfe_ipv4 *si, int len)
+{
+	struct hlist_head *hash_list = si->hlist_conn_match_hash_head;
+	int i;
+
+	for (i = 0; i < len; i++) {
+		INIT_HLIST_HEAD(&hash_list[i]);
+	}
+}
+
+#ifdef SFE_PROCESS_LOCAL_OUT
+/*
+ * sfe_ipv4_local_out()
+ *	Called for packets from ip_local_out() - post encapsulation & other packets
+ */
+static unsigned int sfe_ipv4_local_out(void *priv, struct sk_buff *skb, const struct nf_hook_state *nhs)
+{
+	struct sfe_l2_info l2_info = {0};
+
+	DEBUG_TRACE("%px: sfe: sfe_ipv4_local_out hook called.\n", skb);
+
+	if (likely(skb->skb_iif)) {
+		return sfe_ipv4_recv(skb->dev, skb, &l2_info, true) ? NF_STOLEN : NF_ACCEPT;
+	}
+
+	return NF_ACCEPT;
+}
+
+/*
+ * struct nf_hook_ops sfe_ipv4_ops_local_out[]
+ *	Hooks into netfilter local out packet monitoring points.
+ */
+static struct nf_hook_ops sfe_ipv4_ops_local_out[] __read_mostly = {
+
+	/*
+	 * Local out routing hook is used to monitor packets.
+	 */
+	{
+		.hook           = sfe_ipv4_local_out,
+		.pf             = PF_INET,
+		.hooknum        = NF_INET_LOCAL_OUT,
+		.priority       = NF_IP_PRI_FIRST,
+	},
+};
+#endif
+
+/*
+ * sfe_ipv4_init()
+ */
+int sfe_ipv4_init(void)
+{
+	struct sfe_ipv4 *si = &__si;
+	int result = -1;
+
+	DEBUG_INFO("SFE IPv4 init\n");
+
+	sfe_ipv4_conn_match_hash_init(si, ARRAY_SIZE(si->hlist_conn_match_hash_head));
+
+	si->stats_pcpu = alloc_percpu_gfp(struct sfe_ipv4_stats, GFP_KERNEL | __GFP_ZERO);
+	if (!si->stats_pcpu) {
+		DEBUG_ERROR("failed to allocate stats memory for sfe_ipv4\n");
+		goto exit0;
+	}
+
+	/*
+	 * Create sys/sfe_ipv4
+	 */
+	si->sys_ipv4 = kobject_create_and_add("sfe_ipv4", NULL);
+	if (!si->sys_ipv4) {
+		DEBUG_ERROR("failed to register sfe_ipv4\n");
+		goto exit1;
+	}
+
+	/*
+	 * Create files, one for each parameter supported by this module.
+	 */
+	result = sysfs_create_file(si->sys_ipv4, &sfe_ipv4_debug_dev_attr.attr);
+	if (result) {
+		DEBUG_ERROR("failed to register debug dev file: %d\n", result);
+		goto exit2;
+	}
+
+	result = sysfs_create_file(si->sys_ipv4, &sfe_ipv4_cpu_attr.attr);
+	if (result) {
+		DEBUG_ERROR("failed to register debug dev file: %d\n", result);
+		goto exit3;
+	}
+
+	result = sysfs_create_file(si->sys_ipv4,
+				   &sfe_ipv4_dscp_rewrite_mark_to_match_attr.attr);
+	if (result) {
+		DEBUG_ERROR("failed to register DSCP rewrite mark_to_match file: %d\n",
+			    result);
+		goto exit4;
+	}
+	result = sysfs_create_file(si->sys_ipv4,
+				   &sfe_ipv4_dscp_rewrite_dscp_to_set_attr.attr);
+	if (result) {
+		DEBUG_ERROR("failed to register DSCP rewrite dscp_to_set file: %d\n",
+			    result);
+		goto exit5;
+	}
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+	result = sysfs_create_file(si->sys_ipv4, &sfe_ipv4_flow_cookie_attr.attr);
+	if (result) {
+		DEBUG_ERROR("failed to register flow cookie enable file: %d\n", result);
+		goto exit6;
+	}
+#endif /* CONFIG_NF_FLOW_COOKIE */
+
+#ifdef SFE_PROCESS_LOCAL_OUT
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	result = nf_register_hooks(sfe_ipv4_ops_local_out, ARRAY_SIZE(sfe_ipv4_ops_local_out));
+#else
+	result = nf_register_net_hooks(&init_net, sfe_ipv4_ops_local_out, ARRAY_SIZE(sfe_ipv4_ops_local_out));
+#endif
+	if (result < 0) {
+		DEBUG_ERROR("can't register nf local out hook: %d\n", result);
+		goto exit7;
+	}
+	DEBUG_INFO("Register nf local out hook success: %d\n", result);
+#endif
+	/*
+	 * Register our debug char device.
+	 */
+	result = register_chrdev(0, "sfe_ipv4", &sfe_ipv4_debug_dev_fops);
+	if (result < 0) {
+		DEBUG_ERROR("Failed to register chrdev: %d\n", result);
+		goto exit8;
+	}
+
+	si->debug_dev = result;
+	si->work_cpu = WORK_CPU_UNBOUND;
+
+	/*
+	 * Create a work to handle periodic statistics.
+	 */
+	INIT_DELAYED_WORK(&(si->sync_dwork), sfe_ipv4_periodic_sync);
+	schedule_delayed_work_on(si->work_cpu, &(si->sync_dwork), ((HZ + 99) / 100));
+
+	spin_lock_init(&si->lock);
+	return 0;
+
+exit8:
+#ifdef SFE_PROCESS_LOCAL_OUT
+	DEBUG_TRACE("sfe: Unregister local out hook\n");
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	nf_unregister_hooks(sfe_ipv4_ops_local_out, ARRAY_SIZE(sfe_ipv4_ops_local_out));
+#else
+	nf_unregister_net_hooks(&init_net, sfe_ipv4_ops_local_out, ARRAY_SIZE(sfe_ipv4_ops_local_out));
+#endif
+exit7:
+#endif
+#ifdef CONFIG_NF_FLOW_COOKIE
+	sysfs_remove_file(si->sys_ipv4, &sfe_ipv4_flow_cookie_attr.attr);
+
+exit6:
+#endif /* CONFIG_NF_FLOW_COOKIE */
+	sysfs_remove_file(si->sys_ipv4,
+			  &sfe_ipv4_dscp_rewrite_dscp_to_set_attr.attr);
+exit5:
+	sysfs_remove_file(si->sys_ipv4,
+			  &sfe_ipv4_dscp_rewrite_mark_to_match_attr.attr);
+exit4:
+	sysfs_remove_file(si->sys_ipv4, &sfe_ipv4_cpu_attr.attr);
+exit3:
+	sysfs_remove_file(si->sys_ipv4, &sfe_ipv4_debug_dev_attr.attr);
+
+exit2:
+	kobject_put(si->sys_ipv4);
+
+exit1:
+	free_percpu(si->stats_pcpu);
+
+exit0:
+	return result;
+}
+
+/*
+ * sfe_ipv4_exit()
+ */
+void sfe_ipv4_exit(void)
+{
+	struct sfe_ipv4 *si = &__si;
+
+	DEBUG_INFO("SFE IPv4 exit\n");
+	/*
+	 * Destroy all connections.
+	 */
+	sfe_ipv4_destroy_all_rules_for_dev(NULL);
+
+	cancel_delayed_work_sync(&si->sync_dwork);
+
+	unregister_chrdev(si->debug_dev, "sfe_ipv4");
+
+#ifdef SFE_PROCESS_LOCAL_OUT
+	DEBUG_TRACE("sfe: Unregister local out hook\n");
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	nf_unregister_hooks(sfe_ipv4_ops_local_out, ARRAY_SIZE(sfe_ipv4_ops_local_out));
+#else
+	nf_unregister_net_hooks(&init_net, sfe_ipv4_ops_local_out, ARRAY_SIZE(sfe_ipv4_ops_local_out));
+#endif
+#endif
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+	sysfs_remove_file(si->sys_ipv4, &sfe_ipv4_flow_cookie_attr.attr);
+#endif /* CONFIG_NF_FLOW_COOKIE */
+	sysfs_remove_file(si->sys_ipv4,
+			  &sfe_ipv4_dscp_rewrite_dscp_to_set_attr.attr);
+	sysfs_remove_file(si->sys_ipv4,
+			  &sfe_ipv4_dscp_rewrite_mark_to_match_attr.attr);
+	sysfs_remove_file(si->sys_ipv4, &sfe_ipv4_debug_dev_attr.attr);
+
+	sysfs_remove_file(si->sys_ipv4, &sfe_ipv4_cpu_attr.attr);
+
+	kobject_put(si->sys_ipv4);
+
+	free_percpu(si->stats_pcpu);
+}
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+EXPORT_SYMBOL(sfe_register_flow_cookie_cb);
+EXPORT_SYMBOL(sfe_unregister_flow_cookie_cb);
+#endif
diff --git a/qca-nss-sfe/sfe_ipv4.h b/qca-nss-sfe/sfe_ipv4.h
new file mode 100644
index 0000000..4e8169b
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv4.h
@@ -0,0 +1,422 @@
+/*
+ * sfe_ipv4.h
+ *	Shortcut forwarding engine header file for IPv4.
+ *
+ * Copyright (c) 2013-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __SFE_IPV4_H
+#define __SFE_IPV4_H
+
+#define SFE_IPV4_DSCP_MASK 0x3
+#define SFE_IPV4_DSCP_SHIFT 2
+
+/*
+ * Specifies the lower bound on ACK numbers carried in the TCP header
+ */
+#define SFE_IPV4_TCP_MAX_ACK_WINDOW 65520
+
+/*
+ * IPv4 TCP connection match additional data.
+ */
+struct sfe_ipv4_tcp_connection_match {
+	u8 win_scale;		/* Window scale */
+	u32 max_win;		/* Maximum window size seen */
+	u32 end;			/* Sequence number of the next byte to send (seq + segment length) */
+	u32 max_end;		/* Sequence number of the last byte to ack */
+};
+
+/*
+ * Bit flags for IPv4 connection matching entry.
+ */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_SRC (1<<0)
+					/* Perform source translation */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_DEST (1<<1)
+					/* Perform destination translation */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK (1<<2)
+					/* Ignore TCP sequence numbers */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR (1<<3)
+					/* Fast Ethernet header write */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_L2_HDR (1<<4)
+					/* Fast Ethernet header write */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_PRIORITY_REMARK (1<<5)
+					/* remark priority of SKB */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_DSCP_REMARK (1<<6)
+					/* remark DSCP of packet */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_CSUM_OFFLOAD (1<<7)
+					/* checksum offload.*/
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_PPPOE_DECAP (1<<8)
+					/* Indicates that PPPoE should be decapsulated */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_PPPOE_ENCAP (1<<9)
+					/* Indicates that PPPoE should be encapsulated */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_BRIDGE_FLOW (1<<10)
+					/* Bridge flow */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_MARK (1<<11)
+					/* skb mark of the packet */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_INSERT_EGRESS_VLAN_TAG (1<<12)
+					/* Insert VLAN tag */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK (1<<13)
+					/* Source interface check */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_PASSTHROUGH (1<<14)
+					/* passthrough flow: encap/decap to be skipped for this flow */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT (1<<15)
+					/* skb go fast xmit */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT_FLOW_CHECKED (1<<16)
+					/* Fast xmit flow checked or not */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT_DEV_ADMISSION (1<<17)
+					/* Fast xmit may be possible for this flow, if SFE check passes */
+#define SFE_IPV4_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK_NO_FLUSH (1<<18)
+					/* Source interface check but do not flush the connection */
+
+/*
+ * IPv4 connection matching structure.
+ */
+struct sfe_ipv4_connection_match {
+	/*
+	 * References to other objects.
+	 */
+	struct hlist_node hnode;
+
+	struct sfe_ipv4_connection *connection;
+	struct sfe_ipv4_connection_match *counter_match;
+					/* Matches the flow in the opposite direction as the one in *connection */
+	/*
+	 * Characteristics that identify flows that match this rule.
+	 */
+	struct net_device *match_dev;	/* Network device */
+	u8 match_protocol;		/* Protocol */
+	__be32 match_src_ip;		/* Source IP address */
+	__be32 match_dest_ip;		/* Destination IP address */
+	__be16 match_src_port;		/* Source port/connection ident */
+	__be16 match_dest_port;		/* Destination port/connection ident */
+
+	struct udp_sock *up;		/* Stores UDP sock information; valid only in decap path */
+	struct net_protocol *proto;	/* stores protocol handler; valid only in decap path */
+
+	/*
+	 * Control the operations of the match.
+	 */
+	u32 flags;			/* Bit flags */
+#ifdef CONFIG_NF_FLOW_COOKIE
+	u32 flow_cookie;		/* used flow cookie, for debug */
+#endif
+#ifdef CONFIG_XFRM
+	u32 flow_accel;             /* The flow accelerated or not */
+#endif
+
+	/*
+	 * Connection state that we track once we match.
+	 */
+	union {				/* Protocol-specific state */
+		struct sfe_ipv4_tcp_connection_match tcp;
+	} protocol_state;
+
+	/*
+	 * VLAN headers
+	 */
+	struct sfe_vlan_hdr ingress_vlan_hdr[SFE_MAX_VLAN_DEPTH];
+	struct sfe_vlan_hdr egress_vlan_hdr[SFE_MAX_VLAN_DEPTH];
+
+	/*
+	 * Stats recorded in a sync period. These stats will be added to
+	 * rx_packet_count64/rx_byte_count64 after a sync period.
+	 */
+	atomic_t rx_packet_count;
+	atomic_t rx_byte_count;
+
+	/*
+	 * Packet translation information.
+	 */
+	__be32 xlate_src_ip;		/* Address after source translation */
+	__be16 xlate_src_port;	/* Port/connection ident after source translation */
+	u16 xlate_src_csum_adjustment;
+					/* Transport layer checksum adjustment after source translation */
+	u16 xlate_src_partial_csum_adjustment;
+					/* Transport layer pseudo header checksum adjustment after source translation */
+
+	__be32 xlate_dest_ip;		/* Address after destination translation */
+	__be16 xlate_dest_port;	/* Port/connection ident after destination translation */
+	u16 xlate_dest_csum_adjustment;
+					/* Transport layer checksum adjustment after destination translation */
+	u16 xlate_dest_partial_csum_adjustment;
+					/* Transport layer pseudo header checksum adjustment after destination translation */
+
+	/*
+	 * QoS information
+	 */
+	u32 priority;
+	u32 dscp;
+	u32 mark;			/* mark for outgoing packet */
+
+	/*
+	 * Packet transmit information.
+	 */
+	struct net_device *xmit_dev;	/* Network device on which to transmit */
+	unsigned short int xmit_dev_mtu;
+					/* Interface MTU */
+	u16 xmit_dest_mac[ETH_ALEN / 2];
+					/* Destination MAC address to use when forwarding */
+	u16 xmit_src_mac[ETH_ALEN / 2];
+					/* Source MAC address to use when forwarding */
+
+	u8 ingress_vlan_hdr_cnt;        /* Ingress active vlan headers count */
+	u8 egress_vlan_hdr_cnt;         /* Egress active vlan headers count */
+
+	/*
+	 * Summary stats.
+	 */
+	u64 rx_packet_count64;
+	u64 rx_byte_count64;
+
+	/*
+	 * PPPoE information
+	 */
+	u16 pppoe_session_id;
+	u8 pppoe_remote_mac[ETH_ALEN];
+
+	/*
+	 * Size of all needed L2 headers
+	 */
+	u16 l2_hdr_size;
+
+	/*
+	 * xmit device's feature
+	 */
+	netdev_features_t features;
+};
+
+/*
+ * Per-connection data structure.
+ */
+struct sfe_ipv4_connection {
+	struct sfe_ipv4_connection *next;
+					/* Pointer to the next entry in a hash chain */
+	struct sfe_ipv4_connection *prev;
+					/* Pointer to the previous entry in a hash chain */
+	int protocol;			/* IP protocol number */
+	__be32 src_ip;			/* Src IP addr pre-translation */
+	__be32 src_ip_xlate;		/* Src IP addr post-translation */
+	__be32 dest_ip;			/* Dest IP addr pre-translation */
+	__be32 dest_ip_xlate;		/* Dest IP addr post-translation */
+	__be16 src_port;		/* Src port pre-translation */
+	__be16 src_port_xlate;		/* Src port post-translation */
+	__be16 dest_port;		/* Dest port pre-translation */
+	__be16 dest_port_xlate;		/* Dest port post-translation */
+	struct sfe_ipv4_connection_match *original_match;
+					/* Original direction matching structure */
+	struct net_device *original_dev;
+					/* Original direction source device */
+	struct sfe_ipv4_connection_match *reply_match;
+					/* Reply direction matching structure */
+	struct net_device *reply_dev;	/* Reply direction source device */
+	u64 last_sync_jiffies;		/* Jiffies count for the last sync */
+	struct sfe_ipv4_connection *all_connections_next;
+					/* Pointer to the next entry in the list of all connections */
+	struct sfe_ipv4_connection *all_connections_prev;
+					/* Pointer to the previous entry in the list of all connections */
+	u32 debug_read_seq;		/* sequence number for debug dump */
+	bool removed;			/* Indicates the connection is removed */
+	struct rcu_head rcu;		/* delay rcu free */
+};
+
+/*
+ * IPv4 connections and hash table size information.
+ */
+#define SFE_IPV4_CONNECTION_HASH_SHIFT 12
+#define SFE_IPV4_CONNECTION_HASH_SIZE (1 << SFE_IPV4_CONNECTION_HASH_SHIFT)
+#define SFE_IPV4_CONNECTION_HASH_MASK (SFE_IPV4_CONNECTION_HASH_SIZE - 1)
+
+enum sfe_ipv4_exception_events {
+	SFE_IPV4_EXCEPTION_EVENT_UDP_HEADER_INCOMPLETE,
+	SFE_IPV4_EXCEPTION_EVENT_UDP_NO_CONNECTION,
+	SFE_IPV4_EXCEPTION_EVENT_UDP_IP_OPTIONS_OR_INITIAL_FRAGMENT,
+	SFE_IPV4_EXCEPTION_EVENT_UDP_SMALL_TTL,
+	SFE_IPV4_EXCEPTION_EVENT_UDP_NEEDS_FRAGMENTATION,
+	SFE_IPV4_EXCEPTION_EVENT_TCP_HEADER_INCOMPLETE,
+	SFE_IPV4_EXCEPTION_EVENT_TCP_NO_CONNECTION_SLOW_FLAGS,
+	SFE_IPV4_EXCEPTION_EVENT_TCP_NO_CONNECTION_FAST_FLAGS,
+	SFE_IPV4_EXCEPTION_EVENT_TCP_IP_OPTIONS_OR_INITIAL_FRAGMENT,
+	SFE_IPV4_EXCEPTION_EVENT_TCP_SMALL_TTL,
+	SFE_IPV4_EXCEPTION_EVENT_TCP_NEEDS_FRAGMENTATION,
+	SFE_IPV4_EXCEPTION_EVENT_TCP_FLAGS,
+	SFE_IPV4_EXCEPTION_EVENT_TCP_SEQ_EXCEEDS_RIGHT_EDGE,
+	SFE_IPV4_EXCEPTION_EVENT_TCP_SMALL_DATA_OFFS,
+	SFE_IPV4_EXCEPTION_EVENT_TCP_BAD_SACK,
+	SFE_IPV4_EXCEPTION_EVENT_TCP_BIG_DATA_OFFS,
+	SFE_IPV4_EXCEPTION_EVENT_TCP_SEQ_BEFORE_LEFT_EDGE,
+	SFE_IPV4_EXCEPTION_EVENT_TCP_ACK_EXCEEDS_RIGHT_EDGE,
+	SFE_IPV4_EXCEPTION_EVENT_TCP_ACK_BEFORE_LEFT_EDGE,
+	SFE_IPV4_EXCEPTION_EVENT_ICMP_HEADER_INCOMPLETE,
+	SFE_IPV4_EXCEPTION_EVENT_ICMP_UNHANDLED_TYPE,
+	SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_HEADER_INCOMPLETE,
+	SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_NON_V4,
+	SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_IP_OPTIONS_INCOMPLETE,
+	SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_UDP_HEADER_INCOMPLETE,
+	SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_TCP_HEADER_INCOMPLETE,
+	SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_UNHANDLED_PROTOCOL,
+	SFE_IPV4_EXCEPTION_EVENT_ICMP_NO_CONNECTION,
+	SFE_IPV4_EXCEPTION_EVENT_ICMP_FLUSHED_CONNECTION,
+	SFE_IPV4_EXCEPTION_EVENT_HEADER_INCOMPLETE,
+	SFE_IPV4_EXCEPTION_EVENT_HEADER_CSUM_BAD,
+	SFE_IPV4_EXCEPTION_EVENT_BAD_TOTAL_LENGTH,
+	SFE_IPV4_EXCEPTION_EVENT_NON_V4,
+	SFE_IPV4_EXCEPTION_EVENT_NON_INITIAL_FRAGMENT,
+	SFE_IPV4_EXCEPTION_EVENT_DATAGRAM_INCOMPLETE,
+	SFE_IPV4_EXCEPTION_EVENT_IP_OPTIONS_INCOMPLETE,
+	SFE_IPV4_EXCEPTION_EVENT_UNHANDLED_PROTOCOL,
+	SFE_IPV4_EXCEPTION_EVENT_NO_HEADROOM,
+	SFE_IPV4_EXCEPTION_EVENT_INVALID_PPPOE_SESSION,
+	SFE_IPV4_EXCEPTION_EVENT_INCORRECT_PPPOE_PARSING,
+	SFE_IPV4_EXCEPTION_EVENT_PPPOE_NOT_SET_IN_CME,
+	SFE_IPV4_EXCEPTION_EVENT_INGRESS_VLAN_TAG_MISMATCH,
+	SFE_IPV4_EXCEPTION_EVENT_INVALID_SRC_IFACE,
+	SFE_IPV4_EXCEPTION_EVENT_GRE_HEADER_INCOMPLETE,
+	SFE_IPV4_EXCEPTION_EVENT_GRE_NO_CONNECTION,
+	SFE_IPV4_EXCEPTION_EVENT_GRE_IP_OPTIONS_OR_INITIAL_FRAGMENT,
+	SFE_IPV4_EXCEPTION_EVENT_GRE_SMALL_TTL,
+	SFE_IPV4_EXCEPTION_EVENT_GRE_NEEDS_FRAGMENTATION,
+	SFE_IPV4_EXCEPTION_EVENT_LAST
+};
+
+/*
+ * per CPU stats
+ */
+struct sfe_ipv4_stats {
+	/*
+	 * Stats recorded in a sync period. These stats will be added to
+	 * connection_xxx64 after a sync period.
+	 */
+	u64 connection_create_requests64;
+					/* Number of IPv4 connection create requests */
+	u64 connection_create_collisions64;
+					/* Number of IPv4 connection create requests that collided with existing hash table entries */
+	u64 connection_create_failures64;
+					/* Number of IPv4 connection create requests that failed */
+	u64 connection_destroy_requests64;
+					/* Number of IPv4 connection destroy requests */
+	u64 connection_destroy_misses64;
+					/* Number of IPv4 connection destroy requests that missed our hash table */
+	u64 connection_match_hash_hits64;
+					/* Number of IPv4 connection match hash hits */
+	u64 connection_match_hash_reorders64;
+					/* Number of IPv4 connection match hash reorders */
+	u64 connection_flushes64;		/* Number of IPv4 connection flushes */
+	u64 packets_dropped64;			/* Number of IPv4 packets dropped */
+	u64 packets_forwarded64;		/* Number of IPv4 packets forwarded */
+	u64 packets_fast_xmited64;		/* Number of IPv4 packets fast transmited */
+	u64 packets_not_forwarded64;	/* Number of IPv4 packets not forwarded */
+	u64 exception_events64[SFE_IPV4_EXCEPTION_EVENT_LAST];
+	u64 pppoe_encap_packets_forwarded64;	/* Number of IPv4 PPPoE encap packets forwarded */
+	u64 pppoe_decap_packets_forwarded64;	/* Number of IPv4 PPPoE decap packets forwarded */
+	u64 pppoe_bridge_packets_forwarded64;	/* Number of IPv4 PPPoE bridge packets forwarded */
+};
+
+/*
+ * Per-module structure.
+ */
+struct sfe_ipv4 {
+	spinlock_t lock;		/* Lock for SMP correctness */
+	struct sfe_ipv4_connection *all_connections_head;
+					/* Head of the list of all connections */
+	struct sfe_ipv4_connection *all_connections_tail;
+					/* Tail of the list of all connections */
+	unsigned int num_connections;	/* Number of connections */
+	struct delayed_work sync_dwork;	/* Work to sync the statistics */
+	unsigned int work_cpu;		/* The core to run stats sync on */
+
+	sfe_sync_rule_callback_t __rcu sync_rule_callback;
+					/* Callback function registered by a connection manager for stats syncing */
+	struct sfe_ipv4_connection *conn_hash[SFE_IPV4_CONNECTION_HASH_SIZE];
+					/* Connection hash table */
+
+	struct hlist_head hlist_conn_match_hash_head[SFE_IPV4_CONNECTION_HASH_SIZE];
+					/* Connection match hash table */
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+	struct sfe_flow_cookie_entry sfe_flow_cookie_table[SFE_FLOW_COOKIE_SIZE];
+					/* flow cookie table*/
+	flow_cookie_set_func_t flow_cookie_set_func;
+					/* function used to configure flow cookie in hardware*/
+	int flow_cookie_enable;
+					/* Enable/disable flow cookie at runtime */
+#endif
+
+	struct sfe_ipv4_stats __percpu *stats_pcpu;
+					/* Per CPU statistics. */
+
+	struct sfe_ipv4_connection *wc_next; /* Connection list walk pointer for stats sync */
+
+	/*
+	 * Control state.
+	 */
+	struct kobject *sys_ipv4;	/* sysfs linkage */
+	int debug_dev;			/* Major number of the debug char device */
+	u32 debug_read_seq;	/* sequence number for debug dump */
+
+	/*
+	 * DSCP rewrite table
+	 * When `mark_to_match` is set non-zero then any packet with the
+	 * specified skb->mark will override flow DSCP policy with
+	 * `dscp_to_set` value. i.e. basically equivalent to `iptables -m mark
+	 * --mark <mark_to_match> -j DSCP --set-dscp <dscp_to_set>`
+	 */
+	u32 dscp_rewrite_mark_to_match;
+	u32 dscp_rewrite_dscp_to_set;
+};
+
+/*
+ * Enumeration of the XML output.
+ */
+enum sfe_ipv4_debug_xml_states {
+	SFE_IPV4_DEBUG_XML_STATE_START,
+	SFE_IPV4_DEBUG_XML_STATE_CONNECTIONS_START,
+	SFE_IPV4_DEBUG_XML_STATE_CONNECTIONS_CONNECTION,
+	SFE_IPV4_DEBUG_XML_STATE_CONNECTIONS_END,
+	SFE_IPV4_DEBUG_XML_STATE_EXCEPTIONS_START,
+	SFE_IPV4_DEBUG_XML_STATE_EXCEPTIONS_EXCEPTION,
+	SFE_IPV4_DEBUG_XML_STATE_EXCEPTIONS_END,
+	SFE_IPV4_DEBUG_XML_STATE_STATS,
+	SFE_IPV4_DEBUG_XML_STATE_END,
+	SFE_IPV4_DEBUG_XML_STATE_DONE
+};
+
+/*
+ * XML write state.
+ */
+struct sfe_ipv4_debug_xml_write_state {
+	enum sfe_ipv4_debug_xml_states state;
+					/* XML output file state machine state */
+	int iter_exception;		/* Next exception iterator */
+};
+
+typedef bool (*sfe_ipv4_debug_xml_write_method_t)(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length,
+						  int *total_read, struct sfe_ipv4_debug_xml_write_state *ws);
+
+u16 sfe_ipv4_gen_ip_csum(struct iphdr *iph);
+void sfe_ipv4_exception_stats_inc(struct sfe_ipv4 *si, enum sfe_ipv4_exception_events reason);
+bool sfe_ipv4_remove_connection(struct sfe_ipv4 *si, struct sfe_ipv4_connection *c);
+void sfe_ipv4_flush_connection(struct sfe_ipv4 *si, struct sfe_ipv4_connection *c, sfe_sync_reason_t reason);
+void sfe_ipv4_sync_status(struct sfe_ipv4 *si, struct sfe_ipv4_connection *c, sfe_sync_reason_t reason);
+
+struct sfe_ipv4_connection_match *
+sfe_ipv4_find_connection_match_rcu(struct sfe_ipv4 *si, struct net_device *dev, u8 protocol,
+					__be32 src_ip, __be16 src_port,
+					__be32 dest_ip, __be16 dest_port);
+
+void sfe_ipv4_exit(void);
+int sfe_ipv4_init(void);
+
+#endif /* __SFE_IPV4_H */
diff --git a/qca-nss-sfe/sfe_ipv4_gre.c b/qca-nss-sfe/sfe_ipv4_gre.c
new file mode 100644
index 0000000..9626a58
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv4_gre.c
@@ -0,0 +1,328 @@
+/*
+ * sfe_ipv4_gre.c
+ *	Shortcut forwarding engine file for IPv4 GRE
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/skbuff.h>
+#include <net/protocol.h>
+#include <linux/etherdevice.h>
+#include <linux/lockdep.h>
+#include <net/gre.h>
+#include <net/pptp.h>
+
+#include "sfe_debug.h"
+#include "sfe_api.h"
+#include "sfe.h"
+#include "sfe_flow_cookie.h"
+#include "sfe_ipv4.h"
+#include "sfe_vlan.h"
+
+/*
+ * sfe_ipv4_recv_gre()
+ *	GRE tunnel packet receive and forwarding.
+ */
+int sfe_ipv4_recv_gre(struct sfe_ipv4 *si, struct sk_buff *skb, struct net_device *dev,
+		      unsigned int len, struct iphdr *iph, unsigned int ihl, bool sync_on_find,
+		      struct sfe_l2_info *l2_info, bool tun_outer)
+{
+	struct sfe_ipv4_connection_match *cm;
+	struct pptp_gre_header *pptp_hdr;
+	struct gre_base_hdr *gre_hdr;
+	struct net_device *xmit_dev;
+	__be16 dest_port = 0;
+	bool passthrough;
+	bool bridge_flow;
+	__be32 dest_ip;
+	__be32 src_ip;
+	bool hw_csum;
+	bool ret;
+	u8 ttl;
+
+	/*
+	 * Is our packet too short to contain a valid GRE header?
+	 */
+	if (unlikely(!pskb_may_pull(skb, sizeof(*gre_hdr) + ihl))) {
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_GRE_HEADER_INCOMPLETE);
+		DEBUG_TRACE("packet too short for GRE header\n");
+		return 0;
+	}
+
+
+	/*
+	 * Read the source and destination IP address.
+	 */
+	src_ip = iph->saddr;
+	dest_ip = iph->daddr;
+
+	rcu_read_lock();
+
+	/*
+	 * Look for a connection match with 4 tuple if it is PPTP
+	 */
+	gre_hdr = (struct gre_base_hdr *)(skb->data + ihl);
+
+	if ((gre_hdr->protocol == GRE_PROTO_PPP) && likely(pskb_may_pull(skb, (sizeof(*pptp_hdr) - 8) + ihl))) {
+		pptp_hdr = (struct pptp_gre_header *)(skb->data + ihl);
+		dest_port = pptp_hdr->call_id;
+	}
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+	cm = si->sfe_flow_cookie_table[skb->flow_cookie & SFE_FLOW_COOKIE_MASK].match;
+	if (unlikely(!cm)) {
+		cm = sfe_ipv4_find_connection_match_rcu(si, dev, IPPROTO_GRE, src_ip, 0, dest_ip, dest_port);
+	}
+#else
+	cm = sfe_ipv4_find_connection_match_rcu(si, dev, IPPROTO_GRE, src_ip, 0, dest_ip, dest_port);
+#endif
+
+	if (unlikely(!cm)) {
+		rcu_read_unlock();
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_GRE_NO_CONNECTION);
+		DEBUG_INFO("no GRE connection match found dev %s src ip %pI4 dest ip %pI4 port %d\n", dev->name, &src_ip, &dest_ip, ntohs(dest_port));
+		return 0;
+	}
+
+	/*
+	 * Source interface validate.
+	 */
+	if (unlikely((cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK) && (cm->match_dev != dev))) {
+		if (!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK_NO_FLUSH)) {
+			struct sfe_ipv4_connection *c = cm->connection;
+			int ret;
+
+			DEBUG_TRACE("flush on source interface check failure\n");
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv4_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			if (ret) {
+				sfe_ipv4_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+		}
+		rcu_read_unlock();
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_INVALID_SRC_IFACE);
+		DEBUG_TRACE("exception the packet on source interface check failure\n");
+		return 0;
+	}
+
+	passthrough = cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_PASSTHROUGH;
+
+	/*
+	 * If our packet has been marked as "sync on find" we can't actually
+	 * forward it in the fast path, but now that we've found an associated
+	 * connection we need sync its status before exception it to slow path unless
+	 * it is passthrough (packets not directed to DUT) packet.
+	 * TODO: revisit to ensure that pass through traffic is not bypassing firewall for fragmented cases
+	 */
+	if (unlikely(sync_on_find) && !passthrough) {
+		sfe_ipv4_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_GRE_IP_OPTIONS_OR_INITIAL_FRAGMENT);
+		DEBUG_TRACE("%px: sfe: sync on find\n", cm);
+		return 0;
+	}
+
+	/*
+	 * Do we expect an ingress VLAN tag for this flow?
+	 */
+	if (unlikely(!sfe_vlan_validate_ingress_tag(skb, cm->ingress_vlan_hdr_cnt, cm->ingress_vlan_hdr, l2_info))) {
+		rcu_read_unlock();
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_INGRESS_VLAN_TAG_MISMATCH);
+		DEBUG_TRACE("VLAN tag mismatch. skb=%px\n", skb);
+		return 0;
+	}
+
+	bridge_flow = !!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_BRIDGE_FLOW);
+
+	/*
+	 * Does our TTL allow forwarding?
+	 */
+	ttl = iph->ttl;
+	if (!bridge_flow && (ttl < 2) && passthrough) {
+		sfe_ipv4_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+
+		DEBUG_TRACE("%px: sfe: TTL too low\n", skb);
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_GRE_SMALL_TTL);
+		return 0;
+	}
+
+	/*
+	 * From this point on we're good to modify the packet.
+	 */
+
+	/*
+	 * Check if skb was cloned. If it was, unshare it. Because
+	 * the data area is going to be written in this path and we don't want to
+	 * change the cloned skb's data section.
+	 */
+	if (unlikely(skb_cloned(skb))) {
+		DEBUG_TRACE("%px: skb is a cloned skb\n", skb);
+		skb = skb_unshare(skb, GFP_ATOMIC);
+		if (!skb) {
+			DEBUG_WARN("Failed to unshare the cloned skb\n");
+			rcu_read_unlock();
+			return 1;
+		}
+
+		/*
+		 * Update the iph and udph pointers with the unshared skb's data area.
+		 */
+		iph = (struct iphdr *)skb->data;
+	}
+
+	/*
+	 * Check if skb has enough headroom to write L2 headers
+	 */
+	if (unlikely(skb_headroom(skb) < cm->l2_hdr_size)) {
+		rcu_read_unlock();
+		DEBUG_WARN("%px: Not enough headroom: %u\n", skb, skb_headroom(skb));
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_NO_HEADROOM);
+		return 0;
+	}
+
+	/*
+	 * Enable HW csum if rx checksum is verified and xmit interface is CSUM offload capable.
+	 */
+	hw_csum = !!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_CSUM_OFFLOAD) && (skb->ip_summed == CHECKSUM_UNNECESSARY);
+
+	/*
+	 * protocol handler will be valid only in decap-path.
+	 */
+	if (cm->proto) {
+		struct net_protocol *ipprot = cm->proto;
+		skb_reset_network_header(skb);
+		skb_pull(skb, ihl);
+		skb_reset_transport_header(skb);
+		skb->fast_forwarded = 1;
+
+		ret = ipprot->handler(skb);
+		if (ret) {
+			this_cpu_inc(si->stats_pcpu->packets_not_forwarded64);
+			rcu_read_unlock();
+			DEBUG_TRACE("GRE handler returned error %u\n", ret);
+			return 1;
+		}
+
+		/*
+		 * Update traffic stats
+		 */
+		atomic_inc(&cm->rx_packet_count);
+		atomic_add(len, &cm->rx_byte_count);
+
+		this_cpu_inc(si->stats_pcpu->packets_forwarded64);
+		rcu_read_unlock();
+		return 1;
+	}
+
+	/*
+	 * If our packet is larger than the MTU of the transmit interface then
+	 * we can't forward it easily.
+	 */
+	if (unlikely(len > cm->xmit_dev_mtu)) {
+		sfe_ipv4_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_GRE_NEEDS_FRAGMENTATION);
+		DEBUG_TRACE("%px: sfe: larger than MTU\n", cm);
+		return 0;
+	}
+
+	/*
+	 * Decrement our TTL
+	 */
+	iph->ttl = (ttl - (u8)(!bridge_flow && !tun_outer));
+
+	/*
+	 * Update DSCP
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_DSCP_REMARK)) {
+		iph->tos = (iph->tos & SFE_IPV4_DSCP_MASK) | cm->dscp;
+	}
+
+	/*
+	 * Replace the IP checksum.
+	 */
+	if (likely(hw_csum)) {
+		skb->ip_summed = CHECKSUM_PARTIAL;
+	} else {
+		iph->check = sfe_ipv4_gen_ip_csum(iph);
+	}
+
+	/*
+	 * Update traffic stats
+	 */
+	atomic_inc(&cm->rx_packet_count);
+	atomic_add(len, &cm->rx_byte_count);
+
+	xmit_dev = cm->xmit_dev;
+	skb->dev = xmit_dev;
+
+	/*
+	 * Check to see if we need to add VLAN tags
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_INSERT_EGRESS_VLAN_TAG)) {
+		sfe_vlan_add_tag(skb, cm->egress_vlan_hdr_cnt, cm->egress_vlan_hdr);
+	}
+
+	/*
+	 * For the simple case we write this really fast.
+	 */
+	if (cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR) {
+		struct ethhdr *eth = (struct ethhdr *)__skb_push(skb, ETH_HLEN);
+		eth->h_proto = htons(ETH_P_IP);
+		ether_addr_copy((u8 *)eth->h_dest, (u8 *)cm->xmit_dest_mac);
+		ether_addr_copy((u8 *)eth->h_source, (u8 *)cm->xmit_src_mac);
+	} else if (cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_L2_HDR) {
+		dev_hard_header(skb, xmit_dev, ETH_P_IP, cm->xmit_dest_mac, cm->xmit_src_mac, len);
+	}
+
+	/*
+	 * Update priority of skb.
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_PRIORITY_REMARK)) {
+		skb->priority = cm->priority;
+	}
+
+	/*
+	 * Mark outgoing packet.
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_MARK)) {
+		skb->mark = cm->mark;
+	}
+
+	this_cpu_inc(si->stats_pcpu->packets_forwarded64);
+
+	rcu_read_unlock();
+
+	/*
+	 * We're going to check for GSO flags when we transmit the packet so
+	 * start fetching the necessary cache line now.
+	 */
+	prefetch(skb_shinfo(skb));
+
+	/*
+	 * Mark that this packet has been fast forwarded.
+	 */
+	skb->fast_forwarded = 1;
+
+	/*
+	 * Send the packet on its way.
+	 */
+	dev_queue_xmit(skb);
+
+	return 1;
+}
diff --git a/qca-nss-sfe/sfe_ipv4_gre.h b/qca-nss-sfe/sfe_ipv4_gre.h
new file mode 100644
index 0000000..b60ce9b
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv4_gre.h
@@ -0,0 +1,21 @@
+/*
+ * sfe_ipv4_gre.h
+ *	Shortcut forwarding engine - IPv4 GRE header file
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+int sfe_ipv4_recv_gre(struct sfe_ipv4 *si, struct sk_buff *skb, struct net_device *dev,
+		      unsigned int len, struct iphdr *iph, unsigned int ihl, bool sync_on_find,
+		      struct sfe_l2_info *l2_info, bool tun_outer);
diff --git a/qca-nss-sfe/sfe_ipv4_icmp.c b/qca-nss-sfe/sfe_ipv4_icmp.c
new file mode 100644
index 0000000..b680c4d
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv4_icmp.c
@@ -0,0 +1,206 @@
+/*
+ * sfe_ipv4_icmp.c
+ *	Shortcut forwarding engine - IPv4 ICMP implementation
+ *
+ * Copyright (c) 2013-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/skbuff.h>
+#include <linux/ip.h>
+#include <net/udp.h>
+#include <net/tcp.h>
+#include <net/icmp.h>
+#include <linux/etherdevice.h>
+#include <linux/lockdep.h>
+
+#include "sfe_debug.h"
+#include "sfe_api.h"
+#include "sfe.h"
+#include "sfe_flow_cookie.h"
+#include "sfe_ipv4.h"
+
+/*
+ * sfe_ipv4_recv_icmp()
+ *	Handle ICMP packet receives.
+ *
+ * ICMP packets aren't handled as a "fast path" and always have us process them
+ * through the default Linux stack.  What we do need to do is look for any errors
+ * about connections we are handling in the fast path.  If we find any such
+ * connections then we want to flush their state so that the ICMP error path
+ * within Linux has all of the correct state should it need it.
+ */
+int sfe_ipv4_recv_icmp(struct sfe_ipv4 *si, struct sk_buff *skb, struct net_device *dev,
+			      unsigned int len, struct iphdr *iph, unsigned int ihl)
+{
+	struct icmphdr *icmph;
+	struct iphdr *icmp_iph;
+	unsigned int icmp_ihl_words;
+	unsigned int icmp_ihl;
+	u32 *icmp_trans_h;
+	struct udphdr *icmp_udph;
+	struct tcphdr *icmp_tcph;
+	__be32 src_ip;
+	__be32 dest_ip;
+	__be16 src_port;
+	__be16 dest_port;
+	struct sfe_ipv4_connection_match *cm;
+	struct sfe_ipv4_connection *c;
+	u32 pull_len = sizeof(struct icmphdr) + ihl;
+	bool ret;
+
+	/*
+	 * Is our packet too short to contain a valid ICMP header?
+	 */
+	len -= ihl;
+	if (!pskb_may_pull(skb, pull_len)) {
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_ICMP_HEADER_INCOMPLETE);
+
+		DEBUG_TRACE("packet too short for ICMP header\n");
+		return 0;
+	}
+
+	/*
+	 * We only handle "destination unreachable" and "time exceeded" messages.
+	 */
+	icmph = (struct icmphdr *)(skb->data + ihl);
+	if ((icmph->type != ICMP_DEST_UNREACH)
+	    && (icmph->type != ICMP_TIME_EXCEEDED)) {
+
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_ICMP_UNHANDLED_TYPE);
+		DEBUG_TRACE("unhandled ICMP type: 0x%x\n", icmph->type);
+		return 0;
+	}
+
+	/*
+	 * Do we have the full embedded IP header?
+	 */
+	len -= sizeof(struct icmphdr);
+	pull_len += sizeof(struct iphdr);
+	if (!pskb_may_pull(skb, pull_len)) {
+
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_HEADER_INCOMPLETE);
+		DEBUG_TRACE("Embedded IP header not complete\n");
+		return 0;
+	}
+
+	/*
+	 * Is our embedded IP version wrong?
+	 */
+	icmp_iph = (struct iphdr *)(icmph + 1);
+	if (unlikely(icmp_iph->version != 4)) {
+
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_NON_V4);
+		DEBUG_TRACE("IP version: %u\n", icmp_iph->version);
+		return 0;
+	}
+
+	/*
+	 * Do we have the full embedded IP header, including any options?
+	 */
+	icmp_ihl_words = icmp_iph->ihl;
+	icmp_ihl = icmp_ihl_words << 2;
+	pull_len += icmp_ihl - sizeof(struct iphdr);
+	if (!pskb_may_pull(skb, pull_len)) {
+
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_IP_OPTIONS_INCOMPLETE);
+		DEBUG_TRACE("Embedded header not large enough for IP options\n");
+		return 0;
+	}
+
+	len -= icmp_ihl;
+	icmp_trans_h = ((u32 *)icmp_iph) + icmp_ihl_words;
+
+	/*
+	 * Handle the embedded transport layer header.
+	 */
+	switch (icmp_iph->protocol) {
+	case IPPROTO_UDP:
+		/*
+		 * We should have 8 bytes of UDP header - that's enough to identify
+		 * the connection.
+		 */
+		pull_len += 8;
+		if (!pskb_may_pull(skb, pull_len)) {
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_UDP_HEADER_INCOMPLETE);
+			DEBUG_TRACE("Incomplete embedded UDP header\n");
+			return 0;
+		}
+
+		icmp_udph = (struct udphdr *)icmp_trans_h;
+		src_port = icmp_udph->source;
+		dest_port = icmp_udph->dest;
+		break;
+
+	case IPPROTO_TCP:
+		/*
+		 * We should have 8 bytes of TCP header - that's enough to identify
+		 * the connection.
+		 */
+		pull_len += 8;
+		if (!pskb_may_pull(skb, pull_len)) {
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_TCP_HEADER_INCOMPLETE);
+			DEBUG_TRACE("Incomplete embedded TCP header\n");
+			return 0;
+		}
+
+		icmp_tcph = (struct tcphdr *)icmp_trans_h;
+		src_port = icmp_tcph->source;
+		dest_port = icmp_tcph->dest;
+		break;
+
+	default:
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_UNHANDLED_PROTOCOL);
+		DEBUG_TRACE("Unhandled embedded IP protocol: %u\n", icmp_iph->protocol);
+		return 0;
+	}
+
+	src_ip = icmp_iph->saddr;
+	dest_ip = icmp_iph->daddr;
+
+	rcu_read_lock();
+
+	/*
+	 * Look for a connection match.  Note that we reverse the source and destination
+	 * here because our embedded message contains a packet that was sent in the
+	 * opposite direction to the one in which we just received it.  It will have
+	 * been sent on the interface from which we received it though so that's still
+	 * ok to use.
+	 */
+	cm = sfe_ipv4_find_connection_match_rcu(si, dev, icmp_iph->protocol, dest_ip, dest_port, src_ip, src_port);
+	if (unlikely(!cm)) {
+
+		rcu_read_unlock();
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_ICMP_NO_CONNECTION);
+		DEBUG_TRACE("no connection found\n");
+		return 0;
+	}
+
+	/*
+	 * We found a connection so now remove it from the connection list and flush
+	 * its state.
+	 */
+	c = cm->connection;
+	spin_lock_bh(&si->lock);
+	ret = sfe_ipv4_remove_connection(si, c);
+	spin_unlock_bh(&si->lock);
+
+	if (ret) {
+		sfe_ipv4_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+	}
+	rcu_read_unlock();
+	sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_ICMP_FLUSHED_CONNECTION);
+	return 0;
+}
diff --git a/qca-nss-sfe/sfe_ipv4_icmp.h b/qca-nss-sfe/sfe_ipv4_icmp.h
new file mode 100644
index 0000000..5a79611
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv4_icmp.h
@@ -0,0 +1,22 @@
+/*
+ * sfe_ipv4_icmp.h
+ *	Shortcut forwarding engine - IPv4 ICMP header file
+ *
+ * Copyright (c) 2013-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+int sfe_ipv4_recv_icmp(struct sfe_ipv4 *si, struct sk_buff *skb, struct net_device *dev,
+			      unsigned int len, struct iphdr *iph, unsigned int ihl);
diff --git a/qca-nss-sfe/sfe_ipv4_tcp.c b/qca-nss-sfe/sfe_ipv4_tcp.c
new file mode 100644
index 0000000..b2d5ec9
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv4_tcp.c
@@ -0,0 +1,752 @@
+/*
+ * sfe_ipv4_tcp.c
+ *	Shortcut forwarding engine - IPv4 TCP implementation
+ *
+ * Copyright (c) 2013-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/skbuff.h>
+#include <net/tcp.h>
+#include <linux/etherdevice.h>
+#include <linux/lockdep.h>
+
+#include "sfe_debug.h"
+#include "sfe_api.h"
+#include "sfe.h"
+#include "sfe_flow_cookie.h"
+#include "sfe_ipv4.h"
+#include "sfe_pppoe.h"
+#include "sfe_vlan.h"
+
+/*
+ * sfe_ipv4_process_tcp_option_sack()
+ *	Parse TCP SACK option and update ack according
+ */
+static bool sfe_ipv4_process_tcp_option_sack(const struct tcphdr *th, const u32 data_offs,
+					     u32 *ack)
+{
+	u32 length = sizeof(struct tcphdr);
+	u8 *ptr = (u8 *)th + length;
+
+	/*
+	 * Ignore processing if TCP packet has only TIMESTAMP option.
+	 */
+	if (likely(data_offs == length + TCPOLEN_TIMESTAMP + 1 + 1)
+	    && likely(ptr[0] == TCPOPT_NOP)
+	    && likely(ptr[1] == TCPOPT_NOP)
+	    && likely(ptr[2] == TCPOPT_TIMESTAMP)
+	    && likely(ptr[3] == TCPOLEN_TIMESTAMP)) {
+		return true;
+	}
+
+	/*
+	 * TCP options. Parse SACK option.
+	 */
+	while (length < data_offs) {
+		u8 size;
+		u8 kind;
+
+		ptr = (u8 *)th + length;
+		kind = *ptr;
+
+		/*
+		 * NOP, for padding
+		 * Not in the switch because to fast escape and to not calculate size
+		 */
+		if (kind == TCPOPT_NOP) {
+			length++;
+			continue;
+		}
+
+		if (kind == TCPOPT_SACK) {
+			u32 sack = 0;
+			u8 re = 1 + 1;
+
+			size = *(ptr + 1);
+			if ((size < (1 + 1 + TCPOLEN_SACK_PERBLOCK))
+			    || ((size - (1 + 1)) % (TCPOLEN_SACK_PERBLOCK))
+			    || (size > (data_offs - length))) {
+				return false;
+			}
+
+			re += 4;
+			while (re < size) {
+				u32 sack_re;
+				u8 *sptr = ptr + re;
+				sack_re = (sptr[0] << 24) | (sptr[1] << 16) | (sptr[2] << 8) | sptr[3];
+				if (sack_re > sack) {
+					sack = sack_re;
+				}
+				re += TCPOLEN_SACK_PERBLOCK;
+			}
+			if (sack > *ack) {
+				*ack = sack;
+			}
+			length += size;
+			continue;
+		}
+		if (kind == TCPOPT_EOL) {
+			return true;
+		}
+		size = *(ptr + 1);
+		if (size < 2) {
+			return false;
+		}
+		length += size;
+	}
+
+	return true;
+}
+
+/*
+ * sfe_ipv4_recv_tcp()
+ *	Handle TCP packet receives and forwarding.
+ */
+int sfe_ipv4_recv_tcp(struct sfe_ipv4 *si, struct sk_buff *skb, struct net_device *dev,
+			     unsigned int len, struct iphdr *iph, unsigned int ihl, bool sync_on_find, struct sfe_l2_info *l2_info)
+{
+	struct tcphdr *tcph;
+	__be32 src_ip;
+	__be32 dest_ip;
+	__be16 src_port;
+	__be16 dest_port;
+	struct sfe_ipv4_connection_match *cm;
+	struct sfe_ipv4_connection_match *counter_cm;
+	u8 ttl;
+	u32 flags;
+	struct net_device *xmit_dev;
+	bool ret;
+	bool hw_csum;
+	bool bridge_flow;
+	bool fast_xmit;
+	netdev_features_t features;
+
+	/*
+	 * Is our packet too short to contain a valid TCP header?
+	 */
+	if (unlikely(!pskb_may_pull(skb, (sizeof(struct tcphdr) + ihl)))) {
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_TCP_HEADER_INCOMPLETE);
+		DEBUG_TRACE("packet too short for TCP header\n");
+		return 0;
+	}
+
+	/*
+	 * Read the IP address and port information.  Read the IP header data first
+	 * because we've almost certainly got that in the cache.  We may not yet have
+	 * the TCP header cached though so allow more time for any prefetching.
+	 */
+	src_ip = iph->saddr;
+	dest_ip = iph->daddr;
+
+	tcph = (struct tcphdr *)(skb->data + ihl);
+	src_port = tcph->source;
+	dest_port = tcph->dest;
+	flags = tcp_flag_word(tcph);
+
+	rcu_read_lock();
+
+	/*
+	 * Look for a connection match.
+	 */
+#ifdef CONFIG_NF_FLOW_COOKIE
+	cm = si->sfe_flow_cookie_table[skb->flow_cookie & SFE_FLOW_COOKIE_MASK].match;
+	if (unlikely(!cm)) {
+		cm = sfe_ipv4_find_connection_match_rcu(si, dev, IPPROTO_TCP, src_ip, src_port, dest_ip, dest_port);
+	}
+#else
+	cm = sfe_ipv4_find_connection_match_rcu(si, dev, IPPROTO_TCP, src_ip, src_port, dest_ip, dest_port);
+#endif
+	if (unlikely(!cm)) {
+		/*
+		 * We didn't get a connection but as TCP is connection-oriented that
+		 * may be because this is a non-fast connection (not running established).
+		 * For diagnostic purposes we differentiate this here.
+		 */
+		if (likely((flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK)) == TCP_FLAG_ACK)) {
+
+			rcu_read_unlock();
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_TCP_NO_CONNECTION_FAST_FLAGS);
+			DEBUG_TRACE("no connection found - fast flags\n");
+			return 0;
+		}
+
+		rcu_read_unlock();
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_TCP_NO_CONNECTION_SLOW_FLAGS);
+		DEBUG_TRACE("no connection found - slow flags: 0x%x\n",
+			    flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK));
+		return 0;
+	}
+
+	/*
+	 * Source interface validate.
+	 */
+	if (unlikely((cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK) && (cm->match_dev != dev))) {
+		if (!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK_NO_FLUSH)) {
+			struct sfe_ipv4_connection *c = cm->connection;
+			DEBUG_TRACE("flush on source interface check failure\n");
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv4_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			if (ret) {
+				sfe_ipv4_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+		}
+		rcu_read_unlock();
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_INVALID_SRC_IFACE);
+		DEBUG_TRACE("exception the packet on source interface check failure\n");
+		return 0;
+	}
+
+	/*
+	 * If our packet has beern marked as "flush on find" we can't actually
+	 * forward it in the fast path, but now that we've found an associated
+	 * connection we need sync its status before throw it slow path.
+	 */
+	if (unlikely(sync_on_find)) {
+		sfe_ipv4_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_TCP_IP_OPTIONS_OR_INITIAL_FRAGMENT);
+		DEBUG_TRACE("Sync on find\n");
+		return 0;
+	}
+
+#ifdef CONFIG_XFRM
+	/*
+	 * We can't accelerate the flow on this direction, just let it go
+	 * through the slow path.
+	 */
+	if (unlikely(!cm->flow_accel)) {
+		rcu_read_unlock();
+		this_cpu_inc(si->stats_pcpu->packets_not_forwarded64);
+		return 0;
+	}
+#endif
+
+	/*
+	 * Do we expect an ingress VLAN tag for this flow?
+	 */
+	if (unlikely(!sfe_vlan_validate_ingress_tag(skb, cm->ingress_vlan_hdr_cnt, cm->ingress_vlan_hdr, l2_info))) {
+		rcu_read_unlock();
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_INGRESS_VLAN_TAG_MISMATCH);
+		DEBUG_TRACE("VLAN tag mismatch. skb=%px\n", skb);
+		return 0;
+	}
+
+	bridge_flow = !!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_BRIDGE_FLOW);
+
+	/*
+	 * Does our TTL allow forwarding?
+	 */
+	if (likely(!bridge_flow)) {
+		ttl = iph->ttl;
+		if (unlikely(ttl < 2)) {
+			sfe_ipv4_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+			rcu_read_unlock();
+
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_TCP_SMALL_TTL);
+			DEBUG_TRACE("TTL too low\n");
+			return 0;
+		}
+	}
+
+	/*
+	 * If our packet is larger than the MTU of the transmit interface then
+	 * we can't forward it easily.
+	 */
+	if (unlikely((len > cm->xmit_dev_mtu) && !skb_is_gso(skb))) {
+		sfe_ipv4_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_TCP_IP_OPTIONS_OR_INITIAL_FRAGMENT);
+		DEBUG_TRACE("Larger than MTU\n");
+		return 0;
+	}
+
+	/*
+	 * Look at our TCP flags.  Anything missing an ACK or that has RST, SYN or FIN
+	 * set is not a fast path packet.
+	 */
+	if (unlikely((flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK)) != TCP_FLAG_ACK)) {
+		struct sfe_ipv4_connection *c = cm->connection;
+		spin_lock_bh(&si->lock);
+		ret = sfe_ipv4_remove_connection(si, c);
+		spin_unlock_bh(&si->lock);
+
+		DEBUG_TRACE("TCP flags: 0x%x are not fast\n",
+			    flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK));
+		if (ret) {
+			sfe_ipv4_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+		}
+		rcu_read_unlock();
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_TCP_FLAGS);
+		return 0;
+	}
+
+	counter_cm = cm->counter_match;
+
+	/*
+	 * Are we doing sequence number checking?
+	 */
+	if (likely(!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK))) {
+		u32 seq;
+		u32 ack;
+		u32 sack;
+		u32 data_offs;
+		u32 end;
+		u32 left_edge;
+		u32 scaled_win;
+		u32 max_end;
+
+		/*
+		 * Is our sequence fully past the right hand edge of the window?
+		 */
+		seq = ntohl(tcph->seq);
+		if (unlikely((s32)(seq - (cm->protocol_state.tcp.max_end + 1)) > 0)) {
+			struct sfe_ipv4_connection *c = cm->connection;
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv4_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			DEBUG_TRACE("seq: %u exceeds right edge: %u\n",
+				    seq, cm->protocol_state.tcp.max_end + 1);
+			if (ret) {
+				sfe_ipv4_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+			rcu_read_unlock();
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_TCP_SEQ_EXCEEDS_RIGHT_EDGE);
+			return 0;
+		}
+
+		/*
+		 * Check that our TCP data offset isn't too short.
+		 */
+		data_offs = tcph->doff << 2;
+		if (unlikely(data_offs < sizeof(struct tcphdr))) {
+			struct sfe_ipv4_connection *c = cm->connection;
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv4_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			DEBUG_TRACE("TCP data offset: %u, too small\n", data_offs);
+			if (ret) {
+				sfe_ipv4_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+			rcu_read_unlock();
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_TCP_SMALL_DATA_OFFS);
+			return 0;
+		}
+
+		/*
+		 * Update ACK according to any SACK option.
+		 */
+		ack = ntohl(tcph->ack_seq);
+		sack = ack;
+		if (unlikely(!sfe_ipv4_process_tcp_option_sack(tcph, data_offs, &sack))) {
+			struct sfe_ipv4_connection *c = cm->connection;
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv4_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			DEBUG_TRACE("TCP option SACK size is wrong\n");
+			if (ret) {
+				sfe_ipv4_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+			rcu_read_unlock();
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_TCP_BAD_SACK);
+			return 0;
+		}
+
+		/*
+		 * Check that our TCP data offset isn't past the end of the packet.
+		 */
+		data_offs += sizeof(struct iphdr);
+		if (unlikely(len < data_offs)) {
+			struct sfe_ipv4_connection *c = cm->connection;
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv4_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			DEBUG_TRACE("TCP data offset: %u, past end of packet: %u\n",
+				    data_offs, len);
+			if (ret) {
+				sfe_ipv4_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+			rcu_read_unlock();
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_TCP_BIG_DATA_OFFS);
+			return 0;
+		}
+
+		end = seq + len - data_offs;
+
+		/*
+		 * Is our sequence fully before the left hand edge of the window?
+		 */
+		if (unlikely((s32)(end - (cm->protocol_state.tcp.end
+						- counter_cm->protocol_state.tcp.max_win - 1)) < 0)) {
+			struct sfe_ipv4_connection *c = cm->connection;
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv4_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			DEBUG_TRACE("seq: %u before left edge: %u\n",
+				    end, cm->protocol_state.tcp.end - counter_cm->protocol_state.tcp.max_win - 1);
+			if (ret) {
+				sfe_ipv4_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+			rcu_read_unlock();
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_TCP_SEQ_BEFORE_LEFT_EDGE);
+			return 0;
+		}
+
+		/*
+		 * Are we acking data that is to the right of what has been sent?
+		 */
+		if (unlikely((s32)(sack - (counter_cm->protocol_state.tcp.end + 1)) > 0)) {
+			struct sfe_ipv4_connection *c = cm->connection;
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv4_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			DEBUG_TRACE("ack: %u exceeds right edge: %u\n",
+				    sack, counter_cm->protocol_state.tcp.end + 1);
+			if (ret) {
+				sfe_ipv4_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+			rcu_read_unlock();
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_TCP_ACK_EXCEEDS_RIGHT_EDGE);
+			return 0;
+		}
+
+		/*
+		 * Is our ack too far before the left hand edge of the window?
+		 */
+		left_edge = counter_cm->protocol_state.tcp.end
+			    - cm->protocol_state.tcp.max_win
+			    - SFE_IPV4_TCP_MAX_ACK_WINDOW
+			    - 1;
+		if (unlikely((s32)(sack - left_edge) < 0)) {
+			struct sfe_ipv4_connection *c = cm->connection;
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv4_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			DEBUG_TRACE("ack: %u before left edge: %u\n", sack, left_edge);
+			if (ret) {
+				sfe_ipv4_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+			rcu_read_unlock();
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_TCP_ACK_BEFORE_LEFT_EDGE);
+			return 0;
+		}
+
+		/*
+		 * Have we just seen the largest window size yet for this connection?  If yes
+		 * then we need to record the new value.
+		 */
+		scaled_win = ntohs(tcph->window) << cm->protocol_state.tcp.win_scale;
+		scaled_win += (sack - ack);
+		if (unlikely(cm->protocol_state.tcp.max_win < scaled_win)) {
+			cm->protocol_state.tcp.max_win = scaled_win;
+		}
+
+		/*
+		 * If our sequence and/or ack numbers have advanced then record the new state.
+		 */
+		if (likely((s32)(end - cm->protocol_state.tcp.end) >= 0)) {
+			cm->protocol_state.tcp.end = end;
+		}
+
+		max_end = sack + scaled_win;
+		if (likely((s32)(max_end - counter_cm->protocol_state.tcp.max_end) >= 0)) {
+			counter_cm->protocol_state.tcp.max_end = max_end;
+		}
+	}
+
+	/*
+	 * Check if skb was cloned. If it was, unshare it. Because
+	 * the data area is going to be written in this path and we don't want to
+	 * change the cloned skb's data section.
+	 */
+	if (unlikely(skb_cloned(skb))) {
+		DEBUG_TRACE("%px: skb is a cloned skb\n", skb);
+		skb = skb_unshare(skb, GFP_ATOMIC);
+		if (!skb) {
+			DEBUG_WARN("Failed to unshare the cloned skb\n");
+			rcu_read_unlock();
+			return 0;
+		}
+
+		/*
+		 * Update the iph and tcph pointers with the unshared skb's data area.
+		 */
+		iph = (struct iphdr *)skb->data;
+		tcph = (struct tcphdr *)(skb->data + ihl);
+	}
+
+	/*
+	 * For PPPoE packets, match server MAC and session id
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_PPPOE_DECAP)) {
+		struct pppoe_hdr *ph;
+		struct ethhdr *eth;
+
+		if (unlikely(!sfe_l2_parse_flag_check(l2_info, SFE_L2_PARSE_FLAGS_PPPOE_INGRESS))) {
+			rcu_read_unlock();
+			DEBUG_TRACE("%px: PPPoE header not present in packet for PPPoE rule\n", skb);
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_INCORRECT_PPPOE_PARSING);
+			return 0;
+		}
+
+		ph = (struct pppoe_hdr *)(skb->head + sfe_l2_pppoe_hdr_offset_get(l2_info));
+		eth = (struct ethhdr *)(skb->head + sfe_l2_hdr_offset_get(l2_info));
+		if (unlikely(cm->pppoe_session_id != ntohs(ph->sid)) || unlikely(!(ether_addr_equal((u8*)cm->pppoe_remote_mac, (u8 *)eth->h_source)))) {
+			DEBUG_TRACE("%px: PPPoE sessions with session IDs %d and %d or server MACs %pM and %pM did not match\n",
+							skb, cm->pppoe_session_id, htons(ph->sid), cm->pppoe_remote_mac, eth->h_source);
+			rcu_read_unlock();
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_INVALID_PPPOE_SESSION);
+			return 0;
+		}
+		skb->protocol = htons(l2_info->protocol);
+		this_cpu_inc(si->stats_pcpu->pppoe_decap_packets_forwarded64);
+
+	} else if (unlikely(sfe_l2_parse_flag_check(l2_info, SFE_L2_PARSE_FLAGS_PPPOE_INGRESS))) {
+
+		/*
+		 * If packet contains PPPoE header but CME doesn't contain PPPoE flag yet we are exceptioning the packet to linux
+		 */
+		if (unlikely(!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_BRIDGE_FLOW))) {
+			rcu_read_unlock();
+			DEBUG_TRACE("%px: CME doesn't contain PPPoE flag but packet has PPPoE header\n", skb);
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_PPPOE_NOT_SET_IN_CME);
+			return 0;
+		}
+
+		/*
+		 * For bridged flows when packet contains PPPoE header, restore the header back and forward to xmit interface
+		 */
+		__skb_push(skb, (sizeof(struct pppoe_hdr) + sizeof(struct sfe_ppp_hdr)));
+		l2_info->l2_hdr_size -= (sizeof(struct pppoe_hdr) + sizeof(struct sfe_ppp_hdr));
+		this_cpu_inc(si->stats_pcpu->pppoe_bridge_packets_forwarded64);
+	}
+
+	/*
+	 * Check if skb has enough headroom to write L2 headers
+	 */
+	if (unlikely(skb_headroom(skb) < cm->l2_hdr_size)) {
+		rcu_read_unlock();
+		DEBUG_WARN("%px: Not enough headroom: %u\n", skb, skb_headroom(skb));
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_NO_HEADROOM);
+		return 0;
+	}
+
+	/*
+	 * From this point on we're good to modify the packet.
+	 */
+
+	/*
+	 * For PPPoE flows, add PPPoE header before L2 header is added.
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_PPPOE_ENCAP)) {
+		sfe_pppoe_add_header(skb, cm->pppoe_session_id, PPP_IP);
+		this_cpu_inc(si->stats_pcpu->pppoe_encap_packets_forwarded64);
+	}
+
+	/*
+	 * Apply packet Mark.
+	 * If Mark was set by the Ingress Qdisc that takes precedence over
+	 * flow policy.
+	 */
+	if (likely(skb->mark == 0)) {
+		if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_MARK)) {
+			skb->mark = cm->mark;
+		}
+	}
+
+	/*
+	 * Update DSCP
+	 * DSCP rewrite table takes precedence over flow policy.
+	 */
+	if (unlikely(si->dscp_rewrite_mark_to_match != 0 &&
+		     si->dscp_rewrite_mark_to_match == skb->mark)) {
+		iph->tos = (iph->tos & SFE_IPV4_DSCP_MASK) |
+			si->dscp_rewrite_dscp_to_set;
+	} else if (unlikely(cm->flags &
+			    SFE_IPV4_CONNECTION_MATCH_FLAG_DSCP_REMARK)) {
+		iph->tos = (iph->tos & SFE_IPV4_DSCP_MASK) | cm->dscp;
+	}
+
+	/*
+	 * Decrement our TTL.
+	 */
+	if (likely(!bridge_flow)) {
+		iph->ttl = ttl - 1;
+	}
+
+	/*
+	 * Enable HW csum if rx checksum is verified and xmit interface is CSUM offload capable.
+	 * Note: If L4 csum at Rx was found to be incorrect, we (router) should use incremental L4 checksum here
+	 * so that HW does not re-calculate/replace the L4 csum
+	 */
+	hw_csum = !!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_CSUM_OFFLOAD) && (skb->ip_summed == CHECKSUM_UNNECESSARY);
+
+	/*
+	 * Do we have to perform translations of the source address/port?
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_SRC)) {
+		u16 tcp_csum;
+		u32 sum;
+
+		iph->saddr = cm->xlate_src_ip;
+		tcph->source = cm->xlate_src_port;
+
+		if (unlikely(!hw_csum)) {
+			tcp_csum = tcph->check;
+			if (unlikely(skb->ip_summed == CHECKSUM_PARTIAL)) {
+				sum = tcp_csum + cm->xlate_src_partial_csum_adjustment;
+			} else {
+				sum = tcp_csum + cm->xlate_src_csum_adjustment;
+			}
+
+			sum = (sum & 0xffff) + (sum >> 16);
+			tcph->check = (u16)sum;
+		}
+	}
+
+	/*
+	 * Do we have to perform translations of the destination address/port?
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_DEST)) {
+		u16 tcp_csum;
+		u32 sum;
+
+		iph->daddr = cm->xlate_dest_ip;
+		tcph->dest = cm->xlate_dest_port;
+
+		if (unlikely(!hw_csum)) {
+			tcp_csum = tcph->check;
+			if (unlikely(skb->ip_summed == CHECKSUM_PARTIAL)) {
+				sum = tcp_csum + cm->xlate_dest_partial_csum_adjustment;
+			} else {
+				sum = tcp_csum + cm->xlate_dest_csum_adjustment;
+			}
+
+			sum = (sum & 0xffff) + (sum >> 16);
+			tcph->check = (u16)sum;
+		}
+	}
+
+	/*
+	 * If HW checksum offload is not possible, full L3 checksum and incremental L4 checksum
+	 * are used to update the packet. Setting ip_summed to CHECKSUM_UNNECESSARY ensures checksum is
+	 * not recalculated further in packet path.
+	 */
+	if (likely(hw_csum)) {
+		skb->ip_summed = CHECKSUM_PARTIAL;
+	} else {
+		iph->check = sfe_ipv4_gen_ip_csum(iph);
+		skb->ip_summed = CHECKSUM_UNNECESSARY;
+	}
+
+	/*
+	 * Update traffic stats.
+	 */
+	atomic_inc(&cm->rx_packet_count);
+	atomic_add(len, &cm->rx_byte_count);
+
+	xmit_dev = cm->xmit_dev;
+	skb->dev = xmit_dev;
+
+	/*
+	 * Check to see if we need to add VLAN tags
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_INSERT_EGRESS_VLAN_TAG)) {
+		sfe_vlan_add_tag(skb, cm->egress_vlan_hdr_cnt, cm->egress_vlan_hdr);
+	}
+
+	/*
+	 * Check to see if we need to write an Ethernet header.
+	 */
+	if (likely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_L2_HDR)) {
+		if (unlikely(!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR))) {
+			dev_hard_header(skb, xmit_dev, ntohs(skb->protocol),
+					cm->xmit_dest_mac, cm->xmit_src_mac, len);
+		} else {
+			/*
+			 * For the simple case we write this really fast.
+			 */
+			struct ethhdr *eth = (struct ethhdr *)__skb_push(skb, ETH_HLEN);
+
+			eth->h_proto = skb->protocol;
+
+			ether_addr_copy((u8 *)eth->h_dest, (u8 *)cm->xmit_dest_mac);
+			ether_addr_copy((u8 *)eth->h_source, (u8 *)cm->xmit_src_mac);
+		}
+	}
+
+	/*
+	 * Update priority of skb.
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_PRIORITY_REMARK)) {
+		skb->priority = cm->priority;
+	}
+
+	/*
+	 * For the first packets, check if it could got fast xmit.
+	 */
+	if (unlikely(!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT_FLOW_CHECKED)
+				&& (cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT_DEV_ADMISSION))){
+		cm->features = netif_skb_features(skb);
+		if (likely(sfe_fast_xmit_check(skb, cm->features))) {
+			cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT;
+		}
+		cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT_FLOW_CHECKED;
+	}
+	features = cm->features;
+	fast_xmit = !!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT);
+
+	rcu_read_unlock();
+
+	this_cpu_inc(si->stats_pcpu->packets_forwarded64);
+
+	/*
+	 * We're going to check for GSO flags when we transmit the packet so
+	 * start fetching the necessary cache line now.
+	 */
+	prefetch(skb_shinfo(skb));
+
+	/*
+	 * We do per packet condition check before we could fast xmit the
+	 * packet.
+	 */
+	if (likely(fast_xmit && dev_fast_xmit(skb, xmit_dev, features))) {
+		this_cpu_inc(si->stats_pcpu->packets_fast_xmited64);
+		return 1;
+	}
+
+	/*
+	 * Mark that this packet has been fast forwarded.
+	 */
+	skb->fast_forwarded = 1;
+
+	/*
+	 * Send the packet on its way.
+	 */
+	dev_queue_xmit(skb);
+
+	return 1;
+}
diff --git a/qca-nss-sfe/sfe_ipv4_tcp.h b/qca-nss-sfe/sfe_ipv4_tcp.h
new file mode 100644
index 0000000..b80f367
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv4_tcp.h
@@ -0,0 +1,22 @@
+/*
+ * sfe_ipv4_tcp.h
+ *	Shortcut forwarding engine - IPv4 TCP header file
+ *
+ * Copyright (c) 2013-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+int sfe_ipv4_recv_tcp(struct sfe_ipv4 *si, struct sk_buff *skb, struct net_device *dev,
+			     unsigned int len, struct iphdr *iph, unsigned int ihl, bool sync_on_find, struct sfe_l2_info *l2_info);
diff --git a/qca-nss-sfe/sfe_ipv4_udp.c b/qca-nss-sfe/sfe_ipv4_udp.c
new file mode 100644
index 0000000..4b15f7c
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv4_udp.c
@@ -0,0 +1,596 @@
+/*
+ * sfe_ipv4_udp.c
+ *	Shortcut forwarding engine - IPv4 UDP implementation
+ *
+ * Copyright (c) 2013-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/skbuff.h>
+#include <net/udp.h>
+#include <linux/etherdevice.h>
+#include <linux/lockdep.h>
+#include <linux/version.h>
+
+#include "sfe_debug.h"
+#include "sfe_api.h"
+#include "sfe.h"
+#include "sfe_flow_cookie.h"
+#include "sfe_ipv4.h"
+#include "sfe_pppoe.h"
+#include "sfe_vlan.h"
+
+/*
+ * sfe_ipv4_udp_sk_deliver()
+ *	Deliver the packet to the protocol handler registered with Linux.
+ *	To be called under rcu_read_lock()
+ *	Returns:
+ *	1 if the packet needs to be passed to Linux.
+ *	0 if the packet is processed successfully.
+ *	-1 if the packet is dropped in SFE.
+ */
+static int sfe_ipv4_udp_sk_deliver(struct sk_buff *skb, struct sfe_ipv4_connection_match *cm, unsigned int ihl)
+{
+	struct udp_sock *up;
+	struct sock *sk;
+	int ret;
+	int (*encap_rcv)(struct sock *sk, struct sk_buff *skb);
+
+	/*
+	 * Call the decap handler for valid encap_rcv handler.
+	 */
+	up = rcu_dereference(cm->up);
+	encap_rcv = READ_ONCE(up->encap_rcv);
+	if (!encap_rcv) {
+		DEBUG_ERROR("%px: sfe: Error: up->encap_rcv is NULL\n", skb);
+		return 1;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	nf_reset(skb);
+#else
+	nf_reset_ct(skb);
+#endif
+
+	skb_pull(skb, ihl);
+	skb_reset_transport_header(skb);
+
+	/*
+	 * Verify checksum before giving to encap_rcv handler function.
+	 * TODO: The following approach is ignorant for UDPLITE for now.
+	 * Instead, consider calling Linux API to do checksum validation.
+	 */
+	if (unlikely(skb->ip_summed != CHECKSUM_UNNECESSARY) && unlikely(skb->ip_summed != CHECKSUM_COMPLETE)) {
+		skb->csum = inet_compute_pseudo(skb, IPPROTO_UDP);
+		if (unlikely(__skb_checksum_complete(skb))) {
+			DEBUG_ERROR("%px: sfe: Invalid udp checksum\n", skb);
+			kfree_skb(skb);
+			return -1;
+		}
+		DEBUG_TRACE("%px: sfe: udp checksum verified in s/w correctly.\n", skb);
+	}
+
+	sk = (struct sock *)up;
+
+	/*
+	 * At this point, L4 checksum has already been verified and pkt is going
+	 * to Linux's tunnel decap-handler. Setting ip_summed field to CHECKSUM_NONE,
+	 * to ensure that later packet's inner header checksum is validated correctly.
+	 * TODO: Find the fix to set skb->ip_summed = CHECKSUM_NONE;
+	 */
+
+	/*
+	 * encap_rcv() returns the following value:
+	 * =0 if skb was successfully passed to the encap
+	 *    handler or was discarded by it.
+	 * >0 if skb should be passed on to UDP.
+	 * <0 if skb should be resubmitted as proto -N
+	 */
+	ret = encap_rcv(sk, skb);
+	if (unlikely(ret)) {
+		/*
+		 * If encap_rcv fails, vxlan driver drops the packet.
+		 * No need to free the skb here.
+		 */
+
+		DEBUG_ERROR("%px: sfe: udp-decap API return error: %d\n", skb, ret);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * sfe_ipv4_recv_udp()
+ *	Handle UDP packet receives and forwarding.
+ */
+int sfe_ipv4_recv_udp(struct sfe_ipv4 *si, struct sk_buff *skb, struct net_device *dev,
+			     unsigned int len, struct iphdr *iph, unsigned int ihl,
+			     bool sync_on_find, struct sfe_l2_info *l2_info, bool tun_outer)
+{
+	struct udphdr *udph;
+	__be32 src_ip;
+	__be32 dest_ip;
+	__be16 src_port;
+	__be16 dest_port;
+	struct sfe_ipv4_connection_match *cm;
+	u8 ttl;
+	struct net_device *xmit_dev;
+	bool hw_csum;
+	int err;
+	bool bridge_flow;
+	int ret;
+	bool fast_xmit;
+	netdev_features_t features;
+
+	/*
+	 * Is our packet too short to contain a valid UDP header?
+	 */
+	if (unlikely(!pskb_may_pull(skb, (sizeof(struct udphdr) + ihl)))) {
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_UDP_HEADER_INCOMPLETE);
+		DEBUG_TRACE("%px: packet too short for UDP header\n", skb);
+		return 0;
+	}
+
+	/*
+	 * Read the IP address and port information.  Read the IP header data first
+	 * because we've almost certainly got that in the cache.  We may not yet have
+	 * the UDP header cached though so allow more time for any prefetching.
+	 */
+	src_ip = iph->saddr;
+	dest_ip = iph->daddr;
+
+	udph = (struct udphdr *)(skb->data + ihl);
+	src_port = udph->source;
+	dest_port = udph->dest;
+
+	rcu_read_lock();
+
+	/*
+	 * Look for a connection match.
+	 */
+#ifdef CONFIG_NF_FLOW_COOKIE
+	cm = si->sfe_flow_cookie_table[skb->flow_cookie & SFE_FLOW_COOKIE_MASK].match;
+	if (unlikely(!cm)) {
+		cm = sfe_ipv4_find_connection_match_rcu(si, dev, IPPROTO_UDP, src_ip, src_port, dest_ip, dest_port);
+	}
+#else
+	/*
+	 * 5-tuple lookup for UDP flow.
+	 */
+	cm = sfe_ipv4_find_connection_match_rcu(si, dev, IPPROTO_UDP, src_ip, src_port, dest_ip, dest_port);
+#endif
+	if (unlikely(!cm)) {
+
+		/*
+		 * try a 4-tuple lookup; required for tunnels like vxlan.
+		 */
+		cm = sfe_ipv4_find_connection_match_rcu(si, dev, IPPROTO_UDP, src_ip, 0, dest_ip, dest_port);
+		if (unlikely(!cm)) {
+			rcu_read_unlock();
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_UDP_NO_CONNECTION);
+			DEBUG_TRACE("%px: sfe: no connection found in 4-tuple lookup.\n", skb);
+			return 0;
+		}
+	}
+
+	/*
+	 * Source interface validate.
+	 */
+	if (unlikely((cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK) && (cm->match_dev != dev))) {
+		if (!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK_NO_FLUSH)) {
+			struct sfe_ipv4_connection *c = cm->connection;
+			DEBUG_TRACE("flush on source interface check failure\n");
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv4_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			if (ret) {
+				sfe_ipv4_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+		}
+		rcu_read_unlock();
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_INVALID_SRC_IFACE);
+		DEBUG_TRACE("exception the packet on source interface check failure\n");
+		return 0;
+	}
+
+	/*
+	 * If our packet has beern marked as "flush on find" we can't actually
+	 * forward it in the fast path, but now that we've found an associated
+	 * connection we need sync its status before exception it to slow path.
+	 */
+	if (unlikely(sync_on_find)) {
+		sfe_ipv4_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_UDP_IP_OPTIONS_OR_INITIAL_FRAGMENT);
+		DEBUG_TRACE("%px: sfe: sync on find\n", cm);
+		return 0;
+	}
+
+#ifdef CONFIG_XFRM
+	/*
+	 * We can't accelerate the flow on this direction, just let it go
+	 * through the slow path.
+	 */
+	if (unlikely(!cm->flow_accel)) {
+		rcu_read_unlock();
+		this_cpu_inc(si->stats_pcpu->packets_not_forwarded64);
+		return 0;
+	}
+#endif
+
+	/*
+	 * Do we expect an ingress VLAN tag for this flow?
+	 */
+	if (unlikely(!sfe_vlan_validate_ingress_tag(skb, cm->ingress_vlan_hdr_cnt, cm->ingress_vlan_hdr, l2_info))) {
+		rcu_read_unlock();
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_INGRESS_VLAN_TAG_MISMATCH);
+		DEBUG_TRACE("VLAN tag mismatch. skb=%px\n", skb);
+		return 0;
+	}
+
+	bridge_flow = !!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_BRIDGE_FLOW);
+
+	/*
+	 * Does our TTL allow forwarding?
+	 */
+	if (likely(!bridge_flow)) {
+		ttl = iph->ttl;
+		if (unlikely(ttl < 2)) {
+			sfe_ipv4_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+			rcu_read_unlock();
+
+			DEBUG_TRACE("%px: sfe: TTL too low\n", skb);
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_UDP_SMALL_TTL);
+			return 0;
+		}
+	}
+
+	/*
+	 * If our packet is larger than the MTU of the transmit interface then
+	 * we can't forward it easily.
+	 */
+	if (unlikely(len > cm->xmit_dev_mtu)) {
+		sfe_ipv4_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_UDP_NEEDS_FRAGMENTATION);
+		DEBUG_TRACE("%px: sfe: larger than MTU\n", cm);
+		return 0;
+	}
+
+	/*
+	 * Check if skb was cloned. If it was, unshare it. Because
+	 * the data area is going to be written in this path and we don't want to
+	 * change the cloned skb's data section.
+	 */
+	if (unlikely(skb_cloned(skb))) {
+		DEBUG_TRACE("%px: skb is a cloned skb\n", skb);
+		skb = skb_unshare(skb, GFP_ATOMIC);
+		if (!skb) {
+			DEBUG_WARN("%px: Failed to unshare the cloned skb\n", skb);
+			rcu_read_unlock();
+			return 0;
+		}
+
+		/*
+		 * Update the iph and udph pointers with the unshared skb's data area.
+		 */
+		iph = (struct iphdr *)skb->data;
+		udph = (struct udphdr *)(skb->data + ihl);
+	}
+
+	/*
+	 * For PPPoE packets, match server MAC and session id
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_PPPOE_DECAP)) {
+		struct pppoe_hdr *ph;
+		struct ethhdr *eth;
+
+		if (unlikely(!sfe_l2_parse_flag_check(l2_info, SFE_L2_PARSE_FLAGS_PPPOE_INGRESS))) {
+			rcu_read_unlock();
+			DEBUG_TRACE("%px: PPPoE header not present in packet for PPPoE rule\n", skb);
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_INCORRECT_PPPOE_PARSING);
+			return 0;
+		}
+
+		ph = (struct pppoe_hdr *)(skb->head + sfe_l2_pppoe_hdr_offset_get(l2_info));
+		eth = (struct ethhdr *)(skb->head + sfe_l2_hdr_offset_get(l2_info));
+		if (unlikely(cm->pppoe_session_id != ntohs(ph->sid)) || unlikely(!(ether_addr_equal((u8*)cm->pppoe_remote_mac, (u8 *)eth->h_source)))) {
+			DEBUG_TRACE("%px: PPPoE sessions with session IDs %d and %d or server MACs %pM and %pM did not match\n",
+							skb, cm->pppoe_session_id, htons(ph->sid), cm->pppoe_remote_mac, eth->h_source);
+			rcu_read_unlock();
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_INVALID_PPPOE_SESSION);
+			return 0;
+		}
+		skb->protocol = htons(l2_info->protocol);
+		this_cpu_inc(si->stats_pcpu->pppoe_decap_packets_forwarded64);
+
+	} else if (unlikely(sfe_l2_parse_flag_check(l2_info, SFE_L2_PARSE_FLAGS_PPPOE_INGRESS))) {
+
+		/*
+		 * If packet contains PPPoE header but CME doesn't contain PPPoE flag yet we are exceptioning the packet to linux
+		 */
+		if (unlikely(!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_BRIDGE_FLOW))) {
+			rcu_read_unlock();
+			DEBUG_TRACE("%px: CME doesn't contain PPPoE flag but packet has PPPoE header\n", skb);
+			sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_PPPOE_NOT_SET_IN_CME);
+			return 0;
+
+		}
+
+		/*
+		 * For bridged flows when packet contains PPPoE header, restore the header back and forward to xmit interface
+		 */
+		__skb_push(skb, (sizeof(struct pppoe_hdr) + sizeof(struct sfe_ppp_hdr)));
+		l2_info->l2_hdr_size -= (sizeof(struct pppoe_hdr) + sizeof(struct sfe_ppp_hdr));
+		this_cpu_inc(si->stats_pcpu->pppoe_bridge_packets_forwarded64);
+	}
+
+	/*
+	 * Check if skb has enough headroom to write L2 headers
+	 */
+	if (unlikely(skb_headroom(skb) < cm->l2_hdr_size)) {
+		rcu_read_unlock();
+		DEBUG_WARN("%px: Not enough headroom: %u\n", skb, skb_headroom(skb));
+		sfe_ipv4_exception_stats_inc(si, SFE_IPV4_EXCEPTION_EVENT_NO_HEADROOM);
+		return 0;
+	}
+
+	/*
+	 * From this point on we're good to modify the packet.
+	 */
+
+	/*
+	 * For PPPoE flows, add PPPoE header before L2 header is added.
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_PPPOE_ENCAP)) {
+		sfe_pppoe_add_header(skb, cm->pppoe_session_id, PPP_IP);
+		this_cpu_inc(si->stats_pcpu->pppoe_encap_packets_forwarded64);
+	}
+
+	/*
+	 * Enable HW csum if rx checksum is verified and xmit interface is CSUM offload capable.
+	 * Note: If L4 csum at Rx was found to be incorrect, we (router) should use incremental L4 checksum here
+	 * so that HW does not re-calculate/replace the L4 csum
+	 */
+	hw_csum = !!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_CSUM_OFFLOAD) && (skb->ip_summed == CHECKSUM_UNNECESSARY);
+
+	/*
+	 * Do we have to perform translations of the source address/port?
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_SRC)) {
+		u16 udp_csum;
+
+		iph->saddr = cm->xlate_src_ip;
+		udph->source = cm->xlate_src_port;
+
+		/*
+		 * Do we have a non-zero UDP checksum?  If we do then we need
+		 * to update it.
+		 */
+		if (unlikely(!hw_csum)) {
+			udp_csum = udph->check;
+			if (likely(udp_csum)) {
+				u32 sum;
+
+				if (unlikely(skb->ip_summed == CHECKSUM_PARTIAL)) {
+					sum = udp_csum + cm->xlate_src_partial_csum_adjustment;
+				} else {
+					sum = udp_csum + cm->xlate_src_csum_adjustment;
+				}
+
+				sum = (sum & 0xffff) + (sum >> 16);
+				udph->check = (u16)sum;
+			}
+		}
+	}
+
+	/*
+	 * Do we have to perform translations of the destination address/port?
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_DEST)) {
+		u16 udp_csum;
+
+		iph->daddr = cm->xlate_dest_ip;
+		udph->dest = cm->xlate_dest_port;
+
+		/*
+		 * Do we have a non-zero UDP checksum?  If we do then we need
+		 * to update it.
+		 */
+		if (unlikely(!hw_csum)) {
+			udp_csum = udph->check;
+			if (likely(udp_csum)) {
+				u32 sum;
+
+				/*
+				 * TODO: Use a common API for below incremental checksum calculation
+				 * for IPv4/IPv6 UDP/TCP
+				 */
+				if (unlikely(skb->ip_summed == CHECKSUM_PARTIAL)) {
+					sum = udp_csum + cm->xlate_dest_partial_csum_adjustment;
+				} else {
+					sum = udp_csum + cm->xlate_dest_csum_adjustment;
+				}
+
+				sum = (sum & 0xffff) + (sum >> 16);
+				udph->check = (u16)sum;
+			}
+		}
+	}
+
+	/*
+	 * UDP sock will be valid only in decap-path.
+	 * Call encap_rcv function associated with udp_sock in cm.
+	 */
+	if (unlikely(cm->up)) {
+		/*
+		 * Call decap handler associated with sock.
+		 * Also validates UDP checksum before calling decap handler.
+		 */
+		err = sfe_ipv4_udp_sk_deliver(skb, cm, ihl);
+		if (unlikely(err == -1)) {
+			rcu_read_unlock();
+			this_cpu_inc(si->stats_pcpu->packets_dropped64);
+			return 1;
+		} else if (unlikely(err == 1)) {
+			rcu_read_unlock();
+			this_cpu_inc(si->stats_pcpu->packets_not_forwarded64);
+			return 0;
+		}
+
+		/*
+		 * Update traffic stats.
+		 */
+		atomic_inc(&cm->rx_packet_count);
+		atomic_add(len, &cm->rx_byte_count);
+
+		rcu_read_unlock();
+		this_cpu_inc(si->stats_pcpu->packets_forwarded64);
+		DEBUG_TRACE("%px: sfe: sfe_ipv4_recv_udp -> encap_rcv done.\n", skb);
+		return 1;
+	}
+
+	/*
+	 * Decrement our TTL
+	 * Except when called from hook function in post-decap.
+	 */
+	if (likely(!bridge_flow)) {
+		iph->ttl -= (u8)(!tun_outer);
+	}
+
+	/*
+	 * Apply packet Mark.
+	 * If Mark was set by the Ingress Qdisc that takes precedence over
+	 * flow policy.
+	 */
+	if (likely(skb->mark == 0)) {
+		if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_MARK)) {
+			skb->mark = cm->mark;
+		}
+	}
+
+	/*
+	 * Update DSCP
+	 * DSCP rewrite table takes precedence over flow policy.
+	 */
+	if (unlikely(si->dscp_rewrite_mark_to_match != 0 &&
+		     si->dscp_rewrite_mark_to_match == skb->mark)) {
+		iph->tos = (iph->tos & SFE_IPV4_DSCP_MASK) |
+			si->dscp_rewrite_dscp_to_set;
+	} else if (unlikely(cm->flags &
+			    SFE_IPV4_CONNECTION_MATCH_FLAG_DSCP_REMARK)) {
+		iph->tos = (iph->tos & SFE_IPV4_DSCP_MASK) | cm->dscp;
+	}
+
+	/*
+	 * If HW checksum offload is not possible, full L3 checksum and incremental L4 checksum
+	 * are used to update the packet. Setting ip_summed to CHECKSUM_UNNECESSARY ensures checksum is
+	 * not recalculated further in packet path.
+	 */
+	if (likely(hw_csum)) {
+		skb->ip_summed = CHECKSUM_PARTIAL;
+	} else {
+		iph->check = sfe_ipv4_gen_ip_csum(iph);
+	}
+
+	/*
+	 * Update traffic stats.
+	 */
+	atomic_inc(&cm->rx_packet_count);
+	atomic_add(len, &cm->rx_byte_count);
+
+	xmit_dev = cm->xmit_dev;
+	skb->dev = xmit_dev;
+
+	/*
+	 * Check to see if we need to add VLAN tags
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_INSERT_EGRESS_VLAN_TAG)) {
+		sfe_vlan_add_tag(skb, cm->egress_vlan_hdr_cnt, cm->egress_vlan_hdr);
+	}
+
+	/*
+	 * Check to see if we need to write an Ethernet header.
+	 */
+	if (likely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_L2_HDR)) {
+		if (unlikely(!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR))) {
+			dev_hard_header(skb, xmit_dev, ntohs(skb->protocol),
+					cm->xmit_dest_mac, cm->xmit_src_mac, len);
+		} else {
+			/*
+			 * For the simple case we write this really fast.
+			 */
+			struct ethhdr *eth = (struct ethhdr *)__skb_push(skb, ETH_HLEN);
+			eth->h_proto = skb->protocol;
+			ether_addr_copy((u8 *)eth->h_dest, (u8 *)cm->xmit_dest_mac);
+			ether_addr_copy((u8 *)eth->h_source, (u8 *)cm->xmit_src_mac);
+		}
+	}
+
+	/*
+	 * Update priority of skb.
+	 */
+	if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_PRIORITY_REMARK)) {
+		skb->priority = cm->priority;
+	}
+
+	/*
+	 * For the first packets, check if it could got fast xmit.
+	 */
+	if (unlikely(!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT_FLOW_CHECKED)
+				&& (cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT_DEV_ADMISSION))){
+		cm->features = netif_skb_features(skb);
+		if (likely(sfe_fast_xmit_check(skb, cm->features))) {
+			cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT;
+		}
+		cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT_FLOW_CHECKED;
+	}
+	features = cm->features;
+
+	fast_xmit = !!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_FAST_XMIT);
+
+	rcu_read_unlock();
+
+	this_cpu_inc(si->stats_pcpu->packets_forwarded64);
+
+	/*
+	 * We're going to check for GSO flags when we transmit the packet so
+	 * start fetching the necessary cache line now.
+	 */
+	prefetch(skb_shinfo(skb));
+
+	/*
+	 * We do per packet condition check before we could fast xmit the
+	 * packet.
+	 */
+	if (likely(fast_xmit && dev_fast_xmit(skb, xmit_dev, features))) {
+		this_cpu_inc(si->stats_pcpu->packets_fast_xmited64);
+		return 1;
+	}
+
+	/*
+	 * Mark that this packet has been fast forwarded.
+	 */
+	skb->fast_forwarded = 1;
+
+	/*
+	 * Send the packet on its way.
+	 */
+	dev_queue_xmit(skb);
+
+	return 1;
+}
diff --git a/qca-nss-sfe/sfe_ipv4_udp.h b/qca-nss-sfe/sfe_ipv4_udp.h
new file mode 100644
index 0000000..d7c5e6b
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv4_udp.h
@@ -0,0 +1,22 @@
+/*
+ * sfe_ipv4_udp.h
+ *	Shortcut forwarding engine - IPv4 UDP header file
+ *
+ * Copyright (c) 2013-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+int sfe_ipv4_recv_udp(struct sfe_ipv4 *si, struct sk_buff *skb, struct net_device *dev,
+			     unsigned int len, struct iphdr *iph, unsigned int ihl, bool sync_on_find,
+			     struct sfe_l2_info *l2_info, bool tun_outer);
diff --git a/qca-nss-sfe/sfe_ipv6.c b/qca-nss-sfe/sfe_ipv6.c
new file mode 100644
index 0000000..a3ac446
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv6.c
@@ -0,0 +1,2789 @@
+/*
+ * sfe_ipv6.c
+ *	Shortcut forwarding engine - IPv6 support.
+ *
+ * Copyright (c) 2015-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/module.h>
+#include <linux/sysfs.h>
+#include <linux/skbuff.h>
+#include <linux/icmp.h>
+#include <net/tcp.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#include <net/udp.h>
+#include <net/vxlan.h>
+#include <linux/refcount.h>
+#include <linux/netfilter.h>
+#include <linux/inetdevice.h>
+#include <linux/netfilter_ipv6.h>
+#include <net/protocol.h>
+#include <net/addrconf.h>
+#include <net/gre.h>
+
+#include "sfe_debug.h"
+#include "sfe_api.h"
+#include "sfe.h"
+#include "sfe_flow_cookie.h"
+#include "sfe_ipv6.h"
+#include "sfe_ipv6_udp.h"
+#include "sfe_ipv6_tcp.h"
+#include "sfe_ipv6_icmp.h"
+#include "sfe_pppoe.h"
+#include "sfe_ipv6_tunipip6.h"
+#include "sfe_ipv6_gre.h"
+
+#define sfe_ipv6_addr_copy(src, dest) memcpy((void *)(dest), (void *)(src), 16)
+
+static char *sfe_ipv6_exception_events_string[SFE_IPV6_EXCEPTION_EVENT_LAST] = {
+	"UDP_HEADER_INCOMPLETE",
+	"UDP_NO_CONNECTION",
+	"UDP_IP_OPTIONS_OR_INITIAL_FRAGMENT",
+	"UDP_SMALL_TTL",
+	"UDP_NEEDS_FRAGMENTATION",
+	"TCP_HEADER_INCOMPLETE",
+	"TCP_NO_CONNECTION_SLOW_FLAGS",
+	"TCP_NO_CONNECTION_FAST_FLAGS",
+	"TCP_IP_OPTIONS_OR_INITIAL_FRAGMENT",
+	"TCP_SMALL_TTL",
+	"TCP_NEEDS_FRAGMENTATION",
+	"TCP_FLAGS",
+	"TCP_SEQ_EXCEEDS_RIGHT_EDGE",
+	"TCP_SMALL_DATA_OFFS",
+	"TCP_BAD_SACK",
+	"TCP_BIG_DATA_OFFS",
+	"TCP_SEQ_BEFORE_LEFT_EDGE",
+	"TCP_ACK_EXCEEDS_RIGHT_EDGE",
+	"TCP_ACK_BEFORE_LEFT_EDGE",
+	"ICMP_HEADER_INCOMPLETE",
+	"ICMP_UNHANDLED_TYPE",
+	"ICMP_IPV6_HEADER_INCOMPLETE",
+	"ICMP_IPV6_NON_V6",
+	"ICMP_IPV6_IP_OPTIONS_INCOMPLETE",
+	"ICMP_IPV6_UDP_HEADER_INCOMPLETE",
+	"ICMP_IPV6_TCP_HEADER_INCOMPLETE",
+	"ICMP_IPV6_UNHANDLED_PROTOCOL",
+	"ICMP_NO_CONNECTION",
+	"ICMP_FLUSHED_CONNECTION",
+	"HEADER_INCOMPLETE",
+	"BAD_TOTAL_LENGTH",
+	"NON_V6",
+	"NON_INITIAL_FRAGMENT",
+	"DATAGRAM_INCOMPLETE",
+	"IP_OPTIONS_INCOMPLETE",
+	"UNHANDLED_PROTOCOL",
+	"FLOW_COOKIE_ADD_FAIL",
+	"NO_HEADROOM",
+	"INVALID_PPPOE_SESSION",
+	"INCORRECT_PPPOE_PARSING",
+	"PPPOE_NOT_SET_IN_CME",
+	"INGRESS_VLAN_TAG_MISMATCH",
+	"INVALID_SOURCE_INTERFACE",
+	"TUNIPIP6_HEADER_INCOMPLETE",
+	"TUNIPIP6_NO_CONNECTION",
+	"TUNIPIP6_IP_OPTIONS_OR_INITIAL_FRAGMENT",
+	"TUNIPIP6_SMALL_TTL",
+	"TUNIPIP6_NEEDS_FRAGMENTATION",
+	"TUNIPIP6_SYNC_ON_FIND",
+	"GRE_HEADER_INCOMPLETE",
+	"GRE_NO_CONNECTION",
+	"GRE_IP_OPTIONS_OR_INITIAL_FRAGMENT",
+	"GRE_SMALL_TTL",
+	"GRE_NEEDS_FRAGMENTATION"
+};
+
+static struct sfe_ipv6 __si6;
+
+/*
+ * sfe_ipv6_get_debug_dev()
+ */
+static ssize_t sfe_ipv6_get_debug_dev(struct device *dev, struct device_attribute *attr, char *buf);
+
+/*
+ * sysfs attributes.
+ */
+static const struct device_attribute sfe_ipv6_debug_dev_attr =
+	__ATTR(debug_dev, S_IWUSR | S_IRUGO, sfe_ipv6_get_debug_dev, NULL);
+
+/*
+ * sfe_ipv6_get_connection_match_hash()
+ *	Generate the hash used in connection match lookups.
+ */
+static inline unsigned int sfe_ipv6_get_connection_match_hash(struct net_device *dev, u8 protocol,
+							      struct sfe_ipv6_addr *src_ip, __be16 src_port,
+							      struct sfe_ipv6_addr *dest_ip, __be16 dest_port)
+{
+	u32 idx, hash = 0;
+
+	for (idx = 0; idx < 4; idx++) {
+		hash ^= src_ip->addr[idx] ^ dest_ip->addr[idx];
+	}
+	hash =  hash ^ protocol ^ ntohs(src_port ^ dest_port);
+	return ((hash >> SFE_IPV6_CONNECTION_HASH_SHIFT) ^ hash) & SFE_IPV6_CONNECTION_HASH_MASK;
+}
+
+/*
+ * sfe_ipv6_find_connection_match_rcu()
+ *	Get the IPv6 flow match info that corresponds to a particular 5-tuple.
+ */
+struct sfe_ipv6_connection_match *
+sfe_ipv6_find_connection_match_rcu(struct sfe_ipv6 *si, struct net_device *dev, u8 protocol,
+					struct sfe_ipv6_addr *src_ip, __be16 src_port,
+					struct sfe_ipv6_addr *dest_ip, __be16 dest_port)
+{
+	struct sfe_ipv6_connection_match *cm = NULL;
+	unsigned int conn_match_idx;
+	struct hlist_head *lhead;
+	WARN_ON_ONCE(!rcu_read_lock_held());
+
+	conn_match_idx = sfe_ipv6_get_connection_match_hash(dev, protocol, src_ip, src_port, dest_ip, dest_port);
+
+	lhead = &si->hlist_conn_match_hash_head[conn_match_idx];
+
+	/*
+	 * Hopefully the first entry is the one we want.
+	 */
+	hlist_for_each_entry_rcu(cm, lhead, hnode) {
+		if ((cm->match_dest_port != dest_port) ||
+		    (cm->match_src_port != src_port) ||
+		    (!sfe_ipv6_addr_equal(cm->match_src_ip, src_ip)) ||
+		    (!sfe_ipv6_addr_equal(cm->match_dest_ip, dest_ip)) ||
+		    (cm->match_protocol != protocol) ||
+		    (cm->match_dev != dev)) {
+			continue;
+		}
+
+		this_cpu_inc(si->stats_pcpu->connection_match_hash_hits64);
+
+		break;
+
+	}
+
+	return cm;
+}
+
+/*
+ * sfe_ipv6_connection_match_update_summary_stats()
+ *	Update the summary stats for a connection match entry.
+ */
+static inline void sfe_ipv6_connection_match_update_summary_stats(struct sfe_ipv6_connection_match *cm,
+                                               u32 *packets, u32 *bytes)
+
+{
+	u32 packet_count, byte_count;
+
+	packet_count = atomic_read(&cm->rx_packet_count);
+	cm->rx_packet_count64 += packet_count;
+	atomic_sub(packet_count, &cm->rx_packet_count);
+
+	byte_count = atomic_read(&cm->rx_byte_count);
+	cm->rx_byte_count64 += byte_count;
+	atomic_sub(byte_count, &cm->rx_byte_count);
+
+	*packets = packet_count;
+	*bytes = byte_count;
+}
+
+/*
+ * sfe_ipv6_connection_match_compute_translations()
+ *	Compute port and address translations for a connection match entry.
+ */
+static void sfe_ipv6_connection_match_compute_translations(struct sfe_ipv6_connection_match *cm)
+{
+	u32 diff[9];
+	u32 *idx_32;
+	u16 *idx_16;
+
+	/*
+	 * Before we insert the entry look to see if this is tagged as doing address
+	 * translations.  If it is then work out the adjustment that we need to apply
+	 * to the transport checksum.
+	 */
+	if (cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_SRC) {
+		u32 adj = 0;
+		u32 carry = 0;
+
+		/*
+		 * Precompute an incremental checksum adjustment so we can
+		 * edit packets in this stream very quickly.  The algorithm is from RFC1624.
+		 */
+		idx_32 = diff;
+		*(idx_32++) = cm->match_src_ip[0].addr[0];
+		*(idx_32++) = cm->match_src_ip[0].addr[1];
+		*(idx_32++) = cm->match_src_ip[0].addr[2];
+		*(idx_32++) = cm->match_src_ip[0].addr[3];
+
+		idx_16 = (u16 *)idx_32;
+		*(idx_16++) = cm->match_src_port;
+		*(idx_16++) = ~cm->xlate_src_port;
+		idx_32 = (u32 *)idx_16;
+
+		*(idx_32++) = ~cm->xlate_src_ip[0].addr[0];
+		*(idx_32++) = ~cm->xlate_src_ip[0].addr[1];
+		*(idx_32++) = ~cm->xlate_src_ip[0].addr[2];
+		*(idx_32++) = ~cm->xlate_src_ip[0].addr[3];
+
+		/*
+		 * When we compute this fold it down to a 16-bit offset
+		 * as that way we can avoid having to do a double
+		 * folding of the twos-complement result because the
+		 * addition of 2 16-bit values cannot cause a double
+		 * wrap-around!
+		 */
+		for (idx_32 = diff; idx_32 < diff + 9; idx_32++) {
+			u32 w = *idx_32;
+			adj += carry;
+			adj += w;
+			carry = (w > adj);
+		}
+		adj += carry;
+		adj = (adj & 0xffff) + (adj >> 16);
+		adj = (adj & 0xffff) + (adj >> 16);
+		cm->xlate_src_csum_adjustment = (u16)adj;
+	}
+
+	if (cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_DEST) {
+		u32 adj = 0;
+		u32 carry = 0;
+
+		/*
+		 * Precompute an incremental checksum adjustment so we can
+		 * edit packets in this stream very quickly.  The algorithm is from RFC1624.
+		 */
+		idx_32 = diff;
+		*(idx_32++) = cm->match_dest_ip[0].addr[0];
+		*(idx_32++) = cm->match_dest_ip[0].addr[1];
+		*(idx_32++) = cm->match_dest_ip[0].addr[2];
+		*(idx_32++) = cm->match_dest_ip[0].addr[3];
+
+		idx_16 = (u16 *)idx_32;
+		*(idx_16++) = cm->match_dest_port;
+		*(idx_16++) = ~cm->xlate_dest_port;
+		idx_32 = (u32 *)idx_16;
+
+		*(idx_32++) = ~cm->xlate_dest_ip[0].addr[0];
+		*(idx_32++) = ~cm->xlate_dest_ip[0].addr[1];
+		*(idx_32++) = ~cm->xlate_dest_ip[0].addr[2];
+		*(idx_32++) = ~cm->xlate_dest_ip[0].addr[3];
+
+		/*
+		 * When we compute this fold it down to a 16-bit offset
+		 * as that way we can avoid having to do a double
+		 * folding of the twos-complement result because the
+		 * addition of 2 16-bit values cannot cause a double
+		 * wrap-around!
+		 */
+		for (idx_32 = diff; idx_32 < diff + 9; idx_32++) {
+			u32 w = *idx_32;
+			adj += carry;
+			adj += w;
+			carry = (w > adj);
+		}
+		adj += carry;
+		adj = (adj & 0xffff) + (adj >> 16);
+		adj = (adj & 0xffff) + (adj >> 16);
+		cm->xlate_dest_csum_adjustment = (u16)adj;
+	}
+}
+
+/*
+ * sfe_ipv6_update_summary_stats()
+ *	Update the summary stats.
+ */
+static void sfe_ipv6_update_summary_stats(struct sfe_ipv6 *si, struct sfe_ipv6_stats *stats)
+{
+	int i = 0;
+
+	memset(stats, 0, sizeof(*stats));
+
+	for_each_possible_cpu(i) {
+		const struct sfe_ipv6_stats *s = per_cpu_ptr(si->stats_pcpu, i);
+
+		stats->connection_create_requests64 += s->connection_create_requests64;
+		stats->connection_create_collisions64 += s->connection_create_collisions64;
+		stats->connection_create_failures64 += s->connection_create_failures64;
+		stats->connection_destroy_requests64 += s->connection_destroy_requests64;
+		stats->connection_destroy_misses64 += s->connection_destroy_misses64;
+		stats->connection_match_hash_hits64 += s->connection_match_hash_hits64;
+		stats->connection_match_hash_reorders64 += s->connection_match_hash_reorders64;
+		stats->connection_flushes64 += s->connection_flushes64;
+		stats->packets_dropped64 += s->packets_dropped64;
+		stats->packets_forwarded64 += s->packets_forwarded64;
+		stats->packets_fast_xmited64 += s->packets_fast_xmited64;
+		stats->packets_not_forwarded64 += s->packets_not_forwarded64;
+		stats->pppoe_encap_packets_forwarded64 += s->pppoe_encap_packets_forwarded64;
+		stats->pppoe_decap_packets_forwarded64 += s->pppoe_decap_packets_forwarded64;
+		stats->pppoe_bridge_packets_forwarded64 += s->pppoe_bridge_packets_forwarded64;
+	}
+}
+
+/*
+ * sfe_ipv6_insert_connection_match()
+ *	Insert a connection match into the hash.
+ *
+ * On entry we must be holding the lock that protects the hash table.
+ */
+static inline void sfe_ipv6_insert_connection_match(struct sfe_ipv6 *si,
+						    struct sfe_ipv6_connection_match *cm)
+{
+	unsigned int conn_match_idx
+		= sfe_ipv6_get_connection_match_hash(cm->match_dev, cm->match_protocol,
+						     cm->match_src_ip, cm->match_src_port,
+						     cm->match_dest_ip, cm->match_dest_port);
+
+	lockdep_assert_held(&si->lock);
+
+	hlist_add_head_rcu(&cm->hnode, &si->hlist_conn_match_hash_head[conn_match_idx]);
+#ifdef CONFIG_NF_FLOW_COOKIE
+	if (!si->flow_cookie_enable || !(cm->flags & (SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_SRC | SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_DEST)))
+		return;
+
+	/*
+	 * Configure hardware to put a flow cookie in packet of this flow,
+	 * then we can accelerate the lookup process when we received this packet.
+	 */
+	for (conn_match_idx = 1; conn_match_idx < SFE_FLOW_COOKIE_SIZE; conn_match_idx++) {
+		struct sfe_ipv6_flow_cookie_entry *entry = &si->sfe_flow_cookie_table[conn_match_idx];
+
+		if ((NULL == entry->match) && time_is_before_jiffies(entry->last_clean_time + HZ)) {
+			sfe_ipv6_flow_cookie_set_func_t func;
+
+			rcu_read_lock();
+			func = rcu_dereference(si->flow_cookie_set_func);
+			if (func) {
+				if (!func(cm->match_protocol, cm->match_src_ip->addr, cm->match_src_port,
+					 cm->match_dest_ip->addr, cm->match_dest_port, conn_match_idx)) {
+					entry->match = cm;
+					cm->flow_cookie = conn_match_idx;
+				} else {
+					si->exception_events[SFE_IPV6_EXCEPTION_EVENT_FLOW_COOKIE_ADD_FAIL]++;
+				}
+			}
+			rcu_read_unlock();
+
+			break;
+		}
+	}
+#endif
+}
+
+/*
+ * sfe_ipv6_remove_connection_match()
+ *	Remove a connection match object from the hash.
+ */
+static inline void sfe_ipv6_remove_connection_match(struct sfe_ipv6 *si, struct sfe_ipv6_connection_match *cm)
+{
+
+	lockdep_assert_held(&si->lock);
+#ifdef CONFIG_NF_FLOW_COOKIE
+	if (si->flow_cookie_enable) {
+		/*
+		 * Tell hardware that we no longer need a flow cookie in packet of this flow
+		 */
+		unsigned int conn_match_idx;
+
+		for (conn_match_idx = 1; conn_match_idx < SFE_FLOW_COOKIE_SIZE; conn_match_idx++) {
+			struct sfe_ipv6_flow_cookie_entry *entry = &si->sfe_flow_cookie_table[conn_match_idx];
+
+			if (cm == entry->match) {
+				sfe_ipv6_flow_cookie_set_func_t func;
+
+				rcu_read_lock();
+				func = rcu_dereference(si->flow_cookie_set_func);
+				if (func) {
+					func(cm->match_protocol, cm->match_src_ip->addr, cm->match_src_port,
+					     cm->match_dest_ip->addr, cm->match_dest_port, 0);
+				}
+				rcu_read_unlock();
+
+				cm->flow_cookie = 0;
+				entry->match = NULL;
+				entry->last_clean_time = jiffies;
+				break;
+			}
+		}
+	}
+#endif
+	hlist_del_init_rcu(&cm->hnode);
+
+}
+
+/*
+ * sfe_ipv6_get_connection_hash()
+ *	Generate the hash used in connection lookups.
+ */
+static inline unsigned int sfe_ipv6_get_connection_hash(u8 protocol, struct sfe_ipv6_addr *src_ip, __be16 src_port,
+							struct sfe_ipv6_addr *dest_ip, __be16 dest_port)
+{
+	u32 idx, hash = 0;
+
+	for (idx = 0; idx < 4; idx++) {
+		hash ^= src_ip->addr[idx] ^ dest_ip->addr[idx];
+	}
+	hash = hash ^ protocol ^ ntohs(src_port ^ dest_port);
+	return ((hash >> SFE_IPV6_CONNECTION_HASH_SHIFT) ^ hash) & SFE_IPV6_CONNECTION_HASH_MASK;
+}
+
+/*
+ * sfe_ipv6_find_connection()
+ *	Get the IPv6 connection info that corresponds to a particular 5-tuple.
+ *
+ * On entry we must be holding the lock that protects the hash table.
+ */
+static inline struct sfe_ipv6_connection *sfe_ipv6_find_connection(struct sfe_ipv6 *si, u32 protocol,
+								   struct sfe_ipv6_addr *src_ip, __be16 src_port,
+								   struct sfe_ipv6_addr *dest_ip, __be16 dest_port)
+{
+	struct sfe_ipv6_connection *c;
+
+	unsigned int conn_idx = sfe_ipv6_get_connection_hash(protocol, src_ip, src_port, dest_ip, dest_port);
+
+	lockdep_assert_held(&si->lock);
+	c = si->conn_hash[conn_idx];
+
+	while (c) {
+		if ((c->src_port == src_port)
+		    && (c->dest_port == dest_port)
+		    && (sfe_ipv6_addr_equal(c->src_ip, src_ip))
+		    && (sfe_ipv6_addr_equal(c->dest_ip, dest_ip))
+		    && (c->protocol == protocol)) {
+			return c;
+		}
+		c = c->next;
+	}
+
+	return NULL;
+}
+
+/*
+ * sfe_ipv6_insert_connection()
+ *	Insert a connection into the hash.
+ *
+ * On entry we must be holding the lock that protects the hash table.
+ */
+static void sfe_ipv6_insert_connection(struct sfe_ipv6 *si, struct sfe_ipv6_connection *c)
+{
+	struct sfe_ipv6_connection **hash_head;
+	struct sfe_ipv6_connection *prev_head;
+	unsigned int conn_idx;
+
+	lockdep_assert_held(&si->lock);
+
+	/*
+	 * Insert entry into the connection hash.
+	 */
+	conn_idx = sfe_ipv6_get_connection_hash(c->protocol, c->src_ip, c->src_port,
+						c->dest_ip, c->dest_port);
+	hash_head = &si->conn_hash[conn_idx];
+	prev_head = *hash_head;
+	c->prev = NULL;
+	if (prev_head) {
+		prev_head->prev = c;
+	}
+
+	c->next = prev_head;
+	*hash_head = c;
+
+	/*
+	 * Insert entry into the "all connections" list.
+	 */
+	if (si->all_connections_tail) {
+		c->all_connections_prev = si->all_connections_tail;
+		si->all_connections_tail->all_connections_next = c;
+	} else {
+		c->all_connections_prev = NULL;
+		si->all_connections_head = c;
+	}
+
+	si->all_connections_tail = c;
+	c->all_connections_next = NULL;
+	si->num_connections++;
+
+	/*
+	 * Insert the connection match objects too.
+	 */
+	sfe_ipv6_insert_connection_match(si, c->original_match);
+	sfe_ipv6_insert_connection_match(si, c->reply_match);
+}
+
+/*
+ * sfe_ipv6_remove_connection()
+ *	Remove a sfe_ipv6_connection object from the hash.
+ *
+ * On entry we must be holding the lock that protects the hash table.
+ */
+bool sfe_ipv6_remove_connection(struct sfe_ipv6 *si, struct sfe_ipv6_connection *c)
+{
+
+	lockdep_assert_held(&si->lock);
+	if (c->removed) {
+		DEBUG_ERROR("%px: Connection has been removed already\n", c);
+		return false;
+	}
+
+	/*
+	 * dereference the decap direction top_interface_dev
+	 */
+	if (c->reply_match->top_interface_dev) {
+		dev_put(c->reply_match->top_interface_dev);
+	}
+	/*
+	 * Remove the connection match objects.
+	 */
+	sfe_ipv6_remove_connection_match(si, c->reply_match);
+	sfe_ipv6_remove_connection_match(si, c->original_match);
+
+	/*
+	 * Unlink the connection.
+	 */
+	if (c->prev) {
+		c->prev->next = c->next;
+	} else {
+		unsigned int conn_idx = sfe_ipv6_get_connection_hash(c->protocol, c->src_ip, c->src_port,
+								     c->dest_ip, c->dest_port);
+		si->conn_hash[conn_idx] = c->next;
+	}
+
+	if (c->next) {
+		c->next->prev = c->prev;
+	}
+
+	/*
+	 * Unlink connection from all_connections list
+	 */
+	if (c->all_connections_prev) {
+		c->all_connections_prev->all_connections_next = c->all_connections_next;
+	} else {
+		si->all_connections_head = c->all_connections_next;
+	}
+
+	if (c->all_connections_next) {
+		c->all_connections_next->all_connections_prev = c->all_connections_prev;
+	} else {
+		si->all_connections_tail = c->all_connections_prev;
+	}
+
+	/*
+	 * If I am the next sync connection, move the sync to my next or head.
+	 */
+	if (unlikely(si->wc_next == c)) {
+		si->wc_next = c->all_connections_next;
+	}
+
+	c->removed = true;
+	si->num_connections--;
+	return true;
+}
+
+/*
+ * sfe_ipv6_gen_sync_connection()
+ *	Sync a connection.
+ *
+ * On entry to this function we expect that the lock for the connection is either
+ * already held (while called from sfe_ipv6_periodic_sync() or isn't required
+ * (while called from sfe_ipv6_flush_sfe_ipv6_connection())
+ */
+static void sfe_ipv6_gen_sync_connection(struct sfe_ipv6 *si, struct sfe_ipv6_connection *c,
+					struct sfe_connection_sync *sis, sfe_sync_reason_t reason,
+					u64 now_jiffies)
+{
+	struct sfe_ipv6_connection_match *original_cm;
+	struct sfe_ipv6_connection_match *reply_cm;
+	u32 packet_count, byte_count;
+
+	/*
+	 * Fill in the update message.
+	 */
+	sis->is_v6 = 1;
+	sis->protocol = c->protocol;
+	sis->src_ip.ip6[0] = c->src_ip[0];
+	sis->src_ip_xlate.ip6[0] = c->src_ip_xlate[0];
+	sis->dest_ip.ip6[0] = c->dest_ip[0];
+	sis->dest_ip_xlate.ip6[0] = c->dest_ip_xlate[0];
+	sis->src_port = c->src_port;
+	sis->src_port_xlate = c->src_port_xlate;
+	sis->dest_port = c->dest_port;
+	sis->dest_port_xlate = c->dest_port_xlate;
+
+	original_cm = c->original_match;
+	reply_cm = c->reply_match;
+	sis->src_td_max_window = original_cm->protocol_state.tcp.max_win;
+	sis->src_td_end = original_cm->protocol_state.tcp.end;
+	sis->src_td_max_end = original_cm->protocol_state.tcp.max_end;
+	sis->dest_td_max_window = reply_cm->protocol_state.tcp.max_win;
+	sis->dest_td_end = reply_cm->protocol_state.tcp.end;
+	sis->dest_td_max_end = reply_cm->protocol_state.tcp.max_end;
+
+	sfe_ipv6_connection_match_update_summary_stats(original_cm, &packet_count, &byte_count);
+	sis->src_new_packet_count = packet_count;
+	sis->src_new_byte_count = byte_count;
+
+	sfe_ipv6_connection_match_update_summary_stats(reply_cm, &packet_count, &byte_count);
+	sis->dest_new_packet_count = packet_count;
+	sis->dest_new_byte_count = byte_count;
+
+	sis->src_dev = original_cm->match_dev;
+	sis->src_packet_count = original_cm->rx_packet_count64;
+	sis->src_byte_count = original_cm->rx_byte_count64;
+
+	sis->dest_dev = reply_cm->match_dev;
+	sis->dest_packet_count = reply_cm->rx_packet_count64;
+	sis->dest_byte_count = reply_cm->rx_byte_count64;
+
+	sis->reason = reason;
+
+	/*
+	 * Get the time increment since our last sync.
+	 */
+	sis->delta_jiffies = now_jiffies - c->last_sync_jiffies;
+	c->last_sync_jiffies = now_jiffies;
+}
+
+/*
+ * sfe_ipv6_free_sfe_ipv6_connection_rcu()
+ *	Called at RCU qs state to free the connection object.
+ */
+static void sfe_ipv6_free_sfe_ipv6_connection_rcu(struct rcu_head *head)
+{
+	struct sfe_ipv6_connection *c;
+	struct udp_sock *up;
+	struct sock *sk;
+
+	/*
+	 * We dont need spin lock as the connection is already removed from link list
+	 */
+	c = container_of(head, struct sfe_ipv6_connection, rcu);
+	BUG_ON(!c->removed);
+
+	DEBUG_TRACE("%px: connecton has been deleted\n", c);
+
+	/*
+	 * Decrease the refcount taken in function sfe_ipv6_create_rule()
+	 * during call of __udp6_lib_lookup()
+	 */
+	up = c->reply_match->up;
+	if (up) {
+		sk = (struct sock *)up;
+		sock_put(sk);
+	}
+
+	/*
+	 * Release our hold of the source and dest devices and free the memory
+	 * for our connection objects.
+	 */
+	dev_put(c->original_dev);
+	dev_put(c->reply_dev);
+	kfree(c->original_match);
+	kfree(c->reply_match);
+	kfree(c);
+}
+
+/*
+ * sfe_ipv6_sync_status()
+ *	update a connection status to its connection manager.
+ *
+ * si: the ipv6 context
+ * c: which connection to be notified
+ * reason: what kind of reason: flush, or destroy
+ */
+void sfe_ipv6_sync_status(struct sfe_ipv6 *si,
+				      struct sfe_ipv6_connection *c,
+				      sfe_sync_reason_t reason)
+{
+	struct sfe_connection_sync sis;
+	u64 now_jiffies;
+	sfe_sync_rule_callback_t sync_rule_callback;
+
+	rcu_read_lock();
+	sync_rule_callback = rcu_dereference(si->sync_rule_callback);
+
+	if (unlikely(!sync_rule_callback)) {
+		rcu_read_unlock();
+		return;
+	}
+
+	/*
+	 * Generate a sync message and then sync.
+	 */
+	now_jiffies = get_jiffies_64();
+	sfe_ipv6_gen_sync_connection(si, c, &sis, reason, now_jiffies);
+	sync_rule_callback(&sis);
+
+	rcu_read_unlock();
+}
+
+/*
+ * sfe_ipv6_flush_connection()
+ *	Flush a connection and free all associated resources.
+ *
+ * We need to be called with bottom halves disabled locally as we need to acquire
+ * the connection hash lock and release it again.  In general we're actually called
+ * from within a BH and so we're fine, but we're also called when connections are
+ * torn down.
+ */
+void sfe_ipv6_flush_connection(struct sfe_ipv6 *si,
+				      struct sfe_ipv6_connection *c,
+				      sfe_sync_reason_t reason)
+{
+	BUG_ON(!c->removed);
+
+	this_cpu_inc(si->stats_pcpu->connection_flushes64);
+	sfe_ipv6_sync_status(si, c, reason);
+
+	/*
+	 * Release our hold of the source and dest devices and free the memory
+	 * for our connection objects.
+	 */
+	call_rcu(&c->rcu, sfe_ipv6_free_sfe_ipv6_connection_rcu);
+}
+
+ /*
+ * sfe_ipv6_exception_stats_inc()
+ *	Increment exception stats.
+ */
+void sfe_ipv6_exception_stats_inc(struct sfe_ipv6 *si, enum sfe_ipv6_exception_events reason)
+{
+	struct sfe_ipv6_stats *stats = this_cpu_ptr(si->stats_pcpu);
+
+	stats->exception_events64[reason]++;
+	stats->packets_not_forwarded64++;
+}
+
+/*
+ * sfe_ipv6_is_local_ip()
+ *	return true if it is local ip otherwise return false
+ */
+static bool sfe_ipv6_is_local_ip(struct sfe_ipv6 *si, uint8_t *addr)
+{
+	struct net_device *dev;
+	struct in6_addr ip_addr;
+	memcpy(ip_addr.s6_addr, addr, 16);
+
+	dev = ipv6_dev_find(&init_net, &ip_addr, 1);
+	if (dev) {
+		dev_put(dev);
+		return true;
+	}
+
+	return false;
+}
+
+/*
+ * sfe_ipv6_recv()
+ *	Handle packet receives and forwaring.
+ *
+ * Returns 1 if the packet is forwarded or 0 if it isn't.
+ */
+int sfe_ipv6_recv(struct net_device *dev, struct sk_buff *skb, struct sfe_l2_info *l2_info, bool tun_outer)
+{
+	struct sfe_ipv6 *si = &__si6;
+	unsigned int len;
+	unsigned int payload_len;
+	unsigned int ihl = sizeof(struct ipv6hdr);
+	bool sync_on_find = false;
+	struct ipv6hdr *iph;
+	u8 next_hdr;
+
+	/*
+	 * Check that we have space for an IP header and an uplayer header here.
+	 */
+	len = skb->len;
+	if (!pskb_may_pull(skb, ihl + sizeof(struct sfe_ipv6_ext_hdr))) {
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_HEADER_INCOMPLETE);
+		DEBUG_TRACE("len: %u is too short\n", len);
+		return 0;
+	}
+
+	/*
+	 * Is our IP version wrong?
+	 */
+	iph = (struct ipv6hdr *)skb->data;
+	if (unlikely(iph->version != 6)) {
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_NON_V6);
+		DEBUG_TRACE("IP version: %u\n", iph->version);
+		return 0;
+	}
+
+	/*
+	 * Does our datagram fit inside the skb?
+	 */
+	payload_len = ntohs(iph->payload_len);
+	if (unlikely(payload_len > (len - ihl))) {
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_DATAGRAM_INCOMPLETE);
+		DEBUG_TRACE("payload_len: %u, exceeds len: %u\n", payload_len, (len - (unsigned int)sizeof(struct ipv6hdr)));
+		return 0;
+	}
+
+	next_hdr = iph->nexthdr;
+	while (unlikely(sfe_ipv6_is_ext_hdr(next_hdr))) {
+		struct sfe_ipv6_ext_hdr *ext_hdr;
+		unsigned int ext_hdr_len;
+
+		ext_hdr = (struct sfe_ipv6_ext_hdr *)(skb->data + ihl);
+
+		ext_hdr_len = ext_hdr->hdr_len;
+		ext_hdr_len <<= 3;
+		ext_hdr_len += sizeof(struct sfe_ipv6_ext_hdr);
+		ihl += ext_hdr_len;
+		if (!pskb_may_pull(skb, ihl + sizeof(struct sfe_ipv6_ext_hdr))) {
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_HEADER_INCOMPLETE);
+
+			DEBUG_TRACE("extension header %d not completed\n", next_hdr);
+			return 0;
+		}
+		/*
+		 * Any packets have extend hdr, won't be handled in the fast
+		 * path,sync its status and exception to the kernel.
+		 */
+		sync_on_find = true;
+		next_hdr = ext_hdr->next_hdr;
+	}
+
+	if (IPPROTO_UDP == next_hdr) {
+		return sfe_ipv6_recv_udp(si, skb, dev, len, iph, ihl, sync_on_find, l2_info, tun_outer);
+	}
+
+	if (IPPROTO_TCP == next_hdr) {
+		return sfe_ipv6_recv_tcp(si, skb, dev, len, iph, ihl, sync_on_find, l2_info);
+	}
+
+	if (IPPROTO_ICMPV6 == next_hdr) {
+		return sfe_ipv6_recv_icmp(si, skb, dev, len, iph, ihl);
+	}
+
+	if (IPPROTO_IPIP == next_hdr) {
+		return sfe_ipv6_recv_tunipip6(si, skb, dev, len, iph, ihl, sync_on_find, l2_info, true);
+	}
+
+#ifdef SFE_GRE_TUN_ENABLE
+	if (IPPROTO_GRE == next_hdr) {
+		return sfe_ipv6_recv_gre(si, skb, dev, len, iph, ihl, sync_on_find, l2_info, tun_outer);
+	}
+#endif
+
+	sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_UNHANDLED_PROTOCOL);
+	DEBUG_TRACE("not UDP, TCP or ICMP: %u\n", next_hdr);
+	return 0;
+}
+
+/*
+ * sfe_ipv6_update_tcp_state()
+ *	update TCP window variables.
+ */
+static void
+sfe_ipv6_update_tcp_state(struct sfe_ipv6_connection *c,
+			  struct sfe_ipv6_rule_create_msg *msg)
+{
+	struct sfe_ipv6_connection_match *orig_cm;
+	struct sfe_ipv6_connection_match *repl_cm;
+	struct sfe_ipv6_tcp_connection_match *orig_tcp;
+	struct sfe_ipv6_tcp_connection_match *repl_tcp;
+
+	orig_cm = c->original_match;
+	repl_cm = c->reply_match;
+	orig_tcp = &orig_cm->protocol_state.tcp;
+	repl_tcp = &repl_cm->protocol_state.tcp;
+
+	/* update orig */
+	if (orig_tcp->max_win < msg->tcp_rule.flow_max_window) {
+		orig_tcp->max_win = msg->tcp_rule.flow_max_window;
+	}
+	if ((s32)(orig_tcp->end - msg->tcp_rule.flow_end) < 0) {
+		orig_tcp->end = msg->tcp_rule.flow_end;
+	}
+	if ((s32)(orig_tcp->max_end - msg->tcp_rule.flow_max_end) < 0) {
+		orig_tcp->max_end = msg->tcp_rule.flow_max_end;
+	}
+
+	/* update reply */
+	if (repl_tcp->max_win < msg->tcp_rule.return_max_window) {
+		repl_tcp->max_win = msg->tcp_rule.return_max_window;
+	}
+	if ((s32)(repl_tcp->end - msg->tcp_rule.return_end) < 0) {
+		repl_tcp->end = msg->tcp_rule.return_end;
+	}
+	if ((s32)(repl_tcp->max_end - msg->tcp_rule.return_max_end) < 0) {
+		repl_tcp->max_end = msg->tcp_rule.return_max_end;
+	}
+
+	/* update match flags */
+	orig_cm->flags &= ~SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK;
+	repl_cm->flags &= ~SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK;
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_NO_SEQ_CHECK) {
+		orig_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK;
+		repl_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK;
+	}
+}
+
+/*
+ * sfe_ipv6_update_protocol_state()
+ *	update protocol specified state machine.
+ */
+static void
+sfe_ipv6_update_protocol_state(struct sfe_ipv6_connection *c,
+			       struct sfe_ipv6_rule_create_msg *msg)
+{
+	switch (msg->tuple.protocol) {
+	case IPPROTO_TCP:
+		sfe_ipv6_update_tcp_state(c, msg);
+		break;
+	}
+}
+
+/*
+ * sfe_ipv6_match_entry_set_vlan()
+ */
+static void sfe_ipv6_match_entry_set_vlan(
+			struct sfe_ipv6_connection_match *cm,
+			u32 primary_ingress_vlan_tag,
+			u32 primary_egress_vlan_tag,
+			u32 secondary_ingress_vlan_tag,
+			u32 secondary_egress_vlan_tag)
+{
+	u16 tpid;
+	/*
+	 * Prevent stacking header counts when updating.
+	 */
+	cm->ingress_vlan_hdr_cnt = 0;
+	cm->egress_vlan_hdr_cnt = 0;
+	memset(cm->ingress_vlan_hdr, 0, sizeof(cm->ingress_vlan_hdr));
+	memset(cm->egress_vlan_hdr, 0, sizeof(cm->egress_vlan_hdr));
+
+	/*
+	 * vlan_hdr[0] corresponds to outer tag
+	 * vlan_hdr[1] corresponds to inner tag
+	 * Extract the vlan information (tpid and tci) from rule message
+	 */
+	if ((primary_ingress_vlan_tag & VLAN_VID_MASK) != SFE_VLAN_ID_NOT_CONFIGURED) {
+		tpid = (u16)(primary_ingress_vlan_tag >> 16);
+		cm->ingress_vlan_hdr[0].tpid = ntohs(tpid);
+		cm->ingress_vlan_hdr[0].tci = (u16)primary_ingress_vlan_tag;
+		cm->ingress_vlan_hdr_cnt++;
+	}
+
+	if ((secondary_ingress_vlan_tag & VLAN_VID_MASK) != SFE_VLAN_ID_NOT_CONFIGURED) {
+		tpid = (u16)(secondary_ingress_vlan_tag >> 16);
+		cm->ingress_vlan_hdr[1].tpid = ntohs(tpid);
+		cm->ingress_vlan_hdr[1].tci = (u16)secondary_ingress_vlan_tag;
+		cm->ingress_vlan_hdr_cnt++;
+	}
+
+	if ((primary_egress_vlan_tag & VLAN_VID_MASK) != SFE_VLAN_ID_NOT_CONFIGURED) {
+		tpid = (u16)(primary_egress_vlan_tag >> 16);
+		cm->egress_vlan_hdr[0].tpid = ntohs(tpid);
+		cm->egress_vlan_hdr[0].tci = (u16)primary_egress_vlan_tag;
+		cm->egress_vlan_hdr_cnt++;
+	}
+
+	if ((secondary_egress_vlan_tag & VLAN_VID_MASK) != SFE_VLAN_ID_NOT_CONFIGURED) {
+		tpid = (u16)(secondary_egress_vlan_tag >> 16);
+		cm->egress_vlan_hdr[1].tpid = ntohs(tpid);
+		cm->egress_vlan_hdr[1].tci = (u16)secondary_egress_vlan_tag;
+		cm->egress_vlan_hdr_cnt++;
+	}
+}
+
+/*
+ * sfe_ipv6_update_rule()
+ *	update forwarding rule after rule is created.
+ */
+void sfe_ipv6_update_rule(struct sfe_ipv6_rule_create_msg *msg)
+
+{
+	struct sfe_ipv6_connection *c;
+	struct sfe_ipv6 *si = &__si6;
+
+	spin_lock_bh(&si->lock);
+
+	c = sfe_ipv6_find_connection(si,
+				     msg->tuple.protocol,
+				     (struct sfe_ipv6_addr *)msg->tuple.flow_ip,
+				     msg->tuple.flow_ident,
+				     (struct sfe_ipv6_addr *)msg->tuple.return_ip,
+				     msg->tuple.return_ident);
+	if (c != NULL) {
+		sfe_ipv6_update_protocol_state(c, msg);
+	}
+
+	spin_unlock_bh(&si->lock);
+}
+
+/*
+ * sfe_ipv6_mark_rule_update()
+ *	Updates the mark values of match entries.
+ */
+void sfe_ipv6_mark_rule_update(struct sfe_connection_mark *mark)
+{
+	struct sfe_ipv6_connection *c;
+	struct sfe_ipv6 *si = &__si6;
+
+	spin_lock_bh(&si->lock);
+	c = sfe_ipv6_find_connection(si, mark->protocol,
+				     (struct sfe_ipv6_addr *)mark->src_ip,
+				     mark->src_port,
+				     (struct sfe_ipv6_addr *)mark->dest_ip,
+				     mark->dest_port);
+	if (!c) {
+		spin_unlock_bh(&si->lock);
+		DEBUG_WARN("%px: connection not found for mark update\n", mark);
+		return;
+	}
+	c->original_match ->mark = mark->mark;
+	c->reply_match->mark = mark->mark;
+	spin_unlock_bh(&si->lock);
+	DEBUG_TRACE("%px: connection mark updated with %d\n", mark, mark->mark);
+}
+EXPORT_SYMBOL(sfe_ipv6_mark_rule_update);
+
+/*
+ * sfe_ipv6_xmit_eth_type_check
+ *	Checking if MAC header has to be written.
+ */
+static inline bool sfe_ipv6_xmit_eth_type_check(struct net_device *dev, u32 cm_flags)
+{
+	if (!(dev->flags & IFF_NOARP)) {
+		return true;
+	}
+
+	/*
+	 * For PPPoE, since we are now supporting PPPoE encapsulation, we are writing L2 header.
+	 */
+	if (cm_flags & SFE_IPV6_CONNECTION_MATCH_FLAG_PPPOE_ENCAP) {
+		return true;
+	}
+
+	return false;
+}
+
+/*
+ * sfe_ipv6_create_rule()
+ *	Create a forwarding rule.
+ */
+int sfe_ipv6_create_rule(struct sfe_ipv6_rule_create_msg *msg)
+{
+	struct sfe_ipv6 *si = &__si6;
+	struct sfe_ipv6_connection *c, *old_c;
+	struct sfe_ipv6_connection_match *original_cm;
+	struct sfe_ipv6_connection_match *reply_cm;
+	struct net_device *dest_dev;
+	struct net_device *src_dev;
+	struct sfe_ipv6_5tuple *tuple = &msg->tuple;
+	struct sock *sk;
+	struct net *net;
+	unsigned int src_if_idx;
+
+	s32 flow_interface_num = msg->conn_rule.flow_top_interface_num;
+	s32 return_interface_num = msg->conn_rule.return_top_interface_num;
+
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE) {
+		flow_interface_num = msg->conn_rule.flow_interface_num;
+	}
+
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE) {
+		return_interface_num = msg->conn_rule.return_interface_num;
+	}
+
+	src_dev = dev_get_by_index(&init_net, flow_interface_num);
+	if (!src_dev) {
+		DEBUG_WARN("%px: Unable to find src_dev corresponding to %d\n", msg,
+						flow_interface_num);
+		this_cpu_inc(si->stats_pcpu->connection_create_failures64);
+		return -EINVAL;
+	}
+
+	dest_dev = dev_get_by_index(&init_net, return_interface_num);
+	if (!dest_dev) {
+		DEBUG_WARN("%px: Unable to find dest_dev corresponding to %d\n", msg,
+						return_interface_num);
+		this_cpu_inc(si->stats_pcpu->connection_create_failures64);
+		dev_put(src_dev);
+		return -EINVAL;
+	}
+
+	if (unlikely((dest_dev->reg_state != NETREG_REGISTERED) ||
+		     (src_dev->reg_state != NETREG_REGISTERED))) {
+		DEBUG_WARN("%px: src_dev=%s and dest_dev=%s are unregistered\n", msg,
+						src_dev->name, dest_dev->name);
+		this_cpu_inc(si->stats_pcpu->connection_create_failures64);
+		dev_put(src_dev);
+		dev_put(dest_dev);
+		return -EINVAL;
+	}
+
+	/*
+	 * Allocate the various connection tracking objects.
+	 */
+	c = (struct sfe_ipv6_connection *)kzalloc(sizeof(struct sfe_ipv6_connection), GFP_ATOMIC);
+	if (unlikely(!c)) {
+		DEBUG_WARN("%px: memory allocation of connection entry failed\n", msg);
+		this_cpu_inc(si->stats_pcpu->connection_create_failures64);
+		dev_put(src_dev);
+		dev_put(dest_dev);
+		return -ENOMEM;
+	}
+
+	original_cm = (struct sfe_ipv6_connection_match *)kzalloc(sizeof(struct sfe_ipv6_connection_match), GFP_ATOMIC);
+	if (unlikely(!original_cm)) {
+		this_cpu_inc(si->stats_pcpu->connection_create_failures64);
+		DEBUG_WARN("%px: memory allocation of connection match entry failed\n", msg);
+		kfree(c);
+		dev_put(src_dev);
+		dev_put(dest_dev);
+		return -ENOMEM;
+	}
+
+	reply_cm = (struct sfe_ipv6_connection_match *)kzalloc(sizeof(struct sfe_ipv6_connection_match), GFP_ATOMIC);
+	if (unlikely(!reply_cm)) {
+		this_cpu_inc(si->stats_pcpu->connection_create_failures64);
+		DEBUG_WARN("%px: memory allocation of connection match entry failed\n", msg);
+		kfree(original_cm);
+		kfree(c);
+		dev_put(src_dev);
+		dev_put(dest_dev);
+		return -ENOMEM;
+	}
+
+	this_cpu_inc(si->stats_pcpu->connection_create_requests64);
+
+	spin_lock_bh(&si->lock);
+
+	/*
+	 * Check to see if there is already a flow that matches the rule we're
+	 * trying to create.  If there is then we can't create a new one.
+	 */
+	old_c = sfe_ipv6_find_connection(si,
+					tuple->protocol,
+					(struct sfe_ipv6_addr *)tuple->flow_ip,
+					tuple->flow_ident,
+					(struct sfe_ipv6_addr *)tuple->return_ip,
+					tuple->return_ident);
+
+	if (old_c != NULL) {
+		this_cpu_inc(si->stats_pcpu->connection_create_collisions64);
+
+		/*
+		 * If we already have the flow then it's likely that this
+		 * request to create the connection rule contains more
+		 * up-to-date information. Check and update accordingly.
+		 */
+		sfe_ipv6_update_protocol_state(old_c, msg);
+		spin_unlock_bh(&si->lock);
+
+		kfree(reply_cm);
+		kfree(original_cm);
+		kfree(c);
+		dev_put(src_dev);
+		dev_put(dest_dev);
+
+		DEBUG_TRACE("connection already exists -  p: %d\n"
+			    "  s: %s:%pxM:%pI6:%u, d: %s:%pxM:%pI6:%u\n",
+			    tuple->protocol,
+			    src_dev->name, msg->conn_rule.flow_mac, tuple->flow_ip, ntohs(tuple->flow_ident),
+			   dest_dev->name, msg->conn_rule.return_mac, tuple->return_ip, ntohs(tuple->return_ident));
+		return -EADDRINUSE;
+	}
+
+	/*
+	 * Fill in the "original" direction connection matching object.
+	 * Note that the transmit MAC address is "dest_mac_xlate" because
+	 * we always know both ends of a connection by their translated
+	 * addresses and not their public addresses.
+	 */
+	original_cm->match_dev = src_dev;
+	original_cm->match_protocol = tuple->protocol;
+	original_cm->match_src_ip[0] = *(struct sfe_ipv6_addr *)tuple->flow_ip;
+	original_cm->match_src_port = netif_is_vxlan(src_dev) ? 0 : tuple->flow_ident;
+	original_cm->match_dest_ip[0] = *(struct sfe_ipv6_addr *)tuple->return_ip;
+	original_cm->match_dest_port = tuple->return_ident;
+
+	original_cm->xlate_src_ip[0] = *(struct sfe_ipv6_addr *)tuple->flow_ip;
+	original_cm->xlate_src_port = tuple->flow_ident;
+	original_cm->xlate_dest_ip[0] = *(struct sfe_ipv6_addr *)tuple->return_ip;
+	original_cm->xlate_dest_port =  tuple->return_ident;
+
+	original_cm->xmit_dev = dest_dev;
+
+	original_cm->xmit_dev_mtu = msg->conn_rule.return_mtu;
+
+	original_cm->connection = c;
+	original_cm->counter_match = reply_cm;
+
+	/*
+	 * Valid in decap direction only
+	 */
+	RCU_INIT_POINTER(original_cm->up, NULL);
+
+	if (msg->valid_flags & SFE_RULE_CREATE_MARK_VALID) {
+		original_cm->mark =  msg->mark_rule.flow_mark;
+		original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_MARK;
+	}
+	if (msg->valid_flags & SFE_RULE_CREATE_QOS_VALID) {
+		original_cm->priority = msg->qos_rule.flow_qos_tag;
+		original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_PRIORITY_REMARK;
+	}
+
+	if (msg->valid_flags & SFE_RULE_CREATE_DSCP_MARKING_VALID) {
+		original_cm->dscp = msg->dscp_rule.flow_dscp << SFE_IPV6_DSCP_SHIFT;
+		original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_DSCP_REMARK;
+	}
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_BRIDGE_FLOW) {
+		original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_BRIDGE_FLOW;
+	}
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_FLOW_TRANSMIT_FAST) {
+		original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT_DEV_ADMISSION;
+	}
+
+
+	/*
+	 * Add VLAN rule to original_cm
+	 */
+	if (msg->valid_flags & SFE_RULE_CREATE_VLAN_VALID) {
+		struct sfe_vlan_rule *vlan_primary_rule = &msg->vlan_primary_rule;
+		struct sfe_vlan_rule *vlan_secondary_rule = &msg->vlan_secondary_rule;
+		sfe_ipv6_match_entry_set_vlan(original_cm,
+					     vlan_primary_rule->ingress_vlan_tag,
+					     vlan_primary_rule->egress_vlan_tag,
+					     vlan_secondary_rule->ingress_vlan_tag,
+					     vlan_secondary_rule->egress_vlan_tag);
+
+		if ((msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE) &&
+			original_cm->egress_vlan_hdr_cnt > 0) {
+			original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_INSERT_EGRESS_VLAN_TAG;
+			original_cm->l2_hdr_size += original_cm->egress_vlan_hdr_cnt * VLAN_HLEN;
+		}
+	}
+
+	if ((IPPROTO_GRE == tuple->protocol) && !sfe_ipv6_is_local_ip(si, (uint8_t *)original_cm->match_dest_ip)) {
+		original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_PASSTHROUGH;
+	}
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+	original_cm->flow_cookie = 0;
+#endif
+#ifdef CONFIG_XFRM
+	if (msg->valid_flags & SFE_RULE_CREATE_DIRECTION_VALID) {
+		original_cm->flow_accel = msg->direction_rule.flow_accel;
+	} else {
+		original_cm->flow_accel = 1;
+	}
+#endif
+	/*
+	 * If l2_features are disabled and flow uses l2 features such as macvlan/bridge/pppoe/vlan,
+	 * bottom interfaces are expected to be disabled in the flow rule and always top interfaces
+	 * are used. In such cases, do not use HW csum offload. csum offload is used only when we
+	 * are sending directly to the destination interface that supports it.
+	 */
+	if (likely(dest_dev->features & NETIF_F_HW_CSUM) && sfe_dev_has_hw_csum(dest_dev)) {
+		if ((msg->conn_rule.return_top_interface_num == msg->conn_rule.return_interface_num) ||
+			(msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_RETURN_BOTTOM_INTERFACE)) {
+			/*
+			 * Dont enable CSUM offload
+			 */
+#if 0
+			 original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_CSUM_OFFLOAD;
+#endif
+		}
+	}
+
+	/*
+	 * Adding PPPoE parameters to original and reply entries based on the direction where
+	 * PPPoE header is valid in ECM rule.
+	 *
+	 * If PPPoE is valid in flow direction (from interface is PPPoE), then
+	 *	original cm will have PPPoE at ingress (strip PPPoE header)
+	 *	reply cm will have PPPoE at egress (add PPPoE header)
+	 *
+	 * If PPPoE is valid in return direction (to interface is PPPoE), then
+	 *	original cm will have PPPoE at egress (add PPPoE header)
+	 *	reply cm will have PPPoE at ingress (strip PPPoE header)
+	 */
+	if (msg->valid_flags & SFE_RULE_CREATE_PPPOE_DECAP_VALID) {
+		original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_PPPOE_DECAP;
+		original_cm->pppoe_session_id = msg->pppoe_rule.flow_pppoe_session_id;
+		ether_addr_copy(original_cm->pppoe_remote_mac, msg->pppoe_rule.flow_pppoe_remote_mac);
+
+		reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_PPPOE_ENCAP;
+		reply_cm->l2_hdr_size += SFE_PPPOE_SESSION_HEADER_SIZE;
+		reply_cm->pppoe_session_id = msg->pppoe_rule.flow_pppoe_session_id;
+		ether_addr_copy(reply_cm->pppoe_remote_mac, msg->pppoe_rule.flow_pppoe_remote_mac);
+	}
+
+	if (msg->valid_flags & SFE_RULE_CREATE_PPPOE_ENCAP_VALID) {
+		original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_PPPOE_ENCAP;
+		original_cm->l2_hdr_size += SFE_PPPOE_SESSION_HEADER_SIZE;
+		original_cm->pppoe_session_id = msg->pppoe_rule.return_pppoe_session_id;
+		ether_addr_copy(original_cm->pppoe_remote_mac, msg->pppoe_rule.return_pppoe_remote_mac);
+
+		reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_PPPOE_DECAP;
+		reply_cm->pppoe_session_id = msg->pppoe_rule.return_pppoe_session_id;
+		ether_addr_copy(reply_cm->pppoe_remote_mac, msg->pppoe_rule.return_pppoe_remote_mac);
+	}
+
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_FLOW_SRC_INTERFACE_CHECK) {
+		original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK;
+	}
+
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_FLOW_SRC_INTERFACE_CHECK_NO_FLUSH) {
+		original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK_NO_FLUSH;
+	}
+
+	/*
+	 * For the non-arp interface, we don't write L2 HDR.
+	 * Excluding PPPoE from this, since we are now supporting PPPoE encap/decap.
+	 */
+	if (sfe_ipv6_xmit_eth_type_check(dest_dev, original_cm->flags)) {
+
+		/*
+		 * Check whether the rule has configured a specific source MAC address to use.
+		 * This is needed when virtual L3 interfaces such as br-lan, macvlan, vlan are used during egress
+		 */
+		if (msg->rule_flags & SFE_RULE_CREATE_FLAG_BRIDGE_FLOW) {
+			ether_addr_copy((u8 *)original_cm->xmit_src_mac, (u8 *)msg->conn_rule.flow_mac);
+		} else {
+			if ((msg->valid_flags & SFE_RULE_CREATE_SRC_MAC_VALID) &&
+			    (msg->src_mac_rule.mac_valid_flags & SFE_SRC_MAC_RETURN_VALID)) {
+				ether_addr_copy((u8 *)original_cm->xmit_src_mac, (u8 *)msg->src_mac_rule.return_src_mac);
+			} else {
+				ether_addr_copy((u8 *)original_cm->xmit_src_mac, (u8 *)dest_dev->dev_addr);
+			}
+		}
+		ether_addr_copy((u8 *)original_cm->xmit_dest_mac, (u8 *)msg->conn_rule.return_mac);
+
+		original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_L2_HDR;
+		original_cm->l2_hdr_size += ETH_HLEN;
+
+		/*
+		 * If our dev writes Ethernet headers then we can write a really fast
+		 * version
+		 */
+		if (dest_dev->header_ops) {
+			if (dest_dev->header_ops->create == eth_header) {
+				original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR;
+			}
+		}
+	}
+
+	/*
+	 * Fill in the "reply" direction connection matching object.
+	 */
+	reply_cm->match_dev = dest_dev;
+	reply_cm->match_protocol = tuple->protocol;
+	reply_cm->match_src_ip[0] = *(struct sfe_ipv6_addr *)tuple->return_ip;
+	reply_cm->match_dest_ip[0] = *(struct sfe_ipv6_addr *)tuple->flow_ip;
+	reply_cm->match_dest_port = tuple->flow_ident;
+	reply_cm->xlate_src_ip[0] = *(struct sfe_ipv6_addr *)tuple->return_ip;
+	reply_cm->xlate_src_port = tuple->return_ident;
+	reply_cm->xlate_dest_ip[0] = *(struct sfe_ipv6_addr *)tuple->flow_ip;
+	reply_cm->xlate_dest_port = tuple->flow_ident;
+
+	/*
+	 * Keep source port as 0 for VxLAN tunnels.
+	 */
+	if (netif_is_vxlan(src_dev) || netif_is_vxlan(dest_dev)) {
+		reply_cm->match_src_port = 0;
+	} else {
+		reply_cm->match_src_port = tuple->return_ident;
+	}
+
+	reply_cm->xmit_dev = src_dev;
+	reply_cm->xmit_dev_mtu = msg->conn_rule.flow_mtu;
+
+	reply_cm->connection = c;
+	reply_cm->counter_match = original_cm;
+
+	if (msg->valid_flags & SFE_RULE_CREATE_MARK_VALID) {
+		reply_cm->mark =  msg->mark_rule.return_mark;
+		reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_MARK;
+	}
+	if (msg->valid_flags & SFE_RULE_CREATE_QOS_VALID) {
+		reply_cm->priority = msg->qos_rule.return_qos_tag;
+		reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_PRIORITY_REMARK;
+	}
+	if (msg->valid_flags & SFE_RULE_CREATE_DSCP_MARKING_VALID) {
+		reply_cm->dscp = msg->dscp_rule.return_dscp << SFE_IPV6_DSCP_SHIFT;
+		reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_DSCP_REMARK;
+	}
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_BRIDGE_FLOW) {
+		reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_BRIDGE_FLOW;
+	}
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_RETURN_TRANSMIT_FAST) {
+		reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT_DEV_ADMISSION;
+	}
+
+	if ((IPPROTO_GRE == tuple->protocol) && !sfe_ipv6_is_local_ip(si, (uint8_t *)reply_cm->match_dest_ip)) {
+		reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_PASSTHROUGH;
+	}
+
+	/*
+	 * Setup UDP Socket if found to be valid for decap.
+	 */
+	RCU_INIT_POINTER(reply_cm->up, NULL);
+	net = dev_net(reply_cm->match_dev);
+	src_if_idx = src_dev->ifindex;
+
+	rcu_read_lock();
+
+	/*
+	 * Look for the associated sock object.
+	 * __udp6_lib_lookup() holds a reference for this sock object,
+	 * which will be released in sfe_ipv6_flush_connection()
+	 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	sk = __udp6_lib_lookup(net, (const struct in6_addr *)reply_cm->match_dest_ip,
+			reply_cm->match_dest_port, (const struct in6_addr *)reply_cm->xlate_src_ip,
+			reply_cm->xlate_src_port, src_if_idx, &udp_table);
+#else
+	sk = __udp6_lib_lookup(net, (const struct in6_addr *)reply_cm->match_dest_ip,
+			reply_cm->match_dest_port, (const struct in6_addr *)reply_cm->xlate_src_ip,
+			reply_cm->xlate_src_port, src_if_idx, 0, &udp_table, NULL);
+#endif
+	rcu_read_unlock();
+
+	/*
+	 * We set the UDP sock pointer as valid only for decap direction.
+	 */
+	if (sk && udp_sk(sk)->encap_type) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+		if (!atomic_add_unless(&sk->sk_refcnt, 1, 0)) {
+#else
+		if (!refcount_inc_not_zero(&sk->sk_refcnt)) {
+#endif
+			this_cpu_inc(si->stats_pcpu->connection_create_failures64);
+			spin_unlock_bh(&si->lock);
+			kfree(reply_cm);
+			kfree(original_cm);
+			kfree(c);
+
+			DEBUG_INFO("sfe: unable to take reference for socket  p:%d\n", tuple->protocol);
+			DEBUG_INFO("SK: connection - \n"
+		     			"  s: %s:%pI6(%pI6):%u(%u)\n"
+				   "  d: %s:%pI6(%pI6):%u(%u)\n",
+					reply_cm->match_dev->name, &reply_cm->match_src_ip, &reply_cm->xlate_src_ip,
+					ntohs(reply_cm->match_src_port), ntohs(reply_cm->xlate_src_port),
+					reply_cm->xmit_dev->name, &reply_cm->match_dest_ip, &reply_cm->xlate_dest_ip,
+					ntohs(reply_cm->match_dest_port), ntohs(reply_cm->xlate_dest_port));
+
+			dev_put(src_dev);
+			dev_put(dest_dev);
+
+			return -ESHUTDOWN;
+		}
+
+		rcu_assign_pointer(reply_cm->up, udp_sk(sk));
+		DEBUG_INFO("Sock lookup success with reply_cm direction(%p)\n", sk);
+		DEBUG_INFO("SK: connection - \n"
+			   "  s: %s:%pI6(%pI6):%u(%u)\n"
+			   "  d: %s:%pI6(%pI6):%u(%u)\n",
+			reply_cm->match_dev->name, &reply_cm->match_src_ip, &reply_cm->xlate_src_ip,
+			ntohs(reply_cm->match_src_port), ntohs(reply_cm->xlate_src_port),
+			reply_cm->xmit_dev->name, &reply_cm->match_dest_ip, &reply_cm->xlate_dest_ip,
+			ntohs(reply_cm->match_dest_port), ntohs(reply_cm->xlate_dest_port));
+	}
+
+	/*
+	 * Add VLAN rule to reply_cm
+	 */
+	if (msg->valid_flags & SFE_RULE_CREATE_VLAN_VALID) {
+		struct sfe_vlan_rule *vlan_primary_rule = &msg->vlan_primary_rule;
+		struct sfe_vlan_rule *vlan_secondary_rule = &msg->vlan_secondary_rule;
+		sfe_ipv6_match_entry_set_vlan(reply_cm,
+					     vlan_primary_rule->egress_vlan_tag,
+					     vlan_primary_rule->ingress_vlan_tag,
+					     vlan_secondary_rule->egress_vlan_tag,
+					     vlan_secondary_rule->ingress_vlan_tag);
+
+		if ((msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE) &&
+			reply_cm->egress_vlan_hdr_cnt > 0) {
+			reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_INSERT_EGRESS_VLAN_TAG;
+			reply_cm->l2_hdr_size += reply_cm->egress_vlan_hdr_cnt * VLAN_HLEN;
+		}
+	}
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+	reply_cm->flow_cookie = 0;
+#endif
+#ifdef CONFIG_XFRM
+	if (msg->valid_flags & SFE_RULE_CREATE_DIRECTION_VALID) {
+		reply_cm->flow_accel = msg->direction_rule.return_accel;
+	} else {
+		reply_cm->flow_accel = 1;
+	}
+#endif
+
+	/*
+	 * the inet6_protocol handler will be used only in decap path
+	 * for non passthrough case.
+	 */
+	original_cm->proto = NULL;
+	reply_cm->proto = NULL;
+	original_cm->top_interface_dev = NULL;
+	reply_cm->top_interface_dev = NULL;
+
+#ifdef SFE_GRE_TUN_ENABLE
+	if (!(reply_cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_PASSTHROUGH)) {
+		rcu_read_lock();
+		reply_cm->proto = rcu_dereference(inet6_protos[tuple->protocol]);
+		rcu_read_unlock();
+
+		if (unlikely(!reply_cm->proto)) {
+			this_cpu_inc(si->stats_pcpu->connection_create_failures64);
+			spin_unlock_bh(&si->lock);
+			kfree(reply_cm);
+			kfree(original_cm);
+			kfree(c);
+			dev_put(src_dev);
+			dev_put(dest_dev);
+			DEBUG_WARN("sfe: GRE proto handler is not registered\n");
+			return -EPERM;
+		}
+	}
+#endif
+
+	/*
+	 * Decapsulation path have proto set.
+	 * This is used to differentiate de/encap, and call protocol specific handler.
+	 */
+	if (IPPROTO_IPIP == tuple->protocol) {
+		original_cm->proto = NULL;
+		rcu_read_lock();
+		reply_cm->proto = rcu_dereference(inet6_protos[tuple->protocol]);
+		rcu_read_unlock();
+		reply_cm->top_interface_dev = dev_get_by_index(&init_net, msg->conn_rule.return_top_interface_num);
+
+		if (unlikely(!reply_cm->top_interface_dev)) {
+			DEBUG_WARN("%px: Unable to find top_interface_dev corresponding to %d\n", msg,
+						msg->conn_rule.return_top_interface_num);
+			this_cpu_inc(si->stats_pcpu->connection_create_failures64);
+			spin_unlock_bh(&si->lock);
+			kfree(reply_cm);
+			kfree(original_cm);
+			kfree(c);
+			dev_put(src_dev);
+			dev_put(dest_dev);
+			return -EINVAL;
+		}
+	}
+	/*
+	 * If l2_features are disabled and flow uses l2 features such as macvlan/bridge/pppoe/vlan,
+	 * bottom interfaces are expected to be disabled in the flow rule and always top interfaces
+	 * are used. In such cases, do not use HW csum offload. csum offload is used only when we
+	 * are sending directly to the destination interface that supports it.
+	 */
+	if (likely(src_dev->features & NETIF_F_HW_CSUM) && sfe_dev_has_hw_csum(src_dev)) {
+		if ((msg->conn_rule.flow_top_interface_num == msg->conn_rule.flow_interface_num) ||
+			(msg->rule_flags & SFE_RULE_CREATE_FLAG_USE_FLOW_BOTTOM_INTERFACE)) {
+			/*
+			 * Dont enable CSUM offload
+			 */
+#if 0
+			 reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_CSUM_OFFLOAD;
+#endif
+		}
+	}
+
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_RETURN_SRC_INTERFACE_CHECK) {
+		reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK;
+	}
+
+	if (msg->rule_flags & SFE_RULE_CREATE_FLAG_RETURN_SRC_INTERFACE_CHECK_NO_FLUSH) {
+		reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK_NO_FLUSH;
+	}
+
+	/*
+	 * For the non-arp interface, we don't write L2 HDR.
+	 * Excluding PPPoE from this, since we are now supporting PPPoE encap/decap.
+	 */
+	if (sfe_ipv6_xmit_eth_type_check(src_dev, reply_cm->flags)) {
+
+		/*
+		 * Check whether the rule has configured a specific source MAC address to use.
+		 * This is needed when virtual L3 interfaces such as br-lan, macvlan, vlan are used during egress
+		 */
+		if (msg->rule_flags & SFE_RULE_CREATE_FLAG_BRIDGE_FLOW) {
+			ether_addr_copy((u8 *)reply_cm->xmit_src_mac, (u8 *)msg->conn_rule.return_mac);
+		} else {
+			if ((msg->valid_flags & SFE_RULE_CREATE_SRC_MAC_VALID) &&
+			    (msg->src_mac_rule.mac_valid_flags & SFE_SRC_MAC_FLOW_VALID)) {
+				ether_addr_copy((u8 *)reply_cm->xmit_src_mac, (u8 *)msg->src_mac_rule.flow_src_mac);
+			} else {
+				ether_addr_copy((u8 *)reply_cm->xmit_src_mac, (u8 *)src_dev->dev_addr);
+			}
+		}
+
+		ether_addr_copy((u8 *)reply_cm->xmit_dest_mac, (u8 *)msg->conn_rule.flow_mac);
+
+		reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_L2_HDR;
+		reply_cm->l2_hdr_size += ETH_HLEN;
+
+		/*
+		 * If our dev writes Ethernet headers then we can write a really fast
+		 * version.
+		 */
+		if (src_dev->header_ops) {
+			if (src_dev->header_ops->create == eth_header) {
+				reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR;
+			}
+		}
+	}
+
+	/*
+	 * No support for NAT in ipv6
+	 */
+
+	/*
+	 * Initialize the protocol-specific information that we track.
+	 */
+	switch (tuple->protocol) {
+	case IPPROTO_TCP:
+		original_cm->protocol_state.tcp.win_scale = msg->tcp_rule.flow_window_scale;
+		original_cm->protocol_state.tcp.max_win = msg->tcp_rule.flow_max_window ? msg->tcp_rule.flow_max_window : 1;
+		original_cm->protocol_state.tcp.end = msg->tcp_rule.flow_end;
+		original_cm->protocol_state.tcp.max_end = msg->tcp_rule.flow_max_end;
+		reply_cm->protocol_state.tcp.win_scale = msg->tcp_rule.return_window_scale;
+		reply_cm->protocol_state.tcp.max_win = msg->tcp_rule.return_max_window ? msg->tcp_rule.return_max_window : 1;
+		reply_cm->protocol_state.tcp.end = msg->tcp_rule.return_end;
+		reply_cm->protocol_state.tcp.max_end = msg->tcp_rule.return_max_end;
+		if (msg->rule_flags & SFE_RULE_CREATE_FLAG_NO_SEQ_CHECK) {
+			original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK;
+			reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK;
+		}
+		break;
+	}
+
+	/*
+	 * Fill in the ipv6_connection object.
+	 */
+	c->protocol = tuple->protocol;
+	c->src_ip[0] = *(struct sfe_ipv6_addr *)tuple->flow_ip;
+	c->src_ip_xlate[0] = *(struct sfe_ipv6_addr *)tuple->flow_ip;
+	c->src_port = tuple->flow_ident;
+	c->src_port_xlate = tuple->flow_ident;
+	c->original_dev = src_dev;
+	c->original_match = original_cm;
+
+	c->dest_ip[0] = *(struct sfe_ipv6_addr *)tuple->return_ip;
+	c->dest_ip_xlate[0] = *(struct sfe_ipv6_addr *)tuple->return_ip;
+	c->dest_port = tuple->return_ident;
+	c->dest_port_xlate = tuple->return_ident;
+
+	c->reply_dev = dest_dev;
+	c->reply_match = reply_cm;
+	c->debug_read_seq = 0;
+	c->last_sync_jiffies = get_jiffies_64();
+	c->removed = false;
+
+	sfe_ipv6_connection_match_compute_translations(original_cm);
+	sfe_ipv6_connection_match_compute_translations(reply_cm);
+	sfe_ipv6_insert_connection(si, c);
+
+	spin_unlock_bh(&si->lock);
+
+	/*
+	 * We have everything we need!
+	 */
+	DEBUG_INFO("new connection - p: %d\n"
+		   "  s: %s:%pxM(%pxM):%pI6(%pI6):%u(%u)\n"
+		   "  d: %s:%pxM(%pxM):%pI6(%pI6):%u(%u)\n",
+		   tuple->protocol,
+		   src_dev->name, msg->conn_rule.flow_mac, NULL,
+		   (void *)tuple->flow_ip, (void *)tuple->flow_ip, ntohs(tuple->flow_ident), ntohs(tuple->flow_ident),
+		   dest_dev->name, NULL, msg->conn_rule.return_mac,
+		   (void *)tuple->return_ip, (void *)tuple->return_ip, ntohs(tuple->return_ident), ntohs(tuple->return_ident));
+
+	return 0;
+}
+
+/*
+ * sfe_ipv6_destroy_rule()
+ *	Destroy a forwarding rule.
+ */
+void sfe_ipv6_destroy_rule(struct sfe_ipv6_rule_destroy_msg *msg)
+{
+	struct sfe_ipv6 *si = &__si6;
+	struct sfe_ipv6_connection *c;
+	bool ret;
+	struct sfe_ipv6_5tuple *tuple = &msg->tuple;
+
+	this_cpu_inc(si->stats_pcpu->connection_destroy_requests64);
+
+	spin_lock_bh(&si->lock);
+
+	/*
+	 * Check to see if we have a flow that matches the rule we're trying
+	 * to destroy.  If there isn't then we can't destroy it.
+	 */
+	c = sfe_ipv6_find_connection(si, tuple->protocol, (struct sfe_ipv6_addr *)tuple->flow_ip, tuple->flow_ident,
+				     (struct sfe_ipv6_addr *)tuple->return_ip, tuple->return_ident);
+	if (!c) {
+		spin_unlock_bh(&si->lock);
+
+		this_cpu_inc(si->stats_pcpu->connection_destroy_misses64);
+
+		DEBUG_TRACE("connection does not exist - p: %d, s: %pI6:%u, d: %pI6:%u\n",
+			    tuple->protocol, tuple->flow_ip, ntohs(tuple->flow_ident),
+			    tuple->return_ip, ntohs(tuple->return_ident));
+		return;
+	}
+
+	/*
+	 * Remove our connection details from the hash tables.
+	 */
+	ret = sfe_ipv6_remove_connection(si, c);
+	spin_unlock_bh(&si->lock);
+
+	if (ret) {
+		sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_DESTROY);
+	}
+
+	DEBUG_INFO("connection destroyed - p: %d, s: %pI6:%u, d: %pI6:%u\n",
+		   tuple->protocol, tuple->flow_ip, ntohs(tuple->flow_ident),
+		   tuple->return_ip, ntohs(tuple->return_ident));
+}
+
+/*
+ * sfe_ipv6_register_sync_rule_callback()
+ *	Register a callback for rule synchronization.
+ */
+void sfe_ipv6_register_sync_rule_callback(sfe_sync_rule_callback_t sync_rule_callback)
+{
+	struct sfe_ipv6 *si = &__si6;
+
+	spin_lock_bh(&si->lock);
+	rcu_assign_pointer(si->sync_rule_callback, sync_rule_callback);
+	spin_unlock_bh(&si->lock);
+}
+
+/*
+ * sfe_ipv6_get_debug_dev()
+ */
+static ssize_t sfe_ipv6_get_debug_dev(struct device *dev,
+				      struct device_attribute *attr,
+				      char *buf)
+{
+	struct sfe_ipv6 *si = &__si6;
+	ssize_t count;
+	int num;
+
+	spin_lock_bh(&si->lock);
+	num = si->debug_dev;
+	spin_unlock_bh(&si->lock);
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%d\n", num);
+	return count;
+}
+
+/*
+ * sfe_ipv6_destroy_all_rules_for_dev()
+ *	Destroy all connections that match a particular device.
+ *
+ * If we pass dev as NULL then this destroys all connections.
+ */
+void sfe_ipv6_destroy_all_rules_for_dev(struct net_device *dev)
+{
+	struct sfe_ipv6 *si = &__si6;
+	struct sfe_ipv6_connection *c;
+	bool ret;
+
+another_round:
+	spin_lock_bh(&si->lock);
+
+	for (c = si->all_connections_head; c; c = c->all_connections_next) {
+		/*
+		 * Does this connection relate to the device we are destroying?
+		 */
+		if (!dev
+		    || (dev == c->original_dev)
+		    || (dev == c->reply_dev)) {
+			break;
+		}
+	}
+
+	if (c) {
+		ret = sfe_ipv6_remove_connection(si, c);
+	}
+
+	spin_unlock_bh(&si->lock);
+
+	if (c) {
+		if (ret) {
+			sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_DESTROY);
+		}
+		goto another_round;
+	}
+}
+
+/*
+ * sfe_ipv6_periodic_sync()
+ */
+static void sfe_ipv6_periodic_sync(struct work_struct *work)
+{
+	struct sfe_ipv6 *si = container_of((struct delayed_work *)work, struct sfe_ipv6, sync_dwork);
+	u64 now_jiffies;
+	int quota;
+	sfe_sync_rule_callback_t sync_rule_callback;
+	struct sfe_ipv6_connection *c;
+
+	now_jiffies = get_jiffies_64();
+
+	rcu_read_lock();
+	sync_rule_callback = rcu_dereference(si->sync_rule_callback);
+	if (!sync_rule_callback) {
+		rcu_read_unlock();
+		goto done;
+	}
+
+	spin_lock_bh(&si->lock);
+
+	/*
+	 * If we have reached the end of the connection list, walk from
+	 * the connection head.
+	 */
+	c = si->wc_next;
+	if (unlikely(!c)) {
+		c = si->all_connections_head;
+	}
+	/*
+	 * Get an estimate of the number of connections to parse in this sync.
+	 */
+	quota = (si->num_connections + 63) / 64;
+
+	/*
+	 * Walk the "all connection" list and sync the connection state.
+	 */
+	while (likely(c && quota)) {
+		struct sfe_ipv6_connection_match *cm;
+		struct sfe_ipv6_connection_match *counter_cm;
+		struct sfe_connection_sync sis;
+
+		cm = c->original_match;
+		counter_cm = c->reply_match;
+
+		/*
+		 * Didn't receive packets in the origial direction or reply
+		 * direction, move to the next connection.
+		 */
+		if (!atomic_read(&cm->rx_packet_count) && !atomic_read(&counter_cm->rx_packet_count)) {
+			c = c->all_connections_next;
+			continue;
+		}
+
+		quota--;
+
+		/*
+		 * Sync the connection state.
+		 */
+		sfe_ipv6_gen_sync_connection(si, c, &sis, SFE_SYNC_REASON_STATS, now_jiffies);
+
+		si->wc_next = c->all_connections_next;
+
+		spin_unlock_bh(&si->lock);
+		sync_rule_callback(&sis);
+		spin_lock_bh(&si->lock);
+
+		/*
+		 * c must be set and used in the same lock/unlock window;
+		 * because c could be removed when we don't hold the lock,
+		 * so delay grabbing until after the callback and relock.
+		 */
+		c = si->wc_next;
+	}
+
+	/*
+	 * At the end of loop, put wc_next to the connection we left
+	 */
+	si->wc_next = c;
+
+	spin_unlock_bh(&si->lock);
+	rcu_read_unlock();
+
+done:
+	schedule_delayed_work_on(si->work_cpu, (struct delayed_work *)work, ((HZ + 99) / 100));
+}
+
+/*
+ * sfe_ipv6_debug_dev_read_start()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv6_debug_dev_read_start(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length,
+					  int *total_read, struct sfe_ipv6_debug_xml_write_state *ws)
+{
+	int bytes_read;
+
+	si->debug_read_seq++;
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "<sfe_ipv6>\n");
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	ws->state++;
+	return true;
+}
+
+/*
+ * sfe_ipv6_debug_dev_read_connections_start()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv6_debug_dev_read_connections_start(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length,
+						      int *total_read, struct sfe_ipv6_debug_xml_write_state *ws)
+{
+	int bytes_read;
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t<connections>\n");
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	ws->state++;
+	return true;
+}
+
+/*
+ * sfe_ipv6_debug_dev_read_connections_connection()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv6_debug_dev_read_connections_connection(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length,
+							   int *total_read, struct sfe_ipv6_debug_xml_write_state *ws)
+{
+	struct sfe_ipv6_connection *c;
+	struct sfe_ipv6_connection_match *original_cm;
+	struct sfe_ipv6_connection_match *reply_cm;
+	int bytes_read;
+	int protocol;
+	struct net_device *src_dev;
+	struct sfe_ipv6_addr src_ip;
+	struct sfe_ipv6_addr src_ip_xlate;
+	__be16 src_port;
+	__be16 src_port_xlate;
+	u64 src_rx_packets;
+	u64 src_rx_bytes;
+	struct net_device *dest_dev;
+	struct sfe_ipv6_addr dest_ip;
+	struct sfe_ipv6_addr dest_ip_xlate;
+	__be16 dest_port;
+	__be16 dest_port_xlate;
+	u64 dest_rx_packets;
+	u64 dest_rx_bytes;
+	u64 last_sync_jiffies;
+	u32 src_mark, dest_mark,  src_priority, dest_priority, src_dscp, dest_dscp;
+	u32 packet, byte, original_cm_flags;
+	u16 pppoe_session_id;
+	u8 pppoe_remote_mac[ETH_ALEN];
+	u32 original_fast_xmit, reply_fast_xmit;
+#ifdef CONFIG_NF_FLOW_COOKIE
+	int src_flow_cookie, dst_flow_cookie;
+#endif
+
+	spin_lock_bh(&si->lock);
+
+	for (c = si->all_connections_head; c; c = c->all_connections_next) {
+		if (c->debug_read_seq < si->debug_read_seq) {
+			c->debug_read_seq = si->debug_read_seq;
+			break;
+		}
+	}
+
+	/*
+	 * If there were no connections then move to the next state.
+	 */
+	if (!c) {
+		spin_unlock_bh(&si->lock);
+		ws->state++;
+		return true;
+	}
+
+	original_cm = c->original_match;
+	reply_cm = c->reply_match;
+
+	protocol = c->protocol;
+	src_dev = c->original_dev;
+	src_ip = c->src_ip[0];
+	src_ip_xlate = c->src_ip_xlate[0];
+	src_port = c->src_port;
+	src_port_xlate = c->src_port_xlate;
+	src_priority = original_cm->priority;
+	src_dscp = original_cm->dscp >> SFE_IPV6_DSCP_SHIFT;
+
+	sfe_ipv6_connection_match_update_summary_stats(original_cm, &packet, &byte);
+	sfe_ipv6_connection_match_update_summary_stats(reply_cm, &packet, &byte);
+
+	src_rx_packets = original_cm->rx_packet_count64;
+	src_rx_bytes = original_cm->rx_byte_count64;
+	src_mark = original_cm->mark;
+	original_fast_xmit = original_cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT;
+	dest_dev = c->reply_dev;
+	dest_ip = c->dest_ip[0];
+	dest_ip_xlate = c->dest_ip_xlate[0];
+	dest_port = c->dest_port;
+	dest_port_xlate = c->dest_port_xlate;
+	dest_priority = reply_cm->priority;
+	dest_dscp = reply_cm->dscp >> SFE_IPV6_DSCP_SHIFT;
+	dest_rx_packets = reply_cm->rx_packet_count64;
+	dest_rx_bytes = reply_cm->rx_byte_count64;
+	last_sync_jiffies = get_jiffies_64() - c->last_sync_jiffies;
+	original_cm_flags = original_cm->flags;
+	pppoe_session_id = original_cm->pppoe_session_id;
+	ether_addr_copy(pppoe_remote_mac, original_cm->pppoe_remote_mac);
+	dest_mark = reply_cm->mark;
+	reply_fast_xmit = reply_cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT;
+#ifdef CONFIG_NF_FLOW_COOKIE
+	src_flow_cookie = original_cm->flow_cookie;
+	dst_flow_cookie = reply_cm->flow_cookie;
+#endif
+	spin_unlock_bh(&si->lock);
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t\t<connection "
+				"protocol=\"%u\" "
+				"src_dev=\"%s\" "
+				"src_ip=\"%pI6\" src_ip_xlate=\"%pI6\" "
+				"src_port=\"%u\" src_port_xlate=\"%u\" "
+				"src_priority=\"%u\" src_dscp=\"%u\" "
+				"src_rx_pkts=\"%llu\" src_rx_bytes=\"%llu\" "
+				"src_mark=\"%08x\" "
+				"src_fast_xmit=\"%s\" "
+				"dest_dev=\"%s\" "
+				"dest_ip=\"%pI6\" dest_ip_xlate=\"%pI6\" "
+				"dest_port=\"%u\" dest_port_xlate=\"%u\" "
+				"dest_priority=\"%u\" dest_dscp=\"%u\" "
+				"dest_rx_pkts=\"%llu\" dest_rx_bytes=\"%llu\" "
+				"dest_mark=\"%08x\" "
+				"reply_fast_xmit=\"%s\" "
+#ifdef CONFIG_NF_FLOW_COOKIE
+				"src_flow_cookie=\"%d\" dst_flow_cookie=\"%d\" "
+#endif
+				"last_sync=\"%llu\" ",
+				protocol,
+				src_dev->name,
+				&src_ip, &src_ip_xlate,
+				ntohs(src_port), ntohs(src_port_xlate),
+				src_priority, src_dscp,
+				src_rx_packets, src_rx_bytes,
+				src_mark,
+				original_fast_xmit ? "Yes" : "No",
+				dest_dev->name,
+				&dest_ip, &dest_ip_xlate,
+				ntohs(dest_port), ntohs(dest_port_xlate),
+				dest_priority, dest_dscp,
+				dest_rx_packets, dest_rx_bytes,
+				dest_mark,
+				reply_fast_xmit ? "Yes" : "No",
+#ifdef CONFIG_NF_FLOW_COOKIE
+				src_flow_cookie, dst_flow_cookie,
+#endif
+				last_sync_jiffies);
+
+	if (original_cm_flags &= (SFE_IPV6_CONNECTION_MATCH_FLAG_PPPOE_DECAP | SFE_IPV6_CONNECTION_MATCH_FLAG_PPPOE_ENCAP)) {
+		bytes_read += snprintf(msg + bytes_read, CHAR_DEV_MSG_SIZE, "pppoe_session_id=\"%u\" pppoe_server_MAC=\"%pM\" ",
+			pppoe_session_id, pppoe_remote_mac);
+	}
+
+	bytes_read += snprintf(msg + bytes_read, CHAR_DEV_MSG_SIZE, ")/>\n");
+
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	return true;
+}
+
+/*
+ * sfe_ipv6_debug_dev_read_connections_end()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv6_debug_dev_read_connections_end(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length,
+						    int *total_read, struct sfe_ipv6_debug_xml_write_state *ws)
+{
+	int bytes_read;
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t</connections>\n");
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	ws->state++;
+	return true;
+}
+
+/*
+ * sfe_ipv6_debug_dev_read_exceptions_start()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv6_debug_dev_read_exceptions_start(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length,
+						     int *total_read, struct sfe_ipv6_debug_xml_write_state *ws)
+{
+	int bytes_read;
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t<exceptions>\n");
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	ws->state++;
+	return true;
+}
+
+/*
+ * sfe_ipv6_debug_dev_read_exceptions_exception()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv6_debug_dev_read_exceptions_exception(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length,
+							 int *total_read, struct sfe_ipv6_debug_xml_write_state *ws)
+{
+	int i;
+	u64 val = 0;
+
+	for_each_possible_cpu(i) {
+		const struct sfe_ipv6_stats *s = per_cpu_ptr(si->stats_pcpu, i);
+			val += s->exception_events64[ws->iter_exception];
+	}
+
+	if (val) {
+		int bytes_read;
+
+		bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE,
+				      "\t\t<exception name=\"%s\" count=\"%llu\" />\n",
+				      sfe_ipv6_exception_events_string[ws->iter_exception],
+				      val);
+
+		if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+			return false;
+		}
+
+		*length -= bytes_read;
+		*total_read += bytes_read;
+	}
+
+	ws->iter_exception++;
+	if (ws->iter_exception >= SFE_IPV6_EXCEPTION_EVENT_LAST) {
+		ws->iter_exception = 0;
+		ws->state++;
+	}
+
+	return true;
+}
+
+/*
+ * sfe_ipv6_debug_dev_read_exceptions_end()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv6_debug_dev_read_exceptions_end(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length,
+						   int *total_read, struct sfe_ipv6_debug_xml_write_state *ws)
+{
+	int bytes_read;
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t</exceptions>\n");
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	ws->state++;
+	return true;
+}
+
+/*
+ * sfe_ipv6_debug_dev_read_stats()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv6_debug_dev_read_stats(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length,
+					  int *total_read, struct sfe_ipv6_debug_xml_write_state *ws)
+{
+	int bytes_read;
+	struct sfe_ipv6_stats stats;
+	unsigned int num_conn;
+
+	sfe_ipv6_update_summary_stats(si, &stats);
+
+	spin_lock_bh(&si->lock);
+	num_conn = si->num_connections;
+	spin_unlock_bh(&si->lock);
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t<stats "
+			      "num_connections=\"%u\" "
+			      "pkts_dropped=\"%llu\" "
+			      "pkts_fast_xmited=\"%llu\" "
+			      "pkts_forwarded=\"%llu\" pkts_not_forwarded=\"%llu\" "
+			      "create_requests=\"%llu\" create_collisions=\"%llu\" "
+			      "create_failures=\"%llu\" "
+			      "destroy_requests=\"%llu\" destroy_misses=\"%llu\" "
+			      "flushes=\"%llu\" "
+			      "hash_hits=\"%llu\" hash_reorders=\"%llu\" "
+			      "pppoe_encap_pkts_fwded=\"%llu\" "
+			      "pppoe_decap_pkts_fwded=\"%llu\" "
+			      "pppoe_bridge_pkts_fwded=\"%llu\" />\n",
+
+				num_conn,
+				stats.packets_dropped64,
+				stats.packets_fast_xmited64,
+				stats.packets_forwarded64,
+				stats.packets_not_forwarded64,
+				stats.connection_create_requests64,
+				stats.connection_create_collisions64,
+				stats.connection_create_failures64,
+				stats.connection_destroy_requests64,
+				stats.connection_destroy_misses64,
+				stats.connection_flushes64,
+				stats.connection_match_hash_hits64,
+				stats.connection_match_hash_reorders64,
+				stats.pppoe_encap_packets_forwarded64,
+				stats.pppoe_decap_packets_forwarded64,
+				stats.pppoe_bridge_packets_forwarded64);
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	ws->state++;
+	return true;
+}
+
+/*
+ * sfe_ipv6_debug_dev_read_end()
+ *	Generate part of the XML output.
+ */
+static bool sfe_ipv6_debug_dev_read_end(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length,
+					int *total_read, struct sfe_ipv6_debug_xml_write_state *ws)
+{
+	int bytes_read;
+
+	bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "</sfe_ipv6>\n");
+	if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) {
+		return false;
+	}
+
+	*length -= bytes_read;
+	*total_read += bytes_read;
+
+	ws->state++;
+	return true;
+}
+
+/*
+ * Array of write functions that write various XML elements that correspond to
+ * our XML output state machine.
+ */
+static sfe_ipv6_debug_xml_write_method_t sfe_ipv6_debug_xml_write_methods[SFE_IPV6_DEBUG_XML_STATE_DONE] = {
+	sfe_ipv6_debug_dev_read_start,
+	sfe_ipv6_debug_dev_read_connections_start,
+	sfe_ipv6_debug_dev_read_connections_connection,
+	sfe_ipv6_debug_dev_read_connections_end,
+	sfe_ipv6_debug_dev_read_exceptions_start,
+	sfe_ipv6_debug_dev_read_exceptions_exception,
+	sfe_ipv6_debug_dev_read_exceptions_end,
+	sfe_ipv6_debug_dev_read_stats,
+	sfe_ipv6_debug_dev_read_end,
+};
+
+/*
+ * sfe_ipv6_debug_dev_read()
+ *	Send info to userspace upon read request from user
+ */
+static ssize_t sfe_ipv6_debug_dev_read(struct file *filp, char *buffer, size_t length, loff_t *offset)
+{
+	char msg[CHAR_DEV_MSG_SIZE];
+	int total_read = 0;
+	struct sfe_ipv6_debug_xml_write_state *ws;
+	struct sfe_ipv6 *si = &__si6;
+
+	ws = (struct sfe_ipv6_debug_xml_write_state *)filp->private_data;
+	while ((ws->state != SFE_IPV6_DEBUG_XML_STATE_DONE) && (length > CHAR_DEV_MSG_SIZE)) {
+		if ((sfe_ipv6_debug_xml_write_methods[ws->state])(si, buffer, msg, &length, &total_read, ws)) {
+			continue;
+		}
+	}
+	return total_read;
+}
+
+/*
+ * sfe_ipv6_debug_dev_open()
+ */
+static int sfe_ipv6_debug_dev_open(struct inode *inode, struct file *file)
+{
+	struct sfe_ipv6_debug_xml_write_state *ws;
+
+	ws = (struct sfe_ipv6_debug_xml_write_state *)file->private_data;
+	if (ws) {
+		return 0;
+	}
+
+	ws = kzalloc(sizeof(struct sfe_ipv6_debug_xml_write_state), GFP_KERNEL);
+	if (!ws) {
+		return -ENOMEM;
+	}
+
+	ws->state = SFE_IPV6_DEBUG_XML_STATE_START;
+	file->private_data = ws;
+
+	return 0;
+}
+
+/*
+ * sfe_ipv6_debug_dev_release()
+ */
+static int sfe_ipv6_debug_dev_release(struct inode *inode, struct file *file)
+{
+	struct sfe_ipv6_debug_xml_write_state *ws;
+
+	ws = (struct sfe_ipv6_debug_xml_write_state *)file->private_data;
+	if (ws) {
+		/*
+		 * We've finished with our output so free the write state.
+		 */
+		kfree(ws);
+		file->private_data = NULL;
+	}
+
+	return 0;
+}
+
+/*
+ * File operations used in the debug char device
+ */
+static struct file_operations sfe_ipv6_debug_dev_fops = {
+	.read = sfe_ipv6_debug_dev_read,
+	.open = sfe_ipv6_debug_dev_open,
+	.release = sfe_ipv6_debug_dev_release
+};
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+/*
+ * sfe_ipv6_register_flow_cookie_cb
+ *	register a function in SFE to let SFE use this function to configure flow cookie for a flow
+ *
+ * Hardware driver which support flow cookie should register a callback function in SFE. Then SFE
+ * can use this function to configure flow cookie for a flow.
+ * return: 0, success; !=0, fail
+ */
+int sfe_ipv6_register_flow_cookie_cb(sfe_ipv6_flow_cookie_set_func_t cb)
+{
+	struct sfe_ipv6 *si = &__si6;
+
+	BUG_ON(!cb);
+
+	if (si->flow_cookie_set_func) {
+		return -1;
+	}
+
+	rcu_assign_pointer(si->flow_cookie_set_func, cb);
+	return 0;
+}
+
+/*
+ * sfe_ipv6_unregister_flow_cookie_cb
+ *	unregister function which is used to configure flow cookie for a flow
+ *
+ * return: 0, success; !=0, fail
+ */
+int sfe_ipv6_unregister_flow_cookie_cb(sfe_ipv6_flow_cookie_set_func_t cb)
+{
+	struct sfe_ipv6 *si = &__si6;
+
+	RCU_INIT_POINTER(si->flow_cookie_set_func, NULL);
+	return 0;
+}
+
+/*
+ * sfe_ipv6_get_flow_cookie()
+ */
+static ssize_t sfe_ipv6_get_flow_cookie(struct device *dev,
+					struct device_attribute *attr,
+					char *buf)
+{
+	struct sfe_ipv6 *si = &__si6;
+	return snprintf(buf, (ssize_t)PAGE_SIZE, "%d\n", si->flow_cookie_enable);
+}
+
+/*
+ * sfe_ipv6_set_flow_cookie()
+ */
+static ssize_t sfe_ipv6_set_flow_cookie(struct device *dev,
+					struct device_attribute *attr,
+					const char *buf, size_t size)
+{
+	struct sfe_ipv6 *si = &__si6;
+	si->flow_cookie_enable = strict_strtol(buf, NULL, 0);
+
+	return size;
+}
+
+/*
+ * sysfs attributes.
+ */
+static const struct device_attribute sfe_ipv6_flow_cookie_attr =
+	__ATTR(flow_cookie_enable, S_IWUSR | S_IRUGO, sfe_ipv6_get_flow_cookie, sfe_ipv6_set_flow_cookie);
+#endif /*CONFIG_NF_FLOW_COOKIE*/
+
+/*
+ * sfe_ipv6_get_cpu()
+ */
+static ssize_t sfe_ipv6_get_cpu(struct device *dev,
+					struct device_attribute *attr,
+					char *buf)
+{
+	struct sfe_ipv6 *si = &__si6;
+	return snprintf(buf, (ssize_t)PAGE_SIZE, "%d\n", si->work_cpu);
+}
+
+/*
+ * sfe_ipv6_set_cpu()
+ */
+static ssize_t sfe_ipv6_set_cpu(struct device *dev,
+					struct device_attribute *attr,
+					const char *buf, size_t size)
+{
+	struct sfe_ipv6 *si = &__si6;
+	int work_cpu;
+
+	work_cpu = simple_strtol(buf, NULL, 0);
+	if ((work_cpu >= 0) && (work_cpu <= NR_CPUS)) {
+		si->work_cpu = work_cpu;
+	} else {
+		dev_err(dev, "%s is not in valid range[0,%d]", buf, NR_CPUS);
+	}
+
+	return size;
+}
+/*
+ * sysfs attributes.
+ */
+static const struct device_attribute sfe_ipv6_cpu_attr =
+	__ATTR(stat_work_cpu, S_IWUSR | S_IRUGO, sfe_ipv6_get_cpu, sfe_ipv6_set_cpu);
+
+/*
+ * DSCP rewrite table
+ */
+static ssize_t
+sfe_ipv6_get_dscp_rewrite_mark_to_match(struct device *dev,
+					struct device_attribute *attr,
+					char *buf)
+{
+	struct sfe_ipv6 *si = &__si6;
+	return snprintf(buf, (ssize_t)PAGE_SIZE, "0x%x\n",
+			si->dscp_rewrite_mark_to_match);
+}
+
+static ssize_t
+sfe_ipv6_set_dscp_rewrite_mark_to_match(struct device *dev,
+					struct device_attribute *attr,
+					const char *buf, size_t size)
+{
+	struct sfe_ipv6 *si = &__si6;
+	int ret;
+	u32 mark_to_match;
+
+	ret = kstrtou32(buf, 0, &mark_to_match);
+	if (ret)
+		return ret;
+	si->dscp_rewrite_mark_to_match = mark_to_match;
+	return size;
+}
+
+static const struct device_attribute sfe_ipv6_dscp_rewrite_mark_to_match_attr =
+	__ATTR(dscp_rewrite_mark_to_match, S_IWUSR | S_IRUGO,
+	       sfe_ipv6_get_dscp_rewrite_mark_to_match,
+	       sfe_ipv6_set_dscp_rewrite_mark_to_match);
+
+static ssize_t
+sfe_ipv6_get_dscp_rewrite_dscp_to_set(struct device *dev,
+				      struct device_attribute *attr,
+				      char *buf)
+{
+	struct sfe_ipv6 *si = &__si6;
+	return snprintf(buf, (ssize_t)PAGE_SIZE, "0x%x\n",
+			si->dscp_rewrite_dscp_to_set >> SFE_IPV6_DSCP_SHIFT);
+}
+
+static ssize_t
+sfe_ipv6_set_dscp_rewrite_dscp_to_set(struct device *dev,
+				      struct device_attribute *attr,
+				      const char *buf, size_t size)
+{
+	struct sfe_ipv6 *si = &__si6;
+	int ret;
+	u32 dscp_to_set;
+
+	ret = kstrtou32(buf, 0, &dscp_to_set);
+	if (ret)
+		return ret;
+	si->dscp_rewrite_dscp_to_set = dscp_to_set << SFE_IPV6_DSCP_SHIFT;
+	return size;
+}
+
+static const struct device_attribute sfe_ipv6_dscp_rewrite_dscp_to_set_attr =
+	__ATTR(dscp_rewrite_dscp_to_set, S_IWUSR | S_IRUGO,
+	       sfe_ipv6_get_dscp_rewrite_dscp_to_set,
+	       sfe_ipv6_set_dscp_rewrite_dscp_to_set);
+
+/*
+ * sfe_ipv6_hash_init()
+ *	Initialize conn match hash lists
+ */
+static void sfe_ipv6_conn_match_hash_init(struct sfe_ipv6 *si, int len)
+{
+	struct hlist_head *hash_list = si->hlist_conn_match_hash_head;
+	int i;
+
+	for (i = 0; i < len; i++) {
+		INIT_HLIST_HEAD(&hash_list[i]);
+	}
+}
+
+#ifdef SFE_PROCESS_LOCAL_OUT
+/*
+ * sfe_ipv6_local_out()
+ *	Called for packets from ip_local_out() - post encapsulation & other packets
+ */
+static unsigned int sfe_ipv6_local_out(void *priv,
+				struct sk_buff *skb,
+				const struct nf_hook_state *nhs)
+{
+	struct sfe_l2_info l2_info = {0};
+
+	DEBUG_TRACE("sfe: sfe_ipv6_local_out hook called.\n");
+
+	if (likely(skb->skb_iif)) {
+		return sfe_ipv6_recv(skb->dev, skb, &l2_info, true) ? NF_STOLEN : NF_ACCEPT;
+	}
+
+	return NF_ACCEPT;
+}
+
+/*
+ * struct nf_hook_ops sfe_ipv6_ops_local_out[]
+ *	Hooks into netfilter local out packet monitoring points.
+ */
+static struct nf_hook_ops sfe_ipv6_ops_local_out[] __read_mostly = {
+
+	/*
+	 * Local out routing hook is used to monitor packets.
+	 */
+	{
+		.hook           = sfe_ipv6_local_out,
+		.pf             = PF_INET6,
+		.hooknum        = NF_INET_LOCAL_OUT,
+		.priority       = NF_IP6_PRI_FIRST,
+	},
+};
+#endif
+
+/*
+ * sfe_ipv6_init()
+ */
+int sfe_ipv6_init(void)
+{
+	struct sfe_ipv6 *si = &__si6;
+	int result = -1;
+
+	DEBUG_INFO("SFE IPv6 init\n");
+
+	sfe_ipv6_conn_match_hash_init(si, ARRAY_SIZE(si->hlist_conn_match_hash_head));
+
+	si->stats_pcpu = alloc_percpu_gfp(struct sfe_ipv6_stats, GFP_KERNEL | __GFP_ZERO);
+	if (!si->stats_pcpu) {
+		DEBUG_ERROR("failed to allocate stats memory for sfe_ipv6\n");
+		goto exit0;
+	}
+
+	/*
+	 * Create sys/sfe_ipv6
+	 */
+	si->sys_ipv6 = kobject_create_and_add("sfe_ipv6", NULL);
+	if (!si->sys_ipv6) {
+		DEBUG_ERROR("failed to register sfe_ipv6\n");
+		goto exit1;
+	}
+
+	/*
+	 * Create files, one for each parameter supported by this module.
+	 */
+	result = sysfs_create_file(si->sys_ipv6, &sfe_ipv6_debug_dev_attr.attr);
+	if (result) {
+		DEBUG_ERROR("failed to register debug dev file: %d\n", result);
+		goto exit2;
+	}
+
+	result = sysfs_create_file(si->sys_ipv6, &sfe_ipv6_cpu_attr.attr);
+	if (result) {
+		DEBUG_ERROR("failed to register debug dev file: %d\n", result);
+		goto exit3;
+	}
+
+	result = sysfs_create_file(si->sys_ipv6,
+				   &sfe_ipv6_dscp_rewrite_mark_to_match_attr.attr);
+	if (result) {
+		DEBUG_ERROR("failed to register DSCP rewrite mark_to_match file: %d\n",
+			    result);
+		goto exit4;
+	}
+	result = sysfs_create_file(si->sys_ipv6,
+				   &sfe_ipv6_dscp_rewrite_dscp_to_set_attr.attr);
+	if (result) {
+		DEBUG_ERROR("failed to register DSCP rewrite dscp_to_set file: %d\n",
+			    result);
+		goto exit5;
+	}
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+	result = sysfs_create_file(si->sys_ipv6, &sfe_ipv6_flow_cookie_attr.attr);
+	if (result) {
+		DEBUG_ERROR("failed to register flow cookie enable file: %d\n", result);
+		goto exit6;
+	}
+#endif /* CONFIG_NF_FLOW_COOKIE */
+
+#ifdef SFE_PROCESS_LOCAL_OUT
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	result = nf_register_hooks(sfe_ipv6_ops_local_out, ARRAY_SIZE(sfe_ipv6_ops_local_out));
+#else
+	result = nf_register_net_hooks(&init_net, sfe_ipv6_ops_local_out, ARRAY_SIZE(sfe_ipv6_ops_local_out));
+#endif
+	if (result < 0) {
+		DEBUG_ERROR("can't register nf local out hook: %d\n", result);
+		goto exit7;
+	} else {
+		DEBUG_ERROR("Register nf local out hook success: %d\n", result);
+	}
+#endif
+
+	/*
+	 * Register our debug char device.
+	 */
+	result = register_chrdev(0, "sfe_ipv6", &sfe_ipv6_debug_dev_fops);
+	if (result < 0) {
+		DEBUG_ERROR("Failed to register chrdev: %d\n", result);
+		goto exit8;
+	}
+
+	si->debug_dev = result;
+	si->work_cpu = WORK_CPU_UNBOUND;
+
+	/*
+	 * Create work to handle periodic statistics.
+	 */
+	INIT_DELAYED_WORK(&(si->sync_dwork), sfe_ipv6_periodic_sync);
+	schedule_delayed_work_on(si->work_cpu, &(si->sync_dwork), ((HZ + 99) / 100));
+	spin_lock_init(&si->lock);
+
+	return 0;
+
+exit8:
+#ifdef SFE_PROCESS_LOCAL_OUT
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	DEBUG_TRACE("sfe: Unregister local out hook\n");
+	nf_unregister_hooks(sfe_ipv6_ops_local_out, ARRAY_SIZE(sfe_ipv6_ops_local_out));
+#else
+	DEBUG_TRACE("sfe: Unregister local out hook\n");
+	nf_unregister_net_hooks(&init_net, sfe_ipv6_ops_local_out, ARRAY_SIZE(sfe_ipv6_ops_local_out));
+#endif
+exit7:
+#endif
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+	sysfs_remove_file(si->sys_ipv6, &sfe_ipv6_flow_cookie_attr.attr);
+
+exit6:
+#endif /* CONFIG_NF_FLOW_COOKIE */
+	sysfs_remove_file(si->sys_ipv6,
+			  &sfe_ipv6_dscp_rewrite_dscp_to_set_attr.attr);
+exit5:
+	sysfs_remove_file(si->sys_ipv6,
+			  &sfe_ipv6_dscp_rewrite_mark_to_match_attr.attr);
+exit4:
+	sysfs_remove_file(si->sys_ipv6, &sfe_ipv6_cpu_attr.attr);
+exit3:
+	sysfs_remove_file(si->sys_ipv6, &sfe_ipv6_debug_dev_attr.attr);
+
+exit2:
+	kobject_put(si->sys_ipv6);
+
+exit1:
+	free_percpu(si->stats_pcpu);
+
+exit0:
+	return result;
+}
+
+/*
+ * sfe_ipv6_exit()
+ */
+void sfe_ipv6_exit(void)
+{
+	struct sfe_ipv6 *si = &__si6;
+
+	DEBUG_INFO("SFE IPv6 exit\n");
+
+	/*
+	 * Destroy all connections.
+	 */
+	sfe_ipv6_destroy_all_rules_for_dev(NULL);
+
+	cancel_delayed_work(&si->sync_dwork);
+
+	unregister_chrdev(si->debug_dev, "sfe_ipv6");
+
+	free_percpu(si->stats_pcpu);
+
+#ifdef SFE_PROCESS_LOCAL_OUT
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	DEBUG_TRACE("sfe: Unregister local out hook\n");
+	nf_unregister_hooks(sfe_ipv6_ops_local_out, ARRAY_SIZE(sfe_ipv6_ops_local_out));
+#else
+	DEBUG_TRACE("sfe: Unregister local out hook\n");
+	nf_unregister_net_hooks(&init_net, sfe_ipv6_ops_local_out, ARRAY_SIZE(sfe_ipv6_ops_local_out));
+#endif
+#endif
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+	sysfs_remove_file(si->sys_ipv6, &sfe_ipv6_flow_cookie_attr.attr);
+#endif /* CONFIG_NF_FLOW_COOKIE */
+	sysfs_remove_file(si->sys_ipv6,
+			  &sfe_ipv6_dscp_rewrite_dscp_to_set_attr.attr);
+	sysfs_remove_file(si->sys_ipv6,
+			  &sfe_ipv6_dscp_rewrite_mark_to_match_attr.attr);
+	sysfs_remove_file(si->sys_ipv6, &sfe_ipv6_cpu_attr.attr);
+
+	sysfs_remove_file(si->sys_ipv6, &sfe_ipv6_debug_dev_attr.attr);
+
+	kobject_put(si->sys_ipv6);
+}
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+EXPORT_SYMBOL(sfe_ipv6_register_flow_cookie_cb);
+EXPORT_SYMBOL(sfe_ipv6_unregister_flow_cookie_cb);
+#endif
diff --git a/qca-nss-sfe/sfe_ipv6.h b/qca-nss-sfe/sfe_ipv6.h
new file mode 100644
index 0000000..9c78f1c
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv6.h
@@ -0,0 +1,471 @@
+/*
+ * sfe_ipv6.h
+ *	Shortcut forwarding engine header file for IPv6.
+ *
+ * Copyright (c) 2015-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __SFE_IPV6_H
+#define __SFE_IPV6_H
+
+#define CHAR_DEV_MSG_SIZE 768
+
+#define SFE_IPV6_DSCP_MASK 0xf03f
+#define SFE_IPV6_DSCP_SHIFT 2
+
+#define	SFE_IPV6_FRAG_OFFSET	0xfff8
+
+/*
+ * generic IPv6 extension header
+ */
+struct sfe_ipv6_ext_hdr {
+	__u8 next_hdr;
+	__u8 hdr_len;
+	__u8 padding[6];
+};
+
+/*
+ * Specifies the lower bound on ACK numbers carried in the TCP header
+ */
+#define SFE_IPV6_TCP_MAX_ACK_WINDOW 65520
+
+/*
+ * IPv6 TCP connection match additional data.
+ */
+struct sfe_ipv6_tcp_connection_match {
+	u8 win_scale;		/* Window scale */
+	u32 max_win;		/* Maximum window size seen */
+	u32 end;		/* Sequence number of the next byte to send (seq + segment length) */
+	u32 max_end;		/* Sequence number of the last byte to ack */
+};
+
+/*
+ * Bit flags for IPv6 connection matching entry.
+ */
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_SRC (1<<0)
+					/* Perform source translation */
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_DEST (1<<1)
+					/* Perform destination translation */
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK (1<<2)
+					/* Ignore TCP sequence numbers */
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR (1<<3)
+					/* Fast Ethernet header write */
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_L2_HDR (1<<4)
+					/* Fast Ethernet header write */
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_PRIORITY_REMARK (1<<5)
+					/* remark priority of SKB */
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_DSCP_REMARK (1<<6)
+					/* remark DSCP of packet */
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_CSUM_OFFLOAD (1<<7)
+					/* checksum offload.*/
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_PPPOE_DECAP (1<<8)
+					/* Indicates that PPPoE should be decapsulated */
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_PPPOE_ENCAP (1<<9)
+					/* Indicates that PPPoE should be encapsulated */
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_BRIDGE_FLOW (1<<10)
+					/* Bridge flow */
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_MARK (1<<11)
+					/* set skb mark*/
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_INSERT_EGRESS_VLAN_TAG (1<<12)
+					/* Insert VLAN tag */
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK (1<<13)
+					/* Source interface check */
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_PASSTHROUGH (1<<14)
+					/* passthrough flow: encap/decap to be skipped for this flow */
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT (1<<15)
+					/* go fast xmit*/
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT_FLOW_CHECKED (1<<16)
+					/* fast xmit checked or not*/
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT_DEV_ADMISSION (1<<17)
+					/* Fast xmit may be possible for this flow, if SFE check passes */
+#define SFE_IPV6_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK_NO_FLUSH (1<<18)
+					/* Source interface check but do not flush the connection */
+
+/*
+ * IPv6 connection matching structure.
+ */
+struct sfe_ipv6_connection_match {
+	/*
+	 * References to other objects.
+	 */
+	struct hlist_node hnode;
+	struct sfe_ipv6_connection *connection;
+	struct sfe_ipv6_connection_match *counter_match;
+					/* Matches the flow in the opposite direction as the one in connection */
+	/*
+	 * Characteristics that identify flows that match this rule.
+	 */
+	struct net_device *match_dev;	/* Network device */
+	u8 match_protocol;		/* Protocol */
+	struct sfe_ipv6_addr match_src_ip[1];	/* Source IP address */
+	struct sfe_ipv6_addr match_dest_ip[1];	/* Destination IP address */
+	__be16 match_src_port;		/* Source port/connection ident */
+	__be16 match_dest_port;		/* Destination port/connection ident */
+
+	struct udp_sock *up;		/* Stores UDP sock information; valid only in decap path */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	const struct inet6_protocol *proto;	/* stores protocol handler; valid only in decap path */
+#else
+	struct inet6_protocol *proto;	/* stores protocol handler; valid only in decap path */
+#endif
+
+	/*
+	 * Control the operations of the match.
+	 */
+	u32 flags;			/* Bit flags */
+#ifdef CONFIG_NF_FLOW_COOKIE
+	u32 flow_cookie;		/* used flow cookie, for debug */
+#endif
+#ifdef CONFIG_XFRM
+	u32 flow_accel;            	/* The flow accelerated or not */
+#endif
+
+	/*
+	 * Connection state that we track once we match.
+	 */
+	union {				/* Protocol-specific state */
+		struct sfe_ipv6_tcp_connection_match tcp;
+	} protocol_state;
+
+	/*
+	 * VLAN headers
+	 */
+	struct sfe_vlan_hdr ingress_vlan_hdr[SFE_MAX_VLAN_DEPTH];
+	struct sfe_vlan_hdr egress_vlan_hdr[SFE_MAX_VLAN_DEPTH];
+
+	/*
+	 * Stats recorded in a sync period. These stats will be added to
+	 * rx_packet_count64/rx_byte_count64 after a sync period.
+	 */
+	atomic_t rx_packet_count;
+	atomic_t rx_byte_count;
+
+	/*
+	 * Packet translation information.
+	 */
+	struct sfe_ipv6_addr xlate_src_ip[1];	/* Address after source translation */
+	__be16 xlate_src_port;	/* Port/connection ident after source translation */
+	u16 xlate_src_csum_adjustment;
+					/* Transport layer checksum adjustment after source translation */
+	struct sfe_ipv6_addr xlate_dest_ip[1];	/* Address after destination translation */
+	__be16 xlate_dest_port;	/* Port/connection ident after destination translation */
+	u16 xlate_dest_csum_adjustment;
+					/* Transport layer checksum adjustment after destination translation */
+	u32 mark;			/* mark for outgoing packet */
+
+	/*
+	 * QoS information
+	 */
+	u32 priority;
+	u32 dscp;
+
+	/*
+	 * Packet transmit information.
+	 */
+	struct net_device *xmit_dev;	/* Network device on which to transmit */
+	unsigned short int xmit_dev_mtu;
+					/* Interface MTU */
+	u16 xmit_dest_mac[ETH_ALEN / 2];
+					/* Destination MAC address to use when forwarding */
+	u16 xmit_src_mac[ETH_ALEN / 2];
+					/* Source MAC address to use when forwarding */
+
+	u8 ingress_vlan_hdr_cnt;        /* Ingress active vlan headers count */
+	u8 egress_vlan_hdr_cnt;         /* Egress active vlan headers count */
+
+	/*
+	 * Summary stats.
+	 */
+	u64 rx_packet_count64;
+	u64 rx_byte_count64;
+
+	/*
+	 * PPPoE information.
+	 */
+	u16 pppoe_session_id;
+	u8 pppoe_remote_mac[ETH_ALEN];
+
+	struct net_device *top_interface_dev;	/* Used by tunipip6 to store decap VLAN netdevice.*/
+
+	/*
+	 * Size of all needed L2 headers
+	 */
+	u16 l2_hdr_size;
+
+	/*
+	* xmit device's feature
+	 */
+	netdev_features_t features;
+};
+
+/*
+ * Per-connection data structure.
+ */
+struct sfe_ipv6_connection {
+	struct sfe_ipv6_connection *next;
+					/* Pointer to the next entry in a hash chain */
+	struct sfe_ipv6_connection *prev;
+					/* Pointer to the previous entry in a hash chain */
+	int protocol;			/* IP protocol number */
+	struct sfe_ipv6_addr src_ip[1];		/* Src IP addr pre-translation */
+	struct sfe_ipv6_addr src_ip_xlate[1];	/* Src IP addr post-translation */
+	struct sfe_ipv6_addr dest_ip[1];	/* Dest IP addr pre-translation */
+	struct sfe_ipv6_addr dest_ip_xlate[1];	/* Dest IP addr post-translation */
+	__be16 src_port;		/* Src port pre-translation */
+	__be16 src_port_xlate;		/* Src port post-translation */
+	__be16 dest_port;		/* Dest port pre-translation */
+	__be16 dest_port_xlate;		/* Dest port post-translation */
+	struct sfe_ipv6_connection_match *original_match;
+					/* Original direction matching structure */
+	struct net_device *original_dev;
+					/* Original direction source device */
+	struct sfe_ipv6_connection_match *reply_match;
+					/* Reply direction matching structure */
+	struct net_device *reply_dev;	/* Reply direction source device */
+	u64 last_sync_jiffies;		/* Jiffies count for the last sync */
+	struct sfe_ipv6_connection *all_connections_next;
+					/* Pointer to the next entry in the list of all connections */
+	struct sfe_ipv6_connection *all_connections_prev;
+					/* Pointer to the previous entry in the list of all connections */
+	bool removed;			/* Indicates the connection is removed */
+	struct rcu_head rcu;		/* delay rcu free */
+	u32 debug_read_seq;		/* sequence number for debug dump */
+};
+
+/*
+ * IPv6 connections and hash table size information.
+ */
+#define SFE_IPV6_CONNECTION_HASH_SHIFT 12
+#define SFE_IPV6_CONNECTION_HASH_SIZE (1 << SFE_IPV6_CONNECTION_HASH_SHIFT)
+#define SFE_IPV6_CONNECTION_HASH_MASK (SFE_IPV6_CONNECTION_HASH_SIZE - 1)
+
+enum sfe_ipv6_exception_events {
+	SFE_IPV6_EXCEPTION_EVENT_UDP_HEADER_INCOMPLETE,
+	SFE_IPV6_EXCEPTION_EVENT_UDP_NO_CONNECTION,
+	SFE_IPV6_EXCEPTION_EVENT_UDP_IP_OPTIONS_OR_INITIAL_FRAGMENT,
+	SFE_IPV6_EXCEPTION_EVENT_UDP_SMALL_TTL,
+	SFE_IPV6_EXCEPTION_EVENT_UDP_NEEDS_FRAGMENTATION,
+	SFE_IPV6_EXCEPTION_EVENT_TCP_HEADER_INCOMPLETE,
+	SFE_IPV6_EXCEPTION_EVENT_TCP_NO_CONNECTION_SLOW_FLAGS,
+	SFE_IPV6_EXCEPTION_EVENT_TCP_NO_CONNECTION_FAST_FLAGS,
+	SFE_IPV6_EXCEPTION_EVENT_TCP_IP_OPTIONS_OR_INITIAL_FRAGMENT,
+	SFE_IPV6_EXCEPTION_EVENT_TCP_SMALL_TTL,
+	SFE_IPV6_EXCEPTION_EVENT_TCP_NEEDS_FRAGMENTATION,
+	SFE_IPV6_EXCEPTION_EVENT_TCP_FLAGS,
+	SFE_IPV6_EXCEPTION_EVENT_TCP_SEQ_EXCEEDS_RIGHT_EDGE,
+	SFE_IPV6_EXCEPTION_EVENT_TCP_SMALL_DATA_OFFS,
+	SFE_IPV6_EXCEPTION_EVENT_TCP_BAD_SACK,
+	SFE_IPV6_EXCEPTION_EVENT_TCP_BIG_DATA_OFFS,
+	SFE_IPV6_EXCEPTION_EVENT_TCP_SEQ_BEFORE_LEFT_EDGE,
+	SFE_IPV6_EXCEPTION_EVENT_TCP_ACK_EXCEEDS_RIGHT_EDGE,
+	SFE_IPV6_EXCEPTION_EVENT_TCP_ACK_BEFORE_LEFT_EDGE,
+	SFE_IPV6_EXCEPTION_EVENT_ICMP_HEADER_INCOMPLETE,
+	SFE_IPV6_EXCEPTION_EVENT_ICMP_UNHANDLED_TYPE,
+	SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_HEADER_INCOMPLETE,
+	SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_NON_V6,
+	SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_IP_OPTIONS_INCOMPLETE,
+	SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_UDP_HEADER_INCOMPLETE,
+	SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_TCP_HEADER_INCOMPLETE,
+	SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_UNHANDLED_PROTOCOL,
+	SFE_IPV6_EXCEPTION_EVENT_ICMP_NO_CONNECTION,
+	SFE_IPV6_EXCEPTION_EVENT_ICMP_FLUSHED_CONNECTION,
+	SFE_IPV6_EXCEPTION_EVENT_HEADER_INCOMPLETE,
+	SFE_IPV6_EXCEPTION_EVENT_BAD_TOTAL_LENGTH,
+	SFE_IPV6_EXCEPTION_EVENT_NON_V6,
+	SFE_IPV6_EXCEPTION_EVENT_NON_INITIAL_FRAGMENT,
+	SFE_IPV6_EXCEPTION_EVENT_DATAGRAM_INCOMPLETE,
+	SFE_IPV6_EXCEPTION_EVENT_IP_OPTIONS_INCOMPLETE,
+	SFE_IPV6_EXCEPTION_EVENT_UNHANDLED_PROTOCOL,
+	SFE_IPV6_EXCEPTION_EVENT_FLOW_COOKIE_ADD_FAIL,
+	SFE_IPV6_EXCEPTION_EVENT_NO_HEADROOM,
+	SFE_IPV6_EXCEPTION_EVENT_INVALID_PPPOE_SESSION,
+	SFE_IPV6_EXCEPTION_EVENT_INCORRECT_PPPOE_PARSING,
+	SFE_IPV6_EXCEPTION_EVENT_PPPOE_NOT_SET_IN_CME,
+	SFE_IPV6_EXCEPTION_EVENT_INGRESS_VLAN_TAG_MISMATCH,
+	SFE_IPV6_EXCEPTION_EVENT_INVALID_SRC_IFACE,
+	SFE_IPV6_EXCEPTION_EVENT_TUNIPIP6_HEADER_INCOMPLETE,
+	SFE_IPV6_EXCEPTION_EVENT_TUNIPIP6_NO_CONNECTION,
+	SFE_IPV6_EXCEPTION_EVENT_TUNIPIP6_IP_OPTIONS_OR_INITIAL_FRAGMENT,
+	SFE_IPV6_EXCEPTION_EVENT_TUNIPIP6_SMALL_TTL,
+	SFE_IPV6_EXCEPTION_EVENT_TUNIPIP6_NEEDS_FRAGMENTATION,
+	SFE_IPV6_EXCEPTION_EVENT_TUNIPIP6_SYNC_ON_FIND,
+	SFE_IPV6_EXCEPTION_EVENT_GRE_HEADER_INCOMPLETE,
+	SFE_IPV6_EXCEPTION_EVENT_GRE_NO_CONNECTION,
+	SFE_IPV6_EXCEPTION_EVENT_GRE_IP_OPTIONS_OR_INITIAL_FRAGMENT,
+	SFE_IPV6_EXCEPTION_EVENT_GRE_SMALL_TTL,
+	SFE_IPV6_EXCEPTION_EVENT_GRE_NEEDS_FRAGMENTATION,
+	SFE_IPV6_EXCEPTION_EVENT_LAST
+};
+
+/*
+ * Per CPU stats
+ */
+struct sfe_ipv6_stats {
+	/*
+	 * Stats recorded in a sync period. These stats will be added to
+	 * connection_xxx64 after a sync period.
+	 */
+	u64 connection_create_requests64;
+					/* Number of IPv6 connection create requests */
+	u64 connection_create_collisions64;
+					/* Number of IPv6 connection create requests that collided with existing hash table entries */
+	u64 connection_create_failures64;
+					/* Number of IPv6 connection create requests failures. */
+
+	u64 connection_destroy_requests64;
+					/* Number of IPv6 connection destroy requests */
+	u64 connection_destroy_misses64;
+					/* Number of IPv6 connection destroy requests that missed our hash table */
+	u64 connection_match_hash_hits64;
+					/* Number of IPv6 connection match hash hits */
+	u64 connection_match_hash_reorders64;
+					/* Number of IPv6 connection match hash reorders */
+	u64 connection_flushes64;		/* Number of IPv6 connection flushes */
+	u64 packets_dropped64;			/* Number of IPv4 packets dropped */
+	u64 packets_forwarded64;		/* Number of IPv6 packets forwarded */
+	u64 packets_fast_xmited64;           /* Number of IPv6 packets fast transmited */
+	u64 packets_not_forwarded64;	/* Number of IPv6 packets not forwarded */
+	u64 exception_events64[SFE_IPV6_EXCEPTION_EVENT_LAST];
+	u64 pppoe_encap_packets_forwarded64;	/* Number of IPv6 PPPoE encap packets forwarded */
+	u64 pppoe_decap_packets_forwarded64;	/* Number of IPv6 PPPoE decap packets forwarded */
+	u64 pppoe_bridge_packets_forwarded64;	/* Number of IPv6 PPPoE decap packets forwarded */
+};
+
+/*
+ * Per-module structure.
+ */
+struct sfe_ipv6 {
+	spinlock_t lock;		/* Lock for SMP correctness */
+	struct sfe_ipv6_connection *all_connections_head;
+					/* Head of the list of all connections */
+	struct sfe_ipv6_connection *all_connections_tail;
+					/* Tail of the list of all connections */
+	unsigned int num_connections;	/* Number of connections */
+	struct delayed_work sync_dwork;	/* Work to sync the statistics */
+	unsigned int work_cpu;		/* The core to run stats sync on */
+
+	sfe_sync_rule_callback_t __rcu sync_rule_callback;
+					/* Callback function registered by a connection manager for stats syncing */
+	struct sfe_ipv6_connection *conn_hash[SFE_IPV6_CONNECTION_HASH_SIZE];
+					/* Connection hash table */
+	struct hlist_head hlist_conn_match_hash_head[SFE_IPV6_CONNECTION_HASH_SIZE];
+#ifdef CONFIG_NF_FLOW_COOKIE
+	struct sfe_ipv6_flow_cookie_entry sfe_flow_cookie_table[SFE_FLOW_COOKIE_SIZE];
+					/* flow cookie table*/
+	sfe_ipv6_flow_cookie_set_func_t flow_cookie_set_func;
+					/* function used to configure flow cookie in hardware*/
+	int flow_cookie_enable;
+					/* Enable/disable flow cookie at runtime */
+#endif
+
+	struct sfe_ipv6_stats __percpu *stats_pcpu;
+					/* Common SFE counters. */
+
+	struct sfe_ipv6_connection *wc_next;
+					/* The next walk point in the all connection list*/
+
+	/*
+	 * Control state.
+	 */
+	struct kobject *sys_ipv6;	/* sysfs linkage */
+	int debug_dev;			/* Major number of the debug char device */
+	u32 debug_read_seq;		/* sequence number for debug dump */
+
+	/*
+	 * DSCP rewrite table
+	 * When `mark_to_match` is set non-zero then any packet with the
+	 * specified skb->mark will override flow DSCP policy with
+	 * `dscp_to_set` value. i.e. basically equivalent to `ip6tables -m mark
+	 * --mark <mark_to_match> -j DSCP --set-dscp <dscp_to_set>`
+	 */
+	u32 dscp_rewrite_mark_to_match;
+	u32 dscp_rewrite_dscp_to_set;
+};
+
+/*
+ * Enumeration of the XML output.
+ */
+enum sfe_ipv6_debug_xml_states {
+	SFE_IPV6_DEBUG_XML_STATE_START,
+	SFE_IPV6_DEBUG_XML_STATE_CONNECTIONS_START,
+	SFE_IPV6_DEBUG_XML_STATE_CONNECTIONS_CONNECTION,
+	SFE_IPV6_DEBUG_XML_STATE_CONNECTIONS_END,
+	SFE_IPV6_DEBUG_XML_STATE_EXCEPTIONS_START,
+	SFE_IPV6_DEBUG_XML_STATE_EXCEPTIONS_EXCEPTION,
+	SFE_IPV6_DEBUG_XML_STATE_EXCEPTIONS_END,
+	SFE_IPV6_DEBUG_XML_STATE_STATS,
+	SFE_IPV6_DEBUG_XML_STATE_END,
+	SFE_IPV6_DEBUG_XML_STATE_DONE
+};
+
+/*
+ * XML write state.
+ */
+struct sfe_ipv6_debug_xml_write_state {
+	enum sfe_ipv6_debug_xml_states state;
+					/* XML output file state machine state */
+	int iter_exception;		/* Next exception iterator */
+};
+
+typedef bool (*sfe_ipv6_debug_xml_write_method_t)(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length,
+						  int *total_read, struct sfe_ipv6_debug_xml_write_state *ws);
+
+/*
+ * sfe_ipv6_is_ext_hdr()
+ *	check if we recognize ipv6 extension header
+ */
+static inline bool sfe_ipv6_is_ext_hdr(u8 hdr)
+{
+	return (hdr == NEXTHDR_HOP) ||
+		(hdr == NEXTHDR_ROUTING) ||
+		(hdr == NEXTHDR_FRAGMENT) ||
+		(hdr == NEXTHDR_AUTH) ||
+		(hdr == NEXTHDR_DEST) ||
+		(hdr == NEXTHDR_MOBILITY);
+}
+
+/*
+ * sfe_ipv6_change_dsfield()
+ *	change dscp field in IPv6 packet
+ */
+static inline void sfe_ipv6_change_dsfield(struct ipv6hdr *iph, u8 dscp)
+{
+	__be16 *p = (__be16 *)iph;
+
+	*p = ((*p & htons(SFE_IPV6_DSCP_MASK)) | htons((u16)dscp << 4));
+}
+
+void sfe_ipv6_exception_stats_inc(struct sfe_ipv6 *si, enum sfe_ipv6_exception_events reason);
+
+struct sfe_ipv6_connection_match *
+sfe_ipv6_find_connection_match_rcu(struct sfe_ipv6 *si, struct net_device *dev, u8 protocol,
+					struct sfe_ipv6_addr *src_ip, __be16 src_port,
+					struct sfe_ipv6_addr *dest_ip, __be16 dest_port);
+
+bool sfe_ipv6_remove_connection(struct sfe_ipv6 *si, struct sfe_ipv6_connection *c);
+
+void sfe_ipv6_flush_connection(struct sfe_ipv6 *si,
+				      struct sfe_ipv6_connection *c,
+				      sfe_sync_reason_t reason);
+
+void sfe_ipv6_sync_status(struct sfe_ipv6 *si,
+				      struct sfe_ipv6_connection *c,
+				      sfe_sync_reason_t reason);
+
+void sfe_ipv6_exit(void);
+int sfe_ipv6_init(void);
+
+#endif /* __SFE_IPV6_H */
diff --git a/qca-nss-sfe/sfe_ipv6_gre.c b/qca-nss-sfe/sfe_ipv6_gre.c
new file mode 100644
index 0000000..8a48b3f
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv6_gre.c
@@ -0,0 +1,301 @@
+/*
+ * sfe_ipv6_gre.c
+ *	Shortcut forwarding engine file for IPv6 GRE
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/skbuff.h>
+#include <net/gre.h>
+#include <net/protocol.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#include <net/ip6_checksum.h>
+
+#include "sfe_debug.h"
+#include "sfe_api.h"
+#include "sfe.h"
+#include "sfe_flow_cookie.h"
+#include "sfe_ipv6.h"
+#include "sfe_vlan.h"
+
+/*
+ * sfe_ipv6_recv_gre()
+ *	Handle GRE packet receives and forwarding.
+ */
+int sfe_ipv6_recv_gre(struct sfe_ipv6 *si, struct sk_buff *skb, struct net_device *dev,
+		      unsigned int len, struct ipv6hdr *iph, unsigned int ihl, bool sync_on_find,
+		      struct sfe_l2_info *l2_info, bool tun_outer)
+{
+	struct sfe_ipv6_connection_match *cm;
+	struct sfe_ipv6_addr *dest_ip;
+	struct sfe_ipv6_addr *src_ip;
+	struct net_device *xmit_dev;
+	bool bridge_flow;
+	bool passthrough;
+	bool ret;
+
+	/*
+	 * Is our packet too short to contain a valid UDP header?
+	 */
+	if (!pskb_may_pull(skb, (sizeof(struct gre_base_hdr) + ihl))) {
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_GRE_HEADER_INCOMPLETE);
+		DEBUG_TRACE("packet too short for GRE header\n");
+		return 0;
+	}
+
+	/*
+	 * Read the IP address and port information.  Read the IP header data first
+	 * because we've almost certainly got that in the cache.  We may not yet have
+	 * the UDP header cached though so allow more time for any prefetching.
+	 */
+	src_ip = (struct sfe_ipv6_addr *)iph->saddr.s6_addr32;
+	dest_ip = (struct sfe_ipv6_addr *)iph->daddr.s6_addr32;
+
+	rcu_read_lock();
+
+	/*
+	 * Look for a connection match.
+	 */
+#ifdef CONFIG_NF_FLOW_COOKIE
+	cm = si->sfe_flow_cookie_table[skb->flow_cookie & SFE_FLOW_COOKIE_MASK].match;
+	if (unlikely(!cm)) {
+		cm = sfe_ipv6_find_connection_match_rcu(si, dev, IPPROTO_GRE, src_ip, 0, dest_ip, 0);
+	}
+#else
+	cm = sfe_ipv6_find_connection_match_rcu(si, dev, IPPROTO_GRE, src_ip, 0, dest_ip, 0);
+#endif
+	if (unlikely(!cm)) {
+		rcu_read_unlock();
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_GRE_NO_CONNECTION);
+		DEBUG_TRACE("no connection match found dev %s src ip %pI6 dest ip %pI6\n", dev->name, src_ip, dest_ip);
+		return 0;
+	}
+
+	/*
+	 * Do we expect an ingress VLAN tag for this flow?
+	 */
+	if (unlikely(!sfe_vlan_validate_ingress_tag(skb, cm->ingress_vlan_hdr_cnt, cm->ingress_vlan_hdr, l2_info))) {
+		rcu_read_unlock();
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_INGRESS_VLAN_TAG_MISMATCH);
+		DEBUG_TRACE("VLAN tag mismatch. skb=%px\n", skb);
+		return 0;
+	}
+
+	/*
+	 * Source interface validate.
+	 */
+	if (unlikely((cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK) && (cm->match_dev != dev))) {
+		if (!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK_NO_FLUSH)) {
+			struct sfe_ipv6_connection *c = cm->connection;
+			int ret;
+			DEBUG_TRACE("flush on source interface check failure\n");
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv6_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			if (ret) {
+				sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+		}
+		rcu_read_unlock();
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_INVALID_SRC_IFACE);
+		DEBUG_TRACE("exception the packet on source interface check failure\n");
+		return 0;
+	}
+
+	passthrough = cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_PASSTHROUGH;
+
+	/*
+	 * If our packet has beern marked as "sync on find" we can't actually
+	 * forward it in the fast path, but now that we've found an associated
+	 * connection we need sync its status before exception it to slow path. unless
+	 * it is passthrough packet.
+	 * TODO: revisit to ensure that pass through traffic is not bypassing firewall for fragmented cases
+	 */
+	if (unlikely(sync_on_find) && !passthrough) {
+		sfe_ipv6_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_GRE_IP_OPTIONS_OR_INITIAL_FRAGMENT);
+		DEBUG_TRACE("Sync on find\n");
+		return 0;
+	}
+
+	bridge_flow = !!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_BRIDGE_FLOW);
+
+	/*
+	 * Does our hop_limit allow forwarding?
+	 */
+	if (!bridge_flow && (iph->hop_limit < 2) && passthrough) {
+		sfe_ipv6_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_GRE_SMALL_TTL);
+		DEBUG_TRACE("hop_limit too low\n");
+		return 0;
+	}
+
+	/*
+	 * From this point on we're good to modify the packet.
+	 */
+
+	/*
+	 * Check if skb was cloned. If it was, unshare it. Because
+	 * the data area is going to be written in this path and we don't want to
+	 * change the cloned skb's data section.
+	 */
+	if (unlikely(skb_cloned(skb))) {
+		DEBUG_TRACE("%px: skb is a cloned skb\n", skb);
+		skb = skb_unshare(skb, GFP_ATOMIC);
+		if (!skb) {
+			DEBUG_WARN("Failed to unshare the cloned skb\n");
+			rcu_read_unlock();
+			return 1;
+		}
+
+		/*
+		 * Update the iph and udph pointers with the unshared skb's data area.
+		 */
+		iph = (struct ipv6hdr *)skb->data;
+	}
+
+	/*
+	 * Check if skb has enough headroom to write L2 headers
+	 */
+	if (unlikely(skb_headroom(skb) < cm->l2_hdr_size)) {
+		rcu_read_unlock();
+		DEBUG_WARN("%px: Not enough headroom: %u\n", skb, skb_headroom(skb));
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_NO_HEADROOM);
+		return 0;
+	}
+
+	/*
+	 * protocol handler will be valid only in decap-path.
+	 */
+	if (cm->proto) {
+		struct inet6_protocol *ipprot = cm->proto;
+		skb_reset_network_header(skb);
+		skb_pull(skb, ihl);
+		skb_reset_transport_header(skb);
+		skb->fast_forwarded = 1;
+
+		ret = ipprot->handler(skb);
+		if (ret) {
+			this_cpu_inc(si->stats_pcpu->packets_not_forwarded64);
+			rcu_read_unlock();
+			return 1;
+		}
+
+		/*
+		 * Update traffic stats.
+		 */
+		atomic_inc(&cm->rx_packet_count);
+		atomic_add(len, &cm->rx_byte_count);
+
+		this_cpu_inc(si->stats_pcpu->packets_forwarded64);
+		rcu_read_unlock();
+		DEBUG_TRACE("%p: %s decap done\n",skb, __func__);
+		return 1;
+	}
+
+	/*
+	 * If our packet is larger than the MTU of the transmit interface then
+	 * we can't forward it easily.
+	 */
+	if (unlikely(len > cm->xmit_dev_mtu)) {
+		sfe_ipv6_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_GRE_NEEDS_FRAGMENTATION);
+		DEBUG_TRACE("Larger than MTU\n");
+		return 0;
+	}
+
+	/*
+	 * Update DSCP
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_DSCP_REMARK)) {
+		sfe_ipv6_change_dsfield(iph, cm->dscp);
+	}
+
+	iph->hop_limit -= (u8)(!bridge_flow & !tun_outer);
+
+	/*
+	 * Update traffic stats.
+	 */
+	atomic_inc(&cm->rx_packet_count);
+	atomic_add(len, &cm->rx_byte_count);
+
+	xmit_dev = cm->xmit_dev;
+	skb->dev = xmit_dev;
+
+	/*
+	 * Check to see if we need to add VLAN tags
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_INSERT_EGRESS_VLAN_TAG)) {
+		sfe_vlan_add_tag(skb, cm->egress_vlan_hdr_cnt, cm->egress_vlan_hdr);
+	}
+
+	if (cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR) {
+		/*
+		 * For the simple case we write this really fast.
+		 */
+		struct ethhdr *eth = (struct ethhdr *)__skb_push(skb, ETH_HLEN);
+		eth->h_proto = htons(ETH_P_IPV6);
+		ether_addr_copy((u8 *)eth->h_dest, (u8 *)cm->xmit_dest_mac);
+		ether_addr_copy((u8 *)eth->h_source, (u8 *)cm->xmit_src_mac);
+	} else if (cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_L2_HDR) {
+		dev_hard_header(skb, xmit_dev, ETH_P_IPV6,
+				cm->xmit_dest_mac, cm->xmit_src_mac, len);
+	}
+
+	/*
+	 * Update priority of skb.
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_PRIORITY_REMARK)) {
+		skb->priority = cm->priority;
+	}
+
+	/*
+	 * Mark outgoing packet.
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_MARK)) {
+		skb->mark = cm->mark;
+	}
+
+	rcu_read_unlock();
+
+	this_cpu_inc(si->stats_pcpu->packets_forwarded64);
+
+	/*
+	 * We're going to check for GSO flags when we transmit the packet so
+	 * start fetching the necessary cache line now.
+	 */
+	prefetch(skb_shinfo(skb));
+
+	/*
+	 * Mark that this packet has been fast forwarded.
+	 */
+	skb->fast_forwarded = 1;
+
+	/*
+	 * Send the packet on its way.
+	 */
+	dev_queue_xmit(skb);
+
+	return 1;
+}
diff --git a/qca-nss-sfe/sfe_ipv6_gre.h b/qca-nss-sfe/sfe_ipv6_gre.h
new file mode 100644
index 0000000..dce2176
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv6_gre.h
@@ -0,0 +1,22 @@
+/*
+ * sfe_ipv6_gre.h
+ *	Shortcut forwarding engine header file for IPv6 GRE
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+int sfe_ipv6_recv_gre(struct sfe_ipv6 *si, struct sk_buff *skb, struct net_device *dev,
+		      unsigned int len, struct ipv6hdr *iph, unsigned int ihl, bool sync_on_find,
+		      struct sfe_l2_info *l2_info, bool tun_outer);
diff --git a/qca-nss-sfe/sfe_ipv6_icmp.c b/qca-nss-sfe/sfe_ipv6_icmp.c
new file mode 100644
index 0000000..06e47bb
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv6_icmp.c
@@ -0,0 +1,207 @@
+/*
+ * sfe_ipv6_icmp.c
+ *	Shortcut forwarding engine file for IPv6 ICMP
+ *
+ * Copyright (c) 2015-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/skbuff.h>
+#include <linux/ip.h>
+#include <net/udp.h>
+#include <net/tcp.h>
+#include <net/icmp.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+
+#include "sfe_debug.h"
+#include "sfe_api.h"
+#include "sfe.h"
+#include "sfe_flow_cookie.h"
+#include "sfe_ipv6.h"
+
+/*
+ * sfe_ipv6_recv_icmp()
+ *	Handle ICMP packet receives.
+ *
+ * ICMP packets aren't handled as a "fast path" and always have us process them
+ * through the default Linux stack.  What we do need to do is look for any errors
+ * about connections we are handling in the fast path.  If we find any such
+ * connections then we want to flush their state so that the ICMP error path
+ * within Linux has all of the correct state should it need it.
+ */
+int sfe_ipv6_recv_icmp(struct sfe_ipv6 *si, struct sk_buff *skb, struct net_device *dev,
+			      unsigned int len, struct ipv6hdr *iph, unsigned int ihl)
+{
+	struct icmp6hdr *icmph;
+	struct ipv6hdr *icmp_iph;
+	struct udphdr *icmp_udph;
+	struct tcphdr *icmp_tcph;
+	struct sfe_ipv6_addr *src_ip;
+	struct sfe_ipv6_addr *dest_ip;
+	__be16 src_port;
+	__be16 dest_port;
+	struct sfe_ipv6_connection_match *cm;
+	struct sfe_ipv6_connection *c;
+	u8 next_hdr;
+	bool ret;
+
+	/*
+	 * Is our packet too short to contain a valid ICMP header?
+	 */
+	len -= ihl;
+	if (!pskb_may_pull(skb, ihl + sizeof(struct icmp6hdr))) {
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_ICMP_HEADER_INCOMPLETE);
+
+		DEBUG_TRACE("packet too short for ICMP header\n");
+		return 0;
+	}
+
+	/*
+	 * We only handle "destination unreachable" and "time exceeded" messages.
+	 */
+	icmph = (struct icmp6hdr *)(skb->data + ihl);
+	if ((icmph->icmp6_type != ICMPV6_DEST_UNREACH)
+	    && (icmph->icmp6_type != ICMPV6_TIME_EXCEED)) {
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_ICMP_UNHANDLED_TYPE);
+		DEBUG_TRACE("unhandled ICMP type: 0x%x\n", icmph->icmp6_type);
+		return 0;
+	}
+
+	/*
+	 * Do we have the full embedded IP header?
+	 * We should have 8 bytes of next L4 header - that's enough to identify
+	 * the connection.
+	 */
+	len -= sizeof(struct icmp6hdr);
+	ihl += sizeof(struct icmp6hdr);
+	if (!pskb_may_pull(skb, ihl + sizeof(struct ipv6hdr) + sizeof(struct sfe_ipv6_ext_hdr))) {
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_HEADER_INCOMPLETE);
+		DEBUG_TRACE("Embedded IP header not complete\n");
+		return 0;
+	}
+
+	/*
+	 * Is our embedded IP version wrong?
+	 */
+	icmp_iph = (struct ipv6hdr *)(icmph + 1);
+	if (unlikely(icmp_iph->version != 6)) {
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_NON_V6);
+		DEBUG_TRACE("IP version: %u\n", icmp_iph->version);
+		return 0;
+	}
+
+	len -= sizeof(struct ipv6hdr);
+	ihl += sizeof(struct ipv6hdr);
+	next_hdr = icmp_iph->nexthdr;
+	while (unlikely(sfe_ipv6_is_ext_hdr(next_hdr))) {
+		struct sfe_ipv6_ext_hdr *ext_hdr;
+		unsigned int ext_hdr_len;
+
+		ext_hdr = (struct sfe_ipv6_ext_hdr *)(skb->data + ihl);
+		if (next_hdr == NEXTHDR_FRAGMENT) {
+			struct frag_hdr *frag_hdr = (struct frag_hdr *)ext_hdr;
+			unsigned int frag_off = ntohs(frag_hdr->frag_off);
+
+			if (frag_off & SFE_IPV6_FRAG_OFFSET) {
+
+				DEBUG_TRACE("non-initial fragment\n");
+				sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_NON_INITIAL_FRAGMENT);
+				return 0;
+			}
+		}
+
+		ext_hdr_len = ext_hdr->hdr_len;
+		ext_hdr_len <<= 3;
+		ext_hdr_len += sizeof(struct sfe_ipv6_ext_hdr);
+		len -= ext_hdr_len;
+		ihl += ext_hdr_len;
+		/*
+		 * We should have 8 bytes of next header - that's enough to identify
+		 * the connection.
+		 */
+		if (!pskb_may_pull(skb, ihl + sizeof(struct sfe_ipv6_ext_hdr))) {
+
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_HEADER_INCOMPLETE);
+			DEBUG_TRACE("extension header %d not completed\n", next_hdr);
+			return 0;
+		}
+
+		next_hdr = ext_hdr->next_hdr;
+	}
+
+	/*
+	 * Handle the embedded transport layer header.
+	 */
+	switch (next_hdr) {
+	case IPPROTO_UDP:
+		icmp_udph = (struct udphdr *)(skb->data + ihl);
+		src_port = icmp_udph->source;
+		dest_port = icmp_udph->dest;
+		break;
+
+	case IPPROTO_TCP:
+		icmp_tcph = (struct tcphdr *)(skb->data + ihl);
+		src_port = icmp_tcph->source;
+		dest_port = icmp_tcph->dest;
+		break;
+
+	default:
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_UNHANDLED_PROTOCOL);
+		DEBUG_TRACE("Unhandled embedded IP protocol: %u\n", next_hdr);
+		return 0;
+	}
+
+	src_ip = (struct sfe_ipv6_addr *)icmp_iph->saddr.s6_addr32;
+	dest_ip = (struct sfe_ipv6_addr *)icmp_iph->daddr.s6_addr32;
+
+	rcu_read_lock();
+	/*
+	 * Look for a connection match.  Note that we reverse the source and destination
+	 * here because our embedded message contains a packet that was sent in the
+	 * opposite direction to the one in which we just received it.  It will have
+	 * been sent on the interface from which we received it though so that's still
+	 * ok to use.
+	 */
+	cm = sfe_ipv6_find_connection_match_rcu(si, dev, icmp_iph->nexthdr, dest_ip, dest_port, src_ip, src_port);
+	if (unlikely(!cm)) {
+		rcu_read_unlock();
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_ICMP_NO_CONNECTION);
+		DEBUG_TRACE("no connection found\n");
+		return 0;
+	}
+
+	/*
+	 * We found a connection so now remove it from the connection list and flush
+	 * its state.
+	 */
+	c = cm->connection;
+	spin_lock_bh(&si->lock);
+	ret = sfe_ipv6_remove_connection(si, c);
+	spin_unlock_bh(&si->lock);
+
+	if (ret) {
+		sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+	}
+
+	rcu_read_unlock();
+
+	sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_ICMP_FLUSHED_CONNECTION);
+	return 0;
+}
diff --git a/qca-nss-sfe/sfe_ipv6_icmp.h b/qca-nss-sfe/sfe_ipv6_icmp.h
new file mode 100644
index 0000000..b715576
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv6_icmp.h
@@ -0,0 +1,22 @@
+/*
+ * sfe_ipv6_icmp.h
+ *	Shortcut forwarding engine header file for IPv6 ICMP
+ *
+ * Copyright (c) 2015-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+int sfe_ipv6_recv_icmp(struct sfe_ipv6 *si, struct sk_buff *skb, struct net_device *dev,
+			      unsigned int len, struct ipv6hdr *iph, unsigned int ihl);
diff --git a/qca-nss-sfe/sfe_ipv6_tcp.c b/qca-nss-sfe/sfe_ipv6_tcp.c
new file mode 100644
index 0000000..6ba30b3
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv6_tcp.c
@@ -0,0 +1,757 @@
+/*
+ * sfe_ipv6_tcp.c
+ *	Shortcut forwarding engine file for IPv6 TCP
+ *
+ * Copyright (c) 2015-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/skbuff.h>
+#include <net/tcp.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+
+#include "sfe_debug.h"
+#include "sfe_api.h"
+#include "sfe.h"
+#include "sfe_flow_cookie.h"
+#include "sfe_ipv6.h"
+#include "sfe_pppoe.h"
+#include "sfe_vlan.h"
+
+/*
+ * sfe_ipv6_process_tcp_option_sack()
+ *	Parse TCP SACK option and update ack according
+ */
+static bool sfe_ipv6_process_tcp_option_sack(const struct tcphdr *th, const u32 data_offs,
+					     u32 *ack)
+{
+	u32 length = sizeof(struct tcphdr);
+	u8 *ptr = (u8 *)th + length;
+
+	/*
+	 * Ignore processing if TCP packet has only TIMESTAMP option.
+	 */
+	if (likely(data_offs == length + TCPOLEN_TIMESTAMP + 1 + 1)
+	    && likely(ptr[0] == TCPOPT_NOP)
+	    && likely(ptr[1] == TCPOPT_NOP)
+	    && likely(ptr[2] == TCPOPT_TIMESTAMP)
+	    && likely(ptr[3] == TCPOLEN_TIMESTAMP)) {
+		return true;
+	}
+
+	/*
+	 * TCP options. Parse SACK option.
+	 */
+	while (length < data_offs) {
+		u8 size;
+		u8 kind;
+
+		ptr = (u8 *)th + length;
+		kind = *ptr;
+
+		/*
+		 * NOP, for padding
+		 * Not in the switch because to fast escape and to not calculate size
+		 */
+		if (kind == TCPOPT_NOP) {
+			length++;
+			continue;
+		}
+
+		if (kind == TCPOPT_SACK) {
+			u32 sack = 0;
+			u8 re = 1 + 1;
+
+			size = *(ptr + 1);
+			if ((size < (1 + 1 + TCPOLEN_SACK_PERBLOCK))
+			    || ((size - (1 + 1)) % (TCPOLEN_SACK_PERBLOCK))
+			    || (size > (data_offs - length))) {
+				return false;
+			}
+
+			re += 4;
+			while (re < size) {
+				u32 sack_re;
+				u8 *sptr = ptr + re;
+				sack_re = (sptr[0] << 24) | (sptr[1] << 16) | (sptr[2] << 8) | sptr[3];
+				if (sack_re > sack) {
+					sack = sack_re;
+				}
+				re += TCPOLEN_SACK_PERBLOCK;
+			}
+			if (sack > *ack) {
+				*ack = sack;
+			}
+			length += size;
+			continue;
+		}
+		if (kind == TCPOPT_EOL) {
+			return true;
+		}
+		size = *(ptr + 1);
+		if (size < 2) {
+			return false;
+		}
+		length += size;
+	}
+
+	return true;
+}
+
+/*
+ * sfe_ipv6_recv_tcp()
+ *	Handle TCP packet receives and forwarding.
+ */
+int sfe_ipv6_recv_tcp(struct sfe_ipv6 *si, struct sk_buff *skb, struct net_device *dev,
+			     unsigned int len, struct ipv6hdr *iph, unsigned int ihl, bool sync_on_find, struct sfe_l2_info *l2_info)
+{
+	struct tcphdr *tcph;
+	struct sfe_ipv6_addr *src_ip;
+	struct sfe_ipv6_addr *dest_ip;
+	__be16 src_port;
+	__be16 dest_port;
+	struct sfe_ipv6_connection_match *cm;
+	struct sfe_ipv6_connection_match *counter_cm;
+	u32 flags;
+	struct net_device *xmit_dev;
+	bool ret;
+	bool hw_csum;
+	bool bridge_flow;
+	bool fast_xmit;
+	netdev_features_t features;
+
+	/*
+	 * Is our packet too short to contain a valid TCP header?
+	 */
+	if (!pskb_may_pull(skb, (sizeof(struct tcphdr) + ihl))) {
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TCP_HEADER_INCOMPLETE);
+		DEBUG_TRACE("packet too short for TCP header\n");
+		return 0;
+	}
+
+	/*
+	 * Read the IP address and port information.  Read the IP header data first
+	 * because we've almost certainly got that in the cache.  We may not yet have
+	 * the TCP header cached though so allow more time for any prefetching.
+	 */
+	src_ip = (struct sfe_ipv6_addr *)iph->saddr.s6_addr32;
+	dest_ip = (struct sfe_ipv6_addr *)iph->daddr.s6_addr32;
+
+	tcph = (struct tcphdr *)(skb->data + ihl);
+	src_port = tcph->source;
+	dest_port = tcph->dest;
+	flags = tcp_flag_word(tcph);
+
+	rcu_read_lock();
+
+	/*
+	 * Look for a connection match.
+	 */
+#ifdef CONFIG_NF_FLOW_COOKIE
+	cm = si->sfe_flow_cookie_table[skb->flow_cookie & SFE_FLOW_COOKIE_MASK].match;
+	if (unlikely(!cm)) {
+		cm = sfe_ipv6_find_connection_match_rcu(si, dev, IPPROTO_TCP, src_ip, src_port, dest_ip, dest_port);
+	}
+#else
+	cm = sfe_ipv6_find_connection_match_rcu(si, dev, IPPROTO_TCP, src_ip, src_port, dest_ip, dest_port);
+#endif
+	if (unlikely(!cm)) {
+		/*
+		 * We didn't get a connection but as TCP is connection-oriented that
+		 * may be because this is a non-fast connection (not running established).
+		 * For diagnostic purposes we differentiate this here.
+		 */
+		if (likely((flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK)) == TCP_FLAG_ACK)) {
+			rcu_read_unlock();
+
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TCP_NO_CONNECTION_FAST_FLAGS);
+
+			DEBUG_TRACE("no connection found - fast flags\n");
+			return 0;
+		}
+
+		rcu_read_unlock();
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TCP_NO_CONNECTION_SLOW_FLAGS);
+		DEBUG_TRACE("no connection found - slow flags: 0x%x\n",
+			    flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK));
+		return 0;
+	}
+
+	/*
+	 * Source interface validate.
+	 */
+	if (unlikely((cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK) && (cm->match_dev != dev))) {
+		if (!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK_NO_FLUSH)) {
+			struct sfe_ipv6_connection *c = cm->connection;
+			DEBUG_TRACE("flush on source interface check failure\n");
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv6_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			if (ret) {
+				sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+		}
+		rcu_read_unlock();
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_INVALID_SRC_IFACE);
+		DEBUG_TRACE("exception the packet on source interface check failure\n");
+		return 0;
+	}
+
+	/*
+	 * If our packet has beern marked as "flush on find" we can't actually
+	 * forward it in the fast path, but now that we've found an associated
+	 * connection we need sync its status before throw it slow path.
+	 */
+	if (unlikely(sync_on_find)) {
+		sfe_ipv6_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TCP_IP_OPTIONS_OR_INITIAL_FRAGMENT);
+		DEBUG_TRACE("Sync on find\n");
+		return 0;
+	}
+
+#ifdef CONFIG_XFRM
+	/*
+	 * We can't accelerate the flow on this direction, just let it go
+	 * through the slow path.
+	 */
+	if (unlikely(!cm->flow_accel)) {
+		rcu_read_unlock();
+		this_cpu_inc(si->stats_pcpu->packets_not_forwarded64);
+		return 0;
+	}
+#endif
+
+	/*
+	 * Do we expect an ingress VLAN tag for this flow?
+	 */
+	if (unlikely(!sfe_vlan_validate_ingress_tag(skb, cm->ingress_vlan_hdr_cnt, cm->ingress_vlan_hdr, l2_info))) {
+		rcu_read_unlock();
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_INGRESS_VLAN_TAG_MISMATCH);
+		DEBUG_TRACE("VLAN tag mismatch. skb=%px\n", skb);
+		return 0;
+	}
+
+	bridge_flow = !!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_BRIDGE_FLOW);
+
+	/*
+	 * Does our hop_limit allow forwarding?
+	 */
+	if (likely(!bridge_flow)) {
+		if (unlikely(iph->hop_limit < 2)) {
+			sfe_ipv6_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+			rcu_read_unlock();
+
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TCP_SMALL_TTL);
+			DEBUG_TRACE("hop_limit too low\n");
+			return 0;
+		}
+	}
+
+	/*
+	 * If our packet is larger than the MTU of the transmit interface then
+	 * we can't forward it easily.
+	 */
+	if (unlikely((len > cm->xmit_dev_mtu) && !skb_is_gso(skb))) {
+		sfe_ipv6_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TCP_NEEDS_FRAGMENTATION);
+		DEBUG_TRACE("Larger than MTU\n");
+		return 0;
+	}
+
+	/*
+	 * Look at our TCP flags.  Anything missing an ACK or that has RST, SYN or FIN
+	 * set is not a fast path packet.
+	 */
+	if (unlikely((flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK)) != TCP_FLAG_ACK)) {
+		struct sfe_ipv6_connection *c = cm->connection;
+		spin_lock_bh(&si->lock);
+		ret = sfe_ipv6_remove_connection(si, c);
+		spin_unlock_bh(&si->lock);
+
+		DEBUG_TRACE("TCP flags: 0x%x are not fast\n",
+			    flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK));
+		if (ret) {
+			sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+		}
+		rcu_read_unlock();
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TCP_FLAGS);
+		return 0;
+	}
+
+	counter_cm = cm->counter_match;
+
+	/*
+	 * Are we doing sequence number checking?
+	 */
+	if (likely(!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK))) {
+		u32 seq;
+		u32 ack;
+		u32 sack;
+		u32 data_offs;
+		u32 end;
+		u32 left_edge;
+		u32 scaled_win;
+		u32 max_end;
+
+		/*
+		 * Is our sequence fully past the right hand edge of the window?
+		 */
+		seq = ntohl(tcph->seq);
+		if (unlikely((s32)(seq - (cm->protocol_state.tcp.max_end + 1)) > 0)) {
+			struct sfe_ipv6_connection *c = cm->connection;
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv6_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			DEBUG_TRACE("seq: %u exceeds right edge: %u\n",
+				    seq, cm->protocol_state.tcp.max_end + 1);
+			if (ret) {
+				sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+			rcu_read_unlock();
+
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TCP_SEQ_EXCEEDS_RIGHT_EDGE);
+			return 0;
+		}
+
+		/*
+		 * Check that our TCP data offset isn't too short.
+		 */
+		data_offs = tcph->doff << 2;
+		if (unlikely(data_offs < sizeof(struct tcphdr))) {
+			struct sfe_ipv6_connection *c = cm->connection;
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv6_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			DEBUG_TRACE("TCP data offset: %u, too small\n", data_offs);
+			if (ret) {
+				sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+			rcu_read_unlock();
+
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TCP_SMALL_DATA_OFFS);
+			return 0;
+		}
+
+		/*
+		 * Update ACK according to any SACK option.
+		 */
+		ack = ntohl(tcph->ack_seq);
+		sack = ack;
+		if (unlikely(!sfe_ipv6_process_tcp_option_sack(tcph, data_offs, &sack))) {
+			struct sfe_ipv6_connection *c = cm->connection;
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv6_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			DEBUG_TRACE("TCP option SACK size is wrong\n");
+			if (ret) {
+				sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+			rcu_read_unlock();
+
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TCP_BAD_SACK);
+			return 0;
+		}
+
+		/*
+		 * Check that our TCP data offset isn't past the end of the packet.
+		 */
+		data_offs += sizeof(struct ipv6hdr);
+		if (unlikely(len < data_offs)) {
+			struct sfe_ipv6_connection *c = cm->connection;
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv6_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			DEBUG_TRACE("TCP data offset: %u, past end of packet: %u\n",
+				    data_offs, len);
+			if (ret) {
+				sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+			rcu_read_unlock();
+
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TCP_BIG_DATA_OFFS);
+			return 0;
+		}
+
+		end = seq + len - data_offs;
+
+		/*
+		 * Is our sequence fully before the left hand edge of the window?
+		 */
+		if (unlikely((s32)(end - (cm->protocol_state.tcp.end
+						- counter_cm->protocol_state.tcp.max_win - 1)) < 0)) {
+			struct sfe_ipv6_connection *c = cm->connection;
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv6_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			DEBUG_TRACE("seq: %u before left edge: %u\n",
+				    end, cm->protocol_state.tcp.end - counter_cm->protocol_state.tcp.max_win - 1);
+			if (ret) {
+				sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+			rcu_read_unlock();
+
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TCP_SEQ_BEFORE_LEFT_EDGE);
+			return 0;
+		}
+
+		/*
+		 * Are we acking data that is to the right of what has been sent?
+		 */
+		if (unlikely((s32)(sack - (counter_cm->protocol_state.tcp.end + 1)) > 0)) {
+			struct sfe_ipv6_connection *c = cm->connection;
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv6_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			DEBUG_TRACE("ack: %u exceeds right edge: %u\n",
+				    sack, counter_cm->protocol_state.tcp.end + 1);
+			if (ret) {
+				sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+			rcu_read_unlock();
+
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TCP_ACK_EXCEEDS_RIGHT_EDGE);
+			return 0;
+		}
+
+		/*
+		 * Is our ack too far before the left hand edge of the window?
+		 */
+		left_edge = counter_cm->protocol_state.tcp.end
+			    - cm->protocol_state.tcp.max_win
+			    - SFE_IPV6_TCP_MAX_ACK_WINDOW
+			    - 1;
+		if (unlikely((s32)(sack - left_edge) < 0)) {
+			struct sfe_ipv6_connection *c = cm->connection;
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv6_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			DEBUG_TRACE("ack: %u before left edge: %u\n", sack, left_edge);
+			if (ret) {
+				sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+			rcu_read_unlock();
+
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TCP_ACK_BEFORE_LEFT_EDGE);
+			return 0;
+		}
+
+		/*
+		 * Have we just seen the largest window size yet for this connection?  If yes
+		 * then we need to record the new value.
+		 */
+		scaled_win = ntohs(tcph->window) << cm->protocol_state.tcp.win_scale;
+		scaled_win += (sack - ack);
+		if (unlikely(cm->protocol_state.tcp.max_win < scaled_win)) {
+			cm->protocol_state.tcp.max_win = scaled_win;
+		}
+
+		/*
+		 * If our sequence and/or ack numbers have advanced then record the new state.
+		 */
+		if (likely((s32)(end - cm->protocol_state.tcp.end) >= 0)) {
+			cm->protocol_state.tcp.end = end;
+		}
+
+		max_end = sack + scaled_win;
+		if (likely((s32)(max_end - counter_cm->protocol_state.tcp.max_end) >= 0)) {
+			counter_cm->protocol_state.tcp.max_end = max_end;
+		}
+	}
+
+	/*
+	 * Check if skb was cloned. If it was, unshare it. Because
+	 * the data area is going to be written in this path and we don't want to
+	 * change the cloned skb's data section.
+	 */
+	if (unlikely(skb_cloned(skb))) {
+		DEBUG_TRACE("%px: skb is a cloned skb\n", skb);
+		skb = skb_unshare(skb, GFP_ATOMIC);
+                if (!skb) {
+			DEBUG_WARN("Failed to unshare the cloned skb\n");
+			rcu_read_unlock();
+			return 0;
+		}
+
+		/*
+		 * Update the iph and tcph pointers with the unshared skb's data area.
+		 */
+		iph = (struct ipv6hdr *)skb->data;
+		tcph = (struct tcphdr *)(skb->data + ihl);
+	}
+
+	/*
+	 * For PPPoE packets, match server MAC and session id
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_PPPOE_DECAP)) {
+		struct pppoe_hdr *ph;
+		struct ethhdr *eth;
+
+		if (unlikely(!sfe_l2_parse_flag_check(l2_info, SFE_L2_PARSE_FLAGS_PPPOE_INGRESS))) {
+			rcu_read_unlock();
+			DEBUG_TRACE("%px: PPPoE header not present in packet for PPPoE rule\n", skb);
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_INVALID_PPPOE_SESSION);
+			return 0;
+		}
+
+		ph = (struct pppoe_hdr *)(skb->head + sfe_l2_pppoe_hdr_offset_get(l2_info));
+		eth = (struct ethhdr *)(skb->head + sfe_l2_hdr_offset_get(l2_info));
+
+		if (unlikely(cm->pppoe_session_id != ntohs(ph->sid)) || unlikely(!(ether_addr_equal((u8*)cm->pppoe_remote_mac, (u8 *)eth->h_source)))) {
+			DEBUG_TRACE("%px: PPPoE sessions with session IDs %d and %d or server MACs %pM and %pM did not match \n",
+							skb, cm->pppoe_session_id, htons(ph->sid), cm->pppoe_remote_mac, eth->h_source);
+			rcu_read_unlock();
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_INVALID_PPPOE_SESSION);
+			return 0;
+		}
+		skb->protocol = htons(l2_info->protocol);
+		this_cpu_inc(si->stats_pcpu->pppoe_decap_packets_forwarded64);
+
+	} else if (unlikely(sfe_l2_parse_flag_check(l2_info, SFE_L2_PARSE_FLAGS_PPPOE_INGRESS))) {
+
+		/*
+		 * If packet contains PPPoE header but CME doesn't contain PPPoE flag yet we are exceptioning the packet to linux
+		 */
+		if (unlikely(!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_BRIDGE_FLOW))) {
+			rcu_read_unlock();
+			DEBUG_TRACE("%px: CME doesn't contain PPPoE flag but packet has PPPoE header\n", skb);
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_PPPOE_NOT_SET_IN_CME);
+			return 0;
+
+		}
+
+		/*
+		 * For bridged flows when packet contains PPPoE header, restore the header back and forward to xmit interface
+		 */
+		__skb_push(skb, (sizeof(struct pppoe_hdr) + sizeof(struct sfe_ppp_hdr)));
+		l2_info->l2_hdr_size -= (sizeof(struct pppoe_hdr) + sizeof(struct sfe_ppp_hdr));
+		this_cpu_inc(si->stats_pcpu->pppoe_bridge_packets_forwarded64);
+	}
+
+	/*
+	 * Check if skb has enough headroom to write L2 headers
+	 */
+	if (unlikely(skb_headroom(skb) < cm->l2_hdr_size)) {
+		rcu_read_unlock();
+		DEBUG_WARN("%px: Not enough headroom: %u\n", skb, skb_headroom(skb));
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_NO_HEADROOM);
+		return 0;
+	}
+
+	/*
+	 * From this point on we're good to modify the packet.
+	 */
+
+	/*
+	 * For PPPoE flows, add PPPoE header before L2 header is added.
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_PPPOE_ENCAP)) {
+		sfe_pppoe_add_header(skb, cm->pppoe_session_id, PPP_IPV6);
+		this_cpu_inc(si->stats_pcpu->pppoe_encap_packets_forwarded64);
+	}
+
+	/*
+	 * Apply packet Mark.
+	 * If Mark was set by the Ingress Qdisc that takes precedence over
+	 * flow policy.
+	 */
+	if (likely(skb->mark == 0)) {
+		if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_MARK)) {
+			skb->mark = cm->mark;
+		}
+	}
+
+	/*
+	 * Update DSCP
+	 * DSCP rewrite table takes precedence over flow policy.
+	 */
+	if (unlikely(si->dscp_rewrite_mark_to_match != 0 &&
+		     si->dscp_rewrite_mark_to_match == skb->mark)) {
+		sfe_ipv6_change_dsfield(iph, si->dscp_rewrite_dscp_to_set);
+	} else if (unlikely(cm->flags &
+			    SFE_IPV6_CONNECTION_MATCH_FLAG_DSCP_REMARK)) {
+		sfe_ipv6_change_dsfield(iph, cm->dscp);
+	}
+
+	/*
+	 * Decrement our hop_limit.
+	 */
+	if (likely(!bridge_flow)) {
+		iph->hop_limit -= 1;
+	}
+
+	/*
+	 * Enable HW csum if rx checksum is verified and xmit interface is CSUM offload capable.
+	 * Note: If L4 csum at Rx was found to be incorrect, we (router) should use incremental L4 checksum here
+	 * so that HW does not re-calculate/replace the L4 csum
+	 */
+	hw_csum = !!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_CSUM_OFFLOAD) && (skb->ip_summed == CHECKSUM_UNNECESSARY);
+
+	/*
+	 * Do we have to perform translations of the source address/port?
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_SRC)) {
+		u16 tcp_csum;
+		u32 sum;
+
+		iph->saddr.s6_addr32[0] = cm->xlate_src_ip[0].addr[0];
+		iph->saddr.s6_addr32[1] = cm->xlate_src_ip[0].addr[1];
+		iph->saddr.s6_addr32[2] = cm->xlate_src_ip[0].addr[2];
+		iph->saddr.s6_addr32[3] = cm->xlate_src_ip[0].addr[3];
+		tcph->source = cm->xlate_src_port;
+
+		if (unlikely(!hw_csum)) {
+			tcp_csum = tcph->check;
+			sum = tcp_csum + cm->xlate_src_csum_adjustment;
+			sum = (sum & 0xffff) + (sum >> 16);
+			tcph->check = (u16)sum;
+		}
+	}
+
+	/*
+	 * Do we have to perform translations of the destination address/port?
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_DEST)) {
+		u16 tcp_csum;
+		u32 sum;
+
+		iph->daddr.s6_addr32[0] = cm->xlate_dest_ip[0].addr[0];
+		iph->daddr.s6_addr32[1] = cm->xlate_dest_ip[0].addr[1];
+		iph->daddr.s6_addr32[2] = cm->xlate_dest_ip[0].addr[2];
+		iph->daddr.s6_addr32[3] = cm->xlate_dest_ip[0].addr[3];
+		tcph->dest = cm->xlate_dest_port;
+
+		if (unlikely(!hw_csum)) {
+			tcp_csum = tcph->check;
+			sum = tcp_csum + cm->xlate_dest_csum_adjustment;
+			sum = (sum & 0xffff) + (sum >> 16);
+			tcph->check = (u16)sum;
+		}
+	}
+
+	/*
+	 * If HW checksum offload is not possible, incremental L4 checksum is used to update the packet.
+	 * Setting ip_summed to CHECKSUM_UNNECESSARY ensures checksum is not recalculated further in packet
+	 * path.
+	 */
+	if (likely(hw_csum)) {
+		skb->ip_summed = CHECKSUM_PARTIAL;
+	} else {
+		skb->ip_summed = CHECKSUM_UNNECESSARY;
+	}
+
+	/*
+	 * Update traffic stats.
+	 */
+	atomic_inc(&cm->rx_packet_count);
+	atomic_add(len, &cm->rx_byte_count);
+
+	xmit_dev = cm->xmit_dev;
+	skb->dev = xmit_dev;
+
+	/*
+	 * Check to see if we need to add VLAN tags
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_INSERT_EGRESS_VLAN_TAG)) {
+		sfe_vlan_add_tag(skb, cm->egress_vlan_hdr_cnt, cm->egress_vlan_hdr);
+	}
+
+	/*
+	 * Check to see if we need to write an Ethernet header.
+	 */
+	if (likely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_L2_HDR)) {
+		if (unlikely(!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR))) {
+			dev_hard_header(skb, xmit_dev, ntohs(skb->protocol),
+					cm->xmit_dest_mac, cm->xmit_src_mac, len);
+		} else {
+			/*
+			 * For the simple case we write this really fast.
+			 */
+			struct ethhdr *eth = (struct ethhdr *)__skb_push(skb, ETH_HLEN);
+
+			eth->h_proto = skb->protocol;
+			ether_addr_copy((u8 *)eth->h_dest, (u8 *)cm->xmit_dest_mac);
+			ether_addr_copy((u8 *)eth->h_source, (u8 *)cm->xmit_src_mac);
+		}
+	}
+
+	/*
+	 * Update priority of skb.
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_PRIORITY_REMARK)) {
+		skb->priority = cm->priority;
+	}
+
+	/*
+	 * For the first packets, check if it could got fast xmit.
+	 */
+	if (unlikely(!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT_FLOW_CHECKED)
+				&& (cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT_DEV_ADMISSION))){
+		cm->features = netif_skb_features(skb);
+		if (likely(sfe_fast_xmit_check(skb, cm->features))) {
+			cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT;
+		}
+		cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT_FLOW_CHECKED;
+	}
+	features = cm->features;
+
+	fast_xmit = !!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT);
+
+	rcu_read_unlock();
+
+	this_cpu_inc(si->stats_pcpu->packets_forwarded64);
+
+	/*
+	 * We're going to check for GSO flags when we transmit the packet so
+	 * start fetching the necessary cache line now.
+	 */
+	prefetch(skb_shinfo(skb));
+
+	/*
+	 * We do per packet condition check before we could fast xmit the
+	 * packet.
+	 */
+	if (likely(fast_xmit && dev_fast_xmit(skb, xmit_dev, features))) {
+		this_cpu_inc(si->stats_pcpu->packets_fast_xmited64);
+		return 1;
+	}
+
+	/*
+	 * Mark that this packet has been fast forwarded.
+	 */
+	skb->fast_forwarded = 1;
+
+	/*
+	 * Send the packet on its way.
+	 */
+	dev_queue_xmit(skb);
+
+	return 1;
+}
diff --git a/qca-nss-sfe/sfe_ipv6_tcp.h b/qca-nss-sfe/sfe_ipv6_tcp.h
new file mode 100644
index 0000000..f7a45c5
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv6_tcp.h
@@ -0,0 +1,23 @@
+/*
+ * sfe_ipv6_tcp.h
+ *	Shortcut forwarding engine header file for IPv6 TCP
+ *
+ * Copyright (c) 2015-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+int sfe_ipv6_recv_tcp(struct sfe_ipv6 *si, struct sk_buff *skb, struct net_device *dev,
+			     unsigned int len, struct ipv6hdr *iph, unsigned int ihl,
+			     bool sync_on_find,struct sfe_l2_info *l2_info);
diff --git a/qca-nss-sfe/sfe_ipv6_tunipip6.c b/qca-nss-sfe/sfe_ipv6_tunipip6.c
new file mode 100644
index 0000000..aaf2f89
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv6_tunipip6.c
@@ -0,0 +1,232 @@
+/*
+ * sfe_ipv6_tunipip6.c
+ *	Shortcut forwarding engine file for IPv6 TUNIPIP6
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/skbuff.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#include <net/ip6_checksum.h>
+#include <net/protocol.h>
+
+#include "sfe_debug.h"
+#include "sfe_api.h"
+#include "sfe.h"
+#include "sfe_flow_cookie.h"
+#include "sfe_ipv6.h"
+#include "sfe_vlan.h"
+
+/*
+ * sfe_ipv6_recv_tunipip6()
+ *	Handle TUNIPIP6 packet receives and forwarding.
+ */
+int sfe_ipv6_recv_tunipip6(struct sfe_ipv6 *si, struct sk_buff *skb, struct net_device *dev,
+			     unsigned int len, struct ipv6hdr *iph, unsigned int ihl,
+				 bool sync_on_find, struct sfe_l2_info *l2_info, bool tun_outer)
+{
+	struct sfe_ipv6_addr *src_ip;
+	struct sfe_ipv6_addr *dest_ip;
+	__be16 src_port = 0;
+	__be16 dest_port = 0;
+	struct sfe_ipv6_connection_match *cm;
+
+	DEBUG_TRACE("%px: sfe: sfe_ipv6_recv_tunipip6 called.\n", skb);
+
+	/*
+	 * Read the IP address information.  Read the IP header data first
+	 * because we've almost certainly got that in the cache.
+	 */
+	src_ip = (struct sfe_ipv6_addr *)iph->saddr.s6_addr32;
+	dest_ip = (struct sfe_ipv6_addr *)iph->daddr.s6_addr32;
+
+	rcu_read_lock();
+
+	/*
+	 * Look for a connection match.
+	 */
+#ifdef CONFIG_NF_FLOW_COOKIE
+	cm = si->sfe_flow_cookie_table[skb->flow_cookie & SFE_FLOW_COOKIE_MASK].match;
+	if (unlikely(!cm)) {
+		cm = sfe_ipv6_find_connection_match_rcu(si, dev, IPPROTO_IPIP, src_ip, src_port, dest_ip, dest_port);
+	}
+#else
+	cm = sfe_ipv6_find_connection_match_rcu(si, dev, IPPROTO_IPIP, src_ip, src_port, dest_ip, dest_port);
+#endif
+	if (unlikely(!cm)) {
+		rcu_read_unlock();
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TUNIPIP6_NO_CONNECTION);
+		DEBUG_TRACE("%px: no connection found\n", skb);
+		return 0;
+	}
+
+	/*
+	 * If our packet has been marked as "sync on find" we will sync the status
+	 * and forward it to slowpath.
+	 */
+	if (unlikely(sync_on_find)) {
+		sfe_ipv6_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TUNIPIP6_SYNC_ON_FIND);
+		DEBUG_TRACE("%px: Sync on find\n", skb);
+
+		return 0;
+	}
+
+	/*
+	 * If cm->proto is set, it means the decap path.
+	 * Otherwise we forward the packet in encap path.
+	 */
+	if(cm->proto) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+		const struct inet6_protocol *ipprot = cm->proto;
+#else
+		struct inet6_protocol *ipprot = cm->proto;
+#endif
+
+		/*
+		 * Do we expect an ingress VLAN tag for this flow?
+		 * Note: We will only have ingress tag check in decap direction.
+		 */
+		if (unlikely(!sfe_vlan_validate_ingress_tag(skb, cm->ingress_vlan_hdr_cnt, cm->ingress_vlan_hdr, l2_info))) {
+			rcu_read_unlock();
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_INGRESS_VLAN_TAG_MISMATCH);
+			DEBUG_TRACE("VLAN tag mismatch. skb=%px\n"
+				"cm: %u [0]=%x/%x [1]=%x/%x\n"
+				"l2_info+: %u [0]=%x/%x [1]=%x/%x\n", skb,
+				cm->ingress_vlan_hdr_cnt,
+				htons(cm->ingress_vlan_hdr[0].tpid), cm->ingress_vlan_hdr[0].tci,
+				htons(cm->ingress_vlan_hdr[1].tpid), cm->ingress_vlan_hdr[1].tci,
+				l2_info->vlan_hdr_cnt,
+				htons(l2_info->vlan_hdr[0].tpid), l2_info->vlan_hdr[0].tci,
+				htons(l2_info->vlan_hdr[1].tpid), l2_info->vlan_hdr[1].tci);
+			return 0;
+		}
+		skb_reset_network_header(skb);
+		skb_pull(skb, ihl);
+		skb_reset_transport_header(skb);
+
+		/*
+		 * ipprot->handler(skb) will always return 0;
+		 * There is no way to tell whether the packet is dropped later in linux or not.
+		 * Hence here inc the byte/packet count always.
+		 */
+		atomic_inc(&cm->rx_packet_count);
+		atomic_add(len, &cm->rx_byte_count);
+		this_cpu_inc(si->stats_pcpu->packets_forwarded64);
+		rcu_read_unlock();
+		DEBUG_TRACE("%px: %s decap done \n",skb, __func__);
+
+		/*
+		 * Update top interface for tunnel searching.
+		 */
+		skb->dev = cm->top_interface_dev;
+		ipprot->handler(skb);
+		return 1;
+	}
+
+	/*
+	 * Check if skb has enough headroom to write L2 headers
+	 */
+	if (unlikely(skb_headroom(skb) < cm->l2_hdr_size)) {
+		rcu_read_unlock();
+		DEBUG_WARN("%px: Not enough headroom: %u\n", skb, skb_headroom(skb));
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_NO_HEADROOM);
+		return 0;
+	}
+
+	/*
+	 * If our packet is larger than the MTU of the transmit interface then
+	 * we can't forward it easily.
+	 */
+	if (unlikely(len > cm->xmit_dev_mtu)) {
+		sfe_ipv6_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_TUNIPIP6_NEEDS_FRAGMENTATION);
+		DEBUG_TRACE("%px: Larger than mtu\n", skb);
+		return 0;
+	}
+
+	/*
+	 * Update DSCP
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_DSCP_REMARK)) {
+		sfe_ipv6_change_dsfield(iph, cm->dscp);
+	}
+
+	/*
+	 * Update traffic stats.
+	 */
+	atomic_inc(&cm->rx_packet_count);
+	atomic_add(len, &cm->rx_byte_count);
+
+	skb->dev = cm->xmit_dev;
+
+	/*
+	 * Check to see if we need to add VLAN tags
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_INSERT_EGRESS_VLAN_TAG)) {
+		sfe_vlan_add_tag(skb, cm->egress_vlan_hdr_cnt, cm->egress_vlan_hdr);
+	}
+
+	/*
+	 * Check to see if we need to write a header.
+	 */
+	if (likely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_L2_HDR)) {
+		if (unlikely(!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR))) {
+			dev_hard_header(skb, cm->xmit_dev, ntohs(skb->protocol),
+					cm->xmit_dest_mac, cm->xmit_src_mac, len);
+		} else {
+			struct ethhdr *eth = (struct ethhdr *)__skb_push(skb, ETH_HLEN);
+			eth->h_proto = skb->protocol;
+			ether_addr_copy((u8 *)eth->h_dest, (u8 *)cm->xmit_dest_mac);
+			ether_addr_copy((u8 *)eth->h_source, (u8 *)cm->xmit_src_mac);
+		}
+	}
+
+	/*
+	 * Update priority of skb.
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_PRIORITY_REMARK)) {
+		skb->priority = cm->priority;
+	}
+
+	/*
+	 * Mark outgoing packet.
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_MARK)) {
+		skb->mark = cm->mark;
+	}
+
+	rcu_read_unlock();
+
+	this_cpu_inc(si->stats_pcpu->packets_forwarded64);
+
+	/*
+	 * We're going to check for GSO flags when we transmit the packet so
+	 * start fetching the necessary cache line now.
+	 */
+	prefetch(skb_shinfo(skb));
+
+	/*
+	 * Mark that this packet has been fast forwarded and send it on its way.
+	 */
+	skb->fast_forwarded = 1;
+	dev_queue_xmit(skb);
+
+	return 1;
+}
diff --git a/qca-nss-sfe/sfe_ipv6_tunipip6.h b/qca-nss-sfe/sfe_ipv6_tunipip6.h
new file mode 100644
index 0000000..d6f4f9b
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv6_tunipip6.h
@@ -0,0 +1,22 @@
+/*
+ * sfe_ipv6_tunipip6.h
+ *	Shortcut forwarding engine header file for IPv6 TUNIPIP6
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+int sfe_ipv6_recv_tunipip6(struct sfe_ipv6 *si, struct sk_buff *skb, struct net_device *dev,
+			     unsigned int len, struct ipv6hdr *iph, unsigned int ihl,
+				bool sync_on_find, struct sfe_l2_info *l2_info, bool tun_outer);
diff --git a/qca-nss-sfe/sfe_ipv6_udp.c b/qca-nss-sfe/sfe_ipv6_udp.c
new file mode 100644
index 0000000..445b43f
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv6_udp.c
@@ -0,0 +1,589 @@
+/*
+ * sfe_ipv6_udp.c
+ *	Shortcut forwarding engine file for IPv6 UDP
+ *
+ * Copyright (c) 2015-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/skbuff.h>
+#include <net/udp.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#include <net/ip6_checksum.h>
+
+#include "sfe_debug.h"
+#include "sfe_api.h"
+#include "sfe.h"
+#include "sfe_flow_cookie.h"
+#include "sfe_ipv6.h"
+#include "sfe_pppoe.h"
+#include "sfe_vlan.h"
+
+/*
+ * sfe_ipv6_udp_sk_deliver()
+ *	Deliver the packet to the protocol handler registered with Linux.
+ *	To be called under rcu_read_lock()
+ *	Returns:
+ *	1 if the packet needs to be passed to Linux.
+ *	0 if the packet is processed successfully.
+ *	-1 if the packet is dropped in SFE.
+ */
+static int sfe_ipv6_udp_sk_deliver(struct sk_buff *skb, struct sfe_ipv6_connection_match *cm,
+					 unsigned int ihl)
+{
+	int (*encap_rcv)(struct sock *sk, struct sk_buff *skb);
+	struct udp_sock *up;
+	struct udphdr *udph;
+	struct sock *sk;
+	int ret;
+
+	/*
+	 * Call the decap handler
+	 */
+	up = rcu_dereference(cm->up);
+	encap_rcv = READ_ONCE(up->encap_rcv);
+	if (unlikely(!encap_rcv)) {
+		DEBUG_ERROR("sfe: Error: up->encap_rcv is NULL\n");
+		return 1;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+	nf_reset(skb);
+#else
+	nf_reset_ct(skb);
+#endif
+	skb_pull(skb, ihl);
+	skb_reset_transport_header(skb);
+
+	udph = udp_hdr(skb);
+	if (unlikely(skb->ip_summed != CHECKSUM_UNNECESSARY) && unlikely(skb->ip_summed != CHECKSUM_COMPLETE)) {
+		/*
+		 * Set Pseudo Checksum using Linux API
+		 */
+		if (unlikely(udp6_csum_init(skb, udp_hdr(skb), IPPROTO_UDP))) {
+			DEBUG_ERROR("sfe: udp checksum init() failed: %p\n", skb);
+			kfree_skb(skb);
+			return -1;
+		}
+
+		/*
+		 * Verify checksum before giving to encap_rcv handler function.
+		 */
+		if (unlikely(udp_lib_checksum_complete(skb))) {
+			DEBUG_ERROR("sfe: Invalid udp checksum: %p\n", skb);
+			kfree_skb(skb);
+			return -1;
+		}
+	}
+
+	/*
+	 * Mark that this packet has been fast forwarded.
+	 */
+	sk = (struct sock *)up;
+
+	/*
+	 * TODO: Find the fix  to set skb->ip_summed = CHECKSUM_NONE;
+	 */
+
+	/*
+	 * encap_rcv() returns the following value:
+	 * =0 if skb was successfully passed to the encap
+	 *    handler or was discarded by it.
+	 * >0 if skb should be passed on to UDP.
+	 * <0 if skb should be resubmitted as proto -N
+	 */
+	ret = encap_rcv(sk, skb);
+	if (unlikely(ret)) {
+
+		/*
+		 * If encap_rcv fails, vxlan driver drops the packet.
+		 * No need to free the skb here.
+		 */
+		DEBUG_ERROR("sfe: udp-decap API return error: %d\n", ret);
+		return -1;
+	}
+
+	DEBUG_TRACE("sfe: udp-decap API encap_rcv successful\n");
+	return 0;
+}
+
+/*
+ * sfe_ipv6_recv_udp()
+ *	Handle UDP packet receives and forwarding.
+ */
+int sfe_ipv6_recv_udp(struct sfe_ipv6 *si, struct sk_buff *skb, struct net_device *dev,
+			     unsigned int len, struct ipv6hdr *iph, unsigned int ihl, bool sync_on_find, struct sfe_l2_info *l2_info, bool tun_outer)
+{
+	struct udphdr *udph;
+	struct sfe_ipv6_addr *src_ip;
+	struct sfe_ipv6_addr *dest_ip;
+	__be16 src_port;
+	__be16 dest_port;
+	struct sfe_ipv6_connection_match *cm;
+	struct net_device *xmit_dev;
+	int ret;
+	bool hw_csum;
+	bool bridge_flow;
+	bool fast_xmit;
+	netdev_features_t features;
+
+	DEBUG_TRACE("%px: sfe: sfe_ipv6_recv_udp called.\n", skb);
+
+	/*
+	 * Is our packet too short to contain a valid UDP header?
+	 */
+	if (!pskb_may_pull(skb, (sizeof(struct udphdr) + ihl))) {
+
+		sfe_ipv6_exception_stats_inc(si,SFE_IPV6_EXCEPTION_EVENT_UDP_HEADER_INCOMPLETE);
+		DEBUG_TRACE("packet too short for UDP header\n");
+		return 0;
+	}
+
+	/*
+	 * Read the IP address and port information.  Read the IP header data first
+	 * because we've almost certainly got that in the cache.  We may not yet have
+	 * the UDP header cached though so allow more time for any prefetching.
+	 */
+	src_ip = (struct sfe_ipv6_addr *)iph->saddr.s6_addr32;
+	dest_ip = (struct sfe_ipv6_addr *)iph->daddr.s6_addr32;
+
+	udph = (struct udphdr *)(skb->data + ihl);
+	src_port = udph->source;
+	dest_port = udph->dest;
+
+	rcu_read_lock();
+
+	/*
+	 * Look for a connection match.
+	 */
+#ifdef CONFIG_NF_FLOW_COOKIE
+	cm = si->sfe_flow_cookie_table[skb->flow_cookie & SFE_FLOW_COOKIE_MASK].match;
+	if (unlikely(!cm)) {
+		cm = sfe_ipv6_find_connection_match_rcu(si, dev, IPPROTO_UDP, src_ip, src_port, dest_ip, dest_port);
+	}
+#else
+	cm = sfe_ipv6_find_connection_match_rcu(si, dev, IPPROTO_UDP, src_ip, src_port, dest_ip, dest_port);
+#endif
+	if (unlikely(!cm)) {
+
+		/*
+		 * Try a 4-tuple lookup; required for tunnels like VxLAN.
+		 */
+		cm = sfe_ipv6_find_connection_match_rcu(si, dev, IPPROTO_UDP, src_ip, 0, dest_ip, dest_port);
+		if (unlikely(!cm)) {
+			rcu_read_unlock();
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_UDP_NO_CONNECTION);
+			DEBUG_TRACE("no connection found\n");
+			return 0;
+		}
+		DEBUG_TRACE("sfe: 4-tuple lookup successful\n");
+	}
+
+	/*
+	 * Do we expect an ingress VLAN tag for this flow?
+	 */
+	if (unlikely(!sfe_vlan_validate_ingress_tag(skb, cm->ingress_vlan_hdr_cnt, cm->ingress_vlan_hdr, l2_info))) {
+		rcu_read_unlock();
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_INGRESS_VLAN_TAG_MISMATCH);
+		DEBUG_TRACE("VLAN tag mismatch. skb=%px\n", skb);
+		return 0;
+	}
+
+	/*
+	 * Source interface validate.
+	 */
+	if (unlikely((cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK) && (cm->match_dev != dev))) {
+		if (!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_SRC_INTERFACE_CHECK_NO_FLUSH)) {
+			struct sfe_ipv6_connection *c = cm->connection;
+			DEBUG_TRACE("flush on source interface check failure\n");
+			spin_lock_bh(&si->lock);
+			ret = sfe_ipv6_remove_connection(si, c);
+			spin_unlock_bh(&si->lock);
+
+			if (ret) {
+				sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH);
+			}
+		}
+		rcu_read_unlock();
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_INVALID_SRC_IFACE);
+		DEBUG_TRACE("exception the packet on source interface check failure\n");
+		return 0;
+	}
+
+	/*
+	 * If our packet has been marked as "flush on find" we can't actually
+	 * forward it in the fast path, but now that we've found an associated
+	 * connection we need sync its status before exception it to slow path.
+	 */
+	if (unlikely(sync_on_find)) {
+		sfe_ipv6_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_UDP_IP_OPTIONS_OR_INITIAL_FRAGMENT);
+		DEBUG_TRACE("Sync on find\n");
+		return 0;
+	}
+
+#ifdef CONFIG_XFRM
+	/*
+	 * We can't accelerate the flow on this direction, just let it go
+	 * through the slow path.
+	 */
+	if (unlikely(!cm->flow_accel)) {
+		rcu_read_unlock();
+		this_cpu_inc(si->stats_pcpu->packets_not_forwarded64);
+		return 0;
+	}
+#endif
+
+	bridge_flow = !!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_BRIDGE_FLOW);
+
+	/*
+	 * Does our hop_limit allow forwarding?
+	 */
+	if (likely(!bridge_flow)) {
+		if (unlikely(iph->hop_limit < 2)) {
+			sfe_ipv6_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+			rcu_read_unlock();
+
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_UDP_SMALL_TTL);
+			DEBUG_TRACE("hop_limit too low\n");
+			return 0;
+		}
+	}
+
+	/*
+	 * If our packet is larger than the MTU of the transmit interface then
+	 * we can't forward it easily.
+	 */
+	if (unlikely(len > cm->xmit_dev_mtu)) {
+		sfe_ipv6_sync_status(si, cm->connection, SFE_SYNC_REASON_STATS);
+		rcu_read_unlock();
+
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_UDP_NEEDS_FRAGMENTATION);
+		DEBUG_TRACE("Larger than MTU\n");
+		return 0;
+	}
+
+	/*
+	 * Check if skb was cloned. If it was, unshare it. Because
+	 * the data area is going to be written in this path and we don't want to
+	 * change the cloned skb's data section.
+	 */
+	if (unlikely(skb_cloned(skb))) {
+		DEBUG_TRACE("%px: skb is a cloned skb\n", skb);
+		skb = skb_unshare(skb, GFP_ATOMIC);
+                if (!skb) {
+			DEBUG_WARN("Failed to unshare the cloned skb\n");
+			rcu_read_unlock();
+			return 0;
+		}
+
+		/*
+		 * Update the iph and udph pointers with the unshared skb's data area.
+		 */
+		iph = (struct ipv6hdr *)skb->data;
+		udph = (struct udphdr *)(skb->data + ihl);
+	}
+
+	/*
+	 * For PPPoE packets, match server MAC and session id
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_PPPOE_DECAP)) {
+		struct pppoe_hdr *ph;
+		struct ethhdr *eth;
+
+		if (unlikely(!sfe_l2_parse_flag_check(l2_info, SFE_L2_PARSE_FLAGS_PPPOE_INGRESS))) {
+			rcu_read_unlock();
+			DEBUG_TRACE("%px: PPPoE header not present in packet for PPPoE rule\n", skb);
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_INCORRECT_PPPOE_PARSING);
+			return 0;
+		}
+
+		ph = (struct pppoe_hdr *)(skb->head + sfe_l2_pppoe_hdr_offset_get(l2_info));
+		eth = (struct ethhdr *)(skb->head + sfe_l2_hdr_offset_get(l2_info));
+		if (unlikely(cm->pppoe_session_id != ntohs(ph->sid)) || unlikely(!(ether_addr_equal((u8*)cm->pppoe_remote_mac, (u8 *)eth->h_source)))) {
+			DEBUG_TRACE("%px: PPPoE sessions with session IDs %d and %d or server MACs %pM and %pM did not match\n",
+							skb, cm->pppoe_session_id, htons(ph->sid), cm->pppoe_remote_mac, eth->h_source);
+			rcu_read_unlock();
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_INVALID_PPPOE_SESSION);
+			return 0;
+		}
+		skb->protocol = htons(l2_info->protocol);
+		this_cpu_inc(si->stats_pcpu->pppoe_decap_packets_forwarded64);
+
+	} else if (unlikely(sfe_l2_parse_flag_check(l2_info, SFE_L2_PARSE_FLAGS_PPPOE_INGRESS))) {
+
+		/*
+		 * If packet contains PPPoE header but CME doesn't contain PPPoE flag yet we are exceptioning the packet to linux
+		 */
+
+		if (unlikely(!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_BRIDGE_FLOW))) {
+			rcu_read_unlock();
+			DEBUG_TRACE("%px: CME doesn't contain PPPoE flag but packet has PPPoE header\n", skb);
+			sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_INCORRECT_PPPOE_PARSING);
+			return 0;
+		}
+
+		/*
+		 * For bridged flows when packet contains PPPoE header, restore the header back and forward to xmit interface
+		 */
+		__skb_push(skb, (sizeof(struct pppoe_hdr) + sizeof(struct sfe_ppp_hdr)));
+		l2_info->l2_hdr_size -= (sizeof(struct pppoe_hdr) + sizeof(struct sfe_ppp_hdr));
+		this_cpu_inc(si->stats_pcpu->pppoe_bridge_packets_forwarded64);
+
+	}
+
+	/*
+	 * Check if skb has enough headroom to write L2 headers
+	 */
+	if (unlikely(skb_headroom(skb) < cm->l2_hdr_size)) {
+		rcu_read_unlock();
+		DEBUG_WARN("%px: Not enough headroom: %u\n", skb, skb_headroom(skb));
+		sfe_ipv6_exception_stats_inc(si, SFE_IPV6_EXCEPTION_EVENT_NO_HEADROOM);
+		return 0;
+	}
+
+	/*
+	 * From this point on we're good to modify the packet.
+	 */
+
+	/*
+	 * For PPPoE flows, add PPPoE header before L2 header is added.
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_PPPOE_ENCAP)) {
+		sfe_pppoe_add_header(skb, cm->pppoe_session_id, PPP_IPV6);
+		this_cpu_inc(si->stats_pcpu->pppoe_encap_packets_forwarded64);
+	}
+
+	/*
+	 * UDP sock will be valid only in decap-path.
+	 * Call encap_rcv function associated with udp_sock in cm.
+	 */
+	if (unlikely(cm->up)) {
+
+		/*
+		 * Call decap handler associated with sock.
+		 * Also validates UDP checksum before calling decap handler.
+		 */
+		ret = sfe_ipv6_udp_sk_deliver(skb, cm, ihl);
+		if (unlikely(ret == -1)) {
+			rcu_read_unlock();
+			this_cpu_inc(si->stats_pcpu->packets_dropped64);
+			return 1;
+		} else if (unlikely(ret == 1)) {
+			rcu_read_unlock();
+			this_cpu_inc(si->stats_pcpu->packets_not_forwarded64);
+			return 0;
+		}
+
+		/*
+		 * Update traffic stats
+	 	*/
+		atomic_inc(&cm->rx_packet_count);
+		atomic_add(len, &cm->rx_byte_count);
+
+		rcu_read_unlock();
+		this_cpu_inc(si->stats_pcpu->packets_forwarded64);
+		DEBUG_TRACE("%p: sfe: sfe_ipv4_recv_udp -> encap_rcv done.\n", skb);
+		return 1;
+	}
+
+	/*
+	 * Apply packet Mark.
+	 * If Mark was set by the Ingress Qdisc that takes precedence over
+	 * flow policy.
+	 */
+	if (likely(skb->mark == 0)) {
+		if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_MARK)) {
+			skb->mark = cm->mark;
+		}
+	}
+
+	/*
+	 * Update DSCP
+	 * DSCP rewrite table takes precedence over flow policy.
+	 */
+	if (unlikely(si->dscp_rewrite_mark_to_match != 0 &&
+		     si->dscp_rewrite_mark_to_match == skb->mark)) {
+		sfe_ipv6_change_dsfield(iph, si->dscp_rewrite_dscp_to_set);
+	} else if (unlikely(cm->flags &
+			    SFE_IPV6_CONNECTION_MATCH_FLAG_DSCP_REMARK)) {
+		sfe_ipv6_change_dsfield(iph, cm->dscp);
+	}
+
+	/*
+	 * Decrement our hop_limit.
+	 */
+	if (likely(!bridge_flow)) {
+		iph->hop_limit -= (u8)!tun_outer;
+	}
+
+	/*
+	 * Enable HW csum if rx checksum is verified and xmit interface is CSUM offload capable.
+	 * Note: If L4 csum at Rx was found to be incorrect, we (router) should use incremental L4 checksum here
+	 * so that HW does not re-calculate/replace the L4 csum
+	 */
+	hw_csum = !!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_CSUM_OFFLOAD) && (skb->ip_summed == CHECKSUM_UNNECESSARY);
+
+	/*
+	 * Do we have to perform translations of the source address/port?
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_SRC)) {
+		u16 udp_csum;
+
+		iph->saddr.s6_addr32[0] = cm->xlate_src_ip[0].addr[0];
+		iph->saddr.s6_addr32[1] = cm->xlate_src_ip[0].addr[1];
+		iph->saddr.s6_addr32[2] = cm->xlate_src_ip[0].addr[2];
+		iph->saddr.s6_addr32[3] = cm->xlate_src_ip[0].addr[3];
+		udph->source = cm->xlate_src_port;
+
+		/*
+		 * Do we have a non-zero UDP checksum?  If we do then we need
+		 * to update it.
+		 */
+		if (unlikely(!hw_csum)) {
+			udp_csum = udph->check;
+			if (likely(udp_csum)) {
+				u32 sum = udp_csum + cm->xlate_src_csum_adjustment;
+				sum = (sum & 0xffff) + (sum >> 16);
+				udph->check = (u16)sum;
+			}
+		}
+	}
+
+	/*
+	 * Do we have to perform translations of the destination address/port?
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_DEST)) {
+		u16 udp_csum;
+
+		iph->daddr.s6_addr32[0] = cm->xlate_dest_ip[0].addr[0];
+		iph->daddr.s6_addr32[1] = cm->xlate_dest_ip[0].addr[1];
+		iph->daddr.s6_addr32[2] = cm->xlate_dest_ip[0].addr[2];
+		iph->daddr.s6_addr32[3] = cm->xlate_dest_ip[0].addr[3];
+		udph->dest = cm->xlate_dest_port;
+
+		/*
+		 * Do we have a non-zero UDP checksum?  If we do then we need
+		 * to update it.
+		 */
+		if (unlikely(!hw_csum)) {
+			udp_csum = udph->check;
+			if (likely(udp_csum)) {
+				u32 sum = udp_csum + cm->xlate_dest_csum_adjustment;
+				sum = (sum & 0xffff) + (sum >> 16);
+				udph->check = (u16)sum;
+			}
+		}
+	}
+
+	/*
+	 * If HW checksum offload is not possible, incremental L4 checksum is used to update the packet.
+	 * Setting ip_summed to CHECKSUM_UNNECESSARY ensures checksum is not recalculated further in packet
+	 * path.
+	 */
+	if (likely(hw_csum)) {
+		skb->ip_summed = CHECKSUM_PARTIAL;
+	}
+
+	/*
+	 * Update traffic stats.
+	 */
+	atomic_inc(&cm->rx_packet_count);
+	atomic_add(len, &cm->rx_byte_count);
+
+	xmit_dev = cm->xmit_dev;
+	skb->dev = xmit_dev;
+
+	/*
+	 * Check to see if we need to add VLAN tags
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_INSERT_EGRESS_VLAN_TAG)) {
+		sfe_vlan_add_tag(skb, cm->egress_vlan_hdr_cnt, cm->egress_vlan_hdr);
+	}
+
+	/*
+	 * Check to see if we need to write an Ethernet header.
+	 */
+	if (likely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_L2_HDR)) {
+		if (unlikely(!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR))) {
+			dev_hard_header(skb, xmit_dev, ntohs(skb->protocol),
+					cm->xmit_dest_mac, cm->xmit_src_mac, len);
+		} else {
+			/*
+			 * For the simple case we write this really fast.
+			 */
+			struct ethhdr *eth = (struct ethhdr *)__skb_push(skb, ETH_HLEN);
+			eth->h_proto = skb->protocol;
+			ether_addr_copy((u8 *)eth->h_dest, (u8 *)cm->xmit_dest_mac);
+			ether_addr_copy((u8 *)eth->h_source, (u8 *)cm->xmit_src_mac);
+		}
+	}
+
+	/*
+	 * Update priority of skb.
+	 */
+	if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_PRIORITY_REMARK)) {
+		skb->priority = cm->priority;
+	}
+
+	/*
+	 * For the first packets, check if it could got fast xmit.
+	 */
+	if (unlikely(!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT_FLOW_CHECKED)
+				&& (cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT_DEV_ADMISSION))){
+		cm->features = netif_skb_features(skb);
+		if (likely(sfe_fast_xmit_check(skb, cm->features))) {
+			cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT;
+		}
+		cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT_FLOW_CHECKED;
+	}
+	features = cm->features;
+
+	fast_xmit = !!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_FAST_XMIT);
+
+	rcu_read_unlock();
+
+	this_cpu_inc(si->stats_pcpu->packets_forwarded64);
+
+	/*
+	 * We're going to check for GSO flags when we transmit the packet so
+	 * start fetching the necessary cache line now.
+	 */
+	prefetch(skb_shinfo(skb));
+
+	/*
+	 * We do per packet condition check before we could fast xmit the
+	 * packet.
+	 */
+	if (likely(fast_xmit && dev_fast_xmit(skb, xmit_dev, features))) {
+		this_cpu_inc(si->stats_pcpu->packets_fast_xmited64);
+		return 1;
+	}
+
+	/*
+	 * Mark that this packet has been fast forwarded.
+	 */
+	skb->fast_forwarded = 1;
+
+	/*
+	 * Send the packet on its way.
+	 */
+	dev_queue_xmit(skb);
+
+	return 1;
+}
diff --git a/qca-nss-sfe/sfe_ipv6_udp.h b/qca-nss-sfe/sfe_ipv6_udp.h
new file mode 100644
index 0000000..c350c72
--- /dev/null
+++ b/qca-nss-sfe/sfe_ipv6_udp.h
@@ -0,0 +1,23 @@
+/*
+ * sfe_ipv6_udp.h
+ *	Shortcut forwarding engine header file for IPv6 UDP
+ *
+ * Copyright (c) 2015-2016, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+int sfe_ipv6_recv_udp(struct sfe_ipv6 *si, struct sk_buff *skb, struct net_device *dev,
+			     unsigned int len, struct ipv6hdr *iph, unsigned int ihl, bool sync_on_find,
+			     struct sfe_l2_info *l2_info, bool tun_outer);
diff --git a/qca-nss-sfe/sfe_pppoe.c b/qca-nss-sfe/sfe_pppoe.c
new file mode 100644
index 0000000..996d4d6
--- /dev/null
+++ b/qca-nss-sfe/sfe_pppoe.c
@@ -0,0 +1,132 @@
+/*
+ * sfe_pppoe.c
+ *     API for shortcut forwarding engine PPPoE flows
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/skbuff.h>
+#include <linux/if_pppox.h>
+#include <linux/ppp_defs.h>
+
+#include "sfe_debug.h"
+#include "sfe_api.h"
+#include "sfe.h"
+#include "sfe_pppoe.h"
+
+/*
+ * sfe_pppoe_add_header()
+ *	Add PPPoE header.
+ *
+ * skb->data will point to PPPoE header after the function
+ */
+void sfe_pppoe_add_header(struct sk_buff *skb, u16 pppoe_session_id, u16 ppp_protocol)
+{
+	u16 *l2_header;
+	struct pppoe_hdr *ph;
+	struct sfe_ppp_hdr *ppp;
+	u16 *l3_header = (u16 *)skb->data;
+
+	/*
+	 * PPPoE header (6 bytes) + PPP header (2 bytes)
+	 *
+	 * Hence move by 8 bytes to accomodate PPPoE header
+	 */
+	l2_header = l3_header - ((sizeof(struct pppoe_hdr) + sizeof(struct sfe_ppp_hdr)) / 2);
+
+	/*
+	 * Headers in skb will look like in below sequence
+	 *	| PPPoE hdr(6 bytes) | PPP hdr (2 bytes) | L3 hdr |
+	 *
+	 *	The length field in the PPPoE header indicates the length of the PPPoE payload which
+	 *	consists of a 2-byte PPP header plus a skb->len.
+	 */
+	ph = (struct pppoe_hdr *)l2_header;
+	ph->ver = 1;
+	ph->type = 1;
+	ph->code = 0;
+	ph->sid = htons(pppoe_session_id);
+	ph->length = htons(skb->len + sizeof(struct sfe_ppp_hdr));
+	skb->protocol = htons(ETH_P_PPP_SES);
+
+	/*
+	 * Insert the PPP header protocol
+	 */
+	ppp = (struct sfe_ppp_hdr *)(l2_header + (sizeof(struct pppoe_hdr) / 2));
+	ppp->protocol = htons(ppp_protocol);
+
+	/*
+	 * L2 header offset will point to PPPoE header,
+	 */
+	__skb_push(skb, (sizeof(struct pppoe_hdr) + sizeof(struct sfe_ppp_hdr)));
+}
+
+/*
+ * sfe_pppoe_parse_hdr()
+ *	Parse PPPoE header
+ *
+ * Returns true if the packet is good for further processing.
+ */
+bool sfe_pppoe_parse_hdr(struct sk_buff *skb, struct sfe_l2_info *l2_info)
+{
+	unsigned int len;
+	int pppoe_len;
+	struct sfe_ppp_hdr *ppp;
+	struct pppoe_hdr *ph = (struct pppoe_hdr *)skb->data;
+
+	/*
+	 * Check that we have space for PPPoE header here.
+	 */
+	if (unlikely(!pskb_may_pull(skb, (sizeof(struct pppoe_hdr) + sizeof(struct sfe_ppp_hdr))))) {
+		DEBUG_TRACE("%px: packet too short for PPPoE header\n", skb);
+		return false;
+	}
+
+	len = skb->len;
+	pppoe_len = ntohs(ph->length);
+	if (unlikely(len < pppoe_len)) {
+		DEBUG_TRACE("%px: len: %u is too short to %u\n", skb, len, pppoe_len);
+		return false;
+	}
+
+	ppp = (struct sfe_ppp_hdr *)((u8*)ph + sizeof(*ph));
+
+	/*
+	 * Converting PPP protocol values to ether type protocol values
+	 */
+	switch(ntohs(ppp->protocol)) {
+	case PPP_IP:
+		sfe_l2_protocol_set(l2_info, ETH_P_IP);
+		break;
+
+	case PPP_IPV6:
+		sfe_l2_protocol_set(l2_info, ETH_P_IPV6);
+		break;
+
+	case PPP_LCP:
+		DEBUG_TRACE("%px: LCP packets are not supported in SFE\n", skb);
+		return false;
+
+	default:
+		DEBUG_TRACE("%px: Unsupported protocol : %d in PPP header\n", skb, ntohs(ppp->protocol));
+		return false;
+	}
+
+	sfe_l2_parse_flag_set(l2_info, SFE_L2_PARSE_FLAGS_PPPOE_INGRESS);
+	sfe_l2_pppoe_hdr_offset_set(l2_info, (skb->data - skb->head));
+	sfe_l2_hdr_size_set(l2_info, (sizeof(struct pppoe_hdr) + sizeof(struct sfe_ppp_hdr)));
+
+	return true;
+}
diff --git a/qca-nss-sfe/sfe_pppoe.h b/qca-nss-sfe/sfe_pppoe.h
new file mode 100644
index 0000000..bf11c0d
--- /dev/null
+++ b/qca-nss-sfe/sfe_pppoe.h
@@ -0,0 +1,38 @@
+/*
+ * sfe_pppoe.h
+ *	Shortcut flow acceleration for PPPoE flow
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __SFE_PPPOE_H
+#define __SFE_PPPOE_H
+
+#include <linux/ppp_defs.h>
+#include <linux/if_pppox.h>
+
+struct sfe_ppp_hdr {
+	u16 protocol;
+};
+
+/*
+ * PPPoE (6-byte) + PPP (2-byte) header.
+ */
+#define SFE_PPPOE_SESSION_HEADER_SIZE 8
+
+void sfe_pppoe_add_header(struct sk_buff *skb, u16 pppoe_session_id, u16 ppp_protocol);
+bool sfe_pppoe_parse_hdr(struct sk_buff *skb, struct sfe_l2_info *l2_info);
+
+#endif /* __SFE_PPPOE_H */
diff --git a/qca-nss-sfe/sfe_vlan.h b/qca-nss-sfe/sfe_vlan.h
new file mode 100644
index 0000000..505b24b
--- /dev/null
+++ b/qca-nss-sfe/sfe_vlan.h
@@ -0,0 +1,217 @@
+/*
+ * sfe_vlan.h
+ *	Shortcut flow acceleration for 802.1AD/802.1Q flow
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __SFE_VLAN_H
+#define __SFE_VLAN_H
+
+#include <linux/if_vlan.h>
+
+/*
+ * sfe_vlan_check_and_parse_tag()
+ *
+ * case 1: QinQ frame (e.g. outer tag = 88a80032, inner tag = 81000001):
+ * When entering this function:
+ * ----+-----------------+-----|-----+-----------+-----+---------
+ *     |DMAC    |SMAC    |88|a8|00|32|81|00|00|01|08|00|45|00|
+ * ----+-----------------+-----A-----+-----------+-----+---------
+ *                            skb->data
+ *   skb->protocol = ntohs(ETH_P_8021AD)
+ *   skb->vlan_proto = 0
+ *   skb->vlan_tci = 0
+ *   skb->vlan_present = 0
+ * When exiting:
+ * ----+-----------------+-----------+-----------+-----+---------
+ *     |DMAC    |SMAC    |88|a8|00|32|81|00|00|01|08|00|45|00|
+ * ----+-----------------+-----------+-----------+-----A---------
+ *                                                    skb->data
+ *   skb->protocol = ntohs(ETH_P_IP)
+ *   skb->vlan_proto = 0
+ *   skb->vlan_tci = 0
+ *   skb->vlan_present = 0
+ *   l2_info->vlan_hdr_cnt = 2
+ *   l2_info->vlan_hdr[0].tpid = ntohs(ETH_P_8021AD)
+ *   l2_info->vlan_hdr[0].tci = 0x0032
+ *   l2_info->vlan_hdr[1].tpid = ntohs(ETH_P_8021Q)
+ *   l2_info->vlan_hdr[1].tci = 0x0001
+ *   l2_info->protocol = ETH_P_IP
+ *
+ * case 2: 802.1Q frame (e.g. the tag is 81000001):
+ * When entering this function:
+ * ----+-----------------+-----|-----+-----+---------
+ *     |DMAC    |SMAC    |81|00|00|01|08|00|45|00|
+ * ----+-----------------+-----A-----+-----+---------
+ *                            skb->data
+ *   skb->protocol = ntohs(ETH_P_8021Q)
+ *   skb->vlan_proto = 0
+ *   skb->vlan_tci = 0
+ *   skb->vlan_present = 0
+ * When exiting:
+ * ----+-----------------+-----------+-----+---------
+ *     |DMAC    |SMAC    |81|00|00|01|08|00|45|00|
+ * ----+-----------------+-----------+-----A---------
+ *                                        skb->data
+ *   skb->protocol = ntohs(ETH_P_IP)
+ *   skb->vlan_proto = 0
+ *   skb->vlan_tci = 0
+ *   skb->vlan_present = 0
+ *   l2_info->vlan_hdr_cnt = 1
+ *   l2_info->vlan_hdr[0].tpid = ntohs(ETH_P_8021Q)
+ *   l2_info->vlan_hdr[0].tci = 0x0001
+ *   l2_info->protocol = ETH_P_IP
+ *
+ * case 3: untagged frame
+ * When entering this function:
+ * ----+-----------------+-----|---------------------
+ *     |DMAC    |SMAC    |08|00|45|00|
+ * ----+-----------------+-----A---------------------
+ *                            skb->data
+ *   skb->protocol = ntohs(ETH_P_IP)
+ *   skb->vlan_proto = 0
+ *   skb->vlan_tci = 0
+ *   skb->vlan_present = 0
+ * When exiting:
+ * ----+-----------------+-----|---------------------
+ *     |DMAC    |SMAC    |08|00|45|00|
+ * ----+-----------------+-----A---------------------
+ *                            skb->data
+ *   skb->protocol = ntohs(ETH_P_IP)
+ *   skb->vlan_proto = 0
+ *   skb->vlan_tci = 0
+ *   skb->vlan_present = 0
+ *   l2_info->vlan_hdr_cnt = 0
+ *   l2_info->protocol = ETH_P_IP
+ */
+static inline bool sfe_vlan_check_and_parse_tag(struct sk_buff *skb, struct sfe_l2_info *l2_info)
+{
+	struct vlan_hdr *vhdr;
+
+	l2_info->vlan_hdr_cnt = 0;
+
+	while ((skb->protocol == htons(ETH_P_8021AD) || skb->protocol == htons(ETH_P_8021Q)) &&
+			l2_info->vlan_hdr_cnt < SFE_MAX_VLAN_DEPTH) {
+		if (unlikely(!pskb_may_pull(skb, VLAN_HLEN))) {
+			return false;
+		}
+		vhdr = (struct vlan_hdr *)skb->data;
+		l2_info->vlan_hdr[l2_info->vlan_hdr_cnt].tpid = skb->protocol;
+		l2_info->vlan_hdr[l2_info->vlan_hdr_cnt].tci = ntohs(vhdr->h_vlan_TCI);
+		skb->protocol = vhdr->h_vlan_encapsulated_proto;
+		l2_info->vlan_hdr_cnt++;
+		__skb_pull(skb, VLAN_HLEN);
+	}
+
+	l2_info->protocol = htons(skb->protocol);
+	return true;
+}
+
+/*
+ * sfe_vlan_undo_parse()
+ *      Restore some skb fields which are modified when parsing VLAN tags.
+ */
+static inline void sfe_vlan_undo_parse(struct sk_buff *skb, struct sfe_l2_info *l2_info)
+{
+	if (l2_info->vlan_hdr_cnt == 0) {
+		return;
+	}
+
+	skb->protocol = l2_info->vlan_hdr[0].tpid;
+	__skb_push(skb, l2_info->vlan_hdr_cnt * VLAN_HLEN);
+}
+
+/*
+ * sfe_vlan_validate_ingress_tag()
+ *      Validate ingress packet's VLAN tag
+ */
+static inline bool sfe_vlan_validate_ingress_tag(
+		struct sk_buff *skb, u8 count, struct sfe_vlan_hdr *vlan_hdr, struct sfe_l2_info *l2_info)
+{
+	u8 i;
+
+	if (likely(!sfe_is_l2_feature_enabled())) {
+		return true;
+	}
+
+	if (unlikely(count != l2_info->vlan_hdr_cnt)) {
+		return false;
+	}
+
+	for (i = 0; i < count; i++) {
+		if (unlikely(vlan_hdr[i].tpid != l2_info->vlan_hdr[i].tpid)) {
+			return false;
+		}
+
+		if (unlikely((vlan_hdr[i].tci & VLAN_VID_MASK) !=
+			     (l2_info->vlan_hdr[i].tci & VLAN_VID_MASK))) {
+			return false;
+		}
+	}
+
+	return true;
+}
+
+/*
+ * sfe_vlan_add_tag()
+ *      Add VLAN tags at skb->data.
+ *      Normally, it is called just before adding 14-byte Ethernet header.
+ *
+ *      This function does not update skb->mac_header so later code
+ *      needs to call skb_reset_mac_header()/skb_reset_mac_len() to
+ *      get correct skb->mac_header/skb->mac_len.
+ *
+ *      It assumes:
+ *      - skb->protocol is set
+ *      - skb has enough headroom to write VLAN tags
+ *      - 0 < count <= SFE_MAX_VLAN_DEPTH
+ *
+ * When entering (e.g. skb->protocol = ntohs(ETH_P_IP) or ntohs(ETH_P_PPP_SES)):
+ *  -------------------------------+---------------------
+ *                                 |45|00|...
+ *  -------------------------------A---------------------
+ *                                skb->data
+ *  -------------------------------v-----------------+-----+----------
+ *                                 |11|00|xx|xx|xx|xx|00|21|45|00|...
+ *  -------------------------------+-----------------+-----+----------
+ *
+ * When exiting (e.g. to add outer/inner tag = 88a80032/81000001):
+ *  -------------+-----------+-----+---------------------
+ *         |00|32|81|00|00|01|08|00|45|00|05|d8|....
+ *  -------A-----+-----------+-----+---------------------
+ *        skb->data
+ *  -------v-----+-----------+-----+-----------------+-----+----------
+ *         |00|32|81|00|00|01|88|64|11|00|xx|xx|xx|xx|00|21|45|00|
+ *  -------------+-----------+-----+-----------------+-----+----------
+ *  skb->protocol = ntohs(ETH_P_8021AD)
+ */
+static inline void sfe_vlan_add_tag(struct sk_buff *skb, int count, struct sfe_vlan_hdr *vlan)
+{
+	struct vlan_hdr *vhdr;
+	int i;
+	vlan += (count - 1);
+
+	for (i = 0; i < count; i++) {
+		skb_push(skb, VLAN_HLEN);
+		vhdr = (struct vlan_hdr *)skb->data;
+		vhdr->h_vlan_TCI = htons(vlan->tci);
+		vhdr->h_vlan_encapsulated_proto = skb->protocol;
+		skb->protocol = vlan->tpid;
+		vlan--;
+	}
+}
+
+#endif /* __SFE_VLAN_H */
diff --git a/qca-ovsmgr/.gitignore b/qca-ovsmgr/.gitignore
new file mode 100644
index 0000000..cb831ad
--- /dev/null
+++ b/qca-ovsmgr/.gitignore
@@ -0,0 +1,14 @@
+
+# Ignore general build intermediate files
+*.o
+*.cmd
+*.ko
+*.mod.*
+*.mod
+Module.symvers
+modules.order
+/.tmp_versions/
+built-in.a
+
+# don't ignore .gitignore itself
+!.gitignore
diff --git a/qca-ovsmgr/Makefile b/qca-ovsmgr/Makefile
new file mode 100644
index 0000000..c99850b
--- /dev/null
+++ b/qca-ovsmgr/Makefile
@@ -0,0 +1,14 @@
+# Makefile for the OVS manager
+
+ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64 ipq60xx ipq60xx_64))
+ccflags-y += -DOVSMGR_PPE_SUPPORT
+endif
+
+ccflags-y := -I$(obj) -I$(obj)/..
+ccflags-y += -DOVSMGR_DEBUG_LEVEL=0
+ccflags-y += -Werror -Wall
+
+obj-m += qca-ovsmgr.o
+qca-ovsmgr-objs := ovsmgr.o ovsmgr_dp.o ovsmgr_debugfs.o
+
+obj ?= .
diff --git a/qca-ovsmgr/build.sh b/qca-ovsmgr/build.sh
new file mode 100755
index 0000000..84df137
--- /dev/null
+++ b/qca-ovsmgr/build.sh
@@ -0,0 +1,97 @@
+#!/bin/bash
+
+set -e
+set -o errtrace
+trap 'echo Fatal error: script $0 aborting at line $LINENO, command \"$BASH_COMMAND\" returned $?; exit 1' ERR
+
+PRODUCT_LIST="sirocco"
+
+NUM_JOBS=$(grep -c processor /proc/cpuinfo)
+
+MODULE_NAME="qca-ovsmgr"
+###################################################
+# Setup build toollchain
+###################################################
+sdk_top_dir=$(readlink -e $(dirname $0)/..)
+TOP_DIR=$(readlink -e ${sdk_top_dir}/..)
+
+#export ARCH and build related envs.
+source ${TOP_DIR}/sdk/build_scripts/setup_env.sh
+
+kernel_path=$(readlink -e ${sdk_top_dir}/../kernel)
+soc_type=ipq50xx
+extra_cflags="-I${sdk_top_dir}/${MODULE_NAME}/exports -I${kernel_path}/net/openvswitch"
+
+##################################################
+# Build Kernel Module
+##################################################
+function BuildKModule() {
+    # make kernel module
+    echo "Build ${MODULE_NAME}"
+    ${CROSS_MAKE} -C ${kernel_path} M=${sdk_top_dir}/${MODULE_NAME} SoC=${soc_type} EXTRA_CFLAGS="${extra_cflags}" V=1
+}
+
+##################################################
+# Build & Install
+##################################################
+function BuildAndInstall() {
+    local product=$1
+    local eureka_src_path=$(readlink -e $2)
+    if [ -z ${eureka_src_path} ]; then
+      echo "eureka_src_path doesn't exist"
+      exit 1
+    fi
+
+    # clean previous build
+    find . -name "*.o" -delete
+    find . -name "*.cmd" -delete
+    find . -name "*.ko" -delete
+    find . -name "*.mod.*" -delete
+    find . -name "*.mod" -delete
+    find . -name Module.symvers -delete
+
+    # build module
+    BuildKModule
+
+    # install module
+    echo "Install ${MODULE_NAME}.ko"
+    local module_target_dir="$(GetModulePath ${eureka_src_path} ${product})"
+    mkdir -p ${module_target_dir}
+    cp -f ${MODULE_NAME}.ko ${module_target_dir}/.
+}
+
+function Usage() {
+    cat << EOF
+Usage:
+    $0 <product> <eureka_src_path>
+    Valid products: ${PRODUCT_LIST}
+EOF
+}
+
+function IsProductValid() {
+  local product
+  local ret=1
+
+  for product in ${PRODUCT_LIST}; do
+    if [ "${product}" == "$1" ]; then
+      ret=0
+      break
+    fi
+  done
+
+  return ${ret}
+}
+
+#########################
+####### Main Entry ######
+#########################
+if (( $# < 2 )); then
+  Usage
+else
+  if IsProductValid $1; then
+    BuildAndInstall $1 $2
+  else
+    echo "$1 is a invalid product"
+    Usage
+  fi
+fi
diff --git a/qca-ovsmgr/exports/ovsmgr.h b/qca-ovsmgr/exports/ovsmgr.h
new file mode 100644
index 0000000..d859bf5
--- /dev/null
+++ b/qca-ovsmgr/exports/ovsmgr.h
@@ -0,0 +1,198 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * ovsmgr.h
+ */
+#ifndef __OVSMGR__H
+#define __OVSMGR__H
+
+#include <linux/if_vlan.h>
+
+/*
+ * Notifiers
+ */
+#define OVSMGR_DP_ADD 1
+#define OVSMGR_DP_DEL 2
+#define OVSMGR_DP_BR_ADD 3
+#define OVSMGR_DP_BR_DEL 4
+#define OVSMGR_DP_PORT_ADD 5
+#define OVSMGR_DP_PORT_DEL 6
+#define OVSMGR_DP_FLOW_ADD 7
+#define OVSMGR_DP_FLOW_DEL 8
+#define OVSMGR_DP_FLOW_CHANGE 9
+#define OVSMGR_DP_FLOW_TBL_FLUSH 10
+#define OVSMGR_DP_VLAN_ADD 11
+#define OVSMGR_DP_VLAN_DEL 12
+
+/*
+ * Hook numbers
+ */
+#define OVSMGR_DP_HOOK_PRE_FLOW_PROC  1	/* Call hook function before flow search */
+#define OVSMGR_DP_HOOK_POST_FLOW_PROC 2	/* Call hook function after flow is found */
+
+/*
+ * Signature to validate if skb->cb is populated by OVS manager
+ */
+#define OVSMGR_SKB_SIGNATURE 0xAEAD1246
+
+#define OVSMGR_INVALID_DSCP 0xFFFFFFFF
+
+enum ovsmgr_flow_status {
+	OVSMGR_FLOW_STATUS_ALLOW_ACCEL,		/* Allow the acceleration of the flow, no VLAN operation */
+	OVSMGR_FLOW_STATUS_DENY_ACCEL,		/* Deny the acceleration of the flow */
+	OVSMGR_FLOW_STATUS_DENY_ACCEL_EGRESS,	/* outdev in flow is not allowed for acceleration */
+	OVSMGR_FLOW_STATUS_ALLOW_VLAN_ACCEL,	/* Allow the acceleration of the flow, single VLAN operation */
+	OVSMGR_FLOW_STATUS_ALLOW_VLAN_QINQ_ACCEL,
+						/* Allow the acceleration of the flow, QinQ VLAN operation */
+	OVSMGR_FLOW_STATUS_UNKNOWN		/* Flow status is unknown */
+};
+
+/*
+ * ovsmgr_skb_cb
+ *	skb->cb details updated by OVS manager before forwarding the packet post
+ *	flow hook.
+ */
+struct ovsmgr_skb_cb {
+	uint32_t ovs_sig;
+	void *flow;
+};
+
+#define OVSMGR_OVS_CB(skb) ((struct ovsmgr_skb_cb *)(skb)->cb)
+
+/*
+ * Hook function type
+ */
+typedef unsigned int (*ovsmgr_dp_hookfn_t)(struct sk_buff *skb, struct net_device *out);
+
+/*
+ * ovsmgr_dp_hook_ops
+ *	Datapath hook options
+ */
+struct ovsmgr_dp_hook_ops {
+	struct list_head list;
+	int protocol;			/* IP protocol interested in */
+	int hook_num;			/* Hook number */
+	ovsmgr_dp_hookfn_t hook;	/* Hook function to be called */
+};
+
+/*
+ * ovsmgr_dp_tuple
+ *	Datapath flow tuple
+ */
+struct ovsmgr_dp_tuple {
+	union {
+		struct {
+			__be32 src;
+			__be32 dst;
+		} ipv4;
+
+		struct {
+			struct in6_addr src;
+			struct in6_addr dst;
+		} ipv6;
+	};
+	uint16_t src_port;	/* Source port */
+	uint16_t dst_port;	/* Destination port */
+	uint8_t ip_version;	/* IP version */
+	uint8_t protocol;	/* IP protocol */
+};
+
+/*
+ * ovsmgr_dp_flow
+ *	Datapath flow details
+ */
+struct ovsmgr_dp_flow {
+	struct net_device *indev;		/* Ingress interface */
+	struct net_device *outdev;		/* Egress interface */
+	uint8_t smac[ETH_ALEN];			/* Source MAC */
+	uint8_t dmac[ETH_ALEN];			/* Destination MAC */
+	struct vlan_hdr ingress_vlan;		/* Ingress VLAN header */
+	struct ovsmgr_dp_tuple tuple;		/* Flow tuple */
+	bool is_routed;				/* Routed flag, set when flow is routed */
+};
+
+/*
+ * ovsmgr_dp_flow_stats
+ *	Datapath flow statistics
+ */
+struct ovsmgr_dp_flow_stats {
+	uint32_t pkts;	/* Number of received packets matching the flow */
+	uint32_t bytes;	/* Number of received bytes matching the flow */
+};
+
+/*
+ * ovsmgr_flow_info
+ *	OVS Flow information for the given key.
+ *	ingress[0]/egress[0] represents inner VLAN header details
+ *	ingress[1]/egress[1] represents outer VLAN header details
+ *	0 value represents no vlan operations required
+ *	dscp contains DSCP to be marked for given flow key.
+ */
+struct ovsmgr_flow_info {
+	uint32_t dscp;			/* DSCP mark */
+	struct vlan_hdr ingress[2];	/* Ingress VLAN details */
+	struct vlan_hdr egress[2];	/* Egress VLAN details */
+};
+
+/*
+ * ovsmgr_dp_port_info
+ *	Port notification structure
+ */
+struct ovsmgr_dp_port_info {
+	struct net_device *master;	/* OVS bridge interface */
+	struct net_device *dev;		/* OVS bridge port interface */
+};
+
+/*
+ * ovsmgr_dp_port_vlan_info
+ *	Port VLAN notification structure
+ */
+struct ovsmgr_dp_port_vlan_info {
+	struct vlan_hdr vh;
+	struct net_device *master;
+	struct net_device *dev;
+};
+
+/*
+ * ovsmgr_notifiers_info
+ *	Notifiers structure
+ */
+struct ovsmgr_notifiers_info {
+	union {
+		struct net_device *dev;			/* Netdev for bridge add/del notification */
+		struct ovsmgr_dp_port_info *port;	/* Port details for port add/del notification */
+		struct ovsmgr_dp_port_vlan_info *vlan;	/* Port VLAN details for VLAN add/del notification */
+		struct ovsmgr_dp_flow *flow;		/* Flow details for datapath flow add/del notification */
+	};
+};
+
+void ovsmgr_notifier_register(struct notifier_block *nb);
+void ovsmgr_notifier_unregister(struct notifier_block *nb);
+int ovsmgr_dp_hook_register(struct ovsmgr_dp_hook_ops *ops);
+void ovsmgr_dp_hook_unregister(struct ovsmgr_dp_hook_ops *ops);
+void ovsmgr_bridge_interface_stats_update(struct net_device *dev,
+					  uint32_t rx_packets, uint32_t rx_bytes,
+					  uint32_t tx_packets, uint32_t tx_bytes);
+void ovsmgr_flow_stats_update(struct ovsmgr_dp_flow *flow, struct ovsmgr_dp_flow_stats *stats);
+struct net_device *ovsmgr_port_find(struct sk_buff *skb, struct net_device *dev, struct ovsmgr_dp_flow *flow);
+struct net_device *ovsmgr_port_find_by_mac(struct sk_buff *skb, struct net_device *dev, struct ovsmgr_dp_flow *flow);
+enum ovsmgr_flow_status ovsmgr_flow_info_get(struct ovsmgr_dp_flow *flow,
+					      struct sk_buff *skb, struct ovsmgr_flow_info *ofi);
+struct net_device *ovsmgr_dev_get_master(struct net_device *dev);
+bool ovsmgr_is_ovs_master(struct net_device *dev);
+
+#endif /* __OVSMGR__H */
diff --git a/qca-ovsmgr/ovsmgr.c b/qca-ovsmgr/ovsmgr.c
new file mode 100644
index 0000000..e315210
--- /dev/null
+++ b/qca-ovsmgr/ovsmgr.c
@@ -0,0 +1,235 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * ovsmgr.c
+ */
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/notifier.h>
+
+/*
+ * OpenVSwitch header files
+ */
+#include <datapath.h>
+
+#include "ovsmgr.h"
+#include "ovsmgr_priv.h"
+#include "ovsmgr_debugfs.h"
+
+/*
+ * Registration/Unregistration methods for OVS datapath event notifications.
+ */
+static RAW_NOTIFIER_HEAD(dp_notifier_chain);
+struct ovsmgr_ctx ovsmgr_ctx;
+
+/*
+ * ovsmgr_notifiers_call()
+ *	Call registered notifiers.
+ */
+int ovsmgr_notifiers_call(struct ovsmgr_notifiers_info *info, unsigned long val)
+{
+	return raw_notifier_call_chain(&dp_notifier_chain, val, info);
+}
+
+/*
+ * ovsmgr_notifier_register()
+ *	Register OVS data path notifiers.
+ */
+void ovsmgr_notifier_register(struct notifier_block *nb)
+{
+	raw_notifier_chain_register(&dp_notifier_chain, nb);
+}
+EXPORT_SYMBOL(ovsmgr_notifier_register);
+
+/*
+ * ovsmgr_notifier_unregister()
+ *	Unregister OVS data path notifiers.
+ */
+void ovsmgr_notifier_unregister(struct notifier_block *nb)
+{
+	raw_notifier_chain_unregister(&dp_notifier_chain, nb);
+}
+EXPORT_SYMBOL(ovsmgr_notifier_unregister);
+
+/*
+ * ovsmgr_dp_hook_register()
+ *	Register OVS data path hook for processing packets.
+ */
+int ovsmgr_dp_hook_register(struct ovsmgr_dp_hook_ops *ops)
+{
+	switch (ops->hook_num) {
+	case OVSMGR_DP_HOOK_PRE_FLOW_PROC:
+		/*
+		 * Allow only IGMP/ICMPV6 (MLD) packets in pre hook.
+		 */
+		if ((ops->protocol != IPPROTO_IGMP) && (ops->protocol != IPPROTO_ICMPV6)) {
+			ovsmgr_warn("%px: Only IGMP/ICMPv6 packets will be forwarded in pre-flow hook\n", ops);
+			return -EINVAL;
+		}
+	case OVSMGR_DP_HOOK_POST_FLOW_PROC:
+		break;
+	default:
+		ovsmgr_warn("%px: Invalid hook number\n", ops);
+		return -EINVAL;
+	}
+
+	write_lock_bh(&ovsmgr_ctx.lock);
+	list_add(&ops->list, &ovsmgr_ctx.dp_hooks);
+	write_unlock_bh(&ovsmgr_ctx.lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(ovsmgr_dp_hook_register);
+
+/*
+ * ovsmgr_dp_hook_unregister()
+ *	Unregister OVS data path hook for processing packets.
+ */
+void ovsmgr_dp_hook_unregister(struct ovsmgr_dp_hook_ops *ops)
+{
+	struct ovsmgr_dp_hook_ops *h;
+
+	write_lock_bh(&ovsmgr_ctx.lock);
+	list_for_each_entry(h, &ovsmgr_ctx.dp_hooks, list) {
+		if ((h->protocol == ops->protocol) &&
+			(h->hook_num == ops->hook_num) &&
+			(h->hook == ops->hook)) {
+			list_del(&h->list);
+			break;
+		}
+	}
+	write_unlock_bh(&ovsmgr_ctx.lock);
+}
+EXPORT_SYMBOL(ovsmgr_dp_hook_unregister);
+
+/*
+ * ovsmgr_bridge_interface_stats_update()
+ *	Update OVS bridge interface statistics.
+ */
+void ovsmgr_bridge_interface_stats_update(struct net_device *dev,
+					  uint32_t rx_packets, uint32_t rx_bytes,
+					  uint32_t tx_packets, uint32_t tx_bytes)
+{
+	ovsmgr_dp_bridge_interface_stats_update(dev,
+						rx_packets, rx_bytes,
+						tx_packets, tx_bytes);
+}
+EXPORT_SYMBOL(ovsmgr_bridge_interface_stats_update);
+
+/*
+ * ovsmgr_flow_stats_update()
+ *	Update datapath flow statistics
+ */
+void ovsmgr_flow_stats_update(struct ovsmgr_dp_flow *flow, struct ovsmgr_dp_flow_stats *stats)
+{
+	ovsmgr_dp_flow_stats_update(flow, stats);
+}
+EXPORT_SYMBOL(ovsmgr_flow_stats_update);
+
+/*
+ * ovsmgr_dev_get_master()
+ *	Find datapath bridge interface for given bridge port
+ */
+struct net_device *ovsmgr_dev_get_master(struct net_device *dev)
+{
+	return ovsmgr_dp_dev_get_master(dev);
+}
+EXPORT_SYMBOL(ovsmgr_dev_get_master);
+
+/*
+ * ovsmgr_is_ovs_master()
+ *	Return true if dev is OVS bridge interface
+ */
+bool ovsmgr_is_ovs_master(struct net_device *dev)
+{
+	return ovsmgr_dp_dev_is_master(dev);
+}
+EXPORT_SYMBOL(ovsmgr_is_ovs_master);
+
+/*
+ * ovsmgr_port_find()
+ *	Find datapath egress port for the given skb, bridge dev and flow
+ */
+struct net_device *ovsmgr_port_find(struct sk_buff *skb, struct net_device *dev, struct ovsmgr_dp_flow *flow)
+{
+	return ovsmgr_dp_port_dev_find(skb, dev, flow);
+}
+EXPORT_SYMBOL(ovsmgr_port_find);
+
+/*
+ * ovsmgr_port_find_by_mac()
+ *	Find datapath egress port using MAC address
+ */
+struct net_device *ovsmgr_port_find_by_mac(struct sk_buff *skb, struct net_device *dev, struct ovsmgr_dp_flow *flow)
+{
+	return ovsmgr_dp_port_dev_find_by_mac(skb, dev, flow);
+}
+EXPORT_SYMBOL(ovsmgr_port_find_by_mac);
+
+/*
+ * ovsmgr_flow_info_get()
+ *	Find datapath flow details using flow and skb
+ */
+enum ovsmgr_flow_status ovsmgr_flow_info_get(struct ovsmgr_dp_flow *flow,
+					      struct sk_buff *skb, struct ovsmgr_flow_info *ofi)
+{
+	return ovsmgr_dp_flow_info_get(flow, skb, ofi);
+}
+EXPORT_SYMBOL(ovsmgr_flow_info_get);
+
+/*
+ * ovsmgr_init()
+ *	Initialize OVS Manager
+ */
+int __init ovsmgr_init(void)
+{
+	rwlock_init(&ovsmgr_ctx.lock);
+	INIT_LIST_HEAD(&ovsmgr_ctx.dp_list);
+	INIT_LIST_HEAD(&ovsmgr_ctx.dp_hooks);
+
+	if (ovsmgr_dp_init()) {
+		ovsmgr_warn("Failed to initialize datapath\n");
+		return -1;
+	}
+
+	if (ovsmgr_debugfs_init()) {
+		ovsmgr_warn("Failed to initialize debugfs\n");
+		ovsmgr_dp_exit();
+		return -1;
+	}
+
+	ovsmgr_info("OVS Init successful\n");
+	return 0;
+}
+
+/*
+ * ovsmgr_exit()
+ *	Cleanup OVS Manager and exit
+ */
+void __exit ovsmgr_exit(void)
+{
+	ovsmgr_debugfs_cleanup();
+	ovsmgr_dp_exit();
+	ovsmgr_info("OVS Manager Removed\n");
+}
+
+module_init(ovsmgr_init);
+module_exit(ovsmgr_exit);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("OVS Manager");
diff --git a/qca-ovsmgr/ovsmgr_debugfs.c b/qca-ovsmgr/ovsmgr_debugfs.c
new file mode 100644
index 0000000..8d55f42
--- /dev/null
+++ b/qca-ovsmgr/ovsmgr_debugfs.c
@@ -0,0 +1,134 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * ovsmgr_debugfs.c
+ *	Debugfs implementation for OVS datapath.
+ */
+#include <linux/debugfs.h>
+#include <linux/list.h>
+#include <linux/proc_fs.h>
+#include <asm/atomic.h>
+#include <datapath.h>
+
+#include "ovsmgr.h"
+#include "ovsmgr_priv.h"
+
+static char *port_type[__OVS_VPORT_TYPE_MAX] = {
+	"Unspecified Vport type",
+	"Network device",
+	"Internal device",
+	"GRE device",
+	"VxLAN device",
+	"Geneve device",
+};
+
+/*
+ * ovsmgr_debugfs_dp_info_show()
+ */
+static void ovsmgr_debugfs_dp_info_show(struct ovsmgr_dp *nod, struct seq_file *m)
+{
+	struct ovsmgr_dp_port *nodp;
+
+	seq_printf(m, "Datapath Dev : %s \n", nod->dev->name);
+	seq_printf(m, "datapath instance : %px\n", nod->dp);
+	seq_printf(m, "Statistics:\n");
+
+	list_for_each_entry(nodp, &nod->port_list, node) {
+		seq_printf(m, "Port :\n");
+		seq_printf(m, "\tdevice: %s\n", nodp->dev->name);
+		seq_printf(m, "\tMaster device: %s\n", nodp->master_dev->name);
+		seq_printf(m, "\tinstance : %px\n", nodp->vport);
+		seq_printf(m, "\tport number : %d\n", nodp->vport_num);
+		seq_printf(m, "\tport type : %s\n", port_type[nodp->vport_type]);
+	}
+}
+
+/*
+ * ovsmgr_debugfs_dp_show()
+ */
+static int ovsmgr_debugfs_dp_show(struct seq_file *m, void *p)
+{
+	struct ovsmgr_dp *nod;
+
+	read_lock_bh(&ovsmgr_ctx.lock);
+
+	seq_printf(m, "\tPackets received from DP: %llu\n", (u64)atomic64_read(&ovsmgr_ctx.stats.pkts_from_ovs_dp));
+	seq_printf(m, "\tPacket forwarded to pre flow hooks : %llu\n", (u64)atomic64_read(&ovsmgr_ctx.stats.pkts_fwd_pre_flow));
+	seq_printf(m, "\tPacket forwarded to post flow hooks : %llu\n", (u64)atomic64_read(&ovsmgr_ctx.stats.pkts_fwd_post_flow));
+
+	list_for_each_entry(nod, &ovsmgr_ctx.dp_list, node) {
+		ovsmgr_debugfs_dp_info_show(nod, m);
+	}
+
+	read_unlock_bh(&ovsmgr_ctx.lock);
+	return 0;
+}
+
+/*
+ * ovsmgr_debugfs_dp_open()
+ */
+static int ovsmgr_debugfs_dp_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, ovsmgr_debugfs_dp_show, inode->i_private);
+}
+
+/*
+ * Datapath file operation structure instance
+ */
+static const struct file_operations dp_op = {
+	.open = ovsmgr_debugfs_dp_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = seq_release
+};
+
+/*
+ * ovsmgr_debugfs_cleanup()
+ *	Cleanup the debugfs tree.
+ */
+void ovsmgr_debugfs_cleanup(void)
+{
+	debugfs_remove_recursive(ovsmgr_ctx.dentry);
+}
+
+/*
+ * ovsmgr_debugfs_init()
+ *	Initialize the debugfs tree.
+ */
+int ovsmgr_debugfs_init(void)
+{
+	/*
+	 * initialize debugfs.
+	 */
+	ovsmgr_ctx.dentry = debugfs_create_dir("qca-ovsmgr", NULL);
+	if (!ovsmgr_ctx.dentry) {
+		ovsmgr_warn("Creating debug directory failed\n");
+		return -1;
+	}
+
+	/*
+	 * Create debugfs entries for datapath
+	 */
+	ovsmgr_ctx.dentry_file = debugfs_create_file("ovsdp", S_IRUGO, ovsmgr_ctx.dentry, NULL, &dp_op);
+	if (!ovsmgr_ctx.dentry_file) {
+		ovsmgr_warn("Debugfs file creation failed\n");
+		debugfs_remove_recursive(ovsmgr_ctx.dentry);
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/qca-ovsmgr/ovsmgr_debugfs.h b/qca-ovsmgr/ovsmgr_debugfs.h
new file mode 100644
index 0000000..f3ec61e
--- /dev/null
+++ b/qca-ovsmgr/ovsmgr_debugfs.h
@@ -0,0 +1,25 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * ovsmgr_debugfs.h
+ */
+#ifndef __OVSMGR_DEBUGFS__H
+#define __OVSMGR_DEBUGFS__H
+
+int ovsmgr_debugfs_init(void);
+void ovsmgr_debugfs_cleanup(void);
+#endif /* __OVSMGR_DEBUGFS__H */
diff --git a/qca-ovsmgr/ovsmgr_dp.c b/qca-ovsmgr/ovsmgr_dp.c
new file mode 100644
index 0000000..4003eec
--- /dev/null
+++ b/qca-ovsmgr/ovsmgr_dp.c
@@ -0,0 +1,2113 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * ovsmgr_dp.c
+ */
+
+#include <asm/atomic.h>
+#include <linux/etherdevice.h>
+
+/*
+ * OpenVSwitch header files
+ */
+#include <datapath.h>
+#include "ovsmgr.h"
+#include "ovsmgr_priv.h"
+
+/*
+ * ovsmgr_dp_find()
+ *	Find datapath instance.
+ *
+ * This function should be called under read_lock.
+ */
+static struct ovsmgr_dp *ovsmgr_dp_find(void *dp)
+{
+	struct ovsmgr_dp *nod;
+
+	list_for_each_entry(nod, &ovsmgr_ctx.dp_list, node) {
+		if (nod->dp == dp) {
+			return nod;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * ovsmgr_dp_port_find_by_dev()
+ *	Find datapath instance using dev.
+ *
+ * This function should be called under read_lock
+ */
+static struct ovsmgr_dp_port *ovsmgr_dp_port_find_by_dev(struct ovsmgr_dp *nod, struct net_device *dev)
+{
+	struct ovsmgr_dp_port *nodp;
+
+	list_for_each_entry(nodp, &nod->port_list, node) {
+		if (nodp->dev == dev) {
+			return nodp;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * ovsmgr_dp_port_find_by_num()
+ *	Find datapath port instance using port number and datapath instance.
+ *
+ * This function should be called under read_lock
+ */
+static struct ovsmgr_dp_port *ovsmgr_dp_port_find_by_num(struct ovsmgr_dp *nod, int vport_num)
+{
+	struct ovsmgr_dp_port *nodp;
+
+	list_for_each_entry(nodp, &nod->port_list, node) {
+		if (nodp->vport_num == vport_num) {
+			return nodp;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * ovsmgr_dp_find_by_port()
+ *	Find datapath instance using port number.
+ *
+ * This function should be called under read_lock
+ */
+static struct ovsmgr_dp *ovsmgr_dp_find_by_port(int vport_num)
+{
+	struct ovsmgr_dp_port *nodp;
+	struct ovsmgr_dp *nod;
+
+	list_for_each_entry(nod, &ovsmgr_ctx.dp_list, node) {
+		nodp = ovsmgr_dp_port_find_by_num(nod, vport_num);
+		if (nodp) {
+			return nod;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * ovsmgr_dp_find_by_dev()
+ *	Find datapath instance using dev.
+ *
+ * This function should be called under read_lock
+ */
+static struct ovsmgr_dp *ovsmgr_dp_find_by_dev(struct net_device *dev)
+{
+	struct ovsmgr_dp_port *nodp;
+	struct ovsmgr_dp *nod;
+
+	list_for_each_entry(nod, &ovsmgr_ctx.dp_list, node) {
+		nodp = ovsmgr_dp_port_find_by_dev(nod, dev);
+		if (nodp) {
+			return nod;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * ovsmgr_dp_send_ports_add_notifier
+ *	Notify port add event
+ *
+ * Send port add notifiers Return the first output interface in the actions.
+ */
+static void ovsmgr_dp_send_ports_add_notifier(struct ovsmgr_dp *nod, struct net_device *master_dev)
+{
+	struct ovsmgr_dp_port *nodp;
+	struct ovsmgr_dp_port_info port;
+	struct ovsmgr_notifiers_info info;
+
+	list_for_each_entry(nodp, &nod->port_list, node) {
+		if (!strncmp(nodp->master_name, master_dev->name, IFNAMSIZ) &&
+			    !nodp->add_notified) {
+			nodp->add_notified = true;
+			nodp->master_dev = master_dev;
+			port.master = master_dev;
+			port.dev = nodp->dev;
+			info.port = &port;
+			ovsmgr_notifiers_call(&info, OVSMGR_DP_PORT_ADD);
+		}
+	}
+}
+
+/*
+ * ovsmgr_dp_flow_key_dump()
+ *	Dump flow key
+ */
+static void ovsmgr_dp_flow_key_dump(struct sw_flow_key *key)
+{
+	int i;
+
+	ovsmgr_trace("Phy:\n");
+	ovsmgr_trace("\tpriority = %u\n", key->phy.priority);
+	ovsmgr_trace("\tskb_mark = %u\n", key->phy.skb_mark);
+	ovsmgr_trace("\tin_port = %u\n", key->phy.in_port);
+
+	ovsmgr_trace("Flow Hash = %u\n", key->ovs_flow_hash);
+	ovsmgr_trace("Recirc_id = %u\n", key->recirc_id);
+	ovsmgr_trace("Eth:\n");
+	ovsmgr_trace("\tsmac = %pM\n", &key->eth.src);
+	ovsmgr_trace("\tdmac = %pM\n", &key->eth.dst);
+	ovsmgr_trace("\ttype = %x\n", key->eth.type);
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
+	ovsmgr_trace("\tcvlan tci = %x\n", OVSMGR_KEY_CVLAN_TCI(key));
+#endif
+	ovsmgr_trace("\tvlan tci = %x\n", OVSMGR_KEY_VLAN_TCI(key));
+
+	ovsmgr_trace("IP:\n");
+	ovsmgr_trace("\tproto = %d\n", key->ip.proto);
+	ovsmgr_trace("\ttos = %d\n", key->ip.tos);
+	ovsmgr_trace("\tttl = %d\n", key->ip.ttl);
+
+	ovsmgr_trace("\tfrag = %d\n", key->ip.frag);
+
+	ovsmgr_trace("TCP/UDP:\n");
+	ovsmgr_trace("\tsrc = %x\n", key->tp.src);
+	ovsmgr_trace("\tdst = %x\n", key->tp.dst);
+	ovsmgr_trace("\tflags = %x\n", key->tp.flags);
+
+	if (key->eth.type == htons(ETH_P_IP)) {
+		ovsmgr_trace("IPv4:\n");
+		ovsmgr_trace("\tsrc ip = %pI4\n", &key->ipv4.addr.src);
+		ovsmgr_trace("\tdst ip = %pI4\n", &key->ipv4.addr.dst);
+	} else if (key->eth.type == htons(ETH_P_IPV6)) {
+		ovsmgr_trace("IPv6:\n");
+		ovsmgr_trace("\tsrc ip = %pI6\n", &key->ipv6.addr.src);
+		ovsmgr_trace("\tdst ip = %pI6\n", &key->ipv6.addr.dst);
+	} else {
+		ovsmgr_trace("Eth type = %x\n", key->eth.type);
+	}
+
+	ovsmgr_trace("CT:\n");
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
+	ovsmgr_trace("\tzone = %x\n", key->ct.zone);
+	ovsmgr_trace("\tstate = %x\n", key->ct.state);
+#else
+	ovsmgr_trace("\tzone = %x\n", key->ct_zone);
+	ovsmgr_trace("\tstate = %x\n", key->ct_state);
+#endif
+
+	ovsmgr_trace("\tmark = %x\n", key->ct.mark);
+	ovsmgr_trace("\tlabel: ");
+	for (i = 0 ; i < OVS_CT_LABELS_LEN ; i++) {
+		ovsmgr_trace("%x ", key->ct.labels.ct_labels[i]);
+	}
+}
+
+/*
+ * ovsmgr_dp_flow_mask_dump()
+ *	Dump flow mask
+ */
+static void ovsmgr_dp_flow_mask_dump(struct sw_flow_mask *mask)
+{
+	ovsmgr_trace("ref_count = %d\n", mask->ref_count);
+	ovsmgr_trace("Range:\n");
+	ovsmgr_trace("\tstart = %d\n", mask->range.start);
+	ovsmgr_trace("\tend = %d\n", mask->range.end);
+}
+
+/*
+ * ovsmgr_dp_flow_actions_dump()
+ *	Dump flow actions
+ */
+static void ovsmgr_dp_flow_actions_dump(struct sw_flow_actions *acts)
+{
+	const struct nlattr *a;
+	int rem;
+
+	for (a = acts->actions, rem = acts->actions_len; rem > 0;
+	     a = nla_next(a, &rem)) {
+
+		switch (nla_type(a)) {
+		case OVS_ACTION_ATTR_OUTPUT:
+			ovsmgr_trace("OVS_ACTION_ATTR_OUTPUT: Port = %d\n", nla_get_u32(a));
+			break;
+
+		case OVS_ACTION_ATTR_USERSPACE:
+			ovsmgr_trace("OVS_ACTION_ATTR_USERSPACE\n");
+			break;
+
+		case OVS_ACTION_ATTR_HASH:
+			ovsmgr_trace("OVS_ACTION_ATTR_HASH\n");
+			break;
+
+		case OVS_ACTION_ATTR_PUSH_MPLS:
+			ovsmgr_trace("OVS_ACTION_ATTR_PUSH_MPLS\n");
+			break;
+
+		case OVS_ACTION_ATTR_POP_MPLS:
+			ovsmgr_trace("OVS_ACTION_ATTR_POP_MPLS\n");
+			break;
+
+		case OVS_ACTION_ATTR_PUSH_VLAN: {
+			const struct ovs_action_push_vlan *vlan;
+
+			ovsmgr_trace("OVS_ACTION_ATTR_PUSH_VLAN\n");
+			vlan = nla_data(a);
+			ovsmgr_trace("Vlan details:\n");
+			ovsmgr_trace("\tvlan_tpid = %x\n", vlan->vlan_tpid);
+			ovsmgr_trace("\tvlan_tci = %x\n", vlan->vlan_tci);
+			break;
+		}
+
+		case OVS_ACTION_ATTR_POP_VLAN:
+			ovsmgr_trace("OVS_ACTION_ATTR_POP_VLAN\n");
+			break;
+
+		case OVS_ACTION_ATTR_RECIRC:
+			ovsmgr_trace("OVS_ACTION_ATTR_RECIRC\n");
+			break;
+
+		case OVS_ACTION_ATTR_SET:
+			ovsmgr_trace("OVS_ACTION_ATTR_SET\n");
+			break;
+
+		case OVS_ACTION_ATTR_SET_MASKED:
+			ovsmgr_trace("OVS_ACTION_ATTR_SET_MASKED\n");
+			break;
+
+		case OVS_ACTION_ATTR_SET_TO_MASKED:
+			ovsmgr_trace("OVS_ACTION_ATTR_SET_TO_MASKED\n");
+			break;
+
+		case OVS_ACTION_ATTR_SAMPLE:
+			ovsmgr_trace("OVS_ACTION_ATTR_SAMPLE\n");
+			break;
+
+		case OVS_ACTION_ATTR_CT:
+			ovsmgr_trace("OVS_ACTION_ATTR_CT\n");
+			break;
+		default:
+			ovsmgr_trace("Unknown action: %d\n", nla_type(a));
+		}
+	}
+}
+
+/*
+ * ovsmgr_dp_flow_dump()
+ *	Dump flow details
+ */
+static void ovsmgr_dp_flow_dump(struct sw_flow *flow)
+{
+	struct sw_flow_actions *acts;
+
+	ovsmgr_trace("------- Flow Key --------\n");
+	ovsmgr_dp_flow_key_dump(&flow->key);
+
+	ovsmgr_trace("------- Flow Mask --------\n");
+	ovsmgr_dp_flow_mask_dump(flow->mask);
+
+	acts = rcu_dereference(flow->sf_acts);
+	ovsmgr_trace("------- Flow Actions ------\n");
+	ovsmgr_dp_flow_actions_dump(acts);
+}
+
+/*
+ * ovsmgr_dp_mcast_port_dev_find()
+ *	Find egress datapath port, given skb and datapath interface (dev)
+ */
+static struct net_device *ovsmgr_dp_mcast_port_dev_find(struct ovsmgr_dp *nod,
+							    struct ovsmgr_dp_port *master,
+							    struct ovsmgr_dp_flow *flow, struct sk_buff *skb)
+{
+	struct ovsmgr_dp_port *p;
+	struct sw_flow_key key;
+	struct net_device *dev;
+
+	/*
+	 * For multicast flow there is only one flow rule in datapath.  In case
+	 * of multicast routing flow there is no flow from OVS bridge interface
+	 * to bridge port.  The only way is to search for all the ports that are
+	 * part of bridge.
+	 *
+	 * Create a originate flow key
+	 */
+	memset(&key, 0, sizeof(key));
+	ether_addr_copy(key.eth.src, flow->smac);
+	ether_addr_copy(key.eth.dst, flow->dmac);
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0))
+	key.mac_proto = MAC_PROTO_ETHERNET;
+#endif
+
+	if (flow->tuple.ip_version == 4) {
+		key.ipv4.addr.src = flow->tuple.ipv4.src;
+		key.ipv4.addr.dst = flow->tuple.ipv4.dst;
+		key.eth.type = htons(ETH_P_IP);
+	} else {
+		memcpy(&key.ipv6.addr.src, &flow->tuple.ipv6.src, sizeof(key.ipv6.addr.src));
+		memcpy(&key.ipv6.addr.dst, &flow->tuple.ipv6.dst, sizeof(key.ipv6.addr.dst));
+		key.eth.type = htons(ETH_P_IPV6);
+	}
+
+	key.tp.src = flow->tuple.src_port;
+	key.tp.dst = flow->tuple.dst_port;
+	key.ip.proto = flow->tuple.protocol;
+
+	read_lock(&ovsmgr_ctx.lock);
+	list_for_each_entry(p, &nod->port_list, node) {
+		/*
+		 * Skip search if the port is not part of same bridge
+		 */
+		if (p->master_dev != master->dev) {
+			continue;
+		}
+
+		key.phy.in_port = p->vport_num;
+		dev = ovs_accel_egress_dev_find(nod->dp, &key, skb);
+		if (dev) {
+			read_unlock(&ovsmgr_ctx.lock);
+			ovsmgr_info("%px: Found the egress interface for this flow, returning ingress port: %s\n",
+					nod, p->dev->name);
+			return p->dev;
+		}
+	}
+
+	read_unlock(&ovsmgr_ctx.lock);
+	return NULL;
+}
+
+/*
+ * ovsmgr_dp_is_ipv6_mask_nonzero()
+ *	Return true if ip_addr is non-zero
+ */
+static inline bool ovsmgr_dp_is_ipv6_mask_nonzero(const uint32_t ip_addr[4])
+{
+	return !!(ip_addr[0] | ip_addr[1] | ip_addr[2] | ip_addr[3]);
+}
+
+/*
+ * ovsmgr_dp_ipv6_mask_addr()
+ *	Calculate masked IPv6 address and copy in new_addr
+ */
+static inline void ovsmgr_dp_ipv6_mask_addr(const __be32 old_addr[4], const __be32 v6_addr[4],
+			   const __be32 v6_mask[4], __be32 new_addr[4])
+{
+	new_addr[0] = OVS_MASKED(old_addr[0], v6_addr[0], v6_mask[0]);
+	new_addr[1] = OVS_MASKED(old_addr[1], v6_addr[1], v6_mask[1]);
+	new_addr[2] = OVS_MASKED(old_addr[2], v6_addr[2], v6_mask[2]);
+	new_addr[3] = OVS_MASKED(old_addr[3], v6_addr[3], v6_mask[3]);
+}
+
+/*
+ * ovsmgr_dp_eth_mask_addr()
+ *	Calculate masked MAC address and copy in new_mac
+ */
+static inline void ovsmgr_dp_eth_mask_addr(const u8 *old_mac, const u8 *mac, const u8 *mac_mask, u8 *new_mac)
+{
+	u16 *nmac = (u16 *)new_mac;
+	const u16 *omac = (const u16 *)old_mac;
+	const u16 *tmp_mac = (const u16 *)mac;
+	const u16 *tmp_mask = (const u16 *)mac_mask;
+
+	nmac[0] = OVS_MASKED(omac[0], tmp_mac[0], tmp_mask[0]);
+	nmac[1] = OVS_MASKED(omac[1], tmp_mac[1], tmp_mask[1]);
+	nmac[2] = OVS_MASKED(omac[2], tmp_mac[2], tmp_mask[2]);
+}
+
+/*
+ * ovsmgr_dp_action_set_mask_get_dscp()
+ *	Return DSCP value configured in flow rule
+ */
+static int ovsmgr_dp_action_set_mask_get_dscp(struct sw_flow_key *key, const struct nlattr *a)
+{
+	switch (nla_type(a)) {
+	case OVS_KEY_ATTR_IPV4: {
+		const struct ovs_key_ipv4 *key = nla_data(a);
+		const struct ovs_key_ipv4 *mask = ((struct ovs_key_ipv4 *)nla_data(a) + 1); /* mask starts after key */
+
+		if (mask->ipv4_tos) {
+			ovsmgr_info("%px: Change ipv4 TOS/DSCP to %x:%d\n", key, mask->ipv4_tos, key->ipv4_tos);
+			return key->ipv4_tos;
+		}
+
+		break;
+	}
+	case OVS_KEY_ATTR_IPV6: {
+		const struct ovs_key_ipv6 *key = nla_data(a);
+		const struct ovs_key_ipv6 *mask = ((struct ovs_key_ipv6*)nla_data(a) + 1); /* mask starts after key */
+
+		if (mask->ipv6_tclass) {
+			ovsmgr_info("%px: Change ipv4 TOS/DSCP to %x:%d\n",
+					key, mask->ipv6_tclass,  key->ipv6_tclass);
+			return key->ipv6_tclass;
+		}
+		break;
+
+	}
+	}
+
+	return OVSMGR_INVALID_DSCP;
+}
+
+/*
+ * ovsmgr_dp_flow_can_eth_set_accel()
+ *	Validate Ethernet set actions and see if flow can be accelerated
+ */
+static bool ovsmgr_dp_flow_can_eth_set_accel(const struct ovs_key_ethernet *key, const struct ovs_key_ethernet *mask,
+						struct sk_buff *skb)
+{
+	struct ethhdr *eh;
+	u8 new_saddr[ETH_HLEN], new_daddr[ETH_HLEN];
+
+	eh = eth_hdr(skb);
+
+	ovsmgr_dp_eth_mask_addr(eh->h_source, key->eth_src, mask->eth_src, new_saddr);
+	ovsmgr_dp_eth_mask_addr(eh->h_dest, key->eth_dst, mask->eth_dst, new_daddr);
+	if (!ether_addr_equal(eh->h_source, new_saddr) ||
+	    !ether_addr_equal(eh->h_dest, new_daddr)) {
+		ovsmgr_trace("%px: Change Source/Dest MAC address SMAC: %pM->%pM, DMAC: %pM->%pM\n", key,
+				eh->h_source, new_saddr, eh->h_dest, new_daddr);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * ovsmgr_dp_flow_can_ipv4_set_accel()
+ *	Validate IPv4 set actions and see if flow can be accelerated
+ */
+static bool ovsmgr_dp_flow_can_ipv4_set_accel(const struct ovs_key_ipv4 *key, const struct ovs_key_ipv4 *mask, struct sk_buff *skb)
+{
+	struct iphdr *iph;
+
+	/*
+	 * Check if IP header parameters are changing.
+	 * Allow only DSCP remarking, if other parameters are changing then
+	 * do not allow acceleration.
+	 */
+	iph = ip_hdr(skb);
+	if (mask->ipv4_src) {
+		__be32 new_addr;
+
+		new_addr = OVS_MASKED(iph->saddr, key->ipv4_src, mask->ipv4_src);
+		if (unlikely(new_addr != iph->saddr)) {
+			ovsmgr_trace("%px: Source IP address is changing - %pI4->%pI4\n", key, &iph->saddr, &new_addr);
+			return false;
+		}
+	}
+
+	if (mask->ipv4_dst) {
+		__be32 new_addr;
+
+		new_addr = OVS_MASKED(iph->daddr, key->ipv4_dst, mask->ipv4_dst);
+		if (unlikely(new_addr != iph->daddr)) {
+			ovsmgr_trace("%px: Destination IP address is changing - %pI4->%pI4\n", key, &iph->daddr, &new_addr);
+			return false;
+		}
+	}
+
+	if (mask->ipv4_ttl) {
+		u8 new_ttl;
+
+		new_ttl = OVS_MASKED(iph->ttl, key->ipv4_ttl, mask->ipv4_ttl);
+		if (unlikely(new_ttl != iph->ttl)) {
+			ovsmgr_trace("%px: TTL is changing - %d->%d\n", key, iph->ttl, new_ttl);
+			return false;
+		}
+	}
+
+	if (mask->ipv4_tos) {
+		ovsmgr_info("%px: Change ipv4 TOS/DSCP to %x:%d\n", key, mask->ipv4_tos, key->ipv4_tos);
+		return true;
+	}
+
+	return false;
+}
+
+/*
+ * ovsmgr_dp_flow_can_ipv6_set_accel()
+ *	Validate IPv6 set actions and see if flow can be accelerated
+ */
+static bool ovsmgr_dp_flow_can_ipv6_set_accel(const struct ovs_key_ipv6 *key, const struct ovs_key_ipv6 *mask, struct sk_buff *skb)
+{
+	struct ipv6hdr *ip6h;
+
+	/*
+	 * Check if IPv6 header parameters are changing.
+	 * Allow only DSCP remarking, if other parameters are changing then
+	 * do not allow acceleration.
+	 */
+	ip6h = ipv6_hdr(skb);
+	if (ovsmgr_dp_is_ipv6_mask_nonzero(mask->ipv6_src)) {
+		__be32 *saddr = (__be32 *)&ip6h->saddr;
+		__be32 new_addr[4];
+
+		ovsmgr_dp_ipv6_mask_addr(saddr, key->ipv6_src, mask->ipv6_src, new_addr);
+		if (unlikely(memcmp(saddr, new_addr, sizeof(new_addr)))) {
+			ovsmgr_trace("%px: Source IP address is changing - %pI6->%pI6\n", key, saddr, new_addr);
+			return false;
+		}
+	}
+
+	if (ovsmgr_dp_is_ipv6_mask_nonzero(mask->ipv6_dst)) {
+		__be32 *daddr = (__be32 *)&ip6h->daddr;
+		__be32 new_addr[4];
+
+		ovsmgr_dp_ipv6_mask_addr(daddr, key->ipv6_src, mask->ipv6_src, new_addr);
+		if (unlikely(memcmp(daddr, new_addr, sizeof(new_addr)))) {
+			ovsmgr_trace("%px: Destination IP address is changing - %pI6->%pI6\n", key, daddr, new_addr);
+			return false;
+		}
+	}
+
+	if (mask->ipv6_hlimit) {
+		u8 new_hlimit;
+
+		new_hlimit = OVS_MASKED(ip6h->hop_limit, key->ipv6_hlimit, mask->ipv6_hlimit);
+		if (unlikely(new_hlimit != ip6h->hop_limit)) {
+			ovsmgr_trace("%px: TTL is changing - %d->%d\n", key, ip6h->hop_limit, new_hlimit);
+			return false;
+		}
+	}
+
+	if (mask->ipv6_tclass) {
+		ovsmgr_info("%px: Change ipv4 TOS/DSCP to %x:%d\n", key, mask->ipv6_tclass,  key->ipv6_tclass);
+		return true;
+	}
+
+	return false;
+}
+
+/*
+ * ovsmgr_dp_flow_can_udp_set_accel()
+ *	Validate UDP set actions and see if flow can be accelerated
+ */
+static bool ovsmgr_dp_flow_can_udp_set_accel(const struct ovs_key_udp *key, const struct ovs_key_udp *mask, struct sk_buff *skb)
+{
+	struct udphdr *uh;
+	__be16 src, dst;
+
+	uh = udp_hdr(skb);
+	src = OVS_MASKED(uh->source, key->udp_src, mask->udp_src);
+	dst = OVS_MASKED(uh->dest, key->udp_dst, mask->udp_dst);
+
+	if (unlikely(src != uh->source) || (unlikely(dst != uh->dest)) ) {
+		ovsmgr_trace("%px: Change Source/Dest port: sport: %d->%d, dport: %d->%d\n", key,
+				ntohs(uh->source), ntohs(src), ntohs(uh->dest), ntohs(dst));
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * ovsmgr_dp_flow_can_tcp_set_accel()
+ *	Validate TCP set actions and see if flow can be accelerated
+ */
+static bool ovsmgr_dp_flow_can_tcp_set_accel(const struct ovs_key_tcp *key, const struct ovs_key_tcp *mask, struct sk_buff *skb)
+{
+	struct tcphdr *th;
+	__be16 src, dst;
+
+	th = tcp_hdr(skb);
+	src = OVS_MASKED(th->source, key->tcp_src, mask->tcp_src);
+	dst = OVS_MASKED(th->dest, key->tcp_dst, mask->tcp_dst);
+
+	if (unlikely(src != th->source) || (unlikely(dst != th->dest)) ) {
+		ovsmgr_trace("%px: Change Source/Dest port: sport: %d->%d, dport: %d->%d\n", key,
+				ntohs(th->source), ntohs(src), ntohs(th->dest), ntohs(dst));
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * ovsmgr_dp_flow_can_set_mask_accel()
+ *	Validate flow and actions and see if flow can be accelerated
+ */
+static bool ovsmgr_dp_flow_can_set_mask_accel(struct sw_flow_key *key, const struct nlattr *a, struct sk_buff *skb)
+{
+	switch (nla_type(a)) {
+	case OVS_KEY_ATTR_PRIORITY:
+	case OVS_KEY_ATTR_SKB_MARK:
+		return true;
+	case OVS_KEY_ATTR_IPV4: {
+		    const struct ovs_key_ipv4 *v4_key = nla_data(a);
+		    const struct ovs_key_ipv4 *mask = ((struct ovs_key_ipv4 *)nla_data(a) + 1); /* mask starts after key */
+
+		    if (ovsmgr_dp_flow_can_ipv4_set_accel(v4_key, mask, skb)) {
+			    ovsmgr_trace("%px: IPv4 set actions are supported\n", key);
+			    return true;
+		    }
+
+		    break;
+	}
+	case OVS_KEY_ATTR_IPV6: {
+		    const struct ovs_key_ipv6 *v6_key = nla_data(a);
+		    const struct ovs_key_ipv6 *mask = ((struct ovs_key_ipv6*)nla_data(a) + 1); /* mask starts after key */
+
+		    if (ovsmgr_dp_flow_can_ipv6_set_accel(v6_key, mask, skb)) {
+			    ovsmgr_trace("%px: IPv6 set actions are supported\n", key);
+			    return true;
+		    }
+
+		    break;
+	}
+	case OVS_KEY_ATTR_ETHERNET: {
+		    const struct ovs_key_ethernet *eth_key = nla_data(a);
+		    const struct ovs_key_ethernet *mask = ((struct ovs_key_ethernet*)nla_data(a) + 1); /* mask starts after key */
+
+		    if (ovsmgr_dp_flow_can_eth_set_accel(eth_key, mask, skb)) {
+			    ovsmgr_trace("%px: Ethernet set actions are supported\n", key);
+			    return true;
+		    }
+
+		    break;
+	}
+	case OVS_KEY_ATTR_TCP: {
+		    const struct ovs_key_tcp *tcp_key = nla_data(a);
+		    const struct ovs_key_tcp *mask = ((struct ovs_key_tcp*)nla_data(a) + 1); /* mask starts after key */
+
+		    if (ovsmgr_dp_flow_can_tcp_set_accel(tcp_key, mask, skb)) {
+			    ovsmgr_trace("%px: TCP set actions are supported\n", key);
+			    return true;
+		    }
+
+		    break;
+	}
+	case OVS_KEY_ATTR_UDP: {
+		    const struct ovs_key_udp *udp_key = nla_data(a);
+		    const struct ovs_key_udp *mask = ((struct ovs_key_udp*)nla_data(a) + 1); /* mask starts after key */
+
+		    if (ovsmgr_dp_flow_can_udp_set_accel(udp_key, mask, skb)) {
+			    ovsmgr_trace("%px: UDP set actions are supported\n", key);
+			    return true;
+		    }
+
+		    break;
+	}
+	default:
+		return false;
+	}
+
+	return false;
+}
+
+/*
+ * ovsmgr_dp_flow_can_accel()
+ *	Validate flow and actions and see if flow can be accelerated
+ */
+static bool ovsmgr_dp_flow_can_accel(struct sw_flow *sf, struct sw_flow_key *key,
+					 struct sw_flow_actions *sfa, struct sk_buff *skb)
+{
+	struct ovsmgr_dp_port *nodp;
+	struct ovsmgr_dp *nod;
+	const struct nlattr *a;
+	int port_num, rem;
+	int egress_cnt = 0;
+
+	/*
+	 * Following are the checks done:
+	 *	1. Only TCP and UDP packets are accelerated
+	 *	2. Ingress port shouldn't be internal port (bridge interface)
+	 *	3. Parse supported actions
+	 */
+
+	/*
+	 * 1. Allow specific IP protocols
+	 */
+	switch (key->ip.proto) {
+	case IPPROTO_TCP:
+	case IPPROTO_UDP:
+		break;
+	default:
+		ovsmgr_warn("%px: IP protocol is not supported, proto=%d\n", sf, key->ip.proto);
+		return false;
+	}
+
+	/*
+	 * 2. Do not allow incoming routed packets, ingress
+	 *    interface shouldn't be bridge interface
+	 */
+	port_num = key->phy.in_port;
+	read_lock(&ovsmgr_ctx.lock);
+
+	nod = ovsmgr_dp_find_by_port(port_num);
+	if (!nod) {
+		read_unlock(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: datapath instance is not found, ingress port_num = %d\n", sf, port_num);
+		return false;
+	}
+
+	nodp = ovsmgr_dp_port_find_by_num(nod, port_num);
+	if (!nodp) {
+		read_unlock(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: datapath port instance is not found, ingress port_num = %d\n", sf, port_num);
+		return false;
+	}
+
+	/*
+	 * Do not accelerate packets received from OVS bridge interface.
+	 * These are routed flows.
+	 */
+	if (nodp->vport_type == OVS_VPORT_TYPE_INTERNAL) {
+		read_unlock(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: ingress port(%d:%s): incoming routed flows not forwarded through hook.\n",
+				sf, port_num, nodp->dev->name);
+		return false;
+	}
+	read_unlock(&ovsmgr_ctx.lock);
+
+	for (a = sfa->actions, rem = sfa->actions_len; rem > 0;
+			a = nla_next(a, &rem)) {
+		/*
+		 * 3. Allow specific actions
+		 *	- Allow multiple output actions (multiple egress ports) only for multicast
+		 *	  flow.
+		 *	- Allow specific actions, if any other action is set for
+		 *	  this flow then do not accelerate.
+		 */
+		switch (nla_type(a)) {
+		case OVS_ACTION_ATTR_OUTPUT: {
+
+			port_num = nla_get_u32(a);
+
+			read_lock(&ovsmgr_ctx.lock);
+			nodp = ovsmgr_dp_port_find_by_num(nod, port_num);
+			if (!nodp) {
+				read_unlock(&ovsmgr_ctx.lock);
+				ovsmgr_warn("%px: datapath port instance is not found, port_num = %d\n", sf, port_num);
+				return false;
+			}
+
+			if (nodp->vport_type == OVS_VPORT_TYPE_INTERNAL) {
+				read_unlock(&ovsmgr_ctx.lock);
+				ovsmgr_warn("%px: output port(%d:%s): egress routed flows not forwarded through hook.\n",
+						sf, port_num, nodp->dev->name);
+				return false;
+			}
+
+			read_unlock(&ovsmgr_ctx.lock);
+			egress_cnt++;
+		}
+		case OVS_ACTION_ATTR_PUSH_VLAN:
+		case OVS_ACTION_ATTR_POP_VLAN:
+		case OVS_ACTION_ATTR_CT:
+		     break;
+		case OVS_ACTION_ATTR_SET_MASKED:
+		case OVS_ACTION_ATTR_SET_TO_MASKED: {
+		     ovsmgr_info("%px: Action is SET_MASKED/SET_TO_MASKED: %d\n", sf, nla_type(a));
+		     if (!ovsmgr_dp_flow_can_set_mask_accel(&sf->key, nla_data(a), skb)) {
+			     return false;
+		     }
+
+		     break;
+		}
+		default:
+		     ovsmgr_warn("%px: Action is not supported, action=%x\n", sf, nla_type(a));
+		     return false;
+		}
+	}
+
+	/*
+	 * Do not accelerate the flow if egress_cnt is more than 1 and
+	 * destination IP is unicast.  This could be a broadcast flow rule
+	 * to find the egress for destination port.
+	 */
+	if ((egress_cnt > 1) && (skb->pkt_type != PACKET_MULTICAST)) {
+		ovsmgr_warn("%px: Not multicast packet :egress > 1, type = %d, egress_cnt = %d\n",
+				sf, skb->pkt_type, egress_cnt);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * ovsmgr_dp_flow_first_egress_find()
+ *	Find the first egress port from flow rule
+ */
+static int ovsmgr_dp_flow_first_egress_find(struct sw_flow *sf)
+{
+	struct sw_flow_actions *sfa;
+	const struct nlattr *a;
+	int rem;
+
+	if (!sf) {
+		ovsmgr_warn("flow is null\n");
+		return -EINVAL;
+	}
+
+	sfa = rcu_dereference(sf->sf_acts);
+	if (!sfa) {
+		ovsmgr_warn("%px: flow actions is null\n", sf);
+		return -EINVAL;
+	}
+
+	for (a = sfa->actions, rem = sfa->actions_len; rem > 0;
+	     a = nla_next(a, &rem)) {
+
+		if (nla_type(a) == OVS_ACTION_ATTR_OUTPUT) {
+			return nla_get_u32(a);
+		}
+	}
+
+	return -EINVAL;
+}
+
+/*
+ * ovsmgr_dp_flow_egress_find()
+ *	Return the first output interface in the actions
+ */
+static struct net_device *ovsmgr_dp_flow_egress_find(void *dp, struct sw_flow *sf)
+{
+	int port_num;
+
+	port_num = ovsmgr_dp_flow_first_egress_find(sf);
+	if (unlikely(port_num < 0)) {
+		return NULL;
+	}
+
+	return ovs_accel_dev_find(dp, port_num);
+}
+
+/*
+ * ovsmgr_dp_flow_get()
+ *	Return the flow tuple from datapath flow rule
+ */
+static int ovsmgr_dp_flow_get(void *dp, struct sw_flow *sf, struct ovsmgr_dp_flow *flow)
+{
+	struct sw_flow_key *key = &sf->key;
+
+	memset(flow, 0, sizeof(*flow));
+
+	flow->indev = ovs_accel_dev_find(dp, key->phy.in_port);
+	flow->outdev = ovsmgr_dp_flow_egress_find(dp, sf);
+
+	ether_addr_copy(flow->smac, key->eth.src);
+	ether_addr_copy(flow->dmac, key->eth.dst);
+
+	if (key->eth.type == htons(ETH_P_IP)) {
+		memcpy(&flow->tuple.ipv4, &key->ipv4.addr, sizeof(flow->tuple.ipv4));
+		flow->tuple.ip_version = 4;
+	} else if (key->eth.type == htons(ETH_P_IPV6)) {
+		memcpy(&flow->tuple.ipv6, &key->ipv6.addr, sizeof(flow->tuple.ipv6));
+		flow->tuple.ip_version = 6;
+	} else {
+		ovsmgr_warn("%px: Eth type is not accelerated: %x\n", sf, htons(key->eth.type));
+		return -EINVAL;
+	}
+
+	/*
+	 * copy ingress VLAN
+	 */
+	if (OVSMGR_KEY_VLAN_TCI(key)) {
+		flow->ingress_vlan.h_vlan_TCI = ntohs(OVSMGR_KEY_VLAN_TCI(key)) & ~VLAN_TAG_PRESENT;
+		ovsmgr_info("%px: ingress VLAN tag is %X\n", sf, flow->ingress_vlan.h_vlan_TCI);
+	}
+
+	flow->tuple.src_port = key->tp.src;
+	flow->tuple.dst_port = key->tp.dst;
+	flow->tuple.protocol = key->ip.proto;
+
+	if (!flow->outdev || !flow->indev) {
+		ovsmgr_warn("%px: Output device (outdev:%p) or (indev:%p) is NULL\n", sf, flow->outdev, flow->indev);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * ovsmgr_dp_pkt_process()
+ *	Process datapath packet.
+ */
+static void ovsmgr_dp_pkt_process(void *dp, struct sk_buff *skb, struct sw_flow_key *key,
+		struct sw_flow *sf, struct sw_flow_actions *sfa)
+{
+	struct ovs_skb_cb ovs_cb;
+	struct ovsmgr_dp_hook_ops *ops;
+	struct net_device *out;
+	bool hook_called = false;
+
+	/*
+	 * skb->cb is used internally by OVS datapath.
+	 * Save skb->cb before using, restore it back before returning.
+	 */
+	ovs_cb = *OVS_CB(skb);
+	atomic64_inc(&ovsmgr_ctx.stats.pkts_from_ovs_dp);
+
+	/*
+	 * Call pre-flow hook if flow is NULL
+	 */
+	if (!sf) {
+		/*
+		 * Forward only IGMP/ICMPv6 packets.
+		 */
+		if (likely(key->ip.proto != IPPROTO_IGMP) && likely(key->ip.proto != IPPROTO_ICMPV6))
+			return;
+
+		/*
+		 * Pull Ethernet header from skb before forwarding the packet to hook
+		 */
+		skb_pull(skb, ETH_HLEN);
+		list_for_each_entry(ops, &ovsmgr_ctx.dp_hooks, list) {
+			if (ops->hook_num == OVSMGR_DP_HOOK_PRE_FLOW_PROC) {
+				ops->hook(skb, NULL);
+				hook_called = true;
+			}
+		}
+
+		/*
+		 * Restore Ethernet header
+		 */
+		skb_push(skb, ETH_HLEN);
+
+		if (!hook_called) {
+			ovsmgr_warn("%px: Pre flow hook is not registered.\n", dp);
+		} else {
+			atomic64_inc(&ovsmgr_ctx.stats.pkts_fwd_pre_flow);
+		}
+
+		return;
+	}
+
+	if (!ovsmgr_dp_flow_can_accel(sf, key, sfa, skb)) {
+		ovsmgr_warn("%px: flow cannot be accelerated\n", skb);
+		return;
+	}
+
+	out = ovsmgr_dp_flow_egress_find(dp, sf);
+	if (unlikely(!out)) {
+		ovsmgr_warn("%px: egress interface is not found in flow rule - %px\n", skb, sf);
+		return;
+	}
+
+	/*
+	 * Pull Ethernet header from skb before forwarding the packet to hook
+	 */
+	hook_called = false;
+	OVSMGR_OVS_CB(skb)->flow = sf;
+	OVSMGR_OVS_CB(skb)->ovs_sig = OVSMGR_SKB_SIGNATURE;
+
+	skb_pull(skb, ETH_HLEN);
+	list_for_each_entry(ops, &ovsmgr_ctx.dp_hooks, list) {
+		if (ops->hook_num == OVSMGR_DP_HOOK_POST_FLOW_PROC) {
+			ops->hook(skb, out);
+			hook_called = true;
+		}
+	}
+
+	/*
+	 * Restore Ethernet header
+	 */
+	skb_push(skb, ETH_HLEN);
+
+	if (!hook_called) {
+		ovsmgr_warn("%px: Post flow hook is not registered.\n", dp);
+	} else {
+		atomic64_inc(&ovsmgr_ctx.stats.pkts_fwd_post_flow);
+	}
+
+	/*
+	 * Restore skb->cb
+	 */
+	*OVS_CB(skb) = ovs_cb;
+}
+
+/*
+ * ovsmgr_dp_port_vlan_notify()
+ *	Send VLAN add/del notification
+ */
+static void ovsmgr_dp_port_vlan_notify(void *dp, struct ovsmgr_dp_flow *flow, int event)
+{
+	struct ovsmgr_dp_port_vlan_info vlan;
+	struct ovsmgr_notifiers_info info;
+	struct ovsmgr_dp_port *nodp;
+	struct ovsmgr_dp *nod;
+	int i;
+
+	read_lock_bh(&ovsmgr_ctx.lock);
+
+	nod = ovsmgr_dp_find(dp);
+	if (!nod) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: datapath instance is not found\n", dp);
+		return;
+	}
+
+	nodp = ovsmgr_dp_port_find_by_dev(nod, flow->indev);
+	if (!nodp) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: Port is not found, dev = %s\n", dp, flow->indev->name);
+		return;
+	}
+
+	/*
+	 * Check if VLAN is set for the port.
+	 */
+	for (i = 0; i < OVSMGR_PORT_VLAN_MAX_CNT; i++) {
+		if (nodp->vlan[i].h_vlan_TCI == flow->ingress_vlan.h_vlan_TCI) {
+			if (event == OVSMGR_DP_VLAN_ADD) {
+				/*
+				 * VLAN ID is already notified
+				 */
+				read_unlock_bh(&ovsmgr_ctx.lock);
+				return;
+			}
+
+			if (event == OVSMGR_DP_VLAN_DEL) {
+				vlan.dev = flow->indev;
+				vlan.master = nodp->master_dev;
+				vlan.vh.h_vlan_TCI = flow->ingress_vlan.h_vlan_TCI;
+				info.vlan = &vlan;
+				ovsmgr_notifiers_call(&info, OVSMGR_DP_VLAN_DEL);
+				nodp->vlan[i].h_vlan_TCI = 0;
+				read_unlock_bh(&ovsmgr_ctx.lock);
+				return;
+			}
+		}
+	}
+
+	for (i = 0; i < OVSMGR_PORT_VLAN_MAX_CNT; i++) {
+		if (!nodp->vlan[i].h_vlan_TCI) {
+			nodp->vlan[i].h_vlan_TCI = flow->ingress_vlan.h_vlan_TCI;
+			vlan.dev = flow->indev;
+			vlan.master = nodp->master_dev;
+			vlan.vh.h_vlan_TCI = flow->ingress_vlan.h_vlan_TCI;
+			info.vlan = &vlan;
+			ovsmgr_notifiers_call(&info, OVSMGR_DP_VLAN_ADD);
+			break;
+		}
+	}
+
+	read_unlock_bh(&ovsmgr_ctx.lock);
+}
+
+/*
+ * ovsmgr_dp_flow_tbl_flush()
+ *	Flow table is flushed in datapath
+ */
+static void ovsmgr_dp_flow_tbl_flush(void *dp)
+{
+	ovsmgr_notifiers_call(NULL, OVSMGR_DP_FLOW_TBL_FLUSH);
+}
+
+/*
+ * ovsmgr_dp_flow_del()
+ *	Flow rule is deleted from datapath
+ */
+static void ovsmgr_dp_flow_del(void *dp, struct sw_flow *sf)
+{
+	struct ovsmgr_notifiers_info info;
+	struct ovsmgr_dp_flow flow;
+
+	ovsmgr_info("%px: flow del - %px\n", dp, sf);
+	ovsmgr_dp_flow_dump(sf);
+
+	if (!ovsmgr_dp_flow_get(dp, sf, &flow)) {
+		if (flow.ingress_vlan.h_vlan_TCI) {
+			ovsmgr_dp_port_vlan_notify(dp, &flow, OVSMGR_DP_VLAN_DEL);
+		}
+
+		info.flow = &flow;
+		ovsmgr_notifiers_call(&info, OVSMGR_DP_FLOW_DEL);
+	}
+}
+
+/*
+ * ovsmgr_dp_flow_drop()
+ *	Check if flow (sf) is set to drop (old actions sfa) and notify delete.
+ */
+static inline void ovsmgr_dp_flow_drop(void *dp, struct sw_flow *sf, struct sw_flow_actions *old_sfa, struct ovsmgr_dp_flow *flow)
+{
+	struct sw_flow_actions *new_acts;
+	struct ovsmgr_notifiers_info info;
+	const struct nlattr *a;
+	int rem, port_num = -1;
+
+	if (!old_sfa) {
+		ovsmgr_info("%px: old_acts is NULL\n", dp);
+		return;
+	}
+
+	new_acts = ovsl_dereference(sf->sf_acts);
+	if (!new_acts) {
+		ovsmgr_info("%px: new_acts is NULL\n", dp);
+		return;
+	}
+
+	/*
+	 * Check if flow action is set to drop in datapath
+	 */
+	if (new_acts->actions_len) {
+		ovsmgr_info("%px: new_acts length is not 0\n", dp);
+		return;
+	}
+
+	ovsmgr_trace("%px: flow drop rule is added in datapath (indev=%s, outdev=%s)\n", dp,
+			flow->indev ? flow->indev->name : NULL,
+			flow->outdev ? flow->outdev->name : NULL);
+
+	/*
+	 * Validate flow, it is possible that the flow may not be accelerated.
+	 */
+	if (!flow->tuple.ip_version) {
+		ovsmgr_info("%px: flow->is not IPv6 or IPv4\n", dp);
+		return;
+	}
+
+	if (unlikely(!flow->indev)) {
+		ovsmgr_info("%px: flow->indev is NULL\n", dp);
+		return;
+	}
+
+	for (a = old_sfa->actions, rem = old_sfa->actions_len; rem > 0;
+	     a = nla_next(a, &rem)) {
+
+		switch (nla_type(a)) {
+		case OVS_ACTION_ATTR_OUTPUT:
+
+			/*
+			 * If the flow is multicast then output action can be many.
+			 *  port_num will hold the last output port.
+			 */
+			port_num = nla_get_u32(a);
+
+#if __has_attribute(__fallthrough__)
+	__attribute__((__fallthrough__));
+#endif
+
+		case OVS_ACTION_ATTR_PUSH_VLAN:
+		case OVS_ACTION_ATTR_POP_VLAN:
+		case OVS_ACTION_ATTR_CT:
+		case OVS_ACTION_ATTR_SET_MASKED:
+		case OVS_ACTION_ATTR_SET_TO_MASKED:
+			continue;
+
+		default:
+			ovsmgr_info("%px: flow was not accelerated, old action(%d)\n", dp, nla_type(a));
+			return;
+		}
+	}
+
+	if (port_num == -1) {
+		ovsmgr_info("%px: port number could not found for old flow\n", dp);
+		return;
+	}
+
+	flow->outdev = ovs_accel_dev_find(dp, port_num);
+	if (!flow->outdev) {
+		ovsmgr_info("%px: flow->outdev is NULL for portnum=%d\n", dp, port_num);
+		return;
+	}
+
+	ovsmgr_trace("%px: Flow is set to drop packets in datapath, sending delete notify (indev=%s, outdev=%s, port=%d)\n",
+					dp, flow->indev->name, flow->outdev->name, port_num);
+
+	info.flow = flow;
+	ovsmgr_notifiers_call(&info, OVSMGR_DP_FLOW_DEL);
+}
+
+/*
+ * ovsmgr_dp_flow_set()
+ *	Flow rule is modified
+ */
+static void ovsmgr_dp_flow_set(void *dp, struct sw_flow *sf, struct sw_flow_actions *sfa)
+{
+	struct ovsmgr_notifiers_info info;
+	struct ovsmgr_dp_flow flow;
+
+	ovsmgr_info("%px: flow set - %px:%px\n", dp, sf, sfa);
+	ovsmgr_dp_flow_dump(sf);
+
+	/*
+	 * Check if old rule got modified to a "drop" rule. If so, defunct the old
+	 * connection in Acceleration engine.
+	 */
+	if (ovsmgr_dp_flow_get(dp, sf, &flow)) {
+		return ovsmgr_dp_flow_drop(dp, sf, sfa, &flow);
+	}
+
+	info.flow = &flow;
+	if (is_multicast_ether_addr(flow.dmac)) {
+		/*
+		 * Multicast flow is updated, send change notifier.
+		 */
+		ovsmgr_notifiers_call(&info, OVSMGR_DP_FLOW_CHANGE);
+	} else {
+		/*
+		 * Unicast flow is updated, send delete notifier.
+		 */
+		ovsmgr_notifiers_call(&info, OVSMGR_DP_FLOW_DEL);
+	}
+}
+
+/*
+ * ovsmgr_dp_flow_add()
+ *	New flow rule is added in the datapath
+ */
+static void ovsmgr_dp_flow_add(void *dp, struct sw_flow *sf)
+{
+	struct ovsmgr_notifiers_info info;
+	struct ovsmgr_dp_flow flow;
+
+	ovsmgr_info("%px: flow add - %px\n", dp, sf);
+	ovsmgr_dp_flow_dump(sf);
+
+	if (!ovsmgr_dp_flow_get(dp, sf, &flow)) {
+		if (flow.ingress_vlan.h_vlan_TCI) {
+			ovsmgr_dp_port_vlan_notify(dp, &flow, OVSMGR_DP_VLAN_ADD);
+		}
+
+		info.flow = &flow;
+		ovsmgr_notifiers_call(&info, OVSMGR_DP_FLOW_ADD);
+	}
+}
+
+/*
+ * ovsmgr_dp_port_del()
+ *	OVS datapath port is deleted
+ */
+static void ovsmgr_dp_port_del(void *dp, void *vp, struct net_device *dev)
+{
+	struct ovsmgr_notifiers_info info;
+	struct ovsmgr_dp_port_info port;
+	struct ovsmgr_dp_port *nodp;
+	struct ovsmgr_dp *nod;
+	struct net_device *master_dev;
+	bool is_vport_internal = false;
+
+	ovsmgr_info("%px:%px port deleting - dev = %s\n", dp, vp, dev->name);
+
+	write_lock_bh(&ovsmgr_ctx.lock);
+	nod = ovsmgr_dp_find(dp);
+	if (!nod) {
+		write_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: datapath instance is not found\n", dp);
+		return;
+	}
+
+	nodp = ovsmgr_dp_port_find_by_dev(nod, dev);
+	if (!nodp) {
+		write_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: Port is not found, dev = %s\n", dp, dev->name);
+		return;
+	}
+
+	master_dev = nodp->master_dev;
+	if (nodp->vport_type == OVS_VPORT_TYPE_INTERNAL) {
+		is_vport_internal = true;
+	}
+
+	/*
+	 * Remove port instance
+	 */
+	list_del(&nodp->node);
+	write_unlock_bh(&ovsmgr_ctx.lock);
+
+	kfree(nodp);
+
+	/*
+	 * Check if master_dev and dev are same and they are internal port.
+	 * These conditions will mean that bridge device is deleted,
+	 * send OVSMGR_DP_BR_DEL notifier.
+	 */
+	if ((master_dev == dev) && is_vport_internal) {
+		info.dev = master_dev;
+		ovsmgr_notifiers_call(&info, OVSMGR_DP_BR_DEL);
+		return;
+	}
+
+	port.master = master_dev;
+	port.dev = dev;
+	info.port = &port;
+
+	ovsmgr_notifiers_call(&info, OVSMGR_DP_PORT_DEL);
+}
+
+/*
+ * ovsmgr_dp_port_add()
+ *	New OVS datapath port is added
+ */
+static void ovsmgr_dp_port_add(void *dp, void *vp, int vp_num, enum ovs_vport_type vp_type,
+				   const char *master, struct net_device *dev)
+{
+	struct ovsmgr_notifiers_info info;
+	struct ovsmgr_dp_port_info port;
+	struct ovsmgr_dp_port *nodp;
+	struct ovsmgr_dp *nod;
+	struct net_device *master_dev = NULL;
+
+	if (!master) {
+		ovsmgr_info("%px: There is no master\n", dp);
+	} else {
+		ovsmgr_info("%px: Master device name set: %s\n", dp, master);
+		master_dev = __dev_get_by_name(&init_net, master);
+		if (!master_dev) {
+			ovsmgr_warn("%px: Master netdev not found\n", dp);
+		}
+	}
+
+	ovsmgr_info("%px:%px new port - dev = %s\n", dp, vp, dev->name);
+
+	nodp = kmalloc(sizeof(*nodp), GFP_KERNEL);
+	if (!nodp) {
+		ovsmgr_warn("%px: Memory allocation failed\n", dp);
+		return;
+	}
+
+	INIT_LIST_HEAD(&nodp->node);
+	nodp->dev = dev;
+	nodp->master_dev = master_dev;
+	nodp->vport_type = vp_type;
+	nodp->vport = vp;
+	nodp->vport_num = vp_num;
+	nodp->add_notified = false;
+	if (master) {
+		strlcpy(nodp->master_name, master, IFNAMSIZ);
+		ovsmgr_info("%px: Master device name set: %s\n", dp, master);
+		master_dev = __dev_get_by_name(&init_net, master);
+		if (!master_dev) {
+			ovsmgr_warn("%px: Master netdev not found\n", dp);
+		}
+	}
+
+	write_lock_bh(&ovsmgr_ctx.lock);
+
+	nod = ovsmgr_dp_find(dp);
+	if (!nod) {
+		write_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: datapath instance is not found\n", dp);
+		kfree(nodp);
+		return;
+	}
+
+	list_add(&nodp->node, &nod->port_list);
+	write_unlock_bh(&ovsmgr_ctx.lock);
+
+	/*
+	 * OVS bridge interface is also a port in datapath.  It
+	 * can be created before or after bridge ports.  So it is
+	 * possible that master is set but master_dev is NULL.  Generate
+	 * OVSMGR_DP_PORT_ADD notifier if master_dev is set, otherwise
+	 * generate when ovs bridge is created.
+	 */
+	if (master_dev && (vp_type != OVS_VPORT_TYPE_INTERNAL)) {
+		port.master = master_dev;
+		port.dev = dev;
+		info.port = &port;
+		ovsmgr_notifiers_call(&info, OVSMGR_DP_PORT_ADD);
+		nodp->add_notified = true;
+		return;
+	}
+
+	/*
+	 * If master_dev is same as dev, it means that OVS bridge interface is
+	 * created.  Send OVSMGR_DP_BR_ADD notifier and later send
+	 * OVSMGR_DP_PORT_ADD notifier for all the ports which are created
+	 * before bridge interface.
+	 */
+	if ((vp_type == OVS_VPORT_TYPE_INTERNAL) && (master_dev == dev)) {
+		info.dev = master_dev;
+		ovsmgr_notifiers_call(&info, OVSMGR_DP_BR_ADD);
+		nodp->add_notified = true;
+		ovsmgr_dp_send_ports_add_notifier(nod, master_dev);
+	}
+}
+
+/*
+ * ovsmgr_dp_del()
+ *	OVS datapath is deleted
+ */
+static void ovsmgr_dp_del(void *dp, struct net_device *dev)
+{
+	struct ovsmgr_notifiers_info info;
+	struct ovsmgr_dp *nod;
+
+	ovsmgr_info("%px: datapath deleting - dev = %s\n", dp, dev->name);
+
+	write_lock_bh(&ovsmgr_ctx.lock);
+	nod = ovsmgr_dp_find(dp);
+	if (!nod) {
+		write_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: datapath instance is not found\n", dp);
+		return;
+	}
+
+	list_del(&nod->node);
+	write_unlock_bh(&ovsmgr_ctx.lock);
+
+	kfree(nod);
+	info.dev = dev;
+	ovsmgr_notifiers_call(&info, OVSMGR_DP_DEL);
+}
+
+/*
+ * ovsmgr_dp_add()
+ *	New OVS data path is created
+ */
+static void ovsmgr_dp_add(void *dp, struct net_device *dev)
+{
+	struct ovsmgr_notifiers_info info;
+	struct ovsmgr_dp *new_dp;
+
+	ovsmgr_info("%px: new datapath - dev = %s\n", dp, dev->name);
+
+	new_dp = kmalloc(sizeof(*new_dp), GFP_KERNEL);
+	if (!new_dp) {
+		ovsmgr_warn("%px: failed to allocation memory\n", dp);
+		return;
+	}
+
+	INIT_LIST_HEAD(&new_dp->node);
+	INIT_LIST_HEAD(&new_dp->port_list);
+	new_dp->dev = dev;
+	new_dp->dp = dp;
+
+	write_lock_bh(&ovsmgr_ctx.lock);
+	list_add(&new_dp->node, &ovsmgr_ctx.dp_list);
+	write_unlock_bh(&ovsmgr_ctx.lock);
+
+	info.dev = dev;
+	ovsmgr_notifiers_call(&info, OVSMGR_DP_ADD);
+}
+
+/*
+ * OVS datapath acceleration callbacks
+ */
+static struct ovs_accel_callback ovs_cb = {
+	.ovs_accel_dp_add = ovsmgr_dp_add,
+	.ovs_accel_dp_del = ovsmgr_dp_del,
+	.ovs_accel_dp_port_add = ovsmgr_dp_port_add,
+	.ovs_accel_dp_port_del = ovsmgr_dp_port_del,
+	.ovs_accel_dp_flow_add = ovsmgr_dp_flow_add,
+	.ovs_accel_dp_flow_del = ovsmgr_dp_flow_del,
+	.ovs_accel_dp_flow_set = ovsmgr_dp_flow_set,
+	.ovs_accel_dp_flow_tbl_flush = ovsmgr_dp_flow_tbl_flush,
+	.ovs_accel_dp_pkt_process = ovsmgr_dp_pkt_process
+};
+
+/*
+ * ovsmgr_dp_flow_key_fill()
+ *	Fill key from flow and in_port
+ */
+static void ovsmgr_dp_flow_key_fill(struct ovsmgr_dp_flow *flow, int in_port, struct sw_flow_key *key)
+{
+	memset(key, 0, sizeof(*key));
+
+	key->phy.in_port = in_port;
+	ether_addr_copy(key->eth.src, flow->smac);
+	ether_addr_copy(key->eth.dst, flow->dmac);
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0))
+	key->mac_proto = MAC_PROTO_ETHERNET;
+#endif
+
+	if (flow->ingress_vlan.h_vlan_TCI) {
+		OVSMGR_KEY_VLAN_TCI(key) = htons(flow->ingress_vlan.h_vlan_TCI | VLAN_TAG_PRESENT);
+	}
+
+	if (flow->tuple.ip_version == 4) {
+		key->ipv4.addr.src = flow->tuple.ipv4.src;
+		key->ipv4.addr.dst = flow->tuple.ipv4.dst;
+		key->eth.type = htons(ETH_P_IP);
+	} else {
+		memcpy(&key->ipv6.addr.src, &flow->tuple.ipv6.src, sizeof(key->ipv6.addr.src));
+		memcpy(&key->ipv6.addr.dst, &flow->tuple.ipv6.dst, sizeof(key->ipv6.addr.dst));
+		key->eth.type = htons(ETH_P_IPV6);
+	}
+
+	key->tp.src = flow->tuple.src_port;
+	key->tp.dst = flow->tuple.dst_port;
+	key->ip.proto = flow->tuple.protocol;
+
+	ovsmgr_dp_flow_key_dump(key);
+}
+
+/*
+ * ovsmgr_dp_flow_info_get_by_mac()
+ *	Find OVS flow rule from MAC address and update VLAN information
+ */
+enum ovsmgr_flow_status ovsmgr_dp_flow_info_get_by_mac(void *dp, struct net_device *indev, struct net_device *outdev,
+							u8 *src, u8 *dst, __be16 type, struct ovsmgr_flow_info *ofi)
+{
+	struct sw_flow_key *sfk;
+	struct sw_flow *sf;
+
+	sf = ovs_accel_flow_find_by_mac(dp, indev, outdev, src, dst, type);
+	if (!sf) {
+		ovsmgr_warn("%px: Couldn't find flow rule using indev:%s, outdev:%s, SMAC:%pM, DMAC:%pM type:0x%x\n",
+				dp, indev ? indev->name:"NULL", outdev ? outdev->name:"NULL", src, dst, type);
+		return OVSMGR_FLOW_STATUS_DENY_ACCEL;
+	}
+
+	/*
+	 * Flow is found and flow key has ingress packet details.
+	 * If the flow rule is expecting VLAN header then it is expected
+	 * that from indev packet should be transmitted with VLAN header.
+	 * Copy ingress VLAN header to egress VLAN in VLAN info.
+	 */
+	sfk = &sf->key;
+	if (OVSMGR_KEY_VLAN_TCI(sfk)) {
+		ofi->egress[0].h_vlan_TCI = ntohs(OVSMGR_KEY_VLAN_TCI(sfk)) & ~VLAN_TAG_PRESENT;
+		ofi->egress[0].h_vlan_encapsulated_proto = ETH_P_8021Q;
+		ovsmgr_info("Egress VLAN : id = %x:%x\n",
+				ofi->egress[0].h_vlan_encapsulated_proto,
+				ofi->egress[0].h_vlan_TCI);
+		return OVSMGR_FLOW_STATUS_ALLOW_VLAN_ACCEL;
+	}
+
+	return OVSMGR_FLOW_STATUS_ALLOW_ACCEL;
+}
+
+/*
+ * ovsmgr_dp_flow_info_get()
+ *	Fill key from flow and in_port
+ */
+enum ovsmgr_flow_status ovsmgr_dp_flow_info_get(struct ovsmgr_dp_flow *flow,
+						     struct sk_buff *skb, struct ovsmgr_flow_info *ofi)
+{
+	struct ovsmgr_dp_port *in_port, *out_port;
+	struct sw_flow_actions *acts;
+	struct sw_flow_key key;
+	struct ovsmgr_dp *nod;
+	const struct nlattr *a;
+	struct sw_flow *sf;
+	enum ovsmgr_flow_status status = OVSMGR_FLOW_STATUS_DENY_ACCEL;
+	bool found_egress = false;
+	int in_port_num, out_port_num;
+	int vlan_index = 0;
+	int rem;
+	uint64_t prev_action = OVS_ACTION_ATTR_UNSPEC;
+	bool pop_vlan = false;
+
+	read_lock_bh(&ovsmgr_ctx.lock);
+
+	nod = ovsmgr_dp_find_by_dev(flow->indev);
+	if (unlikely(!nod)) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: Couldn't find datapath instance for dev = %s\n", flow, flow->indev->name);
+		return OVSMGR_FLOW_STATUS_DENY_ACCEL;
+	}
+
+	in_port = ovsmgr_dp_port_find_by_dev(nod, flow->indev);
+	if (!in_port) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: input datapath port instance is not found for dev = %s\n",
+				nod, flow->indev->name);
+		return OVSMGR_FLOW_STATUS_DENY_ACCEL;
+	}
+
+	out_port = ovsmgr_dp_port_find_by_dev(nod, flow->outdev);
+	if (!out_port) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: output datapath port instance is not found for dev = %s\n",
+				nod, flow->outdev->name);
+		return OVSMGR_FLOW_STATUS_DENY_ACCEL;
+	}
+
+	in_port_num = in_port->vport_num;
+	out_port_num = out_port->vport_num;
+	read_unlock_bh(&ovsmgr_ctx.lock);
+
+	ovsmgr_dp_flow_key_fill(flow, in_port_num, &key);
+
+	/*
+	 * If ingress packet is VLAN tagged then copy VLAN ID
+	 */
+	if (flow->ingress_vlan.h_vlan_TCI) {
+		/*
+		 * If ingress vlan is set then there is no need to update
+		 * ofi->ingress, caller is already aware that there is
+		 * ingress VLAN header.
+		 * This case is valid for multicast flow when there is an
+		 * egress list update.
+		 * Fill TCI in key, OVS datapath expects VLAN_TAG_PRESENT
+		 * to be set in TCI.
+		 */
+		OVSMGR_KEY_VLAN_TCI(&key) = htons(flow->ingress_vlan.h_vlan_TCI) | VLAN_TAG_PRESENT;
+	} else if (skb && skb_vlan_tag_present(skb)) {
+		/*
+		 * Read VLAN tag from skb
+		 * VLAN_TAG_PRESENT is set by kernel in skb, fill TCI in key.
+		 */
+		OVSMGR_KEY_VLAN_TCI(&key) = htons(skb->vlan_tci);
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 5, 0))
+		key.eth.vlan.tpid = htons(ETH_P_8021Q);
+		OVSMGR_KEY_VLAN_TCI(&key) |= htons(VLAN_TAG_PRESENT);
+#endif
+
+		ofi->ingress[0].h_vlan_TCI = skb_vlan_tag_get(skb);
+		ofi->ingress[0].h_vlan_encapsulated_proto = ntohs(skb->vlan_proto);
+		ovsmgr_info("Ingress VLAN : id = %x:%x\n",
+				ofi->ingress[0].h_vlan_encapsulated_proto,
+				ofi->ingress[0].h_vlan_TCI);
+
+		status = OVSMGR_FLOW_STATUS_ALLOW_VLAN_ACCEL;
+	}
+
+	/*
+	 * Find datapath rule with key.
+	 * If rule is not found and it is a routed flow, then find rule using
+	 * MAC addresses. For routed flows flow->indev is always OVS bridge interface.
+	 *
+	 * DSCP remarking action may not be configured.
+	 * Initialize DSCP value to invalid.
+	 */
+	ofi->dscp = OVSMGR_INVALID_DSCP;
+
+	sf = ovs_accel_flow_find(nod->dp, &key);
+	if (!sf) {
+		if (!flow->is_routed) {
+			ovsmgr_warn("%px:Couldn't find flow rule \n", flow);
+			return OVSMGR_FLOW_STATUS_DENY_ACCEL;
+		}
+
+		/*
+		 * Multicast flows are always uni-directional, call
+		 * ovsmgr_dp_flow_info_get_by_mac() API with populated
+		 * source and destination mac address.
+		 */
+		if (is_multicast_ether_addr(flow->dmac)) {
+			return ovsmgr_dp_flow_info_get_by_mac(nod->dp, flow->indev, flow->outdev,
+					key.eth.src, key.eth.dst, key.eth.type, ofi);
+		}
+
+		/*
+		 * For unicast flows, we need to swap the source and dest mac address
+		 * as we are querying for the reverse direction.
+		 */
+		return ovsmgr_dp_flow_info_get_by_mac(nod->dp, flow->outdev, flow->indev, key.eth.dst,
+					key.eth.src, key.eth.type, ofi);
+	}
+
+	/*
+	 * Flow is found, find if VLAN operations are needed and check
+	 * if egress port is allowed.
+	 */
+	rcu_read_lock();
+	acts = rcu_dereference(sf->sf_acts);
+
+	for (a = acts->actions, rem = acts->actions_len; rem > 0;
+	     a = nla_next(a, &rem)) {
+		switch (nla_type(a)) {
+		case OVS_ACTION_ATTR_OUTPUT:
+			if (out_port_num == nla_get_u32(a)) {
+				ovsmgr_info("%px: Found egress port in flow rule: %d\n", flow, out_port_num);
+				found_egress = true;
+				if (status == OVSMGR_FLOW_STATUS_DENY_ACCEL)
+					status = OVSMGR_FLOW_STATUS_ALLOW_ACCEL;
+				break;
+			}
+
+			prev_action = OVS_ACTION_ATTR_OUTPUT;
+			break;
+		case OVS_ACTION_ATTR_PUSH_VLAN: {
+			const struct ovs_action_push_vlan *vlan;
+
+			vlan = nla_data(a);
+			ovsmgr_info("Vlan details:\n");
+			ovsmgr_info("\tvlan_tpid = %x\n", vlan->vlan_tpid);
+			ovsmgr_info("\tvlan_tci = %x\n", vlan->vlan_tci & ~VLAN_TAG_PRESENT);
+
+			/*
+			 * Retain the VLAN information only for the below conditions,
+			 * 1. PUSH_VLAN is the first action
+			 * 2. Previous action was PUSH_VLAN
+			 *
+			 * Reset the VLAN information for all the other conditions.
+			 */
+			if ((prev_action != OVS_ACTION_ATTR_UNSPEC) &&
+					(prev_action != OVS_ACTION_ATTR_PUSH_VLAN)) {
+				vlan_index = 0;
+				ofi->egress[0].h_vlan_TCI = 0;
+				ofi->egress[0].h_vlan_encapsulated_proto = 0;
+				ofi->egress[1].h_vlan_TCI = 0;
+				ofi->egress[1].h_vlan_encapsulated_proto = 0;
+			}
+
+			/*
+			 * Allow only two VLAN headers
+			 */
+			if (vlan_index == 2) {
+				ovsmgr_info("%px: More than 2 VLAN headers, don't accelerate\n", flow);
+				rcu_read_unlock();
+				return OVSMGR_FLOW_STATUS_DENY_ACCEL;
+			}
+
+			ofi->egress[vlan_index].h_vlan_TCI = ntohs(vlan->vlan_tci) & ~VLAN_TAG_PRESENT;
+			ofi->egress[vlan_index].h_vlan_encapsulated_proto = ntohs(vlan->vlan_tpid);
+			vlan_index++;
+			prev_action = OVS_ACTION_ATTR_PUSH_VLAN;
+			break;
+		}
+		case OVS_ACTION_ATTR_POP_VLAN:
+			pop_vlan = true;
+			prev_action = OVS_ACTION_ATTR_POP_VLAN;
+			break;
+		case OVS_ACTION_ATTR_SET_MASKED:
+			prev_action = OVS_ACTION_ATTR_SET_MASKED;
+			ofi->dscp = ovsmgr_dp_action_set_mask_get_dscp(&sf->key, nla_data(a));
+			ovsmgr_info("%px: DSCP = %x\n", sf, ofi->dscp);
+			break;
+		case OVS_ACTION_ATTR_SET_TO_MASKED: {
+			prev_action = OVS_ACTION_ATTR_SET_TO_MASKED;
+			ofi->dscp = ovsmgr_dp_action_set_mask_get_dscp(&sf->key, nla_data(a));
+			ovsmgr_info("%px: DSCP = %x\n", sf, ofi->dscp);
+			break;
+		}
+		}
+
+		/*
+		 * If the egress port is found then the job is done.
+		 */
+		if (found_egress) {
+			break;
+		}
+	}
+	rcu_read_unlock();
+
+	/*
+	 * Do not accelerate if flow->outdev is not part of output list
+	 */
+	if (!found_egress) {
+		return OVSMGR_FLOW_STATUS_DENY_ACCEL;
+	}
+
+	switch (vlan_index) {
+	case 1: /* return single VLAN operation. */
+		return OVSMGR_FLOW_STATUS_ALLOW_VLAN_ACCEL;
+	case 2: /* return QinQ VLAN operation. */
+		return OVSMGR_FLOW_STATUS_ALLOW_VLAN_QINQ_ACCEL;
+	}
+
+	/*
+	 * If there is no POP_VLAN action and
+	 * it is a bridge flow, then the egress and ingress
+	 * VLANs are same.
+	 */
+	if (!pop_vlan && !flow->is_routed) {
+		ofi->egress[0].h_vlan_TCI = ofi->ingress[0].h_vlan_TCI;
+		ofi->egress[0].h_vlan_encapsulated_proto = ofi->ingress[0].h_vlan_encapsulated_proto;
+	}
+
+	return status;
+}
+
+/*
+ * ovsmgr_dp_dev_get_master()
+ *	Find datapath bridge interface for given bridge port
+ */
+struct net_device *ovsmgr_dp_dev_get_master(struct net_device *dev)
+{
+	struct ovsmgr_dp *nod;
+	struct ovsmgr_dp_port *nodp;
+	struct net_device *master_dev;
+
+	read_lock_bh(&ovsmgr_ctx.lock);
+	nod = ovsmgr_dp_find_by_dev(dev);
+	if (!nod) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("Couldn't find datapath instance, dev = %s\n", dev->name);
+		return NULL;
+	}
+
+	nodp = ovsmgr_dp_port_find_by_dev(nod, dev);
+	if (!nodp) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: input datapath port instance is not found for dev = %s\n",
+				nod, dev->name);
+		return NULL;
+	}
+
+	master_dev = nodp->master_dev;
+	read_unlock_bh(&ovsmgr_ctx.lock);
+	return master_dev;
+}
+
+/*
+ * ovsmgr_dp_dev_is_master()
+ *	Return true if dev is OVS bridge interface
+ */
+bool ovsmgr_dp_dev_is_master(struct net_device *dev)
+{
+	struct ovsmgr_dp *nod;
+	struct ovsmgr_dp_port *nodp;
+	bool is_master = false;
+
+	read_lock_bh(&ovsmgr_ctx.lock);
+	nod = ovsmgr_dp_find_by_dev(dev);
+	if (!nod) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("Couldn't find datapath instance, dev = %s\n", dev->name);
+		return false;
+	}
+
+	nodp = ovsmgr_dp_port_find_by_dev(nod, dev);
+	if (!nodp) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: input datapath port instance is not found for dev = %s\n",
+				nod, dev->name);
+		return false;
+	}
+
+	if ((nodp->vport_type == OVS_VPORT_TYPE_INTERNAL) && (nodp->master_dev == dev)) {
+		is_master = true;
+	}
+
+	read_unlock_bh(&ovsmgr_ctx.lock);
+	return is_master;
+}
+
+/*
+ * ovsmgr_dp_bridge_interface_stats_update()
+ *	Update OVS datapath bridge interface statistics.
+ */
+void ovsmgr_dp_bridge_interface_stats_update(struct net_device *dev,
+					  uint32_t rx_packets, uint32_t rx_bytes,
+					  uint32_t tx_packets, uint32_t tx_bytes)
+{
+	struct pcpu_sw_netstats *ovs_stats;
+
+	if (!ovsmgr_dp_dev_is_master(dev)) {
+		ovsmgr_warn("%px: %s is not an OVS bridge device\n", dev, dev->name);
+		return;
+	}
+
+	ovs_stats = this_cpu_ptr(dev->tstats);
+	u64_stats_update_begin(&ovs_stats->syncp);
+	ovs_stats->rx_packets += rx_packets;
+	ovs_stats->rx_bytes += rx_bytes;
+	ovs_stats->tx_packets += tx_packets;
+	ovs_stats->tx_bytes += tx_bytes;
+	u64_stats_update_end(&ovs_stats->syncp);
+}
+
+/*
+ * ovsmgr_dp_flow_stats_update()
+ *	Update datapath flow statistics
+ */
+void ovsmgr_dp_flow_stats_update(struct ovsmgr_dp_flow *flow, struct ovsmgr_dp_flow_stats *stats)
+{
+	struct sw_flow_key key;
+	struct ovsmgr_dp_port *in_port, *out_port;
+	struct ovsmgr_dp *nod;
+	void *out_vport;
+	int in_port_num;
+
+	/*
+	 * for bridge flows:
+	 *	indev and outdev are OVS bridge ports.
+	 * for route flows:
+	 *	indev or outdev is OVS bridge port.
+	 * TODO: Do we need to add route/bridge flag in flow?  This would
+	 * help us to check if we need to find dp with outdev if indev fails
+	 */
+	read_lock_bh(&ovsmgr_ctx.lock);
+	nod = ovsmgr_dp_find_by_dev(flow->indev);
+	if (unlikely(!nod)) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: Couldn't find datapath instance for dev = %s\n", flow, flow->indev->name);
+		return;
+	}
+
+	in_port = ovsmgr_dp_port_find_by_dev(nod, flow->indev);
+	if (!in_port) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: input datapath port instance is not found for dev = %s\n",
+				nod, flow->indev->name);
+		return;
+	}
+
+	out_port = ovsmgr_dp_port_find_by_dev(nod, flow->outdev);
+	if (!out_port) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: output datapath port instance is not found for dev = %s\n",
+				nod, flow->outdev->name);
+		return;
+	}
+
+	in_port_num = in_port->vport_num;
+	out_vport = out_port->vport;
+	read_unlock_bh(&ovsmgr_ctx.lock);
+
+	ovsmgr_dp_flow_key_fill(flow, in_port_num, &key);
+	if (ovs_accel_flow_stats_update(nod->dp, out_vport, &key, stats->pkts, stats->bytes)) {
+		ovsmgr_warn("%px: Couldnt update statistics\n", nod->dp);
+	}
+}
+
+/*
+ * ovsmgr_dp_port_dev_find_by_mac()
+ *	Find egress datapath port, given skb, datapath interface (dev) and flow
+ */
+struct net_device *ovsmgr_dp_port_dev_find_by_mac(struct sk_buff *skb, struct net_device *dev,
+							struct ovsmgr_dp_flow *flow)
+{
+	struct ovsmgr_dp *nod;
+	struct ovsmgr_dp_port *nodp;
+	struct sw_flow *sf;
+	struct net_device *ovs_port;
+	void *dp;
+	uint16_t type;
+
+	read_lock_bh(&ovsmgr_ctx.lock);
+	nod = ovsmgr_dp_find_by_dev(dev);
+	if (!nod) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: Couldn't find datapath instance, dev = %s\n", skb, dev->name);
+		return NULL;
+	}
+
+	nodp = ovsmgr_dp_port_find_by_dev(nod, dev);
+	if (!nodp) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: Couldn't find datapath port instance, dev = %s\n", skb, dev->name);
+		return NULL;
+	}
+
+	if (nodp->vport_type != OVS_VPORT_TYPE_INTERNAL) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: Interface type is not internal, dev = %s\n", skb, dev->name);
+		return NULL;
+	}
+
+	dp = nod->dp;
+	read_unlock_bh(&ovsmgr_ctx.lock);
+
+	if (flow->tuple.ip_version == 4) {
+		type = htons(ETH_P_IP);
+	} else {
+		type = htons(ETH_P_IPV6);
+	}
+
+	sf = ovs_accel_flow_find_by_mac(dp, NULL, dev, flow->smac, flow->dmac, type);
+	if (!sf) {
+		ovsmgr_warn("%px: datapath flow is not found with SMAC: %pM, DMAC: %pM, dev = %s\n",
+				skb, flow->smac, flow->dmac, dev->name);
+		return NULL;
+	}
+
+	/*
+	 * Find the dev by ingress port number
+	 */
+	read_lock_bh(&ovsmgr_ctx.lock);
+	nodp = ovsmgr_dp_port_find_by_num(nod, sf->key.phy.in_port);
+	if (!nodp) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: DP port is not found, port number: %d, dev = %s\n", skb, sf->key.phy.in_port, dev->name);
+		return NULL;
+	}
+
+	ovs_port = nodp->dev;
+	read_unlock_bh(&ovsmgr_ctx.lock);
+
+	return ovs_port;
+}
+
+/*
+ * ovsmgr_dp_port_dev_find()
+ *	Find egress datapath port, given skb and datapath interface (dev)
+ */
+struct net_device *ovsmgr_dp_port_dev_find(struct sk_buff *skb,
+					       struct net_device *dev, struct ovsmgr_dp_flow *flow)
+{
+	struct ovsmgr_dp *nod;
+	struct ovsmgr_dp_port *nodp;
+	struct sw_flow_key key;
+	void *dp;
+	int vport_num;
+
+	read_lock_bh(&ovsmgr_ctx.lock);
+	nod = ovsmgr_dp_find_by_dev(dev);
+	if (!nod) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: Couldn't find datapath instance, dev = %s\n", skb, dev->name);
+		return NULL;
+	}
+
+	nodp = ovsmgr_dp_port_find_by_dev(nod, dev);
+	if (!nodp) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: Couldn't find datapath port instance, dev = %s\n", skb, dev->name);
+		return NULL;
+	}
+
+	if (nodp->vport_type != OVS_VPORT_TYPE_INTERNAL) {
+		read_unlock_bh(&ovsmgr_ctx.lock);
+		ovsmgr_warn("%px: Interface type is not internal, dev = %s\n", skb, dev->name);
+		return NULL;
+	}
+
+	dp = nod->dp;
+	vport_num = nodp->vport_num;
+	read_unlock_bh(&ovsmgr_ctx.lock);
+
+	/*
+	 * Multicast address requires finding the ingress interface through all
+	 * bridge ports
+	 */
+	if (is_multicast_ether_addr(flow->dmac)) {
+		return ovsmgr_dp_mcast_port_dev_find(nod, nodp, flow, skb);
+	}
+
+	ether_addr_copy(flow->smac, dev->dev_addr);
+	ovsmgr_dp_flow_key_fill(flow, vport_num, &key);
+
+	return ovs_accel_egress_dev_find(dp, &key, skb);
+}
+
+/*
+ * ovsmgr_exit()
+ *	Cleanup datapath context
+ */
+void ovsmgr_dp_exit(void)
+{
+	struct ovsmgr_dp *nod, *temp_dp;
+
+	ovs_unregister_accelerator(&ovs_cb);
+	/*
+	 * Cleanup the database.
+	 */
+	write_lock_bh(&ovsmgr_ctx.lock);
+	list_for_each_entry_safe(nod, temp_dp, &ovsmgr_ctx.dp_list, node) {
+		struct ovsmgr_dp_port *nodp, *temp_port;
+
+		list_for_each_entry_safe(nodp, temp_port, &nod->port_list, node) {
+			list_del(&nodp->node);
+			kfree(nodp);
+		}
+
+		list_del(&nod->node);
+		kfree(nod);
+	}
+
+	write_unlock_bh(&ovsmgr_ctx.lock);
+}
+
+/*
+ * ovsmgr_init()
+ *	Initialize datapath context
+ */
+int ovsmgr_dp_init(void)
+{
+	return ovs_register_accelerator(&ovs_cb);
+}
diff --git a/qca-ovsmgr/ovsmgr_priv.h b/qca-ovsmgr/ovsmgr_priv.h
new file mode 100644
index 0000000..6bcb442
--- /dev/null
+++ b/qca-ovsmgr/ovsmgr_priv.h
@@ -0,0 +1,163 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/*
+ * ovsmgr_priv.h
+ */
+#ifndef __OVSMGR_PRIV__H
+#define __OVSMGR_PRIV__H
+
+#include <linux/version.h>
+
+#define OVSMGR_DEBUG_LVL_ERROR 1	/* Turn on debug for an error. */
+#define OVSMGR_DEBUG_LVL_WARN 2		/* Turn on debug for a warning. */
+#define OVSMGR_DEBUG_LVL_INFO 3		/* Turn on debug for information. */
+#define OVSMGR_DEBUG_LVL_TRACE 4	/* Turn on debug for trace. */
+
+/*
+ * Maximum number of VLAN's per port
+ */
+#define OVSMGR_PORT_VLAN_MAX_CNT 32
+
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define ovsmgr_error(s, ...) do { \
+	if (net_ratelimit()) {  \
+		pr_alert("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);  \
+	} \
+} while (0)
+
+#if defined(CONFIG_DYNAMIC_DEBUG)
+/*
+ * Compile messages for dynamic enable/disable
+ */
+#define ovsmgr_info(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define ovsmgr_trace(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+#define ovsmgr_warn(s, ...) pr_debug("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__)
+
+#else
+/*
+ * Statically compile messages at different levels
+ */
+#if (OVSMGR_DEBUG_LEVEL >= OVSMGR_DEBUG_LVL_INFO)
+#define ovsmgr_info(s, ...) pr_notice("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);
+#else
+#define ovsmgr_info(s, ...)
+#endif
+
+#if (OVSMGR_DEBUG_LEVEL >= OVSMGR_DEBUG_LVL_TRACE)
+#define ovsmgr_trace(s, ...) pr_info("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);
+#else
+#define ovsmgr_trace(s, ...)
+#endif
+
+#if (OVSMGR_DEBUG_LEVEL >= OVSMGR_DEBUG_LVL_WARN)
+#define ovsmgr_warn(s, ...) pr_warn("%s[%d]:" s, __func__, __LINE__, ##__VA_ARGS__);
+#else
+#define ovsmgr_warn(s, ...)
+#endif
+#endif /* !CONFIG_DYNAMIC_DEBUG */
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
+#define OVSMGR_KEY_VLAN_TCI(key) (key)->eth.tci
+#else
+#define OVSMGR_KEY_VLAN_TCI(key) (key)->eth.vlan.tci
+#define OVSMGR_KEY_CVLAN_TCI(key) (key)->eth.cvlan.tci
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0))
+#define VLAN_TAG_PRESENT VLAN_CFI_MASK
+#endif
+
+/*
+ * ovsmgr_stats
+ *	Datapath statistics maintained by OVS manager
+ */
+struct ovsmgr_stats {
+	atomic64_t pkts_from_ovs_dp;	/* Number of packets received from OVS datapath */
+	atomic64_t pkts_fwd_pre_flow;	/* Number of packets forwarded to pre flow hook functions*/
+	atomic64_t pkts_fwd_post_flow;	/* Number of packets forwarded to post flow hook functions*/
+};
+
+/*
+ * ovsmgr_ctx
+ *	OVS manager context
+ */
+struct ovsmgr_ctx {
+	struct list_head dp_list;	/* List of data paths */
+	struct list_head dp_hooks;	/* List of registered hooks */
+	rwlock_t lock;			/* Lock to access datapath list */
+	struct dentry *dentry;		/* Debugfs entry for OVS */
+	struct dentry *dentry_file;	/* Debugfs file entry for OVS */
+	struct ovsmgr_stats stats;	/* Pakcet processing statistics. */
+};
+
+/*
+ * ovsmgr_dp_port
+ *	Datapath port details
+ */
+struct ovsmgr_dp_port {
+	struct list_head node;				/* To add to port_list */
+	struct net_device *dev;				/* Port netdev  */
+	struct net_device *master_dev;			/* Master netdev */
+	struct vlan_hdr vlan[OVSMGR_PORT_VLAN_MAX_CNT];	/* VLAN configuration for this port */
+	char master_name[IFNAMSIZ];			/* Master device name */
+	void *vport;					/* OVS datapath port context */
+	int vport_num;					/* OVS datapath port number */
+	enum ovs_vport_type vport_type;			/* OVS datapath port type */
+	bool add_notified;				/* Set to true if port add notifier is sent */
+};
+
+/*
+ * ovsmgr_dp
+ *	Datapath details
+ */
+struct ovsmgr_dp {
+	struct list_head node;		/* To add to dp_list */
+	struct list_head port_list;	/* List of bridge ports */
+	struct net_device *dev;		/* netdev representing data path */
+	void *dp;			/* OVS data path context */
+};
+
+/*
+ * ovsmgr_dp_ctx
+ *	OVS manager context
+ */
+struct ovsmgr_dp_ctx {
+	struct list_head dp_list;	/* List of data paths */
+	rwlock_t lock;			/* Lock to access dp_list */
+};
+
+extern struct ovsmgr_ctx ovsmgr_ctx;
+
+int ovsmgr_dp_init(void);
+void ovsmgr_dp_exit(void);
+int ovsmgr_notifiers_call(struct ovsmgr_notifiers_info *info, unsigned long val);
+void ovsmgr_dp_bridge_interface_stats_update(struct net_device *dev,
+					  uint32_t rx_packets, uint32_t rx_bytes,
+					  uint32_t tx_packets, uint32_t tx_bytes);
+void ovsmgr_dp_flow_stats_update(struct ovsmgr_dp_flow *flow, struct ovsmgr_dp_flow_stats *stats);
+struct net_device *ovsmgr_dp_port_dev_find(struct sk_buff *skb,
+					       struct net_device *dev, struct ovsmgr_dp_flow *flow);
+struct net_device *ovsmgr_dp_port_dev_find_by_mac(struct sk_buff *skb, struct net_device *dev,
+							struct ovsmgr_dp_flow *flow);
+struct net_device *ovsmgr_dp_dev_get_master(struct net_device *dev);
+bool ovsmgr_dp_dev_is_master(struct net_device *dev);
+enum ovsmgr_flow_status ovsmgr_dp_flow_info_get(struct ovsmgr_dp_flow *flow,
+						     struct sk_buff *skb, struct ovsmgr_flow_info *ofi);
+
+#endif /* __OVSMGR_PRIV__H */
diff --git a/qca-ssdk/.gitignore b/qca-ssdk/.gitignore
new file mode 100644
index 0000000..95944c9
--- /dev/null
+++ b/qca-ssdk/.gitignore
@@ -0,0 +1,9 @@
+
+# Ignore general build intermediate files
+Module.symvers
+/build/
+/temp/
+
+
+# don't ignore .gitignore itself
+!.gitignore
diff --git a/qca-ssdk/ChangeLog b/qca-ssdk/ChangeLog
new file mode 100644
index 0000000..547dba4
--- /dev/null
+++ b/qca-ssdk/ChangeLog
@@ -0,0 +1,129 @@
+============================================================
+Changes for SSDK 1.0.3:
+============================================================
+
+* Support HORUS:
+  - Add chip type HORUS and related source code.
+
+
+
+
+============================================================                           
+Changes for SSDK 1.0.4:                                                
+============================================================                           
+                                                
+* Support ISIS:                                                
+  - Add chip type ISIS and related source code.     
+
+
+
+
+============================================================ 
+Changes for SSDK 1.0.5:                                                                         
+============================================================
+                                            
+* Speed up FDB entry next operation.
+* Support linux 2.6.31 version.  
+
+
+
+
+============================================================  
+Changes for SSDK 1.0.6:                                                                         
+============================================================
+                                            
+* New APIs pppoe_session_id_set/get are supported for ISIS chip.
+* Fix parameter speed check bug in API isis_port_speed_set.
+
+
+
+
+============================================================  
+Changes for SSDK 1.0.7:                                                                         
+============================================================
+* Fix address bytes order bug in API _isis_ip6_base_addr_set/get.
+* Change the socket call for user space and kernel communication to nonblocking way.
+* Remove force routing function for ISIS acl action.
+* Add configuration for ISIS register accessing speed up feature in ./config file.
+* Add configuration for ISIS NAT helper feature in ./config.file.
+
+
+
+
+============================================================  
+Changes for SSDK 1.0.8:                                                                         
+============================================================
+* Offer ioctl based method for linux kernel&user space communication
+* Remove some port property logic limitation for ISIS.
+* Remove FDB CRC mode setting in ISIS init.
+* Add some operation mode flag for ISIS NAPT entry next operation.
+* Add some operation mode flag for ISIS NAPT del opertion.
+* Fix one bug for fdb entry extendnext command parsing when shell works at slient mode. 
+* Fix one bug in ISIS ACL rule delete operation(isis_acl_rule_delete).
+* Fix one bug in ISIS queue shapper get operation(isis_rate_queue_shaper_get).
+* Add new API for ISIS MAC based VLAN translation.(isis_port_mac_vlan_xlt_set/isis_port_mac_vlan_xlt_get).
+* Add new API for ISIS add/delete port to/from an exist FDB entry.(isis_fdb_port_add/isis_fdb_port_del).
+* Add new API for ISIS ACL rules active/deactive. (isis_acl_rule_active/isis_acl_rule_deactive).
+* Add new API for ISIS wcmp hash mode setting. (isis_ip_wcmp_hash_mode_set/isis_ip_wcmp_hash_mode_get).
+* Add new API for ISIS host entry aging time setting. (isis_ip_age_time_set/isis_ip_age_time_get).
+* Add new API for ISIS interrupt operation. (isis_intr_mask_set/isis_intr_mask_get/isis_intr_status_get/
+      isis_intr_status_clear/isis_intr_port_link_mask_set/isis_intr_port_link_mask_get/isis_intr_port_link_status_get).
+* Add new API for ISIS port MAC mode setting. (isis_interface_mac_mode_set/isis_interface_mac_mode_get).
+* Add new API for ISIS port PHY mode setting. (isis_interface_phy_mode_set/isis_interface_phy_mode_get).
+* Add new API for ISIS 802.3az setting. (isis_port_3az_status_set/isis_port_3az_status_get).
+* Add new API for ISIS link status getting. (isis_port_link_status_get).
+* Add new API for ISIS MAC TX status setting. (isis_port_txmac_status_set/isis_port_txmac_status_get).
+* Add new API for ISIS MAC RX status setting. (isis_port_rxmac_status_set/isis_port_rxmac_status_get).
+* Add new API for ISIS MAC TX flow control setting. (isis_port_txfc_status_set/isis_port_txfc_status_get).
+* Add new API for ISIS MAC RX flow control setting. (isis_port_rxfc_status_set/isis_port_rxfc_status_get).
+* Add new API for ISIS MAC back pressure setting. (isis_port_bp_status_set/isis_port_bp_status_get).
+* Add new API for ISIS link force mode setting. (isis_port_link_forcemode_set/isis_port_link_forcemode_get).
+* Fix one bug in Giga PHY device autoneg ability setting operation.
+* Makefile change for ISIS NAT helper refactoring.
+
+============================================================
+Changes for SSDK 1.1.x:
+============================================================
+* Add support for QCA833x family (ISISC, S17c).
+* Add support for out-of-band register access through ethernet packets with Atheros header. (S17/S17c)
+* Add IPV6 Hardware Routing (ISISC, S17c).
+* Add new API for set/get status of one ACL rule source filter. (S17c only)
+* Add new API for set/get arl search mode as ivl or svl when vlan invalid. (S17c only)
+* Add new API for interface control:
+fal_interface_fx100_ctrl_set/fal_interface_fx100_ctrl_get/fal_interface_fx100_status_get/fal_interface_fx100_status_set/fal_interface_mac06_exch_get/fal_interface_mac06_exch_set. (S17c only)
+* Add new API for MIB counter:
+fal_mib_port_flush_counters/fal_mib_cpukeep_set/fal_mib_cpukeep_get. (S17c only)
+*Add new API for Misc:
+fal_intr_mask_mac_linkchg_set/fal_intr_mask_mac_linkchg_get/fal_intr_status_mac_linkchg_get/fal_cpu_vid_en_set/fal_cpu_vid_en_get/fal_rtd_pppoe_en_set/fal_rtd_pppoe_en_get/fal_intr_status_mac_linkchg_clear (S17c only)
+* Add new API for nat: nat_prv_base_mask_set/nat_prv_base_mask_get. (S17c only)
+* Add new API for port ctrl:
+fal_port_mac_loopback_set/fal_port_mac_loopback_set. (S17c only)
+* Add new API for port vlan:
+fal_netisolate_set/fal_netisolate_get/fal_eg_trans_filter_bypass_en_set/fal_eg_trans_filter_bypass_en_get. (S17c only)
+* Add new API for QoS:
+fal_qos_port_force_spri_status_set/fal_qos_port_force_spri_status_get/fal_qos_port_force_cpri_status_set/fal_qos_port_force_cpri_status_get. (S17c only)
+* Add new API for Rate limit:
+fal_rate_port_add_rate_byte_set/fal_rate_port_add_rate_byte_get/fal_rate_port_gol_flow_en_set/fal_rate_port_gol_flow_en_get.
+
+============================================================
+Changes for SSDK 1.1.1:
+============================================================
+* Add IGMP mldv2 support
+
+============================================================
+Changes for SSDK 1.1.2:
+============================================================
+* Add API for Trunk support
+* Add API for MAC loopback support
+
+============================================================
+Changes for SSDK 1.1.3:
+============================================================
+* Support CHIP_TYPE=ALL_CHIP
+============================================================
+Changes for SSDK 1.1.3.2:
+============================================================
+* Add hsl_shared_api.h (sync from Perforce server)
+* Add support for Linux Kernel 3.2.0 
+* Add support for LITTLE ENDIAN (especially for HNAT)
+* Add support for ARM CPU
diff --git a/qca-ssdk/Makefile b/qca-ssdk/Makefile
new file mode 100755
index 0000000..3a7f4f6
--- /dev/null
+++ b/qca-ssdk/Makefile
@@ -0,0 +1,54 @@
+include ./config
+
+ifndef PRJ_PATH
+  PRJ_PATH=$(shell pwd)
+endif
+export PRJ_PATH
+
+include ./make/config.mk
+include ./make/tools.mk
+include ./make/$(OS)_opt.mk
+
+SUB_DIR=$(patsubst %/, %, $(dir $(wildcard src/*/Makefile)))
+SUB_LIB=$(subst src/, , $(SUB_DIR))
+
+all: $(BIN_DIR) kslib
+	mkdir -p ./temp/;cd ./temp;cp ../build/bin/ssdk_ks_km.a ./;ar -x ssdk_ks_km.a; cp ../ko_Makefile ./Makefile;
+	make -C $(SYS_PATH) M=$(PRJ_PATH)/temp/ CROSS_COMPILE=$(TOOLPREFIX) modules
+	cp $(PRJ_PATH)/temp/Module.symvers $(PRJ_PATH)/Module.symvers;
+	cp temp/*.ko build/bin;
+	rm -Rf ./temp/*.o ./temp/*.ko ./temp/*.a
+	@echo "---Build [SSDK-$(VERSION)] at $(BUILD_DATE) finished."
+
+kslib:kslib_o
+	$(AR) -r $(BIN_DIR)/$(KS_MOD)_$(RUNMODE).a $(wildcard $(BLD_DIR)/KSLIB/*.o)
+
+kslib_o:
+	$(foreach i, $(SUB_LIB), $(MAKE) MODULE_TYPE=KSLIB -C src/$i all || exit 1;)
+
+uslib:uslib_o
+	$(AR) -r $(BIN_DIR)/$(US_MOD)_$(RUNMODE).a $(wildcard $(BLD_DIR)/USLIB/*.o)
+
+uslib_o:
+	$(foreach i, $(SUB_LIB), $(MAKE) MODULE_TYPE=USLIB -C src/$i all || exit 1;)
+
+shell:uslib shell_o
+	$(CP) $(BLD_DIR)/SHELL/$(SHELLOBJ) $(BIN_DIR)/$(SHELLOBJ)
+	$(STRIP) $(BIN_DIR)/$(SHELLOBJ)
+
+shell_o:
+	$(foreach i, $(SUB_LIB), $(MAKE) MODULE_TYPE=SHELL -C src/$i all || exit 1;)
+
+$(BIN_DIR):
+	$(MKDIR) -p $@
+
+release:
+	@cd make; ./release.sh $(VER)
+
+clean:
+	$(RM) -f $(BLD_DIR)/KSLIB/*
+	$(RM) -f $(BLD_DIR)/USLIB/*
+	$(RM) -f $(BLD_DIR)/SHELL/*
+	$(RM) -f $(BIN_DIR)/*
+	$(RM) -rf temp
+	$(RM) -f Module.symvers
diff --git a/qca-ssdk/app/nathelper/linux/host_helper.c b/qca-ssdk/app/nathelper/linux/host_helper.c
new file mode 100755
index 0000000..e98bcbc
--- /dev/null
+++ b/qca-ssdk/app/nathelper/linux/host_helper.c
@@ -0,0 +1,2253 @@
+/*
+ * Copyright (c) 2012, 2015, 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifdef KVER32
+#include <linux/kconfig.h>
+#include <linux/version.h>
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#endif
+#include <linux/if_arp.h>
+#include <linux/netdevice.h>
+#include <linux/netfilter_arp.h>
+#include <linux/inetdevice.h>
+#include <linux/netfilter_ipv4/ip_tables.h>
+#include <linux/in.h>
+#include <linux/ip.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/icmp.h>
+#ifdef KVER32
+#include <linux/export.h>
+#endif
+#include <net/netfilter/nf_conntrack.h>
+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+#include <linux/if_vlan.h>
+#endif
+#if defined (CONFIG_BRIDGE)
+#include <../net/bridge/br_private.h>
+#endif
+#include <linux/ppp_defs.h>
+#include <linux/filter.h>
+#include <linux/if_pppox.h>
+#include <linux/if_ppp.h>
+#include <linux/ppp_channel.h>
+#include <linux/ppp-comp.h>
+#include <net/sock.h>
+#include <net/route.h>
+#include <net/netevent.h>
+#include <net/ipv6.h>
+#include <net/ip_fib.h>
+#include "hsl_api.h"
+#include "fal_nat.h"
+#include "fal_ip.h"
+#include "fal_fdb.h"
+#include "hsl.h"
+#include "nat_helper.h"
+#include "napt_acl.h"
+#include "lib/nat_helper_hsl.h"
+#include "lib/nat_helper_dt.h"
+#include "hsl_shared_api.h"
+#include <net/addrconf.h>
+
+
+#undef CONFIG_IPV6_HWACCEL
+
+
+#ifdef CONFIG_IPV6_HWACCEL
+#include <net/ndisc.h>
+#include <net/neighbour.h>
+#include <net/netevent.h>
+#include <net/ipv6.h>
+#include <net/ip6_route.h>
+#include <linux/ipv6.h>
+#include <linux/netfilter_ipv6.h>
+#endif
+
+//#define AP136_QCA_HEADER_EN 1
+#define MAC_LEN 6
+#define IP_LEN 4
+#define ARP_HEADER_LEN 8
+
+#define ARP_ENTRY_MAX 128
+
+#define DESS_CHIP_VER	0x14
+#define HOST_PREFIX_MAX	31
+
+/* P6 is used by loop dev. */
+#define S17_P6PAD_MODE_REG_VALUE 0x01000000
+
+#define MULTIROUTE_WR
+
+extern struct net init_net;
+
+//char *nat_lan_dev_list = "eth0.1";
+char nat_lan_dev_list[IFNAMSIZ*4] = "br-lan eth0.1";
+char nat_wan_dev_list[IFNAMSIZ*5] = "eth0.2";
+
+char nat_wan_port = 0x20;
+int setup_wan_if = 0;
+int setup_lan_if=0;
+
+#define NAT_LAN_DEV_VID 1
+#define NAT_WAN_DEV_VID 2
+
+uint32_t nat_lan_vid  = NAT_LAN_DEV_VID;
+uint32_t nat_wan_vid = NAT_WAN_DEV_VID;
+
+
+static int wan_fid = 0xffff;
+static fal_pppoe_session_t pppoetbl = {0};
+static uint32_t pppoe_gwid = 0;
+static char nat_bridge_dev[IFNAMSIZ*4] = "br-lan";
+static uint8_t lanip[4] = {0}, lanipmask[4] = {0}, wanip[4] = {0};
+#ifdef CONFIG_IPV6_HWACCEL
+static struct in6_addr wan6ip = IN6ADDR_ANY_INIT;
+static struct in6_addr lan6ip = IN6ADDR_ANY_INIT;
+#endif
+
+extern int nat_chip_ver;
+
+
+#ifdef ISISC
+struct ipv6_default_route_binding
+{
+    struct in6_addr next_hop;
+    uint32_t nh_entry_id;
+};
+#endif
+
+#ifdef MULTIROUTE_WR
+#define MAX_HOST 8
+struct wan_next_hop
+{
+    u_int32_t host_ip;
+    u_int32_t entry_id;
+    u_int32_t in_acl;
+    u_int32_t in_use;
+    u_int8_t  host_mac[6];
+};
+static struct net_device *multi_route_indev = NULL;
+static struct wan_next_hop wan_nh_ent[MAX_HOST] = {{0}};
+
+#define NAT_BACKGROUND_TASK
+
+#ifdef NAT_BACKGROUND_TASK
+#define NAT_HELPER_MSG_MAX 512
+
+struct bg_ring_buf_cb {
+	unsigned int read_idx;
+	unsigned int write_idx;
+	unsigned int num;
+	unsigned int full_flag;
+	struct nat_helper_bg_msg *buf;
+};
+
+struct bg_task_cb {
+	/*struct semaphore bg_sem;  */   /*trigger thread work*/
+	spinlock_t bg_lock;           /*ring buf access protect*/
+	/*struct task_struct *bg_task;*/
+	struct workqueue_struct *nat_wq;
+	struct bg_ring_buf_cb ring;
+};
+
+enum{
+	NAT_HELPER_ARP_ADD_MSG = 0,
+	NAT_HELPER_ARP_DEL_MSG,
+	NAT_HELPER_IPV6_MSG
+};
+
+struct arp_in_msg {
+	uint8_t mac[ETH_ALEN];
+	char name[IFNAMSIZ]; /* device name */
+	uint32_t ip;
+	struct net_device *in;
+};
+
+struct ipv6_msg {
+	struct sk_buff *skb;
+	struct net_device *in;
+};
+
+
+struct nat_helper_bg_msg {
+	struct work_struct work;
+	uint32_t msg_type;
+	uint16_t sub_type;
+	uint16_t reservd;
+	union {
+		struct arp_in_msg arp_in;
+		struct ipv6_msg   ipv6;
+	};
+};
+
+
+struct bg_task_cb task_cb;
+
+int bg_ring_buf_write(struct nat_helper_bg_msg msg)
+{
+	unsigned int idx = 0;
+
+	spin_lock_bh(&task_cb.bg_lock);
+	
+	if((task_cb.ring).full_flag &&
+		((task_cb.ring).read_idx == (task_cb.ring).write_idx)) {
+		HNAT_PRINTK("ring buf is full!\n");
+		spin_unlock_bh(&task_cb.bg_lock);
+		return -1;
+	}
+	msg.work = (task_cb.ring).buf[(task_cb.ring).write_idx].work;
+	(task_cb.ring).buf[(task_cb.ring).write_idx] = msg;
+	idx = (task_cb.ring).write_idx;
+
+	(task_cb.ring).write_idx = ((task_cb.ring).write_idx+1)%NAT_HELPER_MSG_MAX;
+	if(task_cb.ring.read_idx == task_cb.ring.write_idx)
+		task_cb.ring.full_flag = 1;
+
+	spin_unlock_bh(&task_cb.bg_lock);
+	queue_work(task_cb.nat_wq, &(task_cb.ring).buf[idx].work);
+
+	return 0;
+}
+
+int bg_ring_buf_read(struct nat_helper_bg_msg *msg)
+{
+	spin_lock_bh(&task_cb.bg_lock);
+	task_cb.ring.read_idx = (task_cb.ring.read_idx+1)%NAT_HELPER_MSG_MAX;
+	task_cb.ring.full_flag = 0;
+	spin_unlock_bh(&task_cb.bg_lock);
+
+	return 0;
+}
+
+
+
+#endif
+
+a_uint32_t nat_helper_wan_port_get(void)
+{
+	a_uint32_t i = 0;
+
+	for (i = 0; i < 6; i ++) {
+		if ((nat_wan_port >> i) & 1)
+			break;
+	}
+
+	return i;
+}
+
+static int wan_nh_get(u_int32_t host_ip)
+{
+    int i;
+
+    host_ip = htonl(host_ip);
+
+    for (i=0; i<MAX_HOST; i++)
+    {
+        if ((wan_nh_ent[i].host_ip != 0) && !memcmp(&wan_nh_ent[i].host_ip, &host_ip, 4))
+        {
+            // printk("%s %d\n", __FUNCTION__, __LINE__);
+            // if ((wan_nh_ent[i].entry_id != 0) && (wan_nh_ent[i].in_acl != 1))
+            if (wan_nh_ent[i].in_acl != 1)
+            {
+                wan_nh_ent[i].in_acl = 1;
+
+                return i;
+            }
+            // printk("%s %d\n", __FUNCTION__, __LINE__);
+        }
+        printk("%s %d wan_nh_ent 0x%08x host_ip 0x%08x\n", __FUNCTION__, __LINE__, wan_nh_ent[i].host_ip, host_ip);
+    }
+
+    return -1;
+}
+
+static void wan_nh_add(u_int8_t *host_ip , u_int8_t *host_mac, u_int32_t id)
+{
+    int i;
+
+    for( i = 0 ; i < MAX_HOST ; i++ )
+    {
+        if((wan_nh_ent[i].host_ip != 0) && !memcmp(&wan_nh_ent[i].host_ip, host_ip, 4))
+        {
+            if (host_mac == NULL) break;
+
+            if(!memcmp(&wan_nh_ent[i].host_mac, host_mac,6))
+                return;
+            else
+                break ;
+        }
+
+        if(wan_nh_ent[i].host_ip == 0)
+            break;
+    }
+
+    if (i < MAX_HOST)
+    {
+        if ((wan_nh_ent[i].in_use) && (wan_nh_ent[i].in_acl)) return;
+
+        memcpy(&wan_nh_ent[i].host_ip, host_ip, 4);
+        if (host_mac != NULL)
+        {
+            memcpy(wan_nh_ent[i].host_mac, host_mac, 6);
+            wan_nh_ent[i].entry_id = id;
+            if ((wan_nh_ent[i].in_use) && !(wan_nh_ent[i].in_acl))
+            {
+                droute_add_acl_rules(*(uint32_t *)&lanip, *(uint32_t *)&lanipmask, id);
+                /* set the in_acl flag */
+                wan_nh_ent[i].in_acl = 1;
+            }
+        }
+        else
+        {
+            /* set the in_use flag */
+            wan_nh_ent[i].in_use = 1;
+        }
+        HNAT_PRINTK("%s: ip %08x (%d)\n" ,__func__, wan_nh_ent[i].host_ip, i);
+    }
+}
+
+uint32_t get_next_hop(uint32_t daddr, uint32_t saddr)
+{
+    struct fib_result res;
+#ifdef KVER32
+    struct flowi4 fl =
+    {
+        .flowi4_iif =  multi_route_indev->ifindex,
+        .flowi4_mark = 0,
+        .flowi4_tos = 0,
+        .flowi4_scope = RT_SCOPE_UNIVERSE,
+        .daddr = htonl(daddr),
+        .saddr = htonl(saddr),
+    };
+#else
+    struct flowi fl = { .nl_u = { .ip4_u =
+            {
+                .daddr = daddr,
+                .saddr = saddr,
+                .tos = 0,
+                .scope = RT_SCOPE_UNIVERSE,
+            }
+        },
+        .mark = 0,
+        .iif = multi_route_indev->ifindex
+    };
+#endif
+    struct net    * net = dev_net(multi_route_indev);
+    struct fib_nh *mrnh = NULL;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0))
+    if (fib_lookup(net, &fl, &res) != 0)
+#else
+   if (fib_lookup(net, &fl, &res,0) != 0)
+#endif
+    {
+        return 0;
+    }
+    else
+    {
+        mrnh = res.fi->fib_nh;
+        if (NULL == mrnh)
+        {
+            return 0;
+        }
+    }
+
+    return ntohl(mrnh->nh_gw);
+}
+
+uint32_t napt_set_default_route(fal_ip4_addr_t dst_addr, fal_ip4_addr_t src_addr)
+{
+    sw_error_t rv;
+
+    /* search for the next hop (s) */
+    if (!(get_aclrulemask() & (1 << S17_ACL_LIST_DROUTE)))
+    {
+        if (multi_route_indev && \
+                (nf_athrs17_hnat_wan_type != NF_S17_WAN_TYPE_PPPOE) &&
+                (nf_athrs17_hnat_wan_type != NF_S17_WAN_TYPE_PPPOES0))
+        {
+            uint32_t next_hop = get_next_hop(dst_addr, src_addr);
+
+            HNAT_PRINTK("Next hop: %08x\n", next_hop);
+            if (next_hop != 0)
+            {
+                fal_host_entry_t arp_entry;
+
+                memset(&arp_entry, 0, sizeof(arp_entry));
+                arp_entry.ip4_addr = next_hop;
+                arp_entry.flags = FAL_IP_IP4_ADDR;
+                rv = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &arp_entry);
+                if (rv != SW_OK)
+                {
+                    printk("%s: IP_HOST_GET error... (non-existed host: %08x?) \n", __func__, next_hop);
+                    /* add into the nh_ent */
+                    wan_nh_add((u_int8_t *)&next_hop, (u_int8_t *)NULL, 0);
+                }
+                else
+                {
+                    if (wan_nh_get(next_hop) != -1)
+                        droute_add_acl_rules(*(uint32_t *)&lanip, *(uint32_t *)&lanipmask, arp_entry.entry_id);
+                    else
+                        printk("%s %d\n", __FUNCTION__, __LINE__);
+                }
+            }
+            else
+            {
+                HNAT_PRINTK("no need to set the default route... \n");
+                // set_aclrulemask (S17_ACL_LIST_DROUTE);
+            }
+        }
+        else
+        {
+            printk("multi_route_indev %pK nf_athrs17_hnat_wan_type %d\n", multi_route_indev, nf_athrs17_hnat_wan_type);
+        }
+    }
+    /* end next hop (s) */
+
+    return SW_OK;
+}
+#endif /* MULTIROUTE_WR */
+
+void qcaswitch_hostentry_flush(void)
+{
+    fal_host_entry_t hostentry;
+    sw_error_t ret;
+
+    do
+    {
+        memset(&hostentry, 0, sizeof(fal_host_entry_t));
+        hostentry.entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+        ret = IP_HOST_NEXT (0, FAL_IP_ENTRY_ID_EN, &hostentry);
+        if (SW_OK == ret)
+        {
+            IP_HOST_DEL(0, FAL_IP_ENTRY_IPADDR_EN, &hostentry);
+        }
+    }while (SW_OK == ret);
+
+    return;
+}
+
+#ifdef CONFIG_IPV6_HWACCEL /* only for S17c */
+static struct in6_addr* get_ipv6_default_gateway(void)
+{
+    /* ip_route_output_key can't return correct default nexhop
+     * routes are less than 4 and it only searches in route
+     * hash, not in fib, so use fib_lookup.
+     */
+    struct in6_addr *ip6addr = NULL;
+    struct in6_addr des_addr = IN6ADDR_ANY_INIT;
+    struct rt6_info *rt = rt6_lookup(&init_net, &des_addr, NULL, 0, 0);
+
+    if (rt)
+    {
+        ip6addr = &rt->rt6i_gateway;
+    }
+
+    return ip6addr;
+}
+
+static int add_pppoev6_host_entry(void)
+{
+    struct in6_addr local_lan6ip = IN6ADDR_ANY_INIT;
+    unsigned long  flags;
+    int ppp_sid, ppp_sid2;
+    unsigned char ppp_peer_mac[ETH_ALEN];
+    unsigned char ppp_peer_mac2[ETH_ALEN];
+    a_uint32_t ppp_peer_ip = 0;
+    int wvid;
+    fal_host_entry_t nh_arp_entry;
+    sw_error_t rv;
+    a_uint32_t droute_entry_id = 0;
+    a_bool_t ena;
+    static fal_pppoe_session_t pppoev6_sid_table = {0};
+    struct  in6_addr *next_hop;
+
+    local_irq_save(flags);
+    memcpy(&local_lan6ip, &lan6ip, sizeof(struct in6_addr));
+    ppp_sid2 = nf_athrs17_hnat_ppp_id2;
+    ppp_sid = nf_athrs17_hnat_ppp_id;
+    ppp_peer_ip = nf_athrs17_hnat_ppp_peer_ip;
+    memcpy(ppp_peer_mac, nf_athrs17_hnat_ppp_peer_mac, ETH_ALEN);
+    memcpy(ppp_peer_mac2, nf_athrs17_hnat_ppp_peer_mac2, ETH_ALEN);
+    wvid = wan_fid;
+    local_irq_restore(flags);
+
+    if (NF_S17_WAN_TYPE_PPPOE != nf_athrs17_hnat_wan_type)
+    {
+        return SW_BAD_STATE;
+    }
+
+    if (__ipv6_addr_type(&local_lan6ip) == IPV6_ADDR_ANY)
+    {
+        /* Cannot get lanip6 successfully. */
+        return SW_BAD_STATE;
+    }
+    if (0xffff == wvid)
+    {
+        printk("%s: Cannot get WAN vid!\n", __FUNCTION__);
+        return SW_FAIL;
+    }
+
+    if (0 == nf_athrs17_hnat_ppp_peer_ip)
+    {
+        return SW_FAIL;
+    }
+
+    next_hop = get_ipv6_default_gateway();
+    if (NULL == next_hop)
+    {
+        printk("No IPv6 Gateway!\n");
+        return SW_BAD_STATE;
+    }
+
+    if (0 != ppp_sid)
+    {
+        if ((ppp_sid == ppp_sid2)||(0 == ppp_sid2)) /* v4 and v6 have the same session id */
+        {
+            memset(&nh_arp_entry, 0, sizeof(nh_arp_entry));
+            nh_arp_entry.ip4_addr = ppp_peer_ip;
+            nh_arp_entry.flags = FAL_IP_IP4_ADDR;
+            rv = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &nh_arp_entry);
+            if (rv != SW_OK)
+            {
+                printk("%s: IP_HOST_GET error (0x%08x)\n", __func__, ppp_peer_ip);
+                if (PPPOE_STATUS_GET(0, &ena) != SW_OK)
+                {
+                    if (!ena)
+                    {
+                        if (PPPOE_STATUS_SET(0, A_TRUE) != SW_OK)
+                        {
+                            aos_printk("Cannot enable the PPPoE mode\n");
+                            return SW_FAIL;
+                        }
+                    }
+                }
+                pppoev6_sid_table.session_id = ppp_sid;
+                pppoev6_sid_table.multi_session = 1;
+                pppoev6_sid_table.uni_session = 1;
+                pppoev6_sid_table.entry_id = 0;
+                /* set the PPPoE edit reg (0x2200), and PPPoE session reg (0x5f000) */
+                rv = PPPOE_SESSION_TABLE_ADD(0, &pppoev6_sid_table);
+                if (rv == SW_OK)
+                {
+                    a_int32_t a_entry_id = -1;
+
+                    PPPOE_SESSION_ID_SET(0, pppoev6_sid_table.entry_id, pppoev6_sid_table.session_id);
+                    aos_printk("pppoe session: %d, entry_id: %d\n",
+                               pppoev6_sid_table.session_id, pppoev6_sid_table.entry_id);
+                    /* create the peer host ARP entry */
+                    a_entry_id = arp_hw_add(S17_WAN_PORT, wan_fid, (void *)&ppp_peer_ip, (void *)ppp_peer_mac, 0);
+                    if (a_entry_id >= 0) /* hostentry creation okay */
+                    {
+                        rv = IP_HOST_PPPOE_BIND(0, a_entry_id, pppoev6_sid_table.entry_id, A_TRUE);
+                        if ( rv != SW_OK)
+                        {
+                            aos_printk("IP_HOST_PPPOE_BIND failed (entry: %d, rv: %d)... \n",
+                                       a_entry_id, rv);
+                            PPPOE_SESSION_TABLE_DEL(0, &pppoev6_sid_table);
+                            return SW_FAIL;
+                        }
+                        droute_entry_id = a_entry_id;
+                    }
+                    else
+                    {
+                        PPPOE_SESSION_TABLE_DEL(0, &pppoev6_sid_table);
+                        return SW_FAIL;
+                    }
+                }
+                else
+                {
+                    aos_printk("PPPoE session add failed.. (id: %d)\n",
+                               pppoev6_sid_table.session_id);
+                    aos_printk("rv: %d\n", rv);
+                    return SW_FAIL;
+                }
+            }
+            else
+            {
+                droute_entry_id = nh_arp_entry.entry_id;
+            }
+            ipv6_droute_add_acl_rules(&local_lan6ip, droute_entry_id);
+        }
+        else /* Not the same session id */
+        {
+            if (PPPOE_STATUS_GET(0, &ena) != SW_OK)
+            {
+                if (!ena)
+                {
+                    if (PPPOE_STATUS_SET(0, A_TRUE) != SW_OK)
+                    {
+                        aos_printk("Cannot enable the PPPoE mode\n");
+                        return SW_FAIL;
+                    }
+                }
+            }
+            memset(&nh_arp_entry, 0, sizeof(nh_arp_entry));
+            memcpy((void *)&nh_arp_entry.ip6_addr, (void *)next_hop, sizeof(nh_arp_entry.ip6_addr));
+            nh_arp_entry.flags = FAL_IP_IP6_ADDR;
+            rv = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &nh_arp_entry);
+            if (rv != SW_OK)
+            {
+                /* ARP alread setup. */
+                return SW_OK;
+            }
+            pppoev6_sid_table.session_id = ppp_sid2;
+            pppoev6_sid_table.multi_session = 1;
+            pppoev6_sid_table.uni_session = 1;
+            pppoev6_sid_table.entry_id = 0;
+            /* set the PPPoE edit reg (0x2200), and PPPoE session reg (0x5f000) */
+            rv = PPPOE_SESSION_TABLE_ADD(0, &pppoev6_sid_table);
+            if (rv == SW_OK)
+            {
+                a_int32_t a_entry_id = -1;
+
+                PPPOE_SESSION_ID_SET(0, pppoev6_sid_table.entry_id, pppoev6_sid_table.session_id);
+                aos_printk("pppoe session: %d, entry_id: %d\n",
+                           pppoev6_sid_table.session_id, pppoev6_sid_table.entry_id);
+                /* create the peer host ARP entry */
+                a_entry_id = arp_hw_add(S17_WAN_PORT, wan_fid, (void *)next_hop, ppp_peer_mac2, 1);
+                if (a_entry_id >= 0) /* hostentry creation okay */
+                {
+                    rv = IP_HOST_PPPOE_BIND(0, a_entry_id, pppoev6_sid_table.entry_id, A_TRUE);
+                    if ( rv != SW_OK)
+                    {
+                        aos_printk("IP_HOST_PPPOE_BIND failed (entry: %d, rv: %d)... \n",
+                                   a_entry_id, rv);
+                        PPPOE_SESSION_TABLE_DEL(0, &pppoev6_sid_table);
+                        return SW_FAIL;
+                    }
+                    droute_entry_id = a_entry_id;
+                }
+                else
+                {
+                    PPPOE_SESSION_TABLE_DEL(0, &pppoev6_sid_table);
+                    return SW_FAIL;
+                }
+            }
+            else
+            {
+                aos_printk("PPPoE session add failed.. (id: %d)\n",
+                           pppoev6_sid_table.session_id);
+                aos_printk("rv: %d\n", rv);
+                return SW_FAIL;
+            }
+            ipv6_droute_add_acl_rules(&local_lan6ip, droute_entry_id);
+        }
+    }
+
+    return SW_OK;
+}
+
+uint32_t napt_set_ipv6_default_route(void)
+{
+    sw_error_t rv;
+    static a_bool_t ipv6_droute_setup = A_FALSE;
+    static struct ipv6_default_route_binding ipv6_droute_bind = {IN6ADDR_ANY_INIT,0};
+    struct in6_addr local_lan6ip = IN6ADDR_ANY_INIT;
+    unsigned long  flags;
+
+	if (((nat_chip_ver&0xffff)>>8) == DESS_CHIP_VER)
+		return SW_OK;
+
+    /* search for the next hop (s)*/
+    if (NF_S17_WAN_TYPE_IP == nf_athrs17_hnat_wan_type)
+    {
+        struct  in6_addr *next_hop = get_ipv6_default_gateway();
+
+        // printk("IPv6 next hop: %pI6\n", next_hop);
+
+        if (next_hop != NULL)
+        {
+            fal_host_entry_t ipv6_neigh_entry;
+
+            if (__ipv6_addr_type(next_hop) == IPV6_ADDR_LINKLOCAL)
+                return SW_OK;
+
+            local_irq_save(flags);
+            memcpy(&local_lan6ip, &lan6ip, sizeof(struct in6_addr));
+            local_irq_restore(flags);
+
+            memset(&ipv6_neigh_entry, 0, sizeof(ipv6_neigh_entry));
+            memcpy(&ipv6_neigh_entry.ip6_addr, next_hop, 16);
+            ipv6_neigh_entry.flags = FAL_IP_IP6_ADDR;
+            rv = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &ipv6_neigh_entry);
+            if ((rv != SW_OK)||(__ipv6_addr_type(&local_lan6ip) == IPV6_ADDR_ANY))
+            {
+                if (ipv6_droute_setup)
+                {
+                    ipv6_droute_del_acl_rules();
+                    memset(&ipv6_droute_bind, 0, sizeof(ipv6_droute_bind));
+                    ipv6_droute_setup = A_FALSE;
+                }
+            }
+            else
+            {
+                if (ipv6_droute_setup)
+                {
+                    if (!ipv6_addr_equal(&ipv6_droute_bind.next_hop, next_hop) ||
+                            ipv6_droute_bind.nh_entry_id != ipv6_neigh_entry.entry_id)
+                    {
+                        ipv6_droute_del_acl_rules();
+                    }
+                }
+                ipv6_droute_bind.next_hop = *next_hop;
+                ipv6_droute_bind.nh_entry_id = ipv6_neigh_entry.entry_id;
+
+                ipv6_droute_add_acl_rules(&local_lan6ip, ipv6_neigh_entry.entry_id);
+                ipv6_droute_setup = A_TRUE;
+            }
+        }
+        else
+        {
+            if (ipv6_droute_setup)
+            {
+                ipv6_droute_del_acl_rules();
+                memset(&ipv6_droute_bind, 0, sizeof(ipv6_droute_bind));
+                ipv6_droute_setup = A_FALSE;
+            }
+        }
+    }
+    else if (NF_S17_WAN_TYPE_IP == nf_athrs17_hnat_wan_type)
+    {
+        add_pppoev6_host_entry();
+    }
+
+    return SW_OK;
+}
+#endif /* ifdef CONFIG_IPV6_HWACCEL */
+
+static sw_error_t hnat_add_host_route(
+		fal_ip4_addr_t ip_addr,
+		uint32_t prefix_len)
+{
+	fal_host_route_t host_route;
+
+	memset(&host_route, 0, sizeof(fal_host_route_t));
+
+	IP_HOST_ROUTE_GET(0, 0, &host_route);
+	if ((host_route.route_addr.ip4_addr == ip_addr) &&
+	    (host_route.prefix_length == prefix_len) &&
+	    host_route.valid)
+	    return SW_OK;
+
+	host_route.valid = A_TRUE;
+	host_route.vrf_id = 0;
+	host_route.ip_version = 0;
+	host_route.route_addr.ip4_addr = ip_addr;
+	host_route.prefix_length = prefix_len;
+
+	return IP_HOST_ROUTE_ADD(0, 0, &host_route);
+}
+static sw_error_t setup_interface_entry(char *list_if, int is_wan)
+{
+    char temp[IFNAMSIZ*4]; /* Max 4 interface entries right now. */
+    char *dev_name, *list_all;
+    struct net_device *nat_dev;
+    struct in_device *in_device_lan = NULL, *in_device_wan = NULL;
+    uint8_t *devmac, if_mac_addr[MAC_LEN];
+    char *br_name;
+    uint32_t vid = 0;
+    sw_error_t setup_error;
+    uint32_t ipv6 = 0;
+
+    memcpy(temp, list_if, strlen(list_if)+1);
+    list_all = temp;
+
+    setup_error = SW_FAIL;
+    rcu_read_lock();
+    while ((dev_name = strsep(&list_all, " ")) != NULL)
+    {
+        nat_dev = dev_get_by_name(&init_net, dev_name);
+        if (NULL == nat_dev)
+        {
+            // printk("%s: Cannot get device %s by name!\n", __FUNCTION__, dev_name);
+            setup_error = SW_FAIL;
+            continue;
+        }
+#if defined (CONFIG_BRIDGE)
+#ifdef KVER32
+        if (NULL != br_port_get_rcu(nat_dev)) /* under bridge interface. */
+        {
+            /* Get bridge interface name */
+            br_name = (char *)(br_port_get_rcu(nat_dev)->br->dev->name);
+            if (!is_wan) {
+                strlcat (nat_lan_dev_list, " ", sizeof(nat_lan_dev_list));
+                strlcat (nat_lan_dev_list, br_name, sizeof(nat_lan_dev_list));
+            }
+            /* Get dmac */
+            devmac = (uint8_t *)(br_port_get_rcu(nat_dev)->br->dev->dev_addr);
+        }
+#else
+        if (NULL != nat_dev->br_port) /* under bridge interface. */
+        {
+            /* Get bridge interface name */
+            br_name = (char *)nat_dev->br_port->br->dev->name;
+            //memcpy (nat_bridge_dev, br_name, sizeof(br_name));
+            strcat (nat_lan_dev_list, " ");
+            strcat (nat_lan_dev_list, br_name);
+            /* Get dmac */
+            devmac = (uint8_t *)nat_dev->br_port->br->dev->dev_addr;
+        }
+#endif
+        else
+#endif /* CONFIG_BRIDGE */
+        {
+            devmac = (uint8_t *)nat_dev->dev_addr;
+        }
+        /* get vid */
+#if 0
+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+        vid = vlan_dev_vlan_id(nat_dev);
+#else
+        vid = 0;
+#endif
+#endif
+		if(is_wan)
+			vid = nat_wan_vid;
+		else
+			vid = nat_lan_vid;
+#ifdef CONFIG_IPV6_HWACCEL
+        ipv6 = 1;
+        if (is_wan)
+        {
+            wan_fid = vid;
+        }
+#else
+        ipv6 = 0;
+        if (is_wan)
+        {
+            if (NF_S17_WAN_TYPE_PPPOEV6 == nf_athrs17_hnat_wan_type)
+                ipv6 = 1;
+            wan_fid = vid;
+        }
+#endif
+#ifdef ISISC
+        if (0 == is_wan) /* Not WAN -> LAN */
+        {
+            /* Setup private and netmask as soon as possible */
+            if (br_port_get_rcu(nat_dev)) /* under bridge interface. */
+            {
+                in_device_lan = (struct in_device *) (br_port_get_rcu(nat_dev)->br->dev->ip_ptr);
+            }
+            else
+            {
+                in_device_lan = (struct in_device *) nat_dev->ip_ptr;
+            }
+
+            if ((in_device_lan) && (in_device_lan->ifa_list))
+            {
+                nat_hw_prv_mask_set((a_uint32_t)(in_device_lan->ifa_list->ifa_mask));
+                nat_hw_prv_base_set((a_uint32_t)(in_device_lan->ifa_list->ifa_address));
+#ifndef KVER32
+                printk("Set private base 0x%08x for %s\n", (a_uint32_t)(in_device_lan->ifa_list->ifa_address), nat_dev->br_port->br->dev->name);
+#endif
+                memcpy(&lanip, (void *)&(in_device_lan->ifa_list->ifa_address), 4); /* copy Lan port IP. */
+		memcpy(&lanipmask, (void *)&(in_device_lan->ifa_list->ifa_mask), 4);
+#ifndef ISISC
+                redirect_internal_ip_packets_to_cpu_on_wan_add_acl_rules((a_uint32_t)(in_device_lan->ifa_list->ifa_address),
+                                                                            (a_uint32_t)(in_device_lan->ifa_list->ifa_mask));
+#endif
+            }
+
+            if(setup_lan_if) {
+                dev_put(nat_dev);
+                rcu_read_unlock();
+                return SW_OK;
+            } else {
+                setup_lan_if = 1;
+            }
+        }
+#endif
+        if (1 == is_wan) {
+            if (br_port_get_rcu(nat_dev)) {
+                in_device_wan = (struct in_device *) (br_port_get_rcu(nat_dev)->br->dev->ip_ptr);
+            } else {
+                in_device_wan = (struct in_device *) nat_dev->ip_ptr;
+            }
+            if((nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_IP) &&
+               (in_device_wan) && (in_device_wan->ifa_list))
+            {
+                a_uint32_t index;
+
+                if (((nat_chip_ver&0xffff) >> 8) == DESS_CHIP_VER) {
+                    a_uint32_t ip, len;
+
+                    ip = in_device_wan->ifa_list->ifa_address & in_device_wan->ifa_list->ifa_mask;
+                    ip = ntohl(ip);
+                    len = 32 - ffs(ntohl(in_device_wan->ifa_list->ifa_mask));
+                    hnat_add_host_route(ip, len);
+                }
+                nat_hw_pub_ip_add(ntohl((a_uint32_t)(in_device_wan->ifa_list->ifa_address)),
+                                                &index);
+                HNAT_PRINTK("pubip add 0x%x\n", (a_uint32_t)(in_device_wan->ifa_list->ifa_address));
+        	}
+        }
+        memcpy(if_mac_addr, devmac, MAC_LEN);
+        devmac = if_mac_addr;
+        dev_put(nat_dev);
+
+        if(if_mac_add(devmac, vid, ipv6) != 0)
+        {
+            setup_error = SW_FAIL;
+            continue;
+        }
+        else
+        {
+            setup_error = SW_OK;
+            break;
+        }
+    }
+
+    rcu_read_unlock();
+    return setup_error;
+}
+
+static void setup_dev_list(void)
+{
+	fal_vlan_t entry;
+	uint32_t tmp_vid = 0xffffffff;
+
+	/*get the vlan entry*/
+	while(1) {
+		if(SW_OK != VLAN_NEXT(0, tmp_vid, &entry))
+			break;
+		tmp_vid = entry.vid;
+		if(tmp_vid != 0) {
+			if(entry.mem_ports & nat_wan_port) {
+				/*wan port*/
+				HNAT_PRINTK("wan port vid:%d\n", tmp_vid);
+				nat_wan_vid = tmp_vid;
+				snprintf(nat_wan_dev_list, IFNAMSIZ*5,
+					 "eth0.%d eth1.%d eth0 pppoe-wan erouter0 br-wan",
+					 tmp_vid, tmp_vid);
+			} else {
+				/*lan port*/
+				HNAT_PRINTK("lan port vid:%d\n", tmp_vid);
+				nat_lan_vid = tmp_vid;
+				snprintf(nat_lan_dev_list, IFNAMSIZ*4, "eth0.%d eth1.%d eth1 br-lan",
+					tmp_vid, tmp_vid);
+			}
+		}
+	}
+}
+
+static int setup_all_interface_entry(void)
+{
+    //static int setup_lan_if=0;
+    static int setup_default_vid = 0;
+    int i = 0;
+
+	setup_dev_list();
+
+    if (0 == setup_default_vid)
+    {
+        for (i=0; i<7; i++) /* For AR8327/AR8337, only 7 port */
+        {
+#ifdef NAT_TODO /* need to implement here */
+            PORTVLAN_ROUTE_DEFV_SET(0, i);
+#endif
+        }
+        setup_default_vid = 1;
+    }
+
+    //if (0 == setup_lan_if)
+    {
+#ifdef ISISC
+        //MISC_ARP_CMD_SET(0, FAL_MAC_FRWRD); /* Should be put in init function. */
+#if 0
+        MISC_ARP_SP_NOT_FOUND_SET(0, FAL_MAC_RDT_TO_CPU);
+#endif
+#endif
+        if (SW_OK == setup_interface_entry(nat_lan_dev_list, 0))
+        {
+            //setup_lan_if = 1; /* setup LAN interface entry success */
+            //printk("Setup LAN interface entry done!\n");
+        }
+    }
+
+    if (0 == setup_wan_if)
+    {
+        if (SW_OK == setup_interface_entry(nat_wan_dev_list, 1))
+        {
+            setup_wan_if = 1; /* setup WAN interface entry success */
+        }
+    }
+	if (((nat_chip_ver&0xffff)>>8) == NAT_CHIP_VER_8327) {
+		if ((nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOE) ||
+			(nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6))
+		{
+			uint8_t buf[6];
+
+			memcpy(buf, nf_athrs17_hnat_ppp_peer_mac, ETH_ALEN);
+			HNAT_PRINTK("Peer MAC: %s ", buf);
+			/* add the peer interface with VID */
+			if_mac_add(buf, wan_fid, 0);
+			HNAT_PRINTK(" --> (%.2x-%.2x-%.2x-%.2x-%.2x-%.2x)\n", \
+				buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+			memcpy(&wanip, (void *)&nf_athrs17_hnat_wan_ip, 4);
+		}
+	}
+
+    return 1;
+}
+
+/* check for pppoe session change */
+static void isis_pppoe_check_for_redial(void)
+{
+    if (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_IP)
+        return;
+
+    if(((nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOE) \
+            || (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6)) \
+            && (pppoetbl.session_id != 0))
+    {
+        if(pppoetbl.session_id != nf_athrs17_hnat_ppp_id)
+        {
+            aos_printk("%s: PPPoE session ID changed... \n", __func__);
+            if (nf_athrs17_hnat_wan_type != NF_S17_WAN_TYPE_PPPOEV6)
+            {
+                if (PPPOE_SESSION_TABLE_DEL(0, &pppoetbl) != SW_OK)
+                {
+                    aos_printk("delete old pppoe session %d entry_id %d failed.. \n", pppoetbl.session_id, pppoetbl.entry_id);
+                    return;
+                }
+
+                /* force PPPoE parser for multi- and uni-cast packets; for v1.0.7+ */
+                pppoetbl.session_id = nf_athrs17_hnat_ppp_id;
+                pppoetbl.multi_session = 1;
+			if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8327)
+				pppoetbl.uni_session = 1;
+			else
+                		pppoetbl.uni_session = 0;
+                pppoetbl.entry_id = 0;
+                /* set the PPPoE edit reg (0x2200), and PPPoE session reg (0x5f000) */
+                if (PPPOE_SESSION_TABLE_ADD(0, &pppoetbl) == SW_OK)
+                {
+                    PPPOE_SESSION_ID_SET(0, pppoetbl.entry_id, pppoetbl.session_id);
+                    printk("%s: new pppoe session id: %x, entry_id: %x\n", __func__, pppoetbl.session_id, pppoetbl.entry_id);
+                }
+            }
+            else  /* nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6 */
+            {
+                /* reset the session Id only */
+                aos_printk("IPV6 PPPOE mode... \n");
+                pppoetbl.session_id = nf_athrs17_hnat_ppp_id;
+                PPPOE_SESSION_ID_SET(0, pppoetbl.entry_id, pppoetbl.session_id);
+                printk("%s: new pppoe session id: %x, entry_id: %x\n", __func__, pppoetbl.session_id, pppoetbl.entry_id);
+            }
+            /* read back the WAN IP */
+            memcpy(&wanip, (void *)&nf_athrs17_hnat_wan_ip, 4);
+            aos_printk("Read the WAN IP back... %.8x\n", *(uint32_t *)&wanip);
+            /* change the PPPoE ACL to ensure the packet is correctly forwarded by the HNAT engine */
+            pppoe_add_acl_rules(*(uint32_t *)&wanip, *(uint32_t *)&lanip,
+            						*(uint32_t *)&lanipmask, pppoe_gwid);
+        }
+    }
+}
+
+#ifdef ISIS /* only for S17 */
+static void pppoev6_mac6_loop_dev(void)
+{
+#define PPPOEV6_SESSION_ID  0xfffe
+    fal_pppoe_session_t ptbl;
+	sw_error_t rv;
+	a_uint32_t entry;
+
+    memset(&ptbl, 0, sizeof(fal_pppoe_session_t));
+
+    aos_printk("%s: set MAC6 as loopback device\n", __func__);
+
+    ptbl.session_id = PPPOEV6_SESSION_ID;
+    ptbl.multi_session = 1;
+    ptbl.uni_session = 1;
+    ptbl.entry_id = 0xe;
+
+    /* set the PPPoE edit reg (0x2200), and PPPoE session reg (0x5f000) */
+    if (PPPOE_SESSION_TABLE_ADD(0, &ptbl) == SW_OK)
+    {
+        PPPOE_SESSION_ID_SET(0, ptbl.entry_id, ptbl.session_id);
+        aos_printk("%s: pppoe session id: %d added into entry: %d \n", __func__, ptbl.session_id, ptbl.entry_id);
+    }
+    else
+    {
+        aos_printk("%s: failed on adding pppoe session id: %d\n", __func__, ptbl.session_id);
+    }
+
+    /* PPPoE entry 0 */
+	entry = PPPOEV6_SESSION_ID;
+	REG_ENTRY_SET(rv, 0, PPPOE_EDIT, 0, (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+
+    aos_printk("%s: end of function... \n", __func__);
+}
+
+static void pppoev6_remove_parser(uint32_t entry_id)
+{
+	sw_error_t rv;
+	a_uint32_t entry;
+	
+    aos_printk("%s: clear entry id: %d\n", __func__, entry_id);
+    /* clear the session id in the PPPoE parser engine */
+	entry = 0;
+	REG_ENTRY_SET(rv, 0, PPPOE_SESSION,
+					entry_id, (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+}
+
+#if 0
+static void pppoev6_mac6_stop_learning(void)
+{
+    /* do not disable this port if some other registers are already filled in
+       to prevent setting conflict */
+    int val = S17_P6PAD_MODE_REG_VALUE;
+	sw_error_t rv;
+	a_uint32_t entry;
+
+    if ( val != (1<<24))
+    {
+        aos_printk("%s: MAC 6 already being used!\n", __FUNCTION__);
+        return;
+    }
+
+
+    /* clear the MAC6 learning bit */
+	REG_ENTRY_GET(rv, 0, PORT_LOOKUP_CTL, 6, (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+	entry = entry & ~(1<<20);
+	REG_ENTRY_SET(rv, 0, PORT_LOOKUP_CTL, 6, (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+
+    /* force loopback mode */
+	entry = 0x7e;
+	REG_ENTRY_SET(rv, 0, PORT_STATUS, 6, (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+	entry = 0x10;
+	REG_ENTRY_SET(rv, 0, PORT_HDR_CTL, 6, (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+}
+#endif
+#endif // ifdef ISIS
+
+static int add_pppoe_host_entry(uint32_t sport, a_int32_t arp_entry_id)
+{
+    a_bool_t ena;
+    int rv = SW_OK;
+    fal_host_entry_t nh_arp_entry;
+
+    if (0xffff == wan_fid)
+    {
+        printk("%s: Cannot get WAN vid!\n", __FUNCTION__);
+        return SW_FAIL;
+    }
+
+    if (PPPOE_STATUS_GET(0, &ena) != SW_OK)
+    {
+        aos_printk("Cannot get the PPPoE mode\n");
+        ena = 0;
+    }
+
+    memset(&nh_arp_entry, 0, sizeof(nh_arp_entry));
+    nh_arp_entry.ip4_addr = ntohl(nf_athrs17_hnat_ppp_peer_ip);
+    nh_arp_entry.flags = FAL_IP_IP4_ADDR;
+    rv = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &nh_arp_entry);
+    if (SW_OK != rv || pppoetbl.session_id != nf_athrs17_hnat_ppp_id)
+    {
+        if ((!ena) && (PPPOE_STATUS_SET(0, A_TRUE) != SW_OK))
+            aos_printk("Cannot enable the PPPoE mode\n");
+
+        aos_printk("PPPoE enable mode: %d\n", ena);
+
+        pppoetbl.session_id = nf_athrs17_hnat_ppp_id;
+        pppoetbl.multi_session = 1;
+		if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8327)
+			pppoetbl.uni_session = 1;
+		else
+        		pppoetbl.uni_session = 0;
+        pppoetbl.entry_id = 0;
+
+        /* set the PPPoE edit reg (0x2200), and PPPoE session reg (0x5f000) */
+        rv = PPPOE_SESSION_TABLE_ADD(0, &pppoetbl);
+        if (rv == SW_OK)
+        {
+            uint8_t mbuf[6], ibuf[4];
+            a_int32_t a_entry_id = -1;
+			a_uint32_t index;
+
+            PPPOE_SESSION_ID_SET(0, pppoetbl.entry_id, pppoetbl.session_id);
+            aos_printk("pppoe session: %d, entry_id: %d\n", pppoetbl.session_id, pppoetbl.entry_id);
+
+            if (((nat_chip_ver&0xffff)>>8) == DESS_CHIP_VER) {
+                hnat_add_host_route(ntohl(nf_athrs17_hnat_wan_ip),
+				HOST_PREFIX_MAX);
+            }
+
+            /* create the peer host ARP entry */
+            memcpy(ibuf, (void *)&nf_athrs17_hnat_ppp_peer_ip, 4);
+            memcpy(mbuf, nf_athrs17_hnat_ppp_peer_mac, ETH_ALEN);
+
+            a_entry_id = arp_hw_add(S17_WAN_PORT, wan_fid, ibuf, mbuf, 0);
+            if (a_entry_id >= 0) /* hostentry creation okay */
+            {
+                aos_printk("(1)Bind PPPoE session ID: %d, entry_id: %d to host entry: %d\n", \
+                           pppoetbl.session_id, pppoetbl.entry_id, a_entry_id);
+
+                rv = IP_HOST_PPPOE_BIND(0, a_entry_id, pppoetbl.entry_id, A_TRUE);
+                if ( rv != SW_OK)
+                {
+                    aos_printk("IP_HOST_PPPOE_BIND failed (entry: %d, rv: %d)... \n", a_entry_id, rv);
+                }
+
+                aos_printk("adding ACLs \n");
+                pppoe_gwid = a_entry_id;
+			pppoe_add_acl_rules(nf_athrs17_hnat_wan_ip, *(uint32_t *)&lanip,
+								*(uint32_t *)&lanipmask, a_entry_id);
+			nat_hw_pub_ip_add(ntohl(nf_athrs17_hnat_wan_ip), &index);
+                aos_printk("ACL creation okay... \n");
+            } else {
+			HNAT_PRINTK("pppoe arp add fail!\n");
+            }
+        }
+        else
+        {
+            aos_printk("PPPoE session add failed.. (id: %d)\n", pppoetbl.session_id);
+            aos_printk("rv: %d\n", rv);
+        }
+
+#ifdef ISIS
+        if (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6)
+        {
+            aos_printk("IPV6 PPPOE mode... (share the same ID with IPV4's)\n");
+            pppoev6_mac6_loop_dev();
+            pppoev6_remove_parser(pppoetbl.entry_id);
+
+            /* bind the first LAN host to the pseudo PPPoE ID */
+            rv = IP_HOST_PPPOE_BIND(0, arp_entry_id, 0, A_TRUE);
+            if ( rv != SW_OK)
+            {
+                aos_printk("IP_HOST_PPPOE_BIND failed (entry: %d, rv: %d)... \n", arp_entry_id, rv);
+            }
+        }
+#endif // ifdef ISIS
+    }
+#ifdef ISIS
+    else  /* ena */
+    {
+        if ((nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6) &&
+                (sport != S17_WAN_PORT)&& (arp_entry_id != 0))
+        {
+            aos_printk("IPV6 PPPoE mode\n");
+            /* bind LAN hosts to the pseudo PPPoE ID */
+            rv = IP_HOST_PPPOE_BIND(0, arp_entry_id, 0, A_TRUE);
+            if ( rv != SW_OK)
+            {
+                aos_printk("IP_HOST_PPPOE_BIND failed (entry: %d, rv: %d)... \n", arp_entry_id, rv);
+            }
+        }
+    }
+#endif // ifdef ISIS
+
+    return SW_OK;
+}
+
+static int
+dev_check(char *in_dev, char *dev_list)
+{
+    char *list_dev;
+    char temp[100] = {0};
+    char *list;
+
+    if(!in_dev || !dev_list)
+    {
+        return 0;
+    }
+
+    strlcpy(temp, dev_list, sizeof(temp));
+    list = temp;
+
+    while ((list_dev = strsep(&list, " ")) != NULL)
+    {
+        HNAT_PRINTK("%s: strlen:%d list_dev:%s in_dev:%s\n",
+                    __func__, strlen(list_dev), list_dev, in_dev);
+
+        if (!strncmp(list_dev, in_dev, strlen(list_dev)))
+        {
+            HNAT_PRINTK("%s: %s\n", __FUNCTION__, list_dev);
+            return 1;
+        }
+    }
+
+    return 0;
+}
+
+#ifndef ISISC
+static uint32_t get_netmask_from_netdevice(const struct net_device *in_net_dev)
+{
+    struct in_device *my_in_device = NULL;
+    uint32_t result = 0xffffff00;
+
+    if((in_net_dev) && (in_net_dev->ip_ptr != NULL))
+    {
+        my_in_device = (struct in_device *)(in_net_dev->ip_ptr);
+        if(my_in_device->ifa_list != NULL)
+        {
+            result = my_in_device->ifa_list->ifa_mask;
+        }
+    }
+
+    return result;
+}
+#endif
+
+
+static void hnat_add_neigh(struct neighbour *neigh) 
+{
+	struct nat_helper_bg_msg msg;
+	struct net_device *dev = NULL;
+
+	memset(&msg, 0, sizeof(msg));
+	msg.arp_in.ip = *((uint32_t *)neigh->primary_key);
+	memcpy(msg.arp_in.mac, neigh->ha, ETH_ALEN);
+	strlcpy(msg.arp_in.name, neigh->dev->name, IFNAMSIZ);
+	msg.arp_in.in = neigh->dev;
+
+	if (neigh->dev->priv_flags & IFF_EBRIDGE) {
+		if (!(dev = br_port_dev_get(neigh->dev, neigh->ha, NULL, 0))) {
+			HNAT_ERR_PRINTK("Failed to find bridge port by [%pM]\n",
+				neigh->ha);
+			return ;
+		}
+	} else {
+		dev = neigh->dev;
+		dev_hold(dev);
+	}
+
+	if (strncmp(dev->name, "eth", strlen("eth")) &&
+	     strncmp(dev->name, "erouter", strlen("erouter"))) {
+		dev_put(dev);
+		return ;
+	}
+
+	dev_put(dev);
+
+	msg.msg_type = NAT_HELPER_ARP_ADD_MSG;
+	bg_ring_buf_write(msg);
+}
+
+static void hnat_del_neigh(struct neighbour *neigh)
+{
+	struct nat_helper_bg_msg msg;
+
+	memset(&msg, 0, sizeof(msg));
+	msg.arp_in.ip  = ntohl(*((uint32_t *)neigh->primary_key));
+
+	msg.msg_type = NAT_HELPER_ARP_DEL_MSG;
+	bg_ring_buf_write(msg);
+}
+
+static int hnat_netevent_event(struct notifier_block *unused, unsigned long event, void *ptr)
+{
+	struct neigh_table *tbl;
+	struct neighbour *neigh;
+
+	if (event != NETEVENT_NEIGH_UPDATE)
+		return NOTIFY_DONE;
+
+	neigh = ptr;
+	tbl = neigh->tbl;
+
+	if (tbl->family != AF_INET)
+		return NOTIFY_DONE;
+
+	HNAT_PRINTK("netevent state %d for ip[%pI4]\n",
+		neigh->nud_state, (uint32_t *)neigh->primary_key);
+
+	if (neigh->nud_state & NUD_VALID) {
+		if (neigh->nud_state & NUD_NOARP) {
+			return NOTIFY_DONE;
+		}
+
+		HNAT_PRINTK("New ARP entry ip[%pI4] mac[%pM]\n",
+			(uint32_t *)neigh->primary_key, neigh->ha);
+		hnat_add_neigh(neigh);
+	} else {
+		HNAT_PRINTK("Del ARP entry ip[%pI4] mac[%pM] with status[%d]\n",
+			(uint32_t *)neigh->primary_key, neigh->ha, neigh->nud_state);
+		hnat_del_neigh(neigh);
+	}
+
+	return NOTIFY_DONE;	
+}
+
+#ifdef NAT_BACKGROUND_TASK
+static unsigned int
+arp_del(struct nat_helper_bg_msg *msg)
+{
+	fal_host_entry_t host;
+
+	memset(&host, 0, sizeof(host));
+
+	if (!nat_hw_prv_base_is_match(msg->arp_in.ip))
+		return 0;
+
+	if (napt_hw_get_by_sip(msg->arp_in.ip)) {
+		host.flags |= FAL_IP_IP4_ADDR;
+		host.ip4_addr = msg->arp_in.ip;
+		IP_HOST_DEL(0, FAL_IP_ENTRY_IPADDR_EN, &host);
+	}
+
+	return 0;
+}
+
+static unsigned int
+arp_add(struct nat_helper_bg_msg *msg)
+{
+    uint8_t *smac;
+    uint8_t dev_is_lan = 0;
+    uint32_t sport = 0, vid = 0;
+    a_bool_t prvbasemode = 1;
+    sw_error_t rv = SW_OK;
+    struct arp_in_msg *arp_info = &msg->arp_in;
+    a_int32_t arp_entry_id = -1;
+    fal_fdb_entry_t entry;
+
+
+    /* check for PPPoE redial here, to reduce overheads */
+    isis_pppoe_check_for_redial();
+
+    /* do not write out host table if HNAT is disabled */
+    if (!nf_athrs17_hnat)
+        return 0;
+
+    setup_all_interface_entry();
+
+    if(dev_check((char *)arp_info->name, (char *)nat_wan_dev_list))
+    {
+
+    }
+    else if (dev_check((char *)arp_info->name, (char *)nat_lan_dev_list))
+    {
+        dev_is_lan = 1;
+    }
+    else
+    {
+        HNAT_INFO_PRINTK("Not Support device: %s\n",  (char *)arp_info->name);
+        return 0;
+    }
+
+    if(dev_is_lan) {
+         vid = nat_lan_vid;
+    } else {
+         vid = nat_wan_vid;
+    }
+
+    memset(&entry, 0, sizeof(entry));
+
+    entry.fid = vid;
+
+    smac = arp_info->mac;
+    aos_mem_copy(&(entry.addr), smac, sizeof(fal_mac_addr_t));
+    if(FDB_ENTRY_SEARCH(0, &entry) == SW_OK) {
+        vid  = entry.fid;
+        sport = 0;
+        while (sport < 32) {
+            if(entry.port.map & (1 << sport)) {
+                break;
+            }
+            sport++;
+        }
+    } else {
+        HNAT_PRINTK("not find the FDB entry\n");
+    }
+
+
+    if (sport == 0) {
+        HNAT_PRINTK("Not the expected arp, ignore it!\n");
+        return 0;
+    }
+
+    arp_entry_id = arp_hw_add(sport, vid, (a_uint8_t *)&arp_info->ip, smac, 0);
+    if(arp_entry_id < 0)
+    {
+        HNAT_ERR_PRINTK("ARP entry error!!\n");
+        return 0;
+    }
+
+    if (0 == dev_is_lan)
+    {
+        struct in_device *in_dev;
+
+        in_dev = __in_dev_get_rtnl(arp_info->in);
+        if (in_dev) {
+            if (in_dev->ifa_list) {
+                *(uint32_t *)&wanip = ntohl(in_dev->ifa_list->ifa_local);
+            }
+        }
+#ifdef MULTIROUTE_WR
+        wan_nh_add((u_int8_t *)&arp_info->ip, smac, arp_entry_id);
+#endif
+    }
+
+    if(dev_is_lan && nat_hw_prv_base_can_update())
+    {
+        nat_hw_flush();
+        nat_hw_prv_base_update_disable();
+#ifdef MULTIROUTE_WR
+        //multi_route_indev = in;
+#endif
+    }
+    multi_route_indev = arp_info->in;
+
+    if ((nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOE) ||
+            (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6))
+    {
+        add_pppoe_host_entry(sport, arp_entry_id);
+    }
+
+	if (((nat_chip_ver & 0xffff)>>8) != NAT_CHIP_VER_8327)
+		return 1;
+
+    /* check for SIP and DIP range */
+    if ((lanip[0] != 0) && (wanip[0] != 0))
+    {
+	 rv = NAT_PRV_ADDR_MODE_GET(0, &prvbasemode);
+	 if (rv == SW_NOT_SUPPORTED || rv == SW_NOT_INITIALIZED) {
+		 return 1;
+	 }
+	 else if (rv != SW_OK) {
+		 aos_printk("Private IP base mode check failed: %d\n", prvbasemode);
+	 }
+
+        if (!prvbasemode) /* mode 0 */
+        {
+            if ((lanip[0] == wanip[0]) && (lanip[1] == wanip[1]))
+            {
+                if ((lanip[2] & 0xf0) == (wanip[2] & 0xf0))
+                {
+                    if (get_aclrulemask()& (1 << S17_ACL_LIST_IPCONF))
+                        return 0;
+
+                    aos_printk("LAN IP and WAN IP conflict... \n");
+                    /* set h/w acl to filter out this case */
+#ifdef MULTIROUTE_WR
+                    // if ( (wan_nh_ent[0].host_ip != 0) && (wan_nh_ent[0].entry_id != 0))
+                    if ( (wan_nh_ent[0].host_ip != 0))
+                        ip_conflict_add_acl_rules(*(uint32_t *)&wanip, *(uint32_t *)&lanip, wan_nh_ent[0].entry_id);
+#endif
+                    return 0;
+                }
+            }
+        }
+        else  /* mode 1*/
+        {
+            ;; /* do nothing */
+        }
+    }
+
+    return 1;
+}
+#endif
+
+static struct notifier_block hnat_netevent_notifier = {
+	.notifier_call = hnat_netevent_event,
+};
+
+#ifdef AUTO_UPDATE_PPPOE_INFO
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0))
+struct prv_ppp_file {
+	int		k;
+	struct sk_buff_head xmitq;
+	struct sk_buff_head recvq;
+	wait_queue_head_t wait;
+	atomic_t	cnt;
+	int		hlen;
+	int		idx;
+	int		d;
+};
+struct prv_ppp {
+	struct prv_ppp_file	file;
+	char	*o;
+	struct list_head channels;
+	int		n_channels;
+	spinlock_t	rlock;
+	spinlock_t	wlock;
+	int		m;
+	unsigned int	flags;
+	unsigned int	xmitstate;
+	unsigned int	recvstate;
+	int		d;
+	char *vj;
+	int	mode[6];
+	struct sk_buff	*xpending;
+	char *xcmp;
+	void		*xstate;
+	char *rcmp;
+	void		*rstate;
+	unsigned long	l_xmit;
+	unsigned long	l_recv;
+	struct net_device *dev;
+	int		resv1;
+#ifdef CONFIG_PPP_MULTILINK
+	int		resv2;
+	u32		resv3;
+	int		resv4;
+	u32		resv5;
+	u32		resv6;
+	struct sk_buff_head rq;
+#endif /* CONFIG_PPP_MULTILINK */
+#ifdef CONFIG_PPP_FILTER
+	char *p_filter;
+	char *a_filter;
+	unsigned p_len, a_len;
+#endif /* CONFIG_PPP_FILTER */
+	char	*pnet;
+};
+
+struct prv_channel {
+	struct prv_ppp_file	file;
+	struct list_head list;
+	struct ppp_channel *chan;
+	struct rw_semaphore sem;
+	spinlock_t	downlock;
+	struct prv_ppp	*ppp;
+	char	*cnet;
+	struct list_head clist;
+	rwlock_t	uplock;
+#ifdef CONFIG_PPP_MULTILINK
+	u8		resv1;
+	u8		resv2;
+	u32		resv3;
+	int		resv4;
+#endif
+};
+#endif
+
+static int qcaswitch_pppoe_ip_event(struct notifier_block *this,
+                                    unsigned long event, void *ptr)
+{
+    struct in_ifaddr *ifa = (struct in_ifaddr *)ptr;
+    struct net_device *dev = (struct net_device *)ifa->ifa_dev->dev;
+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0))
+	struct list_head *list;
+	struct prv_channel *pch;
+	struct prv_ppp *ppp = netdev_priv(dev);
+	#endif
+    struct sock *sk;
+    struct pppox_sock *po;
+    static int connection_count = 0;
+    fal_pppoe_session_t del_pppoetbl;
+	int channel_count;
+	struct ppp_channel *ppp_chan[1];
+	int channel_protocol;
+
+    if (!((dev->type == ARPHRD_PPP) && (dev->flags & IFF_POINTOPOINT)))
+        return NOTIFY_DONE;
+
+    if (dev_net(dev) != &init_net)
+        return NOTIFY_DONE;
+
+    setup_all_interface_entry();
+
+    switch (event)
+    {
+        case NETDEV_UP:
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+            if (ppp_is_multilink(dev) == 0) {
+                /* not doing multilink: send it down the first channel */
+			channel_count = ppp_hold_channels(dev, ppp_chan, 1);
+			if (channel_count != 1)
+				return NOTIFY_DONE;
+
+			channel_protocol = ppp_channel_get_protocol(ppp_chan[0]);
+			if (channel_protocol == PX_PROTO_OE)
+			{
+				if (ppp_chan[0]->private)
+				{
+					/* the NETDEV_UP event will be sent many times
+					* because of ifa operation ifa->ifa_local != ifa->ifa_address
+					* means that remote ip is really added.
+					*/
+					if (ifa->ifa_local == ifa->ifa_address)
+					{
+						ppp_release_channels(ppp_chan, 1);
+						return NOTIFY_DONE;
+					}
+					sk = (struct sock *)(ppp_chan[0]->private);
+					po = (struct pppox_sock*)sk;
+					connection_count++;
+					if (((NF_S17_WAN_TYPE_PPPOE == nf_athrs17_hnat_wan_type) &&
+					(0 != nf_athrs17_hnat_ppp_id))) /* another session for IPv6 */
+					{
+						nf_athrs17_hnat_ppp_id2 = ntohs(po->proto.pppoe.pa.sid);
+						memcpy(nf_athrs17_hnat_ppp_peer_mac2,
+							po->proto.pppoe.pa.remote, ETH_ALEN);
+					} else {
+						nf_athrs17_hnat_wan_type = NF_S17_WAN_TYPE_PPPOE;
+						nf_athrs17_hnat_wan_ip = ifa->ifa_local;
+						nf_athrs17_hnat_ppp_peer_ip = ifa->ifa_address;
+						memcpy(nf_athrs17_hnat_ppp_peer_mac,
+							po->pppoe_pa.remote, ETH_ALEN);
+						nf_athrs17_hnat_ppp_id = ntohs(po->pppoe_pa.sid);
+					}
+					ppp_release_channels(ppp_chan, 1);
+				} else {
+					ppp_release_channels(ppp_chan, 1);
+					/* channel got unregistered */
+					return NOTIFY_DONE;
+				}
+			} else {
+				ppp_release_channels(ppp_chan, 1);
+				/* channel got unregistered */
+				return NOTIFY_DONE;
+			}
+		}
+	#else
+		//struct prv_ppp *ppp = netdev_priv(dev);
+		//struct prv_channel *pch;
+		list = &ppp->channels;
+		if (list_empty(list))
+                return NOTIFY_DONE;
+		if ((ppp->flags & SC_MULTILINK) == 0) {
+			list = list->next;
+			pch = list_entry(list, struct prv_channel, clist);
+			if (pch->chan)
+			{
+				if (pch->chan->private) {
+					if (ifa->ifa_local == ifa->ifa_address)
+						return NOTIFY_DONE;
+					sk = (struct sock *)pch->chan->private;
+					po = (struct pppox_sock*)sk;
+					connection_count++;
+					if (((NF_S17_WAN_TYPE_PPPOE == nf_athrs17_hnat_wan_type) &&
+						(0 != nf_athrs17_hnat_ppp_id)))
+					{
+						nf_athrs17_hnat_ppp_id2 = po->num;
+						memcpy(nf_athrs17_hnat_ppp_peer_mac2, po->pppoe_pa.remote, ETH_ALEN);
+					}
+					else
+					{
+						nf_athrs17_hnat_wan_type = NF_S17_WAN_TYPE_PPPOE;
+						nf_athrs17_hnat_wan_ip = ifa->ifa_local;
+		                            nf_athrs17_hnat_ppp_peer_ip = ifa->ifa_address;
+		                            memcpy(nf_athrs17_hnat_ppp_peer_mac, po->pppoe_pa.remote, ETH_ALEN);
+		                            nf_athrs17_hnat_ppp_id = ntohs(po->pppoe_pa.sid);
+					}
+				}
+			}
+			else
+			{
+				return NOTIFY_DONE;
+			}
+		}
+	#endif
+		break;
+
+        case NETDEV_DOWN:
+            if (NF_S17_WAN_TYPE_PPPOE != nf_athrs17_hnat_wan_type)
+            {
+                return NOTIFY_DONE;
+            }
+            connection_count--;
+            if (ifa->ifa_local == nf_athrs17_hnat_wan_ip)
+            {
+                /* PPPoE Interface really down */
+                ipv6_droute_del_acl_rules();
+                del_pppoetbl.session_id = nf_athrs17_hnat_ppp_id;
+                del_pppoetbl.multi_session = 1;
+			if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8327)
+				del_pppoetbl.uni_session = 1;
+			else
+                		del_pppoetbl.uni_session = 0;
+                del_pppoetbl.entry_id = 0;
+                PPPOE_SESSION_TABLE_DEL(0, &del_pppoetbl);
+		memset(&pppoetbl, 0, sizeof(pppoetbl));
+                nf_athrs17_hnat_wan_type = NF_S17_WAN_TYPE_IP;
+                nf_athrs17_hnat_wan_ip = 0;
+                nf_athrs17_hnat_ppp_peer_ip = 0;
+                nf_athrs17_hnat_ppp_id = 0;
+                memset(&nf_athrs17_hnat_ppp_peer_mac, 0, ETH_ALEN);
+            }
+            else
+            {
+                if (0 != nf_athrs17_hnat_ppp_id2)
+                {
+                    del_pppoetbl.session_id = nf_athrs17_hnat_ppp_id2;
+                    del_pppoetbl.multi_session = 1;
+				if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8327)
+					del_pppoetbl.uni_session = 1;
+				else
+                    		del_pppoetbl.uni_session = 0;
+                    del_pppoetbl.entry_id = 0;
+                    PPPOE_SESSION_TABLE_DEL(0, &del_pppoetbl);
+			memset(&pppoetbl, 0, sizeof(pppoetbl));
+                }
+                nf_athrs17_hnat_ppp_id2 = 0;
+                memset(&nf_athrs17_hnat_ppp_peer_mac2, 0, ETH_ALEN);
+            }
+            qcaswitch_hostentry_flush();
+            break;
+
+        default:
+            break;
+    }
+    return NOTIFY_DONE;
+}
+
+/* a linux interface is configured with ipaddr, then
+ * it becomes a L3 routing interface
+ * add the router mac of this interface to the table
+ */
+/* FIXME: only hande pppoe event right now. */
+static int qcaswitch_ip_event(struct notifier_block *this,
+                              unsigned long event, void *ptr)
+{
+    struct in_ifaddr *ifa = (struct in_ifaddr *)ptr;
+    struct net_device *dev = (struct net_device *)ifa->ifa_dev->dev;
+
+    if ((dev->type == ARPHRD_PPP) && (dev->flags & IFF_POINTOPOINT))
+    {
+        return qcaswitch_pppoe_ip_event(this, event, ptr);
+    }
+
+    return NOTIFY_DONE;
+}
+
+
+static struct notifier_block qcaswitch_ip_notifier =
+{
+    .notifier_call = qcaswitch_ip_event,
+    .priority = 100,
+};
+#endif // ifdef AUTO_UPDATE_PPPOE_INFO
+
+#define HOST_AGEOUT_STATUS 1
+void host_check_aging(void)
+{
+    fal_host_entry_t *host_entry_p, host_entry= {0};
+    sw_error_t rv;
+    int cnt = 0;
+    unsigned long flags;
+    fal_napt_entry_t src_napt = {0}, pub_napt = {0};
+
+    host_entry_p = &host_entry;
+    host_entry_p->entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+
+	/*check host is not neccessary, check napt is enough*/
+	return;
+
+    local_irq_save(flags);
+    while (1)
+    {
+        host_entry_p->status = HOST_AGEOUT_STATUS;
+        /* FIXME: now device id is set to 0. */
+        rv = IP_HOST_NEXT (0, FAL_IP_ENTRY_STATUS_EN, host_entry_p);
+        // rv = IP_HOST_NEXT (0, 0, host_entry_p);
+        if (SW_OK != rv)
+            break;
+        if (cnt >= ARP_ENTRY_MAX) // arp entry number
+            break;
+
+        if (ARP_AGE_NEVER == host_entry_p->status)
+            continue;
+
+        if ((S17_WAN_PORT == host_entry_p->port_id) &&
+                (host_entry_p->counter_en))
+        {
+            if (0 != host_entry_p->packet)
+            {
+                // arp entry is using, update it.
+                host_entry.status = ARP_AGE;
+                printk("Update WAN port hostentry!\n");
+                IP_HOST_ADD(0, host_entry_p);
+            }
+            else
+            {
+                printk("Del WAN port hostentry!\n");
+                IP_HOST_DEL(0, FAL_IP_ENTRY_IPADDR_EN, host_entry_p);
+            }
+            continue;
+        }
+
+        src_napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+        memcpy(&src_napt.src_addr, &host_entry_p->ip4_addr, sizeof(fal_ip4_addr_t));
+        pub_napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+        memcpy(&pub_napt.trans_addr, &host_entry_p->ip4_addr, sizeof(fal_ip4_addr_t));
+        if((NAPT_NEXT(0, FAL_NAT_ENTRY_SOURCE_IP_EN ,&src_napt) !=0) && \
+                (NAPT_NEXT(0, FAL_NAT_ENTRY_PUBLIC_IP_EN ,&pub_napt) != 0))
+        {
+            /* Cannot find naptentry */
+            printk("ARP id 0x%x: Cannot find NAPT entry!\n", host_entry_p->entry_id);
+            IP_HOST_DEL(0, FAL_IP_ENTRY_IPADDR_EN, host_entry_p);
+            continue;
+        }
+        // arp entry is using, update it.
+        host_entry_p->status = ARP_AGE;
+        IP_HOST_ADD(0, host_entry_p);
+        printk("update entry 0x%x port %d\n", host_entry_p->entry_id, host_entry_p->port_id);
+        cnt++;
+    }
+    local_irq_restore(flags);
+}
+
+#ifdef CONFIG_IPV6_HWACCEL
+#define IPV6_LEN 16
+#define MAC_LEN 6
+#define PROTO_ICMPV6 0x3a
+#define NEIGHBOUR_SOL 135
+#define NEIGHBOUR_AD 136
+
+struct icmpv6_option
+{
+    __u8 type;
+    __u8 len;
+    __u8 mac[MAC_LEN];
+};
+#if 0
+static unsigned int ipv6_handle(unsigned   int   hooknum,
+                                struct   sk_buff   *skb,
+                                const   struct   net_device   *in,
+                                const   struct   net_device   *out,
+                                int   (*okfn)(struct   sk_buff   *))
+{
+	struct sk_buff *new_skb = NULL;
+	struct nat_helper_bg_msg msg;
+	/*unsigned long flags = 0;*/
+
+	if (!nf_athrs17_hnat)
+        return NF_ACCEPT;
+
+	new_skb = skb_clone(skb, GFP_ATOMIC);
+	if(new_skb) {
+		memset(&msg, 0, sizeof(msg));
+		msg.msg_type = NAT_HELPER_IPV6_MSG;
+		msg.ipv6.skb = new_skb;
+		msg.ipv6.in = (struct net_device *)in;
+
+		/*send msgto background task*/
+		/*spin_lock_irqsave(&task_cb.bg_lock, flags);*/
+		if(bg_ring_buf_write(msg))
+			kfree_skb(new_skb);
+		/*spin_unlock_irqrestore(&task_cb.bg_lock, flags);*/
+	}
+	
+	return NF_ACCEPT;
+	
+}
+#endif
+
+#ifdef NAT_BACKGROUND_TASK
+
+static unsigned int ipv6_bg_handle(struct nat_helper_bg_msg *msg)
+{
+	struct net_device *in = msg->arp_in.in;
+	struct sk_buff *skb = msg->arp_in.skb;
+	
+    struct ipv6hdr *iph6 = ipv6_hdr(skb);
+    struct icmp6hdr *icmp6 = icmp6_hdr(skb);
+    __u8 *sip = ((__u8 *)icmp6)+sizeof(struct icmp6hdr);
+    struct icmpv6_option *icmpv6_opt = (struct icmpv6_option *)(sip+IPV6_LEN);
+    __u8 *sa = icmpv6_opt->mac;
+
+    uint32_t sport = 0, vid = 0;
+    struct inet6_ifaddr *in_device_addr = NULL;
+    uint8_t dev_is_lan = 0;
+    uint8_t *smac;
+	
+
+    /* do not write out host table if HNAT is disabled */
+    if (!nf_athrs17_hnat)
+        return 0;
+
+    setup_all_interface_entry();
+
+    if(dev_check((char *)in->name, (char *)nat_wan_dev_list))
+    {
+        dev_is_lan = 0;
+    }
+    else if (dev_check((char *)in->name, (char *)nat_lan_dev_list))
+    {
+        dev_is_lan = 1;
+    }
+    else
+    {
+        HNAT_PRINTK("Not Support device: %s\n",  (char *)in->name);
+        return 0;
+    }
+
+    if(PROTO_ICMPV6 == iph6->nexthdr)
+    {
+        if(NEIGHBOUR_AD == icmp6->icmp6_type)
+        {
+			fal_fdb_entry_t entry;
+            if (__ipv6_addr_type((struct in6_addr*)sip) & IPV6_ADDR_LINKLOCAL)
+                return 0;
+
+#ifdef AP136_QCA_HEADER_EN
+            if(arp_if_info_get((void *)(skb->head), &sport, &vid) != 0)
+            {
+                return 0;
+            }
+
+            if ((0 == vid)||(0 == sport))
+            {
+                printk("Error: Null sport or vid!!\n");
+                return 0;
+            }
+#else
+            if(dev_is_lan) {
+                 vid = NAT_LAN_DEV_VID;
+            } else {
+                 vid = NAT_WAN_DEV_VID;
+            }
+
+            memset(&entry, 0, sizeof(entry));
+
+            entry.fid = vid;
+            smac = skb_mac_header(skb) + MAC_LEN;
+            aos_mem_copy(&(entry.addr), smac, sizeof(fal_mac_addr_t));
+
+            if(FDB_ENTRY_SEARCH(0, &entry) == SW_OK) {
+                vid  = entry.fid;
+                sport = 0;
+                while (sport < 32) {
+                    if(entry.port.map & (1 << sport)) {
+                        break;
+                    }
+                    sport++;
+                }
+            } else {
+                printk("not find the FDB entry\n");
+            }
+#endif
+            if ((0 == dev_is_lan) && (S17_WAN_PORT != sport))
+            {
+                printk("Error: WAN port %d\n", sport);
+                return 0;
+            }
+
+            HNAT_PRINTK("ND Reply %x %x\n",icmpv6_opt->type,icmpv6_opt->len);
+            HNAT_PRINTK("isis_v6: incoming packet, sip = %02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x\n"
+                        ,sip[0],sip[1],sip[2],sip[3],sip[4],sip[5],sip[6],sip[7]
+                        ,sip[8],sip[9],sip[10],sip[11],sip[12],sip[13],sip[14],sip[15]
+                       );
+            HNAT_PRINTK("isis_v6: incoming packet, sa  = %.2x-%.2x-%.2x-%.2x-%.2x-%.2x\n", sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]);
+            HNAT_PRINTK("isis_v6: vid = %d sport = %d\n", vid, sport);
+
+            //add nd entry
+            if((2 == icmpv6_opt->type) && (1 == icmpv6_opt->len))
+            {
+                arp_hw_add(sport, vid, sip, sa, 1);
+            }
+            else /* ND AD packets without option filed? Fix Me!! */
+            {
+		sa = skb_mac_header(skb) + MAC_LEN;
+                HNAT_PRINTK("isis_v6 Changed sa  = %.2x-%.2x-%.2x-%.2x-%.2x-%.2x\n", sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]);
+                arp_hw_add(sport, vid, sip, sa, 1);
+            }
+
+#ifdef NAT_TODO /* should be ok */
+            if ((NULL != in->ip6_ptr) && (NULL != ((struct inet6_dev *)in->ip6_ptr)->addr_list))
+#else
+            if (NULL != in->ip6_ptr)
+#endif
+            {
+                //list_for_each_entry(in_device_addr, &(in->ip6_ptr)->addr_list, if_list);
+                struct inet6_dev *idev = __in6_dev_get(in);
+                list_for_each_entry(in_device_addr, &idev->addr_list, if_list) {
+            		if (in_device_addr->scope == 0 &&
+            		    !(in_device_addr->flags & IFA_F_TENTATIVE)) {
+            			break;
+            		}
+        	    }
+
+                if (0 == dev_is_lan)
+                {
+                    /* WAN ipv6 address*/
+                    memcpy(&wan6ip, (__u8 *)&in_device_addr->addr, sizeof(struct in6_addr));
+                    HNAT_PRINTK("%s: ipv6 wanip %pI6\n", in->name, &wan6ip);
+                }
+                else
+                {
+                    /* LAN ipv6 address*/
+                    memcpy(&lan6ip, (__u8 *)&in_device_addr->addr, sizeof(struct in6_addr));
+                    HNAT_PRINTK("%s: ipv6 lanip %pI6\n", in->name, &lan6ip);
+                }
+            }
+        }
+    }
+
+    return 1;
+}
+#endif
+
+#if 0
+static struct nf_hook_ops ipv6_inhook =
+{
+    .hook = ipv6_handle,
+    #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0))
+    .owner = THIS_MODULE,
+    #endif
+    .pf = PF_INET6,
+    .hooknum = NF_INET_PRE_ROUTING,
+    .priority = NF_IP6_PRI_CONNTRACK,
+};
+#endif
+#endif /* CONFIG_IPV6_HWACCEL */
+
+#ifdef NAT_BACKGROUND_TASK
+
+static void nat_task_entry(struct work_struct *wq)
+{
+	struct nat_helper_bg_msg msg;
+	/*unsigned long flags = 0;*/
+	unsigned int result = 0;
+
+	msg = *(struct nat_helper_bg_msg *)wq;
+
+	/*spin_lock_irqsave(&task_cb.bg_lock, flags);*/
+	bg_ring_buf_read(NULL);
+	/*spin_unlock_irqrestore(&task_cb.bg_lock, flags);*/
+
+	if(msg.msg_type == NAT_HELPER_ARP_ADD_MSG) {
+		result =  arp_add(&msg);
+	} else if (msg.msg_type == NAT_HELPER_ARP_DEL_MSG) {
+		result =  arp_del(&msg);
+	}
+	#ifdef CONFIG_IPV6_HWACCEL
+	else if(msg.msg_type == NAT_HELPER_IPV6_MSG) {
+		result = ipv6_bg_handle(&msg);
+	}
+	#endif
+
+	HNAT_PRINTK("handle msg: %d, result: %d\n", msg.msg_type, result);
+	
+}
+
+void nat_helper_bg_task_init()
+{
+	unsigned int i = 0;
+	struct nat_helper_bg_msg *msg;
+	/*create the thread and alloc ring buffer*/
+
+	memset(&task_cb, 0, sizeof(task_cb));
+
+	task_cb.nat_wq = create_singlethread_workqueue("nat_wq");
+
+    if(!task_cb.nat_wq)
+    {
+        aos_printk("create nat workqueuefail\n");
+        return;
+    }
+
+	/*init lock and alloc the ring buffer*/
+	
+	/*sema_init(&task_cb.bg_sem, 0);*/
+	spin_lock_init(&task_cb.bg_lock);
+	
+	task_cb.ring.num = NAT_HELPER_MSG_MAX;
+	task_cb.ring.buf = kzalloc(NAT_HELPER_MSG_MAX * sizeof(struct nat_helper_bg_msg), GFP_ATOMIC);
+	if(!task_cb.ring.buf) {
+		aos_printk("ring buf alloc fail!\n");
+		return;
+	}
+	msg = (struct nat_helper_bg_msg*)task_cb.ring.buf;
+	for(i = 0; i < task_cb.ring.num; i++) 
+	{
+		INIT_WORK(&msg[i].work, nat_task_entry);
+	}
+
+	aos_printk("bg task init successfull!\n");
+	
+}
+
+void nat_helper_bg_task_exit()
+{
+	/*stop the workqueue and release the ring buffer*/
+	if(task_cb.nat_wq)
+		destroy_workqueue(task_cb.nat_wq);
+	if(task_cb.ring.buf)
+		kfree(task_cb.ring.buf);
+}
+#endif
+
+
+extern int napt_procfs_init(void);
+extern void napt_procfs_exit(void);
+
+void host_helper_init(a_uint32_t portbmp)
+{
+	REG_GET(0, 0, (a_uint8_t *)&nat_chip_ver, 4);
+
+	/* header len 4 with type 0xaaaa */
+	HEADER_TYPE_SET(0, A_TRUE, 0xaaaa);
+	if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8337 ||
+		((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_DESS) {
+		/* For S17c (ISISC), it is not necessary to make all frame with header */
+		printk("host_helper_init start\n");
+		//PORT_TXHDR_MODE_SET(0, 0, FAL_ONLY_MANAGE_FRAME_EN);
+		/* Fix tag disappear problem, set TO_CPU_VID_CHG_EN, 0xc00 bit1 */
+		CPU_VID_EN_SET(0, A_TRUE);
+		/* set RM_RTD_PPPOE_EN, 0xc00 bit0 */
+		RTD_PPPOE_EN_SET(0, A_TRUE);
+		/* Avoid ARP response storm for HUB, now this fix only apply on PORT5 */
+		#if 0
+		MISC_ARP_SP_NOT_FOUND_SET(0, FAL_MAC_RDT_TO_CPU);
+		MISC_ARP_GUARD_SET(0, S17_WAN_PORT, FAL_MAC_IP_PORT_GUARD);
+		#endif
+		/* set VLAN_TRANS_TEST register bit, to block packets from WAN port has private dip */
+		NETISOLATE_SET(0, A_TRUE);
+	} else {
+		PORT_TXHDR_MODE_SET(0, 0, FAL_ALL_TYPE_FRAME_EN);
+	}
+    CPU_PORT_STATUS_SET(0, A_TRUE);
+    IP_ROUTE_STATUS_SET(0, A_TRUE);
+
+    napt_procfs_init();
+    memcpy(nat_bridge_dev, nat_lan_dev_list, strlen(nat_lan_dev_list)+1);
+
+    register_netevent_notifier(&hnat_netevent_notifier);
+/*hnat not upport ipv6*/
+#if 0
+#ifdef CONFIG_IPV6_HWACCEL
+    aos_printk("Registering IPv6 hooks... \n");
+    nf_register_hook(&ipv6_inhook);
+#endif
+#endif
+
+#ifdef AUTO_UPDATE_PPPOE_INFO
+    register_inetaddr_notifier(&qcaswitch_ip_notifier);
+#endif // ifdef AUTO_UPDATE_PPPOE_INFO
+
+    nat_wan_port = portbmp;
+
+    /* Enable ACLs to handle MLD packets */
+    upnp_ssdp_add_acl_rules();
+    ipv6_snooping_solicted_node_add_acl_rules();
+    ipv6_snooping_sextuple0_group_add_acl_rules();
+    ipv6_snooping_quintruple0_1_group_add_acl_rules();
+
+    napt_helper_hsl_init();
+}
+
+void host_helper_exit(void)
+{
+    napt_procfs_exit();
+
+    unregister_netevent_notifier(&hnat_netevent_notifier);
+#if 0
+#ifdef CONFIG_IPV6_HWACCEL
+    nf_unregister_hook(&ipv6_inhook);
+#endif
+#endif
+
+	#ifdef AUTO_UPDATE_PPPOE_INFO
+	unregister_inetaddr_notifier(&qcaswitch_ip_notifier);
+	#endif
+}
+
diff --git a/qca-ssdk/app/nathelper/linux/lib/nat_helper_dt.c b/qca-ssdk/app/nathelper/linux/lib/nat_helper_dt.c
new file mode 100755
index 0000000..8594188
--- /dev/null
+++ b/qca-ssdk/app/nathelper/linux/lib/nat_helper_dt.c
@@ -0,0 +1,1357 @@
+/*
+ * Copyright (c) 2012, 2015, 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifdef KVER32
+#include <linux/kconfig.h>
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#endif
+#include <linux/kthread.h>
+#include <linux/udp.h>
+#include <linux/rculist_nulls.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+
+#include "../nat_helper.h"
+#include "../napt_helper.h"
+#include "../napt_acl.h"
+
+#include "fal_type.h"
+#include "fal_nat.h"
+
+#include "nat_helper_dt.h"
+#include "nat_helper_hsl.h"
+
+#define NAPT_CT_POLLING_SEC         5
+#define NPAT_CT_POLLING_QUOTA	256
+
+extern int nat_sockopts_init;
+extern uint32_t napt_set_default_route(fal_ip4_addr_t dst_addr, fal_ip4_addr_t src_addr);
+#ifdef CONFIG_IPV6_HWACCEL
+extern uint32_t napt_set_ipv6_default_route(void);
+#endif
+extern void nat_ipt_sockopts_replace(void);
+extern void qcaswitch_hostentry_flush(void);
+
+#define NAPT_BUFFER_HASH_SIZE        (NAPT_TABLE_SIZE)
+#define NAPT_BUFFER_SIZE             ((NAPT_BUFFER_HASH_SIZE)*8)
+
+static a_uint32_t napt_buffer_hash_size = NAPT_TABLE_SIZE;
+static a_uint32_t napt_buffer_size = (NAPT_BUFFER_HASH_SIZE)*8;
+static a_uint32_t napt_ct_hw_cnt = 0;
+static a_uint8_t napt_thread_pending = 0;
+
+a_uint32_t polling_quota = NPAT_CT_POLLING_QUOTA;
+
+extern int nat_chip_ver;
+
+struct napt_ct
+{
+    struct napt_ct *next;
+    uintptr_t ct_addr;
+    a_uint64_t ct_packets;
+    a_uint8_t in_hw;
+    a_uint16_t hw_index;
+    a_uint8_t deny;
+	a_uint64_t last_jiffies;
+};
+
+struct napt_debug_counter
+{
+	a_uint32_t interate_cnt;
+	a_uint32_t care_cnt;
+	a_uint32_t thresh_low_cnt;
+};
+
+struct nhlist_head
+{
+    struct napt_ct *next;
+};
+
+static struct nhlist_head *ct_buf_hash_head = NULL;
+static struct napt_ct *ct_buf = NULL;
+static a_uint32_t ct_buf_ct_cnt = 0;
+static struct napt_debug_counter napt_ct_debug_info;
+
+int scan_period = NAPT_CT_POLLING_SEC;
+int scan_enable = 1;
+int napt_need_clean = 0;
+/*pppoe dhcp siwtch pre-handle*/
+int wan_switch = 0;
+
+
+static a_int32_t
+napt_hash_buf_init(struct napt_ct **hash, struct nhlist_head **hash_head)
+{
+    a_uint32_t hash_size = NAPT_BUFFER_HASH_SIZE;
+    a_uint32_t buffer_size = NAPT_BUFFER_SIZE;
+
+    *hash = (struct napt_ct *)kmalloc(sizeof(struct napt_ct)*buffer_size, GFP_ATOMIC);
+    if(!(*hash))
+    {
+        HNAT_PRINTK("NAPT INIT ERROR! No Sufficient Memory!");
+        return -1;
+    }
+
+    *hash_head = (struct nhlist_head *)kmalloc(sizeof(struct nhlist_head)*hash_size, GFP_ATOMIC);
+    if(!(*hash_head))
+    {
+        HNAT_PRINTK("NAPT INIT ERROR! No Sufficient Memory!");
+        kfree(*hash);
+        return -1;
+    }
+
+    memset(*hash,0,sizeof(struct napt_ct)*buffer_size);
+    memset(*hash_head,0,sizeof(struct nhlist_head)*hash_size);
+
+    return 0;
+}
+
+#include <linux/hash.h>
+static a_uint32_t
+napt_ct_hash(uintptr_t ct_addr)
+{
+	/*
+	if(nf_athrs17_hnat_sync_counter_en == 0)
+		return (((ct_addr) * (0x9e370001UL)) >> 22);
+	else
+		return (((ct_addr) * (0x9e370001UL)) >> 29);
+	*/
+	return hash_long(ct_addr, NAPT_TABLE_BITS);
+}
+
+static struct napt_ct *
+napt_hash_add(uintptr_t ct_addr, a_uint32_t *hash_cnt,
+              struct napt_ct *hash, struct nhlist_head *hash_head)
+{
+    struct napt_ct *entry = 0,*last = 0,*node = 0;
+    struct nhlist_head *head = 0;
+    a_uint32_t hash_index = napt_ct_hash(ct_addr);
+		a_uint32_t i = 0, j = 0, index = 0xffffffff;
+
+    if(*hash_cnt >= napt_buffer_size)
+    {
+        return NULL;
+    }
+    head = &(hash_head[hash_index]);
+    entry = head->next;
+
+    while(entry)
+    {
+        if(ct_addr == entry->ct_addr)
+        {
+            return entry;
+        }
+        else
+        {
+            last = entry;
+            entry = entry->next;
+        }
+    }
+	/*find a valid position*/
+	for (i = *hash_cnt; i < napt_buffer_size; i++) {
+		if (hash[i].ct_addr == 0)
+			break;
+	}
+	if (i >= napt_buffer_size) {
+		for (j = 0; j < *hash_cnt; j++) {
+			if (hash[j].ct_addr == 0)
+				break;
+		}
+		if (j >= *hash_cnt)
+			return NULL;
+		index = j;
+	} else {
+		index = i;
+	}
+
+    node = &(hash[index]);
+    node->ct_addr = ct_addr;
+    node->ct_packets = 0;
+    node->in_hw = 0;
+    node->hw_index = 0;
+    node->deny = 0;
+
+    if(head->next == 0)
+    {
+        head->next = node;
+    }
+    else
+    {
+        last->next = node;
+    }
+    (*hash_cnt)++;
+
+    return node;
+}
+
+static struct napt_ct *
+napt_hash_find(uintptr_t ct_addr, a_uint32_t *hash_cnt,
+               struct napt_ct *hash, struct nhlist_head *hash_head)
+{
+    struct napt_ct *entry = 0;
+    struct nhlist_head *head = 0;
+    a_uint32_t hash_index = napt_ct_hash(ct_addr);
+
+    if(*hash_cnt == 0)
+    {
+        return NULL;
+    }
+#if 0 /* prevent empty entries. */
+    if(*hash_cnt >= NAPT_BUFFER_SIZE)
+    {
+        return NULL;
+    }
+#endif
+
+    head = &(hash_head[hash_index]);
+
+    if(head->next == 0)
+    {
+        return NULL;
+    }
+    entry = head->next;
+    do
+    {
+        if(ct_addr == entry->ct_addr)
+        {
+            return entry;
+        }
+
+        entry = entry->next;
+    }
+    while(entry);
+
+    return NULL;
+}
+
+static a_int32_t
+napt_ct_buf_init(void)
+{
+    return napt_hash_buf_init(&ct_buf, &ct_buf_hash_head);
+}
+
+static void
+napt_ct_buf_exit(void)
+{
+    if(ct_buf_hash_head)
+        kfree(ct_buf_hash_head);
+
+    if(ct_buf)
+        kfree(ct_buf);
+}
+
+static void
+napt_ct_buf_flush(void)
+{
+    ct_buf_ct_cnt = 0;
+    memset(ct_buf,0,sizeof(struct napt_ct)*NAPT_BUFFER_SIZE);
+    memset(ct_buf_hash_head,0,sizeof(struct nhlist_head)*NAPT_BUFFER_HASH_SIZE);
+}
+
+static a_uint32_t
+napt_ct_cnt_get(void)
+{
+    return ct_buf_ct_cnt;
+}
+
+static struct napt_ct *
+napt_ct_buf_ct_find(uintptr_t ct_addr)
+{
+    return napt_hash_find(ct_addr, &ct_buf_ct_cnt,
+                          ct_buf, ct_buf_hash_head);
+}
+
+static a_uint64_t
+napt_ct_buf_pkts_get(struct napt_ct *napt_ct)
+{
+    return napt_ct->ct_packets;
+}
+
+static void
+napt_ct_buf_pkts_update(struct napt_ct *napt_ct, a_uint64_t packets)
+{
+    napt_ct->ct_packets = packets;
+}
+
+static a_uint8_t
+napt_ct_buf_deny_get(struct napt_ct *napt_ct)
+{
+    return napt_ct->deny;
+}
+
+static void
+napt_ct_buf_deny_set(struct napt_ct *napt_ct, a_uint8_t deny)
+{
+    napt_ct->deny = deny;
+}
+
+static void
+napt_ct_buf_deny_clear(struct napt_ct *napt_ct)
+{
+    napt_ct->deny = 0;
+}
+
+static a_uint8_t
+napt_ct_buf_in_hw_get(struct napt_ct *napt_ct, a_uint16_t *hw_index)
+{
+    *hw_index = napt_ct->hw_index;
+    return napt_ct->in_hw;
+}
+
+static void
+napt_ct_buf_in_hw_set(struct napt_ct *napt_ct, a_uint16_t hw_index)
+{
+    napt_ct->in_hw = 1;
+    napt_ct->hw_index = hw_index;
+}
+
+static void
+napt_ct_buf_in_hw_clear(struct napt_ct *napt_ct)
+{
+    napt_ct->in_hw = 0;
+    napt_ct->hw_index = 0;
+}
+
+static void
+napt_ct_buf_ct_info_clear(struct napt_ct *napt_ct)
+{
+	a_uint32_t hash_index = napt_ct_hash(napt_ct->ct_addr);
+	struct nhlist_head *head = 0;
+	struct napt_ct *entry = 0, *last = 0;
+
+	head = &ct_buf_hash_head[hash_index];
+	entry = head->next;
+	while (entry && entry != napt_ct) {
+		last = entry;
+		entry = entry->next;
+	}
+	if (last == 0)
+		head->next = napt_ct->next;
+	else
+		last->next = napt_ct->next;
+    napt_ct->ct_addr = 0;
+    napt_ct->ct_packets = 0;
+	napt_ct->deny = 0;
+	napt_ct->next = NULL;
+}
+
+static struct napt_ct *
+napt_ct_buf_ct_add(uintptr_t ct_addr)
+{
+    struct napt_ct *napt_ct;
+    napt_ct = napt_hash_add(ct_addr, &ct_buf_ct_cnt,
+                            ct_buf, ct_buf_hash_head);
+
+    if(napt_ct)
+    {
+        /*ct pkts initial*/
+        napt_ct_buf_pkts_update(napt_ct, NAPT_CT_PKTS_GET(ct_addr));
+    }
+
+    return napt_ct;
+}
+
+#define NAPT_CT_PERMANENT_DENY 5
+static uintptr_t napt_ct_addr[NAPT_TABLE_SIZE] = {0};
+a_uint32_t napt_cookie[NAPT_TABLE_SIZE*2] = {0};
+
+a_uint32_t packet_thres_base = 50;
+static a_uint64_t packets_bdir_total = 0;
+static a_uint64_t packets_bdir_thres = 0;
+
+static inline a_int32_t
+before(a_uint64_t seq1, a_uint64_t seq2)
+{
+    return ((int64_t)(seq1-seq2) < 0);
+}
+
+static a_uint8_t
+napt_ct_pkts_reach_thres(uintptr_t ct_addr, struct napt_ct *napt_ct,
+                         a_uint8_t pkts_sum)
+{
+    a_uint64_t packets_bdir_old = napt_ct_buf_pkts_get(napt_ct);
+    a_uint64_t packets_bdir_new = NAPT_CT_PKTS_GET(ct_addr);
+
+    if(pkts_sum)
+    {
+        if(packets_bdir_new > packets_bdir_old)
+        {
+            packets_bdir_total += (packets_bdir_new - packets_bdir_old);
+        }
+    }
+
+    napt_ct_buf_pkts_update(napt_ct, packets_bdir_new);
+
+    HNAT_PRINTK("<%s> ct:%x packets_bdir_old:%lld ==> packets_bdir_new:%lld, thresh:%lld\n",
+                __func__, ct_addr, packets_bdir_old, packets_bdir_new, packets_bdir_thres);
+
+    if(before((packets_bdir_old+packets_bdir_thres), packets_bdir_new))
+    {
+        return 1;
+    }
+
+    return 0;
+}
+
+a_uint8_t napt_dnat_flow_find_del(
+		napt_entry_t *napt,
+		fal_napt_entry_t *entry)
+{
+	fal_napt_entry_t tmp_entry;
+	napt_entry_t tmp_napt;
+	a_int32_t ret;
+
+	memset(&tmp_entry, 0, sizeof(tmp_entry));
+	memset(&tmp_napt, 0, sizeof(tmp_napt));
+	tmp_napt = *napt;
+	tmp_napt.src_addr = 0;
+	ret = napt_hw_get(&tmp_napt, &tmp_entry);
+	if(!ret) {
+		napt_hw_del(&tmp_napt);
+		*entry = tmp_entry;
+		return 0;
+	}
+	return 1;
+}
+
+a_uint8_t napt_snat_flow_find_del(
+		napt_entry_t *napt,
+		fal_napt_entry_t *entry)
+{
+	fal_napt_entry_t tmp_entry;
+	napt_entry_t tmp_napt;
+	a_int32_t ret;
+
+	memset(&tmp_entry, 0, sizeof(tmp_entry));
+	memset(&tmp_napt, 0, sizeof(tmp_napt));
+	tmp_napt = *napt;
+	tmp_napt.trans_addr = 0;
+	ret = napt_hw_get(&tmp_napt, &tmp_entry);
+	if(!ret) {
+		napt_hw_del(&tmp_napt);
+		*entry = tmp_entry;
+		return 0;
+	}
+	return 1;
+}
+
+
+
+
+static a_int32_t
+napt_ct_hw_add(uintptr_t ct_addr, a_uint16_t *hw_index)
+{
+    napt_entry_t napt = {0};
+    a_uint32_t index, i, dcookie = 0, scookie = 0;
+	fal_napt_entry_t entry;
+	a_uint8_t ret = 0;
+	sw_error_t rv = SW_OK;
+
+    if (!ct_addr)
+        return -1;
+
+    NAPT_CT_TO_HW_ENTRY(ct_addr, &napt);
+
+    if(nat_hw_pub_ip_add(napt.trans_addr, &index) == 0)
+    {
+        napt.trans_addr = index;
+
+    }
+    else
+    {
+        HNAT_ERR_PRINTK("####%s##nat_hw_pub_ip_add fail!\n", __func__);
+        return -1;
+    }
+	if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_DESS) {
+		ret = napt_dnat_flow_find_del(&napt, &entry);
+		if(!ret) {
+			dcookie = entry.flow_cookie;
+		}
+		ret = napt_snat_flow_find_del(&napt, &entry);
+		if(!ret) {
+			scookie = entry.flow_cookie;
+		}
+	}
+	rv = napt_hw_add(&napt);
+
+    if(rv == 0)
+    {
+        HNAT_PRINTK("%s: success entry_id:0x%x ct 0x%x\n", __func__, napt.entry_id, ct_addr);
+
+        if(napt_ct_addr[napt.entry_id])
+        {
+            HNAT_ERR_PRINTK("fault: napt HW:%x can not be overwrited!\n",
+                            napt.entry_id);
+
+        }
+        else
+        {
+            napt_ct_addr[napt.entry_id] = ct_addr;
+            *hw_index = napt.entry_id;
+            // Added from 1.0.7 for default route.
+            napt_set_default_route(napt.dst_addr, napt.src_addr);
+			if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_DESS) {
+				i = napt.entry_id;
+				napt_cookie[i*2] = dcookie;
+				napt_cookie[i*2+1] = scookie;
+			}
+		napt_ct_hw_cnt++;
+
+            return 0;
+        }
+    }
+    else
+    {
+        HNAT_PRINTK("%s:fail rv:%d entry_id:%x(maybe full)\n",
+                    __func__,rv, napt.entry_id);
+        nat_hw_pub_ip_del(napt.trans_addr);
+    }
+
+    return -1;
+}
+
+static a_int32_t
+napt_ct_hw_del (napt_entry_t *napt)
+{
+    if(napt_hw_del(napt)!= 0)
+    {
+        HNAT_ERR_PRINTK("%s: isis_napt_del fail\n", __func__);
+        return -1;
+    }
+	napt_ct_hw_cnt--;
+    if(nat_hw_pub_ip_del(napt->trans_addr) != 0)
+    {
+        HNAT_ERR_PRINTK("%s: public_ip_del fail\n", __func__);
+        //return -1;
+    }
+    return 0;
+}
+
+void nat_helper_cookie_del(a_uint32_t hw_index)
+{
+	struct napt_ct *napt_ct = NULL;
+	uintptr_t ct_addr;
+	ct_addr = napt_ct_addr[hw_index];
+	if(ct_addr) {
+		napt_ct = napt_ct_buf_ct_find(ct_addr);
+	}
+	if(napt_ct)
+    {
+        napt_ct_buf_in_hw_clear(napt_ct);
+
+        if(napt_ct_buf_deny_get(napt_ct) != NAPT_CT_PERMANENT_DENY)
+        {
+            napt_ct_buf_ct_info_clear(napt_ct);
+        }
+		NAPT_CT_AGING_ENABLE(napt_ct_addr[hw_index]);
+    }
+	napt_ct_addr[hw_index] = 0;
+	napt_cookie[hw_index*2] = 0;
+	napt_cookie[hw_index*2+1] = 0;
+	HNAT_INFO_PRINTK("nat_helper_cookie_del for index 0x%x\n", hw_index);
+}
+
+
+static a_int32_t
+napt_ct_del(struct napt_ct *napt_ct, napt_entry_t *napt)
+{
+    a_uint16_t hw_index = napt->entry_id;
+
+    HNAT_PRINTK("%s: 0x%x ct 0x%x\n", __FUNCTION__, hw_index, napt_ct_addr[hw_index]);
+
+    if(napt_ct_hw_del(napt) != 0)
+    {
+        return -1;
+    }
+
+    NAPT_CT_AGING_ENABLE(napt_ct_addr[hw_index]);
+    napt_ct_addr[hw_index] = 0;
+	if(napt_cookie[hw_index*2]) {
+		napt_hw_dnat_cookie_add(napt, napt_cookie[hw_index*2]);
+		napt_cookie[hw_index*2] = 0;
+	}
+	if(napt_cookie[hw_index*2+1]) {
+		napt_hw_snat_cookie_add(napt, napt_cookie[hw_index*2+1]);
+		napt_cookie[hw_index*2+1] = 0;
+	}
+
+    if(napt_ct)
+    {
+        napt_ct_buf_in_hw_clear(napt_ct);
+
+        if(napt_ct_buf_deny_get(napt_ct) != NAPT_CT_PERMANENT_DENY)
+        {
+            napt_ct_buf_ct_info_clear(napt_ct);
+        }
+    }
+
+    return 0;
+}
+
+static a_int32_t
+napt_ct_del_by_index (struct napt_ct *napt_ct, a_uint16_t hw_index)
+{
+    napt_entry_t napt = {0};
+
+    if(napt_hw_get_by_index(&napt, hw_index) != 0)
+    {
+        return -1;
+    }
+
+    return napt_ct_del(napt_ct, &napt);
+}
+
+static a_int32_t
+napt_ct_in_hw_sanity_check(struct napt_ct *napt_ct, a_uint16_t hw_index)
+{
+	a_uint16_t ct_hw_index = 0;
+    if(!napt_ct)
+    {
+        HNAT_ERR_PRINTK("<%s>hw_index:%d error napt_ct can't find\n",
+                        __func__, hw_index);
+        return -1;
+    }
+
+    if(napt_ct_buf_in_hw_get(napt_ct, &ct_hw_index) == 0)
+    {
+        HNAT_ERR_PRINTK("<%s>hw_index:%d in_hw:0 error\n",
+                        __func__, hw_index);
+        return -1;
+    }
+
+    if(hw_index != ct_hw_index)
+    {
+        HNAT_ERR_PRINTK("<%s>hw_index:%d buf_hw_index:%d\n",
+                        __func__, hw_index, ct_hw_index);
+        return -1;
+    }
+
+    return 0;
+}
+
+void
+napt_ct_hw_aging(void)
+{
+#define NAPT_AGEOUT_STATUS 1
+
+    uintptr_t ct_addr;
+	a_uint32_t cnt= 0;
+    napt_entry_t napt = {0};
+
+
+    if(napt_hw_first_by_age(&napt, NAPT_AGEOUT_STATUS) != 0)
+    {
+        return;
+    }
+
+    do
+    {
+        a_uint16_t hw_index = napt.entry_id;
+		struct napt_ct *napt_ct = NULL;
+        ct_addr = napt_ct_addr[hw_index];
+
+        if(ct_addr)
+        {
+            napt_ct = napt_ct_buf_ct_find(ct_addr);
+            if(napt_ct_in_hw_sanity_check(napt_ct, hw_index) != 0)
+            {
+                HNAT_ERR_PRINTK("<%s> napt_ct_in_hw_sanity_check fail\n", __func__);
+                continue;
+            }
+
+            if((nf_athrs17_hnat_sync_counter_en == 0) && (napt_ct_pkts_reach_thres(ct_addr, napt_ct, 0)))
+            {
+                printk("<aging>set PERMANENT deny ct:%lx\n", (a_ulong_t)ct_addr);
+                napt_ct_buf_deny_set(napt_ct, NAPT_CT_PERMANENT_DENY);
+            }
+        }
+        else
+        {
+            HNAT_ERR_PRINTK("<aging> error: in_hw but ct = NULL hw_index:%x\n", hw_index);
+        }
+
+        napt_ct_del(napt_ct, &napt);
+        HNAT_INFO_PRINTK("ct:%x aged!\n", ct_addr);
+        cnt++;
+        if ((cnt % polling_quota) == 0) {
+            NAPT_CT_TASK_SLEEP(1);
+        }
+
+    }
+    while(napt_hw_next_by_age(&napt, NAPT_AGEOUT_STATUS) != -1);
+
+#if 0
+    if(napt_hw_used_count_get() == 0)
+    {
+        nat_hw_prv_base_update_enable();
+    }
+#endif 
+
+    return;
+}
+
+static a_uint32_t
+napt_ct_counter_sync(a_uint32_t hw_index)
+{
+	napt_entry_t napt = {0};
+	struct nf_conn *ct = NULL;
+	struct nf_conn_counter *cct = NULL;
+	a_uint64_t delta_jiffies = 0, now_jiffies;
+	a_uint32_t ct_addr = napt_ct_addr[hw_index];
+	struct napt_ct *napt_ct;
+
+	if((nf_athrs17_hnat_sync_counter_en == 0) || (napt_ct_addr[hw_index] == 0) || (hw_index >= NAPT_TABLE_SIZE))
+		return -1;
+
+	ct = (struct nf_conn *)(uintptr_t)napt_ct_addr[hw_index];
+	cct = (struct nf_conn_counter *)nf_conn_acct_find(ct);
+	napt_ct = napt_ct_buf_ct_find(ct_addr);
+	if (napt_ct) {
+		now_jiffies = (a_uint64_t)get_jiffies_64();
+		delta_jiffies = now_jiffies - napt_ct->last_jiffies;
+		napt_ct->last_jiffies = now_jiffies;
+	}
+	
+	if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) {
+		ct->timeout.expires += delta_jiffies;
+	}
+
+	if((cct != NULL) && (napt_hw_get_by_index(&napt, hw_index) == 0))
+	{
+		spin_lock_bh(&ct->lock);
+		if ((ct->status & IPS_NAT_MASK) == IPS_SRC_NAT) {
+			atomic64_add(napt.egress_packet, &cct[IP_CT_DIR_ORIGINAL].packets);
+			atomic64_add(napt.egress_byte, &cct[IP_CT_DIR_ORIGINAL].bytes);
+			atomic64_add(napt.ingress_packet, &cct[IP_CT_DIR_REPLY].packets);
+			atomic64_add(napt.ingress_byte, &cct[IP_CT_DIR_REPLY].bytes);
+		} else {
+			atomic64_add(napt.ingress_packet, &cct[IP_CT_DIR_ORIGINAL].packets);
+			atomic64_add(napt.ingress_byte, &cct[IP_CT_DIR_ORIGINAL].bytes);
+			atomic64_add(napt.egress_packet, &cct[IP_CT_DIR_REPLY].packets);
+			atomic64_add(napt.egress_byte, &cct[IP_CT_DIR_REPLY].bytes);
+		}
+		spin_unlock_bh(&ct->lock);
+		HNAT_PRINTK("original packets:0x%llx  bytes:0x%llx\n",
+				cct[IP_CT_DIR_ORIGINAL].packets, cct[IP_CT_DIR_ORIGINAL].bytes);
+		HNAT_PRINTK("reply packets:0x%llx  bytes:0x%llx\n",
+				cct[IP_CT_DIR_REPLY].packets, cct[IP_CT_DIR_REPLY].bytes);
+	}
+
+	return 0;
+}
+
+static a_int32_t
+napt_ct_timer_update(a_uint32_t hw_index)
+{
+	struct nf_conn *ct = NULL;
+	struct nf_conn_counter *cct = NULL;
+	a_uint64_t delta_jiffies = 0, now_jiffies;
+	uintptr_t ct_addr = napt_ct_addr[hw_index];
+	struct napt_ct *napt_ct;
+
+	if((napt_ct_addr[hw_index] == 0) || (hw_index >= NAPT_TABLE_SIZE))
+		return -1;
+
+	ct = (struct nf_conn *)(uintptr_t)napt_ct_addr[hw_index];
+	cct = (struct nf_conn_counter *)nf_conn_acct_find(ct);
+	napt_ct = napt_ct_buf_ct_find(ct_addr);
+	if (napt_ct) {
+		now_jiffies = (a_uint64_t)get_jiffies_64();
+		delta_jiffies = now_jiffies - napt_ct->last_jiffies;
+		napt_ct->last_jiffies = now_jiffies;
+	}
+
+	if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) {
+		ct->timeout.expires += delta_jiffies;
+	}
+
+	return 0;
+}
+
+void napt_ct_counter_decrease(void)
+{
+	ct_buf_ct_cnt--;
+}
+
+#define NAPT_INVALID_CT_NEED_HW_CLEAR(hw_index)  \
+                                ((napt_ct_valid[hw_index] == 0) && \
+                                 (napt_ct_addr[hw_index] != 0))
+static a_uint32_t
+napt_ct_hw_sync(a_uint8_t napt_ct_valid[])
+{
+    a_uint16_t hw_index;
+    a_uint32_t napt_ct_offload_cnt = 0;
+
+    for(hw_index = 0; hw_index < NAPT_TABLE_SIZE; hw_index++)
+    {
+		#if 0
+		napt_ct_counter_sync(hw_index);
+		#endif
+
+        if(NAPT_INVALID_CT_NEED_HW_CLEAR(hw_index))
+        {
+
+            uintptr_t ct_addr = napt_ct_addr[hw_index];
+            struct napt_ct *napt_ct = napt_ct_buf_ct_find(ct_addr);
+
+			HNAT_INFO_PRINTK("should hw clear for  %d\n", hw_index);
+
+            if(napt_ct_in_hw_sanity_check(napt_ct, hw_index) != 0)
+            {
+                HNAT_ERR_PRINTK("<%s> napt_ct_in_hw_sanity_check fail\n", __func__);
+                continue;
+            }
+
+            if(napt_ct_del_by_index(napt_ct, hw_index) == 0)
+            {
+                napt_ct_buf_deny_clear(napt_ct);
+            }
+            else
+            {
+                HNAT_ERR_PRINTK("<napt_ct_hw_sync>hw_index:%d napt_hw_del_by_index fail\n",
+                                hw_index);
+            }
+        }
+
+        if(napt_ct_valid[hw_index])
+        {
+            napt_ct_offload_cnt++;
+        }
+    }
+
+    return napt_ct_offload_cnt;
+}
+
+static void
+napt_ct_frag_hw_yield(struct napt_ct *napt_ct, a_uint16_t hw_index)
+{
+    napt_entry_t napt = {0};
+
+    /*os and hw are both traffic; hw offload giveup*/
+    if(napt_hw_get_by_index(&napt, hw_index) == 0)
+    {
+        if(napt.status == 0xe)
+        {
+            a_uint8_t deny = napt_ct_buf_deny_get(napt_ct);
+            napt_ct_buf_deny_set(napt_ct, (++deny));
+
+            if(deny >= NAPT_CT_PERMANENT_DENY)
+            {
+                /*os service only*/
+                HNAT_ERR_PRINTK("<napt_ct_frag_hw_yield> hw service deny\n");
+                napt_ct_del(napt_ct, &napt);
+            }
+
+            //printk("<napt_ct_frag_hw_yield> deny:%d\n", deny);
+        }
+    }
+}
+
+#define NAPT_CT_IS_REUSED_BY_OS(in_hw, ct_addr)   ((in_hw) && \
+                                    NAPT_CT_AGING_IS_ENABLE(ct_addr))
+static a_int32_t
+napt_ct_check_add_one(uintptr_t ct_addr, a_uint8_t *napt_ct_valid)
+{
+    struct napt_ct *napt_ct = NULL;
+    a_uint16_t hw_index;
+    a_uint8_t in_hw;
+
+    if((napt_ct = napt_ct_buf_ct_find(ct_addr)) == NULL)
+    {
+        if((napt_ct = napt_ct_buf_ct_add(ct_addr)) == NULL)
+        {
+            HNAT_ERR_PRINTK("<napt_ct_scan> error hash full\n");
+            return -1;
+        }
+    }
+
+    if(napt_ct_buf_deny_get(napt_ct) >= NAPT_CT_PERMANENT_DENY)
+    {
+        HNAT_INFO_PRINTK("<napt_ct_scan> ct:%x is PERMANENT deny\n",
+               ct_addr);
+        return -1;
+
+    }
+    else
+    {
+        if (napt_ct_pkts_reach_thres(ct_addr, napt_ct, 1))
+        {
+            if(napt_ct_buf_in_hw_get(napt_ct, &hw_index))
+            {
+                //printk("<napt_ct_scan> ct:%x* is exist\n", ct_addr);
+				if(nf_athrs17_hnat_sync_counter_en == 0)
+				{
+                	HNAT_ERR_PRINTK("<napt_ct_scan> ct:%x* is exist\n", ct_addr);
+                	napt_ct_frag_hw_yield(napt_ct, hw_index);
+				}
+            }
+            else
+            {
+                if(napt_ct_hw_add(ct_addr, &hw_index) == 0)
+                {
+                    NAPT_CT_AGING_DISABLE(ct_addr);
+	       napt_ct->last_jiffies = get_jiffies_64();
+
+                    napt_ct_buf_in_hw_set(napt_ct, hw_index);
+#ifdef NAT_TODO
+                    ct->in_hnat = 1; /* contrack in HNAT now. */
+#endif
+                }
+            }
+        } else {
+        	HNAT_INFO_PRINTK("can not reach thres for napt_ct=%pK\n", napt_ct);
+        }
+
+        in_hw = napt_ct_buf_in_hw_get(napt_ct, &hw_index);
+        if(in_hw)
+        {
+            if(!NAPT_CT_IS_REUSED_BY_OS(in_hw, ct_addr))
+            {
+                napt_ct_valid[hw_index] = 1;
+            }
+        }
+    }
+
+    return 0;
+}
+
+static void
+napt_ct_pkts_thres_calc_init(void)
+{
+    packets_bdir_total = 0;
+    packets_bdir_thres = packet_thres_base;
+
+}
+
+a_uint64_t
+uint64_div_uint32(a_uint64_t div, a_uint32_t base)
+{
+    register a_uint32_t i;
+    a_uint64_t result;
+
+    union
+    {
+        a_uint64_t n64[2];
+        struct
+        {
+            a_uint32_t l0;// 0
+            a_uint32_t h0;// 1
+            a_uint32_t l1;// 2
+            a_uint32_t h1;// 3
+        } n32;
+    } n;
+
+    if(base == 0)
+    {
+        return  0;
+    }
+
+    if(div < base)
+    {
+        return 0;
+    }
+
+    n.n64[0] = div;
+    n.n64[1] = 0;
+    result = 0;
+    i = 0;
+
+    //if div is 32bits, set start from 32
+    if(n.n32.h0 == 0)
+    {
+        n.n32.h0 = n.n32.l0;
+        n.n32.l0 = 0;
+        i = 32;
+    }
+
+    //left shift until highest bit
+    for(; i<64; ++i)
+    {
+        if((n.n32.h0 & 0x80000000) == 0x80000000)
+        {
+            break;
+        }
+        else
+        {
+            n.n64[0] = n.n64[0] << 1;
+        }
+    }
+
+    for (; i<64; ++i)
+    {
+        n.n64[1] = (n.n64[1] << 1) + (n.n64[0] >> 63);
+        n.n64[0] = (n.n64[0] << 1);
+        result = result << 1 ;
+
+        if(n.n64[1] >= base)
+        {
+            n.n64[1] = n.n64[1]- base;
+            ++result;
+        }
+    }
+
+    return result;
+}
+
+static void
+napt_ct_pkts_thres_calc(a_uint32_t cnt, a_uint32_t napt_ct_offload_cnt)
+{
+    a_uint64_t packets_bdir_avg = 0;
+    a_uint64_t packets_bdir_thres_temp = 0;
+
+    /*ct_avg_pkts* (1+ (ct_offload_cnt/ct_hw_max) )*/
+    packets_bdir_avg = uint64_div_uint32(packets_bdir_total, cnt);
+    packets_bdir_thres_temp = packets_bdir_avg +
+                              uint64_div_uint32((packets_bdir_avg *(a_uint64_t)napt_ct_offload_cnt),
+                                      NAPT_TABLE_SIZE);
+
+    if(packets_bdir_thres_temp > packet_thres_base)
+    {
+        packets_bdir_thres = packets_bdir_thres_temp;
+    }
+
+    //HNAT_ERR_PRINTK("###<%s> total:%lld cnt:%d avg:%lld  threshold:%lld###\n", __func__,
+    //    packets_bdir_total, cnt, packets_bdir_avg, packets_bdir_thres);
+    HNAT_INFO_PRINTK("calc pkts avg:%lld offload_cnt:%d threshold:%lld\n",
+                    packets_bdir_avg, napt_ct_offload_cnt, packets_bdir_thres);
+}
+
+#define NAPT_CT_SHOULD_CARE(ct) ((ct) && \
+                                  NAPT_CT_TYPE_IS_NAT(ct) && \
+                                  !NAPT_CT_TYPE_IS_NAT_ALG(ct) && \
+                                  NAPT_CT_INTF_EXPECTED(ct) && \
+                                  NAPT_CT_STATUS_IS_ESTAB(ct) &&\
+                                  nat_hw_prv_base_is_match( \
+                                            NAPT_CT_PRIV_IP_GET(ct)))
+a_uint8_t napt_ct_valid_tbl[NAPT_TABLE_SIZE] = {0};
+static a_int32_t
+napt_ct_check_add(void)
+{
+	uintptr_t ct_addr = 0;
+	a_uint32_t ct_buf_valid_cnt = 0, care_cnt = 0, ct_cnt = 0;
+	static a_uint32_t hash = 0;
+	uintptr_t iterate = 0;
+	a_uint32_t napt_ct_offload_cnt = 0;
+	a_uint16_t hw_index;
+
+	napt_ct_pkts_thres_calc_init();
+
+	NAPT_CT_LIST_LOCK();
+	while((ct_addr = NAPT_CT_LIST_ITERATE(&hash, &iterate)))
+	{
+		ct_cnt++;
+		if (NAPT_CT_SHOULD_CARE(ct_addr))
+		{
+			if(napt_ct_check_add_one(ct_addr, napt_ct_valid_tbl) != -1)
+			{
+				ct_buf_valid_cnt++;
+			}
+			care_cnt++;
+			if (care_cnt >= polling_quota) {
+				break;
+			}
+		}
+	}
+
+	NAPT_CT_LIST_UNLOCK();
+	HNAT_INFO_PRINTK("ct_cnt=0x%x, care_cnt=0x%x\n", ct_cnt, care_cnt);
+
+
+	if (!ct_addr) {
+		napt_ct_offload_cnt = napt_ct_hw_sync(napt_ct_valid_tbl);
+		napt_ct_pkts_thres_calc(ct_buf_valid_cnt, napt_ct_offload_cnt);
+		memset(napt_ct_valid_tbl, 0, NAPT_TABLE_SIZE);
+	}
+
+	for(hw_index = 0; hw_index < NAPT_TABLE_SIZE; hw_index++) {
+		if (nf_athrs17_hnat_sync_counter_en)
+			napt_ct_counter_sync(hw_index);
+		else
+			napt_ct_timer_update(hw_index);
+	}
+
+	return ct_buf_valid_cnt;
+}
+
+static a_int32_t
+napt_ct_add(uintptr_t ct_addr, a_uint8_t *napt_ct_valid)
+{
+    struct napt_ct *napt_ct;
+
+    if((napt_ct = napt_ct_buf_ct_add(ct_addr)) == NULL)
+    {
+        HNAT_ERR_PRINTK("<napt_ct_buffer_update> error hash full\n");
+        return -1;
+    }
+
+    return 0;
+}
+
+static a_int32_t
+napt_ct_buffer_ct_status_update(void)
+{
+    uintptr_t ct_addr = 0;
+    a_uint32_t hash = 0;
+    uintptr_t iterate = 0;
+
+    NAPT_CT_LIST_LOCK();
+
+    while((ct_addr = NAPT_CT_LIST_ITERATE(&hash, &iterate)))
+    {
+        if (NAPT_CT_SHOULD_CARE(ct_addr))
+        {
+            napt_ct_add(ct_addr, NULL);
+        }
+    }
+
+    NAPT_CT_LIST_UNLOCK();
+
+    return 0;
+}
+
+static void
+napt_ct_buffer_hw_status_update(void)
+{
+    a_uint16_t hw_index;
+
+    for(hw_index = 0; hw_index < NAPT_TABLE_SIZE; hw_index++)
+    {
+        uintptr_t ct_addr = napt_ct_addr[hw_index];
+        if(ct_addr)
+        {
+            struct napt_ct *napt_ct = napt_ct_buf_ct_find(ct_addr);
+            if(napt_ct)
+            {
+                napt_ct_buf_in_hw_set(napt_ct, hw_index);
+
+            }
+            else
+            {
+                if(napt_ct_del_by_index(napt_ct, hw_index) != 0)
+                {
+                    HNAT_ERR_PRINTK("<%s>hw_index:%d napt_ct_del_by_index fail\n",
+                                    __func__, hw_index);
+                }
+            }
+        }
+    }
+
+    return;
+}
+
+static void
+napt_ct_buffer_refresh(void)
+{
+    HNAT_INFO_PRINTK("napt_ct_buffer_refresh\n");
+
+    napt_ct_buf_flush();
+
+    napt_ct_buffer_ct_status_update();
+    napt_ct_buffer_hw_status_update();
+}
+
+static void
+napt_ct_buffer_refresh_check(a_uint32_t ct_buf_valid_cnt)
+{
+#define NAPT_CT_BUF_REFRESH_THRES             1000
+    HNAT_INFO_PRINTK("ct_buffer_hash_cnt:%d cnt:%d max:%d\n",
+                    napt_ct_cnt_get(), ct_buf_valid_cnt/2, NAPT_CT_BUF_REFRESH_THRES);
+
+    if((napt_ct_cnt_get() - ct_buf_valid_cnt/2) > NAPT_CT_BUF_REFRESH_THRES)
+    {
+        napt_ct_buffer_refresh();
+    }
+}
+
+static void
+napt_ct_hw_exit(void)
+{
+    a_uint8_t napt_ct_valid[NAPT_TABLE_SIZE];
+
+    /*set all ct invalid to cleanup*/
+    memset(napt_ct_valid, 0, sizeof(napt_ct_valid));
+
+    napt_ct_hw_sync(napt_ct_valid);
+}
+
+void
+napt_ct_scan(void)
+{
+    a_uint32_t ct_buf_valid_cnt = 0;
+
+    ct_buf_valid_cnt = napt_ct_check_add();
+
+    napt_ct_buffer_refresh_check(ct_buf_valid_cnt);
+}
+
+void napt_wan_switch_prehandle(void)
+{
+	if (wan_switch) {
+		napt_thread_pending = 1;
+		L3_STATUS_SET(0, A_FALSE);
+		napt_ct_hw_exit();
+		napt_hw_flush();
+		qcaswitch_hostentry_flush();
+		droute_del_acl_rules();
+		ipv6_droute_del_acl_rules();
+		if (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOE)
+			pppoe_del_acl_rules();
+		#ifdef MULTIROUTE_WR
+		ip_conflict_del_acl_rules();
+		#endif
+		if_mac_cleanup();
+		L3_STATUS_SET(0, A_TRUE);
+		napt_thread_pending = 0;
+	}
+}
+
+static a_int32_t
+napt_ct_init(void)
+{
+	if(nf_athrs17_hnat_sync_counter_en == 0)
+	{
+		napt_buffer_hash_size = NAPT_TABLE_SIZE;
+		napt_buffer_size = NAPT_TABLE_SIZE*8;
+	}
+	else
+	{
+		napt_buffer_hash_size = 8;
+		napt_buffer_size = NAPT_TABLE_SIZE;
+	}
+
+    napt_hw_mode_init();
+
+    if(napt_ct_buf_init() != 0)
+    {
+        HNAT_ERR_PRINTK("*****napt_ct_buf_init fail*******\n");
+        return -1;
+    }
+
+    return 0;
+}
+
+static a_int32_t
+napt_ct_exit(void)
+{
+    napt_hw_mode_cleanup();
+
+    napt_ct_hw_exit();
+    napt_ct_buf_exit();
+
+    return 0;
+}
+
+static a_int32_t
+napt_ct_scan_thread(void *param)
+{
+#define NAPT_CT_AGING_SEC           20
+#define ARP_CHECK_AGING_SEC       40
+
+    a_uint32_t times = (NAPT_CT_AGING_SEC/scan_period);
+    a_uint32_t arp_check_time = (ARP_CHECK_AGING_SEC/scan_period);
+    // a_bool_t l3_enable;
+
+    if(napt_ct_init() != 0)
+    {
+        return 0;
+    }
+
+    while(1)
+    {
+		if(!nat_sockopts_init) {
+			nat_ipt_sockopts_replace();
+		}
+		if (napt_thread_pending) {
+			NAPT_CT_TASK_SLEEP(scan_period);
+			continue;
+		}
+
+		if (scan_enable) {
+			if((--times) == 0)
+			{
+				HNAT_PRINTK("[ct hw aging start]\n");
+				napt_ct_hw_aging();
+				HNAT_PRINTK("[ct hw aging end]\n");
+				times = (NAPT_CT_AGING_SEC/scan_period);
+			}
+
+			if((--arp_check_time) == 0)
+			{
+				host_check_aging();
+				arp_check_time = (ARP_CHECK_AGING_SEC/scan_period);
+			}
+
+			if (times != NAPT_CT_AGING_SEC/scan_period) {
+				HNAT_PRINTK("[ct scan start]\n");
+				napt_ct_scan();
+				HNAT_PRINTK("[ct scan end]\n");
+			}
+		} else {
+			if (napt_need_clean) {
+				napt_need_clean = 0;
+				napt_ct_hw_exit();
+			}
+		}
+
+#ifdef ISISC /* only for S17c */
+#ifdef CONFIG_IPV6_HWACCEL
+		napt_set_ipv6_default_route();
+#endif
+#endif
+        
+		if (NAPT_CT_TASK_SHOULD_STOP()) {
+			printk("should stop!\n");
+			break;
+		}
+
+		NAPT_CT_TASK_SLEEP(scan_period);
+	}
+
+    napt_ct_exit();
+
+    return 0;
+}
+
+void napt_helper_show(void)
+{
+	a_uint16_t hw_index;
+	for(hw_index = 0; hw_index < NAPT_TABLE_SIZE; hw_index++) {
+		if (napt_ct_addr[hw_index]) {
+			printk("index[%d] exist: 0x%lx\n", hw_index, (a_ulong_t)napt_ct_addr[hw_index]);
+		}
+	}
+	printk("current hardware offload count: 0x%x\n", napt_ct_hw_cnt);
+	printk("interate:0x%x, care:0x%x, low_thresh=0x%x\n",
+			napt_ct_debug_info.interate_cnt,
+			napt_ct_debug_info.care_cnt,
+			napt_ct_debug_info.thresh_low_cnt);
+}
+
+void
+napt_helper_init(void)
+{
+    const char napt_thread_name[] = "napt_ct_scan";
+
+    NAPT_CT_TASK_START(napt_ct_scan_thread, napt_thread_name);
+}
+
+
+void
+napt_helper_exit(void)
+{
+    NAPT_CT_TASK_STOP();
+}
+
diff --git a/qca-ssdk/app/nathelper/linux/lib/nat_helper_dt.h b/qca-ssdk/app/nathelper/linux/lib/nat_helper_dt.h
new file mode 100755
index 0000000..bd3550b
--- /dev/null
+++ b/qca-ssdk/app/nathelper/linux/lib/nat_helper_dt.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _NAT_HELPER_DT_H
+#define _NAT_HELPER_DT_H
+
+extern void host_check_aging(void);
+void napt_ct_counter_decrease(void);
+
+#endif /*_NAT_HELPER_DT_H*/
diff --git a/qca-ssdk/app/nathelper/linux/lib/nat_helper_hsl.c b/qca-ssdk/app/nathelper/linux/lib/nat_helper_hsl.c
new file mode 100755
index 0000000..a186690
--- /dev/null
+++ b/qca-ssdk/app/nathelper/linux/lib/nat_helper_hsl.c
@@ -0,0 +1,879 @@
+/*
+ * Copyright (c) 2012, 2015, 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifdef KVER32
+#include <linux/kconfig.h> 
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#endif
+#include <linux/if_arp.h>
+#include <linux/netdevice.h>
+#include <linux/netfilter_arp.h>
+#include <linux/netfilter_ipv4/ip_tables.h>
+#include <net/netfilter/nf_conntrack.h>
+
+#include "fal_nat.h"
+#include "fal_ip.h"
+
+#include "hsl_api.h"
+#include "hsl.h"
+#include "hsl_shared_api.h"
+#include "../nat_helper.h"
+#include "nat_helper_dt.h"
+#include "nat_helper_hsl.h"
+#include "../napt_acl.h"
+
+int nat_chip_ver = 0;
+a_bool_t napt_add_bypass_check = A_TRUE;
+
+/* support 4 different interfaces (or 4 VLANs) */
+static fal_intf_mac_entry_t global_if_mac_entry[MAX_INTF_NUM] = {{0}};
+static a_uint8_t if_mac_count = 0;
+
+extern int setup_wan_if;
+extern int setup_lan_if;
+
+#define DESS_CHIP(ver) ((((ver)&0xffff)>>8) == NAT_CHIP_VER_DESS)
+
+#define ARP_HW_COUNTER_OFFSET  8
+
+static a_uint8_t
+nat_hw_debug_counter_get(void)
+{
+    static a_uint32_t nat_debug_counter = 0;
+
+    return ((nat_debug_counter++) & 0x7);
+}
+
+static a_uint8_t
+arp_hw_debug_counter_get(void)
+{
+    static a_uint32_t ip_debug_counter = 0;
+
+    return ((ip_debug_counter++) & 0x7) + ARP_HW_COUNTER_OFFSET;
+}
+
+
+a_int32_t
+nat_hw_add(nat_entry_t *nat)
+{
+    fal_nat_entry_t hw_nat = {0};
+
+    hw_nat.flags = nat->flags;
+    hw_nat.src_addr = nat->src_addr;
+    hw_nat.trans_addr = nat->trans_addr;
+    hw_nat.port_num = nat->port_num;
+    hw_nat.port_range = nat->port_range;
+    hw_nat.counter_en = 1;
+    hw_nat.counter_id = nat_hw_debug_counter_get();
+
+    if(NAT_ADD(0, &hw_nat) != 0)
+    {
+        return -1;
+    }
+    nat->entry_id = hw_nat.entry_id;
+
+    return 0;
+}
+
+a_int32_t
+nat_hw_del_by_index(a_uint32_t index)
+{
+    fal_nat_entry_t nat_entry = {0};
+
+    HNAT_PRINTK("NAT_DEL(1) index=%d########\n", index);
+
+    nat_entry.entry_id = index;
+    if(NAT_DEL(0, FAL_NAT_ENTRY_ID_EN, &nat_entry)!= 0)
+    {
+        return -1;
+    }
+
+    return 0;
+}
+
+a_int32_t
+nat_hw_flush(void)
+{
+    if(NAT_DEL(0, 0, 0)!= 0)
+    {
+        return -1;
+    }
+
+    return 0;
+}
+
+a_int32_t
+napt_hw_flush(void)
+{
+    if(NAPT_DEL(0, 0, 0)!= 0)
+    {
+        return -1;
+    }
+
+    return 0;
+}
+
+static a_uint32_t private_ip_can_update = 1;
+a_int32_t
+nat_hw_prv_base_can_update(void)
+{
+    return private_ip_can_update;
+}
+
+void
+nat_hw_prv_base_update_enable(void)
+{
+    private_ip_can_update = 1;
+}
+
+void
+nat_hw_prv_base_update_disable(void)
+{
+    private_ip_can_update = 0;
+}
+
+static a_uint32_t private_ip_base = 0xc0a80000;
+static a_uint32_t private_net_mask = 0xffffff00;
+a_int32_t
+nat_hw_prv_base_set(a_uint32_t ip)
+{
+#define PRIVATE_IP_MASK 0xffffff00
+
+    ip = ntohl(ip);
+
+	if (((nat_chip_ver & 0xffff) >> 8) == NAT_CHIP_VER_8327)
+    		private_ip_base = ip & PRIVATE_IP_MASK;
+	else
+		private_ip_base = ip & nat_hw_prv_mask_get();
+
+
+	if(DESS_CHIP(nat_chip_ver)) {
+		if (IP_PRV_BASE_ADDR_SET(0, 0, (fal_ip4_addr_t)ip) != 0)
+	    {
+	        return -1;
+	    }
+	} else {
+	    if (NAT_PRV_BASE_ADDR_SET(0, (fal_ip4_addr_t)ip) != 0)
+	    {
+	        return -1;
+	    }
+	}
+
+    HNAT_PRINTK("%s: private_ip_base:%x private_ip_can_update:%d\n",
+                __func__, private_ip_base, private_ip_can_update);
+
+    return 0;
+}
+
+a_uint32_t
+nat_hw_prv_base_get(void)
+{
+    return private_ip_base;
+}
+
+
+a_int32_t
+nat_hw_prv_mask_set(a_uint32_t ipmask)
+{
+    ipmask = ntohl(ipmask);
+
+	if(DESS_CHIP(nat_chip_ver)) {
+		if (IP_PRV_BASE_MASK_SET(0, 0, (fal_ip4_addr_t)ipmask) != 0)
+	    {
+	        return -1;
+	    }
+	} else if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8337) {
+	    if (NAT_PRV_BASE_MASK_SET(0, (fal_ip4_addr_t)ipmask) != 0)
+	    {
+	        return -1;
+	    }
+	}
+    private_net_mask = ipmask;
+
+    HNAT_PRINTK("%s: 0x%08x\n", __FUNCTION__, private_net_mask);
+
+    return 0;
+}
+
+a_uint32_t
+nat_hw_prv_mask_get(void)
+{
+    return private_net_mask;
+}
+
+
+a_int32_t
+nat_hw_prv_base_is_match(a_uint32_t ip)
+{
+#define PRIVATE_IP_MASK 0xffffff00
+
+    a_uint32_t prv_base = private_ip_base;
+    a_uint32_t prv_mask;
+
+	if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8327) {
+    		if((prv_base & PRIVATE_IP_MASK) == (ip & PRIVATE_IP_MASK))
+				return 1;
+	} else {
+		prv_mask = nat_hw_prv_mask_get();
+		if((prv_base & prv_mask) == (ip & prv_mask))
+        		return 1;
+	}
+
+    HNAT_PRINTK("%s: private_ip_base:%x usaddr:%x mismatch\n",
+                __func__, prv_base, ip);
+
+    return 0;
+}
+
+static a_int32_t
+_arp_hw_if_mac_add(fal_intf_mac_entry_t *if_mac_entry)
+{
+    return IP_INTF_ENTRY_ADD(0, if_mac_entry);
+}
+
+static a_int32_t
+_arp_hw_if_mac_del(fal_intf_mac_entry_t *if_mac_entry)
+{
+    return IP_INTF_ENTRY_DEL(0, FAL_IP_ENTRY_ID_EN, if_mac_entry);
+}
+
+a_int32_t
+if_mac_cleanup(void)
+{
+	a_uint8_t i = 0;
+
+	if_mac_count = 0;
+	for(i = 0; i < MAX_INTF_NUM; i++)
+	{
+		if(_arp_hw_if_mac_del(&global_if_mac_entry[i]) != 0) {
+			printk("mac del fail!\n");
+			return -1;
+		}
+		memset(&global_if_mac_entry[i], 0, sizeof(fal_intf_mac_entry_t));
+	}
+
+	setup_wan_if = 0;
+	setup_lan_if = 0;
+
+	return 0;
+}
+
+#define MACADDR_LEN	6
+a_int32_t
+if_mac_add(a_uint8_t *mac, a_uint32_t vid, uint32_t ipv6)
+{
+    a_uint8_t i = 0;
+    a_uint8_t zero_mac[MACADDR_LEN] = {0};
+
+    if (!memcmp(mac, zero_mac, MACADDR_LEN))
+        return 0;
+
+    if(if_mac_count > MAX_INTF_NUM)
+        return -1;
+
+    for(i = 0; i < if_mac_count; i++)
+    {
+        if((!memcmp(global_if_mac_entry[i].mac_addr.uc, mac, 6)) &&
+                (global_if_mac_entry[i].vid_low == vid))
+        {
+            HNAT_PRINTK("%s: mac exist id:%d\n", __func__,
+                        global_if_mac_entry[i].entry_id);
+            return 0;
+        }
+    }
+
+    if(if_mac_count == MAX_INTF_NUM)
+    {
+        HNAT_ERR_PRINTK("%s: reach mac count max\n", __func__);
+        return -1;
+    }
+
+    memset(&global_if_mac_entry[if_mac_count], 0, sizeof(fal_intf_mac_entry_t));
+    memcpy(global_if_mac_entry[if_mac_count].mac_addr.uc, mac, 6);
+
+    global_if_mac_entry[if_mac_count].entry_id = if_mac_count;
+    if (1 == ipv6)
+    {
+        global_if_mac_entry[if_mac_count].ip6_route = 1;
+    }
+    else
+    {
+        global_if_mac_entry[if_mac_count].ip6_route = 0;
+    }
+    global_if_mac_entry[if_mac_count].ip4_route = 1;
+
+    if (vid == 0)
+    {
+        global_if_mac_entry[if_mac_count].vid_low = 0;
+        global_if_mac_entry[if_mac_count].vid_high = 511;
+    }
+    else
+    {
+        global_if_mac_entry[if_mac_count].vid_low = vid;
+        global_if_mac_entry[if_mac_count].vid_high = vid;
+    }
+
+    if(_arp_hw_if_mac_add(&global_if_mac_entry[if_mac_count])!= 0)
+    {
+        return -1;
+    }
+
+    HNAT_PRINTK("%s: count:%d index:%d vid:%d  mac:%02x-%02x-%02x-%02x-%02x-%02x\n",
+                __func__, if_mac_count, global_if_mac_entry[if_mac_count].entry_id, vid,
+                mac[0],mac[1],mac[2],mac[3],mac[4],mac[5]);
+    if_mac_count ++;
+
+    return 0;
+}
+
+static a_int32_t
+_arp_hw_add(fal_host_entry_t *arp_entry)
+{
+    return IP_HOST_ADD(0, arp_entry);
+}
+
+a_int32_t
+arp_hw_add(a_uint32_t port, a_uint32_t intf_id, a_uint8_t *ip, a_uint8_t *mac, int is_ipv6_entry)
+{
+    fal_host_entry_t arp_entry;
+
+
+#ifdef ISIS /* Only for AR8337(S17) */
+    if (NF_S17_WAN_TYPE_PPPOEV6 == nf_athrs17_hnat_wan_type)
+    {
+        memset(&arp_entry,0,sizeof(arp_entry));
+        memcpy(&arp_entry.ip4_addr, ip, 4);
+        memcpy(arp_entry.mac_addr.uc, mac, 6);
+        arp_entry.status = ARP_AGE_NEVER;
+        if (port == S17_WAN_PORT)
+        {
+            arp_entry.port_id = port;
+        }
+	 else
+        {
+            arp_entry.port_id = 6; /* always assigned to MAC 6 */
+        }
+        arp_entry.flags = FAL_IP_IP4_ADDR;
+    }
+    else
+#endif /* not ISIS */
+    {
+        memset(&arp_entry,0,sizeof(arp_entry));
+        if (0 == is_ipv6_entry)
+        {
+            memcpy(&arp_entry.ip4_addr, ip, 4);
+            arp_entry.ip4_addr = ntohl(arp_entry.ip4_addr);
+            arp_entry.flags = FAL_IP_IP4_ADDR;
+        }
+        else
+        {
+            memcpy(&arp_entry.ip6_addr, ip, 16);
+            arp_entry.flags = FAL_IP_IP6_ADDR;
+        }
+        memcpy(arp_entry.mac_addr.uc, mac, 6);
+        if ((NF_S17_WAN_TYPE_PPPOE == nf_athrs17_hnat_wan_type) && \
+            (S17_WAN_PORT == port))
+        {
+            arp_entry.status = ARP_AGE_NEVER;
+        }
+        else
+        {
+            arp_entry.status = ARP_AGE;
+        }
+        arp_entry.port_id = port;
+    }
+
+    arp_entry.intf_id = intf_id;
+
+    arp_entry.counter_en = 1;
+    if (S17_WAN_PORT == port)
+    {
+        arp_entry.counter_id = 0xf;
+    }
+    else
+    {
+        arp_entry.counter_id = arp_hw_debug_counter_get();
+    }
+
+	if (IP_HOST_GET(0, 0x10, &arp_entry)) {
+		HNAT_PRINTK("new arp for 0x%x\n", arp_entry.ip4_addr);
+		if(_arp_hw_add(&arp_entry) != 0)
+		{
+			HNAT_ERR_PRINTK("%s: fail\n", __func__);
+			return -1;
+		}
+	}
+
+    if (0 == is_ipv6_entry)
+    {
+        HNAT_PRINTK("%s: index:%x  port:%d ip:%d.%d.%d.%d\n",
+                    __func__, arp_entry.entry_id, port,
+                    *(ip), *(ip+1), *(ip+2), *(ip+3));
+    }
+    
+    if (0 != (arp_entry.entry_id & 0xFFFFFC00))
+    {
+        printk("Warning: arp_entry id should be only 10 bits!\n");
+    }
+
+    return arp_entry.entry_id;
+}
+
+#define AOS_HEADER_MAGIC 0xC0DE
+
+a_int32_t
+arp_if_info_get(void *data, a_uint32_t *sport, a_uint32_t *vid)
+{
+	aos_header_t *athr_header = NULL;
+    if((data==0) || (sport==0) || (vid==0))
+    {
+        return -1;
+    }
+
+	athr_header = (aos_header_t *)data;
+
+#if 0
+    /*atheros header magic check*/
+    if(athr_header->magic != AOS_HEADER_MAGIC)
+    {
+        return -1;
+    }
+#endif
+
+    *sport = athr_header->sport;
+    *vid = athr_header->vid;
+
+    return 0;
+}
+
+#define MAX_PUBLIC_IP_CNT 16
+struct public_ip_shadow
+{
+    a_uint32_t   ip;
+    a_uint32_t   use_cnt;
+};
+
+static struct public_ip_shadow public_ip_shadow[MAX_PUBLIC_IP_CNT]= {{0}};
+static a_uint32_t public_ip_cnt = 0;
+
+a_int32_t
+nat_hw_pub_ip_add(a_uint32_t ip, a_uint32_t *index)
+{
+    sw_error_t rv;
+    a_uint32_t hw_index;
+    a_uint32_t i;
+	fal_nat_pub_addr_t ip_entry;
+
+    for(i=0; i<MAX_PUBLIC_IP_CNT; i++)
+    {
+        if((ip == public_ip_shadow[i].ip) && (public_ip_shadow[i].use_cnt))
+        {
+            public_ip_shadow[i].use_cnt++;
+            *index = i;
+            return 0;
+        }
+    }
+
+    if(public_ip_cnt >= MAX_PUBLIC_IP_CNT)
+    {
+        return -1;
+    }
+
+	memset(&ip_entry, 0, sizeof(ip_entry));
+    ip_entry.pub_addr = ip;
+    rv = NAT_PUB_ADDR_ADD(0,&ip_entry);
+    if(rv != 0)
+    {
+        return -1;
+    }
+
+    public_ip_cnt++;
+    hw_index = ip_entry.entry_id;
+    public_ip_shadow[hw_index].ip = ip;
+    public_ip_shadow[hw_index].use_cnt++;
+    *index = hw_index;
+
+    HNAT_PRINTK("%s: public_ip_cnt:%d index:%d ip:0x%x\n",
+                __func__, public_ip_cnt, hw_index, public_ip_shadow[hw_index].ip);
+    return 0;
+}
+
+
+void
+napt_hw_mode_init(void)
+{
+    sw_error_t rv;
+    /* age_speedup+age_thres_1/4+age_step_4+age_timer_28s*1+
+       stop_age_when1+overwrite_disable */
+    /* Also set NAT mode Port strict mode/symmetric mode */
+    a_uint32_t entry = 0x15F01CB;
+
+    REG_ENTRY_SET(rv, 0, NAT_CTRL, 0, (a_uint8_t *) (&entry),
+                      sizeof (a_uint32_t));
+
+    REG_ENTRY_GET(rv, 0, ROUTER_CTRL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+
+    /*set locktime 100us*/
+    SW_SET_REG_BY_FIELD(ROUTER_CTRL, GLB_LOCKTIME, 1, entry);
+    SW_SET_REG_BY_FIELD(ROUTER_CTRL, ARP_AGE_MODE, 1, entry);
+
+    REG_ENTRY_SET(rv, 0, ROUTER_CTRL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    REG_ENTRY_GET(rv, 0, MOD_ENABLE, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_SET_REG_BY_FIELD(MOD_ENABLE, L3_EN, 1, entry);
+    REG_ENTRY_SET(rv, 0, MOD_ENABLE, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+
+    ACL_STATUS_SET(0, A_TRUE);
+}
+
+void
+napt_hw_mode_cleanup(void)
+{
+	a_uint32_t entry;
+	sw_error_t rv;
+	if (!DESS_CHIP(nat_chip_ver)) {
+		IP_ROUTE_STATUS_SET(0, A_FALSE);
+		entry = 0;
+	} else {
+		REG_ENTRY_GET(rv, 0, NAT_CTRL, 0,
+                      		(a_uint8_t *) (&entry), sizeof (a_uint32_t));
+		SW_SET_REG_BY_FIELD(NAT_CTRL, NAT_EN, 0, entry);
+	}
+	REG_ENTRY_SET(rv, 0, NAT_CTRL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+	ACL_STATUS_SET(0, A_FALSE);
+}
+
+a_int32_t
+nat_hw_pub_ip_del(a_uint32_t index)
+{
+    sw_error_t rv;
+
+    if(public_ip_shadow[index].use_cnt>0)
+    {
+        public_ip_shadow[index].use_cnt--;
+        if(public_ip_shadow[index].use_cnt == 0)
+        {
+			fal_nat_pub_addr_t ip_entry;
+            HNAT_PRINTK("%s: public_ip_cnt:%d index:%d ip:0x%x\n",
+                        __func__, public_ip_cnt, index, public_ip_shadow[index].ip);
+            memset(&ip_entry,0,sizeof(ip_entry));
+            ip_entry.pub_addr = public_ip_shadow[index].ip;
+            rv = NAT_PUB_ADDR_DEL(0, 1, &ip_entry);
+            if(rv != 0)
+            {
+                return -1;
+            }
+
+            public_ip_cnt--;
+        }
+        return 0;
+    }
+
+    return -1;
+}
+
+#define napt_entry_cp(to, from) \
+{ \
+    (to)->entry_id = (from)->entry_id; \
+    (to)->status = (from)->status; \
+    (to)->flags = (from)->flags; \
+    (to)->src_addr = (from)->src_addr; \
+    (to)->src_port = (from)->src_port; \
+    (to)->dst_addr = (from)->dst_addr; \
+    (to)->dst_port = (from)->dst_port; \
+    (to)->trans_addr = (from)->trans_addr; \
+    (to)->trans_port = (from)->trans_port; \
+    (to)->ingress_packet = (from)->ingress_packet; \
+    (to)->ingress_byte = (from)->ingress_byte; \
+    (to)->egress_packet = (from)->egress_packet; \
+    (to)->egress_byte = (from)->egress_byte; \
+}
+
+a_int32_t
+napt_hw_add(napt_entry_t *napt)
+{
+	a_int32_t ret = 0;
+	fal_napt_entry_t fal_napt = {0};
+	fal_host_entry_t host_entry = {0};
+	a_uint32_t next_hop = 0;
+
+	napt_entry_cp(&fal_napt, napt);
+
+	fal_napt.flags |= FAL_NAT_ENTRY_TRANS_IPADDR_INDEX;
+	fal_napt.counter_en = 1;
+	fal_napt.counter_id = nat_hw_debug_counter_get();
+	fal_napt.action = FAL_MAC_FRWRD;
+
+	if (!napt_add_bypass_check) {
+		/*check arp entry*/
+		host_entry.flags = FAL_IP_IP4_ADDR;
+		host_entry.ip4_addr = fal_napt.src_addr;
+		ret = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &host_entry);
+		if (ret) {
+			HNAT_ERR_PRINTK("can not find src host entry!\n");
+			return ret;
+		}
+		if (nf_athrs17_hnat_wan_type != NF_S17_WAN_TYPE_PPPOE) {
+			next_hop = get_next_hop(fal_napt.dst_addr, fal_napt.src_addr);
+			host_entry.ip4_addr =  next_hop ? next_hop : fal_napt.dst_addr;
+			ret = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &host_entry);
+			if (ret) {
+				HNAT_ERR_PRINTK("can not find dst host entry!\n");
+				return ret;
+			}
+		}
+	}
+
+	ret = NAPT_ADD(0, &fal_napt);
+
+	napt->entry_id = fal_napt.entry_id;
+	return ret;
+}
+
+a_int32_t
+napt_hw_get(napt_entry_t *napt, fal_napt_entry_t *entry)
+{
+	a_int32_t ret = 0;
+	fal_napt_entry_t fal_napt = {0};
+
+	napt_entry_cp(&fal_napt, napt);
+
+	ret = NAPT_GET(0, 0, &fal_napt);
+
+	if(!ret)
+		*entry = fal_napt;
+	return ret;
+}
+
+a_int32_t
+napt_hw_dnat_cookie_add(napt_entry_t *napt, a_uint32_t cookie)
+{
+	a_int32_t ret = 0;
+	fal_napt_entry_t fal_napt = {0};
+	fal_napt.flags = napt->flags | 0x10;
+	fal_napt.status = 0xf;
+	fal_napt.dst_addr = napt->dst_addr;
+	fal_napt.dst_port = napt->dst_port;
+	fal_napt.trans_addr = napt->trans_addr;
+	fal_napt.trans_port = napt->trans_port;
+	fal_napt.src_port = napt->src_port;
+	fal_napt.action = FAL_MAC_RDT_TO_CPU;
+	fal_napt.flow_cookie = cookie;
+	ret = NAPT_ADD(0, &fal_napt);
+	return ret;
+}
+
+a_int32_t
+napt_hw_snat_cookie_add(napt_entry_t *napt, a_uint32_t cookie)
+{
+	a_int32_t ret = 0;
+	fal_napt_entry_t fal_napt = {0};
+	fal_napt.flags = napt->flags | 0x10;
+	fal_napt.status = 0xf;
+	fal_napt.dst_addr = napt->dst_addr;
+	fal_napt.dst_port = napt->dst_port;
+	fal_napt.src_addr = napt->src_addr;
+	fal_napt.src_port = napt->src_port;
+	fal_napt.trans_port = napt->trans_port;
+	fal_napt.action = FAL_MAC_RDT_TO_CPU;
+	fal_napt.flow_cookie = cookie;
+	ret = NAPT_ADD(0, &fal_napt);
+	return ret;
+}
+
+
+
+
+a_int32_t
+napt_hw_del(napt_entry_t *napt)
+{
+    a_int32_t ret = 0;
+
+    fal_napt_entry_t fal_napt = {0};
+
+    napt_entry_cp(&fal_napt, napt);
+	napt_ct_counter_decrease();
+
+    ret = NAPT_DEL(0, FAL_NAT_ENTRY_KEY_EN, &fal_napt);
+
+    if(ret != 0)
+    {
+        return -1;
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+a_int32_t
+napt_hw_first_by_age(napt_entry_t *napt, a_uint32_t age)
+{
+    a_int32_t ret = 0;
+    fal_napt_entry_t fal_napt = {0};
+
+    fal_napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+    fal_napt.status = age;
+
+    if(NAPT_NEXT(0, FAL_NAT_ENTRY_AGE_EN ,&fal_napt) !=0)
+    {
+        ret = -1;
+    }
+
+    napt_entry_cp(napt, &fal_napt);
+
+    return ret;
+}
+
+a_int32_t
+napt_hw_next_by_age(napt_entry_t *napt, a_uint32_t age)
+{
+    a_int32_t ret = 0;
+    fal_napt_entry_t fal_napt = {0};
+
+    fal_napt.entry_id = napt->entry_id;
+    fal_napt.status = age;
+
+    if(NAPT_NEXT(0, FAL_NAT_ENTRY_AGE_EN ,&fal_napt) !=0)
+    {
+        ret = -1;
+    }
+
+    napt_entry_cp(napt, &fal_napt);
+
+    return ret;
+}
+
+a_int32_t
+napt_hw_get_by_index(napt_entry_t *napt, a_uint16_t hw_index)
+{
+    fal_napt_entry_t fal_napt = {0};
+	sw_error_t rv;
+
+    if(hw_index == 0)
+    {
+        fal_napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+    }
+    else
+    {
+        fal_napt.entry_id = hw_index - 1;
+    }
+
+    if((rv = NAPT_NEXT(0, 0, &fal_napt)) != 0)
+    {
+        HNAT_ERR_PRINTK("<napt_hw_get_by_index>[rv:%d] error hw:%x sw:%x\n",
+                        rv, napt->entry_id, hw_index);
+        return -1;
+    }
+
+    napt_entry_cp(napt, &fal_napt);
+
+    if(napt->entry_id != hw_index)
+    {
+        HNAT_ERR_PRINTK("<napt_hw_get_by_index>hw_index error hw:%x sw:%x\n",
+                        napt->entry_id, hw_index);
+        return -1;
+    }
+
+    return 0;
+}
+
+a_int32_t napt_hw_get_by_sip(a_uint32_t sip)
+{
+	fal_napt_entry_t napt;
+
+	memset(&napt, 0, sizeof(fal_napt_entry_t));
+	napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+	napt.src_addr = sip;
+	if (NAPT_NEXT(0, FAL_NAT_ENTRY_SOURCE_IP_EN, &napt) == SW_OK) {
+		return 0;
+	}
+
+	return -1;
+}
+
+a_uint32_t
+napt_hw_used_count_get(void)
+{
+#define NAPT_USED_COUNT
+#define NAPT_USED_COUNT_OFFSET                       0x0e44 /*was:0x0e38*/
+#define NAPT_USED_COUNT_E_LENGTH                     11
+#define NAPT_USED_COUNT_E_OFFSET                     0x0
+#define NAPT_USED_COUNT_NR_E                         1
+    sw_error_t rv;
+
+    a_uint32_t count = 0;
+    REG_ENTRY_GET(rv, 0, NAPT_USED_COUNT, 0, (a_uint8_t *) (&count),
+                      sizeof (a_uint32_t));
+
+    return count;
+}
+
+sw_error_t napt_l3_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, L3_EN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+sw_error_t napt_l3_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, L3_EN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t napt_helper_hsl_init()
+{
+	return SW_OK;
+}
+
+
diff --git a/qca-ssdk/app/nathelper/linux/lib/nat_helper_hsl.h b/qca-ssdk/app/nathelper/linux/lib/nat_helper_hsl.h
new file mode 100755
index 0000000..3cae382
--- /dev/null
+++ b/qca-ssdk/app/nathelper/linux/lib/nat_helper_hsl.h
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2012, 2015, 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _NAT_HELPER_HSL_H
+#define _NAT_HELPER_HSL_H
+
+#ifdef KVER32
+#include <linux/kconfig.h> 
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#endif
+
+#include <linux/if_ether.h>
+#include "fal_nat.h"
+
+#define NAT_HW_NUM 32
+#define NAT_HW_PORT_RANGE_MAX 255
+
+#define FAL_NAT_ENTRY_PROTOCOL_TCP         0x1
+#define FAL_NAT_ENTRY_PROTOCOL_UDP         0x2
+#define FAL_NAT_ENTRY_PROTOCOL_PPTP        0x4
+#define FAL_NAT_ENTRY_PROTOCOL_ANY         0x8
+#define FAL_NAT_ENTRY_PORT_CHECK           0x20
+
+#define MAX_INTF_NUM    4
+
+/* WAN connection types */
+#define NF_S17_WAN_TYPE_IP  0   /* DHCP, static IP connection */
+#define NF_S17_WAN_TYPE_PPPOE   1   /* PPPoE connection */
+#define NF_S17_WAN_TYPE_GRE 2   /* GRE connections, ex: PPTP */
+#define NF_S17_WAN_TYPE_PPPOEV6 3   /* IPv6 PPPoE connection  using the same session as IPv4 connection */
+#define NF_S17_WAN_TYPE_PPPOES0 4   /* PPPoE connection but not yet connected */
+/* define the H/W Age mode for NAPT entries */
+#define ARP_AGE_NEVER   7
+#define ARP_AGE 6
+
+#if !defined (HSL_STANDALONG)
+extern a_uint32_t nat_dev_id;
+
+/*NAT API*/
+#define NAPT_ADD(dev_id, ...) fal_napt_add(nat_dev_id, ##__VA_ARGS__)
+#define NAPT_GET(dev_id, ...) fal_napt_get(nat_dev_id, ##__VA_ARGS__)
+#define NAT_PUB_ADDR_ADD(dev_id, ...) fal_nat_pub_addr_add(nat_dev_id, ##__VA_ARGS__)
+#define NAPT_NEXT(dev_id, ...) fal_napt_next(nat_dev_id, ##__VA_ARGS__)
+#define NAT_PRV_BASE_ADDR_SET(dev_id, ...) fal_nat_prv_base_addr_set(nat_dev_id, ##__VA_ARGS__)
+#define NAT_PRV_BASE_MASK_SET(dev_id, ...) fal_nat_prv_base_mask_set(nat_dev_id, ##__VA_ARGS__)
+#define NAPT_DEL(dev_id, ...) fal_napt_del(nat_dev_id, ##__VA_ARGS__)
+#define NAT_DEL(dev_id, ...) fal_nat_del(nat_dev_id, ##__VA_ARGS__)
+#define NAT_PUB_ADDR_DEL(dev_id, ...) fal_nat_pub_addr_del(nat_dev_id, ##__VA_ARGS__)
+#define NAT_ADD(dev_id, ...) fal_nat_add(nat_dev_id, ##__VA_ARGS__)
+#define NAT_PRV_ADDR_MODE_GET(dev_id, ...) fal_nat_prv_addr_mode_get(nat_dev_id, ##__VA_ARGS__)
+
+/*IP API*/
+#define IP_INTF_ENTRY_ADD(dev_id, ...) fal_ip_intf_entry_add(nat_dev_id, ##__VA_ARGS__)
+#define IP_HOST_ADD(dev_id, ...) fal_ip_host_add(nat_dev_id, ##__VA_ARGS__)
+#define IP_HOST_DEL(dev_id, ...) fal_ip_host_del(nat_dev_id, ##__VA_ARGS__)
+#define IP_HOST_GET(dev_id, ...) fal_ip_host_get(nat_dev_id, ##__VA_ARGS__)
+#define IP_HOST_NEXT(dev_id, ...) fal_ip_host_next(nat_dev_id, ##__VA_ARGS__)
+#define IP_INTF_ENTRY_DEL(dev_id, ...) fal_ip_intf_entry_del(nat_dev_id, ##__VA_ARGS__)
+#define IP_HOST_PPPOE_BIND(dev_id, ...) fal_ip_host_pppoe_bind(nat_dev_id, ##__VA_ARGS__)
+#define IP_ROUTE_STATUS_SET(dev_id, ...) fal_ip_route_status_set(nat_dev_id, ##__VA_ARGS__)
+#define IP_HOST_ROUTE_ADD(dev_id, ...) fal_ip_host_route_set(nat_dev_id, ##__VA_ARGS__)
+#define IP_PRV_BASE_ADDR_SET(dev_id, ...) fal_ip_vrf_base_addr_set(nat_dev_id, ##__VA_ARGS__)
+#define IP_PRV_BASE_MASK_SET(dev_id, ...) fal_ip_vrf_base_mask_set(nat_dev_id, ##__VA_ARGS__)
+
+/* PPPOE */
+#define PPPOE_STATUS_GET(dev_id, ...) fal_pppoe_status_get(nat_dev_id, ##__VA_ARGS__)
+#define PPPOE_STATUS_SET(dev_id, ...) fal_pppoe_status_set(nat_dev_id, ##__VA_ARGS__)
+#define PPPOE_SESSION_ID_SET(dev_id, ...) fal_pppoe_session_id_set(nat_dev_id, ##__VA_ARGS__)
+#define PPPOE_SESSION_TABLE_ADD(dev_id, ...) fal_pppoe_session_table_add(nat_dev_id, ##__VA_ARGS__)
+#define PPPOE_SESSION_TABLE_DEL(dev_id, ...) fal_pppoe_session_table_del(nat_dev_id, ##__VA_ARGS__)
+#define RTD_PPPOE_EN_SET(dev_id, ...) fal_rtd_pppoe_en_set(nat_dev_id, ##__VA_ARGS__)
+
+/*MISC API*/
+#define MISC_ARP_CMD_SET(dev_id, ...) fal_arp_cmd_set(nat_dev_id, ##__VA_ARGS__)
+#define CPU_VID_EN_SET(dev_id, ...) fal_cpu_vid_en_set(nat_dev_id, ##__VA_ARGS__)
+#define PORT_ARP_ACK_STATUS_SET(dev_id, ...) fal_port_arp_ack_status_set(nat_dev_id, ##__VA_ARGS__)
+#define CPU_PORT_STATUS_SET(dev_id, ...) fal_cpu_port_status_set(nat_dev_id, ##__VA_ARGS__)
+
+/*ACL API*/
+#define ACL_RULE_ADD(dev_id, ...) fal_acl_rule_add(nat_dev_id, ##__VA_ARGS__)
+#define ACL_RULE_DEL(dev_id, ...) fal_acl_rule_delete(nat_dev_id, ##__VA_ARGS__)
+#define ACL_LIST_CREATE(dev_id, ...) fal_acl_list_creat(nat_dev_id, ##__VA_ARGS__)
+#define ACL_LIST_DESTROY(dev_id, ...) fal_acl_list_destroy(nat_dev_id, ##__VA_ARGS__)
+#define ACL_LIST_BIND(dev_id, ...) fal_acl_list_bind(nat_dev_id, ##__VA_ARGS__)
+#define ACL_LIST_UNBIND(dev_id, ...) fal_acl_list_unbind(nat_dev_id, ##__VA_ARGS__)
+#define ACL_STATUS_GET(dev_id, ...) fal_acl_status_get(nat_dev_id, ##__VA_ARGS__)
+#define ACL_STATUS_SET(dev_id, ...) fal_acl_status_set(nat_dev_id, ##__VA_ARGS__)
+#define ACL_PORT_UDF_PROFILE_SET(dev_id, ...) fal_acl_port_udf_profile_set(nat_dev_id, ##__VA_ARGS__)
+
+/*VLAN API */
+#define VLAN_NEXT(dev_id, ...) fal_vlan_next(nat_dev_id, ##__VA_ARGS__)
+
+/* PORTVLAN API */
+#define PORTVLAN_ROUTE_DEFV_SET(dev_id, port_id)
+#define NETISOLATE_SET(dev_id, ...) fal_netisolate_set(nat_dev_id, ##__VA_ARGS__)
+
+/* PORT_CTRL API */
+#define HEADER_TYPE_SET(dev_id, ...) fal_header_type_set(nat_dev_id, ##__VA_ARGS__)
+#define PORT_TXHDR_MODE_SET(dev_id, ...) fal_port_txhdr_mode_set(nat_dev_id, ##__VA_ARGS__)
+
+/* REG ACCESS API */
+#define REG_GET(dev_id, ...) fal_reg_get(nat_dev_id, ##__VA_ARGS__)
+
+
+#define L3_STATUS_SET(dev_id, ...) napt_l3_status_set(nat_dev_id, ##__VA_ARGS__)
+#define L3_STATUS_GET(dev_id, ...) napt_l3_status_get(nat_dev_id, ##__VA_ARGS__)
+
+#define FDB_ENTRY_SEARCH(dev_id, ...) fal_fdb_entry_search(nat_dev_id, ##__VA_ARGS__)
+#define IP_HOST_ROUTE_GET(dev_id, ...) fal_ip_host_route_get(nat_dev_id, ##__VA_ARGS__)
+
+#define REG_ENTRY_SET(rv, dev_id, ...) HSL_REG_ENTRY_SET(rv, nat_dev_id, ##__VA_ARGS__)
+#define REG_ENTRY_GET(rv, dev_id, ...) HSL_REG_ENTRY_GET(rv, nat_dev_id, ##__VA_ARGS__)
+#endif
+
+extern int nf_athrs17_hnat;
+extern int nf_athrs17_hnat_wan_type;
+extern int nf_athrs17_hnat_ppp_id;
+extern int nf_athrs17_hnat_udp_thresh;
+extern a_uint32_t nf_athrs17_hnat_wan_ip;
+extern a_uint32_t nf_athrs17_hnat_ppp_peer_ip;
+extern unsigned char nf_athrs17_hnat_ppp_peer_mac[ETH_ALEN];
+extern unsigned char nf_athrs17_hnat_wan_mac[ETH_ALEN];
+extern int nf_athrs17_hnat_sync_counter_en;
+
+extern int nf_athrs17_hnat_ppp_id2;
+extern unsigned char nf_athrs17_hnat_ppp_peer_mac2[ETH_ALEN];
+
+enum {
+	NAT_CHIP_VER_8327 = 0x12,
+	NAT_CHIP_VER_8337 = 0x13,
+	NAT_CHIP_VER_DESS = 0x14,
+};
+
+typedef struct
+{
+    a_uint32_t entry_id;
+    a_uint32_t flags;
+    a_uint32_t src_addr;
+    a_uint32_t trans_addr;
+    a_uint16_t port_num;
+    a_uint16_t port_range;
+} nat_entry_t;
+
+typedef struct
+{
+    a_uint32_t entry_id;
+    a_uint32_t flags;
+    a_uint32_t status;
+    a_uint32_t src_addr;
+    a_uint32_t dst_addr;
+    a_uint16_t src_port;
+    a_uint16_t dst_port;
+    a_uint32_t trans_addr;
+    a_uint16_t trans_port;
+    a_uint32_t ingress_packet;
+    a_uint32_t ingress_byte;
+    a_uint32_t egress_packet;
+    a_uint32_t egress_byte;
+} napt_entry_t;
+
+#if defined (__BIG_ENDIAN)
+typedef struct
+{
+    a_uint16_t ver:2;
+    a_uint16_t pri:3;
+    a_uint16_t type:5;
+    a_uint16_t rev:2;
+    a_uint16_t with_tag:1;
+    a_uint16_t sport:3;
+    a_uint16_t vid;
+    a_uint16_t magic;
+} aos_header_t;
+#elif defined (__LITTLE_ENDIAN)
+typedef struct
+{
+    a_uint16_t vid;
+    a_uint16_t sport:3;
+    a_uint16_t with_tag:1;
+    a_uint16_t rev:2;
+    a_uint16_t type:5;
+    a_uint16_t pri:3;
+    a_uint16_t ver:2;
+} aos_header_t;
+#else
+#error "no ENDIAN"
+#endif
+
+a_int32_t
+nat_hw_add(nat_entry_t *nat);
+a_int32_t
+nat_hw_del_by_index(a_uint32_t index);
+a_int32_t
+nat_hw_flush(void);
+a_int32_t
+napt_hw_flush(void);
+a_int32_t
+nat_hw_prv_base_can_update(void);
+void
+nat_hw_prv_base_update_enable(void);
+void
+nat_hw_prv_base_update_disable(void);
+a_int32_t
+nat_hw_prv_base_set(a_uint32_t ip);
+a_uint32_t
+nat_hw_prv_base_get(void);
+a_int32_t
+nat_hw_prv_mask_set(a_uint32_t ipmask);
+a_uint32_t
+nat_hw_prv_mask_get(void);
+a_int32_t
+nat_hw_prv_base_is_match(a_uint32_t ip);
+a_int32_t
+if_mac_add(uint8_t *mac, uint32_t vid, uint32_t ipv6);
+a_int32_t
+if_mac_cleanup(void);
+a_int32_t
+arp_hw_add(a_uint32_t port, a_uint32_t intf_id, a_uint8_t *ip, a_uint8_t *mac, int is_ipv6_entry);
+a_int32_t
+arp_if_info_get(void *data, a_uint32_t *sport, a_uint32_t *vid);
+a_int32_t
+nat_hw_pub_ip_add(a_uint32_t ip, a_uint32_t *index);
+void
+napt_hw_mode_init(void);
+void
+napt_hw_mode_cleanup(void);
+a_int32_t
+nat_hw_pub_ip_del(a_uint32_t index);
+a_int32_t
+napt_hw_add(napt_entry_t *napt_entry);
+a_int32_t
+napt_hw_get(napt_entry_t *napt, fal_napt_entry_t *entry);
+a_int32_t
+napt_hw_dnat_cookie_add(napt_entry_t *napt, a_uint32_t cookie);
+a_int32_t
+napt_hw_snat_cookie_add(napt_entry_t *napt, a_uint32_t cookie);
+a_int32_t
+napt_hw_del(napt_entry_t *napt_entry);
+a_int32_t
+napt_hw_first_by_age(napt_entry_t *napt, a_uint32_t age);
+a_int32_t
+napt_hw_next_by_age(napt_entry_t *napt, a_uint32_t age);
+a_int32_t
+napt_hw_get_by_index(napt_entry_t *napt, a_uint16_t hw_index);
+a_int32_t napt_hw_get_by_sip(a_uint32_t sip);
+a_uint32_t
+napt_hw_used_count_get(void);
+
+sw_error_t napt_l3_status_set(a_uint32_t dev_id, a_bool_t enable);
+sw_error_t napt_l3_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+sw_error_t napt_helper_hsl_init(void);
+
+
+#endif /*_NAT_HELPER_HSL_H*/
+
diff --git a/qca-ssdk/app/nathelper/linux/napt_acl.c b/qca-ssdk/app/nathelper/linux/napt_acl.c
new file mode 100755
index 0000000..2d0de4f
--- /dev/null
+++ b/qca-ssdk/app/nathelper/linux/napt_acl.c
@@ -0,0 +1,1622 @@
+/*
+ * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifdef KVER32
+#include <linux/kconfig.h> 
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#endif
+#include <linux/if_arp.h>
+#include <linux/netdevice.h>
+
+#include "napt_acl.h"
+#include "nat_helper.h"
+#include "lib/nat_helper_hsl.h"
+#include "hsl_shared_api.h"
+
+static uint32_t aclrulemask = 0;
+extern int nat_chip_ver;
+
+uint32_t
+get_aclrulemask(void)
+{
+    uint32_t ret;
+    unsigned long  flags;
+
+    local_irq_save(flags);
+    ret = aclrulemask;
+    local_irq_restore(flags);
+
+    return ret;
+}
+
+void
+set_aclrulemask(uint32_t acl_list)
+{
+    unsigned long  flags;
+
+    local_irq_save(flags);
+    aclrulemask |= 1<<acl_list;
+    local_irq_restore(flags);
+
+    return;
+}
+
+void
+unset_aclrulemask(uint32_t acl_list)
+{
+    unsigned long  flags;
+
+    local_irq_save(flags);
+    aclrulemask &= ~(1<<acl_list);
+    local_irq_restore(flags);
+
+    return;
+}
+
+/*
+ * set the IPv4 default route (to the next hop)
+ */
+void
+droute_add_acl_rules(uint32_t local_ip, uint32_t local_ip_mask, uint32_t gw_entry_id)
+{
+    fal_acl_rule_t myacl;
+    uint32_t rtnval;
+    a_bool_t val;
+    int i;
+
+    if (get_aclrulemask() & (1 << S17_ACL_LIST_DROUTE))
+        return;
+
+    aos_printk("Adding ACL rules %d - Default Route \n", S17_ACL_LIST_DROUTE);
+
+    printk("%s %d: 0x%08x\n", __FUNCTION__, __LINE__, ntohl(local_ip));
+
+    memset(&myacl, 0, sizeof(fal_acl_rule_t));
+    myacl.rule_type = FAL_ACL_RULE_IP4;
+    myacl.dest_ip4_val = ntohl(local_ip);
+    myacl.dest_ip4_mask = ntohl(local_ip_mask);
+    /*
+    IPv4 rule, with DIP field
+    if DIP != Lan IP, force the ARP index redirect to the next hop
+        enable packet forwarding & forward only. i.e. no FORCE_L3_MODE
+        ARP_INDEX_EN, to the next hop ARP index, bind on LAN ports
+    */
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_INVERSE_ALL );
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP4_DIP );
+    FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_ARP_EN );
+
+    myacl.arp_ptr = gw_entry_id;
+
+    rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_DROUTE, S17_ACL_LIST_PRIO_HIGH);
+    if ( rtnval != SW_OK )
+    {
+        aos_printk("ACL_LIST_CREATE ERROR...\n" );
+        aos_printk("already created!? \n");
+        return ;
+    }
+
+    rtnval = ACL_RULE_ADD (0, S17_ACL_LIST_DROUTE, 0, 1, &myacl );
+    if ( rtnval != SW_OK )
+    {
+        aos_printk ( "ACL_RULE_ADD ERROR...\n" );
+        return ;
+    }
+
+    for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+        if (i != S17_WAN_PORT)
+            ACL_LIST_BIND (0, S17_ACL_LIST_DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+    }
+
+    /* check for the ACL enable bit */
+    if (ACL_STATUS_GET(0, &val) == SW_OK)
+    {
+        if (val != A_TRUE)
+        {
+            aos_printk("ACL is not yet enabled. Enabling... \n");
+            ACL_STATUS_SET(0, A_TRUE);
+        }
+    }
+
+    set_aclrulemask(S17_ACL_LIST_DROUTE);
+}
+void
+droute_del_acl_rules(void)
+{
+	int i;
+
+	if (!(get_aclrulemask() & (1 << S17_ACL_LIST_DROUTE)))
+		return;
+
+	HNAT_PRINTK("IPv4 default route del rule #%d\n", S17_ACL_LIST_DROUTE);
+
+	for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+		if (i != S17_WAN_PORT)
+			ACL_LIST_UNBIND(0, S17_ACL_LIST_DROUTE,
+				FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+	}
+
+	ACL_RULE_DEL(0, S17_ACL_LIST_DROUTE, 0, 1);
+
+
+	ACL_LIST_DESTROY(0, S17_ACL_LIST_DROUTE);
+
+	unset_aclrulemask(S17_ACL_LIST_DROUTE);
+}
+
+/*
+ * set the IPv6 default route (to the next hop)
+ */
+void
+ipv6_droute_add_acl_rules(struct in6_addr *local_ip, uint32_t gw_entry_id)
+{
+    fal_acl_rule_t myacl;
+    uint32_t rtnval;
+    a_bool_t val;
+    int i;
+
+    if (get_aclrulemask() & (1 << S17_ACL_LIST_IPV6DROUTE))
+        return;
+
+    printk("Adding ACL rules %d - IPv6 Default Route \n", S17_ACL_LIST_IPV6DROUTE);
+
+    memset(&myacl, 0, sizeof(fal_acl_rule_t));
+    myacl.rule_type = FAL_ACL_RULE_IP6;
+
+    myacl.dest_ip6_val.ul[0] =  local_ip->s6_addr32[0]; /* FF02::1:FF00:0000/104 */
+    myacl.dest_ip6_val.ul[1] =  local_ip->s6_addr32[1];
+    myacl.dest_ip6_val.ul[2] =  local_ip->s6_addr32[2];
+    myacl.dest_ip6_val.ul[3] =  local_ip->s6_addr32[3];
+    myacl.dest_ip6_mask.ul[0] = 0xffffffff;
+    myacl.dest_ip6_mask.ul[1] = 0xffffffff;
+    myacl.dest_ip6_mask.ul[2] = 0xffffffff;
+    myacl.dest_ip6_mask.ul[3] = 0xff000000;
+
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_INVERSE_ALL );
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+    FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_ARP_EN );
+
+    myacl.arp_ptr = gw_entry_id;
+
+    rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_IPV6DROUTE, S17_ACL_LIST_PRIO_HIGH);
+    if ( rtnval != SW_OK )
+    {
+        printk("qcaswitch_acl_list_creat ERROR...\n" );
+        printk("already created!? \n");
+        return ;
+    }
+
+    rtnval = ACL_RULE_ADD (0, S17_ACL_LIST_IPV6DROUTE, 0, 1, &myacl );
+    if ( rtnval != SW_OK )
+    {
+        printk ( "qcaswitch_acl_rule_add ERROR...\n" );
+        return ;
+    }
+
+    for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+        if (i != S17_WAN_PORT)
+            ACL_LIST_BIND (0, S17_ACL_LIST_IPV6DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+    }
+
+    /* check for the ACL enable bit */
+    if (ACL_STATUS_GET(0, &val) == SW_OK)
+    {
+        if (val != A_TRUE)
+        {
+            printk("ACL is not yet enabled. Enabling... \n");
+            ACL_STATUS_SET(0, A_TRUE);
+        }
+    }
+
+    set_aclrulemask(S17_ACL_LIST_IPV6DROUTE);
+}
+
+/*
+ * Del Default Route  ACL rules
+ */
+void ipv6_droute_del_acl_rules(void)
+{
+    int i;
+
+    HNAT_PRINTK("IPv6 default route del rule #%d\n", S17_ACL_LIST_IPV6DROUTE);
+
+    if (!(get_aclrulemask() & (1 << S17_ACL_LIST_IPV6DROUTE)))
+        return;
+
+    for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+        if (i != S17_WAN_PORT)
+            ACL_LIST_UNBIND(0, S17_ACL_LIST_IPV6DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+    }
+
+    ACL_RULE_DEL(0, S17_ACL_LIST_IPV6DROUTE, 0, 1);
+
+
+    ACL_LIST_DESTROY(0, S17_ACL_LIST_IPV6DROUTE);
+
+    unset_aclrulemask(S17_ACL_LIST_IPV6DROUTE);
+}
+
+
+static int isis_pppoe_del_rule0(void)
+{
+    int rtnval;
+
+    rtnval = ACL_LIST_UNBIND(0, S17_ACL_LIST_PPPOE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT);
+    if (rtnval != SW_OK)
+        aos_printk("unbind error... \n");
+
+    rtnval = ACL_RULE_DEL(0, S17_ACL_LIST_PPPOE, 0, 1);
+    if (rtnval != SW_OK)
+        aos_printk("delete error... \n");
+
+    rtnval = ACL_LIST_DESTROY(0, S17_ACL_LIST_PPPOE);
+    if (rtnval != SW_OK)
+        aos_printk("destroy error... \n");
+
+    return rtnval;
+}
+
+
+/*
+ * PPPoE ACL rules
+ * Force ARP_INDEX_EN to the next hop for CPU port
+ * Force SNAT and ARP_INDEX_EN to the next hop for LAN ports
+ */
+void pppoe_add_acl_rules(
+		uint32_t wan_ip, uint32_t local_ip,
+		uint32_t local_ip_mask, uint32_t gw_entry_id)
+{
+    fal_acl_rule_t myacl;
+    uint32_t rtnval, cnt;
+    a_bool_t val;
+    int i;
+
+    /* do the 1st, 2nd and 3rd rules */
+    for (cnt = 0; cnt < 3; cnt++)
+    {
+        memset(&myacl, 0, sizeof(fal_acl_rule_t));
+
+        switch (cnt)
+        {
+            case 0:
+			if (((nat_chip_ver & 0xffff)>>8) != NAT_CHIP_VER_8327)
+				break;
+
+                aos_printk("PPPoE adding rule #%d\n", S17_ACL_LIST_PPPOE);
+                myacl.rule_type = FAL_ACL_RULE_IP4;
+                myacl.src_ip4_val = wan_ip;
+                myacl.src_ip4_mask = 0xffffffff;
+                aos_printk("WAN IP: %.8x\n", wan_ip);
+                /*
+                  IPv4 rule, with SIP field
+                  IF SIP == WAN IP, FORCE the ARP_INDEX_EN to the PPPoE ARP INDEX
+                  enable packet forwarding & forward only. i.e. no FORCE_L3_MODE
+                  ARP_INDEX_EN, to the PPPoE peer ARP index,
+                  Change the CVID to WAN_VID (2)
+                  Bind to CPU port
+                */
+                FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_SIP);
+                FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_MAC_CTAG_VID);
+
+                FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_ARP_EN);
+                FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID);
+
+                myacl.arp_ptr = gw_entry_id;
+                /* fixed with CVID = 2 */
+                myacl.ctag_vid = 2;
+
+                rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_PPPOE, S17_ACL_LIST_PRIO_HIGH);
+                if (rtnval != SW_OK)
+                {
+                    aos_printk("ACL_LIST_CREATE ERROR...\n");
+                    aos_printk("PPPoE Session ID changed !? \n");
+                    /* delete the old ACL list */
+                    rtnval = isis_pppoe_del_rule0();
+                    if (rtnval != SW_OK)
+                        aos_printk("pppoe_del_rule0: %d \n", rtnval);
+
+                    /* create the ACL list again */
+                    rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_PPPOE, S17_ACL_LIST_PRIO_HIGH);
+                    if (rtnval != SW_OK)
+                    {
+                        aos_printk("ACL_LIST_CREATE ERROR...\n");
+                        break;
+                    }
+                }
+
+                rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_PPPOE, 0, 1, &myacl);
+                if (rtnval != SW_OK)
+                {
+                    aos_printk("ACL_RULE_ADD ERROR...\n");
+                    break;
+                }
+
+                ACL_LIST_BIND(0, S17_ACL_LIST_PPPOE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT_W);
+
+                break;
+
+            case 1:
+                aos_printk("PPPoE adding rule #%d\n", S17_ACL_LIST_PPPOE+1);
+                myacl.rule_type = FAL_ACL_RULE_IP4;
+                myacl.dest_ip4_val = ntohl(local_ip);
+                myacl.dest_ip4_mask = ntohl(local_ip_mask);
+
+                /*
+                  IPv4 rule, with DIP field
+                  IF DIP != LAN IP, FORCE the ARP_INDEX_EN to the PPPoE ARP INDEX
+                  AND FORCE L3 SNAT
+                  ARP_INDEX_EN, to the PPPoE peer ARP index
+                  Bind to LAN ports
+                */
+
+                FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+                FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_DIP);
+
+                FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN);
+                FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_ARP_EN);
+
+                myacl.arp_ptr = gw_entry_id;
+                myacl.policy_fwd = FAL_ACL_POLICY_SNAT;
+
+                rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_PPPOE+1, S17_ACL_LIST_PRIO_HIGH);
+                if (rtnval != SW_OK)
+                {
+                    aos_printk("ACL_LIST_CREATE ERROR...\n");
+                    break;
+                }
+
+                rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_PPPOE+1, 0, 1, &myacl);
+                if (rtnval != SW_OK)
+                {
+                    aos_printk("ACL_RULE_ADD ERROR...\n");
+                    break;
+                }
+                /* bind to LAN ports (1-4) */
+                for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+                    if (i != S17_WAN_PORT)
+                        ACL_LIST_BIND(0, S17_ACL_LIST_PPPOE+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+                }
+
+                break;
+
+            case 2:
+                /*
+                    User defined filter ACL
+                    filter out 0x8100000288641100 packets and set the CVID to
+                    a predefined VID (100 in this case)
+                    ARP_INDEX_EN, to the PPPoE peer ARP index
+                    Bind to CPU port
+                 */
+                aos_printk("PPPoE adding rule #%d\n", S17_ACL_LIST_PPPOE+2);
+                myacl.rule_type = FAL_ACL_RULE_UDF;
+                /* set the UDP ACL type as L2, with length 8, offset 12 */
+                ACL_PORT_UDF_PROFILE_SET(0, S17_CPU_PORT, FAL_ACL_UDF_TYPE_L2, 12, 8);
+                myacl.udf_len = 8;
+                myacl.udf_offset = 12;
+                myacl.udf_type = FAL_ACL_UDF_TYPE_L2;
+                memset(&myacl.udf_val, 0, sizeof(myacl.udf_val));
+                memset(&myacl.udf_mask, 0, sizeof(myacl.udf_mask));
+                /* UDF filter to check for 0x8100000288641100 packets */
+                myacl.udf_val[0] = 0x81;
+                myacl.udf_val[1] = 0x00;
+                myacl.udf_val[2] = 0x00;
+                myacl.udf_val[3] = 0x02;
+                myacl.udf_val[4] = 0x88;
+                myacl.udf_val[5] = 0x64;
+                myacl.udf_val[6] = 0x11;
+                myacl.udf_val[7] = 0x00;
+
+                myacl.udf_mask[0] = 0xff;
+                myacl.udf_mask[1] = 0xff;
+                myacl.udf_mask[2] = 0xff;
+                myacl.udf_mask[3] = 0xff;
+                myacl.udf_mask[4] = 0xff;
+                myacl.udf_mask[5] = 0xff;
+                myacl.udf_mask[6] = 0xff;
+                myacl.udf_mask[7] = 0xff;
+
+                FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_UDF);
+                FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_MAC_CTAG_VID);
+
+                FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_ARP_EN);
+                FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID);
+
+                myacl.arp_ptr = gw_entry_id;
+                /* fixed with CVID = 100 */
+                myacl.ctag_vid = 100;
+
+                rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_PPPOE + 2, S17_ACL_LIST_PRIO_HIGH);
+                if (rtnval != SW_OK)
+                {
+                    aos_printk("ACL_LIST_CREATE ERROR...\n");
+                    break;
+                }
+
+                rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_PPPOE + 2, 0, 1, &myacl);
+                if (rtnval != SW_OK)
+                {
+                    aos_printk("ACL_RULE_ADD ERROR...\n");
+                    break;
+                }
+
+                ACL_LIST_BIND(0, S17_ACL_LIST_PPPOE + 2, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT);
+                break;
+        }
+    }
+
+    if (ACL_STATUS_GET(0, &val) == SW_OK)
+    {
+        if (val != A_TRUE)
+        {
+            aos_printk("ACL is not yet enabled. Enabling... \n");
+            ACL_STATUS_SET(0, A_TRUE);
+        }
+    }
+}
+
+static void pppoe_del_acl_rule1(void)
+{
+	int i;
+	for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+		if (i != S17_WAN_PORT)
+			ACL_LIST_UNBIND(0, S17_ACL_LIST_PPPOE+1,
+				FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+	}
+
+	    ACL_RULE_DEL(0, S17_ACL_LIST_PPPOE+1, 0, 1);
+
+	    ACL_LIST_DESTROY(0, S17_ACL_LIST_PPPOE+1);
+}
+
+static void pppoe_del_acl_rule2(void)
+{
+	    ACL_LIST_UNBIND(0, S17_ACL_LIST_PPPOE+2, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT);
+	    ACL_LIST_UNBIND(0, S17_ACL_LIST_PPPOE+2, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1);
+	    ACL_LIST_UNBIND(0, S17_ACL_LIST_PPPOE+2, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2);
+	    ACL_LIST_UNBIND(0, S17_ACL_LIST_PPPOE+2, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3);
+
+	    ACL_RULE_DEL(0, S17_ACL_LIST_PPPOE+2, 0, 1);
+
+	    ACL_LIST_DESTROY(0, S17_ACL_LIST_PPPOE+2);
+}
+void pppoe_del_acl_rules(void)
+{
+	if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8327)
+		isis_pppoe_del_rule0();
+	pppoe_del_acl_rule1();
+	pppoe_del_acl_rule2();
+}
+/*
+ * When LAN & WAN IPs are too close, apply this ACL
+ * ex: WAN 192.168.1.x, LAN 192.168.0.x
+ */
+void
+ip_conflict_add_acl_rules(uint32_t wan_ip, uint32_t lan_ip, uint32_t gw_entry_id)
+{
+    fal_acl_rule_t myacl;
+    uint32_t rtnval, cnt;
+    a_bool_t val;
+    int i;
+
+    if (get_aclrulemask() & (1 << S17_ACL_LIST_IPCONF)) return;
+
+    for (cnt = 0; cnt < 2; cnt++)
+    {
+        memset(&myacl, 0, sizeof(fal_acl_rule_t));
+
+        aos_printk("IP conflict adding rule #%d\n", cnt);
+
+        switch (cnt)
+        {
+            case 0:
+                myacl.rule_type = FAL_ACL_RULE_IP4;
+                myacl.dest_ip4_val = lan_ip;
+                myacl.dest_ip4_mask = 0xffffff00;
+                myacl.src_ip4_val = lan_ip;
+                myacl.src_ip4_mask = 0xffffff00;
+
+                /*
+                  IPv4 rule, with DIP & SIP field
+                  for DIP and SIP = LAN IP, do the next step
+                */
+                FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_DIP);
+                FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_SIP);
+
+                rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_IPCONF, S17_ACL_LIST_PRIO_HIGH);
+                if (rtnval != SW_OK)
+                {
+                    aos_printk("ACL_LIST_CREATE ERROR...\n");
+                    break;
+                }
+
+                rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_IPCONF, 0, 1, &myacl);
+                if (rtnval != SW_OK)
+                {
+                    aos_printk("ACL_RULE_ADD ERROR...\n");
+                    break;
+                }
+
+                /* bind to LAN ports */
+	   for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+	       if (i != S17_WAN_PORT)
+                        ACL_LIST_BIND(0, S17_ACL_LIST_IPCONF, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+	   }
+
+                aclrulemask |= (1 << S17_ACL_LIST_IPCONF);
+                set_aclrulemask(S17_ACL_LIST_IPCONF);
+
+                break;
+
+            case 1:
+                aos_printk("ARP index entry_id: %d\n", gw_entry_id);
+
+                myacl.rule_type = FAL_ACL_RULE_IP4;
+                myacl.src_ip4_val = lan_ip;
+                myacl.src_ip4_mask = 0xffffff00;
+
+                /*
+                  IPv4 rule, with SIP field
+                  enable packet forwarding & forward only. i.e. no FORCE_L3_MODE
+                  ARP_INDEX_EN, to the PPPoE peer ARP index
+                */
+
+                FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_SIP);
+
+                FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN);
+                FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_ARP_EN);
+
+                myacl.arp_ptr = gw_entry_id;
+                myacl.policy_fwd = FAL_ACL_POLICY_SNAT;
+
+                /* rule no. 4 */
+                rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_IPCONF+1, S17_ACL_LIST_PRIO_HIGH);
+                if (rtnval != SW_OK)
+                {
+                    aos_printk("ACL_LIST_CREATE ERROR...\n");
+                    break;
+                }
+
+                rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_IPCONF+1, 0, 1, &myacl);
+                if (rtnval != SW_OK)
+                {
+                    aos_printk("ACL_RULE_ADD ERROR...\n");
+                    break;
+                }
+                /* bind to LAN ports (1-4) */
+	   for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+	       if (i != S17_WAN_PORT)
+                        ACL_LIST_BIND(0, S17_ACL_LIST_IPCONF+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+	   }
+
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    if (ACL_STATUS_GET(0, &val) == SW_OK)
+    {
+        if (val != A_TRUE)
+        {
+            aos_printk("ACL is not yet enabled. Enabling... \n");
+            ACL_STATUS_SET(0, A_TRUE);
+        }
+    }
+}
+
+void ip_conflict_del_acl_rules(void)
+{
+	int i;
+
+	if (!(get_aclrulemask() & (1 << S17_ACL_LIST_IPCONF)))
+		return;
+
+	for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+	    if (i != S17_WAN_PORT) {
+	        ACL_LIST_UNBIND(0, S17_ACL_LIST_IPCONF, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+	        ACL_LIST_UNBIND(0, S17_ACL_LIST_IPCONF+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+	    }
+	}
+
+	ACL_RULE_DEL(0, S17_ACL_LIST_IPCONF, 0, 1);
+
+	ACL_LIST_DESTROY(0, S17_ACL_LIST_IPCONF);
+
+	ACL_RULE_DEL(0, S17_ACL_LIST_IPCONF+1, 0, 1);
+
+	ACL_LIST_DESTROY(0, S17_ACL_LIST_IPCONF+1);
+
+	unset_aclrulemask(S17_ACL_LIST_IPCONF);
+}
+
+
+/*
+solicted_node address
+    FF02::1:FF00:0000/104 => Solicited-Node Address
+*/
+void
+ipv6_snooping_solicted_node_add_acl_rules ( void )
+{
+    fal_acl_rule_t myacl;
+    uint32_t rtnval;
+    a_bool_t val;
+    int i;
+
+    memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+
+    aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_IPV6_SOLICITED_NODE, __func__);
+    myacl.rule_type = FAL_ACL_RULE_IP6;
+    myacl.dest_ip6_val.ul[0] = 0xff020000; /* FF02::1:FF00:0000/104 */
+    myacl.dest_ip6_val.ul[1] = 0x00000000;
+    myacl.dest_ip6_val.ul[2] = 0x00000001;
+    myacl.dest_ip6_val.ul[3] = 0xff000000;
+
+    myacl.dest_ip6_mask.ul[0] = 0xffffffff;
+    myacl.dest_ip6_mask.ul[1] = 0xffffffff;
+    myacl.dest_ip6_mask.ul[2] = 0xffffffff;
+    myacl.dest_ip6_mask.ul[3] = 0xff000000;
+
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+    /* ACL action destination port, WAN, LAN and CPU ports */
+    myacl.ports = (1 << S17_WAN_PORT) | (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+                  (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+#else
+    /* ACL action destination port, LAN and CPU ports */
+    myacl.ports = (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+                  (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+    myacl.vid_val = 0x1;
+    myacl.vid_mask = 0xfff;
+
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_VID );
+#endif
+
+    FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+    rtnval = ACL_LIST_CREATE ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, S17_ACL_LIST_PRIO_MID);
+    if ( rtnval != SW_OK )
+    {
+        if(rtnval == SW_ALREADY_EXIST)
+        {
+            //aos_printk ( "ipv6_snooping_solicted rules acl list already exists.\n");
+
+        } else {
+            aos_printk ( "%s: ACL_LIST_CREATE ERROR (%d)...\n", __func__, rtnval );
+        }
+        return;
+    }
+
+    rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, 0, 1, &myacl );
+    if ( rtnval != SW_OK )
+    {
+        aos_printk ( "%s: ACL_RULE_ADD ERROR...(%d)\n", __func__, rtnval );
+        return;
+    }
+
+    // ACL pattern source port
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+    ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT );
+#endif
+    ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT );
+    for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+        if (i != S17_WAN_PORT)
+            ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+    }
+
+    if ( ACL_STATUS_GET ( 0, &val ) == SW_OK )
+    {
+        if ( val != A_TRUE )
+        {
+            aos_printk ( "ACL is not yet enabled. Enabling... \n" );
+            ACL_STATUS_SET(0, A_TRUE);
+        }
+    }
+}
+
+
+/*
+Node Information Queries (RFC 4620 is experimental)
+    FF02:0:0:0:0:2:FF00::/104 => Node Information Queries
+*/
+void
+ipv6_snooping_nodeinfo_query_add_acl_rules ( void )
+{
+    fal_acl_rule_t myacl;
+    uint32_t rtnval;
+    a_bool_t val;
+    int i;
+
+    memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+
+    aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_IPV6_NODEINFO_QUERY, __func__);
+    myacl.rule_type = FAL_ACL_RULE_IP6;
+    myacl.dest_ip6_val.ul[0] = 0xff020000; /* FF02:0:0:0:0:2:FF00::/104 */
+    myacl.dest_ip6_val.ul[1] = 0x00000000;
+    myacl.dest_ip6_val.ul[2] = 0x00000002;
+    myacl.dest_ip6_val.ul[3] = 0xff000000;
+
+    myacl.dest_ip6_mask.ul[0] = 0xffffffff;
+    myacl.dest_ip6_mask.ul[1] = 0xffffffff;
+    myacl.dest_ip6_mask.ul[2] = 0xffffffff;
+    myacl.dest_ip6_mask.ul[3] = 0xff000000;
+
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+    /* ACL action destination port, WAN, LAN and CPU ports */
+    myacl.ports = (1 << S17_WAN_PORT) | (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+                  (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+#else
+    /* ACL action destination port, LAN and CPU ports */
+    myacl.ports = (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+                  (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+    myacl.vid_val = 0x1;
+    myacl.vid_mask = 0xfff;
+
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_VID );
+#endif
+
+    FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+    rtnval = ACL_LIST_CREATE ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, S17_ACL_LIST_PRIO_MID);
+    if ( rtnval != SW_OK )
+    {
+        aos_printk ( "%s: ACL_LIST_CREATE ERROR (%d)...\n", __func__, rtnval );
+        return;
+    }
+
+    rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, 0, 1, &myacl );
+    if ( rtnval != SW_OK )
+    {
+        aos_printk ( "%s: ACL_RULE_ADD ERROR...(%d)\n", __func__, rtnval );
+        return;
+    }
+
+    // ACL pattern source port
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+    ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT );
+#endif
+    ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT );
+    for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+        if (i != S17_WAN_PORT)
+            ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+    }
+
+    if ( ACL_STATUS_GET ( 0, &val ) == SW_OK )
+    {
+        if ( val != A_TRUE )
+        {
+            aos_printk ( "ACL is not yet enabled. Enabling... \n" );
+            ACL_STATUS_SET(0, A_TRUE);
+        }
+    }
+}
+
+
+/*
+sextuple0_group_acl_rules contains following addresses:
+    FF02:0:0:0:0:0:0:1 => All Nodes Address
+    FF02:0:0:0:0:0:0:2 => All Routers Address
+    FF02:0:0:0:0:0:0:9 => RIP Routers
+    FF02:0:0:0:0:0:0:C => SSDP
+    FF02:0:0:0:0:0:0:16 => All MLDv2-capable routers
+    FF02:0:0:0:0:0:0:FB => mDNSv6
+*/
+void
+ipv6_snooping_sextuple0_group_add_acl_rules ( void )
+{
+    fal_acl_rule_t myacl;
+    uint32_t rtnval;
+    a_bool_t val;
+    int i;
+
+    memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+
+    aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, __func__);
+    myacl.rule_type = FAL_ACL_RULE_IP6;
+    myacl.dest_ip6_val.ul[0] = 0xff020000; /* FF02::/120 */
+    myacl.dest_ip6_val.ul[1] = 0x00000000;
+    myacl.dest_ip6_val.ul[2] = 0x00000000;
+    myacl.dest_ip6_val.ul[3] = 0x00000000;
+
+    myacl.dest_ip6_mask.ul[0] = 0xffffffff;
+    myacl.dest_ip6_mask.ul[1] = 0xffffffff;
+    myacl.dest_ip6_mask.ul[2] = 0xffffffff;
+    myacl.dest_ip6_mask.ul[3] = 0xffffff00;
+
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+    /* ACL action destination port, WAN, LAN and CPU ports */
+    myacl.ports = (1 << S17_WAN_PORT) | (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+                  (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+#else
+    /* ACL action destination port, LAN and CPU ports */
+    myacl.ports = (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+                  (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+    myacl.vid_val = 0x1;
+    myacl.vid_mask = 0xfff;
+
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_VID );
+#endif
+
+    FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+    rtnval = ACL_LIST_CREATE ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, S17_ACL_LIST_PRIO_MID);
+    if ( rtnval != SW_OK )
+    {
+        if(rtnval == SW_ALREADY_EXIST)
+        {
+            //aos_printk ( "ipv6_snooping_sextuple0 rules acl list already exists.\n");
+        } else {
+            aos_printk ( "%s: ACL_LIST_CREATE ERROR (%d)...\n", __func__, rtnval );
+        }
+        return;
+    }
+    rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, 0, 1, &myacl );
+    if ( rtnval != SW_OK )
+    {
+        aos_printk ( "%s: ACL_RULE_ADD ERROR...(%d)\n", __func__, rtnval );
+        return;
+    }
+
+    // ACL pattern source port
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+    ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT );
+#endif
+    ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT );
+    for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+        if (i != S17_WAN_PORT)
+            ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i );
+    }
+
+    if ( ACL_STATUS_GET ( 0, &val ) == SW_OK )
+    {
+        if ( val != A_TRUE )
+        {
+            aos_printk ( "ACL is not yet enabled. Enabling... \n" );
+            ACL_STATUS_SET(0, A_TRUE);
+        }
+    }
+}
+
+
+/*
+quintruple0_1_group_acl_rules contains following addresses:
+    FF02:0:0:0:0:0:1:2 => All-dhcp-agents
+    FF02:0:0:0:0:0:1:3 => LLMNR
+*/
+void
+ipv6_snooping_quintruple0_1_group_add_acl_rules ( void )
+{
+    fal_acl_rule_t myacl;
+    uint32_t rtnval;
+    a_bool_t val;
+    int i;
+
+    memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+
+    aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, __func__);
+    myacl.rule_type = FAL_ACL_RULE_IP6;
+    myacl.dest_ip6_val.ul[0] = 0xff020000; /* FF02:0:0:0:0:0:1::/125 */
+    myacl.dest_ip6_val.ul[1] = 0x00000000;
+    myacl.dest_ip6_val.ul[2] = 0x00000000;
+    myacl.dest_ip6_val.ul[3] = 0x00010000;
+
+    myacl.dest_ip6_mask.ul[0] = 0xffffffff;
+    myacl.dest_ip6_mask.ul[1] = 0xffffffff;
+    myacl.dest_ip6_mask.ul[2] = 0xffffffff;
+    myacl.dest_ip6_mask.ul[3] = 0xfffffff8;
+
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+    myacl.ports = (1 << S17_WAN_PORT) | (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+                  (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+#else
+    /* ACL action destination port, LAN and CPU ports */
+    myacl.ports = (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+                  (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+    myacl.vid_val = 0x1;
+    myacl.vid_mask = 0xfff;
+
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_VID );
+#endif
+
+    FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+    rtnval = ACL_LIST_CREATE ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, S17_ACL_LIST_PRIO_MID);
+    if ( rtnval != SW_OK )
+    {
+        if(rtnval == SW_ALREADY_EXIST)
+        {
+            //aos_printk ( "ipv6_snooping_quintruple0 rules acl list already exists.\n");
+        } else {
+            aos_printk ( "%s: ACL_LIST_CREATE ERROR (%d)...\n", __func__, rtnval );
+        }
+        return;
+    }
+    rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, 0, 1, &myacl );
+    if ( rtnval != SW_OK )
+    {
+        aos_printk ( "%s: ACL_RULE_ADD ERROR...(%d)\n", __func__, rtnval );
+        return;
+    }
+
+    /* ACL pattern soruce port */
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+    ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT );
+#endif
+    ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT );
+    for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+        if (i != S17_WAN_PORT)
+            ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i );
+    }
+
+    if ( ACL_STATUS_GET ( 0, &val ) == SW_OK )
+    {
+        if ( val != A_TRUE )
+        {
+            aos_printk ( "ACL is not yet enabled. Enabling... \n" );
+            ACL_STATUS_SET(0, A_TRUE);
+        }
+    }
+}
+
+/*
+When HW IGMPSNOOPING Enabled, we need to let UPnP SSDP Multicast packets send to lan
+*/
+void upnp_ssdp_add_acl_rules(void)
+{
+    fal_acl_rule_t myacl;
+    uint32_t rtnval;
+    a_bool_t val;
+    int i;
+
+    aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_UPNP_SSDP, __func__);
+    memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+
+    myacl.rule_type = FAL_ACL_RULE_IP4;
+    myacl.dest_ip4_val = 0xeffffffa;  // 239.255.255.250
+    myacl.dest_ip4_mask = 0xffffffff;
+    /* ACL action destination port, LAN and CPU ports */
+    myacl.ports = (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+                  (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP4_DIP );
+    FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+    rtnval = ACL_LIST_CREATE ( 0, S17_ACL_LIST_UPNP_SSDP, S17_ACL_LIST_PRIO_MID);
+    if ( rtnval != SW_OK )
+    {
+        if(rtnval == SW_ALREADY_EXIST)
+        {
+            //aos_printk ( "upnp_ssdp rules acl list already exists.\n");
+        } else {
+            aos_printk ( "upnp_ssdp_acl_rules: ACL_LIST_CREATE ERROR (%d)...\n",rtnval );
+        }
+        return ;
+    }
+
+    rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_UPNP_SSDP, 0, 1, &myacl );
+    if ( rtnval != SW_OK )
+    {
+        aos_printk ( "upnp_ssdp_acl_rules: ACL_RULE_ADD ERROR...(%d)\n" ,rtnval );
+        return ;
+    }
+
+    // Pattern source port
+    ACL_LIST_BIND ( 0, S17_ACL_LIST_UPNP_SSDP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT );
+    for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+        if (i != S17_WAN_PORT)
+            ACL_LIST_BIND ( 0, S17_ACL_LIST_UPNP_SSDP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i );
+    }
+
+    if (ACL_STATUS_GET(0, &val) == SW_OK)
+    {
+        if (val != A_TRUE)
+        {
+            aos_printk("ACL is not yet enabled. Enabling... \n");
+            ACL_STATUS_SET(0, A_TRUE);
+        }
+    }
+}
+
+void filter_power_cord_acl_rules(void)
+{
+    fal_acl_rule_t myacl;
+    uint32_t rtnval;
+    a_bool_t val;
+
+    aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_PLC_FILTER, __func__);
+
+    memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+    myacl.rule_type = FAL_ACL_RULE_MAC;
+
+    myacl.ethtype_val     = 0x88e1;
+    myacl.ethtype_mask    = 0xffff;
+
+    /* ACL action destination port PLC port */
+    myacl.ports = (1 << S17_CPU_PORT) | (1 << 6);
+
+    /* Set pattern type*/
+    memset ( &myacl.field_flg, 0, sizeof ( myacl.field_flg ) );
+    FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE ); // set ethtype as pattern
+
+    /* Set action type*/
+    memset ( &myacl.action_flg, 0, sizeof ( myacl.action_flg ) );
+    FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT); // set action as DENY, FAL_ACL_ACTION_DENY
+
+    /*
+        memcpy ( myacl.dest_mac_val.uc,  mac, 6 );
+        memcpy ( myacl.dest_mac_mask.uc, mac_mask, 6 );
+        FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_DA );
+    */
+
+    rtnval = ACL_LIST_CREATE (0, S17_ACL_LIST_PLC_FILTER, S17_ACL_LIST_PRIO_HIGH);
+    if(rtnval != SW_OK)
+    {
+        aos_printk ( "filter_power_cord_acl_rules: ACL_LIST_CREATE ERROR (%d)\n",rtnval );
+        return;
+    }
+
+    rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_PLC_FILTER, 0, 1, &myacl );
+    if ( rtnval != SW_OK )
+    {
+        aos_printk ( "filter_power_cord_acl_rules: ACL_RULE_ADD ERROR...(%d)\n", rtnval );
+        return;
+    }
+
+    // ACL pattern source port
+    ACL_LIST_BIND ( 0, S17_ACL_LIST_PLC_FILTER, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT);
+    ACL_LIST_BIND ( 0, S17_ACL_LIST_PLC_FILTER, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, 6);
+
+    if ( ACL_STATUS_GET ( 0, &val ) == SW_OK )
+    {
+        if ( val != A_TRUE )
+        {
+            aos_printk ( "ACL is not yet enabled. Enabling... \n" );
+            ACL_STATUS_SET ( 0, A_TRUE );
+        }
+    }
+}
+
+/* enable pppoe_passthrough by default */
+static int isis_pppoe_passthrough = 0;
+
+unsigned int isis_pppoe_passthrough_process(struct sk_buff *skb, aos_header_t *athr_header)
+{
+    unsigned char *smac = &skb->data[6];
+
+    if ( isis_pppoe_passthrough == 0 )
+        return -1;
+
+    if ( ( ( skb->data[20] == 0x88 && ( skb->data[21] == 0x63 ) ) || ( skb->data[16] == 0x88 && ( skb->data[17] == 0x63 ) ) )
+            && ( athr_header->sport != S17_WAN_PORT ) )
+    {
+        pppoe_passthrough_acl_rules ( 0, smac );
+    }
+
+    return 0;
+}
+
+unsigned int isis_set_pppoe_passthrough ( int enable )
+{
+    if ( enable )
+        isis_pppoe_passthrough = 1;
+    else
+        isis_pppoe_passthrough = 0;
+
+    printk ( "## isis_set_pppoe_passthrough %s !\n", enable != 0 ? "enabled" : "disabled" );
+
+    return 0;
+}
+
+unsigned int isis_enable_pppoe_discovery_acl(void)
+{
+#if 0
+    printk ( "## isis_enable_pppoe_discovery_acl !\n");
+
+    athrs17_reg_write ( MOD_ENABLE_OFFSET, athrs17_reg_read ( MOD_ENABLE_OFFSET ) | ( 1 << MOD_ENABLE_ACL_EN_BOFFSET ) );
+    printk ( "athrs17_reg_write(MOD_ENABLE_OFFSET) = 0x%08x\n", athrs17_reg_read ( MOD_ENABLE_OFFSET ) );
+#endif
+    return 0;
+}
+
+
+int pppoe_passthrough_acl_rules(uint32_t gw_entry_id, unsigned char *mac)
+{
+    fal_acl_rule_t myacl;
+    uint32_t rtnval;
+    a_bool_t val;
+    uint32_t rule_list_id;
+    unsigned char mac_mask[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+    int i;
+
+    if (isis_pppoe_passthrough > MAX_PPPOE_PASSTHROUGH_NUM)
+    {
+        aos_printk("Support %d PPPoE passthrough hosts only... \n", MAX_PPPOE_PASSTHROUGH_NUM);
+        return -1;
+    }
+
+    {
+        /* lan -> wan, pppoe discovery */
+        rule_list_id = S17_ACL_LIST_PPPOE_PASSTHROUGH_LAN_TO_WAN + (isis_pppoe_passthrough - 1) * 2;
+        printk ( "creating ACL list_id: %d \n", rule_list_id );
+
+        memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+        myacl.rule_type = FAL_ACL_RULE_MAC;
+        memcpy ( myacl.src_mac_val.uc, mac, 6 );
+        memcpy ( myacl.src_mac_mask.uc, mac_mask, 6 );
+        myacl.ethtype_val     = 0x8863;
+        myacl.ethtype_mask    = 0xffff;
+
+        myacl.ports = (1 << S17_WAN_PORT);
+
+        memset ( &myacl.field_flg, 0, sizeof ( myacl.field_flg ) );
+
+        FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_SA );
+        FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE );
+
+        memset ( &myacl.action_flg, 0, sizeof ( myacl.action_flg ) );
+
+        FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+        rtnval = ACL_LIST_CREATE (0, rule_list_id, S17_ACL_LIST_PRIO_MID);
+        if ( rtnval != SW_OK )
+        {
+            aos_printk ( "pppoe_passthrough_acl_rules: ACL_LIST_CREATE ERROR (%d)\n",rtnval );
+            return -1;
+        }
+
+        rtnval = ACL_RULE_ADD ( 0, rule_list_id, 0, 1, &myacl );
+        if ( rtnval != SW_OK )
+        {
+            aos_printk ( "pppoe_passthrough_acl_rules: ACL_RULE_ADD ERROR...(%d)\n", rtnval );
+            return -1;
+        }
+
+        for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+            if (i != S17_WAN_PORT)
+                ACL_LIST_BIND ( 0, rule_list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+        }
+
+    }
+
+    {
+        /* lan -> wan, pppoe session */
+        rule_list_id = S17_ACL_LIST_PPPOE_PASSTHROUGH_LAN_TO_WAN + (isis_pppoe_passthrough - 1) * 2 + 1;
+
+        printk ( "creating ACL list_id: %d \n", rule_list_id );
+
+        memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+        myacl.rule_type = FAL_ACL_RULE_MAC;
+        memcpy ( myacl.src_mac_val.uc, mac, 6 );
+        memcpy ( myacl.src_mac_mask.uc, mac_mask, 6 );
+
+        myacl.ethtype_val     = 0x8864;
+        myacl.ethtype_mask    = 0xffff;
+
+        myacl.ports = ( 1<<S17_WAN_PORT /* WAN */ );
+
+        memset ( &myacl.field_flg, 0, sizeof ( myacl.field_flg ) );
+
+        FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_SA );
+        FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE );
+
+        memset ( &myacl.action_flg, 0, sizeof ( myacl.action_flg ) );
+
+        FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+        rtnval = ACL_LIST_CREATE ( 0, rule_list_id, S17_ACL_LIST_PRIO_MID);
+        if ( rtnval != SW_OK )
+        {
+            aos_printk ( "pppoe_passthrough_acl_rules: ACL_LIST_CREATE ERROR...(%d)\n",rtnval );
+        }
+
+        rtnval = ACL_RULE_ADD ( 0, rule_list_id, 0, 1, &myacl );
+
+        if ( rtnval != SW_OK )
+        {
+            aos_printk ( "pppoe_passthrough_acl_rules: ACL_RULE_ADD ERROR...(%d)\n", rtnval );
+        }
+        for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+            if (i != S17_WAN_PORT)
+                ACL_LIST_BIND ( 0, rule_list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+        }
+
+    }
+
+    {
+        /* lan <- wan, pppoe discovery */
+        rule_list_id = S17_ACL_LIST_PPPOE_PASSTHROUGH_WAN_TO_LAN + (isis_pppoe_passthrough - 1) * 2;
+
+        printk ( "creating ACL list_id: %d \n", rule_list_id );
+
+        memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+        myacl.rule_type = FAL_ACL_RULE_MAC;
+        memcpy ( myacl.dest_mac_val.uc, mac, 6 );
+        memcpy ( myacl.dest_mac_mask.uc, mac_mask, 6 );
+
+        myacl.ethtype_val     = 0x8863;
+        myacl.ethtype_mask    = 0xffff;
+
+        myacl.ports = (1 << S17_LAN_PORT0) |
+                      (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+
+        memset ( &myacl.field_flg, 0, sizeof ( myacl.field_flg ) );
+
+        FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_DA );
+        FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE );
+
+        memset ( &myacl.action_flg, 0, sizeof ( myacl.action_flg ) );
+
+        FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+        rtnval = ACL_LIST_CREATE (0, rule_list_id, S17_ACL_LIST_PRIO_MID);
+        if ( rtnval != SW_OK )
+        {
+            aos_printk ( "pppoe_passthrough_acl_rules: ACL_LIST_CREATE ERROR (%d)\n",rtnval );
+            return -1;
+        }
+
+        rtnval = ACL_RULE_ADD ( 0, rule_list_id, 0, 1, &myacl );
+
+        if ( rtnval != SW_OK )
+        {
+            aos_printk ( "pppoe_passthrough_acl_rules: ACL_RULE_ADD ERROR...(%d)\n", rtnval );
+            return -1;
+        }
+
+        ACL_LIST_BIND ( 0, rule_list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT);
+    }
+
+    {
+        /* lan <- wan, pppoe session */
+        rule_list_id = S17_ACL_LIST_PPPOE_PASSTHROUGH_WAN_TO_LAN + (isis_pppoe_passthrough - 1) * 2 + 1;
+
+        printk ( "creating ACL list_id: %d \n", rule_list_id );
+
+        memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+        myacl.rule_type = FAL_ACL_RULE_MAC;
+        memcpy ( myacl.dest_mac_val.uc, mac, 6 );
+        memcpy ( myacl.dest_mac_mask.uc, mac_mask, 6 );
+
+        myacl.ethtype_val     = 0x8864;
+        myacl.ethtype_mask    = 0xffff;
+
+        myacl.ports = (1 << S17_LAN_PORT0) |
+                      (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+
+        memset ( &myacl.field_flg, 0, sizeof ( myacl.field_flg ) );
+
+        FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_DA );
+        FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE );
+
+        memset ( &myacl.action_flg, 0, sizeof ( myacl.action_flg ) );
+
+        FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+        rtnval = ACL_LIST_CREATE ( 0, rule_list_id, S17_ACL_LIST_PRIO_MID);
+        if ( rtnval != SW_OK )
+        {
+            aos_printk ( "pppoe_passthrough_acl_rules: ACL_LIST_CREATE ERROR...(%d)\n",rtnval );
+            return -1;
+        }
+
+        rtnval = ACL_RULE_ADD ( 0, rule_list_id, 0, 1, &myacl );
+
+        if ( rtnval != SW_OK )
+        {
+            aos_printk ( "pppoe_passthrough_acl_rules: ACL_RULE_ADD ERROR...(%d)\n", rtnval );
+            return -1;
+        }
+
+        ACL_LIST_BIND ( 0, rule_list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT);
+    }
+
+    if ( ACL_STATUS_GET ( 0, &val ) == SW_OK )
+    {
+        if ( val != A_TRUE )
+        {
+            aos_printk ( "ACL is not yet enabled. Enabling... \n" );
+            ACL_STATUS_SET ( 0, A_TRUE );
+        }
+    }
+
+    /* add the counter */
+    isis_pppoe_passthrough++;
+
+    return 0;
+}
+
+void icmp_from_wan_acl_rule(void)
+{
+    fal_acl_rule_t myacl;
+    a_uint32_t rtnval;
+
+    printk("WAN ICMP ACL Rules\n");
+    memset(&myacl, 0, sizeof(fal_acl_rule_t));
+
+    myacl.rule_type = FAL_ACL_RULE_IP4;
+    myacl.ip_proto_val = 0x1;               /* ICMP */
+    myacl.ip_proto_mask = 0xff;
+
+    /* dest port : CPU Port */
+    myacl.ports = 1 << S17_CPU_PORT;
+
+    FAL_FIELD_FLG_SET (myacl.field_flg, FAL_ACL_FIELD_IP_PROTO);
+    FAL_ACTION_FLG_SET (myacl.action_flg, FAL_ACL_ACTION_RDTCPU);
+
+    rtnval = ACL_LIST_CREATE(0, S17_ACL_ICMP_FROM_WAN, S17_ACL_LIST_PRIO_HIGH);
+
+    if (rtnval != SW_OK)
+    {
+        if(rtnval == SW_ALREADY_EXIST)
+        {
+            aos_printk ( "athrs17_icmp_from_wan_acl_rules: rules acl list already exists !\n");
+        }
+        else
+        {
+            aos_printk ( "athrs17_icmp_from_wan_acl_rules: ACL_LIST_CREATE ERROR (%d)...\n",rtnval );
+        }
+        return ;
+    }
+
+    rtnval = ACL_RULE_ADD(0, S17_ACL_ICMP_FROM_WAN, 0, 1, &myacl);
+
+    if (rtnval != SW_OK)
+    {
+        ACL_LIST_DESTROY(0, S17_ACL_ICMP_FROM_WAN);
+        aos_printk("athrs17_icmp_from_wan_acl_rules: ACL_RULE_ADD ERROR...(%d)\n" ,rtnval);
+        return ;
+    }
+
+    /* source port : WAN Port */
+    ACL_LIST_BIND(0, S17_ACL_ICMP_FROM_WAN, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT);
+}
+
+/*
+Once
+1. Both lan and wan interface entry have been created
+2. Lan size PC's host entry has been created
+3. Wan has receive the packet destination IP belong to PC on Lan
+Force to redirect it to CPU
+*/
+void redirect_internal_ip_packets_to_cpu_on_wan_add_acl_rules(uint32_t lan_ip, uint32_t lan_netmask)
+{
+    fal_acl_rule_t myacl;
+    a_uint32_t rtnval;
+    a_bool_t val;
+
+    if (get_aclrulemask() & (1 << S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN)) return;
+
+    aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN, __func__);
+
+    memset(&myacl, 0, sizeof(fal_acl_rule_t));
+    myacl.rule_type = FAL_ACL_RULE_IP4;
+    //myacl.ip_proto_val = 0x1;               /* ICMP */
+    //myacl.ip_proto_mask = 0xff;
+    printk("redirect_internal_ip_packets_to_cpu_on_wan_add_acl_rules, Lan: %u.%u.%u.%u / %u.%u.%u.%u\n"
+           ,((unsigned char *)&lan_ip)[0] ,((unsigned char *)&lan_ip)[1]
+           ,((unsigned char *)&lan_ip)[2] ,((unsigned char *)&lan_ip)[3]
+           ,((unsigned char *)&lan_netmask)[0] ,((unsigned char *)&lan_netmask)[1]
+           ,((unsigned char *)&lan_netmask)[2] ,((unsigned char *)&lan_netmask)[3]
+          );
+
+    myacl.dest_ip4_val = lan_ip;
+    myacl.dest_ip4_mask = lan_netmask;
+
+    /* dest port : CPU Port */
+    myacl.ports = 1 << S17_CPU_PORT;
+
+    //FAL_FIELD_FLG_SET (myacl.field_flg, FAL_ACL_FIELD_IP_PROTO);
+    FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_DIP);
+    FAL_ACTION_FLG_SET (myacl.action_flg, FAL_ACL_ACTION_RDTCPU);
+
+    rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN, S17_ACL_LIST_PRIO_HIGH);
+
+    if (rtnval != SW_OK)
+    {
+        if(rtnval == SW_ALREADY_EXIST)
+        {
+            aos_printk ( "redirect_internal_ip_packets_to_cpu_on_wan_add_acl_rules: rules acl list already exists !\n");
+        }
+        else
+        {
+            aos_printk ( "redirect_internal_ip_packets_to_cpu_on_wan_add_acl_rules: ACL_LIST_CREATE ERROR (%d)...\n",rtnval );
+        }
+        return ;
+    }
+
+    rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN, 0, 1, &myacl);
+
+    if (rtnval != SW_OK)
+    {
+        ACL_LIST_DESTROY(0, S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN);
+        aos_printk("redirect_internal_ip_packets_to_cpu_on_wan_add_acl_rules: ACL_RULE_ADD ERROR...(%d)\n" ,rtnval);
+        return ;
+    }
+
+    /* source port : WAN Port */
+    ACL_LIST_BIND(0, S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT);
+
+    /* check for the ACL enable bit */
+    if (ACL_STATUS_GET(0, &val) == SW_OK)
+    {
+        if (val != A_TRUE)
+        {
+            aos_printk("ACL is not yet enabled. Enabling... \n");
+            ACL_STATUS_SET(0, A_TRUE);
+        }
+    }
+    set_aclrulemask(S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN);
+}
+
+void udp_checksum_zero_acl_rule(uint32_t gw_entry_id)
+{
+    fal_acl_rule_t myacl;
+    a_uint32_t rtnval;
+    int i;
+
+    if (get_aclrulemask() & (1 << S17_ACL_LIST_UDP0)) return;
+
+    memset(&myacl, 0, sizeof(fal_acl_rule_t));
+
+    /*
+        User defined filter ACL
+        filter out UDP(0x11) checksum (0x0000) packets
+        and set FORCE_L3_MODE ARP_INDEX_OVER_EN=1 ARP_INDEX=default route
+        Bind to WAN/LAN port
+    */
+    aos_printk("UDP checksum adding rule #%d\n", S17_ACL_LIST_UDP0);
+    myacl.rule_type = FAL_ACL_RULE_UDF;
+    /* set the UDP ACL type as L3, with length 1, offset 9 */
+    /* set the UDP ACL type as L4, with length 2, offset 6 */
+
+    for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+        ACL_PORT_UDF_PROFILE_SET(0, i, FAL_ACL_UDF_TYPE_L3, 9, 1);
+        ACL_PORT_UDF_PROFILE_SET(0, i, FAL_ACL_UDF_TYPE_L4, 6, 2);
+    }
+
+    myacl.udf_len = 3;
+    myacl.udf_offset = 0;
+    myacl.udf_type = FAL_ACL_UDF_TYPE_L2;
+    memset(&myacl.udf_val, 0, sizeof(myacl.udf_val));
+    memset(&myacl.udf_mask, 0, sizeof(myacl.udf_mask));
+    /* UDF filter to check for UDP checksum 0 packets */
+    myacl.udf_val[0] = 0x11;
+    myacl.udf_val[1] = 0x00;
+    myacl.udf_val[2] = 0x00;
+    myacl.udf_val[3] = 0x00;
+    myacl.udf_val[4] = 0x00;
+    myacl.udf_val[5] = 0x00;
+    myacl.udf_val[6] = 0x00;
+    myacl.udf_val[7] = 0x00;
+
+    myacl.udf_mask[0] = 0xff;
+    myacl.udf_mask[1] = 0xff;
+    myacl.udf_mask[2] = 0xff;
+    myacl.udf_mask[3] = 0x00;
+    myacl.udf_mask[4] = 0x00;
+    myacl.udf_mask[5] = 0x00;
+    myacl.udf_mask[6] = 0x00;
+    myacl.udf_mask[7] = 0x00;
+
+    FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_UDF);
+    FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_ARP_EN);
+
+    myacl.arp_ptr = gw_entry_id;
+    myacl.policy_fwd = FAL_ACL_POLICY_ROUTE;
+
+
+    rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_UDP0, S17_ACL_LIST_PRIO_HIGH);
+    if (rtnval != SW_OK)
+    {
+        aos_printk("#%d, ACL_LIST_CREATE ERROR...%d\n",S17_ACL_LIST_UDP0,rtnval);
+        return;
+    }
+
+    rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_UDP0, 0, 1, &myacl);
+    if (rtnval != SW_OK)
+    {
+        ACL_LIST_DESTROY(0, S17_ACL_LIST_UDP0);
+        aos_printk("#%d, ACL_RULE_ADD ERROR...%d\n",S17_ACL_LIST_UDP0,rtnval);
+        return;
+    }
+
+    for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+        ACL_LIST_BIND(0, S17_ACL_LIST_UDP0, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+    }
+
+    set_aclrulemask(S17_ACL_LIST_UDP0);
+}
+
+
+void dscp_remap_acl_rule(uint32_t ori_dscp, uint32_t dscp)
+{
+    fal_acl_rule_t myacl;
+    a_uint32_t rtnval;
+    uint32_t ori_tos, tos_val;
+    a_bool_t val;
+    int i;
+
+    ori_tos = ori_dscp << 2;
+    tos_val = dscp << 2;
+
+    if (get_aclrulemask() & (1 << S17_ACL_LIST_DSCP_REMAP))
+        return;
+        
+    aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_DSCP_REMAP, __func__);
+    memset(&myacl, 0, sizeof(fal_acl_rule_t));
+    myacl.rule_type = FAL_ACL_RULE_IP4;
+
+    aos_printk("Remap DSCP value from %d to %d\n", ori_dscp, dscp);
+    myacl.ip_dscp_val = ori_tos;
+    myacl.ip_dscp_mask = 0xff;
+
+    FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP_DSCP);
+    FAL_ACTION_FLG_SET (myacl.action_flg, FAL_ACL_ACTION_REMARK_DSCP);
+
+    /* Action : new DSCP value */
+    myacl.dscp = tos_val;
+
+    rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_DSCP_REMAP, S17_ACL_LIST_PRIO_HIGH);
+
+    if (rtnval != SW_OK)
+    {
+        if(rtnval == SW_ALREADY_EXIST)
+        {
+            //aos_printk ( "%s: rules acl list already exists !\n", __FUNCTION__);
+        } else {
+            aos_printk ( "%s: ACL_LIST_CREATE ERROR (%d)...\n", __FUNCTION__, rtnval );
+        }
+        return ;
+    }
+
+    rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_DSCP_REMAP, 0, 1, &myacl);
+
+    if (rtnval != SW_OK)
+    {
+        ACL_LIST_DESTROY(0, S17_ACL_LIST_DSCP_REMAP);
+        aos_printk("%s: ACL_RULE_ADD ERROR...(%d)\n", __FUNCTION__, rtnval);
+        return ;
+    }
+
+    /* source port : LAN Ports */
+    for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) {
+        if (i != S17_WAN_PORT)
+            ACL_LIST_BIND(0, S17_ACL_LIST_DSCP_REMAP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+    }
+
+    /* check for the ACL enable bit */
+    if (ACL_STATUS_GET(0, &val) == SW_OK)
+    {
+        if (val != A_TRUE)
+        {
+            aos_printk("ACL is not yet enabled. Enabling... \n");
+            ACL_STATUS_SET(0, A_TRUE);
+        }
+    }
+    set_aclrulemask(S17_ACL_LIST_DSCP_REMAP);
+}
+
diff --git a/qca-ssdk/app/nathelper/linux/napt_acl.h b/qca-ssdk/app/nathelper/linux/napt_acl.h
new file mode 100755
index 0000000..67e3945
--- /dev/null
+++ b/qca-ssdk/app/nathelper/linux/napt_acl.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#include "fal_nat.h"
+#include "fal_ip.h"
+#include "hsl_api.h"
+#include "hsl.h"
+
+#if defined(DESS)
+#include "dess_acl.h"
+#include "dess_reg.h"
+#elif defined(ISISC)
+#include "isisc_acl.h"
+#include "isisc_reg.h"
+#else
+#include "isis_acl.h"
+#include "isis_reg.h"
+#endif
+
+
+#define MAX_PPPOE_PASSTHROUGH_NUM 4
+/* ACL list priority */
+#define S17_ACL_LIST_PRIO_HIGH  0
+#define S17_ACL_LIST_PRIO_MID   1
+#define S17_ACL_LIST_PRIO_LOW   2
+#define S17_ACL_LIST_PRIO_LOWEST    3
+
+#define S17_ACL_LIST_IPCONF 0
+#define S17_ACL_LIST_UDP0   1
+#define S17_ACL_LIST_DROUTE 2
+#define S17_ACL_LIST_PPPOE  3
+#define S17_ACL_LIST_IPV6MLD    5
+#define S17_ACL_LIST_IPV6_SOLICITED_NODE    7
+#define S17_ACL_LIST_IPV6_NODEINFO_QUERY    9
+#define S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP   11
+#define S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP   13
+#define S17_ACL_LIST_UPNP_SSDP  15
+#define S17_ACL_LIST_PPPOE_PASSTHROUGH_LAN_TO_WAN 17
+#define S17_ACL_LIST_PPPOE_PASSTHROUGH_WAN_TO_LAN 19
+#define S17_ACL_LIST_PLC_FILTER 22
+#define S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN 26
+#define S17_ACL_ICMP_FROM_WAN 27
+#define S17_ACL_LIST_IPV6DROUTE 28
+#define S17_ACL_LIST_DSCP_REMAP 29
+
+
+/* port # of WAN, 1 for DB120 demo board */
+//#define S17_WAN_PORT    5
+#define S17_CPU_PORT    0
+
+#define S17_CPU_PORT_W    6
+
+#define S17_LAN_PORT0   1
+#define S17_LAN_PORT1   2
+#define S17_LAN_PORT2   3
+#define S17_LAN_PORT3   4
+#define S17_LAN_PORT4   5
+
+
+
+
+uint32_t get_aclrulemask(void);
+void set_aclrulemask(uint32_t acl_list);
+
+void droute_add_acl_rules(uint32_t local_ip, uint32_t local_ip_mask, uint32_t gw_entry_id);
+void droute_del_acl_rules(void);
+void ipv6_droute_del_acl_rules(void);
+void ipv6_droute_add_acl_rules(struct in6_addr *local_ip, uint32_t gw_entry_id);
+void pppoe_add_acl_rules(
+	uint32_t wan_ip, uint32_t local_ip,
+	uint32_t local_ip_mask, uint32_t gw_entry_id);
+void pppoe_del_acl_rules(void);
+void ip_conflict_add_acl_rules(uint32_t wan_ip, uint32_t lan_ip, uint32_t gw_entry_id);
+void ipv6_snooping_solicted_node_add_acl_rules(void);
+void ipv6_snooping_nodeinfo_query_add_acl_rules(void);
+void ipv6_snooping_sextuple0_group_add_acl_rules(void);
+void ipv6_snooping_quintruple0_1_group_add_acl_rules ( void );
+void ip_conflict_del_acl_rules(void);
+void upnp_ssdp_add_acl_rules(void);
+unsigned int isis_set_pppoe_passthrough(int enable);
+unsigned int isis_enable_pppoe_discovery_acl(void);
+int pppoe_passthrough_acl_rules(uint32_t gw_entry_id, unsigned char *mac);
diff --git a/qca-ssdk/app/nathelper/linux/napt_helper.c b/qca-ssdk/app/nathelper/linux/napt_helper.c
new file mode 100755
index 0000000..e6efbbf
--- /dev/null
+++ b/qca-ssdk/app/nathelper/linux/napt_helper.c
@@ -0,0 +1,406 @@
+/*
+ * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifdef KVER32
+#include <linux/kconfig.h>  
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#endif
+#include <linux/kthread.h>
+#include <linux/udp.h>
+#include <linux/rculist_nulls.h>
+#ifdef KVER32
+#include <linux/rcupdate.h>
+#endif
+#include <linux/if_arp.h>
+#include <linux/if_vlan.h>
+#include <linux/inetdevice.h>
+#include <linux/string.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack_helper.h>
+#include <net/netfilter/nf_conntrack.h>
+#include "nat_helper.h"
+#include "napt_acl.h"
+
+#include "lib/nat_helper_hsl.h"
+
+extern struct net init_net;
+static struct task_struct *ct_task;
+
+/*#undef HNAT_PRINTK
+#define HNAT_PRINTK(x...) aos_printk(x)*/
+
+#ifdef KVER32
+extern void __rcu_read_lock(void);
+extern void __rcu_read_unlock(void);
+extern unsigned int nf_conntrack_htable_size;
+#endif
+
+a_bool_t napt_aging_ctrl_en = 0;
+
+void
+napt_ct_aging_disable(uintptr_t ct_addr)
+{
+	struct nf_conn *ct = NULL;
+	if(nf_athrs17_hnat_sync_counter_en || !napt_aging_ctrl_en)
+		return;
+
+    if(!ct_addr)
+    {
+        return;
+    }
+
+	ct = (struct nf_conn *)ct_addr;
+
+    if (timer_pending(&ct->timeout))
+    {
+        del_timer(&ct->timeout);
+    }
+}
+
+int
+napt_ct_aging_is_enable(uintptr_t ct_addr)
+{
+	struct nf_conn *ct = NULL;
+    if(!ct_addr)
+    {
+        return 0;
+    }
+
+	if(nf_athrs17_hnat_sync_counter_en || !napt_aging_ctrl_en)
+		return 0;
+
+	ct = (struct nf_conn *)ct_addr;
+
+    return timer_pending(&(((struct nf_conn *)ct)->timeout));
+}
+
+void
+napt_ct_aging_enable(uintptr_t ct_addr)
+{
+	struct nf_conn *ct = NULL;
+	uint16_t l3num = 0;
+	uint8_t protonum = 0;
+	if(nf_athrs17_hnat_sync_counter_en || !napt_aging_ctrl_en)
+		return;
+
+    if(!ct_addr)
+    {
+        return;
+    }
+
+    if(napt_ct_aging_is_enable(ct_addr))
+    {
+        return;
+    }
+
+	ct = (struct nf_conn *)ct_addr;
+	l3num = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num;
+	protonum = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.protonum;
+
+    ct->timeout.expires = jiffies+10*HZ;
+
+    if ((l3num == AF_INET) && (protonum == IPPROTO_TCP))
+    {
+        if (ct->proto.tcp.state == TCP_CONNTRACK_ESTABLISHED)
+        {
+            ct->timeout.expires = jiffies+(5*24*60*60*HZ);
+        }
+    }
+
+    HNAT_PRINTK("<aging> ct:[%x] add timeout again\n",  ct_addr);
+    add_timer(&ct->timeout);
+}
+
+void
+napt_ct_to_hw_entry(uintptr_t ct_addr, napt_entry_t *napt)
+{
+	struct nf_conn *ct = NULL;
+	struct nf_conntrack_tuple *org_tuple, *rep_tuple;
+	uint8_t protonum = 0;
+
+    if(!ct_addr)
+    {
+        return;
+    }
+
+#define NAPT_AGE   0xe
+
+	ct = (struct nf_conn *)ct_addr;
+
+    if ((ct->status & IPS_NAT_MASK) == IPS_SRC_NAT)     //snat
+    {
+        org_tuple = &(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple);
+        rep_tuple = &(ct->tuplehash[IP_CT_DIR_REPLY].tuple);
+
+    }
+    else                                                //dnat
+    {
+        org_tuple = &(ct->tuplehash[IP_CT_DIR_REPLY].tuple);
+        rep_tuple = &(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple);
+    }
+
+	protonum = org_tuple->dst.protonum;
+
+    if(org_tuple->src.l3num == AF_INET)
+    {
+        if(protonum == IPPROTO_TCP)
+        {
+            napt->flags = FAL_NAT_ENTRY_PROTOCOL_TCP;
+
+        }
+        else if(protonum == IPPROTO_UDP)
+        {
+            napt->flags = FAL_NAT_ENTRY_PROTOCOL_UDP;
+
+        }
+    }
+
+    napt->src_addr = ntohl(org_tuple->src.u3.ip);
+    napt->src_port = ntohs(org_tuple->src.u.all);
+    napt->dst_addr = ntohl(org_tuple->dst.u3.ip);
+    napt->dst_port = ntohs(org_tuple->dst.u.all);
+    napt->trans_addr = ntohl(rep_tuple->dst.u3.ip);
+    napt->trans_port = ntohs(rep_tuple->dst.u.all);
+    napt->status = NAPT_AGE;
+
+    return;
+}
+
+uint64_t
+napt_ct_pkts_get(uintptr_t ct_addr)
+{
+	struct nf_conn *ct = NULL;
+	struct nf_conn_counter *cct = NULL;
+    if(!ct_addr)
+    {
+        return 0;
+    }
+
+	ct = (struct nf_conn *)ct_addr;
+	cct = (struct nf_conn_counter *)nf_conn_acct_find(ct);
+
+    if(cct)
+    {
+        return (atomic64_read(&cct[IP_CT_DIR_ORIGINAL].packets) +
+                atomic64_read(&cct[IP_CT_DIR_REPLY].packets));
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+int
+napt_ct_type_is_nat(uintptr_t ct_addr)
+{
+	struct nf_conn *ct = NULL;
+    if(!ct_addr)
+    {
+        return 0;
+    }
+
+	ct = (struct nf_conn *)ct_addr;
+
+    return ((IPS_NAT_MASK & (ct)->status)?1:0);
+}
+
+int
+napt_ct_type_is_nat_alg(uintptr_t ct_addr)
+{
+	struct nf_conn *ct = NULL;
+	if(!ct_addr)
+	{
+		return 0;
+	}
+	ct = (struct nf_conn *)ct_addr;
+	return ((nfct_help(ct))?1:0);
+}
+
+int
+napt_ct_intf_is_expected(uintptr_t ct_addr)
+{
+	struct nf_conn *ct = (struct nf_conn *)ct_addr;
+	struct nf_conntrack_tuple *rep_tuple;
+	uint32_t dst_ip;
+	struct net_device *dev = NULL;
+
+	if(!ct_addr)
+	{
+		return 0;
+	}
+
+	if ((ct->status & IPS_NAT_MASK) == IPS_SRC_NAT)
+		rep_tuple = &(ct->tuplehash[IP_CT_DIR_REPLY].tuple);
+	else
+		rep_tuple = &(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple);
+	dst_ip = rep_tuple->dst.u3.ip;
+	dev = ip_dev_find(&init_net, dst_ip);
+	if(dev) {
+		if(dev->type == ARPHRD_ETHER) {
+			if(strstr(dev->name, "eth0") || strstr(dev->name, "erouter0") ||
+			   strstr(dev->name, "br-wan") || strstr(dev->name, "eth1")) {
+				dev_put(dev);
+				return 1;
+			}
+		} else if (dev->type == ARPHRD_PPP) {
+			dev_put(dev);
+			return 1;
+		}
+		dev_put(dev);
+	}
+
+	return 0;
+}
+
+int
+napt_ct_status_is_estab(uintptr_t ct_addr)
+{
+	struct nf_conn *ct = NULL;
+	uint16_t l3num = 0;
+	uint8_t protonum = 0;
+
+    if(!ct_addr)
+    {
+        return 0;
+    }
+
+	ct = (struct nf_conn *)ct_addr;
+	l3num = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num;
+	protonum = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.protonum;
+
+    if ((l3num == AF_INET) && (protonum == IPPROTO_TCP))
+    {
+        if (ct->proto.tcp.state == TCP_CONNTRACK_ESTABLISHED)
+        {
+            return 1;
+        }
+    }
+    else if ((l3num == AF_INET) && (protonum == IPPROTO_UDP))
+    {
+        return 1;
+    }
+
+    return 0;
+}
+
+uint32_t
+napt_ct_priv_ip_get(uintptr_t ct_addr)
+{
+	struct nf_conn *ct = NULL;
+	uint32_t usaddr = 0;
+
+    if(!ct_addr)
+    {
+        return 0;
+    }
+
+	ct = (struct nf_conn *)ct_addr;
+
+    if ((ct->status & IPS_NAT_MASK) == IPS_SRC_NAT)     //snat
+    {
+        usaddr = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3.ip;
+    }
+    else
+    {
+        usaddr = ct->tuplehash[IP_CT_DIR_REPLY].tuple.src.u3.ip;
+    }
+
+    usaddr = ntohl(usaddr);
+
+    return usaddr;
+}
+
+void
+napt_ct_list_lock(void)
+{
+    rcu_read_lock();
+}
+
+void
+napt_ct_list_unlock(void)
+{
+    rcu_read_unlock();
+}
+
+uintptr_t
+napt_ct_list_iterate(uint32_t *hash, uintptr_t *iterate)
+{
+	struct net *net = &init_net;
+	struct nf_conntrack_tuple_hash *h = NULL;
+	struct nf_conn *ct = NULL;
+	struct hlist_nulls_node *pos = (struct hlist_nulls_node *) (*iterate);
+
+	while(*hash < nf_conntrack_htable_size)
+	{
+		if(pos == 0)
+		{
+			/*get head for list*/
+			pos = rcu_dereference((&net->ct.hash[*hash])->first);
+		}
+
+		hlist_nulls_for_each_entry_from(h, pos, hnnode)
+		{
+			(*iterate) = (uintptr_t)(pos->next);
+			ct = nf_ct_tuplehash_to_ctrack(h);
+			return  (uintptr_t) ct;
+		}
+
+		++(*hash);
+		pos = 0;
+	}
+
+	*hash = 0;
+	return 0;
+}
+
+int
+napt_ct_task_should_stop(void)
+{
+    return kthread_should_stop();
+}
+
+void
+napt_ct_task_start(int (*task)(void*), const char *task_name)
+{
+    ct_task = kthread_create(task, NULL, task_name);
+
+    if(IS_ERR(ct_task))
+    {
+        aos_printk("thread: %s create fail\n", task_name);
+        return;
+    }
+
+    wake_up_process(ct_task);
+
+    HNAT_PRINTK("thread: %s create success pid:%d\n",
+                task_name, ct_task->pid);
+}
+
+void
+napt_ct_task_stop(void)
+{
+    if(ct_task)
+    {
+        kthread_stop(ct_task);
+    }
+}
+
+void
+napt_ct_task_sleep(int secs)
+{
+    msleep_interruptible(secs*1000);
+}
diff --git a/qca-ssdk/app/nathelper/linux/napt_helper.h b/qca-ssdk/app/nathelper/linux/napt_helper.h
new file mode 100755
index 0000000..e833189
--- /dev/null
+++ b/qca-ssdk/app/nathelper/linux/napt_helper.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _NAPT_HELPER_H
+#define _NAPT_HELPER_H
+
+
+
+#define USING_LINUX2631 1
+
+#ifdef USING_LINUX2631
+
+void
+napt_ct_task_start(int (*task)(void*), const char *task_name);
+void
+napt_ct_task_stop(void);
+int
+napt_ct_task_should_stop(void);
+void
+napt_ct_task_sleep(int secs);
+void
+napt_ct_list_lock(void);
+void
+napt_ct_list_unlock(void);
+uintptr_t
+napt_ct_list_iterate(uint32_t *hash, uintptr_t *pos) ;
+void
+napt_ct_to_hw_entry(uintptr_t ct_addr, void *napt);
+void
+napt_ct_aging_enable(uintptr_t ct_addr);
+void
+napt_ct_aging_disable(uintptr_t ct_addr);
+int
+napt_ct_aging_is_enable(uintptr_t ct_addr);
+uint64_t
+napt_ct_pkts_get(uintptr_t ct_addr);
+int
+napt_ct_type_is_nat(uintptr_t ct_addr);
+int
+napt_ct_type_is_nat_alg(uintptr_t ct_addr);
+int
+napt_ct_status_is_estab(uintptr_t ct_addr);
+uint32_t
+napt_ct_priv_ip_get(uintptr_t ct_addr);
+int
+napt_ct_intf_is_expected(uintptr_t ct_addr);
+
+
+
+#define NAPT_CT_TASK_START          napt_ct_task_start
+#define NAPT_CT_TASK_STOP           napt_ct_task_stop
+#define NAPT_CT_TASK_SHOULD_STOP    napt_ct_task_should_stop
+#define NAPT_CT_TASK_SLEEP          napt_ct_task_sleep
+
+#define NAPT_CT_LIST_LOCK           napt_ct_list_lock
+#define NAPT_CT_LIST_UNLOCK         napt_ct_list_unlock
+#define NAPT_CT_LIST_ITERATE        napt_ct_list_iterate
+
+#define NAPT_CT_AGING_IS_ENABLE     napt_ct_aging_is_enable
+#define NAPT_CT_AGING_ENABLE        napt_ct_aging_enable
+#define NAPT_CT_AGING_DISABLE       napt_ct_aging_disable
+
+#define NAPT_CT_TYPE_IS_NAT         napt_ct_type_is_nat
+#define NAPT_CT_STATUS_IS_ESTAB     napt_ct_status_is_estab
+#define NAPT_CT_PRIV_IP_GET         napt_ct_priv_ip_get
+#define NAPT_CT_PKTS_GET            napt_ct_pkts_get
+#define NAPT_CT_TO_HW_ENTRY         napt_ct_to_hw_entry
+#define NAPT_CT_TYPE_IS_NAT_ALG     napt_ct_type_is_nat_alg
+#define NAPT_CT_INTF_EXPECTED       napt_ct_intf_is_expected
+
+
+#else
+
+
+
+#endif
+
+
+#endif
diff --git a/qca-ssdk/app/nathelper/linux/napt_procfs.c b/qca-ssdk/app/nathelper/linux/napt_procfs.c
new file mode 100755
index 0000000..4f5a664
--- /dev/null
+++ b/qca-ssdk/app/nathelper/linux/napt_procfs.c
@@ -0,0 +1,1316 @@
+/*
+ * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ *  napt_procfs.c -  create files in /proc
+ *
+ */
+#include <linux/version.h>
+#ifdef KVER32
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/kconfig.h>
+#include <linux/proc_fs.h>
+#include <linux/sysfs.h>
+#include <linux/if_ether.h>
+#include <asm/uaccess.h>    /* for copy_from_user */
+#include "aos_types.h"
+
+#ifdef AUTO_UPDATE_PPPOE_INFO
+#define NF_PROCFS_PERM  0444
+#else
+#define NF_PROCFS_PERM  0644
+#endif
+
+#define ATHRS17_MAC_LEN         13      // 12+1
+#define ATHRS17_IP_LEN     9       // 8+1
+#define ATHRS17_CHAR_MAX_LEN ATHRS17_MAC_LEN
+
+#define NF_PROCFS_DIR                        "qca_switch"
+
+#define NF_ATHRS17_HNAT_NAME                 "nf_athrs17_hnat"
+#define NF_ATHRS17_HNAT_WAN_TYPE_NAME        "nf_athrs17_hnat_wan_type"
+#define NF_ATHRS17_HNAT_PPP_ID_NAME          "nf_athrs17_hnat_ppp_id"
+#define NF_ATHRS17_HNAT_UDP_THRESH_NAME      "nf_athrs17_hnat_udp_thresh"
+#define NF_ATHRS17_HNAT_WAN_IP_NAME          "nf_athrs17_hnat_wan_ip"
+#define NF_ATHRS17_HNAT_PPP_PEER_IP_NAME     "nf_athrs17_hnat_ppp_peer_ip"
+#define NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME    "nf_athrs17_hnat_ppp_peer_mac"
+#define NF_ATHRS17_HNAT_WAN_MAC_NAME         "nf_athrs17_hnat_wan_mac"
+
+#define NF_ATHRS17_HNAT_PPP_ID2_NAME          "nf_athrs17_hnat_ppp_id2"
+#define NF_ATHRS17_HNAT_PPP_PEER_MAC2_NAME    "nf_athrs17_hnat_ppp_peer_mac2"
+
+/* for PPPoE */
+int nf_athrs17_hnat = 1;
+int nf_athrs17_hnat_wan_type = 0;
+int nf_athrs17_hnat_ppp_id = 0;
+int nf_athrs17_hnat_udp_thresh = 0;
+a_uint32_t nf_athrs17_hnat_wan_ip = 0;
+a_uint32_t nf_athrs17_hnat_ppp_peer_ip = 0;
+unsigned char nf_athrs17_hnat_ppp_peer_mac[ETH_ALEN] = {0};
+unsigned char nf_athrs17_hnat_wan_mac[ETH_ALEN] = {0};
+extern int nf_athrs17_hnat_sync_counter_en;
+extern char  hnat_log_en;
+extern int scan_period;
+extern int scan_enable;
+extern int napt_need_clean;
+extern int wan_switch;
+extern char nat_wan_port;
+extern a_uint32_t packet_thres_base;
+extern a_uint32_t polling_quota;
+extern a_bool_t napt_add_bypass_check;
+extern void napt_wan_switch_prehandle(void);
+/* for IPv6 over PPPoE (only for S17c)*/
+int nf_athrs17_hnat_ppp_id2 = 0;
+unsigned char nf_athrs17_hnat_ppp_peer_mac2[ETH_ALEN] = {0};
+
+#if 0
+static void setup_proc_entry(void)
+{
+    nf_athrs17_hnat = 1;
+    nf_athrs17_hnat_wan_type = 0;
+    nf_athrs17_hnat_ppp_id = 0;
+    memset(&nf_athrs17_hnat_ppp_peer_mac, 0, ETH_ALEN);
+    memset(&nf_athrs17_hnat_wan_mac, 0, ETH_ALEN);
+    nf_athrs17_hnat_ppp_peer_ip = 0;
+    nf_athrs17_hnat_wan_ip = 0;
+
+    nf_athrs17_hnat_ppp_id2 = 0;
+    memset(&nf_athrs17_hnat_ppp_peer_mac2, 0, ETH_ALEN);
+	nf_athrs17_hnat_sync_counter_en = 0;
+}
+
+/**
+ * This structure hold information about the /proc file
+ *
+ */
+static struct proc_dir_entry *qca_switch_dir;
+
+static struct proc_dir_entry *nf_athrs17_hnat_file;
+static struct proc_dir_entry *nf_athrs17_hnat_wan_type_file;
+static struct proc_dir_entry *nf_athrs17_hnat_ppp_id_file;
+static struct proc_dir_entry *nf_athrs17_hnat_udp_thresh_file;
+static struct proc_dir_entry *nf_athrs17_hnat_wan_ip_file;
+static struct proc_dir_entry *nf_athrs17_hnat_ppp_peer_ip_file;
+static struct proc_dir_entry *nf_athrs17_hnat_ppp_peer_mac_file;
+static struct proc_dir_entry *nf_athrs17_hnat_wan_mac_file;
+
+static struct proc_dir_entry *nf_athrs17_hnat_ppp_id2_file;
+static struct proc_dir_entry *nf_athrs17_hnat_ppp_peer_mac2_file;
+
+/**
+ * This function is called then the /proc file is read
+ *
+ */
+static int procfile_read_int(char *page, char **start, off_t off, int count,  int *eof, void *data)
+{
+    int ret;
+    int *prv_data = (int *)data;
+
+	ret = snprintf(page, sizeof(int), "%d\n", *prv_data);
+
+    return ret;
+}
+
+static int procfile_read_ip(char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+	int ret;
+	unsigned char *prv_data = (unsigned char *)data;
+
+	ret = snprintf(page, sizeof(a_uint32_t), "%d.%d.%d.%d\n", prv_data[0], prv_data[1], prv_data[2], prv_data[3]);
+
+	return ret;
+}
+
+static int procfile_read_mac(char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+	int ret;
+	unsigned char *prv_data = (unsigned char *)data;
+	unsigned long long *ptr_ull;
+
+	ret = snprintf(page, sizeof(unsigned char)*ETH_ALEN, "%.2x-%.2x-%.2x-%.2x-%.2x-%.2x\n",
+				prv_data[0], prv_data[1], prv_data[2], prv_data[3], prv_data[4], prv_data[5]);
+
+	ptr_ull = (unsigned long long *)prv_data;
+
+	return ret;
+}
+
+/**
+ * This function is called with the /proc file is written
+ *
+ */
+#ifdef AUTO_UPDATE_PPPOE_INFO
+#define procfile_write_int NULL
+#define procfile_write_ip NULL
+#define procfile_write_mac NULL
+#else
+static int procfile_write_int(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+    int len;
+    uint8_t tmp_buf[9] = {'0', '0', '0', '0', '0', '0', '0', '0', '0'};
+    unsigned int *prv_data = (unsigned int *)data;
+	int res = 0;
+    
+    if(count > sizeof(tmp_buf))
+        len = sizeof(tmp_buf);
+    else
+        len = count;
+
+    if(copy_from_user(tmp_buf, buffer, len))
+        return -EFAULT;
+
+	tmp_buf[len-1] = '\0';
+	res = kstrtol((const char *)tmp_buf, 10, prv_data);
+	if(res < 0)
+		return res;
+
+    // printk("[write] prv_data 0x%p -> 0x%08x\n", prv_data, *prv_data);
+
+    return len;
+}
+
+static int procfile_write_ip(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+    int ret;
+    int len;
+    unsigned char tmp_buf[ATHRS17_IP_LEN];
+    unsigned long *prv_data = (unsigned long *)data;
+	int res = 0;
+
+    if(count > ATHRS17_IP_LEN)
+        len = ATHRS17_IP_LEN;
+    else
+        len = count;
+		
+    if(copy_from_user(tmp_buf, buffer, len))
+		return -EFAULT;
+
+    tmp_buf[len-1] = '\0';
+
+	res = kstrtol((const char *)tmp_buf, 16, prv_data);
+	if(res < 0)
+		return res;
+
+    return ret;
+}
+
+static int procfile_write_mac(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+    int ret;
+    int len;
+    unsigned char tmp_buf[ATHRS17_MAC_LEN];
+    unsigned char *ptr_char;
+    unsigned long long *prv_data = (unsigned long long *)data;
+	int res = 0;
+
+    if(count > ATHRS17_MAC_LEN)
+        len = ATHRS17_MAC_LEN;
+    else
+        len = count;
+		
+    if(copy_from_user((void *)tmp_buf, buffer, len))
+		return -EFAULT;
+
+    tmp_buf[len-1] = 't';
+
+	res = kstrtoll((const char *)tmp_buf, 16, prv_data);
+	if(res < 0)
+		return res;
+    *prv_data = cpu_to_be64p(prv_data);
+    ptr_char = (unsigned char *)prv_data;
+    ptr_char[0] = ptr_char[2];
+    ptr_char[1] = ptr_char[3];
+    ptr_char[2] = ptr_char[4];
+    ptr_char[3] = ptr_char[5];
+    ptr_char[4] = ptr_char[6];
+    ptr_char[5] = ptr_char[7];
+
+    return ret;
+}
+#endif // ifdef AUTO_UPDATE_PPPOE_INFO
+
+
+int napt_procfs_init(void)
+{
+    int ret = 0;
+
+    setup_proc_entry();
+
+    /* create directory */
+    qca_switch_dir = proc_mkdir(NF_PROCFS_DIR, NULL);
+    if(qca_switch_dir == NULL)
+    {
+        ret = -ENOMEM;
+        goto err_out;
+    }
+
+    /* create the /proc file */
+    nf_athrs17_hnat_file = create_proc_entry(NF_ATHRS17_HNAT_NAME, 0644, qca_switch_dir);
+    if (NULL == nf_athrs17_hnat_file)
+    {
+        printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_NAME);
+        goto no_athrs17_hnat;
+    }
+    nf_athrs17_hnat_file->data = &nf_athrs17_hnat;
+    nf_athrs17_hnat_file->read_proc  = procfile_read_int;
+    nf_athrs17_hnat_file->write_proc = procfile_write_int;
+    printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_NAME);
+
+    nf_athrs17_hnat_wan_type_file = create_proc_entry(NF_ATHRS17_HNAT_WAN_TYPE_NAME, NF_PROCFS_PERM, qca_switch_dir);
+    if (NULL == nf_athrs17_hnat_wan_type_file)
+    {
+        printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_TYPE_NAME);
+        goto no_athrs17_hnat_wan_type;
+    }
+    nf_athrs17_hnat_wan_type_file->data = &nf_athrs17_hnat_wan_type;
+    nf_athrs17_hnat_wan_type_file->read_proc  = procfile_read_int;
+    nf_athrs17_hnat_wan_type_file->write_proc = procfile_write_int;
+    printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_TYPE_NAME);
+
+    nf_athrs17_hnat_ppp_id_file = create_proc_entry(NF_ATHRS17_HNAT_PPP_ID_NAME, NF_PROCFS_PERM, qca_switch_dir);
+    if (NULL == nf_athrs17_hnat_ppp_id_file)
+    {
+        printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_ID_NAME);
+        goto no_athrs17_hnat_ppp_id;
+    }
+    nf_athrs17_hnat_ppp_id_file->data = &nf_athrs17_hnat_ppp_id;
+    nf_athrs17_hnat_ppp_id_file->read_proc  = procfile_read_int;
+    nf_athrs17_hnat_ppp_id_file->write_proc = procfile_write_int;
+    printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_ID_NAME);
+
+    nf_athrs17_hnat_udp_thresh_file = create_proc_entry(NF_ATHRS17_HNAT_UDP_THRESH_NAME, NF_PROCFS_PERM, qca_switch_dir);
+    if (NULL == nf_athrs17_hnat_udp_thresh_file)
+    {
+        printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_UDP_THRESH_NAME);
+        goto no_athrs17_hnat_udp_thresh;
+    }
+    nf_athrs17_hnat_udp_thresh_file->data = &nf_athrs17_hnat_udp_thresh;
+    nf_athrs17_hnat_udp_thresh_file->read_proc  = procfile_read_int;
+    nf_athrs17_hnat_udp_thresh_file->write_proc = procfile_write_int;
+    printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_UDP_THRESH_NAME);
+
+    nf_athrs17_hnat_wan_ip_file = create_proc_entry(NF_ATHRS17_HNAT_WAN_IP_NAME, NF_PROCFS_PERM, qca_switch_dir);
+    if (NULL == nf_athrs17_hnat_wan_ip_file)
+    {
+        printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_IP_NAME);
+        goto no_athrs17_hnat_wan_ip;
+    }
+    nf_athrs17_hnat_wan_ip_file->data = &nf_athrs17_hnat_wan_ip;
+    nf_athrs17_hnat_wan_ip_file->read_proc  = procfile_read_ip;
+    nf_athrs17_hnat_wan_ip_file->write_proc = procfile_write_ip;
+    printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_IP_NAME);
+
+    nf_athrs17_hnat_ppp_peer_ip_file = create_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_IP_NAME, NF_PROCFS_PERM, qca_switch_dir);
+    if (NULL == nf_athrs17_hnat_ppp_peer_ip_file)
+    {
+        printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_IP_NAME);
+        goto no_athrs17_hnat_ppp_peer_ip;
+    }
+    nf_athrs17_hnat_ppp_peer_ip_file->data = &nf_athrs17_hnat_ppp_peer_ip;
+    nf_athrs17_hnat_ppp_peer_ip_file->read_proc  = procfile_read_ip;
+    nf_athrs17_hnat_ppp_peer_ip_file->write_proc = procfile_write_ip;
+    printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_IP_NAME);
+
+    nf_athrs17_hnat_ppp_peer_mac_file = create_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME, NF_PROCFS_PERM, qca_switch_dir);
+    if (NULL == nf_athrs17_hnat_ppp_peer_mac_file)
+    {
+        printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME);
+        goto no_athrs17_hnat_ppp_peer_mac;
+    }
+    nf_athrs17_hnat_ppp_peer_mac_file->data = &nf_athrs17_hnat_ppp_peer_mac;
+    nf_athrs17_hnat_ppp_peer_mac_file->read_proc  = procfile_read_mac;
+    nf_athrs17_hnat_ppp_peer_mac_file->write_proc = procfile_write_mac;
+    printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME);
+
+    nf_athrs17_hnat_wan_mac_file = create_proc_entry(NF_ATHRS17_HNAT_WAN_MAC_NAME, NF_PROCFS_PERM, qca_switch_dir);
+    if (NULL == nf_athrs17_hnat_wan_mac_file)
+    {
+        printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_MAC_NAME);
+        goto no_athrs17_hnat_wan_mac;
+    }
+    nf_athrs17_hnat_wan_mac_file->data = &nf_athrs17_hnat_wan_mac;
+    nf_athrs17_hnat_wan_mac_file->read_proc  = procfile_read_mac;
+    nf_athrs17_hnat_wan_mac_file->write_proc = procfile_write_mac;
+    printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_MAC_NAME);
+
+    nf_athrs17_hnat_ppp_id2_file = create_proc_entry(NF_ATHRS17_HNAT_PPP_ID2_NAME, NF_PROCFS_PERM, qca_switch_dir);
+    if (NULL == nf_athrs17_hnat_ppp_id2_file)
+    {
+        printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_ID2_NAME);
+        goto no_athrs17_hnat_ppp_id;
+    }
+    nf_athrs17_hnat_ppp_id2_file->data = &nf_athrs17_hnat_ppp_id2;
+    nf_athrs17_hnat_ppp_id2_file->read_proc  = procfile_read_int;
+    nf_athrs17_hnat_ppp_id2_file->write_proc = procfile_write_int;
+    printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_ID2_NAME);
+
+    nf_athrs17_hnat_ppp_peer_mac2_file = create_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_MAC2_NAME, NF_PROCFS_PERM, qca_switch_dir);
+    if (NULL == nf_athrs17_hnat_ppp_peer_mac2_file)
+    {
+        printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_MAC2_NAME);
+        goto no_athrs17_hnat_ppp_peer_mac;
+    }
+    nf_athrs17_hnat_ppp_peer_mac2_file->data = &nf_athrs17_hnat_ppp_peer_mac2;
+    nf_athrs17_hnat_ppp_peer_mac2_file->read_proc  = procfile_read_mac;
+    nf_athrs17_hnat_ppp_peer_mac2_file->write_proc = procfile_write_mac;
+    printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME);
+
+    return 0;
+
+no_athrs17_hnat_wan_mac:
+    remove_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME, qca_switch_dir);
+no_athrs17_hnat_ppp_peer_mac:
+    remove_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_IP_NAME, qca_switch_dir);
+no_athrs17_hnat_ppp_peer_ip:
+    remove_proc_entry(NF_ATHRS17_HNAT_WAN_IP_NAME, qca_switch_dir);
+no_athrs17_hnat_wan_ip:
+    remove_proc_entry(NF_ATHRS17_HNAT_UDP_THRESH_NAME, qca_switch_dir);
+no_athrs17_hnat_udp_thresh:
+    remove_proc_entry(NF_ATHRS17_HNAT_PPP_ID_NAME, qca_switch_dir);
+no_athrs17_hnat_ppp_id:
+    remove_proc_entry(NF_ATHRS17_HNAT_WAN_TYPE_NAME, qca_switch_dir);
+no_athrs17_hnat_wan_type:
+    remove_proc_entry(NF_ATHRS17_HNAT_NAME, qca_switch_dir);
+no_athrs17_hnat:
+    remove_proc_entry(NF_PROCFS_DIR, NULL);
+err_out:
+    return ret;
+}
+
+void napt_procfs_exit(void)
+{
+    remove_proc_entry(NF_ATHRS17_HNAT_NAME, qca_switch_dir);
+    remove_proc_entry(NF_ATHRS17_HNAT_WAN_TYPE_NAME, qca_switch_dir);
+    remove_proc_entry(NF_ATHRS17_HNAT_PPP_ID_NAME, qca_switch_dir);
+    remove_proc_entry(NF_ATHRS17_HNAT_UDP_THRESH_NAME, qca_switch_dir);
+    remove_proc_entry(NF_ATHRS17_HNAT_WAN_IP_NAME, qca_switch_dir);
+    remove_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_IP_NAME, qca_switch_dir);
+    remove_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME, qca_switch_dir);
+    remove_proc_entry(NF_ATHRS17_HNAT_WAN_MAC_NAME, qca_switch_dir);
+    remove_proc_entry(NF_ATHRS17_HNAT_PPP_ID2_NAME, qca_switch_dir);
+    remove_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_MAC2_NAME, qca_switch_dir);
+    remove_proc_entry(NF_PROCFS_DIR, NULL);
+    printk(KERN_INFO "/proc/%s/%s removed\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_NAME);
+}
+#else
+static ssize_t napt_hnat_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = (a_uint32_t)nf_athrs17_hnat;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t napt_hnat_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	nf_athrs17_hnat = num;
+
+	return count;
+}
+
+static ssize_t napt_wan_type_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = (a_uint32_t)nf_athrs17_hnat_wan_type;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t napt_wan_type_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	nf_athrs17_hnat_wan_type = num;
+
+	return count;
+}
+
+static ssize_t napt_ppp_id_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = (a_uint32_t)nf_athrs17_hnat_ppp_id;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t napt_ppp_id_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	nf_athrs17_hnat_ppp_id = num;
+
+	return count;
+}
+
+static ssize_t napt_udp_thresh_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = (a_uint32_t)nf_athrs17_hnat_udp_thresh;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t napt_udp_thresh_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	nf_athrs17_hnat_udp_thresh = num;
+
+	return count;
+}
+
+static ssize_t napt_wan_ip_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	unsigned char* data;
+
+	data = (unsigned char*)&nf_athrs17_hnat_wan_ip;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%d.%d.%d.%d",
+					data[0], data[1], data[2], data[3]);
+	return count;
+}
+
+static ssize_t napt_wan_ip_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	nf_athrs17_hnat_wan_ip = num;
+
+	return count;
+}
+
+static ssize_t napt_ppp_peer_ip_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	unsigned char* data;
+
+	data = (unsigned char*)&nf_athrs17_hnat_ppp_peer_ip;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%d.%d.%d.%d",
+					data[0], data[1], data[2], data[3]);
+	return count;
+}
+
+static ssize_t napt_ppp_peer_ip_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	nf_athrs17_hnat_ppp_peer_ip = num;
+
+	return count;
+}
+
+static ssize_t napt_peer_mac_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	unsigned char* data;
+
+	data = (unsigned char*)&nf_athrs17_hnat_ppp_peer_mac;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%.2x-%.2x-%.2x-%.2x-%.2x-%.2x",
+					data[0], data[1], data[2], data[3], data[4], data[5]);
+	return count;
+}
+
+static ssize_t napt_peer_mac_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[32];
+	unsigned long long prv_data;
+	unsigned char *ptr_char;
+	int res = 0;
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	res = kstrtoll((const char *)num_buf, 16, &prv_data);
+	if(res < 0)
+		return res;
+
+	prv_data = cpu_to_be64p(&prv_data);
+	ptr_char = (unsigned char *)&prv_data;
+	nf_athrs17_hnat_ppp_peer_mac[0] = ptr_char[2];
+    nf_athrs17_hnat_ppp_peer_mac[1] = ptr_char[3];
+    nf_athrs17_hnat_ppp_peer_mac[2] = ptr_char[4];
+    nf_athrs17_hnat_ppp_peer_mac[3] = ptr_char[5];
+    nf_athrs17_hnat_ppp_peer_mac[4] = ptr_char[6];
+    nf_athrs17_hnat_ppp_peer_mac[5] = ptr_char[7];
+
+	return count;
+}
+
+static ssize_t napt_wan_mac_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	unsigned char* data;
+
+	data = (unsigned char*)&nf_athrs17_hnat_wan_mac;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%.2x-%.2x-%.2x-%.2x-%.2x-%.2x",
+					data[0], data[1], data[2], data[3], data[4], data[5]);
+	return count;
+}
+
+static ssize_t napt_wan_mac_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[32];
+	unsigned long long prv_data;
+	unsigned char *ptr_char;
+	int res = 0;
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	res = kstrtoll((const char *)num_buf, 16, &prv_data);
+	if(res < 0)
+		return res;
+
+	prv_data = cpu_to_be64p(&prv_data);
+	ptr_char = (unsigned char *)&prv_data;
+	nf_athrs17_hnat_wan_mac[0] = ptr_char[2];
+    nf_athrs17_hnat_wan_mac[1] = ptr_char[3];
+    nf_athrs17_hnat_wan_mac[2] = ptr_char[4];
+    nf_athrs17_hnat_wan_mac[3] = ptr_char[5];
+    nf_athrs17_hnat_wan_mac[4] = ptr_char[6];
+    nf_athrs17_hnat_wan_mac[5] = ptr_char[7];
+
+	return count;
+}
+
+static ssize_t napt_peer_mac2_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	unsigned char* data;
+
+	data = (unsigned char*)&nf_athrs17_hnat_ppp_peer_mac2;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%.2x-%.2x-%.2x-%.2x-%.2x-%.2x",
+					data[0], data[1], data[2], data[3], data[4], data[5]);
+	return count;
+}
+
+static ssize_t napt_peer_mac2_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[32];
+	unsigned long long prv_data;
+	unsigned char *ptr_char;
+	int res = 0;
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	res = kstrtoll((const char *)num_buf, 16, &prv_data);
+	if(res < 0)
+		return res;
+
+	prv_data = cpu_to_be64p(&prv_data);
+	ptr_char = (unsigned char *)&prv_data;
+	nf_athrs17_hnat_ppp_peer_mac2[0] = ptr_char[2];
+    nf_athrs17_hnat_ppp_peer_mac2[1] = ptr_char[3];
+    nf_athrs17_hnat_ppp_peer_mac2[2] = ptr_char[4];
+    nf_athrs17_hnat_ppp_peer_mac2[3] = ptr_char[5];
+    nf_athrs17_hnat_ppp_peer_mac2[4] = ptr_char[6];
+    nf_athrs17_hnat_ppp_peer_mac2[5] = ptr_char[7];
+
+	return count;
+}
+
+static ssize_t napt_ppp_id2_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = (a_uint32_t)nf_athrs17_hnat_ppp_id2;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t napt_ppp_id2_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	nf_athrs17_hnat_ppp_id2 = num;
+
+	return count;
+}
+
+static ssize_t napt_sync_counter_en_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = (a_uint32_t)nf_athrs17_hnat_sync_counter_en;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t napt_sync_counter_en_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	nf_athrs17_hnat_sync_counter_en = num;
+
+	return count;
+}
+
+static ssize_t napt_log_en_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = (a_uint32_t)hnat_log_en;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t napt_log_en_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	hnat_log_en = num;
+
+	return count;
+}
+
+static ssize_t napt_scan_period_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = (a_uint32_t)scan_period;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t napt_scan_period_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	scan_period = num;
+
+	return count;
+}
+
+static ssize_t napt_scan_enable_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = (a_uint32_t)scan_enable;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t napt_scan_enable_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	scan_enable = num;
+
+	return count;
+}
+
+static ssize_t napt_need_clean_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = (a_uint32_t)napt_need_clean;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t napt_need_clean_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	napt_need_clean = num;
+
+	return count;
+}
+
+static ssize_t napt_wan_switch_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = (a_uint32_t)wan_switch;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t napt_wan_switch_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	wan_switch = num;
+	napt_wan_switch_prehandle();
+
+	return count;
+}
+
+static ssize_t napt_wan_port_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = (a_uint32_t)nat_wan_port;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t napt_wan_port_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	nat_wan_port = num;
+
+	return count;
+}
+
+static ssize_t napt_thresh_base_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = packet_thres_base;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t napt_thresh_base_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	packet_thres_base = num;
+
+	return count;
+}
+
+static ssize_t napt_polling_quota_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = polling_quota;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t napt_polling_quota_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	polling_quota = num;
+
+	return count;
+}
+
+static ssize_t napt_bypass_check_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = napt_add_bypass_check;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t napt_bypass_check_set(struct device *dev,
+		  struct device_attribute *attr,
+		  const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	napt_add_bypass_check = num;
+
+	return count;
+}
+
+extern void napt_helper_show(void);
+static ssize_t napt_log_show_get(struct device *dev,
+		  struct device_attribute *attr,
+		  char *buf)
+{
+	napt_helper_show();
+	return 0;
+}
+
+struct kobject *napt_sys = NULL;
+static const struct device_attribute napt_hnat_attr =
+	__ATTR(hnat, 0660, napt_hnat_get, napt_hnat_set);
+static const struct device_attribute napt_wan_type_attr =
+	__ATTR(wan_type, 0660, napt_wan_type_get, napt_wan_type_set);
+static const struct device_attribute napt_ppp_id_attr =
+	__ATTR(ppp_id, 0660, napt_ppp_id_get, napt_ppp_id_set);
+static const struct device_attribute napt_udp_thresh_attr =
+	__ATTR(udp_thresh, 0660, napt_udp_thresh_get, napt_udp_thresh_set);
+static const struct device_attribute napt_wan_ip_attr =
+	__ATTR(wan_ip, 0660, napt_wan_ip_get, napt_wan_ip_set);
+static const struct device_attribute napt_ppp_peer_ip_attr =
+	__ATTR(peer_ip, 0660, napt_ppp_peer_ip_get, napt_ppp_peer_ip_set);
+static const struct device_attribute napt_ppp_peer_mac_attr =
+	__ATTR(peer_mac, 0660, napt_peer_mac_get, napt_peer_mac_set);
+static const struct device_attribute napt_wan_mac_attr =
+	__ATTR(wan_mac, 0660, napt_wan_mac_get, napt_wan_mac_set);
+static const struct device_attribute napt_ppp_id2_attr =
+	__ATTR(ppp_id2, 0660, napt_ppp_id2_get, napt_ppp_id2_set);
+static const struct device_attribute napt_ppp_peer_mac2_attr =
+	__ATTR(peer_mac2, 0660, napt_peer_mac2_get, napt_peer_mac2_set);
+static const struct device_attribute napt_sync_counter_en_attr =
+	__ATTR(sync_counter_en, 0660, napt_sync_counter_en_get, napt_sync_counter_en_set);
+static const struct device_attribute napt_log_en_attr =
+	__ATTR(log_en, 0660, napt_log_en_get, napt_log_en_set);
+static const struct device_attribute napt_log_show_attr =
+	__ATTR(log_show, 0660, napt_log_show_get, NULL);
+static const struct device_attribute napt_scan_period_attr =
+	__ATTR(speriod, 0660, napt_scan_period_get, napt_scan_period_set);
+static const struct device_attribute napt_scan_enable_attr =
+	__ATTR(scan_en, 0660, napt_scan_enable_get, napt_scan_enable_set);
+static const struct device_attribute napt_need_clean_attr =
+	__ATTR(napt_clean, 0660, napt_need_clean_get, napt_need_clean_set);
+static const struct device_attribute napt_wan_switch_attr =
+	__ATTR(napt_switch, 0660, napt_wan_switch_get, napt_wan_switch_set);
+static const struct device_attribute napt_wan_port_attr =
+	__ATTR(wan_port, 0660, napt_wan_port_get, napt_wan_port_set);
+static const struct device_attribute napt_thresh_base_attr =
+	__ATTR(thresh_base, 0660, napt_thresh_base_get, napt_thresh_base_set);
+static const struct device_attribute napt_polling_quota_attr =
+	__ATTR(ct_quota, 0660, napt_polling_quota_get, napt_polling_quota_set);
+static const struct device_attribute napt_bypass_check_attr =
+	__ATTR(bypass_check, 0660, napt_bypass_check_get, napt_bypass_check_set);
+
+int napt_procfs_init(void)
+{
+	int ret = 0;
+
+	napt_sys = kobject_create_and_add("ssdk_napt", NULL);
+	if (!napt_sys) {
+		printk("napt failed to register sysfs\n ");
+		return ret;
+	}
+
+
+
+	ret = sysfs_create_file(napt_sys, &napt_hnat_attr.attr);
+	if (ret) {
+		printk("Failed to register hnat SysFS file\n");
+		goto CLEANUP_1;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_wan_type_attr.attr);
+	if (ret) {
+		printk("Failed to register wan type SysFS file\n");
+		goto CLEANUP_2;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_ppp_id_attr.attr);
+	if (ret) {
+		printk("Failed to register ppp id SysFS file\n");
+		goto CLEANUP_3;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_udp_thresh_attr.attr);
+	if (ret) {
+		printk("Failed to register udp thresh SysFS file\n");
+		goto CLEANUP_4;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_wan_ip_attr.attr);
+	if (ret) {
+		printk("Failed to register wan ip SysFS file\n");
+		goto CLEANUP_5;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_ppp_peer_ip_attr.attr);
+	if (ret) {
+		printk("Failed to register ppp peer ip SysFS file\n");
+		goto CLEANUP_6;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_ppp_peer_mac_attr.attr);
+	if (ret) {
+		printk("Failed to register ppp peer mac SysFS file\n");
+		goto CLEANUP_7;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_wan_mac_attr.attr);
+	if (ret) {
+		printk("Failed to register wan mac SysFS file\n");
+		goto CLEANUP_8;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_ppp_id2_attr.attr);
+	if (ret) {
+		printk("Failed to register ppp id2 SysFS file\n");
+		goto CLEANUP_9;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_ppp_peer_mac2_attr.attr);
+	if (ret) {
+		printk("Failed to register ppp peer mac2 SysFS file\n");
+		goto CLEANUP_10;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_sync_counter_en_attr.attr);
+	if (ret) {
+		printk("Failed to register sync counter en SysFS file\n");
+		goto CLEANUP_11;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_log_en_attr.attr);
+	if (ret) {
+		printk("Failed to register log en SysFS file\n");
+		goto CLEANUP_12;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_log_show_attr.attr);
+	if (ret) {
+		printk("Failed to register log show SysFS file\n");
+		goto CLEANUP_13;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_scan_period_attr.attr);
+	if (ret) {
+		printk("Failed to register scan period SysFS file\n");
+		goto CLEANUP_14;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_scan_enable_attr.attr);
+	if (ret) {
+		printk("Failed to register scan enable SysFS file\n");
+		goto CLEANUP_15;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_need_clean_attr.attr);
+	if (ret) {
+		printk("Failed to register napt clean SysFS file\n");
+		goto CLEANUP_16;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_wan_switch_attr.attr);
+	if (ret) {
+		printk("Failed to register napt wan switch SysFS file\n");
+		goto CLEANUP_17;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_wan_port_attr.attr);
+	if (ret) {
+		printk("Failed to register napt wan port SysFS file\n");
+		goto CLEANUP_18;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_thresh_base_attr.attr);
+	if (ret) {
+		printk("Failed to register napt thresh base SysFS file\n");
+		goto CLEANUP_19;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_polling_quota_attr.attr);
+	if (ret) {
+		printk("Failed to register napt polling quota SysFS file\n");
+		goto CLEANUP_20;
+	}
+	ret = sysfs_create_file(napt_sys, &napt_bypass_check_attr.attr);
+	if (ret) {
+		printk("Failed to register napt add check bypass SysFS file\n");
+		goto CLEANUP_21;
+	}
+	return 0;
+CLEANUP_21:
+	sysfs_remove_file(napt_sys, &napt_polling_quota_attr.attr);
+CLEANUP_20:
+	sysfs_remove_file(napt_sys, &napt_thresh_base_attr.attr);
+CLEANUP_19:
+	sysfs_remove_file(napt_sys, &napt_wan_port_attr.attr);
+CLEANUP_18:
+	sysfs_remove_file(napt_sys, &napt_wan_switch_attr.attr);
+CLEANUP_17:
+	sysfs_remove_file(napt_sys, &napt_need_clean_attr.attr);
+CLEANUP_16:
+	sysfs_remove_file(napt_sys, &napt_scan_enable_attr.attr);
+CLEANUP_15:
+	sysfs_remove_file(napt_sys, &napt_scan_period_attr.attr);
+CLEANUP_14:
+	sysfs_remove_file(napt_sys, &napt_log_show_attr.attr);
+CLEANUP_13:
+	sysfs_remove_file(napt_sys, &napt_log_en_attr.attr);
+CLEANUP_12:
+	sysfs_remove_file(napt_sys, &napt_sync_counter_en_attr.attr);
+CLEANUP_11:
+	sysfs_remove_file(napt_sys, &napt_ppp_peer_mac2_attr.attr);
+CLEANUP_10:
+	sysfs_remove_file(napt_sys, &napt_ppp_id2_attr.attr);
+CLEANUP_9:
+	sysfs_remove_file(napt_sys, &napt_wan_mac_attr.attr);
+CLEANUP_8:
+	sysfs_remove_file(napt_sys, &napt_ppp_peer_mac_attr.attr);
+CLEANUP_7:
+	sysfs_remove_file(napt_sys, &napt_ppp_peer_ip_attr.attr);
+CLEANUP_6:
+	sysfs_remove_file(napt_sys, &napt_wan_ip_attr.attr);
+CLEANUP_5:
+	sysfs_remove_file(napt_sys, &napt_udp_thresh_attr.attr);
+CLEANUP_4:
+	sysfs_remove_file(napt_sys, &napt_ppp_id_attr.attr);
+CLEANUP_3:
+	sysfs_remove_file(napt_sys, &napt_wan_type_attr.attr);
+CLEANUP_2:
+	sysfs_remove_file(napt_sys, &napt_hnat_attr.attr);
+CLEANUP_1:
+	kobject_put(napt_sys);
+
+	return ret;
+}
+
+void napt_procfs_exit(void)
+{
+	printk("napt procfs exit\n");
+
+	sysfs_remove_file(napt_sys, &napt_bypass_check_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_polling_quota_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_thresh_base_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_wan_port_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_wan_switch_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_need_clean_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_scan_enable_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_scan_period_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_log_show_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_log_en_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_sync_counter_en_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_ppp_peer_mac2_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_ppp_id2_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_wan_mac_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_ppp_peer_mac_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_ppp_peer_ip_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_wan_ip_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_udp_thresh_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_ppp_id_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_wan_type_attr.attr);
+	sysfs_remove_file(napt_sys, &napt_hnat_attr.attr);
+
+	kobject_put(napt_sys);
+}
+
+
+#endif
+
diff --git a/qca-ssdk/app/nathelper/linux/nat_helper.c b/qca-ssdk/app/nathelper/linux/nat_helper.c
new file mode 100755
index 0000000..789f152
--- /dev/null
+++ b/qca-ssdk/app/nathelper/linux/nat_helper.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifdef KVER32
+#include <linux/kconfig.h> 
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#endif
+#include <linux/string.h>
+
+
+#include "nat_helper.h"
+#include "fal_init.h"
+#include "fal_mirror.h"
+#include "hsl_shared_api.h"
+
+char hnat_log_en = HNAT_LOG_LEVEL_DISABLE;
+char hnat_log_buffer[NAT_LOG_MAX_SIZE];
+
+void hnat_log_msg(int level, char *string, ...)
+{
+
+	va_list   ptr;
+
+	if(level < hnat_log_en)
+		return;
+	memset(hnat_log_buffer, 0, sizeof(hnat_log_buffer));
+	va_start(ptr,string);
+	vsnprintf(hnat_log_buffer,sizeof(hnat_log_buffer), string, ptr);
+	va_end(ptr);
+	aos_printk("%s\n", hnat_log_buffer);
+}
+
+a_uint32_t nat_dev_id = 0;
+static a_bool_t nat_mirror_status = A_FALSE;
+static fal_port_t nat_mirror_port = 0;
+
+sw_error_t
+nat_helper_init(uint32_t dev_id, uint32_t portbmp)
+{
+	if (fal_switch_devid_get(SSDK_CURRENT_CHIP_TYPE, &nat_dev_id) == SW_OK) {
+		/*Add egress port6 if GMAC1 is connected to port6 via SGMII*/
+		if(1 == nat_dev_id) {
+			fal_mirr_analysis_port_get(nat_dev_id, &nat_mirror_port);
+			fal_mirr_port_eg_get(nat_dev_id, 0, &nat_mirror_status);
+
+			fal_mirr_analysis_port_set(nat_dev_id, 6);
+			fal_mirr_port_eg_set(nat_dev_id, 0, A_TRUE);
+		}
+		aos_printk("nat helper module dev_id:%d\n", nat_dev_id);
+	} else {
+		return SW_FAIL;
+	}
+
+	nat_helper_bg_task_init();
+	host_helper_init(portbmp);
+	napt_helper_init();
+	nat_ipt_helper_init();
+
+	aos_printk("Hello, nat helper module for 1.2!\n");
+
+	return SW_OK;
+}
+
+sw_error_t
+nat_helper_cleanup(uint32_t dev_id)
+{
+	if(1 == nat_dev_id) {
+		fal_mirr_analysis_port_set(nat_dev_id, nat_mirror_port);
+		fal_mirr_port_eg_set(nat_dev_id, 0, nat_mirror_status);
+	}
+    host_helper_exit();
+    napt_helper_exit();
+    nat_ipt_helper_exit();
+	nat_helper_bg_task_exit();
+
+    aos_printk("Goodbye, nat helper module!\n");
+
+    return SW_OK;
+}
+
diff --git a/qca-ssdk/app/nathelper/linux/nat_helper.h b/qca-ssdk/app/nathelper/linux/nat_helper.h
new file mode 100755
index 0000000..f8e5870
--- /dev/null
+++ b/qca-ssdk/app/nathelper/linux/nat_helper.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2012, 2015, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _NAT_HELPER_H
+#define _NAT_HELPER_H
+
+#include "sw.h"
+
+#define NAPT_TABLE_BITS 10
+#define NAPT_TABLE_SIZE (1 << NAPT_TABLE_BITS)
+//#define NAPT_TABLE_SIZE 1024
+
+#define S17_WAN_PORT nat_helper_wan_port_get()
+
+void host_helper_init(a_uint32_t portbmp);
+void host_helper_exit(void);
+void  napt_helper_init(void);
+void napt_helper_exit(void);
+void nat_ipt_helper_init(void);
+void nat_ipt_helper_exit(void);
+
+void nat_helper_bg_task_init(void);
+void nat_helper_bg_task_exit(void);
+
+a_uint32_t nat_helper_wan_port_get(void);
+uint32_t get_next_hop(uint32_t daddr,  uint32_t saddr);
+
+void hnat_log_msg(int level, char *string, ...);
+#define NAT_LOG_MAX_SIZE 1024
+enum {
+	HNAT_LOG_LEVEL_DEBUG = 0,
+	HNAT_LOG_LEVEL_INFO,
+	HNAT_LOG_LEVEL_ERR,
+	HNAT_LOG_LEVEL_DISABLE
+};
+#define HNAT_PRINTK(arg...)  \
+			hnat_log_msg(HNAT_LOG_LEVEL_DEBUG, arg)
+#define HNAT_INFO_PRINTK(arg...)  \
+			hnat_log_msg(HNAT_LOG_LEVEL_INFO, arg)
+#define HNAT_ERR_PRINTK(arg...)  \
+			hnat_log_msg(HNAT_LOG_LEVEL_ERR, arg)
+
+
+#endif
diff --git a/qca-ssdk/app/nathelper/linux/nat_ipt_helper.c b/qca-ssdk/app/nathelper/linux/nat_ipt_helper.c
new file mode 100755
index 0000000..d48c26e
--- /dev/null
+++ b/qca-ssdk/app/nathelper/linux/nat_ipt_helper.c
@@ -0,0 +1,761 @@
+/*
+ * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifdef KVER32
+#include <linux/kconfig.h>
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#endif
+#include <linux/netfilter_ipv4/ip_tables.h>
+#include <net/netfilter/nf_nat.h>
+#include <linux/netfilter/nf_nat.h>
+#include <linux/netfilter/xt_multiport.h>
+#include <linux/netfilter/xt_tcpudp.h>
+#include <linux/netfilter/x_tables.h>
+#include "nat_helper.h"
+
+#include "lib/nat_helper_hsl.h"
+#include "lib/nat_helper_dt.h"
+
+
+#define nf_nat_ipv4_multi_range_compat  \
+                nf_nat_ipv4_multi_range_compat
+#define nf_nat_range        nf_nat_ipv4_range
+#define ipt_entry_target    xt_entry_target
+#define ipt_entry_match     xt_entry_match
+
+#define IPT_MATCH_ITERATE(e, fun, args...) \
+({								    \
+	unsigned int i;					\
+	int ret = 0;					\
+	struct xt_entry_match *m;	    \
+								    \
+	for (i = sizeof(struct ipt_entry);	\
+	     i < (e)->target_offset;		\
+	     i += m->u.match_size) {	\
+		m = (void *)e + i;			\
+		ret = fun(m , ##args);		\
+		if (ret != 0)					\
+			break;					    \
+	}							        \
+	ret;							\
+})
+
+#define IPT_ENTRY_ITERATE(entries, size, fun, args...) \
+({								        \
+	unsigned int k, j;					\
+	int ret = 0;						\
+	struct ipt_entry *e;			    \
+								        \
+	for (k = 0, j = 0; k < (size);		\
+	    k += (e)->next_offset, j++) { \
+		e = (void *)(entries) + k;	\
+		if (j < 0)					\
+			continue;				\
+								    \
+		ret = fun(e , ##args);	    \
+		if (ret != 0)				\
+			break;					\
+	}							    \
+	ret;						\
+})
+
+
+#define IPT_BUFFER_INIT_LEN 1000
+#define NF_NAT_INIT_ENTRIES_NUM 5
+
+static int
+nat_ipt_set_ctl(struct sock *sk, int cmd, void __user * user, unsigned int len);
+static int
+nat_ipt_get_ctl(struct sock *sk, int cmd, void __user * user, int *len);
+
+int nat_sockopts_init = 0;
+
+/*those initial value will be overwrited by orignal iptables sockopts*/
+static struct nf_sockopt_ops orgi_ipt_sockopts;
+static struct nf_sockopt_ops tmp_ipt_sockopts =
+{
+    /*pls check linux/in.h*/
+#define IPT_TEMP_BASE_CTL       60
+#define IPT_TEMP_SET_MAX        (IPT_TEMP_BASE_CTL+1)
+#define IPT_TEMP_GET_MAX        (IPT_TEMP_BASE_CTL+2)
+    .pf = PF_INET,
+    .set_optmin = IPT_TEMP_BASE_CTL,
+    .set_optmax = IPT_TEMP_SET_MAX,
+    .set = nat_ipt_set_ctl,
+    .get_optmin = IPT_TEMP_BASE_CTL,
+    .get_optmax = IPT_TEMP_GET_MAX,
+    .get = nat_ipt_get_ctl
+};
+
+static struct nf_sockopt_ops *ipt_sockopts = NULL;
+static uint32_t snat_seq = 0;
+static uint32_t hw_nat_ipt_seq[NAT_HW_NUM] = {0};
+static uint32_t hw_nat_pip_idx[NAT_HW_NUM] = {0};
+static uint8_t *gbuffer, *sbuffer;
+static unsigned int glen, slen;
+static struct ipt_replace old_replace;
+
+static void
+nat_ipt_del(struct ipt_replace ireplace)
+{
+    int i, j;
+    struct ipt_entry *gentry = NULL;
+    struct ipt_entry *sentry = NULL;
+    struct xt_entry_target *gtarget = NULL;
+    struct xt_entry_target *starget = NULL;
+    struct nf_nat_ipv4_multi_range_compat *grange = NULL;
+    struct nf_nat_ipv4_multi_range_compat *srange = NULL;
+    uint8_t *gptr, *sptr;
+	unsigned int oldnum = ireplace.num_counters;
+	unsigned int seq = 1;
+    gptr = gbuffer;
+    sptr = sbuffer;
+
+    HNAT_PRINTK("into nat_ipt_del\n");
+    for (i = oldnum; i >= 0; i--)//NF_NAT_INIT_ENTRIES_NUM; i--)
+    {
+        gentry = (struct ipt_entry *)gptr;
+        sentry = (struct ipt_entry *)sptr;
+        gtarget = (struct xt_entry_target *)((uint8_t *) gentry + gentry->target_offset);
+        starget = (struct xt_entry_target *)((uint8_t *) sentry + sentry->target_offset);
+        grange = (struct nf_nat_ipv4_multi_range_compat *)((uint8_t *) gtarget + sizeof (*gtarget));
+        srange = (struct nf_nat_ipv4_multi_range_compat *)((uint8_t *) starget + sizeof (*starget));
+
+        HNAT_PRINTK("(%d)isis_nat_del name %s:%s#####(%x:%x %x)###\n",
+                    i, gtarget->u.user.name, starget->u.user.name,
+                    gentry->ip.src.s_addr, gentry->ip.dst.s_addr,
+                    grange->range[0].min.all);
+
+        if (strcmp(gtarget->u.user.name, starget->u.user.name))
+        {
+            /*if (!strcmp(gtarget->u.user.name, "DNAT")) {
+                if (gentry->ip.src.s_addr || !gentry->ip.dst.s_addr
+                    || grange->range[0].min.all)
+                    return;
+                goto delete;
+            } else */
+            if (!strcmp(gtarget->u.user.name, "SNAT"))
+            {
+                if (!gentry->ip.src.s_addr || gentry->ip.dst.s_addr
+                        || grange->range[0].min.all)
+                    return;
+                goto delete;
+            }
+            return;
+        } /*else if (!strcmp(gtarget->u.user.name, "DNAT")) {
+            if (memcmp(gentry, sentry, gentry->next_offset)) {
+                if (gentry->ip.src.s_addr || !gentry->ip.dst.s_addr
+                    || grange->range[0].min.all)
+                    return;
+                goto delete;
+            }
+        } */else if (!strcmp(gtarget->u.user.name, "SNAT"))
+        {
+            if (memcmp(gentry, sentry, gentry->next_offset))
+            {
+                if (!gentry->ip.src.s_addr || gentry->ip.dst.s_addr
+                        || grange->range[0].min.all)
+                    return;
+                goto delete;
+            }
+        }
+        gptr += gentry->next_offset;
+        sptr += gentry->next_offset;
+        if(!strcmp(gtarget->u.user.name, "SNAT"))
+        {
+            seq++;
+        }
+    }
+    HNAT_PRINTK("NONE to delete\n");
+    return;
+
+delete:
+    HNAT_PRINTK("READY to delete one\n");
+    for (j = 0; j < NAT_HW_NUM; j++)
+    {
+        HNAT_PRINTK("ready [%d] (hw)%x:(sw)%x######\n",
+                    j, hw_nat_ipt_seq[j], seq);
+        if (hw_nat_ipt_seq[j] == seq)
+        {
+            if(nat_hw_del_by_index(j) != 0)
+            {
+                return;
+            }
+            //public_ip_del(hw_nat_pip_idx[j]);
+        }
+    }
+
+    for(i = 0; i < NAT_HW_NUM; i++)
+    {
+        if(hw_nat_ipt_seq[i] > seq)
+        {
+            hw_nat_ipt_seq[i]--;
+        }
+        else if(hw_nat_ipt_seq[i] == seq)
+        {
+            hw_nat_ipt_seq[i]=0;
+        }
+    }
+
+    return;
+}
+
+static void
+nat_ipt_to_hw_entry(struct ipt_entry *e,
+                    nat_entry_t *nat)
+{
+#define P_ANY  0
+#define P_TCP  6
+#define P_UDP  17
+
+    struct ipt_entry_target *t = (struct ipt_entry_target *)ipt_get_target(e);
+
+    const struct nf_nat_ipv4_multi_range_compat *mr =
+        (struct nf_nat_ipv4_multi_range_compat *)(t->data);
+    const struct nf_nat_range *range = &mr->range[0];
+
+    uint32_t sip = ntohl(e->ip.src.s_addr);
+    uint32_t pip = ntohl(range->min_ip);
+    uint16_t proto = e->ip.proto;
+
+    memset((void *) nat, 0, sizeof (nat_entry_t));
+
+    nat->src_addr = sip;
+    nat->trans_addr = pip;
+
+    if (proto == P_TCP)
+    {
+        nat->flags = FAL_NAT_ENTRY_PROTOCOL_TCP;
+    }
+    else if (proto == P_UDP)
+    {
+        nat->flags = FAL_NAT_ENTRY_PROTOCOL_UDP;
+    }
+    else if (proto == P_ANY)
+    {
+        nat->flags = FAL_NAT_ENTRY_PROTOCOL_ANY;
+    }
+}
+
+static int
+nat_ipt_hw_add(nat_entry_t *nat)
+{
+	uint32_t index = 0;
+    if(nat_hw_add(nat) != 0)
+    {
+        return -1;
+    }
+
+    hw_nat_ipt_seq[nat->entry_id] = snat_seq;
+    HNAT_PRINTK("###nat_ipt_hw_add hw_nat_ipt_seq[%d]:%d###\n",
+                nat->entry_id, snat_seq);
+
+    hw_nat_pip_idx[nat->entry_id] = nat->trans_addr;
+
+    if(nat_hw_prv_base_can_update())
+    {
+        nat_hw_prv_base_set(nat->src_addr);
+        nat_hw_prv_base_update_disable();
+    }
+
+    if(nat_hw_pub_ip_add(nat->trans_addr, &index)!= 0)
+    {
+        return -1;
+    }
+
+    return 0;
+}
+
+static int
+nat_ipt_hw_port_range_add(nat_entry_t *nat,
+                          uint16_t port_start, uint16_t port_end,
+                          struct xt_multiport *xport)
+{
+    unsigned int i;
+
+    nat->flags |= FAL_NAT_ENTRY_PORT_CHECK;
+
+    if(xport)
+    {
+        //some discontinuous ports
+        for (i = 0; i < xport->count; i++)
+        {
+
+            nat->port_num = xport->ports[i];
+            nat->port_range = 1;
+
+            if(nat_ipt_hw_add(nat))
+            {
+                HNAT_PRINTK("isis_nat_add(xport:%d) fail!\n", nat->port_num);
+                return -1;
+            }
+
+            HNAT_PRINTK("(1)isis_nat_add(xport:%d) success\n", nat->port_num);
+        }
+    }
+    else
+    {
+        //one port or port range
+        uint16_t port_min, port_max;
+
+        for (i = port_start; i <= port_end; i+= NAT_HW_PORT_RANGE_MAX)
+        {
+            port_min = i;
+            if((port_end-port_min)>(NAT_HW_PORT_RANGE_MAX-1))
+            {
+                port_max = port_min+(NAT_HW_PORT_RANGE_MAX-1);
+            }
+            else
+            {
+                port_max = port_end;
+            }
+
+            nat->port_num = port_min;
+            nat->port_range = (port_max - port_min + 1);
+
+            if(nat_ipt_hw_add(nat))
+            {
+                HNAT_PRINTK("isis_nat_add(range port:%d~%d) fail!\n",
+                            port_min, port_max);
+                return -1;
+            }
+
+            HNAT_PRINTK("(2)isis_nat_add(range port:%d~%d) success\n", port_min, port_max);
+        }
+    }
+
+    return 0;
+}
+
+static int
+nat_ipt_check_none_matches(struct ipt_entry *e)
+{
+    nat_entry_t nat = {0};
+
+    nat_ipt_to_hw_entry(e, &nat);
+
+    if(nat_ipt_hw_add(&nat) != 0)
+    {
+        HNAT_PRINTK("(1)isis_nat_add(none port)fail!\n");
+        return -1;
+    }
+
+    HNAT_PRINTK("(1)isis_nat_add(none port) success\n");
+
+    return 0;
+}
+static int
+nat_ipt_check_matches(struct ipt_entry_match *m,
+                      struct ipt_entry *e,
+                      unsigned int *j)
+{
+    int ret = 0;
+
+    nat_entry_t nat = {0};
+    uint16_t port_start = 0, port_end = 0;
+    struct xt_multiport *xport = NULL;
+
+    if(strcmp(m->u.user.name, "udp") == 0)
+    {
+        struct xt_udp *udpinfo = (struct xt_udp *)m->data;
+        port_start = udpinfo->spts[0];
+        port_end = udpinfo->spts[1];
+
+    }
+    else if(strcmp(m->u.user.name, "tcp") == 0)
+    {
+        struct xt_tcp *tcpinfo = (struct xt_tcp *)m->data;
+        port_start = tcpinfo->spts[0];
+        port_end = tcpinfo->spts[1];
+
+    }
+    else if(strcmp(m->u.user.name, "multiport") == 0)
+    {
+        struct xt_multiport xport_data = {0};
+		struct ipt_entry_target *t = ipt_get_target(e);
+        xport = &xport_data;
+
+        if(t->u.user.revision == 0)
+        {
+            xport = (struct xt_multiport *)m->data;
+
+        }
+        else if(t->u.user.revision == 1)
+        {
+            const struct xt_multiport_v1 *xportv1 =
+                (struct xt_multiport_v1 *)m->data;
+            memcpy(xport->ports, xportv1->ports, sizeof(xportv1->ports));
+            xport->count = xportv1->count;
+        }
+
+        if(xport->flags != XT_MULTIPORT_SOURCE)
+        {
+            memset(xport->ports, 0, sizeof(xport->ports));
+        }
+
+    }
+    else
+    {
+        (*j)++ ;
+        HNAT_PRINTK("###no support matches m->u.user.name:%s\n",
+                    m->u.user.name);
+        return -1;
+    }
+
+    nat_ipt_to_hw_entry(e, &nat);
+    ret = nat_ipt_hw_port_range_add(&nat, port_start, port_end, xport);
+
+    (*j)++ ;
+
+    return ret;
+}
+
+//check netmask !=32
+#define NAT_IPT_RULE_IS_FOR_NAPT(e)  (((e)->ip.smsk.s_addr) != 0xffffffff)
+#define NAT_IPT_RULE_IS_NONE_MATCHES(e)  (((e)->target_offset) == \
+                                            (sizeof(struct ipt_entry)))
+
+static int
+nat_ipt_find_check_entry(struct ipt_entry *e, unsigned int underflow,
+                         unsigned int *i)
+{
+    int ret = 0;
+    static uint16_t next_offset = 0;
+	struct ipt_entry_target *t = ipt_get_target(e);
+
+    if(*i == 0)
+    {
+        snat_seq = 0;
+        next_offset = e->next_offset;
+    }
+    else
+    {
+        next_offset += e->next_offset;
+    }
+
+    if (!strcmp(t->u.user.name, "SNAT"))
+    {
+        ++snat_seq;
+
+        if(NAT_IPT_RULE_IS_FOR_NAPT(e))
+        {
+            HNAT_PRINTK("this ipt rule only for HW napt offload\n");
+
+        }
+        else
+        {
+            /*for basic nat offload*/
+            HNAT_PRINTK("[%d]next_offset:%d underflow:%d\n",
+                        *i, next_offset, underflow);
+
+            if(next_offset == underflow)  //new one
+            {
+
+                if(NAT_IPT_RULE_IS_NONE_MATCHES(e))
+                {
+                    /*none matches*/
+                    ret = nat_ipt_check_none_matches(e);
+
+                }
+                else
+                {
+                    unsigned int j = 0;
+                    /*iterate matches*/
+                    ret = IPT_MATCH_ITERATE(e, nat_ipt_check_matches, e, &j);
+                }
+            }
+        }
+    }
+
+    (*i)++ ;
+
+    return ret;
+}
+
+static void
+nat_ipt_data_cleanup(void)
+{
+    if (gbuffer)
+        kfree(gbuffer);
+
+    gbuffer = NULL;
+
+    if (sbuffer)
+        kfree(sbuffer);
+
+    sbuffer = NULL;
+}
+
+static void
+nat_ipt_data_init(void)
+{
+    /*alloc initial set buffer*/
+    sbuffer = kmalloc(IPT_BUFFER_INIT_LEN, GFP_ATOMIC);
+
+    if(sbuffer)
+    {
+        memset(sbuffer, 0, IPT_BUFFER_INIT_LEN);
+        slen = IPT_BUFFER_INIT_LEN;
+    }
+    else
+    {
+        HNAT_PRINTK("%s sbuffer memory allocate fail\n", __func__);
+    }
+
+    /*alloc initial get buffer*/
+    gbuffer = kmalloc(IPT_BUFFER_INIT_LEN, GFP_ATOMIC);
+
+    if(gbuffer)
+    {
+        memset(gbuffer, 0, IPT_BUFFER_INIT_LEN);
+        glen = IPT_BUFFER_INIT_LEN;
+    }
+    else
+    {
+        HNAT_PRINTK("%s gbuffer memory allocate fail\n", __func__);
+    }
+
+
+    /*set initial underflow: nf_nat_rule.c*/
+    memset(&old_replace, 0, sizeof (old_replace));
+
+    /*record ipt rule(SNAT) sequence for hw nat*/
+    memset(hw_nat_ipt_seq, 0, NAT_HW_NUM);
+
+    /*record ipt rule(SNAT) pubip index for hw nat*/
+    memset(hw_nat_pip_idx, 0, NAT_HW_NUM);
+}
+
+static void
+nat_ipt_flush(void)
+{
+    napt_hw_flush();
+
+    nat_hw_flush();
+
+    nat_ipt_data_cleanup();
+    nat_ipt_data_init();
+
+    HNAT_PRINTK("------(nat flush done)------\n");
+}
+
+static void
+nat_ipt_add(struct ipt_replace ireplace)
+{
+    unsigned int i = 0;
+
+    IPT_ENTRY_ITERATE(sbuffer,
+                      ireplace.size,
+                      nat_ipt_find_check_entry,
+                      ireplace.underflow[NF_INET_POST_ROUTING],
+                      &i);
+}
+
+static int
+nat_ipt_hook_type_check(struct ipt_replace ireplace)
+{
+    int ret = -1;
+
+    HNAT_PRINTK("------we only support SNAT-----\n");
+
+    if((old_replace.underflow[NF_INET_POST_ROUTING]-
+        old_replace.hook_entry[NF_INET_POST_ROUTING]) !=
+        (ireplace.underflow[NF_INET_POST_ROUTING]-
+        ireplace.hook_entry[NF_INET_POST_ROUTING]))
+    {
+        HNAT_PRINTK("------this is POSTROUTING(SNAT):yes!------\n");
+        ret = 0;
+
+    }
+    else if ((old_replace.underflow[NF_INET_PRE_ROUTING]-
+        old_replace.hook_entry[NF_INET_PRE_ROUTING]) !=
+        (ireplace.underflow[NF_INET_PRE_ROUTING]-
+        ireplace.hook_entry[NF_INET_PRE_ROUTING]))
+    {
+        HNAT_PRINTK("------this is PREROUTING(DNAT):no!------\n");
+
+    }
+    else if((old_replace.underflow[NF_INET_LOCAL_OUT]-
+        old_replace.hook_entry[NF_INET_LOCAL_OUT]) !=
+        (ireplace.underflow[NF_INET_LOCAL_OUT]-
+        ireplace.hook_entry[NF_INET_LOCAL_OUT]))
+    {
+        HNAT_PRINTK("------this is OUTPUT:no!------\n");
+
+    }
+    else
+    {
+        HNAT_PRINTK("------this is UNKNOW:no!------\n");
+
+    }
+
+    return ret;
+}
+
+static void
+nat_ipt_rules_cp_from_user(void **buf, unsigned int *buf_len,
+                           void __user *user, unsigned int user_len)
+{
+    if((*buf == 0) || (user == 0))
+    {
+        return;
+    }
+
+    if (*buf_len < user_len)
+    {
+        if(*buf)
+        {
+            kfree(*buf);
+            *buf = kmalloc(user_len, GFP_ATOMIC);
+			if(*buf == NULL)
+			{
+				HNAT_PRINTK("%s memory allocate fail\n", __func__);
+				return;
+			}
+            *buf_len = user_len;
+        }
+    }
+    HNAT_PRINTK("(2)nat_ipt_rules_cp_from_user *buf:%x user:%x user_len:%d\n",
+                (unsigned int)(uintptr_t)*buf, (unsigned int)(uintptr_t)user, user_len);
+    copy_from_user(*buf, user, user_len);
+
+    return;
+}
+
+static int
+nat_ipt_set_ctl(struct sock *sk, int cmd, void __user * user, unsigned int len)
+{
+    struct ipt_replace ireplace;
+
+	memset(&ireplace, 0, sizeof(ireplace));
+
+    HNAT_PRINTK("NAT set hook\n");
+
+    if (cmd != IPT_SO_SET_REPLACE)
+        goto normal;
+
+    copy_from_user(&ireplace, user, sizeof (ireplace));
+
+    if (strcmp(ireplace.name, "nat")
+            || (ireplace.num_entries == ireplace.num_counters))
+    {
+        HNAT_PRINTK("none NAT or no new entry %d", ireplace.num_entries);
+        goto normal;
+    }
+
+
+    if (ireplace.num_entries == NF_NAT_INIT_ENTRIES_NUM)
+    {
+        nat_ipt_flush();
+        goto normal;
+    }
+
+    if (nat_ipt_hook_type_check(ireplace) != 0)
+    {
+        goto normal;
+    }
+
+    nat_ipt_rules_cp_from_user((void **)&sbuffer, &slen,
+                               (user + sizeof (ireplace)),
+                               ireplace.size);
+
+    if (ireplace.num_entries > ireplace.num_counters)
+    {
+        nat_ipt_add(ireplace);
+    }
+    else
+    {
+        nat_ipt_del(ireplace);
+    }
+
+normal:
+    /*save old_replace for next hook type check*/
+    old_replace = ireplace;
+
+    return orgi_ipt_sockopts.set(sk, cmd, user, len);
+}
+
+static int
+nat_ipt_get_ctl(struct sock *sk, int cmd, void __user * user, int *len)
+{
+    int k = orgi_ipt_sockopts.get(sk, cmd, user, len);
+
+    if (cmd == IPT_SO_GET_ENTRIES)
+    {
+
+        struct ipt_get_entries entries;
+
+        copy_from_user(&entries, user, sizeof (entries));
+
+        nat_ipt_rules_cp_from_user((void **)&gbuffer, &glen,
+                                   (user + sizeof (struct ipt_get_entries)),
+                                   (*len - sizeof (entries)));
+    }
+    return k;
+}
+
+
+void
+nat_ipt_sockopts_replace(void)
+{
+	int ret = 0;
+    /*register an temp sockopts to find ipt_sockopts*/
+    if((ret = nf_register_sockopt(&tmp_ipt_sockopts)) < 0) {
+		return;
+    }
+    list_for_each_entry(ipt_sockopts, tmp_ipt_sockopts.list.next, list)
+    {
+        if (ipt_sockopts->set_optmin == IPT_BASE_CTL)
+        {
+			nat_sockopts_init = 1;
+            break;
+        }
+    }
+    nf_unregister_sockopt(&tmp_ipt_sockopts);
+	if(!nat_sockopts_init)
+		return;
+
+    /*save orginal ipt_sockopts*/
+    orgi_ipt_sockopts = *ipt_sockopts;
+
+    /*replace ipt_sockopts with our opts*/
+    ipt_sockopts->set = nat_ipt_set_ctl;
+    ipt_sockopts->get = nat_ipt_get_ctl;
+}
+
+static void
+nat_ipt_sockopts_restore(void)
+{
+    ipt_sockopts->set = orgi_ipt_sockopts.set;
+    ipt_sockopts->get = orgi_ipt_sockopts.get;
+}
+
+void
+nat_ipt_helper_init(void)
+{
+    nat_ipt_sockopts_replace();
+    nat_ipt_data_init();
+}
+
+void
+nat_ipt_helper_exit(void)
+{
+    nat_ipt_sockopts_restore();
+    nat_ipt_data_cleanup();
+    nat_hw_flush();
+}
+
diff --git a/qca-ssdk/build.sh b/qca-ssdk/build.sh
new file mode 100755
index 0000000..c0d1b70
--- /dev/null
+++ b/qca-ssdk/build.sh
@@ -0,0 +1,93 @@
+#!/bin/bash
+
+set -e
+set -o errtrace
+trap 'echo Fatal error: script $0 aborting at line $LINENO, command \"$BASH_COMMAND\" returned $?; exit 1' ERR
+
+PRODUCT_LIST="sirocco"
+
+NUM_JOBS=$(grep -c processor /proc/cpuinfo)
+
+###################################################
+# Setup build toollchain
+###################################################
+sdk_top_dir=$(readlink -e $(dirname $0)/..)
+TOP_DIR=$(readlink -e ${sdk_top_dir}/..)
+
+#export ARCH and build related envs.
+source ${TOP_DIR}/sdk/build_scripts/setup_env.sh
+
+kver=5.4
+tool_path=${CROSS_COMPILER_DIR}
+kernel_path=$(readlink -e ${sdk_top_dir}/../kernel)
+
+makeflags="KVER=${kver} TOOL_PATH=${tool_path} SYS_PATH=${kernel_path} TOOLPREFIX=${CROSS_COMPILE} CHIP_TYPE=MP ISISC_ENABLE=enable HK_CHIP=enable"
+
+##################################################
+# Build Kernel Module
+##################################################
+function BuildKModule() {
+    # make kernel module
+    echo "Build qca-ssdk"
+    ${CROSS_MAKE} ${makeflags} V=1
+}
+
+##################################################
+# Build & Install
+##################################################
+function BuildAndInstall() {
+    local product=$1
+    local eureka_src_path=$(readlink -e $2)
+    if [ -z ${eureka_src_path} ]; then
+      echo "eureka_src_path doesn't exist"
+      exit 1
+    fi
+
+    # clean previous build
+    make ${makeflags} clean
+
+    # build module
+    BuildKModule
+
+    # install module
+    echo "Install qca-ssdk.ko"
+    local module_target_dir="$(GetModulePath ${eureka_src_path} ${product})"
+    mkdir -p ${module_target_dir}
+    cp -f build/bin/qca-ssdk.ko ${module_target_dir}/.
+}
+
+function Usage() {
+    cat << EOF
+Usage:
+    $0 <product> <eureka_src_path>
+    Valid products: ${PRODUCT_LIST}
+EOF
+}
+
+function IsProductValid() {
+  local product
+  local ret=1
+
+  for product in ${PRODUCT_LIST}; do
+    if [ "${product}" == "$1" ]; then
+      ret=0
+      break
+    fi
+  done
+
+  return ${ret}
+}
+
+#########################
+####### Main Entry ######
+#########################
+if (( $# < 2 )); then
+  Usage
+else
+  if IsProductValid $1; then
+    BuildAndInstall $1 $2
+  else
+    echo "$1 is a invalid product"
+    Usage
+  fi
+fi
diff --git a/qca-ssdk/config b/qca-ssdk/config
new file mode 100755
index 0000000..91f5e87
--- /dev/null
+++ b/qca-ssdk/config
@@ -0,0 +1,423 @@
+#############################################
+#	Arch/Board Generic Setting	    #
+#############################################
+#CPU=mips
+OS=linux
+
+ifeq ($(KVER),$(filter 3.14%,$(KVER)))
+	OS_VER=3_14
+endif
+
+ifeq ($(KVER),$(filter 4.4%,$(KVER)))
+	OS_VER=4_4
+endif
+
+ifeq ($(KVER),$(filter 4.1%,$(KVER)))
+	OS_VER=4_1
+endif
+
+ifeq ($(KVER),$(filter 4.9%,$(KVER)))
+	OS_VER=4_9
+endif
+
+ifeq ($(KVER),$(filter 5.4%,$(KVER)))
+	OS_VER=5_4
+endif
+
+ifeq ($(KVER), 3.4.0)
+	OS_VER=3_4
+endif
+
+ifeq ($(KVER), 3.18)
+	OS_VER=3_18
+endif
+
+ifeq ($(KVER), 3.18.21)
+	OS_VER=3_18
+endif
+
+ifeq ($(KVER), 3.4.103)
+	OS_VER=3_4
+endif
+
+ifeq ($(KVER), 3.3.8)
+	OS_VER=3_2
+endif
+
+ifeq ($(ARCH), arm)
+	BOARD=ipq806x
+endif
+
+ifeq ($(ARCH), mips)
+	BOARD=ar71xx
+endif
+
+ifeq ($(BOARD), ar71xx)
+	BOARD_NAME=BOARD_AR71XX
+endif
+
+ifeq ($(BOARD), ipq806x)
+	BOARD_NAME=BOARD_IPQ806X
+endif
+
+OS_SUB=31
+
+ifndef OS_VER
+	OS_VER=2_6
+endif
+
+#OS subversion, 2.6.31 for WASP (db120)
+#OS_SUB=31
+
+#GCC version, 3 or 4
+#GCC_VER=4
+
+#############################################
+#	MIPS Linux2.6 Specfic Setting       #
+#############################################
+#pb45
+#TOOL_PATH=/disk/pb45/sw/build/gcc-3.4.4-2.16.1/build_mips_nofpu/bin
+#SYS_PATH=/disk/pb45/sw/linux/kernels/mips-linux-2.6.15
+
+#ap81 compatiable with OpenWRT
+ifndef TOOL_PATH
+	TOOL_PATH=/disk/ap81fus/sw/build/gcc-3.4.4-2.16.1/build_mips/bin
+endif
+
+ifndef SYS_PATH
+	SYS_PATH=/disk/ap81fus/sw/linux/kernels/mips-linux-2.6.15
+endif
+
+ifeq ($(ARCH), mips)
+	CPU_CFLAG=-Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-common -fno-strict-aliasing -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB -D$(BOARD_NAME)
+endif
+
+#db120
+ifeq ($(BOARD_TYPE),db12x)
+	OS_SUB=31
+	GCC_VER=4
+	TOOL_PATH=$(TOPDIR)/build/gcc-4.3.3/build_mips/staging_dir/usr/bin
+	SYS_PATH=$(TOPDIR)/linux/kernels/mips-linux-2.6.31
+	CPU_CFLAG=-Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB
+endif
+
+#############################################
+#	ARM Specfic Setting                 #
+#############################################
+ifeq ($(ARCH), arm)
+	ifeq ($(KVER), 3.4.0)
+		CPU_CFLAG=-D__LINUX_ARM_ARCH__=7  -DMODULE -fno-common -DCONFIG_MMU -D$(BOARD_NAME)
+	endif
+	ifeq ($(KVER), 3.4.103)
+		CPU_CFLAG=-D__LINUX_ARM_ARCH__=7  -DMODULE -fno-common -DCONFIG_MMU -D$(BOARD_NAME)
+	endif
+	ifeq ($(KVER), 3.18.21)
+		CPU_CFLAG=-D__LINUX_ARM_ARCH__=7  -DMODULE -fno-common -DCONFIG_MMU -D$(BOARD_NAME)
+	endif
+	ifeq ($(KVER),$(filter 4.4% 5.4%,$(KVER)))
+		CPU_CFLAG=-D__LINUX_ARM_ARCH__=7  -DMODULE -fno-common -DCONFIG_MMU -D$(BOARD_NAME)
+	endif
+	
+	ifeq ($(KVER),$(filter 3.14%,$(KVER)))
+		CPU_CFLAG= -DMODULE -nostdinc -D$(BOARD_NAME) -mlittle-endian -Wundef -Wstrict-prototypes -Wno-trigraphs -Werror -fno-strict-aliasing -fno-common -Wno-format-security -fno-delete-null-pointer-checks -O2 -fno-dwarf2-cfi-asm -mabi=aapcs-linux -mno-thumb-interwork -mfpu=vfp -funwind-tables -marm -D__LINUX_ARM_ARCH__=7 -march=armv7-a -msoft-float -Uarm -Wframe-larger-than=1024 -fno-stack-protector -Wno-unused-but-set-variable -fomit-frame-pointer -g -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-overflow -fconserve-stack -Werror=implicit-int -DCC_HAVE_ASM_GOTO    -D"KBUILD_STR(s)=\#s" -D"KBUILD_BASENAME=KBUILD_STR(mem)"
+	endif
+	
+	ifeq ($(KVER),$(filter 4.9% 4.4% 5.4%,$(KVER)))
+		CPU_CFLAG= -DMODULE -nostdinc -D$(BOARD_NAME) -mlittle-endian -Wundef -Wstrict-prototypes -Wno-trigraphs -Werror -fno-strict-aliasing -fno-common -Wno-format-security -fno-delete-null-pointer-checks -O2 -fno-dwarf2-cfi-asm -mabi=aapcs-linux -mno-thumb-interwork -mfpu=vfp -funwind-tables -marm -D__LINUX_ARM_ARCH__=7 -march=armv7-a -msoft-float -Uarm -Wframe-larger-than=2048 -fno-stack-protector -Wno-unused-but-set-variable -fomit-frame-pointer -g -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-overflow -fconserve-stack -Werror=implicit-int -DCC_HAVE_ASM_GOTO    -D"KBUILD_STR(s)=\#s" -D"KBUILD_BASENAME=KBUILD_STR(mem)"
+	endif
+	
+	ifeq ($(KVER),$(filter 3.18%,$(KVER)))
+		CPU_CFLAG= -DMODULE -nostdinc -D$(BOARD_NAME) -mlittle-endian -Wundef -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Wno-format-security -fno-delete-null-pointer-checks -O2 -fno-dwarf2-cfi-asm -mabi=aapcs-linux -mno-thumb-interwork -mfpu=vfp -funwind-tables -marm -D__LINUX_ARM_ARCH__=7 -march=armv7-a -msoft-float -Uarm -Wframe-larger-than=1024 -fno-stack-protector -Wno-unused-but-set-variable -fomit-frame-pointer -g -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-overflow -fconserve-stack -Werror=implicit-int -DCC_HAVE_ASM_GOTO    -D"KBUILD_STR(s)=\#s" -D"KBUILD_BASENAME=KBUILD_STR(mem)"
+	endif
+endif
+
+ifeq ($(ARCH), arm64)
+	ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4%,$(KVER)))
+		CPU_CFLAG=  -DMODULE -Os -pipe -march=armv8-a -mcpu=cortex-a53+crypto  -fno-strict-aliasing -Werror -fno-common -Wno-format-security -Wno-pointer-sign -Wno-unused-but-set-variable -Wno-error=unused-result -mcmodel=large
+	endif
+	_COMPILER := $(lastword $(subst -, ,$(strip $(CC))))
+
+	# gcc only cflags
+	ifeq ($(_COMPILER),gcc)
+		CPU_CFLAG += -fno-caller-saves -mpc-relative-literal-loads
+	endif
+
+	# ignore clang warnings
+	ifeq ($(_COMPILER),clang)
+		CPU_CFLAG += -Wno-tautological-constant-compare
+		CPU_CFLAG += -Wno-sometimes-uninitialized
+		CPU_CFLAG += -Wno-asm-operand-widths
+		CPU_CFLAG += -Wno-enum-conversion
+		CPU_CFLAG += -Wno-constant-logical-operand
+		CPU_CFLAG += -Wno-bool-operation
+		CPU_CFLAG += -Wno-gnu-variable-sized-type-not-at-end
+	endif
+endif
+
+#############################################
+#	Board Specfic Setting		    #
+#############################################
+ifeq ($(BOARD_TYPE), ap136)
+	OS_SUB=31
+	GCC_VER=4
+	TOOL_PATH=$(TOPDIR)/build/gcc-4.3.3/build_mips/staging_dir/usr/bin
+	SYS_PATH=$(TOPDIR)/linux/kernels/mips-linux-2.6.31
+	CPU_CFLAG=-Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB
+endif
+
+#############################################
+#	OS Specfic Setting		    #
+#############################################
+#For MIPS Linux2.4
+#TOOL_PATH=/home/perforce/kernel2.4/5.3.1.20/tools/gcc-3.3.3-2.4.25/toolchain_mips/bin
+#SYS_PATH=/home/perforce/kernel2.4/5.3.1.20/src/kernels/mips-linux-2.4.25
+
+#TOOLPREFIX=$(CPU)-$(OS)-
+#CPU_CFLAG=-Wstrict-prototypes -Wundef -fomit-frame-pointer -G 0 -mno-abicalls -Wno-trigraphs -fno-strict-aliasing -fno-common -ffreestanding -O2 -fno-pic -pipe -mabi=32 -march=r4600 -Wa,-32 -Wa,-march=r4600 -Wa,--trap -DMODULE -mlong-calls -DEXPORT_SYMTAB
+
+#############################################
+#	SDK Generic Setting	            #
+#############################################
+ifeq ($(SWCONFIG_FEATURE), disable)
+	SWCONFIG=FALSE
+else
+	SWCONFIG=TRUE
+endif
+
+KERNEL_MODE=TRUE
+
+#compatiable with OpenWRT
+ifeq ($(SWITCH_SSDK_MODE),user)
+	KERNEL_MODE=FLASE
+endif
+
+#FAL=FALSE or not define FAL, FAL will not be included in SSDK
+FAL=TRUE
+
+#############################################
+#	SDK Chip Setting		    #
+#############################################
+#CHIP_TYPE can be defined as ATHENA, GARUDA, SHIVA, HORUS, ISIS, ISISC, DESS, HPPE, CPPE, MP and ALL_CHIP(ALL_CHIP means GARUDA, SHIVA, HORUS, ISIS, ISISC, DESS and HPPE CPPE MP)
+ifndef CHIP_TYPE
+	CHIP_TYPE=ALL_CHIP
+endif
+
+
+#############################################
+#	SDK OS Specfic Setting		    #
+#############################################
+#UK_IF=FALSE or not define UK_IF, UK_IF will not be included in SSDK
+#when UK_IF=TRUE one of UK_NETLINK,UK_IOCTL must be defined as TRUE
+UK_IF=TRUE
+#UK_IOCTL=TRUE define user-kernel space communication based on ioctl
+UK_IOCTL=TRUE
+UK_MINOR_DEV=254
+
+#API_LOCK=FALSE or not define API_LOCK, API_LOCK will not be included in SSDK
+API_LOCK=FALSE
+
+#REG_ACCESS_SPEEDUP=FALSE or not define REG_ACCESS_SPEEDUP, REG_ACCESS_SPEEDUP will not be enabled, now only ISIS supports
+REG_ACCESS_SPEEDUP=FALSE
+
+
+#############################################
+#	All Supported Features	    	    #
+#############################################
+#ACL FDB IGMP LEAKY LED MIB MIRROR MISC PORTCONTROL PORTVLAN QOS RATE STP VLAN
+#IN_X=FALSE or not define IN_X, X will not be included in SSDK
+IN_ACL=TRUE
+IN_FDB=TRUE
+IN_IGMP=TRUE
+IN_LEAKY=TRUE
+IN_LED=TRUE
+IN_MIB=TRUE
+IN_MIRROR=TRUE
+IN_MISC=TRUE
+IN_PORTCONTROL=TRUE
+IN_PORTVLAN=TRUE
+IN_QOS=TRUE
+IN_RATE=TRUE
+IN_STP=TRUE
+IN_VLAN=TRUE
+IN_REDUCED_ACL=FALSE
+IN_COSMAP=TRUE
+IN_IP=TRUE
+IN_NAT=TRUE
+IN_TRUNK=TRUE
+IN_SEC=TRUE
+IN_PPPOE=TRUE
+
+ifeq ($(HNAT_FEATURE), enable)
+	IN_NAT_HELPER=TRUE
+else
+	IN_NAT_HELPER=FALSE
+endif
+
+ifeq ($(RFS_FEATURE), enable)
+	IN_RFS=TRUE
+else
+	IN_RFS=FALSE
+endif
+
+IN_INTERFACECONTROL=TRUE
+IN_MACBLOCK=FALSE
+
+#############################################
+# PHY CHIP Features According To Switch     #
+#############################################
+ifeq (ALL_CHIP, $(CHIP_TYPE))
+	IN_AQUANTIA_PHY=TRUE
+	IN_QCA803X_PHY=TRUE
+	IN_QCA808X_PHY=TRUE
+	IN_PHY_I2C_MODE=TRUE
+	IN_MALIBU_PHY=TRUE
+	IN_SFP_PHY=TRUE
+	IN_SFP=TRUE
+else ifeq (HPPE, $(CHIP_TYPE))
+	IN_AQUANTIA_PHY=TRUE
+	IN_QCA803X_PHY=TRUE
+	IN_QCA808X_PHY=TRUE
+	IN_PHY_I2C_MODE=TRUE
+	IN_SFP_PHY=TRUE
+	IN_MALIBU_PHY=TRUE
+else ifeq (CPPE, $(CHIP_TYPE))
+	IN_QCA808X_PHY=TRUE
+	IN_PHY_I2C_MODE=TRUE
+	IN_MALIBU_PHY=TRUE
+else ifeq (DESS, $(CHIP_TYPE))
+	IN_MALIBU_PHY=TRUE
+else ifeq (MP, $(CHIP_TYPE))
+	IN_QCA803X_PHY=TRUE
+	IN_QCA808X_PHY=TRUE
+else
+	IN_QCA803X_PHY=FALSE
+	IN_QCA808X_PHY=FALSE
+	IN_AQUANTIA_PHY=FALSE
+	IN_MALIBU_PHY=FALSE
+	IN_SFP_PHY=FALSE
+	IN_SFP=FALSE
+endif
+
+ifeq ($(SFE_FEATURE), enable)
+	IN_SFE=TRUE
+else
+	IN_SFE=FALSE
+endif
+
+#QCA808X PHY features
+ifeq ($(IN_QCA808X_PHY), TRUE)
+	ifeq ($(PTP_FEATURE), enable)
+		IN_PTP=TRUE
+	else
+		IN_PTP=FALSE
+	endif
+endif
+
+#IN_PHY_I2C_MODE depends on IN_SFP_PHY
+ifeq ($(IN_PHY_I2C_MODE), TRUE)
+	IN_SFP_PHY=TRUE
+endif
+
+#############################################
+# SDK Features According To Switch Chip     #
+#############################################
+ifneq (, $(filter HPPE CPPE ALL_CHIP, $(CHIP_TYPE)))
+	IN_FLOW=TRUE
+	IN_RSS_HASH=TRUE
+	IN_QM=TRUE
+	IN_VSI=TRUE
+	IN_CTRLPKT=TRUE
+	IN_SERVCODE=TRUE
+	IN_BM=TRUE
+	IN_SHAPER=TRUE
+	IN_POLICER=TRUE
+endif
+
+ifneq (, $(filter HPPE CPPE MP ALL_CHIP, $(CHIP_TYPE)))
+	IN_UNIPHY=TRUE
+endif
+
+#############################################
+# 	MINI SSDK Features Selection        #
+#############################################
+ifeq ($(MINI_SSDK), enable)
+	IN_FDB_MINI=TRUE
+	IN_MISC_MINI=TRUE
+	IN_PORTCONTROL_MINI=TRUE
+	IN_QOS_MINI=TRUE
+	IN_COSMAP_MINI=TRUE
+	IN_PORTVLAN_MINI=TRUE
+	IN_VLAN_MINI=TRUE
+	IN_VSI_MINI=TRUE
+	IN_BM_MINI=TRUE
+	IN_SHAPER_MINI=TRUE
+	IN_POLICER_MINI=TRUE
+	IN_FLOW_MINI=TRUE
+	IN_QM_MINI=TRUE
+	IN_UNIPHY_MINI=TRUE
+	IN_IP_MINI=TRUE
+	IN_SFP=FALSE
+
+	#disable modules for MINI HPPE/CPPE
+	ifneq (, $(filter HPPE CPPE, $(CHIP_TYPE)))
+		IN_SERVCODE=FALSE
+		IN_PPPOE=FALSE
+		IN_NAT=FALSE
+		IN_COSMAP=FALSE
+		IN_RATE=FALSE
+		IN_IGMP=FALSE
+		IN_LEAKY=FALSE
+		IN_LED=FALSE
+		IN_INTERFACECONTROL=FALSE
+	endif
+	
+	ifeq ($(HNAT_FEATURE), enable)
+		IN_MISC_MINI=FALSE
+		IN_PORTVLAN_MINI=FALSE
+		IN_IP_MINI=FALSE
+		IN_MISC=TRUE
+		IN_PORTVLAN=TRUE
+		IN_IP=TRUE
+		IN_NAT=TRUE
+	endif
+endif
+
+#############################################
+# SDK Features According To Specfic Switch  #
+#############################################
+ifneq ($(HK_CHIP), enable)
+	CHIP_TYPE=NONHK_CHIP
+endif
+
+ifeq (MP, $(CHIP_TYPE))
+	ifeq (disable, $(ISISC_ENABLE))
+		IN_ACL=FALSE
+		IN_FDB=FALSE
+		IN_IGMP=FALSE
+		IN_LEAKY=FALSE
+		IN_LED=FALSE
+		IN_MIRROR=FALSE
+		IN_MISC=FALSE
+		IN_PORTVLAN=FALSE
+		IN_QOS=FALSE
+		IN_RATE=FALSE
+		IN_STP=FALSE
+		IN_VLAN=FALSE
+		IN_REDUCED_ACL=FALSE
+		IN_COSMAP=FALSE
+		IN_IP=FALSE
+		IN_NAT=FALSE
+		IN_FLOW=FALSE
+		IN_TRUNK=FALSE
+		IN_RSS_HASH=FALSE
+		IN_SEC=FALSE
+		IN_QM=FALSE
+		IN_PPPOE=FALSE
+		IN_VSI=FALSE
+		IN_CTRLPKT=FALSE
+		IN_SERVCODE=FALSE
+		IN_BM=FALSE
+		IN_SHAPER=FALSE
+		IN_POLICER=FALSE
+	endif
+endif
diff --git a/qca-ssdk/include/adpt/adpt.h b/qca-ssdk/include/adpt/adpt.h
new file mode 100755
index 0000000..b497350
--- /dev/null
+++ b/qca-ssdk/include/adpt/adpt.h
@@ -0,0 +1,1604 @@
+/*
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _ADPT_H_
+#define _ADPT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal_fdb.h"
+#include "fal_portvlan.h"
+#include "fal_ctrlpkt.h"
+#include "fal_servcode.h"
+#include "fal_rss_hash.h"
+#include "fal_mib.h"
+#include "fal_port_ctrl.h"
+#include "fal_mirror.h"
+#include "fal_trunk.h"
+#include "fal_ip.h"
+#include "fal_qm.h"
+#include "fal_flow.h"
+#include "ssdk_init.h"
+#include "fal_type.h"
+#include "fal_stp.h"
+#include "fal_vsi.h"
+#include "fal_pppoe.h"
+#include "fal_sec.h"
+#include "fal_acl.h"
+#include "fal_qos.h"
+#include "fal_shaper.h"
+#include "fal_bm.h"
+#include "fal_init.h"
+#include "fal_policer.h"
+#include "fal_misc.h"
+#include "fal_ptp.h"
+#include "fal_sfp.h"
+#include "ssdk_plat.h"
+
+#define ADPT_DEV_ID_CHECK(dev_id) \
+do { \
+    if (dev_id >= SW_MAX_NR_DEV) \
+        return SW_OUT_OF_RANGE; \
+} while (0)
+
+#define ADPT_PORT_ID_CHECK(port_id) \
+do { \
+    if (port_id >= SW_MAX_NR_PORT) \
+        return SW_OUT_OF_RANGE; \
+} while (0)
+
+#define ADPT_NULL_POINT_CHECK(point) \
+do { \
+    if (point == NULL) \
+        return SW_BAD_PTR; \
+} while (0)
+
+typedef sw_error_t (*adpt_fdb_first_func)(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+typedef sw_error_t (*adpt_fdb_next_func)(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+typedef sw_error_t (*adpt_fdb_add_func)(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+typedef sw_error_t (*adpt_fdb_age_time_set_func)(a_uint32_t dev_id, a_uint32_t * time);
+typedef sw_error_t (*adpt_fdb_extend_next_func)(a_uint32_t dev_id, fal_fdb_op_t * option,
+                        fal_fdb_entry_t * entry);
+typedef sw_error_t (*adpt_fdb_learn_ctrl_get_func)(a_uint32_t dev_id, a_bool_t * enable);
+typedef sw_error_t (*adpt_fdb_age_time_get_func)(a_uint32_t dev_id, a_uint32_t * time);
+typedef sw_error_t (*adpt_port_fdb_learn_limit_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable, a_uint32_t cnt);
+typedef sw_error_t (*adpt_fdb_port_add_func)(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+typedef sw_error_t (*adpt_fdb_port_learn_set_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+typedef sw_error_t (*adpt_fdb_port_learn_get_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+typedef sw_error_t (*adpt_fdb_port_newaddr_lrn_set_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd);
+typedef sw_error_t (*adpt_fdb_port_newaddr_lrn_get_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd);
+typedef sw_error_t (*adpt_fdb_port_stamove_set_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd);
+typedef sw_error_t (*adpt_fdb_port_stamove_get_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd);
+typedef sw_error_t (*adpt_port_fdb_learn_counter_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t * cnt);
+typedef sw_error_t (*adpt_fdb_extend_first_func)(a_uint32_t dev_id, fal_fdb_op_t * option,
+                         fal_fdb_entry_t * entry);
+typedef sw_error_t (*adpt_fdb_transfer_func)(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+                     a_uint32_t fid, fal_fdb_op_t * option);
+typedef sw_error_t (*adpt_fdb_port_del_func)(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+typedef sw_error_t (*adpt_fdb_find_func)(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+typedef sw_error_t (*adpt_fdb_learn_ctrl_set_func)(a_uint32_t dev_id, a_bool_t enable);
+typedef sw_error_t (*adpt_port_fdb_learn_exceed_cmd_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+                                      fal_fwd_cmd_t * cmd);
+typedef sw_error_t (*adpt_fdb_del_by_port_func)(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag);
+typedef sw_error_t (*adpt_port_fdb_learn_limit_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable, a_uint32_t * cnt);
+typedef sw_error_t (*adpt_fdb_age_ctrl_set_func)(a_uint32_t dev_id, a_bool_t enable);
+typedef sw_error_t (*adpt_fdb_del_by_mac_func)(a_uint32_t dev_id, const fal_fdb_entry_t *entry);
+typedef sw_error_t (*adpt_fdb_iterate_func)(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry);
+typedef sw_error_t (*adpt_port_fdb_learn_exceed_cmd_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+                                      fal_fwd_cmd_t cmd);
+typedef sw_error_t (*adpt_fdb_del_all_func)(a_uint32_t dev_id, a_uint32_t flag);
+typedef sw_error_t (*adpt_fdb_age_ctrl_get_func)(a_uint32_t dev_id, a_bool_t * enable);
+typedef sw_error_t (*adpt_fdb_port_maclimit_ctrl_set_func)(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl);
+typedef sw_error_t (*adpt_fdb_port_maclimit_ctrl_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl);
+typedef sw_error_t (*adpt_fdb_del_by_fid_func)(a_uint32_t dev_id, a_uint16_t fid, a_uint32_t flag);
+
+typedef sw_error_t (*adpt_mib_cpukeep_get_func)(a_uint32_t dev_id, a_bool_t * enable);
+typedef sw_error_t (*adpt_mib_cpukeep_set_func)(a_uint32_t dev_id, a_bool_t  enable);
+typedef sw_error_t (*adpt_get_mib_info_func)(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_mib_info_t * mib_info );
+typedef sw_error_t (*adpt_get_tx_mib_info_func)(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_mib_info_t * mib_info );
+typedef sw_error_t (*adpt_mib_status_set_func)(a_uint32_t dev_id, a_bool_t enable);
+typedef sw_error_t (*adpt_mib_port_flush_counters_func)(a_uint32_t dev_id, fal_port_t port_id);
+typedef sw_error_t (*adpt_mib_status_get_func)(a_uint32_t dev_id, a_bool_t * enable);
+typedef sw_error_t (*adpt_get_rx_mib_info_func)(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_mib_info_t * mib_info );
+typedef sw_error_t (*adpt_get_xgmib_info_func)(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_xgmib_info_t * mib_info );
+typedef sw_error_t (*adpt_get_tx_xgmib_info_func)(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_xgmib_info_t * mib_info );
+typedef sw_error_t (*adpt_get_rx_xgmib_info_func)(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_xgmib_info_t * mib_info );
+
+typedef sw_error_t (*adpt_stp_port_state_get_func)(a_uint32_t dev_id, a_uint32_t st_id,
+                     fal_port_t port_id, fal_stp_state_t * state);
+typedef sw_error_t (*adpt_stp_port_state_set_func)(a_uint32_t dev_id, a_uint32_t st_id,
+                     fal_port_t port_id, fal_stp_state_t state);
+
+typedef sw_error_t (*adpt_port_vlan_vsi_set_func)(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id);
+typedef sw_error_t (*adpt_port_vlan_vsi_get_func)(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t *vsi_id);
+typedef sw_error_t (*adpt_port_vsi_set_func)(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vsi_id);
+typedef sw_error_t (*adpt_port_vsi_get_func)(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vsi_id);
+typedef sw_error_t (*adpt_vsi_stamove_set_func)(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove);
+typedef sw_error_t (*adpt_vsi_stamove_get_func)(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove);
+typedef sw_error_t (*adpt_vsi_newaddr_lrn_set_func)(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn);
+typedef sw_error_t (*adpt_vsi_newaddr_lrn_get_func)(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn);
+typedef sw_error_t (*adpt_vsi_member_set_func)(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member);
+typedef sw_error_t (*adpt_vsi_member_get_func)(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member);
+typedef sw_error_t (*adpt_vsi_counter_get_func)(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_counter_t *counter);
+typedef sw_error_t (*adpt_vsi_counter_cleanup_func)(a_uint32_t dev_id, a_uint32_t vsi_id);
+
+// portctrl function.
+
+typedef sw_error_t (*adpt_port_local_loopback_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					a_bool_t * enable);
+typedef sw_error_t (*adpt_port_autoneg_restart_func)(a_uint32_t dev_id, fal_port_t port_id);
+typedef sw_error_t (*adpt_port_duplex_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_duplex_t duplex);
+typedef sw_error_t (*adpt_port_rxmac_status_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					  a_bool_t * enable);
+typedef sw_error_t (*adpt_port_cdt_func)(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t mdi_pair, fal_cable_status_t * cable_status,
+		a_uint32_t * cable_len);
+typedef sw_error_t (*adpt_port_txmac_status_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+					  a_bool_t enable);
+typedef sw_error_t (*adpt_port_combo_fiber_mode_set_func)(a_uint32_t dev_id,
+						  a_uint32_t port_id,
+						  fal_port_fiber_mode_t mode);
+typedef sw_error_t (*adpt_port_combo_medium_status_get_func)(a_uint32_t dev_id,
+							 a_uint32_t port_id,
+							 fal_port_medium_t *
+							 medium);
+typedef sw_error_t (*adpt_port_magic_frame_mac_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+				   fal_mac_addr_t * mac);
+typedef sw_error_t (*adpt_port_powersave_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable);
+typedef sw_error_t (*adpt_port_hibernate_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable);
+typedef sw_error_t (*adpt_port_max_frame_size_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t max_frame);
+typedef sw_error_t (*adpt_port_8023az_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t * enable);
+typedef sw_error_t (*adpt_port_rxfc_status_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					 a_bool_t * enable);
+typedef sw_error_t (*adpt_port_txfc_status_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					 a_bool_t * enable);
+typedef sw_error_t (*adpt_port_remote_loopback_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+					 a_bool_t enable);
+typedef sw_error_t (*adpt_port_flowctrl_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t enable);
+typedef sw_error_t (*adpt_port_mru_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl);
+typedef sw_error_t (*adpt_port_autoneg_status_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					a_bool_t * status);
+typedef sw_error_t (*adpt_port_txmac_status_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					  a_bool_t * enable);
+typedef sw_error_t (*adpt_port_mdix_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+				  fal_port_mdix_mode_t * mode);
+typedef sw_error_t (*adpt_ports_link_status_get_func)(a_uint32_t dev_id, a_uint32_t * status);
+typedef sw_error_t (*adpt_port_mac_loopback_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t enable);
+typedef sw_error_t (*adpt_port_phy_id_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+			  a_uint16_t * org_id, a_uint16_t * rev_id);
+typedef sw_error_t (*adpt_port_mru_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl);
+typedef sw_error_t (*adpt_port_power_on_func)(a_uint32_t dev_id, fal_port_t port_id);
+typedef sw_error_t (*adpt_port_speed_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+				   fal_port_speed_t speed);
+typedef sw_error_t (*adpt_port_interface_mode_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+				  fal_port_interface_mode_t * mode);
+typedef sw_error_t (*adpt_port_duplex_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_duplex_t * pduplex);
+typedef sw_error_t (*adpt_port_autoneg_adv_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					 a_uint32_t * autoadv);
+typedef sw_error_t (*adpt_port_mdix_status_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					 fal_port_mdix_status_t * mode);
+typedef sw_error_t (*adpt_port_mtu_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl);
+typedef sw_error_t (*adpt_port_link_status_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					 a_bool_t * status);
+typedef sw_error_t (*adpt_port_8023az_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t enable);
+typedef sw_error_t (*adpt_port_powersave_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable);
+typedef sw_error_t (*adpt_port_combo_prefer_medium_get_func)(a_uint32_t dev_id,
+							 a_uint32_t port_id,
+							 fal_port_medium_t *
+							 medium);
+typedef sw_error_t (*adpt_port_max_frame_size_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t *max_frame);
+typedef sw_error_t (*adpt_port_combo_prefer_medium_set_func)(a_uint32_t dev_id,
+						 a_uint32_t port_id,
+						 fal_port_medium_t medium);
+typedef sw_error_t (*adpt_port_power_off_func)(a_uint32_t dev_id, fal_port_t port_id);
+typedef sw_error_t (*adpt_port_txfc_status_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+					 a_bool_t enable);
+typedef sw_error_t (*adpt_port_counter_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+		   a_bool_t enable);
+typedef sw_error_t (*adpt_port_combo_fiber_mode_get_func)(a_uint32_t dev_id,
+						  a_uint32_t port_id,
+						  fal_port_fiber_mode_t * mode);
+typedef sw_error_t (*adpt_port_local_loopback_set_func)(a_uint32_t dev_id,
+						fal_port_t port_id,
+						a_bool_t enable);
+typedef sw_error_t (*adpt_port_wol_status_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t enable);
+typedef sw_error_t (*adpt_port_magic_frame_mac_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+				   fal_mac_addr_t * mac);
+typedef sw_error_t (*adpt_port_flowctrl_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t * enable);
+typedef sw_error_t (*adpt_port_rxmac_status_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+					  a_bool_t enable);
+typedef sw_error_t (*adpt_port_counter_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+		   a_bool_t * enable);
+typedef sw_error_t (*adpt_port_interface_mode_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+				  fal_port_interface_mode_t mode);
+typedef sw_error_t (*adpt_port_mac_loopback_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t * enable);
+typedef sw_error_t (*adpt_port_hibernate_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable);
+typedef sw_error_t (*adpt_port_autoneg_adv_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+					 a_uint32_t autoadv);
+typedef sw_error_t (*adpt_port_remote_loopback_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					 a_bool_t * enable);
+typedef sw_error_t (*adpt_port_counter_show_func)(a_uint32_t dev_id, fal_port_t port_id,
+				 fal_port_counter_info_t * counter_info);
+typedef sw_error_t (*adpt_port_autoneg_enable_func)(a_uint32_t dev_id, fal_port_t port_id);
+typedef sw_error_t (*adpt_port_mtu_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl);
+typedef sw_error_t (*adpt_port_interface_mode_status_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+				  fal_port_interface_mode_t * mode);
+typedef sw_error_t (*adpt_port_reset_func)(a_uint32_t dev_id, fal_port_t port_id);
+typedef sw_error_t (*adpt_port_rxfc_status_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+					 a_bool_t enable);
+typedef sw_error_t (*adpt_port_speed_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+				   fal_port_speed_t * pspeed);
+typedef sw_error_t (*adpt_port_mdix_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+				  fal_port_mdix_mode_t mode);
+typedef sw_error_t (*adpt_port_wol_status_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t * enable);
+typedef sw_error_t (*adpt_port_source_filter_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t * enable);
+typedef sw_error_t (*adpt_port_source_filter_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t enable);
+typedef sw_error_t (*adpt_port_mux_mac_type_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+	a_uint32_t mode0,	a_uint32_t mode1, a_uint32_t mode2);
+typedef sw_error_t (*adpt_port_mac_speed_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_speed_t speed);
+typedef sw_error_t (*adpt_port_mac_duplex_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_duplex_t duplex);
+typedef sw_error_t (*adpt_port_polling_sw_sync_func)(struct qca_phy_priv *priv);
+
+typedef sw_error_t (*adpt_port_bridge_txmac_set_func)(a_uint32_t dev_id,
+		fal_port_t port_id, a_bool_t enable);
+
+typedef sw_error_t (*adpt_port_interface_mode_apply_func)(a_uint32_t dev_id);
+
+typedef sw_error_t (*adpt_port_interface_3az_status_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t enable);
+typedef sw_error_t (*adpt_port_interface_3az_status_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t * enable);
+typedef sw_error_t (*adpt_port_flowctrl_forcemode_set_func) (a_uint32_t dev_id,
+		fal_port_t port_id, a_bool_t enable);
+typedef sw_error_t (*adpt_port_flowctrl_forcemode_get_func) (a_uint32_t dev_id,
+		fal_port_t port_id, a_bool_t * enable);
+typedef sw_error_t (*adpt_port_promisc_mode_set_func)(a_uint32_t dev_id,
+			fal_port_t port_id, a_bool_t enable);
+typedef sw_error_t (*adpt_port_promisc_mode_get_func)(a_uint32_t dev_id,
+			fal_port_t port_id, a_bool_t *enable);
+typedef sw_error_t (*adpt_port_interface_eee_cfg_set_func)(a_uint32_t dev_id,
+			fal_port_t port_id, fal_port_eee_cfg_t *port_eee_cfg);
+typedef sw_error_t (*adpt_port_interface_eee_cfg_get_func)(a_uint32_t dev_id,
+			fal_port_t port_id, fal_port_eee_cfg_t *port_eee_cfg);
+typedef sw_error_t (*adpt_port_source_filter_config_set_func)(a_uint32_t dev_id,
+			fal_port_t port_id, fal_src_filter_config_t *src_filter_config);
+typedef sw_error_t (*adpt_port_source_filter_config_get_func)(a_uint32_t dev_id,
+			fal_port_t port_id, fal_src_filter_config_t *src_filter_config);
+typedef sw_error_t (*adpt_switch_port_loopback_set_func)(a_uint32_t dev_id,
+			fal_port_t port_id, fal_loopback_config_t *loopback_cfg);
+typedef sw_error_t (*adpt_switch_port_loopback_get_func)(a_uint32_t dev_id,
+			fal_port_t port_id, fal_loopback_config_t *loopback_cfg);
+typedef sw_error_t (*adpt_port_netdev_notify_func)(struct qca_phy_priv *priv,
+			a_uint32_t port_id);
+typedef sw_error_t (*adpt_port_phy_status_get_func)(a_uint32_t dev_id,
+			fal_port_t port_id, struct port_phy_status *phy_status);
+// mirror
+typedef sw_error_t (*adpt_mirr_port_in_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable);
+typedef sw_error_t (*adpt_mirr_port_in_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable);
+typedef sw_error_t (*adpt_mirr_port_eg_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable);
+typedef sw_error_t (*adpt_mirr_port_eg_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable);
+typedef sw_error_t (*adpt_mirr_analysis_port_set_func)(a_uint32_t dev_id, fal_port_t port_id);
+typedef sw_error_t (*adpt_mirr_analysis_port_get_func)(a_uint32_t dev_id, fal_port_t * port_id);
+typedef sw_error_t (*adpt_mirr_analysis_config_set_func)(a_uint32_t dev_id, fal_mirr_direction_t direction,
+				fal_mirr_analysis_config_t * config);
+typedef sw_error_t (*adpt_mirr_analysis_config_get_func)(a_uint32_t dev_id, fal_mirr_direction_t direction,
+				fal_mirr_analysis_config_t * config);
+
+//rss hash
+typedef sw_error_t (*adpt_rss_hash_config_set_func)(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config);
+typedef sw_error_t (*adpt_rss_hash_config_get_func)(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config);
+
+//trunk
+typedef sw_error_t (*adpt_trunk_fail_over_en_get_func)(a_uint32_t dev_id, a_bool_t * fail_over);
+typedef sw_error_t (*adpt_trunk_hash_mode_get_func)(a_uint32_t dev_id, a_uint32_t * hash_mode);
+typedef sw_error_t (*adpt_trunk_group_get_func)(a_uint32_t dev_id, a_uint32_t trunk_id,
+                        a_bool_t * enable, fal_pbmp_t * member);
+typedef sw_error_t (*adpt_trunk_group_set_func)(a_uint32_t dev_id, a_uint32_t trunk_id,
+                        a_bool_t enable, fal_pbmp_t member);
+typedef sw_error_t (*adpt_trunk_fail_over_en_set_func)(a_uint32_t dev_id, a_bool_t fail_over);
+typedef sw_error_t (*adpt_trunk_hash_mode_set_func)(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+typedef sw_error_t (*adpt_ip_network_route_get_func)(a_uint32_t dev_id,
+			a_uint32_t index, a_uint8_t type,
+			fal_network_route_entry_t *entry);
+typedef sw_error_t (*adpt_ip_network_route_add_func)(a_uint32_t dev_id,
+			a_uint32_t index,
+			fal_network_route_entry_t *entry);
+typedef sw_error_t (*adpt_ip_network_route_del_func)(a_uint32_t dev_id,
+			a_uint32_t index,
+			a_uint8_t type);
+typedef sw_error_t (*adpt_ip_host_add_func)(
+			a_uint32_t dev_id, fal_host_entry_t * host_entry);
+typedef sw_error_t (*adpt_ip_vsi_sg_cfg_get_func)(
+			a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_sg_cfg_t *sg_cfg);
+typedef sw_error_t (*adpt_ip_pub_addr_set_func)(
+			a_uint32_t dev_id, a_uint32_t index,
+			fal_ip_pub_addr_t *entry);
+typedef sw_error_t (*adpt_ip_pub_addr_get_func)(
+			a_uint32_t dev_id, a_uint32_t index,
+			fal_ip_pub_addr_t *entry);
+typedef sw_error_t (*adpt_ip_port_sg_cfg_set_func)(
+			a_uint32_t dev_id, fal_port_t port_id,
+    			fal_sg_cfg_t *sg_cfg);
+typedef sw_error_t (*adpt_ip_port_intf_get_func)(
+			a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id);
+typedef sw_error_t (*adpt_ip_vsi_arp_sg_cfg_set_func)(
+			a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_arp_sg_cfg_t *arp_sg_cfg);
+typedef sw_error_t (*adpt_ip_port_intf_set_func)(
+			a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id);
+typedef sw_error_t (*adpt_ip_vsi_sg_cfg_set_func)(
+			a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_sg_cfg_t *sg_cfg);
+typedef sw_error_t (*adpt_ip_host_next_func)(
+			a_uint32_t dev_id, a_uint32_t next_mode,
+			fal_host_entry_t * host_entry);
+typedef sw_error_t (*adpt_ip_port_macaddr_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_macaddr_entry_t *macaddr);
+typedef sw_error_t (*adpt_ip_vsi_intf_get_func)(
+			a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id);
+typedef sw_error_t (*adpt_ip_port_sg_cfg_get_func)(
+			a_uint32_t dev_id, fal_port_t port_id,
+    			fal_sg_cfg_t *sg_cfg);
+typedef sw_error_t (*adpt_ip_intf_get_func)(
+    			a_uint32_t dev_id,
+    			a_uint32_t index,
+    			fal_intf_entry_t *entry);
+typedef sw_error_t (*adpt_ip_host_del_func)(
+			a_uint32_t dev_id, a_uint32_t del_mode,
+			fal_host_entry_t * host_entry);
+typedef sw_error_t (*adpt_ip_route_mismatch_get_func)(
+			a_uint32_t dev_id, fal_fwd_cmd_t *cmd);
+typedef sw_error_t (*adpt_ip_vsi_arp_sg_cfg_get_func)(
+			a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_arp_sg_cfg_t *arp_sg_cfg);
+typedef sw_error_t (*adpt_ip_port_arp_sg_cfg_set_func)(
+			a_uint32_t dev_id, fal_port_t port_id,
+    			fal_arp_sg_cfg_t *arp_sg_cfg);
+typedef sw_error_t (*adpt_ip_vsi_mc_mode_set_func)(
+			a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_mc_mode_cfg_t *cfg);
+typedef sw_error_t (*adpt_ip_vsi_intf_set_func)(
+			a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id);
+typedef sw_error_t (*adpt_ip_nexthop_get_func)(a_uint32_t dev_id,
+			a_uint32_t index, fal_ip_nexthop_t *entry);
+typedef sw_error_t (*adpt_ip_route_mismatch_set_func)(
+			a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+typedef sw_error_t (*adpt_ip_host_get_func)(
+			a_uint32_t dev_id, a_uint32_t get_mode,
+                    fal_host_entry_t * host_entry);
+typedef sw_error_t (*adpt_ip_intf_set_func)(
+    			a_uint32_t dev_id,
+    			a_uint32_t index,
+    			fal_intf_entry_t *entry);
+typedef sw_error_t (*adpt_ip_vsi_mc_mode_get_func)(
+			a_uint32_t dev_id,
+			a_uint32_t vsi,
+    			fal_mc_mode_cfg_t *cfg);
+typedef sw_error_t (*adpt_ip_port_macaddr_get_func)(
+			a_uint32_t dev_id, fal_port_t port_id,
+    			fal_macaddr_entry_t *macaddr);
+typedef sw_error_t (*adpt_ip_port_arp_sg_cfg_get_func)(
+			a_uint32_t dev_id, fal_port_t port_id,
+    			fal_arp_sg_cfg_t *arp_sg_cfg);
+typedef sw_error_t (*adpt_ip_nexthop_set_func)(a_uint32_t dev_id,
+			a_uint32_t index, fal_ip_nexthop_t *entry);
+typedef sw_error_t (*adpt_ip_global_ctrl_get_func)(a_uint32_t dev_id,
+			fal_ip_global_cfg_t *cfg);
+typedef sw_error_t (*adpt_ip_global_ctrl_set_func)(a_uint32_t dev_id,
+			fal_ip_global_cfg_t *cfg);
+
+typedef sw_error_t (*adpt_flow_global_cfg_get_func)(
+		a_uint32_t dev_id,
+		fal_flow_global_cfg_t *cfg);
+typedef sw_error_t (*adpt_flow_global_cfg_set_func)(
+		a_uint32_t dev_id,
+		fal_flow_global_cfg_t *cfg);
+typedef sw_error_t (*adpt_flow_host_add_func)(
+		a_uint32_t dev_id,
+		a_uint32_t add_mode,
+		fal_flow_host_entry_t *flow_host_entry);
+typedef sw_error_t (*adpt_flow_entry_get_func)(
+		a_uint32_t dev_id,
+		a_uint32_t get_mode,
+		fal_flow_entry_t *flow_entry);
+typedef sw_error_t (*adpt_flow_entry_del_func)(
+		a_uint32_t dev_id,
+		a_uint32_t del_mode,
+		fal_flow_entry_t *flow_entry);
+typedef sw_error_t (*adpt_flow_entry_next_func)(
+		a_uint32_t dev_id,
+		a_uint32_t next_mode,
+		fal_flow_entry_t *flow_entry);
+typedef sw_error_t (*adpt_flow_status_get_func)(
+		a_uint32_t dev_id, a_bool_t *enable);
+typedef sw_error_t (*adpt_flow_ctrl_set_func)(
+		a_uint32_t dev_id,
+		fal_flow_pkt_type_t type,
+		fal_flow_direction_t dir,
+		fal_flow_mgmt_t *ctrl);
+typedef sw_error_t (*adpt_flow_age_timer_get_func)(
+		a_uint32_t dev_id, fal_flow_age_timer_t *age_timer);
+typedef sw_error_t (*adpt_flow_status_set_func)(
+		a_uint32_t dev_id, a_bool_t enable);
+typedef sw_error_t (*adpt_flow_host_get_func)(
+		a_uint32_t dev_id,
+		a_uint32_t get_mode,
+		fal_flow_host_entry_t *flow_host_entry);
+typedef sw_error_t (*adpt_flow_host_del_func)(
+		a_uint32_t dev_id,
+		a_uint32_t del_mode,
+		fal_flow_host_entry_t *flow_host_entry);
+typedef sw_error_t (*adpt_flow_ctrl_get_func)(
+		a_uint32_t dev_id,
+		fal_flow_pkt_type_t type,
+		fal_flow_direction_t dir,
+		fal_flow_mgmt_t *ctrl);
+typedef sw_error_t (*adpt_flow_age_timer_set_func)(
+		a_uint32_t dev_id, fal_flow_age_timer_t *age_timer);
+typedef sw_error_t (*adpt_flow_entry_add_func)(
+		a_uint32_t dev_id,
+		a_uint32_t add_mode, /*index or hash*/
+		fal_flow_entry_t *flow_entry);
+typedef sw_error_t (*adpt_ucast_hash_map_set_func)(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t rss_hash,
+		a_int8_t queue_hash);
+typedef sw_error_t (*adpt_ac_dynamic_threshold_get_func)(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		fal_ac_dynamic_threshold_t *cfg);
+typedef sw_error_t (*adpt_ucast_queue_base_profile_get_func)(
+		a_uint32_t dev_id,
+		fal_ucast_queue_dest_t *queue_dest,
+		a_uint32_t *queue_base, a_uint8_t *profile);
+typedef sw_error_t (*adpt_port_mcast_priority_class_get_func)(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint8_t priority,
+		a_uint8_t *queue_class);
+typedef sw_error_t (*adpt_ac_dynamic_threshold_set_func)(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		fal_ac_dynamic_threshold_t *cfg);
+typedef sw_error_t (*adpt_ac_prealloc_buffer_set_func)(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		a_uint16_t num);
+typedef sw_error_t (*adpt_ucast_default_hash_get_func)(
+		a_uint32_t dev_id,
+		a_uint8_t *hash_value);
+typedef sw_error_t (*adpt_ucast_default_hash_set_func)(
+		a_uint32_t dev_id,
+		a_uint8_t hash_value);
+typedef sw_error_t (*adpt_ac_queue_group_get_func)(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_uint8_t *group_id);
+typedef sw_error_t (*adpt_ac_ctrl_get_func)(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_ctrl_t *cfg);
+typedef sw_error_t (*adpt_ac_prealloc_buffer_get_func)(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		a_uint16_t *num);
+typedef sw_error_t (*adpt_port_mcast_priority_class_set_func)(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint8_t priority,
+		a_uint8_t queue_class);
+typedef sw_error_t (*adpt_ucast_hash_map_get_func)(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t rss_hash,
+		a_int8_t *queue_hash);
+typedef sw_error_t (*adpt_ac_static_threshold_set_func)(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_static_threshold_t *cfg);
+typedef sw_error_t (*adpt_ac_queue_group_set_func)(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_uint8_t group_id);
+typedef sw_error_t (*adpt_ac_group_buffer_get_func)(
+		a_uint32_t dev_id,
+		a_uint8_t group_id,
+		fal_ac_group_buffer_t *cfg);
+typedef sw_error_t (*adpt_mcast_cpu_code_class_get_func)(
+		a_uint32_t dev_id,
+		a_uint8_t cpu_code,
+		a_uint8_t *queue_class);
+typedef sw_error_t (*adpt_ac_ctrl_set_func)(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_ctrl_t *cfg);
+typedef sw_error_t (*adpt_ucast_priority_class_get_func)(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t priority,
+		a_uint8_t *class);
+typedef sw_error_t (*adpt_queue_flush_func)(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint16_t queue_id);
+typedef sw_error_t (*adpt_mcast_cpu_code_class_set_func)(
+		a_uint32_t dev_id,
+		a_uint8_t cpu_code,
+		a_uint8_t queue_class);
+typedef sw_error_t (*adpt_ucast_priority_class_set_func)(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t priority,
+		a_uint8_t class);
+typedef sw_error_t (*adpt_ac_static_threshold_get_func)(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_static_threshold_t *cfg);
+typedef sw_error_t (*adpt_ucast_queue_base_profile_set_func)(
+		a_uint32_t dev_id,
+		fal_ucast_queue_dest_t *queue_dest,
+		a_uint32_t queue_base, a_uint8_t profile);
+typedef sw_error_t (*adpt_ac_group_buffer_set_func)(
+		a_uint32_t dev_id,
+		a_uint8_t group_id,
+		fal_ac_group_buffer_t *cfg);
+typedef sw_error_t (*adpt_queue_counter_cleanup_func)(
+		a_uint32_t dev_id, a_uint32_t queue_id);
+typedef sw_error_t (*adpt_queue_counter_get_func)(
+		a_uint32_t dev_id, a_uint32_t queue_id,
+		fal_queue_stats_t *info);
+typedef sw_error_t (*adpt_queue_counter_ctrl_get_func)(
+		a_uint32_t dev_id, a_bool_t *cnt_en);
+typedef sw_error_t (*adpt_queue_counter_ctrl_set_func)(
+		a_uint32_t dev_id, a_bool_t cnt_en);
+typedef sw_error_t (*adpt_qm_enqueue_ctrl_set_func)(
+		a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t enable);
+typedef sw_error_t (*adpt_qm_enqueue_ctrl_get_func)(
+		a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t *enable);
+typedef sw_error_t (*adpt_qm_port_source_profile_set_func)(
+		a_uint32_t dev_id, fal_port_t port, a_uint32_t src_profile);
+typedef sw_error_t (*adpt_qm_port_source_profile_get_func)(
+		a_uint32_t dev_id, fal_port_t port, a_uint32_t *src_profile);
+
+
+/*portvlan module begin*/
+typedef sw_error_t (*adpt_global_qinq_mode_set_func)(a_uint32_t dev_id, fal_global_qinq_mode_t *mode);
+typedef sw_error_t (*adpt_global_qinq_mode_get_func)(a_uint32_t dev_id, fal_global_qinq_mode_t *mode);
+typedef sw_error_t (*adpt_tpid_set_func)(a_uint32_t dev_id, fal_tpid_t *tpid);
+typedef sw_error_t (*adpt_tpid_get_func)(a_uint32_t dev_id, fal_tpid_t *tpid);
+typedef sw_error_t (*adpt_egress_tpid_set_func)(a_uint32_t dev_id, fal_tpid_t *tpid);
+typedef sw_error_t (*adpt_egress_tpid_get_func)(a_uint32_t dev_id, fal_tpid_t *tpid);
+typedef sw_error_t (*adpt_port_qinq_mode_set_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode);
+typedef sw_error_t (*adpt_port_qinq_mode_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode);
+typedef sw_error_t (*adpt_port_ingress_vlan_filter_set_func)(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t *filter);
+typedef sw_error_t (*adpt_port_ingress_vlan_filter_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t *filter);
+typedef sw_error_t (*adpt_port_default_vlantag_set_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag);
+typedef sw_error_t (*adpt_port_default_vlantag_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag);
+typedef sw_error_t (*adpt_port_tag_propagation_set_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlantag_propagation_t *prop);
+typedef sw_error_t (*adpt_port_tag_propagation_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlantag_propagation_t *prop);
+typedef sw_error_t (*adpt_port_vlantag_egmode_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_vlantag_egress_mode_t *port_egvlanmode);
+typedef sw_error_t (*adpt_port_vlantag_egmode_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_vlantag_egress_mode_t *port_egvlanmode);
+typedef sw_error_t (*adpt_port_vlan_xlt_miss_cmd_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_fwd_cmd_t *cmd);
+typedef sw_error_t (*adpt_port_vlan_xlt_miss_cmd_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_fwd_cmd_t cmd);
+typedef sw_error_t (*adpt_port_vlan_trans_add_func)(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+typedef sw_error_t (*adpt_port_vlan_trans_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+typedef sw_error_t (*adpt_port_vlan_trans_del_func)(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+typedef sw_error_t (*adpt_port_vlan_trans_iterate_func)(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * iterator, fal_vlan_trans_entry_t *entry);
+typedef sw_error_t (*adpt_port_vsi_egmode_set_func)(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t egmode);
+typedef sw_error_t (*adpt_port_vsi_egmode_get_func)(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t * egmode);
+typedef sw_error_t (*adpt_port_vlantag_vsi_egmode_enable_set_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+typedef sw_error_t (*adpt_port_vlantag_vsi_egmode_enable_get_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+typedef sw_error_t (*adpt_qinq_mode_set_func)(a_uint32_t dev_id, fal_qinq_mode_t mode);
+typedef sw_error_t (*adpt_qinq_mode_get_func)(a_uint32_t dev_id, fal_qinq_mode_t * mode);
+typedef sw_error_t (*adpt_port_qinq_role_set_func)(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role);
+typedef sw_error_t (*adpt_port_qinq_role_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role);
+typedef sw_error_t (*adpt_port_invlan_mode_set_func)(a_uint32_t dev_id, fal_port_t port_id, fal_pt_invlan_mode_t mode);
+typedef sw_error_t (*adpt_port_invlan_mode_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_pt_invlan_mode_t * mode);
+typedef sw_error_t (*adpt_port_vlan_trans_adv_add_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action);
+typedef sw_error_t (*adpt_port_vlan_trans_adv_del_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action);
+typedef sw_error_t (*adpt_port_vlan_trans_adv_getfirst_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action);
+typedef sw_error_t (*adpt_port_vlan_trans_adv_getnext_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action);
+typedef sw_error_t (*adpt_port_vlan_counter_get_func)(a_uint32_t dev_id, a_uint32_t cnt_index, fal_port_vlan_counter_t * counter);
+typedef sw_error_t (*adpt_port_vlan_counter_cleanup_func)(a_uint32_t dev_id, a_uint32_t cnt_index);
+typedef sw_error_t (*adpt_portvlan_member_add_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_t mem_port_id);
+typedef sw_error_t (*adpt_portvlan_member_del_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_t mem_port_id);
+typedef sw_error_t (*adpt_portvlan_member_update_func)(a_uint32_t dev_id, fal_port_t port_id, fal_pbmp_t mem_port_map);
+typedef sw_error_t (*adpt_portvlan_member_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_pbmp_t * mem_port_map);
+/*portvlan module end*/
+
+/*ctrlpkt module end*/
+typedef sw_error_t (*adpt_mgmtctrl_ethtype_profile_set_func)(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t ethtype);
+typedef sw_error_t (*adpt_mgmtctrl_ethtype_profile_get_func)(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t * ethtype);
+typedef sw_error_t (*adpt_mgmtctrl_rfdb_profile_set_func)(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr);
+typedef sw_error_t (*adpt_mgmtctrl_rfdb_profile_get_func)(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr);
+typedef sw_error_t (*adpt_mgmtctrl_ctrlpkt_profile_add_func)(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt);
+typedef sw_error_t (*adpt_mgmtctrl_ctrlpkt_profile_del_func)(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt);
+typedef sw_error_t (*adpt_mgmtctrl_ctrlpkt_profile_getfirst_func)(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt);
+typedef sw_error_t (*adpt_mgmtctrl_ctrlpkt_profile_getnext_func)(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt);
+/*ctrlpkt module end*/
+
+/*service module end*/
+typedef sw_error_t (*adpt_servcode_config_set_func)(a_uint32_t dev_id,
+		a_uint32_t servcode_index, fal_servcode_config_t *entry);
+typedef sw_error_t (*adpt_servcode_config_get_func)(a_uint32_t dev_id,
+		a_uint32_t servcode_index, fal_servcode_config_t *entry);
+typedef sw_error_t (*adpt_servcode_loopcheck_en_func)(a_uint32_t dev_id, a_bool_t enable);
+typedef sw_error_t (*adpt_servcode_loopcheck_status_get_func)(a_uint32_t dev_id, a_bool_t *enable);
+/*service module end*/
+
+//pppoe
+typedef sw_error_t (*adpt_pppoe_session_table_add_func)(
+		a_uint32_t dev_id,
+		fal_pppoe_session_t * session_tbl);
+typedef sw_error_t (*adpt_pppoe_session_table_del_func)(
+		a_uint32_t dev_id,
+		fal_pppoe_session_t * session_tbl);
+typedef sw_error_t (*adpt_pppoe_session_table_get_func)(
+		a_uint32_t dev_id,
+		fal_pppoe_session_t * session_tbl);
+typedef sw_error_t (*adpt_pppoe_en_set_func)(
+		a_uint32_t dev_id,
+		a_uint32_t l3_if,
+		a_uint32_t enable);
+typedef sw_error_t (*adpt_pppoe_en_get_func)(
+		a_uint32_t dev_id,
+		a_uint32_t l3_if,
+		a_uint32_t *enable);
+
+typedef sw_error_t (*adpt_sec_l3_excep_parser_ctrl_set_func)(
+		a_uint32_t dev_id,
+		fal_l3_excep_parser_ctrl *ctrl);
+typedef sw_error_t (*adpt_sec_l3_excep_ctrl_get_func)(
+		a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl);
+typedef sw_error_t (*adpt_sec_l3_excep_parser_ctrl_get_func)(
+		a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl);
+typedef sw_error_t (*adpt_sec_l4_excep_parser_ctrl_set_func)(
+		a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl);
+typedef sw_error_t (*adpt_sec_l3_excep_ctrl_set_func)(
+		a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl);
+typedef sw_error_t (*adpt_sec_l4_excep_parser_ctrl_get_func)(
+		a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl);
+
+typedef sw_error_t (*adpt_acl_list_bind_func)(a_uint32_t dev_id, a_uint32_t list_id, fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx);
+typedef sw_error_t (*adpt_acl_list_dump_func)(a_uint32_t dev_id);
+typedef sw_error_t (*adpt_acl_udf_profile_set_func)(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t udf_type, a_uint32_t offset);
+typedef sw_error_t (*adpt_acl_rule_query_func)(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, fal_acl_rule_t * rule);
+typedef sw_error_t (*adpt_acl_list_unbind_func)(a_uint32_t dev_id, a_uint32_t list_id, fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx);
+typedef sw_error_t (*adpt_acl_rule_add_func)(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule);
+typedef sw_error_t (*adpt_acl_rule_delete_func)(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr);
+typedef sw_error_t (*adpt_acl_rule_dump_func)(a_uint32_t dev_id);
+typedef sw_error_t (*adpt_acl_udf_profile_get_func)(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t *udf_type, a_uint32_t *offset);
+typedef sw_error_t (*adpt_acl_list_creat_func)(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri);
+typedef sw_error_t (*adpt_acl_list_destroy_func)(a_uint32_t dev_id, a_uint32_t list_id);
+
+typedef sw_error_t (*adpt_qos_port_pri_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_pri_precedence_t *pri);
+typedef sw_error_t (*adpt_qos_port_pri_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_pri_precedence_t *pri);
+typedef sw_error_t (*adpt_qos_cosmap_pcp_get_func)(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t pcp, fal_qos_cosmap_t *cosmap);
+typedef sw_error_t (*adpt_queue_scheduler_set_func)(a_uint32_t dev_id,
+					a_uint32_t node_id,
+					fal_queue_scheduler_level_t level,
+					fal_port_t port_id,
+					fal_qos_scheduler_cfg_t *scheduler_cfg);
+typedef sw_error_t (*adpt_queue_scheduler_get_func)(a_uint32_t dev_id,
+					a_uint32_t node_id,
+					fal_queue_scheduler_level_t level,
+					fal_port_t *port_id,
+					fal_qos_scheduler_cfg_t *scheduler_cfg);
+typedef sw_error_t (*adpt_port_queues_get_func)(a_uint32_t dev_id,
+					fal_port_t port_id,
+					fal_queue_bmp_t *queue_bmp);
+typedef sw_error_t (*adpt_qos_cosmap_pcp_set_func)(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t pcp, fal_qos_cosmap_t *cosmap);
+typedef sw_error_t (*adpt_qos_port_remark_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_remark_enable_t *remark);
+typedef sw_error_t (*adpt_qos_cosmap_dscp_get_func)(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t dscp, fal_qos_cosmap_t *cosmap);
+typedef sw_error_t (*adpt_qos_cosmap_flow_set_func)(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint16_t flow, fal_qos_cosmap_t *cosmap);
+typedef sw_error_t (*adpt_qos_port_group_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_group_t *group);
+typedef sw_error_t (*adpt_ring_queue_map_set_func)(a_uint32_t dev_id,
+					a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp);
+typedef sw_error_t (*adpt_qos_cosmap_dscp_set_func)(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t dscp, fal_qos_cosmap_t *cosmap);
+typedef sw_error_t (*adpt_qos_port_remark_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_remark_enable_t *remark);
+typedef sw_error_t (*adpt_qos_cosmap_flow_get_func)(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint16_t flow, fal_qos_cosmap_t *cosmap);
+typedef sw_error_t (*adpt_qos_port_group_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_group_t *group);
+typedef sw_error_t (*adpt_ring_queue_map_get_func)(a_uint32_t dev_id,
+					a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp);
+
+//shaper
+
+typedef sw_error_t (*adpt_flow_shaper_set_func)(a_uint32_t dev_id, a_uint32_t flow_id,
+					fal_shaper_config_t * shaper);
+typedef sw_error_t (*adpt_queue_shaper_get_func)(a_uint32_t dev_id, a_uint32_t queue_id,
+					fal_shaper_config_t * shaper);
+typedef sw_error_t (*adpt_queue_shaper_token_number_set_func)(a_uint32_t dev_id,a_uint32_t queue_id,
+					fal_shaper_token_number_t *token_number);
+typedef sw_error_t (*adpt_port_shaper_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					fal_shaper_config_t * shaper);
+typedef sw_error_t (*adpt_flow_shaper_time_slot_get_func)(a_uint32_t dev_id, a_uint32_t *time_slot);
+typedef sw_error_t (*adpt_port_shaper_time_slot_get_func)(a_uint32_t dev_id, a_uint32_t *time_slot);
+typedef sw_error_t (*adpt_flow_shaper_time_slot_set_func)(a_uint32_t dev_id, a_uint32_t time_slot);
+typedef sw_error_t (*adpt_port_shaper_token_number_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+					fal_shaper_token_number_t *token_number);
+typedef sw_error_t (*adpt_queue_shaper_token_number_get_func)(a_uint32_t dev_id, a_uint32_t queue_id,
+					fal_shaper_token_number_t *token_number);
+typedef sw_error_t (*adpt_queue_shaper_time_slot_get_func)(a_uint32_t dev_id, a_uint32_t *time_slot);
+typedef sw_error_t (*adpt_port_shaper_token_number_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					fal_shaper_token_number_t *token_number);
+typedef sw_error_t (*adpt_flow_shaper_token_number_set_func)(a_uint32_t dev_id, a_uint32_t flow_id,
+					fal_shaper_token_number_t *token_number);
+typedef sw_error_t (*adpt_flow_shaper_token_number_get_func)(a_uint32_t dev_id, a_uint32_t flow_id,
+					fal_shaper_token_number_t *token_number);
+typedef sw_error_t (*adpt_port_shaper_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+					fal_shaper_config_t * shaper);
+typedef sw_error_t (*adpt_port_shaper_time_slot_set_func)(a_uint32_t dev_id, a_uint32_t time_slot);
+typedef sw_error_t (*adpt_flow_shaper_get_func)(a_uint32_t dev_id, a_uint32_t flow_id,
+					fal_shaper_config_t * shaper);
+typedef sw_error_t (*adpt_queue_shaper_set_func)(a_uint32_t dev_id,a_uint32_t queue_id,
+					fal_shaper_config_t * shaper);
+typedef sw_error_t (*adpt_queue_shaper_time_slot_set_func)(a_uint32_t dev_id, a_uint32_t time_slot);
+typedef sw_error_t (*adpt_shaper_ipg_preamble_length_get_func)(a_uint32_t dev_id, a_uint32_t *ipg_pre_length);
+typedef sw_error_t (*adpt_shaper_ipg_preamble_length_set_func)(a_uint32_t dev_id, a_uint32_t ipg_pre_length);
+
+typedef sw_error_t (*adpt_tdm_tick_num_set_func)(a_uint32_t dev_id, a_uint32_t tick_num);
+typedef sw_error_t (*adpt_tdm_tick_num_get_func)(a_uint32_t dev_id, a_uint32_t *tick_num);
+typedef sw_error_t (*adpt_port_scheduler_cfg_set_func)(a_uint32_t dev_id, a_uint32_t tick_index,
+					fal_port_scheduler_cfg_t *cfg);
+typedef sw_error_t (*adpt_port_scheduler_cfg_reset_func)(a_uint32_t dev_id, fal_port_t port_id);
+typedef sw_error_t (*adpt_port_scheduler_cfg_get_func)(a_uint32_t dev_id, a_uint32_t tick_index,
+					fal_port_scheduler_cfg_t *cfg);
+typedef sw_error_t (*adpt_scheduler_dequeue_ctrl_get_func)(a_uint32_t dev_id, a_uint32_t queue_id,
+					a_bool_t *enable);
+typedef sw_error_t (*adpt_scheduler_dequeue_ctrl_set_func)(a_uint32_t dev_id, a_uint32_t queue_id,
+					a_bool_t enable);
+typedef sw_error_t (*adpt_qos_port_mode_pri_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_mode_t mode, a_uint32_t *pri);
+typedef sw_error_t (*adpt_qos_port_mode_pri_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_mode_t mode, a_uint32_t pri);
+typedef sw_error_t (*adpt_port_scheduler_resource_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+					fal_portscheduler_resource_t *cfg);
+typedef sw_error_t (*adpt_port_bufgroup_map_get_func)(a_uint32_t dev_id, fal_port_t port,
+			a_uint8_t *group);
+typedef sw_error_t (*adpt_bm_port_reserved_buffer_get_func)(a_uint32_t dev_id, fal_port_t port,
+			a_uint16_t *prealloc_buff, a_uint16_t *react_buff);
+typedef sw_error_t (*adpt_bm_bufgroup_buffer_get_func)(a_uint32_t dev_id, a_uint8_t group,
+			a_uint16_t *buff_num);
+typedef sw_error_t (*adpt_bm_port_dynamic_thresh_get_func)(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_dynamic_cfg_t *cfg);
+typedef sw_error_t (*adpt_port_bm_ctrl_get_func)(a_uint32_t dev_id, fal_port_t port, a_bool_t *enable);
+typedef sw_error_t (*adpt_bm_bufgroup_buffer_set_func)(a_uint32_t dev_id, a_uint8_t group,
+			a_uint16_t buff_num);
+typedef sw_error_t (*adpt_port_bufgroup_map_set_func)(a_uint32_t dev_id, fal_port_t port,
+			a_uint8_t group);
+typedef sw_error_t (*adpt_bm_port_static_thresh_get_func)(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_static_cfg_t *cfg);
+typedef sw_error_t (*adpt_bm_port_reserved_buffer_set_func)(a_uint32_t dev_id, fal_port_t port,
+			a_uint16_t prealloc_buff, a_uint16_t react_buff);
+typedef sw_error_t (*adpt_bm_port_static_thresh_set_func)(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_static_cfg_t *cfg);
+typedef sw_error_t (*adpt_bm_port_dynamic_thresh_set_func)(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_dynamic_cfg_t *cfg);
+typedef sw_error_t (*adpt_port_bm_ctrl_set_func)(a_uint32_t dev_id, fal_port_t port, a_bool_t enable);
+typedef sw_error_t (*adpt_port_tdm_ctrl_set_func)(a_uint32_t dev_id, fal_port_tdm_ctrl_t *ctrl);
+typedef sw_error_t (*adpt_port_tdm_tick_cfg_set_func)(a_uint32_t dev_id, a_uint32_t tick_index,
+			fal_port_tdm_tick_cfg_t *cfg);
+typedef sw_error_t (*adpt_bm_port_counter_get_func)(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_port_counter_t *counter);
+
+//policer
+typedef sw_error_t (*adpt_acl_policer_counter_get_func)(a_uint32_t dev_id, a_uint32_t index,
+		fal_policer_counter_t *counter);
+typedef sw_error_t (*adpt_port_policer_counter_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+		fal_policer_counter_t *counter);
+typedef sw_error_t (*adpt_port_compensation_byte_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t  *length);
+typedef sw_error_t (*adpt_port_policer_entry_get_func)(a_uint32_t dev_id, fal_port_t port_id,
+		fal_policer_config_t *policer, fal_policer_action_t *ation);
+typedef sw_error_t (*adpt_port_policer_entry_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+		fal_policer_config_t *policer, fal_policer_action_t *ation);
+typedef sw_error_t (*adpt_acl_policer_entry_get_func)(a_uint32_t dev_id, a_uint32_t index,
+		fal_policer_config_t *policer, fal_policer_action_t *ation);
+typedef sw_error_t (*adpt_acl_policer_entry_set_func)(a_uint32_t dev_id, a_uint32_t index,
+		fal_policer_config_t *policer, fal_policer_action_t *ation);
+typedef sw_error_t (*adpt_policer_time_slot_get_func)(a_uint32_t dev_id, a_uint32_t *time_slot);
+typedef sw_error_t (*adpt_port_compensation_byte_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t  length);
+typedef sw_error_t (*adpt_policer_time_slot_set_func)(a_uint32_t dev_id, a_uint32_t time_slot);
+
+typedef sw_error_t (*adpt_policer_global_counter_get_func)(a_uint32_t dev_id,
+		fal_policer_global_counter_t *counter);
+typedef sw_error_t (*adpt_policer_bypass_en_set_func)(a_uint32_t dev_id,
+	fal_policer_frame_type_t frame_type, a_bool_t enable);
+typedef sw_error_t (*adpt_policer_bypass_en_get_func)(a_uint32_t dev_id,
+	fal_policer_frame_type_t frame_type, a_bool_t *enable);
+
+/* misc */
+typedef sw_error_t (*adpt_debug_port_counter_enable_func)(a_uint32_t dev_id,
+			fal_port_t port_id, fal_counter_en_t * cnt_en);
+typedef sw_error_t (*adpt_debug_port_counter_status_get_func)(a_uint32_t dev_id,
+			fal_port_t port_id, fal_counter_en_t * cnt_en);
+typedef sw_error_t (*adpt_debug_counter_get_func)(a_bool_t show_type);
+typedef sw_error_t (*adpt_debug_counter_set_func)(void);
+typedef sw_error_t (*adpt_intr_port_link_mask_set_func) (a_uint32_t dev_id,
+			fal_port_t port_id, a_uint32_t intr_mask);
+typedef sw_error_t (*adpt_intr_port_link_mask_get_func) (a_uint32_t dev_id,
+			fal_port_t port_id, a_uint32_t * intr_mask);
+typedef sw_error_t (*adpt_intr_port_link_status_get_func)(a_uint32_t dev_id,
+			fal_port_t port_id, a_uint32_t * intr_status);
+
+/* uniphy */
+typedef sw_error_t (*adpt_uniphy_mode_set_func)(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode);
+
+/* ptp */
+typedef sw_error_t (*adpt_ptp_config_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_config_t *config);
+typedef sw_error_t (*adpt_ptp_config_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_config_t *config);
+typedef sw_error_t (*adpt_ptp_reference_clock_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_reference_clock_t ref_clock);
+typedef sw_error_t (*adpt_ptp_reference_clock_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_reference_clock_t *ref_clock);
+typedef sw_error_t (*adpt_ptp_rx_timestamp_mode_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_rx_timestamp_mode_t ts_mode);
+typedef sw_error_t (*adpt_ptp_rx_timestamp_mode_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_rx_timestamp_mode_t *ts_mode);
+typedef sw_error_t (*adpt_ptp_timestamp_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_direction_t direction,
+		fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time);
+typedef sw_error_t (*adpt_ptp_pkt_timestamp_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_time_t *time);
+typedef sw_error_t (*adpt_ptp_pkt_timestamp_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_time_t *time);
+typedef sw_error_t (*adpt_ptp_grandmaster_mode_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_grandmaster_mode_t *gm_mode);
+typedef sw_error_t (*adpt_ptp_grandmaster_mode_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_grandmaster_mode_t *gm_mode);
+typedef sw_error_t (*adpt_ptp_rtc_time_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_time_t *time);
+typedef sw_error_t (*adpt_ptp_rtc_time_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_time_t *time);
+typedef sw_error_t (*adpt_ptp_rtc_time_clear_func)(a_uint32_t dev_id,
+		a_uint32_t port_id);
+typedef sw_error_t (*adpt_ptp_rtc_adjtime_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_time_t *time);
+typedef sw_error_t (*adpt_ptp_rtc_adjfreq_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_time_t *time);
+typedef sw_error_t (*adpt_ptp_rtc_adjfreq_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_time_t *time);
+typedef sw_error_t (*adpt_ptp_link_delay_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_time_t *time);
+typedef sw_error_t (*adpt_ptp_link_delay_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_time_t *time);
+typedef sw_error_t (*adpt_ptp_security_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_security_t *sec);
+typedef sw_error_t (*adpt_ptp_security_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_security_t *sec);
+typedef sw_error_t (*adpt_ptp_pps_signal_control_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_pps_signal_control_t *sig_control);
+typedef sw_error_t (*adpt_ptp_pps_signal_control_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_pps_signal_control_t *sig_control);
+typedef sw_error_t (*adpt_ptp_rx_crc_recalc_enable_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t status);
+typedef sw_error_t (*adpt_ptp_rx_crc_recalc_status_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t *status);
+typedef sw_error_t (*adpt_ptp_asym_correction_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_asym_correction_t *asym_cf);
+typedef sw_error_t (*adpt_ptp_asym_correction_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_asym_correction_t *asym_cf);
+typedef sw_error_t (*adpt_ptp_output_waveform_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_output_waveform_t *waveform);
+typedef sw_error_t (*adpt_ptp_output_waveform_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_output_waveform_t *waveform);
+typedef sw_error_t (*adpt_ptp_rtc_time_snapshot_enable_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t status);
+typedef sw_error_t (*adpt_ptp_rtc_time_snapshot_status_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t *status);
+typedef sw_error_t (*adpt_ptp_increment_sync_from_clock_enable_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t status);
+typedef sw_error_t (*adpt_ptp_increment_sync_from_clock_status_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t *status);
+typedef sw_error_t (*adpt_ptp_tod_uart_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_tod_uart_t *tod_uart);
+typedef sw_error_t (*adpt_ptp_tod_uart_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_tod_uart_t *tod_uart);
+typedef sw_error_t (*adpt_ptp_enhanced_timestamp_engine_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_direction_t direction,
+		fal_ptp_enhanced_ts_engine_t *ts_engine);
+typedef sw_error_t (*adpt_ptp_enhanced_timestamp_engine_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_direction_t direction,
+		fal_ptp_enhanced_ts_engine_t *ts_engine);
+typedef sw_error_t (*adpt_ptp_trigger_set_func)(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t trigger_id, fal_ptp_trigger_t *triger);
+typedef sw_error_t (*adpt_ptp_trigger_get_func)(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t trigger_id, fal_ptp_trigger_t *triger);
+typedef sw_error_t (*adpt_ptp_capture_set_func)(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t capture_id, fal_ptp_capture_t *capture);
+typedef sw_error_t (*adpt_ptp_capture_get_func)(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t capture_id, fal_ptp_capture_t *capture);
+typedef sw_error_t (*adpt_ptp_interrupt_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_interrupt_t *interrupt);
+typedef sw_error_t (*adpt_ptp_interrupt_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_interrupt_t *interrupt);
+
+/* sfp */
+typedef sw_error_t (*adpt_sfp_eeprom_data_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_data_t *entry);
+typedef sw_error_t (*adpt_sfp_eeprom_data_set_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_data_t *entry);
+typedef sw_error_t (*adpt_sfp_diag_ctrl_status_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_ctrl_status_t *ctrl_status);
+typedef sw_error_t (*adpt_sfp_diag_extenal_calibration_const_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_cal_const_t *cal_const);
+typedef sw_error_t (*adpt_sfp_link_length_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_link_length_t *link_len);
+typedef sw_error_t (*adpt_sfp_diag_internal_threshold_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_internal_threshold_t *threshold);
+typedef sw_error_t (*adpt_sfp_diag_realtime_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_realtime_diag_t *real_diag);
+typedef sw_error_t (*adpt_sfp_laser_wavelength_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_laser_wavelength_t *laser_wavelen);
+typedef sw_error_t (*adpt_sfp_option_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_option_t *option);
+typedef sw_error_t (*adpt_sfp_checkcode_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_cc_type_t cc_type, a_uint8_t *ccode);
+typedef sw_error_t (*adpt_sfp_diag_alarm_warning_flag_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_alarm_warn_flag_t *alarm_warn_flag);
+typedef sw_error_t (*adpt_sfp_device_type_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_dev_type_t *sfp_id);
+typedef sw_error_t (*adpt_sfp_vendor_info_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_vendor_info_t *vender_info);
+typedef sw_error_t (*adpt_sfp_transceiver_code_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_transc_code_t *transc_code);
+typedef sw_error_t (*adpt_sfp_ctrl_rate_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_rate_t *rate_limit);
+typedef sw_error_t (*adpt_sfp_enhanced_cfg_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_enhanced_cfg_t *enhanced_feature);
+typedef sw_error_t (*adpt_sfp_rate_encode_get_func)(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_sfp_rate_encode_t *encode);
+
+/*led*/
+typedef sw_error_t (*adpt_led_ctrl_pattern_set_func)(a_uint32_t dev_id,
+	led_pattern_group_t group, led_pattern_id_t led_pattern_id,
+	led_ctrl_pattern_t * pattern);
+typedef sw_error_t (*adpt_led_ctrl_pattern_get_func)(a_uint32_t dev_id,
+	led_pattern_group_t group, led_pattern_id_t led_pattern_id,
+	led_ctrl_pattern_t * pattern);
+typedef sw_error_t (*adpt_led_ctrl_source_set_func)(a_uint32_t dev_id,
+	a_uint32_t source_id, led_ctrl_pattern_t *pattern);
+
+typedef struct
+{
+	ssdk_chip_type chip_type;
+	a_uint32_t chip_revision;
+}adpt_chip_ver_t;
+typedef struct
+{
+	a_uint32_t adpt_fdb_func_bitmap[2];
+	adpt_fdb_first_func adpt_fdb_first;
+	adpt_fdb_next_func adpt_fdb_next;
+	adpt_fdb_add_func adpt_fdb_add;
+	adpt_fdb_age_time_set_func adpt_fdb_age_time_set;
+	adpt_fdb_extend_next_func adpt_fdb_extend_next;
+	adpt_fdb_learn_ctrl_get_func adpt_fdb_learn_ctrl_get;
+	adpt_fdb_age_time_get_func adpt_fdb_age_time_get;
+	adpt_port_fdb_learn_limit_set_func adpt_port_fdb_learn_limit_set;
+	adpt_fdb_port_add_func adpt_fdb_port_add;
+	adpt_fdb_port_learn_set_func adpt_fdb_port_learn_set;
+	adpt_fdb_port_learn_get_func adpt_fdb_port_learn_get;
+	adpt_fdb_port_newaddr_lrn_set_func adpt_fdb_port_newaddr_lrn_set;
+	adpt_fdb_port_newaddr_lrn_get_func adpt_fdb_port_newaddr_lrn_get;
+	adpt_fdb_port_stamove_set_func adpt_fdb_port_stamove_set;
+	adpt_fdb_port_stamove_get_func adpt_fdb_port_stamove_get;
+	adpt_port_fdb_learn_counter_get_func adpt_port_fdb_learn_counter_get;
+	adpt_fdb_extend_first_func adpt_fdb_extend_first;
+	adpt_fdb_transfer_func adpt_fdb_transfer;
+	adpt_fdb_port_del_func adpt_fdb_port_del;
+	adpt_fdb_find_func adpt_fdb_find;
+	adpt_fdb_learn_ctrl_set_func adpt_fdb_learn_ctrl_set;
+	adpt_port_fdb_learn_exceed_cmd_get_func adpt_port_fdb_learn_exceed_cmd_get;
+	adpt_fdb_del_by_port_func adpt_fdb_del_by_port;
+	adpt_port_fdb_learn_limit_get_func adpt_port_fdb_learn_limit_get;
+	adpt_fdb_age_ctrl_set_func adpt_fdb_age_ctrl_set;
+	adpt_fdb_del_by_mac_func adpt_fdb_del_by_mac;
+	adpt_fdb_iterate_func adpt_fdb_iterate;
+	adpt_port_fdb_learn_exceed_cmd_set_func adpt_port_fdb_learn_exceed_cmd_set;
+	adpt_fdb_del_all_func adpt_fdb_del_all;
+	adpt_fdb_age_ctrl_get_func adpt_fdb_age_ctrl_get;
+	adpt_fdb_port_maclimit_ctrl_set_func adpt_fdb_port_maclimit_ctrl_set;
+	adpt_fdb_port_maclimit_ctrl_get_func adpt_fdb_port_maclimit_ctrl_get;
+	adpt_fdb_del_by_fid_func adpt_fdb_del_by_fid;
+	/*mib*/
+	a_uint32_t adpt_mib_func_bitmap;
+	adpt_mib_cpukeep_get_func adpt_mib_cpukeep_get;
+	adpt_mib_cpukeep_set_func adpt_mib_cpukeep_set;
+	adpt_get_mib_info_func adpt_get_mib_info;
+	adpt_get_tx_mib_info_func adpt_get_tx_mib_info;
+	adpt_mib_status_set_func adpt_mib_status_set;
+	adpt_mib_port_flush_counters_func adpt_mib_port_flush_counters;
+	adpt_mib_status_get_func adpt_mib_status_get;
+	adpt_get_rx_mib_info_func adpt_get_rx_mib_info;
+	adpt_get_xgmib_info_func adpt_get_xgmib_info;
+	adpt_get_tx_xgmib_info_func adpt_get_tx_xgmib_info;
+	adpt_get_rx_xgmib_info_func adpt_get_rx_xgmib_info;
+
+	a_uint32_t adpt_stp_func_bitmap;
+	adpt_stp_port_state_get_func adpt_stp_port_state_get;
+	adpt_stp_port_state_set_func adpt_stp_port_state_set;
+
+    /*vsi*/
+	a_uint32_t adpt_vsi_func_bitmap;
+	adpt_port_vlan_vsi_set_func adpt_port_vlan_vsi_set;
+	adpt_port_vlan_vsi_get_func adpt_port_vlan_vsi_get;
+	adpt_port_vsi_set_func adpt_port_vsi_set;
+	adpt_port_vsi_get_func adpt_port_vsi_get;
+	adpt_vsi_stamove_set_func adpt_vsi_stamove_set;
+	adpt_vsi_stamove_get_func adpt_vsi_stamove_get;
+	adpt_vsi_newaddr_lrn_set_func adpt_vsi_newaddr_lrn_set;
+	adpt_vsi_newaddr_lrn_get_func adpt_vsi_newaddr_lrn_get;
+	adpt_vsi_member_set_func adpt_vsi_member_set;
+	adpt_vsi_member_get_func adpt_vsi_member_get;
+	adpt_vsi_counter_get_func adpt_vsi_counter_get;
+	adpt_vsi_counter_cleanup_func adpt_vsi_counter_cleanup;
+
+	// port_ctrl
+	a_uint32_t adpt_port_ctrl_func_bitmap[3];
+	adpt_port_local_loopback_get_func adpt_port_local_loopback_get;
+	adpt_port_autoneg_restart_func adpt_port_autoneg_restart;
+	adpt_port_duplex_set_func adpt_port_duplex_set;
+	adpt_port_rxmac_status_get_func adpt_port_rxmac_status_get;
+	adpt_port_cdt_func adpt_port_cdt;
+	adpt_port_txmac_status_set_func adpt_port_txmac_status_set;
+	adpt_port_combo_fiber_mode_set_func adpt_port_combo_fiber_mode_set;
+	adpt_port_combo_medium_status_get_func adpt_port_combo_medium_status_get;
+	adpt_port_magic_frame_mac_set_func adpt_port_magic_frame_mac_set;
+	adpt_port_powersave_set_func adpt_port_powersave_set;
+	adpt_port_hibernate_set_func adpt_port_hibernate_set;
+	adpt_port_max_frame_size_get_func adpt_port_max_frame_size_get;
+	adpt_port_8023az_get_func adpt_port_8023az_get;
+	adpt_port_rxfc_status_get_func adpt_port_rxfc_status_get;
+	adpt_port_txfc_status_get_func adpt_port_txfc_status_get;
+	adpt_port_remote_loopback_set_func adpt_port_remote_loopback_set;
+	adpt_port_flowctrl_set_func adpt_port_flowctrl_set;
+	adpt_port_mru_set_func adpt_port_mru_set;
+	adpt_port_autoneg_status_get_func adpt_port_autoneg_status_get;
+	adpt_port_txmac_status_get_func adpt_port_txmac_status_get;
+	adpt_port_mdix_get_func adpt_port_mdix_get;
+	adpt_ports_link_status_get_func adpt_ports_link_status_get;
+	adpt_port_mac_loopback_set_func adpt_port_mac_loopback_set;
+	adpt_port_phy_id_get_func adpt_port_phy_id_get;
+	adpt_port_mru_get_func adpt_port_mru_get;
+	adpt_port_power_on_func adpt_port_power_on;
+	adpt_port_speed_set_func adpt_port_speed_set;
+	adpt_port_interface_mode_get_func adpt_port_interface_mode_get;
+	adpt_port_duplex_get_func adpt_port_duplex_get;
+	adpt_port_autoneg_adv_get_func adpt_port_autoneg_adv_get;
+	adpt_port_mdix_status_get_func adpt_port_mdix_status_get;
+	adpt_port_mtu_set_func adpt_port_mtu_set;
+	adpt_port_link_status_get_func adpt_port_link_status_get;
+	adpt_port_8023az_set_func adpt_port_8023az_set;
+	adpt_port_powersave_get_func adpt_port_powersave_get;
+	adpt_port_combo_prefer_medium_get_func adpt_port_combo_prefer_medium_get;
+	adpt_port_max_frame_size_set_func adpt_port_max_frame_size_set;
+	adpt_port_combo_prefer_medium_set_func adpt_port_combo_prefer_medium_set;
+	adpt_port_power_off_func adpt_port_power_off;
+	adpt_port_txfc_status_set_func adpt_port_txfc_status_set;
+	adpt_port_counter_set_func adpt_port_counter_set;
+	adpt_port_combo_fiber_mode_get_func adpt_port_combo_fiber_mode_get;
+	adpt_port_local_loopback_set_func adpt_port_local_loopback_set;
+	adpt_port_wol_status_set_func adpt_port_wol_status_set;
+	adpt_port_magic_frame_mac_get_func adpt_port_magic_frame_mac_get;
+	adpt_port_flowctrl_get_func adpt_port_flowctrl_get;
+	adpt_port_rxmac_status_set_func adpt_port_rxmac_status_set;
+	adpt_port_counter_get_func adpt_port_counter_get;
+	adpt_port_interface_mode_set_func adpt_port_interface_mode_set;
+	adpt_port_mac_loopback_get_func adpt_port_mac_loopback_get;
+	adpt_port_hibernate_get_func adpt_port_hibernate_get;
+	adpt_port_autoneg_adv_set_func adpt_port_autoneg_adv_set;
+	adpt_port_remote_loopback_get_func adpt_port_remote_loopback_get;
+	adpt_port_counter_show_func adpt_port_counter_show;
+	adpt_port_autoneg_enable_func adpt_port_autoneg_enable;
+	adpt_port_mtu_get_func adpt_port_mtu_get;
+	adpt_port_interface_mode_status_get_func adpt_port_interface_mode_status_get;
+	adpt_port_reset_func adpt_port_reset;
+	adpt_port_rxfc_status_set_func adpt_port_rxfc_status_set;
+	adpt_port_speed_get_func adpt_port_speed_get;
+	adpt_port_mdix_set_func adpt_port_mdix_set;
+	adpt_port_wol_status_get_func adpt_port_wol_status_get;
+	adpt_port_source_filter_set_func adpt_port_source_filter_set;
+	adpt_port_source_filter_get_func adpt_port_source_filter_get;
+	adpt_port_mux_mac_type_set_func adpt_port_mux_mac_type_set;
+	adpt_port_mac_speed_set_func adpt_port_mac_speed_set;
+	adpt_port_mac_duplex_set_func adpt_port_mac_duplex_set;
+	adpt_port_netdev_notify_func adpt_port_netdev_notify_set;
+	adpt_port_polling_sw_sync_func adpt_port_polling_sw_sync_set;
+
+	adpt_port_bridge_txmac_set_func adpt_port_bridge_txmac_set;
+
+	adpt_port_interface_mode_apply_func adpt_port_interface_mode_apply;
+	adpt_port_interface_3az_status_set_func adpt_port_interface_3az_status_set;
+	adpt_port_interface_3az_status_get_func adpt_port_interface_3az_status_get;
+	adpt_port_flowctrl_forcemode_set_func adpt_port_flowctrl_forcemode_set;
+	adpt_port_flowctrl_forcemode_get_func adpt_port_flowctrl_forcemode_get;
+	adpt_port_promisc_mode_set_func adpt_port_promisc_mode_set;
+	adpt_port_promisc_mode_get_func adpt_port_promisc_mode_get;
+	adpt_port_interface_eee_cfg_set_func adpt_port_interface_eee_cfg_set;
+	adpt_port_interface_eee_cfg_get_func adpt_port_interface_eee_cfg_get;
+	adpt_port_source_filter_config_set_func adpt_port_source_filter_config_set;
+	adpt_port_source_filter_config_get_func adpt_port_source_filter_config_get;
+	adpt_switch_port_loopback_set_func adpt_switch_port_loopback_set;
+	adpt_switch_port_loopback_get_func adpt_switch_port_loopback_get;
+	adpt_port_phy_status_get_func adpt_port_phy_status_get;
+// mirror
+	a_uint32_t adpt_mirror_func_bitmap;
+	adpt_mirr_port_in_set_func adpt_mirr_port_in_set;
+	adpt_mirr_port_in_get_func adpt_mirr_port_in_get;
+	adpt_mirr_port_eg_set_func adpt_mirr_port_eg_set;
+	adpt_mirr_port_eg_get_func adpt_mirr_port_eg_get;
+	adpt_mirr_analysis_port_set_func adpt_mirr_analysis_port_set;
+	adpt_mirr_analysis_port_get_func adpt_mirr_analysis_port_get;
+	adpt_mirr_analysis_config_set_func adpt_mirr_analysis_config_set;
+	adpt_mirr_analysis_config_get_func adpt_mirr_analysis_config_get;
+//rss hash
+	a_uint32_t adpt_rss_hash_func_bitmap;
+	adpt_rss_hash_config_set_func adpt_rss_hash_config_set;
+	adpt_rss_hash_config_get_func adpt_rss_hash_config_get;
+//trunk
+	a_uint32_t adpt_trunk_func_bitmap;
+	adpt_trunk_fail_over_en_get_func adpt_trunk_fail_over_en_get;
+	adpt_trunk_hash_mode_get_func adpt_trunk_hash_mode_get;
+	adpt_trunk_group_get_func adpt_trunk_group_get;
+	adpt_trunk_group_set_func adpt_trunk_group_set;
+	adpt_trunk_fail_over_en_set_func adpt_trunk_fail_over_en_set;
+	adpt_trunk_hash_mode_set_func adpt_trunk_hash_mode_set;
+
+	/* ip */
+	a_uint32_t adpt_ip_func_bitmap[2];
+	adpt_ip_network_route_get_func adpt_ip_network_route_get;
+	adpt_ip_network_route_add_func adpt_ip_network_route_add;
+	adpt_ip_network_route_del_func adpt_ip_network_route_del;
+	adpt_ip_host_add_func adpt_ip_host_add;
+	adpt_ip_vsi_sg_cfg_get_func adpt_ip_vsi_sg_cfg_get;
+	adpt_ip_pub_addr_set_func adpt_ip_pub_addr_set;
+	adpt_ip_pub_addr_get_func adpt_ip_pub_addr_get;
+	adpt_ip_port_sg_cfg_set_func adpt_ip_port_sg_cfg_set;
+	adpt_ip_port_intf_get_func adpt_ip_port_intf_get;
+	adpt_ip_vsi_arp_sg_cfg_set_func adpt_ip_vsi_arp_sg_cfg_set;
+	adpt_ip_port_intf_set_func adpt_ip_port_intf_set;
+	adpt_ip_vsi_sg_cfg_set_func adpt_ip_vsi_sg_cfg_set;
+	adpt_ip_host_next_func adpt_ip_host_next;
+	adpt_ip_port_macaddr_set_func adpt_ip_port_macaddr_set;
+	adpt_ip_vsi_intf_get_func adpt_ip_vsi_intf_get;
+	adpt_ip_port_sg_cfg_get_func adpt_ip_port_sg_cfg_get;
+	adpt_ip_intf_get_func adpt_ip_intf_get;
+	adpt_ip_host_del_func adpt_ip_host_del;
+	adpt_ip_route_mismatch_get_func adpt_ip_route_mismatch_get;
+	adpt_ip_vsi_arp_sg_cfg_get_func adpt_ip_vsi_arp_sg_cfg_get;
+	adpt_ip_port_arp_sg_cfg_set_func adpt_ip_port_arp_sg_cfg_set;
+	adpt_ip_vsi_mc_mode_set_func adpt_ip_vsi_mc_mode_set;
+	adpt_ip_vsi_intf_set_func adpt_ip_vsi_intf_set;
+	adpt_ip_nexthop_get_func adpt_ip_nexthop_get;
+	adpt_ip_route_mismatch_set_func adpt_ip_route_mismatch_set;
+	adpt_ip_host_get_func adpt_ip_host_get;
+	adpt_ip_intf_set_func adpt_ip_intf_set;
+	adpt_ip_vsi_mc_mode_get_func adpt_ip_vsi_mc_mode_get;
+	adpt_ip_port_macaddr_get_func adpt_ip_port_macaddr_get;
+	adpt_ip_port_arp_sg_cfg_get_func adpt_ip_port_arp_sg_cfg_get;
+	adpt_ip_nexthop_set_func adpt_ip_nexthop_set;
+	adpt_ip_global_ctrl_get_func adpt_ip_global_ctrl_get;
+	adpt_ip_global_ctrl_set_func adpt_ip_global_ctrl_set;
+	/* flow */
+	a_uint32_t adpt_flow_func_bitmap;
+	adpt_flow_host_add_func adpt_flow_host_add;
+	adpt_flow_entry_get_func adpt_flow_entry_get;
+	adpt_flow_entry_del_func adpt_flow_entry_del;
+	adpt_flow_entry_next_func adpt_flow_entry_next;
+	adpt_flow_status_get_func adpt_flow_status_get;
+	adpt_flow_ctrl_set_func adpt_flow_ctrl_set;
+	adpt_flow_age_timer_get_func adpt_flow_age_timer_get;
+	adpt_flow_status_set_func adpt_flow_status_set;
+	adpt_flow_host_get_func adpt_flow_host_get;
+	adpt_flow_host_del_func adpt_flow_host_del;
+	adpt_flow_ctrl_get_func adpt_flow_ctrl_get;
+	adpt_flow_age_timer_set_func adpt_flow_age_timer_set;
+	adpt_flow_entry_add_func adpt_flow_entry_add;
+	adpt_flow_global_cfg_get_func adpt_flow_global_cfg_get;
+	adpt_flow_global_cfg_set_func adpt_flow_global_cfg_set;
+
+	/* qm */
+	a_uint32_t adpt_qm_func_bitmap[2];
+	adpt_ucast_hash_map_set_func adpt_ucast_hash_map_set;
+	adpt_ac_dynamic_threshold_get_func adpt_ac_dynamic_threshold_get;
+	adpt_ucast_queue_base_profile_get_func adpt_ucast_queue_base_profile_get;
+	adpt_port_mcast_priority_class_get_func adpt_port_mcast_priority_class_get;
+	adpt_ac_dynamic_threshold_set_func adpt_ac_dynamic_threshold_set;
+	adpt_ac_prealloc_buffer_set_func adpt_ac_prealloc_buffer_set;
+	adpt_ucast_default_hash_get_func adpt_ucast_default_hash_get;
+	adpt_ucast_default_hash_set_func adpt_ucast_default_hash_set;
+	adpt_ac_queue_group_get_func adpt_ac_queue_group_get;
+	adpt_ac_ctrl_get_func adpt_ac_ctrl_get;
+	adpt_ac_prealloc_buffer_get_func adpt_ac_prealloc_buffer_get;
+	adpt_port_mcast_priority_class_set_func adpt_port_mcast_priority_class_set;
+	adpt_ucast_hash_map_get_func adpt_ucast_hash_map_get;
+	adpt_ac_static_threshold_set_func adpt_ac_static_threshold_set;
+	adpt_ac_queue_group_set_func adpt_ac_queue_group_set;
+	adpt_ac_group_buffer_get_func adpt_ac_group_buffer_get;
+	adpt_mcast_cpu_code_class_get_func adpt_mcast_cpu_code_class_get;
+	adpt_ac_ctrl_set_func adpt_ac_ctrl_set;
+	adpt_ucast_priority_class_get_func adpt_ucast_priority_class_get;
+	adpt_queue_flush_func adpt_queue_flush;
+	adpt_mcast_cpu_code_class_set_func adpt_mcast_cpu_code_class_set;
+	adpt_ucast_priority_class_set_func adpt_ucast_priority_class_set;
+	adpt_ac_static_threshold_get_func adpt_ac_static_threshold_get;
+	adpt_ucast_queue_base_profile_set_func adpt_ucast_queue_base_profile_set;
+	adpt_ac_group_buffer_set_func adpt_ac_group_buffer_set;
+	adpt_queue_counter_cleanup_func adpt_queue_counter_cleanup;
+	adpt_queue_counter_get_func adpt_queue_counter_get;
+	adpt_queue_counter_ctrl_get_func adpt_queue_counter_ctrl_get;
+	adpt_queue_counter_ctrl_set_func adpt_queue_counter_ctrl_set;
+	adpt_qm_enqueue_ctrl_set_func adpt_qm_enqueue_ctrl_set;
+	adpt_qm_enqueue_ctrl_get_func adpt_qm_enqueue_ctrl_get;
+	adpt_qm_port_source_profile_set_func adpt_qm_port_source_profile_set;
+	adpt_qm_port_source_profile_get_func adpt_qm_port_source_profile_get;
+
+	/*portvlan module begin*/
+	a_uint32_t adpt_portvlan_func_bitmap[2];
+	adpt_global_qinq_mode_set_func adpt_global_qinq_mode_set;
+	adpt_global_qinq_mode_get_func adpt_global_qinq_mode_get;
+	adpt_tpid_set_func adpt_tpid_set;
+	adpt_tpid_get_func adpt_tpid_get;
+	adpt_egress_tpid_set_func adpt_egress_tpid_set;
+	adpt_egress_tpid_get_func adpt_egress_tpid_get;
+	adpt_port_qinq_mode_set_func adpt_port_qinq_mode_set;
+	adpt_port_qinq_mode_get_func adpt_port_qinq_mode_get;
+	adpt_port_ingress_vlan_filter_set_func adpt_port_ingress_vlan_filter_set;
+	adpt_port_ingress_vlan_filter_get_func adpt_port_ingress_vlan_filter_get;
+	adpt_port_default_vlantag_set_func adpt_port_default_vlantag_set;
+	adpt_port_default_vlantag_get_func adpt_port_default_vlantag_get;
+	adpt_port_tag_propagation_set_func adpt_port_tag_propagation_set;
+	adpt_port_tag_propagation_get_func adpt_port_tag_propagation_get;
+	adpt_port_vlantag_egmode_set_func adpt_port_vlantag_egmode_set;
+	adpt_port_vlantag_egmode_get_func adpt_port_vlantag_egmode_get;
+	adpt_port_vlan_xlt_miss_cmd_set_func adpt_port_vlan_xlt_miss_cmd_set;
+	adpt_port_vlan_xlt_miss_cmd_get_func adpt_port_vlan_xlt_miss_cmd_get;
+	adpt_port_vlan_trans_add_func adpt_port_vlan_trans_add;
+	adpt_port_vlan_trans_get_func adpt_port_vlan_trans_get;
+	adpt_port_vlan_trans_del_func adpt_port_vlan_trans_del;
+	adpt_port_vlan_trans_iterate_func adpt_port_vlan_trans_iterate;
+	adpt_port_vsi_egmode_set_func adpt_port_vsi_egmode_set;
+	adpt_port_vsi_egmode_get_func adpt_port_vsi_egmode_get;
+	adpt_port_vlantag_vsi_egmode_enable_set_func adpt_port_vlantag_vsi_egmode_enable_set;
+	adpt_port_vlantag_vsi_egmode_enable_get_func adpt_port_vlantag_vsi_egmode_enable_get;
+	adpt_qinq_mode_set_func adpt_qinq_mode_set;
+	adpt_qinq_mode_get_func adpt_qinq_mode_get;
+	adpt_port_qinq_role_set_func adpt_port_qinq_role_set;
+	adpt_port_qinq_role_get_func adpt_port_qinq_role_get;
+	adpt_port_invlan_mode_set_func adpt_port_invlan_mode_set;
+	adpt_port_invlan_mode_get_func adpt_port_invlan_mode_get;
+	adpt_port_vlan_trans_adv_add_func adpt_port_vlan_trans_adv_add;
+	adpt_port_vlan_trans_adv_del_func adpt_port_vlan_trans_adv_del;
+	adpt_port_vlan_trans_adv_getfirst_func adpt_port_vlan_trans_adv_getfirst;
+	adpt_port_vlan_trans_adv_getnext_func adpt_port_vlan_trans_adv_getnext;
+	adpt_port_vlan_counter_get_func adpt_port_vlan_counter_get;
+	adpt_port_vlan_counter_cleanup_func adpt_port_vlan_counter_cleanup;
+	adpt_portvlan_member_add_func adpt_portvlan_member_add;
+	adpt_portvlan_member_del_func adpt_portvlan_member_del;
+	adpt_portvlan_member_update_func adpt_portvlan_member_update;
+	adpt_portvlan_member_get_func adpt_portvlan_member_get;
+	/*portvlan module end*/
+
+	/*ctrlpkt module begin*/
+	a_uint32_t adpt_ctrlpkt_func_bitmap;
+	adpt_mgmtctrl_ethtype_profile_set_func adpt_mgmtctrl_ethtype_profile_set;
+	adpt_mgmtctrl_ethtype_profile_get_func adpt_mgmtctrl_ethtype_profile_get;
+	adpt_mgmtctrl_rfdb_profile_set_func adpt_mgmtctrl_rfdb_profile_set;
+	adpt_mgmtctrl_rfdb_profile_get_func adpt_mgmtctrl_rfdb_profile_get;
+	adpt_mgmtctrl_ctrlpkt_profile_add_func adpt_mgmtctrl_ctrlpkt_profile_add;
+	adpt_mgmtctrl_ctrlpkt_profile_del_func adpt_mgmtctrl_ctrlpkt_profile_del;
+	adpt_mgmtctrl_ctrlpkt_profile_getfirst_func adpt_mgmtctrl_ctrlpkt_profile_getfirst;
+	adpt_mgmtctrl_ctrlpkt_profile_getnext_func adpt_mgmtctrl_ctrlpkt_profile_getnext;
+	/*ctrlpkt module end*/
+
+	/*servcode module begin*/
+	a_uint32_t adpt_servcode_func_bitmap;
+	adpt_servcode_config_set_func adpt_servcode_config_set;
+	adpt_servcode_config_get_func adpt_servcode_config_get;
+	adpt_servcode_loopcheck_en_func adpt_servcode_loopcheck_en;
+	adpt_servcode_loopcheck_status_get_func adpt_servcode_loopcheck_status_get;
+	/*servcode module end*/
+
+	/* pppoe */
+	a_uint32_t adpt_pppoe_func_bitmap;
+	adpt_pppoe_session_table_add_func adpt_pppoe_session_table_add;
+	adpt_pppoe_session_table_del_func adpt_pppoe_session_table_del;
+	adpt_pppoe_session_table_get_func adpt_pppoe_session_table_get;
+	adpt_pppoe_en_set_func adpt_pppoe_en_set;
+	adpt_pppoe_en_get_func adpt_pppoe_en_get;
+
+	/*sec */
+	a_uint32_t adpt_sec_func_bitmap;
+	adpt_sec_l3_excep_parser_ctrl_set_func adpt_sec_l3_excep_parser_ctrl_set;
+	adpt_sec_l3_excep_ctrl_get_func adpt_sec_l3_excep_ctrl_get;
+	adpt_sec_l3_excep_parser_ctrl_get_func adpt_sec_l3_excep_parser_ctrl_get;
+	adpt_sec_l4_excep_parser_ctrl_set_func adpt_sec_l4_excep_parser_ctrl_set;
+	adpt_sec_l3_excep_ctrl_set_func adpt_sec_l3_excep_ctrl_set;
+	adpt_sec_l4_excep_parser_ctrl_get_func adpt_sec_l4_excep_parser_ctrl_get;
+
+	/*acl*/
+	a_uint32_t adpt_acl_func_bitmap;
+	adpt_acl_list_bind_func adpt_acl_list_bind;
+	adpt_acl_list_dump_func adpt_acl_list_dump;
+	adpt_acl_udf_profile_set_func adpt_acl_udf_profile_set;
+	adpt_acl_rule_query_func adpt_acl_rule_query;
+	adpt_acl_list_unbind_func adpt_acl_list_unbind;
+	adpt_acl_rule_add_func adpt_acl_rule_add;
+	adpt_acl_rule_delete_func adpt_acl_rule_delete;
+	adpt_acl_rule_dump_func adpt_acl_rule_dump;
+	adpt_acl_udf_profile_get_func adpt_acl_udf_profile_get;
+	adpt_acl_list_creat_func adpt_acl_list_creat;
+	adpt_acl_list_destroy_func adpt_acl_list_destroy;
+
+	/* qos */
+	a_uint32_t adpt_qos_func_bitmap;
+	adpt_qos_port_pri_set_func adpt_qos_port_pri_set;
+	adpt_qos_port_pri_get_func adpt_qos_port_pri_get;
+	adpt_qos_cosmap_pcp_get_func adpt_qos_cosmap_pcp_get;
+	adpt_queue_scheduler_set_func adpt_queue_scheduler_set;
+	adpt_queue_scheduler_get_func adpt_queue_scheduler_get;
+	adpt_port_queues_get_func adpt_port_queues_get;
+	adpt_qos_cosmap_pcp_set_func adpt_qos_cosmap_pcp_set;
+	adpt_qos_port_remark_get_func adpt_qos_port_remark_get;
+	adpt_qos_cosmap_dscp_get_func adpt_qos_cosmap_dscp_get;
+	adpt_qos_cosmap_flow_set_func adpt_qos_cosmap_flow_set;
+	adpt_qos_port_group_set_func adpt_qos_port_group_set;
+	adpt_ring_queue_map_set_func adpt_ring_queue_map_set;
+	adpt_qos_cosmap_dscp_set_func adpt_qos_cosmap_dscp_set;
+	adpt_qos_port_remark_set_func adpt_qos_port_remark_set;
+	adpt_qos_cosmap_flow_get_func adpt_qos_cosmap_flow_get;
+	adpt_qos_port_group_get_func adpt_qos_port_group_get;
+	adpt_ring_queue_map_get_func adpt_ring_queue_map_get;
+	adpt_tdm_tick_num_set_func adpt_tdm_tick_num_set;
+	adpt_tdm_tick_num_get_func adpt_tdm_tick_num_get;
+	adpt_port_scheduler_cfg_set_func adpt_port_scheduler_cfg_set;
+	adpt_port_scheduler_cfg_get_func adpt_port_scheduler_cfg_get;
+	adpt_scheduler_dequeue_ctrl_get_func adpt_scheduler_dequeue_ctrl_get;
+	adpt_scheduler_dequeue_ctrl_set_func adpt_scheduler_dequeue_ctrl_set;
+	adpt_qos_port_mode_pri_get_func adpt_qos_port_mode_pri_get;
+	adpt_qos_port_mode_pri_set_func adpt_qos_port_mode_pri_set;
+	adpt_port_scheduler_cfg_reset_func adpt_port_scheduler_cfg_reset;
+	adpt_port_scheduler_resource_get_func adpt_port_scheduler_resource_get;
+
+	/* bm */
+	a_uint32_t adpt_bm_func_bitmap;
+	adpt_port_bufgroup_map_get_func adpt_port_bufgroup_map_get;
+	adpt_bm_port_reserved_buffer_get_func adpt_bm_port_reserved_buffer_get;
+	adpt_bm_bufgroup_buffer_get_func adpt_bm_bufgroup_buffer_get;
+	adpt_bm_port_dynamic_thresh_get_func adpt_bm_port_dynamic_thresh_get;
+	adpt_port_bm_ctrl_get_func adpt_port_bm_ctrl_get;
+	adpt_bm_bufgroup_buffer_set_func adpt_bm_bufgroup_buffer_set;
+	adpt_port_bufgroup_map_set_func adpt_port_bufgroup_map_set;
+	adpt_bm_port_static_thresh_get_func adpt_bm_port_static_thresh_get;
+	adpt_bm_port_reserved_buffer_set_func adpt_bm_port_reserved_buffer_set;
+	adpt_bm_port_static_thresh_set_func adpt_bm_port_static_thresh_set;
+	adpt_bm_port_dynamic_thresh_set_func adpt_bm_port_dynamic_thresh_set;
+	adpt_port_bm_ctrl_set_func adpt_port_bm_ctrl_set;
+	adpt_port_tdm_ctrl_set_func adpt_port_tdm_ctrl_set;
+	adpt_port_tdm_tick_cfg_set_func adpt_port_tdm_tick_cfg_set;
+	adpt_bm_port_counter_get_func adpt_bm_port_counter_get;
+
+	//shaper
+	a_uint32_t adpt_shaper_func_bitmap;
+	adpt_flow_shaper_set_func adpt_flow_shaper_set;
+	adpt_queue_shaper_get_func adpt_queue_shaper_get;
+	adpt_queue_shaper_token_number_set_func adpt_queue_shaper_token_number_set;
+	adpt_port_shaper_get_func adpt_port_shaper_get;
+	adpt_flow_shaper_time_slot_get_func adpt_flow_shaper_time_slot_get;
+	adpt_port_shaper_time_slot_get_func adpt_port_shaper_time_slot_get;
+	adpt_flow_shaper_time_slot_set_func adpt_flow_shaper_time_slot_set;
+	adpt_shaper_ipg_preamble_length_set_func adpt_shaper_ipg_preamble_length_set;
+	adpt_port_shaper_token_number_set_func adpt_port_shaper_token_number_set;
+	adpt_queue_shaper_token_number_get_func adpt_queue_shaper_token_number_get;
+	adpt_queue_shaper_time_slot_get_func adpt_queue_shaper_time_slot_get;
+	adpt_port_shaper_token_number_get_func adpt_port_shaper_token_number_get;
+	adpt_flow_shaper_token_number_set_func adpt_flow_shaper_token_number_set;
+	adpt_flow_shaper_token_number_get_func adpt_flow_shaper_token_number_get;
+	adpt_shaper_ipg_preamble_length_get_func adpt_shaper_ipg_preamble_length_get;
+	adpt_port_shaper_set_func adpt_port_shaper_set;
+	adpt_port_shaper_time_slot_set_func adpt_port_shaper_time_slot_set;
+	adpt_flow_shaper_get_func adpt_flow_shaper_get;
+	adpt_queue_shaper_set_func adpt_queue_shaper_set;
+	adpt_queue_shaper_time_slot_set_func adpt_queue_shaper_time_slot_set;
+
+//policer
+	a_uint32_t adpt_policer_func_bitmap;
+	adpt_acl_policer_counter_get_func adpt_acl_policer_counter_get;
+	adpt_port_policer_counter_get_func adpt_port_policer_counter_get;
+	adpt_port_compensation_byte_get_func adpt_port_compensation_byte_get;
+	adpt_port_policer_entry_get_func adpt_port_policer_entry_get;
+	adpt_port_policer_entry_set_func adpt_port_policer_entry_set;
+	adpt_acl_policer_entry_get_func adpt_acl_policer_entry_get;
+	adpt_acl_policer_entry_set_func adpt_acl_policer_entry_set;
+	adpt_policer_time_slot_get_func adpt_policer_time_slot_get;
+	adpt_port_compensation_byte_set_func adpt_port_compensation_byte_set;
+	adpt_policer_time_slot_set_func adpt_policer_time_slot_set;
+	adpt_policer_global_counter_get_func adpt_policer_global_counter_get;
+	adpt_policer_bypass_en_set_func adpt_policer_bypass_en_set;
+	adpt_policer_bypass_en_get_func adpt_policer_bypass_en_get;
+
+	/* misc */
+	adpt_debug_port_counter_enable_func adpt_debug_port_counter_enable;
+	adpt_debug_port_counter_status_get_func adpt_debug_port_counter_status_get;
+	adpt_debug_counter_set_func adpt_debug_counter_set;
+	adpt_debug_counter_get_func adpt_debug_counter_get;
+	adpt_intr_port_link_mask_set_func adpt_intr_port_link_mask_set;
+	adpt_intr_port_link_mask_get_func adpt_intr_port_link_mask_get;
+	adpt_intr_port_link_status_get_func adpt_intr_port_link_status_get;
+
+	/* uniphy */
+	adpt_uniphy_mode_set_func adpt_uniphy_mode_set;
+
+	/* ptp */
+	adpt_ptp_config_set_func adpt_ptp_config_set;
+	adpt_ptp_config_get_func adpt_ptp_config_get;
+	adpt_ptp_reference_clock_set_func adpt_ptp_reference_clock_set;
+	adpt_ptp_reference_clock_get_func adpt_ptp_reference_clock_get;
+	adpt_ptp_rx_timestamp_mode_set_func adpt_ptp_rx_timestamp_mode_set;
+	adpt_ptp_rx_timestamp_mode_get_func adpt_ptp_rx_timestamp_mode_get;
+	adpt_ptp_timestamp_get_func adpt_ptp_timestamp_get;
+	adpt_ptp_pkt_timestamp_set_func adpt_ptp_pkt_timestamp_set;
+	adpt_ptp_pkt_timestamp_get_func adpt_ptp_pkt_timestamp_get;
+	adpt_ptp_grandmaster_mode_set_func adpt_ptp_grandmaster_mode_set;
+	adpt_ptp_grandmaster_mode_get_func adpt_ptp_grandmaster_mode_get;
+	adpt_ptp_rtc_time_get_func adpt_ptp_rtc_time_get;
+	adpt_ptp_rtc_time_set_func adpt_ptp_rtc_time_set;
+	adpt_ptp_rtc_time_clear_func adpt_ptp_rtc_time_clear;
+	adpt_ptp_rtc_adjtime_set_func adpt_ptp_rtc_adjtime_set;
+	adpt_ptp_rtc_adjfreq_set_func adpt_ptp_rtc_adjfreq_set;
+	adpt_ptp_rtc_adjfreq_get_func adpt_ptp_rtc_adjfreq_get;
+	adpt_ptp_link_delay_set_func adpt_ptp_link_delay_set;
+	adpt_ptp_link_delay_get_func adpt_ptp_link_delay_get;
+	adpt_ptp_security_set_func adpt_ptp_security_set;
+	adpt_ptp_security_get_func adpt_ptp_security_get;
+	adpt_ptp_pps_signal_control_set_func adpt_ptp_pps_signal_control_set;
+	adpt_ptp_pps_signal_control_get_func adpt_ptp_pps_signal_control_get;
+	adpt_ptp_rx_crc_recalc_enable_func adpt_ptp_rx_crc_recalc_enable;
+	adpt_ptp_rx_crc_recalc_status_get_func adpt_ptp_rx_crc_recalc_status_get;
+	adpt_ptp_asym_correction_set_func adpt_ptp_asym_correction_set;
+	adpt_ptp_asym_correction_get_func adpt_ptp_asym_correction_get;
+	adpt_ptp_output_waveform_set_func adpt_ptp_output_waveform_set;
+	adpt_ptp_output_waveform_get_func adpt_ptp_output_waveform_get;
+	adpt_ptp_rtc_time_snapshot_enable_func adpt_ptp_rtc_time_snapshot_enable;
+	adpt_ptp_rtc_time_snapshot_status_get_func adpt_ptp_rtc_time_snapshot_status_get;
+	adpt_ptp_increment_sync_from_clock_enable_func adpt_ptp_increment_sync_from_clock_enable;
+	adpt_ptp_increment_sync_from_clock_status_get_func \
+		adpt_ptp_increment_sync_from_clock_status_get;
+	adpt_ptp_tod_uart_set_func adpt_ptp_tod_uart_set;
+	adpt_ptp_tod_uart_get_func adpt_ptp_tod_uart_get;
+	adpt_ptp_enhanced_timestamp_engine_set_func adpt_ptp_enhanced_timestamp_engine_set;
+	adpt_ptp_enhanced_timestamp_engine_get_func adpt_ptp_enhanced_timestamp_engine_get;
+	adpt_ptp_trigger_set_func adpt_ptp_trigger_set;
+	adpt_ptp_trigger_get_func adpt_ptp_trigger_get;
+	adpt_ptp_capture_set_func adpt_ptp_capture_set;
+	adpt_ptp_capture_get_func adpt_ptp_capture_get;
+	adpt_ptp_interrupt_set_func adpt_ptp_interrupt_set;
+	adpt_ptp_interrupt_get_func adpt_ptp_interrupt_get;
+
+	/* sfp */
+	adpt_sfp_eeprom_data_get_func adpt_sfp_eeprom_data_get;
+	adpt_sfp_eeprom_data_set_func adpt_sfp_eeprom_data_set;
+	adpt_sfp_diag_ctrl_status_get_func adpt_sfp_diag_ctrl_status_get;
+	adpt_sfp_diag_extenal_calibration_const_get_func
+		adpt_sfp_diag_extenal_calibration_const_get;
+	adpt_sfp_link_length_get_func adpt_sfp_link_length_get;
+	adpt_sfp_diag_internal_threshold_get_func adpt_sfp_diag_internal_threshold_get;
+	adpt_sfp_diag_realtime_get_func adpt_sfp_diag_realtime_get;
+	adpt_sfp_laser_wavelength_get_func adpt_sfp_laser_wavelength_get;
+	adpt_sfp_option_get_func adpt_sfp_option_get;
+	adpt_sfp_checkcode_get_func adpt_sfp_checkcode_get;
+	adpt_sfp_diag_alarm_warning_flag_get_func adpt_sfp_diag_alarm_warning_flag_get;
+	adpt_sfp_device_type_get_func adpt_sfp_device_type_get;
+	adpt_sfp_vendor_info_get_func adpt_sfp_vendor_info_get;
+	adpt_sfp_transceiver_code_get_func adpt_sfp_transceiver_code_get;
+	adpt_sfp_ctrl_rate_get_func adpt_sfp_ctrl_rate_get;
+	adpt_sfp_enhanced_cfg_get_func adpt_sfp_enhanced_cfg_get;
+	adpt_sfp_rate_encode_get_func adpt_sfp_rate_encode_get;
+	/*led*/
+	adpt_led_ctrl_pattern_set_func adpt_led_ctrl_pattern_set;
+	adpt_led_ctrl_pattern_get_func adpt_led_ctrl_pattern_get;
+	adpt_led_ctrl_source_set_func adpt_led_ctrl_source_set;
+}adpt_api_t;
+
+
+adpt_api_t *adpt_api_ptr_get(a_uint32_t dev_id);
+sw_error_t adpt_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+sw_error_t adpt_module_func_ctrl_set(a_uint32_t dev_id,
+		a_uint32_t module, fal_func_ctrl_t *func_ctrl);
+sw_error_t adpt_module_func_ctrl_get(a_uint32_t dev_id,
+		a_uint32_t module, fal_func_ctrl_t *func_ctrl);
+sw_error_t adpt_module_func_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+#ifdef SCOMPHY
+a_uint32_t adapt_scomphy_revision_get(a_uint32_t dev_id);
+#endif
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif
diff --git a/qca-ssdk/include/adpt/cppe/adpt_cppe_flow.h b/qca-ssdk/include/adpt/cppe/adpt_cppe_flow.h
new file mode 100755
index 0000000..72480e5
--- /dev/null
+++ b/qca-ssdk/include/adpt/cppe/adpt_cppe_flow.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _ADPT_CPPE_FLOW_
+#define _ADPT_CPPE_FLOW_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#ifndef IN_FLOW_MINI
+sw_error_t
+adpt_cppe_flow_copy_escape_set(a_uint32_t dev_id, a_bool_t enable);
+
+sw_error_t
+adpt_cppe_flow_copy_escape_get(a_uint32_t dev_id, a_bool_t *enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif
diff --git a/qca-ssdk/include/adpt/cppe/adpt_cppe_mib.h b/qca-ssdk/include/adpt/cppe/adpt_cppe_mib.h
new file mode 100755
index 0000000..3b1302e
--- /dev/null
+++ b/qca-ssdk/include/adpt/cppe/adpt_cppe_mib.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _ADPT_CPPE_MIB_H_
+#define _ADPT_CPPE_MIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+sw_error_t
+adpt_cppe_lpbk_mib_cpukeep_get(a_uint32_t dev_id, a_uint32_t port_id,
+	a_bool_t *enable);
+
+sw_error_t
+adpt_cppe_lpbk_mib_cpukeep_set(a_uint32_t dev_id, a_uint32_t port_id,
+	a_bool_t enable);
+
+sw_error_t
+adpt_hppe_lpbk_mib_status_get(a_uint32_t dev_id, a_uint32_t port_id,
+	a_bool_t *enable);
+
+sw_error_t
+adpt_cppe_lpbk_mib_status_set(a_uint32_t dev_id, a_uint32_t port_id,
+	a_bool_t enable);
+
+sw_error_t
+adpt_cppe_lpbk_mib_flush_counters(a_uint32_t dev_id,
+	fal_port_t port_id);
+
+sw_error_t
+adpt_cppe_lpbk_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+	fal_mib_info_t * mib_info );
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif
diff --git a/qca-ssdk/include/adpt/cppe/adpt_cppe_misc.h b/qca-ssdk/include/adpt/cppe/adpt_cppe_misc.h
new file mode 100755
index 0000000..db2d7d9
--- /dev/null
+++ b/qca-ssdk/include/adpt/cppe/adpt_cppe_misc.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _ADPT_CPPE_MISC_
+#define _ADPT_CPPE_MISC_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+sw_error_t
+adpt_cppe_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id,
+		fal_counter_en_t *cnt_en);
+sw_error_t
+adpt_cppe_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_counter_en_t *cnt_en);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif
diff --git a/qca-ssdk/include/adpt/cppe/adpt_cppe_portctrl.h b/qca-ssdk/include/adpt/cppe/adpt_cppe_portctrl.h
new file mode 100755
index 0000000..9e38ed3
--- /dev/null
+++ b/qca-ssdk/include/adpt/cppe/adpt_cppe_portctrl.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _ADPT_CPPE_PORTCTRLH_
+#define _ADPT_CPPE_PORTCTRLH_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2          0x0
+#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4          0x1
+#define CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3          0x0
+#define CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS         0x1
+#define CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4          0x0
+#define CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0          0x1
+#define CPPE_PORT5_GMAC_SEL_GMAC                  0x0
+#define CPPE_PORT5_GMAC_SEL_XGMAC                 0x1
+#define CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK        0x0
+#define CPPE_PCS0_CHANNEL4_SEL_PORT3_CLOCK        0x1
+#define CPPE_PCS0_CHANNEL0_SEL_PSGMII             0x0
+#define CPPE_PCS0_CHANNEL0_SEL_SGMIIPLUS          0x1
+#define CPPE_DETECTION_PHY_FAILURE                0xFFFF
+#define CPPE_LOOPBACK_PORT_RATE_FREQUENCY         300  /* 300MHZ*/
+#define CPPE_LOOPBACK_PORT_NUM                    0x1
+
+sw_error_t
+_adpt_cppe_port_mux_mac_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t port_type);
+sw_error_t
+adpt_cppe_port_mru_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl);
+sw_error_t
+adpt_cppe_port_mru_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_cppe_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl);
+sw_error_t
+adpt_cppe_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl);
+sw_error_t
+adpt_cppe_port_source_filter_set(a_uint32_t dev_id,
+		fal_port_t port_id, a_bool_t enable);
+sw_error_t
+adpt_cppe_port_source_filter_get(a_uint32_t dev_id,
+		fal_port_t port_id, a_bool_t * enable);
+sw_error_t
+adpt_cppe_port_source_filter_config_set(
+		a_uint32_t dev_id, fal_port_t port_id,
+		fal_src_filter_config_t *src_filter_config);
+sw_error_t
+adpt_cppe_port_source_filter_config_get
+		(a_uint32_t dev_id, fal_port_t port_id,
+		fal_src_filter_config_t* src_filter_config);
+#endif
+sw_error_t
+adpt_cppe_port_to_channel_convert(a_uint32_t dev_id,
+		a_uint32_t port_id, a_uint32_t *channel_id);
+sw_error_t
+adpt_cppe_switch_port_loopback_set(a_uint32_t dev_id,
+	fal_port_t port_id, fal_loopback_config_t *loopback_cfg);
+
+sw_error_t
+adpt_cppe_switch_port_loopback_get(a_uint32_t dev_id,
+	fal_port_t port_id, fal_loopback_config_t *loopback_cfg);
+
+sw_error_t
+adpt_cppe_switch_port_loopback_flowctrl_set(a_uint32_t dev_id,
+	fal_port_t port_id, a_bool_t enable);
+
+sw_error_t
+adpt_cppe_switch_port_loopback_flowctrl_get(a_uint32_t dev_id,
+	fal_port_t port_id, a_bool_t *enable);
+
+sw_error_t
+adpt_cppe_lpbk_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
+	a_uint32_t *max_frame);
+
+sw_error_t
+adpt_cppe_lpbk_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
+	a_uint32_t max_frame);
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif
diff --git a/qca-ssdk/include/adpt/cppe/adpt_cppe_qm.h b/qca-ssdk/include/adpt/cppe/adpt_cppe_qm.h
new file mode 100755
index 0000000..a38b475
--- /dev/null
+++ b/qca-ssdk/include/adpt/cppe/adpt_cppe_qm.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _ADPT_CPPE_QM_H_
+#define _ADPT_CPPE_QM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#ifndef IN_QM_MINI
+sw_error_t
+adpt_cppe_qm_port_source_profile_set(
+		a_uint32_t dev_id, fal_port_t port, a_uint32_t src_profile);
+sw_error_t
+adpt_cppe_qm_port_source_profile_get(
+		a_uint32_t dev_id, fal_port_t port, a_uint32_t *src_profile);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif
+
+
diff --git a/qca-ssdk/include/adpt/cppe/adpt_cppe_qos.h b/qca-ssdk/include/adpt/cppe/adpt_cppe_qos.h
new file mode 100644
index 0000000..867e733
--- /dev/null
+++ b/qca-ssdk/include/adpt/cppe/adpt_cppe_qos.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _ADPT_CPPE_QOS_H_
+#define _ADPT_CPPE_QOS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+sw_error_t
+adpt_cppe_qos_port_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_pri_precedence_t *pri);
+sw_error_t
+adpt_cppe_qos_port_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_pri_precedence_t *pri);
+sw_error_t
+adpt_cppe_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t pcp,
+					fal_qos_cosmap_t *cosmap);
+sw_error_t
+adpt_cppe_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t pcp,
+					fal_qos_cosmap_t *cosmap);
+sw_error_t
+adpt_cppe_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t dscp,
+					fal_qos_cosmap_t *cosmap);
+sw_error_t
+adpt_cppe_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint16_t flow,
+					fal_qos_cosmap_t *cosmap);
+sw_error_t
+adpt_cppe_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_group_t *group);
+sw_error_t
+adpt_cppe_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t dscp,
+					fal_qos_cosmap_t *cosmap);
+sw_error_t
+adpt_cppe_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint16_t flow,
+					fal_qos_cosmap_t *cosmap);
+sw_error_t
+adpt_cppe_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_group_t *group);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif
+
diff --git a/qca-ssdk/include/adpt/cppe/adpt_cppe_uniphy.h b/qca-ssdk/include/adpt/cppe/adpt_cppe_uniphy.h
new file mode 100755
index 0000000..635fdbf
--- /dev/null
+++ b/qca-ssdk/include/adpt/cppe/adpt_cppe_uniphy.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _ADPT_CPPE_UNIPHYH_
+#define _ADPT_CPPE_UNIPHYH_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+sw_error_t
+__adpt_cppe_uniphy_channel_selection_set(a_uint32_t dev_id,
+	a_uint32_t ch0_selection, a_uint32_t ch4_selection);
+
+void
+__adpt_hppe_gcc_uniphy_xpcs_reset(a_uint32_t dev_id, a_uint32_t uniphy_index,
+		a_bool_t enable);
+sw_error_t
+__adpt_hppe_uniphy_calibrate(a_uint32_t dev_id, a_uint32_t uniphy_index);
+
+void
+__adpt_cppe_gcc_uniphy_software_reset(a_uint32_t dev_id,
+		a_uint32_t uniphy_index);
+sw_error_t
+__adpt_cppe_uniphy_mode_set(a_uint32_t dev_id,
+		a_uint32_t uniphy_index, a_uint32_t mode);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif
diff --git a/qca-ssdk/include/adpt/hppe/adpt_hppe.h b/qca-ssdk/include/adpt/hppe/adpt_hppe.h
new file mode 100755
index 0000000..d8c5be4
--- /dev/null
+++ b/qca-ssdk/include/adpt/hppe/adpt_hppe.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _ADPT_HPPE_H_
+#define _ADPT_HPPE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+void adpt_hppe_fdb_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_fdb_init(a_uint32_t dev_id);
+void adpt_hppe_portvlan_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_portvlan_init(a_uint32_t dev_id);
+void adpt_hppe_ctrlpkt_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_ctrlpkt_init(a_uint32_t dev_id);
+void adpt_hppe_servcode_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_servcode_init(a_uint32_t dev_id);
+void adpt_hppe_rss_hash_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_rss_hash_init(a_uint32_t dev_id);
+void adpt_hppe_mib_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_mib_init(a_uint32_t dev_id);
+void adpt_hppe_stp_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_stp_init(a_uint32_t dev_id);
+void adpt_hppe_vsi_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_vsi_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_port_ctrl_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_misc_init(a_uint32_t dev_id);
+
+void adpt_hppe_mirror_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_mirror_init(a_uint32_t dev_id);
+void adpt_hppe_trunk_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_trunk_init(a_uint32_t dev_id);
+void adpt_hppe_ip_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_ip_init(a_uint32_t dev_id);
+void adpt_hppe_qm_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_qm_init(a_uint32_t dev_id);
+void adpt_hppe_flow_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_flow_init(a_uint32_t dev_id);
+
+void adpt_hppe_pppoe_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_pppoe_init(a_uint32_t dev_id);
+void adpt_hppe_sec_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_sec_init(a_uint32_t dev_id);
+
+void adpt_hppe_acl_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_acl_init(a_uint32_t dev_id);
+void adpt_hppe_qos_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_qos_init(a_uint32_t dev_id);
+void adpt_hppe_bm_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_bm_init(a_uint32_t dev_id);
+
+sw_error_t adpt_hppe_shaper_init(a_uint32_t dev_id);
+
+void adpt_hppe_port_ctrl_func_bitmap_init(a_uint32_t dev_id);
+
+void adpt_hppe_shaper_func_bitmap_init(a_uint32_t dev_id);
+
+sw_error_t adpt_hppe_policer_init(a_uint32_t dev_id);
+
+void adpt_hppe_policer_func_bitmap_init(a_uint32_t dev_id);
+
+sw_error_t adpt_hppe_uniphy_init(a_uint32_t dev_id);
+
+/*shaper*/
+#define HPPE_MAX_C_TOKEN_NUM 0x3fffffff
+#define HPPE_MAX_E_TOKEN_NUM 0x3fffffff
+
+#define HPPE_POLICER_TIMESLOT_DFT 600
+#define HPPE_PORT_SHAPER_TIMESLOT_DFT 8
+#define HPPE_FLOW_SHAPER_TIMESLOT_DFT 64
+#define HPPE_QUEUE_SHAPER_TIMESLOT_DFT 300
+#define HPPE_SHAPER_IPG_PREAMBLE_LEN_DFT 20
+
+/*BM*/
+#define HPPE_BM_PORT_NUM 15
+#define HPPE_BM_PHY_PORT_OFFSET 8
+
+void adpt_hppe_ptp_func_bitmap_init(a_uint32_t dev_id);
+sw_error_t adpt_hppe_ptp_init(a_uint32_t dev_id);
+
+#define HPPE_REVISION              0x0
+#define CPPE_REVISION              0x1
+#define UNKNOWN_REVISION           0xff
+
+a_uint32_t adpt_hppe_chip_revision_get(a_uint32_t dev_id);
+
+#ifdef IN_FDB
+sw_error_t
+adpt_hppe_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif
diff --git a/qca-ssdk/include/adpt/mp/adpt_mp.h b/qca-ssdk/include/adpt/mp/adpt_mp.h
new file mode 100644
index 0000000..47ba498
--- /dev/null
+++ b/qca-ssdk/include/adpt/mp/adpt_mp.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ADPT_MP_H_
+#define _ADPT_MP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#define MP_PORT_TO_GMAC_ID(port_id) (port_id -1)
+#define MP_MAX_PORT 2
+#define MP_GMAC0 0
+#define MP_GMAC1 1
+#define MP_PORT_ID_CHECK(port_id) \
+do { \
+    if (port_id > MP_MAX_PORT) \
+        return SW_OUT_OF_RANGE; \
+} while (0)
+
+sw_error_t adpt_mp_intr_init(a_uint32_t dev_id);
+sw_error_t adpt_mp_mib_init(a_uint32_t dev_id);
+sw_error_t adpt_mp_portctrl_init(a_uint32_t dev_id);
+sw_error_t adpt_mp_uniphy_init(a_uint32_t dev_id);
+sw_error_t adpt_mp_led_init(a_uint32_t dev_id);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif
diff --git a/qca-ssdk/include/adpt/mp/adpt_mp_portctrl.h b/qca-ssdk/include/adpt/mp/adpt_mp_portctrl.h
new file mode 100755
index 0000000..f5b8397
--- /dev/null
+++ b/qca-ssdk/include/adpt/mp/adpt_mp_portctrl.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ADPT_PORTCTRL_H_
+#define _ADPT_PORTCTRL_H_
+
+
+#define GMAC_SPEED_10M                       0x0
+#define GMAC_SPEED_100M                      0x1
+#define GMAC_SPEED_1000M                     0x0
+#define GMAC_FULL_DUPLEX                     0x1
+#define GMAC_HALF_DUPLEX                     0x0
+#define GMAC_PAUSE_TIME                      0xffff
+#define GMAC_PAUSE_ZERO_QUANTA_ENABLE        0x0
+#define GMAC_JD_ENABLE                       0x1
+#define GMAC_WD_DISABLE                      0x0
+#define GMAC_FRAME_BURST_ENABLE              0x1
+#define GMAC_JUMBO_FRAME_ENABLE              0x1
+#define GMAC_MAX_FRAME_CTRL_ENABLE           0x1
+#define GMAC_LPI_LINK_UP                     0x1
+#define GMAC_LPI_AUTO_MODE                   0x1
+#define GMAC_TX_STORE_FORWAD_ENABLE          0x1
+#define GMAC_RX_STORE_FORWAD_ENABLE          0x1
+#define GMAC_FORWARD_ERROR_FRAME_DISABLE     0x0
+#define GMAC_DROP_GAINT_FRAME_DISABLE        0x0
+#define GMAC_FLUSH_RECEIVED_FRAMES_DISABLE   0x1
+#define GMAC_HW_FLOWCTRL_ENABLE              0x1
+#define GMAC_ACTIVATE_FLOWCTRL_MASK          0x800600
+#define GMAC_ACTIVATE_FLOWCTRL_WITH_1KB      0x0
+#define GMAC_ACTIVATE_FLOWCTRL_WITH_2KB      0x200
+#define GMAC_ACTIVATE_FLOWCTRL_WITH_3KB      0x400
+#define GMAC_ACTIVATE_FLOWCTRL_WITH_4KB      0x600
+#define GMAC_ACTIVATE_FLOWCTRL_WITH_5KB      0x800000
+#define GMAC_ACTIVATE_FLOWCTRL_WITH_6KB      0x800200
+#define GMAC_ACTIVATE_FLOWCTRL_WITH_7KB      0x800400
+#define GMAC_DACTIVATE_FLOWCTRL_MASK         0x401800
+#define GMAC_DACTIVATE_FLOWCTRL_WITH_1KB     0x0
+#define GMAC_DACTIVATE_FLOWCTRL_WITH_2KB     0x800
+#define GMAC_DACTIVATE_FLOWCTRL_WITH_3KB     0x1000
+#define GMAC_DACTIVATE_FLOWCTRL_WITH_4KB     0x1800
+#define GMAC_DACTIVATE_FLOWCTRL_WITH_5KB     0x400000
+#define GMAC_DACTIVATE_FLOWCTRL_WITH_6KB     0x400800
+#define GMAC_DACTIVATE_FLOWCTRL_WITH_7KB     0x401000
+
+#define GMAC_HW_FLOWCTRL_DISABLE         0x0
+#define PORT_LPI_ENABLE_STATUS           0x3
+#define PORT_LPI_TASK_RUNNING            0x10000
+#define PORT_LPI_TASK_START              0x20000
+#define PORT_MAX_FRAME_SIZE              0x3fff
+
+#endif
diff --git a/qca-ssdk/include/adpt/mp/adpt_mp_uniphy.h b/qca-ssdk/include/adpt/mp/adpt_mp_uniphy.h
new file mode 100755
index 0000000..1e20b71
--- /dev/null
+++ b/qca-ssdk/include/adpt/mp/adpt_mp_uniphy.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _ADPT_MP_UNIPHY_H_
+#define _ADPT_MP_UNIPHY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                         /* __cplusplus */
+
+void
+adpt_mp_gcc_uniphy_port_reset(a_uint32_t dev_id, a_uint32_t port_id);
+
+sw_error_t
+adpt_mp_gcc_uniphy_port_clock_set(a_uint32_t dev_id, a_uint32_t port_id,
+	a_bool_t enable);
+
+sw_error_t
+adpt_mp_uniphy_adapter_port_reset(a_uint32_t dev_id, a_uint32_t port_id);
+
+sw_error_t
+adpt_mp_uniphy_mode_configure(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode);
+
+#ifdef __cplusplus
+}
+#endif                         /* __cplusplus */
+#endif
diff --git a/qca-ssdk/include/adpt/sfp/adpt_sfp.h b/qca-ssdk/include/adpt/sfp/adpt_sfp.h
new file mode 100755
index 0000000..81cdf38
--- /dev/null
+++ b/qca-ssdk/include/adpt/sfp/adpt_sfp.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _ADPT_SFP_H_
+#define _ADPT_SFP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+sw_error_t adpt_sfp_init(a_uint32_t dev_id);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif
diff --git a/qca-ssdk/include/api/api_access.h b/qca-ssdk/include/api/api_access.h
new file mode 100755
index 0000000..78e9eb0
--- /dev/null
+++ b/qca-ssdk/include/api/api_access.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _API_ACCESS_H
+#define _API_ACCESS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+    sw_api_func_t *
+    sw_api_func_find(a_uint32_t api_id);
+
+    sw_api_param_t *
+    sw_api_param_find(a_uint32_t api_id);
+
+    a_uint32_t
+    sw_api_param_nums(a_uint32_t api_id);
+
+    sw_error_t
+    sw_api_get(sw_api_t *sw_api);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _API_ACCESS_H */
diff --git a/qca-ssdk/include/api/api_desc.h b/qca-ssdk/include/api/api_desc.h
new file mode 100755
index 0000000..388f454
--- /dev/null
+++ b/qca-ssdk/include/api/api_desc.h
@@ -0,0 +1,4771 @@
+/*
+ * Copyright (c) 2012, 2015-2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/*qca808x_start*/
+#ifndef _API_DESC_H_
+#define _API_DESC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#define SW_API_PT_DUPLEX_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_DUPLEX_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_DUPLEX_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_DUPLEX_GET, SW_DUPLEX, \
+		    sizeof(fal_port_duplex_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "duplex"),
+
+#define SW_API_PT_DUPLEX_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_DUPLEX_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_PT_DUPLEX_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_DUPLEX_SET, SW_DUPLEX, \
+		    sizeof(fal_port_duplex_t), SW_PARAM_IN, \
+		    "duplex"),
+
+#define SW_API_PT_SPEED_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_SPEED_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_SPEED_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_SPEED_GET, SW_SPEED, \
+		    sizeof(fal_port_speed_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "speed"),
+
+#define SW_API_PT_SPEED_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_SPEED_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_SPEED_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_SPEED_SET, SW_SPEED, \
+		    sizeof(fal_port_speed_t), SW_PARAM_IN, \
+		    "speed"),
+
+#define SW_API_PT_AN_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_AN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_AN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_AN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "autoneg"),
+
+
+#define SW_API_PT_AN_ENABLE_DESC \
+    SW_PARAM_DEF(SW_API_PT_AN_ENABLE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_AN_ENABLE, SW_UINT32, 4, SW_PARAM_IN, "Port No."),
+
+
+#define SW_API_PT_AN_RESTART_DESC \
+    SW_PARAM_DEF(SW_API_PT_AN_RESTART, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_AN_RESTART, SW_UINT32, 4, SW_PARAM_IN, "Port No."),
+
+#define SW_API_PT_AN_ADV_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_AN_ADV_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_AN_ADV_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_AN_ADV_GET, SW_CAP, 4, SW_PARAM_PTR|SW_PARAM_OUT, "autoneg"),
+
+#define SW_API_PT_AN_ADV_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_AN_ADV_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_AN_ADV_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_AN_ADV_SET, SW_CAP, 4, SW_PARAM_IN, "autoneg"),
+/*qca808x_end*/
+
+#define SW_API_PT_HDR_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_HDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_HDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_HDR_SET, SW_ENABLE, 4, SW_PARAM_IN, "Header"),
+
+#define SW_API_PT_HDR_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_HDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_HDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_HDR_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Header"),
+
+#define SW_API_PT_FLOWCTRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_FLOWCTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_FLOWCTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_FLOWCTRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Flow control"),
+
+#define SW_API_PT_FLOWCTRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_FLOWCTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_FLOWCTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_FLOWCTRL_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Flow control"),
+
+#define SW_API_PT_FLOWCTRL_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Force mode"),
+
+#define SW_API_PT_FLOWCTRL_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Force mode"),
+
+#define SW_API_PT_POWERSAVE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_POWERSAVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_POWERSAVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_POWERSAVE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Powersave Status"),
+
+#define SW_API_PT_POWERSAVE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_POWERSAVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_POWERSAVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_POWERSAVE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Powersave Status"),
+/*qca808x_start*/
+#define SW_API_PT_HIBERNATE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_HIBERNATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_HIBERNATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_HIBERNATE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Hibernate status"),
+
+#define SW_API_PT_HIBERNATE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_HIBERNATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_HIBERNATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_HIBERNATE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Hibernate Status"),
+
+#define SW_API_PT_CDT_DESC \
+    SW_PARAM_DEF(SW_API_PT_CDT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_CDT, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_CDT, SW_UINT32, 4, SW_PARAM_IN, "MDI Pair ID"), \
+    SW_PARAM_DEF(SW_API_PT_CDT, SW_CABLESTATUS, 4, SW_PARAM_PTR|SW_PARAM_OUT, "cable status"), \
+    SW_PARAM_DEF(SW_API_PT_CDT, SW_CABLELEN, 4, SW_PARAM_PTR|SW_PARAM_OUT, "cable len"),
+/*qca808x_end*/
+#define SW_API_PT_TXHDR_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_TXHDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_TXHDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_TXHDR_SET, SW_HDRMODE, \
+		    sizeof(fal_port_header_mode_t), \
+		    SW_PARAM_IN, "HdrMode"),
+
+#define SW_API_PT_TXHDR_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_TXHDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_TXHDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_TXHDR_GET, SW_HDRMODE, \
+		    sizeof(fal_port_header_mode_t), \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "HdrMode"),
+
+#define SW_API_PT_RXHDR_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_RXHDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_RXHDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_RXHDR_SET, SW_HDRMODE, \
+		    sizeof(fal_port_header_mode_t), \
+		    SW_PARAM_IN, "HdrMode"),
+
+#define SW_API_PT_RXHDR_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_RXHDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_RXHDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_RXHDR_GET, SW_HDRMODE, \
+		    sizeof(fal_port_header_mode_t), \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "HdrMode"),
+
+#define SW_API_HEADER_TYPE_SET_DESC \
+    SW_PARAM_DEF(SW_API_HEADER_TYPE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_HEADER_TYPE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), \
+    SW_PARAM_DEF(SW_API_HEADER_TYPE_SET, SW_UINT32, 4, SW_PARAM_IN, "Value"),
+
+#define SW_API_HEADER_TYPE_GET_DESC \
+    SW_PARAM_DEF(SW_API_HEADER_TYPE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_HEADER_TYPE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), \
+    SW_PARAM_DEF(SW_API_HEADER_TYPE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"),
+
+#define SW_API_TXMAC_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_TXMAC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_TXMAC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_TXMAC_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"),
+
+#define SW_API_TXMAC_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_TXMAC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_TXMAC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_TXMAC_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"),
+
+#define SW_API_RXMAC_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_RXMAC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_RXMAC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_RXMAC_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"),
+
+#define SW_API_RXMAC_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_RXMAC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_RXMAC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_RXMAC_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"),
+
+#define SW_API_TXFC_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_TXFC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_TXFC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_TXFC_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"),
+
+#define SW_API_TXFC_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_TXFC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_TXFC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_TXFC_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"),
+
+#define SW_API_RXFC_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_RXFC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_RXFC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_RXFC_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"),
+
+#define SW_API_RXFC_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_RXFC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_RXFC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_RXFC_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"),
+
+#define SW_API_BP_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_BP_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BP_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_BP_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"),
+
+#define SW_API_BP_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_BP_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BP_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_BP_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"),
+
+#define SW_API_PT_LINK_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_LINK_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_LINK_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_LINK_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"),
+
+#define SW_API_PT_LINK_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_LINK_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_LINK_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_LINK_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"),
+/*qca808x_start*/
+#define SW_API_PT_LINK_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_LINK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_LINK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_LINK_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+/*qca808x_end*/
+#define SW_API_PTS_LINK_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTS_LINK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTS_LINK_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_PT_MAC_LOOPBACK_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_PT_MAC_LOOPBACK_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_PT_CONGESTION_DROP_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"), \
+    SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_PT_CONGESTION_DROP_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"), \
+    SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_PT_RING_FLOW_CTRL_THRES_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_SET, SW_UINT32, 4, SW_PARAM_IN, "Ring ID"), \
+    SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_SET, SW_UINT8, 1, SW_PARAM_IN, "On Thres"), \
+    SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_SET, SW_UINT8, 1, SW_PARAM_IN, "Off Thres"),
+
+#define SW_API_PT_RING_FLOW_CTRL_THRES_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_GET, SW_UINT32, 4, SW_PARAM_IN, "Ring ID"), \
+    SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_GET, SW_UINT8, 1, SW_PARAM_PTR|SW_PARAM_OUT, "On Thres"), \
+    SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_GET, SW_UINT8, 1, SW_PARAM_PTR|SW_PARAM_OUT, "Off Thres"),
+/*qca808x_start*/
+#define SW_API_PT_8023AZ_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_8023AZ_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_8023AZ_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_8023AZ_SET, SW_ENABLE, 4, SW_PARAM_IN, "8023az Status"),
+
+#define SW_API_PT_8023AZ_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_8023AZ_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_8023AZ_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_8023AZ_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "8023az Status"),
+
+#define SW_API_PT_MDIX_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_MDIX_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_MDIX_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_MDIX_SET, SW_CROSSOVER_MODE, \
+		    sizeof(fal_port_mdix_mode_t), SW_PARAM_IN, "Crossover Mode"),
+
+
+#define SW_API_PT_MDIX_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_MDIX_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_MDIX_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_MDIX_GET, SW_CROSSOVER_MODE, \
+		    sizeof(fal_port_mdix_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Crossover Mode"),
+
+#define SW_API_PT_MDIX_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_MDIX_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_MDIX_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_MDIX_STATUS_GET, SW_CROSSOVER_STATUS, \
+		    sizeof(fal_port_mdix_status_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Crossover Status"),
+/*qca808x_end*/
+
+#define SW_API_PT_COMBO_PREFER_MEDIUM_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_SET, SW_PREFER_MEDIUM, \
+		    sizeof(fal_port_medium_t), SW_PARAM_IN, "Prefer Medium"),
+
+
+#define SW_API_PT_COMBO_PREFER_MEDIUM_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_GET, SW_PREFER_MEDIUM, \
+		    sizeof(fal_port_medium_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Prefer Medium"),
+
+#define SW_API_PT_COMBO_MEDIUM_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_COMBO_MEDIUM_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_COMBO_MEDIUM_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_COMBO_MEDIUM_STATUS_GET, SW_PREFER_MEDIUM, \
+		    sizeof(fal_port_medium_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Medium Type"),
+
+#define SW_API_PT_COMBO_FIBER_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_COMBO_FIBER_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_COMBO_FIBER_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_COMBO_FIBER_MODE_SET, SW_FIBER_MODE, \
+		    sizeof(fal_port_fiber_mode_t), SW_PARAM_IN, "Fbier Mode"),
+
+
+#define SW_API_PT_COMBO_FIBER_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_COMBO_FIBER_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_COMBO_FIBER_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_COMBO_FIBER_MODE_GET, SW_FIBER_MODE, \
+		    sizeof(fal_port_fiber_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Fiber Mode"),
+/*qca808x_start*/
+
+#define SW_API_PT_LOCAL_LOOPBACK_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_LOCAL_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_LOCAL_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_LOCAL_LOOPBACK_SET, SW_ENABLE, 4, \
+		    SW_PARAM_IN, "Local Loopback Status"),
+
+#define SW_API_PT_LOCAL_LOOPBACK_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_LOCAL_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_LOCAL_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_LOCAL_LOOPBACK_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Local Loopback Status"),
+
+#define SW_API_PT_REMOTE_LOOPBACK_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_REMOTE_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_REMOTE_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_REMOTE_LOOPBACK_SET, SW_ENABLE, 4, \
+		    SW_PARAM_IN, "Remote Loopback Status"),
+
+#define SW_API_PT_REMOTE_LOOPBACK_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_REMOTE_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_REMOTE_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_REMOTE_LOOPBACK_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Remote Loopback Status"),
+
+#define SW_API_PT_RESET_DESC \
+    SW_PARAM_DEF(SW_API_PT_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_RESET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),
+
+#define SW_API_PT_POWER_OFF_DESC \
+    SW_PARAM_DEF(SW_API_PT_POWER_OFF, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_POWER_OFF, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),
+
+#define SW_API_PT_POWER_ON_DESC \
+    SW_PARAM_DEF(SW_API_PT_POWER_ON, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_POWER_ON, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),
+
+#define SW_API_PT_MAGIC_FRAME_MAC_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_MAGIC_FRAME_MAC_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_MAGIC_FRAME_MAC_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_MAGIC_FRAME_MAC_SET, SW_MACADDR, \
+		    sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "[Magic mac]"),
+
+#define SW_API_PT_MAGIC_FRAME_MAC_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_MAGIC_FRAME_MAC_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_MAGIC_FRAME_MAC_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_MAGIC_FRAME_MAC_GET, SW_MACADDR, \
+		    sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "[Magic mac]"),
+
+#define SW_API_PT_PHY_ID_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_PHY_ID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_PHY_ID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_PHY_ID_GET, SW_UINT16, 2, SW_PARAM_PTR|SW_PARAM_OUT, "Org ID"), \
+    SW_PARAM_DEF(SW_API_PT_PHY_ID_GET, SW_UINT16, 2, SW_PARAM_PTR|SW_PARAM_OUT, "Rev ID"),
+
+#define SW_API_PT_WOL_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_WOL_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_WOL_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_WOL_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Wol Status"),
+
+#define SW_API_PT_WOL_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_WOL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_WOL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_WOL_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Wol Status"),
+/*qca808x_end*/
+
+#define SW_API_PT_INTERFACE_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_SET, SW_INTERFACE_MODE, \
+		    sizeof(fal_port_interface_mode_t), SW_PARAM_IN, "Interface Mode"),
+
+
+#define SW_API_PT_INTERFACE_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_GET, SW_INTERFACE_MODE, \
+		    sizeof(fal_port_interface_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Interface Mode"),
+#define SW_API_PT_INTERFACE_MODE_APPLY_DESC \
+		SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_APPLY, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+/*qca808x_start*/
+#define SW_API_PT_INTERFACE_MODE_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_STATUS_GET, SW_INTERFACE_MODE, \
+		    sizeof(fal_port_interface_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Interface Status"),
+
+#define SW_API_DEBUG_PHYCOUNTER_SET_DESC \
+    SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Counter Status"),
+
+#define SW_API_DEBUG_PHYCOUNTER_GET_DESC \
+    SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Counter Status"),
+
+#define SW_API_DEBUG_PHYCOUNTER_SHOW_DESC \
+    SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_SHOW, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_SHOW, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_SHOW, SW_COUNTER_INFO, \
+		    sizeof(fal_port_counter_info_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Phy Counter Statistics On Port"),
+/*qca808x_end*/
+
+#define SW_API_PT_MTU_SET_DESC \
+	SW_PARAM_DEF(SW_API_PT_MTU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+	SW_PARAM_DEF(SW_API_PT_MTU_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+	SW_PARAM_DEF(SW_API_PT_MTU_SET, SW_MTU_ENTRY, \
+		    sizeof(fal_mtu_ctrl_t), SW_PARAM_PTR|SW_PARAM_IN, "Port MTU"),
+
+#define SW_API_PT_MTU_GET_DESC \
+	SW_PARAM_DEF(SW_API_PT_MTU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+	SW_PARAM_DEF(SW_API_PT_MTU_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+	SW_PARAM_DEF(SW_API_PT_MTU_GET, SW_MTU_INFO, \
+		    sizeof(fal_mtu_ctrl_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Port MTU"),
+
+#define SW_API_PT_MRU_SET_DESC \
+	SW_PARAM_DEF(SW_API_PT_MRU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+	SW_PARAM_DEF(SW_API_PT_MRU_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+	SW_PARAM_DEF(SW_API_PT_MRU_SET, SW_MRU_ENTRY, \
+		    sizeof(fal_mru_ctrl_t), SW_PARAM_PTR|SW_PARAM_IN, "Port MRU"),
+
+#define SW_API_PT_MRU_GET_DESC \
+	SW_PARAM_DEF(SW_API_PT_MRU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+	SW_PARAM_DEF(SW_API_PT_MRU_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+	SW_PARAM_DEF(SW_API_PT_MRU_GET, SW_MRU_INFO, \
+		    sizeof(fal_mru_ctrl_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \
+		    "Port MRU"),
+
+#define SW_API_PT_SOURCE_FILTER_GET_DESC \
+	SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+	SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+	SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_GET, SW_ENABLE, 4, \
+			SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_PT_SOURCE_FILTER_SET_DESC \
+	SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+	SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+	SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_PT_FRAME_MAX_SIZE_GET_DESC \
+	SW_PARAM_DEF(SW_API_PT_FRAME_MAX_SIZE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+	SW_PARAM_DEF(SW_API_PT_FRAME_MAX_SIZE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+	SW_PARAM_DEF(SW_API_PT_FRAME_MAX_SIZE_GET, SW_UINT32, 4, \
+			SW_PARAM_PTR|SW_PARAM_OUT, "Frame Max Size"),
+
+#define SW_API_PT_FRAME_MAX_SIZE_SET_DESC \
+	SW_PARAM_DEF(SW_API_PT_FRAME_MAX_SIZE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+	SW_PARAM_DEF(SW_API_PT_FRAME_MAX_SIZE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+	SW_PARAM_DEF(SW_API_PT_FRAME_MAX_SIZE_SET, SW_UINT32, 4, \
+			SW_PARAM_IN, "Frame Max Size"),
+
+#define SW_API_PT_INTERFACE_3AZ_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_SET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_IN, "Status"),
+
+#define SW_API_PT_INTERFACE_3AZ_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_GET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_PT_PROMISC_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_PROMISC_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_PROMISC_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_PT_PROMISC_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_PT_PROMISC_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_PROMISC_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_PT_PROMISC_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_PT_PROMISC_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_PT_INTERFACE_EEE_CFG_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_EEE_CFG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_EEE_CFG_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_EEE_CFG_SET, SW_PORT_EEE_CONFIG, \
+		sizeof(fal_port_eee_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "EEE"),
+
+#define SW_API_PT_INTERFACE_EEE_CFG_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_EEE_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_EEE_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_INTERFACE_EEE_CFG_GET, SW_PORT_EEE_CONFIG, \
+		sizeof(fal_port_eee_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "EEE"),
+
+#define SW_API_PT_SOURCE_FILTER_CONFIG_GET_DESC \
+	SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+	SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+	SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_GET, SW_SRC_FILTER_CONFIG, \
+		sizeof(fal_src_filter_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "srcfilter config"),
+
+#define SW_API_PT_SOURCE_FILTER_CONFIG_SET_DESC \
+	SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+	SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+	SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_SET, SW_SRC_FILTER_CONFIG, \
+		sizeof(fal_src_filter_config_t), SW_PARAM_PTR|SW_PARAM_IN, "srcfilter config"),
+
+#define SW_API_PT_SWITCH_PORT_LOOPBACK_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_SET, SW_PORT_LOOPBACK_CONFIG, \
+        sizeof(fal_loopback_config_t), SW_PARAM_PTR|SW_PARAM_IN, "LOOPBACK"),
+
+#define SW_API_PT_SWITCH_PORT_LOOPBACK_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_GET, SW_PORT_LOOPBACK_CONFIG,\
+        sizeof(fal_loopback_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "LOOPBACK"),
+
+#define SW_API_VLAN_ADD_DESC \
+    SW_PARAM_DEF(SW_API_VLAN_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VLAN_ADD, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"),
+
+#define SW_API_VLAN_DEL_DESC \
+    SW_PARAM_DEF(SW_API_VLAN_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VLAN_DEL, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"),
+
+#define SW_API_VLAN_MEM_UPDATE_DESC \
+    SW_PARAM_DEF(SW_API_VLAN_MEM_UPDATE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VLAN_MEM_UPDATE, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"), \
+    SW_PARAM_DEF(SW_API_VLAN_MEM_UPDATE, SW_PBMP, \
+		    sizeof(fal_pbmp_t), SW_PARAM_IN, \
+		    "Member Port Map"), \
+    SW_PARAM_DEF(SW_API_VLAN_MEM_UPDATE, SW_PBMP, \
+		    sizeof(fal_pbmp_t), SW_PARAM_IN, \
+		    "U Member Port Map"),
+
+#define SW_API_VLAN_FIND_DESC \
+    SW_PARAM_DEF(SW_API_VLAN_FIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VLAN_FIND, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"), \
+    SW_PARAM_DEF(SW_API_VLAN_FIND, SW_VLAN, \
+		    sizeof(fal_vlan_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Vlan Entry"),
+
+#define SW_API_VLAN_NEXT_DESC \
+    SW_PARAM_DEF(SW_API_VLAN_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VLAN_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"), \
+    SW_PARAM_DEF(SW_API_VLAN_NEXT, SW_VLAN, \
+		    sizeof(fal_vlan_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Vlan Entry"),
+
+#define SW_API_VLAN_APPEND_DESC \
+    SW_PARAM_DEF(SW_API_VLAN_APPEND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VLAN_APPEND, SW_VLAN, \
+		    sizeof(fal_vlan_t), SW_PARAM_PTR|SW_PARAM_IN, "Vlan Entry"),
+
+#define SW_API_VLAN_FLUSH_DESC \
+    SW_PARAM_DEF(SW_API_VLAN_FLUSH, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#define SW_API_VLAN_FID_SET_DESC \
+    SW_PARAM_DEF(SW_API_VLAN_FID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_VLAN_FID_SET, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \
+    SW_PARAM_DEF(SW_API_VLAN_FID_SET, SW_UINT32, 4, SW_PARAM_IN, "FDB ID"),
+
+#define SW_API_VLAN_FID_GET_DESC \
+    SW_PARAM_DEF(SW_API_VLAN_FID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_VLAN_FID_GET, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \
+    SW_PARAM_DEF(SW_API_VLAN_FID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "FDB ID"),
+
+#define SW_API_VLAN_MEMBER_ADD_DESC \
+    SW_PARAM_DEF(SW_API_VLAN_MEMBER_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_VLAN_MEMBER_ADD, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \
+    SW_PARAM_DEF(SW_API_VLAN_MEMBER_ADD, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_VLAN_MEMBER_ADD, SW_EGMODE, \
+		    sizeof(fal_pt_1q_egmode_t), \
+		    SW_PARAM_IN, "Port Info"),
+
+#define SW_API_VLAN_MEMBER_DEL_DESC \
+    SW_PARAM_DEF(SW_API_VLAN_MEMBER_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_VLAN_MEMBER_DEL, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \
+    SW_PARAM_DEF(SW_API_VLAN_MEMBER_DEL, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),
+
+#define SW_API_VLAN_LEARN_STATE_SET_DESC \
+    SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \
+    SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_VLAN_LEARN_STATE_GET_DESC \
+    SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \
+    SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_LAN_WAN_CFG_SET_DESC \
+    SW_PARAM_DEF(SW_API_LAN_WAN_CFG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_LAN_WAN_CFG_SET, SW_LAN_WAN_CFG, sizeof(qca_lan_wan_cfg_t), \
+		    SW_PARAM_PTR|SW_PARAM_IN, "Vlan Lan Wan Configuration"),
+
+#define SW_API_LAN_WAN_CFG_GET_DESC \
+    SW_PARAM_DEF(SW_API_LAN_WAN_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_LAN_WAN_CFG_GET, SW_LAN_WAN_CFG, sizeof(qca_lan_wan_cfg_t), \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Vlan Lan Wan Configuration"),
+
+#define SW_API_PT_ING_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_ING_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_ING_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_ING_MODE_GET, SW_1QMODE, \
+		    sizeof(fal_pt_1qmode_t), \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "1qmode"),
+
+#define SW_API_PT_ING_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_ING_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_ING_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_ING_MODE_SET, SW_1QMODE, \
+		    sizeof(fal_pt_1qmode_t), \
+		    SW_PARAM_IN, "1qmode"),
+
+#define SW_API_PT_EG_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_EG_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_EG_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_EG_MODE_GET, SW_EGMODE, \
+		    sizeof(fal_pt_1q_egmode_t),\
+		    SW_PARAM_PTR|SW_PARAM_OUT, "egvlan"),
+
+#define SW_API_PT_EG_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_EG_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_EG_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_EG_MODE_SET, SW_EGMODE, \
+		    sizeof(fal_pt_1q_egmode_t),  \
+		    SW_PARAM_IN, "egvlan"),
+
+#define SW_API_PT_VLAN_MEM_ADD_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_MEM_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_VLAN_MEM_ADD, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_VLAN_MEM_ADD, SW_UINT32, 4, SW_PARAM_IN, "Member Port Id"),
+
+#define SW_API_PT_VLAN_MEM_DEL_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_MEM_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_VLAN_MEM_DEL, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_VLAN_MEM_DEL, SW_UINT32, 4, SW_PARAM_IN, "Member Port Id"),
+
+#define SW_API_PT_VLAN_MEM_UPDATE_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_MEM_UPDATE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_VLAN_MEM_UPDATE, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_VLAN_MEM_UPDATE, SW_PBMP, \
+		    sizeof(fal_pbmp_t), SW_PARAM_IN, \
+		    "Member Port Bitmap"),
+
+#define SW_API_PT_VLAN_MEM_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_MEM_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VLAN_MEM_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."),  \
+    SW_PARAM_DEF(SW_API_PT_VLAN_MEM_GET, SW_PBMP, \
+		    sizeof(fal_pbmp_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Member Port Bitmap"),
+
+#define SW_API_PT_DEF_VID_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_DEF_VID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_DEF_VID_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID."),  \
+    SW_PARAM_DEF(SW_API_PT_DEF_VID_SET, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"),
+
+#define SW_API_PT_DEF_VID_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_DEF_VID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_DEF_VID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID."),  \
+    SW_PARAM_DEF(SW_API_PT_DEF_VID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Vlan Id"),
+
+#define SW_API_PT_FORCE_DEF_VID_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),    \
+    SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_SET, SW_ENABLE, 4, SW_PARAM_IN, "Force"),
+
+#define SW_API_PT_FORCE_DEF_VID_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),    \
+    SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Force"),
+
+#define SW_API_PT_FORCE_PORTVLAN_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),    \
+    SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Force"),
+
+#define SW_API_PT_FORCE_PORTVLAN_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),    \
+    SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Force"),
+
+#define SW_API_PT_NESTVLAN_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_NESTVLAN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_NESTVLAN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_NESTVLAN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Nestvlan"),
+
+#define SW_API_PT_NESTVLAN_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_NESTVLAN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_NESTVLAN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),    \
+    SW_PARAM_DEF(SW_API_PT_NESTVLAN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Nestvlan"),
+
+#define SW_API_NESTVLAN_TPID_SET_DESC \
+    SW_PARAM_DEF(SW_API_NESTVLAN_TPID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_NESTVLAN_TPID_SET, SW_UINT32, 4, SW_PARAM_IN, "TPID"),
+
+#define SW_API_NESTVLAN_TPID_GET_DESC \
+    SW_PARAM_DEF(SW_API_NESTVLAN_TPID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_NESTVLAN_TPID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "TPID"),
+
+#define SW_API_PT_IN_VLAN_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_SET, SW_INVLAN, \
+		    sizeof(fal_pt_invlan_mode_t), SW_PARAM_IN, "Invlan"),
+
+#define SW_API_PT_IN_VLAN_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),    \
+    SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_GET, SW_INVLAN, \
+		    sizeof(fal_pt_invlan_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Invlan"),
+
+#define SW_API_PT_TLS_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_TLS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_TLS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),    \
+    SW_PARAM_DEF(SW_API_PT_TLS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_PT_TLS_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_TLS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_TLS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),    \
+    SW_PARAM_DEF(SW_API_PT_TLS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_PT_PRI_PROPAGATION_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_PT_PRI_PROPAGATION_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),    \
+    SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_PT_DEF_SVID_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_DEF_SVID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_DEF_SVID_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_DEF_SVID_SET, SW_UINT32, 4, SW_PARAM_IN, "svid"),
+
+#define SW_API_PT_DEF_SVID_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_DEF_SVID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_DEF_SVID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),    \
+    SW_PARAM_DEF(SW_API_PT_DEF_SVID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "svid"),
+
+#define SW_API_PT_DEF_CVID_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_DEF_CVID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_DEF_CVID_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_DEF_CVID_SET, SW_UINT32, 4, SW_PARAM_IN, "cvid"),
+
+#define SW_API_PT_DEF_CVID_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_DEF_CVID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_DEF_CVID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),    \
+    SW_PARAM_DEF(SW_API_PT_DEF_CVID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "cvid"),
+
+#define SW_API_PT_VLAN_PROPAGATION_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_SET, SW_VLANPROPAGATION, \
+		    sizeof(fal_vlan_propagation_mode_t), SW_PARAM_IN, "Vlan propagation"),
+
+#define SW_API_PT_VLAN_PROPAGATION_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_GET, SW_VLANPROPAGATION, \
+		    sizeof(fal_vlan_propagation_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Vlan propagation"),
+
+#define SW_API_PT_VLAN_TRANS_ADD_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADD, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADD, SW_VLANTRANSLATION, \
+		    sizeof(fal_vlan_trans_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Vlan Translation"),
+
+#define SW_API_PT_VLAN_TRANS_DEL_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_DEL, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_DEL, SW_VLANTRANSLATION, \
+		    sizeof(fal_vlan_trans_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Vlan Translation"),
+
+#define SW_API_PT_VLAN_TRANS_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_GET, SW_VLANTRANSLATION, \
+		    sizeof(fal_vlan_trans_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \
+		    "Vlan Translation"),
+
+#define SW_API_QINQ_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_QINQ_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_QINQ_MODE_SET, SW_QINQMODE, \
+		    sizeof(fal_qinq_mode_t), SW_PARAM_IN, "qinq mode"),
+
+#define SW_API_QINQ_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_QINQ_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_QINQ_MODE_GET, SW_QINQMODE, \
+		    sizeof(fal_qinq_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "qinq mode"),
+
+#define SW_API_PT_QINQ_ROLE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_SET, SW_QINQROLE, \
+		    sizeof(fal_qinq_port_role_t), SW_PARAM_IN, "qinq role"),
+
+#define SW_API_PT_QINQ_ROLE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),    \
+    SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_GET, SW_QINQROLE, \
+		    sizeof(fal_qinq_port_role_t), SW_PARAM_PTR|SW_PARAM_OUT, "qinq role"),
+
+#define SW_API_PT_VLAN_TRANS_ITERATE_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ITERATE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ITERATE, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ITERATE, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Iterator"),\
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ITERATE, SW_VLANTRANSLATION, \
+		    sizeof(fal_vlan_trans_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "Vlan Translation"),
+
+#define SW_API_PT_MAC_VLAN_XLT_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"),
+
+#define SW_API_PT_MAC_VLAN_XLT_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),    \
+    SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_NETISOLATE_SET_DESC \
+    SW_PARAM_DEF(SW_API_NETISOLATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_NETISOLATE_SET, SW_ENABLE, 4, SW_PARAM_IN, "enable"),
+
+#define SW_API_NETISOLATE_GET_DESC \
+    SW_PARAM_DEF(SW_API_NETISOLATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_NETISOLATE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "enable"),
+
+#define SW_API_EG_FLTR_BYPASS_EN_SET_DESC \
+    SW_PARAM_DEF(SW_API_EG_FLTR_BYPASS_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_EG_FLTR_BYPASS_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "enable"),
+
+#define SW_API_EG_FLTR_BYPASS_EN_GET_DESC \
+    SW_PARAM_DEF(SW_API_EG_FLTR_BYPASS_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_EG_FLTR_BYPASS_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "enable"),
+
+#define SW_API_PT_VRF_ID_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_VRF_ID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VRF_ID_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_VRF_ID_SET, SW_UINT32, 4, SW_PARAM_IN, "vrf_id"),
+
+#define SW_API_PT_VRF_ID_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_VRF_ID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VRF_ID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VRF_ID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "vrf_id"),
+
+#define SW_API_GLOBAL_QINQ_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_GLOBAL_QINQ_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_GLOBAL_QINQ_MODE_SET, SW_GLOBAL_QINQMODE, \
+		    sizeof(fal_global_qinq_mode_t), SW_PARAM_PTR|SW_PARAM_IN, "global qinq mode"),
+
+#define SW_API_GLOBAL_QINQ_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_GLOBAL_QINQ_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_GLOBAL_QINQ_MODE_GET, SW_GLOBAL_QINQMODE, \
+		    sizeof(fal_global_qinq_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "global qinq mode"),
+
+#define SW_API_PORT_QINQ_MODE_SET_DESC \
+    SW_PARAM_DEF( SW_API_PORT_QINQ_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF( SW_API_PORT_QINQ_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF( SW_API_PORT_QINQ_MODE_SET, SW_PT_QINQMODE, \
+		    sizeof(fal_port_qinq_role_t), SW_PARAM_PTR|SW_PARAM_IN, "port qinq mode"),
+
+#define SW_API_PORT_QINQ_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PORT_QINQ_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PORT_QINQ_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PORT_QINQ_MODE_GET, SW_PT_QINQMODE, \
+		    sizeof(fal_port_qinq_role_t), SW_PARAM_PTR|SW_PARAM_OUT, "port qinq mode"),
+
+#define SW_API_TPID_SET_DESC \
+    SW_PARAM_DEF(SW_API_TPID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_TPID_SET, SW_TPID, \
+		    sizeof(fal_tpid_t), SW_PARAM_PTR|SW_PARAM_IN, "ingress tpid"),
+
+#define SW_API_TPID_GET_DESC \
+    SW_PARAM_DEF(SW_API_TPID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_TPID_GET, SW_TPID, \
+		    sizeof(fal_tpid_t), SW_PARAM_PTR|SW_PARAM_OUT, "ingress tpid"),
+
+#define SW_API_EGRESS_TPID_SET_DESC \
+    SW_PARAM_DEF(SW_API_EGRESS_TPID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_EGRESS_TPID_SET, SW_TPID, \
+		    sizeof(fal_tpid_t), SW_PARAM_PTR|SW_PARAM_IN, "egress tpid"),
+
+#define SW_API_EGRESS_TPID_GET_DESC \
+    SW_PARAM_DEF(SW_API_EGRESS_TPID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_EGRESS_TPID_GET, SW_TPID, \
+		    sizeof(fal_tpid_t), SW_PARAM_PTR|SW_PARAM_OUT, "egress tpid"),
+
+#define SW_API_PT_INGRESS_VLAN_FILTER_SET_DESC \
+    SW_PARAM_DEF( SW_API_PT_INGRESS_VLAN_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF( SW_API_PT_INGRESS_VLAN_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF( SW_API_PT_INGRESS_VLAN_FILTER_SET, SW_INGRESS_FILTER, \
+		    sizeof(fal_ingress_vlan_filter_t), SW_PARAM_PTR|SW_PARAM_IN, \
+		    "ingress filter mode"),
+
+#define SW_API_PT_INGRESS_VLAN_FILTER_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_INGRESS_VLAN_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_INGRESS_VLAN_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_INGRESS_VLAN_FILTER_GET, SW_INGRESS_FILTER, \
+		    sizeof(fal_ingress_vlan_filter_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "ingress filter mode"),
+
+#define SW_API_PT_DEFAULT_VLANTAG_SET_DESC \
+    SW_PARAM_DEF( SW_API_PT_DEFAULT_VLANTAG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF( SW_API_PT_DEFAULT_VLANTAG_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF( SW_API_PT_DEFAULT_VLANTAG_SET, SW_PT_VLAN_DIRECTION, \
+		    sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \
+    SW_PARAM_DEF( SW_API_PT_DEFAULT_VLANTAG_SET, SW_PT_DEF_VID_EN, \
+		    sizeof(fal_port_default_vid_enable_t), SW_PARAM_PTR|SW_PARAM_IN, \
+		    "default vid en"), \
+    SW_PARAM_DEF( SW_API_PT_DEFAULT_VLANTAG_SET, SW_PT_VLAN_TAG, \
+		    sizeof(fal_port_vlan_tag_t), SW_PARAM_PTR|SW_PARAM_IN, "vlan tag"),
+
+#define SW_API_PT_DEFAULT_VLANTAG_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_DEFAULT_VLANTAG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_DEFAULT_VLANTAG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_DEFAULT_VLANTAG_GET, SW_PT_VLAN_DIRECTION, \
+		    sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \
+    SW_PARAM_DEF(SW_API_PT_DEFAULT_VLANTAG_GET, SW_PT_DEF_VID_EN, \
+		    sizeof(fal_port_default_vid_enable_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "default vid en"), \
+    SW_PARAM_DEF(SW_API_PT_DEFAULT_VLANTAG_GET, SW_PT_VLAN_TAG, \
+		    sizeof(fal_port_vlan_tag_t), SW_PARAM_PTR|SW_PARAM_OUT, "vlan tag"),
+
+#define SW_API_PT_TAG_PROPAGATION_SET_DESC \
+    SW_PARAM_DEF( SW_API_PT_TAG_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF( SW_API_PT_TAG_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF( SW_API_PT_TAG_PROPAGATION_SET, SW_PT_VLAN_DIRECTION, \
+		    sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \
+    SW_PARAM_DEF( SW_API_PT_TAG_PROPAGATION_SET, SW_TAG_PROPAGATION, \
+		    sizeof(fal_vlantag_propagation_t), SW_PARAM_PTR|SW_PARAM_IN, \
+		    "tag propagation"),
+
+#define SW_API_PT_TAG_PROPAGATION_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_TAG_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_TAG_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_TAG_PROPAGATION_GET, SW_PT_VLAN_DIRECTION, \
+		    sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \
+    SW_PARAM_DEF(SW_API_PT_TAG_PROPAGATION_GET, SW_TAG_PROPAGATION, \
+		    sizeof(fal_vlantag_propagation_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "tag propagation"),
+
+#define SW_API_PT_VLANTAG_EGMODE_SET_DESC \
+    SW_PARAM_DEF( SW_API_PT_VLANTAG_EGMODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF( SW_API_PT_VLANTAG_EGMODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF( SW_API_PT_VLANTAG_EGMODE_SET, SW_EGRESS_MODE, \
+		    sizeof(fal_vlantag_egress_mode_t), SW_PARAM_PTR|SW_PARAM_IN, "egress mode"),
+
+#define SW_API_PT_VLANTAG_EGMODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLANTAG_EGMODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VLANTAG_EGMODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_VLANTAG_EGMODE_GET, SW_EGRESS_MODE, \
+		    sizeof(fal_vlantag_egress_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "egress mode"),
+
+#define SW_API_PT_VLAN_XLT_MISS_CMD_SET_DESC \
+    SW_PARAM_DEF( SW_API_PT_VLAN_XLT_MISS_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF( SW_API_PT_VLAN_XLT_MISS_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF( SW_API_PT_VLAN_XLT_MISS_CMD_SET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "miss xlt cmd"),
+
+#define SW_API_PT_VLAN_XLT_MISS_CMD_GET_DESC \
+    SW_PARAM_DEF( SW_API_PT_VLAN_XLT_MISS_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF( SW_API_PT_VLAN_XLT_MISS_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF( SW_API_PT_VLAN_XLT_MISS_CMD_GET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "miss xlt cmd"),
+
+#define SW_API_PT_VSI_EGMODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_SET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_SET, SW_EGMODE, \
+		    sizeof(fal_pt_1q_egmode_t), SW_PARAM_IN, "Egress mode"),
+
+#define SW_API_PT_VSI_EGMODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_GET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_GET, SW_EGMODE, \
+		    sizeof(fal_pt_1q_egmode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Egress mode"),
+
+#define SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_PT_VLAN_TRANS_ADV_ADD_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_ADD, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_ADD, SW_PT_VLAN_DIRECTION, \
+		    sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_ADD, SW_PT_VLAN_TRANS_ADV_RULE, \
+		    sizeof(fal_vlan_trans_adv_rule_t), SW_PARAM_PTR|SW_PARAM_IN, \
+		    "vlan trans rule"), \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_ADD, SW_PT_VLAN_TRANS_ADV_ACTION, \
+		    sizeof(fal_vlan_trans_adv_action_t), SW_PARAM_PTR|SW_PARAM_IN, \
+		    "vlan trans action"),
+
+#define SW_API_PT_VLAN_TRANS_ADV_DEL_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_DEL, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_DEL, SW_PT_VLAN_DIRECTION, \
+		    sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_DEL, SW_PT_VLAN_TRANS_ADV_RULE, \
+		    sizeof(fal_vlan_trans_adv_rule_t), SW_PARAM_PTR|SW_PARAM_IN, \
+		    "vlan trans rule"), \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_DEL, SW_PT_VLAN_TRANS_ADV_ACTION, \
+		    sizeof(fal_vlan_trans_adv_action_t), SW_PARAM_PTR|SW_PARAM_IN, \
+		    "vlan trans action"),
+
+#define SW_API_PT_VLAN_TRANS_ADV_GETFIRST_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETFIRST, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETFIRST, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETFIRST, SW_PT_VLAN_DIRECTION, \
+		    sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETFIRST, SW_PT_VLAN_TRANS_ADV_RULE, \
+		    sizeof(fal_vlan_trans_adv_rule_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "vlan trans rule"), \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETFIRST, SW_PT_VLAN_TRANS_ADV_ACTION, \
+		    sizeof(fal_vlan_trans_adv_action_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "vlan trans action"),
+
+#define SW_API_PT_VLAN_TRANS_ADV_GETNEXT_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETNEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETNEXT, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETNEXT, SW_PT_VLAN_DIRECTION, \
+		    sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETNEXT, SW_PT_VLAN_TRANS_ADV_RULE, \
+		    sizeof(fal_vlan_trans_adv_rule_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \
+		    "vlan trans rule"), \
+    SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETNEXT, SW_PT_VLAN_TRANS_ADV_ACTION, \
+		    sizeof(fal_vlan_trans_adv_action_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \
+		    "vlan trans action"),
+
+#define SW_API_PT_VLAN_COUNTER_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VLAN_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Cnt Index"), \
+    SW_PARAM_DEF(SW_API_PT_VLAN_COUNTER_GET, SW_PT_VLAN_COUNTER, \
+		    sizeof(fal_port_vlan_counter_t), SW_PARAM_PTR|SW_PARAM_OUT, "enable"),
+
+#define SW_API_PT_VLAN_COUNTER_CLEANUP_DESC \
+    SW_PARAM_DEF(SW_API_PT_VLAN_COUNTER_CLEANUP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_PT_VLAN_COUNTER_CLEANUP, SW_UINT32, 4, SW_PARAM_IN, "Cnt Index"),
+
+#define SW_API_FDB_ADD_DESC \
+    SW_PARAM_DEF(SW_API_FDB_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_ADD, SW_FDBENTRY, \
+		    sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Entry"),
+
+#define SW_API_FDB_RFS_SET_DESC \
+		SW_PARAM_DEF(SW_API_FDB_RFS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+		SW_PARAM_DEF(SW_API_FDB_RFS_SET, SW_FDB_RFS, \
+		    sizeof(fal_fdb_rfs_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Rfs"),
+
+#define SW_API_FDB_RFS_DEL_DESC \
+		SW_PARAM_DEF(SW_API_FDB_RFS_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+		SW_PARAM_DEF(SW_API_FDB_RFS_DEL, SW_FDB_RFS, \
+		    sizeof(fal_fdb_rfs_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Rfs"),
+
+
+#define SW_API_FDB_DELALL_DESC \
+    SW_PARAM_DEF(SW_API_FDB_DELALL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_DELALL, SW_UINT32, 4, SW_PARAM_IN, "Flag"),
+
+#define SW_API_FDB_DELPORT_DESC \
+    SW_PARAM_DEF(SW_API_FDB_DELPORT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_DELPORT, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_FDB_DELPORT, SW_UINT32, 4, SW_PARAM_IN, "Flag"),
+
+#define SW_API_FDB_DELMAC_DESC \
+    SW_PARAM_DEF(SW_API_FDB_DELMAC, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_DELMAC, SW_FDBENTRY, \
+		    sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Entry"),
+
+#define SW_API_FDB_FIRST_DESC \
+    SW_PARAM_DEF(SW_API_FDB_FIRST, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_FIRST, SW_FDBENTRY, \
+		    sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "Fdb Entry"),
+
+#define SW_API_FDB_NEXT_DESC \
+    SW_PARAM_DEF(SW_API_FDB_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_NEXT, SW_FDBENTRY, \
+		    sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Fdb Entry"),
+
+#define SW_API_FDB_FIND_DESC \
+    SW_PARAM_DEF(SW_API_FDB_FIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_FIND, SW_FDBENTRY, \
+		    sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Fdb Entry"),
+
+#define SW_API_FDB_PT_LEARN_SET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_PT_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_LEARN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Learn"),
+
+#define SW_API_FDB_PT_LEARN_GET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_PT_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_LEARN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Learn"),
+
+#define SW_API_FDB_PT_NEWADDR_LEARN_SET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Learn Ctrl"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_SET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Action"),
+
+#define SW_API_FDB_PT_NEWADDR_LEARN_GET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Learn Ctrl"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_GET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Action"),
+
+#define SW_API_FDB_PT_STAMOVE_SET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Station Move"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_SET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Action"),
+
+#define SW_API_FDB_PT_STAMOVE_GET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Station Move"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_GET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Action"),
+
+#define SW_API_FDB_AGE_CTRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_AGE_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_AGE_CTRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Age"),
+
+#define SW_API_FDB_AGE_CTRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_AGE_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_AGE_CTRL_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Age"),
+
+#define SW_API_FDB_LEARN_CTRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_LEARN_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_LEARN_CTRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Learn Ctrl"),
+
+#define SW_API_FDB_LEARN_CTRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_LEARN_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_LEARN_CTRL_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Learn Ctrl"),
+
+#define SW_API_FDB_VLAN_IVL_SVL_SET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_VLAN_IVL_SVL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_VLAN_IVL_SVL_SET, SW_FDBSMODE, 4, SW_PARAM_IN, "Smode"),
+
+#define SW_API_FDB_VLAN_IVL_SVL_GET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_VLAN_IVL_SVL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_VLAN_IVL_SVL_GET, SW_FDBSMODE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Smode"),
+
+#define SW_API_FDB_AGE_TIME_SET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_AGE_TIME_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_AGE_TIME_SET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Time"),
+
+#define SW_API_FDB_AGE_TIME_GET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_AGE_TIME_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_AGE_TIME_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Time"),
+
+#define SW_API_FDB_ITERATE_DESC \
+    SW_PARAM_DEF(SW_API_FDB_ITERATE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_ITERATE, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Iterator"),\
+    SW_PARAM_DEF(SW_API_FDB_ITERATE, SW_FDBENTRY, \
+		    sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "Fdb Entry"),
+
+#define SW_API_FDB_EXTEND_NEXT_DESC \
+    SW_PARAM_DEF(SW_API_FDB_EXTEND_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_EXTEND_NEXT, SW_FDBOPRATION, \
+		    sizeof(fal_fdb_op_t), SW_PARAM_PTR|SW_PARAM_IN, "OperateOption"),\
+    SW_PARAM_DEF(SW_API_FDB_EXTEND_NEXT, SW_FDBENTRY, \
+		    sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Fdb Entry"),
+
+#define SW_API_FDB_EXTEND_FIRST_DESC \
+    SW_PARAM_DEF(SW_API_FDB_EXTEND_FIRST, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_EXTEND_FIRST, SW_FDBOPRATION, \
+		    sizeof(fal_fdb_op_t), SW_PARAM_PTR|SW_PARAM_IN, "OperateOption"),\
+    SW_PARAM_DEF(SW_API_FDB_EXTEND_FIRST, SW_FDBENTRY, \
+		    sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Fdb Entry"),
+
+#define SW_API_FDB_TRANSFER_DESC \
+    SW_PARAM_DEF(SW_API_FDB_TRANSFER, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_TRANSFER, SW_UINT32, 4, SW_PARAM_IN, "Old Port ID"),\
+    SW_PARAM_DEF(SW_API_FDB_TRANSFER, SW_UINT32, 4, SW_PARAM_IN, "New Port ID"),\
+    SW_PARAM_DEF(SW_API_FDB_TRANSFER, SW_UINT32, 4, SW_PARAM_IN, "FID"),\
+    SW_PARAM_DEF(SW_API_FDB_TRANSFER, SW_FDBOPRATION, \
+		    sizeof(fal_fdb_op_t), SW_PARAM_PTR|SW_PARAM_IN, "OperateOption"),
+
+#define SW_API_PT_FDB_LEARN_COUNTER_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_COUNTER_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "LearnCnt"),
+
+#define SW_API_PT_FDB_LEARN_LIMIT_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), \
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "LimitCnt"),
+
+#define SW_API_PT_FDB_LEARN_LIMIT_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), \
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "LimitCnt"),
+
+#define SW_API_PT_FDB_LEARN_EXCEED_CMD_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"),
+
+#define SW_API_PT_FDB_LEARN_EXCEED_CMD_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"),
+
+#define SW_API_FDB_LEARN_LIMIT_SET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), \
+    SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "LimitCnt"),
+
+#define SW_API_FDB_LEARN_LIMIT_GET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), \
+    SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "LimitCnt"),
+
+#define SW_API_FDB_LEARN_EXCEED_CMD_SET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"),
+
+#define SW_API_FDB_LEARN_EXCEED_CMD_GET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"),
+
+#define SW_API_FDB_RESV_ADD_DESC \
+    SW_PARAM_DEF(SW_API_FDB_RESV_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_RESV_ADD, SW_FDBENTRY, \
+		    sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Resv Entry"),
+
+#define SW_API_FDB_RESV_DEL_DESC \
+    SW_PARAM_DEF(SW_API_FDB_RESV_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_RESV_DEL, SW_FDBENTRY, \
+		    sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Resv Entry"),
+
+#define SW_API_FDB_RESV_FIND_DESC \
+    SW_PARAM_DEF(SW_API_FDB_RESV_FIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_RESV_FIND, SW_FDBENTRY, \
+		    sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \
+		    "Fdb Resv Entry"),
+
+#define SW_API_FDB_RESV_ITERATE_DESC \
+    SW_PARAM_DEF(SW_API_FDB_RESV_ITERATE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_RESV_ITERATE, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Iterator"),\
+    SW_PARAM_DEF(SW_API_FDB_RESV_ITERATE, SW_FDBENTRY, \
+		    sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "Fdb Resv Entry"),
+
+#define SW_API_FDB_PT_LEARN_STATIC_SET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, SW_ENABLE, 4, SW_PARAM_IN, "LearnStatic"),
+
+#define SW_API_FDB_PT_LEARN_STATIC_GET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "LearnStatic"),
+
+#define SW_API_FDB_PORT_ADD_DESC \
+    SW_PARAM_DEF(SW_API_FDB_PORT_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PORT_ADD, SW_UINT32, 4, SW_PARAM_IN, "FID"),\
+    SW_PARAM_DEF(SW_API_FDB_PORT_ADD, SW_MACADDR, \
+		    sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "Address"),\
+    SW_PARAM_DEF(SW_API_FDB_PORT_ADD, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),
+
+#define SW_API_FDB_PORT_DEL_DESC \
+    SW_PARAM_DEF(SW_API_FDB_PORT_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PORT_DEL, SW_UINT32, 4, SW_PARAM_IN, "FID"),\
+    SW_PARAM_DEF(SW_API_FDB_PORT_DEL, SW_MACADDR, \
+		    sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "Address"),\
+    SW_PARAM_DEF(SW_API_FDB_PORT_DEL, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),
+
+#define SW_API_FDB_PT_MACLIMIT_CTRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_SET, SW_MACLIMIT_CTRL, \
+		    sizeof(fal_maclimit_ctrl_t), SW_PARAM_PTR|SW_PARAM_IN, "MacLimit Ctrl"),
+
+#define SW_API_FDB_PT_MACLIMIT_CTRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_GET, SW_MACLIMIT_CTRL, \
+		    sizeof(fal_maclimit_ctrl_t), SW_PARAM_PTR|SW_PARAM_OUT, "MacLimit Ctrl"),
+
+#define SW_API_FDB_DEL_BY_FID_DESC \
+    SW_PARAM_DEF(SW_API_FDB_DEL_BY_FID, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_FDB_DEL_BY_FID, SW_UINT16, 2, SW_PARAM_IN, "FID"),\
+    SW_PARAM_DEF(SW_API_FDB_DEL_BY_FID, SW_UINT32, 4, SW_PARAM_IN, "Flag"),
+
+
+#define SW_API_ACL_LIST_CREAT_DESC \
+    SW_PARAM_DEF(SW_API_ACL_LIST_CREAT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_LIST_CREAT, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+    SW_PARAM_DEF(SW_API_ACL_LIST_CREAT, SW_UINT32, 4, SW_PARAM_IN, "List Priority"),
+
+#define SW_API_ACL_LIST_DESTROY_DESC \
+    SW_PARAM_DEF(SW_API_ACL_LIST_DESTROY, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_LIST_DESTROY, SW_UINT32, 4, SW_PARAM_IN, "List ID"),
+
+#define SW_API_ACL_RULE_ADD_DESC \
+    SW_PARAM_DEF(SW_API_ACL_RULE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_ADD, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Rule Number"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_ADD, SW_ACLRULE,  \
+		    sizeof(fal_acl_rule_t), SW_PARAM_PTR|SW_PARAM_IN, "Rule"),
+
+#define SW_API_ACL_RULE_DELETE_DESC \
+    SW_PARAM_DEF(SW_API_ACL_RULE_DELETE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_DELETE, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_DELETE, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_DELETE, SW_UINT32, 4, SW_PARAM_IN, "Rule Number"),
+
+#define SW_API_ACL_RULE_QUERY_DESC \
+    SW_PARAM_DEF(SW_API_ACL_RULE_QUERY, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_QUERY, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_QUERY, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_QUERY, SW_ACLRULE, \
+		    sizeof(fal_acl_rule_t), SW_PARAM_PTR|SW_PARAM_OUT, "Rule"),
+
+#define SW_API_ACL_LIST_BIND_DESC \
+    SW_PARAM_DEF(SW_API_ACL_LIST_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_LIST_BIND, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+    SW_PARAM_DEF(SW_API_ACL_LIST_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_LIST_BIND, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+    SW_PARAM_DEF(SW_API_ACL_LIST_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#define SW_API_ACL_LIST_UNBIND_DESC \
+    SW_PARAM_DEF(SW_API_ACL_LIST_UNBIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_LIST_UNBIND, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+    SW_PARAM_DEF(SW_API_ACL_LIST_UNBIND, SW_UINT32, 4, SW_PARAM_IN, "Direction"),\
+    SW_PARAM_DEF(SW_API_ACL_LIST_UNBIND, SW_UINT32, 4, SW_PARAM_IN, "Object Type"),\
+    SW_PARAM_DEF(SW_API_ACL_LIST_UNBIND, SW_UINT32, 4, SW_PARAM_IN, "Object Index"),
+
+#define SW_API_ACL_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_ACL_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"),
+
+#define SW_API_ACL_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_ACL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_ACL_LIST_DUMP_DESC \
+    SW_PARAM_DEF(SW_API_ACL_LIST_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#define SW_API_ACL_RULE_DUMP_DESC \
+    SW_PARAM_DEF(SW_API_ACL_RULE_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#define SW_API_ACL_PT_UDF_PROFILE_SET_DESC \
+    SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, SW_ACL_UDF_TYPE, \
+		    sizeof(fal_acl_udf_type_t), SW_PARAM_IN, "udf_type"),\
+    SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "udf_offset"),\
+    SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "udf_length"),
+
+#define SW_API_ACL_PT_UDF_PROFILE_GET_DESC \
+    SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, SW_ACL_UDF_TYPE, \
+		    sizeof(fal_acl_udf_type_t), SW_PARAM_IN, "udf_type"),\
+    SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "udf_offset"),\
+    SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "udf_length"),
+
+#define SW_API_ACL_RULE_ACTIVE_DESC \
+    SW_PARAM_DEF(SW_API_ACL_RULE_ACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_ACTIVE, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_ACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_ACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Rule Number"),
+
+#define SW_API_ACL_RULE_DEACTIVE_DESC \
+    SW_PARAM_DEF(SW_API_ACL_RULE_DEACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_DEACTIVE, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_DEACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_DEACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Rule Number"),
+
+#define SW_API_ACL_RULE_SRC_FILTER_STS_SET_DESC \
+    SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_ACL_RULE_SRC_FILTER_STS_GET_DESC \
+    SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\
+    SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_ACL_UDF_SET_DESC \
+    SW_PARAM_DEF(SW_API_ACL_UDF_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_UDF_SET, SW_ACL_UDF_PKT_TYPE, \
+		    sizeof(fal_acl_udf_pkt_type_t), SW_PARAM_IN, "udf_packet_type"),\
+    SW_PARAM_DEF(SW_API_ACL_UDF_SET, SW_UINT32, 4, SW_PARAM_IN, "udf_index"),\
+    SW_PARAM_DEF(SW_API_ACL_UDF_SET, SW_ACL_UDF_TYPE, \
+		    sizeof(fal_acl_udf_type_t), SW_PARAM_IN, "udf_type"),\
+    SW_PARAM_DEF(SW_API_ACL_UDF_SET, SW_UINT32, 4, SW_PARAM_IN, "udf_offset"),
+
+#define SW_API_ACL_UDF_GET_DESC \
+    SW_PARAM_DEF(SW_API_ACL_UDF_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_ACL_UDF_GET, SW_ACL_UDF_PKT_TYPE, \
+		    sizeof(fal_acl_udf_pkt_type_t), SW_PARAM_IN, "udf_packet_type"),\
+    SW_PARAM_DEF(SW_API_ACL_UDF_GET, SW_UINT32, 4, SW_PARAM_IN, "udf_index"),\
+    SW_PARAM_DEF(SW_API_ACL_UDF_GET, SW_ACL_UDF_TYPE, \
+		    sizeof(fal_acl_udf_type_t), SW_PARAM_PTR|SW_PARAM_OUT, "udf_type"),\
+    SW_PARAM_DEF(SW_API_ACL_UDF_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "udf_offset"),
+
+#define SW_API_QOS_SCH_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_SCH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_SCH_MODE_SET, SW_SCH, \
+		    sizeof(fal_sch_mode_t), SW_PARAM_IN, "Schedule mode"),\
+    SW_PARAM_DEF(SW_API_QOS_SCH_MODE_SET, SW_UINT_A, 16, SW_PARAM_PTR|SW_PARAM_IN, "Weight"),
+
+#define SW_API_QOS_SCH_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_SCH_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_SCH_MODE_GET, SW_SCH, \
+		    sizeof(fal_sch_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Schedule mode"),\
+    SW_PARAM_DEF(SW_API_QOS_SCH_MODE_GET, SW_UINT_A, 16, SW_PARAM_PTR|SW_PARAM_OUT, "Weight"),
+
+#define SW_API_QOS_QU_TX_BUF_ST_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, SW_ENABLE, 4, SW_PARAM_IN, "Buffer limit"),
+
+#define SW_API_QOS_QU_TX_BUF_ST_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Buffer limit"),
+
+#define SW_API_QOS_QU_TX_BUF_NR_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Buffer Number"),
+
+#define SW_API_QOS_QU_TX_BUF_NR_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Buffer Number"),
+
+#define SW_API_QOS_PT_TX_BUF_ST_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, SW_ENABLE, 4, SW_PARAM_IN, "Buffer limit"),
+
+#define SW_API_QOS_PT_TX_BUF_ST_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Buffer limit"),
+
+#define SW_API_QOS_PT_RED_EN_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "enable"),
+
+#define SW_API_QOS_PT_RED_EN_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "enable"),
+
+#define SW_API_QOS_PT_TX_BUF_NR_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Buffer Number"),
+
+#define SW_API_QOS_PT_TX_BUF_NR_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Buffer Number"),
+
+#define SW_API_QOS_PT_RX_BUF_NR_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Buffer Number"),
+
+#define SW_API_QOS_PT_RX_BUF_NR_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Buffer Number"),
+
+#define SW_API_QOS_PORT_GROUP_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PORT_GROUP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_GROUP_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_GROUP_SET, SW_PORTGROUP, \
+		    sizeof(fal_qos_group_t), SW_PARAM_PTR|SW_PARAM_IN, "PortGroup"),
+
+#define SW_API_QOS_PORT_GROUP_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PORT_GROUP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_GROUP_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_GROUP_GET, SW_PORTGROUP, \
+		    sizeof(fal_qos_group_t), SW_PARAM_PTR|SW_PARAM_OUT, "PortGroup"),
+
+#define SW_API_QOS_PORT_PRI_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PORT_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_PRI_SET, SW_PORTPRI, \
+		    sizeof(fal_qos_pri_precedence_t), SW_PARAM_PTR|SW_PARAM_IN, "PortPri"),
+
+#define SW_API_QOS_PORT_PRI_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PORT_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_PRI_GET, SW_PORTPRI, \
+		    sizeof(fal_qos_pri_precedence_t), SW_PARAM_PTR|SW_PARAM_OUT, "PortPri"),
+
+#define SW_API_QOS_PORT_REMARK_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PORT_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_REMARK_SET, SW_PORTREMARK, \
+		    sizeof(fal_qos_remark_enable_t), SW_PARAM_PTR|SW_PARAM_IN, "PortRemark"),
+
+#define SW_API_QOS_PORT_REMARK_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PORT_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_REMARK_GET, SW_PORTREMARK, \
+		    sizeof(fal_qos_remark_enable_t), SW_PARAM_PTR|SW_PARAM_OUT, "PortRemark"),
+
+#define SW_API_QOS_PCP_MAP_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PCP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PCP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Group ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PCP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "PCP"),\
+    SW_PARAM_DEF(SW_API_QOS_PCP_MAP_SET, SW_COSMAP, \
+		    sizeof(fal_qos_cosmap_t), SW_PARAM_PTR|SW_PARAM_IN, "Cosmap"),
+
+#define SW_API_QOS_PCP_MAP_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PCP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PCP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Group ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PCP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "PCP"),\
+    SW_PARAM_DEF(SW_API_QOS_PCP_MAP_GET, SW_COSMAP, \
+		    sizeof(fal_qos_cosmap_t), SW_PARAM_PTR|SW_PARAM_OUT, "Cosmap"),
+
+#define SW_API_QOS_FLOW_MAP_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Group ID"),\
+    SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Flow"),\
+    SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_SET, SW_COSMAP, \
+		    sizeof(fal_qos_cosmap_t), SW_PARAM_PTR|SW_PARAM_IN, "Cosmap"),
+
+#define SW_API_QOS_FLOW_MAP_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Group ID"),\
+    SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Flow"),\
+    SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_GET, SW_COSMAP, \
+		    sizeof(fal_qos_cosmap_t), SW_PARAM_PTR|SW_PARAM_OUT, "Cosmap"),
+
+#define SW_API_QOS_DSCP_MAP_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Group ID"),\
+    SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dscp"),\
+    SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_SET, SW_COSMAP, \
+		    sizeof(fal_qos_cosmap_t), SW_PARAM_PTR|SW_PARAM_IN, "Cosmap"),
+
+#define SW_API_QOS_DSCP_MAP_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Group ID"),\
+    SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dscp"),\
+    SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_GET, SW_COSMAP, \
+		    sizeof(fal_qos_cosmap_t), SW_PARAM_PTR|SW_PARAM_OUT, "Cosmap"),
+
+#define SW_API_QOS_QUEUE_SCHEDULER_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_SET, SW_UINT32, 4, SW_PARAM_IN, "Node ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_SET, SW_UINT32, 4, SW_PARAM_IN, "Level"),\
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_SET, SW_SCHEDULER, \
+		    sizeof(fal_qos_scheduler_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "Scheduler"),
+
+#define SW_API_QOS_QUEUE_SCHEDULER_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_GET, SW_UINT32, 4, SW_PARAM_IN, "Node ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_GET, SW_UINT32, 4, SW_PARAM_IN, "Level"),\
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_GET, SW_SCHEDULER, \
+		    sizeof(fal_qos_scheduler_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "Scheduler"),
+
+#define SW_API_QOS_RING_QUEUE_MAP_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Ring ID"),\
+    SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_SET, SW_QUEUEBMP, \
+		    sizeof(fal_queue_bmp_t), SW_PARAM_PTR|SW_PARAM_IN, "Queue bmp"),
+
+#define SW_API_QOS_RING_QUEUE_MAP_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Ring ID"),\
+    SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_GET, SW_QUEUEBMP, \
+		    sizeof(fal_queue_bmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "Queue bmp"),
+
+#define SW_API_QOS_PORT_SCHEDULER_CFG_RESET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PORT_SCHEDULER_CFG_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_SCHEDULER_CFG_RESET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),
+
+#define SW_API_QOS_RING_QUEUE_MAP_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Ring ID"),\
+    SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_GET, SW_QUEUEBMP, \
+		    sizeof(fal_queue_bmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "Queue bmp"),
+
+#define SW_API_QOS_PORT_QUEUES_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PORT_QUEUES_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_QUEUES_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_QUEUES_GET, SW_QUEUEBMP, \
+		    sizeof(fal_queue_bmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "Queue bmp"),
+
+#define SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "queue ID"), \
+    SW_PARAM_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_IN, "dequeue en"),
+
+#define SW_API_QOS_SCHEDULER_DEQUEU_CTRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "queue ID"), \
+    SW_PARAM_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_GET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "dequeue en"),
+
+#define SW_API_QOS_PORT_SCHEDULER_RESOURCE_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PORT_SCHEDULER_RESOURCE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QOS_PORT_SCHEDULER_RESOURCE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_QOS_PORT_SCHEDULER_RESOURCE_GET, SW_RESOURCE_SCHE, \
+		    sizeof(fal_portscheduler_resource_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "scheduler resource"),
+
+#define SW_API_COSMAP_UP_QU_SET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_COSMAP_UP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"),\
+    SW_PARAM_DEF(SW_API_COSMAP_UP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue"),
+
+#define SW_API_COSMAP_UP_QU_GET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_COSMAP_UP_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"),\
+    SW_PARAM_DEF(SW_API_COSMAP_UP_QU_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Queue"),
+
+#define SW_API_COSMAP_DSCP_QU_SET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"),\
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue"),
+
+#define SW_API_COSMAP_DSCP_QU_GET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"),\
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Queue"),
+
+#define SW_API_QOS_PT_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_SET, SW_QOS, \
+		    sizeof(fal_qos_mode_t), SW_PARAM_IN, "Qos mode"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_QOS_PT_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_GET, SW_QOS, \
+		    sizeof(fal_qos_mode_t), SW_PARAM_IN, "Qos mode"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_QOS_PT_MODE_PRI_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_SET, SW_QOS, \
+		    sizeof(fal_qos_mode_t), SW_PARAM_IN, "Qos mode"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"),
+
+#define SW_API_QOS_PT_MODE_PRI_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_GET, SW_QOS, \
+		    sizeof(fal_qos_mode_t), SW_PARAM_IN, "Qos mode"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Priority"),
+
+#define SW_API_QOS_PORT_DEF_UP_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_SET, SW_UINT32, 4, SW_PARAM_IN, "default up"),
+
+#define SW_API_QOS_PORT_DEF_UP_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "default up"),
+
+#define SW_API_QOS_PORT_SCH_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_SET, SW_SCH, \
+		    sizeof(fal_sch_mode_t), SW_PARAM_IN, "Schedule mode"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_SET, SW_UINT_A, 24, SW_PARAM_PTR|SW_PARAM_IN, "Weight"),
+
+#define SW_API_QOS_PORT_SCH_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_GET, SW_SCH, \
+		    sizeof(fal_sch_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Schedule mode"),\
+    SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_GET, SW_UINT_A, 24, SW_PARAM_PTR|SW_PARAM_OUT, "Weight"),
+
+#define SW_API_QOS_PT_DEF_SPRI_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "default spri"),
+
+#define SW_API_QOS_PT_DEF_SPRI_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "default spri"),
+
+#define SW_API_QOS_PT_DEF_CPRI_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "default cpri"),
+
+
+#define SW_API_QOS_PT_FORCE_SPRI_ST_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_QOS_PT_FORCE_SPRI_ST_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_QOS_PT_FORCE_CPRI_ST_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_QOS_PT_FORCE_CPRI_ST_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+
+
+#define SW_API_QOS_PT_DEF_CPRI_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "default cpri"),
+
+
+#define SW_API_QOS_QUEUE_REMARK_SET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Table ID"), \
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_QOS_QUEUE_REMARK_GET_DESC \
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Table ID"), \
+    SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+
+
+
+#define SW_API_PT_IGMPS_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "IGMP snooping"),
+
+#define SW_API_PT_IGMPS_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "IGMP snooping"),
+
+#define SW_API_IGMP_MLD_CMD_SET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_MLD_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_MLD_CMD_SET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"),
+
+#define SW_API_IGMP_MLD_CMD_GET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_MLD_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_MLD_CMD_GET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"),
+
+#define SW_API_IGMP_PT_JOIN_SET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Join"),
+
+#define SW_API_IGMP_PT_JOIN_GET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Join"),
+
+#define SW_API_IGMP_PT_LEAVE_SET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Leave"),
+
+#define SW_API_IGMP_PT_LEAVE_GET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Leave"),
+
+#define SW_API_IGMP_RP_SET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_RP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_RP_SET, SW_PBMP, \
+		    sizeof(fal_pbmp_t), SW_PARAM_IN, "Ports"),
+
+#define SW_API_IGMP_RP_GET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_RP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_RP_GET, SW_PBMP, \
+		    sizeof(fal_pbmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "Ports"),
+
+#define SW_API_IGMP_ENTRY_CREAT_SET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_CREAT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_CREAT_SET, SW_ENABLE, 4, SW_PARAM_IN, "creat Entry"),
+
+#define SW_API_IGMP_ENTRY_CREAT_GET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_CREAT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_CREAT_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "creat Entry"),
+
+#define SW_API_IGMP_ENTRY_STATIC_SET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_STATIC_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_STATIC_SET, SW_ENABLE, 4, SW_PARAM_IN, "static"),
+
+#define SW_API_IGMP_ENTRY_STATIC_GET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_STATIC_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_STATIC_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "static"),
+
+#define SW_API_IGMP_ENTRY_LEAKY_SET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, SW_ENABLE, 4, SW_PARAM_IN, "leaky"),
+
+#define SW_API_IGMP_ENTRY_LEAKY_GET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "leaky"),
+
+#define SW_API_IGMP_ENTRY_V3_SET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_V3_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_V3_SET, SW_ENABLE, 4, SW_PARAM_IN, "version3"),
+
+#define SW_API_IGMP_ENTRY_V3_GET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_V3_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_V3_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "version3"),
+
+#define SW_API_IGMP_ENTRY_QUEUE_SET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, SW_ENABLE, 4, SW_PARAM_IN, "queue"), \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, SW_UINT32, 4, SW_PARAM_IN, "queue_id"),
+
+#define SW_API_IGMP_ENTRY_QUEUE_GET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "queue"), \
+    SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "queue_id"),
+
+#define SW_API_PT_IGMP_LEARN_LIMIT_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), \
+    SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "LimitCnt"),
+
+#define SW_API_PT_IGMP_LEARN_LIMIT_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), \
+    SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "LimitCnt"),
+
+#define SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"),
+
+#define SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"),
+
+#define SW_API_IGMP_SG_ENTRY_SET_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_SET, SW_SGENTRY, \
+		    sizeof(fal_igmp_sg_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "entry"),
+
+#define SW_API_IGMP_SG_ENTRY_CLEAR_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_CLEAR, SW_SGENTRY, \
+		    sizeof(fal_igmp_sg_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "entry"),
+
+#define SW_API_IGMP_SG_ENTRY_QUERY_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_QUERY, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_QUERY, SW_SGINFOENTRY, \
+		    sizeof(fal_igmp_sg_info_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "info"),
+
+#define SW_API_IGMP_SG_ENTRY_SHOW_DESC \
+    SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_SHOW, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+
+
+
+#define SW_API_UC_LEAKY_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_UC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_UC_LEAKY_MODE_SET, SW_LEAKY, \
+		    sizeof(fal_leaky_ctrl_mode_t), SW_PARAM_IN, "Uc Leaky mode"),
+
+#define SW_API_UC_LEAKY_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_UC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_UC_LEAKY_MODE_GET, SW_LEAKY, \
+		    sizeof(fal_leaky_ctrl_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Uc Leaky mode"),
+
+#define SW_API_MC_LEAKY_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_MC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MC_LEAKY_MODE_SET, SW_LEAKY, \
+		    sizeof(fal_leaky_ctrl_mode_t), SW_PARAM_IN, "Mc Leaky mode"),
+
+#define SW_API_MC_LEAKY_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_MC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MC_LEAKY_MODE_GET, SW_LEAKY, \
+		    sizeof(fal_leaky_ctrl_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Mc Leaky mode"),
+
+#define SW_API_ARP_LEAKY_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Arp leaky"),
+
+#define SW_API_ARP_LEAKY_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Arp leaky"),
+
+#define SW_API_PT_UC_LEAKY_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Port Unicast leaky"),
+
+#define SW_API_PT_UC_LEAKY_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Port Uc leaky"),
+
+#define SW_API_PT_MC_LEAKY_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Port Multicast leaky"),
+
+#define SW_API_PT_MC_LEAKY_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Port Mc leaky"),
+
+
+
+#define SW_API_MIRROR_ANALY_PT_SET_DESC \
+    SW_PARAM_DEF(SW_API_MIRROR_ANALY_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MIRROR_ANALY_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),
+
+#define SW_API_MIRROR_ANALY_PT_GET_DESC \
+    SW_PARAM_DEF(SW_API_MIRROR_ANALY_PT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MIRROR_ANALY_PT_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Port ID"),
+
+#define SW_API_MIRROR_IN_PT_SET_DESC \
+    SW_PARAM_DEF(SW_API_MIRROR_IN_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MIRROR_IN_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_MIRROR_IN_PT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Ingerss mirror"),
+
+#define SW_API_MIRROR_IN_PT_GET_DESC \
+    SW_PARAM_DEF(SW_API_MIRROR_IN_PT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MIRROR_IN_PT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_MIRROR_IN_PT_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Ingeress mirror"),
+
+#define SW_API_MIRROR_EG_PT_SET_DESC \
+    SW_PARAM_DEF(SW_API_MIRROR_EG_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MIRROR_EG_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_MIRROR_EG_PT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Egerss mirror"),
+
+#define SW_API_MIRROR_EG_PT_GET_DESC \
+    SW_PARAM_DEF(SW_API_MIRROR_EG_PT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MIRROR_EG_PT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_MIRROR_EG_PT_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Egeress mirror"),
+
+#define SW_API_MIRROR_ANALYSIS_CONFIG_SET_DESC \
+    SW_PARAM_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_SET, SW_MIRR_DIRECTION, \
+		    sizeof(fal_mirr_direction_t), SW_PARAM_IN, "Direction"), \
+    SW_PARAM_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_SET, SW_MIRR_ANALYSIS_CONFIG, \
+		    sizeof(fal_mirr_analysis_config_t), SW_PARAM_PTR|SW_PARAM_IN, "Config"),
+
+#define SW_API_MIRROR_ANALYSIS_CONFIG_GET_DESC \
+    SW_PARAM_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_GET, SW_MIRR_DIRECTION, \
+		    sizeof(fal_mirr_direction_t), SW_PARAM_IN, "Direction"), \
+    SW_PARAM_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_GET, SW_MIRR_ANALYSIS_CONFIG, \
+		    sizeof(fal_mirr_analysis_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "Config"),
+
+#define SW_API_RSS_HASH_CONFIG_SET_DESC \
+    SW_PARAM_DEF(SW_API_RSS_HASH_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_RSS_HASH_CONFIG_SET, SW_RSS_HASH_MODE, \
+		    sizeof(fal_rss_hash_mode_t), SW_PARAM_IN, "Mode"), \
+    SW_PARAM_DEF(SW_API_RSS_HASH_CONFIG_SET, SW_RSS_HASH_CONFIG, \
+		    sizeof(fal_rss_hash_config_t), SW_PARAM_PTR|SW_PARAM_IN, "Config"),
+
+#define SW_API_RSS_HASH_CONFIG_GET_DESC \
+    SW_PARAM_DEF(SW_API_RSS_HASH_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_RSS_HASH_CONFIG_GET, SW_RSS_HASH_MODE, \
+		    sizeof(fal_rss_hash_mode_t), SW_PARAM_IN, "Mode"), \
+    SW_PARAM_DEF(SW_API_RSS_HASH_CONFIG_GET, SW_RSS_HASH_CONFIG, \
+		    sizeof(fal_rss_hash_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "Config"),
+
+#define SW_API_RATE_QU_EGRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_QU_EGRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_QU_EGRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_QU_EGRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+    SW_PARAM_DEF(SW_API_RATE_QU_EGRL_SET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Speed"),\
+    SW_PARAM_DEF(SW_API_RATE_QU_EGRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Rate limit"),
+
+#define SW_API_RATE_QU_EGRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_QU_EGRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_QU_EGRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_QU_EGRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+    SW_PARAM_DEF(SW_API_RATE_QU_EGRL_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Speed"),\
+    SW_PARAM_DEF(SW_API_RATE_QU_EGRL_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Rate limit"),
+
+#define SW_API_RATE_PT_EGRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_PT_EGRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_EGRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_EGRL_SET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Speed"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_EGRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Rate limit"),
+
+#define SW_API_RATE_PT_EGRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_PT_EGRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_EGRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_EGRL_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Speed"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_EGRL_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Rate limit"),
+
+#define SW_API_RATE_PT_INRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_PT_INRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_INRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_INRL_SET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Speed"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_INRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Rate limit"),
+
+#define SW_API_RATE_PT_INRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_PT_INRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_INRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_INRL_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Speed"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_INRL_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Rate limit"),
+
+#define SW_API_STORM_CTRL_FRAME_SET_DESC \
+    SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_SET, SW_STORM, \
+		    sizeof(fal_storm_type_t), SW_PARAM_IN, "Frame type"),\
+    SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_SET, SW_ENABLE, 4, SW_PARAM_IN, "strom contrl"),
+
+#define SW_API_STORM_CTRL_FRAME_GET_DESC \
+    SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_GET, SW_STORM, \
+		    sizeof(fal_storm_type_t), SW_PARAM_IN, "Frame type"),\
+    SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "strom contrl"),
+
+#define SW_API_STORM_CTRL_RATE_SET_DESC \
+    SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_SET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Speed"),
+
+#define SW_API_STORM_CTRL_RATE_GET_DESC \
+    SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Speed"),
+
+#define SW_API_RATE_PORT_POLICER_SET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_SET, SW_INGPOLICER, \
+		    sizeof(fal_port_policer_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \
+		    "Policer"),
+
+#define SW_API_RATE_PORT_POLICER_GET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_GET, SW_INGPOLICER, \
+		    sizeof(fal_port_policer_t), SW_PARAM_PTR|SW_PARAM_OUT, "Policer"),
+
+#define SW_API_RATE_PORT_SHAPER_SET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"), \
+    SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_SET, SW_EGSHAPER, \
+		    sizeof(fal_egress_shaper_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Shaper"),
+
+#define SW_API_RATE_PORT_SHAPER_GET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), \
+    SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_GET, SW_EGSHAPER, \
+		    sizeof(fal_egress_shaper_t), SW_PARAM_PTR|SW_PARAM_OUT, "Shaper"),
+
+#define SW_API_RATE_QUEUE_SHAPER_SET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+    SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), \
+    SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_SET, SW_EGSHAPER, \
+		    sizeof(fal_egress_shaper_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Shaper"),
+
+#define SW_API_RATE_QUEUE_SHAPER_GET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+    SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), \
+    SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_GET, SW_EGSHAPER, \
+		    sizeof(fal_egress_shaper_t), SW_PARAM_PTR|SW_PARAM_OUT, "Shaper"),
+
+#define SW_API_RATE_ACL_POLICER_SET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_SET, SW_UINT32, 4, SW_PARAM_IN, "Policer ID"),\
+    SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_SET, SW_ACLPOLICER, \
+		    sizeof(fal_acl_policer_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Policer"),
+
+#define SW_API_RATE_ACL_POLICER_GET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_GET, SW_UINT32, 4, SW_PARAM_IN, "Policer ID"),\
+    SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_GET, SW_ACLPOLICER, \
+		    sizeof(fal_acl_policer_t), SW_PARAM_PTR|SW_PARAM_OUT, "Policer"),
+
+#define SW_API_RATE_PT_ADDRATEBYTE_SET_DESC\
+    SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, SW_UINT32, 4, SW_PARAM_IN, "AddRateByte"),
+
+#define SW_API_RATE_PT_ADDRATEBYTE_GET_DESC\
+    SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "AddRateByte"),
+
+#define SW_API_RATE_PT_GOL_FLOW_EN_SET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_RATE_PT_GOL_FLOW_EN_GET_DESC \
+    SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_STP_PT_STATE_SET_DESC \
+    SW_PARAM_DEF(SW_API_STP_PT_STATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_STP_PT_STATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Spaning tree ID"),\
+    SW_PARAM_DEF(SW_API_STP_PT_STATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_STP_PT_STATE_SET, SW_STP, \
+		    sizeof(fal_stp_state_t), SW_PARAM_IN, "Port State"),
+
+#define SW_API_STP_PT_STATE_GET_DESC \
+    SW_PARAM_DEF(SW_API_STP_PT_STATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_STP_PT_STATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Spaning tree ID"),\
+    SW_PARAM_DEF(SW_API_STP_PT_STATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+    SW_PARAM_DEF(SW_API_STP_PT_STATE_GET, SW_STP, \
+		    sizeof(fal_stp_state_t), SW_PARAM_PTR|SW_PARAM_OUT, "Port State"),
+
+
+
+
+#define SW_API_PT_MIB_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_MIB_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_MIB_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_MIB_GET, SW_MIB, \
+		    sizeof(fal_mib_info_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+              "MIB info"),
+#define SW_API_PT_XGMIB_GET_DESC \
+   SW_PARAM_DEF(SW_API_PT_XGMIB_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+   SW_PARAM_DEF(SW_API_PT_XGMIB_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+   SW_PARAM_DEF(SW_API_PT_XGMIB_GET, SW_XGMIB, \
+		    sizeof(fal_xgmib_info_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+				  "XGMIB info"),
+
+#define SW_API_MIB_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_MIB_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MIB_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "MIB status"),
+
+#define SW_API_MIB_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_MIB_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MIB_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "MIB status"),
+
+#define SW_API_PT_MIB_FLUSH_COUNTERS_DESC\
+    SW_PARAM_DEF(SW_API_PT_MIB_FLUSH_COUNTERS, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_MIB_FLUSH_COUNTERS, SW_UINT32, 4, SW_PARAM_IN, "Port No."),
+
+#define SW_API_MIB_CPU_KEEP_SET_DESC \
+    SW_PARAM_DEF(SW_API_MIB_CPU_KEEP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MIB_CPU_KEEP_SET, SW_ENABLE, 4, SW_PARAM_IN, "CPU_KEEP Set"),
+
+#define SW_API_MIB_CPU_KEEP_GET_DESC \
+    SW_PARAM_DEF(SW_API_MIB_CPU_KEEP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MIB_CPU_KEEP_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "CPU_KEEP Get"),
+
+#define SW_API_PT_MIB_COUNTER_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_MIB_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_MIB_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+    SW_PARAM_DEF(SW_API_PT_MIB_COUNTER_GET, SW_MIB_CNTR, \
+		    sizeof(fal_mib_counter_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+              "MIB Counter"),
+
+
+
+#define SW_API_ARP_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_ARP_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_ARP_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "ARP acknowledge"),
+
+#define SW_API_ARP_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_ARP_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_ARP_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "ARP acknowledge"),
+
+#define SW_API_FRAME_MAX_SIZE_SET_DESC \
+    SW_PARAM_DEF(SW_API_FRAME_MAX_SIZE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FRAME_MAX_SIZE_SET, SW_UINT32, 4, SW_PARAM_IN, "Frame Size"),
+
+#define SW_API_FRAME_MAX_SIZE_GET_DESC \
+    SW_PARAM_DEF(SW_API_FRAME_MAX_SIZE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FRAME_MAX_SIZE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Frame Size"),
+
+#define SW_API_PT_UNK_SA_CMD_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_SET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Forwarding"),
+
+#define SW_API_PT_UNK_SA_CMD_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_GET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Forwarding"),
+
+#define SW_API_PT_UNK_UC_FILTER_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Filter"),
+
+#define SW_API_PT_UNK_UC_FILTER_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Filter"),
+
+#define SW_API_PT_UNK_MC_FILTER_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Filter"),
+
+#define SW_API_PT_UNK_MC_FILTER_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Filter"),
+
+#define SW_API_PT_BC_FILTER_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_BC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_BC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_BC_FILTER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Filter"),
+
+#define SW_API_PT_BC_FILTER_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_BC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_BC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_BC_FILTER_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Filter"),
+
+#define SW_API_CPU_PORT_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_CPU_PORT_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_CPU_PORT_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Cpu port"),
+
+#define SW_API_CPU_PORT_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_CPU_PORT_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_CPU_PORT_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Cpu port"),
+
+#define SW_API_BC_TO_CPU_PORT_SET_DESC \
+    SW_PARAM_DEF(SW_API_BC_TO_CPU_PORT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BC_TO_CPU_PORT_SET, SW_ENABLE, 4, SW_PARAM_IN, "ToCpu"),
+
+#define SW_API_BC_TO_CPU_PORT_GET_DESC \
+    SW_PARAM_DEF(SW_API_BC_TO_CPU_PORT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BC_TO_CPU_PORT_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "ToCpu"),
+
+#define SW_API_PPPOE_CMD_SET_DESC \
+    SW_PARAM_DEF(SW_API_PPPOE_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_CMD_SET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Forwarding"),
+
+#define SW_API_PPPOE_CMD_GET_DESC \
+    SW_PARAM_DEF(SW_API_PPPOE_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_CMD_GET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Forwarding"),
+
+#define SW_API_PPPOE_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_PPPOE_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "PPPOE"),
+
+#define SW_API_PPPOE_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_PPPOE_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "PPPOE"),
+
+#define SW_API_PT_DHCP_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_DHCP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_DHCP_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_DHCP_SET, SW_ENABLE, 4, SW_PARAM_IN, "DHCP"),
+
+#define SW_API_PT_DHCP_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_DHCP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_DHCP_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_DHCP_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "DHCP"),
+
+#define SW_API_ARP_CMD_SET_DESC \
+    SW_PARAM_DEF(SW_API_ARP_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_ARP_CMD_SET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"),
+
+#define SW_API_ARP_CMD_GET_DESC \
+    SW_PARAM_DEF(SW_API_ARP_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_ARP_CMD_GET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"),
+
+#define SW_API_EAPOL_CMD_SET_DESC \
+    SW_PARAM_DEF(SW_API_EAPOL_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_EAPOL_CMD_SET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"),
+
+#define SW_API_EAPOL_CMD_GET_DESC \
+    SW_PARAM_DEF(SW_API_EAPOL_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_EAPOL_CMD_GET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"),
+
+#define SW_API_PPPOE_SESSION_ADD_DESC \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_ADD, SW_UINT32, 4, SW_PARAM_IN, "Session ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_ADD, SW_ENABLE, 4, SW_PARAM_IN, "StripHdr"),
+
+#define SW_API_PPPOE_SESSION_DEL_DESC \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_DEL, SW_UINT32, 4, SW_PARAM_IN, "Session ID"),
+
+#define SW_API_PPPOE_SESSION_GET_DESC \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_GET, SW_UINT32, 4, SW_PARAM_IN, "Session ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "StripHdr"),
+
+#define SW_API_EAPOL_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_EAPOL_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_EAPOL_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_EAPOL_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_EAPOL_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_EAPOL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_EAPOL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_EAPOL_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_RIPV1_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_RIPV1_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_RIPV1_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_RIPV1_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_RIPV1_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_RIPV1_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_PT_ARP_REQ_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "ARP Req acknowledge"),
+
+#define SW_API_PT_ARP_REQ_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "ARP Req acknowledge"),
+
+#define SW_API_PT_ARP_ACK_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "ARP Ack acknowledge"),
+
+#define SW_API_PT_ARP_ACK_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "ARP Ack acknowledge"),
+
+#define SW_API_PPPOE_SESSION_TABLE_ADD_DESC \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, SW_PPPOE,  \
+		    sizeof(fal_pppoe_session_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Session"),
+
+#define SW_API_PPPOE_SESSION_TABLE_DEL_DESC \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, SW_PPPOE,  \
+		    sizeof(fal_pppoe_session_t), SW_PARAM_PTR|SW_PARAM_IN, "Session"),
+
+#define SW_API_PPPOE_SESSION_TABLE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_GET, SW_PPPOE,  \
+		    sizeof(fal_pppoe_session_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Session"),
+
+#define SW_API_PPPOE_SESSION_ID_SET_DESC \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_SET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_SET, SW_UINT32, 4, SW_PARAM_IN, "ID"),
+
+#define SW_API_PPPOE_SESSION_ID_GET_DESC \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_GET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \
+    SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "ID"),
+
+#define SW_API_INTR_MASK_SET_DESC \
+    SW_PARAM_DEF(SW_API_INTR_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_INTR_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Mask"),
+
+#define SW_API_INTR_MASK_GET_DESC \
+    SW_PARAM_DEF(SW_API_INTR_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_INTR_MASK_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Mask"),
+
+#define SW_API_INTR_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_INTR_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_INTR_STATUS_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_INTR_STATUS_CLEAR_DESC \
+    SW_PARAM_DEF(SW_API_INTR_STATUS_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_INTR_STATUS_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Status"),
+
+#define SW_API_INTR_PORT_LINK_MASK_SET_DESC \
+    SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Mask"),
+
+#define SW_API_INTR_PORT_LINK_MASK_GET_DESC \
+    SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Mask"),
+
+#define SW_API_INTR_PORT_LINK_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_INTR_MASK_MAC_LINKCHG_SET_DESC \
+    SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_INTR_MASK_MAC_LINKCHG_GET_DESC \
+    SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_INTR_STATUS_MAC_LINKCHG_GET_DESC \
+    SW_PARAM_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_GET, SW_PBMP, \
+		    sizeof(fal_pbmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "Intr Port Bitmap"),
+
+#define SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR_DESC \
+    SW_PARAM_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#define SW_API_CPU_VID_EN_SET_DESC \
+    SW_PARAM_DEF(SW_API_CPU_VID_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_CPU_VID_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Cpu vid"),
+
+#define SW_API_CPU_VID_EN_GET_DESC \
+    SW_PARAM_DEF(SW_API_CPU_VID_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_CPU_VID_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Cpu vid"),
+
+#define SW_API_RTD_PPPOE_EN_SET_DESC \
+    SW_PARAM_DEF(SW_API_RTD_PPPOE_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_RTD_PPPOE_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "RTD PPPoE"),
+
+#define SW_API_RTD_PPPOE_EN_GET_DESC \
+    SW_PARAM_DEF(SW_API_RTD_PPPOE_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_RTD_PPPOE_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "RTD PPPoE"),
+
+#define SW_API_PPPOE_EN_SET_DESC \
+    SW_PARAM_DEF(SW_API_PPPOE_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "L3 Interface"), \
+    SW_PARAM_DEF(SW_API_PPPOE_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_PPPOE_EN_GET_DESC \
+    SW_PARAM_DEF(SW_API_PPPOE_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PPPOE_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "L3 Interface"), \
+    SW_PARAM_DEF(SW_API_PPPOE_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_GLOBAL_MACADDR_SET_DESC \
+    SW_PARAM_DEF(SW_API_GLOBAL_MACADDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_GLOBAL_MACADDR_SET, SW_MACADDR, \
+		    sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "[Macaddr]:"),
+
+#define SW_API_GLOBAL_MACADDR_GET_DESC \
+    SW_PARAM_DEF(SW_API_GLOBAL_MACADDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_GLOBAL_MACADDR_GET, SW_MACADDR, \
+		    sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "[Macaddr]:"),
+
+#define SW_API_LLDP_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_LLDP_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_LLDP_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "LLDP"),
+
+#define SW_API_LLDP_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_LLDP_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_LLDP_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "LLDP"),
+
+#define SW_API_FRAME_CRC_RESERVE_SET_DESC \
+    SW_PARAM_DEF(SW_API_FRAME_CRC_RESERVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FRAME_CRC_RESERVE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_FRAME_CRC_RESERVE_GET_DESC \
+    SW_PARAM_DEF(SW_API_FRAME_CRC_RESERVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FRAME_CRC_RESERVE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_DEBUG_PORT_COUNTER_ENABLE_DESC \
+    SW_PARAM_DEF(SW_API_DEBUG_PORT_COUNTER_ENABLE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_DEBUG_PORT_COUNTER_ENABLE, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_DEBUG_PORT_COUNTER_ENABLE, SW_DEBUG_COUNTER_EN, \
+		    sizeof(fal_counter_en_t), SW_PARAM_PTR|SW_PARAM_IN, "enable"),
+
+#define SW_API_DEBUG_PORT_COUNTER_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_DEBUG_PORT_COUNTER_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),    \
+    SW_PARAM_DEF(SW_API_DEBUG_PORT_COUNTER_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),   \
+    SW_PARAM_DEF(SW_API_DEBUG_PORT_COUNTER_STATUS_GET, SW_DEBUG_COUNTER_EN, \
+		    sizeof(fal_counter_en_t), SW_PARAM_PTR|SW_PARAM_OUT, "enable"),
+
+#define SW_API_LED_PATTERN_SET_DESC \
+    SW_PARAM_DEF(SW_API_LED_PATTERN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_LED_PATTERN_SET, SW_UINT32, 4, SW_PARAM_IN, "Pattern Group"),\
+    SW_PARAM_DEF(SW_API_LED_PATTERN_SET, SW_UINT32, 4, SW_PARAM_IN, "Pattern ID"),\
+    SW_PARAM_DEF(SW_API_LED_PATTERN_SET, SW_LEDPATTERN, \
+		    sizeof(led_ctrl_pattern_t), SW_PARAM_PTR|SW_PARAM_IN, "Pattern"),
+
+#define SW_API_LED_PATTERN_GET_DESC \
+    SW_PARAM_DEF(SW_API_LED_PATTERN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_LED_PATTERN_GET, SW_UINT32, 4, SW_PARAM_IN, "Pattern Group"),\
+    SW_PARAM_DEF(SW_API_LED_PATTERN_GET, SW_UINT32, 4, SW_PARAM_IN, "Pattern ID"),\
+    SW_PARAM_DEF(SW_API_LED_PATTERN_GET, SW_LEDPATTERN, \
+		    sizeof(led_ctrl_pattern_t), SW_PARAM_PTR|SW_PARAM_OUT, "Pattern"),
+
+/*qca808x_start*/
+#define SW_API_PHY_GET_DESC \
+    SW_PARAM_DEF(SW_API_PHY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_PHY_GET, SW_UINT32, 4, SW_PARAM_IN, "Phy ID"),\
+    SW_PARAM_DEF(SW_API_PHY_GET, SW_UINT32, 4, SW_PARAM_IN, "Reg ID"),\
+    SW_PARAM_DEF(SW_API_PHY_GET, SW_UINT16, 2, SW_PARAM_PTR|SW_PARAM_OUT, "Data"),
+
+
+#define SW_API_PHY_SET_DESC \
+    SW_PARAM_DEF(SW_API_PHY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_PHY_SET, SW_UINT32, 4, SW_PARAM_IN, "Phy ID"),\
+    SW_PARAM_DEF(SW_API_PHY_SET, SW_UINT32, 4, SW_PARAM_IN, "Reg ID"),\
+    SW_PARAM_DEF(SW_API_PHY_SET, SW_UINT16, 2, SW_PARAM_IN, "Data"),
+/*qca808x_end*/
+
+#define SW_API_REG_GET_DESC \
+    SW_PARAM_DEF(SW_API_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\
+    SW_PARAM_DEF(SW_API_REG_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Data"),\
+    SW_PARAM_DEF(SW_API_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"),
+
+#define SW_API_REG_SET_DESC \
+    SW_PARAM_DEF(SW_API_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\
+    SW_PARAM_DEF(SW_API_REG_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "Data"),\
+    SW_PARAM_DEF(SW_API_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"),
+
+#define SW_API_PSGMII_REG_GET_DESC \
+    SW_PARAM_DEF(SW_API_PSGMII_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_PSGMII_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\
+    SW_PARAM_DEF(SW_API_PSGMII_REG_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Data"),\
+    SW_PARAM_DEF(SW_API_PSGMII_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"),
+
+#define SW_API_PSGMII_REG_SET_DESC \
+    SW_PARAM_DEF(SW_API_PSGMII_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_PSGMII_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\
+    SW_PARAM_DEF(SW_API_PSGMII_REG_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "Data"),\
+    SW_PARAM_DEF(SW_API_PSGMII_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"),
+
+#define SW_API_REG_FIELD_GET_DESC \
+    SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\
+    SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_IN, "Bit Offset"),\
+    SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_IN, "Field Len"),\
+    SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Data"),\
+    SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"),
+
+#define SW_API_REG_FIELD_SET_DESC \
+    SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\
+    SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_IN, "Bit Offset"),\
+    SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_IN, "Field Len"),\
+    SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "Data"),\
+    SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"),
+
+#define SW_API_REG_DUMP_DESC \
+    SW_PARAM_DEF(SW_API_REG_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_REG_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Register group idx"), \
+    SW_PARAM_DEF(SW_API_REG_DUMP, SW_REG_DUMP, \
+		    sizeof(fal_reg_dump_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Register dump"),
+
+#define SW_API_DBG_REG_DUMP_DESC \
+    SW_PARAM_DEF(SW_API_DBG_REG_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_DBG_REG_DUMP, SW_DBG_REG_DUMP, \
+		    sizeof(fal_debug_reg_dump_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Debug Register dump"),
+
+#define SW_API_DBG_PSGMII_SELF_TEST_DESC \
+    SW_PARAM_DEF(SW_API_DBG_PSGMII_SELF_TEST, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_DBG_PSGMII_SELF_TEST, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_IN, "enable"),\
+    SW_PARAM_DEF(SW_API_DBG_PSGMII_SELF_TEST, SW_UINT32, 4, SW_PARAM_IN, "times"),\
+    SW_PARAM_DEF(SW_API_DBG_PSGMII_SELF_TEST, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_PHY_DUMP_DESC \
+	SW_PARAM_DEF(SW_API_PHY_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+	SW_PARAM_DEF(SW_API_PHY_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Phy ID"),\
+	SW_PARAM_DEF(SW_API_PHY_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Register group idx"), \
+	SW_PARAM_DEF(SW_API_PHY_DUMP, SW_PHY_DUMP, \
+		    sizeof(fal_phy_dump_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "PHY dump"),
+
+
+#define SW_API_UNIPHY_REG_GET_DESC \
+    SW_PARAM_DEF(SW_API_UNIPHY_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_UNIPHY_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Reg Index"),\
+    SW_PARAM_DEF(SW_API_UNIPHY_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\
+    SW_PARAM_DEF(SW_API_UNIPHY_REG_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Data"),\
+    SW_PARAM_DEF(SW_API_UNIPHY_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"),
+
+#define SW_API_UNIPHY_REG_SET_DESC \
+    SW_PARAM_DEF(SW_API_UNIPHY_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_UNIPHY_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Reg Index"),\
+    SW_PARAM_DEF(SW_API_UNIPHY_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\
+    SW_PARAM_DEF(SW_API_UNIPHY_REG_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "Data"),\
+    SW_PARAM_DEF(SW_API_UNIPHY_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"),
+
+#define SW_API_COSMAP_DSCP_TO_PRI_SET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"),     \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"),
+
+#define SW_API_COSMAP_DSCP_TO_PRI_GET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"),    \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Priority"),
+
+#define SW_API_COSMAP_DSCP_TO_DP_SET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"),     \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "DP"),
+
+#define SW_API_COSMAP_DSCP_TO_DP_GET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"),    \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "DP"),
+
+#define SW_API_COSMAP_UP_TO_PRI_SET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"),     \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"),
+
+#define SW_API_COSMAP_UP_TO_PRI_GET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"),    \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Priority"),
+
+#define SW_API_COSMAP_UP_TO_DP_SET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"),     \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "DP"),
+
+#define SW_API_COSMAP_UP_TO_DP_GET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"),    \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "DP"),
+
+#define SW_API_COSMAP_DSCP_TO_EHPRI_SET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"),     \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"),
+
+#define SW_API_COSMAP_DSCP_TO_EHPRI_GET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"),    \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Priority"),
+
+#define SW_API_COSMAP_DSCP_TO_EHDP_SET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHDP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHDP_SET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"),     \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHDP_SET, SW_UINT32, 4, SW_PARAM_IN, "DP"),
+
+#define SW_API_COSMAP_DSCP_TO_EHDP_GET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHDP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHDP_GET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"),    \
+    SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHDP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "DP"),
+
+#define SW_API_COSMAP_UP_TO_EHPRI_SET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"),     \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"),
+
+#define SW_API_COSMAP_UP_TO_EHPRI_GET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"),    \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHPRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Priority"),
+
+#define SW_API_COSMAP_UP_TO_EHDP_SET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHDP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHDP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"),     \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHDP_SET, SW_UINT32, 4, SW_PARAM_IN, "DP"),
+
+#define SW_API_COSMAP_UP_TO_EHDP_GET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHDP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHDP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"),    \
+    SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHDP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "DP"),
+
+#define SW_API_COSMAP_PRI_TO_QU_SET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), \
+    SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue"),
+
+#define SW_API_COSMAP_PRI_TO_QU_GET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), \
+    SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Queue"),
+
+#define SW_API_COSMAP_PRI_TO_EHQU_SET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), \
+    SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue"),
+
+#define SW_API_COSMAP_PRI_TO_EHQU_GET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), \
+    SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Queue"),
+
+#define SW_API_COSMAP_EG_REMARK_SET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Table ID"), \
+    SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_SET, SW_REMARKENTRY, \
+		    sizeof(fal_egress_remark_table_t), SW_PARAM_IN|SW_PARAM_PTR, "Table Entry"),
+
+#define SW_API_COSMAP_EG_REMARK_GET_DESC \
+    SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Table ID"), \
+    SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_GET, SW_REMARKENTRY, \
+		    sizeof(fal_egress_remark_table_t), SW_PARAM_OUT|SW_PARAM_PTR, "Table Entry"),
+
+
+
+#define SW_API_SEC_NORM_SET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_NORM_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_NORM_SET, SW_UINT32, 4, SW_PARAM_IN, "NormItem"), \
+    SW_PARAM_DEF(SW_API_SEC_NORM_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_NORM_GET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_NORM_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_NORM_GET, SW_UINT32, 4, SW_PARAM_IN, "NormItem"), \
+    SW_PARAM_DEF(SW_API_SEC_NORM_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_MAC_SET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_MAC_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_MAC_SET, SW_SEC_MAC, 4, SW_PARAM_IN, "MAC related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_MAC_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_MAC_GET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_MAC_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_MAC_GET, SW_SEC_MAC, 4, SW_PARAM_IN, "MAC related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_MAC_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_IP_SET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_IP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_IP_SET, SW_SEC_IP, 4, SW_PARAM_IN, "IP related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_IP_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_IP_GET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_IP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_IP_GET, SW_SEC_IP, 4, SW_PARAM_IN, "IP related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_IP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_IP4_SET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_IP4_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_IP4_SET, SW_SEC_IP4, 4, SW_PARAM_IN, "IP4 related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_IP4_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_IP4_GET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_IP4_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_IP4_GET, SW_SEC_IP4, 4, SW_PARAM_IN, "IP4 related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_IP4_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_IP6_SET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_IP6_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_IP6_SET, SW_SEC_IP6, 4, SW_PARAM_IN, "IP6 related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_IP6_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_IP6_GET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_IP6_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_IP6_GET, SW_SEC_IP6, 4, SW_PARAM_IN, "IP6 related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_IP6_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_TCP_SET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_TCP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_TCP_SET, SW_SEC_TCP, 4, SW_PARAM_IN, "TCP related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_TCP_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_TCP_GET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_TCP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_TCP_GET, SW_SEC_TCP, 4, SW_PARAM_IN, "TCP related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_TCP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_UDP_SET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_UDP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_UDP_SET, SW_SEC_UDP, 4, SW_PARAM_IN, "UDP related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_UDP_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_UDP_GET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_UDP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_UDP_GET, SW_SEC_UDP, 4, SW_PARAM_IN, "UDP related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_UDP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_ICMP4_SET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_ICMP4_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_ICMP4_SET, SW_SEC_ICMP4, 4, \
+		    SW_PARAM_IN, "ICMP4 related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_ICMP4_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_ICMP4_GET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_ICMP4_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_ICMP4_GET, SW_SEC_ICMP4, 4, \
+		    SW_PARAM_IN, "ICMP4 related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_ICMP4_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_ICMP6_SET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_ICMP6_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_ICMP6_SET, SW_SEC_ICMP6, 4, \
+		    SW_PARAM_IN, "ICMP6 related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_ICMP6_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_ICMP6_GET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_ICMP6_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_ICMP6_GET, SW_SEC_ICMP6, 4, \
+		    SW_PARAM_IN, "ICMP6 related normalized item"), \
+    SW_PARAM_DEF(SW_API_SEC_ICMP6_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_L3_PARSER_CTRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_L3_PARSER_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_L3_PARSER_CTRL_GET, SW_L3_PARSER, \
+		    sizeof(fal_l3_excep_parser_ctrl), SW_PARAM_PTR|SW_PARAM_OUT, "L3Parser"),
+
+#define SW_API_SEC_L3_PARSER_CTRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_L3_PARSER_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_L3_PARSER_CTRL_SET, SW_L3_PARSER, \
+		    sizeof(fal_l3_excep_parser_ctrl), SW_PARAM_PTR|SW_PARAM_IN, "L3Parser"),
+
+#define SW_API_SEC_L4_PARSER_CTRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_L4_PARSER_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_L4_PARSER_CTRL_GET, SW_L4_PARSER, \
+		    sizeof(fal_l4_excep_parser_ctrl), SW_PARAM_PTR|SW_PARAM_OUT, "L4Parser"),
+
+#define SW_API_SEC_L4_PARSER_CTRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_L4_PARSER_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_L4_PARSER_CTRL_SET, SW_L4_PARSER, \
+		    sizeof(fal_l4_excep_parser_ctrl), SW_PARAM_PTR|SW_PARAM_IN, "L4Parser"),
+
+#define SW_API_SEC_EXP_CTRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_EXP_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_EXP_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "ExpType"),   \
+    SW_PARAM_DEF(SW_API_SEC_EXP_CTRL_GET, SW_EXP_CTRL, \
+		    sizeof(fal_l3_excep_ctrl_t), SW_PARAM_PTR|SW_PARAM_OUT, "ExpCtrl"),
+
+#define SW_API_SEC_EXP_CTRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_SEC_EXP_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_SEC_EXP_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "ExpType"),   \
+    SW_PARAM_DEF(SW_API_SEC_EXP_CTRL_SET, SW_EXP_CTRL, \
+		    sizeof(fal_l3_excep_ctrl_t), SW_PARAM_PTR|SW_PARAM_IN, "ExpCtrl"),
+
+#define SW_API_IP_HOST_ADD_DESC \
+    SW_PARAM_DEF(SW_API_IP_HOST_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_IP_HOST_ADD, SW_IP_HOSTENTRY, \
+		    sizeof(fal_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Hostentry"),
+
+#define SW_API_IP_HOST_DEL_DESC \
+    SW_PARAM_DEF(SW_API_IP_HOST_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_IP_HOST_DEL, SW_UINT32, 4, SW_PARAM_IN, "DelMode"),  \
+    SW_PARAM_DEF(SW_API_IP_HOST_DEL, SW_IP_HOSTENTRY, \
+		    sizeof(fal_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Hostentry"),
+
+#define SW_API_IP_HOST_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_HOST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_IP_HOST_GET, SW_UINT32, 4, SW_PARAM_IN, "GetMode"),  \
+    SW_PARAM_DEF(SW_API_IP_HOST_GET, SW_IP_HOSTENTRY, \
+		    sizeof(fal_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Hostentry"),
+
+#define SW_API_IP_HOST_NEXT_DESC \
+    SW_PARAM_DEF(SW_API_IP_HOST_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_IP_HOST_NEXT, SW_UINT32, 4, SW_PARAM_IN, "NextMode"),  \
+    SW_PARAM_DEF(SW_API_IP_HOST_NEXT, SW_IP_HOSTENTRY, \
+		    sizeof(fal_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Hostentry"),
+
+#define SW_API_IP_HOST_COUNTER_BIND_DESC \
+    SW_PARAM_DEF(SW_API_IP_HOST_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_IP_HOST_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "EntryID"),  \
+    SW_PARAM_DEF(SW_API_IP_HOST_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "CounterID"),\
+    SW_PARAM_DEF(SW_API_IP_HOST_COUNTER_BIND, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_IP_HOST_PPPOE_BIND_DESC \
+    SW_PARAM_DEF(SW_API_IP_HOST_PPPOE_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_HOST_PPPOE_BIND, SW_UINT32, 4, SW_PARAM_IN, "EntryID"), \
+    SW_PARAM_DEF(SW_API_IP_HOST_PPPOE_BIND, SW_UINT32, 4, SW_PARAM_IN, "PPPoEID"), \
+    SW_PARAM_DEF(SW_API_IP_HOST_PPPOE_BIND, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_IP_PT_ARP_LEARN_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "LearnStatus"),
+
+#define SW_API_IP_PT_ARP_LEARN_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "LearnStatus"),
+
+#define SW_API_IP_ARP_LEARN_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_ARP_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_ARP_LEARN_SET, SW_ARP_LEARNMODE, \
+		    sizeof(fal_arp_learn_mode_t), SW_PARAM_IN, "LearnMode"),
+
+#define SW_API_IP_ARP_LEARN_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_ARP_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_ARP_LEARN_GET, SW_ARP_LEARNMODE, \
+		    sizeof(fal_arp_learn_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "LearnMode"),
+
+#define SW_API_IP_SOURCE_GUARD_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_SET, SW_IP_GUARDMODE, \
+		    sizeof(fal_source_guard_mode_t), SW_PARAM_IN, "GuardMode"),
+
+#define SW_API_IP_SOURCE_GUARD_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_GET, SW_IP_GUARDMODE, \
+		    sizeof(fal_source_guard_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "GuardMode"),
+
+#define SW_API_IP_ARP_GUARD_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_ARP_GUARD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_ARP_GUARD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_IP_ARP_GUARD_SET, SW_IP_GUARDMODE, \
+		    sizeof(fal_source_guard_mode_t), SW_PARAM_IN, "GuardMode"),
+
+#define SW_API_IP_ARP_GUARD_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_ARP_GUARD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_ARP_GUARD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_IP_ARP_GUARD_GET, SW_IP_GUARDMODE, \
+		    sizeof(fal_source_guard_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "GuardMode"),
+
+#define SW_API_IP_ROUTE_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_ROUTE_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_ROUTE_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"),
+
+#define SW_API_IP_ROUTE_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_ROUTE_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_ROUTE_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_IP_INTF_ENTRY_ADD_DESC \
+    SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_ADD, SW_INTFMACENTRY, \
+		    sizeof(fal_intf_mac_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Entry"),
+
+#define SW_API_IP_INTF_ENTRY_DEL_DESC \
+    SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "Del Mode"),  \
+    SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_DEL, SW_INTFMACENTRY, \
+		    sizeof(fal_intf_mac_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Entry"),
+
+#define SW_API_IP_INTF_ENTRY_NEXT_DESC \
+    SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Next Mode"),  \
+    SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_NEXT, SW_INTFMACENTRY, \
+		    sizeof(fal_intf_mac_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Entry"),
+
+#define SW_API_IP_UNK_SOURCE_CMD_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Forwarding"),
+
+#define SW_API_IP_UNK_SOURCE_CMD_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Forwarding"),
+
+#define SW_API_ARP_UNK_SOURCE_CMD_SET_DESC \
+    SW_PARAM_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Forwarding"),
+
+#define SW_API_ARP_UNK_SOURCE_CMD_GET_DESC \
+    SW_PARAM_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Forwarding"),
+
+#define SW_API_IP_AGE_TIME_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_AGE_TIME_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IP_AGE_TIME_SET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Time"),
+
+#define SW_API_IP_AGE_TIME_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_AGE_TIME_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_IP_AGE_TIME_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Time"),
+
+#define SW_API_WCMP_HASH_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_WCMP_HASH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_WCMP_HASH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Hash Mode"),
+
+#define SW_API_WCMP_HASH_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_WCMP_HASH_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_WCMP_HASH_MODE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Hash Mode"),
+
+#define SW_API_IP_VRF_BASE_ADDR_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_VRF_BASE_ADDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_VRF_BASE_ADDR_SET, SW_UINT32, 4, SW_PARAM_IN, "VRF ID"), \
+    SW_PARAM_DEF(SW_API_IP_VRF_BASE_ADDR_SET, SW_IP4ADDR, \
+		    sizeof(fal_ip4_addr_t), SW_PARAM_IN, "BaseAddr"),
+
+#define SW_API_IP_VRF_BASE_ADDR_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_VRF_BASE_ADDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_VRF_BASE_ADDR_GET, SW_UINT32, 4, SW_PARAM_IN, "VRF ID"), \
+    SW_PARAM_DEF(SW_API_IP_VRF_BASE_ADDR_GET, SW_IP4ADDR, \
+		    sizeof(fal_ip4_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "BaseAddr"),
+
+#define SW_API_IP_VRF_BASE_MASK_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_VRF_BASE_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_VRF_BASE_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "VRF ID"), \
+    SW_PARAM_DEF(SW_API_IP_VRF_BASE_MASK_SET, SW_IP4ADDR, \
+		    sizeof(fal_ip4_addr_t), SW_PARAM_IN, "BaseMask"),
+
+#define SW_API_IP_VRF_BASE_MASK_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_VRF_BASE_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_VRF_BASE_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "VRF ID"), \
+    SW_PARAM_DEF(SW_API_IP_VRF_BASE_MASK_GET, SW_IP4ADDR, \
+		    sizeof(fal_ip4_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "BaseMask"),
+
+#define SW_API_IP_DEFAULT_ROUTE_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_ROUTE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_ROUTE_SET, SW_UINT32, 4, SW_PARAM_IN, "DefaultRoute ID"), \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_ROUTE_SET, SW_DEFAULT_ROUTE_ENTRY, \
+		    sizeof(fal_default_route_t), SW_PARAM_PTR|SW_PARAM_IN, "DefaultRoute"),
+
+#define SW_API_IP_DEFAULT_ROUTE_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_ROUTE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_ROUTE_GET, SW_UINT32, 4, SW_PARAM_IN, "DefaultRoute ID"), \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_ROUTE_GET, SW_DEFAULT_ROUTE_ENTRY, \
+		    sizeof(fal_default_route_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \
+		    "DefaultRoute"),
+
+#define SW_API_IP_HOST_ROUTE_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_HOST_ROUTE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_HOST_ROUTE_SET, SW_UINT32, 4, SW_PARAM_IN, "HostRoute ID"), \
+    SW_PARAM_DEF(SW_API_IP_HOST_ROUTE_SET, SW_HOST_ROUTE_ENTRY, \
+		    sizeof(fal_host_route_t), SW_PARAM_PTR|SW_PARAM_IN, "HostRoute"),
+
+#define SW_API_IP_HOST_ROUTE_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_HOST_ROUTE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_HOST_ROUTE_GET, SW_UINT32, 4, SW_PARAM_IN, "HostRoute ID"), \
+    SW_PARAM_DEF(SW_API_IP_HOST_ROUTE_GET, SW_HOST_ROUTE_ENTRY, \
+		    sizeof(fal_host_route_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "HostRoute"),
+
+#define SW_API_IP_WCMP_ENTRY_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_WCMP_ENTRY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_WCMP_ENTRY_SET, SW_UINT32, 4, SW_PARAM_IN, "Wcmp ID"), \
+    SW_PARAM_DEF(SW_API_IP_WCMP_ENTRY_SET, SW_IP_WCMP_ENTRY, \
+		    sizeof(fal_ip_wcmp_t), SW_PARAM_PTR|SW_PARAM_IN, "WcmpEntry"),
+
+#define SW_API_IP_WCMP_ENTRY_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_WCMP_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_WCMP_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "Wcmp ID"), \
+    SW_PARAM_DEF(SW_API_IP_WCMP_ENTRY_GET, SW_IP_WCMP_ENTRY, \
+		    sizeof(fal_ip_wcmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "WcmpEntry"),
+
+#define SW_API_IP_RFS_IP4_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_RFS_IP4_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_RFS_IP4_SET, SW_IP_RFS_IP4, \
+		    sizeof(fal_ip4_rfs_t), SW_PARAM_PTR|SW_PARAM_IN, "RfsIp4"),
+
+#define SW_API_IP_RFS_IP6_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_RFS_IP6_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_RFS_IP6_SET, SW_IP_RFS_IP6, \
+		    sizeof(fal_ip6_rfs_t), SW_PARAM_PTR|SW_PARAM_IN, "RfsIp6"),
+
+#define SW_API_IP_RFS_IP4_DEL_DESC \
+    SW_PARAM_DEF(SW_API_IP_RFS_IP4_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_RFS_IP4_DEL, SW_IP_RFS_IP4, \
+		    sizeof(fal_ip4_rfs_t), SW_PARAM_PTR|SW_PARAM_IN, "RfsIp4"),
+
+#define SW_API_IP_RFS_IP6_DEL_DESC \
+    SW_PARAM_DEF(SW_API_IP_RFS_IP6_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_RFS_IP6_DEL, SW_IP_RFS_IP6, \
+		    sizeof(fal_ip6_rfs_t), SW_PARAM_PTR|SW_PARAM_IN, "RfsIp6"),
+
+#define SW_API_IP_DEFAULT_FLOW_CMD_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Vrf ID"), \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_SET, SW_FLOWTYPE, \
+		    sizeof(fal_flow_type_t), SW_PARAM_IN, "FlowType"), \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_SET, SW_FLOWCMD, \
+		    sizeof(fal_default_flow_cmd_t), SW_PARAM_IN, "FlowCmd"),
+
+#define SW_API_IP_DEFAULT_FLOW_CMD_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Vrf ID"), \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_GET, SW_FLOWTYPE, \
+		    sizeof(fal_flow_type_t), SW_PARAM_IN, "FlowType"), \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_GET, SW_FLOWCMD, \
+		    sizeof(fal_default_flow_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "FlowCmd"),
+
+#define SW_API_IP_DEFAULT_RT_FLOW_CMD_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Vrf ID"), \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET, SW_FLOWTYPE, \
+		    sizeof(fal_flow_type_t), SW_PARAM_IN, "FlowType"), \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET, SW_FLOWCMD, \
+		    sizeof(fal_default_flow_cmd_t), SW_PARAM_IN, "FlowCmd"),
+
+#define SW_API_IP_DEFAULT_RT_FLOW_CMD_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Vrf ID"), \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET, SW_FLOWTYPE, \
+		    sizeof(fal_flow_type_t), SW_PARAM_IN, "FlowType"), \
+    SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET, SW_FLOWCMD, \
+		    sizeof(fal_default_flow_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "FlowCmd"),
+
+#define SW_API_IP_VIS_ARP_SG_CFG_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_VIS_ARP_SG_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_VIS_ARP_SG_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \
+    SW_PARAM_DEF(SW_API_IP_VIS_ARP_SG_CFG_GET, SW_ARP_SG_CFG, \
+		    sizeof(fal_arp_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ArpSg"),
+
+#define SW_API_IP_VIS_ARP_SG_CFG_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_VIS_ARP_SG_CFG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_VIS_ARP_SG_CFG_SET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \
+    SW_PARAM_DEF(SW_API_IP_VIS_ARP_SG_CFG_SET, SW_ARP_SG_CFG, \
+		    sizeof(fal_arp_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "ArpSg"),
+
+#define SW_API_IP_NETWORK_ROUTE_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_GET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \
+    SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_GET, SW_UINT8, 1, SW_PARAM_IN, "Type"), \
+    SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_GET, SW_IP_NETWORK_ROUTE, \
+		    sizeof(fal_network_route_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "NetworkRoute"),
+
+#define SW_API_IP_NETWORK_ROUTE_ADD_DESC \
+    SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Index"), \
+    SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_ADD, SW_IP_NETWORK_ROUTE, \
+		    sizeof(fal_network_route_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "NetworkRoute"),
+
+#define SW_API_IP_INTF_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_INTF_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_INTF_GET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \
+    SW_PARAM_DEF(SW_API_IP_INTF_GET, SW_IP_INTF, \
+		    sizeof(fal_intf_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "INTF"),
+
+#define SW_API_IP_INTF_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_INTF_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_INTF_SET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \
+    SW_PARAM_DEF(SW_API_IP_INTF_SET, SW_IP_INTF, \
+		    sizeof(fal_intf_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "INTF"),
+
+#define SW_API_IP_VSI_INTF_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_VSI_INTF_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_VSI_INTF_GET, SW_UINT32, 4, SW_PARAM_IN, "vSI"), \
+    SW_PARAM_DEF(SW_API_IP_VSI_INTF_GET, SW_IP_VSI_INTF, \
+		    sizeof(fal_intf_id_t), SW_PARAM_PTR|SW_PARAM_OUT, "VsiIntf"),
+
+#define SW_API_IP_VSI_INTF_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_VSI_INTF_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_VSI_INTF_SET, SW_UINT32, 4, SW_PARAM_IN, "Vsi"), \
+    SW_PARAM_DEF(SW_API_IP_VSI_INTF_SET, SW_IP_VSI_INTF, \
+		    sizeof(fal_intf_id_t), SW_PARAM_PTR|SW_PARAM_IN, "VsiIntf"),
+
+#define SW_API_IP_PORT_INTF_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_PORT_INTF_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_PORT_INTF_GET, SW_UINT32, 4, SW_PARAM_IN, "port"), \
+    SW_PARAM_DEF(SW_API_IP_PORT_INTF_GET, SW_IP_VSI_INTF, \
+		    sizeof(fal_intf_id_t), SW_PARAM_PTR|SW_PARAM_OUT, "PortIntf"),
+
+#define SW_API_IP_PORT_INTF_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_PORT_INTF_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_PORT_INTF_SET, SW_UINT32, 4, SW_PARAM_IN, "Port"), \
+    SW_PARAM_DEF(SW_API_IP_PORT_INTF_SET, SW_IP_VSI_INTF, \
+		    sizeof(fal_intf_id_t), SW_PARAM_PTR|SW_PARAM_IN, "PortIntf"),
+
+#define SW_API_IP_NEXTHOP_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_NEXTHOP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_NEXTHOP_GET, SW_UINT32, 4, SW_PARAM_IN, "index"), \
+    SW_PARAM_DEF(SW_API_IP_NEXTHOP_GET, SW_IP_NEXTHOP, \
+		    sizeof(fal_ip_nexthop_t), SW_PARAM_PTR|SW_PARAM_OUT, "Nexthop"),
+
+#define SW_API_IP_NEXTHOP_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_NEXTHOP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_NEXTHOP_SET, SW_UINT32, 4, SW_PARAM_IN, "index"), \
+    SW_PARAM_DEF(SW_API_IP_NEXTHOP_SET, SW_IP_NEXTHOP, \
+		    sizeof(fal_ip_nexthop_t), SW_PARAM_PTR|SW_PARAM_IN, "Nexthop"),
+
+#define SW_API_IP_VSI_SG_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_VSI_SG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_VSI_SG_SET, SW_UINT32, 4, SW_PARAM_IN, "vsi"), \
+    SW_PARAM_DEF(SW_API_IP_VSI_SG_SET, SW_IP_SG, \
+		    sizeof(fal_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "vsisg"),
+
+#define SW_API_IP_VSI_SG_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_VSI_SG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_VSI_SG_GET, SW_UINT32, 4, SW_PARAM_IN, "vsi"), \
+    SW_PARAM_DEF(SW_API_IP_VSI_SG_GET, SW_IP_SG, \
+		    sizeof(fal_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "vsisg"),
+
+#define SW_API_IP_PORT_SG_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_PORT_SG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_PORT_SG_SET, SW_UINT32, 4, SW_PARAM_IN, "port"), \
+    SW_PARAM_DEF(SW_API_IP_PORT_SG_SET, SW_IP_SG, \
+		    sizeof(fal_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "portsg"),
+
+#define SW_API_IP_PORT_SG_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_PORT_SG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_PORT_SG_GET, SW_UINT32, 4, SW_PARAM_IN, "port"), \
+    SW_PARAM_DEF(SW_API_IP_PORT_SG_GET, SW_IP_SG, \
+		    sizeof(fal_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "portsg"),
+
+#define SW_API_IP_PUB_IP_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_PUB_IP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_PUB_IP_SET, SW_UINT32, 4, SW_PARAM_IN, "index"),  \
+    SW_PARAM_DEF(SW_API_IP_PUB_IP_SET, SW_IP_PUB, \
+		    sizeof(fal_ip_pub_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "PubAdd"),
+
+#define SW_API_IP_NETWORK_ROUTE_DEL_DESC \
+    SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_DEL, SW_UINT32, 4, SW_PARAM_IN, "index"),  \
+    SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_DEL, SW_UINT8, 1, SW_PARAM_IN, "type"),
+
+#define SW_API_IP_PUB_IP_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_PUB_IP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_PUB_IP_GET, SW_UINT32, 4, SW_PARAM_IN, "index"),  \
+    SW_PARAM_DEF(SW_API_IP_PUB_IP_GET, SW_IP_PUB, \
+		    sizeof(fal_ip_pub_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "PubGet"),
+
+#define SW_API_IP_PORT_MAC_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_PORT_MAC_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_PORT_MAC_GET, SW_UINT32, 4, SW_PARAM_IN, "port"), \
+    SW_PARAM_DEF(SW_API_IP_PORT_MAC_GET, SW_IP_PORTMAC, \
+		    sizeof(fal_macaddr_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "portmac"),
+
+#define SW_API_IP_PORT_MAC_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_PORT_MAC_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_PORT_MAC_SET, SW_UINT32, 4, SW_PARAM_IN, "port"), \
+    SW_PARAM_DEF(SW_API_IP_PORT_MAC_SET, SW_IP_PORTMAC, \
+		    sizeof(fal_macaddr_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "portmac"),
+
+#define SW_API_IP_ROUTE_MISS_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_ROUTE_MISS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_ROUTE_MISS_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "cmd"),
+
+#define SW_API_IP_ROUTE_MISS_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_ROUTE_MISS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_ROUTE_MISS_SET, SW_UINT32, 4, SW_PARAM_IN, "cmd"),
+
+#define SW_API_IP_PORT_ARP_SG_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_PORT_ARP_SG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_PORT_ARP_SG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_IP_PORT_ARP_SG_GET, SW_ARP_SG_CFG, \
+		    sizeof(fal_arp_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "portArpSg"),
+
+#define SW_API_IP_PORT_ARP_SG_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_PORT_ARP_SG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_PORT_ARP_SG_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_IP_PORT_ARP_SG_SET, SW_ARP_SG_CFG, \
+		    sizeof(fal_arp_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "portArpSg"),
+
+#define SW_API_IP_VSI_MC_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_IP_VSI_MC_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_VSI_MC_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Vsi"), \
+    SW_PARAM_DEF(SW_API_IP_VSI_MC_MODE_GET, SW_IP_MCMODE, \
+		    sizeof(fal_mc_mode_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "mcmode"),
+
+#define SW_API_IP_VSI_MC_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_IP_VSI_MC_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_IP_VSI_MC_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Vsi"), \
+    SW_PARAM_DEF(SW_API_IP_VSI_MC_MODE_SET, SW_IP_MCMODE, \
+		    sizeof(fal_mc_mode_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "mcmode"),
+
+#define SW_API_GLOBAL_CTRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_GLOBAL_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_GLOBAL_CTRL_SET, SW_IP_GLOBAL, \
+		    sizeof(fal_ip_global_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "global"),
+
+#define SW_API_GLOBAL_CTRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_GLOBAL_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_GLOBAL_CTRL_GET, SW_IP_GLOBAL, \
+		    sizeof(fal_ip_global_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "global"),
+
+
+#define SW_API_FLOW_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_FLOW_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "status"),
+
+#define SW_API_FLOW_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_FLOW_STATUS_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "status"),
+
+#define SW_API_FLOW_AGE_TIMER_SET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_AGE_TIMER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_FLOW_AGE_TIMER_SET, SW_FLOW_AGE, \
+		    sizeof(fal_flow_age_timer_t), SW_PARAM_PTR|SW_PARAM_IN, "age"),
+
+#define SW_API_FLOW_AGE_TIMER_GET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_AGE_TIMER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_FLOW_AGE_TIMER_GET, SW_FLOW_AGE, \
+		    sizeof(fal_flow_age_timer_t), SW_PARAM_PTR|SW_PARAM_OUT, "age"),
+
+#define SW_API_FLOW_CTRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_FLOW_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "type"),  \
+    SW_PARAM_DEF(SW_API_FLOW_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "dir"),  \
+    SW_PARAM_DEF(SW_API_FLOW_CTRL_SET, SW_FLOW_CTRL, \
+		    sizeof(fal_flow_mgmt_t), SW_PARAM_PTR|SW_PARAM_IN, "ctrl"),
+
+#define SW_API_FLOW_CTRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_FLOW_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "type"),  \
+    SW_PARAM_DEF(SW_API_FLOW_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "dir"),  \
+    SW_PARAM_DEF(SW_API_FLOW_CTRL_GET, SW_FLOW_CTRL, \
+		    sizeof(fal_flow_mgmt_t), SW_PARAM_PTR|SW_PARAM_OUT, "ctrl"),
+
+#define SW_API_FLOW_ENTRY_ADD_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_ENTRY_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_FLOW_ENTRY_ADD, SW_UINT32, 4, SW_PARAM_IN, "add mode"),  \
+    SW_PARAM_DEF(SW_API_FLOW_ENTRY_ADD, SW_FLOW_ENTRY, \
+		    sizeof(fal_flow_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \
+		    "Flowentry"),
+
+#define SW_API_FLOW_ENTRY_DEL_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_FLOW_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "Del mode"),  \
+    SW_PARAM_DEF(SW_API_FLOW_ENTRY_DEL, SW_FLOW_ENTRY, \
+		    sizeof(fal_flow_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Flowentry"),
+
+#define SW_API_FLOW_ENTRY_GET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_FLOW_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "get mode"),  \
+    SW_PARAM_DEF(SW_API_FLOW_ENTRY_GET, SW_FLOW_ENTRY, \
+		    sizeof(fal_flow_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \
+		    "Flowentry"),
+
+#define SW_API_FLOW_HOST_ADD_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_HOST_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_FLOW_HOST_ADD, SW_UINT32, 4, SW_PARAM_IN, "add mode"),  \
+    SW_PARAM_DEF(SW_API_FLOW_HOST_ADD, SW_FLOW_HOST, \
+		    sizeof(fal_flow_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \
+		    "Flowhost"),
+
+#define SW_API_FLOW_HOST_DEL_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_HOST_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_FLOW_HOST_DEL, SW_UINT32, 4, SW_PARAM_IN, "Del mode"),  \
+    SW_PARAM_DEF(SW_API_FLOW_HOST_DEL, SW_FLOW_HOST, \
+		    sizeof(fal_flow_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Flowhost"),
+
+#define SW_API_FLOW_HOST_GET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_HOST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_FLOW_HOST_GET, SW_UINT32, 4, SW_PARAM_IN, "get mode"),  \
+    SW_PARAM_DEF(SW_API_FLOW_HOST_GET, SW_FLOW_HOST, \
+		    sizeof(fal_flow_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \
+		    "Flowhost"),
+
+#define SW_API_FLOW_GLOBAL_CFG_GET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_GLOBAL_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_FLOW_GLOBAL_CFG_GET, SW_FLOW_GLOBAL, \
+		    sizeof(fal_flow_global_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "Flowglobal"),
+
+#define SW_API_FLOW_GLOBAL_CFG_SET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_GLOBAL_CFG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_FLOW_GLOBAL_CFG_SET, SW_FLOW_GLOBAL, \
+		    sizeof(fal_flow_global_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "Flowglobal"),
+
+#define SW_API_FLOWENTRY_NEXT_DESC \
+    SW_PARAM_DEF(SW_API_FLOWENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_FLOWENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Next mode"),  \
+    SW_PARAM_DEF(SW_API_FLOWENTRY_NEXT, SW_FLOW_ENTRY, \
+		    sizeof(fal_flow_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Flowentry"),
+
+#define SW_API_NAT_ADD_DESC \
+    SW_PARAM_DEF(SW_API_NAT_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_NAT_ADD, SW_NATENTRY, \
+		    sizeof(fal_nat_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Natentry"),
+
+#define SW_API_NAT_DEL_DESC \
+    SW_PARAM_DEF(SW_API_NAT_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_NAT_DEL, SW_UINT32, 4, SW_PARAM_IN, "DelMode"),  \
+    SW_PARAM_DEF(SW_API_NAT_DEL, SW_NATENTRY, \
+		    sizeof(fal_nat_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Natentry"),
+
+#define SW_API_NAT_GET_DESC \
+    SW_PARAM_DEF(SW_API_NAT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_NAT_GET, SW_UINT32, 4, SW_PARAM_IN, "GetMode"),  \
+    SW_PARAM_DEF(SW_API_NAT_GET, SW_NATENTRY, \
+		    sizeof(fal_nat_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Natentry"),
+
+#define SW_API_NAT_NEXT_DESC \
+    SW_PARAM_DEF(SW_API_NAT_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_NAT_NEXT, SW_UINT32, 4, SW_PARAM_IN, "NextMode"),  \
+    SW_PARAM_DEF(SW_API_NAT_NEXT, SW_NATENTRY, \
+		    sizeof(fal_nat_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Natentry"),
+
+#define SW_API_NAT_COUNTER_BIND_DESC \
+    SW_PARAM_DEF(SW_API_NAT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_NAT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "EntryID"),  \
+    SW_PARAM_DEF(SW_API_NAT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "CounterID"),\
+    SW_PARAM_DEF(SW_API_NAT_COUNTER_BIND, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_NAPT_ADD_DESC \
+    SW_PARAM_DEF(SW_API_NAPT_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_NAPT_ADD, SW_NAPTENTRY, \
+		    sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Naptentry"),
+
+#define SW_API_NAPT_DEL_DESC \
+    SW_PARAM_DEF(SW_API_NAPT_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_NAPT_DEL, SW_UINT32, 4, SW_PARAM_IN, "DelMode"),  \
+    SW_PARAM_DEF(SW_API_NAPT_DEL, SW_NAPTENTRY, \
+		    sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Naptentry"),
+
+#define SW_API_NAPT_GET_DESC \
+    SW_PARAM_DEF(SW_API_NAPT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_NAPT_GET, SW_UINT32, 4, SW_PARAM_IN, "GetMode"),  \
+    SW_PARAM_DEF(SW_API_NAPT_GET, SW_NAPTENTRY, \
+		    sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Naptentry"),
+
+#define SW_API_NAPT_NEXT_DESC \
+    SW_PARAM_DEF(SW_API_NAPT_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_NAPT_NEXT, SW_UINT32, 4, SW_PARAM_IN, "NextMode"),  \
+    SW_PARAM_DEF(SW_API_NAPT_NEXT, SW_NAPTENTRY, \
+		    sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Naptentry"),
+
+#define SW_API_NAPT_COUNTER_BIND_DESC \
+    SW_PARAM_DEF(SW_API_NAPT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_NAPT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "EntryID"),  \
+    SW_PARAM_DEF(SW_API_NAPT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "CounterID"),\
+    SW_PARAM_DEF(SW_API_NAPT_COUNTER_BIND, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_FLOW_ADD_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_FLOW_ADD, SW_FLOWENTRY, \
+		    sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Flowentry"),
+
+#define SW_API_FLOW_DEL_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_FLOW_DEL, SW_UINT32, 4, SW_PARAM_IN, "DelMode"),  \
+    SW_PARAM_DEF(SW_API_FLOW_DEL, SW_FLOWENTRY, \
+		    sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Flowentry"),
+
+#define SW_API_FLOW_GET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_FLOW_GET, SW_UINT32, 4, SW_PARAM_IN, "GetMode"),  \
+    SW_PARAM_DEF(SW_API_FLOW_GET, SW_FLOWENTRY, \
+		    sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Flowentry"),
+
+#define SW_API_FLOW_NEXT_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_FLOW_NEXT, SW_UINT32, 4, SW_PARAM_IN, "NextMode"),  \
+    SW_PARAM_DEF(SW_API_FLOW_NEXT, SW_FLOWENTRY, \
+		    sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Flowentry"),
+
+#define SW_API_FLOW_COOKIE_SET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_COOKIE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_FLOW_COOKIE_SET, SW_FLOWCOOKIE, \
+		    sizeof(fal_flow_cookie_t), SW_PARAM_PTR|SW_PARAM_IN, "Flowcookieentry"),
+
+#define SW_API_FLOW_RFS_SET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_RFS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_FLOW_RFS_SET, SW_UINT32, 4, SW_PARAM_IN, "action"), \
+    SW_PARAM_DEF(SW_API_FLOW_RFS_SET, SW_FLOWRFS, \
+		    sizeof(fal_flow_rfs_t), SW_PARAM_PTR|SW_PARAM_IN, "Flowrfs"),
+
+
+#define SW_API_FLOW_COUNTER_BIND_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_FLOW_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "EntryID"),  \
+    SW_PARAM_DEF(SW_API_FLOW_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "CounterID"),\
+    SW_PARAM_DEF(SW_API_FLOW_COUNTER_BIND, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_NAT_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_NAT_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_NAT_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"),
+
+#define SW_API_NAT_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_NAT_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_NAT_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_NAT_HASH_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_NAT_HASH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_NAT_HASH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Hashmode"),
+
+#define SW_API_NAT_HASH_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_NAT_HASH_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_NAT_HASH_MODE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Hashmode"),
+
+#define SW_API_NAPT_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_NAPT_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_NAPT_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"),
+
+#define SW_API_NAPT_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_NAPT_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_NAPT_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_NAPT_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_NAPT_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_NAPT_MODE_SET, SW_NAPTMODE, \
+		    sizeof(fal_napt_mode_t), SW_PARAM_IN, "Mode"),
+
+#define SW_API_NAPT_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_NAPT_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_NAPT_MODE_GET, SW_NAPTMODE, \
+		    sizeof(fal_napt_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Mode"),
+
+#define SW_API_PRV_BASE_ADDR_SET_DESC \
+    SW_PARAM_DEF(SW_API_PRV_BASE_ADDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_PRV_BASE_ADDR_SET, SW_IP4ADDR, \
+		    sizeof(fal_ip4_addr_t), SW_PARAM_IN, "BaseAddr"),
+
+#define SW_API_PRV_BASE_ADDR_GET_DESC \
+    SW_PARAM_DEF(SW_API_PRV_BASE_ADDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_PRV_BASE_ADDR_GET, SW_IP4ADDR, \
+		    sizeof(fal_ip4_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "BaseAddr"),
+
+#define SW_API_PRV_ADDR_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PRV_ADDR_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_PRV_ADDR_MODE_SET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_IN, "Mode"),
+
+#define SW_API_PRV_ADDR_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PRV_ADDR_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_PRV_ADDR_MODE_GET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "Mode"),
+
+#define SW_API_PUB_ADDR_ENTRY_ADD_DESC \
+    SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_ADD, SW_PUBADDRENTRY, \
+		    sizeof(fal_nat_pub_addr_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \
+		    "PubAddrEntry"),
+
+#define SW_API_PUB_ADDR_ENTRY_DEL_DESC \
+    SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "DelMode"),  \
+    SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_DEL, SW_PUBADDRENTRY, \
+		    sizeof(fal_nat_pub_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "PubAddrEntry"),
+
+#define SW_API_PUB_ADDR_ENTRY_NEXT_DESC \
+    SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),   \
+    SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "NextMode"),  \
+    SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, SW_PUBADDRENTRY, \
+		    sizeof(fal_nat_pub_addr_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \
+		    "PubAddrEntry"),
+
+#define SW_API_NAT_UNK_SESSION_CMD_SET_DESC \
+    SW_PARAM_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Forwarding"),
+
+#define SW_API_NAT_UNK_SESSION_CMD_GET_DESC \
+    SW_PARAM_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, SW_MACCMD, \
+		    sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Forwarding"),
+
+#define SW_API_PRV_BASE_MASK_SET_DESC \
+    SW_PARAM_DEF(SW_API_PRV_BASE_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_PRV_BASE_MASK_SET, SW_IP4ADDR, \
+		    sizeof(fal_ip4_addr_t), SW_PARAM_IN, "BaseMask"),
+
+#define SW_API_PRV_BASE_MASK_GET_DESC \
+    SW_PARAM_DEF(SW_API_PRV_BASE_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_PRV_BASE_MASK_GET, SW_IP4ADDR, \
+		    sizeof(fal_ip4_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "BaseMask"),
+
+#define SW_API_NAT_GLOBAL_SET_DESC \
+    SW_PARAM_DEF(SW_API_NAT_GLOBAL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),  \
+    SW_PARAM_DEF(SW_API_NAT_GLOBAL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"),  \
+    SW_PARAM_DEF(SW_API_NAT_GLOBAL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Sync Flow Counter"), \
+    SW_PARAM_DEF(SW_API_NAT_GLOBAL_SET, SW_UINT32, 4, SW_PARAM_IN, "wan portbmp"),
+
+#define SW_API_TRUNK_GROUP_SET_DESC \
+    SW_PARAM_DEF(SW_API_TRUNK_GROUP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_TRUNK_GROUP_SET, SW_UINT32, 4, SW_PARAM_IN, "Trunk ID"), \
+    SW_PARAM_DEF(SW_API_TRUNK_GROUP_SET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_IN, "Status"), \
+    SW_PARAM_DEF(SW_API_TRUNK_GROUP_SET, SW_PBMP, \
+		    sizeof(fal_pbmp_t), SW_PARAM_IN, "Member Port Bitmap"),
+
+#define SW_API_TRUNK_GROUP_GET_DESC \
+    SW_PARAM_DEF(SW_API_TRUNK_GROUP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_TRUNK_GROUP_GET, SW_UINT32, 4, SW_PARAM_IN, "Trunk ID"), \
+    SW_PARAM_DEF(SW_API_TRUNK_GROUP_GET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "Status"), \
+    SW_PARAM_DEF(SW_API_TRUNK_GROUP_GET, SW_PBMP, \
+		    sizeof(fal_pbmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "Member Port Bitmap"),
+
+#define SW_API_TRUNK_HASH_SET_DESC \
+    SW_PARAM_DEF(SW_API_TRUNK_HASH_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_TRUNK_HASH_SET, SW_UINT32, 4, SW_PARAM_IN, "Hash Mode"),
+
+#define SW_API_TRUNK_HASH_GET_DESC \
+    SW_PARAM_DEF(SW_API_TRUNK_HASH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_TRUNK_HASH_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Hash Mode"),
+
+#define SW_API_TRUNK_MAN_SA_SET_DESC \
+    SW_PARAM_DEF(SW_API_TRUNK_MAN_SA_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_TRUNK_MAN_SA_SET, SW_MACADDR, \
+		    sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "[Manipulable SA]:"),
+
+#define SW_API_TRUNK_MAN_SA_GET_DESC \
+    SW_PARAM_DEF(SW_API_TRUNK_MAN_SA_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_TRUNK_MAN_SA_GET, SW_MACADDR, \
+		    sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "[Manipulable SA]:"),
+
+#define SW_API_TRUNK_FAILOVER_EN_SET_DESC \
+    SW_PARAM_DEF(SW_API_TRUNK_FAILOVER_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_TRUNK_FAILOVER_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Failover Status"),
+
+#define SW_API_TRUNK_FAILOVER_EN_GET_DESC \
+    SW_PARAM_DEF(SW_API_TRUNK_FAILOVER_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_TRUNK_FAILOVER_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Failover Status"),
+
+#define SW_API_MAC_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_MAC_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MAC_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_MAC_MODE_SET, SW_MACCONFIG, \
+		    sizeof(fal_mac_config_t), SW_PARAM_PTR|SW_PARAM_IN, "MAC config"),
+
+#define SW_API_MAC_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_MAC_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MAC_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_MAC_MODE_GET, SW_MACCONFIG, \
+		    sizeof(fal_mac_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "MAC config"),
+
+#define SW_API_PORT_3AZ_STATUS_SET_DESC \
+    SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_SET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_IN, "Status"),
+
+#define SW_API_PORT_3AZ_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_GET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_PHY_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PHY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PHY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Phy ID"), \
+    SW_PARAM_DEF(SW_API_PHY_MODE_SET, SW_PHYCONFIG, \
+		    sizeof(fal_phy_config_t), SW_PARAM_PTR|SW_PARAM_IN, "PHY config"),
+
+#define SW_API_PHY_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PHY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PHY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Phy ID"), \
+    SW_PARAM_DEF(SW_API_PHY_MODE_GET, SW_PHYCONFIG, \
+		    sizeof(fal_phy_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "PHY config"),
+
+#define SW_API_FX100_CTRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_FX100_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FX100_CTRL_SET, SW_FX100CONFIG, \
+		    sizeof(fal_fx100_ctrl_config_t), SW_PARAM_PTR|SW_PARAM_IN, "fx100 config"),
+
+#define SW_API_FX100_CTRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_FX100_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FX100_CTRL_GET, SW_FX100CONFIG, \
+		    sizeof(fal_fx100_ctrl_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "fx100 config"),
+
+#define SW_API_FX100_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_FX100_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FX100_STATUS_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "fx100 status"),
+
+
+#define SW_API_MAC06_EXCH_SET_DESC \
+    SW_PARAM_DEF(SW_API_MAC06_EXCH_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MAC06_EXCH_SET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_IN, "enable"),
+
+#define SW_API_MAC06_EXCH_GET_DESC \
+    SW_PARAM_DEF(SW_API_MAC06_EXCH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MAC06_EXCH_GET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "enable"),
+
+#define SW_API_VSI_ALLOC_DESC \
+    SW_PARAM_DEF(SW_API_VSI_ALLOC, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VSI_ALLOC, SW_UINT32, \
+		    sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "VSI value"),
+
+#define SW_API_VSI_FREE_DESC \
+    SW_PARAM_DEF(SW_API_VSI_FREE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VSI_FREE, SW_UINT32, 4, SW_PARAM_IN, "VSI value"), \
+
+#define SW_API_PORT_VSI_SET_DESC \
+    SW_PARAM_DEF(SW_API_PORT_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PORT_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PORT_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "VSI value"),
+
+#define SW_API_PORT_VSI_GET_DESC \
+    SW_PARAM_DEF(SW_API_PORT_VSI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PORT_VSI_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PORT_VSI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "VSI value"),
+
+#define SW_API_PORT_VLAN_VSI_SET_DESC \
+    SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "STAG VID"), \
+    SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "CTAG VID"), \
+    SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "VSI value"),
+
+#define SW_API_PORT_VLAN_VSI_GET_DESC \
+    SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_GET, SW_UINT32, 4, SW_PARAM_IN, "STAG VID"), \
+    SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_GET, SW_UINT32, 4, SW_PARAM_IN, "CTAG VID"), \
+    SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "VSI value"),
+
+#define SW_API_VSI_TBL_DUMP_DESC \
+    SW_PARAM_DEF(SW_API_VSI_TBL_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#define SW_API_VSI_NEWADDR_LRN_GET_DESC \
+    SW_PARAM_DEF(SW_API_VSI_NEWADDR_LRN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VSI_NEWADDR_LRN_GET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \
+    SW_PARAM_DEF(SW_API_VSI_NEWADDR_LRN_GET, SW_VSI_NEWADDR_LRN, \
+		    sizeof(fal_vsi_newaddr_lrn_t), SW_PARAM_PTR|SW_PARAM_OUT, "newaddr_lrn"),
+
+#define SW_API_VSI_NEWADDR_LRN_SET_DESC \
+    SW_PARAM_DEF(SW_API_VSI_NEWADDR_LRN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VSI_NEWADDR_LRN_SET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \
+    SW_PARAM_DEF(SW_API_VSI_NEWADDR_LRN_SET, SW_VSI_NEWADDR_LRN, \
+		    sizeof(fal_vsi_newaddr_lrn_t), SW_PARAM_PTR|SW_PARAM_IN, "newaddr_lrn"),
+
+#define SW_API_VSI_STAMOVE_SET_DESC \
+    SW_PARAM_DEF(SW_API_VSI_STAMOVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VSI_STAMOVE_SET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \
+    SW_PARAM_DEF(SW_API_VSI_STAMOVE_SET, SW_VSI_STAMOVE, \
+		    sizeof(fal_vsi_stamove_t), SW_PARAM_PTR|SW_PARAM_IN, "stamove"),
+
+#define SW_API_VSI_STAMOVE_GET_DESC \
+    SW_PARAM_DEF(SW_API_VSI_STAMOVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VSI_STAMOVE_GET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \
+    SW_PARAM_DEF(SW_API_VSI_STAMOVE_GET, SW_VSI_STAMOVE, \
+		    sizeof(fal_vsi_stamove_t), SW_PARAM_PTR|SW_PARAM_OUT, "stamove"),
+
+#define SW_API_VSI_MEMBER_SET_DESC \
+    SW_PARAM_DEF(SW_API_VSI_MEMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VSI_MEMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \
+    SW_PARAM_DEF(SW_API_VSI_MEMBER_SET, SW_VSI_MEMBER, \
+		    sizeof(fal_vsi_member_t), SW_PARAM_PTR|SW_PARAM_IN, "members"),
+
+#define SW_API_VSI_MEMBER_GET_DESC \
+    SW_PARAM_DEF(SW_API_VSI_MEMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VSI_MEMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \
+    SW_PARAM_DEF(SW_API_VSI_MEMBER_GET, SW_VSI_MEMBER, \
+		    sizeof(fal_vsi_member_t), SW_PARAM_PTR|SW_PARAM_OUT, "members"),
+
+#define SW_API_VSI_COUNTER_GET_DESC \
+    SW_PARAM_DEF(SW_API_VSI_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VSI_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \
+    SW_PARAM_DEF(SW_API_VSI_COUNTER_GET, SW_VSI_COUNTER, \
+		    sizeof(fal_vsi_counter_t), SW_PARAM_PTR|SW_PARAM_OUT, "counter"),
+
+#define SW_API_VSI_COUNTER_CLEANUP_DESC \
+    SW_PARAM_DEF(SW_API_VSI_COUNTER_CLEANUP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_VSI_COUNTER_CLEANUP, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"),
+
+#define SW_API_UCAST_QUEUE_BASE_PROFILE_SET_DESC \
+    SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_SET, SW_UCAST_QUEUE_MAP, \
+		    sizeof(fal_ucast_queue_dest_t), SW_PARAM_PTR|SW_PARAM_IN, "queue dest"), \
+    SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue base"), \
+    SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_SET, SW_UINT8, 1, SW_PARAM_IN, "Profile"),
+
+#define SW_API_UCAST_QUEUE_BASE_PROFILE_GET_DESC \
+    SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_GET, SW_UCAST_QUEUE_MAP, \
+		    sizeof(fal_ucast_queue_dest_t), SW_PARAM_PTR|SW_PARAM_IN, "queue dest"), \
+    SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Queue base"), \
+    SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_GET, SW_UINT8, 1, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Profile"),
+
+#define SW_API_UCAST_PRIORITY_CLASS_SET_DESC \
+    SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_SET, SW_UINT8, 1, SW_PARAM_IN, "Profile"), \
+    SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_SET, SW_UINT8, 1, SW_PARAM_IN, "Priority"), \
+    SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_SET, SW_UINT8, 1, SW_PARAM_IN, "Class"),
+
+#define SW_API_UCAST_PRIORITY_CLASS_GET_DESC \
+    SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_GET, SW_UINT8, 1, SW_PARAM_IN, "Profile"), \
+    SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_GET, SW_UINT8, 1, SW_PARAM_IN, "Priority"), \
+    SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_GET, SW_UINT8, 1, SW_PARAM_PTR|SW_PARAM_OUT, "Class"),
+
+#define SW_API_UCAST_HASH_MAP_SET_DESC \
+    SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_SET, SW_UINT8, 1, SW_PARAM_IN, "Profile"), \
+    SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_SET, SW_UINT8, 1, SW_PARAM_IN, "Rss hash"), \
+    SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_SET, SW_UINT8, 1, SW_PARAM_IN, "Queue hash"),
+
+#define SW_API_UCAST_HASH_MAP_GET_DESC \
+    SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_GET, SW_UINT8, 1, SW_PARAM_IN, "Profile"), \
+    SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_GET, SW_UINT8, 1, SW_PARAM_IN, "Rss hash"), \
+    SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_GET, SW_UINT8, 1, SW_PARAM_PTR|SW_PARAM_OUT, "Queue hash"),
+
+#define SW_API_MCAST_CPUCODE_CLASS_SET_DESC \
+    SW_PARAM_DEF(SW_API_MCAST_CPUCODE_CLASS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MCAST_CPUCODE_CLASS_SET, SW_UINT8, 1, SW_PARAM_IN, "Cpu code"), \
+    SW_PARAM_DEF(SW_API_MCAST_CPUCODE_CLASS_SET, SW_UINT8, 1, SW_PARAM_IN, "Queue Class"),
+
+#define SW_API_MCAST_CPUCODE_CLASS_GET_DESC \
+    SW_PARAM_DEF(SW_API_MCAST_CPUCODE_CLASS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MCAST_CPUCODE_CLASS_GET, SW_UINT8, 1, SW_PARAM_IN, "Cpu code"), \
+    SW_PARAM_DEF(SW_API_MCAST_CPUCODE_CLASS_GET, SW_UINT8, 1, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Queue Class"),
+
+#define SW_API_MCAST_PRIORITY_CLASS_SET_DESC \
+    SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_SET, SW_UINT8, 1, SW_PARAM_IN, "Priority"), \
+    SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_SET, SW_UINT8, 1, SW_PARAM_IN, "Queue Class"),
+
+#define SW_API_MCAST_PRIORITY_CLASS_GET_DESC \
+    SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_GET, SW_UINT8, 1, SW_PARAM_IN, "Priority"), \
+    SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_GET, SW_UINT8, 1, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Queue Class"),
+
+#define SW_API_QUEUE_FLUSH_DESC \
+    SW_PARAM_DEF(SW_API_QUEUE_FLUSH, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_FLUSH, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_FLUSH, SW_UINT16, 2, SW_PARAM_IN, "queue ID"),
+
+#define SW_API_UCAST_DFLT_HASH_MAP_SET_DESC \
+    SW_PARAM_DEF(SW_API_UCAST_DFLT_HASH_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_UCAST_DFLT_HASH_MAP_SET, SW_UINT8, 1, SW_PARAM_IN, "ucast dflt hash"),
+
+#define SW_API_UCAST_DFLT_HASH_MAP_GET_DESC \
+    SW_PARAM_DEF(SW_API_UCAST_DFLT_HASH_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_UCAST_DFLT_HASH_MAP_GET, SW_UINT8, 1, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "ucast dflt hash"),
+
+#define SW_API_AC_CTRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_AC_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_AC_CTRL_SET, SW_AC_OBJ, \
+		    sizeof(fal_ac_obj_t), SW_PARAM_PTR|SW_PARAM_IN, "ac obj"), \
+    SW_PARAM_DEF(SW_API_AC_CTRL_SET, SW_AC_CTRL, \
+		    sizeof(fal_ac_ctrl_t), SW_PARAM_PTR|SW_PARAM_IN, "ac ctrl"),
+
+#define SW_API_AC_CTRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_AC_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_AC_CTRL_GET, SW_AC_OBJ, \
+		    sizeof(fal_ac_obj_t), SW_PARAM_PTR|SW_PARAM_IN, "AC obj"), \
+    SW_PARAM_DEF(SW_API_AC_CTRL_GET, SW_AC_CTRL, \
+		    sizeof(fal_ac_ctrl_t), SW_PARAM_PTR|SW_PARAM_OUT, "ac ctrl"),
+
+#define SW_API_AC_PRE_BUFFER_SET_DESC \
+    SW_PARAM_DEF(SW_API_AC_PRE_BUFFER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_AC_PRE_BUFFER_SET, SW_AC_OBJ, \
+		    sizeof(fal_ac_obj_t), SW_PARAM_PTR|SW_PARAM_IN, "AC obj"), \
+    SW_PARAM_DEF(SW_API_AC_PRE_BUFFER_SET, SW_UINT16, 2, SW_PARAM_IN, "num"),
+
+#define SW_API_AC_PRE_BUFFER_GET_DESC \
+    SW_PARAM_DEF(SW_API_AC_PRE_BUFFER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_AC_PRE_BUFFER_GET, SW_AC_OBJ, \
+		    sizeof(fal_ac_obj_t), SW_PARAM_PTR|SW_PARAM_IN, "AC obj"), \
+    SW_PARAM_DEF(SW_API_AC_PRE_BUFFER_GET, SW_UINT16, 2, SW_PARAM_PTR|SW_PARAM_OUT, "num"),
+
+#define SW_API_QUEUE_GROUP_SET_DESC \
+    SW_PARAM_DEF(SW_API_QUEUE_GROUP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_GROUP_SET, SW_UINT32, 4, SW_PARAM_IN, "queue id"), \
+    SW_PARAM_DEF(SW_API_QUEUE_GROUP_SET, SW_UINT8, 1, SW_PARAM_IN, "group id"),
+
+#define SW_API_QUEUE_GROUP_GET_DESC \
+    SW_PARAM_DEF(SW_API_QUEUE_GROUP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_GROUP_GET, SW_UINT32, 4, SW_PARAM_IN, "queue id"), \
+    SW_PARAM_DEF(SW_API_QUEUE_GROUP_GET, SW_UINT8, 1, SW_PARAM_PTR|SW_PARAM_OUT, "group id"),
+
+#define SW_API_STATIC_THRESH_SET_DESC \
+    SW_PARAM_DEF(SW_API_STATIC_THRESH_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_STATIC_THRESH_SET, SW_AC_OBJ, \
+		    sizeof(fal_ac_obj_t), SW_PARAM_PTR|SW_PARAM_IN, "AC obj"), \
+    SW_PARAM_DEF(SW_API_STATIC_THRESH_SET, SW_STATIC_THRESH, \
+		    sizeof(fal_ac_static_threshold_t), SW_PARAM_PTR|SW_PARAM_IN, "static thresh"),
+
+#define SW_API_STATIC_THRESH_GET_DESC \
+    SW_PARAM_DEF(SW_API_STATIC_THRESH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_STATIC_THRESH_GET, SW_AC_OBJ, \
+		    sizeof(fal_ac_obj_t), SW_PARAM_PTR|SW_PARAM_IN, "AC obj"), \
+    SW_PARAM_DEF(SW_API_STATIC_THRESH_GET, SW_STATIC_THRESH, \
+		    sizeof(fal_ac_static_threshold_t), SW_PARAM_PTR|SW_PARAM_OUT, "static thresh"),
+
+#define SW_API_DYNAMIC_THRESH_SET_DESC \
+    SW_PARAM_DEF(SW_API_DYNAMIC_THRESH_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_DYNAMIC_THRESH_SET, SW_UINT32, 4, SW_PARAM_IN, "queue id"), \
+    SW_PARAM_DEF(SW_API_DYNAMIC_THRESH_SET, SW_DYNAMIC_THRESH, \
+		    sizeof(fal_ac_dynamic_threshold_t), SW_PARAM_PTR|SW_PARAM_IN, \
+		    "dynamic thresh"),
+
+#define SW_API_DYNAMIC_THRESH_GET_DESC \
+    SW_PARAM_DEF(SW_API_DYNAMIC_THRESH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_DYNAMIC_THRESH_GET, SW_UINT32, 4, SW_PARAM_IN, "queue id"), \
+    SW_PARAM_DEF(SW_API_DYNAMIC_THRESH_GET, SW_DYNAMIC_THRESH, \
+		    sizeof(fal_ac_dynamic_threshold_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "dynamic thresh"),
+
+#define SW_API_GOURP_BUFFER_SET_DESC \
+    SW_PARAM_DEF(SW_API_GOURP_BUFFER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_GOURP_BUFFER_SET, SW_UINT8, 1, SW_PARAM_IN, "group"), \
+    SW_PARAM_DEF(SW_API_GOURP_BUFFER_SET, SW_GROUP_BUFFER, \
+		    sizeof(fal_ac_group_buffer_t), SW_PARAM_PTR|SW_PARAM_IN, "buffer cfg"),
+
+#define SW_API_GOURP_BUFFER_GET_DESC \
+    SW_PARAM_DEF(SW_API_GOURP_BUFFER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_GOURP_BUFFER_GET, SW_UINT8, 1, SW_PARAM_IN, "group"), \
+    SW_PARAM_DEF(SW_API_GOURP_BUFFER_GET, SW_GROUP_BUFFER, \
+		    sizeof(fal_ac_group_buffer_t), SW_PARAM_PTR|SW_PARAM_OUT, "buffer cfg"),
+
+#define SW_API_QUEUE_CNT_CTRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_QUEUE_CNT_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_CNT_CTRL_GET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "queue cnt en"),
+
+#define SW_API_QUEUE_CNT_CTRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_QUEUE_CNT_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_CNT_CTRL_SET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_IN, "queue cnt en"),
+
+#define SW_API_QUEUE_CNT_CLEANUP_DESC \
+    SW_PARAM_DEF(SW_API_QUEUE_CNT_CLEANUP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_CNT_CLEANUP, SW_UINT32, 4, SW_PARAM_IN, "queue id"),
+
+#define SW_API_QUEUE_CNT_GET_DESC \
+    SW_PARAM_DEF(SW_API_QUEUE_CNT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_CNT_GET, SW_UINT32, 4, SW_PARAM_IN, "queue ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_CNT_GET, SW_QM_CNT, \
+		    sizeof(fal_queue_stats_t), SW_PARAM_PTR|SW_PARAM_OUT, "queue cnt"),
+
+#define SW_API_QM_ENQUEUE_CTRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_QM_ENQUEUE_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QM_ENQUEUE_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "queue ID"), \
+    SW_PARAM_DEF(SW_API_QM_ENQUEUE_CTRL_SET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_IN, "enqueue en"),
+
+#define SW_API_QM_ENQUEUE_CTRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_QM_ENQUEUE_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QM_ENQUEUE_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "queue ID"), \
+    SW_PARAM_DEF(SW_API_QM_ENQUEUE_CTRL_GET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "enqueue en"),
+
+#define SW_API_QM_SOURCE_PROFILE_SET_DESC \
+    SW_PARAM_DEF(SW_API_QM_SOURCE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QM_SOURCE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_QM_SOURCE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Source profile"),
+
+#define SW_API_QM_SOURCE_PROFILE_GET_DESC \
+    SW_PARAM_DEF(SW_API_QM_SOURCE_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QM_SOURCE_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_QM_SOURCE_PROFILE_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Source profile"),
+
+#define SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET_DESC \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Profile ID"), \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Ethernet Type"),
+
+#define SW_API_MGMTCTRL_ETHTYPE_PROFILE_GET_DESC \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Profile ID"), \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Ethernet Type"),
+
+#define SW_API_MGMTCTRL_RFDB_PROFILE_SET_DESC \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Profile ID"), \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_SET, SW_MACADDR, \
+		    sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "Address"),
+
+#define SW_API_MGMTCTRL_RFDB_PROFILE_GET_DESC \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Profile ID"), \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_GET, SW_MACADDR, \
+		    sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "Address"),
+
+#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_ADD_DESC \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_ADD, SW_CTRLPKT_PROFILE, \
+		    sizeof(fal_ctrlpkt_profile_t), SW_PARAM_PTR|SW_PARAM_IN, "app entry"),
+
+#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_DEL_DESC \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_DEL, SW_CTRLPKT_PROFILE, \
+		    sizeof(fal_ctrlpkt_profile_t), SW_PARAM_PTR|SW_PARAM_IN, "app entry"),
+
+#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST_DESC \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST, SW_CTRLPKT_PROFILE, \
+		    sizeof(fal_ctrlpkt_profile_t), SW_PARAM_PTR|SW_PARAM_OUT, "app entry"),
+
+#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT_DESC \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT, SW_CTRLPKT_PROFILE, \
+		    sizeof(fal_ctrlpkt_profile_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \
+		    "app entry"),
+
+#define SW_API_SERVCODE_CONFIG_SET_DESC \
+    SW_PARAM_DEF(SW_API_SERVCODE_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SERVCODE_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \
+    SW_PARAM_DEF(SW_API_SERVCODE_CONFIG_SET, SW_SERVCODE_CONFIG, \
+		    sizeof(fal_servcode_config_t), SW_PARAM_PTR|SW_PARAM_IN, "Servcode Config"),
+
+#define SW_API_SERVCODE_CONFIG_GET_DESC \
+    SW_PARAM_DEF(SW_API_SERVCODE_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SERVCODE_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \
+    SW_PARAM_DEF(SW_API_SERVCODE_CONFIG_GET, SW_SERVCODE_CONFIG, \
+		    sizeof(fal_servcode_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "Servcode Config"),
+
+#define SW_API_SERVCODE_LOOPCHECK_EN_DESC \
+    SW_PARAM_DEF(SW_API_SERVCODE_LOOPCHECK_EN, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SERVCODE_LOOPCHECK_EN, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_SERVCODE_LOOPCHECK_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_SERVCODE_LOOPCHECK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SERVCODE_LOOPCHECK_STATUS_GET, SW_ENABLE, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_BM_CTRL_SET_DESC \
+    SW_PARAM_DEF(SW_API_BM_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BM_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \
+    SW_PARAM_DEF(SW_API_BM_CTRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "bm ctrl"),
+
+#define SW_API_BM_CTRL_GET_DESC \
+    SW_PARAM_DEF(SW_API_BM_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BM_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \
+    SW_PARAM_DEF(SW_API_BM_CTRL_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "bm ctrl"),
+
+#define SW_API_BM_PORTGROUP_MAP_SET_DESC \
+    SW_PARAM_DEF(SW_API_BM_PORTGROUP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BM_PORTGROUP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \
+    SW_PARAM_DEF(SW_API_BM_PORTGROUP_MAP_SET, SW_UINT8, 4, SW_PARAM_IN, "group"),
+
+#define SW_API_BM_PORTGROUP_MAP_GET_DESC \
+    SW_PARAM_DEF(SW_API_BM_PORTGROUP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BM_PORTGROUP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \
+    SW_PARAM_DEF(SW_API_BM_PORTGROUP_MAP_GET, SW_UINT8, 4, SW_PARAM_PTR|SW_PARAM_OUT, "group"),
+
+#define SW_API_BM_GROUP_BUFFER_SET_DESC \
+    SW_PARAM_DEF(SW_API_BM_GROUP_BUFFER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BM_GROUP_BUFFER_SET, SW_UINT8, 1, SW_PARAM_IN, "group id"), \
+    SW_PARAM_DEF(SW_API_BM_GROUP_BUFFER_SET, SW_UINT16, 2, SW_PARAM_IN, "buff num"),
+
+#define SW_API_BM_GROUP_BUFFER_GET_DESC \
+    SW_PARAM_DEF(SW_API_BM_GROUP_BUFFER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BM_GROUP_BUFFER_GET, SW_UINT8, 1, SW_PARAM_IN, "group id"), \
+    SW_PARAM_DEF(SW_API_BM_GROUP_BUFFER_GET, SW_UINT16, 2, SW_PARAM_PTR|SW_PARAM_OUT, "buff num"),
+
+#define SW_API_BM_PORT_RSVBUFFER_SET_DESC \
+    SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_SET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \
+    SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_SET, SW_UINT16, 2, SW_PARAM_IN, "prealloc buff"), \
+    SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_SET, SW_UINT16, 2, SW_PARAM_IN, "react buff"),
+
+#define SW_API_BM_PORT_RSVBUFFER_GET_DESC \
+    SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_GET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \
+    SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_GET, SW_UINT16, 2, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "prealloc buff"), \
+    SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_GET, SW_UINT16, 2, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "react buff"),
+
+#define SW_API_BM_STATIC_THRESH_SET_DESC \
+    SW_PARAM_DEF(SW_API_BM_STATIC_THRESH_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BM_STATIC_THRESH_SET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \
+    SW_PARAM_DEF(SW_API_BM_STATIC_THRESH_SET, SW_BMSTHRESH, \
+		    sizeof(fal_bm_static_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "static thresh"),
+
+#define SW_API_BM_STATIC_THRESH_GET_DESC \
+    SW_PARAM_DEF(SW_API_BM_STATIC_THRESH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BM_STATIC_THRESH_GET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \
+    SW_PARAM_DEF(SW_API_BM_STATIC_THRESH_GET, SW_BMSTHRESH, \
+		    sizeof(fal_bm_static_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "static thresh"),
+
+#define SW_API_BM_DYNAMIC_THRESH_SET_DESC \
+    SW_PARAM_DEF(SW_API_BM_DYNAMIC_THRESH_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BM_DYNAMIC_THRESH_SET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \
+    SW_PARAM_DEF(SW_API_BM_DYNAMIC_THRESH_SET, SW_BMDTHRESH, \
+		    sizeof(fal_bm_dynamic_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "dynamic thresh"),
+
+#define SW_API_BM_DYNAMIC_THRESH_GET_DESC \
+    SW_PARAM_DEF(SW_API_BM_DYNAMIC_THRESH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BM_DYNAMIC_THRESH_GET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \
+    SW_PARAM_DEF(SW_API_BM_DYNAMIC_THRESH_GET, SW_BMDTHRESH, \
+		    sizeof(fal_bm_dynamic_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "dynamic thresh"),
+
+#define SW_API_BM_PORT_COUNTER_GET_DESC \
+    SW_PARAM_DEF(SW_API_BM_PORT_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_BM_PORT_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \
+    SW_PARAM_DEF(SW_API_BM_PORT_COUNTER_GET, SW_BMPORTCNT, \
+		    sizeof(fal_bm_port_counter_t), SW_PARAM_PTR|SW_PARAM_OUT, "port counter"),
+
+#define SW_API_PORT_SHAPER_TIMESLOT_SET_DESC \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Time Slot"),
+
+#define SW_API_PORT_SHAPER_TIMESLOT_GET_DESC \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_TIMESLOT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_TIMESLOT_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Time Slot"),
+
+#define SW_API_FLOW_SHAPER_TIMESLOT_SET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Time Slot"),
+
+#define SW_API_FLOW_SHAPER_TIMESLOT_GET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_TIMESLOT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_TIMESLOT_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Time Slot"),
+
+#define SW_API_QUEUE_SHAPER_TIMESLOT_SET_DESC \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Time Slot"),
+
+#define SW_API_QUEUE_SHAPER_TIMESLOT_GET_DESC \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TIMESLOT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TIMESLOT_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Time Slot"),
+
+#define SW_API_PORT_SHAPER_TOKEN_NUMBER_SET_DESC \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_SET, SW_PORT_SHAPER_TOKEN_CONFIG, \
+		    sizeof(fal_shaper_token_number_t), SW_PARAM_PTR|SW_PARAM_IN, "CONFIG"),
+
+#define SW_API_PORT_SHAPER_TOKEN_NUMBER_GET_DESC \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_GET, SW_PORT_SHAPER_TOKEN_CONFIG, \
+		    sizeof(fal_shaper_token_number_t), SW_PARAM_PTR|SW_PARAM_OUT, "CONFIG"),
+
+#define SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "Flow ID"), \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET, SW_SHAPER_TOKEN_CONFIG, \
+		    sizeof(fal_shaper_token_number_t), SW_PARAM_PTR|SW_PARAM_IN, "CONFIG"),
+
+#define SW_API_FLOW_SHAPER_TOKEN_NUMBER_GET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "Flow ID"), \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_GET, SW_SHAPER_TOKEN_CONFIG, \
+		    sizeof(fal_shaper_token_number_t), SW_PARAM_PTR|SW_PARAM_OUT, "CONFIG"),
+
+#define SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET_DESC \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET, SW_SHAPER_TOKEN_CONFIG, \
+		    sizeof(fal_shaper_token_number_t), SW_PARAM_PTR|SW_PARAM_IN, "CONFIG"),
+
+#define SW_API_QUEUE_SHAPER_TOKEN_NUMBER_GET_DESC \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_GET, SW_SHAPER_TOKEN_CONFIG, \
+		    sizeof(fal_shaper_token_number_t), SW_PARAM_PTR|SW_PARAM_OUT, "CONFIG"),
+
+#define SW_API_PORT_SHAPER_SET_DESC \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_SET, SW_PORT_SHAPER_CONFIG, \
+		    sizeof(fal_shaper_config_t), SW_PARAM_PTR|SW_PARAM_IN, "CONFIG"),
+
+#define SW_API_PORT_SHAPER_GET_DESC \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PORT_SHAPER_GET, SW_PORT_SHAPER_CONFIG, \
+		    sizeof(fal_shaper_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "CONFIG"),
+
+#define SW_API_FLOW_SHAPER_SET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Flow ID"), \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_SET, SW_SHAPER_CONFIG, \
+		    sizeof(fal_shaper_config_t), SW_PARAM_PTR|SW_PARAM_IN, "CONFIG"),
+
+#define SW_API_FLOW_SHAPER_GET_DESC \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Flow ID"), \
+    SW_PARAM_DEF(SW_API_FLOW_SHAPER_GET, SW_SHAPER_CONFIG, \
+		    sizeof(fal_shaper_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "CONFIG"),
+
+#define SW_API_QUEUE_SHAPER_SET_DESC \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_SET, SW_SHAPER_CONFIG, \
+		    sizeof(fal_shaper_config_t), SW_PARAM_PTR|SW_PARAM_IN, "CONFIG"),
+
+#define SW_API_QUEUE_SHAPER_GET_DESC \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"), \
+    SW_PARAM_DEF(SW_API_QUEUE_SHAPER_GET, SW_SHAPER_CONFIG, \
+		    sizeof(fal_shaper_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "CONFIG"),
+
+#define SW_API_SHAPER_IPG_PRE_SET_DESC \
+    SW_PARAM_DEF(SW_API_SHAPER_IPG_PRE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SHAPER_IPG_PRE_SET, SW_UINT32, 4, SW_PARAM_IN, "IPG and Preamble"),
+
+#define SW_API_SHAPER_IPG_PRE_GET_DESC \
+    SW_PARAM_DEF(SW_API_SHAPER_IPG_PRE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SHAPER_IPG_PRE_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "IPG and Preamble"),
+
+#define SW_API_POLICER_TIMESLOT_SET_DESC \
+    SW_PARAM_DEF(SW_API_POLICER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Time Slot"),
+
+#define SW_API_POLICER_TIMESLOT_GET_DESC \
+    SW_PARAM_DEF(SW_API_POLICER_TIMESLOT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_TIMESLOT_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Time Slot"),
+
+#define SW_API_POLICER_PORT_COUNTER_GET_DESC \
+    SW_PARAM_DEF(SW_API_POLICER_PORT_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_PORT_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_PORT_COUNTER_GET, SW_POLICER_COUNTER, \
+		    sizeof(fal_policer_counter_t), SW_PARAM_PTR|SW_PARAM_OUT, "Port Statistics"),
+
+#define SW_API_POLICER_ACL_COUNTER_GET_DESC \
+    SW_PARAM_DEF(SW_API_POLICER_ACL_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_ACL_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \
+    SW_PARAM_DEF(SW_API_POLICER_ACL_COUNTER_GET, SW_POLICER_COUNTER, \
+		    sizeof(fal_policer_counter_t), SW_PARAM_PTR|SW_PARAM_OUT, "ACL Statistics"),
+
+#define SW_API_POLICER_COMPENSATION_SET_DESC \
+    SW_PARAM_DEF(SW_API_POLICER_COMPENSATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_COMPENSATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_COMPENSATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Number"),
+
+#define SW_API_POLICER_COMPENSATION_GET_DESC \
+    SW_PARAM_DEF(SW_API_POLICER_COMPENSATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_COMPENSATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_COMPENSATION_GET, SW_UINT32, 4, \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Number"),
+
+#define SW_API_POLICER_PORT_ENTRY_SET_DESC \
+    SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_SET, SW_POLICER_PORT_CONFIG, \
+		    sizeof(fal_policer_config_t), SW_PARAM_PTR|SW_PARAM_IN, "Port Config"), \
+    SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_SET, SW_POLICER_CMD_CONFIG, \
+		    sizeof(fal_policer_action_t), SW_PARAM_PTR|SW_PARAM_IN, "CMD"),
+
+#define SW_API_POLICER_PORT_ENTRY_GET_DESC \
+    SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_GET, SW_POLICER_PORT_CONFIG, \
+		    sizeof(fal_policer_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "Port Config"), \
+    SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_GET, SW_POLICER_CMD_CONFIG, \
+		    sizeof(fal_policer_action_t), SW_PARAM_PTR|SW_PARAM_OUT, "CMD"),
+
+#define SW_API_POLICER_ACL_ENTRY_SET_DESC \
+    SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_SET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \
+    SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_SET, SW_POLICER_ACL_CONFIG, \
+		    sizeof(fal_policer_config_t), SW_PARAM_PTR|SW_PARAM_IN, "ACL Config"), \
+    SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_SET, SW_POLICER_CMD_CONFIG, \
+		    sizeof(fal_policer_action_t), SW_PARAM_PTR|SW_PARAM_IN, "CMD"),
+
+#define SW_API_POLICER_ACL_ENTRY_GET_DESC \
+    SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \
+    SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_GET, SW_POLICER_ACL_CONFIG, \
+		    sizeof(fal_policer_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "ACL Config"), \
+    SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_GET, SW_POLICER_CMD_CONFIG, \
+		    sizeof(fal_policer_action_t), SW_PARAM_PTR|SW_PARAM_OUT, "CMD"),
+
+#define SW_API_POLICER_GLOBAL_COUNTER_GET_DESC \
+    SW_PARAM_DEF(SW_API_POLICER_GLOBAL_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_GLOBAL_COUNTER_GET, SW_POLICER_GLOBAL_COUNTER, \
+		    sizeof(fal_policer_global_counter_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Global Statistics"),
+
+#define SW_API_POLICER_BYPASS_EN_SET_DESC \
+    SW_PARAM_DEF(SW_API_POLICER_BYPASS_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_BYPASS_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "frame_type"), \
+    SW_PARAM_DEF(SW_API_POLICER_BYPASS_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"),
+
+#define SW_API_POLICER_BYPASS_EN_GET_DESC \
+    SW_PARAM_DEF(SW_API_POLICER_BYPASS_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_POLICER_BYPASS_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "frame_type"), \
+    SW_PARAM_DEF(SW_API_POLICER_BYPASS_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_PTP_CONFIG_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_CONFIG_SET, SW_PTP_CONFIG, \
+		    sizeof(fal_ptp_config_t), SW_PARAM_PTR|SW_PARAM_IN, "CONFIG"),
+
+#define SW_API_PTP_CONFIG_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_CONFIG_GET, SW_PTP_CONFIG, \
+		    sizeof(fal_ptp_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "CONFIG"),
+
+#define SW_API_PTP_REFERENCE_CLOCK_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_REFERENCE_CLOCK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_REFERENCE_CLOCK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_REFERENCE_CLOCK_SET, SW_PTP_REFERENCE_CLOCK, \
+		    sizeof(fal_ptp_reference_clock_t), SW_PARAM_IN, "Ref Clock"),
+
+#define SW_API_PTP_REFERENCE_CLOCK_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_REFERENCE_CLOCK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_REFERENCE_CLOCK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_REFERENCE_CLOCK_GET, SW_PTP_REFERENCE_CLOCK, \
+		    sizeof(fal_ptp_reference_clock_t), SW_PARAM_PTR|SW_PARAM_OUT, "Ref Clock"),
+
+#define SW_API_PTP_RX_TIMESTAMP_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_SET, SW_PTP_RX_TIMESTAMP_MODE, \
+		    sizeof(fal_ptp_rx_timestamp_mode_t), SW_PARAM_IN, "Timestamp Mode"),
+
+#define SW_API_PTP_RX_TIMESTAMP_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_GET, SW_PTP_RX_TIMESTAMP_MODE, \
+		    sizeof(fal_ptp_rx_timestamp_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Timestamp Mode"),
+
+#define SW_API_PTP_TIMESTAMP_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_TIMESTAMP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_TIMESTAMP_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_TIMESTAMP_GET, SW_PTP_DIRECTION, \
+		    sizeof(fal_ptp_direction_t), SW_PARAM_IN, "Direction"), \
+    SW_PARAM_DEF(SW_API_PTP_TIMESTAMP_GET, SW_PTP_PKT_INFO, \
+		    sizeof(fal_ptp_pkt_info_t), SW_PARAM_PTR|SW_PARAM_IN, "Pkt Info"), \
+    SW_PARAM_DEF(SW_API_PTP_TIMESTAMP_GET, SW_PTP_TIME, \
+		    sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_OUT, "Time"),
+
+#define SW_API_PTP_PKT_TIMESTAMP_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_PKT_TIMESTAMP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_PKT_TIMESTAMP_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_PKT_TIMESTAMP_SET, SW_PTP_TIME, \
+		    sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_IN, "Time"),
+
+#define SW_API_PTP_PKT_TIMESTAMP_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_PKT_TIMESTAMP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_PKT_TIMESTAMP_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_PKT_TIMESTAMP_GET, SW_PTP_TIME, \
+		    sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_OUT, "Time"),
+
+#define SW_API_PTP_GRANDMASTER_MODE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_GRANDMASTER_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_GRANDMASTER_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_GRANDMASTER_MODE_SET, SW_PTP_GRANDMASTER_MODE, \
+		    sizeof(fal_ptp_grandmaster_mode_t), SW_PARAM_PTR|SW_PARAM_IN, \
+		    "Grandmaster Mode"),
+
+#define SW_API_PTP_GRANDMASTER_MODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_GRANDMASTER_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_GRANDMASTER_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_GRANDMASTER_MODE_GET, SW_PTP_GRANDMASTER_MODE, \
+		    sizeof(fal_ptp_grandmaster_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+		    "Grandmaster Mode"),
+
+#define SW_API_PTP_RTC_TIME_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SET, SW_PTP_TIME, \
+		    sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_IN, "Time"),
+
+#define SW_API_PTP_RTC_TIME_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_RTC_TIME_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RTC_TIME_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RTC_TIME_GET, SW_PTP_TIME, \
+		    sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_OUT, "Time"),
+
+#define SW_API_PTP_RTC_TIME_CLEAR_DESC \
+    SW_PARAM_DEF(SW_API_PTP_RTC_TIME_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RTC_TIME_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),
+
+#define SW_API_PTP_RTC_ADJTIME_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_RTC_ADJTIME_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RTC_ADJTIME_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RTC_ADJTIME_SET, SW_PTP_TIME, \
+		    sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_IN, "Time"),
+
+#define SW_API_PTP_RTC_ADJFREQ_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_RTC_ADJFREQ_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RTC_ADJFREQ_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RTC_ADJFREQ_SET, SW_PTP_TIME, \
+		    sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_IN, "Time"),
+
+#define SW_API_PTP_RTC_ADJFREQ_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_RTC_ADJFREQ_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RTC_ADJFREQ_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RTC_ADJFREQ_GET, SW_PTP_TIME, \
+		    sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_OUT, "Time"),
+
+#define SW_API_PTP_LINK_DELAY_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_LINK_DELAY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_LINK_DELAY_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_LINK_DELAY_SET, SW_PTP_TIME, \
+		    sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_IN, "Time"),
+
+#define SW_API_PTP_LINK_DELAY_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_LINK_DELAY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_LINK_DELAY_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_LINK_DELAY_GET, SW_PTP_TIME, \
+		    sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_OUT, "Time"),
+
+#define SW_API_PTP_SECURITY_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_SECURITY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_SECURITY_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_SECURITY_SET, SW_PTP_SECURITY, \
+		    sizeof(fal_ptp_security_t), SW_PARAM_PTR|SW_PARAM_IN, "Security"),
+
+#define SW_API_PTP_SECURITY_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_SECURITY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_SECURITY_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_SECURITY_GET, SW_PTP_SECURITY, \
+		    sizeof(fal_ptp_security_t), SW_PARAM_PTR|SW_PARAM_OUT, "Security"),
+
+#define SW_API_PTP_PPS_SIGNAL_CONTROL_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_SET, SW_PTP_PPS_SIGNAL_CONTROL, \
+		    sizeof(fal_ptp_pps_signal_control_t), SW_PARAM_PTR|SW_PARAM_IN, "Sig Ctrl"),
+
+#define SW_API_PTP_PPS_SIGNAL_CONTROL_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_GET, SW_PTP_PPS_SIGNAL_CONTROL, \
+		    sizeof(fal_ptp_pps_signal_control_t), SW_PARAM_PTR|SW_PARAM_OUT, "Sig Ctrl"),
+
+#define SW_API_PTP_RX_CRC_RECALC_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_RX_CRC_RECALC_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RX_CRC_RECALC_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RX_CRC_RECALC_SET, SW_ENABLE, sizeof(a_bool_t), SW_PARAM_IN, "Status"),
+
+#define SW_API_PTP_RX_CRC_RECALC_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_RX_CRC_RECALC_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RX_CRC_RECALC_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RX_CRC_RECALC_GET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_PTP_ASYM_CORRECTION_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_ASYM_CORRECTION_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_ASYM_CORRECTION_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_ASYM_CORRECTION_SET, SW_PTP_ASYM_CORRECTION, \
+		    sizeof(fal_ptp_asym_correction_t), \
+		    SW_PARAM_PTR|SW_PARAM_IN, "Asym CF"),
+
+#define SW_API_PTP_ASYM_CORRECTION_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_ASYM_CORRECTION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_ASYM_CORRECTION_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_ASYM_CORRECTION_GET, SW_PTP_ASYM_CORRECTION, \
+		    sizeof(fal_ptp_asym_correction_t), \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Asym CF"),
+
+#define SW_API_PTP_OUTPUT_WAVEFORM_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_OUTPUT_WAVEFORM_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_OUTPUT_WAVEFORM_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_OUTPUT_WAVEFORM_SET, SW_PTP_OUTPUT_WAVEFORM, \
+		    sizeof(fal_ptp_output_waveform_t), \
+		    SW_PARAM_PTR|SW_PARAM_IN, "Waveform"),
+
+#define SW_API_PTP_OUTPUT_WAVEFORM_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_OUTPUT_WAVEFORM_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_OUTPUT_WAVEFORM_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_OUTPUT_WAVEFORM_GET, SW_PTP_OUTPUT_WAVEFORM, \
+		    sizeof(fal_ptp_output_waveform_t), \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Waveform"),
+
+#define SW_API_PTP_RTC_TIME_SNAPSHOT_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_SET, SW_ENABLE, \
+		    sizeof(a_bool_t), SW_PARAM_IN, "Status"),
+
+#define SW_API_PTP_RTC_TIME_SNAPSHOT_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_GET, SW_ENABLE, sizeof(a_bool_t), \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_SET, SW_ENABLE, sizeof(a_bool_t), \
+		    SW_PARAM_IN, "Status"),
+
+#define SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_GET, SW_ENABLE, sizeof(a_bool_t), \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_PTP_TOD_UART_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_TOD_UART_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_TOD_UART_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_TOD_UART_SET, SW_PTP_TOD_UART, sizeof(fal_ptp_tod_uart_t), \
+		    SW_PARAM_PTR|SW_PARAM_IN, "TOD UART"),
+
+#define SW_API_PTP_TOD_UART_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_TOD_UART_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_TOD_UART_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_TOD_UART_GET, SW_PTP_TOD_UART, sizeof(fal_ptp_tod_uart_t), \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "TOD UART"),
+
+#define SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET, SW_PTP_DIRECTION, \
+		    sizeof(fal_ptp_direction_t), SW_PARAM_IN, "Direction"), \
+    SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET, SW_PTP_ENHANCED_TS_ENGINE, \
+		    sizeof(fal_ptp_enhanced_ts_engine_t), SW_PARAM_PTR|SW_PARAM_IN, "TS Engine"),
+
+#define SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET, SW_PTP_DIRECTION, \
+		    sizeof(fal_ptp_direction_t), SW_PARAM_IN, "Direction"), \
+    SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET, SW_PTP_ENHANCED_TS_ENGINE, \
+		    sizeof(fal_ptp_enhanced_ts_engine_t), SW_PARAM_PTR|SW_PARAM_OUT, "TS Engine"),
+
+#define SW_API_PTP_TRIGGER_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_TRIGGER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_TRIGGER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_TRIGGER_SET, SW_UINT32, 4, SW_PARAM_IN, "Trigger ID"), \
+    SW_PARAM_DEF(SW_API_PTP_TRIGGER_SET, SW_PTP_TRIGGER, sizeof(fal_ptp_trigger_t), \
+		    SW_PARAM_PTR|SW_PARAM_IN, "Trigger"),
+
+#define SW_API_PTP_TRIGGER_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_TRIGGER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_TRIGGER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_TRIGGER_GET, SW_UINT32, 4, SW_PARAM_IN, "Trigger ID"), \
+    SW_PARAM_DEF(SW_API_PTP_TRIGGER_GET, SW_PTP_TRIGGER, sizeof(fal_ptp_trigger_t), \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Trigger"),
+
+#define SW_API_PTP_CAPTURE_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_CAPTURE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_CAPTURE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_CAPTURE_SET, SW_UINT32, 4, SW_PARAM_IN, "Capture ID"), \
+    SW_PARAM_DEF(SW_API_PTP_CAPTURE_SET, SW_PTP_CAPTURE, sizeof(fal_ptp_capture_t), \
+		    SW_PARAM_PTR|SW_PARAM_IN, "Capture"),
+
+#define SW_API_PTP_CAPTURE_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_CAPTURE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_CAPTURE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_CAPTURE_GET, SW_UINT32, 4, SW_PARAM_IN, "Capture ID"), \
+    SW_PARAM_DEF(SW_API_PTP_CAPTURE_GET, SW_PTP_CAPTURE, sizeof(fal_ptp_capture_t), \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Capture"),
+
+#define SW_API_PTP_INTERRUPT_SET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_INTERRUPT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_INTERRUPT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_INTERRUPT_SET, SW_PTP_INTERRUPT, sizeof(SW_PTP_INTERRUPT), \
+		    SW_PARAM_PTR|SW_PARAM_IN, "Interrupt"),
+
+#define SW_API_PTP_INTERRUPT_GET_DESC \
+    SW_PARAM_DEF(SW_API_PTP_INTERRUPT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_PTP_INTERRUPT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_PTP_INTERRUPT_GET, SW_PTP_INTERRUPT, sizeof(SW_PTP_INTERRUPT), \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Interrupt"),
+
+#define SW_API_SFP_DATA_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_DATA_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_SFP_DATA_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_DATA_GET, SW_SFP_DATA, \
+		    sizeof(fal_sfp_data_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Data"),
+
+#define SW_API_SFP_DATA_SET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_DATA_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+    SW_PARAM_DEF(SW_API_SFP_DATA_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_DATA_SET, SW_SFP_DATA, \
+		    sizeof(fal_sfp_data_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Data"),
+
+#define SW_API_SFP_DEV_TYPE_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_DEV_TYPE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SFP_DEV_TYPE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_DEV_TYPE_GET, SW_SFP_DEV_TYPE, \
+		    sizeof(fal_sfp_dev_type_t), SW_PARAM_PTR|SW_PARAM_OUT, "Device Type"),
+
+#define SW_API_SFP_TRANSC_CODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_TRANSC_CODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SFP_TRANSC_CODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_TRANSC_CODE_GET, SW_SFP_TRANSC_CODE, \
+		    sizeof(fal_sfp_transc_code_t), SW_PARAM_PTR|SW_PARAM_OUT, "Transceiver Code"),
+
+#define SW_API_SFP_RATE_ENCODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_RATE_ENCODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SFP_RATE_ENCODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_RATE_ENCODE_GET, SW_SFP_RATE_ENCODE, \
+		    sizeof(fal_sfp_rate_encode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Rate Encode"),
+
+#define SW_API_SFP_LINK_LENGTH_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_LINK_LENGTH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SFP_LINK_LENGTH_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_LINK_LENGTH_GET, SW_SFP_LINK_LENGTH, \
+		    sizeof(fal_sfp_link_length_t), SW_PARAM_PTR|SW_PARAM_OUT, "Link Length"),
+
+#define SW_API_SFP_VENDOR_INFO_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_VENDOR_INFO_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SFP_VENDOR_INFO_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_VENDOR_INFO_GET, SW_SFP_VENDOR_INFO, \
+		    sizeof(fal_sfp_vendor_info_t), SW_PARAM_PTR|SW_PARAM_OUT, "Vendor Info"),
+
+#define SW_API_SFP_LASER_WAVELENGTH_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_LASER_WAVELENGTH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SFP_LASER_WAVELENGTH_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_LASER_WAVELENGTH_GET, SW_SFP_LASER_WAVELENGTH, \
+		    sizeof(fal_sfp_laser_wavelength_t), SW_PARAM_PTR|SW_PARAM_OUT, "Wave Length"),
+
+#define SW_API_SFP_OPTION_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_OPTION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SFP_OPTION_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_OPTION_GET, SW_SFP_OPTION, \
+		    sizeof(fal_sfp_option_t), SW_PARAM_PTR|SW_PARAM_OUT, "Option"),
+
+#define SW_API_SFP_CTRL_RATE_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_CTRL_RATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SFP_CTRL_RATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_CTRL_RATE_GET, SW_SFP_CTRL_RATE, \
+		    sizeof(fal_sfp_rate_t), SW_PARAM_PTR|SW_PARAM_OUT, "Control Rate"),
+
+#define SW_API_SFP_ENHANCED_CFG_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_ENHANCED_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SFP_ENHANCED_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_ENHANCED_CFG_GET, SW_SFP_ENHANCED_CFG, \
+		    sizeof(fal_sfp_enhanced_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "Enhanced Config"),
+
+#define SW_API_SFP_DIAG_THRESHOLD_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_DIAG_THRESHOLD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SFP_DIAG_THRESHOLD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_DIAG_THRESHOLD_GET, SW_SFP_DIAG_THRESHOLD, \
+		    sizeof(fal_sfp_internal_threshold_t), SW_PARAM_PTR|SW_PARAM_OUT, "Threshold"),
+
+#define SW_API_SFP_DIAG_CAL_CONST_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_DIAG_CAL_CONST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SFP_DIAG_CAL_CONST_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_DIAG_CAL_CONST_GET, SW_SFP_DIAG_CAL_CONST, \
+		    sizeof(fal_sfp_cal_const_t), SW_PARAM_PTR|SW_PARAM_OUT, "Calibration"),
+
+#define SW_API_SFP_DIAG_REALTIME_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_DIAG_REALTIME_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SFP_DIAG_REALTIME_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_DIAG_REALTIME_GET, SW_SFP_DIAG_REALTIME, \
+		    sizeof(fal_sfp_realtime_diag_t), SW_PARAM_PTR|SW_PARAM_OUT, "Realtime Diag"),
+
+#define SW_API_SFP_DIAG_CTRL_STATUS_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_DIAG_CTRL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SFP_DIAG_CTRL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_DIAG_CTRL_STATUS_GET, SW_SFP_CTRL_STATUS, \
+		    sizeof(fal_sfp_ctrl_status_t), SW_PARAM_PTR|SW_PARAM_OUT, "Control Status"),
+
+#define SW_API_SFP_DIAG_ALARM_WARN_FLAG_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_DIAG_ALARM_WARN_FLAG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SFP_DIAG_ALARM_WARN_FLAG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_DIAG_ALARM_WARN_FLAG_GET, SW_SFP_ALARM_WARN_FLAG, \
+		    sizeof(fal_sfp_alarm_warn_flag_t), SW_PARAM_PTR|SW_PARAM_OUT, "A/W Flag"),
+
+#define SW_API_SFP_CHECKCODE_GET_DESC \
+    SW_PARAM_DEF(SW_API_SFP_CHECKCODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SFP_CHECKCODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+    SW_PARAM_DEF(SW_API_SFP_CHECKCODE_GET, SW_SFP_CCODE_TYPE, \
+		    sizeof(fal_sfp_cc_type_t), SW_PARAM_IN, "Check Code Type"), \
+    SW_PARAM_DEF(SW_API_SFP_CHECKCODE_GET, SW_UINT8, \
+		    sizeof(a_uint8_t), SW_PARAM_PTR|SW_PARAM_OUT, "Check Code"),
+
+/*qca808x_start*/
+
+#define SW_API_DESC(api_id) api_id##_DESC
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _API_DESC_H_ */
+/*qca808x_end*/
+
diff --git a/qca-ssdk/include/api/sw_api.h b/qca-ssdk/include/api/sw_api.h
new file mode 100755
index 0000000..127fb59
--- /dev/null
+++ b/qca-ssdk/include/api/sw_api.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2012, 2015-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _SW_API_H
+#define _SW_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+
+#define SW_MAX_API_BUF         2048
+#define SW_MAX_API_PARAM       12 /* cmd type + return value + ten parameters */
+#define SW_MAX_PAYLOAD         (SW_MAX_API_PARAM << 2)  /* maximum payload size for netlink msg*/
+#define SW_PARAM_IN            0x1
+#define SW_PARAM_OUT           0x2
+#define SW_PARAM_PTR           0x4
+
+#define SW_API_DEF(ioctl, name) {ioctl, name}
+
+#define SW_PARAM_DEF(ioctl, data, size, type, name) {ioctl, size, data, type}
+
+typedef enum
+{
+	SW_UINT8 = 1,
+	SW_INT8,
+	SW_UINT16,
+	SW_INT16,
+	SW_UINT32,
+	SW_INT32,
+	SW_UINT64,
+	SW_INT64,
+	SW_ENABLE,
+	SW_SPEED,
+	SW_DUPLEX,
+	SW_1QMODE,
+	SW_EGMODE,
+	SW_CAP,
+	SW_VLAN,
+	SW_LAN_WAN_CFG,
+	SW_PBMP,
+	SW_MIB,
+	SW_MIB_CNTR,
+	SW_XGMIB,
+	SW_MACADDR,
+	SW_FDBENTRY,
+	SW_MACLIMIT_CTRL,
+	SW_SCH,
+	SW_QOS,
+	SW_STORM,
+	SW_STP,
+	SW_LEAKY,
+	SW_MACCMD,
+	SW_FLOWTYPE,
+	SW_FLOWCMD,
+	SW_UINT_A,
+	SW_ACLRULE,
+	SW_LEDPATTERN,
+	SW_INVLAN,
+	SW_VLANPROPAGATION,
+	SW_VLANTRANSLATION,
+	SW_QINQMODE,
+	SW_QINQROLE,
+	SW_CABLESTATUS,
+	SW_CABLELEN,
+	SW_SSDK_CFG,
+	SW_HDRMODE,
+	SW_FDBOPRATION,
+	SW_PPPOE,
+	SW_PPPOE_LESS,
+	SW_ACL_UDF_TYPE,
+	SW_IP_HOSTENTRY,
+	SW_ARP_LEARNMODE,
+	SW_IP_GUARDMODE,
+	SW_NATENTRY,
+	SW_NAPTENTRY,
+	SW_FLOWENTRY,
+	SW_NAPTMODE,
+	SW_IP4ADDR,
+	SW_IP6ADDR,
+	SW_INTFMACENTRY,
+	SW_PUBADDRENTRY,
+	SW_INGPOLICER,
+	SW_EGSHAPER,
+	SW_ACLPOLICER,
+	SW_MACCONFIG,
+	SW_PHYCONFIG,
+	SW_DATA_MAX,
+	SW_FDBSMODE,
+	SW_FX100CONFIG,
+	SW_SGENTRY,
+	SW_SEC_MAC,
+	SW_SEC_IP,
+	SW_SEC_IP4,
+	SW_SEC_IP6,
+	SW_SEC_TCP,
+	SW_SEC_UDP,
+	SW_SEC_ICMP4,
+	SW_SEC_ICMP6,
+	SW_REMARKENTRY,
+	SW_SGINFOENTRY,
+	SW_DEFAULT_ROUTE_ENTRY,
+	SW_HOST_ROUTE_ENTRY,
+	SW_IP_WCMP_ENTRY,
+	SW_IP_RFS_IP4,
+	SW_IP_RFS_IP6,
+	SW_FLOWCOOKIE,
+	SW_FDB_RFS,
+	SW_FLOWRFS,
+	SW_CROSSOVER_MODE,
+	SW_CROSSOVER_STATUS,
+	SW_PREFER_MEDIUM,
+	SW_FIBER_MODE,
+	SW_INTERFACE_MODE,
+	SW_COUNTER_INFO,
+	SW_REG_DUMP,
+	SW_DBG_REG_DUMP,
+	SW_VSI_NEWADDR_LRN,
+	SW_VSI_STAMOVE,
+	SW_VSI_MEMBER,
+	SW_VSI_COUNTER,
+	SW_MTU_INFO,
+	SW_MRU_INFO,
+	SW_MTU_ENTRY,
+	SW_MRU_ENTRY,
+	SW_FRAME_MAX_SIZE,
+	SW_SOURCE_FILTER,
+	SW_ARP_SG_CFG,
+	SW_IP_NETWORK_ROUTE,
+	SW_IP_INTF,
+	SW_IP_VSI_INTF,
+	SW_IP_NEXTHOP,
+	SW_UCAST_QUEUE_MAP,
+	SW_UCAST_PRI_CLASS,
+	SW_MCAST_PRI_CLASS,
+	SW_IP_SG,
+	SW_IP_PUB,
+	SW_IP_PORTMAC,
+	SW_IP_MCMODE,
+	SW_FLOW_AGE,
+	SW_FLOW_CTRL,
+	SW_AC_CTRL,
+	SW_AC_OBJ,
+	SW_STATIC_THRESH,
+	SW_DYNAMIC_THRESH,
+	SW_GROUP_BUFFER,
+	SW_FLOW_ENTRY,
+	SW_FLOW_HOST,
+	SW_IP_GLOBAL,
+	SW_FLOW_GLOBAL,
+	SW_GLOBAL_QINQMODE,
+	SW_PT_QINQMODE,
+	SW_TPID,
+	SW_INGRESS_FILTER,
+	SW_PT_DEF_VID_EN,
+	SW_PT_VLAN_TAG,
+	SW_PT_VLAN_DIRECTION,
+	SW_PT_VLAN_TRANS_ADV_RULE,
+	SW_PT_VLAN_TRANS_ADV_ACTION,
+	SW_PT_VLAN_COUNTER,
+	SW_DEBUG_COUNTER_EN,
+	SW_TAG_PROPAGATION,
+	SW_EGRESS_DEFAULT_VID,
+	SW_EGRESS_MODE,
+	SW_CTRLPKT_PROFILE,
+	SW_SERVCODE_CONFIG,
+	SW_RSS_HASH_MODE,
+	SW_RSS_HASH_CONFIG,
+	SW_MIRR_ANALYSIS_CONFIG,
+	SW_MIRR_DIRECTION,
+	SW_L3_PARSER,
+	SW_L4_PARSER,
+	SW_EXP_CTRL,
+	SW_ACL_UDF_PKT_TYPE,
+	SW_PORTGROUP,
+	SW_PORTPRI,
+	SW_PORTREMARK,
+	SW_COSMAP,
+	SW_SCHEDULER,
+	SW_QUEUEBMP,
+	SW_BMSTHRESH,
+	SW_BMDTHRESH,
+	SW_BMPORTCNT,
+	SW_PORT_SHAPER_TOKEN_CONFIG,
+	SW_SHAPER_TOKEN_CONFIG,
+	SW_PORT_SHAPER_CONFIG,
+	SW_SHAPER_CONFIG,
+	SW_MODULE,
+	SW_FUNC_CTRL,
+	SW_QM_CNT,
+	SW_POLICER_COUNTER,
+	SW_POLICER_PORT_CONFIG,
+	SW_POLICER_ACL_CONFIG,
+	SW_POLICER_CMD_CONFIG,
+	SW_POLICER_GLOBAL_COUNTER,
+	SW_PHY_DUMP,
+	SW_RESOURCE_SCHE,
+	SW_PTP_CONFIG,
+	SW_PTP_REFERENCE_CLOCK,
+	SW_PTP_RX_TIMESTAMP_MODE,
+	SW_PTP_DIRECTION,
+	SW_PTP_PKT_INFO,
+	SW_PTP_TIME,
+	SW_PTP_GRANDMASTER_MODE,
+	SW_PTP_SECURITY,
+	SW_PTP_PPS_SIGNAL_CONTROL,
+	SW_PTP_ASYM_CORRECTION,
+	SW_PTP_OUTPUT_WAVEFORM,
+	SW_PTP_TOD_UART,
+	SW_PTP_ENHANCED_TS_ENGINE,
+	SW_PTP_TRIGGER,
+	SW_PTP_CAPTURE,
+	SW_PTP_INTERRUPT,
+	SW_PORT_EEE_CONFIG,
+	SW_SRC_FILTER_CONFIG,
+	SW_PORT_LOOPBACK_CONFIG,
+	SW_SFP_DATA,
+	SW_SFP_DEV_TYPE,
+	SW_SFP_TRANSC_CODE,
+	SW_SFP_RATE_ENCODE,
+	SW_SFP_LINK_LENGTH,
+	SW_SFP_VENDOR_INFO,
+	SW_SFP_LASER_WAVELENGTH,
+	SW_SFP_OPTION,
+	SW_SFP_CTRL_RATE,
+	SW_SFP_ENHANCED_CFG,
+	SW_SFP_DIAG_THRESHOLD,
+	SW_SFP_DIAG_CAL_CONST,
+	SW_SFP_DIAG_REALTIME,
+	SW_SFP_CTRL_STATUS,
+	SW_SFP_ALARM_WARN_FLAG,
+	SW_SFP_CCODE_TYPE,
+} sw_data_type_e;
+
+    typedef struct
+    {
+        a_uint32_t api_id;
+        void *func;
+    } sw_api_func_t;
+
+    typedef struct
+    {
+        a_uint32_t api_id;
+        a_uint16_t data_size;
+        a_uint8_t  data_type;
+        a_uint8_t  param_type;
+    } sw_api_param_t;
+
+    typedef struct
+    {
+        a_uint32_t api_id;
+        sw_api_func_t *api_fp;
+        sw_api_param_t *api_pp;
+        a_uint32_t api_nr;
+    } sw_api_t;
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _SW_API_H */
diff --git a/qca-ssdk/include/api/sw_ioctl.h b/qca-ssdk/include/api/sw_ioctl.h
new file mode 100755
index 0000000..5c404e3
--- /dev/null
+++ b/qca-ssdk/include/api/sw_ioctl.h
@@ -0,0 +1,989 @@
+/*
+ * Copyright (c) 2012, 2015-2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/*qca808x_start*/
+#ifndef _SW_IOCTL_H_
+#define _SW_IOCTL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+    /*init*/
+#define SW_API_INIT_OFFSET         10
+#define SW_API_SWITCH_INIT         (0  + SW_API_INIT_OFFSET)
+#define SW_API_SWITCH_RESET        (1  + SW_API_INIT_OFFSET)
+#define SW_API_SSDK_CFG            (2  + SW_API_INIT_OFFSET)
+#define SW_API_MODULE_FUNC_CTRL_SET   (3  + SW_API_INIT_OFFSET)
+#define SW_API_MODULE_FUNC_CTRL_GET   (4  + SW_API_INIT_OFFSET)
+
+    /*port ctrl*/
+#define SW_API_PORT_OFFSET          30
+#define SW_API_PT_DUPLEX_GET        (0  + SW_API_PORT_OFFSET)
+#define SW_API_PT_DUPLEX_SET        (1  + SW_API_PORT_OFFSET)
+#define SW_API_PT_SPEED_GET         (2  + SW_API_PORT_OFFSET)
+#define SW_API_PT_SPEED_SET         (3  + SW_API_PORT_OFFSET)
+#define SW_API_PT_AN_ADV_GET        (4  + SW_API_PORT_OFFSET)
+#define SW_API_PT_AN_ADV_SET        (5  + SW_API_PORT_OFFSET)
+#define SW_API_PT_AN_GET            (6  + SW_API_PORT_OFFSET)
+#define SW_API_PT_AN_ENABLE         (7  + SW_API_PORT_OFFSET)
+#define SW_API_PT_AN_RESTART        (8  + SW_API_PORT_OFFSET)
+/*qca808x_end*/
+#define SW_API_PT_HDR_SET           (9  + SW_API_PORT_OFFSET)
+#define SW_API_PT_HDR_GET           (10 + SW_API_PORT_OFFSET)
+#define SW_API_PT_FLOWCTRL_SET      (11 + SW_API_PORT_OFFSET)
+#define SW_API_PT_FLOWCTRL_GET      (12 + SW_API_PORT_OFFSET)
+#define SW_API_PT_FLOWCTRL_MODE_SET (13 + SW_API_PORT_OFFSET)
+#define SW_API_PT_FLOWCTRL_MODE_GET (14 + SW_API_PORT_OFFSET)
+#define SW_API_PT_POWERSAVE_SET     (15 + SW_API_PORT_OFFSET)
+#define SW_API_PT_POWERSAVE_GET     (16 + SW_API_PORT_OFFSET)
+/*qca808x_start*/
+#define SW_API_PT_HIBERNATE_SET     (17 + SW_API_PORT_OFFSET)
+#define SW_API_PT_HIBERNATE_GET     (18 + SW_API_PORT_OFFSET)
+#define SW_API_PT_CDT               (19 + SW_API_PORT_OFFSET)
+/*qca808x_end*/
+#define SW_API_PT_TXHDR_SET         (20 + SW_API_PORT_OFFSET)
+#define SW_API_PT_TXHDR_GET         (21 + SW_API_PORT_OFFSET)
+#define SW_API_PT_RXHDR_SET         (22 + SW_API_PORT_OFFSET)
+#define SW_API_PT_RXHDR_GET         (23 + SW_API_PORT_OFFSET)
+#define SW_API_HEADER_TYPE_SET      (24 + SW_API_PORT_OFFSET)
+#define SW_API_HEADER_TYPE_GET      (25 + SW_API_PORT_OFFSET)
+#define SW_API_TXMAC_STATUS_SET     (26 + SW_API_PORT_OFFSET)
+#define SW_API_TXMAC_STATUS_GET     (27 + SW_API_PORT_OFFSET)
+#define SW_API_RXMAC_STATUS_SET     (28 + SW_API_PORT_OFFSET)
+#define SW_API_RXMAC_STATUS_GET     (29 + SW_API_PORT_OFFSET)
+#define SW_API_TXFC_STATUS_SET      (30 + SW_API_PORT_OFFSET)
+#define SW_API_TXFC_STATUS_GET      (31 + SW_API_PORT_OFFSET)
+#define SW_API_RXFC_STATUS_SET      (32 + SW_API_PORT_OFFSET)
+#define SW_API_RXFC_STATUS_GET      (33 + SW_API_PORT_OFFSET)
+#define SW_API_BP_STATUS_SET        (34 + SW_API_PORT_OFFSET)
+#define SW_API_BP_STATUS_GET        (35 + SW_API_PORT_OFFSET)
+#define SW_API_PT_LINK_MODE_SET     (36 + SW_API_PORT_OFFSET)
+#define SW_API_PT_LINK_MODE_GET     (37 + SW_API_PORT_OFFSET)
+/*qca808x_start*/
+#define SW_API_PT_LINK_STATUS_GET   (38 + SW_API_PORT_OFFSET)
+/*qca808x_end*/
+#define SW_API_PT_MAC_LOOPBACK_SET   (39+ SW_API_PORT_OFFSET)
+#define SW_API_PT_MAC_LOOPBACK_GET   (40+ SW_API_PORT_OFFSET)
+#define SW_API_PTS_LINK_STATUS_GET   (41 + SW_API_PORT_OFFSET)
+#define SW_API_PT_CONGESTION_DROP_SET   (42+ SW_API_PORT_OFFSET)
+#define SW_API_PT_CONGESTION_DROP_GET   (43+ SW_API_PORT_OFFSET)
+#define SW_API_PT_RING_FLOW_CTRL_THRES_SET   (44+ SW_API_PORT_OFFSET)
+#define SW_API_PT_RING_FLOW_CTRL_THRES_GET   (45+ SW_API_PORT_OFFSET)
+/*qca808x_start*/
+#define SW_API_PT_8023AZ_SET     (46 + SW_API_PORT_OFFSET)
+#define SW_API_PT_8023AZ_GET     (47 + SW_API_PORT_OFFSET)
+#define SW_API_PT_MDIX_SET  (48 + SW_API_PORT_OFFSET)
+#define SW_API_PT_MDIX_GET  (49 + SW_API_PORT_OFFSET)
+#define SW_API_PT_MDIX_STATUS_GET  (50 + SW_API_PORT_OFFSET)
+/*qca808x_end*/
+#define SW_API_PT_COMBO_PREFER_MEDIUM_SET (51 + SW_API_PORT_OFFSET)
+#define SW_API_PT_COMBO_PREFER_MEDIUM_GET  (52 + SW_API_PORT_OFFSET)
+#define SW_API_PT_COMBO_MEDIUM_STATUS_GET  (53 + SW_API_PORT_OFFSET)
+#define SW_API_PT_COMBO_FIBER_MODE_SET  (54 + SW_API_PORT_OFFSET)
+#define SW_API_PT_COMBO_FIBER_MODE_GET  (55 + SW_API_PORT_OFFSET)
+/*qca808x_start*/
+#define SW_API_PT_LOCAL_LOOPBACK_SET  (56 + SW_API_PORT_OFFSET)
+#define SW_API_PT_LOCAL_LOOPBACK_GET  (57 + SW_API_PORT_OFFSET)
+#define SW_API_PT_REMOTE_LOOPBACK_SET  (58 + SW_API_PORT_OFFSET)
+#define SW_API_PT_REMOTE_LOOPBACK_GET  (59 + SW_API_PORT_OFFSET)
+#define SW_API_PT_RESET  (60 + SW_API_PORT_OFFSET)
+#define SW_API_PT_POWER_OFF  (61 + SW_API_PORT_OFFSET)
+#define SW_API_PT_POWER_ON  (62 + SW_API_PORT_OFFSET)
+#define SW_API_PT_MAGIC_FRAME_MAC_SET  (63 + SW_API_PORT_OFFSET)
+#define SW_API_PT_MAGIC_FRAME_MAC_GET  (64 + SW_API_PORT_OFFSET)
+#define SW_API_PT_PHY_ID_GET  (65 + SW_API_PORT_OFFSET)
+#define SW_API_PT_WOL_STATUS_SET  (66 + SW_API_PORT_OFFSET)
+#define SW_API_PT_WOL_STATUS_GET  (67 + SW_API_PORT_OFFSET)
+/*qca808x_end*/
+#define SW_API_PT_INTERFACE_MODE_SET  (68 + SW_API_PORT_OFFSET)
+#define SW_API_PT_INTERFACE_MODE_GET  (69 + SW_API_PORT_OFFSET)
+/*qca808x_start*/
+#define SW_API_PT_INTERFACE_MODE_STATUS_GET  (70 + SW_API_PORT_OFFSET)
+#define SW_API_DEBUG_PHYCOUNTER_SET  (71 + SW_API_PORT_OFFSET)
+#define SW_API_DEBUG_PHYCOUNTER_GET  (72 + SW_API_PORT_OFFSET)
+#define SW_API_DEBUG_PHYCOUNTER_SHOW  (73 + SW_API_PORT_OFFSET)
+/*qca808x_end*/
+#define SW_API_PT_INTERFACE_MODE_APPLY  (74 + SW_API_PORT_OFFSET)
+#define SW_API_PT_INTERFACE_3AZ_STATUS_SET  (75 + SW_API_PORT_OFFSET)
+#define SW_API_PT_INTERFACE_3AZ_STATUS_GET  (76 + SW_API_PORT_OFFSET)
+#define SW_API_PT_PROMISC_MODE_SET   (77  + SW_API_PORT_OFFSET)
+#define SW_API_PT_PROMISC_MODE_GET   (78  + SW_API_PORT_OFFSET)
+#define SW_API_PT_INTERFACE_EEE_CFG_SET  (79 + SW_API_PORT_OFFSET)
+#define SW_API_PT_INTERFACE_EEE_CFG_GET  (80 + SW_API_PORT_OFFSET)
+#define SW_API_PT_SWITCH_PORT_LOOPBACK_SET  (81 + SW_API_PORT_OFFSET)
+#define SW_API_PT_SWITCH_PORT_LOOPBACK_GET  (82 + SW_API_PORT_OFFSET)
+
+
+    /*vlan*/
+#define SW_API_VLAN_OFFSET         130
+#define SW_API_VLAN_ADD            (0 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_DEL            (1 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_MEM_UPDATE     (2 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_FIND           (3 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_NEXT           (4 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_APPEND         (5 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_FLUSH          (6 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_FID_SET        (7 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_FID_GET        (8 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_MEMBER_ADD     (9 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_MEMBER_DEL     (10 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_LEARN_STATE_SET (11 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_LEARN_STATE_GET (12 + SW_API_VLAN_OFFSET)
+#define SW_API_LAN_WAN_CFG_SET      (13 + SW_API_VLAN_OFFSET)
+#define SW_API_LAN_WAN_CFG_GET      (14 + SW_API_VLAN_OFFSET)
+
+    /*port ctrl extend*/
+#define SW_API_PORT_EXT_OFFSET		160
+#define SW_API_PT_MTU_SET  (0 + SW_API_PORT_EXT_OFFSET)
+#define SW_API_PT_MTU_GET  (1 + SW_API_PORT_EXT_OFFSET)
+#define SW_API_PT_MRU_SET  (2 + SW_API_PORT_EXT_OFFSET)
+#define SW_API_PT_MRU_GET  (3 + SW_API_PORT_EXT_OFFSET)
+#define SW_API_PT_SOURCE_FILTER_GET (4 + SW_API_PORT_EXT_OFFSET)
+#define SW_API_PT_SOURCE_FILTER_SET (5 + SW_API_PORT_EXT_OFFSET)
+#define SW_API_PT_FRAME_MAX_SIZE_GET (6 + SW_API_PORT_EXT_OFFSET)
+#define SW_API_PT_FRAME_MAX_SIZE_SET (7 + SW_API_PORT_EXT_OFFSET)
+#define SW_API_PT_SOURCE_FILTER_CONFIG_GET (8 + SW_API_PORT_EXT_OFFSET)
+#define SW_API_PT_SOURCE_FILTER_CONFIG_SET (9 + SW_API_PORT_EXT_OFFSET)
+
+
+    /*portvlan*/
+#define SW_API_PORTVLAN_OFFSET       200
+#define SW_API_PT_ING_MODE_GET       (0  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_ING_MODE_SET       (1  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_EG_MODE_GET        (2  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_EG_MODE_SET        (3  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_MEM_ADD       (4  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_MEM_DEL       (5  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_MEM_UPDATE    (6  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_MEM_GET       (7  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_DEF_VID_GET        (8  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_DEF_VID_SET        (9  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_FORCE_DEF_VID_SET  (10  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_FORCE_DEF_VID_GET  (11  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_FORCE_PORTVLAN_SET (12  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_FORCE_PORTVLAN_GET (13  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_NESTVLAN_SET       (14  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_NESTVLAN_GET       (15  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_NESTVLAN_TPID_SET     (16  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_NESTVLAN_TPID_GET     (17  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_IN_VLAN_MODE_SET   (18  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_IN_VLAN_MODE_GET   (19  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_TLS_SET            (20  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_TLS_GET            (21  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_PRI_PROPAGATION_SET  (22  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_PRI_PROPAGATION_GET  (23  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_DEF_SVID_SET       (24  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_DEF_SVID_GET       (25  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_DEF_CVID_SET       (26  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_DEF_CVID_GET       (27  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_PROPAGATION_SET (28  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_PROPAGATION_GET (29  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_TRANS_ADD     (30  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_TRANS_DEL     (31  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_TRANS_GET     (32  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_QINQ_MODE_SET         (33  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_QINQ_MODE_GET         (34  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_QINQ_ROLE_SET      (35  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_QINQ_ROLE_GET      (36  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_TRANS_ITERATE (37  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_MAC_VLAN_XLT_SET   (38  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_MAC_VLAN_XLT_GET   (39  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_NETISOLATE_SET   (40  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_NETISOLATE_GET   (41  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_EG_FLTR_BYPASS_EN_SET (42 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_EG_FLTR_BYPASS_EN_GET (43 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VRF_ID_SET            (44  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VRF_ID_GET            (45  + SW_API_PORTVLAN_OFFSET)
+
+#define SW_API_GLOBAL_QINQ_MODE_SET (46  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_GLOBAL_QINQ_MODE_GET (47  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PORT_QINQ_MODE_SET (48  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PORT_QINQ_MODE_GET (49  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_TPID_SET (50  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_TPID_GET (51  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_EGRESS_TPID_SET (52  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_EGRESS_TPID_GET (53  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_INGRESS_VLAN_FILTER_SET (54  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_INGRESS_VLAN_FILTER_GET (55  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_DEFAULT_VLANTAG_SET (56  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_DEFAULT_VLANTAG_GET (57  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_TAG_PROPAGATION_SET (58  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_TAG_PROPAGATION_GET (59  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLANTAG_EGMODE_SET (60  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLANTAG_EGMODE_GET (61  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_XLT_MISS_CMD_SET (62  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_XLT_MISS_CMD_GET (63  + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VSI_EGMODE_SET (64 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VSI_EGMODE_GET (65 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET (66 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET (67 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_TRANS_ADV_ADD (68 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_TRANS_ADV_DEL (69 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_TRANS_ADV_GETFIRST (70 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_TRANS_ADV_GETNEXT (71 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_COUNTER_GET (72 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_COUNTER_CLEANUP (73 + SW_API_PORTVLAN_OFFSET)
+
+
+    /*fdb*/
+#define SW_API_FDB_OFFSET             300
+#define SW_API_FDB_ADD                (0  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_DELALL             (1  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_DELPORT            (2  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_DELMAC             (3  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_FIRST              (4  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_NEXT               (5  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_FIND               (6  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PT_LEARN_SET       (7  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PT_LEARN_GET       (8  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_AGE_CTRL_SET       (9  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_AGE_CTRL_GET       (10  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_AGE_TIME_SET       (11  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_AGE_TIME_GET       (12  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_ITERATE            (13  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_EXTEND_NEXT        (14  + SW_API_FDB_OFFSET)
+#define SW_API_PT_FDB_LEARN_LIMIT_SET (15  + SW_API_FDB_OFFSET)
+#define SW_API_PT_FDB_LEARN_LIMIT_GET (16  + SW_API_FDB_OFFSET)
+#define SW_API_PT_FDB_LEARN_EXCEED_CMD_SET (17  + SW_API_FDB_OFFSET)
+#define SW_API_PT_FDB_LEARN_EXCEED_CMD_GET (18  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_LEARN_LIMIT_SET         (19  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_LEARN_LIMIT_GET         (20  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_LEARN_EXCEED_CMD_SET    (21  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_LEARN_EXCEED_CMD_GET    (22  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_RESV_ADD                (23  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_RESV_DEL                (24  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_RESV_FIND               (25  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_RESV_ITERATE            (26  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_EXTEND_FIRST            (27  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PT_LEARN_STATIC_SET     (28  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PT_LEARN_STATIC_GET     (29  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_TRANSFER                (30  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PORT_ADD                (31  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PORT_DEL                (32  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_VLAN_IVL_SVL_SET        (33  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_VLAN_IVL_SVL_GET        (34  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_RFS_SET                 (35  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_RFS_DEL                 (36  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_LEARN_CTRL_SET          (37  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_LEARN_CTRL_GET          (38  + SW_API_FDB_OFFSET)
+#define SW_API_PT_FDB_LEARN_COUNTER_GET    (39  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PT_NEWADDR_LEARN_SET    (40  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PT_NEWADDR_LEARN_GET    (41  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PT_STAMOVE_SET          (42  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PT_STAMOVE_GET          (43  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PT_MACLIMIT_CTRL_SET    (44  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PT_MACLIMIT_CTRL_GET    (45  + SW_API_FDB_OFFSET)
+#define SW_API_FDB_DEL_BY_FID              (46  + SW_API_FDB_OFFSET)
+
+
+    /*acl*/
+#define SW_API_ACL_OFFSET             400
+#define SW_API_ACL_LIST_CREAT         (0  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_LIST_DESTROY       (1  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_ADD           (2  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_DELETE        (3  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_QUERY         (4  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_LIST_BIND          (5  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_LIST_UNBIND        (6  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_STATUS_SET         (7  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_STATUS_GET         (8  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_LIST_DUMP          (9  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_DUMP          (10  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_PT_UDF_PROFILE_SET (11  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_PT_UDF_PROFILE_GET (12  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_ACTIVE        (13  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_DEACTIVE      (14  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_SRC_FILTER_STS_SET      (15  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_SRC_FILTER_STS_GET      (16  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_GET_OFFSET      (17  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_UDF_SET (18  + SW_API_ACL_OFFSET)
+#define SW_API_ACL_UDF_GET (19  + SW_API_ACL_OFFSET)
+
+    /*qos*/
+#define SW_API_QOS_OFFSET             500
+#define SW_API_QOS_SCH_MODE_SET       (0  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_SCH_MODE_GET       (1  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_QU_TX_BUF_ST_SET   (2  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_QU_TX_BUF_ST_GET   (3  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_QU_TX_BUF_NR_SET   (4  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_QU_TX_BUF_NR_GET   (5  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_TX_BUF_ST_SET   (6  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_TX_BUF_ST_GET   (7  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_TX_BUF_NR_SET   (8  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_TX_BUF_NR_GET   (9  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_RX_BUF_NR_SET   (10  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_RX_BUF_NR_GET   (11  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_MODE_SET        (12  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_MODE_GET        (13  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_MODE_PRI_SET    (14  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_MODE_PRI_GET    (15  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_DEF_UP_SET    (16  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_DEF_UP_GET    (17  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_SCH_MODE_SET  (18  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_SCH_MODE_GET  (19  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_DEF_SPRI_SET    (20  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_DEF_SPRI_GET    (21  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_DEF_CPRI_SET    (22  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_DEF_CPRI_GET    (23  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_FORCE_SPRI_ST_SET   (24  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_FORCE_SPRI_ST_GET   (25  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_FORCE_CPRI_ST_SET   (26  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_FORCE_CPRI_ST_GET   (27  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_QUEUE_REMARK_SET   (28  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_QUEUE_REMARK_GET   (29  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_RED_EN_SET   (30  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_RED_EN_GET   (31  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_GROUP_GET   (32  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_GROUP_SET   (33  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_PRI_GET   (34  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_PRI_SET   (35  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_REMARK_GET   (36  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_REMARK_SET   (37  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PCP_MAP_GET   (38  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PCP_MAP_SET   (39  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_FLOW_MAP_GET   (40  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_FLOW_MAP_SET   (41  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_DSCP_MAP_GET   (42  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_DSCP_MAP_SET   (43  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_QUEUE_SCHEDULER_GET   (44  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_QUEUE_SCHEDULER_SET   (45  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_RING_QUEUE_MAP_GET   (46  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_RING_QUEUE_MAP_SET   (47  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_QUEUES_GET	(48  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_SCHEDULER_DEQUEU_CTRL_GET (49  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET (50  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_SCHEDULER_CFG_RESET (51  + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_SCHEDULER_RESOURCE_GET (52  + SW_API_QOS_OFFSET)
+
+    /* igmp */
+#define SW_API_IGMP_OFFSET            600
+#define SW_API_PT_IGMPS_MODE_SET      (0  + SW_API_IGMP_OFFSET)
+#define SW_API_PT_IGMPS_MODE_GET      (1 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_MLD_CMD_SET       (2  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_MLD_CMD_GET       (3  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_PT_JOIN_SET       (4  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_PT_JOIN_GET       (5  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_PT_LEAVE_SET      (6  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_PT_LEAVE_GET      (7  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_RP_SET            (8  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_RP_GET            (9  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_CREAT_SET   (10  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_CREAT_GET   (11  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_STATIC_SET  (12  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_STATIC_GET  (13  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_LEAKY_SET   (14  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_LEAKY_GET   (15  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_V3_SET      (16  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_V3_GET      (17  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_QUEUE_SET   (18  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_QUEUE_GET   (19  + SW_API_IGMP_OFFSET)
+#define SW_API_PT_IGMP_LEARN_LIMIT_SET (20  + SW_API_IGMP_OFFSET)
+#define SW_API_PT_IGMP_LEARN_LIMIT_GET (21  + SW_API_IGMP_OFFSET)
+#define SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET (22  + SW_API_IGMP_OFFSET)
+#define SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET (23  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_SG_ENTRY_SET (24  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_SG_ENTRY_CLEAR (25  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_SG_ENTRY_SHOW (26  + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_SG_ENTRY_QUERY (27  + SW_API_IGMP_OFFSET)
+
+    /* leaky */
+#define SW_API_LEAKY_OFFSET           700
+#define SW_API_UC_LEAKY_MODE_SET      (0  + SW_API_LEAKY_OFFSET)
+#define SW_API_UC_LEAKY_MODE_GET      (1  + SW_API_LEAKY_OFFSET)
+#define SW_API_MC_LEAKY_MODE_SET      (2  + SW_API_LEAKY_OFFSET)
+#define SW_API_MC_LEAKY_MODE_GET      (3  + SW_API_LEAKY_OFFSET)
+#define SW_API_ARP_LEAKY_MODE_SET     (4  + SW_API_LEAKY_OFFSET)
+#define SW_API_ARP_LEAKY_MODE_GET     (5  + SW_API_LEAKY_OFFSET)
+#define SW_API_PT_UC_LEAKY_MODE_SET   (6  + SW_API_LEAKY_OFFSET)
+#define SW_API_PT_UC_LEAKY_MODE_GET   (7  + SW_API_LEAKY_OFFSET)
+#define SW_API_PT_MC_LEAKY_MODE_SET   (8  + SW_API_LEAKY_OFFSET)
+#define SW_API_PT_MC_LEAKY_MODE_GET   (9  + SW_API_LEAKY_OFFSET)
+
+    /*mirror*/
+#define SW_API_MIR_OFFSET             800
+#define SW_API_MIRROR_ANALY_PT_SET    (0  + SW_API_MIR_OFFSET)
+#define SW_API_MIRROR_ANALY_PT_GET    (1  + SW_API_MIR_OFFSET)
+#define SW_API_MIRROR_IN_PT_SET       (2  + SW_API_MIR_OFFSET)
+#define SW_API_MIRROR_IN_PT_GET       (3  + SW_API_MIR_OFFSET)
+#define SW_API_MIRROR_EG_PT_SET       (4  + SW_API_MIR_OFFSET)
+#define SW_API_MIRROR_EG_PT_GET       (5  + SW_API_MIR_OFFSET)
+#define SW_API_MIRROR_ANALYSIS_CONFIG_SET	(6  + SW_API_MIR_OFFSET)
+#define SW_API_MIRROR_ANALYSIS_CONFIG_GET	(7  + SW_API_MIR_OFFSET)
+
+    /*rate*/
+#define SW_API_RATE_OFFSET            900
+#define SW_API_RATE_QU_EGRL_SET       (0  + SW_API_RATE_OFFSET)
+#define SW_API_RATE_QU_EGRL_GET       (1  + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PT_EGRL_SET       (2  + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PT_EGRL_GET       (3  + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PT_INRL_SET       (4  + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PT_INRL_GET       (5  + SW_API_RATE_OFFSET)
+#define SW_API_STORM_CTRL_FRAME_SET   (6  + SW_API_RATE_OFFSET)
+#define SW_API_STORM_CTRL_FRAME_GET   (7  + SW_API_RATE_OFFSET)
+#define SW_API_STORM_CTRL_RATE_SET    (8  + SW_API_RATE_OFFSET)
+#define SW_API_STORM_CTRL_RATE_GET    (9  + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PORT_POLICER_SET  (10  + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PORT_POLICER_GET  (11  + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PORT_SHAPER_SET   (12  + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PORT_SHAPER_GET   (13  + SW_API_RATE_OFFSET)
+#define SW_API_RATE_QUEUE_SHAPER_SET  (14  + SW_API_RATE_OFFSET)
+#define SW_API_RATE_QUEUE_SHAPER_GET  (15  + SW_API_RATE_OFFSET)
+#define SW_API_RATE_ACL_POLICER_SET   (16  + SW_API_RATE_OFFSET)
+#define SW_API_RATE_ACL_POLICER_GET   (17  + SW_API_RATE_OFFSET)
+#define  SW_API_RATE_PT_ADDRATEBYTE_SET   (18  + SW_API_RATE_OFFSET)
+#define  SW_API_RATE_PT_ADDRATEBYTE_GET   (19  + SW_API_RATE_OFFSET)
+#define  SW_API_RATE_PT_GOL_FLOW_EN_SET   (20  + SW_API_RATE_OFFSET)
+#define  SW_API_RATE_PT_GOL_FLOW_EN_GET   (21  + SW_API_RATE_OFFSET)
+
+    /*stp*/
+#define SW_API_STP_OFFSET             1000
+#define SW_API_STP_PT_STATE_SET       (0  + SW_API_STP_OFFSET)
+#define SW_API_STP_PT_STATE_GET       (1  + SW_API_STP_OFFSET)
+
+    /*mib*/
+#define SW_API_MIB_OFFSET             1100
+#define SW_API_PT_MIB_GET             (0  + SW_API_MIB_OFFSET)
+#define SW_API_MIB_STATUS_SET         (1  + SW_API_MIB_OFFSET)
+#define SW_API_MIB_STATUS_GET         (2  + SW_API_MIB_OFFSET)
+#define SW_API_PT_MIB_FLUSH_COUNTERS  (3+ SW_API_MIB_OFFSET)
+#define SW_API_MIB_CPU_KEEP_SET       (4+ SW_API_MIB_OFFSET)
+#define SW_API_MIB_CPU_KEEP_GET       (5+ SW_API_MIB_OFFSET)
+#define SW_API_PT_XGMIB_GET           (6+ SW_API_MIB_OFFSET)
+#define SW_API_PT_MIB_COUNTER_GET     (7+ SW_API_MIB_OFFSET)
+
+    /*misc*/
+#define SW_API_MISC_OFFSET            1200
+#define SW_API_ARP_STATUS_SET         (0  + SW_API_MISC_OFFSET)
+#define SW_API_ARP_STATUS_GET         (1  + SW_API_MISC_OFFSET)
+#define SW_API_FRAME_MAX_SIZE_SET     (2  + SW_API_MISC_OFFSET)
+#define SW_API_FRAME_MAX_SIZE_GET     (3  + SW_API_MISC_OFFSET)
+#define SW_API_PT_UNK_SA_CMD_SET      (4  + SW_API_MISC_OFFSET)
+#define SW_API_PT_UNK_SA_CMD_GET      (5  + SW_API_MISC_OFFSET)
+#define SW_API_PT_UNK_UC_FILTER_SET   (6  + SW_API_MISC_OFFSET)
+#define SW_API_PT_UNK_UC_FILTER_GET   (7  + SW_API_MISC_OFFSET)
+#define SW_API_PT_UNK_MC_FILTER_SET   (8  + SW_API_MISC_OFFSET)
+#define SW_API_PT_UNK_MC_FILTER_GET   (9  + SW_API_MISC_OFFSET)
+#define SW_API_PT_BC_FILTER_SET       (10  + SW_API_MISC_OFFSET)
+#define SW_API_PT_BC_FILTER_GET       (11  + SW_API_MISC_OFFSET)
+#define SW_API_CPU_PORT_STATUS_SET    (12  + SW_API_MISC_OFFSET)
+#define SW_API_CPU_PORT_STATUS_GET    (13  + SW_API_MISC_OFFSET)
+#define SW_API_BC_TO_CPU_PORT_SET     (14  + SW_API_MISC_OFFSET)
+#define SW_API_BC_TO_CPU_PORT_GET     (15  + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_CMD_SET          (16  + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_CMD_GET          (17  + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_STATUS_SET       (18  + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_STATUS_GET       (19  + SW_API_MISC_OFFSET)
+#define SW_API_PT_DHCP_SET            (20  + SW_API_MISC_OFFSET)
+#define SW_API_PT_DHCP_GET            (21  + SW_API_MISC_OFFSET)
+#define SW_API_ARP_CMD_SET            (22  + SW_API_MISC_OFFSET)
+#define SW_API_ARP_CMD_GET            (23  + SW_API_MISC_OFFSET)
+#define SW_API_EAPOL_CMD_SET          (24  + SW_API_MISC_OFFSET)
+#define SW_API_EAPOL_CMD_GET          (25  + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_ADD      (26  + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_DEL      (27  + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_GET      (28  + SW_API_MISC_OFFSET)
+#define SW_API_EAPOL_STATUS_SET       (29  + SW_API_MISC_OFFSET)
+#define SW_API_EAPOL_STATUS_GET       (30  + SW_API_MISC_OFFSET)
+#define SW_API_RIPV1_STATUS_SET       (31  + SW_API_MISC_OFFSET)
+#define SW_API_RIPV1_STATUS_GET       (32  + SW_API_MISC_OFFSET)
+#define SW_API_PT_ARP_REQ_STATUS_SET         (33  + SW_API_MISC_OFFSET)
+#define SW_API_PT_ARP_REQ_STATUS_GET         (34  + SW_API_MISC_OFFSET)
+#define SW_API_PT_ARP_ACK_STATUS_SET         (35  + SW_API_MISC_OFFSET)
+#define SW_API_PT_ARP_ACK_STATUS_GET         (36  + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_TABLE_ADD      (37  + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_TABLE_DEL      (38  + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_TABLE_GET      (39  + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_ID_SET         (40  + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_ID_GET         (41  + SW_API_MISC_OFFSET)
+#define SW_API_INTR_MASK_SET                (42  + SW_API_MISC_OFFSET)
+#define SW_API_INTR_MASK_GET                (43  + SW_API_MISC_OFFSET)
+#define SW_API_INTR_STATUS_GET              (44  + SW_API_MISC_OFFSET)
+#define SW_API_INTR_STATUS_CLEAR            (45  + SW_API_MISC_OFFSET)
+#define SW_API_INTR_PORT_LINK_MASK_SET      (46  + SW_API_MISC_OFFSET)
+#define SW_API_INTR_PORT_LINK_MASK_GET      (47  + SW_API_MISC_OFFSET)
+#define SW_API_INTR_PORT_LINK_STATUS_GET    (48  + SW_API_MISC_OFFSET)
+#define SW_API_INTR_MASK_MAC_LINKCHG_SET      (49  + SW_API_MISC_OFFSET)
+#define SW_API_INTR_MASK_MAC_LINKCHG_GET      (50  + SW_API_MISC_OFFSET)
+#define SW_API_INTR_STATUS_MAC_LINKCHG_GET    (51  + SW_API_MISC_OFFSET)
+#define SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR    (52 + SW_API_MISC_OFFSET)
+#define SW_API_CPU_VID_EN_SET      (53  + SW_API_MISC_OFFSET)
+#define SW_API_CPU_VID_EN_GET    (54  + SW_API_MISC_OFFSET)
+#define SW_API_RTD_PPPOE_EN_SET      (55  + SW_API_MISC_OFFSET)
+#define SW_API_RTD_PPPOE_EN_GET    (56  + SW_API_MISC_OFFSET)
+#define SW_API_GLOBAL_MACADDR_SET      (57  + SW_API_MISC_OFFSET)
+#define SW_API_GLOBAL_MACADDR_GET    (58  + SW_API_MISC_OFFSET)
+#define SW_API_LLDP_STATUS_SET          (59  + SW_API_MISC_OFFSET)
+#define SW_API_LLDP_STATUS_GET          (60  + SW_API_MISC_OFFSET)
+#define SW_API_FRAME_CRC_RESERVE_SET          (61  + SW_API_MISC_OFFSET)
+#define SW_API_FRAME_CRC_RESERVE_GET          (62  + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_EN_SET			(63  + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_EN_GET			(64  + SW_API_MISC_OFFSET)
+#define SW_API_DEBUG_PORT_COUNTER_ENABLE 	(65  + SW_API_MISC_OFFSET)
+#define SW_API_DEBUG_PORT_COUNTER_STATUS_GET	(66  + SW_API_MISC_OFFSET)
+
+    /*led*/
+#define SW_API_LED_OFFSET             1300
+#define SW_API_LED_PATTERN_SET        (0  + SW_API_LED_OFFSET)
+#define SW_API_LED_PATTERN_GET        (1  + SW_API_LED_OFFSET)
+
+    /* cosmap */
+#define SW_API_COSMAP_OFFSET              1400
+#define SW_API_COSMAP_UP_QU_SET           (0  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_UP_QU_GET           (1  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_QU_SET         (2  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_QU_GET         (3  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_TO_PRI_SET     (4  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_TO_PRI_GET     (5  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_TO_DP_SET      (6  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_TO_DP_GET      (7  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_UP_TO_PRI_SET       (8  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_UP_TO_PRI_GET       (9  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_UP_TO_DP_SET        (10  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_UP_TO_DP_GET        (11  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_PRI_TO_QU_SET       (12  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_PRI_TO_QU_GET       (13  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_PRI_TO_EHQU_SET     (14  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_PRI_TO_EHQU_GET     (15  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_EG_REMARK_SET       (16  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_EG_REMARK_GET       (17  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_TO_EHPRI_SET     (18  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_TO_EHPRI_GET     (19  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_TO_EHDP_SET      (20  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_TO_EHDP_GET      (21  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_UP_TO_EHPRI_SET       (22  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_UP_TO_EHPRI_GET       (23  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_UP_TO_EHDP_SET        (24  + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_UP_TO_EHDP_GET        (25  + SW_API_COSMAP_OFFSET)
+
+    /* sec */
+#define SW_API_SEC_OFFSET             1500
+#define SW_API_SEC_NORM_SET           (0  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_NORM_GET           (1  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_MAC_SET            (2  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_MAC_GET            (3  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_IP_SET             (4  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_IP_GET             (5  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_IP4_SET            (6  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_IP4_GET            (7  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_IP6_SET            (8  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_IP6_GET            (9  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_TCP_SET            (10  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_TCP_GET            (11  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_UDP_SET            (12  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_UDP_GET            (13  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_ICMP4_SET          (14  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_ICMP4_GET          (15  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_ICMP6_SET          (16  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_ICMP6_GET          (17  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_L3_PARSER_CTRL_GET          (18  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_L3_PARSER_CTRL_SET          (19  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_L4_PARSER_CTRL_GET          (20  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_L4_PARSER_CTRL_SET          (21  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_EXP_CTRL_GET          (22  + SW_API_SEC_OFFSET)
+#define SW_API_SEC_EXP_CTRL_SET          (23  + SW_API_SEC_OFFSET)
+
+    /* ip */
+#define SW_API_IP_OFFSET             1600
+#define SW_API_IP_HOST_ADD           (0  + SW_API_IP_OFFSET)
+#define SW_API_IP_HOST_DEL           (1  + SW_API_IP_OFFSET)
+#define SW_API_IP_HOST_GET           (2  + SW_API_IP_OFFSET)
+#define SW_API_IP_HOST_NEXT          (3  + SW_API_IP_OFFSET)
+#define SW_API_IP_HOST_COUNTER_BIND  (4  + SW_API_IP_OFFSET)
+#define SW_API_IP_HOST_PPPOE_BIND    (5  + SW_API_IP_OFFSET)
+#define SW_API_IP_PT_ARP_LEARN_SET   (6  + SW_API_IP_OFFSET)
+#define SW_API_IP_PT_ARP_LEARN_GET   (7  + SW_API_IP_OFFSET)
+#define SW_API_IP_ARP_LEARN_SET      (8  + SW_API_IP_OFFSET)
+#define SW_API_IP_ARP_LEARN_GET      (9  + SW_API_IP_OFFSET)
+#define SW_API_IP_SOURCE_GUARD_SET   (10  + SW_API_IP_OFFSET)
+#define SW_API_IP_SOURCE_GUARD_GET   (11  + SW_API_IP_OFFSET)
+#define SW_API_IP_ARP_GUARD_SET      (12  + SW_API_IP_OFFSET)
+#define SW_API_IP_ARP_GUARD_GET      (13  + SW_API_IP_OFFSET)
+#define SW_API_IP_ROUTE_STATUS_SET   (14  + SW_API_IP_OFFSET)
+#define SW_API_IP_ROUTE_STATUS_GET   (15  + SW_API_IP_OFFSET)
+#define SW_API_IP_INTF_ENTRY_ADD       (16  + SW_API_IP_OFFSET)
+#define SW_API_IP_INTF_ENTRY_DEL       (17  + SW_API_IP_OFFSET)
+#define SW_API_IP_INTF_ENTRY_NEXT      (18  + SW_API_IP_OFFSET)
+#define SW_API_IP_UNK_SOURCE_CMD_SET (19  + SW_API_IP_OFFSET)
+#define SW_API_IP_UNK_SOURCE_CMD_GET (20  + SW_API_IP_OFFSET)
+#define SW_API_ARP_UNK_SOURCE_CMD_SET (21  + SW_API_IP_OFFSET)
+#define SW_API_ARP_UNK_SOURCE_CMD_GET (22  + SW_API_IP_OFFSET)
+#define SW_API_IP_AGE_TIME_SET       (23  + SW_API_IP_OFFSET)
+#define SW_API_IP_AGE_TIME_GET       (24  + SW_API_IP_OFFSET)
+#define SW_API_WCMP_HASH_MODE_SET    (25  + SW_API_IP_OFFSET)
+#define SW_API_WCMP_HASH_MODE_GET    (26  + SW_API_IP_OFFSET)
+#define SW_API_IP_VRF_BASE_ADDR_SET    (27  + SW_API_IP_OFFSET)
+#define SW_API_IP_VRF_BASE_ADDR_GET    (28  + SW_API_IP_OFFSET)
+#define SW_API_IP_VRF_BASE_MASK_SET    (29  + SW_API_IP_OFFSET)
+#define SW_API_IP_VRF_BASE_MASK_GET    (30  + SW_API_IP_OFFSET)
+#define SW_API_IP_DEFAULT_ROUTE_SET    (31  + SW_API_IP_OFFSET)
+#define SW_API_IP_DEFAULT_ROUTE_GET    (32  + SW_API_IP_OFFSET)
+#define SW_API_IP_HOST_ROUTE_SET    (33  + SW_API_IP_OFFSET)
+#define SW_API_IP_HOST_ROUTE_GET    (34  + SW_API_IP_OFFSET)
+#define SW_API_IP_WCMP_ENTRY_SET    (35  + SW_API_IP_OFFSET)
+#define SW_API_IP_WCMP_ENTRY_GET    (36  + SW_API_IP_OFFSET)
+#define SW_API_IP_RFS_IP4_SET       (37  + SW_API_IP_OFFSET)
+#define SW_API_IP_RFS_IP6_SET       (38  + SW_API_IP_OFFSET)
+#define SW_API_IP_RFS_IP4_DEL       (39  + SW_API_IP_OFFSET)
+#define SW_API_IP_RFS_IP6_DEL       (40  + SW_API_IP_OFFSET)
+#define SW_API_IP_DEFAULT_FLOW_CMD_SET    (41  + SW_API_IP_OFFSET)
+#define SW_API_IP_DEFAULT_FLOW_CMD_GET    (42  + SW_API_IP_OFFSET)
+#define SW_API_IP_DEFAULT_RT_FLOW_CMD_SET    (43  + SW_API_IP_OFFSET)
+#define SW_API_IP_DEFAULT_RT_FLOW_CMD_GET    (44  + SW_API_IP_OFFSET)
+#define SW_API_IP_VIS_ARP_SG_CFG_GET    (45  + SW_API_IP_OFFSET)
+#define SW_API_IP_VIS_ARP_SG_CFG_SET    (46  + SW_API_IP_OFFSET)
+#define SW_API_IP_NETWORK_ROUTE_GET    (47  + SW_API_IP_OFFSET)
+#define SW_API_IP_NETWORK_ROUTE_ADD    (48  + SW_API_IP_OFFSET)
+#define SW_API_IP_INTF_GET    (49  + SW_API_IP_OFFSET)
+#define SW_API_IP_INTF_SET    (50  + SW_API_IP_OFFSET)
+#define SW_API_IP_VSI_INTF_GET    (51  + SW_API_IP_OFFSET)
+#define SW_API_IP_VSI_INTF_SET    (52  + SW_API_IP_OFFSET)
+#define SW_API_IP_NEXTHOP_GET    (53  + SW_API_IP_OFFSET)
+#define SW_API_IP_NEXTHOP_SET    (54  + SW_API_IP_OFFSET)
+#define SW_API_IP_VSI_SG_SET    (55  + SW_API_IP_OFFSET)
+#define SW_API_IP_VSI_SG_GET    (56  + SW_API_IP_OFFSET)
+#define SW_API_IP_PORT_SG_SET    (57  + SW_API_IP_OFFSET)
+#define SW_API_IP_PORT_SG_GET    (58  + SW_API_IP_OFFSET)
+#define SW_API_IP_PUB_IP_SET    (59  + SW_API_IP_OFFSET)
+#define SW_API_IP_PUB_IP_GET    (60  + SW_API_IP_OFFSET)
+#define SW_API_IP_NETWORK_ROUTE_DEL    (61  + SW_API_IP_OFFSET)
+#define SW_API_IP_PORT_INTF_GET    (62  + SW_API_IP_OFFSET)
+#define SW_API_IP_PORT_INTF_SET    (63  + SW_API_IP_OFFSET)
+#define SW_API_IP_PORT_MAC_GET    (64  + SW_API_IP_OFFSET)
+#define SW_API_IP_PORT_MAC_SET    (65  + SW_API_IP_OFFSET)
+#define SW_API_IP_ROUTE_MISS_GET    (66  + SW_API_IP_OFFSET)
+#define SW_API_IP_ROUTE_MISS_SET    (67  + SW_API_IP_OFFSET)
+#define SW_API_IP_PORT_ARP_SG_GET    (68  + SW_API_IP_OFFSET)
+#define SW_API_IP_PORT_ARP_SG_SET    (69  + SW_API_IP_OFFSET)
+#define SW_API_IP_VSI_MC_MODE_GET    (70  + SW_API_IP_OFFSET)
+#define SW_API_IP_VSI_MC_MODE_SET    (71  + SW_API_IP_OFFSET)
+#define SW_API_GLOBAL_CTRL_GET    (72  + SW_API_IP_OFFSET)
+#define SW_API_GLOBAL_CTRL_SET    (73  + SW_API_IP_OFFSET)
+
+    /* nat */
+#define SW_API_NAT_OFFSET            1700
+#define SW_API_NAT_ADD               (0  + SW_API_NAT_OFFSET)
+#define SW_API_NAT_DEL               (1  + SW_API_NAT_OFFSET)
+#define SW_API_NAT_GET               (2  + SW_API_NAT_OFFSET)
+#define SW_API_NAT_NEXT              (3  + SW_API_NAT_OFFSET)
+#define SW_API_NAT_COUNTER_BIND      (4  + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_ADD              (5  + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_DEL              (6  + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_GET              (7  + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_NEXT             (8  + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_COUNTER_BIND     (9  + SW_API_NAT_OFFSET)
+#define SW_API_NAT_STATUS_SET        (10  + SW_API_NAT_OFFSET)
+#define SW_API_NAT_STATUS_GET        (11  + SW_API_NAT_OFFSET)
+#define SW_API_NAT_HASH_MODE_SET     (12  + SW_API_NAT_OFFSET)
+#define SW_API_NAT_HASH_MODE_GET     (13  + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_STATUS_SET       (14  + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_STATUS_GET       (15  + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_MODE_SET         (16  + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_MODE_GET         (17  + SW_API_NAT_OFFSET)
+#define SW_API_PRV_BASE_ADDR_SET     (18  + SW_API_NAT_OFFSET)
+#define SW_API_PRV_BASE_ADDR_GET     (19  + SW_API_NAT_OFFSET)
+#define SW_API_PRV_ADDR_MODE_SET     (20  + SW_API_NAT_OFFSET)
+#define SW_API_PRV_ADDR_MODE_GET     (21  + SW_API_NAT_OFFSET)
+#define SW_API_PUB_ADDR_ENTRY_ADD    (22  + SW_API_NAT_OFFSET)
+#define SW_API_PUB_ADDR_ENTRY_DEL    (23  + SW_API_NAT_OFFSET)
+#define SW_API_PUB_ADDR_ENTRY_NEXT   (24  + SW_API_NAT_OFFSET)
+#define SW_API_NAT_UNK_SESSION_CMD_SET (25  + SW_API_NAT_OFFSET)
+#define SW_API_NAT_UNK_SESSION_CMD_GET (26  + SW_API_NAT_OFFSET)
+#define SW_API_PRV_BASE_MASK_SET       (27  + SW_API_NAT_OFFSET)
+#define SW_API_PRV_BASE_MASK_GET       (28  + SW_API_NAT_OFFSET)
+#define SW_API_NAT_GLOBAL_SET          (29  + SW_API_NAT_OFFSET)
+#define SW_API_FLOW_ADD              (30  + SW_API_NAT_OFFSET)
+#define SW_API_FLOW_DEL              (31  + SW_API_NAT_OFFSET)
+#define SW_API_FLOW_GET              (32  + SW_API_NAT_OFFSET)
+#define SW_API_FLOW_NEXT             (33  + SW_API_NAT_OFFSET)
+#define SW_API_FLOW_COUNTER_BIND     (34  + SW_API_NAT_OFFSET)
+#define SW_API_FLOW_COOKIE_SET       (35  + SW_API_NAT_OFFSET)
+#define SW_API_FLOW_RFS_SET          (36  + SW_API_NAT_OFFSET)
+
+
+    /* trunk */
+#define SW_API_TRUNK_OFFSET            1800
+#define SW_API_TRUNK_GROUP_SET         (0  + SW_API_TRUNK_OFFSET)
+#define SW_API_TRUNK_GROUP_GET         (1  + SW_API_TRUNK_OFFSET)
+#define SW_API_TRUNK_HASH_SET          (2  + SW_API_TRUNK_OFFSET)
+#define SW_API_TRUNK_HASH_GET          (3  + SW_API_TRUNK_OFFSET)
+#define SW_API_TRUNK_MAN_SA_SET        (4  + SW_API_TRUNK_OFFSET)
+#define SW_API_TRUNK_MAN_SA_GET        (5  + SW_API_TRUNK_OFFSET)
+#define SW_API_TRUNK_FAILOVER_EN_SET        (6  + SW_API_TRUNK_OFFSET)
+#define SW_API_TRUNK_FAILOVER_EN_GET        (7  + SW_API_TRUNK_OFFSET)
+
+    /* Interface Control */
+#define SW_API_INTERFACE_OFFSET        1900
+#define SW_API_MAC_MODE_SET            (0  + SW_API_INTERFACE_OFFSET)
+#define SW_API_MAC_MODE_GET            (1  + SW_API_INTERFACE_OFFSET)
+#define SW_API_PORT_3AZ_STATUS_SET     (2  + SW_API_INTERFACE_OFFSET)
+#define SW_API_PORT_3AZ_STATUS_GET     (3  + SW_API_INTERFACE_OFFSET)
+#define SW_API_PHY_MODE_SET            (4  + SW_API_INTERFACE_OFFSET)
+#define SW_API_PHY_MODE_GET            (5  + SW_API_INTERFACE_OFFSET)
+#define SW_API_FX100_CTRL_SET          (6  + SW_API_INTERFACE_OFFSET)
+#define SW_API_FX100_CTRL_GET          (7  + SW_API_INTERFACE_OFFSET)
+#define SW_API_FX100_STATUS_GET        (8  + SW_API_INTERFACE_OFFSET)
+#define SW_API_MAC06_EXCH_SET          (9  + SW_API_INTERFACE_OFFSET)
+#define SW_API_MAC06_EXCH_GET          (10  + SW_API_INTERFACE_OFFSET)
+
+    /* VSI */
+#define SW_API_VSI_OFFSET        2000
+#define SW_API_VSI_ALLOC               (0  + SW_API_VSI_OFFSET)
+#define SW_API_VSI_FREE                (1  + SW_API_VSI_OFFSET)
+#define SW_API_PORT_VSI_SET            (2  + SW_API_VSI_OFFSET)
+#define SW_API_PORT_VSI_GET            (3  + SW_API_VSI_OFFSET)
+#define SW_API_PORT_VLAN_VSI_SET       (4  + SW_API_VSI_OFFSET)
+#define SW_API_PORT_VLAN_VSI_GET       (5  + SW_API_VSI_OFFSET)
+#define SW_API_VSI_TBL_DUMP	       (6  + SW_API_VSI_OFFSET)
+#define SW_API_VSI_NEWADDR_LRN_SET     (7  + SW_API_VSI_OFFSET)
+#define SW_API_VSI_NEWADDR_LRN_GET     (8  + SW_API_VSI_OFFSET)
+#define SW_API_VSI_STAMOVE_SET	       (9  + SW_API_VSI_OFFSET)
+#define SW_API_VSI_STAMOVE_GET	       (10 + SW_API_VSI_OFFSET)
+#define SW_API_VSI_MEMBER_SET	       (11 + SW_API_VSI_OFFSET)
+#define SW_API_VSI_MEMBER_GET	       (12 + SW_API_VSI_OFFSET)
+#define SW_API_VSI_COUNTER_GET	       (13 + SW_API_VSI_OFFSET)
+#define SW_API_VSI_COUNTER_CLEANUP	   (14 + SW_API_VSI_OFFSET)
+
+ /* qm */
+#define SW_API_QM_OFFSET            2100
+#define SW_API_UCAST_QUEUE_BASE_PROFILE_SET         (0  + SW_API_QM_OFFSET)
+#define SW_API_UCAST_QUEUE_BASE_PROFILE_GET         (1  + SW_API_QM_OFFSET)
+#define SW_API_UCAST_PRIORITY_CLASS_SET         (2  + SW_API_QM_OFFSET)
+#define SW_API_UCAST_PRIORITY_CLASS_GET         (3  + SW_API_QM_OFFSET)
+#define SW_API_MCAST_PRIORITY_CLASS_SET         (4  + SW_API_QM_OFFSET)
+#define SW_API_MCAST_PRIORITY_CLASS_GET         (5  + SW_API_QM_OFFSET)
+#define SW_API_UCAST_HASH_MAP_SET         (6  + SW_API_QM_OFFSET)
+#define SW_API_UCAST_HASH_MAP_GET         (7 + SW_API_QM_OFFSET)
+#define SW_API_UCAST_DFLT_HASH_MAP_SET         (8  + SW_API_QM_OFFSET)
+#define SW_API_UCAST_DFLT_HASH_MAP_GET         (9 + SW_API_QM_OFFSET)
+#define SW_API_MCAST_CPUCODE_CLASS_SET         (10  + SW_API_QM_OFFSET)
+#define SW_API_MCAST_CPUCODE_CLASS_GET         (11  + SW_API_QM_OFFSET)
+#define SW_API_QUEUE_FLUSH         (12  + SW_API_QM_OFFSET)
+#define SW_API_AC_CTRL_SET         (13  + SW_API_QM_OFFSET)
+#define SW_API_AC_CTRL_GET         (14  + SW_API_QM_OFFSET)
+#define SW_API_AC_PRE_BUFFER_SET         (15  + SW_API_QM_OFFSET)
+#define SW_API_AC_PRE_BUFFER_GET         (16  + SW_API_QM_OFFSET)
+#define SW_API_QUEUE_GROUP_SET         (17  + SW_API_QM_OFFSET)
+#define SW_API_QUEUE_GROUP_GET         (18 + SW_API_QM_OFFSET)
+#define SW_API_STATIC_THRESH_SET         (19  + SW_API_QM_OFFSET)
+#define SW_API_STATIC_THRESH_GET         (20 + SW_API_QM_OFFSET)
+#define SW_API_DYNAMIC_THRESH_SET         (21  + SW_API_QM_OFFSET)
+#define SW_API_DYNAMIC_THRESH_GET         (22 + SW_API_QM_OFFSET)
+#define SW_API_GOURP_BUFFER_SET         (23  + SW_API_QM_OFFSET)
+#define SW_API_GOURP_BUFFER_GET         (24 + SW_API_QM_OFFSET)
+#define SW_API_QUEUE_CNT_CTRL_GET         (25 + SW_API_QM_OFFSET)
+#define SW_API_QUEUE_CNT_CTRL_SET         (26 + SW_API_QM_OFFSET)
+#define SW_API_QUEUE_CNT_GET         (27 + SW_API_QM_OFFSET)
+#define SW_API_QUEUE_CNT_CLEANUP         (28 + SW_API_QM_OFFSET)
+#define SW_API_QM_ENQUEUE_CTRL_SET         (29 + SW_API_QM_OFFSET)
+#define SW_API_QM_ENQUEUE_CTRL_GET         (30 + SW_API_QM_OFFSET)
+#define SW_API_QM_SOURCE_PROFILE_SET         (31 + SW_API_QM_OFFSET)
+#define SW_API_QM_SOURCE_PROFILE_GET         (32 + SW_API_QM_OFFSET)
+
+/* flow */
+#define SW_API_FLOW_OFFSET            2200
+#define SW_API_FLOW_STATUS_SET         (0  + SW_API_FLOW_OFFSET)
+#define SW_API_FLOW_STATUS_GET         (1  + SW_API_FLOW_OFFSET)
+#define SW_API_FLOW_AGE_TIMER_SET         (2  + SW_API_FLOW_OFFSET)
+#define SW_API_FLOW_AGE_TIMER_GET         (3  + SW_API_FLOW_OFFSET)
+#define SW_API_FLOW_CTRL_SET         (4  + SW_API_FLOW_OFFSET)
+#define SW_API_FLOW_CTRL_GET         (5  + SW_API_FLOW_OFFSET)
+#define SW_API_FLOW_ENTRY_ADD         (6  + SW_API_FLOW_OFFSET)
+#define SW_API_FLOW_ENTRY_DEL         (7  + SW_API_FLOW_OFFSET)
+#define SW_API_FLOW_ENTRY_GET         (8  + SW_API_FLOW_OFFSET)
+#define SW_API_FLOW_GLOBAL_CFG_GET         (9  + SW_API_FLOW_OFFSET)
+#define SW_API_FLOW_GLOBAL_CFG_SET         (10  + SW_API_FLOW_OFFSET)
+#define SW_API_FLOWENTRY_NEXT         (11  + SW_API_FLOW_OFFSET)
+
+#define SW_API_FLOW_HOST_ADD         (20  + SW_API_FLOW_OFFSET)
+#define SW_API_FLOW_HOST_DEL         (21  + SW_API_FLOW_OFFSET)
+#define SW_API_FLOW_HOST_GET         (22  + SW_API_FLOW_OFFSET)
+
+/* rss hash */
+#define SW_API_RSS_HASH_OFFSET		2400
+#define SW_API_RSS_HASH_CONFIG_SET	(0 + SW_API_RSS_HASH_OFFSET)
+#define SW_API_RSS_HASH_CONFIG_GET	(1 + SW_API_RSS_HASH_OFFSET)
+
+    /* Ctrlpkt Control */
+#define SW_API_CTRLPKT_OFFSET        2500
+#define SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET (0  + SW_API_CTRLPKT_OFFSET)
+#define SW_API_MGMTCTRL_ETHTYPE_PROFILE_GET (1  + SW_API_CTRLPKT_OFFSET)
+#define SW_API_MGMTCTRL_RFDB_PROFILE_SET (2  + SW_API_CTRLPKT_OFFSET)
+#define SW_API_MGMTCTRL_RFDB_PROFILE_GET (3  + SW_API_CTRLPKT_OFFSET)
+#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_ADD (4  + SW_API_CTRLPKT_OFFSET)
+#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_DEL (5  + SW_API_CTRLPKT_OFFSET)
+#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST (6  + SW_API_CTRLPKT_OFFSET)
+#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT (7  + SW_API_CTRLPKT_OFFSET)
+
+    /* Service Code */
+#define SW_API_SERVCODE_OFFSET        2600
+#define SW_API_SERVCODE_CONFIG_SET	(0  + SW_API_SERVCODE_OFFSET)
+#define SW_API_SERVCODE_CONFIG_GET	(1  + SW_API_SERVCODE_OFFSET)
+#define SW_API_SERVCODE_LOOPCHECK_EN	(2  + SW_API_SERVCODE_OFFSET)
+#define SW_API_SERVCODE_LOOPCHECK_STATUS_GET	(3  + SW_API_SERVCODE_OFFSET)
+
+	/* POLICER */
+#define SW_API_POLICER_OFFSET        2800
+#define SW_API_POLICER_TIMESLOT_SET               (0  + SW_API_POLICER_OFFSET)
+#define SW_API_POLICER_TIMESLOT_GET               (1  + SW_API_POLICER_OFFSET)
+#define SW_API_POLICER_PORT_COUNTER_GET              (2  + SW_API_POLICER_OFFSET)
+#define SW_API_POLICER_ACL_COUNTER_GET                (3  + SW_API_POLICER_OFFSET)
+#define SW_API_POLICER_COMPENSATION_SET               (4  + SW_API_POLICER_OFFSET)
+#define SW_API_POLICER_COMPENSATION_GET               (5  + SW_API_POLICER_OFFSET)
+#define SW_API_POLICER_PORT_ENTRY_SET               (6  + SW_API_POLICER_OFFSET)
+#define SW_API_POLICER_PORT_ENTRY_GET               (7  + SW_API_POLICER_OFFSET)
+#define SW_API_POLICER_ACL_ENTRY_SET               (8  + SW_API_POLICER_OFFSET)
+#define SW_API_POLICER_ACL_ENTRY_GET               (9  + SW_API_POLICER_OFFSET)
+#define SW_API_POLICER_GLOBAL_COUNTER_GET               (10  + SW_API_POLICER_OFFSET)
+#define SW_API_POLICER_BYPASS_EN_SET              (11  + SW_API_POLICER_OFFSET)
+#define SW_API_POLICER_BYPASS_EN_GET              (12  + SW_API_POLICER_OFFSET)
+
+
+/* SHAPER */
+#define SW_API_SHAPER_OFFSET        2900
+#define SW_API_PORT_SHAPER_TIMESLOT_SET               (0  + SW_API_SHAPER_OFFSET)
+#define SW_API_PORT_SHAPER_TIMESLOT_GET               (1  + SW_API_SHAPER_OFFSET)
+#define SW_API_FLOW_SHAPER_TIMESLOT_SET               (2  + SW_API_SHAPER_OFFSET)
+#define SW_API_FLOW_SHAPER_TIMESLOT_GET               (3  + SW_API_SHAPER_OFFSET)
+#define SW_API_QUEUE_SHAPER_TIMESLOT_SET               (4  + SW_API_SHAPER_OFFSET)
+#define SW_API_QUEUE_SHAPER_TIMESLOT_GET               (5  + SW_API_SHAPER_OFFSET)
+#define SW_API_PORT_SHAPER_TOKEN_NUMBER_SET               (6  + SW_API_SHAPER_OFFSET)
+#define SW_API_PORT_SHAPER_TOKEN_NUMBER_GET               (7  + SW_API_SHAPER_OFFSET)
+#define SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET               (8  + SW_API_SHAPER_OFFSET)
+#define SW_API_FLOW_SHAPER_TOKEN_NUMBER_GET               (9  + SW_API_SHAPER_OFFSET)
+#define SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET               (10  + SW_API_SHAPER_OFFSET)
+#define SW_API_QUEUE_SHAPER_TOKEN_NUMBER_GET               (11  + SW_API_SHAPER_OFFSET)
+#define SW_API_PORT_SHAPER_SET               (12  + SW_API_SHAPER_OFFSET)
+#define SW_API_PORT_SHAPER_GET               (13  + SW_API_SHAPER_OFFSET)
+#define SW_API_FLOW_SHAPER_SET               (14  + SW_API_SHAPER_OFFSET)
+#define SW_API_FLOW_SHAPER_GET               (15  + SW_API_SHAPER_OFFSET)
+#define SW_API_QUEUE_SHAPER_SET               (16  + SW_API_SHAPER_OFFSET)
+#define SW_API_QUEUE_SHAPER_GET               (17  + SW_API_SHAPER_OFFSET)
+#define SW_API_SHAPER_IPG_PRE_SET               (18  + SW_API_SHAPER_OFFSET)
+#define SW_API_SHAPER_IPG_PRE_GET               (19  + SW_API_SHAPER_OFFSET)
+
+/* bm */
+#define SW_API_BM_OFFSET            3000
+#define SW_API_BM_CTRL_SET         (0  + SW_API_BM_OFFSET)
+#define SW_API_BM_CTRL_GET         (1  + SW_API_BM_OFFSET)
+#define SW_API_BM_PORTGROUP_MAP_SET         (2  + SW_API_BM_OFFSET)
+#define SW_API_BM_PORTGROUP_MAP_GET         (3  + SW_API_BM_OFFSET)
+#define SW_API_BM_GROUP_BUFFER_SET         (4  + SW_API_BM_OFFSET)
+#define SW_API_BM_GROUP_BUFFER_GET         (5  + SW_API_BM_OFFSET)
+#define SW_API_BM_PORT_RSVBUFFER_SET         (6  + SW_API_BM_OFFSET)
+#define SW_API_BM_PORT_RSVBUFFER_GET         (7  + SW_API_BM_OFFSET)
+#define SW_API_BM_STATIC_THRESH_SET         (8  + SW_API_BM_OFFSET)
+#define SW_API_BM_STATIC_THRESH_GET         (9  + SW_API_BM_OFFSET)
+#define SW_API_BM_DYNAMIC_THRESH_SET         (10  + SW_API_BM_OFFSET)
+#define SW_API_BM_DYNAMIC_THRESH_GET         (11  + SW_API_BM_OFFSET)
+#define SW_API_BM_PORT_COUNTER_GET         (12  + SW_API_BM_OFFSET)
+
+/* ptp */
+#define SW_API_PTP_OFFSET                         3100
+#define SW_API_PTP_CONFIG_SET                     (0  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_CONFIG_GET                     (1  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_REFERENCE_CLOCK_SET            (2  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_REFERENCE_CLOCK_GET            (3  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_RX_TIMESTAMP_MODE_SET          (4  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_RX_TIMESTAMP_MODE_GET          (5  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_TIMESTAMP_GET                  (6  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_PKT_TIMESTAMP_SET              (7  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_PKT_TIMESTAMP_GET              (8  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_GRANDMASTER_MODE_SET           (9  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_GRANDMASTER_MODE_GET           (10  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_RTC_TIME_SET                   (11  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_RTC_TIME_GET                   (12  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_RTC_TIME_CLEAR                 (13  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_RTC_ADJTIME_SET                (14  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_RTC_ADJFREQ_SET                (15  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_RTC_ADJFREQ_GET                (16  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_LINK_DELAY_SET                 (17  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_LINK_DELAY_GET                 (18  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_SECURITY_SET                   (19  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_SECURITY_GET                   (20  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_PPS_SIGNAL_CONTROL_SET         (21  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_PPS_SIGNAL_CONTROL_GET         (22  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_RX_CRC_RECALC_SET              (23  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_RX_CRC_RECALC_GET              (24  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_ASYM_CORRECTION_SET            (25  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_ASYM_CORRECTION_GET            (26  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_OUTPUT_WAVEFORM_SET            (27  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_OUTPUT_WAVEFORM_GET            (28  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_RTC_TIME_SNAPSHOT_SET          (29  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_RTC_TIME_SNAPSHOT_GET          (30  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_SET  (31  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_GET  (32  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_TOD_UART_SET                   (33  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_TOD_UART_GET                   (34  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET  (35  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET  (36  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_TRIGGER_SET                    (37  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_TRIGGER_GET                    (38  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_CAPTURE_SET                    (39  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_CAPTURE_GET                    (40  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_INTERRUPT_SET                  (41  + SW_API_PTP_OFFSET)
+#define SW_API_PTP_INTERRUPT_GET                  (42  + SW_API_PTP_OFFSET)
+
+/* sfp */
+#define SW_API_SFP_OFFSET                         3200
+#define SW_API_SFP_DATA_GET                       (0  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_DATA_SET                       (1  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_DEV_TYPE_GET                   (2  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_TRANSC_CODE_GET                (3  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_RATE_ENCODE_GET                (4  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_LINK_LENGTH_GET                (5  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_VENDOR_INFO_GET                (6  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_LASER_WAVELENGTH_GET           (7  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_OPTION_GET                     (8  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_CTRL_RATE_GET                  (9  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_ENHANCED_CFG_GET               (10  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_DIAG_THRESHOLD_GET             (11  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_DIAG_CAL_CONST_GET             (12  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_DIAG_REALTIME_GET              (13  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_DIAG_CTRL_STATUS_GET           (14  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_DIAG_ALARM_WARN_FLAG_GET       (15  + SW_API_SFP_OFFSET)
+#define SW_API_SFP_CHECKCODE_GET                  (16  + SW_API_SFP_OFFSET)
+
+/*qca808x_start*/
+    /*debug*/
+#define SW_API_DEBUG_OFFSET        10000
+#define SW_API_PHY_GET             (0  + SW_API_DEBUG_OFFSET)
+#define SW_API_PHY_SET             (1  + SW_API_DEBUG_OFFSET)
+/*qca808x_end*/
+#define SW_API_REG_GET             (2  + SW_API_DEBUG_OFFSET)
+#define SW_API_REG_SET             (3  + SW_API_DEBUG_OFFSET)
+#define SW_API_REG_ENTRY_GET       (4  + SW_API_DEBUG_OFFSET)
+#define SW_API_REG_ENTRY_SET       (5  + SW_API_DEBUG_OFFSET)
+#define SW_API_REG_FIELD_GET       (6  + SW_API_DEBUG_OFFSET)
+#define SW_API_REG_FIELD_SET       (7  + SW_API_DEBUG_OFFSET)
+#define SW_API_PSGMII_REG_GET             (8  + SW_API_DEBUG_OFFSET)
+#define SW_API_PSGMII_REG_SET             (9  + SW_API_DEBUG_OFFSET)
+#define SW_API_REG_DUMP          			(10  + SW_API_DEBUG_OFFSET)
+#define SW_API_DBG_REG_DUMP          		(11  + SW_API_DEBUG_OFFSET)
+#define SW_API_DBG_PSGMII_SELF_TEST          		(12  + SW_API_DEBUG_OFFSET)
+#define SW_API_PHY_DUMP             (13  + SW_API_DEBUG_OFFSET)
+#define SW_API_UNIPHY_REG_GET             (20  + SW_API_DEBUG_OFFSET)
+#define SW_API_UNIPHY_REG_SET             (21  + SW_API_DEBUG_OFFSET)
+/*qca808x_start*/
+#define SW_API_PHY_I2C_GET                (22  + SW_API_DEBUG_OFFSET)
+#define SW_API_PHY_I2C_SET                (23  + SW_API_DEBUG_OFFSET)
+
+#define SW_API_MAX                 0xffff
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SW_IOCTL_H_ */
+/*qca808x_end*/
diff --git a/qca-ssdk/include/common/aos_head.h b/qca-ssdk/include/common/aos_head.h
new file mode 100755
index 0000000..b496211
--- /dev/null
+++ b/qca-ssdk/include/common/aos_head.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "aos_mem.h"
+#include "aos_timer.h"
+#include "aos_lock.h"
+#include "aos_types.h"
+
diff --git a/qca-ssdk/include/common/shared_func.h b/qca-ssdk/include/common/shared_func.h
new file mode 100755
index 0000000..729938c
--- /dev/null
+++ b/qca-ssdk/include/common/shared_func.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _SHARED_FUNC_H
+#define _SHARED_FUNC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#define SW_RTN_ON_ERROR(rtn) \
+    do { if (rtn != SW_OK) return(rtn); } while(0);
+
+#define SW_OUT_ON_ERROR(rtn) \
+    do { \
+        if (rtn != SW_OK) { \
+            rv = rtn; \
+            goto out;\
+        } \
+    } while(0);
+
+#define SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rtn, cond1) \
+    { \
+        if ((rtn != SW_OK)) { \
+		if (rtn == cond1) \
+			continue; \
+		else		  \
+			goto out; \
+	}			  \
+    }
+
+#define SW_RTN_ON_ERROR_EXCEPT_COND1(rtn, cond1) \
+    do { \
+        if ((rtn != SW_OK) && (rtn != cond1)) \
+            return rtn; \
+    }while(0);
+
+#define SW_RTN_ON_NULL(op)  \
+    do { \
+        if ((op) == NULL) \
+            return SW_NOT_INITIALIZED;\
+    }while(0);
+
+    /* register functions */
+#define SW_BIT_MASK_U32(nr) (~(0xFFFFFFFF << (nr)))
+
+#define SW_FIELD_MASK_U32(offset, len) \
+    ((SW_BIT_MASK_U32(len) << (offset)))
+
+#define SW_FIELD_MASK_NOT_U32(offset,len) \
+    (~(SW_BIT_MASK_U32(len) << (offset)))
+
+#define SW_FIELD_2_REG(field_val, bit_offset) \
+    (field_val << (bit_offset) )
+
+#define SW_REG_2_FIELD(reg_val, bit_offset, field_len) \
+    (((reg_val) >> (bit_offset)) & ((1 << (field_len)) - 1))
+
+#define SW_REG_SET_BY_FIELD_U32(reg_value, field_value, bit_offset, field_len)\
+    do { \
+        (reg_value) = \
+            (((reg_value) & SW_FIELD_MASK_NOT_U32((bit_offset),(field_len))) \
+              | (((field_value) & SW_BIT_MASK_U32(field_len)) << (bit_offset)));\
+    } while (0)
+
+#define SW_FIELD_GET_BY_REG_U32(reg_value, field_value, bit_offset, field_len)\
+    do { \
+        (field_value) = \
+            (((reg_value) >> (bit_offset)) & SW_BIT_MASK_U32(field_len)); \
+    } while (0)
+
+#define SW_SWAP_BITS_U8(x)         \
+    ((((x)&0x80)>>7) | (((x)&0x40)>>5) | (((x)&0x20)>>3) | (((x)&0x10)>>1) \
+      |(((x)&0x1)<<7) | (((x)&0x2)<<5) | (((x)&0x4)<<3) |(((x)&0x8)<<1) )
+
+
+#define SW_OFFSET_U8_2_U16(byte_offset)   ((byte_offset) >> 1)
+
+#define SW_OFFSET_U16_2_U8(word16_offset)   ((word16_offset) << 1)
+
+#define SW_OFFSET_BIT_2_U8_ALIGN16(bit_offset)   (((bit_offset) / 16) * 2)
+
+#define SW_SET_REG_BY_FIELD(reg, field, field_value, reg_value) \
+    SW_REG_SET_BY_FIELD_U32(reg_value, field_value, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define SW_GET_FIELD_BY_REG(reg, field, field_value, reg_value) \
+    SW_FIELD_GET_BY_REG_U32(reg_value, field_value, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+    /* port bitmap functions */
+#define SW_IS_PBMP_MEMBER(pbm, port)  ((pbm & (1 << port)) ? A_TRUE: A_FALSE)
+#define SW_IS_PBMP_EQ(pbm0, pbm1)  ((pbm0 == pbm1) ? A_TRUE: A_FALSE)
+
+#define SW_PBMP_AND(pbm0, pbm1)  ((pbm0) &= (pbm1))
+#define SW_PBMP_OR(pbm0, pbm1)  ((pbm0) |= (pbm1))
+#define SW_IS_PBMP_INCLUDE(pbm0, pbm1) \
+    ((pbm1 == SW_PBMP_AND(pbm0, pbm1)) ? A_TRUE: A_FALSE)
+
+#define SW_PBMP_CLEAR(pbm) ((pbm) = 0)
+#define SW_PBMP_ADD_PORT(pbm, port) ((pbm) |= (1U << (port)))
+#define SW_PBMP_DEL_PORT(pbm,port) ((pbm) &= ~(1U << (port)))
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SHARED_FUNC_H */
diff --git a/qca-ssdk/include/common/sw.h b/qca-ssdk/include/common/sw.h
new file mode 100755
index 0000000..fa82d56
--- /dev/null
+++ b/qca-ssdk/include/common/sw.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _SW_H_
+#define _SW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw_config.h"
+#include "aos_head.h"
+#include "sw_error.h"
+#include "shared_func.h"
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SW_H_ */
+
diff --git a/qca-ssdk/include/common/sw_config.h b/qca-ssdk/include/common/sw_config.h
new file mode 100755
index 0000000..d1c4f69
--- /dev/null
+++ b/qca-ssdk/include/common/sw_config.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _SW_CONFIG_H
+#define _SW_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define SW_MAX_NR_DEV      3
+#define SW_MAX_NR_PORT     16
+
+#ifdef HSL_STANDALONG
+#define HSL_LOCAL
+#else
+#define HSL_LOCAL static
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif
diff --git a/qca-ssdk/include/common/sw_error.h b/qca-ssdk/include/common/sw_error.h
new file mode 100755
index 0000000..7a17517
--- /dev/null
+++ b/qca-ssdk/include/common/sw_error.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _SW_ERROR_H
+#define _SW_ERROR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+    typedef enum {
+        SW_OK              = 0,       /* Operation succeeded                 */
+        SW_FAIL            = -1,      /* Operation failed                    */
+        SW_BAD_VALUE       = -2,      /* Illegal value                       */
+        SW_OUT_OF_RANGE    = -3,      /* Value is out of range               */
+        SW_BAD_PARAM       = -4,      /* Illegal parameter(s)                */
+        SW_BAD_PTR         = -5,      /* Illegal pointer value               */
+        SW_BAD_LEN         = -6,      /* Wrong length                        */
+        SW_BAD_STATE       = -7,      /* Wrong state of state machine        */
+        SW_READ_ERROR      = -8,      /* Read operation failed               */
+        SW_WRITE_ERROR     = -9,      /* Write operation failed              */
+        SW_CREATE_ERROR    = -10,     /* Fail in creating an entry           */
+        SW_DELETE_ERROR    = -11,     /* Fail in deleteing an entry          */
+        SW_NOT_FOUND       = -12,     /* Entry not found                     */
+        SW_NO_CHANGE       = -13,     /* The parameter(s) is the same        */
+        SW_NO_MORE         = -14,     /* No more entry found                 */
+        SW_NO_SUCH         = -15,     /* No such entry                       */
+        SW_ALREADY_EXIST   = -16,     /* Tried to create existing entry      */
+        SW_FULL            = -17,     /* Table is full                       */
+        SW_EMPTY           = -18,     /* Table is empty                      */
+        SW_NOT_SUPPORTED   = -19,     /* This request is not support         */
+        SW_NOT_IMPLEMENTED = -20,     /* This request is not implemented     */
+        SW_NOT_INITIALIZED = -21,     /* The item is not initialized         */
+        SW_BUSY            = -22,     /* Operation is still running          */
+        SW_TIMEOUT         = -23,     /* Operation Time Out                  */
+        SW_DISABLE         = -24,     /* Operation is disabled               */
+        SW_NO_RESOURCE     = -25,     /* Resource not available (memory ...) */
+        SW_INIT_ERROR      = -26,     /* Error occured while INIT process    */
+        SW_NOT_READY       = -27,     /* The other side is not ready yet     */
+        SW_OUT_OF_MEM      = -28,     /* Cpu memory allocation failed.       */
+        SW_ABORTED         = -29      /* Operation has been aborted.         */
+    } sw_error_t;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SW_ERROR_H */
+
diff --git a/qca-ssdk/include/common/util.h b/qca-ssdk/include/common/util.h
new file mode 100755
index 0000000..9baa22e
--- /dev/null
+++ b/qca-ssdk/include/common/util.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _UTIL_H_
+#define _UTIL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#define LL_IN_ORDER  0x1
+#define LL_FIX_NDNR  0x2
+
+    typedef enum {
+        LL_CMP_EQUAL = 0,
+        LL_CMP_GREATER = 1,
+        LL_CMP_SMALLER = 2
+    }
+                     ll_cmp_rslt_t;
+
+    typedef ll_cmp_rslt_t(*ll_nd_cmp) (void *src, void *dest);
+
+    typedef void (*ll_nd_dump) (void *data);
+
+    typedef struct _sll_node_t
+    {
+        struct _sll_node_t *next;
+        void *data;
+    } sll_node_t;
+
+    typedef struct
+    {
+        sll_node_t *fst_nd;
+        a_uint32_t nd_nr;
+        a_uint32_t flag;
+        ll_nd_cmp nd_cmp;
+        ll_nd_dump nd_dump;
+        sll_node_t *free_nd;
+    } sll_head_t;
+
+    sll_head_t *sll_creat(ll_nd_cmp cmp_func, ll_nd_dump dump_func,
+                          a_uint32_t flag, a_uint32_t nd_nr);
+
+    void sll_destroy(sll_head_t * sll);
+
+    void sll_lock(sll_head_t * sll);
+
+    void sll_unlock(sll_head_t * sll);
+
+    void *sll_nd_find(const sll_head_t * sll, void *data,
+                      a_ulong_t *iterator);
+
+    void *sll_nd_next(const sll_head_t *sll, a_ulong_t *iterator);
+
+    sw_error_t sll_nd_insert(sll_head_t * sll, void *data);
+
+    sw_error_t sll_nd_delete(sll_head_t * sll, void *data);
+
+    typedef struct
+    {
+        a_uint32_t id_ptr;
+        a_uint32_t id_nr;
+        a_uint32_t id_min;
+        a_uint32_t id_size;
+        void *id_pool;
+    } sid_pool_t;
+
+    sid_pool_t *sid_pool_creat(a_uint32_t id_nr, a_uint32_t min_id);
+
+    void sid_pool_destroy(sid_pool_t * pool);
+
+    sw_error_t sid_pool_id_alloc(sid_pool_t * pool, a_uint32_t * id);
+
+    sw_error_t sid_pool_id_free(sid_pool_t * pool, a_uint32_t id);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _UTIL_H_ */
diff --git a/qca-ssdk/include/fal/fal.h b/qca-ssdk/include/fal/fal.h
new file mode 100755
index 0000000..09d21ff
--- /dev/null
+++ b/qca-ssdk/include/fal/fal.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2012, 2017-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/*qca808x_start*/
+#ifndef _FAL_H
+#define _FAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+#include "fal_port_ctrl.h"
+/*qca808x_end*/
+#include "fal_misc.h"
+#include "fal_vlan.h"
+#include "fal_fdb.h"
+#include "fal_portvlan.h"
+#include "fal_qos.h"
+#include "fal_stp.h"
+#include "fal_rate.h"
+#include "fal_mirror.h"
+#include "fal_leaky.h"
+#include "fal_igmp.h"
+#include "fal_mib.h"
+#include "fal_acl.h"
+#include "fal_led.h"
+/*qca808x_start*/
+#include "fal_reg_access.h"
+#include "fal_init.h"
+/*qca808x_end*/
+#include "fal_cosmap.h"
+#include "fal_ip.h"
+#include "fal_nat.h"
+#include "fal_flow.h"
+#include "fal_qm.h"
+#include "fal_sec.h"
+#include "fal_trunk.h"
+#include "fal_interface_ctrl.h"
+#include "fal_fdb.h"
+#include "fal_multi.h"
+#include "fal_ctrlpkt.h"
+#include "fal_servcode.h"
+#include "fal_rss_hash.h"
+#include "fal_vsi.h"
+#include "fal_pppoe.h"
+#include "fal_bm.h"
+#include "fal_shaper.h"
+#include "fal_policer.h"
+#include "fal_ptp.h"
+#include "fal_sfp.h"
+
+/*qca808x_start*/
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_H */
+/*qca808x_end*/
diff --git a/qca-ssdk/include/fal/fal_acl.h b/qca-ssdk/include/fal/fal_acl.h
new file mode 100755
index 0000000..e9c9f9c
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_acl.h
@@ -0,0 +1,616 @@
+/*
+ * Copyright (c) 2014, 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_acl FAL_ACL
+ * @{
+ */
+#ifndef _FAL_ACL_H_
+#define _FAL_ACL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+
+    /**
+    @brief This enum defines the ACL rule type.
+    */
+    typedef enum {
+        FAL_ACL_RULE_MAC = 0,   /**< include MAC, udf fields*/
+        FAL_ACL_RULE_IP4,       /**< include MAC, IP4 and Tcp/Udp udf fields*/
+        FAL_ACL_RULE_IP6,       /**< include MAC, IP6 and Tcp/Udp udf fields*/
+        FAL_ACL_RULE_UDF,       /**< only include user defined fields*/
+        FAL_ACL_RULE_BUTT,
+    }
+    fal_acl_rule_type_t;
+
+
+    /**
+    @brief This enum defines the ACL field operation type.
+    */
+    typedef enum
+    {
+        FAL_ACL_FIELD_MASK = 0, /**< match operation is mask*/
+        FAL_ACL_FIELD_RANGE,    /**< match operation is range*/
+        FAL_ACL_FIELD_LE,       /**< match operation is less than equal*/
+        FAL_ACL_FIELD_GE,       /**< match operation is greater than equal*/
+        FAL_ACL_FIELD_NE,       /**<- match operation is not equal*/
+        FAL_ACL_FIELD_OP_BUTT,
+    } fal_acl_field_op_t;
+
+
+    typedef enum
+    {
+        FAL_ACL_POLICY_ROUTE = 0,
+        FAL_ACL_POLICY_SNAT,
+        FAL_ACL_POLICY_DNAT,
+        FAL_ACL_POLICY_RESERVE,
+    } fal_policy_forward_t;
+
+    typedef enum
+    {
+        FAL_ACL_COMBINED_NONE = 0,
+        FAL_ACL_COMBINED_START,
+        FAL_ACL_COMBINED_CONTINUE,
+        FAL_ACL_COMBINED_END,
+    } fal_combined_t;
+
+    /**
+    @brief This enum defines the ACL field operation type.
+    */
+    typedef enum
+    {
+        FAL_ACL_UDF_TYPE_L2 = 0, /*start from L2 */
+        FAL_ACL_UDF_TYPE_L3,     /*start from L3 */
+        FAL_ACL_UDF_TYPE_L4,    /*start from L4 */
+        FAL_ACL_UDF_TYPE_L2_SNAP, /*start from SNAP L2 */
+        FAL_ACL_UDF_TYPE_L3_PLUS, /*start from SNAP L3 */
+        FAL_ACL_UDF_TYPE_BUTT,
+    } fal_acl_udf_type_t;
+
+    /**
+    @brief This enum defines the ACL rule type.
+    */
+    typedef enum {
+        FAL_ACL_UDF_NON_IP = 0, /*UDF for non-ip packets*/
+        FAL_ACL_UDF_IP4, /*UDF for IPv4 packets*/
+        FAL_ACL_UDF_IP6, /*UDF for IPv6 packets*/
+        FAL_ACL_UDF_BUTT,
+    }fal_acl_udf_pkt_type_t;
+
+typedef enum {
+	FAL_ACL_DEST_PORT_BMP = 0, /*dest info is bitmap*/
+	FAL_ACL_DEST_NEXTHOP, /*dest info is nexthop*/
+	FAL_ACL_DEST_PORT_ID, /*dest info is port id*/
+}fal_acl_dest_type_t;
+
+#define FAL_ACL_DEST_OFFSET(type,value) (((type)<<24)|(value))
+#define FAL_ACL_DEST_TYPE(dest) (((dest)>>24)&0xff)
+#define FAL_ACL_DEST_VALUE(dest) ((dest)&0xffffff)
+
+#define    FAL_ACL_FIELD_MAC_DA         0
+#define    FAL_ACL_FIELD_MAC_SA         1
+#define    FAL_ACL_FIELD_MAC_ETHTYPE    2
+#define    FAL_ACL_FIELD_MAC_TAGGED     3
+#define    FAL_ACL_FIELD_MAC_UP         4
+#define    FAL_ACL_FIELD_MAC_VID        5
+#define    FAL_ACL_FIELD_IP4_SIP        6
+#define    FAL_ACL_FIELD_IP4_DIP        7
+#define    FAL_ACL_FIELD_IP6_LABEL      8
+#define    FAL_ACL_FIELD_IP6_SIP        9
+#define    FAL_ACL_FIELD_IP6_DIP        10
+#define    FAL_ACL_FIELD_IP_PROTO       11
+#define    FAL_ACL_FIELD_IP_DSCP        12
+#define    FAL_ACL_FIELD_L4_SPORT       13
+#define    FAL_ACL_FIELD_L4_DPORT       14
+#define    FAL_ACL_FIELD_UDF            15
+#define    FAL_ACL_FIELD_MAC_CFI        16
+#define    FAL_ACL_FIELD_ICMP_TYPE      17
+#define    FAL_ACL_FIELD_ICMP_CODE      18
+#define    FAL_ACL_FIELD_TCP_FLAG       19
+#define    FAL_ACL_FIELD_RIPV1          20
+#define    FAL_ACL_FIELD_DHCPV4         21
+#define    FAL_ACL_FIELD_DHCPV6         22
+#define    FAL_ACL_FIELD_MAC_STAG_VID   23
+#define    FAL_ACL_FIELD_MAC_STAG_PRI   24
+#define    FAL_ACL_FIELD_MAC_STAG_DEI   25
+#define    FAL_ACL_FIELD_MAC_STAGGED    26
+#define    FAL_ACL_FIELD_MAC_CTAG_VID   27
+#define    FAL_ACL_FIELD_MAC_CTAG_PRI   28
+#define    FAL_ACL_FIELD_MAC_CTAG_CFI   29
+#define    FAL_ACL_FIELD_MAC_CTAGGED    30
+#define    FAL_ACL_FIELD_INVERSE_ALL    31
+/*new add for hawkeye*/
+#define    FAL_ACL_FIELD_POST_ROURING_EN    32
+#define    FAL_ACL_FIELD_RES_CHAIN    	    33
+#define    FAL_ACL_FIELD_FAKE_MAC_HEADER    34
+#define    FAL_ACL_FIELD_SNAP    35
+#define    FAL_ACL_FIELD_ETHERNET    36
+#define    FAL_ACL_FIELD_IPV6    37
+#define    FAL_ACL_FIELD_IP    38
+#define    FAL_ACL_FIELD_VSI    39
+#define    FAL_ACL_FIELD_PPPOE_SESSIONID    40
+#define    FAL_ACL_FIELD_L3_FRAGMENT    41
+#define    FAL_ACL_FIELD_AH_HEADER    42
+#define    FAL_ACL_FIELD_ESP_HEADER    43
+#define    FAL_ACL_FIELD_MOBILITY_HEADER    44
+#define    FAL_ACL_FIELD_FRAGMENT_HEADER    45
+#define    FAL_ACL_FIELD_OTHER_EXT_HEADER    46
+#define    FAL_ACL_FIELD_L3_TTL    47
+#define    FAL_ACL_FIELD_IPV4_OPTION    48
+#define    FAL_ACL_FIELD_FIRST_FRAGMENT    49
+#define    FAL_ACL_FIELD_L3_LENGTH    50
+#define    FAL_ACL_FIELD_VSI_VALID    51
+#define    FAL_ACL_FIELD_IP_PKT_TYPE    52
+
+#define    FAL_ACL_FIELD_UDF0            53
+#define    FAL_ACL_FIELD_UDF1            54
+#define    FAL_ACL_FIELD_UDF2            55
+#define    FAL_ACL_FIELD_UDF3            56
+
+#define    FAL_ACL_FIELD_NUM    57
+
+
+#define    FAL_ACL_ACTION_PERMIT        0
+#define    FAL_ACL_ACTION_DENY          1
+#define    FAL_ACL_ACTION_REDPT         2
+#define    FAL_ACL_ACTION_RDTCPU        3
+#define    FAL_ACL_ACTION_CPYCPU        4
+#define    FAL_ACL_ACTION_MIRROR        5
+#define    FAL_ACL_ACTION_MODIFY_VLAN   6
+#define    FAL_ACL_ACTION_NEST_VLAN     7
+#define    FAL_ACL_ACTION_REMARK_UP     8
+#define    FAL_ACL_ACTION_REMARK_QUEUE  9
+#define    FAL_ACL_ACTION_REMARK_STAG_VID     10
+#define    FAL_ACL_ACTION_REMARK_STAG_PRI     11
+#define    FAL_ACL_ACTION_REMARK_STAG_DEI     12
+#define    FAL_ACL_ACTION_REMARK_CTAG_VID     13
+#define    FAL_ACL_ACTION_REMARK_CTAG_PRI     14
+#define    FAL_ACL_ACTION_REMARK_CTAG_CFI     15
+#define    FAL_ACL_ACTION_REMARK_LOOKUP_VID   16
+#define    FAL_ACL_ACTION_REMARK_DSCP         17
+#define    FAL_ACL_ACTION_POLICER_EN          18
+#define    FAL_ACL_ACTION_WCMP_EN             19
+#define    FAL_ACL_ACTION_ARP_EN              20
+#define    FAL_ACL_ACTION_POLICY_FORWARD_EN   21
+#define    FAL_ACL_ACTION_BYPASS_EGRESS_TRANS 22
+#define    FAL_ACL_ACTION_MATCH_TRIGGER_INTR  23
+/*new add for hawkeye*/
+#define    FAL_ACL_ACTION_ENQUEUE_PRI 25
+#define    FAL_ACL_ACTION_INT_DP 26
+#define    FAL_ACL_ACTION_SERVICE_CODE 27
+#define    FAL_ACL_ACTION_CPU_CODE 28
+#define    FAL_ACL_ACTION_SYN_TOGGLE 29
+#define    FAL_ACL_ACTION_METADATA_EN 30
+
+
+enum{
+	FAL_ACL_BYPASS_IN_VLAN_MISS = 0,
+	FAL_ACL_BYPASS_SOUCE_GUARD,
+	FAL_ACL_BYPASS_MRU_MTU_CHECK,
+	FAL_ACL_BYPASS_EG_VSI_MEMBER_CHECK = 8,
+	FAL_ACL_BYPASS_EG_VLAN_TRANSLATION,
+	FAL_ACL_BYPASS_EG_VLAN_TAG_CTRL = 10,
+	FAL_ACL_BYPASS_FDB_LEARNING,
+	FAL_ACL_BYPASS_FDB_REFRESH,
+	FAL_ACL_BYPASS_L2_SECURITY,/*new address, station move, learn limit, hash full*/
+	FAL_ACL_BYPASS_MANAGEMENT_FWD,
+	FAL_ACL_BYPASS_L2_FWD = 15,
+	FAL_ACL_BYPASS_IN_STP_CHECK,
+	FAL_ACL_BYPASS_EG_STP_CHECK,
+	FAL_ACL_BYPASS_SOURCE_FILTER,
+	FAL_ACL_BYPASS_POLICYER,
+	FAL_ACL_BYPASS_L2_EDIT = 20,/*VLAN tag edit*/
+	FAL_ACL_BYPASS_L3_EDIT,/*Edit MAC address, PPPoE, IP address, TTL, DSCP, L4 port*/
+	FAL_ACL_BYPASS_POST_ACL_CHECK_ROUTING,
+	FAL_ACL_BYPASS_PORT_ISOLATION,
+};
+
+
+    /**
+      * @brief This type defines the action in Acl rule.
+      *   @details  Comments:
+      *  It's a bit map type, we can access it through macro FAL_ACTION_FLG_SET,
+      * FAL_ACTION_FLG_CLR and FAL_ACTION_FLG_TST.
+    */
+    typedef a_uint32_t fal_acl_action_map_t;
+
+#define FAL_ACTION_FLG_SET(flag, action) \
+    (flag) |= (0x1UL << (action))
+
+#define FAL_ACTION_FLG_CLR(flag, action) \
+    (flag) &= (~(0x1UL << (action)))
+
+#define FAL_ACTION_FLG_TST(flag, action) \
+    ((flag) & (0x1UL << (action))) ? 1 : 0
+
+
+    /**
+      * @brief This type defines the field in Acl rule.
+      *   @details   Comments:
+      *   It's a bit map type, we can access it through macro FAL_FIELD_FLG_SET,
+      *   FAL_FIELD_FLG_CLR and FAL_FIELD_FLG_TST.
+    */
+    typedef a_uint32_t fal_acl_field_map_t[2];
+
+#define FAL_FIELD_FLG_SET(flag, field) \
+    ((flag[(field) / 32]) |= (0x1UL << ((field) % 32)))
+
+#define FAL_FIELD_FLG_CLR(flag, field) \
+    ((flag[(field) / 32]) &= (~(0x1UL << ((field) % 32))))
+
+#define FAL_FIELD_FLG_TST(flag, field) \
+    (((flag[(field) / 32]) & (0x1UL << ((field) % 32))) ? 1 : 0)
+
+#define FAL_ACL_UDF_MAX_LENGTH 16
+
+    /**
+     * @brief This structure defines the Acl rule.
+     *   @details  Fields description:
+     *
+     *
+     *    vid_val - If vid_op equals FAL_ACL_FIELD_MASK it's vlan id field value.
+     *     If vid_op equals FAL_ACL_FIELD_RANGE it's vlan id field low value. If
+     *     vid_op equals other value it's the compared value.
+     *
+     *     vid_mask - If vid_op equals FAL_ACL_FIELD_MASK it's vlan id field mask.
+     *     If vid_op equals FAL_ACL_FIELD_RANGE it's vlan id field high value. If vid_op
+     *     equals other value it's meaningless.
+     *
+     *
+     *     ip_dscp_val - It's eight bits field we can set any value between 0 - 255.
+     *     ip_dscp_mask - It's eight bits field we can set any value between 0 - 255.
+     *
+     *
+     *     src_l4port_val - If src_l4port_op equals FAL_ACL_FIELD_MASK it's layer four
+     *     source port field value. If src_l4port_op equals FAL_ACL_FIELD_RANGE it's
+     *     layer four source port field low value. If src_l4port_op equals other value
+     *     it's the compared value.
+     *
+     *
+     *     src_l4port_mask - If src_l4port_op equals FAL_ACL_FIELD_MASK it's layer four
+     *     source port field mask. If src_l4port_op equals FAL_ACL_FIELD_RANGE it's
+     *     layer four source port field high value. If src_l4port_op equals other value
+     *     it's meaningless.
+     *
+     *
+     *     dest_l4port_val - If dest_l4port_op equals FAL_ACL_FIELD_MASK it's layer four
+     *     destination port field value. If dest_l4port_op equals FAL_ACL_FIELD_RANGE it's
+     *     layer four source port field low value. If dest_l4port_op equals other value
+     *     it's the compared value.
+     *
+     *
+     *     dest_l4port_mask - If dest_l4port_op equals FAL_ACL_FIELD_MASK it's layer four
+     *     source port field mask. If dest_l4port_op equals FAL_ACL_FIELD_RANGE it's
+     *     layer four source port field high value. If dest_l4port_op equals other value
+     *     it's meaningless.
+     *
+     *
+     *     ports - If FAL_ACL_ACTION_REDPT bit is setted in action_flg it's redirect
+     *     destination ports.
+     *
+     *
+     *     dot1p - If FAL_ACL_ACTION_REMARK_DOT1P bit is setted in action_flg it's
+     *     the expected dot1p value.
+     *
+     *
+     *     queue - If FAL_ACL_ACTION_REMARK_QUEUE bit is setted in action_flg it's
+     *     the expected queue value.
+     *
+     *
+     *     vid - If FAL_ACL_ACTION_MODIFY_VLAN or FAL_ACL_ACTION_NEST_VLAN bit is
+     *     setted in action_flg it's the expected vlan id value.
+     */
+typedef struct
+{
+	fal_acl_rule_type_t rule_type;/*mac, IP4, IP6 and UDF*/
+	fal_acl_field_map_t field_flg;/*Indicate which fields are selected*/
+
+	/* fields of mac rule */
+	fal_mac_addr_t     src_mac_val;/*source mac*/
+	fal_mac_addr_t     src_mac_mask;/*source mac mask*/
+	fal_mac_addr_t     dest_mac_val;/*destination mac*/
+	fal_mac_addr_t     dest_mac_mask;/*destionation mac mask*/
+	a_uint16_t         ethtype_val;/*ethernet type*/
+	a_uint16_t         ethtype_mask;/*ethernet type mask*/
+	a_uint16_t         vid_val;/*vlan id, IPQ807x not support*/
+	a_uint16_t         vid_mask;/*vlan id mask*/
+	fal_acl_field_op_t vid_op;/*vlan id operation, larger than or smaller than or range or mask*/
+	a_uint8_t          tagged_val;/*tagged or not, IPQ807x not support*/
+	a_uint8_t          tagged_mask;/*tagged or not mask*/
+	a_uint8_t          up_val;/*cos priority, IPQ807x not support*/
+	a_uint8_t          up_mask;/*cos priority mask*/
+	a_uint8_t          cfi_val;/*CFI value, IPQ807x not support*/
+	a_uint8_t          cfi_mask;/*CFI value mask*/
+	a_uint16_t         resv0;/*reserved*/
+
+	/* fields of enhanced mac rule*/
+	a_uint8_t          stagged_val; /*for s17c : 0-untag, 1-tag, for hawkeye: 2-pritag, 3-utag+pritag, 4- untag+tag, 5-tag+pritag, 6-all*/
+	a_uint8_t          stagged_mask;
+	a_uint8_t          ctagged_val;/*same as stagged define*/
+	a_uint8_t          ctagged_mask;
+	a_uint16_t         stag_vid_val;/*stag vlan id*/
+	a_uint16_t         stag_vid_mask;/*stag vlan id mask*/
+	fal_acl_field_op_t stag_vid_op;/*vlan id operation, larger than or smaller than or range or mask*/
+	a_uint16_t         ctag_vid_val;
+	a_uint16_t         ctag_vid_mask;
+	fal_acl_field_op_t ctag_vid_op;
+	a_uint8_t          stag_pri_val;/*stag priority*/
+	a_uint8_t          stag_pri_mask;/*stag priority mask*/
+	a_uint8_t          ctag_pri_val;
+	a_uint8_t          ctag_pri_mask;
+	a_uint8_t          stag_dei_val;/*stag dei*/
+	a_uint8_t          stag_dei_mask;/*stag dei mask*/
+	a_uint8_t          ctag_cfi_val;/*ctag cfi*/
+	a_uint8_t          ctag_cfi_mask;/*ctag cfi mask*/
+
+	/* fields of ip4 rule */
+	fal_ip4_addr_t      src_ip4_val;/*source ipv4 address*/
+	fal_ip4_addr_t      src_ip4_mask;/*source ipv4 address mask*/
+	fal_ip4_addr_t      dest_ip4_val;/*destination ipv4 address*/
+	fal_ip4_addr_t      dest_ip4_mask;/*destination ipv4 address mask*/
+
+	/* fields of ip6 rule */
+	a_uint32_t         ip6_lable_val;/*ipv6 flow lable, IPQ807x not support*/
+	a_uint32_t         ip6_lable_mask;/*ipv6 flow lable mask*/
+	fal_ip6_addr_t      src_ip6_val;/*source ipv6 address*/
+	fal_ip6_addr_t      src_ip6_mask;/*source ipv6 address mask*/
+	fal_ip6_addr_t      dest_ip6_val;/*destination ipv6 address*/
+	fal_ip6_addr_t      dest_ip6_mask;/*destination ipv6 address mask*/
+
+	/* fields of ip rule */
+	a_uint8_t          ip_proto_val;/*IP protocal*/
+	a_uint8_t          ip_proto_mask;/*IP protocal mask*/
+	a_uint8_t          ip_dscp_val;/*IP DSCP*/
+	a_uint8_t          ip_dscp_mask;/*IP DSCP mask*/
+
+	/* fields of layer four */
+	a_uint16_t         src_l4port_val;/*source L4 port*/
+	a_uint16_t         src_l4port_mask;/*source L4 port mask*/
+	fal_acl_field_op_t src_l4port_op;/*source L4 port operation*/
+	a_uint16_t         dest_l4port_val;/*destination L4 port*/
+	a_uint16_t         dest_l4port_mask;/*destination L4 mask*/
+	fal_acl_field_op_t dest_l4port_op;/*destination L4 operation*/
+	a_uint8_t          icmp_type_val;/*ICMP type*/
+	a_uint8_t          icmp_type_mask;/*ICMP type mask*/
+	a_uint8_t          icmp_code_val;/*ICMP code*/
+	a_uint8_t          icmp_code_mask;/*ICMP code mask*/
+	a_uint8_t          tcp_flag_val;/*tcp flags value*/
+	a_uint8_t          tcp_flag_mask;/*tcp flags mask*/
+	a_uint8_t          ripv1_val;/*Is RIPv1 or not, IPQ807x not support*/
+	a_uint8_t          ripv1_mask;/*RIPv1 mask*/
+	a_uint8_t          dhcpv4_val;/*Is DHCPv4 or not, IPQ807x not support*/
+	a_uint8_t          dhcpv4_mask;
+	a_uint8_t          dhcpv6_val;/*Is DHCPv6 or not, IPQ807x not support*/
+	a_uint8_t          dhcpv6_mask;
+
+	/* user defined fields */
+	fal_acl_udf_type_t udf_type;/*UDF type, IPQ807x not support*/
+	a_uint8_t udf_offset;/*UDF offset, IPQ807x not support*/
+	a_uint8_t udf_len;/*UDF length, IPQ807x not support*/
+	a_uint8_t udf_val[FAL_ACL_UDF_MAX_LENGTH];/*UDF field value*/
+	a_uint8_t udf_mask[FAL_ACL_UDF_MAX_LENGTH];/*UDF field mask*/
+
+	/* fields of action */
+	fal_acl_action_map_t  action_flg;/*Indicate which action apply*/
+	fal_pbmp_t            ports; /*high 8bits, 00-port bitmap, 01-nexthop, 10-vp*/
+	a_uint32_t            match_cnt;/*rule match frame counter*/
+	a_uint16_t            vid;/*modify vlan id, IPQ807x not support*/
+	a_uint8_t             up;/*modify COS priority, IPQ807x not support*/
+	a_uint8_t             queue;/*modify queue*/
+	a_uint16_t            stag_vid;/*modify stag vlan id*/
+	a_uint8_t             stag_pri;/*modify stag priority*/
+	a_uint8_t             stag_dei;/*modify stag dei*/
+	a_uint16_t            ctag_vid;/*modify ctag vlan id*/
+	a_uint8_t             ctag_pri;/*modify ctag priority*/
+	a_uint8_t             ctag_cfi;/*modify ctag dei*/
+	a_uint16_t            policer_ptr;/*specify policer index*/
+	a_uint16_t            arp_ptr;/*specify arp table index, IPQ807x not support*/
+	a_uint16_t            wcmp_ptr;/*specify wcmp table index, IPQ807x not support*/
+	a_uint8_t             dscp;/*modify dscp*/
+	a_uint8_t             rsv;
+	fal_policy_forward_t  policy_fwd;/*SNAT or DNAT or ROUTE, IPQ807x not support*/
+	fal_combined_t    combined;
+
+	/*Only IPQ807x support start*/
+	a_uint8_t pri; /*rule priority 0-7*/
+	a_bool_t post_routing;/*post routing or not*/
+	a_uint8_t acl_pool;/*acl pool*/
+
+	a_bool_t is_ip_val;/*is ip or not*/
+	a_uint8_t is_ip_mask;
+	a_bool_t is_ipv6_val;/*is ipv6 or ipv4*/
+	a_uint8_t is_ipv6_mask;
+	a_bool_t is_fake_mac_header_val;/*is fake mac header or not*/
+	a_uint8_t is_fake_mac_header_mask;
+	a_bool_t is_snap_val;/*is snap or not*/
+	a_uint8_t is_snap_mask;
+	a_bool_t is_ethernet_val;/*is ethernet or not*/
+	a_uint8_t is_ethernet_mask;
+
+	a_bool_t is_fragement_val;/*is fragment or not*/
+	a_uint8_t is_fragement_mask;
+
+	a_bool_t is_ah_header_val;/*is ah header or not*/
+	a_uint8_t is_ah_header_mask;
+
+	a_bool_t is_esp_header_val;/*is esp header or not*/
+	a_uint8_t is_esp_header_mask;
+
+	a_bool_t is_mobility_header_val;/*is mobility header or not*/
+	a_uint8_t is_mobility_header_mask;
+
+	a_bool_t is_fragment_header_val;/*is fragment header or not*/
+	a_uint8_t is_fragment_header_mask;
+
+	a_bool_t is_other_header_val;/*is other header or not*/
+	a_uint8_t is_other_header_mask;
+
+	a_bool_t is_ipv4_option_val;/*is ipv4 option or not*/
+	a_uint8_t is_ipv4_option_mask;
+
+	a_bool_t is_first_frag_val;/*is first fragment or not*/
+	a_uint8_t is_first_frag_mask;
+
+	/*fields of VLAN rule*/
+	a_bool_t vsi_valid;/*vsi valid or not*/
+	a_uint8_t vsi_valid_mask;
+	a_uint8_t vsi; /*vsi value 0-31*/
+	a_uint8_t vsi_mask; /*vsi mask 0-31*/
+	/*fields of L2 MISC rule*/
+	a_uint16_t pppoe_sessionid;/*pppoe session id*/
+	a_uint16_t pppoe_sessionid_mask;/*pppoe session mask*/
+	fal_acl_field_op_t icmp_type_code_op;/*icmp type operation*/
+	/*fields of IP MISC rule*/
+	a_uint8_t l3_ttl;/*L3 TTL,0-ttl 0, 1-ttl 1, 2-ttl 255, 3- ttl other*/
+	a_uint8_t l3_ttl_mask;/*L3 TTL mask*/
+	fal_acl_field_op_t l3_length_op;/*L3 TTL operation*/
+	a_uint16_t l3_length;/*L3 length*/
+	a_uint16_t l3_length_mask;/*L3 length mask*/
+	a_uint16_t l3_pkt_type;/*l3 packet type, 0-tcp, 1-udp, 3-udp_lite, 5-arp, 7-icmp*/
+	a_uint16_t l3_pkt_type_mask;
+	/*field of udf*/
+	fal_acl_field_op_t udf0_op;/*udf operation*/
+	a_uint16_t udf0_val;/*udf value, 2bytes*/
+	a_uint16_t udf0_mask;/*udf mask, 2bytes*/
+	fal_acl_field_op_t udf1_op;
+	a_uint16_t udf1_val;
+	a_uint16_t udf1_mask;
+	a_uint16_t udf2_val;
+	a_uint16_t udf2_mask;
+	a_uint16_t udf3_val;
+	a_uint16_t udf3_mask;
+
+	/*new add acl action for hawkeye*/
+	a_uint32_t bypass_bitmap;/*bypass bitmap*/
+	a_uint8_t enqueue_pri;/*enqueue priority*/
+	a_uint8_t stag_fmt;/*stag format*/
+	a_uint8_t ctag_fmt;/*ctag format*/
+	a_uint8_t int_dp;/*internal dp*/
+	a_uint8_t service_code;/*service code*/
+	a_uint8_t cpu_code;/*cpu code*/
+	a_uint64_t match_bytes;/*rule match bytes counter*/
+	/*Only IPQ807x support End*/
+
+	/*new add acl action for IPQ60xx*/
+	a_uint8_t dscp_mask;/*modify dscp mask,IPQ60xx support*/
+	a_uint8_t qos_res_prec;/*qos res prec,IPQ60xx support*/
+} fal_acl_rule_t;
+
+
+    /**
+    @brief This enum defines the ACL will work on which derection traffic.
+    */
+    typedef enum
+    {
+        FAL_ACL_DIREC_IN = 0,   /**<   Acl will work on ingressive traffic */
+        FAL_ACL_DIREC_EG,       /**<   Acl will work on egressive traffic */
+        FAL_ACL_DIREC_BOTH,     /**<    Acl will work on both ingressive and egressive traffic*/
+    } fal_acl_direc_t;
+
+
+    /**
+    @brief This enum defines the ACL will work on which partiualr object.
+    */
+    typedef enum
+    {
+        FAL_ACL_BIND_PORT = 0,  /**<   Acl wil work on particular port and virtual port */
+        FAL_ACL_BIND_PORTBITMAP = 1,  /**<   Acl wil work on port bitmap */
+        FAL_ACL_BIND_SERVICE_CODE = 2,  /**<   Acl wil work on service code */
+        FAL_ACL_BIND_L3_IF = 3,  /**<   Acl wil work on l3 interface */
+    } fal_acl_bind_obj_t;
+
+enum
+{
+	/*acl*/
+	FUNC_ACL_LIST_CREAT = 0,
+	FUNC_ACL_LIST_DESTROY,
+	FUNC_ACL_RULE_ADD,
+	FUNC_ACL_RULE_DELETE,
+	FUNC_ACL_RULE_QUERY,
+	FUNC_ACL_RULE_DUMP,
+	FUNC_ACL_LIST_BIND,
+	FUNC_ACL_LIST_UNBIND,
+	FUNC_ACL_LIST_DUMP,
+	FUNC_ACL_UDF_PROFILE_SET,
+	FUNC_ACL_UDF_PROFILE_GET,
+};
+
+
+sw_error_t
+fal_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri);
+
+sw_error_t
+fal_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id);
+
+sw_error_t
+fal_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule);
+
+sw_error_t
+fal_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr);
+
+sw_error_t
+fal_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, fal_acl_rule_t * rule);
+
+sw_error_t
+fal_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx);
+
+sw_error_t
+fal_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx);
+
+sw_error_t
+fal_acl_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+sw_error_t
+fal_acl_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+sw_error_t
+fal_acl_list_dump(a_uint32_t dev_id);
+
+sw_error_t
+fal_acl_rule_dump(a_uint32_t dev_id);
+
+sw_error_t
+fal_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id, fal_acl_udf_type_t udf_type, a_uint32_t offset, a_uint32_t length);
+sw_error_t
+fal_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id, fal_acl_udf_type_t udf_type, a_uint32_t * offset, a_uint32_t * length);
+
+sw_error_t
+fal_acl_udf_profile_set(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t udf_type, a_uint32_t offset);
+
+sw_error_t
+fal_acl_udf_profile_get(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t *udf_type, a_uint32_t *offset);
+
+sw_error_t
+fal_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr);
+sw_error_t
+fal_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr);
+sw_error_t
+fal_acl_rule_src_filter_sts_set(a_uint32_t dev_id, a_uint32_t rule_id, a_bool_t enable);
+sw_error_t
+fal_acl_rule_src_filter_sts_get(a_uint32_t dev_id, a_uint32_t rule_id, a_bool_t* enable);
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_ACL_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_api.h b/qca-ssdk/include/fal/fal_api.h
new file mode 100755
index 0000000..51aff57
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_api.h
@@ -0,0 +1,2428 @@
+/*
+ * Copyright (c) 2012, 2015-2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/*qca808x_start*/
+#ifndef _FAL_API_H_
+#define _FAL_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+/*qca808x_end*/
+#ifdef IN_PORTCONTROL
+#ifndef IN_PORTCONTROL_MINI
+/*qca808x_start*/
+#define PORTCONTROL_API \
+    SW_API_DEF(SW_API_PT_DUPLEX_GET, fal_port_duplex_get), \
+    SW_API_DEF(SW_API_PT_DUPLEX_SET, fal_port_duplex_set), \
+    SW_API_DEF(SW_API_PT_SPEED_GET, fal_port_speed_get), \
+    SW_API_DEF(SW_API_PT_SPEED_SET, fal_port_speed_set), \
+    SW_API_DEF(SW_API_PT_AN_GET, fal_port_autoneg_status_get), \
+    SW_API_DEF(SW_API_PT_AN_ENABLE, fal_port_autoneg_enable), \
+    SW_API_DEF(SW_API_PT_AN_RESTART, fal_port_autoneg_restart), \
+    SW_API_DEF(SW_API_PT_AN_ADV_GET, fal_port_autoneg_adv_get), \
+    SW_API_DEF(SW_API_PT_AN_ADV_SET, fal_port_autoneg_adv_set), \
+/*qca808x_end*/\
+    SW_API_DEF(SW_API_PT_HDR_SET, fal_port_hdr_status_set), \
+    SW_API_DEF(SW_API_PT_HDR_GET, fal_port_hdr_status_get), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_SET, fal_port_flowctrl_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_GET, fal_port_flowctrl_get), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, fal_port_flowctrl_forcemode_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, fal_port_flowctrl_forcemode_get), \
+    SW_API_DEF(SW_API_PT_POWERSAVE_SET, fal_port_powersave_set), \
+    SW_API_DEF(SW_API_PT_POWERSAVE_GET, fal_port_powersave_get), \
+/*qca808x_start*/\
+    SW_API_DEF(SW_API_PT_HIBERNATE_SET, fal_port_hibernate_set), \
+    SW_API_DEF(SW_API_PT_HIBERNATE_GET, fal_port_hibernate_get), \
+    SW_API_DEF(SW_API_PT_CDT, fal_port_cdt),  \
+/*qca808x_end*/\
+    SW_API_DEF(SW_API_PT_TXHDR_SET, fal_port_txhdr_mode_set), \
+    SW_API_DEF(SW_API_PT_TXHDR_GET, fal_port_txhdr_mode_get), \
+    SW_API_DEF(SW_API_PT_RXHDR_SET, fal_port_rxhdr_mode_set), \
+    SW_API_DEF(SW_API_PT_RXHDR_GET, fal_port_rxhdr_mode_get), \
+    SW_API_DEF(SW_API_HEADER_TYPE_SET, fal_header_type_set),  \
+    SW_API_DEF(SW_API_HEADER_TYPE_GET, fal_header_type_get),  \
+    SW_API_DEF(SW_API_TXMAC_STATUS_SET, fal_port_txmac_status_set), \
+    SW_API_DEF(SW_API_TXMAC_STATUS_GET, fal_port_txmac_status_get), \
+    SW_API_DEF(SW_API_RXMAC_STATUS_SET, fal_port_rxmac_status_set), \
+    SW_API_DEF(SW_API_RXMAC_STATUS_GET, fal_port_rxmac_status_get), \
+    SW_API_DEF(SW_API_TXFC_STATUS_SET, fal_port_txfc_status_set),   \
+    SW_API_DEF(SW_API_TXFC_STATUS_GET, fal_port_txfc_status_get),   \
+    SW_API_DEF(SW_API_RXFC_STATUS_SET, fal_port_rxfc_status_set),   \
+    SW_API_DEF(SW_API_RXFC_STATUS_GET, fal_port_rxfc_status_get),   \
+    SW_API_DEF(SW_API_BP_STATUS_SET, fal_port_bp_status_set),   \
+    SW_API_DEF(SW_API_BP_STATUS_GET, fal_port_bp_status_get),   \
+    SW_API_DEF(SW_API_PT_LINK_MODE_SET, fal_port_link_forcemode_set),   \
+    SW_API_DEF(SW_API_PT_LINK_MODE_GET, fal_port_link_forcemode_get), \
+/*qca808x_start*/\
+    SW_API_DEF(SW_API_PT_LINK_STATUS_GET, fal_port_link_status_get), \
+/*qca808x_end*/\
+    SW_API_DEF(SW_API_PT_MAC_LOOPBACK_SET, fal_port_mac_loopback_set), \
+    SW_API_DEF(SW_API_PT_MAC_LOOPBACK_GET, fal_port_mac_loopback_get), \
+    SW_API_DEF(SW_API_PTS_LINK_STATUS_GET, fal_ports_link_status_get), \
+    SW_API_DEF(SW_API_PT_CONGESTION_DROP_SET, fal_port_congestion_drop_set), \
+    SW_API_DEF(SW_API_PT_CONGESTION_DROP_GET, fal_port_congestion_drop_get), \
+    SW_API_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_SET, fal_ring_flow_ctrl_thres_set), \
+    SW_API_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_GET, fal_ring_flow_ctrl_thres_get), \
+/*qca808x_start*/\
+    SW_API_DEF(SW_API_PT_8023AZ_SET, fal_port_8023az_set), \
+    SW_API_DEF(SW_API_PT_8023AZ_GET, fal_port_8023az_get), \
+    SW_API_DEF(SW_API_PT_MDIX_SET, fal_port_mdix_set), \
+    SW_API_DEF(SW_API_PT_MDIX_GET, fal_port_mdix_get), \
+    SW_API_DEF(SW_API_PT_MDIX_STATUS_GET, fal_port_mdix_status_get), \
+/*qca808x_end*/\
+    SW_API_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_SET, fal_port_combo_prefer_medium_set), \
+    SW_API_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_GET, fal_port_combo_prefer_medium_get), \
+    SW_API_DEF(SW_API_PT_COMBO_MEDIUM_STATUS_GET, fal_port_combo_medium_status_get), \
+    SW_API_DEF(SW_API_PT_COMBO_FIBER_MODE_SET, fal_port_combo_fiber_mode_set), \
+    SW_API_DEF(SW_API_PT_COMBO_FIBER_MODE_GET, fal_port_combo_fiber_mode_get), \
+/*qca808x_start*/\
+    SW_API_DEF(SW_API_PT_LOCAL_LOOPBACK_SET, fal_port_local_loopback_set), \
+    SW_API_DEF(SW_API_PT_LOCAL_LOOPBACK_GET, fal_port_local_loopback_get), \
+    SW_API_DEF(SW_API_PT_REMOTE_LOOPBACK_SET, fal_port_remote_loopback_set), \
+    SW_API_DEF(SW_API_PT_REMOTE_LOOPBACK_GET, fal_port_remote_loopback_get), \
+    SW_API_DEF(SW_API_PT_RESET, fal_port_reset), \
+    SW_API_DEF(SW_API_PT_POWER_OFF, fal_port_power_off), \
+    SW_API_DEF(SW_API_PT_POWER_ON, fal_port_power_on), \
+    SW_API_DEF(SW_API_PT_MAGIC_FRAME_MAC_SET, fal_port_magic_frame_mac_set), \
+    SW_API_DEF(SW_API_PT_MAGIC_FRAME_MAC_GET, fal_port_magic_frame_mac_get), \
+    SW_API_DEF(SW_API_PT_PHY_ID_GET, fal_port_phy_id_get), \
+    SW_API_DEF(SW_API_PT_WOL_STATUS_SET, fal_port_wol_status_set), \
+    SW_API_DEF(SW_API_PT_WOL_STATUS_GET, fal_port_wol_status_get), \
+/*qca808x_end*/\
+    SW_API_DEF(SW_API_PT_INTERFACE_MODE_SET, fal_port_interface_mode_set), \
+    SW_API_DEF(SW_API_PT_INTERFACE_MODE_APPLY, fal_port_interface_mode_apply), \
+    SW_API_DEF(SW_API_PT_INTERFACE_MODE_GET, fal_port_interface_mode_get), \
+/*qca808x_start*/\
+    SW_API_DEF(SW_API_PT_INTERFACE_MODE_STATUS_GET, fal_port_interface_mode_status_get), \
+    SW_API_DEF(SW_API_DEBUG_PHYCOUNTER_SET, fal_debug_phycounter_set), \
+    SW_API_DEF(SW_API_DEBUG_PHYCOUNTER_GET, fal_debug_phycounter_get), \
+    SW_API_DEF(SW_API_DEBUG_PHYCOUNTER_SHOW, fal_debug_phycounter_show),\
+/*qca808x_end*/\
+    SW_API_DEF(SW_API_PT_MTU_SET, fal_port_mtu_set), \
+    SW_API_DEF(SW_API_PT_MTU_GET, fal_port_mtu_get), \
+    SW_API_DEF(SW_API_PT_MRU_SET, fal_port_mru_set), \
+    SW_API_DEF(SW_API_PT_MRU_GET, fal_port_mru_get), \
+    SW_API_DEF(SW_API_PT_SOURCE_FILTER_GET, fal_port_source_filter_status_get), \
+    SW_API_DEF(SW_API_PT_SOURCE_FILTER_SET, fal_port_source_filter_enable), \
+    SW_API_DEF(SW_API_PT_FRAME_MAX_SIZE_GET, fal_port_max_frame_size_get), \
+    SW_API_DEF(SW_API_PT_FRAME_MAX_SIZE_SET, fal_port_max_frame_size_set), \
+    SW_API_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_SET, fal_port_interface_3az_status_set), \
+    SW_API_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_GET, fal_port_interface_3az_status_get), \
+    SW_API_DEF(SW_API_PT_PROMISC_MODE_SET, fal_port_promisc_mode_set),  \
+    SW_API_DEF(SW_API_PT_PROMISC_MODE_GET, fal_port_promisc_mode_get), \
+    SW_API_DEF(SW_API_PT_INTERFACE_EEE_CFG_SET, fal_port_interface_eee_cfg_set),  \
+    SW_API_DEF(SW_API_PT_INTERFACE_EEE_CFG_GET, fal_port_interface_eee_cfg_get),  \
+    SW_API_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_GET, fal_port_source_filter_config_get), \
+    SW_API_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_SET, fal_port_source_filter_config_set),  \
+    SW_API_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_SET, fal_switch_port_loopback_set),  \
+    SW_API_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_GET, fal_switch_port_loopback_get),
+/*qca808x_start*/
+/*end of PORTCONTROL_API*/
+#define PORTCONTROL_API_PARAM \
+    SW_API_DESC(SW_API_PT_DUPLEX_GET) \
+    SW_API_DESC(SW_API_PT_DUPLEX_SET) \
+    SW_API_DESC(SW_API_PT_SPEED_GET)  \
+    SW_API_DESC(SW_API_PT_SPEED_SET)  \
+    SW_API_DESC(SW_API_PT_AN_GET) \
+    SW_API_DESC(SW_API_PT_AN_ENABLE) \
+    SW_API_DESC(SW_API_PT_AN_RESTART) \
+    SW_API_DESC(SW_API_PT_AN_ADV_GET) \
+    SW_API_DESC(SW_API_PT_AN_ADV_SET) \
+/*qca808x_end*/\
+    SW_API_DESC(SW_API_PT_HDR_SET) \
+    SW_API_DESC(SW_API_PT_HDR_GET) \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_SET) \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_GET) \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET) \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \
+    SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
+    SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
+/*qca808x_start*/\
+    SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
+    SW_API_DESC(SW_API_PT_HIBERNATE_GET) \
+    SW_API_DESC(SW_API_PT_CDT) \
+/*qca808x_end*/\
+    SW_API_DESC(SW_API_PT_TXHDR_SET) \
+    SW_API_DESC(SW_API_PT_TXHDR_GET) \
+    SW_API_DESC(SW_API_PT_RXHDR_SET) \
+    SW_API_DESC(SW_API_PT_RXHDR_GET) \
+    SW_API_DESC(SW_API_HEADER_TYPE_SET) \
+    SW_API_DESC(SW_API_HEADER_TYPE_GET) \
+    SW_API_DESC(SW_API_TXMAC_STATUS_SET) \
+    SW_API_DESC(SW_API_TXMAC_STATUS_GET) \
+    SW_API_DESC(SW_API_RXMAC_STATUS_SET) \
+    SW_API_DESC(SW_API_RXMAC_STATUS_GET) \
+    SW_API_DESC(SW_API_TXFC_STATUS_SET) \
+    SW_API_DESC(SW_API_TXFC_STATUS_GET) \
+    SW_API_DESC(SW_API_RXFC_STATUS_SET) \
+    SW_API_DESC(SW_API_RXFC_STATUS_GET) \
+    SW_API_DESC(SW_API_BP_STATUS_SET) \
+    SW_API_DESC(SW_API_BP_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_LINK_MODE_SET) \
+    SW_API_DESC(SW_API_PT_LINK_MODE_GET) \
+/*qca808x_start*/\
+    SW_API_DESC(SW_API_PT_LINK_STATUS_GET) \
+/*qca808x_end*/\
+    SW_API_DESC(SW_API_PT_MAC_LOOPBACK_SET) \
+    SW_API_DESC(SW_API_PT_MAC_LOOPBACK_GET) \
+    SW_API_DESC(SW_API_PTS_LINK_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_CONGESTION_DROP_SET) \
+    SW_API_DESC(SW_API_PT_CONGESTION_DROP_GET) \
+    SW_API_DESC(SW_API_PT_RING_FLOW_CTRL_THRES_SET) \
+    SW_API_DESC(SW_API_PT_RING_FLOW_CTRL_THRES_GET) \
+/*qca808x_start*/\
+    SW_API_DESC(SW_API_PT_8023AZ_SET) \
+    SW_API_DESC(SW_API_PT_8023AZ_GET) \
+    SW_API_DESC(SW_API_PT_MDIX_SET) \
+    SW_API_DESC(SW_API_PT_MDIX_GET) \
+    SW_API_DESC(SW_API_PT_MDIX_STATUS_GET) \
+/*qca808x_end*/\
+    SW_API_DESC(SW_API_PT_COMBO_PREFER_MEDIUM_SET) \
+    SW_API_DESC(SW_API_PT_COMBO_PREFER_MEDIUM_GET) \
+    SW_API_DESC(SW_API_PT_COMBO_MEDIUM_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_COMBO_FIBER_MODE_SET) \
+    SW_API_DESC(SW_API_PT_COMBO_FIBER_MODE_GET) \
+/*qca808x_start*/\
+    SW_API_DESC(SW_API_PT_LOCAL_LOOPBACK_SET) \
+    SW_API_DESC(SW_API_PT_LOCAL_LOOPBACK_GET) \
+    SW_API_DESC(SW_API_PT_REMOTE_LOOPBACK_SET) \
+    SW_API_DESC(SW_API_PT_REMOTE_LOOPBACK_GET) \
+    SW_API_DESC(SW_API_PT_RESET) \
+    SW_API_DESC(SW_API_PT_POWER_OFF) \
+    SW_API_DESC(SW_API_PT_POWER_ON) \
+    SW_API_DESC(SW_API_PT_MAGIC_FRAME_MAC_SET) \
+    SW_API_DESC(SW_API_PT_MAGIC_FRAME_MAC_GET) \
+    SW_API_DESC(SW_API_PT_PHY_ID_GET) \
+    SW_API_DESC(SW_API_PT_WOL_STATUS_SET) \
+    SW_API_DESC(SW_API_PT_WOL_STATUS_GET) \
+/*qca808x_end*/\
+    SW_API_DESC(SW_API_PT_INTERFACE_MODE_SET) \
+    SW_API_DESC(SW_API_PT_INTERFACE_MODE_GET) \
+    SW_API_DESC(SW_API_PT_INTERFACE_MODE_APPLY) \
+/*qca808x_start*/\
+    SW_API_DESC(SW_API_PT_INTERFACE_MODE_STATUS_GET) \
+    SW_API_DESC(SW_API_DEBUG_PHYCOUNTER_SET) \
+    SW_API_DESC(SW_API_DEBUG_PHYCOUNTER_GET) \
+    SW_API_DESC(SW_API_DEBUG_PHYCOUNTER_SHOW) \
+/*qca808x_end*/\
+    SW_API_DESC(SW_API_PT_MTU_SET) \
+    SW_API_DESC(SW_API_PT_MTU_GET) \
+    SW_API_DESC(SW_API_PT_MRU_SET) \
+    SW_API_DESC(SW_API_PT_MRU_GET) \
+    SW_API_DESC(SW_API_PT_SOURCE_FILTER_GET) \
+    SW_API_DESC(SW_API_PT_SOURCE_FILTER_SET) \
+    SW_API_DESC(SW_API_PT_FRAME_MAX_SIZE_GET) \
+    SW_API_DESC(SW_API_PT_FRAME_MAX_SIZE_SET) \
+    SW_API_DESC(SW_API_PT_INTERFACE_3AZ_STATUS_SET)  \
+    SW_API_DESC(SW_API_PT_INTERFACE_3AZ_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_PROMISC_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_PROMISC_MODE_GET) \
+    SW_API_DESC(SW_API_PT_INTERFACE_EEE_CFG_SET)  \
+    SW_API_DESC(SW_API_PT_INTERFACE_EEE_CFG_GET)  \
+    SW_API_DESC(SW_API_PT_SOURCE_FILTER_CONFIG_GET) \
+    SW_API_DESC(SW_API_PT_SOURCE_FILTER_CONFIG_SET)  \
+    SW_API_DESC(SW_API_PT_SWITCH_PORT_LOOPBACK_SET)  \
+    SW_API_DESC(SW_API_PT_SWITCH_PORT_LOOPBACK_GET)
+/*qca808x_start*/
+/*end of PORTCONTROL_API_PARAM*/
+/*qca808x_end*/
+#else
+#define PORTCONTROL_API \
+    SW_API_DEF(SW_API_PT_DUPLEX_SET, fal_port_duplex_set), \
+    SW_API_DEF(SW_API_PT_SPEED_SET, fal_port_speed_set), \
+    SW_API_DEF(SW_API_PT_AN_ENABLE, fal_port_autoneg_enable), \
+    SW_API_DEF(SW_API_PT_AN_RESTART, fal_port_autoneg_restart), \
+    SW_API_DEF(SW_API_PT_AN_ADV_SET, fal_port_autoneg_adv_set), \
+    SW_API_DEF(SW_API_PT_LINK_MODE_SET, fal_port_link_forcemode_set),   \
+    SW_API_DEF(SW_API_PT_TXHDR_SET, fal_port_txhdr_mode_set), \
+    SW_API_DEF(SW_API_PT_RXHDR_SET, fal_port_rxhdr_mode_set), \
+    SW_API_DEF(SW_API_HEADER_TYPE_SET, fal_header_type_set),  \
+    SW_API_DEF(SW_API_TXMAC_STATUS_SET, fal_port_txmac_status_set), \
+    SW_API_DEF(SW_API_RXMAC_STATUS_SET, fal_port_rxmac_status_set), \
+    SW_API_DEF(SW_API_PT_POWER_OFF, fal_port_power_off), \
+    SW_API_DEF(SW_API_PT_POWER_ON, fal_port_power_on), \
+    SW_API_DEF(SW_API_TXFC_STATUS_SET, fal_port_txfc_status_set),   \
+    SW_API_DEF(SW_API_RXFC_STATUS_SET, fal_port_rxfc_status_set), \
+    SW_API_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_SET, fal_switch_port_loopback_set),  \
+    SW_API_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_GET, fal_switch_port_loopback_get),
+/*end of PORTCONTROL_API*/
+#define PORTCONTROL_API_PARAM \
+    SW_API_DESC(SW_API_PT_DUPLEX_SET) \
+    SW_API_DESC(SW_API_PT_SPEED_SET)  \
+    SW_API_DESC(SW_API_PT_AN_ENABLE) \
+    SW_API_DESC(SW_API_PT_AN_RESTART) \
+    SW_API_DESC(SW_API_PT_AN_ADV_SET) \
+    SW_API_DESC(SW_API_PT_LINK_MODE_SET) \
+    SW_API_DESC(SW_API_PT_TXHDR_SET) \
+    SW_API_DESC(SW_API_PT_RXHDR_SET) \
+    SW_API_DESC(SW_API_HEADER_TYPE_SET) \
+    SW_API_DESC(SW_API_TXMAC_STATUS_SET) \
+    SW_API_DESC(SW_API_RXMAC_STATUS_SET) \
+    SW_API_DESC(SW_API_PT_POWER_OFF) \
+    SW_API_DESC(SW_API_PT_POWER_ON) \
+    SW_API_DESC(SW_API_TXFC_STATUS_SET) \
+    SW_API_DESC(SW_API_RXFC_STATUS_SET) \
+    SW_API_DESC(SW_API_PT_SWITCH_PORT_LOOPBACK_SET)  \
+    SW_API_DESC(SW_API_PT_SWITCH_PORT_LOOPBACK_GET)
+/*end of PORTCONTROL_API_PARAM*/
+#endif
+
+#else
+#define PORTCONTROL_API
+#define PORTCONTROL_API_PARAM
+#endif
+#ifdef IN_VLAN
+#define VLAN_API \
+    SW_API_DEF(SW_API_VLAN_ADD, fal_vlan_create), \
+    SW_API_DEF(SW_API_VLAN_DEL, fal_vlan_delete), \
+    SW_API_DEF(SW_API_VLAN_MEM_UPDATE, fal_vlan_member_update), \
+    SW_API_DEF(SW_API_VLAN_FIND, fal_vlan_find), \
+    SW_API_DEF(SW_API_VLAN_NEXT, fal_vlan_next), \
+    SW_API_DEF(SW_API_VLAN_APPEND, fal_vlan_entry_append), \
+    SW_API_DEF(SW_API_VLAN_FLUSH, fal_vlan_flush), \
+    SW_API_DEF(SW_API_VLAN_FID_SET, fal_vlan_fid_set), \
+    SW_API_DEF(SW_API_VLAN_FID_GET, fal_vlan_fid_get), \
+    SW_API_DEF(SW_API_VLAN_MEMBER_ADD, fal_vlan_member_add), \
+    SW_API_DEF(SW_API_VLAN_MEMBER_DEL, fal_vlan_member_del), \
+    SW_API_DEF(SW_API_VLAN_LEARN_STATE_SET, fal_vlan_learning_state_set), \
+    SW_API_DEF(SW_API_VLAN_LEARN_STATE_GET, fal_vlan_learning_state_get),
+
+#define VLAN_API_PARAM \
+    SW_API_DESC(SW_API_VLAN_ADD) \
+    SW_API_DESC(SW_API_VLAN_DEL) \
+    SW_API_DESC(SW_API_VLAN_MEM_UPDATE) \
+    SW_API_DESC(SW_API_VLAN_FIND) \
+    SW_API_DESC(SW_API_VLAN_NEXT) \
+    SW_API_DESC(SW_API_VLAN_APPEND) \
+    SW_API_DESC(SW_API_VLAN_FLUSH) \
+    SW_API_DESC(SW_API_VLAN_FID_SET) \
+    SW_API_DESC(SW_API_VLAN_FID_GET) \
+    SW_API_DESC(SW_API_VLAN_MEMBER_ADD) \
+    SW_API_DESC(SW_API_VLAN_MEMBER_DEL) \
+    SW_API_DESC(SW_API_VLAN_LEARN_STATE_SET) \
+    SW_API_DESC(SW_API_VLAN_LEARN_STATE_GET)
+#else
+#define VLAN_API
+#define VLAN_API_PARAM
+#endif
+
+#ifdef IN_PORTVLAN
+#ifndef IN_PORTVLAN_MINI
+#define PORTVLAN_API \
+    SW_API_DEF(SW_API_PT_ING_MODE_GET, fal_port_1qmode_get), \
+    SW_API_DEF(SW_API_PT_ING_MODE_SET, fal_port_1qmode_set), \
+    SW_API_DEF(SW_API_PT_EG_MODE_GET, fal_port_egvlanmode_get), \
+    SW_API_DEF(SW_API_PT_EG_MODE_SET, fal_port_egvlanmode_set), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, fal_portvlan_member_add), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, fal_portvlan_member_del), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, fal_portvlan_member_update), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_GET, fal_portvlan_member_get), \
+    SW_API_DEF(SW_API_PT_DEF_VID_SET, fal_port_default_vid_set), \
+    SW_API_DEF(SW_API_PT_DEF_VID_GET, fal_port_default_vid_get), \
+    SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, fal_port_force_default_vid_set), \
+    SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, fal_port_force_default_vid_get), \
+    SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, fal_port_force_portvlan_set), \
+    SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, fal_port_force_portvlan_get), \
+    SW_API_DEF(SW_API_PT_NESTVLAN_SET, fal_port_nestvlan_set), \
+    SW_API_DEF(SW_API_PT_NESTVLAN_GET, fal_port_nestvlan_get), \
+    SW_API_DEF(SW_API_NESTVLAN_TPID_SET, fal_nestvlan_tpid_set), \
+    SW_API_DEF(SW_API_NESTVLAN_TPID_GET, fal_nestvlan_tpid_get), \
+    SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, fal_port_invlan_mode_set), \
+    SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, fal_port_invlan_mode_get), \
+    SW_API_DEF(SW_API_PT_TLS_SET, fal_port_tls_set), \
+    SW_API_DEF(SW_API_PT_TLS_GET, fal_port_tls_get), \
+    SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, fal_port_pri_propagation_set), \
+    SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, fal_port_pri_propagation_get), \
+    SW_API_DEF(SW_API_PT_DEF_SVID_SET, fal_port_default_svid_set), \
+    SW_API_DEF(SW_API_PT_DEF_SVID_GET, fal_port_default_svid_get), \
+    SW_API_DEF(SW_API_PT_DEF_CVID_SET, fal_port_default_cvid_set), \
+    SW_API_DEF(SW_API_PT_DEF_CVID_GET, fal_port_default_cvid_get), \
+    SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_SET, fal_port_vlan_propagation_set), \
+    SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_GET, fal_port_vlan_propagation_get), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, fal_port_vlan_trans_add), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_DEL, fal_port_vlan_trans_del), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_GET, fal_port_vlan_trans_get), \
+    SW_API_DEF(SW_API_QINQ_MODE_SET, fal_qinq_mode_set), \
+    SW_API_DEF(SW_API_QINQ_MODE_GET, fal_qinq_mode_get), \
+    SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, fal_port_qinq_role_set), \
+    SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, fal_port_qinq_role_get), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ITERATE, fal_port_vlan_trans_iterate), \
+    SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_SET, fal_port_mac_vlan_xlt_set), \
+    SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_GET, fal_port_mac_vlan_xlt_get), \
+    SW_API_DEF(SW_API_NETISOLATE_SET, fal_netisolate_set), \
+    SW_API_DEF(SW_API_NETISOLATE_GET, fal_netisolate_get), \
+    SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_SET, fal_eg_trans_filter_bypass_en_set), \
+    SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_GET, fal_eg_trans_filter_bypass_en_get), \
+    SW_API_DEF(SW_API_PT_VRF_ID_SET, fal_port_vrf_id_set), \
+    SW_API_DEF(SW_API_PT_VRF_ID_GET, fal_port_vrf_id_get), \
+    SW_API_DEF(SW_API_GLOBAL_QINQ_MODE_SET, fal_global_qinq_mode_set), \
+    SW_API_DEF(SW_API_GLOBAL_QINQ_MODE_GET, fal_global_qinq_mode_get), \
+    SW_API_DEF(SW_API_PORT_QINQ_MODE_SET, fal_port_qinq_mode_set), \
+    SW_API_DEF(SW_API_PORT_QINQ_MODE_GET, fal_port_qinq_mode_get), \
+    SW_API_DEF(SW_API_TPID_SET, fal_ingress_tpid_set), \
+    SW_API_DEF(SW_API_TPID_GET, fal_ingress_tpid_get), \
+    SW_API_DEF(SW_API_EGRESS_TPID_SET, fal_egress_tpid_set), \
+    SW_API_DEF(SW_API_EGRESS_TPID_GET, fal_egress_tpid_get), \
+    SW_API_DEF(SW_API_PT_INGRESS_VLAN_FILTER_SET, fal_port_ingress_vlan_filter_set), \
+    SW_API_DEF(SW_API_PT_INGRESS_VLAN_FILTER_GET, fal_port_ingress_vlan_filter_get), \
+    SW_API_DEF(SW_API_PT_DEFAULT_VLANTAG_SET, fal_port_default_vlantag_set), \
+    SW_API_DEF(SW_API_PT_DEFAULT_VLANTAG_GET, fal_port_default_vlantag_get), \
+    SW_API_DEF(SW_API_PT_TAG_PROPAGATION_SET, fal_port_tag_propagation_set), \
+    SW_API_DEF(SW_API_PT_TAG_PROPAGATION_GET, fal_port_tag_propagation_get), \
+    SW_API_DEF(SW_API_PT_VLANTAG_EGMODE_SET, fal_port_vlantag_egmode_set), \
+    SW_API_DEF(SW_API_PT_VLANTAG_EGMODE_GET, fal_port_vlantag_egmode_get), \
+    SW_API_DEF(SW_API_PT_VLAN_XLT_MISS_CMD_SET, fal_port_vlan_xlt_miss_cmd_set), \
+    SW_API_DEF(SW_API_PT_VLAN_XLT_MISS_CMD_GET, fal_port_vlan_xlt_miss_cmd_get), \
+    SW_API_DEF(SW_API_PT_VSI_EGMODE_SET, fal_port_vsi_egmode_set), \
+    SW_API_DEF(SW_API_PT_VSI_EGMODE_GET, fal_port_vsi_egmode_get), \
+    SW_API_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET, fal_port_vlantag_vsi_egmode_enable), \
+    SW_API_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET, fal_port_vlantag_vsi_egmode_status_get), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_ADD, fal_port_vlan_trans_adv_add), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_DEL, fal_port_vlan_trans_adv_del), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_GETFIRST, fal_port_vlan_trans_adv_getfirst), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_GETNEXT, fal_port_vlan_trans_adv_getnext), \
+    SW_API_DEF(SW_API_PT_VLAN_COUNTER_GET, fal_port_vlan_counter_get), \
+    SW_API_DEF(SW_API_PT_VLAN_COUNTER_CLEANUP, fal_port_vlan_counter_cleanup),
+
+#define PORTVLAN_API_PARAM \
+    SW_API_DESC(SW_API_PT_ING_MODE_GET) \
+    SW_API_DESC(SW_API_PT_ING_MODE_SET) \
+    SW_API_DESC(SW_API_PT_EG_MODE_GET) \
+    SW_API_DESC(SW_API_PT_EG_MODE_SET) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_GET)    \
+    SW_API_DESC(SW_API_PT_DEF_VID_SET)    \
+    SW_API_DESC(SW_API_PT_DEF_VID_GET)    \
+    SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET)    \
+    SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET)    \
+    SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET)    \
+    SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET)    \
+    SW_API_DESC(SW_API_PT_NESTVLAN_SET)    \
+    SW_API_DESC(SW_API_PT_NESTVLAN_GET)    \
+    SW_API_DESC(SW_API_NESTVLAN_TPID_SET)    \
+    SW_API_DESC(SW_API_NESTVLAN_TPID_GET)    \
+    SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET)   \
+    SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET)   \
+    SW_API_DESC(SW_API_PT_TLS_SET)   \
+    SW_API_DESC(SW_API_PT_TLS_GET)   \
+    SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET)    \
+    SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET)   \
+    SW_API_DESC(SW_API_PT_DEF_SVID_SET)    \
+    SW_API_DESC(SW_API_PT_DEF_SVID_GET)    \
+    SW_API_DESC(SW_API_PT_DEF_CVID_SET)    \
+    SW_API_DESC(SW_API_PT_DEF_CVID_GET)    \
+    SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_SET)   \
+    SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_GET)   \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD) \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_DEL) \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_GET) \
+    SW_API_DESC(SW_API_QINQ_MODE_SET)    \
+    SW_API_DESC(SW_API_QINQ_MODE_GET)    \
+    SW_API_DESC(SW_API_PT_QINQ_ROLE_SET) \
+    SW_API_DESC(SW_API_PT_QINQ_ROLE_GET) \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ITERATE) \
+    SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_SET)   \
+    SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_GET)  \
+    SW_API_DESC(SW_API_NETISOLATE_SET)   \
+    SW_API_DESC(SW_API_NETISOLATE_GET)   \
+    SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_SET)   \
+    SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_GET)   \
+    SW_API_DESC(SW_API_PT_VRF_ID_SET)  \
+    SW_API_DESC(SW_API_PT_VRF_ID_GET) \
+    SW_API_DESC(SW_API_GLOBAL_QINQ_MODE_SET)  \
+    SW_API_DESC(SW_API_GLOBAL_QINQ_MODE_GET) \
+    SW_API_DESC(SW_API_PORT_QINQ_MODE_SET)  \
+    SW_API_DESC(SW_API_PORT_QINQ_MODE_GET) \
+    SW_API_DESC(SW_API_TPID_SET)  \
+    SW_API_DESC(SW_API_TPID_GET) \
+    SW_API_DESC(SW_API_EGRESS_TPID_SET)  \
+    SW_API_DESC(SW_API_EGRESS_TPID_GET) \
+    SW_API_DESC(SW_API_PT_INGRESS_VLAN_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_INGRESS_VLAN_FILTER_GET) \
+    SW_API_DESC(SW_API_PT_DEFAULT_VLANTAG_SET)  \
+    SW_API_DESC(SW_API_PT_DEFAULT_VLANTAG_GET) \
+    SW_API_DESC(SW_API_PT_TAG_PROPAGATION_SET)  \
+    SW_API_DESC(SW_API_PT_TAG_PROPAGATION_GET) \
+    SW_API_DESC(SW_API_PT_VLANTAG_EGMODE_SET)  \
+    SW_API_DESC(SW_API_PT_VLANTAG_EGMODE_GET) \
+    SW_API_DESC(SW_API_PT_VLAN_XLT_MISS_CMD_SET)  \
+    SW_API_DESC(SW_API_PT_VLAN_XLT_MISS_CMD_GET) \
+    SW_API_DESC(SW_API_PT_VSI_EGMODE_SET) \
+    SW_API_DESC(SW_API_PT_VSI_EGMODE_GET) \
+    SW_API_DESC(SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET) \
+    SW_API_DESC(SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET) \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_ADD) \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_DEL) \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_GETFIRST) \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_GETNEXT) \
+    SW_API_DESC(SW_API_PT_VLAN_COUNTER_GET) \
+    SW_API_DESC(SW_API_PT_VLAN_COUNTER_CLEANUP)
+
+#else
+#define PORTVLAN_API \
+    SW_API_DEF(SW_API_GLOBAL_QINQ_MODE_SET, fal_global_qinq_mode_set), \
+    SW_API_DEF(SW_API_GLOBAL_QINQ_MODE_GET, fal_global_qinq_mode_get), \
+    SW_API_DEF(SW_API_PORT_QINQ_MODE_SET, fal_port_qinq_mode_set), \
+    SW_API_DEF(SW_API_PORT_QINQ_MODE_GET, fal_port_qinq_mode_get), \
+    SW_API_DEF(SW_API_QINQ_MODE_SET, fal_qinq_mode_set), \
+    SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, fal_port_qinq_role_set), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, fal_port_vlan_trans_add), \
+    SW_API_DEF(SW_API_TPID_SET, fal_ingress_tpid_set), \
+    SW_API_DEF(SW_API_TPID_GET, fal_ingress_tpid_get), \
+    SW_API_DEF(SW_API_EGRESS_TPID_SET, fal_egress_tpid_set), \
+    SW_API_DEF(SW_API_EGRESS_TPID_GET, fal_egress_tpid_get), \
+    SW_API_DEF(SW_API_PT_INGRESS_VLAN_FILTER_SET, fal_port_ingress_vlan_filter_set), \
+    SW_API_DEF(SW_API_PT_INGRESS_VLAN_FILTER_GET, fal_port_ingress_vlan_filter_get), \
+    SW_API_DEF(SW_API_PT_DEFAULT_VLANTAG_SET, fal_port_default_vlantag_set), \
+    SW_API_DEF(SW_API_PT_DEFAULT_VLANTAG_GET, fal_port_default_vlantag_get), \
+    SW_API_DEF(SW_API_PT_TAG_PROPAGATION_SET, fal_port_tag_propagation_set), \
+    SW_API_DEF(SW_API_PT_TAG_PROPAGATION_GET, fal_port_tag_propagation_get), \
+    SW_API_DEF(SW_API_PT_VLANTAG_EGMODE_SET, fal_port_vlantag_egmode_set), \
+    SW_API_DEF(SW_API_PT_VLANTAG_EGMODE_GET, fal_port_vlantag_egmode_get), \
+    SW_API_DEF(SW_API_PT_VLAN_XLT_MISS_CMD_SET, fal_port_vlan_xlt_miss_cmd_set), \
+    SW_API_DEF(SW_API_PT_VLAN_XLT_MISS_CMD_GET, fal_port_vlan_xlt_miss_cmd_get), \
+    SW_API_DEF(SW_API_PT_VSI_EGMODE_SET, fal_port_vsi_egmode_set), \
+    SW_API_DEF(SW_API_PT_VSI_EGMODE_GET, fal_port_vsi_egmode_get), \
+    SW_API_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET, fal_port_vlantag_vsi_egmode_enable), \
+    SW_API_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET, fal_port_vlantag_vsi_egmode_status_get), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_ADD, fal_port_vlan_trans_adv_add), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_DEL, fal_port_vlan_trans_adv_del), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_GETFIRST, fal_port_vlan_trans_adv_getfirst), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_GETNEXT, fal_port_vlan_trans_adv_getnext), \
+    SW_API_DEF(SW_API_PT_VLAN_COUNTER_GET, fal_port_vlan_counter_get), \
+    SW_API_DEF(SW_API_PT_VLAN_COUNTER_CLEANUP, fal_port_vlan_counter_cleanup), \
+    SW_API_DEF(SW_API_PT_ING_MODE_SET, fal_port_1qmode_set), \
+    SW_API_DEF(SW_API_PT_EG_MODE_SET, fal_port_egvlanmode_set), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, fal_portvlan_member_add), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, fal_portvlan_member_del), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, fal_portvlan_member_update), \
+    SW_API_DEF(SW_API_PT_DEF_VID_SET, fal_port_default_vid_set), \
+    SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, fal_port_force_default_vid_set), \
+    SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, fal_port_force_portvlan_set), \
+    SW_API_DEF(SW_API_PT_NESTVLAN_SET, fal_port_nestvlan_set), \
+    SW_API_DEF(SW_API_NESTVLAN_TPID_SET, fal_nestvlan_tpid_set), \
+    SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, fal_port_invlan_mode_set), \
+    SW_API_DEF(SW_API_PT_DEF_SVID_SET, fal_port_default_svid_set), \
+    SW_API_DEF(SW_API_PT_DEF_CVID_SET, fal_port_default_cvid_set),
+
+#define PORTVLAN_API_PARAM \
+    SW_API_DESC(SW_API_GLOBAL_QINQ_MODE_SET)  \
+    SW_API_DESC(SW_API_GLOBAL_QINQ_MODE_GET) \
+    SW_API_DESC(SW_API_PORT_QINQ_MODE_SET)  \
+    SW_API_DESC(SW_API_PORT_QINQ_MODE_GET) \
+    SW_API_DESC(SW_API_QINQ_MODE_SET)    \
+    SW_API_DESC(SW_API_PT_QINQ_ROLE_SET) \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD) \
+    SW_API_DESC(SW_API_TPID_SET)  \
+    SW_API_DESC(SW_API_TPID_GET) \
+    SW_API_DESC(SW_API_EGRESS_TPID_SET)  \
+    SW_API_DESC(SW_API_EGRESS_TPID_GET) \
+    SW_API_DESC(SW_API_PT_INGRESS_VLAN_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_INGRESS_VLAN_FILTER_GET) \
+    SW_API_DESC(SW_API_PT_DEFAULT_VLANTAG_SET)  \
+    SW_API_DESC(SW_API_PT_DEFAULT_VLANTAG_GET) \
+    SW_API_DESC(SW_API_PT_TAG_PROPAGATION_SET)  \
+    SW_API_DESC(SW_API_PT_TAG_PROPAGATION_GET) \
+    SW_API_DESC(SW_API_PT_VLANTAG_EGMODE_SET)  \
+    SW_API_DESC(SW_API_PT_VLANTAG_EGMODE_GET) \
+    SW_API_DESC(SW_API_PT_VLAN_XLT_MISS_CMD_SET)  \
+    SW_API_DESC(SW_API_PT_VLAN_XLT_MISS_CMD_GET) \
+    SW_API_DESC(SW_API_PT_VSI_EGMODE_SET) \
+    SW_API_DESC(SW_API_PT_VSI_EGMODE_GET) \
+    SW_API_DESC(SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET) \
+    SW_API_DESC(SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET) \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_ADD) \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_DEL) \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_GETFIRST) \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_GETNEXT) \
+    SW_API_DESC(SW_API_PT_VLAN_COUNTER_GET) \
+    SW_API_DESC(SW_API_PT_VLAN_COUNTER_CLEANUP) \
+    SW_API_DESC(SW_API_PT_ING_MODE_SET) \
+    SW_API_DESC(SW_API_PT_EG_MODE_SET) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \
+    SW_API_DESC(SW_API_PT_DEF_VID_SET)    \
+    SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET)    \
+    SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET)    \
+    SW_API_DESC(SW_API_PT_NESTVLAN_SET)    \
+    SW_API_DESC(SW_API_NESTVLAN_TPID_SET)    \
+    SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET)   \
+    SW_API_DESC(SW_API_PT_DEF_SVID_SET)    \
+    SW_API_DESC(SW_API_PT_DEF_CVID_SET)
+
+#endif
+
+#else
+#define PORTVLAN_API
+#define PORTVLAN_API_PARAM
+#endif
+
+#ifdef IN_FDB
+#ifndef IN_FDB_MINI
+#define FDB_API \
+    SW_API_DEF(SW_API_FDB_ADD, fal_fdb_entry_add), \
+    SW_API_DEF(SW_API_FDB_DELALL, fal_fdb_entry_flush), \
+    SW_API_DEF(SW_API_FDB_DELPORT,fal_fdb_entry_del_byport), \
+    SW_API_DEF(SW_API_FDB_DELMAC, fal_fdb_entry_del_bymac), \
+    SW_API_DEF(SW_API_FDB_FIRST,  fal_fdb_entry_getfirst), \
+    SW_API_DEF(SW_API_FDB_NEXT,   fal_fdb_entry_getnext), \
+    SW_API_DEF(SW_API_FDB_FIND,   fal_fdb_entry_search), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_SET,   fal_fdb_port_learn_set), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_GET,   fal_fdb_port_learn_get), \
+    SW_API_DEF(SW_API_FDB_PT_NEWADDR_LEARN_SET, fal_fdb_port_learning_ctrl_set), \
+    SW_API_DEF(SW_API_FDB_PT_NEWADDR_LEARN_GET, fal_fdb_port_learning_ctrl_get), \
+    SW_API_DEF(SW_API_FDB_PT_STAMOVE_SET,       fal_fdb_port_stamove_ctrl_set), \
+    SW_API_DEF(SW_API_FDB_PT_STAMOVE_GET,       fal_fdb_port_stamove_ctrl_get), \
+    SW_API_DEF(SW_API_FDB_AGE_CTRL_SET,   fal_fdb_aging_ctrl_set), \
+    SW_API_DEF(SW_API_FDB_AGE_CTRL_GET,   fal_fdb_aging_ctrl_get), \
+    SW_API_DEF(SW_API_FDB_LEARN_CTRL_SET,  fal_fdb_learning_ctrl_set), \
+    SW_API_DEF(SW_API_FDB_LEARN_CTRL_GET,  fal_fdb_learning_ctrl_get), \
+    SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_SET, fal_fdb_vlan_ivl_svl_set),\
+    SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_GET, fal_fdb_vlan_ivl_svl_get),\
+    SW_API_DEF(SW_API_FDB_AGE_TIME_SET,   fal_fdb_aging_time_set), \
+    SW_API_DEF(SW_API_FDB_AGE_TIME_GET,   fal_fdb_aging_time_get), \
+    SW_API_DEF(SW_API_FDB_ITERATE,        fal_fdb_entry_getnext_byindex), \
+    SW_API_DEF(SW_API_FDB_EXTEND_NEXT,    fal_fdb_entry_extend_getnext),  \
+    SW_API_DEF(SW_API_FDB_EXTEND_FIRST,   fal_fdb_entry_extend_getfirst), \
+    SW_API_DEF(SW_API_FDB_TRANSFER,       fal_fdb_entry_update_byport), \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_COUNTER_GET,  fal_fdb_port_learned_mac_counter_get), \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET,    fal_port_fdb_learn_limit_set),  \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET,    fal_port_fdb_learn_limit_get),  \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET,    fal_port_fdb_learn_exceed_cmd_set),  \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET,    fal_port_fdb_learn_exceed_cmd_get), \
+    SW_API_DEF(SW_API_FDB_LEARN_LIMIT_SET,    fal_fdb_learn_limit_set),  \
+    SW_API_DEF(SW_API_FDB_LEARN_LIMIT_GET,    fal_fdb_learn_limit_get),  \
+    SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET,    fal_fdb_learn_exceed_cmd_set),  \
+    SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET,    fal_fdb_learn_exceed_cmd_get),  \
+    SW_API_DEF(SW_API_FDB_RESV_ADD, fal_fdb_resv_add), \
+    SW_API_DEF(SW_API_FDB_RESV_DEL, fal_fdb_resv_del), \
+    SW_API_DEF(SW_API_FDB_RESV_FIND, fal_fdb_resv_find), \
+    SW_API_DEF(SW_API_FDB_RESV_ITERATE, fal_fdb_resv_iterate), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_SET,   fal_fdb_port_learn_static_set), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_GET,   fal_fdb_port_learn_static_get), \
+    SW_API_DEF(SW_API_FDB_PORT_ADD,   fal_fdb_port_add), \
+    SW_API_DEF(SW_API_FDB_PORT_DEL,   fal_fdb_port_del), \
+    SW_API_DEF(SW_API_FDB_RFS_SET,   fal_fdb_rfs_set),   \
+    SW_API_DEF(SW_API_FDB_RFS_DEL,   fal_fdb_rfs_del),   \
+    SW_API_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_SET, fal_fdb_port_maclimit_ctrl_set), \
+    SW_API_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_GET, fal_fdb_port_maclimit_ctrl_get), \
+    SW_API_DEF(SW_API_FDB_DEL_BY_FID, fal_fdb_entry_del_byfid),
+
+#define FDB_API_PARAM \
+    SW_API_DESC(SW_API_FDB_ADD) \
+    SW_API_DESC(SW_API_FDB_DELALL) \
+    SW_API_DESC(SW_API_FDB_DELPORT) \
+    SW_API_DESC(SW_API_FDB_DELMAC) \
+    SW_API_DESC(SW_API_FDB_FIRST) \
+    SW_API_DESC(SW_API_FDB_NEXT) \
+    SW_API_DESC(SW_API_FDB_FIND) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \
+    SW_API_DESC(SW_API_FDB_PT_NEWADDR_LEARN_SET) \
+    SW_API_DESC(SW_API_FDB_PT_NEWADDR_LEARN_GET) \
+    SW_API_DESC(SW_API_FDB_PT_STAMOVE_SET) \
+    SW_API_DESC(SW_API_FDB_PT_STAMOVE_GET) \
+    SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \
+    SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \
+    SW_API_DESC(SW_API_FDB_LEARN_CTRL_SET) \
+    SW_API_DESC(SW_API_FDB_LEARN_CTRL_GET) \
+    SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_SET) \
+    SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_GET) \
+    SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \
+    SW_API_DESC(SW_API_FDB_AGE_TIME_GET) \
+    SW_API_DESC(SW_API_FDB_ITERATE) \
+    SW_API_DESC(SW_API_FDB_EXTEND_NEXT)  \
+    SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \
+    SW_API_DESC(SW_API_FDB_TRANSFER) \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_COUNTER_GET) \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_SET)  \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_GET)  \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET)  \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_LIMIT_SET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_LIMIT_GET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_SET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_GET)  \
+    SW_API_DESC(SW_API_FDB_RESV_ADD)  \
+    SW_API_DESC(SW_API_FDB_RESV_DEL)  \
+    SW_API_DESC(SW_API_FDB_RESV_FIND) \
+    SW_API_DESC(SW_API_FDB_RESV_ITERATE) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_SET) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_GET) \
+    SW_API_DESC(SW_API_FDB_PORT_ADD)  \
+    SW_API_DESC(SW_API_FDB_PORT_DEL)  \
+    SW_API_DESC(SW_API_FDB_RFS_SET)   \
+    SW_API_DESC(SW_API_FDB_RFS_DEL)   \
+    SW_API_DESC(SW_API_FDB_PT_MACLIMIT_CTRL_SET) \
+    SW_API_DESC(SW_API_FDB_PT_MACLIMIT_CTRL_GET) \
+    SW_API_DESC(SW_API_FDB_DEL_BY_FID)
+#else
+#define FDB_API \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_SET,   fal_fdb_port_learn_set), \
+    SW_API_DEF(SW_API_FDB_EXTEND_FIRST,   fal_fdb_entry_extend_getfirst), \
+    SW_API_DEF(SW_API_FDB_EXTEND_NEXT,    fal_fdb_entry_extend_getnext),
+
+#define FDB_API_PARAM \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \
+    SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \
+    SW_API_DESC(SW_API_FDB_EXTEND_NEXT)
+#endif
+#else
+#define FDB_API
+#define FDB_API_PARAM
+#endif
+
+#ifdef IN_ACL
+#define ACL_API \
+    SW_API_DEF(SW_API_ACL_LIST_CREAT, fal_acl_list_creat), \
+    SW_API_DEF(SW_API_ACL_LIST_DESTROY, fal_acl_list_destroy), \
+    SW_API_DEF(SW_API_ACL_RULE_ADD, fal_acl_rule_add), \
+    SW_API_DEF(SW_API_ACL_RULE_DELETE, fal_acl_rule_delete), \
+    SW_API_DEF(SW_API_ACL_RULE_QUERY, fal_acl_rule_query), \
+    SW_API_DEF(SW_API_ACL_LIST_BIND, fal_acl_list_bind), \
+    SW_API_DEF(SW_API_ACL_LIST_UNBIND, fal_acl_list_unbind), \
+    SW_API_DEF(SW_API_ACL_STATUS_SET, fal_acl_status_set), \
+    SW_API_DEF(SW_API_ACL_STATUS_GET, fal_acl_status_get), \
+    SW_API_DEF(SW_API_ACL_LIST_DUMP, fal_acl_list_dump), \
+    SW_API_DEF(SW_API_ACL_RULE_DUMP, fal_acl_rule_dump), \
+    SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, fal_acl_port_udf_profile_set), \
+    SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, fal_acl_port_udf_profile_get), \
+    SW_API_DEF(SW_API_ACL_RULE_ACTIVE, fal_acl_rule_active), \
+    SW_API_DEF(SW_API_ACL_RULE_DEACTIVE, fal_acl_rule_deactive),\
+    SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, fal_acl_rule_src_filter_sts_set),\
+    SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, fal_acl_rule_src_filter_sts_get),\
+    SW_API_DEF(SW_API_ACL_UDF_SET, fal_acl_udf_profile_set),\
+    SW_API_DEF(SW_API_ACL_UDF_GET, fal_acl_udf_profile_get),
+
+#define ACL_API_PARAM \
+    SW_API_DESC(SW_API_ACL_LIST_CREAT) \
+    SW_API_DESC(SW_API_ACL_LIST_DESTROY) \
+    SW_API_DESC(SW_API_ACL_RULE_ADD) \
+    SW_API_DESC(SW_API_ACL_RULE_DELETE) \
+    SW_API_DESC(SW_API_ACL_RULE_QUERY) \
+    SW_API_DESC(SW_API_ACL_LIST_BIND) \
+    SW_API_DESC(SW_API_ACL_LIST_UNBIND) \
+    SW_API_DESC(SW_API_ACL_STATUS_SET) \
+    SW_API_DESC(SW_API_ACL_STATUS_GET) \
+    SW_API_DESC(SW_API_ACL_LIST_DUMP) \
+    SW_API_DESC(SW_API_ACL_RULE_DUMP) \
+    SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_SET)    \
+    SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_GET)    \
+    SW_API_DESC(SW_API_ACL_RULE_ACTIVE)    \
+    SW_API_DESC(SW_API_ACL_RULE_DEACTIVE) \
+    SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_SET)\
+    SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_GET)\
+    SW_API_DESC(SW_API_ACL_UDF_SET)    \
+    SW_API_DESC(SW_API_ACL_UDF_GET)
+#else
+#define ACL_API
+#define ACL_API_PARAM
+#endif
+
+#ifdef IN_QOS
+#ifndef IN_QOS_MINI
+#define QOS_API \
+    SW_API_DEF(SW_API_QOS_SCH_MODE_SET, fal_qos_sch_mode_set), \
+    SW_API_DEF(SW_API_QOS_SCH_MODE_GET, fal_qos_sch_mode_get), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, fal_qos_queue_tx_buf_status_set), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, fal_qos_queue_tx_buf_status_get), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, fal_qos_queue_tx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, fal_qos_queue_tx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, fal_qos_port_tx_buf_status_set), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, fal_qos_port_tx_buf_status_get), \
+    SW_API_DEF(SW_API_QOS_PT_RED_EN_SET, fal_qos_port_red_en_set), \
+    SW_API_DEF(SW_API_QOS_PT_RED_EN_GET, fal_qos_port_red_en_get), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, fal_qos_port_tx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, fal_qos_port_tx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, fal_qos_port_rx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, fal_qos_port_rx_buf_nr_get), \
+    SW_API_DEF(SW_API_COSMAP_UP_QU_SET, fal_cosmap_up_queue_set), \
+    SW_API_DEF(SW_API_COSMAP_UP_QU_GET, fal_cosmap_up_queue_get), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_QU_SET, fal_cosmap_dscp_queue_set), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_QU_GET, fal_cosmap_dscp_queue_get), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_SET, fal_qos_port_mode_set), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_GET, fal_qos_port_mode_get), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, fal_qos_port_mode_pri_set), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, fal_qos_port_mode_pri_get), \
+    SW_API_DEF(SW_API_QOS_PORT_DEF_UP_SET, fal_qos_port_default_up_set), \
+    SW_API_DEF(SW_API_QOS_PORT_DEF_UP_GET, fal_qos_port_default_up_get), \
+    SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, fal_qos_port_sch_mode_set), \
+    SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, fal_qos_port_sch_mode_get), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_SET, fal_qos_port_default_spri_set), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_GET, fal_qos_port_default_spri_get), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_SET, fal_qos_port_default_cpri_set), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_GET, fal_qos_port_default_cpri_get), \
+    SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, fal_qos_port_force_spri_status_set), \
+    SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, fal_qos_port_force_spri_status_get), \
+    SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, fal_qos_port_force_cpri_status_set), \
+    SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, fal_qos_port_force_cpri_status_get), \
+    SW_API_DEF(SW_API_QOS_QUEUE_REMARK_SET, fal_qos_queue_remark_table_set), \
+    SW_API_DEF(SW_API_QOS_QUEUE_REMARK_GET, fal_qos_queue_remark_table_get), \
+    SW_API_DEF(SW_API_QOS_PORT_GROUP_GET, fal_qos_port_group_get), \
+    SW_API_DEF(SW_API_QOS_PORT_GROUP_SET, fal_qos_port_group_set), \
+    SW_API_DEF(SW_API_QOS_PORT_PRI_GET, fal_qos_port_pri_precedence_get), \
+    SW_API_DEF(SW_API_QOS_PORT_PRI_SET, fal_qos_port_pri_precedence_set), \
+    SW_API_DEF(SW_API_QOS_PORT_REMARK_GET, fal_qos_port_remark_get), \
+    SW_API_DEF(SW_API_QOS_PORT_REMARK_SET, fal_qos_port_remark_set), \
+    SW_API_DEF(SW_API_QOS_PCP_MAP_GET, fal_qos_cosmap_pcp_get), \
+    SW_API_DEF(SW_API_QOS_PCP_MAP_SET, fal_qos_cosmap_pcp_set), \
+    SW_API_DEF(SW_API_QOS_FLOW_MAP_GET, fal_qos_cosmap_flow_get), \
+    SW_API_DEF(SW_API_QOS_FLOW_MAP_SET, fal_qos_cosmap_flow_set), \
+    SW_API_DEF(SW_API_QOS_DSCP_MAP_GET, fal_qos_cosmap_dscp_get), \
+    SW_API_DEF(SW_API_QOS_DSCP_MAP_SET, fal_qos_cosmap_dscp_set), \
+    SW_API_DEF(SW_API_QOS_QUEUE_SCHEDULER_GET, fal_queue_scheduler_get), \
+    SW_API_DEF(SW_API_QOS_QUEUE_SCHEDULER_SET, fal_queue_scheduler_set), \
+    SW_API_DEF(SW_API_QOS_RING_QUEUE_MAP_GET, fal_edma_ring_queue_map_get), \
+    SW_API_DEF(SW_API_QOS_RING_QUEUE_MAP_SET, fal_edma_ring_queue_map_set), \
+    SW_API_DEF(SW_API_QOS_PORT_QUEUES_GET, fal_port_queues_get), \
+    SW_API_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_GET, fal_scheduler_dequeue_ctrl_get), \
+    SW_API_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET, fal_scheduler_dequeue_ctrl_set), \
+    SW_API_DEF(SW_API_QOS_PORT_SCHEDULER_CFG_RESET, fal_port_scheduler_cfg_reset), \
+    SW_API_DEF(SW_API_QOS_PORT_SCHEDULER_RESOURCE_GET, fal_port_scheduler_resource_get),
+
+#define QOS_API_PARAM \
+    SW_API_DESC(SW_API_QOS_SCH_MODE_SET) \
+    SW_API_DESC(SW_API_QOS_SCH_MODE_GET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \
+    SW_API_DESC(SW_API_QOS_PT_RED_EN_SET)\
+    SW_API_DESC(SW_API_QOS_PT_RED_EN_GET)\
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_COSMAP_UP_QU_SET) \
+    SW_API_DESC(SW_API_COSMAP_UP_QU_GET) \
+    SW_API_DESC(SW_API_COSMAP_DSCP_QU_SET) \
+    SW_API_DESC(SW_API_COSMAP_DSCP_QU_GET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_SET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_GET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET) \
+    SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_SET)  \
+    SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_GET)  \
+    SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_SET)  \
+    SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_GET)  \
+    SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_SET)  \
+    SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_GET)  \
+    SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_SET)  \
+    SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_GET)  \
+    SW_API_DESC(SW_API_QOS_QUEUE_REMARK_SET) \
+    SW_API_DESC(SW_API_QOS_QUEUE_REMARK_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_GROUP_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_GROUP_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_PRI_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_PRI_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_REMARK_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_REMARK_SET) \
+    SW_API_DESC(SW_API_QOS_PCP_MAP_GET) \
+    SW_API_DESC(SW_API_QOS_PCP_MAP_SET) \
+    SW_API_DESC(SW_API_QOS_FLOW_MAP_GET) \
+    SW_API_DESC(SW_API_QOS_FLOW_MAP_SET) \
+    SW_API_DESC(SW_API_QOS_DSCP_MAP_GET) \
+    SW_API_DESC(SW_API_QOS_DSCP_MAP_SET) \
+    SW_API_DESC(SW_API_QOS_QUEUE_SCHEDULER_GET) \
+    SW_API_DESC(SW_API_QOS_QUEUE_SCHEDULER_SET) \
+    SW_API_DESC(SW_API_QOS_RING_QUEUE_MAP_GET) \
+    SW_API_DESC(SW_API_QOS_RING_QUEUE_MAP_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_QUEUES_GET) \
+    SW_API_DESC(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_GET) \
+    SW_API_DESC(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_SCHEDULER_CFG_RESET) \
+    SW_API_DESC(SW_API_QOS_PORT_SCHEDULER_RESOURCE_GET)
+#else
+#define QOS_API \
+    SW_API_DEF(SW_API_QOS_PT_MODE_SET, fal_qos_port_mode_set),
+
+
+#define QOS_API_PARAM \
+    SW_API_DESC(SW_API_QOS_PT_MODE_SET)
+
+#endif
+#else
+#define QOS_API
+#define QOS_API_PARAM
+#endif
+
+#ifdef IN_IGMP
+#define IGMP_API \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, fal_port_igmps_status_set), \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, fal_port_igmps_status_get), \
+    SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, fal_igmp_mld_cmd_set), \
+    SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, fal_igmp_mld_cmd_get), \
+    SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, fal_port_igmp_mld_join_set), \
+    SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, fal_port_igmp_mld_join_get), \
+    SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, fal_port_igmp_mld_leave_set), \
+    SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, fal_port_igmp_mld_leave_get), \
+    SW_API_DEF(SW_API_IGMP_RP_SET, fal_igmp_mld_rp_set), \
+    SW_API_DEF(SW_API_IGMP_RP_GET, fal_igmp_mld_rp_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, fal_igmp_mld_entry_creat_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, fal_igmp_mld_entry_creat_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, fal_igmp_mld_entry_static_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, fal_igmp_mld_entry_static_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, fal_igmp_mld_entry_leaky_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, fal_igmp_mld_entry_leaky_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, fal_igmp_mld_entry_v3_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, fal_igmp_mld_entry_v3_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, fal_igmp_mld_entry_queue_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, fal_igmp_mld_entry_queue_get), \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET,    fal_port_igmp_mld_learn_limit_set),  \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET,    fal_port_igmp_mld_learn_limit_get),  \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET,    fal_port_igmp_mld_learn_exceed_cmd_set),  \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET,    fal_port_igmp_mld_learn_exceed_cmd_get), \
+    SW_API_DEF(SW_API_IGMP_SG_ENTRY_SET,    fal_igmp_sg_entry_set),  \
+    SW_API_DEF(SW_API_IGMP_SG_ENTRY_CLEAR,    fal_igmp_sg_entry_clear),  \
+    SW_API_DEF(SW_API_IGMP_SG_ENTRY_SHOW,    fal_igmp_sg_entry_show),  \
+    SW_API_DEF(SW_API_IGMP_SG_ENTRY_QUERY,    fal_igmp_sg_entry_query),
+
+#define IGMP_API_PARAM \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
+    SW_API_DESC(SW_API_IGMP_MLD_CMD_SET)  \
+    SW_API_DESC(SW_API_IGMP_MLD_CMD_GET)  \
+    SW_API_DESC(SW_API_IGMP_PT_JOIN_SET)  \
+    SW_API_DESC(SW_API_IGMP_PT_JOIN_GET)  \
+    SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \
+    SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \
+    SW_API_DESC(SW_API_IGMP_RP_SET) \
+    SW_API_DESC(SW_API_IGMP_RP_GET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_SET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_GET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET) \
+    SW_API_DESC(SW_API_IGMP_SG_ENTRY_SET) \
+    SW_API_DESC(SW_API_IGMP_SG_ENTRY_CLEAR) \
+    SW_API_DESC(SW_API_IGMP_SG_ENTRY_SHOW) \
+    SW_API_DESC(SW_API_IGMP_SG_ENTRY_QUERY)
+#else
+#define IGMP_API
+#define IGMP_API_PARAM
+#endif
+
+#ifdef IN_LEAKY
+#define LEAKY_API \
+    SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, fal_uc_leaky_mode_set), \
+    SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, fal_uc_leaky_mode_get), \
+    SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, fal_mc_leaky_mode_set), \
+    SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, fal_mc_leaky_mode_get), \
+    SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, fal_port_arp_leaky_set), \
+    SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, fal_port_arp_leaky_get), \
+    SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, fal_port_uc_leaky_set), \
+    SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, fal_port_uc_leaky_get), \
+    SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, fal_port_mc_leaky_set), \
+    SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, fal_port_mc_leaky_get),
+
+#define LEAKY_API_PARAM \
+    SW_API_DESC(SW_API_UC_LEAKY_MODE_SET) \
+    SW_API_DESC(SW_API_UC_LEAKY_MODE_GET) \
+    SW_API_DESC(SW_API_MC_LEAKY_MODE_SET) \
+    SW_API_DESC(SW_API_MC_LEAKY_MODE_GET) \
+    SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET)\
+    SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \
+    SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET) \
+    SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET) \
+    SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET) \
+    SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET)
+#else
+#define LEAKY_API
+#define LEAKY_API_PARAM
+#endif
+
+#ifdef IN_MIRROR
+#define MIRROR_API \
+    SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, fal_mirr_analysis_port_set), \
+    SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, fal_mirr_analysis_port_get), \
+    SW_API_DEF(SW_API_MIRROR_IN_PT_SET, fal_mirr_port_in_set), \
+    SW_API_DEF(SW_API_MIRROR_IN_PT_GET, fal_mirr_port_in_get), \
+    SW_API_DEF(SW_API_MIRROR_EG_PT_SET, fal_mirr_port_eg_set), \
+    SW_API_DEF(SW_API_MIRROR_EG_PT_GET, fal_mirr_port_eg_get), \
+    SW_API_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_SET, fal_mirr_analysis_config_set), \
+    SW_API_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_GET, fal_mirr_analysis_config_get),
+
+#define MIRROR_API_PARAM \
+    SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET) \
+    SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET) \
+    SW_API_DESC(SW_API_MIRROR_IN_PT_SET) \
+    SW_API_DESC(SW_API_MIRROR_IN_PT_GET) \
+    SW_API_DESC(SW_API_MIRROR_EG_PT_SET) \
+    SW_API_DESC(SW_API_MIRROR_EG_PT_GET) \
+    SW_API_DESC(SW_API_MIRROR_ANALYSIS_CONFIG_SET) \
+    SW_API_DESC(SW_API_MIRROR_ANALYSIS_CONFIG_GET)
+
+#else
+#define MIRROR_API
+#define MIRROR_API_PARAM
+#endif
+
+#ifdef IN_RATE
+#define RATE_API \
+    SW_API_DEF(SW_API_RATE_QU_EGRL_SET, fal_rate_queue_egrl_set), \
+    SW_API_DEF(SW_API_RATE_QU_EGRL_GET, fal_rate_queue_egrl_get), \
+    SW_API_DEF(SW_API_RATE_PT_EGRL_SET, fal_rate_port_egrl_set), \
+    SW_API_DEF(SW_API_RATE_PT_EGRL_GET, fal_rate_port_egrl_get), \
+    SW_API_DEF(SW_API_RATE_PT_INRL_SET, fal_rate_port_inrl_set), \
+    SW_API_DEF(SW_API_RATE_PT_INRL_GET, fal_rate_port_inrl_get), \
+    SW_API_DEF(SW_API_STORM_CTRL_FRAME_SET, fal_storm_ctrl_frame_set), \
+    SW_API_DEF(SW_API_STORM_CTRL_FRAME_GET, fal_storm_ctrl_frame_get), \
+    SW_API_DEF(SW_API_STORM_CTRL_RATE_SET, fal_storm_ctrl_rate_set), \
+    SW_API_DEF(SW_API_STORM_CTRL_RATE_GET, fal_storm_ctrl_rate_get), \
+    SW_API_DEF(SW_API_RATE_PORT_POLICER_SET, fal_rate_port_policer_set), \
+    SW_API_DEF(SW_API_RATE_PORT_POLICER_GET, fal_rate_port_policer_get), \
+    SW_API_DEF(SW_API_RATE_PORT_SHAPER_SET, fal_rate_port_shaper_set), \
+    SW_API_DEF(SW_API_RATE_PORT_SHAPER_GET, fal_rate_port_shaper_get), \
+    SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_SET, fal_rate_queue_shaper_set), \
+    SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_GET, fal_rate_queue_shaper_get), \
+    SW_API_DEF(SW_API_RATE_ACL_POLICER_SET, fal_rate_acl_policer_set), \
+    SW_API_DEF(SW_API_RATE_ACL_POLICER_GET, fal_rate_acl_policer_get), \
+    SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, fal_rate_port_add_rate_byte_set), \
+    SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, fal_rate_port_add_rate_byte_get), \
+    SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, fal_rate_port_gol_flow_en_set),  \
+    SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, fal_rate_port_gol_flow_en_get),
+
+#define RATE_API_PARAM \
+    SW_API_DESC(SW_API_RATE_QU_EGRL_SET) \
+    SW_API_DESC(SW_API_RATE_QU_EGRL_GET) \
+    SW_API_DESC(SW_API_RATE_PT_EGRL_SET) \
+    SW_API_DESC(SW_API_RATE_PT_EGRL_GET) \
+    SW_API_DESC(SW_API_RATE_PT_INRL_SET) \
+    SW_API_DESC(SW_API_RATE_PT_INRL_GET) \
+    SW_API_DESC(SW_API_STORM_CTRL_FRAME_SET) \
+    SW_API_DESC(SW_API_STORM_CTRL_FRAME_GET) \
+    SW_API_DESC(SW_API_STORM_CTRL_RATE_SET) \
+    SW_API_DESC(SW_API_STORM_CTRL_RATE_GET) \
+    SW_API_DESC(SW_API_RATE_PORT_POLICER_SET) \
+    SW_API_DESC(SW_API_RATE_PORT_POLICER_GET) \
+    SW_API_DESC(SW_API_RATE_PORT_SHAPER_SET) \
+    SW_API_DESC(SW_API_RATE_PORT_SHAPER_GET) \
+    SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_SET) \
+    SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_GET) \
+    SW_API_DESC(SW_API_RATE_ACL_POLICER_SET) \
+    SW_API_DESC(SW_API_RATE_ACL_POLICER_GET) \
+    SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_SET) \
+    SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_GET) \
+    SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_SET) \
+    SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_GET)
+#else
+#define RATE_API
+#define RATE_API_PARAM
+#endif
+
+#ifdef IN_STP
+#define STP_API \
+    SW_API_DEF(SW_API_STP_PT_STATE_SET, fal_stp_port_state_set), \
+    SW_API_DEF(SW_API_STP_PT_STATE_GET, fal_stp_port_state_get),
+
+#define STP_API_PARAM \
+    SW_API_DESC(SW_API_STP_PT_STATE_SET) \
+    SW_API_DESC(SW_API_STP_PT_STATE_GET)
+#else
+#define STP_API
+#define STP_API_PARAM
+#endif
+
+#ifdef IN_MIB
+#define MIB_API \
+    SW_API_DEF(SW_API_PT_MIB_GET, fal_get_mib_info), \
+    SW_API_DEF(SW_API_MIB_STATUS_SET, fal_mib_status_set), \
+    SW_API_DEF(SW_API_MIB_STATUS_GET, fal_mib_status_get), \
+    SW_API_DEF(SW_API_PT_MIB_FLUSH_COUNTERS, fal_mib_port_flush_counters), \
+    SW_API_DEF(SW_API_MIB_CPU_KEEP_SET, fal_mib_cpukeep_set), \
+    SW_API_DEF(SW_API_MIB_CPU_KEEP_GET, fal_mib_cpukeep_get),\
+    SW_API_DEF(SW_API_PT_XGMIB_GET, fal_get_xgmib_info),\
+    SW_API_DEF(SW_API_PT_MIB_COUNTER_GET, fal_mib_counter_get),
+
+#define MIB_API_PARAM \
+    SW_API_DESC(SW_API_PT_MIB_GET)  \
+    SW_API_DESC(SW_API_PT_XGMIB_GET) \
+    SW_API_DESC(SW_API_MIB_STATUS_SET) \
+    SW_API_DESC(SW_API_MIB_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_MIB_FLUSH_COUNTERS) \
+    SW_API_DESC(SW_API_MIB_CPU_KEEP_SET) \
+    SW_API_DESC(SW_API_MIB_CPU_KEEP_GET) \
+    SW_API_DESC(SW_API_PT_MIB_COUNTER_GET)
+#else
+#define MIB_API
+#define MIB_API_PARAM
+#endif
+
+#ifdef IN_MISC
+#ifndef IN_MISC_MINI
+#define MISC_API \
+    SW_API_DEF(SW_API_ARP_STATUS_SET, fal_arp_status_set), \
+    SW_API_DEF(SW_API_ARP_STATUS_GET, fal_arp_status_get), \
+    SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, fal_frame_max_size_set), \
+    SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, fal_frame_max_size_get), \
+    SW_API_DEF(SW_API_PT_UNK_SA_CMD_SET, fal_port_unk_sa_cmd_set), \
+    SW_API_DEF(SW_API_PT_UNK_SA_CMD_GET, fal_port_unk_sa_cmd_get), \
+    SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, fal_port_unk_uc_filter_set), \
+    SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, fal_port_unk_uc_filter_get), \
+    SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, fal_port_unk_mc_filter_set), \
+    SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, fal_port_unk_mc_filter_get), \
+    SW_API_DEF(SW_API_PT_BC_FILTER_SET, fal_port_bc_filter_set), \
+    SW_API_DEF(SW_API_PT_BC_FILTER_GET, fal_port_bc_filter_get), \
+    SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, fal_cpu_port_status_set), \
+    SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, fal_cpu_port_status_get), \
+    SW_API_DEF(SW_API_BC_TO_CPU_PORT_SET, fal_bc_to_cpu_port_set), \
+    SW_API_DEF(SW_API_BC_TO_CPU_PORT_GET, fal_bc_to_cpu_port_get), \
+    SW_API_DEF(SW_API_PT_DHCP_SET, fal_port_dhcp_set), \
+    SW_API_DEF(SW_API_PT_DHCP_GET, fal_port_dhcp_get), \
+    SW_API_DEF(SW_API_ARP_CMD_SET, fal_arp_cmd_set), \
+    SW_API_DEF(SW_API_ARP_CMD_GET, fal_arp_cmd_get), \
+    SW_API_DEF(SW_API_EAPOL_CMD_SET, fal_eapol_cmd_set), \
+    SW_API_DEF(SW_API_EAPOL_CMD_GET, fal_eapol_cmd_get), \
+    SW_API_DEF(SW_API_EAPOL_STATUS_SET, fal_eapol_status_set), \
+    SW_API_DEF(SW_API_EAPOL_STATUS_GET, fal_eapol_status_get), \
+    SW_API_DEF(SW_API_RIPV1_STATUS_SET, fal_ripv1_status_set), \
+    SW_API_DEF(SW_API_RIPV1_STATUS_GET, fal_ripv1_status_get), \
+    SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_SET, fal_port_arp_req_status_set), \
+    SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_GET, fal_port_arp_req_status_get), \
+    SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_SET, fal_port_arp_ack_status_set), \
+    SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_GET, fal_port_arp_ack_status_get), \
+    SW_API_DEF(SW_API_INTR_MASK_SET, fal_intr_mask_set), \
+    SW_API_DEF(SW_API_INTR_MASK_GET, fal_intr_mask_get), \
+    SW_API_DEF(SW_API_INTR_STATUS_GET, fal_intr_status_get),   \
+    SW_API_DEF(SW_API_INTR_STATUS_CLEAR, fal_intr_status_clear), \
+    SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_SET, fal_intr_port_link_mask_set), \
+    SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_GET, fal_intr_port_link_mask_get), \
+    SW_API_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, fal_intr_port_link_status_get), \
+    SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, fal_intr_mask_mac_linkchg_set), \
+    SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, fal_intr_mask_mac_linkchg_get), \
+    SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_GET, fal_intr_status_mac_linkchg_get), \
+    SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, fal_intr_status_mac_linkchg_clear), \
+    SW_API_DEF(SW_API_CPU_VID_EN_SET, fal_cpu_vid_en_set), \
+    SW_API_DEF(SW_API_CPU_VID_EN_GET, fal_cpu_vid_en_get), \
+    SW_API_DEF(SW_API_GLOBAL_MACADDR_SET, fal_global_macaddr_set), \
+    SW_API_DEF(SW_API_GLOBAL_MACADDR_GET, fal_global_macaddr_get), \
+    SW_API_DEF(SW_API_LLDP_STATUS_SET, fal_lldp_status_set), \
+    SW_API_DEF(SW_API_LLDP_STATUS_GET, fal_lldp_status_get), \
+    SW_API_DEF(SW_API_FRAME_CRC_RESERVE_SET, fal_frame_crc_reserve_set), \
+    SW_API_DEF(SW_API_FRAME_CRC_RESERVE_GET, fal_frame_crc_reserve_get), \
+    SW_API_DEF(SW_API_DEBUG_PORT_COUNTER_ENABLE, fal_debug_port_counter_enable), \
+    SW_API_DEF(SW_API_DEBUG_PORT_COUNTER_STATUS_GET, fal_debug_port_counter_status_get),
+
+
+
+#define MISC_API_PARAM \
+    SW_API_DESC(SW_API_ARP_STATUS_SET) \
+    SW_API_DESC(SW_API_ARP_STATUS_GET) \
+    SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET) \
+    SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET) \
+    SW_API_DESC(SW_API_PT_UNK_SA_CMD_SET) \
+    SW_API_DESC(SW_API_PT_UNK_SA_CMD_GET) \
+    SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \
+    SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET) \
+    SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \
+    SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET) \
+    SW_API_DESC(SW_API_PT_BC_FILTER_SET) \
+    SW_API_DESC(SW_API_PT_BC_FILTER_GET) \
+    SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) \
+    SW_API_DESC(SW_API_CPU_PORT_STATUS_GET) \
+    SW_API_DESC(SW_API_BC_TO_CPU_PORT_SET) \
+    SW_API_DESC(SW_API_BC_TO_CPU_PORT_GET) \
+    SW_API_DESC(SW_API_PT_DHCP_SET) \
+    SW_API_DESC(SW_API_PT_DHCP_GET) \
+    SW_API_DESC(SW_API_ARP_CMD_SET) \
+    SW_API_DESC(SW_API_ARP_CMD_GET) \
+    SW_API_DESC(SW_API_EAPOL_CMD_SET) \
+    SW_API_DESC(SW_API_EAPOL_CMD_GET) \
+    SW_API_DESC(SW_API_EAPOL_STATUS_SET) \
+    SW_API_DESC(SW_API_EAPOL_STATUS_GET) \
+    SW_API_DESC(SW_API_RIPV1_STATUS_SET) \
+    SW_API_DESC(SW_API_RIPV1_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_SET) \
+    SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_SET) \
+    SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_GET) \
+    SW_API_DESC(SW_API_INTR_MASK_SET) \
+    SW_API_DESC(SW_API_INTR_MASK_GET) \
+    SW_API_DESC(SW_API_INTR_STATUS_GET)   \
+    SW_API_DESC(SW_API_INTR_STATUS_CLEAR) \
+    SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_SET) \
+    SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_GET) \
+    SW_API_DESC(SW_API_INTR_PORT_LINK_STATUS_GET) \
+    SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_SET) \
+    SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_GET) \
+    SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_GET) \
+    SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR) \
+    SW_API_DESC(SW_API_CPU_VID_EN_SET) \
+    SW_API_DESC(SW_API_CPU_VID_EN_GET) \
+    SW_API_DESC(SW_API_GLOBAL_MACADDR_SET) \
+    SW_API_DESC(SW_API_GLOBAL_MACADDR_GET) \
+    SW_API_DESC(SW_API_LLDP_STATUS_SET) \
+    SW_API_DESC(SW_API_LLDP_STATUS_GET) \
+    SW_API_DESC(SW_API_FRAME_CRC_RESERVE_SET) \
+    SW_API_DESC(SW_API_FRAME_CRC_RESERVE_GET) \
+    SW_API_DESC(SW_API_DEBUG_PORT_COUNTER_ENABLE) \
+    SW_API_DESC(SW_API_DEBUG_PORT_COUNTER_STATUS_GET)
+#else
+#define MISC_API \
+    SW_API_DEF(SW_API_PT_UNK_SA_CMD_SET, fal_port_unk_sa_cmd_set), \
+    SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, fal_port_unk_uc_filter_set), \
+    SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, fal_port_unk_mc_filter_set), \
+    SW_API_DEF(SW_API_PT_BC_FILTER_SET, fal_port_bc_filter_set), \
+    SW_API_DEF(SW_API_EAPOL_STATUS_SET, fal_eapol_status_set), \
+    SW_API_DEF(SW_API_EAPOL_CMD_SET, fal_eapol_cmd_set), \
+    SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, fal_cpu_port_status_set),
+
+#define MISC_API_PARAM \
+    SW_API_DESC(SW_API_PT_UNK_SA_CMD_SET) \
+    SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \
+    SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \
+    SW_API_DESC(SW_API_PT_BC_FILTER_SET) \
+    SW_API_DESC(SW_API_EAPOL_CMD_SET) \
+    SW_API_DESC(SW_API_EAPOL_STATUS_SET) \
+    SW_API_DESC(SW_API_CPU_PORT_STATUS_SET)
+
+#endif
+
+#else
+#define MISC_API
+#define MISC_API_PARAM
+#endif
+
+#ifdef IN_LED
+#define LED_API \
+    SW_API_DEF(SW_API_LED_PATTERN_SET, fal_led_ctrl_pattern_set), \
+    SW_API_DEF(SW_API_LED_PATTERN_GET, fal_led_ctrl_pattern_get),
+
+#define LED_API_PARAM \
+    SW_API_DESC(SW_API_LED_PATTERN_SET) \
+    SW_API_DESC(SW_API_LED_PATTERN_GET)
+#else
+#define LED_API
+#define LED_API_PARAM
+#endif
+
+#ifdef IN_COSMAP
+#ifndef IN_COSMAP_MINI
+#define COSMAP_API \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, fal_cosmap_dscp_to_pri_set), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, fal_cosmap_dscp_to_pri_get), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, fal_cosmap_dscp_to_dp_set), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, fal_cosmap_dscp_to_dp_get), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_SET, fal_cosmap_up_to_pri_set), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_GET, fal_cosmap_up_to_pri_get), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_DP_SET, fal_cosmap_up_to_dp_set), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_DP_GET, fal_cosmap_up_to_dp_get), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_SET, fal_cosmap_pri_to_queue_set), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_GET, fal_cosmap_pri_to_queue_get), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, fal_cosmap_pri_to_ehqueue_set), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, fal_cosmap_pri_to_ehqueue_get), \
+    SW_API_DEF(SW_API_COSMAP_EG_REMARK_SET, fal_cosmap_egress_remark_set), \
+    SW_API_DEF(SW_API_COSMAP_EG_REMARK_GET, fal_cosmap_egress_remark_get), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_SET, fal_cosmap_dscp_to_ehpri_set), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_GET, fal_cosmap_dscp_to_ehpri_get), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_EHDP_SET, fal_cosmap_dscp_to_ehdp_set), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_EHDP_GET, fal_cosmap_dscp_to_ehdp_get), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_EHPRI_SET, fal_cosmap_up_to_ehpri_set), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_EHPRI_GET, fal_cosmap_up_to_ehpri_get), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_EHDP_SET, fal_cosmap_up_to_ehdp_set), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_EHDP_GET, fal_cosmap_up_to_ehdp_get),
+
+#define COSMAP_API_PARAM \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_SET)  \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_GET)  \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_SET)  \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_GET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_SET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_GET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_DP_SET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_DP_GET)  \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_SET)  \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_GET)  \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_SET) \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_GET) \
+    SW_API_DESC(SW_API_COSMAP_EG_REMARK_SET) \
+    SW_API_DESC(SW_API_COSMAP_EG_REMARK_GET) \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_EHPRI_SET)  \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_EHPRI_GET)  \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_EHDP_SET)  \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_EHDP_GET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_EHPRI_SET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_EHPRI_GET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_EHDP_SET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_EHDP_GET)
+#else
+#define COSMAP_API \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_SET, fal_cosmap_pri_to_queue_set), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, fal_cosmap_pri_to_ehqueue_set),
+
+#define COSMAP_API_PARAM \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_SET)  \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_SET)
+#endif
+#else
+#define COSMAP_API
+#define COSMAP_API_PARAM
+#endif
+
+#ifdef IN_SEC
+#define SEC_API \
+    SW_API_DEF(SW_API_SEC_NORM_SET, fal_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_NORM_GET, fal_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_MAC_SET, fal_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_MAC_GET, fal_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_IP_SET, fal_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_IP_GET, fal_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_IP4_SET, fal_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_IP4_GET, fal_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_IP6_SET, fal_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_IP6_GET, fal_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_TCP_SET, fal_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_TCP_GET, fal_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_UDP_SET, fal_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_UDP_GET, fal_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_ICMP4_SET, fal_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_ICMP4_GET, fal_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_ICMP6_SET, fal_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_ICMP6_GET, fal_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_L3_PARSER_CTRL_GET, fal_sec_l3_excep_parser_ctrl_get), \
+    SW_API_DEF(SW_API_SEC_L3_PARSER_CTRL_SET, fal_sec_l3_excep_parser_ctrl_set), \
+    SW_API_DEF(SW_API_SEC_L4_PARSER_CTRL_GET, fal_sec_l4_excep_parser_ctrl_get), \
+    SW_API_DEF(SW_API_SEC_L4_PARSER_CTRL_SET, fal_sec_l4_excep_parser_ctrl_set), \
+    SW_API_DEF(SW_API_SEC_EXP_CTRL_GET, fal_sec_l3_excep_ctrl_get), \
+    SW_API_DEF(SW_API_SEC_EXP_CTRL_SET, fal_sec_l3_excep_ctrl_set),
+
+#define SEC_API_PARAM \
+    SW_API_DESC(SW_API_SEC_NORM_SET) \
+    SW_API_DESC(SW_API_SEC_NORM_GET) \
+    SW_API_DESC(SW_API_SEC_MAC_SET) \
+    SW_API_DESC(SW_API_SEC_MAC_GET) \
+    SW_API_DESC(SW_API_SEC_IP_SET) \
+    SW_API_DESC(SW_API_SEC_IP_GET) \
+    SW_API_DESC(SW_API_SEC_IP4_SET) \
+    SW_API_DESC(SW_API_SEC_IP4_GET) \
+    SW_API_DESC(SW_API_SEC_IP6_SET) \
+    SW_API_DESC(SW_API_SEC_IP6_GET) \
+    SW_API_DESC(SW_API_SEC_TCP_SET) \
+    SW_API_DESC(SW_API_SEC_TCP_GET) \
+    SW_API_DESC(SW_API_SEC_UDP_SET) \
+    SW_API_DESC(SW_API_SEC_UDP_GET) \
+    SW_API_DESC(SW_API_SEC_ICMP4_SET) \
+    SW_API_DESC(SW_API_SEC_ICMP4_GET) \
+    SW_API_DESC(SW_API_SEC_ICMP6_SET) \
+    SW_API_DESC(SW_API_SEC_ICMP6_GET) \
+    SW_API_DESC(SW_API_SEC_L3_PARSER_CTRL_GET) \
+    SW_API_DESC(SW_API_SEC_L3_PARSER_CTRL_SET) \
+    SW_API_DESC(SW_API_SEC_L4_PARSER_CTRL_GET) \
+    SW_API_DESC(SW_API_SEC_L4_PARSER_CTRL_SET) \
+    SW_API_DESC(SW_API_SEC_EXP_CTRL_GET) \
+    SW_API_DESC(SW_API_SEC_EXP_CTRL_SET)
+#else
+#define SEC_API
+#define SEC_API_PARAM
+#endif
+
+#ifdef IN_IP
+#ifndef IN_IP_MINI
+#define IP_API \
+    SW_API_DEF(SW_API_IP_HOST_ADD, fal_ip_host_add), \
+    SW_API_DEF(SW_API_IP_HOST_DEL, fal_ip_host_del), \
+    SW_API_DEF(SW_API_IP_HOST_GET, fal_ip_host_get), \
+    SW_API_DEF(SW_API_IP_HOST_NEXT, fal_ip_host_next), \
+    SW_API_DEF(SW_API_IP_HOST_COUNTER_BIND, fal_ip_host_counter_bind), \
+    SW_API_DEF(SW_API_IP_HOST_PPPOE_BIND, fal_ip_host_pppoe_bind), \
+    SW_API_DEF(SW_API_IP_PT_ARP_LEARN_SET, fal_ip_pt_arp_learn_set), \
+    SW_API_DEF(SW_API_IP_PT_ARP_LEARN_GET, fal_ip_pt_arp_learn_get), \
+    SW_API_DEF(SW_API_IP_ARP_LEARN_SET, fal_ip_arp_learn_set), \
+    SW_API_DEF(SW_API_IP_ARP_LEARN_GET, fal_ip_arp_learn_get), \
+    SW_API_DEF(SW_API_IP_SOURCE_GUARD_SET, fal_ip_source_guard_set), \
+    SW_API_DEF(SW_API_IP_SOURCE_GUARD_GET, fal_ip_source_guard_get), \
+    SW_API_DEF(SW_API_IP_ARP_GUARD_SET, fal_ip_arp_guard_set), \
+    SW_API_DEF(SW_API_IP_ARP_GUARD_GET, fal_ip_arp_guard_get), \
+    SW_API_DEF(SW_API_IP_ROUTE_STATUS_SET, fal_ip_route_status_set), \
+    SW_API_DEF(SW_API_IP_ROUTE_STATUS_GET, fal_ip_route_status_get), \
+    SW_API_DEF(SW_API_IP_INTF_ENTRY_ADD, fal_ip_intf_entry_add), \
+    SW_API_DEF(SW_API_IP_INTF_ENTRY_DEL, fal_ip_intf_entry_del), \
+    SW_API_DEF(SW_API_IP_INTF_ENTRY_NEXT, fal_ip_intf_entry_next), \
+    SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, fal_ip_unk_source_cmd_set), \
+    SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, fal_ip_unk_source_cmd_get), \
+    SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, fal_arp_unk_source_cmd_set), \
+    SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, fal_arp_unk_source_cmd_get), \
+    SW_API_DEF(SW_API_IP_AGE_TIME_SET, fal_ip_age_time_set), \
+    SW_API_DEF(SW_API_IP_AGE_TIME_GET, fal_ip_age_time_get), \
+    SW_API_DEF(SW_API_WCMP_HASH_MODE_SET, fal_ip_wcmp_hash_mode_set), \
+    SW_API_DEF(SW_API_WCMP_HASH_MODE_GET, fal_ip_wcmp_hash_mode_get),  \
+    SW_API_DEF(SW_API_IP_VRF_BASE_ADDR_SET, fal_ip_vrf_base_addr_set), \
+    SW_API_DEF(SW_API_IP_VRF_BASE_ADDR_GET, fal_ip_vrf_base_addr_get), \
+    SW_API_DEF(SW_API_IP_VRF_BASE_MASK_SET, fal_ip_vrf_base_mask_set), \
+    SW_API_DEF(SW_API_IP_VRF_BASE_MASK_GET, fal_ip_vrf_base_mask_get), \
+    SW_API_DEF(SW_API_IP_DEFAULT_ROUTE_SET, fal_ip_default_route_set), \
+    SW_API_DEF(SW_API_IP_DEFAULT_ROUTE_GET, fal_ip_default_route_get), \
+    SW_API_DEF(SW_API_IP_HOST_ROUTE_SET, fal_ip_host_route_set), \
+    SW_API_DEF(SW_API_IP_HOST_ROUTE_GET, fal_ip_host_route_get), \
+    SW_API_DEF(SW_API_IP_WCMP_ENTRY_SET, fal_ip_wcmp_entry_set), \
+    SW_API_DEF(SW_API_IP_WCMP_ENTRY_GET, fal_ip_wcmp_entry_get), \
+    SW_API_DEF(SW_API_IP_RFS_IP4_SET,    fal_ip_rfs_ip4_rule_set), \
+	SW_API_DEF(SW_API_IP_RFS_IP6_SET,    fal_ip_rfs_ip6_rule_set), \
+	SW_API_DEF(SW_API_IP_RFS_IP4_DEL,    fal_ip_rfs_ip4_rule_del), \
+	SW_API_DEF(SW_API_IP_RFS_IP6_DEL,    fal_ip_rfs_ip6_rule_del), \
+    SW_API_DEF(SW_API_IP_DEFAULT_FLOW_CMD_SET, fal_default_flow_cmd_set), \
+    SW_API_DEF(SW_API_IP_DEFAULT_FLOW_CMD_GET, fal_default_flow_cmd_get), \
+    SW_API_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET, fal_default_rt_flow_cmd_set), \
+    SW_API_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET, fal_default_rt_flow_cmd_get), \
+    SW_API_DEF(SW_API_IP_VIS_ARP_SG_CFG_GET, fal_ip_vsi_arp_sg_cfg_get), \
+    SW_API_DEF(SW_API_IP_VIS_ARP_SG_CFG_SET, fal_ip_vsi_arp_sg_cfg_set), \
+    SW_API_DEF(SW_API_IP_NETWORK_ROUTE_GET, fal_ip_network_route_get), \
+    SW_API_DEF(SW_API_IP_NETWORK_ROUTE_ADD, fal_ip_network_route_add), \
+    SW_API_DEF(SW_API_IP_INTF_GET, fal_ip_intf_get), \
+    SW_API_DEF(SW_API_IP_INTF_SET, fal_ip_intf_set), \
+    SW_API_DEF(SW_API_IP_VSI_INTF_GET, fal_ip_vsi_intf_get), \
+    SW_API_DEF(SW_API_IP_VSI_INTF_SET, fal_ip_vsi_intf_set), \
+    SW_API_DEF(SW_API_IP_NEXTHOP_GET, fal_ip_nexthop_get), \
+    SW_API_DEF(SW_API_IP_NEXTHOP_SET, fal_ip_nexthop_set), \
+    SW_API_DEF(SW_API_IP_VSI_SG_SET, fal_ip_vsi_sg_cfg_set), \
+    SW_API_DEF(SW_API_IP_VSI_SG_GET, fal_ip_vsi_sg_cfg_get), \
+    SW_API_DEF(SW_API_IP_PORT_SG_SET, fal_ip_port_sg_cfg_set), \
+    SW_API_DEF(SW_API_IP_PORT_SG_GET, fal_ip_port_sg_cfg_get), \
+    SW_API_DEF(SW_API_IP_PUB_IP_SET, fal_ip_pub_addr_set), \
+    SW_API_DEF(SW_API_IP_PUB_IP_GET, fal_ip_pub_addr_get), \
+    SW_API_DEF(SW_API_IP_NETWORK_ROUTE_DEL, fal_ip_network_route_del), \
+    SW_API_DEF(SW_API_IP_PORT_INTF_GET, fal_ip_port_intf_get), \
+    SW_API_DEF(SW_API_IP_PORT_INTF_SET, fal_ip_port_intf_set), \
+    SW_API_DEF(SW_API_IP_PORT_MAC_GET, fal_ip_port_macaddr_get), \
+    SW_API_DEF(SW_API_IP_PORT_MAC_SET, fal_ip_port_macaddr_set), \
+    SW_API_DEF(SW_API_IP_ROUTE_MISS_GET, fal_ip_route_mismatch_action_get), \
+    SW_API_DEF(SW_API_IP_ROUTE_MISS_SET, fal_ip_route_mismatch_action_set), \
+    SW_API_DEF(SW_API_IP_PORT_ARP_SG_SET, fal_ip_port_arp_sg_cfg_set), \
+    SW_API_DEF(SW_API_IP_PORT_ARP_SG_GET, fal_ip_port_arp_sg_cfg_get), \
+    SW_API_DEF(SW_API_IP_VSI_MC_MODE_SET, fal_ip_vsi_mc_mode_set), \
+    SW_API_DEF(SW_API_IP_VSI_MC_MODE_GET, fal_ip_vsi_mc_mode_get), \
+    SW_API_DEF(SW_API_GLOBAL_CTRL_GET, fal_ip_global_ctrl_get), \
+    SW_API_DEF(SW_API_GLOBAL_CTRL_SET, fal_ip_global_ctrl_set),
+
+#define IP_API_PARAM \
+    SW_API_DESC(SW_API_IP_HOST_ADD) \
+    SW_API_DESC(SW_API_IP_HOST_DEL) \
+    SW_API_DESC(SW_API_IP_HOST_GET) \
+    SW_API_DESC(SW_API_IP_HOST_NEXT) \
+    SW_API_DESC(SW_API_IP_HOST_COUNTER_BIND) \
+    SW_API_DESC(SW_API_IP_HOST_PPPOE_BIND) \
+    SW_API_DESC(SW_API_IP_PT_ARP_LEARN_SET) \
+    SW_API_DESC(SW_API_IP_PT_ARP_LEARN_GET) \
+    SW_API_DESC(SW_API_IP_ARP_LEARN_SET) \
+    SW_API_DESC(SW_API_IP_ARP_LEARN_GET) \
+    SW_API_DESC(SW_API_IP_SOURCE_GUARD_SET) \
+    SW_API_DESC(SW_API_IP_SOURCE_GUARD_GET) \
+    SW_API_DESC(SW_API_IP_ARP_GUARD_SET) \
+    SW_API_DESC(SW_API_IP_ARP_GUARD_GET) \
+    SW_API_DESC(SW_API_IP_ROUTE_STATUS_SET) \
+    SW_API_DESC(SW_API_IP_ROUTE_STATUS_GET) \
+    SW_API_DESC(SW_API_IP_INTF_ENTRY_ADD) \
+    SW_API_DESC(SW_API_IP_INTF_ENTRY_DEL) \
+    SW_API_DESC(SW_API_IP_INTF_ENTRY_NEXT) \
+    SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_SET)  \
+    SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_GET)  \
+    SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_SET) \
+    SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_GET) \
+    SW_API_DESC(SW_API_IP_AGE_TIME_SET)  \
+    SW_API_DESC(SW_API_IP_AGE_TIME_GET) \
+    SW_API_DESC(SW_API_WCMP_HASH_MODE_SET) \
+    SW_API_DESC(SW_API_WCMP_HASH_MODE_GET) \
+    SW_API_DESC(SW_API_IP_VRF_BASE_ADDR_SET) \
+    SW_API_DESC(SW_API_IP_VRF_BASE_ADDR_GET) \
+    SW_API_DESC(SW_API_IP_VRF_BASE_MASK_SET) \
+    SW_API_DESC(SW_API_IP_VRF_BASE_MASK_GET) \
+    SW_API_DESC(SW_API_IP_DEFAULT_ROUTE_SET) \
+    SW_API_DESC(SW_API_IP_DEFAULT_ROUTE_GET) \
+    SW_API_DESC(SW_API_IP_HOST_ROUTE_SET) \
+    SW_API_DESC(SW_API_IP_HOST_ROUTE_GET) \
+    SW_API_DESC(SW_API_IP_WCMP_ENTRY_SET) \
+    SW_API_DESC(SW_API_IP_WCMP_ENTRY_GET) \
+    SW_API_DESC(SW_API_IP_RFS_IP4_SET)  \
+    SW_API_DESC(SW_API_IP_RFS_IP6_SET)  \
+    SW_API_DESC(SW_API_IP_RFS_IP4_DEL)  \
+    SW_API_DESC(SW_API_IP_RFS_IP6_DEL)  \
+    SW_API_DESC(SW_API_IP_DEFAULT_FLOW_CMD_SET) \
+    SW_API_DESC(SW_API_IP_DEFAULT_FLOW_CMD_GET) \
+    SW_API_DESC(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET) \
+    SW_API_DESC(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET) \
+    SW_API_DESC(SW_API_IP_VIS_ARP_SG_CFG_GET) \
+    SW_API_DESC(SW_API_IP_VIS_ARP_SG_CFG_SET) \
+    SW_API_DESC(SW_API_IP_NETWORK_ROUTE_GET) \
+    SW_API_DESC(SW_API_IP_NETWORK_ROUTE_ADD) \
+    SW_API_DESC(SW_API_IP_INTF_GET) \
+    SW_API_DESC(SW_API_IP_INTF_SET) \
+    SW_API_DESC(SW_API_IP_VSI_INTF_GET) \
+    SW_API_DESC(SW_API_IP_VSI_INTF_SET) \
+    SW_API_DESC(SW_API_IP_NEXTHOP_GET) \
+    SW_API_DESC(SW_API_IP_NEXTHOP_SET) \
+    SW_API_DESC(SW_API_IP_VSI_SG_SET) \
+    SW_API_DESC(SW_API_IP_VSI_SG_GET) \
+    SW_API_DESC(SW_API_IP_PORT_SG_SET) \
+    SW_API_DESC(SW_API_IP_PORT_SG_GET) \
+    SW_API_DESC(SW_API_IP_PUB_IP_SET) \
+    SW_API_DESC(SW_API_IP_PUB_IP_GET) \
+    SW_API_DESC(SW_API_IP_NETWORK_ROUTE_DEL) \
+    SW_API_DESC(SW_API_IP_PORT_INTF_GET) \
+    SW_API_DESC(SW_API_IP_PORT_INTF_SET) \
+    SW_API_DESC(SW_API_IP_PORT_MAC_GET) \
+    SW_API_DESC(SW_API_IP_PORT_MAC_SET) \
+    SW_API_DESC(SW_API_IP_ROUTE_MISS_GET) \
+    SW_API_DESC(SW_API_IP_ROUTE_MISS_SET) \
+    SW_API_DESC(SW_API_IP_PORT_ARP_SG_SET) \
+    SW_API_DESC(SW_API_IP_PORT_ARP_SG_GET) \
+    SW_API_DESC(SW_API_IP_VSI_MC_MODE_SET) \
+    SW_API_DESC(SW_API_IP_VSI_MC_MODE_GET) \
+    SW_API_DESC(SW_API_GLOBAL_CTRL_GET) \
+    SW_API_DESC(SW_API_GLOBAL_CTRL_SET)
+#else
+#define IP_API
+#define IP_API_PARAM
+#endif
+#else
+#define IP_API
+#define IP_API_PARAM
+#endif
+
+#ifdef IN_FLOW
+#ifndef IN_FLOW_MINI
+#define FLOW_API \
+    SW_API_DEF(SW_API_FLOW_STATUS_SET, fal_flow_status_set), \
+    SW_API_DEF(SW_API_FLOW_STATUS_GET, fal_flow_status_get), \
+    SW_API_DEF(SW_API_FLOW_AGE_TIMER_SET, fal_flow_age_timer_set), \
+    SW_API_DEF(SW_API_FLOW_AGE_TIMER_GET, fal_flow_age_timer_get), \
+    SW_API_DEF(SW_API_FLOW_CTRL_SET, fal_flow_mgmt_set), \
+    SW_API_DEF(SW_API_FLOW_CTRL_GET, fal_flow_mgmt_get), \
+    SW_API_DEF(SW_API_FLOW_ENTRY_ADD, fal_flow_entry_add), \
+    SW_API_DEF(SW_API_FLOW_ENTRY_DEL, fal_flow_entry_del), \
+    SW_API_DEF(SW_API_FLOW_ENTRY_GET, fal_flow_entry_get), \
+    SW_API_DEF(SW_API_FLOW_GLOBAL_CFG_GET, fal_flow_global_cfg_get), \
+    SW_API_DEF(SW_API_FLOW_GLOBAL_CFG_SET, fal_flow_global_cfg_set), \
+    SW_API_DEF(SW_API_FLOW_HOST_ADD, fal_flow_host_add), \
+    SW_API_DEF(SW_API_FLOW_HOST_GET, fal_flow_host_get), \
+    SW_API_DEF(SW_API_FLOW_HOST_DEL, fal_flow_host_del), \
+    SW_API_DEF(SW_API_FLOWENTRY_NEXT, fal_flow_entry_next),
+
+#define FLOW_API_PARAM \
+    SW_API_DESC(SW_API_FLOW_STATUS_SET) \
+    SW_API_DESC(SW_API_FLOW_STATUS_GET) \
+    SW_API_DESC(SW_API_FLOW_AGE_TIMER_SET) \
+    SW_API_DESC(SW_API_FLOW_AGE_TIMER_GET) \
+    SW_API_DESC(SW_API_FLOW_CTRL_SET) \
+    SW_API_DESC(SW_API_FLOW_CTRL_GET) \
+    SW_API_DESC(SW_API_FLOW_ENTRY_ADD) \
+    SW_API_DESC(SW_API_FLOW_ENTRY_DEL) \
+    SW_API_DESC(SW_API_FLOW_ENTRY_GET) \
+    SW_API_DESC(SW_API_FLOW_GLOBAL_CFG_GET) \
+    SW_API_DESC(SW_API_FLOW_GLOBAL_CFG_SET) \
+    SW_API_DESC(SW_API_FLOW_HOST_ADD) \
+    SW_API_DESC(SW_API_FLOW_HOST_GET) \
+    SW_API_DESC(SW_API_FLOW_HOST_DEL) \
+    SW_API_DESC(SW_API_FLOWENTRY_NEXT)
+#else
+#define FLOW_API \
+    SW_API_DEF(SW_API_FLOW_CTRL_SET, fal_flow_mgmt_set), \
+    SW_API_DEF(SW_API_FLOW_CTRL_GET, fal_flow_mgmt_get),
+
+#define FLOW_API_PARAM \
+    SW_API_DESC(SW_API_FLOW_CTRL_SET) \
+    SW_API_DESC(SW_API_FLOW_CTRL_GET)
+#endif
+#else
+#define FLOW_API
+#define FLOW_API_PARAM
+#endif
+
+
+#ifdef IN_NAT
+#define NAT_API \
+    SW_API_DEF(SW_API_NAT_ADD, fal_nat_add), \
+    SW_API_DEF(SW_API_NAT_DEL, fal_nat_del), \
+    SW_API_DEF(SW_API_NAT_GET, fal_nat_get), \
+    SW_API_DEF(SW_API_NAT_NEXT, fal_nat_next), \
+    SW_API_DEF(SW_API_NAT_COUNTER_BIND, fal_nat_counter_bind), \
+    SW_API_DEF(SW_API_NAPT_ADD, fal_napt_add), \
+    SW_API_DEF(SW_API_NAPT_DEL, fal_napt_del), \
+    SW_API_DEF(SW_API_NAPT_GET, fal_napt_get), \
+    SW_API_DEF(SW_API_NAPT_NEXT, fal_napt_next), \
+    SW_API_DEF(SW_API_NAPT_COUNTER_BIND, fal_napt_counter_bind), \
+    SW_API_DEF(SW_API_FLOW_ADD, fal_flow_add), \
+    SW_API_DEF(SW_API_FLOW_DEL, fal_flow_del), \
+    SW_API_DEF(SW_API_FLOW_GET, fal_flow_get), \
+    SW_API_DEF(SW_API_FLOW_NEXT, fal_flow_next), \
+    SW_API_DEF(SW_API_FLOW_COUNTER_BIND, fal_flow_counter_bind), \
+    SW_API_DEF(SW_API_NAT_STATUS_SET, fal_nat_status_set), \
+    SW_API_DEF(SW_API_NAT_STATUS_GET, fal_nat_status_get), \
+    SW_API_DEF(SW_API_NAT_HASH_MODE_SET, fal_nat_hash_mode_set), \
+    SW_API_DEF(SW_API_NAT_HASH_MODE_GET, fal_nat_hash_mode_get), \
+    SW_API_DEF(SW_API_NAPT_STATUS_SET, fal_napt_status_set), \
+    SW_API_DEF(SW_API_NAPT_STATUS_GET, fal_napt_status_get), \
+    SW_API_DEF(SW_API_NAPT_MODE_SET, fal_napt_mode_set), \
+    SW_API_DEF(SW_API_NAPT_MODE_GET, fal_napt_mode_get), \
+    SW_API_DEF(SW_API_PRV_BASE_ADDR_SET, fal_nat_prv_base_addr_set), \
+    SW_API_DEF(SW_API_PRV_BASE_ADDR_GET, fal_nat_prv_base_addr_get), \
+    SW_API_DEF(SW_API_PRV_ADDR_MODE_SET, fal_nat_prv_addr_mode_set), \
+    SW_API_DEF(SW_API_PRV_ADDR_MODE_GET, fal_nat_prv_addr_mode_get), \
+    SW_API_DEF(SW_API_PUB_ADDR_ENTRY_ADD, fal_nat_pub_addr_add), \
+    SW_API_DEF(SW_API_PUB_ADDR_ENTRY_DEL, fal_nat_pub_addr_del), \
+    SW_API_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, fal_nat_pub_addr_next), \
+    SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, fal_nat_unk_session_cmd_set), \
+    SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, fal_nat_unk_session_cmd_get), \
+    SW_API_DEF(SW_API_PRV_BASE_MASK_SET, fal_nat_prv_base_mask_set), \
+    SW_API_DEF(SW_API_PRV_BASE_MASK_GET, fal_nat_prv_base_mask_get), \
+    SW_API_DEF(SW_API_NAT_GLOBAL_SET, fal_nat_global_set),           \
+    SW_API_DEF(SW_API_FLOW_COOKIE_SET, fal_flow_cookie_set),         \
+    SW_API_DEF(SW_API_FLOW_RFS_SET, fal_flow_rfs_set),
+
+#define NAT_API_PARAM \
+    SW_API_DESC(SW_API_NAT_ADD) \
+    SW_API_DESC(SW_API_NAT_DEL) \
+    SW_API_DESC(SW_API_NAT_GET) \
+    SW_API_DESC(SW_API_NAT_NEXT) \
+    SW_API_DESC(SW_API_NAT_COUNTER_BIND) \
+    SW_API_DESC(SW_API_NAPT_ADD) \
+    SW_API_DESC(SW_API_NAPT_DEL) \
+    SW_API_DESC(SW_API_NAPT_GET) \
+    SW_API_DESC(SW_API_NAPT_NEXT) \
+    SW_API_DESC(SW_API_NAPT_COUNTER_BIND) \
+    SW_API_DESC(SW_API_FLOW_ADD) \
+    SW_API_DESC(SW_API_FLOW_DEL) \
+    SW_API_DESC(SW_API_FLOW_GET) \
+    SW_API_DESC(SW_API_FLOW_NEXT) \
+    SW_API_DESC(SW_API_FLOW_COUNTER_BIND) \
+    SW_API_DESC(SW_API_NAT_STATUS_SET) \
+    SW_API_DESC(SW_API_NAT_STATUS_GET) \
+    SW_API_DESC(SW_API_NAT_HASH_MODE_SET) \
+    SW_API_DESC(SW_API_NAT_HASH_MODE_GET) \
+    SW_API_DESC(SW_API_NAPT_STATUS_SET) \
+    SW_API_DESC(SW_API_NAPT_STATUS_GET) \
+    SW_API_DESC(SW_API_NAPT_MODE_SET) \
+    SW_API_DESC(SW_API_NAPT_MODE_GET) \
+    SW_API_DESC(SW_API_PRV_BASE_ADDR_SET) \
+    SW_API_DESC(SW_API_PRV_BASE_ADDR_GET) \
+    SW_API_DESC(SW_API_PRV_ADDR_MODE_SET) \
+    SW_API_DESC(SW_API_PRV_ADDR_MODE_GET) \
+    SW_API_DESC(SW_API_PUB_ADDR_ENTRY_ADD) \
+    SW_API_DESC(SW_API_PUB_ADDR_ENTRY_DEL) \
+    SW_API_DESC(SW_API_PUB_ADDR_ENTRY_NEXT) \
+    SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_SET) \
+    SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_GET) \
+    SW_API_DESC(SW_API_PRV_BASE_MASK_SET) \
+    SW_API_DESC(SW_API_PRV_BASE_MASK_GET) \
+    SW_API_DESC(SW_API_NAT_GLOBAL_SET)    \
+    SW_API_DESC(SW_API_FLOW_COOKIE_SET)   \
+    SW_API_DESC(SW_API_FLOW_RFS_SET)
+#else
+#define NAT_API
+#define NAT_API_PARAM
+#endif
+
+#ifdef IN_TRUNK
+#define TRUNK_API \
+    SW_API_DEF(SW_API_TRUNK_GROUP_SET, fal_trunk_group_set), \
+    SW_API_DEF(SW_API_TRUNK_GROUP_GET, fal_trunk_group_get), \
+    SW_API_DEF(SW_API_TRUNK_HASH_SET, fal_trunk_hash_mode_set), \
+    SW_API_DEF(SW_API_TRUNK_HASH_GET, fal_trunk_hash_mode_get), \
+    SW_API_DEF(SW_API_TRUNK_MAN_SA_SET, fal_trunk_manipulate_sa_set), \
+    SW_API_DEF(SW_API_TRUNK_MAN_SA_GET, fal_trunk_manipulate_sa_get), \
+    SW_API_DEF(SW_API_TRUNK_FAILOVER_EN_SET, fal_trunk_failover_enable), \
+    SW_API_DEF(SW_API_TRUNK_FAILOVER_EN_GET, fal_trunk_failover_status_get),
+
+#define TRUNK_API_PARAM \
+    SW_API_DESC(SW_API_TRUNK_GROUP_SET) \
+    SW_API_DESC(SW_API_TRUNK_GROUP_GET) \
+    SW_API_DESC(SW_API_TRUNK_HASH_SET)  \
+    SW_API_DESC(SW_API_TRUNK_HASH_GET)  \
+    SW_API_DESC(SW_API_TRUNK_MAN_SA_SET)\
+    SW_API_DESC(SW_API_TRUNK_MAN_SA_GET) \
+    SW_API_DESC(SW_API_TRUNK_FAILOVER_EN_SET)\
+    SW_API_DESC(SW_API_TRUNK_FAILOVER_EN_GET)
+#else
+#define TRUNK_API
+#define TRUNK_API_PARAM
+#endif
+
+#ifdef IN_INTERFACECONTROL
+#define INTERFACECTRL_API \
+    SW_API_DEF(SW_API_MAC_MODE_SET, fal_interface_mac_mode_set), \
+    SW_API_DEF(SW_API_MAC_MODE_GET, fal_interface_mac_mode_get), \
+    SW_API_DEF(SW_API_PORT_3AZ_STATUS_SET, fal_port_3az_status_set), \
+    SW_API_DEF(SW_API_PORT_3AZ_STATUS_GET, fal_port_3az_status_get), \
+    SW_API_DEF(SW_API_PHY_MODE_SET, fal_interface_phy_mode_set), \
+    SW_API_DEF(SW_API_PHY_MODE_GET, fal_interface_phy_mode_get), \
+    SW_API_DEF(SW_API_FX100_CTRL_SET, fal_interface_fx100_ctrl_set), \
+    SW_API_DEF(SW_API_FX100_CTRL_GET, fal_interface_fx100_ctrl_get), \
+    SW_API_DEF(SW_API_FX100_STATUS_GET, fal_interface_fx100_status_get),\
+    SW_API_DEF(SW_API_MAC06_EXCH_SET, fal_interface_mac06_exch_set),\
+    SW_API_DEF(SW_API_MAC06_EXCH_GET, fal_interface_mac06_exch_get),
+
+#define INTERFACECTRL_API_PARAM \
+    SW_API_DESC(SW_API_MAC_MODE_SET)  \
+    SW_API_DESC(SW_API_MAC_MODE_GET)  \
+    SW_API_DESC(SW_API_PORT_3AZ_STATUS_SET)  \
+    SW_API_DESC(SW_API_PORT_3AZ_STATUS_GET)  \
+    SW_API_DESC(SW_API_PHY_MODE_SET)  \
+    SW_API_DESC(SW_API_PHY_MODE_GET)  \
+    SW_API_DESC(SW_API_FX100_CTRL_SET)  \
+    SW_API_DESC(SW_API_FX100_CTRL_GET) \
+    SW_API_DESC(SW_API_FX100_STATUS_GET) \
+    SW_API_DESC(SW_API_MAC06_EXCH_SET) \
+    SW_API_DESC(SW_API_MAC06_EXCH_GET)
+
+#else
+#define INTERFACECTRL_API
+#define INTERFACECTRL_API_PARAM
+#endif
+
+#ifdef IN_VSI
+#ifndef IN_VSI_MINI
+#define VSI_API \
+    SW_API_DEF(SW_API_VSI_ALLOC, ppe_vsi_alloc), \
+    SW_API_DEF(SW_API_VSI_FREE, ppe_vsi_free), \
+    SW_API_DEF(SW_API_PORT_VSI_SET, fal_port_vsi_set), \
+    SW_API_DEF(SW_API_PORT_VSI_GET, fal_port_vsi_get), \
+    SW_API_DEF(SW_API_PORT_VLAN_VSI_SET, ppe_port_vlan_vsi_set), \
+    SW_API_DEF(SW_API_PORT_VLAN_VSI_GET, ppe_port_vlan_vsi_get), \
+    SW_API_DEF(SW_API_VSI_TBL_DUMP, ppe_vsi_tbl_dump), \
+    SW_API_DEF(SW_API_VSI_NEWADDR_LRN_GET, fal_vsi_newaddr_lrn_get), \
+    SW_API_DEF(SW_API_VSI_NEWADDR_LRN_SET, fal_vsi_newaddr_lrn_set), \
+    SW_API_DEF(SW_API_VSI_STAMOVE_SET, fal_vsi_stamove_set), \
+    SW_API_DEF(SW_API_VSI_STAMOVE_GET,fal_vsi_stamove_get),  \
+    SW_API_DEF(SW_API_VSI_MEMBER_SET, fal_vsi_member_set), \
+    SW_API_DEF(SW_API_VSI_MEMBER_GET, fal_vsi_member_get),  \
+    SW_API_DEF(SW_API_VSI_COUNTER_GET,fal_vsi_counter_get),  \
+    SW_API_DEF(SW_API_VSI_COUNTER_CLEANUP,fal_vsi_counter_cleanup),
+
+
+#define VSI_API_PARAM \
+    SW_API_DESC(SW_API_VSI_ALLOC)  \
+    SW_API_DESC(SW_API_VSI_FREE)  \
+    SW_API_DESC(SW_API_PORT_VSI_SET)  \
+    SW_API_DESC(SW_API_PORT_VSI_GET)  \
+    SW_API_DESC(SW_API_PORT_VLAN_VSI_SET)  \
+    SW_API_DESC(SW_API_PORT_VLAN_VSI_GET)  \
+    SW_API_DESC(SW_API_VSI_TBL_DUMP) \
+    SW_API_DESC(SW_API_VSI_NEWADDR_LRN_GET) \
+    SW_API_DESC(SW_API_VSI_NEWADDR_LRN_SET) \
+    SW_API_DESC(SW_API_VSI_STAMOVE_SET) \
+    SW_API_DESC(SW_API_VSI_STAMOVE_GET) \
+    SW_API_DESC(SW_API_VSI_MEMBER_SET) \
+    SW_API_DESC(SW_API_VSI_MEMBER_GET) \
+    SW_API_DESC(SW_API_VSI_COUNTER_GET) \
+    SW_API_DESC(SW_API_VSI_COUNTER_CLEANUP)
+#else
+#define VSI_API \
+    SW_API_DEF(SW_API_VSI_ALLOC, ppe_vsi_alloc), \
+    SW_API_DEF(SW_API_VSI_FREE, ppe_vsi_free), \
+    SW_API_DEF(SW_API_PORT_VSI_SET, fal_port_vsi_set), \
+    SW_API_DEF(SW_API_PORT_VLAN_VSI_SET, ppe_port_vlan_vsi_set), \
+    SW_API_DEF(SW_API_PORT_VLAN_VSI_GET, ppe_port_vlan_vsi_get), \
+    SW_API_DEF(SW_API_VSI_TBL_DUMP, ppe_vsi_tbl_dump), \
+    SW_API_DEF(SW_API_VSI_NEWADDR_LRN_SET, fal_vsi_newaddr_lrn_set), \
+    SW_API_DEF(SW_API_VSI_STAMOVE_SET, fal_vsi_stamove_set), \
+    SW_API_DEF(SW_API_VSI_MEMBER_SET, fal_vsi_member_set), \
+    SW_API_DEF(SW_API_VSI_MEMBER_GET, fal_vsi_member_get),
+
+
+#define VSI_API_PARAM \
+    SW_API_DESC(SW_API_VSI_ALLOC)  \
+    SW_API_DESC(SW_API_VSI_FREE)  \
+    SW_API_DESC(SW_API_PORT_VSI_SET)  \
+    SW_API_DESC(SW_API_PORT_VLAN_VSI_SET)  \
+    SW_API_DESC(SW_API_PORT_VLAN_VSI_GET)  \
+    SW_API_DESC(SW_API_VSI_TBL_DUMP) \
+    SW_API_DESC(SW_API_VSI_NEWADDR_LRN_SET) \
+    SW_API_DESC(SW_API_VSI_STAMOVE_SET) \
+    SW_API_DESC(SW_API_VSI_MEMBER_SET) \
+    SW_API_DESC(SW_API_VSI_MEMBER_GET)
+#endif
+#else
+#define VSI_API
+#define VSI_API_PARAM
+#endif
+
+#ifdef IN_QM
+#ifndef IN_QM_MINI
+#define QM_API \
+    SW_API_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_SET, fal_ucast_queue_base_profile_set), \
+    SW_API_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_GET, fal_ucast_queue_base_profile_get), \
+    SW_API_DEF(SW_API_UCAST_PRIORITY_CLASS_SET, fal_ucast_priority_class_set), \
+    SW_API_DEF(SW_API_UCAST_PRIORITY_CLASS_GET, fal_ucast_priority_class_get), \
+    SW_API_DEF(SW_API_MCAST_PRIORITY_CLASS_SET, fal_port_mcast_priority_class_set), \
+    SW_API_DEF(SW_API_MCAST_PRIORITY_CLASS_GET, fal_port_mcast_priority_class_get), \
+    SW_API_DEF(SW_API_QUEUE_FLUSH, fal_queue_flush), \
+    SW_API_DEF(SW_API_UCAST_HASH_MAP_SET, fal_ucast_hash_map_set), \
+    SW_API_DEF(SW_API_UCAST_HASH_MAP_GET, fal_ucast_hash_map_get), \
+    SW_API_DEF(SW_API_UCAST_DFLT_HASH_MAP_SET, fal_ucast_default_hash_set), \
+    SW_API_DEF(SW_API_UCAST_DFLT_HASH_MAP_GET, fal_ucast_default_hash_get), \
+    SW_API_DEF(SW_API_MCAST_CPUCODE_CLASS_SET, fal_mcast_cpu_code_class_set), \
+    SW_API_DEF(SW_API_MCAST_CPUCODE_CLASS_GET, fal_mcast_cpu_code_class_get), \
+    SW_API_DEF(SW_API_AC_CTRL_SET, fal_ac_ctrl_set), \
+    SW_API_DEF(SW_API_AC_CTRL_GET, fal_ac_ctrl_get), \
+    SW_API_DEF(SW_API_AC_PRE_BUFFER_SET, fal_ac_prealloc_buffer_set), \
+    SW_API_DEF(SW_API_AC_PRE_BUFFER_GET, fal_ac_prealloc_buffer_get), \
+    SW_API_DEF(SW_API_QUEUE_GROUP_SET, fal_ac_queue_group_set), \
+    SW_API_DEF(SW_API_QUEUE_GROUP_GET, fal_ac_queue_group_get), \
+    SW_API_DEF(SW_API_STATIC_THRESH_SET, fal_ac_static_threshold_set), \
+    SW_API_DEF(SW_API_STATIC_THRESH_GET, fal_ac_static_threshold_get), \
+    SW_API_DEF(SW_API_DYNAMIC_THRESH_SET, fal_ac_dynamic_threshold_set), \
+    SW_API_DEF(SW_API_DYNAMIC_THRESH_GET, fal_ac_dynamic_threshold_get), \
+    SW_API_DEF(SW_API_GOURP_BUFFER_SET, fal_ac_group_buffer_set), \
+    SW_API_DEF(SW_API_GOURP_BUFFER_GET, fal_ac_group_buffer_get), \
+    SW_API_DEF(SW_API_QUEUE_CNT_CTRL_GET, fal_queue_counter_ctrl_get), \
+    SW_API_DEF(SW_API_QUEUE_CNT_CTRL_SET, fal_queue_counter_ctrl_set), \
+    SW_API_DEF(SW_API_QUEUE_CNT_GET, fal_queue_counter_get), \
+    SW_API_DEF(SW_API_QUEUE_CNT_CLEANUP, fal_queue_counter_cleanup), \
+    SW_API_DEF(SW_API_QM_ENQUEUE_CTRL_SET, fal_qm_enqueue_ctrl_set), \
+    SW_API_DEF(SW_API_QM_ENQUEUE_CTRL_GET, fal_qm_enqueue_ctrl_get), \
+    SW_API_DEF(SW_API_QM_SOURCE_PROFILE_SET, fal_qm_port_source_profile_set), \
+    SW_API_DEF(SW_API_QM_SOURCE_PROFILE_GET, fal_qm_port_source_profile_get),
+
+#define QM_API_PARAM \
+    SW_API_DESC(SW_API_UCAST_QUEUE_BASE_PROFILE_SET) \
+    SW_API_DESC(SW_API_UCAST_QUEUE_BASE_PROFILE_GET) \
+    SW_API_DESC(SW_API_UCAST_PRIORITY_CLASS_SET) \
+    SW_API_DESC(SW_API_UCAST_PRIORITY_CLASS_GET) \
+    SW_API_DESC(SW_API_MCAST_PRIORITY_CLASS_SET) \
+    SW_API_DESC(SW_API_MCAST_PRIORITY_CLASS_GET) \
+    SW_API_DESC(SW_API_QUEUE_FLUSH) \
+    SW_API_DESC(SW_API_UCAST_HASH_MAP_SET) \
+    SW_API_DESC(SW_API_UCAST_HASH_MAP_GET) \
+    SW_API_DESC(SW_API_UCAST_DFLT_HASH_MAP_SET) \
+    SW_API_DESC(SW_API_UCAST_DFLT_HASH_MAP_GET) \
+    SW_API_DESC(SW_API_MCAST_CPUCODE_CLASS_SET) \
+    SW_API_DESC(SW_API_MCAST_CPUCODE_CLASS_GET) \
+    SW_API_DESC(SW_API_AC_CTRL_SET) \
+    SW_API_DESC(SW_API_AC_CTRL_GET) \
+    SW_API_DESC(SW_API_AC_PRE_BUFFER_SET) \
+    SW_API_DESC(SW_API_AC_PRE_BUFFER_GET) \
+    SW_API_DESC(SW_API_QUEUE_GROUP_SET) \
+    SW_API_DESC(SW_API_QUEUE_GROUP_GET) \
+    SW_API_DESC(SW_API_STATIC_THRESH_SET) \
+    SW_API_DESC(SW_API_STATIC_THRESH_GET) \
+    SW_API_DESC(SW_API_DYNAMIC_THRESH_SET) \
+    SW_API_DESC(SW_API_DYNAMIC_THRESH_GET) \
+    SW_API_DESC(SW_API_GOURP_BUFFER_SET) \
+    SW_API_DESC(SW_API_GOURP_BUFFER_GET) \
+    SW_API_DESC(SW_API_QUEUE_CNT_CTRL_GET) \
+    SW_API_DESC(SW_API_QUEUE_CNT_CTRL_SET) \
+    SW_API_DESC(SW_API_QUEUE_CNT_GET) \
+    SW_API_DESC(SW_API_QUEUE_CNT_CLEANUP) \
+    SW_API_DESC(SW_API_QM_ENQUEUE_CTRL_SET) \
+    SW_API_DESC(SW_API_QM_ENQUEUE_CTRL_GET) \
+    SW_API_DESC(SW_API_QM_SOURCE_PROFILE_SET) \
+    SW_API_DESC(SW_API_QM_SOURCE_PROFILE_GET)
+#else
+#define QM_API \
+    SW_API_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_SET, fal_ucast_queue_base_profile_set), \
+    SW_API_DEF(SW_API_QUEUE_FLUSH, fal_queue_flush), \
+    SW_API_DEF(SW_API_AC_CTRL_SET, fal_ac_ctrl_set), \
+    SW_API_DEF(SW_API_AC_PRE_BUFFER_SET, fal_ac_prealloc_buffer_set), \
+    SW_API_DEF(SW_API_QUEUE_GROUP_SET, fal_ac_queue_group_set), \
+    SW_API_DEF(SW_API_STATIC_THRESH_SET, fal_ac_static_threshold_set), \
+    SW_API_DEF(SW_API_DYNAMIC_THRESH_SET, fal_ac_dynamic_threshold_set), \
+    SW_API_DEF(SW_API_GOURP_BUFFER_SET, fal_ac_group_buffer_set), \
+    SW_API_DEF(SW_API_QM_ENQUEUE_CTRL_SET, fal_qm_enqueue_ctrl_set),
+
+#define QM_API_PARAM \
+    SW_API_DESC(SW_API_UCAST_QUEUE_BASE_PROFILE_SET) \
+    SW_API_DESC(SW_API_QUEUE_FLUSH) \
+    SW_API_DESC(SW_API_AC_CTRL_SET) \
+    SW_API_DESC(SW_API_AC_PRE_BUFFER_SET) \
+    SW_API_DESC(SW_API_QUEUE_GROUP_SET) \
+    SW_API_DESC(SW_API_STATIC_THRESH_SET) \
+    SW_API_DESC(SW_API_DYNAMIC_THRESH_SET) \
+    SW_API_DESC(SW_API_GOURP_BUFFER_SET) \
+    SW_API_DESC(SW_API_QM_ENQUEUE_CTRL_SET)
+#endif
+#else
+#define QM_API
+#define QM_API_PARAM
+#endif
+
+
+#ifdef IN_PPPOE
+#define PPPOE_API \
+    SW_API_DEF(SW_API_PPPOE_CMD_SET, fal_pppoe_cmd_set), \
+    SW_API_DEF(SW_API_PPPOE_CMD_GET, fal_pppoe_cmd_get), \
+    SW_API_DEF(SW_API_PPPOE_STATUS_SET, fal_pppoe_status_set), \
+    SW_API_DEF(SW_API_PPPOE_STATUS_GET, fal_pppoe_status_get), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_ADD, fal_pppoe_session_add), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_DEL, fal_pppoe_session_del), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_GET, fal_pppoe_session_get), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, fal_pppoe_session_table_add), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, fal_pppoe_session_table_del), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_GET, fal_pppoe_session_table_get), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_ID_SET, fal_pppoe_session_id_set), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_ID_GET, fal_pppoe_session_id_get), \
+    SW_API_DEF(SW_API_RTD_PPPOE_EN_SET, fal_rtd_pppoe_en_set), \
+    SW_API_DEF(SW_API_RTD_PPPOE_EN_GET, fal_rtd_pppoe_en_get), \
+    SW_API_DEF(SW_API_PPPOE_EN_SET, fal_pppoe_l3intf_enable), \
+    SW_API_DEF(SW_API_PPPOE_EN_GET, fal_pppoe_l3intf_status_get),
+
+#define PPPOE_API_PARAM \
+    SW_API_DESC(SW_API_PPPOE_CMD_SET) \
+    SW_API_DESC(SW_API_PPPOE_CMD_GET) \
+    SW_API_DESC(SW_API_PPPOE_STATUS_SET) \
+    SW_API_DESC(SW_API_PPPOE_STATUS_GET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_ADD) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_DEL) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_GET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_ADD) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_DEL) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_GET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_ID_SET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_ID_GET) \
+    SW_API_DESC(SW_API_RTD_PPPOE_EN_SET) \
+    SW_API_DESC(SW_API_RTD_PPPOE_EN_GET) \
+    SW_API_DESC(SW_API_PPPOE_EN_SET) \
+    SW_API_DESC(SW_API_PPPOE_EN_GET)
+
+#else
+#define PPPOE_API
+#define PPPOE_API_PARAM
+#endif
+
+#ifdef IN_BM
+#ifndef IN_BM_MINI
+#define BM_API \
+    SW_API_DEF(SW_API_BM_CTRL_SET, fal_port_bm_ctrl_set), \
+    SW_API_DEF(SW_API_BM_CTRL_GET, fal_port_bm_ctrl_get), \
+    SW_API_DEF(SW_API_BM_PORTGROUP_MAP_SET, fal_port_bufgroup_map_set), \
+    SW_API_DEF(SW_API_BM_PORTGROUP_MAP_GET, fal_port_bufgroup_map_get), \
+    SW_API_DEF(SW_API_BM_GROUP_BUFFER_SET, fal_bm_bufgroup_buffer_set), \
+    SW_API_DEF(SW_API_BM_GROUP_BUFFER_GET, fal_bm_bufgroup_buffer_get), \
+    SW_API_DEF(SW_API_BM_PORT_RSVBUFFER_SET, fal_bm_port_reserved_buffer_set), \
+    SW_API_DEF(SW_API_BM_PORT_RSVBUFFER_GET, fal_bm_port_reserved_buffer_get), \
+    SW_API_DEF(SW_API_BM_STATIC_THRESH_SET, fal_bm_port_static_thresh_set), \
+    SW_API_DEF(SW_API_BM_STATIC_THRESH_GET, fal_bm_port_static_thresh_get), \
+    SW_API_DEF(SW_API_BM_DYNAMIC_THRESH_SET, fal_bm_port_dynamic_thresh_set), \
+    SW_API_DEF(SW_API_BM_DYNAMIC_THRESH_GET, fal_bm_port_dynamic_thresh_get), \
+    SW_API_DEF(SW_API_BM_PORT_COUNTER_GET, fal_bm_port_counter_get),
+
+#define BM_API_PARAM \
+    SW_API_DESC(SW_API_BM_CTRL_SET) \
+    SW_API_DESC(SW_API_BM_CTRL_GET) \
+    SW_API_DESC(SW_API_BM_PORTGROUP_MAP_SET) \
+    SW_API_DESC(SW_API_BM_PORTGROUP_MAP_GET) \
+    SW_API_DESC(SW_API_BM_GROUP_BUFFER_SET) \
+    SW_API_DESC(SW_API_BM_GROUP_BUFFER_GET) \
+    SW_API_DESC(SW_API_BM_PORT_RSVBUFFER_SET) \
+    SW_API_DESC(SW_API_BM_PORT_RSVBUFFER_GET) \
+    SW_API_DESC(SW_API_BM_STATIC_THRESH_SET) \
+    SW_API_DESC(SW_API_BM_STATIC_THRESH_GET) \
+    SW_API_DESC(SW_API_BM_DYNAMIC_THRESH_SET) \
+    SW_API_DESC(SW_API_BM_DYNAMIC_THRESH_GET) \
+    SW_API_DESC(SW_API_BM_PORT_COUNTER_GET)
+#else
+#define BM_API \
+    SW_API_DEF(SW_API_BM_CTRL_SET, fal_port_bm_ctrl_set), \
+    SW_API_DEF(SW_API_BM_PORTGROUP_MAP_SET, fal_port_bufgroup_map_set), \
+    SW_API_DEF(SW_API_BM_GROUP_BUFFER_SET, fal_bm_bufgroup_buffer_set), \
+    SW_API_DEF(SW_API_BM_PORT_RSVBUFFER_SET, fal_bm_port_reserved_buffer_set), \
+    SW_API_DEF(SW_API_BM_DYNAMIC_THRESH_SET, fal_bm_port_dynamic_thresh_set),
+
+#define BM_API_PARAM \
+    SW_API_DESC(SW_API_BM_CTRL_SET) \
+    SW_API_DESC(SW_API_BM_PORTGROUP_MAP_SET) \
+    SW_API_DESC(SW_API_BM_GROUP_BUFFER_SET) \
+    SW_API_DESC(SW_API_BM_PORT_RSVBUFFER_SET) \
+    SW_API_DESC(SW_API_BM_DYNAMIC_THRESH_SET)
+#endif
+#else
+#define BM_API
+#define BM_API_PARAM
+#endif
+
+/*qca808x_start*/
+#define REG_API \
+    SW_API_DEF(SW_API_PHY_GET, fal_phy_get), \
+	SW_API_DEF(SW_API_PHY_SET, fal_phy_set), \
+/*qca808x_end*/\
+    SW_API_DEF(SW_API_REG_GET, fal_reg_get), \
+    SW_API_DEF(SW_API_REG_SET, fal_reg_set), \
+    SW_API_DEF(SW_API_PSGMII_REG_GET, fal_psgmii_reg_get), \
+    SW_API_DEF(SW_API_PSGMII_REG_SET, fal_psgmii_reg_set), \
+    SW_API_DEF(SW_API_REG_FIELD_GET, fal_reg_field_get), \
+    SW_API_DEF(SW_API_REG_FIELD_SET, fal_reg_field_set), \
+    SW_API_DEF(SW_API_REG_DUMP, fal_reg_dump), \
+    SW_API_DEF(SW_API_DBG_REG_DUMP, fal_debug_reg_dump), \
+    SW_API_DEF(SW_API_DBG_PSGMII_SELF_TEST, fal_debug_psgmii_self_test), \
+    SW_API_DEF(SW_API_PHY_DUMP, fal_phy_dump), \
+    SW_API_DEF(SW_API_UNIPHY_REG_GET, fal_uniphy_reg_get), \
+    SW_API_DEF(SW_API_UNIPHY_REG_SET, fal_uniphy_reg_set),
+/*qca808x_start*/\
+/*end of REG_API*/
+#define REG_API_PARAM \
+    SW_API_DESC(SW_API_PHY_GET) \
+    SW_API_DESC(SW_API_PHY_SET) \
+/*qca808x_end*/\
+    SW_API_DESC(SW_API_REG_GET) \
+    SW_API_DESC(SW_API_REG_SET) \
+    SW_API_DESC(SW_API_PSGMII_REG_GET) \
+    SW_API_DESC(SW_API_PSGMII_REG_SET) \
+    SW_API_DESC(SW_API_REG_FIELD_GET) \
+    SW_API_DESC(SW_API_REG_FIELD_SET) \
+    SW_API_DESC(SW_API_REG_DUMP) \
+    SW_API_DESC(SW_API_DBG_REG_DUMP) \
+    SW_API_DESC(SW_API_DBG_PSGMII_SELF_TEST) \
+    SW_API_DESC(SW_API_PHY_DUMP) \
+    SW_API_DESC(SW_API_UNIPHY_REG_GET) \
+    SW_API_DESC(SW_API_UNIPHY_REG_SET)
+/*qca808x_start*/\
+/*end of REG_API_PARAM*/
+/*qca808x_end*/
+#ifdef IN_CTRLPKT
+#define CTRLPKT_API \
+    SW_API_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET, fal_mgmtctrl_ethtype_profile_set), \
+    SW_API_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_GET, fal_mgmtctrl_ethtype_profile_get), \
+    SW_API_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_SET, fal_mgmtctrl_rfdb_profile_set), \
+    SW_API_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_GET, fal_mgmtctrl_rfdb_profile_get), \
+    SW_API_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_ADD, fal_mgmtctrl_ctrlpkt_profile_add), \
+    SW_API_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_DEL, fal_mgmtctrl_ctrlpkt_profile_del), \
+    SW_API_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST, fal_mgmtctrl_ctrlpkt_profile_getfirst), \
+    SW_API_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT, fal_mgmtctrl_ctrlpkt_profile_getnext),
+
+#define CTRLPKT_API_PARAM \
+    SW_API_DESC(SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET) \
+    SW_API_DESC(SW_API_MGMTCTRL_ETHTYPE_PROFILE_GET) \
+    SW_API_DESC(SW_API_MGMTCTRL_RFDB_PROFILE_SET) \
+    SW_API_DESC(SW_API_MGMTCTRL_RFDB_PROFILE_GET) \
+    SW_API_DESC(SW_API_MGMTCTRL_CTRLPKT_PROFILE_ADD) \
+    SW_API_DESC(SW_API_MGMTCTRL_CTRLPKT_PROFILE_DEL) \
+    SW_API_DESC(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST) \
+    SW_API_DESC(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT)
+#else
+#define CTRLPKT_API
+#define CTRLPKT_API_PARAM
+#endif
+
+#ifdef IN_SERVCODE
+#define SERVCODE_API \
+    SW_API_DEF(SW_API_SERVCODE_CONFIG_SET, fal_servcode_config_set), \
+    SW_API_DEF(SW_API_SERVCODE_CONFIG_GET, fal_servcode_config_get), \
+    SW_API_DEF(SW_API_SERVCODE_LOOPCHECK_EN, fal_servcode_loopcheck_en), \
+    SW_API_DEF(SW_API_SERVCODE_LOOPCHECK_STATUS_GET, fal_servcode_loopcheck_status_get),
+
+#define SERVCODE_API_PARAM \
+    SW_API_DESC(SW_API_SERVCODE_CONFIG_SET) \
+    SW_API_DESC(SW_API_SERVCODE_CONFIG_GET) \
+    SW_API_DESC(SW_API_SERVCODE_LOOPCHECK_EN) \
+    SW_API_DESC(SW_API_SERVCODE_LOOPCHECK_STATUS_GET)
+#else
+#define SERVCODE_API
+#define SERVCODE_API_PARAM
+#endif
+
+#ifdef IN_RSS_HASH
+#define RSS_HASH_API \
+    SW_API_DEF(SW_API_RSS_HASH_CONFIG_SET, fal_rss_hash_config_set), \
+    SW_API_DEF(SW_API_RSS_HASH_CONFIG_GET, fal_rss_hash_config_get),
+
+#define RSS_HASH_API_PARAM \
+    SW_API_DESC(SW_API_RSS_HASH_CONFIG_SET) \
+    SW_API_DESC(SW_API_RSS_HASH_CONFIG_GET)
+#else
+#define RSS_HASH_API
+#define RSS_HASH_API_PARAM
+#endif
+
+#ifdef IN_SHAPER
+#ifndef IN_SHAPER_MINI
+#define SHAPER_API \
+    SW_API_DEF(SW_API_PORT_SHAPER_TIMESLOT_SET, fal_port_shaper_timeslot_set), \
+    SW_API_DEF(SW_API_PORT_SHAPER_TIMESLOT_GET, fal_port_shaper_timeslot_get), \
+    SW_API_DEF(SW_API_FLOW_SHAPER_TIMESLOT_SET, fal_flow_shaper_timeslot_set), \
+    SW_API_DEF(SW_API_FLOW_SHAPER_TIMESLOT_GET, fal_flow_shaper_timeslot_get), \
+    SW_API_DEF(SW_API_QUEUE_SHAPER_TIMESLOT_SET, fal_queue_shaper_timeslot_set), \
+    SW_API_DEF(SW_API_QUEUE_SHAPER_TIMESLOT_GET, fal_queue_shaper_timeslot_get), \
+    SW_API_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_SET, fal_port_shaper_token_number_set), \
+    SW_API_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_GET, fal_port_shaper_token_number_get), \
+    SW_API_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET, fal_flow_shaper_token_number_set), \
+    SW_API_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_GET, fal_flow_shaper_token_number_get), \
+    SW_API_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET, fal_queue_shaper_token_number_set), \
+    SW_API_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_GET, fal_queue_shaper_token_number_get), \
+    SW_API_DEF(SW_API_PORT_SHAPER_SET, fal_port_shaper_set), \
+    SW_API_DEF(SW_API_PORT_SHAPER_GET,fal_port_shaper_get), \
+    SW_API_DEF(SW_API_FLOW_SHAPER_SET, fal_flow_shaper_set), \
+    SW_API_DEF(SW_API_FLOW_SHAPER_GET,fal_flow_shaper_get), \
+    SW_API_DEF(SW_API_QUEUE_SHAPER_SET, fal_queue_shaper_set), \
+    SW_API_DEF(SW_API_QUEUE_SHAPER_GET,fal_queue_shaper_get), \
+    SW_API_DEF(SW_API_SHAPER_IPG_PRE_SET, fal_shaper_ipg_preamble_length_set), \
+    SW_API_DEF(SW_API_SHAPER_IPG_PRE_GET,fal_shaper_ipg_preamble_length_get),
+
+
+#define SHAPER_API_PARAM \
+    SW_API_DESC(SW_API_PORT_SHAPER_TIMESLOT_SET)  \
+    SW_API_DESC(SW_API_PORT_SHAPER_TIMESLOT_GET)  \
+    SW_API_DESC(SW_API_FLOW_SHAPER_TIMESLOT_SET)  \
+    SW_API_DESC(SW_API_FLOW_SHAPER_TIMESLOT_GET)  \
+    SW_API_DESC(SW_API_QUEUE_SHAPER_TIMESLOT_SET)  \
+    SW_API_DESC(SW_API_QUEUE_SHAPER_TIMESLOT_GET)  \
+    SW_API_DESC(SW_API_PORT_SHAPER_TOKEN_NUMBER_SET) \
+    SW_API_DESC(SW_API_PORT_SHAPER_TOKEN_NUMBER_GET) \
+    SW_API_DESC(SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET) \
+    SW_API_DESC(SW_API_FLOW_SHAPER_TOKEN_NUMBER_GET) \
+    SW_API_DESC(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET) \
+    SW_API_DESC(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_GET) \
+    SW_API_DESC(SW_API_PORT_SHAPER_SET) \
+    SW_API_DESC(SW_API_PORT_SHAPER_GET) \
+    SW_API_DESC(SW_API_FLOW_SHAPER_SET) \
+    SW_API_DESC(SW_API_FLOW_SHAPER_GET) \
+    SW_API_DESC(SW_API_QUEUE_SHAPER_SET) \
+    SW_API_DESC(SW_API_QUEUE_SHAPER_GET) \
+    SW_API_DESC(SW_API_SHAPER_IPG_PRE_SET) \
+    SW_API_DESC(SW_API_SHAPER_IPG_PRE_GET)
+#else
+#define SHAPER_API \
+    SW_API_DEF(SW_API_PORT_SHAPER_TIMESLOT_SET, fal_port_shaper_timeslot_set), \
+    SW_API_DEF(SW_API_FLOW_SHAPER_TIMESLOT_SET, fal_flow_shaper_timeslot_set), \
+    SW_API_DEF(SW_API_QUEUE_SHAPER_TIMESLOT_SET, fal_queue_shaper_timeslot_set), \
+    SW_API_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_SET, fal_port_shaper_token_number_set), \
+    SW_API_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET, fal_flow_shaper_token_number_set), \
+    SW_API_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET, fal_queue_shaper_token_number_set), \
+    SW_API_DEF(SW_API_PORT_SHAPER_SET, fal_port_shaper_set), \
+    SW_API_DEF(SW_API_FLOW_SHAPER_SET, fal_flow_shaper_set), \
+    SW_API_DEF(SW_API_QUEUE_SHAPER_SET, fal_queue_shaper_set), \
+    SW_API_DEF(SW_API_QUEUE_SHAPER_GET,fal_queue_shaper_get), \
+    SW_API_DEF(SW_API_SHAPER_IPG_PRE_SET, fal_shaper_ipg_preamble_length_set),
+
+
+#define SHAPER_API_PARAM \
+    SW_API_DESC(SW_API_PORT_SHAPER_TIMESLOT_SET)  \
+    SW_API_DESC(SW_API_FLOW_SHAPER_TIMESLOT_SET)  \
+    SW_API_DESC(SW_API_QUEUE_SHAPER_TIMESLOT_SET)  \
+    SW_API_DESC(SW_API_PORT_SHAPER_TOKEN_NUMBER_SET) \
+    SW_API_DESC(SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET) \
+    SW_API_DESC(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET) \
+    SW_API_DESC(SW_API_PORT_SHAPER_SET) \
+    SW_API_DESC(SW_API_FLOW_SHAPER_SET) \
+    SW_API_DESC(SW_API_QUEUE_SHAPER_SET) \
+    SW_API_DESC(SW_API_QUEUE_SHAPER_GET) \
+    SW_API_DESC(SW_API_SHAPER_IPG_PRE_SET)
+#endif
+#else
+#define SHAPER_API
+#define SHAPER_API_PARAM
+#endif
+
+#ifdef IN_POLICER
+#ifndef IN_POLICER_MINI
+#define POLICER_API \
+    SW_API_DEF(SW_API_POLICER_TIMESLOT_SET, fal_policer_timeslot_set), \
+    SW_API_DEF(SW_API_POLICER_TIMESLOT_GET, fal_policer_timeslot_get), \
+    SW_API_DEF(SW_API_POLICER_PORT_COUNTER_GET, fal_port_policer_counter_get), \
+    SW_API_DEF(SW_API_POLICER_ACL_COUNTER_GET, fal_acl_policer_counter_get), \
+    SW_API_DEF(SW_API_POLICER_COMPENSATION_SET, fal_port_policer_compensation_byte_set), \
+    SW_API_DEF(SW_API_POLICER_COMPENSATION_GET, fal_port_policer_compensation_byte_get), \
+    SW_API_DEF(SW_API_POLICER_PORT_ENTRY_SET, fal_port_policer_entry_set), \
+    SW_API_DEF(SW_API_POLICER_PORT_ENTRY_GET, fal_port_policer_entry_get), \
+    SW_API_DEF(SW_API_POLICER_ACL_ENTRY_SET, fal_acl_policer_entry_set), \
+    SW_API_DEF(SW_API_POLICER_ACL_ENTRY_GET,fal_acl_policer_entry_get), \
+    SW_API_DEF(SW_API_POLICER_GLOBAL_COUNTER_GET, fal_policer_global_counter_get), \
+    SW_API_DEF(SW_API_POLICER_BYPASS_EN_SET, fal_policer_bypass_en_set), \
+    SW_API_DEF(SW_API_POLICER_BYPASS_EN_GET, fal_policer_bypass_en_get),
+
+#define POLICER_API_PARAM \
+    SW_API_DESC(SW_API_POLICER_TIMESLOT_SET)  \
+    SW_API_DESC(SW_API_POLICER_TIMESLOT_GET)  \
+    SW_API_DESC(SW_API_POLICER_PORT_COUNTER_GET) \
+    SW_API_DESC(SW_API_POLICER_ACL_COUNTER_GET) \
+    SW_API_DESC(SW_API_POLICER_COMPENSATION_SET) \
+    SW_API_DESC(SW_API_POLICER_COMPENSATION_GET) \
+    SW_API_DESC(SW_API_POLICER_PORT_ENTRY_SET) \
+    SW_API_DESC(SW_API_POLICER_PORT_ENTRY_GET) \
+    SW_API_DESC(SW_API_POLICER_ACL_ENTRY_SET) \
+    SW_API_DESC(SW_API_POLICER_ACL_ENTRY_GET) \
+    SW_API_DESC(SW_API_POLICER_GLOBAL_COUNTER_GET) \
+    SW_API_DESC(SW_API_POLICER_BYPASS_EN_SET) \
+    SW_API_DESC(SW_API_POLICER_BYPASS_EN_GET)
+#else
+#define POLICER_API \
+    SW_API_DEF(SW_API_POLICER_TIMESLOT_SET, fal_policer_timeslot_set), \
+    SW_API_DEF(SW_API_POLICER_COMPENSATION_SET, fal_port_policer_compensation_byte_set),
+
+
+#define POLICER_API_PARAM \
+    SW_API_DESC(SW_API_POLICER_TIMESLOT_SET)  \
+    SW_API_DESC(SW_API_POLICER_COMPENSATION_SET)
+#endif
+#else
+#define POLICER_API
+#define POLICER_API_PARAM
+#endif
+
+#ifdef IN_PTP
+#define PTP_API \
+    SW_API_DEF(SW_API_PTP_CONFIG_SET, fal_ptp_config_set), \
+    SW_API_DEF(SW_API_PTP_CONFIG_GET, fal_ptp_config_get), \
+    SW_API_DEF(SW_API_PTP_REFERENCE_CLOCK_SET, fal_ptp_reference_clock_set), \
+    SW_API_DEF(SW_API_PTP_REFERENCE_CLOCK_GET, fal_ptp_reference_clock_get), \
+    SW_API_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_SET, fal_ptp_rx_timestamp_mode_set), \
+    SW_API_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_GET, fal_ptp_rx_timestamp_mode_get), \
+    SW_API_DEF(SW_API_PTP_TIMESTAMP_GET, fal_ptp_timestamp_get), \
+    SW_API_DEF(SW_API_PTP_PKT_TIMESTAMP_SET, fal_ptp_pkt_timestamp_set), \
+    SW_API_DEF(SW_API_PTP_PKT_TIMESTAMP_GET, fal_ptp_pkt_timestamp_get), \
+    SW_API_DEF(SW_API_PTP_GRANDMASTER_MODE_SET, fal_ptp_grandmaster_mode_set), \
+    SW_API_DEF(SW_API_PTP_GRANDMASTER_MODE_GET, fal_ptp_grandmaster_mode_get), \
+    SW_API_DEF(SW_API_PTP_RTC_TIME_SET, fal_ptp_rtc_time_set), \
+    SW_API_DEF(SW_API_PTP_RTC_TIME_GET, fal_ptp_rtc_time_get), \
+    SW_API_DEF(SW_API_PTP_RTC_TIME_CLEAR, fal_ptp_rtc_time_clear), \
+    SW_API_DEF(SW_API_PTP_RTC_ADJTIME_SET, fal_ptp_rtc_adjtime_set), \
+    SW_API_DEF(SW_API_PTP_RTC_ADJFREQ_SET, fal_ptp_rtc_adjfreq_set), \
+    SW_API_DEF(SW_API_PTP_RTC_ADJFREQ_GET, fal_ptp_rtc_adjfreq_get), \
+    SW_API_DEF(SW_API_PTP_LINK_DELAY_SET, fal_ptp_link_delay_set), \
+    SW_API_DEF(SW_API_PTP_LINK_DELAY_GET, fal_ptp_link_delay_get), \
+    SW_API_DEF(SW_API_PTP_SECURITY_SET, fal_ptp_security_set), \
+    SW_API_DEF(SW_API_PTP_SECURITY_GET, fal_ptp_security_get), \
+    SW_API_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_SET, fal_ptp_pps_signal_control_set), \
+    SW_API_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_GET, fal_ptp_pps_signal_control_get), \
+    SW_API_DEF(SW_API_PTP_RX_CRC_RECALC_SET, fal_ptp_rx_crc_recalc_enable), \
+    SW_API_DEF(SW_API_PTP_RX_CRC_RECALC_GET, fal_ptp_rx_crc_recalc_status_get), \
+    SW_API_DEF(SW_API_PTP_ASYM_CORRECTION_SET, fal_ptp_asym_correction_set), \
+    SW_API_DEF(SW_API_PTP_ASYM_CORRECTION_GET, fal_ptp_asym_correction_get), \
+    SW_API_DEF(SW_API_PTP_OUTPUT_WAVEFORM_SET, fal_ptp_output_waveform_set), \
+    SW_API_DEF(SW_API_PTP_OUTPUT_WAVEFORM_GET, fal_ptp_output_waveform_get), \
+    SW_API_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_SET, fal_ptp_rtc_time_snapshot_enable), \
+    SW_API_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_GET, fal_ptp_rtc_time_snapshot_status_get), \
+    SW_API_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_SET, \
+		    fal_ptp_increment_sync_from_clock_enable), \
+    SW_API_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_GET, \
+		    fal_ptp_increment_sync_from_clock_status_get), \
+    SW_API_DEF(SW_API_PTP_TOD_UART_SET, fal_ptp_tod_uart_set), \
+    SW_API_DEF(SW_API_PTP_TOD_UART_GET, fal_ptp_tod_uart_get), \
+    SW_API_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET, fal_ptp_enhanced_timestamp_engine_set), \
+    SW_API_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET, fal_ptp_enhanced_timestamp_engine_get), \
+    SW_API_DEF(SW_API_PTP_TRIGGER_SET, fal_ptp_trigger_set), \
+    SW_API_DEF(SW_API_PTP_TRIGGER_GET, fal_ptp_trigger_get), \
+    SW_API_DEF(SW_API_PTP_CAPTURE_SET, fal_ptp_capture_set), \
+    SW_API_DEF(SW_API_PTP_CAPTURE_GET, fal_ptp_capture_get), \
+    SW_API_DEF(SW_API_PTP_INTERRUPT_SET, fal_ptp_interrupt_set), \
+    SW_API_DEF(SW_API_PTP_INTERRUPT_GET, fal_ptp_interrupt_get),
+
+#define PTP_API_PARAM \
+    SW_API_DESC(SW_API_PTP_CONFIG_SET) \
+    SW_API_DESC(SW_API_PTP_CONFIG_GET) \
+    SW_API_DESC(SW_API_PTP_REFERENCE_CLOCK_SET) \
+    SW_API_DESC(SW_API_PTP_REFERENCE_CLOCK_GET) \
+    SW_API_DESC(SW_API_PTP_RX_TIMESTAMP_MODE_SET) \
+    SW_API_DESC(SW_API_PTP_RX_TIMESTAMP_MODE_GET) \
+    SW_API_DESC(SW_API_PTP_TIMESTAMP_GET) \
+    SW_API_DESC(SW_API_PTP_PKT_TIMESTAMP_SET) \
+    SW_API_DESC(SW_API_PTP_PKT_TIMESTAMP_GET) \
+    SW_API_DESC(SW_API_PTP_GRANDMASTER_MODE_SET) \
+    SW_API_DESC(SW_API_PTP_GRANDMASTER_MODE_GET) \
+    SW_API_DESC(SW_API_PTP_RTC_TIME_SET) \
+    SW_API_DESC(SW_API_PTP_RTC_TIME_GET) \
+    SW_API_DESC(SW_API_PTP_RTC_TIME_CLEAR) \
+    SW_API_DESC(SW_API_PTP_RTC_ADJTIME_SET) \
+    SW_API_DESC(SW_API_PTP_RTC_ADJFREQ_SET) \
+    SW_API_DESC(SW_API_PTP_RTC_ADJFREQ_GET) \
+    SW_API_DESC(SW_API_PTP_LINK_DELAY_SET) \
+    SW_API_DESC(SW_API_PTP_LINK_DELAY_GET) \
+    SW_API_DESC(SW_API_PTP_SECURITY_SET) \
+    SW_API_DESC(SW_API_PTP_SECURITY_GET) \
+    SW_API_DESC(SW_API_PTP_PPS_SIGNAL_CONTROL_SET) \
+    SW_API_DESC(SW_API_PTP_PPS_SIGNAL_CONTROL_GET) \
+    SW_API_DESC(SW_API_PTP_RX_CRC_RECALC_SET) \
+    SW_API_DESC(SW_API_PTP_RX_CRC_RECALC_GET) \
+    SW_API_DESC(SW_API_PTP_ASYM_CORRECTION_SET) \
+    SW_API_DESC(SW_API_PTP_ASYM_CORRECTION_GET) \
+    SW_API_DESC(SW_API_PTP_OUTPUT_WAVEFORM_SET) \
+    SW_API_DESC(SW_API_PTP_OUTPUT_WAVEFORM_GET) \
+    SW_API_DESC(SW_API_PTP_RTC_TIME_SNAPSHOT_SET) \
+    SW_API_DESC(SW_API_PTP_RTC_TIME_SNAPSHOT_GET) \
+    SW_API_DESC(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_SET) \
+    SW_API_DESC(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_GET) \
+    SW_API_DESC(SW_API_PTP_TOD_UART_SET) \
+    SW_API_DESC(SW_API_PTP_TOD_UART_GET) \
+    SW_API_DESC(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET) \
+    SW_API_DESC(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET) \
+    SW_API_DESC(SW_API_PTP_TRIGGER_SET) \
+    SW_API_DESC(SW_API_PTP_TRIGGER_GET) \
+    SW_API_DESC(SW_API_PTP_CAPTURE_SET) \
+    SW_API_DESC(SW_API_PTP_CAPTURE_GET) \
+    SW_API_DESC(SW_API_PTP_INTERRUPT_SET) \
+    SW_API_DESC(SW_API_PTP_INTERRUPT_GET)
+#else
+#define PTP_API
+#define PTP_API_PARAM
+#endif
+
+#ifdef IN_SFP
+#define SFP_API \
+    SW_API_DEF(SW_API_SFP_DATA_GET, fal_sfp_eeprom_data_get), \
+    SW_API_DEF(SW_API_SFP_DATA_SET, fal_sfp_eeprom_data_set), \
+    SW_API_DEF(SW_API_SFP_DEV_TYPE_GET, fal_sfp_device_type_get), \
+    SW_API_DEF(SW_API_SFP_TRANSC_CODE_GET, fal_sfp_transceiver_code_get), \
+    SW_API_DEF(SW_API_SFP_RATE_ENCODE_GET, fal_sfp_rate_encode_get), \
+    SW_API_DEF(SW_API_SFP_LINK_LENGTH_GET, fal_sfp_link_length_get), \
+    SW_API_DEF(SW_API_SFP_VENDOR_INFO_GET, fal_sfp_vendor_info_get), \
+    SW_API_DEF(SW_API_SFP_LASER_WAVELENGTH_GET, fal_sfp_laser_wavelength_get), \
+    SW_API_DEF(SW_API_SFP_OPTION_GET, fal_sfp_option_get), \
+    SW_API_DEF(SW_API_SFP_CTRL_RATE_GET, fal_sfp_ctrl_rate_get), \
+    SW_API_DEF(SW_API_SFP_ENHANCED_CFG_GET, fal_sfp_enhanced_cfg_get), \
+    SW_API_DEF(SW_API_SFP_DIAG_THRESHOLD_GET, fal_sfp_diag_internal_threshold_get), \
+    SW_API_DEF(SW_API_SFP_DIAG_CAL_CONST_GET, fal_sfp_diag_extenal_calibration_const_get), \
+    SW_API_DEF(SW_API_SFP_DIAG_REALTIME_GET, fal_sfp_diag_realtime_get), \
+    SW_API_DEF(SW_API_SFP_DIAG_CTRL_STATUS_GET, fal_sfp_diag_ctrl_status_get), \
+    SW_API_DEF(SW_API_SFP_DIAG_ALARM_WARN_FLAG_GET, fal_sfp_diag_alarm_warning_flag_get), \
+    SW_API_DEF(SW_API_SFP_CHECKCODE_GET, fal_sfp_checkcode_get),
+
+#define SFP_API_PARAM \
+    SW_API_DESC(SW_API_SFP_DATA_GET) \
+    SW_API_DESC(SW_API_SFP_DATA_SET) \
+    SW_API_DESC(SW_API_SFP_DEV_TYPE_GET) \
+    SW_API_DESC(SW_API_SFP_TRANSC_CODE_GET) \
+    SW_API_DESC(SW_API_SFP_RATE_ENCODE_GET) \
+    SW_API_DESC(SW_API_SFP_LINK_LENGTH_GET) \
+    SW_API_DESC(SW_API_SFP_VENDOR_INFO_GET) \
+    SW_API_DESC(SW_API_SFP_LASER_WAVELENGTH_GET) \
+    SW_API_DESC(SW_API_SFP_OPTION_GET) \
+    SW_API_DESC(SW_API_SFP_CTRL_RATE_GET) \
+    SW_API_DESC(SW_API_SFP_ENHANCED_CFG_GET) \
+    SW_API_DESC(SW_API_SFP_DIAG_THRESHOLD_GET) \
+    SW_API_DESC(SW_API_SFP_DIAG_CAL_CONST_GET) \
+    SW_API_DESC(SW_API_SFP_DIAG_REALTIME_GET) \
+    SW_API_DESC(SW_API_SFP_DIAG_CTRL_STATUS_GET) \
+    SW_API_DESC(SW_API_SFP_DIAG_ALARM_WARN_FLAG_GET) \
+    SW_API_DESC(SW_API_SFP_CHECKCODE_GET)
+#else
+#define SFP_API
+#define SFP_API_PARAM
+#endif
+
+/*qca808x_start*/
+#define SSDK_API \
+/*qca808x_end*/\
+    SW_API_DEF(SW_API_SWITCH_RESET, fal_reset), \
+    SW_API_DEF(SW_API_SSDK_CFG, fal_ssdk_cfg), \
+    SW_API_DEF(SW_API_MODULE_FUNC_CTRL_SET, fal_module_func_ctrl_set), \
+    SW_API_DEF(SW_API_MODULE_FUNC_CTRL_GET, fal_module_func_ctrl_get), \
+/*qca808x_start*/\
+    PORTCONTROL_API \
+/*qca808x_end*/\
+    VLAN_API \
+    PORTVLAN_API \
+    FDB_API \
+    ACL_API \
+    QOS_API \
+    IGMP_API \
+    LEAKY_API \
+    MIRROR_API \
+    RATE_API \
+    STP_API \
+    MIB_API \
+    MISC_API \
+    LED_API \
+    COSMAP_API \
+    SEC_API  \
+    IP_API \
+    NAT_API \
+    FLOW_API \
+    TRUNK_API \
+    INTERFACECTRL_API \
+    VSI_API \
+    QM_API \
+    BM_API \
+    PPPOE_API \
+/*qca808x_start*/\
+    REG_API \
+/*qca808x_end*/\
+    CTRLPKT_API \
+    SERVCODE_API \
+    RSS_HASH_API \
+    POLICER_API \
+    SHAPER_API \
+    PTP_API \
+    SFP_API \
+/*qca808x_start*/\
+    SW_API_DEF(SW_API_MAX, NULL),
+
+
+#define SSDK_PARAM  \
+/*qca808x_end*/\
+    SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
+    SW_PARAM_DEF(SW_API_MODULE_FUNC_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MODULE_FUNC_CTRL_SET, SW_MODULE, 4, SW_PARAM_IN, "Module"), \
+    SW_PARAM_DEF(SW_API_MODULE_FUNC_CTRL_SET, SW_FUNC_CTRL, sizeof(fal_func_ctrl_t), \
+		    SW_PARAM_PTR|SW_PARAM_IN, "Function bitmap"), \
+    SW_PARAM_DEF(SW_API_MODULE_FUNC_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_MODULE_FUNC_CTRL_GET, SW_MODULE, 4, SW_PARAM_IN, "Module"), \
+    SW_PARAM_DEF(SW_API_MODULE_FUNC_CTRL_GET, SW_FUNC_CTRL, sizeof(fal_func_ctrl_t), \
+		    SW_PARAM_PTR|SW_PARAM_OUT, "Function bitmap"), \
+    MIB_API_PARAM \
+    LEAKY_API_PARAM \
+    MISC_API_PARAM \
+    IGMP_API_PARAM \
+    MIRROR_API_PARAM \
+/*qca808x_start*/\
+    PORTCONTROL_API_PARAM \
+/*qca808x_end*/\
+    PORTVLAN_API_PARAM \
+    VLAN_API_PARAM \
+    FDB_API_PARAM \
+    QOS_API_PARAM \
+    RATE_API_PARAM \
+    STP_API_PARAM \
+    ACL_API_PARAM \
+    LED_API_PARAM \
+    COSMAP_API_PARAM \
+    SEC_API_PARAM \
+    IP_API_PARAM \
+    NAT_API_PARAM \
+    FLOW_API_PARAM \
+    TRUNK_API_PARAM \
+    INTERFACECTRL_API_PARAM \
+    VSI_API_PARAM \
+    QM_API_PARAM \
+    BM_API_PARAM \
+    PPPOE_API_PARAM \
+/*qca808x_start*/\
+    REG_API_PARAM \
+/*qca808x_end*/\
+    CTRLPKT_API_PARAM \
+    SERVCODE_API_PARAM \
+    RSS_HASH_API_PARAM \
+    POLICER_API_PARAM \
+    SHAPER_API_PARAM \
+    PTP_API_PARAM \
+    SFP_API_PARAM \
+/*qca808x_start*/\
+    SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _FAL_API_H_ */
+/*qca808x_end*/
diff --git a/qca-ssdk/include/fal/fal_bm.h b/qca-ssdk/include/fal/fal_bm.h
new file mode 100755
index 0000000..0f75c3b
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_bm.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_qos FAL_QM
+ * @{
+ */
+#ifndef _FAL_BM_H_
+#define _FAL_BM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+typedef struct
+{
+	a_uint16_t max_thresh;  /* Static Maximum threshold */
+	a_uint16_t resume_off; /*resume offset */
+} fal_bm_static_cfg_t;
+
+typedef struct
+{
+	a_uint8_t weight; /* port weight in the shared group */
+	a_uint16_t shared_ceiling;  /* Maximum shared buffers */
+	a_uint16_t resume_off; /*resume offset */
+	a_uint16_t resume_min_thresh; /* Minumum thresh for resume */
+} fal_bm_dynamic_cfg_t;
+
+typedef struct
+{
+	a_bool_t enable;
+	a_uint32_t offset;
+	a_uint32_t depth;
+} fal_port_tdm_ctrl_t;
+
+typedef struct
+{
+	a_uint64_t drop_byte_counter; /*drop byte due to overload*/
+	a_uint32_t drop_packet_counter; /*drop packet due to overload*/
+	a_uint64_t fc_drop_byte_counter; /*drop byte due to fc*/
+	a_uint32_t fc_drop_packet_counter; /*drop packet due to fc*/
+	a_uint32_t used_counter; /*total used buffer counter for the port*/
+	a_uint32_t react_counter; /*react used buffer counter for the port*/
+} fal_bm_port_counter_t;
+
+#define FAL_PORT_TDB_DIR_INGRESS	0
+#define FAL_PORT_TDB_DIR_EGRESS	1
+typedef struct
+{
+	a_uint8_t valid; /* 0 for invalid and 1 for valid*/
+	a_uint8_t direction; /* 0 for ingreee and 1 for egress */
+	fal_port_t port;
+} fal_port_tdm_tick_cfg_t;
+
+enum {
+	FUNC_PORT_BUFGROUP_MAP_GET = 0,
+	FUNC_BM_PORT_RESERVED_BUFFER_GET,
+	FUNC_BM_BUFGROUP_BUFFER_GET,
+	FUNC_BM_PORT_DYNAMIC_THRESH_GET,
+	FUNC_PORT_BM_CTRL_GET,
+	FUNC_BM_BUFGROUP_BUFFER_SET,
+	FUNC_PORT_BUFGROUP_MAP_SET,
+	FUNC_BM_PORT_STATIC_THRESH_GET,
+	FUNC_BM_PORT_RESERVED_BUFFER_SET,
+	FUNC_BM_PORT_STATIC_THRESH_SET,
+	FUNC_BM_PORT_DYNAMIC_THRESH_SET,
+	FUNC_PORT_BM_CTRL_SET,
+	FUNC_PORT_TDM_CTRL_SET,
+	FUNC_PORT_TDM_TICK_CFG_SET,
+	FUNC_BM_PORT_COUNTER_GET,
+};
+
+sw_error_t
+fal_port_bm_ctrl_set(a_uint32_t dev_id, fal_port_t port, a_bool_t enable);
+
+sw_error_t
+fal_port_bufgroup_map_set(a_uint32_t dev_id, fal_port_t port,
+			a_uint8_t group);
+
+sw_error_t
+fal_bm_port_dynamic_thresh_set(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_dynamic_cfg_t *cfg);
+
+sw_error_t
+fal_bm_bufgroup_buffer_set(a_uint32_t dev_id, a_uint8_t group,
+			a_uint16_t buff_num);
+
+sw_error_t
+fal_bm_port_reserved_buffer_set(a_uint32_t dev_id, fal_port_t port,
+			a_uint16_t prealloc_buff, a_uint16_t react_buff);
+
+#ifndef IN_BM_MINI
+sw_error_t
+fal_port_bm_ctrl_get(a_uint32_t dev_id, fal_port_t port, a_bool_t *enable);
+
+sw_error_t
+fal_port_bufgroup_map_get(a_uint32_t dev_id, fal_port_t port,
+			a_uint8_t *group);
+sw_error_t
+fal_bm_bufgroup_buffer_get(a_uint32_t dev_id, a_uint8_t group,
+			a_uint16_t *buff_num);
+sw_error_t
+fal_bm_port_reserved_buffer_get(a_uint32_t dev_id, fal_port_t port,
+			a_uint16_t *prealloc_buff, a_uint16_t *react_buff);
+
+sw_error_t
+fal_bm_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_static_cfg_t *cfg);
+
+sw_error_t
+fal_bm_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_static_cfg_t *cfg);
+sw_error_t
+fal_bm_port_dynamic_thresh_get(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_dynamic_cfg_t *cfg);
+
+sw_error_t
+fal_bm_port_counter_get(a_uint32_t dev_id, fal_port_t port,
+		fal_bm_port_counter_t *counter);
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _PORT_BM_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_cosmap.h b/qca-ssdk/include/fal/fal_cosmap.h
new file mode 100755
index 0000000..707ce29
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_cosmap.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_cosmap FAL_COSMAP
+ * @{
+ */
+#ifndef _FAL_COSMAP_H_
+#define _FAL_COSMAP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+    typedef struct
+    {
+        a_bool_t remark_dscp;
+        a_bool_t remark_up;
+        a_bool_t remark_dei;
+        a_uint8_t g_dscp;
+        a_uint8_t y_dscp;
+        a_uint8_t g_up;
+        a_uint8_t y_up;
+        a_uint8_t g_dei;
+        a_uint8_t y_dei;
+    } fal_egress_remark_table_t;
+
+#ifndef IN_COSMAP_MINI
+    sw_error_t
+    fal_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp,
+                               a_uint32_t pri);
+
+    sw_error_t
+    fal_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+                               a_uint32_t * pri);
+
+    sw_error_t
+    fal_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp,
+                              a_uint32_t dp);
+
+    sw_error_t
+    fal_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp,
+                              a_uint32_t * dp);
+
+    sw_error_t
+    fal_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up,
+                             a_uint32_t pri);
+
+    sw_error_t
+    fal_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up,
+                             a_uint32_t * pri);
+
+    sw_error_t
+    fal_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up,
+                            a_uint32_t dp);
+
+    sw_error_t
+    fal_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up,
+                            a_uint32_t * dp);
+
+    sw_error_t
+    fal_cosmap_dscp_to_ehpri_set(a_uint32_t dev_id, a_uint32_t dscp,
+                               a_uint32_t pri);
+
+    sw_error_t
+    fal_cosmap_dscp_to_ehpri_get(a_uint32_t dev_id, a_uint32_t dscp,
+                               a_uint32_t * pri);
+
+    sw_error_t
+    fal_cosmap_dscp_to_ehdp_set(a_uint32_t dev_id, a_uint32_t dscp,
+                              a_uint32_t dp);
+
+    sw_error_t
+    fal_cosmap_dscp_to_ehdp_get(a_uint32_t dev_id, a_uint32_t dscp,
+                              a_uint32_t * dp);
+
+    sw_error_t
+    fal_cosmap_up_to_ehpri_set(a_uint32_t dev_id, a_uint32_t up,
+                             a_uint32_t pri);
+
+    sw_error_t
+    fal_cosmap_up_to_ehpri_get(a_uint32_t dev_id, a_uint32_t up,
+                             a_uint32_t * pri);
+
+    sw_error_t
+    fal_cosmap_up_to_ehdp_set(a_uint32_t dev_id, a_uint32_t up,
+                            a_uint32_t dp);
+
+    sw_error_t
+    fal_cosmap_up_to_ehdp_get(a_uint32_t dev_id, a_uint32_t up,
+                            a_uint32_t * dp);
+#endif
+    sw_error_t
+    fal_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+                                a_uint32_t queue);
+
+	sw_error_t
+	fal_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+                                  a_uint32_t queue);
+#ifndef IN_COSMAP_MINI
+    sw_error_t
+    fal_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+                                a_uint32_t * queue);
+
+    sw_error_t
+    fal_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+                                  a_uint32_t * queue);
+
+    sw_error_t
+    fal_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+                                 fal_egress_remark_table_t * tbl);
+
+    sw_error_t
+    fal_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+                                 fal_egress_remark_table_t * tbl);
+#endif
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_COSMAP_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/fal/fal_ctrlpkt.h b/qca-ssdk/include/fal/fal_ctrlpkt.h
new file mode 100755
index 0000000..0903a2e
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_ctrlpkt.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_gen FAL_CTRLPKT
+ * @{
+ */
+#ifndef _FAL_CTRLPKT_H_
+#define _FAL_CTRLPKT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+
+#if defined(SW_API_LOCK) && (!defined(HSL_STANDALONG))
+#define FAL_CTRLPKT_API_LOCK
+#define FAL_CTRLPKT_API_UNLOCK
+#else
+#define FAL_CTRLPKT_API_LOCK
+#define FAL_CTRLPKT_API_UNLOCK
+#endif
+
+
+typedef struct {
+	fal_fwd_cmd_t action; /* the action when condition matched */
+	a_bool_t sg_bypass; /* check if sg_bypass when condition matched */
+	a_bool_t l2_filter_bypass; /* check if l2_filter_bypass when condition matched */
+	a_bool_t in_stp_bypass; /* check if in_stp_bypass when condition matched */
+	a_bool_t in_vlan_fltr_bypass; /* check if in_vlan_fltr_bypass when condition matched */
+} fal_ctrlpkt_action_t;
+
+typedef struct
+{
+	a_bool_t mgt_eapol; /* eapol protocol management type */
+	a_bool_t mgt_pppoe; /* pppoe protocol management type */
+	a_bool_t mgt_igmp; /* igmp protocol management type */
+	a_bool_t mgt_arp_req; /* arp request protocol management type */
+	a_bool_t mgt_arp_rep; /* arp response protocol management type */
+	a_bool_t mgt_dhcp4; /* dhcp4 protocol management type */
+	a_bool_t mgt_mld; /* mld protocol management type */
+	a_bool_t mgt_ns; /* ns protocol management type */
+	a_bool_t mgt_na; /* na protocol management type */
+	a_bool_t mgt_dhcp6; /* dhcp6 protocol management type */
+} fal_ctrlpkt_protocol_type_t;
+
+typedef struct {
+	fal_ctrlpkt_action_t action; /* the all action when condition matched */
+	fal_pbmp_t port_map; /* the condition port bitmap */
+	a_uint32_t ethtype_profile_bitmap; /* the condition ethtype_profile bitmap */
+	a_uint32_t rfdb_profile_bitmap; /* the condition rfdb_profile bitmap */
+	fal_ctrlpkt_protocol_type_t protocol_types; /* the condition protocol types */
+} fal_ctrlpkt_profile_t;
+
+enum {
+	FUNC_MGMTCTRL_ETHTYPE_PROFILE_SET = 0,
+	FUNC_MGMTCTRL_ETHTYPE_PROFILE_GET,
+	FUNC_MGMTCTRL_RFDB_PROFILE_SET,
+	FUNC_MGMTCTRL_RFDB_PROFILE_GET,
+	FUNC_MGMTCTRL_CTRLPKT_PROFILE_ADD,
+	FUNC_MGMTCTRL_CTRLPKT_PROFILE_DEL,
+	FUNC_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST,
+	FUNC_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT,
+};
+
+sw_error_t fal_mgmtctrl_ethtype_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t ethtype);
+sw_error_t fal_mgmtctrl_ethtype_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t * ethtype);
+
+sw_error_t fal_mgmtctrl_rfdb_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr);
+sw_error_t fal_mgmtctrl_rfdb_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr);
+
+sw_error_t fal_mgmtctrl_ctrlpkt_profile_add(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt);
+sw_error_t fal_mgmtctrl_ctrlpkt_profile_del(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt);
+sw_error_t fal_mgmtctrl_ctrlpkt_profile_getfirst(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt);
+sw_error_t fal_mgmtctrl_ctrlpkt_profile_getnext(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_CTRLPKT_H_ */
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/fal/fal_fdb.h b/qca-ssdk/include/fal/fal_fdb.h
new file mode 100755
index 0000000..791dba9
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_fdb.h
@@ -0,0 +1,338 @@
+/*
+ * Copyright (c) 2012, 2015-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_fdb FAL_FDB
+ * @{
+ */
+#ifndef _FAL_FDB_H_
+#define _FAL_FDB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+    /**
+      @details  Fields description:
+
+        portmap_en - If value of portmap_en is A_TRUE then port.map is valid
+        otherwise port.id is valid.
+
+
+        leaky_en - If value of leaky_en is A_TRUE then packets which
+        destination address equals addr in this entry would be leaky.
+
+
+        mirror_en - If value of mirror_en is A_TRUE then packets which
+        destination address equals addr in this entry would be mirrored.
+
+
+        clone_en - If value of clone_en is A_TRUE which means this address is
+        a mac clone address.
+    @brief This structure defines the Fdb entry.
+
+    */
+    typedef struct
+    {
+        fal_mac_addr_t addr; /* mac address of fdb entry */
+        a_uint16_t    fid; /* vlan_id/vsi value of fdb entry */
+        fal_fwd_cmd_t dacmd; /* source address command */
+        fal_fwd_cmd_t sacmd; /* dest address command */
+        union
+        {
+            fal_port_t id; /* union value is port id value */
+            fal_pbmp_t map; /* union value is bitmap value */
+        } port;
+        a_bool_t portmap_en; /* use port bitmap or not */
+        a_bool_t is_multicast; /* if it is a multicast mac fdb entry */
+        a_bool_t static_en; /* enable static or not */
+        a_bool_t leaky_en; /* enable leaky or not */
+        a_bool_t mirror_en; /* enable mirror or not */
+        a_bool_t clone_en; /* enable clone or not */
+        a_bool_t cross_pt_state; /* cross port state */
+        a_bool_t da_pri_en; /* enable da pri or not */
+        a_uint8_t da_queue; /* da queue value */
+        a_bool_t white_list_en; /* enable white list or not */
+        a_bool_t load_balance_en; /* enable load balance value or not */
+        a_uint8_t load_balance; /* load balance value */
+        a_bool_t entry_valid; /* check if entry is value */
+        a_bool_t lookup_valid; /* check if entry is lookup */
+    } fal_fdb_entry_t;
+
+    typedef struct
+    {
+        fal_mac_addr_t addr;
+        a_uint16_t    fid;
+        a_uint8_t load_balance;
+    } fal_fdb_rfs_t;
+
+    typedef struct
+    {
+        a_bool_t enable; /* enable port learn limit or not */
+        a_uint32_t limit_num; /* port learn limit number */
+        fal_fwd_cmd_t action; /* the action when port learn number exceed limit*/
+    } fal_maclimit_ctrl_t;
+
+#define FAL_FDB_DEL_STATIC   0x1
+
+    typedef struct
+    {
+        a_bool_t port_en; /* enable port value matching or not */
+        a_bool_t fid_en; /* enable fid value matching or not */
+        a_bool_t multicast_en; /* enable multicast value matching or not */
+    } fal_fdb_op_t;
+
+    typedef enum
+    {
+        INVALID_VLAN_SVL=0,
+        INVALID_VLAN_IVL
+    } fal_fdb_smode;
+
+enum {
+	FUNC_FDB_ENTRY_ADD = 0,
+	FUNC_FDB_ENTRY_FLUSH,
+	FUNC_FDB_ENTRY_DEL_BYPORT,
+	FUNC_FDB_ENTRY_DEL_BYMAC,
+	FUNC_FDB_ENTRY_GETFIRST,
+	FUNC_FDB_ENTRY_GETNEXT,
+	FUNC_FDB_ENTRY_SEARCH,
+	FUNC_FDB_PORT_LEARN_SET,
+	FUNC_FDB_PORT_LEARN_GET,
+	FUNC_FDB_PORT_LEARNING_CTRL_SET,
+	FUNC_FDB_PORT_LEARNING_CTRL_GET,
+	FUNC_FDB_PORT_STAMOVE_CTRL_SET,
+	FUNC_FDB_PORT_STAMOVE_CTRL_GET,
+	FUNC_FDB_AGING_CTRL_SET,
+	FUNC_FDB_AGING_CTRL_GET,
+	FUNC_FDB_LEARNING_CTRL_SET,
+	FUNC_FDB_LEARNING_CTRL_GET,
+	FUNC_FDB_AGING_TIME_SET,
+	FUNC_FDB_AGING_TIME_GET,
+	FUNC_FDB_ENTRY_GETNEXT_BYINDEX,
+	FUNC_FDB_ENTRY_EXTEND_GETNEXT,
+	FUNC_FDB_ENTRY_EXTEND_GETFIRST,
+	FUNC_FDB_ENTRY_UPDATE_BYPORT,
+	FUNC_PORT_FDB_LEARN_LIMIT_SET,
+	FUNC_PORT_FDB_LEARN_LIMIT_GET,
+	FUNC_PORT_FDB_LEARN_EXCEED_CMD_SET,
+	FUNC_PORT_FDB_LEARN_EXCEED_CMD_GET,
+	FUNC_FDB_PORT_LEARNED_MAC_COUNTER_GET,
+	FUNC_FDB_PORT_ADD,
+	FUNC_FDB_PORT_DEL,
+	FUNC_FDB_PORT_MACLIMIT_CTRL_SET,
+	FUNC_FDB_PORT_MACLIMIT_CTRL_GET,
+	FUNC_FDB_DEL_BY_FID,
+};
+
+#ifndef IN_FDB_MINI
+    sw_error_t
+    fal_fdb_entry_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+	sw_error_t
+    fal_fdb_rfs_set(a_uint32_t dev_id, const fal_fdb_rfs_t * entry);
+
+	sw_error_t
+    fal_fdb_rfs_del(a_uint32_t dev_id, const fal_fdb_rfs_t * entry);
+#endif
+
+    sw_error_t
+    fal_fdb_entry_flush(a_uint32_t dev_id, a_uint32_t flag);
+
+
+    sw_error_t
+    fal_fdb_entry_del_byport(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag);
+
+    sw_error_t
+    fal_fdb_entry_del_bymac(a_uint32_t dev_id, const fal_fdb_entry_t *entry);
+
+    sw_error_t
+    fal_fdb_entry_getfirst(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+#ifndef IN_FDB_MINI
+    sw_error_t
+    fal_fdb_entry_getnext(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+#endif
+
+    sw_error_t
+    fal_fdb_entry_search(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+sw_error_t
+    fal_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+#ifndef IN_FDB_MINI
+    sw_error_t
+    fal_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+#endif
+    sw_error_t
+    fal_fdb_port_learning_ctrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable, fal_fwd_cmd_t cmd);
+#ifndef IN_FDB_MINI
+    sw_error_t
+    fal_fdb_port_learning_ctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t *enable, fal_fwd_cmd_t *cmd);
+#endif
+
+    sw_error_t
+    fal_fdb_port_stamove_ctrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable, fal_fwd_cmd_t cmd);
+
+#ifndef IN_FDB_MINI
+    sw_error_t
+    fal_fdb_port_stamove_ctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t *enable, fal_fwd_cmd_t *cmd);
+#endif
+
+    sw_error_t
+    fal_fdb_aging_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+
+#ifndef IN_FDB_MINI
+    sw_error_t
+    fal_fdb_aging_ctrl_get(a_uint32_t dev_id, a_bool_t * enable);
+#endif
+
+    sw_error_t
+    fal_fdb_learning_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+
+#ifndef IN_FDB_MINI
+    sw_error_t
+    fal_fdb_learning_ctrl_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    sw_error_t
+    fal_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode);
+
+    sw_error_t
+    fal_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode * smode);
+
+    sw_error_t
+    fal_fdb_aging_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+
+    sw_error_t
+    fal_fdb_aging_time_get(a_uint32_t dev_id, a_uint32_t * time);
+#endif
+    sw_error_t
+    fal_fdb_entry_getnext_byindex(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry);
+
+    sw_error_t
+    fal_fdb_entry_extend_getnext(a_uint32_t dev_id, fal_fdb_op_t * option,
+                        fal_fdb_entry_t * entry);
+
+    sw_error_t
+    fal_fdb_entry_extend_getfirst(a_uint32_t dev_id, fal_fdb_op_t * option,
+                         fal_fdb_entry_t * entry);
+
+#ifndef IN_FDB_MINI
+    sw_error_t
+    fal_fdb_entry_update_byport(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+                     a_uint32_t fid, fal_fdb_op_t * option);
+
+    sw_error_t
+    fal_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable, a_uint32_t cnt);
+
+    sw_error_t
+    fal_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable, a_uint32_t * cnt);
+
+    sw_error_t
+    fal_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                      fal_fwd_cmd_t cmd);
+
+
+    sw_error_t
+    fal_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                      fal_fwd_cmd_t * cmd);
+
+    sw_error_t
+    fal_fdb_port_learned_mac_counter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t * cnt);
+
+    sw_error_t
+    fal_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt);
+
+    sw_error_t
+    fal_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt);
+
+    sw_error_t
+    fal_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+    sw_error_t
+    fal_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+    sw_error_t
+    fal_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+    sw_error_t
+    fal_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+    sw_error_t
+    fal_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+    sw_error_t
+    fal_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry);
+
+    sw_error_t
+    fal_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    sw_error_t
+    fal_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable);
+
+    sw_error_t
+    fal_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+    sw_error_t
+    fal_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+    sw_error_t
+    fal_fdb_port_maclimit_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl);
+
+    sw_error_t
+    fal_fdb_port_maclimit_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl);
+#endif
+
+    sw_error_t
+    fal_fdb_entry_del_byfid(a_uint32_t dev_id, a_uint16_t fid, a_uint32_t flag);
+
+#define fal_fdb_add 	fal_fdb_entry_add
+#define fal_fdb_del_all	fal_fdb_entry_flush
+#define fal_fdb_del_by_port	fal_fdb_entry_del_byport
+#define fal_fdb_del_by_mac	fal_fdb_entry_del_bymac
+#define fal_fdb_first		fal_fdb_entry_getfirst
+#define fal_fdb_next		fal_fdb_entry_getnext
+#define fal_fdb_find		fal_fdb_entry_search
+#define fal_fdb_age_ctrl_set		fal_fdb_aging_ctrl_set
+#define fal_fdb_age_ctrl_get		fal_fdb_aging_ctrl_get
+#define fal_fdb_age_time_set		fal_fdb_aging_time_set
+#define fal_fdb_age_time_get		fal_fdb_aging_time_get
+#define fal_fdb_iterate			fal_fdb_entry_getnext_byindex
+#define fal_fdb_extend_next		fal_fdb_entry_extend_getnext
+#define fal_fdb_extend_first		fal_fdb_entry_extend_getfirst
+#define fal_fdb_transfer		fal_fdb_entry_update_byport
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_FDB_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_flow.h b/qca-ssdk/include/fal/fal_flow.h
new file mode 100755
index 0000000..f859868
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_flow.h
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_flow
+ * @{
+ */
+#ifndef _FAL_FLOW_H_
+#define _FAL_FLOW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+#include "fal/fal_ip.h"
+
+typedef enum {
+	FAL_FLOW_L3_UNICAST = 0,
+	FAL_FLOW_L2_UNICAST,
+	FAL_FLOW_MCAST,
+} fal_flow_pkt_type_t;
+
+typedef enum {
+	FAL_FLOW_LAN_TO_LAN_DIR = 0,
+	FAL_FLOW_LAN_TO_WAN_DIR,
+	FAL_FLOW_WAN_TO_LAN_DIR,
+	FAL_FLOW_WAN_TO_WAN_DIR,
+	FAL_FLOW_UNKOWN_DIR_DIR,
+} fal_flow_direction_t;
+
+typedef enum {
+	FAL_FLOW_FORWARD = 0,
+	FAL_FLOW_SNAT,
+	FAL_FLOW_DNAT,
+	FAL_FLOW_ROUTE,
+	FAL_FLOW_BRIDGE,
+} fal_flow_fwd_type_t;
+
+/* FLOW entry type field */
+#define FAL_FLOW_IP4_5TUPLE_ADDR        0x1
+#define FAL_FLOW_IP6_5TUPLE_ADDR        0x2
+#define FAL_FLOW_IP4_3TUPLE_ADDR        0x4
+#define FAL_FLOW_IP6_3TUPLE_ADDR        0x8
+
+#define FAL_FLOW_OP_MODE_KEY         0x0
+#define FAL_FLOW_OP_MODE_INDEX     0x1
+#define FAL_FLOW_OP_MODE_FLUSH     0x2
+
+#define FAL_FLOW_PROTOCOL_OTHER    0
+#define FAL_FLOW_PROTOCOL_TCP	        1
+#define FAL_FLOW_PROTOCOL_UDP	  2
+#define FAL_FLOW_PROTOCOL_UDPLITE  3
+
+
+typedef struct {
+	fal_fwd_cmd_t miss_action; /* flow mismatch action*/
+	a_bool_t frag_bypass_en; /*0 for disable and 1 for enable*/
+	a_bool_t tcp_spec_bypass_en; /*0 for disable and 1 for enable*/
+	a_bool_t all_bypass_en; /*0 for disable and 1 for enable*/
+	a_uint8_t key_sel; /*0 for source ip address and 1 for destination ip address*/
+} fal_flow_mgmt_t;
+
+typedef struct {
+	a_uint32_t entry_id; /*entry index*/ 
+	a_uint8_t entry_type; /*1:ipv4 5 tuple, 2:ipv6 5 tuple, 4:ipv4 3 tuple, 8:ipv6 3 tuple*/
+	a_uint8_t host_addr_type; /*0:souce ip index, 1:destination ip index*/
+	a_uint16_t host_addr_index; /*host table entry index*/
+	a_uint8_t protocol; /*1:tcp, 2:udp, 3:udp-lite, 0:other*/
+	a_uint8_t age; /*aging value*/
+	a_bool_t src_intf_valid; /*source interface check valid*/
+	a_uint8_t src_intf_index; /*souce l3 interface*/
+	a_uint8_t fwd_type; /*forward type*/
+	a_uint16_t snat_nexthop; /*nexthop index for snat*/
+	a_uint16_t snat_srcport; /*new source l4 port*/
+	a_uint16_t dnat_nexthop; /*nexthop index for dnat*/
+	a_uint16_t dnat_dstport; /*new destination l4 port*/
+	a_uint16_t route_nexthop; /*nexthop index for route*/
+	a_bool_t port_valid; /*route port valid*/
+	fal_port_t route_port; /*port for route*/
+	fal_port_t bridge_port; /*port for l2 bridge*/
+	a_bool_t deacclr_en; /*0 for disable and 1 for enable*/
+	a_bool_t copy_tocpu_en; /*0 for disable and 1 for enable*/
+	a_uint8_t syn_toggle; /*update by host*/
+	a_uint8_t pri_profile; /*flow qos index*/
+	a_uint8_t sevice_code; /*service code for bypass*/
+	a_uint8_t ip_type; /*0 for ipv4 and 1 for ipv6*/
+	union {
+		fal_ip4_addr_t ipv4;
+		fal_ip6_addr_t ipv6;
+	} flow_ip;
+	a_uint16_t src_port; /*l4 source port*/
+	a_uint16_t dst_port; /*l4 destination port*/
+	a_uint32_t tree_id; /*for qos*/
+	a_uint32_t pkt_counter; /*flow packet counter*/
+	a_uint64_t byte_counter; /*flow byte counter*/
+} fal_flow_entry_t;
+
+typedef struct {
+	fal_fwd_cmd_t src_if_check_action; /*source inferface check fail action*/
+	a_bool_t src_if_check_deacclr_en; /*0 for disable and 1 for enable*/
+	a_bool_t service_loop_en; /*0 for disable and 1 for enable*/
+	fal_fwd_cmd_t service_loop_action; /*0 for disable and 1 for enable*/
+	a_bool_t service_loop_deacclr_en; /*0 for disable and 1 for enable*/ 
+	fal_fwd_cmd_t flow_deacclr_action; /*flow de acceleration action*/
+	fal_fwd_cmd_t sync_mismatch_action; /*sync toggle mismatch action*/
+	a_bool_t sync_mismatch_deacclr_en; /*0 for disable and 1 for enable*/
+	a_uint8_t hash_mode_0; /*0 crc10, 1 xor, 2 crc16*/
+	a_uint8_t hash_mode_1; /*0 crc10, 1 xor, 2 crc16*/
+	a_bool_t flow_mismatch_copy_escape_en; /*0 for disable and 1 for enable*/
+} fal_flow_global_cfg_t;
+
+typedef struct {
+	fal_flow_entry_t flow_entry;
+	fal_host_entry_t host_entry;
+} fal_flow_host_entry_t;
+
+typedef struct {
+	a_uint16_t age_time; /* age value*/
+	a_uint16_t unit; /*0:second 1:cycle 2:million cycle*/
+} fal_flow_age_timer_t;
+
+enum  {
+	FUNC_FLOW_HOST_ADD = 0,
+	FUNC_FLOW_ENTRY_GET,
+	FUNC_FLOW_ENTRY_DEL,
+	FUNC_FLOW_STATUS_GET,
+	FUNC_FLOW_CTRL_SET,
+	FUNC_FLOW_AGE_TIMER_GET,
+	FUNC_FLOW_STATUS_SET,
+	FUNC_FLOW_HOST_GET,
+	FUNC_FLOW_HOST_DEL,
+	FUNC_FLOW_CTRL_GET,
+	FUNC_FLOW_AGE_TIMER_SET,
+	FUNC_FLOW_ENTRY_ADD,
+	FUNC_FLOW_GLOBAL_CFG_GET,
+	FUNC_FLOW_GLOBAL_CFG_SET,
+	FUNC_FLOW_ENTRY_NEXT
+};
+
+#ifndef IN_FLOW_MINI
+sw_error_t
+fal_flow_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+sw_error_t
+fal_flow_status_get(a_uint32_t dev_id, a_bool_t *enable);
+
+sw_error_t
+fal_flow_age_timer_set(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer);
+
+sw_error_t
+fal_flow_age_timer_get(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer);
+#endif
+
+sw_error_t
+fal_flow_mgmt_set(
+		a_uint32_t dev_id,
+		fal_flow_pkt_type_t type,
+		fal_flow_direction_t dir,
+		fal_flow_mgmt_t *mgmt);
+
+sw_error_t
+fal_flow_mgmt_get(
+		a_uint32_t dev_id,
+		fal_flow_pkt_type_t type,
+		fal_flow_direction_t dir,
+		fal_flow_mgmt_t *mgmt);
+
+#ifndef IN_FLOW_MINI
+sw_error_t
+fal_flow_entry_add(
+		a_uint32_t dev_id,
+		a_uint32_t add_mode, /*index or hash*/
+		fal_flow_entry_t *flow_entry);
+
+sw_error_t
+fal_flow_entry_del(
+		a_uint32_t dev_id,
+		a_uint32_t del_mode,
+		fal_flow_entry_t *flow_entry);
+
+sw_error_t
+fal_flow_entry_get(
+		a_uint32_t dev_id,
+		a_uint32_t get_mode,
+		fal_flow_entry_t *flow_entry);
+
+sw_error_t
+fal_flow_entry_next(
+		a_uint32_t dev_id,
+		a_uint32_t next_mode,
+		fal_flow_entry_t *flow_entry);
+
+sw_error_t
+fal_flow_host_add(
+		a_uint32_t dev_id,
+		a_uint32_t add_mode,
+		fal_flow_host_entry_t *flow_host_entry);
+
+sw_error_t
+fal_flow_host_del(
+		a_uint32_t dev_id,
+		a_uint32_t del_mode,
+		fal_flow_host_entry_t *flow_host_entry);
+
+sw_error_t
+fal_flow_host_get(
+		a_uint32_t dev_id,
+		a_uint32_t get_mode,
+		fal_flow_host_entry_t *flow_host_entry);
+
+sw_error_t
+fal_flow_global_cfg_get(
+		a_uint32_t dev_id,
+		fal_flow_global_cfg_t *cfg);
+
+sw_error_t
+fal_flow_global_cfg_set(
+		a_uint32_t dev_id,
+		fal_flow_global_cfg_t *cfg);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_FLOW_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/fal/fal_flowcookie.h b/qca-ssdk/include/fal/fal_flowcookie.h
new file mode 100755
index 0000000..857c5aa
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_flowcookie.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _FAL_FLOWCOOKIE_H_
+#define _FAL_FLOWCOOKIE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+int ssdk_flow_cookie_set(
+		u32 protocol, __be32 src_ip,
+		__be16 src_port, __be32 dst_ip,
+		__be16 dst_port, u16 flowcookie);
+
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_FLOWCOOKIE_H_ */
+
+/**
+ * @}
+ */
+
+
diff --git a/qca-ssdk/include/fal/fal_igmp.h b/qca-ssdk/include/fal/fal_igmp.h
new file mode 100755
index 0000000..36cee4e
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_igmp.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_igmp FAL_IGMP
+ * @{
+ */
+#ifndef _FAL_IGMP_H_
+#define _FAL_IGMP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+#include "fal/fal_multi.h"
+
+
+    sw_error_t
+    fal_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+    sw_error_t
+    fal_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+
+    sw_error_t
+    fal_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+
+    sw_error_t
+    fal_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+
+    sw_error_t
+    fal_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+    sw_error_t
+    fal_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+
+    sw_error_t
+    fal_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+    sw_error_t
+    fal_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+
+    sw_error_t
+    fal_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts);
+
+
+
+    sw_error_t
+    fal_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts);
+
+
+
+    sw_error_t
+    fal_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+    sw_error_t
+    fal_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    sw_error_t
+    fal_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t static_en);
+
+
+    sw_error_t
+    fal_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * static_en);
+
+
+    sw_error_t
+    fal_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    sw_error_t
+    fal_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    sw_error_t
+    fal_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    sw_error_t
+    fal_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    sw_error_t
+    fal_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue);
+
+
+    sw_error_t
+    fal_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue);
+
+
+    sw_error_t
+    fal_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                      a_bool_t enable, a_uint32_t cnt);
+
+
+    sw_error_t
+    fal_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                      a_bool_t * enable, a_uint32_t * cnt);
+
+
+    sw_error_t
+    fal_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                           fal_fwd_cmd_t cmd);
+
+
+    sw_error_t
+    fal_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                           fal_fwd_cmd_t * cmd);
+
+    sw_error_t
+    fal_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+    sw_error_t
+    fal_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+    sw_error_t
+    fal_igmp_sg_entry_show(a_uint32_t dev_id);
+
+    sw_error_t
+    fal_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t * info);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_IGMP_H_ */
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_init.h b/qca-ssdk/include/fal/fal_init.h
new file mode 100755
index 0000000..2d372c5
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_init.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2012, 2016-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*qca808x_start*/
+/**
+ * @defgroup fal_init FAL_INIT
+ * @{
+ */
+#ifndef _FAL_INIT_H_
+#define _FAL_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "ssdk_init.h"
+/*qca808x_end*/
+enum{
+	FAL_MODULE_ACL,
+	FAL_MODULE_VSI,
+	FAL_MODULE_IP,
+	FAL_MODULE_FLOW,
+	FAL_MODULE_QM,
+	FAL_MODULE_QOS,
+	FAL_MODULE_BM,
+	FAL_MODULE_SERVCODE,
+	FAL_MODULE_RSS_HASH,
+	FAL_MODULE_PPPOE,
+	FAL_MODULE_SHAPER,
+	FAL_MODULE_PORTCTRL,
+	FAL_MODULE_MIB,
+	FAL_MODULE_MIRROR,
+	FAL_MODULE_FDB,
+	FAL_MODULE_STP,
+	FAL_MODULE_TRUNK,
+	FAL_MODULE_PORTVLAN,
+	FAL_MODULE_CTRLPKT,
+	FAL_MODULE_SEC,
+	FAL_MODULE_POLICER,
+	FAL_MODULE_MISC,
+	FAL_MODULE_PTP,
+	FAL_MODULE_SFP,
+	FAL_MODULE_MAX,
+};
+
+typedef struct
+{
+	a_uint32_t bitmap[3];
+}fal_func_ctrl_t;
+/*qca808x_start*/
+sw_error_t fal_init(a_uint32_t dev_id, ssdk_init_cfg * cfg);
+/*qca808x_end*/
+sw_error_t fal_reset(a_uint32_t dev_id);
+sw_error_t fal_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg);
+/*qca808x_start*/
+sw_error_t fal_cleanup(void);
+/*qca808x_end*/
+sw_error_t fal_module_func_ctrl_set(a_uint32_t dev_id,
+		a_uint32_t module, fal_func_ctrl_t *func_ctrl);
+sw_error_t fal_module_func_ctrl_get(a_uint32_t dev_id,
+		a_uint32_t module, fal_func_ctrl_t *func_ctrl);
+sw_error_t fal_module_func_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+sw_error_t fal_switch_devid_get(ssdk_chip_type chip_type, a_uint32_t *pdev_id);
+
+/*qca808x_start*/
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_INIT_H_ */
+/**
+ * @}
+ */
+/*qca808x_end*/
diff --git a/qca-ssdk/include/fal/fal_interface_ctrl.h b/qca-ssdk/include/fal/fal_interface_ctrl.h
new file mode 100755
index 0000000..f4383ee
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_interface_ctrl.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_interface_ctrl FAL_INTERFACE_CONTROL
+ * @{
+ */
+#ifndef _FAL_INTERFACECTRL_H_
+#define _FAL_INTERFACECTRL_H_
+
+#ifdef __cplusplus
+extern "c" {
+#endif
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+    typedef enum {
+        FAL_MAC_MODE_RGMII = 0,
+        FAL_MAC_MODE_GMII,
+        FAL_MAC_MODE_MII,
+        FAL_MAC_MODE_SGMII,
+        FAL_MAC_MODE_FIBER,
+        FAL_MAC_MODE_RMII,
+        FAL_MAC_MODE_DEFAULT
+    }
+    fal_interface_mac_mode_t;
+
+    typedef enum
+    {
+        FAL_INTERFACE_CLOCK_MAC_MODE = 0,
+        FAL_INTERFACE_CLOCK_PHY_MODE = 1,
+    } fal_interface_clock_mode_t;
+
+    typedef struct
+    {
+        a_bool_t   txclk_delay_cmd;
+        a_bool_t   rxclk_delay_cmd;
+        a_uint32_t txclk_delay_sel;
+        a_uint32_t rxclk_delay_sel;
+    } fal_mac_rgmii_config_t;
+
+    typedef struct
+    {
+        a_bool_t   master_mode;
+        a_bool_t   slave_mode;
+        a_bool_t   clock_inverse;
+        a_bool_t   pipe_rxclk_sel;
+    } fal_mac_rmii_config_t;
+
+    typedef struct
+    {
+        fal_interface_clock_mode_t   clock_mode;
+        a_uint32_t                   txclk_select;
+        a_uint32_t                   rxclk_select;
+    } fal_mac_gmii_config_t;
+
+    typedef struct
+    {
+        fal_interface_clock_mode_t   clock_mode;
+        a_uint32_t                   txclk_select;
+        a_uint32_t                   rxclk_select;
+    } fal_mac_mii_config_t;
+
+    typedef struct
+    {
+        fal_interface_clock_mode_t  clock_mode;
+        a_bool_t                    auto_neg;
+        a_bool_t                    force_speed;
+        a_bool_t                    prbs_enable;
+        a_bool_t                    rem_phy_lpbk;
+    } fal_mac_sgmii_config_t;
+
+    typedef struct
+    {
+        a_bool_t                    auto_neg;
+        a_bool_t                    fx100_enable;
+    } fal_mac_fiber_config_t;
+
+    typedef struct
+    {
+        fal_interface_mac_mode_t      mac_mode;
+        union
+        {
+            fal_mac_rgmii_config_t    rgmii;
+            fal_mac_gmii_config_t     gmii;
+            fal_mac_mii_config_t      mii;
+            fal_mac_sgmii_config_t    sgmii;
+            fal_mac_rmii_config_t    rmii;
+            fal_mac_fiber_config_t    fiber;
+        } config;
+    } fal_mac_config_t;
+
+    typedef struct
+    {
+        fal_interface_mac_mode_t mac_mode;
+        a_bool_t                 txclk_delay_cmd;
+        a_bool_t                 rxclk_delay_cmd;
+        a_uint32_t               txclk_delay_sel;
+        a_uint32_t               rxclk_delay_sel;
+    } fal_phy_config_t;
+
+    typedef enum
+    {
+        Fx100BASE_MODE = 2,
+    } fx100_ctrl_link_mode_t;
+
+    typedef enum
+    {
+        FX100_SERDS_MODE = 1,
+    } sgmii_fiber_mode_t;
+
+#define    FX100_HALF_DUPLEX  0
+#define    FX100_FULL_DUPLEX  1
+
+    typedef struct
+    {
+        fx100_ctrl_link_mode_t   link_mode;
+        a_bool_t                 overshoot;
+        a_bool_t                 loopback;
+        a_bool_t                 fd_mode;
+        a_bool_t                 col_test;
+        sgmii_fiber_mode_t       sgmii_fiber_mode;
+        a_bool_t                 crs_ctrl;
+        a_bool_t                 loopback_ctrl;
+        a_bool_t                 crs_col_100_ctrl;
+        a_bool_t                 loop_en;
+    } fal_fx100_ctrl_config_t;
+
+    sw_error_t
+    fal_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+    sw_error_t
+    fal_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+    sw_error_t
+    fal_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+
+    sw_error_t
+    fal_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+
+    sw_error_t
+    fal_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
+
+    sw_error_t
+    fal_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
+
+    sw_error_t
+    fal_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config);
+
+    sw_error_t
+    fal_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config);
+
+    sw_error_t
+    fal_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status);
+
+    sw_error_t
+    fal_interface_mac06_exch_set(a_uint32_t dev_id,  a_bool_t enable);
+
+    sw_error_t
+    fal_interface_mac06_exch_get(a_uint32_t dev_id,  a_bool_t* enable);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_INTERFACECTRL_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_ip.h b/qca-ssdk/include/fal/fal_ip.h
new file mode 100755
index 0000000..54eed89
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_ip.h
@@ -0,0 +1,646 @@
+/*
+ * Copyright (c) 2012, 2015, 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_ip FAL_IP
+ * @{
+ */
+#ifndef _FAL_IP_H_
+#define _FAL_IP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+#include "fal_multi.h"
+
+
+#define FAL_MIN_VRF_ID 0
+#define FAL_MAX_VRF_ID 7
+    /* IP WCMP hash key flags */
+#define FAL_WCMP_HASH_KEY_SIP             0x1
+#define FAL_WCMP_HASH_KEY_DIP             0x2
+#define FAL_WCMP_HASH_KEY_SPORT           0x4
+#define FAL_WCMP_HASH_KEY_DPORT           0x8
+
+    /* IP entry operation flags */
+#define FAL_IP_ENTRY_ID_EN               0x1
+#define FAL_IP_ENTRY_INTF_EN             0x2
+#define FAL_IP_ENTRY_PORT_EN             0x4
+#define FAL_IP_ENTRY_STATUS_EN           0x8
+#define FAL_IP_ENTRY_IPADDR_EN           0x10
+#define FAL_IP_ENTRY_ALL_EN              0x20
+
+    /* IP host entry structure flags field */
+#define FAL_IP_IP4_ADDR                         0x1
+#define FAL_IP_IP6_ADDR                         0x2
+#define FAL_IP_CPU_ADDR                         0x4
+#define FAL_IP_IP4_ADDR_MCAST              0x8
+#define FAL_IP_IP6_ADDR_MCAST              0x10
+
+typedef struct {
+	a_uint8_t vsi; /*vsi value for l2 multicast*/
+	fal_ip4_addr_t sip4_addr; /*source ipv4 address*/
+	fal_ip6_addr_t sip6_addr; /*source ipv4 address*/
+} fal_host_mcast_t;
+
+typedef struct
+{
+	a_uint32_t rx_pkt_counter; /*rx packet counter*/
+	a_uint64_t rx_byte_counter; /*rx byte counter*/
+	a_uint32_t rx_drop_pkt_counter; /*rx drop packet counter*/
+	a_uint64_t rx_drop_byte_counter; /*rx drop byte counter*/
+	a_uint32_t tx_pkt_counter; /*tx packet counter*/
+	a_uint64_t tx_byte_counter; /*tx byte counter*/
+	a_uint32_t tx_drop_pkt_counter; /*tx drop packet counter*/
+	a_uint64_t tx_drop_byte_counter; /*tx drop byte counter*/
+} fal_ip_counter_t;
+
+typedef struct
+{
+	a_uint32_t entry_id; /*index for host table*/
+	a_uint32_t flags; /*1:ipv4 uni 2:ipv6 uni 8:ipv4 multi 0x10:ipv6 multi*/
+	a_uint32_t status; /* valid status: 0 or 1*/
+	fal_ip4_addr_t ip4_addr; /* ipv4 address */
+	fal_ip6_addr_t ip6_addr; /* ipv6 address */
+	fal_mac_addr_t mac_addr; /* unused for ppe */
+	a_uint32_t intf_id; /* unused for ppe */
+	a_uint32_t lb_num; /* unused for ppe */
+	a_uint32_t vrf_id; /* unused for ppe */
+	a_uint32_t expect_vid; /* unused for ppe */
+	fal_port_t port_id; /* unused for ppe */
+	a_bool_t mirror_en; /* unused for ppe */
+	a_bool_t counter_en; /* unused for ppe */
+	a_uint32_t counter_id; /* unused for ppe */
+	a_uint32_t packet; /* unused for ppe */
+	a_uint32_t byte; /* unused for ppe */
+	a_bool_t pppoe_en; /* unused for ppe */
+	a_uint32_t pppoe_id; /* unused for ppe */
+	fal_fwd_cmd_t action; /*forward action*/
+	a_uint32_t dst_info; /*bit 12:13: 1.nexthop, 2.port id, 3.port bitmap*/
+	a_uint8_t syn_toggle; /* sync toggle */
+	a_uint8_t lan_wan; /*0: ip over lan side ; 1: ip over wan side*/
+	fal_host_mcast_t mcast_info; /* multicast information */
+} fal_host_entry_t;
+
+    typedef enum
+    {
+        FAL_MAC_IP_GUARD = 0,
+        FAL_MAC_IP_PORT_GUARD,
+        FAL_MAC_IP_VLAN_GUARD,
+        FAL_MAC_IP_PORT_VLAN_GUARD,
+        FAL_NO_SOURCE_GUARD,
+    } fal_source_guard_mode_t;
+
+    typedef enum
+    {
+        FAL_DEFAULT_FLOW_FORWARD = 0,
+        FAL_DEFAULT_FLOW_DROP,
+        FAL_DEFAULT_FLOW_RDT_TO_CPU,
+        FAL_DEFAULT_FLOW_ADMIT_ALL,
+    } fal_default_flow_cmd_t;
+
+    typedef enum
+    {
+        FAL_FLOW_LAN_TO_LAN = 0,
+        FAL_FLOW_WAN_TO_LAN,
+        FAL_FLOW_LAN_TO_WAN,
+        FAL_FLOW_WAN_TO_WAN,
+    } fal_flow_type_t;
+
+    typedef enum
+    {
+        FAL_GLB_LOCK_TIME_DISABLE = 0,
+        FAL_GLB_LOCK_TIME_100US,
+        FAL_GLB_LOCK_TIME_1MS,
+        FAL_GLB_LOCK_TIME_10MS,
+    } fal_glb_lock_time_t;
+
+    typedef enum
+    {
+        FAL_ARP_LEARN_LOCAL = 0,
+        FAL_ARP_LEARN_ALL,
+    } fal_arp_learn_mode_t;
+
+    /* IP host entry auto learn arp packets type */
+#define FAL_ARP_LEARN_REQ                0x1
+#define FAL_ARP_LEARN_ACK                0x2
+
+    typedef struct
+    {
+        a_uint32_t entry_id;
+        a_uint32_t vrf_id;
+        a_uint16_t vid_low;
+        a_uint16_t vid_high;
+        fal_mac_addr_t mac_addr;
+        a_bool_t ip4_route;
+        a_bool_t ip6_route;
+    } fal_intf_mac_entry_t;
+
+    typedef struct
+    {
+        a_uint32_t nh_nr;
+        a_uint32_t nh_id[16];
+    } fal_ip_wcmp_t;
+
+    typedef struct
+    {
+        fal_mac_addr_t mac_addr;
+        fal_ip4_addr_t ip4_addr;
+		a_uint32_t     vid;
+		a_uint8_t      load_balance;
+    } fal_ip4_rfs_t;
+
+	typedef struct
+    {
+        fal_mac_addr_t mac_addr;
+        fal_ip6_addr_t ip6_addr;
+		a_uint32_t     vid;
+		a_uint8_t      load_balance;
+    } fal_ip6_rfs_t;
+
+    typedef struct
+    {
+        a_bool_t valid;
+        a_uint32_t vrf_id;
+        fal_addr_type_t ip_version; /*0 for IPv4 and 1 for IPv6*/
+        a_uint32_t droute_type; /*0 for ARP and 1 for WCMP*/
+        a_uint32_t index;/*when droute_type equals 0, means ARP entry index or means WCMP indexs*/
+    } fal_default_route_t;
+
+    typedef struct
+    {
+        a_bool_t valid;
+        a_uint32_t vrf_id;
+        a_uint32_t ip_version; /*0 for IPv4 and 1 for IPv6*/
+        union {
+        fal_ip4_addr_t ip4_addr;
+        fal_ip6_addr_t ip6_addr;
+	}route_addr;
+        a_uint32_t prefix_length;/*For IPv4, up to 32 and for IPv6, up to 128*/
+    } fal_host_route_t;
+
+typedef struct
+{
+	a_bool_t ipv4_arp_sg_en; /*0 for disable and 1 for enable*/
+	fal_fwd_cmd_t ipv4_arp_sg_vio_action; /* check fail action for arp source guard */
+	a_bool_t ipv4_arp_sg_port_en; /* source port based arp source guard enable */
+	a_bool_t ipv4_arp_sg_svlan_en; /* source svlan based arp source guard enable */
+	a_bool_t ipv4_arp_sg_cvlan_en; /* source cvlan based arp source guard enable */
+	fal_fwd_cmd_t ipv4_arp_src_unk_action; /* unknown action for arp source guard */
+	a_bool_t ip_nd_sg_en; /*0 for disable and 1 for enable*/
+	fal_fwd_cmd_t ip_nd_sg_vio_action; /* check fail action for nd source guard */
+	a_bool_t ip_nd_sg_port_en; /* source port based nd source guard enable */
+	a_bool_t ip_nd_sg_svlan_en; /* source svlan based nd source guard enable */
+	a_bool_t ip_nd_sg_cvlan_en; /* source cvlan based nd source guard enable */
+	fal_fwd_cmd_t ip_nd_src_unk_action; /* unknown action for nd source guard */
+} fal_arp_sg_cfg_t;
+
+typedef enum
+{
+	FAL_MC_MODE_GV = 0, /*not support igmpv3 source filter*/
+	FAL_MC_MODE_SGV /*support igmpv3 source filter*/
+} fal_mc_mode_t;
+
+typedef struct
+{
+	a_bool_t l2_ipv4_mc_en; /*0 for disable and 1 for enable*/
+	fal_mc_mode_t l2_ipv4_mc_mode; /*two modes*/
+	a_bool_t l2_ipv6_mc_en; /*0 for disable and 1 for enable*/
+	fal_mc_mode_t l2_ipv6_mc_mode; /*same with IPv4*/
+} fal_mc_mode_cfg_t;
+
+typedef struct
+{
+	a_uint8_t type; /*0 for IPv4 and 1 for IPv6*/
+	fal_fwd_cmd_t action; /* forward action */
+	a_uint32_t dst_info; /*bit 12:13: 1.nexthop, 2.port id, 3.port bitmap*/
+	a_uint8_t lan_wan; /* 0:ip over lan side; 1:ip over wan side */
+	union {
+		fal_ip4_addr_t ip4_addr; /* ipv4 address */
+		fal_ip6_addr_t ip6_addr; /* ipv6 address */
+	} route_addr;
+	union {
+		fal_ip4_addr_t ip4_addr_mask; /* ipv4 address mask */
+		fal_ip6_addr_t ip6_addr_mask; /* ipv6 address mask */
+	} route_addr_mask;
+} fal_network_route_entry_t;
+
+typedef struct {
+	a_uint16_t mru; /* Maximum Receive Unit*/
+	a_uint16_t mtu; /* Maximum Transmission Unit*/
+	a_bool_t ttl_dec_bypass_en; /* Bypass TTL Decrement enable*/
+	a_bool_t ipv4_uc_route_en; /*0 for disble and 1 for enable*/
+	a_bool_t ipv6_uc_route_en; /*0 for disble and 1 for enable*/
+	a_bool_t icmp_trigger_en; /* ICMP trigger flag enable*/
+	fal_fwd_cmd_t ttl_exceed_action; /*action for ttl 0*/
+	a_bool_t ttl_exceed_deacclr_en; /*0 for disble and 1 for enable*/
+	a_uint8_t mac_addr_bitmap; /* bitmap for mac address*/
+	fal_mac_addr_t mac_addr; /* mac address */
+	fal_ip_counter_t counter; /* interface related counter */
+} fal_intf_entry_t;
+
+typedef struct
+{
+	a_bool_t l3_if_valid; /*0 for disable and 1 for enable*/
+	a_uint32_t l3_if_index; /*index for interface table*/        	  
+} fal_intf_id_t;
+
+typedef enum
+{
+	FAL_NEXTHOP_L3 = 0,
+	FAL_NEXTHOP_VP,
+} fal_nexthop_type_t;
+
+typedef struct
+{
+	fal_nexthop_type_t type; /* 0: L3 1:port*/
+	a_uint8_t vsi; /* output vsi value if type is 0 */
+	fal_port_t port; /* destination port */
+	a_uint32_t if_index; /* egress interface index */
+	a_bool_t ip_to_me_en; /* 0 for disable and 1 for enable*/
+	a_uint8_t pub_ip_index; /*index to public ip address*/
+	a_uint8_t stag_fmt; /* 0: untag 1:tagged*/
+	a_uint16_t svid; /*svlan id*/
+	a_int8_t ctag_fmt; /* 0: untag 1:tagged*/
+	a_uint16_t cvid; /* cvlan id */
+	fal_mac_addr_t mac_addr; /* mac address */
+	fal_ip4_addr_t dnat_ip; /*dnat ip address*/
+} fal_ip_nexthop_t;
+
+typedef struct
+{
+	a_bool_t ipv4_sg_en; /*0 for disable and 1 for enable*/
+	fal_fwd_cmd_t ipv4_sg_vio_action; /* check fail action for ipv4 source guard */
+	a_bool_t ipv4_sg_port_en; /* source port based ipv4 source guard enable */
+	a_bool_t ipv4_sg_svlan_en; /* source svlan based ipv4 source guard enable */
+	a_bool_t ipv4_sg_cvlan_en; /* source cvlan based ipv4 source guard enable */
+	fal_fwd_cmd_t ipv4_src_unk_action; /* unknown action for ipv4 source guard */
+	a_bool_t ipv6_sg_en; /*0 for disable and 1 for enable*/
+	fal_fwd_cmd_t ipv6_sg_vio_action; /* check fail action for ipv6 source guard */
+	a_bool_t ipv6_sg_port_en; /* source port based ipv6 source guard enable */
+	a_bool_t ipv6_sg_svlan_en; /* source svlan based ipv6 source guard enable */
+	a_bool_t ipv6_sg_cvlan_en; /* source cvlan based ipv6 source guard enable */
+	fal_fwd_cmd_t ipv6_src_unk_action; /* unknown action for ipv6 source guard */
+} fal_sg_cfg_t;
+
+typedef struct
+{
+	fal_ip4_addr_t pub_ip_addr; /*public ip address*/
+} fal_ip_pub_addr_t;
+
+typedef struct {
+	a_bool_t valid; /* valid flag */
+	fal_mac_addr_t mac_addr; /* mac address */
+} fal_macaddr_entry_t;
+
+typedef struct
+{
+	fal_fwd_cmd_t mru_fail_action; /*mru check fail action*/
+	a_bool_t mru_deacclr_en; /*0 for disable and 1 for enable*/
+	fal_fwd_cmd_t mtu_fail_action; /*mtu check fail action*/
+	a_bool_t mtu_deacclr_en; /*0 for disable and 1 for enable*/
+	fal_fwd_cmd_t mtu_nonfrag_fail_action; /*mtu check fail action for non-fragment */
+	a_bool_t mtu_df_deacclr_en; /*0 for disable and 1 for enable*/
+	fal_fwd_cmd_t prefix_bc_action; /*0 forward, 1 drop, 2 copy, 3 rdt_cpu*/
+	a_bool_t prefix_deacclr_en; /*0 for disable and 1 for enable*/
+	fal_fwd_cmd_t icmp_rdt_action; /*0 forward, 1 drop, 2 copy, 3 rdt_cpu*/
+	a_bool_t icmp_rdt_deacclr_en; /*0 for disable and 1 for enable*/
+	a_uint8_t hash_mode_0; /*0 crc10, 1 xor, 2 crc16*/
+	a_uint8_t hash_mode_1; /*0 crc10, 1 xor, 2 crc16*/
+} fal_ip_global_cfg_t;
+
+enum {
+	FUNC_IP_NETWORK_ROUTE_GET = 0,
+	FUNC_IP_HOST_ADD,
+	FUNC_IP_VSI_SG_CFG_GET,
+	FUNC_IP_PUB_ADDR_SET,
+	FUNC_IP_PORT_SG_CFG_SET,
+	FUNC_IP_PORT_INTF_GET,
+	FUNC_IP_VSI_ARP_SG_CFG_SET,
+	FUNC_IP_PUB_ADDR_GET,
+	FUNC_IP_PORT_INTF_SET,
+	FUNC_IP_VSI_SG_CFG_SET,
+	FUNC_IP_HOST_NEXT,
+	FUNC_IP_PORT_MACADDR_SET,
+	FUNC_IP_VSI_INTF_GET,
+	FUNC_IP_NETWORK_ROUTE_ADD,
+	FUNC_IP_PORT_SG_CFG_GET,
+	FUNC_IP_INTF_GET,
+	FUNC_IP_NETWORK_ROUTE_DEL,
+	FUNC_IP_HOST_DEL,
+	FUNC_IP_ROUTE_MISMATCH_GET,
+	FUNC_IP_VSI_ARP_SG_CFG_GET,
+	FUNC_IP_PORT_ARP_SG_CFG_SET,
+	FUNC_IP_VSI_MC_MODE_SET,
+	FUNC_IP_VSI_INTF_SET,
+	FUNC_IP_NEXTHOP_GET,
+	FUNC_IP_ROUTE_MISMATCH_SET,
+	FUNC_IP_HOST_GET,
+	FUNC_IP_INTF_SET,
+	FUNC_IP_VSI_MC_MODE_GET,
+	FUNC_IP_PORT_MACADDR_GET,
+	FUNC_IP_PORT_ARP_SG_CFG_GET,
+	FUNC_IP_NEXTHOP_SET,
+	FUNC_IP_GLOBAL_CTRL_GET,
+	FUNC_IP_GLOBAL_CTRL_SET,
+};
+
+#ifndef IN_IP_MINI
+sw_error_t
+fal_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry);
+
+sw_error_t
+fal_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                fal_host_entry_t * host_entry);
+
+sw_error_t
+fal_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                fal_host_entry_t * host_entry);
+
+sw_error_t
+fal_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                 fal_host_entry_t * host_entry);
+
+sw_error_t
+fal_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                         a_uint32_t cnt_id, a_bool_t enable);
+
+sw_error_t
+fal_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                       a_uint32_t pppoe_id, a_bool_t enable);
+
+sw_error_t
+fal_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_uint32_t flags);
+
+sw_error_t
+fal_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_uint32_t * flags);
+
+sw_error_t
+fal_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode);
+
+sw_error_t
+fal_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode);
+
+sw_error_t
+fal_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_source_guard_mode_t mode);
+
+sw_error_t
+fal_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_source_guard_mode_t * mode);
+
+sw_error_t
+fal_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_source_guard_mode_t mode);
+
+sw_error_t
+fal_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_source_guard_mode_t * mode);
+
+sw_error_t
+fal_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+sw_error_t
+fal_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+sw_error_t
+fal_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry);
+
+sw_error_t
+fal_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                      fal_intf_mac_entry_t * entry);
+
+sw_error_t
+fal_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                       fal_intf_mac_entry_t * entry);
+
+sw_error_t
+fal_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+sw_error_t
+fal_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+sw_error_t
+fal_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+sw_error_t
+fal_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+sw_error_t
+fal_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+sw_error_t
+fal_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+sw_error_t
+fal_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+
+sw_error_t
+fal_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+
+sw_error_t
+fal_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+sw_error_t
+fal_ip_rfs_ip4_rule_set(a_uint32_t dev_id, fal_ip4_rfs_t * rfs);
+
+sw_error_t
+fal_ip_rfs_ip6_rule_set(a_uint32_t dev_id, fal_ip6_rfs_t * rfs);
+
+sw_error_t
+fal_ip_rfs_ip4_rule_del(a_uint32_t dev_id, fal_ip4_rfs_t * rfs);
+
+sw_error_t
+fal_ip_rfs_ip6_rule_del(a_uint32_t dev_id, fal_ip6_rfs_t * rfs);
+
+sw_error_t
+fal_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+sw_error_t
+fal_ip_vrf_base_addr_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr);
+
+sw_error_t
+fal_ip_vrf_base_addr_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr);
+
+sw_error_t
+fal_ip_vrf_base_mask_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr);
+
+sw_error_t
+fal_ip_vrf_base_mask_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr);
+
+sw_error_t
+fal_ip_default_route_set(a_uint32_t dev_id, a_uint32_t droute_id,
+		fal_default_route_t * entry);
+
+sw_error_t
+fal_ip_default_route_get(a_uint32_t dev_id, a_uint32_t droute_id,
+		fal_default_route_t * entry);
+
+sw_error_t
+fal_ip_host_route_set(a_uint32_t dev_id, a_uint32_t hroute_id,
+		fal_host_route_t * entry);
+
+sw_error_t
+fal_ip_host_route_get(a_uint32_t dev_id, a_uint32_t hroute_id,
+		fal_host_route_t * entry);
+
+sw_error_t
+fal_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id,
+		fal_ip_wcmp_t * wcmp);
+
+sw_error_t
+fal_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id,
+		fal_ip_wcmp_t * wcmp);
+
+sw_error_t
+fal_default_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id,
+		fal_flow_type_t type, fal_default_flow_cmd_t cmd);
+
+sw_error_t
+fal_default_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id,
+		fal_flow_type_t type, fal_default_flow_cmd_t * cmd);
+
+sw_error_t
+fal_default_rt_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id,
+		fal_flow_type_t type, fal_default_flow_cmd_t cmd);
+
+sw_error_t
+fal_default_rt_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id,
+		fal_flow_type_t type, fal_default_flow_cmd_t * cmd);
+
+sw_error_t
+fal_ip_vsi_arp_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi,
+			fal_arp_sg_cfg_t *arp_sg_cfg);
+
+sw_error_t
+fal_ip_vsi_arp_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi,
+			fal_arp_sg_cfg_t *arp_sg_cfg);
+
+sw_error_t
+fal_ip_network_route_add(a_uint32_t dev_id, a_uint32_t index,
+			fal_network_route_entry_t *entry);
+
+sw_error_t
+fal_ip_network_route_get(a_uint32_t dev_id,
+			a_uint32_t index, a_uint8_t type,
+			fal_network_route_entry_t *entry);
+
+sw_error_t
+fal_ip_network_route_del(a_uint32_t dev_id,
+			a_uint32_t index, a_uint8_t type);
+
+sw_error_t
+fal_ip_intf_set(a_uint32_t dev_id,
+		a_uint32_t index,
+		fal_intf_entry_t *entry);
+
+sw_error_t
+fal_ip_intf_get(a_uint32_t dev_id,
+    		a_uint32_t index,
+    		fal_intf_entry_t *entry);
+
+sw_error_t
+fal_ip_vsi_intf_set(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id);
+
+sw_error_t
+fal_ip_vsi_intf_get(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id);
+
+sw_error_t
+fal_ip_port_intf_set(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id);
+
+sw_error_t
+fal_ip_port_intf_get(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id);
+
+sw_error_t
+fal_ip_nexthop_set(a_uint32_t dev_id, a_uint32_t index,
+			fal_ip_nexthop_t *entry);
+
+sw_error_t
+fal_ip_nexthop_get(a_uint32_t dev_id, a_uint32_t index,
+			fal_ip_nexthop_t *entry);
+
+sw_error_t
+fal_ip_vsi_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi,
+			fal_sg_cfg_t *sg_cfg);
+
+sw_error_t
+fal_ip_vsi_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi,
+			fal_sg_cfg_t *sg_cfg);
+
+sw_error_t
+fal_ip_port_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
+			fal_sg_cfg_t *sg_cfg);
+
+sw_error_t
+fal_ip_port_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
+			fal_sg_cfg_t *sg_cfg);
+
+sw_error_t
+fal_ip_pub_addr_set(a_uint32_t dev_id, a_uint32_t index,
+			fal_ip_pub_addr_t *entry);
+
+sw_error_t
+fal_ip_pub_addr_get(a_uint32_t dev_id, a_uint32_t index,
+			fal_ip_pub_addr_t *entry);
+
+sw_error_t
+fal_ip_port_macaddr_set(a_uint32_t dev_id, fal_port_t port_id,
+			fal_macaddr_entry_t *macaddr);
+
+sw_error_t
+fal_ip_port_macaddr_get(a_uint32_t dev_id, fal_port_t port_id,
+			fal_macaddr_entry_t *macaddr);
+
+sw_error_t
+fal_ip_route_mismatch_action_set(a_uint32_t dev_id, fal_fwd_cmd_t action);
+
+sw_error_t
+fal_ip_route_mismatch_action_get(a_uint32_t dev_id, fal_fwd_cmd_t *action);
+
+sw_error_t
+fal_ip_port_arp_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
+			fal_arp_sg_cfg_t *arp_sg_cfg);
+
+sw_error_t
+fal_ip_port_arp_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
+			fal_arp_sg_cfg_t *arp_sg_cfg);
+
+sw_error_t
+fal_ip_vsi_mc_mode_set(a_uint32_t dev_id, a_uint32_t vsi,
+			fal_mc_mode_cfg_t *cfg);
+
+sw_error_t
+fal_ip_vsi_mc_mode_get(a_uint32_t dev_id, a_uint32_t vsi,
+			fal_mc_mode_cfg_t *cfg);
+
+sw_error_t
+fal_ip_global_ctrl_get(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg);
+
+sw_error_t
+fal_ip_global_ctrl_set(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_IP_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_leaky.h b/qca-ssdk/include/fal/fal_leaky.h
new file mode 100755
index 0000000..01ad94e
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_leaky.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_leaky FAL_LEAKY
+ * @{
+ */
+#ifndef _FAL_LEAKY_H_
+#define _FAL_LEAKY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+    /**
+    @brief This enum defines the leaky control mode.
+    */
+    typedef enum {
+        FAL_LEAKY_PORT_CTRL = 0,        /**<   control leaky through port which packets received*/
+        FAL_LEAKY_FDB_CTRL,             /**<   control leaky through fdb entry*/
+        FAL_LEAKY_CTRL_MODE_BUTT
+    }
+    fal_leaky_ctrl_mode_t;
+
+
+
+    sw_error_t
+    fal_uc_leaky_mode_set(a_uint32_t dev_id,
+                          fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+
+    sw_error_t
+    fal_uc_leaky_mode_get(a_uint32_t dev_id,
+                          fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+
+    sw_error_t
+    fal_mc_leaky_mode_set(a_uint32_t dev_id,
+                          fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+
+    sw_error_t
+    fal_mc_leaky_mode_get(a_uint32_t dev_id,
+                          fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+
+    sw_error_t
+    fal_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable);
+
+
+
+    sw_error_t
+    fal_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable);
+
+
+
+    sw_error_t
+    fal_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable);
+
+
+
+    sw_error_t
+    fal_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable);
+
+
+
+    sw_error_t
+    fal_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable);
+
+
+
+    sw_error_t
+    fal_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable);
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_LEAKY_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_led.h b/qca-ssdk/include/fal/fal_led.h
new file mode 100644
index 0000000..45d59df
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_led.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2012,2018,2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_led FAL_LED
+ * @{
+ */
+#ifndef _FAL_LED_H_
+#define _FAL_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+    /**
+    @brief This enum defines the led group.
+    */
+    typedef enum {
+        LED_LAN_PORT_GROUP = 0,   /**<   control lan ports*/
+        LED_WAN_PORT_GROUP,       /**<   control wan ports*/
+        LED_MAC_PORT_GROUP,       /**<   control mac ports*/
+        LED_GROUP_BUTT
+    }
+    led_pattern_group_t;
+
+    /**
+    @brief This enum defines the led pattern id, each ports has three led
+           and pattern0 relates to led0, pattern1 relates to led1, pattern2 relates to led2.
+    */
+    typedef a_uint32_t led_pattern_id_t;
+
+
+    /**
+    @brief This enum defines the led control pattern mode.
+    */
+    typedef enum
+    {
+        LED_ALWAYS_OFF = 0,
+        LED_ALWAYS_BLINK,
+        LED_ALWAYS_ON,
+        LED_PATTERN_MAP_EN,
+        LED_PATTERN_MODE_BUTT
+    } led_pattern_mode_t;
+
+
+#define     FULL_DUPLEX_LIGHT_EN   0
+#define     HALF_DUPLEX_LIGHT_EN   1
+#define     POWER_ON_LIGHT_EN      2
+#define     LINK_1000M_LIGHT_EN    3
+#define     LINK_100M_LIGHT_EN     4
+#define     LINK_10M_LIGHT_EN      5
+#define     COLLISION_BLINK_EN     6
+#define     RX_TRAFFIC_BLINK_EN    7
+#define     TX_TRAFFIC_BLINK_EN    8
+#define     LINKUP_OVERRIDE_EN     9
+#define     LED_ACTIVE_HIGH        10
+#define     LINK_2500M_LIGHT_EN    11
+#define     LED_MAP_10M_SPEED \
+    (BIT(POWER_ON_LIGHT_EN) | BIT(LINK_10M_LIGHT_EN) | BIT(COLLISION_BLINK_EN) |\
+    BIT(RX_TRAFFIC_BLINK_EN) | BIT(TX_TRAFFIC_BLINK_EN) | BIT(LINKUP_OVERRIDE_EN))
+#define     LED_MAP_100M_SPEED \
+    (BIT(POWER_ON_LIGHT_EN) | BIT(LINK_100M_LIGHT_EN) | BIT(COLLISION_BLINK_EN) |\
+    BIT(RX_TRAFFIC_BLINK_EN) | BIT(TX_TRAFFIC_BLINK_EN) | BIT(LINKUP_OVERRIDE_EN))
+#define     LED_MAP_1000M_SPEED \
+    (BIT(POWER_ON_LIGHT_EN) | BIT(LINK_1000M_LIGHT_EN) | BIT(COLLISION_BLINK_EN) |\
+    BIT(RX_TRAFFIC_BLINK_EN) | BIT(TX_TRAFFIC_BLINK_EN) | BIT(LINKUP_OVERRIDE_EN))
+#define     LED_MAP_2500M_SPEED \
+    (BIT(POWER_ON_LIGHT_EN) | BIT(LINK_2500M_LIGHT_EN) | BIT(COLLISION_BLINK_EN) |\
+    BIT(RX_TRAFFIC_BLINK_EN) | BIT(TX_TRAFFIC_BLINK_EN) | BIT(LINKUP_OVERRIDE_EN))
+#define     LED_MAP_ALL_SPEED \
+    (LED_MAP_10M_SPEED | LED_MAP_100M_SPEED | LED_MAP_1000M_SPEED |\
+    LED_MAP_2500M_SPEED)
+
+#define     PORT_LED_SOURCE_MAX    0x3
+
+    /**
+    @brief This enum defines the led control pattern map.
+    */
+    typedef a_uint32_t led_pattern_map_t;
+
+
+    /**
+    @brief This enum defines the led control pattern mode.
+    */
+    typedef enum
+    {
+        LED_BLINK_2HZ = 0,
+        LED_BLINK_4HZ,
+        LED_BLINK_8HZ,
+        LED_BLINK_TXRX,    /**< Frequency relates to speed, 1000M-8HZ,100M->4HZ,10M->2HZ,Others->4HZ */
+        LED_BLINK_FREQ_BUTT
+    } led_blink_freq_t;
+
+
+    typedef struct
+    {
+        led_pattern_mode_t  mode;
+        led_pattern_map_t   map;
+        led_blink_freq_t    freq;
+    } led_ctrl_pattern_t;
+
+
+
+
+
+    sw_error_t
+    fal_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                             led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+
+
+    sw_error_t
+    fal_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                             led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+	sw_error_t
+	fal_led_source_pattern_set(a_uint32_t dev_id, a_uint32_t source_id,
+                            led_ctrl_pattern_t * pattern);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_LED_H_ */
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/fal/fal_mib.h b/qca-ssdk/include/fal/fal_mib.h
new file mode 100755
index 0000000..b4b59ff
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_mib.h
@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_mib FAL_MIB
+ * @{
+ */
+#ifndef _FAL_MIB_H
+#define _FAL_MIB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+    /**@brief This structure defines the mib infomation.
+    */
+    typedef struct
+    {
+        a_uint32_t RxBroad;
+        a_uint32_t RxPause;
+        a_uint32_t RxMulti;
+        a_uint32_t RxFcsErr;
+        a_uint32_t RxAllignErr;
+        a_uint32_t RxRunt;
+        a_uint32_t RxFragment;
+        a_uint32_t Rx64Byte;
+        a_uint32_t Rx128Byte;
+        a_uint32_t Rx256Byte;
+        a_uint32_t Rx512Byte;
+        a_uint32_t Rx1024Byte;
+        a_uint32_t Rx1518Byte;
+        a_uint32_t RxMaxByte;
+        a_uint32_t RxTooLong;
+        a_uint32_t RxGoodByte_lo;       /**<  low 32 bits of RxGoodByte statistc item */
+        a_uint32_t RxGoodByte_hi;       /**<   high 32 bits of RxGoodByte statistc item*/
+        a_uint32_t RxBadByte_lo;        /**<   low 32 bits of RxBadByte statistc item */
+        a_uint32_t RxBadByte_hi;        /**<   high 32 bits of RxBadByte statistc item */
+        a_uint32_t RxOverFlow;		/* no this counter for Hawkeye*/
+        a_uint32_t Filtered;			/*no this counter for Hawkeye*/
+        a_uint32_t TxBroad;
+        a_uint32_t TxPause;
+        a_uint32_t TxMulti;
+        a_uint32_t TxUnderRun;
+        a_uint32_t Tx64Byte;
+        a_uint32_t Tx128Byte;
+        a_uint32_t Tx256Byte;
+        a_uint32_t Tx512Byte;
+        a_uint32_t Tx1024Byte;
+        a_uint32_t Tx1518Byte;
+        a_uint32_t TxMaxByte;
+        a_uint32_t TxOverSize;	/*no this counter for Hawkeye*/
+        a_uint32_t TxByte_lo;       /**<  low 32 bits of TxByte statistc item */
+        a_uint32_t TxByte_hi;       /**<  high 32 bits of TxByte statistc item */
+        a_uint32_t TxCollision;
+        a_uint32_t TxAbortCol;
+        a_uint32_t TxMultiCol;
+        a_uint32_t TxSingalCol;
+        a_uint32_t TxExcDefer;
+        a_uint32_t TxDefer;
+        a_uint32_t TxLateCol;
+        a_uint32_t RxUniCast;
+        a_uint32_t TxUniCast;
+        a_uint32_t RxJumboFcsErr;	/* add for  Hawkeye*/
+        a_uint32_t RxJumboAligenErr;		/* add for Hawkeye*/
+        a_uint32_t Rx14To63;	/*add for ipq60xx lpbk port*/
+        a_uint32_t RxTooLongByte_lo;	/*add for ipq60xx lpbk port*/
+        a_uint32_t RxTooLongByte_hi;	/*add for ipq60xx lpbk port*/
+        a_uint32_t RxRuntByte_lo;	/*add for ipq60xx lpbk port*/
+        a_uint32_t RxRuntByte_hi;	/*add for ipq60xx lpbk port*/
+    } fal_mib_info_t;
+
+/*define structure for software with 64bit*/
+typedef struct
+{
+	a_uint64_t RxBroad;
+	a_uint64_t RxPause;
+	a_uint64_t RxMulti;
+	a_uint64_t RxFcsErr;
+	a_uint64_t RxAllignErr;
+	a_uint64_t RxRunt;
+	a_uint64_t RxFragment;
+	a_uint64_t Rx64Byte;
+	a_uint64_t Rx128Byte;
+	a_uint64_t Rx256Byte;
+	a_uint64_t Rx512Byte;
+	a_uint64_t Rx1024Byte;
+	a_uint64_t Rx1518Byte;
+	a_uint64_t RxMaxByte;
+	a_uint64_t RxTooLong;
+	a_uint64_t RxGoodByte;
+	a_uint64_t RxBadByte;
+	a_uint64_t RxOverFlow;		/* no this counter for Hawkeye*/
+	a_uint64_t Filtered;			/*no this counter for Hawkeye*/
+	a_uint64_t TxBroad;
+	a_uint64_t TxPause;
+	a_uint64_t TxMulti;
+	a_uint64_t TxUnderRun;
+	a_uint64_t Tx64Byte;
+	a_uint64_t Tx128Byte;
+	a_uint64_t Tx256Byte;
+	a_uint64_t Tx512Byte;
+	a_uint64_t Tx1024Byte;
+	a_uint64_t Tx1518Byte;
+	a_uint64_t TxMaxByte;
+	a_uint64_t TxOverSize;	/*no this counter for Hawkeye*/
+	a_uint64_t TxByte;
+	a_uint64_t TxCollision;
+	a_uint64_t TxAbortCol;
+	a_uint64_t TxMultiCol;
+	a_uint64_t TxSingalCol;
+	a_uint64_t TxExcDefer;
+	a_uint64_t TxDefer;
+	a_uint64_t TxLateCol;
+	a_uint64_t RxUniCast;
+	a_uint64_t TxUniCast;
+	a_uint64_t RxJumboFcsErr;	/* add for  Hawkeye*/
+	a_uint64_t RxJumboAligenErr;	/* add for Hawkeye*/
+	a_uint64_t Rx14To63;	/*add for ipq60xx lpbk port*/
+	a_uint64_t RxTooLongByte;	/*add for ipq60xx lpbk port*/
+	a_uint64_t RxRuntByte;	/*add for ipq60xx lpbk port*/
+} fal_mib_counter_t;
+
+enum
+{
+	/*mib*/
+	FUNC_GET_MIB_INFO = 0,
+	FUNC_GET_RX_MIB_INFO,
+	FUNC_GET_TX_MIB_INFO,
+	FUNC_GET_XGMIB_INFO,
+	FUNC_GET_TX_XGMIB_INFO,
+	FUNC_GET_RX_XGMIB_INFO,
+	FUNC_MIB_STATUS_SET,
+	FUNC_MIB_STATUS_GET,
+	FUNC_MIB_PORT_FLUSH_COUNTERS,
+	FUNC_MIB_CPUKEEP_SET,
+	FUNC_MIB_CPUKEEP_GET
+};
+
+typedef struct
+{
+	a_uint64_t	RxFrame;
+	a_uint64_t	RxByte;
+	a_uint64_t	RxByteGood;
+	a_uint64_t	RxBroadGood;
+	a_uint64_t	RxMultiGood;
+	a_uint64_t	RxFcsErr;
+	a_uint64_t	RxRuntErr ;
+	a_uint64_t	RxJabberError;
+	a_uint64_t	RxUndersizeGood;
+	a_uint64_t	RxOversizeGood;
+	a_uint64_t	Rx64Byte;
+	a_uint64_t	Rx128Byte;
+	a_uint64_t	Rx256Byte;
+	a_uint64_t	Rx512Byte;
+	a_uint64_t	Rx1024Byte;
+	a_uint64_t	RxMaxByte;
+	a_uint64_t	RxUnicastGood;
+	a_uint64_t	RxLengthError;
+	a_uint64_t	RxOutOfRangeError;
+	a_uint64_t	RxPause;
+	a_uint64_t	RxOverFlow;
+	a_uint64_t	RxVLANFrameGoodBad;
+	a_uint64_t	RxWatchDogError;
+	a_uint64_t	RxLPIUsec;
+	a_uint64_t	RxLPITran;
+	a_uint64_t	RxDropFrameGoodBad;
+	a_uint64_t	RxDropByteGoodBad;
+
+	a_uint64_t	TxByte;
+	a_uint64_t	TxFrame;
+	a_uint64_t	TxBroadGood;
+	a_uint64_t	TxMultiGood;
+	a_uint64_t	Tx64Byte;
+	a_uint64_t	Tx128Byte;
+	a_uint64_t	Tx256Byte;
+	a_uint64_t	Tx512Byte;
+	a_uint64_t	Tx1024Byte;
+	a_uint64_t	TxMaxByte;
+	a_uint64_t	TxUnicast;
+	a_uint64_t	TxMulti;
+	a_uint64_t	TxBroad;
+	a_uint64_t	TxUnderFlowError;
+	a_uint64_t	TxByteGood;
+	a_uint64_t	TxFrameGood;
+	a_uint64_t	TxPause;
+	a_uint64_t	TxVLANFrameGood;
+	a_uint64_t	TxLPIUsec;
+	a_uint64_t	TxLPITran;
+} fal_xgmib_info_t;
+
+sw_error_t
+fal_get_xgmib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_xgmib_info_t * mib_info );
+
+sw_error_t
+fal_get_rx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_xgmib_info_t * mib_info );
+
+sw_error_t
+fal_get_tx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_xgmib_info_t * mib_info );
+
+sw_error_t
+fal_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_mib_info_t * mib_info );
+
+sw_error_t
+fal_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_mib_info_t * mib_info );
+
+sw_error_t
+fal_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_mib_info_t * mib_info );
+
+sw_error_t
+fal_mib_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+sw_error_t
+fal_mib_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+sw_error_t
+fal_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id);
+
+sw_error_t
+fal_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t  enable);
+
+sw_error_t
+fal_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable);
+
+sw_error_t
+fal_mib_counter_alloc(a_uint32_t dev_id, a_uint64_t **p_mibcounter);
+
+sw_error_t
+fal_mib_counter_get(a_uint32_t dev_id, fal_port_t port_id,
+				fal_mib_counter_t *mib_counter);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _FAL_MIB_H */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_mirror.h b/qca-ssdk/include/fal/fal_mirror.h
new file mode 100755
index 0000000..51158d7
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_mirror.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_mirror FAL_MIRROR
+ * @{
+ */
+#ifndef _FAL_MIRROR_H_
+#define _FAL_MIRROR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+typedef struct
+{
+	fal_port_t port_id;
+	a_uint32_t priority;
+} fal_mirr_analysis_config_t;
+
+typedef enum
+{
+	FAL_MIRR_INGRESS= 0,
+	FAL_MIRR_EGRESS,
+	FAL_MIRR_BOTH,
+} fal_mirr_direction_t;
+
+enum
+{
+	FUNC_MIRR_ANALYSIS_PORT_SET = 0,
+	FUNC_MIRR_ANALYSIS_PORT_GET,
+	FUNC_MIRR_PORT_IN_SET,
+	FUNC_MIRR_PORT_IN_GET,
+	FUNC_MIRR_PORT_EG_SET,
+	FUNC_MIRR_PORT_EG_GET,
+	FUNC_MIRR_ANALYSIS_CONFIG_SET,
+	FUNC_MIRR_ANALYSIS_CONFIG_GET,
+};
+
+sw_error_t
+fal_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id);
+
+sw_error_t
+fal_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id);
+
+sw_error_t
+fal_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id,
+			a_bool_t enable);
+sw_error_t
+fal_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+			a_bool_t * enable);
+sw_error_t
+fal_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id,
+			a_bool_t enable);
+sw_error_t
+fal_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id,
+			a_bool_t * enable);
+
+sw_error_t
+fal_mirr_analysis_config_set(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config);
+
+sw_error_t
+fal_mirr_analysis_config_get(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _PORT_MIRROR_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_misc.h b/qca-ssdk/include/fal/fal_misc.h
new file mode 100755
index 0000000..c25d744
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_misc.h
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_gen FAL_MISC
+ * @{
+ */
+#ifndef _FAL_MISC_H_
+#define _FAL_MISC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+
+    typedef enum
+    {
+        FAL_LOOP_CHECK_1MS = 0,
+        FAL_LOOP_CHECK_10MS,
+        FAL_LOOP_CHECK_100MS,
+        FAL_LOOP_CHECK_500MS,
+    } fal_loop_check_time_t;
+
+	typedef struct
+	{
+		a_bool_t rx_counter_en; /* Enable/disable virtual port rx counter */
+		a_bool_t vp_uni_tx_counter_en; /* Enable/disable virtual port unicast tx counter */
+		a_bool_t port_mc_tx_counter_en; /* Enable/disable physical port multicast tx counter */
+		a_bool_t port_tx_counter_en; /* Enable/disable physical port tx counter */
+	} fal_counter_en_t;
+
+	sw_error_t
+	fal_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id, fal_counter_en_t * cnt_en);
+
+	sw_error_t
+	fal_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id, fal_counter_en_t * cnt_en);
+
+    /* define switch interrupt type bitmap */
+#define FAL_SWITCH_INTR_LINK_STATUS      0x1  /* up/down/speed/duplex status */
+#ifndef IN_MISC_MINI
+    sw_error_t fal_arp_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+    sw_error_t fal_arp_status_get(a_uint32_t dev_id, a_bool_t * enable);
+#endif
+
+
+    sw_error_t fal_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size);
+
+
+
+    sw_error_t fal_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size);
+
+
+
+    sw_error_t
+    fal_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_fwd_cmd_t cmd);
+
+    sw_error_t
+    fal_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable);
+
+	sw_error_t
+    fal_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable);
+
+	sw_error_t
+    fal_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable);
+
+    sw_error_t
+    fal_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_fwd_cmd_t * cmd);
+
+    sw_error_t
+    fal_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable);
+
+    sw_error_t
+    fal_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable);
+
+
+    sw_error_t
+    fal_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable);
+
+
+    sw_error_t
+    fal_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+#ifndef IN_MISC_MINI
+    sw_error_t
+    fal_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+
+    sw_error_t
+    fal_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+    sw_error_t
+    fal_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+
+    sw_error_t
+    fal_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+    sw_error_t
+    fal_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    sw_error_t
+    fal_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    sw_error_t
+    fal_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+#endif
+
+    sw_error_t
+    fal_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+#ifndef IN_MISC_MINI
+    sw_error_t
+    fal_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+#endif
+    sw_error_t
+    fal_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+#ifndef IN_MISC_MINI
+    sw_error_t
+    fal_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+    sw_error_t
+    fal_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    sw_error_t
+    fal_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    sw_error_t
+    fal_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    sw_error_t
+    fal_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    sw_error_t
+    fal_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    sw_error_t
+    fal_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    sw_error_t
+    fal_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask);
+
+
+    sw_error_t
+    fal_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask);
+
+
+    sw_error_t
+    fal_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status);
+
+
+    sw_error_t
+    fal_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status);
+
+
+    sw_error_t
+    fal_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask);
+
+
+    sw_error_t
+    fal_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask);
+
+
+    sw_error_t
+    fal_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask);
+
+
+    sw_error_t
+    fal_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+
+    sw_error_t
+    fal_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+    sw_error_t
+    fal_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t *port_bitmap);
+
+    sw_error_t
+    fal_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable);
+
+    sw_error_t
+    fal_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    sw_error_t
+    fal_intr_status_mac_linkchg_clear(a_uint32_t dev_id);
+
+	sw_error_t
+    fal_global_macaddr_set(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+	sw_error_t
+    fal_global_macaddr_get(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+
+	sw_error_t
+	fal_lldp_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+	sw_error_t
+	fal_lldp_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+	sw_error_t
+	fal_frame_crc_reserve_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+	sw_error_t
+	fal_frame_crc_reserve_get(a_uint32_t dev_id, a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_MISC_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_multi.h b/qca-ssdk/include/fal/fal_multi.h
new file mode 100755
index 0000000..30b727f
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_multi.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _FAL_MULTI_H_
+#define _FAL_MULTI_H_
+
+/*supports 32 entries*/
+#define FAL_IGMP_SG_ENTRY_MAX 32
+
+typedef enum
+{
+    FAL_ADDR_IPV4 = 0,
+    FAL_ADDR_IPV6
+} fal_addr_type_t;
+
+typedef struct
+{
+    fal_addr_type_t type;
+    union
+    {
+        fal_ip4_addr_t ip4_addr;
+        fal_ip6_addr_t ip6_addr;
+    } u;
+} fal_igmp_sg_addr_t;
+
+typedef struct
+{
+    fal_igmp_sg_addr_t source;
+    fal_igmp_sg_addr_t group;
+    fal_pbmp_t port_map;
+    a_uint32_t vlan_id;
+} fal_igmp_sg_entry_t;
+
+//#define MULTI_DEBUG_
+#ifdef MULTI_DEBUG_
+#define MULTI_DEBUG(x...) aos_printk(x)
+#else
+#define MULTI_DEBUG(x...)
+#endif
+
+#define FAL_ACL_LIST_MULTICAST 55
+#define FAL_MULTICAST_PRI   5
+
+#define MULT_ACTION_SET      0
+#define MULT_ACTION_CLEAR    1
+
+// static a_uint32_t rule_nr=1;
+
+typedef struct
+{
+    a_uint8_t index; //MAX is 32
+    fal_igmp_sg_entry_t entry; //Stores the specific ACL rule info
+} multi_acl_info_t;
+
+typedef struct
+{
+    a_uint8_t cnt; //MAX is 32
+    multi_acl_info_t acl_info[FAL_IGMP_SG_ENTRY_MAX]; //Stores the all ACL rule info
+} fal_igmp_sg_info_t;
+
+#endif
diff --git a/qca-ssdk/include/fal/fal_nat.h b/qca-ssdk/include/fal/fal_nat.h
new file mode 100755
index 0000000..643919c
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_nat.h
@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2012, 2015,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_nat FAL_NAT
+ * @{
+ */
+#ifndef _FAL_NAT_H_
+#define _FAL_NAT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+
+#define FAL_NAT_ENTRY_PROTOCOL_TCP         0x1
+#define FAL_NAT_ENTRY_PROTOCOL_UDP         0x2
+#define FAL_NAT_ENTRY_PROTOCOL_PPTP        0x4
+#define FAL_NAT_ENTRY_PROTOCOL_ANY         0x8
+#define FAL_NAT_ENTRY_TRANS_IPADDR_INDEX   0x10
+#define FAL_NAT_ENTRY_PORT_CHECK           0x20
+#define FAL_NAT_HASH_KEY_PORT              0x40
+#define FAL_NAT_HASH_KEY_IPADDR            0x80
+
+
+    /* NAT entry operation flags */
+#define FAL_NAT_ENTRY_ID_EN                 0x1
+#define FAL_NAT_ENTRY_SRC_IPADDR_EN         0x2
+#define FAL_NAT_ENTRY_TRANS_IPADDR_EN       0x4
+#define FAL_NAT_ENTRY_KEY_EN                0x8
+#define FAL_NAT_ENTRY_PUBLIC_IP_EN          0x10
+#define FAL_NAT_ENTRY_SOURCE_IP_EN          0x20
+#define FAL_NAT_ENTRY_AGE_EN                0x40
+#define FAL_NAT_ENTRY_SYNC_EN               0x80
+
+
+    typedef struct
+    {
+        a_uint32_t     entry_id;
+        a_uint32_t     flags;
+        a_uint32_t     status;
+        fal_ip4_addr_t src_addr;
+        fal_ip4_addr_t dst_addr;
+        a_uint16_t     src_port;
+        a_uint16_t     dst_port;
+        fal_ip4_addr_t trans_addr;
+        a_uint16_t     trans_port;
+        a_uint16_t     rsv;
+        a_bool_t       mirror_en;
+        a_bool_t       counter_en;
+        a_uint32_t     counter_id;
+        a_uint32_t     ingress_packet;
+        a_uint32_t     ingress_byte;
+        a_uint32_t     egress_packet;
+        a_uint32_t     egress_byte;
+        fal_fwd_cmd_t  action;
+		a_uint32_t     load_balance;
+		a_uint32_t     flow_cookie;
+		a_uint32_t     vrf_id;
+		a_uint32_t     aging_sync;
+		a_bool_t       priority_en;
+		a_uint32_t     priority_val;
+    } fal_napt_entry_t;
+
+	typedef struct
+    {
+        a_uint32_t     proto;  /*1 tcp; 2 udp*/
+        fal_ip4_addr_t src_addr;
+        fal_ip4_addr_t dst_addr;
+        a_uint16_t     src_port;
+        a_uint16_t     dst_port;
+		a_uint32_t     flow_cookie;
+    } fal_flow_cookie_t;
+
+	typedef struct
+    {
+        a_uint32_t     proto;  /*1 tcp; 2 udp*/
+        fal_ip4_addr_t src_addr;
+        fal_ip4_addr_t dst_addr;
+        a_uint16_t     src_port;
+        a_uint16_t     dst_port;
+		a_uint8_t     load_balance;
+    } fal_flow_rfs_t;
+
+
+    typedef struct
+    {
+        a_uint32_t     entry_id;
+        a_uint32_t     flags;
+        a_uint32_t     status;
+        fal_ip4_addr_t src_addr;
+        fal_ip4_addr_t trans_addr;
+        a_uint16_t     port_num;
+        a_uint16_t     port_range;
+        a_uint32_t     slct_idx;
+        a_bool_t       mirror_en;
+        a_bool_t       counter_en;
+        a_uint32_t     counter_id;
+        a_uint32_t     ingress_packet;
+        a_uint32_t     ingress_byte;
+        a_uint32_t     egress_packet;
+        a_uint32_t     egress_byte;
+        fal_fwd_cmd_t  action;
+		a_uint32_t     vrf_id;
+    } fal_nat_entry_t;
+
+
+    typedef enum
+    {
+        FAL_NAPT_FULL_CONE = 0,
+        FAL_NAPT_STRICT_CONE,
+        FAL_NAPT_PORT_STRICT,
+        FAL_NAPT_SYNMETRIC,
+    } fal_napt_mode_t;
+
+
+    typedef struct
+    {
+        a_uint32_t     entry_id;
+        fal_ip4_addr_t pub_addr;
+    } fal_nat_pub_addr_t;
+
+
+    sw_error_t
+    fal_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry);
+
+
+    sw_error_t
+    fal_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_entry_t * nat_entry);
+
+
+    sw_error_t
+    fal_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * nat_entry);
+
+
+    sw_error_t
+    fal_nat_next(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * nat_entry);
+
+
+    sw_error_t
+    fal_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, a_bool_t enable);
+
+
+    sw_error_t
+    fal_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry);
+
+
+    sw_error_t
+    fal_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * napt_entry);
+
+
+    sw_error_t
+    fal_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * napt_entry);
+
+
+    sw_error_t
+    fal_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_napt_entry_t * napt_entry);
+
+
+    sw_error_t
+    fal_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, a_bool_t enable);
+
+
+    sw_error_t
+    fal_flow_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry);
+
+	sw_error_t
+    fal_flow_cookie_set(a_uint32_t dev_id, fal_flow_cookie_t * flow_cookie);
+
+	sw_error_t
+	fal_flow_rfs_set(a_uint32_t dev_id, a_uint8_t action, fal_flow_rfs_t * rfs);
+
+    sw_error_t
+    fal_flow_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * napt_entry);
+
+
+    sw_error_t
+    fal_flow_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * napt_entry);
+
+
+    sw_error_t
+    fal_flow_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_napt_entry_t * napt_entry);
+
+
+    sw_error_t
+    fal_flow_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, a_bool_t enable);
+
+
+    sw_error_t
+    fal_nat_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    sw_error_t
+    fal_nat_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    sw_error_t
+    fal_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode);
+
+
+    sw_error_t
+    fal_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode);
+
+
+    sw_error_t
+    fal_napt_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    sw_error_t
+    fal_napt_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    sw_error_t
+    fal_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode);
+
+
+    sw_error_t
+    fal_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode);
+
+
+    sw_error_t
+    fal_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode);
+
+
+    sw_error_t
+    fal_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+
+    sw_error_t
+    fal_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+    sw_error_t
+    fal_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+    sw_error_t
+    fal_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+
+    sw_error_t
+    fal_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en);
+
+
+    sw_error_t
+    fal_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en);
+
+
+    sw_error_t
+    fal_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry);
+
+
+    sw_error_t
+    fal_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_pub_addr_t * entry);
+
+
+    sw_error_t
+    fal_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_nat_pub_addr_t * entry);
+
+
+    sw_error_t
+    fal_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    sw_error_t
+    fal_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+    sw_error_t
+    fal_nat_global_set(a_uint32_t dev_id, a_bool_t enable,
+    		a_bool_t sync_cnt_enable, a_uint32_t portbmp);
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_NAT_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/fal/fal_policer.h b/qca-ssdk/include/fal/fal_policer.h
new file mode 100755
index 0000000..b54092c
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_policer.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2016-2018, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_policer FAL_POLICER
+ * @{
+ */
+#ifndef _FAL_POLICER_H_
+#define _FAL_POLICER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+typedef struct
+{
+	a_bool_t		meter_en;	/* meter enable or disable */
+	a_bool_t		couple_en;	/*  two buckets coupling enable or disable*/
+	a_uint32_t	color_mode;	/* color aware or color blind */
+	a_uint32_t	frame_type;	/* frame type, bit0:unicast;bit1: unkown unicast;bit2:multicast;bit3: unknown multicast; bit4:broadcast */
+	a_uint32_t 	meter_mode;
+	a_uint32_t	meter_unit; /* 0:byte based; 1:packet based*/
+	a_uint32_t	cir;	/* committed information rate */
+	a_uint32_t	cbs;	/* committed burst size */
+	a_uint32_t	eir; /* excess information rate */
+	a_uint32_t	ebs; /* excess burst size */
+} fal_policer_config_t;
+
+typedef struct
+{
+	a_bool_t yellow_priority_en; /* yellow traffic internal priority change enable*/
+	a_bool_t yellow_drop_priority_en; /* yellow traffic internal drop priority change enable*/
+	a_bool_t yellow_pcp_en; /* yellow traffic pcp change enable*/
+	a_bool_t yellow_dei_en; /* yellow traffic dei change enable*/
+	a_uint32_t yellow_priority; /* yellow traffic internal priority value*/
+	a_uint32_t yellow_drop_priority; /* yellow traffic internal drop priority value*/
+	a_uint32_t yellow_pcp; /* yellow traffic pcp value*/
+	a_uint32_t yellow_dei; /* yellow traffic dei value*/
+	fal_fwd_cmd_t red_action; /* red traffic drop or forward*/
+	a_bool_t red_priority_en; /* red traffic internal priority change enable*/
+	a_bool_t red_drop_priority_en; /* red traffic internal drop priority change enable*/
+	a_bool_t red_pcp_en; /* red traffic pcp change enable*/
+	a_bool_t red_dei_en; /* red traffic dei change enable*/
+	a_uint32_t red_priority; /* red traffic internal priority value*/
+	a_uint32_t red_drop_priority; /* red traffic internal drop priority value*/
+	a_uint32_t red_pcp; /* red traffic pcp value*/
+	a_uint32_t red_dei;  /* red traffic dei value*/
+}fal_policer_action_t;
+
+typedef struct
+{
+    a_uint32_t green_packet_counter; /*green packet counter */
+    a_uint64_t green_byte_counter; /*green byte counter */
+    a_uint32_t yellow_packet_counter; /*yellow packet counter */
+    a_uint64_t yellow_byte_counter; /*yellow byte counter */
+    a_uint32_t red_packet_counter; /*red packet counter */
+    a_uint64_t red_byte_counter; /*red byte counter */
+} fal_policer_counter_t;
+
+typedef struct
+{
+    a_uint32_t policer_drop_packet_counter; /*drop packet counter by policer*/
+    a_uint64_t policer_drop_byte_counter; /*drop byte counter by policer */
+    a_uint32_t policer_forward_packet_counter; /*forward packet counter by policer*/
+    a_uint64_t policer_forward_byte_counter; /*forward byte counter by policer*/
+    a_uint32_t policer_bypass_packet_counter; /*bypass packet counter by policer*/
+    a_uint64_t policer_bypass_byte_counter; /*bypass byte counter by policer */
+} fal_policer_global_counter_t;
+
+enum
+{
+	FUNC_ADPT_ACL_POLICER_COUNTER_GET = 0,
+	FUNC_ADPT_PORT_POLICER_COUNTER_GET,
+	FUNC_ADPT_PORT_COMPENSATION_BYTE_GET,
+	FUNC_ADPT_PORT_POLICER_ENTRY_GET,
+	FUNC_ADPT_PORT_POLICER_ENTRY_SET,
+	FUNC_ADPT_ACL_POLICER_ENTRY_GET,
+	FUNC_ADPT_ACL_POLICER_ENTRY_SET,
+	FUNC_ADPT_POLICER_TIME_SLOT_GET,
+	FUNC_ADPT_PORT_COMPENSATION_BYTE_SET,
+	FUNC_ADPT_POLICER_TIME_SLOT_SET,
+	FUNC_ADPT_POLICER_GLOBAL_COUNTER_GET,
+	FUNC_ADPT_POLICER_BYPASS_EN_SET,
+	FUNC_ADPT_POLICER_BYPASS_EN_GET,
+};
+
+
+typedef enum {
+	FAL_FRAME_DROPPED = 0,
+} fal_policer_frame_type_t;
+
+#ifndef IN_POLICER_MINI
+sw_error_t
+fal_port_policer_entry_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_policer_config_t *policer, fal_policer_action_t *action);
+
+sw_error_t
+fal_port_policer_entry_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_policer_config_t *policer, fal_policer_action_t *atcion);
+
+sw_error_t
+fal_acl_policer_entry_set(a_uint32_t dev_id, a_uint32_t index,
+		fal_policer_config_t *policer, fal_policer_action_t *action);
+
+sw_error_t
+fal_acl_policer_entry_get(a_uint32_t dev_id, a_uint32_t index,
+		fal_policer_config_t *policer, fal_policer_action_t *action);
+
+sw_error_t
+fal_port_policer_counter_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_policer_counter_t *counter);
+
+sw_error_t
+fal_acl_policer_counter_get(a_uint32_t dev_id, a_uint32_t index,
+		fal_policer_counter_t *counter);
+
+sw_error_t
+fal_port_policer_compensation_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t *length);
+
+sw_error_t
+fal_policer_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot);
+
+sw_error_t
+fal_policer_global_counter_get(a_uint32_t dev_id,
+		fal_policer_global_counter_t *counter);
+
+sw_error_t
+fal_policer_bypass_en_get(a_uint32_t dev_id, fal_policer_frame_type_t frame_type,
+	a_bool_t *enable);
+#endif
+
+sw_error_t
+fal_port_policer_compensation_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t length);
+
+sw_error_t
+fal_policer_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot);
+
+sw_error_t
+fal_policer_bypass_en_set(a_uint32_t dev_id, fal_policer_frame_type_t frame_type,
+	a_bool_t enable);
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_POLICER_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_port_ctrl.h b/qca-ssdk/include/fal/fal_port_ctrl.h
new file mode 100755
index 0000000..ab7e382
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_port_ctrl.h
@@ -0,0 +1,801 @@
+/*
+ * Copyright (c) 2012, 2015-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+/*qca808x_start*/
+/**
+ * @defgroup fal_port_ctrl FAL_PORT_CONTROL
+ * @{
+ */
+#ifndef _FAL_PORTCTRL_H_
+#define _FAL_PORTCTRL_H_
+
+#ifdef __cplusplus
+extern "c" {
+#endif
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+	typedef enum {
+		FAL_HALF_DUPLEX = 0,
+		FAL_FULL_DUPLEX,
+		FAL_DUPLEX_BUTT = 0xffff
+	} fal_port_duplex_t;
+
+	typedef enum {
+		FAL_SPEED_10 = 10,
+		FAL_SPEED_100 = 100,
+		FAL_SPEED_1000 = 1000,
+		FAL_SPEED_2500 = 2500,
+		FAL_SPEED_5000 = 5000,
+		FAL_SPEED_10000 = 10000,
+		FAL_SPEED_BUTT = 0xffff,
+	} fal_port_speed_t;
+
+	typedef enum {
+		FAL_CABLE_STATUS_NORMAL = 0,
+		FAL_CABLE_STATUS_SHORT = 1,
+		FAL_CABLE_STATUS_OPENED = 2,
+		FAL_CABLE_STATUS_INVALID = 3,
+		FAL_CABLE_STATUS_CROSSOVERA = 4,
+		FAL_CABLE_STATUS_CROSSOVERB = 5,
+		FAL_CABLE_STATUS_CROSSOVERC = 6,
+		FAL_CABLE_STATUS_CROSSOVERD = 7,
+		FAL_CABLE_STATUS_LOW_MISMATCH =8,
+		FAL_CABLE_STATUS_HIGH_MISMATCH =9,
+		FAL_CABLE_STATUS_BUTT = 0xffff,
+	} fal_cable_status_t;
+
+struct port_phy_status
+{
+	a_uint32_t link_status;
+	fal_port_speed_t speed;
+	fal_port_duplex_t duplex;
+	a_bool_t tx_flowctrl;
+	a_bool_t rx_flowctrl;
+};
+
+#define FAL_ENABLE                1
+#define FAL_DISABLE               0
+#define FAL_MAX_PORT_NUMBER       8
+#define FAL_DEFAULT_LOOPBACK_RATE 14
+
+//phy autoneg adv
+#define FAL_PHY_ADV_10T_HD      0x01
+#define FAL_PHY_ADV_10T_FD      0x02
+#define FAL_PHY_ADV_100TX_HD    0x04
+#define FAL_PHY_ADV_100TX_FD    0x08
+//#define FAL_PHY_ADV_1000T_HD    0x100
+#define FAL_PHY_ADV_1000T_FD    0x200
+#define FAL_PHY_ADV_1000BX_HD    0x400
+#define FAL_PHY_ADV_1000BX_FD    0x800
+#define FAL_PHY_ADV_2500T_FD    0x1000
+#define FAL_PHY_ADV_5000T_FD    0x2000
+#define FAL_PHY_ADV_10000T_FD    0x4000
+#define FAL_PHY_ADV_10G_R_FD    0x8000
+
+#define FAL_DEFAULT_MAX_FRAME_SIZE 0x5ee
+
+#define FAL_PHY_ADV_FE_SPEED_ALL   \
+    (FAL_PHY_ADV_10T_HD | FAL_PHY_ADV_10T_FD | FAL_PHY_ADV_100TX_HD |\
+     FAL_PHY_ADV_100TX_FD)
+
+#define FAL_PHY_ADV_GE_SPEED_ALL   \
+    (FAL_PHY_ADV_10T_HD | FAL_PHY_ADV_10T_FD | FAL_PHY_ADV_100TX_HD |\
+     FAL_PHY_ADV_100TX_FD | FAL_PHY_ADV_1000T_FD)
+
+#define FAL_PHY_ADV_BX_SPEED_ALL   \
+    (FAL_PHY_ADV_1000BX_HD | FAL_PHY_ADV_1000BX_FD |FAL_PHY_ADV_10G_R_FD)
+
+#define FAL_PHY_ADV_XGE_SPEED_ALL   \
+		(FAL_PHY_ADV_2500T_FD | FAL_PHY_ADV_5000T_FD | FAL_PHY_ADV_10000T_FD)
+
+#define FAL_PHY_ADV_PAUSE       0x10
+#define FAL_PHY_ADV_ASY_PAUSE   0x20
+#define FAL_PHY_FE_ADV_ALL         \
+    (FAL_PHY_ADV_FE_SPEED_ALL | FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE)
+#define FAL_PHY_GE_ADV_ALL         \
+    (FAL_PHY_ADV_GE_SPEED_ALL | FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE)
+
+#define FAL_PHY_COMBO_ADV_ALL         \
+    (FAL_PHY_ADV_BX_SPEED_ALL | FAL_PHY_ADV_GE_SPEED_ALL | FAL_PHY_ADV_XGE_SPEED_ALL|\
+FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE)
+
+//phy capablity
+#define FAL_PHY_AUTONEG_CAPS   0x01
+#define FAL_PHY_100T2_HD_CAPS  0x02
+#define FAL_PHY_100T2_FD_CAPS  0x04
+#define FAL_PHY_10T_HD_CAPS    0x08
+#define FAL_PHY_10T_FD_CAPS    0x10
+#define FAL_PHY_100X_HD_CAPS   0x20
+#define FAL_PHY_100X_FD_CAPS   0x40
+#define FAL_PHY_100T4_CAPS     0x80
+//#define FAL_PHY_1000T_HD_CAPS  0x100
+#define FAL_PHY_1000T_FD_CAPS  0x200
+//#define FAL_PHY_1000X_HD_CAPS  0x400
+#define FAL_PHY_1000X_FD_CAPS  0x800
+
+//phy partner capablity
+#define FAL_PHY_PART_10T_HD   0x1
+#define FAL_PHY_PART_10T_FD   0x2
+#define FAL_PHY_PART_100TX_HD 0x4
+#define FAL_PHY_PART_100TX_FD 0x8
+//#define FAL_PHY_PART_1000T_HD 0x10
+#define FAL_PHY_PART_1000T_FD 0x20
+#define FAL_PHY_PART_2500T_FD 0x40
+#define FAL_PHY_PART_5000T_FD 0x80
+#define FAL_PHY_PART_10000T_FD 0x100
+
+//phy interrupt flag
+#define FAL_PHY_INTR_SPEED_CHANGE         0x1
+#define FAL_PHY_INTR_DUPLEX_CHANGE        0x2
+#define FAL_PHY_INTR_STATUS_UP_CHANGE     0x4
+#define FAL_PHY_INTR_STATUS_DOWN_CHANGE   0x8
+#define FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE   0x10
+#define FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE   0x20
+#define FAL_PHY_INTR_MEDIA_STATUS_CHANGE   0x40
+#define FAL_PHY_INTR_WOL_STATUS   0x80
+#define FAL_PHY_INTR_POE_STATUS   0x100
+
+/* phy eee */
+#define FAL_PHY_EEE_10BASE_T  0x1
+#define FAL_PHY_EEE_100BASE_T  0x2
+#define FAL_PHY_EEE_1000BASE_T  0x4
+#define FAL_PHY_EEE_2500BASE_T  0x8
+#define FAL_PHY_EEE_5000BASE_T  0x10
+#define FAL_PHY_EEE_10000BASE_T  0x20
+	typedef enum {
+		FAL_NO_HEADER_EN = 0,
+		FAL_ONLY_MANAGE_FRAME_EN,
+		FAL_ALL_TYPE_FRAME_EN
+	} fal_port_header_mode_t;
+
+	typedef struct {
+		a_uint16_t pair_a_status;
+		a_uint16_t pair_b_status;
+		a_uint16_t pair_c_status;
+		a_uint16_t pair_d_status;
+		a_uint32_t pair_a_len;
+		a_uint32_t pair_b_len;
+		a_uint32_t pair_c_len;
+		a_uint32_t pair_d_len;
+	} fal_port_cdt_t;
+
+/*below is new add for malibu phy*/
+
+/** Phy mdix mode */
+	typedef enum {
+		PHY_MDIX_AUTO = 0,
+			      /**< Auto MDI/MDIX */
+		PHY_MDIX_MDI = 1,
+			      /**< Fixed MDI */
+		PHY_MDIX_MDIX = 2
+			      /**< Fixed MDIX */
+	} fal_port_mdix_mode_t;
+
+/** Phy mdix status */
+	typedef enum {
+		PHY_MDIX_STATUS_MDI = 0,
+				    /**< Fixed MDI */
+		PHY_MDIX_STATUS_MDIX = 1
+				    /**< Fixed MDIX */
+	} fal_port_mdix_status_t;
+
+/** Phy master mode */
+	typedef enum {
+		PHY_MASTER_MASTER = 0,
+				/**< Phy manual MASTER configuration */
+		PHY_MASTER_SLAVE = 1,
+				/**< Phy manual SLAVE configuration */
+		PHY_MASTER_AUTO = 2
+				/**< Phy automatic MASTER/SLAVE configuration */
+	} fal_port_master_t;
+
+/** Phy preferred medium type */
+	typedef enum {
+		PHY_MEDIUM_COPPER = 0,
+				/**< Copper */
+		PHY_MEDIUM_FIBER = 1,
+				/**< Fiber */
+
+	} fal_port_medium_t;
+
+/** Phy pages */
+	typedef enum {
+		PHY_SGBX_PAGES = 0,
+				/**< sgbx pages */
+		PHY_COPPER_PAGES = 1
+				/**< copper pages */
+	} fal_port_reg_pages_t;
+
+/** Phy preferred Fiber mode */
+	typedef enum {
+		PHY_FIBER_100FX = 0,
+				/**< 100FX fiber mode */
+		PHY_FIBER_1000BX = 1,
+				/**< 1000BX fiber mode */
+		PHY_FIBER_10G_R = 2,
+	} fal_port_fiber_mode_t;
+
+/** Phy reset status */
+	typedef enum {
+		PHY_RESET_DONE = 0,
+				/**< Phy reset done */
+		PHY_RESET_BUSY = 1
+				/**< Phy still in reset process */
+	} fal_port_reset_status_t;
+
+/** Phy auto-negotiation status */
+	typedef enum {
+		PHY_AUTO_NEG_STATUS_BUSY = 0,
+				    /**< Phy still in auto-negotiation process */
+		PHY_AUTO_NEG_STATUS_DONE = 1
+				    /**< Phy auto-negotiation done */
+	} fal_port_auto_neg_status_t;
+
+
+/** Phy interface mode */
+	typedef enum {
+		PHY_PSGMII_BASET = 0,
+				/**< PSGMII mode */
+		PHY_PSGMII_BX1000 = 1,
+				/**< PSGMII BX1000 mode */
+		PHY_PSGMII_FX100 = 2,
+				/**< PSGMII FX100 mode */
+		PHY_PSGMII_AMDET = 3,
+				/**< PSGMII Auto mode */
+		PHY_SGMII_BASET = 4,
+				/**< SGMII mode */
+		PORT_QSGMII,
+				/**<QSGMII mode*/
+		PORT_SGMII_PLUS,
+				/**<PORT_SGMII_PLUS mode*/
+		PORT_USXGMII,
+				/**<PORT_USXGMII mode*/
+		PORT_10GBASE_R,
+				/**<PORT_10GBASE_R mode*/
+		PORT_RGMII_BASET,
+				/**< RGMII mode */
+		PORT_RGMII_BX1000,
+				/**< RGMII BX1000 mode */
+		PORT_RGMII_FX100,
+				/**< RGMII FX100 mode */
+		PORT_RGMII_AMDET,
+				/**< RGMII Auto mode */
+		PHY_PSGMII_FIBER,
+				/** <PHY_PSGMII_FIBER mode */
+		PORT_SGMII_FIBER,
+				/** <PORT SGMII_FIBER mode*/
+		PORT_INTERFACE_MODE_MAX = 0xFF
+	} fal_port_interface_mode_t;
+
+/** Phy counter information */
+typedef struct {
+	a_uint32_t RxGoodFrame;
+	a_uint32_t RxBadCRC;
+	a_uint32_t TxGoodFrame;
+	a_uint32_t TxBadCRC;
+	a_uint32_t SysRxGoodFrame;
+	a_uint32_t SysRxBadCRC;
+	a_uint32_t SysTxGoodFrame;
+	a_uint32_t SysTxBadCRC;
+} fal_port_counter_info_t;
+
+/*above is new add for malibu phy*/
+/*qca808x_end*/
+typedef struct {
+	a_bool_t enable;
+	a_uint32_t capability;
+	a_uint32_t lpi_sleep_timer; /* unit is us*/
+	a_uint32_t advertisement;
+	a_uint32_t lpi_tx_enable;
+	a_uint32_t eee_status;
+	a_uint32_t lpi_wakeup_timer; /* unit is us*/
+	a_uint32_t link_partner_advertisement;
+} fal_port_eee_cfg_t;
+
+enum
+{
+	/*port contorl*/
+	FUNC_ADPT_PORT_LOCAL_LOOPBACK_GET = 0,
+	FUNC_ADPT_PORT_AUTONEG_RESTART,
+	FUNC_ADPT_PORT_DUPLEX_SET,
+	FUNC_ADPT_PORT_RXMAC_STATUS_GET,
+	FUNC_ADPT_PORT_CDT,
+	FUNC_ADPT_PORT_TXMAC_STATUS_SET,
+	FUNC_ADPT_PORT_COMBO_FIBER_MODE_SET,
+	FUNC_ADPT_PORT_COMBO_MEDIUM_STATUS_GET,
+	FUNC_ADPT_PORT_MAGIC_FRAME_MAC_SET,
+	FUNC_ADPT_PORT_POWERSAVE_SET,
+	FUNC_ADPT_PORT_HIBERNATE_SET,
+	FUNC_ADPT_PORT_8023AZ_GET,
+	FUNC_ADPT_PORT_RXFC_STATUS_GET,
+	FUNC_ADPT_PORT_TXFC_STATUS_GET,
+	FUNC_ADPT_PORT_REMOTE_LOOPBACK_SET,
+	FUNC_ADPT_PORT_FLOWCTRL_SET,
+	FUNC_ADPT_PORT_MRU_SET,
+	FUNC_ADPT_PORT_AUTONEG_STATUS_GET,
+	FUNC_ADPT_PORT_TXMAC_STATUS_GET,
+	FUNC_ADPT_PORT_MDIX_GET,
+	FUNC_ADPT_PORTS_LINK_STATUS_GET,
+	FUNC_ADPT_PORT_MAC_LOOPBACK_SET,
+	FUNC_ADPT_PORT_PHY_ID_GET,
+	FUNC_ADPT_PORT_MRU_GET,
+	FUNC_ADPT_PORT_POWER_ON,
+	FUNC_ADPT_PORT_SPEED_SET,
+	FUNC_ADPT_PORT_INTERFACE_MODE_GET,
+	FUNC_ADPT_PORT_DUPLEX_GET,
+	FUNC_ADPT_PORT_AUTONEG_ADV_GET,
+	FUNC_ADPT_PORT_MDIX_STATUS_GET,
+	FUNC_ADPT_PORT_MTU_SET,
+	FUNC_ADPT_PORT_LINK_STATUS_GET,
+
+	FUNC_ADPT_PORT_8023AZ_SET,
+	FUNC_ADPT_PORT_POWERSAVE_GET,
+	FUNC_ADPT_PORT_COMBO_PREFER_MEDIUM_GET,
+	FUNC_ADPT_PORT_COMBO_PREFER_MEDIUM_SET,
+	FUNC_ADPT_PORT_POWER_OFF,
+	FUNC_ADPT_PORT_TXFC_STATUS_SET,
+	FUNC_ADPT_PORT_COUNTER_SET,
+	FUNC_ADPT_PORT_COMBO_FIBER_MODE_GET,
+	FUNC_ADPT_PORT_LOCAL_LOOPBACK_SET,
+	FUNC_ADPT_PORT_WOL_STATUS_SET,
+	FUNC_ADPT_PORT_MAGIC_FRAME_MAC_GET,
+	FUNC_ADPT_PORT_FLOWCTRL_GET,
+	FUNC_ADPT_PORT_RXMAC_STATUS_SET,
+	FUNC_ADPT_PORT_COUNTER_GET,
+	FUNC_ADPT_PORT_INTERFACE_MODE_SET,
+	FUNC_ADPT_PORT_MAC_LOOPBACK_GET,
+	FUNC_ADPT_PORT_HIBERNATE_GET,
+	FUNC_ADPT_PORT_AUTONEG_ADV_SET,
+	FUNC_ADPT_PORT_REMOTE_LOOPBACK_GET,
+	FUNC_ADPT_PORT_COUNTER_SHOW,
+	FUNC_ADPT_PORT_AUTONEG_ENABLE,
+	FUNC_ADPT_PORT_MTU_GET,
+	FUNC_ADPT_PORT_INTERFACE_MODE_STATUS_GET,
+	FUNC_ADPT_PORT_RESET,
+	FUNC_ADPT_PORT_RXFC_STATUS_SET,
+	FUNC_ADPT_PORT_SPEED_GET,
+	FUNC_ADPT_PORT_MDIX_SET,
+	FUNC_ADPT_PORT_WOL_STATUS_GET,
+	FUNC_ADPT_PORT_MAX_FRAME_SIZE_SET,
+	FUNC_ADPT_PORT_MAX_FRAME_SIZE_GET,
+	FUNC_ADPT_PORT_SOURCE_FILTER_GET,
+	FUNC_ADPT_PORT_SOURCE_FILTER_SET,
+
+	FUNC_ADPT_PORT_INTERFACE_MODE_APPLY,
+	FUNC_ADPT_PORT_INTERFACE_3AZ_STATUS_SET,
+	FUNC_ADPT_PORT_INTERFACE_3AZ_STATUS_GET,
+	FUNC_ADPT_PORT_PROMISC_MODE_SET,
+	FUNC_ADPT_PORT_PROMISC_MODE_GET,
+	FUNC_ADPT_PORT_FLOWCTRL_FORCEMODE_SET,
+	FUNC_ADPT_PORT_FLOWCTRL_FORCEMODE_GET,
+};
+
+typedef struct {
+	a_uint32_t 		mtu_size;
+	fal_fwd_cmd_t 	action;
+} fal_mtu_ctrl_t;
+
+typedef struct {
+	a_uint32_t 		mru_size;
+	fal_fwd_cmd_t 	action;
+} fal_mru_ctrl_t;
+
+typedef enum {
+	FAL_SRC_FILTER_MODE_VP = 0,
+	FAL_SRC_FILTER_MODE_PHYSICAL = 1,
+} fal_src_filter_mode_t;
+
+typedef struct {
+	a_bool_t	src_filter_enable;
+	fal_src_filter_mode_t	src_filter_mode;
+} fal_src_filter_config_t;
+
+typedef struct {
+	a_bool_t enable;
+	a_bool_t crc_stripped;
+	a_uint32_t loopback_rate; /*Mpps*/
+}fal_loopback_config_t;
+
+sw_error_t
+fal_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t max_frame);
+
+sw_error_t
+fal_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t *max_frame);
+
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+fal_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl);
+
+sw_error_t
+fal_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl);
+
+sw_error_t
+fal_port_mru_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl);
+
+sw_error_t
+fal_port_mru_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl);
+#endif
+
+/*qca808x_start*/
+sw_error_t
+fal_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_duplex_t duplex);
+
+sw_error_t
+fal_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_duplex_t * pduplex);
+
+sw_error_t
+fal_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+			       fal_port_speed_t speed);
+
+sw_error_t
+fal_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+			       fal_port_speed_t * pspeed);
+
+sw_error_t
+fal_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+					a_bool_t * status);
+
+sw_error_t
+fal_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
+
+sw_error_t
+fal_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
+
+sw_error_t
+fal_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+				     a_uint32_t autoadv);
+sw_error_t
+fal_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+				     a_uint32_t * autoadv);
+/*qca808x_end*/
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+fal_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+				    a_bool_t enable);
+
+sw_error_t
+fal_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+				    a_bool_t * enable);
+#endif
+sw_error_t
+fal_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t enable);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+fal_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t * enable);
+
+sw_error_t
+fal_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t enable);
+
+sw_error_t
+fal_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t * enable);
+#endif
+sw_error_t
+fal_port_flowctrl_forcemode_set(a_uint32_t dev_id,
+					    fal_port_t port_id,
+					    a_bool_t enable);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+fal_port_flowctrl_forcemode_get(a_uint32_t dev_id,
+					    fal_port_t port_id,
+					    a_bool_t * enable);
+#endif
+sw_error_t
+fal_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+				    fal_port_header_mode_t mode);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+fal_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+				    fal_port_header_mode_t * mode);
+#endif
+sw_error_t
+fal_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+				    fal_port_header_mode_t mode);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+fal_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+				    fal_port_header_mode_t * mode);
+#endif
+sw_error_t
+fal_header_type_set(a_uint32_t dev_id, a_bool_t enable,
+				a_uint32_t type);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+fal_header_type_get(a_uint32_t dev_id, a_bool_t * enable,
+				a_uint32_t * type);
+#endif
+sw_error_t
+fal_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id,
+				      a_bool_t enable);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+fal_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id,
+				      a_bool_t * enable);
+#endif
+sw_error_t
+fal_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id,
+				      a_bool_t enable);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+fal_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id,
+				      a_bool_t * enable);
+#endif
+sw_error_t
+fal_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t enable);
+
+sw_error_t
+fal_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t * enable);
+
+sw_error_t
+fal_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t enable);
+
+sw_error_t
+fal_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t * enable);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+fal_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id,
+				   a_bool_t enable);
+
+sw_error_t
+fal_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id,
+				   a_bool_t * enable);
+#endif
+sw_error_t
+fal_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+					a_bool_t enable);
+
+sw_error_t
+fal_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+					a_bool_t * enable);
+/*qca808x_start*/
+sw_error_t
+fal_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t * status);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+fal_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status);
+/*qca808x_end*/
+sw_error_t
+fal_port_congestion_drop_set(a_uint32_t dev_id, fal_port_t port_id,
+					 a_uint32_t queue_id, a_bool_t enable);
+
+sw_error_t
+fal_port_congestion_drop_get(a_uint32_t dev_id, fal_port_t port_id,
+					 a_uint32_t queue_id,
+					 a_bool_t * enable);
+sw_error_t
+fal_ring_flow_ctrl_thres_set(a_uint32_t dev_id, a_uint32_t ring_id,
+					 a_uint8_t on_thres,
+					 a_uint8_t off_thres);
+
+sw_error_t
+fal_ring_flow_ctrl_thres_get(a_uint32_t dev_id, a_uint32_t ring_id,
+					 a_uint8_t * on_thres,
+					 a_uint8_t * off_thres);
+/*qca808x_start*/
+sw_error_t
+fal_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable);
+
+
+sw_error_t
+fal_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable);
+
+
+sw_error_t
+fal_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable);
+
+
+sw_error_t
+fal_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable);
+
+sw_error_t
+fal_port_cdt(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t mdi_pair, fal_cable_status_t * cable_status,
+		a_uint32_t * cable_len);
+
+
+sw_error_t
+fal_port_8023az_set(a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t enable);
+
+sw_error_t
+fal_port_8023az_get(a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t * enable);
+
+sw_error_t
+fal_port_mdix_set(a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_mdix_mode_t mode);
+
+sw_error_t
+fal_port_mdix_get(a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_mdix_mode_t * mode);
+
+sw_error_t
+fal_port_mdix_status_get(a_uint32_t dev_id, fal_port_t port_id,
+				     fal_port_mdix_status_t * mode);
+/*qca808x_end*/
+sw_error_t
+fal_port_combo_prefer_medium_set(a_uint32_t dev_id,
+					     a_uint32_t port_id,
+					     fal_port_medium_t medium);
+
+sw_error_t
+fal_port_combo_prefer_medium_get(a_uint32_t dev_id,
+						     a_uint32_t port_id,
+						     fal_port_medium_t *
+						     medium);
+
+sw_error_t
+fal_port_combo_medium_status_get(a_uint32_t dev_id,
+						     a_uint32_t port_id,
+						     fal_port_medium_t *
+						     medium);
+sw_error_t
+fal_port_combo_fiber_mode_set(a_uint32_t dev_id,
+						  a_uint32_t port_id,
+						  fal_port_fiber_mode_t mode);
+
+sw_error_t
+fal_port_combo_fiber_mode_get(a_uint32_t dev_id,
+						  a_uint32_t port_id,
+						  fal_port_fiber_mode_t * mode);
+/*qca808x_start*/
+sw_error_t
+fal_port_local_loopback_set(a_uint32_t dev_id,
+						fal_port_t port_id,
+						a_bool_t enable);
+
+sw_error_t
+fal_port_local_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
+					a_bool_t * enable);
+
+sw_error_t
+fal_port_remote_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
+					 a_bool_t enable);
+
+sw_error_t
+fal_port_remote_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
+					 a_bool_t * enable);
+sw_error_t
+fal_port_reset(a_uint32_t dev_id, fal_port_t port_id);
+#endif
+sw_error_t
+fal_port_power_off(a_uint32_t dev_id, fal_port_t port_id);
+
+sw_error_t
+fal_port_power_on(a_uint32_t dev_id, fal_port_t port_id);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+fal_port_magic_frame_mac_set(a_uint32_t dev_id, fal_port_t port_id,
+				   fal_mac_addr_t * mac);
+
+sw_error_t
+fal_port_magic_frame_mac_get(a_uint32_t dev_id, fal_port_t port_id,
+				   fal_mac_addr_t * mac);
+
+sw_error_t
+fal_port_phy_id_get(a_uint32_t dev_id, fal_port_t port_id,
+		      a_uint16_t * org_id, a_uint16_t * rev_id);
+
+sw_error_t
+fal_port_wol_status_set(a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t enable);
+
+ /*all indirect */
+sw_error_t
+fal_port_wol_status_get(a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * enable);
+ /*qca808x_end*/
+sw_error_t
+fal_port_interface_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t mode);
+
+sw_error_t
+fal_port_interface_mode_apply(a_uint32_t dev_id);
+
+sw_error_t
+fal_port_interface_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t * mode);
+/*qca808x_start*/
+sw_error_t
+fal_port_interface_mode_status_get(a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t * mode);
+
+sw_error_t
+fal_debug_phycounter_set(a_uint32_t dev_id, fal_port_t port_id,
+		   a_bool_t enable);
+
+sw_error_t
+fal_debug_phycounter_get(a_uint32_t dev_id, fal_port_t port_id,
+		   a_bool_t * enable);
+
+sw_error_t
+fal_debug_phycounter_show(a_uint32_t dev_id, fal_port_t port_id,
+				 fal_port_counter_info_t * port_counter_info);
+#endif
+/*qca808x_end*/
+
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+fal_port_source_filter_status_get(a_uint32_t dev_id,
+				fal_port_t port_id, a_bool_t * enable);
+
+sw_error_t
+fal_port_source_filter_enable(a_uint32_t dev_id,
+				fal_port_t port_id, a_bool_t enable);
+
+sw_error_t
+fal_port_source_filter_config_get(a_uint32_t dev_id,
+	fal_port_t port_id, fal_src_filter_config_t * src_filter_config);
+
+sw_error_t
+fal_port_source_filter_config_set(a_uint32_t dev_id,
+	fal_port_t port_id, fal_src_filter_config_t *src_filter_config);
+
+sw_error_t
+fal_port_interface_3az_status_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t enable);
+
+sw_error_t
+fal_port_interface_3az_status_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t * enable);
+
+sw_error_t
+fal_port_promisc_mode_get(a_uint32_t dev_id,fal_port_t port_id,a_bool_t *enable);
+#endif
+
+sw_error_t
+fal_port_promisc_mode_set(a_uint32_t dev_id,fal_port_t port_id,a_bool_t enable);
+sw_error_t
+fal_port_interface_eee_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
+	fal_port_eee_cfg_t *port_eee_cfg);
+sw_error_t
+fal_port_interface_eee_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
+	fal_port_eee_cfg_t *port_eee_cfg);
+sw_error_t
+fal_switch_port_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
+	fal_loopback_config_t *loopback_cfg);
+sw_error_t
+fal_switch_port_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
+	fal_loopback_config_t *loopback_cfg);
+
+/*qca808x_start*/
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* _FAL_PORTCTRL_H_ */
+/**
+ * @}
+ */
+/*qca808x_end*/
diff --git a/qca-ssdk/include/fal/fal_portvlan.h b/qca-ssdk/include/fal/fal_portvlan.h
new file mode 100755
index 0000000..2eb8c64
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_portvlan.h
@@ -0,0 +1,738 @@
+/*
+ * Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+ * @defgroup fal_port_vlan FAL_PORT_VLAN
+ * @{
+ */
+#ifndef _FAL_PORT_VLAN_H_
+#define _FAL_PORT_VLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+#if defined(SW_API_LOCK) && (!defined(HSL_STANDALONG))
+#define FAL_PORTVLAN_API_LOCK
+#define FAL_PORTVLAN_API_UNLOCK
+#else
+#define FAL_PORTVLAN_API_LOCK
+#define FAL_PORTVLAN_API_UNLOCK
+#endif
+
+#define FAL_DEF_VLAN_STPID 0x88a8
+#define FAL_DEF_VLAN_CTPID 0x8100
+
+    /**
+    @brief This enum defines 802.1q mode type.
+    */
+    typedef enum {
+        FAL_1Q_DISABLE = 0, /**<  802.1q mode disbale, port based vlan */
+        FAL_1Q_SECURE,      /**<   secure mode, packets which vid isn't in vlan table or source port isn't in vlan port member will be discarded.*/
+        FAL_1Q_CHECK,       /**<   check mode, packets which vid isn't in vlan table will be discarded, packets which source port isn't in vlan port member will forward base on vlan port member*/
+        FAL_1Q_FALLBACK,    /**<   fallback mode, packets which vid isn't in vlan table will forwarded base on port vlan, packet's which source port isn't in vlan port member will forward base on vlan port member.*/
+        FAL_1Q_MODE_BUTT
+    }
+    fal_pt_1qmode_t;
+
+    /**
+    @brief This enum defines receive packets tagged mode.
+    */
+    typedef enum
+    {
+        FAL_INVLAN_ADMIT_ALL = 0,  /**<  receive all packets include tagged and untagged */
+        FAL_INVLAN_ADMIT_TAGGED,   /**<  only receive tagged packets*/
+        FAL_INVLAN_ADMIT_UNTAGGED, /**<  only receive untagged packets include priority tagged */
+        FAL_INVLAN_MODE_BUTT
+    } fal_pt_invlan_mode_t;
+
+    /**
+    @brief This enum defines vlan propagation mode.
+    */
+    typedef enum
+    {
+        FAL_VLAN_PROPAGATION_DISABLE = 0, /**<  vlan propagation disable */
+        FAL_VLAN_PROPAGATION_CLONE,       /**<  vlan paopagation mode is clone */
+        FAL_VLAN_PROPAGATION_REPLACE,     /**<  vlan paopagation mode is repalce */
+        FAL_VLAN_PROPAGATION_MODE_BUTT
+    } fal_vlan_propagation_mode_t;
+
+    typedef enum
+    {
+        FAL_FRAMETYPE_ETHERNET = 0,
+        FAL_FRAMETYPE_RFC_1024 = 1,
+        FAL_FRAMETYPE_LLC_OTHER = 2,
+        FAL_FRAMETYPE_ETHORRFC1024 = 3,
+    } fal_frametype_t;
+
+    typedef enum
+    {
+        FAL_VID_XLT_CMD_UNCHANGED = 0,
+        FAL_VID_XLT_CMD_ADDORREPLACE = 1,
+        FAL_VID_XLT_CMD_DELETE = 2,
+    } fal_vid_xlt_cmd_t;
+
+    typedef enum
+    {
+        FAL_PORT_VLAN_ALL = 0,
+        FAL_PORT_VLAN_INGRESS = 1,
+        FAL_PORT_VLAN_EGRESS = 2,
+    } fal_port_vlan_direction_t;
+
+
+    /**
+      @details  Fields description:
+
+     o_vid - original vlan id
+     s_vid - service vid id
+     c_vid - custom vid id
+     bi_dir - entry search direction
+     forward_dir - entry search direction only be forward
+     reverse_dir - entry search direction only be reverse
+     o_vid_is_cvid - o_vid in entry means c_vid not s_vid
+     s_vid_enable  - s_vid in entry is valid
+     c_vid_enable  - c_vid in entry is valid
+     one_2_one_vlan- the entry used for 1:1 vlan
+    @brief This structure defines the vlan translation entry.
+
+    */
+
+    typedef struct
+    {
+        a_uint32_t o_vid;        /* original vid */
+        a_uint32_t s_vid;        /* service vid */
+        a_uint32_t c_vid;        /* customer vid */
+        a_bool_t   bi_dir;       /* lookup can be forward and reverse */
+        a_bool_t   forward_dir;  /* lookup direction only can be from o_vid to s_vid and/or c_vid*/
+        a_bool_t   reverse_dir;  /* lookup direction only can be from s_vid and/or c_vid to o_vid*/
+        a_bool_t   o_vid_is_cvid;
+        a_bool_t   s_vid_enable; /* enable svid value or not */
+        a_bool_t   c_vid_enable; /* enable cvid value or not */
+        a_bool_t   one_2_one_vlan;
+
+	/*direction check*/
+	a_uint32_t trans_direction; /* 0 is for ingress, 1 is for egress */
+
+        /*vsi check*/
+        a_bool_t   vsi_valid; /* check if rule will include vsi value valid */
+        a_bool_t   vsi_enable; /* check if rule will include vsi value */
+        a_uint32_t   vsi; /* vsi value */
+
+        /*protocol and ethernet type*/
+        a_bool_t   protocol_enable; /* enable protocol value or not */
+        a_uint16_t   protocol; /* protocol value */
+        a_bool_t   frmtype_enable; /* enable frame type value or not */
+        fal_frametype_t   frmtype; /* frame type value */
+
+        /*tagged mode, bit 0 for untagged, bit 1 for priority tagged and bit 2 for tagged*/
+        a_uint8_t   s_tagged; /* stag type is untagged/pri tagged/tagged */
+        a_uint8_t   c_tagged; /* ctag type is untagged/pri tagged/tagged */
+
+        /*cpcp and cdei*/
+        a_bool_t   c_pcp_enable; /* check if rule will include customer pcp value */
+        a_uint8_t   c_pcp; /* customer pcp value */
+        a_bool_t   c_dei_enable; /* check if rule will include customer dei value */
+        a_uint8_t   c_dei; /* customer dei value */
+        /*spcp and sdei*/
+        a_bool_t   s_pcp_enable; /* check if rule will include service pcp value */
+        a_uint8_t   s_pcp; /* service pcp value */
+        a_bool_t   s_dei_enable; /* check if rule will include service dei value */
+        a_uint8_t   s_dei; /* service dei value */
+
+        /*translation action*/
+        /*counter action*/
+        a_bool_t   counter_enable; /* check if action will enable counter_id */
+        a_uint8_t   counter_id;  /* counter id */
+        /*vsi action*/
+        a_bool_t   vsi_action_enable; /* check if action will enable vsi action */
+        a_uint8_t   vsi_action; /* vsi action */
+        /*svid action*/
+        fal_vid_xlt_cmd_t   svid_xlt_cmd; /* check if action will do svid xlt */
+        a_uint16_t   svid_xlt; /* svid xlt operation */
+        /*cvid action*/
+        fal_vid_xlt_cmd_t   cvid_xlt_cmd; /* check if action will do cvid xlt */
+        a_uint16_t   cvid_xlt; /* cvid xlt operation */
+        /*swap svid and cvid action*/
+        a_bool_t   swap_svid_cvid; /* check if action will do svid and cvid swap operation */
+        /*spcp action*/
+        a_bool_t   spcp_xlt_enable; /* check if action will enable spcp xlt */
+        a_uint8_t   spcp_xlt; /* spcp xlt operation */
+        /*cpcp action*/
+        a_bool_t   cpcp_xlt_enable; /* check if action will enable cpcp xlt */
+        a_uint8_t   cpcp_xlt; /* cpcp xlt operation */
+        /*swap spcp and cpcp action*/
+        a_bool_t   swap_spcp_cpcp; /* check if action will do spcp and cpcp swap operation */
+        /*sdei action*/
+        a_bool_t   sdei_xlt_enable; /* check if action will enable sdei xlt */
+        a_uint8_t   sdei_xlt; /* sdei xlt operation */
+        /*cdei action*/
+        a_bool_t   cdei_xlt_enable; /* check if action will enable cdei xlt */
+        a_uint8_t   cdei_xlt; /* cdei xlt operation */
+        /*swap sdei and cdei action*/
+        a_bool_t   swap_sdei_cdei; /* check if action will do sdei and cdei swap operation */
+
+	 /*port bitmap for this entry*/
+	 a_uint32_t port_bitmap; /* rule must be include port_bitmap */
+    } fal_vlan_trans_entry_t;
+
+    /**
+    @brief This enum defines qinq working mode.
+    */
+    typedef enum
+    {
+        FAL_QINQ_CTAG_MODE = 0,
+        FAL_QINQ_STAG_MODE,
+        FAL_QINQ_MODE_BUTT
+    } fal_qinq_mode_t;
+
+    /**
+    @brief This enum defines port role in qinq mode.
+    */
+    typedef enum
+    {
+        FAL_QINQ_EDGE_PORT = 0,
+        FAL_QINQ_CORE_PORT,
+        FAL_QINQ_PORT_ROLE_BUTT
+    } fal_qinq_port_role_t;
+
+enum {
+	FUNC_PORT_INVLAN_MODE_SET = 0,
+	FUNC_PORT_INVLAN_MODE_GET,
+	FUNC_PORT_VLAN_TRANS_ADD,
+	FUNC_PORT_VLAN_TRANS_DEL,
+	FUNC_PORT_VLAN_TRANS_GET,
+	FUNC_QINQ_MODE_SET,
+	FUNC_QINQ_MODE_GET,
+	FUNC_PORT_QINQ_ROLE_SET,
+	FUNC_PORT_QINQ_ROLE_GET,
+	FUNC_PORT_VLAN_TRANS_ITERATE,
+	FUNC_GLOBAL_QINQ_MODE_SET,
+	FUNC_GLOBAL_QINQ_MODE_GET,
+	FUNC_PORT_QINQ_MODE_SET,
+	FUNC_PORT_QINQ_MODE_GET,
+	FUNC_INGRESS_TPID_SET,
+	FUNC_INGRESS_TPID_GET,
+	FUNC_EGRESS_TPID_SET,
+	FUNC_EGRESS_TPID_GET,
+	FUNC_PORT_INGRESS_VLAN_FILTER_SET,
+	FUNC_PORT_INGRESS_VLAN_FILTER_GET,
+	FUNC_PORT_DEFAULT_VLANTAG_SET,
+	FUNC_PORT_DEFAULT_VLANTAG_GET,
+	FUNC_PORT_TAG_PROPAGATION_SET,
+	FUNC_PORT_TAG_PROPAGATION_GET,
+	FUNC_PORT_VLANTAG_EGMODE_SET,
+	FUNC_PORT_VLANTAG_EGMODE_GET,
+	FUNC_PORT_VLAN_XLT_MISS_CMD_SET,
+	FUNC_PORT_VLAN_XLT_MISS_CMD_GET,
+	FUNC_PORT_VSI_EGMODE_SET,
+	FUNC_PORT_VSI_EGMODE_GET,
+	FUNC_PORT_VLANTAG_VSI_EGMODE_ENABLE_SET,
+	FUNC_PORT_VLANTAG_VSI_EGMODE_ENABLE_GET,
+	FUNC_PORT_VLAN_TRANS_ADV_ADD,
+	FUNC_PORT_VLAN_TRANS_ADV_DEL,
+	FUNC_PORT_VLAN_TRANS_ADV_GETFIRST,
+	FUNC_PORT_VLAN_TRANS_ADV_GETNEXT,
+	FUNC_PORT_VLAN_COUNTER_GET,
+	FUNC_PORT_VLAN_COUNTER_CLEANUP,
+	FUNC_PORT_VLAN_MEMBER_ADD,
+	FUNC_PORT_VLAN_MEMBER_DEL,
+	FUNC_PORT_VLAN_MEMBER_UPDATE,
+	FUNC_PORT_VLAN_MEMBER_GET,
+};
+
+    sw_error_t
+    fal_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_pt_1qmode_t port_1qmode);
+
+
+#ifndef IN_PORTVLAN_MINI
+    sw_error_t
+    fal_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_pt_1qmode_t * pport_1qmode);
+
+#endif
+
+    sw_error_t
+    fal_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pt_1q_egmode_t port_egvlanmode);
+
+
+#ifndef IN_PORTVLAN_MINI
+    sw_error_t
+    fal_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pt_1q_egmode_t * pport_egvlanmode);
+
+#endif
+
+    sw_error_t
+    fal_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_port_t mem_port_id);
+
+
+
+    sw_error_t
+    fal_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_port_t mem_port_id);
+
+
+
+    sw_error_t
+    fal_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_pbmp_t mem_port_map);
+
+
+#ifndef IN_PORTVLAN_MINI
+    sw_error_t
+    fal_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pbmp_t * mem_port_map);
+#endif
+
+
+    sw_error_t
+    fal_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t vid);
+
+
+#ifndef IN_PORTVLAN_MINI
+    sw_error_t
+    fal_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * vid);
+
+#endif
+
+    sw_error_t
+    fal_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable);
+
+
+#ifndef IN_PORTVLAN_MINI
+    sw_error_t
+    fal_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable);
+#endif
+
+
+    sw_error_t
+    fal_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable);
+
+
+#ifndef IN_PORTVLAN_MINI
+    sw_error_t
+    fal_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable);
+
+#endif
+
+    sw_error_t
+    fal_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable);
+
+
+#ifndef IN_PORTVLAN_MINI
+    sw_error_t
+    fal_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable);
+#endif
+
+
+    sw_error_t
+    fal_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid);
+
+
+#ifndef IN_PORTVLAN_MINI
+    sw_error_t
+    fal_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid);
+#endif
+
+    sw_error_t
+    fal_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pt_invlan_mode_t mode);
+
+#ifndef IN_PORTVLAN_MINI
+    sw_error_t
+    fal_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pt_invlan_mode_t * mode);
+#endif
+ sw_error_t
+    fal_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+                     a_bool_t enable);
+#ifndef IN_PORTVLAN_MINI
+   
+
+
+    sw_error_t
+    fal_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+                     a_bool_t * enable);
+
+
+    sw_error_t
+    fal_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable);
+
+
+    sw_error_t
+    fal_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable);
+#endif
+
+    sw_error_t
+    fal_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t vid);
+
+#ifndef IN_PORTVLAN_MINI
+    sw_error_t
+    fal_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * vid);
+#endif
+
+    sw_error_t
+    fal_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t vid);
+
+#ifndef IN_PORTVLAN_MINI
+    sw_error_t
+    fal_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * vid);
+#endif
+	sw_error_t
+    fal_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_vlan_propagation_mode_t mode);
+
+    sw_error_t
+    fal_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role);
+
+
+    sw_error_t
+    fal_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode);
+
+    sw_error_t
+    fal_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+#ifndef IN_PORTVLAN_MINI
+
+
+    sw_error_t
+    fal_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_vlan_propagation_mode_t * mode);
+
+
+    sw_error_t
+    fal_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+    sw_error_t
+    fal_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+    sw_error_t
+    fal_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode);
+
+
+    sw_error_t
+    fal_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role);
+
+
+    sw_error_t
+    fal_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * iterator, fal_vlan_trans_entry_t * entry);
+
+
+    sw_error_t
+    fal_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable);
+
+
+    sw_error_t
+    fal_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable);
+
+    sw_error_t
+    fal_netisolate_set(a_uint32_t dev_id, a_uint32_t enable);
+
+    sw_error_t
+    fal_netisolate_get(a_uint32_t dev_id, a_uint32_t * enable);
+
+    sw_error_t
+    fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_uint32_t enable);
+
+    sw_error_t
+    fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_uint32_t * enable);
+
+    sw_error_t
+    fal_port_vrf_id_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t vrf_id);
+
+    sw_error_t
+    fal_port_vrf_id_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * vrf_id);
+#endif
+
+
+#define FAL_FLG_TST(flag, field) \
+    (((flag) & (field)) ? 1 : 0)
+
+#define FAL_GLOBAL_QINQ_MODE_INGRESS_EN (0x1UL << 0)
+#define FAL_GLOBAL_QINQ_MODE_EGRESS_EN (0x1UL << 1)
+#define FAL_GLOBAL_QINQ_MODE_EGRESS_UNTOUCHED_FOR_CPU_CODE (0x1UL << 2)
+	typedef struct {
+	    a_uint32_t mask;/*bit 0 for ingress and bit 1 for egress*/
+	    fal_qinq_mode_t ingress_mode; /* ingress direction mode */
+	    fal_qinq_mode_t egress_mode; /* egress direction mode */
+	    a_bool_t untouched_for_cpucode; /*egress untouched with cpu_code!=0 to cpu port 0 */
+	} fal_global_qinq_mode_t;
+
+#define FAL_PORT_QINQ_ROLE_INGRESS_EN (0x1UL << 0)
+#define FAL_PORT_QINQ_ROLE_EGRESS_EN (0x1UL << 1)
+	typedef struct {
+	    a_uint32_t mask;/*bit 0 for ingress and bit 1 for egress*/
+	    fal_qinq_port_role_t ingress_port_role; /* port inress direction role */
+	    fal_qinq_port_role_t egress_port_role; /* port egress direction role */
+	} fal_port_qinq_role_t;
+
+#define FAL_TPID_CTAG_EN (0x1UL << 0)
+#define FAL_TPID_STAG_EN (0x1UL << 1)
+    typedef struct
+	{
+		a_uint32_t mask; /*bit 0 for ctpid and bit 1 for stpid*/
+		a_uint16_t ctpid; /* customer tpid value */
+		a_uint16_t stpid; /* service tpid value */
+	} fal_tpid_t;
+
+	typedef struct {
+		a_bool_t membership_filter; /* check if ingress will filter port in vlan filter */
+		a_bool_t tagged_filter; /* check if ingress will filter tagged packet */
+		a_bool_t untagged_filter; /* check if ingress will filter untagged packet */
+		a_bool_t priority_filter; /* check if ingress will filter priority packet */
+	} fal_ingress_vlan_filter_t;
+
+#define FAL_PORT_VLAN_TAG_CVID_EN (0x1UL << 0)
+#define FAL_PORT_VLAN_TAG_SVID_EN (0x1UL << 1)
+#define FAL_PORT_VLAN_TAG_CPCP_EN (0x1UL << 2)
+#define FAL_PORT_VLAN_TAG_SPCP_EN (0x1UL << 3)
+#define FAL_PORT_VLAN_TAG_CDEI_EN (0x1UL << 4)
+#define FAL_PORT_VLAN_TAG_SDEI_EN (0x1UL << 5)
+    typedef struct
+	{
+		a_uint32_t mask;	/*bit 0 for ctag vid;
+					 *bit 1 for stag vid;
+					 *bit 2 for ctag priority;
+					 *bit 3 for stag priority;
+					 *bit 4 for ctag dei;
+					 *bit 5 for stag dei*/
+		a_uint16_t cvid; /* customer vid value */
+		a_uint16_t svid; /* service vid value */
+		a_uint16_t cpri; /* customer pri value */
+		a_uint16_t spri; /* service pri value */
+		a_uint16_t cdei; /* customer dei value */
+		a_uint16_t sdei; /* service dei value */
+	} fal_port_vlan_tag_t;
+
+	typedef struct {
+		a_bool_t default_cvid_en; /* enable default cvid or not */
+		a_bool_t default_svid_en; /* enable default svid or not */
+	} fal_port_default_vid_enable_t;
+
+#define FAL_PORT_PROPAGATION_VID_EN (0x1UL << 0)
+#define FAL_PORT_PROPAGATION_PCP_EN (0x1UL << 1)
+#define FAL_PORT_PROPAGATION_DEI_EN (0x1UL << 2)
+    typedef struct
+	{
+    	a_uint32_t mask; /*bit 0 for vid;
+							*bit 1 for priority;
+							*bit 2 for dei*/
+		fal_vlan_propagation_mode_t vid_propagation; /* enable vid propagation or not */
+		fal_vlan_propagation_mode_t pri_propagation; /* enable pri propagation or not */
+		fal_vlan_propagation_mode_t dei_propagation; /* enable dei propagation or not */
+	} fal_vlantag_propagation_t;
+
+#define FAL_EGRESSMODE_CTAG_EN (0x1UL << 0)
+#define FAL_EGRESSMODE_STAG_EN (0x1UL << 1)
+	typedef struct
+	{
+    	a_uint32_t mask; /*bit 0 for ctag and bit 1 for stag*/
+		fal_pt_1q_egmode_t     stag_mode; /* stag mode */
+		fal_pt_1q_egmode_t     ctag_mode; /* ctag mode */
+	} fal_vlantag_egress_mode_t;
+
+	typedef struct
+	{
+		a_uint32_t	port_bitmap; /* rule need know which ports matched this rule */
+
+		a_uint8_t	s_tagged; /* rule need know stag type(untagged/pri_tagged/tagged) */
+		a_bool_t	s_vid_enable; /* check if rule will include service vid value */
+		a_uint32_t	s_vid; /* service vid */
+		a_bool_t	s_pcp_enable; /* check if rule will include service pcp value */
+		a_uint8_t	s_pcp; /* service pcp value */
+		a_bool_t	s_dei_enable; /* check if rule will include service dei value */
+		a_uint8_t	s_dei; /* service dei value */
+
+		a_uint8_t	c_tagged; /* rule need know ctag type(untagged/pri_tagged/tagged) */
+		a_bool_t	c_vid_enable; /* check if rule will include customer vid value */
+		a_uint32_t	c_vid; /* customer vid */
+		a_bool_t	c_pcp_enable; /* check if rule will include customer pcp value */
+		a_uint8_t	c_pcp; /* customer pcp value */
+		a_bool_t	c_dei_enable; /* check if rule will include customer dei value */
+		a_uint8_t	c_dei; /* customert dei value */
+
+		/* these four fields just for vlan ingress rule */
+		a_bool_t	frmtype_enable; /* check if rule will include frame type value */
+		fal_frametype_t	frmtype; /* frame type value */
+		a_bool_t	protocol_enable; /* check if rule will include protocol value */
+		a_uint16_t	protocol; /* protocol value */
+
+		/* these three fields just for vlan egress rule */
+		a_bool_t	vsi_valid; /* check if rule will include vsi value valid */
+		a_bool_t	vsi_enable; /* check if rule will include vsi value */
+		a_uint32_t	vsi; /* vsi value */
+	} fal_vlan_trans_adv_rule_t;
+
+	typedef struct
+	{
+		a_bool_t	swap_svid_cvid; /* check if action will do svid and cvid swap operation */
+		fal_vid_xlt_cmd_t	svid_xlt_cmd; /* check if action will do svid xlt operation */
+		a_uint16_t	svid_xlt; /* service vid xlt value */
+		fal_vid_xlt_cmd_t	cvid_xlt_cmd; /* check if action will do cvid xlt operation */
+		a_uint16_t	cvid_xlt; /* customer vid xlt value */
+
+		a_bool_t	swap_spcp_cpcp; /* check if action will do spcp and cpcp swap operation */
+		a_bool_t	spcp_xlt_enable; /* check if action will enable spcp xlt */
+		a_uint8_t	spcp_xlt; /* service pcp xlt value */
+		a_bool_t	cpcp_xlt_enable; /* check if action will enable cpcp xlt */
+		a_uint8_t	cpcp_xlt; /* customer pcp xlt value */
+
+
+		a_bool_t	swap_sdei_cdei; /* check if action will do sdei and cdei swap operation */
+		a_bool_t	sdei_xlt_enable; /* check if action will enable sdei xlt */
+		a_uint8_t	sdei_xlt; /* service dei xlt value */
+		a_bool_t	cdei_xlt_enable; /* check if action will enable cdei xlt */
+		a_uint8_t	cdei_xlt; /* customer dei xlt value */
+
+		a_bool_t	counter_enable; /* check if action will enable counter_id */
+		a_uint8_t	counter_id;  /* counter id */
+
+		/* these two fields just for vlan ingress action */
+		a_bool_t	vsi_xlt_enable; /* check if action will enable vsi xlt */
+		a_uint8_t	vsi_xlt; /* vsi xlt value */
+	} fal_vlan_trans_adv_action_t;
+
+	typedef struct
+	{
+		a_uint32_t rx_packet_counter; /* ingress vlan translation pkt counter */
+		a_uint64_t rx_byte_counter; /* ingress vlan translation byte counter */
+		a_uint32_t tx_packet_counter; /* egress vlan translation pkt counter */
+		a_uint64_t tx_byte_counter; /* egress vlan translation byte counter */
+	} fal_port_vlan_counter_t;
+
+	sw_error_t
+	fal_port_vlan_counter_get(a_uint32_t dev_id, a_uint32_t cnt_index, fal_port_vlan_counter_t * counter);
+	sw_error_t
+	fal_port_vlan_counter_cleanup(a_uint32_t dev_id, a_uint32_t cnt_index);
+
+    sw_error_t
+    fal_global_qinq_mode_set(a_uint32_t dev_id, fal_global_qinq_mode_t *mode);
+    sw_error_t
+    fal_global_qinq_mode_get(a_uint32_t dev_id, fal_global_qinq_mode_t *mode);
+
+    sw_error_t
+    fal_port_qinq_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode);
+    sw_error_t
+    fal_port_qinq_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode);
+
+    sw_error_t
+    fal_ingress_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid);
+    sw_error_t
+    fal_ingress_tpid_get(a_uint32_t dev_id, fal_tpid_t *tpid);
+
+    sw_error_t
+    fal_egress_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid);
+    sw_error_t
+    fal_egress_tpid_get(a_uint32_t dev_id, fal_tpid_t *tpid);
+
+    sw_error_t
+    fal_port_ingress_vlan_filter_set(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t *filter);
+    sw_error_t
+    fal_port_ingress_vlan_filter_get(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t *filter);
+
+    sw_error_t
+    fal_port_default_vlantag_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_port_vlan_direction_t direction, fal_port_default_vid_enable_t *default_vid_en,
+                                 fal_port_vlan_tag_t *default_tag);
+    sw_error_t
+    fal_port_default_vlantag_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_port_vlan_direction_t direction, fal_port_default_vid_enable_t *default_vid_en,
+                                 fal_port_vlan_tag_t *default_tag);
+
+    sw_error_t
+    fal_port_tag_propagation_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlantag_propagation_t *prop);
+    sw_error_t
+    fal_port_tag_propagation_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlantag_propagation_t *prop);
+
+    sw_error_t
+    fal_port_vlan_xlt_miss_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_fwd_cmd_t cmd);
+    sw_error_t
+    fal_port_vlan_xlt_miss_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_fwd_cmd_t *cmd);
+
+    sw_error_t
+    fal_port_vlantag_egmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_vlantag_egress_mode_t *port_egvlanmode);
+    sw_error_t
+    fal_port_vlantag_egmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_vlantag_egress_mode_t *port_egvlanmode);
+
+    sw_error_t
+    fal_port_vsi_egmode_set(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t egmode);
+
+    sw_error_t
+    fal_port_vsi_egmode_get(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t * egmode);
+
+    sw_error_t
+    fal_port_vlantag_vsi_egmode_enable(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+    sw_error_t
+    fal_port_vlantag_vsi_egmode_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+    sw_error_t
+    fal_port_vlan_trans_adv_add(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                            fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action);
+
+    sw_error_t
+    fal_port_vlan_trans_adv_del(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                            fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action);
+
+    sw_error_t
+    fal_port_vlan_trans_adv_getfirst(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                            fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action);
+
+    sw_error_t
+    fal_port_vlan_trans_adv_getnext(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                            fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _PORT_VLAN_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_pppoe.h b/qca-ssdk/include/fal/fal_pppoe.h
new file mode 100755
index 0000000..6897837
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_pppoe.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_pppoe FAL_PPPOE
+ * @{
+ */
+#ifndef _FAL_PPPOE_H_
+#define _FAL_PPPOE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+enum {
+	FUNC_PPPOE_SESSION_TABLE_ADD = 0,
+	FUNC_PPPOE_SESSION_TABLE_DEL,
+	FUNC_PPPOE_SESSION_TABLE_GET,
+	FUNC_PPPOE_EN_SET,
+	FUNC_PPPOE_EN_GET,
+};
+
+typedef struct
+{
+	a_uint32_t entry_id; /* the entry id saved to pppoe table */
+	a_uint32_t session_id; /* pppoe session id */
+	a_bool_t   multi_session; /* matched multicast session */
+	a_bool_t   uni_session; /* matched unicast session */
+	a_uint32_t vrf_id; /* vrf id, HPPE not supported */
+	a_uint32_t port_bitmap; /* matched ports */
+	a_uint32_t l3_if_index; /* if matched, this l3 interface index will remove pppoe header */
+	a_bool_t   l3_if_valid; /* this l3 interface index valid or not */
+	a_bool_t   smac_valid; /* if matched source mac address */
+	fal_mac_addr_t smac_addr; /* matched source mac address */
+} fal_pppoe_session_t;
+
+sw_error_t
+fal_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+sw_error_t
+fal_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+sw_error_t
+fal_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+sw_error_t
+fal_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+sw_error_t
+fal_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr);
+
+sw_error_t
+fal_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id);
+
+sw_error_t
+fal_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr);
+
+sw_error_t
+fal_pppoe_session_table_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+sw_error_t
+fal_pppoe_session_table_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+sw_error_t
+fal_pppoe_session_table_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+sw_error_t
+fal_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+                         a_uint32_t id);
+
+sw_error_t
+fal_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+                         a_uint32_t * id);
+
+sw_error_t
+fal_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable);
+
+sw_error_t
+fal_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable);
+
+sw_error_t
+fal_pppoe_l3intf_enable(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t enable);
+
+sw_error_t
+fal_pppoe_l3intf_status_get(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t *enable);
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_PPPOE_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_ptp.h b/qca-ssdk/include/fal/fal_ptp.h
new file mode 100755
index 0000000..5fec4c5
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_ptp.h
@@ -0,0 +1,496 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_ptp FAL_PTP
+ * @{
+ */
+#ifndef _FAL_PTP_H_
+#define _FAL_PTP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+typedef enum {
+	FAL_OC_CLOCK_MODE = 0, /* OC clock mode */
+	FAL_BC_CLOCK_MODE,     /* BC clock mode */
+	FAL_E2ETC_CLOCK_MODE,  /* E2E TC clock mode */
+	FAL_P2PTC_CLOCK_MODE   /* P2P TC clock mode */
+} fal_ptp_clock_mode_t;
+
+typedef enum {
+	FAL_ONE_STEP_MODE = 0, /* one step mode */
+	FAL_TWO_STEP_MODE,     /* two step mode */
+	FAL_AUTO_MODE	       /* step mode is selected through packet field */
+} fal_ptp_step_mode_t;
+
+typedef struct {
+	a_bool_t ptp_en;	         /* enable/disable ptp feature */
+	fal_ptp_clock_mode_t clock_mode; /* clock mode */
+	fal_ptp_step_mode_t step_mode;   /* step mode */
+} fal_ptp_config_t;
+
+typedef enum {
+	FAL_REF_CLOCK_LOCAL = 0,/* use local clock as reference clock */
+	FAL_REF_CLOCK_SYNCE,	/* use synce clock as reference clock */
+	FAL_REF_CLOCK_EXTERNAL,	/* use external clock as reference clock */
+} fal_ptp_reference_clock_t;
+
+typedef enum {
+	FAL_RX_TS_MDIO = 0,	/* timestamp will be saved to MDIO register */
+	FAL_RX_TS_EMBED,	/* timestamp will be saved to packet PTP header */
+} fal_ptp_rx_timestamp_mode_t;
+
+typedef struct{
+	a_int64_t seconds;         /* second field */
+	a_int32_t nanoseconds;     /* nano second field */
+	a_int32_t fracnanoseconds; /* fraction nano second field */
+} fal_ptp_time_t;
+
+typedef enum {
+	FAL_RX_DIRECTION = 0,     /* ptp rx direction */
+	FAL_TX_DIRECTION          /* ptp tx direction */
+} fal_ptp_direction_t;
+
+typedef struct{
+	a_uint32_t sequence_id;		/* packet field: sequenceId */
+	a_uint64_t clock_identify;	/* packet field: ClockIdentify */
+	a_uint32_t port_number;		/* packet field: SourcePortID */
+	a_uint32_t msg_type;		/* packet field: message type */
+} fal_ptp_pkt_info_t;
+
+typedef enum {
+	FAL_GM_PPSIN_MODE = 0,	/* use PSSIN mode to sync nanoseconds */
+	FAL_GM_HWPLL_MODE,	/* use HWPLL mode to sync nanoseconds */
+	FAL_GM_SWPLL_MODE,	/* use SWPLL mode to sync nanoseconds */
+} fal_ptp_grandmaster_ns_sync_mode_t;
+
+typedef enum {  /* maximun frequency offset of rtc_clk from PPS source */
+	FAL_GM_MAXFREQ_1PPM = 0,
+	FAL_GM_MAXFREQ_10PPM,
+	FAL_GM_MAXFREQ_50PPM,
+	FAL_GM_MAXFREQ_100PPM,
+	FAL_GM_MAXFREQ_150PPM,
+	FAL_GM_MAXFREQ_200PPM,    /* 802.3 standard select this value */
+	FAL_GM_MAXFREQ_250PPM,
+	FAL_GM_MAXFREQ_300PPM,
+	FAL_GM_MAXFREQ_0PPM
+} fal_ptp_grandmaster_maxfreq_offset_t;
+
+typedef struct {
+	a_bool_t grandmaster_mode_en;	/* enable/disable grandmaster mode */
+	a_bool_t grandmaster_second_sync_en; /* GPS receiver second sync feature */
+	fal_ptp_grandmaster_maxfreq_offset_t freq_offset; /* for HWPLL */
+	a_bool_t right_shift_in_kp; /* for HWPLL, left or right shift */
+	a_uint32_t kp_value; /* for HWPLL, proportional part coefficient */
+	a_bool_t right_shift_in_ki; /* for HWPLL, left or right shift */
+	a_uint32_t ki_value; /* for HWPLL, integral part coefficient */
+	fal_ptp_grandmaster_ns_sync_mode_t ns_sync_mode; /* nano second sync mode */
+} fal_ptp_grandmaster_mode_t;
+
+typedef struct {
+	a_bool_t address_check_en; /* address should matched when regard it as PTP packet */
+	a_bool_t ipv6_udp_checksum_recal_en; /* recalculate ipv6 udp checksum on TX direction */
+	a_bool_t version_check_en; /* PTP version should matched when regard it as PTP packet */
+	a_uint32_t ptp_version;    /* ptp version number to match */
+	a_bool_t ipv4_udp_checksum_force_zero_en; /* force ipv4 checksum to 0 on TX direction */
+	a_bool_t ipv6_embed_udp_checksum_force_zero_en; /* force RX ipv6 checksum to 0 */
+} fal_ptp_security_t;
+
+typedef struct {
+	a_bool_t negative_in_latency;	/* ingress latency value is positive or negative */
+	a_uint32_t in_latency;		/* ingress latency value */
+	a_uint32_t out_phase;		/* adjust the phase of PPS outout signal */
+	a_uint32_t out_pulse_width;	/* adjust the pulse width of PPS outout signal */
+} fal_ptp_pps_signal_control_t;
+
+typedef struct {
+	a_bool_t eg_asym_en;	  /* enable egress asymmetry correction */
+	a_bool_t in_asym_en;	  /* enable ingress asymmetry correction */
+	a_uint32_t eg_asym_value; /* egress asymmetry correction value */
+	a_uint32_t in_asym_value; /* ingress asymmetry correction value */
+} fal_ptp_asym_correction_t;
+
+typedef enum {
+	FAL_WAVE_FREQ = 0,	/* select wave period as SYNC_CLKO_PTP output */
+	FAL_PULSE_10MS,		/* select pulse 10ms as SYNC_CLKO_PTP output */
+	FAL_TRIGGER0_GPIO,	/* select trigger0 status as SYNC_CLKO_PTP output */
+	FAL_RX_PTP_STATE,	/* select RX PTP state as SYNC_CLKO_PTP output */
+} fal_ptp_waveform_type_t;
+
+typedef struct {
+	fal_ptp_waveform_type_t waveform_type; /* select the wave output type */
+	a_bool_t wave_align_pps_out_en;	/* for FAL_WAVE_FREQ, enable wave align pps output */
+	a_uint64_t wave_period;		/* for FAL_WAVE_FREQ, wave period */
+} fal_ptp_output_waveform_t;
+
+enum {
+	FAL_UART_START_POLARITY_HIGH_EN = 0,	/* polarity of start bit is low/high */
+	FAL_UART_MSB_FIRST_EN,			/* output LSB/MSB first */
+	FAL_UART_PARITY_CHECK_EN,		/* parity check is enable/disable */
+	FAL_UART_AUTO_TOD_OUT_EN,		/* enable output TOD via UART automatically */
+	FAL_UART_AUTO_TOD_IN_EN			/* enable input TOD via UART automatically */
+};
+
+enum {
+	FAL_UART_RX_BUFFER_DATA_PRESENT = 0,	/* RX BUFFER has data */
+	FAL_UART_RX_BUFFER_FULL,		/* RX BUFFER is full */
+	FAL_UART_RX_BUFFER_ALMOST_FULL,		/* RX BUFFER is full-1 */
+	FAL_UART_RX_BUFFER_HALF_FULL,		/* RX BUFFER is half full */
+	FAL_UART_RX_BUFFER_ALMOST_EMPTY,	/* RX BUFFER is 1 */
+	FAL_UART_TX_BUFFER_FULL,		/* TX BUFFER is full */
+	FAL_UART_TX_BUFFER_ALMOST_FULL,		/* TX BUFFER is full-1 */
+	FAL_UART_TX_BUFFER_HALF_FULL,		/* TX BUFFER is half full */
+	FAL_UART_TX_BUFFER_ALMOST_EMPTY,	/* TX BUFFER is 1 */
+};
+
+typedef struct {
+	a_uint16_t baud_config;	/* baud_config = (125 * 10^6)/(16)/baud_rate for speed <= 1G */
+				/* baud_config = (200 * 10^6)/(16)/baud_rate for speed >= 2.5 G */
+	a_uint32_t uart_config_bmp; /* refer to FAL_UART_START_POLARITY_HIGH_EN */
+	a_bool_t reset_buf_en;	/* reset TOD UART RX/TX buffer, self clearing */
+	a_uint32_t buf_status_bmp; /* refer to FAL_UART_RX_BUFFER_DATA_PRESENT */
+	a_uint16_t tx_buf_value;   /* the uart data to transport */
+	a_uint16_t rx_buf_value;   /* the uart data received */
+} fal_ptp_tod_uart_t;
+
+enum {
+	FAL_ENHANCED_TS_ETH_TYPE_EN = 0,     /* timestamp the matched ethernet type */
+	FAL_ENHANCED_TS_DMAC_EN,             /* timestamp the matched dst mac */
+	FAL_ENHANCED_TS_RESV_DMAC_EN,        /* timestamp the matched ptp dst mac */
+	FAL_ENHANCED_TS_IPV4_L4_PROTO_EN,    /* timestamp the matched layer 4 protocol id */
+	FAL_ENHANCED_TS_IPV4_DIP_EN,         /* timestamp the matched ipv4 dst addr */
+	FAL_ENHANCED_TS_RESV_IPV4_DIP_EN,    /* timestamp the matched ptp ipv4 dst addr */
+	FAL_ENHANCED_TS_IPV6_NEXT_HEADER_EN, /* timestamp the matched ipv6 next header field */
+	FAL_ENHANCED_TS_IPV6_DIP_EN,         /* timestamp the matched ipv6 dst addr */
+	FAL_ENHANCED_TS_RESV_IPV6_DIP_EN,    /* timestamp the matched ptp ipv6 dst addr */
+	FAL_ENHANCED_TS_UDP_DPORT_EN,        /* timestamp the matched udp dport number */
+	FAL_ENHANCED_TS_RESV_UDP_DPORT_EN,   /* timestamp the matched udp dport number */
+	FAL_ENHANCED_TS_Y1731_EN,            /* timestamp the received Y1731 frame */
+	FAL_ENHANCED_TS_Y1731_TIMESTAMP_INSERT_EN, /* enable inserting RX Y1731 timestamp */
+	FAL_ENHANCED_TS_Y1731_MAC_EN /* TX direction check smac, RX direction check dmac */
+};
+
+enum {
+	FAL_ENHANCED_TS_ETH_TYPE_STATUS = 0,        /* the MAC type of received packet matches
+						      the filter setting */
+	FAL_ENHANCED_TS_DMAC_STATUS,                /* the dest MAC of received packet matches
+						      the filter setting */
+	FAL_ENHANCED_TS_RESV_PRIM_DMAC_STATUS,      /* the dest MAC of received packet matches
+						      PTP primary multicast MAC address */
+	FAL_ENHANCED_TS_RESV_PDELAY_DMAC_STATUS,    /* the dest MAC of received packet matches
+						      PTP peer delay multicast MAC address */
+	FAL_ENHANCED_TS_IPV4_L4_PROTO_STATUS,       /* the L4 layer protocol of received packet
+						      matched the filter setting */
+	FAL_ENHANCED_TS_IPV4_DIP_STATUS,            /* the IPv4 dest address of received packet
+						      matched the filter setting */
+	FAL_ENHANCED_TS_RESV_IPV4_PRIM_DIP_STATUS,  /* the IPv4 dest address of received packet
+						      matches PTP primary multicast ipv4 addr */
+	FAL_ENHANCED_TS_RESV_IPV4_PDELAY_DIP_STATUS,/* the IPv4 dest address of received packet
+							matches PTP peer delay multicast addr */
+	FAL_ENHANCED_TS_IPV6_NEXT_HEADER_STATUS,    /* the next header fielf of receviced packet
+						       matches the filter setting */
+	FAL_ENHANCED_TS_IPV6_DIP_STATUS,            /* the ipv6 dest addr of received packet
+						       matches the filter setting */
+	FAL_ENHANCED_TS_RESV_IPV6_PRIM_DIP_STATUS,  /* the ipv6 dest address of received packet
+						       matches PTP primary multicast ipv6 addr */
+	FAL_ENHANCED_TS_RESV_IPV6_PDELAY_DIP_STATUS,/* the ipv6 dest address of received packet
+						       matches PTP peer delay multicast addr */
+	FAL_ENHANCED_TS_UDP_DPORT_STATUS,           /* the UDP dest port of received packet
+						       matches the filter setting */
+	FAL_ENHANCED_TS_RESV_UDP_DPORT_STATUS,      /* the UDP dest port of received packet
+						       matches udp dport of ptp event packet */
+	FAL_ENHANCED_TS_Y1731_MATCH_STATUS          /* the received frame is Y.1731 OAM frame */
+};
+
+typedef struct {
+	a_bool_t filt_en;	/* enable/disable filter feature */
+	a_uint32_t enhance_ts_conf_bmp; /* refer to FAL_ENHANCED_TS_ETH_TYPE_EN */
+	a_uint32_t eth_type;            /* ethernet type value */
+	fal_mac_addr_t dmac_addr;       /* dest mac address */
+	a_uint32_t ipv4_l4_proto;       /* ipv4 layer 4 protocol field */
+	fal_ip4_addr_t ipv4_dip;        /* ipv4 dest ip addr */
+	fal_ip6_addr_t ipv6_dip;        /* ipv6 dest ip addr */
+	a_uint32_t udp_dport;           /* udp dest port */
+	fal_mac_addr_t y1731_mac_addr;	/* TX check smac, RX check dmac */
+	a_uint32_t enhance_ts_status_bmp; 	/* refer to FAL_ENHANCED_TS_ETH_TYPE_STATUS */
+	a_uint32_t enhance_ts_status_pre_bmp;	/* TX NOT SUPPORT */
+	a_uint32_t y1731_identity;	/* save Y1731 identify value */
+	a_uint32_t y1731_identity_pre;	/* TX NOT SUPPORT */
+	fal_ptp_time_t timestamp;	/* save packet timestamp when matched */
+	fal_ptp_time_t timestamp_pre;	/* TX NOT SUPPORT */
+} fal_ptp_enhanced_ts_engine_t;
+
+typedef struct {
+	a_bool_t trigger_en;            /* enable trigger or not */
+	a_bool_t output_force_en;       /* force trigger output a force value */
+	int output_force_value;         /* the forced value */
+	int patten_select;              /* trigger pattern:
+					   0 single rising edge;
+					   1 single falling edge;
+					   2 trigger pulse;
+					   3 trigger periodic waveform;
+					   4 toggle mode;
+					 */
+	int late_operation;             /* if later, trigger immediately */
+	int notify;                     /* report the completion of trigger */
+	int trigger_effect;             /* write 1 to generate a high pulse when trigger happen */
+	fal_ptp_time_t tim;             /* the trigger timestamp */
+} fal_ptp_trigger_conf_t;
+
+typedef struct {
+	int trigger_finished;           /* trigger finished or not */
+	int trigger_active;             /* trigger is active or not */
+	int trigger_error;              /* trigger error status
+					   0 no error
+					   1 trigger time prior to current time
+					   2 initial value error for edge trigger
+					 */
+} fal_ptp_trigger_status_t;
+
+typedef struct {
+	fal_ptp_trigger_conf_t trigger_conf;
+	fal_ptp_trigger_status_t trigger_status;
+} fal_ptp_trigger_t;
+
+typedef struct {
+	int status_clear;              /* clear event status register */
+	int notify_event;              /* notify event through interrupt */
+	int single_multi_select;       /* 1 for single or 0 for multi event capture */
+	a_bool_t fall_edge_en;         /* enable falling edge detection */
+	a_bool_t rise_edge_en;         /* enable rising edge detection */
+} fal_ptp_capture_conf_t;
+
+typedef struct {
+	int event_detected;            /* event detected or not */
+	int fall_rise_edge_detected;   /* 0 for rising edge, 1 for falling edge detected */
+	int single_multi_detected;     /* 0 for single event, 1 for multi event detected */
+	int event_missed_cnt;          /* the number of events missed */
+	fal_ptp_time_t tim;            /* event timestamp */
+} fal_ptp_capture_status_t;
+
+typedef struct {
+	fal_ptp_capture_conf_t capture_conf;
+	fal_ptp_capture_status_t capture_status;
+} fal_ptp_capture_t;
+
+enum {
+	FAL_PTP_INTR_EXPAND = 0,/* expand interrupt, FAL_PTP_INTR_TX_GTSE ~ FAL_PTP_INTR_CAP1 */
+	FAL_PTP_INTR_RX,	/* ptp pkt rx interrupt */
+	FAL_PTP_INTR_TX,	/* ptp pkt tx interrupt */
+	FAL_PTP_INTR_TX_GTSE,	/* gtse pkt tx interrupt */
+	FAL_PTP_INTR_RX_GTSE,	/* gtse pkt rx interrupt */
+	FAL_PTP_INTR_TX_BUF,	/* uart tod tx buffer half full interrupt */
+	FAL_PTP_INTR_RX_BUF,	/* uart tod rx buffer half full interrupt */
+	FAL_PTP_INTR_PPS_OUT,	/* PPS output interrupt */
+	FAL_PTP_INTR_PPS_IN,	/* PPS input interrupt */
+	FAL_PTP_INTR_10MS,	/* each 10ms interrupt */
+	FAL_PTP_INTR_TRIG0,	/* trigger0 interrupt */
+	FAL_PTP_INTR_TRIG1,	/* trigger1 interrupt */
+	FAL_PTP_INTR_CAP0,	/* capture0 interrupt */
+	FAL_PTP_INTR_CAP1	/* capture1 interrupt */
+};
+
+typedef struct {
+	a_uint32_t intr_mask;
+	a_uint32_t intr_status;
+} fal_ptp_interrupt_t;
+
+sw_error_t
+fal_ptp_config_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_config_t *config);
+
+sw_error_t
+fal_ptp_config_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_config_t *config);
+
+sw_error_t
+fal_ptp_reference_clock_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_reference_clock_t ref_clock);
+
+sw_error_t
+fal_ptp_reference_clock_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_reference_clock_t *ref_clock);
+
+sw_error_t
+fal_ptp_rx_timestamp_mode_set(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_rx_timestamp_mode_t ts_mode);
+
+sw_error_t
+fal_ptp_rx_timestamp_mode_get(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_rx_timestamp_mode_t *ts_mode);
+
+sw_error_t
+fal_ptp_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_direction_t direction,
+		fal_ptp_pkt_info_t *pkt_info,
+		fal_ptp_time_t *time);
+
+sw_error_t
+fal_ptp_pkt_timestamp_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time);
+
+sw_error_t
+fal_ptp_pkt_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time);
+
+sw_error_t
+fal_ptp_grandmaster_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_grandmaster_mode_t *gm_mode);
+
+sw_error_t
+fal_ptp_grandmaster_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_grandmaster_mode_t *gm_mode);
+
+sw_error_t
+fal_ptp_rtc_time_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time);
+
+sw_error_t
+fal_ptp_rtc_time_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time);
+
+sw_error_t
+fal_ptp_rtc_time_clear(a_uint32_t dev_id, a_uint32_t port_id);
+
+sw_error_t
+fal_ptp_rtc_adjtime_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time);
+
+sw_error_t
+fal_ptp_rtc_adjfreq_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time);
+
+sw_error_t
+fal_ptp_rtc_adjfreq_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time);
+
+sw_error_t
+fal_ptp_link_delay_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time);
+
+sw_error_t
+fal_ptp_link_delay_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time);
+
+sw_error_t
+fal_ptp_security_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_security_t *sec);
+
+sw_error_t
+fal_ptp_security_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_security_t *sec);
+
+sw_error_t
+fal_ptp_pps_signal_control_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_pps_signal_control_t *sig_control);
+
+sw_error_t
+fal_ptp_pps_signal_control_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_pps_signal_control_t *sig_control);
+
+sw_error_t
+fal_ptp_rx_crc_recalc_enable(a_uint32_t dev_id, a_uint32_t port_id,
+		a_bool_t status);
+
+sw_error_t
+fal_ptp_rx_crc_recalc_status_get(a_uint32_t dev_id, a_uint32_t port_id,
+		a_bool_t *status);
+
+sw_error_t
+fal_ptp_asym_correction_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_asym_correction_t *asym_cf);
+
+sw_error_t
+fal_ptp_asym_correction_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_asym_correction_t* asym_cf);
+
+sw_error_t
+fal_ptp_output_waveform_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_output_waveform_t *waveform);
+
+sw_error_t
+fal_ptp_output_waveform_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_output_waveform_t *waveform);
+
+sw_error_t
+fal_ptp_rtc_time_snapshot_enable(a_uint32_t dev_id, a_uint32_t port_id,
+		a_bool_t status);
+
+sw_error_t
+fal_ptp_rtc_time_snapshot_status_get(a_uint32_t dev_id, a_uint32_t port_id,
+		a_bool_t *status);
+
+sw_error_t
+fal_ptp_increment_sync_from_clock_enable(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t status);
+
+sw_error_t
+fal_ptp_increment_sync_from_clock_status_get(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t *status);
+
+sw_error_t
+fal_ptp_tod_uart_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_tod_uart_t *tod_uart);
+
+sw_error_t
+fal_ptp_tod_uart_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_tod_uart_t *tod_uart);
+
+sw_error_t
+fal_ptp_enhanced_timestamp_engine_set(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_direction_t direction,
+		fal_ptp_enhanced_ts_engine_t *ts_engine);
+
+sw_error_t
+fal_ptp_enhanced_timestamp_engine_get(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_direction_t direction,
+		fal_ptp_enhanced_ts_engine_t *ts_engine);
+
+sw_error_t
+fal_ptp_trigger_set(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t trigger_id, fal_ptp_trigger_t *triger);
+
+sw_error_t
+fal_ptp_trigger_get(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t trigger_id, fal_ptp_trigger_t *triger);
+
+sw_error_t
+fal_ptp_capture_set(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t capture_id, fal_ptp_capture_t *capture);
+
+sw_error_t
+fal_ptp_capture_get(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t capture_id, fal_ptp_capture_t *capture);
+
+sw_error_t
+fal_ptp_interrupt_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_interrupt_t *interrupt);
+
+sw_error_t
+fal_ptp_interrupt_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_interrupt_t *interrupt);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_PTP_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_qm.h b/qca-ssdk/include/fal/fal_qm.h
new file mode 100755
index 0000000..a15f0b5
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_qm.h
@@ -0,0 +1,344 @@
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_qos FAL_QM
+ * @{
+ */
+#ifndef _FAL_QM_H_
+#define _FAL_QM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+typedef enum {
+	FAL_AC_QUEUE = 0,
+	FAL_AC_GROUP
+} fal_ac_type_t;
+
+typedef struct {
+	fal_ac_type_t type;
+	a_uint32_t obj_id;
+} fal_ac_obj_t;
+
+typedef struct {
+	a_bool_t ac_en; /* 0 for disable and 1 for enable*/
+	a_bool_t ac_fc_en; /* ac for flow control packets */
+} fal_ac_ctrl_t;
+
+typedef struct {
+	a_uint16_t prealloc_buffer; /* guareented buffer number */
+	a_uint16_t total_buffer; /* total buffer number */
+} fal_ac_group_buffer_t;
+
+typedef struct {
+	a_bool_t color_enable; /* 1 for color aware and 0 for color-blind */
+	a_bool_t wred_enable; /* 1 for wred and 0 for tail drop */
+	a_uint16_t green_max;
+	a_uint16_t green_min_off; /*gap between green max and green min*/
+	a_uint16_t yel_max_off; /*gap between green max and yel max*/
+	a_uint16_t yel_min_off; /*gap between green max and yel min*/
+	a_uint16_t red_max_off; /*gap between green max and red max*/
+	a_uint16_t red_min_off; /*gap between green max and red min*/
+	a_uint16_t green_resume_off; /* green resume offset */
+	a_uint16_t yel_resume_off; /* yellow resume offset */
+	a_uint16_t red_resume_off; /* red resume offset */
+} fal_ac_static_threshold_t;
+
+typedef struct {
+	a_bool_t color_enable; /* 1 for color aware and 0 for color-blind */
+	a_bool_t wred_enable; /* 1 for wred and 0 for tail drop */
+	a_uint8_t shared_weight; /* weight in the shared group */
+	a_uint16_t green_min_off; /*gap between green max and green min*/
+	a_uint16_t yel_max_off; /*gap between green max and yel max*/
+	a_uint16_t yel_min_off; /*gap between green max and yel min*/
+	a_uint16_t red_max_off; /*gap between green max and red max*/
+	a_uint16_t red_min_off; /*gap between green max and red min*/
+	a_uint16_t green_resume_off; /* green resume offset */
+	a_uint16_t yel_resume_off; /* yellow resume offset */
+	a_uint16_t red_resume_off; /* red resume offset */
+	a_uint16_t ceiling; /*shared ceiling*/
+} fal_ac_dynamic_threshold_t;
+
+typedef struct {
+	a_uint8_t src_profile; /* queue source profile */
+	a_bool_t service_code_en;
+	a_uint16_t service_code;
+	a_bool_t cpu_code_en;
+	a_uint16_t cpu_code;
+	fal_port_t dst_port; /* destination physical or VP port */
+} fal_ucast_queue_dest_t;
+
+#define FAL_QM_DROP_ITEMS	6
+typedef struct {
+	a_uint32_t tx_packets;
+	a_uint64_t tx_bytes;
+	a_uint32_t pending_buff_num;
+	a_uint32_t drop_packets[FAL_QM_DROP_ITEMS];
+	a_uint64_t drop_bytes[FAL_QM_DROP_ITEMS];
+} fal_queue_stats_t;
+
+enum {
+	FUNC_UCAST_HASH_MAP_SET = 0,
+	FUNC_AC_DYNAMIC_THRESHOLD_GET,
+	FUNC_UCAST_QUEUE_BASE_PROFILE_GET,
+	FUNC_PORT_MCAST_PRIORITY_CLASS_GET,
+	FUNC_AC_DYNAMIC_THRESHOLD_SET,
+	FUNC_AC_PREALLOC_BUFFER_SET,
+	FUNC_UCAST_DEFAULT_HASH_GET,
+	FUNC_UCAST_DEFAULT_HASH_SET,
+	FUNC_AC_QUEUE_GROUP_GET,
+	FUNC_AC_CTRL_GET,
+	FUNC_AC_PREALLOC_BUFFER_GET,
+	FUNC_PORT_MCAST_PRIORITY_CLASS_SET,
+	FUNC_UCAST_HASH_MAP_GET,
+	FUNC_AC_STATIC_THRESHOLD_SET,
+	FUNC_AC_QUEUE_GROUP_SET,
+	FUNC_AC_GROUP_BUFFER_GET,
+	FUNC_MCAST_CPU_CODE_CLASS_GET,
+	FUNC_AC_CTRL_SET,
+	FUNC_UCAST_PRIORITY_CLASS_GET,
+	FUNC_QUEUE_FLUSH,
+	FUNC_MCAST_CPU_CODE_CLASS_SET,
+	FUNC_UCAST_PRIORITY_CLASS_SET,
+	FUNC_AC_STATIC_THRESHOLD_GET,
+	FUNC_UCAST_QUEUE_BASE_PROFILE_SET,
+	FUNC_AC_GROUP_BUFFER_SET,
+	FUNC_QUEUE_COUNTER_CLEANUP,
+	FUNC_QUEUE_COUNTER_GET,
+	FUNC_QUEUE_COUNTER_CTRL_GET,
+	FUNC_QUEUE_COUNTER_CTRL_SET,
+	FUNC_QM_ENQUEUE_CTRL_GET,
+	FUNC_QM_ENQUEUE_CTRL_SET,
+	FUNC_QM_PORT_SRCPROFILE_GET,
+	FUNC_QM_PORT_SRCPROFILE_SET,
+};
+
+sw_error_t
+fal_ac_ctrl_set(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_ctrl_t *cfg);
+
+#ifndef IN_QM_MINI
+sw_error_t
+fal_ac_ctrl_get(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_ctrl_t *cfg);
+#endif
+
+sw_error_t
+fal_ac_prealloc_buffer_set(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		a_uint16_t num);
+
+#ifndef IN_QM_MINI
+sw_error_t
+fal_ac_prealloc_buffer_get(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		a_uint16_t *num);
+#endif
+
+sw_error_t
+fal_ac_queue_group_set(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_uint8_t group_id);
+
+#ifndef IN_QM_MINI
+sw_error_t
+fal_ac_queue_group_get(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_uint8_t *group_id);
+#endif
+
+sw_error_t
+fal_ac_static_threshold_set(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_static_threshold_t *cfg);
+
+#ifndef IN_QM_MINI
+sw_error_t
+fal_ac_static_threshold_get(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_static_threshold_t *cfg);
+#endif
+
+sw_error_t
+fal_ac_dynamic_threshold_set(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		fal_ac_dynamic_threshold_t *cfg);
+
+#ifndef IN_QM_MINI
+sw_error_t
+fal_ac_dynamic_threshold_get(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		fal_ac_dynamic_threshold_t *cfg);
+#endif
+
+sw_error_t
+fal_ac_group_buffer_set(
+		a_uint32_t dev_id,
+		a_uint8_t group_id,
+		fal_ac_group_buffer_t *cfg);
+
+#ifndef IN_QM_MINI
+sw_error_t
+fal_ac_group_buffer_get(
+		a_uint32_t dev_id,
+		a_uint8_t group_id,
+		fal_ac_group_buffer_t *cfg);
+#endif
+
+sw_error_t
+fal_ucast_queue_base_profile_set(
+		a_uint32_t dev_id,
+		fal_ucast_queue_dest_t *queue_dest,
+		a_uint32_t queue_base, a_uint8_t profile);
+
+#ifndef IN_QM_MINI
+sw_error_t
+fal_ucast_queue_base_profile_get(
+		a_uint32_t dev_id,
+		fal_ucast_queue_dest_t *queue_dest,
+		a_uint32_t *queue_base, a_uint8_t *profile);
+
+sw_error_t
+fal_ucast_priority_class_set(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t priority,
+		a_uint8_t class);
+
+sw_error_t
+fal_ucast_priority_class_get(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t priority,
+		a_uint8_t *class);
+
+sw_error_t
+fal_ucast_hash_map_set(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t rss_hash,
+		a_int8_t queue_hash);
+
+sw_error_t
+fal_ucast_hash_map_get(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t rss_hash,
+		a_int8_t *queue_hash);
+
+sw_error_t
+fal_mcast_cpu_code_class_set(
+		a_uint32_t dev_id,
+		a_uint8_t cpu_code,
+		a_uint8_t queue_class);
+
+sw_error_t
+fal_mcast_cpu_code_class_get(
+		a_uint32_t dev_id,
+		a_uint8_t cpu_code,
+		a_uint8_t *queue_class);
+
+sw_error_t
+fal_port_mcast_priority_class_set(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint8_t priority,
+		a_uint8_t queue_class);
+
+sw_error_t
+fal_port_mcast_priority_class_get(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint8_t priority,
+		a_uint8_t *queue_class);
+
+#endif
+sw_error_t
+fal_queue_flush(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint16_t queue_id);
+
+#ifndef IN_QM_MINI
+sw_error_t
+fal_ucast_default_hash_set(
+		a_uint32_t dev_id,
+		a_uint8_t hash_value);
+
+sw_error_t
+fal_ucast_default_hash_get(
+		a_uint32_t dev_id,
+		a_uint8_t *hash_value);
+
+sw_error_t
+fal_queue_counter_ctrl_set(a_uint32_t dev_id, a_bool_t cnt_en);
+
+sw_error_t
+fal_queue_counter_ctrl_get(a_uint32_t dev_id, a_bool_t *cnt_en);
+
+sw_error_t
+fal_queue_counter_get(a_uint32_t dev_id, a_uint32_t queue_id, fal_queue_stats_t *info);
+
+sw_error_t
+fal_queue_counter_cleanup(a_uint32_t dev_id, a_uint32_t queue_id);
+#endif
+
+sw_error_t
+fal_qm_enqueue_ctrl_set(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t enable);
+
+#ifndef IN_QM_MINI
+sw_error_t
+fal_qm_enqueue_ctrl_get(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t *enable);
+
+sw_error_t
+fal_qm_port_source_profile_set(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint32_t src_profile);
+
+sw_error_t
+fal_qm_port_source_profile_get(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint32_t *src_profile);
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _PORT_QM_H_ */
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/fal/fal_qos.h b/qca-ssdk/include/fal/fal_qos.h
new file mode 100644
index 0000000..30c894e
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_qos.h
@@ -0,0 +1,442 @@
+/*
+ * Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_qos FAL_QOS
+ * @{
+ */
+#ifndef _FAL_QOS_H_
+#define _FAL_QOS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+    /**
+    @brief This enum defines traffic scheduling mode.
+    */
+    typedef enum {
+        FAL_SCH_SP_MODE = 0,    /**<  strict priority scheduling mode */
+        FAL_SCH_WRR_MODE,       /**<   weight round robin scheduling mode*/
+        FAL_SCH_MIX_MODE,       /**<  sp and wrr mixed scheduling mode */
+        FAL_SCH_MIX_PLUS_MODE,  /**<  sp and wrr mixed plus scheduling mode */
+        FAL_SCH_MODE_BUTT
+    }
+    fal_sch_mode_t;
+
+    /**
+    @brief This enum defines qos assignment mode.
+    */
+    typedef enum
+    {
+        FAL_QOS_DA_MODE = 0,    /**<   qos assignment based on destination mac address*/
+        FAL_QOS_UP_MODE,        /**<   qos assignment based on 802.1p field in vlan tag*/
+        FAL_QOS_DSCP_MODE,      /**<  qos assignment based on dscp field in ip header */
+        FAL_QOS_PORT_MODE,      /**<  qos assignment based on port */
+        FAL_QOS_FLOW_MODE,      /**<  qos assignment based on flow */
+        FAL_QOS_MODE_BUTT
+    } fal_qos_mode_t;
+
+typedef struct {
+	a_uint8_t pcp_group; /* 0: group 0 1: group 1 */
+	a_uint8_t dscp_group;
+	a_uint8_t flow_group;
+} fal_qos_group_t;
+
+typedef struct {
+	a_uint8_t pcp_pri;
+	a_uint8_t dscp_pri;
+	a_int8_t preheader_pri;
+	a_uint8_t flow_pri;
+	a_uint8_t acl_pri;
+	a_uint8_t post_acl_pri;
+	a_bool_t pcp_pri_force;
+	a_bool_t dscp_pri_force;
+} fal_qos_pri_precedence_t;
+
+typedef struct {
+	a_bool_t pcp_change_en;
+	a_bool_t dei_chage_en;
+	a_bool_t dscp_change_en;
+} fal_qos_remark_enable_t;
+
+typedef struct {
+	a_uint8_t internal_pcp;
+	a_uint8_t internal_dei;
+	a_uint8_t internal_pri;
+	a_uint8_t internal_dscp;
+	a_uint8_t internal_dp;
+	a_uint8_t dscp_mask;
+	a_bool_t dscp_en;
+	a_bool_t pcp_en;
+	a_bool_t dei_en;
+	a_bool_t pri_en;
+	a_bool_t dp_en;
+	a_uint8_t qos_prec; /* resolution precedence */
+} fal_qos_cosmap_t;
+
+typedef enum {
+	FAL_DRR_IPG_PREAMBLE_FRAME_CRC = 0, /* IPG + Preamble + Frame + CRC */
+	FAL_DRR_FRAME_CRC, /* Frame + CRC */
+	FAL_DRR_L3_EXCLUDE_CRC  /* after Ethernet type excude CRC*/
+} fal_qos_drr_frame_mode_t;
+
+typedef struct {
+	a_uint8_t sp_id; /* SP id L0:0~63 L1:0~7 */
+	a_uint8_t e_pri; /*SP priority for E path:0~7 low to high */
+	a_uint8_t c_pri; /* SP priority for C path: 0~7 low to high */
+	a_uint8_t c_drr_id; /*C DRR ID L0:0~159 L1:0~35*/
+	a_uint8_t e_drr_id; /*E DRR ID L0:0~159 L1:0~35*/
+	a_uint16_t e_drr_wt; /* DRR weight in E DRR: 0~1023 */
+	a_uint16_t c_drr_wt; /* DRR weight in C DRR: 0~1023 */
+	a_uint8_t c_drr_unit; /* 0:byte based; 1:packet based */
+	a_uint8_t e_drr_unit; /* 0:byte based; 1:packet based */
+	fal_qos_drr_frame_mode_t drr_frame_mode;
+} fal_qos_scheduler_cfg_t;
+
+typedef struct {
+	a_uint32_t en_scheduler_port_bmp; /* port bitmap of en-scheduler */
+	a_uint32_t en_scheduler_port; /* port of en-scheduler */
+	a_uint32_t de_scheduler_port; /* port of de-shceduler */
+} fal_port_scheduler_cfg_t;
+
+typedef enum {
+	FAL_QUEUE_SCHEDULER_LEVEL0 = 0,
+	FAL_QUEUE_SCHEDULER_LEVEL1,
+} fal_queue_scheduler_level_t;
+
+
+typedef struct {
+	a_uint32_t bmp[10];
+} fal_queue_bmp_t;
+
+enum {
+	FUNC_QOS_PORT_PRI_SET = 0,
+	FUNC_QOS_PORT_PRI_GET,
+	FUNC_QOS_COSMAP_PCP_GET,
+	FUNC_QUEUE_SCHEDULER_SET,
+	FUNC_QUEUE_SCHEDULER_GET,
+	FUNC_PORT_QUEUES_GET,
+	FUNC_QOS_COSMAP_PCP_SET,
+	FUNC_QOS_PORT_REMARK_GET,
+	FUNC_QOS_COSMAP_DSCP_GET,
+	FUNC_QOS_COSMAP_FLOW_SET,
+	FUNC_QOS_PORT_GROUP_SET,
+	FUNC_RING_QUEUE_MAP_SET,
+	FUNC_QOS_COSMAP_DSCP_SET,
+	FUNC_QOS_PORT_REMARK_SET,
+	FUNC_QOS_COSMAP_FLOW_GET,
+	FUNC_QOS_PORT_GROUP_GET,
+	FUNC_RING_QUEUE_MAP_GET,
+	FUNC_TDM_TICK_NUM_SET,
+	FUNC_TDM_TICK_NUM_GET,
+	FUNC_PORT_SCHEDULER_CFG_SET,
+	FUNC_PORT_SCHEDULER_CFG_GET,
+	FUNC_SCHEDULER_DEQUEUE_CTRL_GET,
+	FUNC_SCHEDULER_DEQUEUE_CTRL_SET,
+	FUNC_QOS_PORT_MODE_PRI_GET,
+	FUNC_QOS_PORT_MODE_PRI_SET,
+	FUNC_QOS_PORT_SCHEDULER_CFG_RESET,
+	FUNC_QOS_PORT_SCHEDULER_RESOURCE_GET,
+};
+
+typedef struct {
+	a_uint16_t ucastq_start;
+	a_uint16_t ucastq_num;
+	a_uint16_t mcastq_start;
+	a_uint16_t mcastq_num;
+	a_uint16_t l0sp_start;
+	a_uint16_t l0sp_num;
+	a_uint16_t l0cdrr_start;
+	a_uint16_t l0cdrr_num;
+	a_uint16_t l0edrr_start;
+	a_uint16_t l0edrr_num;
+	a_uint16_t l1sp_start;
+	a_uint16_t l1sp_num;
+	a_uint16_t l1cdrr_start;
+	a_uint16_t l1cdrr_num;
+	a_uint16_t l1edrr_start;
+	a_uint16_t l1edrr_num;
+} fal_portscheduler_resource_t;
+
+#define FAL_DOT1P_MIN    0
+#define FAL_DOT1P_MAX    7
+
+#define FAL_DSCP_MIN     0
+#define FAL_DSCP_MAX     63
+
+#ifndef IN_QOS_MINI
+    sw_error_t
+    fal_qos_sch_mode_set(a_uint32_t dev_id,
+                         fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+
+    sw_error_t
+    fal_qos_sch_mode_get(a_uint32_t dev_id,
+                         fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+
+    sw_error_t
+    fal_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable);
+
+    sw_error_t
+    fal_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t * enable);
+
+
+    sw_error_t
+    fal_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_queue_t queue_id, a_uint32_t * number);
+
+
+    sw_error_t
+    fal_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable);
+
+
+    sw_error_t
+    fal_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable);
+
+    
+
+    sw_error_t
+    fal_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+
+    
+
+
+    sw_error_t
+    fal_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * number);
+
+    sw_error_t
+    fal_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * number);
+
+    sw_error_t
+    fal_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+                            fal_queue_t queue);
+
+
+    sw_error_t
+    fal_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+                            fal_queue_t * queue);
+
+
+    sw_error_t
+    fal_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+                              fal_queue_t queue);
+
+
+    sw_error_t
+    fal_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+                              fal_queue_t * queue);
+#endif
+	sw_error_t
+    fal_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * number);
+	sw_error_t
+    fal_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+    sw_error_t
+    fal_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_qos_mode_t mode, a_bool_t enable);
+
+	sw_error_t
+    fal_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * number);
+
+    
+	sw_error_t
+    fal_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_queue_t queue_id, a_uint32_t * number);
+
+#ifndef IN_QOS_MINI
+sw_error_t
+    fal_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_qos_mode_t mode, a_bool_t * enable);
+
+    sw_error_t
+    fal_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_qos_mode_t mode, a_uint32_t pri);
+
+
+    sw_error_t
+    fal_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_qos_mode_t mode, a_uint32_t * pri);
+
+
+    sw_error_t
+    fal_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t up);
+
+
+    sw_error_t
+    fal_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * up);
+
+    sw_error_t
+    fal_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                              fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+    sw_error_t
+    fal_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                              fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+    sw_error_t
+    fal_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t spri);
+
+    sw_error_t
+    fal_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t * spri);
+
+    sw_error_t
+    fal_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t cpri);
+
+    sw_error_t
+    fal_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t * cpri);
+
+    sw_error_t
+    fal_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                       a_bool_t enable);
+
+    sw_error_t
+    fal_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                       a_bool_t* enable);
+
+    sw_error_t
+    fal_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                       a_bool_t enable);
+
+    sw_error_t
+    fal_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                       a_bool_t* enable);
+
+    sw_error_t
+    fal_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable);
+
+
+    sw_error_t
+    fal_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable);
+#endif
+
+sw_error_t
+fal_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_group_t *group);
+
+sw_error_t
+fal_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_group_t *group);
+
+sw_error_t
+fal_qos_port_pri_precedence_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_pri_precedence_t *pri);
+
+sw_error_t
+fal_qos_port_pri_precedence_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_pri_precedence_t *pri);
+
+sw_error_t
+fal_qos_port_remark_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_remark_enable_t *remark);
+
+sw_error_t
+fal_qos_port_remark_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_remark_enable_t *remark);
+
+sw_error_t
+fal_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t pcp, fal_qos_cosmap_t *cosmap);
+
+sw_error_t
+fal_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t pcp, fal_qos_cosmap_t *cosmap);
+
+sw_error_t
+fal_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint16_t flow, fal_qos_cosmap_t *cosmap);
+
+sw_error_t
+fal_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint16_t flow, fal_qos_cosmap_t *cosmap);
+
+sw_error_t
+fal_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t dscp, fal_qos_cosmap_t *cosmap);
+
+sw_error_t
+fal_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t dscp, fal_qos_cosmap_t *cosmap);
+
+
+sw_error_t
+fal_queue_scheduler_set(a_uint32_t dev_id,
+					a_uint32_t node_id, fal_queue_scheduler_level_t level,
+					fal_port_t port_id,
+					fal_qos_scheduler_cfg_t *scheduler_cfg);
+
+sw_error_t
+fal_queue_scheduler_get(a_uint32_t dev_id,
+					a_uint32_t node_id, fal_queue_scheduler_level_t level,
+					fal_port_t *port_id,
+					fal_qos_scheduler_cfg_t *scheduler_cfg);
+
+sw_error_t
+fal_edma_ring_queue_map_get(a_uint32_t dev_id, 
+					a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp);
+
+sw_error_t
+fal_edma_ring_queue_map_set(a_uint32_t dev_id, 
+					a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp);
+sw_error_t
+fal_port_queues_get(a_uint32_t dev_id, 
+				fal_port_t port_id, fal_queue_bmp_t *queue_bmp);
+
+sw_error_t
+fal_scheduler_dequeue_ctrl_set(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t enable);
+
+sw_error_t
+fal_scheduler_dequeue_ctrl_get(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t *enable);
+
+sw_error_t
+fal_port_scheduler_cfg_reset(
+		a_uint32_t dev_id,
+		fal_port_t port_id);
+
+sw_error_t
+fal_port_scheduler_resource_get(
+		a_uint32_t dev_id,
+		fal_port_t port_id,
+		fal_portscheduler_resource_t *cfg);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _PORT_QOS_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_rate.h b/qca-ssdk/include/fal/fal_rate.h
new file mode 100755
index 0000000..99c7377
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_rate.h
@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_rate FAL_RATE
+ * @{
+ */
+#ifndef _FAL_RATE_H_
+#define _FAL_RATE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+    /**
+    @brief This enum defines storm type
+    */
+    typedef enum {
+        FAL_UNICAST_STORM = 0,      /**<  storm caused by unknown unicast packets */
+        FAL_MULTICAST_STORM,        /**<  storm caused by unknown multicast packets */
+        FAL_BROADCAST_STORM,        /**<  storm caused by broadcast packets */
+        FAL_STORM_TYPE_BUTT
+    }
+    fal_storm_type_t;
+
+
+
+    sw_error_t
+    fal_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_queue_t queue_id, a_uint32_t * speed,
+                            a_bool_t enable);
+
+
+
+    sw_error_t
+    fal_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_queue_t queue_id, a_uint32_t * speed,
+                            a_bool_t * enable);
+
+
+
+    sw_error_t
+    fal_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * speed, a_bool_t enable);
+
+
+
+    sw_error_t
+    fal_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * speed, a_bool_t * enable);
+
+
+
+    sw_error_t
+    fal_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * speed, a_bool_t enable);
+
+
+
+    sw_error_t
+    fal_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * speed, a_bool_t * enable);
+
+
+
+    sw_error_t
+    fal_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_storm_type_t frame_type, a_bool_t enable);
+
+
+
+    sw_error_t
+    fal_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_storm_type_t frame_type,
+                             a_bool_t * enable);
+
+
+
+    sw_error_t
+    fal_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * rate);
+
+
+
+    sw_error_t
+    fal_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * rate);
+
+
+    typedef enum
+    {
+        FAL_RATE_MI_100US = 0,
+        FAL_RATE_MI_1MS,
+        FAL_RATE_MI_10MS,
+        FAL_RATE_MI_100MS,
+    } fal_rate_mt_t;
+
+
+    typedef struct
+    {
+        fal_traffic_unit_t meter_unit;
+        a_uint32_t         cir;
+        a_uint32_t         eir;
+        a_uint32_t         cbs;
+        a_uint32_t         ebs;
+    } fal_egress_shaper_t;
+
+
+#define FAL_INGRESS_POLICING_TCP_CTRL     0x2
+#define FAL_INGRESS_POLICING_MANAGEMENT   0x4
+#define FAL_INGRESS_POLICING_BROAD        0x8
+#define FAL_INGRESS_POLICING_UNK_UNI      0x10
+#define FAL_INGRESS_POLICING_UNK_MUL      0x20
+#define FAL_INGRESS_POLICING_UNI          0x40
+#define FAL_INGRESS_POLICING_MUL          0x80
+
+
+    typedef struct
+    {
+        a_bool_t           c_enable;
+        a_bool_t           e_enable;
+        a_bool_t           combine_mode;
+        fal_traffic_unit_t meter_unit;
+        a_bool_t           color_mode;
+        a_bool_t           couple_flag;
+        a_bool_t           deficit_en;
+        a_uint32_t         cir;
+        a_uint32_t         eir;
+        a_uint32_t         cbs;
+        a_uint32_t         ebs;
+        a_uint32_t         c_rate_flag;
+        a_uint32_t         e_rate_flag;
+        fal_rate_mt_t      c_meter_interval;
+        fal_rate_mt_t      e_meter_interval;
+    } fal_port_policer_t;
+
+
+    typedef struct
+    {
+        a_bool_t           counter_mode;
+        fal_traffic_unit_t meter_unit;
+        fal_rate_mt_t      meter_interval;
+        a_bool_t           color_mode;
+        a_bool_t           couple_flag;
+        a_bool_t           deficit_en;
+        a_uint32_t         cir;
+        a_uint32_t         eir;
+        a_uint32_t         cbs;
+        a_uint32_t         ebs;
+        a_uint32_t         counter_high;
+        a_uint32_t         counter_low;
+    } fal_acl_policer_t;
+
+
+    sw_error_t
+    fal_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_port_policer_t * policer);
+
+
+    sw_error_t
+    fal_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_port_policer_t * policer);
+
+
+    sw_error_t
+    fal_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable, fal_egress_shaper_t * shaper);
+
+
+    sw_error_t
+    fal_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable, fal_egress_shaper_t * shaper);
+
+
+    sw_error_t
+    fal_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_queue_t queue_id, a_bool_t enable,
+                              fal_egress_shaper_t * shaper);
+
+
+    sw_error_t
+    fal_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_queue_t queue_id, a_bool_t * enable,
+                              fal_egress_shaper_t * shaper);
+
+
+    sw_error_t
+    fal_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+                             fal_acl_policer_t * policer);
+
+
+    sw_error_t
+    fal_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+                             fal_acl_policer_t * policer);
+
+    sw_error_t
+    fal_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_uint32_t  number);
+
+    sw_error_t
+    fal_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_uint32_t  *number);
+
+    sw_error_t
+    fal_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t  enable);
+    sw_error_t
+    fal_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t*  enable);
+
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_RATE_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_reg_access.h b/qca-ssdk/include/fal/fal_reg_access.h
new file mode 100755
index 0000000..c5389a5
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_reg_access.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*qca808x_start*/
+/**
+ * @defgroup fal_reg_access FAL_REG_ACCESS
+ * @{
+ */
+#ifndef _FAL_REG_ACCESS_H_
+#define _FAL_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+    sw_error_t
+    fal_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+                a_uint32_t reg, a_uint16_t * value);
+
+    sw_error_t
+    fal_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+                a_uint32_t reg, a_uint16_t value);
+/*qca808x_end*/
+
+    sw_error_t
+    fal_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                a_uint32_t value_len);
+
+    sw_error_t
+    fal_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                a_uint32_t value_len);
+
+    sw_error_t
+    fal_psgmii_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                a_uint32_t value_len);
+
+    sw_error_t
+    fal_psgmii_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                a_uint32_t value_len);
+
+    sw_error_t
+    fal_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                      a_uint32_t bit_offset, a_uint32_t field_len,
+                      a_uint8_t value[], a_uint32_t value_len);
+
+    sw_error_t
+    fal_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                      a_uint32_t bit_offset, a_uint32_t field_len,
+                      const a_uint8_t value[], a_uint32_t value_len);
+
+	sw_error_t
+	fal_debug_reg_dump(a_uint32_t dev_id, fal_debug_reg_dump_t *reg_dump);
+
+	sw_error_t
+	fal_reg_dump(a_uint32_t dev_id, a_uint32_t reg_idx,fal_reg_dump_t *reg_dump);
+
+	sw_error_t
+	fal_debug_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable,
+		a_uint32_t times, a_uint32_t *result);
+
+	sw_error_t
+	fal_phy_dump(a_uint32_t dev_id, a_uint32_t phy_addr,
+		a_uint32_t idx, fal_phy_dump_t * phy_dump);
+
+	sw_error_t
+	fal_uniphy_reg_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr,
+		a_uint8_t value[], a_uint32_t value_len);
+
+	sw_error_t
+	fal_uniphy_reg_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr,
+		a_uint8_t value[], a_uint32_t value_len);
+
+/*qca808x_start*/
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_REG_ACCESS_H_ */
+
+/**
+ * @}
+ */
+/*qca808x_end*/
+
diff --git a/qca-ssdk/include/fal/fal_rfs.h b/qca-ssdk/include/fal/fal_rfs.h
new file mode 100755
index 0000000..08c64d6
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_rfs.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_rfs FAL_RFS
+ * @{
+ */
+#ifndef _FAL_RFS_H_
+#define _FAL_RFS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+#if 0
+typedef struct
+{
+    u8 addr[6];
+    u16    fid;
+    u8 load_balance;
+} ssdk_fdb_rfs_t;
+
+typedef struct
+{
+    u8 mac_addr[6];
+    u32 ip4_addr;
+	u32     vid;
+	u8      load_balance;
+} ssdk_ip4_rfs_t;
+
+typedef struct
+{
+    u8 mac_addr[6];
+    u32 ip6_addr[4];
+	u32     vid;
+	u8      load_balance;
+} ssdk_ip6_rfs_t;
+
+
+
+int ssdk_rfs_ipct_rule_set(
+	__be32 ip_src, __be32 ip_dst,
+	__be16 sport, __be16 dport, uint8_t proto,
+	u16 loadbalance, bool action);
+
+int ssdk_rfs_mac_rule_set(ssdk_fdb_rfs_t *rfs);
+int ssdk_rfs_mac_rule_del(ssdk_fdb_rfs_t *rfs);
+
+int
+ssdk_ip_rfs_ip4_rule_set(ssdk_ip4_rfs_t * rfs);
+
+int
+ssdk_ip_rfs_ip6_rule_set(ssdk_ip6_rfs_t * rfs);
+
+int
+ssdk_ip_rfs_ip4_rule_del(ssdk_ip4_rfs_t * rfs);
+
+int
+ssdk_ip_rfs_ip6_rule_del(ssdk_ip6_rfs_t * rfs);
+#endif
+int ssdk_rfs_mac_rule_set(u16 vid, u8* mac, u8 ldb, int is_set);
+int ssdk_rfs_ip4_rule_set(u16 vid, u32 ip, u8* mac, u8 ldb, int is_set);
+int ssdk_rfs_ip6_rule_set(u16 vid, u8* ip, u8* mac, u8 ldb, int is_set);
+int ssdk_rfs_ipct_rule_set(
+	__be32 ip_src, __be32 ip_dst,
+	__be16 sport, __be16 dport, uint8_t proto,
+	u16 loadbalance, bool action);
+
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_RFS_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/fal/fal_rss_hash.h b/qca-ssdk/include/fal/fal_rss_hash.h
new file mode 100755
index 0000000..e11b9b0
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_rss_hash.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_gen FAL_RSS_HASH
+ * @{
+ */
+#ifndef _FAL_RSS_HASH_H_
+#define _FAL_RSS_HASH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+#if defined(SW_API_LOCK) && (!defined(HSL_STANDALONG))
+#define FAL_RSS_HASH_API_LOCK
+#define FAL_RSS_HASH_API_UNLOCK
+#else
+#define FAL_RSS_HASH_API_LOCK
+#define FAL_RSS_HASH_API_UNLOCK
+#endif
+
+typedef enum
+{
+	FAL_RSS_HASH_IPV4V6 = 0,
+	FAL_RSS_HASH_IPV4ONLY = 1,
+	FAL_RSS_HASH_IPV6ONLY = 2,
+} fal_rss_hash_mode_t;
+
+typedef struct
+{
+	a_uint32_t 	hash_mask; /* final hash value bits */
+	a_bool_t	hash_fragment_mode; /* enable fragment mode or not */
+	a_uint32_t	hash_seed; /* rss hash seed value */
+	a_uint32_t	hash_sip_mix; /* source ip hash mix */
+	a_uint32_t	hash_dip_mix; /* dest ip hash mix */
+	a_uint8_t	hash_protocol_mix; /* L4 protocol hash mix */
+	a_uint8_t	hash_sport_mix; /* L4 source port hash mix */
+	a_uint8_t	hash_dport_mix; /* L4 dest port hash mix */
+	a_uint32_t	hash_fin_inner; /* hash fin inner mix */
+	a_uint32_t	hash_fin_outer; /* hash fin outer mix */
+} fal_rss_hash_config_t;
+
+enum {
+	FUNC_RSS_HASH_CONFIG_SET = 0,
+	FUNC_RSS_HASH_CONFIG_GET,
+};
+
+sw_error_t
+fal_rss_hash_config_set(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config);
+
+sw_error_t
+fal_rss_hash_config_get(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_RSS_HASH_H_ */
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/fal/fal_sec.h b/qca-ssdk/include/fal/fal_sec.h
new file mode 100755
index 0000000..eff27fe
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_sec.h
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_sec FAL_SEC
+ * @{
+ */
+#ifndef _FAL_SEC_H_
+#define _FAL_SEC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+/* Exception: L2 */
+#define FAL_SEC_EXP_UNKNOWN_L2_PROT                  1
+#define FAL_SEC_EXP_PPPOE_WRONG_VER_TYPE             2
+#define FAL_SEC_EXP_PPPOE_WRONG_CODE                 3
+#define FAL_SEC_EXP_PPPOE_UNSUPPORTED_PPP_PROT       4
+/* Exception: IPv4 */
+#define FAL_SEC_EXP_IPV4_WRONG_VER                   5
+#define FAL_SEC_EXP_IPV4_SMALL_IHL                   6
+#define FAL_SEC_EXP_IPV4_WITH_OPTION                 7
+
+#define FAL_SEC_EXP_IPV4_HDR_INCOMPLETE              8
+
+#define FAL_SEC_EXP_IPV4_BAD_TOTAL_LEN               9
+#define FAL_SEC_EXP_IPV4_DATA_INCOMPLETE             10
+
+#define FAL_SEC_EXP_IPV4_FRAG                        11
+#define FAL_SEC_EXP_IPV4_PING_OF_DEATH               12
+
+#define FAL_SEC_EXP_IPV4_SNALL_TTL                   13
+#define FAL_SEC_EXP_IPV4_UNK_IP_PROT                 14
+#define FAL_SEC_EXP_IPV4_CHECKSUM_ERR                15
+#define FAL_SEC_EXP_IPV4_INV_SIP                     16
+#define FAL_SEC_EXP_IPV4_INV_DIP                     17
+#define FAL_SEC_EXP_IPV4_LAND_ATTACK                 18
+#define FAL_SEC_EXP_IPV4_AH_HDR_INCOMPLETE           19
+#define FAL_SEC_EXP_IPV4_AH_HDR_CROSS_BORDER         20
+#define FAL_SEC_EXP_IPV4_ESP_HDR_INCOMPLETE          21
+/* Exception: IPv6 */
+#define FAL_SEC_EXP_IPV6_WRONG_VER                   22
+#define FAL_SEC_EXP_IPV6_HDR_INCOMPLETE              23
+#define FAL_SEC_EXP_IPV6_BAD_PAYLOAD_LEN             24
+#define FAL_SEC_EXP_IPV6_DATA_INCOMPLETE             25
+#define FAL_SEC_EXP_IPV6_WITH_EXT_HDR                26
+#define FAL_SEC_EXP_IPV6_SMALL_HOP_LIMIT             27
+#define FAL_SEC_EXP_IPV6_INV_SIP                     28
+#define FAL_SEC_EXP_IPV6_INV_DIP                     29
+#define FAL_SEC_EXP_IPV6_LAND_ATTACK                 30
+#define FAL_SEC_EXP_IPV6_FRAG                        31
+#define FAL_SEC_EXP_IPV6_PING_OF_DEATH               32
+#define FAL_SEC_EXP_IPV6_WITH_MORE_EXT_HDR           33
+#define FAL_SEC_EXP_IPV6_UNK_LAST_NEXT_HDR           34
+#define FAL_SEC_EXP_IPV6_MOBILITY_HDR_INCOMPLETE     35
+#define FAL_SEC_EXP_IPV6_MOBILITY_HDR_CROSS_BORDER   36
+#define FAL_SEC_EXP_IPV6_AH_HDR_INCOMPLETE           37
+#define FAL_SEC_EXP_IPV6_AH_HDR_CROSS_BORDER         38
+#define FAL_SEC_EXP_IPV6_ESP_HDR_INCOMPLETE          39
+#define FAL_SEC_EXP_IPV6_ESP_HDR_CROSS_BORDER        40
+
+#define FAL_SEC_EXP_IPV6_OTHER_EXT_HDR_INCOMPLETE    41
+#define FAL_SEC_EXP_IPV6_OTHER_EXT_HDR_CROSS_BORDER  42
+
+/* Exception: L4 */
+#define FAL_SEC_EXP_TCP_HDR_INCOMPLETE               43
+#define FAL_SEC_EXP_TCP_HDR_CROSS_BORDER             44
+#define FAL_SEC_EXP_TCP_SMAE_SP_DP                   45
+#define FAL_SEC_EXP_TCP_SMALL_DATA_OFFSET            46
+#define FAL_SEC_EXP_TCP_FLAGS_0                      47
+#define FAL_SEC_EXP_TCP_FLAGS_1                      48
+#define FAL_SEC_EXP_TCP_FLAGS_2                      49
+#define FAL_SEC_EXP_TCP_FLAGS_3                      50
+#define FAL_SEC_EXP_TCP_FLAGS_4                      51
+#define FAL_SEC_EXP_TCP_FLAGS_5                      52
+#define FAL_SEC_EXP_TCP_FLAGS_6                      53
+#define FAL_SEC_EXP_TCP_FLAGS_7                      54
+#define FAL_SEC_EXP_TCP_CHECKSUM_ERR                 55
+#define FAL_SEC_EXP_UDP_HDR_INCOMPLETE               56
+#define FAL_SEC_EXP_UDP_HDR_CROSS_BORDER             57
+
+#define FAL_SEC_EXP_UDP_SMAE_SP_DP                   58
+#define FAL_SEC_EXP_UDP_BAD_LEN                      59
+#define FAL_SEC_EXP_UDP_DATA_INCOMPLETE              60
+
+
+#define FAL_SEC_EXP_UDP_CHECKSUM_ERR                 61
+#define FAL_SEC_EXP_UDP_LITE_HDR_INCOMPLETE          62
+#define FAL_SEC_EXP_UDP_LITE_HDR_CROSS_BORDER        63
+#define FAL_SEC_EXP_UDP_LITE_SMAE_SP_DP              64
+/* Other exception  */
+#define FAL_SEC_EXP_UDP_LITE_CSM_COV_1_TO_7          65
+#define FAL_SEC_EXP_UDP_LITE_CSM_COV_TOO_LONG        66
+#define FAL_SEC_EXP_UDP_LITE_CSM_COV_CROSS_BORDER    67
+#define FAL_SEC_EXP_UDP_LITE_CHECKSUM_ERR            68
+
+/**/
+
+#define FAL_SEC_EXP_FAKE_L2_PROT_ERR                 69
+#define FAL_SEC_EXP_FAKE_MAC_HEADER_ERR              70
+
+
+    typedef enum {
+        /* define MAC layer related normalization items */
+        FAL_NORM_MAC_RESV_VID_CMD = 0,
+        FAL_NORM_MAC_INVALID_SRC_ADDR_CMD,
+
+        /* define IP layer related normalization items */
+        FAL_NORM_IP_INVALID_VER_CMD,
+        FAL_NROM_IP_SAME_ADDR_CMD,
+        FAL_NROM_IP_TTL_CHANGE_STATUS,
+        FAL_NROM_IP_TTL_VALUE,
+
+        /* define IP4 related normalization items */
+        FAL_NROM_IP4_INVALID_HL_CMD,
+        FAL_NROM_IP4_HDR_OPTIONS_CMD,
+        FAL_NROM_IP4_INVALID_DF_CMD,
+        FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD,
+        FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD,
+        FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD,
+        FAL_NROM_IP4_INVALID_SIP_CMD,
+        FAL_NROM_IP4_INVALID_DIP_CMD,
+        FAL_NROM_IP4_INVALID_CHKSUM_CMD,
+        FAL_NROM_IP4_INVALID_PL_CMD,
+        FAL_NROM_IP4_DF_CLEAR_STATUS,
+        FAL_NROM_IP4_IPID_RANDOM_STATUS,
+        FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE,
+
+        /* define IP4 related normalization items */
+        FAL_NROM_IP6_INVALID_PL_CMD,
+        FAL_NROM_IP6_INVALID_SIP_CMD,
+        FAL_NROM_IP6_INVALID_DIP_CMD,
+
+        /* define TCP related normalization items */
+        FAL_NROM_TCP_BLAT_CMD,
+        FAL_NROM_TCP_INVALID_HL_CMD,
+        FAL_NROM_TCP_INVALID_SYN_CMD,
+        FAL_NROM_TCP_SU_BLOCK_CMD,
+        FAL_NROM_TCP_SP_BLOCK_CMD,
+        FAL_NROM_TCP_SAP_BLOCK_CMD,
+        FAL_NROM_TCP_XMAS_SCAN_CMD,
+        FAL_NROM_TCP_NULL_SCAN_CMD,
+        FAL_NROM_TCP_SR_BLOCK_CMD,
+        FAL_NROM_TCP_SF_BLOCK_CMD,
+        FAL_NROM_TCP_SAR_BLOCK_CMD,
+        FAL_NROM_TCP_RST_SCAN_CMD,
+        FAL_NROM_TCP_SYN_WITH_DATA_CMD,
+        FAL_NROM_TCP_RST_WITH_DATA_CMD,
+        FAL_NROM_TCP_FA_BLOCK_CMD,
+        FAL_NROM_TCP_PA_BLOCK_CMD,
+        FAL_NROM_TCP_UA_BLOCK_CMD,
+        FAL_NROM_TCP_INVALID_CHKSUM_CMD,
+        FAL_NROM_TCP_INVALID_URGPTR_CMD,
+        FAL_NROM_TCP_INVALID_OPTIONS_CMD,
+        FAL_NROM_TCP_MIN_HDR_SIZE,
+
+        /* define UDP related normalization items */
+        FAL_NROM_UDP_BLAT_CMD,
+        FAL_NROM_UDP_INVALID_LEN_CMD,
+        FAL_NROM_UDP_INVALID_CHKSUM_CMD,
+
+        /* define ICMP related normalization items */
+        FAL_NROM_ICMP4_PING_PL_EXCEED_CMD,
+        FAL_NROM_ICMP6_PING_PL_EXCEED_CMD,
+        FAL_NROM_ICMP4_PING_FRAG_CMD,
+        FAL_NROM_ICMP6_PING_FRAG_CMD,
+        FAL_NROM_ICMP4_PING_MAX_PL_VALUE,
+        FAL_NROM_ICMP6_PING_MAX_PL_VALUE,
+    }
+    fal_norm_item_t;
+
+	typedef struct {
+		fal_fwd_cmd_t cmd; /* action for the exception */
+		a_bool_t deacclr_en; /* 0 for disable and 1 for disable */
+		a_bool_t l3route_only_en; /*host/network route 0: disable and 1: enable*/
+		a_bool_t l2fwd_only_en; /*l2 forward 0: disable and 1: enable*/
+		a_bool_t l3flow_en; /* 0 for disable and 1 for disable */
+		a_bool_t l2flow_en; /* 0 for disable and 1 for disable */
+		a_bool_t multicast_en; /* 0 for disable and 1 for disable */
+	} fal_l3_excep_ctrl_t;
+
+	typedef struct {
+		a_uint8_t small_ip4ttl; /* small ttl value checking */
+		a_uint8_t small_ip6hoplimit; /*small hoplimit value for check*/
+	} fal_l3_excep_parser_ctrl;
+
+#define TCP_FLAGS_MAX	8
+	typedef struct {
+		a_uint8_t tcp_flags[TCP_FLAGS_MAX]; /*flag for exception*/
+		a_uint8_t tcp_flags_mask[TCP_FLAGS_MAX]; /*flag mask*/
+	} fal_l4_excep_parser_ctrl;
+
+enum {
+	FUNC_SEC_L3_EXCEP_CTRL_SET = 0,
+	FUNC_SEC_L3_EXCEP_CTRL_GET,
+	FUNC_SEC_L3_EXCEP_PARSER_CTRL_SET,
+	FUNC_SEC_L3_EXCEP_PARSER_CTRL_GET,
+	FUNC_SEC_L4_EXCEP_PARSER_CTRL_SET,
+	FUNC_SEC_L4_EXCEP_PARSER_CTRL_GET,
+};
+
+    sw_error_t
+    fal_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value);
+
+    sw_error_t
+    fal_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value);
+
+    sw_error_t
+    fal_sec_l3_excep_ctrl_set(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl);
+
+    sw_error_t
+    fal_sec_l3_excep_ctrl_get(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl);
+
+    sw_error_t
+    fal_sec_l3_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl);
+
+    sw_error_t
+    fal_sec_l3_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl);
+
+    sw_error_t
+    fal_sec_l4_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl);
+
+    sw_error_t
+    fal_sec_l4_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl);
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_SEC_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/fal/fal_servcode.h b/qca-ssdk/include/fal/fal_servcode.h
new file mode 100755
index 0000000..cf8705b
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_servcode.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_gen FAL_SERVCODE
+ * @{
+ */
+#ifndef _FAL_SERVCODE_H_
+#define _FAL_SERVCODE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+#if defined(SW_API_LOCK) && (!defined(HSL_STANDALONG))
+#define FAL_SERVCODE_API_LOCK
+#define FAL_SERVCODE_API_UNLOCK
+#else
+#define FAL_SERVCODE_API_LOCK
+#define FAL_SERVCODE_API_UNLOCK
+#endif
+
+enum {
+	FLD_UPDATE_CAPWAP_EN = 0, /*only for IP197*/
+	FLD_UPDATE_DIRECTION, /*only for IP197*/
+	FLD_UPDATE_DEST_INFO,
+	FLD_UPDATE_SRC_INFO,
+	FLD_UPDATE_INT_PRI,
+	FLD_UPDATE_SERVICE_CODE,
+	FLD_UPDATE_HASH_FLOW_INDEX,
+	FLD_UPDATE_FAKE_L2_PROT_EN, /*only for IP197*/
+};
+
+enum {
+	IN_VLAN_TAG_FMT_CHECK_BYP = 0,
+	IN_VLAN_MEMBER_CHECK_BYP,
+	IN_VLAN_XLT_BYP,
+	MY_MAC_CHECK_BYP,
+	DIP_LOOKUP_BYP,
+	FLOW_LOOKUP_BYP = 5,
+	FLOW_ACTION_BYP,
+	ACL_BYP,
+	FAKE_MAC_HEADER_BYP,
+	SERVICE_CODE_BYP,
+	WRONG_PKT_FMT_L2_BYP = 10,
+	WRONG_PKT_FMT_L3_IPV4_BYP,
+	WRONG_PKT_FMT_L3_IPV6_BYP,
+	WRONG_PKT_FMT_L4_BYP,
+	FLOW_SERVICE_CODE_BYP,
+	ACL_SERVICE_CODE_BYP = 15,
+	FAKE_L2_PROTO_BYP,
+	PPPOE_TERMINATION_BYP,
+	DEFAULT_VLAN_BYP,
+	IN_VLAN_ASSIGN_FAIL_BYP = 24,
+	SOURCE_GUARD_BYP,
+	MRU_MTU_CHECK_BYP,
+	FLOW_SRC_CHECK_BYP,
+	FLOW_QOS_BYP,
+
+	EG_VLAN_MEMBER_CHECK_BYP = 32,
+	EG_VLAN_XLT_BYP,
+	EG_VLAN_TAG_FMT_CTRL_BYP,
+	FDB_LEARN_BYP = 35,
+	FDB_REFRESH_BYP,
+	L2_SOURCE_SEC_BYP,
+	MANAGEMENT_FWD_BYP,
+	BRIDGING_FWD_BYP,
+	IN_STP_FLTR_BYP = 40,
+	EG_STP_FLTR_BYP,
+	SOURCE_FLTR_BYP,
+	POLICER_BYP,
+	L2_PKT_EDIT_BYP,
+	L3_PKT_EDIT_BYP = 45,
+	ACL_POST_ROUTING_CHECK_BYP,
+	PORT_ISOLATION_BYP,
+	/* for cypress Qos bypass */
+	PRE_ACL_QOS_BYP,
+	POST_ACL_QOS_BYP,
+	DSCP_QOS_BYP,
+	PCP_QOS_BYP,
+	PREHEADER_QOS_BYP,
+
+	RX_VLAN_COUNTER_BYP = 64,
+	RX_COUNTER_BYP,
+	TX_VLAN_COUNTER_BYP,
+	TX_COUNTER_BYP,
+};
+
+typedef struct {
+	a_bool_t dest_port_valid; /* dest_port_id valid or not */
+	fal_port_t dest_port_id; /* destination physical port id:0-7 */
+	a_uint32_t  bypass_bitmap[3]; /* refer to enum IN_VLAN_TAG_FMT_CHECK_BYP... */
+	a_uint32_t  direction; /* if dest is vp, fill it in dest_info or src_info, 0:dest, 1:src */
+
+	a_uint32_t  field_update_bitmap; /* refer to enum FLD_UPDATE_CAPWAP_EN... */
+	a_uint32_t  next_service_code; /* next service code */
+	a_uint32_t  hw_services; /* HW_SERVICES to IP-197 */
+	a_uint32_t  offset_sel; /* Select the offset value to IP-197:0: l3_offset, 1:l4_offset */
+} fal_servcode_config_t;
+
+enum
+{
+	/*servcode*/
+	FUNC_SERVCODE_CONFIG_SET = 0,
+	FUNC_SERVCODE_CONFIG_GET,
+	FUNC_SERVCODE_LOOPCHECK_EN,
+	FUNC_SERVCODE_LOOPCHECK_STATUS_GET,
+};
+
+sw_error_t fal_servcode_config_set(a_uint32_t dev_id, a_uint32_t servcode_index, fal_servcode_config_t *entry);
+sw_error_t fal_servcode_config_get(a_uint32_t dev_id, a_uint32_t servcode_index, fal_servcode_config_t *entry);
+sw_error_t fal_servcode_loopcheck_en(a_uint32_t dev_id, a_bool_t enable);
+sw_error_t fal_servcode_loopcheck_status_get(a_uint32_t dev_id, a_bool_t *enable);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_SERVCODE_H_ */
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/fal/fal_sfp.h b/qca-ssdk/include/fal/fal_sfp.h
new file mode 100755
index 0000000..973245c
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_sfp.h
@@ -0,0 +1,578 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_sfp FAL_SFP
+ * @{
+ */
+#ifndef _FAL_SFP_H_
+#define _FAL_SFP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+typedef enum {
+	FAL_SFP_CC_BASE = 0,  /* Check code for Base ID Fields (addresses 0 to 62) */
+	FAL_SFP_CC_EXT,       /* Check code for the Extended ID Fields (addresses 64 to 94) */
+	FAL_SFP_CC_DMI,       /* Check code for Base Diagnostic Fields (addresses 0 to 94) */
+} fal_sfp_cc_type_t;
+
+typedef struct {
+	a_uint32_t addr;       /* Addr A0h or A2h */
+	a_uint32_t offset;     /* offset in eeprom */
+	a_uint32_t count;      /* data bytes */
+	a_uint8_t data[256];   /* data value */
+} fal_sfp_data_t;
+
+/* A0h offset: 0-2 bytes */
+typedef struct {
+	a_uint8_t identifier;      /* type of transceiver */
+	/*
+	 * 00h: Unknown or unspecified
+	 * 01h: GBIC
+	 * 02h: Module soldered to motherboard (ex: SFF)
+	 * 03h: SFP or SFP “Plus”
+	 * 04h: Reserved for “300 pin XBI” devices*
+	 * 05h: Reserved for “Xenpak” devices*
+	 * 06h: Reserved for “XFP” devices*
+	 * 07h: Reserved for “XFF” devices*
+	 * 08h: Reserved for “XFP-E” devices*
+	 * 09h: Reserved for “XPak” devices*
+	 * 0Ah: Reserved for “X2” devices*
+	 * 0Bh: Reserved for “DWDM-SFP” devices*
+	 * 0Ch: Reserved for “QSFP” devices*
+	 * 0D-7Fh: Reserved, unallocated
+	 * 80-FFh: Vendor specific
+	 */
+	a_uint8_t ext_indentifier; /* Extended identifier of type of transceiver */
+	/*
+	 * 00h: GBIC definition is not specified or not compliant with a defined MOD_DEF.
+	 * 01h: GBIC is compliant with MOD_DEF 1
+	 * 02h: GBIC is compliant with MOD_DEF 2
+	 * 03h: GBIC is compliant with MOD_DEF 3
+	 * 04h: GBIC/SFP function is defined by two-wire interface ID only
+	 * 05h: GBIC is compliant with MOD_DEF 5
+	 * 06h: GBIC is compliant with MOD_DEF 6
+	 * 07h: GBIC is compliant with MOD_DEF 7
+	 * 08-FFh: Unallocated
+	 */
+	a_uint8_t connector_type;  /* Code for connector type */
+	/*
+	 * 00h: Unknown or unspecified
+	 * 01h: SC
+	 * 02h: Fibre Channel Style 1 copper connector
+	 * 03h: Fibre Channel Style 2 copper connector
+	 * 04h: BNC/TNC
+	 * 05h: Fibre Channel coaxial headers
+	 * 06h: FiberJack
+	 * 07h: LC
+	 * 08h: MT-RJ
+	 * 09h: MU
+	 * 0AH: SG
+	 * 0Bh: Optical pigtail
+	 * 0Ch: MPO Parallel Optic
+	 * 0D-1Fh: Unallocated
+	 * 20h: HSSDC II
+	 * 21h: Copper pigtail
+	 * 22h: RJ45
+	 * 23h-7Fh: Unallocated
+	 * 80h-FFh: Vendor specific
+	 */
+} fal_sfp_dev_type_t;
+
+/* A0h offset: 3-10 bytes */
+typedef struct {
+	a_uint8_t eth_10g_ccode;           /* 10G Ethernet Compliance Codes */
+	/*
+	 * offset 3 bit7: 10G Base-ER
+	 * offset 3 bit6: 10G Base-LRM
+	 * offset 3 bit5: 10G Base-LR
+	 * offset 3 bit4: 10G Base-SR
+	 */
+	a_uint8_t infiniband_ccode;        /* Infiniband Compliance Codes */
+	/*
+	 * offset 3 bit3: 1X SX
+	 * offset 3 bit2: 1X LX
+	 * offset 3 bit1: 1X Copper Active
+	 * offset 3 bit0: 1X Copper Passive
+	 */
+	a_uint8_t escon_ccode;             /* ESCON Compliance Codes */
+	/*
+	 * offset 4 bit7: ESCON MMF, 1310nm LED
+	 * offset 4 bit6: ESCON SMF, 1310nm Laser
+	 */
+	a_uint16_t sonet_ccode;            /* SONET Compliance Codes */
+	/*
+	 * offset 4 bit5: OC-192, short reach
+	 * offset 4 bit4: SONET reach specifier bit 1
+	 * offset 4 bit3: SONET reach specifier bit 2
+	 * offset 4 bit2: OC-48, long reach
+	 * offset 4 bit1: OC-48, intermediate reach
+	 * offset 4 bit0: OC-48, short reach
+	 * offset 5 bit7: Unallocated
+	 * offset 5 bit6: OC-12, single mode, long reach
+	 * offset 5 bit5: OC-12, single mode, inter. reach
+	 * offset 5 bit4: OC-12, short reach
+	 * offset 5 bit3: Unallocated
+	 * offset 5 bit2: OC-3, single mode, long reach
+	 * offset 5 bit1: OC-3, single mode, inter. reach
+	 * offset 5 bit0: OC-3, short reach
+	 */
+	a_uint8_t eth_ccode;               /* Ethernet Compliance Codes */
+	/*
+	 * offset 6 bit7: BASE-PX
+	 * offset 6 bit6: BASE-BX10
+	 * offset 6 bit5: 100BASE-FX
+	 * offset 6 bit4: 100BASE-LX/LX10
+	 * offset 6 bit3: 1000BASE-T
+	 * offset 6 bit2: 1000BASE-CX
+	 * offset 6 bit1: 1000BASE-LX
+	 * offset 6 bit0: 1000BASE-SX
+	 */
+	a_uint8_t fibre_chan_link_length;  /* Fibre Channel Link Length */
+	/*
+	 * offset 7 bit7: very long distance (V)
+	 * offset 7 bit6: short distance (S)
+	 * offset 7 bit5: intermediate distance (I)
+	 * offset 7 bit4: long distance (L)
+	 * offset 7 bit3: medium distance (M)
+	 */
+	a_uint8_t fibre_chan_tech;         /* Fibre Channel Technology */
+	/*
+	 * offset 7 bit2: Shortwave laser, linear Rx (SA)
+	 * offset 7 bit1: Longwave laser (LC)
+	 * offset 7 bit0: Electrical inter-enclosure (EL)
+	 * offset 8 bit7: Electrical intra-enclosure (EL)
+	 * offset 8 bit6: Shortwave laser w/o OFC (SN)
+	 * offset 8 bit5: Shortwave laser with OFC4 (SL)
+	 * offset 8 bit4: Longwave laser (LL)
+	 */
+	a_uint8_t sfp_cable_tech;          /* SFP+ Cable Technology */
+	/*
+	 * offset 8 bit3: Active Cable
+	 * offset 8 bit2: passive Cable
+	 * offset 8 bit1: unallocated
+	 * offset 8 bit0: unallocated
+	 */
+	a_uint8_t fibre_chan_trans_md;     /* Fibre Channel Transmission Media */
+	/*
+	 * offset 9 bit7: twin axial pair(TW)
+	 * offset 9 bit6: twisted pair(TP)
+	 * offset 9 bit5: miniature coax(MI)
+	 * offset 9 bit4: video coax(TV)
+	 * offset 9 bit3: multimode, 62.5um(M6)
+	 * offset 9 bit2: multimode, 50um(M5,M5E)
+	 * offset 9 bit1: unallocated
+	 * offset 9 bit0: sigle mode(SM)
+	 */
+	a_uint8_t fibre_chan_speed;        /* Fibre Channel Speed */
+	/*
+	 * offset 10 bit7: 1200 MBytes/sec
+	 * offset 10 bit6: 800 MBytes/sec
+	 * offset 10 bit5: 1600 MBytes/sec
+	 * offset 10 bit4: 400 MBytes/sec
+	 * offset 10 bit3: unallocated
+	 * offset 10 bit2: 200 MBytes/sec
+	 * offset 10 bit1: unallocated
+	 * offset 10 bit0: 100 MBytes/sec
+	 */
+} fal_sfp_transc_code_t;
+
+/* A0h offset: 11-13 bytes */
+typedef struct {
+	a_uint8_t encode;              /* the serial encoding mechanism */
+	/*
+	 * 0h: Unspecified
+	 * 1h: 8B/10B
+	 * 2h: 4B/5B
+	 * 3h: NRZ
+	 * 4h: Manchester
+	 * 5h: SONET Scrambled
+	 * 6h： 64B/66B
+	 * 7h-FFh: Unallocated
+	 */
+	a_uint8_t nominal_bit_rate;    /* the nomial bit rate */
+	/*
+	 * these bits necessary to encode and delimit the signal
+	 * as well as those bits carrying data information,
+	 * the actual transfer rate will depend on the encoding
+	 * of the data definded by the encode value above.
+	 */
+	a_uint8_t rate_id;             /* the selected rate */
+	/*
+	 * 0h: Unspecified
+	 * 1h: Defined for SFF-8079 (4/2/1G Rate_Select & AS0/AS1)
+	 * 2h: Defined for SFF-8431 (8/4/2G Rx Rate_Select only)
+	 * 3h: Unspecified *
+	 * 4h: Defined for SFF-8431 (8/4/2G Tx Rate_Select only)
+	 * 5h: Unspecified *
+	 * 6h: Defined for SFF-8431 (8/4/2G Independent Rx & Tx Rate_select)
+	 * 7h-FFh: Unallocated
+	 */
+} fal_sfp_rate_encode_t;
+
+
+/* A0h offset: 14-19 bytes */
+typedef struct {
+	a_uint8_t single_mode_length_km;     /* the link length of km in single mode */
+	a_uint8_t single_mode_length_100m;   /* the link length of 100m in single mode */
+	a_uint8_t om2_mode_length_10m;       /* the link length of 10m micron multimode OM2 */
+	a_uint8_t om1_mode_length_10m;       /* the link length of 10m micron multimode OM1 */
+	a_uint8_t copper_mode_length_1m;     /* the link length of 1m copper mode */
+	a_uint8_t om3_mode_length_1m;        /* the link length of 10m micron multimode OM3 */
+} fal_sfp_link_length_t;
+
+/* A0h offset: 20-35 bytes vendor name*/
+/* A0h offset: 36th byte transceiver code */
+/* A0h offset: 37-39 bytes vendor oui */
+/* A0h offset: 40-55 bytes vendor pn */
+/* A0h offset: 56-59 bytes vendor rev */
+/* A0h offset: 68-83 bytes for the vendor serial number */
+/* A0h offset: 84-91 bytes for the vendor's date code in ascii charaters */
+typedef struct {
+	a_uint8_t vendor_name[16];     /* vendor name */
+	a_uint8_t vendor_oui[3];       /* vendor OUI */
+	a_uint8_t vendor_pn[16];       /* vendor PN */
+	a_uint8_t vendor_rev[4];       /* vendor Rev */
+	a_uint8_t vendor_sn[16];       /* the vendor serial number */
+	a_uint8_t vendor_date_code[8]; /* the vendor's date code in ascii charaters */
+} fal_sfp_vendor_info_t;
+
+/* A0h offset: 60-61 bytes */
+typedef struct {
+	a_uint16_t laser_wavelength;   /* the output laser wave length in nm */
+} fal_sfp_laser_wavelength_t;
+
+/* A0h offset: 62 byte unallocated */
+/* A0h offset: 63 byte for checksum  base */
+
+/* A0h offset: 64-65 bytes */
+typedef struct {
+	/* the implemented options */
+	a_uint8_t linear_recv_output:1;
+	a_uint8_t pwr_level_declar:1;
+	a_uint8_t cool_transc_declar:1;
+	a_uint8_t reversed_1:5;
+
+	a_uint8_t reversed_2:1;
+	a_uint8_t loss_signal:1;
+	a_uint8_t loss_invert_signal:1;
+	a_uint8_t tx_fault_signal:1;
+	a_uint8_t tx_disable:1;
+	a_uint8_t rate_sel:1;
+	a_uint8_t reversed_3:2;
+	/*
+	 * offset 64 bit7-3: Unallocated
+	 * offset 64 bit2: Cooled Transceiver Declaration (see SFF-8431)
+	 * offset 64 bit1: Power Level Declaration (see SFF-8431)
+	 * offset 64 bit0: Linear Receiver Output Implemented (see SFF-8431)
+	 * offset 65 bit7-6: Unallocated
+	 * offset 65 bit5: RATE_SELECT functionality is implemented
+	 * offset 65 bit4: TX_DISABLE is implemented and disables the high speed serial output
+	 * offset 65 bit3: TX_FAULT signal implemented. (See SFP MSA)
+	 * offset 65 bit2: Loss of Signal implemented, signal inverted from standard definition
+	 * offset 65 bit1: Loss of Signal implemented, signal as defined in SFP MSA
+	 * offset 65 bit0: Unallocated
+	 */
+} fal_sfp_option_t;
+
+/* A0h offset: 66-67 bytes */
+typedef struct {
+	a_uint8_t upper_rate_limit;    /* the upper rate limit */
+	a_uint8_t lower_rate_limit;    /* the lower rate limit */
+} fal_sfp_rate_t;
+
+/* A0h offset: 68-83 bytes for the vendor serial number */
+/* A0h offset: 84-91 bytes for the vendor's date code in ascii charaters */
+
+/* A0h offset: 92-94 bytes */
+typedef struct {
+	/* digital diagnostic monitoring type */
+	a_uint8_t reserved_type:2;
+	a_uint8_t addr_mode:1;
+	a_uint8_t rec_pwr_type:1;
+	a_uint8_t external_cal:1;
+	a_uint8_t internal_cal:1;
+	a_uint8_t diag_mon_flag:1;
+	a_uint8_t legacy_type:1;
+	/*
+	 * bit 7: Reserved for legacy diagnostic
+	 * bit 6: Digital diagnostic monitoring implemented
+	 * bit 5: Internally calibrated
+	 * bit 4: Externally calibrated
+	 * bit 3: Received power measurement type
+	 * 0 = OMA, 1 = average power
+	 * bit 2: Address change required “addressing modes”
+	 * bit1~0: unallocated
+	 */
+	/* optional digital diagnostic features implemented */
+	a_uint8_t reserved_op:1;
+	a_uint8_t soft_rate_sel_op:1;
+	a_uint8_t app_sel_op:1;
+	a_uint8_t soft_rate_ctrl_op:1;
+	a_uint8_t rx_los_op:1;
+	a_uint8_t tx_fault_op:1;
+	a_uint8_t tx_disable_ctrl_op:1;
+	a_uint8_t alarm_warning_flag_op:1;
+	/*
+	 * bit 7: Optional Alarm/warning flags implemented for all monitored quantities
+	 * bit 6: Optional soft TX_DISABLE control and monitoring implemented
+	 * bit 5: Optional soft TX_FAULT monitoring implemented
+	 * bit 4: Optional soft RX_LOS monitoring implemented
+	 * bit 3: Optional soft RATE_SELECT control and monitoring implemented
+	 * bit 2: Optional Application Select control implemented per SFF-8079
+	 * bit 1: Optional soft Rate Select control implemented per SFF-8431
+	 * bit 0: Unallocated
+	 */
+	a_uint8_t compliance_feature; /* the implemented features */
+	/*
+	 * 00h: Digital diagnostic functionality not included or undefined
+	 * 01h: Includes functionality described in Rev 9.3 of SFF-8472.
+	 * 02h: Includes functionality described in Rev 9.5 of SFF-8472.
+	 * 03h: Includes functionality described in Rev 10.2 of SFF-8472.
+	 * 04h: Includes functionality described in Rev 10.4 of SFF-8472.
+	 * 05h~FFh: Unallocated
+	 */
+} fal_sfp_enhanced_cfg_t;
+
+/* A0h offset: 95th byte for checksum extended id field */
+
+/* A0h offset: 96-127 bytes Vendor Specific */
+/* A0h offset: 128-255 bytes Reserved */
+
+/* A2h offset: 0-39 bytes */
+typedef struct {
+	a_uint16_t temp_high_alarm;      /* the temperature alarm high value */
+	a_uint16_t temp_low_alarm;       /* the temperature alarm low value */
+	a_uint16_t temp_high_warning;    /* the temperature warning high value */
+	a_uint16_t temp_low_warning;     /* the temperature warning low value */
+	a_uint16_t vol_high_alarm;       /* the voltage alarm high value */
+	a_uint16_t vol_low_alarm;        /* the voltage alarm low value */
+	a_uint16_t vol_high_warning;     /* the voltage warning high value */
+	a_uint16_t vol_low_warning;      /* the voltage warning low value */
+	a_uint16_t bias_high_alarm;      /* the bias alarm high value */
+	a_uint16_t bias_low_alarm;       /* the bias alarm low value */
+	a_uint16_t bias_high_warning;    /* the bias warning high value */
+	a_uint16_t bias_low_warning;     /* the bias warning low value */
+	a_uint16_t tx_power_high_alarm;  /* the tx power alarm high value */
+	a_uint16_t tx_power_low_alarm;   /* the tx power alarm low value */
+	a_uint16_t tx_power_high_warning;/* the tx power warning high value */
+	a_uint16_t tx_power_low_warning; /* the tx power warning low value */
+	a_uint16_t rx_power_high_alarm;  /* the rx power alarm high value */
+	a_uint16_t rx_power_low_alarm;   /* the rx power alarm low value */
+	a_uint16_t rx_power_high_warning;/* the rx power warning high value */
+	a_uint16_t rx_power_low_warning; /* the rx power warning low value */
+} fal_sfp_internal_threshold_t;
+
+/* A2h offset: 40-55 bytes Reserved for future monitored quantities */
+
+/* A2h offset: 56-91 bytes */
+typedef struct {
+	a_uint32_t rx_power4;      /* Single precision floating point Rx optical power4 */
+	a_uint32_t rx_power3;      /* Single precision floating point Rx optical power3 */
+	a_uint32_t rx_power2;      /* Single precision floating point Rx optical power2 */
+	a_uint32_t rx_power1;      /* Single precision floating point Rx optical power1 */
+	a_uint32_t rx_power0;      /* Single precision floating point Rx optical power0 */
+	a_uint16_t tx_bias_slope;  /* Fixed decimal for laser bias current */
+	a_uint16_t tx_bias_offset; /* Fixed decimal for laser bias current */
+	a_uint16_t tx_power_slope; /* Fixed decimal for transmitter coupled output power */
+	a_uint16_t tx_power_offset;/* Fixed decimal for transmitter coupled output power */
+	a_uint16_t temp_slope;     /* Fixed decimal for internal module temperature	*/
+	a_uint16_t temp_offset;    /* Fixed decimal for internal module temperature */
+	a_uint16_t vol_slope;      /* Fixed decimal for internal module supply voltage */
+	a_uint16_t vol_offset;     /* Fixed decimal for internal module supply voltage */
+} fal_sfp_cal_const_t;
+
+/* A2h offset: 92-94 bytes Unallocated */
+
+/* A2h offset: 95th byte checsum for Base Diagnostic Fields*/
+
+/* A2h offset: 96-105 bytes */
+typedef struct {
+	a_uint16_t cur_temp;        /* Internally measured module temperature */
+	a_uint16_t cur_vol;         /* Internally measured supply voltage in transceiver */
+	a_uint16_t tx_cur_bias;     /* Internally measured TX Bias Current */
+	a_uint16_t tx_cur_power;    /* Measured TX output power */
+	a_uint16_t rx_cur_power;    /* Measured RX input power */
+} fal_sfp_realtime_diag_t;
+
+/* A2h offset: 106-109 bytes Unallocated */
+
+/* A2h offset: 110th byte for base control/status */
+/* A2h offset: 111th byte Reserved */
+/* A2h offset: 118th byte for extend control/status */
+typedef struct {
+	/* Optional Status/Control Bits */
+	a_uint8_t data_ready:1;
+	a_uint8_t rx_los:1;
+	a_uint8_t tx_fault:1;
+	a_uint8_t soft_rate_sel:1;
+	a_uint8_t rate_sel:1;
+	a_uint8_t rs_state:1;
+	a_uint8_t soft_tx_disable:1;
+	a_uint8_t tx_disable:1;
+
+	/*
+	 * bit7: tx disable state
+	 * bit6: soft tx disable select
+	 * bit5: rs state
+	 * bit4: rate_select state
+	 * bit3: soft rate_select select
+	 * bit2: tx fault state
+	 * bit1: rx_los state
+	 * bit0: data_ready_bar state
+	 */
+
+	/* Extended Control/Status Bits */
+	a_uint8_t pwr_level_sel:1;
+	a_uint8_t pwr_level_op_state:1;
+	a_uint8_t reserved_1:1;
+	a_uint8_t soft_rs_sel:1;
+	a_uint8_t reserved_2:4;
+	/*
+	 * bit7-4: Reserved
+	 * bit3:   soft RS select
+	 * bit2:   Reserved
+	 * bit1:   Power level operation state
+	 * bit0:   Power level select
+	 */
+} fal_sfp_ctrl_status_t;
+
+/* A2h offset: 112-113 byte Alarm flag bits */
+/* A2h offset: 114-115 byte Alarm Reserved */
+/* A2h offset: 116-117 byte Warning flag bits */
+typedef struct {
+	/* internal diagnose exceeds high alarm level */
+	a_uint8_t tx_pwr_low_alarm:1;
+	a_uint8_t tx_pwr_high_alarm:1;
+	a_uint8_t tx_bias_low_alarm:1;
+	a_uint8_t tx_bias_high_alarm:1;
+	a_uint8_t vcc_low_alarm:1;
+	a_uint8_t vcc_high_alarm:1;
+	a_uint8_t tmp_low_alarm:1;
+	a_uint8_t tmp_high_alarm:1;
+	a_uint8_t reserved_alarm:6;
+	a_uint8_t rx_pwr_low_alarm:1;
+	a_uint8_t rx_pwr_high_alarm:1;
+
+	/* internal diagnose exceeds high warn level */
+	a_uint8_t tx_pwr_low_warning:1;
+	a_uint8_t tx_pwr_high_warning:1;
+	a_uint8_t tx_bias_low_warning:1;
+	a_uint8_t tx_bias_high_warning:1;
+	a_uint8_t vcc_low_warning:1;
+	a_uint8_t vcc_high_warning:1;
+	a_uint8_t tmp_low_warning:1;
+	a_uint8_t tmp_high_warning:1;
+	a_uint8_t reserved_warning:6;
+	a_uint8_t rx_pwr_low_warning:1;
+	a_uint8_t rx_pwr_high_warning:1;
+	/*
+	 * bit 15: internal temperature exceeds high alarm/warning level
+	 * bit 14: internal temperature is below low alarm/warning level
+	 * bit 13: internal supply voltage exceeds high alarm/warning level
+	 * bit 12: internal supply voltage is below low alarm/warning level
+	 * bit 11: TX Bias current exceeds high alarm/warning level
+	 * bit 10: TX Bias current is below low alarm/warning level
+	 * bit 09: TX output power exceeds high alarm/warning level
+	 * bit 08: TX output power is below low alarm/warning level
+	 * bit 07: Received Power exceeds high alarm/warning level
+	 * bit 06: Received Power is below low alarm/warning level
+	 * bit 05~00: reserved alarm/warning
+	 */
+} fal_sfp_alarm_warn_flag_t;
+
+/* A2h offset: 119th byte Reserved */
+/* A2h offset: 120-127 byte Vendor Specific locations */
+/* A2h offset: 128-247 byte User EEPROM */
+/* A2h offset: 248-255 byte Vendor Specific locations */
+
+sw_error_t
+fal_sfp_eeprom_data_get(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry);
+
+sw_error_t
+fal_sfp_eeprom_data_set(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry);
+
+sw_error_t
+fal_sfp_device_type_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_dev_type_t *sfp_id);
+
+sw_error_t
+fal_sfp_transceiver_code_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_transc_code_t *transc_code);
+
+sw_error_t
+fal_sfp_rate_encode_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_rate_encode_t *encode);
+
+sw_error_t
+fal_sfp_link_length_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_link_length_t *link_len);
+
+sw_error_t
+fal_sfp_vendor_info_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_vendor_info_t *vender_info);
+
+sw_error_t
+fal_sfp_laser_wavelength_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_laser_wavelength_t *laser_wavelen);
+
+sw_error_t
+fal_sfp_option_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_option_t *option);
+
+sw_error_t
+fal_sfp_ctrl_rate_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_rate_t *rate_limit);
+
+sw_error_t
+fal_sfp_enhanced_cfg_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_enhanced_cfg_t *enhanced_feature);
+
+sw_error_t
+fal_sfp_diag_internal_threshold_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_internal_threshold_t *threshold);
+
+sw_error_t
+fal_sfp_diag_extenal_calibration_const_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_cal_const_t *cal_const);
+
+sw_error_t
+fal_sfp_diag_realtime_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_realtime_diag_t *real_diag);
+
+sw_error_t
+fal_sfp_diag_ctrl_status_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_ctrl_status_t *ctrl_status);
+
+sw_error_t
+fal_sfp_diag_alarm_warning_flag_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_alarm_warn_flag_t *alarm_warn_flag);
+
+sw_error_t
+fal_sfp_checkcode_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_cc_type_t cc_type, a_uint8_t *ccode);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_SFP_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_shaper.h b/qca-ssdk/include/fal/fal_shaper.h
new file mode 100755
index 0000000..e266eeb
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_shaper.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_shaper FAL_SHAPER
+ * @{
+ */
+#ifndef _FAL_SHAPER_H_
+#define _FAL_SHAPER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+typedef enum
+{
+	FAL_IPG_PREAMBLE_FRAME_CRC = 0,  /* IPG + Preamble + Frame + CRC */
+	FAL_FRAME_CRC,  /* Frame + CRC */
+	FAL_L3_EXCLUDE_CRC  /* after Ethernet type excude CRC*/
+} fal_shaper_frame_mode_t;
+
+typedef struct
+{
+	a_bool_t  couple_en; /* two buckets coupled enable or disable*/
+	a_uint32_t meter_unit; /* 0 byte based, 1 frame based */
+	a_bool_t	c_shaper_en; /* egress shaer C bucket enable or disable */
+	a_uint32_t cbs; /* committed burst size */
+	a_uint32_t cir; /* committed information rate */
+	a_bool_t	e_shaper_en; /* egress shaper E bucket enable or disable */
+	a_uint32_t ebs; /* excess burst size */
+	a_uint32_t eir; /* excess information rate */
+	fal_shaper_frame_mode_t shaper_frame_mode; /* shaper frame mode */
+} fal_shaper_config_t;
+
+typedef struct
+{
+     a_bool_t      c_token_number_negative_en; /* C token is negative or not */
+     a_uint32_t    c_token_number; /* C token value */
+     a_bool_t      e_token_number_negative_en; /* E token is negative or not */
+     a_uint32_t    e_token_number; /* E token value */
+} fal_shaper_token_number_t;
+
+enum
+{
+	FUNC_ADPT_FLOW_SHAPER_SET = 0,
+	FUNC_ADPT_QUEUE_SHAPER_GET,
+	FUNC_ADPT_QUEUE_SHAPER_TOKEN_NUMBER_SET,
+	FUNC_ADPT_PORT_SHAPER_GET,
+	FUNC_ADPT_FLOW_SHAPER_TIME_SLOT_GET,
+	FUNC_ADPT_PORT_SHAPER_TIME_SLOT_GET,
+	FUNC_ADPT_FLOW_SHAPER_TIME_SLOT_SET,
+	FUNC_ADPT_PORT_SHAPER_TOKEN_NUMBER_SET,
+	FUNC_ADPT_QUEUE_SHAPER_TOKEN_NUMBER_GET,
+	FUNC_ADPT_QUEUE_SHAPER_TIME_SLOT_GET,
+	FUNC_ADPT_PORT_SHAPER_TOKEN_NUMBER_GET,
+	FUNC_ADPT_FLOW_SHAPER_TOKEN_NUMBER_SET,
+	FUNC_ADPT_FLOW_SHAPER_TOKEN_NUMBER_GET,
+	FUNC_ADPT_PORT_SHAPER_SET,
+	FUNC_ADPT_PORT_SHAPER_TIME_SLOT_SET,
+	FUNC_ADPT_FLOW_SHAPER_GET,
+	FUNC_ADPT_QUEUE_SHAPER_SET,
+	FUNC_ADPT_QUEUE_SHAPER_TIME_SLOT_SET,
+	FUNC_ADPT_SHAPER_IPG_PREAMBLE_LENGTH_SET,
+	FUNC_ADPT_SHAPER_IPG_PREAMBLE_LENGTH_GET,
+};
+
+sw_error_t
+fal_queue_shaper_token_number_set(a_uint32_t dev_id,a_uint32_t queue_id,
+		fal_shaper_token_number_t *token_number);
+
+sw_error_t
+fal_flow_shaper_token_number_set(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_token_number_t *token_number);
+
+sw_error_t
+fal_port_shaper_token_number_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_token_number_t *token_number);
+
+sw_error_t
+fal_port_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot);
+
+sw_error_t
+fal_queue_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot);
+
+sw_error_t
+fal_flow_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot);
+
+sw_error_t
+fal_shaper_ipg_preamble_length_set(a_uint32_t dev_id, a_uint32_t ipg_pre_length);
+
+sw_error_t
+fal_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_config_t * shaper);
+
+sw_error_t
+fal_queue_shaper_set(a_uint32_t dev_id,a_uint32_t queue_id,
+		fal_shaper_config_t * shaper);
+
+sw_error_t
+fal_queue_shaper_get(a_uint32_t dev_id, a_uint32_t queue_id,
+		fal_shaper_config_t * shaper);
+
+sw_error_t
+fal_flow_shaper_set(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_config_t * shaper);
+
+#ifndef IN_SHAPER_MINI
+sw_error_t
+fal_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_config_t * shaper);
+
+sw_error_t
+fal_flow_shaper_get(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_config_t * shaper);
+
+sw_error_t
+fal_queue_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t queue_id,
+		fal_shaper_token_number_t *token_number);
+
+sw_error_t
+fal_flow_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_token_number_t *token_number);
+
+sw_error_t
+fal_port_shaper_token_number_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_token_number_t *token_number);
+
+sw_error_t
+fal_port_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot);
+
+sw_error_t
+fal_queue_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot);
+
+sw_error_t
+fal_flow_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot);
+
+sw_error_t
+fal_shaper_ipg_preamble_length_get(a_uint32_t dev_id, a_uint32_t *ipg_pre_length);
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_SHAPER_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_stp.h b/qca-ssdk/include/fal/fal_stp.h
new file mode 100755
index 0000000..9d87a9b
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_stp.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_stp FAL_STP
+ * @{
+ */
+#ifndef _FAL_STP_H_
+#define _FAL_STP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+#define FAL_SINGLE_STP_ID 0
+
+    /**
+    @brief This enum defines port state for spanning tree.
+    */
+    typedef enum {
+        FAL_STP_DISABLED = 0,   /**<   disable state*/
+        FAL_STP_BLOCKING,        /**<   blocking state*/
+        FAL_STP_LISTENING,      /**<   listening state*/
+        FAL_STP_LEARNING,       /**<    learning state*/
+        FAL_STP_FORWARDING,     /**<   forwarding state*/
+        FAL_STP_STATE_BUTT
+    }
+    fal_stp_state_t;
+
+/*
+ * These two #define lines are used to keep them for the
+ * compatibility of previous project.
+ */
+#define FAL_STP_BLOKING FAL_STP_BLOCKING
+#define FAL_STP_FARWARDING FAL_STP_FORWARDING
+
+enum {
+	FUNC_STP_PORT_STATE_SET = 0,
+	FUNC_STP_PORT_STATE_GET,
+};
+
+    sw_error_t
+    fal_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                           fal_port_t port_id, fal_stp_state_t state);
+
+
+
+    sw_error_t
+    fal_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                           fal_port_t port_id, fal_stp_state_t * state);
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_STP_H_ */
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_trunk.h b/qca-ssdk/include/fal/fal_trunk.h
new file mode 100644
index 0000000..d252961
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_trunk.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2012, 2016-2018, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_trunk FAL_TRUNK
+ * @{
+ */
+#ifndef _FAL_TRUNK_H_
+#define _FAL_TRUNK_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+
+#define FAL_TRUNK_HASH_KEY_DA              0x1
+#define FAL_TRUNK_HASH_KEY_SA              0x2
+#define FAL_TRUNK_HASH_KEY_DIP             0x4
+#define FAL_TRUNK_HASH_KEY_SIP             0x8
+#define FAL_TRUNK_HASH_KEY_SRC_PORT        0x10
+#define FAL_TRUNK_HASH_KEY_L4_SRC_PORT     0x20
+#define FAL_TRUNK_HASH_KEY_L4_DST_PORT     0x40
+#define FAL_TRUNK_HASH_KEY_UDF0            0x80
+#define FAL_TRUNK_HASH_KEY_UDF1            0x100
+#define FAL_TRUNK_HASH_KEY_UDF2            0x200
+#define FAL_TRUNK_HASH_KEY_UDF3            0x400
+#define FAL_TRUNK_GROUP_MAX_MEMEBER        8
+
+enum {
+	FUNC_TRUNK_GROUP_SET = 0,
+	FUNC_TRUNK_GROUP_GET,
+	FUNC_TRUNK_HASH_MODE_SET,
+	FUNC_TRUNK_HASH_MODE_GET,
+	FUNC_TRUNK_FAILOVER_ENABLE,
+	FUNC_TRUNK_FAILOVER_STATUS_GET,
+};
+
+sw_error_t
+fal_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+			a_bool_t enable, fal_pbmp_t member);
+sw_error_t
+fal_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+			a_bool_t * enable, fal_pbmp_t * member);
+sw_error_t
+fal_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+sw_error_t
+fal_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+sw_error_t
+fal_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+sw_error_t
+fal_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+sw_error_t
+fal_trunk_failover_enable(a_uint32_t dev_id, a_bool_t failover);
+
+sw_error_t
+fal_trunk_failover_status_get(a_uint32_t dev_id, a_bool_t * failover);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_TRUNK_H_ */
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_type.h b/qca-ssdk/include/fal/fal_type.h
new file mode 100755
index 0000000..0f680a4
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_type.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_type FAL_TYPE
+ * @{
+ */
+#ifndef _FAL_TYPE_H_
+#define _FAL_TYPE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+    typedef a_uint32_t fal_port_t;
+
+/*fal_port_t definition,
+	bit31-bit24: port_type, 0-physical port, 1-trunk port, 2-virtual port
+	bit23-bit0: physical port id or trunk id or virtual port id*/
+#define FAL_PORT_TYPE_PPORT 0
+#define FAL_PORT_TYPE_TRUNK 1
+#define FAL_PORT_TYPE_VPORT 2
+
+#define FAL_PORT_ID_TYPE(port_id) (((port_id)>>24)&0xff)
+#define FAL_PORT_ID_VALUE(port_id) ((port_id)&0xffffff)
+#define FAL_PORT_ID(type, value) (((type)<<24)|(value))
+
+#define FAL_IS_PPORT(port_id) (((FAL_PORT_ID_TYPE(port_id))==FAL_PORT_TYPE_PPORT)?1:0)
+#define FAL_IS_TRUNK(port_id) (((FAL_PORT_ID_TYPE(port_id))==FAL_PORT_TYPE_TRUNK)?1:0)
+#define FAL_IS_VPORT(port_id) (((FAL_PORT_ID_TYPE(port_id))==FAL_PORT_TYPE_VPORT)?1:0)
+
+
+#if (SW_MAX_NR_PORT <= 32)
+    typedef a_uint32_t fal_pbmp_t;
+#else
+    typedef a_uint64_t fal_pbmp_t;
+#endif
+
+    typedef struct
+    {
+        a_uint8_t uc[6];
+    } fal_mac_addr_t;
+
+    typedef a_uint32_t fal_ip4_addr_t;
+
+    typedef struct
+    {
+        a_uint32_t ul[4];
+    } fal_ip6_addr_t;
+
+    /**
+    @brief This enum defines several forwarding command type.
+    * Field description:
+        FAL_MAC_FRWRD      - packets are normally forwarded
+        FAL_MAC_DROP       - packets are dropped
+        FAL_MAC_CPY_TO_CPU - packets are copyed to cpu
+        FAL_MAC_RDT_TO_CPU - packets are redirected to cpu
+    */
+    typedef enum
+    {
+        FAL_MAC_FRWRD = 0,      /**<   packets are normally forwarded */
+        FAL_MAC_DROP,           /**<   packets are dropped */
+        FAL_MAC_CPY_TO_CPU,     /**<   packets are copyed to cpu */
+        FAL_MAC_RDT_TO_CPU      /**<   packets are redirected to cpu */
+    } fal_fwd_cmd_t;
+
+    typedef enum
+    {
+        FAL_BYTE_BASED = 0,
+        FAL_FRAME_BASED,
+        FAL_RATE_MODE_BUTT
+    } fal_traffic_unit_t;
+
+    typedef a_uint32_t fal_queue_t;
+
+#define FAL_SVL_FID   0xffff
+
+
+    /**
+    @brief This enum defines packets transmitted out vlan tagged mode.
+    */
+    typedef enum
+    {
+        FAL_EG_UNMODIFIED = 0,  /**<  egress transmit packets unmodified */
+        FAL_EG_UNTAGGED,        /**<   egress transmit packets without vlan tag*/
+        FAL_EG_TAGGED,          /**<  egress transmit packets with vlan tag     */
+        FAL_EG_HYBRID,          /**<  egress transmit packets in hybrid tag mode     */
+        FAL_EG_UNTOUCHED,
+        FAL_EG_MODE_BUTT
+    } fal_pt_1q_egmode_t;
+
+#define FAL_NEXT_ENTRY_FIRST_ID 0xffffffff
+
+	typedef struct{
+		a_uint32_t reg_count;
+		a_uint32_t reg_base;
+		a_uint32_t reg_end;
+		a_uint32_t reg_value[256];
+		a_int8_t   reg_name[32];
+	}fal_reg_dump_t;
+
+	typedef struct{
+		a_uint32_t reg_count;
+		a_uint32_t reg_addr[32];
+		a_uint32_t reg_value[32];
+		a_int8_t   reg_name[32];
+	}fal_debug_reg_dump_t;
+
+typedef struct{
+	a_uint32_t phy_count;
+	a_uint32_t phy_base;
+	a_uint32_t phy_end;
+	a_uint16_t phy_value[256];
+	a_int8_t   phy_name[32];
+}fal_phy_dump_t;
+
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_TYPE_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_uk_if.h b/qca-ssdk/include/fal/fal_uk_if.h
new file mode 100755
index 0000000..faad2f2
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_uk_if.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _FAL_UK_IF_H_
+#define _FAL_UK_IF_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+#include "ssdk_init.h"
+
+    sw_error_t
+    sw_uk_exec(a_uint32_t api_id, ...);
+
+    sw_error_t
+    ssdk_init(a_uint32_t dev_id, ssdk_init_cfg * cfg);
+
+    sw_error_t
+    ssdk_cleanup(void);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_UK_IF_H_ */
+
+
diff --git a/qca-ssdk/include/fal/fal_vlan.h b/qca-ssdk/include/fal/fal_vlan.h
new file mode 100755
index 0000000..6386e05
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_vlan.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_vlan FAL_VLAN
+ * @{
+ */
+#ifndef _FAL_VLAN_H
+#define _FAL_VLAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+    /**
+    @brief This structure defines vlan entry.
+    */
+    typedef struct
+    {
+        a_uint16_t vid;     /**<  vlan entry id */
+        a_uint16_t fid;     /**<   filter data base id*/
+        fal_pbmp_t mem_ports;       /**<  member port bit map */
+        fal_pbmp_t tagged_ports;    /**<   bit map of tagged infomation for member port*/
+        fal_pbmp_t untagged_ports;  /**<   bit map of untagged infomation for member port*/
+        fal_pbmp_t unmodify_ports;/**<   bit map of unmodified infomation for member port*/
+        fal_pbmp_t u_ports;
+        a_bool_t   learn_dis;   /**< disable address learning*/
+        a_bool_t   vid_pri_en;  /**<   enable 802.1p*/
+        a_uint8_t  vid_pri;     /**<   vlaue of 802.1p when enable vid_pri_en*/
+    } fal_vlan_t;
+
+
+    sw_error_t
+    fal_vlan_entry_append(a_uint32_t dev_id, fal_vlan_t * vlan_entry);
+
+
+
+    sw_error_t
+    fal_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+
+    sw_error_t
+    fal_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+
+    sw_error_t
+    fal_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+
+    sw_error_t
+    fal_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                           fal_pbmp_t member, fal_pbmp_t u_member);
+
+
+
+    sw_error_t
+    fal_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+
+    sw_error_t
+    fal_vlan_reset(a_uint32_t dev_id);
+
+
+    sw_error_t
+    fal_vlan_flush(a_uint32_t dev_id);
+
+
+    sw_error_t
+    fal_vlan_init(a_uint32_t dev_id);
+
+
+    sw_error_t
+    fal_vlan_cleanup(void);
+
+
+    sw_error_t
+    fal_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid);
+
+
+    sw_error_t
+    fal_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid);
+
+
+    sw_error_t
+    fal_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+                        fal_port_t port_id, fal_pt_1q_egmode_t port_info);
+
+
+    sw_error_t
+    fal_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id);
+
+
+    sw_error_t
+    fal_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+                                a_bool_t enable);
+
+
+    sw_error_t
+    fal_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+                                a_bool_t * enable);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _FAL_VLAN_H */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/fal/fal_vsi.h b/qca-ssdk/include/fal/fal_vsi.h
new file mode 100755
index 0000000..2e4a42e
--- /dev/null
+++ b/qca-ssdk/include/fal/fal_vsi.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_stp FAL_VSI
+ * @{
+ */
+#ifndef _FAL_VSI_H_
+#define _FAL_VSI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal/fal_type.h"
+
+#define FAL_VSI_INVALID 0xffff
+#define FAL_VLAN_INVALID 0xffff
+#define FAL_VSI_MAX 31
+#define FAL_VLAN_MAX 4095
+
+typedef struct{
+	a_uint32_t lrn_en; /*0: disable new address learn, 1: enable new address learn*/
+	fal_fwd_cmd_t action;/*0:forward, 1:drop, 2: copy to CPU, 3: redirect to CPU*/
+}fal_vsi_newaddr_lrn_t;
+
+typedef struct{
+	a_uint32_t stamove_en;/*0:disable station move, 1: enable station move*/
+	fal_fwd_cmd_t action;/*0:forward, 1:drop, 2: copy to CPU, 3: redirect to CPU*/
+}fal_vsi_stamove_t;
+
+typedef struct{
+	a_uint32_t member_ports;/*VSI member ports for all packets*/
+	a_uint32_t uuc_ports;/*VSI member ports for unknown unicast*/
+	a_uint32_t umc_ports;/*VSI member ports for unknown multicast*/
+	a_uint32_t bc_ports;/*VSI member ports for broadcast*/
+}fal_vsi_member_t;
+
+
+typedef struct
+{
+	a_uint32_t rx_packet_counter;
+	a_uint64_t rx_byte_counter;
+	a_uint32_t tx_packet_counter;
+	a_uint64_t tx_byte_counter;
+	a_uint32_t fwd_packet_counter;
+	a_uint64_t fwd_byte_counter;
+	a_uint32_t drop_packet_counter;
+	a_uint64_t drop_byte_counter;
+}fal_vsi_counter_t;
+
+
+enum{
+	FUNC_PORT_VLAN_VSI_SET,
+	FUNC_PORT_VLAN_VSI_GET,
+	FUNC_PORT_VSI_SET,
+	FUNC_PORT_VSI_GET,
+	FUNC_VSI_STAMOVE_SET,
+	FUNC_VSI_STAMOVE_GET,
+	FUNC_VSI_NEWADDR_LRN_SET,
+	FUNC_VSI_NEWADDR_LRN_GET,
+	FUNC_VSI_MEMBER_SET,
+	FUNC_VSI_MEMBER_GET,
+	FUNC_VSI_COUNTER_GET,
+	FUNC_VSI_COUNTER_CLEANUP,
+};
+
+sw_error_t
+fal_vsi_alloc(a_uint32_t dev_id, a_uint32_t *vsi);
+
+sw_error_t
+fal_vsi_free(a_uint32_t dev_id, a_uint32_t vsi);
+
+sw_error_t
+fal_port_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vsi_id);
+
+#ifndef IN_VSI_MINI
+sw_error_t
+fal_port_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vsi_id);
+
+sw_error_t
+fal_vsi_stamove_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove);
+
+sw_error_t
+fal_vsi_newaddr_lrn_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn);
+
+sw_error_t
+fal_vsi_counter_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_counter_t *counter);
+
+sw_error_t
+fal_vsi_counter_cleanup(a_uint32_t dev_id, a_uint32_t vsi_id);
+#endif
+
+sw_error_t
+fal_port_vlan_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id);
+
+sw_error_t
+fal_port_vlan_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t *vsi_id);
+
+sw_error_t
+fal_vsi_tbl_dump(a_uint32_t dev_id);
+
+sw_error_t
+fal_vsi_newaddr_lrn_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn);
+
+sw_error_t
+fal_vsi_stamove_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove);
+
+sw_error_t
+fal_vsi_member_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member);
+
+sw_error_t
+fal_vsi_member_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member);
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _FAL_VSI_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/hsl/athena/athena_api.h b/qca-ssdk/include/hsl/athena/athena_api.h
new file mode 100755
index 0000000..543cab6
--- /dev/null
+++ b/qca-ssdk/include/hsl/athena/athena_api.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _ATHENA_API_H_
+#define _ATHENA_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#ifdef IN_PORTCONTROL
+#define PORTCONTROL_API \
+    SW_API_DEF(SW_API_PT_DUPLEX_GET, athena_port_duplex_get), \
+    SW_API_DEF(SW_API_PT_DUPLEX_SET, athena_port_duplex_set), \
+    SW_API_DEF(SW_API_PT_SPEED_GET, athena_port_speed_get), \
+    SW_API_DEF(SW_API_PT_SPEED_SET, athena_port_speed_set), \
+    SW_API_DEF(SW_API_PT_AN_GET, athena_port_autoneg_status_get), \
+    SW_API_DEF(SW_API_PT_AN_ENABLE, athena_port_autoneg_enable), \
+    SW_API_DEF(SW_API_PT_AN_RESTART, athena_port_autoneg_restart), \
+    SW_API_DEF(SW_API_PT_AN_ADV_GET, athena_port_autoneg_adv_get), \
+    SW_API_DEF(SW_API_PT_AN_ADV_SET, athena_port_autoneg_adv_set), \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, athena_port_igmps_status_set), \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, athena_port_igmps_status_get), \
+    SW_API_DEF(SW_API_PT_POWERSAVE_SET, athena_port_powersave_set), \
+    SW_API_DEF(SW_API_PT_POWERSAVE_GET, athena_port_powersave_get), \
+    SW_API_DEF(SW_API_PT_HIBERNATE_SET, athena_port_hibernate_set), \
+    SW_API_DEF(SW_API_PT_HIBERNATE_GET, athena_port_hibernate_get),
+
+
+#define PORTCONTROL_API_PARAM \
+    SW_API_DESC(SW_API_PT_DUPLEX_GET)  \
+    SW_API_DESC(SW_API_PT_DUPLEX_SET)  \
+    SW_API_DESC(SW_API_PT_SPEED_GET)  \
+    SW_API_DESC(SW_API_PT_SPEED_SET)  \
+    SW_API_DESC(SW_API_PT_AN_GET)  \
+    SW_API_DESC(SW_API_PT_AN_ENABLE)  \
+    SW_API_DESC(SW_API_PT_AN_RESTART) \
+    SW_API_DESC(SW_API_PT_AN_ADV_GET) \
+    SW_API_DESC(SW_API_PT_AN_ADV_SET) \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
+    SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
+    SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
+    SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
+    SW_API_DESC(SW_API_PT_HIBERNATE_GET)
+#else
+#define PORTCONTROL_API
+#define PORTCONTROL_API_PARAM
+#endif
+
+#ifdef IN_VLAN
+#define VLAN_API \
+    SW_API_DEF(SW_API_VLAN_ADD, athena_vlan_create), \
+    SW_API_DEF(SW_API_VLAN_DEL, athena_vlan_delete), \
+    SW_API_DEF(SW_API_VLAN_MEM_UPDATE, athena_vlan_member_update), \
+    SW_API_DEF(SW_API_VLAN_FIND, athena_vlan_find), \
+    SW_API_DEF(SW_API_VLAN_NEXT, athena_vlan_next), \
+    SW_API_DEF(SW_API_VLAN_APPEND, athena_vlan_entry_append),
+
+#define VLAN_API_PARAM \
+    SW_API_DESC(SW_API_VLAN_ADD)  \
+    SW_API_DESC(SW_API_VLAN_DEL)  \
+    SW_API_DESC(SW_API_VLAN_MEM_UPDATE) \
+    SW_API_DESC(SW_API_VLAN_FIND) \
+    SW_API_DESC(SW_API_VLAN_NEXT) \
+    SW_API_DESC(SW_API_VLAN_APPEND)
+#else
+#define VLAN_API
+#define VLAN_API_PARAM
+#endif
+
+#ifdef IN_PORTVLAN
+#define PORTVLAN_API \
+    SW_API_DEF(SW_API_PT_ING_MODE_GET, athena_port_1qmode_get), \
+    SW_API_DEF(SW_API_PT_ING_MODE_SET, athena_port_1qmode_set), \
+    SW_API_DEF(SW_API_PT_EG_MODE_GET, athena_port_egvlanmode_get), \
+    SW_API_DEF(SW_API_PT_EG_MODE_SET, athena_port_egvlanmode_set), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, athena_portvlan_member_add), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, athena_portvlan_member_del), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, athena_portvlan_member_update), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_GET, athena_portvlan_member_get), \
+ 
+#define PORTVLAN_API_PARAM \
+    SW_API_DESC(SW_API_PT_ING_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_ING_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_EG_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_EG_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE)  \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_GET)
+#else
+#define PORTVLAN_API
+#define PORTVLAN_API_PARAM
+#endif
+
+#ifdef IN_FDB
+#define FDB_API \
+    SW_API_DEF(SW_API_FDB_ADD, athena_fdb_add), \
+    SW_API_DEF(SW_API_FDB_DELALL, athena_fdb_del_all), \
+    SW_API_DEF(SW_API_FDB_DELPORT,athena_fdb_del_by_port), \
+    SW_API_DEF(SW_API_FDB_DELMAC, athena_fdb_del_by_mac), \
+    SW_API_DEF(SW_API_FDB_FIRST,  athena_fdb_first), \
+    SW_API_DEF(SW_API_FDB_NEXT,   athena_fdb_next),
+
+#define FDB_API_PARAM \
+    SW_API_DESC(SW_API_FDB_ADD)  \
+    SW_API_DESC(SW_API_FDB_DELALL)  \
+    SW_API_DESC(SW_API_FDB_DELPORT) \
+    SW_API_DESC(SW_API_FDB_DELMAC)  \
+    SW_API_DESC(SW_API_FDB_FIRST)   \
+    SW_API_DESC(SW_API_FDB_NEXT)
+#else
+#define FDB_API
+#define FDB_API_PARAM
+#endif
+
+#ifdef IN_MIB
+#define MIB_API \
+    SW_API_DEF(SW_API_PT_MIB_GET, athena_get_mib_info),
+
+#define MIB_API_PARAM \
+    SW_API_DESC(SW_API_PT_MIB_GET)
+#else
+#define MIB_API
+#define MIB_API_PARAM
+#endif
+
+#define REG_API \
+    SW_API_DEF(SW_API_PHY_GET, athena_phy_get), \
+    SW_API_DEF(SW_API_PHY_SET, athena_phy_set), \
+    SW_API_DEF(SW_API_REG_GET, athena_reg_get), \
+    SW_API_DEF(SW_API_REG_SET, athena_reg_set), \
+    SW_API_DEF(SW_API_REG_FIELD_GET, athena_reg_field_get), \
+    SW_API_DEF(SW_API_REG_FIELD_SET, athena_reg_field_set),
+
+#define REG_API_PARAM \
+    SW_API_DESC(SW_API_PHY_GET)  \
+    SW_API_DESC(SW_API_PHY_SET)  \
+    SW_API_DESC(SW_API_REG_GET)  \
+    SW_API_DESC(SW_API_REG_SET)  \
+    SW_API_DESC(SW_API_REG_FIELD_GET) \
+    SW_API_DESC(SW_API_REG_FIELD_SET)
+
+#define SSDK_API \
+    SW_API_DEF(SW_API_SWITCH_RESET, athena_reset), \
+    SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \
+    MIB_API \
+    PORTCONTROL_API \
+    PORTVLAN_API \
+    VLAN_API \
+    FDB_API \
+    REG_API \
+    SW_API_DEF(SW_API_MAX, NULL)
+
+#define SSDK_PARAM  \
+    SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
+    MIB_API_PARAM \
+    PORTCONTROL_API_PARAM \
+    PORTVLAN_API_PARAM \
+    VLAN_API_PARAM \
+    FDB_API_PARAM \
+    REG_API_PARAM \
+    SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#if (defined(USER_MODE) && defined(KERNEL_MODULE))
+#undef SSDK_API
+#undef SSDK_PARAM
+
+#define SSDK_API \
+    REG_API \
+    SW_API_DEF(SW_API_MAX, NULL),
+
+#define SSDK_PARAM  \
+    REG_API_PARAM \
+    SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _ATHENA_API_H_ */
diff --git a/qca-ssdk/include/hsl/athena/athena_fdb.h b/qca-ssdk/include/hsl/athena/athena_fdb.h
new file mode 100755
index 0000000..7a4cb85
--- /dev/null
+++ b/qca-ssdk/include/hsl/athena/athena_fdb.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _ATHENA_FDB_H
+#define _ATHENA_FDB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_fdb.h"
+
+    sw_error_t athena_fdb_init(a_uint32_t dev_id);
+
+#ifdef IN_FDB
+#define ATHENA_FDB_INIT(rv, dev_id) \
+    { \
+        rv = athena_fdb_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ATHENA_FDB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    athena_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id,
+                           a_uint32_t flag);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * addr);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ATHENA_FDB_H */
+
diff --git a/qca-ssdk/include/hsl/athena/athena_init.h b/qca-ssdk/include/hsl/athena/athena_init.h
new file mode 100755
index 0000000..2720961
--- /dev/null
+++ b/qca-ssdk/include/hsl/athena/athena_init.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _ATHENA_INIT_H_
+#define _ATHENA_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+    sw_error_t
+    athena_init(a_uint32_t dev_id, ssdk_init_cfg * cfg);
+
+    sw_error_t
+    athena_cleanup(a_uint32_t dev_id);
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    athena_reset(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ATHENA_INIT_H_ */
+
+
diff --git a/qca-ssdk/include/hsl/athena/athena_mib.h b/qca-ssdk/include/hsl/athena/athena_mib.h
new file mode 100755
index 0000000..0e1bc1b
--- /dev/null
+++ b/qca-ssdk/include/hsl/athena/athena_mib.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _ATHENA_MIB_H
+#define _ATHENA_MIB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mib.h"
+
+    sw_error_t
+    athena_mib_init(a_uint32_t dev_id);
+
+#ifdef IN_MIB
+#define ATHENA_MIB_INIT(rv, dev_id) \
+    { \
+        rv = athena_mib_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ATHENA_MIB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    athena_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_mib_info_t * mib_info );
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ATHENA_MIB_H */
diff --git a/qca-ssdk/include/hsl/athena/athena_port_ctrl.h b/qca-ssdk/include/hsl/athena/athena_port_ctrl.h
new file mode 100755
index 0000000..73f6770
--- /dev/null
+++ b/qca-ssdk/include/hsl/athena/athena_port_ctrl.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ATHENA_PORT_CTRL_H
+#define _ATHENA_PORT_CTRL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_port_ctrl.h"
+
+    sw_error_t athena_port_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTCONTROL
+#define ATHENA_PORT_CTRL_INIT(rv, dev_id) \
+    { \
+        rv = athena_port_ctrl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ATHENA_PORT_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_port_duplex_t duplex);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_port_duplex_t * pduplex);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_speed_t speed);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_speed_t * pspeed);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * status);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t autoadv);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * autoadv);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ATHENA_PORT_CTRL_H */
diff --git a/qca-ssdk/include/hsl/athena/athena_portvlan.h b/qca-ssdk/include/hsl/athena/athena_portvlan.h
new file mode 100755
index 0000000..00385d9
--- /dev/null
+++ b/qca-ssdk/include/hsl/athena/athena_portvlan.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _ATHENA_PORTVLAN_H
+#define _ATHENA_PORTVLAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_portvlan.h"
+
+    sw_error_t
+    athena_portvlan_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTVLAN
+#define ATHENA_PORTVLAN_INIT(rv, dev_id) \
+    { \
+        rv = athena_portvlan_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ATHENA_PORTVLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_1qmode_t port_1qmode);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_1qmode_t * pport_1qmode);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_pt_1q_egmode_t port_egvlanmode);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_pt_1q_egmode_t * pport_egvlanmode);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t mem_port_id);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t mem_port_id);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_pbmp_t mem_port_map);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_pbmp_t *mem_port_map);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ATHENA_PORTVLAN_H */
diff --git a/qca-ssdk/include/hsl/athena/athena_reg.h b/qca-ssdk/include/hsl/athena/athena_reg.h
new file mode 100755
index 0000000..3553ce7
--- /dev/null
+++ b/qca-ssdk/include/hsl/athena/athena_reg.h
@@ -0,0 +1,2157 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _ATHENA_REG_H
+#define _ATHENA_REG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define MAX_ENTRY_LEN 128
+
+#define HSL_RW 1
+#define HSL_RO 0
+
+    /**
+      * Athena Mask Control Register
+      */
+#define MASK_CTL                  "mask"
+#define MASK_CTL_ID               0
+#define MASK_CTL_OFFSET           0x0000
+#define MASK_CTL_E_LENGTH         4
+#define MASK_CTL_E_OFFSET         0
+#define MASK_CTL_NR_E             0
+
+#define SOFT_RST                              "mask_rst"
+#define MASK_CTL_SOFT_RST_BOFFSET             31
+#define MASK_CTL_SOFT_RST_BLEN                1
+#define MASK_CTL_SOFT_RST_FLAG                HSL_RW
+
+#define MII_CLK_SEL                           "mask_clks"
+#define MASK_CTL_MII_CLK_SEL_BOFFSET          24
+#define MASK_CTL_MII_CLK_SEL_BLEN             1
+#define MASK_CTL_MII_CLK_SEL_FLAG             HSL_RW
+
+#define RMII_PHY_RX_SEL                       "mask_prxs"
+#define MASK_CTL_RMII_PHY_RX_SEL_BOFFSET      23
+#define MASK_CTL_RMII_PHY_RX_SEL_BLEN         1
+#define MASK_CTL_RMII_PHY_RX_SEL_FLAG         HSL_RW
+
+#define RMII_PHY_TX_SEL                       "mask_ptxs"
+#define MASK_CTL_RMII_PHY_TX_SEL_BOFFSET      22
+#define MASK_CTL_RMII_PHY_TX_SEL_BLEN         1
+#define MASK_CTL_RMII_PHY_TX_SEL_FLAG         HSL_RW
+
+#define RMII_MAC_RX_SEL                       "mask_mrxs"
+#define MASK_CTL_RMII_MAC_RX_SEL_BOFFSET      21
+#define MASK_CTL_RMII_MAC_RX_SEL_BLEN         1
+#define MASK_CTL_RMII_MAC_RX_SEL_FLAG         HSL_RW
+
+#define RMII_MAC_TX_SEL                       "mask_mtxs"
+#define MASK_CTL_RMII_MAC_TX_SEL_BOFFSET      20
+#define MASK_CTL_RMII_MAC_TX_SEL_BLEN         1
+#define MASK_CTL_RMII_MAC_TX_SEL_FLAG         HSL_RW
+
+#define LOAD_EEPROM                           "mask_ldro"
+#define MASK_CTL_LOAD_EEPROM_BOFFSET          16
+#define MASK_CTL_LOAD_EEPROM_BLEN             1
+#define MASK_CTL_LOAD_EEPROM_FLAG             HSL_RW
+
+#define DEVICE_ID                             "mask_did"
+#define MASK_CTL_DEVICE_ID_BOFFSET            8
+#define MASK_CTL_DEVICE_ID_BLEN               8
+#define MASK_CTL_DEVICE_ID_FLAG               HSL_RO
+
+#define REV_ID                                "mask_rid"
+#define MASK_CTL_REV_ID_BOFFSET               0
+#define MASK_CTL_REV_ID_BLEN                  8
+#define MASK_CTL_REV_ID_FLAG                  HSL_RO
+
+    /**
+      * Global Interrupt Register
+      */
+#define GLOBAL_INT                "gint"
+#define GLOBAL_INT_ID             1
+#define GLOBAL_INT_OFFSET         0x0010
+#define GLOBAL_INT_E_LENGTH       4
+#define GLOBAL_INT_E_OFFSET       0
+#define GLOBAL_INT_NR_E           0
+
+#define GLB_QM_ERR_CNT                            "gint_qmen"
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BOFFSET         24
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BLEN            8
+#define GLOBAL_INT_GLB_QM_ERR_CNT_FLAG            HSL_RO
+
+#define GLB_LOOKUP_ERR                            "gint_glblper"
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BOFFSET         17
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BLEN            1
+#define GLOBAL_INT_GLB_LOOKUP_ERR_FLAG            HSL_RW
+
+#define GLB_QM_ERR                                "gint_glbqmer"
+#define GLOBAL_INT_GLB_QM_ERR_BOFFSET             16
+#define GLOBAL_INT_GLB_QM_ERR_BLEN                1
+#define GLOBAL_INT_GLB_QM_ERR_FLAG                HSL_RW
+
+#define GLB_HW_INI_DONE                           "gint_hwid"
+#define GLOBAL_INT_GLB_HW_INI_DONE_BOFFSET        14
+#define GLOBAL_INT_GLB_HW_INI_DONE_BLEN           1
+#define GLOBAL_INT_GLB_HW_INI_DONE_FLAG           HSL_RW
+
+#define GLB_MIB_INI                               "gint_mibi"
+#define GLOBAL_INT_GLB_MIB_INI_BOFFSET            13
+#define GLOBAL_INT_GLB_MIB_INI_BLEN               1
+#define GLOBAL_INT_GLB_MIB_INI_FLAG               HSL_RW
+
+#define GLB_MIB_DONE                              "gint_mibd"
+#define GLOBAL_INT_GLB_MIB_DONE_BOFFSET           12
+#define GLOBAL_INT_GLB_MIB_DONE_BLEN              1
+#define GLOBAL_INT_GLB_MIB_DONE_FLAG              HSL_RW
+
+#define GLB_BIST_DONE                             "gint_bisd"
+#define GLOBAL_INT_GLB_BIST_DONE_BOFFSET          11
+#define GLOBAL_INT_GLB_BIST_DONE_BLEN             1
+#define GLOBAL_INT_GLB_BIST_DONE_FLAG             HSL_RW
+
+#define GLB_VT_MISS_VIO                           "gint_vtms"
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BOFFSET        10
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BLEN           1
+#define GLOBAL_INT_GLB_VT_MISS_VIO_FLAG           HSL_RW
+
+#define GLB_VT_MEM_VIO                            "gint_vtme"
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BOFFSET         9
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BLEN            1
+#define GLOBAL_INT_GLB_VT_MEM_VIO_FLAG            HSL_RW
+
+#define GLB_VT_DONE                               "gint_vtd"
+#define GLOBAL_INT_GLB_VT_DONE_BOFFSET            8
+#define GLOBAL_INT_GLB_VT_DONE_BLEN               1
+#define GLOBAL_INT_GLB_VT_DONE_FLAG               HSL_RW
+
+#define GLB_QM_INI                                "gint_qmin"
+#define GLOBAL_INT_GLB_QM_INI_BOFFSET             7
+#define GLOBAL_INT_GLB_QM_INI_BLEN                1
+#define GLOBAL_INT_GLB_QM_INI_FLAG                HSL_RW
+
+#define GLB_AT_INI                                "gint_atin"
+#define GLOBAL_INT_GLB_AT_INI_BOFFSET             6
+#define GLOBAL_INT_GLB_AT_INI_BLEN                1
+#define GLOBAL_INT_GLB_AT_INI_FLAG                HSL_RW
+
+#define GLB_ARL_FULL                              "gint_arlf"
+#define GLOBAL_INT_GLB_ARL_FULL_BOFFSET           5
+#define GLOBAL_INT_GLB_ARL_FULL_BLEN              1
+#define GLOBAL_INT_GLB_ARL_FULL_FLAG              HSL_RW
+
+#define GLB_ARL_DONE                              "gint_arld"
+#define GLOBAL_INT_GLB_ARL_DONE_BOFFSET           4
+#define GLOBAL_INT_GLB_ARL_DONE_BLEN              1
+#define GLOBAL_INT_GLB_ARL_DONE_FLAG              HSL_RW
+
+#define GLB_MDIO_DONE                             "gint_mdid"
+#define GLOBAL_INT_GLB_MDIO_DONE_BOFFSET          3
+#define GLOBAL_INT_GLB_MDIO_DONE_BLEN             1
+#define GLOBAL_INT_GLB_MDIO_DONE_FLAG             HSL_RW
+
+#define GLB_PHY_INT                               "gint_phyi"
+#define GLOBAL_INT_GLB_PHY_INT_BOFFSET            2
+#define GLOBAL_INT_GLB_PHY_INT_BLEN               1
+#define GLOBAL_INT_GLB_PHY_INT_FLAG               HSL_RW
+
+#define GLB_EEPROM_ERR                        "gint_epei"
+#define GLOBAL_INT_GLB_EEPROM_ERR_BOFFSET     1
+#define GLOBAL_INT_GLB_EEPROM_ERR_BLEN        1
+#define GLOBAL_INT_GLB_EEPROM_ERR_FLAG        HSL_RW
+
+#define GLB_EEPROM_INT                        "gint_epi"
+#define GLOBAL_INT_GLB_EEPROM_INT_BOFFSET     0
+#define GLOBAL_INT_GLB_EEPROM_INT_BLEN        1
+#define GLOBAL_INT_GLB_EEPROM_INT_FLAG        HSL_RW
+
+    /**
+      * Global Interrupt Mask Register
+      */
+#define GLOBAL_INT_MASK           "gintm"
+#define GLOBAL_INT_MASK_ID        2
+#define GLOBAL_INT_MASK_OFFSET    0x0014
+#define GLOBAL_INT_MASK_E_LENGTH  4
+#define GLOBAL_INT_MASK_E_OFFSET  0
+#define GLOBAL_INT_MASK_NR_E      0
+
+#define GLBM_LOOKUP_ERR                          "gintm_lpe"
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BOFFSET  17
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BLEN     1
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_FLAG     HSL_RW
+
+#define GLBM_QM_ERR                                "gintm_qme"
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BOFFSET        16
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BLEN           1
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_FLAG           HSL_RW
+
+#define GLBM_HW_INI_DONE                           "gintm_hwid"
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BOFFSET   14
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BLEN      1
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_FLAG      HSL_RW
+
+#define GLBM_MIB_INI                               "gintm_mibi"
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BOFFSET       13
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BLEN          1
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_FLAG          HSL_RW
+
+#define GLBM_MIB_DONE                              "gintm_mibd"
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BOFFSET      12
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BLEN         1
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_FLAG         HSL_RW
+
+#define GLBM_BIST_DONE                             "gintm_bisd"
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BOFFSET     11
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BLEN        1
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_FLAG        HSL_RW
+
+#define GLBM_VT_MISS_VIO                           "gintm_vtms"
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BOFFSET   10
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BLEN      1
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_FLAG      HSL_RW
+
+#define GLBM_VT_MEM_VIO                            "gintm_vtme"
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BOFFSET    9
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BLEN       1
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_FLAG       HSL_RW
+
+#define GLBM_VT_DONE                               "gintm_vtd"
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BOFFSET       8
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BLEN          1
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_FLAG          HSL_RW
+
+#define GLBM_QM_INI                                "gintm_qmin"
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BOFFSET        7
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BLEN           1
+#define GLOBAL_INT_MASK_GLBM_QM_INI_FLAG           HSL_RW
+
+#define GLBM_AT_INI                                "gintm_atin"
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BOFFSET        6
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BLEN           1
+#define GLOBAL_INT_MASK_GLBM_AT_INI_FLAG           HSL_RW
+
+#define GLBM_ARL_FULL                              "gintm_arlf"
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BOFFSET      5
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BLEN         1
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_FLAG         HSL_RW
+
+#define GLBM_ARL_DONE                              "gintm_arld"
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BOFFSET      4
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BLEN         1
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_FLAG         HSL_RW
+
+#define GLBM_MDIO_DONE                             "gintm_mdid"
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BOFFSET     3
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BLEN        1
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_FLAG        HSL_RW
+
+#define GLBM_PHY_INT                               "gintm_phy"
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BOFFSET       2
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BLEN          1
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_FLAG          HSL_RW
+
+#define GLBM_EEPROM_ERR                            "gintm_epe"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BOFFSET    1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BLEN       1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_FLAG       HSL_RW
+
+#define GLBM_EEPROM_INT                            "gintm_ep"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BOFFSET    0
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BLEN       1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_FLAG       HSL_RW
+
+
+    /**
+      * Global MAC Address Register
+      */
+//high
+#define GLOBAL_MAC_ADDR0           "gmac0"
+#define GLOBAL_MAC_ADDR0_ID        3
+#define GLOBAL_MAC_ADDR0_OFFSET    0x0020
+#define GLOBAL_MAC_ADDR0_E_LENGTH  4
+#define GLOBAL_MAC_ADDR0_E_OFFSET  0
+#define GLOBAL_MAC_ADDR0_NR_E      0
+
+#define GLB_BYTE4                                  "gmac_b4"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET         8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN            8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG            HSL_RW
+
+#define GLB_BYTE5                                  "gmac_b5"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET         0
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN            8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG            HSL_RW
+
+
+//low
+#define GLOBAL_MAC_ADDR1           "gmac1"
+#define GLOBAL_MAC_ADDR1_ID        4
+#define GLOBAL_MAC_ADDR1_OFFSET    0x0024
+#define GLOBAL_MAC_ADDR1_E_LENGTH  4
+#define GLOBAL_MAC_ADDR1_E_OFFSET  0
+#define GLOBAL_MAC_ADDR1_NR_E      0
+
+#define GLB_BYTE0                                  "gmac_b0"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET         24
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG            HSL_RW
+
+#define GLB_BYTE1                                  "gmac_b1"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET         16
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG            HSL_RW
+
+#define GLB_BYTE2                                  "gmac_b2"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET         8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG            HSL_RW
+
+#define GLB_BYTE3                                  "gmac_b3"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET         0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG            HSL_RW
+
+    /**
+      * Global Control Register
+      */
+#define GLOBAL_CTL                "gctl"
+#define GLOBAL_CTL_ID             5
+#define GLOBAL_CTL_OFFSET         0x0030
+#define GLOBAL_CTL_E_LENGTH       4
+#define GLOBAL_CTL_E_OFFSET       0
+#define GLOBAL_CTL_NR_E           0
+
+#define WEIGHT_PRIORITY                       "gctl_wpri"
+#define GLOBAL_CTL_WEIGHT_PRIORITY_BOFFSET    31
+#define GLOBAL_CTL_WEIGHT_PRIORITY_BLEN       1
+#define GLOBAL_CTL_WEIGHT_PRIORITY_FLAG       HSL_RW
+
+#define RATE_DROP_EN                          "gctl_rden"
+#define GLOBAL_CTL_RATE_DROP_EN_BOFFSET       30
+#define GLOBAL_CTL_RATE_DROP_EN_BLEN          1
+#define GLOBAL_CTL_RATE_DROP_EN_FLAG          HSL_RW
+
+#define QM_PRI_MODE                           "gctl_qmpm"
+#define GLOBAL_CTL_QM_PRI_MODE_BOFFSET        29
+#define GLOBAL_CTL_QM_PRI_MODE_BLEN           1
+#define GLOBAL_CTL_QM_PRI_MODE_FLAG           HSL_RW
+
+#define MIX_PRIORITY                          "gctl_mpri"
+#define GLOBAL_CTL_MIX_PRIORITY_BOFFSET       28
+#define GLOBAL_CTL_MIX_PRIORITY_BLEN          1
+#define GLOBAL_CTL_MIX_PRIORITY_FLAG          HSL_RW
+
+#define RATE_CRE_LIMIT                        "gctl_rcrl"
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BOFFSET     26
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BLEN        2
+#define GLOBAL_CTL_RATE_CRE_LIMIT_FLAG        HSL_RW
+
+#define RATE_TIME_SLOT                        "gctl_rtms"
+#define GLOBAL_CTL_RATE_TIME_SLOT_BOFFSET     24
+#define GLOBAL_CTL_RATE_TIME_SLOT_BLEN        2
+#define GLOBAL_CTL_RATE_TIME_SLOT_FLAG        HSL_RW
+
+#define RELOAD_TIMER                          "gctl_rdtm"
+#define GLOBAL_CTL_RELOAD_TIMER_BOFFSET       20
+#define GLOBAL_CTL_RELOAD_TIMER_BLEN          4
+#define GLOBAL_CTL_RELOAD_TIMER_FLAG          HSL_RW
+
+#define QM_CNT_LOCK                           "gctl_qmcl"
+#define GLOBAL_CTL_QM_CNT_LOCK_BOFFSET        19
+#define GLOBAL_CTL_QM_CNT_LOCK_BLEN           1
+#define GLOBAL_CTL_QM_CNT_LOCK_FLAG           HSL_RO
+
+#define BROAD_DROP_EN                         "gctl_bden"
+#define GLOBAL_CTL_BROAD_DROP_EN_BOFFSET      18
+#define GLOBAL_CTL_BROAD_DROP_EN_BLEN         1
+#define GLOBAL_CTL_BROAD_DROP_EN_FLAG         HSL_RW
+
+#define BROAD_STORM_CTRL                      "gctl_bsct"
+#define GLOBAL_CTL_BROAD_STORM_CTRL_BOFFSET   16
+#define GLOBAL_CTL_BROAD_STORM_CTRL_BLEN      2
+#define GLOBAL_CTL_BROAD_STORM_CTRL_FLAG      HSL_RW
+
+#define BROAD_STORM_EN                        "gctl_bsen"
+#define GLOBAL_CTL_BROAD_STORM_EN_BOFFSET     11
+#define GLOBAL_CTL_BROAD_STORM_EN_BLEN        1
+#define GLOBAL_CTL_BROAD_STORM_EN_FLAG        HSL_RW
+
+#define MAX_FRAME_SIZE                        "gctl_mfsz"
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BOFFSET     0
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BLEN        11
+#define GLOBAL_CTL_MAX_FRAME_SIZE_FLAG        HSL_RW
+
+    /**
+      * Flow Control Register
+      */
+#define FLOW_CTL                  "fctl"
+#define FLOW_CTL_ID               6
+#define FLOW_CTL_OFFSET           0x0034
+#define FLOW_CTL_E_LENGTH         4
+#define FLOW_CTL_E_OFFSET         0
+#define FLOW_CTL_NR_E             0
+
+#define TEST_PAUSE                            "fctl_tps"
+#define FLOW_CTL_TEST_PAUSE_BOFFSET           31
+#define FLOW_CTL_TEST_PAUSE_BLEN              1
+#define FLOW_CTL_TEST_PAUSE_FLAG              HSL_RW
+
+#define PORT_PAUSE_OFF_THRES                  "fctl_pofft"
+#define FLOW_CTL_PORT_PAUSE_OFF_THRES_BOFFSET 24
+#define FLOW_CTL_PORT_PAUSE_OFF_THRES_BLEN    7
+#define FLOW_CTL_PORT_PAUSE_OFF_THRES_FLAG    HSL_RW
+
+#define PORT_PAUSE_ON_THRES                   "fctl_pont"
+#define FLOW_CTL_PORT_PAUSE_ON_THRES_BOFFSET  16
+#define FLOW_CTL_PORT_PAUSE_ON_THRES_BLEN     7
+#define FLOW_CTL_PORT_PAUSE_ON_THRES_FLAG     HSL_RW
+
+#define GOL_PAUSE_OFF_THRES                   "fctl_gofft"
+#define FLOW_CTL_GOL_PAUSE_OFF_THRES_BOFFSET  8
+#define FLOW_CTL_GOL_PAUSE_OFF_THRES_BLEN     8
+#define FLOW_CTL_GOL_PAUSE_OFF_THRES_FLAG     HSL_RW
+
+#define GOL_PAUSE_ON_THRES                    "fctl_gont"
+#define FLOW_CTL_GOL_PAUSE_ON_THRES_BOFFSET   0
+#define FLOW_CTL_GOL_PAUSE_ON_THRES_BLEN      8
+#define FLOW_CTL_GOL_PAUSE_ON_THRES_FLAG      HSL_RW
+
+    /**
+      * QM Control Register
+      */
+#define QM_CTL                    "qmct"
+#define QM_CTL_ID                 7
+#define QM_CTL_OFFSET             0x0038
+#define QM_CTL_E_LENGTH           4
+#define QM_CTL_E_OFFSET           0
+#define QM_CTL_NR_E               0
+
+#define QM_ERR_RST_EN                           "qmct_qeren"
+#define QM_CTL_QM_ERR_RST_EN_BOFFSET          31
+#define QM_CTL_QM_ERR_RST_EN_BLEN             1
+#define QM_CTL_QM_ERR_RST_EN_FLAG             HSL_RW
+
+#define LOOKUP_ERR_RST_EN                     "qmct_lpesen"
+#define QM_CTL_LOOKUP_ERR_RST_EN_BOFFSET      30
+#define QM_CTL_LOOKUP_ERR_RST_EN_BLEN         1
+#define QM_CTL_LOOKUP_ERR_RST_EN_FLAG         HSL_RW
+
+#define FLOOD_TO_CPU_EN                       "qmct_fdcpuen"
+#define QM_CTL_FLOOD_TO_CPU_EN_BOFFSET        10
+#define QM_CTL_FLOOD_TO_CPU_EN_BLEN           1
+#define QM_CTL_FLOOD_TO_CPU_EN_FLAG           HSL_RW
+
+#define QM_FUNC_TEST                          "qmct_qmft"
+#define QM_CTL_QM_FUNC_TEST_BOFFSET           9
+#define QM_CTL_QM_FUNC_TEST_BLEN              1
+#define QM_CTL_QM_FUNC_TEST_FLAG              HSL_RW
+
+#define MS_FC_EN                              "qmct_msfe"
+#define QM_CTL_MS_FC_EN_BOFFSET               8
+#define QM_CTL_MS_FC_EN_BLEN                  1
+#define QM_CTL_MS_FC_EN_FLAG                  HSL_RW
+
+#define FLOW_DROP_EN                          "qmct_fden"
+#define QM_CTL_FLOW_DROP_EN_BOFFSET           7
+#define QM_CTL_FLOW_DROP_EN_BLEN              1
+#define QM_CTL_FLOW_DROP_EN_FLAG              HSL_RW
+
+#define FLOW_DROP_CNT                         "qmct_fdcn"
+#define QM_CTL_FLOW_DROP_CNT_BOFFSET          0
+#define QM_CTL_FLOW_DROP_CNT_BLEN             5
+#define QM_CTL_FLOW_DROP_CNT_FLAG             HSL_RW
+
+    /**
+      * QM Error Register
+      */
+#define QM_ERR                    "qmer"
+#define QM_ERR_ID                 8
+#define QM_ERR_OFFSET             0x003C
+#define QM_ERR_E_LENGTH           4
+#define QM_ERR_E_OFFSET           0
+#define QM_ERR_NR_E               0
+
+#define QM_ERR_DATA                           "qmer_data"
+#define QM_ERR_QM_ERR_DATA_BOFFSET            0
+#define QM_ERR_QM_ERR_DATA_BLEN               32
+#define QM_ERR_QM_ERR_DATA_FLAG               HSL_RO
+
+    /**
+      * Vlan Table Function Register
+      */
+//high
+#define VLAN_TABLE_FUNC0           "vtbf0"
+#define VLAN_TABLE_FUNC0_ID        9
+#define VLAN_TABLE_FUNC0_OFFSET    0x0040
+#define VLAN_TABLE_FUNC0_E_LENGTH  4
+#define VLAN_TABLE_FUNC0_E_OFFSET  0
+#define VLAN_TABLE_FUNC0_NR_E      0
+
+#define VT_PRI_EN                              "vtbf_vtpen"
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET     31
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN        1
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG        HSL_RW
+
+#define VT_PRI                                 "vtbf_vtpri"
+#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET        28
+#define VLAN_TABLE_FUNC0_VT_PRI_BLEN           3
+#define VLAN_TABLE_FUNC0_VT_PRI_FLAG           HSL_RW
+
+#define VLAN_ID                                "vtbf_vid"
+#define VLAN_TABLE_FUNC0_VLAN_ID_BOFFSET       16
+#define VLAN_TABLE_FUNC0_VLAN_ID_BLEN          12
+#define VLAN_TABLE_FUNC0_VLAN_ID_FLAG          HSL_RW
+
+#define VT_PORT_NUM                            "vtbf_vtpn"
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BOFFSET   8
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BLEN      4
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_FLAG      HSL_RW
+
+#define VT_FULL_VIO                            "vtbf_vtflv"
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BOFFSET   4
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BLEN      1
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_FLAG      HSL_RW
+
+#define VT_BUSY                                "vtbf_vtbs"
+#define VLAN_TABLE_FUNC0_VT_BUSY_BOFFSET       3
+#define VLAN_TABLE_FUNC0_VT_BUSY_BLEN          1
+#define VLAN_TABLE_FUNC0_VT_BUSY_FLAG          HSL_RW
+
+#define VT_FUNC                                "vtbf_vtfc"
+#define VLAN_TABLE_FUNC0_VT_FUNC_BOFFSET       0
+#define VLAN_TABLE_FUNC0_VT_FUNC_BLEN          3
+#define VLAN_TABLE_FUNC0_VT_FUNC_FLAG          HSL_RW
+
+//low
+#define VLAN_TABLE_FUNC1           "vtbf1"
+#define VLAN_TABLE_FUNC1_ID        10
+#define VLAN_TABLE_FUNC1_OFFSET    0x0044
+#define VLAN_TABLE_FUNC1_E_LENGTH  4
+#define VLAN_TABLE_FUNC1_E_OFFSET  0
+#define VLAN_TABLE_FUNC1_NR_E      0
+
+#define PORT_TAG_EN                            "vtbf_pgen"
+#define VLAN_TABLE_FUNC1_PORT_TAG_EN_BOFFSET   12
+#define VLAN_TABLE_FUNC1_PORT_TAG_EN_BLEN      20
+#define VLAN_TABLE_FUNC1_PORT_TAG_EN_FLAG      HSL_RW
+
+#define VT_VALID                               "vtbf_vtvd"
+#define VLAN_TABLE_FUNC1_VT_VALID_BOFFSET      11
+#define VLAN_TABLE_FUNC1_VT_VALID_BLEN         1
+#define VLAN_TABLE_FUNC1_VT_VALID_FLAG         HSL_RW
+
+#define VID_MEM                                "vtbf_vidm"
+#define VLAN_TABLE_FUNC1_VID_MEM_BOFFSET       0
+#define VLAN_TABLE_FUNC1_VID_MEM_BLEN          10
+#define VLAN_TABLE_FUNC1_VID_MEM_FLAG          HSL_RW
+
+    /**
+      * Address Table Function Register
+      */
+#define ADDR_TABLE_FUNC0           "atbf0"
+#define ADDR_TABLE_FUNC0_ID        11
+#define ADDR_TABLE_FUNC0_OFFSET    0x0050
+#define ADDR_TABLE_FUNC0_E_LENGTH  4
+#define ADDR_TABLE_FUNC0_E_OFFSET  0
+#define ADDR_TABLE_FUNC0_NR_E      0
+
+#define AT_ADDR_BYTE4                          "atbf_adb4"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 24
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE5                          "atbf_adb5"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 16
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG    HSL_RW
+
+#define AT_FULL_VIO                            "atbf_atfv"
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BOFFSET   12
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BLEN      1
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_FLAG      HSL_RW
+
+#define AT_PORT_NUM                            "atbf_atpn"
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BOFFSET   8
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BLEN      4
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_FLAG      HSL_RW
+
+#define AT_BUSY                                "atbf_atbs"
+#define ADDR_TABLE_FUNC0_AT_BUSY_BOFFSET       3
+#define ADDR_TABLE_FUNC0_AT_BUSY_BLEN          1
+#define ADDR_TABLE_FUNC0_AT_BUSY_FLAG          HSL_RW
+
+#define AT_FUNC                                "atbf_atfc"
+#define ADDR_TABLE_FUNC0_AT_FUNC_BOFFSET       0
+#define ADDR_TABLE_FUNC0_AT_FUNC_BLEN          3
+#define ADDR_TABLE_FUNC0_AT_FUNC_FLAG          HSL_RW
+
+
+#define ADDR_TABLE_FUNC1           "atbf1"
+#define ADDR_TABLE_FUNC1_ID        12
+#define ADDR_TABLE_FUNC1_OFFSET    0x0054
+#define ADDR_TABLE_FUNC1_E_LENGTH  4
+#define ADDR_TABLE_FUNC1_E_OFFSET  0
+#define ADDR_TABLE_FUNC1_NR_E      0
+
+#define AT_ADDR_BYTE0                          "atbf_adb0"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 24
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE1                          "atbf_adb1"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 16
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE2                          "atbf_adb2"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BOFFSET 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE3                          "atbf_adb3"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BOFFSET 0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_FLAG    HSL_RW
+
+
+#define ADDR_TABLE_FUNC2           "atbf2"
+#define ADDR_TABLE_FUNC2_ID        13
+#define ADDR_TABLE_FUNC2_OFFSET    0x0058
+#define ADDR_TABLE_FUNC2_E_LENGTH  4
+#define ADDR_TABLE_FUNC2_E_OFFSET  0
+#define ADDR_TABLE_FUNC2_NR_E      0
+
+#define COPY_TO_CPU                            "atbf_cpcpu"
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET   26
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN      1
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG      HSL_RW
+
+#define REDRCT_TO_CPU                          "atbf_rdcpu"
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 25
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN    1
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG    HSL_RW
+
+#define SA_DROP_EN                             "atbf_saden"
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BOFFSET    16
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BLEN       1
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_FLAG       HSL_RW
+
+#define AT_STATUS                              "atbf_atsts"
+#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET     14
+#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN        2
+#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG        HSL_RW
+
+#define MIRROR_EN                              "atbf_miren"
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BOFFSET     13
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BLEN        1
+#define ADDR_TABLE_FUNC2_MIRROR_EN_FLAG        HSL_RW
+
+#define AT_PRI_EN                              "atbf_atpen"
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BOFFSET     12
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BLEN        1
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_FLAG        HSL_RW
+
+#define AT_PRI                                 "atbf_atpri"
+#define ADDR_TABLE_FUNC2_AT_PRI_BOFFSET        10
+#define ADDR_TABLE_FUNC2_AT_PRI_BLEN           2
+#define ADDR_TABLE_FUNC2_AT_PRI_FLAG           HSL_RW
+
+#define DES_PORT                               "atbf_desp"
+#define ADDR_TABLE_FUNC2_DES_PORT_BOFFSET      0
+#define ADDR_TABLE_FUNC2_DES_PORT_BLEN         10
+#define ADDR_TABLE_FUNC2_DES_PORT_FLAG         HSL_RW
+
+    /**
+      * Address Table Control Register
+      */
+#define ADDR_TABLE_CTL            "atbc"
+#define ADDR_TABLE_CTL_ID         14
+#define ADDR_TABLE_CTL_OFFSET     0x005C
+#define ADDR_TABLE_CTL_E_LENGTH   4
+#define ADDR_TABLE_CTL_E_OFFSET   0
+#define ADDR_TABLE_CTL_NR_E       0
+
+#define ARP_EN                                 "atbc_arpe"
+#define ADDR_TABLE_CTL_ARP_EN_BOFFSET          20
+#define ADDR_TABLE_CTL_ARP_EN_BLEN             1
+#define ADDR_TABLE_CTL_ARP_EN_FLAG             HSL_RW
+
+#define ARL_INI_EN                             "atbc_arlie"
+#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET      19
+#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN         1
+#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG         HSL_RW
+
+#define BPDU_EN                                "atbc_bpdue"
+#define ADDR_TABLE_CTL_BPDU_EN_BOFFSET         18
+#define ADDR_TABLE_CTL_BPDU_EN_BLEN            1
+#define ADDR_TABLE_CTL_BPDU_EN_FLAG            HSL_RW
+
+#define AGE_EN                                 "atbc_agee"
+#define ADDR_TABLE_CTL_AGE_EN_BOFFSET          17
+#define ADDR_TABLE_CTL_AGE_EN_BLEN             1
+#define ADDR_TABLE_CTL_AGE_EN_FLAG             HSL_RW
+
+#define AGE_TIME                               "atbc_aget"
+#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET        0
+#define ADDR_TABLE_CTL_AGE_TIME_BLEN           16
+#define ADDR_TABLE_CTL_AGE_TIME_FLAG           HSL_RW
+
+    /**
+      * IP Priority Mapping Register
+      */
+#define IP_PRI_MAPPING0            "imap0"
+#define IP_PRI_MAPPING0_ID         15
+#define IP_PRI_MAPPING0_OFFSET     0x0060
+#define IP_PRI_MAPPING0_E_LENGTH   4
+#define IP_PRI_MAPPING0_E_OFFSET   0
+#define IP_PRI_MAPPING0_NR_E       0
+
+#define IP_0X3C                                "imap_ip3c"
+#define IP_PRI_MAPPING0_IP_0X3C_BOFFSET        30
+#define IP_PRI_MAPPING0_IP_0X3C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X3C_FLAG           HSL_RW
+
+#define IP_0X38                                "imap_ip38"
+#define IP_PRI_MAPPING0_IP_0X38_BOFFSET        28
+#define IP_PRI_MAPPING0_IP_0X38_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X38_FLAG           HSL_RW
+
+#define IP_0X34                                "imap_ip34"
+#define IP_PRI_MAPPING0_IP_0X34_BOFFSET        26
+#define IP_PRI_MAPPING0_IP_0X34_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X34_FLAG           HSL_RW
+
+#define IP_0X30                                "imap_ip30"
+#define IP_PRI_MAPPING0_IP_0X30_BOFFSET        24
+#define IP_PRI_MAPPING0_IP_0X30_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X30_FLAG           HSL_RW
+
+#define IP_0X2C                                "imap_ip2c"
+#define IP_PRI_MAPPING0_IP_0X2C_BOFFSET        22
+#define IP_PRI_MAPPING0_IP_0X2C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X2C_FLAG           HSL_RW
+
+#define IP_0X28                                "imap_ip28"
+#define IP_PRI_MAPPING0_IP_0X28_BOFFSET        20
+#define IP_PRI_MAPPING0_IP_0X28_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X28_FLAG           HSL_RW
+
+#define IP_0X24                                "imap_ip24"
+#define IP_PRI_MAPPING0_IP_0X24_BOFFSET        18
+#define IP_PRI_MAPPING0_IP_0X24_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X24_FLAG           HSL_RW
+
+#define IP_0X20                                "imap_ip20"
+#define IP_PRI_MAPPING0_IP_0X20_BOFFSET        16
+#define IP_PRI_MAPPING0_IP_0X20_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X20_FLAG           HSL_RW
+
+#define IP_0X1C                                "imap_ip1c"
+#define IP_PRI_MAPPING0_IP_0X1C_BOFFSET        14
+#define IP_PRI_MAPPING0_IP_0X1C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X1C_FLAG           HSL_RW
+
+#define IP_0X18                                "imap_ip18"
+#define IP_PRI_MAPPING0_IP_0X18_BOFFSET        12
+#define IP_PRI_MAPPING0_IP_0X18_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X18_FLAG           HSL_RW
+
+#define IP_0X14                                "imap_ip14"
+#define IP_PRI_MAPPING0_IP_0X14_BOFFSET        10
+#define IP_PRI_MAPPING0_IP_0X14_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X14_FLAG           HSL_RW
+
+#define IP_0X10                                "imap_ip10"
+#define IP_PRI_MAPPING0_IP_0X10_BOFFSET        8
+#define IP_PRI_MAPPING0_IP_0X10_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X10_FLAG           HSL_RW
+
+#define IP_0X0C                                "imap_ip0c"
+#define IP_PRI_MAPPING0_IP_0X0C_BOFFSET        6
+#define IP_PRI_MAPPING0_IP_0X0C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X0C_FLAG           HSL_RW
+
+#define IP_0X08                                "imap_ip08"
+#define IP_PRI_MAPPING0_IP_0X08_BOFFSET        4
+#define IP_PRI_MAPPING0_IP_0X08_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X08_FLAG           HSL_RW
+
+#define IP_0X04                                "imap_ip04"
+#define IP_PRI_MAPPING0_IP_0X04_BOFFSET        2
+#define IP_PRI_MAPPING0_IP_0X04_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X04_FLAG           HSL_RW
+
+#define IP_0X00                                "imap_ip00"
+#define IP_PRI_MAPPING0_IP_0X00_BOFFSET        0
+#define IP_PRI_MAPPING0_IP_0X00_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X00_FLAG           HSL_RW
+
+#define IP_PRI_MAPPING1            "imap1"
+#define IP_PRI_MAPPING1_ID         16
+#define IP_PRI_MAPPING1_OFFSET     0x0064
+#define IP_PRI_MAPPING1_E_LENGTH   4
+#define IP_PRI_MAPPING1_E_OFFSET   0
+#define IP_PRI_MAPPING1_NR_E       0
+
+#define IP_0X7C                                "imap_ip7c"
+#define IP_PRI_MAPPING1_IP_0X7C_BOFFSET        30
+#define IP_PRI_MAPPING1_IP_0X7C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X7C_FLAG           HSL_RW
+
+#define IP_0X78                                "imap_ip78"
+#define IP_PRI_MAPPING1_IP_0X78_BOFFSET        28
+#define IP_PRI_MAPPING1_IP_0X78_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X78_FLAG           HSL_RW
+
+#define IP_0X74                                "imap_ip74"
+#define IP_PRI_MAPPING1_IP_0X74_BOFFSET        26
+#define IP_PRI_MAPPING1_IP_0X74_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X74_FLAG           HSL_RW
+
+#define IP_0X70                                "imap_ip70"
+#define IP_PRI_MAPPING1_IP_0X70_BOFFSET        24
+#define IP_PRI_MAPPING1_IP_0X70_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X70_FLAG           HSL_RW
+
+#define IP_0X6C                                "imap_ip6c"
+#define IP_PRI_MAPPING1_IP_0X6C_BOFFSET        22
+#define IP_PRI_MAPPING1_IP_0X6C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X6C_FLAG           HSL_RW
+
+#define IP_0X68                                "imap_ip68"
+#define IP_PRI_MAPPING1_IP_0X68_BOFFSET        20
+#define IP_PRI_MAPPING1_IP_0X68_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X68_FLAG           HSL_RW
+
+#define IP_0X64                                "imap_ip64"
+#define IP_PRI_MAPPING1_IP_0X64_BOFFSET        18
+#define IP_PRI_MAPPING1_IP_0X64_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X64_FLAG           HSL_RW
+
+#define IP_0X60                                "imap_ip60"
+#define IP_PRI_MAPPING1_IP_0X60_BOFFSET        16
+#define IP_PRI_MAPPING1_IP_0X60_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X60_FLAG           HSL_RW
+
+#define IP_0X5C                                "imap_ip5c"
+#define IP_PRI_MAPPING1_IP_0X5C_BOFFSET        14
+#define IP_PRI_MAPPING1_IP_0X5C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X5C_FLAG           HSL_RW
+
+#define IP_0X58                                "imap_ip58"
+#define IP_PRI_MAPPING1_IP_0X58_BOFFSET        12
+#define IP_PRI_MAPPING1_IP_0X58_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X58_FLAG           HSL_RW
+
+#define IP_0X54                                "imap_ip54"
+#define IP_PRI_MAPPING1_IP_0X54_BOFFSET        10
+#define IP_PRI_MAPPING1_IP_0X54_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X54_FLAG           HSL_RW
+
+#define IP_0X50                                "imap_ip50"
+#define IP_PRI_MAPPING1_IP_0X50_BOFFSET        8
+#define IP_PRI_MAPPING1_IP_0X50_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X50_FLAG           HSL_RW
+
+#define IP_0X4C                                "imap_ip4c"
+#define IP_PRI_MAPPING1_IP_0X4C_BOFFSET        6
+#define IP_PRI_MAPPING1_IP_0X4C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X4C_FLAG           HSL_RW
+
+#define IP_0X48                                "imap_ip48"
+#define IP_PRI_MAPPING1_IP_0X48_BOFFSET        4
+#define IP_PRI_MAPPING1_IP_0X48_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X48_FLAG           HSL_RW
+
+#define IP_0X44                                "imap_ip44"
+#define IP_PRI_MAPPING1_IP_0X44_BOFFSET        2
+#define IP_PRI_MAPPING1_IP_0X44_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X44_FLAG           HSL_RW
+
+#define IP_0X40                                "imap_ip40"
+#define IP_PRI_MAPPING1_IP_0X40_BOFFSET        0
+#define IP_PRI_MAPPING1_IP_0X40_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X40_FLAG           HSL_RW
+
+
+#define IP_PRI_MAPPING2            "imap2"
+#define IP_PRI_MAPPING2_ID         17
+#define IP_PRI_MAPPING2_OFFSET     0x0068
+#define IP_PRI_MAPPING2_E_LENGTH   4
+#define IP_PRI_MAPPING2_E_OFFSET   0
+#define IP_PRI_MAPPING2_NR_E       0
+
+#define IP_0XBC                                "imap_ipbc"
+#define IP_PRI_MAPPING2_IP_0XBC_BOFFSET        30
+#define IP_PRI_MAPPING2_IP_0XBC_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XBC_FLAG           HSL_RW
+
+#define IP_0XB8                                "imap_ipb8"
+#define IP_PRI_MAPPING2_IP_0XB8_BOFFSET        28
+#define IP_PRI_MAPPING2_IP_0XB8_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XB8_FLAG           HSL_RW
+
+#define IP_0XB4                                "imap_ipb4"
+#define IP_PRI_MAPPING2_IP_0XB4_BOFFSET        26
+#define IP_PRI_MAPPING2_IP_0XB4_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XB4_FLAG           HSL_RW
+
+#define IP_0XB0                                "imap_ipb0"
+#define IP_PRI_MAPPING2_IP_0XB0_BOFFSET        24
+#define IP_PRI_MAPPING2_IP_0XB0_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XB0_FLAG           HSL_RW
+
+#define IP_0XAC                                "imap_ipac"
+#define IP_PRI_MAPPING2_IP_0XAC_BOFFSET        22
+#define IP_PRI_MAPPING2_IP_0XAC_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XAC_FLAG           HSL_RW
+
+#define IP_0XA8                                "imap_ipa8"
+#define IP_PRI_MAPPING2_IP_0XA8_BOFFSET        20
+#define IP_PRI_MAPPING2_IP_0XA8_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XA8_FLAG           HSL_RW
+
+#define IP_0XA4                                "imap_ipa4"
+#define IP_PRI_MAPPING2_IP_0XA4_BOFFSET        18
+#define IP_PRI_MAPPING2_IP_0XA4_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XA4_FLAG           HSL_RW
+
+#define IP_0XA0                                "imap_ipa0"
+#define IP_PRI_MAPPING2_IP_0XA0_BOFFSET        16
+#define IP_PRI_MAPPING2_IP_0XA0_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XA0_FLAG           HSL_RW
+
+#define IP_0X9C                                "imap_ip9c"
+#define IP_PRI_MAPPING2_IP_0X9C_BOFFSET        14
+#define IP_PRI_MAPPING2_IP_0X9C_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X9C_FLAG           HSL_RW
+
+#define IP_0X98                                "imap_ip98"
+#define IP_PRI_MAPPING2_IP_0X98_BOFFSET        12
+#define IP_PRI_MAPPING2_IP_0X98_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X98_FLAG           HSL_RW
+
+#define IP_0X94                                "imap_ip94"
+#define IP_PRI_MAPPING2_IP_0X94_BOFFSET        10
+#define IP_PRI_MAPPING2_IP_0X94_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X94_FLAG           HSL_RW
+
+#define IP_0X90                                "imap_ip90"
+#define IP_PRI_MAPPING2_IP_0X90_BOFFSET        8
+#define IP_PRI_MAPPING2_IP_0X90_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X90_FLAG           HSL_RW
+
+#define IP_0X8C                                "imap_ip8c"
+#define IP_PRI_MAPPING2_IP_0X8C_BOFFSET        6
+#define IP_PRI_MAPPING2_IP_0X8C_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X8C_FLAG           HSL_RW
+
+#define IP_0X88                                "imap_ip88"
+#define IP_PRI_MAPPING2_IP_0X88_BOFFSET        4
+#define IP_PRI_MAPPING2_IP_0X88_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X88_FLAG           HSL_RW
+
+#define IP_0X84                                "imap_ip84"
+#define IP_PRI_MAPPING2_IP_0X84_BOFFSET        2
+#define IP_PRI_MAPPING2_IP_0X84_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X84_FLAG           HSL_RW
+
+#define IP_0X80                                "imap_ip80"
+#define IP_PRI_MAPPING2_IP_0X80_BOFFSET        0
+#define IP_PRI_MAPPING2_IP_0X80_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X80_FLAG           HSL_RW
+
+#define IP_PRI_MAPPING3            "imap3"
+#define IP_PRI_MAPPING3_ID         18
+#define IP_PRI_MAPPING3_OFFSET     0x006C
+#define IP_PRI_MAPPING3_E_LENGTH   4
+#define IP_PRI_MAPPING3_E_OFFSET   0
+#define IP_PRI_MAPPING3_NR_E       0
+
+#define IP_0XFC                                "imap_ipfc"
+#define IP_PRI_MAPPING3_IP_0XFC_BOFFSET        30
+#define IP_PRI_MAPPING3_IP_0XFC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XFC_FLAG           HSL_RW
+
+#define IP_0XF8                                "imap_ipf8"
+#define IP_PRI_MAPPING3_IP_0XF8_BOFFSET        28
+#define IP_PRI_MAPPING3_IP_0XF8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XF8_FLAG           HSL_RW
+
+#define IP_0XF4                                "imap_ipf4"
+#define IP_PRI_MAPPING3_IP_0XF4_BOFFSET        26
+#define IP_PRI_MAPPING3_IP_0XF4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XF4_FLAG           HSL_RW
+
+#define IP_0XF0                                "imap_ipf0"
+#define IP_PRI_MAPPING3_IP_0XF0_BOFFSET        24
+#define IP_PRI_MAPPING3_IP_0XF0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XF0_FLAG           HSL_RW
+
+#define IP_0XEC                                "imap_ipec"
+#define IP_PRI_MAPPING3_IP_0XEC_BOFFSET        22
+#define IP_PRI_MAPPING3_IP_0XEC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XEC_FLAG           HSL_RW
+
+#define IP_0XE8                                "imap_ipe8"
+#define IP_PRI_MAPPING3_IP_0XE8_BOFFSET        20
+#define IP_PRI_MAPPING3_IP_0XE8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XE8_FLAG           HSL_RW
+
+#define IP_0XE4                                "imap_ipe4"
+#define IP_PRI_MAPPING3_IP_0XE4_BOFFSET        18
+#define IP_PRI_MAPPING3_IP_0XE4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XE4_FLAG           HSL_RW
+
+#define IP_0XE0                                "imap_ipe0"
+#define IP_PRI_MAPPING3_IP_0XE0_BOFFSET        16
+#define IP_PRI_MAPPING3_IP_0XE0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XE0_FLAG           HSL_RW
+
+#define IP_0XDC                                "imap_ipdc"
+#define IP_PRI_MAPPING3_IP_0XDC_BOFFSET        14
+#define IP_PRI_MAPPING3_IP_0XDC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XDC_FLAG           HSL_RW
+
+#define IP_0XD8                                "imap_ipd8"
+#define IP_PRI_MAPPING3_IP_0XD8_BOFFSET        12
+#define IP_PRI_MAPPING3_IP_0XD8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XD8_FLAG           HSL_RW
+
+#define IP_0XD4                                "imap_ipd4"
+#define IP_PRI_MAPPING3_IP_0XD4_BOFFSET        10
+#define IP_PRI_MAPPING3_IP_0XD4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XD4_FLAG           HSL_RW
+
+#define IP_0XD0                                "imap_ipd0"
+#define IP_PRI_MAPPING3_IP_0XD0_BOFFSET        8
+#define IP_PRI_MAPPING3_IP_0XD0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XD0_FLAG           HSL_RW
+
+#define IP_0XCC                                "imap_ipcc"
+#define IP_PRI_MAPPING3_IP_0XCC_BOFFSET        6
+#define IP_PRI_MAPPING3_IP_0XCC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XCC_FLAG           HSL_RW
+
+#define IP_0XC8                                "imap_ipc8"
+#define IP_PRI_MAPPING3_IP_0XC8_BOFFSET        4
+#define IP_PRI_MAPPING3_IP_0XC8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XC8_FLAG           HSL_RW
+
+#define IP_0XC4                                "imap_ipc4"
+#define IP_PRI_MAPPING3_IP_0XC4_BOFFSET        2
+#define IP_PRI_MAPPING3_IP_0XC4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XC4_FLAG           HSL_RW
+
+#define IP_0XC0                                "imap_ipc0"
+#define IP_PRI_MAPPING3_IP_0XC0_BOFFSET        0
+#define IP_PRI_MAPPING3_IP_0XC0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XC0_FLAG           HSL_RW
+
+    /**
+      * Tag Priority Mapping Register
+      */
+#define TAG_PRI_MAPPING           "tpmap"
+#define TAG_PRI_MAPPING_ID        19
+#define TAG_PRI_MAPPING_OFFSET    0x0070
+#define TAG_PRI_MAPPING_E_LENGTH  4
+#define TAG_PRI_MAPPING_E_OFFSET  0
+#define TAG_PRI_MAPPING_NR_E      0
+
+#define TAG_0X07                                "tpmap_tg07"
+#define TAG_PRI_MAPPING_TAG_0X07_BOFFSET      14
+#define TAG_PRI_MAPPING_TAG_0X07_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X07_FLAG         HSL_RW
+
+#define TAG_0X06                              "tpmap_tg06"
+#define TAG_PRI_MAPPING_TAG_0X06_BOFFSET      12
+#define TAG_PRI_MAPPING_TAG_0X06_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X06_FLAG         HSL_RW
+
+#define TAG_0X05                              "tpmap_tg05"
+#define TAG_PRI_MAPPING_TAG_0X05_BOFFSET      10
+#define TAG_PRI_MAPPING_TAG_0X05_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X05_FLAG         HSL_RW
+
+#define TAG_0X04                              "tpmap_tg04"
+#define TAG_PRI_MAPPING_TAG_0X04_BOFFSET      8
+#define TAG_PRI_MAPPING_TAG_0X04_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X04_FLAG         HSL_RW
+
+#define TAG_0X03                              "tpmap_tg03"
+#define TAG_PRI_MAPPING_TAG_0X03_BOFFSET      6
+#define TAG_PRI_MAPPING_TAG_0X03_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X03_FLAG         HSL_RW
+
+#define TAG_0X02                              "tpmap_tg02"
+#define TAG_PRI_MAPPING_TAG_0X02_BOFFSET      4
+#define TAG_PRI_MAPPING_TAG_0X02_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X02_FLAG         HSL_RW
+
+#define TAG_0X01                              "tpmap_tg01"
+#define TAG_PRI_MAPPING_TAG_0X01_BOFFSET      2
+#define TAG_PRI_MAPPING_TAG_0X01_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X01_FLAG         HSL_RW
+
+#define TAG_0X00                              "tpmap_tg00"
+#define TAG_PRI_MAPPING_TAG_0X00_BOFFSET      0
+#define TAG_PRI_MAPPING_TAG_0X00_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X00_FLAG         HSL_RW
+
+    /**
+      * Cpu Port Register
+      */
+#define CPU_PORT                  "cpup"
+#define CPU_PORT_ID               20
+#define CPU_PORT_OFFSET           0x0078
+#define CPU_PORT_E_LENGTH         4
+#define CPU_PORT_E_OFFSET         0
+#define CPU_PORT_NR_E             0
+
+#define CPU_PORT_EN                           "cpup_cpupe"
+#define CPU_PORT_CPU_PORT_EN_BOFFSET          8
+#define CPU_PORT_CPU_PORT_EN_BLEN             1
+#define CPU_PORT_CPU_PORT_EN_FLAG             HSL_RW
+
+#define MIRROR_PORT_NUM                       "cpup_mirpn"
+#define CPU_PORT_MIRROR_PORT_NUM_BOFFSET      4
+#define CPU_PORT_MIRROR_PORT_NUM_BLEN         4
+#define CPU_PORT_MIRROR_PORT_NUM_FLAG         HSL_RW
+
+#define RMII_CUT                              "cpup_rmcut"
+#define CPU_PORT_RMII_CUT_BOFFSET             0
+#define CPU_PORT_RMII_CUT_BLEN                1
+#define CPU_PORT_RMII_CUT_FLAG                HSL_RW
+
+    /**
+      * MIB Function Register
+      */
+#define MIB_CNT                  "mibcnt"
+#define MIB_CNT_ID               21
+#define MIB_CNT_OFFSET           0x0080
+#define MIB_CNT_E_LENGTH         4
+#define MIB_CNT_E_OFFSET         0
+#define MIB_CNT_NR_E             0
+
+#define MIB_FUNC                              "mibcnt_mibf"
+#define MIB_CNT_MIB_FUNC_BOFFSET              24
+#define MIB_CNT_MIB_FUNC_BLEN                 3
+#define MIB_CNT_MIB_FUNC_FLAG                 HSL_RW
+
+#define MIB_BUSY                              "mibcnt_mibb"
+#define MIB_CNT_MIB_BUSY_BOFFSET              17
+#define MIB_CNT_MIB_BUSY_BLEN                 1
+#define MIB_CNT_MIB_BUSY_FLAG                 HSL_RW
+
+#define MIB_AT_HALF_EN                        "mibcnt_mibhe"
+#define MIB_CNT_MIB_AT_HALF_EN_BOFFSET        16
+#define MIB_CNT_MIB_AT_HALF_EN_BLEN           1
+#define MIB_CNT_MIB_AT_HALF_EN_FLAG           HSL_RW
+
+#define MIB_TIMER                             "mibcnt_mibt"
+#define MIB_CNT_MIB_TIMER_BOFFSET             0
+#define MIB_CNT_MIB_TIMER_BLEN                16
+#define MIB_CNT_MIB_TIMER_FLAG                HSL_RW
+
+    /**
+      * SPI Interface Register
+      */
+#define SPI_INTERFACE             "spi"
+#define SPI_INTERFACE_ID          22
+#define SPI_INTERFACE_OFFSET      0x0090
+#define SPI_INTERFACE_E_LENGTH    4
+#define SPI_INTERFACE_E_OFFSET    0
+#define SPI_INTERFACE_NR_E        0
+
+#define DEBUG_OEN                               "spi_dben"
+#define SPI_INTERFACE_DEBUG_OEN_BOFFSET       7
+#define SPI_INTERFACE_DEBUG_OEN_BLEN          25
+#define SPI_INTERFACE_DEBUG_OEN_FLAG          HSL_RO
+
+#define SPI_EN                                "spi_spien"
+#define SPI_INTERFACE_SPI_EN_BOFFSET          5
+#define SPI_INTERFACE_SPI_EN_BLEN             1
+#define SPI_INTERFACE_SPI_EN_FLAG             HSL_RO
+
+#define SPI_SPEED                             "spi_spisp"
+#define SPI_INTERFACE_SPI_SPEED_BOFFSET       4
+#define SPI_INTERFACE_SPI_SPEED_BLEN          1
+#define SPI_INTERFACE_SPI_SPEED_FLAG          HSL_RO
+
+#define UART_SPEED                            "spi_utsp"
+#define SPI_INTERFACE_UART_SPEED_BOFFSET      3
+#define SPI_INTERFACE_UART_SPEED_BLEN         1
+#define SPI_INTERFACE_UART_SPEED_FLAG         HSL_RO
+
+#define RMII_EN                               "spi_rmen"
+#define SPI_INTERFACE_RMII_EN_BOFFSET         2
+#define SPI_INTERFACE_RMII_EN_BLEN            1
+#define SPI_INTERFACE_RMII_EN_FLAG            HSL_RO
+
+#define MII_EN                                "spi_miien"
+#define SPI_INTERFACE_MII_EN_BOFFSET          1
+#define SPI_INTERFACE_MII_EN_BLEN             1
+#define SPI_INTERFACE_MII_EN_FLAG             HSL_RO
+
+#define SPI_SIZE                              "spi_spisz"
+#define SPI_INTERFACE_SPI_SIZE_BOFFSET        0
+#define SPI_INTERFACE_SPI_SIZE_BLEN           1
+#define SPI_INTERFACE_SPI_SIZE_FLAG           HSL_RO
+
+    /**
+      * MDIO High Address Register
+      */
+#define MDIO_HIGH_ADDR            "mdiohd"
+#define MDIO_HIGH_ADDR_ID         23
+#define MDIO_HIGH_ADDR_OFFSET     0x0094
+#define MDIO_HIGH_ADDR_E_LENGTH   4
+#define MDIO_HIGH_ADDR_E_OFFSET   0
+#define MDIO_HIGH_ADDR_NR_E       0
+
+#define MDIO_HA                               "mdiohd_ha"
+#define MDIO_HIGH_ADDR_MDIO_HA_BOFFSET        0
+#define MDIO_HIGH_ADDR_MDIO_HA_BLEN           9
+#define MDIO_HIGH_ADDR_MDIO_HA_FLAG           HSL_RW
+
+    /**
+      * Destination IP Address Register
+      */
+#define DIP_ADDR               "dip"
+#define DIP_ADDR_ID            24
+#define DIP_ADDR_OFFSET        0x0098
+#define DIP_ADDR_E_LENGTH      4
+#define DIP_ADDR_E_OFFSET      0
+#define DIP_ADDR_NR_E          0
+
+#define DES_IP_ADDR                           "dip_addr"
+#define DIP_ADDR_DES_IP_ADDR_BOFFSET          0
+#define DIP_ADDR_DES_IP_ADDR_BLEN             32
+#define DIP_ADDR_DES_IP_ADDR_FLAG             HSL_RW
+
+    /**
+      * BIST Control Register
+      */
+#define BIST_CTL                  "bctl"
+#define BIST_CTL_ID               25
+#define BIST_CTL_OFFSET           0x00A0
+#define BIST_CTL_E_LENGTH         4
+#define BIST_CTL_E_OFFSET         0
+#define BIST_CTL_NR_E             0
+
+#define BIST_BUSY                             "bctl_busy"
+#define BIST_CTL_BIST_BUSY_BOFFSET            31
+#define BIST_CTL_BIST_BUSY_BLEN               1
+#define BIST_CTL_BIST_BUSY_FLAG               HSL_RW
+
+#define BIST_ERR_MEM                          "bctl_errmem"
+#define BIST_CTL_BIST_ERR_MEM_BOFFSET         24
+#define BIST_CTL_BIST_ERR_MEM_BLEN            4
+#define BIST_CTL_BIST_ERR_MEM_FLAG            HSL_RO
+
+#define BIST_PTN_EN_2                         "bctl_ptnen2"
+#define BIST_CTL_BIST_PTN_EN_2_BOFFSET        22
+#define BIST_CTL_BIST_PTN_EN_2_BLEN           1
+#define BIST_CTL_BIST_PTN_EN_2_FLAG           HSL_RW
+
+#define BIST_PTN_EN_1                         "bctl_ptnen1"
+#define BIST_CTL_BIST_PTN_EN_1_BOFFSET        21
+#define BIST_CTL_BIST_PTN_EN_1_BLEN           1
+#define BIST_CTL_BIST_PTN_EN_1_FLAG           HSL_RW
+
+#define BIST_PTN_EN_0                         "bctl_ptnen0"
+#define BIST_CTL_BIST_PTN_EN_0_BOFFSET        20
+#define BIST_CTL_BIST_PTN_EN_0_BLEN           1
+#define BIST_CTL_BIST_PTN_EN_0_FLAG           HSL_RW
+
+#define BIST_ERR_PTN                          "bctl_errptn"
+#define BIST_CTL_BIST_ERR_PTN_BOFFSET         16
+#define BIST_CTL_BIST_ERR_PTN_BLEN            2
+#define BIST_CTL_BIST_ERR_PTN_FLAG            HSL_RO
+
+#define BIST_ERR_CNT                          "bctl_errcnt"
+#define BIST_CTL_BIST_ERR_CNT_BOFFSET         13
+#define BIST_CTL_BIST_ERR_CNT_BLEN            3
+#define BIST_CTL_BIST_ERR_CNT_FLAG            HSL_RO
+
+#define BIST_ERR_ADDR                         "bctl_errad"
+#define BIST_CTL_BIST_ERR_ADDR_BOFFSET        0
+#define BIST_CTL_BIST_ERR_ADDR_BLEN           13
+#define BIST_CTL_BIST_ERR_ADDR_FLAG           HSL_RO
+
+    /**
+      * Debug Control Register
+      */
+#define DEBUG_CTL0                 "dctl0"
+#define DEBUG_CTL0_ID              26
+#define DEBUG_CTL0_OFFSET          0x00F0
+#define DEBUG_CTL0_E_LENGTH        4
+#define DEBUG_CTL0_E_OFFSET        0
+#define DEBUG_CTL0_NR_E            0
+
+#define DEBUG_SEL                               "dctl_sel"
+#define DEBUG_CTL0_DEBUG_SEL_BOFFSET          16
+#define DEBUG_CTL0_DEBUG_SEL_BLEN             8
+#define DEBUG_CTL0_DEBUG_SEL_FLAG             HSL_RW
+
+#define DEBUG_PORT_NUM                        "dctl_ptnum"
+#define DEBUG_CTL0_DEBUG_PORT_NUM_BOFFSET     8
+#define DEBUG_CTL0_DEBUG_PORT_NUM_BLEN        4
+#define DEBUG_CTL0_DEBUG_PORT_NUM_FLAG        HSL_RW
+
+#define DEBUG_ADDR                            "dctl_addr"
+#define DEBUG_CTL0_DEBUG_ADDR_BOFFSET         0
+#define DEBUG_CTL0_DEBUG_ADDR_BLEN            8
+#define DEBUG_CTL0_DEBUG_ADDR_FLAG            HSL_RW
+
+
+#define DEBUG_CTL1                 "dctl1"
+#define DEBUG_CTL1_ID              27
+#define DEBUG_CTL1_OFFSET          0x00F4
+#define DEBUG_CTL1_E_LENGTH        4
+#define DEBUG_CTL1_E_OFFSET        0
+#define DEBUG_CTL1_NR_E            0
+
+#define DEBUG_DATA                             "dctl_data"
+#define DEBUG_CTL1_DEBUG_DATA_BOFFSET          0
+#define DEBUG_CTL1_DEBUG_DATA_BLEN             32
+#define DEBUG_CTL1_DEBUG_DATA_FLAG             HSL_RO
+
+    /**
+      * QM Debug Control Register
+      */
+#define QM_DEBUG_CTL              "qmdctl"
+#define QM_DEBUG_CTL_ID           28
+#define QM_DEBUG_CTL_OFFSET       0x00F8
+#define QM_DEBUG_CTL_E_LENGTH     4
+#define QM_DEBUG_CTL_E_OFFSET     0
+#define QM_DEBUG_CTL_NR_E         0
+
+#define QM_DBG_CTRL                             "qmdctl_dbgctl"
+#define QM_DEBUG_CTL_QM_DBG_CTRL_BOFFSET        0
+#define QM_DEBUG_CTL_QM_DBG_CTRL_BLEN           32
+#define QM_DEBUG_CTL_QM_DBG_CTRL_FLAG           HSL_RW
+
+    /**
+      * Port Status Register
+      */
+#define PORT_STATUS               "ptsts"
+#define PORT_STATUS_ID            29
+#define PORT_STATUS_OFFSET        0x0100
+#define PORT_STATUS_E_LENGTH      4
+#define PORT_STATUS_E_OFFSET      0x0100
+#define PORT_STATUS_NR_E          6
+
+#define LINK_ASYN_PAUSE                         "ptsts_lasynp"
+#define PORT_STATUS_LINK_ASYN_PAUSE_BOFFSET     11
+#define PORT_STATUS_LINK_ASYN_PAUSE_BLEN        1
+#define PORT_STATUS_LINK_ASYN_PAUSE_FLAG        HSL_RO
+
+#define LINK_PAUSE                              "ptsts_lpause"
+#define PORT_STATUS_LINK_PAUSE_BOFFSET          10
+#define PORT_STATUS_LINK_PAUSE_BLEN             1
+#define PORT_STATUS_LINK_PAUSE_FLAG             HSL_RO
+
+#define LINK_EN                                 "ptsts_linken"
+#define PORT_STATUS_LINK_EN_BOFFSET             9
+#define PORT_STATUS_LINK_EN_BLEN                1
+#define PORT_STATUS_LINK_EN_FLAG                HSL_RW
+
+#define LINK                                    "ptsts_ptlink"
+#define PORT_STATUS_LINK_BOFFSET                8
+#define PORT_STATUS_LINK_BLEN                   1
+#define PORT_STATUS_LINK_FLAG                   HSL_RO
+
+#define DUPLEX_MODE                             "ptsts_dupmod"
+#define PORT_STATUS_DUPLEX_MODE_BOFFSET         6
+#define PORT_STATUS_DUPLEX_MODE_BLEN            1
+#define PORT_STATUS_DUPLEX_MODE_FLAG            HSL_RW
+
+#define RX_FLOW_EN                              "ptsts_rxfwen"
+#define PORT_STATUS_RX_FLOW_EN_BOFFSET          5
+#define PORT_STATUS_RX_FLOW_EN_BLEN             1
+#define PORT_STATUS_RX_FLOW_EN_FLAG             HSL_RW
+
+#define TX_FLOW_EN                              "ptsts_txfwen"
+#define PORT_STATUS_TX_FLOW_EN_BOFFSET          4
+#define PORT_STATUS_TX_FLOW_EN_BLEN             1
+#define PORT_STATUS_TX_FLOW_EN_FLAG             HSL_RW
+
+#define RXMAC_EN                                "ptsts_rxmacen"
+#define PORT_STATUS_RXMAC_EN_BOFFSET            3
+#define PORT_STATUS_RXMAC_EN_BLEN               1
+#define PORT_STATUS_RXMAC_EN_FLAG               HSL_RW
+
+#define TXMAC_EN                                "ptsts_txmacen"
+#define PORT_STATUS_TXMAC_EN_BOFFSET            2
+#define PORT_STATUS_TXMAC_EN_BLEN               1
+#define PORT_STATUS_TXMAC_EN_FLAG               HSL_RW
+
+#define SPEED_MODE                              "ptsts_speed"
+#define PORT_STATUS_SPEED_MODE_BOFFSET          0
+#define PORT_STATUS_SPEED_MODE_BLEN             2
+#define PORT_STATUS_SPEED_MODE_FLAG             HSL_RW
+
+    /**
+      * Port Control Register
+      */
+#define PORT_CTL                  "pctl"
+#define PORT_CTL_ID               30
+#define PORT_CTL_OFFSET           0x0104
+#define PORT_CTL_E_LENGTH         4
+#define PORT_CTL_E_OFFSET         0x0100
+#define PORT_CTL_NR_E             6
+
+#define ING_MIRROR_EN                             "pctl_ingmiren"
+#define PORT_CTL_ING_MIRROR_EN_BOFFSET          17
+#define PORT_CTL_ING_MIRROR_EN_BLEN             1
+#define PORT_CTL_ING_MIRROR_EN_FLAG             HSL_RW
+
+#define EG_MIRROR_EN                            "pctl_egmiren"
+#define PORT_CTL_EG_MIRROR_EN_BOFFSET           16
+#define PORT_CTL_EG_MIRROR_EN_BLEN              1
+#define PORT_CTL_EG_MIRROR_EN_FLAG              HSL_RW
+
+#define LEARN_EN                                "pctl_learnen"
+#define PORT_CTL_LEARN_EN_BOFFSET               14
+#define PORT_CTL_LEARN_EN_BLEN                  1
+#define PORT_CTL_LEARN_EN_FLAG                  HSL_RW
+
+#define SINGLE_VLAN_EN                          "pctl_svlanen"
+#define PORT_CTL_SINGLE_VLAN_EN_BOFFSET         13
+#define PORT_CTL_SINGLE_VLAN_EN_BLEN            1
+#define PORT_CTL_SINGLE_VLAN_EN_FLAG            HSL_RW
+
+#define MAC_LOOP_BACK                           "pctl_maclp"
+#define PORT_CTL_MAC_LOOP_BACK_BOFFSET          12
+#define PORT_CTL_MAC_LOOP_BACK_BLEN             1
+#define PORT_CTL_MAC_LOOP_BACK_FLAG             HSL_RW
+
+#define HEAD_EN                                 "pctl_headen"
+#define PORT_CTL_HEAD_EN_BOFFSET                11
+#define PORT_CTL_HEAD_EN_BLEN                   1
+#define PORT_CTL_HEAD_EN_FLAG                   HSL_RW
+
+#define IGMP_MLD_EN                             "pctl_imlden"
+#define PORT_CTL_IGMP_MLD_EN_BOFFSET            10
+#define PORT_CTL_IGMP_MLD_EN_BLEN               1
+#define PORT_CTL_IGMP_MLD_EN_FLAG               HSL_RW
+
+#define EG_VLAN_MODE                            "pctl_egvmode"
+#define PORT_CTL_EG_VLAN_MODE_BOFFSET           8
+#define PORT_CTL_EG_VLAN_MODE_BLEN              2
+#define PORT_CTL_EG_VLAN_MODE_FLAG              HSL_RW
+
+#define LEARN_ONE_LOCK                          "pctl_lonelck"
+#define PORT_CTL_LEARN_ONE_LOCK_BOFFSET         7
+#define PORT_CTL_LEARN_ONE_LOCK_BLEN            1
+#define PORT_CTL_LEARN_ONE_LOCK_FLAG            HSL_RW
+
+#define PORT_STATE                              "pctl_pstate"
+#define PORT_CTL_PORT_STATE_BOFFSET             0
+#define PORT_CTL_PORT_STATE_BLEN                3
+#define PORT_CTL_PORT_STATE_FLAG                HSL_RW
+
+    /**
+      * Port Based Vlan Register
+      */
+#define PORT_BASE_VLAN            "pbvlan"
+#define PORT_BASE_VLAN_ID         31
+#define PORT_BASE_VLAN_OFFSET     0x0108
+#define PORT_BASE_VLAN_E_LENGTH   4
+#define PORT_BASE_VLAN_E_OFFSET   0x0100
+#define PORT_BASE_VLAN_NR_E     6
+
+#define DOT1Q_MODE                              "pbvlan_8021q"
+#define PORT_BASE_VLAN_DOT1Q_MODE_BOFFSET       30
+#define PORT_BASE_VLAN_DOT1Q_MODE_BLEN          2
+#define PORT_BASE_VLAN_DOT1Q_MODE_FLAG          HSL_RW
+
+#define ING_PRI                                 "pbvlan_ingpri"
+#define PORT_BASE_VLAN_ING_PRI_BOFFSET          28
+#define PORT_BASE_VLAN_ING_PRI_BLEN             2
+#define PORT_BASE_VLAN_ING_PRI_FLAG             HSL_RW
+
+#define EG_TAG_PRI0                             "pbvlan_egtpri"
+#define PORT_BASE_VLAN_EG_TAG_PRI0_BOFFSET      27
+#define PORT_BASE_VLAN_EG_TAG_PRI0_BLEN         1
+#define PORT_BASE_VLAN_EG_TAG_PRI0_FLAG         HSL_RW
+
+#define PORT_VID_MEM                            "pbvlan_pvidm"
+#define PORT_BASE_VLAN_PORT_VID_MEM_BOFFSET     16
+#define PORT_BASE_VLAN_PORT_VID_MEM_BLEN        6
+#define PORT_BASE_VLAN_PORT_VID_MEM_FLAG        HSL_RW
+
+#define PORT_VID                                "pbvlan_ptvid"
+#define PORT_BASE_VLAN_PORT_VID_BOFFSET         0
+#define PORT_BASE_VLAN_PORT_VID_BLEN            12
+#define PORT_BASE_VLAN_PORT_VID_FLAG            HSL_RW
+
+    /**
+      * Port Rate Limit Register
+      */
+#define RATE_LIMIT                "rlmt"
+#define RATE_LIMIT_ID             32
+#define RATE_LIMIT_OFFSET         0x010C
+#define RATE_LIMIT_E_LENGTH       4
+#define RATE_LIMIT_E_OFFSET       0x0100
+#define RATE_LIMIT_NR_E         6
+
+#define EGRESS_RATE_EN                          "rlmt_egrateen"
+#define RATE_LIMIT_EGRESS_RATE_EN_BOFFSET       25
+#define RATE_LIMIT_EGRESS_RATE_EN_BLEN          1
+#define RATE_LIMIT_EGRESS_RATE_EN_FLAG          HSL_RW
+
+#define INGRESS_RATE_EN                         "rlmt_ingrateen"
+#define RATE_LIMIT_INGRESS_RATE_EN_BOFFSET      24
+#define RATE_LIMIT_INGRESS_RATE_EN_BLEN         1
+#define RATE_LIMIT_INGRESS_RATE_EN_FLAG         HSL_RW
+
+#define EG_RATE                                 "rlmt_egrate"
+#define RATE_LIMIT_EG_RATE_BOFFSET              16
+#define RATE_LIMIT_EG_RATE_BLEN                 4
+#define RATE_LIMIT_EG_RATE_FLAG                 HSL_RW
+
+#define ING_RATE                                "rlmt_ingrate"
+#define RATE_LIMIT_ING_RATE_BOFFSET             0
+#define RATE_LIMIT_ING_RATE_BLEN                4
+#define RATE_LIMIT_ING_RATE_FLAG                HSL_RW
+
+    /**
+      * Priority Control Register
+      */
+#define PRI_CTL                   "prctl"
+#define PRI_CTL_ID                33
+#define PRI_CTL_OFFSET            0x0110
+#define PRI_CTL_E_LENGTH          4
+#define PRI_CTL_E_OFFSET          0x0100
+#define PRI_CTL_NR_E              6
+
+#define PORT_PRI_EN                             "prctl_ptprien"
+#define PRI_CTL_PORT_PRI_EN_BOFFSET             19
+#define PRI_CTL_PORT_PRI_EN_BLEN                1
+#define PRI_CTL_PORT_PRI_EN_FLAG                HSL_RW
+
+#define DA_PRI_EN                               "prctl_daprien"
+#define PRI_CTL_DA_PRI_EN_BOFFSET               18
+#define PRI_CTL_DA_PRI_EN_BLEN                  1
+#define PRI_CTL_DA_PRI_EN_FLAG                  HSL_RW
+
+#define VLAN_PRI_EN                             "prctl_vprien"
+#define PRI_CTL_VLAN_PRI_EN_BOFFSET             17
+#define PRI_CTL_VLAN_PRI_EN_BLEN                1
+#define PRI_CTL_VLAN_PRI_EN_FLAG                HSL_RW
+
+#define IP_PRI_EN                               "prctl_ipprien"
+#define PRI_CTL_IP_PRI_EN_BOFFSET               16
+#define PRI_CTL_IP_PRI_EN_BLEN                  1
+#define PRI_CTL_IP_PRI_EN_FLAG                  HSL_RW
+
+#define DA_PRI_SEL                              "prctl_dapris"
+#define PRI_CTL_DA_PRI_SEL_BOFFSET              6
+#define PRI_CTL_DA_PRI_SEL_BLEN                 2
+#define PRI_CTL_DA_PRI_SEL_FLAG                 HSL_RW
+
+#define VLAN_PRI_SEL                            "prctl_vpris"
+#define PRI_CTL_VLAN_PRI_SEL_BOFFSET            4
+#define PRI_CTL_VLAN_PRI_SEL_BLEN               2
+#define PRI_CTL_VLAN_PRI_SEL_FLAG               HSL_RW
+
+#define IP_PRI_SEL                              "prctl_ippris"
+#define PRI_CTL_IP_PRI_SEL_BOFFSET              2
+#define PRI_CTL_IP_PRI_SEL_BLEN                 2
+#define PRI_CTL_IP_PRI_SEL_FLAG                 HSL_RW
+
+#define PORT_PRI_SEL                            "prctl_ptpris"
+#define PRI_CTL_PORT_PRI_SEL_BOFFSET            0
+#define PRI_CTL_PORT_PRI_SEL_BLEN               2
+#define PRI_CTL_PORT_PRI_SEL_FLAG               HSL_RW
+
+
+//mib memory info
+#define MIB_RXBROAD                       "RxBroad"
+#define MIB_RXBROAD_ID                    34
+#define MIB_RXBROAD_OFFSET                0x19000
+#define MIB_RXBROAD_E_LENGTH              4
+#define MIB_RXBROAD_E_OFFSET              0xa0
+#define MIB_RXBROAD_NR_E                  6
+
+#define MIB_RXPAUSE                       "RxPause"
+#define MIB_RXPAUSE_ID                    35
+#define MIB_RXPAUSE_OFFSET                0x19004
+#define MIB_RXPAUSE_E_LENGTH              4
+#define MIB_RXPAUSE_E_OFFSET              0xa0
+#define MIB_RXPAUSE_NR_E                  6
+
+#define MIB_RXMULTI                       "RxMulti"
+#define MIB_RXMULTI_ID                    36
+#define MIB_RXMULTI_OFFSET                0x19008
+#define MIB_RXMULTI_E_LENGTH              4
+#define MIB_RXMULTI_E_OFFSET              0xa0
+#define MIB_RXMULTI_NR_E                  6
+
+#define MIB_RXFCSERR                      "RxFcsErr"
+#define MIB_RXFCSERR_ID                   37
+#define MIB_RXFCSERR_OFFSET               0x1900C
+#define MIB_RXFCSERR_E_LENGTH             4
+#define MIB_RXFCSERR_E_OFFSET             0xa0
+#define MIB_RXFCSERR_NR_E                 6
+
+#define MIB_RXALLIGNERR                   "RxAllignErr"
+#define MIB_RXALLIGNERR_ID                38
+#define MIB_RXALLIGNERR_OFFSET            0x19010
+#define MIB_RXALLIGNERR_E_LENGTH          4
+#define MIB_RXALLIGNERR_E_OFFSET          0xa0
+#define MIB_RXALLIGNERR_NR_E              6
+
+#define MIB_RXRUNT                        "RxRunt"
+#define MIB_RXRUNT_ID                     39
+#define MIB_RXRUNT_OFFSET                 0x19014
+#define MIB_RXRUNT_E_LENGTH               4
+#define MIB_RXRUNT_E_OFFSET               0xa0
+#define MIB_RXRUNT_NR_E                   6
+
+#define MIB_RXFRAGMENT                    "RxFragment"
+#define MIB_RXFRAGMENT_ID                 40
+#define MIB_RXFRAGMENT_OFFSET             0x19018
+#define MIB_RXFRAGMENT_E_LENGTH           4
+#define MIB_RXFRAGMENT_E_OFFSET           0xa0
+#define MIB_RXFRAGMENT_NR_E               6
+
+#define MIB_RX64BYTE                      "Rx64Byte"
+#define MIB_RX64BYTE_ID                   41
+#define MIB_RX64BYTE_OFFSET               0x1901C
+#define MIB_RX64BYTE_E_LENGTH             4
+#define MIB_RX64BYTE_E_OFFSET             0xa0
+#define MIB_RX64BYTE_NR_E                 6
+
+#define MIB_RX128BYTE                     "Rx128Byte"
+#define MIB_RX128BYTE_ID                  42
+#define MIB_RX128BYTE_OFFSET              0x19020
+#define MIB_RX128BYTE_E_LENGTH            4
+#define MIB_RX128BYTE_E_OFFSET            0xa0
+#define MIB_RX128BYTE_NR_E                6
+
+#define MIB_RX256BYTE                     "Rx256Byte"
+#define MIB_RX256BYTE_ID                  43
+#define MIB_RX256BYTE_OFFSET              0x19024
+#define MIB_RX256BYTE_E_LENGTH            4
+#define MIB_RX256BYTE_E_OFFSET            0xa0
+#define MIB_RX256BYTE_NR_E                6
+
+#define MIB_RX512BYTE                     "Rx512Byte"
+#define MIB_RX512BYTE_ID                  44
+#define MIB_RX512BYTE_OFFSET              0x19028
+#define MIB_RX512BYTE_E_LENGTH            4
+#define MIB_RX512BYTE_E_OFFSET            0xa0
+#define MIB_RX512BYTE_NR_E                6
+
+#define MIB_RX1024BYTE                    "Rx1024Byte"
+#define MIB_RX1024BYTE_ID                 45
+#define MIB_RX1024BYTE_OFFSET             0x1902C
+#define MIB_RX1024BYTE_E_LENGTH           4
+#define MIB_RX1024BYTE_E_OFFSET           0xa0
+#define MIB_RX1024BYTE_NR_E               6
+
+#define MIB_RX1518BYTE                    "Rx1518Byte"  //reserved for s16 
+
+#define MIB_RXMAXBYTE                     "RxMaxByte"
+#define MIB_RXMAXBYTE_ID                  46
+#define MIB_RXMAXBYTE_OFFSET              0x19030
+#define MIB_RXMAXBYTE_E_LENGTH            4
+#define MIB_RXMAXBYTE_E_OFFSET            0xa0
+#define MIB_RXMAXBYTE_NR_E                6
+
+#define MIB_RXTOOLONG                     "RxTooLong"
+#define MIB_RXTOOLONG_ID                  47
+#define MIB_RXTOOLONG_OFFSET              0x19034
+#define MIB_RXTOOLONG_E_LENGTH            4
+#define MIB_RXTOOLONG_E_OFFSET            0xa0
+#define MIB_RXTOOLONG_NR_E                6
+
+#define MIB_RXGOODBYTE_LO                 "RxGoodByteLo"
+#define MIB_RXGOODBYTE_LO_ID              48
+#define MIB_RXGOODBYTE_LO_OFFSET          0x19038
+#define MIB_RXGOODBYTE_LO_E_LENGTH        4
+#define MIB_RXGOODBYTE_LO_E_OFFSET        0xa0
+#define MIB_RXGOODBYTE_LO_NR_E            6
+
+#define MIB_RXGOODBYTE_HI                 "RxGoodByteHi"
+#define MIB_RXGOODBYTE_HI_ID              49
+#define MIB_RXGOODBYTE_HI_OFFSET          0x1903C
+#define MIB_RXGOODBYTE_HI_E_LENGTH        4
+#define MIB_RXGOODBYTE_HI_E_OFFSET        0xa0
+#define MIB_RXGOODBYTE_HI_NR_E            6
+
+#define MIB_RXBADBYTE_LO                  "RxBadByteLo"
+#define MIB_RXBADBYTE_LO_ID               50
+#define MIB_RXBADBYTE_LO_OFFSET           0x19040
+#define MIB_RXBADBYTE_LO_E_LENGTH         4
+#define MIB_RXBADBYTE_LO_E_OFFSET         0xa0
+#define MIB_RXBADBYTE_LO_NR_E             6
+
+#define MIB_RXBADBYTE_HI                  "RxBadByteHi"
+#define MIB_RXBADBYTE_HI_ID               51
+#define MIB_RXBADBYTE_HI_OFFSET           0x19044
+#define MIB_RXBADBYTE_HI_E_LENGTH         4
+#define MIB_RXBADBYTE_HI_E_OFFSET         0xa0
+#define MIB_RXBADBYTE_HI_NR_E             6
+
+#define MIB_RXOVERFLOW                    "RxOverFlow"
+#define MIB_RXOVERFLOW_ID                 52
+#define MIB_RXOVERFLOW_OFFSET             0x19048
+#define MIB_RXOVERFLOW_E_LENGTH           4
+#define MIB_RXOVERFLOW_E_OFFSET           0xa0
+#define MIB_RXOVERFLOW_NR_E               6
+
+#define MIB_FILTERED                      "Filtered"
+#define MIB_FILTERED_ID                   53
+#define MIB_FILTERED_OFFSET               0x1904C
+#define MIB_FILTERED_E_LENGTH             4
+#define MIB_FILTERED_E_OFFSET             0xa0
+#define MIB_FILTERED_NR_E                 6
+
+#define MIB_TXBROAD                       "TxBroad"
+#define MIB_TXBROAD_ID                    54
+#define MIB_TXBROAD_OFFSET                0x19050
+#define MIB_TXBROAD_E_LENGTH              4
+#define MIB_TXBROAD_E_OFFSET              0xa0
+#define MIB_TXBROAD_NR_E                  6
+
+#define MIB_TXPAUSE                       "TxPause"
+#define MIB_TXPAUSE_ID                    55
+#define MIB_TXPAUSE_OFFSET                0x19054
+#define MIB_TXPAUSE_E_LENGTH              4
+#define MIB_TXPAUSE_E_OFFSET              0xa0
+#define MIB_TXPAUSE_NR_E                  6
+
+#define MIB_TXMULTI                       "TxMulti"
+#define MIB_TXMULTI_ID                    56
+#define MIB_TXMULTI_OFFSET                0x19058
+#define MIB_TXMULTI_E_LENGTH              4
+#define MIB_TXMULTI_E_OFFSET              0xa0
+#define MIB_TXMULTI_NR_E                  6
+
+#define MIB_TXUNDERRUN                    "TxUnderRun"
+#define MIB_TXUNDERRUN_ID                 57
+#define MIB_TXUNDERRUN_OFFSET             0x1905C
+#define MIB_TXUNDERRUN_E_LENGTH           4
+#define MIB_TXUNDERRUN_E_OFFSET           0xa0
+#define MIB_TXUNDERRUN_NR_E               6
+
+#define MIB_TX64BYTE                      "Tx64Byte"
+#define MIB_TX64BYTE_ID                   58
+#define MIB_TX64BYTE_OFFSET               0x19060
+#define MIB_TX64BYTE_E_LENGTH             4
+#define MIB_TX64BYTE_E_OFFSET             0xa0
+#define MIB_TX64BYTE_NR_E                 6
+
+#define MIB_TX128BYTE                     "Tx128Byte"
+#define MIB_TX128BYTE_ID                  59
+#define MIB_TX128BYTE_OFFSET              0x19064
+#define MIB_TX128BYTE_E_LENGTH            4
+#define MIB_TX128BYTE_E_OFFSET            0xa0
+#define MIB_TX128BYTE_NR_E                6
+
+#define MIB_TX256BYTE                     "Tx256Byte"
+#define MIB_TX256BYTE_ID                  60
+#define MIB_TX256BYTE_OFFSET              0x19068
+#define MIB_TX256BYTE_E_LENGTH            4
+#define MIB_TX256BYTE_E_OFFSET            0xa0
+#define MIB_TX256BYTE_NR_E                6
+
+#define MIB_TX512BYTE                     "Tx512Byte"
+#define MIB_TX512BYTE_ID                  61
+#define MIB_TX512BYTE_OFFSET              0x1906C
+#define MIB_TX512BYTE_E_LENGTH            4
+#define MIB_TX512BYTE_E_OFFSET            0xa0
+#define MIB_TX512BYTE_NR_E                6
+
+#define MIB_TX1024BYTE                    "Tx1024Byte"
+#define MIB_TX1024BYTE_ID                 62
+#define MIB_TX1024BYTE_OFFSET             0x19070
+#define MIB_TX1024BYTE_E_LENGTH           4
+#define MIB_TX1024BYTE_E_OFFSET           0xa0
+#define MIB_TX1024BYTE_NR_E               6
+
+#define MIB_TX1518BYTE                    "Tx1518Byte"  //reserved for s16 
+
+#define MIB_TXMAXBYTE                     "TxMaxByte"
+#define MIB_TXMAXBYTE_ID                  63
+#define MIB_TXMAXBYTE_OFFSET              0x19074
+#define MIB_TXMAXBYTE_E_LENGTH            4
+#define MIB_TXMAXBYTE_E_OFFSET            0xa0
+#define MIB_TXMAXBYTE_NR_E                6
+
+#define MIB_TXOVERSIZE                    "TxOverSize"
+#define MIB_TXOVERSIZE_ID                 64
+#define MIB_TXOVERSIZE_OFFSET             0x19078
+#define MIB_TXOVERSIZE_E_LENGTH           4
+#define MIB_TXOVERSIZE_E_OFFSET           0xa0
+#define MIB_TXOVERSIZE_NR_E              6
+
+#define MIB_TXBYTE_LO                     "TxByteLo"
+#define MIB_TXBYTE_LO_ID                  65
+#define MIB_TXBYTE_LO_OFFSET              0x1907C
+#define MIB_TXBYTE_LO_E_LENGTH            4
+#define MIB_TXBYTE_LO_E_OFFSET            0xa0
+#define MIB_TXBYTE_LO_NR_E                6
+
+#define MIB_TXBYTE_HI                     "TxByteHi"
+#define MIB_TXBYTE_HI_ID                  66
+#define MIB_TXBYTE_HI_OFFSET              0x19080
+#define MIB_TXBYTE_HI_E_LENGTH            4
+#define MIB_TXBYTE_HI_E_OFFSET            0xa0
+#define MIB_TXBYTE_HI_NR_E                6
+
+#define MIB_TXCOLLISION                   "TxCollision"
+#define MIB_TXCOLLISION_ID                67
+#define MIB_TXCOLLISION_OFFSET            0x19084
+#define MIB_TXCOLLISION_E_LENGTH          4
+#define MIB_TXCOLLISION_E_OFFSET          0xa0
+#define MIB_TXCOLLISION_NR_E              6
+
+#define MIB_TXABORTCOL                    "TxAbortCol"
+#define MIB_TXABORTCOL_ID                 68
+#define MIB_TXABORTCOL_OFFSET             0x19088
+#define MIB_TXABORTCOL_E_LENGTH           4
+#define MIB_TXABORTCOL_E_OFFSET           0xa0
+#define MIB_TXABORTCOL_NR_E               6
+
+#define MIB_TXMULTICOL                    "TxMultiCol"
+#define MIB_TXMULTICOL_ID                 69
+#define MIB_TXMULTICOL_OFFSET             0x1908C
+#define MIB_TXMULTICOL_E_LENGTH           4
+#define MIB_TXMULTICOL_E_OFFSET           0xa0
+#define MIB_TXMULTICOL_NR_E               6
+
+#define MIB_TXSINGALCOL                   "TxSingalCol"
+#define MIB_TXSINGALCOL_ID                70
+#define MIB_TXSINGALCOL_OFFSET            0x19090
+#define MIB_TXSINGALCOL_E_LENGTH          4
+#define MIB_TXSINGALCOL_E_OFFSET          0xa0
+#define MIB_TXSINGALCOL_NR_E              6
+
+#define MIB_TXEXCDEFER                    "TxExcDefer"
+#define MIB_TXEXCDEFER_ID                 71
+#define MIB_TXEXCDEFER_OFFSET             0x19094
+#define MIB_TXEXCDEFER_E_LENGTH           4
+#define MIB_TXEXCDEFER_E_OFFSET           0xa0
+#define MIB_TXEXCDEFER_NR_E               6
+
+#define MIB_TXDEFER                       "TxDefer"
+#define MIB_TXDEFER_ID                    72
+#define MIB_TXDEFER_OFFSET                0x19098
+#define MIB_TXDEFER_E_LENGTH              4
+#define MIB_TXDEFER_E_OFFSET              0xa0
+#define MIB_TXDEFER_NR_E                  6
+
+#define MIB_TXLATECOL                     "TxLateCol"
+#define MIB_TXLATECOL_ID                  73
+#define MIB_TXLATECOL_OFFSET              0x1909C
+#define MIB_TXLATECOL_E_LENGTH            4
+#define MIB_TXLATECOL_E_OFFSET            0xa0
+#define MIB_TXLATECOL_NR_E                6
+
+//second mem block
+#define MIB_RXBROAD_2                     "RxBroad_2"
+#define MIB_RXBROAD_2_ID                  34
+#define MIB_RXBROAD_2_OFFSET              (MIB_RXBROAD_OFFSET + 0x400)
+#define MIB_RXBROAD_2_E_LENGTH            4
+#define MIB_RXBROAD_2_E_OFFSET            0xa0
+#define MIB_RXBROAD_2_NR_E                6
+
+#define MIB_RXPAUSE_2                     "RxPause_2"
+#define MIB_RXPAUSE_2_ID                  35
+#define MIB_RXPAUSE_2_OFFSET              (MIB_RXPAUSE_OFFSET + 0x400)
+#define MIB_RXPAUSE_2_E_LENGTH            4
+#define MIB_RXPAUSE_2_E_OFFSET            0xa0
+#define MIB_RXPAUSE_2_NR_E                6
+
+#define MIB_RXMULTI_2                     "RxMulti_2"
+#define MIB_RXMULTI_2_ID                  36
+#define MIB_RXMULTI_2_OFFSET              (MIB_RXMULTI_OFFSET + 0x400)
+#define MIB_RXMULTI_2_E_LENGTH            4
+#define MIB_RXMULTI_2_E_OFFSET            0xa0
+#define MIB_RXMULTI_2_NR_E                6
+
+#define MIB_RXFCSERR_2                    "RxFcsErr_2"
+#define MIB_RXFCSERR_2_ID                 37
+#define MIB_RXFCSERR_2_OFFSET             (MIB_RXFCSERR_OFFSET + 0x400)
+#define MIB_RXFCSERR_2_E_LENGTH           4
+#define MIB_RXFCSERR_2_E_OFFSET           0xa0
+#define MIB_RXFCSERR_2_NR_E               6
+
+#define MIB_RXALLIGNERR_2                 "RxAllignErr_2"
+#define MIB_RXALLIGNERR_2_ID              38
+#define MIB_RXALLIGNERR_2_OFFSET          (MIB_RXALLIGNERR_OFFSET + 0x400)
+#define MIB_RXALLIGNERR_2_E_LENGTH        4
+#define MIB_RXALLIGNERR_2_E_OFFSET        0xa0
+#define MIB_RXALLIGNERR_2_NR_E            6
+
+#define MIB_RXRUNT_2                      "RxRunt_2"
+#define MIB_RXRUNT_2_ID                   39
+#define MIB_RXRUNT_2_OFFSET               (MIB_RXRUNT_OFFSET + 0x400)
+#define MIB_RXRUNT_2_E_LENGTH             4
+#define MIB_RXRUNT_2_E_OFFSET             0xa0
+#define MIB_RXRUNT_2_NR_E                 6
+
+#define MIB_RXFRAGMENT_2                  "RxFragment_2"
+#define MIB_RXFRAGMENT_2_ID               40
+#define MIB_RXFRAGMENT_2_OFFSET           (MIB_RXFRAGMENT_OFFSET + 0x400)
+#define MIB_RXFRAGMENT_2_E_LENGTH         4
+#define MIB_RXFRAGMENT_2_E_OFFSET         0xa0
+#define MIB_RXFRAGMENT_2_NR_E             6
+
+#define MIB_RX64BYTE_2                    "Rx64Byte_2"
+#define MIB_RX64BYTE_2_ID                 41
+#define MIB_RX64BYTE_2_OFFSET             (MIB_RX64BYTE_OFFSET + 0x400)
+#define MIB_RX64BYTE_2_E_LENGTH           4
+#define MIB_RX64BYTE_2_E_OFFSET           0xa0
+#define MIB_RX64BYTE_2_NR_E               6
+
+#define MIB_RX128BYTE_2                   "Rx128Byte_2"
+#define MIB_RX128BYTE_2_ID                42
+#define MIB_RX128BYTE_2_OFFSET            (MIB_RX128BYTE_OFFSET + 0x400)
+#define MIB_RX128BYTE_2_E_LENGTH          4
+#define MIB_RX128BYTE_2_E_OFFSET          0xa0
+#define MIB_RX128BYTE_2_NR_E              6
+
+#define MIB_RX256BYTE_2                   "Rx256Byte_2"
+#define MIB_RX256BYTE_2_ID                43
+#define MIB_RX256BYTE_2_OFFSET            (MIB_RX256BYTE_OFFSET + 0x400)
+#define MIB_RX256BYTE_2_E_LENGTH          4
+#define MIB_RX256BYTE_2_E_OFFSET          0xa0
+#define MIB_RX256BYTE_2_NR_E              6
+
+#define MIB_RX512BYTE_2                   "Rx512Byte_2"
+#define MIB_RX512BYTE_2_ID                44
+#define MIB_RX512BYTE_2_OFFSET            (MIB_RX512BYTE_OFFSET + 0x400)
+#define MIB_RX512BYTE_2_E_LENGTH          4
+#define MIB_RX512BYTE_2_E_OFFSET          0xa0
+#define MIB_RX512BYTE_2_NR_E              6
+
+#define MIB_RX1024BYTE_2                  "Rx1024Byte_2"
+#define MIB_RX1024BYTE_2_ID               45
+#define MIB_RX1024BYTE_2_OFFSET           (MIB_RX1024BYTE_OFFSET + 0x400)
+#define MIB_RX1024BYTE_2_E_LENGTH         4
+#define MIB_RX1024BYTE_2_E_OFFSET         0xa0
+#define MIB_RX1024BYTE_2_NR_E             6
+
+#define MIB_RXMAXBYTE_2                   "RxMaxByte_2"
+#define MIB_RXMAXBYTE_2_ID                46
+#define MIB_RXMAXBYTE_2_OFFSET            (MIB_RXMAXBYTE_OFFSET + 0x400)
+#define MIB_RXMAXBYTE_2_E_LENGTH          4
+#define MIB_RXMAXBYTE_2_E_OFFSET          0xa0
+#define MIB_RXMAXBYTE_2_NR_E              6
+
+#define MIB_RXTOOLONG_2                   "RxTooLong_2"
+#define MIB_RXTOOLONG_2_ID                47
+#define MIB_RXTOOLONG_2_OFFSET            (MIB_RXTOOLONG_OFFSET + 0x400)
+#define MIB_RXTOOLONG_2_E_LENGTH          4
+#define MIB_RXTOOLONG_2_E_OFFSET          0xa0
+#define MIB_RXTOOLONG_2_NR_E             6
+
+#define MIB_RXGOODBYTE_LO_2               "RxGoodByteLo_2"
+#define MIB_RXGOODBYTE_LO_2_ID            48
+#define MIB_RXGOODBYTE_LO_2_OFFSET        (MIB_RXGOODBYTE_LO_OFFSET + 0x400)
+#define MIB_RXGOODBYTE_LO_2_E_LENGTH      4
+#define MIB_RXGOODBYTE_LO_2_E_OFFSET      0xa0
+#define MIB_RXGOODBYTE_LO_2_NR_E          6
+
+#define MIB_RXGOODBYTE_HI_2               "RxGoodByteHi_2"
+#define MIB_RXGOODBYTE_HI_2_ID            49
+#define MIB_RXGOODBYTE_HI_2_OFFSET        (MIB_RXGOODBYTE_HI_OFFSET + 0x400)
+#define MIB_RXGOODBYTE_HI_2_E_LENGTH      4
+#define MIB_RXGOODBYTE_HI_2_E_OFFSET      0xa0
+#define MIB_RXGOODBYTE_HI_2_NR_E          6
+
+#define MIB_RXBADBYTE_LO_2                "RxBadByteLo_2"
+#define MIB_RXBADBYTE_LO_2_ID             50
+#define MIB_RXBADBYTE_LO_2_OFFSET         (MIB_RXBADBYTE_LO_OFFSET + 0x400)
+#define MIB_RXBADBYTE_LO_2_E_LENGTH       4
+#define MIB_RXBADBYTE_LO_2_E_OFFSET       0xa0
+#define MIB_RXBADBYTE_LO_2_NR_E           6
+
+#define MIB_RXBADBYTE_HI_2                "RxBadByteHi_2"
+#define MIB_RXBADBYTE_HI_2_ID             51
+#define MIB_RXBADBYTE_HI_2_OFFSET         (MIB_RXBADBYTE_HI_OFFSET + 0x400)
+#define MIB_RXBADBYTE_HI_2_E_LENGTH       4
+#define MIB_RXBADBYTE_HI_2_E_OFFSET       0xa0
+#define MIB_RXBADBYTE_HI_2_NR_E           6
+
+#define MIB_RXOVERFLOW_2                  "RxOverFlow_2"
+#define MIB_RXOVERFLOW_2_ID               52
+#define MIB_RXOVERFLOW_2_OFFSET           (MIB_RXOVERFLOW_OFFSET + 0x400)
+#define MIB_RXOVERFLOW_2_E_LENGTH         4
+#define MIB_RXOVERFLOW_2_E_OFFSET         0xa0
+#define MIB_RXOVERFLOW_2_NR_E             6
+
+#define MIB_FILTERED_2                    "Filtered_2"
+#define MIB_FILTERED_2_ID                 53
+#define MIB_FILTERED_2_OFFSET             (MIB_FILTERED_OFFSET + 0x400)
+#define MIB_FILTERED_2_E_LENGTH           4
+#define MIB_FILTERED_2_E_OFFSET           0xa0
+#define MIB_FILTERED_2_NR_E               6
+
+#define MIB_TXBROAD_2                     "TxBroad_2"
+#define MIB_TXBROAD_2_ID                  54
+#define MIB_TXBROAD_2_OFFSET              (MIB_TXBROAD_OFFSET + 0x400)
+#define MIB_TXBROAD_2_E_LENGTH            4
+#define MIB_TXBROAD_2_E_OFFSET            0xa0
+#define MIB_TXBROAD_2_NR_E                6
+
+#define MIB_TXPAUSE_2                     "TxPause_2"
+#define MIB_TXPAUSE_2_ID                  55
+#define MIB_TXPAUSE_2_OFFSET              (MIB_TXPAUSE_OFFSET + 0x400)
+#define MIB_TXPAUSE_2_E_LENGTH            4
+#define MIB_TXPAUSE_2_E_OFFSET            0xa0
+#define MIB_TXPAUSE_2_NR_E                6
+
+#define MIB_TXMULTI_2                     "TxMulti_2"
+#define MIB_TXMULTI_2_ID                  56
+#define MIB_TXMULTI_2_OFFSET              (MIB_TXMULTI_OFFSET + 0x400)
+#define MIB_TXMULTI_2_E_LENGTH            4
+#define MIB_TXMULTI_2_E_OFFSET            0xa0
+#define MIB_TXMULTI_2_NR_E                6
+
+#define MIB_TXUNDERRUN_2                  "TxUnderRun_2"
+#define MIB_TXUNDERRUN_2_ID               57
+#define MIB_TXUNDERRUN_2_OFFSET           (MIB_TXUNDERRUN_OFFSET + 0x400)
+#define MIB_TXUNDERRUN_2_E_LENGTH         4
+#define MIB_TXUNDERRUN_2_E_OFFSET         0xa0
+#define MIB_TXUNDERRUN_2_NR_E             6
+
+#define MIB_TX64BYTE_2                    "Tx64Byte_2"
+#define MIB_TX64BYTE_2_ID                 58
+#define MIB_TX64BYTE_2_OFFSET             (MIB_TX64BYTE_OFFSET + 0x400)
+#define MIB_TX64BYTE_2_E_LENGTH           4
+#define MIB_TX64BYTE_2_E_OFFSET           0xa0
+#define MIB_TX64BYTE_2_NR_E               6
+
+#define MIB_TX128BYTE_2                   "Tx128Byte_2"
+#define MIB_TX128BYTE_2_ID                59
+#define MIB_TX128BYTE_2_OFFSET            (MIB_TX128BYTE_OFFSET + 0x400)
+#define MIB_TX128BYTE_2_E_LENGTH          4
+#define MIB_TX128BYTE_2_E_OFFSET          0xa0
+#define MIB_TX128BYTE_2_NR_E              6
+
+#define MIB_TX256BYTE_2                   "Tx256Byte_2"
+#define MIB_TX256BYTE_2_ID                60
+#define MIB_TX256BYTE_2_OFFSET            (MIB_TX256BYTE_OFFSET + 0x400)
+#define MIB_TX256BYTE_2_E_LENGTH          4
+#define MIB_TX256BYTE_2_E_OFFSET          0xa0
+#define MIB_TX256BYTE_2_NR_E              6
+
+#define MIB_TX512BYTE_2                   "Tx512Byte_2"
+#define MIB_TX512BYTE_2_ID                61
+#define MIB_TX512BYTE_2_OFFSET            (MIB_TX512BYTE_OFFSET + 0x400)
+#define MIB_TX512BYTE_2_E_LENGTH          4
+#define MIB_TX512BYTE_2_E_OFFSET          0xa0
+#define MIB_TX512BYTE_2_NR_E              6
+
+#define MIB_TX1024BYTE_2                  "Tx1024Byte_2"
+#define MIB_TX1024BYTE_2_ID               62
+#define MIB_TX1024BYTE_2_OFFSET           (MIB_TX1024BYTE_OFFSET + 0x400)
+#define MIB_TX1024BYTE_2_E_LENGTH         4
+#define MIB_TX1024BYTE_2_E_OFFSET         0xa0
+#define MIB_TX1024BYTE_2_NR_E             6
+
+#define MIB_TXMAXBYTE_2                   "TxMaxByte_2"
+#define MIB_TXMAXBYTE_2_ID                63
+#define MIB_TXMAXBYTE_2_OFFSET            (MIB_TXMAXBYTE_OFFSET + 0x400)
+#define MIB_TXMAXBYTE_2_E_LENGTH          4
+#define MIB_TXMAXBYTE_2_E_OFFSET          0xa0
+#define MIB_TXMAXBYTE_2_NR_E              6
+
+#define MIB_TXOVERSIZE_2                  "TxOverSize_2"
+#define MIB_TXOVERSIZE_2_ID               64
+#define MIB_TXOVERSIZE_2_OFFSET           (MIB_TXOVERSIZE_OFFSET + 0x400)
+#define MIB_TXOVERSIZE_2_E_LENGTH         4
+#define MIB_TXOVERSIZE_2_E_OFFSET         0xa0
+#define MIB_TXOVERSIZE_2_NR_E             6
+
+#define MIB_TXBYTE_LO_2                   "TxByteLo_2"
+#define MIB_TXBYTE_LO_2_ID                65
+#define MIB_TXBYTE_LO_2_OFFSET            (MIB_TXBYTE_LO_OFFSET + 0x400)
+#define MIB_TXBYTE_LO_2_E_LENGTH          4
+#define MIB_TXBYTE_LO_2_E_OFFSET          0xa0
+#define MIB_TXBYTE_LO_2_NR_E              6
+
+#define MIB_TXBYTE_HI_2                   "TxByteHi_2"
+#define MIB_TXBYTE_HI_2_ID                66
+#define MIB_TXBYTE_HI_2_OFFSET            (MIB_TXBYTE_HI_OFFSET + 0x400)
+#define MIB_TXBYTE_HI_2_E_LENGTH          4
+#define MIB_TXBYTE_HI_2_E_OFFSET          0xa0
+#define MIB_TXBYTE_HI_2_NR_E              6
+
+#define MIB_TXCOLLISION_2                 "TxCollision_2"
+#define MIB_TXCOLLISION_2_ID              67
+#define MIB_TXCOLLISION_2_OFFSET          (MIB_TXCOLLISION_OFFSET + 0x400)
+#define MIB_TXCOLLISION_2_E_LENGTH        4
+#define MIB_TXCOLLISION_2_E_OFFSET        0xa0
+#define MIB_TXCOLLISION_2_NR_E            6
+
+#define MIB_TXABORTCOL_2                  "TxAbortCol_2"
+#define MIB_TXABORTCOL_2_ID               68
+#define MIB_TXABORTCOL_2_OFFSET           (MIB_TXABORTCOL_OFFSET + 0x400)
+#define MIB_TXABORTCOL_2_E_LENGTH         4
+#define MIB_TXABORTCOL_2_E_OFFSET         0xa0
+#define MIB_TXABORTCOL_2_NR_E             6
+
+#define MIB_TXMULTICOL_2                  "TxMultiCol_2"
+#define MIB_TXMULTICOL_2_ID               69
+#define MIB_TXMULTICOL_2_OFFSET           (MIB_TXMULTICOL_OFFSET + 0x400)
+#define MIB_TXMULTICOL_2_E_LENGTH         4
+#define MIB_TXMULTICOL_2_E_OFFSET         0xa0
+#define MIB_TXMULTICOL_2_NR_E             6
+
+#define MIB_TXSINGALCOL_2                 "TxSingalCol_2"
+#define MIB_TXSINGALCOL_2_ID              70
+#define MIB_TXSINGALCOL_2_OFFSET          (MIB_TXSINGALCOL_OFFSET + 0x400)
+#define MIB_TXSINGALCOL_2_E_LENGTH        4
+#define MIB_TXSINGALCOL_2_E_OFFSET        0xa0
+#define MIB_TXSINGALCOL_2_NR_E            6
+
+#define MIB_TXEXCDEFER_2                  "TxExcDefer_2"
+#define MIB_TXEXCDEFER_2_ID               71
+#define MIB_TXEXCDEFER_2_OFFSET           (MIB_TXEXCDEFER_OFFSET + 0x400)
+#define MIB_TXEXCDEFER_2_E_LENGTH         4
+#define MIB_TXEXCDEFER_2_E_OFFSET         0xa0
+#define MIB_TXEXCDEFER_2_NR_E             6
+
+#define MIB_TXDEFER_2                     "TxDefer_2"
+#define MIB_TXDEFER_2_ID                  72
+#define MIB_TXDEFER_2_OFFSET              (MIB_TXDEFER_OFFSET + 0x400)
+#define MIB_TXDEFER_2_E_LENGTH            4
+#define MIB_TXDEFER_2_E_OFFSET            0xa0
+#define MIB_TXDEFER_2_NR_E                6
+
+#define MIB_TXLATECOL_2                   "TxLateCol_2"
+#define MIB_TXLATECOL_2_ID                73
+#define MIB_TXLATECOL_2_OFFSET            (MIB_TXLATECOL_OFFSET + 0x400)
+#define MIB_TXLATECOL_2_E_LENGTH          4
+#define MIB_TXLATECOL_2_E_OFFSET          0xa0
+#define MIB_TXLATECOL_2_NR_E              6
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ATHENA_REG_H */
+
diff --git a/qca-ssdk/include/hsl/athena/athena_reg_access.h b/qca-ssdk/include/hsl/athena/athena_reg_access.h
new file mode 100755
index 0000000..60f4b28
--- /dev/null
+++ b/qca-ssdk/include/hsl/athena/athena_reg_access.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _ATHENA_REG_ACCESS_H_
+#define _ATHENA_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "sw.h"
+
+    sw_error_t
+    athena_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+                   a_uint32_t reg, a_uint16_t * value);
+
+    sw_error_t
+    athena_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+                   a_uint32_t reg, a_uint16_t value);
+
+    sw_error_t
+    athena_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                   a_uint32_t value_len);
+
+    sw_error_t
+    athena_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                   a_uint32_t value_len);
+
+    sw_error_t
+    athena_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                         a_uint32_t bit_offset, a_uint32_t field_len,
+                         a_uint8_t value[], a_uint32_t value_len);
+
+    sw_error_t
+    athena_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                         a_uint32_t bit_offset, a_uint32_t field_len,
+                         const a_uint8_t value[], a_uint32_t value_len);
+
+    sw_error_t
+    athena_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode);
+
+    sw_error_t
+    athena_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ATHENA_REG_ACCESS_H_ */
+
diff --git a/qca-ssdk/include/hsl/athena/athena_vlan.h b/qca-ssdk/include/hsl/athena/athena_vlan.h
new file mode 100755
index 0000000..5e97c72
--- /dev/null
+++ b/qca-ssdk/include/hsl/athena/athena_vlan.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ATHENA_VLAN_H
+#define _ATHENA_VLAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_vlan.h"
+
+    sw_error_t
+    athena_vlan_reset(a_uint32_t dev_id);
+
+    sw_error_t
+    athena_vlan_init(a_uint32_t dev_id);
+
+    sw_error_t
+    athena_vlan_cleanup(a_uint32_t dev_id);
+
+#ifdef IN_VLAN
+#define ATHENA_VLAN_RESET(rv, dev_id) \
+    { \
+        rv = athena_vlan_reset(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define ATHENA_VLAN_INIT(rv, dev_id) \
+    { \
+        rv = athena_vlan_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define ATHENA_VLAN_CLEANUP(rv, dev_id) \
+    { \
+        rv = athena_vlan_cleanup(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ATHENA_VLAN_RESET(rv, dev_id)
+#define ATHENA_VLAN_INIT(rv, dev_id)
+#define ATHENA_VLAN_CLEANUP(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    athena_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+
+    HSL_LOCAL sw_error_t
+    athena_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                              fal_pbmp_t member, fal_pbmp_t u_member);
+
+
+    HSL_LOCAL sw_error_t
+    athena_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ATHENA_VLAN_H */
diff --git a/qca-ssdk/include/hsl/cppe/cppe_loopback.h b/qca-ssdk/include/hsl/cppe/cppe_loopback.h
new file mode 100755
index 0000000..ed9ff8c
--- /dev/null
+++ b/qca-ssdk/include/hsl/cppe/cppe_loopback.h
@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _CPPE_LOOPBACK_H_
+#define _CPPE_LOOPBACK_H_
+
+sw_error_t
+cppe_lpbk_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_enable_u *value);
+
+sw_error_t
+cppe_lpbk_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_enable_u *value);
+
+sw_error_t
+cppe_lpbk_fifo_1_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_fifo_1_ctrl_u *value);
+
+sw_error_t
+cppe_lpbk_fifo_1_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_fifo_1_ctrl_u *value);
+
+sw_error_t
+cppe_lpbk_fifo_2_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_fifo_2_ctrl_u *value);
+
+sw_error_t
+cppe_lpbk_fifo_2_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_fifo_2_ctrl_u *value);
+
+sw_error_t
+cppe_lpbk_pps_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_pps_ctrl_u *value);
+
+sw_error_t
+cppe_lpbk_pps_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_pps_ctrl_u *value);
+
+sw_error_t
+cppe_lpbk_mac_junmo_size_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_mac_junmo_size_u *value);
+
+sw_error_t
+cppe_lpbk_mac_junmo_size_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_mac_junmo_size_u *value);
+
+sw_error_t
+cppe_lpbk_mib_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_mib_ctrl_u *value);
+
+sw_error_t
+cppe_lpbk_mib_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_mib_ctrl_u *value);
+
+sw_error_t
+cppe_lpbk_mib_uni_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkuni_u *value);
+
+sw_error_t
+cppe_lpbk_mib_multi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkmulti_u *value);
+
+sw_error_t
+cppe_lpbk_mib_broad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkbroad_u *value);
+
+sw_error_t
+cppe_lpbk_mib_pkt64_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt64_u *value);
+
+sw_error_t
+cppe_lpbk_mib_pkt65to127_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt65to127_u *value);
+
+sw_error_t
+cppe_lpbk_mib_pkt128to255_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt128to255_u *value);
+
+sw_error_t
+cppe_lpbk_mib_pkt256to511_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt256to511_u *value);
+
+sw_error_t
+cppe_lpbk_mib_pkt512to1023_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt512to1023_u *value);
+
+sw_error_t
+cppe_lpbk_mib_pkt1024to1518_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt1024to1518_u *value);
+
+sw_error_t
+cppe_lpbk_mib_pkt1519tox_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt1519tox_u *value);
+
+sw_error_t
+cppe_lpbk_mib_toolong_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkttoolong_u *value);
+
+sw_error_t
+cppe_lpbk_mib_byte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkbyte_l_u *value);
+
+sw_error_t
+cppe_lpbk_mib_byte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkbyte_h_u *value);
+
+sw_error_t
+cppe_lpbk_mib_drop_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkdropcounter_u *value);
+
+sw_error_t
+cppe_lpbk_mib_tooshort_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkttooshort_u *value);
+
+sw_error_t
+cppe_lpbk_mib_pkt14to63_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt14to63_u *value);
+
+sw_error_t
+cppe_lpbk_mib_toolongbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbktoolongbyte_l_u *value);
+
+sw_error_t
+cppe_lpbk_mib_toolongbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbktoolongbyte_h_u *value);
+
+
+sw_error_t
+cppe_lpbk_mib_tooshortbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbktooshortbyte_l_u *value);
+
+sw_error_t
+cppe_lpbk_mib_tooshortbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbktooshortbyte_h_u *value);
+#endif
diff --git a/qca-ssdk/include/hsl/cppe/cppe_loopback_reg.h b/qca-ssdk/include/hsl/cppe/cppe_loopback_reg.h
new file mode 100755
index 0000000..899e8cf
--- /dev/null
+++ b/qca-ssdk/include/hsl/cppe/cppe_loopback_reg.h
@@ -0,0 +1,578 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef CPPE_LOOPBACK_REG_H
+#define CPPE_LOOPBACK_REG_H
+
+/*[register] LPBK_ENABLE*/
+#define LPBK_ENABLE
+#define LPBK_ENABLE_ADDRESS 0x00
+#define LPBK_ENABLE_NUM     6
+#define LPBK_ENABLEL_INC     0x200
+#define LPBK_ENABLE_TYPE    REG_TYPE_RW
+#define LPBK_ENABLE_DEFAULT 0x0
+	/*[field] LPBK_EN*/
+	#define LPBK_EN_LPBK_EN
+	#define LPBK_EN_LPBK_EN_OFFSET  0
+	#define LPBK_EN_LPBK_EN_LEN     1
+	#define LLPBK_EN_LPBK_EN_DEFAULT 0x0
+	/*[field] FLOWCTRL_EN*/
+	#define LPBK_ENABLE_FLOWCTRL_EN
+	#define LPBK_ENABLE_FLOWCTRL_EN_OFFSET  1
+	#define LPBK_ENABLE_FLOWCTRL_EN_LEN     1
+	#define LPBK_ENABLE_FLOWCTRL_EN_DEFAULT 0x1
+	/*[field] FLOWCTRL_MODE*/
+	#define LPBK_EN_FLOWCTRL_MODE
+	#define LPBK_EN_FLOWCTRL_MODE_OFFSET  2
+	#define LPBK_EN_FLOWCTRL_MODE_LEN     1
+	#define LPBK_EN_FLOWCTRL_MODE_DEFAULT 0x0
+	/*[field] CRC_STRIP_EN*/
+	#define LPBK_EN_CRC_STRIP_EN
+	#define LPBK_EN_CRC_STRIP_EN_OFFSET  2
+	#define LPBK_EN_CRC_STRIP_EN_LEN     1
+	#define LPBK_EN_CRC_STRIP_EN_DEFAULT 0x1
+struct lpbk_enable {
+	a_uint32_t lpbk_en:1;
+	a_uint32_t flowctrl_en :1;
+	a_uint32_t flowctrl_mode:1;
+	a_uint32_t crc_strip_en:1;
+	a_uint32_t _reserved0:28;
+};
+union lpbk_enable_u {
+	a_uint32_t val;
+	struct lpbk_enable bf;
+};
+
+/*[register] LPBK_FIFO_1_CTRL*/
+#define LPBK_FIFO_1_CTRL
+#define LPBK_FIFO_1_CTRL_ADDRESS 0x04
+#define LPBK_FIFO_1_CTRL_NUM     6
+#define LPBK_FIFO_1_CTRL_INC     0x200
+#define LPBK_FIFO_1_CTRL_TYPE    REG_TYPE_RW
+#define LPBK_FIFO_1_CTRL_DEFAULT 0x3
+	/*[field] LPBK_FIFO_1_THRESHOLD*/
+	#define LPBK_FIFO_1_CTRL_LPBK_FIFO_1_THRESHOLD
+	#define LPBK_FIFO_1_CTRL_LPBK_FIFO_1_THRESHOLD_OFFSET  0
+	#define LPBK_FIFO_1_CTRL_LPBK_FIFO_1_THRESHOLD_LEN     3
+	#define LPBK_FIFO_1_CTRL_LPBK_FIFO_1_THRESHOLD_DEFAULT 0x0
+struct lpbk_fifo_1_ctrl {
+	a_uint32_t lpbk_fifo_1_threshold:3;
+	a_uint32_t _reserved0:29;
+};
+union lpbk_fifo_1_ctrl_u {
+	a_uint32_t val;
+	struct lpbk_fifo_1_ctrl bf;
+};
+
+/*[register] LPBK_FIFO_2_CTRL*/
+#define LPBK_FIFO_2_CTRL
+#define LPBK_FIFO_2_CTRL_ADDRESS 0x08
+#define LPBK_FIFO_2_CTRL_NUM     6
+#define LPBK_FIFO_2_CTRL_INC     0x200
+#define LPBK_FIFO_2_CTRL_TYPE    REG_TYPE_RW
+#define LPBK_FIFO_2_CTRL_DEFAULT 0x1
+	/*[field] LPBK_FIFO_2_THRESHOLD*/
+	#define LPBK_FIFO_2_CTRL_LPBK_FIFO_2_THRESHOLD
+	#define LPBK_FIFO_2_CTRL_LPBK_FIFO_2_THRESHOLD_OFFSET  0
+	#define LPBK_FIFO_2_CTRL_LPBK_FIFO_2_THRESHOLD_LEN     3
+	#define LPBK_FIFO_2_CTRL_LPBK_FIFO_2_THRESHOLD_DEFAULT 0x0
+struct lpbk_fifo_2_ctrl {
+	a_uint32_t lpbk_fifo_2_threshold:3;
+	a_uint32_t _reserved0:29;
+};
+union lpbk_fifo_2_ctrl_u {
+	a_uint32_t val;
+	struct lpbk_fifo_2_ctrl bf;
+};
+
+/*[register] LPBK_PPS_CTRL*/
+#define LPBK_PPS_CTRL
+#define LPBK_PPS_CTRL_ADDRESS 0x0c
+#define LPBK_PPS_CTRL_NUM     6
+#define LPBK_PPS_CTRL_INC     0x200
+#define LPBK_PPS_CTRL_TYPE    REG_TYPE_RW
+#define LPBK_PPS_CTRL_DEFAULT 0x0
+	/*[field] LPBK_PPS_THRESHOLD*/
+	#define LPBK_PPS_CTRL_LPBK_PPS_THRESHOLD
+	#define LPBK_PPS_CTRL_LPBK_PPS_THRESHOLD_OFFSET  0
+	#define LPBK_PPS_CTRL_LPBK_PPS_THRESHOLD_LEN     9
+	#define LPBK_PPS_CTRL_LPBK_PPS_THRESHOLD_DEFAULT 0x16
+struct lpbk_pps_ctrl {
+	a_uint32_t lpbk_pps_threshold:9;
+	a_uint32_t _reserved0:13;
+};
+union lpbk_pps_ctrl_u {
+	a_uint32_t val;
+	struct lpbk_pps_ctrl bf;
+};
+
+/*[register] LPBK_MAC_JUNMO_SIZE*/
+#define LPBK_MAC_JUNMO_SIZE
+#define LPBK_MAC_JUNMO_SIZE_ADDRESS 0x10
+#define LPBK_MAC_JUNMO_SIZE_NUM     6
+#define LPBK_MAC_JUNMO_SIZE_INC     0x200
+#define LPBK_MAC_JUNMO_SIZE_TYPE    REG_TYPE_RW
+#define LPBK_MAC_JUNMO_SIZE_DEFAULT 0x0
+	/*[field] LPBK_MAC_JUMBO_SIZE*/
+	#define LPBK_MAC_JUNMO_SIZE_LPBK_MAC_JUMBO_SIZE
+	#define LPBK_MAC_JUNMO_SIZE_LPBK_MAC_JUMBO_SIZE_OFFSET  0
+	#define LPBK_MAC_JUNMO_SIZE_LPBK_MAC_JUMBO_SIZE_LEN     14
+	#define LPBK_MAC_JUNMO_SIZE_LPBK_MAC_JUMBO_SIZE_DEFAULT 0x5EA
+struct lpbk_mac_junmo_size {
+	a_uint32_t lpbk_mac_jumbo_size:14;
+	a_uint32_t _reserved0:18;
+};
+union lpbk_mac_junmo_size_u {
+	a_uint32_t val;
+	struct lpbk_mac_junmo_size bf;
+};
+
+/*[register] LPBK_MIB_CTRL*/
+#define LPBK_MIB_CTRL
+#define LPBK_MIB_CTRL_ADDRESS 0x14
+#define LPBK_MIB_CTRL_NUM     6
+#define LPBK_MIB_CTRL_INC     0x200
+#define LPBK_MIB_CTRL_TYPE    REG_TYPE_RW
+#define LPBK_MIB_CTRL_DEFAULT 0x0
+	/*[field] MIB_EN*/
+	#define LPBK_MIB_CTRL_MIB_EN
+	#define LPBK_MIB_CTRL_MIB_EN_OFFSET  0
+	#define LPBK_MIB_CTRL_MIB_EN_LEN     1
+	#define LPBK_MIB_CTRL_MIB_EN_DEFAULT 0x1
+	/*[field] MIB_RESET*/
+	#define LPBK_MIB_CTRL_MIB_RESET
+	#define LPBK_MIB_CTRL_MIB_RESET_OFFSET  1
+	#define LPBK_MIB_CTRL_MIB_RESET_LEN     1
+	#define LPBK_MIB_CTRL_MIB_RESET_DEFAULT 0x0
+	/*[field] MIB_RD_CLR*/
+	#define LPBK_MIB_CTRL_MIB_RD_CLR
+	#define LPBK_MIB_CTRL_MIB_RD_CLR_OFFSET  2
+	#define LPBK_MIB_CTRL_MIB_RD_CLR_LEN     1
+	#define LPBK_MIB_CTRL_MIB_RD_CLR_DEFAULT 0x0
+struct lpbk_mib_ctrl {
+	a_uint32_t  mib_en:1;
+	a_uint32_t  mib_reset:1;
+	a_uint32_t  mib_rd_clr:1;
+	a_uint32_t  _reserved0:29;
+};
+union lpbk_mib_ctrl_u {
+	a_uint32_t val;
+	struct lpbk_mib_ctrl bf;
+};
+
+/*[register] LPBKUNI*/
+#define LPBKUNI
+#define LPBKUNI_ADDRESS 0x20
+#define LPBKUNI_NUM     6
+#define LPBKUNI_INC     0x200
+#define LPBKUNI_TYPE    REG_TYPE_RO
+#define LPBKUNI_DEFAULT 0x0
+	/*[field] LPBKUNI*/
+	#define LPBKUNI_LPBKUNI
+	#define LPBKUNI_LPBKUNI_OFFSET  0
+	#define LPBKUNI_LPBKUNI_LEN     32
+	#define LPBKUNI_LPBKUNI_DEFAULT 0x0
+struct lpbkuni {
+	a_uint32_t  lpbkuni:32;
+};
+union lpbkuni_u {
+	a_uint32_t val;
+	struct lpbkuni bf;
+};
+
+/*[register] LPBKMULTI*/
+#define LPBKMULTI
+#define LPBKMULTI_ADDRESS 0x24
+#define LPBKMULTI_NUM     6
+#define LPBKMULTI_INC     0x200
+#define LPBKMULTI_TYPE    REG_TYPE_RO
+#define LPBKMULTI_DEFAULT 0x0
+	/*[field] LPBKMULTI*/
+	#define LPBKMULTI_LPBKMULTI
+	#define LPBKMULTI_LPBKMULTI_OFFSET  0
+	#define LPBKMULTI_LPBKMULTI_LEN     32
+	#define LPBKMULTI_LPBKMULTI_DEFAULT 0x0
+struct lpbkmulti {
+	a_uint32_t  lpbkmulti:32;
+};
+union lpbkmulti_u {
+	a_uint32_t val;
+	struct lpbkmulti bf;
+};
+
+/*[register] LPBKBROAD*/
+#define LPBKBROAD
+#define LPBKBROAD_ADDRESS 0x28
+#define LPBKBROAD_NUM     6
+#define LPBKBROAD_INC     0x200
+#define LPBKBROAD_TYPE    REG_TYPE_RO
+#define LPBKBROAD_DEFAULT 0x0
+	/*[field] LPBK_BROAD*/
+	#define LPBKBROAD_LPBKBROAD
+	#define LPBKBROAD_LPBKBROAD_OFFSET  0
+	#define LPBKBROAD_LPBKBROAD_LEN     32
+	#define LPBKBROAD_LPBKBROAD_DEFAULT 0x0
+struct lpbkbroad {
+	a_uint32_t  lpbkbroad:32;
+};
+union lpbkbroad_u {
+	a_uint32_t val;
+	struct lpbkbroad bf;
+};
+
+/*[register] LPBKPKT64*/
+#define LPBKPKT64
+#define LPBKPKT64_ADDRESS 0x2c
+#define LPBKPKT64_NUM     6
+#define LPBKPKT64_INC     0x200
+#define LPBKPKT64_TYPE    REG_TYPE_RO
+#define LPBKPKT64_DEFAULT 0x0
+	/*[field] LPBKPKT64*/
+	#define LPBKPKT64_LPBKPKT64
+	#define LPBKPKT64_LPBKPKT64_OFFSET  0
+	#define LPBKPKT64_LPBKPKT64_LEN     32
+	#define LPBKPKT64_LPBKPKT64_DEFAULT 0x0
+struct lpbkpkt64 {
+	a_uint32_t  lpbkpkt64:32;
+};
+union lpbkpkt64_u {
+	a_uint32_t val;
+	struct lpbkpkt64 bf;
+};
+
+/*[register] LPBKPKT65TO127*/
+#define LPBKPKT65TO127
+#define LPBKPKT65TO127_ADDRESS 0x30
+#define LPBKPKT65TO127_NUM     6
+#define LPBKPKT65TO127_INC     0x200
+#define LPBKPKT65TO127_TYPE    REG_TYPE_RO
+#define LPBKPKT65TO1277_DEFAULT 0x0
+	/*[field] LPBKPKT65TO127*/
+	#define LPBKPKT65TO127_LPBKPKT65TO127
+	#define LPBKPKT65TO127_LPBKPKT65TO127_OFFSET  0
+	#define LPBKPKT65TO127_LPBKPKT65TO127_LEN     32
+	#define LPBKPKT65TO127_LPBKPKT65TO127_DEFAULT 0x0
+struct lpbkpkt65to127 {
+	a_uint32_t  lpbkpkt65to127:32;
+};
+union lpbkpkt65to127_u {
+	a_uint32_t val;
+	struct lpbkpkt65to127 bf;
+};
+
+/*[register] LPBKPKT128TO255*/
+#define LPBKPKT128TO255
+#define LPBKPKT128TO255_ADDRESS 0x34
+#define LPBKPKT128TO255_NUM     6
+#define LPBKPKT128TO255_INC     0x200
+#define LPBKPKT128TO255_TYPE    REG_TYPE_RO
+#define LPBKPKT128TO255_DEFAULT 0x0
+	/*[field] LPBKPKT128TO255*/
+	#define LPBKPKT128TO255_LPBKPKT128TO255
+	#define LPBKPKT128TO255_LPBKPKT128TO255_OFFSET  0
+	#define LPBKPKT128TO255_LPBKPKT128TO255_LEN     32
+	#define LPBKPKT128TO255_LPBKPKT128TO255_DEFAULT 0x0
+struct lpbkpkt128to255 {
+	a_uint32_t  lpbkpkt128to255:32;
+};
+union lpbkpkt128to255_u {
+	a_uint32_t val;
+	struct lpbkpkt128to255 bf;
+};
+
+/*[register] LPBKPKT256TO511*/
+#define LPBKPKT256TO511
+#define LPBKPKT256TO511_ADDRESS 0x38
+#define LPBKPKT256TO511_NUM     6
+#define LPBKPKT256TO511_INC     0x200
+#define LPBKPKT256TO511_TYPE    REG_TYPE_RO
+#define LPBKPKT256TO511_DEFAULT 0x0
+	/*[field] LPBKPKT256TO511*/
+	#define LPBKPKT256TO511_LPBKPKT256TO511
+	#define LPBKPKT256TO511_LPBKPKT256TO511_OFFSET  0
+	#define LPBKPKT256TO511_LPBKPKT256TO511_LEN     32
+	#define LPBKPKT256TO511_LPBKPKT256TO511_DEFAULT 0x0
+struct lpbkpkt256to511 {
+	a_uint32_t  lpbkpkt256to511:32;
+};
+union lpbkpkt256to511_u {
+	a_uint32_t val;
+	struct lpbkpkt256to511 bf;
+};
+
+/*[register] LPBKPKT512TO1023*/
+#define LPBKPKT512TO1023
+#define LPBKPKT512TO1023_ADDRESS 0x3c
+#define LPBKPKT512TO1023_NUM     6
+#define LPBKPKT512TO1023_INC     0x200
+#define LPBKPKT512TO1023_TYPE    REG_TYPE_RO
+#define LPBKPKT512TO1023_DEFAULT 0x0
+	/*[field] LPBKPKT512TO1023*/
+	#define LPBKPKT512TO1023_LPBKPKT512TO1023
+	#define LPBKPKT512TO1023_LPBKPKT512TO1023_OFFSET  0
+	#define LPBKPKT512TO1023_LPBKPKT512TO1023_LEN     32
+	#define LPBKPKT512TO1023_LPBKPKT512TO1023_DEFAULT 0x0
+struct lpbkpkt512to1023 {
+	a_uint32_t  lpbkpkt512to1023:32;
+};
+union lpbkpkt512to1023_u {
+	a_uint32_t val;
+	struct lpbkpkt512to1023 bf;
+};
+
+/*[register] LPBKPKT1024TO1518*/
+#define LPBKPKT1024TO1518
+#define LPBKPKT1024TO1518_ADDRESS 0x40
+#define LPBKPKT1024TO1518_NUM     6
+#define LPBKPKT1024TO1518_INC     0x200
+#define LPBKPKT1024TO1518_TYPE    REG_TYPE_RO
+#define LPBKPKT1024TO1518_DEFAULT 0x0
+	/*[field] RXPKT1024TO1518*/
+	#define LPBKPKT1024TO1518_LPBKPKT1024TO1518
+	#define LPBKPKT1024TO1518_OFFSET  0
+	#define LPBKPKT1024TO1518_LEN     32
+	#define LPBKPKT1024TO1518_DEFAULT 0x0
+
+struct lpbkpkt1024to1518 {
+	a_uint32_t  lpbkpkt1024to1518:32;
+};
+union lpbkpkt1024to1518_u {
+	a_uint32_t val;
+	struct lpbkpkt1024to1518 bf;
+};
+
+/*[register] LPBKPKT1519TOX*/
+#define LPBKPKT1519TOX
+#define LPBKPKT1519TOX_ADDRESS 0x44
+#define LPBKPKT1519TOX_NUM     6
+#define LPBKPKT1519TOX_INC     0x200
+#define LPBKPKT1519TOX_TYPE    REG_TYPE_RO
+#define LPBKPKT1519TOX_DEFAULT 0x0
+	/*[field] RXPKT1519TOX*/
+	#define LPBKPKT1519TOX_LPBKPKT1519TOX
+	#define LPBKPKT1519TOX_LPBKPKT1519TOX_OFFSET  0
+	#define LPBKPKT1519TOX_LPBKPKT1519TOX_LEN     32
+	#define LPBKPKT1519TOX_LPBKPKT1519TOX_DEFAULT 0x0
+struct lpbkpkt1519tox {
+	a_uint32_t  lpbkpkt1519tox:32;
+};
+union lpbkpkt1519tox_u {
+	a_uint32_t val;
+	struct lpbkpkt1519tox bf;
+};
+
+/*[register] LPBKPKTTOOLONG*/
+#define LPBKPKTTOOLONG
+#define LPBKPKTTOOLONG_ADDRESS 0x48
+#define LPBKPKTTOOLONG_NUM     6
+#define LPBKPKTTOOLONG_INC     0x200
+#define LPBKPKTTOOLONG_TYPE    REG_TYPE_RO
+#define LPBKPKTTOOLONG_DEFAULT 0x0
+	/*[field] RXTOOLONG*/
+	#define LPBKPKTTOOLONG_LPBKPKTTOOLONG
+	#define LPBKPKTTOOLONG_LPBKPKTTOOLONG_OFFSET  0
+	#define LPBKPKTTOOLONG_LPBKPKTTOOLONG_LEN     32
+	#define LPBKPKTTOOLONG_LPBKPKTTOOLONG_DEFAULT 0x0
+struct lpbkpkttoolong {
+	a_uint32_t  lpbkpkttoolong:32;
+};
+union lpbkpkttoolong_u {
+	a_uint32_t val;
+	struct lpbkpkttoolong bf;
+};
+
+/*[register] LPBKBYTE_L*/
+#define LPBKBYTE_L
+#define LPBKBYTE_L_ADDRESS 0x4c
+#define LPBKBYTE_L_NUM     6
+#define LPBKBYTE_L_INC     0x200
+#define LPBKBYTE_L_TYPE    REG_TYPE_RO
+#define LPBKBYTE_L_DEFAULT 0x0
+	/*[field] LPBKBYTE_L*/
+	#define LPBKBYTE_L_LPBKBYTE_L
+	#define LPBKBYTE_L_LPBKBYTE_L_OFFSET  0
+	#define LPBKBYTE_L_LPBKBYTE_L_LEN     32
+	#define LPBKBYTE_L_LPBKBYTE_L_DEFAULT 0x0
+struct lpbkbyte_l {
+	a_uint32_t  lpbkbyte_l:32;
+};
+union lpbkbyte_l_u {
+	a_uint32_t val;
+	struct lpbkbyte_l bf;
+};
+
+/*[register] LPBKBYTE_H*/
+#define LPBKBYTE_H
+#define LPBKBYTE_H_ADDRESS 0x50
+#define LPBKBYTE_H_NUM     6
+#define LPBKBYTE_H_INC     0x200
+#define LPBKBYTE_H_TYPE    REG_TYPE_RO
+#define LPBKBYTE_H_DEFAULT 0x0
+	/*[field] LPBKBYTE_H*/
+	#define LPBKBYTE_H_LPBKBYTE_H
+	#define LPBKBYTE_H_LPBKBYTE_H_OFFSET  0
+	#define LPBKBYTE_H_LPBKBYTE_H_LEN     32
+	#define LPBKBYTE_H_LPBKBYTE_H_DEFAULT 0x0
+
+struct lpbkbyte_h {
+	a_uint32_t  lpbkbyte_h:32;
+};
+union lpbkbyte_h_u {
+	a_uint32_t val;
+	struct lpbkbyte_h bf;
+};
+
+/*[register] LPBKDROPCOUNTER*/
+#define LPBKDROPCOUNTER
+#define LPBKDROPCOUNTER_ADDRESS 0x54
+#define LPBKDROPCOUNTER_NUM     6
+#define LPBKDROPCOUNTER_INC     0x200
+#define LPBKDROPCOUNTER_TYPE    REG_TYPE_RO
+#define LPBKDROPCOUNTER_DEFAULT 0x0
+	/*[field] LPBKDROPCOUNTER*/
+	#define LPBKDROPCOUNTER_LPBKDROPCOUNTER
+	#define LPBKDROPCOUNTER_OFFSET  0
+	#define LPBKDROPCOUNTER_LEN     32
+	#define LPBKDROPCOUNTER_DEFAULT 0x0
+struct lpbkdropcounter {
+	a_uint32_t  lpbkdropcounter:32;
+};
+union lpbkdropcounter_u {
+	a_uint32_t val;
+	struct lpbkdropcounter bf;
+};
+
+/*[register] LPBKTOOSHORT*/
+#define LPBKPKTTOOSHORT
+#define LPBKPKTTOOSHORT_ADDRESS 0x68
+#define LPBKPKTTOOSHORT_NUM     6
+#define LPBKPKTTOOSHORT_INC     0x200
+#define LPBKPKTTOOSHORT_TYPE    REG_TYPE_RO
+#define LPBKPKTTOOSHORT_DEFAULT 0x0
+	/*[field] LPBKPKTTOOSHORT*/
+	#define LPBKPKTTOOSHORT_LPBKPKTTOOSHORT
+	#define LPBKPKTTOOSHORT_OFFSET  0
+	#define LPBKPKTTOOSHORT_LEN     32
+	#define LPBKPKTTOOSHORT_DEFAULT 0x0
+struct lpbkpkttooshort {
+	a_uint32_t  lpbkpkttooshort:32;
+};
+union lpbkpkttooshort_u {
+	a_uint32_t val;
+	struct lpbkpkttooshort bf;
+};
+
+/*[register] LPBKPKT14TO63*/
+#define LPBKPKT14TO63
+#define LPBKPKT14TO63_ADDRESS 0x6c
+#define LPBKPKT14TO63_NUM     6
+#define LPBKPKT14TO63_INC     0x200
+#define LPBKPKT14TO63_TYPE    REG_TYPE_RO
+#define LPBKPKT14TO63_DEFAULT 0x0
+	/*[field] LPBKPKT14TO63*/
+	#define LPBKPKT14TO63_LPBKPKT14TO63
+	#define LPBKPKT14TO63_OFFSET  0
+	#define LPBKPKT14TO63_LEN     32
+	#define LPBKPKT14TO63_DEFAULT 0x0
+struct lpbkpkt14to63 {
+	a_uint32_t  lpbkpkt14to63:32;
+};
+union lpbkpkt14to63_u {
+	a_uint32_t val;
+	struct lpbkpkt14to63 bf;
+};
+
+/*[register] LPBKTOOLONGBYTE_L*/
+#define LPBKTOOLONGBYTE_L
+#define LPBKTOOLONGBYTE_L_ADDRESS 0x70
+#define LPBKTOOLONGBYTE_L_NUM     6
+#define LPBKTOOLONGBYTE_L_INC     0x200
+#define LPBKTOOLONGBYTE_L_TYPE    REG_TYPE_RO
+#define LPBKTOOLONGBYTE_L_DEFAULT 0x0
+	/*[field] LPBKTOOLONGBYTE_L*/
+	#define LPBKTOOLONGBYTE_L_LPBKTOOLONGBYTE_L
+	#define LPBKTOOLONGBYTE_L_LPBKTOOLONGBYTE_L_OFFSET  0
+	#define LPBKTOOLONGBYTE_L_LPBKTOOLONGBYTE_L_LEN     32
+	#define LPBKTOOLONGBYTE_L_LPBKTOOLONGBYTE_L_DEFAULT 0x0
+struct lpbktoolongbyte_l {
+	a_uint32_t  lpbktoolongbyte_l:32;
+};
+union lpbktoolongbyte_l_u {
+	a_uint32_t val;
+	struct lpbktoolongbyte_l bf;
+};
+
+/*[register] LPBKTOOLONGBYTE_H*/
+#define LPBKTOOLONGBYTE_H
+#define LPBKTOOLONGBYTE_H_ADDRESS 0x74
+#define LPBKTOOLONGBYTE_H_NUM     6
+#define LPBKTOOLONGBYTE_H_INC     0x200
+#define LPBKTOOLONGBYTE_H_TYPE    REG_TYPE_RO
+#define LPBKTOOLONGBYTE_H_DEFAULT 0x0
+	/*[field] LPBKTOOLONGBYTE_L*/
+	#define LPBKTOOLONGBYTE_H_LPBKTOOLONGBYTE_H
+	#define LPBKTOOLONGBYTE_H_LPBKTOOLONGBYTE_H_OFFSET  0
+	#define LPBKTOOLONGBYTE_H_LPBKTOOLONGBYTE_H_LEN     32
+	#define LPBKTOOLONGBYTE_H_LPBKTOOLONGBYTE_H_DEFAULT 0x0
+struct lpbktoolongbyte_h {
+	a_uint32_t  lpbktoolongbyte_h:32;
+};
+union lpbktoolongbyte_h_u {
+	a_uint32_t val;
+	struct lpbktoolongbyte_h bf;
+};
+
+/*[register] LPBKTOOSHORTBYTE_L*/
+#define LPBKTOOSHORTBYTE_L
+#define LPBKTOOSHORTBYTE_L_ADDRESS 0x78
+#define LPBKTOOSHORTBYTE_L_NUM     6
+#define LPBKTOOSHORTBYTE_L_INC     0x200
+#define LPBKTOOLONGBYTE_L_TYPE    REG_TYPE_RO
+#define LPBKTOOLONGBYTE_L_DEFAULT 0x0
+	/*[field] LPBKTOOLONGBYTE_L*/
+	#define LPBKTOOSHORTBYTE_L_LPBKTOOSHORTBYTE_L
+	#define LPBKTOOSHORTBYTE_L_LPBKTOOSHORTBYTE_L_OFFSET  0
+	#define LPBKTOOSHORTBYTE_L_LPBKTOOSHORTBYTE_L_LEN     32
+	#define LPBKTOOSHORTBYTE_L_LPBKTOOSHORTBYTE_L_DEFAULT 0x0
+struct lpbktooshortbyte_l {
+	a_uint32_t  lpbktooshortbyte_l:32;
+};
+union lpbktooshortbyte_l_u {
+	a_uint32_t val;
+	struct lpbktooshortbyte_l bf;
+};
+
+/*[register] LPBKTOOSHORTBYTE_H*/
+#define LPBKTOOSHORTBYTE_H
+#define LPBKTOOSHORTBYTE_H_ADDRESS 0x7c
+#define LPBKTOOSHORTBYTE_H_NUM     6
+#define LPBKTOOSHORTBYTE_H_INC     0x200
+#define LPBKTOOSHORTBYTE_H_TYPE    REG_TYPE_RO
+#define LPBKTOOSHORTBYTE_H_DEFAULT 0x0
+	/*[field] LPBKTOOLONGBYTE_L*/
+	#define LPBKTOOSHORTBYTE_H_LPBKTOOSHORTBYTE_H
+	#define LPBKTOOSHORTBYTE_H_OFFSET  0
+	#define LPBKTOOSHORTBYTE_H_LEN     32
+	#define LPBKTOOSHORTBYTE_H_DEFAULT 0x0
+struct lpbktooshortbyte_h {
+	a_uint32_t  lpbktooshortbyte_h:32;
+};
+union lpbktooshortbyte_h_u {
+	a_uint32_t val;
+	struct lpbktooshortbyte_h bf;
+};
+#endif
diff --git a/qca-ssdk/include/hsl/cppe/cppe_portctrl.h b/qca-ssdk/include/hsl/cppe/cppe_portctrl.h
new file mode 100755
index 0000000..b211c8c
--- /dev/null
+++ b/qca-ssdk/include/hsl/cppe/cppe_portctrl.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _CPPE_PORTCTRL_H_
+#define _CPPE_PORTCTRL_H_
+#include "cppe_portctrl_reg.h"
+
+#define CPPE_MRU_MTU_CTRL_TBL_MAX_ENTRY	256
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_dscp_res_prec_force_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_dscp_res_prec_force_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pcp_res_prec_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pcp_res_prec_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pcp_qos_group_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pcp_qos_group_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pcp_res_prec_force_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pcp_res_prec_force_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_post_acl_res_prec_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_post_acl_res_prec_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_preheader_res_prec_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_preheader_res_prec_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_dscp_res_prec_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_dscp_res_prec_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pre_acl_res_prec_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pre_acl_res_prec_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_flow_res_prec_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_flow_res_prec_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_dscp_qos_group_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_dscp_qos_group_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_src_profile_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_src_profile_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_source_filter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_source_filter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_source_filter_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_source_filter_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union cppe_mru_mtu_ctrl_tbl_u *value);
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union cppe_mru_mtu_ctrl_tbl_u *value);
+
+sw_error_t
+cppe_port_phy_status_1_get(
+		a_uint32_t dev_id,
+		union cppe_port_phy_status_1_u *value);
+
+sw_error_t
+cppe_port5_pcs1_phy_status_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+#endif
diff --git a/qca-ssdk/include/hsl/cppe/cppe_portctrl_reg.h b/qca-ssdk/include/hsl/cppe/cppe_portctrl_reg.h
new file mode 100755
index 0000000..d12d8d0
--- /dev/null
+++ b/qca-ssdk/include/hsl/cppe/cppe_portctrl_reg.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _CPPE_PORTCTRL_REG_H_
+#define _CPPE_PORTCTRL_REG_H_
+
+/*[table] CPPE_MRU_MTU_CTRL_TBL*/
+#define CPPE_MRU_MTU_CTRL_TBL
+#define CPPE_MRU_MTU_CTRL_TBL_ADDRESS 0x3000
+#define CPPE_MRU_MTU_CTRL_TBL_NUM     256
+#define CPPE_MRU_MTU_CTRL_TBL_INC     0x10
+#define CPPE_MRU_MTU_CTRL_TBL_TYPE    REG_TYPE_RW
+#define CPPE_MRU_MTU_CTRL_TBL_DEFAULT 0x0
+	/*[field] MRU*/
+	#define CPPE_MRU_MTU_CTRL_TBL_MRU
+	#define CPPE_MRU_MTU_CTRL_TBL_MRU_OFFSET  0
+	#define CPPE_MRU_MTU_CTRL_TBL_MRU_LEN     14
+	#define CPPE_MRU_MTU_CTRL_TBL_MRU_DEFAULT 0x0
+	/*[field] MRU_CMD*/
+	#define CPPE_MRU_MTU_CTRL_TBL_MRU_CMD
+	#define CPPE_MRU_MTU_CTRL_TBL_MRU_CMD_OFFSET  14
+	#define CPPE_MRU_MTU_CTRL_TBL_MRU_CMD_LEN     2
+	#define CPPE_MRU_MTU_CTRL_TBL_MRU_CMD_DEFAULT 0x0
+	/*[field] MTU*/
+	#define CPPE_MRU_MTU_CTRL_TBL_MTU
+	#define CPPE_MRU_MTU_CTRL_TBL_MTU_OFFSET  16
+	#define CPPE_MRU_MTU_CTRL_TBL_MTU_LEN     14
+	#define CPPE_MRU_MTU_CTRL_TBL_MTU_DEFAULT 0x0
+	/*[field] MTU_CMD*/
+	#define CPPE_MRU_MTU_CTRL_TBL_MTU_CMD
+	#define CPPE_MRU_MTU_CTRL_TBL_MTU_CMD_OFFSET  30
+	#define CPPE_MRU_MTU_CTRL_TBL_MTU_CMD_LEN     2
+	#define CPPE_MRU_MTU_CTRL_TBL_MTU_CMD_DEFAULT 0x0
+	/*[field] RX_CNT_EN*/
+	#define CPPE_MRU_MTU_CTRL_TBL_RX_CNT_EN
+	#define CPPE_MRU_MTU_CTRL_TBL_RX_CNT_EN_OFFSET  32
+	#define CPPE_MRU_MTU_CTRL_TBL_RX_CNT_EN_LEN     1
+	#define CPPE_MRU_MTU_CTRL_TBL_RX_CNT_EN_DEFAULT 0x0
+	/*[field] TX_CNT_EN*/
+	#define CPPE_MRU_MTU_CTRL_TBL_TX_CNT_EN
+	#define CPPE_MRU_MTU_CTRL_TBL_TX_CNT_EN_OFFSET  33
+	#define CPPE_MRU_MTU_CTRL_TBL_TX_CNT_EN_LEN     1
+	#define CPPE_MRU_MTU_CTRL_TBL_TX_CNT_EN_DEFAULT 0x0
+	/*[field] SRC_PROFILE*/
+	#define CPPE_MRU_MTU_CTRL_TBL_SRC_PROFILE
+	#define CPPE_MRU_MTU_CTRL_TBL_SRC_PROFILE_OFFSET  34
+	#define CPPE_MRU_MTU_CTRL_TBL_SRC_PROFILE_LEN     2
+	#define CPPE_MRU_MTU_CTRL_TBL_SRC_PROFILE_DEFAULT 0x0
+	/*[field] PCP_QOS_GROUP_ID*/
+	#define CPPE_MRU_MTU_CTRL_TBL_PCP_QOS_GROUP_ID
+	#define CPPE_MRU_MTU_CTRL_TBL_PCP_QOS_GROUP_ID_OFFSET  36
+	#define CPPE_MRU_MTU_CTRL_TBL_PCP_QOS_GROUP_ID_LEN     1
+	#define CPPE_MRU_MTU_CTRL_TBL_PCP_QOS_GROUP_ID_DEFAULT 0x0
+	/*[field] DSCP_QOS_GROUP_ID*/
+	#define CPPE_MRU_MTU_CTRL_TBL_DSCP_QOS_GROUP_ID
+	#define CPPE_MRU_MTU_CTRL_TBL_DSCP_QOS_GROUP_ID_OFFSET  37
+	#define CPPE_MRU_MTU_CTRL_TBL_DSCP_QOS_GROUP_ID_LEN     1
+	#define CPPE_MRU_MTU_CTRL_TBL_DSCP_QOS_GROUP_ID_DEFAULT 0x0
+	/*[field] PCP_RES_PREC_FORCE*/
+	#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_FORCE
+	#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_FORCE_OFFSET  38
+	#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_FORCE_LEN     1
+	#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_FORCE_DEFAULT 0x0
+	/*[field] DSCP_RES_PREC_FORCE*/
+	#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_FORCE
+	#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_FORCE_OFFSET  39
+	#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_FORCE_LEN     1
+	#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_FORCE_DEFAULT 0x0
+	/*[field] PREHEADER_RES_PREC*/
+	#define CPPE_MRU_MTU_CTRL_TBL_PREHEADER_RES_PREC
+	#define CPPE_MRU_MTU_CTRL_TBL_PREHEADER_RES_PREC_OFFSET  40
+	#define CPPE_MRU_MTU_CTRL_TBL_PREHEADER_RES_PREC_LEN     3
+	#define CPPE_MRU_MTU_CTRL_TBL_PREHEADER_RES_PREC_DEFAULT 0x0
+	/*[field] PCP_RES_PREC*/
+	#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC
+	#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_OFFSET  43
+	#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_LEN     3
+	#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_DEFAULT 0x0
+	/*[field] DSCP_RES_PREC*/
+	#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC
+	#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_OFFSET  46
+	#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_LEN     3
+	#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_DEFAULT 0x0
+	/*[field] FLOW_RES_PREC*/
+	#define CPPE_MRU_MTU_CTRL_TBL_FLOW_RES_PREC
+	#define CPPE_MRU_MTU_CTRL_TBL_FLOW_RES_PREC_OFFSET  49
+	#define CPPE_MRU_MTU_CTRL_TBL_FLOW_RES_PREC_LEN     3
+	#define CPPE_MRU_MTU_CTRL_TBL_FLOW_RES_PREC_DEFAULT 0x0
+	/*[field] PRE_ACL_RES_PREC*/
+	#define CPPE_MRU_MTU_CTRL_TBL_PRE_ACL_RES_PREC
+	#define CPPE_MRU_MTU_CTRL_TBL_PRE_ACL_RES_PREC_OFFSET  52
+	#define CPPE_MRU_MTU_CTRL_TBL_PRE_ACL_RES_PREC_LEN     3
+	#define CPPE_MRU_MTU_CTRL_TBL_PRE_ACL_RES_PREC_DEFAULT 0x0
+	/*[field] POST_ACL_RES_PREC*/
+	#define CPPE_MRU_MTU_CTRL_TBL_POST_ACL_RES_PREC
+	#define CPPE_MRU_MTU_CTRL_TBL_POST_ACL_RES_PREC_OFFSET  55
+	#define CPPE_MRU_MTU_CTRL_TBL_POST_ACL_RES_PREC_LEN     3
+	#define CPPE_MRU_MTU_CTRL_TBL_POST_ACL_RES_PREC_DEFAULT 0x0
+	/*[field] SOURCE_FILTERING_BYPASS*/
+	#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_BYPASS
+	#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_BYPASS_OFFSET  58
+	#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_BYPASS_LEN     1
+	#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_BYPASS_DEFAULT 0x0
+	/*[field] SOURCE_FILTERING_MODE*/
+	#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_MODE
+	#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_MODE_OFFSET  59
+	#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_MODE_LEN     1
+	#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_MODE_DEFAULT 0x0
+
+struct cppe_mru_mtu_ctrl_tbl {
+	a_uint32_t  mru:14;
+	a_uint32_t  mru_cmd:2;
+	a_uint32_t  mtu:14;
+	a_uint32_t  mtu_cmd:2;
+	a_uint32_t  rx_cnt_en:1;
+	a_uint32_t  tx_cnt_en:1;
+	a_uint32_t  src_profile:2;
+	a_uint32_t  pcp_qos_group_id:1;
+	a_uint32_t  dscp_qos_group_id:1;
+	a_uint32_t  pcp_res_prec_force:1;
+	a_uint32_t  dscp_res_prec_force:1;
+	a_uint32_t  preheader_res_prec:3;
+	a_uint32_t  pcp_res_prec:3;
+	a_uint32_t  dscp_res_prec:3;
+	a_uint32_t  flow_res_prec:3;
+	a_uint32_t  pre_acl_res_prec:3;
+	a_uint32_t  post_acl_res_prec:3;
+	a_uint32_t  source_filtering_bypass:1;
+	a_uint32_t  source_filtering_mode:1;
+	a_uint32_t  _reserved0:4;
+};
+
+union cppe_mru_mtu_ctrl_tbl_u {
+	a_uint32_t val[2];
+	struct cppe_mru_mtu_ctrl_tbl bf;
+};
+
+struct cppe_port_phy_status_1 {
+	a_uint32_t  port5_pcs0_phy_status:8;
+	a_uint32_t  port4_pcs0_phy_status:8;
+	a_uint32_t  port5_pcs1_phy_status:8;
+	a_uint32_t  _reserved0:8;
+};
+
+union cppe_port_phy_status_1_u {
+	a_uint32_t val;
+	struct cppe_port_phy_status_1 bf;
+};
+
+#endif
\ No newline at end of file
diff --git a/qca-ssdk/include/hsl/cppe/cppe_qos.h b/qca-ssdk/include/hsl/cppe/cppe_qos.h
new file mode 100755
index 0000000..ae58396
--- /dev/null
+++ b/qca-ssdk/include/hsl/cppe/cppe_qos.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _CPPE_QOS_H_
+#define _CPPE_QOS_H_
+
+#define QOS_MAPPING_TBL_MAX_ENTRY	2592
+#define QOS_MAPPING_FLOW_TBL_MAX_ENTRY	2048
+#define QOS_MAPPING_DSCP_TBL_MAX_ENTRY	256
+#define QOS_MAPPING_PCP_TBL_MAX_ENTRY	16
+#define QOS_MAPPING_TBL_MAX_GROUP	2
+
+
+sw_error_t
+cppe_qos_mapping_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union qos_mapping_tbl_u *value);
+
+sw_error_t
+cppe_qos_mapping_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union qos_mapping_tbl_u *value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dei_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dei_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_qos_mapping_tbl_dscp_tc_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_qos_mapping_tbl_dscp_tc_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dscp_tc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dscp_tc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dp_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dp_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pri_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pri_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_qos_mapping_tbl_qos_res_prec_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_qos_mapping_tbl_qos_res_prec_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pcp_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pcp_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dscp_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dscp_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+#endif
\ No newline at end of file
diff --git a/qca-ssdk/include/hsl/cppe/cppe_qos_reg.h b/qca-ssdk/include/hsl/cppe/cppe_qos_reg.h
new file mode 100755
index 0000000..92e473b
--- /dev/null
+++ b/qca-ssdk/include/hsl/cppe/cppe_qos_reg.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _CPPE_QOS_REG_H_
+#define _CPPE_QOS_REG_H_
+
+/*[table] QOS_MAPPING_TBL*/
+#define QOS_MAPPING_TBL
+#define QOS_MAPPING_TBL_ADDRESS 0x20000
+#define QOS_MAPPING_TBL_NUM     2592
+#define QOS_MAPPING_TBL_INC     0x10
+#define QOS_MAPPING_TBL_TYPE    REG_TYPE_RW
+#define QOS_MAPPING_TBL_DEFAULT 0x0
+	/*[field] INT_DSCP_TC*/
+	#define QOS_MAPPING_TBL_INT_DSCP_TC
+	#define QOS_MAPPING_TBL_INT_DSCP_TC_OFFSET  0
+	#define QOS_MAPPING_TBL_INT_DSCP_TC_LEN     8
+	#define QOS_MAPPING_TBL_INT_DSCP_TC_DEFAULT 0x0
+	/*[field] DSCP_TC_MASK*/
+	#define QOS_MAPPING_TBL_DSCP_TC_MASK
+	#define QOS_MAPPING_TBL_DSCP_TC_MASK_OFFSET  8
+	#define QOS_MAPPING_TBL_DSCP_TC_MASK_LEN     8
+	#define QOS_MAPPING_TBL_DSCP_TC_MASK_DEFAULT 0x0
+	/*[field] INT_DSCP_EN*/
+	#define QOS_MAPPING_TBL_INT_DSCP_EN
+	#define QOS_MAPPING_TBL_INT_DSCP_EN_OFFSET  16
+	#define QOS_MAPPING_TBL_INT_DSCP_EN_LEN     1
+	#define QOS_MAPPING_TBL_INT_DSCP_EN_DEFAULT 0x0
+	/*[field] INT_PCP_EN*/
+	#define QOS_MAPPING_TBL_INT_PCP_EN
+	#define QOS_MAPPING_TBL_INT_PCP_EN_OFFSET  17
+	#define QOS_MAPPING_TBL_INT_PCP_EN_LEN     1
+	#define QOS_MAPPING_TBL_INT_PCP_EN_DEFAULT 0x0
+	/*[field] INT_PCP*/
+	#define QOS_MAPPING_TBL_INT_PCP
+	#define QOS_MAPPING_TBL_INT_PCP_OFFSET  18
+	#define QOS_MAPPING_TBL_INT_PCP_LEN     3
+	#define QOS_MAPPING_TBL_INT_PCP_DEFAULT 0x0
+	/*[field] INT_DEI_EN*/
+	#define QOS_MAPPING_TBL_INT_DEI_EN
+	#define QOS_MAPPING_TBL_INT_DEI_EN_OFFSET  21
+	#define QOS_MAPPING_TBL_INT_DEI_EN_LEN     1
+	#define QOS_MAPPING_TBL_INT_DEI_EN_DEFAULT 0x0
+	/*[field] INT_DEI*/
+	#define QOS_MAPPING_TBL_INT_DEI
+	#define QOS_MAPPING_TBL_INT_DEI_OFFSET  22
+	#define QOS_MAPPING_TBL_INT_DEI_LEN     1
+	#define QOS_MAPPING_TBL_INT_DEI_DEFAULT 0x0
+	/*[field] INT_PRI_EN*/
+	#define QOS_MAPPING_TBL_INT_PRI_EN
+	#define QOS_MAPPING_TBL_INT_PRI_EN_OFFSET  23
+	#define QOS_MAPPING_TBL_INT_PRI_EN_LEN     1
+	#define QOS_MAPPING_TBL_INT_PRI_EN_DEFAULT 0x0
+	/*[field] INT_PRI*/
+	#define QOS_MAPPING_TBL_INT_PRI
+	#define QOS_MAPPING_TBL_INT_PRI_OFFSET  24
+	#define QOS_MAPPING_TBL_INT_PRI_LEN     4
+	#define QOS_MAPPING_TBL_INT_PRI_DEFAULT 0x0
+	/*[field] INT_DP_EN*/
+	#define QOS_MAPPING_TBL_INT_DP_EN
+	#define QOS_MAPPING_TBL_INT_DP_EN_OFFSET  28
+	#define QOS_MAPPING_TBL_INT_DP_EN_LEN     1
+	#define QOS_MAPPING_TBL_INT_DP_EN_DEFAULT 0x0
+	/*[field] INT_DP*/
+	#define QOS_MAPPING_TBL_INT_DP
+	#define QOS_MAPPING_TBL_INT_DP_OFFSET  29
+	#define QOS_MAPPING_TBL_INT_DP_LEN     2
+	#define QOS_MAPPING_TBL_INT_DP_DEFAULT 0x0
+	/*[field] QOS_RES_PREC*/
+	#define QOS_MAPPING_TBL_QOS_RES_PREC
+	#define QOS_MAPPING_TBL_QOS_RES_PREC_OFFSET  31
+	#define QOS_MAPPING_TBL_QOS_RES_PREC_LEN     3
+	#define QOS_MAPPING_TBL_QOS_RES_PREC_DEFAULT 0x0
+
+struct qos_mapping_tbl {
+	a_uint32_t  int_dscp_tc:8;
+	a_uint32_t  dscp_tc_mask:8;
+	a_uint32_t  int_dscp_en:1;
+	a_uint32_t  int_pcp_en:1;
+	a_uint32_t  int_pcp:3;
+	a_uint32_t  int_dei_en:1;
+	a_uint32_t  int_dei:1;
+	a_uint32_t  int_pri_en:1;
+	a_uint32_t  int_pri:4;
+	a_uint32_t  int_dp_en:1;
+	a_uint32_t  int_dp:2;
+	a_uint32_t  qos_res_prec_0:1;
+	a_uint32_t  qos_res_prec_1:2;
+	a_uint32_t  _reserved0:30;
+};
+
+union qos_mapping_tbl_u {
+	a_uint32_t val[2];
+	struct qos_mapping_tbl bf;
+};
+
+#endif
\ No newline at end of file
diff --git a/qca-ssdk/include/hsl/dess/dess_acl.h b/qca-ssdk/include/hsl/dess/dess_acl.h
new file mode 100755
index 0000000..76e8fee
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_acl.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_acl DESS_ACL
+ * @{
+ */
+#ifndef _DESS_ACL_H_
+#define _DESS_ACL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_acl.h"
+
+    sw_error_t dess_acl_init(a_uint32_t dev_id);
+
+    sw_error_t dess_acl_reset(a_uint32_t dev_id);
+
+    sw_error_t dess_acl_cleanup(a_uint32_t dev_id);
+
+
+#ifdef IN_ACL
+#define DESS_ACL_INIT(rv, dev_id) \
+    { \
+        rv = dess_acl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define DESS_ACL_RESET(rv, dev_id) \
+    { \
+        rv = dess_acl_reset(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define DESS_ACL_CLEANUP(rv, dev_id) \
+    { \
+        rv = dess_acl_cleanup(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_ACL_INIT(rv, dev_id)
+#define DESS_ACL_RESET(rv, dev_id)
+#define DESS_ACL_CLEANUP(rv, dev_id)
+#endif
+
+    sw_error_t
+    dess_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+                        a_uint32_t list_pri);
+
+    sw_error_t
+    dess_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+                      a_uint32_t rule_id, a_uint32_t rule_nr,
+                      fal_acl_rule_t * rule);
+
+    sw_error_t
+    dess_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+                         a_uint32_t rule_id, a_uint32_t rule_nr);
+
+    a_uint32_t
+    dess_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id);
+
+    sw_error_t
+    dess_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                       fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                       a_uint32_t obj_idx);
+
+    sw_error_t
+    dess_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                         fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                         a_uint32_t obj_idx);
+
+    sw_error_t
+    dess_acl_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    sw_error_t
+    dess_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+                        a_uint32_t rule_id, fal_acl_rule_t * rule);
+
+    sw_error_t
+    dess_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act);
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    dess_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id);
+
+    HSL_LOCAL sw_error_t
+    dess_acl_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_acl_list_dump(a_uint32_t dev_id);
+
+    HSL_LOCAL sw_error_t
+    dess_acl_rule_dump(a_uint32_t dev_id);
+
+    HSL_LOCAL sw_error_t
+    dess_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_acl_udf_type_t udf_type,
+                                  a_uint32_t offset, a_uint32_t length);
+
+    HSL_LOCAL sw_error_t
+    dess_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_acl_udf_type_t udf_type,
+                                  a_uint32_t * offset, a_uint32_t * length);
+
+    HSL_LOCAL sw_error_t
+    dess_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+                         a_uint32_t rule_id, a_uint32_t rule_nr);
+
+    HSL_LOCAL sw_error_t
+    dess_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+                           a_uint32_t rule_id, a_uint32_t rule_nr);
+    HSL_LOCAL sw_error_t
+    dess_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+                                     a_uint32_t rule_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
+                                     a_uint32_t rule_id, a_bool_t* enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_ACL_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/dess/dess_api.h b/qca-ssdk/include/hsl/dess/dess_api.h
new file mode 100755
index 0000000..7b92fbd
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_api.h
@@ -0,0 +1,1174 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _DESS_API_H_
+#define _DESS_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#ifdef IN_PORTCONTROL
+#define PORTCONTROL_API \
+    SW_API_DEF(SW_API_PT_DUPLEX_GET, dess_port_duplex_get), \
+    SW_API_DEF(SW_API_PT_DUPLEX_SET, dess_port_duplex_set), \
+    SW_API_DEF(SW_API_PT_SPEED_GET, dess_port_speed_get), \
+    SW_API_DEF(SW_API_PT_SPEED_SET, dess_port_speed_set), \
+    SW_API_DEF(SW_API_PT_AN_GET, dess_port_autoneg_status_get), \
+    SW_API_DEF(SW_API_PT_AN_ENABLE, dess_port_autoneg_enable), \
+    SW_API_DEF(SW_API_PT_AN_RESTART, dess_port_autoneg_restart), \
+    SW_API_DEF(SW_API_PT_AN_ADV_GET, dess_port_autoneg_adv_get), \
+    SW_API_DEF(SW_API_PT_AN_ADV_SET, dess_port_autoneg_adv_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_SET, dess_port_flowctrl_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_GET, dess_port_flowctrl_get), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, dess_port_flowctrl_forcemode_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, dess_port_flowctrl_forcemode_get), \
+    SW_API_DEF(SW_API_PT_POWERSAVE_SET, dess_port_powersave_set), \
+    SW_API_DEF(SW_API_PT_POWERSAVE_GET, dess_port_powersave_get), \
+    SW_API_DEF(SW_API_PT_HIBERNATE_SET, dess_port_hibernate_set), \
+    SW_API_DEF(SW_API_PT_HIBERNATE_GET, dess_port_hibernate_get), \
+    SW_API_DEF(SW_API_PT_CDT, dess_port_cdt), \
+    SW_API_DEF(SW_API_PT_TXHDR_SET, dess_port_txhdr_mode_set), \
+    SW_API_DEF(SW_API_PT_TXHDR_GET, dess_port_txhdr_mode_get), \
+    SW_API_DEF(SW_API_PT_RXHDR_SET, dess_port_rxhdr_mode_set), \
+    SW_API_DEF(SW_API_PT_RXHDR_GET, dess_port_rxhdr_mode_get), \
+    SW_API_DEF(SW_API_HEADER_TYPE_SET, dess_header_type_set),  \
+    SW_API_DEF(SW_API_HEADER_TYPE_GET, dess_header_type_get), \
+    SW_API_DEF(SW_API_TXMAC_STATUS_SET, dess_port_txmac_status_set), \
+    SW_API_DEF(SW_API_TXMAC_STATUS_GET, dess_port_txmac_status_get), \
+    SW_API_DEF(SW_API_RXMAC_STATUS_SET, dess_port_rxmac_status_set), \
+    SW_API_DEF(SW_API_RXMAC_STATUS_GET, dess_port_rxmac_status_get), \
+    SW_API_DEF(SW_API_TXFC_STATUS_SET, dess_port_txfc_status_set),   \
+    SW_API_DEF(SW_API_TXFC_STATUS_GET, dess_port_txfc_status_get),   \
+    SW_API_DEF(SW_API_RXFC_STATUS_SET, dess_port_rxfc_status_set),   \
+    SW_API_DEF(SW_API_RXFC_STATUS_GET, dess_port_rxfc_status_get),   \
+    SW_API_DEF(SW_API_BP_STATUS_SET, dess_port_bp_status_set),   \
+    SW_API_DEF(SW_API_BP_STATUS_GET, dess_port_bp_status_get),   \
+    SW_API_DEF(SW_API_PT_LINK_MODE_SET, dess_port_link_forcemode_set),   \
+    SW_API_DEF(SW_API_PT_LINK_MODE_GET, dess_port_link_forcemode_get), \
+    SW_API_DEF(SW_API_PT_LINK_STATUS_GET, dess_port_link_status_get), \
+    SW_API_DEF(SW_API_PT_MAC_LOOPBACK_SET, dess_port_mac_loopback_set), \
+    SW_API_DEF(SW_API_PT_MAC_LOOPBACK_GET, dess_port_mac_loopback_get), \
+    SW_API_DEF(SW_API_PT_CONGESTION_DROP_SET, dess_port_congestion_drop_set), \
+    SW_API_DEF(SW_API_PT_CONGESTION_DROP_GET, dess_port_congestion_drop_get), \
+    SW_API_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_SET, dess_ring_flow_ctrl_thres_set), \
+    SW_API_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_GET, dess_ring_flow_ctrl_thres_get),\
+    SW_API_DEF(SW_API_PT_8023AZ_SET, dess_port_8023az_set), \
+    SW_API_DEF(SW_API_PT_8023AZ_GET, dess_port_8023az_get), \
+    SW_API_DEF(SW_API_PT_MDIX_SET, dess_port_mdix_set), \
+    SW_API_DEF(SW_API_PT_MDIX_GET, dess_port_mdix_get), \
+    SW_API_DEF(SW_API_PT_MDIX_STATUS_GET, dess_port_mdix_status_get), \
+    SW_API_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_SET, dess_port_combo_prefer_medium_set), \
+    SW_API_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_GET, dess_port_combo_prefer_medium_get), \
+    SW_API_DEF(SW_API_PT_COMBO_MEDIUM_STATUS_GET, dess_port_combo_medium_status_get), \
+    SW_API_DEF(SW_API_PT_COMBO_FIBER_MODE_SET, dess_port_combo_fiber_mode_set), \
+    SW_API_DEF(SW_API_PT_COMBO_FIBER_MODE_GET, dess_port_combo_fiber_mode_get), \
+    SW_API_DEF(SW_API_PT_LOCAL_LOOPBACK_SET, dess_port_local_loopback_set), \
+    SW_API_DEF(SW_API_PT_LOCAL_LOOPBACK_GET, dess_port_local_loopback_get), \
+    SW_API_DEF(SW_API_PT_REMOTE_LOOPBACK_SET, dess_port_remote_loopback_set), \
+    SW_API_DEF(SW_API_PT_REMOTE_LOOPBACK_GET, dess_port_remote_loopback_get), \
+    SW_API_DEF(SW_API_PT_RESET, dess_port_reset), \
+    SW_API_DEF(SW_API_PT_POWER_OFF, dess_port_power_off), \
+    SW_API_DEF(SW_API_PT_POWER_ON, dess_port_power_on),
+
+#define PORTCONTROL_API_PARAM \
+    SW_API_DESC(SW_API_PT_DUPLEX_GET) \
+    SW_API_DESC(SW_API_PT_DUPLEX_SET) \
+    SW_API_DESC(SW_API_PT_SPEED_GET)  \
+    SW_API_DESC(SW_API_PT_SPEED_SET)  \
+    SW_API_DESC(SW_API_PT_AN_GET)  \
+    SW_API_DESC(SW_API_PT_AN_ENABLE)   \
+    SW_API_DESC(SW_API_PT_AN_RESTART)  \
+    SW_API_DESC(SW_API_PT_AN_ADV_GET)  \
+    SW_API_DESC(SW_API_PT_AN_ADV_SET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_SET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_GET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \
+    SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
+    SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
+    SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
+    SW_API_DESC(SW_API_PT_HIBERNATE_GET) \
+    SW_API_DESC(SW_API_PT_CDT) \
+    SW_API_DESC(SW_API_PT_TXHDR_SET) \
+    SW_API_DESC(SW_API_PT_TXHDR_GET) \
+    SW_API_DESC(SW_API_PT_RXHDR_SET) \
+    SW_API_DESC(SW_API_PT_RXHDR_GET) \
+    SW_API_DESC(SW_API_HEADER_TYPE_SET) \
+    SW_API_DESC(SW_API_HEADER_TYPE_GET) \
+    SW_API_DESC(SW_API_TXMAC_STATUS_SET) \
+    SW_API_DESC(SW_API_TXMAC_STATUS_GET) \
+    SW_API_DESC(SW_API_RXMAC_STATUS_SET) \
+    SW_API_DESC(SW_API_RXMAC_STATUS_GET) \
+    SW_API_DESC(SW_API_TXFC_STATUS_SET) \
+    SW_API_DESC(SW_API_TXFC_STATUS_GET) \
+    SW_API_DESC(SW_API_RXFC_STATUS_SET) \
+    SW_API_DESC(SW_API_RXFC_STATUS_GET) \
+    SW_API_DESC(SW_API_BP_STATUS_SET) \
+    SW_API_DESC(SW_API_BP_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_LINK_MODE_SET) \
+    SW_API_DESC(SW_API_PT_LINK_MODE_GET) \
+    SW_API_DESC(SW_API_PT_LINK_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_MAC_LOOPBACK_SET) \
+    SW_API_DESC(SW_API_PT_MAC_LOOPBACK_GET) \
+    SW_API_DESC(SW_API_PT_CONGESTION_DROP_SET) \
+    SW_API_DESC(SW_API_PT_CONGESTION_DROP_GET) \
+    SW_API_DESC(SW_API_PT_RING_FLOW_CTRL_THRES_SET) \
+    SW_API_DESC(SW_API_PT_RING_FLOW_CTRL_THRES_GET)\
+    SW_API_DESC(SW_API_PT_8023AZ_SET) \
+    SW_API_DESC(SW_API_PT_8023AZ_GET) \
+    SW_API_DESC(SW_API_PT_MDIX_SET) \
+    SW_API_DESC(SW_API_PT_MDIX_GET) \
+    SW_API_DESC(SW_API_PT_MDIX_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_COMBO_PREFER_MEDIUM_SET) \
+    SW_API_DESC(SW_API_PT_COMBO_PREFER_MEDIUM_GET) \
+    SW_API_DESC(SW_API_PT_COMBO_MEDIUM_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_COMBO_FIBER_MODE_SET) \
+    SW_API_DESC(SW_API_PT_COMBO_FIBER_MODE_GET) \
+    SW_API_DESC(SW_API_PT_LOCAL_LOOPBACK_SET) \
+    SW_API_DESC(SW_API_PT_LOCAL_LOOPBACK_GET) \
+    SW_API_DESC(SW_API_PT_REMOTE_LOOPBACK_SET) \
+    SW_API_DESC(SW_API_PT_REMOTE_LOOPBACK_GET) \
+    SW_API_DESC(SW_API_PT_RESET) \
+    SW_API_DESC(SW_API_PT_POWER_OFF) \
+    SW_API_DESC(SW_API_PT_POWER_ON)
+
+#else
+#define PORTCONTROL_API
+#define PORTCONTROL_API_PARAM
+#endif
+
+#ifdef IN_VLAN
+#define VLAN_API \
+    SW_API_DEF(SW_API_VLAN_ADD, dess_vlan_create), \
+    SW_API_DEF(SW_API_VLAN_DEL, dess_vlan_delete), \
+    SW_API_DEF(SW_API_VLAN_FIND, dess_vlan_find), \
+    SW_API_DEF(SW_API_VLAN_NEXT, dess_vlan_next), \
+    SW_API_DEF(SW_API_VLAN_APPEND, dess_vlan_entry_append), \
+    SW_API_DEF(SW_API_VLAN_FLUSH, dess_vlan_flush), \
+    SW_API_DEF(SW_API_VLAN_FID_SET, dess_vlan_fid_set), \
+    SW_API_DEF(SW_API_VLAN_FID_GET, dess_vlan_fid_get), \
+    SW_API_DEF(SW_API_VLAN_MEMBER_ADD, dess_vlan_member_add), \
+    SW_API_DEF(SW_API_VLAN_MEMBER_DEL, dess_vlan_member_del), \
+    SW_API_DEF(SW_API_VLAN_LEARN_STATE_SET, dess_vlan_learning_state_set), \
+    SW_API_DEF(SW_API_VLAN_LEARN_STATE_GET, dess_vlan_learning_state_get),
+
+#define VLAN_API_PARAM \
+    SW_API_DESC(SW_API_VLAN_ADD)     \
+    SW_API_DESC(SW_API_VLAN_DEL)     \
+    SW_API_DESC(SW_API_VLAN_FIND)    \
+    SW_API_DESC(SW_API_VLAN_NEXT)    \
+    SW_API_DESC(SW_API_VLAN_APPEND)  \
+    SW_API_DESC(SW_API_VLAN_FLUSH)   \
+    SW_API_DESC(SW_API_VLAN_FID_SET) \
+    SW_API_DESC(SW_API_VLAN_FID_GET) \
+    SW_API_DESC(SW_API_VLAN_MEMBER_ADD) \
+    SW_API_DESC(SW_API_VLAN_MEMBER_DEL) \
+    SW_API_DESC(SW_API_VLAN_LEARN_STATE_SET) \
+    SW_API_DESC(SW_API_VLAN_LEARN_STATE_GET)
+#else
+#define VLAN_API
+#define VLAN_API_PARAM
+#endif
+
+#ifdef IN_PORTVLAN
+#define PORTVLAN_API \
+    SW_API_DEF(SW_API_PT_ING_MODE_GET, dess_port_1qmode_get), \
+    SW_API_DEF(SW_API_PT_ING_MODE_SET, dess_port_1qmode_set), \
+    SW_API_DEF(SW_API_PT_EG_MODE_GET, dess_port_egvlanmode_get), \
+    SW_API_DEF(SW_API_PT_EG_MODE_SET, dess_port_egvlanmode_set), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, dess_portvlan_member_add), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, dess_portvlan_member_del), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, dess_portvlan_member_update), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_GET, dess_portvlan_member_get), \
+    SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, dess_port_force_default_vid_set), \
+    SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, dess_port_force_default_vid_get), \
+    SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, dess_port_force_portvlan_set), \
+    SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, dess_port_force_portvlan_get), \
+    SW_API_DEF(SW_API_NESTVLAN_TPID_SET, dess_nestvlan_tpid_set), \
+    SW_API_DEF(SW_API_NESTVLAN_TPID_GET, dess_nestvlan_tpid_get), \
+    SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, dess_port_invlan_mode_set), \
+    SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, dess_port_invlan_mode_get), \
+    SW_API_DEF(SW_API_PT_TLS_SET, dess_port_tls_set), \
+    SW_API_DEF(SW_API_PT_TLS_GET, dess_port_tls_get), \
+    SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, dess_port_pri_propagation_set), \
+    SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, dess_port_pri_propagation_get), \
+    SW_API_DEF(SW_API_PT_DEF_SVID_SET, dess_port_default_svid_set), \
+    SW_API_DEF(SW_API_PT_DEF_SVID_GET, dess_port_default_svid_get), \
+    SW_API_DEF(SW_API_PT_DEF_CVID_SET, dess_port_default_cvid_set), \
+    SW_API_DEF(SW_API_PT_DEF_CVID_GET, dess_port_default_cvid_get), \
+    SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_SET, dess_port_vlan_propagation_set), \
+    SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_GET, dess_port_vlan_propagation_get), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, dess_port_vlan_trans_add), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_DEL, dess_port_vlan_trans_del), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_GET, dess_port_vlan_trans_get), \
+    SW_API_DEF(SW_API_QINQ_MODE_SET, dess_qinq_mode_set), \
+    SW_API_DEF(SW_API_QINQ_MODE_GET, dess_qinq_mode_get), \
+    SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, dess_port_qinq_role_set), \
+    SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, dess_port_qinq_role_get), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ITERATE, dess_port_vlan_trans_iterate), \
+    SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_SET, dess_port_mac_vlan_xlt_set), \
+    SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_GET, dess_port_mac_vlan_xlt_get), \
+    SW_API_DEF(SW_API_NETISOLATE_SET, dess_netisolate_set), \
+    SW_API_DEF(SW_API_NETISOLATE_GET, dess_netisolate_get),\
+    SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_SET, dess_eg_trans_filter_bypass_en_set), \
+    SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_GET, dess_eg_trans_filter_bypass_en_get),
+
+
+#define PORTVLAN_API_PARAM \
+    SW_API_DESC(SW_API_PT_ING_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_ING_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_EG_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_EG_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE)  \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_GET)     \
+    SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET)    \
+    SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET)    \
+    SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET)   \
+    SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET)   \
+    SW_API_DESC(SW_API_NESTVLAN_TPID_SET)    \
+    SW_API_DESC(SW_API_NESTVLAN_TPID_GET)    \
+    SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET)    \
+    SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET)    \
+    SW_API_DESC(SW_API_PT_TLS_SET)    \
+    SW_API_DESC(SW_API_PT_TLS_GET)    \
+    SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET)    \
+    SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET)    \
+    SW_API_DESC(SW_API_PT_DEF_SVID_SET)    \
+    SW_API_DESC(SW_API_PT_DEF_SVID_GET)    \
+    SW_API_DESC(SW_API_PT_DEF_CVID_SET)    \
+    SW_API_DESC(SW_API_PT_DEF_CVID_GET)    \
+    SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_SET)    \
+    SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_GET)    \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD)  \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_DEL)  \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_GET)  \
+    SW_API_DESC(SW_API_QINQ_MODE_SET)      \
+    SW_API_DESC(SW_API_QINQ_MODE_GET)      \
+    SW_API_DESC(SW_API_PT_QINQ_ROLE_SET)   \
+    SW_API_DESC(SW_API_PT_QINQ_ROLE_GET)   \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ITERATE) \
+    SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_SET)   \
+    SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_GET)  \
+    SW_API_DESC(SW_API_NETISOLATE_SET)   \
+    SW_API_DESC(SW_API_NETISOLATE_GET)   \
+    SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_SET) \
+    SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_GET)
+
+#else
+#define PORTVLAN_API
+#define PORTVLAN_API_PARAM
+#endif
+
+#ifdef IN_FDB
+#define FDB_API \
+    SW_API_DEF(SW_API_FDB_ADD, dess_fdb_add), \
+    SW_API_DEF(SW_API_FDB_DELALL, dess_fdb_del_all), \
+    SW_API_DEF(SW_API_FDB_DELPORT,dess_fdb_del_by_port), \
+    SW_API_DEF(SW_API_FDB_DELMAC, dess_fdb_del_by_mac), \
+    SW_API_DEF(SW_API_FDB_FIND,   dess_fdb_find), \
+    SW_API_DEF(SW_API_FDB_EXTEND_NEXT,    dess_fdb_extend_next),  \
+    SW_API_DEF(SW_API_FDB_EXTEND_FIRST,   dess_fdb_extend_first),  \
+    SW_API_DEF(SW_API_FDB_TRANSFER,       dess_fdb_transfer),  \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_SET,   dess_fdb_port_learn_set), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_GET,   dess_fdb_port_learn_get), \
+    SW_API_DEF(SW_API_FDB_AGE_CTRL_SET,   dess_fdb_age_ctrl_set), \
+    SW_API_DEF(SW_API_FDB_AGE_CTRL_GET,   dess_fdb_age_ctrl_get), \
+    SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_SET, dess_fdb_vlan_ivl_svl_set),\
+    SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_GET, dess_fdb_vlan_ivl_svl_get),\
+    SW_API_DEF(SW_API_FDB_AGE_TIME_SET,   dess_fdb_age_time_set), \
+    SW_API_DEF(SW_API_FDB_AGE_TIME_GET,   dess_fdb_age_time_get), \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET,    dess_port_fdb_learn_limit_set),  \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET,    dess_port_fdb_learn_limit_get),  \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET,    dess_port_fdb_learn_exceed_cmd_set),  \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET,    dess_port_fdb_learn_exceed_cmd_get), \
+    SW_API_DEF(SW_API_FDB_LEARN_LIMIT_SET,    dess_fdb_learn_limit_set),  \
+    SW_API_DEF(SW_API_FDB_LEARN_LIMIT_GET,    dess_fdb_learn_limit_get),  \
+    SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET,    dess_fdb_learn_exceed_cmd_set),  \
+    SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET,    dess_fdb_learn_exceed_cmd_get),  \
+    SW_API_DEF(SW_API_FDB_RESV_ADD, dess_fdb_resv_add), \
+    SW_API_DEF(SW_API_FDB_RESV_DEL, dess_fdb_resv_del), \
+    SW_API_DEF(SW_API_FDB_RESV_FIND, dess_fdb_resv_find), \
+    SW_API_DEF(SW_API_FDB_RESV_ITERATE, dess_fdb_resv_iterate), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_SET,   dess_fdb_port_learn_static_set), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_GET,   dess_fdb_port_learn_static_get), \
+    SW_API_DEF(SW_API_FDB_PORT_ADD,   dess_fdb_port_add), \
+    SW_API_DEF(SW_API_FDB_PORT_DEL,   dess_fdb_port_del),
+
+#define FDB_API_PARAM \
+    SW_API_DESC(SW_API_FDB_ADD) \
+    SW_API_DESC(SW_API_FDB_DELALL)  \
+    SW_API_DESC(SW_API_FDB_DELPORT) \
+    SW_API_DESC(SW_API_FDB_DELMAC) \
+    SW_API_DESC(SW_API_FDB_FIND) \
+    SW_API_DESC(SW_API_FDB_EXTEND_NEXT)  \
+    SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \
+    SW_API_DESC(SW_API_FDB_TRANSFER) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \
+    SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \
+    SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \
+    SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_SET) \
+    SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_GET) \
+    SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \
+    SW_API_DESC(SW_API_FDB_AGE_TIME_GET) \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_SET)  \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_GET)  \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET)  \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_LIMIT_SET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_LIMIT_GET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_SET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_GET)  \
+    SW_API_DESC(SW_API_FDB_RESV_ADD)  \
+    SW_API_DESC(SW_API_FDB_RESV_DEL)  \
+    SW_API_DESC(SW_API_FDB_RESV_FIND) \
+    SW_API_DESC(SW_API_FDB_RESV_ITERATE) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_SET) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_GET) \
+    SW_API_DESC(SW_API_FDB_PORT_ADD)  \
+    SW_API_DESC(SW_API_FDB_PORT_DEL)
+
+#else
+#define FDB_API
+#define FDB_API_PARAM
+#endif
+
+
+#ifdef IN_ACL
+#define ACL_API \
+    SW_API_DEF(SW_API_ACL_LIST_CREAT, dess_acl_list_creat), \
+    SW_API_DEF(SW_API_ACL_LIST_DESTROY, dess_acl_list_destroy), \
+    SW_API_DEF(SW_API_ACL_RULE_ADD, dess_acl_rule_add), \
+    SW_API_DEF(SW_API_ACL_RULE_DELETE, dess_acl_rule_delete), \
+    SW_API_DEF(SW_API_ACL_RULE_QUERY, dess_acl_rule_query), \
+    SW_API_DEF(SW_API_ACL_LIST_BIND, dess_acl_list_bind), \
+    SW_API_DEF(SW_API_ACL_LIST_UNBIND, dess_acl_list_unbind), \
+    SW_API_DEF(SW_API_ACL_STATUS_SET, dess_acl_status_set), \
+    SW_API_DEF(SW_API_ACL_STATUS_GET, dess_acl_status_get), \
+    SW_API_DEF(SW_API_ACL_LIST_DUMP, dess_acl_list_dump), \
+    SW_API_DEF(SW_API_ACL_RULE_DUMP, dess_acl_rule_dump), \
+    SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, dessort_udf_profile_set), \
+    SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, dess_acl_port_udf_profile_get), \
+    SW_API_DEF(SW_API_ACL_RULE_ACTIVE, dess_acl_rule_active), \
+    SW_API_DEF(SW_API_ACL_RULE_DEACTIVE, dess_acl_rule_deactive),\
+    SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, dess_acl_rule_src_filter_sts_set),\
+    SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, dess_acl_rule_src_filter_sts_get), \
+    SW_API_DEF(SW_API_ACL_RULE_GET_OFFSET, dess_acl_rule_get_offset),
+
+#define ACL_API_PARAM \
+    SW_API_DESC(SW_API_ACL_LIST_CREAT)   \
+    SW_API_DESC(SW_API_ACL_LIST_DESTROY) \
+    SW_API_DESC(SW_API_ACL_RULE_ADD)     \
+    SW_API_DESC(SW_API_ACL_RULE_DELETE)  \
+    SW_API_DESC(SW_API_ACL_RULE_QUERY)   \
+    SW_API_DESC(SW_API_ACL_LIST_BIND)    \
+    SW_API_DESC(SW_API_ACL_LIST_UNBIND)  \
+    SW_API_DESC(SW_API_ACL_STATUS_SET)   \
+    SW_API_DESC(SW_API_ACL_STATUS_GET)   \
+    SW_API_DESC(SW_API_ACL_LIST_DUMP)    \
+    SW_API_DESC(SW_API_ACL_RULE_DUMP)    \
+    SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_SET)    \
+    SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_GET)    \
+    SW_API_DESC(SW_API_ACL_RULE_ACTIVE)    \
+    SW_API_DESC(SW_API_ACL_RULE_DEACTIVE) \
+    SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_SET) \
+    SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_GET)
+#else
+#define ACL_API
+#define ACL_API_PARAM
+#endif
+
+
+#ifdef IN_QOS
+#define QOS_API \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, dess_qos_queue_tx_buf_status_set), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, dess_qos_queue_tx_buf_status_get), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, dess_qos_queue_tx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, dess_qos_queue_tx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, dess_qos_port_tx_buf_status_set), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, dess_qos_port_tx_buf_status_get), \
+    SW_API_DEF(SW_API_QOS_PT_RED_EN_SET, dess_qos_port_red_en_set),\
+    SW_API_DEF(SW_API_QOS_PT_RED_EN_GET, dess_qos_port_red_en_get),\
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, dess_qos_port_tx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, dess_qos_port_tx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, dess_qos_port_rx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, dess_qos_port_rx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_SET, dess_qos_port_mode_set), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_GET, dess_qos_port_mode_get), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, dess_qos_port_mode_pri_set), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, dess_qos_port_mode_pri_get), \
+    SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, dess_qos_port_sch_mode_set), \
+    SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, dess_qos_port_sch_mode_get), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_SET, dess_qos_port_default_spri_set), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_GET, dess_qos_port_default_spri_get), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_SET, dess_qos_port_default_cpri_set), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_GET, dess_qos_port_default_cpri_get), \
+    SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, dess_qos_port_force_spri_status_set), \
+    SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, dess_qos_port_force_spri_status_get), \
+    SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, dess_qos_port_force_cpri_status_set), \
+    SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, dess_qos_port_force_cpri_status_get), \
+    SW_API_DEF(SW_API_QOS_QUEUE_REMARK_SET, dess_qos_queue_remark_table_set), \
+    SW_API_DEF(SW_API_QOS_QUEUE_REMARK_GET, dess_qos_queue_remark_table_get),
+
+
+#define QOS_API_PARAM \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \
+    SW_API_DESC(SW_API_QOS_PT_RED_EN_SET) \
+    SW_API_DESC(SW_API_QOS_PT_RED_EN_GET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_SET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_GET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET) \
+    SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_SET)  \
+    SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_GET)  \
+    SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_SET)  \
+    SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_GET)  \
+    SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_SET)  \
+    SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_GET)  \
+    SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_SET)  \
+    SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_GET)  \
+    SW_API_DESC(SW_API_QOS_QUEUE_REMARK_SET) \
+    SW_API_DESC(SW_API_QOS_QUEUE_REMARK_GET)
+#else
+#define QOS_API
+#define QOS_API_PARAM
+#endif
+
+
+#ifdef IN_IGMP
+#define IGMP_API \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, dess_port_igmps_status_set), \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, dess_port_igmps_status_get), \
+    SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, dess_igmp_mld_cmd_set), \
+    SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, dess_igmp_mld_cmd_get), \
+    SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, dess_port_igmp_mld_join_set), \
+    SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, dess_port_igmp_mld_join_get), \
+    SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, dess_port_igmp_mld_leave_set), \
+    SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, dess_port_igmp_mld_leave_get), \
+    SW_API_DEF(SW_API_IGMP_RP_SET, dess_igmp_mld_rp_set), \
+    SW_API_DEF(SW_API_IGMP_RP_GET, dess_igmp_mld_rp_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, dess_igmp_mld_entry_creat_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, dess_igmp_mld_entry_creat_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, dess_igmp_mld_entry_static_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, dess_igmp_mld_entry_static_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, dess_igmp_mld_entry_leaky_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, dess_igmp_mld_entry_leaky_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, dess_igmp_mld_entry_v3_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, dess_igmp_mld_entry_v3_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, dess_igmp_mld_entry_queue_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, dess_igmp_mld_entry_queue_get), \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET,    dess_port_igmp_mld_learn_limit_set),  \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET,    dess_port_igmp_mld_learn_limit_get),  \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET,    dess_port_igmp_mld_learn_exceed_cmd_set),  \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET,    dess_port_igmp_mld_learn_exceed_cmd_get), \
+    SW_API_DEF(SW_API_IGMP_SG_ENTRY_SET,    dess_igmp_sg_entry_set),  \
+    SW_API_DEF(SW_API_IGMP_SG_ENTRY_CLEAR,    dess_igmp_sg_entry_clear),  \
+    SW_API_DEF(SW_API_IGMP_SG_ENTRY_SHOW,    dess_igmp_sg_entry_show),
+
+#define IGMP_API_PARAM \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
+    SW_API_DESC(SW_API_IGMP_MLD_CMD_SET)  \
+    SW_API_DESC(SW_API_IGMP_MLD_CMD_GET)  \
+    SW_API_DESC(SW_API_IGMP_PT_JOIN_SET)  \
+    SW_API_DESC(SW_API_IGMP_PT_JOIN_GET)  \
+    SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \
+    SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \
+    SW_API_DESC(SW_API_IGMP_RP_SET)  \
+    SW_API_DESC(SW_API_IGMP_RP_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_SET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_GET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET) \
+    SW_API_DESC(SW_API_IGMP_SG_ENTRY_SET) \
+    SW_API_DESC(SW_API_IGMP_SG_ENTRY_CLEAR) \
+    SW_API_DESC(SW_API_IGMP_SG_ENTRY_SHOW)
+#else
+#define IGMP_API
+#define IGMP_API_PARAM
+#endif
+
+
+#ifdef IN_LEAKY
+#define LEAKY_API \
+    SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, dess_uc_leaky_mode_set), \
+    SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, dess_uc_leaky_mode_get), \
+    SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, dess_mc_leaky_mode_set), \
+    SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, dess_mc_leaky_mode_get), \
+    SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, dess_port_arp_leaky_set), \
+    SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, dess_port_arp_leaky_get), \
+    SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, dess_port_uc_leaky_set), \
+    SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, dess_port_uc_leaky_get), \
+    SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, dess_port_mc_leaky_set), \
+    SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, dess_port_mc_leaky_get),
+
+#define LEAKY_API_PARAM \
+    SW_API_DESC(SW_API_UC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_UC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_MC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_MC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \
+    SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \
+    SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET)
+#else
+#define LEAKY_API
+#define LEAKY_API_PARAM
+#endif
+
+
+#ifdef IN_MIRROR
+#define MIRROR_API \
+    SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, dess_mirr_analysis_port_set), \
+    SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, dess_mirr_analysis_port_get), \
+    SW_API_DEF(SW_API_MIRROR_IN_PT_SET, dess_mirr_port_in_set), \
+    SW_API_DEF(SW_API_MIRROR_IN_PT_GET, dess_mirr_port_in_get), \
+    SW_API_DEF(SW_API_MIRROR_EG_PT_SET, dess_mirr_port_eg_set), \
+    SW_API_DEF(SW_API_MIRROR_EG_PT_GET, dess_mirr_port_eg_get),
+
+#define MIRROR_API_PARAM \
+    SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET)  \
+    SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET)  \
+    SW_API_DESC(SW_API_MIRROR_IN_PT_SET)  \
+    SW_API_DESC(SW_API_MIRROR_IN_PT_GET)  \
+    SW_API_DESC(SW_API_MIRROR_EG_PT_SET)  \
+    SW_API_DESC(SW_API_MIRROR_EG_PT_GET)
+#else
+#define MIRROR_API
+#define MIRROR_API_PARAM
+#endif
+
+
+#ifdef IN_RATE
+#define RATE_API \
+    SW_API_DEF(SW_API_RATE_PORT_POLICER_SET, dess_rate_port_policer_set), \
+    SW_API_DEF(SW_API_RATE_PORT_POLICER_GET, dess_rate_port_policer_get), \
+    SW_API_DEF(SW_API_RATE_PORT_SHAPER_SET, dess_rate_port_shaper_set), \
+    SW_API_DEF(SW_API_RATE_PORT_SHAPER_GET, dess_rate_port_shaper_get), \
+    SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_SET, dess_rate_queue_shaper_set), \
+    SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_GET, dess_rate_queue_shaper_get), \
+    SW_API_DEF(SW_API_RATE_ACL_POLICER_SET, dess_rate_acl_policer_set), \
+    SW_API_DEF(SW_API_RATE_ACL_POLICER_GET, dess_rate_acl_policer_get), \
+    SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, dess_rate_port_add_rate_byte_set), \
+    SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, dess_rate_port_add_rate_byte_get), \
+    SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, dess_rate_port_gol_flow_en_set), \
+    SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, dess_rate_port_gol_flow_en_get),
+
+#define RATE_API_PARAM \
+    SW_API_DESC(SW_API_RATE_PORT_POLICER_SET) \
+    SW_API_DESC(SW_API_RATE_PORT_POLICER_GET) \
+    SW_API_DESC(SW_API_RATE_PORT_SHAPER_SET) \
+    SW_API_DESC(SW_API_RATE_PORT_SHAPER_GET) \
+    SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_SET) \
+    SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_GET) \
+    SW_API_DESC(SW_API_RATE_ACL_POLICER_SET) \
+    SW_API_DESC(SW_API_RATE_ACL_POLICER_GET) \
+    SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_SET) \
+    SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_GET) \
+    SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_SET) \
+    SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_GET)
+#else
+#define RATE_API
+#define RATE_API_PARAM
+#endif
+
+
+#ifdef IN_STP
+#define STP_API \
+    SW_API_DEF(SW_API_STP_PT_STATE_SET, dess_stp_port_state_set), \
+    SW_API_DEF(SW_API_STP_PT_STATE_GET, dess_stp_port_state_get),
+
+#define STP_API_PARAM \
+    SW_API_DESC(SW_API_STP_PT_STATE_SET) \
+    SW_API_DESC(SW_API_STP_PT_STATE_GET)
+#else
+#define STP_API
+#define STP_API_PARAM
+#endif
+
+
+#ifdef IN_MIB
+#define MIB_API \
+    SW_API_DEF(SW_API_PT_MIB_GET, dess_get_mib_info), \
+    SW_API_DEF(SW_API_MIB_STATUS_SET, dess_mib_status_set), \
+    SW_API_DEF(SW_API_MIB_STATUS_GET, dess_mib_status_get), \
+    SW_API_DEF(SW_API_PT_MIB_FLUSH_COUNTERS, dess_mib_port_flush_counters), \
+    SW_API_DEF(SW_API_MIB_CPU_KEEP_SET, dess_mib_cpukeep_set), \
+    SW_API_DEF(SW_API_MIB_CPU_KEEP_GET, dess_mib_cpukeep_get),
+
+
+#define MIB_API_PARAM \
+    SW_API_DESC(SW_API_PT_MIB_GET)  \
+    SW_API_DESC(SW_API_MIB_STATUS_SET) \
+    SW_API_DESC(SW_API_MIB_STATUS_GET)\
+    SW_API_DESC(SW_API_PT_MIB_FLUSH_COUNTERS) \
+    SW_API_DESC(SW_API_MIB_CPU_KEEP_SET) \
+    SW_API_DESC(SW_API_MIB_CPU_KEEP_GET)
+#else
+#define MIB_API
+#define MIB_API_PARAM
+#endif
+
+
+#ifdef IN_MISC
+#define MISC_API \
+    SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, dess_frame_max_size_set), \
+    SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, dess_frame_max_size_get), \
+    SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, dess_port_unk_uc_filter_set), \
+    SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, dess_port_unk_uc_filter_get), \
+    SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, dess_port_unk_mc_filter_set), \
+    SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, dess_port_unk_mc_filter_get), \
+    SW_API_DEF(SW_API_PT_BC_FILTER_SET, dess_port_bc_filter_set), \
+    SW_API_DEF(SW_API_PT_BC_FILTER_GET, dess_port_bc_filter_get), \
+    SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, dess_cpu_port_status_set), \
+    SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, dess_cpu_port_status_get), \
+    SW_API_DEF(SW_API_PPPOE_CMD_SET, dess_pppoe_cmd_set), \
+    SW_API_DEF(SW_API_PPPOE_CMD_GET, dess_pppoe_cmd_get), \
+    SW_API_DEF(SW_API_PPPOE_STATUS_SET, dess_pppoe_status_set), \
+    SW_API_DEF(SW_API_PPPOE_STATUS_GET, dess_pppoe_status_get), \
+    SW_API_DEF(SW_API_PT_DHCP_SET, dess_port_dhcp_set), \
+    SW_API_DEF(SW_API_PT_DHCP_GET, dess_port_dhcp_get), \
+    SW_API_DEF(SW_API_ARP_CMD_SET, dess_arp_cmd_set), \
+    SW_API_DEF(SW_API_ARP_CMD_GET, dess_arp_cmd_get), \
+    SW_API_DEF(SW_API_EAPOL_CMD_SET, dess_eapol_cmd_set), \
+    SW_API_DEF(SW_API_EAPOL_CMD_GET, dess_eapol_cmd_get), \
+    SW_API_DEF(SW_API_EAPOL_STATUS_SET, dess_eapol_status_set), \
+    SW_API_DEF(SW_API_EAPOL_STATUS_GET, dess_eapol_status_get), \
+    SW_API_DEF(SW_API_RIPV1_STATUS_SET, dess_ripv1_status_set), \
+    SW_API_DEF(SW_API_RIPV1_STATUS_GET, dess_ripv1_status_get), \
+    SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_SET, dess_port_arp_req_status_set), \
+    SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_GET, dess_port_arp_req_status_get), \
+    SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_SET, dess_port_arp_ack_status_set), \
+    SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_GET, dess_port_arp_ack_status_get), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, dess_pppoe_session_table_add), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, dess_pppoe_session_table_del), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_GET, dess_pppoe_session_table_get), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_ID_SET, dess_pppoe_session_id_set), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_ID_GET, dess_pppoe_session_id_get), \
+    SW_API_DEF(SW_API_INTR_MASK_SET, dess_intr_mask_set), \
+    SW_API_DEF(SW_API_INTR_MASK_GET, dess_intr_mask_get), \
+    SW_API_DEF(SW_API_INTR_STATUS_GET, dess_intr_status_get),   \
+    SW_API_DEF(SW_API_INTR_STATUS_CLEAR, dess_intr_status_clear), \
+    SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_SET, dess_intr_port_link_mask_set), \
+    SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_GET, dess_intr_port_link_mask_get), \
+    SW_API_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, dess_intr_port_link_status_get),\
+    SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, dess_intr_mask_mac_linkchg_set), \
+    SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, dess_intr_mask_mac_linkchg_get), \
+    SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_GET, dess_intr_status_mac_linkchg_get), \
+        SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, dess_intr_status_mac_linkchg_clear), \
+    SW_API_DEF(SW_API_CPU_VID_EN_SET, dess_cpu_vid_en_set), \
+    SW_API_DEF(SW_API_CPU_VID_EN_GET, dess_cpu_vid_en_get), \
+    SW_API_DEF(SW_API_RTD_PPPOE_EN_SET, dess_rtd_pppoe_en_set), \
+    SW_API_DEF(SW_API_RTD_PPPOE_EN_GET, dess_rtd_pppoe_en_get), \
+	SW_API_DEF(SW_API_GLOBAL_MACADDR_SET, dess_global_macaddr_set), \
+    SW_API_DEF(SW_API_GLOBAL_MACADDR_GET, dess_global_macaddr_get), \
+    SW_API_DEF(SW_API_LLDP_STATUS_SET, dess_lldp_status_set), \
+    SW_API_DEF(SW_API_LLDP_STATUS_GET, dess_lldp_status_get), \
+    SW_API_DEF(SW_API_FRAME_CRC_RESERVE_SET, dess_frame_crc_reserve_set), \
+    SW_API_DEF(SW_API_FRAME_CRC_RESERVE_GET, dess_frame_crc_reserve_get),
+
+#define MISC_API_PARAM \
+    SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET)  \
+    SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET)  \
+    SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET)  \
+    SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET)  \
+    SW_API_DESC(SW_API_PT_BC_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_BC_FILTER_GET)  \
+    SW_API_DESC(SW_API_CPU_PORT_STATUS_SET)  \
+    SW_API_DESC(SW_API_CPU_PORT_STATUS_GET)  \
+    SW_API_DESC(SW_API_PPPOE_CMD_SET)  \
+    SW_API_DESC(SW_API_PPPOE_CMD_GET)  \
+    SW_API_DESC(SW_API_PPPOE_STATUS_SET)  \
+    SW_API_DESC(SW_API_PPPOE_STATUS_GET)  \
+    SW_API_DESC(SW_API_PT_DHCP_SET)  \
+    SW_API_DESC(SW_API_PT_DHCP_GET)  \
+    SW_API_DESC(SW_API_ARP_CMD_SET)  \
+    SW_API_DESC(SW_API_ARP_CMD_GET)  \
+    SW_API_DESC(SW_API_EAPOL_CMD_SET) \
+    SW_API_DESC(SW_API_EAPOL_CMD_GET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_ADD)  \
+    SW_API_DESC(SW_API_PPPOE_SESSION_DEL)  \
+    SW_API_DESC(SW_API_PPPOE_SESSION_GET)  \
+    SW_API_DESC(SW_API_EAPOL_STATUS_SET)  \
+    SW_API_DESC(SW_API_EAPOL_STATUS_GET)  \
+    SW_API_DESC(SW_API_RIPV1_STATUS_SET)  \
+    SW_API_DESC(SW_API_RIPV1_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_SET) \
+    SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_SET) \
+    SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_GET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_ADD) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_DEL) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_GET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_ID_SET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_ID_GET) \
+    SW_API_DESC(SW_API_INTR_MASK_SET) \
+    SW_API_DESC(SW_API_INTR_MASK_GET) \
+    SW_API_DESC(SW_API_INTR_STATUS_GET)   \
+    SW_API_DESC(SW_API_INTR_STATUS_CLEAR) \
+    SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_SET) \
+    SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_GET) \
+    SW_API_DESC(SW_API_INTR_PORT_LINK_STATUS_GET) \
+     SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_SET) \
+    SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_GET) \
+    SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_GET) \
+    SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR) \
+    SW_API_DESC(SW_API_CPU_VID_EN_SET)  \
+    SW_API_DESC(SW_API_CPU_VID_EN_GET)  \
+    SW_API_DESC(SW_API_RTD_PPPOE_EN_SET)  \
+    SW_API_DESC(SW_API_RTD_PPPOE_EN_GET) \
+    SW_API_DESC(SW_API_GLOBAL_MACADDR_SET)  \
+    SW_API_DESC(SW_API_GLOBAL_MACADDR_GET) \
+    SW_API_DESC(SW_API_LLDP_STATUS_SET)  \
+    SW_API_DESC(SW_API_LLDP_STATUS_GET)  \
+    SW_API_DESC(SW_API_FRAME_CRC_RESERVE_SET)  \
+    SW_API_DESC(SW_API_FRAME_CRC_RESERVE_GET)
+
+#else
+#define MISC_API
+#define MISC_API_PARAM
+#endif
+
+
+#ifdef IN_LED
+#define LED_API \
+    SW_API_DEF(SW_API_LED_PATTERN_SET, dess_led_ctrl_pattern_set), \
+    SW_API_DEF(SW_API_LED_PATTERN_GET, dess_led_ctrl_pattern_get),
+
+#define LED_API_PARAM \
+    SW_API_DESC(SW_API_LED_PATTERN_SET) \
+    SW_API_DESC(SW_API_LED_PATTERN_GET)
+#else
+#define LED_API
+#define LED_API_PARAM
+#endif
+
+#ifdef IN_COSMAP
+#define COSMAP_API \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, dess_cosmap_dscp_to_pri_set), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, dess_cosmap_dscp_to_pri_get), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, dess_cosmap_dscp_to_dp_set), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, dess_cosmap_dscp_to_dp_get), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_SET, dess_cosmap_up_to_pri_set), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_GET, dess_cosmap_up_to_pri_get), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_DP_SET, dess_cosmap_up_to_dp_set), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_DP_GET, dess_cosmap_up_to_dp_get), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_SET, dess_cosmap_pri_to_queue_set), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_GET, dess_cosmap_pri_to_queue_get), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, dess_cosmap_pri_to_ehqueue_set), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, dess_cosmap_pri_to_ehqueue_get), \
+    SW_API_DEF(SW_API_COSMAP_EG_REMARK_SET, dess_cosmap_egress_remark_set), \
+    SW_API_DEF(SW_API_COSMAP_EG_REMARK_GET, dess_cosmap_egress_remark_get),
+
+#define COSMAP_API_PARAM \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_SET)  \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_GET)  \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_SET)  \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_GET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_SET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_GET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_DP_SET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_DP_GET)  \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_SET)  \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_GET)  \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_SET) \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_GET) \
+    SW_API_DESC(SW_API_COSMAP_EG_REMARK_SET) \
+    SW_API_DESC(SW_API_COSMAP_EG_REMARK_GET)
+#else
+#define COSMAP_API
+#define COSMAP_API_PARAM
+#endif
+
+#ifdef IN_SEC
+#define SEC_API \
+    SW_API_DEF(SW_API_SEC_NORM_SET, dess_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_NORM_GET, dess_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_MAC_SET, dess_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_MAC_GET, dess_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_IP_SET, dess_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_IP_GET, dess_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_IP4_SET, dess_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_IP4_GET, dess_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_IP6_SET, dess_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_IP6_GET, dess_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_TCP_SET, dess_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_TCP_GET, dess_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_UDP_SET, dess_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_UDP_GET, dess_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_ICMP4_SET, dess_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_ICMP4_GET, dess_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_ICMP6_SET, dess_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_ICMP6_GET, dess_sec_norm_item_get),
+
+#define SEC_API_PARAM \
+    SW_API_DESC(SW_API_SEC_NORM_SET) \
+    SW_API_DESC(SW_API_SEC_NORM_GET) \
+    SW_API_DESC(SW_API_SEC_MAC_SET) \
+    SW_API_DESC(SW_API_SEC_MAC_GET) \
+    SW_API_DESC(SW_API_SEC_IP_SET) \
+    SW_API_DESC(SW_API_SEC_IP_GET) \
+    SW_API_DESC(SW_API_SEC_IP4_SET) \
+    SW_API_DESC(SW_API_SEC_IP4_GET) \
+    SW_API_DESC(SW_API_SEC_IP6_SET) \
+    SW_API_DESC(SW_API_SEC_IP6_GET) \
+    SW_API_DESC(SW_API_SEC_TCP_SET) \
+    SW_API_DESC(SW_API_SEC_TCP_GET) \
+    SW_API_DESC(SW_API_SEC_UDP_SET) \
+    SW_API_DESC(SW_API_SEC_UDP_GET) \
+    SW_API_DESC(SW_API_SEC_ICMP4_SET) \
+    SW_API_DESC(SW_API_SEC_ICMP4_GET) \
+    SW_API_DESC(SW_API_SEC_ICMP6_SET) \
+    SW_API_DESC(SW_API_SEC_ICMP6_GET)
+#else
+#define SEC_API
+#define SEC_API_PARAM
+#endif
+
+#ifdef IN_IP
+#define IP_API \
+    SW_API_DEF(SW_API_IP_HOST_ADD, dess_ip_host_add), \
+    SW_API_DEF(SW_API_IP_HOST_DEL, dess_ip_host_del), \
+    SW_API_DEF(SW_API_IP_HOST_GET, dess_ip_host_get), \
+    SW_API_DEF(SW_API_IP_HOST_NEXT, dess_ip_host_next), \
+    SW_API_DEF(SW_API_IP_HOST_COUNTER_BIND, dess_ip_host_counter_bind), \
+    SW_API_DEF(SW_API_IP_HOST_PPPOE_BIND, dess_ip_host_pppoe_bind), \
+    SW_API_DEF(SW_API_IP_PT_ARP_LEARN_SET, dess_ip_pt_arp_learn_set), \
+    SW_API_DEF(SW_API_IP_PT_ARP_LEARN_GET, dess_ip_pt_arp_learn_get), \
+    SW_API_DEF(SW_API_IP_ARP_LEARN_SET, dess_ip_arp_learn_set), \
+    SW_API_DEF(SW_API_IP_ARP_LEARN_GET, dess_ip_arp_learn_get), \
+    SW_API_DEF(SW_API_IP_SOURCE_GUARD_SET, dess_ip_source_guard_set), \
+    SW_API_DEF(SW_API_IP_SOURCE_GUARD_GET, dess_ip_source_guard_get), \
+    SW_API_DEF(SW_API_IP_ARP_GUARD_SET, dess_ip_arp_guard_set), \
+    SW_API_DEF(SW_API_IP_ARP_GUARD_GET, dess_ip_arp_guard_get), \
+    SW_API_DEF(SW_API_IP_ROUTE_STATUS_SET, dess_ip_route_status_set), \
+    SW_API_DEF(SW_API_IP_ROUTE_STATUS_GET, dess_ip_route_status_get), \
+    SW_API_DEF(SW_API_IP_INTF_ENTRY_ADD, dess_ip_intf_entry_add), \
+    SW_API_DEF(SW_API_IP_INTF_ENTRY_DEL, dess_ip_intf_entry_del), \
+    SW_API_DEF(SW_API_IP_INTF_ENTRY_NEXT, dess_ip_intf_entry_next), \
+    SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, dess_ip_unk_source_cmd_set),  \
+    SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, dess_ip_unk_source_cmd_get), \
+    SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, dess_arp_unk_source_cmd_set), \
+    SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, dess_arp_unk_source_cmd_get), \
+    SW_API_DEF(SW_API_IP_AGE_TIME_SET, dess_ip_age_time_set), \
+    SW_API_DEF(SW_API_IP_AGE_TIME_GET, dess_ip_age_time_get), \
+    SW_API_DEF(SW_API_WCMP_HASH_MODE_SET, dess_ip_wcmp_hash_mode_set), \
+    SW_API_DEF(SW_API_WCMP_HASH_MODE_GET, dess_ip_wcmp_hash_mode_get), \
+    SW_API_DEF(SW_API_IP_DEFAULT_FLOW_CMD_SET, dess_default_flow_cmd_set), \
+    SW_API_DEF(SW_API_IP_DEFAULT_FLOW_CMD_GET, dess_default_flow_cmd_get), \
+    SW_API_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET, dess_default_rt_flow_cmd_set), \
+    SW_API_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET, dess_default_rt_flow_cmd_get),
+
+#define IP_API_PARAM \
+    SW_API_DESC(SW_API_IP_HOST_ADD) \
+    SW_API_DESC(SW_API_IP_HOST_DEL) \
+    SW_API_DESC(SW_API_IP_HOST_GET) \
+    SW_API_DESC(SW_API_IP_HOST_NEXT) \
+    SW_API_DESC(SW_API_IP_HOST_COUNTER_BIND) \
+    SW_API_DESC(SW_API_IP_HOST_PPPOE_BIND) \
+    SW_API_DESC(SW_API_IP_PT_ARP_LEARN_SET) \
+    SW_API_DESC(SW_API_IP_PT_ARP_LEARN_GET) \
+    SW_API_DESC(SW_API_IP_ARP_LEARN_SET) \
+    SW_API_DESC(SW_API_IP_ARP_LEARN_GET) \
+    SW_API_DESC(SW_API_IP_SOURCE_GUARD_SET) \
+    SW_API_DESC(SW_API_IP_SOURCE_GUARD_GET) \
+    SW_API_DESC(SW_API_IP_ARP_GUARD_SET) \
+    SW_API_DESC(SW_API_IP_ARP_GUARD_GET) \
+    SW_API_DESC(SW_API_IP_ROUTE_STATUS_SET) \
+    SW_API_DESC(SW_API_IP_ROUTE_STATUS_GET) \
+    SW_API_DESC(SW_API_IP_INTF_ENTRY_ADD)  \
+    SW_API_DESC(SW_API_IP_INTF_ENTRY_DEL)  \
+    SW_API_DESC(SW_API_IP_INTF_ENTRY_NEXT) \
+    SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_SET)  \
+    SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_GET)  \
+    SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_SET) \
+    SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_GET) \
+    SW_API_DESC(SW_API_IP_AGE_TIME_SET) \
+    SW_API_DESC(SW_API_IP_AGE_TIME_GET) \
+    SW_API_DESC(SW_API_WCMP_HASH_MODE_SET) \
+    SW_API_DESC(SW_API_WCMP_HASH_MODE_GET) \
+    SW_API_DESC(SW_API_IP_DEFAULT_FLOW_CMD_SET) \
+    SW_API_DESC(SW_API_IP_DEFAULT_FLOW_CMD_GET) \
+    SW_API_DESC(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET) \
+    SW_API_DESC(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET)
+
+#else
+#define IP_API
+#define IP_API_PARAM
+#endif
+
+#ifdef IN_NAT
+#define NAT_API \
+    SW_API_DEF(SW_API_NAT_ADD, dess_nat_add), \
+    SW_API_DEF(SW_API_NAT_DEL, dess_nat_del), \
+    SW_API_DEF(SW_API_NAT_GET, dess_nat_get), \
+    SW_API_DEF(SW_API_NAT_NEXT, dess_nat_next), \
+    SW_API_DEF(SW_API_NAT_COUNTER_BIND, dess_nat_counter_bind), \
+    SW_API_DEF(SW_API_NAPT_ADD, dess_napt_add), \
+    SW_API_DEF(SW_API_NAPT_DEL, dess_napt_del), \
+    SW_API_DEF(SW_API_NAPT_GET, dess_napt_get), \
+    SW_API_DEF(SW_API_NAPT_NEXT, dess_napt_next), \
+    SW_API_DEF(SW_API_NAPT_COUNTER_BIND, dess_napt_counter_bind), \
+    SW_API_DEF(SW_API_FLOW_ADD, dess_flow_add), \
+    SW_API_DEF(SW_API_FLOW_DEL, dess_flow_del), \
+    SW_API_DEF(SW_API_FLOW_GET, dess_flow_get), \
+    SW_API_DEF(SW_API_FLOW_NEXT, dess_flow_next), \
+    SW_API_DEF(SW_API_FLOW_COUNTER_BIND, dess_flow_counter_bind), \
+    SW_API_DEF(SW_API_NAT_STATUS_SET, dess_nat_status_set), \
+    SW_API_DEF(SW_API_NAT_STATUS_GET, dess_nat_status_get), \
+    SW_API_DEF(SW_API_NAT_HASH_MODE_SET, dess_nat_hash_mode_set), \
+    SW_API_DEF(SW_API_NAT_HASH_MODE_GET, dess_nat_hash_mode_get), \
+    SW_API_DEF(SW_API_NAPT_STATUS_SET, dess_napt_status_set), \
+    SW_API_DEF(SW_API_NAPT_STATUS_GET, dess_napt_status_get), \
+    SW_API_DEF(SW_API_NAPT_MODE_SET, dess_napt_mode_set), \
+    SW_API_DEF(SW_API_NAPT_MODE_GET, dess_napt_mode_get), \
+    SW_API_DEF(SW_API_PRV_BASE_ADDR_SET, dess_nat_prv_base_addr_set), \
+    SW_API_DEF(SW_API_PRV_BASE_ADDR_GET, dess_nat_prv_base_addr_get), \
+    SW_API_DEF(SW_API_PUB_ADDR_ENTRY_ADD, dess_nat_pub_addr_add), \
+    SW_API_DEF(SW_API_PUB_ADDR_ENTRY_DEL, dess_nat_pub_addr_del), \
+    SW_API_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, dess_nat_pub_addr_next), \
+    SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, dess_nat_unk_session_cmd_set), \
+    SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, dess_nat_unk_session_cmd_get), \
+    SW_API_DEF(SW_API_PRV_BASE_MASK_SET, dess_nat_prv_base_mask_set), \
+    SW_API_DEF(SW_API_PRV_BASE_MASK_GET, dess_nat_prv_base_mask_get), \
+    SW_API_DEF(SW_API_NAT_GLOBAL_SET, dess_nat_global_set),
+
+#define NAT_API_PARAM \
+    SW_API_DESC(SW_API_NAT_ADD) \
+    SW_API_DESC(SW_API_NAT_DEL) \
+    SW_API_DESC(SW_API_NAT_GET) \
+    SW_API_DESC(SW_API_NAT_NEXT) \
+    SW_API_DESC(SW_API_NAT_COUNTER_BIND) \
+    SW_API_DESC(SW_API_NAPT_ADD) \
+    SW_API_DESC(SW_API_NAPT_DEL) \
+    SW_API_DESC(SW_API_NAPT_GET) \
+    SW_API_DESC(SW_API_NAPT_NEXT) \
+    SW_API_DESC(SW_API_NAPT_COUNTER_BIND) \
+    SW_API_DESC(SW_API_FLOW_ADD) \
+    SW_API_DESC(SW_API_FLOW_DEL) \
+    SW_API_DESC(SW_API_FLOW_GET) \
+    SW_API_DESC(SW_API_FLOW_NEXT) \
+    SW_API_DESC(SW_API_FLOW_COUNTER_BIND) \
+    SW_API_DESC(SW_API_NAT_STATUS_SET) \
+    SW_API_DESC(SW_API_NAT_STATUS_GET) \
+    SW_API_DESC(SW_API_NAT_HASH_MODE_SET) \
+    SW_API_DESC(SW_API_NAT_HASH_MODE_GET) \
+    SW_API_DESC(SW_API_NAPT_STATUS_SET) \
+    SW_API_DESC(SW_API_NAPT_STATUS_GET) \
+    SW_API_DESC(SW_API_NAPT_MODE_SET) \
+    SW_API_DESC(SW_API_NAPT_MODE_GET) \
+    SW_API_DESC(SW_API_PRV_BASE_ADDR_SET) \
+    SW_API_DESC(SW_API_PRV_BASE_ADDR_GET) \
+    SW_API_DESC(SW_API_PUB_ADDR_ENTRY_ADD) \
+    SW_API_DESC(SW_API_PUB_ADDR_ENTRY_DEL) \
+    SW_API_DESC(SW_API_PUB_ADDR_ENTRY_NEXT) \
+    SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_SET) \
+    SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_GET) \
+    SW_API_DESC(SW_API_PRV_BASE_MASK_SET) \
+    SW_API_DESC(SW_API_PRV_BASE_MASK_GET) \
+    SW_API_DESC(SW_API_NAT_GLOBAL_SET)
+#else
+#define NAT_API
+#define NAT_API_PARAM
+#endif
+
+#ifdef IN_TRUNK
+#define TRUNK_API \
+    SW_API_DEF(SW_API_TRUNK_GROUP_SET, dess_trunk_group_set), \
+    SW_API_DEF(SW_API_TRUNK_GROUP_GET, dess_trunk_group_get), \
+    SW_API_DEF(SW_API_TRUNK_HASH_SET, dess_trunk_hash_mode_set), \
+    SW_API_DEF(SW_API_TRUNK_HASH_GET, dess_trunk_hash_mode_get), \
+    SW_API_DEF(SW_API_TRUNK_MAN_SA_SET, dess_trunk_manipulate_sa_set), \
+    SW_API_DEF(SW_API_TRUNK_MAN_SA_GET, dess_trunk_manipulate_sa_get),
+
+#define TRUNK_API_PARAM \
+    SW_API_DESC(SW_API_TRUNK_GROUP_SET) \
+    SW_API_DESC(SW_API_TRUNK_GROUP_GET) \
+    SW_API_DESC(SW_API_TRUNK_HASH_SET)  \
+    SW_API_DESC(SW_API_TRUNK_HASH_GET)  \
+    SW_API_DESC(SW_API_TRUNK_MAN_SA_SET)\
+    SW_API_DESC(SW_API_TRUNK_MAN_SA_GET)
+#else
+#define TRUNK_API
+#define TRUNK_API_PARAM
+#endif
+
+#ifdef IN_INTERFACECONTROL
+#define INTERFACECTRL_API \
+    SW_API_DEF(SW_API_MAC_MODE_SET, dess_interface_mac_mode_set), \
+    SW_API_DEF(SW_API_MAC_MODE_GET, dess_interface_mac_mode_get), \
+    SW_API_DEF(SW_API_PORT_3AZ_STATUS_SET, dess_port_3az_status_set), \
+    SW_API_DEF(SW_API_PORT_3AZ_STATUS_GET, dess_port_3az_status_get), \
+    SW_API_DEF(SW_API_PHY_MODE_SET, dess_interface_phy_mode_set), \
+    SW_API_DEF(SW_API_PHY_MODE_GET, dess_interface_phy_mode_get), \
+    SW_API_DEF(SW_API_FX100_CTRL_SET, dess_interface_fx100_ctrl_set), \
+    SW_API_DEF(SW_API_FX100_CTRL_GET, dess_interface_fx100_ctrl_get), \
+    SW_API_DEF(SW_API_FX100_STATUS_GET, dess_interface_fx100_status_get), \
+    SW_API_DEF(SW_API_MAC06_EXCH_SET, dess_interface_mac06_exch_set), \
+    SW_API_DEF(SW_API_MAC06_EXCH_GET, dess_interface_mac06_exch_get),
+
+#define INTERFACECTRL_API_PARAM \
+    SW_API_DESC(SW_API_MAC_MODE_SET)  \
+    SW_API_DESC(SW_API_MAC_MODE_GET)  \
+    SW_API_DESC(SW_API_PORT_3AZ_STATUS_SET)  \
+    SW_API_DESC(SW_API_PORT_3AZ_STATUS_GET)  \
+    SW_API_DESC(SW_API_PHY_MODE_SET)  \
+    SW_API_DESC(SW_API_PHY_MODE_GET)  \
+    SW_API_DESC(SW_API_FX100_CTRL_SET)  \
+    SW_API_DESC(SW_API_FX100_CTRL_GET)  \
+    SW_API_DESC(SW_API_FX100_STATUS_GET) \
+    SW_API_DESC(SW_API_MAC06_EXCH_SET) \
+    SW_API_DESC(SW_API_MAC06_EXCH_GET)
+
+#else
+#define INTERFACECTRL_API
+#define INTERFACECTRL_API_PARAM
+#endif
+
+#define REG_API \
+    SW_API_DEF(SW_API_PHY_GET, dess_phy_get), \
+    SW_API_DEF(SW_API_PHY_SET, dess_phy_set), \
+    SW_API_DEF(SW_API_REG_GET, dess_reg_get), \
+    SW_API_DEF(SW_API_PSGMII_REG_SET, dess_psgmii_reg_set), \
+    SW_API_DEF(SW_API_PSGMII_REG_GET, dess_psgmii_reg_get), \
+    SW_API_DEF(SW_API_REG_SET, dess_reg_set), \
+    SW_API_DEF(SW_API_REG_FIELD_GET, dess_reg_field_get), \
+    SW_API_DEF(SW_API_REG_FIELD_SET, dess_reg_field_set), \
+    SW_API_DEF(SW_API_REG_DUMP, dess_regsiter_dump), \
+    SW_API_DEF(SW_API_DBG_REG_DUMP, dess_debug_regsiter_dump), \
+    SW_API_DEF(SW_API_DBG_PSGMII_SELF_TEST, fal_debug_psgmii_self_test), \
+    SW_API_DEF(SW_API_PHY_DUMP, fal_phy_dump),
+
+
+#define REG_API_PARAM \
+    SW_API_DESC(SW_API_PHY_GET) \
+    SW_API_DESC(SW_API_PHY_SET) \
+    SW_API_DESC(SW_API_REG_GET) \
+    SW_API_DESC(SW_API_REG_SET) \
+    SW_API_DESC(SW_API_PSGMII_REG_GET) \
+    SW_API_DESC(SW_API_PSGMII_REG_SET) \
+    SW_API_DESC(SW_API_REG_FIELD_GET) \
+    SW_API_DESC(SW_API_REG_FIELD_SET) \
+    SW_API_DESC(SW_API_REG_DUMP)  \
+    SW_API_DESC(SW_API_DBG_REG_DUMP) \
+    SW_API_DESC(SW_API_DBG_PSGMII_SELF_TEST) \
+    SW_API_DESC(SW_API_PHY_DUMP)
+
+
+
+#define SSDK_API \
+    SW_API_DEF(SW_API_SWITCH_RESET, dess_reset), \
+    SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \
+    PORTCONTROL_API \
+    VLAN_API \
+    PORTVLAN_API \
+    FDB_API    \
+    ACL_API    \
+    QOS_API    \
+    IGMP_API   \
+    LEAKY_API  \
+    MIRROR_API \
+    RATE_API \
+    STP_API  \
+    MIB_API  \
+    MISC_API \
+    LED_API  \
+    COSMAP_API \
+    SEC_API  \
+    IP_API \
+    NAT_API \
+    TRUNK_API \
+    INTERFACECTRL_API \
+    REG_API  \
+    SW_API_DEF(SW_API_MAX, NULL),
+
+
+#define SSDK_PARAM  \
+    SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
+    MIB_API_PARAM    \
+    LEAKY_API_PARAM  \
+    MISC_API_PARAM   \
+    IGMP_API_PARAM   \
+    MIRROR_API_PARAM \
+    PORTCONTROL_API_PARAM \
+    PORTVLAN_API_PARAM    \
+    VLAN_API_PARAM \
+    FDB_API_PARAM  \
+    QOS_API_PARAM  \
+    RATE_API_PARAM \
+    STP_API_PARAM  \
+    ACL_API_PARAM  \
+    LED_API_PARAM  \
+    COSMAP_API_PARAM \
+    SEC_API_PARAM  \
+    IP_API_PARAM \
+    NAT_API_PARAM \
+    TRUNK_API_PARAM \
+    INTERFACECTRL_API_PARAM \
+    REG_API_PARAM  \
+    SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#if (defined(USER_MODE) && defined(KERNEL_MODULE))
+#undef SSDK_API
+#undef SSDK_PARAM
+
+#define SSDK_API \
+    REG_API \
+    SW_API_DEF(SW_API_MAX, NULL),
+
+#define SSDK_PARAM  \
+    REG_API_PARAM \
+    SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _DESS_API_H_ */
+_ */
diff --git a/qca-ssdk/include/hsl/dess/dess_cosmap.h b/qca-ssdk/include/hsl/dess/dess_cosmap.h
new file mode 100755
index 0000000..5ab1141
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_cosmap.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_cosmap DESS_COSMAP
+ * @{
+ */
+#ifndef _DESS_COSMAP_H_
+#define _DESS_COSMAP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_cosmap.h"
+
+    sw_error_t dess_cosmap_init(a_uint32_t dev_id);
+
+#ifdef IN_COSMAP
+#define DESS_COSMAP_INIT(rv, dev_id) \
+    { \
+        rv = dess_cosmap_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_COSMAP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp,
+                                a_uint32_t pri);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+                                a_uint32_t * pri);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp,
+                               a_uint32_t dp);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp,
+                               a_uint32_t * dp);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up,
+                              a_uint32_t pri);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up,
+                              a_uint32_t * pri);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up,
+                             a_uint32_t dp);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up,
+                             a_uint32_t * dp);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_dscp_to_ehpri_set(a_uint32_t dev_id, a_uint32_t dscp,
+                                a_uint32_t pri);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_dscp_to_ehpri_get(a_uint32_t dev_id, a_uint32_t dscp,
+                                a_uint32_t * pri);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_dscp_to_ehdp_set(a_uint32_t dev_id, a_uint32_t dscp,
+                               a_uint32_t dp);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_dscp_to_ehdp_get(a_uint32_t dev_id, a_uint32_t dscp,
+                               a_uint32_t * dp);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_up_to_ehpri_set(a_uint32_t dev_id, a_uint32_t up,
+                              a_uint32_t pri);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_up_to_ehpri_get(a_uint32_t dev_id, a_uint32_t up,
+                              a_uint32_t * pri);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_up_to_ehdp_set(a_uint32_t dev_id, a_uint32_t up,
+                             a_uint32_t dp);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_up_to_ehdp_get(a_uint32_t dev_id, a_uint32_t up,
+                             a_uint32_t * dp);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+                                 a_uint32_t queue);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+                                 a_uint32_t * queue);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+                                   a_uint32_t queue);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+                                   a_uint32_t * queue);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+                                  fal_egress_remark_table_t * tbl);
+
+    HSL_LOCAL sw_error_t
+    dess_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+                                  fal_egress_remark_table_t * tbl);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_COSMAP_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_fdb.h b/qca-ssdk/include/hsl/dess/dess_fdb.h
new file mode 100755
index 0000000..801c9c3
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_fdb.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_fdb DESS_FDB
+ * @{
+ */
+#ifndef _DESS_FDB_H_
+#define _DESS_FDB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_fdb.h"
+
+    sw_error_t dess_fdb_init(a_uint32_t dev_id);
+
+#ifdef IN_FDB
+#define DESS_FDB_INIT(rv, dev_id) \
+    { \
+        rv = dess_fdb_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_FDB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t flag);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * op,
+                         fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+                          fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port,
+                      fal_port_t new_port, a_uint32_t fid,
+                      fal_fdb_op_t * option);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode * smode);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+    HSL_LOCAL sw_error_t
+    dess_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable, a_uint32_t cnt);
+
+    HSL_LOCAL sw_error_t
+    dess_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable, a_uint32_t * cnt);
+
+    HSL_LOCAL sw_error_t
+    dess_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id,
+                                       fal_port_t port_id,
+                                       fal_fwd_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    dess_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id,
+                                       fal_port_t port_id,
+                                       fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable,
+                             a_uint32_t cnt);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable,
+                             a_uint32_t * cnt);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+                          fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+    HSL_LOCAL sw_error_t
+    dess_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_FDB_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_fdb_prv.h b/qca-ssdk/include/hsl/dess/dess_fdb_prv.h
new file mode 100755
index 0000000..e0f4f0a
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_fdb_prv.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_FDB_PRV_H_
+#define _DESS_FDB_PRV_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+
+#define ARL_FLUSH_ALL             1
+#define ARL_LOAD_ENTRY            2
+#define ARL_PURGE_ENTRY           3
+#define ARL_FLUSH_ALL_UNLOCK      4
+#define ARL_FLUSH_PORT_UNICAST    5
+#define ARL_NEXT_ENTRY            6
+#define ARL_FIND_ENTRY            7
+#define ARL_TRANSFER_ENTRY        8
+
+#define ARL_FIRST_ENTRY           1001
+#define ARL_FLUSH_PORT_NO_STATIC  1002
+#define ARL_FLUSH_PORT_AND_STATIC 1003
+
+#define DESS_MAX_FID                   4095
+#define DESS_MAX_LEARN_LIMIT_CNT       2048
+#define DESS_MAX_PORT_LEARN_LIMIT_CNT  1024
+
+    sw_error_t
+    inter_dess_fdb_flush(a_uint32_t dev_id, a_uint32_t flag);
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_FDB_PRV_H_ */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_igmp.h b/qca-ssdk/include/hsl/dess/dess_igmp.h
new file mode 100755
index 0000000..bc80881
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_igmp.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_igmp DESS_IGMP
+ * @{
+ */
+#ifndef _DESS_IGMP_H_
+#define _DESS_IGMP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_igmp.h"
+#include "fal/fal_multi.h"
+
+    sw_error_t
+    dess_igmp_init(a_uint32_t dev_id);
+
+#ifdef IN_IGMP
+#define DESS_IGMP_INIT(rv, dev_id) \
+    { \
+        rv = dess_igmp_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_IGMP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    dess_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts);
+
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts);
+
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue);
+
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                       a_bool_t enable, a_uint32_t cnt);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                       a_bool_t * enable, a_uint32_t * cnt);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                            fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                            fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_sg_entry_show(a_uint32_t dev_id);
+
+    HSL_LOCAL sw_error_t
+    dess_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t * info);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _DESS_IGMP_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/dess/dess_init.h b/qca-ssdk/include/hsl/dess/dess_init.h
new file mode 100755
index 0000000..7767151
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_init.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_init DESS_INIT
+ * @{
+ */
+#ifndef _DESS_INIT_H_
+#define _DESS_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+
+    sw_error_t
+    dess_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+
+    sw_error_t
+    dess_cleanup(a_uint32_t dev_id);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _DESS_INIT_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/dess/dess_interface_ctrl.h b/qca-ssdk/include/hsl/dess/dess_interface_ctrl.h
new file mode 100755
index 0000000..08f3134
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_interface_ctrl.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_INTERFACE_CTRL_H_
+#define _DESS_INTERFACE_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_interface_ctrl.h"
+
+    sw_error_t dess_interface_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_INTERFACECONTROL
+#define DESS_INTERFACE_CTRL_INIT(rv, dev_id) \
+    { \
+        rv = dess_interface_ctrl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_INTERFACE_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    dess_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+  
+	HSL_LOCAL sw_error_t
+	dess_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+    
+	HSL_LOCAL sw_error_t
+	dess_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_INTERFACE_CTRL_H_ */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_ip.h b/qca-ssdk/include/hsl/dess/dess_ip.h
new file mode 100755
index 0000000..339bd83
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_ip.h
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_IP_H_
+#define _DESS_IP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_ip.h"
+
+    sw_error_t dess_ip_init(a_uint32_t dev_id);
+
+    sw_error_t dess_ip_reset(a_uint32_t dev_id);
+
+#ifdef IN_IP
+#define DESS_IP_INIT(rv, dev_id) \
+    { \
+        rv = dess_ip_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define DESS_IP_RESET(rv, dev_id) \
+    { \
+        rv = dess_ip_reset(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_IP_INIT(rv, dev_id)
+#define DESS_IP_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    dess_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                     fal_host_entry_t * host_entry);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                     fal_host_entry_t * host_entry);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                      fal_host_entry_t * host_entry);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                              a_uint32_t cnt_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                            a_uint32_t pppoe_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t flags);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * flags);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_source_guard_mode_t mode);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_source_guard_mode_t * mode);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_source_guard_mode_t mode);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_source_guard_mode_t * mode);
+
+    HSL_LOCAL sw_error_t
+    dess_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    dess_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                           fal_intf_mac_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                            fal_intf_mac_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+
+	HSL_LOCAL sw_error_t
+    dess_ip_rfs_ip4_set(a_uint32_t dev_id, fal_ip4_rfs_t * rfs);
+
+	HSL_LOCAL sw_error_t
+    dess_ip_rfs_ip6_set(a_uint32_t dev_id, fal_ip6_rfs_t * rfs);
+
+	HSL_LOCAL sw_error_t
+    dess_ip_rfs_ip4_del(a_uint32_t dev_id, fal_ip4_rfs_t * rfs);
+
+	HSL_LOCAL sw_error_t
+    dess_ip_rfs_ip6_del(a_uint32_t dev_id, fal_ip6_rfs_t * rfs);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_vrf_base_addr_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_vrf_base_addr_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_vrf_base_mask_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_vrf_base_mask_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_default_route_set(a_uint32_t dev_id, a_uint32_t droute_id, fal_default_route_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_default_route_get(a_uint32_t dev_id, a_uint32_t droute_id, fal_default_route_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_host_route_set(a_uint32_t dev_id, a_uint32_t hroute_id, fal_host_route_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_ip_host_route_get(a_uint32_t dev_id, a_uint32_t hroute_id, fal_host_route_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_default_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    dess_default_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    dess_default_rt_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    dess_default_rt_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t * cmd);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_IP_H_ */
diff --git a/qca-ssdk/include/hsl/dess/dess_leaky.h b/qca-ssdk/include/hsl/dess/dess_leaky.h
new file mode 100755
index 0000000..a4d3fda
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_leaky.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_LEAKY_H_
+#define _DESS_LEAKY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_leaky.h"
+
+    sw_error_t dess_leaky_init(a_uint32_t dev_id);
+
+#ifdef IN_LEAKY
+#define DESS_LEAKY_INIT(rv, dev_id) \
+    { \
+        rv = dess_leaky_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_LEAKY_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    dess_uc_leaky_mode_set(a_uint32_t dev_id,
+                           fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    dess_uc_leaky_mode_get(a_uint32_t dev_id,
+                           fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    dess_mc_leaky_mode_set(a_uint32_t dev_id,
+                           fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    dess_mc_leaky_mode_get(a_uint32_t dev_id,
+                           fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_LEAKY_H_ */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_led.h b/qca-ssdk/include/hsl/dess/dess_led.h
new file mode 100755
index 0000000..77da266
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_led.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_LED_H_
+#define _DESS_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_led.h"
+
+    sw_error_t
+    dess_led_init(a_uint32_t dev_id);
+
+#ifdef IN_LED
+#define DESS_LED_INIT(rv, dev_id) \
+    { \
+        rv = dess_led_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_LED_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    dess_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                              led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+
+    HSL_LOCAL sw_error_t
+    dess_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                              led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+	HSL_LOCAL sw_error_t
+	dess_led_source_pattern_set(a_uint32_t dev_id, a_uint32_t source_id, led_ctrl_pattern_t * pattern);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _DESS_LED_H_ */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_mib.h b/qca-ssdk/include/hsl/dess/dess_mib.h
new file mode 100755
index 0000000..12dfb29
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_mib.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_MIB_H_
+#define _DESS_MIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mib.h"
+
+    sw_error_t
+    dess_mib_init(a_uint32_t dev_id);
+
+#ifdef IN_MIB
+#define DESS_MIB_INIT(rv, dev_id) \
+    { \
+        rv = dess_mib_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_MIB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    dess_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_mib_info_t * mib_info );
+
+
+    HSL_LOCAL sw_error_t
+    dess_mib_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_mib_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id);
+
+    HSL_LOCAL sw_error_t
+    dess_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _DESS_MIB_H_ */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_mirror.h b/qca-ssdk/include/hsl/dess/dess_mirror.h
new file mode 100755
index 0000000..88c1e4f
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_mirror.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_MIRROR_H_
+#define _DESS_MIRROR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_mirror.h"
+#define  MIRROR_ANALYZER_NONE  0xf
+
+    sw_error_t dess_mirr_init(a_uint32_t dev_id);
+
+#ifdef IN_MIRROR
+#define DESS_MIRR_INIT(rv, dev_id) \
+    { \
+        rv = dess_mirr_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_MIRR_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    dess_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    dess_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id);
+
+
+    HSL_LOCAL sw_error_t
+    dess_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_MIRROR_H_ */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_misc.h b/qca-ssdk/include/hsl/dess/dess_misc.h
new file mode 100755
index 0000000..961e812
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_misc.h
@@ -0,0 +1,258 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_MISC_H_
+#define _DESS_MISC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_misc.h"
+
+    sw_error_t dess_misc_init(a_uint32_t dev_id);
+
+#ifdef IN_MISC
+#define DESS_MISC_INIT(rv, dev_id) \
+    { \
+        rv = dess_misc_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_MISC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    dess_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size);
+
+
+    HSL_LOCAL sw_error_t
+    dess_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    dess_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    dess_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    dess_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    dess_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    dess_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    dess_pppoe_session_table_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+    HSL_LOCAL sw_error_t
+    dess_pppoe_session_table_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+    HSL_LOCAL sw_error_t
+    dess_pppoe_session_table_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+    HSL_LOCAL sw_error_t
+    dess_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+                              a_uint32_t id);
+
+
+    HSL_LOCAL sw_error_t
+    dess_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+                              a_uint32_t * id);
+
+
+    HSL_LOCAL sw_error_t
+    dess_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask);
+
+
+    HSL_LOCAL sw_error_t
+    dess_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask);
+
+
+    HSL_LOCAL sw_error_t
+    dess_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status);
+
+
+    HSL_LOCAL sw_error_t
+    dess_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status);
+
+
+    HSL_LOCAL sw_error_t
+    dess_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag);
+
+
+    HSL_LOCAL sw_error_t
+    dess_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag);
+
+
+    HSL_LOCAL sw_error_t
+    dess_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag);
+
+    HSL_LOCAL sw_error_t
+    dess_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t *port_bitmap);
+
+    HSL_LOCAL sw_error_t
+    dess_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_intr_status_mac_linkchg_clear(a_uint32_t dev_id);
+
+	HSL_LOCAL sw_error_t
+	dess_global_macaddr_set(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+	HSL_LOCAL sw_error_t
+	dess_global_macaddr_get(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+	HSL_LOCAL sw_error_t
+    dess_lldp_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_lldp_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+	HSL_LOCAL sw_error_t
+    dess_frame_crc_reserve_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_frame_crc_reserve_get(a_uint32_t dev_id, a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/dess/dess_nat.h b/qca-ssdk/include/hsl/dess/dess_nat.h
new file mode 100755
index 0000000..57156fc
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_nat.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_NAT_H_
+#define _DESS_NAT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_nat.h"
+
+    sw_error_t dess_nat_init(a_uint32_t dev_id);
+
+    sw_error_t dess_nat_reset(a_uint32_t dev_id);
+
+#ifdef IN_NAT
+#define DESS_NAT_INIT(rv, dev_id) \
+    { \
+        rv = dess_nat_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define DESS_NAT_RESET(rv, dev_id) \
+    { \
+        rv = dess_nat_reset(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_NAT_INIT(rv, dev_id)
+#define DESS_NAT_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    dess_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                   fal_napt_entry_t * napt_entry);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+    HSL_LOCAL sw_error_t
+    dess_napt_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                  fal_napt_entry_t * napt_entry);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                 fal_nat_entry_t * nat_entry);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                          fal_nat_pub_addr_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                 fal_nat_entry_t * nat_entry);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                  fal_nat_entry_t * nat_entry);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                          a_uint32_t cnt_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_napt_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                  fal_napt_entry_t * napt_entry);
+
+    HSL_LOCAL sw_error_t
+    dess_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                           a_uint32_t cnt_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode);
+
+    HSL_LOCAL sw_error_t
+    dess_napt_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_napt_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode);
+
+    HSL_LOCAL sw_error_t
+    dess_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                           fal_nat_pub_addr_t * entry);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    dess_nat_global_set(a_uint32_t dev_id, a_bool_t enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_NAT_H_ */
diff --git a/qca-ssdk/include/hsl/dess/dess_nat_helper.h b/qca-ssdk/include/hsl/dess/dess_nat_helper.h
new file mode 100755
index 0000000..13c0fb1
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_nat_helper.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_NAT_HELPER_H_
+#define _DESS_NAT_HELPER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_nat.h"
+
+    sw_error_t nat_helper_init(a_uint32_t dev_id, a_uint32_t portbmp);
+
+    sw_error_t nat_helper_cleanup(a_uint32_t dev_id);
+
+#ifdef IN_NAT_HELPER
+#define DESS_NAT_HELPER_INIT(rv, dev_id, portbmp) \
+    { \
+        rv = nat_helper_init(dev_id, portbmp); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define DESS_NAT_HELPER_CLEANUP(rv, dev_id) \
+    { \
+        rv = nat_helper_cleanup(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_NAT_HELPER_INIT(rv, dev_id, portbmp)
+#define DESS_NAT_HELPER_CLEANUP(rv, dev_id)
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_NAT_HELPER_H_ */
diff --git a/qca-ssdk/include/hsl/dess/dess_port_ctrl.h b/qca-ssdk/include/hsl/dess/dess_port_ctrl.h
new file mode 100755
index 0000000..b08b0b5
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_port_ctrl.h
@@ -0,0 +1,360 @@
+/*
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_PORT_CTRL_H_
+#define _DESS_PORT_CTRL_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif				/* __cplusplus */
+
+#include "fal/fal_port_ctrl.h"
+
+  sw_error_t dess_port_ctrl_init (a_uint32_t dev_id);
+
+#ifdef IN_PORTCONTROL
+#define DESS_PORT_CTRL_INIT(rv, dev_id) \
+    { \
+        rv = dess_port_ctrl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_PORT_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id,
+			  fal_port_duplex_t duplex);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id,
+			  fal_port_duplex_t * pduplex);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_speed_set (a_uint32_t dev_id, fal_port_t port_id,
+			 fal_port_speed_t speed);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_speed_get (a_uint32_t dev_id, fal_port_t port_id,
+			 fal_port_speed_t * pspeed);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t * status);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id,
+			       a_uint32_t autoadv);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_uint32_t * autoadv);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_flowctrl_set (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_flowctrl_get (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t * enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_flowctrl_forcemode_set (a_uint32_t dev_id,
+				      fal_port_t port_id, a_bool_t enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_flowctrl_forcemode_get (a_uint32_t dev_id,
+				      fal_port_t port_id, a_bool_t * enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t * enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t * enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+		   fal_cable_status_t * cable_status, a_uint32_t * cable_len);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_rxhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_header_mode_t mode);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_rxhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_header_mode_t * mode);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_txhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_header_mode_t mode);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_txhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_header_mode_t * mode);
+
+
+  HSL_LOCAL sw_error_t
+    dess_header_type_set (a_uint32_t dev_id, a_bool_t enable,
+			  a_uint32_t type);
+
+
+  HSL_LOCAL sw_error_t
+    dess_header_type_get (a_uint32_t dev_id, a_bool_t * enable,
+			  a_uint32_t * type);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_txmac_status_set (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_txmac_status_get (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t * enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_rxmac_status_set (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_rxmac_status_get (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t * enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_txfc_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_txfc_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_rxfc_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_rxfc_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_bp_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_bp_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t * enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_link_forcemode_set (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_link_forcemode_get (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t * enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * status);
+
+  HSL_LOCAL sw_error_t
+    dess_port_mac_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t enable);
+
+
+  HSL_LOCAL sw_error_t
+    dess_port_mac_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t * enable);
+
+  HSL_LOCAL sw_error_t
+    dess_port_congestion_drop_set (a_uint32_t dev_id, fal_port_t port_id,
+				   a_uint32_t queue_id, a_bool_t enable);
+
+  HSL_LOCAL sw_error_t
+    dess_port_congestion_drop_get (a_uint32_t dev_id, fal_port_t port_id,
+				   a_uint32_t queue_id, a_bool_t * enable);
+
+  HSL_LOCAL sw_error_t
+    dess_ring_flow_ctrl_thres_set (a_uint32_t dev_id, a_uint32_t ring_id,
+				   a_uint8_t on_thres, a_uint8_t off_thres);
+
+  HSL_LOCAL sw_error_t
+    dess_ring_flow_ctrl_thres_get (a_uint32_t dev_id, a_uint32_t ring_id,
+				   a_uint8_t * on_thres,
+				   a_uint8_t * off_thres);
+
+  HSL_LOCAL sw_error_t
+    dess_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable);
+
+  HSL_LOCAL sw_error_t
+    dess_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable);
+
+  HSL_LOCAL sw_error_t
+    dess_port_mdix_set (a_uint32_t dev_id, a_uint32_t phy_id,
+			fal_port_mdix_mode_t mode);
+
+  HSL_LOCAL sw_error_t
+    dess_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id,
+			fal_port_mdix_mode_t * mode);
+
+  HSL_LOCAL sw_error_t
+    dess_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			       fal_port_mdix_status_t * mode);
+
+  HSL_LOCAL sw_error_t
+    dess_port_combo_prefer_medium_set (a_uint32_t dev_id, a_uint32_t phy_id,
+				       fal_port_medium_t phy_medium);
+
+  HSL_LOCAL sw_error_t
+    dess_port_combo_prefer_medium_get (a_uint32_t dev_id, a_uint32_t phy_id,
+				       fal_port_medium_t * phy_medium);
+
+  HSL_LOCAL sw_error_t
+    dess_port_combo_medium_status_get (a_uint32_t dev_id, a_uint32_t phy_id,
+				       fal_port_medium_t * phy_medium);
+
+  HSL_LOCAL sw_error_t
+    dess_port_combo_fiber_mode_set (a_uint32_t dev_id, a_uint32_t phy_id,
+				    fal_port_fiber_mode_t fiber_mode);
+
+  HSL_LOCAL sw_error_t
+    dess_port_combo_fiber_mode_get (a_uint32_t dev_id, a_uint32_t phy_id,
+				    fal_port_fiber_mode_t * fiber_mode);
+
+  HSL_LOCAL sw_error_t
+    dess_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t enable);
+
+  HSL_LOCAL sw_error_t
+    dess_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t * enable);
+
+  HSL_LOCAL sw_error_t
+    dess_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+				   a_bool_t enable);
+
+  HSL_LOCAL sw_error_t
+    dess_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+				   a_bool_t * enable);
+
+  HSL_LOCAL sw_error_t
+    dess_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id,
+				   fal_mac_addr_t * mac);
+
+  HSL_LOCAL sw_error_t
+    dess_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id,
+				   fal_mac_addr_t * mac);
+
+  HSL_LOCAL sw_error_t
+    dess_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id,
+		      a_uint16_t * org_id, a_uint16_t * rev_id);
+
+  HSL_LOCAL sw_error_t
+    dess_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t enable);
+
+  HSL_LOCAL sw_error_t
+    dess_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * enable);
+
+  HSL_LOCAL sw_error_t
+    dess_port_reset (a_uint32_t dev_id, fal_port_t port_id);
+
+  HSL_LOCAL sw_error_t
+    dess_port_power_off (a_uint32_t dev_id, fal_port_t port_id);
+
+  HSL_LOCAL sw_error_t
+    dess_port_power_on (a_uint32_t dev_id, fal_port_t port_id);
+
+  HSL_LOCAL sw_error_t
+    dess_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t mode);
+
+  HSL_LOCAL sw_error_t
+    dess_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t * mode);
+
+  HSL_LOCAL sw_error_t
+    dess_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t * mode);
+   HSL_LOCAL sw_error_t
+    dess_port_counter_set (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t enable);
+
+  HSL_LOCAL sw_error_t
+    dess_port_counter_get (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * enable);
+   HSL_LOCAL sw_error_t
+    dess_port_counter_show (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_counter_info_t * counter_info);
+#endif
+
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* _DESS_PORT_CTRL_H_ */
diff --git a/qca-ssdk/include/hsl/dess/dess_portvlan.h b/qca-ssdk/include/hsl/dess/dess_portvlan.h
new file mode 100755
index 0000000..e68e127
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_portvlan.h
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_PORTVLAN_H_
+#define _DESS_PORTVLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_portvlan.h"
+
+    sw_error_t dess_portvlan_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTVLAN
+#define DESS_PORTVLAN_INIT(rv, dev_id) \
+    { \
+        rv = dess_portvlan_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_PORTVLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_1qmode_t port_1qmode);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_1qmode_t * pport_1qmode);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pt_1q_egmode_t port_egvlanmode);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pt_1q_egmode_t * pport_egvlanmode);
+
+
+    HSL_LOCAL sw_error_t
+    dess_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t mem_port_id);
+
+
+    HSL_LOCAL sw_error_t
+    dess_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t mem_port_id);
+
+
+    HSL_LOCAL sw_error_t
+    dess_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_pbmp_t mem_port_map);
+
+
+    HSL_LOCAL sw_error_t
+    dess_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pbmp_t * mem_port_map);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid);
+
+
+    HSL_LOCAL sw_error_t
+    dess_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pt_invlan_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pt_invlan_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+                      a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+                      a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t vid);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * vid);
+
+    HSL_LOCAL sw_error_t
+    dess_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t vid);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * vid);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_vlan_propagation_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_vlan_propagation_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t * iterator, fal_vlan_trans_entry_t * entry);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_netisolate_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_netisolate_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_PORTVLAN_H */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_psgmii.h b/qca-ssdk/include/hsl/dess/dess_psgmii.h
new file mode 100755
index 0000000..7c9b580
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_psgmii.h
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _DESS_PSGMII_H_
+#define _DESS_PSGMII_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+/*PSGMII Registers*/
+#define PSGMIIPHY_MODECFG_1   0xcc
+#define PSGMIIPHY_PHY_INTERFACE  0x10C
+#define PSGMIIPHY_EEE_CH0_1		0x168
+#define PSGMIIPHY_EEE_CH0_2		0x16C
+#define PSGMIIPHY_EEE_CH0_3		0x170
+#define PSGMIIPHY_EEE_CH0_4		0x174
+#define PSGMIIPHY_EEE_CH0_5		0x178
+#define PSGMIIPHY_EEE_CH0_6		0x17C
+#define PSGMIIPHY_EEE_CH0_7		0x180
+#define PSGMIIPHY_EEE_CH1_1		0x184
+#define PSGMIIPHY_EEE_CH1_2		0x188
+#define PSGMIIPHY_EEE_CH1_3		0x18C
+#define PSGMIIPHY_EEE_CH2_1		0x190
+#define PSGMIIPHY_EEE_CH2_2		0x194
+#define PSGMIIPHY_EEE_CH2_3		0x198
+#define PSGMIIPHY_EEE_CH3_1		0x19C
+#define PSGMIIPHY_EEE_CH3_2		0x1A0
+#define PSGMIIPHY_EEE_CH3_3		0x1A4
+#define PSGMIIPHY_EEE_CH4_1		0x1A8
+#define PSGMIIPHY_EEE_CH4_2		0x1AC
+#define PSGMIIPHY_EEE_CH4_3		0x1B0
+
+#define PSGMIIPHY_MODE_CONTROL          0x1b4
+#define PSGMIIPHY_FIFO                        0x1b8
+
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_1	0x1BC
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4	0x1C8
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5	0x1CC
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4	0x1e0
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5	0x1e4
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4	0x1f8
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5	0x1fC
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4	0x210
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5	0x214
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4	0x228
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5	0x22C
+
+#define PSGMIIPHY_CHANNEL0TXSTATE			0x248
+#define PSGMIIPHY_CHANNEL0RXSTATES			0x24c
+#define PSGMIIPHY_CHANNEL1TXSTATE			0x250
+#define PSGMIIPHY_CHANNEL1RXSTATES			0x254
+#define PSGMIIPHY_CHANNEL2TXSTATE			0x258
+#define PSGMIIPHY_CHANNEL2RXSTATES			0x25c
+#define PSGMIIPHY_CHANNEL3TXSTATE			0x260
+#define PSGMIIPHY_CHANNEL3RXSTATES			0x264
+#define PSGMIIPHY_CHANNEL4TXSTATE			0x268
+#define PSGMIIPHY_CHANNEL4RXSTATES			0x26c
+
+/* PSGMII Registers Field*/
+
+/*PSGMIIPHY_EEE_CH0_1 register field*/
+#define PSGMIIPHY_EEE_DIS_LPI 0x2
+#define PSGMIIPHY_EEE_EN_LPI 0x1
+
+/*PSGMIIPHY_MODE_CONTROL register field*/
+#define PSGMIIPHY_MODE_SW_V17_V18 0x8000
+/* Interface Mode, bits 12:14 */
+#define PSGMIIPHY_MODE_CH0_MODE_1000BASEX      0x0000
+#define PSGMIIPHY_MODE_CH0_MODE_PSGMII_PHY      0x1000
+#define PSGMIIPHY_MODE_CH0_MODE_PSGMII_MAC      0x2000
+#define PSGMIIPHY_MODE_CH0_PSGMII_QSGMII 0x200
+#define PSGMIIPHY_MODE_CH0_QSGMII_SGMII 0x100
+#define PSGMIIPHY_MODE_SGMII_EVEN_LOW 0x0008
+#define PSGMIIPHY_MODE_CH4_CH1_0_SGMII 0x0004
+#define PSGMIIPHY_MODE_CH1_CH0_SGMII 0x0002
+#define PSGMIIPHY_MODE_CH0_ATHR_CSCO_MODE_25M 0x0001
+
+/*CHANNEL_0_INPUT_OUTPUT_1 register field*/
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_1_MR_AN_COMPLETE 0x800
+
+/*CHANNEL_0_INPUT_OUTPUT_4 register field*/
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_POWER_ON_25M 0x400
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MAIN_RESET_25M 0x200
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M 0x100
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_RESTART_AN_25M 0x80
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_AN_ENABLE_25M 0x40
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MR_REG4_CH_25M 0x20
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MR_NP_LOADED_25M 0x10
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_FORCE_SPEED_25M 0x08
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_SPEED_25M_10M 0x02
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_SPEED_25M_100M 0x04
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_SPEED_25M_1000M 0x06
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_REM_PHY_LPBK 0x00
+
+/*CHANNEL_0_INPUT_OUTPUT_5 register field*/
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_FULL_DUPLEX_25M 0x800
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_HALF_DUPLEX_25M 0x400
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_REMOTE_FAULT_25M 0x300
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_LINK_25M 0x80
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_DUPLEX_MODE_25M 0x40
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_SPEED_MODE_25M 0x30
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_PAUSE_SG_TX_EN_25M 0x08
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_NEXT_PAGE_25M 0x04
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_PAUSE_25M 0x02
+#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_ASYM_PAUSE_25M 0x01
+
+/*CHANNEL_1_INPUT_OUTPUT_4 register field*/
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_POWER_ON_25M 0x400
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_MR_MAIN_RESET_25M 0x200
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M 0x100
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_MR_RESTART_AN_25M 0x80
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_MR_AN_ENABLE_25M 0x40
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_MR_MR_REG4_CH_25M 0x20
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_MR_MR_NP_LOADED_25M 0x10
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_FORCE_SPEED_25M 0x08
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_SPEED_25M_10M 0x02
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_SPEED_25M_100M 0x04
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_SPEED_25M_1000M 0x06
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_REM_PHY_LPBK 0x00
+
+/*CHANNEL_1_INPUT_OUTPUT_5 register field*/
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_FULL_DUPLEX_25M 0x800
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_HALF_DUPLEX_25M 0x400
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_REMOTE_FAULT_25M 0x300
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_LINK_25M 0x80
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_DUPLEX_MODE_25M 0x40
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_SPEED_MODE_25M 0x30
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_PAUSE_SG_TX_EN_25M 0x08
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_NEXT_PAGE_25M 0x04
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_PAUSE_25M 0x02
+#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_ASYM_PAUSE_25M 0x01
+
+/*CHANNEL_2_INPUT_OUTPUT_4 register field*/
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_POWER_ON_25M 0x400
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_MR_MAIN_RESET_25M 0x200
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M 0x100
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_MR_RESTART_AN_25M 0x80
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_MR_AN_ENABLE_25M 0x40
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_MR_MR_REG4_CH_25M 0x20
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_MR_MR_NP_LOADED_25M 0x10
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_FORCE_SPEED_25M 0x08
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_SPEED_25M_10M 0x02
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_SPEED_25M_100M 0x04
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_SPEED_25M_1000M 0x06
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_REM_PHY_LPBK 0x00
+
+/*CHANNEL_2_INPUT_OUTPUT_5 register field*/
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_FULL_DUPLEX_25M 0x800
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_HALF_DUPLEX_25M 0x400
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_REMOTE_FAULT_25M 0x300
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_LINK_25M 0x80
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_DUPLEX_MODE_25M 0x40
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_SPEED_MODE_25M 0x30
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_PAUSE_SG_TX_EN_25M 0x08
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_NEXT_PAGE_25M 0x04
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_PAUSE_25M 0x02
+#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_ASYM_PAUSE_25M 0x01
+
+/*CHANNEL_3_INPUT_OUTPUT_4 register field*/
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_POWER_ON_25M 0x400
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_MR_MAIN_RESET_25M 0x200
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M 0x100
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_MR_RESTART_AN_25M 0x80
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_MR_AN_ENABLE_25M 0x40
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_MR_MR_REG4_CH_25M 0x20
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_MR_MR_NP_LOADED_25M 0x10
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_FORCE_SPEED_25M 0x08
+
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_MASK 0x06
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_10M 0x0
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_100M 0x02
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_1000M 0x04
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_REM_PHY_LPBK 0x00
+
+/*CHANNEL_3_INPUT_OUTPUT_5 register field*/
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_FULL_DUPLEX_25M 0x800
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_HALF_DUPLEX_25M 0x400
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_REMOTE_FAULT_25M 0x300
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_LINK_25M 0x80
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_DUPLEX_MODE_25M 0x40
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_MODE_25M 0x30
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_25M_10M 0x00
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_25M_100M 0x10
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_25M_1000M 0x20
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_PAUSE_SG_TX_EN_25M 0x08
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_NEXT_PAGE_25M 0x04
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_PAUSE_25M 0x02
+#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_ASYM_PAUSE_25M 0x01
+
+/*CHANNEL_4_INPUT_OUTPUT_4 register field*/
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_POWER_ON_25M 0x400
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_MR_MAIN_RESET_25M 0x200
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M 0x100
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_MR_RESTART_AN_25M 0x80
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_MR_AN_ENABLE_25M 0x40
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_MR_MR_REG4_CH_25M 0x20
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_MR_MR_NP_LOADED_25M 0x10
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_FORCE_SPEED_25M 0x08
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_SPEED_25M_10M 0x02
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_SPEED_25M_100M 0x04
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_SPEED_25M_1000M 0x06
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_REM_PHY_LPBK 0x00
+
+/*CHANNEL_4_INPUT_OUTPUT_5 register field*/
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_FULL_DUPLEX_25M 0x800
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_HALF_DUPLEX_25M 0x400
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_REMOTE_FAULT_25M 0x300
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_LINK_25M 0x80
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_DUPLEX_MODE_25M 0x40
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_SPEED_MODE_25M 0x30
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_PAUSE_SG_TX_EN_25M 0x08
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_NEXT_PAGE_25M 0x04
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_PAUSE_25M 0x02
+#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_ASYM_PAUSE_25M 0x01
+
+typedef enum {
+        PSGMII_MAC_MODE_PSGMII = 0,
+        PSGMII_MAC_MODE_QSGMII,
+        PSGMII_MAC_MODE_SGMII,
+        PSGMII_MAC_MODE_DEFAULT
+}psgmii_interface_mac_mode_t;
+
+    sw_error_t
+    dess_psgmii_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+             a_uint32_t value_len);
+
+    sw_error_t
+    dess_psgmii_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+             a_uint32_t value_len);
+
+    sw_error_t
+    dess_psgmii_set_lpi(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable);
+
+    sw_error_t
+    dess_psgmii_get_lpi(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable);
+
+    sw_error_t
+    dess_psgmii_set_interface_type(a_uint32_t dev_id, a_uint32_t phy_id,
+										psgmii_interface_mac_mode_t mode);
+
+    sw_error_t
+    dess_psgmii_get_interface_type(a_uint32_t dev_id, a_uint32_t * phy_id,
+										psgmii_interface_mac_mode_t * mode);
+
+    a_bool_t
+    dess_psgmii_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id);
+
+    sw_error_t
+    dess_psgmii_reset(a_uint32_t dev_id, a_uint32_t phy_id);
+
+    sw_error_t
+    dess_psgmii_poweroff(a_uint32_t dev_id, a_uint32_t phy_id);
+
+    sw_error_t
+    dess_psgmii_poweron(a_uint32_t dev_id, a_uint32_t phy_id);
+
+    a_bool_t
+    dess_psgmii_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id);
+
+    sw_error_t
+    dess_psgmii_set_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+                           a_bool_t enable);
+
+    sw_error_t
+    dess_psgmii_get_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+                           a_bool_t * enable);
+
+    a_bool_t dess_psgmii_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id);
+
+    sw_error_t
+    dess_psgmii_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id);
+
+    sw_error_t
+    dess_psgmii_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id);
+
+    sw_error_t
+    dess_psgmii_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+                      fal_port_duplex_t duplex);
+
+    sw_error_t
+    dess_psgmii_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+                      fal_port_duplex_t * duplex);
+
+    sw_error_t
+    dess_psgmii_set_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+                     fal_port_speed_t speed);
+
+    sw_error_t
+    dess_psgmii_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+                     fal_port_speed_t * speed);
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_PSGMII_H_ */
diff --git a/qca-ssdk/include/hsl/dess/dess_qos.h b/qca-ssdk/include/hsl/dess/dess_qos.h
new file mode 100755
index 0000000..083e3a8
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_qos.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_QOS_H_
+#define _DESS_QOS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_qos.h"
+
+    sw_error_t dess_qos_init(a_uint32_t dev_id);
+
+#ifdef IN_QOS
+#define DESS_QOS_INIT(rv, dev_id) \
+    { \
+        rv = dess_qos_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_QOS_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_queue_tx_buf_status_set(a_uint32_t dev_id,
+                                     fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_queue_tx_buf_status_get(a_uint32_t dev_id,
+                                     fal_port_t port_id,
+                                     a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t* enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_queue_t queue_id,
+                                 a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_queue_t queue_id,
+                                 a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_qos_mode_t mode, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_qos_mode_t mode, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_qos_mode_t mode, a_uint32_t pri);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_qos_mode_t mode, a_uint32_t * pri);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                               fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                               fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_uint32_t spri);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_uint32_t * spri);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_uint32_t cpri);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_uint32_t * cpri);
+
+    sw_error_t
+    dess_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                        a_bool_t enable);
+
+    sw_error_t
+    dess_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                        a_bool_t* enable);
+
+    sw_error_t
+    dess_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                        a_bool_t enable);
+
+    sw_error_t
+    dess_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                        a_bool_t* enable);
+
+    HSL_LOCAL sw_error_t
+    dess_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_QOS_H_ */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_rate.h b/qca-ssdk/include/hsl/dess/dess_rate.h
new file mode 100755
index 0000000..d5316f9
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_rate.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_RATE_H_
+#define _DESS_RATE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_rate.h"
+
+    sw_error_t dess_rate_init(a_uint32_t dev_id);
+
+#ifdef IN_RATE
+#define DESS_RATE_INIT(rv, dev_id) \
+    { \
+        rv = dess_rate_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_RATE_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    dess_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_port_policer_t * policer);
+
+    HSL_LOCAL sw_error_t
+    dess_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_port_policer_t * policer);
+
+    HSL_LOCAL sw_error_t
+    dess_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable,
+                              fal_egress_shaper_t * shaper);
+
+    HSL_LOCAL sw_error_t
+    dess_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable,
+                              fal_egress_shaper_t * shaper);
+
+    HSL_LOCAL sw_error_t
+    dess_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_bool_t enable,
+                               fal_egress_shaper_t * shaper);
+
+    HSL_LOCAL sw_error_t
+    dess_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_bool_t * enable,
+                               fal_egress_shaper_t * shaper);
+
+    HSL_LOCAL sw_error_t
+    dess_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+                              fal_acl_policer_t * policer);
+
+    HSL_LOCAL sw_error_t
+    dess_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+                              fal_acl_policer_t * policer);
+
+    HSL_LOCAL sw_error_t
+    dess_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_uint32_t  number);
+
+    HSL_LOCAL sw_error_t
+    dess_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_uint32_t  *number);
+
+    HSL_LOCAL sw_error_t
+    dess_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t  enable);
+
+    HSL_LOCAL sw_error_t
+    dess_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t*  enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_RATE_H_ */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_reg.h b/qca-ssdk/include/hsl/dess/dess_reg.h
new file mode 100755
index 0000000..89b67d1
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_reg.h
@@ -0,0 +1,5011 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _DESS_REG_H_
+#define _DESS_REG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#define DESS_DEVICE_ID   0x14 /* TBD */
+
+#define MAX_ENTRY_LEN   128
+
+#define HSL_RW 1
+#define HSL_RO 0
+
+
+    /* DESS Mask Control Register */
+#define MASK_CTL
+#define MASK_CTL_ID               0
+#define MASK_CTL_OFFSET           0x0000
+#define MASK_CTL_E_LENGTH         4
+#define MASK_CTL_E_OFFSET         0
+#define MASK_CTL_NR_E             1
+
+#define DEVICE_ID
+#define MASK_CTL_DEVICE_ID_BOFFSET            8
+#define MASK_CTL_DEVICE_ID_BLEN               8
+#define MASK_CTL_DEVICE_ID_FLAG               HSL_RO
+
+#define REV_ID
+#define MASK_CTL_REV_ID_BOFFSET               0
+#define MASK_CTL_REV_ID_BLEN                  8
+#define MASK_CTL_REV_ID_FLAG                  HSL_RO
+
+
+/* RGMII Control Register */
+#define RGMII_CTRL
+#define RGMII_CTRL_ID                                          0
+#define RGMII_CTRL_OFFSET                                      0x0004
+#define RGMII_CTRL_E_LENGTH                                    4
+#define RGMII_CTRL_E_OFFSET                                    0
+#define RGMII_CTRL_NR_E                                        1
+
+#define RMII1_MASTER_EN
+#define RGMII_CTRL_RMII1_MASTER_EN_BOFFSET                            25
+#define RGMII_CTRL_RMII1_MASTER_EN_BLEN                               1
+#define RGMII_CTRL_RMII1_MASTER_EN_FLAG                               HSL_RW
+
+#define RMII0_MASTER_EN
+#define RGMII_CTRL_RMII0_MASTER_EN_BOFFSET                            24
+#define RGMII_CTRL_RMII0_MASTER_EN_BLEN                               1
+#define RGMII_CTRL_RMII0_MASTER_EN_FLAG                               HSL_RW
+
+
+/* Global Interrupt Status Register1 */
+#define GBL_INT_STATUS1
+#define GBL_INT_STATUS1_ID             1
+#define GBL_INT_STATUS1_OFFSET         0x0024
+#define GBL_INT_STATUS1_E_LENGTH       4
+#define GBL_INT_STATUS1_E_OFFSET       0
+#define GBL_INT_STATUS1_NR_E           1
+
+#define LINK_CHG_INT_S
+#define GBL_INT_STATUS1_LINK_CHG_INT_S_BOFFSET 1
+#define GBL_INT_STATUS1_LINK_CHG_INT_S_BLEN        7
+#define GBL_INT_STATUS1_LINK_CHG_INT_S_FLAG    HSL_RW
+
+#define PHY_INT_S
+#define GBL_INT_STATUS1_PHY_INT_S_BOFFSET         15
+#define GBL_INT_STATUS1_PHY_INT_S_BLEN            1
+#define GBL_INT_STATUS1_PHY_INT_S_FLAG            HSL_RO
+
+
+    /* Global Interrupt Mask Register1 */
+#define GBL_INT_MASK1
+#define GBL_INT_MASK1_ID             1
+#define GBL_INT_MASK1_OFFSET         0x002c
+#define GBL_INT_MASK1_E_LENGTH       4
+#define GBL_INT_MASK1_E_OFFSET       0
+#define GBL_INT_MASK1_NR_E           1
+
+#define LINK_CHG_INT_M
+#define GBL_INT_MASK1_LINK_CHG_INT_M_BOFFSET 1
+#define GBL_INT_MASK1_LINK_CHG_INT_M_BLEN        7
+#define GBL_INT_MASK1_LINK_CHG_INT_M_FLAG    HSL_RW
+
+#define PHY_INT_M
+#define GBL_INT_MASK1_PHY_INT_M_BOFFSET           15
+#define GBL_INT_MASK1_PHY_INT_M_BLEN              1
+#define GBL_INT_MASK1_PHY_INT_M_FLAG              HSL_RO
+
+
+
+
+    /* Module Enable Register */
+#define MOD_ENABLE
+#define MOD_ENABLE_OFFSET           0x0030
+#define MOD_ENABLE_E_LENGTH         4
+#define MOD_ENABLE_E_OFFSET         0
+#define MOD_ENABLE_NR_E             1
+
+#define L3_EN
+#define MOD_ENABLE_L3_EN_BOFFSET                  2
+#define MOD_ENABLE_L3_EN_BLEN                     1
+#define MOD_ENABLE_L3_EN_FLAG                     HSL_RW
+
+#define ACL_EN
+#define MOD_ENABLE_ACL_EN_BOFFSET                 1
+#define MOD_ENABLE_ACL_EN_BLEN                    1
+#define MOD_ENABLE_ACL_EN_FLAG                    HSL_RW
+
+#define MIB_EN
+#define MOD_ENABLE_MIB_EN_BOFFSET                 0
+#define MOD_ENABLE_MIB_EN_BLEN                    1
+#define MOD_ENABLE_MIB_EN_FLAG                    HSL_RW
+
+
+
+
+    /* MIB Function Register */
+#define MIB_FUNC
+#define MIB_FUNC_OFFSET           0x0034
+#define MIB_FUNC_E_LENGTH         4
+#define MIB_FUNC_E_OFFSET         0
+#define MIB_FUNC_NR_E             1
+
+#define MIB_FUN
+#define MIB_FUNC_MIB_FUN_BOFFSET               24
+#define MIB_FUNC_MIB_FUN_BLEN                  3
+#define MIB_FUNC_MIB_FUN_FLAG                  HSL_RW
+
+#define MIB_FLUSH_PORT
+#define MIB_FUNC_MIB_FLUSH_PORT_BOFFSET        21
+#define MIB_FUNC_MIB_FLUSH_PORT_BLEN            3
+#define MIB_FUNC_MIB_FLUSH_PORT_FLAG          HSL_RW
+
+#define MIB_CPU_KEEP
+#define MIB_FUNC_MIB_CPU_KEEP_BOFFSET     20
+#define MIB_FUNC_MIB_CPU_KEEP_BLEN          1
+#define MIB_FUNC_MIB_CPU_KEEP_FLAG         HSL_RW
+
+#define MIB_BUSY
+#define MIB_FUNC_MIB_BUSY_BOFFSET              17
+#define MIB_FUNC_MIB_BUSY_BLEN                 1
+#define MIB_FUNC_MIB_BUSY_FLAG                 HSL_RW
+
+#define MIB_AT_HALF_EN
+#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET        16
+#define MIB_FUNC_MIB_AT_HALF_EN_BLEN           1
+#define MIB_FUNC_MIB_AT_HALF_EN_FLAG           HSL_RW
+
+#define MIB_TIMER
+#define MIB_FUNC_MIB_TIMER_BOFFSET             0
+#define MIB_FUNC_MIB_TIMER_BLEN                16
+#define MIB_FUNC_MIB_TIMER_FLAG                HSL_RW
+
+
+
+
+    /* Service tag Register */
+#define SERVICE_TAG
+#define SERVICE_TAG_OFFSET           0x0048
+#define SERVICE_TAG_E_LENGTH         4
+#define SERVICE_TAG_E_OFFSET         0
+#define SERVICE_TAG_NR_E             1
+
+#define STAG_MODE
+#define SERVICE_TAG_STAG_MODE_BOFFSET    17
+#define SERVICE_TAG_STAG_MODE_BLEN       1
+#define SERVICE_TAG_STAG_MODE_FLAG       HSL_RW
+
+#define TAG_VALUE
+#define SERVICE_TAG_TAG_VALUE_BOFFSET    0
+#define SERVICE_TAG_TAG_VALUE_BLEN       16
+#define SERVICE_TAG_TAG_VALUE_FLAG       HSL_RW
+
+
+
+
+    /* Global MAC Address Register */
+#define GLOBAL_MAC_ADDR0
+#define GLOBAL_MAC_ADDR0_OFFSET    0x0060
+#define GLOBAL_MAC_ADDR0_E_LENGTH  4
+#define GLOBAL_MAC_ADDR0_E_OFFSET  0
+#define GLOBAL_MAC_ADDR0_NR_E      1
+
+#define GLB_BYTE4
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET         8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN            8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG            HSL_RW
+
+#define GLB_BYTE5
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET         0
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN            8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG            HSL_RW
+
+#define GLOBAL_MAC_ADDR1
+#define GLOBAL_MAC_ADDR1_ID        4
+#define GLOBAL_MAC_ADDR1_OFFSET    0x0064
+#define GLOBAL_MAC_ADDR1_E_LENGTH  4
+#define GLOBAL_MAC_ADDR1_E_OFFSET  0
+#define GLOBAL_MAC_ADDR1_NR_E      1
+
+#define GLB_BYTE0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET         24
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG            HSL_RW
+
+#define GLB_BYTE1
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET         16
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG            HSL_RW
+
+#define GLB_BYTE2
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET         8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG            HSL_RW
+
+#define GLB_BYTE3
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET         0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG            HSL_RW
+
+
+
+
+    /* Max Size Register */
+#define MAX_SIZE
+#define MAX_SIZE_OFFSET        0x0078
+#define MAX_SIZE_E_LENGTH      4
+#define MAX_SIZE_E_OFFSET      0
+#define MAX_SIZE_NR_E          1
+
+#define CRC_RESERVE
+#define MAX_SIZE_CRC_RESERVE_BOFFSET     16
+#define MAX_SIZE_CRC_RESERVE_BLEN        1
+#define MAX_SIZE_CRC_RESERVE_FLAG        HSL_RW
+
+#define MAX_FRAME_SIZE
+#define MAX_SIZE_MAX_FRAME_SIZE_BOFFSET     0
+#define MAX_SIZE_MAX_FRAME_SIZE_BLEN        14
+#define MAX_SIZE_MAX_FRAME_SIZE_FLAG        HSL_RW
+
+
+
+
+
+
+
+
+
+
+
+
+    /* Port Status Register */
+#define PORT_STATUS
+#define PORT_STATUS_OFFSET        0x007c
+#define PORT_STATUS_E_LENGTH      4
+#define PORT_STATUS_E_OFFSET      0x0004
+#define PORT_STATUS_NR_E          7
+
+#define FLOW_LINK_EN
+#define PORT_STATUS_FLOW_LINK_EN_BOFFSET        12
+#define PORT_STATUS_FLOW_LINK_EN_BLEN           1
+#define PORT_STATUS_FLOW_LINK_EN_FLAG           HSL_RW
+
+#define AUTO_RX_FLOW
+#define PORT_STATUS_AUTO_RX_FLOW_BOFFSET        11
+#define PORT_STATUS_AUTO_RX_FLOW_BLEN           1
+#define PORT_STATUS_AUTO_RX_FLOW_FLAG           HSL_RO
+
+#define AUTO_TX_FLOW
+#define PORT_STATUS_AUTO_TX_FLOW_BOFFSET        10
+#define PORT_STATUS_AUTO_TX_FLOW_BLEN           1
+#define PORT_STATUS_AUTO_TX_FLOW_FLAG           HSL_RO
+
+#define LINK_EN
+#define PORT_STATUS_LINK_EN_BOFFSET             9
+#define PORT_STATUS_LINK_EN_BLEN                1
+#define PORT_STATUS_LINK_EN_FLAG                HSL_RW
+
+#define LINK
+#define PORT_STATUS_LINK_BOFFSET                8
+#define PORT_STATUS_LINK_BLEN                   1
+#define PORT_STATUS_LINK_FLAG                   HSL_RO
+
+#define TX_HALF_FLOW_EN
+#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET     7
+#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN        1
+#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG        HSL_RW
+
+#define DUPLEX_MODE
+#define PORT_STATUS_DUPLEX_MODE_BOFFSET         6
+#define PORT_STATUS_DUPLEX_MODE_BLEN            1
+#define PORT_STATUS_DUPLEX_MODE_FLAG            HSL_RW
+
+#define RX_FLOW_EN
+#define PORT_STATUS_RX_FLOW_EN_BOFFSET          5
+#define PORT_STATUS_RX_FLOW_EN_BLEN             1
+#define PORT_STATUS_RX_FLOW_EN_FLAG             HSL_RW
+
+#define TX_FLOW_EN
+#define PORT_STATUS_TX_FLOW_EN_BOFFSET          4
+#define PORT_STATUS_TX_FLOW_EN_BLEN             1
+#define PORT_STATUS_TX_FLOW_EN_FLAG             HSL_RW
+
+#define RXMAC_EN
+#define PORT_STATUS_RXMAC_EN_BOFFSET            3
+#define PORT_STATUS_RXMAC_EN_BLEN               1
+#define PORT_STATUS_RXMAC_EN_FLAG               HSL_RW
+
+#define TXMAC_EN
+#define PORT_STATUS_TXMAC_EN_BOFFSET            2
+#define PORT_STATUS_TXMAC_EN_BLEN               1
+#define PORT_STATUS_TXMAC_EN_FLAG               HSL_RW
+
+#define SPEED_MODE
+#define PORT_STATUS_SPEED_MODE_BOFFSET          0
+#define PORT_STATUS_SPEED_MODE_BLEN             2
+#define PORT_STATUS_SPEED_MODE_FLAG             HSL_RW
+
+
+
+
+    /* Header Ctl Register */
+#define HEADER_CTL
+#define HEADER_CTL_OFFSET        0x0098
+#define HEADER_CTL_E_LENGTH      4
+#define HEADER_CTL_E_OFFSET      0x0004
+#define HEADER_CTL_NR_E          1
+
+#define TYPE_LEN
+#define HEADER_CTL_TYPE_LEN_BOFFSET          16
+#define HEADER_CTL_TYPE_LEN_BLEN             1
+#define HEADER_CTL_TYPE_LEN_FLAG             HSL_RW
+
+#define TYPE_VAL
+#define HEADER_CTL_TYPE_VAL_BOFFSET         0
+#define HEADER_CTL_TYPE_VAL_BLEN            16
+#define HEADER_CTL_TYPE_VAL_FLAG            HSL_RW
+
+
+
+
+    /* Port Header Ctl Register */
+#define PORT_HDR_CTL
+#define PORT_HDR_CTL_OFFSET        0x009c
+#define PORT_HDR_CTL_E_LENGTH      4
+#define PORT_HDR_CTL_E_OFFSET      0x0004
+#define PORT_HDR_CTL_NR_E          7
+
+#define IPG_DEC_EN
+#define PORT_HDR_CTL_IPG_DEC_EN_BOFFSET          5
+#define PORT_HDR_CTL_IPG_DEC_EN_BLEN             1
+#define PORT_HDR_CTL_IPG_DEC_EN_FLAG             HSL_RW
+
+#define LOOPBACK_EN
+#define PORT_HDR_CTL_LOOPBACK_EN_BOFFSET         4
+#define PORT_HDR_CTL_LOOPBACK_EN_BLEN            1
+#define PORT_HDR_CTL_LOOPBACK_EN_FLAG            HSL_RW
+
+#define RXHDR_MODE
+#define PORT_HDR_CTL_RXHDR_MODE_BOFFSET          2
+#define PORT_HDR_CTL_RXHDR_MODE_BLEN             2
+#define PORT_HDR_CTL_RXHDR_MODE_FLAG             HSL_RW
+
+#define TXHDR_MODE
+#define PORT_HDR_CTL_TXHDR_MODE_BOFFSET          0
+#define PORT_HDR_CTL_TXHDR_MODE_BLEN             2
+#define PORT_HDR_CTL_TXHDR_MODE_FLAG             HSL_RW
+
+
+
+
+    /* EEE control Register */
+#define EEE_CTL
+#define EEE_CTL_OFFSET    0x0100
+#define EEE_CTL_E_LENGTH  4
+#define EEE_CTL_E_OFFSET  0
+#define EEE_CTL_NR_E      1
+
+#define LPI_STATE_REMAP_EN_5
+#define EEE_CTL_LPI_STATE_REMAP_EN_5_BOFFSET                   13
+#define EEE_CTL_LPI_STATE_REMAP_EN_5_BLEN                      1
+#define EEE_CTL_LPI_STATE_REMAP_EN_5_FLAG                      HSL_RW
+
+#define LPI_EN_5
+#define EEE_CTL_LPI_EN_5_BOFFSET                               12
+#define EEE_CTL_LPI_EN_5_BLEN                                  1
+#define EEE_CTL_LPI_EN_5_FLAG                                  HSL_RW
+
+#define LPI_STATE_REMAP_EN_4
+#define EEE_CTL_LPI_STATE_REMAP_EN_4_BOFFSET                   11
+#define EEE_CTL_LPI_STATE_REMAP_EN_4_BLEN                      1
+#define EEE_CTL_LPI_STATE_REMAP_EN_4_FLAG                      HSL_RW
+
+#define LPI_EN_4
+#define EEE_CTL_LPI_EN_4_BOFFSET                               10
+#define EEE_CTL_LPI_EN_4_BLEN                                  1
+#define EEE_CTL_LPI_EN_4_FLAG                                  HSL_RW
+
+#define LPI_STATE_REMAP_EN_3
+#define EEE_CTL_LPI_STATE_REMAP_EN_3_BOFFSET                   9
+#define EEE_CTL_LPI_STATE_REMAP_EN_3_BLEN                      1
+#define EEE_CTL_LPI_STATE_REMAP_EN_3_FLAG                      HSL_RW
+
+#define LPI_EN_3
+#define EEE_CTL_LPI_EN_3_BOFFSET                               8
+#define EEE_CTL_LPI_EN_3_BLEN                                  1
+#define EEE_CTL_LPI_EN_3_FLAG                                  HSL_RW
+
+#define LPI_STATE_REMAP_EN_2
+#define EEE_CTL_LPI_STATE_REMAP_EN_2_BOFFSET                   7
+#define EEE_CTL_LPI_STATE_REMAP_EN_2_BLEN                      1
+#define EEE_CTL_LPI_STATE_REMAP_EN_2_FLAG                      HSL_RW
+
+#define LPI_EN_2
+#define EEE_CTL_LPI_EN_2_BOFFSET                               6
+#define EEE_CTL_LPI_EN_2_BLEN                                  1
+#define EEE_CTL_LPI_EN_2_FLAG                                  HSL_RW
+
+#define LPI_STATE_REMAP_EN_1
+#define EEE_CTL_LPI_STATE_REMAP_EN_1_BOFFSET                   5
+#define EEE_CTL_LPI_STATE_REMAP_EN_1_BLEN                      1
+#define EEE_CTL_LPI_STATE_REMAP_EN_1_FLAG                      HSL_RW
+
+#define LPI_EN_1
+#define EEE_CTL_LPI_EN_1_BOFFSET                               4
+#define EEE_CTL_LPI_EN_1_BLEN                                  1
+#define EEE_CTL_LPI_EN_1_FLAG                                  HSL_RW
+
+
+
+
+    /* Frame Ack Ctl0 Register */
+#define FRAME_ACK_CTL0
+#define FRAME_ACK_CTL0_OFFSET    0x0210
+#define FRAME_ACK_CTL0_E_LENGTH  4
+#define FRAME_ACK_CTL0_E_OFFSET  0
+#define FRAME_ACK_CTL0_NR_E      1
+
+#define ARP_REQ_EN
+#define FRAME_ACK_CTL0_ARP_REQ_EN_BOFFSET             6
+#define FRAME_ACK_CTL0_ARP_REQ_EN_BLEN                1
+#define FRAME_ACK_CTL0_ARP_REQ_EN_FLAG                HSL_RW
+
+#define ARP_REP_EN
+#define FRAME_ACK_CTL0_ARP_REP_EN_BOFFSET             5
+#define FRAME_ACK_CTL0_ARP_REP_EN_BLEN                1
+#define FRAME_ACK_CTL0_ARP_REP_EN_FLAG                HSL_RW
+
+#define DHCP_EN
+#define FRAME_ACK_CTL0_DHCP_EN_BOFFSET                4
+#define FRAME_ACK_CTL0_DHCP_EN_BLEN                   1
+#define FRAME_ACK_CTL0_DHCP_EN_FLAG                   HSL_RW
+
+#define EAPOL_EN
+#define FRAME_ACK_CTL0_EAPOL_EN_BOFFSET               3
+#define FRAME_ACK_CTL0_EAPOL_EN_BLEN                  1
+#define FRAME_ACK_CTL0_EAPOL_EN_FLAG                  HSL_RW
+
+#define LEAVE_EN
+#define FRAME_ACK_CTL0_LEAVE_EN_BOFFSET               2
+#define FRAME_ACK_CTL0_LEAVE_EN_BLEN                  1
+#define FRAME_ACK_CTL0_LEAVE_EN_FLAG                  HSL_RW
+
+#define JOIN_EN
+#define FRAME_ACK_CTL0_JOIN_EN_BOFFSET                1
+#define FRAME_ACK_CTL0_JOIN_EN_BLEN                   1
+#define FRAME_ACK_CTL0_JOIN_EN_FLAG                   HSL_RW
+
+#define IGMP_MLD_EN
+#define FRAME_ACK_CTL0_IGMP_MLD_EN_BOFFSET            0
+#define FRAME_ACK_CTL0_IGMP_MLD_EN_BLEN               1
+#define FRAME_ACK_CTL0_IGMP_MLD_EN_FLAG               HSL_RW
+
+
+
+
+    /* Frame Ack Ctl1 Register */
+#define FRAME_ACK_CTL1
+#define FRAME_ACK_CTL1_OFFSET    0x0214
+#define FRAME_ACK_CTL1_E_LENGTH  4
+#define FRAME_ACK_CTL1_E_OFFSET  0
+#define FRAME_ACK_CTL1_NR_E      1
+
+#define LLDP_EN
+#define FRAME_ACK_CTL1_LLDP_EN_BOFFSET               26
+#define FRAME_ACK_CTL1_LLDP_EN_BLEN                  1
+#define FRAME_ACK_CTL1_LLDP_EN_FLAG                  HSL_RW
+
+
+#define PPPOE_EN
+#define FRAME_ACK_CTL1_PPPOE_EN_BOFFSET               25
+#define FRAME_ACK_CTL1_PPPOE_EN_BLEN                  1
+#define FRAME_ACK_CTL1_PPPOE_EN_FLAG                  HSL_RW
+
+#define IGMP_V3_EN
+#define FRAME_ACK_CTL1_IGMP_V3_EN_BOFFSET             24
+#define FRAME_ACK_CTL1_IGMP_V3_EN_BLEN                1
+#define FRAME_ACK_CTL1_IGMP_V3_EN_FLAG                HSL_RW
+
+
+
+
+    /* Window Rule Ctl0 Register */
+#define WIN_RULE_CTL0
+#define WIN_RULE_CTL0_OFFSET               0x0218
+#define WIN_RULE_CTL0_E_LENGTH             4
+#define WIN_RULE_CTL0_E_OFFSET             0x4
+#define WIN_RULE_CTL0_NR_E                 7
+
+#define L4_LENGTH
+#define WIN_RULE_CTL0_L4_LENGTH_BOFFSET    24
+#define WIN_RULE_CTL0_L4_LENGTH_BLEN       4
+#define WIN_RULE_CTL0_L4_LENGTH_FLAG       HSL_RW
+
+#define L3_LENGTH
+#define WIN_RULE_CTL0_L3_LENGTH_BOFFSET    20
+#define WIN_RULE_CTL0_L3_LENGTH_BLEN       4
+#define WIN_RULE_CTL0_L3_LENGTH_FLAG       HSL_RW
+
+#define L2_LENGTH
+#define WIN_RULE_CTL0_L2_LENGTH_BOFFSET    16
+#define WIN_RULE_CTL0_L2_LENGTH_BLEN       4
+#define WIN_RULE_CTL0_L2_LENGTH_FLAG       HSL_RW
+
+#define L4_OFFSET
+#define WIN_RULE_CTL0_L4_OFFSET_BOFFSET    10
+#define WIN_RULE_CTL0_L4_OFFSET_BLEN       5
+#define WIN_RULE_CTL0_L4_OFFSET_FLAG       HSL_RW
+
+#define L3_OFFSET
+#define WIN_RULE_CTL0_L3_OFFSET_BOFFSET    5
+#define WIN_RULE_CTL0_L3_OFFSET_BLEN       5
+#define WIN_RULE_CTL0_L3_OFFSET_FLAG       HSL_RW
+
+#define L2_OFFSET
+#define WIN_RULE_CTL0_L2_OFFSET_BOFFSET    0
+#define WIN_RULE_CTL0_L2_OFFSET_BLEN       5
+#define WIN_RULE_CTL0_L2_OFFSET_FLAG       HSL_RW
+
+
+
+
+    /* Window Rule Ctl1 Register */
+#define WIN_RULE_CTL1
+#define WIN_RULE_CTL1_OFFSET               0x0234
+#define WIN_RULE_CTL1_E_LENGTH             4
+#define WIN_RULE_CTL1_E_OFFSET             0x4
+#define WIN_RULE_CTL1_NR_E                 7
+
+#define L3P_LENGTH
+#define WIN_RULE_CTL1_L3P_LENGTH_BOFFSET   20
+#define WIN_RULE_CTL1_L3P_LENGTH_BLEN      4
+#define WIN_RULE_CTL1_L3P_LENGTH_FLAG      HSL_RW
+
+#define L2S_LENGTH
+#define WIN_RULE_CTL1_L2S_LENGTH_BOFFSET   16
+#define WIN_RULE_CTL1_L2S_LENGTH_BLEN      4
+#define WIN_RULE_CTL1_L2S_LENGTH_FLAG      HSL_RW
+
+#define L3P_OFFSET
+#define WIN_RULE_CTL1_L3P_OFFSET_BOFFSET   5
+#define WIN_RULE_CTL1_L3P_OFFSET_BLEN      5
+#define WIN_RULE_CTL1_L3P_OFFSET_FLAG      HSL_RW
+
+#define L2S_OFFSET
+#define WIN_RULE_CTL1_L2S_OFFSET_BOFFSET   0
+#define WIN_RULE_CTL1_L2S_OFFSET_BLEN      5
+#define WIN_RULE_CTL1_L2S_OFFSET_FLAG      HSL_RW
+
+
+
+
+    /* Trunk Hash Mode Register */
+#define TRUNK_HASH_MODE
+#define TRUNK_HASH_MODE_OFFSET               0x0270
+#define TRUNK_HASH_MODE_E_LENGTH             4
+#define TRUNK_HASH_MODE_E_OFFSET             0x4
+#define TRUNK_HASH_MODE_NR_E                 1
+
+#define DIP_EN
+#define TRUNK_HASH_MODE_DIP_EN_BOFFSET       3
+#define TRUNK_HASH_MODE_DIP_EN_BLEN          1
+#define TRUNK_HASH_MODE_DIP_EN_FLAG          HSL_RW
+
+#define SIP_EN
+#define TRUNK_HASH_MODE_SIP_EN_BOFFSET       2
+#define TRUNK_HASH_MODE_SIP_EN_BLEN          1
+#define TRUNK_HASH_MODE_SIP_EN_FLAG          HSL_RW
+
+#define SA_EN
+#define TRUNK_HASH_MODE_SA_EN_BOFFSET        1
+#define TRUNK_HASH_MODE_SA_EN_BLEN           1
+#define TRUNK_HASH_MODE_SA_EN_FLAG           HSL_RW
+
+#define DA_EN
+#define TRUNK_HASH_MODE_DA_EN_BOFFSET        0
+#define TRUNK_HASH_MODE_DA_EN_BLEN           1
+#define TRUNK_HASH_MODE_DA_EN_FLAG           HSL_RW
+
+
+
+
+    /* Vlan Table Function0 Register */
+#define VLAN_TABLE_FUNC0
+#define VLAN_TABLE_FUNC0_OFFSET    0x0610
+#define VLAN_TABLE_FUNC0_E_LENGTH  4
+#define VLAN_TABLE_FUNC0_E_OFFSET  0
+#define VLAN_TABLE_FUNC0_NR_E      1
+
+#define VT_VALID
+#define VLAN_TABLE_FUNC0_VT_VALID_BOFFSET      20
+#define VLAN_TABLE_FUNC0_VT_VALID_BLEN         1
+#define VLAN_TABLE_FUNC0_VT_VALID_FLAG         HSL_RW
+
+#define IVL_EN
+#define VLAN_TABLE_FUNC0_IVL_EN_BOFFSET        19
+#define VLAN_TABLE_FUNC0_IVL_EN_BLEN           1
+#define VLAN_TABLE_FUNC0_IVL_EN_FLAG           HSL_RW
+
+#define LEARN_DIS
+#define VLAN_TABLE_FUNC0_LEARN_DIS_BOFFSET     18
+#define VLAN_TABLE_FUNC0_LEARN_DIS_BLEN        1
+#define VLAN_TABLE_FUNC0_LEARN_DIS_FLAG        HSL_RW
+
+#define VID_MEM
+#define VLAN_TABLE_FUNC0_VID_MEM_BOFFSET       4
+#define VLAN_TABLE_FUNC0_VID_MEM_BLEN          14
+#define VLAN_TABLE_FUNC0_VID_MEM_FLAG          HSL_RW
+
+#define VT_PRI_EN
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET     3
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN        1
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG        HSL_RW
+
+#define VT_PRI
+#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET        0
+#define VLAN_TABLE_FUNC0_VT_PRI_BLEN           3
+#define VLAN_TABLE_FUNC0_VT_PRI_FLAG           HSL_RW
+
+    /* Vlan Table Function1 Register */
+#define VLAN_TABLE_FUNC1
+#define VLAN_TABLE_FUNC1_OFFSET    0x0614
+#define VLAN_TABLE_FUNC1_E_LENGTH  4
+#define VLAN_TABLE_FUNC1_E_OFFSET  0
+#define VLAN_TABLE_FUNC1_NR_E      1
+
+#define VT_BUSY
+#define VLAN_TABLE_FUNC1_VT_BUSY_BOFFSET       31
+#define VLAN_TABLE_FUNC1_VT_BUSY_BLEN          1
+#define VLAN_TABLE_FUNC1_VT_BUSY_FLAG          HSL_RW
+
+#define VLAN_ID
+#define VLAN_TABLE_FUNC1_VLAN_ID_BOFFSET       16
+#define VLAN_TABLE_FUNC1_VLAN_ID_BLEN          12
+#define VLAN_TABLE_FUNC1_VLAN_ID_FLAG          HSL_RW
+
+#define VT_PORT_NUM
+#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BOFFSET   8
+#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BLEN      4
+#define VLAN_TABLE_FUNC1_VT_PORT_NUM_FLAG      HSL_RW
+
+#define VT_FULL_VIO
+#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BOFFSET   4
+#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BLEN      1
+#define VLAN_TABLE_FUNC1_VT_FULL_VIO_FLAG      HSL_RW
+
+#define VT_FUNC
+#define VLAN_TABLE_FUNC1_VT_FUNC_BOFFSET       0
+#define VLAN_TABLE_FUNC1_VT_FUNC_BLEN          3
+#define VLAN_TABLE_FUNC1_VT_FUNC_FLAG          HSL_RW
+
+
+
+
+    /* Address Table Function0 Register */
+#define ADDR_TABLE_FUNC0
+#define ADDR_TABLE_FUNC0_OFFSET    0x0600
+#define ADDR_TABLE_FUNC0_E_LENGTH  4
+#define ADDR_TABLE_FUNC0_E_OFFSET  0
+#define ADDR_TABLE_FUNC0_NR_E      1
+
+
+#define AT_ADDR_BYTE2
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BOFFSET 24
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE3
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BOFFSET 16
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE4
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE5
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 0
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG    HSL_RW
+
+    /* Address Table Function1 Register */
+#define ADDR_TABLE_FUNC1
+#define ADDR_TABLE_FUNC1_OFFSET    0x0604
+#define ADDR_TABLE_FUNC1_E_LENGTH  4
+#define ADDR_TABLE_FUNC1_E_OFFSET  0
+#define ADDR_TABLE_FUNC1_NR_E      1
+
+#define SA_DROP_EN
+#define ADDR_TABLE_FUNC1_SA_DROP_EN_BOFFSET    30
+#define ADDR_TABLE_FUNC1_SA_DROP_EN_BLEN       1
+#define ADDR_TABLE_FUNC1_SA_DROP_EN_FLAG       HSL_RW
+
+#define MIRROR_EN
+#define ADDR_TABLE_FUNC1_MIRROR_EN_BOFFSET     29
+#define ADDR_TABLE_FUNC1_MIRROR_EN_BLEN        1
+#define ADDR_TABLE_FUNC1_MIRROR_EN_FLAG        HSL_RW
+
+#define AT_PRI_EN
+#define ADDR_TABLE_FUNC1_AT_PRI_EN_BOFFSET     28
+#define ADDR_TABLE_FUNC1_AT_PRI_EN_BLEN        1
+#define ADDR_TABLE_FUNC1_AT_PRI_EN_FLAG        HSL_RW
+
+#define AT_SVL_EN
+#define ADDR_TABLE_FUNC1_AT_SVL_EN_BOFFSET     27
+#define ADDR_TABLE_FUNC1_AT_SVL_EN_BLEN        1
+#define ADDR_TABLE_FUNC1_AT_SVL_EN_FLAG        HSL_RW
+
+#define AT_PRI
+#define ADDR_TABLE_FUNC1_AT_PRI_BOFFSET        24
+#define ADDR_TABLE_FUNC1_AT_PRI_BLEN           3
+#define ADDR_TABLE_FUNC1_AT_PRI_FLAG           HSL_RW
+
+#define CROSS_PT
+#define ADDR_TABLE_FUNC1_CROSS_PT_BOFFSET      23
+#define ADDR_TABLE_FUNC1_CROSS_PT_BLEN         1
+#define ADDR_TABLE_FUNC1_CROSS_PT_FLAG         HSL_RW
+
+#define DES_PORT
+#define ADDR_TABLE_FUNC1_DES_PORT_BOFFSET      16
+#define ADDR_TABLE_FUNC1_DES_PORT_BLEN         7
+#define ADDR_TABLE_FUNC1_DES_PORT_FLAG         HSL_RW
+
+#define AT_ADDR_BYTE0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE1
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG    HSL_RW
+
+    /* Address Table Function2 Register */
+#define ADDR_TABLE_FUNC2
+#define ADDR_TABLE_FUNC2_OFFSET    0x0608
+#define ADDR_TABLE_FUNC2_E_LENGTH  4
+#define ADDR_TABLE_FUNC2_E_OFFSET  0
+#define ADDR_TABLE_FUNC2_NR_E      1
+
+
+#define LOAD_BALANCE_EN
+#define ADDR_TABLE_FUNC2_LOAD_BALANCE_EN_BOFFSET         23
+#define ADDR_TABLE_FUNC2_LOAD_BALANCE_EN_BLEN            1
+#define ADDR_TABLE_FUNC2_LOAD_BALANCE_EN_FLAG            HSL_RW
+
+#define LOAD_BALANCE
+#define ADDR_TABLE_FUNC2_LOAD_BALANCE_BOFFSET         21
+#define ADDR_TABLE_FUNC2_LOAD_BALANCE_BLEN            2
+#define ADDR_TABLE_FUNC2_LOAD_BALANCE_FLAG            HSL_RW
+
+#define WL_EN
+#define ADDR_TABLE_FUNC2_WL_EN_BOFFSET         20
+#define ADDR_TABLE_FUNC2_WL_EN_BLEN            1
+#define ADDR_TABLE_FUNC2_WL_EN_FLAG            HSL_RW
+
+#define AT_VID
+#define ADDR_TABLE_FUNC2_AT_VID_BOFFSET        8
+#define ADDR_TABLE_FUNC2_AT_VID_BLEN           12
+#define ADDR_TABLE_FUNC2_AT_VID_FLAG           HSL_RW
+
+#define SHORT_LOOP
+#define ADDR_TABLE_FUNC2_SHORT_LOOP_BOFFSET    7
+#define ADDR_TABLE_FUNC2_SHORT_LOOP_BLEN       1
+#define ADDR_TABLE_FUNC2_SHORT_LOOP_FLAG       HSL_RW
+
+#define COPY_TO_CPU
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET   6
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN      1
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG      HSL_RW
+
+#define REDRCT_TO_CPU
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 5
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN    1
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG    HSL_RW
+
+#define LEAKY_EN
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET      4
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN         1
+#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG         HSL_RW
+
+#define AT_STATUS
+#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET     0
+#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN        4
+#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG        HSL_RW
+
+    /* Address Table Function3 Register */
+#define ADDR_TABLE_FUNC3
+#define ADDR_TABLE_FUNC3_OFFSET    0x060c
+#define ADDR_TABLE_FUNC3_E_LENGTH  4
+#define ADDR_TABLE_FUNC3_E_OFFSET  0
+#define ADDR_TABLE_FUNC3_NR_E      1
+
+#define AT_BUSY
+#define ADDR_TABLE_FUNC3_AT_BUSY_BOFFSET       31
+#define ADDR_TABLE_FUNC3_AT_BUSY_BLEN          1
+#define ADDR_TABLE_FUNC3_AT_BUSY_FLAG          HSL_RW
+
+#define NEW_PORT_NUM
+#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BOFFSET  22
+#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BLEN     3
+#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_FLAG     HSL_RW
+
+#define AT_INDEX
+#define ADDR_TABLE_FUNC3_AT_INDEX_BOFFSET      16
+#define ADDR_TABLE_FUNC3_AT_INDEX_BLEN         5
+#define ADDR_TABLE_FUNC3_AT_INDEX_FLAG         HSL_RW
+
+#define AT_VID_EN
+#define ADDR_TABLE_FUNC3_AT_VID_EN_BOFFSET     15
+#define ADDR_TABLE_FUNC3_AT_VID_EN_BLEN        1
+#define ADDR_TABLE_FUNC3_AT_VID_EN_FLAG        HSL_RW
+
+#define AT_PORT_EN
+#define ADDR_TABLE_FUNC3_AT_PORT_EN_BOFFSET    14
+#define ADDR_TABLE_FUNC3_AT_PORT_EN_BLEN       1
+#define ADDR_TABLE_FUNC3_AT_PORT_EN_FLAG       HSL_RW
+
+#define AT_MULTI_EN
+#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BOFFSET   13
+#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BLEN      1
+#define ADDR_TABLE_FUNC3_AT_MULTI_EN_FLAG      HSL_RW
+
+#define AT_FULL_VIO
+#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BOFFSET   12
+#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BLEN      1
+#define ADDR_TABLE_FUNC3_AT_FULL_VIO_FLAG      HSL_RW
+
+#define AT_PORT_NUM
+#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BOFFSET   8
+#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BLEN      4
+#define ADDR_TABLE_FUNC3_AT_PORT_NUM_FLAG      HSL_RW
+
+#define FLUSH_ST_EN
+#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BOFFSET   4
+#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BLEN      1
+#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_FLAG      HSL_RW
+
+#define AT_FUNC
+#define ADDR_TABLE_FUNC3_AT_FUNC_BOFFSET       0
+#define ADDR_TABLE_FUNC3_AT_FUNC_BLEN          4
+#define ADDR_TABLE_FUNC3_AT_FUNC_FLAG          HSL_RW
+
+
+
+
+    /* Reserve Address Table0 Register */
+#define RESV_ADDR_TBL0
+#define RESV_ADDR_TBL0_OFFSET    0x3c000
+#define RESV_ADDR_TBL0_E_LENGTH  4
+#define RESV_ADDR_TBL0_E_OFFSET  0
+#define RESV_ADDR_TBL0_NR_E      1
+
+#define RESV_ADDR_BYTE2
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BOFFSET 24
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BLEN    8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_FLAG    HSL_RW
+
+#define RESV_ADDR_BYTE3
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BOFFSET 16
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BLEN    8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_FLAG    HSL_RW
+
+#define RESV_ADDR_BYTE4
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BOFFSET 8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BLEN    8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_FLAG    HSL_RW
+
+#define RESV_ADDR_BYTE5
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BOFFSET 0
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BLEN    8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_FLAG    HSL_RW
+
+    /* Reserve Address Table1 Register */
+#define RESV_ADDR_TBL1
+#define RESV_ADDR_TBL1_OFFSET    0x3c004
+#define RESV_ADDR_TBL1_E_LENGTH  4
+#define RESV_ADDR_TBL1_E_OFFSET  0
+#define RESV_ADDR_TBL1_NR_E      1
+
+#define RESV_COPY_TO_CPU
+#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BOFFSET   31
+#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BLEN      1
+#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_FLAG      HSL_RW
+
+#define RESV_REDRCT_TO_CPU
+#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BOFFSET 30
+#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BLEN    1
+#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_FLAG    HSL_RW
+
+#define RESV_LEAKY_EN
+#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BOFFSET      29
+#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BLEN         1
+#define RESV_ADDR_TBL1_RESV_LEAKY_EN_FLAG         HSL_RW
+
+#define RESV_MIRROR_EN
+#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BOFFSET     28
+#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BLEN        1
+#define RESV_ADDR_TBL1_RESV_MIRROR_EN_FLAG        HSL_RW
+
+#define RESV_PRI_EN
+#define RESV_ADDR_TBL1_RESV_PRI_EN_BOFFSET     27
+#define RESV_ADDR_TBL1_RESV_PRI_EN_BLEN        1
+#define RESV_ADDR_TBL1_RESV_PRI_EN_FLAG        HSL_RW
+
+#define RESV_PRI
+#define RESV_ADDR_TBL1_RESV_PRI_BOFFSET        24
+#define RESV_ADDR_TBL1_RESV_PRI_BLEN           3
+#define RESV_ADDR_TBL1_RESV_PRI_FLAG           HSL_RW
+
+#define RESV_CROSS_PT
+#define RESV_ADDR_TBL1_RESV_CROSS_PT_BOFFSET      23
+#define RESV_ADDR_TBL1_RESV_CROSS_PT_BLEN         1
+#define RESV_ADDR_TBL1_RESV_CROSS_PT_FLAG         HSL_RW
+
+#define RESV_DES_PORT
+#define RESV_ADDR_TBL1_RESV_DES_PORT_BOFFSET      16
+#define RESV_ADDR_TBL1_RESV_DES_PORT_BLEN         7
+#define RESV_ADDR_TBL1_RESV_DES_PORT_FLAG         HSL_RW
+
+#define RESV_ADDR_BYTE0
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BOFFSET 8
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BLEN    8
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_FLAG    HSL_RW
+
+#define RESV_ADDR_BYTE1
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BOFFSET 0
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BLEN    8
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_FLAG    HSL_RW
+
+    /* Reserve Address Table2 Register */
+#define RESV_ADDR_TBL2
+#define RESV_ADDR_TBL2_OFFSET    0x3c008
+#define RESV_ADDR_TBL2_E_LENGTH  4
+#define RESV_ADDR_TBL2_E_OFFSET  0
+#define RESV_ADDR_TBL2_NR_E      1
+
+#define RESV_STATUS
+#define RESV_ADDR_TBL2_RESV_STATUS_BOFFSET     0
+#define RESV_ADDR_TBL2_RESV_STATUS_BLEN        1
+#define RESV_ADDR_TBL2_RESV_STATUS_FLAG        HSL_RW
+
+
+
+
+    /* Address Table Control Register */
+#define ADDR_TABLE_CTL
+#define ADDR_TABLE_CTL_OFFSET     0x0618
+#define ADDR_TABLE_CTL_E_LENGTH   4
+#define ADDR_TABLE_CTL_E_OFFSET   0
+#define ADDR_TABLE_CTL_NR_E       1
+
+#define ARL_INI_EN
+#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET        31
+#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN           1
+#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG           HSL_RW
+
+#define LEARN_CHANGE_EN
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET   30
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN      1
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG      HSL_RW
+
+#define IGMP_JOIN_LEAKY
+#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BOFFSET   29
+#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BLEN      1
+#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_FLAG      HSL_RW
+
+#define IGMP_CREAT_EN
+#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BOFFSET     28
+#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BLEN        1
+#define ADDR_TABLE_CTL_IGMP_CREAT_EN_FLAG        HSL_RW
+
+#define IGMP_PRI_EN
+#define ADDR_TABLE_CTL_IGMP_PRI_EN_BOFFSET       27
+#define ADDR_TABLE_CTL_IGMP_PRI_EN_BLEN          1
+#define ADDR_TABLE_CTL_IGMP_PRI_EN_FLAG          HSL_RW
+
+#define IGMP_PRI
+#define ADDR_TABLE_CTL_IGMP_PRI_BOFFSET          24
+#define ADDR_TABLE_CTL_IGMP_PRI_BLEN             3
+#define ADDR_TABLE_CTL_IGMP_PRI_FLAG             HSL_RW
+
+#define IGMP_JOIN_STATIC
+#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BOFFSET  20
+#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BLEN     4
+#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_FLAG     HSL_RW
+
+#define AGE_EN
+#define ADDR_TABLE_CTL_AGE_EN_BOFFSET            19
+#define ADDR_TABLE_CTL_AGE_EN_BLEN               1
+#define ADDR_TABLE_CTL_AGE_EN_FLAG               HSL_RW
+
+#define LOOP_CHECK_TIMER
+#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BOFFSET  16
+#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BLEN     3
+#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_FLAG     HSL_RW
+
+#define AGE_TIME
+#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET          0
+#define ADDR_TABLE_CTL_AGE_TIME_BLEN             16
+#define ADDR_TABLE_CTL_AGE_TIME_FLAG             HSL_RW
+
+
+
+
+    /* Global Forward Control0 Register */
+#define FORWARD_CTL0
+#define FORWARD_CTL0_OFFSET             0x0620
+#define FORWARD_CTL0_E_LENGTH           4
+#define FORWARD_CTL0_E_OFFSET           0
+#define FORWARD_CTL0_NR_E               1
+
+#define ARP_CMD
+#define FORWARD_CTL0_ARP_CMD_BOFFSET                26
+#define FORWARD_CTL0_ARP_CMD_BLEN                   2
+#define FORWARD_CTL0_ARP_CMD_FLAG                   HSL_RW
+
+#define IP_NOT_FOUND
+#define FORWARD_CTL0_IP_NOT_FOUND_BOFFSET           24
+#define FORWARD_CTL0_IP_NOT_FOUND_BLEN              2
+#define FORWARD_CTL0_IP_NOT_FOUND_FLAG              HSL_RW
+
+#define ARP_NOT_FOUND
+#define FORWARD_CTL0_ARP_NOT_FOUND_BOFFSET          22
+#define FORWARD_CTL0_ARP_NOT_FOUND_BLEN             2
+#define FORWARD_CTL0_ARP_NOT_FOUND_FLAG             HSL_RW
+
+#define HASH_MODE
+#define FORWARD_CTL0_HASH_MODE_BOFFSET              20
+#define FORWARD_CTL0_HASH_MODE_BLEN                 2
+#define FORWARD_CTL0_HASH_MODE_FLAG                 HSL_RW
+
+#define NAT_NOT_FOUND_DROP
+#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BOFFSET     17
+#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BLEN        1
+#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_FLAG        HSL_RW
+
+#define SP_NOT_FOUND_DROP
+#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BOFFSET      16
+#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BLEN         1
+#define FORWARD_CTL0_SP_NOT_FOUND_DROP_FLAG         HSL_RW
+
+#define IGMP_LEAVE_DROP
+#define FORWARD_CTL0_IGMP_LEAVE_DROP_BOFFSET        14
+#define FORWARD_CTL0_IGMP_LEAVE_DROP_BLEN           1
+#define FORWARD_CTL0_IGMP_LEAVE_DROP_FLAG           HSL_RW
+
+#define ARL_UNI_LEAKY
+#define FORWARD_CTL0_ARL_UNI_LEAKY_BOFFSET          13
+#define FORWARD_CTL0_ARL_UNI_LEAKY_BLEN             1
+#define FORWARD_CTL0_ARL_UNI_LEAKY_FLAG             HSL_RW
+
+#define ARL_MUL_LEAKY
+#define FORWARD_CTL0_ARL_MUL_LEAKY_BOFFSET          12
+#define FORWARD_CTL0_ARL_MUL_LEAKY_BLEN             1
+#define FORWARD_CTL0_ARL_MUL_LEAKY_FLAG             HSL_RW
+
+#define MANAGE_VID_VIO_DROP_EN
+#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BOFFSET 11
+#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BLEN    1
+#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_FLAG    HSL_RW
+
+#define CPU_PORT_EN
+#define FORWARD_CTL0_CPU_PORT_EN_BOFFSET            10
+#define FORWARD_CTL0_CPU_PORT_EN_BLEN               1
+#define FORWARD_CTL0_CPU_PORT_EN_FLAG               HSL_RW
+
+#define PPPOE_RDT_EN
+#define FORWARD_CTL0_PPPOE_RDT_EN_BOFFSET           8
+#define FORWARD_CTL0_PPPOE_RDT_EN_BLEN              1
+#define FORWARD_CTL0_PPPOE_RDT_EN_FLAG              HSL_RW
+
+#define MIRROR_PORT_NUM
+#define FORWARD_CTL0_MIRROR_PORT_NUM_BOFFSET        4
+#define FORWARD_CTL0_MIRROR_PORT_NUM_BLEN           4
+#define FORWARD_CTL0_MIRROR_PORT_NUM_FLAG           HSL_RW
+
+#define IGMP_COPY_EN
+#define FORWARD_CTL0_IGMP_COPY_EN_BOFFSET           3
+#define FORWARD_CTL0_IGMP_COPY_EN_BLEN              1
+#define FORWARD_CTL0_IGMP_COPY_EN_FLAG              HSL_RW
+
+#define RIP_CPY_EN
+#define FORWARD_CTL0_RIP_CPY_EN_BOFFSET             2
+#define FORWARD_CTL0_RIP_CPY_EN_BLEN                1
+#define FORWARD_CTL0_RIP_CPY_EN_FLAG                HSL_RW
+
+#define EAPOL_CMD
+#define FORWARD_CTL0_EAPOL_CMD_BOFFSET              0
+#define FORWARD_CTL0_EAPOL_CMD_BLEN                 1
+#define FORWARD_CTL0_EAPOL_CMD_FLAG                 HSL_RW
+
+    /* Global Forward Control1 Register */
+#define FORWARD_CTL1
+#define FORWARD_CTL1_OFFSET             0x0624
+#define FORWARD_CTL1_E_LENGTH           4
+#define FORWARD_CTL1_E_OFFSET           0
+#define FORWARD_CTL1_NR_E               1
+
+#define IGMP_DP
+#define FORWARD_CTL1_IGMP_DP_BOFFSET          24
+#define FORWARD_CTL1_IGMP_DP_BLEN             7
+#define FORWARD_CTL1_IGMP_DP_FLAG             HSL_RW
+
+#define BC_FLOOD_DP
+#define FORWARD_CTL1_BC_FLOOD_DP_BOFFSET      16
+#define FORWARD_CTL1_BC_FLOOD_DP_BLEN         7
+#define FORWARD_CTL1_BC_FLOOD_DP_FLAG         HSL_RW
+
+#define MUL_FLOOD_DP
+#define FORWARD_CTL1_MUL_FLOOD_DP_BOFFSET     8
+#define FORWARD_CTL1_MUL_FLOOD_DP_BLEN        7
+#define FORWARD_CTL1_MUL_FLOOD_DP_FLAG        HSL_RW
+
+#define UNI_FLOOD_DP
+#define FORWARD_CTL1_UNI_FLOOD_DP_BOFFSET     0
+#define FORWARD_CTL1_UNI_FLOOD_DP_BLEN        7
+#define FORWARD_CTL1_UNI_FLOOD_DP_FLAG        HSL_RW
+
+
+
+
+    /* Global Learn Limit Ctl Register */
+#define GLOBAL_LEARN_LIMIT_CTL
+#define GLOBAL_LEARN_LIMIT_CTL_OFFSET            0x0628
+#define GLOBAL_LEARN_LIMIT_CTL_E_LENGTH          4
+#define GLOBAL_LEARN_LIMIT_CTL_E_OFFSET          0
+#define GLOBAL_LEARN_LIMIT_CTL_NR_E              1
+
+#define GOL_SA_LEARN_LIMIT_EN
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BOFFSET          12
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BLEN             1
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_FLAG             HSL_RW
+
+#define GOL_SA_LEARN_LIMIT_DROP_EN
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BOFFSET     13
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BLEN        1
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_FLAG        HSL_RW
+
+#define GOL_SA_LEARN_CNT
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BOFFSET               0
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BLEN                  12
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_FLAG                  HSL_RW
+
+
+
+
+    /* DSCP To Priority Register */
+#define DSCP_TO_PRI
+#define DSCP_TO_PRI_OFFSET     0x0630
+#define DSCP_TO_PRI_E_LENGTH   4
+#define DSCP_TO_PRI_E_OFFSET   0x0004
+#define DSCP_TO_PRI_NR_E       8
+
+
+
+
+    /* UP To Priority Register */
+#define UP_TO_PRI
+#define UP_TO_PRI_OFFSET     0x0650
+#define UP_TO_PRI_E_LENGTH   4
+#define UP_TO_PRI_E_OFFSET   0x0004
+#define UP_TO_PRI_NR_E       1
+
+
+
+
+    /* WAN DSCP To Priority Register */
+#define DSCP_TO_EHPRI
+#define DSCP_TO_EHPRI_OFFSET     0x0730
+#define DSCP_TO_EHPRI_E_LENGTH   4
+#define DSCP_TO_EHPRI_E_OFFSET   0x0004
+#define DSCP_TO_EHPRI_NR_E       8
+
+
+
+
+    /* WAN UP To Priority Register */
+#define UP_TO_EHPRI
+#define UP_TO_EHPRI_OFFSET     0x0750
+#define UP_TO_EHPRI_E_LENGTH   4
+#define UP_TO_EHPRI_E_OFFSET   0x0004
+#define UP_TO_EHPRI_NR_E       1
+
+
+
+
+    /* Port Lookup control Register */
+#define PORT_LOOKUP_CTL
+#define PORT_LOOKUP_CTL_OFFSET     0x0660
+#define PORT_LOOKUP_CTL_E_LENGTH   4
+#define PORT_LOOKUP_CTL_E_OFFSET   0x000c
+#define PORT_LOOKUP_CTL_NR_E       7
+
+#define MULTI_DROP_EN
+#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BOFFSET    31
+#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BLEN       1
+#define PORT_LOOKUP_CTL_MULTI_DROP_EN_FLAG       HSL_RW
+
+#define UNI_LEAKY_EN
+#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BOFFSET     28
+#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BLEN        1
+#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_FLAG        HSL_RW
+
+#define MUL_LEAKY_EN
+#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BOFFSET     27
+#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BLEN        1
+#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_FLAG        HSL_RW
+
+#define ARP_LEAKY_EN
+#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BOFFSET     26
+#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BLEN        1
+#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_FLAG        HSL_RW
+
+#define ING_MIRROR_EN
+#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BOFFSET    25
+#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BLEN       1
+#define PORT_LOOKUP_CTL_ING_MIRROR_EN_FLAG       HSL_RW
+
+#define PORT_LOOP_BACK
+#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BOFFSET   21
+#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BLEN      1
+#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_FLAG      HSL_RW
+
+#define LEARN_EN
+#define PORT_LOOKUP_CTL_LEARN_EN_BOFFSET         20
+#define PORT_LOOKUP_CTL_LEARN_EN_BLEN            1
+#define PORT_LOOKUP_CTL_LEARN_EN_FLAG            HSL_RW
+
+#define PORT_STATE
+#define PORT_LOOKUP_CTL_PORT_STATE_BOFFSET       16
+#define PORT_LOOKUP_CTL_PORT_STATE_BLEN          3
+#define PORT_LOOKUP_CTL_PORT_STATE_FLAG          HSL_RW
+
+#define FORCE_PVLAN
+#define PORT_LOOKUP_CTL_FORCE_PVLAN_BOFFSET      10
+#define PORT_LOOKUP_CTL_FORCE_PVLAN_BLEN         1
+#define PORT_LOOKUP_CTL_FORCE_PVLAN_FLAG         HSL_RW
+
+#define DOT1Q_MODE
+#define PORT_LOOKUP_CTL_DOT1Q_MODE_BOFFSET       8
+#define PORT_LOOKUP_CTL_DOT1Q_MODE_BLEN          2
+#define PORT_LOOKUP_CTL_DOT1Q_MODE_FLAG          HSL_RW
+
+#define PORT_VID_MEM
+#define PORT_LOOKUP_CTL_PORT_VID_MEM_BOFFSET     0
+#define PORT_LOOKUP_CTL_PORT_VID_MEM_BLEN        7
+#define PORT_LOOKUP_CTL_PORT_VID_MEM_FLAG        HSL_RW
+
+
+
+
+    /* Priority Control Register */
+#define PRI_CTL
+#define PRI_CTL_OFFSET            0x0664
+#define PRI_CTL_E_LENGTH          4
+#define PRI_CTL_E_OFFSET          0x000c
+#define PRI_CTL_NR_E              7
+
+#define EG_MAC_BASE_VLAN_EN
+#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BOFFSET     20
+#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BLEN        1
+#define PRI_CTL_EG_MAC_BASE_VLAN_EN_FLAG        HSL_RW
+
+#define FLOW_PRI_EN
+#define PRI_CTL_FLOW_PRI_EN_BOFFSET               19
+#define PRI_CTL_FLOW_PRI_EN_BLEN                  1
+#define PRI_CTL_FLOW_PRI_EN_FLAG                  HSL_RW
+
+#define DA_PRI_EN
+#define PRI_CTL_DA_PRI_EN_BOFFSET               18
+#define PRI_CTL_DA_PRI_EN_BLEN                  1
+#define PRI_CTL_DA_PRI_EN_FLAG                  HSL_RW
+
+#define VLAN_PRI_EN
+#define PRI_CTL_VLAN_PRI_EN_BOFFSET             17
+#define PRI_CTL_VLAN_PRI_EN_BLEN                1
+#define PRI_CTL_VLAN_PRI_EN_FLAG                HSL_RW
+
+#define IP_PRI_EN
+#define PRI_CTL_IP_PRI_EN_BOFFSET               16
+#define PRI_CTL_IP_PRI_EN_BLEN                  1
+#define PRI_CTL_IP_PRI_EN_FLAG                  HSL_RW
+
+#define FLOW_PRI_SEL
+#define PRI_CTL_FLOW_PRI_SEL_BOFFSET              8
+#define PRI_CTL_FLOW_PRI_SEL_BLEN                 2
+#define PRI_CTL_FLOW_PRI_SEL_FLAG                 HSL_RW
+
+#define DA_PRI_SEL
+#define PRI_CTL_DA_PRI_SEL_BOFFSET              6
+#define PRI_CTL_DA_PRI_SEL_BLEN                 2
+#define PRI_CTL_DA_PRI_SEL_FLAG                 HSL_RW
+
+#define VLAN_PRI_SEL
+#define PRI_CTL_VLAN_PRI_SEL_BOFFSET            4
+#define PRI_CTL_VLAN_PRI_SEL_BLEN               2
+#define PRI_CTL_VLAN_PRI_SEL_FLAG               HSL_RW
+
+#define IP_PRI_SEL
+#define PRI_CTL_IP_PRI_SEL_BOFFSET              2
+#define PRI_CTL_IP_PRI_SEL_BLEN                 2
+#define PRI_CTL_IP_PRI_SEL_FLAG                 HSL_RW
+
+
+
+    /* Port Learn Limit Ctl Register */
+#define PORT_LEARN_LIMIT_CTL
+#define PORT_LEARN_LIMIT_CTL_OFFSET            0x0668
+#define PORT_LEARN_LIMIT_CTL_E_LENGTH          4
+#define PORT_LEARN_LIMIT_CTL_E_OFFSET          0x000c
+#define PORT_LEARN_LIMIT_CTL_NR_E              7
+
+#define IGMP_JOIN_LIMIT_DROP_EN
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BOFFSET    29
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BLEN       1
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_FLAG       HSL_RW
+
+#define SA_LEARN_LIMIT_DROP_EN
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BOFFSET     28
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BLEN        1
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_FLAG        HSL_RW
+
+#define IGMP_JOIN_LIMIT_EN
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BOFFSET         27
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BLEN            1
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_FLAG            HSL_RW
+
+#define IGMP_JOIN_CNT
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BOFFSET              16
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BLEN                 11
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_FLAG                 HSL_RW
+
+#define SA_LEARN_STATUS
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BOFFSET            12
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BLEN               4
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_FLAG               HSL_RW
+
+#define SA_LEARN_LIMIT_EN
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BOFFSET          11
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BLEN             1
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_FLAG             HSL_RW
+
+#define SA_LEARN_CNT
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BOFFSET               0
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BLEN                  11
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_FLAG                  HSL_RW
+
+
+
+    /* Global Trunk Ctl0 Register */
+#define GOL_TRUNK_CTL0
+#define GOL_TRUNK_CTL0_OFFSET               0x0700
+#define GOL_TRUNK_CTL0_E_LENGTH             4
+#define GOL_TRUNK_CTL0_E_OFFSET             0x4
+#define GOL_TRUNK_CTL0_NR_E                 1
+
+
+    /* Global Trunk Ctl1 Register */
+#define GOL_TRUNK_CTL1
+#define GOL_TRUNK_CTL1_OFFSET               0x0704
+#define GOL_TRUNK_CTL1_E_LENGTH             4
+#define GOL_TRUNK_CTL1_E_OFFSET             0x4
+#define GOL_TRUNK_CTL1_NR_E                 2
+
+
+    /* ACL Forward source filter Register */
+#define ACL_FWD_SRC_FILTER_CTL0
+#define ACL_FWD_SRC_FILTER_CTL0_OFFSET               0x0710
+#define ACL_FWD_SRC_FILTER_CTL0_E_LENGTH             4
+#define ACL_FWD_SRC_FILTER_CTL0_E_OFFSET             0x4
+#define ACL_FWD_SRC_FILTER_CTL0_NR_E                 3
+
+
+    /* VLAN translation register */
+#define VLAN_TRANS
+#define VLAN_TRANS_OFFSET     0x0418
+#define VLAN_TRANS_E_LENGTH   4
+#define VLAN_TRANS_E_OFFSET   0
+#define VLAN_TRANS_NR_E       7
+
+#define EG_FLTR_BYPASS_EN
+#define VLAN_TRANS_EG_FLTR_BYPASS_EN_BOFFSET     1
+#define VLAN_TRANS_EG_FLTR_BYPASS_EN_BLEN        1
+#define VLAN_TRANS_EG_FLTR_BYPASS_EN_FLAG        HSL_RW
+
+#define NET_ISO
+#define VLAN_TRANS_NET_ISO_BOFFSET       0
+#define VLAN_TRANS_NET_ISO_BLEN          1
+#define VLAN_TRANS_NET_ISO_FLAG          HSL_RW
+
+
+    /* Port vlan0 Register */
+#define PORT_VLAN0
+#define PORT_VLAN0_OFFSET     0x0420
+#define PORT_VLAN0_E_LENGTH   4
+#define PORT_VLAN0_E_OFFSET   0x0008
+#define PORT_VLAN0_NR_E       7
+
+#define ING_CPRI
+#define PORT_VLAN0_ING_CPRI_BOFFSET       29
+#define PORT_VLAN0_ING_CPRI_BLEN          3
+#define PORT_VLAN0_ING_CPRI_FLAG          HSL_RW
+
+#define ING_FORCE_CPRI
+#define PORT_VLAN0_ING_FORCE_CPRI_BOFFSET       28
+#define PORT_VLAN0_ING_FORCE_CPRI_BLEN          1
+#define PORT_VLAN0_ING_FORCE_CPRI_FLAG          HSL_RW
+
+#define DEF_CVID
+#define PORT_VLAN0_DEF_CVID_BOFFSET       16
+#define PORT_VLAN0_DEF_CVID_BLEN          12
+#define PORT_VLAN0_DEF_CVID_FLAG          HSL_RW
+
+#define ING_SPRI
+#define PORT_VLAN0_ING_SPRI_BOFFSET       13
+#define PORT_VLAN0_ING_SPRI_BLEN          3
+#define PORT_VLAN0_ING_SPRI_FLAG          HSL_RW
+
+#define ING_FORCE_SPRI
+#define PORT_VLAN0_ING_FORCE_SPRI_BOFFSET       12
+#define PORT_VLAN0_ING_FORCE_SPRI_BLEN          1
+#define PORT_VLAN0_ING_FORCE_SPRI_FLAG          HSL_RW
+
+#define DEF_SVID
+#define PORT_VLAN0_DEF_SVID_BOFFSET       0
+#define PORT_VLAN0_DEF_SVID_BLEN          12
+#define PORT_VLAN0_DEF_SVID_FLAG          HSL_RW
+
+    /* Port vlan1 Register */
+#define PORT_VLAN1
+#define PORT_VLAN1_OFFSET     0x0424
+#define PORT_VLAN1_E_LENGTH   4
+#define PORT_VLAN1_E_OFFSET   0x0008
+#define PORT_VLAN1_NR_E       7
+
+#define VRF_ID
+#define PORT_VLAN1_VRF_ID_BOFFSET   15
+#define PORT_VLAN1_VRF_ID_BLEN      3
+#define PORT_VLAN1_VRF_ID_FLAG      HSL_RW
+
+#define EG_VLAN_MODE
+#define PORT_VLAN1_EG_VLAN_MODE_BOFFSET   12
+#define PORT_VLAN1_EG_VLAN_MODE_BLEN      2
+#define PORT_VLAN1_EG_VLAN_MODE_FLAG      HSL_RW
+
+#define VLAN_DIS
+#define PORT_VLAN1_VLAN_DIS_BOFFSET       11
+#define PORT_VLAN1_VLAN_DIS_BLEN          1
+#define PORT_VLAN1_VLAN_DIS_FLAG          HSL_RW
+
+#define SP_CHECK_EN
+#define PORT_VLAN1_SP_CHECK_EN_BOFFSET    10
+#define PORT_VLAN1_SP_CHECK_EN_BLEN       1
+#define PORT_VLAN1_SP_CHECK_EN_FLAG       HSL_RW
+
+#define COREP_EN
+#define PORT_VLAN1_COREP_EN_BOFFSET       9
+#define PORT_VLAN1_COREP_EN_BLEN          1
+#define PORT_VLAN1_COREP_EN_FLAG          HSL_RW
+
+#define FORCE_DEF_VID
+#define PORT_VLAN1_FORCE_DEF_VID_BOFFSET  8
+#define PORT_VLAN1_FORCE_DEF_VID_BLEN     1
+#define PORT_VLAN1_FORCE_DEF_VID_FLAG     HSL_RW
+
+#define TLS_EN
+#define PORT_VLAN1_TLS_EN_BOFFSET         7
+#define PORT_VLAN1_TLS_EN_BLEN            1
+#define PORT_VLAN1_TLS_EN_FLAG            HSL_RW
+
+#define PROPAGATION_EN
+#define PORT_VLAN1_PROPAGATION_EN_BOFFSET 6
+#define PORT_VLAN1_PROPAGATION_EN_BLEN    1
+#define PORT_VLAN1_PROPAGATION_EN_FLAG    HSL_RW
+
+#define CLONE
+#define PORT_VLAN1_CLONE_BOFFSET          5
+#define PORT_VLAN1_CLONE_BLEN             1
+#define PORT_VLAN1_CLONE_FLAG             HSL_RW
+
+#define PRI_PROPAGATION
+#define PORT_VLAN1_PRI_PROPAGATION_BOFFSET   4
+#define PORT_VLAN1_PRI_PROPAGATION_BLEN      1
+#define PORT_VLAN1_VLAN_PRI_PROPAGATION_FLAG HSL_RW
+
+#define IN_VLAN_MODE
+#define PORT_VLAN1_IN_VLAN_MODE_BOFFSET      2
+#define PORT_VLAN1_IN_VLAN_MODE_BLEN         2
+#define PORT_VLAN1_IN_VLAN_MODE_FLAG         HSL_RW
+
+
+    /* Route Default VID Register */
+#define ROUTER_DEFV
+#define ROUTER_DEFV_OFFSET     0x0c70
+#define ROUTER_DEFV_E_LENGTH   4
+#define ROUTER_DEFV_E_OFFSET   0x0004
+#define ROUTER_DEFV_NR_E       4
+
+
+    /* Route Egress VLAN Mode Register */
+#define ROUTER_EG
+#define ROUTER_EG_OFFSET     0x0c80
+#define ROUTER_EG_E_LENGTH   4
+#define ROUTER_EG_E_OFFSET   0x0004
+#define ROUTER_EG_NR_E       1
+
+/* port flow control threshold Register */
+#define PORT_FLOC_CTRL_THRESH
+#define PORT_FLOC_CTRL_THRESH_OFFSET	0x9b0
+#define PORT_FLOC_CTRL_THRESH_E_LENGTH   4
+#define PORT_FLOC_CTRL_THRESH_E_OFFSET   0x0004
+#define PORT_FLOC_CTRL_THRESH_NR_E       7
+
+
+    /* LED control Register */
+#define LED_CTRL               "ledctrl"
+#define LED_CTRL_ID            25
+#define LED_CTRL_OFFSET        0x0050
+#define LED_CTRL_E_LENGTH      4
+#define LED_CTRL_E_OFFSET      0
+#define LED_CTRL_NR_E          3
+
+#define PATTERN_EN                           "lctrl_pen"
+#define LED_CTRL_PATTERN_EN_BOFFSET          14
+#define LED_CTRL_PATTERN_EN_BLEN             2
+#define LED_CTRL_PATTERN_EN_FLAG             HSL_RW
+
+#define FULL_LIGHT_EN                        "lctrl_fen"
+#define LED_CTRL_FULL_LIGHT_EN_BOFFSET       13
+#define LED_CTRL_FULL_LIGHT_EN_BLEN          1
+#define LED_CTRL_FULL_LIGHT_EN_FLAG          HSL_RW
+
+#define HALF_LIGHT_EN                        "lctrl_hen"
+#define LED_CTRL_HALF_LIGHT_EN_BOFFSET       12
+#define LED_CTRL_HALF_LIGHT_EN_BLEN          1
+#define LED_CTRL_HALF_LIGHT_EN_FLAG          HSL_RW
+
+#define POWERON_LIGHT_EN                     "lctrl_poen"
+#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET    11
+#define LED_CTRL_POWERON_LIGHT_EN_BLEN       1
+#define LED_CTRL_POWERON_LIGHT_EN_FLAG       HSL_RW
+
+#define GE_LIGHT_EN                          "lctrl_geen"
+#define LED_CTRL_GE_LIGHT_EN_BOFFSET         10
+#define LED_CTRL_GE_LIGHT_EN_BLEN            1
+#define LED_CTRL_GE_LIGHT_EN_FLAG            HSL_RW
+
+#define FE_LIGHT_EN                          "lctrl_feen"
+#define LED_CTRL_FE_LIGHT_EN_BOFFSET         9
+#define LED_CTRL_FE_LIGHT_EN_BLEN            1
+#define LED_CTRL_FE_LIGHT_EN_FLAG            HSL_RW
+
+#define ETH_LIGHT_EN                         "lctrl_ethen"
+#define LED_CTRL_ETH_LIGHT_EN_BOFFSET        8
+#define LED_CTRL_ETH_LIGHT_EN_BLEN           1
+#define LED_CTRL_ETH_LIGHT_EN_FLAG           HSL_RW
+
+#define COL_BLINK_EN                         "lctrl_cen"
+#define LED_CTRL_COL_BLINK_EN_BOFFSET        7
+#define LED_CTRL_COL_BLINK_EN_BLEN           1
+#define LED_CTRL_COL_BLINK_EN_FLAG           HSL_RW
+
+#define RX_BLINK_EN                          "lctrl_rxen"
+#define LED_CTRL_RX_BLINK_EN_BOFFSET         5
+#define LED_CTRL_RX_BLINK_EN_BLEN            1
+#define LED_CTRL_RX_BLINK_EN_FLAG            HSL_RW
+
+#define TX_BLINK_EN                          "lctrl_txen"
+#define LED_CTRL_TX_BLINK_EN_BOFFSET         4
+#define LED_CTRL_TX_BLINK_EN_BLEN            1
+#define LED_CTRL_TX_BLINK_EN_FLAG            HSL_RW
+
+#define LINKUP_OVER_EN                       "lctrl_loen"
+#define LED_CTRL_LINKUP_OVER_EN_BOFFSET      2
+#define LED_CTRL_LINKUP_OVER_EN_BLEN         1
+#define LED_CTRL_LINKUP_OVER_EN_FLAG         HSL_RW
+
+#define BLINK_FREQ                           "lctrl_bfreq"
+#define LED_CTRL_BLINK_FREQ_BOFFSET          0
+#define LED_CTRL_BLINK_FREQ_BLEN             2
+#define LED_CTRL_BLINK_FREQ_FLAG             HSL_RW
+
+    /* LED control Register */
+#define LED_PATTERN               "ledpatten"
+#define LED_PATTERN_ID            25
+#define LED_PATTERN_OFFSET        0x005c
+#define LED_PATTERN_E_LENGTH      4
+#define LED_PATTERN_E_OFFSET      0
+#define LED_PATTERN_NR_E          1
+
+
+#define P3L2_MODE
+#define LED_PATTERN_P3L2_MODE_BOFFSET       24
+#define LED_PATTERN_P3L2_MODE_BLEN          2
+#define LED_PATTERN_P3L2_MODE_FLAG          HSL_RW
+
+#define P3L1_MODE
+#define LED_PATTERN_P3L1_MODE_BOFFSET       22
+#define LED_PATTERN_P3L1_MODE_BLEN          2
+#define LED_PATTERN_P3L1_MODE_FLAG          HSL_RW
+
+#define P3L0_MODE
+#define LED_PATTERN_P3L0_MODE_BOFFSET       20
+#define LED_PATTERN_P3L0_MODE_BLEN          2
+#define LED_PATTERN_P3L0_MODE_FLAG          HSL_RW
+
+#define P2L2_MODE
+#define LED_PATTERN_P2L2_MODE_BOFFSET       18
+#define LED_PATTERN_P2L2_MODE_BLEN          2
+#define LED_PATTERN_P2L2_MODE_FLAG          HSL_RW
+
+#define P2L1_MODE
+#define LED_PATTERN_P2L1_MODE_BOFFSET       16
+#define LED_PATTERN_P2L1_MODE_BLEN          2
+#define LED_PATTERN_P2L1_MODE_FLAG          HSL_RW
+
+#define P2L0_MODE
+#define LED_PATTERN_P2L0_MODE_BOFFSET       14
+#define LED_PATTERN_P2L0_MODE_BLEN          2
+#define LED_PATTERN_P2L0_MODE_FLAG          HSL_RW
+
+#define P1L2_MODE
+#define LED_PATTERN_P1L2_MODE_BOFFSET       12
+#define LED_PATTERN_P1L2_MODE_BLEN          2
+#define LED_PATTERN_P1L2_MODE_FLAG          HSL_RW
+
+#define P1L1_MODE
+#define LED_PATTERN_P1L1_MODE_BOFFSET       10
+#define LED_PATTERN_P1L1_MODE_BLEN          2
+#define LED_PATTERN_P1L1_MODE_FLAG          HSL_RW
+
+#define P1L0_MODE
+#define LED_PATTERN_P1L0_MODE_BOFFSET       8
+#define LED_PATTERN_P1L0_MODE_BLEN          2
+#define LED_PATTERN_P1L0_MODE_FLAG          HSL_RW
+
+
+
+
+    /* Pri To Queue Register */
+#define PRI_TO_QUEUE
+#define PRI_TO_QUEUE_OFFSET         0x0814
+#define PRI_TO_QUEUE_E_LENGTH       4
+#define PRI_TO_QUEUE_E_OFFSET       0x0004
+#define PRI_TO_QUEUE_NR_E           1
+
+
+
+
+    /* Pri To EhQueue Register */
+#define PRI_TO_EHQUEUE
+#define PRI_TO_EHQUEUE_OFFSET         0x0810
+#define PRI_TO_EHQUEUE_E_LENGTH       4
+#define PRI_TO_EHQUEUE_E_OFFSET       0x0004
+#define PRI_TO_EHQUEUE_NR_E           1
+
+
+
+
+    /*Global Flow Control Register*/
+#define QM_CTRL_REG
+#define QM_CTRL_REG_OFFSET       0X0808
+#define QM_CTRL_REG_E_LENGTH     4
+#define QM_CTRL_REG_E_OFFSET     0x0004
+#define QM_CTRL_REG_NR_E         1
+
+#define GOL_FLOW_EN
+#define QM_CTRL_REG_GOL_FLOW_EN_BOFFSET    16
+#define QM_CTRL_REG_GOL_FLOW_EN_BLEN       7
+#define QM_CTRL_REG_GOL_FLOW_EN_FLAG       HSL_RW
+
+#define QM_FUNC_TEST
+#define QM_CTRL_REG_QM_FUNC_TEST_BOFFSET   10
+#define QM_CTRL_REG_QM_FUNC_TEST_BLEN      1
+#define QM_CTRL_REG_QM_FUNC_TEST_FLAG      HSL_RW
+
+#define RATE_DROP_EN
+#define QM_CTRL_REG_RATE_DROP_EN_BOFFSET 7
+#define QM_CTRL_REG_RATE_DROP_EN_BLEN    1
+#define QM_CTRL_REG_RATE_DROP_EN_FLAG    HSL_RW
+
+#define FLOW_DROP_EN
+#define QM_CTRL_REG_FLOW_DROP_EN_BOFFSET 6
+#define QM_CTRL_REG_FLOW_DROP_EN_BLEN    1
+#define QM_CTRL_REG_FLOW_DROP_EN_FLAG    HSL_RW
+
+#define FLOW_DROP_CNT
+#define QM_CTRL_REG_FLOW_DROP_CNT_BOFFSET 0
+#define QM_CTRL_REG_FLOW_DROP_CNT_BLEN    6
+#define QM_CTRL_REG_FLOW_DROP_CNT_FLAG    HSL_RW
+
+
+
+
+    /* Port HOL CTL0 Register */
+#define PORT_HOL_CTL0
+#define PORT_HOL_CTL0_OFFSET         0x0970
+#define PORT_HOL_CTL0_E_LENGTH       4
+#define PORT_HOL_CTL0_E_OFFSET       0x0008
+#define PORT_HOL_CTL0_NR_E           7
+
+#define PORT_DESC_NR
+#define PORT_HOL_CTL0_PORT_DESC_NR_BOFFSET           24
+#define PORT_HOL_CTL0_PORT_DESC_NR_BLEN              6
+#define PORT_HOL_CTL0_PORT_DESC_NR_FLAG              HSL_RW
+
+#define QUEUE5_DESC_NR
+#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BOFFSET         20
+#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE5_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE4_DESC_NR
+#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BOFFSET         16
+#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE4_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE3_DESC_NR
+#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BOFFSET         12
+#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE3_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE2_DESC_NR
+#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BOFFSET         8
+#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE2_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE1_DESC_NR
+#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BOFFSET         4
+#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE1_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE0_DESC_NR
+#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BOFFSET         0
+#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE0_DESC_NR_FLAG            HSL_RW
+
+    /* Port HOL CTL1 Register */
+#define PORT_HOL_CTL1
+#define PORT_HOL_CTL1_OFFSET         0x0974
+#define PORT_HOL_CTL1_E_LENGTH       4
+#define PORT_HOL_CTL1_E_OFFSET       0x0008
+#define PORT_HOL_CTL1_NR_E           7
+
+#define EG_MIRROR_EN
+#define PORT_HOL_CTL1_EG_MIRROR_EN_BOFFSET           16
+#define PORT_HOL_CTL1_EG_MIRROR_EN_BLEN              1
+#define PORT_HOL_CTL1_EG_MIRROR_EN_FLAG              HSL_RW
+
+#define PORT_RED_EN
+#define PORT_HOL_CTL1_PORT_RED_EN_BOFFSET            8
+#define PORT_HOL_CTL1_PORT_RED_EN_BLEN               1
+#define PORT_HOL_CTL1_PORT_RED_EN_FLAG               HSL_RW
+
+#define PORT_DESC_EN
+#define PORT_HOL_CTL1_PORT_DESC_EN_BOFFSET           7
+#define PORT_HOL_CTL1_PORT_DESC_EN_BLEN              1
+#define PORT_HOL_CTL1_PORT_DESC_EN_FLAG              HSL_RW
+
+#define QUEUE_DESC_EN
+#define PORT_HOL_CTL1_QUEUE_DESC_EN_BOFFSET          6
+#define PORT_HOL_CTL1_QUEUE_DESC_EN_BLEN             1
+#define PORT_HOL_CTL1_QUEUE_DESC_EN_FLAG             HSL_RW
+
+#define PORT_IN_DESC_EN
+#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BOFFSET        0
+#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BLEN           4
+#define PORT_HOL_CTL1_PORT_IN_DESC_EN_FLAG           HSL_RW
+
+
+    /* PKT edit control register */
+#define PKT_CTRL
+#define PKT_CTRL_OFFSET     0x0c00
+#define PKT_CTRL_E_LENGTH   4
+#define PKT_CTRL_E_OFFSET   0
+#define PKT_CTRL_NR_E       7
+
+#define CPU_VID_EN
+#define PKT_CTRL_CPU_VID_EN_BOFFSET       1
+#define PKT_CTRL_CPU_VID_EN_BLEN          1
+#define PKT_CTRL_CPU_VID_EN_FLAG          HSL_RW
+
+
+#define RTD_PPPOE_EN
+#define PKT_CTRL_RTD_PPPOE_EN_BOFFSET       0
+#define PKT_CTRL_RTD_PPPOE_EN_BLEN          1
+#define PKT_CTRL_RTD_PPPOE_EN_FLAG          HSL_RW
+
+
+
+
+    /* mib memory info */
+#define MIB_RXBROAD
+#define MIB_RXBROAD_OFFSET                0x01000
+#define MIB_RXBROAD_E_LENGTH              4
+#define MIB_RXBROAD_E_OFFSET              0x100
+#define MIB_RXBROAD_NR_E                  7
+
+#define MIB_RXPAUSE
+#define MIB_RXPAUSE_OFFSET                0x01004
+#define MIB_RXPAUSE_E_LENGTH              4
+#define MIB_RXPAUSE_E_OFFSET              0x100
+#define MIB_RXPAUSE_NR_E                  7
+
+#define MIB_RXMULTI
+#define MIB_RXMULTI_OFFSET                0x01008
+#define MIB_RXMULTI_E_LENGTH              4
+#define MIB_RXMULTI_E_OFFSET              0x100
+#define MIB_RXMULTI_NR_E                  7
+
+#define MIB_RXFCSERR
+#define MIB_RXFCSERR_OFFSET               0x0100c
+#define MIB_RXFCSERR_E_LENGTH             4
+#define MIB_RXFCSERR_E_OFFSET             0x100
+#define MIB_RXFCSERR_NR_E                 7
+
+#define MIB_RXALLIGNERR
+#define MIB_RXALLIGNERR_OFFSET            0x01010
+#define MIB_RXALLIGNERR_E_LENGTH          4
+#define MIB_RXALLIGNERR_E_OFFSET          0x100
+#define MIB_RXALLIGNERR_NR_E              7
+
+#define MIB_RXRUNT
+#define MIB_RXRUNT_OFFSET                 0x01014
+#define MIB_RXRUNT_E_LENGTH               4
+#define MIB_RXRUNT_E_OFFSET               0x100
+#define MIB_RXRUNT_NR_E                   7
+
+#define MIB_RXFRAGMENT
+#define MIB_RXFRAGMENT_OFFSET             0x01018
+#define MIB_RXFRAGMENT_E_LENGTH           4
+#define MIB_RXFRAGMENT_E_OFFSET           0x100
+#define MIB_RXFRAGMENT_NR_E               7
+
+#define MIB_RX64BYTE
+#define MIB_RX64BYTE_OFFSET               0x0101c
+#define MIB_RX64BYTE_E_LENGTH             4
+#define MIB_RX64BYTE_E_OFFSET             0x100
+#define MIB_RX64BYTE_NR_E                 7
+
+#define MIB_RX128BYTE
+#define MIB_RX128BYTE_OFFSET              0x01020
+#define MIB_RX128BYTE_E_LENGTH            4
+#define MIB_RX128BYTE_E_OFFSET            0x100
+#define MIB_RX128BYTE_NR_E                7
+
+#define MIB_RX256BYTE
+#define MIB_RX256BYTE_OFFSET              0x01024
+#define MIB_RX256BYTE_E_LENGTH            4
+#define MIB_RX256BYTE_E_OFFSET            0x100
+#define MIB_RX256BYTE_NR_E                7
+
+#define MIB_RX512BYTE
+#define MIB_RX512BYTE_OFFSET              0x01028
+#define MIB_RX512BYTE_E_LENGTH            4
+#define MIB_RX512BYTE_E_OFFSET            0x100
+#define MIB_RX512BYTE_NR_E                7
+
+#define MIB_RX1024BYTE
+#define MIB_RX1024BYTE_OFFSET             0x0102c
+#define MIB_RX1024BYTE_E_LENGTH           4
+#define MIB_RX1024BYTE_E_OFFSET           0x100
+#define MIB_RX1024BYTE_NR_E               7
+
+#define MIB_RX1518BYTE
+#define MIB_RX1518BYTE_OFFSET             0x01030
+#define MIB_RX1518BYTE_E_LENGTH           4
+#define MIB_RX1518BYTE_E_OFFSET           0x100
+#define MIB_RX1518BYTE_NR_E               7
+
+#define MIB_RXMAXBYTE
+#define MIB_RXMAXBYTE_OFFSET              0x01034
+#define MIB_RXMAXBYTE_E_LENGTH            4
+#define MIB_RXMAXBYTE_E_OFFSET            0x100
+#define MIB_RXMAXBYTE_NR_E                7
+
+#define MIB_RXTOOLONG
+#define MIB_RXTOOLONG_OFFSET              0x01038
+#define MIB_RXTOOLONG_E_LENGTH            4
+#define MIB_RXTOOLONG_E_OFFSET            0x100
+#define MIB_RXTOOLONG_NR_E                7
+
+#define MIB_RXGOODBYTE_LO
+#define MIB_RXGOODBYTE_LO_OFFSET          0x0103c
+#define MIB_RXGOODBYTE_LO_E_LENGTH        4
+#define MIB_RXGOODBYTE_LO_E_OFFSET        0x100
+#define MIB_RXGOODBYTE_LO_NR_E            7
+
+#define MIB_RXGOODBYTE_HI
+#define MIB_RXGOODBYTE_HI_OFFSET          0x01040
+#define MIB_RXGOODBYTE_HI_E_LENGTH        4
+#define MIB_RXGOODBYTE_HI_E_OFFSET        0x100
+#define MIB_RXGOODBYTE_HI_NR_E            7
+
+#define MIB_RXBADBYTE_LO
+#define MIB_RXBADBYTE_LO_OFFSET           0x01044
+#define MIB_RXBADBYTE_LO_E_LENGTH         4
+#define MIB_RXBADBYTE_LO_E_OFFSET         0x100
+#define MIB_RXBADBYTE_LO_NR_E             7
+
+#define MIB_RXBADBYTE_HI
+#define MIB_RXBADBYTE_HI_OFFSET           0x01048
+#define MIB_RXBADBYTE_HI_E_LENGTH         4
+#define MIB_RXBADBYTE_HI_E_OFFSET         0x100
+#define MIB_RXBADBYTE_HI_NR_E             7
+
+#define MIB_RXOVERFLOW
+#define MIB_RXOVERFLOW_OFFSET             0x0104c
+#define MIB_RXOVERFLOW_E_LENGTH           4
+#define MIB_RXOVERFLOW_E_OFFSET           0x100
+#define MIB_RXOVERFLOW_NR_E               7
+
+#define MIB_FILTERED
+#define MIB_FILTERED_OFFSET               0x01050
+#define MIB_FILTERED_E_LENGTH             4
+#define MIB_FILTERED_E_OFFSET             0x100
+#define MIB_FILTERED_NR_E                 7
+
+#define MIB_TXBROAD
+#define MIB_TXBROAD_OFFSET                0x01054
+#define MIB_TXBROAD_E_LENGTH              4
+#define MIB_TXBROAD_E_OFFSET              0x100
+#define MIB_TXBROAD_NR_E                  7
+
+#define MIB_TXPAUSE
+#define MIB_TXPAUSE_OFFSET                0x01058
+#define MIB_TXPAUSE_E_LENGTH              4
+#define MIB_TXPAUSE_E_OFFSET              0x100
+#define MIB_TXPAUSE_NR_E                  7
+
+#define MIB_TXMULTI
+#define MIB_TXMULTI_OFFSET                0x0105c
+#define MIB_TXMULTI_E_LENGTH              4
+#define MIB_TXMULTI_E_OFFSET              0x100
+#define MIB_TXMULTI_NR_E                  7
+
+#define MIB_TXUNDERRUN
+#define MIB_TXUNDERRUN_OFFSET             0x01060
+#define MIB_TXUNDERRUN_E_LENGTH           4
+#define MIB_TXUNDERRUN_E_OFFSET           0x100
+#define MIB_TXUNDERRUN_NR_E               7
+
+#define MIB_TX64BYTE
+#define MIB_TX64BYTE_OFFSET               0x01064
+#define MIB_TX64BYTE_E_LENGTH             4
+#define MIB_TX64BYTE_E_OFFSET             0x100
+#define MIB_TX64BYTE_NR_E                 7
+
+#define MIB_TX128BYTE
+#define MIB_TX128BYTE_OFFSET              0x01068
+#define MIB_TX128BYTE_E_LENGTH            4
+#define MIB_TX128BYTE_E_OFFSET            0x100
+#define MIB_TX128BYTE_NR_E                7
+
+#define MIB_TX256BYTE
+#define MIB_TX256BYTE_OFFSET              0x0106c
+#define MIB_TX256BYTE_E_LENGTH            4
+#define MIB_TX256BYTE_E_OFFSET            0x100
+#define MIB_TX256BYTE_NR_E                7
+
+#define MIB_TX512BYTE
+#define MIB_TX512BYTE_OFFSET              0x01070
+#define MIB_TX512BYTE_E_LENGTH            4
+#define MIB_TX512BYTE_E_OFFSET            0x100
+#define MIB_TX512BYTE_NR_E                7
+
+#define MIB_TX1024BYTE
+#define MIB_TX1024BYTE_OFFSET             0x01074
+#define MIB_TX1024BYTE_E_LENGTH           4
+#define MIB_TX1024BYTE_E_OFFSET           0x100
+#define MIB_TX1024BYTE_NR_E               7
+
+#define MIB_TX1518BYTE
+#define MIB_TX1518BYTE_OFFSET             0x01078
+#define MIB_TX1518BYTE_E_LENGTH           4
+#define MIB_TX1518BYTE_E_OFFSET           0x100
+#define MIB_TX1518BYTE_NR_E               7
+
+#define MIB_TXMAXBYTE
+#define MIB_TXMAXBYTE_OFFSET              0x0107c
+#define MIB_TXMAXBYTE_E_LENGTH            4
+#define MIB_TXMAXBYTE_E_OFFSET            0x100
+#define MIB_TXMAXBYTE_NR_E                7
+
+#define MIB_TXOVERSIZE
+#define MIB_TXOVERSIZE_OFFSET             0x01080
+#define MIB_TXOVERSIZE_E_LENGTH           4
+#define MIB_TXOVERSIZE_E_OFFSET           0x100
+#define MIB_TXOVERSIZE_NR_E               7
+
+#define MIB_TXBYTE_LO
+#define MIB_TXBYTE_LO_OFFSET              0x01084
+#define MIB_TXBYTE_LO_E_LENGTH            4
+#define MIB_TXBYTE_LO_E_OFFSET            0x100
+#define MIB_TXBYTE_LO_NR_E                7
+
+#define MIB_TXBYTE_HI
+#define MIB_TXBYTE_HI_OFFSET              0x01088
+#define MIB_TXBYTE_HI_E_LENGTH            4
+#define MIB_TXBYTE_HI_E_OFFSET            0x100
+#define MIB_TXBYTE_HI_NR_E                7
+
+#define MIB_TXCOLLISION
+#define MIB_TXCOLLISION_OFFSET            0x0108c
+#define MIB_TXCOLLISION_E_LENGTH          4
+#define MIB_TXCOLLISION_E_OFFSET          0x100
+#define MIB_TXCOLLISION_NR_E              7
+
+#define MIB_TXABORTCOL
+#define MIB_TXABORTCOL_OFFSET             0x01090
+#define MIB_TXABORTCOL_E_LENGTH           4
+#define MIB_TXABORTCOL_E_OFFSET           0x100
+#define MIB_TXABORTCOL_NR_E               7
+
+#define MIB_TXMULTICOL
+#define MIB_TXMULTICOL_OFFSET             0x01094
+#define MIB_TXMULTICOL_E_LENGTH           4
+#define MIB_TXMULTICOL_E_OFFSET           0x100
+#define MIB_TXMULTICOL_NR_E               7
+
+#define MIB_TXSINGALCOL
+#define MIB_TXSINGALCOL_OFFSET            0x01098
+#define MIB_TXSINGALCOL_E_LENGTH          4
+#define MIB_TXSINGALCOL_E_OFFSET          0x100
+#define MIB_TXSINGALCOL_NR_E              7
+
+#define MIB_TXEXCDEFER
+#define MIB_TXEXCDEFER_OFFSET             0x0109c
+#define MIB_TXEXCDEFER_E_LENGTH           4
+#define MIB_TXEXCDEFER_E_OFFSET           0x100
+#define MIB_TXEXCDEFER_NR_E               7
+
+#define MIB_TXDEFER
+#define MIB_TXDEFER_OFFSET                0x010a0
+#define MIB_TXDEFER_E_LENGTH              4
+#define MIB_TXDEFER_E_OFFSET              0x100
+#define MIB_TXDEFER_NR_E                  7
+
+#define MIB_TXLATECOL
+#define MIB_TXLATECOL_OFFSET              0x010a4
+#define MIB_TXLATECOL_E_LENGTH            4
+#define MIB_TXLATECOL_E_OFFSET            0x100
+#define MIB_TXLATECOL_NR_E                7
+
+#define MIB_RXUNICAST
+#define MIB_RXUNICAST_OFFSET              0x010a8
+#define MIB_RXUNICAST_E_LENGTH            4
+#define MIB_RXUNICAST_E_OFFSET            0x100
+#define MIB_RXUNICAST_NR_E                7
+
+#define MIB_TXUNICAST
+#define MIB_TXUNICAST_OFFSET              0x010ac
+#define MIB_TXUNICAST_E_LENGTH            4
+#define MIB_TXUNICAST_E_OFFSET            0x100
+#define MIB_TXUNICAST_NR_E                7
+
+    /* ACL Action Register */
+#define ACL_RSLT0                         10
+#define ACL_RSLT0_OFFSET                  0x5a000
+#define ACL_RSLT0_E_LENGTH                4
+#define ACL_RSLT0_E_OFFSET                0x10
+#define ACL_RSLT0_NR_E                    96
+
+#define CTAGPRI
+#define ACL_RSLT0_CTAGPRI_BOFFSET         29
+#define ACL_RSLT0_CTAGPRI_BLEN            3
+#define ACL_RSLT0_CTAGPRI_FLAG            HSL_RW
+
+#define CTAGCFI
+#define ACL_RSLT0_CTAGCFI_BOFFSET         28
+#define ACL_RSLT0_CTAGCFI_BLEN            1
+#define ACL_RSLT0_CTAGCFI_FLAG            HSL_RW
+
+#define CTAGVID
+#define ACL_RSLT0_CTAGVID_BOFFSET         16
+#define ACL_RSLT0_CTAGVID_BLEN            12
+#define ACL_RSLT0_CTAGVID_FLAG            HSL_RW
+
+#define STAGPRI
+#define ACL_RSLT0_STAGPRI_BOFFSET         13
+#define ACL_RSLT0_STAGPRI_BLEN            3
+#define ACL_RSLT0_STAGPRI_FLAG            HSL_RW
+
+#define STAGDEI
+#define ACL_RSLT0_STAGDEI_BOFFSET         12
+#define ACL_RSLT0_STAGDEI_BLEN            1
+#define ACL_RSLT0_STAGDEI_FLAG            HSL_RW
+
+#define STAGVID
+#define ACL_RSLT0_STAGVID_BOFFSET         0
+#define ACL_RSLT0_STAGVID_BLEN            12
+#define ACL_RSLT0_STAGVID_FLAG            HSL_RW
+
+
+#define ACL_RSLT1                         11
+#define ACL_RSLT1_OFFSET                  0x5a004
+#define ACL_RSLT1_E_LENGTH                4
+#define ACL_RSLT1_E_OFFSET                0x10
+#define ACL_RSLT1_NR_E                    96
+
+#define DES_PORT0
+#define ACL_RSLT1_DES_PORT0_BOFFSET       29
+#define ACL_RSLT1_DES_PORT0_BLEN          3
+#define ACL_RSLT1_DES_PORT0_FLAG          HSL_RW
+
+#define PRI_QU_EN
+#define ACL_RSLT1_PRI_QU_EN_BOFFSET       28
+#define ACL_RSLT1_PRI_QU_EN_BLEN          1
+#define ACL_RSLT1_PRI_QU_EN_FLAG          HSL_RW
+
+#define PRI_QU
+#define ACL_RSLT1_PRI_QU_BOFFSET          25
+#define ACL_RSLT1_PRI_QU_BLEN             3
+#define ACL_RSLT1_PRI_QU_FLAG             HSL_RW
+
+#define WCMP_EN
+#define ACL_RSLT1_WCMP_EN_BOFFSET         24
+#define ACL_RSLT1_WCMP_EN_BLEN            1
+#define ACL_RSLT1_WCMP_EN_FLAG            HSL_RW
+
+#define ARP_PTR
+#define ACL_RSLT1_ARP_PTR_BOFFSET         17
+#define ACL_RSLT1_ARP_PTR_BLEN            7
+#define ACL_RSLT1_ARP_PTR_FLAG            HSL_RW
+
+#define ARP_PTR_EN
+#define ACL_RSLT1_ARP_PTR_EN_BOFFSET      16
+#define ACL_RSLT1_ARP_PTR_EN_BLEN         1
+#define ACL_RSLT1_ARP_PTR_EN_FLAG         HSL_RW
+
+#define FORCE_L3_MODE
+#define ACL_RSLT1_FORCE_L3_MODE_BOFFSET   14
+#define ACL_RSLT1_FORCE_L3_MODE_BLEN      2
+#define ACL_RSLT1_FORCE_L3_MODE_FLAG      HSL_RW
+
+#define LOOK_VID_CHG
+#define ACL_RSLT1_LOOK_VID_CHG_BOFFSET    13
+#define ACL_RSLT1_LOOK_VID_CHG_BLEN       1
+#define ACL_RSLT1_LOOK_VID_CHG_FLAG       HSL_RW
+
+#define TRANS_CVID_CHG
+#define ACL_RSLT1_TRANS_CVID_CHG_BOFFSET  12
+#define ACL_RSLT1_TRANS_CVID_CHG_BLEN     1
+#define ACL_RSLT1_TRANS_CVID_CHG_FLAG     HSL_RW
+
+#define TRANS_SVID_CHG
+#define ACL_RSLT1_TRANS_SVID_CHG_BOFFSET  11
+#define ACL_RSLT1_TRANS_SVID_CHG_BLEN     1
+#define ACL_RSLT1_TRANS_SVID_CHG_FLAG     HSL_RW
+
+#define CTAG_CFI_CHG
+#define ACL_RSLT1_CTAG_CFI_CHG_BOFFSET    10
+#define ACL_RSLT1_CTAG_CFI_CHG_BLEN       1
+#define ACL_RSLT1_CTAG_CFI_CHG_FLAG       HSL_RW
+
+#define CTAG_PRI_REMAP
+#define ACL_RSLT1_CTAG_PRI_REMAP_BOFFSET  9
+#define ACL_RSLT1_CTAG_PRI_REMAP_BLEN     1
+#define ACL_RSLT1_CTAG_PRI_REMAP_FLAG     HSL_RW
+
+#define STAG_DEI_CHG
+#define ACL_RSLT1_STAG_DEI_CHG_BOFFSET    8
+#define ACL_RSLT1_STAG_DEI_CHG_BLEN       1
+#define ACL_RSLT1_STAG_DEI_CHG_FLAG       HSL_RW
+
+#define STAG_PRI_REMAP
+#define ACL_RSLT1_STAG_PRI_REMAP_BOFFSET  7
+#define ACL_RSLT1_STAG_PRI_REMAP_BLEN     1
+#define ACL_RSLT1_STAG_PRI_REMAP_FLAG     HSL_RW
+
+#define DSCP_REMAP
+#define ACL_RSLT1_DSCP_REMAP_BOFFSET      6
+#define ACL_RSLT1_DSCP_REMAP_BLEN         1
+#define ACL_RSLT1_DSCP_REMAP_FLAG         HSL_RW
+
+#define DSCPV
+#define ACL_RSLT1_DSCPV_BOFFSET           0
+#define ACL_RSLT1_DSCPV_BLEN              6
+#define ACL_RSLT1_DSCPV_FLAG              HSL_RW
+
+#define ACL_RSLT2                         12
+#define ACL_RSLT2_OFFSET                  0x5a008
+#define ACL_RSLT2_E_LENGTH                4
+#define ACL_RSLT2_E_OFFSET                0x10
+#define ACL_RSLT2_NR_E                    96
+
+#define TRIGGER_INTR
+#define ACL_RSLT2_TRIGGER_INTR_BOFFSET    16
+#define ACL_RSLT2_TRIGGER_INTR_BLEN       1
+#define ACL_RSLT2_TRIGGER_INTR_FLAG       HSL_RW
+
+#define EG_BYPASS
+#define ACL_RSLT2_EG_BYPASS_BOFFSET       15
+#define ACL_RSLT2_EG_BYPASS_BLEN          1
+#define ACL_RSLT2_EG_BYPASS_FLAG          HSL_RW
+
+#define POLICER_EN
+#define ACL_RSLT2_POLICER_EN_BOFFSET      14
+#define ACL_RSLT2_POLICER_EN_BLEN         1
+#define ACL_RSLT2_POLICER_EN_FLAG         HSL_RW
+
+#define POLICER_PTR
+#define ACL_RSLT2_POLICER_PTR_BOFFSET     9
+#define ACL_RSLT2_POLICER_PTR_BLEN        5
+#define ACL_RSLT2_POLICER_PTR_FLAG        HSL_RW
+
+#define FWD_CMD
+#define ACL_RSLT2_FWD_CMD_BOFFSET         6
+#define ACL_RSLT2_FWD_CMD_BLEN            3
+#define ACL_RSLT2_FWD_CMD_FLAG            HSL_RW
+
+#define MIRR_EN
+#define ACL_RSLT2_MIRR_EN_BOFFSET         5
+#define ACL_RSLT2_MIRR_EN_BLEN            1
+#define ACL_RSLT2_MIRR_EN_FLAG            HSL_RW
+
+#define DES_PORT_EN
+#define ACL_RSLT2_DES_PORT_EN_BOFFSET     4
+#define ACL_RSLT2_DES_PORT_EN_BLEN        1
+#define ACL_RSLT2_DES_PORT_EN_FLAG        HSL_RW
+
+#define DES_PORT1
+#define ACL_RSLT2_DES_PORT1_BOFFSET       0
+#define ACL_RSLT2_DES_PORT1_BLEN          4
+#define ACL_RSLT2_DES_PORT1_FLAG          HSL_RW
+
+
+
+
+    /* MAC Type Rule Field Define */
+#define MAC_RUL_V0                         0
+#define MAC_RUL_V0_OFFSET                  0x58000
+#define MAC_RUL_V0_E_LENGTH                4
+#define MAC_RUL_V0_E_OFFSET                0x20
+#define MAC_RUL_V0_NR_E                    96
+
+#define DAV_BYTE2
+#define MAC_RUL_V0_DAV_BYTE2_BOFFSET       24
+#define MAC_RUL_V0_DAV_BYTE2_BLEN          8
+#define MAC_RUL_V0_DAV_BYTE2_FLAG          HSL_RW
+
+#define DAV_BYTE3
+#define MAC_RUL_V0_DAV_BYTE3_BOFFSET       16
+#define MAC_RUL_V0_DAV_BYTE3_BLEN          8
+#define MAC_RUL_V0_DAV_BYTE3_FLAG          HSL_RW
+
+#define DAV_BYTE4
+#define MAC_RUL_V0_DAV_BYTE4_BOFFSET       8
+#define MAC_RUL_V0_DAV_BYTE4_BLEN          8
+#define MAC_RUL_V0_DAV_BYTE4_FLAG          HSL_RW
+
+#define DAV_BYTE5
+#define MAC_RUL_V0_DAV_BYTE5_BOFFSET       0
+#define MAC_RUL_V0_DAV_BYTE5_BLEN          8
+#define MAC_RUL_V0_DAV_BYTE5_FLAG          HSL_RW
+
+
+#define MAC_RUL_V1                         1
+#define MAC_RUL_V1_OFFSET                  0x58004
+#define MAC_RUL_V1_E_LENGTH                4
+#define MAC_RUL_V1_E_OFFSET                0x20
+#define MAC_RUL_V1_NR_E                    96
+
+#define SAV_BYTE4
+#define MAC_RUL_V1_SAV_BYTE4_BOFFSET       24
+#define MAC_RUL_V1_SAV_BYTE4_BLEN          8
+#define MAC_RUL_V1_SAV_BYTE4_FLAG          HSL_RW
+
+#define SAV_BYTE5
+#define MAC_RUL_V1_SAV_BYTE5_BOFFSET       16
+#define MAC_RUL_V1_SAV_BYTE5_BLEN          8
+#define MAC_RUL_V1_SAV_BYTE5_FLAG          HSL_RW
+
+#define DAV_BYTE0
+#define MAC_RUL_V1_DAV_BYTE0_BOFFSET       8
+#define MAC_RUL_V1_DAV_BYTE0_BLEN          8
+#define MAC_RUL_V1_DAV_BYTE0_FLAG          HSL_RW
+
+#define DAV_BYTE1
+#define MAC_RUL_V1_DAV_BYTE1_BOFFSET       0
+#define MAC_RUL_V1_DAV_BYTE1_BLEN          8
+#define MAC_RUL_V1_DAV_BYTE1_FLAG          HSL_RW
+
+
+#define MAC_RUL_V2                         2
+#define MAC_RUL_V2_OFFSET                  0x58008
+#define MAC_RUL_V2_E_LENGTH                4
+#define MAC_RUL_V2_E_OFFSET                0x20
+#define MAC_RUL_V2_NR_E                    96
+
+#define SAV_BYTE0
+#define MAC_RUL_V2_SAV_BYTE0_BOFFSET       24
+#define MAC_RUL_V2_SAV_BYTE0_BLEN          8
+#define MAC_RUL_V2_SAV_BYTE0_FLAG          HSL_RW
+
+#define SAV_BYTE1
+#define MAC_RUL_V2_SAV_BYTE1_BOFFSET       16
+#define MAC_RUL_V2_SAV_BYTE1_BLEN          8
+#define MAC_RUL_V2_SAV_BYTE1_FLAG          HSL_RW
+
+#define SAV_BYTE2
+#define MAC_RUL_V2_SAV_BYTE2_BOFFSET       8
+#define MAC_RUL_V2_SAV_BYTE2_BLEN          8
+#define MAC_RUL_V2_SAV_BYTE2_FLAG          HSL_RW
+
+#define SAV_BYTE3
+#define MAC_RUL_V2_SAV_BYTE3_BOFFSET       0
+#define MAC_RUL_V2_SAV_BYTE3_BLEN          8
+#define MAC_RUL_V2_SAV_BYTE3_FLAG          HSL_RW
+
+
+#define MAC_RUL_V3                         3
+#define MAC_RUL_V3_ID                      13
+#define MAC_RUL_V3_OFFSET                  0x5800c
+#define MAC_RUL_V3_E_LENGTH                4
+#define MAC_RUL_V3_E_OFFSET                0x20
+#define MAC_RUL_V3_NR_E                    96
+
+#define ETHTYPV
+#define MAC_RUL_V3_ETHTYPV_BOFFSET         16
+#define MAC_RUL_V3_ETHTYPV_BLEN            16
+#define MAC_RUL_V3_ETHTYPV_FLAG            HSL_RW
+
+#define VLANPRIV
+#define MAC_RUL_V3_VLANPRIV_BOFFSET        13
+#define MAC_RUL_V3_VLANPRIV_BLEN           3
+#define MAC_RUL_V3_VLANPRIV_FLAG           HSL_RW
+
+#define VLANCFIV
+#define MAC_RUL_V3_VLANCFIV_BOFFSET        12
+#define MAC_RUL_V3_VLANCFIV_BLEN           1
+#define MAC_RUL_V3_VLANCFIV_FLAG           HSL_RW
+
+#define VLANIDV
+#define MAC_RUL_V3_VLANIDV_BOFFSET         0
+#define MAC_RUL_V3_VLANIDV_BLEN            12
+#define MAC_RUL_V3_VLANIDV_FLAG            HSL_RW
+
+
+#define MAC_RUL_V4                         4
+#define MAC_RUL_V4_OFFSET                  0x58010
+#define MAC_RUL_V4_E_LENGTH                4
+#define MAC_RUL_V4_E_OFFSET                0x20
+#define MAC_RUL_V4_NR_E                    96
+
+#define RULE_INV
+#define MAC_RUL_V4_RULE_INV_BOFFSET        7
+#define MAC_RUL_V4_RULE_INV_BLEN           1
+#define MAC_RUL_V4_RULE_INV_FLAG           HSL_RW
+
+#define SRC_PT
+#define MAC_RUL_V4_SRC_PT_BOFFSET          0
+#define MAC_RUL_V4_SRC_PT_BLEN             7
+#define MAC_RUL_V4_SRC_PT_FLAG             HSL_RW
+
+
+#define MAC_RUL_M0                         5
+#define MAC_RUL_M0_OFFSET                  0x59000
+#define MAC_RUL_M0_E_LENGTH                4
+#define MAC_RUL_M0_E_OFFSET                0x20
+#define MAC_RUL_M0_NR_E                    96
+
+#define DAM_BYTE2
+#define MAC_RUL_M0_DAM_BYTE2_BOFFSET       24
+#define MAC_RUL_M0_DAM_BYTE2_BLEN          8
+#define MAC_RUL_M0_DAM_BYTE2_FLAG          HSL_RW
+
+#define DAM_BYTE3
+#define MAC_RUL_M0_DAM_BYTE3_BOFFSET       16
+#define MAC_RUL_M0_DAM_BYTE3_BLEN          8
+#define MAC_RUL_M0_DAM_BYTE3_FLAG          HSL_RW
+
+#define DAM_BYTE4
+#define MAC_RUL_M0_DAM_BYTE4_BOFFSET       8
+#define MAC_RUL_M0_DAM_BYTE4_BLEN          8
+#define MAC_RUL_M0_DAM_BYTE4_FLAG          HSL_RW
+
+#define DAM_BYTE5
+#define MAC_RUL_M0_DAM_BYTE5_BOFFSET       0
+#define MAC_RUL_M0_DAM_BYTE5_BLEN          8
+#define MAC_RUL_M0_DAM_BYTE5_FLAG          HSL_RW
+
+
+#define MAC_RUL_M1                         6
+#define MAC_RUL_M1_OFFSET                  0x59004
+#define MAC_RUL_M1_E_LENGTH                4
+#define MAC_RUL_M1_E_OFFSET                0x20
+#define MAC_RUL_M1_NR_E                    96
+
+#define SAM_BYTE4
+#define MAC_RUL_M1_SAM_BYTE4_BOFFSET       24
+#define MAC_RUL_M1_SAM_BYTE4_BLEN          8
+#define MAC_RUL_M1_SAM_BYTE4_FLAG          HSL_RW
+
+#define SAM_BYTE5
+#define MAC_RUL_M1_SAM_BYTE5_BOFFSET       16
+#define MAC_RUL_M1_SAM_BYTE5_BLEN          8
+#define MAC_RUL_M1_SAM_BYTE5_FLAG          HSL_RW
+
+#define DAM_BYTE0
+#define MAC_RUL_M1_DAM_BYTE0_BOFFSET       8
+#define MAC_RUL_M1_DAM_BYTE0_BLEN          8
+#define MAC_RUL_M1_DAM_BYTE0_FLAG          HSL_RW
+
+#define DAM_BYTE1
+#define MAC_RUL_M1_DAM_BYTE1_BOFFSET       0
+#define MAC_RUL_M1_DAM_BYTE1_BLEN          8
+#define MAC_RUL_M1_DAM_BYTE1_FLAG          HSL_RW
+
+
+#define MAC_RUL_M2                         7
+#define MAC_RUL_M2_OFFSET                  0x59008
+#define MAC_RUL_M2_E_LENGTH                4
+#define MAC_RUL_M2_E_OFFSET                0x20
+#define MAC_RUL_M2_NR_E                    96
+
+#define SAM_BYTE0
+#define MAC_RUL_M2_SAM_BYTE0_BOFFSET       24
+#define MAC_RUL_M2_SAM_BYTE0_BLEN          8
+#define MAC_RUL_M2_SAM_BYTE0_FLAG          HSL_RW
+
+#define SAM_BYTE1
+#define MAC_RUL_M2_SAM_BYTE1_BOFFSET       16
+#define MAC_RUL_M2_SAM_BYTE1_BLEN          8
+#define MAC_RUL_M2_SAM_BYTE1_FLAG          HSL_RW
+
+#define SAM_BYTE2
+#define MAC_RUL_M2_SAM_BYTE2_BOFFSET       8
+#define MAC_RUL_M2_SAM_BYTE2_BLEN          8
+#define MAC_RUL_M2_SAM_BYTE2_FLAG          HSL_RW
+
+#define SAM_BYTE3
+#define MAC_RUL_M2_SAM_BYTE3_BOFFSET       0
+#define MAC_RUL_M2_SAM_BYTE3_BLEN          8
+#define MAC_RUL_M2_SAM_BYTE3_FLAG          HSL_RW
+
+
+#define MAC_RUL_M3                         8
+#define MAC_RUL_M3_OFFSET                  0x5900c
+#define MAC_RUL_M3_E_LENGTH                4
+#define MAC_RUL_M3_E_OFFSET                0x20
+#define MAC_RUL_M3_NR_E                    96
+
+#define ETHTYPM
+#define MAC_RUL_M3_ETHTYPM_BOFFSET         16
+#define MAC_RUL_M3_ETHTYPM_BLEN            16
+#define MAC_RUL_M3_ETHTYPM_FLAG            HSL_RW
+
+#define VLANPRIM
+#define MAC_RUL_M3_VLANPRIM_BOFFSET        13
+#define MAC_RUL_M3_VLANPRIM_BLEN           3
+#define MAC_RUL_M3_VLANPRIM_FLAG           HSL_RW
+
+#define VLANCFIM
+#define MAC_RUL_M3_VLANCFIM_BOFFSET        12
+#define MAC_RUL_M3_VLANCFIM_BLEN           1
+#define MAC_RUL_M3_VLANCFIM_FLAG           HSL_RW
+
+#define VLANIDM
+#define MAC_RUL_M3_VLANIDM_BOFFSET         0
+#define MAC_RUL_M3_VLANIDM_BLEN            12
+#define MAC_RUL_M3_VLANIDM_FLAG            HSL_RW
+
+
+#define MAC_RUL_M4                         9
+#define MAC_RUL_M4_OFFSET                  0x59010
+#define MAC_RUL_M4_E_LENGTH                4
+#define MAC_RUL_M4_E_OFFSET                0x20
+#define MAC_RUL_M4_NR_E                    96
+
+#define RULE_VALID
+#define MAC_RUL_M4_RULE_VALID_BOFFSET      6
+#define MAC_RUL_M4_RULE_VALID_BLEN         2
+#define MAC_RUL_M4_RULE_VALID_FLAG         HSL_RW
+
+#define TAGGEDM
+#define MAC_RUL_M4_TAGGEDM_BOFFSET         5
+#define MAC_RUL_M4_TAGGEDM_BLEN            1
+#define MAC_RUL_M4_TAGGEDM_FLAG            HSL_RW
+
+#define TAGGEDV
+#define MAC_RUL_M4_TAGGEDV_BOFFSET         4
+#define MAC_RUL_M4_TAGGEDV_BLEN            1
+#define MAC_RUL_M4_TAGGEDV_FLAG            HSL_RW
+
+#define VIDMSK
+#define MAC_RUL_M4_VIDMSK_BOFFSET          3
+#define MAC_RUL_M4_VIDMSK_BLEN             1
+#define MAC_RUL_M4_VIDMSK_FLAG             HSL_RW
+
+#define RULE_TYP
+#define MAC_RUL_M4_RULE_TYP_BOFFSET        0
+#define MAC_RUL_M4_RULE_TYP_BLEN           3
+#define MAC_RUL_M4_RULE_TYP_FLAG           HSL_RW
+
+
+
+
+    /* IP4 Type Rule Field Define */
+#define IP4_RUL_V0                         0
+#define IP4_RUL_V0_OFFSET                  0x58000
+#define IP4_RUL_V0_E_LENGTH                4
+#define IP4_RUL_V0_E_OFFSET                0x20
+#define IP4_RUL_V0_NR_E                    96
+
+#define DIPV
+#define IP4_RUL_V0_DIPV_BOFFSET            0
+#define IP4_RUL_V0_DIPV_BLEN               32
+#define IP4_RUL_V0_DIPV_FLAG               HSL_RW
+
+
+#define IP4_RUL_V1                         1
+#define IP4_RUL_V1_OFFSET                  0x58004
+#define IP4_RUL_V1_E_LENGTH                4
+#define IP4_RUL_V1_E_OFFSET                0x20
+#define IP4_RUL_V1_NR_E                    96
+
+#define SIPV
+#define IP4_RUL_V1_SIPV_BOFFSET            0
+#define IP4_RUL_V1_SIPV_BLEN               32
+#define IP4_RUL_V1_SIPV_FLAG               HSL_RW
+
+
+#define IP4_RUL_V2                         2
+#define IP4_RUL_V2_OFFSET                  0x58008
+#define IP4_RUL_V2_E_LENGTH                4
+#define IP4_RUL_V2_E_OFFSET                0x20
+#define IP4_RUL_V2_NR_E                    96
+
+#define IP4PROTV
+#define IP4_RUL_V2_IP4PROTV_BOFFSET        0
+#define IP4_RUL_V2_IP4PROTV_BLEN           8
+#define IP4_RUL_V2_IP4PROTV_FLAG           HSL_RW
+
+#define IP4DSCPV
+#define IP4_RUL_V2_IP4DSCPV_BOFFSET        8
+#define IP4_RUL_V2_IP4DSCPV_BLEN           8
+#define IP4_RUL_V2_IP4DSCPV_FLAG           HSL_RW
+
+#define IP4DPORTV
+#define IP4_RUL_V2_IP4DPORTV_BOFFSET       16
+#define IP4_RUL_V2_IP4DPORTV_BLEN          16
+#define IP4_RUL_V2_IP4DPORTV_FLAG          HSL_RW
+
+
+#define IP4_RUL_V3                         3
+#define IP4_RUL_V3_OFFSET                  0x5800c
+#define IP4_RUL_V3_E_LENGTH                4
+#define IP4_RUL_V3_E_OFFSET                0x20
+#define IP4_RUL_V3_NR_E                    96
+
+#define IP4TCPFLAGV
+#define IP4_RUL_V3_IP4TCPFLAGV_BOFFSET     24
+#define IP4_RUL_V3_IP4TCPFLAGV_BLEN        6
+#define IP4_RUL_V3_IP4TCPFLAGV_FLAG        HSL_RW
+
+#define IP4DHCPV
+#define IP4_RUL_V3_IP4DHCPV_BOFFSET        22
+#define IP4_RUL_V3_IP4DHCPV_BLEN           1
+#define IP4_RUL_V3_IP4DHCPV_FLAG           HSL_RW
+
+#define IP4RIPV
+#define IP4_RUL_V3_IP4RIPV_BOFFSET         21
+#define IP4_RUL_V3_IP4RIPV_BLEN            1
+#define IP4_RUL_V3_IP4RIPV_FLAG            HSL_RW
+
+#define ICMP_EN
+#define IP4_RUL_V3_ICMP_EN_BOFFSET         20
+#define IP4_RUL_V3_ICMP_EN_BLEN            1
+#define IP4_RUL_V3_ICMP_EN_FLAG            HSL_RW
+
+#define IP4SPORTV
+#define IP4_RUL_V3_IP4SPORTV_BOFFSET       0
+#define IP4_RUL_V3_IP4SPORTV_BLEN          16
+#define IP4_RUL_V3_IP4SPORTV_FLAG          HSL_RW
+
+#define IP4ICMPTYPV
+#define IP4_RUL_V3_IP4ICMPTYPV_BOFFSET     8
+#define IP4_RUL_V3_IP4ICMPTYPV_BLEN        8
+#define IP4_RUL_V3_IP4ICMPTYPV_FLAG        HSL_RW
+
+#define IP4ICMPCODEV
+#define IP4_RUL_V3_IP4ICMPCODEV_BOFFSET    0
+#define IP4_RUL_V3_IP4ICMPCODEV_BLEN       8
+#define IP4_RUL_V3_IP4ICMPCODEV_FLAG       HSL_RW
+
+
+#define IP4_RUL_V4                         4
+#define IP4_RUL_V4_OFFSET                  0x58010
+#define IP4_RUL_V4_E_LENGTH                4
+#define IP4_RUL_V4_E_OFFSET                0x20
+#define IP4_RUL_V4_NR_E                    96
+
+
+#define IP4_RUL_M0                         5
+#define IP4_RUL_M0_OFFSET                  0x59000
+#define IP4_RUL_M0_E_LENGTH                4
+#define IP4_RUL_M0_E_OFFSET                0x20
+#define IP4_RUL_M0_NR_E                    96
+
+#define DIPM
+#define IP4_RUL_M0_DIPM_BOFFSET            0
+#define IP4_RUL_M0_DIPM_BLEN               32
+#define IP4_RUL_M0_DIPM_FLAG               HSL_RW
+
+
+#define IP4_RUL_M1                         6
+#define IP4_RUL_M1_OFFSET                  0x59004
+#define IP4_RUL_M1_E_LENGTH                4
+#define IP4_RUL_M1_E_OFFSET                0x20
+#define IP4_RUL_M1_NR_E                    96
+
+#define SIPM
+#define IP4_RUL_M1_SIPM_BOFFSET            0
+#define IP4_RUL_M1_SIPM_BLEN               32
+#define IP4_RUL_M1_SIPM_FLAG               HSL_RW
+
+
+#define IP4_RUL_M2                         7
+#define IP4_RUL_M2_OFFSET                  0x59008
+#define IP4_RUL_M2_E_LENGTH                4
+#define IP4_RUL_M2_E_OFFSET                0x20
+#define IP4_RUL_M2_NR_E                    96
+
+#define IP4PROTM
+#define IP4_RUL_M2_IP4PROTM_BOFFSET        0
+#define IP4_RUL_M2_IP4PROTM_BLEN           8
+#define IP4_RUL_M2_IP4PROTM_FLAG           HSL_RW
+
+#define IP4DSCPM
+#define IP4_RUL_M2_IP4DSCPM_BOFFSET        8
+#define IP4_RUL_M2_IP4DSCPM_BLEN           8
+#define IP4_RUL_M2_IP4DSCPM_FLAG           HSL_RW
+
+#define IP4DPORTM
+#define IP4_RUL_M2_IP4DPORTM_BOFFSET       16
+#define IP4_RUL_M2_IP4DPORTM_BLEN          16
+#define IP4_RUL_M2_IP4DPORTM_FLAG          HSL_RW
+
+
+#define IP4_RUL_M3                         8
+#define IP4_RUL_M3_OFFSET                  0x5900c
+#define IP4_RUL_M3_E_LENGTH                4
+#define IP4_RUL_M3_E_OFFSET                0x20
+#define IP4_RUL_M3_NR_E                    96
+
+#define IP4TCPFLAGM
+#define IP4_RUL_M3_IP4TCPFLAGM_BOFFSET     24
+#define IP4_RUL_M3_IP4TCPFLAGM_BLEN        6
+#define IP4_RUL_M3_IP4TCPFLAGM_FLAG        HSL_RW
+
+#define IP4DHCPM
+#define IP4_RUL_M3_IP4DHCPM_BOFFSET        22
+#define IP4_RUL_M3_IP4DHCPM_BLEN           1
+#define IP4_RUL_M3_IP4DHCPM_FLAG           HSL_RW
+
+#define IP4RIPM
+#define IP4_RUL_M3_IP4RIPM_BOFFSET         21
+#define IP4_RUL_M3_IP4RIPM_BLEN            1
+#define IP4_RUL_M3_IP4RIPM_FLAG            HSL_RW
+
+#define IP4DPORTM_EN
+#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET    17
+#define IP4_RUL_M3_IP4DPORTM_EN_BLEN       1
+#define IP4_RUL_M3_IP4DPORTM_EN_FLAG       HSL_RW
+
+#define IP4SPORTM_EN
+#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET    16
+#define IP4_RUL_M3_IP4SPORTM_EN_BLEN       1
+#define IP4_RUL_M3_IP4SPORTM_EN_FLAG       HSL_RW
+
+#define IP4SPORTM
+#define IP4_RUL_M3_IP4SPORTM_BOFFSET       0
+#define IP4_RUL_M3_IP4SPORTM_BLEN          16
+#define IP4_RUL_M3_IP4SPORTM_FLAG          HSL_RW
+
+#define IP4ICMPTYPM
+#define IP4_RUL_M3_IP4ICMPTYPM_BOFFSET     8
+#define IP4_RUL_M3_IP4ICMPTYPM_BLEN        8
+#define IP4_RUL_M3_IP4ICMPTYPM_FLAG        HSL_RW
+
+#define IP4ICMPCODEM
+#define IP4_RUL_M3_IP4ICMPCODEM_BOFFSET    0
+#define IP4_RUL_M3_IP4ICMPCODEM_BLEN       8
+#define IP4_RUL_M3_IP4ICMPCODEM_FLAG       HSL_RW
+
+
+#define IP4_RUL_M4                         9
+#define IP4_RUL_M4_OFFSET                  0x59010
+#define IP4_RUL_M4_E_LENGTH                4
+#define IP4_RUL_M4_E_OFFSET                0x20
+#define IP4_RUL_M4_NR_E                    32
+
+
+
+
+    /* IP6 Type1 Rule Field Define */
+#define IP6_RUL1_V0                        0
+#define IP6_RUL1_V0_OFFSET                 0x58000
+#define IP6_RUL1_V0_E_LENGTH               4
+#define IP6_RUL1_V0_E_OFFSET               0x20
+#define IP6_RUL1_V0_NR_E                   96
+
+#define IP6_DIPV0
+#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET      0
+#define IP6_RUL1_V0_IP6_DIPV0_BLEN         32
+#define IP6_RUL1_V0_IP6_DIPV0_FLAG         HSL_RW
+
+
+#define IP6_RUL1_V1                        1
+#define IP6_RUL1_V1_OFFSET                 0x58004
+#define IP6_RUL1_V1_E_LENGTH               4
+#define IP6_RUL1_V1_E_OFFSET               0x20
+#define IP6_RUL1_V1_NR_E                   96
+
+#define IP6_DIPV1
+#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET      0
+#define IP6_RUL1_V1_IP6_DIPv1_BLEN         32
+#define IP6_RUL1_V1_IP6_DIPV1_FLAG         HSL_RW
+
+
+#define IP6_RUL1_V2                        2
+#define IP6_RUL1_V2_OFFSET                 0x58008
+#define IP6_RUL1_V2_E_LENGTH               4
+#define IP6_RUL1_V2_E_OFFSET               0x20
+#define IP6_RUL1_V2_NR_E                   96
+
+#define IP6_DIPV2
+#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET      0
+#define IP6_RUL1_V2_IP6_DIPv2_BLEN         32
+#define IP6_RUL1_V2_IP6_DIPV2_FLAG         HSL_RW
+
+
+#define IP6_RUL1_V3                        3
+#define IP6_RUL1_V3_OFFSET                 0x5800c
+#define IP6_RUL1_V3_E_LENGTH               4
+#define IP6_RUL1_V3_E_OFFSET               0x20
+#define IP6_RUL1_V3_NR_E                   96
+
+#define IP6_DIPV3
+#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET      0
+#define IP6_RUL1_V3_IP6_DIPv3_BLEN         32
+#define IP6_RUL1_V3_IP6_DIPV3_FLAG         HSL_RW
+
+
+#define IP6_RUL1_V4                        4
+#define IP6_RUL1_V4_OFFSET                 0x58010
+#define IP6_RUL1_V4_E_LENGTH               4
+#define IP6_RUL1_V4_E_OFFSET               0x20
+#define IP6_RUL1_V4_NR_E                   96
+
+
+#define IP6_RUL1_M0                        5
+#define IP6_RUL1_M0_OFFSET                 0x59000
+#define IP6_RUL1_M0_E_LENGTH               4
+#define IP6_RUL1_M0_E_OFFSET               0x20
+#define IP6_RUL1_M0_NR_E                   96
+
+#define IP6_DIPM0
+#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET      0
+#define IP6_RUL1_M0_IP6_DIPM0_BLEN         32
+#define IP6_RUL1_M0_IP6_DIPM0_FLAG         HSL_RW
+
+
+#define IP6_RUL1_M1                        6
+#define IP6_RUL1_M1_OFFSET                 0x59004
+#define IP6_RUL1_M1_E_LENGTH               4
+#define IP6_RUL1_M1_E_OFFSET               0x20
+#define IP6_RUL1_M1_NR_E                   96
+
+#define IP6_DIPM1
+#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET      0
+#define IP6_RUL1_M1_IP6_DIPM1_BLEN         32
+#define IP6_RUL1_M1_IP6_DIPM1_FLAG         HSL_RW
+
+
+#define IP6_RUL1_M2                        7
+#define IP6_RUL1_M2_OFFSET                 0x59008
+#define IP6_RUL1_M2_E_LENGTH               4
+#define IP6_RUL1_M2_E_OFFSET               0x20
+#define IP6_RUL1_M2_NR_E                   96
+
+#define IP6_DIPM2
+#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET      0
+#define IP6_RUL1_M2_IP6_DIPM2_BLEN         32
+#define IP6_RUL1_M2_IP6_DIPM2_FLAG         HSL_RW
+
+
+#define IP6_RUL1_M3                        8
+#define IP6_RUL1_M3_OFFSET                 0x5900c
+#define IP6_RUL1_M3_E_LENGTH               4
+#define IP6_RUL1_M3_E_OFFSET               0x20
+#define IP6_RUL1_M3_NR_E                   96
+
+#define IP6_DIPM3
+#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET      0
+#define IP6_RUL1_M3_IP6_DIPM3_BLEN         32
+#define IP6_RUL1_M3_IP6_DIPM3_FLAG         HSL_RW
+
+
+#define IP6_RUL1_M4                        9
+#define IP6_RUL1_M4_OFFSET                 0x59010
+#define IP6_RUL1_M4_E_LENGTH               4
+#define IP6_RUL1_M4_E_OFFSET               0x20
+#define IP6_RUL1_M4_NR_E                   96
+
+
+
+
+    /* IP6 Type2 Rule Field Define */
+#define IP6_RUL2_V0                        0
+#define IP6_RUL2_V0_OFFSET                 0x58000
+#define IP6_RUL2_V0_E_LENGTH               4
+#define IP6_RUL2_V0_E_OFFSET               0x20
+#define IP6_RUL2_V0_NR_E                   96
+
+#define IP6_SIPV0
+#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET      0
+#define IP6_RUL2_V0_IP6_SIPv0_BLEN         32
+#define IP6_RUL2_V0_IP6_SIPV0_FLAG         HSL_RW
+
+
+#define IP6_RUL2_V1                        1
+#define IP6_RUL2_V1_OFFSET                 0x58004
+#define IP6_RUL2_V1_E_LENGTH               4
+#define IP6_RUL2_V1_E_OFFSET               0x20
+#define IP6_RUL2_V1_NR_E                   96
+
+#define IP6_SIPV1
+#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET      0
+#define IP6_RUL2_V1_IP6_SIPv1_BLEN         32
+#define IP6_RUL2_V1_IP6_SIPV1_FLAG         HSL_RW
+
+
+#define IP6_RUL2_V2                        2
+#define IP6_RUL2_V2_OFFSET                 0x58008
+#define IP6_RUL2_V2_E_LENGTH               4
+#define IP6_RUL2_V2_E_OFFSET               0x20
+#define IP6_RUL2_V2_NR_E                   96
+
+#define IP6_SIPV2
+#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET      0
+#define IP6_RUL2_V2_IP6_SIPv2_BLEN         32
+#define IP6_RUL2_V2_IP6_SIPV2_FLAG         HSL_RW
+
+
+#define IP6_RUL2_V3                        3
+#define IP6_RUL2_V3_OFFSET                 0x5800c
+#define IP6_RUL2_V3_E_LENGTH               4
+#define IP6_RUL2_V3_E_OFFSET               0x20
+#define IP6_RUL2_V3_NR_E                   96
+
+#define IP6_SIPV3
+#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET      0
+#define IP6_RUL2_V3_IP6_SIPv3_BLEN         32
+#define IP6_RUL2_V3_IP6_SIPV3_FLAG         HSL_RW
+
+
+#define IP6_RUL2_V4                        4
+#define IP6_RUL2_V4_OFFSET                 0x58010
+#define IP6_RUL2_V4_E_LENGTH               4
+#define IP6_RUL2_V4_E_OFFSET               0x20
+#define IP6_RUL2_V4_NR_E                   96
+
+
+#define IP6_RUL2_M0                        5
+#define IP6_RUL2_M0_OFFSET                 0x59000
+#define IP6_RUL2_M0_E_LENGTH               4
+#define IP6_RUL2_M0_E_OFFSET               0x20
+#define IP6_RUL2_M0_NR_E                   96
+
+#define IP6_SIPM0
+#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET      0
+#define IP6_RUL2_M0_IP6_SIPM0_BLEN         32
+#define IP6_RUL2_M0_IP6_SIPM0_FLAG         HSL_RW
+
+
+#define IP6_RUL2_M1                        6
+#define IP6_RUL2_M1_OFFSET                 0x59004
+#define IP6_RUL2_M1_E_LENGTH               4
+#define IP6_RUL2_M1_E_OFFSET               0x20
+#define IP6_RUL2_M1_NR_E                   96
+
+#define IP6_SIPM1
+#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET      0
+#define IP6_RUL2_M1_IP6_DIPM1_BLEN         32
+#define IP6_RUL2_M1_IP6_DIPM1_FLAG         HSL_RW
+
+
+#define IP6_RUL2_M2                        7
+#define IP6_RUL2_M2_OFFSET                 0x59008
+#define IP6_RUL2_M2_E_LENGTH               4
+#define IP6_RUL2_M2_E_OFFSET               0x20
+#define IP6_RUL2_M2_NR_E                   96
+
+#define IP6_SIPM2
+#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET      0
+#define IP6_RUL2_M2_IP6_DIPM2_BLEN         32
+#define IP6_RUL2_M2_IP6_DIPM2_FLAG         HSL_RW
+
+
+#define IP6_RUL2_M3                        8
+#define IP6_RUL2_M3_OFFSET                 0x5900c
+#define IP6_RUL2_M3_E_LENGTH               4
+#define IP6_RUL2_M3_E_OFFSET               0x20
+#define IP6_RUL2_M3_NR_E                   96
+
+#define IP6_SIPM3
+#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET      0
+#define IP6_RUL2_M3_IP6_SIPM3_BLEN         32
+#define IP6_RUL2_M3_IP6_SIPM3_FLAG         HSL_RW
+
+
+#define IP6_RUL2_M4                        9
+#define IP6_RUL2_M4_OFFSET                 0x59010
+#define IP6_RUL2_M4_E_LENGTH               4
+#define IP6_RUL2_M4_E_OFFSET               0x20
+#define IP6_RUL2_M4_NR_E                   96
+
+
+
+
+    /* IP6 Type3 Rule Field Define */
+#define IP6_RUL3_V0                        0
+#define IP6_RUL3_V0_OFFSET                 0x58000
+#define IP6_RUL3_V0_E_LENGTH               4
+#define IP6_RUL3_V0_E_OFFSET               0x20
+#define IP6_RUL3_V0_NR_E                   96
+
+#define IP6PROTV
+#define IP6_RUL3_V0_IP6PROTV_BOFFSET       0
+#define IP6_RUL3_V0_IP6PROTV_BLEN          8
+#define IP6_RUL3_V0_IP6PROTV_FLAG          HSL_RW
+
+#define IP6DSCPV
+#define IP6_RUL3_V0_IP6DSCPV_BOFFSET       8
+#define IP6_RUL3_V0_IP6DSCPV_BLEN          8
+#define IP6_RUL3_V0_IP6DSCPV_FLAG          HSL_RW
+
+
+#define IP6_RUL3_V1                        1
+#define IP6_RUL3_V1_OFFSET                 0x58004
+#define IP6_RUL3_V1_E_LENGTH               4
+#define IP6_RUL3_V1_E_OFFSET               0x20
+#define IP6_RUL3_V1_NR_E                   96
+
+#define IP6LABEL1V
+#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET     16
+#define IP6_RUL3_V1_IP6LABEL1V_BLEN        16
+#define IP6_RUL3_V1_IP6LABEL1V_FLAG        HSL_RW
+
+
+#define IP6_RUL3_V2                        2
+#define IP6_RUL3_V2_OFFSET                 0x58008
+#define IP6_RUL3_V2_E_LENGTH               4
+#define IP6_RUL3_V2_E_OFFSET               0x20
+#define IP6_RUL3_V2_NR_E                   96
+
+#define IP6LABEL2V
+#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET     0
+#define IP6_RUL3_V2_IP6LABEL2V_BLEN        4
+#define IP6_RUL3_V2_IP6LABEL2V_FLAG        HSL_RW
+
+#define IP6DPORTV
+#define IP6_RUL3_V2_IP6DPORTV_BOFFSET      16
+#define IP6_RUL3_V2_IP6DPORTV_BLEN         16
+#define IP6_RUL3_V2_IP6DPORTV_FLAG         HSL_RW
+
+
+#define IP6_RUL3_V3                        3
+#define IP6_RUL3_V3_OFFSET                 0x5800c
+#define IP6_RUL3_V3_E_LENGTH               4
+#define IP6_RUL3_V3_E_OFFSET               0x20
+#define IP6_RUL3_V3_NR_E                   96
+
+#define IP6TCPFLAGV
+#define IP6_RUL3_V3_IP6TCPFLAGV_BOFFSET    24
+#define IP6_RUL3_V3_IP6TCPFLAGV_BLEN       6
+#define IP6_RUL3_V3_IP6TCPFLAGV_FLAG       HSL_RW
+
+#define IP6FWDTYPV
+#define IP6_RUL3_V3_IP6FWDTYPV_BOFFSET     23
+#define IP6_RUL3_V3_IP6FWDTYPV_BLEN        1
+#define IP6_RUL3_V3_IP6FWDTYPV_FLAG        HSL_RW
+
+#define IP6DHCPV
+#define IP6_RUL3_V3_IP6DHCPV_BOFFSET       22
+#define IP6_RUL3_V3_IP6DHCPV_BLEN          1
+#define IP6_RUL3_V3_IP6DHCPV_FLAG          HSL_RW
+
+#define ICMP6_EN
+#define IP6_RUL3_V3_ICMP6_EN_BOFFSET       20
+#define IP6_RUL3_V3_ICMP6_EN_BLEN          1
+#define IP6_RUL3_V3_ICMP6_EN_FLAG          HSL_RW
+
+#define IP6SPORTV
+#define IP6_RUL3_V3_IP6SPORTV_BOFFSET      0
+#define IP6_RUL3_V3_IP6SPORTV_BLEN         16
+#define IP6_RUL3_V3_IP6SPORTV_FLAG         HSL_RW
+
+#define IP6ICMPTYPV
+#define IP6_RUL3_V3_IP6ICMPTYPV_BOFFSET    8
+#define IP6_RUL3_V3_IP6ICMPTYPV_BLEN       8
+#define IP6_RUL3_V3_IP6ICMPTYPV_FLAG       HSL_RW
+
+#define IP6ICMPCODEV
+#define IP6_RUL3_V3_IP6ICMPCODEV_BOFFSET   0
+#define IP6_RUL3_V3_IP6ICMPCODEV_BLEN      8
+#define IP6_RUL3_V3_IP6ICMPCODEV_FLAG      HSL_RW
+
+
+#define IP6_RUL3_V4                        4
+#define IP6_RUL3_V4_OFFSET                 0x58010
+#define IP6_RUL3_V4_E_LENGTH               4
+#define IP6_RUL3_V4_E_OFFSET               0x20
+#define IP6_RUL3_V4_NR_E                   96
+
+
+#define IP6_RUL3_M0                        5
+#define IP6_RUL3_M0_OFFSET                 0x59000
+#define IP6_RUL3_M0_E_LENGTH               4
+#define IP6_RUL3_M0_E_OFFSET               0x20
+#define IP6_RUL3_M0_NR_E                   96
+
+#define IP6PROTM
+#define IP6_RUL3_M0_IP6PROTM_BOFFSET       0
+#define IP6_RUL3_M0_IP6PROTM_BLEN          8
+#define IP6_RUL3_M0_IP6PROTM_FLAG          HSL_RW
+
+#define IP6DSCPM
+#define IP6_RUL3_M0_IP6DSCPM_BOFFSET       8
+#define IP6_RUL3_M0_IP6DSCPM_BLEN          8
+#define IP6_RUL3_M0_IP6DSCPM_FLAG          HSL_RW
+
+
+#define IP6_RUL3_M1                        6
+#define IP6_RUL3_M1_OFFSET                 0x59004
+#define IP6_RUL3_M1_E_LENGTH               4
+#define IP6_RUL3_M1_E_OFFSET               0x20
+#define IP6_RUL3_M1_NR_E                   96
+
+#define IP6LABEL1M
+#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET     16
+#define IP6_RUL3_M1_IP6LABEL1M_BLEN        16
+#define IP6_RUL3_M1_IP6LABEL1M_FLAG        HSL_RW
+
+
+#define IP6_RUL3_M2                        7
+#define IP6_RUL3_M2_OFFSET                 0x59008
+#define IP6_RUL3_M2_E_LENGTH               4
+#define IP6_RUL3_M2_E_OFFSET               0x20
+#define IP6_RUL3_M2_NR_E                   96
+
+#define IP6LABEL2M
+#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET     0
+#define IP6_RUL3_M2_IP6LABEL2M_BLEN        4
+#define IP6_RUL3_M2_IP6LABEL21M_FLAG       HSL_RW
+
+#define IP6DPORTM
+#define IP6_RUL3_M2_IP6DPORTM_BOFFSET      16
+#define IP6_RUL3_M2_IP6DPORTM_BLEN         16
+#define IP6_RUL3_M2_IP6DPORTM_FLAG         HSL_RW
+
+
+#define IP6_RUL3_M3                        8
+#define IP6_RUL3_M3_OFFSET                 0x5900c
+#define IP6_RUL3_M3_E_LENGTH               4
+#define IP6_RUL3_M3_E_OFFSET               0x20
+#define IP6_RUL3_M3_NR_E                   96
+
+#define IP6TCPFLAGM
+#define IP6_RUL3_M3_IP6TCPFLAGM_BOFFSET    24
+#define IP6_RUL3_M3_IP6TCPFLAGM_BLEN       6
+#define IP6_RUL3_M3_IP6TCPFLAGM_FLAG       HSL_RW
+
+#define IP6RWDTYPM
+#define IP6_RUL3_M3_IP6RWDTYPV_BOFFSET     23
+#define IP6_RUL3_M3_IP6RWDTYPV_BLEN        1
+#define IP6_RUL3_M3_IP6RWDTYPV_FLAG        HSL_RW
+
+#define IP6DHCPM
+#define IP6_RUL3_M3_IP6DHCPM_BOFFSET       22
+#define IP6_RUL3_M3_IP6DHCPM_BLEN          1
+#define IP6_RUL3_M3_IP6DHCPM_FLAG          HSL_RW
+
+#define IP6DPORTM_EN
+#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET   17
+#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN      1
+#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG      HSL_RW
+
+#define IP6SPORTM_EN
+#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET   16
+#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN      1
+#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG      HSL_RW
+
+#define IP6SPORTM
+#define IP6_RUL3_M3_IP6SPORTM_BOFFSET      0
+#define IP6_RUL3_M3_IP6SPORTM_BLEN         16
+#define IP6_RUL3_M3_IP6SPORTM_FLAG         HSL_RW
+
+#define IP6ICMPTYPM
+#define IP6_RUL3_M3_IP6ICMPTYPM_BOFFSET     8
+#define IP6_RUL3_M3_IP6ICMPTYPM_BLEN        8
+#define IP6_RUL3_M3_IP6ICMPTYPM_FLAG        HSL_RW
+
+#define IP6ICMPCODEM
+#define IP6_RUL3_M3_IP6ICMPCODEM_BOFFSET    0
+#define IP6_RUL3_M3_IP6ICMPCODEM_BLEN       8
+#define IP6_RUL3_M3_IP6ICMPCODEM_FLAG       HSL_RW
+
+
+#define IP6_RUL3_M4                        9
+#define IP6_RUL3_M4_OFFSET                 0x59010
+#define IP6_RUL3_M4_E_LENGTH               4
+#define IP6_RUL3_M4_E_OFFSET               0x20
+#define IP6_RUL3_M4_NR_E                   96
+
+
+
+
+    /* Enhanced MAC Type Rule Field Define */
+#define EHMAC_RUL_V0                         0
+#define EHMAC_RUL_V0_OFFSET                  0x58000
+#define EHMAC_RUL_V0_E_LENGTH                4
+#define EHMAC_RUL_V0_E_OFFSET                0x20
+#define EHMAC_RUL_V0_NR_E                    96
+
+#define DAV_BYTE2
+#define EHMAC_RUL_V0_DAV_BYTE2_BOFFSET       24
+#define EHMAC_RUL_V0_DAV_BYTE2_BLEN          8
+#define EHMAC_RUL_V0_DAV_BYTE2_FLAG          HSL_RW
+
+#define DAV_BYTE3
+#define EHMAC_RUL_V0_DAV_BYTE3_BOFFSET       16
+#define EHMAC_RUL_V0_DAV_BYTE3_BLEN          8
+#define EHMAC_RUL_V0_DAV_BYTE3_FLAG          HSL_RW
+
+#define DAV_BYTE4
+#define EHMAC_RUL_V0_DAV_BYTE4_BOFFSET       8
+#define EHMAC_RUL_V0_DAV_BYTE4_BLEN          8
+#define EHMAC_RUL_V0_DAV_BYTE4_FLAG          HSL_RW
+
+#define DAV_BYTE5
+#define EHMAC_RUL_V0_DAV_BYTE5_BOFFSET       0
+#define EHMAC_RUL_V0_DAV_BYTE5_BLEN          8
+#define EHMAC_RUL_V0_DAV_BYTE5_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_V1                         1
+#define EHMAC_RUL_V1_OFFSET                  0x58004
+#define EHMAC_RUL_V1_E_LENGTH                4
+#define EHMAC_RUL_V1_E_OFFSET                0x20
+#define EHMAC_RUL_V1_NR_E                    96
+
+#define SAV_BYTE4
+#define EHMAC_RUL_V1_SAV_BYTE4_BOFFSET       24
+#define EHMAC_RUL_V1_SAV_BYTE4_BLEN          8
+#define EHMAC_RUL_V1_SAV_BYTE4_FLAG          HSL_RW
+
+#define SAV_BYTE5
+#define EHMAC_RUL_V1_SAV_BYTE5_BOFFSET       16
+#define EHMAC_RUL_V1_SAV_BYTE5_BLEN          8
+#define EHMAC_RUL_V1_SAV_BYTE5_FLAG          HSL_RW
+
+#define DAV_BYTE0
+#define EHMAC_RUL_V1_DAV_BYTE0_BOFFSET       8
+#define EHMAC_RUL_V1_DAV_BYTE0_BLEN          8
+#define EHMAC_RUL_V1_DAV_BYTE0_FLAG          HSL_RW
+
+#define DAV_BYTE1
+#define EHMAC_RUL_V1_DAV_BYTE1_BOFFSET       0
+#define EHMAC_RUL_V1_DAV_BYTE1_BLEN          8
+#define EHMAC_RUL_V1_DAV_BYTE1_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_V2                         2
+#define EHMAC_RUL_V2_OFFSET                  0x58008
+#define EHMAC_RUL_V2_E_LENGTH                4
+#define EHMAC_RUL_V2_E_OFFSET                0x20
+#define EHMAC_RUL_V2_NR_E                    96
+
+#define CTAG_VIDLV
+#define EHMAC_RUL_V2_CTAG_VIDLV_BOFFSET      24
+#define EHMAC_RUL_V2_CTAG_VIDLV_BLEN         8
+#define EHMAC_RUL_V2_CTAG_VIDLV_FLAG         HSL_RW
+
+#define STAG_PRIV
+#define EHMAC_RUL_V2_STAG_PRIV_BOFFSET       21
+#define EHMAC_RUL_V2_STAG_PRIV_BLEN          3
+#define EHMAC_RUL_V2_STAG_PRIV_FLAG          HSL_RW
+
+#define STAG_DEIV
+#define EHMAC_RUL_V2_STAG_DEIV_BOFFSET       20
+#define EHMAC_RUL_V2_STAG_DEIV_BLEN          1
+#define EHMAC_RUL_V2_STAG_DEIV_FLAG          HSL_RW
+
+#define STAG_VIDV
+#define EHMAC_RUL_V2_STAG_VIDV_BOFFSET       8
+#define EHMAC_RUL_V2_STAG_VIDV_BLEN          12
+#define EHMAC_RUL_V2_STAG_VIDV_FLAG          HSL_RW
+
+#define SAV_BYTE3
+#define EHMAC_RUL_V2_SAV_BYTE3_BOFFSET       0
+#define EHMAC_RUL_V2_SAV_BYTE3_BLEN          8
+#define EHMAC_RUL_V2_SAV_BYTE3_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_V3                         3
+#define EHMAC_RUL_V3_ID                      13
+#define EHMAC_RUL_V3_OFFSET                  0x5800c
+#define EHMAC_RUL_V3_E_LENGTH                4
+#define EHMAC_RUL_V3_E_OFFSET                0x20
+#define EHMAC_RUL_V3_NR_E                    96
+
+#define STAGGEDM
+#define EHMAC_RUL_V3_STAGGEDM_BOFFSET         31
+#define EHMAC_RUL_V3_STAGGEDM_BLEN            1
+#define EHMAC_RUL_V3_STAGGEDM_FLAG            HSL_RW
+
+#define STAGGEDV
+#define EHMAC_RUL_V3_STAGGEDV_BOFFSET         30
+#define EHMAC_RUL_V3_STAGGEDV_BLEN            1
+#define EHMAC_RUL_V3_STAGGEDV_FLAG            HSL_RW
+
+#define DA_EN
+#define EHMAC_RUL_V3_DA_EN_BOFFSET          25
+#define EHMAC_RUL_V3_DA_EN_BLEN             1
+#define EHMAC_RUL_V3_DA_EN_FLAG             HSL_RW
+
+#define SVIDMSK
+#define EHMAC_RUL_V3_SVIDMSK_BOFFSET          24
+#define EHMAC_RUL_V3_SVIDMSK_BLEN             1
+#define EHMAC_RUL_V3_SVIDMSK_FLAG             HSL_RW
+
+#define ETHTYPV
+#define EHMAC_RUL_V3_ETHTYPV_BOFFSET         8
+#define EHMAC_RUL_V3_ETHTYPV_BLEN            16
+#define EHMAC_RUL_V3_ETHTYPV_FLAG            HSL_RW
+
+#define CTAG_PRIV
+#define EHMAC_RUL_V3_CTAG_PRIV_BOFFSET       5
+#define EHMAC_RUL_V3_CTAG_PRIV_BLEN          3
+#define EHMAC_RUL_V3_CTAG_PRIV_FLAG          HSL_RW
+
+#define CTAG_CFIV
+#define EHMAC_RUL_V3_CTAG_CFIV_BOFFSET       4
+#define EHMAC_RUL_V3_CTAG_CFIV_BLEN          1
+#define EHMAC_RUL_V3_CTAG_CFIV_FLAG          HSL_RW
+
+#define CTAG_VIDHV
+#define EHMAC_RUL_V3_CTAG_VIDHV_BOFFSET      0
+#define EHMAC_RUL_V3_CTAG_VIDHV_BLEN         4
+#define EHMAC_RUL_V3_CTAG_VIDHV_FLAG         HSL_RW
+
+
+#define EHMAC_RUL_V4                         4
+#define EHMAC_RUL_V4_OFFSET                  0x58010
+#define EHMAC_RUL_V4_E_LENGTH                4
+#define EHMAC_RUL_V4_E_OFFSET                0x20
+#define EHMAC_RUL_V4_NR_E                    96
+
+
+#define EHMAC_RUL_M0                         5
+#define EHMAC_RUL_M0_OFFSET                  0x59000
+#define EHMAC_RUL_M0_E_LENGTH                4
+#define EHMAC_RUL_M0_E_OFFSET                0x20
+#define EHMAC_RUL_M0_NR_E                    96
+
+#define DAM_BYTE2
+#define EHMAC_RUL_M0_DAM_BYTE2_BOFFSET       24
+#define EHMAC_RUL_M0_DAM_BYTE2_BLEN          8
+#define EHMAC_RUL_M0_DAM_BYTE2_FLAG          HSL_RW
+
+#define DAM_BYTE3
+#define EHMAC_RUL_M0_DAM_BYTE3_BOFFSET       16
+#define EHMAC_RUL_M0_DAM_BYTE3_BLEN          8
+#define EHMAC_RUL_M0_DAM_BYTE3_FLAG          HSL_RW
+
+#define DAM_BYTE4
+#define EHMAC_RUL_M0_DAM_BYTE4_BOFFSET       8
+#define EHMAC_RUL_M0_DAM_BYTE4_BLEN          8
+#define EHMAC_RUL_M0_DAM_BYTE4_FLAG          HSL_RW
+
+#define DAM_BYTE5
+#define EHMAC_RUL_M0_DAM_BYTE5_BOFFSET       0
+#define EHMAC_RUL_M0_DAM_BYTE5_BLEN          8
+#define EHMAC_RUL_M0_DAM_BYTE5_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_M1                         6
+#define EHMAC_RUL_M1_OFFSET                  0x59004
+#define EHMAC_RUL_M1_E_LENGTH                4
+#define EHMAC_RUL_M1_E_OFFSET                0x20
+#define EHMAC_RUL_M1_NR_E                    96
+
+#define SAM_BYTE4
+#define EHMAC_RUL_M1_SAM_BYTE4_BOFFSET       24
+#define EHMAC_RUL_M1_SAM_BYTE4_BLEN          8
+#define EHMAC_RUL_M1_SAM_BYTE4_FLAG          HSL_RW
+
+#define SAM_BYTE5
+#define EHMAC_RUL_M1_SAM_BYTE5_BOFFSET       16
+#define EHMAC_RUL_M1_SAM_BYTE5_BLEN          8
+#define EHMAC_RUL_M1_SAM_BYTE5_FLAG          HSL_RW
+
+#define DAM_BYTE0
+#define EHMAC_RUL_M1_DAM_BYTE0_BOFFSET       8
+#define EHMAC_RUL_M1_DAM_BYTE0_BLEN          8
+#define EHMAC_RUL_M1_DAM_BYTE0_FLAG          HSL_RW
+
+#define DAM_BYTE1
+#define EHMAC_RUL_M1_DAM_BYTE1_BOFFSET       0
+#define EHMAC_RUL_M1_DAM_BYTE1_BLEN          8
+#define EHMAC_RUL_M1_DAM_BYTE1_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_M2                         7
+#define EHMAC_RUL_M2_OFFSET                  0x59008
+#define EHMAC_RUL_M2_E_LENGTH                4
+#define EHMAC_RUL_M2_E_OFFSET                0x20
+#define EHMAC_RUL_M2_NR_E                    96
+
+#define CTAG_VIDLM
+#define EHMAC_RUL_M2_CTAG_VIDLM_BOFFSET      24
+#define EHMAC_RUL_M2_CTAG_VIDLM_BLEN         8
+#define EHMAC_RUL_M2_CTAG_VIDLM_FLAG         HSL_RW
+
+#define STAG_PRIM
+#define EHMAC_RUL_M2_STAG_PRIM_BOFFSET       21
+#define EHMAC_RUL_M2_STAG_PRIM_BLEN          3
+#define EHMAC_RUL_M2_STAG_PRIM_FLAG          HSL_RW
+
+#define STAG_DEIM
+#define EHMAC_RUL_M2_STAG_DEIM_BOFFSET       20
+#define EHMAC_RUL_M2_STAG_DEIM_BLEN          1
+#define EHMAC_RUL_M2_STAG_DEIM_FLAG          HSL_RW
+
+#define STAG_VIDM
+#define EHMAC_RUL_M2_STAG_VIDM_BOFFSET       8
+#define EHMAC_RUL_M2_STAG_VIDM_BLEN          12
+#define EHMAC_RUL_M2_STAG_VIDM_FLAG          HSL_RW
+
+#define SAM_BYTE3
+#define EHMAC_RUL_M2_SAM_BYTE3_BOFFSET       0
+#define EHMAC_RUL_M2_SAM_BYTE3_BLEN          8
+#define EHMAC_RUL_M2_SAM_BYTE3_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_M3                         8
+#define EHMAC_RUL_M3_OFFSET                  0x5900c
+#define EHMAC_RUL_M3_E_LENGTH                4
+#define EHMAC_RUL_M3_E_OFFSET                0x20
+#define EHMAC_RUL_M3_NR_E                    96
+
+#define ETHTYPM
+#define EHMAC_RUL_M3_ETHTYPM_BOFFSET         8
+#define EHMAC_RUL_M3_ETHTYPM_BLEN            16
+#define EHMAC_RUL_M3_ETHTYPM_FLAG            HSL_RW
+
+#define CTAG_PRIM
+#define EHMAC_RUL_M3_CTAG_PRIM_BOFFSET       5
+#define EHMAC_RUL_M3_CTAG_PRIM_BLEN          3
+#define EHMAC_RUL_M3_CTAG_PRIM_FLAG          HSL_RW
+
+#define CTAG_CFIM
+#define EHMAC_RUL_M3_CTAG_CFIM_BOFFSET       4
+#define EHMAC_RUL_M3_CTAG_CFIM_BLEN          1
+#define EHMAC_RUL_M3_CTAG_CFIM_FLAG          HSL_RW
+
+#define CTAG_VIDHM
+#define EHMAC_RUL_M3_CTAG_VIDHM_BOFFSET      0
+#define EHMAC_RUL_M3_CTAG_VIDHM_BLEN         4
+#define EHMAC_RUL_M3_CTAG_VIDHM_FLAG         HSL_RW
+
+
+#define EHMAC_RUL_M4                         9
+#define EHMAC_RUL_M4_OFFSET                  0x59010
+#define EHMAC_RUL_M4_E_LENGTH                4
+#define EHMAC_RUL_M4_E_OFFSET                0x20
+#define EHMAC_RUL_M4_NR_E                    96
+
+#define CTAGGEDM
+#define EHMAC_RUL_M4_CTAGGEDM_BOFFSET        5
+#define EHMAC_RUL_M4_CTAGGEDM_BLEN           1
+#define EHMAC_RUL_M4_CTAGGEDM_FLAG           HSL_RW
+
+#define CTAGGEDV
+#define EHMAC_RUL_M4_CTAGGEDV_BOFFSET        4
+#define EHMAC_RUL_M4_CTAGGEDV_BLEN           1
+#define EHMAC_RUL_M4_CTAGGEDV_FLAG           HSL_RW
+
+#define CVIDMSK
+#define EHMAC_RUL_M4_CVIDMSK_BOFFSET         3
+#define EHMAC_RUL_M4_CVIDMSK_BLEN            1
+#define EHMAC_RUL_M4_CVIDMSK_FLAG            HSL_RW
+
+
+
+
+    /* PPPoE Session Table Define */
+#define PPPOE_SESSION
+#define PPPOE_SESSION_OFFSET                       0x5f000
+#define PPPOE_SESSION_E_LENGTH                     4
+#define PPPOE_SESSION_E_OFFSET                     0x4
+#define PPPOE_SESSION_NR_E                         16
+
+#define VRF_ID
+#define PPPOE_SESSION_VRF_ID_BOFFSET           18
+#define PPPOE_SESSION_VRF_ID_BLEN              3
+#define PPPOE_SESSION_VRF_ID_FLAG              HSL_RW
+
+#define ENTRY_VALID
+#define PPPOE_SESSION_ENTRY_VALID_BOFFSET          16
+#define PPPOE_SESSION_ENTRY_VALID_BLEN             2
+#define PPPOE_SESSION_ENTRY_VALID_FLAG             HSL_RW
+
+#define SEESION_ID
+#define PPPOE_SESSION_SEESION_ID_BOFFSET           0
+#define PPPOE_SESSION_SEESION_ID_BLEN              16
+#define PPPOE_SESSION_SEESION_ID_FLAG              HSL_RW
+
+
+
+#define PPPOE_EDIT
+#define PPPOE_EDIT_OFFSET                       0x02200
+#define PPPOE_EDIT_E_LENGTH                     4
+#define PPPOE_EDIT_E_OFFSET                     0x10
+#define PPPOE_EDIT_NR_E                         16
+
+#define EDIT_ID
+#define PPPOE_EDIT_EDIT_ID_BOFFSET              0
+#define PPPOE_EDIT_EDIT_ID_BLEN                 16
+#define PPPOE_EDIT_EDIT_ID_FLAG                 HSL_RW
+
+
+
+
+    /* L3 Host Entry Define */
+#define HOST_ENTRY0
+#define HOST_ENTRY0_OFFSET                       0x0e80
+#define HOST_ENTRY0_E_LENGTH                     4
+#define HOST_ENTRY0_E_OFFSET                     0x0
+#define HOST_ENTRY0_NR_E                         1
+
+#define IP_ADDR
+#define HOST_ENTRY0_IP_ADDR_BOFFSET              0
+#define HOST_ENTRY0_IP_ADDR_BLEN                 32
+#define HOST_ENTRY0_IP_ADDR_FLAG                 HSL_RW
+
+
+#define HOST_ENTRY1
+#define HOST_ENTRY1_OFFSET                       0x0e84
+#define HOST_ENTRY1_E_LENGTH                     4
+#define HOST_ENTRY1_E_OFFSET                     0x0
+#define HOST_ENTRY1_NR_E                         1
+
+
+#define HOST_ENTRY2
+#define HOST_ENTRY2_OFFSET                       0x0e88
+#define HOST_ENTRY2_E_LENGTH                     4
+#define HOST_ENTRY2_E_OFFSET                     0x0
+#define HOST_ENTRY2_NR_E                         1
+
+
+#define HOST_ENTRY3
+#define HOST_ENTRY3_OFFSET                       0x0e8c
+#define HOST_ENTRY3_E_LENGTH                     4
+#define HOST_ENTRY3_E_OFFSET                     0x0
+#define HOST_ENTRY3_NR_E                         1
+
+
+#define HOST_ENTRY4
+#define HOST_ENTRY4_OFFSET                       0x0e90
+#define HOST_ENTRY4_E_LENGTH                     4
+#define HOST_ENTRY4_E_OFFSET                     0x0
+#define HOST_ENTRY4_NR_E                         1
+
+#define MAC_ADDR2
+#define HOST_ENTRY4_MAC_ADDR2_BOFFSET            24
+#define HOST_ENTRY4_MAC_ADDR2_BLEN               8
+#define HOST_ENTRY4_MAC_ADDR2_FLAG               HSL_RW
+
+#define MAC_ADDR3
+#define HOST_ENTRY4_MAC_ADDR3_BOFFSET            16
+#define HOST_ENTRY4_MAC_ADDR3_BLEN               8
+#define HOST_ENTRY4_MAC_ADDR3_FLAG               HSL_RW
+
+#define MAC_ADDR4
+#define HOST_ENTRY4_MAC_ADDR4_BOFFSET            8
+#define HOST_ENTRY4_MAC_ADDR4_BLEN               8
+#define HOST_ENTRY4_MAC_ADDR4_FLAG               HSL_RW
+
+#define MAC_ADDR5
+#define HOST_ENTRY4_MAC_ADDR5_BOFFSET            0
+#define HOST_ENTRY4_MAC_ADDR5_BLEN               8
+#define HOST_ENTRY4_MAC_ADDR5_FLAG               HSL_RW
+
+#define HOST_ENTRY5
+#define HOST_ENTRY5_OFFSET                       0x0e94
+#define HOST_ENTRY5_E_LENGTH                     4
+#define HOST_ENTRY5_E_OFFSET                     0x0
+#define HOST_ENTRY5_NR_E                         1
+
+#define CPU_ADDR
+#define HOST_ENTRY5_CPU_ADDR_BOFFSET             31
+#define HOST_ENTRY5_CPU_ADDR_BLEN                1
+#define HOST_ENTRY5_CPU_ADDR_FLAG                HSL_RW
+
+#define SRC_PORT
+#define HOST_ENTRY5_SRC_PORT_BOFFSET             28
+#define HOST_ENTRY5_SRC_PORT_BLEN                3
+#define HOST_ENTRY5_SRC_PORT_FLAG                HSL_RW
+
+#define INTF_ID
+#define HOST_ENTRY5_INTF_ID_BOFFSET              16
+#define HOST_ENTRY5_INTF_ID_BLEN                 12
+#define HOST_ENTRY5_INTF_ID_FLAG                 HSL_RW
+
+#define MAC_ADDR0
+#define HOST_ENTRY5_MAC_ADDR0_BOFFSET            8
+#define HOST_ENTRY5_MAC_ADDR0_BLEN               8
+#define HOST_ENTRY5_MAC_ADDR0_FLAG               HSL_RW
+
+#define MAC_ADDR1
+#define HOST_ENTRY5_MAC_ADDR1_BOFFSET            0
+#define HOST_ENTRY5_MAC_ADDR1_BLEN               8
+#define HOST_ENTRY5_MAC_ADDR1_FLAG               HSL_RW
+
+
+#define HOST_ENTRY6
+#define HOST_ENTRY6_OFFSET                       0x0e98
+#define HOST_ENTRY6_E_LENGTH                     4
+#define HOST_ENTRY6_E_OFFSET                     0x0
+#define HOST_ENTRY6_NR_E                         1
+
+#define LB_BIT
+#define HOST_ENTRY6_LB_BIT_BOFFSET             19
+#define HOST_ENTRY6_LB_BIT_BLEN                3
+#define HOST_ENTRY6_LB_BIT_FLAG                HSL_RW
+
+#define VRF_ID
+#define HOST_ENTRY6_VRF_ID_BOFFSET             16
+#define HOST_ENTRY6_VRF_ID_BLEN                3
+#define HOST_ENTRY6_VRF_ID_FLAG                HSL_RW
+
+#define IP_VER
+#define HOST_ENTRY6_IP_VER_BOFFSET               15
+#define HOST_ENTRY6_IP_VER_BLEN                  1
+#define HOST_ENTRY6_IP_VER_FLAG                  HSL_RW
+
+#define AGE_FLAG
+#define HOST_ENTRY6_AGE_FLAG_BOFFSET             12
+#define HOST_ENTRY6_AGE_FLAG_BLEN                3
+#define HOST_ENTRY6_AGE_FLAG_FLAG                HSL_RW
+
+#define PPPOE_EN
+#define HOST_ENTRY6_PPPOE_EN_BOFFSET             11
+#define HOST_ENTRY6_PPPOE_EN_BLEN                1
+#define HOST_ENTRY6_PPPOE_EN_FLAG                HSL_RW
+
+#define PPPOE_IDX
+#define HOST_ENTRY6_PPPOE_IDX_BOFFSET            7
+#define HOST_ENTRY6_PPPOE_IDX_BLEN               4
+#define HOST_ENTRY6_PPPOE_IDX_FLAG               HSL_RW
+
+#define CNT_EN
+#define HOST_ENTRY6_CNT_EN_BOFFSET               6
+#define HOST_ENTRY6_CNT_EN_BLEN                  1
+#define HOST_ENTRY6_CNT_EN_FLAG                  HSL_RW
+
+#define CNT_IDX
+#define HOST_ENTRY6_CNT_IDX_BOFFSET              2
+#define HOST_ENTRY6_CNT_IDX_BLEN                 4
+#define HOST_ENTRY6_CNT_IDX_FLAG                 HSL_RW
+
+#define ACTION
+#define HOST_ENTRY6_ACTION_BOFFSET               0
+#define HOST_ENTRY6_ACTION_BLEN                  2
+#define HOST_ENTRY6_ACTION_FLAG                  HSL_RW
+
+
+#define HOST_ENTRY7
+#define HOST_ENTRY7_OFFSET                       0x0e58
+#define HOST_ENTRY7_E_LENGTH                     4
+#define HOST_ENTRY7_E_OFFSET                     0x0
+#define HOST_ENTRY7_NR_E                         1
+
+#define TBL_BUSY
+#define HOST_ENTRY7_TBL_BUSY_BOFFSET             31
+#define HOST_ENTRY7_TBL_BUSY_BLEN                1
+#define HOST_ENTRY7_TBL_BUSY_FLAG                HSL_RW
+
+#define SPEC_SYNC
+#define HOST_ENTRY7_SPEC_SYNC_BOFFSET            23
+#define HOST_ENTRY7_SPEC_SYNC_BLEN               1
+#define HOST_ENTRY7_SPEC_SYNC_FLAG               HSL_RW
+
+#define SPEC_SP
+#define HOST_ENTRY7_SPEC_SP_BOFFSET              22
+#define HOST_ENTRY7_SPEC_SP_BLEN                 1
+#define HOST_ENTRY7_SPEC_SP_FLAG                 HSL_RW
+
+#define SPEC_VID
+#define HOST_ENTRY7_SPEC_VID_BOFFSET             21
+#define HOST_ENTRY7_SPEC_VID_BLEN                1
+#define HOST_ENTRY7_SPEC_VID_FLAG                HSL_RW
+
+#define SPEC_PIP
+#define HOST_ENTRY7_SPEC_PIP_BOFFSET             20
+#define HOST_ENTRY7_SPEC_PIP_BLEN                1
+#define HOST_ENTRY7_SPEC_PIP_FLAG                HSL_RW
+
+#define SPEC_SIP
+#define HOST_ENTRY7_SPEC_SIP_BOFFSET             19
+#define HOST_ENTRY7_SPEC_SIP_BLEN                1
+#define HOST_ENTRY7_SPEC_SIP_FLAG                HSL_RW
+
+#define SPEC_STATUS
+#define HOST_ENTRY7_SPEC_STATUS_BOFFSET          18
+#define HOST_ENTRY7_SPEC_STATUS_BLEN             1
+#define HOST_ENTRY7_SPEC_STATUS_FLAG             HSL_RW
+
+#define TBL_IDX
+#define HOST_ENTRY7_TBL_IDX_BOFFSET              8
+#define HOST_ENTRY7_TBL_IDX_BLEN                 10
+#define HOST_ENTRY7_TBL_IDX_FLAG                 HSL_RW
+
+#define TBL_STAUS
+#define HOST_ENTRY7_TBL_STAUS_BOFFSET            7
+#define HOST_ENTRY7_TBL_STAUS_BLEN               1
+#define HOST_ENTRY7_TBL_STAUS_FLAG               HSL_RW
+
+#define TBL_SEL
+#define HOST_ENTRY7_TBL_SEL_BOFFSET              4
+#define HOST_ENTRY7_TBL_SEL_BLEN                 2
+#define HOST_ENTRY7_TBL_SEL_FLAG                 HSL_RW
+
+#define ENTRY_FUNC
+#define HOST_ENTRY7_ENTRY_FUNC_BOFFSET           0
+#define HOST_ENTRY7_ENTRY_FUNC_BLEN              3
+#define HOST_ENTRY7_ENTRY_FUNC_FLAG              HSL_RW
+
+
+
+
+#define NAT_ENTRY0
+#define NAT_ENTRY0_OFFSET                       0x0e80
+#define NAT_ENTRY0_E_LENGTH                     4
+#define NAT_ENTRY0_E_OFFSET                     0x0
+#define NAT_ENTRY0_NR_E                         1
+
+#define IP_ADDR
+#define NAT_ENTRY0_IP_ADDR_BOFFSET              0
+#define NAT_ENTRY0_IP_ADDR_BLEN                 32
+#define NAT_ENTRY0_IP_ADDR_FLAG                 HSL_RW
+
+
+#define NAT_ENTRY1
+#define NAT_ENTRY1_OFFSET                       0x0e84
+#define NAT_ENTRY1_E_LENGTH                     4
+#define NAT_ENTRY1_E_OFFSET                     0x0
+#define NAT_ENTRY1_NR_E                         1
+
+#define PRV_IPADDR0
+#define NAT_ENTRY1_PRV_IPADDR0_BOFFSET          24
+#define NAT_ENTRY1_PRV_IPADDR0_BLEN             8
+#define NAT_ENTRY1_PRV_IPADDR0_FLAG             HSL_RW
+
+#define PORT_RANGE
+#define NAT_ENTRY1_PORT_RANGE_BOFFSET            16
+#define NAT_ENTRY1_PORT_RANGE_BLEN               8
+#define NAT_ENTRY1_PORT_RANGE_FLAG               HSL_RW
+
+#define PORT_NUM
+#define NAT_ENTRY1_PORT_NUM_BOFFSET              0
+#define NAT_ENTRY1_PORT_NUM_BLEN                 16
+#define NAT_ENTRY1_PORT_NUM_FLAG                 HSL_RW
+
+
+#define NAT_ENTRY2
+#define NAT_ENTRY2_OFFSET                       0x0e88
+#define NAT_ENTRY2_E_LENGTH                     4
+#define NAT_ENTRY2_E_OFFSET                     0x0
+#define NAT_ENTRY2_NR_E                         1
+
+#define HASH_KEY
+#define NAT_ENTRY2_HASH_KEY_BOFFSET             30
+#define NAT_ENTRY2_HASH_KEY_BLEN                2
+#define NAT_ENTRY2_HASH_KEY_FLAG                HSL_RW
+
+#define ACTION
+#define NAT_ENTRY2_ACTION_BOFFSET               28
+#define NAT_ENTRY2_ACTION_BLEN                  2
+#define NAT_ENTRY2_ACTION_FLAG                  HSL_RW
+
+#define CNT_EN
+#define NAT_ENTRY2_CNT_EN_BOFFSET               27
+#define NAT_ENTRY2_CNT_EN_BLEN                  1
+#define NAT_ENTRY2_CNT_EN_FLAG                  HSL_RW
+
+#define CNT_IDX
+#define NAT_ENTRY2_CNT_IDX_BOFFSET              24
+#define NAT_ENTRY2_CNT_IDX_BLEN                 3
+#define NAT_ENTRY2_CNT_IDX_FLAG                 HSL_RW
+
+#define PRV_IPADDR1
+#define NAT_ENTRY2_PRV_IPADDR1_BOFFSET          0
+#define NAT_ENTRY2_PRV_IPADDR1_BLEN             24
+#define NAT_ENTRY2_PRV_IPADDR1_FLAG             HSL_RW
+
+
+#define NAT_ENTRY3
+#define NAT_ENTRY3_OFFSET                       0x0e8c
+#define NAT_ENTRY3_E_LENGTH                     4
+#define NAT_ENTRY3_E_OFFSET                     0x0
+#define NAT_ENTRY3_NR_E                         1
+
+#define VRF_ID
+#define NAT_ENTRY3_VRF_ID_BOFFSET               4
+#define NAT_ENTRY3_VRF_ID_BLEN                  3
+#define NAT_ENTRY3_VRF_ID_FLAG                  HSL_RW
+
+#define ENTRY_VALID
+#define NAT_ENTRY3_ENTRY_VALID_BOFFSET          3
+#define NAT_ENTRY3_ENTRY_VALID_BLEN             1
+#define NAT_ENTRY3_ENTRY_VALID_FLAG             HSL_RW
+
+#define PORT_EN
+#define NAT_ENTRY3_PORT_EN_BOFFSET              2
+#define NAT_ENTRY3_PORT_EN_BLEN                 1
+#define NAT_ENTRY3_PORT_EN_FLAG                 HSL_RW
+
+#define PRO_TYP
+#define NAT_ENTRY3_PRO_TYP_BOFFSET              0
+#define NAT_ENTRY3_PRO_TYP_BLEN                 2
+#define NAT_ENTRY3_PRO_TYP_FLAG                 HSL_RW
+
+
+#define NAPT_ENTRY0
+#define NAPT_ENTRY0_OFFSET                       0x0e80
+#define NAPT_ENTRY0_E_LENGTH                     4
+#define NAPT_ENTRY0_E_OFFSET                     0x0
+#define NAPT_ENTRY0_NR_E                         1
+
+#define DST_IPADDR
+#define NAPT_ENTRY0_DST_IPADDR_BOFFSET           0
+#define NAPT_ENTRY0_DST_IPADDR_BLEN              32
+#define NAPT_ENTRY0_DST_IPADDR_FLAG              HSL_RW
+
+
+#define NAPT_ENTRY1
+#define NAPT_ENTRY1_OFFSET                       0x0e84
+#define NAPT_ENTRY1_E_LENGTH                     4
+#define NAPT_ENTRY1_E_OFFSET                     0x0
+#define NAPT_ENTRY1_NR_E                         1
+
+#define SRC_PORT
+#define NAPT_ENTRY1_SRC_PORT_BOFFSET            16
+#define NAPT_ENTRY1_SRC_PORT_BLEN              16
+#define NAPT_ENTRY1_SRC_PORT_FLAG              HSL_RW
+
+#define DST_PORT
+#define NAPT_ENTRY1_DST_PORT_BOFFSET           0
+#define NAPT_ENTRY1_DST_PORT_BLEN              16
+#define NAPT_ENTRY1_DST_PORT_FLAG              HSL_RW
+
+
+#define NAPT_ENTRY2
+#define NAPT_ENTRY2_OFFSET                       0x0e88
+#define NAPT_ENTRY2_E_LENGTH                     4
+#define NAPT_ENTRY2_E_OFFSET                     0x0
+#define NAPT_ENTRY2_NR_E                         1
+
+#define SRC_IPADDR0
+#define NAPT_ENTRY2_SRC_IPADDR0_BOFFSET           20
+#define NAPT_ENTRY2_SRC_IPADDR0_BLEN              12
+#define NAPT_ENTRY2_SRC_IPADDR0_FLAG              HSL_RW
+
+#define TRANS_IPADDR
+#define NAPT_ENTRY2_TRANS_IPADDR_BOFFSET           16
+#define NAPT_ENTRY2_TRANS_IPADDR_BLEN              4
+#define NAPT_ENTRY2_TRANS_IPADDR_FLAG              HSL_RW
+
+#define TRANS_PORT
+#define NAPT_ENTRY2_TRANS_PORT_BOFFSET           0
+#define NAPT_ENTRY2_TRANS_PORT_BLEN              16
+#define NAPT_ENTRY2_TRANS_PORT_FLAG              HSL_RW
+
+
+#define NAPT_ENTRY3
+#define NAPT_ENTRY3_OFFSET                       0x0e8c
+#define NAPT_ENTRY3_E_LENGTH                     4
+#define NAPT_ENTRY3_E_OFFSET                     0x0
+#define NAPT_ENTRY3_NR_E                         1
+
+#define PRIORITY_EN
+#define NAPT_ENTRY3_PRIORITY_EN_BOFFSET          31
+#define NAPT_ENTRY3_PRIORITY_EN_BLEN             1
+#define NAPT_ENTRY3_PRIORITY_EN_FLAG             HSL_RW
+
+#define PRIORITY_VAL
+#define NAPT_ENTRY3_PRIORITY_VAL_BOFFSET         28
+#define NAPT_ENTRY3_PRIORITY_VAL_BLEN            3
+#define NAPT_ENTRY3_PRIORITY_VAL_FLAG            HSL_RW
+
+#define CNT_EN
+#define NAPT_ENTRY3_CNT_EN_BOFFSET               27
+#define NAPT_ENTRY3_CNT_EN_BLEN                  1
+#define NAPT_ENTRY3_CNT_EN_FLAG                  HSL_RW
+
+#define CNT_IDX
+#define NAPT_ENTRY3_CNT_IDX_BOFFSET              24
+#define NAPT_ENTRY3_CNT_IDX_BLEN                 3
+#define NAPT_ENTRY3_CNT_IDX_FLAG                 HSL_RW
+
+#define PROT_TYP
+#define NAPT_ENTRY3_PROT_TYP_BOFFSET             22
+#define NAPT_ENTRY3_PROT_TYP_BLEN                2
+#define NAPT_ENTRY3_PROT_TYP_FLAG                HSL_RW
+
+#define ACTION
+#define NAPT_ENTRY3_ACTION_BOFFSET               20
+#define NAPT_ENTRY3_ACTION_BLEN                  2
+#define NAPT_ENTRY3_ACTION_FLAG                  HSL_RW
+
+#define SRC_IPADDR1
+#define NAPT_ENTRY3_SRC_IPADDR1_BOFFSET           0
+#define NAPT_ENTRY3_SRC_IPADDR1_BLEN              20
+#define NAPT_ENTRY3_SRC_IPADDR1_FLAG              HSL_RW
+
+
+#define NAPT_ENTRY4
+#define NAPT_ENTRY4_OFFSET                       0x0e90
+#define NAPT_ENTRY4_E_LENGTH                     4
+#define NAPT_ENTRY4_E_OFFSET                     0x0
+#define NAPT_ENTRY4_NR_E                         1
+
+#define LOAD_BALANCE
+#define NAPT_ENTRY4_LOAD_BALANCE_BOFFSET         19
+#define NAPT_ENTRY4_LOAD_BALANCE_BLEN            3
+#define NAPT_ENTRY4_LOAD_BALANCE_FLAG            HSL_RW
+
+#define FLOW_COOKIE
+#define NAPT_ENTRY4_FLOW_COOKIE_BOFFSET          8
+#define NAPT_ENTRY4_FLOW_COOKIE_BLEN             11
+#define NAPT_ENTRY4_FLOW_COOKIE_FLAG             HSL_RW
+
+#define VRF_ID
+#define NAPT_ENTRY4_VRF_ID_BOFFSET               5
+#define NAPT_ENTRY4_VRF_ID_BLEN                  3
+#define NAPT_ENTRY4_VRF_ID_FLAG                  HSL_RW
+
+#define AGE_SYNC
+#define NAPT_ENTRY4_AGE_SYNC_BOFFSET             4
+#define NAPT_ENTRY4_AGE_SYNC_BLEN                1
+#define NAPT_ENTRY4_AGE_SYNC_FLAG                HSL_RO
+
+#define AGE_FLAG
+#define NAPT_ENTRY4_AGE_FLAG_BOFFSET             0
+#define NAPT_ENTRY4_AGE_FLAG_BLEN                4
+#define NAPT_ENTRY4_AGE_FLAG_FLAG                HSL_RW
+
+
+#define ROUTER_CTRL
+#define ROUTER_CTRL_OFFSET                       0x0e00
+#define ROUTER_CTRL_E_LENGTH                     4
+#define ROUTER_CTRL_E_OFFSET                     0x0
+#define ROUTER_CTRL_NR_E                         1
+
+#define ARP_LEARN_MODE
+#define ROUTER_CTRL_ARP_LEARN_MODE_BOFFSET       19
+#define ROUTER_CTRL_ARP_LEARN_MODE_BLEN          1
+#define ROUTER_CTRL_ARP_LEARN_MODE_FLAG          HSL_RW
+
+#define GLB_LOCKTIME
+#define ROUTER_CTRL_GLB_LOCKTIME_BOFFSET       16
+#define ROUTER_CTRL_GLB_LOCKTIME_BLEN          2
+#define ROUTER_CTRL_GLB_LOCKTIME_FLAG          HSL_RW
+
+#define ARP_AGE_TIME
+#define ROUTER_CTRL_ARP_AGE_TIME_BOFFSET         8
+#define ROUTER_CTRL_ARP_AGE_TIME_BLEN            8
+#define ROUTER_CTRL_ARP_AGE_TIME_FLAG            HSL_RW
+
+#define WCMP_HAHS_DP
+#define ROUTER_CTRL_WCMP_HAHS_DP_BOFFSET         7
+#define ROUTER_CTRL_WCMP_HAHS_DP_BLEN            1
+#define ROUTER_CTRL_WCMP_HAHS_DP_FLAG            HSL_RW
+
+#define WCMP_HAHS_DIP
+#define ROUTER_CTRL_WCMP_HAHS_DIP_BOFFSET        6
+#define ROUTER_CTRL_WCMP_HAHS_DIP_BLEN           1
+#define ROUTER_CTRL_WCMP_HAHS_DIP_FLAG           HSL_RW
+
+#define WCMP_HAHS_SP
+#define ROUTER_CTRL_WCMP_HAHS_SP_BOFFSET         5
+#define ROUTER_CTRL_WCMP_HAHS_SP_BLEN            1
+#define ROUTER_CTRL_WCMP_HAHS_SP_FLAG            HSL_RW
+
+#define WCMP_HAHS_SIP
+#define ROUTER_CTRL_WCMP_HAHS_SIP_BOFFSET        4
+#define ROUTER_CTRL_WCMP_HAHS_SIP_BLEN           1
+#define ROUTER_CTRL_WCMP_HAHS_SIP_FLAG           HSL_RW
+
+#define ARP_AGE_MODE
+#define ROUTER_CTRL_ARP_AGE_MODE_BOFFSET         1
+#define ROUTER_CTRL_ARP_AGE_MODE_BLEN            1
+#define ROUTER_CTRL_ARP_AGE_MODE_FLAG            HSL_RW
+
+#define ROUTER_EN
+#define ROUTER_CTRL_ROUTER_EN_BOFFSET            0
+#define ROUTER_CTRL_ROUTER_EN_BLEN               1
+#define ROUTER_CTRL_ROUTER_EN_FLAG               HSL_RW
+
+
+
+
+#define ROUTER_PTCTRL0
+#define ROUTER_PTCTRL0_OFFSET                       0x0e04
+#define ROUTER_PTCTRL0_E_LENGTH                     4
+#define ROUTER_PTCTRL0_E_OFFSET                     0x0
+#define ROUTER_PTCTRL0_NR_E                         1
+
+
+
+
+#define ROUTER_PTCTRL1
+#define ROUTER_PTCTRL1_OFFSET                       0x0e08
+#define ROUTER_PTCTRL1_E_LENGTH                     4
+#define ROUTER_PTCTRL1_E_OFFSET                     0x0
+#define ROUTER_PTCTRL1_NR_E                         1
+
+
+
+#define ROUTER_PTCTRL2
+#define ROUTER_PTCTRL2_OFFSET                       0x0e0c
+#define ROUTER_PTCTRL2_E_LENGTH                     4
+#define ROUTER_PTCTRL2_E_OFFSET                     0x0
+#define ROUTER_PTCTRL2_NR_E                         1
+
+#define ARP_PT_UP
+#define ROUTER_PTCTRL2_ARP_PT_UP_BOFFSET               16
+#define ROUTER_PTCTRL2_ARP_PT_UP_BLEN                  7
+#define ROUTER_PTCTRL2_ARP_PT_UP_FLAG                  HSL_RW
+
+#define ARP_LEARN_ACK
+#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET               8
+#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BLEN                  7
+#define ROUTER_PTCTRL2_ARP_LEARN_ACK_FLAG                  HSL_RW
+
+#define ARP_LEARN_REQ
+#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BOFFSET               0
+#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BLEN                  7
+#define ROUTER_PTCTRL2_ARP_LEARN_REQ_FLAG                  HSL_RW
+
+
+
+
+#define NAT_CTRL
+#define NAT_CTRL_OFFSET                       0x0e38
+#define NAT_CTRL_E_LENGTH                     4
+#define NAT_CTRL_E_OFFSET                     0x0
+#define NAT_CTRL_NR_E                         1
+
+#define NAT_HASH_MODE
+#define NAT_CTRL_NAT_HASH_MODE_BOFFSET        5
+#define NAT_CTRL_NAT_HASH_MODE_BLEN           2
+#define NAT_CTRL_NAT_HASH_MODE_FLAG           HSL_RW
+
+#define NAPT_OVERRIDE
+#define NAT_CTRL_NAPT_OVERRIDE_BOFFSET        4
+#define NAT_CTRL_NAPT_OVERRIDE_BLEN           1
+#define NAT_CTRL_NAPT_OVERRIDE_FLAG           HSL_RW
+
+#define NAPT_MODE
+#define NAT_CTRL_NAPT_MODE_BOFFSET            2
+#define NAT_CTRL_NAPT_MODE_BLEN               2
+#define NAT_CTRL_NAPT_MODE_FLAG               HSL_RW
+
+#define NAT_EN
+#define NAT_CTRL_NAT_EN_BOFFSET               1
+#define NAT_CTRL_NAT_EN_BLEN                  1
+#define NAT_CTRL_NAT_EN_FLAG                  HSL_RW
+
+#define NAPT_EN
+#define NAT_CTRL_NAPT_EN_BOFFSET              0
+#define NAT_CTRL_NAPT_EN_BLEN                 1
+#define NAT_CTRL_NAPT_EN_FLAG                 HSL_RW
+
+
+
+#define FlOW_CMD_CTL
+#define FlOW_CMD_CTL_OFFSET                       0x0ea0
+#define FlOW_CMD_CTL_E_LENGTH                     4
+#define FlOW_CMD_CTL_E_OFFSET                     0x4
+#define FlOW_CMD_CTL_NR_E                         8
+
+#define LAN_2_LAN_DEFAULT
+#define FlOW_CMD_CTL_LAN_2_LAN_DEFAULT_BOFFSET        26
+#define FlOW_CMD_CTL_LAN_2_LAN_DEFAULT_BLEN           2
+#define FlOW_CMD_CTL_LAN_2_LAN_DEFAULT_FLAG           HSL_RW
+
+#define WAN_2_LAN_DEFAULT
+#define FlOW_CMD_CTL_WAN_2_LAN_DEFAULT_BOFFSET        24
+#define FlOW_CMD_CTL_WAN_2_LAN_DEFAULT_BLEN           2
+#define FlOW_CMD_CTL_WAN_2_LAN_DEFAULT_FLAG           HSL_RW
+
+#define LAN_2_WAN_DEFAULT
+#define FlOW_CMD_CTL_LAN_2_WAN_DEFAULT_BOFFSET            22
+#define FlOW_CMD_CTL_LAN_2_WAN_DEFAULT_BLEN               2
+#define FlOW_CMD_CTL_LAN_2_WAN_DEFAULT_FLAG               HSL_RW
+
+#define WAN_2_WAN_DEFAULT
+#define FlOW_CMD_CTL_WAN_2_WAN_DEFAULT_BOFFSET               20
+#define FlOW_CMD_CTL_WAN_2_WAN_DEFAULT_BLEN                  2
+#define FlOW_CMD_CTL_WAN_2_WAN_DEFAULT_FLAG                  HSL_RW
+
+
+#define FlOW_RT_CMD_CTL
+#define FlOW_RT_CMD_CTL_OFFSET                       0x0ec0
+#define FlOW_RT_CMD_CTL_E_LENGTH                     4
+#define FlOW_RT_CMD_CTL_E_OFFSET                     0x4
+#define FlOW_RT_CMD_CTL_NR_E                         8
+
+#define LAN_2_LAN_DEFAULT
+#define FlOW_RT_CMD_CTL_LAN_2_LAN_DEFAULT_BOFFSET        26
+#define FlOW_RT_CMD_CTL_LAN_2_LAN_DEFAULT_BLEN           2
+#define FlOW_RT_CMD_CTL_LAN_2_LAN_DEFAULT_FLAG           HSL_RW
+
+#define WAN_2_LAN_DEFAULT
+#define FlOW_RT_CMD_CTL_WAN_2_LAN_DEFAULT_BOFFSET        24
+#define FlOW_RT_CMD_CTL_WAN_2_LAN_DEFAULT_BLEN           2
+#define FlOW_RT_CMD_CTL_WAN_2_LAN_DEFAULT_FLAG           HSL_RW
+
+#define LAN_2_WAN_DEFAULT
+#define FlOW_RT_CMD_CTL_LAN_2_WAN_DEFAULT_BOFFSET            22
+#define FlOW_RT_CMD_CTL_LAN_2_WAN_DEFAULT_BLEN               2
+#define FlOW_RT_CMD_CTL_LAN_2_WAN_DEFAULT_FLAG               HSL_RW
+
+#define WAN_2_WAN_DEFAULT
+#define FlOW_RT_CMD_CTL_WAN_2_WAN_DEFAULT_BOFFSET               20
+#define FlOW_RT_CMD_CTL_WAN_2_WAN_DEFAULT_BLEN                  2
+#define FlOW_RT_CMD_CTL_WAN_2_WAN_DEFAULT_FLAG                  HSL_RW
+
+
+
+#define PRV_BASEADDR
+#define PRV_BASEADDR_OFFSET                       0x0e5c
+#define PRV_BASEADDR_E_LENGTH                     4
+#define PRV_BASEADDR_E_OFFSET                     0x0
+#define PRV_BASEADDR_NR_E                         1
+
+#define IP4_ADDR
+#define PRV_BASEADDR_IP4_ADDR_BOFFSET             0
+#define PRV_BASEADDR_IP4_ADDR_BLEN                20
+#define PRV_BASEADDR_IP4_ADDR_FLAG                HSL_RW
+
+
+
+
+#define PRVIP_ADDR
+#define PRVIP_ADDR_OFFSET                         0x0470
+#define PRVIP_ADDR_E_LENGTH                       4
+#define PRVIP_ADDR_E_OFFSET                       0x0
+#define PRVIP_ADDR_NR_E                           1
+
+#define IP4_BASEADDR
+#define PRVIP_ADDR_IP4_BASEADDR_BOFFSET           0
+#define PRVIP_ADDR_IP4_BASEADDR_BLEN              32
+#define PRVIP_ADDR_IP4_BASEADDR_FLAG              HSL_RW
+
+
+#define PRVIP_MASK
+#define PRVIP_MASK_OFFSET                         0x0474
+#define PRVIP_MASK_E_LENGTH                       4
+#define PRVIP_MASK_E_OFFSET                       0x0
+#define PRVIP_MASK_NR_E                           1
+
+#define IP4_BASEMASK
+#define PRVIP_MASK_IP4_BASEMASK_BOFFSET           0
+#define PRVIP_MASK_IP4_BASEMASK_BLEN              32
+#define PRVIP_MASK_IP4_BASEMASK_FLAG              HSL_RW
+
+
+
+
+#define PUB_ADDR0
+#define PUB_ADDR0_OFFSET                       0x5aa00
+#define PUB_ADDR0_E_LENGTH                     4
+#define PUB_ADDR0_E_OFFSET                     0x0
+#define PUB_ADDR0_NR_E                         1
+
+#define IP4_ADDR
+#define PUB_ADDR0_IP4_ADDR_BOFFSET             0
+#define PUB_ADDR0_IP4_ADDR_BLEN                32
+#define PUB_ADDR0_IP4_ADDR_FLAG                HSL_RW
+
+
+#define PUB_ADDR1
+#define PUB_ADDR1_OFFSET                       0x5aa04
+#define PUB_ADDR1_E_LENGTH                     4
+#define PUB_ADDR1_E_OFFSET                     0x0
+#define PUB_ADDR1_NR_E                         1
+
+#define ADDR_VALID
+#define PUB_ADDR1_ADDR_VALID_BOFFSET           0
+#define PUB_ADDR1_ADDR_VALID_BLEN              1
+#define PUB_ADDR1_ADDR_VALID_FLAG              HSL_RW
+
+
+
+
+#define INTF_ADDR_ENTRY0
+#define INTF_ADDR_ENTRY0_OFFSET                     0x5aa00
+#define INTF_ADDR_ENTRY0_E_LENGTH                   4
+#define INTF_ADDR_ENTRY0_E_OFFSET                   0x0
+#define INTF_ADDR_ENTRY0_NR_E                       8
+
+#define MAC_ADDR2
+#define INTF_ADDR_ENTRY0_MAC_ADDR2_BOFFSET          24
+#define INTF_ADDR_ENTRY0_MAC_ADDR2_BLEN             8
+#define INTF_ADDR_ENTRY0_MAC_ADDR2_FLAG             HSL_RW
+
+#define MAC_ADDR3
+#define INTF_ADDR_ENTRY0_MAC_ADDR3_BOFFSET          16
+#define INTF_ADDR_ENTRY0_MAC_ADDR3_BLEN             8
+#define INTF_ADDR_ENTRY0_MAC_ADDR3_FLAG             HSL_RW
+
+#define MAC_ADDR4
+#define INTF_ADDR_ENTRY0_MAC_ADDR4_BOFFSET          8
+#define INTF_ADDR_ENTRY0_MAC_ADDR4_BLEN             8
+#define INTF_ADDR_ENTRY0_MAC_ADDR4_FLAG             HSL_RW
+
+#define MAC_ADDR5
+#define INTF_ADDR_ENTRY0_MAC_ADDR5_BOFFSET          0
+#define INTF_ADDR_ENTRY0_MAC_ADDR5_BLEN             8
+#define INTF_ADDR_ENTRY0_MAC_ADDR5_FLAG             HSL_RW
+
+
+#define INTF_ADDR_ENTRY1
+#define INTF_ADDR_ENTRY1_OFFSET                     0x5aa04
+#define INTF_ADDR_ENTRY1_E_LENGTH                   4
+#define INTF_ADDR_ENTRY1_E_OFFSET                   0x0
+#define INTF_ADDR_ENTRY1_NR_E                       8
+
+#define VID_HIGH0
+#define INTF_ADDR_ENTRY1_VID_HIGH0_BOFFSET          28
+#define INTF_ADDR_ENTRY1_VID_HIGH0_BLEN             4
+#define INTF_ADDR_ENTRY1_VID_HIGH0_FLAG             HSL_RW
+
+#define VID_LOW
+#define INTF_ADDR_ENTRY1_VID_LOW_BOFFSET            16
+#define INTF_ADDR_ENTRY1_VID_LOW_BLEN               12
+#define INTF_ADDR_ENTRY1_VID_LOW_FLAG               HSL_RW
+
+#define MAC_ADDR0
+#define INTF_ADDR_ENTRY1_MAC_ADDR0_BOFFSET          8
+#define INTF_ADDR_ENTRY1_MAC_ADDR0_BLEN             8
+#define INTF_ADDR_ENTRY1_MAC_ADDR0_FLAG             HSL_RW
+
+#define MAC_ADDR1
+#define INTF_ADDR_ENTRY1_MAC_ADDR1_BOFFSET          0
+#define INTF_ADDR_ENTRY1_MAC_ADDR1_BLEN             8
+#define INTF_ADDR_ENTRY1_MAC_ADDR1_FLAG             HSL_RW
+
+
+#define INTF_ADDR_ENTRY2
+#define INTF_ADDR_ENTRY2_OFFSET                     0x5aa08
+#define INTF_ADDR_ENTRY2_E_LENGTH                   4
+#define INTF_ADDR_ENTRY2_E_OFFSET                   0x0
+#define INTF_ADDR_ENTRY2_NR_E                       8
+
+#define VRF_ID
+#define INTF_ADDR_ENTRY2_VRF_ID_BOFFSET          10
+#define INTF_ADDR_ENTRY2_VRF_ID_BLEN             3
+#define INTF_ADDR_ENTRY2_VRF_ID_FLAG             HSL_RW
+
+#define IP6_ROUTE
+#define INTF_ADDR_ENTRY2_IP6_ROUTE_BOFFSET          9
+#define INTF_ADDR_ENTRY2_IP6_ROUTE_BLEN             1
+#define INTF_ADDR_ENTRY2_IP6_ROUTE_FLAG             HSL_RW
+
+#define IP4_ROUTE
+#define INTF_ADDR_ENTRY2_IP4_ROUTE_BOFFSET          8
+#define INTF_ADDR_ENTRY2_IP4_ROUTE_BLEN             1
+#define INTF_ADDR_ENTRY2_IP4_ROUTE_FLAG             HSL_RW
+
+#define VID_HIGH1
+#define INTF_ADDR_ENTRY2_VID_HIGH1_BOFFSET          0
+#define INTF_ADDR_ENTRY2_VID_HIGH1_BLEN             8
+#define INTF_ADDR_ENTRY2_VID_HIGH1_FLAG             HSL_RW
+
+
+#define IP4_DEFAULT_ROUTE_ENTRY
+#define IP4_DEFAULT_ROUTE_ENTRY_OFFSET                     0x004c4
+#define IP4_DEFAULT_ROUTE_ENTRY_E_LENGTH                   4
+#define IP4_DEFAULT_ROUTE_ENTRY_E_OFFSET                   0x0
+#define IP4_DEFAULT_ROUTE_ENTRY_NR_E                       8
+
+#define VALID
+#define IP4_DEFAULT_ROUTE_ENTRY_VALID_BOFFSET          11
+#define IP4_DEFAULT_ROUTE_ENTRY_VALID_BLEN             1
+#define IP4_DEFAULT_ROUTE_ENTRY_VALID_FLAG             HSL_RW
+
+#define VRF
+#define IP4_DEFAULT_ROUTE_ENTRY_VRF_BOFFSET          8
+#define IP4_DEFAULT_ROUTE_ENTRY_VRF_BLEN             3
+#define IP4_DEFAULT_ROUTE_ENTRY_VRF_FLAG             HSL_RW
+
+#define ARP_WCMP_TYPE
+#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_BOFFSET          7
+#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_BLEN             1
+#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_FLAG             HSL_RW
+
+#define ARP_WCMP_INDEX
+#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_BOFFSET          0
+#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_BLEN             7
+#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_FLAG             HSL_RW
+
+#define IP6_DEFAULT_ROUTE_ENTRY
+#define IP6_DEFAULT_ROUTE_ENTRY_OFFSET                     0x004c4
+#define IP6_DEFAULT_ROUTE_ENTRY_E_LENGTH                   4
+#define IP6_DEFAULT_ROUTE_ENTRY_E_OFFSET                   0x0
+#define IP6_DEFAULT_ROUTE_ENTRY_NR_E                       8
+
+#define VALID
+#define IP6_DEFAULT_ROUTE_ENTRY_VALID_BOFFSET          11
+#define IP6_DEFAULT_ROUTE_ENTRY_VALID_BLEN             1
+#define IP6_DEFAULT_ROUTE_ENTRY_VALID_FLAG             HSL_RW
+
+#define VRF
+#define IP6_DEFAULT_ROUTE_ENTRY_VRF_BOFFSET          8
+#define IP6_DEFAULT_ROUTE_ENTRY_VRF_BLEN             3
+#define IP6_DEFAULT_ROUTE_ENTRY_VRF_FLAG             HSL_RW
+
+#define ARP_WCMP_TYPE
+#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_BOFFSET          7
+#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_BLEN             1
+#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_FLAG             HSL_RW
+
+#define ARP_WCMP_INDEX
+#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_BOFFSET          0
+#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_BLEN             7
+#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_FLAG             HSL_RW
+
+#define IP4_HOST_ROUTE_ENTRY0
+#define IP4_HOST_ROUTE_ENTRY0_OFFSET                     0x5b000
+#define IP4_HOST_ROUTE_ENTRY0_E_LENGTH                   4
+#define IP4_HOST_ROUTE_ENTRY0_E_OFFSET                   0x0
+#define IP4_HOST_ROUTE_ENTRY0_NR_E                       16
+
+#define IP4_ADDRL
+#define IP4_HOST_ROUTE_ENTRY0_IP4_ADDRL_BOFFSET          5
+#define IP4_HOST_ROUTE_ENTRY0_IP4_ADDRL_BLEN             27
+#define IP4_HOST_ROUTE_ENTRY0_IP4_ADDRL_FLAG             HSL_RW
+
+#define PREFIX_LENGTH
+#define IP4_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_BOFFSET     0
+#define IP4_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_BLEN        5
+#define IP4_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_FLAG        HSL_RW
+
+#define IP4_HOST_ROUTE_ENTRY1
+#define IP4_HOST_ROUTE_ENTRY1_OFFSET                     0x5b004
+#define IP4_HOST_ROUTE_ENTRY1_E_LENGTH                   4
+#define IP4_HOST_ROUTE_ENTRY1_E_OFFSET                   0x0
+#define IP4_HOST_ROUTE_ENTRY1_NR_E                       16
+
+#define VALID
+#define IP4_HOST_ROUTE_ENTRY1_VALID_BOFFSET          8
+#define IP4_HOST_ROUTE_ENTRY1_VALID_BLEN             1
+#define IP4_HOST_ROUTE_ENTRY1_VALID_FLAG             HSL_RW
+
+#define VRF
+#define IP4_HOST_ROUTE_ENTRY1_VRF_BOFFSET          5
+#define IP4_HOST_ROUTE_ENTRY1_VRF_BLEN             3
+#define IP4_HOST_ROUTE_ENTRY1_VRF_FLAG             HSL_RW
+
+#define IP4_ADDRH
+#define IP4_HOST_ROUTE_ENTRY1_IP4_ADDRH_BOFFSET     0
+#define IP4_HOST_ROUTE_ENTRY1_IP4_ADDRH_BLEN        5
+#define IP4_HOST_ROUTE_ENTRY1_IP4_ADDRH_FLAG        HSL_RW
+
+#define IP6_HOST_ROUTE_ENTRY0
+#define IP6_HOST_ROUTE_ENTRY0_OFFSET                     0x5b100
+#define IP6_HOST_ROUTE_ENTRY0_E_LENGTH                   4
+#define IP6_HOST_ROUTE_ENTRY0_E_OFFSET                   0x0
+#define IP6_HOST_ROUTE_ENTRY0_NR_E                       16
+
+#define PREFIX_LENGTH
+#define IP6_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_BOFFSET          0
+#define IP6_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_BLEN             7
+#define IP6_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_FLAG             HSL_RW
+
+#define IP6_ADDR0L
+#define IP6_HOST_ROUTE_ENTRY0_IP6_ADDR0L_BOFFSET          7
+#define IP6_HOST_ROUTE_ENTRY0_IP6_ADDR0L_BLEN             25
+#define IP6_HOST_ROUTE_ENTRY0_IP6_ADDR0L_FLAG             HSL_RW
+
+#define IP6_HOST_ROUTE_ENTRY1
+#define IP6_HOST_ROUTE_ENTRY1_OFFSET                     0x5b104
+#define IP6_HOST_ROUTE_ENTRY1_E_LENGTH                   4
+#define IP6_HOST_ROUTE_ENTRY1_E_OFFSET                   0x0
+#define IP6_HOST_ROUTE_ENTRY1_NR_E                       16
+
+#define IP6_ADDR0H
+#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR0H_BOFFSET          0
+#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR0H_BLEN             7
+#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR0H_FLAG             HSL_RW
+
+#define IP6_ADDR1L
+#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR1L_BOFFSET          7
+#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR1L_BLEN             25
+#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR1L_FLAG             HSL_RW
+
+#define IP6_HOST_ROUTE_ENTRY2
+#define IP6_HOST_ROUTE_ENTRY2_OFFSET                     0x5b108
+#define IP6_HOST_ROUTE_ENTRY2_E_LENGTH                   4
+#define IP6_HOST_ROUTE_ENTRY2_E_OFFSET                   0x0
+#define IP6_HOST_ROUTE_ENTRY2_NR_E                       16
+
+#define IP6_ADDR1H
+#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR1H_BOFFSET          0
+#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR1H_BLEN             7
+#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR1H_FLAG             HSL_RW
+
+#define IP6_ADDR2L
+#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR2L_BOFFSET          7
+#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR2L_BLEN             25
+#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR2L_FLAG             HSL_RW
+
+#define IP6_HOST_ROUTE_ENTRY3
+#define IP6_HOST_ROUTE_ENTRY3_OFFSET                     0x5b10c
+#define IP6_HOST_ROUTE_ENTRY3_E_LENGTH                   4
+#define IP6_HOST_ROUTE_ENTRY3_E_OFFSET                   0x0
+#define IP6_HOST_ROUTE_ENTRY3_NR_E                       16
+
+#define IP6_ADDR2H
+#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR2H_BOFFSET          0
+#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR2H_BLEN             7
+#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR2H_FLAG             HSL_RW
+
+#define IP6_ADDR3L
+#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR3L_BOFFSET          7
+#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR3L_BLEN             25
+#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR3L_FLAG             HSL_RW
+
+#define IP6_HOST_ROUTE_ENTRY4
+#define IP6_HOST_ROUTE_ENTRY4_OFFSET                     0x5b110
+#define IP6_HOST_ROUTE_ENTRY4_E_LENGTH                   4
+#define IP6_HOST_ROUTE_ENTRY4_E_OFFSET                   0x0
+#define IP6_HOST_ROUTE_ENTRY4_NR_E                       16
+
+#define IP6_ADDR3H
+#define IP6_HOST_ROUTE_ENTRY4_IP6_ADDR3H_BOFFSET          0
+#define IP6_HOST_ROUTE_ENTRY4_IP6_ADDR3H_BLEN             7
+#define IP6_HOST_ROUTE_ENTRY4_IP6_ADDR3H_FLAG             HSL_RW
+
+#define VRF
+#define IP6_HOST_ROUTE_ENTRY4_VRF_BOFFSET          7
+#define IP6_HOST_ROUTE_ENTRY4_VRF_BLEN             3
+#define IP6_HOST_ROUTE_ENTRY4_VRF_FLAG             HSL_RW
+
+#define VALID
+#define IP6_HOST_ROUTE_ENTRY4_VALID_BOFFSET          10
+#define IP6_HOST_ROUTE_ENTRY4_VALID_BLEN             1
+#define IP6_HOST_ROUTE_ENTRY4_VALID_FLAG             HSL_RW
+
+
+    /* Port Shaper Register0 */
+#define EG_SHAPER0
+#define EG_SHAPER0_OFFSET         0x0890
+#define EG_SHAPER0_E_LENGTH       4
+#define EG_SHAPER0_E_OFFSET       0x0020
+#define EG_SHAPER0_NR_E           7
+
+#define EG_Q1_CIR
+#define EG_SHAPER0_EG_Q1_CIR_BOFFSET          16
+#define EG_SHAPER0_EG_Q1_CIR_BLEN             15
+#define EG_SHAPER0_EG_Q1_CIR_FLAG             HSL_RW
+
+#define EG_Q0_CIR
+#define EG_SHAPER0_EG_Q0_CIR_BOFFSET          0
+#define EG_SHAPER0_EG_Q0_CIR_BLEN             15
+#define EG_SHAPER0_EG_Q0_CIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register1 */
+#define EG_SHAPER1
+#define EG_SHAPER1_OFFSET         0x0894
+#define EG_SHAPER1_E_LENGTH       4
+#define EG_SHAPER1_E_OFFSET       0x0020
+#define EG_SHAPER1_NR_E           7
+
+#define EG_Q3_CIR
+#define EG_SHAPER1_EG_Q3_CIR_BOFFSET          16
+#define EG_SHAPER1_EG_Q3_CIR_BLEN             15
+#define EG_SHAPER1_EG_Q3_CIR_FLAG             HSL_RW
+
+#define EG_Q2_CIR
+#define EG_SHAPER1_EG_Q2_CIR_BOFFSET          0
+#define EG_SHAPER1_EG_Q2_CIR_BLEN             15
+#define EG_SHAPER1_EG_Q2_CIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register2 */
+#define EG_SHAPER2
+#define EG_SHAPER2_OFFSET         0x0898
+#define EG_SHAPER2_E_LENGTH       4
+#define EG_SHAPER2_E_OFFSET       0x0020
+#define EG_SHAPER2_NR_E           7
+
+#define EG_Q5_CIR
+#define EG_SHAPER2_EG_Q5_CIR_BOFFSET          16
+#define EG_SHAPER2_EG_Q5_CIR_BLEN             15
+#define EG_SHAPER2_EG_Q5_CIR_FLAG             HSL_RW
+
+#define EG_Q4_CIR
+#define EG_SHAPER2_EG_Q4_CIR_BOFFSET          0
+#define EG_SHAPER2_EG_Q4_CIR_BLEN             15
+#define EG_SHAPER2_EG_Q4_CIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register3 */
+#define EG_SHAPER3
+#define EG_SHAPER3_OFFSET         0x089c
+#define EG_SHAPER3_E_LENGTH       4
+#define EG_SHAPER3_E_OFFSET       0x0020
+#define EG_SHAPER3_NR_E           7
+
+#define EG_Q1_EIR
+#define EG_SHAPER3_EG_Q1_EIR_BOFFSET          16
+#define EG_SHAPER3_EG_Q1_EIR_BLEN             15
+#define EG_SHAPER3_EG_Q1_EIR_FLAG             HSL_RW
+
+#define EG_Q0_EIR
+#define EG_SHAPER3_EG_Q0_EIR_BOFFSET          0
+#define EG_SHAPER3_EG_Q0_EIR_BLEN             15
+#define EG_SHAPER3_EG_Q0_EIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register4 */
+#define EG_SHAPER4
+#define EG_SHAPER4_OFFSET         0x08a0
+#define EG_SHAPER4_E_LENGTH       4
+#define EG_SHAPER4_E_OFFSET       0x0020
+#define EG_SHAPER4_NR_E           7
+
+#define EG_Q3_EIR
+#define EG_SHAPER4_EG_Q3_EIR_BOFFSET          16
+#define EG_SHAPER4_EG_Q3_EIR_BLEN             15
+#define EG_SHAPER4_EG_Q3_EIR_FLAG             HSL_RW
+
+#define EG_Q2_EIR
+#define EG_SHAPER4_EG_Q2_EIR_BOFFSET          0
+#define EG_SHAPER4_EG_Q2_EIR_BLEN             15
+#define EG_SHAPER4_EG_Q2_EIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register5 */
+#define EG_SHAPER5
+#define EG_SHAPER5_OFFSET         0x08a4
+#define EG_SHAPER5_E_LENGTH       4
+#define EG_SHAPER5_E_OFFSET       0x0020
+#define EG_SHAPER5_NR_E           7
+
+#define EG_Q5_EIR
+#define EG_SHAPER5_EG_Q5_EIR_BOFFSET          16
+#define EG_SHAPER5_EG_Q5_EIR_BLEN             15
+#define EG_SHAPER5_EG_Q5_EIR_FLAG             HSL_RW
+
+#define EG_Q4_EIR
+#define EG_SHAPER5_EG_Q4_EIR_BOFFSET          0
+#define EG_SHAPER5_EG_Q4_EIR_BLEN             15
+#define EG_SHAPER5_EG_Q4_EIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register6 */
+#define EG_SHAPER6
+#define EG_SHAPER6_OFFSET         0x08a8
+#define EG_SHAPER6_E_LENGTH       4
+#define EG_SHAPER6_E_OFFSET       0x0020
+#define EG_SHAPER6_NR_E           7
+
+#define EG_Q3_CBS
+#define EG_SHAPER6_EG_Q3_CBS_BOFFSET          28
+#define EG_SHAPER6_EG_Q3_CBS_BLEN             3
+#define EG_SHAPER6_EG_Q3_CBS_FLAG             HSL_RW
+
+#define EG_Q3_EBS
+#define EG_SHAPER6_EG_Q3_EBS_BOFFSET          24
+#define EG_SHAPER6_EG_Q3_EBS_BLEN             3
+#define EG_SHAPER6_EG_Q3_EBS_FLAG             HSL_RW
+
+#define EG_Q2_CBS
+#define EG_SHAPER6_EG_Q2_CBS_BOFFSET          20
+#define EG_SHAPER6_EG_Q2_CBS_BLEN             3
+#define EG_SHAPER6_EG_Q2_CBS_FLAG             HSL_RW
+
+#define EG_Q2_EBS
+#define EG_SHAPER6_EG_Q2_EBS_BOFFSET          16
+#define EG_SHAPER6_EG_Q2_EBS_BLEN             3
+#define EG_SHAPER6_EG_Q2_EBS_FLAG             HSL_RW
+
+#define EG_Q1_CBS
+#define EG_SHAPER6_EG_Q1_CBS_BOFFSET          12
+#define EG_SHAPER6_EG_Q1_CBS_BLEN             3
+#define EG_SHAPER6_EG_Q1_CBS_FLAG             HSL_RW
+
+#define EG_Q1_EBS
+#define EG_SHAPER6_EG_Q1_EBS_BOFFSET          8
+#define EG_SHAPER6_EG_Q1_EBS_BLEN             3
+#define EG_SHAPER6_EG_Q1_EBS_FLAG             HSL_RW
+
+#define EG_Q0_CBS
+#define EG_SHAPER6_EG_Q0_CBS_BOFFSET          4
+#define EG_SHAPER6_EG_Q0_CBS_BLEN             3
+#define EG_SHAPER6_EG_Q0_CBS_FLAG             HSL_RW
+
+#define EG_Q0_EBS
+#define EG_SHAPER6_EG_Q0_EBS_BOFFSET          0
+#define EG_SHAPER6_EG_Q0_EBS_BLEN             3
+#define EG_SHAPER6_EG_Q0_EBS_FLAG             HSL_RW
+
+
+    /* Port Shaper Register7 */
+#define EG_SHAPER7
+#define EG_SHAPER7_OFFSET         0x08ac
+#define EG_SHAPER7_E_LENGTH       4
+#define EG_SHAPER7_E_OFFSET       0x0020
+#define EG_SHAPER7_NR_E           7
+
+#define EG_Q5_CBS
+#define EG_SHAPER7_EG_Q5_CBS_BOFFSET          28
+#define EG_SHAPER7_EG_Q5_CBS_BLEN             3
+#define EG_SHAPER7_EG_Q5_CBS_FLAG             HSL_RW
+
+#define EG_Q5_EBS
+#define EG_SHAPER7_EG_Q5_EBS_BOFFSET          24
+#define EG_SHAPER7_EG_Q5_EBS_BLEN             3
+#define EG_SHAPER7_EG_Q5_EBS_FLAG             HSL_RW
+
+#define EG_Q4_CBS
+#define EG_SHAPER7_EG_Q4_CBS_BOFFSET          20
+#define EG_SHAPER7_EG_Q4_CBS_BLEN             3
+#define EG_SHAPER7_EG_Q4_CBS_FLAG             HSL_RW
+
+#define EG_Q4_EBS
+#define EG_SHAPER7_EG_Q4_EBS_BOFFSET          16
+#define EG_SHAPER7_EG_Q4_EBS_BLEN             3
+#define EG_SHAPER7_EG_Q4_EBS_FLAG             HSL_RW
+
+#define EG_Q5_UNIT
+#define EG_SHAPER7_EG_Q5_UNIT_BOFFSET          13
+#define EG_SHAPER7_EG_Q5_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q5_UNIT_FLAG             HSL_RW
+
+#define EG_Q4_UNIT
+#define EG_SHAPER7_EG_Q4_UNIT_BOFFSET          12
+#define EG_SHAPER7_EG_Q4_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q4_UNIT_FLAG             HSL_RW
+
+#define EG_Q3_UNIT
+#define EG_SHAPER7_EG_Q3_UNIT_BOFFSET          11
+#define EG_SHAPER7_EG_Q3_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q3_UNIT_FLAG             HSL_RW
+
+#define EG_Q2_UNIT
+#define EG_SHAPER7_EG_Q2_UNIT_BOFFSET          10
+#define EG_SHAPER7_EG_Q2_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q2_UNIT_FLAG             HSL_RW
+
+#define EG_Q1_UNIT
+#define EG_SHAPER7_EG_Q1_UNIT_BOFFSET          9
+#define EG_SHAPER7_EG_Q1_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q1_UNIT_FLAG             HSL_RW
+
+#define EG_Q0_UNIT
+#define EG_SHAPER7_EG_Q0_UNIT_BOFFSET          8
+#define EG_SHAPER7_EG_Q0_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q0_UNIT_FLAG             HSL_RW
+
+#define EG_PT
+#define EG_SHAPER7_EG_PT_BOFFSET          3
+#define EG_SHAPER7_EG_PT_BLEN             1
+#define EG_SHAPER7_EG_PT_FLAG             HSL_RW
+
+#define EG_TS
+#define EG_SHAPER7_EG_TS_BOFFSET          0
+#define EG_SHAPER7_EG_TS_BLEN             3
+#define EG_SHAPER7_EG_TS_FLAG             HSL_RW
+
+
+
+    /* ACL Policer Register0 */
+#define ACL_POLICER0
+#define ACL_POLICER0_OFFSET         0x0a00
+#define ACL_POLICER0_E_LENGTH       4
+#define ACL_POLICER0_E_OFFSET       0x0008
+#define ACL_POLICER0_NR_E           32
+
+#define ACL_CBS
+#define ACL_POLICER0_ACL_CBS_BOFFSET          15
+#define ACL_POLICER0_ACL_CBS_BLEN             3
+#define ACL_POLICER0_ACL_CBS_FLAG             HSL_RW
+
+#define ACL_CIR
+#define ACL_POLICER0_ACL_CIR_BOFFSET          0
+#define ACL_POLICER0_ACL_CIR_BLEN             15
+#define ACL_POLICER0_ACL_CIR_FLAG             HSL_RW
+
+
+    /* ACL Policer Register1 */
+#define ACL_POLICER1
+#define ACL_POLICER1_OFFSET         0x0a04
+#define ACL_POLICER1_E_LENGTH       4
+#define ACL_POLICER1_E_OFFSET       0x0008
+#define ACL_POLICER1_NR_E           32
+
+#define ACL_BORROW
+#define ACL_POLICER1_ACL_BORROW_BOFFSET          23
+#define ACL_POLICER1_ACL_BORROW_BLEN             1
+#define ACL_POLICER1_ACL_BORROW_FLAG             HSL_RW
+
+#define ACL_UNIT
+#define ACL_POLICER1_ACL_UNIT_BOFFSET          22
+#define ACL_POLICER1_ACL_UNIT_BLEN             1
+#define ACL_POLICER1_ACL_UNIT_FLAG             HSL_RW
+
+#define ACL_CF
+#define ACL_POLICER1_ACL_CF_BOFFSET          21
+#define ACL_POLICER1_ACL_CF_BLEN             1
+#define ACL_POLICER1_ACL_CF_FLAG             HSL_RW
+
+#define ACL_CM
+#define ACL_POLICER1_ACL_CM_BOFFSET          20
+#define ACL_POLICER1_ACL_CM_BLEN             1
+#define ACL_POLICER1_ACL_CM_FLAG             HSL_RW
+
+#define ACL_TS
+#define ACL_POLICER1_ACL_TS_BOFFSET          18
+#define ACL_POLICER1_ACL_TS_BLEN             2
+#define ACL_POLICER1_ACL_TS_FLAG             HSL_RW
+
+#define ACL_EBS
+#define ACL_POLICER1_ACL_EBS_BOFFSET          15
+#define ACL_POLICER1_ACL_EBS_BLEN             3
+#define ACL_POLICER1_ACL_EBS_FLAG             HSL_RW
+
+#define ACL_EIR
+#define ACL_POLICER1_ACL_EIR_BOFFSET          0
+#define ACL_POLICER1_ACL_EIR_BLEN             15
+#define ACL_POLICER1_ACL_EIR_FLAG             HSL_RW
+
+
+	/* Flow Congestion Drop CTRL0 */
+#define FLOW_CONGE_DROP_CTRL0
+#define FLOW_CONGE_DROP_CTRL0_OFFSET         0x0b74
+#define FLOW_CONGE_DROP_CTRL0_E_LENGTH       4
+#define FLOW_CONGE_DROP_CTRL0_E_OFFSET       4
+#define FLOW_CONGE_DROP_CTRL0_NR_E           1
+
+#define EN5
+#define FLOW_CONGE_DROP_CTRL0_EN5_BOFFSET        22
+#define FLOW_CONGE_DROP_CTRL0_EN5_BLEN           6
+#define FLOW_CONGE_DROP_CTRL0_EN5_FLAG           HSL_RW
+
+#define EN4
+#define FLOW_CONGE_DROP_CTRL0_EN4_BOFFSET        18
+#define FLOW_CONGE_DROP_CTRL0_EN4_BLEN           4
+#define FLOW_CONGE_DROP_CTRL0_EN4_FLAG           HSL_RW
+
+#define EN3
+#define FLOW_CONGE_DROP_CTRL0_EN3_BOFFSET        14
+#define FLOW_CONGE_DROP_CTRL0_EN3_BLEN           4
+#define FLOW_CONGE_DROP_CTRL0_EN3_FLAG           HSL_RW
+
+#define EN2
+#define FLOW_CONGE_DROP_CTRL0_EN2_BOFFSET        10
+#define FLOW_CONGE_DROP_CTRL0_EN2_BLEN           4
+#define FLOW_CONGE_DROP_CTRL0_EN2_FLAG           HSL_RW
+
+#define EN1
+#define FLOW_CONGE_DROP_CTRL0_EN1_BOFFSET        6
+#define FLOW_CONGE_DROP_CTRL0_EN1_BLEN           4
+#define FLOW_CONGE_DROP_CTRL0_EN1_FLAG           HSL_RW
+
+#define EN0
+#define FLOW_CONGE_DROP_CTRL0_EN0_BOFFSET        0
+#define FLOW_CONGE_DROP_CTRL0_EN0_BLEN           6
+#define FLOW_CONGE_DROP_CTRL0_EN0_FLAG           HSL_RW
+
+		/* Ring Flow Control Threshold Register*/
+#define RING_FLOW_CTRL_THRES
+#define RING_FLOW_CTRL_THRES_OFFSET         0x0b80
+#define RING_FLOW_CTRL_THRES_E_LENGTH       4
+#define RING_FLOW_CTRL_THRES_E_OFFSET       4
+#define RING_FLOW_CTRL_THRES_NR_E           8
+
+#define XON
+#define RING_FLOW_CTRL_THRES_XON_BOFFSET        16
+#define RING_FLOW_CTRL_THRES_XON_BLEN           8
+#define RING_FLOW_CTRL_THRES_XON_FLAG           HSL_RW
+
+#define XOFF
+#define RING_FLOW_CTRL_THRES_XOFF_BOFFSET        0
+#define RING_FLOW_CTRL_THRES_XOFF_BLEN           8
+#define RING_FLOW_CTRL_THRES_XOFF_FLAG           HSL_RW
+
+
+
+
+    /* ACL Counter Register0 */
+#define ACL_COUNTER0
+#define ACL_COUNTER0_OFFSET         0x1c000
+#define ACL_COUNTER0_E_LENGTH       4
+#define ACL_COUNTER0_E_OFFSET       0x0008
+#define ACL_COUNTER0_NR_E           32
+
+    /* ACL Counter Register1 */
+#define ACL_COUNTER1
+#define ACL_COUNTER1_OFFSET         0x1c004
+#define ACL_COUNTER1_E_LENGTH       4
+#define ACL_COUNTER1_E_OFFSET       0x0008
+#define ACL_COUNTER1_NR_E           32
+
+
+
+
+    /* INGRESS Policer Register0 */
+#define INGRESS_POLICER0
+#define INGRESS_POLICER0_OFFSET         0x0b00
+#define INGRESS_POLICER0_E_LENGTH       4
+#define INGRESS_POLICER0_E_OFFSET       0x0010
+#define INGRESS_POLICER0_NR_E           7
+
+#define ADD_RATE_BYTE
+#define INGRESS_POLICER0_ADD_RATE_BYTE_BOFFSET 24
+#define INGRESS_POLICER0_ADD_RATE_BYTE_BLEN 8
+#define INGRESS_POLICER0_ADD_RATE_BYTE_FLAG HSL_RW
+
+#define C_ING_TS
+#define INGRESS_POLICER0_C_ING_TS_BOFFSET          22
+#define INGRESS_POLICER0_C_ING_TS_BLEN             2
+#define INGRESS_POLICER0_C_ING_TS_FLAG             HSL_RW
+
+#define RATE_MODE
+#define INGRESS_POLICER0_RATE_MODE_BOFFSET          20
+#define INGRESS_POLICER0_RATE_MODE_BLEN             1
+#define INGRESS_POLICER0_RATE_MODE_FLAG             HSL_RW
+
+#define INGRESS_CBS
+#define INGRESS_POLICER0_INGRESS_CBS_BOFFSET          15
+#define INGRESS_POLICER0_INGRESS_CBS_BLEN             3
+#define INGRESS_POLICER0_INGRESS_CBS_FLAG             HSL_RW
+
+#define INGRESS_CIR
+#define INGRESS_POLICER0_INGRESS_CIR_BOFFSET          0
+#define INGRESS_POLICER0_INGRESS_CIR_BLEN             15
+#define INGRESS_POLICER0_INGRESS_CIR_FLAG             HSL_RW
+
+
+    /* INGRESS Policer Register1 */
+#define INGRESS_POLICER1
+#define INGRESS_POLICER1_OFFSET         0x0b04
+#define INGRESS_POLICER1_E_LENGTH       4
+#define INGRESS_POLICER1_E_OFFSET       0x0010
+#define INGRESS_POLICER1_NR_E           7
+
+#define INGRESS_BORROW
+#define INGRESS_POLICER1_INGRESS_BORROW_BOFFSET          23
+#define INGRESS_POLICER1_INGRESS_BORROW_BLEN             1
+#define INGRESS_POLICER1_INGRESS_BORROW_FLAG             HSL_RW
+
+#define INGRESS_UNIT
+#define INGRESS_POLICER1_INGRESS_UNIT_BOFFSET          22
+#define INGRESS_POLICER1_INGRESS_UNIT_BLEN             1
+#define INGRESS_POLICER1_INGRESS_UNIT_FLAG             HSL_RW
+
+#define INGRESS_CF
+#define INGRESS_POLICER1_INGRESS_CF_BOFFSET          21
+#define INGRESS_POLICER1_INGRESS_CF_BLEN             1
+#define INGRESS_POLICER1_INGRESS_CF_FLAG             HSL_RW
+
+#define INGRESS_CM
+#define INGRESS_POLICER1_INGRESS_CM_BOFFSET          20
+#define INGRESS_POLICER1_INGRESS_CM_BLEN             1
+#define INGRESS_POLICER1_INGRESS_CM_FLAG             HSL_RW
+
+#define E_ING_TS
+#define INGRESS_POLICER1_E_ING_TS_BOFFSET          18
+#define INGRESS_POLICER1_E_ING_TS_BLEN             2
+#define INGRESS_POLICER1_E_ING_TS_FLAG             HSL_RW
+
+#define INGRESS_EBS
+#define INGRESS_POLICER1_INGRESS_EBS_BOFFSET          15
+#define INGRESS_POLICER1_INGRESS_EBS_BLEN             3
+#define INGRESS_POLICER1_INGRESS_EBS_FLAG             HSL_RW
+
+#define INGRESS_EIR
+#define INGRESS_POLICER1_INGRESS_EIR_BOFFSET          0
+#define INGRESS_POLICER1_INGRESS_EIR_BLEN             15
+#define INGRESS_POLICER1_INGRESS_EIR_FLAG             HSL_RW
+
+
+    /* INGRESS Policer Register2 */
+#define INGRESS_POLICER2
+#define INGRESS_POLICER2_OFFSET                 0x0b08
+#define INGRESS_POLICER2_E_LENGTH               4
+#define INGRESS_POLICER2_E_OFFSET               0x0010
+#define INGRESS_POLICER2_NR_E                   7
+
+#define C_MUL
+#define INGRESS_POLICER2_C_MUL_BOFFSET          15
+#define INGRESS_POLICER2_C_MUL_BLEN             1
+#define INGRESS_POLICER2_C_UNK_MUL_FLAG         HSL_RW
+
+#define C_UNI
+#define INGRESS_POLICER2_C_UNI_BOFFSET          14
+#define INGRESS_POLICER2_C_UNI_BLEN             1
+#define INGRESS_POLICER2_C_UNI_FLAG             HSL_RW
+
+#define C_UNK_MUL
+#define INGRESS_POLICER2_C_UNK_MUL_BOFFSET      13
+#define INGRESS_POLICER2_C_UNK_MUL_BLEN         1
+#define INGRESS_POLICER2_C_UNK_MUL_FLAG         HSL_RW
+
+#define C_UNK_UNI
+#define INGRESS_POLICER2_C_UNK_UNI_BOFFSET      12
+#define INGRESS_POLICER2_C_UNK_UNI_BLEN         1
+#define INGRESS_POLICER2_C_UNK_UNI_FLAG         HSL_RW
+
+#define C_BROAD
+#define INGRESS_POLICER2_C_BROAD_BOFFSET        11
+#define INGRESS_POLICER2_C_BROAD_BLEN           1
+#define INGRESS_POLICER2_C_BROAD_FLAG           HSL_RW
+
+#define C_MANAGE
+#define INGRESS_POLICER2_C_MANAGC_BOFFSET       10
+#define INGRESS_POLICER2_C_MANAGC_BLEN          1
+#define INGRESS_POLICER2_C_MANAGC_FLAG          HSL_RW
+
+#define C_TCP
+#define INGRESS_POLICER2_C_TCP_BOFFSET          9
+#define INGRESS_POLICER2_C_TCP_BLEN             1
+#define INGRESS_POLICER2_C_TCP_FLAG             HSL_RW
+
+#define C_MIRR
+#define INGRESS_POLICER2_C_MIRR_BOFFSET         8
+#define INGRESS_POLICER2_C_MIRR_BLEN            1
+#define INGRESS_POLICER2_C_MIRR_FLAG            HSL_RW
+
+#define E_MUL
+#define INGRESS_POLICER2_E_MUL_BOFFSET          7
+#define INGRESS_POLICER2_E_MUL_BLEN             1
+#define INGRESS_POLICER2_E_UNK_MUL_FLAG         HSL_RW
+
+#define E_UNI
+#define INGRESS_POLICER2_E_UNI_BOFFSET          6
+#define INGRESS_POLICER2_E_UNI_BLEN             1
+#define INGRESS_POLICER2_E_UNI_FLAG             HSL_RW
+
+#define E_UNK_MUL
+#define INGRESS_POLICER2_E_UNK_MUL_BOFFSET      5
+#define INGRESS_POLICER2_E_UNK_MUL_BLEN         1
+#define INGRESS_POLICER2_E_UNK_MUL_FLAG         HSL_RW
+
+#define E_UNK_UNI
+#define INGRESS_POLICER2_E_UNK_UNI_BOFFSET      4
+#define INGRESS_POLICER2_E_UNK_UNI_BLEN         1
+#define INGRESS_POLICER2_E_UNK_UNI_FLAG         HSL_RW
+
+#define E_BROAD
+#define INGRESS_POLICER2_E_BROAD_BOFFSET        3
+#define INGRESS_POLICER2_E_BROAD_BLEN           1
+#define INGRESS_POLICER2_E_BROAD_FLAG           HSL_RW
+
+#define E_MANAGE
+#define INGRESS_POLICER2_E_MANAGE_BOFFSET       2
+#define INGRESS_POLICER2_E_MANAGE_BLEN          1
+#define INGRESS_POLICER2_E_MANAGE_FLAG          HSL_RW
+
+#define E_TCP
+#define INGRESS_POLICER2_E_TCP_BOFFSET          1
+#define INGRESS_POLICER2_E_TCP_BLEN             1
+#define INGRESS_POLICER2_E_TCP_FLAG             HSL_RW
+
+#define E_MIRR
+#define INGRESS_POLICER2_E_MIRR_BOFFSET         0
+#define INGRESS_POLICER2_E_MIRR_BLEN            1
+#define INGRESS_POLICER2_E_MIRR_FLAG            HSL_RW
+
+
+
+
+    /* Port Rate Limit2 Register */
+#define WRR_CTRL
+#define WRR_CTRL_OFFSET                         0x0830
+#define WRR_CTRL_E_LENGTH                       4
+#define WRR_CTRL_E_OFFSET                       0x0004
+#define WRR_CTRL_NR_E                           7
+
+#define SCH_MODE
+#define WRR_CTRL_SCH_MODE_BOFFSET               30
+#define WRR_CTRL_SCH_MODE_BLEN                  2
+#define WRR_CTRL_SCH_MODE_FLAG                  HSL_RW
+
+#define Q5_W
+#define WRR_CTRL_Q5_W_BOFFSET                   25
+#define WRR_CTRL_Q5_W_BLEN                      5
+#define WRR_CTRL_Q5_W_FLAG                      HSL_RW
+
+#define Q4_W
+#define WRR_CTRL_Q4_W_BOFFSET                   20
+#define WRR_CTRL_Q4_W_BLEN                      5
+#define WRR_CTRL_Q4_W_FLAG                      HSL_RW
+
+#define Q3_W
+#define WRR_CTRL_Q3_W_BOFFSET                   15
+#define WRR_CTRL_Q3_W_BLEN                      5
+#define WRR_CTRL_Q3_W_FLAG                      HSL_RW
+
+#define Q2_W
+#define WRR_CTRL_Q2_W_BOFFSET                   10
+#define WRR_CTRL_Q2_W_BLEN                      5
+#define WRR_CTRL_Q2_W_FLAG                      HSL_RW
+
+#define Q1_W
+#define WRR_CTRL_Q1_W_BOFFSET                   5
+#define WRR_CTRL_Q1_W_BLEN                      5
+#define WRR_CTRL_Q1_W_FLAG                      HSL_RW
+
+#define Q0_W
+#define WRR_CTRL_Q0_W_BOFFSET                   0
+#define WRR_CTRL_Q0_W_BLEN                      5
+#define WRR_CTRL_Q0_W_FLAG                      HSL_RW
+
+/* Global Interrupt Register0 */
+#define GLOBAL_INT0
+#define GLOBAL_INT0_OFFSET    0x0020
+#define GLOBAL_INT0_E_LENGTH  4
+#define GLOBAL_INT0_E_OFFSET  0
+#define GLOBAL_INT0_NR_E      1
+
+/* Global Interrupt Register1 */
+#define GLOBAL_INT1
+#define GLOBAL_INT1_OFFSET    0x0024
+#define GLOBAL_INT1_E_LENGTH  4
+#define GLOBAL_INT1_E_OFFSET  0
+#define GLOBAL_INT1_NR_E      1
+
+/* Global Interrupt Mask Register0  */
+#define GLOBAL_INT0_MASK
+#define GLOBAL_INT0_MASK_OFFSET    0x0028
+#define GLOBAL_INT0_MASK_E_LENGTH  4
+#define GLOBAL_INT0_MASK_E_OFFSET  0
+#define GLOBAL_INT0_MASK_NR_E      1
+
+/* Global Interrupt Mask Register1  */
+#define GLOBAL_INT1_MASK
+#define GLOBAL_INT1_MASK_OFFSET    0x002c
+#define GLOBAL_INT1_MASK_E_LENGTH  4
+#define GLOBAL_INT1_MASK_E_OFFSET  0
+#define GLOBAL_INT1_MASK_NR_E      1
+
+
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_REG_H_ */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_reg_access.h b/qca-ssdk/include/hsl/dess/dess_reg_access.h
new file mode 100755
index 0000000..5eb0436
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_reg_access.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2014,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _DESS_REG_ACCESS_H_
+#define _DESS_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "sw.h"
+
+    sw_error_t
+    dess_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+                 a_uint32_t reg, a_uint16_t * value);
+
+    sw_error_t
+    dess_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+                 a_uint32_t reg, a_uint16_t value);
+
+    sw_error_t
+    dess_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                 a_uint32_t value_len);
+
+    sw_error_t
+    dess_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                 a_uint32_t value_len);
+
+    sw_error_t
+    dess_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                       a_uint32_t bit_offset, a_uint32_t field_len,
+                       a_uint8_t value[], a_uint32_t value_len);
+
+    sw_error_t
+    dess_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                       a_uint32_t bit_offset, a_uint32_t field_len,
+                       const a_uint8_t value[], a_uint32_t value_len);
+
+	sw_error_t
+	dess_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump);
+
+	sw_error_t
+	dess_debug_regsiter_dump(a_uint32_t dev_id, fal_debug_reg_dump_t * dbg_reg_dump);
+
+
+    sw_error_t
+    dess_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode);
+
+    sw_error_t
+    dess_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode);
+
+	sw_error_t
+	dess_phy_dump(a_uint32_t dev_id, a_uint32_t phy_addr,
+		a_uint32_t idx, fal_phy_dump_t * phy_dump);
+
+	sw_error_t
+	dess_debug_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable,
+		a_uint32_t times, a_uint32_t * result);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _DESS_REG_ACCESS_H_ */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_sec.h b/qca-ssdk/include/hsl/dess/dess_sec.h
new file mode 100755
index 0000000..1ef340a
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_sec.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_SEC_H_
+#define _DESS_SEC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_sec.h"
+
+    sw_error_t dess_sec_init(a_uint32_t dev_id);
+
+#ifdef IN_SEC
+#define DESS_SEC_INIT(rv, dev_id) \
+    { \
+        rv = dess_sec_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_SEC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    dess_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item,
+                           void *value);
+
+    HSL_LOCAL sw_error_t
+    dess_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item,
+                           void *value);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_SEC_H_ */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_stp.h b/qca-ssdk/include/hsl/dess/dess_stp.h
new file mode 100755
index 0000000..c1450cd
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_stp.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_STP_H_
+#define _DESS_STP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_stp.h"
+
+    sw_error_t dess_stp_init(a_uint32_t dev_id);
+
+#ifdef IN_STP
+#define DESS_STP_INIT(rv, dev_id) \
+    { \
+        rv = dess_stp_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_STP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    dess_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                            fal_port_t port_id, fal_stp_state_t state);
+
+
+    HSL_LOCAL sw_error_t
+    dess_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                            fal_port_t port_id, fal_stp_state_t * state);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_STP_H_ */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_trunk.h b/qca-ssdk/include/hsl/dess/dess_trunk.h
new file mode 100755
index 0000000..60e751a
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_trunk.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_TRUNK_H_
+#define _DESS_TRUNK_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_trunk.h"
+
+    sw_error_t dess_trunk_init(a_uint32_t dev_id);
+
+#ifdef IN_TRUNK
+#define DESS_TRUNK_INIT(rv, dev_id) \
+    { \
+        rv = dess_trunk_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_TRUNK_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    dess_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+                         a_bool_t enable, fal_pbmp_t member);
+
+    HSL_LOCAL sw_error_t
+    dess_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+                         a_bool_t * enable, fal_pbmp_t * member);
+
+    HSL_LOCAL sw_error_t
+    dess_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+    HSL_LOCAL sw_error_t
+    dess_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _DESS_TRUNK_H_ */
+
diff --git a/qca-ssdk/include/hsl/dess/dess_vlan.h b/qca-ssdk/include/hsl/dess/dess_vlan.h
new file mode 100755
index 0000000..efe0992
--- /dev/null
+++ b/qca-ssdk/include/hsl/dess/dess_vlan.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _DESS_VLAN_H_
+#define _DESS_VLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_vlan.h"
+
+    sw_error_t
+    dess_vlan_init(a_uint32_t dev_id);
+
+#ifdef IN_VLAN
+#define DESS_VLAN_INIT(rv, dev_id) \
+    { \
+        rv = dess_vlan_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define DESS_VLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    dess_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry);
+
+
+    HSL_LOCAL sw_error_t
+    dess_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+    HSL_LOCAL sw_error_t
+    dess_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+    HSL_LOCAL sw_error_t
+    dess_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+    HSL_LOCAL sw_error_t
+    dess_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+    HSL_LOCAL sw_error_t
+    dess_vlan_flush(a_uint32_t dev_id);
+
+
+    HSL_LOCAL sw_error_t
+    dess_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid);
+
+
+    HSL_LOCAL sw_error_t
+    dess_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid);
+
+
+    HSL_LOCAL sw_error_t
+    dess_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+                         fal_port_t port_id, fal_pt_1q_egmode_t port_info);
+
+
+    HSL_LOCAL sw_error_t
+    dess_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    dess_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+                                 a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    dess_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+                                 a_bool_t * enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _DESS_VLAN_H_ */
+
diff --git a/qca-ssdk/include/hsl/garuda/garuda_acl.h b/qca-ssdk/include/hsl/garuda/garuda_acl.h
new file mode 100755
index 0000000..2e6794a
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_acl.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_acl GARUDA_ACL
+ * @{
+ */
+#ifndef _GARUDA_ACL_H_
+#define _GARUDA_ACL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_acl.h"
+
+    sw_error_t
+    garuda_acl_init(a_uint32_t dev_id);
+
+    sw_error_t
+    garuda_acl_reset(a_uint32_t dev_id);
+
+#ifdef IN_ACL
+#define GARUDA_ACL_INIT(rv, dev_id) \
+    { \
+        rv = garuda_acl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define GARUDA_ACL_RESET(rv, dev_id) \
+    { \
+        rv = garuda_acl_reset(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define GARUDA_ACL_INIT(rv, dev_id)
+#define GARUDA_ACL_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    garuda_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+                          a_uint32_t list_pri);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+                        a_uint32_t rule_id, a_uint32_t rule_nr,
+                        fal_acl_rule_t * rule);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+                           a_uint32_t rule_id, a_uint32_t rule_nr);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+                          a_uint32_t rule_id, fal_acl_rule_t * rule);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                         fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                         a_uint32_t obj_idx);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                           fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                           a_uint32_t obj_idx);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_acl_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_acl_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    garuda_acl_list_dump(a_uint32_t dev_id);
+
+    HSL_LOCAL sw_error_t
+    garuda_acl_rule_dump(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _GARUDA_ACL_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/garuda/garuda_api.h b/qca-ssdk/include/hsl/garuda/garuda_api.h
new file mode 100755
index 0000000..d5cd0ca
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_api.h
@@ -0,0 +1,531 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _GARUDA_API_H_
+#define _GARUDA_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#ifdef IN_PORTCONTROL
+#define PORTCONTROL_API \
+    SW_API_DEF(SW_API_PT_DUPLEX_GET, garuda_port_duplex_get), \
+    SW_API_DEF(SW_API_PT_DUPLEX_SET, garuda_port_duplex_set), \
+    SW_API_DEF(SW_API_PT_SPEED_GET, garuda_port_speed_get), \
+    SW_API_DEF(SW_API_PT_SPEED_SET, garuda_port_speed_set), \
+    SW_API_DEF(SW_API_PT_AN_GET, garuda_port_autoneg_status_get), \
+    SW_API_DEF(SW_API_PT_AN_ENABLE, garuda_port_autoneg_enable), \
+    SW_API_DEF(SW_API_PT_AN_RESTART, garuda_port_autoneg_restart), \
+    SW_API_DEF(SW_API_PT_AN_ADV_GET, garuda_port_autoneg_adv_get), \
+    SW_API_DEF(SW_API_PT_AN_ADV_SET, garuda_port_autoneg_adv_set), \
+    SW_API_DEF(SW_API_PT_HDR_SET, garuda_port_hdr_status_set), \
+    SW_API_DEF(SW_API_PT_HDR_GET, garuda_port_hdr_status_get), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_SET, garuda_port_flowctrl_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_GET, garuda_port_flowctrl_get), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, garuda_port_flowctrl_forcemode_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, garuda_port_flowctrl_forcemode_get),\
+    SW_API_DEF(SW_API_PT_POWERSAVE_SET, garuda_port_powersave_set), \
+    SW_API_DEF(SW_API_PT_POWERSAVE_GET, garuda_port_powersave_get), \
+    SW_API_DEF(SW_API_PT_HIBERNATE_SET, garuda_port_hibernate_set), \
+    SW_API_DEF(SW_API_PT_HIBERNATE_GET, garuda_port_hibernate_get), \
+    SW_API_DEF(SW_API_PT_CDT, garuda_port_cdt),
+
+#define PORTCONTROL_API_PARAM \
+    SW_API_DESC(SW_API_PT_DUPLEX_GET) \
+    SW_API_DESC(SW_API_PT_DUPLEX_SET) \
+    SW_API_DESC(SW_API_PT_SPEED_GET) \
+    SW_API_DESC(SW_API_PT_SPEED_SET) \
+    SW_API_DESC(SW_API_PT_AN_GET) \
+    SW_API_DESC(SW_API_PT_AN_ENABLE) \
+    SW_API_DESC(SW_API_PT_AN_RESTART) \
+    SW_API_DESC(SW_API_PT_AN_ADV_GET) \
+    SW_API_DESC(SW_API_PT_AN_ADV_SET) \
+    SW_API_DESC(SW_API_PT_HDR_SET) \
+    SW_API_DESC(SW_API_PT_HDR_GET) \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_SET) \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_GET) \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET) \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET)\
+    SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
+    SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
+    SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
+    SW_API_DESC(SW_API_PT_HIBERNATE_GET) \
+    SW_API_DESC(SW_API_PT_CDT)
+
+#else
+#define PORTCONTROL_API
+#define PORTCONTROL_API_PARAM
+#endif
+
+#ifdef IN_VLAN
+#define VLAN_API \
+    SW_API_DEF(SW_API_VLAN_ADD, garuda_vlan_create), \
+    SW_API_DEF(SW_API_VLAN_DEL, garuda_vlan_delete), \
+    SW_API_DEF(SW_API_VLAN_MEM_UPDATE, garuda_vlan_member_update), \
+    SW_API_DEF(SW_API_VLAN_FIND, garuda_vlan_find), \
+    SW_API_DEF(SW_API_VLAN_NEXT, garuda_vlan_next), \
+    SW_API_DEF(SW_API_VLAN_APPEND, garuda_vlan_entry_append),
+
+#define VLAN_API_PARAM \
+    SW_API_DESC(SW_API_VLAN_ADD) \
+    SW_API_DESC(SW_API_VLAN_DEL) \
+    SW_API_DESC(SW_API_VLAN_MEM_UPDATE) \
+    SW_API_DESC(SW_API_VLAN_FIND) \
+    SW_API_DESC(SW_API_VLAN_NEXT) \
+    SW_API_DESC(SW_API_VLAN_APPEND)
+#else
+#define VLAN_API
+#define VLAN_API_PARAM
+#endif
+
+#ifdef IN_PORTVLAN
+#define PORTVLAN_API \
+    SW_API_DEF(SW_API_PT_ING_MODE_GET, garuda_port_1qmode_get), \
+    SW_API_DEF(SW_API_PT_ING_MODE_SET, garuda_port_1qmode_set), \
+    SW_API_DEF(SW_API_PT_EG_MODE_GET, garuda_port_egvlanmode_get), \
+    SW_API_DEF(SW_API_PT_EG_MODE_SET, garuda_port_egvlanmode_set), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, garuda_portvlan_member_add), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, garuda_portvlan_member_del), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, garuda_portvlan_member_update), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_GET, garuda_portvlan_member_get), \
+    SW_API_DEF(SW_API_PT_DEF_VID_SET, garuda_port_default_vid_set), \
+    SW_API_DEF(SW_API_PT_DEF_VID_GET, garuda_port_default_vid_get), \
+    SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, garuda_port_force_default_vid_set), \
+    SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, garuda_port_force_default_vid_get), \
+    SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, garuda_port_force_portvlan_set), \
+    SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, garuda_port_force_portvlan_get), \
+    SW_API_DEF(SW_API_PT_NESTVLAN_SET, garuda_port_nestvlan_set), \
+    SW_API_DEF(SW_API_PT_NESTVLAN_GET, garuda_port_nestvlan_get), \
+    SW_API_DEF(SW_API_NESTVLAN_TPID_SET, garuda_nestvlan_tpid_set), \
+    SW_API_DEF(SW_API_NESTVLAN_TPID_GET, garuda_nestvlan_tpid_get),
+
+#define PORTVLAN_API_PARAM \
+    SW_API_DESC(SW_API_PT_ING_MODE_GET) \
+    SW_API_DESC(SW_API_PT_ING_MODE_SET) \
+    SW_API_DESC(SW_API_PT_EG_MODE_GET) \
+    SW_API_DESC(SW_API_PT_EG_MODE_SET) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_GET)    \
+    SW_API_DESC(SW_API_PT_DEF_VID_SET)    \
+    SW_API_DESC(SW_API_PT_DEF_VID_GET)    \
+    SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET)    \
+    SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET)    \
+    SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET)    \
+    SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET)    \
+    SW_API_DESC(SW_API_PT_NESTVLAN_SET)    \
+    SW_API_DESC(SW_API_PT_NESTVLAN_GET)    \
+    SW_API_DESC(SW_API_NESTVLAN_TPID_SET)    \
+    SW_API_DESC(SW_API_NESTVLAN_TPID_GET)
+#else
+#define PORTVLAN_API
+#define PORTVLAN_API_PARAM
+#endif
+
+#ifdef IN_FDB
+#define FDB_API \
+    SW_API_DEF(SW_API_FDB_ADD, garuda_fdb_add), \
+    SW_API_DEF(SW_API_FDB_DELALL, garuda_fdb_del_all), \
+    SW_API_DEF(SW_API_FDB_DELPORT,garuda_fdb_del_by_port), \
+    SW_API_DEF(SW_API_FDB_DELMAC, garuda_fdb_del_by_mac), \
+    SW_API_DEF(SW_API_FDB_FIRST,  garuda_fdb_first), \
+    SW_API_DEF(SW_API_FDB_NEXT,   garuda_fdb_next), \
+    SW_API_DEF(SW_API_FDB_FIND,   garuda_fdb_find), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_SET,   garuda_fdb_port_learn_set), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_GET,   garuda_fdb_port_learn_get), \
+    SW_API_DEF(SW_API_FDB_AGE_CTRL_SET,   garuda_fdb_age_ctrl_set), \
+    SW_API_DEF(SW_API_FDB_AGE_CTRL_GET,   garuda_fdb_age_ctrl_get), \
+    SW_API_DEF(SW_API_FDB_AGE_TIME_SET,   garuda_fdb_age_time_set), \
+    SW_API_DEF(SW_API_FDB_AGE_TIME_GET,   garuda_fdb_age_time_get),
+
+#define FDB_API_PARAM \
+    SW_API_DESC(SW_API_FDB_ADD) \
+    SW_API_DESC(SW_API_FDB_DELALL) \
+    SW_API_DESC(SW_API_FDB_DELPORT) \
+    SW_API_DESC(SW_API_FDB_DELMAC) \
+    SW_API_DESC(SW_API_FDB_FIRST) \
+    SW_API_DESC(SW_API_FDB_NEXT) \
+    SW_API_DESC(SW_API_FDB_FIND) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \
+    SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \
+    SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \
+    SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \
+    SW_API_DESC(SW_API_FDB_AGE_TIME_GET)
+#else
+#define FDB_API
+#define FDB_API_PARAM
+#endif
+
+#ifdef IN_ACL
+#define ACL_API \
+    SW_API_DEF(SW_API_ACL_LIST_CREAT, garuda_acl_list_creat), \
+    SW_API_DEF(SW_API_ACL_LIST_DESTROY, garuda_acl_list_destroy), \
+    SW_API_DEF(SW_API_ACL_RULE_ADD, garuda_acl_rule_add), \
+    SW_API_DEF(SW_API_ACL_RULE_DELETE, garuda_acl_rule_delete), \
+    SW_API_DEF(SW_API_ACL_RULE_QUERY, garuda_acl_rule_query), \
+    SW_API_DEF(SW_API_ACL_LIST_BIND, garuda_acl_list_bind), \
+    SW_API_DEF(SW_API_ACL_LIST_UNBIND, garuda_acl_list_unbind), \
+    SW_API_DEF(SW_API_ACL_STATUS_SET, garuda_acl_status_set), \
+    SW_API_DEF(SW_API_ACL_STATUS_GET, garuda_acl_status_get), \
+    SW_API_DEF(SW_API_ACL_LIST_DUMP, garuda_acl_list_dump), \
+    SW_API_DEF(SW_API_ACL_RULE_DUMP, garuda_acl_rule_dump),
+
+#define ACL_API_PARAM \
+    SW_API_DESC(SW_API_ACL_LIST_CREAT) \
+    SW_API_DESC(SW_API_ACL_LIST_DESTROY) \
+    SW_API_DESC(SW_API_ACL_RULE_ADD) \
+    SW_API_DESC(SW_API_ACL_RULE_DELETE) \
+    SW_API_DESC(SW_API_ACL_RULE_QUERY) \
+    SW_API_DESC(SW_API_ACL_LIST_BIND) \
+    SW_API_DESC(SW_API_ACL_LIST_UNBIND) \
+    SW_API_DESC(SW_API_ACL_STATUS_SET) \
+    SW_API_DESC(SW_API_ACL_STATUS_GET) \
+    SW_API_DESC(SW_API_ACL_LIST_DUMP) \
+    SW_API_DESC(SW_API_ACL_RULE_DUMP)
+#else
+#define ACL_API
+#define ACL_API_PARAM
+#endif
+
+#ifdef IN_QOS
+#define QOS_API \
+    SW_API_DEF(SW_API_QOS_SCH_MODE_SET, garuda_qos_sch_mode_set), \
+    SW_API_DEF(SW_API_QOS_SCH_MODE_GET, garuda_qos_sch_mode_get), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, garuda_qos_queue_tx_buf_status_set), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, garuda_qos_queue_tx_buf_status_get), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, garuda_qos_queue_tx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, garuda_qos_queue_tx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, garuda_qos_port_tx_buf_status_set), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, garuda_qos_port_tx_buf_status_get), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, garuda_qos_port_tx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, garuda_qos_port_tx_buf_nr_get), \
+    SW_API_DEF(SW_API_COSMAP_UP_QU_SET, garuda_cosmap_up_queue_set), \
+    SW_API_DEF(SW_API_COSMAP_UP_QU_GET, garuda_cosmap_up_queue_get), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_QU_SET, garuda_cosmap_dscp_queue_set), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_QU_GET, garuda_cosmap_dscp_queue_get), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_SET, garuda_qos_port_mode_set), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_GET, garuda_qos_port_mode_get), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, garuda_qos_port_mode_pri_set), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, garuda_qos_port_mode_pri_get), \
+    SW_API_DEF(SW_API_QOS_PORT_DEF_UP_SET, garuda_qos_port_default_up_set), \
+    SW_API_DEF(SW_API_QOS_PORT_DEF_UP_GET, garuda_qos_port_default_up_get),
+
+#define QOS_API_PARAM \
+    SW_API_DESC(SW_API_QOS_SCH_MODE_SET) \
+    SW_API_DESC(SW_API_QOS_SCH_MODE_GET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_COSMAP_UP_QU_SET) \
+    SW_API_DESC(SW_API_COSMAP_UP_QU_GET) \
+    SW_API_DESC(SW_API_COSMAP_DSCP_QU_SET) \
+    SW_API_DESC(SW_API_COSMAP_DSCP_QU_GET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_SET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_GET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET)
+#else
+#define QOS_API
+#define QOS_API_PARAM
+#endif
+
+#ifdef IN_IGMP
+#define IGMP_API \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, garuda_port_igmps_status_set), \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, garuda_port_igmps_status_get), \
+    SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, garuda_igmp_mld_cmd_set), \
+    SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, garuda_igmp_mld_cmd_get), \
+    SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, garuda_port_igmp_mld_join_set), \
+    SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, garuda_port_igmp_mld_join_get), \
+    SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, garuda_port_igmp_mld_leave_set), \
+    SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, garuda_port_igmp_mld_leave_get), \
+    SW_API_DEF(SW_API_IGMP_RP_SET, garuda_igmp_mld_rp_set), \
+    SW_API_DEF(SW_API_IGMP_RP_GET, garuda_igmp_mld_rp_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, garuda_igmp_mld_entry_creat_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, garuda_igmp_mld_entry_creat_get),
+
+#define IGMP_API_PARAM \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
+    SW_API_DESC(SW_API_IGMP_MLD_CMD_SET)  \
+    SW_API_DESC(SW_API_IGMP_MLD_CMD_GET)  \
+    SW_API_DESC(SW_API_IGMP_PT_JOIN_SET)  \
+    SW_API_DESC(SW_API_IGMP_PT_JOIN_GET)  \
+    SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \
+    SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \
+    SW_API_DESC(SW_API_IGMP_RP_SET) \
+    SW_API_DESC(SW_API_IGMP_RP_GET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET)
+#else
+#define IGMP_API
+#define IGMP_API_PARAM
+#endif
+
+#ifdef IN_LEAKY
+#define LEAKY_API \
+    SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, garuda_uc_leaky_mode_set), \
+    SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, garuda_uc_leaky_mode_get), \
+    SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, garuda_mc_leaky_mode_set), \
+    SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, garuda_mc_leaky_mode_get), \
+    SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, garuda_port_arp_leaky_set), \
+    SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, garuda_port_arp_leaky_get), \
+    SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, garuda_port_uc_leaky_set), \
+    SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, garuda_port_uc_leaky_get), \
+    SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, garuda_port_mc_leaky_set), \
+    SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, garuda_port_mc_leaky_get),
+
+#define LEAKY_API_PARAM \
+    SW_API_DESC(SW_API_UC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_UC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_MC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_MC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \
+    SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \
+    SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET) \
+    SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET) \
+    SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET) \
+    SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET)
+#else
+#define LEAKY_API
+#define LEAKY_API_PARAM
+#endif
+
+#ifdef IN_MIRROR
+#define MIRROR_API \
+    SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, garuda_mirr_analysis_port_set), \
+    SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, garuda_mirr_analysis_port_get), \
+    SW_API_DEF(SW_API_MIRROR_IN_PT_SET, garuda_mirr_port_in_set), \
+    SW_API_DEF(SW_API_MIRROR_IN_PT_GET, garuda_mirr_port_in_get), \
+    SW_API_DEF(SW_API_MIRROR_EG_PT_SET, garuda_mirr_port_eg_set), \
+    SW_API_DEF(SW_API_MIRROR_EG_PT_GET, garuda_mirr_port_eg_get),
+
+#define MIRROR_API_PARAM \
+    SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET) \
+    SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET) \
+    SW_API_DESC(SW_API_MIRROR_IN_PT_SET) \
+    SW_API_DESC(SW_API_MIRROR_IN_PT_GET) \
+    SW_API_DESC(SW_API_MIRROR_EG_PT_SET) \
+    SW_API_DESC(SW_API_MIRROR_EG_PT_GET)
+#else
+#define MIRROR_API
+#define MIRROR_API_PARAM
+#endif
+
+#ifdef IN_RATE
+#define RATE_API \
+    SW_API_DEF(SW_API_RATE_QU_EGRL_SET, garuda_rate_queue_egrl_set), \
+    SW_API_DEF(SW_API_RATE_QU_EGRL_GET, garuda_rate_queue_egrl_get), \
+    SW_API_DEF(SW_API_RATE_PT_EGRL_SET, garuda_rate_port_egrl_set), \
+    SW_API_DEF(SW_API_RATE_PT_EGRL_GET, garuda_rate_port_egrl_get), \
+    SW_API_DEF(SW_API_RATE_PT_INRL_SET, garuda_rate_port_inrl_set), \
+    SW_API_DEF(SW_API_RATE_PT_INRL_GET, garuda_rate_port_inrl_get), \
+    SW_API_DEF(SW_API_STORM_CTRL_FRAME_SET, garuda_storm_ctrl_frame_set), \
+    SW_API_DEF(SW_API_STORM_CTRL_FRAME_GET, garuda_storm_ctrl_frame_get), \
+    SW_API_DEF(SW_API_STORM_CTRL_RATE_SET, garuda_storm_ctrl_rate_set), \
+    SW_API_DEF(SW_API_STORM_CTRL_RATE_GET, garuda_storm_ctrl_rate_get),
+
+#define RATE_API_PARAM \
+    SW_API_DESC(SW_API_RATE_QU_EGRL_SET) \
+    SW_API_DESC(SW_API_RATE_QU_EGRL_GET) \
+    SW_API_DESC(SW_API_RATE_PT_EGRL_SET) \
+    SW_API_DESC(SW_API_RATE_PT_EGRL_GET) \
+    SW_API_DESC(SW_API_RATE_PT_INRL_SET) \
+    SW_API_DESC(SW_API_RATE_PT_INRL_GET) \
+    SW_API_DESC(SW_API_STORM_CTRL_FRAME_SET) \
+    SW_API_DESC(SW_API_STORM_CTRL_FRAME_GET) \
+    SW_API_DESC(SW_API_STORM_CTRL_RATE_SET) \
+    SW_API_DESC(SW_API_STORM_CTRL_RATE_GET)
+#else
+#define RATE_API
+#define RATE_API_PARAM
+#endif
+
+#ifdef IN_STP
+#define STP_API \
+    SW_API_DEF(SW_API_STP_PT_STATE_SET, garuda_stp_port_state_set), \
+    SW_API_DEF(SW_API_STP_PT_STATE_GET, garuda_stp_port_state_get),
+
+#define STP_API_PARAM \
+    SW_API_DESC(SW_API_STP_PT_STATE_SET) \
+    SW_API_DESC(SW_API_STP_PT_STATE_GET)
+#else
+#define STP_API
+#define STP_API_PARAM
+#endif
+
+#ifdef IN_MIB
+#define MIB_API \
+    SW_API_DEF(SW_API_PT_MIB_GET, garuda_get_mib_info), \
+    SW_API_DEF(SW_API_MIB_STATUS_SET, garuda_mib_status_set), \
+    SW_API_DEF(SW_API_MIB_STATUS_GET, garuda_mib_status_get),
+
+#define MIB_API_PARAM \
+    SW_API_DESC(SW_API_PT_MIB_GET) \
+    SW_API_DESC(SW_API_MIB_STATUS_SET) \
+    SW_API_DESC(SW_API_MIB_STATUS_GET)
+#else
+#define MIB_API
+#define MIB_API_PARAM
+#endif
+
+#ifdef IN_MISC
+#define MISC_API \
+    SW_API_DEF(SW_API_ARP_STATUS_SET, garuda_arp_status_set), \
+    SW_API_DEF(SW_API_ARP_STATUS_GET, garuda_arp_status_get), \
+    SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, garuda_frame_max_size_set), \
+    SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, garuda_frame_max_size_get), \
+    SW_API_DEF(SW_API_PT_UNK_SA_CMD_SET, garuda_port_unk_sa_cmd_set), \
+    SW_API_DEF(SW_API_PT_UNK_SA_CMD_GET, garuda_port_unk_sa_cmd_get), \
+    SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, garuda_port_unk_uc_filter_set), \
+    SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, garuda_port_unk_uc_filter_get), \
+    SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, garuda_port_unk_mc_filter_set), \
+    SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, garuda_port_unk_mc_filter_get), \
+    SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, garuda_cpu_port_status_set), \
+    SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, garuda_cpu_port_status_get), \
+    SW_API_DEF(SW_API_BC_TO_CPU_PORT_SET, garuda_bc_to_cpu_port_set), \
+    SW_API_DEF(SW_API_BC_TO_CPU_PORT_GET, garuda_bc_to_cpu_port_get), \
+    SW_API_DEF(SW_API_PPPOE_CMD_SET, garuda_pppoe_cmd_set), \
+    SW_API_DEF(SW_API_PPPOE_CMD_GET, garuda_pppoe_cmd_get), \
+    SW_API_DEF(SW_API_PPPOE_STATUS_SET, garuda_pppoe_status_set), \
+    SW_API_DEF(SW_API_PPPOE_STATUS_GET, garuda_pppoe_status_get), \
+    SW_API_DEF(SW_API_PT_DHCP_SET, garuda_port_dhcp_set), \
+    SW_API_DEF(SW_API_PT_DHCP_GET, garuda_port_dhcp_get),
+
+#define MISC_API_PARAM \
+    SW_API_DESC(SW_API_ARP_STATUS_SET) \
+    SW_API_DESC(SW_API_ARP_STATUS_GET) \
+    SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET) \
+    SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET) \
+    SW_API_DESC(SW_API_PT_UNK_SA_CMD_SET) \
+    SW_API_DESC(SW_API_PT_UNK_SA_CMD_GET) \
+    SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \
+    SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET) \
+    SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \
+    SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET) \
+    SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) \
+    SW_API_DESC(SW_API_CPU_PORT_STATUS_GET) \
+    SW_API_DESC(SW_API_BC_TO_CPU_PORT_SET) \
+    SW_API_DESC(SW_API_BC_TO_CPU_PORT_GET) \
+    SW_API_DESC(SW_API_PPPOE_CMD_SET) \
+    SW_API_DESC(SW_API_PPPOE_CMD_GET) \
+    SW_API_DESC(SW_API_PPPOE_STATUS_SET) \
+    SW_API_DESC(SW_API_PPPOE_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_DHCP_SET) \
+    SW_API_DESC(SW_API_PT_DHCP_GET)
+#else
+#define MISC_API
+#define MISC_API_PARAM
+#endif
+
+#ifdef IN_LED
+#define LED_API \
+    SW_API_DEF(SW_API_LED_PATTERN_SET, garuda_led_ctrl_pattern_set), \
+    SW_API_DEF(SW_API_LED_PATTERN_GET, garuda_led_ctrl_pattern_get),
+
+#define LED_API_PARAM \
+    SW_API_DESC(SW_API_LED_PATTERN_SET) \
+    SW_API_DESC(SW_API_LED_PATTERN_GET)
+#else
+#define LED_API
+#define LED_API_PARAM
+#endif
+
+#define REG_API \
+    SW_API_DEF(SW_API_PHY_GET, garuda_phy_get), \
+    SW_API_DEF(SW_API_PHY_SET, garuda_phy_set), \
+    SW_API_DEF(SW_API_REG_GET, garuda_reg_get), \
+    SW_API_DEF(SW_API_REG_SET, garuda_reg_set), \
+    SW_API_DEF(SW_API_REG_FIELD_GET, garuda_reg_field_get), \
+    SW_API_DEF(SW_API_REG_FIELD_SET, garuda_reg_field_set),
+
+#define REG_API_PARAM \
+    SW_API_DESC(SW_API_PHY_GET) \
+    SW_API_DESC(SW_API_PHY_SET) \
+    SW_API_DESC(SW_API_REG_GET) \
+    SW_API_DESC(SW_API_REG_SET) \
+    SW_API_DESC(SW_API_REG_FIELD_GET) \
+    SW_API_DESC(SW_API_REG_FIELD_SET)
+
+#define SSDK_API \
+    SW_API_DEF(SW_API_SWITCH_RESET, garuda_reset), \
+    SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \
+    PORTCONTROL_API \
+    VLAN_API \
+    PORTVLAN_API \
+    FDB_API \
+    ACL_API \
+    QOS_API \
+    IGMP_API \
+    LEAKY_API \
+    MIRROR_API \
+    RATE_API \
+    STP_API \
+    MIB_API \
+    MISC_API \
+    LED_API \
+    REG_API \
+    SW_API_DEF(SW_API_MAX, NULL),
+
+#define SSDK_PARAM  \
+    SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
+    MIB_API_PARAM \
+    LEAKY_API_PARAM \
+    MISC_API_PARAM \
+    IGMP_API_PARAM \
+    MIRROR_API_PARAM \
+    PORTCONTROL_API_PARAM \
+    PORTVLAN_API_PARAM \
+    VLAN_API_PARAM \
+    FDB_API_PARAM \
+    QOS_API_PARAM \
+    RATE_API_PARAM \
+    STP_API_PARAM \
+    ACL_API_PARAM \
+    LED_API_PARAM \
+    REG_API_PARAM \
+    SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#if (defined(USER_MODE) && defined(KERNEL_MODULE))
+#undef SSDK_API
+#undef SSDK_PARAM
+
+#define SSDK_API \
+    REG_API \
+    SW_API_DEF(SW_API_MAX, NULL),
+
+#define SSDK_PARAM  \
+    REG_API_PARAM \
+    SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _GARUDA_API_H_ */
diff --git a/qca-ssdk/include/hsl/garuda/garuda_fdb.h b/qca-ssdk/include/hsl/garuda/garuda_fdb.h
new file mode 100755
index 0000000..b50d2fc
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_fdb.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_fdb GARUDA_FDB
+ * @{
+ */
+#ifndef _GARUDA_FDB_H_
+#define _GARUDA_FDB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_fdb.h"
+
+    sw_error_t
+    garuda_fdb_init(a_uint32_t dev_id);
+
+#ifdef IN_FDB
+#define GARUDA_FDB_INIT(rv, dev_id) \
+    { \
+        rv = garuda_fdb_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define GARUDA_FDB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    garuda_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_fdb_del_by_mac(a_uint32_t dev_id,
+                          const fal_fdb_entry_t *entry);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t *enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _GARUDA_FDB_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/garuda/garuda_igmp.h b/qca-ssdk/include/hsl/garuda/garuda_igmp.h
new file mode 100755
index 0000000..4872304
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_igmp.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_igmp GARUDA_IGMP
+ * @{
+ */
+#ifndef _GARUDA_IGMP_H_
+#define _GARUDA_IGMP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_igmp.h"
+
+    sw_error_t
+    garuda_igmp_init(a_uint32_t dev_id);
+
+#ifdef IN_IGMP
+#define GARUDA_IGMP_INIT(rv, dev_id) \
+    { \
+        rv = garuda_igmp_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define GARUDA_IGMP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _GARUDA_IGMP_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/garuda/garuda_init.h b/qca-ssdk/include/hsl/garuda/garuda_init.h
new file mode 100755
index 0000000..b724501
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_init.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_init GARUDA_INIT
+ * @{
+ */
+#ifndef _GARUDA_INIT_H_
+#define _GARUDA_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+    sw_error_t
+    garuda_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+    sw_error_t
+    garuda_cleanup(a_uint32_t dev_id);
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    garuda_reset(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _GARUDA_INIT_H_ */
+
diff --git a/qca-ssdk/include/hsl/garuda/garuda_leaky.h b/qca-ssdk/include/hsl/garuda/garuda_leaky.h
new file mode 100755
index 0000000..dfd95ec
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_leaky.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_leaky GARUDA_LEAKY
+ * @{
+ */
+#ifndef _GARUDA_LEAKY_H_
+#define _GARUDA_LEAKY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_leaky.h"
+
+    sw_error_t garuda_leaky_init(a_uint32_t dev_id);
+
+#ifdef IN_LEAKY
+#define GARUDA_LEAKY_INIT(rv, dev_id) \
+    { \
+        rv = garuda_leaky_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define GARUDA_LEAKY_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    garuda_uc_leaky_mode_set(a_uint32_t dev_id,
+                             fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_uc_leaky_mode_get(a_uint32_t dev_id,
+                             fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_mc_leaky_mode_set(a_uint32_t dev_id,
+                             fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_mc_leaky_mode_get(a_uint32_t dev_id,
+                             fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _GARUDA_LEAKY_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/garuda/garuda_led.h b/qca-ssdk/include/hsl/garuda/garuda_led.h
new file mode 100755
index 0000000..16340bf
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_led.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _GARUDA_LED_H_
+#define _GARUDA_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_led.h"
+
+    sw_error_t
+    garuda_led_init(a_uint32_t dev_id);
+
+#ifdef IN_LED
+#define GARUDA_LED_INIT(rv, dev_id) \
+    { \
+        rv = garuda_led_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define GARUDA_LED_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    garuda_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                                led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                                led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _GARUDA_LED_H_ */
diff --git a/qca-ssdk/include/hsl/garuda/garuda_mib.h b/qca-ssdk/include/hsl/garuda/garuda_mib.h
new file mode 100755
index 0000000..3fc578a
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_mib.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_mib GARUDA_MIB
+ * @{
+ */
+#ifndef _GARUDA_MIB_H_
+#define _GARUDA_MIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mib.h"
+
+    sw_error_t
+    garuda_mib_init(a_uint32_t dev_id);
+
+#ifdef IN_MIB
+#define GARUDA_MIB_INIT(rv, dev_id) \
+    { \
+        rv = garuda_mib_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define GARUDA_MIB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    garuda_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_mib_info_t * mib_info );
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_mib_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_mib_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _GARUDA_MIB_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/garuda/garuda_mirror.h b/qca-ssdk/include/hsl/garuda/garuda_mirror.h
new file mode 100755
index 0000000..00f3901
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_mirror.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_mirror GARUDA_MIRROR
+ * @{
+ */
+#ifndef _GARUDA_MIRROR_H_
+#define _GARUDA_MIRROR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_mirror.h"
+
+    sw_error_t garuda_mirr_init(a_uint32_t dev_id);
+
+#ifdef IN_MIRROR
+#define GARUDA_MIRR_INIT(rv, dev_id) \
+    { \
+        rv = garuda_mirr_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define GARUDA_MIRR_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    garuda_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _GARUDA_MIRROR_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/garuda/garuda_misc.h b/qca-ssdk/include/hsl/garuda/garuda_misc.h
new file mode 100755
index 0000000..26ee619
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_misc.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _GARUDA_MISC_H_
+#define _GARUDA_MISC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_misc.h"
+
+    sw_error_t garuda_misc_init(a_uint32_t dev_id);
+
+#ifdef IN_MISC
+#define GARUDA_MISC_INIT(rv, dev_id) \
+    { \
+        rv = garuda_misc_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define GARUDA_MISC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    garuda_arp_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_arp_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_fwd_cmd_t cmd);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_fwd_cmd_t * cmd);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _GARUDA_MISC_H_ */
diff --git a/qca-ssdk/include/hsl/garuda/garuda_port_ctrl.h b/qca-ssdk/include/hsl/garuda/garuda_port_ctrl.h
new file mode 100755
index 0000000..ebfec94
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_port_ctrl.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_port_ctrl GARUDA_PORT_CONTROL
+ * @{
+ */
+#ifndef _GARUDA_PORT_CTRL_H_
+#define _GARUDA_PORT_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_port_ctrl.h"
+
+    sw_error_t garuda_port_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTCONTROL
+#define GARUDA_PORT_CTRL_INIT(rv, dev_id) \
+    { \
+        rv = garuda_port_ctrl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define GARUDA_PORT_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_port_duplex_t duplex);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_port_duplex_t * pduplex);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_speed_t speed);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_speed_t * pspeed);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * status);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
+
+    HSL_LOCAL sw_error_t
+    garuda_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t autoadv);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * autoadv);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_flowctrl_forcemode_set(a_uint32_t dev_id,
+                                       fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_flowctrl_forcemode_get(a_uint32_t dev_id,
+                                       fal_port_t port_id,
+                                       a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    garuda_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+                    fal_cable_status_t *cable_status, a_uint32_t *cable_len);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _GARUDA_PORT_CTRL_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/garuda/garuda_portvlan.h b/qca-ssdk/include/hsl/garuda/garuda_portvlan.h
new file mode 100755
index 0000000..9fa278b
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_portvlan.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+ * @defgroup garuda_port_vlan GARUDA_PORT_VLAN
+ * @{
+ */
+#ifndef _GARUDA_PORTVLAN_H_
+#define _GARUDA_PORTVLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_portvlan.h"
+
+    sw_error_t garuda_portvlan_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTVLAN
+#define GARUDA_PORTVLAN_INIT(rv, dev_id) \
+    { \
+        rv = garuda_portvlan_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define GARUDA_PORTVLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_1qmode_t port_1qmode);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_1qmode_t * pport_1qmode);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_pt_1q_egmode_t port_egvlanmode);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_pt_1q_egmode_t * pport_egvlanmode);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t mem_port_id);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t mem_port_id);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_pbmp_t mem_port_map);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_pbmp_t * mem_port_map);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t vid);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * vid);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                      a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    garuda_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ATHENA_PORTVLAN_H */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/garuda/garuda_qos.h b/qca-ssdk/include/hsl/garuda/garuda_qos.h
new file mode 100755
index 0000000..2b60f50
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_qos.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_qos GARUDA_QOS
+ * @{
+ */
+#ifndef _GARUDA_QOS_H_
+#define _GARUDA_QOS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_qos.h"
+
+    sw_error_t garuda_qos_init(a_uint32_t dev_id);
+
+#ifdef IN_QOS
+#define GARUDA_QOS_INIT(rv, dev_id) \
+    { \
+        rv = garuda_qos_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define GARUDA_QOS_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_sch_mode_set(a_uint32_t dev_id,
+                            fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_sch_mode_get(a_uint32_t dev_id,
+                            fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_queue_tx_buf_status_set(a_uint32_t dev_id,
+                                       fal_port_t port_id, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_queue_tx_buf_status_get(a_uint32_t dev_id,
+                                       fal_port_t port_id,
+                                       a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                      a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                      a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_queue_t queue_id,
+                                   a_uint32_t * number);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_queue_t queue_id,
+                                   a_uint32_t * number);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t * number);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t * number);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+                               fal_queue_t queue);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+                               fal_queue_t * queue);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+                                 fal_queue_t queue);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+                                 fal_queue_t * queue);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_qos_mode_t mode, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_qos_mode_t mode, a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_qos_mode_t mode, a_uint32_t pri);
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_qos_mode_t mode, a_uint32_t * pri);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_uint32_t up);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_uint32_t * up);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _GARUDA_QOS_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/garuda/garuda_rate.h b/qca-ssdk/include/hsl/garuda/garuda_rate.h
new file mode 100755
index 0000000..eb76efa
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_rate.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_rate GARUDA_RATE
+ * @{
+ */
+#ifndef _GARUDA_RATE_H_
+#define _GARUDA_RATE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_rate.h"
+
+    sw_error_t garuda_rate_init(a_uint32_t dev_id);
+
+#ifdef IN_RATE
+#define GARUDA_RATE_INIT(rv, dev_id) \
+    { \
+        rv = garuda_rate_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define GARUDA_RATE_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    garuda_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_uint32_t * speed,
+                               a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_uint32_t * speed,
+                               a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * speed, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * speed, a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * speed, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * speed, a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_storm_type_t storm_type, a_bool_t enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_storm_type_t storm_type, a_bool_t * enable);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * rate_in_pps);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * rate_in_pps);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _GARUDA_RATE_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/garuda/garuda_reduced_acl.h b/qca-ssdk/include/hsl/garuda/garuda_reduced_acl.h
new file mode 100755
index 0000000..08be794
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_reduced_acl.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _GARUDA_REDUCED_ACL_H_
+#define _GARUDA_REDUCED_ACL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+
+    sw_error_t
+    garuda_acl_rule_write(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+                          a_uint32_t msk[8]);
+
+    sw_error_t
+    garuda_acl_action_write(a_uint32_t dev_id, a_uint32_t act_idx,
+                            a_uint32_t act);
+
+    sw_error_t
+    garuda_acl_slct_write(a_uint32_t dev_id, a_uint32_t slct_idx,
+                          a_uint32_t slct[8]);
+
+    sw_error_t
+    garuda_acl_rule_read(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+                         a_uint32_t msk[8]);
+
+    sw_error_t
+    garuda_acl_action_read(a_uint32_t dev_id, a_uint32_t act_idx,
+                           a_uint32_t * act);
+
+    sw_error_t
+    garuda_acl_slct_read(a_uint32_t dev_id, a_uint32_t slct_idx,
+                         a_uint32_t slct[8]);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _GARUDA_REDUCED_ACL_H_ */
+
diff --git a/qca-ssdk/include/hsl/garuda/garuda_reg.h b/qca-ssdk/include/hsl/garuda/garuda_reg.h
new file mode 100755
index 0000000..3216970
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_reg.h
@@ -0,0 +1,3614 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _GARUDA_REG_H_
+#define _GARUDA_REG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#define MAX_ENTRY_LEN 128
+
+#define HSL_RW 1
+#define HSL_RO 0
+
+
+    /* GARUDA Mask Control Register */
+#define MASK_CTL                  "mask"
+#define MASK_CTL_ID               0
+#define MASK_CTL_OFFSET           0x0000
+#define MASK_CTL_E_LENGTH         4
+#define MASK_CTL_E_OFFSET         0
+#define MASK_CTL_NR_E             1
+
+#define SOFT_RST                              "mask_rst"
+#define MASK_CTL_SOFT_RST_BOFFSET             31
+#define MASK_CTL_SOFT_RST_BLEN                1
+#define MASK_CTL_SOFT_RST_FLAG                HSL_RW
+
+#define MII_CLK5_SEL                          "mask_clk5s"
+#define MASK_CTL_MII_CLK5_SEL_BOFFSET         21
+#define MASK_CTL_MII_CLK5_SEL_BLEN            1
+#define MASK_CTL_MII_CLK5_SEL_FLAG            HSL_RW
+
+#define MII_CLK0_SEL                          "mask_clk0s"
+#define MASK_CTL_MII_CLK0_SEL_BOFFSET         20
+#define MASK_CTL_MII_CLK0_SEL_BLEN            1
+#define MASK_CTL_MII_CLK0_SEL_FLAG            HSL_RW
+
+#define LOAD_EEPROM                           "mask_ldro"
+#define MASK_CTL_LOAD_EEPROM_BOFFSET          16
+#define MASK_CTL_LOAD_EEPROM_BLEN             1
+#define MASK_CTL_LOAD_EEPROM_FLAG             HSL_RW
+
+#define DEVICE_ID                             "mask_did"
+#define MASK_CTL_DEVICE_ID_BOFFSET            8
+#define MASK_CTL_DEVICE_ID_BLEN               8
+#define MASK_CTL_DEVICE_ID_FLAG               HSL_RO
+
+#define REV_ID                                "mask_rid"
+#define MASK_CTL_REV_ID_BOFFSET               0
+#define MASK_CTL_REV_ID_BLEN                  8
+#define MASK_CTL_REV_ID_FLAG                  HSL_RO
+
+
+    /* GARUDA Mask Control Register */
+#define POSTRIP                  "postrip"
+#define POSTRIP_ID               0
+#define POSTRIP_OFFSET           0x0008
+#define POSTRIP_E_LENGTH         4
+#define POSTRIP_E_OFFSET         0
+#define POSTRIP_NR_E             1
+
+#define POWER_ON_SEL                           "postrip_sel"
+#define POSTRIP_POWER_ON_SEL_BOFFSET           31
+#define POSTRIP_POWER_ON_SEL_BLEN              1
+#define POSTRIP_POWER_ON_SEL_FLAG              HSL_RW
+
+#define RXDELAY_S1                             "postrip_rx_s1"
+#define POSTRIP_RXDELAY_S1_BOFFSET             26
+#define POSTRIP_RXDELAY_S1_BLEN                1
+#define POSTRIP_RXDELAY_S1_FLAG                HSL_RW
+
+#define SPI_EN                                 "postrip_spi"
+#define POSTRIP_SPI_EN_BOFFSET                 25
+#define POSTRIP_SPI_EN_BLEN                    1
+#define POSTRIP_SPI_EN_FLAG                    HSL_RW
+
+#define LED_OPEN_EN                            "postrip_led"
+#define POSTRIP_LED_OPEN_EN_BOFFSET            24
+#define POSTRIP_LED_OPEN_EN_BLEN               1
+#define POSTRIP_LED_OPEN_EN_FLAG               HSL_RW
+
+#define RXDELAY_S0                             "postrip_rx_s0"
+#define POSTRIP_RXDELAY_S0_BOFFSET             23
+#define POSTRIP_RXDELAY_S0_BLEN                1
+#define POSTRIP_RXDELAY_S0_FLAG                HSL_RW
+
+#define TXDELAY_S1                             "postrip_tx_s1"
+#define POSTRIP_TXDELAY_S1_BOFFSET             22
+#define POSTRIP_TXDELAY_S1_BLEN                1
+#define POSTRIP_TXDELAY_S1_FLAG                HSL_RW
+
+#define TXDELAY_S0                             "postrip_tx_s0"
+#define POSTRIP_TXDELAY_S0_BOFFSET             21
+#define POSTRIP_TXDELAY_S0_BLEN                1
+#define POSTRIP_TXDELAY_S0_FLAG                HSL_RW
+
+#define LPW_EXIT                               "postrip_lpw_exit"
+#define POSTRIP_LPW_EXIT_BOFFSET               20
+#define POSTRIP_LPW_EXIT_BLEN                  1
+#define POSTRIP_LPW_EXIT_FLAG                  HSL_RW
+
+#define PHY_PLL_ON                             "postrip_phy_pll"
+#define POSTRIP_PHY_PLL_ON_BOFFSET             19
+#define POSTRIP_PHY_PLL_ON_BLEN                1
+#define POSTRIP_PHY_PLL_ON_FLAG                HSL_RW
+
+#define MAN_ENABLE                             "postrip_man_en"
+#define POSTRIP_MAN_ENABLE_BOFFSET             18
+#define POSTRIP_MAN_ENABLE_BLEN                1
+#define POSTRIP_MAN_ENABLE_FLAG                HSL_RW
+
+#define LPW_STATE_EN                           "postrip_lpw_state"
+#define POSTRIP_LPW_STATE_EN_BOFFSET           17
+#define POSTRIP_LPW_STATE_EN_BLEN              1
+#define POSTRIP_LPW_STATE_EN_FLAG              HSL_RW
+
+#define POWER_DOWN_HW                          "postrip_power_down"
+#define POSTRIP_POWER_DOWN_HW_BOFFSET          16
+#define POSTRIP_POWER_DOWN_HW_BLEN             1
+#define POSTRIP_POWER_DOWN_HW_FLAG             HSL_RW
+
+#define MAC5_PHY_MODE                          "postrip_mac5_phy"
+#define POSTRIP_MAC5_PHY_MODE_BOFFSET          15
+#define POSTRIP_MAC5_PHY_MODE_BLEN             1
+#define POSTRIP_MAC5_PHY_MODE_FLAG             HSL_RW
+
+#define MAC5_MAC_MODE                          "postrip_mac5_mac"
+#define POSTRIP_MAC5_MAC_MODE_BOFFSET          14
+#define POSTRIP_MAC5_MAC_MODE_BLEN             1
+#define POSTRIP_MAC5_MAC_MODE_FLAG             HSL_RW
+
+#define DBG_MODE_I                             "postrip_dbg"
+#define POSTRIP_DBG_MODE_I_BOFFSET             13
+#define POSTRIP_DBG_MODE_I_BLEN                1
+#define POSTRIP_DBG_MODE_I_FLAG                HSL_RW
+
+#define HIB_PULSE_HW                           "postrip_hib"
+#define POSTRIP_HIB_PULSE_HW_BOFFSET           12
+#define POSTRIP_HIB_PULSE_HW_BLEN              1
+#define POSTRIP_HIB_PULSE_HW_FLAG              HSL_RW
+
+#define SEL_CLK25M                             "postrip_clk25"
+#define POSTRIP_SEL_CLK25M_BOFFSET             11
+#define POSTRIP_SEL_CLK25M_BLEN                1
+#define POSTRIP_SEL_CLK25M_FLAG                HSL_RW
+
+#define GATE_25M_EN                            "postrip_gate25"
+#define POSTRIP_GATE_25M_EN_BOFFSET            10
+#define POSTRIP_GATE_25M_EN_BLEN               1
+#define POSTRIP_GATE_25M_EN_FLAG               HSL_RW
+
+#define SEL_ANA_RST                            "postrip_sel_ana"
+#define POSTRIP_SEL_ANA_RST_BOFFSET            9
+#define POSTRIP_SEL_ANA_RST_BLEN               1
+#define POSTRIP_SEL_ANA_RST_FLAG               HSL_RW
+
+#define SERDES_EN                              "postrip_serdes_en"
+#define POSTRIP_SERDES_EN_BOFFSET              8
+#define POSTRIP_SERDES_EN_BLEN                 1
+#define POSTRIP_SERDES_EN_FLAG                 HSL_RW
+
+#define RGMII_TXCLK_DELAY_EN                   "postrip_tx_delay"
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_BOFFSET   7
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_BLEN      1
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_FLAG      HSL_RW
+
+#define RGMII_RXCLK_DELAY_EN                   "postrip_rx_delay"
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_BOFFSET   6
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_BLEN      1
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_FLAG      HSL_RW
+
+#define RTL_MODE                               "postrip_rtl"
+#define POSTRIP_RTL_MODE_BOFFSET               5
+#define POSTRIP_RTL_MODE_BLEN                  1
+#define POSTRIP_RTL_MODE_FLAG                  HSL_RW
+
+#define MAC0_MAC_MODE                          "postrip_mac0_mac"
+#define POSTRIP_MAC0_MAC_MODE_BOFFSET          4
+#define POSTRIP_MAC0_MAC_MODE_BLEN             1
+#define POSTRIP_MAC0_MAC_MODE_FLAG             HSL_RW
+
+#define PHY4_RGMII_EN                          "postrip_phy4_rgmii"
+#define POSTRIP_PHY4_RGMII_EN_BOFFSET          3
+#define POSTRIP_PHY4_RGMII_EN_BLEN             1
+#define POSTRIP_PHY4_RGMII_EN_FLAG             HSL_RW
+
+#define PHY4_GMII_EN                           "postrip_phy4_gmii"
+#define POSTRIP_PHY4_GMII_EN_BOFFSET           2
+#define POSTRIP_PHY4_GMII_EN_BLEN              1
+#define POSTRIP_PHY4_GMII_EN_FLAG              HSL_RW
+
+#define MAC0_RGMII_EN                          "postrip_mac0_rgmii"
+#define POSTRIP_MAC0_RGMII_EN_BOFFSET          1
+#define POSTRIP_MAC0_RGMII_EN_BLEN             1
+#define POSTRIP_MAC0_RGMII_EN_FLAG             HSL_RW
+
+#define MAC0_GMII_EN                           "postrip_mac0_gmii"
+#define POSTRIP_MAC0_GMII_EN_BOFFSET           0
+#define POSTRIP_MAC0_GMII_EN_BLEN              1
+#define POSTRIP_MAC0_GMII_EN_FLAG              HSL_RW
+
+
+
+    /* Global Interrupt Register */
+#define GLOBAL_INT                "gint"
+#define GLOBAL_INT_ID             1
+#define GLOBAL_INT_OFFSET         0x0010
+#define GLOBAL_INT_E_LENGTH       4
+#define GLOBAL_INT_E_OFFSET       0
+#define GLOBAL_INT_NR_E           1
+
+#define GLB_QM_ERR_CNT                            "gint_qmen"
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BOFFSET         24
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BLEN            8
+#define GLOBAL_INT_GLB_QM_ERR_CNT_FLAG            HSL_RO
+
+#define GLB_LOOKUP_ERR                            "gint_glblper"
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BOFFSET         17
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BLEN            1
+#define GLOBAL_INT_GLB_LOOKUP_ERR_FLAG            HSL_RW
+
+#define GLB_QM_ERR                                "gint_glbqmer"
+#define GLOBAL_INT_GLB_QM_ERR_BOFFSET             16
+#define GLOBAL_INT_GLB_QM_ERR_BLEN                1
+#define GLOBAL_INT_GLB_QM_ERR_FLAG                HSL_RW
+
+#define GLB_HW_INI_DONE                           "gint_hwid"
+#define GLOBAL_INT_GLB_HW_INI_DONE_BOFFSET        14
+#define GLOBAL_INT_GLB_HW_INI_DONE_BLEN           1
+#define GLOBAL_INT_GLB_HW_INI_DONE_FLAG           HSL_RW
+
+#define GLB_MIB_INI                               "gint_mibi"
+#define GLOBAL_INT_GLB_MIB_INI_BOFFSET            13
+#define GLOBAL_INT_GLB_MIB_INI_BLEN               1
+#define GLOBAL_INT_GLB_MIB_INI_FLAG               HSL_RW
+
+#define GLB_MIB_DONE                              "gint_mibd"
+#define GLOBAL_INT_GLB_MIB_DONE_BOFFSET           12
+#define GLOBAL_INT_GLB_MIB_DONE_BLEN              1
+#define GLOBAL_INT_GLB_MIB_DONE_FLAG              HSL_RW
+
+#define GLB_BIST_DONE                             "gint_bisd"
+#define GLOBAL_INT_GLB_BIST_DONE_BOFFSET          11
+#define GLOBAL_INT_GLB_BIST_DONE_BLEN             1
+#define GLOBAL_INT_GLB_BIST_DONE_FLAG             HSL_RW
+
+#define GLB_VT_MISS_VIO                           "gint_vtms"
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BOFFSET        10
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BLEN           1
+#define GLOBAL_INT_GLB_VT_MISS_VIO_FLAG           HSL_RW
+
+#define GLB_VT_MEM_VIO                            "gint_vtme"
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BOFFSET         9
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BLEN            1
+#define GLOBAL_INT_GLB_VT_MEM_VIO_FLAG            HSL_RW
+
+#define GLB_VT_DONE                               "gint_vtd"
+#define GLOBAL_INT_GLB_VT_DONE_BOFFSET            8
+#define GLOBAL_INT_GLB_VT_DONE_BLEN               1
+#define GLOBAL_INT_GLB_VT_DONE_FLAG               HSL_RW
+
+#define GLB_QM_INI                                "gint_qmin"
+#define GLOBAL_INT_GLB_QM_INI_BOFFSET             7
+#define GLOBAL_INT_GLB_QM_INI_BLEN                1
+#define GLOBAL_INT_GLB_QM_INI_FLAG                HSL_RW
+
+#define GLB_AT_INI                                "gint_atin"
+#define GLOBAL_INT_GLB_AT_INI_BOFFSET             6
+#define GLOBAL_INT_GLB_AT_INI_BLEN                1
+#define GLOBAL_INT_GLB_AT_INI_FLAG                HSL_RW
+
+#define GLB_ARL_FULL                              "gint_arlf"
+#define GLOBAL_INT_GLB_ARL_FULL_BOFFSET           5
+#define GLOBAL_INT_GLB_ARL_FULL_BLEN              1
+#define GLOBAL_INT_GLB_ARL_FULL_FLAG              HSL_RW
+
+#define GLB_ARL_DONE                              "gint_arld"
+#define GLOBAL_INT_GLB_ARL_DONE_BOFFSET           4
+#define GLOBAL_INT_GLB_ARL_DONE_BLEN              1
+#define GLOBAL_INT_GLB_ARL_DONE_FLAG              HSL_RW
+
+#define GLB_MDIO_DONE                             "gint_mdid"
+#define GLOBAL_INT_GLB_MDIO_DONE_BOFFSET          3
+#define GLOBAL_INT_GLB_MDIO_DONE_BLEN             1
+#define GLOBAL_INT_GLB_MDIO_DONE_FLAG             HSL_RW
+
+#define GLB_PHY_INT                               "gint_phyi"
+#define GLOBAL_INT_GLB_PHY_INT_BOFFSET            2
+#define GLOBAL_INT_GLB_PHY_INT_BLEN               1
+#define GLOBAL_INT_GLB_PHY_INT_FLAG               HSL_RW
+
+#define GLB_EEPROM_ERR                            "gint_epei"
+#define GLOBAL_INT_GLB_EEPROM_ERR_BOFFSET         1
+#define GLOBAL_INT_GLB_EEPROM_ERR_BLEN            1
+#define GLOBAL_INT_GLB_EEPROM_ERR_FLAG            HSL_RW
+
+#define GLB_EEPROM_INT                            "gint_epi"
+#define GLOBAL_INT_GLB_EEPROM_INT_BOFFSET         0
+#define GLOBAL_INT_GLB_EEPROM_INT_BLEN            1
+#define GLOBAL_INT_GLB_EEPROM_INT_FLAG            HSL_RW
+
+
+    /* Global Interrupt Mask Register */
+#define GLOBAL_INT_MASK           "gintm"
+#define GLOBAL_INT_MASK_ID        2
+#define GLOBAL_INT_MASK_OFFSET    0x0014
+#define GLOBAL_INT_MASK_E_LENGTH  4
+#define GLOBAL_INT_MASK_E_OFFSET  0
+#define GLOBAL_INT_MASK_NR_E      1
+
+#define GLBM_LOOKUP_ERR                          "gintm_lpe"
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BOFFSET  17
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BLEN     1
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_FLAG     HSL_RW
+
+#define GLBM_QM_ERR                                "gintm_qme"
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BOFFSET        16
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BLEN           1
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_FLAG           HSL_RW
+
+#define GLBM_HW_INI_DONE                           "gintm_hwid"
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BOFFSET   14
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BLEN      1
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_FLAG      HSL_RW
+
+#define GLBM_MIB_INI                               "gintm_mibi"
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BOFFSET       13
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BLEN          1
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_FLAG          HSL_RW
+
+#define GLBM_MIB_DONE                              "gintm_mibd"
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BOFFSET      12
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BLEN         1
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_FLAG         HSL_RW
+
+#define GLBM_BIST_DONE                             "gintm_bisd"
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BOFFSET     11
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BLEN        1
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_FLAG        HSL_RW
+
+#define GLBM_VT_MISS_VIO                           "gintm_vtms"
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BOFFSET   10
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BLEN      1
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_FLAG      HSL_RW
+
+#define GLBM_VT_MEM_VIO                            "gintm_vtme"
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BOFFSET    9
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BLEN       1
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_FLAG       HSL_RW
+
+#define GLBM_VT_DONE                               "gintm_vtd"
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BOFFSET       8
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BLEN          1
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_FLAG          HSL_RW
+
+#define GLBM_QM_INI                                "gintm_qmin"
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BOFFSET        7
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BLEN           1
+#define GLOBAL_INT_MASK_GLBM_QM_INI_FLAG           HSL_RW
+
+#define GLBM_AT_INI                                "gintm_atin"
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BOFFSET        6
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BLEN           1
+#define GLOBAL_INT_MASK_GLBM_AT_INI_FLAG           HSL_RW
+
+#define GLBM_ARL_FULL                              "gintm_arlf"
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BOFFSET      5
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BLEN         1
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_FLAG         HSL_RW
+
+#define GLBM_ARL_DONE                              "gintm_arld"
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BOFFSET      4
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BLEN         1
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_FLAG         HSL_RW
+
+#define GLBM_MDIO_DONE                             "gintm_mdid"
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BOFFSET     3
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BLEN        1
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_FLAG        HSL_RW
+
+#define GLBM_PHY_INT                               "gintm_phy"
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BOFFSET       2
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BLEN          1
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_FLAG          HSL_RW
+
+#define GLBM_EEPROM_ERR                            "gintm_epe"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BOFFSET    1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BLEN       1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_FLAG       HSL_RW
+
+#define GLBM_EEPROM_INT                            "gintm_ep"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BOFFSET    0
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BLEN       1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_FLAG       HSL_RW
+
+
+    /* Global MAC Address Register */
+#define GLOBAL_MAC_ADDR0           "gmac0"
+#define GLOBAL_MAC_ADDR0_ID        3
+#define GLOBAL_MAC_ADDR0_OFFSET    0x0020
+#define GLOBAL_MAC_ADDR0_E_LENGTH  4
+#define GLOBAL_MAC_ADDR0_E_OFFSET  0
+#define GLOBAL_MAC_ADDR0_NR_E      1
+
+#define GLB_BYTE4                                  "gmac_b4"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET         8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN            8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG            HSL_RW
+
+#define GLB_BYTE5                                  "gmac_b5"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET         0
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN            8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG            HSL_RW
+
+#define GLOBAL_MAC_ADDR1           "gmac1"
+#define GLOBAL_MAC_ADDR1_ID        4
+#define GLOBAL_MAC_ADDR1_OFFSET    0x0024
+#define GLOBAL_MAC_ADDR1_E_LENGTH  4
+#define GLOBAL_MAC_ADDR1_E_OFFSET  0
+#define GLOBAL_MAC_ADDR1_NR_E      1
+
+#define GLB_BYTE0                                  "gmac_b0"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET         24
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG            HSL_RW
+
+#define GLB_BYTE1                                  "gmac_b1"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET         16
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG            HSL_RW
+
+#define GLB_BYTE2                                  "gmac_b2"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET         8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG            HSL_RW
+
+#define GLB_BYTE3                                  "gmac_b3"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET         0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG            HSL_RW
+
+
+    /* Flood Mask Register */
+#define FLOOD_MASK                "fmask"
+#define FLOOD_MASK_ID             5
+#define FLOOD_MASK_OFFSET         0x002c
+#define FLOOD_MASK_E_LENGTH       4
+#define FLOOD_MASK_E_OFFSET       0
+#define FLOOD_MASK_NR_E           1
+
+#define BROAD_TO_CPU                        "fmask_btocpu"
+#define FLOOD_MASK_BROAD_TO_CPU_BOFFSET     26
+#define FLOOD_MASK_BROAD_TO_CPU_BLEN        1
+#define FLOOD_MASK_BROAD_TO_CPU_FLAG        HSL_RW
+
+#define ARL_MUL_LEAKY                       "fmask_amlky"
+#define FLOOD_MASK_ARL_MUL_LEAKY_BOFFSET    25
+#define FLOOD_MASK_ARL_MUL_LEAKY_BLEN       1
+#define FLOOD_MASK_ARL_MUL_LEAKY_FLAG       HSL_RW
+
+#define ARL_UNI_LEAKY                       "fmask_aulky"
+#define FLOOD_MASK_ARL_UNI_LEAKY_BOFFSET    24
+#define FLOOD_MASK_ARL_UNI_LEAKY_BLEN       1
+#define FLOOD_MASK_ARL_UNI_LEAKY_FLAG       HSL_RW
+
+#define MUL_FLOOD_DP                        "fmask_mfdp"
+#define FLOOD_MASK_MUL_FLOOD_DP_BOFFSET     16
+#define FLOOD_MASK_MUL_FLOOD_DP_BLEN        6
+#define FLOOD_MASK_MUL_FLOOD_DP_FLAG        HSL_RW
+
+#define IGMP_DP                             "fmask_igmpdp"
+#define FLOOD_MASK_IGMP_DP_BOFFSET          8
+#define FLOOD_MASK_IGMP_DP_BLEN             6
+#define FLOOD_MASK_IGMP_DP_FLAG             HSL_RW
+
+#define UNI_FLOOD_DP                        "fmask_ufdp"
+#define FLOOD_MASK_UNI_FLOOD_DP_BOFFSET     0
+#define FLOOD_MASK_UNI_FLOOD_DP_BLEN        6
+#define FLOOD_MASK_UNI_FLOOD_DP_FLAG        HSL_RW
+
+
+    /* Global Control Register */
+#define GLOBAL_CTL                "gctl"
+#define GLOBAL_CTL_ID             5
+#define GLOBAL_CTL_OFFSET         0x0030
+#define GLOBAL_CTL_E_LENGTH       4
+#define GLOBAL_CTL_E_OFFSET       0
+#define GLOBAL_CTL_NR_E           1
+
+#define WEIGHT_PRIORITY                       "gctl_wpri"
+#define GLOBAL_CTL_WEIGHT_PRIORITY_BOFFSET    31
+#define GLOBAL_CTL_WEIGHT_PRIORITY_BLEN       1
+#define GLOBAL_CTL_WEIGHT_PRIORITY_FLAG       HSL_RW
+
+#define RATE_DROP_EN                          "gctl_rden"
+#define GLOBAL_CTL_RATE_DROP_EN_BOFFSET       30
+#define GLOBAL_CTL_RATE_DROP_EN_BLEN          1
+#define GLOBAL_CTL_RATE_DROP_EN_FLAG          HSL_RW
+
+#define QM_PRI_MODE                           "gctl_qmpm"
+#define GLOBAL_CTL_QM_PRI_MODE_BOFFSET        29
+#define GLOBAL_CTL_QM_PRI_MODE_BLEN           1
+#define GLOBAL_CTL_QM_PRI_MODE_FLAG           HSL_RW
+
+#define MIX_PRIORITY                          "gctl_mpri"
+#define GLOBAL_CTL_MIX_PRIORITY_BOFFSET       28
+#define GLOBAL_CTL_MIX_PRIORITY_BLEN          1
+#define GLOBAL_CTL_MIX_PRIORITY_FLAG          HSL_RW
+
+#define RATE_CRE_LIMIT                        "gctl_rcrl"
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BOFFSET     26
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BLEN        2
+#define GLOBAL_CTL_RATE_CRE_LIMIT_FLAG        HSL_RW
+
+#define RATE_TIME_SLOT                        "gctl_rtms"
+#define GLOBAL_CTL_RATE_TIME_SLOT_BOFFSET     24
+#define GLOBAL_CTL_RATE_TIME_SLOT_BLEN        2
+#define GLOBAL_CTL_RATE_TIME_SLOT_FLAG        HSL_RW
+
+#define RELOAD_TIMER                          "gctl_rdtm"
+#define GLOBAL_CTL_RELOAD_TIMER_BOFFSET       20
+#define GLOBAL_CTL_RELOAD_TIMER_BLEN          4
+#define GLOBAL_CTL_RELOAD_TIMER_FLAG          HSL_RW
+
+#define QM_CNT_LOCK                           "gctl_qmcl"
+#define GLOBAL_CTL_QM_CNT_LOCK_BOFFSET        19
+#define GLOBAL_CTL_QM_CNT_LOCK_BLEN           1
+#define GLOBAL_CTL_QM_CNT_LOCK_FLAG           HSL_RO
+
+#define BROAD_DROP_EN                         "gctl_bden"
+#define GLOBAL_CTL_BROAD_DROP_EN_BOFFSET      18
+#define GLOBAL_CTL_BROAD_DROP_EN_BLEN         1
+#define GLOBAL_CTL_BROAD_DROP_EN_FLAG         HSL_RW
+
+#define MAX_FRAME_SIZE                        "gctl_mfsz"
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BOFFSET     0
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BLEN        14
+#define GLOBAL_CTL_MAX_FRAME_SIZE_FLAG        HSL_RW
+
+
+    /* Flow Control Register */
+#define FLOW_CTL                  "fctl"
+#define FLOW_CTL_ID               6
+#define FLOW_CTL_OFFSET           0x0034
+#define FLOW_CTL_E_LENGTH         4
+#define FLOW_CTL_E_OFFSET         0
+#define FLOW_CTL_NR_E             1
+
+#define TEST_PAUSE                            "fctl_tps"
+#define FLOW_CTL_TEST_PAUSE_BOFFSET           31
+#define FLOW_CTL_TEST_PAUSE_BLEN              1
+#define FLOW_CTL_TEST_PAUSE_FLAG              HSL_RW
+
+#define PORT_PAUSE_OFF_THRES                  "fctl_pofft"
+#define FLOW_CTL_PORT_PAUSE_OFF_THRES_BOFFSET 24
+#define FLOW_CTL_PORT_PAUSE_OFF_THRES_BLEN    7
+#define FLOW_CTL_PORT_PAUSE_OFF_THRES_FLAG    HSL_RW
+
+#define PORT_PAUSE_ON_THRES                   "fctl_pont"
+#define FLOW_CTL_PORT_PAUSE_ON_THRES_BOFFSET  16
+#define FLOW_CTL_PORT_PAUSE_ON_THRES_BLEN     7
+#define FLOW_CTL_PORT_PAUSE_ON_THRES_FLAG     HSL_RW
+
+#define GOL_PAUSE_OFF_THRES                   "fctl_gofft"
+#define FLOW_CTL_GOL_PAUSE_OFF_THRES_BOFFSET  8
+#define FLOW_CTL_GOL_PAUSE_OFF_THRES_BLEN     8
+#define FLOW_CTL_GOL_PAUSE_OFF_THRES_FLAG     HSL_RW
+
+#define GOL_PAUSE_ON_THRES                    "fctl_gont"
+#define FLOW_CTL_GOL_PAUSE_ON_THRES_BOFFSET   0
+#define FLOW_CTL_GOL_PAUSE_ON_THRES_BLEN      8
+#define FLOW_CTL_GOL_PAUSE_ON_THRES_FLAG      HSL_RW
+
+
+    /* QM Control Register */
+#define QM_CTL                    "qmct"
+#define QM_CTL_ID                 7
+#define QM_CTL_OFFSET             0x003c
+#define QM_CTL_E_LENGTH           4
+#define QM_CTL_E_OFFSET           0
+#define QM_CTL_NR_E               1
+
+#define QM_ERR_RST_EN                         "qmct_qeren"
+#define QM_CTL_QM_ERR_RST_EN_BOFFSET          31
+#define QM_CTL_QM_ERR_RST_EN_BLEN             1
+#define QM_CTL_QM_ERR_RST_EN_FLAG             HSL_RW
+
+#define LOOKUP_ERR_RST_EN                     "qmct_lpesen"
+#define QM_CTL_LOOKUP_ERR_RST_EN_BOFFSET      30
+#define QM_CTL_LOOKUP_ERR_RST_EN_BLEN         1
+#define QM_CTL_LOOKUP_ERR_RST_EN_FLAG         HSL_RW
+
+#define IGMP_CREAT_EN                         "qmct_igmpcrt"
+#define QM_CTL_IGMP_CREAT_EN_BOFFSET          22
+#define QM_CTL_IGMP_CREAT_EN_BLEN             1
+#define QM_CTL_IGMP_CREAT_EN_FLAG             HSL_RW
+
+#define ACL_EN                                "qmct_aclen"
+#define QM_CTL_ACL_EN_BOFFSET                 21
+#define QM_CTL_ACL_EN_BLEN                    1
+#define QM_CTL_ACL_EN_FLAG                    HSL_RW
+
+#define PPPOE_RDT_EN                          "qmct_pppoerdten"
+#define QM_CTL_PPPOE_RDT_EN_BOFFSET           20
+#define QM_CTL_PPPOE_RDT_EN_BLEN              1
+#define QM_CTL_PPPOE_RDT_EN_FLAG              HSL_RW
+
+#define IGMP_COPY_EN                          "qmct_igmpcpy"
+#define QM_CTL_IGMP_COPY_EN_BOFFSET           11
+#define QM_CTL_IGMP_COPY_EN_BLEN              1
+#define QM_CTL_IGMP_COPY_EN_FLAG              HSL_RW
+
+#define PPPOE_EN                              "qmct_pppoeen"
+#define QM_CTL_PPPOE_EN_BOFFSET               10
+#define QM_CTL_PPPOE_EN_BLEN                  1
+#define QM_CTL_PPPOE_EN_FLAG                  HSL_RW
+
+#define QM_FUNC_TEST                          "qmct_qmft"
+#define QM_CTL_QM_FUNC_TEST_BOFFSET           9
+#define QM_CTL_QM_FUNC_TEST_BLEN              1
+#define QM_CTL_QM_FUNC_TEST_FLAG              HSL_RW
+
+#define MS_FC_EN                              "qmct_msfe"
+#define QM_CTL_MS_FC_EN_BOFFSET               8
+#define QM_CTL_MS_FC_EN_BLEN                  1
+#define QM_CTL_MS_FC_EN_FLAG                  HSL_RW
+
+#define FLOW_DROP_EN                          "qmct_fden"
+#define QM_CTL_FLOW_DROP_EN_BOFFSET           7
+#define QM_CTL_FLOW_DROP_EN_BLEN              1
+#define QM_CTL_FLOW_DROP_EN_FLAG              HSL_RW
+
+#define MANAGE_VID_VIO_DROP_EN                "qmct_mden"
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BOFFSET 6
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BLEN    1
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_FLAG    HSL_RW
+
+#define FLOW_DROP_CNT                         "qmct_fdcn"
+#define QM_CTL_FLOW_DROP_CNT_BOFFSET          0
+#define QM_CTL_FLOW_DROP_CNT_BLEN             6
+#define QM_CTL_FLOW_DROP_CNT_FLAG             HSL_RW
+
+
+    /* Vlan Table Function Register */
+#define VLAN_TABLE_FUNC0           "vtbf0"
+#define VLAN_TABLE_FUNC0_ID        9
+#define VLAN_TABLE_FUNC0_OFFSET    0x0040
+#define VLAN_TABLE_FUNC0_E_LENGTH  4
+#define VLAN_TABLE_FUNC0_E_OFFSET  0
+#define VLAN_TABLE_FUNC0_NR_E      1
+
+#define VT_PRI_EN                              "vtbf_vtpen"
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET     31
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN        1
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG        HSL_RW
+
+#define VT_PRI                                 "vtbf_vtpri"
+#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET        28
+#define VLAN_TABLE_FUNC0_VT_PRI_BLEN           3
+#define VLAN_TABLE_FUNC0_VT_PRI_FLAG           HSL_RW
+
+#define VLAN_ID                                "vtbf_vid"
+#define VLAN_TABLE_FUNC0_VLAN_ID_BOFFSET       16
+#define VLAN_TABLE_FUNC0_VLAN_ID_BLEN          12
+#define VLAN_TABLE_FUNC0_VLAN_ID_FLAG          HSL_RW
+
+#define VT_PORT_NUM                            "vtbf_vtpn"
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BOFFSET   8
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BLEN      4
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_FLAG      HSL_RW
+
+#define VT_FULL_VIO                            "vtbf_vtflv"
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BOFFSET   4
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BLEN      1
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_FLAG      HSL_RW
+
+#define VT_BUSY                                "vtbf_vtbs"
+#define VLAN_TABLE_FUNC0_VT_BUSY_BOFFSET       3
+#define VLAN_TABLE_FUNC0_VT_BUSY_BLEN          1
+#define VLAN_TABLE_FUNC0_VT_BUSY_FLAG          HSL_RW
+
+#define VT_FUNC                                "vtbf_vtfc"
+#define VLAN_TABLE_FUNC0_VT_FUNC_BOFFSET       0
+#define VLAN_TABLE_FUNC0_VT_FUNC_BLEN          3
+#define VLAN_TABLE_FUNC0_VT_FUNC_FLAG          HSL_RW
+
+#define VLAN_TABLE_FUNC1           "vtbf1"
+#define VLAN_TABLE_FUNC1_ID        10
+#define VLAN_TABLE_FUNC1_OFFSET    0x0044
+#define VLAN_TABLE_FUNC1_E_LENGTH  4
+#define VLAN_TABLE_FUNC1_E_OFFSET  0
+#define VLAN_TABLE_FUNC1_NR_E      1
+
+#define VT_VALID                               "vtbf_vtvd"
+#define VLAN_TABLE_FUNC1_VT_VALID_BOFFSET      11
+#define VLAN_TABLE_FUNC1_VT_VALID_BLEN         1
+#define VLAN_TABLE_FUNC1_VT_VALID_FLAG         HSL_RW
+
+#define VID_MEM                                "vtbf_vidm"
+#define VLAN_TABLE_FUNC1_VID_MEM_BOFFSET       0
+#define VLAN_TABLE_FUNC1_VID_MEM_BLEN          10
+#define VLAN_TABLE_FUNC1_VID_MEM_FLAG          HSL_RW
+
+
+    /* Address Table Function Register */
+#define ADDR_TABLE_FUNC0           "atbf0"
+#define ADDR_TABLE_FUNC0_ID        11
+#define ADDR_TABLE_FUNC0_OFFSET    0x0050
+#define ADDR_TABLE_FUNC0_E_LENGTH  4
+#define ADDR_TABLE_FUNC0_E_OFFSET  0
+#define ADDR_TABLE_FUNC0_NR_E      1
+
+#define AT_ADDR_BYTE4                          "atbf_adb4"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 24
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE5                          "atbf_adb5"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 16
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG    HSL_RW
+
+#define AT_FULL_VIO                            "atbf_atfv"
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BOFFSET   12
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BLEN      1
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_FLAG      HSL_RW
+
+#define AT_PORT_NUM                            "atbf_atpn"
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BOFFSET   8
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BLEN      4
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_FLAG      HSL_RW
+
+#define FLUSH_ST_EN                            "atbf_fsen"
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BOFFSET   4
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BLEN      1
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_FLAG      HSL_RW
+
+#define AT_BUSY                                "atbf_atbs"
+#define ADDR_TABLE_FUNC0_AT_BUSY_BOFFSET       3
+#define ADDR_TABLE_FUNC0_AT_BUSY_BLEN          1
+#define ADDR_TABLE_FUNC0_AT_BUSY_FLAG          HSL_RW
+
+#define AT_FUNC                                "atbf_atfc"
+#define ADDR_TABLE_FUNC0_AT_FUNC_BOFFSET       0
+#define ADDR_TABLE_FUNC0_AT_FUNC_BLEN          3
+#define ADDR_TABLE_FUNC0_AT_FUNC_FLAG          HSL_RW
+
+#define ADDR_TABLE_FUNC1           "atbf1"
+#define ADDR_TABLE_FUNC1_ID        12
+#define ADDR_TABLE_FUNC1_OFFSET    0x0054
+#define ADDR_TABLE_FUNC1_E_LENGTH  4
+#define ADDR_TABLE_FUNC1_E_OFFSET  0
+#define ADDR_TABLE_FUNC1_NR_E      0
+
+#define AT_ADDR_BYTE0                          "atbf_adb0"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 24
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE1                          "atbf_adb1"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 16
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE2                          "atbf_adb2"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BOFFSET 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE3                          "atbf_adb3"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BOFFSET 0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_FLAG    HSL_RW
+
+#define ADDR_TABLE_FUNC2           "atbf2"
+#define ADDR_TABLE_FUNC2_ID        13
+#define ADDR_TABLE_FUNC2_OFFSET    0x0058
+#define ADDR_TABLE_FUNC2_E_LENGTH  4
+#define ADDR_TABLE_FUNC2_E_OFFSET  0
+#define ADDR_TABLE_FUNC2_NR_E      0
+
+#define COPY_TO_CPU                            "atbf_cpcpu"
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET   26
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN      1
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG      HSL_RW
+
+#define REDRCT_TO_CPU                          "atbf_rdcpu"
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 25
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN    1
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG    HSL_RW
+
+#define LEAKY_EN                               "atbf_lkyen"
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET      24
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN         1
+#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG         HSL_RW
+
+#define AT_STATUS                              "atbf_atsts"
+#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET     16
+#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN        4
+#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG        HSL_RW
+
+#define CLONE_EN                               "atbf_clone"
+#define ADDR_TABLE_FUNC2_CLONE_EN_BOFFSET      15
+#define ADDR_TABLE_FUNC2_CLONE_EN_BLEN         1
+#define ADDR_TABLE_FUNC2_CLONE_EN_FLAG         HSL_RW
+
+#define SA_DROP_EN                             "atbf_saden"
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BOFFSET    14
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BLEN       1
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_FLAG       HSL_RW
+
+#define MIRROR_EN                              "atbf_miren"
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BOFFSET     13
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BLEN        1
+#define ADDR_TABLE_FUNC2_MIRROR_EN_FLAG        HSL_RW
+
+#define AT_PRI_EN                              "atbf_atpen"
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BOFFSET     12
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BLEN        1
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_FLAG        HSL_RW
+
+#define AT_PRI                                 "atbf_atpri"
+#define ADDR_TABLE_FUNC2_AT_PRI_BOFFSET        10
+#define ADDR_TABLE_FUNC2_AT_PRI_BLEN           2
+#define ADDR_TABLE_FUNC2_AT_PRI_FLAG           HSL_RW
+
+#define DES_PORT                               "atbf_desp"
+#define ADDR_TABLE_FUNC2_DES_PORT_BOFFSET      0
+#define ADDR_TABLE_FUNC2_DES_PORT_BLEN         6
+#define ADDR_TABLE_FUNC2_DES_PORT_FLAG         HSL_RW
+
+
+    /* Address Table Control Register */
+#define ADDR_TABLE_CTL            "atbc"
+#define ADDR_TABLE_CTL_ID         14
+#define ADDR_TABLE_CTL_OFFSET     0x005C
+#define ADDR_TABLE_CTL_E_LENGTH   4
+#define ADDR_TABLE_CTL_E_OFFSET   0
+#define ADDR_TABLE_CTL_NR_E       1
+
+#define ARP_EN                                 "atbc_arpe"
+#define ADDR_TABLE_CTL_ARP_EN_BOFFSET          20
+#define ADDR_TABLE_CTL_ARP_EN_BLEN             1
+#define ADDR_TABLE_CTL_ARP_EN_FLAG             HSL_RW
+
+#define ARL_INI_EN                             "atbc_arlie"
+#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET      19
+#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN         1
+#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG         HSL_RW
+
+#define LEARN_CHANGE_EN                        "atbc_lcen"
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 18
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN    1
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG    HSL_RW
+
+#define AGE_EN                                 "atbc_agee"
+#define ADDR_TABLE_CTL_AGE_EN_BOFFSET          17
+#define ADDR_TABLE_CTL_AGE_EN_BLEN             1
+#define ADDR_TABLE_CTL_AGE_EN_FLAG             HSL_RW
+
+#define AGE_TIME                               "atbc_aget"
+#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET        0
+#define ADDR_TABLE_CTL_AGE_TIME_BLEN           16
+#define ADDR_TABLE_CTL_AGE_TIME_FLAG           HSL_RW
+
+
+    /* IP Priority Mapping Register */
+#define IP_PRI_MAPPING            "imap"
+#define IP_PRI_MAPPING_ID         15
+#define IP_PRI_MAPPING_OFFSET     0x0060
+#define IP_PRI_MAPPING_E_LENGTH   4
+#define IP_PRI_MAPPING_E_OFFSET   0
+#define IP_PRI_MAPPING_NR_E       1
+
+
+    /* IP Priority Mapping Register */
+#define IP_PRI_MAPPING0            "imap0"
+#define IP_PRI_MAPPING0_ID         15
+#define IP_PRI_MAPPING0_OFFSET     0x0060
+#define IP_PRI_MAPPING0_E_LENGTH   4
+#define IP_PRI_MAPPING0_E_OFFSET   0
+#define IP_PRI_MAPPING0_NR_E       0
+
+#define IP_0X3C                                "imap_ip3c"
+#define IP_PRI_MAPPING0_IP_0X3C_BOFFSET        30
+#define IP_PRI_MAPPING0_IP_0X3C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X3C_FLAG           HSL_RW
+
+#define IP_0X38                                "imap_ip38"
+#define IP_PRI_MAPPING0_IP_0X38_BOFFSET        28
+#define IP_PRI_MAPPING0_IP_0X38_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X38_FLAG           HSL_RW
+
+#define IP_0X34                                "imap_ip34"
+#define IP_PRI_MAPPING0_IP_0X34_BOFFSET        26
+#define IP_PRI_MAPPING0_IP_0X34_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X34_FLAG           HSL_RW
+
+#define IP_0X30                                "imap_ip30"
+#define IP_PRI_MAPPING0_IP_0X30_BOFFSET        24
+#define IP_PRI_MAPPING0_IP_0X30_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X30_FLAG           HSL_RW
+
+#define IP_0X2C                                "imap_ip2c"
+#define IP_PRI_MAPPING0_IP_0X2C_BOFFSET        22
+#define IP_PRI_MAPPING0_IP_0X2C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X2C_FLAG           HSL_RW
+
+#define IP_0X28                                "imap_ip28"
+#define IP_PRI_MAPPING0_IP_0X28_BOFFSET        20
+#define IP_PRI_MAPPING0_IP_0X28_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X28_FLAG           HSL_RW
+
+#define IP_0X24                                "imap_ip24"
+#define IP_PRI_MAPPING0_IP_0X24_BOFFSET        18
+#define IP_PRI_MAPPING0_IP_0X24_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X24_FLAG           HSL_RW
+
+#define IP_0X20                                "imap_ip20"
+#define IP_PRI_MAPPING0_IP_0X20_BOFFSET        16
+#define IP_PRI_MAPPING0_IP_0X20_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X20_FLAG           HSL_RW
+
+#define IP_0X1C                                "imap_ip1c"
+#define IP_PRI_MAPPING0_IP_0X1C_BOFFSET        14
+#define IP_PRI_MAPPING0_IP_0X1C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X1C_FLAG           HSL_RW
+
+#define IP_0X18                                "imap_ip18"
+#define IP_PRI_MAPPING0_IP_0X18_BOFFSET        12
+#define IP_PRI_MAPPING0_IP_0X18_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X18_FLAG           HSL_RW
+
+#define IP_0X14                                "imap_ip14"
+#define IP_PRI_MAPPING0_IP_0X14_BOFFSET        10
+#define IP_PRI_MAPPING0_IP_0X14_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X14_FLAG           HSL_RW
+
+#define IP_0X10                                "imap_ip10"
+#define IP_PRI_MAPPING0_IP_0X10_BOFFSET        8
+#define IP_PRI_MAPPING0_IP_0X10_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X10_FLAG           HSL_RW
+
+#define IP_0X0C                                "imap_ip0c"
+#define IP_PRI_MAPPING0_IP_0X0C_BOFFSET        6
+#define IP_PRI_MAPPING0_IP_0X0C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X0C_FLAG           HSL_RW
+
+#define IP_0X08                                "imap_ip08"
+#define IP_PRI_MAPPING0_IP_0X08_BOFFSET        4
+#define IP_PRI_MAPPING0_IP_0X08_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X08_FLAG           HSL_RW
+
+#define IP_0X04                                "imap_ip04"
+#define IP_PRI_MAPPING0_IP_0X04_BOFFSET        2
+#define IP_PRI_MAPPING0_IP_0X04_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X04_FLAG           HSL_RW
+
+#define IP_0X00                                "imap_ip00"
+#define IP_PRI_MAPPING0_IP_0X00_BOFFSET        0
+#define IP_PRI_MAPPING0_IP_0X00_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X00_FLAG           HSL_RW
+
+#define IP_PRI_MAPPING1            "imap1"
+#define IP_PRI_MAPPING1_ID         16
+#define IP_PRI_MAPPING1_OFFSET     0x0064
+#define IP_PRI_MAPPING1_E_LENGTH   4
+#define IP_PRI_MAPPING1_E_OFFSET   0
+#define IP_PRI_MAPPING1_NR_E       0
+
+#define IP_0X7C                                "imap_ip7c"
+#define IP_PRI_MAPPING1_IP_0X7C_BOFFSET        30
+#define IP_PRI_MAPPING1_IP_0X7C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X7C_FLAG           HSL_RW
+
+#define IP_0X78                                "imap_ip78"
+#define IP_PRI_MAPPING1_IP_0X78_BOFFSET        28
+#define IP_PRI_MAPPING1_IP_0X78_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X78_FLAG           HSL_RW
+
+#define IP_0X74                                "imap_ip74"
+#define IP_PRI_MAPPING1_IP_0X74_BOFFSET        26
+#define IP_PRI_MAPPING1_IP_0X74_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X74_FLAG           HSL_RW
+
+#define IP_0X70                                "imap_ip70"
+#define IP_PRI_MAPPING1_IP_0X70_BOFFSET        24
+#define IP_PRI_MAPPING1_IP_0X70_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X70_FLAG           HSL_RW
+
+#define IP_0X6C                                "imap_ip6c"
+#define IP_PRI_MAPPING1_IP_0X6C_BOFFSET        22
+#define IP_PRI_MAPPING1_IP_0X6C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X6C_FLAG           HSL_RW
+
+#define IP_0X68                                "imap_ip68"
+#define IP_PRI_MAPPING1_IP_0X68_BOFFSET        20
+#define IP_PRI_MAPPING1_IP_0X68_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X68_FLAG           HSL_RW
+
+#define IP_0X64                                "imap_ip64"
+#define IP_PRI_MAPPING1_IP_0X64_BOFFSET        18
+#define IP_PRI_MAPPING1_IP_0X64_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X64_FLAG           HSL_RW
+
+#define IP_0X60                                "imap_ip60"
+#define IP_PRI_MAPPING1_IP_0X60_BOFFSET        16
+#define IP_PRI_MAPPING1_IP_0X60_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X60_FLAG           HSL_RW
+
+#define IP_0X5C                                "imap_ip5c"
+#define IP_PRI_MAPPING1_IP_0X5C_BOFFSET        14
+#define IP_PRI_MAPPING1_IP_0X5C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X5C_FLAG           HSL_RW
+
+#define IP_0X58                                "imap_ip58"
+#define IP_PRI_MAPPING1_IP_0X58_BOFFSET        12
+#define IP_PRI_MAPPING1_IP_0X58_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X58_FLAG           HSL_RW
+
+#define IP_0X54                                "imap_ip54"
+#define IP_PRI_MAPPING1_IP_0X54_BOFFSET        10
+#define IP_PRI_MAPPING1_IP_0X54_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X54_FLAG           HSL_RW
+
+#define IP_0X50                                "imap_ip50"
+#define IP_PRI_MAPPING1_IP_0X50_BOFFSET        8
+#define IP_PRI_MAPPING1_IP_0X50_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X50_FLAG           HSL_RW
+
+#define IP_0X4C                                "imap_ip4c"
+#define IP_PRI_MAPPING1_IP_0X4C_BOFFSET        6
+#define IP_PRI_MAPPING1_IP_0X4C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X4C_FLAG           HSL_RW
+
+#define IP_0X48                                "imap_ip48"
+#define IP_PRI_MAPPING1_IP_0X48_BOFFSET        4
+#define IP_PRI_MAPPING1_IP_0X48_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X48_FLAG           HSL_RW
+
+#define IP_0X44                                "imap_ip44"
+#define IP_PRI_MAPPING1_IP_0X44_BOFFSET        2
+#define IP_PRI_MAPPING1_IP_0X44_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X44_FLAG           HSL_RW
+
+#define IP_0X40                                "imap_ip40"
+#define IP_PRI_MAPPING1_IP_0X40_BOFFSET        0
+#define IP_PRI_MAPPING1_IP_0X40_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X40_FLAG           HSL_RW
+
+
+#define IP_PRI_MAPPING2            "imap2"
+#define IP_PRI_MAPPING2_ID         17
+#define IP_PRI_MAPPING2_OFFSET     0x0068
+#define IP_PRI_MAPPING2_E_LENGTH   4
+#define IP_PRI_MAPPING2_E_OFFSET   0
+#define IP_PRI_MAPPING2_NR_E       0
+
+#define IP_0XBC                                "imap_ipbc"
+#define IP_PRI_MAPPING2_IP_0XBC_BOFFSET        30
+#define IP_PRI_MAPPING2_IP_0XBC_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XBC_FLAG           HSL_RW
+
+#define IP_0XB8                                "imap_ipb8"
+#define IP_PRI_MAPPING2_IP_0XB8_BOFFSET        28
+#define IP_PRI_MAPPING2_IP_0XB8_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XB8_FLAG           HSL_RW
+
+#define IP_0XB4                                "imap_ipb4"
+#define IP_PRI_MAPPING2_IP_0XB4_BOFFSET        26
+#define IP_PRI_MAPPING2_IP_0XB4_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XB4_FLAG           HSL_RW
+
+#define IP_0XB0                                "imap_ipb0"
+#define IP_PRI_MAPPING2_IP_0XB0_BOFFSET        24
+#define IP_PRI_MAPPING2_IP_0XB0_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XB0_FLAG           HSL_RW
+
+#define IP_0XAC                                "imap_ipac"
+#define IP_PRI_MAPPING2_IP_0XAC_BOFFSET        22
+#define IP_PRI_MAPPING2_IP_0XAC_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XAC_FLAG           HSL_RW
+
+#define IP_0XA8                                "imap_ipa8"
+#define IP_PRI_MAPPING2_IP_0XA8_BOFFSET        20
+#define IP_PRI_MAPPING2_IP_0XA8_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XA8_FLAG           HSL_RW
+
+#define IP_0XA4                                "imap_ipa4"
+#define IP_PRI_MAPPING2_IP_0XA4_BOFFSET        18
+#define IP_PRI_MAPPING2_IP_0XA4_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XA4_FLAG           HSL_RW
+
+#define IP_0XA0                                "imap_ipa0"
+#define IP_PRI_MAPPING2_IP_0XA0_BOFFSET        16
+#define IP_PRI_MAPPING2_IP_0XA0_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XA0_FLAG           HSL_RW
+
+#define IP_0X9C                                "imap_ip9c"
+#define IP_PRI_MAPPING2_IP_0X9C_BOFFSET        14
+#define IP_PRI_MAPPING2_IP_0X9C_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X9C_FLAG           HSL_RW
+
+#define IP_0X98                                "imap_ip98"
+#define IP_PRI_MAPPING2_IP_0X98_BOFFSET        12
+#define IP_PRI_MAPPING2_IP_0X98_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X98_FLAG           HSL_RW
+
+#define IP_0X94                                "imap_ip94"
+#define IP_PRI_MAPPING2_IP_0X94_BOFFSET        10
+#define IP_PRI_MAPPING2_IP_0X94_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X94_FLAG           HSL_RW
+
+#define IP_0X90                                "imap_ip90"
+#define IP_PRI_MAPPING2_IP_0X90_BOFFSET        8
+#define IP_PRI_MAPPING2_IP_0X90_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X90_FLAG           HSL_RW
+
+#define IP_0X8C                                "imap_ip8c"
+#define IP_PRI_MAPPING2_IP_0X8C_BOFFSET        6
+#define IP_PRI_MAPPING2_IP_0X8C_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X8C_FLAG           HSL_RW
+
+#define IP_0X88                                "imap_ip88"
+#define IP_PRI_MAPPING2_IP_0X88_BOFFSET        4
+#define IP_PRI_MAPPING2_IP_0X88_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X88_FLAG           HSL_RW
+
+#define IP_0X84                                "imap_ip84"
+#define IP_PRI_MAPPING2_IP_0X84_BOFFSET        2
+#define IP_PRI_MAPPING2_IP_0X84_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X84_FLAG           HSL_RW
+
+#define IP_0X80                                "imap_ip80"
+#define IP_PRI_MAPPING2_IP_0X80_BOFFSET        0
+#define IP_PRI_MAPPING2_IP_0X80_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X80_FLAG           HSL_RW
+
+#define IP_PRI_MAPPING3            "imap3"
+#define IP_PRI_MAPPING3_ID         18
+#define IP_PRI_MAPPING3_OFFSET     0x006C
+#define IP_PRI_MAPPING3_E_LENGTH   4
+#define IP_PRI_MAPPING3_E_OFFSET   0
+#define IP_PRI_MAPPING3_NR_E       0
+
+#define IP_0XFC                                "imap_ipfc"
+#define IP_PRI_MAPPING3_IP_0XFC_BOFFSET        30
+#define IP_PRI_MAPPING3_IP_0XFC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XFC_FLAG           HSL_RW
+
+#define IP_0XF8                                "imap_ipf8"
+#define IP_PRI_MAPPING3_IP_0XF8_BOFFSET        28
+#define IP_PRI_MAPPING3_IP_0XF8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XF8_FLAG           HSL_RW
+
+#define IP_0XF4                                "imap_ipf4"
+#define IP_PRI_MAPPING3_IP_0XF4_BOFFSET        26
+#define IP_PRI_MAPPING3_IP_0XF4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XF4_FLAG           HSL_RW
+
+#define IP_0XF0                                "imap_ipf0"
+#define IP_PRI_MAPPING3_IP_0XF0_BOFFSET        24
+#define IP_PRI_MAPPING3_IP_0XF0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XF0_FLAG           HSL_RW
+
+#define IP_0XEC                                "imap_ipec"
+#define IP_PRI_MAPPING3_IP_0XEC_BOFFSET        22
+#define IP_PRI_MAPPING3_IP_0XEC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XEC_FLAG           HSL_RW
+
+#define IP_0XE8                                "imap_ipe8"
+#define IP_PRI_MAPPING3_IP_0XE8_BOFFSET        20
+#define IP_PRI_MAPPING3_IP_0XE8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XE8_FLAG           HSL_RW
+
+#define IP_0XE4                                "imap_ipe4"
+#define IP_PRI_MAPPING3_IP_0XE4_BOFFSET        18
+#define IP_PRI_MAPPING3_IP_0XE4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XE4_FLAG           HSL_RW
+
+#define IP_0XE0                                "imap_ipe0"
+#define IP_PRI_MAPPING3_IP_0XE0_BOFFSET        16
+#define IP_PRI_MAPPING3_IP_0XE0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XE0_FLAG           HSL_RW
+
+#define IP_0XDC                                "imap_ipdc"
+#define IP_PRI_MAPPING3_IP_0XDC_BOFFSET        14
+#define IP_PRI_MAPPING3_IP_0XDC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XDC_FLAG           HSL_RW
+
+#define IP_0XD8                                "imap_ipd8"
+#define IP_PRI_MAPPING3_IP_0XD8_BOFFSET        12
+#define IP_PRI_MAPPING3_IP_0XD8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XD8_FLAG           HSL_RW
+
+#define IP_0XD4                                "imap_ipd4"
+#define IP_PRI_MAPPING3_IP_0XD4_BOFFSET        10
+#define IP_PRI_MAPPING3_IP_0XD4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XD4_FLAG           HSL_RW
+
+#define IP_0XD0                                "imap_ipd0"
+#define IP_PRI_MAPPING3_IP_0XD0_BOFFSET        8
+#define IP_PRI_MAPPING3_IP_0XD0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XD0_FLAG           HSL_RW
+
+#define IP_0XCC                                "imap_ipcc"
+#define IP_PRI_MAPPING3_IP_0XCC_BOFFSET        6
+#define IP_PRI_MAPPING3_IP_0XCC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XCC_FLAG           HSL_RW
+
+#define IP_0XC8                                "imap_ipc8"
+#define IP_PRI_MAPPING3_IP_0XC8_BOFFSET        4
+#define IP_PRI_MAPPING3_IP_0XC8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XC8_FLAG           HSL_RW
+
+#define IP_0XC4                                "imap_ipc4"
+#define IP_PRI_MAPPING3_IP_0XC4_BOFFSET        2
+#define IP_PRI_MAPPING3_IP_0XC4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XC4_FLAG           HSL_RW
+
+#define IP_0XC0                                "imap_ipc0"
+#define IP_PRI_MAPPING3_IP_0XC0_BOFFSET        0
+#define IP_PRI_MAPPING3_IP_0XC0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XC0_FLAG           HSL_RW
+
+
+    /* Tag Priority Mapping Register */
+#define TAG_PRI_MAPPING           "tpmap"
+#define TAG_PRI_MAPPING_ID        19
+#define TAG_PRI_MAPPING_OFFSET    0x0070
+#define TAG_PRI_MAPPING_E_LENGTH  4
+#define TAG_PRI_MAPPING_E_OFFSET  0
+#define TAG_PRI_MAPPING_NR_E      1
+
+#define TAG_0X07                                "tpmap_tg07"
+#define TAG_PRI_MAPPING_TAG_0X07_BOFFSET      14
+#define TAG_PRI_MAPPING_TAG_0X07_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X07_FLAG         HSL_RW
+
+#define TAG_0X06                              "tpmap_tg06"
+#define TAG_PRI_MAPPING_TAG_0X06_BOFFSET      12
+#define TAG_PRI_MAPPING_TAG_0X06_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X06_FLAG         HSL_RW
+
+#define TAG_0X05                              "tpmap_tg05"
+#define TAG_PRI_MAPPING_TAG_0X05_BOFFSET      10
+#define TAG_PRI_MAPPING_TAG_0X05_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X05_FLAG         HSL_RW
+
+#define TAG_0X04                              "tpmap_tg04"
+#define TAG_PRI_MAPPING_TAG_0X04_BOFFSET      8
+#define TAG_PRI_MAPPING_TAG_0X04_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X04_FLAG         HSL_RW
+
+#define TAG_0X03                              "tpmap_tg03"
+#define TAG_PRI_MAPPING_TAG_0X03_BOFFSET      6
+#define TAG_PRI_MAPPING_TAG_0X03_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X03_FLAG         HSL_RW
+
+#define TAG_0X02                              "tpmap_tg02"
+#define TAG_PRI_MAPPING_TAG_0X02_BOFFSET      4
+#define TAG_PRI_MAPPING_TAG_0X02_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X02_FLAG         HSL_RW
+
+#define TAG_0X01                              "tpmap_tg01"
+#define TAG_PRI_MAPPING_TAG_0X01_BOFFSET      2
+#define TAG_PRI_MAPPING_TAG_0X01_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X01_FLAG         HSL_RW
+
+#define TAG_0X00                              "tpmap_tg00"
+#define TAG_PRI_MAPPING_TAG_0X00_BOFFSET      0
+#define TAG_PRI_MAPPING_TAG_0X00_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X00_FLAG         HSL_RW
+
+
+    /* Service tag Register */
+#define SERVICE_TAG                  "servicetag"
+#define SERVICE_TAG_ID               20
+#define SERVICE_TAG_OFFSET           0x0074
+#define SERVICE_TAG_E_LENGTH         4
+#define SERVICE_TAG_E_OFFSET         0
+#define SERVICE_TAG_NR_E             1
+
+#define TAG_VALUE                        "servicetag_val"
+#define SERVICE_TAG_TAG_VALUE_BOFFSET    0
+#define SERVICE_TAG_TAG_VALUE_BLEN       16
+#define SERVICE_TAG_TAG_VALUE_FLAG       HSL_RW
+
+
+    /* Cpu Port Register */
+#define CPU_PORT                  "cpup"
+#define CPU_PORT_ID               20
+#define CPU_PORT_OFFSET           0x0078
+#define CPU_PORT_E_LENGTH         4
+#define CPU_PORT_E_OFFSET         0
+#define CPU_PORT_NR_E             0
+
+#define CPU_PORT_EN                           "cpup_cpupe"
+#define CPU_PORT_CPU_PORT_EN_BOFFSET          8
+#define CPU_PORT_CPU_PORT_EN_BLEN             1
+#define CPU_PORT_CPU_PORT_EN_FLAG             HSL_RW
+
+#define MIRROR_PORT_NUM                       "cpup_mirpn"
+#define CPU_PORT_MIRROR_PORT_NUM_BOFFSET      4
+#define CPU_PORT_MIRROR_PORT_NUM_BLEN         4
+#define CPU_PORT_MIRROR_PORT_NUM_FLAG         HSL_RW
+
+
+    /* MIB Function Register */
+#define MIB_FUNC                  "mibfunc"
+#define MIB_FUNC_ID               21
+#define MIB_FUNC_OFFSET           0x0080
+#define MIB_FUNC_E_LENGTH         4
+#define MIB_FUNC_E_OFFSET         0
+#define MIB_FUNC_NR_E             1
+
+#define MAC_CRC_EN                            "mibfunc_crcen"
+#define MIB_FUNC_MAC_CRC_EN_BOFFSET            31
+#define MIB_FUNC_MAC_CRC_EN_BLEN               1
+#define MIB_FUNC_MAC_CRC_EN_FLAG               HSL_RW
+
+#define MIB_EN                               "mib_en"
+#define MIB_FUNC_MIB_EN_BOFFSET              30
+#define MIB_FUNC_MIB_EN_BLEN                 1
+#define MIB_FUNC_MIB_EN_FLAG                 HSL_RW
+
+#define MIB_FUN                              "mibfunc_mibf"
+#define MIB_FUNC_MIB_FUN_BOFFSET              24
+#define MIB_FUNC_MIB_FUN_BLEN                 3
+#define MIB_FUNC_MIB_FUN_FLAG                 HSL_RW
+
+#define MIB_BUSY                              "mibfunc_mibb"
+#define MIB_FUNC_MIB_BUSY_BOFFSET              17
+#define MIB_FUNC_MIB_BUSY_BLEN                 1
+#define MIB_FUNC_MIB_BUSY_FLAG                 HSL_RW
+
+#define MIB_AT_HALF_EN                        "mibfunc_mibhe"
+#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET        16
+#define MIB_FUNC_MIB_AT_HALF_EN_BLEN           1
+#define MIB_FUNC_MIB_AT_HALF_EN_FLAG           HSL_RW
+
+#define MIB_TIMER                             "mibfunc_mibt"
+#define MIB_FUNC_MIB_TIMER_BOFFSET             0
+#define MIB_FUNC_MIB_TIMER_BLEN                16
+#define MIB_FUNC_MIB_TIMER_FLAG                HSL_RW
+
+
+    /* Mdio control Register */
+#define MDIO_CTRL               "mctrl"
+#define MDIO_CTRL_ID            24
+#define MDIO_CTRL_OFFSET        0x0098
+#define MDIO_CTRL_E_LENGTH      4
+#define MDIO_CTRL_E_OFFSET      0
+#define MDIO_CTRL_NR_E          1
+
+#define MSTER_EN                        "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET      30
+#define MDIO_CTRL_MSTER_EN_BLEN         1
+#define MDIO_CTRL_MSTER_EN_FLAG         HSL_RW
+
+#define MSTER_EN                        "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET      30
+#define MDIO_CTRL_MSTER_EN_BLEN         1
+#define MDIO_CTRL_MSTER_EN_FLAG         HSL_RW
+
+#define CMD                             "mctrl_cmd"
+#define MDIO_CTRL_CMD_BOFFSET           27
+#define MDIO_CTRL_CMD_BLEN              1
+#define MDIO_CTRL_CMD_FLAG              HSL_RW
+
+#define SUP_PRE                         "mctrl_spre"
+#define MDIO_CTRL_SUP_PRE_BOFFSET       26
+#define MDIO_CTRL_SUP_PRE_BLEN          1
+#define MDIO_CTRL_SUP_PRE_FLAG          HSL_RW
+
+#define PHY_ADDR                        "mctrl_phyaddr"
+#define MDIO_CTRL_PHY_ADDR_BOFFSET      21
+#define MDIO_CTRL_PHY_ADDR_BLEN         5
+#define MDIO_CTRL_PHY_ADDR_FLAG         HSL_RW
+
+#define REG_ADDR                        "mctrl_regaddr"
+#define MDIO_CTRL_REG_ADDR_BOFFSET      16
+#define MDIO_CTRL_REG_ADDR_BLEN         5
+#define MDIO_CTRL_REG_ADDR_FLAG         HSL_RW
+
+#define DATA                            "mctrl_data"
+#define MDIO_CTRL_DATA_BOFFSET          0
+#define MDIO_CTRL_DATA_BLEN             16
+#define MDIO_CTRL_DATA_FLAG             HSL_RW
+
+
+
+
+    /* BIST control Register */
+#define BIST_CTRL               "bctrl"
+#define BIST_CTRL_ID            24
+#define BIST_CTRL_OFFSET        0x00a0
+#define BIST_CTRL_E_LENGTH      4
+#define BIST_CTRL_E_OFFSET      0
+#define BIST_CTRL_NR_E          1
+
+#define BIST_BUSY                        "bctrl_bb"
+#define BIST_CTRL_BIST_BUSY_BOFFSET      31
+#define BIST_CTRL_BIST_BUSY_BLEN         1
+#define BIST_CTRL_BIST_BUSY_FLAG         HSL_RW
+
+#define ONE_ERR                          "bctrl_oe"
+#define BIST_CTRL_ONE_ERR_BOFFSET        30
+#define BIST_CTRL_ONE_ERR_BLEN           1
+#define BIST_CTRL_ONE_ERR_FLAG           HSL_RO
+
+#define ERR_MEM                          "bctrl_em"
+#define BIST_CTRL_ERR_MEM_BOFFSET        24
+#define BIST_CTRL_ERR_MEM_BLEN           4
+#define BIST_CTRL_ERR_MEM_FLAG           HSL_RO
+
+#define PTN_EN2                          "bctrl_pe2"
+#define BIST_CTRL_PTN_EN2_BOFFSET        22
+#define BIST_CTRL_PTN_EN2_BLEN           1
+#define BIST_CTRL_PTN_EN2_FLAG           HSL_RW
+
+#define PTN_EN1                          "bctrl_pe1"
+#define BIST_CTRL_PTN_EN1_BOFFSET        21
+#define BIST_CTRL_PTN_EN1_BLEN           1
+#define BIST_CTRL_PTN_EN1_FLAG           HSL_RW
+
+#define PTN_EN0                          "bctrl_pe0"
+#define BIST_CTRL_PTN_EN0_BOFFSET        20
+#define BIST_CTRL_PTN_EN0_BLEN           1
+#define BIST_CTRL_PTN_EN0_FLAG           HSL_RW
+
+#define ERR_PTN                          "bctrl_ep"
+#define BIST_CTRL_ERR_PTN_BOFFSET        16
+#define BIST_CTRL_ERR_PTN_BLEN           2
+#define BIST_CTRL_ERR_PTN_FLAG           HSL_RO
+
+#define ERR_CNT                          "bctrl_ec"
+#define BIST_CTRL_ERR_CNT_BOFFSET        13
+#define BIST_CTRL_ERR_CNT_BLEN           3
+#define BIST_CTRL_ERR_CNT_FLAG           HSL_RO
+
+#define ERR_ADDR                         "bctrl_ea"
+#define BIST_CTRL_ERR_ADDR_BOFFSET       0
+#define BIST_CTRL_ERR_ADDR_BLEN          13
+#define BIST_CTRL_ERR_ADDR_FLAG          HSL_RO
+
+
+
+
+    /* BIST recover Register */
+#define BIST_RCV               "brcv"
+#define BIST_RCV_ID            24
+#define BIST_RCV_OFFSET        0x00a4
+#define BIST_RCV_E_LENGTH      4
+#define BIST_RCV_E_OFFSET      0
+#define BIST_RCV_NR_E          1
+
+#define RCV_EN                           "brcv_en"
+#define BIST_RCV_RCV_EN_BOFFSET          31
+#define BIST_RCV_RCV_EN_BLEN             1
+#define BIST_RCV_RCV_EN_FLAG             HSL_RW
+
+#define RCV_ADDR                         "brcv_addr"
+#define BIST_RCV_RCV_ADDR_BOFFSET        0
+#define BIST_RCV_RCV_ADDR_BLEN           13
+#define BIST_RCV_RCV_ADDR_FLAG           HSL_RW
+
+
+
+
+    /* LED control Register */
+#define LED_CTRL               "ledctrl"
+#define LED_CTRL_ID            25
+#define LED_CTRL_OFFSET        0x00b0
+#define LED_CTRL_E_LENGTH      4
+#define LED_CTRL_E_OFFSET      0
+#define LED_CTRL_NR_E          1
+
+#define PATTERN_EN                           "lctrl_pen"
+#define LED_CTRL_PATTERN_EN_BOFFSET          14
+#define LED_CTRL_PATTERN_EN_BLEN             2
+#define LED_CTRL_PATTERN_EN_FLAG             HSL_RW
+
+#define FULL_LIGHT_EN                        "lctrl_fen"
+#define LED_CTRL_FULL_LIGHT_EN_BOFFSET       13
+#define LED_CTRL_FULL_LIGHT_EN_BLEN          1
+#define LED_CTRL_FULL_LIGHT_EN_FLAG          HSL_RW
+
+#define HALF_LIGHT_EN                        "lctrl_hen"
+#define LED_CTRL_HALF_LIGHT_EN_BOFFSET       12
+#define LED_CTRL_HALF_LIGHT_EN_BLEN          1
+#define LED_CTRL_HALF_LIGHT_EN_FLAG          HSL_RW
+
+#define POWERON_LIGHT_EN                     "lctrl_poen"
+#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET    11
+#define LED_CTRL_POWERON_LIGHT_EN_BLEN       1
+#define LED_CTRL_POWERON_LIGHT_EN_FLAG       HSL_RW
+
+#define GE_LIGHT_EN                          "lctrl_geen"
+#define LED_CTRL_GE_LIGHT_EN_BOFFSET         10
+#define LED_CTRL_GE_LIGHT_EN_BLEN            1
+#define LED_CTRL_GE_LIGHT_EN_FLAG            HSL_RW
+
+#define FE_LIGHT_EN                          "lctrl_feen"
+#define LED_CTRL_FE_LIGHT_EN_BOFFSET         9
+#define LED_CTRL_FE_LIGHT_EN_BLEN            1
+#define LED_CTRL_FE_LIGHT_EN_FLAG            HSL_RW
+
+#define ETH_LIGHT_EN                         "lctrl_ethen"
+#define LED_CTRL_ETH_LIGHT_EN_BOFFSET        8
+#define LED_CTRL_ETH_LIGHT_EN_BLEN           1
+#define LED_CTRL_ETH_LIGHT_EN_FLAG           HSL_RW
+
+#define COL_BLINK_EN                         "lctrl_cen"
+#define LED_CTRL_COL_BLINK_EN_BOFFSET        7
+#define LED_CTRL_COL_BLINK_EN_BLEN           1
+#define LED_CTRL_COL_BLINK_EN_FLAG           HSL_RW
+
+#define RX_BLINK_EN                          "lctrl_rxen"
+#define LED_CTRL_RX_BLINK_EN_BOFFSET         5
+#define LED_CTRL_RX_BLINK_EN_BLEN            1
+#define LED_CTRL_RX_BLINK_EN_FLAG            HSL_RW
+
+#define TX_BLINK_EN                          "lctrl_txen"
+#define LED_CTRL_TX_BLINK_EN_BOFFSET         4
+#define LED_CTRL_TX_BLINK_EN_BLEN            1
+#define LED_CTRL_TX_BLINK_EN_FLAG            HSL_RW
+
+#define LINKUP_OVER_EN                       "lctrl_loen"
+#define LED_CTRL_LINKUP_OVER_EN_BOFFSET      2
+#define LED_CTRL_LINKUP_OVER_EN_BLEN         1
+#define LED_CTRL_LINKUP_OVER_EN_FLAG         HSL_RW
+
+#define BLINK_FREQ                           "lctrl_bfreq"
+#define LED_CTRL_BLINK_FREQ_BOFFSET          0
+#define LED_CTRL_BLINK_FREQ_BLEN             2
+#define LED_CTRL_BLINK_FREQ_FLAG             HSL_RW
+
+
+    /* Port Status Register */
+#define PORT_STATUS               "ptsts"
+#define PORT_STATUS_ID            29
+#define PORT_STATUS_OFFSET        0x0100
+#define PORT_STATUS_E_LENGTH      4
+#define PORT_STATUS_E_OFFSET      0x0100
+#define PORT_STATUS_NR_E          6
+
+#define FLOW_LINK_EN                            "ptsts_flen"
+#define PORT_STATUS_FLOW_LINK_EN_BOFFSET        12
+#define PORT_STATUS_FLOW_LINK_EN_BLEN           1
+#define PORT_STATUS_FLOW_LINK_EN_FLAG           HSL_RW
+
+
+#define LINK_ASYN_PAUSE                         "ptsts_lasynp"
+#define PORT_STATUS_LINK_ASYN_PAUSE_BOFFSET     11
+#define PORT_STATUS_LINK_ASYN_PAUSE_BLEN        1
+#define PORT_STATUS_LINK_ASYN_PAUSE_FLAG        HSL_RO
+
+#define LINK_PAUSE                              "ptsts_lpause"
+#define PORT_STATUS_LINK_PAUSE_BOFFSET          10
+#define PORT_STATUS_LINK_PAUSE_BLEN             1
+#define PORT_STATUS_LINK_PAUSE_FLAG             HSL_RO
+
+#define LINK_EN                                 "ptsts_linken"
+#define PORT_STATUS_LINK_EN_BOFFSET             9
+#define PORT_STATUS_LINK_EN_BLEN                1
+#define PORT_STATUS_LINK_EN_FLAG                HSL_RW
+
+#define LINK                                    "ptsts_ptlink"
+#define PORT_STATUS_LINK_BOFFSET                8
+#define PORT_STATUS_LINK_BLEN                   1
+#define PORT_STATUS_LINK_FLAG                   HSL_RO
+
+#define TX_HALF_FLOW_EN
+#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET     7
+#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN        1
+#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG        HSL_RW
+
+#define DUPLEX_MODE                             "ptsts_dupmod"
+#define PORT_STATUS_DUPLEX_MODE_BOFFSET         6
+#define PORT_STATUS_DUPLEX_MODE_BLEN            1
+#define PORT_STATUS_DUPLEX_MODE_FLAG            HSL_RW
+
+#define RX_FLOW_EN                              "ptsts_rxfwen"
+#define PORT_STATUS_RX_FLOW_EN_BOFFSET          5
+#define PORT_STATUS_RX_FLOW_EN_BLEN             1
+#define PORT_STATUS_RX_FLOW_EN_FLAG             HSL_RW
+
+#define TX_FLOW_EN                              "ptsts_txfwen"
+#define PORT_STATUS_TX_FLOW_EN_BOFFSET          4
+#define PORT_STATUS_TX_FLOW_EN_BLEN             1
+#define PORT_STATUS_TX_FLOW_EN_FLAG             HSL_RW
+
+#define RXMAC_EN                                "ptsts_rxmacen"
+#define PORT_STATUS_RXMAC_EN_BOFFSET            3
+#define PORT_STATUS_RXMAC_EN_BLEN               1
+#define PORT_STATUS_RXMAC_EN_FLAG               HSL_RW
+
+#define TXMAC_EN                                "ptsts_txmacen"
+#define PORT_STATUS_TXMAC_EN_BOFFSET            2
+#define PORT_STATUS_TXMAC_EN_BLEN               1
+#define PORT_STATUS_TXMAC_EN_FLAG               HSL_RW
+
+#define SPEED_MODE                              "ptsts_speed"
+#define PORT_STATUS_SPEED_MODE_BOFFSET          0
+#define PORT_STATUS_SPEED_MODE_BLEN             2
+#define PORT_STATUS_SPEED_MODE_FLAG             HSL_RW
+
+
+    /* Port Control Register */
+#define PORT_CTL                  "pctl"
+#define PORT_CTL_ID               30
+#define PORT_CTL_OFFSET           0x0104
+#define PORT_CTL_E_LENGTH         4
+#define PORT_CTL_E_OFFSET         0x0100
+#define PORT_CTL_NR_E             6
+
+#define LEAVE_EN                                "pctl_leaveen"
+#define PORT_CTL_LEAVE_EN_BOFFSET               21
+#define PORT_CTL_LEAVE_EN_BLEN                  1
+#define PORT_CTL_LEAVE_EN_FLAG                  HSL_RW
+
+#define JOIN_EN                                 "pctl_joinen"
+#define PORT_CTL_JOIN_EN_BOFFSET                20
+#define PORT_CTL_JOIN_EN_BLEN                   1
+#define PORT_CTL_JOIN_EN_FLAG                   HSL_RW
+
+#define DHCP_EN                                 "pctl_dhcpen"
+#define PORT_CTL_DHCP_EN_BOFFSET                19
+#define PORT_CTL_DHCP_EN_BLEN                   1
+#define PORT_CTL_DHCP_EN_FLAG                   HSL_RW
+
+#define ING_MIRROR_EN                           "pctl_ingmiren"
+#define PORT_CTL_ING_MIRROR_EN_BOFFSET          17
+#define PORT_CTL_ING_MIRROR_EN_BLEN             1
+#define PORT_CTL_ING_MIRROR_EN_FLAG             HSL_RW
+
+#define EG_MIRROR_EN                            "pctl_egmiren"
+#define PORT_CTL_EG_MIRROR_EN_BOFFSET           16
+#define PORT_CTL_EG_MIRROR_EN_BLEN              1
+#define PORT_CTL_EG_MIRROR_EN_FLAG              HSL_RW
+
+#define DTAG_EN                                 "pctl_dtagen"
+#define PORT_CTL_DTAG_EN_BOFFSET                15
+#define PORT_CTL_DTAG_EN_BLEN                   1
+#define PORT_CTL_DTAG_EN_FLAG                   HSL_RW
+
+#define LEARN_EN                                "pctl_learnen"
+#define PORT_CTL_LEARN_EN_BOFFSET               14
+#define PORT_CTL_LEARN_EN_BLEN                  1
+#define PORT_CTL_LEARN_EN_FLAG                  HSL_RW
+
+#define SINGLE_VLAN_EN                          "pctl_svlanen"
+#define PORT_CTL_SINGLE_VLAN_EN_BOFFSET         13
+#define PORT_CTL_SINGLE_VLAN_EN_BLEN            1
+#define PORT_CTL_SINGLE_VLAN_EN_FLAG            HSL_RW
+
+#define MAC_LOOP_BACK                           "pctl_maclp"
+#define PORT_CTL_MAC_LOOP_BACK_BOFFSET          12
+#define PORT_CTL_MAC_LOOP_BACK_BLEN             1
+#define PORT_CTL_MAC_LOOP_BACK_FLAG             HSL_RW
+
+#define HEAD_EN                                 "pctl_headen"
+#define PORT_CTL_HEAD_EN_BOFFSET                11
+#define PORT_CTL_HEAD_EN_BLEN                   1
+#define PORT_CTL_HEAD_EN_FLAG                   HSL_RW
+
+#define IGMP_MLD_EN                             "pctl_imlden"
+#define PORT_CTL_IGMP_MLD_EN_BOFFSET            10
+#define PORT_CTL_IGMP_MLD_EN_BLEN               1
+#define PORT_CTL_IGMP_MLD_EN_FLAG               HSL_RW
+
+#define EG_VLAN_MODE                            "pctl_egvmode"
+#define PORT_CTL_EG_VLAN_MODE_BOFFSET           8
+#define PORT_CTL_EG_VLAN_MODE_BLEN              2
+#define PORT_CTL_EG_VLAN_MODE_FLAG              HSL_RW
+
+#define LEARN_ONE_LOCK                          "pctl_lonelck"
+#define PORT_CTL_LEARN_ONE_LOCK_BOFFSET         7
+#define PORT_CTL_LEARN_ONE_LOCK_BLEN            1
+#define PORT_CTL_LEARN_ONE_LOCK_FLAG            HSL_RW
+
+#define PORT_LOCK_EN                            "pctl_locken"
+#define PORT_CTL_PORT_LOCK_EN_BOFFSET           6
+#define PORT_CTL_PORT_LOCK_EN_BLEN              1
+#define PORT_CTL_PORT_LOCK_EN_FLAG              HSL_RW
+
+#define LOCK_DROP_EN                            "pctl_dropen"
+#define PORT_CTL_LOCK_DROP_EN_BOFFSET           5
+#define PORT_CTL_LOCK_DROP_EN_BLEN              1
+#define PORT_CTL_LOCK_DROP_EN_FLAG              HSL_RW
+
+#define PORT_STATE                              "pctl_pstate"
+#define PORT_CTL_PORT_STATE_BOFFSET             0
+#define PORT_CTL_PORT_STATE_BLEN                3
+#define PORT_CTL_PORT_STATE_FLAG                HSL_RW
+
+
+    /* Port Based Vlan Register */
+#define PORT_BASE_VLAN            "pbvlan"
+#define PORT_BASE_VLAN_ID         31
+#define PORT_BASE_VLAN_OFFSET     0x0108
+#define PORT_BASE_VLAN_E_LENGTH   4
+#define PORT_BASE_VLAN_E_OFFSET   0x0100
+#define PORT_BASE_VLAN_NR_E     6
+
+#define DOT1Q_MODE                              "pbvlan_8021q"
+#define PORT_BASE_VLAN_DOT1Q_MODE_BOFFSET       30
+#define PORT_BASE_VLAN_DOT1Q_MODE_BLEN          2
+#define PORT_BASE_VLAN_DOT1Q_MODE_FLAG          HSL_RW
+
+#define ING_PRI                                 "pbvlan_ingpri"
+#define PORT_BASE_VLAN_ING_PRI_BOFFSET          27
+#define PORT_BASE_VLAN_ING_PRI_BLEN             3
+#define PORT_BASE_VLAN_ING_PRI_FLAG             HSL_RW
+
+#define FORCE_PVLAN                             "pbvlan_fpvlan"
+#define PORT_BASE_VLAN_FORCE_PVLAN_BOFFSET      26
+#define PORT_BASE_VLAN_FORCE_PVLAN_BLEN         1
+#define PORT_BASE_VLAN_FORCE_PVLAN_FLAG         HSL_RW
+
+#define PORT_VID_MEM                            "pbvlan_pvidm"
+#define PORT_BASE_VLAN_PORT_VID_MEM_BOFFSET     16
+#define PORT_BASE_VLAN_PORT_VID_MEM_BLEN        6
+#define PORT_BASE_VLAN_PORT_VID_MEM_FLAG        HSL_RW
+
+#define ARP_LEAKY_EN                            "pbvlan_alen"
+#define PORT_BASE_VLAN_ARP_LEAKY_EN_BOFFSET     15
+#define PORT_BASE_VLAN_ARP_LEAKY_EN_BLEN        1
+#define PORT_BASE_VLAN_ARP_LEAKY_EN_FLAG        HSL_RW
+
+#define UNI_LEAKY_EN                            "pbvlan_ulen"
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_BOFFSET     14
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_BLEN        1
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_FLAG        HSL_RW
+
+#define MUL_LEAKY_EN                            "pbvlan_mlen"
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_BOFFSET     13
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_BLEN        1
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_FLAG        HSL_RW
+
+#define FORCE_DEF_VID                           "pbvlan_fdvid"
+#define PORT_BASE_VLAN_FORCE_DEF_VID_BOFFSET    12
+#define PORT_BASE_VLAN_FORCE_DEF_VID_BLEN       1
+#define PORT_BASE_VLAN_FORCE_DEF_VID_FLAG       HSL_RW
+
+#define PORT_VID                                "pbvlan_ptvid"
+#define PORT_BASE_VLAN_PORT_VID_BOFFSET         0
+#define PORT_BASE_VLAN_PORT_VID_BLEN            12
+#define PORT_BASE_VLAN_PORT_VID_FLAG            HSL_RW
+
+
+    /* Port Rate Limit0 Register */
+#define RATE_LIMIT0                "rlmt0"
+#define RATE_LIMIT0_ID             32
+#define RATE_LIMIT0_OFFSET         0x010C
+#define RATE_LIMIT0_E_LENGTH       4
+#define RATE_LIMIT0_E_OFFSET       0x0100
+#define RATE_LIMIT0_NR_E           6
+
+#define ADD_RATE_BYTE                          "rlmt_addbyte"
+#define RATE_LIMIT0_ADD_RATE_BYTE_BOFFSET      24
+#define RATE_LIMIT0_ADD_RATE_BYTE_BLEN         8
+#define RATE_LIMIT0_ADD_RATE_BYTE_FLAG         HSL_RW
+
+#define EG_RATE_EN                             "rlmt_egen"
+#define RATE_LIMIT0_EG_RATE_EN_BOFFSET         23
+#define RATE_LIMIT0_EG_RATE_EN_BLEN            1
+#define RATE_LIMIT0_EG_RATE_EN_FLAG            HSL_RW
+
+#define EG_MNG_RATE_EN                         "rlmt_egmngen"
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET     22
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN        1
+#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG        HSL_RW
+
+#define IN_MNG_RATE_EN                         "rlmt_inmngen"
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET     21
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN        1
+#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG        HSL_RW
+
+#define IN_MUL_RATE_EN                         "rlmt_inmulen"
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET     20
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN        1
+#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG        HSL_RW
+
+#define ING_RATE                               "rlmt_ingrate"
+#define RATE_LIMIT0_ING_RATE_BOFFSET           0
+#define RATE_LIMIT0_ING_RATE_BLEN              15
+#define RATE_LIMIT0_ING_RATE_FLAG              HSL_RW
+
+
+    /* Priority Control Register */
+#define PRI_CTL                   "prctl"
+#define PRI_CTL_ID                33
+#define PRI_CTL_OFFSET            0x0110
+#define PRI_CTL_E_LENGTH          4
+#define PRI_CTL_E_OFFSET          0x0100
+#define PRI_CTL_NR_E              6
+
+#define PORT_PRI_EN                             "prctl_ptprien"
+#define PRI_CTL_PORT_PRI_EN_BOFFSET             19
+#define PRI_CTL_PORT_PRI_EN_BLEN                1
+#define PRI_CTL_PORT_PRI_EN_FLAG                HSL_RW
+
+#define DA_PRI_EN                               "prctl_daprien"
+#define PRI_CTL_DA_PRI_EN_BOFFSET               18
+#define PRI_CTL_DA_PRI_EN_BLEN                  1
+#define PRI_CTL_DA_PRI_EN_FLAG                  HSL_RW
+
+#define VLAN_PRI_EN                             "prctl_vprien"
+#define PRI_CTL_VLAN_PRI_EN_BOFFSET             17
+#define PRI_CTL_VLAN_PRI_EN_BLEN                1
+#define PRI_CTL_VLAN_PRI_EN_FLAG                HSL_RW
+
+#define IP_PRI_EN                               "prctl_ipprien"
+#define PRI_CTL_IP_PRI_EN_BOFFSET               16
+#define PRI_CTL_IP_PRI_EN_BLEN                  1
+#define PRI_CTL_IP_PRI_EN_FLAG                  HSL_RW
+
+#define DA_PRI_SEL                              "prctl_dapris"
+#define PRI_CTL_DA_PRI_SEL_BOFFSET              6
+#define PRI_CTL_DA_PRI_SEL_BLEN                 2
+#define PRI_CTL_DA_PRI_SEL_FLAG                 HSL_RW
+
+#define VLAN_PRI_SEL                            "prctl_vpris"
+#define PRI_CTL_VLAN_PRI_SEL_BOFFSET            4
+#define PRI_CTL_VLAN_PRI_SEL_BLEN               2
+#define PRI_CTL_VLAN_PRI_SEL_FLAG               HSL_RW
+
+#define IP_PRI_SEL                              "prctl_ippris"
+#define PRI_CTL_IP_PRI_SEL_BOFFSET              2
+#define PRI_CTL_IP_PRI_SEL_BLEN                 2
+#define PRI_CTL_IP_PRI_SEL_FLAG                 HSL_RW
+
+#define PORT_PRI_SEL                            "prctl_ptpris"
+#define PRI_CTL_PORT_PRI_SEL_BOFFSET            0
+#define PRI_CTL_PORT_PRI_SEL_BLEN               2
+#define PRI_CTL_PORT_PRI_SEL_FLAG               HSL_RW
+
+
+    /* Storm Control Register */
+#define STORM_CTL                 "sctrl"
+#define STORM_CTL_ID                33
+#define STORM_CTL_OFFSET            0x0114
+#define STORM_CTL_E_LENGTH          4
+#define STORM_CTL_E_OFFSET          0x0100
+#define STORM_CTL_NR_E              6
+
+#define UNIT                             "sctrl_unit"
+#define STORM_CTL_UNIT_BOFFSET           24
+#define STORM_CTL_UNIT_BLEN              2
+#define STORM_CTL_UNIT_FLAG              HSL_RW
+
+#define MUL_EN                           "sctrl_mulen"
+#define STORM_CTL_MUL_EN_BOFFSET         10
+#define STORM_CTL_MUL_EN_BLEN            1
+#define STORM_CTL_MUL_EN_FLAG            HSL_RW
+
+#define UNI_EN                           "sctrl_unien"
+#define STORM_CTL_UNI_EN_BOFFSET         9
+#define STORM_CTL_UNI_EN_BLEN            1
+#define STORM_CTL_UNI_EN_FLAG            HSL_RW
+
+#define BRO_EN                           "sctrl_broen"
+#define STORM_CTL_BRO_EN_BOFFSET         8
+#define STORM_CTL_BRO_EN_BLEN            1
+#define STORM_CTL_BRO_EN_FLAG            HSL_RW
+
+#define RATE                             "sctrl_rate"
+#define STORM_CTL_RATE_BOFFSET           0
+#define STORM_CTL_RATE_BLEN              4
+#define STORM_CTL_RATE_FLAG              HSL_RW
+
+
+    /* Queue Control Register */
+#define QUEUE_CTL                   "qctl"
+#define QUEUE_CTL_ID                34
+#define QUEUE_CTL_OFFSET            0x0118
+#define QUEUE_CTL_E_LENGTH          4
+#define QUEUE_CTL_E_OFFSET          0x0100
+#define QUEUE_CTL_NR_E              6
+
+#define PORT_DESC_EN                             "qctl_pdescen"
+#define QUEUE_CTL_PORT_DESC_EN_BOFFSET           25
+#define QUEUE_CTL_PORT_DESC_EN_BLEN              1
+#define QUEUE_CTL_PORT_DESC_EN_FLAG              HSL_RW
+
+#define QUEUE_DESC_EN                            "qctl_qdescen"
+#define QUEUE_CTL_QUEUE_DESC_EN_BOFFSET          24
+#define QUEUE_CTL_QUEUE_DESC_EN_BLEN             1
+#define QUEUE_CTL_QUEUE_DESC_EN_FLAG             HSL_RW
+
+#define PORT_DESC_NR                             "qctl_pdscpnr"
+#define QUEUE_CTL_PORT_DESC_NR_BOFFSET           16
+#define QUEUE_CTL_PORT_DESC_NR_BLEN              6
+#define QUEUE_CTL_PORT_DESC_NR_FLAG              HSL_RW
+
+#define QUEUE3_DESC_NR                           "qctl_q3dscpnr"
+#define QUEUE_CTL_QUEUE3_DESC_NR_BOFFSET         12
+#define QUEUE_CTL_QUEUE3_DESC_NR_BLEN            4
+#define QUEUE_CTL_QUEUE3_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE2_DESC_NR                           "qctl_q2dscpnr"
+#define QUEUE_CTL_QUEUE2_DESC_NR_BOFFSET         8
+#define QUEUE_CTL_QUEUE2_DESC_NR_BLEN            4
+#define QUEUE_CTL_QUEUE2_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE1_DESC_NR                           "qctl_q1dscpnr"
+#define QUEUE_CTL_QUEUE1_DESC_NR_BOFFSET         4
+#define QUEUE_CTL_QUEUE1_DESC_NR_BLEN            4
+#define QUEUE_CTL_QUEUE1_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE0_DESC_NR                           "qctl_q0dscpnr"
+#define QUEUE_CTL_QUEUE0_DESC_NR_BOFFSET         0
+#define QUEUE_CTL_QUEUE0_DESC_NR_BLEN            4
+#define QUEUE_CTL_QUEUE0_DESC_NR_FLAG            HSL_RW
+
+
+    /* Port Rate Limit1 Register */
+#define RATE_LIMIT1                "rlmt1"
+#define RATE_LIMIT1_ID             32
+#define RATE_LIMIT1_OFFSET         0x011C
+#define RATE_LIMIT1_E_LENGTH       4
+#define RATE_LIMIT1_E_OFFSET       0x0100
+#define RATE_LIMIT1_NR_E           6
+
+#define EG_Q1_RATE                              "rlmt_egq1rate"
+#define RATE_LIMIT1_EG_Q1_RATE_BOFFSET          16
+#define RATE_LIMIT1_EG_Q1_RATE_BLEN             15
+#define RATE_LIMIT1_EG_Q1_RATE_FLAG             HSL_RW
+
+#define EG_Q0_RATE                              "rlmt_egq0rate"
+#define RATE_LIMIT1_EG_Q0_RATE_BOFFSET          0
+#define RATE_LIMIT1_EG_Q0_RATE_BLEN             15
+#define RATE_LIMIT1_EG_Q0_RATE_FLAG             HSL_RW
+
+
+    /* Port Rate Limit2 Register */
+#define RATE_LIMIT2                "rlmt2"
+#define RATE_LIMIT2_ID             32
+#define RATE_LIMIT2_OFFSET         0x0120
+#define RATE_LIMIT2_E_LENGTH       4
+#define RATE_LIMIT2_E_OFFSET       0x0100
+#define RATE_LIMIT2_NR_E           6
+
+#define EG_Q3_RATE                              "rlmt_egq3rate"
+#define RATE_LIMIT2_EG_Q3_RATE_BOFFSET          16
+#define RATE_LIMIT2_EG_Q3_RATE_BLEN             15
+#define RATE_LIMIT2_EG_Q3_RATE_FLAG             HSL_RW
+
+#define EG_Q2_RATE                              "rlmt_egq2rate"
+#define RATE_LIMIT2_EG_Q2_RATE_BOFFSET          0
+#define RATE_LIMIT2_EG_Q2_RATE_BLEN             15
+#define RATE_LIMIT2_EG_Q2_RATE_FLAG             HSL_RW
+
+
+    /* mib memory info */
+#define MIB_RXBROAD                       "RxBroad"
+#define MIB_RXBROAD_ID                    34
+#define MIB_RXBROAD_OFFSET                0x20000
+#define MIB_RXBROAD_E_LENGTH              4
+#define MIB_RXBROAD_E_OFFSET              0x100
+#define MIB_RXBROAD_NR_E                  6
+
+#define MIB_RXPAUSE                       "RxPause"
+#define MIB_RXPAUSE_ID                    35
+#define MIB_RXPAUSE_OFFSET                0x20004
+#define MIB_RXPAUSE_E_LENGTH              4
+#define MIB_RXPAUSE_E_OFFSET              0x100
+#define MIB_RXPAUSE_NR_E                  6
+
+#define MIB_RXMULTI                       "RxMulti"
+#define MIB_RXMULTI_ID                    36
+#define MIB_RXMULTI_OFFSET                0x20008
+#define MIB_RXMULTI_E_LENGTH              4
+#define MIB_RXMULTI_E_OFFSET              0x100
+#define MIB_RXMULTI_NR_E                  6
+
+#define MIB_RXFCSERR                      "RxFcsErr"
+#define MIB_RXFCSERR_ID                   37
+#define MIB_RXFCSERR_OFFSET               0x2000c
+#define MIB_RXFCSERR_E_LENGTH             4
+#define MIB_RXFCSERR_E_OFFSET             0x100
+#define MIB_RXFCSERR_NR_E                 6
+
+#define MIB_RXALLIGNERR                   "RxAllignErr"
+#define MIB_RXALLIGNERR_ID                38
+#define MIB_RXALLIGNERR_OFFSET            0x20010
+#define MIB_RXALLIGNERR_E_LENGTH          4
+#define MIB_RXALLIGNERR_E_OFFSET          0x100
+#define MIB_RXALLIGNERR_NR_E              6
+
+#define MIB_RXRUNT                        "RxRunt"
+#define MIB_RXRUNT_ID                     39
+#define MIB_RXRUNT_OFFSET                 0x20014
+#define MIB_RXRUNT_E_LENGTH               4
+#define MIB_RXRUNT_E_OFFSET               0x100
+#define MIB_RXRUNT_NR_E                   6
+
+#define MIB_RXFRAGMENT                    "RxFragment"
+#define MIB_RXFRAGMENT_ID                 40
+#define MIB_RXFRAGMENT_OFFSET             0x20018
+#define MIB_RXFRAGMENT_E_LENGTH           4
+#define MIB_RXFRAGMENT_E_OFFSET           0x100
+#define MIB_RXFRAGMENT_NR_E               6
+
+#define MIB_RX64BYTE                      "Rx64Byte"
+#define MIB_RX64BYTE_ID                   41
+#define MIB_RX64BYTE_OFFSET               0x2001c
+#define MIB_RX64BYTE_E_LENGTH             4
+#define MIB_RX64BYTE_E_OFFSET             0x100
+#define MIB_RX64BYTE_NR_E                 6
+
+#define MIB_RX128BYTE                     "Rx128Byte"
+#define MIB_RX128BYTE_ID                  42
+#define MIB_RX128BYTE_OFFSET              0x20020
+#define MIB_RX128BYTE_E_LENGTH            4
+#define MIB_RX128BYTE_E_OFFSET            0x100
+#define MIB_RX128BYTE_NR_E                6
+
+#define MIB_RX256BYTE                     "Rx256Byte"
+#define MIB_RX256BYTE_ID                  43
+#define MIB_RX256BYTE_OFFSET              0x20024
+#define MIB_RX256BYTE_E_LENGTH            4
+#define MIB_RX256BYTE_E_OFFSET            0x100
+#define MIB_RX256BYTE_NR_E                6
+
+#define MIB_RX512BYTE                     "Rx512Byte"
+#define MIB_RX512BYTE_ID                  44
+#define MIB_RX512BYTE_OFFSET              0x20028
+#define MIB_RX512BYTE_E_LENGTH            4
+#define MIB_RX512BYTE_E_OFFSET            0x100
+#define MIB_RX512BYTE_NR_E                6
+
+#define MIB_RX1024BYTE                    "Rx1024Byte"
+#define MIB_RX1024BYTE_ID                 45
+#define MIB_RX1024BYTE_OFFSET             0x2002c
+#define MIB_RX1024BYTE_E_LENGTH           4
+#define MIB_RX1024BYTE_E_OFFSET           0x100
+#define MIB_RX1024BYTE_NR_E               6
+
+#define MIB_RX1518BYTE                    "Rx1518Byte"
+#define MIB_RX1518BYTE_ID                 45
+#define MIB_RX1518BYTE_OFFSET             0x20030
+#define MIB_RX1518BYTE_E_LENGTH           4
+#define MIB_RX1518BYTE_E_OFFSET           0x100
+#define MIB_RX1518BYTE_NR_E               6
+
+#define MIB_RXMAXBYTE                     "RxMaxByte"
+#define MIB_RXMAXBYTE_ID                  46
+#define MIB_RXMAXBYTE_OFFSET              0x20034
+#define MIB_RXMAXBYTE_E_LENGTH            4
+#define MIB_RXMAXBYTE_E_OFFSET            0x100
+#define MIB_RXMAXBYTE_NR_E                6
+
+#define MIB_RXTOOLONG                     "RxTooLong"
+#define MIB_RXTOOLONG_ID                  47
+#define MIB_RXTOOLONG_OFFSET              0x20038
+#define MIB_RXTOOLONG_E_LENGTH            4
+#define MIB_RXTOOLONG_E_OFFSET            0x100
+#define MIB_RXTOOLONG_NR_E                6
+
+#define MIB_RXGOODBYTE_LO                 "RxGoodByteLo"
+#define MIB_RXGOODBYTE_LO_ID              48
+#define MIB_RXGOODBYTE_LO_OFFSET          0x2003c
+#define MIB_RXGOODBYTE_LO_E_LENGTH        4
+#define MIB_RXGOODBYTE_LO_E_OFFSET        0x100
+#define MIB_RXGOODBYTE_LO_NR_E            6
+
+#define MIB_RXGOODBYTE_HI                 "RxGoodByteHi"
+#define MIB_RXGOODBYTE_HI_ID              49
+#define MIB_RXGOODBYTE_HI_OFFSET          0x20040
+#define MIB_RXGOODBYTE_HI_E_LENGTH        4
+#define MIB_RXGOODBYTE_HI_E_OFFSET        0x100
+#define MIB_RXGOODBYTE_HI_NR_E            6
+
+#define MIB_RXBADBYTE_LO                  "RxBadByteLo"
+#define MIB_RXBADBYTE_LO_ID               50
+#define MIB_RXBADBYTE_LO_OFFSET           0x20044
+#define MIB_RXBADBYTE_LO_E_LENGTH         4
+#define MIB_RXBADBYTE_LO_E_OFFSET         0x100
+#define MIB_RXBADBYTE_LO_NR_E             6
+
+#define MIB_RXBADBYTE_HI                  "RxBadByteHi"
+#define MIB_RXBADBYTE_HI_ID               51
+#define MIB_RXBADBYTE_HI_OFFSET           0x20048
+#define MIB_RXBADBYTE_HI_E_LENGTH         4
+#define MIB_RXBADBYTE_HI_E_OFFSET         0x100
+#define MIB_RXBADBYTE_HI_NR_E             6
+
+#define MIB_RXOVERFLOW                    "RxOverFlow"
+#define MIB_RXOVERFLOW_ID                 52
+#define MIB_RXOVERFLOW_OFFSET             0x2004c
+#define MIB_RXOVERFLOW_E_LENGTH           4
+#define MIB_RXOVERFLOW_E_OFFSET           0x100
+#define MIB_RXOVERFLOW_NR_E               6
+
+#define MIB_FILTERED                      "Filtered"
+#define MIB_FILTERED_ID                   53
+#define MIB_FILTERED_OFFSET               0x20050
+#define MIB_FILTERED_E_LENGTH             4
+#define MIB_FILTERED_E_OFFSET             0x100
+#define MIB_FILTERED_NR_E                 6
+
+#define MIB_TXBROAD                       "TxBroad"
+#define MIB_TXBROAD_ID                    54
+#define MIB_TXBROAD_OFFSET                0x20054
+#define MIB_TXBROAD_E_LENGTH              4
+#define MIB_TXBROAD_E_OFFSET              0x100
+#define MIB_TXBROAD_NR_E                  6
+
+#define MIB_TXPAUSE                       "TxPause"
+#define MIB_TXPAUSE_ID                    55
+#define MIB_TXPAUSE_OFFSET                0x20058
+#define MIB_TXPAUSE_E_LENGTH              4
+#define MIB_TXPAUSE_E_OFFSET              0x100
+#define MIB_TXPAUSE_NR_E                  6
+
+#define MIB_TXMULTI                       "TxMulti"
+#define MIB_TXMULTI_ID                    56
+#define MIB_TXMULTI_OFFSET                0x2005c
+#define MIB_TXMULTI_E_LENGTH              4
+#define MIB_TXMULTI_E_OFFSET              0x100
+#define MIB_TXMULTI_NR_E                  6
+
+#define MIB_TXUNDERRUN                    "TxUnderRun"
+#define MIB_TXUNDERRUN_ID                 57
+#define MIB_TXUNDERRUN_OFFSET             0x20060
+#define MIB_TXUNDERRUN_E_LENGTH           4
+#define MIB_TXUNDERRUN_E_OFFSET           0x100
+#define MIB_TXUNDERRUN_NR_E               6
+
+#define MIB_TX64BYTE                      "Tx64Byte"
+#define MIB_TX64BYTE_ID                   58
+#define MIB_TX64BYTE_OFFSET               0x20064
+#define MIB_TX64BYTE_E_LENGTH             4
+#define MIB_TX64BYTE_E_OFFSET             0x100
+#define MIB_TX64BYTE_NR_E                 6
+
+#define MIB_TX128BYTE                     "Tx128Byte"
+#define MIB_TX128BYTE_ID                  59
+#define MIB_TX128BYTE_OFFSET              0x20068
+#define MIB_TX128BYTE_E_LENGTH            4
+#define MIB_TX128BYTE_E_OFFSET            0x100
+#define MIB_TX128BYTE_NR_E                6
+
+#define MIB_TX256BYTE                     "Tx256Byte"
+#define MIB_TX256BYTE_ID                  60
+#define MIB_TX256BYTE_OFFSET              0x2006c
+#define MIB_TX256BYTE_E_LENGTH            4
+#define MIB_TX256BYTE_E_OFFSET            0x100
+#define MIB_TX256BYTE_NR_E                6
+
+#define MIB_TX512BYTE                     "Tx512Byte"
+#define MIB_TX512BYTE_ID                  61
+#define MIB_TX512BYTE_OFFSET              0x20070
+#define MIB_TX512BYTE_E_LENGTH            4
+#define MIB_TX512BYTE_E_OFFSET            0x100
+#define MIB_TX512BYTE_NR_E                6
+
+#define MIB_TX1024BYTE                    "Tx1024Byte"
+#define MIB_TX1024BYTE_ID                 62
+#define MIB_TX1024BYTE_OFFSET             0x20074
+#define MIB_TX1024BYTE_E_LENGTH           4
+#define MIB_TX1024BYTE_E_OFFSET           0x100
+#define MIB_TX1024BYTE_NR_E               6
+
+#define MIB_TX1518BYTE                    "Tx1518Byte"
+#define MIB_TX1518BYTE_ID                 62
+#define MIB_TX1518BYTE_OFFSET             0x20078
+#define MIB_TX1518BYTE_E_LENGTH           4
+#define MIB_TX1518BYTE_E_OFFSET           0x100
+#define MIB_TX1518BYTE_NR_E               6
+
+#define MIB_TXMAXBYTE                     "TxMaxByte"
+#define MIB_TXMAXBYTE_ID                  63
+#define MIB_TXMAXBYTE_OFFSET              0x2007c
+#define MIB_TXMAXBYTE_E_LENGTH            4
+#define MIB_TXMAXBYTE_E_OFFSET            0x100
+#define MIB_TXMAXBYTE_NR_E                6
+
+#define MIB_TXOVERSIZE                    "TxOverSize"
+#define MIB_TXOVERSIZE_ID                 64
+#define MIB_TXOVERSIZE_OFFSET             0x20080
+#define MIB_TXOVERSIZE_E_LENGTH           4
+#define MIB_TXOVERSIZE_E_OFFSET           0x100
+#define MIB_TXOVERSIZE_NR_E               6
+
+#define MIB_TXBYTE_LO                     "TxByteLo"
+#define MIB_TXBYTE_LO_ID                  65
+#define MIB_TXBYTE_LO_OFFSET              0x20084
+#define MIB_TXBYTE_LO_E_LENGTH            4
+#define MIB_TXBYTE_LO_E_OFFSET            0x100
+#define MIB_TXBYTE_LO_NR_E                6
+
+#define MIB_TXBYTE_HI                     "TxByteHi"
+#define MIB_TXBYTE_HI_ID                  66
+#define MIB_TXBYTE_HI_OFFSET              0x20088
+#define MIB_TXBYTE_HI_E_LENGTH            4
+#define MIB_TXBYTE_HI_E_OFFSET            0x100
+#define MIB_TXBYTE_HI_NR_E                6
+
+#define MIB_TXCOLLISION                   "TxCollision"
+#define MIB_TXCOLLISION_ID                67
+#define MIB_TXCOLLISION_OFFSET            0x2008c
+#define MIB_TXCOLLISION_E_LENGTH          4
+#define MIB_TXCOLLISION_E_OFFSET          0x100
+#define MIB_TXCOLLISION_NR_E              6
+
+#define MIB_TXABORTCOL                    "TxAbortCol"
+#define MIB_TXABORTCOL_ID                 68
+#define MIB_TXABORTCOL_OFFSET             0x20090
+#define MIB_TXABORTCOL_E_LENGTH           4
+#define MIB_TXABORTCOL_E_OFFSET           0x100
+#define MIB_TXABORTCOL_NR_E               6
+
+#define MIB_TXMULTICOL                    "TxMultiCol"
+#define MIB_TXMULTICOL_ID                 69
+#define MIB_TXMULTICOL_OFFSET             0x20094
+#define MIB_TXMULTICOL_E_LENGTH           4
+#define MIB_TXMULTICOL_E_OFFSET           0x100
+#define MIB_TXMULTICOL_NR_E               6
+
+#define MIB_TXSINGALCOL                   "TxSingalCol"
+#define MIB_TXSINGALCOL_ID                70
+#define MIB_TXSINGALCOL_OFFSET            0x20098
+#define MIB_TXSINGALCOL_E_LENGTH          4
+#define MIB_TXSINGALCOL_E_OFFSET          0x100
+#define MIB_TXSINGALCOL_NR_E              6
+
+#define MIB_TXEXCDEFER                    "TxExcDefer"
+#define MIB_TXEXCDEFER_ID                 71
+#define MIB_TXEXCDEFER_OFFSET             0x2009c
+#define MIB_TXEXCDEFER_E_LENGTH           4
+#define MIB_TXEXCDEFER_E_OFFSET           0x100
+#define MIB_TXEXCDEFER_NR_E               6
+
+#define MIB_TXDEFER                       "TxDefer"
+#define MIB_TXDEFER_ID                    72
+#define MIB_TXDEFER_OFFSET                0x200a0
+#define MIB_TXDEFER_E_LENGTH              4
+#define MIB_TXDEFER_E_OFFSET              0x100
+#define MIB_TXDEFER_NR_E                  6
+
+#define MIB_TXLATECOL                     "TxLateCol"
+#define MIB_TXLATECOL_ID                  73
+#define MIB_TXLATECOL_OFFSET              0x200a4
+#define MIB_TXLATECOL_E_LENGTH            4
+#define MIB_TXLATECOL_E_OFFSET            0x100
+#define MIB_TXLATECOL_NR_E                6
+
+#if 0
+    /* mib info second mem block */
+#define MIB_RXBROAD_2                     "RxBroad_2"
+#define MIB_RXBROAD_2_ID                  34
+#define MIB_RXBROAD_2_OFFSET              (MIB_RXBROAD_OFFSET + 0x400)
+#define MIB_RXBROAD_2_E_LENGTH            4
+#define MIB_RXBROAD_2_E_OFFSET            0xa8
+#define MIB_RXBROAD_2_NR_E                6
+
+#define MIB_RXPAUSE_2                     "RxPause_2"
+#define MIB_RXPAUSE_2_ID                  35
+#define MIB_RXPAUSE_2_OFFSET              (MIB_RXPAUSE_OFFSET + 0x400)
+#define MIB_RXPAUSE_2_E_LENGTH            4
+#define MIB_RXPAUSE_2_E_OFFSET            0xa8
+#define MIB_RXPAUSE_2_NR_E                6
+
+#define MIB_RXMULTI_2                     "RxMulti_2"
+#define MIB_RXMULTI_2_ID                  36
+#define MIB_RXMULTI_2_OFFSET              (MIB_RXMULTI_OFFSET + 0x400)
+#define MIB_RXMULTI_2_E_LENGTH            4
+#define MIB_RXMULTI_2_E_OFFSET            0xa8
+#define MIB_RXMULTI_2_NR_E                6
+
+#define MIB_RXFCSERR_2                    "RxFcsErr_2"
+#define MIB_RXFCSERR_2_ID                 37
+#define MIB_RXFCSERR_2_OFFSET             (MIB_RXFCSERR_OFFSET + 0x400)
+#define MIB_RXFCSERR_2_E_LENGTH           4
+#define MIB_RXFCSERR_2_E_OFFSET           0xa8
+#define MIB_RXFCSERR_2_NR_E               6
+
+#define MIB_RXALLIGNERR_2                 "RxAllignErr_2"
+#define MIB_RXALLIGNERR_2_ID              38
+#define MIB_RXALLIGNERR_2_OFFSET          (MIB_RXALLIGNERR_OFFSET + 0x400)
+#define MIB_RXALLIGNERR_2_E_LENGTH        4
+#define MIB_RXALLIGNERR_2_E_OFFSET        0xa8
+#define MIB_RXALLIGNERR_2_NR_E            6
+
+#define MIB_RXRUNT_2                      "RxRunt_2"
+#define MIB_RXRUNT_2_ID                   39
+#define MIB_RXRUNT_2_OFFSET               (MIB_RXRUNT_OFFSET + 0x400)
+#define MIB_RXRUNT_2_E_LENGTH             4
+#define MIB_RXRUNT_2_E_OFFSET             0xa8
+#define MIB_RXRUNT_2_NR_E                 6
+
+#define MIB_RXFRAGMENT_2                  "RxFragment_2"
+#define MIB_RXFRAGMENT_2_ID               40
+#define MIB_RXFRAGMENT_2_OFFSET           (MIB_RXFRAGMENT_OFFSET + 0x400)
+#define MIB_RXFRAGMENT_2_E_LENGTH         4
+#define MIB_RXFRAGMENT_2_E_OFFSET         0xa8
+#define MIB_RXFRAGMENT_2_NR_E             6
+
+#define MIB_RX64BYTE_2                    "Rx64Byte_2"
+#define MIB_RX64BYTE_2_ID                 41
+#define MIB_RX64BYTE_2_OFFSET             (MIB_RX64BYTE_OFFSET + 0x400)
+#define MIB_RX64BYTE_2_E_LENGTH           4
+#define MIB_RX64BYTE_2_E_OFFSET           0xa8
+#define MIB_RX64BYTE_2_NR_E               6
+
+#define MIB_RX128BYTE_2                   "Rx128Byte_2"
+#define MIB_RX128BYTE_2_ID                42
+#define MIB_RX128BYTE_2_OFFSET            (MIB_RX128BYTE_OFFSET + 0x400)
+#define MIB_RX128BYTE_2_E_LENGTH          4
+#define MIB_RX128BYTE_2_E_OFFSET          0xa8
+#define MIB_RX128BYTE_2_NR_E              6
+
+#define MIB_RX256BYTE_2                   "Rx256Byte_2"
+#define MIB_RX256BYTE_2_ID                43
+#define MIB_RX256BYTE_2_OFFSET            (MIB_RX256BYTE_OFFSET + 0x400)
+#define MIB_RX256BYTE_2_E_LENGTH          4
+#define MIB_RX256BYTE_2_E_OFFSET          0xa8
+#define MIB_RX256BYTE_2_NR_E              6
+
+#define MIB_RX512BYTE_2                   "Rx512Byte_2"
+#define MIB_RX512BYTE_2_ID                44
+#define MIB_RX512BYTE_2_OFFSET            (MIB_RX512BYTE_OFFSET + 0x400)
+#define MIB_RX512BYTE_2_E_LENGTH          4
+#define MIB_RX512BYTE_2_E_OFFSET          0xa8
+#define MIB_RX512BYTE_2_NR_E              6
+
+#define MIB_RX1024BYTE_2                  "Rx1024Byte_2"
+#define MIB_RX1024BYTE_2_ID               45
+#define MIB_RX1024BYTE_2_OFFSET           (MIB_RX1024BYTE_OFFSET + 0x400)
+#define MIB_RX1024BYTE_2_E_LENGTH         4
+#define MIB_RX1024BYTE_2_E_OFFSET         0xa8
+#define MIB_RX1024BYTE_2_NR_E             6
+
+#define MIB_RX1518BYTE_2                  "Rx1518Byte_2"
+#define MIB_RX1518BYTE_2_ID               45
+#define MIB_RX1518BYTE_2_OFFSET           (MIB_RX1518BYTE_OFFSET + 0x400)
+#define MIB_RX1518BYTE_2_E_LENGTH         4
+#define MIB_RX1518BYTE_2_E_OFFSET         0xa8
+#define MIB_RX1518BYTE_2_NR_E             6
+
+#define MIB_RXMAXBYTE_2                   "RxMaxByte_2"
+#define MIB_RXMAXBYTE_2_ID                46
+#define MIB_RXMAXBYTE_2_OFFSET            (MIB_RXMAXBYTE_OFFSET + 0x400)
+#define MIB_RXMAXBYTE_2_E_LENGTH          4
+#define MIB_RXMAXBYTE_2_E_OFFSET          0xa8
+#define MIB_RXMAXBYTE_2_NR_E              6
+
+#define MIB_RXTOOLONG_2                   "RxTooLong_2"
+#define MIB_RXTOOLONG_2_ID                47
+#define MIB_RXTOOLONG_2_OFFSET            (MIB_RXTOOLONG_OFFSET + 0x400)
+#define MIB_RXTOOLONG_2_E_LENGTH          4
+#define MIB_RXTOOLONG_2_E_OFFSET          0xa8
+#define MIB_RXTOOLONG_2_NR_E             6
+
+#define MIB_RXGOODBYTE_LO_2               "RxGoodByteLo_2"
+#define MIB_RXGOODBYTE_LO_2_ID            48
+#define MIB_RXGOODBYTE_LO_2_OFFSET        (MIB_RXGOODBYTE_LO_OFFSET + 0x400)
+#define MIB_RXGOODBYTE_LO_2_E_LENGTH      4
+#define MIB_RXGOODBYTE_LO_2_E_OFFSET      0xa8
+#define MIB_RXGOODBYTE_LO_2_NR_E          6
+
+#define MIB_RXGOODBYTE_HI_2               "RxGoodByteHi_2"
+#define MIB_RXGOODBYTE_HI_2_ID            49
+#define MIB_RXGOODBYTE_HI_2_OFFSET        (MIB_RXGOODBYTE_HI_OFFSET + 0x400)
+#define MIB_RXGOODBYTE_HI_2_E_LENGTH      4
+#define MIB_RXGOODBYTE_HI_2_E_OFFSET      0xa8
+#define MIB_RXGOODBYTE_HI_2_NR_E          6
+
+#define MIB_RXBADBYTE_LO_2                "RxBadByteLo_2"
+#define MIB_RXBADBYTE_LO_2_ID             50
+#define MIB_RXBADBYTE_LO_2_OFFSET         (MIB_RXBADBYTE_LO_OFFSET + 0x400)
+#define MIB_RXBADBYTE_LO_2_E_LENGTH       4
+#define MIB_RXBADBYTE_LO_2_E_OFFSET       0xa8
+#define MIB_RXBADBYTE_LO_2_NR_E           6
+
+#define MIB_RXBADBYTE_HI_2                "RxBadByteHi_2"
+#define MIB_RXBADBYTE_HI_2_ID             51
+#define MIB_RXBADBYTE_HI_2_OFFSET         (MIB_RXBADBYTE_HI_OFFSET + 0x400)
+#define MIB_RXBADBYTE_HI_2_E_LENGTH       4
+#define MIB_RXBADBYTE_HI_2_E_OFFSET       0xa8
+#define MIB_RXBADBYTE_HI_2_NR_E           6
+
+#define MIB_RXOVERFLOW_2                  "RxOverFlow_2"
+#define MIB_RXOVERFLOW_2_ID               52
+#define MIB_RXOVERFLOW_2_OFFSET           (MIB_RXOVERFLOW_OFFSET + 0x400)
+#define MIB_RXOVERFLOW_2_E_LENGTH         4
+#define MIB_RXOVERFLOW_2_E_OFFSET         0xa8
+#define MIB_RXOVERFLOW_2_NR_E             6
+
+#define MIB_FILTERED_2                    "Filtered_2"
+#define MIB_FILTERED_2_ID                 53
+#define MIB_FILTERED_2_OFFSET             (MIB_FILTERED_OFFSET + 0x400)
+#define MIB_FILTERED_2_E_LENGTH           4
+#define MIB_FILTERED_2_E_OFFSET           0xa8
+#define MIB_FILTERED_2_NR_E               6
+
+#define MIB_TXBROAD_2                     "TxBroad_2"
+#define MIB_TXBROAD_2_ID                  54
+#define MIB_TXBROAD_2_OFFSET              (MIB_TXBROAD_OFFSET + 0x400)
+#define MIB_TXBROAD_2_E_LENGTH            4
+#define MIB_TXBROAD_2_E_OFFSET            0xa8
+#define MIB_TXBROAD_2_NR_E                6
+
+#define MIB_TXPAUSE_2                     "TxPause_2"
+#define MIB_TXPAUSE_2_ID                  55
+#define MIB_TXPAUSE_2_OFFSET              (MIB_TXPAUSE_OFFSET + 0x400)
+#define MIB_TXPAUSE_2_E_LENGTH            4
+#define MIB_TXPAUSE_2_E_OFFSET            0xa8
+#define MIB_TXPAUSE_2_NR_E                6
+
+#define MIB_TXMULTI_2                     "TxMulti_2"
+#define MIB_TXMULTI_2_ID                  56
+#define MIB_TXMULTI_2_OFFSET              (MIB_TXMULTI_OFFSET + 0x400)
+#define MIB_TXMULTI_2_E_LENGTH            4
+#define MIB_TXMULTI_2_E_OFFSET            0xa8
+#define MIB_TXMULTI_2_NR_E                6
+
+#define MIB_TXUNDERRUN_2                  "TxUnderRun_2"
+#define MIB_TXUNDERRUN_2_ID               57
+#define MIB_TXUNDERRUN_2_OFFSET           (MIB_TXUNDERRUN_OFFSET + 0x400)
+#define MIB_TXUNDERRUN_2_E_LENGTH         4
+#define MIB_TXUNDERRUN_2_E_OFFSET         0xa8
+#define MIB_TXUNDERRUN_2_NR_E             6
+
+#define MIB_TX64BYTE_2                    "Tx64Byte_2"
+#define MIB_TX64BYTE_2_ID                 58
+#define MIB_TX64BYTE_2_OFFSET             (MIB_TX64BYTE_OFFSET + 0x400)
+#define MIB_TX64BYTE_2_E_LENGTH           4
+#define MIB_TX64BYTE_2_E_OFFSET           0xa8
+#define MIB_TX64BYTE_2_NR_E               6
+
+#define MIB_TX128BYTE_2                   "Tx128Byte_2"
+#define MIB_TX128BYTE_2_ID                59
+#define MIB_TX128BYTE_2_OFFSET            (MIB_TX128BYTE_OFFSET + 0x400)
+#define MIB_TX128BYTE_2_E_LENGTH          4
+#define MIB_TX128BYTE_2_E_OFFSET          0xa8
+#define MIB_TX128BYTE_2_NR_E              6
+
+#define MIB_TX256BYTE_2                   "Tx256Byte_2"
+#define MIB_TX256BYTE_2_ID                60
+#define MIB_TX256BYTE_2_OFFSET            (MIB_TX256BYTE_OFFSET + 0x400)
+#define MIB_TX256BYTE_2_E_LENGTH          4
+#define MIB_TX256BYTE_2_E_OFFSET          0xa8
+#define MIB_TX256BYTE_2_NR_E              6
+
+#define MIB_TX512BYTE_2                   "Tx512Byte_2"
+#define MIB_TX512BYTE_2_ID                61
+#define MIB_TX512BYTE_2_OFFSET            (MIB_TX512BYTE_OFFSET + 0x400)
+#define MIB_TX512BYTE_2_E_LENGTH          4
+#define MIB_TX512BYTE_2_E_OFFSET          0xa8
+#define MIB_TX512BYTE_2_NR_E              6
+
+#define MIB_TX1024BYTE_2                  "Tx1024Byte_2"
+#define MIB_TX1024BYTE_2_ID               62
+#define MIB_TX1024BYTE_2_OFFSET           (MIB_TX1024BYTE_OFFSET + 0x400)
+#define MIB_TX1024BYTE_2_E_LENGTH         4
+#define MIB_TX1024BYTE_2_E_OFFSET         0xa8
+#define MIB_TX1024BYTE_2_NR_E             6
+
+#define MIB_TX1518BYTE_2                  "Tx1518Byte_2"
+#define MIB_TX1518BYTE_2_ID               62
+#define MIB_TX1518BYTE_2_OFFSET           (MIB_TX1518BYTE_OFFSET + 0x400)
+#define MIB_TX1518BYTE_2_E_LENGTH         4
+#define MIB_TX1518BYTE_2_E_OFFSET         0xa8
+#define MIB_TX1518BYTE_2_NR_E             6
+
+#define MIB_TXMAXBYTE_2                   "TxMaxByte_2"
+#define MIB_TXMAXBYTE_2_ID                63
+#define MIB_TXMAXBYTE_2_OFFSET            (MIB_TXMAXBYTE_OFFSET + 0x400)
+#define MIB_TXMAXBYTE_2_E_LENGTH          4
+#define MIB_TXMAXBYTE_2_E_OFFSET          0xa8
+#define MIB_TXMAXBYTE_2_NR_E              6
+
+#define MIB_TXOVERSIZE_2                  "TxOverSize_2"
+#define MIB_TXOVERSIZE_2_ID               64
+#define MIB_TXOVERSIZE_2_OFFSET           (MIB_TXOVERSIZE_OFFSET + 0x400)
+#define MIB_TXOVERSIZE_2_E_LENGTH         4
+#define MIB_TXOVERSIZE_2_E_OFFSET         0xa8
+#define MIB_TXOVERSIZE_2_NR_E             6
+
+#define MIB_TXBYTE_LO_2                   "TxByteLo_2"
+#define MIB_TXBYTE_LO_2_ID                65
+#define MIB_TXBYTE_LO_2_OFFSET            (MIB_TXBYTE_LO_OFFSET + 0x400)
+#define MIB_TXBYTE_LO_2_E_LENGTH          4
+#define MIB_TXBYTE_LO_2_E_OFFSET          0xa8
+#define MIB_TXBYTE_LO_2_NR_E              6
+
+#define MIB_TXBYTE_HI_2                   "TxByteHi_2"
+#define MIB_TXBYTE_HI_2_ID                66
+#define MIB_TXBYTE_HI_2_OFFSET            (MIB_TXBYTE_HI_OFFSET + 0x400)
+#define MIB_TXBYTE_HI_2_E_LENGTH          4
+#define MIB_TXBYTE_HI_2_E_OFFSET          0xa8
+#define MIB_TXBYTE_HI_2_NR_E              6
+
+#define MIB_TXCOLLISION_2                 "TxCollision_2"
+#define MIB_TXCOLLISION_2_ID              67
+#define MIB_TXCOLLISION_2_OFFSET          (MIB_TXCOLLISION_OFFSET + 0x400)
+#define MIB_TXCOLLISION_2_E_LENGTH        4
+#define MIB_TXCOLLISION_2_E_OFFSET        0xa8
+#define MIB_TXCOLLISION_2_NR_E            6
+
+#define MIB_TXABORTCOL_2                  "TxAbortCol_2"
+#define MIB_TXABORTCOL_2_ID               68
+#define MIB_TXABORTCOL_2_OFFSET           (MIB_TXABORTCOL_OFFSET + 0x400)
+#define MIB_TXABORTCOL_2_E_LENGTH         4
+#define MIB_TXABORTCOL_2_E_OFFSET         0xa8
+#define MIB_TXABORTCOL_2_NR_E             6
+
+#define MIB_TXMULTICOL_2                  "TxMultiCol_2"
+#define MIB_TXMULTICOL_2_ID               69
+#define MIB_TXMULTICOL_2_OFFSET           (MIB_TXMULTICOL_OFFSET + 0x400)
+#define MIB_TXMULTICOL_2_E_LENGTH         4
+#define MIB_TXMULTICOL_2_E_OFFSET         0xa8
+#define MIB_TXMULTICOL_2_NR_E             6
+
+#define MIB_TXSINGALCOL_2                 "TxSingalCol_2"
+#define MIB_TXSINGALCOL_2_ID              70
+#define MIB_TXSINGALCOL_2_OFFSET          (MIB_TXSINGALCOL_OFFSET + 0x400)
+#define MIB_TXSINGALCOL_2_E_LENGTH        4
+#define MIB_TXSINGALCOL_2_E_OFFSET        0xa8
+#define MIB_TXSINGALCOL_2_NR_E            6
+
+#define MIB_TXEXCDEFER_2                  "TxExcDefer_2"
+#define MIB_TXEXCDEFER_2_ID               71
+#define MIB_TXEXCDEFER_2_OFFSET           (MIB_TXEXCDEFER_OFFSET + 0x400)
+#define MIB_TXEXCDEFER_2_E_LENGTH         4
+#define MIB_TXEXCDEFER_2_E_OFFSET         0xa8
+#define MIB_TXEXCDEFER_2_NR_E             6
+
+#define MIB_TXDEFER_2                     "TxDefer_2"
+#define MIB_TXDEFER_2_ID                  72
+#define MIB_TXDEFER_2_OFFSET              (MIB_TXDEFER_OFFSET + 0x400)
+#define MIB_TXDEFER_2_E_LENGTH            4
+#define MIB_TXDEFER_2_E_OFFSET            0xa8
+#define MIB_TXDEFER_2_NR_E                6
+
+#define MIB_TXLATECOL_2                   "TxLateCol_2"
+#define MIB_TXLATECOL_2_ID                73
+#define MIB_TXLATECOL_2_OFFSET            (MIB_TXLATECOL_OFFSET + 0x400)
+#define MIB_TXLATECOL_2_E_LENGTH          4
+#define MIB_TXLATECOL_2_E_OFFSET          0xa8
+#define MIB_TXLATECOL_2_NR_E              6
+#endif
+
+#define ACL_RSLT                         "aclact"
+#define ACL_RSLT_ID                      13
+#define ACL_RSLT_OFFSET                  0x58000
+#define ACL_RSLT_E_LENGTH                4
+#define ACL_RSLT_E_OFFSET                0x20
+#define ACL_RSLT_NR_E                    32
+
+#define RDTCPU                           "aclact_rdtpu"
+#define ACL_RSLT_RDTCPU_BOFFSET          31
+#define ACL_RSLT_RDTCPU_BLEN             1
+#define ACL_RSLT_RDTCPU_FLAG             HSL_RW
+
+#define CPYCPU                           "aclact_cpcpu"
+#define ACL_RSLT_CPYCPU_BOFFSET          30
+#define ACL_RSLT_CPYCPU_BLEN             1
+#define ACL_RSLT_CPYCPU_FLAG             HSL_RW
+
+#define MIRR_EN                          "aclact_mirr"
+#define ACL_RSLT_MIRR_EN_BOFFSET         29
+#define ACL_RSLT_MIRR_EN_BLEN            1
+#define ACL_RSLT_MIRR_EN_FLAG            HSL_RW
+
+#define STAG_CHG_EN                      "aclact_rdcpu"
+#define ACL_RSLT_STAG_CHG_EN_BOFFSET     28
+#define ACL_RSLT_STAG_CHG_EN_BLEN        1
+#define ACL_RSLT_STAG_CHG_EN_FLAG        HSL_RW
+
+#define VID_MEM_EN                       "aclact_rdcpu"
+#define ACL_RSLT_VID_MEM_EN_BOFFSET      27
+#define ACL_RSLT_VID_MEM_EN_BLEN         1
+#define ACL_RSLT_VID_MEM_EN_FLAG         HSL_RW
+
+#define DES_PORT_EN                      "aclact_rdcpu"
+#define ACL_RSLT_DES_PORT_EN_BOFFSET     26
+#define ACL_RSLT_DES_PORT_EN_BLEN        1
+#define ACL_RSLT_DES_PORT_EN_FLAG        HSL_RW
+
+#define PORT_MEM                         "aclact_rdcpu"
+#define ACL_RSLT_PORT_MEM_BOFFSET        20
+#define ACL_RSLT_PORT_MEM_BLEN           6
+#define ACL_RSLT_PORT_MEM_FLAG           HSL_RW
+
+#define REMARK_PRI_QU                    "aclact_rdcpu"
+#define ACL_RSLT_REMARK_PRI_QU_BOFFSET   19
+#define ACL_RSLT_REMARK_PRI_QU_BLEN      1
+#define ACL_RSLT_REMARK_PRI_QU_FLAG      HSL_RW
+
+#define DOT1P                            "aclact_rdcpu"
+#define ACL_RSLT_DOT1P_BOFFSET           16
+#define ACL_RSLT_DOT1P_BLEN              3
+#define ACL_RSLT_DOT1P_FLAG              HSL_RW
+
+#define PRI_QU                           "aclact_rdcpu"
+#define ACL_RSLT_PRI_QU_BOFFSET          14
+#define ACL_RSLT_PRI_QU_BLEN             2
+#define ACL_RSLT_PRI_QU_FLAG             HSL_RW
+
+#define REMARK_DOT1P                     "aclact_rdcpu"
+#define ACL_RSLT_REMARK_DOT1P_BOFFSET    13
+#define ACL_RSLT_REMARK_DOT1P_BLEN       1
+#define ACL_RSLT_REMARK_DOT1P_FLAG       HSL_RW
+
+#define CHG_VID_EN                       "aclact_rdcpu"
+#define ACL_RSLT_CHG_VID_EN_BOFFSET      12
+#define ACL_RSLT_CHG_VID_EN_BLEN         1
+#define ACL_RSLT_CHG_VID_EN_FLAG         HSL_RW
+
+#define VID                              "aclact_rdcpu"
+#define ACL_RSLT_VID_BOFFSET             0
+#define ACL_RSLT_VID_BLEN                12
+#define ACL_RSLT_VID_FLAG                HSL_RW
+
+
+
+
+#define RUL_SLCT0                         "rulslct0"
+#define RUL_SLCT0_ID                      13
+#define RUL_SLCT0_OFFSET                  0x58800
+#define RUL_SLCT0_E_LENGTH                4
+#define RUL_SLCT0_E_OFFSET                0x20
+#define RUL_SLCT0_NR_E                    32
+
+#define ADDR3_EN                         "rulslct_addr3en"
+#define RUL_SLCT0_ADDR3_EN_BOFFSET        3
+#define RUL_SLCT0_ADDR3_EN_BLEN           1
+#define RUL_SLCT0_ADDR3_EN_FLAG           HSL_RW
+
+#define ADDR2_EN                         "rulslct_addr2en"
+#define RUL_SLCT0_ADDR2_EN_BOFFSET        2
+#define RUL_SLCT0_ADDR2_EN_BLEN           1
+#define RUL_SLCT0_ADDR2_EN_FLAG           HSL_RW
+
+#define ADDR1_EN                         "rulslct_addr1en"
+#define RUL_SLCT0_ADDR1_EN_BOFFSET        1
+#define RUL_SLCT0_ADDR1_EN_BLEN           1
+#define RUL_SLCT0_ADDR1_EN_FLAG           HSL_RW
+
+#define ADDR0_EN                         "rulslct_addr0en"
+#define RUL_SLCT0_ADDR0_EN_BOFFSET        0
+#define RUL_SLCT0_ADDR0_EN_BLEN           1
+#define RUL_SLCT0_ADDR0_EN_FLAG           HSL_RW
+
+
+
+
+#define RUL_SLCT1                         "rulslct1"
+#define RUL_SLCT1_ID                      13
+#define RUL_SLCT1_OFFSET                  0x58804
+#define RUL_SLCT1_E_LENGTH                4
+#define RUL_SLCT1_E_OFFSET                0x20
+#define RUL_SLCT1_NR_E                    32
+
+#define ADDR0                            "rulslct1_addr0"
+#define RUL_SLCT1_ADDR0_BOFFSET           0
+#define RUL_SLCT1_ADDR0_BLEN              5
+#define RUL_SLCT1_ADDR0_FLAG              HSL_RW
+
+
+
+
+#define RUL_SLCT2                         "rulslct2"
+#define RUL_SLCT2_ID                      13
+#define RUL_SLCT2_OFFSET                  0x58808
+#define RUL_SLCT2_E_LENGTH                4
+#define RUL_SLCT2_E_OFFSET                0x20
+#define RUL_SLCT2_NR_E                    32
+
+#define ADDR1                            "rulslct2_addr1"
+#define RUL_SLCT2_ADDR1_BOFFSET           0
+#define RUL_SLCT2_ADDR1_BLEN              5
+#define RUL_SLCT2_ADDR1_FLAG              HSL_RW
+
+
+
+
+#define RUL_SLCT3                         "rulslct3"
+#define RUL_SLCT3_ID                      13
+#define RUL_SLCT3_OFFSET                  0x5880c
+#define RUL_SLCT3_E_LENGTH                4
+#define RUL_SLCT3_E_OFFSET                0x20
+#define RUL_SLCT3_NR_E                    32
+
+#define ADDR2                            "rulslct3_addr2"
+#define RUL_SLCT3_ADDR2_BOFFSET           0
+#define RUL_SLCT3_ADDR2_BLEN              5
+#define RUL_SLCT3_ADDR2_FLAG              HSL_RW
+
+
+
+
+#define RUL_SLCT4                         "rulslct4"
+#define RUL_SLCT4_ID                      13
+#define RUL_SLCT4_OFFSET                  0x58810
+#define RUL_SLCT4_E_LENGTH                4
+#define RUL_SLCT4_E_OFFSET                0x20
+#define RUL_SLCT4_NR_E                    32
+
+#define ADDR3                            "rulslct4_addr3"
+#define RUL_SLCT4_ADDR3_BOFFSET          0
+#define RUL_SLCT4_ADDR3_BLEN             5
+#define RUL_SLCT4_ADDR3_FLAG              HSL_RW
+
+
+
+
+#define RUL_SLCT6                         "rulslct6"
+#define RUL_SLCT6_ID                      13
+#define RUL_SLCT6_OFFSET                  0x58818
+#define RUL_SLCT6_E_LENGTH                4
+#define RUL_SLCT6_E_OFFSET                0x20
+#define RUL_SLCT6_NR_E                    32
+
+#define RULE_LEN                           "rulslct6_rulelen"
+#define RUL_SLCT6_RULE_LEN_BOFFSET         0
+#define RUL_SLCT6_RULE_LEN_BLEN            6
+#define RUL_SLCT6_RULE_LEN_FLAG            HSL_RW
+
+
+
+
+#define RUL_TYPE                         "ruletype"
+#define RUL_TYPE_ID                      13
+#define RUL_TYPE_OFFSET                  0x5881c
+#define RUL_TYPE_E_LENGTH                4
+#define RUL_TYPE_E_OFFSET                0x20
+#define RUL_TYPE_NR_E                    32
+
+#define TYP                              "ruletype_typ"
+#define RUL_TYPE_TYP_BOFFSET             0
+#define RUL_TYPE_TYP_BLEN                3
+#define RUL_TYPE_TYP_FLAG                 HSL_RW
+
+
+
+
+#define MAC_RUL_V0                         "macrv0"
+#define MAC_RUL_V0_ID                      13
+#define MAC_RUL_V0_OFFSET                  0x58400
+#define MAC_RUL_V0_E_LENGTH                4
+#define MAC_RUL_V0_E_OFFSET                0x20
+#define MAC_RUL_V0_NR_E                    32
+
+#define DAV_BYTE2                             "macrv0_dav2"
+#define MAC_RUL_V0_DAV_BYTE2_BOFFSET             24
+#define MAC_RUL_V0_DAV_BYTE2_BLEN                8
+#define MAC_RUL_V0_DAV_BYTE2_FLAG                HSL_RW
+
+#define DAV_BYTE3                             "macrv0_dav3"
+#define MAC_RUL_V0_DAV_BYTE3_BOFFSET             16
+#define MAC_RUL_V0_DAV_BYTE3_BLEN                8
+#define MAC_RUL_V0_DAV_BYTE3_FLAG                HSL_RW
+
+#define DAV_BYTE4                             "macrv0_dav4"
+#define MAC_RUL_V0_DAV_BYTE4_BOFFSET             8
+#define MAC_RUL_V0_DAV_BYTE4_BLEN                8
+#define MAC_RUL_V0_DAV_BYTE4_FLAG                HSL_RW
+
+#define DAV_BYTE5                             "macrv0_dav5"
+#define MAC_RUL_V0_DAV_BYTE5_BOFFSET             0
+#define MAC_RUL_V0_DAV_BYTE5_BLEN                8
+#define MAC_RUL_V0_DAV_BYTE5_FLAG                HSL_RW
+
+
+
+
+#define MAC_RUL_V1                         "macrv1"
+#define MAC_RUL_V1_ID                      13
+#define MAC_RUL_V1_OFFSET                  0x58404
+#define MAC_RUL_V1_E_LENGTH                4
+#define MAC_RUL_V1_E_OFFSET                0x20
+#define MAC_RUL_V1_NR_E                    32
+
+#define SAV_BYTE4                             "macrv1_sav4"
+#define MAC_RUL_V1_SAV_BYTE4_BOFFSET             24
+#define MAC_RUL_V1_SAV_BYTE4_BLEN                8
+#define MAC_RUL_V1_SAV_BYTE4_FLAG                HSL_RW
+
+#define SAV_BYTE5                             "macrv1_sav5"
+#define MAC_RUL_V1_SAV_BYTE5_BOFFSET             16
+#define MAC_RUL_V1_SAV_BYTE5_BLEN                8
+#define MAC_RUL_V1_SAV_BYTE5_FLAG                HSL_RW
+
+#define DAV_BYTE0                             "macrv1_dav0"
+#define MAC_RUL_V1_DAV_BYTE0_BOFFSET             8
+#define MAC_RUL_V1_DAV_BYTE0_BLEN                8
+#define MAC_RUL_V1_DAV_BYTE0_FLAG                HSL_RW
+
+#define DAV_BYTE1                             "macrv1_dav1"
+#define MAC_RUL_V1_DAV_BYTE1_BOFFSET             0
+#define MAC_RUL_V1_DAV_BYTE1_BLEN                8
+#define MAC_RUL_V1_DAV_BYTE1_FLAG                HSL_RW
+
+
+
+
+#define MAC_RUL_V2                         "macrv2"
+#define MAC_RUL_V2_ID                      13
+#define MAC_RUL_V2_OFFSET                  0x58408
+#define MAC_RUL_V2_E_LENGTH                4
+#define MAC_RUL_V2_E_OFFSET                0x20
+#define MAC_RUL_V2_NR_E                    32
+
+#define SAV_BYTE0                             "macrv2_sav0"
+#define MAC_RUL_V2_SAV_BYTE0_BOFFSET             24
+#define MAC_RUL_V2_SAV_BYTE0_BLEN                8
+#define MAC_RUL_V2_SAV_BYTE0_FLAG                HSL_RW
+
+#define SAV_BYTE1                             "macrv2_sav1"
+#define MAC_RUL_V2_SAV_BYTE1_BOFFSET             16
+#define MAC_RUL_V2_SAV_BYTE1_BLEN                8
+#define MAC_RUL_V2_SAV_BYTE1_FLAG                HSL_RW
+
+#define SAV_BYTE2                             "macrv2_sav2"
+#define MAC_RUL_V2_SAV_BYTE2_BOFFSET             8
+#define MAC_RUL_V2_SAV_BYTE2_BLEN                8
+#define MAC_RUL_V2_SAV_BYTE2_FLAG                HSL_RW
+
+#define SAV_BYTE3                             "macrv2_sav3"
+#define MAC_RUL_V2_SAV_BYTE3_BOFFSET             0
+#define MAC_RUL_V2_SAV_BYTE3_BLEN                8
+#define MAC_RUL_V2_SAV_BYTE3_FLAG                HSL_RW
+
+
+
+
+#define MAC_RUL_V3                         "macrv3"
+#define MAC_RUL_V3_ID                      13
+#define MAC_RUL_V3_OFFSET                  0x5840c
+#define MAC_RUL_V3_E_LENGTH                4
+#define MAC_RUL_V3_E_OFFSET                0x20
+#define MAC_RUL_V3_NR_E                    32
+
+#define ETHTYPV                             "macrv3_ethtypv"
+#define MAC_RUL_V3_ETHTYPV_BOFFSET             16
+#define MAC_RUL_V3_ETHTYPV_BLEN                16
+#define MAC_RUL_V3_ETHTYPV_FLAG                HSL_RW
+
+#define VLANPRIV                             "macrv3_vlanpriv"
+#define MAC_RUL_V3_VLANPRIV_BOFFSET             13
+#define MAC_RUL_V3_VLANPRIV_BLEN                3
+#define MAC_RUL_V3_VLANPRIV_FLAG                HSL_RW
+
+#define VLANIDV                             "macrv3_vlanidv"
+#define MAC_RUL_V3_VLANIDV_BOFFSET             0
+#define MAC_RUL_V3_VLANIDV_BLEN                12
+#define MAC_RUL_V3_VLANIDV_FLAG                HSL_RW
+
+
+
+
+#define MAC_RUL_V4                         "macrv4"
+#define MAC_RUL_V4_ID                      13
+#define MAC_RUL_V4_OFFSET                  0x58410
+#define MAC_RUL_V4_E_LENGTH                4
+#define MAC_RUL_V4_E_OFFSET                0x20
+#define MAC_RUL_V4_NR_E                    32
+
+#define TAGGEDM                           "macrv4_vlanid"
+#define MAC_RUL_V4_TAGGEDM_BOFFSET             7
+#define MAC_RUL_V4_TAGGEDM_BLEN                1
+#define MAC_RUL_V4_TAGGEDM_FLAG                HSL_RW
+
+#define TAGGEDV                           "macrv4_vlanid"
+#define MAC_RUL_V4_TAGGEDV_BOFFSET             6
+#define MAC_RUL_V4_TAGGEDV_BLEN                1
+#define MAC_RUL_V4_TAGGEDV_FLAG                HSL_RW
+
+#define MAC_INPT                           "macrv4_vlanid"
+#define MAC_RUL_V4_MAC_INPT_BOFFSET         0
+#define MAC_RUL_V4_MAC_INPT_BLEN            6
+#define MAC_RUL_V4_MAC_INPT_FLAG            HSL_RW
+
+
+
+
+
+#define MAC_RUL_M0                         "macrv0"
+#define MAC_RUL_M0_ID                      13
+#define MAC_RUL_M0_OFFSET                  0x58c00
+#define MAC_RUL_M0_E_LENGTH                4
+#define MAC_RUL_M0_E_OFFSET                0x20
+#define MAC_RUL_M0_NR_E                    32
+
+#define DAM_BYTE2                             "macrv0_dam2"
+#define MAC_RUL_M0_DAM_BYTE2_BOFFSET             24
+#define MAC_RUL_M0_DAM_BYTE2_BLEN                8
+#define MAC_RUL_M0_DAM_BYTE2_FLAG                HSL_RW
+
+#define DAM_BYTE3                             "macrv0_dam3"
+#define MAC_RUL_M0_DAM_BYTE3_BOFFSET             16
+#define MAC_RUL_M0_DAM_BYTE3_BLEN                8
+#define MAC_RUL_M0_DAM_BYTE3_FLAG                HSL_RW
+
+#define DAM_BYTE4                             "macrv0_dam4"
+#define MAC_RUL_M0_DAM_BYTE4_BOFFSET             8
+#define MAC_RUL_M0_DAM_BYTE4_BLEN                8
+#define MAC_RUL_M0_DAM_BYTE4_FLAG                HSL_RW
+
+#define DAM_BYTE5                             "macrv0_dam5"
+#define MAC_RUL_M0_DAM_BYTE5_BOFFSET             0
+#define MAC_RUL_M0_DAM_BYTE5_BLEN                8
+#define MAC_RUL_M0_DAM_BYTE5_FLAG                HSL_RW
+
+
+
+
+#define MAC_RUL_M1                         "macrm1"
+#define MAC_RUL_M1_ID                      13
+#define MAC_RUL_M1_OFFSET                  0x58c04
+#define MAC_RUL_M1_E_LENGTH                4
+#define MAC_RUL_M1_E_OFFSET                0x20
+#define MAC_RUL_M1_NR_E                    32
+
+#define SAM_BYTE4                             "macrm1_sam4"
+#define MAC_RUL_M1_SAM_BYTE4_BOFFSET             24
+#define MAC_RUL_M1_SAM_BYTE4_BLEN                8
+#define MAC_RUL_M1_SAM_BYTE4_FLAG                HSL_RW
+
+#define SAM_BYTE5                             "macrm1_sam5"
+#define MAC_RUL_M1_SAM_BYTE5_BOFFSET             16
+#define MAC_RUL_M1_SAM_BYTE5_BLEN                8
+#define MAC_RUL_M1_SAM_BYTE5_FLAG                HSL_RW
+
+#define DAM_BYTE0                             "macrm1_dam0"
+#define MAC_RUL_M1_DAM_BYTE0_BOFFSET             8
+#define MAC_RUL_M1_DAM_BYTE0_BLEN                8
+#define MAC_RUL_M1_DAM_BYTE0_FLAG                HSL_RW
+
+#define DAM_BYTE1                             "macrm1_dam1"
+#define MAC_RUL_M1_DAM_BYTE1_BOFFSET             0
+#define MAC_RUL_M1_DAM_BYTE1_BLEN                8
+#define MAC_RUL_M1_DAM_BYTE1_FLAG                HSL_RW
+
+
+
+
+#define MAC_RUL_M2                         "macrm2"
+#define MAC_RUL_M2_ID                      13
+#define MAC_RUL_M2_OFFSET                  0x58c08
+#define MAC_RUL_M2_E_LENGTH                4
+#define MAC_RUL_M2_E_OFFSET                0x20
+#define MAC_RUL_M2_NR_E                    32
+
+#define SAM_BYTE0                             "macrm2_sam0"
+#define MAC_RUL_M2_SAM_BYTE0_BOFFSET             24
+#define MAC_RUL_M2_SAM_BYTE0_BLEN                8
+#define MAC_RUL_M2_SAM_BYTE0_FLAG                HSL_RW
+
+#define SAM_BYTE1                             "macrm2_samv1"
+#define MAC_RUL_M2_SAM_BYTE1_BOFFSET             16
+#define MAC_RUL_M2_SAM_BYTE1_BLEN                8
+#define MAC_RUL_M2_SAM_BYTE1_FLAG                HSL_RW
+
+#define SAM_BYTE2                             "macrm2_sam2"
+#define MAC_RUL_M2_SAM_BYTE2_BOFFSET             8
+#define MAC_RUL_M2_SAM_BYTE2_BLEN                8
+#define MAC_RUL_M2_SAM_BYTE2_FLAG                HSL_RW
+
+#define SAM_BYTE3                             "macrm2_sam3"
+#define MAC_RUL_M2_SAM_BYTE3_BOFFSET             0
+#define MAC_RUL_M2_SAM_BYTE3_BLEN                8
+#define MAC_RUL_M2_SAM_BYTE3_FLAG                HSL_RW
+
+
+
+
+#define MAC_RUL_M3                         "macrv3"
+#define MAC_RUL_M3_ID                      13
+#define MAC_RUL_M3_OFFSET                  0x58c0c
+#define MAC_RUL_M3_E_LENGTH                4
+#define MAC_RUL_M3_E_OFFSET                0x20
+#define MAC_RUL_M3_NR_E                    32
+
+#define ETHTYPM                             "macrm3_ethtypm"
+#define MAC_RUL_M3_ETHTYPM_BOFFSET             16
+#define MAC_RUL_M3_ETHTYPM_BLEN                16
+#define MAC_RUL_M3_ETHTYPM_FLAG                HSL_RW
+
+#define VLANPRIM                             "macrm3_vlanprim"
+#define MAC_RUL_M3_VLANPRIM_BOFFSET             13
+#define MAC_RUL_M3_VLANPRIM_BLEN                3
+#define MAC_RUL_M3_VLANPRIM_FLAG                HSL_RW
+
+#define VIDMSK                               "macrm3_vidmsk"
+#define MAC_RUL_M3_VIDMSK_BOFFSET             12
+#define MAC_RUL_M3_VIDMSK_BLEN                1
+#define MAC_RUL_M3_VIDMSK_FLAG                HSL_RW
+
+#define VLANIDM                             "macrm3_vlanidm"
+#define MAC_RUL_M3_VLANIDM_BOFFSET             0
+#define MAC_RUL_M3_VLANIDM_BLEN                12
+#define MAC_RUL_M3_VLANIDM_FLAG                HSL_RW
+
+
+
+
+#define IP4_RUL_V0                         "ip4v0"
+#define IP4_RUL_V0_ID                      13
+#define IP4_RUL_V0_OFFSET                  0x58400
+#define IP4_RUL_V0_E_LENGTH                4
+#define IP4_RUL_V0_E_OFFSET                0x20
+#define IP4_RUL_V0_NR_E                    32
+
+#define DIPV                                "ip4v0_dipv"
+#define IP4_RUL_V0_DIPV_BOFFSET             0
+#define IP4_RUL_V0_DIPV_BLEN                32
+#define IP4_RUL_V0_DIPV_FLAG                HSL_RW
+
+
+
+
+#define IP4_RUL_V1                         "ip4v1"
+#define IP4_RUL_V1_ID                      13
+#define IP4_RUL_V1_OFFSET                  0x58404
+#define IP4_RUL_V1_E_LENGTH                4
+#define IP4_RUL_V1_E_OFFSET                0x20
+#define IP4_RUL_V1_NR_E                    32
+
+#define SIPV                               "ip4v1_sipv"
+#define IP4_RUL_V1_SIPV_BOFFSET             0
+#define IP4_RUL_V1_SIPV_BLEN                32
+#define IP4_RUL_V1_SIPV_FLAG                HSL_RW
+
+
+
+
+#define IP4_RUL_V2                         "ip4v2"
+#define IP4_RUL_V2_ID                      13
+#define IP4_RUL_V2_OFFSET                  0x58408
+#define IP4_RUL_V2_E_LENGTH                4
+#define IP4_RUL_V2_E_OFFSET                0x20
+#define IP4_RUL_V2_NR_E                    32
+
+#define IP4PROTV                               "ip4v2_protv"
+#define IP4_RUL_V2_IP4PROTV_BOFFSET             0
+#define IP4_RUL_V2_IP4PROTV_BLEN                8
+#define IP4_RUL_V2_IP4PROTV_FLAG                HSL_RW
+
+#define IP4DSCPV                               "ip4v2_dscpv"
+#define IP4_RUL_V2_IP4DSCPV_BOFFSET             8
+#define IP4_RUL_V2_IP4DSCPV_BLEN                8
+#define IP4_RUL_V2_IP4DSCPV_FLAG                HSL_RW
+
+#define IP4DPORTV                               "ip4v2_dportv"
+#define IP4_RUL_V2_IP4DPORTV_BOFFSET             16
+#define IP4_RUL_V2_IP4DPORTV_BLEN                16
+#define IP4_RUL_V2_IP4DPORTV_FLAG                HSL_RW
+
+
+
+
+#define IP4_RUL_V3                         "ip4v3"
+#define IP4_RUL_V3_ID                      13
+#define IP4_RUL_V3_OFFSET                  0x5840c
+#define IP4_RUL_V3_E_LENGTH                4
+#define IP4_RUL_V3_E_OFFSET                0x20
+#define IP4_RUL_V3_NR_E                    32
+
+#define IP4SPORTV                          "ip4v3_sportv"
+#define IP4_RUL_V3_IP4SPORTV_BOFFSET       0
+#define IP4_RUL_V3_IP4SPORTV_BLEN          16
+#define IP4_RUL_V3_IP4SPORTV_FLAG          HSL_RW
+
+
+#define IP4_RUL_V4                         "ip4v2"
+#define IP4_RUL_V4_ID                      13
+#define IP4_RUL_V4_OFFSET                  0x58410
+#define IP4_RUL_V4_E_LENGTH                4
+#define IP4_RUL_V4_E_OFFSET                0x20
+#define IP4_RUL_V4_NR_E                    32
+
+#define IP4_INPT                            "ip4rv4_inpt"
+#define IP4_RUL_V4_IP4_INPT_BOFFSET             0
+#define IP4_RUL_V4_IP4_INPT_BLEN                6
+#define IP4_RUL_V4_IP4_INPT_FLAG                HSL_RW
+
+
+
+
+
+
+#define IP4_RUL_M0                         "ip4m0"
+#define IP4_RUL_M0_ID                      13
+#define IP4_RUL_M0_OFFSET                  0x58c00
+#define IP4_RUL_M0_E_LENGTH                4
+#define IP4_RUL_M0_E_OFFSET                0x20
+#define IP4_RUL_M0_NR_E                    32
+
+#define DIPM                             "ip4m0_dipm"
+#define IP4_RUL_M0_DIPM_BOFFSET             0
+#define IP4_RUL_M0_DIPM_BLEN                32
+#define IP4_RUL_M0_DIPM_FLAG                HSL_RW
+
+
+
+
+#define IP4_RUL_M1                         "ip4m1"
+#define IP4_RUL_M1_ID                      13
+#define IP4_RUL_M1_OFFSET                  0x58c04
+#define IP4_RUL_M1_E_LENGTH                4
+#define IP4_RUL_M1_E_OFFSET                0x20
+#define IP4_RUL_M1_NR_E                    32
+
+#define SIPM                               "ip4m1_sipm"
+#define IP4_RUL_M1_SIPM_BOFFSET             0
+#define IP4_RUL_M1_SIPM_BLEN                32
+#define IP4_RUL_M1_SIPM_FLAG                HSL_RW
+
+
+
+
+#define IP4_RUL_M2                         "ip4m2"
+#define IP4_RUL_M2_ID                      13
+#define IP4_RUL_M2_OFFSET                  0x58c08
+#define IP4_RUL_M2_E_LENGTH                4
+#define IP4_RUL_M2_E_OFFSET                0x20
+#define IP4_RUL_M2_NR_E                    32
+
+#define IP4PROTM                               "ip4m2_protm"
+#define IP4_RUL_M2_IP4PROTM_BOFFSET             0
+#define IP4_RUL_M2_IP4PROTM_BLEN                8
+#define IP4_RUL_M2_IP4PROTM_FLAG                HSL_RW
+
+#define IP4DSCPM                               "ip4m2_dscpm"
+#define IP4_RUL_M2_IP4DSCPM_BOFFSET             8
+#define IP4_RUL_M2_IP4DSCPM_BLEN                8
+#define IP4_RUL_M2_IP4DSCPM_FLAG                HSL_RW
+
+#define IP4DPORTM                               "ip4m2_dportm"
+#define IP4_RUL_M2_IP4DPORTM_BOFFSET             16
+#define IP4_RUL_M2_IP4DPORTM_BLEN                16
+#define IP4_RUL_M2_IP4DPORTM_FLAG                HSL_RW
+
+
+
+
+#define IP4_RUL_M3                         "ip4m3"
+#define IP4_RUL_M3_ID                      13
+#define IP4_RUL_M3_OFFSET                  0x58c0c
+#define IP4_RUL_M3_E_LENGTH                4
+#define IP4_RUL_M3_E_OFFSET                0x20
+#define IP4_RUL_M3_NR_E                    32
+
+#define IP4SPORTM                               "ip4m3_sportm"
+#define IP4_RUL_M3_IP4SPORTM_BOFFSET             0
+#define IP4_RUL_M3_IP4SPORTM_BLEN                16
+#define IP4_RUL_M3_IP4SPORTM_FLAG                HSL_RW
+
+#define IP4SPORTM_EN                             "ip4m3_sportmen"
+#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET           16
+#define IP4_RUL_M3_IP4SPORTM_EN_BLEN                1
+#define IP4_RUL_M3_IP4SPORTM_EN_FLAG                HSL_RW
+
+#define IP4DPORTM_EN                               "ip4m3_dportmen"
+#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET             17
+#define IP4_RUL_M3_IP4DPORTM_EN_BLEN                1
+#define IP4_RUL_M3_IP4DPORTM_EN_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL1_V0                        "ip6r1v0"
+#define IP6_RUL1_V0_ID                      13
+#define IP6_RUL1_V0_OFFSET                  0x58400
+#define IP6_RUL1_V0_E_LENGTH                4
+#define IP6_RUL1_V0_E_OFFSET                0x20
+#define IP6_RUL1_V0_NR_E                    32
+
+#define IP6_DIPV0                           "ip6r1v0_dipv0"
+#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET             0
+#define IP6_RUL1_V0_IP6_DIPV0_BLEN                32
+#define IP6_RUL1_V0_IP6_DIPV0_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL1_V1                        "ip6r1v1"
+#define IP6_RUL1_V1_ID                      13
+#define IP6_RUL1_V1_OFFSET                  0x58404
+#define IP6_RUL1_V1_E_LENGTH                4
+#define IP6_RUL1_V1_E_OFFSET                0x20
+#define IP6_RUL1_V1_NR_E                    32
+
+#define IP6_DIPV1                           "ip6r1v1_dipv1"
+#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET             0
+#define IP6_RUL1_V1_IP6_DIPv1_BLEN                32
+#define IP6_RUL1_V1_IP6_DIPV1_FLAG                HSL_RW
+
+
+
+#define IP6_RUL1_V2                        "ip6r1v2"
+#define IP6_RUL1_V2_ID                      13
+#define IP6_RUL1_V2_OFFSET                  0x58408
+#define IP6_RUL1_V2_E_LENGTH                4
+#define IP6_RUL1_V2_E_OFFSET                0x20
+#define IP6_RUL1_V2_NR_E                    32
+
+#define IP6_DIPV2                           "ip6r1v2_dipv2"
+#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET             0
+#define IP6_RUL1_V2_IP6_DIPv2_BLEN                32
+#define IP6_RUL1_V2_IP6_DIPV2_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL1_V3                        "ip6r1v3"
+#define IP6_RUL1_V3_ID                      13
+#define IP6_RUL1_V3_OFFSET                  0x5840c
+#define IP6_RUL1_V3_E_LENGTH                4
+#define IP6_RUL1_V3_E_OFFSET                0x20
+#define IP6_RUL1_V3_NR_E                    32
+
+#define IP6_DIPV3                           "ip6r1v3_dipv3"
+#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET             0
+#define IP6_RUL1_V3_IP6_DIPv3_BLEN                32
+#define IP6_RUL1_V3_IP6_DIPV3_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL1_V4                        "ip6r1v4"
+#define IP6_RUL1_V4_ID                      13
+#define IP6_RUL1_V4_OFFSET                  0x58410
+#define IP6_RUL1_V4_E_LENGTH                4
+#define IP6_RUL1_V4_E_OFFSET                0x20
+#define IP6_RUL1_V4_NR_E                    32
+
+#define IP6_RUL1_INPT                           "ip6r1v4_inpt"
+#define IP6_RUL1_V4_IP6_RUL1_INPT_BOFFSET             0
+#define IP6_RUL1_V4_IP6_RUL1_INPT_BLEN                6
+#define IP6_RUL1_V4_IP6_RUL1_INPT_FLAG                HSL_RW
+
+
+
+
+
+#define IP6_RUL1_M0                        "ip6r1m0"
+#define IP6_RUL1_M0_ID                      13
+#define IP6_RUL1_M0_OFFSET                  0x58c00
+#define IP6_RUL1_M0_E_LENGTH                4
+#define IP6_RUL1_M0_E_OFFSET                0x20
+#define IP6_RUL1_M0_NR_E                    32
+
+#define IP6_DIPM0                           "ip6r1m0_dipm0"
+#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET             0
+#define IP6_RUL1_M0_IP6_DIPM0_BLEN                32
+#define IP6_RUL1_M0_IP6_DIPM0_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL1_M1                        "ip6r1m1"
+#define IP6_RUL1_M1_ID                      13
+#define IP6_RUL1_M1_OFFSET                  0x58c04
+#define IP6_RUL1_M1_E_LENGTH                4
+#define IP6_RUL1_M1_E_OFFSET                0x20
+#define IP6_RUL1_M1_NR_E                    32
+
+#define IP6_DIPM1                           "ip6r1m1_dipm1"
+#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET             0
+#define IP6_RUL1_M1_IP6_DIPM1_BLEN                32
+#define IP6_RUL1_M1_IP6_DIPM1_FLAG                HSL_RW
+
+
+
+#define IP6_RUL1_M2                        "ip6r1m2"
+#define IP6_RUL1_M2_ID                      13
+#define IP6_RUL1_M2_OFFSET                  0x58c08
+#define IP6_RUL1_M2_E_LENGTH                4
+#define IP6_RUL1_M2_E_OFFSET                0x20
+#define IP6_RUL1_M2_NR_E                    32
+
+#define IP6_DIPM2                           "ip6r1m2_dipm2"
+#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET             0
+#define IP6_RUL1_M2_IP6_DIPM2_BLEN                32
+#define IP6_RUL1_M2_IP6_DIPM2_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL1_M3                        "ip6r1m3"
+#define IP6_RUL1_M3_ID                      13
+#define IP6_RUL1_M3_OFFSET                  0x58c0c
+#define IP6_RUL1_M3_E_LENGTH                4
+#define IP6_RUL1_M3_E_OFFSET                0x20
+#define IP6_RUL1_M3_NR_E                    32
+
+#define IP6_DIPM3                           "ip6r1m3_dipm3"
+#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET             0
+#define IP6_RUL1_M3_IP6_DIPM3_BLEN                32
+#define IP6_RUL1_M3_IP6_DIPM3_FLAG                HSL_RW
+
+
+
+
+
+#define IP6_RUL2_V0                        "ip6r2v0"
+#define IP6_RUL2_V0_ID                      13
+#define IP6_RUL2_V0_OFFSET                  0x58400
+#define IP6_RUL2_V0_E_LENGTH                4
+#define IP6_RUL2_V0_E_OFFSET                0x20
+#define IP6_RUL2_V0_NR_E                    32
+
+#define IP6_SIPV0                           "ip6r2v0_sipv0"
+#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET             0
+#define IP6_RUL2_V0_IP6_SIPv0_BLEN                32
+#define IP6_RUL2_V0_IP6_SIPV0_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL2_V1                        "ip6r2v1"
+#define IP6_RUL2_V1_ID                      13
+#define IP6_RUL2_V1_OFFSET                  0x58404
+#define IP6_RUL2_V1_E_LENGTH                4
+#define IP6_RUL2_V1_E_OFFSET                0x20
+#define IP6_RUL2_V1_NR_E                    32
+
+#define IP6_SIPV1                           "ip6r2v1_sipv1"
+#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET             0
+#define IP6_RUL2_V1_IP6_SIPv1_BLEN                32
+#define IP6_RUL2_V1_IP6_SIPV1_FLAG                HSL_RW
+
+
+
+#define IP6_RUL2_V2                        "ip6r2v2"
+#define IP6_RUL2_V2_ID                      13
+#define IP6_RUL2_V2_OFFSET                  0x58408
+#define IP6_RUL2_V2_E_LENGTH                4
+#define IP6_RUL2_V2_E_OFFSET                0x20
+#define IP6_RUL2_V2_NR_E                    32
+
+#define IP6_SIPV2                           "ip6r2v2_sipv2"
+#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET             0
+#define IP6_RUL2_V2_IP6_SIPv2_BLEN                32
+#define IP6_RUL2_V2_IP6_SIPV2_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL2_V3                        "ip6r2v3"
+#define IP6_RUL2_V3_ID                      13
+#define IP6_RUL2_V3_OFFSET                  0x5840c
+#define IP6_RUL2_V3_E_LENGTH                4
+#define IP6_RUL2_V3_E_OFFSET                0x20
+#define IP6_RUL2_V3_NR_E                    32
+
+#define IP6_SIPV3                           "ip6r2v3_sipv3"
+#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET             0
+#define IP6_RUL2_V3_IP6_SIPv3_BLEN                32
+#define IP6_RUL2_V3_IP6_SIPV3_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL2_V4                        "ip6r2v4"
+#define IP6_RUL2_V4_ID                      13
+#define IP6_RUL2_V4_OFFSET                  0x58410
+#define IP6_RUL2_V4_E_LENGTH                4
+#define IP6_RUL2_V4_E_OFFSET                0x20
+#define IP6_RUL2_V4_NR_E                    32
+
+#define IP6_RUL2_INPT                           "ip6r2v4_inptm"
+#define IP6_RUL2_V4_IP6_RUL2_INPT_BOFFSET             0
+#define IP6_RUL2_V4_IP6_RUL2_INPT_BLEN                6
+#define IP6_RUL2_V4_IP6_RUL2_INPT_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL2_M0                        "ip6r2m0"
+#define IP6_RUL2_M0_ID                      13
+#define IP6_RUL2_M0_OFFSET                  0x58c00
+#define IP6_RUL2_M0_E_LENGTH                4
+#define IP6_RUL2_M0_E_OFFSET                0x20
+#define IP6_RUL2_M0_NR_E                    32
+
+#define IP6_SIPM0                           "ip6r2m0_sipm0"
+#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET             0
+#define IP6_RUL2_M0_IP6_SIPM0_BLEN                32
+#define IP6_RUL2_M0_IP6_SIPM0_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL2_M1                        "ip6r2m1"
+#define IP6_RUL2_M1_ID                      13
+#define IP6_RUL2_M1_OFFSET                  0x58c04
+#define IP6_RUL2_M1_E_LENGTH                4
+#define IP6_RUL2_M1_E_OFFSET                0x20
+#define IP6_RUL2_M1_NR_E                    32
+
+#define IP6_SIPM1                           "ip6r2m1_sipm1"
+#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET             0
+#define IP6_RUL2_M1_IP6_DIPM1_BLEN                32
+#define IP6_RUL2_M1_IP6_DIPM1_FLAG                HSL_RW
+
+
+
+#define IP6_RUL2_M2                        "ip6r2m2"
+#define IP6_RUL2_M2_ID                      13
+#define IP6_RUL2_M2_OFFSET                  0x58c08
+#define IP6_RUL2_M2_E_LENGTH                4
+#define IP6_RUL2_M2_E_OFFSET                0x20
+#define IP6_RUL2_M2_NR_E                    32
+
+#define IP6_SIPM2                           "ip6r2m2_sipm2"
+#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET             0
+#define IP6_RUL2_M2_IP6_DIPM2_BLEN                32
+#define IP6_RUL2_M2_IP6_DIPM2_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL2_M3                        "ip6r2m3"
+#define IP6_RUL2_M3_ID                      13
+#define IP6_RUL2_M3_OFFSET                  0x58c0c
+#define IP6_RUL2_M3_E_LENGTH                4
+#define IP6_RUL2_M3_E_OFFSET                0x20
+#define IP6_RUL2_M3_NR_E                    32
+
+#define IP6_SIPM3                           "ip6r2m3_sipm3"
+#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET             0
+#define IP6_RUL2_M3_IP6_SIPM3_BLEN                32
+#define IP6_RUL2_M3_IP6_SIPM3_FLAG                HSL_RW
+
+
+
+
+
+#define IP6_RUL3_V0                        "ip6r3v0"
+#define IP6_RUL3_V0_ID                      13
+#define IP6_RUL3_V0_OFFSET                  0x58400
+#define IP6_RUL3_V0_E_LENGTH                4
+#define IP6_RUL3_V0_E_OFFSET                0x20
+#define IP6_RUL3_V0_NR_E                    32
+
+#define IP6PROTV                           "ip6r3v0_protv"
+#define IP6_RUL3_V0_IP6PROTV_BOFFSET             0
+#define IP6_RUL3_V0_IP6PROTV_BLEN                8
+#define IP6_RUL3_V0_IP6PROTV_FLAG                HSL_RW
+
+#define IP6DSCPV                           "ip6r3v0_dscpv"
+#define IP6_RUL3_V0_IP6DSCPV_BOFFSET             8
+#define IP6_RUL3_V0_IP6DSCPV_BLEN                8
+#define IP6_RUL3_V0_IP6DSCPV_FLAG                HSL_RW
+
+#define IP6DPORTV                           "ip6r3v0_dportv"
+#define IP6_RUL3_V0_IP6DPORTV_BOFFSET             16
+#define IP6_RUL3_V0_IP6DPORTV_BLEN                16
+#define IP6_RUL3_V0_IP6DPORTV_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL3_V1                        "ip6r3v1"
+#define IP6_RUL3_V1_ID                      13
+#define IP6_RUL3_V1_OFFSET                  0x58404
+#define IP6_RUL3_V1_E_LENGTH                4
+#define IP6_RUL3_V1_E_OFFSET                0x20
+#define IP6_RUL3_V1_NR_E                    32
+
+#define IP6SPORTV                           "ip6r3v1_sportv"
+#define IP6_RUL3_V1_IP6SPORTV_BOFFSET             0
+#define IP6_RUL3_V1_IP6SPORTV_BLEN                16
+#define IP6_RUL3_V1_IP6SPORTV_FLAG                HSL_RW
+
+#define IP6LABEL1V                           "ip6r3v1_label1v"
+#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET             16
+#define IP6_RUL3_V1_IP6LABEL1V_BLEN                16
+#define IP6_RUL3_V1_IP6LABEL1V_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL3_V2                        "ip6r3v2"
+#define IP6_RUL3_V2_ID                      13
+#define IP6_RUL3_V2_OFFSET                  0x58408
+#define IP6_RUL3_V2_E_LENGTH                4
+#define IP6_RUL3_V2_E_OFFSET                0x20
+#define IP6_RUL3_V2_NR_E                    32
+
+#define IP6LABEL2V                           "ip6r3v2_label2v"
+#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET             0
+#define IP6_RUL3_V2_IP6LABEL2V_BLEN                4
+#define IP6_RUL3_V2_IP6LABEL2V_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL3_V4                        "ip6r3v4"
+#define IP6_RUL3_V4_ID                      13
+#define IP6_RUL3_V4_OFFSET                  0x58410
+#define IP6_RUL3_V4_E_LENGTH                4
+#define IP6_RUL3_V4_E_OFFSET                0x20
+#define IP6_RUL3_V4_NR_E                    32
+
+#define IP6_RUL3_INPT                           "ip6r3v4_inpt"
+#define IP6_RUL3_V4_IP6_RUL3_INPT_BOFFSET             0
+#define IP6_RUL3_V4_IP6_RUL3_INPT_BLEN                6
+#define IP6_RUL3_V4_IP6_RUL3_INPT_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL3_M0                        "ip6r3m0"
+#define IP6_RUL3_M0_ID                      13
+#define IP6_RUL3_M0_OFFSET                  0x58c00
+#define IP6_RUL3_M0_E_LENGTH                4
+#define IP6_RUL3_M0_E_OFFSET                0x20
+#define IP6_RUL3_M0_NR_E                    32
+
+#define IP6PROTM                           "ip6r3m0_protm"
+#define IP6_RUL3_M0_IP6PROTM_BOFFSET             0
+#define IP6_RUL3_M0_IP6PROTM_BLEN                8
+#define IP6_RUL3_M0_IP6PROTM_FLAG                HSL_RW
+
+#define IP6DSCPM                           "ip6r3m0_dscpm"
+#define IP6_RUL3_M0_IP6DSCPM_BOFFSET             8
+#define IP6_RUL3_M0_IP6DSCPM_BLEN                8
+#define IP6_RUL3_M0_IP6DSCPM_FLAG                HSL_RW
+
+#define IP6DPORTM                           "ip6r3m0_dportm"
+#define IP6_RUL3_M0_IP6DPORTM_BOFFSET             16
+#define IP6_RUL3_M0_IP6DPORTM_BLEN                16
+#define IP6_RUL3_M0_IP6DPORTM_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL3_M1                        "ip6r3m1"
+#define IP6_RUL3_M1_ID                      13
+#define IP6_RUL3_M1_OFFSET                  0x58c04
+#define IP6_RUL3_M1_E_LENGTH                4
+#define IP6_RUL3_M1_E_OFFSET                0x20
+#define IP6_RUL3_M1_NR_E                    32
+
+#define IP6SPORTM                           "ip6r3m1_sportm"
+#define IP6_RUL3_M1_IP6SPORTM_BOFFSET             0
+#define IP6_RUL3_M1_IP6SPORTM_BLEN                16
+#define IP6_RUL3_M1_IP6SPORTM_FLAG                HSL_RW
+
+#define IP6LABEL1M                           "ip6r3m1_label1m"
+#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET             16
+#define IP6_RUL3_M1_IP6LABEL1M_BLEN                16
+#define IP6_RUL3_M1_IP6LABEL1M_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL3_M2                        "ip6r3m2"
+#define IP6_RUL3_M2_ID                      13
+#define IP6_RUL3_M2_OFFSET                  0x58c08
+#define IP6_RUL3_M2_E_LENGTH                4
+#define IP6_RUL3_M2_E_OFFSET                0x20
+#define IP6_RUL3_M2_NR_E                    32
+
+#define IP6LABEL2M                           "ip6r3m2_label2m"
+#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET             0
+#define IP6_RUL3_M2_IP6LABEL2M_BLEN                4
+#define IP6_RUL3_M2_IP6LABEL21M_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL3_M3                        "ip6r3m3"
+#define IP6_RUL3_M3_ID                      13
+#define IP6_RUL3_M3_OFFSET                  0x58c0c
+#define IP6_RUL3_M3_E_LENGTH                4
+#define IP6_RUL3_M3_E_OFFSET                0x20
+#define IP6_RUL3_M3_NR_E                    32
+
+
+#define IP6DPORTM_EN                               "ip6r3m3_dportmen"
+#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET             25
+#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN                1
+#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG                HSL_RW
+
+#define IP6SPORTM_EN                               "ip6r3m3_sportmen"
+#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET             24
+#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN                1
+#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG                HSL_RW
+
+
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _GARUDA_REG_H_ */
+
diff --git a/qca-ssdk/include/hsl/garuda/garuda_reg_access.h b/qca-ssdk/include/hsl/garuda/garuda_reg_access.h
new file mode 100755
index 0000000..3325e9f
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_reg_access.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _GARUDA_REG_ACCESS_H_
+#define _GARUDA_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "sw.h"
+
+    sw_error_t
+    garuda_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+                   a_uint32_t reg, a_uint16_t * value);
+
+    sw_error_t
+    garuda_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+                   a_uint32_t reg, a_uint16_t value);
+
+    sw_error_t
+    garuda_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                   a_uint32_t value_len);
+
+    sw_error_t
+    garuda_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                   a_uint32_t value_len);
+
+    sw_error_t
+    garuda_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                         a_uint32_t bit_offset, a_uint32_t field_len,
+                         a_uint8_t value[], a_uint32_t value_len);
+
+    sw_error_t
+    garuda_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                         a_uint32_t bit_offset, a_uint32_t field_len,
+                         const a_uint8_t value[], a_uint32_t value_len);
+
+    sw_error_t
+    garuda_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode);
+
+    sw_error_t
+    garuda_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _GARUDA_REG_ACCESS_H_ */
+
diff --git a/qca-ssdk/include/hsl/garuda/garuda_stp.h b/qca-ssdk/include/hsl/garuda/garuda_stp.h
new file mode 100755
index 0000000..c811291
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_stp.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_stp GARUDA_STP
+ * @{
+ */
+#ifndef _GARUDA_STP_H_
+#define _GARUDA_STP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_stp.h"
+
+    sw_error_t garuda_stp_init(a_uint32_t dev_id);
+
+#ifdef IN_STP
+#define GARUDA_STP_INIT(rv, dev_id) \
+    { \
+        rv = garuda_stp_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define GARUDA_STP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    garuda_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                              fal_port_t port_id, fal_stp_state_t state);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                              fal_port_t port_id, fal_stp_state_t * state);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _GARUDA_STP_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/garuda/garuda_vlan.h b/qca-ssdk/include/hsl/garuda/garuda_vlan.h
new file mode 100755
index 0000000..9eff433
--- /dev/null
+++ b/qca-ssdk/include/hsl/garuda/garuda_vlan.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_vlan GARUDA_VLAN
+ * @{
+ */
+#ifndef _GARUDA_VLAN_H_
+#define _GARUDA_VLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_vlan.h"
+
+    sw_error_t
+    garuda_vlan_init(a_uint32_t dev_id);
+
+#ifdef IN_VLAN
+#define GARUDA_VLAN_INIT(rv, dev_id) \
+    { \
+        rv = garuda_vlan_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define GARUDA_VLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    garuda_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                              fal_pbmp_t member, fal_pbmp_t u_member);
+
+
+
+    HSL_LOCAL sw_error_t
+    garuda_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _GARUDA_VLAN_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/horus/horus_api.h b/qca-ssdk/include/hsl/horus/horus_api.h
new file mode 100755
index 0000000..aed76d2
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_api.h
@@ -0,0 +1,559 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HORUS_API_H_
+#define _HORUS_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#ifdef IN_PORTCONTROL
+#define PORTCONTROL_API \
+    SW_API_DEF(SW_API_PT_DUPLEX_GET, horus_port_duplex_get), \
+    SW_API_DEF(SW_API_PT_DUPLEX_SET, horus_port_duplex_set), \
+    SW_API_DEF(SW_API_PT_SPEED_GET, horus_port_speed_get), \
+    SW_API_DEF(SW_API_PT_SPEED_SET, horus_port_speed_set), \
+    SW_API_DEF(SW_API_PT_AN_GET, horus_port_autoneg_status_get), \
+    SW_API_DEF(SW_API_PT_AN_ENABLE, horus_port_autoneg_enable), \
+    SW_API_DEF(SW_API_PT_AN_RESTART, horus_port_autoneg_restart), \
+    SW_API_DEF(SW_API_PT_AN_ADV_GET, horus_port_autoneg_adv_get), \
+    SW_API_DEF(SW_API_PT_AN_ADV_SET, horus_port_autoneg_adv_set), \
+    SW_API_DEF(SW_API_PT_HDR_SET, horus_port_hdr_status_set), \
+    SW_API_DEF(SW_API_PT_HDR_GET, horus_port_hdr_status_get), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_SET, horus_port_flowctrl_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_GET, horus_port_flowctrl_get), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, horus_port_flowctrl_forcemode_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, horus_port_flowctrl_forcemode_get), \
+    SW_API_DEF(SW_API_PT_POWERSAVE_SET, horus_port_powersave_set), \
+    SW_API_DEF(SW_API_PT_POWERSAVE_GET, horus_port_powersave_get), \
+    SW_API_DEF(SW_API_PT_HIBERNATE_SET, horus_port_hibernate_set), \
+    SW_API_DEF(SW_API_PT_HIBERNATE_GET, horus_port_hibernate_get), \
+    SW_API_DEF(SW_API_PT_CDT, horus_port_cdt),
+
+#define PORTCONTROL_API_PARAM \
+    SW_API_DESC(SW_API_PT_DUPLEX_GET) \
+    SW_API_DESC(SW_API_PT_DUPLEX_SET) \
+    SW_API_DESC(SW_API_PT_SPEED_GET)  \
+    SW_API_DESC(SW_API_PT_SPEED_SET)  \
+    SW_API_DESC(SW_API_PT_AN_GET)  \
+    SW_API_DESC(SW_API_PT_AN_ENABLE)   \
+    SW_API_DESC(SW_API_PT_AN_RESTART)  \
+    SW_API_DESC(SW_API_PT_AN_ADV_GET)  \
+    SW_API_DESC(SW_API_PT_AN_ADV_SET)  \
+    SW_API_DESC(SW_API_PT_HDR_SET)  \
+    SW_API_DESC(SW_API_PT_HDR_GET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_SET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_GET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
+    SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
+    SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
+    SW_API_DESC(SW_API_PT_HIBERNATE_GET) \
+    SW_API_DESC(SW_API_PT_CDT)
+#else
+#define PORTCONTROL_API
+#define PORTCONTROL_API_PARAM
+#endif
+
+
+#ifdef IN_VLAN
+#define VLAN_API \
+    SW_API_DEF(SW_API_VLAN_ADD, horus_vlan_create), \
+    SW_API_DEF(SW_API_VLAN_DEL, horus_vlan_delete), \
+    SW_API_DEF(SW_API_VLAN_MEM_UPDATE, horus_vlan_member_update), \
+    SW_API_DEF(SW_API_VLAN_FIND, horus_vlan_find), \
+    SW_API_DEF(SW_API_VLAN_NEXT, horus_vlan_next), \
+    SW_API_DEF(SW_API_VLAN_APPEND, horus_vlan_entry_append),
+
+#define VLAN_API_PARAM \
+    SW_API_DESC(SW_API_VLAN_ADD)  \
+    SW_API_DESC(SW_API_VLAN_DEL)  \
+    SW_API_DESC(SW_API_VLAN_MEM_UPDATE)  \
+    SW_API_DESC(SW_API_VLAN_FIND)  \
+    SW_API_DESC(SW_API_VLAN_NEXT)  \
+    SW_API_DESC(SW_API_VLAN_APPEND)
+#else
+#define VLAN_API
+#define VLAN_API_PARAM
+#endif
+
+
+#ifdef IN_PORTVLAN
+#define PORTVLAN_API \
+    SW_API_DEF(SW_API_PT_ING_MODE_GET, horus_port_1qmode_get), \
+    SW_API_DEF(SW_API_PT_ING_MODE_SET, horus_port_1qmode_set), \
+    SW_API_DEF(SW_API_PT_EG_MODE_GET, horus_port_egvlanmode_get), \
+    SW_API_DEF(SW_API_PT_EG_MODE_SET, horus_port_egvlanmode_set), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, horus_portvlan_member_add), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, horus_portvlan_member_del), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, horus_portvlan_member_update), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_GET, horus_portvlan_member_get), \
+    SW_API_DEF(SW_API_PT_DEF_VID_SET, horus_port_default_vid_set), \
+    SW_API_DEF(SW_API_PT_DEF_VID_GET, horus_port_default_vid_get), \
+    SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, horus_port_force_default_vid_set), \
+    SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, horus_port_force_default_vid_get), \
+    SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, horus_port_force_portvlan_set), \
+    SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, horus_port_force_portvlan_get), \
+    SW_API_DEF(SW_API_NESTVLAN_TPID_SET, horus_nestvlan_tpid_set), \
+    SW_API_DEF(SW_API_NESTVLAN_TPID_GET, horus_nestvlan_tpid_get), \
+    SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, horus_port_invlan_mode_set), \
+    SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, horus_port_invlan_mode_get), \
+    SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, horus_port_pri_propagation_set), \
+    SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, horus_port_pri_propagation_get), \
+    SW_API_DEF(SW_API_QINQ_MODE_SET, horus_qinq_mode_set), \
+    SW_API_DEF(SW_API_QINQ_MODE_GET, horus_qinq_mode_get), \
+    SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, horus_port_qinq_role_set), \
+    SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, horus_port_qinq_role_get),
+
+#define PORTVLAN_API_PARAM \
+    SW_API_DESC(SW_API_PT_ING_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_ING_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_EG_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_EG_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE)  \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_GET)     \
+    SW_API_DESC(SW_API_PT_DEF_VID_SET)    \
+    SW_API_DESC(SW_API_PT_DEF_VID_GET)    \
+    SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET)    \
+    SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET)    \
+    SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET)   \
+    SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET)   \
+    SW_API_DESC(SW_API_NESTVLAN_TPID_SET)    \
+    SW_API_DESC(SW_API_NESTVLAN_TPID_GET)    \
+    SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET)    \
+    SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET)    \
+    SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET)    \
+    SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET)    \
+    SW_API_DESC(SW_API_QINQ_MODE_SET)      \
+    SW_API_DESC(SW_API_QINQ_MODE_GET)      \
+    SW_API_DESC(SW_API_PT_QINQ_ROLE_SET)   \
+    SW_API_DESC(SW_API_PT_QINQ_ROLE_GET)
+#else
+#define PORTVLAN_API
+#define PORTVLAN_API_PARAM
+#endif
+
+
+#ifdef IN_FDB
+#define FDB_API \
+    SW_API_DEF(SW_API_FDB_ADD, horus_fdb_add), \
+    SW_API_DEF(SW_API_FDB_DELALL, horus_fdb_del_all), \
+    SW_API_DEF(SW_API_FDB_DELPORT,horus_fdb_del_by_port), \
+    SW_API_DEF(SW_API_FDB_DELMAC, horus_fdb_del_by_mac), \
+    SW_API_DEF(SW_API_FDB_FIRST,  horus_fdb_first), \
+    SW_API_DEF(SW_API_FDB_NEXT,   horus_fdb_next), \
+    SW_API_DEF(SW_API_FDB_FIND,   horus_fdb_find), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_SET,   horus_fdb_port_learn_set), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_GET,   horus_fdb_port_learn_get), \
+    SW_API_DEF(SW_API_FDB_AGE_CTRL_SET,   horus_fdb_age_ctrl_set), \
+    SW_API_DEF(SW_API_FDB_AGE_CTRL_GET,   horus_fdb_age_ctrl_get), \
+    SW_API_DEF(SW_API_FDB_AGE_TIME_SET,   horus_fdb_age_time_set), \
+    SW_API_DEF(SW_API_FDB_AGE_TIME_GET,   horus_fdb_age_time_get),
+
+#define FDB_API_PARAM \
+    SW_API_DESC(SW_API_FDB_ADD)  \
+    SW_API_DESC(SW_API_FDB_DELALL)  \
+    SW_API_DESC(SW_API_FDB_DELPORT) \
+    SW_API_DESC(SW_API_FDB_DELMAC)  \
+    SW_API_DESC(SW_API_FDB_FIRST)   \
+    SW_API_DESC(SW_API_FDB_NEXT)    \
+    SW_API_DESC(SW_API_FDB_FIND)    \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \
+    SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \
+    SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \
+    SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \
+    SW_API_DESC(SW_API_FDB_AGE_TIME_GET)
+#else
+#define FDB_API
+#define FDB_API_PARAM
+#endif
+
+
+#ifdef IN_QOS
+#define QOS_API \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, horus_qos_queue_tx_buf_status_set), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, horus_qos_queue_tx_buf_status_get), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, horus_qos_queue_tx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, horus_qos_queue_tx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, horus_qos_port_tx_buf_status_set), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, horus_qos_port_tx_buf_status_get), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, horus_qos_port_tx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, horus_qos_port_tx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, horus_qos_port_rx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, horus_qos_port_rx_buf_nr_get), \
+    SW_API_DEF(SW_API_COSMAP_UP_QU_SET, horus_cosmap_up_queue_set), \
+    SW_API_DEF(SW_API_COSMAP_UP_QU_GET, horus_cosmap_up_queue_get), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_QU_SET, horus_cosmap_dscp_queue_set), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_QU_GET, horus_cosmap_dscp_queue_get), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_SET, horus_qos_port_mode_set), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_GET, horus_qos_port_mode_get), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, horus_qos_port_mode_pri_set), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, horus_qos_port_mode_pri_get), \
+    SW_API_DEF(SW_API_QOS_PORT_DEF_UP_SET, horus_qos_port_default_up_set), \
+    SW_API_DEF(SW_API_QOS_PORT_DEF_UP_GET, horus_qos_port_default_up_get), \
+    SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, horus_qos_port_sch_mode_set), \
+    SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, horus_qos_port_sch_mode_get),
+
+#define QOS_API_PARAM \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_COSMAP_UP_QU_SET) \
+    SW_API_DESC(SW_API_COSMAP_UP_QU_GET) \
+    SW_API_DESC(SW_API_COSMAP_DSCP_QU_SET) \
+    SW_API_DESC(SW_API_COSMAP_DSCP_QU_GET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_SET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_GET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET)
+#else
+#define QOS_API
+#define QOS_API_PARAM
+#endif
+
+
+#ifdef IN_IGMP
+#define IGMP_API \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, horus_port_igmps_status_set), \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, horus_port_igmps_status_get), \
+    SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, horus_igmp_mld_cmd_set), \
+    SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, horus_igmp_mld_cmd_get), \
+    SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, horus_port_igmp_mld_join_set), \
+    SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, horus_port_igmp_mld_join_get), \
+    SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, horus_port_igmp_mld_leave_set), \
+    SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, horus_port_igmp_mld_leave_get), \
+    SW_API_DEF(SW_API_IGMP_RP_SET, horus_igmp_mld_rp_set), \
+    SW_API_DEF(SW_API_IGMP_RP_GET, horus_igmp_mld_rp_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, horus_igmp_mld_entry_creat_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, horus_igmp_mld_entry_creat_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, horus_igmp_mld_entry_static_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, horus_igmp_mld_entry_static_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, horus_igmp_mld_entry_leaky_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, horus_igmp_mld_entry_leaky_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, horus_igmp_mld_entry_v3_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, horus_igmp_mld_entry_v3_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, horus_igmp_mld_entry_queue_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, horus_igmp_mld_entry_queue_get), \
+ 
+#define IGMP_API_PARAM \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
+    SW_API_DESC(SW_API_IGMP_MLD_CMD_SET)  \
+    SW_API_DESC(SW_API_IGMP_MLD_CMD_GET)  \
+    SW_API_DESC(SW_API_IGMP_PT_JOIN_SET)  \
+    SW_API_DESC(SW_API_IGMP_PT_JOIN_GET)  \
+    SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \
+    SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \
+    SW_API_DESC(SW_API_IGMP_RP_SET)  \
+    SW_API_DESC(SW_API_IGMP_RP_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET)
+#else
+#define IGMP_API
+#define IGMP_API_PARAM
+#endif
+
+
+#ifdef IN_LEAKY
+#define LEAKY_API \
+    SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, horus_uc_leaky_mode_set), \
+    SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, horus_uc_leaky_mode_get), \
+    SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, horus_mc_leaky_mode_set), \
+    SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, horus_mc_leaky_mode_get), \
+    SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, horus_port_arp_leaky_set), \
+    SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, horus_port_arp_leaky_get), \
+    SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, horus_port_uc_leaky_set), \
+    SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, horus_port_uc_leaky_get), \
+    SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, horus_port_mc_leaky_set), \
+    SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, horus_port_mc_leaky_get),
+
+#define LEAKY_API_PARAM \
+    SW_API_DESC(SW_API_UC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_UC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_MC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_MC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \
+    SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \
+    SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET)
+#else
+#define LEAKY_API
+#define LEAKY_API_PARAM
+#endif
+
+
+#ifdef IN_MIRROR
+#define MIRROR_API \
+    SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, horus_mirr_analysis_port_set), \
+    SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, horus_mirr_analysis_port_get), \
+    SW_API_DEF(SW_API_MIRROR_IN_PT_SET, horus_mirr_port_in_set), \
+    SW_API_DEF(SW_API_MIRROR_IN_PT_GET, horus_mirr_port_in_get), \
+    SW_API_DEF(SW_API_MIRROR_EG_PT_SET, horus_mirr_port_eg_set), \
+    SW_API_DEF(SW_API_MIRROR_EG_PT_GET, horus_mirr_port_eg_get),
+
+#define MIRROR_API_PARAM \
+    SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET)  \
+    SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET)  \
+    SW_API_DESC(SW_API_MIRROR_IN_PT_SET)  \
+    SW_API_DESC(SW_API_MIRROR_IN_PT_GET)  \
+    SW_API_DESC(SW_API_MIRROR_EG_PT_SET)  \
+    SW_API_DESC(SW_API_MIRROR_EG_PT_GET)
+#else
+#define MIRROR_API
+#define MIRROR_API_PARAM
+#endif
+
+
+
+#ifdef IN_RATE
+#define RATE_API \
+    SW_API_DEF(SW_API_RATE_PT_EGRL_SET, horus_rate_port_egrl_set), \
+    SW_API_DEF(SW_API_RATE_PT_EGRL_GET, horus_rate_port_egrl_get), \
+    SW_API_DEF(SW_API_RATE_PT_INRL_SET, horus_rate_port_inrl_set), \
+    SW_API_DEF(SW_API_RATE_PT_INRL_GET, horus_rate_port_inrl_get), \
+    SW_API_DEF(SW_API_STORM_CTRL_FRAME_SET, horus_storm_ctrl_frame_set), \
+    SW_API_DEF(SW_API_STORM_CTRL_FRAME_GET, horus_storm_ctrl_frame_get), \
+    SW_API_DEF(SW_API_STORM_CTRL_RATE_SET, horus_storm_ctrl_rate_set), \
+    SW_API_DEF(SW_API_STORM_CTRL_RATE_GET, horus_storm_ctrl_rate_get),
+
+#define RATE_API_PARAM \
+    SW_API_DESC(SW_API_RATE_PT_EGRL_SET) \
+    SW_API_DESC(SW_API_RATE_PT_EGRL_GET) \
+    SW_API_DESC(SW_API_RATE_PT_INRL_SET) \
+    SW_API_DESC(SW_API_RATE_PT_INRL_GET) \
+    SW_API_DESC(SW_API_STORM_CTRL_FRAME_SET) \
+    SW_API_DESC(SW_API_STORM_CTRL_FRAME_GET) \
+    SW_API_DESC(SW_API_STORM_CTRL_RATE_SET)  \
+    SW_API_DESC(SW_API_STORM_CTRL_RATE_GET)
+#else
+#define RATE_API
+#define RATE_API_PARAM
+#endif
+
+
+#ifdef IN_STP
+#define STP_API \
+    SW_API_DEF(SW_API_STP_PT_STATE_SET, horus_stp_port_state_set), \
+    SW_API_DEF(SW_API_STP_PT_STATE_GET, horus_stp_port_state_get),
+
+#define STP_API_PARAM \
+    SW_API_DESC(SW_API_STP_PT_STATE_SET) \
+    SW_API_DESC(SW_API_STP_PT_STATE_GET)
+#else
+#define STP_API
+#define STP_API_PARAM
+#endif
+
+
+#ifdef IN_MIB
+#define MIB_API \
+    SW_API_DEF(SW_API_PT_MIB_GET, horus_get_mib_info), \
+    SW_API_DEF(SW_API_MIB_STATUS_SET, horus_mib_status_set), \
+    SW_API_DEF(SW_API_MIB_STATUS_GET, horus_mib_status_get),
+
+#define MIB_API_PARAM \
+    SW_API_DESC(SW_API_PT_MIB_GET)  \
+    SW_API_DESC(SW_API_MIB_STATUS_SET) \
+    SW_API_DESC(SW_API_MIB_STATUS_GET)
+#else
+#define MIB_API
+#define MIB_API_PARAM
+#endif
+
+
+#ifdef IN_MISC
+#define MISC_API \
+    SW_API_DEF(SW_API_ARP_STATUS_SET, horus_arp_status_set), \
+    SW_API_DEF(SW_API_ARP_STATUS_GET, horus_arp_status_get), \
+    SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, horus_frame_max_size_set), \
+    SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, horus_frame_max_size_get), \
+    SW_API_DEF(SW_API_PT_UNK_SA_CMD_SET, horus_port_unk_sa_cmd_set), \
+    SW_API_DEF(SW_API_PT_UNK_SA_CMD_GET, horus_port_unk_sa_cmd_get), \
+    SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, horus_port_unk_uc_filter_set), \
+    SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, horus_port_unk_uc_filter_get), \
+    SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, horus_port_unk_mc_filter_set), \
+    SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, horus_port_unk_mc_filter_get), \
+    SW_API_DEF(SW_API_PT_BC_FILTER_SET, horus_port_bc_filter_set), \
+    SW_API_DEF(SW_API_PT_BC_FILTER_GET, horus_port_bc_filter_get), \
+    SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, horus_cpu_port_status_set), \
+    SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, horus_cpu_port_status_get), \
+    SW_API_DEF(SW_API_PPPOE_CMD_SET, horus_pppoe_cmd_set), \
+    SW_API_DEF(SW_API_PPPOE_CMD_GET, horus_pppoe_cmd_get), \
+    SW_API_DEF(SW_API_PPPOE_STATUS_SET, horus_pppoe_status_set), \
+    SW_API_DEF(SW_API_PPPOE_STATUS_GET, horus_pppoe_status_get), \
+    SW_API_DEF(SW_API_PT_DHCP_SET, horus_port_dhcp_set), \
+    SW_API_DEF(SW_API_PT_DHCP_GET, horus_port_dhcp_get), \
+    SW_API_DEF(SW_API_ARP_CMD_SET, horus_arp_cmd_set), \
+    SW_API_DEF(SW_API_ARP_CMD_GET, horus_arp_cmd_get), \
+    SW_API_DEF(SW_API_EAPOL_CMD_SET, horus_eapol_cmd_set), \
+    SW_API_DEF(SW_API_EAPOL_CMD_GET, horus_eapol_cmd_get), \
+    SW_API_DEF(SW_API_EAPOL_STATUS_SET, horus_eapol_status_set), \
+    SW_API_DEF(SW_API_EAPOL_STATUS_GET, horus_eapol_status_get), \
+    SW_API_DEF(SW_API_RIPV1_STATUS_SET, horus_ripv1_status_set), \
+    SW_API_DEF(SW_API_RIPV1_STATUS_GET, horus_ripv1_status_get),
+
+#define MISC_API_PARAM \
+    SW_API_DESC(SW_API_ARP_STATUS_SET)  \
+    SW_API_DESC(SW_API_ARP_STATUS_GET)  \
+    SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET)  \
+    SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET)  \
+    SW_API_DESC(SW_API_PT_UNK_SA_CMD_SET)  \
+    SW_API_DESC(SW_API_PT_UNK_SA_CMD_GET)  \
+    SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET)  \
+    SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET)  \
+    SW_API_DESC(SW_API_PT_BC_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_BC_FILTER_GET)  \
+    SW_API_DESC(SW_API_CPU_PORT_STATUS_SET)  \
+    SW_API_DESC(SW_API_CPU_PORT_STATUS_GET)  \
+    SW_API_DESC(SW_API_PPPOE_CMD_SET)  \
+    SW_API_DESC(SW_API_PPPOE_CMD_GET)  \
+    SW_API_DESC(SW_API_PPPOE_STATUS_SET)  \
+    SW_API_DESC(SW_API_PPPOE_STATUS_GET)  \
+    SW_API_DESC(SW_API_PT_DHCP_SET)  \
+    SW_API_DESC(SW_API_PT_DHCP_GET)  \
+    SW_API_DESC(SW_API_ARP_CMD_SET)  \
+    SW_API_DESC(SW_API_ARP_CMD_GET)  \
+    SW_API_DESC(SW_API_EAPOL_CMD_SET) \
+    SW_API_DESC(SW_API_EAPOL_CMD_GET) \
+    SW_API_DESC(SW_API_EAPOL_STATUS_SET)  \
+    SW_API_DESC(SW_API_EAPOL_STATUS_GET)  \
+    SW_API_DESC(SW_API_RIPV1_STATUS_SET)  \
+    SW_API_DESC(SW_API_RIPV1_STATUS_GET)
+#else
+#define MISC_API
+#define MISC_API_PARAM
+#endif
+
+
+#ifdef IN_LED
+#define LED_API \
+    SW_API_DEF(SW_API_LED_PATTERN_SET, horus_led_ctrl_pattern_set), \
+    SW_API_DEF(SW_API_LED_PATTERN_GET, horus_led_ctrl_pattern_get),
+
+#define LED_API_PARAM \
+    SW_API_DESC(SW_API_LED_PATTERN_SET) \
+    SW_API_DESC(SW_API_LED_PATTERN_GET)
+#else
+#define LED_API
+#define LED_API_PARAM
+#endif
+
+
+#define REG_API \
+    SW_API_DEF(SW_API_PHY_GET, horus_phy_get), \
+    SW_API_DEF(SW_API_PHY_SET, horus_phy_set), \
+    SW_API_DEF(SW_API_REG_GET, horus_reg_get), \
+    SW_API_DEF(SW_API_REG_SET, horus_reg_set), \
+    SW_API_DEF(SW_API_REG_FIELD_GET, horus_reg_field_get), \
+    SW_API_DEF(SW_API_REG_FIELD_SET, horus_reg_field_set),
+
+#define REG_API_PARAM \
+    SW_API_DESC(SW_API_PHY_GET) \
+    SW_API_DESC(SW_API_PHY_SET) \
+    SW_API_DESC(SW_API_REG_GET) \
+    SW_API_DESC(SW_API_REG_SET) \
+    SW_API_DESC(SW_API_REG_FIELD_GET) \
+    SW_API_DESC(SW_API_REG_FIELD_SET)
+
+
+#define SSDK_API \
+    SW_API_DEF(SW_API_SWITCH_RESET, horus_reset), \
+    SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \
+    PORTCONTROL_API \
+    VLAN_API \
+    PORTVLAN_API \
+    FDB_API    \
+    QOS_API    \
+    IGMP_API   \
+    LEAKY_API  \
+    MIRROR_API \
+    RATE_API \
+    STP_API  \
+    MIB_API  \
+    MISC_API \
+    LED_API  \
+    REG_API  \
+    SW_API_DEF(SW_API_MAX, NULL),
+
+
+#define SSDK_PARAM  \
+    SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
+    MIB_API_PARAM    \
+    LEAKY_API_PARAM  \
+    MISC_API_PARAM   \
+    IGMP_API_PARAM   \
+    MIRROR_API_PARAM \
+    PORTCONTROL_API_PARAM \
+    PORTVLAN_API_PARAM    \
+    VLAN_API_PARAM \
+    FDB_API_PARAM  \
+    QOS_API_PARAM  \
+    RATE_API_PARAM \
+    STP_API_PARAM  \
+    LED_API_PARAM  \
+    REG_API_PARAM  \
+    SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+
+#if (defined(USER_MODE) && defined(KERNEL_MODULE))
+#undef SSDK_API
+#undef SSDK_PARAM
+
+#define SSDK_API \
+    REG_API \
+    SW_API_DEF(SW_API_MAX, NULL),
+
+#define SSDK_PARAM  \
+    REG_API_PARAM \
+    SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _HORUS_API_H_ */
diff --git a/qca-ssdk/include/hsl/horus/horus_fdb.h b/qca-ssdk/include/hsl/horus/horus_fdb.h
new file mode 100755
index 0000000..3097bab
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_fdb.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_fdb HORUS_FDB
+ * @{
+ */
+#ifndef _HORUS_FDB_H_
+#define _HORUS_FDB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_fdb.h"
+
+    sw_error_t
+    horus_fdb_init(a_uint32_t dev_id);
+
+#ifdef IN_FDB
+#define HORUS_FDB_INIT(rv, dev_id) \
+    { \
+        rv = horus_fdb_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define HORUS_FDB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    horus_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+
+    HSL_LOCAL sw_error_t
+    horus_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag);
+
+
+    HSL_LOCAL sw_error_t
+    horus_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag);
+
+
+    HSL_LOCAL sw_error_t
+    horus_fdb_del_by_mac(a_uint32_t dev_id,
+                         const fal_fdb_entry_t *entry);
+
+
+    HSL_LOCAL sw_error_t
+    horus_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+    HSL_LOCAL sw_error_t
+    horus_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+    HSL_LOCAL sw_error_t
+    horus_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+    HSL_LOCAL sw_error_t
+    horus_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+
+    HSL_LOCAL sw_error_t
+    horus_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HORUS_FDB_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/horus/horus_igmp.h b/qca-ssdk/include/hsl/horus/horus_igmp.h
new file mode 100755
index 0000000..e17b67a
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_igmp.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_igmp HORUS_IGMP
+ * @{
+ */
+#ifndef _HORUS_IGMP_H_
+#define _HORUS_IGMP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_igmp.h"
+
+    sw_error_t
+    horus_igmp_init(a_uint32_t dev_id);
+
+#ifdef IN_IGMP
+#define HORUS_IGMP_INIT(rv, dev_id) \
+    { \
+        rv = horus_igmp_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define HORUS_IGMP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    horus_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    horus_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts);
+
+
+    HSL_LOCAL sw_error_t
+    horus_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts);
+
+
+    HSL_LOCAL sw_error_t
+    horus_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue);
+
+
+    HSL_LOCAL sw_error_t
+    horus_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _HORUS_IGMP_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/horus/horus_init.h b/qca-ssdk/include/hsl/horus/horus_init.h
new file mode 100755
index 0000000..3888764
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_init.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_init HORUS_INIT
+ * @{
+ */
+#ifndef _HORUS_INIT_H_
+#define _HORUS_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+
+    sw_error_t
+    horus_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+
+    sw_error_t
+    horus_reset(a_uint32_t dev_id);
+
+
+    sw_error_t
+    horus_cleanup(a_uint32_t dev_id);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HORUS_INIT_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/horus/horus_leaky.h b/qca-ssdk/include/hsl/horus/horus_leaky.h
new file mode 100755
index 0000000..eb66999
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_leaky.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_leaky HORUS_LEAKY
+ * @{
+ */
+#ifndef _HORUS_LEAKY_H_
+#define _HORUS_LEAKY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_leaky.h"
+
+    sw_error_t horus_leaky_init(a_uint32_t dev_id);
+
+#ifdef IN_LEAKY
+#define HORUS_LEAKY_INIT(rv, dev_id) \
+    { \
+        rv = horus_leaky_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define HORUS_LEAKY_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    horus_uc_leaky_mode_set(a_uint32_t dev_id,
+                            fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    horus_uc_leaky_mode_get(a_uint32_t dev_id,
+                            fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    horus_mc_leaky_mode_set(a_uint32_t dev_id,
+                            fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    horus_mc_leaky_mode_get(a_uint32_t dev_id,
+                            fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _HORUS_LEAKY_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/horus/horus_led.h b/qca-ssdk/include/hsl/horus/horus_led.h
new file mode 100755
index 0000000..c7d8a92
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_led.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _HORUS_LED_H_
+#define _HORUS_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_led.h"
+
+    sw_error_t
+    horus_led_init(a_uint32_t dev_id);
+
+#ifdef IN_LED
+#define HORUS_LED_INIT(rv, dev_id) \
+    { \
+        rv = horus_led_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define HORUS_LED_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    horus_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                               led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+
+    HSL_LOCAL sw_error_t
+    horus_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                               led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HORUS_LED_H_ */
diff --git a/qca-ssdk/include/hsl/horus/horus_mib.h b/qca-ssdk/include/hsl/horus/horus_mib.h
new file mode 100755
index 0000000..6f1963e
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_mib.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_mib HORUS_MIB
+ * @{
+ */
+#ifndef _HORUS_MIB_H_
+#define _HORUS_MIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mib.h"
+
+    sw_error_t
+    horus_mib_init(a_uint32_t dev_id);
+
+#ifdef IN_MIB
+#define HORUS_MIB_INIT(rv, dev_id) \
+    { \
+        rv = horus_mib_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define HORUS_MIB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    horus_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_mib_info_t * mib_info );
+
+
+    HSL_LOCAL sw_error_t
+    horus_mib_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_mib_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HORUS_MIB_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/horus/horus_mirror.h b/qca-ssdk/include/hsl/horus/horus_mirror.h
new file mode 100755
index 0000000..ae51f7e
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_mirror.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_mirror HORUS_MIRROR
+ * @{
+ */
+#ifndef _HORUS_MIRROR_H_
+#define _HORUS_MIRROR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_mirror.h"
+
+    sw_error_t horus_mirr_init(a_uint32_t dev_id);
+
+#ifdef IN_MIRROR
+#define HORUS_MIRR_INIT(rv, dev_id) \
+    { \
+        rv = horus_mirr_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define HORUS_MIRR_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    horus_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    horus_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id);
+
+
+    HSL_LOCAL sw_error_t
+    horus_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _HORUS_MIRROR_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/horus/horus_misc.h b/qca-ssdk/include/hsl/horus/horus_misc.h
new file mode 100755
index 0000000..5572444
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_misc.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_misc HORUS_MISC
+ * @{
+ */
+#ifndef _HORUS_MISC_H_
+#define _HORUS_MISC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_misc.h"
+
+    sw_error_t horus_misc_init(a_uint32_t dev_id);
+
+#ifdef IN_MISC
+#define HORUS_MISC_INIT(rv, dev_id) \
+    { \
+        rv = horus_misc_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define HORUS_MISC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    horus_arp_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_arp_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size);
+
+
+    HSL_LOCAL sw_error_t
+    horus_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    horus_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    horus_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    horus_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    horus_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    horus_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    horus_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    horus_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    horus_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    horus_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _HORUS_GEN_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/horus/horus_port_ctrl.h b/qca-ssdk/include/hsl/horus/horus_port_ctrl.h
new file mode 100755
index 0000000..580f49e
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_port_ctrl.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_port_ctrl HORUS_PORT_CONTROL
+ * @{
+ */
+#ifndef _HORUS_PORT_CTRL_H_
+#define _HORUS_PORT_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_port_ctrl.h"
+
+    sw_error_t horus_port_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTCONTROL
+#define HORUS_PORT_CTRL_INIT(rv, dev_id) \
+    { \
+        rv = horus_port_ctrl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define HORUS_PORT_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_duplex_t duplex);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_duplex_t * pduplex);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_speed_t speed);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_speed_t * pspeed);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * status);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t autoadv);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * autoadv);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_flowctrl_forcemode_set(a_uint32_t dev_id,
+                                      fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_flowctrl_forcemode_get(a_uint32_t dev_id,
+                                      fal_port_t port_id,
+                                      a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    horus_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+                   fal_cable_status_t *cable_status, a_uint32_t *cable_len);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _HORUS_PORT_CTRL_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/horus/horus_portvlan.h b/qca-ssdk/include/hsl/horus/horus_portvlan.h
new file mode 100755
index 0000000..d1237f9
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_portvlan.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+ * @defgroup horus_port_vlan HORUS_PORT_VLAN
+ * @{
+ */
+#ifndef _HORUS_PORTVLAN_H_
+#define _HORUS_PORTVLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_portvlan.h"
+
+    sw_error_t horus_portvlan_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTVLAN
+#define HORUS_PORTVLAN_INIT(rv, dev_id) \
+    { \
+        rv = horus_portvlan_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define HORUS_PORTVLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_1qmode_t port_1qmode);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_1qmode_t * pport_1qmode);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pt_1q_egmode_t port_egvlanmode);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pt_1q_egmode_t * pport_egvlanmode);
+
+
+    HSL_LOCAL sw_error_t
+    horus_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t mem_port_id);
+
+
+    HSL_LOCAL sw_error_t
+    horus_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t mem_port_id);
+
+
+    HSL_LOCAL sw_error_t
+    horus_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_pbmp_t mem_port_map);
+
+
+    HSL_LOCAL sw_error_t
+    horus_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pbmp_t * mem_port_map);
+
+    HSL_LOCAL sw_error_t
+    horus_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid);
+
+    HSL_LOCAL sw_error_t
+    horus_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid);
+
+    HSL_LOCAL sw_error_t
+    horus_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid);
+
+
+    HSL_LOCAL sw_error_t
+    horus_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_pt_invlan_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_pt_invlan_mode_t * mode);
+
+    HSL_LOCAL sw_error_t
+    horus_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    horus_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role);
+
+
+    HSL_LOCAL sw_error_t
+    horus_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role);
+
+
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ATHENA_PORTVLAN_H */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/horus/horus_qos.h b/qca-ssdk/include/hsl/horus/horus_qos.h
new file mode 100755
index 0000000..f3cf75d
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_qos.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_qos HORUS_QOS
+ * @{
+ */
+#ifndef _HORUS_QOS_H_
+#define _HORUS_QOS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_qos.h"
+
+    sw_error_t horus_qos_init(a_uint32_t dev_id);
+
+#ifdef IN_QOS
+#define HORUS_QOS_INIT(rv, dev_id) \
+    { \
+        rv = horus_qos_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define HORUS_QOS_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_queue_tx_buf_status_set(a_uint32_t dev_id,
+                                      fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_queue_tx_buf_status_get(a_uint32_t dev_id,
+                                      fal_port_t port_id,
+                                      a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    horus_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_queue_t queue_id,
+                                  a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_queue_t queue_id,
+                                  a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    horus_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+                              fal_queue_t queue);
+
+
+    HSL_LOCAL sw_error_t
+    horus_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+                              fal_queue_t * queue);
+
+
+    HSL_LOCAL sw_error_t
+    horus_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+                                fal_queue_t queue);
+
+
+    HSL_LOCAL sw_error_t
+    horus_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+                                fal_queue_t * queue);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_qos_mode_t mode, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_qos_mode_t mode, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_qos_mode_t mode, a_uint32_t pri);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_qos_mode_t mode, a_uint32_t * pri);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t up);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t * up);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                                fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+
+    HSL_LOCAL sw_error_t
+    horus_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                                fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _HORUS_QOS_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/horus/horus_rate.h b/qca-ssdk/include/hsl/horus/horus_rate.h
new file mode 100755
index 0000000..84b04d7
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_rate.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_rate HORUS_RATE
+ * @{
+ */
+#ifndef _HORUS_RATE_H_
+#define _HORUS_RATE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_rate.h"
+
+    sw_error_t horus_rate_init(a_uint32_t dev_id);
+
+#ifdef IN_RATE
+#define HORUS_RATE_INIT(rv, dev_id) \
+    { \
+        rv = horus_rate_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define HORUS_RATE_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    horus_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * speed, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * speed, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * speed, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * speed, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_storm_type_t storm_type, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_storm_type_t storm_type, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    horus_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * rate_in_pps);
+
+
+    HSL_LOCAL sw_error_t
+    horus_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * rate_in_pps);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _HORUS_RATE_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/horus/horus_reg.h b/qca-ssdk/include/hsl/horus/horus_reg.h
new file mode 100755
index 0000000..891e2c4
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_reg.h
@@ -0,0 +1,2431 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HORUS_REG_H_
+#define _HORUS_REG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#define MAX_ENTRY_LEN 128
+
+#define HSL_RW 1
+#define HSL_RO 0
+
+
+    /* Garuda Mask Control Register */
+#define MASK_CTL                  "mask"
+#define MASK_CTL_ID               0
+#define MASK_CTL_OFFSET           0x0000
+#define MASK_CTL_E_LENGTH         4
+#define MASK_CTL_E_OFFSET         0
+#define MASK_CTL_NR_E             1
+
+#define SOFT_RST                              "mask_rst"
+#define MASK_CTL_SOFT_RST_BOFFSET             31
+#define MASK_CTL_SOFT_RST_BLEN                1
+#define MASK_CTL_SOFT_RST_FLAG                HSL_RW
+
+#define MII_CLK5_SEL                          "mask_clk5s"
+#define MASK_CTL_MII_CLK5_SEL_BOFFSET         21
+#define MASK_CTL_MII_CLK5_SEL_BLEN            1
+#define MASK_CTL_MII_CLK5_SEL_FLAG            HSL_RW
+
+#define MII_CLK0_SEL                          "mask_clk0s"
+#define MASK_CTL_MII_CLK0_SEL_BOFFSET         20
+#define MASK_CTL_MII_CLK0_SEL_BLEN            1
+#define MASK_CTL_MII_CLK0_SEL_FLAG            HSL_RW
+
+#define LOAD_EEPROM                           "mask_ldro"
+#define MASK_CTL_LOAD_EEPROM_BOFFSET          16
+#define MASK_CTL_LOAD_EEPROM_BLEN             1
+#define MASK_CTL_LOAD_EEPROM_FLAG             HSL_RW
+
+#define DEVICE_ID                             "mask_did"
+#define MASK_CTL_DEVICE_ID_BOFFSET            8
+#define MASK_CTL_DEVICE_ID_BLEN               8
+#define MASK_CTL_DEVICE_ID_FLAG               HSL_RO
+
+#define REV_ID                                "mask_rid"
+#define MASK_CTL_REV_ID_BOFFSET               0
+#define MASK_CTL_REV_ID_BLEN                  8
+#define MASK_CTL_REV_ID_FLAG                  HSL_RO
+
+
+    /* Garuda Mask Control Register */
+#define POSTRIP                  "postrip"
+#define POSTRIP_ID               0
+#define POSTRIP_OFFSET           0x0008
+#define POSTRIP_E_LENGTH         4
+#define POSTRIP_E_OFFSET         0
+#define POSTRIP_NR_E             1
+
+#define POWER_ON_SEL                           "postrip_sel"
+#define POSTRIP_POWER_ON_SEL_BOFFSET           31
+#define POSTRIP_POWER_ON_SEL_BLEN              1
+#define POSTRIP_POWER_ON_SEL_FLAG              HSL_RW
+
+#define RXDELAY_S1                             "postrip_rx_s1"
+#define POSTRIP_RXDELAY_S1_BOFFSET             26
+#define POSTRIP_RXDELAY_S1_BLEN                1
+#define POSTRIP_RXDELAY_S1_FLAG                HSL_RW
+
+#define SPI_EN                                 "postrip_spi"
+#define POSTRIP_SPI_EN_BOFFSET                 25
+#define POSTRIP_SPI_EN_BLEN                    1
+#define POSTRIP_SPI_EN_FLAG                    HSL_RW
+
+#define LED_OPEN_EN                            "postrip_led"
+#define POSTRIP_LED_OPEN_EN_BOFFSET            24
+#define POSTRIP_LED_OPEN_EN_BLEN               1
+#define POSTRIP_LED_OPEN_EN_FLAG               HSL_RW
+
+#define RXDELAY_S0                             "postrip_rx_s0"
+#define POSTRIP_RXDELAY_S0_BOFFSET             23
+#define POSTRIP_RXDELAY_S0_BLEN                1
+#define POSTRIP_RXDELAY_S0_FLAG                HSL_RW
+
+#define TXDELAY_S1                             "postrip_tx_s1"
+#define POSTRIP_TXDELAY_S1_BOFFSET             22
+#define POSTRIP_TXDELAY_S1_BLEN                1
+#define POSTRIP_TXDELAY_S1_FLAG                HSL_RW
+
+#define TXDELAY_S0                             "postrip_tx_s0"
+#define POSTRIP_TXDELAY_S0_BOFFSET             21
+#define POSTRIP_TXDELAY_S0_BLEN                1
+#define POSTRIP_TXDELAY_S0_FLAG                HSL_RW
+
+#define LPW_EXIT                               "postrip_lpw_exit"
+#define POSTRIP_LPW_EXIT_BOFFSET               20
+#define POSTRIP_LPW_EXIT_BLEN                  1
+#define POSTRIP_LPW_EXIT_FLAG                  HSL_RW
+
+#define PHY_PLL_ON                             "postrip_phy_pll"
+#define POSTRIP_PHY_PLL_ON_BOFFSET             19
+#define POSTRIP_PHY_PLL_ON_BLEN                1
+#define POSTRIP_PHY_PLL_ON_FLAG                HSL_RW
+
+#define MAN_ENABLE                             "postrip_man_en"
+#define POSTRIP_MAN_ENABLE_BOFFSET             18
+#define POSTRIP_MAN_ENABLE_BLEN                1
+#define POSTRIP_MAN_ENABLE_FLAG                HSL_RW
+
+#define LPW_STATE_EN                           "postrip_lpw_state"
+#define POSTRIP_LPW_STATE_EN_BOFFSET           17
+#define POSTRIP_LPW_STATE_EN_BLEN              1
+#define POSTRIP_LPW_STATE_EN_FLAG              HSL_RW
+
+#define POWER_DOWN_HW                          "postrip_power_down"
+#define POSTRIP_POWER_DOWN_HW_BOFFSET          16
+#define POSTRIP_POWER_DOWN_HW_BLEN             1
+#define POSTRIP_POWER_DOWN_HW_FLAG             HSL_RW
+
+#define MAC5_PHY_MODE                          "postrip_mac5_phy"
+#define POSTRIP_MAC5_PHY_MODE_BOFFSET          15
+#define POSTRIP_MAC5_PHY_MODE_BLEN             1
+#define POSTRIP_MAC5_PHY_MODE_FLAG             HSL_RW
+
+#define MAC5_MAC_MODE                          "postrip_mac5_mac"
+#define POSTRIP_MAC5_MAC_MODE_BOFFSET          14
+#define POSTRIP_MAC5_MAC_MODE_BLEN             1
+#define POSTRIP_MAC5_MAC_MODE_FLAG             HSL_RW
+
+#define DBG_MODE_I                             "postrip_dbg"
+#define POSTRIP_DBG_MODE_I_BOFFSET             13
+#define POSTRIP_DBG_MODE_I_BLEN                1
+#define POSTRIP_DBG_MODE_I_FLAG                HSL_RW
+
+#define HIB_PULSE_HW                           "postrip_hib"
+#define POSTRIP_HIB_PULSE_HW_BOFFSET           12
+#define POSTRIP_HIB_PULSE_HW_BLEN              1
+#define POSTRIP_HIB_PULSE_HW_FLAG              HSL_RW
+
+#define SEL_CLK25M                             "postrip_clk25"
+#define POSTRIP_SEL_CLK25M_BOFFSET             11
+#define POSTRIP_SEL_CLK25M_BLEN                1
+#define POSTRIP_SEL_CLK25M_FLAG                HSL_RW
+
+#define GATE_25M_EN                            "postrip_gate25"
+#define POSTRIP_GATE_25M_EN_BOFFSET            10
+#define POSTRIP_GATE_25M_EN_BLEN               1
+#define POSTRIP_GATE_25M_EN_FLAG               HSL_RW
+
+#define SEL_ANA_RST                            "postrip_sel_ana"
+#define POSTRIP_SEL_ANA_RST_BOFFSET            9
+#define POSTRIP_SEL_ANA_RST_BLEN               1
+#define POSTRIP_SEL_ANA_RST_FLAG               HSL_RW
+
+#define SERDES_EN                              "postrip_serdes_en"
+#define POSTRIP_SERDES_EN_BOFFSET              8
+#define POSTRIP_SERDES_EN_BLEN                 1
+#define POSTRIP_SERDES_EN_FLAG                 HSL_RW
+
+#define RGMII_TXCLK_DELAY_EN                   "postrip_tx_delay"
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_BOFFSET   7
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_BLEN      1
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_FLAG      HSL_RW
+
+#define RGMII_RXCLK_DELAY_EN                   "postrip_rx_delay"
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_BOFFSET   6
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_BLEN      1
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_FLAG      HSL_RW
+
+#define RTL_MODE                               "postrip_rtl"
+#define POSTRIP_RTL_MODE_BOFFSET               5
+#define POSTRIP_RTL_MODE_BLEN                  1
+#define POSTRIP_RTL_MODE_FLAG                  HSL_RW
+
+#define MAC0_MAC_MODE                          "postrip_mac0_mac"
+#define POSTRIP_MAC0_MAC_MODE_BOFFSET          4
+#define POSTRIP_MAC0_MAC_MODE_BLEN             1
+#define POSTRIP_MAC0_MAC_MODE_FLAG             HSL_RW
+
+#define PHY4_RGMII_EN                          "postrip_phy4_rgmii"
+#define POSTRIP_PHY4_RGMII_EN_BOFFSET          3
+#define POSTRIP_PHY4_RGMII_EN_BLEN             1
+#define POSTRIP_PHY4_RGMII_EN_FLAG             HSL_RW
+
+#define PHY4_GMII_EN                           "postrip_phy4_gmii"
+#define POSTRIP_PHY4_GMII_EN_BOFFSET           2
+#define POSTRIP_PHY4_GMII_EN_BLEN              1
+#define POSTRIP_PHY4_GMII_EN_FLAG              HSL_RW
+
+#define MAC0_RGMII_EN                          "postrip_mac0_rgmii"
+#define POSTRIP_MAC0_RGMII_EN_BOFFSET          1
+#define POSTRIP_MAC0_RGMII_EN_BLEN             1
+#define POSTRIP_MAC0_RGMII_EN_FLAG             HSL_RW
+
+#define MAC0_GMII_EN                           "postrip_mac0_gmii"
+#define POSTRIP_MAC0_GMII_EN_BOFFSET           0
+#define POSTRIP_MAC0_GMII_EN_BLEN              1
+#define POSTRIP_MAC0_GMII_EN_FLAG              HSL_RW
+
+
+
+    /* Global Interrupt Register */
+#define GLOBAL_INT                "gint"
+#define GLOBAL_INT_ID             1
+#define GLOBAL_INT_OFFSET         0x0014
+#define GLOBAL_INT_E_LENGTH       4
+#define GLOBAL_INT_E_OFFSET       0
+#define GLOBAL_INT_NR_E           1
+
+#define GLB_QM_ERR_CNT                            "gint_qmen"
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BOFFSET         24
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BLEN            8
+#define GLOBAL_INT_GLB_QM_ERR_CNT_FLAG            HSL_RO
+
+#define GLB_LOOKUP_ERR                            "gint_glblper"
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BOFFSET         17
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BLEN            1
+#define GLOBAL_INT_GLB_LOOKUP_ERR_FLAG            HSL_RW
+
+#define GLB_QM_ERR                                "gint_glbqmer"
+#define GLOBAL_INT_GLB_QM_ERR_BOFFSET             16
+#define GLOBAL_INT_GLB_QM_ERR_BLEN                1
+#define GLOBAL_INT_GLB_QM_ERR_FLAG                HSL_RW
+
+#define GLB_HW_INI_DONE                           "gint_hwid"
+#define GLOBAL_INT_GLB_HW_INI_DONE_BOFFSET        14
+#define GLOBAL_INT_GLB_HW_INI_DONE_BLEN           1
+#define GLOBAL_INT_GLB_HW_INI_DONE_FLAG           HSL_RW
+
+#define GLB_MIB_INI                               "gint_mibi"
+#define GLOBAL_INT_GLB_MIB_INI_BOFFSET            13
+#define GLOBAL_INT_GLB_MIB_INI_BLEN               1
+#define GLOBAL_INT_GLB_MIB_INI_FLAG               HSL_RW
+
+#define GLB_MIB_DONE                              "gint_mibd"
+#define GLOBAL_INT_GLB_MIB_DONE_BOFFSET           12
+#define GLOBAL_INT_GLB_MIB_DONE_BLEN              1
+#define GLOBAL_INT_GLB_MIB_DONE_FLAG              HSL_RW
+
+#define GLB_BIST_DONE                             "gint_bisd"
+#define GLOBAL_INT_GLB_BIST_DONE_BOFFSET          11
+#define GLOBAL_INT_GLB_BIST_DONE_BLEN             1
+#define GLOBAL_INT_GLB_BIST_DONE_FLAG             HSL_RW
+
+#define GLB_VT_MISS_VIO                           "gint_vtms"
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BOFFSET        10
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BLEN           1
+#define GLOBAL_INT_GLB_VT_MISS_VIO_FLAG           HSL_RW
+
+#define GLB_VT_MEM_VIO                            "gint_vtme"
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BOFFSET         9
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BLEN            1
+#define GLOBAL_INT_GLB_VT_MEM_VIO_FLAG            HSL_RW
+
+#define GLB_VT_DONE                               "gint_vtd"
+#define GLOBAL_INT_GLB_VT_DONE_BOFFSET            8
+#define GLOBAL_INT_GLB_VT_DONE_BLEN               1
+#define GLOBAL_INT_GLB_VT_DONE_FLAG               HSL_RW
+
+#define GLB_QM_INI                                "gint_qmin"
+#define GLOBAL_INT_GLB_QM_INI_BOFFSET             7
+#define GLOBAL_INT_GLB_QM_INI_BLEN                1
+#define GLOBAL_INT_GLB_QM_INI_FLAG                HSL_RW
+
+#define GLB_AT_INI                                "gint_atin"
+#define GLOBAL_INT_GLB_AT_INI_BOFFSET             6
+#define GLOBAL_INT_GLB_AT_INI_BLEN                1
+#define GLOBAL_INT_GLB_AT_INI_FLAG                HSL_RW
+
+#define GLB_ARL_FULL                              "gint_arlf"
+#define GLOBAL_INT_GLB_ARL_FULL_BOFFSET           5
+#define GLOBAL_INT_GLB_ARL_FULL_BLEN              1
+#define GLOBAL_INT_GLB_ARL_FULL_FLAG              HSL_RW
+
+#define GLB_ARL_DONE                              "gint_arld"
+#define GLOBAL_INT_GLB_ARL_DONE_BOFFSET           4
+#define GLOBAL_INT_GLB_ARL_DONE_BLEN              1
+#define GLOBAL_INT_GLB_ARL_DONE_FLAG              HSL_RW
+
+#define GLB_MDIO_DONE                             "gint_mdid"
+#define GLOBAL_INT_GLB_MDIO_DONE_BOFFSET          3
+#define GLOBAL_INT_GLB_MDIO_DONE_BLEN             1
+#define GLOBAL_INT_GLB_MDIO_DONE_FLAG             HSL_RW
+
+#define GLB_PHY_INT                               "gint_phyi"
+#define GLOBAL_INT_GLB_PHY_INT_BOFFSET            2
+#define GLOBAL_INT_GLB_PHY_INT_BLEN               1
+#define GLOBAL_INT_GLB_PHY_INT_FLAG               HSL_RW
+
+#define GLB_EEPROM_ERR                            "gint_epei"
+#define GLOBAL_INT_GLB_EEPROM_ERR_BOFFSET         1
+#define GLOBAL_INT_GLB_EEPROM_ERR_BLEN            1
+#define GLOBAL_INT_GLB_EEPROM_ERR_FLAG            HSL_RW
+
+#define GLB_EEPROM_INT                            "gint_epi"
+#define GLOBAL_INT_GLB_EEPROM_INT_BOFFSET         0
+#define GLOBAL_INT_GLB_EEPROM_INT_BLEN            1
+#define GLOBAL_INT_GLB_EEPROM_INT_FLAG            HSL_RW
+
+
+    /* Global Interrupt Mask Register */
+#define GLOBAL_INT_MASK           "gintm"
+#define GLOBAL_INT_MASK_ID        2
+#define GLOBAL_INT_MASK_OFFSET    0x0018
+#define GLOBAL_INT_MASK_E_LENGTH  4
+#define GLOBAL_INT_MASK_E_OFFSET  0
+#define GLOBAL_INT_MASK_NR_E      1
+
+#define GLBM_LOOKUP_ERR                          "gintm_lpe"
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BOFFSET  17
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BLEN     1
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_FLAG     HSL_RW
+
+#define GLBM_QM_ERR                                "gintm_qme"
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BOFFSET        16
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BLEN           1
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_FLAG           HSL_RW
+
+#define GLBM_HW_INI_DONE                           "gintm_hwid"
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BOFFSET   14
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BLEN      1
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_FLAG      HSL_RW
+
+#define GLBM_MIB_INI                               "gintm_mibi"
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BOFFSET       13
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BLEN          1
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_FLAG          HSL_RW
+
+#define GLBM_MIB_DONE                              "gintm_mibd"
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BOFFSET      12
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BLEN         1
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_FLAG         HSL_RW
+
+#define GLBM_BIST_DONE                             "gintm_bisd"
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BOFFSET     11
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BLEN        1
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_FLAG        HSL_RW
+
+#define GLBM_VT_MISS_VIO                           "gintm_vtms"
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BOFFSET   10
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BLEN      1
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_FLAG      HSL_RW
+
+#define GLBM_VT_MEM_VIO                            "gintm_vtme"
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BOFFSET    9
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BLEN       1
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_FLAG       HSL_RW
+
+#define GLBM_VT_DONE                               "gintm_vtd"
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BOFFSET       8
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BLEN          1
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_FLAG          HSL_RW
+
+#define GLBM_QM_INI                                "gintm_qmin"
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BOFFSET        7
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BLEN           1
+#define GLOBAL_INT_MASK_GLBM_QM_INI_FLAG           HSL_RW
+
+#define GLBM_AT_INI                                "gintm_atin"
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BOFFSET        6
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BLEN           1
+#define GLOBAL_INT_MASK_GLBM_AT_INI_FLAG           HSL_RW
+
+#define GLBM_ARL_FULL                              "gintm_arlf"
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BOFFSET      5
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BLEN         1
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_FLAG         HSL_RW
+
+#define GLBM_ARL_DONE                              "gintm_arld"
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BOFFSET      4
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BLEN         1
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_FLAG         HSL_RW
+
+#define GLBM_MDIO_DONE                             "gintm_mdid"
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BOFFSET     3
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BLEN        1
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_FLAG        HSL_RW
+
+#define GLBM_PHY_INT                               "gintm_phy"
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BOFFSET       2
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BLEN          1
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_FLAG          HSL_RW
+
+#define GLBM_EEPROM_ERR                            "gintm_epe"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BOFFSET    1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BLEN       1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_FLAG       HSL_RW
+
+#define GLBM_EEPROM_INT                            "gintm_ep"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BOFFSET    0
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BLEN       1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_FLAG       HSL_RW
+
+
+    /* Global MAC Address Register */
+#define GLOBAL_MAC_ADDR0           "gmac0"
+#define GLOBAL_MAC_ADDR0_ID        3
+#define GLOBAL_MAC_ADDR0_OFFSET    0x0020
+#define GLOBAL_MAC_ADDR0_E_LENGTH  4
+#define GLOBAL_MAC_ADDR0_E_OFFSET  0
+#define GLOBAL_MAC_ADDR0_NR_E      1
+
+#define GLB_BYTE4                                  "gmac_b4"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET         8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN            8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG            HSL_RW
+
+#define GLB_BYTE5                                  "gmac_b5"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET         0
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN            8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG            HSL_RW
+
+#define GLOBAL_MAC_ADDR1           "gmac1"
+#define GLOBAL_MAC_ADDR1_ID        4
+#define GLOBAL_MAC_ADDR1_OFFSET    0x0024
+#define GLOBAL_MAC_ADDR1_E_LENGTH  4
+#define GLOBAL_MAC_ADDR1_E_OFFSET  0
+#define GLOBAL_MAC_ADDR1_NR_E      1
+
+#define GLB_BYTE0                                  "gmac_b0"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET         24
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG            HSL_RW
+
+#define GLB_BYTE1                                  "gmac_b1"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET         16
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG            HSL_RW
+
+#define GLB_BYTE2                                  "gmac_b2"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET         8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG            HSL_RW
+
+#define GLB_BYTE3                                  "gmac_b3"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET         0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG            HSL_RW
+
+
+    /* Flood Mask Register */
+#define FLOOD_MASK                "fmask"
+#define FLOOD_MASK_ID             5
+#define FLOOD_MASK_OFFSET         0x002c
+#define FLOOD_MASK_E_LENGTH       4
+#define FLOOD_MASK_E_OFFSET       0
+#define FLOOD_MASK_NR_E           1
+
+#define BC_FLOOD_DP                         "fmask_bfdp"
+#define FLOOD_MASK_BC_FLOOD_DP_BOFFSET      25
+#define FLOOD_MASK_BC_FLOOD_DP_BLEN         6
+#define FLOOD_MASK_BC_FLOOD_DP_FLAG         HSL_RW
+
+#define ARL_UNI_LEAKY                       "fmask_aulky"
+#define FLOOD_MASK_ARL_UNI_LEAKY_BOFFSET    24
+#define FLOOD_MASK_ARL_UNI_LEAKY_BLEN       1
+#define FLOOD_MASK_ARL_UNI_LEAKY_FLAG       HSL_RW
+
+#define ARL_MUL_LEAKY                       "fmask_amlky"
+#define FLOOD_MASK_ARL_MUL_LEAKY_BOFFSET    23
+#define FLOOD_MASK_ARL_MUL_LEAKY_BLEN       1
+#define FLOOD_MASK_ARL_MUL_LEAKY_FLAG       HSL_RW
+
+#define MUL_FLOOD_DP                        "fmask_mfdp"
+#define FLOOD_MASK_MUL_FLOOD_DP_BOFFSET     16
+#define FLOOD_MASK_MUL_FLOOD_DP_BLEN        6
+#define FLOOD_MASK_MUL_FLOOD_DP_FLAG        HSL_RW
+
+#define IGMP_DP                             "fmask_igmpdp"
+#define FLOOD_MASK_IGMP_DP_BOFFSET          8
+#define FLOOD_MASK_IGMP_DP_BLEN             6
+#define FLOOD_MASK_IGMP_DP_FLAG             HSL_RW
+
+#define UNI_FLOOD_DP                        "fmask_ufdp"
+#define FLOOD_MASK_UNI_FLOOD_DP_BOFFSET     0
+#define FLOOD_MASK_UNI_FLOOD_DP_BLEN        6
+#define FLOOD_MASK_UNI_FLOOD_DP_FLAG        HSL_RW
+
+
+    /* Global Control Register */
+#define GLOBAL_CTL                "gctl"
+#define GLOBAL_CTL_ID             5
+#define GLOBAL_CTL_OFFSET         0x0030
+#define GLOBAL_CTL_E_LENGTH       4
+#define GLOBAL_CTL_E_OFFSET       0
+#define GLOBAL_CTL_NR_E           1
+
+#define RATE_DROP_EN                          "gctl_rden"
+#define GLOBAL_CTL_RATE_DROP_EN_BOFFSET       29
+#define GLOBAL_CTL_RATE_DROP_EN_BLEN          1
+#define GLOBAL_CTL_RATE_DROP_EN_FLAG          HSL_RW
+
+#define QM_PRI_MODE                           "gctl_qmpm"
+#define GLOBAL_CTL_QM_PRI_MODE_BOFFSET        28
+#define GLOBAL_CTL_QM_PRI_MODE_BLEN           1
+#define GLOBAL_CTL_QM_PRI_MODE_FLAG           HSL_RW
+
+#define RATE_CRE_LIMIT                        "gctl_rcrl"
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BOFFSET     26
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BLEN        2
+#define GLOBAL_CTL_RATE_CRE_LIMIT_FLAG        HSL_RW
+
+#define RATE_TIME_SLOT                        "gctl_rtms"
+#define GLOBAL_CTL_RATE_TIME_SLOT_BOFFSET     24
+#define GLOBAL_CTL_RATE_TIME_SLOT_BLEN        2
+#define GLOBAL_CTL_RATE_TIME_SLOT_FLAG        HSL_RW
+
+#define RELOAD_TIMER                          "gctl_rdtm"
+#define GLOBAL_CTL_RELOAD_TIMER_BOFFSET       20
+#define GLOBAL_CTL_RELOAD_TIMER_BLEN          4
+#define GLOBAL_CTL_RELOAD_TIMER_FLAG          HSL_RW
+
+#define QM_CNT_LOCK                           "gctl_qmcl"
+#define GLOBAL_CTL_QM_CNT_LOCK_BOFFSET        19
+#define GLOBAL_CTL_QM_CNT_LOCK_BLEN           1
+#define GLOBAL_CTL_QM_CNT_LOCK_FLAG           HSL_RO
+
+#define BROAD_DROP_EN                         "gctl_bden"
+#define GLOBAL_CTL_BROAD_DROP_EN_BOFFSET      18
+#define GLOBAL_CTL_BROAD_DROP_EN_BLEN         1
+#define GLOBAL_CTL_BROAD_DROP_EN_FLAG         HSL_RW
+
+#define MAX_FRAME_SIZE                        "gctl_mfsz"
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BOFFSET     0
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BLEN        14
+#define GLOBAL_CTL_MAX_FRAME_SIZE_FLAG        HSL_RW
+
+
+    /* Flow Control Register */
+#define FLOW_CTL0                  "fctl"
+#define FLOW_CTL0_ID               6
+#define FLOW_CTL0_OFFSET           0x0034
+#define FLOW_CTL0_E_LENGTH         4
+#define FLOW_CTL0_E_OFFSET         0
+#define FLOW_CTL0_NR_E             1
+
+#define TEST_PAUSE                             "fctl_tps"
+#define FLOW_CTL0_TEST_PAUSE_BOFFSET           31
+#define FLOW_CTL0_TEST_PAUSE_BLEN              1
+#define FLOW_CTL0_TEST_PAUSE_FLAG              HSL_RW
+
+
+#define GOL_PAUSE_ON_THRES                     "fctl_gont"
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BOFFSET   16
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BLEN      8
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_FLAG      HSL_RW
+
+#define GOL_PAUSE_OFF_THRES                    "fctl_gofft"
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BOFFSET  0
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BLEN     8
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_FLAG     HSL_RW
+
+
+
+
+    /* Flow Control1 Register */
+#define FLOW_CTL1                  "fctl1"
+#define FLOW_CTL1_ID               6
+#define FLOW_CTL1_OFFSET           0x0038
+#define FLOW_CTL1_E_LENGTH         4
+#define FLOW_CTL1_E_OFFSET         0
+#define FLOW_CTL1_NR_E             1
+
+#define PORT_PAUSE_ON_THRES                    "fctl1_pont"
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BOFFSET  16
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BLEN     8
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_FLAG     HSL_RW
+
+#define PORT_PAUSE_OFF_THRES                   "fctl1_pofft"
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BOFFSET 0
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BLEN    8
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_FLAG    HSL_RW
+
+
+
+
+    /* QM Control Register */
+#define QM_CTL                    "qmct"
+#define QM_CTL_ID                 7
+#define QM_CTL_OFFSET             0x003c
+#define QM_CTL_E_LENGTH           4
+#define QM_CTL_E_OFFSET           0
+#define QM_CTL_NR_E               1
+
+#define QM_ERR_RST_EN                         "qmct_qeren"
+#define QM_CTL_QM_ERR_RST_EN_BOFFSET          31
+#define QM_CTL_QM_ERR_RST_EN_BLEN             1
+#define QM_CTL_QM_ERR_RST_EN_FLAG             HSL_RW
+
+#define LOOKUP_ERR_RST_EN                     "qmct_lpesen"
+#define QM_CTL_LOOKUP_ERR_RST_EN_BOFFSET      30
+#define QM_CTL_LOOKUP_ERR_RST_EN_BLEN         1
+#define QM_CTL_LOOKUP_ERR_RST_EN_FLAG         HSL_RW
+
+#define IGMP_JOIN_STATIC                      "qmct_igmpjs"
+#define QM_CTL_IGMP_JOIN_STATIC_BOFFSET       24
+#define QM_CTL_IGMP_JOIN_STATIC_BLEN          4
+#define QM_CTL_IGMP_JOIN_STATIC_FLAG          HSL_RW
+
+#define IGMP_JOIN_LEAKY                       "qmct_igmpjl"
+#define QM_CTL_IGMP_JOIN_LEAKY_BOFFSET        23
+#define QM_CTL_IGMP_JOIN_LEAKY_BLEN           1
+#define QM_CTL_IGMP_JOIN_LEAKY_FLAG           HSL_RW
+
+#define IGMP_CREAT_EN                         "qmct_igmpcrt"
+#define QM_CTL_IGMP_CREAT_EN_BOFFSET          22
+#define QM_CTL_IGMP_CREAT_EN_BLEN             1
+#define QM_CTL_IGMP_CREAT_EN_FLAG             HSL_RW
+
+#define PPPOE_RDT_EN                          "qmct_pppoerdten"
+#define QM_CTL_PPPOE_RDT_EN_BOFFSET           20
+#define QM_CTL_PPPOE_RDT_EN_BLEN              1
+#define QM_CTL_PPPOE_RDT_EN_FLAG              HSL_RW
+
+#define IGMP_V3_EN                            "qmct_igmpv3e"
+#define QM_CTL_IGMP_V3_EN_BOFFSET             19
+#define QM_CTL_IGMP_V3_EN_BLEN                1
+#define QM_CTL_IGMP_V3_EN_FLAG                HSL_RW
+
+#define IGMP_PRI_EN                           "qmct_igmpprie"
+#define QM_CTL_IGMP_PRI_EN_BOFFSET            18
+#define QM_CTL_IGMP_PRI_EN_BLEN               1
+#define QM_CTL_IGMP_PRI_EN_FLAG               HSL_RW
+
+#define IGMP_PRI                              "qmct_igmppri"
+#define QM_CTL_IGMP_PRI_BOFFSET               16
+#define QM_CTL_IGMP_PRI_BLEN                  2
+#define QM_CTL_IGMP_PRI_FLAG                  HSL_RW
+
+#define ARP_EN                                "qmct_arpe"
+#define QM_CTL_ARP_EN_BOFFSET                 15
+#define QM_CTL_ARP_EN_BLEN                    1
+#define QM_CTL_ARP_EN_FLAG                    HSL_RW
+
+#define ARP_CMD                               "qmct_arpc"
+#define QM_CTL_ARP_CMD_BOFFSET                14
+#define QM_CTL_ARP_CMD_BLEN                   1
+#define QM_CTL_ARP_CMD_FLAG                   HSL_RW
+
+#define RIP_CPY_EN                            "qmct_ripcpyen"
+#define QM_CTL_RIP_CPY_EN_BOFFSET             13
+#define QM_CTL_RIP_CPY_EN_BLEN                1
+#define QM_CTL_RIP_CPY_EN_FLAG                HSL_RW
+
+#define EAPOL_CMD                             "qmct_eapolc"
+#define QM_CTL_EAPOL_CMD_BOFFSET              12
+#define QM_CTL_EAPOL_CMD_BLEN                 1
+#define QM_CTL_EAPOL_CMD_FLAG                 HSL_RW
+
+#define IGMP_COPY_EN                          "qmct_igmpcpy"
+#define QM_CTL_IGMP_COPY_EN_BOFFSET           11
+#define QM_CTL_IGMP_COPY_EN_BLEN              1
+#define QM_CTL_IGMP_COPY_EN_FLAG              HSL_RW
+
+#define PPPOE_EN                              "qmct_pppoeen"
+#define QM_CTL_PPPOE_EN_BOFFSET               10
+#define QM_CTL_PPPOE_EN_BLEN                  1
+#define QM_CTL_PPPOE_EN_FLAG                  HSL_RW
+
+#define QM_FUNC_TEST                          "qmct_qmft"
+#define QM_CTL_QM_FUNC_TEST_BOFFSET           9
+#define QM_CTL_QM_FUNC_TEST_BLEN              1
+#define QM_CTL_QM_FUNC_TEST_FLAG              HSL_RW
+
+#define MS_FC_EN                              "qmct_msfe"
+#define QM_CTL_MS_FC_EN_BOFFSET               8
+#define QM_CTL_MS_FC_EN_BLEN                  1
+#define QM_CTL_MS_FC_EN_FLAG                  HSL_RW
+
+#define FLOW_DROP_EN                          "qmct_fden"
+#define QM_CTL_FLOW_DROP_EN_BOFFSET           7
+#define QM_CTL_FLOW_DROP_EN_BLEN              1
+#define QM_CTL_FLOW_DROP_EN_FLAG              HSL_RW
+
+#define MANAGE_VID_VIO_DROP_EN                "qmct_mden"
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BOFFSET 6
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BLEN    1
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_FLAG    HSL_RW
+
+#define FLOW_DROP_CNT                         "qmct_fdcn"
+#define QM_CTL_FLOW_DROP_CNT_BOFFSET          0
+#define QM_CTL_FLOW_DROP_CNT_BLEN             6
+#define QM_CTL_FLOW_DROP_CNT_FLAG             HSL_RW
+
+
+    /* Vlan Table Function Register */
+#define VLAN_TABLE_FUNC0           "vtbf0"
+#define VLAN_TABLE_FUNC0_ID        9
+#define VLAN_TABLE_FUNC0_OFFSET    0x0040
+#define VLAN_TABLE_FUNC0_E_LENGTH  4
+#define VLAN_TABLE_FUNC0_E_OFFSET  0
+#define VLAN_TABLE_FUNC0_NR_E      1
+
+#define VT_PRI_EN                              "vtbf_vtpen"
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET     31
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN        1
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG        HSL_RW
+
+#define VT_PRI                                 "vtbf_vtpri"
+#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET        28
+#define VLAN_TABLE_FUNC0_VT_PRI_BLEN           3
+#define VLAN_TABLE_FUNC0_VT_PRI_FLAG           HSL_RW
+
+#define VLAN_ID                                "vtbf_vid"
+#define VLAN_TABLE_FUNC0_VLAN_ID_BOFFSET       16
+#define VLAN_TABLE_FUNC0_VLAN_ID_BLEN          12
+#define VLAN_TABLE_FUNC0_VLAN_ID_FLAG          HSL_RW
+
+#define VT_PORT_NUM                            "vtbf_vtpn"
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BOFFSET   8
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BLEN      4
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_FLAG      HSL_RW
+
+#define VT_FULL_VIO                            "vtbf_vtflv"
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BOFFSET   4
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BLEN      1
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_FLAG      HSL_RW
+
+#define VT_BUSY                                "vtbf_vtbs"
+#define VLAN_TABLE_FUNC0_VT_BUSY_BOFFSET       3
+#define VLAN_TABLE_FUNC0_VT_BUSY_BLEN          1
+#define VLAN_TABLE_FUNC0_VT_BUSY_FLAG          HSL_RW
+
+#define VT_FUNC                                "vtbf_vtfc"
+#define VLAN_TABLE_FUNC0_VT_FUNC_BOFFSET       0
+#define VLAN_TABLE_FUNC0_VT_FUNC_BLEN          3
+#define VLAN_TABLE_FUNC0_VT_FUNC_FLAG          HSL_RW
+
+#define VLAN_TABLE_FUNC1           "vtbf1"
+#define VLAN_TABLE_FUNC1_ID        10
+#define VLAN_TABLE_FUNC1_OFFSET    0x0044
+#define VLAN_TABLE_FUNC1_E_LENGTH  4
+#define VLAN_TABLE_FUNC1_E_OFFSET  0
+#define VLAN_TABLE_FUNC1_NR_E      1
+
+#define VT_VALID                               "vtbf_vtvd"
+#define VLAN_TABLE_FUNC1_VT_VALID_BOFFSET      11
+#define VLAN_TABLE_FUNC1_VT_VALID_BLEN         1
+#define VLAN_TABLE_FUNC1_VT_VALID_FLAG         HSL_RW
+
+#define LEARN_DIS                              "vtbf_ldis"
+#define VLAN_TABLE_FUNC1_LEARN_DIS_BOFFSET     10
+#define VLAN_TABLE_FUNC1_LEARN_DIS_BLEN        1
+#define VLAN_TABLE_FUNC1_LEARN_DIS_FLAG        HSL_RW
+
+#define VID_MEM                                "vtbf_vidm"
+#define VLAN_TABLE_FUNC1_VID_MEM_BOFFSET       0
+#define VLAN_TABLE_FUNC1_VID_MEM_BLEN          6
+#define VLAN_TABLE_FUNC1_VID_MEM_FLAG          HSL_RW
+
+
+    /* Address Table Function Register */
+#define ADDR_TABLE_FUNC0           "atbf0"
+#define ADDR_TABLE_FUNC0_ID        11
+#define ADDR_TABLE_FUNC0_OFFSET    0x0050
+#define ADDR_TABLE_FUNC0_E_LENGTH  4
+#define ADDR_TABLE_FUNC0_E_OFFSET  0
+#define ADDR_TABLE_FUNC0_NR_E      1
+
+#define AT_ADDR_BYTE4                          "atbf_adb4"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 24
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE5                          "atbf_adb5"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 16
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG    HSL_RW
+
+#define AT_FULL_VIO                            "atbf_atfv"
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BOFFSET   12
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BLEN      1
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_FLAG      HSL_RW
+
+#define AT_PORT_NUM                            "atbf_atpn"
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BOFFSET   8
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BLEN      4
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_FLAG      HSL_RW
+
+#define FLUSH_ST_EN                            "atbf_fsen"
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BOFFSET   4
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BLEN      1
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_FLAG      HSL_RW
+
+#define AT_BUSY                                "atbf_atbs"
+#define ADDR_TABLE_FUNC0_AT_BUSY_BOFFSET       3
+#define ADDR_TABLE_FUNC0_AT_BUSY_BLEN          1
+#define ADDR_TABLE_FUNC0_AT_BUSY_FLAG          HSL_RW
+
+#define AT_FUNC                                "atbf_atfc"
+#define ADDR_TABLE_FUNC0_AT_FUNC_BOFFSET       0
+#define ADDR_TABLE_FUNC0_AT_FUNC_BLEN          3
+#define ADDR_TABLE_FUNC0_AT_FUNC_FLAG          HSL_RW
+
+#define ADDR_TABLE_FUNC1           "atbf1"
+#define ADDR_TABLE_FUNC1_ID        12
+#define ADDR_TABLE_FUNC1_OFFSET    0x0054
+#define ADDR_TABLE_FUNC1_E_LENGTH  4
+#define ADDR_TABLE_FUNC1_E_OFFSET  0
+#define ADDR_TABLE_FUNC1_NR_E      0
+
+#define AT_ADDR_BYTE0                          "atbf_adb0"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 24
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE1                          "atbf_adb1"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 16
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE2                          "atbf_adb2"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BOFFSET 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE3                          "atbf_adb3"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BOFFSET 0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_FLAG    HSL_RW
+
+#define ADDR_TABLE_FUNC2           "atbf2"
+#define ADDR_TABLE_FUNC2_ID        13
+#define ADDR_TABLE_FUNC2_OFFSET    0x0058
+#define ADDR_TABLE_FUNC2_E_LENGTH  4
+#define ADDR_TABLE_FUNC2_E_OFFSET  0
+#define ADDR_TABLE_FUNC2_NR_E      0
+
+#define COPY_TO_CPU                            "atbf_cpcpu"
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET   26
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN      1
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG      HSL_RW
+
+#define REDRCT_TO_CPU                          "atbf_rdcpu"
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 25
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN    1
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG    HSL_RW
+
+#define LEAKY_EN                               "atbf_lkyen"
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET      24
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN         1
+#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG         HSL_RW
+
+#define AT_STATUS                              "atbf_atsts"
+#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET     16
+#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN        4
+#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG        HSL_RW
+
+#define CLONE_EN                               "atbf_clone"
+#define ADDR_TABLE_FUNC2_CLONE_EN_BOFFSET      15
+#define ADDR_TABLE_FUNC2_CLONE_EN_BLEN         1
+#define ADDR_TABLE_FUNC2_CLONE_EN_FLAG         HSL_RW
+
+#define SA_DROP_EN                             "atbf_saden"
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BOFFSET    14
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BLEN       1
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_FLAG       HSL_RW
+
+#define MIRROR_EN                              "atbf_miren"
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BOFFSET     13
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BLEN        1
+#define ADDR_TABLE_FUNC2_MIRROR_EN_FLAG        HSL_RW
+
+#define AT_PRI_EN                              "atbf_atpen"
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BOFFSET     12
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BLEN        1
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_FLAG        HSL_RW
+
+#define AT_PRI                                 "atbf_atpri"
+#define ADDR_TABLE_FUNC2_AT_PRI_BOFFSET        10
+#define ADDR_TABLE_FUNC2_AT_PRI_BLEN           2
+#define ADDR_TABLE_FUNC2_AT_PRI_FLAG           HSL_RW
+
+#define CROSS_PT                               "atbf_cpt"
+#define ADDR_TABLE_FUNC2_CROSS_PT_BOFFSET      8
+#define ADDR_TABLE_FUNC2_CROSS_PT_BLEN         1
+#define ADDR_TABLE_FUNC2_CROSS_PT_FLAG         HSL_RW
+
+#define DES_PORT                               "atbf_desp"
+#define ADDR_TABLE_FUNC2_DES_PORT_BOFFSET      0
+#define ADDR_TABLE_FUNC2_DES_PORT_BLEN         6
+#define ADDR_TABLE_FUNC2_DES_PORT_FLAG         HSL_RW
+
+
+    /* Address Table Control Register */
+#define ADDR_TABLE_CTL            "atbc"
+#define ADDR_TABLE_CTL_ID         14
+#define ADDR_TABLE_CTL_OFFSET     0x005C
+#define ADDR_TABLE_CTL_E_LENGTH   4
+#define ADDR_TABLE_CTL_E_OFFSET   0
+#define ADDR_TABLE_CTL_NR_E       1
+
+#define LOOP_CH_TIME                           "atbc_lct"
+#define ADDR_TABLE_CTL_LOOP_CH_TIME_BOFFSET    24
+#define ADDR_TABLE_CTL_LOOP_CH_TIMEP_BLEN      3
+#define ADDR_TABLE_CTL_LOOP_CH_TIME_FLAG       HSL_RW
+
+#define RESVID_DROP                            "atbc_rviddrop"
+#define ADDR_TABLE_CTL_RESVID_DROP_BOFFSET     22
+#define ADDR_TABLE_CTL_RESVID_DROP_BLEN        1
+#define ADDR_TABLE_CTL_RESVID_DROP_FLAG        HSL_RW
+
+#define STAG_MODE                              "atbc_stag"
+#define ADDR_TABLE_CTL_STAG_MODE_BOFFSET       21
+#define ADDR_TABLE_CTL_STAG_MODE_BLEN          1
+#define ADDR_TABLE_CTL_STAG_MODE_FLAG          HSL_RW
+
+#define ARL_INI_EN                             "atbc_arlie"
+#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET      19
+#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN         1
+#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG         HSL_RW
+
+#define LEARN_CHANGE_EN                        "atbc_lcen"
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 18
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN    1
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG    HSL_RW
+
+#define AGE_EN                                 "atbc_agee"
+#define ADDR_TABLE_CTL_AGE_EN_BOFFSET          17
+#define ADDR_TABLE_CTL_AGE_EN_BLEN             1
+#define ADDR_TABLE_CTL_AGE_EN_FLAG             HSL_RW
+
+#define AGE_TIME                               "atbc_aget"
+#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET        0
+#define ADDR_TABLE_CTL_AGE_TIME_BLEN           16
+#define ADDR_TABLE_CTL_AGE_TIME_FLAG           HSL_RW
+
+
+    /* IP Priority Mapping Register */
+#define IP_PRI_MAPPING            "imap"
+#define IP_PRI_MAPPING_ID         15
+#define IP_PRI_MAPPING_OFFSET     0x0060
+#define IP_PRI_MAPPING_E_LENGTH   4
+#define IP_PRI_MAPPING_E_OFFSET   0
+#define IP_PRI_MAPPING_NR_E       1
+
+
+    /* IP Priority Mapping Register */
+#define IP_PRI_MAPPING0            "imap0"
+#define IP_PRI_MAPPING0_ID         15
+#define IP_PRI_MAPPING0_OFFSET     0x0060
+#define IP_PRI_MAPPING0_E_LENGTH   4
+#define IP_PRI_MAPPING0_E_OFFSET   0
+#define IP_PRI_MAPPING0_NR_E       0
+
+#define IP_0X3C                                "imap_ip3c"
+#define IP_PRI_MAPPING0_IP_0X3C_BOFFSET        30
+#define IP_PRI_MAPPING0_IP_0X3C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X3C_FLAG           HSL_RW
+
+#define IP_0X38                                "imap_ip38"
+#define IP_PRI_MAPPING0_IP_0X38_BOFFSET        28
+#define IP_PRI_MAPPING0_IP_0X38_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X38_FLAG           HSL_RW
+
+#define IP_0X34                                "imap_ip34"
+#define IP_PRI_MAPPING0_IP_0X34_BOFFSET        26
+#define IP_PRI_MAPPING0_IP_0X34_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X34_FLAG           HSL_RW
+
+#define IP_0X30                                "imap_ip30"
+#define IP_PRI_MAPPING0_IP_0X30_BOFFSET        24
+#define IP_PRI_MAPPING0_IP_0X30_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X30_FLAG           HSL_RW
+
+#define IP_0X2C                                "imap_ip2c"
+#define IP_PRI_MAPPING0_IP_0X2C_BOFFSET        22
+#define IP_PRI_MAPPING0_IP_0X2C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X2C_FLAG           HSL_RW
+
+#define IP_0X28                                "imap_ip28"
+#define IP_PRI_MAPPING0_IP_0X28_BOFFSET        20
+#define IP_PRI_MAPPING0_IP_0X28_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X28_FLAG           HSL_RW
+
+#define IP_0X24                                "imap_ip24"
+#define IP_PRI_MAPPING0_IP_0X24_BOFFSET        18
+#define IP_PRI_MAPPING0_IP_0X24_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X24_FLAG           HSL_RW
+
+#define IP_0X20                                "imap_ip20"
+#define IP_PRI_MAPPING0_IP_0X20_BOFFSET        16
+#define IP_PRI_MAPPING0_IP_0X20_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X20_FLAG           HSL_RW
+
+#define IP_0X1C                                "imap_ip1c"
+#define IP_PRI_MAPPING0_IP_0X1C_BOFFSET        14
+#define IP_PRI_MAPPING0_IP_0X1C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X1C_FLAG           HSL_RW
+
+#define IP_0X18                                "imap_ip18"
+#define IP_PRI_MAPPING0_IP_0X18_BOFFSET        12
+#define IP_PRI_MAPPING0_IP_0X18_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X18_FLAG           HSL_RW
+
+#define IP_0X14                                "imap_ip14"
+#define IP_PRI_MAPPING0_IP_0X14_BOFFSET        10
+#define IP_PRI_MAPPING0_IP_0X14_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X14_FLAG           HSL_RW
+
+#define IP_0X10                                "imap_ip10"
+#define IP_PRI_MAPPING0_IP_0X10_BOFFSET        8
+#define IP_PRI_MAPPING0_IP_0X10_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X10_FLAG           HSL_RW
+
+#define IP_0X0C                                "imap_ip0c"
+#define IP_PRI_MAPPING0_IP_0X0C_BOFFSET        6
+#define IP_PRI_MAPPING0_IP_0X0C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X0C_FLAG           HSL_RW
+
+#define IP_0X08                                "imap_ip08"
+#define IP_PRI_MAPPING0_IP_0X08_BOFFSET        4
+#define IP_PRI_MAPPING0_IP_0X08_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X08_FLAG           HSL_RW
+
+#define IP_0X04                                "imap_ip04"
+#define IP_PRI_MAPPING0_IP_0X04_BOFFSET        2
+#define IP_PRI_MAPPING0_IP_0X04_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X04_FLAG           HSL_RW
+
+#define IP_0X00                                "imap_ip00"
+#define IP_PRI_MAPPING0_IP_0X00_BOFFSET        0
+#define IP_PRI_MAPPING0_IP_0X00_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X00_FLAG           HSL_RW
+
+#define IP_PRI_MAPPING1            "imap1"
+#define IP_PRI_MAPPING1_ID         16
+#define IP_PRI_MAPPING1_OFFSET     0x0064
+#define IP_PRI_MAPPING1_E_LENGTH   4
+#define IP_PRI_MAPPING1_E_OFFSET   0
+#define IP_PRI_MAPPING1_NR_E       0
+
+#define IP_0X7C                                "imap_ip7c"
+#define IP_PRI_MAPPING1_IP_0X7C_BOFFSET        30
+#define IP_PRI_MAPPING1_IP_0X7C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X7C_FLAG           HSL_RW
+
+#define IP_0X78                                "imap_ip78"
+#define IP_PRI_MAPPING1_IP_0X78_BOFFSET        28
+#define IP_PRI_MAPPING1_IP_0X78_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X78_FLAG           HSL_RW
+
+#define IP_0X74                                "imap_ip74"
+#define IP_PRI_MAPPING1_IP_0X74_BOFFSET        26
+#define IP_PRI_MAPPING1_IP_0X74_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X74_FLAG           HSL_RW
+
+#define IP_0X70                                "imap_ip70"
+#define IP_PRI_MAPPING1_IP_0X70_BOFFSET        24
+#define IP_PRI_MAPPING1_IP_0X70_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X70_FLAG           HSL_RW
+
+#define IP_0X6C                                "imap_ip6c"
+#define IP_PRI_MAPPING1_IP_0X6C_BOFFSET        22
+#define IP_PRI_MAPPING1_IP_0X6C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X6C_FLAG           HSL_RW
+
+#define IP_0X68                                "imap_ip68"
+#define IP_PRI_MAPPING1_IP_0X68_BOFFSET        20
+#define IP_PRI_MAPPING1_IP_0X68_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X68_FLAG           HSL_RW
+
+#define IP_0X64                                "imap_ip64"
+#define IP_PRI_MAPPING1_IP_0X64_BOFFSET        18
+#define IP_PRI_MAPPING1_IP_0X64_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X64_FLAG           HSL_RW
+
+#define IP_0X60                                "imap_ip60"
+#define IP_PRI_MAPPING1_IP_0X60_BOFFSET        16
+#define IP_PRI_MAPPING1_IP_0X60_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X60_FLAG           HSL_RW
+
+#define IP_0X5C                                "imap_ip5c"
+#define IP_PRI_MAPPING1_IP_0X5C_BOFFSET        14
+#define IP_PRI_MAPPING1_IP_0X5C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X5C_FLAG           HSL_RW
+
+#define IP_0X58                                "imap_ip58"
+#define IP_PRI_MAPPING1_IP_0X58_BOFFSET        12
+#define IP_PRI_MAPPING1_IP_0X58_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X58_FLAG           HSL_RW
+
+#define IP_0X54                                "imap_ip54"
+#define IP_PRI_MAPPING1_IP_0X54_BOFFSET        10
+#define IP_PRI_MAPPING1_IP_0X54_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X54_FLAG           HSL_RW
+
+#define IP_0X50                                "imap_ip50"
+#define IP_PRI_MAPPING1_IP_0X50_BOFFSET        8
+#define IP_PRI_MAPPING1_IP_0X50_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X50_FLAG           HSL_RW
+
+#define IP_0X4C                                "imap_ip4c"
+#define IP_PRI_MAPPING1_IP_0X4C_BOFFSET        6
+#define IP_PRI_MAPPING1_IP_0X4C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X4C_FLAG           HSL_RW
+
+#define IP_0X48                                "imap_ip48"
+#define IP_PRI_MAPPING1_IP_0X48_BOFFSET        4
+#define IP_PRI_MAPPING1_IP_0X48_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X48_FLAG           HSL_RW
+
+#define IP_0X44                                "imap_ip44"
+#define IP_PRI_MAPPING1_IP_0X44_BOFFSET        2
+#define IP_PRI_MAPPING1_IP_0X44_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X44_FLAG           HSL_RW
+
+#define IP_0X40                                "imap_ip40"
+#define IP_PRI_MAPPING1_IP_0X40_BOFFSET        0
+#define IP_PRI_MAPPING1_IP_0X40_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X40_FLAG           HSL_RW
+
+
+#define IP_PRI_MAPPING2            "imap2"
+#define IP_PRI_MAPPING2_ID         17
+#define IP_PRI_MAPPING2_OFFSET     0x0068
+#define IP_PRI_MAPPING2_E_LENGTH   4
+#define IP_PRI_MAPPING2_E_OFFSET   0
+#define IP_PRI_MAPPING2_NR_E       0
+
+#define IP_0XBC                                "imap_ipbc"
+#define IP_PRI_MAPPING2_IP_0XBC_BOFFSET        30
+#define IP_PRI_MAPPING2_IP_0XBC_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XBC_FLAG           HSL_RW
+
+#define IP_0XB8                                "imap_ipb8"
+#define IP_PRI_MAPPING2_IP_0XB8_BOFFSET        28
+#define IP_PRI_MAPPING2_IP_0XB8_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XB8_FLAG           HSL_RW
+
+#define IP_0XB4                                "imap_ipb4"
+#define IP_PRI_MAPPING2_IP_0XB4_BOFFSET        26
+#define IP_PRI_MAPPING2_IP_0XB4_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XB4_FLAG           HSL_RW
+
+#define IP_0XB0                                "imap_ipb0"
+#define IP_PRI_MAPPING2_IP_0XB0_BOFFSET        24
+#define IP_PRI_MAPPING2_IP_0XB0_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XB0_FLAG           HSL_RW
+
+#define IP_0XAC                                "imap_ipac"
+#define IP_PRI_MAPPING2_IP_0XAC_BOFFSET        22
+#define IP_PRI_MAPPING2_IP_0XAC_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XAC_FLAG           HSL_RW
+
+#define IP_0XA8                                "imap_ipa8"
+#define IP_PRI_MAPPING2_IP_0XA8_BOFFSET        20
+#define IP_PRI_MAPPING2_IP_0XA8_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XA8_FLAG           HSL_RW
+
+#define IP_0XA4                                "imap_ipa4"
+#define IP_PRI_MAPPING2_IP_0XA4_BOFFSET        18
+#define IP_PRI_MAPPING2_IP_0XA4_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XA4_FLAG           HSL_RW
+
+#define IP_0XA0                                "imap_ipa0"
+#define IP_PRI_MAPPING2_IP_0XA0_BOFFSET        16
+#define IP_PRI_MAPPING2_IP_0XA0_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XA0_FLAG           HSL_RW
+
+#define IP_0X9C                                "imap_ip9c"
+#define IP_PRI_MAPPING2_IP_0X9C_BOFFSET        14
+#define IP_PRI_MAPPING2_IP_0X9C_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X9C_FLAG           HSL_RW
+
+#define IP_0X98                                "imap_ip98"
+#define IP_PRI_MAPPING2_IP_0X98_BOFFSET        12
+#define IP_PRI_MAPPING2_IP_0X98_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X98_FLAG           HSL_RW
+
+#define IP_0X94                                "imap_ip94"
+#define IP_PRI_MAPPING2_IP_0X94_BOFFSET        10
+#define IP_PRI_MAPPING2_IP_0X94_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X94_FLAG           HSL_RW
+
+#define IP_0X90                                "imap_ip90"
+#define IP_PRI_MAPPING2_IP_0X90_BOFFSET        8
+#define IP_PRI_MAPPING2_IP_0X90_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X90_FLAG           HSL_RW
+
+#define IP_0X8C                                "imap_ip8c"
+#define IP_PRI_MAPPING2_IP_0X8C_BOFFSET        6
+#define IP_PRI_MAPPING2_IP_0X8C_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X8C_FLAG           HSL_RW
+
+#define IP_0X88                                "imap_ip88"
+#define IP_PRI_MAPPING2_IP_0X88_BOFFSET        4
+#define IP_PRI_MAPPING2_IP_0X88_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X88_FLAG           HSL_RW
+
+#define IP_0X84                                "imap_ip84"
+#define IP_PRI_MAPPING2_IP_0X84_BOFFSET        2
+#define IP_PRI_MAPPING2_IP_0X84_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X84_FLAG           HSL_RW
+
+#define IP_0X80                                "imap_ip80"
+#define IP_PRI_MAPPING2_IP_0X80_BOFFSET        0
+#define IP_PRI_MAPPING2_IP_0X80_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X80_FLAG           HSL_RW
+
+#define IP_PRI_MAPPING3            "imap3"
+#define IP_PRI_MAPPING3_ID         18
+#define IP_PRI_MAPPING3_OFFSET     0x006C
+#define IP_PRI_MAPPING3_E_LENGTH   4
+#define IP_PRI_MAPPING3_E_OFFSET   0
+#define IP_PRI_MAPPING3_NR_E       0
+
+#define IP_0XFC                                "imap_ipfc"
+#define IP_PRI_MAPPING3_IP_0XFC_BOFFSET        30
+#define IP_PRI_MAPPING3_IP_0XFC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XFC_FLAG           HSL_RW
+
+#define IP_0XF8                                "imap_ipf8"
+#define IP_PRI_MAPPING3_IP_0XF8_BOFFSET        28
+#define IP_PRI_MAPPING3_IP_0XF8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XF8_FLAG           HSL_RW
+
+#define IP_0XF4                                "imap_ipf4"
+#define IP_PRI_MAPPING3_IP_0XF4_BOFFSET        26
+#define IP_PRI_MAPPING3_IP_0XF4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XF4_FLAG           HSL_RW
+
+#define IP_0XF0                                "imap_ipf0"
+#define IP_PRI_MAPPING3_IP_0XF0_BOFFSET        24
+#define IP_PRI_MAPPING3_IP_0XF0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XF0_FLAG           HSL_RW
+
+#define IP_0XEC                                "imap_ipec"
+#define IP_PRI_MAPPING3_IP_0XEC_BOFFSET        22
+#define IP_PRI_MAPPING3_IP_0XEC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XEC_FLAG           HSL_RW
+
+#define IP_0XE8                                "imap_ipe8"
+#define IP_PRI_MAPPING3_IP_0XE8_BOFFSET        20
+#define IP_PRI_MAPPING3_IP_0XE8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XE8_FLAG           HSL_RW
+
+#define IP_0XE4                                "imap_ipe4"
+#define IP_PRI_MAPPING3_IP_0XE4_BOFFSET        18
+#define IP_PRI_MAPPING3_IP_0XE4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XE4_FLAG           HSL_RW
+
+#define IP_0XE0                                "imap_ipe0"
+#define IP_PRI_MAPPING3_IP_0XE0_BOFFSET        16
+#define IP_PRI_MAPPING3_IP_0XE0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XE0_FLAG           HSL_RW
+
+#define IP_0XDC                                "imap_ipdc"
+#define IP_PRI_MAPPING3_IP_0XDC_BOFFSET        14
+#define IP_PRI_MAPPING3_IP_0XDC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XDC_FLAG           HSL_RW
+
+#define IP_0XD8                                "imap_ipd8"
+#define IP_PRI_MAPPING3_IP_0XD8_BOFFSET        12
+#define IP_PRI_MAPPING3_IP_0XD8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XD8_FLAG           HSL_RW
+
+#define IP_0XD4                                "imap_ipd4"
+#define IP_PRI_MAPPING3_IP_0XD4_BOFFSET        10
+#define IP_PRI_MAPPING3_IP_0XD4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XD4_FLAG           HSL_RW
+
+#define IP_0XD0                                "imap_ipd0"
+#define IP_PRI_MAPPING3_IP_0XD0_BOFFSET        8
+#define IP_PRI_MAPPING3_IP_0XD0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XD0_FLAG           HSL_RW
+
+#define IP_0XCC                                "imap_ipcc"
+#define IP_PRI_MAPPING3_IP_0XCC_BOFFSET        6
+#define IP_PRI_MAPPING3_IP_0XCC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XCC_FLAG           HSL_RW
+
+#define IP_0XC8                                "imap_ipc8"
+#define IP_PRI_MAPPING3_IP_0XC8_BOFFSET        4
+#define IP_PRI_MAPPING3_IP_0XC8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XC8_FLAG           HSL_RW
+
+#define IP_0XC4                                "imap_ipc4"
+#define IP_PRI_MAPPING3_IP_0XC4_BOFFSET        2
+#define IP_PRI_MAPPING3_IP_0XC4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XC4_FLAG           HSL_RW
+
+#define IP_0XC0                                "imap_ipc0"
+#define IP_PRI_MAPPING3_IP_0XC0_BOFFSET        0
+#define IP_PRI_MAPPING3_IP_0XC0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XC0_FLAG           HSL_RW
+
+
+    /* Tag Priority Mapping Register */
+#define TAG_PRI_MAPPING           "tpmap"
+#define TAG_PRI_MAPPING_ID        19
+#define TAG_PRI_MAPPING_OFFSET    0x0070
+#define TAG_PRI_MAPPING_E_LENGTH  4
+#define TAG_PRI_MAPPING_E_OFFSET  0
+#define TAG_PRI_MAPPING_NR_E      1
+
+#define TAG_0X07                                "tpmap_tg07"
+#define TAG_PRI_MAPPING_TAG_0X07_BOFFSET      14
+#define TAG_PRI_MAPPING_TAG_0X07_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X07_FLAG         HSL_RW
+
+#define TAG_0X06                              "tpmap_tg06"
+#define TAG_PRI_MAPPING_TAG_0X06_BOFFSET      12
+#define TAG_PRI_MAPPING_TAG_0X06_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X06_FLAG         HSL_RW
+
+#define TAG_0X05                              "tpmap_tg05"
+#define TAG_PRI_MAPPING_TAG_0X05_BOFFSET      10
+#define TAG_PRI_MAPPING_TAG_0X05_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X05_FLAG         HSL_RW
+
+#define TAG_0X04                              "tpmap_tg04"
+#define TAG_PRI_MAPPING_TAG_0X04_BOFFSET      8
+#define TAG_PRI_MAPPING_TAG_0X04_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X04_FLAG         HSL_RW
+
+#define TAG_0X03                              "tpmap_tg03"
+#define TAG_PRI_MAPPING_TAG_0X03_BOFFSET      6
+#define TAG_PRI_MAPPING_TAG_0X03_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X03_FLAG         HSL_RW
+
+#define TAG_0X02                              "tpmap_tg02"
+#define TAG_PRI_MAPPING_TAG_0X02_BOFFSET      4
+#define TAG_PRI_MAPPING_TAG_0X02_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X02_FLAG         HSL_RW
+
+#define TAG_0X01                              "tpmap_tg01"
+#define TAG_PRI_MAPPING_TAG_0X01_BOFFSET      2
+#define TAG_PRI_MAPPING_TAG_0X01_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X01_FLAG         HSL_RW
+
+#define TAG_0X00                              "tpmap_tg00"
+#define TAG_PRI_MAPPING_TAG_0X00_BOFFSET      0
+#define TAG_PRI_MAPPING_TAG_0X00_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X00_FLAG         HSL_RW
+
+
+    /* Service tag Register */
+#define SERVICE_TAG                  "servicetag"
+#define SERVICE_TAG_ID               20
+#define SERVICE_TAG_OFFSET           0x0074
+#define SERVICE_TAG_E_LENGTH         4
+#define SERVICE_TAG_E_OFFSET         0
+#define SERVICE_TAG_NR_E             1
+
+#define TAG_VALUE                        "servicetag_val"
+#define SERVICE_TAG_TAG_VALUE_BOFFSET    0
+#define SERVICE_TAG_TAG_VALUE_BLEN       16
+#define SERVICE_TAG_TAG_VALUE_FLAG       HSL_RW
+
+
+    /* Cpu Port Register */
+#define CPU_PORT                  "cpup"
+#define CPU_PORT_ID               20
+#define CPU_PORT_OFFSET           0x0078
+#define CPU_PORT_E_LENGTH         4
+#define CPU_PORT_E_OFFSET         0
+#define CPU_PORT_NR_E             0
+
+#define CPU_PORT_EN                           "cpup_cpupe"
+#define CPU_PORT_CPU_PORT_EN_BOFFSET          8
+#define CPU_PORT_CPU_PORT_EN_BLEN             1
+#define CPU_PORT_CPU_PORT_EN_FLAG             HSL_RW
+
+#define MIRROR_PORT_NUM                       "cpup_mirpn"
+#define CPU_PORT_MIRROR_PORT_NUM_BOFFSET      4
+#define CPU_PORT_MIRROR_PORT_NUM_BLEN         4
+#define CPU_PORT_MIRROR_PORT_NUM_FLAG         HSL_RW
+
+
+    /* MIB Function Register */
+#define MIB_FUNC                  "mibfunc"
+#define MIB_FUNC_ID               21
+#define MIB_FUNC_OFFSET           0x0080
+#define MIB_FUNC_E_LENGTH         4
+#define MIB_FUNC_E_OFFSET         0
+#define MIB_FUNC_NR_E             1
+
+#define MAC_CRC_EN                            "mibfunc_crcen"
+#define MIB_FUNC_MAC_CRC_EN_BOFFSET            31
+#define MIB_FUNC_MAC_CRC_EN_BLEN               1
+#define MIB_FUNC_MAC_CRC_EN_FLAG               HSL_RW
+
+#define MIB_EN                               "mib_en"
+#define MIB_FUNC_MIB_EN_BOFFSET              30
+#define MIB_FUNC_MIB_EN_BLEN                 1
+#define MIB_FUNC_MIB_EN_FLAG                 HSL_RW
+
+#define MIB_FUN                              "mibfunc_mibf"
+#define MIB_FUNC_MIB_FUN_BOFFSET              24
+#define MIB_FUNC_MIB_FUN_BLEN                 3
+#define MIB_FUNC_MIB_FUN_FLAG                 HSL_RW
+
+#define MIB_BUSY                              "mibfunc_mibb"
+#define MIB_FUNC_MIB_BUSY_BOFFSET              17
+#define MIB_FUNC_MIB_BUSY_BLEN                 1
+#define MIB_FUNC_MIB_BUSY_FLAG                 HSL_RW
+
+#define MIB_AT_HALF_EN                        "mibfunc_mibhe"
+#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET        16
+#define MIB_FUNC_MIB_AT_HALF_EN_BLEN           1
+#define MIB_FUNC_MIB_AT_HALF_EN_FLAG           HSL_RW
+
+#define MIB_TIMER                             "mibfunc_mibt"
+#define MIB_FUNC_MIB_TIMER_BOFFSET             0
+#define MIB_FUNC_MIB_TIMER_BLEN                16
+#define MIB_FUNC_MIB_TIMER_FLAG                HSL_RW
+
+
+    /* Mdio control Register */
+#define MDIO_CTRL               "mctrl"
+#define MDIO_CTRL_ID            24
+#define MDIO_CTRL_OFFSET        0x0098
+#define MDIO_CTRL_E_LENGTH      4
+#define MDIO_CTRL_E_OFFSET      0
+#define MDIO_CTRL_NR_E          1
+
+#define MSTER_EN                        "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET      30
+#define MDIO_CTRL_MSTER_EN_BLEN         1
+#define MDIO_CTRL_MSTER_EN_FLAG         HSL_RW
+
+#define MSTER_EN                        "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET      30
+#define MDIO_CTRL_MSTER_EN_BLEN         1
+#define MDIO_CTRL_MSTER_EN_FLAG         HSL_RW
+
+#define CMD                             "mctrl_cmd"
+#define MDIO_CTRL_CMD_BOFFSET           27
+#define MDIO_CTRL_CMD_BLEN              1
+#define MDIO_CTRL_CMD_FLAG              HSL_RW
+
+#define SUP_PRE                         "mctrl_spre"
+#define MDIO_CTRL_SUP_PRE_BOFFSET       26
+#define MDIO_CTRL_SUP_PRE_BLEN          1
+#define MDIO_CTRL_SUP_PRE_FLAG          HSL_RW
+
+#define PHY_ADDR                        "mctrl_phyaddr"
+#define MDIO_CTRL_PHY_ADDR_BOFFSET      21
+#define MDIO_CTRL_PHY_ADDR_BLEN         5
+#define MDIO_CTRL_PHY_ADDR_FLAG         HSL_RW
+
+#define REG_ADDR                        "mctrl_regaddr"
+#define MDIO_CTRL_REG_ADDR_BOFFSET      16
+#define MDIO_CTRL_REG_ADDR_BLEN         5
+#define MDIO_CTRL_REG_ADDR_FLAG         HSL_RW
+
+#define DATA                            "mctrl_data"
+#define MDIO_CTRL_DATA_BOFFSET          0
+#define MDIO_CTRL_DATA_BLEN             16
+#define MDIO_CTRL_DATA_FLAG             HSL_RW
+
+
+
+
+    /* BIST control Register */
+#define BIST_CTRL               "bctrl"
+#define BIST_CTRL_ID            24
+#define BIST_CTRL_OFFSET        0x00a0
+#define BIST_CTRL_E_LENGTH      4
+#define BIST_CTRL_E_OFFSET      0
+#define BIST_CTRL_NR_E          1
+
+#define BIST_BUSY                        "bctrl_bb"
+#define BIST_CTRL_BIST_BUSY_BOFFSET      31
+#define BIST_CTRL_BIST_BUSY_BLEN         1
+#define BIST_CTRL_BIST_BUSY_FLAG         HSL_RW
+
+#define ONE_ERR                          "bctrl_oe"
+#define BIST_CTRL_ONE_ERR_BOFFSET        30
+#define BIST_CTRL_ONE_ERR_BLEN           1
+#define BIST_CTRL_ONE_ERR_FLAG           HSL_RO
+
+#define ERR_MEM                          "bctrl_em"
+#define BIST_CTRL_ERR_MEM_BOFFSET        24
+#define BIST_CTRL_ERR_MEM_BLEN           4
+#define BIST_CTRL_ERR_MEM_FLAG           HSL_RO
+
+#define PTN_EN2                          "bctrl_pe2"
+#define BIST_CTRL_PTN_EN2_BOFFSET        22
+#define BIST_CTRL_PTN_EN2_BLEN           1
+#define BIST_CTRL_PTN_EN2_FLAG           HSL_RW
+
+#define PTN_EN1                          "bctrl_pe1"
+#define BIST_CTRL_PTN_EN1_BOFFSET        21
+#define BIST_CTRL_PTN_EN1_BLEN           1
+#define BIST_CTRL_PTN_EN1_FLAG           HSL_RW
+
+#define PTN_EN0                          "bctrl_pe0"
+#define BIST_CTRL_PTN_EN0_BOFFSET        20
+#define BIST_CTRL_PTN_EN0_BLEN           1
+#define BIST_CTRL_PTN_EN0_FLAG           HSL_RW
+
+#define ERR_PTN                          "bctrl_ep"
+#define BIST_CTRL_ERR_PTN_BOFFSET        16
+#define BIST_CTRL_ERR_PTN_BLEN           2
+#define BIST_CTRL_ERR_PTN_FLAG           HSL_RO
+
+#define ERR_CNT                          "bctrl_ec"
+#define BIST_CTRL_ERR_CNT_BOFFSET        13
+#define BIST_CTRL_ERR_CNT_BLEN           2
+#define BIST_CTRL_ERR_CNT_FLAG           HSL_RO
+
+#define ERR_ADDR                         "bctrl_ea"
+#define BIST_CTRL_ERR_ADDR_BOFFSET       0
+#define BIST_CTRL_ERR_ADDR_BLEN          12
+#define BIST_CTRL_ERR_ADDR_FLAG          HSL_RO
+
+
+
+
+    /* BIST recover Register */
+#define BIST_RCV               "brcv"
+#define BIST_RCV_ID            24
+#define BIST_RCV_OFFSET        0x00a4
+#define BIST_RCV_E_LENGTH      4
+#define BIST_RCV_E_OFFSET      0
+#define BIST_RCV_NR_E          1
+
+#define RCV_EN                           "brcv_en"
+#define BIST_RCV_RCV_EN_BOFFSET          31
+#define BIST_RCV_RCV_EN_BLEN             1
+#define BIST_RCV_RCV_EN_FLAG             HSL_RW
+
+#define RCV_ADDR                         "brcv_addr"
+#define BIST_RCV_RCV_ADDR_BOFFSET        0
+#define BIST_RCV_RCV_ADDR_BLEN           12
+#define BIST_RCV_RCV_ADDR_FLAG           HSL_RW
+
+
+
+
+    /* LED control Register */
+#define LED_CTRL               "ledctrl"
+#define LED_CTRL_ID            25
+#define LED_CTRL_OFFSET        0x00b0
+#define LED_CTRL_E_LENGTH      4
+#define LED_CTRL_E_OFFSET      0
+#define LED_CTRL_NR_E          1
+
+#define PATTERN_EN                           "lctrl_pen"
+#define LED_CTRL_PATTERN_EN_BOFFSET          14
+#define LED_CTRL_PATTERN_EN_BLEN             2
+#define LED_CTRL_PATTERN_EN_FLAG             HSL_RW
+
+#define FULL_LIGHT_EN                        "lctrl_fen"
+#define LED_CTRL_FULL_LIGHT_EN_BOFFSET       13
+#define LED_CTRL_FULL_LIGHT_EN_BLEN          1
+#define LED_CTRL_FULL_LIGHT_EN_FLAG          HSL_RW
+
+#define HALF_LIGHT_EN                        "lctrl_hen"
+#define LED_CTRL_HALF_LIGHT_EN_BOFFSET       12
+#define LED_CTRL_HALF_LIGHT_EN_BLEN          1
+#define LED_CTRL_HALF_LIGHT_EN_FLAG          HSL_RW
+
+#define POWERON_LIGHT_EN                     "lctrl_poen"
+#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET    11
+#define LED_CTRL_POWERON_LIGHT_EN_BLEN       1
+#define LED_CTRL_POWERON_LIGHT_EN_FLAG       HSL_RW
+
+#define GE_LIGHT_EN                          "lctrl_geen"
+#define LED_CTRL_GE_LIGHT_EN_BOFFSET         10
+#define LED_CTRL_GE_LIGHT_EN_BLEN            1
+#define LED_CTRL_GE_LIGHT_EN_FLAG            HSL_RW
+
+#define FE_LIGHT_EN                          "lctrl_feen"
+#define LED_CTRL_FE_LIGHT_EN_BOFFSET         9
+#define LED_CTRL_FE_LIGHT_EN_BLEN            1
+#define LED_CTRL_FE_LIGHT_EN_FLAG            HSL_RW
+
+#define ETH_LIGHT_EN                         "lctrl_ethen"
+#define LED_CTRL_ETH_LIGHT_EN_BOFFSET        8
+#define LED_CTRL_ETH_LIGHT_EN_BLEN           1
+#define LED_CTRL_ETH_LIGHT_EN_FLAG           HSL_RW
+
+#define COL_BLINK_EN                         "lctrl_cen"
+#define LED_CTRL_COL_BLINK_EN_BOFFSET        7
+#define LED_CTRL_COL_BLINK_EN_BLEN           1
+#define LED_CTRL_COL_BLINK_EN_FLAG           HSL_RW
+
+#define RX_BLINK_EN                          "lctrl_rxen"
+#define LED_CTRL_RX_BLINK_EN_BOFFSET         5
+#define LED_CTRL_RX_BLINK_EN_BLEN            1
+#define LED_CTRL_RX_BLINK_EN_FLAG            HSL_RW
+
+#define TX_BLINK_EN                          "lctrl_txen"
+#define LED_CTRL_TX_BLINK_EN_BOFFSET         4
+#define LED_CTRL_TX_BLINK_EN_BLEN            1
+#define LED_CTRL_TX_BLINK_EN_FLAG            HSL_RW
+
+#define LINKUP_OVER_EN                       "lctrl_loen"
+#define LED_CTRL_LINKUP_OVER_EN_BOFFSET      2
+#define LED_CTRL_LINKUP_OVER_EN_BLEN         1
+#define LED_CTRL_LINKUP_OVER_EN_FLAG         HSL_RW
+
+#define BLINK_FREQ                           "lctrl_bfreq"
+#define LED_CTRL_BLINK_FREQ_BOFFSET          0
+#define LED_CTRL_BLINK_FREQ_BLEN             2
+#define LED_CTRL_BLINK_FREQ_FLAG             HSL_RW
+
+    /* LED control Register */
+#define LED_PATTERN               "ledpatten"
+#define LED_PATTERN_ID            25
+#define LED_PATTERN_OFFSET        0x00bc
+#define LED_PATTERN_E_LENGTH      4
+#define LED_PATTERN_E_OFFSET      0
+#define LED_PATTERN_NR_E          1
+
+#define P3L1_MODE                           "p3l1_mode"
+#define LED_PATTERN_P3L1_MODE_BOFFSET       24
+#define LED_PATTERN_P3L1_MODE_BLEN          2
+#define LED_PATTERN_P3L1_MODE_FLAG          HSL_RW
+
+#define P3L0_MODE                           "p3l0_mode"
+#define LED_PATTERN_P3L0_MODE_BOFFSET       22
+#define LED_PATTERN_P3L0_MODE_BLEN          2
+#define LED_PATTERN_P3L0_MODE_FLAG          HSL_RW
+
+#define P2L1_MODE                           "p2l1_mode"
+#define LED_PATTERN_P2L1_MODE_BOFFSET       20
+#define LED_PATTERN_P2L1_MODE_BLEN          2
+#define LED_PATTERN_P2L1_MODE_FLAG          HSL_RW
+
+#define P2L0_MODE                           "p2l0_mode"
+#define LED_PATTERN_P2L0_MODE_BOFFSET       18
+#define LED_PATTERN_P2L0_MODE_BLEN          2
+#define LED_PATTERN_P2L0_MODE_FLAG          HSL_RW
+
+#define P1L1_MODE                           "p1l1_mode"
+#define LED_PATTERN_P1L1_MODE_BOFFSET       16
+#define LED_PATTERN_P1L1_MODE_BLEN          2
+#define LED_PATTERN_P1L1_MODE_FLAG          HSL_RW
+
+#define P1L0_MODE                           "p1l0_mode"
+#define LED_PATTERN_P1L0_MODE_BOFFSET       14
+#define LED_PATTERN_P1L0_MODE_BLEN          2
+#define LED_PATTERN_P1L0_MODE_FLAG          HSL_RW
+
+#define M5_MODE                             "m5_mode"
+#define LED_PATTERN_M5_MODE_BOFFSET         10
+#define LED_PATTERN_M5_MODE_BLEN            2
+#define LED_PATTERN_M5_MODE_FLAG            HSL_RW
+
+
+    /* Port Status Register */
+#define PORT_STATUS               "ptsts"
+#define PORT_STATUS_ID            29
+#define PORT_STATUS_OFFSET        0x0100
+#define PORT_STATUS_E_LENGTH      4
+#define PORT_STATUS_E_OFFSET      0x0100
+#define PORT_STATUS_NR_E          6
+
+#define FLOW_LINK_EN                            "ptsts_flen"
+#define PORT_STATUS_FLOW_LINK_EN_BOFFSET        12
+#define PORT_STATUS_FLOW_LINK_EN_BLEN           1
+#define PORT_STATUS_FLOW_LINK_EN_FLAG           HSL_RW
+
+
+#define LINK_ASYN_PAUSE                         "ptsts_lasynp"
+#define PORT_STATUS_LINK_ASYN_PAUSE_BOFFSET     11
+#define PORT_STATUS_LINK_ASYN_PAUSE_BLEN        1
+#define PORT_STATUS_LINK_ASYN_PAUSE_FLAG        HSL_RO
+
+#define LINK_PAUSE                              "ptsts_lpause"
+#define PORT_STATUS_LINK_PAUSE_BOFFSET          10
+#define PORT_STATUS_LINK_PAUSE_BLEN             1
+#define PORT_STATUS_LINK_PAUSE_FLAG             HSL_RO
+
+#define LINK_EN                                 "ptsts_linken"
+#define PORT_STATUS_LINK_EN_BOFFSET             9
+#define PORT_STATUS_LINK_EN_BLEN                1
+#define PORT_STATUS_LINK_EN_FLAG                HSL_RW
+
+#define LINK                                    "ptsts_ptlink"
+#define PORT_STATUS_LINK_BOFFSET                8
+#define PORT_STATUS_LINK_BLEN                   1
+#define PORT_STATUS_LINK_FLAG                   HSL_RO
+
+#define TX_HALF_FLOW_EN
+#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET     7
+#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN        1
+#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG        HSL_RW
+
+#define DUPLEX_MODE                             "ptsts_dupmod"
+#define PORT_STATUS_DUPLEX_MODE_BOFFSET         6
+#define PORT_STATUS_DUPLEX_MODE_BLEN            1
+#define PORT_STATUS_DUPLEX_MODE_FLAG            HSL_RW
+
+#define RX_FLOW_EN                              "ptsts_rxfwen"
+#define PORT_STATUS_RX_FLOW_EN_BOFFSET          5
+#define PORT_STATUS_RX_FLOW_EN_BLEN             1
+#define PORT_STATUS_RX_FLOW_EN_FLAG             HSL_RW
+
+#define TX_FLOW_EN                              "ptsts_txfwen"
+#define PORT_STATUS_TX_FLOW_EN_BOFFSET          4
+#define PORT_STATUS_TX_FLOW_EN_BLEN             1
+#define PORT_STATUS_TX_FLOW_EN_FLAG             HSL_RW
+
+#define RXMAC_EN                                "ptsts_rxmacen"
+#define PORT_STATUS_RXMAC_EN_BOFFSET            3
+#define PORT_STATUS_RXMAC_EN_BLEN               1
+#define PORT_STATUS_RXMAC_EN_FLAG               HSL_RW
+
+#define TXMAC_EN                                "ptsts_txmacen"
+#define PORT_STATUS_TXMAC_EN_BOFFSET            2
+#define PORT_STATUS_TXMAC_EN_BLEN               1
+#define PORT_STATUS_TXMAC_EN_FLAG               HSL_RW
+
+#define SPEED_MODE                              "ptsts_speed"
+#define PORT_STATUS_SPEED_MODE_BOFFSET          0
+#define PORT_STATUS_SPEED_MODE_BLEN             2
+#define PORT_STATUS_SPEED_MODE_FLAG             HSL_RW
+
+
+    /* Port Control Register */
+#define PORT_CTL                  "pctl"
+#define PORT_CTL_ID               30
+#define PORT_CTL_OFFSET           0x0104
+#define PORT_CTL_E_LENGTH         4
+#define PORT_CTL_E_OFFSET         0x0100
+#define PORT_CTL_NR_E             6
+
+#define EAPOL_EN                                "pctl_eapolen"
+#define PORT_CTL_EAPOL_EN_BOFFSET               23
+#define PORT_CTL_EAPOL_EN_BLEN                  1
+#define PORT_CTL_EAPOL_EN_FLAG                  HSL_RW
+
+#define ARP_LEAKY_EN                            "pbvlan_alen"
+#define PORT_CTL_ARP_LEAKY_EN_BOFFSET           22
+#define PORT_CTL_ARP_LEAKY_EN_BLEN              1
+#define PORT_CTL_ARP_LEAKY_EN_FLAG              HSL_RW
+
+#define LEAVE_EN                                "pctl_leaveen"
+#define PORT_CTL_LEAVE_EN_BOFFSET               21
+#define PORT_CTL_LEAVE_EN_BLEN                  1
+#define PORT_CTL_LEAVE_EN_FLAG                  HSL_RW
+
+#define JOIN_EN                                 "pctl_joinen"
+#define PORT_CTL_JOIN_EN_BOFFSET                20
+#define PORT_CTL_JOIN_EN_BLEN                   1
+#define PORT_CTL_JOIN_EN_FLAG                   HSL_RW
+
+#define DHCP_EN                                 "pctl_dhcpen"
+#define PORT_CTL_DHCP_EN_BOFFSET                19
+#define PORT_CTL_DHCP_EN_BLEN                   1
+#define PORT_CTL_DHCP_EN_FLAG                   HSL_RW
+
+#define ING_MIRROR_EN                           "pctl_ingmiren"
+#define PORT_CTL_ING_MIRROR_EN_BOFFSET          17
+#define PORT_CTL_ING_MIRROR_EN_BLEN             1
+#define PORT_CTL_ING_MIRROR_EN_FLAG             HSL_RW
+
+#define EG_MIRROR_EN                            "pctl_egmiren"
+#define PORT_CTL_EG_MIRROR_EN_BOFFSET           16
+#define PORT_CTL_EG_MIRROR_EN_BLEN              1
+#define PORT_CTL_EG_MIRROR_EN_FLAG              HSL_RW
+
+#define LEARN_EN                                "pctl_learnen"
+#define PORT_CTL_LEARN_EN_BOFFSET               14
+#define PORT_CTL_LEARN_EN_BLEN                  1
+#define PORT_CTL_LEARN_EN_FLAG                  HSL_RW
+
+#define MAC_LOOP_BACK                           "pctl_maclp"
+#define PORT_CTL_MAC_LOOP_BACK_BOFFSET          12
+#define PORT_CTL_MAC_LOOP_BACK_BLEN             1
+#define PORT_CTL_MAC_LOOP_BACK_FLAG             HSL_RW
+
+#define HEAD_EN                                 "pctl_headen"
+#define PORT_CTL_HEAD_EN_BOFFSET                11
+#define PORT_CTL_HEAD_EN_BLEN                   1
+#define PORT_CTL_HEAD_EN_FLAG                   HSL_RW
+
+#define IGMP_MLD_EN                             "pctl_imlden"
+#define PORT_CTL_IGMP_MLD_EN_BOFFSET            10
+#define PORT_CTL_IGMP_MLD_EN_BLEN               1
+#define PORT_CTL_IGMP_MLD_EN_FLAG               HSL_RW
+
+#define EG_VLAN_MODE                            "pctl_egvmode"
+#define PORT_CTL_EG_VLAN_MODE_BOFFSET           8
+#define PORT_CTL_EG_VLAN_MODE_BLEN              2
+#define PORT_CTL_EG_VLAN_MODE_FLAG              HSL_RW
+
+#define LEARN_ONE_LOCK                          "pctl_lonelck"
+#define PORT_CTL_LEARN_ONE_LOCK_BOFFSET         7
+#define PORT_CTL_LEARN_ONE_LOCK_BLEN            1
+#define PORT_CTL_LEARN_ONE_LOCK_FLAG            HSL_RW
+
+#define PORT_LOCK_EN                            "pctl_locken"
+#define PORT_CTL_PORT_LOCK_EN_BOFFSET           6
+#define PORT_CTL_PORT_LOCK_EN_BLEN              1
+#define PORT_CTL_PORT_LOCK_EN_FLAG              HSL_RW
+
+#define LOCK_DROP_EN                            "pctl_dropen"
+#define PORT_CTL_LOCK_DROP_EN_BOFFSET           5
+#define PORT_CTL_LOCK_DROP_EN_BLEN              1
+#define PORT_CTL_LOCK_DROP_EN_FLAG              HSL_RW
+
+#define PORT_STATE                              "pctl_pstate"
+#define PORT_CTL_PORT_STATE_BOFFSET             0
+#define PORT_CTL_PORT_STATE_BLEN                3
+#define PORT_CTL_PORT_STATE_FLAG                HSL_RW
+
+
+    /* Port dot1q Register */
+#define PORT_DOT1Q            "pdot1Q"
+#define PORT_DOT1Q_ID         31
+#define PORT_DOT1Q_OFFSET     0x0108
+#define PORT_DOT1Q_E_LENGTH   4
+#define PORT_DOT1Q_E_OFFSET   0x0100
+#define PORT_DOT1Q_NR_E       6
+
+#define ING_PRI                              "pdot1q_ingpri"
+#define PORT_DOT1Q_ING_PRI_BOFFSET           29
+#define PORT_DOT1Q_ING_PRI_BLEN              3
+#define PORT_DOT1Q_ING_PRI_FLAG              HSL_RW
+
+#define FORCE_PVLAN                          "pdot1q_fpvlan"
+#define PORT_DOT1Q_FORCE_PVLAN_BOFFSET       28
+#define PORT_DOT1Q_FORCE_PVLAN_BLEN          1
+#define PORT_DOT1Q_FORCE_PVLAN_FLAG          HSL_RW
+
+#define DEF_VID                              "pdot1q_dcvid"
+#define PORT_DOT1Q_DEF_VID_BOFFSET           16
+#define PORT_DOT1Q_DEF_VID_BLEN              12
+#define PORT_DOT1Q_DEF_VID_FLAG              HSL_RW
+
+#define FORCE_DEF_VID                        "pbot1q_fdvid"
+#define PORT_DOT1Q_FORCE_DEF_VID_BOFFSET     12
+#define PORT_DOT1Q_FORCE_DEF_VID_BLEN        1
+#define PORT_DOT1Q_FORCE_DEF_VID_FLAG        HSL_RW
+
+
+    /* Port Based Vlan Register */
+#define PORT_BASE_VLAN            "pbvlan"
+#define PORT_BASE_VLAN_ID         31
+#define PORT_BASE_VLAN_OFFSET     0x010c
+#define PORT_BASE_VLAN_E_LENGTH   4
+#define PORT_BASE_VLAN_E_OFFSET   0x0100
+#define PORT_BASE_VLAN_NR_E       6
+
+#define DOT1Q_MODE                              "pbvlan_8021q"
+#define PORT_BASE_VLAN_DOT1Q_MODE_BOFFSET       30
+#define PORT_BASE_VLAN_DOT1Q_MODE_BLEN          2
+#define PORT_BASE_VLAN_DOT1Q_MODE_FLAG          HSL_RW
+
+#define COREP_EN                                "pbvlan_corepen"
+#define PORT_BASE_VLAN_COREP_EN_BOFFSET         29
+#define PORT_BASE_VLAN_COREP_EN_BLEN            1
+#define PORT_BASE_VLAN_COREP_EN_FLAG            HSL_RW
+
+#define IN_VLAN_MODE                            "pbvlan_imode"
+#define PORT_BASE_VLAN_IN_VLAN_MODE_BOFFSET     27
+#define PORT_BASE_VLAN_IN_VLAN_MODE_BLEN        2
+#define PORT_BASE_VLAN_IN_VLAN_MODE_FLAG        HSL_RW
+
+#define PRI_PROPAGATION                         "pbvlan_prip"
+#define PORT_BASE_VLAN_PRI_PROPAGATION_BOFFSET  23
+#define PORT_BASE_VLAN_PRI_PROPAGATION_BLEN     1
+#define PORT_BASE_VLAN_PRI_PROPAGATION_FLAG     HSL_RW
+
+#define PORT_VID_MEM                            "pbvlan_pvidm"
+#define PORT_BASE_VLAN_PORT_VID_MEM_BOFFSET     16
+#define PORT_BASE_VLAN_PORT_VID_MEM_BLEN        6
+#define PORT_BASE_VLAN_PORT_VID_MEM_FLAG        HSL_RW
+
+#define UNI_LEAKY_EN                            "pbvlan_ulen"
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_BOFFSET     14
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_BLEN        1
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_FLAG        HSL_RW
+
+#define MUL_LEAKY_EN                            "pbvlan_mlen"
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_BOFFSET     13
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_BLEN        1
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_FLAG        HSL_RW
+
+
+    /* Port Rate Limit0 Register */
+#define RATE_LIMIT0                "rlmt0"
+#define RATE_LIMIT0_ID             32
+#define RATE_LIMIT0_OFFSET         0x0110
+#define RATE_LIMIT0_E_LENGTH       4
+#define RATE_LIMIT0_E_OFFSET       0x0100
+#define RATE_LIMIT0_NR_E           6
+
+#define ADD_RATE_BYTE                          "rlmt_addbyte"
+#define RATE_LIMIT0_ADD_RATE_BYTE_BOFFSET      24
+#define RATE_LIMIT0_ADD_RATE_BYTE_BLEN         8
+#define RATE_LIMIT0_ADD_RATE_BYTE_FLAG         HSL_RW
+
+#define EG_MNG_RATE_EN                         "rlmt_egmngen"
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET     22
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN        1
+#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG        HSL_RW
+
+#define IN_MNG_RATE_EN                         "rlmt_inmngen"
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET     21
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN        1
+#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG        HSL_RW
+
+#define IN_MUL_RATE_EN                         "rlmt_inmulen"
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET     20
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN        1
+#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG        HSL_RW
+
+#define ING_RATE                               "rlmt_ingrate"
+#define RATE_LIMIT0_ING_RATE_BOFFSET           0
+#define RATE_LIMIT0_ING_RATE_BLEN              13
+#define RATE_LIMIT0_ING_RATE_FLAG              HSL_RW
+
+
+    /* Priority Control Register */
+#define PRI_CTL                   "prctl"
+#define PRI_CTL_ID                33
+#define PRI_CTL_OFFSET            0x0114
+#define PRI_CTL_E_LENGTH          4
+#define PRI_CTL_E_OFFSET          0x0100
+#define PRI_CTL_NR_E              6
+
+#define PORT_PRI_EN                             "prctl_ptprien"
+#define PRI_CTL_PORT_PRI_EN_BOFFSET             19
+#define PRI_CTL_PORT_PRI_EN_BLEN                1
+#define PRI_CTL_PORT_PRI_EN_FLAG                HSL_RW
+
+#define DA_PRI_EN                               "prctl_daprien"
+#define PRI_CTL_DA_PRI_EN_BOFFSET               18
+#define PRI_CTL_DA_PRI_EN_BLEN                  1
+#define PRI_CTL_DA_PRI_EN_FLAG                  HSL_RW
+
+#define VLAN_PRI_EN                             "prctl_vprien"
+#define PRI_CTL_VLAN_PRI_EN_BOFFSET             17
+#define PRI_CTL_VLAN_PRI_EN_BLEN                1
+#define PRI_CTL_VLAN_PRI_EN_FLAG                HSL_RW
+
+#define IP_PRI_EN                               "prctl_ipprien"
+#define PRI_CTL_IP_PRI_EN_BOFFSET               16
+#define PRI_CTL_IP_PRI_EN_BLEN                  1
+#define PRI_CTL_IP_PRI_EN_FLAG                  HSL_RW
+
+#define DA_PRI_SEL                              "prctl_dapris"
+#define PRI_CTL_DA_PRI_SEL_BOFFSET              6
+#define PRI_CTL_DA_PRI_SEL_BLEN                 2
+#define PRI_CTL_DA_PRI_SEL_FLAG                 HSL_RW
+
+#define VLAN_PRI_SEL                            "prctl_vpris"
+#define PRI_CTL_VLAN_PRI_SEL_BOFFSET            4
+#define PRI_CTL_VLAN_PRI_SEL_BLEN               2
+#define PRI_CTL_VLAN_PRI_SEL_FLAG               HSL_RW
+
+#define IP_PRI_SEL                              "prctl_ippris"
+#define PRI_CTL_IP_PRI_SEL_BOFFSET              2
+#define PRI_CTL_IP_PRI_SEL_BLEN                 2
+#define PRI_CTL_IP_PRI_SEL_FLAG                 HSL_RW
+
+#define PORT_PRI_SEL                            "prctl_ptpris"
+#define PRI_CTL_PORT_PRI_SEL_BOFFSET            0
+#define PRI_CTL_PORT_PRI_SEL_BLEN               2
+#define PRI_CTL_PORT_PRI_SEL_FLAG               HSL_RW
+
+
+    /* Storm Control Register */
+#define STORM_CTL                 "sctrl"
+#define STORM_CTL_ID                33
+#define STORM_CTL_OFFSET            0x0118
+#define STORM_CTL_E_LENGTH          4
+#define STORM_CTL_E_OFFSET          0x0100
+#define STORM_CTL_NR_E              6
+
+#define UNIT                             "sctrl_unit"
+#define STORM_CTL_UNIT_BOFFSET           24
+#define STORM_CTL_UNIT_BLEN              2
+#define STORM_CTL_UNIT_FLAG              HSL_RW
+
+#define MUL_EN                           "sctrl_mulen"
+#define STORM_CTL_MUL_EN_BOFFSET         10
+#define STORM_CTL_MUL_EN_BLEN            1
+#define STORM_CTL_MUL_EN_FLAG            HSL_RW
+
+#define UNI_EN                           "sctrl_unien"
+#define STORM_CTL_UNI_EN_BOFFSET         9
+#define STORM_CTL_UNI_EN_BLEN            1
+#define STORM_CTL_UNI_EN_FLAG            HSL_RW
+
+#define BRO_EN                           "sctrl_broen"
+#define STORM_CTL_BRO_EN_BOFFSET         8
+#define STORM_CTL_BRO_EN_BLEN            1
+#define STORM_CTL_BRO_EN_FLAG            HSL_RW
+
+#define RATE                             "sctrl_rate"
+#define STORM_CTL_RATE_BOFFSET           0
+#define STORM_CTL_RATE_BLEN              4
+#define STORM_CTL_RATE_FLAG              HSL_RW
+
+
+    /* Queue Control Register */
+#define QUEUE_CTL                   "qctl"
+#define QUEUE_CTL_ID                34
+#define QUEUE_CTL_OFFSET            0x011c
+#define QUEUE_CTL_E_LENGTH          4
+#define QUEUE_CTL_E_OFFSET          0x0100
+#define QUEUE_CTL_NR_E              6
+
+#define PORT_IN_DESC_EN                          "qctl_pdescen"
+#define QUEUE_CTL_PORT_IN_DESC_EN_BOFFSET        28
+#define QUEUE_CTL_PORT_IN_DESC_EN_BLEN           4
+#define QUEUE_CTL_PORT_IN_DESC_EN_FLAG           HSL_RW
+
+#define PORT_DESC_EN                             "qctl_pdescen"
+#define QUEUE_CTL_PORT_DESC_EN_BOFFSET           25
+#define QUEUE_CTL_PORT_DESC_EN_BLEN              1
+#define QUEUE_CTL_PORT_DESC_EN_FLAG              HSL_RW
+
+#define QUEUE_DESC_EN                            "qctl_qdescen"
+#define QUEUE_CTL_QUEUE_DESC_EN_BOFFSET          24
+#define QUEUE_CTL_QUEUE_DESC_EN_BLEN             1
+#define QUEUE_CTL_QUEUE_DESC_EN_FLAG             HSL_RW
+
+#define PORT_DESC_NR                             "qctl_pdscpnr"
+#define QUEUE_CTL_PORT_DESC_NR_BOFFSET           16
+#define QUEUE_CTL_PORT_DESC_NR_BLEN              6
+#define QUEUE_CTL_PORT_DESC_NR_FLAG              HSL_RW
+
+#define QUEUE3_DESC_NR                           "qctl_q3dscpnr"
+#define QUEUE_CTL_QUEUE3_DESC_NR_BOFFSET         12
+#define QUEUE_CTL_QUEUE3_DESC_NR_BLEN            4
+#define QUEUE_CTL_QUEUE3_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE2_DESC_NR                           "qctl_q2dscpnr"
+#define QUEUE_CTL_QUEUE2_DESC_NR_BOFFSET         8
+#define QUEUE_CTL_QUEUE2_DESC_NR_BLEN            4
+#define QUEUE_CTL_QUEUE2_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE1_DESC_NR                           "qctl_q1dscpnr"
+#define QUEUE_CTL_QUEUE1_DESC_NR_BOFFSET         4
+#define QUEUE_CTL_QUEUE1_DESC_NR_BLEN            4
+#define QUEUE_CTL_QUEUE1_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE0_DESC_NR                           "qctl_q0dscpnr"
+#define QUEUE_CTL_QUEUE0_DESC_NR_BOFFSET         0
+#define QUEUE_CTL_QUEUE0_DESC_NR_BLEN            4
+#define QUEUE_CTL_QUEUE0_DESC_NR_FLAG            HSL_RW
+
+
+    /* Port Rate Limit1 Register */
+#define RATE_LIMIT1                "rlmt1"
+#define RATE_LIMIT1_ID             32
+#define RATE_LIMIT1_OFFSET         0x0120
+#define RATE_LIMIT1_E_LENGTH       4
+#define RATE_LIMIT1_E_OFFSET       0x0100
+#define RATE_LIMIT1_NR_E           6
+
+#define EG_RATE                              "rlmt_egrate"
+#define RATE_LIMIT1_EG_RATE_BOFFSET          0
+#define RATE_LIMIT1_EG_RATE_BLEN             13
+#define RATE_LIMIT1_EG_RATE_FLAG             HSL_RW
+
+
+    /* Port Rate Limit3 Register */
+#define RATE_LIMIT3                "rlmt3"
+#define RATE_LIMIT3_ID             32
+#define RATE_LIMIT3_OFFSET         0x0128
+#define RATE_LIMIT3_E_LENGTH       4
+#define RATE_LIMIT3_E_OFFSET       0x0100
+#define RATE_LIMIT3_NR_E           6
+
+#define EG_CBS                                "rlmt_egcbs"
+#define RATE_LIMIT3_EG_CBS_BOFFSET            16
+#define RATE_LIMIT3_EG_CBS_BLEN               2
+#define RATE_LIMIT3_EG_CBS_FLAG               HSL_RW
+
+#define EG_TS                                  "rlmt_egts"
+#define RATE_LIMIT3_EG_TS_BOFFSET              0
+#define RATE_LIMIT3_EG_TS_BLEN                 3
+#define RATE_LIMIT3_EG_TS_FLAG                 HSL_RW
+
+
+    /* Weight Round Robin Register */
+#define WRR_CTRL                                "wrrc"
+#define WRR_CTRL_ID                             32
+#define WRR_CTRL_OFFSET                         0x012c
+#define WRR_CTRL_E_LENGTH                       4
+#define WRR_CTRL_E_OFFSET                       0x0100
+#define WRR_CTRL_NR_E                           6
+
+#define SCH_MODE                                "wrrc_mode"
+#define WRR_CTRL_SCH_MODE_BOFFSET               29
+#define WRR_CTRL_SCH_MODE_BLEN                  2
+#define WRR_CTRL_SCH_MODE_FLAG                  HSL_RW
+
+
+    /* mib memory info */
+#define MIB_RXBROAD                       "RxBroad"
+#define MIB_RXBROAD_ID                    34
+#define MIB_RXBROAD_OFFSET                0x20000
+#define MIB_RXBROAD_E_LENGTH              4
+#define MIB_RXBROAD_E_OFFSET              0x100
+#define MIB_RXBROAD_NR_E                  6
+
+#define MIB_RXPAUSE                       "RxPause"
+#define MIB_RXPAUSE_ID                    35
+#define MIB_RXPAUSE_OFFSET                0x20004
+#define MIB_RXPAUSE_E_LENGTH              4
+#define MIB_RXPAUSE_E_OFFSET              0x100
+#define MIB_RXPAUSE_NR_E                  6
+
+#define MIB_RXMULTI                       "RxMulti"
+#define MIB_RXMULTI_ID                    36
+#define MIB_RXMULTI_OFFSET                0x20008
+#define MIB_RXMULTI_E_LENGTH              4
+#define MIB_RXMULTI_E_OFFSET              0x100
+#define MIB_RXMULTI_NR_E                  6
+
+#define MIB_RXFCSERR                      "RxFcsErr"
+#define MIB_RXFCSERR_ID                   37
+#define MIB_RXFCSERR_OFFSET               0x2000c
+#define MIB_RXFCSERR_E_LENGTH             4
+#define MIB_RXFCSERR_E_OFFSET             0x100
+#define MIB_RXFCSERR_NR_E                 6
+
+#define MIB_RXALLIGNERR                   "RxAllignErr"
+#define MIB_RXALLIGNERR_ID                38
+#define MIB_RXALLIGNERR_OFFSET            0x20010
+#define MIB_RXALLIGNERR_E_LENGTH          4
+#define MIB_RXALLIGNERR_E_OFFSET          0x100
+#define MIB_RXALLIGNERR_NR_E              6
+
+#define MIB_RXRUNT                        "RxRunt"
+#define MIB_RXRUNT_ID                     39
+#define MIB_RXRUNT_OFFSET                 0x20014
+#define MIB_RXRUNT_E_LENGTH               4
+#define MIB_RXRUNT_E_OFFSET               0x100
+#define MIB_RXRUNT_NR_E                   6
+
+#define MIB_RXFRAGMENT                    "RxFragment"
+#define MIB_RXFRAGMENT_ID                 40
+#define MIB_RXFRAGMENT_OFFSET             0x20018
+#define MIB_RXFRAGMENT_E_LENGTH           4
+#define MIB_RXFRAGMENT_E_OFFSET           0x100
+#define MIB_RXFRAGMENT_NR_E               6
+
+#define MIB_RX64BYTE                      "Rx64Byte"
+#define MIB_RX64BYTE_ID                   41
+#define MIB_RX64BYTE_OFFSET               0x2001c
+#define MIB_RX64BYTE_E_LENGTH             4
+#define MIB_RX64BYTE_E_OFFSET             0x100
+#define MIB_RX64BYTE_NR_E                 6
+
+#define MIB_RX128BYTE                     "Rx128Byte"
+#define MIB_RX128BYTE_ID                  42
+#define MIB_RX128BYTE_OFFSET              0x20020
+#define MIB_RX128BYTE_E_LENGTH            4
+#define MIB_RX128BYTE_E_OFFSET            0x100
+#define MIB_RX128BYTE_NR_E                6
+
+#define MIB_RX256BYTE                     "Rx256Byte"
+#define MIB_RX256BYTE_ID                  43
+#define MIB_RX256BYTE_OFFSET              0x20024
+#define MIB_RX256BYTE_E_LENGTH            4
+#define MIB_RX256BYTE_E_OFFSET            0x100
+#define MIB_RX256BYTE_NR_E                6
+
+#define MIB_RX512BYTE                     "Rx512Byte"
+#define MIB_RX512BYTE_ID                  44
+#define MIB_RX512BYTE_OFFSET              0x20028
+#define MIB_RX512BYTE_E_LENGTH            4
+#define MIB_RX512BYTE_E_OFFSET            0x100
+#define MIB_RX512BYTE_NR_E                6
+
+#define MIB_RX1024BYTE                    "Rx1024Byte"
+#define MIB_RX1024BYTE_ID                 45
+#define MIB_RX1024BYTE_OFFSET             0x2002c
+#define MIB_RX1024BYTE_E_LENGTH           4
+#define MIB_RX1024BYTE_E_OFFSET           0x100
+#define MIB_RX1024BYTE_NR_E               6
+
+#define MIB_RX1518BYTE                    "Rx1518Byte"
+#define MIB_RX1518BYTE_ID                 45
+#define MIB_RX1518BYTE_OFFSET             0x20030
+#define MIB_RX1518BYTE_E_LENGTH           4
+#define MIB_RX1518BYTE_E_OFFSET           0x100
+#define MIB_RX1518BYTE_NR_E               6
+
+#define MIB_RXMAXBYTE                     "RxMaxByte"
+#define MIB_RXMAXBYTE_ID                  46
+#define MIB_RXMAXBYTE_OFFSET              0x20034
+#define MIB_RXMAXBYTE_E_LENGTH            4
+#define MIB_RXMAXBYTE_E_OFFSET            0x100
+#define MIB_RXMAXBYTE_NR_E                6
+
+#define MIB_RXTOOLONG                     "RxTooLong"
+#define MIB_RXTOOLONG_ID                  47
+#define MIB_RXTOOLONG_OFFSET              0x20038
+#define MIB_RXTOOLONG_E_LENGTH            4
+#define MIB_RXTOOLONG_E_OFFSET            0x100
+#define MIB_RXTOOLONG_NR_E                6
+
+#define MIB_RXGOODBYTE_LO                 "RxGoodByteLo"
+#define MIB_RXGOODBYTE_LO_ID              48
+#define MIB_RXGOODBYTE_LO_OFFSET          0x2003c
+#define MIB_RXGOODBYTE_LO_E_LENGTH        4
+#define MIB_RXGOODBYTE_LO_E_OFFSET        0x100
+#define MIB_RXGOODBYTE_LO_NR_E            6
+
+#define MIB_RXGOODBYTE_HI                 "RxGoodByteHi"
+#define MIB_RXGOODBYTE_HI_ID              49
+#define MIB_RXGOODBYTE_HI_OFFSET          0x20040
+#define MIB_RXGOODBYTE_HI_E_LENGTH        4
+#define MIB_RXGOODBYTE_HI_E_OFFSET        0x100
+#define MIB_RXGOODBYTE_HI_NR_E            6
+
+#define MIB_RXBADBYTE_LO                  "RxBadByteLo"
+#define MIB_RXBADBYTE_LO_ID               50
+#define MIB_RXBADBYTE_LO_OFFSET           0x20044
+#define MIB_RXBADBYTE_LO_E_LENGTH         4
+#define MIB_RXBADBYTE_LO_E_OFFSET         0x100
+#define MIB_RXBADBYTE_LO_NR_E             6
+
+#define MIB_RXBADBYTE_HI                  "RxBadByteHi"
+#define MIB_RXBADBYTE_HI_ID               51
+#define MIB_RXBADBYTE_HI_OFFSET           0x20048
+#define MIB_RXBADBYTE_HI_E_LENGTH         4
+#define MIB_RXBADBYTE_HI_E_OFFSET         0x100
+#define MIB_RXBADBYTE_HI_NR_E             6
+
+#define MIB_RXOVERFLOW                    "RxOverFlow"
+#define MIB_RXOVERFLOW_ID                 52
+#define MIB_RXOVERFLOW_OFFSET             0x2004c
+#define MIB_RXOVERFLOW_E_LENGTH           4
+#define MIB_RXOVERFLOW_E_OFFSET           0x100
+#define MIB_RXOVERFLOW_NR_E               6
+
+#define MIB_FILTERED                      "Filtered"
+#define MIB_FILTERED_ID                   53
+#define MIB_FILTERED_OFFSET               0x20050
+#define MIB_FILTERED_E_LENGTH             4
+#define MIB_FILTERED_E_OFFSET             0x100
+#define MIB_FILTERED_NR_E                 6
+
+#define MIB_TXBROAD                       "TxBroad"
+#define MIB_TXBROAD_ID                    54
+#define MIB_TXBROAD_OFFSET                0x20054
+#define MIB_TXBROAD_E_LENGTH              4
+#define MIB_TXBROAD_E_OFFSET              0x100
+#define MIB_TXBROAD_NR_E                  6
+
+#define MIB_TXPAUSE                       "TxPause"
+#define MIB_TXPAUSE_ID                    55
+#define MIB_TXPAUSE_OFFSET                0x20058
+#define MIB_TXPAUSE_E_LENGTH              4
+#define MIB_TXPAUSE_E_OFFSET              0x100
+#define MIB_TXPAUSE_NR_E                  6
+
+#define MIB_TXMULTI                       "TxMulti"
+#define MIB_TXMULTI_ID                    56
+#define MIB_TXMULTI_OFFSET                0x2005c
+#define MIB_TXMULTI_E_LENGTH              4
+#define MIB_TXMULTI_E_OFFSET              0x100
+#define MIB_TXMULTI_NR_E                  6
+
+#define MIB_TXUNDERRUN                    "TxUnderRun"
+#define MIB_TXUNDERRUN_ID                 57
+#define MIB_TXUNDERRUN_OFFSET             0x20060
+#define MIB_TXUNDERRUN_E_LENGTH           4
+#define MIB_TXUNDERRUN_E_OFFSET           0x100
+#define MIB_TXUNDERRUN_NR_E               6
+
+#define MIB_TX64BYTE                      "Tx64Byte"
+#define MIB_TX64BYTE_ID                   58
+#define MIB_TX64BYTE_OFFSET               0x20064
+#define MIB_TX64BYTE_E_LENGTH             4
+#define MIB_TX64BYTE_E_OFFSET             0x100
+#define MIB_TX64BYTE_NR_E                 6
+
+#define MIB_TX128BYTE                     "Tx128Byte"
+#define MIB_TX128BYTE_ID                  59
+#define MIB_TX128BYTE_OFFSET              0x20068
+#define MIB_TX128BYTE_E_LENGTH            4
+#define MIB_TX128BYTE_E_OFFSET            0x100
+#define MIB_TX128BYTE_NR_E                6
+
+#define MIB_TX256BYTE                     "Tx256Byte"
+#define MIB_TX256BYTE_ID                  60
+#define MIB_TX256BYTE_OFFSET              0x2006c
+#define MIB_TX256BYTE_E_LENGTH            4
+#define MIB_TX256BYTE_E_OFFSET            0x100
+#define MIB_TX256BYTE_NR_E                6
+
+#define MIB_TX512BYTE                     "Tx512Byte"
+#define MIB_TX512BYTE_ID                  61
+#define MIB_TX512BYTE_OFFSET              0x20070
+#define MIB_TX512BYTE_E_LENGTH            4
+#define MIB_TX512BYTE_E_OFFSET            0x100
+#define MIB_TX512BYTE_NR_E                6
+
+#define MIB_TX1024BYTE                    "Tx1024Byte"
+#define MIB_TX1024BYTE_ID                 62
+#define MIB_TX1024BYTE_OFFSET             0x20074
+#define MIB_TX1024BYTE_E_LENGTH           4
+#define MIB_TX1024BYTE_E_OFFSET           0x100
+#define MIB_TX1024BYTE_NR_E               6
+
+#define MIB_TX1518BYTE                    "Tx1518Byte"
+#define MIB_TX1518BYTE_ID                 62
+#define MIB_TX1518BYTE_OFFSET             0x20078
+#define MIB_TX1518BYTE_E_LENGTH           4
+#define MIB_TX1518BYTE_E_OFFSET           0x100
+#define MIB_TX1518BYTE_NR_E               6
+
+#define MIB_TXMAXBYTE                     "TxMaxByte"
+#define MIB_TXMAXBYTE_ID                  63
+#define MIB_TXMAXBYTE_OFFSET              0x2007c
+#define MIB_TXMAXBYTE_E_LENGTH            4
+#define MIB_TXMAXBYTE_E_OFFSET            0x100
+#define MIB_TXMAXBYTE_NR_E                6
+
+#define MIB_TXOVERSIZE                    "TxOverSize"
+#define MIB_TXOVERSIZE_ID                 64
+#define MIB_TXOVERSIZE_OFFSET             0x20080
+#define MIB_TXOVERSIZE_E_LENGTH           4
+#define MIB_TXOVERSIZE_E_OFFSET           0x100
+#define MIB_TXOVERSIZE_NR_E               6
+
+#define MIB_TXBYTE_LO                     "TxByteLo"
+#define MIB_TXBYTE_LO_ID                  65
+#define MIB_TXBYTE_LO_OFFSET              0x20084
+#define MIB_TXBYTE_LO_E_LENGTH            4
+#define MIB_TXBYTE_LO_E_OFFSET            0x100
+#define MIB_TXBYTE_LO_NR_E                6
+
+#define MIB_TXBYTE_HI                     "TxByteHi"
+#define MIB_TXBYTE_HI_ID                  66
+#define MIB_TXBYTE_HI_OFFSET              0x20088
+#define MIB_TXBYTE_HI_E_LENGTH            4
+#define MIB_TXBYTE_HI_E_OFFSET            0x100
+#define MIB_TXBYTE_HI_NR_E                6
+
+#define MIB_TXCOLLISION                   "TxCollision"
+#define MIB_TXCOLLISION_ID                67
+#define MIB_TXCOLLISION_OFFSET            0x2008c
+#define MIB_TXCOLLISION_E_LENGTH          4
+#define MIB_TXCOLLISION_E_OFFSET          0x100
+#define MIB_TXCOLLISION_NR_E              6
+
+#define MIB_TXABORTCOL                    "TxAbortCol"
+#define MIB_TXABORTCOL_ID                 68
+#define MIB_TXABORTCOL_OFFSET             0x20090
+#define MIB_TXABORTCOL_E_LENGTH           4
+#define MIB_TXABORTCOL_E_OFFSET           0x100
+#define MIB_TXABORTCOL_NR_E               6
+
+#define MIB_TXMULTICOL                    "TxMultiCol"
+#define MIB_TXMULTICOL_ID                 69
+#define MIB_TXMULTICOL_OFFSET             0x20094
+#define MIB_TXMULTICOL_E_LENGTH           4
+#define MIB_TXMULTICOL_E_OFFSET           0x100
+#define MIB_TXMULTICOL_NR_E               6
+
+#define MIB_TXSINGALCOL                   "TxSingalCol"
+#define MIB_TXSINGALCOL_ID                70
+#define MIB_TXSINGALCOL_OFFSET            0x20098
+#define MIB_TXSINGALCOL_E_LENGTH          4
+#define MIB_TXSINGALCOL_E_OFFSET          0x100
+#define MIB_TXSINGALCOL_NR_E              6
+
+#define MIB_TXEXCDEFER                    "TxExcDefer"
+#define MIB_TXEXCDEFER_ID                 71
+#define MIB_TXEXCDEFER_OFFSET             0x2009c
+#define MIB_TXEXCDEFER_E_LENGTH           4
+#define MIB_TXEXCDEFER_E_OFFSET           0x100
+#define MIB_TXEXCDEFER_NR_E               6
+
+#define MIB_TXDEFER                       "TxDefer"
+#define MIB_TXDEFER_ID                    72
+#define MIB_TXDEFER_OFFSET                0x200a0
+#define MIB_TXDEFER_E_LENGTH              4
+#define MIB_TXDEFER_E_OFFSET              0x100
+#define MIB_TXDEFER_NR_E                  6
+
+#define MIB_TXLATECOL                     "TxLateCol"
+#define MIB_TXLATECOL_ID                  73
+#define MIB_TXLATECOL_OFFSET              0x200a4
+#define MIB_TXLATECOL_E_LENGTH            4
+#define MIB_TXLATECOL_E_OFFSET            0x100
+#define MIB_TXLATECOL_NR_E                6
+
+
+#define PPPOE_SESSION                              "pppoes"
+#define PPPOE_SESSION_ID                           13
+#define PPPOE_SESSION_OFFSET                       0x59100
+#define PPPOE_SESSION_E_LENGTH                     4
+#define PPPOE_SESSION_E_OFFSET                     0x4
+#define PPPOE_SESSION_NR_E                         16
+
+#define ENTRY_VALID                                "pppoes_v"
+#define PPPOE_SESSION_ENTRY_VALID_BOFFSET          19
+#define PPPOE_SESSION_ENTRY_VALID_BLEN             1
+#define PPPOE_SESSION_ENTRY_VALID_FLAG             HSL_RW
+
+#define STRIP_EN                                   "pppoes_s"
+#define PPPOE_SESSION_STRIP_EN_BOFFSET             16
+#define PPPOE_SESSION_STRIP_EN_BLEN                1
+#define PPPOE_SESSION_STRIP_EN_FLAG                HSL_RW
+
+#define SEESION_ID                                 "pppoes_id"
+#define PPPOE_SESSION_SEESION_ID_BOFFSET           0
+#define PPPOE_SESSION_SEESION_ID_BLEN              16
+#define PPPOE_SESSION_SEESION_ID_FLAG              HSL_RW
+
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _HORUS_REG_H_ */
+
diff --git a/qca-ssdk/include/hsl/horus/horus_reg_access.h b/qca-ssdk/include/hsl/horus/horus_reg_access.h
new file mode 100755
index 0000000..a41ef6c
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_reg_access.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HORUS_REG_ACCESS_H_
+#define _HORUS_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "sw.h"
+
+    sw_error_t
+    horus_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+                  a_uint32_t reg, a_uint16_t * value);
+
+    sw_error_t
+    horus_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+                  a_uint32_t reg, a_uint16_t value);
+
+    sw_error_t
+    horus_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                  a_uint32_t value_len);
+
+    sw_error_t
+    horus_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                  a_uint32_t value_len);
+
+    sw_error_t
+    horus_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                        a_uint32_t bit_offset, a_uint32_t field_len,
+                        a_uint8_t value[], a_uint32_t value_len);
+
+    sw_error_t
+    horus_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                        a_uint32_t bit_offset, a_uint32_t field_len,
+                        const a_uint8_t value[], a_uint32_t value_len);
+
+    sw_error_t
+    horus_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode);
+
+    sw_error_t
+    horus_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HORUS_REG_ACCESS_H_ */
+
diff --git a/qca-ssdk/include/hsl/horus/horus_stp.h b/qca-ssdk/include/hsl/horus/horus_stp.h
new file mode 100755
index 0000000..ed22814
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_stp.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_stp HORUS_STP
+ * @{
+ */
+#ifndef _HORUS_STP_H_
+#define _HORUS_STP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_stp.h"
+
+    sw_error_t horus_stp_init(a_uint32_t dev_id);
+
+#ifdef IN_STP
+#define HORUS_STP_INIT(rv, dev_id) \
+    { \
+        rv = horus_stp_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define HORUS_STP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    horus_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                             fal_port_t port_id, fal_stp_state_t state);
+
+
+    HSL_LOCAL sw_error_t
+    horus_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                             fal_port_t port_id, fal_stp_state_t * state);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _HORUS_STP_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/horus/horus_vlan.h b/qca-ssdk/include/hsl/horus/horus_vlan.h
new file mode 100755
index 0000000..9429131
--- /dev/null
+++ b/qca-ssdk/include/hsl/horus/horus_vlan.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_vlan HORUS_VLAN
+ * @{
+ */
+#ifndef _HORUS_VLAN_H_
+#define _HORUS_VLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_vlan.h"
+
+    sw_error_t
+    horus_vlan_init(a_uint32_t dev_id);
+
+#ifdef IN_VLAN
+#define HORUS_VLAN_INIT(rv, dev_id) \
+    { \
+        rv = horus_vlan_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define HORUS_VLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    horus_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry);
+
+
+    HSL_LOCAL sw_error_t
+    horus_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+    HSL_LOCAL sw_error_t
+    horus_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+    HSL_LOCAL sw_error_t
+    horus_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+    HSL_LOCAL sw_error_t
+    horus_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                             fal_pbmp_t member, fal_pbmp_t u_member);
+
+
+    HSL_LOCAL sw_error_t
+    horus_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HORUS_VLAN_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/hppe/hppe_acl.h b/qca-ssdk/include/hsl/hppe/hppe_acl.h
new file mode 100755
index 0000000..ec2bb13
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_acl.h
@@ -0,0 +1,1256 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_ACL_H_
+#define _HPPE_ACL_H_
+
+#define IPO_RULE_REG_MAX_ENTRY	512
+#define IPO_MASK_REG_MAX_ENTRY	512
+#define RULE_EXT_1_REG_MAX_ENTRY	64
+#define RULE_EXT_2_REG_MAX_ENTRY	64
+#define RULE_EXT_4_REG_MAX_ENTRY	64
+#define IPO_ACTION_MAX_ENTRY	512
+#define IPO_CNT_TBL_MAX_ENTRY	512
+
+sw_error_t
+hppe_non_ip_udf0_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_non_ip_udf0_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_non_ip_udf1_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_non_ip_udf1_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_non_ip_udf2_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_non_ip_udf2_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_non_ip_udf3_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_non_ip_udf3_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv4_udf0_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv4_udf0_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv4_udf1_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv4_udf1_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv4_udf2_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv4_udf2_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv4_udf3_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv4_udf3_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv6_udf0_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv6_udf0_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv6_udf1_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv6_udf1_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv6_udf2_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv6_udf2_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv6_udf3_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_ipv6_udf3_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value);
+
+sw_error_t
+hppe_non_ip_udf0_ctrl_reg_udf0_base_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_non_ip_udf0_ctrl_reg_udf0_base_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_non_ip_udf0_ctrl_reg_udf0_offset_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_non_ip_udf0_ctrl_reg_udf0_offset_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_non_ip_udf1_ctrl_reg_udf1_base_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_non_ip_udf1_ctrl_reg_udf1_base_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_non_ip_udf1_ctrl_reg_udf1_offset_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_non_ip_udf1_ctrl_reg_udf1_offset_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_non_ip_udf2_ctrl_reg_udf2_offset_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_non_ip_udf2_ctrl_reg_udf2_offset_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_non_ip_udf2_ctrl_reg_udf2_base_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_non_ip_udf2_ctrl_reg_udf2_base_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_non_ip_udf3_ctrl_reg_udf3_base_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_non_ip_udf3_ctrl_reg_udf3_base_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_non_ip_udf3_ctrl_reg_udf3_offset_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_non_ip_udf3_ctrl_reg_udf3_offset_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv4_udf0_ctrl_reg_udf0_base_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv4_udf0_ctrl_reg_udf0_base_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv4_udf0_ctrl_reg_udf0_offset_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv4_udf0_ctrl_reg_udf0_offset_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv4_udf1_ctrl_reg_udf1_base_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv4_udf1_ctrl_reg_udf1_base_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv4_udf1_ctrl_reg_udf1_offset_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv4_udf1_ctrl_reg_udf1_offset_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv4_udf2_ctrl_reg_udf2_offset_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv4_udf2_ctrl_reg_udf2_offset_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv4_udf2_ctrl_reg_udf2_base_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv4_udf2_ctrl_reg_udf2_base_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv4_udf3_ctrl_reg_udf3_base_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv4_udf3_ctrl_reg_udf3_base_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv4_udf3_ctrl_reg_udf3_offset_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv4_udf3_ctrl_reg_udf3_offset_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv6_udf0_ctrl_reg_udf0_base_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv6_udf0_ctrl_reg_udf0_base_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv6_udf0_ctrl_reg_udf0_offset_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv6_udf0_ctrl_reg_udf0_offset_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv6_udf1_ctrl_reg_udf1_base_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv6_udf1_ctrl_reg_udf1_base_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv6_udf1_ctrl_reg_udf1_offset_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv6_udf1_ctrl_reg_udf1_offset_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv6_udf2_ctrl_reg_udf2_offset_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv6_udf2_ctrl_reg_udf2_offset_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv6_udf2_ctrl_reg_udf2_base_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv6_udf2_ctrl_reg_udf2_base_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv6_udf3_ctrl_reg_udf3_base_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv6_udf3_ctrl_reg_udf3_base_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipv6_udf3_ctrl_reg_udf3_offset_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipv6_udf3_ctrl_reg_udf3_offset_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipo_rule_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_rule_reg_u *value);
+
+sw_error_t
+hppe_ipo_rule_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_rule_reg_u *value);
+
+sw_error_t
+hppe_ipo_mask_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_mask_reg_u *value);
+
+sw_error_t
+hppe_ipo_mask_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_mask_reg_u *value);
+
+sw_error_t
+hppe_rule_ext_1_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rule_ext_1_reg_u *value);
+
+sw_error_t
+hppe_rule_ext_1_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rule_ext_1_reg_u *value);
+
+sw_error_t
+hppe_rule_ext_2_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rule_ext_2_reg_u *value);
+
+sw_error_t
+hppe_rule_ext_2_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rule_ext_2_reg_u *value);
+
+sw_error_t
+hppe_rule_ext_4_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rule_ext_4_reg_u *value);
+
+sw_error_t
+hppe_rule_ext_4_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rule_ext_4_reg_u *value);
+
+sw_error_t
+hppe_ipo_dbg_addr_reg_get(
+		a_uint32_t dev_id,
+		union ipo_dbg_addr_reg_u *value);
+
+sw_error_t
+hppe_ipo_dbg_addr_reg_set(
+		a_uint32_t dev_id,
+		union ipo_dbg_addr_reg_u *value);
+
+sw_error_t
+hppe_ipo_dbg_data_reg_get(
+		a_uint32_t dev_id,
+		union ipo_dbg_data_reg_u *value);
+
+sw_error_t
+hppe_ipo_dbg_data_reg_set(
+		a_uint32_t dev_id,
+		union ipo_dbg_data_reg_u *value);
+
+sw_error_t
+hppe_ipo_spare_reg_reg_get(
+		a_uint32_t dev_id,
+		union ipo_spare_reg_reg_u *value);
+
+sw_error_t
+hppe_ipo_spare_reg_reg_set(
+		a_uint32_t dev_id,
+		union ipo_spare_reg_reg_u *value);
+
+sw_error_t
+hppe_ipo_glb_hit_counter_reg_get(
+		a_uint32_t dev_id,
+		union ipo_glb_hit_counter_reg_u *value);
+
+sw_error_t
+hppe_ipo_glb_hit_counter_reg_set(
+		a_uint32_t dev_id,
+		union ipo_glb_hit_counter_reg_u *value);
+
+sw_error_t
+hppe_ipo_glb_miss_counter_reg_get(
+		a_uint32_t dev_id,
+		union ipo_glb_miss_counter_reg_u *value);
+
+sw_error_t
+hppe_ipo_glb_miss_counter_reg_set(
+		a_uint32_t dev_id,
+		union ipo_glb_miss_counter_reg_u *value);
+
+sw_error_t
+hppe_ipo_glb_bypass_counter_reg_get(
+		a_uint32_t dev_id,
+		union ipo_glb_bypass_counter_reg_u *value);
+
+sw_error_t
+hppe_ipo_glb_bypass_counter_reg_set(
+		a_uint32_t dev_id,
+		union ipo_glb_bypass_counter_reg_u *value);
+
+sw_error_t
+hppe_ipo_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_cnt_tbl_u *value);
+
+sw_error_t
+hppe_ipo_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_cnt_tbl_u *value);
+
+sw_error_t
+hppe_ipo_cnt_tbl_hit_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_ipo_cnt_tbl_hit_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_ipo_cnt_tbl_hit_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_cnt_tbl_hit_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+sw_error_t
+hppe_ipo_rule_reg_src_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_rule_reg_src_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_rule_reg_inverse_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_rule_reg_inverse_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_rule_reg_rule_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_rule_reg_rule_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_rule_reg_src_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_rule_reg_src_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_rule_reg_range_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_rule_reg_range_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_rule_reg_post_routing_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_rule_reg_post_routing_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_rule_reg_fake_mac_header_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_rule_reg_fake_mac_header_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_rule_reg_res_chain_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_rule_reg_res_chain_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_rule_reg_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_rule_reg_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_rule_reg_rule_field_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_ipo_rule_reg_rule_field_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_ipo_mask_reg_maskfield_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_ipo_mask_reg_maskfield_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_3_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_3_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rule_ext_2_reg_ext4_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rule_ext_2_reg_ext4_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rule_ext_2_reg_ext4_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rule_ext_2_reg_ext4_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rule_ext_4_reg_ext8_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rule_ext_4_reg_ext8_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_dbg_addr_reg_ipo_dbg_addr_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipo_dbg_addr_reg_ipo_dbg_addr_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipo_dbg_data_reg_ipo_dbg_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipo_dbg_data_reg_ipo_dbg_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipo_spare_reg_reg_spare_reg_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipo_spare_reg_reg_spare_reg_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipo_glb_hit_counter_reg_hit_count_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipo_glb_hit_counter_reg_hit_count_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipo_glb_miss_counter_reg_miss_count_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipo_glb_miss_counter_reg_miss_count_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipo_glb_bypass_counter_reg_bypass_count_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipo_glb_bypass_counter_reg_bypass_count_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ipo_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_action_u *value);
+
+sw_error_t
+hppe_ipo_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_action_u *value);
+
+sw_error_t
+hppe_ipo_action_mirror_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_mirror_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_ctag_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_ctag_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_int_dp_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_int_dp_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_enqueue_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_enqueue_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_stag_pcp_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_stag_pcp_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_dscp_tc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_dscp_tc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_cpu_code_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_cpu_code_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_stag_dei_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_stag_dei_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_ctag_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_ctag_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_dest_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_dest_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_svid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_svid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_dest_info_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_dest_info_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_policer_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_policer_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_int_dp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_int_dp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_ctag_pcp_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_ctag_pcp_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_metadata_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_metadata_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_enqueue_pri_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_enqueue_pri_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_stag_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_stag_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_fwd_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_fwd_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_bypass_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_bypass_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_ctag_dei_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_ctag_dei_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_policer_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_policer_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_ctag_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_ctag_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_stag_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_stag_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_syn_toggle_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_syn_toggle_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_service_code_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_service_code_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_qid_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_qid_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_service_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_service_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_cvid_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_cvid_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_cvid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_cvid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_svid_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_svid_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_cpu_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_cpu_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_dscp_tc_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_dscp_tc_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_qid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_qid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipo_action_stag_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipo_action_stag_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_acl_reg.h b/qca-ssdk/include/hsl/hppe/hppe_acl_reg.h
new file mode 100755
index 0000000..db18ea4
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_acl_reg.h
@@ -0,0 +1,842 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_ACL_REG_H
+#define HPPE_ACL_REG_H
+
+/*[register] NON_IP_UDF0_CTRL_REG*/
+#define NON_IP_UDF0_CTRL_REG
+#define NON_IP_UDF0_CTRL_REG_ADDRESS 0x38
+#define NON_IP_UDF0_CTRL_REG_NUM     1
+#define NON_IP_UDF0_CTRL_REG_INC     0x4
+#define NON_IP_UDF0_CTRL_REG_TYPE    REG_TYPE_RW
+#define NON_IP_UDF0_CTRL_REG_DEFAULT 0x0
+	/*[field] UDF0_BASE*/
+	#define NON_IP_UDF0_CTRL_REG_UDF0_BASE
+	#define NON_IP_UDF0_CTRL_REG_UDF0_BASE_OFFSET  0
+	#define NON_IP_UDF0_CTRL_REG_UDF0_BASE_LEN     2
+	#define NON_IP_UDF0_CTRL_REG_UDF0_BASE_DEFAULT 0x0
+	/*[field] UDF0_OFFSET*/
+	#define NON_IP_UDF0_CTRL_REG_UDF0_OFFSET
+	#define NON_IP_UDF0_CTRL_REG_UDF0_OFFSET_OFFSET  8
+	#define NON_IP_UDF0_CTRL_REG_UDF0_OFFSET_LEN     6
+	#define NON_IP_UDF0_CTRL_REG_UDF0_OFFSET_DEFAULT 0x0
+
+struct udf_ctrl_reg {
+	a_uint32_t  udf_base:2;
+	a_uint32_t  _reserved0:6;
+	a_uint32_t  udf_offset:6;
+	a_uint32_t  _reserved1:18;
+};
+
+union udf_ctrl_reg_u {
+	a_uint32_t val;
+	struct udf_ctrl_reg bf;
+};
+
+/*[register] NON_IP_UDF1_CTRL_REG*/
+#define NON_IP_UDF1_CTRL_REG
+#define NON_IP_UDF1_CTRL_REG_ADDRESS 0x3c
+#define NON_IP_UDF1_CTRL_REG_NUM     1
+#define NON_IP_UDF1_CTRL_REG_INC     0x4
+#define NON_IP_UDF1_CTRL_REG_TYPE    REG_TYPE_RW
+#define NON_IP_UDF1_CTRL_REG_DEFAULT 0x0
+	/*[field] UDF1_BASE*/
+	#define NON_IP_UDF1_CTRL_REG_UDF1_BASE
+	#define NON_IP_UDF1_CTRL_REG_UDF1_BASE_OFFSET  0
+	#define NON_IP_UDF1_CTRL_REG_UDF1_BASE_LEN     2
+	#define NON_IP_UDF1_CTRL_REG_UDF1_BASE_DEFAULT 0x0
+	/*[field] UDF1_OFFSET*/
+	#define NON_IP_UDF1_CTRL_REG_UDF1_OFFSET
+	#define NON_IP_UDF1_CTRL_REG_UDF1_OFFSET_OFFSET  8
+	#define NON_IP_UDF1_CTRL_REG_UDF1_OFFSET_LEN     6
+	#define NON_IP_UDF1_CTRL_REG_UDF1_OFFSET_DEFAULT 0x0
+
+/*[register] NON_IP_UDF2_CTRL_REG*/
+#define NON_IP_UDF2_CTRL_REG
+#define NON_IP_UDF2_CTRL_REG_ADDRESS 0x40
+#define NON_IP_UDF2_CTRL_REG_NUM     1
+#define NON_IP_UDF2_CTRL_REG_INC     0x4
+#define NON_IP_UDF2_CTRL_REG_TYPE    REG_TYPE_RW
+#define NON_IP_UDF2_CTRL_REG_DEFAULT 0x0
+	/*[field] UDF2_BASE*/
+	#define NON_IP_UDF2_CTRL_REG_UDF2_BASE
+	#define NON_IP_UDF2_CTRL_REG_UDF2_BASE_OFFSET  0
+	#define NON_IP_UDF2_CTRL_REG_UDF2_BASE_LEN     2
+	#define NON_IP_UDF2_CTRL_REG_UDF2_BASE_DEFAULT 0x0
+	/*[field] UDF2_OFFSET*/
+	#define NON_IP_UDF2_CTRL_REG_UDF2_OFFSET
+	#define NON_IP_UDF2_CTRL_REG_UDF2_OFFSET_OFFSET  8
+	#define NON_IP_UDF2_CTRL_REG_UDF2_OFFSET_LEN     6
+	#define NON_IP_UDF2_CTRL_REG_UDF2_OFFSET_DEFAULT 0x0
+
+/*[register] NON_IP_UDF3_CTRL_REG*/
+#define NON_IP_UDF3_CTRL_REG
+#define NON_IP_UDF3_CTRL_REG_ADDRESS 0x44
+#define NON_IP_UDF3_CTRL_REG_NUM     1
+#define NON_IP_UDF3_CTRL_REG_INC     0x4
+#define NON_IP_UDF3_CTRL_REG_TYPE    REG_TYPE_RW
+#define NON_IP_UDF3_CTRL_REG_DEFAULT 0x0
+	/*[field] UDF3_BASE*/
+	#define NON_IP_UDF3_CTRL_REG_UDF3_BASE
+	#define NON_IP_UDF3_CTRL_REG_UDF3_BASE_OFFSET  0
+	#define NON_IP_UDF3_CTRL_REG_UDF3_BASE_LEN     2
+	#define NON_IP_UDF3_CTRL_REG_UDF3_BASE_DEFAULT 0x0
+	/*[field] UDF3_OFFSET*/
+	#define NON_IP_UDF3_CTRL_REG_UDF3_OFFSET
+	#define NON_IP_UDF3_CTRL_REG_UDF3_OFFSET_OFFSET  8
+	#define NON_IP_UDF3_CTRL_REG_UDF3_OFFSET_LEN     6
+	#define NON_IP_UDF3_CTRL_REG_UDF3_OFFSET_DEFAULT 0x0
+
+/*[register] IPV4_UDF0_CTRL_REG*/
+#define IPV4_UDF0_CTRL_REG
+#define IPV4_UDF0_CTRL_REG_ADDRESS 0x48
+#define IPV4_UDF0_CTRL_REG_NUM     1
+#define IPV4_UDF0_CTRL_REG_INC     0x4
+#define IPV4_UDF0_CTRL_REG_TYPE    REG_TYPE_RW
+#define IPV4_UDF0_CTRL_REG_DEFAULT 0x0
+	/*[field] UDF0_BASE*/
+	#define IPV4_UDF0_CTRL_REG_UDF0_BASE
+	#define IPV4_UDF0_CTRL_REG_UDF0_BASE_OFFSET  0
+	#define IPV4_UDF0_CTRL_REG_UDF0_BASE_LEN     2
+	#define IPV4_UDF0_CTRL_REG_UDF0_BASE_DEFAULT 0x0
+	/*[field] UDF0_OFFSET*/
+	#define IPV4_UDF0_CTRL_REG_UDF0_OFFSET
+	#define IPV4_UDF0_CTRL_REG_UDF0_OFFSET_OFFSET  8
+	#define IPV4_UDF0_CTRL_REG_UDF0_OFFSET_LEN     6
+	#define IPV4_UDF0_CTRL_REG_UDF0_OFFSET_DEFAULT 0x0
+
+/*[register] IPV4_UDF1_CTRL_REG*/
+#define IPV4_UDF1_CTRL_REG
+#define IPV4_UDF1_CTRL_REG_ADDRESS 0x4c
+#define IPV4_UDF1_CTRL_REG_NUM     1
+#define IPV4_UDF1_CTRL_REG_INC     0x4
+#define IPV4_UDF1_CTRL_REG_TYPE    REG_TYPE_RW
+#define IPV4_UDF1_CTRL_REG_DEFAULT 0x0
+	/*[field] UDF1_BASE*/
+	#define IPV4_UDF1_CTRL_REG_UDF1_BASE
+	#define IPV4_UDF1_CTRL_REG_UDF1_BASE_OFFSET  0
+	#define IPV4_UDF1_CTRL_REG_UDF1_BASE_LEN     2
+	#define IPV4_UDF1_CTRL_REG_UDF1_BASE_DEFAULT 0x0
+	/*[field] UDF1_OFFSET*/
+	#define IPV4_UDF1_CTRL_REG_UDF1_OFFSET
+	#define IPV4_UDF1_CTRL_REG_UDF1_OFFSET_OFFSET  8
+	#define IPV4_UDF1_CTRL_REG_UDF1_OFFSET_LEN     6
+	#define IPV4_UDF1_CTRL_REG_UDF1_OFFSET_DEFAULT 0x0
+
+/*[register] IPV4_UDF2_CTRL_REG*/
+#define IPV4_UDF2_CTRL_REG
+#define IPV4_UDF2_CTRL_REG_ADDRESS 0x50
+#define IPV4_UDF2_CTRL_REG_NUM     1
+#define IPV4_UDF2_CTRL_REG_INC     0x4
+#define IPV4_UDF2_CTRL_REG_TYPE    REG_TYPE_RW
+#define IPV4_UDF2_CTRL_REG_DEFAULT 0x0
+	/*[field] UDF2_BASE*/
+	#define IPV4_UDF2_CTRL_REG_UDF2_BASE
+	#define IPV4_UDF2_CTRL_REG_UDF2_BASE_OFFSET  0
+	#define IPV4_UDF2_CTRL_REG_UDF2_BASE_LEN     2
+	#define IPV4_UDF2_CTRL_REG_UDF2_BASE_DEFAULT 0x0
+	/*[field] UDF2_OFFSET*/
+	#define IPV4_UDF2_CTRL_REG_UDF2_OFFSET
+	#define IPV4_UDF2_CTRL_REG_UDF2_OFFSET_OFFSET  8
+	#define IPV4_UDF2_CTRL_REG_UDF2_OFFSET_LEN     6
+	#define IPV4_UDF2_CTRL_REG_UDF2_OFFSET_DEFAULT 0x0
+
+/*[register] IPV4_UDF3_CTRL_REG*/
+#define IPV4_UDF3_CTRL_REG
+#define IPV4_UDF3_CTRL_REG_ADDRESS 0x54
+#define IPV4_UDF3_CTRL_REG_NUM     1
+#define IPV4_UDF3_CTRL_REG_INC     0x4
+#define IPV4_UDF3_CTRL_REG_TYPE    REG_TYPE_RW
+#define IPV4_UDF3_CTRL_REG_DEFAULT 0x0
+	/*[field] UDF3_BASE*/
+	#define IPV4_UDF3_CTRL_REG_UDF3_BASE
+	#define IPV4_UDF3_CTRL_REG_UDF3_BASE_OFFSET  0
+	#define IPV4_UDF3_CTRL_REG_UDF3_BASE_LEN     2
+	#define IPV4_UDF3_CTRL_REG_UDF3_BASE_DEFAULT 0x0
+	/*[field] UDF3_OFFSET*/
+	#define IPV4_UDF3_CTRL_REG_UDF3_OFFSET
+	#define IPV4_UDF3_CTRL_REG_UDF3_OFFSET_OFFSET  8
+	#define IPV4_UDF3_CTRL_REG_UDF3_OFFSET_LEN     6
+	#define IPV4_UDF3_CTRL_REG_UDF3_OFFSET_DEFAULT 0x0
+
+/*[register] IPV6_UDF0_CTRL_REG*/
+#define IPV6_UDF0_CTRL_REG
+#define IPV6_UDF0_CTRL_REG_ADDRESS 0x58
+#define IPV6_UDF0_CTRL_REG_NUM     1
+#define IPV6_UDF0_CTRL_REG_INC     0x4
+#define IPV6_UDF0_CTRL_REG_TYPE    REG_TYPE_RW
+#define IPV6_UDF0_CTRL_REG_DEFAULT 0x0
+	/*[field] UDF0_BASE*/
+	#define IPV6_UDF0_CTRL_REG_UDF0_BASE
+	#define IPV6_UDF0_CTRL_REG_UDF0_BASE_OFFSET  0
+	#define IPV6_UDF0_CTRL_REG_UDF0_BASE_LEN     2
+	#define IPV6_UDF0_CTRL_REG_UDF0_BASE_DEFAULT 0x0
+	/*[field] UDF0_OFFSET*/
+	#define IPV6_UDF0_CTRL_REG_UDF0_OFFSET
+	#define IPV6_UDF0_CTRL_REG_UDF0_OFFSET_OFFSET  8
+	#define IPV6_UDF0_CTRL_REG_UDF0_OFFSET_LEN     6
+	#define IPV6_UDF0_CTRL_REG_UDF0_OFFSET_DEFAULT 0x0
+
+/*[register] IPV6_UDF1_CTRL_REG*/
+#define IPV6_UDF1_CTRL_REG
+#define IPV6_UDF1_CTRL_REG_ADDRESS 0x5c
+#define IPV6_UDF1_CTRL_REG_NUM     1
+#define IPV6_UDF1_CTRL_REG_INC     0x4
+#define IPV6_UDF1_CTRL_REG_TYPE    REG_TYPE_RW
+#define IPV6_UDF1_CTRL_REG_DEFAULT 0x0
+	/*[field] UDF1_BASE*/
+	#define IPV6_UDF1_CTRL_REG_UDF1_BASE
+	#define IPV6_UDF1_CTRL_REG_UDF1_BASE_OFFSET  0
+	#define IPV6_UDF1_CTRL_REG_UDF1_BASE_LEN     2
+	#define IPV6_UDF1_CTRL_REG_UDF1_BASE_DEFAULT 0x0
+	/*[field] UDF1_OFFSET*/
+	#define IPV6_UDF1_CTRL_REG_UDF1_OFFSET
+	#define IPV6_UDF1_CTRL_REG_UDF1_OFFSET_OFFSET  8
+	#define IPV6_UDF1_CTRL_REG_UDF1_OFFSET_LEN     6
+	#define IPV6_UDF1_CTRL_REG_UDF1_OFFSET_DEFAULT 0x0
+
+/*[register] IPV6_UDF2_CTRL_REG*/
+#define IPV6_UDF2_CTRL_REG
+#define IPV6_UDF2_CTRL_REG_ADDRESS 0x60
+#define IPV6_UDF2_CTRL_REG_NUM     1
+#define IPV6_UDF2_CTRL_REG_INC     0x4
+#define IPV6_UDF2_CTRL_REG_TYPE    REG_TYPE_RW
+#define IPV6_UDF2_CTRL_REG_DEFAULT 0x0
+	/*[field] UDF2_BASE*/
+	#define IPV6_UDF2_CTRL_REG_UDF2_BASE
+	#define IPV6_UDF2_CTRL_REG_UDF2_BASE_OFFSET  0
+	#define IPV6_UDF2_CTRL_REG_UDF2_BASE_LEN     2
+	#define IPV6_UDF2_CTRL_REG_UDF2_BASE_DEFAULT 0x0
+	/*[field] UDF2_OFFSET*/
+	#define IPV6_UDF2_CTRL_REG_UDF2_OFFSET
+	#define IPV6_UDF2_CTRL_REG_UDF2_OFFSET_OFFSET  8
+	#define IPV6_UDF2_CTRL_REG_UDF2_OFFSET_LEN     6
+	#define IPV6_UDF2_CTRL_REG_UDF2_OFFSET_DEFAULT 0x0
+
+/*[register] IPV6_UDF3_CTRL_REG*/
+#define IPV6_UDF3_CTRL_REG
+#define IPV6_UDF3_CTRL_REG_ADDRESS 0x64
+#define IPV6_UDF3_CTRL_REG_NUM     1
+#define IPV6_UDF3_CTRL_REG_INC     0x4
+#define IPV6_UDF3_CTRL_REG_TYPE    REG_TYPE_RW
+#define IPV6_UDF3_CTRL_REG_DEFAULT 0x0
+	/*[field] UDF3_BASE*/
+	#define IPV6_UDF3_CTRL_REG_UDF3_BASE
+	#define IPV6_UDF3_CTRL_REG_UDF3_BASE_OFFSET  0
+	#define IPV6_UDF3_CTRL_REG_UDF3_BASE_LEN     2
+	#define IPV6_UDF3_CTRL_REG_UDF3_BASE_DEFAULT 0x0
+	/*[field] UDF3_OFFSET*/
+	#define IPV6_UDF3_CTRL_REG_UDF3_OFFSET
+	#define IPV6_UDF3_CTRL_REG_UDF3_OFFSET_OFFSET  8
+	#define IPV6_UDF3_CTRL_REG_UDF3_OFFSET_LEN     6
+	#define IPV6_UDF3_CTRL_REG_UDF3_OFFSET_DEFAULT 0x0
+
+/*[table] IPO_RULE_REG*/
+#define IPO_RULE_REG
+#define IPO_RULE_REG_ADDRESS 0x0
+#define IPO_RULE_REG_NUM     512
+#define IPO_RULE_REG_INC     0x10
+#define IPO_RULE_REG_TYPE    REG_TYPE_RW
+#define IPO_RULE_REG_DEFAULT 0x0
+	/*[field] RULE_FIELD*/
+	#define IPO_RULE_REG_RULE_FIELD
+	#define IPO_RULE_REG_RULE_FIELD_OFFSET  0
+	#define IPO_RULE_REG_RULE_FIELD_LEN     52
+	#define IPO_RULE_REG_RULE_FIELD_DEFAULT 0x0
+	/*[field] FAKE_MAC_HEADER*/
+	#define IPO_RULE_REG_FAKE_MAC_HEADER
+	#define IPO_RULE_REG_FAKE_MAC_HEADER_OFFSET  52
+	#define IPO_RULE_REG_FAKE_MAC_HEADER_LEN     1
+	#define IPO_RULE_REG_FAKE_MAC_HEADER_DEFAULT 0x0
+	/*[field] RANGE_EN*/
+	#define IPO_RULE_REG_RANGE_EN
+	#define IPO_RULE_REG_RANGE_EN_OFFSET  53
+	#define IPO_RULE_REG_RANGE_EN_LEN     1
+	#define IPO_RULE_REG_RANGE_EN_DEFAULT 0x0
+	/*[field] INVERSE_EN*/
+	#define IPO_RULE_REG_INVERSE_EN
+	#define IPO_RULE_REG_INVERSE_EN_OFFSET  54
+	#define IPO_RULE_REG_INVERSE_EN_LEN     1
+	#define IPO_RULE_REG_INVERSE_EN_DEFAULT 0x0
+	/*[field] RULE_TYPE*/
+	#define IPO_RULE_REG_RULE_TYPE
+	#define IPO_RULE_REG_RULE_TYPE_OFFSET  55
+	#define IPO_RULE_REG_RULE_TYPE_LEN     4
+	#define IPO_RULE_REG_RULE_TYPE_DEFAULT 0x0
+	/*[field] SRC_TYPE*/
+	#define IPO_RULE_REG_SRC_TYPE
+	#define IPO_RULE_REG_SRC_TYPE_OFFSET  59
+	#define IPO_RULE_REG_SRC_TYPE_LEN     2
+	#define IPO_RULE_REG_SRC_TYPE_DEFAULT 0x0
+	/*[field] SRC*/
+	#define IPO_RULE_REG_SRC
+	#define IPO_RULE_REG_SRC_OFFSET  61
+	#define IPO_RULE_REG_SRC_LEN     8
+	#define IPO_RULE_REG_SRC_DEFAULT 0x0
+	/*[field] PRI*/
+	#define IPO_RULE_REG_PRI
+	#define IPO_RULE_REG_PRI_OFFSET  69
+	#define IPO_RULE_REG_PRI_LEN     9
+	#define IPO_RULE_REG_PRI_DEFAULT 0x0
+	/*[field] RES_CHAIN*/
+	#define IPO_RULE_REG_RES_CHAIN
+	#define IPO_RULE_REG_RES_CHAIN_OFFSET  78
+	#define IPO_RULE_REG_RES_CHAIN_LEN     1
+	#define IPO_RULE_REG_RES_CHAIN_DEFAULT 0x0
+	/*[field] POST_ROUTING_EN*/
+	#define IPO_RULE_REG_POST_ROUTING_EN
+	#define IPO_RULE_REG_POST_ROUTING_EN_OFFSET  79
+	#define IPO_RULE_REG_POST_ROUTING_EN_LEN     1
+	#define IPO_RULE_REG_POST_ROUTING_EN_DEFAULT 0x0
+
+struct ipo_rule_reg {
+	a_uint32_t  rule_field_0:32;
+	a_uint32_t  rule_field_1:20;
+	a_uint32_t  fake_mac_header:1;
+	a_uint32_t  range_en:1;
+	a_uint32_t  inverse_en:1;
+	a_uint32_t  rule_type:4;
+	a_uint32_t  src_type:2;
+	a_uint32_t  src_0:3;
+	a_uint32_t  src_1:5;
+	a_uint32_t  pri:9;
+	a_uint32_t  res_chain:1;
+	a_uint32_t  post_routing_en:1;
+	a_uint32_t  _reserved0:16;
+};
+
+union ipo_rule_reg_u {
+	a_uint32_t val[3];
+	struct ipo_rule_reg bf;
+};
+
+/*[table] IPO_MASK_REG*/
+#define IPO_MASK_REG
+#define IPO_MASK_REG_ADDRESS 0x2000
+#define IPO_MASK_REG_NUM     512
+#define IPO_MASK_REG_INC     0x10
+#define IPO_MASK_REG_TYPE    REG_TYPE_RW
+#define IPO_MASK_REG_DEFAULT 0x0
+	/*[field] MASKFIELD*/
+	#define IPO_MASK_REG_MASKFIELD
+	#define IPO_MASK_REG_MASKFIELD_OFFSET  0
+	#define IPO_MASK_REG_MASKFIELD_LEN     53
+	#define IPO_MASK_REG_MASKFIELD_DEFAULT 0x0
+
+struct ipo_mask_reg {
+	a_uint32_t  maskfield_0:32;
+	a_uint32_t  maskfield_1:21;
+	a_uint32_t  _reserved0:11;
+};
+
+union ipo_mask_reg_u {
+	a_uint32_t val[2];
+	struct ipo_mask_reg bf;
+};
+
+/*[register] RULE_EXT_1_REG*/
+#define RULE_EXT_1_REG
+#define RULE_EXT_1_REG_ADDRESS 0x4000
+#define RULE_EXT_1_REG_NUM     64
+#define RULE_EXT_1_REG_INC     0x4
+#define RULE_EXT_1_REG_TYPE    REG_TYPE_RW
+#define RULE_EXT_1_REG_DEFAULT 0x0
+	/*[field] EXT2_0*/
+	#define RULE_EXT_1_REG_EXT2_0
+	#define RULE_EXT_1_REG_EXT2_0_OFFSET  0
+	#define RULE_EXT_1_REG_EXT2_0_LEN     1
+	#define RULE_EXT_1_REG_EXT2_0_DEFAULT 0x0
+	/*[field] EXT2_1*/
+	#define RULE_EXT_1_REG_EXT2_1
+	#define RULE_EXT_1_REG_EXT2_1_OFFSET  1
+	#define RULE_EXT_1_REG_EXT2_1_LEN     1
+	#define RULE_EXT_1_REG_EXT2_1_DEFAULT 0x0
+	/*[field] EXT2_2*/
+	#define RULE_EXT_1_REG_EXT2_2
+	#define RULE_EXT_1_REG_EXT2_2_OFFSET  2
+	#define RULE_EXT_1_REG_EXT2_2_LEN     1
+	#define RULE_EXT_1_REG_EXT2_2_DEFAULT 0x0
+	/*[field] EXT2_3*/
+	#define RULE_EXT_1_REG_EXT2_3
+	#define RULE_EXT_1_REG_EXT2_3_OFFSET  3
+	#define RULE_EXT_1_REG_EXT2_3_LEN     1
+	#define RULE_EXT_1_REG_EXT2_3_DEFAULT 0x0
+
+struct rule_ext_1_reg {
+	a_uint32_t  ext2_0:1;
+	a_uint32_t  ext2_1:1;
+	a_uint32_t  ext2_2:1;
+	a_uint32_t  ext2_3:1;
+	a_uint32_t  _reserved0:28;
+};
+
+union rule_ext_1_reg_u {
+	a_uint32_t val;
+	struct rule_ext_1_reg bf;
+};
+
+/*[register] RULE_EXT_2_REG*/
+#define RULE_EXT_2_REG
+#define RULE_EXT_2_REG_ADDRESS 0x4100
+#define RULE_EXT_2_REG_NUM     64
+#define RULE_EXT_2_REG_INC     0x4
+#define RULE_EXT_2_REG_TYPE    REG_TYPE_RW
+#define RULE_EXT_2_REG_DEFAULT 0x0
+	/*[field] EXT4_0*/
+	#define RULE_EXT_2_REG_EXT4_0
+	#define RULE_EXT_2_REG_EXT4_0_OFFSET  0
+	#define RULE_EXT_2_REG_EXT4_0_LEN     1
+	#define RULE_EXT_2_REG_EXT4_0_DEFAULT 0x0
+	/*[field] EXT4_1*/
+	#define RULE_EXT_2_REG_EXT4_1
+	#define RULE_EXT_2_REG_EXT4_1_OFFSET  1
+	#define RULE_EXT_2_REG_EXT4_1_LEN     1
+	#define RULE_EXT_2_REG_EXT4_1_DEFAULT 0x0
+
+struct rule_ext_2_reg {
+	a_uint32_t  ext4_0:1;
+	a_uint32_t  ext4_1:1;
+	a_uint32_t  _reserved0:30;
+};
+
+union rule_ext_2_reg_u {
+	a_uint32_t val;
+	struct rule_ext_2_reg bf;
+};
+
+/*[register] RULE_EXT_4_REG*/
+#define RULE_EXT_4_REG
+#define RULE_EXT_4_REG_ADDRESS 0x4200
+#define RULE_EXT_4_REG_NUM     64
+#define RULE_EXT_4_REG_INC     0x4
+#define RULE_EXT_4_REG_TYPE    REG_TYPE_RW
+#define RULE_EXT_4_REG_DEFAULT 0x0
+	/*[field] EXT8*/
+	#define RULE_EXT_4_REG_EXT8
+	#define RULE_EXT_4_REG_EXT8_OFFSET  0
+	#define RULE_EXT_4_REG_EXT8_LEN     1
+	#define RULE_EXT_4_REG_EXT8_DEFAULT 0x0
+
+struct rule_ext_4_reg {
+	a_uint32_t  ext8:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union rule_ext_4_reg_u {
+	a_uint32_t val;
+	struct rule_ext_4_reg bf;
+};
+
+/*[register] IPO_DBG_ADDR_REG*/
+#define IPO_DBG_ADDR_REG
+#define IPO_DBG_ADDR_REG_ADDRESS 0x4300
+#define IPO_DBG_ADDR_REG_NUM     1
+#define IPO_DBG_ADDR_REG_INC     0x4
+#define IPO_DBG_ADDR_REG_TYPE    REG_TYPE_RW
+#define IPO_DBG_ADDR_REG_DEFAULT 0x0
+	/*[field] IPO_DBG_ADDR*/
+	#define IPO_DBG_ADDR_REG_IPO_DBG_ADDR
+	#define IPO_DBG_ADDR_REG_IPO_DBG_ADDR_OFFSET  0
+	#define IPO_DBG_ADDR_REG_IPO_DBG_ADDR_LEN     32
+	#define IPO_DBG_ADDR_REG_IPO_DBG_ADDR_DEFAULT 0x0
+
+struct ipo_dbg_addr_reg {
+	a_uint32_t  ipo_dbg_addr:32;
+};
+
+union ipo_dbg_addr_reg_u {
+	a_uint32_t val;
+	struct ipo_dbg_addr_reg bf;
+};
+
+/*[register] IPO_DBG_DATA_REG*/
+#define IPO_DBG_DATA_REG
+#define IPO_DBG_DATA_REG_ADDRESS 0x4304
+#define IPO_DBG_DATA_REG_NUM     1
+#define IPO_DBG_DATA_REG_INC     0x4
+#define IPO_DBG_DATA_REG_TYPE    REG_TYPE_RO
+#define IPO_DBG_DATA_REG_DEFAULT 0x0
+	/*[field] IPO_DBG_DATA*/
+	#define IPO_DBG_DATA_REG_IPO_DBG_DATA
+	#define IPO_DBG_DATA_REG_IPO_DBG_DATA_OFFSET  0
+	#define IPO_DBG_DATA_REG_IPO_DBG_DATA_LEN     32
+	#define IPO_DBG_DATA_REG_IPO_DBG_DATA_DEFAULT 0x0
+
+struct ipo_dbg_data_reg {
+	a_uint32_t  ipo_dbg_data:32;
+};
+
+union ipo_dbg_data_reg_u {
+	a_uint32_t val;
+	struct ipo_dbg_data_reg bf;
+};
+
+/*[register] IPO_SPARE_REG_REG*/
+#define IPO_SPARE_REG_REG
+#define IPO_SPARE_REG_REG_ADDRESS 0x4308
+#define IPO_SPARE_REG_REG_NUM     1
+#define IPO_SPARE_REG_REG_INC     0x4
+#define IPO_SPARE_REG_REG_TYPE    REG_TYPE_RW
+#define IPO_SPARE_REG_REG_DEFAULT 0x0
+	/*[field] SPARE_REG*/
+	#define IPO_SPARE_REG_REG_SPARE_REG
+	#define IPO_SPARE_REG_REG_SPARE_REG_OFFSET  0
+	#define IPO_SPARE_REG_REG_SPARE_REG_LEN     32
+	#define IPO_SPARE_REG_REG_SPARE_REG_DEFAULT 0x0
+
+struct ipo_spare_reg_reg {
+	a_uint32_t  spare_reg:32;
+};
+
+union ipo_spare_reg_reg_u {
+	a_uint32_t val;
+	struct ipo_spare_reg_reg bf;
+};
+
+/*[register] IPO_GLB_HIT_COUNTER_REG*/
+#define IPO_GLB_HIT_COUNTER_REG
+#define IPO_GLB_HIT_COUNTER_REG_ADDRESS 0x430c
+#define IPO_GLB_HIT_COUNTER_REG_NUM     1
+#define IPO_GLB_HIT_COUNTER_REG_INC     0x4
+#define IPO_GLB_HIT_COUNTER_REG_TYPE    REG_TYPE_RO
+#define IPO_GLB_HIT_COUNTER_REG_DEFAULT 0x0
+	/*[field] HIT_COUNT*/
+	#define IPO_GLB_HIT_COUNTER_REG_HIT_COUNT
+	#define IPO_GLB_HIT_COUNTER_REG_HIT_COUNT_OFFSET  0
+	#define IPO_GLB_HIT_COUNTER_REG_HIT_COUNT_LEN     32
+	#define IPO_GLB_HIT_COUNTER_REG_HIT_COUNT_DEFAULT 0x0
+
+struct ipo_glb_hit_counter_reg {
+	a_uint32_t  hit_count:32;
+};
+
+union ipo_glb_hit_counter_reg_u {
+	a_uint32_t val;
+	struct ipo_glb_hit_counter_reg bf;
+};
+
+/*[register] IPO_GLB_MISS_COUNTER_REG*/
+#define IPO_GLB_MISS_COUNTER_REG
+#define IPO_GLB_MISS_COUNTER_REG_ADDRESS 0x4310
+#define IPO_GLB_MISS_COUNTER_REG_NUM     1
+#define IPO_GLB_MISS_COUNTER_REG_INC     0x4
+#define IPO_GLB_MISS_COUNTER_REG_TYPE    REG_TYPE_RO
+#define IPO_GLB_MISS_COUNTER_REG_DEFAULT 0x0
+	/*[field] MISS_COUNT*/
+	#define IPO_GLB_MISS_COUNTER_REG_MISS_COUNT
+	#define IPO_GLB_MISS_COUNTER_REG_MISS_COUNT_OFFSET  0
+	#define IPO_GLB_MISS_COUNTER_REG_MISS_COUNT_LEN     32
+	#define IPO_GLB_MISS_COUNTER_REG_MISS_COUNT_DEFAULT 0x0
+
+struct ipo_glb_miss_counter_reg {
+	a_uint32_t  miss_count:32;
+};
+
+union ipo_glb_miss_counter_reg_u {
+	a_uint32_t val;
+	struct ipo_glb_miss_counter_reg bf;
+};
+
+/*[register] IPO_GLB_BYPASS_COUNTER_REG*/
+#define IPO_GLB_BYPASS_COUNTER_REG
+#define IPO_GLB_BYPASS_COUNTER_REG_ADDRESS 0x4314
+#define IPO_GLB_BYPASS_COUNTER_REG_NUM     1
+#define IPO_GLB_BYPASS_COUNTER_REG_INC     0x4
+#define IPO_GLB_BYPASS_COUNTER_REG_TYPE    REG_TYPE_RO
+#define IPO_GLB_BYPASS_COUNTER_REG_DEFAULT 0x0
+	/*[field] BYPASS_COUNT*/
+	#define IPO_GLB_BYPASS_COUNTER_REG_BYPASS_COUNT
+	#define IPO_GLB_BYPASS_COUNTER_REG_BYPASS_COUNT_OFFSET  0
+	#define IPO_GLB_BYPASS_COUNTER_REG_BYPASS_COUNT_LEN     32
+	#define IPO_GLB_BYPASS_COUNTER_REG_BYPASS_COUNT_DEFAULT 0x0
+
+struct ipo_glb_bypass_counter_reg {
+	a_uint32_t  bypass_count:32;
+};
+
+union ipo_glb_bypass_counter_reg_u {
+	a_uint32_t val;
+	struct ipo_glb_bypass_counter_reg bf;
+};
+
+/*[table] IPO_CNT_TBL*/
+#define IPO_CNT_TBL
+#define IPO_CNT_TBL_ADDRESS 0x74000
+#define IPO_CNT_TBL_NUM     512
+#define IPO_CNT_TBL_INC     0x10
+#define IPO_CNT_TBL_TYPE    REG_TYPE_RW
+#define IPO_CNT_TBL_DEFAULT 0x0
+	/*[field] HIT_PKT_CNT*/
+	#define IPO_CNT_TBL_HIT_PKT_CNT
+	#define IPO_CNT_TBL_HIT_PKT_CNT_OFFSET  0
+	#define IPO_CNT_TBL_HIT_PKT_CNT_LEN     32
+	#define IPO_CNT_TBL_HIT_PKT_CNT_DEFAULT 0x0
+	/*[field] HIT_BYTE_CNT*/
+	#define IPO_CNT_TBL_HIT_BYTE_CNT
+	#define IPO_CNT_TBL_HIT_BYTE_CNT_OFFSET  32
+	#define IPO_CNT_TBL_HIT_BYTE_CNT_LEN     40
+	#define IPO_CNT_TBL_HIT_BYTE_CNT_DEFAULT 0x0
+
+struct ipo_cnt_tbl {
+	a_uint32_t  hit_pkt_cnt:32;
+	a_uint32_t  hit_byte_cnt_0:32;
+	a_uint32_t  hit_byte_cnt_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union ipo_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct ipo_cnt_tbl bf;
+};
+
+/*[table] IPO_ACTION*/
+#define IPO_ACTION
+#define IPO_ACTION_ADDRESS 0x8000
+#define IPO_ACTION_NUM     512
+#define IPO_ACTION_INC     0x20
+#define IPO_ACTION_TYPE    REG_TYPE_RW
+#define IPO_ACTION_DEFAULT 0x0
+	/*[field] DEST_INFO_CHANGE_EN*/
+	#define IPO_ACTION_DEST_INFO_CHANGE_EN
+	#define IPO_ACTION_DEST_INFO_CHANGE_EN_OFFSET  0
+	#define IPO_ACTION_DEST_INFO_CHANGE_EN_LEN     1
+	#define IPO_ACTION_DEST_INFO_CHANGE_EN_DEFAULT 0x0
+	/*[field] FWD_CMD*/
+	#define IPO_ACTION_FWD_CMD
+	#define IPO_ACTION_FWD_CMD_OFFSET  1
+	#define IPO_ACTION_FWD_CMD_LEN     2
+	#define IPO_ACTION_FWD_CMD_DEFAULT 0x0
+	/*[field] DEST_INFO*/
+	#define IPO_ACTION_DEST_INFO
+	#define IPO_ACTION_DEST_INFO_OFFSET  3
+	#define IPO_ACTION_DEST_INFO_LEN     14
+	#define IPO_ACTION_DEST_INFO_DEFAULT 0x0
+	/*[field] MIRROR_EN*/
+	#define IPO_ACTION_MIRROR_EN
+	#define IPO_ACTION_MIRROR_EN_OFFSET  17
+	#define IPO_ACTION_MIRROR_EN_LEN     1
+	#define IPO_ACTION_MIRROR_EN_DEFAULT 0x0
+	/*[field] BYPASS_BITMAP*/
+	#define IPO_ACTION_BYPASS_BITMAP
+	#define IPO_ACTION_BYPASS_BITMAP_OFFSET  18
+	#define IPO_ACTION_BYPASS_BITMAP_LEN     32
+	#define IPO_ACTION_BYPASS_BITMAP_DEFAULT 0x0
+	/*[field] SVID_CHANGE_EN*/
+	#define IPO_ACTION_SVID_CHANGE_EN
+	#define IPO_ACTION_SVID_CHANGE_EN_OFFSET  50
+	#define IPO_ACTION_SVID_CHANGE_EN_LEN     1
+	#define IPO_ACTION_SVID_CHANGE_EN_DEFAULT 0x0
+	/*[field] STAG_FMT*/
+	#define IPO_ACTION_STAG_FMT
+	#define IPO_ACTION_STAG_FMT_OFFSET  51
+	#define IPO_ACTION_STAG_FMT_LEN     1
+	#define IPO_ACTION_STAG_FMT_DEFAULT 0x0
+	/*[field] SVID*/
+	#define IPO_ACTION_SVID
+	#define IPO_ACTION_SVID_OFFSET  52
+	#define IPO_ACTION_SVID_LEN     12
+	#define IPO_ACTION_SVID_DEFAULT 0x0
+	/*[field] CVID_CHANGE_EN*/
+	#define IPO_ACTION_CVID_CHANGE_EN
+	#define IPO_ACTION_CVID_CHANGE_EN_OFFSET  64
+	#define IPO_ACTION_CVID_CHANGE_EN_LEN     1
+	#define IPO_ACTION_CVID_CHANGE_EN_DEFAULT 0x0
+	/*[field] CTAG_FMT*/
+	#define IPO_ACTION_CTAG_FMT
+	#define IPO_ACTION_CTAG_FMT_OFFSET  65
+	#define IPO_ACTION_CTAG_FMT_LEN     1
+	#define IPO_ACTION_CTAG_FMT_DEFAULT 0x0
+	/*[field] CVID*/
+	#define IPO_ACTION_CVID
+	#define IPO_ACTION_CVID_OFFSET  66
+	#define IPO_ACTION_CVID_LEN     12
+	#define IPO_ACTION_CVID_DEFAULT 0x0
+	/*[field] DSCP_TC_CHANGE_EN*/
+	#define IPO_ACTION_DSCP_TC_CHANGE_EN
+	#define IPO_ACTION_DSCP_TC_CHANGE_EN_OFFSET  78
+	#define IPO_ACTION_DSCP_TC_CHANGE_EN_LEN     1
+	#define IPO_ACTION_DSCP_TC_CHANGE_EN_DEFAULT 0x0
+	/*[field] DSCP_TC*/
+	#define IPO_ACTION_DSCP_TC
+	#define IPO_ACTION_DSCP_TC_OFFSET  79
+	#define IPO_ACTION_DSCP_TC_LEN     8
+	#define IPO_ACTION_DSCP_TC_DEFAULT 0x0
+	/*[field] STAG_PCP_CHANGE_EN*/
+	#define IPO_ACTION_STAG_PCP_CHANGE_EN
+	#define IPO_ACTION_STAG_PCP_CHANGE_EN_OFFSET  87
+	#define IPO_ACTION_STAG_PCP_CHANGE_EN_LEN     1
+	#define IPO_ACTION_STAG_PCP_CHANGE_EN_DEFAULT 0x0
+	/*[field] STAG_PCP*/
+	#define IPO_ACTION_STAG_PCP
+	#define IPO_ACTION_STAG_PCP_OFFSET  88
+	#define IPO_ACTION_STAG_PCP_LEN     3
+	#define IPO_ACTION_STAG_PCP_DEFAULT 0x0
+	/*[field] STAG_DEI_CHANGE_EN*/
+	#define IPO_ACTION_STAG_DEI_CHANGE_EN
+	#define IPO_ACTION_STAG_DEI_CHANGE_EN_OFFSET  91
+	#define IPO_ACTION_STAG_DEI_CHANGE_EN_LEN     1
+	#define IPO_ACTION_STAG_DEI_CHANGE_EN_DEFAULT 0x0
+	/*[field] STAG_DEI*/
+	#define IPO_ACTION_STAG_DEI
+	#define IPO_ACTION_STAG_DEI_OFFSET  92
+	#define IPO_ACTION_STAG_DEI_LEN     1
+	#define IPO_ACTION_STAG_DEI_DEFAULT 0x0
+	/*[field] CTAG_PCP_CHANGE_EN*/
+	#define IPO_ACTION_CTAG_PCP_CHANGE_EN
+	#define IPO_ACTION_CTAG_PCP_CHANGE_EN_OFFSET  93
+	#define IPO_ACTION_CTAG_PCP_CHANGE_EN_LEN     1
+	#define IPO_ACTION_CTAG_PCP_CHANGE_EN_DEFAULT 0x0
+	/*[field] CTAG_PCP*/
+	#define IPO_ACTION_CTAG_PCP
+	#define IPO_ACTION_CTAG_PCP_OFFSET  94
+	#define IPO_ACTION_CTAG_PCP_LEN     3
+	#define IPO_ACTION_CTAG_PCP_DEFAULT 0x0
+	/*[field] CTAG_DEI_CHANGE_EN*/
+	#define IPO_ACTION_CTAG_DEI_CHANGE_EN
+	#define IPO_ACTION_CTAG_DEI_CHANGE_EN_OFFSET  97
+	#define IPO_ACTION_CTAG_DEI_CHANGE_EN_LEN     1
+	#define IPO_ACTION_CTAG_DEI_CHANGE_EN_DEFAULT 0x0
+	/*[field] CTAG_DEI*/
+	#define IPO_ACTION_CTAG_DEI
+	#define IPO_ACTION_CTAG_DEI_OFFSET  98
+	#define IPO_ACTION_CTAG_DEI_LEN     1
+	#define IPO_ACTION_CTAG_DEI_DEFAULT 0x0
+	/*[field] ENQUEUE_PRI_CHANGE_EN*/
+	#define IPO_ACTION_ENQUEUE_PRI_CHANGE_EN
+	#define IPO_ACTION_ENQUEUE_PRI_CHANGE_EN_OFFSET  99
+	#define IPO_ACTION_ENQUEUE_PRI_CHANGE_EN_LEN     1
+	#define IPO_ACTION_ENQUEUE_PRI_CHANGE_EN_DEFAULT 0x0
+	/*[field] ENQUEUE_PRI*/
+	#define IPO_ACTION_ENQUEUE_PRI
+	#define IPO_ACTION_ENQUEUE_PRI_OFFSET  100
+	#define IPO_ACTION_ENQUEUE_PRI_LEN     4
+	#define IPO_ACTION_ENQUEUE_PRI_DEFAULT 0x0
+	/*[field] INT_DP_CHANGE_EN*/
+	#define IPO_ACTION_INT_DP_CHANGE_EN
+	#define IPO_ACTION_INT_DP_CHANGE_EN_OFFSET  104
+	#define IPO_ACTION_INT_DP_CHANGE_EN_LEN     1
+	#define IPO_ACTION_INT_DP_CHANGE_EN_DEFAULT 0x0
+	/*[field] INT_DP*/
+	#define IPO_ACTION_INT_DP
+	#define IPO_ACTION_INT_DP_OFFSET  105
+	#define IPO_ACTION_INT_DP_LEN     2
+	#define IPO_ACTION_INT_DP_DEFAULT 0x0
+	/*[field] POLICER_EN*/
+	#define IPO_ACTION_POLICER_EN
+	#define IPO_ACTION_POLICER_EN_OFFSET  107
+	#define IPO_ACTION_POLICER_EN_LEN     1
+	#define IPO_ACTION_POLICER_EN_DEFAULT 0x0
+	/*[field] POLICER_INDEX*/
+	#define IPO_ACTION_POLICER_INDEX
+	#define IPO_ACTION_POLICER_INDEX_OFFSET  108
+	#define IPO_ACTION_POLICER_INDEX_LEN     9
+	#define IPO_ACTION_POLICER_INDEX_DEFAULT 0x0
+	/*[field] QID_EN*/
+	#define IPO_ACTION_QID_EN
+	#define IPO_ACTION_QID_EN_OFFSET  117
+	#define IPO_ACTION_QID_EN_LEN     1
+	#define IPO_ACTION_QID_EN_DEFAULT 0x0
+	/*[field] QID*/
+	#define IPO_ACTION_QID
+	#define IPO_ACTION_QID_OFFSET  118
+	#define IPO_ACTION_QID_LEN     8
+	#define IPO_ACTION_QID_DEFAULT 0x0
+	/*[field] SERVICE_CODE_EN*/
+	#define IPO_ACTION_SERVICE_CODE_EN
+	#define IPO_ACTION_SERVICE_CODE_EN_OFFSET  126
+	#define IPO_ACTION_SERVICE_CODE_EN_LEN     1
+	#define IPO_ACTION_SERVICE_CODE_EN_DEFAULT 0x0
+	/*[field] SERVICE_CODE*/
+	#define IPO_ACTION_SERVICE_CODE
+	#define IPO_ACTION_SERVICE_CODE_OFFSET  127
+	#define IPO_ACTION_SERVICE_CODE_LEN     8
+	#define IPO_ACTION_SERVICE_CODE_DEFAULT 0x0
+	/*[field] SYN_TOGGLE*/
+	#define IPO_ACTION_SYN_TOGGLE
+	#define IPO_ACTION_SYN_TOGGLE_OFFSET  135
+	#define IPO_ACTION_SYN_TOGGLE_LEN     1
+	#define IPO_ACTION_SYN_TOGGLE_DEFAULT 0x0
+	/*[field] CPU_CODE_EN*/
+	#define IPO_ACTION_CPU_CODE_EN
+	#define IPO_ACTION_CPU_CODE_EN_OFFSET  136
+	#define IPO_ACTION_CPU_CODE_EN_LEN     1
+	#define IPO_ACTION_CPU_CODE_EN_DEFAULT 0x0
+	/*[field] CPU_CODE*/
+	#define IPO_ACTION_CPU_CODE
+	#define IPO_ACTION_CPU_CODE_OFFSET  137
+	#define IPO_ACTION_CPU_CODE_LEN     8
+	#define IPO_ACTION_CPU_CODE_DEFAULT 0x0
+	/*[field] METADATA_EN*/
+	#define IPO_ACTION_METADATA_EN
+	#define IPO_ACTION_METADATA_EN_OFFSET  145
+	#define IPO_ACTION_METADATA_EN_LEN     1
+	#define IPO_ACTION_METADATA_EN_DEFAULT 0x0
+
+struct ipo_action {
+	a_uint32_t  dest_info_change_en:1;
+	a_uint32_t  fwd_cmd:2;
+	a_uint32_t  dest_info:14;
+	a_uint32_t  mirror_en:1;
+	a_uint32_t  bypass_bitmap_0:14;
+	a_uint32_t  bypass_bitmap_1:18;
+	a_uint32_t  svid_change_en:1;
+	a_uint32_t  stag_fmt:1;
+	a_uint32_t  svid:12;
+	a_uint32_t  cvid_change_en:1;
+	a_uint32_t  ctag_fmt:1;
+	a_uint32_t  cvid:12;
+	a_uint32_t  dscp_tc_change_en:1;
+	a_uint32_t  dscp_tc:8;
+	a_uint32_t  stag_pcp_change_en:1;
+	a_uint32_t  stag_pcp:3;
+	a_uint32_t  stag_dei_change_en:1;
+	a_uint32_t  stag_dei:1;
+	a_uint32_t  ctag_pcp_change_en:1;
+	a_uint32_t  ctag_pcp_0:2;
+	a_uint32_t  ctag_pcp_1:1;
+	a_uint32_t  ctag_dei_change_en:1;
+	a_uint32_t  ctag_dei:1;
+	a_uint32_t  enqueue_pri_change_en:1;
+	a_uint32_t  enqueue_pri:4;
+	a_uint32_t  int_dp_change_en:1;
+	a_uint32_t  int_dp:2;
+	a_uint32_t  policer_en:1;
+	a_uint32_t  policer_index:9;
+	a_uint32_t  qid_en:1;
+	a_uint32_t  qid:8;
+	a_uint32_t  service_code_en:1;
+	a_uint32_t  service_code_0:1;
+	a_uint32_t  service_code_1:7;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  cpu_code_en:1;
+	a_uint32_t  cpu_code:8;
+	a_uint32_t  metadata_en:1;
+	a_uint32_t  dscp_tc_mask:8;
+	a_uint32_t  qos_res_prec:3;
+	a_uint32_t  _reserved0:3;
+};
+
+union ipo_action_u {
+	a_uint32_t val[5];
+	struct ipo_action bf;
+};
+
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_bm.h b/qca-ssdk/include/hsl/hppe/hppe_bm.h
new file mode 100755
index 0000000..d48f441
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_bm.h
@@ -0,0 +1,1218 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_BM_H_
+#define _HPPE_BM_H_
+
+#define DEQ_FIFO_CFG_MAX_ENTRY	9
+#define PORT_FC_MODE_MAX_ENTRY	15
+#define PORT_FC_STATUS_MAX_ENTRY	15
+#define PORT_GROUP_ID_MAX_ENTRY	15
+#define PORT_CNT_MAX_ENTRY	15
+#define PORT_REACTED_CNT_MAX_ENTRY	15
+#define SHARED_GROUP_CNT_MAX_ENTRY	4
+#define SHARED_GROUP_CFG_MAX_ENTRY	4
+#define PORT_PROFILE_TH_CFG_MAX_ENTRY	15
+#define REACT_PROFILE_TH_CFG_MAX_ENTRY	15
+#define GRP_PROFILE_TH_CFG_MAX_ENTRY	4
+#define PORT_OUT_PROFILE_CNT_MAX_ENTRY	15
+#define PORT_IN_PROFILE_CNT_MAX_ENTRY	15
+#define REACT_OUT_PROFILE_CNT_MAX_ENTRY	15
+#define REACT_IN_PROFILE_CNT_MAX_ENTRY	15
+#define GRP_OUT_PROFILE_CNT_MAX_ENTRY	4
+#define GRP_IN_PROFILE_CNT_MAX_ENTRY	4
+#define PORT_FC_CFG_MAX_ENTRY	15
+#define LLM_MAX_ENTRY	2048
+#define RCM_MAX_ENTRY	2048
+#define DM_MAX_ENTRY	8192
+
+
+sw_error_t
+hppe_fb_fifo_cfg_get(
+		a_uint32_t dev_id,
+		union fb_fifo_cfg_u *value);
+
+sw_error_t
+hppe_fb_fifo_cfg_set(
+		a_uint32_t dev_id,
+		union fb_fifo_cfg_u *value);
+
+sw_error_t
+hppe_fp_fifo_cfg_get(
+		a_uint32_t dev_id,
+		union fp_fifo_cfg_u *value);
+
+sw_error_t
+hppe_fp_fifo_cfg_set(
+		a_uint32_t dev_id,
+		union fp_fifo_cfg_u *value);
+
+sw_error_t
+hppe_deq_fifo_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union deq_fifo_cfg_u *value);
+
+sw_error_t
+hppe_deq_fifo_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union deq_fifo_cfg_u *value);
+
+sw_error_t
+hppe_tick_dly_cfg_get(
+		a_uint32_t dev_id,
+		union tick_dly_cfg_u *value);
+
+sw_error_t
+hppe_tick_dly_cfg_set(
+		a_uint32_t dev_id,
+		union tick_dly_cfg_u *value);
+
+sw_error_t
+hppe_bm_rsv_0_get(
+		a_uint32_t dev_id,
+		union bm_rsv_0_u *value);
+
+sw_error_t
+hppe_bm_rsv_0_set(
+		a_uint32_t dev_id,
+		union bm_rsv_0_u *value);
+
+sw_error_t
+hppe_bm_rsv_1_get(
+		a_uint32_t dev_id,
+		union bm_rsv_1_u *value);
+
+sw_error_t
+hppe_bm_rsv_1_set(
+		a_uint32_t dev_id,
+		union bm_rsv_1_u *value);
+
+sw_error_t
+hppe_bm_dbg_addr_get(
+		a_uint32_t dev_id,
+		union bm_dbg_addr_u *value);
+
+sw_error_t
+hppe_bm_dbg_addr_set(
+		a_uint32_t dev_id,
+		union bm_dbg_addr_u *value);
+
+sw_error_t
+hppe_bm_dbg_data_get(
+		a_uint32_t dev_id,
+		union bm_dbg_data_u *value);
+
+sw_error_t
+hppe_bm_dbg_data_set(
+		a_uint32_t dev_id,
+		union bm_dbg_data_u *value);
+
+sw_error_t
+hppe_port_fc_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_fc_mode_u *value);
+
+sw_error_t
+hppe_port_fc_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_fc_mode_u *value);
+
+sw_error_t
+hppe_port_fc_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_fc_status_u *value);
+
+sw_error_t
+hppe_port_fc_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_fc_status_u *value);
+
+sw_error_t
+hppe_port_group_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_group_id_u *value);
+
+sw_error_t
+hppe_port_group_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_group_id_u *value);
+
+sw_error_t
+hppe_port_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_cnt_u *value);
+
+sw_error_t
+hppe_port_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_cnt_u *value);
+
+sw_error_t
+hppe_port_reacted_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_reacted_cnt_u *value);
+
+sw_error_t
+hppe_port_reacted_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_reacted_cnt_u *value);
+
+sw_error_t
+hppe_shared_group_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union shared_group_cnt_u *value);
+
+sw_error_t
+hppe_shared_group_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union shared_group_cnt_u *value);
+
+sw_error_t
+hppe_shared_group_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union shared_group_cfg_u *value);
+
+sw_error_t
+hppe_shared_group_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union shared_group_cfg_u *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_get(
+		a_uint32_t dev_id,
+		union port_profile_cnt_en_u *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_set(
+		a_uint32_t dev_id,
+		union port_profile_cnt_en_u *value);
+
+sw_error_t
+hppe_grp_profile_cnt_en_get(
+		a_uint32_t dev_id,
+		union grp_profile_cnt_en_u *value);
+
+sw_error_t
+hppe_grp_profile_cnt_en_set(
+		a_uint32_t dev_id,
+		union grp_profile_cnt_en_u *value);
+
+sw_error_t
+hppe_port_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_profile_th_cfg_u *value);
+
+sw_error_t
+hppe_port_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_profile_th_cfg_u *value);
+
+sw_error_t
+hppe_react_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union react_profile_th_cfg_u *value);
+
+sw_error_t
+hppe_react_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union react_profile_th_cfg_u *value);
+
+sw_error_t
+hppe_grp_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_profile_th_cfg_u *value);
+
+sw_error_t
+hppe_grp_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_profile_th_cfg_u *value);
+
+sw_error_t
+hppe_tot_react_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		union tot_react_profile_th_cfg_u *value);
+
+sw_error_t
+hppe_tot_react_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		union tot_react_profile_th_cfg_u *value);
+
+sw_error_t
+hppe_port_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_out_profile_cnt_u *value);
+
+sw_error_t
+hppe_port_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_out_profile_cnt_u *value);
+
+sw_error_t
+hppe_port_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_in_profile_cnt_u *value);
+
+sw_error_t
+hppe_port_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_in_profile_cnt_u *value);
+
+sw_error_t
+hppe_react_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union react_out_profile_cnt_u *value);
+
+sw_error_t
+hppe_react_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union react_out_profile_cnt_u *value);
+
+sw_error_t
+hppe_react_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union react_in_profile_cnt_u *value);
+
+sw_error_t
+hppe_react_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union react_in_profile_cnt_u *value);
+
+sw_error_t
+hppe_grp_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_out_profile_cnt_u *value);
+
+sw_error_t
+hppe_grp_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_out_profile_cnt_u *value);
+
+sw_error_t
+hppe_grp_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_in_profile_cnt_u *value);
+
+sw_error_t
+hppe_grp_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_in_profile_cnt_u *value);
+
+sw_error_t
+hppe_tot_react_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		union tot_react_out_profile_cnt_u *value);
+
+sw_error_t
+hppe_tot_react_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		union tot_react_out_profile_cnt_u *value);
+
+sw_error_t
+hppe_tot_react_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		union tot_react_in_profile_cnt_u *value);
+
+sw_error_t
+hppe_tot_react_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		union tot_react_in_profile_cnt_u *value);
+
+sw_error_t
+hppe_port_fc_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_fc_cfg_u *value);
+
+sw_error_t
+hppe_port_fc_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_fc_cfg_u *value);
+
+sw_error_t
+hppe_llm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union llm_u *value);
+
+sw_error_t
+hppe_llm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union llm_u *value);
+
+sw_error_t
+hppe_rcm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rcm_u *value);
+
+sw_error_t
+hppe_rcm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rcm_u *value);
+
+sw_error_t
+hppe_dm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union dm_u *value);
+
+sw_error_t
+hppe_dm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union dm_u *value);
+
+sw_error_t
+hppe_fb_fifo_cfg_fb_fifo_thres_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fb_fifo_cfg_fb_fifo_thres_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fp_fifo_cfg_fp_fifo_thres_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fp_fifo_cfg_fp_fifo_thres_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_deq_fifo_cfg_deq_fifo_thres_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_deq_fifo_cfg_deq_fifo_thres_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tick_dly_cfg_tick_dly_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_tick_dly_cfg_tick_dly_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_bm_rsv_0_rsv_0_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_bm_rsv_0_rsv_0_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_bm_rsv_1_rsv_1_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_bm_rsv_1_rsv_1_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_bm_dbg_addr_dbg_addr_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_bm_dbg_addr_dbg_addr_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_bm_dbg_data_dbg_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_bm_dbg_data_dbg_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_fc_mode_fc_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_fc_mode_fc_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_fc_status_port_fc_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_fc_status_port_fc_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_fc_status_port_xon_th_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_fc_status_port_xon_th_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_group_id_port_shared_group_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_group_id_port_shared_group_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_cnt_port_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_cnt_port_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_reacted_cnt_port_reacted_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_reacted_cnt_port_reacted_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_shared_group_cnt_shared_group_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_shared_group_cnt_shared_group_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_shared_group_cfg_shared_group_limit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_shared_group_cfg_shared_group_limit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_8_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_8_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_7_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_7_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_6_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_6_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_2_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_2_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_8_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_8_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_5_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_5_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_12_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_12_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_4_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_4_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_3_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_3_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_10_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_10_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_4_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_4_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_5_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_5_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_14_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_14_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_14_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_14_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_3_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_3_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_1_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_1_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_0_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_0_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_7_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_7_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_13_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_13_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_6_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_6_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_0_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_0_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_13_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_13_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_11_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_11_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_1_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_1_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_12_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_12_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_11_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_11_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_10_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_10_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_9_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_9_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_2_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_2_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_9_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_9_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_3_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_3_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_grp_profile_cnt_en_tot_rect_cnt_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_grp_profile_cnt_en_tot_rect_cnt_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_1_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_1_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_0_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_0_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_2_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_2_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_profile_th_cfg_port_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_profile_th_cfg_port_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_react_profile_th_cfg_react_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_react_profile_th_cfg_react_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_grp_profile_th_cfg_grp_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_grp_profile_th_cfg_grp_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tot_react_profile_th_cfg_tot_react_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_tot_react_profile_th_cfg_tot_react_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_out_profile_cnt_port_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_out_profile_cnt_port_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_in_profile_cnt_port_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_in_profile_cnt_port_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_react_out_profile_cnt_react_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_react_out_profile_cnt_react_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_react_in_profile_cnt_react_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_react_in_profile_cnt_react_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_grp_out_profile_cnt_grp_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_grp_out_profile_cnt_grp_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_grp_in_profile_cnt_grp_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_grp_in_profile_cnt_grp_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tot_react_out_profile_cnt_tot_react_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_tot_react_out_profile_cnt_tot_react_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_tot_react_in_profile_cnt_tot_react_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_tot_react_in_profile_cnt_tot_react_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_fc_cfg_port_pre_alloc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_fc_cfg_port_pre_alloc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_fc_cfg_port_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_fc_cfg_port_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_fc_cfg_port_shared_dynamic_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_fc_cfg_port_shared_dynamic_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_fc_cfg_port_shared_weight_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_fc_cfg_port_shared_weight_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_fc_cfg_port_resume_floor_th_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_fc_cfg_port_resume_floor_th_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_fc_cfg_port_react_limit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_fc_cfg_port_react_limit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_fc_cfg_port_shared_ceiling_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_fc_cfg_port_shared_ceiling_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_llm_eop_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_llm_eop_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_llm_nxt_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_llm_nxt_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rcm_ref_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rcm_ref_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_dm_pkt_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_dm_pkt_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+#endif
+
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_bm_reg.h b/qca-ssdk/include/hsl/hppe/hppe_bm_reg.h
new file mode 100755
index 0000000..8b4d98f
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_bm_reg.h
@@ -0,0 +1,1036 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_BM_REG_H
+#define HPPE_BM_REG_H
+
+/*[register] FB_FIFO_CFG*/
+#define FB_FIFO_CFG
+#define FB_FIFO_CFG_ADDRESS 0x0
+#define FB_FIFO_CFG_NUM     1
+#define FB_FIFO_CFG_INC     0x4
+#define FB_FIFO_CFG_TYPE    REG_TYPE_RW
+#define FB_FIFO_CFG_DEFAULT 0x10
+	/*[field] FB_FIFO_THRES*/
+	#define FB_FIFO_CFG_FB_FIFO_THRES
+	#define FB_FIFO_CFG_FB_FIFO_THRES_OFFSET  0
+	#define FB_FIFO_CFG_FB_FIFO_THRES_LEN     5
+	#define FB_FIFO_CFG_FB_FIFO_THRES_DEFAULT 0x10
+
+struct fb_fifo_cfg {
+	a_uint32_t  fb_fifo_thres:5;
+	a_uint32_t  _reserved0:27;
+};
+
+union fb_fifo_cfg_u {
+	a_uint32_t val;
+	struct fb_fifo_cfg bf;
+};
+
+/*[register] FP_FIFO_CFG*/
+#define FP_FIFO_CFG
+#define FP_FIFO_CFG_ADDRESS 0x4
+#define FP_FIFO_CFG_NUM     1
+#define FP_FIFO_CFG_INC     0x4
+#define FP_FIFO_CFG_TYPE    REG_TYPE_RW
+#define FP_FIFO_CFG_DEFAULT 0x10
+	/*[field] FP_FIFO_THRES*/
+	#define FP_FIFO_CFG_FP_FIFO_THRES
+	#define FP_FIFO_CFG_FP_FIFO_THRES_OFFSET  0
+	#define FP_FIFO_CFG_FP_FIFO_THRES_LEN     5
+	#define FP_FIFO_CFG_FP_FIFO_THRES_DEFAULT 0x10
+
+struct fp_fifo_cfg {
+	a_uint32_t  fp_fifo_thres:5;
+	a_uint32_t  _reserved0:27;
+};
+
+union fp_fifo_cfg_u {
+	a_uint32_t val;
+	struct fp_fifo_cfg bf;
+};
+
+/*[register] DEQ_FIFO_CFG*/
+#define DEQ_FIFO_CFG
+#define DEQ_FIFO_CFG_ADDRESS 0x8
+#define DEQ_FIFO_CFG_NUM     9
+#define DEQ_FIFO_CFG_INC     0x4
+#define DEQ_FIFO_CFG_TYPE    REG_TYPE_RW
+#define DEQ_FIFO_CFG_DEFAULT 0x2
+	/*[field] DEQ_FIFO_THRES*/
+	#define DEQ_FIFO_CFG_DEQ_FIFO_THRES
+	#define DEQ_FIFO_CFG_DEQ_FIFO_THRES_OFFSET  0
+	#define DEQ_FIFO_CFG_DEQ_FIFO_THRES_LEN     3
+	#define DEQ_FIFO_CFG_DEQ_FIFO_THRES_DEFAULT 0x2
+
+struct deq_fifo_cfg {
+	a_uint32_t  deq_fifo_thres:3;
+	a_uint32_t  _reserved0:29;
+};
+
+union deq_fifo_cfg_u {
+	a_uint32_t val;
+	struct deq_fifo_cfg bf;
+};
+
+/*[register] TICK_DLY_CFG*/
+#define TICK_DLY_CFG
+#define TICK_DLY_CFG_ADDRESS 0x2c
+#define TICK_DLY_CFG_NUM     1
+#define TICK_DLY_CFG_INC     0x4
+#define TICK_DLY_CFG_TYPE    REG_TYPE_RW
+#define TICK_DLY_CFG_DEFAULT 0x0
+	/*[field] TICK_DLY*/
+	#define TICK_DLY_CFG_TICK_DLY
+	#define TICK_DLY_CFG_TICK_DLY_OFFSET  0
+	#define TICK_DLY_CFG_TICK_DLY_LEN     1
+	#define TICK_DLY_CFG_TICK_DLY_DEFAULT 0x0
+
+struct tick_dly_cfg {
+	a_uint32_t  tick_dly:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union tick_dly_cfg_u {
+	a_uint32_t val;
+	struct tick_dly_cfg bf;
+};
+
+/*[register] BM_RSV_0*/
+#define BM_RSV_0
+#define BM_RSV_0_ADDRESS 0x30
+#define BM_RSV_0_NUM     1
+#define BM_RSV_0_INC     0x4
+#define BM_RSV_0_TYPE    REG_TYPE_RW
+#define BM_RSV_0_DEFAULT 0x0
+	/*[field] RSV_0*/
+	#define BM_RSV_0_RSV_0
+	#define BM_RSV_0_RSV_0_OFFSET  0
+	#define BM_RSV_0_RSV_0_LEN     32
+	#define BM_RSV_0_RSV_0_DEFAULT 0x0
+
+struct bm_rsv_0 {
+	a_uint32_t  rsv_0:32;
+};
+
+union bm_rsv_0_u {
+	a_uint32_t val;
+	struct bm_rsv_0 bf;
+};
+
+/*[register] BM_RSV_1*/
+#define BM_RSV_1
+#define BM_RSV_1_ADDRESS 0x34
+#define BM_RSV_1_NUM     1
+#define BM_RSV_1_INC     0x4
+#define BM_RSV_1_TYPE    REG_TYPE_RW
+#define BM_RSV_1_DEFAULT 0x0
+	/*[field] RSV_1*/
+	#define BM_RSV_1_RSV_1
+	#define BM_RSV_1_RSV_1_OFFSET  0
+	#define BM_RSV_1_RSV_1_LEN     32
+	#define BM_RSV_1_RSV_1_DEFAULT 0x0
+
+struct bm_rsv_1 {
+	a_uint32_t  rsv_1:32;
+};
+
+union bm_rsv_1_u {
+	a_uint32_t val;
+	struct bm_rsv_1 bf;
+};
+
+/*[register] BM_DBG_ADDR*/
+#define BM_DBG_ADDR
+#define BM_DBG_ADDR_ADDRESS 0x80
+#define BM_DBG_ADDR_NUM     1
+#define BM_DBG_ADDR_INC     0x4
+#define BM_DBG_ADDR_TYPE    REG_TYPE_RW
+#define BM_DBG_ADDR_DEFAULT 0x0
+	/*[field] DBG_ADDR*/
+	#define BM_DBG_ADDR_DBG_ADDR
+	#define BM_DBG_ADDR_DBG_ADDR_OFFSET  0
+	#define BM_DBG_ADDR_DBG_ADDR_LEN     8
+	#define BM_DBG_ADDR_DBG_ADDR_DEFAULT 0x0
+
+struct bm_dbg_addr {
+	a_uint32_t  dbg_addr:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union bm_dbg_addr_u {
+	a_uint32_t val;
+	struct bm_dbg_addr bf;
+};
+
+/*[register] BM_DBG_DATA*/
+#define BM_DBG_DATA
+#define BM_DBG_DATA_ADDRESS 0x84
+#define BM_DBG_DATA_NUM     1
+#define BM_DBG_DATA_INC     0x4
+#define BM_DBG_DATA_TYPE    REG_TYPE_RO
+#define BM_DBG_DATA_DEFAULT 0x0
+	/*[field] DBG_DATA*/
+	#define BM_DBG_DATA_DBG_DATA
+	#define BM_DBG_DATA_DBG_DATA_OFFSET  0
+	#define BM_DBG_DATA_DBG_DATA_LEN     32
+	#define BM_DBG_DATA_DBG_DATA_DEFAULT 0x0
+
+struct bm_dbg_data {
+	a_uint32_t  dbg_data:32;
+};
+
+union bm_dbg_data_u {
+	a_uint32_t val;
+	struct bm_dbg_data bf;
+};
+
+/*[register] PORT_FC_MODE*/
+#define PORT_FC_MODE
+#define PORT_FC_MODE_ADDRESS 0x100
+#define PORT_FC_MODE_NUM     15
+#define PORT_FC_MODE_INC     0x4
+#define PORT_FC_MODE_TYPE    REG_TYPE_RW
+#define PORT_FC_MODE_DEFAULT 0x0
+	/*[field] FC_EN*/
+	#define PORT_FC_MODE_FC_EN
+	#define PORT_FC_MODE_FC_EN_OFFSET  0
+	#define PORT_FC_MODE_FC_EN_LEN     1
+	#define PORT_FC_MODE_FC_EN_DEFAULT 0x0
+
+struct port_fc_mode {
+	a_uint32_t  fc_en:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union port_fc_mode_u {
+	a_uint32_t val;
+	struct port_fc_mode bf;
+};
+
+/*[register] PORT_FC_STATUS*/
+#define PORT_FC_STATUS
+#define PORT_FC_STATUS_ADDRESS 0x140
+#define PORT_FC_STATUS_NUM     15
+#define PORT_FC_STATUS_INC     0x4
+#define PORT_FC_STATUS_TYPE    REG_TYPE_RO
+#define PORT_FC_STATUS_DEFAULT 0x0
+	/*[field] PORT_XON_TH*/
+	#define PORT_FC_STATUS_PORT_XON_TH
+	#define PORT_FC_STATUS_PORT_XON_TH_OFFSET  0
+	#define PORT_FC_STATUS_PORT_XON_TH_LEN     11
+	#define PORT_FC_STATUS_PORT_XON_TH_DEFAULT 0x0
+	/*[field] PORT_FC_STATUS*/
+	#define PORT_FC_STATUS_PORT_FC_STATUS
+	#define PORT_FC_STATUS_PORT_FC_STATUS_OFFSET  16
+	#define PORT_FC_STATUS_PORT_FC_STATUS_LEN     2
+	#define PORT_FC_STATUS_PORT_FC_STATUS_DEFAULT 0x0
+
+struct port_fc_status {
+	a_uint32_t  port_xon_th:11;
+	a_uint32_t  _reserved0:5;
+	a_uint32_t  port_fc_status:2;
+	a_uint32_t  _reserved1:14;
+};
+
+union port_fc_status_u {
+	a_uint32_t val;
+	struct port_fc_status bf;
+};
+
+/*[register] PORT_GROUP_ID*/
+#define PORT_GROUP_ID
+#define PORT_GROUP_ID_ADDRESS 0x180
+#define PORT_GROUP_ID_NUM     15
+#define PORT_GROUP_ID_INC     0x4
+#define PORT_GROUP_ID_TYPE    REG_TYPE_RW
+#define PORT_GROUP_ID_DEFAULT 0x0
+	/*[field] PORT_SHARED_GROUP_ID*/
+	#define PORT_GROUP_ID_PORT_SHARED_GROUP_ID
+	#define PORT_GROUP_ID_PORT_SHARED_GROUP_ID_OFFSET  0
+	#define PORT_GROUP_ID_PORT_SHARED_GROUP_ID_LEN     2
+	#define PORT_GROUP_ID_PORT_SHARED_GROUP_ID_DEFAULT 0x0
+
+struct port_group_id {
+	a_uint32_t  port_shared_group_id:2;
+	a_uint32_t  _reserved0:30;
+};
+
+union port_group_id_u {
+	a_uint32_t val;
+	struct port_group_id bf;
+};
+
+/*[register] PORT_CNT*/
+#define PORT_CNT
+#define PORT_CNT_ADDRESS 0x1c0
+#define PORT_CNT_NUM     15
+#define PORT_CNT_INC     0x4
+#define PORT_CNT_TYPE    REG_TYPE_RO
+#define PORT_CNT_DEFAULT 0x0
+	/*[field] PORT_CNT*/
+	#define PORT_CNT_PORT_CNT
+	#define PORT_CNT_PORT_CNT_OFFSET  0
+	#define PORT_CNT_PORT_CNT_LEN     11
+	#define PORT_CNT_PORT_CNT_DEFAULT 0x0
+
+struct port_cnt {
+	a_uint32_t  port_cnt:11;
+	a_uint32_t  _reserved0:21;
+};
+
+union port_cnt_u {
+	a_uint32_t val;
+	struct port_cnt bf;
+};
+
+/*[register] PORT_REACTED_CNT*/
+#define PORT_REACTED_CNT
+#define PORT_REACTED_CNT_ADDRESS 0x240
+#define PORT_REACTED_CNT_NUM     15
+#define PORT_REACTED_CNT_INC     0x4
+#define PORT_REACTED_CNT_TYPE    REG_TYPE_RO
+#define PORT_REACTED_CNT_DEFAULT 0x0
+	/*[field] PORT_REACTED_CNT*/
+	#define PORT_REACTED_CNT_PORT_REACTED_CNT
+	#define PORT_REACTED_CNT_PORT_REACTED_CNT_OFFSET  0
+	#define PORT_REACTED_CNT_PORT_REACTED_CNT_LEN     9
+	#define PORT_REACTED_CNT_PORT_REACTED_CNT_DEFAULT 0x0
+
+struct port_reacted_cnt {
+	a_uint32_t  port_reacted_cnt:9;
+	a_uint32_t  _reserved0:23;
+};
+
+union port_reacted_cnt_u {
+	a_uint32_t val;
+	struct port_reacted_cnt bf;
+};
+
+/*[register] SHARED_GROUP_CNT*/
+#define SHARED_GROUP_CNT
+#define SHARED_GROUP_CNT_ADDRESS 0x280
+#define SHARED_GROUP_CNT_NUM     4
+#define SHARED_GROUP_CNT_INC     0x4
+#define SHARED_GROUP_CNT_TYPE    REG_TYPE_RO
+#define SHARED_GROUP_CNT_DEFAULT 0x0
+	/*[field] SHARED_GROUP_CNT*/
+	#define SHARED_GROUP_CNT_SHARED_GROUP_CNT
+	#define SHARED_GROUP_CNT_SHARED_GROUP_CNT_OFFSET  0
+	#define SHARED_GROUP_CNT_SHARED_GROUP_CNT_LEN     11
+	#define SHARED_GROUP_CNT_SHARED_GROUP_CNT_DEFAULT 0x0
+
+struct shared_group_cnt {
+	a_uint32_t  shared_group_cnt:11;
+	a_uint32_t  _reserved0:21;
+};
+
+union shared_group_cnt_u {
+	a_uint32_t val;
+	struct shared_group_cnt bf;
+};
+
+/*[register] SHARED_GROUP_CFG*/
+#define SHARED_GROUP_CFG
+#define SHARED_GROUP_CFG_ADDRESS 0x290
+#define SHARED_GROUP_CFG_NUM     4
+#define SHARED_GROUP_CFG_INC     0x4
+#define SHARED_GROUP_CFG_TYPE    REG_TYPE_RW
+#define SHARED_GROUP_CFG_DEFAULT 0x0
+	/*[field] SHARED_GROUP_LIMIT*/
+	#define SHARED_GROUP_CFG_SHARED_GROUP_LIMIT
+	#define SHARED_GROUP_CFG_SHARED_GROUP_LIMIT_OFFSET  0
+	#define SHARED_GROUP_CFG_SHARED_GROUP_LIMIT_LEN     11
+	#define SHARED_GROUP_CFG_SHARED_GROUP_LIMIT_DEFAULT 0x0
+
+struct shared_group_cfg {
+	a_uint32_t  shared_group_limit:11;
+	a_uint32_t  _reserved0:21;
+};
+
+union shared_group_cfg_u {
+	a_uint32_t val;
+	struct shared_group_cfg bf;
+};
+
+/*[register] PORT_PROFILE_CNT_EN*/
+#define PORT_PROFILE_CNT_EN
+#define PORT_PROFILE_CNT_EN_ADDRESS 0x300
+#define PORT_PROFILE_CNT_EN_NUM     1
+#define PORT_PROFILE_CNT_EN_INC     0x4
+#define PORT_PROFILE_CNT_EN_TYPE    REG_TYPE_RW
+#define PORT_PROFILE_CNT_EN_DEFAULT 0x0
+	/*[field] PORT_CNT_EN_0*/
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_0
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_0_OFFSET  0
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_0_LEN     1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_0_DEFAULT 0x0
+	/*[field] PORT_CNT_EN_1*/
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_1_OFFSET  1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_1_LEN     1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_1_DEFAULT 0x0
+	/*[field] PORT_CNT_EN_2*/
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_2
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_2_OFFSET  2
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_2_LEN     1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_2_DEFAULT 0x0
+	/*[field] PORT_CNT_EN_3*/
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_3
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_3_OFFSET  3
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_3_LEN     1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_3_DEFAULT 0x0
+	/*[field] PORT_CNT_EN_4*/
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_4
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_4_OFFSET  4
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_4_LEN     1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_4_DEFAULT 0x0
+	/*[field] PORT_CNT_EN_5*/
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_5
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_5_OFFSET  5
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_5_LEN     1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_5_DEFAULT 0x0
+	/*[field] PORT_CNT_EN_6*/
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_6
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_6_OFFSET  6
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_6_LEN     1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_6_DEFAULT 0x0
+	/*[field] PORT_CNT_EN_7*/
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_7
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_7_OFFSET  7
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_7_LEN     1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_7_DEFAULT 0x0
+	/*[field] PORT_CNT_EN_8*/
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_8
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_8_OFFSET  8
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_8_LEN     1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_8_DEFAULT 0x0
+	/*[field] PORT_CNT_EN_9*/
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_9
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_9_OFFSET  9
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_9_LEN     1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_9_DEFAULT 0x0
+	/*[field] PORT_CNT_EN_10*/
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_10
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_10_OFFSET  10
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_10_LEN     1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_10_DEFAULT 0x0
+	/*[field] PORT_CNT_EN_11*/
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_11
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_11_OFFSET  11
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_11_LEN     1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_11_DEFAULT 0x0
+	/*[field] PORT_CNT_EN_12*/
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_12
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_12_OFFSET  12
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_12_LEN     1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_12_DEFAULT 0x0
+	/*[field] PORT_CNT_EN_13*/
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_13
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_13_OFFSET  13
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_13_LEN     1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_13_DEFAULT 0x0
+	/*[field] PORT_CNT_EN_14*/
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_14
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_14_OFFSET  14
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_14_LEN     1
+	#define PORT_PROFILE_CNT_EN_PORT_CNT_EN_14_DEFAULT 0x0
+	/*[field] REACT_CNT_EN_0*/
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_0
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_0_OFFSET  16
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_0_LEN     1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_0_DEFAULT 0x0
+	/*[field] REACT_CNT_EN_1*/
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_1_OFFSET  17
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_1_LEN     1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_1_DEFAULT 0x0
+	/*[field] REACT_CNT_EN_2*/
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_2
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_2_OFFSET  18
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_2_LEN     1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_2_DEFAULT 0x0
+	/*[field] REACT_CNT_EN_3*/
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_3
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_3_OFFSET  19
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_3_LEN     1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_3_DEFAULT 0x0
+	/*[field] REACT_CNT_EN_4*/
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_4
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_4_OFFSET  20
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_4_LEN     1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_4_DEFAULT 0x0
+	/*[field] REACT_CNT_EN_5*/
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_5
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_5_OFFSET  21
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_5_LEN     1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_5_DEFAULT 0x0
+	/*[field] REACT_CNT_EN_6*/
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_6
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_6_OFFSET  22
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_6_LEN     1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_6_DEFAULT 0x0
+	/*[field] REACT_CNT_EN_7*/
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_7
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_7_OFFSET  23
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_7_LEN     1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_7_DEFAULT 0x0
+	/*[field] REACT_CNT_EN_8*/
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_8
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_8_OFFSET  24
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_8_LEN     1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_8_DEFAULT 0x0
+	/*[field] REACT_CNT_EN_9*/
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_9
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_9_OFFSET  25
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_9_LEN     1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_9_DEFAULT 0x0
+	/*[field] REACT_CNT_EN_10*/
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_10
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_10_OFFSET  26
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_10_LEN     1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_10_DEFAULT 0x0
+	/*[field] REACT_CNT_EN_11*/
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_11
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_11_OFFSET  27
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_11_LEN     1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_11_DEFAULT 0x0
+	/*[field] REACT_CNT_EN_12*/
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_12
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_12_OFFSET  28
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_12_LEN     1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_12_DEFAULT 0x0
+	/*[field] REACT_CNT_EN_13*/
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_13
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_13_OFFSET  29
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_13_LEN     1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_13_DEFAULT 0x0
+	/*[field] REACT_CNT_EN_14*/
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_14
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_14_OFFSET  30
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_14_LEN     1
+	#define PORT_PROFILE_CNT_EN_REACT_CNT_EN_14_DEFAULT 0x0
+
+struct port_profile_cnt_en {
+	a_uint32_t  port_cnt_en_0:1;
+	a_uint32_t  port_cnt_en_1:1;
+	a_uint32_t  port_cnt_en_2:1;
+	a_uint32_t  port_cnt_en_3:1;
+	a_uint32_t  port_cnt_en_4:1;
+	a_uint32_t  port_cnt_en_5:1;
+	a_uint32_t  port_cnt_en_6:1;
+	a_uint32_t  port_cnt_en_7:1;
+	a_uint32_t  port_cnt_en_8:1;
+	a_uint32_t  port_cnt_en_9:1;
+	a_uint32_t  port_cnt_en_10:1;
+	a_uint32_t  port_cnt_en_11:1;
+	a_uint32_t  port_cnt_en_12:1;
+	a_uint32_t  port_cnt_en_13:1;
+	a_uint32_t  port_cnt_en_14:1;
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  react_cnt_en_0:1;
+	a_uint32_t  react_cnt_en_1:1;
+	a_uint32_t  react_cnt_en_2:1;
+	a_uint32_t  react_cnt_en_3:1;
+	a_uint32_t  react_cnt_en_4:1;
+	a_uint32_t  react_cnt_en_5:1;
+	a_uint32_t  react_cnt_en_6:1;
+	a_uint32_t  react_cnt_en_7:1;
+	a_uint32_t  react_cnt_en_8:1;
+	a_uint32_t  react_cnt_en_9:1;
+	a_uint32_t  react_cnt_en_10:1;
+	a_uint32_t  react_cnt_en_11:1;
+	a_uint32_t  react_cnt_en_12:1;
+	a_uint32_t  react_cnt_en_13:1;
+	a_uint32_t  react_cnt_en_14:1;
+	a_uint32_t  _reserved1:1;
+};
+
+union port_profile_cnt_en_u {
+	a_uint32_t val;
+	struct port_profile_cnt_en bf;
+};
+
+/*[register] GRP_PROFILE_CNT_EN*/
+#define GRP_PROFILE_CNT_EN
+#define GRP_PROFILE_CNT_EN_ADDRESS 0x304
+#define GRP_PROFILE_CNT_EN_NUM     1
+#define GRP_PROFILE_CNT_EN_INC     0x4
+#define GRP_PROFILE_CNT_EN_TYPE    REG_TYPE_RW
+#define GRP_PROFILE_CNT_EN_DEFAULT 0x0
+	/*[field] GRP_CNT_EN_0*/
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_0
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_0_OFFSET  0
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_0_LEN     1
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_0_DEFAULT 0x0
+	/*[field] GRP_CNT_EN_1*/
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_1
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_1_OFFSET  1
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_1_LEN     1
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_1_DEFAULT 0x0
+	/*[field] GRP_CNT_EN_2*/
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_2
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_2_OFFSET  2
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_2_LEN     1
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_2_DEFAULT 0x0
+	/*[field] GRP_CNT_EN_3*/
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_3
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_3_OFFSET  3
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_3_LEN     1
+	#define GRP_PROFILE_CNT_EN_GRP_CNT_EN_3_DEFAULT 0x0
+	/*[field] TOT_RECT_CNT_EN*/
+	#define GRP_PROFILE_CNT_EN_TOT_RECT_CNT_EN
+	#define GRP_PROFILE_CNT_EN_TOT_RECT_CNT_EN_OFFSET  4
+	#define GRP_PROFILE_CNT_EN_TOT_RECT_CNT_EN_LEN     1
+	#define GRP_PROFILE_CNT_EN_TOT_RECT_CNT_EN_DEFAULT 0x0
+
+struct grp_profile_cnt_en {
+	a_uint32_t  grp_cnt_en_0:1;
+	a_uint32_t  grp_cnt_en_1:1;
+	a_uint32_t  grp_cnt_en_2:1;
+	a_uint32_t  grp_cnt_en_3:1;
+	a_uint32_t  tot_rect_cnt_en:1;
+	a_uint32_t  _reserved0:27;
+};
+
+union grp_profile_cnt_en_u {
+	a_uint32_t val;
+	struct grp_profile_cnt_en bf;
+};
+
+/*[register] PORT_PROFILE_TH_CFG*/
+#define PORT_PROFILE_TH_CFG
+#define PORT_PROFILE_TH_CFG_ADDRESS 0x308
+#define PORT_PROFILE_TH_CFG_NUM     15
+#define PORT_PROFILE_TH_CFG_INC     0x4
+#define PORT_PROFILE_TH_CFG_TYPE    REG_TYPE_RW
+#define PORT_PROFILE_TH_CFG_DEFAULT 0x0
+	/*[field] PORT_PROFILE_TH_CFG*/
+	#define PORT_PROFILE_TH_CFG_PORT_PROFILE_TH_CFG
+	#define PORT_PROFILE_TH_CFG_PORT_PROFILE_TH_CFG_OFFSET  0
+	#define PORT_PROFILE_TH_CFG_PORT_PROFILE_TH_CFG_LEN     11
+	#define PORT_PROFILE_TH_CFG_PORT_PROFILE_TH_CFG_DEFAULT 0x0
+
+struct port_profile_th_cfg {
+	a_uint32_t  port_profile_th_cfg:11;
+	a_uint32_t  _reserved0:21;
+};
+
+union port_profile_th_cfg_u {
+	a_uint32_t val;
+	struct port_profile_th_cfg bf;
+};
+
+/*[register] REACT_PROFILE_TH_CFG*/
+#define REACT_PROFILE_TH_CFG
+#define REACT_PROFILE_TH_CFG_ADDRESS 0x348
+#define REACT_PROFILE_TH_CFG_NUM     15
+#define REACT_PROFILE_TH_CFG_INC     0x4
+#define REACT_PROFILE_TH_CFG_TYPE    REG_TYPE_RW
+#define REACT_PROFILE_TH_CFG_DEFAULT 0x0
+	/*[field] REACT_PROFILE_TH_CFG*/
+	#define REACT_PROFILE_TH_CFG_REACT_PROFILE_TH_CFG
+	#define REACT_PROFILE_TH_CFG_REACT_PROFILE_TH_CFG_OFFSET  0
+	#define REACT_PROFILE_TH_CFG_REACT_PROFILE_TH_CFG_LEN     9
+	#define REACT_PROFILE_TH_CFG_REACT_PROFILE_TH_CFG_DEFAULT 0x0
+
+struct react_profile_th_cfg {
+	a_uint32_t  react_profile_th_cfg:9;
+	a_uint32_t  _reserved0:23;
+};
+
+union react_profile_th_cfg_u {
+	a_uint32_t val;
+	struct react_profile_th_cfg bf;
+};
+
+/*[register] GRP_PROFILE_TH_CFG*/
+#define GRP_PROFILE_TH_CFG
+#define GRP_PROFILE_TH_CFG_ADDRESS 0x388
+#define GRP_PROFILE_TH_CFG_NUM     4
+#define GRP_PROFILE_TH_CFG_INC     0x4
+#define GRP_PROFILE_TH_CFG_TYPE    REG_TYPE_RW
+#define GRP_PROFILE_TH_CFG_DEFAULT 0x0
+	/*[field] GRP_PROFILE_TH_CFG*/
+	#define GRP_PROFILE_TH_CFG_GRP_PROFILE_TH_CFG
+	#define GRP_PROFILE_TH_CFG_GRP_PROFILE_TH_CFG_OFFSET  0
+	#define GRP_PROFILE_TH_CFG_GRP_PROFILE_TH_CFG_LEN     11
+	#define GRP_PROFILE_TH_CFG_GRP_PROFILE_TH_CFG_DEFAULT 0x0
+
+struct grp_profile_th_cfg {
+	a_uint32_t  grp_profile_th_cfg:11;
+	a_uint32_t  _reserved0:21;
+};
+
+union grp_profile_th_cfg_u {
+	a_uint32_t val;
+	struct grp_profile_th_cfg bf;
+};
+
+/*[register] TOT_REACT_PROFILE_TH_CFG*/
+#define TOT_REACT_PROFILE_TH_CFG
+#define TOT_REACT_PROFILE_TH_CFG_ADDRESS 0x398
+#define TOT_REACT_PROFILE_TH_CFG_NUM     1
+#define TOT_REACT_PROFILE_TH_CFG_INC     0x4
+#define TOT_REACT_PROFILE_TH_CFG_TYPE    REG_TYPE_RW
+#define TOT_REACT_PROFILE_TH_CFG_DEFAULT 0x0
+	/*[field] TOT_REACT_PROFILE_TH_CFG*/
+	#define TOT_REACT_PROFILE_TH_CFG_TOT_REACT_PROFILE_TH_CFG
+	#define TOT_REACT_PROFILE_TH_CFG_TOT_REACT_PROFILE_TH_CFG_OFFSET  0
+	#define TOT_REACT_PROFILE_TH_CFG_TOT_REACT_PROFILE_TH_CFG_LEN     11
+	#define TOT_REACT_PROFILE_TH_CFG_TOT_REACT_PROFILE_TH_CFG_DEFAULT 0x0
+
+struct tot_react_profile_th_cfg {
+	a_uint32_t  tot_react_profile_th_cfg:11;
+	a_uint32_t  _reserved0:21;
+};
+
+union tot_react_profile_th_cfg_u {
+	a_uint32_t val;
+	struct tot_react_profile_th_cfg bf;
+};
+
+/*[register] PORT_OUT_PROFILE_CNT*/
+#define PORT_OUT_PROFILE_CNT
+#define PORT_OUT_PROFILE_CNT_ADDRESS 0x3a0
+#define PORT_OUT_PROFILE_CNT_NUM     15
+#define PORT_OUT_PROFILE_CNT_INC     0x4
+#define PORT_OUT_PROFILE_CNT_TYPE    REG_TYPE_RW
+#define PORT_OUT_PROFILE_CNT_DEFAULT 0x0
+	/*[field] PORT_OUT_PROFILE_CNT*/
+	#define PORT_OUT_PROFILE_CNT_PORT_OUT_PROFILE_CNT
+	#define PORT_OUT_PROFILE_CNT_PORT_OUT_PROFILE_CNT_OFFSET  0
+	#define PORT_OUT_PROFILE_CNT_PORT_OUT_PROFILE_CNT_LEN     32
+	#define PORT_OUT_PROFILE_CNT_PORT_OUT_PROFILE_CNT_DEFAULT 0x0
+
+struct port_out_profile_cnt {
+	a_uint32_t  port_out_profile_cnt:32;
+};
+
+union port_out_profile_cnt_u {
+	a_uint32_t val;
+	struct port_out_profile_cnt bf;
+};
+
+/*[register] PORT_IN_PROFILE_CNT*/
+#define PORT_IN_PROFILE_CNT
+#define PORT_IN_PROFILE_CNT_ADDRESS 0x3e0
+#define PORT_IN_PROFILE_CNT_NUM     15
+#define PORT_IN_PROFILE_CNT_INC     0x4
+#define PORT_IN_PROFILE_CNT_TYPE    REG_TYPE_RW
+#define PORT_IN_PROFILE_CNT_DEFAULT 0x0
+	/*[field] PORT_IN_PROFILE_CNT*/
+	#define PORT_IN_PROFILE_CNT_PORT_IN_PROFILE_CNT
+	#define PORT_IN_PROFILE_CNT_PORT_IN_PROFILE_CNT_OFFSET  0
+	#define PORT_IN_PROFILE_CNT_PORT_IN_PROFILE_CNT_LEN     32
+	#define PORT_IN_PROFILE_CNT_PORT_IN_PROFILE_CNT_DEFAULT 0x0
+
+struct port_in_profile_cnt {
+	a_uint32_t  port_in_profile_cnt:32;
+};
+
+union port_in_profile_cnt_u {
+	a_uint32_t val;
+	struct port_in_profile_cnt bf;
+};
+
+/*[register] REACT_OUT_PROFILE_CNT*/
+#define REACT_OUT_PROFILE_CNT
+#define REACT_OUT_PROFILE_CNT_ADDRESS 0x420
+#define REACT_OUT_PROFILE_CNT_NUM     15
+#define REACT_OUT_PROFILE_CNT_INC     0x4
+#define REACT_OUT_PROFILE_CNT_TYPE    REG_TYPE_RW
+#define REACT_OUT_PROFILE_CNT_DEFAULT 0x0
+	/*[field] REACT_OUT_PROFILE_CNT*/
+	#define REACT_OUT_PROFILE_CNT_REACT_OUT_PROFILE_CNT
+	#define REACT_OUT_PROFILE_CNT_REACT_OUT_PROFILE_CNT_OFFSET  0
+	#define REACT_OUT_PROFILE_CNT_REACT_OUT_PROFILE_CNT_LEN     32
+	#define REACT_OUT_PROFILE_CNT_REACT_OUT_PROFILE_CNT_DEFAULT 0x0
+
+struct react_out_profile_cnt {
+	a_uint32_t  react_out_profile_cnt:32;
+};
+
+union react_out_profile_cnt_u {
+	a_uint32_t val;
+	struct react_out_profile_cnt bf;
+};
+
+/*[register] REACT_IN_PROFILE_CNT*/
+#define REACT_IN_PROFILE_CNT
+#define REACT_IN_PROFILE_CNT_ADDRESS 0x460
+#define REACT_IN_PROFILE_CNT_NUM     15
+#define REACT_IN_PROFILE_CNT_INC     0x4
+#define REACT_IN_PROFILE_CNT_TYPE    REG_TYPE_RW
+#define REACT_IN_PROFILE_CNT_DEFAULT 0x0
+	/*[field] REACT_IN_PROFILE_CNT*/
+	#define REACT_IN_PROFILE_CNT_REACT_IN_PROFILE_CNT
+	#define REACT_IN_PROFILE_CNT_REACT_IN_PROFILE_CNT_OFFSET  0
+	#define REACT_IN_PROFILE_CNT_REACT_IN_PROFILE_CNT_LEN     32
+	#define REACT_IN_PROFILE_CNT_REACT_IN_PROFILE_CNT_DEFAULT 0x0
+
+struct react_in_profile_cnt {
+	a_uint32_t  react_in_profile_cnt:32;
+};
+
+union react_in_profile_cnt_u {
+	a_uint32_t val;
+	struct react_in_profile_cnt bf;
+};
+
+/*[register] GRP_OUT_PROFILE_CNT*/
+#define GRP_OUT_PROFILE_CNT
+#define GRP_OUT_PROFILE_CNT_ADDRESS 0x4a0
+#define GRP_OUT_PROFILE_CNT_NUM     4
+#define GRP_OUT_PROFILE_CNT_INC     0x4
+#define GRP_OUT_PROFILE_CNT_TYPE    REG_TYPE_RW
+#define GRP_OUT_PROFILE_CNT_DEFAULT 0x0
+	/*[field] GRP_OUT_PROFILE_CNT*/
+	#define GRP_OUT_PROFILE_CNT_GRP_OUT_PROFILE_CNT
+	#define GRP_OUT_PROFILE_CNT_GRP_OUT_PROFILE_CNT_OFFSET  0
+	#define GRP_OUT_PROFILE_CNT_GRP_OUT_PROFILE_CNT_LEN     32
+	#define GRP_OUT_PROFILE_CNT_GRP_OUT_PROFILE_CNT_DEFAULT 0x0
+
+struct grp_out_profile_cnt {
+	a_uint32_t  grp_out_profile_cnt:32;
+};
+
+union grp_out_profile_cnt_u {
+	a_uint32_t val;
+	struct grp_out_profile_cnt bf;
+};
+
+/*[register] GRP_IN_PROFILE_CNT*/
+#define GRP_IN_PROFILE_CNT
+#define GRP_IN_PROFILE_CNT_ADDRESS 0x4b0
+#define GRP_IN_PROFILE_CNT_NUM     4
+#define GRP_IN_PROFILE_CNT_INC     0x4
+#define GRP_IN_PROFILE_CNT_TYPE    REG_TYPE_RW
+#define GRP_IN_PROFILE_CNT_DEFAULT 0x0
+	/*[field] GRP_IN_PROFILE_CNT*/
+	#define GRP_IN_PROFILE_CNT_GRP_IN_PROFILE_CNT
+	#define GRP_IN_PROFILE_CNT_GRP_IN_PROFILE_CNT_OFFSET  0
+	#define GRP_IN_PROFILE_CNT_GRP_IN_PROFILE_CNT_LEN     32
+	#define GRP_IN_PROFILE_CNT_GRP_IN_PROFILE_CNT_DEFAULT 0x0
+
+struct grp_in_profile_cnt {
+	a_uint32_t  grp_in_profile_cnt:32;
+};
+
+union grp_in_profile_cnt_u {
+	a_uint32_t val;
+	struct grp_in_profile_cnt bf;
+};
+
+/*[register] TOT_REACT_OUT_PROFILE_CNT*/
+#define TOT_REACT_OUT_PROFILE_CNT
+#define TOT_REACT_OUT_PROFILE_CNT_ADDRESS 0x4c0
+#define TOT_REACT_OUT_PROFILE_CNT_NUM     1
+#define TOT_REACT_OUT_PROFILE_CNT_INC     0x4
+#define TOT_REACT_OUT_PROFILE_CNT_TYPE    REG_TYPE_RW
+#define TOT_REACT_OUT_PROFILE_CNT_DEFAULT 0x0
+	/*[field] TOT_REACT_OUT_PROFILE_CNT*/
+	#define TOT_REACT_OUT_PROFILE_CNT_TOT_REACT_OUT_PROFILE_CNT
+	#define TOT_REACT_OUT_PROFILE_CNT_TOT_REACT_OUT_PROFILE_CNT_OFFSET  0
+	#define TOT_REACT_OUT_PROFILE_CNT_TOT_REACT_OUT_PROFILE_CNT_LEN     32
+	#define TOT_REACT_OUT_PROFILE_CNT_TOT_REACT_OUT_PROFILE_CNT_DEFAULT 0x0
+
+struct tot_react_out_profile_cnt {
+	a_uint32_t  tot_react_out_profile_cnt:32;
+};
+
+union tot_react_out_profile_cnt_u {
+	a_uint32_t val;
+	struct tot_react_out_profile_cnt bf;
+};
+
+/*[register] TOT_REACT_IN_PROFILE_CNT*/
+#define TOT_REACT_IN_PROFILE_CNT
+#define TOT_REACT_IN_PROFILE_CNT_ADDRESS 0x4c4
+#define TOT_REACT_IN_PROFILE_CNT_NUM     1
+#define TOT_REACT_IN_PROFILE_CNT_INC     0x4
+#define TOT_REACT_IN_PROFILE_CNT_TYPE    REG_TYPE_RW
+#define TOT_REACT_IN_PROFILE_CNT_DEFAULT 0x0
+	/*[field] TOT_REACT_IN_PROFILE_CNT*/
+	#define TOT_REACT_IN_PROFILE_CNT_TOT_REACT_IN_PROFILE_CNT
+	#define TOT_REACT_IN_PROFILE_CNT_TOT_REACT_IN_PROFILE_CNT_OFFSET  0
+	#define TOT_REACT_IN_PROFILE_CNT_TOT_REACT_IN_PROFILE_CNT_LEN     32
+	#define TOT_REACT_IN_PROFILE_CNT_TOT_REACT_IN_PROFILE_CNT_DEFAULT 0x0
+
+struct tot_react_in_profile_cnt {
+	a_uint32_t  tot_react_in_profile_cnt:32;
+};
+
+union tot_react_in_profile_cnt_u {
+	a_uint32_t val;
+	struct tot_react_in_profile_cnt bf;
+};
+
+/*[table] PORT_FC_CFG*/
+#define PORT_FC_CFG
+#define PORT_FC_CFG_ADDRESS 0x1000
+#define PORT_FC_CFG_NUM     15
+#define PORT_FC_CFG_INC     0x10
+#define PORT_FC_CFG_TYPE    REG_TYPE_RW
+#define PORT_FC_CFG_DEFAULT 0x0
+	/*[field] PORT_REACT_LIMIT*/
+	#define PORT_FC_CFG_PORT_REACT_LIMIT
+	#define PORT_FC_CFG_PORT_REACT_LIMIT_OFFSET  0
+	#define PORT_FC_CFG_PORT_REACT_LIMIT_LEN     9
+	#define PORT_FC_CFG_PORT_REACT_LIMIT_DEFAULT 0x0
+	/*[field] PORT_RESUME_FLOOR_TH*/
+	#define PORT_FC_CFG_PORT_RESUME_FLOOR_TH
+	#define PORT_FC_CFG_PORT_RESUME_FLOOR_TH_OFFSET  9
+	#define PORT_FC_CFG_PORT_RESUME_FLOOR_TH_LEN     9
+	#define PORT_FC_CFG_PORT_RESUME_FLOOR_TH_DEFAULT 0x0
+	/*[field] PORT_RESUME_OFFSET*/
+	#define PORT_FC_CFG_PORT_RESUME_OFFSET
+	#define PORT_FC_CFG_PORT_RESUME_OFFSET_OFFSET  18
+	#define PORT_FC_CFG_PORT_RESUME_OFFSET_LEN     11
+	#define PORT_FC_CFG_PORT_RESUME_OFFSET_DEFAULT 0x0
+	/*[field] PORT_SHARED_CEILING*/
+	#define PORT_FC_CFG_PORT_SHARED_CEILING
+	#define PORT_FC_CFG_PORT_SHARED_CEILING_OFFSET  29
+	#define PORT_FC_CFG_PORT_SHARED_CEILING_LEN     11
+	#define PORT_FC_CFG_PORT_SHARED_CEILING_DEFAULT 0x0
+	/*[field] PORT_SHARED_WEIGHT*/
+	#define PORT_FC_CFG_PORT_SHARED_WEIGHT
+	#define PORT_FC_CFG_PORT_SHARED_WEIGHT_OFFSET  40
+	#define PORT_FC_CFG_PORT_SHARED_WEIGHT_LEN     3
+	#define PORT_FC_CFG_PORT_SHARED_WEIGHT_DEFAULT 0x0
+	/*[field] PORT_SHARED_DYNAMIC*/
+	#define PORT_FC_CFG_PORT_SHARED_DYNAMIC
+	#define PORT_FC_CFG_PORT_SHARED_DYNAMIC_OFFSET  43
+	#define PORT_FC_CFG_PORT_SHARED_DYNAMIC_LEN     1
+	#define PORT_FC_CFG_PORT_SHARED_DYNAMIC_DEFAULT 0x0
+	/*[field] PORT_PRE_ALLOC*/
+	#define PORT_FC_CFG_PORT_PRE_ALLOC
+	#define PORT_FC_CFG_PORT_PRE_ALLOC_OFFSET  44
+	#define PORT_FC_CFG_PORT_PRE_ALLOC_LEN     11
+	#define PORT_FC_CFG_PORT_PRE_ALLOC_DEFAULT 0x0
+
+struct port_fc_cfg {
+	a_uint32_t  port_react_limit:9;
+	a_uint32_t  port_resume_floor_th:9;
+	a_uint32_t  port_resume_offset:11;
+	a_uint32_t  port_shared_ceiling_0:3;
+	a_uint32_t  port_shared_ceiling_1:8;
+	a_uint32_t  port_shared_weight:3;
+	a_uint32_t  port_shared_dynamic:1;
+	a_uint32_t  port_pre_alloc:11;
+	a_uint32_t  _reserved0:9;
+};
+
+union port_fc_cfg_u {
+	a_uint32_t val[2];
+	struct port_fc_cfg bf;
+};
+
+/*[table] LLM*/
+#define LLM
+#define LLM_ADDRESS 0x10000
+#define LLM_NUM     2048
+#define LLM_INC     0x10
+#define LLM_TYPE    REG_TYPE_RW
+#define LLM_DEFAULT 0x0
+	/*[field] NXT_PTR*/
+	#define LLM_NXT_PTR
+	#define LLM_NXT_PTR_OFFSET  0
+	#define LLM_NXT_PTR_LEN     11
+	#define LLM_NXT_PTR_DEFAULT 0x0
+	/*[field] EOP*/
+	#define LLM_EOP
+	#define LLM_EOP_OFFSET  11
+	#define LLM_EOP_LEN     1
+	#define LLM_EOP_DEFAULT 0x0
+
+struct llm {
+	a_uint32_t  nxt_ptr:11;
+	a_uint32_t  eop:1;
+	a_uint32_t  _reserved0:20;
+};
+
+union llm_u {
+	a_uint32_t val;
+	struct llm bf;
+};
+
+/*[table] RCM*/
+#define RCM
+#define RCM_ADDRESS 0x20000
+#define RCM_NUM     2048
+#define RCM_INC     0x10
+#define RCM_TYPE    REG_TYPE_RW
+#define RCM_DEFAULT 0x0
+	/*[field] REF_CNT*/
+	#define RCM_REF_CNT
+	#define RCM_REF_CNT_OFFSET  0
+	#define RCM_REF_CNT_LEN     4
+	#define RCM_REF_CNT_DEFAULT 0x0
+
+struct rcm {
+	a_uint32_t  ref_cnt:4;
+	a_uint32_t  _reserved0:28;
+};
+
+union rcm_u {
+	a_uint32_t val;
+	struct rcm bf;
+};
+
+/*[table] DM*/
+#define DM
+#define DM_ADDRESS 0x80000
+#define DM_NUM     8192
+#define DM_INC     0x40
+#define DM_TYPE    REG_TYPE_RW
+#define DM_DEFAULT 0x0
+	/*[field] PKT_DATA*/
+	#define DM_PKT_DATA
+	#define DM_PKT_DATA_OFFSET  0
+	#define DM_PKT_DATA_LEN     512
+	#define DM_PKT_DATA_DEFAULT 0x0
+
+struct dm {
+	a_uint32_t  pkt_data_0:32;
+	a_uint32_t  pkt_data_1:32;
+	a_uint32_t  pkt_data_2:32;
+	a_uint32_t  pkt_data_3:32;
+	a_uint32_t  pkt_data_4:32;
+	a_uint32_t  pkt_data_5:32;
+	a_uint32_t  pkt_data_6:32;
+	a_uint32_t  pkt_data_7:32;
+	a_uint32_t  pkt_data_8:32;
+	a_uint32_t  pkt_data_9:32;
+	a_uint32_t  pkt_data_10:32;
+	a_uint32_t  pkt_data_11:32;
+	a_uint32_t  pkt_data_12:32;
+	a_uint32_t  pkt_data_13:32;
+	a_uint32_t  pkt_data_14:32;
+	a_uint32_t  pkt_data_15:32;
+};
+
+union dm_u {
+	a_uint32_t val[16];
+	struct dm bf;
+};
+
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_ctrlpkt.h b/qca-ssdk/include/hsl/hppe/hppe_ctrlpkt.h
new file mode 100755
index 0000000..83503a3
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_ctrlpkt.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_CTRLPKT_H_
+#define _HPPE_CTRLPKT_H_
+
+#define ETHERTYPE_CTRL_MAX_ENTRY	4
+#define RFDB_TBL_MAX_ENTRY	32
+#define APP_CTRL_MAX_ENTRY	32
+
+
+sw_error_t
+hppe_ethertype_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ethertype_ctrl_u *value);
+
+sw_error_t
+hppe_ethertype_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ethertype_ctrl_u *value);
+
+sw_error_t
+hppe_app_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union app_ctrl_u *value);
+
+sw_error_t
+hppe_app_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union app_ctrl_u *value);
+
+sw_error_t
+hppe_ethertype_ctrl_ethertype_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ethertype_ctrl_ethertype_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ethertype_ctrl_ethertype_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ethertype_ctrl_ethertype_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_app_ctrl_portbitmap_include_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_app_ctrl_portbitmap_include_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_app_ctrl_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_app_ctrl_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_app_ctrl_portbitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_app_ctrl_portbitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_app_ctrl_rfdb_index_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_app_ctrl_rfdb_index_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_app_ctrl_protocol_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_app_ctrl_protocol_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_app_ctrl_in_stg_byp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_app_ctrl_in_stg_byp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_app_ctrl_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_app_ctrl_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_app_ctrl_l2_sec_byp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_app_ctrl_l2_sec_byp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_app_ctrl_protocol_include_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_app_ctrl_protocol_include_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_app_ctrl_ethertype_include_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_app_ctrl_ethertype_include_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_app_ctrl_sg_byp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_app_ctrl_sg_byp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_app_ctrl_rfdb_include_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_app_ctrl_rfdb_include_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_app_ctrl_ethertype_index_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_app_ctrl_ethertype_index_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_app_ctrl_in_vlan_fltr_byp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_app_ctrl_in_vlan_fltr_byp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_ctrlpkt_reg.h b/qca-ssdk/include/hsl/hppe/hppe_ctrlpkt_reg.h
new file mode 100755
index 0000000..943157f
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_ctrlpkt_reg.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef HPPE_CTRLPKT_REG_H
+#define HPPE_CTRLPKT_REG_H
+
+/**
+ * @defgroup
+ * @{
+ */
+/*[register] ETHERTYPE_CTRL*/
+#define ETHERTYPE_CTRL
+#define ETHERTYPE_CTRL_ADDRESS 0x80
+#define ETHERTYPE_CTRL_NUM     4
+#define ETHERTYPE_CTRL_INC     0x4
+#define ETHERTYPE_CTRL_TYPE    REG_TYPE_RW
+#define ETHERTYPE_CTRL_DEFAULT 0x0
+	/*[field] ETHERTYPE_EN*/
+	#define ETHERTYPE_CTRL_ETHERTYPE_EN
+	#define ETHERTYPE_CTRL_ETHERTYPE_EN_OFFSET  0
+	#define ETHERTYPE_CTRL_ETHERTYPE_EN_LEN     1
+	#define ETHERTYPE_CTRL_ETHERTYPE_EN_DEFAULT 0x0
+	/*[field] ETHERTYPE*/
+	#define ETHERTYPE_CTRL_ETHERTYPE
+	#define ETHERTYPE_CTRL_ETHERTYPE_OFFSET  16
+	#define ETHERTYPE_CTRL_ETHERTYPE_LEN     16
+	#define ETHERTYPE_CTRL_ETHERTYPE_DEFAULT 0x0
+
+struct ethertype_ctrl {
+	a_uint32_t  ethertype_en:1;
+	a_uint32_t  _reserved0:15;
+	a_uint32_t  ethertype:16;
+};
+
+union ethertype_ctrl_u {
+	a_uint32_t val;
+	struct ethertype_ctrl bf;
+};
+
+/*[table] APP_CTRL*/
+#define APP_CTRL
+#define APP_CTRL_ADDRESS 0x1400
+#define APP_CTRL_NUM     32
+#define APP_CTRL_INC     0x10
+#define APP_CTRL_TYPE    REG_TYPE_RW
+#define APP_CTRL_DEFAULT 0x0
+	/*[field] VALID*/
+	#define APP_CTRL_VALID
+	#define APP_CTRL_VALID_OFFSET  0
+	#define APP_CTRL_VALID_LEN     1
+	#define APP_CTRL_VALID_DEFAULT 0x0
+	/*[field] RFDB_INCLUDE*/
+	#define APP_CTRL_RFDB_INCLUDE
+	#define APP_CTRL_RFDB_INCLUDE_OFFSET  1
+	#define APP_CTRL_RFDB_INCLUDE_LEN     1
+	#define APP_CTRL_RFDB_INCLUDE_DEFAULT 0x0
+	/*[field] RFDB_INDEX_BITMAP*/
+	#define APP_CTRL_RFDB_INDEX_BITMAP
+	#define APP_CTRL_RFDB_INDEX_BITMAP_OFFSET  2
+	#define APP_CTRL_RFDB_INDEX_BITMAP_LEN     32
+	#define APP_CTRL_RFDB_INDEX_BITMAP_DEFAULT 0x0
+	/*[field] PROTOCOL_INCLUDE*/
+	#define APP_CTRL_PROTOCOL_INCLUDE
+	#define APP_CTRL_PROTOCOL_INCLUDE_OFFSET  34
+	#define APP_CTRL_PROTOCOL_INCLUDE_LEN     1
+	#define APP_CTRL_PROTOCOL_INCLUDE_DEFAULT 0x0
+	/*[field] PROTOCOL_BITMAP*/
+	#define APP_CTRL_PROTOCOL_BITMAP
+	#define APP_CTRL_PROTOCOL_BITMAP_OFFSET  35
+	#define APP_CTRL_PROTOCOL_BITMAP_LEN     26
+	#define APP_CTRL_PROTOCOL_BITMAP_DEFAULT 0x0
+	/*[field] ETHERTYPE_INCLUDE*/
+	#define APP_CTRL_ETHERTYPE_INCLUDE
+	#define APP_CTRL_ETHERTYPE_INCLUDE_OFFSET  61
+	#define APP_CTRL_ETHERTYPE_INCLUDE_LEN     1
+	#define APP_CTRL_ETHERTYPE_INCLUDE_DEFAULT 0x0
+	/*[field] ETHERTYPE_INDEX_BITMAP*/
+	#define APP_CTRL_ETHERTYPE_INDEX_BITMAP
+	#define APP_CTRL_ETHERTYPE_INDEX_BITMAP_OFFSET  62
+	#define APP_CTRL_ETHERTYPE_INDEX_BITMAP_LEN     4
+	#define APP_CTRL_ETHERTYPE_INDEX_BITMAP_DEFAULT 0x0
+	/*[field] PORTBITMAP_INCLUDE*/
+	#define APP_CTRL_PORTBITMAP_INCLUDE
+	#define APP_CTRL_PORTBITMAP_INCLUDE_OFFSET  66
+	#define APP_CTRL_PORTBITMAP_INCLUDE_LEN     1
+	#define APP_CTRL_PORTBITMAP_INCLUDE_DEFAULT 0x0
+	/*[field] PORTBITMAP*/
+	#define APP_CTRL_PORTBITMAP
+	#define APP_CTRL_PORTBITMAP_OFFSET  67
+	#define APP_CTRL_PORTBITMAP_LEN     8
+	#define APP_CTRL_PORTBITMAP_DEFAULT 0x0
+	/*[field] IN_VLAN_FLTR_BYP*/
+	#define APP_CTRL_IN_VLAN_FLTR_BYP
+	#define APP_CTRL_IN_VLAN_FLTR_BYP_OFFSET  75
+	#define APP_CTRL_IN_VLAN_FLTR_BYP_LEN     1
+	#define APP_CTRL_IN_VLAN_FLTR_BYP_DEFAULT 0x0
+	/*[field] IN_STG_BYP*/
+	#define APP_CTRL_IN_STG_BYP
+	#define APP_CTRL_IN_STG_BYP_OFFSET  76
+	#define APP_CTRL_IN_STG_BYP_LEN     1
+	#define APP_CTRL_IN_STG_BYP_DEFAULT 0x0
+	/*[field] L2_SEC_BYP*/
+	#define APP_CTRL_L2_SEC_BYP
+	#define APP_CTRL_L2_SEC_BYP_OFFSET  77
+	#define APP_CTRL_L2_SEC_BYP_LEN     1
+	#define APP_CTRL_L2_SEC_BYP_DEFAULT 0x0
+	/*[field] SG_BYP*/
+	#define APP_CTRL_SG_BYP
+	#define APP_CTRL_SG_BYP_OFFSET  78
+	#define APP_CTRL_SG_BYP_LEN     1
+	#define APP_CTRL_SG_BYP_DEFAULT 0x0
+	/*[field] CMD*/
+	#define APP_CTRL_CMD
+	#define APP_CTRL_CMD_OFFSET  79
+	#define APP_CTRL_CMD_LEN     2
+	#define APP_CTRL_CMD_DEFAULT 0x0
+
+struct app_ctrl {
+	a_uint32_t  valid:1;
+	a_uint32_t  rfdb_include:1;
+	a_uint32_t  rfdb_index_bitmap_0:30;
+	a_uint32_t  rfdb_index_bitmap_1:2;
+	a_uint32_t  protocol_include:1;
+	a_uint32_t  protocol_bitmap:26;
+	a_uint32_t  ethertype_include:1;
+	a_uint32_t  ethertype_index_bitmap_0:2;
+	a_uint32_t  ethertype_index_bitmap_1:2;
+	a_uint32_t  portbitmap_include:1;
+	a_uint32_t  portbitmap:8;
+	a_uint32_t  in_vlan_fltr_byp:1;
+	a_uint32_t  in_stg_byp:1;
+	a_uint32_t  l2_sec_byp:1;
+	a_uint32_t  sg_byp:1;
+	a_uint32_t  cmd:2;
+	a_uint32_t  _reserved0:15;
+};
+
+union app_ctrl_u {
+	a_uint32_t val[3];
+	struct app_ctrl bf;
+};
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_fdb.h b/qca-ssdk/include/hsl/hppe/hppe_fdb.h
new file mode 100755
index 0000000..d99bfd6
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_fdb.h
@@ -0,0 +1,900 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_FDB_H_
+#define _HPPE_FDB_H_
+
+#define PRE_L2_CNT_TBL_MAX_ENTRY	32
+#define PORT_BRIDGE_CTRL_MAX_ENTRY	8
+#define PORT_LRN_LIMIT_CTRL_MAX_ENTRY	8
+#define PORT_LRN_LIMIT_COUNTER_MAX_ENTRY	8
+#define RFDB_TBL_MAX_ENTRY	32
+#define FDB_TBL_MAX_ENTRY	2048
+
+
+sw_error_t
+hppe_l2_dbg_addr_get(
+		a_uint32_t dev_id,
+		union l2_dbg_addr_u *value);
+
+sw_error_t
+hppe_l2_dbg_addr_set(
+		a_uint32_t dev_id,
+		union l2_dbg_addr_u *value);
+
+sw_error_t
+hppe_l2_dbg_data_get(
+		a_uint32_t dev_id,
+		union l2_dbg_data_u *value);
+
+sw_error_t
+hppe_l2_dbg_data_set(
+		a_uint32_t dev_id,
+		union l2_dbg_data_u *value);
+
+sw_error_t
+hppe_fdb_tbl_op_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_u *value);
+
+sw_error_t
+hppe_fdb_tbl_op_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_u *value);
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_rslt_u *value);
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_rslt_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_u *value);
+
+sw_error_t
+hppe_age_timer_get(
+		a_uint32_t dev_id,
+		union age_timer_u *value);
+
+sw_error_t
+hppe_age_timer_set(
+		a_uint32_t dev_id,
+		union age_timer_u *value);
+
+sw_error_t
+hppe_l2_global_conf_get(
+		a_uint32_t dev_id,
+		union l2_global_conf_u *value);
+
+sw_error_t
+hppe_l2_global_conf_set(
+		a_uint32_t dev_id,
+		union l2_global_conf_u *value);
+
+sw_error_t
+hppe_l2_dbgcnt_cmd_get(
+		a_uint32_t dev_id,
+		union l2_dbgcnt_cmd_u *value);
+
+sw_error_t
+hppe_l2_dbgcnt_cmd_set(
+		a_uint32_t dev_id,
+		union l2_dbgcnt_cmd_u *value);
+
+sw_error_t
+hppe_l2_dbgcnt_rdata_get(
+		a_uint32_t dev_id,
+		union l2_dbgcnt_rdata_u *value);
+
+sw_error_t
+hppe_l2_dbgcnt_rdata_set(
+		a_uint32_t dev_id,
+		union l2_dbgcnt_rdata_u *value);
+
+sw_error_t
+hppe_l2_dbgcnt_wdata_get(
+		a_uint32_t dev_id,
+		union l2_dbgcnt_wdata_u *value);
+
+sw_error_t
+hppe_l2_dbgcnt_wdata_set(
+		a_uint32_t dev_id,
+		union l2_dbgcnt_wdata_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data0_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_data0_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data0_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_data0_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data1_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_data1_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data1_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_data1_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data2_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_data2_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data2_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_data2_u *value);
+
+sw_error_t
+hppe_fdb_tbl_op_data0_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_data0_u *value);
+
+sw_error_t
+hppe_fdb_tbl_op_data0_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_data0_u *value);
+
+sw_error_t
+hppe_fdb_tbl_op_data1_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_data1_u *value);
+
+sw_error_t
+hppe_fdb_tbl_op_data1_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_data1_u *value);
+
+sw_error_t
+hppe_fdb_tbl_op_data2_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_data2_u *value);
+
+sw_error_t
+hppe_fdb_tbl_op_data2_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_data2_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data0_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_data0_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data0_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_data0_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data1_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_data1_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data1_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_data1_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data2_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_data2_u *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data2_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_data2_u *value);
+
+sw_error_t
+hppe_port_bridge_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_bridge_ctrl_u *value);
+
+sw_error_t
+hppe_port_bridge_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_bridge_ctrl_u *value);
+
+sw_error_t
+hppe_port_lrn_limit_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_lrn_limit_ctrl_u *value);
+
+sw_error_t
+hppe_port_lrn_limit_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_lrn_limit_ctrl_u *value);
+
+sw_error_t
+hppe_port_lrn_limit_counter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_lrn_limit_counter_u *value);
+
+sw_error_t
+hppe_port_lrn_limit_counter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_lrn_limit_counter_u *value);
+
+sw_error_t
+hppe_rfdb_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rfdb_tbl_u *value);
+
+sw_error_t
+hppe_rfdb_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rfdb_tbl_u *value);
+
+sw_error_t
+hppe_fdb_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union fdb_tbl_u *value);
+
+sw_error_t
+hppe_fdb_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union fdb_tbl_u *value);
+
+sw_error_t
+hppe_l2_dbg_addr_l2_dbg_addr_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l2_dbg_addr_l2_dbg_addr_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l2_dbg_data_l2_dbg_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l2_dbg_data_l2_dbg_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_op_op_mode_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_op_op_mode_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_op_op_type_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_op_op_type_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_op_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_op_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_op_cmd_id_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_op_cmd_id_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_op_byp_rslt_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_op_byp_rslt_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_op_mode_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_op_mode_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_op_type_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_op_type_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_cmd_id_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_cmd_id_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_byp_rslt_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_byp_rslt_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_op_rslt_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_op_rslt_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_valid_cnt_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_valid_cnt_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_cmd_id_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_cmd_id_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_op_rslt_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_op_rslt_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_valid_cnt_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_valid_cnt_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_cmd_id_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_cmd_id_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_age_timer_age_val_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_age_timer_age_val_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l2_global_conf_fdb_hash_full_fwd_cmd_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l2_global_conf_fdb_hash_full_fwd_cmd_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l2_global_conf_failover_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l2_global_conf_failover_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l2_global_conf_lrn_ctrl_mode_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l2_global_conf_lrn_ctrl_mode_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l2_global_conf_age_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l2_global_conf_age_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l2_global_conf_fdb_hash_mode_1_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l2_global_conf_fdb_hash_mode_1_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l2_global_conf_lrn_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l2_global_conf_lrn_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l2_global_conf_fdb_hash_mode_0_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l2_global_conf_fdb_hash_mode_0_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l2_global_conf_age_ctrl_mode_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l2_global_conf_age_ctrl_mode_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_l2_global_conf_service_code_loop_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l2_global_conf_service_code_loop_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+#endif
+
+sw_error_t
+hppe_l2_dbgcnt_cmd_type_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l2_dbgcnt_cmd_type_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l2_dbgcnt_cmd_addr_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l2_dbgcnt_cmd_addr_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l2_dbgcnt_rdata_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l2_dbgcnt_rdata_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l2_dbgcnt_wdata_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l2_dbgcnt_wdata_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data0_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data0_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data1_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data1_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data2_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data2_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_op_data0_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_op_data0_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_op_data1_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_op_data1_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_op_data2_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_op_data2_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data0_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data0_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data1_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data1_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data2_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data2_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_bridge_ctrl_txmac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_bridge_ctrl_txmac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_bridge_ctrl_port_isolation_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_bridge_ctrl_port_isolation_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_bridge_ctrl_station_move_lrn_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_bridge_ctrl_station_move_lrn_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_bridge_ctrl_new_addr_fwd_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_bridge_ctrl_new_addr_fwd_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_bridge_ctrl_promisc_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_bridge_ctrl_promisc_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_bridge_ctrl_new_addr_lrn_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_bridge_ctrl_new_addr_lrn_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_bridge_ctrl_station_move_fwd_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_bridge_ctrl_station_move_fwd_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_lrn_limit_ctrl_lrn_lmt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_lrn_limit_ctrl_lrn_lmt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_lrn_limit_ctrl_lrn_lmt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_lrn_limit_ctrl_lrn_lmt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_lrn_limit_ctrl_lrn_lmt_exceed_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_lrn_limit_ctrl_lrn_lmt_exceed_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_lrn_limit_counter_lrn_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_lrn_limit_counter_lrn_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rfdb_tbl_mac_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_rfdb_tbl_mac_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_rfdb_tbl_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rfdb_tbl_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_fdb_reg.h b/qca-ssdk/include/hsl/hppe/hppe_fdb_reg.h
new file mode 100755
index 0000000..1bbc37f
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_fdb_reg.h
@@ -0,0 +1,838 @@
+/*
+ * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_FDB_REG_H
+#define HPPE_FDB_REG_H
+
+/*[register] L2_DBG_ADDR*/
+#define L2_DBG_ADDR
+#define L2_DBG_ADDR_ADDRESS 0x0
+#define L2_DBG_ADDR_NUM     1
+#define L2_DBG_ADDR_INC     0x4
+#define L2_DBG_ADDR_TYPE    REG_TYPE_RW
+#define L2_DBG_ADDR_DEFAULT 0x0
+	/*[field] L2_DBG_ADDR*/
+	#define L2_DBG_ADDR_L2_DBG_ADDR
+	#define L2_DBG_ADDR_L2_DBG_ADDR_OFFSET  0
+	#define L2_DBG_ADDR_L2_DBG_ADDR_LEN     32
+	#define L2_DBG_ADDR_L2_DBG_ADDR_DEFAULT 0x0
+
+struct l2_dbg_addr {
+	a_uint32_t  l2_dbg_addr:32;
+};
+
+union l2_dbg_addr_u {
+	a_uint32_t val;
+	struct l2_dbg_addr bf;
+};
+
+/*[register] L2_DBG_DATA*/
+#define L2_DBG_DATA
+#define L2_DBG_DATA_ADDRESS 0x4
+#define L2_DBG_DATA_NUM     1
+#define L2_DBG_DATA_INC     0x4
+#define L2_DBG_DATA_TYPE    REG_TYPE_RO
+#define L2_DBG_DATA_DEFAULT 0x0
+	/*[field] L2_DBG_DATA*/
+	#define L2_DBG_DATA_L2_DBG_DATA
+	#define L2_DBG_DATA_L2_DBG_DATA_OFFSET  0
+	#define L2_DBG_DATA_L2_DBG_DATA_LEN     32
+	#define L2_DBG_DATA_L2_DBG_DATA_DEFAULT 0x0
+
+struct l2_dbg_data {
+	a_uint32_t  l2_dbg_data:32;
+};
+
+union l2_dbg_data_u {
+	a_uint32_t val;
+	struct l2_dbg_data bf;
+};
+
+/*[register] FDB_TBL_OP*/
+#define FDB_TBL_OP
+#define FDB_TBL_OP_ADDRESS 0x8
+#define FDB_TBL_OP_NUM     1
+#define FDB_TBL_OP_INC     0x4
+#define FDB_TBL_OP_TYPE    REG_TYPE_RW
+#define FDB_TBL_OP_DEFAULT 0x0
+	/*[field] CMD_ID*/
+	#define FDB_TBL_OP_CMD_ID
+	#define FDB_TBL_OP_CMD_ID_OFFSET  0
+	#define FDB_TBL_OP_CMD_ID_LEN     4
+	#define FDB_TBL_OP_CMD_ID_DEFAULT 0x0
+	/*[field] BYP_RSLT_EN*/
+	#define FDB_TBL_OP_BYP_RSLT_EN
+	#define FDB_TBL_OP_BYP_RSLT_EN_OFFSET  4
+	#define FDB_TBL_OP_BYP_RSLT_EN_LEN     1
+	#define FDB_TBL_OP_BYP_RSLT_EN_DEFAULT 0x0
+	/*[field] OP_TYPE*/
+	#define FDB_TBL_OP_OP_TYPE
+	#define FDB_TBL_OP_OP_TYPE_OFFSET  5
+	#define FDB_TBL_OP_OP_TYPE_LEN     3
+	#define FDB_TBL_OP_OP_TYPE_DEFAULT 0x0
+	/*[field] HASH_BLOCK_BITMAP*/
+	#define FDB_TBL_OP_HASH_BLOCK_BITMAP
+	#define FDB_TBL_OP_HASH_BLOCK_BITMAP_OFFSET  8
+	#define FDB_TBL_OP_HASH_BLOCK_BITMAP_LEN     2
+	#define FDB_TBL_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0
+	/*[field] OP_MODE*/
+	#define FDB_TBL_OP_OP_MODE
+	#define FDB_TBL_OP_OP_MODE_OFFSET  10
+	#define FDB_TBL_OP_OP_MODE_LEN     1
+	#define FDB_TBL_OP_OP_MODE_DEFAULT 0x0
+	/*[field] ENTRY_INDEX*/
+	#define FDB_TBL_OP_ENTRY_INDEX
+	#define FDB_TBL_OP_ENTRY_INDEX_OFFSET  11
+	#define FDB_TBL_OP_ENTRY_INDEX_LEN     11
+	#define FDB_TBL_OP_ENTRY_INDEX_DEFAULT 0x0
+
+struct fdb_tbl_op {
+	a_uint32_t  cmd_id:4;
+	a_uint32_t  byp_rslt_en:1;
+	a_uint32_t  op_type:3;
+	a_uint32_t  hash_block_bitmap:2;
+	a_uint32_t  op_mode:1;
+	a_uint32_t  entry_index:11;
+	a_uint32_t  _reserved0:10;
+};
+
+union fdb_tbl_op_u {
+	a_uint32_t val;
+	struct fdb_tbl_op bf;
+};
+
+/*[register] FDB_TBL_RD_OP*/
+#define FDB_TBL_RD_OP
+#define FDB_TBL_RD_OP_ADDRESS 0x10
+#define FDB_TBL_RD_OP_NUM     1
+#define FDB_TBL_RD_OP_INC     0x4
+#define FDB_TBL_RD_OP_TYPE    REG_TYPE_RW
+#define FDB_TBL_RD_OP_DEFAULT 0x0
+	/*[field] CMD_ID*/
+	#define FDB_TBL_RD_OP_CMD_ID
+	#define FDB_TBL_RD_OP_CMD_ID_OFFSET  0
+	#define FDB_TBL_RD_OP_CMD_ID_LEN     4
+	#define FDB_TBL_RD_OP_CMD_ID_DEFAULT 0x0
+	/*[field] BYP_RSLT_EN*/
+	#define FDB_TBL_RD_OP_BYP_RSLT_EN
+	#define FDB_TBL_RD_OP_BYP_RSLT_EN_OFFSET  4
+	#define FDB_TBL_RD_OP_BYP_RSLT_EN_LEN     1
+	#define FDB_TBL_RD_OP_BYP_RSLT_EN_DEFAULT 0x0
+	/*[field] OP_TYPE*/
+	#define FDB_TBL_RD_OP_OP_TYPE
+	#define FDB_TBL_RD_OP_OP_TYPE_OFFSET  5
+	#define FDB_TBL_RD_OP_OP_TYPE_LEN     3
+	#define FDB_TBL_RD_OP_OP_TYPE_DEFAULT 0x0
+	/*[field] HASH_BLOCK_BITMAP*/
+	#define FDB_TBL_RD_OP_HASH_BLOCK_BITMAP
+	#define FDB_TBL_RD_OP_HASH_BLOCK_BITMAP_OFFSET  8
+	#define FDB_TBL_RD_OP_HASH_BLOCK_BITMAP_LEN     2
+	#define FDB_TBL_RD_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0
+	/*[field] OP_MODE*/
+	#define FDB_TBL_RD_OP_OP_MODE
+	#define FDB_TBL_RD_OP_OP_MODE_OFFSET  10
+	#define FDB_TBL_RD_OP_OP_MODE_LEN     1
+	#define FDB_TBL_RD_OP_OP_MODE_DEFAULT 0x0
+	/*[field] ENTRY_INDEX*/
+	#define FDB_TBL_RD_OP_ENTRY_INDEX
+	#define FDB_TBL_RD_OP_ENTRY_INDEX_OFFSET  11
+	#define FDB_TBL_RD_OP_ENTRY_INDEX_LEN     11
+	#define FDB_TBL_RD_OP_ENTRY_INDEX_DEFAULT 0x0
+
+struct fdb_tbl_rd_op {
+	a_uint32_t  cmd_id:4;
+	a_uint32_t  byp_rslt_en:1;
+	a_uint32_t  op_type:3;
+	a_uint32_t  hash_block_bitmap:2;
+	a_uint32_t  op_mode:1;
+	a_uint32_t  entry_index:11;
+	a_uint32_t  _reserved0:10;
+};
+
+union fdb_tbl_rd_op_u {
+	a_uint32_t val;
+	struct fdb_tbl_rd_op bf;
+};
+
+/*[register] FDB_TBL_OP_RSLT*/
+#define FDB_TBL_OP_RSLT
+#define FDB_TBL_OP_RSLT_ADDRESS 0x20
+#define FDB_TBL_OP_RSLT_NUM     1
+#define FDB_TBL_OP_RSLT_INC     0x4
+#define FDB_TBL_OP_RSLT_TYPE    REG_TYPE_RO
+#define FDB_TBL_OP_RSLT_DEFAULT 0x0
+	/*[field] CMD_ID*/
+	#define FDB_TBL_OP_RSLT_CMD_ID
+	#define FDB_TBL_OP_RSLT_CMD_ID_OFFSET  0
+	#define FDB_TBL_OP_RSLT_CMD_ID_LEN     4
+	#define FDB_TBL_OP_RSLT_CMD_ID_DEFAULT 0x0
+	/*[field] OP_RSLT*/
+	#define FDB_TBL_OP_RSLT_OP_RSLT
+	#define FDB_TBL_OP_RSLT_OP_RSLT_OFFSET  4
+	#define FDB_TBL_OP_RSLT_OP_RSLT_LEN     1
+	#define FDB_TBL_OP_RSLT_OP_RSLT_DEFAULT 0x0
+	/*[field] VALID_CNT*/
+	#define FDB_TBL_OP_RSLT_VALID_CNT
+	#define FDB_TBL_OP_RSLT_VALID_CNT_OFFSET  5
+	#define FDB_TBL_OP_RSLT_VALID_CNT_LEN     4
+	#define FDB_TBL_OP_RSLT_VALID_CNT_DEFAULT 0x0
+	/*[field] ENTRY_INDEX*/
+	#define FDB_TBL_OP_RSLT_ENTRY_INDEX
+	#define FDB_TBL_OP_RSLT_ENTRY_INDEX_OFFSET  9
+	#define FDB_TBL_OP_RSLT_ENTRY_INDEX_LEN     11
+	#define FDB_TBL_OP_RSLT_ENTRY_INDEX_DEFAULT 0x0
+
+struct fdb_tbl_op_rslt {
+	a_uint32_t  cmd_id:4;
+	a_uint32_t  op_rslt:1;
+	a_uint32_t  valid_cnt:4;
+	a_uint32_t  entry_index:11;
+	a_uint32_t  _reserved0:12;
+};
+
+union fdb_tbl_op_rslt_u {
+	a_uint32_t val;
+	struct fdb_tbl_op_rslt bf;
+};
+
+/*[register] FDB_TBL_RD_OP_RSLT*/
+#define FDB_TBL_RD_OP_RSLT
+#define FDB_TBL_RD_OP_RSLT_ADDRESS 0x30
+#define FDB_TBL_RD_OP_RSLT_NUM     1
+#define FDB_TBL_RD_OP_RSLT_INC     0x4
+#define FDB_TBL_RD_OP_RSLT_TYPE    REG_TYPE_RO
+#define FDB_TBL_RD_OP_RSLT_DEFAULT 0x0
+	/*[field] CMD_ID*/
+	#define FDB_TBL_RD_OP_RSLT_CMD_ID
+	#define FDB_TBL_RD_OP_RSLT_CMD_ID_OFFSET  0
+	#define FDB_TBL_RD_OP_RSLT_CMD_ID_LEN     4
+	#define FDB_TBL_RD_OP_RSLT_CMD_ID_DEFAULT 0x0
+	/*[field] OP_RSLT*/
+	#define FDB_TBL_RD_OP_RSLT_OP_RSLT
+	#define FDB_TBL_RD_OP_RSLT_OP_RSLT_OFFSET  4
+	#define FDB_TBL_RD_OP_RSLT_OP_RSLT_LEN     1
+	#define FDB_TBL_RD_OP_RSLT_OP_RSLT_DEFAULT 0x0
+	/*[field] VALID_CNT*/
+	#define FDB_TBL_RD_OP_RSLT_VALID_CNT
+	#define FDB_TBL_RD_OP_RSLT_VALID_CNT_OFFSET  5
+	#define FDB_TBL_RD_OP_RSLT_VALID_CNT_LEN     4
+	#define FDB_TBL_RD_OP_RSLT_VALID_CNT_DEFAULT 0x0
+	/*[field] ENTRY_INDEX*/
+	#define FDB_TBL_RD_OP_RSLT_ENTRY_INDEX
+	#define FDB_TBL_RD_OP_RSLT_ENTRY_INDEX_OFFSET  9
+	#define FDB_TBL_RD_OP_RSLT_ENTRY_INDEX_LEN     11
+	#define FDB_TBL_RD_OP_RSLT_ENTRY_INDEX_DEFAULT 0x0
+
+struct fdb_tbl_rd_op_rslt {
+	a_uint32_t  cmd_id:4;
+	a_uint32_t  op_rslt:1;
+	a_uint32_t  valid_cnt:4;
+	a_uint32_t  entry_index:11;
+	a_uint32_t  _reserved0:12;
+};
+
+union fdb_tbl_rd_op_rslt_u {
+	a_uint32_t val;
+	struct fdb_tbl_rd_op_rslt bf;
+};
+
+/*[register] AGE_TIMER*/
+#define AGE_TIMER
+#define AGE_TIMER_ADDRESS 0x34
+#define AGE_TIMER_NUM     1
+#define AGE_TIMER_INC     0x4
+#define AGE_TIMER_TYPE    REG_TYPE_RW
+#define AGE_TIMER_DEFAULT 0x0
+	/*[field] AGE_VAL*/
+	#define AGE_TIMER_AGE_VAL
+	#define AGE_TIMER_AGE_VAL_OFFSET  0
+	#define AGE_TIMER_AGE_VAL_LEN     20
+	#define AGE_TIMER_AGE_VAL_DEFAULT 0x0
+
+struct age_timer {
+	a_uint32_t  age_val:20;
+	a_uint32_t  _reserved0:12;
+};
+
+union age_timer_u {
+	a_uint32_t val;
+	struct age_timer bf;
+};
+
+/*[register] L2_GLOBAL_CONF*/
+#define L2_GLOBAL_CONF
+#define L2_GLOBAL_CONF_ADDRESS 0x38
+#define L2_GLOBAL_CONF_NUM     1
+#define L2_GLOBAL_CONF_INC     0x4
+#define L2_GLOBAL_CONF_TYPE    REG_TYPE_RW
+#define L2_GLOBAL_CONF_DEFAULT 0xc0
+	/*[field] FDB_HASH_MODE_0*/
+	#define L2_GLOBAL_CONF_FDB_HASH_MODE_0
+	#define L2_GLOBAL_CONF_FDB_HASH_MODE_0_OFFSET  0
+	#define L2_GLOBAL_CONF_FDB_HASH_MODE_0_LEN     2
+	#define L2_GLOBAL_CONF_FDB_HASH_MODE_0_DEFAULT 0x0
+	/*[field] FDB_HASH_MODE_1*/
+	#define L2_GLOBAL_CONF_FDB_HASH_MODE_1
+	#define L2_GLOBAL_CONF_FDB_HASH_MODE_1_OFFSET  2
+	#define L2_GLOBAL_CONF_FDB_HASH_MODE_1_LEN     2
+	#define L2_GLOBAL_CONF_FDB_HASH_MODE_1_DEFAULT 0x0
+	/*[field] FDB_HASH_FULL_FWD_CMD*/
+	#define L2_GLOBAL_CONF_FDB_HASH_FULL_FWD_CMD
+	#define L2_GLOBAL_CONF_FDB_HASH_FULL_FWD_CMD_OFFSET  4
+	#define L2_GLOBAL_CONF_FDB_HASH_FULL_FWD_CMD_LEN     2
+	#define L2_GLOBAL_CONF_FDB_HASH_FULL_FWD_CMD_DEFAULT 0x0
+	/*[field] LRN_EN*/
+	#define L2_GLOBAL_CONF_LRN_EN
+	#define L2_GLOBAL_CONF_LRN_EN_OFFSET  6
+	#define L2_GLOBAL_CONF_LRN_EN_LEN     1
+	#define L2_GLOBAL_CONF_LRN_EN_DEFAULT 0x1
+	/*[field] AGE_EN*/
+	#define L2_GLOBAL_CONF_AGE_EN
+	#define L2_GLOBAL_CONF_AGE_EN_OFFSET  7
+	#define L2_GLOBAL_CONF_AGE_EN_LEN     1
+	#define L2_GLOBAL_CONF_AGE_EN_DEFAULT 0x1
+	/*[field] LRN_CTRL_MODE*/
+	#define L2_GLOBAL_CONF_LRN_CTRL_MODE
+	#define L2_GLOBAL_CONF_LRN_CTRL_MODE_OFFSET  8
+	#define L2_GLOBAL_CONF_LRN_CTRL_MODE_LEN     1
+	#define L2_GLOBAL_CONF_LRN_CTRL_MODE_DEFAULT 0x0
+	/*[field] AGE_CTRL_MODE*/
+	#define L2_GLOBAL_CONF_AGE_CTRL_MODE
+	#define L2_GLOBAL_CONF_AGE_CTRL_MODE_OFFSET  9
+	#define L2_GLOBAL_CONF_AGE_CTRL_MODE_LEN     1
+	#define L2_GLOBAL_CONF_AGE_CTRL_MODE_DEFAULT 0x0
+	/*[field] FAILOVER_EN*/
+	#define L2_GLOBAL_CONF_FAILOVER_EN
+	#define L2_GLOBAL_CONF_FAILOVER_EN_OFFSET  10
+	#define L2_GLOBAL_CONF_FAILOVER_EN_LEN     1
+	#define L2_GLOBAL_CONF_FAILOVER_EN_DEFAULT 0x0
+	/*[field] SERVICE_CODE_LOOP*/
+	#define L2_GLOBAL_CONF_SERVICE_CODE_LOOP
+	#define L2_GLOBAL_CONF_SERVICE_CODE_LOOP_OFFSET  11
+	#define L2_GLOBAL_CONF_SERVICE_CODE_LOOP_LEN     1
+	#define L2_GLOBAL_CONF_SERVICE_CODE_LOOP_DEFAULT 0x0
+
+struct l2_global_conf {
+	a_uint32_t  fdb_hash_mode_0:2;
+	a_uint32_t  fdb_hash_mode_1:2;
+	a_uint32_t  fdb_hash_full_fwd_cmd:2;
+	a_uint32_t  lrn_en:1;
+	a_uint32_t  age_en:1;
+	a_uint32_t  lrn_ctrl_mode:1;
+	a_uint32_t  age_ctrl_mode:1;
+	a_uint32_t  failover_en:1;
+	a_uint32_t  service_code_loop:1;
+	a_uint32_t  l2_flow_copy_escape:1;
+	a_uint32_t  _reserved0:19;
+};
+
+union l2_global_conf_u {
+	a_uint32_t val;
+	struct l2_global_conf bf;
+};
+
+/*[register] L2_DBGCNT_CMD*/
+#define L2_DBGCNT_CMD
+#define L2_DBGCNT_CMD_ADDRESS 0x44
+#define L2_DBGCNT_CMD_NUM     1
+#define L2_DBGCNT_CMD_INC     0x4
+#define L2_DBGCNT_CMD_TYPE    REG_TYPE_RW
+#define L2_DBGCNT_CMD_DEFAULT 0x0
+	/*[field] ADDR*/
+	#define L2_DBGCNT_CMD_ADDR
+	#define L2_DBGCNT_CMD_ADDR_OFFSET  0
+	#define L2_DBGCNT_CMD_ADDR_LEN     8
+	#define L2_DBGCNT_CMD_ADDR_DEFAULT 0x0
+	/*[field] TYPE*/
+	#define L2_DBGCNT_CMD_TYPE_F
+	#define L2_DBGCNT_CMD_TYPE_F_OFFSET  8
+	#define L2_DBGCNT_CMD_TYPE_F_LEN     2
+	#define L2_DBGCNT_CMD_TYPE_F_DEFAULT 0x0
+
+struct l2_dbgcnt_cmd {
+	a_uint32_t  addr:8;
+	a_uint32_t  type:2;
+	a_uint32_t  _reserved0:22;
+};
+
+union l2_dbgcnt_cmd_u {
+	a_uint32_t val;
+	struct l2_dbgcnt_cmd bf;
+};
+
+/*[register] L2_DBGCNT_RDATA*/
+#define L2_DBGCNT_RDATA
+#define L2_DBGCNT_RDATA_ADDRESS 0x48
+#define L2_DBGCNT_RDATA_NUM     1
+#define L2_DBGCNT_RDATA_INC     0x4
+#define L2_DBGCNT_RDATA_TYPE    REG_TYPE_RO
+#define L2_DBGCNT_RDATA_DEFAULT 0x0
+	/*[field] DATA*/
+	#define L2_DBGCNT_RDATA_DATA
+	#define L2_DBGCNT_RDATA_DATA_OFFSET  0
+	#define L2_DBGCNT_RDATA_DATA_LEN     32
+	#define L2_DBGCNT_RDATA_DATA_DEFAULT 0x0
+
+struct l2_dbgcnt_rdata {
+	a_uint32_t  data:32;
+};
+
+union l2_dbgcnt_rdata_u {
+	a_uint32_t val;
+	struct l2_dbgcnt_rdata bf;
+};
+
+/*[register] L2_DBGCNT_WDATA*/
+#define L2_DBGCNT_WDATA
+#define L2_DBGCNT_WDATA_ADDRESS 0x4c
+#define L2_DBGCNT_WDATA_NUM     1
+#define L2_DBGCNT_WDATA_INC     0x4
+#define L2_DBGCNT_WDATA_TYPE    REG_TYPE_RW
+#define L2_DBGCNT_WDATA_DEFAULT 0x0
+	/*[field] DATA*/
+	#define L2_DBGCNT_WDATA_DATA
+	#define L2_DBGCNT_WDATA_DATA_OFFSET  0
+	#define L2_DBGCNT_WDATA_DATA_LEN     32
+	#define L2_DBGCNT_WDATA_DATA_DEFAULT 0x0
+
+struct l2_dbgcnt_wdata {
+	a_uint32_t  data:32;
+};
+
+union l2_dbgcnt_wdata_u {
+	a_uint32_t val;
+	struct l2_dbgcnt_wdata bf;
+};
+
+/*[register] FDB_TBL_RD_OP_RSLT_DATA0*/
+#define FDB_TBL_RD_OP_RSLT_DATA0
+#define FDB_TBL_RD_OP_RSLT_DATA0_ADDRESS 0x200
+#define FDB_TBL_RD_OP_RSLT_DATA0_NUM     1
+#define FDB_TBL_RD_OP_RSLT_DATA0_INC     0x10
+#define FDB_TBL_RD_OP_RSLT_DATA0_TYPE    REG_TYPE_RO
+#define FDB_TBL_RD_OP_RSLT_DATA0_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FDB_TBL_RD_OP_RSLT_DATA0_DATA
+	#define FDB_TBL_RD_OP_RSLT_DATA0_DATA_OFFSET  0
+	#define FDB_TBL_RD_OP_RSLT_DATA0_DATA_LEN     32
+	#define FDB_TBL_RD_OP_RSLT_DATA0_DATA_DEFAULT 0x0
+
+struct fdb_tbl_rd_op_rslt_data0 {
+	a_uint32_t  data:32;
+};
+
+union fdb_tbl_rd_op_rslt_data0_u {
+	a_uint32_t val;
+	struct fdb_tbl_rd_op_rslt_data0 bf;
+};
+
+/*[register] FDB_TBL_RD_OP_RSLT_DATA1*/
+#define FDB_TBL_RD_OP_RSLT_DATA1
+#define FDB_TBL_RD_OP_RSLT_DATA1_ADDRESS 0x204
+#define FDB_TBL_RD_OP_RSLT_DATA1_NUM     1
+#define FDB_TBL_RD_OP_RSLT_DATA1_INC     0x10
+#define FDB_TBL_RD_OP_RSLT_DATA1_TYPE    REG_TYPE_RO
+#define FDB_TBL_RD_OP_RSLT_DATA1_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FDB_TBL_RD_OP_RSLT_DATA1_DATA
+	#define FDB_TBL_RD_OP_RSLT_DATA1_DATA_OFFSET  0
+	#define FDB_TBL_RD_OP_RSLT_DATA1_DATA_LEN     32
+	#define FDB_TBL_RD_OP_RSLT_DATA1_DATA_DEFAULT 0x0
+
+struct fdb_tbl_rd_op_rslt_data1 {
+	a_uint32_t  data:32;
+};
+
+union fdb_tbl_rd_op_rslt_data1_u {
+	a_uint32_t val;
+	struct fdb_tbl_rd_op_rslt_data1 bf;
+};
+
+/*[register] FDB_TBL_RD_OP_RSLT_DATA2*/
+#define FDB_TBL_RD_OP_RSLT_DATA2
+#define FDB_TBL_RD_OP_RSLT_DATA2_ADDRESS 0x208
+#define FDB_TBL_RD_OP_RSLT_DATA2_NUM     1
+#define FDB_TBL_RD_OP_RSLT_DATA2_INC     0x10
+#define FDB_TBL_RD_OP_RSLT_DATA2_TYPE    REG_TYPE_RO
+#define FDB_TBL_RD_OP_RSLT_DATA2_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FDB_TBL_RD_OP_RSLT_DATA2_DATA
+	#define FDB_TBL_RD_OP_RSLT_DATA2_DATA_OFFSET  0
+	#define FDB_TBL_RD_OP_RSLT_DATA2_DATA_LEN     32
+	#define FDB_TBL_RD_OP_RSLT_DATA2_DATA_DEFAULT 0x0
+
+struct fdb_tbl_rd_op_rslt_data2 {
+	a_uint32_t  data:32;
+};
+
+union fdb_tbl_rd_op_rslt_data2_u {
+	a_uint32_t val;
+	struct fdb_tbl_rd_op_rslt_data2 bf;
+};
+
+/*[register] FDB_TBL_OP_DATA0*/
+#define FDB_TBL_OP_DATA0
+#define FDB_TBL_OP_DATA0_ADDRESS 0x230
+#define FDB_TBL_OP_DATA0_NUM     1
+#define FDB_TBL_OP_DATA0_INC     0x10
+#define FDB_TBL_OP_DATA0_TYPE    REG_TYPE_RW
+#define FDB_TBL_OP_DATA0_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FDB_TBL_OP_DATA0_DATA
+	#define FDB_TBL_OP_DATA0_DATA_OFFSET  0
+	#define FDB_TBL_OP_DATA0_DATA_LEN     32
+	#define FDB_TBL_OP_DATA0_DATA_DEFAULT 0x0
+
+struct fdb_tbl_op_data0 {
+	a_uint32_t  data:32;
+};
+
+union fdb_tbl_op_data0_u {
+	a_uint32_t val;
+	struct fdb_tbl_op_data0 bf;
+};
+
+/*[register] FDB_TBL_OP_DATA1*/
+#define FDB_TBL_OP_DATA1
+#define FDB_TBL_OP_DATA1_ADDRESS 0x234
+#define FDB_TBL_OP_DATA1_NUM     1
+#define FDB_TBL_OP_DATA1_INC     0x10
+#define FDB_TBL_OP_DATA1_TYPE    REG_TYPE_RW
+#define FDB_TBL_OP_DATA1_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FDB_TBL_OP_DATA1_DATA
+	#define FDB_TBL_OP_DATA1_DATA_OFFSET  0
+	#define FDB_TBL_OP_DATA1_DATA_LEN     32
+	#define FDB_TBL_OP_DATA1_DATA_DEFAULT 0x0
+
+struct fdb_tbl_op_data1 {
+	a_uint32_t  data:32;
+};
+
+union fdb_tbl_op_data1_u {
+	a_uint32_t val;
+	struct fdb_tbl_op_data1 bf;
+};
+
+/*[register] FDB_TBL_OP_DATA2*/
+#define FDB_TBL_OP_DATA2
+#define FDB_TBL_OP_DATA2_ADDRESS 0x238
+#define FDB_TBL_OP_DATA2_NUM     1
+#define FDB_TBL_OP_DATA2_INC     0x10
+#define FDB_TBL_OP_DATA2_TYPE    REG_TYPE_RW
+#define FDB_TBL_OP_DATA2_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FDB_TBL_OP_DATA2_DATA
+	#define FDB_TBL_OP_DATA2_DATA_OFFSET  0
+	#define FDB_TBL_OP_DATA2_DATA_LEN     32
+	#define FDB_TBL_OP_DATA2_DATA_DEFAULT 0x0
+
+struct fdb_tbl_op_data2 {
+	a_uint32_t  data:32;
+};
+
+union fdb_tbl_op_data2_u {
+	a_uint32_t val;
+	struct fdb_tbl_op_data2 bf;
+};
+
+/*[register] FDB_TBL_RD_OP_DATA0*/
+#define FDB_TBL_RD_OP_DATA0
+#define FDB_TBL_RD_OP_DATA0_ADDRESS 0x260
+#define FDB_TBL_RD_OP_DATA0_NUM     1
+#define FDB_TBL_RD_OP_DATA0_INC     0x10
+#define FDB_TBL_RD_OP_DATA0_TYPE    REG_TYPE_RW
+#define FDB_TBL_RD_OP_DATA0_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FDB_TBL_RD_OP_DATA0_DATA
+	#define FDB_TBL_RD_OP_DATA0_DATA_OFFSET  0
+	#define FDB_TBL_RD_OP_DATA0_DATA_LEN     32
+	#define FDB_TBL_RD_OP_DATA0_DATA_DEFAULT 0x0
+
+struct fdb_tbl_rd_op_data0 {
+	a_uint32_t  data:32;
+};
+
+union fdb_tbl_rd_op_data0_u {
+	a_uint32_t val;
+	struct fdb_tbl_rd_op_data0 bf;
+};
+
+/*[register] FDB_TBL_RD_OP_DATA1*/
+#define FDB_TBL_RD_OP_DATA1
+#define FDB_TBL_RD_OP_DATA1_ADDRESS 0x264
+#define FDB_TBL_RD_OP_DATA1_NUM     1
+#define FDB_TBL_RD_OP_DATA1_INC     0x10
+#define FDB_TBL_RD_OP_DATA1_TYPE    REG_TYPE_RW
+#define FDB_TBL_RD_OP_DATA1_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FDB_TBL_RD_OP_DATA1_DATA
+	#define FDB_TBL_RD_OP_DATA1_DATA_OFFSET  0
+	#define FDB_TBL_RD_OP_DATA1_DATA_LEN     32
+	#define FDB_TBL_RD_OP_DATA1_DATA_DEFAULT 0x0
+
+struct fdb_tbl_rd_op_data1 {
+	a_uint32_t  data:32;
+};
+
+union fdb_tbl_rd_op_data1_u {
+	a_uint32_t val;
+	struct fdb_tbl_rd_op_data1 bf;
+};
+
+/*[register] FDB_TBL_RD_OP_DATA2*/
+#define FDB_TBL_RD_OP_DATA2
+#define FDB_TBL_RD_OP_DATA2_ADDRESS 0x268
+#define FDB_TBL_RD_OP_DATA2_NUM     1
+#define FDB_TBL_RD_OP_DATA2_INC     0x10
+#define FDB_TBL_RD_OP_DATA2_TYPE    REG_TYPE_RW
+#define FDB_TBL_RD_OP_DATA2_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FDB_TBL_RD_OP_DATA2_DATA
+	#define FDB_TBL_RD_OP_DATA2_DATA_OFFSET  0
+	#define FDB_TBL_RD_OP_DATA2_DATA_LEN     32
+	#define FDB_TBL_RD_OP_DATA2_DATA_DEFAULT 0x0
+
+struct fdb_tbl_rd_op_data2 {
+	a_uint32_t  data:32;
+};
+
+union fdb_tbl_rd_op_data2_u {
+	a_uint32_t val;
+	struct fdb_tbl_rd_op_data2 bf;
+};
+
+/*[register] PORT_BRIDGE_CTRL*/
+#define PORT_BRIDGE_CTRL
+#define PORT_BRIDGE_CTRL_ADDRESS 0x300
+#define PORT_BRIDGE_CTRL_NUM     8
+#define PORT_BRIDGE_CTRL_INC     0x4
+#define PORT_BRIDGE_CTRL_TYPE    REG_TYPE_RW
+#define PORT_BRIDGE_CTRL_DEFAULT 0x2ff09
+	/*[field] NEW_ADDR_LRN_EN*/
+	#define PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN
+	#define PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN_OFFSET  0
+	#define PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN_LEN     1
+	#define PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN_DEFAULT 0x1
+	/*[field] NEW_ADDR_FWD_CMD*/
+	#define PORT_BRIDGE_CTRL_NEW_ADDR_FWD_CMD
+	#define PORT_BRIDGE_CTRL_NEW_ADDR_FWD_CMD_OFFSET  1
+	#define PORT_BRIDGE_CTRL_NEW_ADDR_FWD_CMD_LEN     2
+	#define PORT_BRIDGE_CTRL_NEW_ADDR_FWD_CMD_DEFAULT 0x0
+	/*[field] STATION_MOVE_LRN_EN*/
+	#define PORT_BRIDGE_CTRL_STATION_MOVE_LRN_EN
+	#define PORT_BRIDGE_CTRL_STATION_MOVE_LRN_EN_OFFSET  3
+	#define PORT_BRIDGE_CTRL_STATION_MOVE_LRN_EN_LEN     1
+	#define PORT_BRIDGE_CTRL_STATION_MOVE_LRN_EN_DEFAULT 0x1
+	/*[field] STATION_MOVE_FWD_CMD*/
+	#define PORT_BRIDGE_CTRL_STATION_MOVE_FWD_CMD
+	#define PORT_BRIDGE_CTRL_STATION_MOVE_FWD_CMD_OFFSET  4
+	#define PORT_BRIDGE_CTRL_STATION_MOVE_FWD_CMD_LEN     2
+	#define PORT_BRIDGE_CTRL_STATION_MOVE_FWD_CMD_DEFAULT 0x0
+	/*[field] PORT_ISOLATION_BITMAP*/
+	#define PORT_BRIDGE_CTRL_PORT_ISOLATION_BITMAP
+	#define PORT_BRIDGE_CTRL_PORT_ISOLATION_BITMAP_OFFSET  8
+	#define PORT_BRIDGE_CTRL_PORT_ISOLATION_BITMAP_LEN     8
+	#define PORT_BRIDGE_CTRL_PORT_ISOLATION_BITMAP_DEFAULT 0xff
+	/*[field] TXMAC_EN*/
+	#define PORT_BRIDGE_CTRL_TXMAC_EN
+	#define PORT_BRIDGE_CTRL_TXMAC_EN_OFFSET  16
+	#define PORT_BRIDGE_CTRL_TXMAC_EN_LEN     1
+	#define PORT_BRIDGE_CTRL_TXMAC_EN_DEFAULT 0x0
+	/*[field] PROMISC_EN*/
+	#define PORT_BRIDGE_CTRL_PROMISC_EN
+	#define PORT_BRIDGE_CTRL_PROMISC_EN_OFFSET  17
+	#define PORT_BRIDGE_CTRL_PROMISC_EN_LEN     1
+	#define PORT_BRIDGE_CTRL_PROMISC_EN_DEFAULT 0x1
+
+struct port_bridge_ctrl {
+	a_uint32_t  new_addr_lrn_en:1;
+	a_uint32_t  new_addr_fwd_cmd:2;
+	a_uint32_t  station_move_lrn_en:1;
+	a_uint32_t  station_move_fwd_cmd:2;
+	a_uint32_t  _reserved0:2;
+	a_uint32_t  port_isolation_bitmap:8;
+	a_uint32_t  txmac_en:1;
+	a_uint32_t  promisc_en:1;
+	a_uint32_t  _reserved1:14;
+};
+
+union port_bridge_ctrl_u {
+	a_uint32_t val;
+	struct port_bridge_ctrl bf;
+};
+
+/*[register] PORT_LRN_LIMIT_CTRL*/
+#define PORT_LRN_LIMIT_CTRL
+#define PORT_LRN_LIMIT_CTRL_ADDRESS 0x400
+#define PORT_LRN_LIMIT_CTRL_NUM     8
+#define PORT_LRN_LIMIT_CTRL_INC     0x4
+#define PORT_LRN_LIMIT_CTRL_TYPE    REG_TYPE_RW
+#define PORT_LRN_LIMIT_CTRL_DEFAULT 0x1800
+	/*[field] LRN_LMT_CNT*/
+	#define PORT_LRN_LIMIT_CTRL_LRN_LMT_CNT
+	#define PORT_LRN_LIMIT_CTRL_LRN_LMT_CNT_OFFSET  0
+	#define PORT_LRN_LIMIT_CTRL_LRN_LMT_CNT_LEN     12
+	#define PORT_LRN_LIMIT_CTRL_LRN_LMT_CNT_DEFAULT 0x800
+	/*[field] LRN_LMT_EN*/
+	#define PORT_LRN_LIMIT_CTRL_LRN_LMT_EN
+	#define PORT_LRN_LIMIT_CTRL_LRN_LMT_EN_OFFSET  12
+	#define PORT_LRN_LIMIT_CTRL_LRN_LMT_EN_LEN     1
+	#define PORT_LRN_LIMIT_CTRL_LRN_LMT_EN_DEFAULT 0x1
+	/*[field] LRN_LMT_EXCEED_FWD*/
+	#define PORT_LRN_LIMIT_CTRL_LRN_LMT_EXCEED_FWD
+	#define PORT_LRN_LIMIT_CTRL_LRN_LMT_EXCEED_FWD_OFFSET  13
+	#define PORT_LRN_LIMIT_CTRL_LRN_LMT_EXCEED_FWD_LEN     2
+	#define PORT_LRN_LIMIT_CTRL_LRN_LMT_EXCEED_FWD_DEFAULT 0x0
+
+struct port_lrn_limit_ctrl {
+	a_uint32_t  lrn_lmt_cnt:12;
+	a_uint32_t  lrn_lmt_en:1;
+	a_uint32_t  lrn_lmt_exceed_fwd:2;
+	a_uint32_t  _reserved0:17;
+};
+
+union port_lrn_limit_ctrl_u {
+	a_uint32_t val;
+	struct port_lrn_limit_ctrl bf;
+};
+
+/*[register] PORT_LRN_LIMIT_COUNTER*/
+#define PORT_LRN_LIMIT_COUNTER
+#define PORT_LRN_LIMIT_COUNTER_ADDRESS 0x500
+#define PORT_LRN_LIMIT_COUNTER_NUM     8
+#define PORT_LRN_LIMIT_COUNTER_INC     0x4
+#define PORT_LRN_LIMIT_COUNTER_TYPE    REG_TYPE_RO
+#define PORT_LRN_LIMIT_COUNTER_DEFAULT 0x0
+	/*[field] LRN_CNT*/
+	#define PORT_LRN_LIMIT_COUNTER_LRN_CNT
+	#define PORT_LRN_LIMIT_COUNTER_LRN_CNT_OFFSET  0
+	#define PORT_LRN_LIMIT_COUNTER_LRN_CNT_LEN     12
+	#define PORT_LRN_LIMIT_COUNTER_LRN_CNT_DEFAULT 0x0
+
+struct port_lrn_limit_counter {
+	a_uint32_t  lrn_cnt:12;
+	a_uint32_t  _reserved0:20;
+};
+
+union port_lrn_limit_counter_u {
+	a_uint32_t val;
+	struct port_lrn_limit_counter bf;
+};
+
+/*[table] RFDB_TBL*/
+#define RFDB_TBL
+#define RFDB_TBL_ADDRESS 0x1000
+#define RFDB_TBL_NUM     32
+#define RFDB_TBL_INC     0x8
+#define RFDB_TBL_TYPE    REG_TYPE_RW
+#define RFDB_TBL_DEFAULT 0x0
+	/*[field] MAC_ADDR*/
+	#define RFDB_TBL_MAC_ADDR
+	#define RFDB_TBL_MAC_ADDR_OFFSET  0
+	#define RFDB_TBL_MAC_ADDR_LEN     48
+	#define RFDB_TBL_MAC_ADDR_DEFAULT 0x0
+	/*[field] VALID*/
+	#define RFDB_TBL_VALID
+	#define RFDB_TBL_VALID_OFFSET  48
+	#define RFDB_TBL_VALID_LEN     1
+	#define RFDB_TBL_VALID_DEFAULT 0x0
+
+struct rfdb_tbl {
+	a_uint32_t  mac_addr_0:32;
+	a_uint32_t  mac_addr_1:16;
+	a_uint32_t  valid:1;
+	a_uint32_t  _reserved0:15;
+};
+
+union rfdb_tbl_u {
+	a_uint32_t val[2];
+	struct rfdb_tbl bf;
+};
+
+/*[table] FDB_TBL*/
+#define FDB_TBL
+#define FDB_TBL_ADDRESS 0x10000
+#define FDB_TBL_NUM     2048
+#define FDB_TBL_INC     0x10
+#define FDB_TBL_TYPE    REG_TYPE_RW
+#define FDB_TBL_DEFAULT 0x0
+	/*[field] MAC_ADDR*/
+	#define FDB_TBL_MAC_ADDR
+	#define FDB_TBL_MAC_ADDR_OFFSET  0
+	#define FDB_TBL_MAC_ADDR_LEN     48
+	#define FDB_TBL_MAC_ADDR_DEFAULT 0x0
+	/*[field] ENTRY_VALID*/
+	#define FDB_TBL_ENTRY_VALID
+	#define FDB_TBL_ENTRY_VALID_OFFSET  48
+	#define FDB_TBL_ENTRY_VALID_LEN     1
+	#define FDB_TBL_ENTRY_VALID_DEFAULT 0x0
+	/*[field] LOOKUP_VALID*/
+	#define FDB_TBL_LOOKUP_VALID
+	#define FDB_TBL_LOOKUP_VALID_OFFSET  49
+	#define FDB_TBL_LOOKUP_VALID_LEN     1
+	#define FDB_TBL_LOOKUP_VALID_DEFAULT 0x0
+	/*[field] VSI*/
+	#define FDB_TBL_VSI
+	#define FDB_TBL_VSI_OFFSET  50
+	#define FDB_TBL_VSI_LEN     5
+	#define FDB_TBL_VSI_DEFAULT 0x0
+	/*[field] DST_INFO*/
+	#define FDB_TBL_DST_INFO
+	#define FDB_TBL_DST_INFO_OFFSET  55
+	#define FDB_TBL_DST_INFO_LEN     14
+	#define FDB_TBL_DST_INFO_DEFAULT 0x0
+	/*[field] SA_CMD*/
+	#define FDB_TBL_SA_CMD
+	#define FDB_TBL_SA_CMD_OFFSET  69
+	#define FDB_TBL_SA_CMD_LEN     2
+	#define FDB_TBL_SA_CMD_DEFAULT 0x0
+	/*[field] DA_CMD*/
+	#define FDB_TBL_DA_CMD
+	#define FDB_TBL_DA_CMD_OFFSET  71
+	#define FDB_TBL_DA_CMD_LEN     2
+	#define FDB_TBL_DA_CMD_DEFAULT 0x0
+	/*[field] HIT_AGE*/
+	#define FDB_TBL_HIT_AGE
+	#define FDB_TBL_HIT_AGE_OFFSET  73
+	#define FDB_TBL_HIT_AGE_LEN     2
+	#define FDB_TBL_HIT_AGE_DEFAULT 0x0
+
+struct fdb_tbl {
+	a_uint32_t  mac_addr_0:32;
+	a_uint32_t  mac_addr_1:16;
+	a_uint32_t  entry_valid:1;
+	a_uint32_t  lookup_valid:1;
+	a_uint32_t  vsi:5;
+	a_uint32_t  dst_info_0:9;
+	a_uint32_t  dst_info_1:5;
+	a_uint32_t  sa_cmd:2;
+	a_uint32_t  da_cmd:2;
+	a_uint32_t  hit_age:2;
+	a_uint32_t  _reserved0:21;
+};
+
+union fdb_tbl_u {
+	a_uint32_t val[3];
+	struct fdb_tbl bf;
+};
+
+
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_flow.h b/qca-ssdk/include/hsl/hppe/hppe_flow.h
new file mode 100755
index 0000000..437b720
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_flow.h
@@ -0,0 +1,2264 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_FLOW_H_
+#define _HPPE_FLOW_H_
+
+#define FLOW_CTRL1_MAX_ENTRY	3
+#define IN_FLOW_3TUPLE_TBL_MAX_ENTRY	4096
+#define IN_FLOW_IPV6_3TUPLE_TBL_MAX_ENTRY	2048
+#define IN_FLOW_IPV6_5TUPLE_TBL_MAX_ENTRY	2048
+#define IN_FLOW_TBL_MAX_ENTRY	4096
+#define EG_FLOW_TREE_MAP_TBL_MAX_ENTRY	4096
+#define IN_FLOW_CNT_TBL_MAX_ENTRY	4096
+
+sw_error_t
+hppe_in_flow_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_cnt_tbl_u *value);
+
+sw_error_t
+hppe_in_flow_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_cnt_tbl_u *value);
+
+sw_error_t
+hppe_flow_ctrl0_get(
+		a_uint32_t dev_id,
+		union flow_ctrl0_u *value);
+
+sw_error_t
+hppe_flow_ctrl0_set(
+		a_uint32_t dev_id,
+		union flow_ctrl0_u *value);
+
+sw_error_t
+hppe_flow_ctrl1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union flow_ctrl1_u *value);
+
+sw_error_t
+hppe_flow_ctrl1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union flow_ctrl1_u *value);
+
+
+sw_error_t
+hppe_in_flow_tbl_op_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_u *value);
+
+sw_error_t
+hppe_in_flow_host_tbl_op_get(
+		a_uint32_t dev_id,
+		union in_flow_host_tbl_op_u *value);
+
+sw_error_t
+hppe_in_flow_host_tbl_op_set(
+		a_uint32_t dev_id,
+		union in_flow_host_tbl_op_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data0_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data0_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data0_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data0_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data1_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data1_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data1_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data1_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data2_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data2_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data2_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data2_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data3_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data3_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data3_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data3_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data4_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data4_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data4_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data4_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data5_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data5_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data5_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data5_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data6_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data6_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data6_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data6_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data7_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data7_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data7_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data7_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data8_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data8_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data8_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data8_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data0_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data0_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data0_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data0_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data1_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data1_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data1_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data1_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data2_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data2_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data2_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data2_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data3_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data3_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data3_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data3_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data4_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data4_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data4_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data4_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data5_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data5_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data5_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data5_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data6_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data6_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data6_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data6_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data7_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data7_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data7_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data7_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data8_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data8_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data8_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data8_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data9_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data9_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data9_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data9_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_rslt_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_rslt_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_rslt_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_rslt_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_rslt_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_rslt_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_u *value);
+
+sw_error_t
+hppe_in_flow_host_tbl_rd_op_get(
+		a_uint32_t dev_id,
+		union in_flow_host_tbl_rd_op_u *value);
+
+sw_error_t
+hppe_in_flow_host_tbl_rd_op_set(
+		a_uint32_t dev_id,
+		union in_flow_host_tbl_rd_op_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data0_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data0_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data0_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data0_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data1_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data1_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data1_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data1_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data2_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data2_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data2_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data2_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data3_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data3_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data3_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data3_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data4_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data4_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data4_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data4_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data5_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data5_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data5_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data5_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data6_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data6_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data6_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data6_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data7_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data7_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data7_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data7_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data8_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data8_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data8_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data8_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data0_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data0_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data0_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data0_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data1_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data1_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data1_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data1_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data2_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data2_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data2_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data2_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data3_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data3_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data3_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data3_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data4_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data4_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data4_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data4_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data5_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data5_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data5_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data5_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data6_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data6_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data6_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data6_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data7_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data7_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data7_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data7_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data8_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data8_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data8_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data8_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data9_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data9_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data9_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data9_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_rslt_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_rslt_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_rslt_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_rslt_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_rslt_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_rslt_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data0_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data0_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data0_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data0_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data1_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data1_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data1_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data1_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data2_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data2_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data2_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data2_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data3_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data3_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data3_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data3_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data4_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data4_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data4_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data4_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data5_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data5_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data5_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data5_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data6_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data6_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data6_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data6_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data7_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data7_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data7_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data7_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data8_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data8_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data8_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data8_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data0_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data0_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data0_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data0_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data1_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data1_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data1_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data1_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data2_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data2_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data2_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data2_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data3_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data3_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data3_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data3_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data4_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data4_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data4_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data4_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data5_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data5_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data5_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data5_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data6_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data6_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data6_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data6_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data7_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data7_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data7_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data7_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data8_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data8_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data8_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data8_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data9_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data9_u *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data9_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data9_u *value);
+
+sw_error_t
+hppe_in_flow_3tuple_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_3tuple_tbl_u *value);
+
+sw_error_t
+hppe_in_flow_3tuple_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_3tuple_tbl_u *value);
+
+sw_error_t
+hppe_in_flow_ipv6_3tuple_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_ipv6_3tuple_tbl_u *value);
+
+sw_error_t
+hppe_in_flow_ipv6_3tuple_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_ipv6_3tuple_tbl_u *value);
+
+sw_error_t
+hppe_in_flow_ipv6_5tuple_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_ipv6_5tuple_tbl_u *value);
+
+sw_error_t
+hppe_in_flow_ipv6_5tuple_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_ipv6_5tuple_tbl_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_tbl_u *value);
+
+sw_error_t
+hppe_in_flow_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_tbl_u *value);
+
+sw_error_t
+hppe_eg_flow_tree_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_flow_tree_map_tbl_u *value);
+
+sw_error_t
+hppe_eg_flow_tree_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_flow_tree_map_tbl_u *value);
+
+sw_error_t
+hppe_flow_ctrl0_flow_hash_mode_0_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_ctrl0_flow_hash_mode_0_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_ctrl0_flow_age_timer_unit_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_ctrl0_flow_age_timer_unit_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_ctrl0_flow_hash_mode_1_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_ctrl0_flow_hash_mode_1_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_ctrl0_flow_age_timer_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_ctrl0_flow_age_timer_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_ctrl0_flow_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_ctrl0_flow_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_frag_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_frag_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_key_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_key_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_key_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_key_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_frag_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_frag_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_miss_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_miss_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_key_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_key_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_tcp_special_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_tcp_special_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_tcp_special_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_tcp_special_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_frag_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_frag_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_tcp_special_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_tcp_special_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_miss_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_miss_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_frag_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_frag_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_tcp_special_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_tcp_special_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_key_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_key_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_miss_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_miss_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_key_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_key_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_tcp_special_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_tcp_special_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_frag_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_frag_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_miss_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_miss_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_miss_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_miss_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_flow_tbl_op_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_cmd_id_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_cmd_id_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_byp_rslt_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_byp_rslt_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_op_mode_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_op_mode_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_op_type_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_op_type_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_op_host_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_op_host_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_op_result_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_op_result_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_busy_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_busy_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_host_tbl_op_host_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_host_tbl_op_host_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_host_tbl_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_host_tbl_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data0_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data0_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data1_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data1_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data2_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data2_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data3_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data3_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data4_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data4_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data5_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data5_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data6_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data6_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data7_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data7_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data8_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_data8_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data0_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data0_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data1_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data1_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data2_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data2_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data3_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data3_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data4_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data4_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data5_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data5_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data6_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data6_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data7_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data7_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data8_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data8_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data9_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_data9_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_op_rslt_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_op_rslt_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_valid_cnt_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_valid_cnt_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_flow_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_flow_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_cmd_id_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_cmd_id_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_op_rslt_host_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_op_rslt_host_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_cmd_id_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_cmd_id_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_byp_rslt_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_byp_rslt_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_mode_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_mode_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_type_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_type_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_host_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_host_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_result_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_result_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_busy_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_busy_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_host_tbl_rd_op_host_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_host_tbl_rd_op_host_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_host_tbl_rd_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_host_tbl_rd_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data0_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data0_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data1_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data1_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data2_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data2_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data3_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data3_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data4_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data4_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data5_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data5_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data6_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data6_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data7_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data7_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data8_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data8_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data0_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data0_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data1_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data1_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data2_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data2_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data3_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data3_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data4_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data4_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data5_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data5_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data6_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data6_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data7_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data7_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data8_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data8_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data9_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data9_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_op_rslt_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_op_rslt_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_valid_cnt_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_valid_cnt_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_flow_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_flow_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_cmd_id_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_cmd_id_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_rslt_host_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_rslt_host_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data0_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data0_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data1_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data1_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data2_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data2_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data3_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data3_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data4_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data4_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data5_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data5_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data6_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data6_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data7_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data7_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data8_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data8_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data0_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data0_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data1_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data1_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data2_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data2_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data3_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data3_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data4_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data4_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data5_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data5_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data6_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data6_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data7_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data7_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data8_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data8_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data9_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data9_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_eg_flow_tree_map_tbl_tree_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_flow_tree_map_tbl_tree_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_flow_cnt_tbl_hit_byte_counter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_in_flow_cnt_tbl_hit_byte_counter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_in_flow_cnt_tbl_hit_pkt_counter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_flow_cnt_tbl_hit_pkt_counter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_ipv4_5tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_tbl_u *entry);
+
+sw_error_t
+hppe_flow_ipv4_3tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_3tuple_tbl_u *entry);
+
+sw_error_t
+hppe_flow_ipv6_5tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry);
+
+sw_error_t
+hppe_flow_ipv6_3tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry);
+
+sw_error_t
+hppe_flow_flush_common(a_uint32_t dev_id);
+
+sw_error_t
+hppe_flow_ipv4_5tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_tbl_u *entry);
+
+sw_error_t
+hppe_flow_ipv4_3tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_3tuple_tbl_u *entry);
+
+sw_error_t
+hppe_flow_ipv6_5tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry);
+
+sw_error_t
+hppe_flow_ipv6_3tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry);
+
+sw_error_t
+hppe_flow_ipv4_5tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_tbl_u *entry);
+
+sw_error_t
+hppe_flow_ipv4_3tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_3tuple_tbl_u *entry);
+
+sw_error_t
+hppe_flow_ipv6_5tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry);
+
+sw_error_t
+hppe_flow_ipv6_3tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry);
+
+
+#include "hppe_ip_reg.h"
+
+sw_error_t
+hppe_flow_host_get_common(
+		a_uint32_t dev_id,
+		a_uint32_t op_mode,
+		a_uint32_t *index,
+		a_uint32_t *data,
+		a_uint32_t num);
+
+
+sw_error_t
+hppe_flow_host_flush_common(a_uint32_t dev_id);
+
+
+sw_error_t
+hppe_flow_host_op_both_common(
+		a_uint32_t dev_id,
+		a_uint32_t op_type,
+		a_uint32_t op_mode,
+		a_uint32_t *index);
+
+
+sw_error_t
+hppe_flow_entry_host_op_ipv4_5tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_entry_host_op_ipv4_3tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_3tuple_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_entry_host_op_ipv6_5tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_entry_host_op_ipv6_3tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_entry_host_op_ipv4_5tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_entry_host_op_ipv4_3tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_3tuple_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_entry_host_op_ipv6_5tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_entry_host_op_ipv6_3tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_entry_host_op_ipv4_5tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_entry_host_op_ipv4_3tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_3tuple_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_entry_host_op_ipv6_5tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_entry_host_op_ipv6_3tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_host_data_op_common(
+		a_uint32_t dev_id,
+		a_uint32_t op_type,
+		a_uint32_t op_mode,
+		a_uint32_t *index);
+
+
+sw_error_t
+hppe_flow_host_ipv4_data_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_host_ipv6_data_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_host_ipv4_data_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_host_ipv6_data_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_host_ipv4_data_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_tbl_u *entry);
+
+
+sw_error_t
+hppe_flow_host_ipv6_data_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_tbl_u *entry);
+
+sw_error_t
+hppe_flow_host_ipv4_data_rd_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_tbl_u *entry);
+
+sw_error_t
+hppe_flow_host_ipv6_data_rd_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_tbl_u *entry);
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_flow_reg.h b/qca-ssdk/include/hsl/hppe/hppe_flow_reg.h
new file mode 100755
index 0000000..41b9c44
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_flow_reg.h
@@ -0,0 +1,2856 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_FLOW_REG_H_
+#define _HPPE_FLOW_REG_H_
+
+/*[register] FLOW_CTRL0*/
+#define FLOW_CTRL0
+#define FLOW_CTRL0_ADDRESS 0x368
+#define FLOW_CTRL0_NUM     1
+#define FLOW_CTRL0_INC     0x4
+#define FLOW_CTRL0_TYPE    REG_TYPE_RW
+#define FLOW_CTRL0_DEFAULT 0xc89
+	/*[field] FLOW_EN*/
+	#define FLOW_CTRL0_FLOW_EN
+	#define FLOW_CTRL0_FLOW_EN_OFFSET  0
+	#define FLOW_CTRL0_FLOW_EN_LEN     1
+	#define FLOW_CTRL0_FLOW_EN_DEFAULT 0x1
+	/*[field] FLOW_HASH_MODE_0*/
+	#define FLOW_CTRL0_FLOW_HASH_MODE_0
+	#define FLOW_CTRL0_FLOW_HASH_MODE_0_OFFSET  1
+	#define FLOW_CTRL0_FLOW_HASH_MODE_0_LEN     2
+	#define FLOW_CTRL0_FLOW_HASH_MODE_0_DEFAULT 0x0
+	/*[field] FLOW_HASH_MODE_1*/
+	#define FLOW_CTRL0_FLOW_HASH_MODE_1
+	#define FLOW_CTRL0_FLOW_HASH_MODE_1_OFFSET  3
+	#define FLOW_CTRL0_FLOW_HASH_MODE_1_LEN     2
+	#define FLOW_CTRL0_FLOW_HASH_MODE_1_DEFAULT 0x1
+	/*[field] FLOW_AGE_TIMER*/
+	#define FLOW_CTRL0_FLOW_AGE_TIMER
+	#define FLOW_CTRL0_FLOW_AGE_TIMER_OFFSET  5
+	#define FLOW_CTRL0_FLOW_AGE_TIMER_LEN     16
+	#define FLOW_CTRL0_FLOW_AGE_TIMER_DEFAULT 0x64
+	/*[field] FLOW_AGE_TIMER_UNIT*/
+	#define FLOW_CTRL0_FLOW_AGE_TIMER_UNIT
+	#define FLOW_CTRL0_FLOW_AGE_TIMER_UNIT_OFFSET  21
+	#define FLOW_CTRL0_FLOW_AGE_TIMER_UNIT_LEN     2
+	#define FLOW_CTRL0_FLOW_AGE_TIMER_UNIT_DEFAULT 0x0
+
+struct flow_ctrl0 {
+	a_uint32_t  flow_en:1;
+	a_uint32_t  flow_hash_mode_0:2;
+	a_uint32_t  flow_hash_mode_1:2;
+	a_uint32_t  flow_age_timer:16;
+	a_uint32_t  flow_age_timer_unit:2;
+	a_uint32_t  _reserved0:9;
+};
+
+union flow_ctrl0_u {
+	a_uint32_t val;
+	struct flow_ctrl0 bf;
+};
+
+/*[register] FLOW_CTRL1*/
+#define FLOW_CTRL1
+#define FLOW_CTRL1_ADDRESS 0x36c
+#define FLOW_CTRL1_NUM     3
+#define FLOW_CTRL1_INC     0x4
+#define FLOW_CTRL1_TYPE    REG_TYPE_RW
+#define FLOW_CTRL1_DEFAULT 0x20000
+	/*[field] FLOW_CTL0_MISS_ACTION*/
+	#define FLOW_CTRL1_FLOW_CTL0_MISS_ACTION
+	#define FLOW_CTRL1_FLOW_CTL0_MISS_ACTION_OFFSET  0
+	#define FLOW_CTRL1_FLOW_CTL0_MISS_ACTION_LEN     2
+	#define FLOW_CTRL1_FLOW_CTL0_MISS_ACTION_DEFAULT 0x0
+	/*[field] FLOW_CTL0_FRAG_BYPASS*/
+	#define FLOW_CTRL1_FLOW_CTL0_FRAG_BYPASS
+	#define FLOW_CTRL1_FLOW_CTL0_FRAG_BYPASS_OFFSET  2
+	#define FLOW_CTRL1_FLOW_CTL0_FRAG_BYPASS_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL0_FRAG_BYPASS_DEFAULT 0x0
+	/*[field] FLOW_CTL0_TCP_SPECIAL*/
+	#define FLOW_CTRL1_FLOW_CTL0_TCP_SPECIAL
+	#define FLOW_CTRL1_FLOW_CTL0_TCP_SPECIAL_OFFSET  3
+	#define FLOW_CTRL1_FLOW_CTL0_TCP_SPECIAL_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL0_TCP_SPECIAL_DEFAULT 0x0
+	/*[field] FLOW_CTL0_BYPASS*/
+	#define FLOW_CTRL1_FLOW_CTL0_BYPASS
+	#define FLOW_CTRL1_FLOW_CTL0_BYPASS_OFFSET  4
+	#define FLOW_CTRL1_FLOW_CTL0_BYPASS_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL0_BYPASS_DEFAULT 0x0
+	/*[field] FLOW_CTL0_KEY_SEL*/
+	#define FLOW_CTRL1_FLOW_CTL0_KEY_SEL
+	#define FLOW_CTRL1_FLOW_CTL0_KEY_SEL_OFFSET  5
+	#define FLOW_CTRL1_FLOW_CTL0_KEY_SEL_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL0_KEY_SEL_DEFAULT 0x0
+	/*[field] FLOW_CTL1_MISS_ACTION*/
+	#define FLOW_CTRL1_FLOW_CTL1_MISS_ACTION
+	#define FLOW_CTRL1_FLOW_CTL1_MISS_ACTION_OFFSET  6
+	#define FLOW_CTRL1_FLOW_CTL1_MISS_ACTION_LEN     2
+	#define FLOW_CTRL1_FLOW_CTL1_MISS_ACTION_DEFAULT 0x0
+	/*[field] FLOW_CTL1_FRAG_BYPASS*/
+	#define FLOW_CTRL1_FLOW_CTL1_FRAG_BYPASS
+	#define FLOW_CTRL1_FLOW_CTL1_FRAG_BYPASS_OFFSET  8
+	#define FLOW_CTRL1_FLOW_CTL1_FRAG_BYPASS_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL1_FRAG_BYPASS_DEFAULT 0x0
+	/*[field] FLOW_CTL1_TCP_SPECIAL*/
+	#define FLOW_CTRL1_FLOW_CTL1_TCP_SPECIAL
+	#define FLOW_CTRL1_FLOW_CTL1_TCP_SPECIAL_OFFSET  9
+	#define FLOW_CTRL1_FLOW_CTL1_TCP_SPECIAL_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL1_TCP_SPECIAL_DEFAULT 0x0
+	/*[field] FLOW_CTL1_BYPASS*/
+	#define FLOW_CTRL1_FLOW_CTL1_BYPASS
+	#define FLOW_CTRL1_FLOW_CTL1_BYPASS_OFFSET  10
+	#define FLOW_CTRL1_FLOW_CTL1_BYPASS_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL1_BYPASS_DEFAULT 0x0
+	/*[field] FLOW_CTL1_KEY_SEL*/
+	#define FLOW_CTRL1_FLOW_CTL1_KEY_SEL
+	#define FLOW_CTRL1_FLOW_CTL1_KEY_SEL_OFFSET  11
+	#define FLOW_CTRL1_FLOW_CTL1_KEY_SEL_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL1_KEY_SEL_DEFAULT 0x0
+	/*[field] FLOW_CTL2_MISS_ACTION*/
+	#define FLOW_CTRL1_FLOW_CTL2_MISS_ACTION
+	#define FLOW_CTRL1_FLOW_CTL2_MISS_ACTION_OFFSET  12
+	#define FLOW_CTRL1_FLOW_CTL2_MISS_ACTION_LEN     2
+	#define FLOW_CTRL1_FLOW_CTL2_MISS_ACTION_DEFAULT 0x0
+	/*[field] FLOW_CTL2_FRAG_BYPASS*/
+	#define FLOW_CTRL1_FLOW_CTL2_FRAG_BYPASS
+	#define FLOW_CTRL1_FLOW_CTL2_FRAG_BYPASS_OFFSET  14
+	#define FLOW_CTRL1_FLOW_CTL2_FRAG_BYPASS_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL2_FRAG_BYPASS_DEFAULT 0x0
+	/*[field] FLOW_CTL2_TCP_SPECIAL*/
+	#define FLOW_CTRL1_FLOW_CTL2_TCP_SPECIAL
+	#define FLOW_CTRL1_FLOW_CTL2_TCP_SPECIAL_OFFSET  15
+	#define FLOW_CTRL1_FLOW_CTL2_TCP_SPECIAL_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL2_TCP_SPECIAL_DEFAULT 0x0
+	/*[field] FLOW_CTL2_BYPASS*/
+	#define FLOW_CTRL1_FLOW_CTL2_BYPASS
+	#define FLOW_CTRL1_FLOW_CTL2_BYPASS_OFFSET  16
+	#define FLOW_CTRL1_FLOW_CTL2_BYPASS_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL2_BYPASS_DEFAULT 0x0
+	/*[field] FLOW_CTL2_KEY_SEL*/
+	#define FLOW_CTRL1_FLOW_CTL2_KEY_SEL
+	#define FLOW_CTRL1_FLOW_CTL2_KEY_SEL_OFFSET  17
+	#define FLOW_CTRL1_FLOW_CTL2_KEY_SEL_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL2_KEY_SEL_DEFAULT 0x1
+	/*[field] FLOW_CTL3_MISS_ACTION*/
+	#define FLOW_CTRL1_FLOW_CTL3_MISS_ACTION
+	#define FLOW_CTRL1_FLOW_CTL3_MISS_ACTION_OFFSET  18
+	#define FLOW_CTRL1_FLOW_CTL3_MISS_ACTION_LEN     2
+	#define FLOW_CTRL1_FLOW_CTL3_MISS_ACTION_DEFAULT 0x0
+	/*[field] FLOW_CTL3_FRAG_BYPASS*/
+	#define FLOW_CTRL1_FLOW_CTL3_FRAG_BYPASS
+	#define FLOW_CTRL1_FLOW_CTL3_FRAG_BYPASS_OFFSET  20
+	#define FLOW_CTRL1_FLOW_CTL3_FRAG_BYPASS_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL3_FRAG_BYPASS_DEFAULT 0x0
+	/*[field] FLOW_CTL3_TCP_SPECIAL*/
+	#define FLOW_CTRL1_FLOW_CTL3_TCP_SPECIAL
+	#define FLOW_CTRL1_FLOW_CTL3_TCP_SPECIAL_OFFSET  21
+	#define FLOW_CTRL1_FLOW_CTL3_TCP_SPECIAL_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL3_TCP_SPECIAL_DEFAULT 0x0
+	/*[field] FLOW_CTL3_BYPASS*/
+	#define FLOW_CTRL1_FLOW_CTL3_BYPASS
+	#define FLOW_CTRL1_FLOW_CTL3_BYPASS_OFFSET  22
+	#define FLOW_CTRL1_FLOW_CTL3_BYPASS_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL3_BYPASS_DEFAULT 0x0
+	/*[field] FLOW_CTL3_KEY_SEL*/
+	#define FLOW_CTRL1_FLOW_CTL3_KEY_SEL
+	#define FLOW_CTRL1_FLOW_CTL3_KEY_SEL_OFFSET  23
+	#define FLOW_CTRL1_FLOW_CTL3_KEY_SEL_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL3_KEY_SEL_DEFAULT 0x0
+	/*[field] FLOW_CTL4_MISS_ACTION*/
+	#define FLOW_CTRL1_FLOW_CTL4_MISS_ACTION
+	#define FLOW_CTRL1_FLOW_CTL4_MISS_ACTION_OFFSET  24
+	#define FLOW_CTRL1_FLOW_CTL4_MISS_ACTION_LEN     2
+	#define FLOW_CTRL1_FLOW_CTL4_MISS_ACTION_DEFAULT 0x0
+	/*[field] FLOW_CTL4_FRAG_BYPASS*/
+	#define FLOW_CTRL1_FLOW_CTL4_FRAG_BYPASS
+	#define FLOW_CTRL1_FLOW_CTL4_FRAG_BYPASS_OFFSET  26
+	#define FLOW_CTRL1_FLOW_CTL4_FRAG_BYPASS_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL4_FRAG_BYPASS_DEFAULT 0x0
+	/*[field] FLOW_CTL4_TCP_SPECIAL*/
+	#define FLOW_CTRL1_FLOW_CTL4_TCP_SPECIAL
+	#define FLOW_CTRL1_FLOW_CTL4_TCP_SPECIAL_OFFSET  27
+	#define FLOW_CTRL1_FLOW_CTL4_TCP_SPECIAL_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL4_TCP_SPECIAL_DEFAULT 0x0
+	/*[field] FLOW_CTL4_BYPASS*/
+	#define FLOW_CTRL1_FLOW_CTL4_BYPASS
+	#define FLOW_CTRL1_FLOW_CTL4_BYPASS_OFFSET  28
+	#define FLOW_CTRL1_FLOW_CTL4_BYPASS_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL4_BYPASS_DEFAULT 0x0
+	/*[field] FLOW_CTL4_KEY_SEL*/
+	#define FLOW_CTRL1_FLOW_CTL4_KEY_SEL
+	#define FLOW_CTRL1_FLOW_CTL4_KEY_SEL_OFFSET  29
+	#define FLOW_CTRL1_FLOW_CTL4_KEY_SEL_LEN     1
+	#define FLOW_CTRL1_FLOW_CTL4_KEY_SEL_DEFAULT 0x0
+
+struct flow_ctrl1 {
+	a_uint32_t  flow_ctl0_miss_action:2;
+	a_uint32_t  flow_ctl0_frag_bypass:1;
+	a_uint32_t  flow_ctl0_tcp_special:1;
+	a_uint32_t  flow_ctl0_bypass:1;
+	a_uint32_t  flow_ctl0_key_sel:1;
+	a_uint32_t  flow_ctl1_miss_action:2;
+	a_uint32_t  flow_ctl1_frag_bypass:1;
+	a_uint32_t  flow_ctl1_tcp_special:1;
+	a_uint32_t  flow_ctl1_bypass:1;
+	a_uint32_t  flow_ctl1_key_sel:1;
+	a_uint32_t  flow_ctl2_miss_action:2;
+	a_uint32_t  flow_ctl2_frag_bypass:1;
+	a_uint32_t  flow_ctl2_tcp_special:1;
+	a_uint32_t  flow_ctl2_bypass:1;
+	a_uint32_t  flow_ctl2_key_sel:1;
+	a_uint32_t  flow_ctl3_miss_action:2;
+	a_uint32_t  flow_ctl3_frag_bypass:1;
+	a_uint32_t  flow_ctl3_tcp_special:1;
+	a_uint32_t  flow_ctl3_bypass:1;
+	a_uint32_t  flow_ctl3_key_sel:1;
+	a_uint32_t  flow_ctl4_miss_action:2;
+	a_uint32_t  flow_ctl4_frag_bypass:1;
+	a_uint32_t  flow_ctl4_tcp_special:1;
+	a_uint32_t  flow_ctl4_bypass:1;
+	a_uint32_t  flow_ctl4_key_sel:1;
+	a_uint32_t  _reserved0:2;
+};
+
+union flow_ctrl1_u {
+	a_uint32_t val;
+	struct flow_ctrl1 bf;
+};
+
+/*[register] IN_FLOW_TBL_OP*/
+#define IN_FLOW_TBL_OP
+#define IN_FLOW_TBL_OP_ADDRESS 0x3b8
+#define IN_FLOW_TBL_OP_NUM     1
+#define IN_FLOW_TBL_OP_INC     0x4
+#define IN_FLOW_TBL_OP_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_OP_DEFAULT 0x0
+	/*[field] CMD_ID*/
+	#define IN_FLOW_TBL_OP_CMD_ID
+	#define IN_FLOW_TBL_OP_CMD_ID_OFFSET  0
+	#define IN_FLOW_TBL_OP_CMD_ID_LEN     4
+	#define IN_FLOW_TBL_OP_CMD_ID_DEFAULT 0x0
+	/*[field] BYP_RSLT_EN*/
+	#define IN_FLOW_TBL_OP_BYP_RSLT_EN
+	#define IN_FLOW_TBL_OP_BYP_RSLT_EN_OFFSET  4
+	#define IN_FLOW_TBL_OP_BYP_RSLT_EN_LEN     1
+	#define IN_FLOW_TBL_OP_BYP_RSLT_EN_DEFAULT 0x0
+	/*[field] OP_TYPE*/
+	#define IN_FLOW_TBL_OP_OP_TYPE
+	#define IN_FLOW_TBL_OP_OP_TYPE_OFFSET  5
+	#define IN_FLOW_TBL_OP_OP_TYPE_LEN     3
+	#define IN_FLOW_TBL_OP_OP_TYPE_DEFAULT 0x0
+	/*[field] HASH_BLOCK_BITMAP*/
+	#define IN_FLOW_TBL_OP_HASH_BLOCK_BITMAP
+	#define IN_FLOW_TBL_OP_HASH_BLOCK_BITMAP_OFFSET  8
+	#define IN_FLOW_TBL_OP_HASH_BLOCK_BITMAP_LEN     2
+	#define IN_FLOW_TBL_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0
+	/*[field] OP_MODE*/
+	#define IN_FLOW_TBL_OP_OP_MODE
+	#define IN_FLOW_TBL_OP_OP_MODE_OFFSET  10
+	#define IN_FLOW_TBL_OP_OP_MODE_LEN     1
+	#define IN_FLOW_TBL_OP_OP_MODE_DEFAULT 0x0
+	/*[field] OP_HOST_EN*/
+	#define IN_FLOW_TBL_OP_OP_HOST_EN
+	#define IN_FLOW_TBL_OP_OP_HOST_EN_OFFSET  11
+	#define IN_FLOW_TBL_OP_OP_HOST_EN_LEN     1
+	#define IN_FLOW_TBL_OP_OP_HOST_EN_DEFAULT 0x0
+	/*[field] ENTRY_INDEX*/
+	#define IN_FLOW_TBL_OP_ENTRY_INDEX
+	#define IN_FLOW_TBL_OP_ENTRY_INDEX_OFFSET  12
+	#define IN_FLOW_TBL_OP_ENTRY_INDEX_LEN     12
+	#define IN_FLOW_TBL_OP_ENTRY_INDEX_DEFAULT 0x0
+	/*[field] OP_RESULT*/
+	#define IN_FLOW_TBL_OP_OP_RESULT
+	#define IN_FLOW_TBL_OP_OP_RESULT_OFFSET  24
+	#define IN_FLOW_TBL_OP_OP_RESULT_LEN     1
+	#define IN_FLOW_TBL_OP_OP_RESULT_DEFAULT 0x0
+	/*[field] BUSY*/
+	#define IN_FLOW_TBL_OP_BUSY
+	#define IN_FLOW_TBL_OP_BUSY_OFFSET  25
+	#define IN_FLOW_TBL_OP_BUSY_LEN     1
+	#define IN_FLOW_TBL_OP_BUSY_DEFAULT 0x0
+
+struct in_flow_tbl_op {
+	a_uint32_t  cmd_id:4;
+	a_uint32_t  byp_rslt_en:1;
+	a_uint32_t  op_type:3;
+	a_uint32_t  hash_block_bitmap:2;
+	a_uint32_t  op_mode:1;
+	a_uint32_t  op_host_en:1;
+	a_uint32_t  entry_index:12;
+	a_uint32_t  op_result:1;
+	a_uint32_t  busy:1;
+	a_uint32_t  _reserved0:6;
+};
+
+union in_flow_tbl_op_u {
+	a_uint32_t val;
+	struct in_flow_tbl_op bf;
+};
+
+/*[register] IN_FLOW_HOST_TBL_OP*/
+#define IN_FLOW_HOST_TBL_OP
+#define IN_FLOW_HOST_TBL_OP_ADDRESS 0x3bc
+#define IN_FLOW_HOST_TBL_OP_NUM     1
+#define IN_FLOW_HOST_TBL_OP_INC     0x4
+#define IN_FLOW_HOST_TBL_OP_TYPE    REG_TYPE_RW
+#define IN_FLOW_HOST_TBL_OP_DEFAULT 0x0
+	/*[field] HASH_BLOCK_BITMAP*/
+	#define IN_FLOW_HOST_TBL_OP_HASH_BLOCK_BITMAP
+	#define IN_FLOW_HOST_TBL_OP_HASH_BLOCK_BITMAP_OFFSET  0
+	#define IN_FLOW_HOST_TBL_OP_HASH_BLOCK_BITMAP_LEN     2
+	#define IN_FLOW_HOST_TBL_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0
+	/*[field] HOST_ENTRY_INDEX*/
+	#define IN_FLOW_HOST_TBL_OP_HOST_ENTRY_INDEX
+	#define IN_FLOW_HOST_TBL_OP_HOST_ENTRY_INDEX_OFFSET  2
+	#define IN_FLOW_HOST_TBL_OP_HOST_ENTRY_INDEX_LEN     13
+	#define IN_FLOW_HOST_TBL_OP_HOST_ENTRY_INDEX_DEFAULT 0x0
+
+struct in_flow_host_tbl_op {
+	a_uint32_t  hash_block_bitmap:2;
+	a_uint32_t  host_entry_index:13;
+	a_uint32_t  _reserved0:17;
+};
+
+union in_flow_host_tbl_op_u {
+	a_uint32_t val;
+	struct in_flow_host_tbl_op bf;
+};
+
+/*[register] IN_FLOW_TBL_OP_DATA0*/
+#define IN_FLOW_TBL_OP_DATA0
+#define IN_FLOW_TBL_OP_DATA0_ADDRESS 0x3c0
+#define IN_FLOW_TBL_OP_DATA0_NUM     1
+#define IN_FLOW_TBL_OP_DATA0_INC     0x4
+#define IN_FLOW_TBL_OP_DATA0_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_OP_DATA0_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_OP_DATA0_DATA
+	#define IN_FLOW_TBL_OP_DATA0_DATA_OFFSET  0
+	#define IN_FLOW_TBL_OP_DATA0_DATA_LEN     32
+	#define IN_FLOW_TBL_OP_DATA0_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_op_data0 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_op_data0_u {
+	a_uint32_t val;
+	struct in_flow_tbl_op_data0 bf;
+};
+
+/*[register] IN_FLOW_TBL_OP_DATA1*/
+#define IN_FLOW_TBL_OP_DATA1
+#define IN_FLOW_TBL_OP_DATA1_ADDRESS 0x3c4
+#define IN_FLOW_TBL_OP_DATA1_NUM     1
+#define IN_FLOW_TBL_OP_DATA1_INC     0x4
+#define IN_FLOW_TBL_OP_DATA1_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_OP_DATA1_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_OP_DATA1_DATA
+	#define IN_FLOW_TBL_OP_DATA1_DATA_OFFSET  0
+	#define IN_FLOW_TBL_OP_DATA1_DATA_LEN     32
+	#define IN_FLOW_TBL_OP_DATA1_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_op_data1 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_op_data1_u {
+	a_uint32_t val;
+	struct in_flow_tbl_op_data1 bf;
+};
+
+/*[register] IN_FLOW_TBL_OP_DATA2*/
+#define IN_FLOW_TBL_OP_DATA2
+#define IN_FLOW_TBL_OP_DATA2_ADDRESS 0x3c8
+#define IN_FLOW_TBL_OP_DATA2_NUM     1
+#define IN_FLOW_TBL_OP_DATA2_INC     0x4
+#define IN_FLOW_TBL_OP_DATA2_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_OP_DATA2_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_OP_DATA2_DATA
+	#define IN_FLOW_TBL_OP_DATA2_DATA_OFFSET  0
+	#define IN_FLOW_TBL_OP_DATA2_DATA_LEN     32
+	#define IN_FLOW_TBL_OP_DATA2_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_op_data2 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_op_data2_u {
+	a_uint32_t val;
+	struct in_flow_tbl_op_data2 bf;
+};
+
+/*[register] IN_FLOW_TBL_OP_DATA3*/
+#define IN_FLOW_TBL_OP_DATA3
+#define IN_FLOW_TBL_OP_DATA3_ADDRESS 0x3cc
+#define IN_FLOW_TBL_OP_DATA3_NUM     1
+#define IN_FLOW_TBL_OP_DATA3_INC     0x4
+#define IN_FLOW_TBL_OP_DATA3_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_OP_DATA3_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_OP_DATA3_DATA
+	#define IN_FLOW_TBL_OP_DATA3_DATA_OFFSET  0
+	#define IN_FLOW_TBL_OP_DATA3_DATA_LEN     32
+	#define IN_FLOW_TBL_OP_DATA3_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_op_data3 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_op_data3_u {
+	a_uint32_t val;
+	struct in_flow_tbl_op_data3 bf;
+};
+
+/*[register] IN_FLOW_TBL_OP_DATA4*/
+#define IN_FLOW_TBL_OP_DATA4
+#define IN_FLOW_TBL_OP_DATA4_ADDRESS 0x3d0
+#define IN_FLOW_TBL_OP_DATA4_NUM     1
+#define IN_FLOW_TBL_OP_DATA4_INC     0x4
+#define IN_FLOW_TBL_OP_DATA4_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_OP_DATA4_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_OP_DATA4_DATA
+	#define IN_FLOW_TBL_OP_DATA4_DATA_OFFSET  0
+	#define IN_FLOW_TBL_OP_DATA4_DATA_LEN     32
+	#define IN_FLOW_TBL_OP_DATA4_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_op_data4 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_op_data4_u {
+	a_uint32_t val;
+	struct in_flow_tbl_op_data4 bf;
+};
+
+/*[register] IN_FLOW_TBL_OP_DATA5*/
+#define IN_FLOW_TBL_OP_DATA5
+#define IN_FLOW_TBL_OP_DATA5_ADDRESS 0x3d4
+#define IN_FLOW_TBL_OP_DATA5_NUM     1
+#define IN_FLOW_TBL_OP_DATA5_INC     0x4
+#define IN_FLOW_TBL_OP_DATA5_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_OP_DATA5_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_OP_DATA5_DATA
+	#define IN_FLOW_TBL_OP_DATA5_DATA_OFFSET  0
+	#define IN_FLOW_TBL_OP_DATA5_DATA_LEN     32
+	#define IN_FLOW_TBL_OP_DATA5_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_op_data5 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_op_data5_u {
+	a_uint32_t val;
+	struct in_flow_tbl_op_data5 bf;
+};
+
+/*[register] IN_FLOW_TBL_OP_DATA6*/
+#define IN_FLOW_TBL_OP_DATA6
+#define IN_FLOW_TBL_OP_DATA6_ADDRESS 0x3d8
+#define IN_FLOW_TBL_OP_DATA6_NUM     1
+#define IN_FLOW_TBL_OP_DATA6_INC     0x4
+#define IN_FLOW_TBL_OP_DATA6_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_OP_DATA6_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_OP_DATA6_DATA
+	#define IN_FLOW_TBL_OP_DATA6_DATA_OFFSET  0
+	#define IN_FLOW_TBL_OP_DATA6_DATA_LEN     32
+	#define IN_FLOW_TBL_OP_DATA6_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_op_data6 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_op_data6_u {
+	a_uint32_t val;
+	struct in_flow_tbl_op_data6 bf;
+};
+
+/*[register] IN_FLOW_TBL_OP_DATA7*/
+#define IN_FLOW_TBL_OP_DATA7
+#define IN_FLOW_TBL_OP_DATA7_ADDRESS 0x3dc
+#define IN_FLOW_TBL_OP_DATA7_NUM     1
+#define IN_FLOW_TBL_OP_DATA7_INC     0x4
+#define IN_FLOW_TBL_OP_DATA7_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_OP_DATA7_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_OP_DATA7_DATA
+	#define IN_FLOW_TBL_OP_DATA7_DATA_OFFSET  0
+	#define IN_FLOW_TBL_OP_DATA7_DATA_LEN     32
+	#define IN_FLOW_TBL_OP_DATA7_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_op_data7 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_op_data7_u {
+	a_uint32_t val;
+	struct in_flow_tbl_op_data7 bf;
+};
+
+/*[register] IN_FLOW_TBL_OP_DATA8*/
+#define IN_FLOW_TBL_OP_DATA8
+#define IN_FLOW_TBL_OP_DATA8_ADDRESS 0x3e0
+#define IN_FLOW_TBL_OP_DATA8_NUM     1
+#define IN_FLOW_TBL_OP_DATA8_INC     0x4
+#define IN_FLOW_TBL_OP_DATA8_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_OP_DATA8_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_OP_DATA8_DATA
+	#define IN_FLOW_TBL_OP_DATA8_DATA_OFFSET  0
+	#define IN_FLOW_TBL_OP_DATA8_DATA_LEN     32
+	#define IN_FLOW_TBL_OP_DATA8_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_op_data8 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_op_data8_u {
+	a_uint32_t val;
+	struct in_flow_tbl_op_data8 bf;
+};
+
+/*[register] FLOW_HOST_TBL_OP_DATA0*/
+#define FLOW_HOST_TBL_OP_DATA0
+#define FLOW_HOST_TBL_OP_DATA0_ADDRESS 0x3e4
+#define FLOW_HOST_TBL_OP_DATA0_NUM     1
+#define FLOW_HOST_TBL_OP_DATA0_INC     0x4
+#define FLOW_HOST_TBL_OP_DATA0_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_OP_DATA0_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_OP_DATA0_DATA
+	#define FLOW_HOST_TBL_OP_DATA0_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_OP_DATA0_DATA_LEN     32
+	#define FLOW_HOST_TBL_OP_DATA0_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_op_data0 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_op_data0_u {
+	a_uint32_t val;
+	struct flow_host_tbl_op_data0 bf;
+};
+
+/*[register] FLOW_HOST_TBL_OP_DATA1*/
+#define FLOW_HOST_TBL_OP_DATA1
+#define FLOW_HOST_TBL_OP_DATA1_ADDRESS 0x3e8
+#define FLOW_HOST_TBL_OP_DATA1_NUM     1
+#define FLOW_HOST_TBL_OP_DATA1_INC     0x4
+#define FLOW_HOST_TBL_OP_DATA1_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_OP_DATA1_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_OP_DATA1_DATA
+	#define FLOW_HOST_TBL_OP_DATA1_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_OP_DATA1_DATA_LEN     32
+	#define FLOW_HOST_TBL_OP_DATA1_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_op_data1 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_op_data1_u {
+	a_uint32_t val;
+	struct flow_host_tbl_op_data1 bf;
+};
+
+/*[register] FLOW_HOST_TBL_OP_DATA2*/
+#define FLOW_HOST_TBL_OP_DATA2
+#define FLOW_HOST_TBL_OP_DATA2_ADDRESS 0x3ec
+#define FLOW_HOST_TBL_OP_DATA2_NUM     1
+#define FLOW_HOST_TBL_OP_DATA2_INC     0x4
+#define FLOW_HOST_TBL_OP_DATA2_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_OP_DATA2_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_OP_DATA2_DATA
+	#define FLOW_HOST_TBL_OP_DATA2_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_OP_DATA2_DATA_LEN     32
+	#define FLOW_HOST_TBL_OP_DATA2_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_op_data2 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_op_data2_u {
+	a_uint32_t val;
+	struct flow_host_tbl_op_data2 bf;
+};
+
+/*[register] FLOW_HOST_TBL_OP_DATA3*/
+#define FLOW_HOST_TBL_OP_DATA3
+#define FLOW_HOST_TBL_OP_DATA3_ADDRESS 0x3f0
+#define FLOW_HOST_TBL_OP_DATA3_NUM     1
+#define FLOW_HOST_TBL_OP_DATA3_INC     0x4
+#define FLOW_HOST_TBL_OP_DATA3_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_OP_DATA3_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_OP_DATA3_DATA
+	#define FLOW_HOST_TBL_OP_DATA3_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_OP_DATA3_DATA_LEN     32
+	#define FLOW_HOST_TBL_OP_DATA3_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_op_data3 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_op_data3_u {
+	a_uint32_t val;
+	struct flow_host_tbl_op_data3 bf;
+};
+
+/*[register] FLOW_HOST_TBL_OP_DATA4*/
+#define FLOW_HOST_TBL_OP_DATA4
+#define FLOW_HOST_TBL_OP_DATA4_ADDRESS 0x3f4
+#define FLOW_HOST_TBL_OP_DATA4_NUM     1
+#define FLOW_HOST_TBL_OP_DATA4_INC     0x4
+#define FLOW_HOST_TBL_OP_DATA4_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_OP_DATA4_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_OP_DATA4_DATA
+	#define FLOW_HOST_TBL_OP_DATA4_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_OP_DATA4_DATA_LEN     32
+	#define FLOW_HOST_TBL_OP_DATA4_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_op_data4 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_op_data4_u {
+	a_uint32_t val;
+	struct flow_host_tbl_op_data4 bf;
+};
+
+/*[register] FLOW_HOST_TBL_OP_DATA5*/
+#define FLOW_HOST_TBL_OP_DATA5
+#define FLOW_HOST_TBL_OP_DATA5_ADDRESS 0x3f8
+#define FLOW_HOST_TBL_OP_DATA5_NUM     1
+#define FLOW_HOST_TBL_OP_DATA5_INC     0x4
+#define FLOW_HOST_TBL_OP_DATA5_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_OP_DATA5_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_OP_DATA5_DATA
+	#define FLOW_HOST_TBL_OP_DATA5_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_OP_DATA5_DATA_LEN     32
+	#define FLOW_HOST_TBL_OP_DATA5_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_op_data5 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_op_data5_u {
+	a_uint32_t val;
+	struct flow_host_tbl_op_data5 bf;
+};
+
+/*[register] FLOW_HOST_TBL_OP_DATA6*/
+#define FLOW_HOST_TBL_OP_DATA6
+#define FLOW_HOST_TBL_OP_DATA6_ADDRESS 0x3fc
+#define FLOW_HOST_TBL_OP_DATA6_NUM     1
+#define FLOW_HOST_TBL_OP_DATA6_INC     0x4
+#define FLOW_HOST_TBL_OP_DATA6_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_OP_DATA6_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_OP_DATA6_DATA
+	#define FLOW_HOST_TBL_OP_DATA6_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_OP_DATA6_DATA_LEN     32
+	#define FLOW_HOST_TBL_OP_DATA6_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_op_data6 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_op_data6_u {
+	a_uint32_t val;
+	struct flow_host_tbl_op_data6 bf;
+};
+
+/*[register] FLOW_HOST_TBL_OP_DATA7*/
+#define FLOW_HOST_TBL_OP_DATA7
+#define FLOW_HOST_TBL_OP_DATA7_ADDRESS 0x400
+#define FLOW_HOST_TBL_OP_DATA7_NUM     1
+#define FLOW_HOST_TBL_OP_DATA7_INC     0x4
+#define FLOW_HOST_TBL_OP_DATA7_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_OP_DATA7_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_OP_DATA7_DATA
+	#define FLOW_HOST_TBL_OP_DATA7_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_OP_DATA7_DATA_LEN     32
+	#define FLOW_HOST_TBL_OP_DATA7_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_op_data7 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_op_data7_u {
+	a_uint32_t val;
+	struct flow_host_tbl_op_data7 bf;
+};
+
+/*[register] FLOW_HOST_TBL_OP_DATA8*/
+#define FLOW_HOST_TBL_OP_DATA8
+#define FLOW_HOST_TBL_OP_DATA8_ADDRESS 0x404
+#define FLOW_HOST_TBL_OP_DATA8_NUM     1
+#define FLOW_HOST_TBL_OP_DATA8_INC     0x4
+#define FLOW_HOST_TBL_OP_DATA8_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_OP_DATA8_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_OP_DATA8_DATA
+	#define FLOW_HOST_TBL_OP_DATA8_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_OP_DATA8_DATA_LEN     32
+	#define FLOW_HOST_TBL_OP_DATA8_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_op_data8 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_op_data8_u {
+	a_uint32_t val;
+	struct flow_host_tbl_op_data8 bf;
+};
+
+/*[register] FLOW_HOST_TBL_OP_DATA9*/
+#define FLOW_HOST_TBL_OP_DATA9
+#define FLOW_HOST_TBL_OP_DATA9_ADDRESS 0x408
+#define FLOW_HOST_TBL_OP_DATA9_NUM     1
+#define FLOW_HOST_TBL_OP_DATA9_INC     0x4
+#define FLOW_HOST_TBL_OP_DATA9_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_OP_DATA9_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_OP_DATA9_DATA
+	#define FLOW_HOST_TBL_OP_DATA9_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_OP_DATA9_DATA_LEN     32
+	#define FLOW_HOST_TBL_OP_DATA9_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_op_data9 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_op_data9_u {
+	a_uint32_t val;
+	struct flow_host_tbl_op_data9 bf;
+};
+
+/*[register] IN_FLOW_TBL_OP_RSLT*/
+#define IN_FLOW_TBL_OP_RSLT
+#define IN_FLOW_TBL_OP_RSLT_ADDRESS 0x40c
+#define IN_FLOW_TBL_OP_RSLT_NUM     1
+#define IN_FLOW_TBL_OP_RSLT_INC     0x4
+#define IN_FLOW_TBL_OP_RSLT_TYPE    REG_TYPE_RO
+#define IN_FLOW_TBL_OP_RSLT_DEFAULT 0x0
+	/*[field] CMD_ID*/
+	#define IN_FLOW_TBL_OP_RSLT_CMD_ID
+	#define IN_FLOW_TBL_OP_RSLT_CMD_ID_OFFSET  0
+	#define IN_FLOW_TBL_OP_RSLT_CMD_ID_LEN     4
+	#define IN_FLOW_TBL_OP_RSLT_CMD_ID_DEFAULT 0x0
+	/*[field] OP_RSLT*/
+	#define IN_FLOW_TBL_OP_RSLT_OP_RSLT
+	#define IN_FLOW_TBL_OP_RSLT_OP_RSLT_OFFSET  4
+	#define IN_FLOW_TBL_OP_RSLT_OP_RSLT_LEN     1
+	#define IN_FLOW_TBL_OP_RSLT_OP_RSLT_DEFAULT 0x0
+	/*[field] FLOW_ENTRY_INDEX*/
+	#define IN_FLOW_TBL_OP_RSLT_FLOW_ENTRY_INDEX
+	#define IN_FLOW_TBL_OP_RSLT_FLOW_ENTRY_INDEX_OFFSET  5
+	#define IN_FLOW_TBL_OP_RSLT_FLOW_ENTRY_INDEX_LEN     12
+	#define IN_FLOW_TBL_OP_RSLT_FLOW_ENTRY_INDEX_DEFAULT 0x0
+	/*[field] VALID_CNT*/
+	#define IN_FLOW_TBL_OP_RSLT_VALID_CNT
+	#define IN_FLOW_TBL_OP_RSLT_VALID_CNT_OFFSET  17
+	#define IN_FLOW_TBL_OP_RSLT_VALID_CNT_LEN     4
+	#define IN_FLOW_TBL_OP_RSLT_VALID_CNT_DEFAULT 0x0
+
+struct in_flow_tbl_op_rslt {
+	a_uint32_t  cmd_id:4;
+	a_uint32_t  op_rslt:1;
+	a_uint32_t  flow_entry_index:12;
+	a_uint32_t  valid_cnt:4;
+	a_uint32_t  _reserved0:11;
+};
+
+union in_flow_tbl_op_rslt_u {
+	a_uint32_t val;
+	struct in_flow_tbl_op_rslt bf;
+};
+
+/*[register] FLOW_HOST_TBL_OP_RSLT*/
+#define FLOW_HOST_TBL_OP_RSLT
+#define FLOW_HOST_TBL_OP_RSLT_ADDRESS 0x410
+#define FLOW_HOST_TBL_OP_RSLT_NUM     1
+#define FLOW_HOST_TBL_OP_RSLT_INC     0x4
+#define FLOW_HOST_TBL_OP_RSLT_TYPE    REG_TYPE_RO
+#define FLOW_HOST_TBL_OP_RSLT_DEFAULT 0x0
+	/*[field] HOST_ENTRY_INDEX*/
+	#define FLOW_HOST_TBL_OP_RSLT_HOST_ENTRY_INDEX
+	#define FLOW_HOST_TBL_OP_RSLT_HOST_ENTRY_INDEX_OFFSET  0
+	#define FLOW_HOST_TBL_OP_RSLT_HOST_ENTRY_INDEX_LEN     13
+	#define FLOW_HOST_TBL_OP_RSLT_HOST_ENTRY_INDEX_DEFAULT 0x0
+
+struct flow_host_tbl_op_rslt {
+	a_uint32_t  host_entry_index:13;
+	a_uint32_t  _reserved0:19;
+};
+
+union flow_host_tbl_op_rslt_u {
+	a_uint32_t val;
+	struct flow_host_tbl_op_rslt bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_OP*/
+#define IN_FLOW_TBL_RD_OP
+#define IN_FLOW_TBL_RD_OP_ADDRESS 0x414
+#define IN_FLOW_TBL_RD_OP_NUM     1
+#define IN_FLOW_TBL_RD_OP_INC     0x4
+#define IN_FLOW_TBL_RD_OP_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_RD_OP_DEFAULT 0x0
+	/*[field] CMD_ID*/
+	#define IN_FLOW_TBL_RD_OP_CMD_ID
+	#define IN_FLOW_TBL_RD_OP_CMD_ID_OFFSET  0
+	#define IN_FLOW_TBL_RD_OP_CMD_ID_LEN     4
+	#define IN_FLOW_TBL_RD_OP_CMD_ID_DEFAULT 0x0
+	/*[field] BYP_RSLT_EN*/
+	#define IN_FLOW_TBL_RD_OP_BYP_RSLT_EN
+	#define IN_FLOW_TBL_RD_OP_BYP_RSLT_EN_OFFSET  4
+	#define IN_FLOW_TBL_RD_OP_BYP_RSLT_EN_LEN     1
+	#define IN_FLOW_TBL_RD_OP_BYP_RSLT_EN_DEFAULT 0x0
+	/*[field] OP_TYPE*/
+	#define IN_FLOW_TBL_RD_OP_OP_TYPE
+	#define IN_FLOW_TBL_RD_OP_OP_TYPE_OFFSET  5
+	#define IN_FLOW_TBL_RD_OP_OP_TYPE_LEN     3
+	#define IN_FLOW_TBL_RD_OP_OP_TYPE_DEFAULT 0x0
+	/*[field] HASH_BLOCK_BITMAP*/
+	#define IN_FLOW_TBL_RD_OP_HASH_BLOCK_BITMAP
+	#define IN_FLOW_TBL_RD_OP_HASH_BLOCK_BITMAP_OFFSET  8
+	#define IN_FLOW_TBL_RD_OP_HASH_BLOCK_BITMAP_LEN     2
+	#define IN_FLOW_TBL_RD_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0
+	/*[field] OP_MODE*/
+	#define IN_FLOW_TBL_RD_OP_OP_MODE
+	#define IN_FLOW_TBL_RD_OP_OP_MODE_OFFSET  10
+	#define IN_FLOW_TBL_RD_OP_OP_MODE_LEN     1
+	#define IN_FLOW_TBL_RD_OP_OP_MODE_DEFAULT 0x0
+	/*[field] OP_HOST_EN*/
+	#define IN_FLOW_TBL_RD_OP_OP_HOST_EN
+	#define IN_FLOW_TBL_RD_OP_OP_HOST_EN_OFFSET  11
+	#define IN_FLOW_TBL_RD_OP_OP_HOST_EN_LEN     1
+	#define IN_FLOW_TBL_RD_OP_OP_HOST_EN_DEFAULT 0x0
+	/*[field] ENTRY_INDEX*/
+	#define IN_FLOW_TBL_RD_OP_ENTRY_INDEX
+	#define IN_FLOW_TBL_RD_OP_ENTRY_INDEX_OFFSET  12
+	#define IN_FLOW_TBL_RD_OP_ENTRY_INDEX_LEN     12
+	#define IN_FLOW_TBL_RD_OP_ENTRY_INDEX_DEFAULT 0x0
+	/*[field] OP_RESULT*/
+	#define IN_FLOW_TBL_RD_OP_OP_RESULT
+	#define IN_FLOW_TBL_RD_OP_OP_RESULT_OFFSET  24
+	#define IN_FLOW_TBL_RD_OP_OP_RESULT_LEN     1
+	#define IN_FLOW_TBL_RD_OP_OP_RESULT_DEFAULT 0x0
+	/*[field] BUSY*/
+	#define IN_FLOW_TBL_RD_OP_BUSY
+	#define IN_FLOW_TBL_RD_OP_BUSY_OFFSET  25
+	#define IN_FLOW_TBL_RD_OP_BUSY_LEN     1
+	#define IN_FLOW_TBL_RD_OP_BUSY_DEFAULT 0x0
+
+struct in_flow_tbl_rd_op {
+	a_uint32_t  cmd_id:4;
+	a_uint32_t  byp_rslt_en:1;
+	a_uint32_t  op_type:3;
+	a_uint32_t  hash_block_bitmap:2;
+	a_uint32_t  op_mode:1;
+	a_uint32_t  op_host_en:1;
+	a_uint32_t  entry_index:12;
+	a_uint32_t  op_result:1;
+	a_uint32_t  busy:1;
+	a_uint32_t  _reserved0:6;
+};
+
+union in_flow_tbl_rd_op_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_op bf;
+};
+
+/*[register] IN_FLOW_HOST_TBL_RD_OP*/
+#define IN_FLOW_HOST_TBL_RD_OP
+#define IN_FLOW_HOST_TBL_RD_OP_ADDRESS 0x418
+#define IN_FLOW_HOST_TBL_RD_OP_NUM     1
+#define IN_FLOW_HOST_TBL_RD_OP_INC     0x4
+#define IN_FLOW_HOST_TBL_RD_OP_TYPE    REG_TYPE_RW
+#define IN_FLOW_HOST_TBL_RD_OP_DEFAULT 0x0
+	/*[field] HASH_BLOCK_BITMAP*/
+	#define IN_FLOW_HOST_TBL_RD_OP_HASH_BLOCK_BITMAP
+	#define IN_FLOW_HOST_TBL_RD_OP_HASH_BLOCK_BITMAP_OFFSET  0
+	#define IN_FLOW_HOST_TBL_RD_OP_HASH_BLOCK_BITMAP_LEN     2
+	#define IN_FLOW_HOST_TBL_RD_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0
+	/*[field] HOST_ENTRY_INDEX*/
+	#define IN_FLOW_HOST_TBL_RD_OP_HOST_ENTRY_INDEX
+	#define IN_FLOW_HOST_TBL_RD_OP_HOST_ENTRY_INDEX_OFFSET  2
+	#define IN_FLOW_HOST_TBL_RD_OP_HOST_ENTRY_INDEX_LEN     13
+	#define IN_FLOW_HOST_TBL_RD_OP_HOST_ENTRY_INDEX_DEFAULT 0x0
+
+struct in_flow_host_tbl_rd_op {
+	a_uint32_t  hash_block_bitmap:2;
+	a_uint32_t  host_entry_index:13;
+	a_uint32_t  _reserved0:17;
+};
+
+union in_flow_host_tbl_rd_op_u {
+	a_uint32_t val;
+	struct in_flow_host_tbl_rd_op bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_OP_DATA0*/
+#define IN_FLOW_TBL_RD_OP_DATA0
+#define IN_FLOW_TBL_RD_OP_DATA0_ADDRESS 0x41c
+#define IN_FLOW_TBL_RD_OP_DATA0_NUM     1
+#define IN_FLOW_TBL_RD_OP_DATA0_INC     0x4
+#define IN_FLOW_TBL_RD_OP_DATA0_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_RD_OP_DATA0_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_OP_DATA0_DATA
+	#define IN_FLOW_TBL_RD_OP_DATA0_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_OP_DATA0_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_OP_DATA0_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_op_data0 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_op_data0_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_op_data0 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_OP_DATA1*/
+#define IN_FLOW_TBL_RD_OP_DATA1
+#define IN_FLOW_TBL_RD_OP_DATA1_ADDRESS 0x420
+#define IN_FLOW_TBL_RD_OP_DATA1_NUM     1
+#define IN_FLOW_TBL_RD_OP_DATA1_INC     0x4
+#define IN_FLOW_TBL_RD_OP_DATA1_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_RD_OP_DATA1_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_OP_DATA1_DATA
+	#define IN_FLOW_TBL_RD_OP_DATA1_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_OP_DATA1_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_OP_DATA1_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_op_data1 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_op_data1_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_op_data1 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_OP_DATA2*/
+#define IN_FLOW_TBL_RD_OP_DATA2
+#define IN_FLOW_TBL_RD_OP_DATA2_ADDRESS 0x424
+#define IN_FLOW_TBL_RD_OP_DATA2_NUM     1
+#define IN_FLOW_TBL_RD_OP_DATA2_INC     0x4
+#define IN_FLOW_TBL_RD_OP_DATA2_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_RD_OP_DATA2_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_OP_DATA2_DATA
+	#define IN_FLOW_TBL_RD_OP_DATA2_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_OP_DATA2_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_OP_DATA2_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_op_data2 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_op_data2_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_op_data2 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_OP_DATA3*/
+#define IN_FLOW_TBL_RD_OP_DATA3
+#define IN_FLOW_TBL_RD_OP_DATA3_ADDRESS 0x428
+#define IN_FLOW_TBL_RD_OP_DATA3_NUM     1
+#define IN_FLOW_TBL_RD_OP_DATA3_INC     0x4
+#define IN_FLOW_TBL_RD_OP_DATA3_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_RD_OP_DATA3_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_OP_DATA3_DATA
+	#define IN_FLOW_TBL_RD_OP_DATA3_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_OP_DATA3_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_OP_DATA3_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_op_data3 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_op_data3_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_op_data3 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_OP_DATA4*/
+#define IN_FLOW_TBL_RD_OP_DATA4
+#define IN_FLOW_TBL_RD_OP_DATA4_ADDRESS 0x42c
+#define IN_FLOW_TBL_RD_OP_DATA4_NUM     1
+#define IN_FLOW_TBL_RD_OP_DATA4_INC     0x4
+#define IN_FLOW_TBL_RD_OP_DATA4_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_RD_OP_DATA4_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_OP_DATA4_DATA
+	#define IN_FLOW_TBL_RD_OP_DATA4_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_OP_DATA4_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_OP_DATA4_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_op_data4 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_op_data4_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_op_data4 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_OP_DATA5*/
+#define IN_FLOW_TBL_RD_OP_DATA5
+#define IN_FLOW_TBL_RD_OP_DATA5_ADDRESS 0x430
+#define IN_FLOW_TBL_RD_OP_DATA5_NUM     1
+#define IN_FLOW_TBL_RD_OP_DATA5_INC     0x4
+#define IN_FLOW_TBL_RD_OP_DATA5_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_RD_OP_DATA5_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_OP_DATA5_DATA
+	#define IN_FLOW_TBL_RD_OP_DATA5_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_OP_DATA5_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_OP_DATA5_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_op_data5 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_op_data5_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_op_data5 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_OP_DATA6*/
+#define IN_FLOW_TBL_RD_OP_DATA6
+#define IN_FLOW_TBL_RD_OP_DATA6_ADDRESS 0x434
+#define IN_FLOW_TBL_RD_OP_DATA6_NUM     1
+#define IN_FLOW_TBL_RD_OP_DATA6_INC     0x4
+#define IN_FLOW_TBL_RD_OP_DATA6_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_RD_OP_DATA6_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_OP_DATA6_DATA
+	#define IN_FLOW_TBL_RD_OP_DATA6_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_OP_DATA6_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_OP_DATA6_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_op_data6 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_op_data6_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_op_data6 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_OP_DATA7*/
+#define IN_FLOW_TBL_RD_OP_DATA7
+#define IN_FLOW_TBL_RD_OP_DATA7_ADDRESS 0x438
+#define IN_FLOW_TBL_RD_OP_DATA7_NUM     1
+#define IN_FLOW_TBL_RD_OP_DATA7_INC     0x4
+#define IN_FLOW_TBL_RD_OP_DATA7_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_RD_OP_DATA7_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_OP_DATA7_DATA
+	#define IN_FLOW_TBL_RD_OP_DATA7_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_OP_DATA7_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_OP_DATA7_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_op_data7 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_op_data7_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_op_data7 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_OP_DATA8*/
+#define IN_FLOW_TBL_RD_OP_DATA8
+#define IN_FLOW_TBL_RD_OP_DATA8_ADDRESS 0x43c
+#define IN_FLOW_TBL_RD_OP_DATA8_NUM     1
+#define IN_FLOW_TBL_RD_OP_DATA8_INC     0x4
+#define IN_FLOW_TBL_RD_OP_DATA8_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_RD_OP_DATA8_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_OP_DATA8_DATA
+	#define IN_FLOW_TBL_RD_OP_DATA8_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_OP_DATA8_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_OP_DATA8_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_op_data8 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_op_data8_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_op_data8 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_OP_DATA0*/
+#define FLOW_HOST_TBL_RD_OP_DATA0
+#define FLOW_HOST_TBL_RD_OP_DATA0_ADDRESS 0x440
+#define FLOW_HOST_TBL_RD_OP_DATA0_NUM     1
+#define FLOW_HOST_TBL_RD_OP_DATA0_INC     0x4
+#define FLOW_HOST_TBL_RD_OP_DATA0_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_RD_OP_DATA0_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_OP_DATA0_DATA
+	#define FLOW_HOST_TBL_RD_OP_DATA0_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_OP_DATA0_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_OP_DATA0_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_op_data0 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_op_data0_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_op_data0 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_OP_DATA1*/
+#define FLOW_HOST_TBL_RD_OP_DATA1
+#define FLOW_HOST_TBL_RD_OP_DATA1_ADDRESS 0x444
+#define FLOW_HOST_TBL_RD_OP_DATA1_NUM     1
+#define FLOW_HOST_TBL_RD_OP_DATA1_INC     0x4
+#define FLOW_HOST_TBL_RD_OP_DATA1_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_RD_OP_DATA1_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_OP_DATA1_DATA
+	#define FLOW_HOST_TBL_RD_OP_DATA1_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_OP_DATA1_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_OP_DATA1_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_op_data1 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_op_data1_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_op_data1 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_OP_DATA2*/
+#define FLOW_HOST_TBL_RD_OP_DATA2
+#define FLOW_HOST_TBL_RD_OP_DATA2_ADDRESS 0x448
+#define FLOW_HOST_TBL_RD_OP_DATA2_NUM     1
+#define FLOW_HOST_TBL_RD_OP_DATA2_INC     0x4
+#define FLOW_HOST_TBL_RD_OP_DATA2_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_RD_OP_DATA2_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_OP_DATA2_DATA
+	#define FLOW_HOST_TBL_RD_OP_DATA2_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_OP_DATA2_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_OP_DATA2_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_op_data2 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_op_data2_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_op_data2 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_OP_DATA3*/
+#define FLOW_HOST_TBL_RD_OP_DATA3
+#define FLOW_HOST_TBL_RD_OP_DATA3_ADDRESS 0x44c
+#define FLOW_HOST_TBL_RD_OP_DATA3_NUM     1
+#define FLOW_HOST_TBL_RD_OP_DATA3_INC     0x4
+#define FLOW_HOST_TBL_RD_OP_DATA3_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_RD_OP_DATA3_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_OP_DATA3_DATA
+	#define FLOW_HOST_TBL_RD_OP_DATA3_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_OP_DATA3_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_OP_DATA3_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_op_data3 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_op_data3_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_op_data3 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_OP_DATA4*/
+#define FLOW_HOST_TBL_RD_OP_DATA4
+#define FLOW_HOST_TBL_RD_OP_DATA4_ADDRESS 0x450
+#define FLOW_HOST_TBL_RD_OP_DATA4_NUM     1
+#define FLOW_HOST_TBL_RD_OP_DATA4_INC     0x4
+#define FLOW_HOST_TBL_RD_OP_DATA4_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_RD_OP_DATA4_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_OP_DATA4_DATA
+	#define FLOW_HOST_TBL_RD_OP_DATA4_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_OP_DATA4_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_OP_DATA4_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_op_data4 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_op_data4_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_op_data4 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_OP_DATA5*/
+#define FLOW_HOST_TBL_RD_OP_DATA5
+#define FLOW_HOST_TBL_RD_OP_DATA5_ADDRESS 0x454
+#define FLOW_HOST_TBL_RD_OP_DATA5_NUM     1
+#define FLOW_HOST_TBL_RD_OP_DATA5_INC     0x4
+#define FLOW_HOST_TBL_RD_OP_DATA5_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_RD_OP_DATA5_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_OP_DATA5_DATA
+	#define FLOW_HOST_TBL_RD_OP_DATA5_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_OP_DATA5_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_OP_DATA5_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_op_data5 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_op_data5_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_op_data5 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_OP_DATA6*/
+#define FLOW_HOST_TBL_RD_OP_DATA6
+#define FLOW_HOST_TBL_RD_OP_DATA6_ADDRESS 0x458
+#define FLOW_HOST_TBL_RD_OP_DATA6_NUM     1
+#define FLOW_HOST_TBL_RD_OP_DATA6_INC     0x4
+#define FLOW_HOST_TBL_RD_OP_DATA6_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_RD_OP_DATA6_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_OP_DATA6_DATA
+	#define FLOW_HOST_TBL_RD_OP_DATA6_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_OP_DATA6_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_OP_DATA6_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_op_data6 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_op_data6_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_op_data6 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_OP_DATA7*/
+#define FLOW_HOST_TBL_RD_OP_DATA7
+#define FLOW_HOST_TBL_RD_OP_DATA7_ADDRESS 0x45c
+#define FLOW_HOST_TBL_RD_OP_DATA7_NUM     1
+#define FLOW_HOST_TBL_RD_OP_DATA7_INC     0x4
+#define FLOW_HOST_TBL_RD_OP_DATA7_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_RD_OP_DATA7_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_OP_DATA7_DATA
+	#define FLOW_HOST_TBL_RD_OP_DATA7_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_OP_DATA7_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_OP_DATA7_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_op_data7 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_op_data7_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_op_data7 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_OP_DATA8*/
+#define FLOW_HOST_TBL_RD_OP_DATA8
+#define FLOW_HOST_TBL_RD_OP_DATA8_ADDRESS 0x460
+#define FLOW_HOST_TBL_RD_OP_DATA8_NUM     1
+#define FLOW_HOST_TBL_RD_OP_DATA8_INC     0x4
+#define FLOW_HOST_TBL_RD_OP_DATA8_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_RD_OP_DATA8_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_OP_DATA8_DATA
+	#define FLOW_HOST_TBL_RD_OP_DATA8_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_OP_DATA8_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_OP_DATA8_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_op_data8 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_op_data8_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_op_data8 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_OP_DATA9*/
+#define FLOW_HOST_TBL_RD_OP_DATA9
+#define FLOW_HOST_TBL_RD_OP_DATA9_ADDRESS 0x464
+#define FLOW_HOST_TBL_RD_OP_DATA9_NUM     1
+#define FLOW_HOST_TBL_RD_OP_DATA9_INC     0x4
+#define FLOW_HOST_TBL_RD_OP_DATA9_TYPE    REG_TYPE_RW
+#define FLOW_HOST_TBL_RD_OP_DATA9_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_OP_DATA9_DATA
+	#define FLOW_HOST_TBL_RD_OP_DATA9_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_OP_DATA9_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_OP_DATA9_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_op_data9 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_op_data9_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_op_data9 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_OP_RSLT*/
+#define IN_FLOW_TBL_RD_OP_RSLT
+#define IN_FLOW_TBL_RD_OP_RSLT_ADDRESS 0x468
+#define IN_FLOW_TBL_RD_OP_RSLT_NUM     1
+#define IN_FLOW_TBL_RD_OP_RSLT_INC     0x4
+#define IN_FLOW_TBL_RD_OP_RSLT_TYPE    REG_TYPE_RO
+#define IN_FLOW_TBL_RD_OP_RSLT_DEFAULT 0x0
+	/*[field] CMD_ID*/
+	#define IN_FLOW_TBL_RD_OP_RSLT_CMD_ID
+	#define IN_FLOW_TBL_RD_OP_RSLT_CMD_ID_OFFSET  0
+	#define IN_FLOW_TBL_RD_OP_RSLT_CMD_ID_LEN     4
+	#define IN_FLOW_TBL_RD_OP_RSLT_CMD_ID_DEFAULT 0x0
+	/*[field] OP_RSLT*/
+	#define IN_FLOW_TBL_RD_OP_RSLT_OP_RSLT
+	#define IN_FLOW_TBL_RD_OP_RSLT_OP_RSLT_OFFSET  4
+	#define IN_FLOW_TBL_RD_OP_RSLT_OP_RSLT_LEN     1
+	#define IN_FLOW_TBL_RD_OP_RSLT_OP_RSLT_DEFAULT 0x0
+	/*[field] FLOW_ENTRY_INDEX*/
+	#define IN_FLOW_TBL_RD_OP_RSLT_FLOW_ENTRY_INDEX
+	#define IN_FLOW_TBL_RD_OP_RSLT_FLOW_ENTRY_INDEX_OFFSET  5
+	#define IN_FLOW_TBL_RD_OP_RSLT_FLOW_ENTRY_INDEX_LEN     12
+	#define IN_FLOW_TBL_RD_OP_RSLT_FLOW_ENTRY_INDEX_DEFAULT 0x0
+	/*[field] VALID_CNT*/
+	#define IN_FLOW_TBL_RD_OP_RSLT_VALID_CNT
+	#define IN_FLOW_TBL_RD_OP_RSLT_VALID_CNT_OFFSET  17
+	#define IN_FLOW_TBL_RD_OP_RSLT_VALID_CNT_LEN     4
+	#define IN_FLOW_TBL_RD_OP_RSLT_VALID_CNT_DEFAULT 0x0
+
+struct in_flow_tbl_rd_op_rslt {
+	a_uint32_t  cmd_id:4;
+	a_uint32_t  op_rslt:1;
+	a_uint32_t  flow_entry_index:12;
+	a_uint32_t  valid_cnt:4;
+	a_uint32_t  _reserved0:11;
+};
+
+union in_flow_tbl_rd_op_rslt_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_op_rslt bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_OP_RSLT*/
+#define FLOW_HOST_TBL_RD_OP_RSLT
+#define FLOW_HOST_TBL_RD_OP_RSLT_ADDRESS 0x46c
+#define FLOW_HOST_TBL_RD_OP_RSLT_NUM     1
+#define FLOW_HOST_TBL_RD_OP_RSLT_INC     0x4
+#define FLOW_HOST_TBL_RD_OP_RSLT_TYPE    REG_TYPE_RO
+#define FLOW_HOST_TBL_RD_OP_RSLT_DEFAULT 0x0
+	/*[field] HOST_ENTRY_INDEX*/
+	#define FLOW_HOST_TBL_RD_OP_RSLT_HOST_ENTRY_INDEX
+	#define FLOW_HOST_TBL_RD_OP_RSLT_HOST_ENTRY_INDEX_OFFSET  0
+	#define FLOW_HOST_TBL_RD_OP_RSLT_HOST_ENTRY_INDEX_LEN     13
+	#define FLOW_HOST_TBL_RD_OP_RSLT_HOST_ENTRY_INDEX_DEFAULT 0x0
+
+struct flow_host_tbl_rd_op_rslt {
+	a_uint32_t  host_entry_index:13;
+	a_uint32_t  _reserved0:19;
+};
+
+union flow_host_tbl_rd_op_rslt_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_op_rslt bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_RSLT_DATA0*/
+#define IN_FLOW_TBL_RD_RSLT_DATA0
+#define IN_FLOW_TBL_RD_RSLT_DATA0_ADDRESS 0x470
+#define IN_FLOW_TBL_RD_RSLT_DATA0_NUM     1
+#define IN_FLOW_TBL_RD_RSLT_DATA0_INC     0x4
+#define IN_FLOW_TBL_RD_RSLT_DATA0_TYPE    REG_TYPE_RO
+#define IN_FLOW_TBL_RD_RSLT_DATA0_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_RSLT_DATA0_DATA
+	#define IN_FLOW_TBL_RD_RSLT_DATA0_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_RSLT_DATA0_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_RSLT_DATA0_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_rslt_data0 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_rslt_data0_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_rslt_data0 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_RSLT_DATA1*/
+#define IN_FLOW_TBL_RD_RSLT_DATA1
+#define IN_FLOW_TBL_RD_RSLT_DATA1_ADDRESS 0x474
+#define IN_FLOW_TBL_RD_RSLT_DATA1_NUM     1
+#define IN_FLOW_TBL_RD_RSLT_DATA1_INC     0x4
+#define IN_FLOW_TBL_RD_RSLT_DATA1_TYPE    REG_TYPE_RO
+#define IN_FLOW_TBL_RD_RSLT_DATA1_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_RSLT_DATA1_DATA
+	#define IN_FLOW_TBL_RD_RSLT_DATA1_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_RSLT_DATA1_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_RSLT_DATA1_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_rslt_data1 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_rslt_data1_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_rslt_data1 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_RSLT_DATA2*/
+#define IN_FLOW_TBL_RD_RSLT_DATA2
+#define IN_FLOW_TBL_RD_RSLT_DATA2_ADDRESS 0x478
+#define IN_FLOW_TBL_RD_RSLT_DATA2_NUM     1
+#define IN_FLOW_TBL_RD_RSLT_DATA2_INC     0x4
+#define IN_FLOW_TBL_RD_RSLT_DATA2_TYPE    REG_TYPE_RO
+#define IN_FLOW_TBL_RD_RSLT_DATA2_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_RSLT_DATA2_DATA
+	#define IN_FLOW_TBL_RD_RSLT_DATA2_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_RSLT_DATA2_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_RSLT_DATA2_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_rslt_data2 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_rslt_data2_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_rslt_data2 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_RSLT_DATA3*/
+#define IN_FLOW_TBL_RD_RSLT_DATA3
+#define IN_FLOW_TBL_RD_RSLT_DATA3_ADDRESS 0x47c
+#define IN_FLOW_TBL_RD_RSLT_DATA3_NUM     1
+#define IN_FLOW_TBL_RD_RSLT_DATA3_INC     0x4
+#define IN_FLOW_TBL_RD_RSLT_DATA3_TYPE    REG_TYPE_RO
+#define IN_FLOW_TBL_RD_RSLT_DATA3_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_RSLT_DATA3_DATA
+	#define IN_FLOW_TBL_RD_RSLT_DATA3_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_RSLT_DATA3_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_RSLT_DATA3_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_rslt_data3 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_rslt_data3_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_rslt_data3 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_RSLT_DATA4*/
+#define IN_FLOW_TBL_RD_RSLT_DATA4
+#define IN_FLOW_TBL_RD_RSLT_DATA4_ADDRESS 0x480
+#define IN_FLOW_TBL_RD_RSLT_DATA4_NUM     1
+#define IN_FLOW_TBL_RD_RSLT_DATA4_INC     0x4
+#define IN_FLOW_TBL_RD_RSLT_DATA4_TYPE    REG_TYPE_RO
+#define IN_FLOW_TBL_RD_RSLT_DATA4_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_RSLT_DATA4_DATA
+	#define IN_FLOW_TBL_RD_RSLT_DATA4_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_RSLT_DATA4_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_RSLT_DATA4_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_rslt_data4 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_rslt_data4_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_rslt_data4 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_RSLT_DATA5*/
+#define IN_FLOW_TBL_RD_RSLT_DATA5
+#define IN_FLOW_TBL_RD_RSLT_DATA5_ADDRESS 0x484
+#define IN_FLOW_TBL_RD_RSLT_DATA5_NUM     1
+#define IN_FLOW_TBL_RD_RSLT_DATA5_INC     0x4
+#define IN_FLOW_TBL_RD_RSLT_DATA5_TYPE    REG_TYPE_RO
+#define IN_FLOW_TBL_RD_RSLT_DATA5_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_RSLT_DATA5_DATA
+	#define IN_FLOW_TBL_RD_RSLT_DATA5_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_RSLT_DATA5_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_RSLT_DATA5_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_rslt_data5 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_rslt_data5_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_rslt_data5 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_RSLT_DATA6*/
+#define IN_FLOW_TBL_RD_RSLT_DATA6
+#define IN_FLOW_TBL_RD_RSLT_DATA6_ADDRESS 0x488
+#define IN_FLOW_TBL_RD_RSLT_DATA6_NUM     1
+#define IN_FLOW_TBL_RD_RSLT_DATA6_INC     0x4
+#define IN_FLOW_TBL_RD_RSLT_DATA6_TYPE    REG_TYPE_RO
+#define IN_FLOW_TBL_RD_RSLT_DATA6_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_RSLT_DATA6_DATA
+	#define IN_FLOW_TBL_RD_RSLT_DATA6_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_RSLT_DATA6_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_RSLT_DATA6_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_rslt_data6 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_rslt_data6_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_rslt_data6 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_RSLT_DATA7*/
+#define IN_FLOW_TBL_RD_RSLT_DATA7
+#define IN_FLOW_TBL_RD_RSLT_DATA7_ADDRESS 0x48c
+#define IN_FLOW_TBL_RD_RSLT_DATA7_NUM     1
+#define IN_FLOW_TBL_RD_RSLT_DATA7_INC     0x4
+#define IN_FLOW_TBL_RD_RSLT_DATA7_TYPE    REG_TYPE_RO
+#define IN_FLOW_TBL_RD_RSLT_DATA7_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_RSLT_DATA7_DATA
+	#define IN_FLOW_TBL_RD_RSLT_DATA7_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_RSLT_DATA7_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_RSLT_DATA7_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_rslt_data7 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_rslt_data7_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_rslt_data7 bf;
+};
+
+/*[register] IN_FLOW_TBL_RD_RSLT_DATA8*/
+#define IN_FLOW_TBL_RD_RSLT_DATA8
+#define IN_FLOW_TBL_RD_RSLT_DATA8_ADDRESS 0x490
+#define IN_FLOW_TBL_RD_RSLT_DATA8_NUM     1
+#define IN_FLOW_TBL_RD_RSLT_DATA8_INC     0x4
+#define IN_FLOW_TBL_RD_RSLT_DATA8_TYPE    REG_TYPE_RO
+#define IN_FLOW_TBL_RD_RSLT_DATA8_DEFAULT 0x0
+	/*[field] DATA*/
+	#define IN_FLOW_TBL_RD_RSLT_DATA8_DATA
+	#define IN_FLOW_TBL_RD_RSLT_DATA8_DATA_OFFSET  0
+	#define IN_FLOW_TBL_RD_RSLT_DATA8_DATA_LEN     32
+	#define IN_FLOW_TBL_RD_RSLT_DATA8_DATA_DEFAULT 0x0
+
+struct in_flow_tbl_rd_rslt_data8 {
+	a_uint32_t  data:32;
+};
+
+union in_flow_tbl_rd_rslt_data8_u {
+	a_uint32_t val;
+	struct in_flow_tbl_rd_rslt_data8 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_RSLT_DATA0*/
+#define FLOW_HOST_TBL_RD_RSLT_DATA0
+#define FLOW_HOST_TBL_RD_RSLT_DATA0_ADDRESS 0x494
+#define FLOW_HOST_TBL_RD_RSLT_DATA0_NUM     1
+#define FLOW_HOST_TBL_RD_RSLT_DATA0_INC     0x4
+#define FLOW_HOST_TBL_RD_RSLT_DATA0_TYPE    REG_TYPE_RO
+#define FLOW_HOST_TBL_RD_RSLT_DATA0_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_RSLT_DATA0_DATA
+	#define FLOW_HOST_TBL_RD_RSLT_DATA0_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_RSLT_DATA0_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_RSLT_DATA0_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_rslt_data0 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_rslt_data0_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_rslt_data0 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_RSLT_DATA1*/
+#define FLOW_HOST_TBL_RD_RSLT_DATA1
+#define FLOW_HOST_TBL_RD_RSLT_DATA1_ADDRESS 0x498
+#define FLOW_HOST_TBL_RD_RSLT_DATA1_NUM     1
+#define FLOW_HOST_TBL_RD_RSLT_DATA1_INC     0x4
+#define FLOW_HOST_TBL_RD_RSLT_DATA1_TYPE    REG_TYPE_RO
+#define FLOW_HOST_TBL_RD_RSLT_DATA1_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_RSLT_DATA1_DATA
+	#define FLOW_HOST_TBL_RD_RSLT_DATA1_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_RSLT_DATA1_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_RSLT_DATA1_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_rslt_data1 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_rslt_data1_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_rslt_data1 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_RSLT_DATA2*/
+#define FLOW_HOST_TBL_RD_RSLT_DATA2
+#define FLOW_HOST_TBL_RD_RSLT_DATA2_ADDRESS 0x49c
+#define FLOW_HOST_TBL_RD_RSLT_DATA2_NUM     1
+#define FLOW_HOST_TBL_RD_RSLT_DATA2_INC     0x4
+#define FLOW_HOST_TBL_RD_RSLT_DATA2_TYPE    REG_TYPE_RO
+#define FLOW_HOST_TBL_RD_RSLT_DATA2_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_RSLT_DATA2_DATA
+	#define FLOW_HOST_TBL_RD_RSLT_DATA2_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_RSLT_DATA2_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_RSLT_DATA2_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_rslt_data2 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_rslt_data2_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_rslt_data2 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_RSLT_DATA3*/
+#define FLOW_HOST_TBL_RD_RSLT_DATA3
+#define FLOW_HOST_TBL_RD_RSLT_DATA3_ADDRESS 0x4a0
+#define FLOW_HOST_TBL_RD_RSLT_DATA3_NUM     1
+#define FLOW_HOST_TBL_RD_RSLT_DATA3_INC     0x4
+#define FLOW_HOST_TBL_RD_RSLT_DATA3_TYPE    REG_TYPE_RO
+#define FLOW_HOST_TBL_RD_RSLT_DATA3_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_RSLT_DATA3_DATA
+	#define FLOW_HOST_TBL_RD_RSLT_DATA3_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_RSLT_DATA3_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_RSLT_DATA3_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_rslt_data3 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_rslt_data3_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_rslt_data3 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_RSLT_DATA4*/
+#define FLOW_HOST_TBL_RD_RSLT_DATA4
+#define FLOW_HOST_TBL_RD_RSLT_DATA4_ADDRESS 0x4a4
+#define FLOW_HOST_TBL_RD_RSLT_DATA4_NUM     1
+#define FLOW_HOST_TBL_RD_RSLT_DATA4_INC     0x4
+#define FLOW_HOST_TBL_RD_RSLT_DATA4_TYPE    REG_TYPE_RO
+#define FLOW_HOST_TBL_RD_RSLT_DATA4_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_RSLT_DATA4_DATA
+	#define FLOW_HOST_TBL_RD_RSLT_DATA4_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_RSLT_DATA4_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_RSLT_DATA4_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_rslt_data4 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_rslt_data4_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_rslt_data4 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_RSLT_DATA5*/
+#define FLOW_HOST_TBL_RD_RSLT_DATA5
+#define FLOW_HOST_TBL_RD_RSLT_DATA5_ADDRESS 0x4a8
+#define FLOW_HOST_TBL_RD_RSLT_DATA5_NUM     1
+#define FLOW_HOST_TBL_RD_RSLT_DATA5_INC     0x4
+#define FLOW_HOST_TBL_RD_RSLT_DATA5_TYPE    REG_TYPE_RO
+#define FLOW_HOST_TBL_RD_RSLT_DATA5_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_RSLT_DATA5_DATA
+	#define FLOW_HOST_TBL_RD_RSLT_DATA5_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_RSLT_DATA5_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_RSLT_DATA5_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_rslt_data5 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_rslt_data5_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_rslt_data5 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_RSLT_DATA6*/
+#define FLOW_HOST_TBL_RD_RSLT_DATA6
+#define FLOW_HOST_TBL_RD_RSLT_DATA6_ADDRESS 0x4ac
+#define FLOW_HOST_TBL_RD_RSLT_DATA6_NUM     1
+#define FLOW_HOST_TBL_RD_RSLT_DATA6_INC     0x4
+#define FLOW_HOST_TBL_RD_RSLT_DATA6_TYPE    REG_TYPE_RO
+#define FLOW_HOST_TBL_RD_RSLT_DATA6_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_RSLT_DATA6_DATA
+	#define FLOW_HOST_TBL_RD_RSLT_DATA6_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_RSLT_DATA6_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_RSLT_DATA6_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_rslt_data6 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_rslt_data6_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_rslt_data6 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_RSLT_DATA7*/
+#define FLOW_HOST_TBL_RD_RSLT_DATA7
+#define FLOW_HOST_TBL_RD_RSLT_DATA7_ADDRESS 0x4b0
+#define FLOW_HOST_TBL_RD_RSLT_DATA7_NUM     1
+#define FLOW_HOST_TBL_RD_RSLT_DATA7_INC     0x4
+#define FLOW_HOST_TBL_RD_RSLT_DATA7_TYPE    REG_TYPE_RO
+#define FLOW_HOST_TBL_RD_RSLT_DATA7_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_RSLT_DATA7_DATA
+	#define FLOW_HOST_TBL_RD_RSLT_DATA7_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_RSLT_DATA7_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_RSLT_DATA7_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_rslt_data7 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_rslt_data7_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_rslt_data7 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_RSLT_DATA8*/
+#define FLOW_HOST_TBL_RD_RSLT_DATA8
+#define FLOW_HOST_TBL_RD_RSLT_DATA8_ADDRESS 0x4b4
+#define FLOW_HOST_TBL_RD_RSLT_DATA8_NUM     1
+#define FLOW_HOST_TBL_RD_RSLT_DATA8_INC     0x4
+#define FLOW_HOST_TBL_RD_RSLT_DATA8_TYPE    REG_TYPE_RO
+#define FLOW_HOST_TBL_RD_RSLT_DATA8_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_RSLT_DATA8_DATA
+	#define FLOW_HOST_TBL_RD_RSLT_DATA8_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_RSLT_DATA8_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_RSLT_DATA8_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_rslt_data8 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_rslt_data8_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_rslt_data8 bf;
+};
+
+/*[register] FLOW_HOST_TBL_RD_RSLT_DATA9*/
+#define FLOW_HOST_TBL_RD_RSLT_DATA9
+#define FLOW_HOST_TBL_RD_RSLT_DATA9_ADDRESS 0x4b8
+#define FLOW_HOST_TBL_RD_RSLT_DATA9_NUM     1
+#define FLOW_HOST_TBL_RD_RSLT_DATA9_INC     0x4
+#define FLOW_HOST_TBL_RD_RSLT_DATA9_TYPE    REG_TYPE_RO
+#define FLOW_HOST_TBL_RD_RSLT_DATA9_DEFAULT 0x0
+	/*[field] DATA*/
+	#define FLOW_HOST_TBL_RD_RSLT_DATA9_DATA
+	#define FLOW_HOST_TBL_RD_RSLT_DATA9_DATA_OFFSET  0
+	#define FLOW_HOST_TBL_RD_RSLT_DATA9_DATA_LEN     32
+	#define FLOW_HOST_TBL_RD_RSLT_DATA9_DATA_DEFAULT 0x0
+
+struct flow_host_tbl_rd_rslt_data9 {
+	a_uint32_t  data:32;
+};
+
+union flow_host_tbl_rd_rslt_data9_u {
+	a_uint32_t val;
+	struct flow_host_tbl_rd_rslt_data9 bf;
+};
+
+/*[table] IN_FLOW_3TUPLE_TBL*/
+#define IN_FLOW_3TUPLE_TBL
+#define IN_FLOW_3TUPLE_TBL_ADDRESS 0x40000
+#define IN_FLOW_3TUPLE_TBL_NUM     4096
+#define IN_FLOW_3TUPLE_TBL_INC     0x20
+#define IN_FLOW_3TUPLE_TBL_TYPE    REG_TYPE_RW
+#define IN_FLOW_3TUPLE_TBL_DEFAULT 0x0
+	/*[field] VALID*/
+	#define IN_FLOW_3TUPLE_TBL_VALID
+	#define IN_FLOW_3TUPLE_TBL_VALID_OFFSET  0
+	#define IN_FLOW_3TUPLE_TBL_VALID_LEN     1
+	#define IN_FLOW_3TUPLE_TBL_VALID_DEFAULT 0x0
+	/*[field] ENTRY_TYPE*/
+	#define IN_FLOW_3TUPLE_TBL_ENTRY_TYPE
+	#define IN_FLOW_3TUPLE_TBL_ENTRY_TYPE_OFFSET  1
+	#define IN_FLOW_3TUPLE_TBL_ENTRY_TYPE_LEN     1
+	#define IN_FLOW_3TUPLE_TBL_ENTRY_TYPE_DEFAULT 0x0
+	/*[field] HOST_ADDR_INDEX_TYPE*/
+	#define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE
+	#define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE_OFFSET  2
+	#define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE_LEN     1
+	#define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE_DEFAULT 0x0
+	/*[field] HOST_ADDR_INDEX*/
+	#define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX
+	#define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX_OFFSET  3
+	#define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX_LEN     13
+	#define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX_DEFAULT 0x0
+	/*[field] PROTOCOL_TYPE*/
+	#define IN_FLOW_3TUPLE_TBL_PROTOCOL_TYPE
+	#define IN_FLOW_3TUPLE_TBL_PROTOCOL_TYPE_OFFSET  16
+	#define IN_FLOW_3TUPLE_TBL_PROTOCOL_TYPE_LEN     2
+	#define IN_FLOW_3TUPLE_TBL_PROTOCOL_TYPE_DEFAULT 0x0
+	/*[field] AGE*/
+	#define IN_FLOW_3TUPLE_TBL_AGE
+	#define IN_FLOW_3TUPLE_TBL_AGE_OFFSET  18
+	#define IN_FLOW_3TUPLE_TBL_AGE_LEN     2
+	#define IN_FLOW_3TUPLE_TBL_AGE_DEFAULT 0x0
+	/*[field] SRC_L3_IF_VALID*/
+	#define IN_FLOW_3TUPLE_TBL_SRC_L3_IF_VALID
+	#define IN_FLOW_3TUPLE_TBL_SRC_L3_IF_VALID_OFFSET  20
+	#define IN_FLOW_3TUPLE_TBL_SRC_L3_IF_VALID_LEN     1
+	#define IN_FLOW_3TUPLE_TBL_SRC_L3_IF_VALID_DEFAULT 0x0
+	/*[field] SRC_L3_IF*/
+	#define IN_FLOW_3TUPLE_TBL_SRC_L3_IF
+	#define IN_FLOW_3TUPLE_TBL_SRC_L3_IF_OFFSET  21
+	#define IN_FLOW_3TUPLE_TBL_SRC_L3_IF_LEN     8
+	#define IN_FLOW_3TUPLE_TBL_SRC_L3_IF_DEFAULT 0x0
+	/*[field] FWD_TYPE*/
+	#define IN_FLOW_3TUPLE_TBL_FWD_TYPE
+	#define IN_FLOW_3TUPLE_TBL_FWD_TYPE_OFFSET  29
+	#define IN_FLOW_3TUPLE_TBL_FWD_TYPE_LEN     3
+	#define IN_FLOW_3TUPLE_TBL_FWD_TYPE_DEFAULT 0x0
+	/*[field] PORT_VP2 reuse FWD_TYPE[1]*/
+	#define IN_FLOW_3TUPLE_TBL_PORT_VP2
+	#define IN_FLOW_3TUPLE_TBL_PORT_VP2_OFFSET  32
+	#define IN_FLOW_3TUPLE_TBL_PORT_VP2_LEN     8
+	#define IN_FLOW_3TUPLE_TBL_PORT_VP2_DEFAULT 0x0
+	/*[field] NEXT_HOP3 reuse FWD_TYPE[2]*/
+	#define IN_FLOW_3TUPLE_TBL_NEXT_HOP3
+	#define IN_FLOW_3TUPLE_TBL_NEXT_HOP3_OFFSET  32
+	#define IN_FLOW_3TUPLE_TBL_NEXT_HOP3_LEN     12
+	#define IN_FLOW_3TUPLE_TBL_NEXT_HOP3_DEFAULT 0x0
+	/*[field] NEXT_HOP1 reuse FWD_TYPE[0]*/
+	#define IN_FLOW_3TUPLE_TBL_NEXT_HOP1
+	#define IN_FLOW_3TUPLE_TBL_NEXT_HOP1_OFFSET  32
+	#define IN_FLOW_3TUPLE_TBL_NEXT_HOP1_LEN     12
+	#define IN_FLOW_3TUPLE_TBL_NEXT_HOP1_DEFAULT 0x0
+	/*[field] NEXT_HOP2 reuse FWD_TYPE[3]*/
+	#define IN_FLOW_3TUPLE_TBL_NEXT_HOP2
+	#define IN_FLOW_3TUPLE_TBL_NEXT_HOP2_OFFSET  32
+	#define IN_FLOW_3TUPLE_TBL_NEXT_HOP2_LEN     12
+	#define IN_FLOW_3TUPLE_TBL_NEXT_HOP2_DEFAULT 0x0
+	/*[field] PORT_VP_VALID1 reuse FWD_TYPE[2]*/
+	#define IN_FLOW_3TUPLE_TBL_PORT_VP_VALID1
+	#define IN_FLOW_3TUPLE_TBL_PORT_VP_VALID1_OFFSET  44
+	#define IN_FLOW_3TUPLE_TBL_PORT_VP_VALID1_LEN     1
+	#define IN_FLOW_3TUPLE_TBL_PORT_VP_VALID1_DEFAULT 0x0
+	/*[field] PORT_VP1 reuse FWD_TYPE[2]*/
+	#define IN_FLOW_3TUPLE_TBL_PORT_VP1
+	#define IN_FLOW_3TUPLE_TBL_PORT_VP1_OFFSET  45
+	#define IN_FLOW_3TUPLE_TBL_PORT_VP1_LEN     8
+	#define IN_FLOW_3TUPLE_TBL_PORT_VP1_DEFAULT 0x0
+	/*[field] DE_ACCE*/
+	#define IN_FLOW_3TUPLE_TBL_DE_ACCE
+	#define IN_FLOW_3TUPLE_TBL_DE_ACCE_OFFSET  60
+	#define IN_FLOW_3TUPLE_TBL_DE_ACCE_LEN     1
+	#define IN_FLOW_3TUPLE_TBL_DE_ACCE_DEFAULT 0x0
+	/*[field] COPY_TO_CPU_EN*/
+	#define IN_FLOW_3TUPLE_TBL_COPY_TO_CPU_EN
+	#define IN_FLOW_3TUPLE_TBL_COPY_TO_CPU_EN_OFFSET  61
+	#define IN_FLOW_3TUPLE_TBL_COPY_TO_CPU_EN_LEN     1
+	#define IN_FLOW_3TUPLE_TBL_COPY_TO_CPU_EN_DEFAULT 0x0
+	/*[field] SYN_TOGGLE*/
+	#define IN_FLOW_3TUPLE_TBL_SYN_TOGGLE
+	#define IN_FLOW_3TUPLE_TBL_SYN_TOGGLE_OFFSET  62
+	#define IN_FLOW_3TUPLE_TBL_SYN_TOGGLE_LEN     1
+	#define IN_FLOW_3TUPLE_TBL_SYN_TOGGLE_DEFAULT 0x0
+	/*[field] PRI_PROFILE*/
+	#define IN_FLOW_3TUPLE_TBL_PRI_PROFILE
+	#define IN_FLOW_3TUPLE_TBL_PRI_PROFILE_OFFSET  63
+	#define IN_FLOW_3TUPLE_TBL_PRI_PROFILE_LEN     5
+	#define IN_FLOW_3TUPLE_TBL_PRI_PROFILE_DEFAULT 0x0
+	/*[field] SERVICE_CODE*/
+	#define IN_FLOW_3TUPLE_TBL_SERVICE_CODE
+	#define IN_FLOW_3TUPLE_TBL_SERVICE_CODE_OFFSET  68
+	#define IN_FLOW_3TUPLE_TBL_SERVICE_CODE_LEN     8
+	#define IN_FLOW_3TUPLE_TBL_SERVICE_CODE_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define IN_FLOW_3TUPLE_TBL_IP_ADDR
+	#define IN_FLOW_3TUPLE_TBL_IP_ADDR_OFFSET  76
+	#define IN_FLOW_3TUPLE_TBL_IP_ADDR_LEN     32
+	#define IN_FLOW_3TUPLE_TBL_IP_ADDR_DEFAULT 0x0
+	/*[field] IP_PROTOCOL*/
+	#define IN_FLOW_3TUPLE_TBL_IP_PROTOCOL
+	#define IN_FLOW_3TUPLE_TBL_IP_PROTOCOL_OFFSET  108
+	#define IN_FLOW_3TUPLE_TBL_IP_PROTOCOL_LEN     8
+	#define IN_FLOW_3TUPLE_TBL_IP_PROTOCOL_DEFAULT 0x0
+
+struct in_flow_tbl_1 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  port_vp2:8;
+	a_uint32_t  _reserved0:20;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:12;
+	a_uint32_t  l4_sport:16;
+	a_uint32_t  l4_dport_0:4;
+	a_uint32_t  l4_dport_1:12;
+	a_uint32_t  _reserved1:20;
+};
+
+struct in_flow_tbl_3 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  next_hop2:12;
+	a_uint32_t  l4_port2:16;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:12;
+	a_uint32_t  l4_sport:16;
+	a_uint32_t  l4_dport_0:4;
+	a_uint32_t  l4_dport_1:12;
+	a_uint32_t  _reserved0:20;
+};
+
+struct in_flow_tbl_0 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  next_hop1:12;
+	a_uint32_t  l4_port1:16;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:12;
+	a_uint32_t  l4_sport:16;
+	a_uint32_t  l4_dport_0:4;
+	a_uint32_t  l4_dport_1:12;
+	a_uint32_t  _reserved0:20;
+};
+
+struct in_flow_tbl_2 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  next_hop3:12;
+	a_uint32_t  port_vp_valid1:1;
+	a_uint32_t  port_vp1:8;
+	a_uint32_t  _reserved0:7;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:12;
+	a_uint32_t  l4_sport:16;
+	a_uint32_t  l4_dport_0:4;
+	a_uint32_t  l4_dport_1:12;
+	a_uint32_t  _reserved1:20;
+};
+
+union in_flow_tbl_u {
+	a_uint32_t val[5];
+	struct in_flow_tbl_0 bf0;
+	struct in_flow_tbl_1 bf1;
+	struct in_flow_tbl_2 bf2;
+	struct in_flow_tbl_3 bf3;
+};
+
+/*[table] IN_FLOW_IPV6_3TUPLE_TBL*/
+#define IN_FLOW_IPV6_3TUPLE_TBL
+#define IN_FLOW_IPV6_3TUPLE_TBL_ADDRESS 0x40000
+#define IN_FLOW_IPV6_3TUPLE_TBL_NUM     2048
+#define IN_FLOW_IPV6_3TUPLE_TBL_INC     0x40
+#define IN_FLOW_IPV6_3TUPLE_TBL_TYPE    REG_TYPE_RW
+#define IN_FLOW_IPV6_3TUPLE_TBL_DEFAULT 0x0
+	/*[field] VALID*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_VALID
+	#define IN_FLOW_IPV6_3TUPLE_TBL_VALID_OFFSET  0
+	#define IN_FLOW_IPV6_3TUPLE_TBL_VALID_LEN     1
+	#define IN_FLOW_IPV6_3TUPLE_TBL_VALID_DEFAULT 0x0
+	/*[field] ENTRY_TYPE*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_ENTRY_TYPE
+	#define IN_FLOW_IPV6_3TUPLE_TBL_ENTRY_TYPE_OFFSET  1
+	#define IN_FLOW_IPV6_3TUPLE_TBL_ENTRY_TYPE_LEN     1
+	#define IN_FLOW_IPV6_3TUPLE_TBL_ENTRY_TYPE_DEFAULT 0x0
+	/*[field] HOST_ADDR_INDEX_TYPE*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE
+	#define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE_OFFSET  2
+	#define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE_LEN     1
+	#define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE_DEFAULT 0x0
+	/*[field] HOST_ADDR_INDEX*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX
+	#define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX_OFFSET  3
+	#define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX_LEN     13
+	#define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX_DEFAULT 0x0
+	/*[field] PROTOCOL_TYPE*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PROTOCOL_TYPE
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PROTOCOL_TYPE_OFFSET  16
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PROTOCOL_TYPE_LEN     2
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PROTOCOL_TYPE_DEFAULT 0x0
+	/*[field] AGE*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_AGE
+	#define IN_FLOW_IPV6_3TUPLE_TBL_AGE_OFFSET  18
+	#define IN_FLOW_IPV6_3TUPLE_TBL_AGE_LEN     2
+	#define IN_FLOW_IPV6_3TUPLE_TBL_AGE_DEFAULT 0x0
+	/*[field] SRC_L3_IF_VALID*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF_VALID
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF_VALID_OFFSET  20
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF_VALID_LEN     1
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF_VALID_DEFAULT 0x0
+	/*[field] SRC_L3_IF*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF_OFFSET  21
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF_LEN     8
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF_DEFAULT 0x0
+	/*[field] FWD_TYPE*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_FWD_TYPE
+	#define IN_FLOW_IPV6_3TUPLE_TBL_FWD_TYPE_OFFSET  29
+	#define IN_FLOW_IPV6_3TUPLE_TBL_FWD_TYPE_LEN     3
+	#define IN_FLOW_IPV6_3TUPLE_TBL_FWD_TYPE_DEFAULT 0x0
+	/*[field] NEXT_HOP3 reuse FWD_TYPE[2]*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP3
+	#define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP3_OFFSET  32
+	#define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP3_LEN     12
+	#define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP3_DEFAULT 0x0
+	/*[field] NEXT_HOP1 reuse FWD_TYPE[1]*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP1
+	#define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP1_OFFSET  32
+	#define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP1_LEN     12
+	#define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP1_DEFAULT 0x0
+	/*[field] NEXT_HOP2 reuse FWD_TYPE[3]*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP2
+	#define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP2_OFFSET  32
+	#define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP2_LEN     12
+	#define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP2_DEFAULT 0x0
+	/*[field] PORT_VP2 reuse FWD_TYPE[0]*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP2
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP2_OFFSET  32
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP2_LEN     8
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP2_DEFAULT 0x0
+	/*[field] PORT_VP_VALID1 reuse FWD_TYPE[2]*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP_VALID1
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP_VALID1_OFFSET  44
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP_VALID1_LEN     1
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP_VALID1_DEFAULT 0x0
+	/*[field] PORT_VP1 reuse FWD_TYPE[2]*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP1
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP1_OFFSET  45
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP1_LEN     8
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP1_DEFAULT 0x0
+	/*[field] DE_ACCE*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_DE_ACCE
+	#define IN_FLOW_IPV6_3TUPLE_TBL_DE_ACCE_OFFSET  60
+	#define IN_FLOW_IPV6_3TUPLE_TBL_DE_ACCE_LEN     1
+	#define IN_FLOW_IPV6_3TUPLE_TBL_DE_ACCE_DEFAULT 0x0
+	/*[field] COPY_TO_CPU_EN*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_COPY_TO_CPU_EN
+	#define IN_FLOW_IPV6_3TUPLE_TBL_COPY_TO_CPU_EN_OFFSET  61
+	#define IN_FLOW_IPV6_3TUPLE_TBL_COPY_TO_CPU_EN_LEN     1
+	#define IN_FLOW_IPV6_3TUPLE_TBL_COPY_TO_CPU_EN_DEFAULT 0x0
+	/*[field] SYN_TOGGLE*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SYN_TOGGLE
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SYN_TOGGLE_OFFSET  62
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SYN_TOGGLE_LEN     1
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SYN_TOGGLE_DEFAULT 0x0
+	/*[field] PRI_PROFILE*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PRI_PROFILE
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PRI_PROFILE_OFFSET  63
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PRI_PROFILE_LEN     5
+	#define IN_FLOW_IPV6_3TUPLE_TBL_PRI_PROFILE_DEFAULT 0x0
+	/*[field] SERVICE_CODE*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SERVICE_CODE
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SERVICE_CODE_OFFSET  68
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SERVICE_CODE_LEN     8
+	#define IN_FLOW_IPV6_3TUPLE_TBL_SERVICE_CODE_DEFAULT 0x0
+	/*[field] IP_PROTOCOL*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_IP_PROTOCOL
+	#define IN_FLOW_IPV6_3TUPLE_TBL_IP_PROTOCOL_OFFSET  108
+	#define IN_FLOW_IPV6_3TUPLE_TBL_IP_PROTOCOL_LEN     8
+	#define IN_FLOW_IPV6_3TUPLE_TBL_IP_PROTOCOL_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define IN_FLOW_IPV6_3TUPLE_TBL_IP_ADDR
+	#define IN_FLOW_IPV6_3TUPLE_TBL_IP_ADDR_OFFSET  140
+	#define IN_FLOW_IPV6_3TUPLE_TBL_IP_ADDR_LEN     128
+	#define IN_FLOW_IPV6_3TUPLE_TBL_IP_ADDR_DEFAULT 0x0
+
+struct in_flow_3tuple_tbl_3 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  next_hop2:12;
+	a_uint32_t  _reserved0:16;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:12;
+	a_uint32_t  ip_protocol:8;
+	a_uint32_t  _reserved1_0:12;
+	a_uint32_t  _reserved1_1:32;
+};
+
+struct in_flow_3tuple_tbl_1 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  port_vp2:8;
+	a_uint32_t  _reserved0:20;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:12;
+	a_uint32_t  ip_protocol:8;
+	a_uint32_t  _reserved1_0:12;
+	a_uint32_t  _reserved1_1:32;
+};
+
+struct in_flow_3tuple_tbl_2 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  next_hop3:12;
+	a_uint32_t  port_vp_valid1:1;
+	a_uint32_t  port_vp1:8;
+	a_uint32_t  _reserved0:7;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:12;
+	a_uint32_t  ip_protocol:8;
+	a_uint32_t  _reserved1_0:12;
+	a_uint32_t  _reserved1_1:32;
+};
+
+struct in_flow_3tuple_tbl_0 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  next_hop1:12;
+	a_uint32_t  _reserved0:16;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:12;
+	a_uint32_t  ip_protocol:8;
+	a_uint32_t  _reserved1_0:12;
+	a_uint32_t  _reserved1_1:32;
+};
+
+union in_flow_3tuple_tbl_u {
+	a_uint32_t val[5];
+	struct in_flow_3tuple_tbl_0 bf0;
+	struct in_flow_3tuple_tbl_1 bf1;
+	struct in_flow_3tuple_tbl_2 bf2;
+	struct in_flow_3tuple_tbl_3 bf3;
+};
+
+/*[table] IN_FLOW_IPV6_5TUPLE_TBL*/
+#define IN_FLOW_IPV6_5TUPLE_TBL
+#define IN_FLOW_IPV6_5TUPLE_TBL_ADDRESS 0x40000
+#define IN_FLOW_IPV6_5TUPLE_TBL_NUM     2048
+#define IN_FLOW_IPV6_5TUPLE_TBL_INC     0x40
+#define IN_FLOW_IPV6_5TUPLE_TBL_TYPE    REG_TYPE_RW
+#define IN_FLOW_IPV6_5TUPLE_TBL_DEFAULT 0x0
+	/*[field] VALID*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_VALID
+	#define IN_FLOW_IPV6_5TUPLE_TBL_VALID_OFFSET  0
+	#define IN_FLOW_IPV6_5TUPLE_TBL_VALID_LEN     1
+	#define IN_FLOW_IPV6_5TUPLE_TBL_VALID_DEFAULT 0x0
+	/*[field] ENTRY_TYPE*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_ENTRY_TYPE
+	#define IN_FLOW_IPV6_5TUPLE_TBL_ENTRY_TYPE_OFFSET  1
+	#define IN_FLOW_IPV6_5TUPLE_TBL_ENTRY_TYPE_LEN     1
+	#define IN_FLOW_IPV6_5TUPLE_TBL_ENTRY_TYPE_DEFAULT 0x0
+	/*[field] HOST_ADDR_INDEX_TYPE*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX_TYPE
+	#define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX_TYPE_OFFSET  2
+	#define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX_TYPE_LEN     1
+	#define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX_TYPE_DEFAULT 0x0
+	/*[field] HOST_ADDR_INDEX*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX
+	#define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX_OFFSET  3
+	#define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX_LEN     13
+	#define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX_DEFAULT 0x0
+	/*[field] PROTOCOL_TYPE*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PROTOCOL_TYPE
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PROTOCOL_TYPE_OFFSET  16
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PROTOCOL_TYPE_LEN     2
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PROTOCOL_TYPE_DEFAULT 0x0
+	/*[field] AGE*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_AGE
+	#define IN_FLOW_IPV6_5TUPLE_TBL_AGE_OFFSET  18
+	#define IN_FLOW_IPV6_5TUPLE_TBL_AGE_LEN     2
+	#define IN_FLOW_IPV6_5TUPLE_TBL_AGE_DEFAULT 0x0
+	/*[field] SRC_L3_IF_VALID*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF_VALID
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF_VALID_OFFSET  20
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF_VALID_LEN     1
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF_VALID_DEFAULT 0x0
+	/*[field] SRC_L3_IF*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF_OFFSET  21
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF_LEN     8
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF_DEFAULT 0x0
+	/*[field] FWD_TYPE*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_FWD_TYPE
+	#define IN_FLOW_IPV6_5TUPLE_TBL_FWD_TYPE_OFFSET  29
+	#define IN_FLOW_IPV6_5TUPLE_TBL_FWD_TYPE_LEN     3
+	#define IN_FLOW_IPV6_5TUPLE_TBL_FWD_TYPE_DEFAULT 0x0
+	/*[field] NEXT_HOP2 reuse FWD_TYPE[3]*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP2
+	#define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP2_OFFSET  32
+	#define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP2_LEN     12
+	#define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP2_DEFAULT 0x0
+	/*[field] PORT_VP2 reuse FWD_TYPE[1]*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP2
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP2_OFFSET  32
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP2_LEN     8
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP2_DEFAULT 0x0
+	/*[field] NEXT_HOP3 reuse FWD_TYPE[2]*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP3
+	#define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP3_OFFSET  32
+	#define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP3_LEN     12
+	#define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP3_DEFAULT 0x0
+	/*[field] NEXT_HOP1 reuse FWD_TYPE[0]*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP1
+	#define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP1_OFFSET  32
+	#define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP1_LEN     12
+	#define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP1_DEFAULT 0x0
+	/*[field] PORT_VP_VALID1 reuse FWD_TYPE[2]*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP_VALID1
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP_VALID1_OFFSET  44
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP_VALID1_LEN     1
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP_VALID1_DEFAULT 0x0
+	/*[field] PORT_VP1 reuse FWD_TYPE[2]*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP1
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP1_OFFSET  45
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP1_LEN     8
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP1_DEFAULT 0x0
+	/*[field] DE_ACCE*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_DE_ACCE
+	#define IN_FLOW_IPV6_5TUPLE_TBL_DE_ACCE_OFFSET  60
+	#define IN_FLOW_IPV6_5TUPLE_TBL_DE_ACCE_LEN     1
+	#define IN_FLOW_IPV6_5TUPLE_TBL_DE_ACCE_DEFAULT 0x0
+	/*[field] COPY_TO_CPU_EN*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_COPY_TO_CPU_EN
+	#define IN_FLOW_IPV6_5TUPLE_TBL_COPY_TO_CPU_EN_OFFSET  61
+	#define IN_FLOW_IPV6_5TUPLE_TBL_COPY_TO_CPU_EN_LEN     1
+	#define IN_FLOW_IPV6_5TUPLE_TBL_COPY_TO_CPU_EN_DEFAULT 0x0
+	/*[field] SYN_TOGGLE*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SYN_TOGGLE
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SYN_TOGGLE_OFFSET  62
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SYN_TOGGLE_LEN     1
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SYN_TOGGLE_DEFAULT 0x0
+	/*[field] PRI_PROFILE*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PRI_PROFILE
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PRI_PROFILE_OFFSET  63
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PRI_PROFILE_LEN     5
+	#define IN_FLOW_IPV6_5TUPLE_TBL_PRI_PROFILE_DEFAULT 0x0
+	/*[field] SERVICE_CODE*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SERVICE_CODE
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SERVICE_CODE_OFFSET  68
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SERVICE_CODE_LEN     8
+	#define IN_FLOW_IPV6_5TUPLE_TBL_SERVICE_CODE_DEFAULT 0x0
+	/*[field] L4_SPORT*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_L4_SPORT
+	#define IN_FLOW_IPV6_5TUPLE_TBL_L4_SPORT_OFFSET  108
+	#define IN_FLOW_IPV6_5TUPLE_TBL_L4_SPORT_LEN     16
+	#define IN_FLOW_IPV6_5TUPLE_TBL_L4_SPORT_DEFAULT 0x0
+	/*[field] L4_DPORT*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_L4_DPORT
+	#define IN_FLOW_IPV6_5TUPLE_TBL_L4_DPORT_OFFSET  124
+	#define IN_FLOW_IPV6_5TUPLE_TBL_L4_DPORT_LEN     16
+	#define IN_FLOW_IPV6_5TUPLE_TBL_L4_DPORT_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define IN_FLOW_IPV6_5TUPLE_TBL_IP_ADDR
+	#define IN_FLOW_IPV6_5TUPLE_TBL_IP_ADDR_OFFSET  140
+	#define IN_FLOW_IPV6_5TUPLE_TBL_IP_ADDR_LEN     128
+	#define IN_FLOW_IPV6_5TUPLE_TBL_IP_ADDR_DEFAULT 0x0
+
+struct in_flow_ipv6_5tuple_tbl_1 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  port_vp2:8;
+	a_uint32_t  _reserved0:20;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  _reserved1_0:20;
+	a_uint32_t  _reserved1_1:12;
+	a_uint32_t  l4_sport:16;
+	a_uint32_t  l4_dport_0:4;
+	a_uint32_t  l4_dport_1:12;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:32;
+	a_uint32_t  ip_addr_2:32;
+	a_uint32_t  ip_addr_3:32;
+	a_uint32_t  ip_addr_4:12;
+	a_uint32_t  _reserved2:20;
+};
+
+struct in_flow_ipv6_5tuple_tbl_0 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  next_hop1:12;
+	a_uint32_t  _reserved0:16;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  _reserved1_0:20;
+	a_uint32_t  _reserved1_1:12;
+	a_uint32_t  l4_sport:16;
+	a_uint32_t  l4_dport_0:4;
+	a_uint32_t  l4_dport_1:12;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:32;
+	a_uint32_t  ip_addr_2:32;
+	a_uint32_t  ip_addr_3:32;
+	a_uint32_t  ip_addr_4:12;
+	a_uint32_t  _reserved2:20;
+};
+
+struct in_flow_ipv6_5tuple_tbl_2 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  next_hop3:12;
+	a_uint32_t  port_vp_valid1:1;
+	a_uint32_t  port_vp1:8;
+	a_uint32_t  _reserved0:7;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  _reserved1_0:20;
+	a_uint32_t  _reserved1_1:12;
+	a_uint32_t  l4_sport:16;
+	a_uint32_t  l4_dport_0:4;
+	a_uint32_t  l4_dport_1:12;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:32;
+	a_uint32_t  ip_addr_2:32;
+	a_uint32_t  ip_addr_3:32;
+	a_uint32_t  ip_addr_4:12;
+	a_uint32_t  _reserved2:20;
+};
+
+struct in_flow_ipv6_5tuple_tbl_3 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  next_hop2:12;
+	a_uint32_t  _reserved0:16;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  _reserved1_0:20;
+	a_uint32_t  _reserved1_1:12;
+	a_uint32_t  l4_sport:16;
+	a_uint32_t  l4_dport_0:4;
+	a_uint32_t  l4_dport_1:12;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:32;
+	a_uint32_t  ip_addr_2:32;
+	a_uint32_t  ip_addr_3:32;
+	a_uint32_t  ip_addr_4:12;
+	a_uint32_t  _reserved2:20;
+};
+
+union in_flow_ipv6_5tuple_tbl_u {
+	a_uint32_t val[9];
+	struct in_flow_ipv6_5tuple_tbl_0 bf0;
+	struct in_flow_ipv6_5tuple_tbl_1 bf1;
+	struct in_flow_ipv6_5tuple_tbl_2 bf2;
+	struct in_flow_ipv6_5tuple_tbl_3 bf3;
+};
+
+/*[table] IN_FLOW_TBL*/
+#define IN_FLOW_TBL
+#define IN_FLOW_TBL_ADDRESS 0x40000
+#define IN_FLOW_TBL_NUM     4096
+#define IN_FLOW_TBL_INC     0x20
+#define IN_FLOW_TBL_TYPE    REG_TYPE_RW
+#define IN_FLOW_TBL_DEFAULT 0x0
+	/*[field] VALID*/
+	#define IN_FLOW_TBL_VALID
+	#define IN_FLOW_TBL_VALID_OFFSET  0
+	#define IN_FLOW_TBL_VALID_LEN     1
+	#define IN_FLOW_TBL_VALID_DEFAULT 0x0
+	/*[field] ENTRY_TYPE*/
+	#define IN_FLOW_TBL_ENTRY_TYPE
+	#define IN_FLOW_TBL_ENTRY_TYPE_OFFSET  1
+	#define IN_FLOW_TBL_ENTRY_TYPE_LEN     1
+	#define IN_FLOW_TBL_ENTRY_TYPE_DEFAULT 0x0
+	/*[field] HOST_ADDR_INDEX_TYPE*/
+	#define IN_FLOW_TBL_HOST_ADDR_INDEX_TYPE
+	#define IN_FLOW_TBL_HOST_ADDR_INDEX_TYPE_OFFSET  2
+	#define IN_FLOW_TBL_HOST_ADDR_INDEX_TYPE_LEN     1
+	#define IN_FLOW_TBL_HOST_ADDR_INDEX_TYPE_DEFAULT 0x0
+	/*[field] HOST_ADDR_INDEX*/
+	#define IN_FLOW_TBL_HOST_ADDR_INDEX
+	#define IN_FLOW_TBL_HOST_ADDR_INDEX_OFFSET  3
+	#define IN_FLOW_TBL_HOST_ADDR_INDEX_LEN     13
+	#define IN_FLOW_TBL_HOST_ADDR_INDEX_DEFAULT 0x0
+	/*[field] PROTOCOL_TYPE*/
+	#define IN_FLOW_TBL_PROTOCOL_TYPE
+	#define IN_FLOW_TBL_PROTOCOL_TYPE_OFFSET  16
+	#define IN_FLOW_TBL_PROTOCOL_TYPE_LEN     2
+	#define IN_FLOW_TBL_PROTOCOL_TYPE_DEFAULT 0x0
+	/*[field] AGE*/
+	#define IN_FLOW_TBL_AGE
+	#define IN_FLOW_TBL_AGE_OFFSET  18
+	#define IN_FLOW_TBL_AGE_LEN     2
+	#define IN_FLOW_TBL_AGE_DEFAULT 0x0
+	/*[field] SRC_L3_IF_VALID*/
+	#define IN_FLOW_TBL_SRC_L3_IF_VALID
+	#define IN_FLOW_TBL_SRC_L3_IF_VALID_OFFSET  20
+	#define IN_FLOW_TBL_SRC_L3_IF_VALID_LEN     1
+	#define IN_FLOW_TBL_SRC_L3_IF_VALID_DEFAULT 0x0
+	/*[field] SRC_L3_IF*/
+	#define IN_FLOW_TBL_SRC_L3_IF
+	#define IN_FLOW_TBL_SRC_L3_IF_OFFSET  21
+	#define IN_FLOW_TBL_SRC_L3_IF_LEN     8
+	#define IN_FLOW_TBL_SRC_L3_IF_DEFAULT 0x0
+	/*[field] FWD_TYPE*/
+	#define IN_FLOW_TBL_FWD_TYPE
+	#define IN_FLOW_TBL_FWD_TYPE_OFFSET  29
+	#define IN_FLOW_TBL_FWD_TYPE_LEN     3
+	#define IN_FLOW_TBL_FWD_TYPE_DEFAULT 0x0
+	/*[field] PORT_VP2 reuse FWD_TYPE[1]*/
+	#define IN_FLOW_TBL_PORT_VP2
+	#define IN_FLOW_TBL_PORT_VP2_OFFSET  32
+	#define IN_FLOW_TBL_PORT_VP2_LEN     8
+	#define IN_FLOW_TBL_PORT_VP2_DEFAULT 0x0
+	/*[field] NEXT_HOP2 reuse FWD_TYPE[3]*/
+	#define IN_FLOW_TBL_NEXT_HOP2
+	#define IN_FLOW_TBL_NEXT_HOP2_OFFSET  32
+	#define IN_FLOW_TBL_NEXT_HOP2_LEN     12
+	#define IN_FLOW_TBL_NEXT_HOP2_DEFAULT 0x0
+	/*[field] NEXT_HOP3 reuse FWD_TYPE[2]*/
+	#define IN_FLOW_TBL_NEXT_HOP3
+	#define IN_FLOW_TBL_NEXT_HOP3_OFFSET  32
+	#define IN_FLOW_TBL_NEXT_HOP3_LEN     12
+	#define IN_FLOW_TBL_NEXT_HOP3_DEFAULT 0x0
+	/*[field] NEXT_HOP1 reuse FWD_TYPE[0]*/
+	#define IN_FLOW_TBL_NEXT_HOP1
+	#define IN_FLOW_TBL_NEXT_HOP1_OFFSET  32
+	#define IN_FLOW_TBL_NEXT_HOP1_LEN     12
+	#define IN_FLOW_TBL_NEXT_HOP1_DEFAULT 0x0
+	/*[field] L4_PORT2 reuse FWD_TYPE[3]*/
+	#define IN_FLOW_TBL_L4_PORT2
+	#define IN_FLOW_TBL_L4_PORT2_OFFSET  44
+	#define IN_FLOW_TBL_L4_PORT2_LEN     16
+	#define IN_FLOW_TBL_L4_PORT2_DEFAULT 0x0
+	/*[field] PORT_VP_VALID1 reuse FWD_TYPE[2]*/
+	#define IN_FLOW_TBL_PORT_VP_VALID1
+	#define IN_FLOW_TBL_PORT_VP_VALID1_OFFSET  44
+	#define IN_FLOW_TBL_PORT_VP_VALID1_LEN     1
+	#define IN_FLOW_TBL_PORT_VP_VALID1_DEFAULT 0x0
+	/*[field] L4_PORT1 reuse FWD_TYPE[0]*/
+	#define IN_FLOW_TBL_L4_PORT1
+	#define IN_FLOW_TBL_L4_PORT1_OFFSET  44
+	#define IN_FLOW_TBL_L4_PORT1_LEN     16
+	#define IN_FLOW_TBL_L4_PORT1_DEFAULT 0x0
+	/*[field] PORT_VP1 reuse FWD_TYPE[2]*/
+	#define IN_FLOW_TBL_PORT_VP1
+	#define IN_FLOW_TBL_PORT_VP1_OFFSET  45
+	#define IN_FLOW_TBL_PORT_VP1_LEN     8
+	#define IN_FLOW_TBL_PORT_VP1_DEFAULT 0x0
+	/*[field] DE_ACCE*/
+	#define IN_FLOW_TBL_DE_ACCE
+	#define IN_FLOW_TBL_DE_ACCE_OFFSET  60
+	#define IN_FLOW_TBL_DE_ACCE_LEN     1
+	#define IN_FLOW_TBL_DE_ACCE_DEFAULT 0x0
+	/*[field] COPY_TO_CPU_EN*/
+	#define IN_FLOW_TBL_COPY_TO_CPU_EN
+	#define IN_FLOW_TBL_COPY_TO_CPU_EN_OFFSET  61
+	#define IN_FLOW_TBL_COPY_TO_CPU_EN_LEN     1
+	#define IN_FLOW_TBL_COPY_TO_CPU_EN_DEFAULT 0x0
+	/*[field] SYN_TOGGLE*/
+	#define IN_FLOW_TBL_SYN_TOGGLE
+	#define IN_FLOW_TBL_SYN_TOGGLE_OFFSET  62
+	#define IN_FLOW_TBL_SYN_TOGGLE_LEN     1
+	#define IN_FLOW_TBL_SYN_TOGGLE_DEFAULT 0x0
+	/*[field] PRI_PROFILE*/
+	#define IN_FLOW_TBL_PRI_PROFILE
+	#define IN_FLOW_TBL_PRI_PROFILE_OFFSET  63
+	#define IN_FLOW_TBL_PRI_PROFILE_LEN     5
+	#define IN_FLOW_TBL_PRI_PROFILE_DEFAULT 0x0
+	/*[field] SERVICE_CODE*/
+	#define IN_FLOW_TBL_SERVICE_CODE
+	#define IN_FLOW_TBL_SERVICE_CODE_OFFSET  68
+	#define IN_FLOW_TBL_SERVICE_CODE_LEN     8
+	#define IN_FLOW_TBL_SERVICE_CODE_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define IN_FLOW_TBL_IP_ADDR
+	#define IN_FLOW_TBL_IP_ADDR_OFFSET  76
+	#define IN_FLOW_TBL_IP_ADDR_LEN     32
+	#define IN_FLOW_TBL_IP_ADDR_DEFAULT 0x0
+	/*[field] L4_SPORT*/
+	#define IN_FLOW_TBL_L4_SPORT
+	#define IN_FLOW_TBL_L4_SPORT_OFFSET  108
+	#define IN_FLOW_TBL_L4_SPORT_LEN     16
+	#define IN_FLOW_TBL_L4_SPORT_DEFAULT 0x0
+	/*[field] L4_DPORT*/
+	#define IN_FLOW_TBL_L4_DPORT
+	#define IN_FLOW_TBL_L4_DPORT_OFFSET  124
+	#define IN_FLOW_TBL_L4_DPORT_LEN     16
+	#define IN_FLOW_TBL_L4_DPORT_DEFAULT 0x0
+
+struct in_flow_ipv6_3tuple_tbl_3 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  next_hop2:12;
+	a_uint32_t  _reserved0:16;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  _reserved1_0:20;
+	a_uint32_t  _reserved1_1:12;
+	a_uint32_t  ip_protocol:8;
+	a_uint32_t  _reserved2_0:12;
+	a_uint32_t  _reserved2_1:12;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:32;
+	a_uint32_t  ip_addr_2:32;
+	a_uint32_t  ip_addr_3:32;
+	a_uint32_t  ip_addr_4:12;
+	a_uint32_t  _reserved3:20;
+};
+
+struct in_flow_ipv6_3tuple_tbl_1 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  next_hop1:12;
+	a_uint32_t  _reserved0:16;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  _reserved1_0:20;
+	a_uint32_t  _reserved1_1:12;
+	a_uint32_t  ip_protocol:8;
+	a_uint32_t  _reserved2_0:12;
+	a_uint32_t  _reserved2_1:12;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:32;
+	a_uint32_t  ip_addr_2:32;
+	a_uint32_t  ip_addr_3:32;
+	a_uint32_t  ip_addr_4:12;
+	a_uint32_t  _reserved3:20;
+};
+
+struct in_flow_ipv6_3tuple_tbl_0 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  port_vp2:8;
+	a_uint32_t  _reserved0:20;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  _reserved1_0:20;
+	a_uint32_t  _reserved1_1:12;
+	a_uint32_t  ip_protocol:8;
+	a_uint32_t  _reserved2_0:12;
+	a_uint32_t  _reserved2_1:12;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:32;
+	a_uint32_t  ip_addr_2:32;
+	a_uint32_t  ip_addr_3:32;
+	a_uint32_t  ip_addr_4:12;
+	a_uint32_t  _reserved3:20;
+};
+
+struct in_flow_ipv6_3tuple_tbl_2 {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  host_addr_index_type:1;
+	a_uint32_t  host_addr_index:13;
+	a_uint32_t  protocol_type:2;
+	a_uint32_t  age:2;
+	a_uint32_t  src_l3_if_valid:1;
+	a_uint32_t  src_l3_if:8;
+	a_uint32_t  fwd_type:3;
+	a_uint32_t  next_hop3:12;
+	a_uint32_t  port_vp_valid1:1;
+	a_uint32_t  port_vp1:8;
+	a_uint32_t  _reserved0:7;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  copy_to_cpu_en:1;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  pri_profile_0:1;
+	a_uint32_t  pri_profile_1:4;
+	a_uint32_t  service_code:8;
+	a_uint32_t  _reserved1_0:20;
+	a_uint32_t  _reserved1_1:12;
+	a_uint32_t  ip_protocol:8;
+	a_uint32_t  _reserved2_0:12;
+	a_uint32_t  _reserved2_1:12;
+	a_uint32_t  ip_addr_0:20;
+	a_uint32_t  ip_addr_1:32;
+	a_uint32_t  ip_addr_2:32;
+	a_uint32_t  ip_addr_3:32;
+	a_uint32_t  ip_addr_4:12;
+	a_uint32_t  _reserved3:20;
+};
+
+union in_flow_ipv6_3tuple_tbl_u {
+	a_uint32_t val[9];
+	struct in_flow_ipv6_3tuple_tbl_0 bf0;
+	struct in_flow_ipv6_3tuple_tbl_1 bf1;
+	struct in_flow_ipv6_3tuple_tbl_2 bf2;
+	struct in_flow_ipv6_3tuple_tbl_3 bf3;
+};
+
+/*[table] EG_FLOW_TREE_MAP_TBL*/
+#define EG_FLOW_TREE_MAP_TBL
+#define EG_FLOW_TREE_MAP_TBL_ADDRESS 0x8000
+#define EG_FLOW_TREE_MAP_TBL_NUM     4096
+#define EG_FLOW_TREE_MAP_TBL_INC     0x4
+#define EG_FLOW_TREE_MAP_TBL_TYPE    REG_TYPE_RW
+#define EG_FLOW_TREE_MAP_TBL_DEFAULT 0x0
+	/*[field] TREE_ID*/
+	#define EG_FLOW_TREE_MAP_TBL_TREE_ID
+	#define EG_FLOW_TREE_MAP_TBL_TREE_ID_OFFSET  0
+	#define EG_FLOW_TREE_MAP_TBL_TREE_ID_LEN     24
+	#define EG_FLOW_TREE_MAP_TBL_TREE_ID_DEFAULT 0x0
+
+struct eg_flow_tree_map_tbl {
+	a_uint32_t  tree_id:24;
+	a_uint32_t  _reserved0:8;
+};
+
+union eg_flow_tree_map_tbl_u {
+	a_uint32_t val;
+	struct eg_flow_tree_map_tbl bf;
+};
+
+/*[table] IN_FLOW_CNT_TBL*/
+#define IN_FLOW_CNT_TBL
+#define IN_FLOW_CNT_TBL_ADDRESS 0x20000
+#define IN_FLOW_CNT_TBL_NUM     4096
+#define IN_FLOW_CNT_TBL_INC     0x10
+#define IN_FLOW_CNT_TBL_TYPE    REG_TYPE_RW
+#define IN_FLOW_CNT_TBL_DEFAULT 0x0
+	/*[field] HIT_PKT_COUNTER*/
+	#define IN_FLOW_CNT_TBL_HIT_PKT_COUNTER
+	#define IN_FLOW_CNT_TBL_HIT_PKT_COUNTER_OFFSET  0
+	#define IN_FLOW_CNT_TBL_HIT_PKT_COUNTER_LEN     32
+	#define IN_FLOW_CNT_TBL_HIT_PKT_COUNTER_DEFAULT 0x0
+	/*[field] HIT_BYTE_COUNTER*/
+	#define IN_FLOW_CNT_TBL_HIT_BYTE_COUNTER
+	#define IN_FLOW_CNT_TBL_HIT_BYTE_COUNTER_OFFSET  32
+	#define IN_FLOW_CNT_TBL_HIT_BYTE_COUNTER_LEN     40
+	#define IN_FLOW_CNT_TBL_HIT_BYTE_COUNTER_DEFAULT 0x0
+
+struct in_flow_cnt_tbl {
+	a_uint32_t  hit_pkt_counter:32;
+	a_uint32_t  hit_byte_counter_0:32;
+	a_uint32_t  hit_byte_counter_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union in_flow_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct in_flow_cnt_tbl bf;
+};
+
+#endif
\ No newline at end of file
diff --git a/qca-ssdk/include/hsl/hppe/hppe_global.h b/qca-ssdk/include/hsl/hppe/hppe_global.h
new file mode 100755
index 0000000..def29f9
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_global.h
@@ -0,0 +1,1204 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_GLOBAL_H_
+#define _HPPE_GLOBAL_H_
+
+sw_error_t
+hppe_switch_id_get(
+		a_uint32_t dev_id,
+		union switch_id_u *value);
+
+sw_error_t
+hppe_switch_id_set(
+		a_uint32_t dev_id,
+		union switch_id_u *value);
+
+sw_error_t
+hppe_rgmii_ctrl_get(
+		a_uint32_t dev_id,
+		union rgmii_ctrl_u *value);
+
+sw_error_t
+hppe_rgmii_ctrl_set(
+		a_uint32_t dev_id,
+		union rgmii_ctrl_u *value);
+
+sw_error_t
+hppe_clk_gating_ctrl_get(
+		a_uint32_t dev_id,
+		union clk_gating_ctrl_u *value);
+
+sw_error_t
+hppe_clk_gating_ctrl_set(
+		a_uint32_t dev_id,
+		union clk_gating_ctrl_u *value);
+
+sw_error_t
+hppe_port_mux_ctrl_get(
+		a_uint32_t dev_id,
+		union port_mux_ctrl_u *value);
+
+sw_error_t
+hppe_port_mux_ctrl_set(
+		a_uint32_t dev_id,
+		union port_mux_ctrl_u *value);
+
+sw_error_t
+cppe_port_mux_ctrl_get(
+		a_uint32_t dev_id,
+		union cppe_port_mux_ctrl_u *value);
+
+sw_error_t
+cppe_port_mux_ctrl_set(
+		a_uint32_t dev_id,
+		union cppe_port_mux_ctrl_u *value);
+
+sw_error_t
+hppe_module_ini_done_int_get(
+		a_uint32_t dev_id,
+		union module_ini_done_int_u *value);
+
+sw_error_t
+hppe_module_ini_done_int_set(
+		a_uint32_t dev_id,
+		union module_ini_done_int_u *value);
+
+sw_error_t
+hppe_module_cpu_done_int_get(
+		a_uint32_t dev_id,
+		union module_cpu_done_int_u *value);
+
+sw_error_t
+hppe_module_cpu_done_int_set(
+		a_uint32_t dev_id,
+		union module_cpu_done_int_u *value);
+
+sw_error_t
+hppe_port_link_int_get(
+		a_uint32_t dev_id,
+		union port_link_int_u *value);
+
+sw_error_t
+hppe_port_link_int_set(
+		a_uint32_t dev_id,
+		union port_link_int_u *value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		union module_ini_done_int_mask_u *value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		union module_ini_done_int_mask_u *value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_get(
+		a_uint32_t dev_id,
+		union module_cpu_done_int_mask_u *value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_set(
+		a_uint32_t dev_id,
+		union module_cpu_done_int_mask_u *value);
+
+sw_error_t
+hppe_port_link_int_mask_get(
+		a_uint32_t dev_id,
+		union port_link_int_mask_u *value);
+
+sw_error_t
+hppe_port_link_int_mask_set(
+		a_uint32_t dev_id,
+		union port_link_int_mask_u *value);
+
+sw_error_t
+hppe_port_phy_status_0_get(
+		a_uint32_t dev_id,
+		union port_phy_status_0_u *value);
+
+sw_error_t
+hppe_port_phy_status_0_set(
+		a_uint32_t dev_id,
+		union port_phy_status_0_u *value);
+
+sw_error_t
+hppe_port_phy_status_1_get(
+		a_uint32_t dev_id,
+		union port_phy_status_1_u *value);
+
+sw_error_t
+hppe_port_phy_status_1_set(
+		a_uint32_t dev_id,
+		union port_phy_status_1_u *value);
+
+sw_error_t
+hppe_port1_status_get(
+		a_uint32_t dev_id,
+		union port1_status_u *value);
+
+sw_error_t
+hppe_port1_status_set(
+		a_uint32_t dev_id,
+		union port1_status_u *value);
+
+sw_error_t
+hppe_port2_status_get(
+		a_uint32_t dev_id,
+		union port2_status_u *value);
+
+sw_error_t
+hppe_port2_status_set(
+		a_uint32_t dev_id,
+		union port2_status_u *value);
+
+sw_error_t
+hppe_port3_status_get(
+		a_uint32_t dev_id,
+		union port3_status_u *value);
+
+sw_error_t
+hppe_port3_status_set(
+		a_uint32_t dev_id,
+		union port3_status_u *value);
+
+sw_error_t
+hppe_port4_status_get(
+		a_uint32_t dev_id,
+		union port4_status_u *value);
+
+sw_error_t
+hppe_port4_status_set(
+		a_uint32_t dev_id,
+		union port4_status_u *value);
+
+sw_error_t
+hppe_port5_status_get(
+		a_uint32_t dev_id,
+		union port5_status_u *value);
+
+sw_error_t
+hppe_port5_status_set(
+		a_uint32_t dev_id,
+		union port5_status_u *value);
+
+sw_error_t
+hppe_port6_status_get(
+		a_uint32_t dev_id,
+		union port6_status_u *value);
+
+sw_error_t
+hppe_port6_status_set(
+		a_uint32_t dev_id,
+		union port6_status_u *value);
+
+sw_error_t
+hppe_reserved_regs_0_get(
+		a_uint32_t dev_id,
+		union reserved_regs_0_u *value);
+
+sw_error_t
+hppe_reserved_regs_0_set(
+		a_uint32_t dev_id,
+		union reserved_regs_0_u *value);
+
+sw_error_t
+hppe_reserved_regs_1_get(
+		a_uint32_t dev_id,
+		union reserved_regs_1_u *value);
+
+sw_error_t
+hppe_reserved_regs_1_set(
+		a_uint32_t dev_id,
+		union reserved_regs_1_u *value);
+
+sw_error_t
+hppe_reserved_regs_2_get(
+		a_uint32_t dev_id,
+		union reserved_regs_2_u *value);
+
+sw_error_t
+hppe_reserved_regs_2_set(
+		a_uint32_t dev_id,
+		union reserved_regs_2_u *value);
+
+sw_error_t
+hppe_reserved_regs_3_get(
+		a_uint32_t dev_id,
+		union reserved_regs_3_u *value);
+
+sw_error_t
+hppe_reserved_regs_3_set(
+		a_uint32_t dev_id,
+		union reserved_regs_3_u *value);
+
+sw_error_t
+hppe_dbg_data_sel_get(
+		a_uint32_t dev_id,
+		union dbg_data_sel_u *value);
+
+sw_error_t
+hppe_dbg_data_sel_set(
+		a_uint32_t dev_id,
+		union dbg_data_sel_u *value);
+
+sw_error_t
+hppe_switch_id_dev_id_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_switch_id_dev_id_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_switch_id_rev_id_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_switch_id_rev_id_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_rgmii_ctrl_rgmii_ctrl_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_rgmii_ctrl_rgmii_ctrl_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_clk_gating_ctrl_clk_gating_ctrl_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_clk_gating_ctrl_clk_gating_ctrl_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_mux_ctrl_port6_pcs_sel_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_mux_ctrl_port6_pcs_sel_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_mux_ctrl_port5_gmac_sel_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_mux_ctrl_port5_gmac_sel_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_mux_ctrl_port5_pcs_sel_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_mux_ctrl_port5_pcs_sel_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_mux_ctrl_port4_pcs_sel_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_mux_ctrl_port4_pcs_sel_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_mux_ctrl_port6_gmac_sel_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_mux_ctrl_port6_gmac_sel_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_iv_ini_done_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_iv_ini_done_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_qm_ini_done_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_qm_ini_done_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_l3_ini_done_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_l3_ini_done_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_bm_ini_done_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_bm_ini_done_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_ptx_ini_done_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_ptx_ini_done_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_tm_ini_done_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_tm_ini_done_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_l2_ini_done_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_l2_ini_done_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_acl_ini_done_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_acl_ini_done_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_ing_rate_ini_done_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_ing_rate_ini_done_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_wr_cmd_overflow_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_wr_cmd_overflow_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_rd_cmd_overflow_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_rd_cmd_overflow_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_qm_cpu_op_done_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_qm_cpu_op_done_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_rd_cmd_overflow_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_rd_cmd_overflow_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_wr_result_vld_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_wr_result_vld_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_rd_result_vld_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_rd_result_vld_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_wr_cmd_overflow_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_wr_cmd_overflow_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_rd_result_vld_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_rd_result_vld_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_wr_cmd_overflow_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_wr_cmd_overflow_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_rd_cmd_overflow_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_rd_cmd_overflow_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_rd_result_vld_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_rd_result_vld_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_wr_result_vld_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_wr_result_vld_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_wr_result_vld_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_wr_result_vld_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_port6_link_chg_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_port6_link_chg_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_xgmac0_an_done_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_xgmac0_an_done_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_port5_1_link_chg_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_port5_1_link_chg_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_port5_0_link_chg_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_port5_0_link_chg_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_port4_link_chg_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_port4_link_chg_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_port3_link_chg_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_port3_link_chg_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_port2_link_chg_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_port2_link_chg_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_xgmac1_an_done_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_xgmac1_an_done_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_port1_link_chg_int_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_port1_link_chg_int_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_tm_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_tm_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_bm_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_bm_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_iv_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_iv_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_acl_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_acl_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_qm_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_qm_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_l2_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_l2_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_ptx_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_ptx_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_ing_rate_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_ing_rate_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_l3_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_ini_done_int_mask_l3_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_wr_result_vld_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_wr_result_vld_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_wr_result_vld_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_wr_result_vld_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_rd_cmd_overflow_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_rd_cmd_overflow_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_wr_cmd_overflow_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_wr_cmd_overflow_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_rd_result_vld_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_rd_result_vld_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_rd_cmd_overflow_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_rd_cmd_overflow_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_wr_cmd_overflow_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_wr_cmd_overflow_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_wr_cmd_overflow_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_wr_cmd_overflow_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_rd_result_vld_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_rd_result_vld_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_wr_result_vld_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_wr_result_vld_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_qm_cpu_op_done_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_qm_cpu_op_done_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_rd_result_vld_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_rd_result_vld_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_rd_cmd_overflow_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_rd_cmd_overflow_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_mask_xgmac0_an_done_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_mask_xgmac0_an_done_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_mask_port2_link_chg_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_mask_port2_link_chg_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_mask_port4_link_chg_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_mask_port4_link_chg_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_mask_port3_link_chg_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_mask_port3_link_chg_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_mask_port5_1_link_chg_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_mask_port5_1_link_chg_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_mask_xgmac1_an_done_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_mask_xgmac1_an_done_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_mask_port1_link_chg_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_mask_port1_link_chg_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_mask_port5_0_link_chg_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_mask_port5_0_link_chg_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_link_int_mask_port6_link_chg_int_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_link_int_mask_port6_link_chg_int_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_phy_status_0_port3_phy_status_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_phy_status_0_port3_phy_status_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_phy_status_0_port4_phy_status_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_phy_status_0_port4_phy_status_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_phy_status_0_port2_phy_status_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_phy_status_0_port2_phy_status_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_phy_status_0_port1_phy_status_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_phy_status_0_port1_phy_status_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_phy_status_1_port6_phy_status_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_phy_status_1_port6_phy_status_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_phy_status_1_port5_0_phy_status_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_phy_status_1_port5_0_phy_status_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_phy_status_1_port5_1_phy_status_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_phy_status_1_port5_1_phy_status_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port1_status_port1_status_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port1_status_port1_status_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port2_status_port2_status_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port2_status_port2_status_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port3_status_port3_status_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port3_status_port3_status_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port4_status_port4_status_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port4_status_port4_status_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port5_status_port3_mac_speed_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port5_status_port3_mac_speed_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port5_status_port2_mac_speed_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port5_status_port2_mac_speed_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port5_status_port1_mac_speed_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port5_status_port1_mac_speed_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port5_status_port5_status_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port5_status_port5_status_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port5_status_port4_mac_speed_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port5_status_port4_mac_speed_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port6_status_port6_status_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port6_status_port6_status_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_reserved_regs_0_spare_regs_0_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_reserved_regs_0_spare_regs_0_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_reserved_regs_1_spare_regs_1_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_reserved_regs_1_spare_regs_1_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_reserved_regs_2_spare_regs_2_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_reserved_regs_2_spare_regs_2_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_reserved_regs_3_spare_regs_3_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_reserved_regs_3_spare_regs_3_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_dbg_data_sel_dbg_data_sel_desp_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_dbg_data_sel_dbg_data_sel_desp_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_dbg_data_sel_dbg_data_sel_switch_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_dbg_data_sel_dbg_data_sel_switch_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_global_reg.h b/qca-ssdk/include/hsl/hppe/hppe_global_reg.h
new file mode 100755
index 0000000..904f4f1
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_global_reg.h
@@ -0,0 +1,988 @@
+/*
+ * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_GLOBAL_REG_H
+#define HPPE_GLOBAL_REG_H
+
+/*[register] SWITCH_ID*/
+#define SWITCH_ID
+#define SWITCH_ID_ADDRESS 0x0
+#define SWITCH_ID_NUM     1
+#define SWITCH_ID_INC     0x4
+#define SWITCH_ID_TYPE    REG_TYPE_RW
+#define SWITCH_ID_DEFAULT 0x1500
+	/*[field] REV_ID*/
+	#define SWITCH_ID_REV_ID
+	#define SWITCH_ID_REV_ID_OFFSET  0
+	#define SWITCH_ID_REV_ID_LEN     8
+	#define SWITCH_ID_REV_ID_DEFAULT 0x0
+	/*[field] DEV_ID*/
+	#define SWITCH_ID_DEV_ID
+	#define SWITCH_ID_DEV_ID_OFFSET  8
+	#define SWITCH_ID_DEV_ID_LEN     8
+	#define SWITCH_ID_DEV_ID_DEFAULT 0x15
+
+struct switch_id {
+	a_uint32_t  rev_id:8;
+	a_uint32_t  dev_id:8;
+	a_uint32_t  _reserved0:16;
+};
+
+union switch_id_u {
+	a_uint32_t val;
+	struct switch_id bf;
+};
+
+/*[register] RGMII_CTRL*/
+#define RGMII_CTRL
+#define RGMII_CTRL_ADDRESS 0x4
+#define RGMII_CTRL_NUM     1
+#define RGMII_CTRL_INC     0x4
+#define RGMII_CTRL_TYPE    REG_TYPE_RW
+#define RGMII_CTRL_DEFAULT 0x0
+	/*[field] RGMII_CTRL*/
+	#define RGMII_CTRL_RGMII_CTRL
+	#define RGMII_CTRL_RGMII_CTRL_OFFSET  0
+	#define RGMII_CTRL_RGMII_CTRL_LEN     32
+	#define RGMII_CTRL_RGMII_CTRL_DEFAULT 0x0
+
+struct rgmii_ctrl {
+	a_uint32_t  rgmii_ctrl:32;
+};
+
+union rgmii_ctrl_u {
+	a_uint32_t val;
+	struct rgmii_ctrl bf;
+};
+
+/*[register] CLK_GATING_CTRL*/
+#define CLK_GATING_CTRL
+#define CLK_GATING_CTRL_ADDRESS 0x8
+#define CLK_GATING_CTRL_NUM     1
+#define CLK_GATING_CTRL_INC     0x4
+#define CLK_GATING_CTRL_TYPE    REG_TYPE_RW
+#define CLK_GATING_CTRL_DEFAULT 0xffffffff
+	/*[field] CLK_GATING_CTRL*/
+	#define CLK_GATING_CTRL_CLK_GATING_CTRL
+	#define CLK_GATING_CTRL_CLK_GATING_CTRL_OFFSET  0
+	#define CLK_GATING_CTRL_CLK_GATING_CTRL_LEN     32
+	#define CLK_GATING_CTRL_CLK_GATING_CTRL_DEFAULT 0xffffffff
+
+struct clk_gating_ctrl {
+	a_uint32_t  clk_gating_ctrl:32;
+};
+
+union clk_gating_ctrl_u {
+	a_uint32_t val;
+	struct clk_gating_ctrl bf;
+};
+
+/*[register] PORT_MUX_CTRL*/
+#define PORT_MUX_CTRL
+#define PORT_MUX_CTRL_ADDRESS 0x10
+#define PORT_MUX_CTRL_NUM     1
+#define PORT_MUX_CTRL_INC     0x4
+#define PORT_MUX_CTRL_TYPE    REG_TYPE_RW
+#define PORT_MUX_CTRL_DEFAULT 0x0
+	/*[field] PORT4_PCS_SEL*/
+	#define PORT_MUX_CTRL_PORT4_PCS_SEL
+	#define PORT_MUX_CTRL_PORT4_PCS_SEL_OFFSET  0
+	#define PORT_MUX_CTRL_PORT4_PCS_SEL_LEN     1
+	#define PORT_MUX_CTRL_PORT4_PCS_SEL_DEFAULT 0x0
+	/*[field] PORT5_PCS_SEL*/
+	#define PORT_MUX_CTRL_PORT5_PCS_SEL
+	#define PORT_MUX_CTRL_PORT5_PCS_SEL_OFFSET  1
+	#define PORT_MUX_CTRL_PORT5_PCS_SEL_LEN     2
+	#define PORT_MUX_CTRL_PORT5_PCS_SEL_DEFAULT 0x0
+	/*[field] PORT5_GMAC_SEL*/
+	#define PORT_MUX_CTRL_PORT5_GMAC_SEL
+	#define PORT_MUX_CTRL_PORT5_GMAC_SEL_OFFSET  3
+	#define PORT_MUX_CTRL_PORT5_GMAC_SEL_LEN     1
+	#define PORT_MUX_CTRL_PORT5_GMAC_SEL_DEFAULT 0x0
+	/*[field] PORT6_PCS_SEL*/
+	#define PORT_MUX_CTRL_PORT6_PCS_SEL
+	#define PORT_MUX_CTRL_PORT6_PCS_SEL_OFFSET  4
+	#define PORT_MUX_CTRL_PORT6_PCS_SEL_LEN     1
+	#define PORT_MUX_CTRL_PORT6_PCS_SEL_DEFAULT 0x0
+	/*[field] PORT6_GMAC_SEL*/
+	#define PORT_MUX_CTRL_PORT6_GMAC_SEL
+	#define PORT_MUX_CTRL_PORT6_GMAC_SEL_OFFSET  5
+	#define PORT_MUX_CTRL_PORT6_GMAC_SEL_LEN     1
+	#define PORT_MUX_CTRL_PORT6_GMAC_SEL_DEFAULT 0x0
+
+struct port_mux_ctrl {
+	a_uint32_t  port4_pcs_sel:1;
+	a_uint32_t  port5_pcs_sel:2;
+	a_uint32_t  port5_gmac_sel:1;
+	a_uint32_t  port6_pcs_sel:1;
+	a_uint32_t  port6_gmac_sel:1;
+	a_uint32_t  _reserved0:26;
+};
+
+union port_mux_ctrl_u {
+	a_uint32_t val;
+	struct port_mux_ctrl bf;
+};
+struct cppe_port_mux_ctrl {
+	a_uint32_t  port3_pcs_sel:2;
+	a_uint32_t  port4_pcs_sel:2;
+	a_uint32_t  port5_pcs_sel:2;
+	a_uint32_t  port5_gmac_sel:1;
+	a_uint32_t  pcs0_ch4_sel:1;
+	a_uint32_t  pcs0_ch0_sel:1;
+	a_uint32_t  _reserved0:23;
+};
+
+union cppe_port_mux_ctrl_u {
+	a_uint32_t val;
+	struct cppe_port_mux_ctrl bf;
+};
+
+/*[register] MODULE_INI_DONE_INT*/
+#define MODULE_INI_DONE_INT
+#define MODULE_INI_DONE_INT_ADDRESS 0x20
+#define MODULE_INI_DONE_INT_NUM     1
+#define MODULE_INI_DONE_INT_INC     0x4
+#define MODULE_INI_DONE_INT_TYPE    REG_TYPE_RW
+#define MODULE_INI_DONE_INT_DEFAULT 0x0
+	/*[field] L3_INI_DONE_INT*/
+	#define MODULE_INI_DONE_INT_L3_INI_DONE_INT
+	#define MODULE_INI_DONE_INT_L3_INI_DONE_INT_OFFSET  0
+	#define MODULE_INI_DONE_INT_L3_INI_DONE_INT_LEN     1
+	#define MODULE_INI_DONE_INT_L3_INI_DONE_INT_DEFAULT 0x0
+	/*[field] ACL_INI_DONE_INT*/
+	#define MODULE_INI_DONE_INT_ACL_INI_DONE_INT
+	#define MODULE_INI_DONE_INT_ACL_INI_DONE_INT_OFFSET  1
+	#define MODULE_INI_DONE_INT_ACL_INI_DONE_INT_LEN     1
+	#define MODULE_INI_DONE_INT_ACL_INI_DONE_INT_DEFAULT 0x0
+	/*[field] L2_INI_DONE_INT*/
+	#define MODULE_INI_DONE_INT_L2_INI_DONE_INT
+	#define MODULE_INI_DONE_INT_L2_INI_DONE_INT_OFFSET  2
+	#define MODULE_INI_DONE_INT_L2_INI_DONE_INT_LEN     1
+	#define MODULE_INI_DONE_INT_L2_INI_DONE_INT_DEFAULT 0x0
+	/*[field] ING_RATE_INI_DONE_INT*/
+	#define MODULE_INI_DONE_INT_ING_RATE_INI_DONE_INT
+	#define MODULE_INI_DONE_INT_ING_RATE_INI_DONE_INT_OFFSET  3
+	#define MODULE_INI_DONE_INT_ING_RATE_INI_DONE_INT_LEN     1
+	#define MODULE_INI_DONE_INT_ING_RATE_INI_DONE_INT_DEFAULT 0x0
+	/*[field] BM_INI_DONE_INT*/
+	#define MODULE_INI_DONE_INT_BM_INI_DONE_INT
+	#define MODULE_INI_DONE_INT_BM_INI_DONE_INT_OFFSET  4
+	#define MODULE_INI_DONE_INT_BM_INI_DONE_INT_LEN     1
+	#define MODULE_INI_DONE_INT_BM_INI_DONE_INT_DEFAULT 0x0
+	/*[field] TM_INI_DONE_INT*/
+	#define MODULE_INI_DONE_INT_TM_INI_DONE_INT
+	#define MODULE_INI_DONE_INT_TM_INI_DONE_INT_OFFSET  5
+	#define MODULE_INI_DONE_INT_TM_INI_DONE_INT_LEN     1
+	#define MODULE_INI_DONE_INT_TM_INI_DONE_INT_DEFAULT 0x0
+	/*[field] QM_INI_DONE_INT*/
+	#define MODULE_INI_DONE_INT_QM_INI_DONE_INT
+	#define MODULE_INI_DONE_INT_QM_INI_DONE_INT_OFFSET  6
+	#define MODULE_INI_DONE_INT_QM_INI_DONE_INT_LEN     1
+	#define MODULE_INI_DONE_INT_QM_INI_DONE_INT_DEFAULT 0x0
+	/*[field] IV_INI_DONE_INT*/
+	#define MODULE_INI_DONE_INT_IV_INI_DONE_INT
+	#define MODULE_INI_DONE_INT_IV_INI_DONE_INT_OFFSET  7
+	#define MODULE_INI_DONE_INT_IV_INI_DONE_INT_LEN     1
+	#define MODULE_INI_DONE_INT_IV_INI_DONE_INT_DEFAULT 0x0
+	/*[field] PTX_INI_DONE_INT*/
+	#define MODULE_INI_DONE_INT_PTX_INI_DONE_INT
+	#define MODULE_INI_DONE_INT_PTX_INI_DONE_INT_OFFSET  8
+	#define MODULE_INI_DONE_INT_PTX_INI_DONE_INT_LEN     1
+	#define MODULE_INI_DONE_INT_PTX_INI_DONE_INT_DEFAULT 0x0
+
+struct module_ini_done_int {
+	a_uint32_t  l3_ini_done_int:1;
+	a_uint32_t  acl_ini_done_int:1;
+	a_uint32_t  l2_ini_done_int:1;
+	a_uint32_t  ing_rate_ini_done_int:1;
+	a_uint32_t  bm_ini_done_int:1;
+	a_uint32_t  tm_ini_done_int:1;
+	a_uint32_t  qm_ini_done_int:1;
+	a_uint32_t  iv_ini_done_int:1;
+	a_uint32_t  ptx_ini_done_int:1;
+	a_uint32_t  _reserved0:23;
+};
+
+union module_ini_done_int_u {
+	a_uint32_t val;
+	struct module_ini_done_int bf;
+};
+
+/*[register] MODULE_CPU_DONE_INT*/
+#define MODULE_CPU_DONE_INT
+#define MODULE_CPU_DONE_INT_ADDRESS 0x24
+#define MODULE_CPU_DONE_INT_NUM     1
+#define MODULE_CPU_DONE_INT_INC     0x4
+#define MODULE_CPU_DONE_INT_TYPE    REG_TYPE_RW
+#define MODULE_CPU_DONE_INT_DEFAULT 0x0
+	/*[field] QM_CPU_OP_DONE_INT*/
+	#define MODULE_CPU_DONE_INT_QM_CPU_OP_DONE_INT
+	#define MODULE_CPU_DONE_INT_QM_CPU_OP_DONE_INT_OFFSET  0
+	#define MODULE_CPU_DONE_INT_QM_CPU_OP_DONE_INT_LEN     1
+	#define MODULE_CPU_DONE_INT_QM_CPU_OP_DONE_INT_DEFAULT 0x0
+	/*[field] L2_FDB_RD_RESULT_VLD_INT*/
+	#define MODULE_CPU_DONE_INT_L2_FDB_RD_RESULT_VLD_INT
+	#define MODULE_CPU_DONE_INT_L2_FDB_RD_RESULT_VLD_INT_OFFSET  1
+	#define MODULE_CPU_DONE_INT_L2_FDB_RD_RESULT_VLD_INT_LEN     1
+	#define MODULE_CPU_DONE_INT_L2_FDB_RD_RESULT_VLD_INT_DEFAULT 0x0
+	/*[field] L2_FDB_WR_RESULT_VLD_INT*/
+	#define MODULE_CPU_DONE_INT_L2_FDB_WR_RESULT_VLD_INT
+	#define MODULE_CPU_DONE_INT_L2_FDB_WR_RESULT_VLD_INT_OFFSET  2
+	#define MODULE_CPU_DONE_INT_L2_FDB_WR_RESULT_VLD_INT_LEN     1
+	#define MODULE_CPU_DONE_INT_L2_FDB_WR_RESULT_VLD_INT_DEFAULT 0x0
+	/*[field] L2_FDB_RD_CMD_OVERFLOW_INT*/
+	#define MODULE_CPU_DONE_INT_L2_FDB_RD_CMD_OVERFLOW_INT
+	#define MODULE_CPU_DONE_INT_L2_FDB_RD_CMD_OVERFLOW_INT_OFFSET  3
+	#define MODULE_CPU_DONE_INT_L2_FDB_RD_CMD_OVERFLOW_INT_LEN     1
+	#define MODULE_CPU_DONE_INT_L2_FDB_RD_CMD_OVERFLOW_INT_DEFAULT 0x0
+	/*[field] L2_FDB_WR_CMD_OVERFLOW_INT*/
+	#define MODULE_CPU_DONE_INT_L2_FDB_WR_CMD_OVERFLOW_INT
+	#define MODULE_CPU_DONE_INT_L2_FDB_WR_CMD_OVERFLOW_INT_OFFSET  4
+	#define MODULE_CPU_DONE_INT_L2_FDB_WR_CMD_OVERFLOW_INT_LEN     1
+	#define MODULE_CPU_DONE_INT_L2_FDB_WR_CMD_OVERFLOW_INT_DEFAULT 0x0
+	/*[field] L3_HOST_WR_CMD_OVERFLOW_INT*/
+	#define MODULE_CPU_DONE_INT_L3_HOST_WR_CMD_OVERFLOW_INT
+	#define MODULE_CPU_DONE_INT_L3_HOST_WR_CMD_OVERFLOW_INT_OFFSET  8
+	#define MODULE_CPU_DONE_INT_L3_HOST_WR_CMD_OVERFLOW_INT_LEN     1
+	#define MODULE_CPU_DONE_INT_L3_HOST_WR_CMD_OVERFLOW_INT_DEFAULT 0x0
+	/*[field] L3_HOST_RD_CMD_OVERFLOW_INT*/
+	#define MODULE_CPU_DONE_INT_L3_HOST_RD_CMD_OVERFLOW_INT
+	#define MODULE_CPU_DONE_INT_L3_HOST_RD_CMD_OVERFLOW_INT_OFFSET  9
+	#define MODULE_CPU_DONE_INT_L3_HOST_RD_CMD_OVERFLOW_INT_LEN     1
+	#define MODULE_CPU_DONE_INT_L3_HOST_RD_CMD_OVERFLOW_INT_DEFAULT 0x0
+	/*[field] L3_HOST_WR_RESULT_VLD_INT*/
+	#define MODULE_CPU_DONE_INT_L3_HOST_WR_RESULT_VLD_INT
+	#define MODULE_CPU_DONE_INT_L3_HOST_WR_RESULT_VLD_INT_OFFSET  10
+	#define MODULE_CPU_DONE_INT_L3_HOST_WR_RESULT_VLD_INT_LEN     1
+	#define MODULE_CPU_DONE_INT_L3_HOST_WR_RESULT_VLD_INT_DEFAULT 0x0
+	/*[field] L3_HOST_RD_RESULT_VLD_INT*/
+	#define MODULE_CPU_DONE_INT_L3_HOST_RD_RESULT_VLD_INT
+	#define MODULE_CPU_DONE_INT_L3_HOST_RD_RESULT_VLD_INT_OFFSET  11
+	#define MODULE_CPU_DONE_INT_L3_HOST_RD_RESULT_VLD_INT_LEN     1
+	#define MODULE_CPU_DONE_INT_L3_HOST_RD_RESULT_VLD_INT_DEFAULT 0x0
+	/*[field] L3_FLOW_WR_CMD_OVERFLOW_INT*/
+	#define MODULE_CPU_DONE_INT_L3_FLOW_WR_CMD_OVERFLOW_INT
+	#define MODULE_CPU_DONE_INT_L3_FLOW_WR_CMD_OVERFLOW_INT_OFFSET  12
+	#define MODULE_CPU_DONE_INT_L3_FLOW_WR_CMD_OVERFLOW_INT_LEN     1
+	#define MODULE_CPU_DONE_INT_L3_FLOW_WR_CMD_OVERFLOW_INT_DEFAULT 0x0
+	/*[field] L3_FLOW_RD_CMD_OVERFLOW_INT*/
+	#define MODULE_CPU_DONE_INT_L3_FLOW_RD_CMD_OVERFLOW_INT
+	#define MODULE_CPU_DONE_INT_L3_FLOW_RD_CMD_OVERFLOW_INT_OFFSET  13
+	#define MODULE_CPU_DONE_INT_L3_FLOW_RD_CMD_OVERFLOW_INT_LEN     1
+	#define MODULE_CPU_DONE_INT_L3_FLOW_RD_CMD_OVERFLOW_INT_DEFAULT 0x0
+	/*[field] L3_FLOW_WR_RESULT_VLD_INT*/
+	#define MODULE_CPU_DONE_INT_L3_FLOW_WR_RESULT_VLD_INT
+	#define MODULE_CPU_DONE_INT_L3_FLOW_WR_RESULT_VLD_INT_OFFSET  14
+	#define MODULE_CPU_DONE_INT_L3_FLOW_WR_RESULT_VLD_INT_LEN     1
+	#define MODULE_CPU_DONE_INT_L3_FLOW_WR_RESULT_VLD_INT_DEFAULT 0x0
+	/*[field] L3_FLOW_RD_RESULT_VLD_INT*/
+	#define MODULE_CPU_DONE_INT_L3_FLOW_RD_RESULT_VLD_INT
+	#define MODULE_CPU_DONE_INT_L3_FLOW_RD_RESULT_VLD_INT_OFFSET  15
+	#define MODULE_CPU_DONE_INT_L3_FLOW_RD_RESULT_VLD_INT_LEN     1
+	#define MODULE_CPU_DONE_INT_L3_FLOW_RD_RESULT_VLD_INT_DEFAULT 0x0
+
+struct module_cpu_done_int {
+	a_uint32_t  qm_cpu_op_done_int:1;
+	a_uint32_t  l2_fdb_rd_result_vld_int:1;
+	a_uint32_t  l2_fdb_wr_result_vld_int:1;
+	a_uint32_t  l2_fdb_rd_cmd_overflow_int:1;
+	a_uint32_t  l2_fdb_wr_cmd_overflow_int:1;
+	a_uint32_t  _reserved0:3;
+	a_uint32_t  l3_host_wr_cmd_overflow_int:1;
+	a_uint32_t  l3_host_rd_cmd_overflow_int:1;
+	a_uint32_t  l3_host_wr_result_vld_int:1;
+	a_uint32_t  l3_host_rd_result_vld_int:1;
+	a_uint32_t  l3_flow_wr_cmd_overflow_int:1;
+	a_uint32_t  l3_flow_rd_cmd_overflow_int:1;
+	a_uint32_t  l3_flow_wr_result_vld_int:1;
+	a_uint32_t  l3_flow_rd_result_vld_int:1;
+	a_uint32_t  _reserved1:16;
+};
+
+union module_cpu_done_int_u {
+	a_uint32_t val;
+	struct module_cpu_done_int bf;
+};
+
+/*[register] PORT_LINK_INT*/
+#define PORT_LINK_INT
+#define PORT_LINK_INT_ADDRESS 0x28
+#define PORT_LINK_INT_NUM     1
+#define PORT_LINK_INT_INC     0x4
+#define PORT_LINK_INT_TYPE    REG_TYPE_RW
+#define PORT_LINK_INT_DEFAULT 0x0
+	/*[field] PORT1_LINK_CHG_INT*/
+	#define PORT_LINK_INT_PORT1_LINK_CHG_INT
+	#define PORT_LINK_INT_PORT1_LINK_CHG_INT_OFFSET  0
+	#define PORT_LINK_INT_PORT1_LINK_CHG_INT_LEN     1
+	#define PORT_LINK_INT_PORT1_LINK_CHG_INT_DEFAULT 0x0
+	/*[field] PORT2_LINK_CHG_INT*/
+	#define PORT_LINK_INT_PORT2_LINK_CHG_INT
+	#define PORT_LINK_INT_PORT2_LINK_CHG_INT_OFFSET  1
+	#define PORT_LINK_INT_PORT2_LINK_CHG_INT_LEN     1
+	#define PORT_LINK_INT_PORT2_LINK_CHG_INT_DEFAULT 0x0
+	/*[field] PORT3_LINK_CHG_INT*/
+	#define PORT_LINK_INT_PORT3_LINK_CHG_INT
+	#define PORT_LINK_INT_PORT3_LINK_CHG_INT_OFFSET  2
+	#define PORT_LINK_INT_PORT3_LINK_CHG_INT_LEN     1
+	#define PORT_LINK_INT_PORT3_LINK_CHG_INT_DEFAULT 0x0
+	/*[field] PORT4_LINK_CHG_INT*/
+	#define PORT_LINK_INT_PORT4_LINK_CHG_INT
+	#define PORT_LINK_INT_PORT4_LINK_CHG_INT_OFFSET  3
+	#define PORT_LINK_INT_PORT4_LINK_CHG_INT_LEN     1
+	#define PORT_LINK_INT_PORT4_LINK_CHG_INT_DEFAULT 0x0
+	/*[field] PORT5_0_LINK_CHG_INT*/
+	#define PORT_LINK_INT_PORT5_0_LINK_CHG_INT
+	#define PORT_LINK_INT_PORT5_0_LINK_CHG_INT_OFFSET  4
+	#define PORT_LINK_INT_PORT5_0_LINK_CHG_INT_LEN     1
+	#define PORT_LINK_INT_PORT5_0_LINK_CHG_INT_DEFAULT 0x0
+	/*[field] PORT5_1_LINK_CHG_INT*/
+	#define PORT_LINK_INT_PORT5_1_LINK_CHG_INT
+	#define PORT_LINK_INT_PORT5_1_LINK_CHG_INT_OFFSET  5
+	#define PORT_LINK_INT_PORT5_1_LINK_CHG_INT_LEN     1
+	#define PORT_LINK_INT_PORT5_1_LINK_CHG_INT_DEFAULT 0x0
+	/*[field] PORT6_LINK_CHG_INT*/
+	#define PORT_LINK_INT_PORT6_LINK_CHG_INT
+	#define PORT_LINK_INT_PORT6_LINK_CHG_INT_OFFSET  6
+	#define PORT_LINK_INT_PORT6_LINK_CHG_INT_LEN     1
+	#define PORT_LINK_INT_PORT6_LINK_CHG_INT_DEFAULT 0x0
+	/*[field] XGMAC0_AN_DONE_INT*/
+	#define PORT_LINK_INT_XGMAC0_AN_DONE_INT
+	#define PORT_LINK_INT_XGMAC0_AN_DONE_INT_OFFSET  8
+	#define PORT_LINK_INT_XGMAC0_AN_DONE_INT_LEN     1
+	#define PORT_LINK_INT_XGMAC0_AN_DONE_INT_DEFAULT 0x0
+	/*[field] XGMAC1_AN_DONE_INT*/
+	#define PORT_LINK_INT_XGMAC1_AN_DONE_INT
+	#define PORT_LINK_INT_XGMAC1_AN_DONE_INT_OFFSET  9
+	#define PORT_LINK_INT_XGMAC1_AN_DONE_INT_LEN     1
+	#define PORT_LINK_INT_XGMAC1_AN_DONE_INT_DEFAULT 0x0
+
+struct port_link_int {
+	a_uint32_t  port1_link_chg_int:1;
+	a_uint32_t  port2_link_chg_int:1;
+	a_uint32_t  port3_link_chg_int:1;
+	a_uint32_t  port4_link_chg_int:1;
+	a_uint32_t  port5_0_link_chg_int:1;
+	a_uint32_t  port5_1_link_chg_int:1;
+	a_uint32_t  port6_link_chg_int:1;
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  xgmac0_an_done_int:1;
+	a_uint32_t  xgmac1_an_done_int:1;
+	a_uint32_t  _reserved1:22;
+};
+
+union port_link_int_u {
+	a_uint32_t val;
+	struct port_link_int bf;
+};
+
+/*[register] MODULE_INI_DONE_INT_MASK*/
+#define MODULE_INI_DONE_INT_MASK
+#define MODULE_INI_DONE_INT_MASK_ADDRESS 0x30
+#define MODULE_INI_DONE_INT_MASK_NUM     1
+#define MODULE_INI_DONE_INT_MASK_INC     0x4
+#define MODULE_INI_DONE_INT_MASK_TYPE    REG_TYPE_RW
+#define MODULE_INI_DONE_INT_MASK_DEFAULT 0x1ff
+	/*[field] L3_INI_DONE_INT_MASK*/
+	#define MODULE_INI_DONE_INT_MASK_L3_INI_DONE_INT_MASK
+	#define MODULE_INI_DONE_INT_MASK_L3_INI_DONE_INT_MASK_OFFSET  0
+	#define MODULE_INI_DONE_INT_MASK_L3_INI_DONE_INT_MASK_LEN     1
+	#define MODULE_INI_DONE_INT_MASK_L3_INI_DONE_INT_MASK_DEFAULT 0x1
+	/*[field] ACL_INI_DONE_INT_MASK*/
+	#define MODULE_INI_DONE_INT_MASK_ACL_INI_DONE_INT_MASK
+	#define MODULE_INI_DONE_INT_MASK_ACL_INI_DONE_INT_MASK_OFFSET  1
+	#define MODULE_INI_DONE_INT_MASK_ACL_INI_DONE_INT_MASK_LEN     1
+	#define MODULE_INI_DONE_INT_MASK_ACL_INI_DONE_INT_MASK_DEFAULT 0x1
+	/*[field] L2_INI_DONE_INT_MASK*/
+	#define MODULE_INI_DONE_INT_MASK_L2_INI_DONE_INT_MASK
+	#define MODULE_INI_DONE_INT_MASK_L2_INI_DONE_INT_MASK_OFFSET  2
+	#define MODULE_INI_DONE_INT_MASK_L2_INI_DONE_INT_MASK_LEN     1
+	#define MODULE_INI_DONE_INT_MASK_L2_INI_DONE_INT_MASK_DEFAULT 0x1
+	/*[field] ING_RATE_INI_DONE_INT_MASK*/
+	#define MODULE_INI_DONE_INT_MASK_ING_RATE_INI_DONE_INT_MASK
+	#define MODULE_INI_DONE_INT_MASK_ING_RATE_INI_DONE_INT_MASK_OFFSET  3
+	#define MODULE_INI_DONE_INT_MASK_ING_RATE_INI_DONE_INT_MASK_LEN     1
+	#define MODULE_INI_DONE_INT_MASK_ING_RATE_INI_DONE_INT_MASK_DEFAULT 0x1
+	/*[field] BM_INI_DONE_INT_MASK*/
+	#define MODULE_INI_DONE_INT_MASK_BM_INI_DONE_INT_MASK
+	#define MODULE_INI_DONE_INT_MASK_BM_INI_DONE_INT_MASK_OFFSET  4
+	#define MODULE_INI_DONE_INT_MASK_BM_INI_DONE_INT_MASK_LEN     1
+	#define MODULE_INI_DONE_INT_MASK_BM_INI_DONE_INT_MASK_DEFAULT 0x1
+	/*[field] TM_INI_DONE_INT_MASK*/
+	#define MODULE_INI_DONE_INT_MASK_TM_INI_DONE_INT_MASK
+	#define MODULE_INI_DONE_INT_MASK_TM_INI_DONE_INT_MASK_OFFSET  5
+	#define MODULE_INI_DONE_INT_MASK_TM_INI_DONE_INT_MASK_LEN     1
+	#define MODULE_INI_DONE_INT_MASK_TM_INI_DONE_INT_MASK_DEFAULT 0x1
+	/*[field] QM_INI_DONE_INT_MASK*/
+	#define MODULE_INI_DONE_INT_MASK_QM_INI_DONE_INT_MASK
+	#define MODULE_INI_DONE_INT_MASK_QM_INI_DONE_INT_MASK_OFFSET  6
+	#define MODULE_INI_DONE_INT_MASK_QM_INI_DONE_INT_MASK_LEN     1
+	#define MODULE_INI_DONE_INT_MASK_QM_INI_DONE_INT_MASK_DEFAULT 0x1
+	/*[field] IV_INI_DONE_INT_MASK*/
+	#define MODULE_INI_DONE_INT_MASK_IV_INI_DONE_INT_MASK
+	#define MODULE_INI_DONE_INT_MASK_IV_INI_DONE_INT_MASK_OFFSET  7
+	#define MODULE_INI_DONE_INT_MASK_IV_INI_DONE_INT_MASK_LEN     1
+	#define MODULE_INI_DONE_INT_MASK_IV_INI_DONE_INT_MASK_DEFAULT 0x1
+	/*[field] PTX_INI_DONE_INT_MASK*/
+	#define MODULE_INI_DONE_INT_MASK_PTX_INI_DONE_INT_MASK
+	#define MODULE_INI_DONE_INT_MASK_PTX_INI_DONE_INT_MASK_OFFSET  8
+	#define MODULE_INI_DONE_INT_MASK_PTX_INI_DONE_INT_MASK_LEN     1
+	#define MODULE_INI_DONE_INT_MASK_PTX_INI_DONE_INT_MASK_DEFAULT 0x1
+
+struct module_ini_done_int_mask {
+	a_uint32_t  l3_ini_done_int_mask:1;
+	a_uint32_t  acl_ini_done_int_mask:1;
+	a_uint32_t  l2_ini_done_int_mask:1;
+	a_uint32_t  ing_rate_ini_done_int_mask:1;
+	a_uint32_t  bm_ini_done_int_mask:1;
+	a_uint32_t  tm_ini_done_int_mask:1;
+	a_uint32_t  qm_ini_done_int_mask:1;
+	a_uint32_t  iv_ini_done_int_mask:1;
+	a_uint32_t  ptx_ini_done_int_mask:1;
+	a_uint32_t  _reserved0:23;
+};
+
+union module_ini_done_int_mask_u {
+	a_uint32_t val;
+	struct module_ini_done_int_mask bf;
+};
+
+/*[register] MODULE_CPU_DONE_INT_MASK*/
+#define MODULE_CPU_DONE_INT_MASK
+#define MODULE_CPU_DONE_INT_MASK_ADDRESS 0x34
+#define MODULE_CPU_DONE_INT_MASK_NUM     1
+#define MODULE_CPU_DONE_INT_MASK_INC     0x4
+#define MODULE_CPU_DONE_INT_MASK_TYPE    REG_TYPE_RW
+#define MODULE_CPU_DONE_INT_MASK_DEFAULT 0xff1f
+	/*[field] QM_CPU_OP_DONE_INT_MASK*/
+	#define MODULE_CPU_DONE_INT_MASK_QM_CPU_OP_DONE_INT_MASK
+	#define MODULE_CPU_DONE_INT_MASK_QM_CPU_OP_DONE_INT_MASK_OFFSET  0
+	#define MODULE_CPU_DONE_INT_MASK_QM_CPU_OP_DONE_INT_MASK_LEN     1
+	#define MODULE_CPU_DONE_INT_MASK_QM_CPU_OP_DONE_INT_MASK_DEFAULT 0x1
+	/*[field] L2_FDB_RD_RESULT_VLD_INT_MASK*/
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_RESULT_VLD_INT_MASK
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_RESULT_VLD_INT_MASK_OFFSET  1
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_RESULT_VLD_INT_MASK_LEN     1
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_RESULT_VLD_INT_MASK_DEFAULT 0x1
+	/*[field] L2_FDB_WR_RESULT_VLD_INT_MASK*/
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_RESULT_VLD_INT_MASK
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_RESULT_VLD_INT_MASK_OFFSET  2
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_RESULT_VLD_INT_MASK_LEN     1
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_RESULT_VLD_INT_MASK_DEFAULT 0x1
+	/*[field] L2_FDB_RD_CMD_OVERFLOW_INT_MASK*/
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_CMD_OVERFLOW_INT_MASK
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_CMD_OVERFLOW_INT_MASK_OFFSET  3
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_CMD_OVERFLOW_INT_MASK_LEN     1
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_CMD_OVERFLOW_INT_MASK_DEFAULT 0x1
+	/*[field] L2_FDB_WR_CMD_OVERFLOW_INT_MASK*/
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_CMD_OVERFLOW_INT_MASK
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_CMD_OVERFLOW_INT_MASK_OFFSET  4
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_CMD_OVERFLOW_INT_MASK_LEN     1
+	#define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_CMD_OVERFLOW_INT_MASK_DEFAULT 0x1
+	/*[field] L3_HOST_WR_CMD_OVERFLOW_INT_MASK*/
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_CMD_OVERFLOW_INT_MASK
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_CMD_OVERFLOW_INT_MASK_OFFSET  8
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_CMD_OVERFLOW_INT_MASK_LEN     1
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_CMD_OVERFLOW_INT_MASK_DEFAULT 0x1
+	/*[field] L3_HOST_RD_CMD_OVERFLOW_INT_MASK*/
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_CMD_OVERFLOW_INT_MASK
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_CMD_OVERFLOW_INT_MASK_OFFSET  9
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_CMD_OVERFLOW_INT_MASK_LEN     1
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_CMD_OVERFLOW_INT_MASK_DEFAULT 0x1
+	/*[field] L3_HOST_WR_RESULT_VLD_INT_MASK*/
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_RESULT_VLD_INT_MASK
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_RESULT_VLD_INT_MASK_OFFSET  10
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_RESULT_VLD_INT_MASK_LEN     1
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_RESULT_VLD_INT_MASK_DEFAULT 0x1
+	/*[field] L3_HOST_RD_RESULT_VLD_INT_MASK*/
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_RESULT_VLD_INT_MASK
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_RESULT_VLD_INT_MASK_OFFSET  11
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_RESULT_VLD_INT_MASK_LEN     1
+	#define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_RESULT_VLD_INT_MASK_DEFAULT 0x1
+	/*[field] L3_FLOW_WR_CMD_OVERFLOW_INT_MASK*/
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_CMD_OVERFLOW_INT_MASK
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_CMD_OVERFLOW_INT_MASK_OFFSET  12
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_CMD_OVERFLOW_INT_MASK_LEN     1
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_CMD_OVERFLOW_INT_MASK_DEFAULT 0x1
+	/*[field] L3_FLOW_RD_CMD_OVERFLOW_INT_MASK*/
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_CMD_OVERFLOW_INT_MASK
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_CMD_OVERFLOW_INT_MASK_OFFSET  13
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_CMD_OVERFLOW_INT_MASK_LEN     1
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_CMD_OVERFLOW_INT_MASK_DEFAULT 0x1
+	/*[field] L3_FLOW_WR_RESULT_VLD_INT_MASK*/
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_RESULT_VLD_INT_MASK
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_RESULT_VLD_INT_MASK_OFFSET  14
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_RESULT_VLD_INT_MASK_LEN     1
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_RESULT_VLD_INT_MASK_DEFAULT 0x1
+	/*[field] L3_FLOW_RD_RESULT_VLD_INT_MASK*/
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_RESULT_VLD_INT_MASK
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_RESULT_VLD_INT_MASK_OFFSET  15
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_RESULT_VLD_INT_MASK_LEN     1
+	#define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_RESULT_VLD_INT_MASK_DEFAULT 0x1
+
+struct module_cpu_done_int_mask {
+	a_uint32_t  qm_cpu_op_done_int_mask:1;
+	a_uint32_t  l2_fdb_rd_result_vld_int_mask:1;
+	a_uint32_t  l2_fdb_wr_result_vld_int_mask:1;
+	a_uint32_t  l2_fdb_rd_cmd_overflow_int_mask:1;
+	a_uint32_t  l2_fdb_wr_cmd_overflow_int_mask:1;
+	a_uint32_t  _reserved0:3;
+	a_uint32_t  l3_host_wr_cmd_overflow_int_mask:1;
+	a_uint32_t  l3_host_rd_cmd_overflow_int_mask:1;
+	a_uint32_t  l3_host_wr_result_vld_int_mask:1;
+	a_uint32_t  l3_host_rd_result_vld_int_mask:1;
+	a_uint32_t  l3_flow_wr_cmd_overflow_int_mask:1;
+	a_uint32_t  l3_flow_rd_cmd_overflow_int_mask:1;
+	a_uint32_t  l3_flow_wr_result_vld_int_mask:1;
+	a_uint32_t  l3_flow_rd_result_vld_int_mask:1;
+	a_uint32_t  _reserved1:16;
+};
+
+union module_cpu_done_int_mask_u {
+	a_uint32_t val;
+	struct module_cpu_done_int_mask bf;
+};
+
+/*[register] PORT_LINK_INT_MASK*/
+#define PORT_LINK_INT_MASK
+#define PORT_LINK_INT_MASK_ADDRESS 0x38
+#define PORT_LINK_INT_MASK_NUM     1
+#define PORT_LINK_INT_MASK_INC     0x4
+#define PORT_LINK_INT_MASK_TYPE    REG_TYPE_RW
+#define PORT_LINK_INT_MASK_DEFAULT 0x37f
+	/*[field] PORT1_LINK_CHG_INT_MASK*/
+	#define PORT_LINK_INT_MASK_PORT1_LINK_CHG_INT_MASK
+	#define PORT_LINK_INT_MASK_PORT1_LINK_CHG_INT_MASK_OFFSET  0
+	#define PORT_LINK_INT_MASK_PORT1_LINK_CHG_INT_MASK_LEN     1
+	#define PORT_LINK_INT_MASK_PORT1_LINK_CHG_INT_MASK_DEFAULT 0x1
+	/*[field] PORT2_LINK_CHG_INT_MASK*/
+	#define PORT_LINK_INT_MASK_PORT2_LINK_CHG_INT_MASK
+	#define PORT_LINK_INT_MASK_PORT2_LINK_CHG_INT_MASK_OFFSET  1
+	#define PORT_LINK_INT_MASK_PORT2_LINK_CHG_INT_MASK_LEN     1
+	#define PORT_LINK_INT_MASK_PORT2_LINK_CHG_INT_MASK_DEFAULT 0x1
+	/*[field] PORT3_LINK_CHG_INT_MASK*/
+	#define PORT_LINK_INT_MASK_PORT3_LINK_CHG_INT_MASK
+	#define PORT_LINK_INT_MASK_PORT3_LINK_CHG_INT_MASK_OFFSET  2
+	#define PORT_LINK_INT_MASK_PORT3_LINK_CHG_INT_MASK_LEN     1
+	#define PORT_LINK_INT_MASK_PORT3_LINK_CHG_INT_MASK_DEFAULT 0x1
+	/*[field] PORT4_LINK_CHG_INT_MASK*/
+	#define PORT_LINK_INT_MASK_PORT4_LINK_CHG_INT_MASK
+	#define PORT_LINK_INT_MASK_PORT4_LINK_CHG_INT_MASK_OFFSET  3
+	#define PORT_LINK_INT_MASK_PORT4_LINK_CHG_INT_MASK_LEN     1
+	#define PORT_LINK_INT_MASK_PORT4_LINK_CHG_INT_MASK_DEFAULT 0x1
+	/*[field] PORT5_0_LINK_CHG_INT_MASK*/
+	#define PORT_LINK_INT_MASK_PORT5_0_LINK_CHG_INT_MASK
+	#define PORT_LINK_INT_MASK_PORT5_0_LINK_CHG_INT_MASK_OFFSET  4
+	#define PORT_LINK_INT_MASK_PORT5_0_LINK_CHG_INT_MASK_LEN     1
+	#define PORT_LINK_INT_MASK_PORT5_0_LINK_CHG_INT_MASK_DEFAULT 0x1
+	/*[field] PORT5_1_LINK_CHG_INT_MASK*/
+	#define PORT_LINK_INT_MASK_PORT5_1_LINK_CHG_INT_MASK
+	#define PORT_LINK_INT_MASK_PORT5_1_LINK_CHG_INT_MASK_OFFSET  5
+	#define PORT_LINK_INT_MASK_PORT5_1_LINK_CHG_INT_MASK_LEN     1
+	#define PORT_LINK_INT_MASK_PORT5_1_LINK_CHG_INT_MASK_DEFAULT 0x1
+	/*[field] PORT6_LINK_CHG_INT_MASK*/
+	#define PORT_LINK_INT_MASK_PORT6_LINK_CHG_INT_MASK
+	#define PORT_LINK_INT_MASK_PORT6_LINK_CHG_INT_MASK_OFFSET  6
+	#define PORT_LINK_INT_MASK_PORT6_LINK_CHG_INT_MASK_LEN     1
+	#define PORT_LINK_INT_MASK_PORT6_LINK_CHG_INT_MASK_DEFAULT 0x1
+	/*[field] XGMAC0_AN_DONE_INT_MASK*/
+	#define PORT_LINK_INT_MASK_XGMAC0_AN_DONE_INT_MASK
+	#define PORT_LINK_INT_MASK_XGMAC0_AN_DONE_INT_MASK_OFFSET  8
+	#define PORT_LINK_INT_MASK_XGMAC0_AN_DONE_INT_MASK_LEN     1
+	#define PORT_LINK_INT_MASK_XGMAC0_AN_DONE_INT_MASK_DEFAULT 0x1
+	/*[field] XGMAC1_AN_DONE_INT_MASK*/
+	#define PORT_LINK_INT_MASK_XGMAC1_AN_DONE_INT_MASK
+	#define PORT_LINK_INT_MASK_XGMAC1_AN_DONE_INT_MASK_OFFSET  9
+	#define PORT_LINK_INT_MASK_XGMAC1_AN_DONE_INT_MASK_LEN     1
+	#define PORT_LINK_INT_MASK_XGMAC1_AN_DONE_INT_MASK_DEFAULT 0x1
+
+struct port_link_int_mask {
+	a_uint32_t  port1_link_chg_int_mask:1;
+	a_uint32_t  port2_link_chg_int_mask:1;
+	a_uint32_t  port3_link_chg_int_mask:1;
+	a_uint32_t  port4_link_chg_int_mask:1;
+	a_uint32_t  port5_0_link_chg_int_mask:1;
+	a_uint32_t  port5_1_link_chg_int_mask:1;
+	a_uint32_t  port6_link_chg_int_mask:1;
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  xgmac0_an_done_int_mask:1;
+	a_uint32_t  xgmac1_an_done_int_mask:1;
+	a_uint32_t  _reserved1:22;
+};
+
+union port_link_int_mask_u {
+	a_uint32_t val;
+	struct port_link_int_mask bf;
+};
+
+/*[register] PORT_PHY_STATUS_0*/
+#define PORT_PHY_STATUS_0
+#define PORT_PHY_STATUS_0_ADDRESS 0x40
+#define PORT_PHY_STATUS_0_NUM     1
+#define PORT_PHY_STATUS_0_INC     0x4
+#define PORT_PHY_STATUS_0_TYPE    REG_TYPE_RO
+#define PORT_PHY_STATUS_0_DEFAULT 0x0
+	/*[field] PORT1_PHY_STATUS*/
+	#define PORT_PHY_STATUS_0_PORT1_PHY_STATUS
+	#define PORT_PHY_STATUS_0_PORT1_PHY_STATUS_OFFSET  0
+	#define PORT_PHY_STATUS_0_PORT1_PHY_STATUS_LEN     8
+	#define PORT_PHY_STATUS_0_PORT1_PHY_STATUS_DEFAULT 0x0
+	/*[field] PORT2_PHY_STATUS*/
+	#define PORT_PHY_STATUS_0_PORT2_PHY_STATUS
+	#define PORT_PHY_STATUS_0_PORT2_PHY_STATUS_OFFSET  8
+	#define PORT_PHY_STATUS_0_PORT2_PHY_STATUS_LEN     8
+	#define PORT_PHY_STATUS_0_PORT2_PHY_STATUS_DEFAULT 0x0
+	/*[field] PORT3_PHY_STATUS*/
+	#define PORT_PHY_STATUS_0_PORT3_PHY_STATUS
+	#define PORT_PHY_STATUS_0_PORT3_PHY_STATUS_OFFSET  16
+	#define PORT_PHY_STATUS_0_PORT3_PHY_STATUS_LEN     8
+	#define PORT_PHY_STATUS_0_PORT3_PHY_STATUS_DEFAULT 0x0
+	/*[field] PORT4_PHY_STATUS*/
+	#define PORT_PHY_STATUS_0_PORT4_PHY_STATUS
+	#define PORT_PHY_STATUS_0_PORT4_PHY_STATUS_OFFSET  24
+	#define PORT_PHY_STATUS_0_PORT4_PHY_STATUS_LEN     8
+	#define PORT_PHY_STATUS_0_PORT4_PHY_STATUS_DEFAULT 0x0
+
+struct port_phy_status_0 {
+	a_uint32_t  port1_phy_status:8;
+	a_uint32_t  port2_phy_status:8;
+	a_uint32_t  port3_phy_status:8;
+	a_uint32_t  port4_phy_status:8;
+};
+
+union port_phy_status_0_u {
+	a_uint32_t val;
+	struct port_phy_status_0 bf;
+};
+
+/*[register] PORT_PHY_STATUS_1*/
+#define PORT_PHY_STATUS_1
+#define PORT_PHY_STATUS_1_ADDRESS 0x44
+#define PORT_PHY_STATUS_1_NUM     1
+#define PORT_PHY_STATUS_1_INC     0x4
+#define PORT_PHY_STATUS_1_TYPE    REG_TYPE_RO
+#define PORT_PHY_STATUS_1_DEFAULT 0x0
+	/*[field] PORT5_0_PHY_STATUS*/
+	#define PORT_PHY_STATUS_1_PORT5_0_PHY_STATUS
+	#define PORT_PHY_STATUS_1_PORT5_0_PHY_STATUS_OFFSET  0
+	#define PORT_PHY_STATUS_1_PORT5_0_PHY_STATUS_LEN     8
+	#define PORT_PHY_STATUS_1_PORT5_0_PHY_STATUS_DEFAULT 0x0
+	/*[field] PORT5_1_PHY_STATUS*/
+	#define PORT_PHY_STATUS_1_PORT5_1_PHY_STATUS
+	#define PORT_PHY_STATUS_1_PORT5_1_PHY_STATUS_OFFSET  8
+	#define PORT_PHY_STATUS_1_PORT5_1_PHY_STATUS_LEN     8
+	#define PORT_PHY_STATUS_1_PORT5_1_PHY_STATUS_DEFAULT 0x0
+	/*[field] PORT6_PHY_STATUS*/
+	#define PORT_PHY_STATUS_1_PORT6_PHY_STATUS
+	#define PORT_PHY_STATUS_1_PORT6_PHY_STATUS_OFFSET  16
+	#define PORT_PHY_STATUS_1_PORT6_PHY_STATUS_LEN     8
+	#define PORT_PHY_STATUS_1_PORT6_PHY_STATUS_DEFAULT 0x0
+
+struct port_phy_status_1 {
+	a_uint32_t  port5_0_phy_status:8;
+	a_uint32_t  port5_1_phy_status:8;
+	a_uint32_t  port6_phy_status:8;
+	a_uint32_t  _reserved0:8;
+};
+
+union port_phy_status_1_u {
+	a_uint32_t val;
+	struct port_phy_status_1 bf;
+};
+
+/*[register] PORT1_STATUS*/
+#define PORT1_STATUS
+#define PORT1_STATUS_ADDRESS 0x50
+#define PORT1_STATUS_NUM     1
+#define PORT1_STATUS_INC     0x4
+#define PORT1_STATUS_TYPE    REG_TYPE_RO
+#define PORT1_STATUS_DEFAULT 0x0
+	/*[field] PORT1_STATUS*/
+	#define PORT1_STATUS_PORT1_STATUS
+	#define PORT1_STATUS_PORT1_STATUS_OFFSET  0
+	#define PORT1_STATUS_PORT1_STATUS_LEN     32
+	#define PORT1_STATUS_PORT1_STATUS_DEFAULT 0x0
+
+struct port1_status {
+	a_uint32_t  port1_status:32;
+};
+
+union port1_status_u {
+	a_uint32_t val;
+	struct port1_status bf;
+};
+
+/*[register] PORT2_STATUS*/
+#define PORT2_STATUS
+#define PORT2_STATUS_ADDRESS 0x54
+#define PORT2_STATUS_NUM     1
+#define PORT2_STATUS_INC     0x4
+#define PORT2_STATUS_TYPE    REG_TYPE_RO
+#define PORT2_STATUS_DEFAULT 0x0
+	/*[field] PORT2_STATUS*/
+	#define PORT2_STATUS_PORT2_STATUS
+	#define PORT2_STATUS_PORT2_STATUS_OFFSET  0
+	#define PORT2_STATUS_PORT2_STATUS_LEN     32
+	#define PORT2_STATUS_PORT2_STATUS_DEFAULT 0x0
+
+struct port2_status {
+	a_uint32_t  port2_status:32;
+};
+
+union port2_status_u {
+	a_uint32_t val;
+	struct port2_status bf;
+};
+
+/*[register] PORT3_STATUS*/
+#define PORT3_STATUS
+#define PORT3_STATUS_ADDRESS 0x58
+#define PORT3_STATUS_NUM     1
+#define PORT3_STATUS_INC     0x4
+#define PORT3_STATUS_TYPE    REG_TYPE_RO
+#define PORT3_STATUS_DEFAULT 0x0
+	/*[field] PORT3_STATUS*/
+	#define PORT3_STATUS_PORT3_STATUS
+	#define PORT3_STATUS_PORT3_STATUS_OFFSET  0
+	#define PORT3_STATUS_PORT3_STATUS_LEN     32
+	#define PORT3_STATUS_PORT3_STATUS_DEFAULT 0x0
+
+struct port3_status {
+	a_uint32_t  port3_status:32;
+};
+
+union port3_status_u {
+	a_uint32_t val;
+	struct port3_status bf;
+};
+
+/*[register] PORT4_STATUS*/
+#define PORT4_STATUS
+#define PORT4_STATUS_ADDRESS 0x5c
+#define PORT4_STATUS_NUM     1
+#define PORT4_STATUS_INC     0x4
+#define PORT4_STATUS_TYPE    REG_TYPE_RO
+#define PORT4_STATUS_DEFAULT 0x0
+	/*[field] PORT4_STATUS*/
+	#define PORT4_STATUS_PORT4_STATUS
+	#define PORT4_STATUS_PORT4_STATUS_OFFSET  0
+	#define PORT4_STATUS_PORT4_STATUS_LEN     32
+	#define PORT4_STATUS_PORT4_STATUS_DEFAULT 0x0
+
+struct port4_status {
+	a_uint32_t  port4_status:32;
+};
+
+union port4_status_u {
+	a_uint32_t val;
+	struct port4_status bf;
+};
+
+/*[register] PORT5_STATUS*/
+#define PORT5_STATUS
+#define PORT5_STATUS_ADDRESS 0x60
+#define PORT5_STATUS_NUM     1
+#define PORT5_STATUS_INC     0x4
+#define PORT5_STATUS_TYPE    REG_TYPE_RO
+#define PORT5_STATUS_DEFAULT 0x0
+	/*[field] PORT5_STATUS*/
+	#define PORT5_STATUS_PORT5_STATUS
+	#define PORT5_STATUS_PORT5_STATUS_OFFSET  0
+	#define PORT5_STATUS_PORT5_STATUS_LEN     8
+	#define PORT5_STATUS_PORT5_STATUS_DEFAULT 0x0
+	/*[field] PORT1_MAC_SPEED*/
+	#define PORT5_STATUS_PORT1_MAC_SPEED
+	#define PORT5_STATUS_PORT1_MAC_SPEED_OFFSET  16
+	#define PORT5_STATUS_PORT1_MAC_SPEED_LEN     2
+	#define PORT5_STATUS_PORT1_MAC_SPEED_DEFAULT 0x0
+	/*[field] PORT2_MAC_SPEED*/
+	#define PORT5_STATUS_PORT2_MAC_SPEED
+	#define PORT5_STATUS_PORT2_MAC_SPEED_OFFSET  18
+	#define PORT5_STATUS_PORT2_MAC_SPEED_LEN     2
+	#define PORT5_STATUS_PORT2_MAC_SPEED_DEFAULT 0x0
+	/*[field] PORT3_MAC_SPEED*/
+	#define PORT5_STATUS_PORT3_MAC_SPEED
+	#define PORT5_STATUS_PORT3_MAC_SPEED_OFFSET  20
+	#define PORT5_STATUS_PORT3_MAC_SPEED_LEN     2
+	#define PORT5_STATUS_PORT3_MAC_SPEED_DEFAULT 0x0
+	/*[field] PORT4_MAC_SPEED*/
+	#define PORT5_STATUS_PORT4_MAC_SPEED
+	#define PORT5_STATUS_PORT4_MAC_SPEED_OFFSET  22
+	#define PORT5_STATUS_PORT4_MAC_SPEED_LEN     2
+	#define PORT5_STATUS_PORT4_MAC_SPEED_DEFAULT 0x0
+
+struct port5_status {
+	a_uint32_t  port5_status:8;
+	a_uint32_t  _reserved0:8;
+	a_uint32_t  port1_mac_speed:2;
+	a_uint32_t  port2_mac_speed:2;
+	a_uint32_t  port3_mac_speed:2;
+	a_uint32_t  port4_mac_speed:2;
+	a_uint32_t  _reserved1:8;
+};
+
+union port5_status_u {
+	a_uint32_t val;
+	struct port5_status bf;
+};
+
+/*[register] PORT6_STATUS*/
+#define PORT6_STATUS
+#define PORT6_STATUS_ADDRESS 0x64
+#define PORT6_STATUS_NUM     1
+#define PORT6_STATUS_INC     0x4
+#define PORT6_STATUS_TYPE    REG_TYPE_RO
+#define PORT6_STATUS_DEFAULT 0x0
+	/*[field] PORT6_STATUS*/
+	#define PORT6_STATUS_PORT6_STATUS
+	#define PORT6_STATUS_PORT6_STATUS_OFFSET  0
+	#define PORT6_STATUS_PORT6_STATUS_LEN     8
+	#define PORT6_STATUS_PORT6_STATUS_DEFAULT 0x0
+
+struct port6_status {
+	a_uint32_t  port6_status:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union port6_status_u {
+	a_uint32_t val;
+	struct port6_status bf;
+};
+
+/*[register] RESERVED_REGS_0*/
+#define RESERVED_REGS_0
+#define RESERVED_REGS_0_ADDRESS 0x70
+#define RESERVED_REGS_0_NUM     1
+#define RESERVED_REGS_0_INC     0x4
+#define RESERVED_REGS_0_TYPE    REG_TYPE_RW
+#define RESERVED_REGS_0_DEFAULT 0x0
+	/*[field] SPARE_REGS_0*/
+	#define RESERVED_REGS_0_SPARE_REGS_0
+	#define RESERVED_REGS_0_SPARE_REGS_0_OFFSET  0
+	#define RESERVED_REGS_0_SPARE_REGS_0_LEN     32
+	#define RESERVED_REGS_0_SPARE_REGS_0_DEFAULT 0x0
+
+struct reserved_regs_0 {
+	a_uint32_t  spare_regs_0:32;
+};
+
+union reserved_regs_0_u {
+	a_uint32_t val;
+	struct reserved_regs_0 bf;
+};
+
+/*[register] RESERVED_REGS_1*/
+#define RESERVED_REGS_1
+#define RESERVED_REGS_1_ADDRESS 0x74
+#define RESERVED_REGS_1_NUM     1
+#define RESERVED_REGS_1_INC     0x4
+#define RESERVED_REGS_1_TYPE    REG_TYPE_RW
+#define RESERVED_REGS_1_DEFAULT 0x0
+	/*[field] SPARE_REGS_1*/
+	#define RESERVED_REGS_1_SPARE_REGS_1
+	#define RESERVED_REGS_1_SPARE_REGS_1_OFFSET  0
+	#define RESERVED_REGS_1_SPARE_REGS_1_LEN     32
+	#define RESERVED_REGS_1_SPARE_REGS_1_DEFAULT 0x0
+
+struct reserved_regs_1 {
+	a_uint32_t  spare_regs_1:32;
+};
+
+union reserved_regs_1_u {
+	a_uint32_t val;
+	struct reserved_regs_1 bf;
+};
+
+/*[register] RESERVED_REGS_2*/
+#define RESERVED_REGS_2
+#define RESERVED_REGS_2_ADDRESS 0x78
+#define RESERVED_REGS_2_NUM     1
+#define RESERVED_REGS_2_INC     0x4
+#define RESERVED_REGS_2_TYPE    REG_TYPE_RW
+#define RESERVED_REGS_2_DEFAULT 0x0
+	/*[field] SPARE_REGS_2*/
+	#define RESERVED_REGS_2_SPARE_REGS_2
+	#define RESERVED_REGS_2_SPARE_REGS_2_OFFSET  0
+	#define RESERVED_REGS_2_SPARE_REGS_2_LEN     32
+	#define RESERVED_REGS_2_SPARE_REGS_2_DEFAULT 0x0
+
+struct reserved_regs_2 {
+	a_uint32_t  spare_regs_2:32;
+};
+
+union reserved_regs_2_u {
+	a_uint32_t val;
+	struct reserved_regs_2 bf;
+};
+
+/*[register] RESERVED_REGS_3*/
+#define RESERVED_REGS_3
+#define RESERVED_REGS_3_ADDRESS 0x7c
+#define RESERVED_REGS_3_NUM     1
+#define RESERVED_REGS_3_INC     0x4
+#define RESERVED_REGS_3_TYPE    REG_TYPE_RW
+#define RESERVED_REGS_3_DEFAULT 0x0
+	/*[field] SPARE_REGS_3*/
+	#define RESERVED_REGS_3_SPARE_REGS_3
+	#define RESERVED_REGS_3_SPARE_REGS_3_OFFSET  0
+	#define RESERVED_REGS_3_SPARE_REGS_3_LEN     32
+	#define RESERVED_REGS_3_SPARE_REGS_3_DEFAULT 0x0
+
+struct reserved_regs_3 {
+	a_uint32_t  spare_regs_3:32;
+};
+
+union reserved_regs_3_u {
+	a_uint32_t val;
+	struct reserved_regs_3 bf;
+};
+
+/*[register] DBG_DATA_SEL*/
+#define DBG_DATA_SEL
+#define DBG_DATA_SEL_ADDRESS 0x80
+#define DBG_DATA_SEL_NUM     1
+#define DBG_DATA_SEL_INC     0x4
+#define DBG_DATA_SEL_TYPE    REG_TYPE_RW
+#define DBG_DATA_SEL_DEFAULT 0x0
+	/*[field] DBG_DATA_SEL_DESP*/
+	#define DBG_DATA_SEL_DBG_DATA_SEL_DESP
+	#define DBG_DATA_SEL_DBG_DATA_SEL_DESP_OFFSET  0
+	#define DBG_DATA_SEL_DBG_DATA_SEL_DESP_LEN     5
+	#define DBG_DATA_SEL_DBG_DATA_SEL_DESP_DEFAULT 0x0
+	/*[field] DBG_DATA_SEL_SWITCH*/
+	#define DBG_DATA_SEL_DBG_DATA_SEL_SWITCH
+	#define DBG_DATA_SEL_DBG_DATA_SEL_SWITCH_OFFSET  5
+	#define DBG_DATA_SEL_DBG_DATA_SEL_SWITCH_LEN     1
+	#define DBG_DATA_SEL_DBG_DATA_SEL_SWITCH_DEFAULT 0x0
+
+struct dbg_data_sel {
+	a_uint32_t  dbg_data_sel_desp:5;
+	a_uint32_t  dbg_data_sel_switch:1;
+	a_uint32_t  _reserved0:26;
+};
+
+union dbg_data_sel_u {
+	a_uint32_t val;
+	struct dbg_data_sel bf;
+};
+
+
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_init.h b/qca-ssdk/include/hsl/hppe/hppe_init.h
new file mode 100755
index 0000000..0ec05ff
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_init.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2016-2017, 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup hppe_init _HPPE_INIT_H_
+ * @{
+ */
+#ifndef _HPPE_INIT_H_
+#define _HPPE_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+#define HPPE_GCC_UNIPHY_REG_INC 0x100
+#define HPPE_TO_XGMAC_PORT_ID(port_id)  (port_id - 5)
+#define HPPE_TO_GMAC_PORT_ID(port_id) (port_id -1)
+#define HPPE_FCS_LEN  4
+
+#define HPPE_MUX_PORT1  5
+#define HPPE_MUX_PORT2  6
+
+#define HPPE_GCC_UNIPHY_PSGMII_SOFT_RESET 0x3ff2
+#define HPPE_GCC_UNIPHY_USXGMII_SOFT_RESET 0x36
+#define HPPE_MAX_PORT_NUM 6
+#define HPPE_GCC_UNIPHY_USXGMII_XPCS_RESET 0x4
+#define HPPE_GCC_UNIPHY_USXGMII_XPCS_RELEASE_RESET 0x0
+
+
+#define HPPE_UNIPHY_BASE1	0x10000
+#define HPPE_UNIPHY_BASE2	0x20000
+#define HPPE_UNIPHY_MAX_DIRECT_ACCESS_REG	0x7fff
+#define HPPE_UNIPHY_INDIRECT_REG_ADDR   0x83fc
+#define HPPE_UNIPHY_INDIRECT_HIGH_ADDR  0x1fff00
+#define HPPE_UNIPHY_INDIRECT_LOW_ADDR   0xff
+#define HPPE_UNIPHY_INDIRECT_DATA       0x20
+#define UNIPHY_CALIBRATION_DONE         0x1
+#define UNIPHY_10GR_LINKUP              0x1
+#define UNIPHY_10GR_LINK_LOSS           0x7
+#define UNIPHY_ATHEROS_NEGOTIATION      0x0
+#define UNIPHY_STANDARD_NEGOTIATION     0x1
+#define UNIPHY_CH0_QSGMII_SGMII_MODE    0x0
+#define UNIPHY_CH0_PSGMII_MODE          0x1
+#define UNIPHY_CH0_SGMII_MODE           0x0
+#define UNIPHY_CH0_QSGMII_MODE          0x1
+#define UNIPHY_SGMII_MODE_ENABLE        0x1
+#define UNIPHY_SGMII_MODE_DISABLE       0x0
+#define UNIPHY_SGMIIPLUS_MODE_ENABLE    0x1
+#define UNIPHY_SGMIIPLUS_MODE_DISABLE   0x0
+#define UNIPHY_XPCS_MODE_ENABLE         0x1
+#define UNIPHY_XPCS_MODE_DISABLE        0x0
+#define UNIPHY_PHY_SGMII_MODE           0x3
+#define UNIPHY_PHY_SGMIIPLUS_MODE       0x5
+#define UNIPHY_SGMII_CHANNEL1_DISABLE   0x0
+#define UNIPHY_SGMII_CHANNEL1_ENABLE    0x1
+#define UNIPHY_SGMII_CHANNEL4_DISABLE   0x0
+#define UNIPHY_SGMII_CHANNEL4_ENABLE    0x1
+#define UNIPHY_FORCE_SPEED_ENABLE       0x1
+
+#define SGMII_1000M_SOURCE1_CLOCK1 0x101
+#define SGMII_100M_SOURCE1_CLOCK1 0x109
+#define SGMII_10M_SOURCE1_CLOCK1 0x109
+#define SGMII_1000M_SOURCE2_CLOCK1 0x301
+#define SGMII_100M_SOURCE2_CLOCK1 0x309
+#define SGMII_10M_SOURCE2_CLOCK1 0x309
+#define SGMII_1000M_CLOCK2 0x0
+#define SGMII_100M_CLOCK2 0x0
+#define SGMII_10M_CLOCK2 0x9
+#define UNIPHY_MISC2_REG_OFFSET 0x218
+#define UNIPHY_PLL_RESET_REG_OFFSET 0x780
+#define UNIPHY_MISC2_REG_VALUE 0x70
+#define UNIPHY_MISC2_REG_SGMII_PLUS_MODE 0x50
+#define UNIPHY_PLL_RESET_REG_VALUE 0x02bf
+#define UNIPHY_PLL_RESET_REG_DEFAULT_VALUE 0x02ff
+#define UNIPHY_MISC2_REG_SGMII_MODE 0x30
+#define UNIPHY_FORCE_SPEED_MODE_ENABLE       0x1
+
+#define AQ_PHY_AUTO_STATUS_REG 0x70001
+#define AQ_PHY_LINK_STATUS_REG 0x7c800
+#define AQ_PHY_FLOWCTRL_STATUS_REG 0x7c810
+#define PHY_MII_STATUS_REG 0x11
+
+
+#define MALIBU_PHY_QSGMII 0x8504
+#define MALIBU_PHY_MODE_REG 0x1f
+#define MALIBU_PSGMII_PHY_ADDR 0x5
+#define MALIBU_MODE_CHANAGE_RESET 0x0
+#define MALIBU_MODE_RESET_DEFAULT_VALUE 0x5f
+#define MALIBU_MODE_RESET_REG 0x0
+
+sw_error_t hppe_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+a_bool_t hppe_mac_port_valid_check(a_uint32_t dev_id, fal_port_t port_id);
+a_bool_t hppe_xgmac_port_check(fal_port_t port_id);
+sw_error_t hppe_cleanup(a_uint32_t dev_id);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HPPE_INIT_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/hppe/hppe_ip.h b/qca-ssdk/include/hsl/hppe/hppe_ip.h
new file mode 100755
index 0000000..e3f17fb
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_ip.h
@@ -0,0 +1,2696 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_IP_H_
+#define _HPPE_IP_H_
+
+#define MY_MAC_TBL_MAX_ENTRY	8
+#define L3_VSI_MAX_ENTRY	32
+#define L3_VSI_EXT_MAX_ENTRY	32
+#define NETWORK_ROUTE_IP_MAX_ENTRY	32
+#define NETWORK_ROUTE_IP_EXT_MAX_ENTRY	32
+#define NETWORK_ROUTE_ACTION_MAX_ENTRY	32
+#define L3_VP_PORT_TBL_MAX_ENTRY	256
+#define IN_L3_IF_TBL_MAX_ENTRY	256
+#define HOST_IPV6_MCAST_TBL_MAX_ENTRY	1536
+#define HOST_IPV4_MCAST_TBL_MAX_ENTRY	3072
+#define HOST_TBL_MAX_ENTRY	6144
+#define HOST_IPV6_TBL_MAX_ENTRY	3072
+#define IN_NEXTHOP_TBL_MAX_ENTRY	2560
+#define EG_L3_IF_TBL_MAX_ENTRY	256
+#define IN_PUB_IP_ADDR_TBL_MAX_ENTRY	16
+#define RT_INTERFACE_CNT_TBL_MAX_ENTRY	512
+
+#ifndef IP_MINI
+sw_error_t
+hppe_rt_interface_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rt_interface_cnt_tbl_u *value);
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rt_interface_cnt_tbl_u *value);
+
+sw_error_t
+hppe_my_mac_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union my_mac_tbl_u *value);
+
+sw_error_t
+hppe_my_mac_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union my_mac_tbl_u *value);
+
+sw_error_t
+hppe_l3_vsi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_vsi_u *value);
+
+sw_error_t
+hppe_l3_vsi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_vsi_u *value);
+
+sw_error_t
+hppe_l3_vsi_ext_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_vsi_ext_u *value);
+
+sw_error_t
+hppe_l3_vsi_ext_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_vsi_ext_u *value);
+
+sw_error_t
+hppe_in_pub_ip_addr_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_pub_ip_addr_tbl_u *value);
+
+sw_error_t
+hppe_in_pub_ip_addr_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_pub_ip_addr_tbl_u *value);
+
+sw_error_t
+hppe_network_route_ip_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union network_route_ip_u *value);
+
+sw_error_t
+hppe_network_route_ip_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union network_route_ip_u *value);
+
+sw_error_t
+hppe_network_route_ip_ext_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union network_route_ip_ext_u *value);
+
+sw_error_t
+hppe_network_route_ip_ext_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union network_route_ip_ext_u *value);
+
+sw_error_t
+hppe_network_route_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union network_route_action_u *value);
+
+sw_error_t
+hppe_network_route_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union network_route_action_u *value);
+#endif
+#if ((!defined IN_IP_MINI) || (!defined IN_FLOW_MINI))
+sw_error_t
+hppe_l3_route_ctrl_get(
+		a_uint32_t dev_id,
+		union l3_route_ctrl_u *value);
+
+sw_error_t
+hppe_l3_route_ctrl_set(
+		a_uint32_t dev_id,
+		union l3_route_ctrl_u *value);
+
+sw_error_t
+hppe_l3_route_ctrl_ext_get(
+		a_uint32_t dev_id,
+		union l3_route_ctrl_ext_u *value);
+
+sw_error_t
+hppe_l3_route_ctrl_ext_set(
+		a_uint32_t dev_id,
+		union l3_route_ctrl_ext_u *value);
+#endif
+#ifndef IN_IP_MINI
+sw_error_t
+hppe_host_tbl_op_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_u *value);
+
+sw_error_t
+hppe_host_tbl_op_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_u *value);
+#endif
+#if ((!defined IN_IP_MINI) || (!defined IN_FLOW_MINI))
+sw_error_t
+hppe_host_tbl_op_data0_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data0_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data0_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data0_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data1_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data1_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data1_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data1_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data2_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data2_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data2_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data2_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data3_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data3_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data3_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data3_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data4_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data4_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data4_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data4_u *value);
+#endif
+#ifndef IN_IP_MINI
+sw_error_t
+hppe_host_tbl_op_data5_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data5_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data5_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data5_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data6_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data6_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data6_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data6_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data7_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data7_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data7_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data7_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data8_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data8_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data8_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data8_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data9_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data9_u *value);
+
+sw_error_t
+hppe_host_tbl_op_data9_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data9_u *value);
+
+sw_error_t
+hppe_host_tbl_op_rslt_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_rslt_u *value);
+
+sw_error_t
+hppe_host_tbl_op_rslt_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_rslt_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_u *value);
+#endif
+#if ((!defined IN_IP_MINI) || (!defined IN_FLOW_MINI))
+sw_error_t
+hppe_host_tbl_rd_op_data0_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data0_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data0_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data0_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data1_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data1_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data1_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data1_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data2_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data2_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data2_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data2_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data3_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data3_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data3_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data3_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data4_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data4_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data4_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data4_u *value);
+#endif
+#ifndef IN_IP_MINI
+sw_error_t
+hppe_host_tbl_rd_op_data5_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data5_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data5_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data5_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data6_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data6_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data6_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data6_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data7_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data7_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data7_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data7_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data8_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data8_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data8_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data8_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data9_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data9_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data9_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data9_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_rslt_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_rslt_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data0_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data0_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data0_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data0_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data1_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data1_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data1_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data1_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data2_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data2_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data2_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data2_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data3_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data3_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data3_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data3_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data4_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data4_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data4_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data4_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data5_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data5_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data5_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data5_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data6_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data6_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data6_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data6_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data7_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data7_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data7_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data7_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data8_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data8_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data8_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data8_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data9_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data9_u *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data9_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data9_u *value);
+
+sw_error_t
+hppe_l3_dbg_cmd_get(
+		a_uint32_t dev_id,
+		union l3_dbg_cmd_u *value);
+
+sw_error_t
+hppe_l3_dbg_cmd_set(
+		a_uint32_t dev_id,
+		union l3_dbg_cmd_u *value);
+
+sw_error_t
+hppe_l3_dbg_wr_data_get(
+		a_uint32_t dev_id,
+		union l3_dbg_wr_data_u *value);
+
+sw_error_t
+hppe_l3_dbg_wr_data_set(
+		a_uint32_t dev_id,
+		union l3_dbg_wr_data_u *value);
+
+sw_error_t
+hppe_l3_dbg_rd_data_get(
+		a_uint32_t dev_id,
+		union l3_dbg_rd_data_u *value);
+
+sw_error_t
+hppe_l3_dbg_rd_data_set(
+		a_uint32_t dev_id,
+		union l3_dbg_rd_data_u *value);
+#endif
+sw_error_t
+hppe_l3_vp_port_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_vp_port_tbl_u *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_vp_port_tbl_u *value);
+#if ((!defined IN_IP_MINI) || (defined IN_PPPOE))
+sw_error_t
+hppe_in_l3_if_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_l3_if_tbl_u *value);
+
+sw_error_t
+hppe_in_l3_if_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_l3_if_tbl_u *value);
+#endif
+#ifndef IN_IP_MINI
+sw_error_t
+hppe_host_ipv6_mcast_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_ipv6_mcast_tbl_u *value);
+
+sw_error_t
+hppe_host_ipv6_mcast_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_ipv6_mcast_tbl_u *value);
+
+sw_error_t
+hppe_host_ipv4_mcast_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_ipv4_mcast_tbl_u *value);
+
+sw_error_t
+hppe_host_ipv4_mcast_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_ipv4_mcast_tbl_u *value);
+
+sw_error_t
+hppe_host_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_tbl_u *value);
+
+sw_error_t
+hppe_host_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_tbl_u *value);
+
+sw_error_t
+hppe_host_ipv6_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_ipv6_tbl_u *value);
+
+sw_error_t
+hppe_host_ipv6_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_ipv6_tbl_u *value);
+
+sw_error_t
+hppe_in_nexthop_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_nexthop_tbl_u *value);
+
+sw_error_t
+hppe_in_nexthop_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_nexthop_tbl_u *value);
+#endif
+#if ((!defined IN_IP_MINI) || (defined IN_PPPOE))
+sw_error_t
+hppe_eg_l3_if_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_l3_if_tbl_u *value);
+
+sw_error_t
+hppe_eg_l3_if_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_l3_if_tbl_u *value);
+#endif
+#ifndef IN_IP_MINI
+sw_error_t
+hppe_my_mac_tbl_mac_da_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_my_mac_tbl_mac_da_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_my_mac_tbl_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_my_mac_tbl_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_l3_if_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_l3_if_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_l2_ipv6_mc_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_l2_ipv6_mc_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_l3_if_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_l3_if_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_l2_ipv6_mc_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_l2_ipv6_mc_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_l2_ipv4_mc_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_l2_ipv4_mc_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_l2_ipv4_mc_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_l2_ipv4_mc_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_network_route_ip_ip_addr_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_network_route_ip_ip_addr_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_network_route_ip_ip_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_network_route_ip_ip_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_network_route_ip_ext_entry_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_network_route_ip_ext_entry_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_network_route_ip_ext_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_network_route_ip_ext_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_network_route_action_lan_wan_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_network_route_action_lan_wan_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_network_route_action_fwd_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_network_route_action_fwd_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_network_route_action_dst_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_network_route_action_dst_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_route_ctrl_flow_src_if_check_de_acce_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_flow_src_if_check_de_acce_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_pppoe_multicast_cmd_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_pppoe_multicast_cmd_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_fail_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_fail_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_flow_src_if_check_cmd_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_flow_src_if_check_cmd_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_icmp_rdt_de_acce_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_icmp_rdt_de_acce_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_flow_de_acce_cmd_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_flow_de_acce_cmd_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_fail_de_acce_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_fail_de_acce_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_flow_sync_mismatch_cmd_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_flow_sync_mismatch_cmd_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_flow_service_code_loop_de_acce_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_flow_service_code_loop_de_acce_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_flow_sync_mismatch_de_acce_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_flow_sync_mismatch_de_acce_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_df_fail_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_df_fail_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_flow_service_code_loop_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_flow_service_code_loop_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mru_check_fail_de_acce_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mru_check_fail_de_acce_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_prefix_bc_cmd_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_prefix_bc_cmd_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_df_fail_de_acce_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_df_fail_de_acce_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_pppoe_multicast_de_acce_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_pppoe_multicast_de_acce_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mru_check_fail_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mru_check_fail_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_icmp_rdt_cmd_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_icmp_rdt_cmd_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_prefix_bc_de_acce_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_ip_prefix_bc_de_acce_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_ext_flow_service_code_loop_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_ext_flow_service_code_loop_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_ext_host_hash_mode_0_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_ext_host_hash_mode_0_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_ext_host_hash_mode_1_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_ext_host_hash_mode_1_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_route_ctrl_ext_ip_route_mismatch_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_route_ctrl_ext_ip_route_mismatch_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+
+sw_error_t
+hppe_host_tbl_op_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_cmd_id_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_cmd_id_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_byp_rslt_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_byp_rslt_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_op_mode_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_op_mode_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_op_type_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_op_type_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_op_result_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_op_result_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_busy_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_busy_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_data0_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_data0_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_data1_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_data1_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_data2_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_data2_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_data3_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_data3_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_data4_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_data4_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_data5_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_data5_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_data6_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_data6_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_data7_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_data7_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_data8_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_data8_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_data9_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_data9_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_rslt_op_rslt_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_rslt_op_rslt_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_rslt_valid_cnt_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_rslt_valid_cnt_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_rslt_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_rslt_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_op_rslt_cmd_id_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_op_rslt_cmd_id_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_cmd_id_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_cmd_id_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_byp_rslt_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_byp_rslt_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_op_mode_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_op_mode_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_op_type_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_op_type_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_op_result_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_op_result_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_busy_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_busy_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data0_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data0_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data1_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data1_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data2_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data2_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data3_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data3_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data4_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data4_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data5_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data5_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data6_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data6_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data7_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data7_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data8_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data8_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data9_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_data9_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_op_rslt_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_op_rslt_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_valid_cnt_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_valid_cnt_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_entry_index_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_entry_index_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_cmd_id_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_cmd_id_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data0_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data0_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data1_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data1_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data2_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data2_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data3_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data3_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data4_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data4_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data5_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data5_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data6_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data6_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data7_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data7_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data8_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data8_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data9_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data9_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_dbg_cmd_type_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_dbg_cmd_type_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_dbg_cmd_addr_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_dbg_cmd_addr_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_dbg_wr_data_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_dbg_wr_data_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_dbg_rd_data_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_dbg_rd_data_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_l3_if_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_l3_if_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_l3_if_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_l3_if_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_mac_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_mac_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_vsi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_vsi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_mac_da_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_mac_da_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_vsi_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_vsi_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l3_if_tbl_ttl_dec_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l3_if_tbl_ttl_dec_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l3_if_tbl_ttl_exceed_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l3_if_tbl_ttl_exceed_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l3_if_tbl_mru_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l3_if_tbl_mru_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l3_if_tbl_ipv4_uc_route_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l3_if_tbl_ipv4_uc_route_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l3_if_tbl_ipv6_uc_route_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l3_if_tbl_ipv6_uc_route_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l3_if_tbl_ttl_exceed_de_acce_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l3_if_tbl_ttl_exceed_de_acce_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l3_if_tbl_icmp_trigger_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l3_if_tbl_icmp_trigger_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l3_if_tbl_mac_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l3_if_tbl_mac_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l3_if_tbl_pppoe_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l3_if_tbl_pppoe_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l3_if_tbl_mtu_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l3_if_tbl_mtu_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_nexthop_tbl_ip_pub_addr_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_nexthop_tbl_ip_pub_addr_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_nexthop_tbl_cvid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_nexthop_tbl_cvid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_nexthop_tbl_post_l3_if_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_nexthop_tbl_post_l3_if_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_nexthop_tbl_mac_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_in_nexthop_tbl_mac_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_in_nexthop_tbl_port_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_nexthop_tbl_port_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_nexthop_tbl_ip_to_me_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_nexthop_tbl_ip_to_me_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_nexthop_tbl_ip_addr_dnat_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_nexthop_tbl_ip_addr_dnat_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_nexthop_tbl_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_nexthop_tbl_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_nexthop_tbl_stag_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_nexthop_tbl_stag_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_nexthop_tbl_vsi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_nexthop_tbl_vsi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_nexthop_tbl_svid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_nexthop_tbl_svid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_nexthop_tbl_ctag_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_nexthop_tbl_ctag_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_l3_if_tbl_session_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_l3_if_tbl_session_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_l3_if_tbl_mac_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_eg_l3_if_tbl_mac_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_eg_l3_if_tbl_pppoe_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_l3_if_tbl_pppoe_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_pub_ip_addr_tbl_ip_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_pub_ip_addr_tbl_ip_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_drop_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_drop_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_drop_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_drop_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+
+sw_error_t
+hppe_host_ipv4_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_tbl_u *entry);
+
+sw_error_t
+hppe_host_ipv6_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_tbl_u *entry);
+
+sw_error_t
+hppe_host_ipv4_mcast_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv4_mcast_tbl_u *entry);
+
+sw_error_t
+hppe_host_ipv6_mcast_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_mcast_tbl_u *entry);
+
+sw_error_t
+hppe_host_ipv4_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_tbl_u *entry);
+
+sw_error_t
+hppe_host_ipv6_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_tbl_u *entry);
+
+sw_error_t
+hppe_host_ipv4_mcast_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv4_mcast_tbl_u *entry);
+
+sw_error_t
+hppe_host_ipv6_mcast_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_mcast_tbl_u *entry);
+
+sw_error_t
+hppe_host_ipv4_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_tbl_u *entry);
+
+sw_error_t
+hppe_host_ipv6_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_tbl_u *entry);
+
+sw_error_t
+hppe_host_ipv4_mcast_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv4_mcast_tbl_u *entry);
+
+sw_error_t
+hppe_host_ipv6_mcast_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_mcast_tbl_u *entry);
+
+sw_error_t
+hppe_host_flush_common(a_uint32_t dev_id);
+#endif
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_ip_reg.h b/qca-ssdk/include/hsl/hppe/hppe_ip_reg.h
new file mode 100755
index 0000000..31be3c3
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_ip_reg.h
@@ -0,0 +1,2240 @@
+/*
+ * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_IP_REG_H_
+#define _HPPE_IP_REG_H_
+
+/*[table] MY_MAC_TBL*/
+#define MY_MAC_TBL
+#define MY_MAC_TBL_ADDRESS 0x0
+#define MY_MAC_TBL_NUM     8
+#define MY_MAC_TBL_INC     0x8
+#define MY_MAC_TBL_TYPE    REG_TYPE_RW
+#define MY_MAC_TBL_DEFAULT 0x0
+	/*[field] MAC_DA*/
+	#define MY_MAC_TBL_MAC_DA
+	#define MY_MAC_TBL_MAC_DA_OFFSET  0
+	#define MY_MAC_TBL_MAC_DA_LEN     48
+	#define MY_MAC_TBL_MAC_DA_DEFAULT 0x0
+	/*[field] VALID*/
+	#define MY_MAC_TBL_VALID
+	#define MY_MAC_TBL_VALID_OFFSET  48
+	#define MY_MAC_TBL_VALID_LEN     1
+	#define MY_MAC_TBL_VALID_DEFAULT 0x0
+
+struct my_mac_tbl {
+	a_uint32_t  mac_da_0:32;
+	a_uint32_t  mac_da_1:16;
+	a_uint32_t  valid:1;
+	a_uint32_t  _reserved0:15;
+};
+
+union my_mac_tbl_u {
+	a_uint32_t val[2];
+	struct my_mac_tbl bf;
+};
+
+/*[register] L3_VSI*/
+#define L3_VSI
+#define L3_VSI_ADDRESS 0x40
+#define L3_VSI_NUM     32
+#define L3_VSI_INC     0x4
+#define L3_VSI_TYPE    REG_TYPE_RW
+#define L3_VSI_DEFAULT 0x0
+	/*[field] L3_IF_VALID*/
+	#define L3_VSI_L3_IF_VALID
+	#define L3_VSI_L3_IF_VALID_OFFSET  0
+	#define L3_VSI_L3_IF_VALID_LEN     1
+	#define L3_VSI_L3_IF_VALID_DEFAULT 0x0
+	/*[field] L3_IF_INDEX*/
+	#define L3_VSI_L3_IF_INDEX
+	#define L3_VSI_L3_IF_INDEX_OFFSET  1
+	#define L3_VSI_L3_IF_INDEX_LEN     8
+	#define L3_VSI_L3_IF_INDEX_DEFAULT 0x0
+	/*[field] L2_IPV4_MC_EN*/
+	#define L3_VSI_L2_IPV4_MC_EN
+	#define L3_VSI_L2_IPV4_MC_EN_OFFSET  9
+	#define L3_VSI_L2_IPV4_MC_EN_LEN     1
+	#define L3_VSI_L2_IPV4_MC_EN_DEFAULT 0x0
+	/*[field] L2_IPV4_MC_MODE*/
+	#define L3_VSI_L2_IPV4_MC_MODE
+	#define L3_VSI_L2_IPV4_MC_MODE_OFFSET  10
+	#define L3_VSI_L2_IPV4_MC_MODE_LEN     1
+	#define L3_VSI_L2_IPV4_MC_MODE_DEFAULT 0x0
+	/*[field] L2_IPV6_MC_EN*/
+	#define L3_VSI_L2_IPV6_MC_EN
+	#define L3_VSI_L2_IPV6_MC_EN_OFFSET  11
+	#define L3_VSI_L2_IPV6_MC_EN_LEN     1
+	#define L3_VSI_L2_IPV6_MC_EN_DEFAULT 0x0
+	/*[field] L2_IPV6_MC_MODE*/
+	#define L3_VSI_L2_IPV6_MC_MODE
+	#define L3_VSI_L2_IPV6_MC_MODE_OFFSET  12
+	#define L3_VSI_L2_IPV6_MC_MODE_LEN     1
+	#define L3_VSI_L2_IPV6_MC_MODE_DEFAULT 0x0
+
+struct l3_vsi {
+	a_uint32_t  l3_if_valid:1;
+	a_uint32_t  l3_if_index:8;
+	a_uint32_t  l2_ipv4_mc_en:1;
+	a_uint32_t  l2_ipv4_mc_mode:1;
+	a_uint32_t  l2_ipv6_mc_en:1;
+	a_uint32_t  l2_ipv6_mc_mode:1;
+	a_uint32_t  _reserved0:19;
+};
+
+union l3_vsi_u {
+	a_uint32_t val;
+	struct l3_vsi bf;
+};
+
+/*[register] L3_VSI_EXT*/
+#define L3_VSI_EXT
+#define L3_VSI_EXT_ADDRESS 0xc0
+#define L3_VSI_EXT_NUM     32
+#define L3_VSI_EXT_INC     0x4
+#define L3_VSI_EXT_TYPE    REG_TYPE_RW
+#define L3_VSI_EXT_DEFAULT 0x0
+	/*[field] IPV4_SG_EN*/
+	#define L3_VSI_EXT_IPV4_SG_EN
+	#define L3_VSI_EXT_IPV4_SG_EN_OFFSET  0
+	#define L3_VSI_EXT_IPV4_SG_EN_LEN     1
+	#define L3_VSI_EXT_IPV4_SG_EN_DEFAULT 0x0
+	/*[field] IPV4_SG_VIO_CMD*/
+	#define L3_VSI_EXT_IPV4_SG_VIO_CMD
+	#define L3_VSI_EXT_IPV4_SG_VIO_CMD_OFFSET  1
+	#define L3_VSI_EXT_IPV4_SG_VIO_CMD_LEN     2
+	#define L3_VSI_EXT_IPV4_SG_VIO_CMD_DEFAULT 0x0
+	/*[field] IPV4_SG_PORT_EN*/
+	#define L3_VSI_EXT_IPV4_SG_PORT_EN
+	#define L3_VSI_EXT_IPV4_SG_PORT_EN_OFFSET  3
+	#define L3_VSI_EXT_IPV4_SG_PORT_EN_LEN     1
+	#define L3_VSI_EXT_IPV4_SG_PORT_EN_DEFAULT 0x0
+	/*[field] IPV4_SG_SVLAN_EN*/
+	#define L3_VSI_EXT_IPV4_SG_SVLAN_EN
+	#define L3_VSI_EXT_IPV4_SG_SVLAN_EN_OFFSET  4
+	#define L3_VSI_EXT_IPV4_SG_SVLAN_EN_LEN     1
+	#define L3_VSI_EXT_IPV4_SG_SVLAN_EN_DEFAULT 0x0
+	/*[field] IPV4_SG_CVLAN_EN*/
+	#define L3_VSI_EXT_IPV4_SG_CVLAN_EN
+	#define L3_VSI_EXT_IPV4_SG_CVLAN_EN_OFFSET  5
+	#define L3_VSI_EXT_IPV4_SG_CVLAN_EN_LEN     1
+	#define L3_VSI_EXT_IPV4_SG_CVLAN_EN_DEFAULT 0x0
+	/*[field] IPV4_SRC_UNK_CMD*/
+	#define L3_VSI_EXT_IPV4_SRC_UNK_CMD
+	#define L3_VSI_EXT_IPV4_SRC_UNK_CMD_OFFSET  6
+	#define L3_VSI_EXT_IPV4_SRC_UNK_CMD_LEN     2
+	#define L3_VSI_EXT_IPV4_SRC_UNK_CMD_DEFAULT 0x0
+	/*[field] IPV6_SG_EN*/
+	#define L3_VSI_EXT_IPV6_SG_EN
+	#define L3_VSI_EXT_IPV6_SG_EN_OFFSET  8
+	#define L3_VSI_EXT_IPV6_SG_EN_LEN     1
+	#define L3_VSI_EXT_IPV6_SG_EN_DEFAULT 0x0
+	/*[field] IPV6_SG_VIO_CMD*/
+	#define L3_VSI_EXT_IPV6_SG_VIO_CMD
+	#define L3_VSI_EXT_IPV6_SG_VIO_CMD_OFFSET  9
+	#define L3_VSI_EXT_IPV6_SG_VIO_CMD_LEN     2
+	#define L3_VSI_EXT_IPV6_SG_VIO_CMD_DEFAULT 0x0
+	/*[field] IPV6_SG_PORT_EN*/
+	#define L3_VSI_EXT_IPV6_SG_PORT_EN
+	#define L3_VSI_EXT_IPV6_SG_PORT_EN_OFFSET  11
+	#define L3_VSI_EXT_IPV6_SG_PORT_EN_LEN     1
+	#define L3_VSI_EXT_IPV6_SG_PORT_EN_DEFAULT 0x0
+	/*[field] IPV6_SG_SVLAN_EN*/
+	#define L3_VSI_EXT_IPV6_SG_SVLAN_EN
+	#define L3_VSI_EXT_IPV6_SG_SVLAN_EN_OFFSET  12
+	#define L3_VSI_EXT_IPV6_SG_SVLAN_EN_LEN     1
+	#define L3_VSI_EXT_IPV6_SG_SVLAN_EN_DEFAULT 0x0
+	/*[field] IPV6_SG_CVLAN_EN*/
+	#define L3_VSI_EXT_IPV6_SG_CVLAN_EN
+	#define L3_VSI_EXT_IPV6_SG_CVLAN_EN_OFFSET  13
+	#define L3_VSI_EXT_IPV6_SG_CVLAN_EN_LEN     1
+	#define L3_VSI_EXT_IPV6_SG_CVLAN_EN_DEFAULT 0x0
+	/*[field] IPV6_SRC_UNK_CMD*/
+	#define L3_VSI_EXT_IPV6_SRC_UNK_CMD
+	#define L3_VSI_EXT_IPV6_SRC_UNK_CMD_OFFSET  14
+	#define L3_VSI_EXT_IPV6_SRC_UNK_CMD_LEN     2
+	#define L3_VSI_EXT_IPV6_SRC_UNK_CMD_DEFAULT 0x0
+	/*[field] IP_ARP_SG_EN*/
+	#define L3_VSI_EXT_IP_ARP_SG_EN
+	#define L3_VSI_EXT_IP_ARP_SG_EN_OFFSET  16
+	#define L3_VSI_EXT_IP_ARP_SG_EN_LEN     1
+	#define L3_VSI_EXT_IP_ARP_SG_EN_DEFAULT 0x0
+	/*[field] IP_ARP_SG_VIO_CMD*/
+	#define L3_VSI_EXT_IP_ARP_SG_VIO_CMD
+	#define L3_VSI_EXT_IP_ARP_SG_VIO_CMD_OFFSET  17
+	#define L3_VSI_EXT_IP_ARP_SG_VIO_CMD_LEN     2
+	#define L3_VSI_EXT_IP_ARP_SG_VIO_CMD_DEFAULT 0x0
+	/*[field] IP_ARP_SG_PORT_EN*/
+	#define L3_VSI_EXT_IP_ARP_SG_PORT_EN
+	#define L3_VSI_EXT_IP_ARP_SG_PORT_EN_OFFSET  19
+	#define L3_VSI_EXT_IP_ARP_SG_PORT_EN_LEN     1
+	#define L3_VSI_EXT_IP_ARP_SG_PORT_EN_DEFAULT 0x0
+	/*[field] IP_ARP_SG_SVLAN_EN*/
+	#define L3_VSI_EXT_IP_ARP_SG_SVLAN_EN
+	#define L3_VSI_EXT_IP_ARP_SG_SVLAN_EN_OFFSET  20
+	#define L3_VSI_EXT_IP_ARP_SG_SVLAN_EN_LEN     1
+	#define L3_VSI_EXT_IP_ARP_SG_SVLAN_EN_DEFAULT 0x0
+	/*[field] IP_ARP_SG_CVLAN_EN*/
+	#define L3_VSI_EXT_IP_ARP_SG_CVLAN_EN
+	#define L3_VSI_EXT_IP_ARP_SG_CVLAN_EN_OFFSET  21
+	#define L3_VSI_EXT_IP_ARP_SG_CVLAN_EN_LEN     1
+	#define L3_VSI_EXT_IP_ARP_SG_CVLAN_EN_DEFAULT 0x0
+	/*[field] IP_ARP_SRC_UNK_CMD*/
+	#define L3_VSI_EXT_IP_ARP_SRC_UNK_CMD
+	#define L3_VSI_EXT_IP_ARP_SRC_UNK_CMD_OFFSET  22
+	#define L3_VSI_EXT_IP_ARP_SRC_UNK_CMD_LEN     2
+	#define L3_VSI_EXT_IP_ARP_SRC_UNK_CMD_DEFAULT 0x0
+	/*[field] IP_ND_SG_EN*/
+	#define L3_VSI_EXT_IP_ND_SG_EN
+	#define L3_VSI_EXT_IP_ND_SG_EN_OFFSET  24
+	#define L3_VSI_EXT_IP_ND_SG_EN_LEN     1
+	#define L3_VSI_EXT_IP_ND_SG_EN_DEFAULT 0x0
+	/*[field] IP_ND_SG_VIO_CMD*/
+	#define L3_VSI_EXT_IP_ND_SG_VIO_CMD
+	#define L3_VSI_EXT_IP_ND_SG_VIO_CMD_OFFSET  25
+	#define L3_VSI_EXT_IP_ND_SG_VIO_CMD_LEN     2
+	#define L3_VSI_EXT_IP_ND_SG_VIO_CMD_DEFAULT 0x0
+	/*[field] IP_ND_SG_PORT_EN*/
+	#define L3_VSI_EXT_IP_ND_SG_PORT_EN
+	#define L3_VSI_EXT_IP_ND_SG_PORT_EN_OFFSET  27
+	#define L3_VSI_EXT_IP_ND_SG_PORT_EN_LEN     1
+	#define L3_VSI_EXT_IP_ND_SG_PORT_EN_DEFAULT 0x0
+	/*[field] IP_ND_SG_SVLAN_EN*/
+	#define L3_VSI_EXT_IP_ND_SG_SVLAN_EN
+	#define L3_VSI_EXT_IP_ND_SG_SVLAN_EN_OFFSET  28
+	#define L3_VSI_EXT_IP_ND_SG_SVLAN_EN_LEN     1
+	#define L3_VSI_EXT_IP_ND_SG_SVLAN_EN_DEFAULT 0x0
+	/*[field] IP_ND_SG_CVLAN_EN*/
+	#define L3_VSI_EXT_IP_ND_SG_CVLAN_EN
+	#define L3_VSI_EXT_IP_ND_SG_CVLAN_EN_OFFSET  29
+	#define L3_VSI_EXT_IP_ND_SG_CVLAN_EN_LEN     1
+	#define L3_VSI_EXT_IP_ND_SG_CVLAN_EN_DEFAULT 0x0
+	/*[field] IP_ND_SRC_UNK_CMD*/
+	#define L3_VSI_EXT_IP_ND_SRC_UNK_CMD
+	#define L3_VSI_EXT_IP_ND_SRC_UNK_CMD_OFFSET  30
+	#define L3_VSI_EXT_IP_ND_SRC_UNK_CMD_LEN     2
+	#define L3_VSI_EXT_IP_ND_SRC_UNK_CMD_DEFAULT 0x0
+
+struct l3_vsi_ext {
+	a_uint32_t  ipv4_sg_en:1;
+	a_uint32_t  ipv4_sg_vio_cmd:2;
+	a_uint32_t  ipv4_sg_port_en:1;
+	a_uint32_t  ipv4_sg_svlan_en:1;
+	a_uint32_t  ipv4_sg_cvlan_en:1;
+	a_uint32_t  ipv4_src_unk_cmd:2;
+	a_uint32_t  ipv6_sg_en:1;
+	a_uint32_t  ipv6_sg_vio_cmd:2;
+	a_uint32_t  ipv6_sg_port_en:1;
+	a_uint32_t  ipv6_sg_svlan_en:1;
+	a_uint32_t  ipv6_sg_cvlan_en:1;
+	a_uint32_t  ipv6_src_unk_cmd:2;
+	a_uint32_t  ip_arp_sg_en:1;
+	a_uint32_t  ip_arp_sg_vio_cmd:2;
+	a_uint32_t  ip_arp_sg_port_en:1;
+	a_uint32_t  ip_arp_sg_svlan_en:1;
+	a_uint32_t  ip_arp_sg_cvlan_en:1;
+	a_uint32_t  ip_arp_src_unk_cmd:2;
+	a_uint32_t  ip_nd_sg_en:1;
+	a_uint32_t  ip_nd_sg_vio_cmd:2;
+	a_uint32_t  ip_nd_sg_port_en:1;
+	a_uint32_t  ip_nd_sg_svlan_en:1;
+	a_uint32_t  ip_nd_sg_cvlan_en:1;
+	a_uint32_t  ip_nd_src_unk_cmd:2;
+};
+
+union l3_vsi_ext_u {
+	a_uint32_t val;
+	struct l3_vsi_ext bf;
+};
+
+/*[register] NETWORK_ROUTE_IP*/
+#define NETWORK_ROUTE_IP
+#define NETWORK_ROUTE_IP_ADDRESS 0x140
+#define NETWORK_ROUTE_IP_NUM     32
+#define NETWORK_ROUTE_IP_INC     0x8
+#define NETWORK_ROUTE_IP_TYPE    REG_TYPE_RW
+#define NETWORK_ROUTE_IP_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define NETWORK_ROUTE_IP_IP_ADDR
+	#define NETWORK_ROUTE_IP_IP_ADDR_OFFSET  0
+	#define NETWORK_ROUTE_IP_IP_ADDR_LEN     32
+	#define NETWORK_ROUTE_IP_IP_ADDR_DEFAULT 0x0
+	/*[field] IP_ADDR_MASK*/
+	#define NETWORK_ROUTE_IP_IP_ADDR_MASK
+	#define NETWORK_ROUTE_IP_IP_ADDR_MASK_OFFSET  32
+	#define NETWORK_ROUTE_IP_IP_ADDR_MASK_LEN     32
+	#define NETWORK_ROUTE_IP_IP_ADDR_MASK_DEFAULT 0x0
+
+struct network_route_ip {
+	a_uint32_t  ip_addr:32;
+	a_uint32_t  ip_addr_mask:32;
+};
+
+union network_route_ip_u {
+	a_uint32_t val[2];
+	struct network_route_ip bf;
+};
+
+/*[register] NETWORK_ROUTE_IP_EXT*/
+#define NETWORK_ROUTE_IP_EXT
+#define NETWORK_ROUTE_IP_EXT_ADDRESS 0x240
+#define NETWORK_ROUTE_IP_EXT_NUM     32
+#define NETWORK_ROUTE_IP_EXT_INC     0x4
+#define NETWORK_ROUTE_IP_EXT_TYPE    REG_TYPE_RW
+#define NETWORK_ROUTE_IP_EXT_DEFAULT 0x0
+	/*[field] VALID*/
+	#define NETWORK_ROUTE_IP_EXT_VALID
+	#define NETWORK_ROUTE_IP_EXT_VALID_OFFSET  0
+	#define NETWORK_ROUTE_IP_EXT_VALID_LEN     1
+	#define NETWORK_ROUTE_IP_EXT_VALID_DEFAULT 0x0
+	/*[field] ENTRY_TYPE*/
+	#define NETWORK_ROUTE_IP_EXT_ENTRY_TYPE
+	#define NETWORK_ROUTE_IP_EXT_ENTRY_TYPE_OFFSET  1
+	#define NETWORK_ROUTE_IP_EXT_ENTRY_TYPE_LEN     1
+	#define NETWORK_ROUTE_IP_EXT_ENTRY_TYPE_DEFAULT 0x0
+
+struct network_route_ip_ext {
+	a_uint32_t  valid:1;
+	a_uint32_t  entry_type:1;
+	a_uint32_t  _reserved0:30;
+};
+
+union network_route_ip_ext_u {
+	a_uint32_t val;
+	struct network_route_ip_ext bf;
+};
+
+/*[register] NETWORK_ROUTE_ACTION*/
+#define NETWORK_ROUTE_ACTION
+#define NETWORK_ROUTE_ACTION_ADDRESS 0x2c0
+#define NETWORK_ROUTE_ACTION_NUM     32
+#define NETWORK_ROUTE_ACTION_INC     0x4
+#define NETWORK_ROUTE_ACTION_TYPE    REG_TYPE_RW
+#define NETWORK_ROUTE_ACTION_DEFAULT 0x0
+	/*[field] FWD_CMD*/
+	#define NETWORK_ROUTE_ACTION_FWD_CMD
+	#define NETWORK_ROUTE_ACTION_FWD_CMD_OFFSET  0
+	#define NETWORK_ROUTE_ACTION_FWD_CMD_LEN     2
+	#define NETWORK_ROUTE_ACTION_FWD_CMD_DEFAULT 0x0
+	/*[field] DST_INFO*/
+	#define NETWORK_ROUTE_ACTION_DST_INFO
+	#define NETWORK_ROUTE_ACTION_DST_INFO_OFFSET  2
+	#define NETWORK_ROUTE_ACTION_DST_INFO_LEN     14
+	#define NETWORK_ROUTE_ACTION_DST_INFO_DEFAULT 0x0
+	/*[field] LAN_WAN*/
+	#define NETWORK_ROUTE_ACTION_LAN_WAN
+	#define NETWORK_ROUTE_ACTION_LAN_WAN_OFFSET  16
+	#define NETWORK_ROUTE_ACTION_LAN_WAN_LEN     1
+	#define NETWORK_ROUTE_ACTION_LAN_WAN_DEFAULT 0x0
+
+struct network_route_action {
+	a_uint32_t  fwd_cmd:2;
+	a_uint32_t  dst_info:14;
+	a_uint32_t  lan_wan:1;
+	a_uint32_t  _reserved0:15;
+};
+
+union network_route_action_u {
+	a_uint32_t val;
+	struct network_route_action bf;
+};
+
+/*[register] L3_ROUTE_CTRL*/
+#define L3_ROUTE_CTRL
+#define L3_ROUTE_CTRL_ADDRESS 0x340
+#define L3_ROUTE_CTRL_NUM     1
+#define L3_ROUTE_CTRL_INC     0x4
+#define L3_ROUTE_CTRL_TYPE    REG_TYPE_RW
+#define L3_ROUTE_CTRL_DEFAULT 0xdbc36db
+	/*[field] IP_MRU_CHECK_FAIL*/
+	#define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL
+	#define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL_OFFSET  0
+	#define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL_LEN     2
+	#define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL_DEFAULT 0x3
+	/*[field] IP_MRU_CHECK_FAIL_DE_ACCE*/
+	#define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL_DE_ACCE
+	#define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL_DE_ACCE_OFFSET  2
+	#define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL_DE_ACCE_LEN     1
+	#define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL_DE_ACCE_DEFAULT 0x0
+	/*[field] IP_MTU_FAIL*/
+	#define L3_ROUTE_CTRL_IP_MTU_FAIL
+	#define L3_ROUTE_CTRL_IP_MTU_FAIL_OFFSET  3
+	#define L3_ROUTE_CTRL_IP_MTU_FAIL_LEN     2
+	#define L3_ROUTE_CTRL_IP_MTU_FAIL_DEFAULT 0x3
+	/*[field] IP_MTU_FAIL_DE_ACCE*/
+	#define L3_ROUTE_CTRL_IP_MTU_FAIL_DE_ACCE
+	#define L3_ROUTE_CTRL_IP_MTU_FAIL_DE_ACCE_OFFSET  5
+	#define L3_ROUTE_CTRL_IP_MTU_FAIL_DE_ACCE_LEN     1
+	#define L3_ROUTE_CTRL_IP_MTU_FAIL_DE_ACCE_DEFAULT 0x0
+	/*[field] IP_MTU_DF_FAIL*/
+	#define L3_ROUTE_CTRL_IP_MTU_DF_FAIL
+	#define L3_ROUTE_CTRL_IP_MTU_DF_FAIL_OFFSET  6
+	#define L3_ROUTE_CTRL_IP_MTU_DF_FAIL_LEN     2
+	#define L3_ROUTE_CTRL_IP_MTU_DF_FAIL_DEFAULT 0x3
+	/*[field] IP_MTU_DF_FAIL_DE_ACCE*/
+	#define L3_ROUTE_CTRL_IP_MTU_DF_FAIL_DE_ACCE
+	#define L3_ROUTE_CTRL_IP_MTU_DF_FAIL_DE_ACCE_OFFSET  8
+	#define L3_ROUTE_CTRL_IP_MTU_DF_FAIL_DE_ACCE_LEN     1
+	#define L3_ROUTE_CTRL_IP_MTU_DF_FAIL_DE_ACCE_DEFAULT 0x0
+	/*[field] IP_PREFIX_BC_CMD*/
+	#define L3_ROUTE_CTRL_IP_PREFIX_BC_CMD
+	#define L3_ROUTE_CTRL_IP_PREFIX_BC_CMD_OFFSET  9
+	#define L3_ROUTE_CTRL_IP_PREFIX_BC_CMD_LEN     2
+	#define L3_ROUTE_CTRL_IP_PREFIX_BC_CMD_DEFAULT 0x3
+	/*[field] IP_PREFIX_BC_DE_ACCE*/
+	#define L3_ROUTE_CTRL_IP_PREFIX_BC_DE_ACCE
+	#define L3_ROUTE_CTRL_IP_PREFIX_BC_DE_ACCE_OFFSET  11
+	#define L3_ROUTE_CTRL_IP_PREFIX_BC_DE_ACCE_LEN     1
+	#define L3_ROUTE_CTRL_IP_PREFIX_BC_DE_ACCE_DEFAULT 0x0
+	/*[field] FLOW_SRC_IF_CHECK_CMD*/
+	#define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_CMD
+	#define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_CMD_OFFSET  12
+	#define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_CMD_LEN     2
+	#define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_CMD_DEFAULT 0x3
+	/*[field] FLOW_SRC_IF_CHECK_DE_ACCE*/
+	#define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_DE_ACCE
+	#define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_DE_ACCE_OFFSET  14
+	#define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_DE_ACCE_LEN     1
+	#define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_DE_ACCE_DEFAULT 0x0
+	/*[field] FLOW_SERVICE_CODE_LOOP*/
+	#define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP
+	#define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP_OFFSET  15
+	#define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP_LEN     2
+	#define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP_DEFAULT 0x0
+	/*[field] FLOW_SERVICE_CODE_LOOP_DE_ACCE*/
+	#define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP_DE_ACCE
+	#define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP_DE_ACCE_OFFSET  17
+	#define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP_DE_ACCE_LEN     1
+	#define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP_DE_ACCE_DEFAULT 0x0
+	/*[field] FLOW_DE_ACCE_CMD*/
+	#define L3_ROUTE_CTRL_FLOW_DE_ACCE_CMD
+	#define L3_ROUTE_CTRL_FLOW_DE_ACCE_CMD_OFFSET  18
+	#define L3_ROUTE_CTRL_FLOW_DE_ACCE_CMD_LEN     2
+	#define L3_ROUTE_CTRL_FLOW_DE_ACCE_CMD_DEFAULT 0x3
+	/*[field] FLOW_SYNC_MISMATCH_CMD*/
+	#define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_CMD
+	#define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_CMD_OFFSET  20
+	#define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_CMD_LEN     2
+	#define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_CMD_DEFAULT 0x3
+	/*[field] FLOW_SYNC_MISMATCH_DE_ACCE*/
+	#define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_DE_ACCE
+	#define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_DE_ACCE_OFFSET  22
+	#define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_DE_ACCE_LEN     1
+	#define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_DE_ACCE_DEFAULT 0x0
+	/*[field] ICMP_RDT_CMD*/
+	#define L3_ROUTE_CTRL_ICMP_RDT_CMD
+	#define L3_ROUTE_CTRL_ICMP_RDT_CMD_OFFSET  23
+	#define L3_ROUTE_CTRL_ICMP_RDT_CMD_LEN     2
+	#define L3_ROUTE_CTRL_ICMP_RDT_CMD_DEFAULT 0x3
+	/*[field] ICMP_RDT_DE_ACCE*/
+	#define L3_ROUTE_CTRL_ICMP_RDT_DE_ACCE
+	#define L3_ROUTE_CTRL_ICMP_RDT_DE_ACCE_OFFSET  25
+	#define L3_ROUTE_CTRL_ICMP_RDT_DE_ACCE_LEN     1
+	#define L3_ROUTE_CTRL_ICMP_RDT_DE_ACCE_DEFAULT 0x0
+	/*[field] PPPOE_MULTICAST_CMD*/
+	#define L3_ROUTE_CTRL_PPPOE_MULTICAST_CMD
+	#define L3_ROUTE_CTRL_PPPOE_MULTICAST_CMD_OFFSET  26
+	#define L3_ROUTE_CTRL_PPPOE_MULTICAST_CMD_LEN     2
+	#define L3_ROUTE_CTRL_PPPOE_MULTICAST_CMD_DEFAULT 0x3
+	/*[field] PPPOE_MULTICAST_DE_ACCE*/
+	#define L3_ROUTE_CTRL_PPPOE_MULTICAST_DE_ACCE
+	#define L3_ROUTE_CTRL_PPPOE_MULTICAST_DE_ACCE_OFFSET  28
+	#define L3_ROUTE_CTRL_PPPOE_MULTICAST_DE_ACCE_LEN     1
+	#define L3_ROUTE_CTRL_PPPOE_MULTICAST_DE_ACCE_DEFAULT 0x0
+
+struct l3_route_ctrl {
+	a_uint32_t  ip_mru_check_fail:2;
+	a_uint32_t  ip_mru_check_fail_de_acce:1;
+	a_uint32_t  ip_mtu_fail:2;
+	a_uint32_t  ip_mtu_fail_de_acce:1;
+	a_uint32_t  ip_mtu_df_fail:2;
+	a_uint32_t  ip_mtu_df_fail_de_acce:1;
+	a_uint32_t  ip_prefix_bc_cmd:2;
+	a_uint32_t  ip_prefix_bc_de_acce:1;
+	a_uint32_t  flow_src_if_check_cmd:2;
+	a_uint32_t  flow_src_if_check_de_acce:1;
+	a_uint32_t  flow_service_code_loop:2;
+	a_uint32_t  flow_service_code_loop_de_acce:1;
+	a_uint32_t  flow_de_acce_cmd:2;
+	a_uint32_t  flow_sync_mismatch_cmd:2;
+	a_uint32_t  flow_sync_mismatch_de_acce:1;
+	a_uint32_t  icmp_rdt_cmd:2;
+	a_uint32_t  icmp_rdt_de_acce:1;
+	a_uint32_t  pppoe_multicast_cmd:2;
+	a_uint32_t  pppoe_multicast_de_acce:1;
+	a_uint32_t  _reserved0:3;
+};
+
+union l3_route_ctrl_u {
+	a_uint32_t val;
+	struct l3_route_ctrl bf;
+};
+
+/*[register] L3_ROUTE_CTRL_EXT*/
+#define L3_ROUTE_CTRL_EXT
+#define L3_ROUTE_CTRL_EXT_ADDRESS 0x344
+#define L3_ROUTE_CTRL_EXT_NUM     1
+#define L3_ROUTE_CTRL_EXT_INC     0x4
+#define L3_ROUTE_CTRL_EXT_TYPE    REG_TYPE_RW
+#define L3_ROUTE_CTRL_EXT_DEFAULT 0x23
+	/*[field] IP_ROUTE_MISMATCH*/
+	#define L3_ROUTE_CTRL_EXT_IP_ROUTE_MISMATCH
+	#define L3_ROUTE_CTRL_EXT_IP_ROUTE_MISMATCH_OFFSET  0
+	#define L3_ROUTE_CTRL_EXT_IP_ROUTE_MISMATCH_LEN     2
+	#define L3_ROUTE_CTRL_EXT_IP_ROUTE_MISMATCH_DEFAULT 0x3
+	/*[field] FLOW_SERVICE_CODE_LOOP_EN*/
+	#define L3_ROUTE_CTRL_EXT_FLOW_SERVICE_CODE_LOOP_EN
+	#define L3_ROUTE_CTRL_EXT_FLOW_SERVICE_CODE_LOOP_EN_OFFSET  2
+	#define L3_ROUTE_CTRL_EXT_FLOW_SERVICE_CODE_LOOP_EN_LEN     1
+	#define L3_ROUTE_CTRL_EXT_FLOW_SERVICE_CODE_LOOP_EN_DEFAULT 0x0
+	/*[field] HOST_HASH_MODE_0*/
+	#define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_0
+	#define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_0_OFFSET  3
+	#define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_0_LEN     2
+	#define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_0_DEFAULT 0x0
+	/*[field] HOST_HASH_MODE_1*/
+	#define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_1
+	#define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_1_OFFSET  5
+	#define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_1_LEN     2
+	#define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_1_DEFAULT 0x1
+
+struct l3_route_ctrl_ext {
+	a_uint32_t  ip_route_mismatch:2;
+	a_uint32_t  flow_service_code_loop_en:1;
+	a_uint32_t  host_hash_mode_0:2;
+	a_uint32_t  host_hash_mode_1:2;
+	a_uint32_t  l3_flow_copy_escape:1;
+	a_uint32_t  _reserved0:24;
+};
+
+union l3_route_ctrl_ext_u {
+	a_uint32_t val;
+	struct l3_route_ctrl_ext bf;
+};
+
+/*[register] HOST_TBL_OP*/
+#define HOST_TBL_OP
+#define HOST_TBL_OP_ADDRESS 0x4bc
+#define HOST_TBL_OP_NUM     1
+#define HOST_TBL_OP_INC     0x4
+#define HOST_TBL_OP_TYPE    REG_TYPE_RW
+#define HOST_TBL_OP_DEFAULT 0x0
+	/*[field] CMD_ID*/
+	#define HOST_TBL_OP_CMD_ID
+	#define HOST_TBL_OP_CMD_ID_OFFSET  0
+	#define HOST_TBL_OP_CMD_ID_LEN     4
+	#define HOST_TBL_OP_CMD_ID_DEFAULT 0x0
+	/*[field] BYP_RSLT_EN*/
+	#define HOST_TBL_OP_BYP_RSLT_EN
+	#define HOST_TBL_OP_BYP_RSLT_EN_OFFSET  4
+	#define HOST_TBL_OP_BYP_RSLT_EN_LEN     1
+	#define HOST_TBL_OP_BYP_RSLT_EN_DEFAULT 0x0
+	/*[field] OP_TYPE*/
+	#define HOST_TBL_OP_OP_TYPE
+	#define HOST_TBL_OP_OP_TYPE_OFFSET  5
+	#define HOST_TBL_OP_OP_TYPE_LEN     3
+	#define HOST_TBL_OP_OP_TYPE_DEFAULT 0x0
+	/*[field] HASH_BLOCK_BITMAP*/
+	#define HOST_TBL_OP_HASH_BLOCK_BITMAP
+	#define HOST_TBL_OP_HASH_BLOCK_BITMAP_OFFSET  8
+	#define HOST_TBL_OP_HASH_BLOCK_BITMAP_LEN     2
+	#define HOST_TBL_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0
+	/*[field] OP_MODE*/
+	#define HOST_TBL_OP_OP_MODE
+	#define HOST_TBL_OP_OP_MODE_OFFSET  10
+	#define HOST_TBL_OP_OP_MODE_LEN     1
+	#define HOST_TBL_OP_OP_MODE_DEFAULT 0x0
+	/*[field] ENTRY_INDEX*/
+	#define HOST_TBL_OP_ENTRY_INDEX
+	#define HOST_TBL_OP_ENTRY_INDEX_OFFSET  11
+	#define HOST_TBL_OP_ENTRY_INDEX_LEN     13
+	#define HOST_TBL_OP_ENTRY_INDEX_DEFAULT 0x0
+	/*[field] OP_RESULT*/
+	#define HOST_TBL_OP_OP_RESULT
+	#define HOST_TBL_OP_OP_RESULT_OFFSET  24
+	#define HOST_TBL_OP_OP_RESULT_LEN     1
+	#define HOST_TBL_OP_OP_RESULT_DEFAULT 0x0
+	/*[field] BUSY*/
+	#define HOST_TBL_OP_BUSY
+	#define HOST_TBL_OP_BUSY_OFFSET  25
+	#define HOST_TBL_OP_BUSY_LEN     1
+	#define HOST_TBL_OP_BUSY_DEFAULT 0x0
+
+struct host_tbl_op {
+	a_uint32_t  cmd_id:4;
+	a_uint32_t  byp_rslt_en:1;
+	a_uint32_t  op_type:3;
+	a_uint32_t  hash_block_bitmap:2;
+	a_uint32_t  op_mode:1;
+	a_uint32_t  entry_index:13;
+	a_uint32_t  op_result:1;
+	a_uint32_t  busy:1;
+	a_uint32_t  _reserved0:6;
+};
+
+union host_tbl_op_u {
+	a_uint32_t val;
+	struct host_tbl_op bf;
+};
+
+/*[register] HOST_TBL_OP_DATA0*/
+#define HOST_TBL_OP_DATA0
+#define HOST_TBL_OP_DATA0_ADDRESS 0x4c0
+#define HOST_TBL_OP_DATA0_NUM     1
+#define HOST_TBL_OP_DATA0_INC     0x4
+#define HOST_TBL_OP_DATA0_TYPE    REG_TYPE_RW
+#define HOST_TBL_OP_DATA0_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_OP_DATA0_DATA
+	#define HOST_TBL_OP_DATA0_DATA_OFFSET  0
+	#define HOST_TBL_OP_DATA0_DATA_LEN     32
+	#define HOST_TBL_OP_DATA0_DATA_DEFAULT 0x0
+
+struct host_tbl_op_data0 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_op_data0_u {
+	a_uint32_t val;
+	struct host_tbl_op_data0 bf;
+};
+
+/*[register] HOST_TBL_OP_DATA1*/
+#define HOST_TBL_OP_DATA1
+#define HOST_TBL_OP_DATA1_ADDRESS 0x4c4
+#define HOST_TBL_OP_DATA1_NUM     1
+#define HOST_TBL_OP_DATA1_INC     0x4
+#define HOST_TBL_OP_DATA1_TYPE    REG_TYPE_RW
+#define HOST_TBL_OP_DATA1_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_OP_DATA1_DATA
+	#define HOST_TBL_OP_DATA1_DATA_OFFSET  0
+	#define HOST_TBL_OP_DATA1_DATA_LEN     32
+	#define HOST_TBL_OP_DATA1_DATA_DEFAULT 0x0
+
+struct host_tbl_op_data1 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_op_data1_u {
+	a_uint32_t val;
+	struct host_tbl_op_data1 bf;
+};
+
+/*[register] HOST_TBL_OP_DATA2*/
+#define HOST_TBL_OP_DATA2
+#define HOST_TBL_OP_DATA2_ADDRESS 0x4c8
+#define HOST_TBL_OP_DATA2_NUM     1
+#define HOST_TBL_OP_DATA2_INC     0x4
+#define HOST_TBL_OP_DATA2_TYPE    REG_TYPE_RW
+#define HOST_TBL_OP_DATA2_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_OP_DATA2_DATA
+	#define HOST_TBL_OP_DATA2_DATA_OFFSET  0
+	#define HOST_TBL_OP_DATA2_DATA_LEN     32
+	#define HOST_TBL_OP_DATA2_DATA_DEFAULT 0x0
+
+struct host_tbl_op_data2 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_op_data2_u {
+	a_uint32_t val;
+	struct host_tbl_op_data2 bf;
+};
+
+/*[register] HOST_TBL_OP_DATA3*/
+#define HOST_TBL_OP_DATA3
+#define HOST_TBL_OP_DATA3_ADDRESS 0x4cc
+#define HOST_TBL_OP_DATA3_NUM     1
+#define HOST_TBL_OP_DATA3_INC     0x4
+#define HOST_TBL_OP_DATA3_TYPE    REG_TYPE_RW
+#define HOST_TBL_OP_DATA3_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_OP_DATA3_DATA
+	#define HOST_TBL_OP_DATA3_DATA_OFFSET  0
+	#define HOST_TBL_OP_DATA3_DATA_LEN     32
+	#define HOST_TBL_OP_DATA3_DATA_DEFAULT 0x0
+
+struct host_tbl_op_data3 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_op_data3_u {
+	a_uint32_t val;
+	struct host_tbl_op_data3 bf;
+};
+
+/*[register] HOST_TBL_OP_DATA4*/
+#define HOST_TBL_OP_DATA4
+#define HOST_TBL_OP_DATA4_ADDRESS 0x4d0
+#define HOST_TBL_OP_DATA4_NUM     1
+#define HOST_TBL_OP_DATA4_INC     0x4
+#define HOST_TBL_OP_DATA4_TYPE    REG_TYPE_RW
+#define HOST_TBL_OP_DATA4_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_OP_DATA4_DATA
+	#define HOST_TBL_OP_DATA4_DATA_OFFSET  0
+	#define HOST_TBL_OP_DATA4_DATA_LEN     32
+	#define HOST_TBL_OP_DATA4_DATA_DEFAULT 0x0
+
+struct host_tbl_op_data4 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_op_data4_u {
+	a_uint32_t val;
+	struct host_tbl_op_data4 bf;
+};
+
+/*[register] HOST_TBL_OP_DATA5*/
+#define HOST_TBL_OP_DATA5
+#define HOST_TBL_OP_DATA5_ADDRESS 0x4d4
+#define HOST_TBL_OP_DATA5_NUM     1
+#define HOST_TBL_OP_DATA5_INC     0x4
+#define HOST_TBL_OP_DATA5_TYPE    REG_TYPE_RW
+#define HOST_TBL_OP_DATA5_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_OP_DATA5_DATA
+	#define HOST_TBL_OP_DATA5_DATA_OFFSET  0
+	#define HOST_TBL_OP_DATA5_DATA_LEN     32
+	#define HOST_TBL_OP_DATA5_DATA_DEFAULT 0x0
+
+struct host_tbl_op_data5 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_op_data5_u {
+	a_uint32_t val;
+	struct host_tbl_op_data5 bf;
+};
+
+/*[register] HOST_TBL_OP_DATA6*/
+#define HOST_TBL_OP_DATA6
+#define HOST_TBL_OP_DATA6_ADDRESS 0x4d8
+#define HOST_TBL_OP_DATA6_NUM     1
+#define HOST_TBL_OP_DATA6_INC     0x4
+#define HOST_TBL_OP_DATA6_TYPE    REG_TYPE_RW
+#define HOST_TBL_OP_DATA6_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_OP_DATA6_DATA
+	#define HOST_TBL_OP_DATA6_DATA_OFFSET  0
+	#define HOST_TBL_OP_DATA6_DATA_LEN     32
+	#define HOST_TBL_OP_DATA6_DATA_DEFAULT 0x0
+
+struct host_tbl_op_data6 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_op_data6_u {
+	a_uint32_t val;
+	struct host_tbl_op_data6 bf;
+};
+
+/*[register] HOST_TBL_OP_DATA7*/
+#define HOST_TBL_OP_DATA7
+#define HOST_TBL_OP_DATA7_ADDRESS 0x4dc
+#define HOST_TBL_OP_DATA7_NUM     1
+#define HOST_TBL_OP_DATA7_INC     0x4
+#define HOST_TBL_OP_DATA7_TYPE    REG_TYPE_RW
+#define HOST_TBL_OP_DATA7_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_OP_DATA7_DATA
+	#define HOST_TBL_OP_DATA7_DATA_OFFSET  0
+	#define HOST_TBL_OP_DATA7_DATA_LEN     32
+	#define HOST_TBL_OP_DATA7_DATA_DEFAULT 0x0
+
+struct host_tbl_op_data7 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_op_data7_u {
+	a_uint32_t val;
+	struct host_tbl_op_data7 bf;
+};
+
+/*[register] HOST_TBL_OP_DATA8*/
+#define HOST_TBL_OP_DATA8
+#define HOST_TBL_OP_DATA8_ADDRESS 0x4e0
+#define HOST_TBL_OP_DATA8_NUM     1
+#define HOST_TBL_OP_DATA8_INC     0x4
+#define HOST_TBL_OP_DATA8_TYPE    REG_TYPE_RW
+#define HOST_TBL_OP_DATA8_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_OP_DATA8_DATA
+	#define HOST_TBL_OP_DATA8_DATA_OFFSET  0
+	#define HOST_TBL_OP_DATA8_DATA_LEN     32
+	#define HOST_TBL_OP_DATA8_DATA_DEFAULT 0x0
+
+struct host_tbl_op_data8 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_op_data8_u {
+	a_uint32_t val;
+	struct host_tbl_op_data8 bf;
+};
+
+/*[register] HOST_TBL_OP_DATA9*/
+#define HOST_TBL_OP_DATA9
+#define HOST_TBL_OP_DATA9_ADDRESS 0x4e4
+#define HOST_TBL_OP_DATA9_NUM     1
+#define HOST_TBL_OP_DATA9_INC     0x4
+#define HOST_TBL_OP_DATA9_TYPE    REG_TYPE_RW
+#define HOST_TBL_OP_DATA9_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_OP_DATA9_DATA
+	#define HOST_TBL_OP_DATA9_DATA_OFFSET  0
+	#define HOST_TBL_OP_DATA9_DATA_LEN     32
+	#define HOST_TBL_OP_DATA9_DATA_DEFAULT 0x0
+
+struct host_tbl_op_data9 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_op_data9_u {
+	a_uint32_t val;
+	struct host_tbl_op_data9 bf;
+};
+
+/*[register] HOST_TBL_OP_RSLT*/
+#define HOST_TBL_OP_RSLT
+#define HOST_TBL_OP_RSLT_ADDRESS 0x4e8
+#define HOST_TBL_OP_RSLT_NUM     1
+#define HOST_TBL_OP_RSLT_INC     0x4
+#define HOST_TBL_OP_RSLT_TYPE    REG_TYPE_RO
+#define HOST_TBL_OP_RSLT_DEFAULT 0x0
+	/*[field] CMD_ID*/
+	#define HOST_TBL_OP_RSLT_CMD_ID
+	#define HOST_TBL_OP_RSLT_CMD_ID_OFFSET  0
+	#define HOST_TBL_OP_RSLT_CMD_ID_LEN     4
+	#define HOST_TBL_OP_RSLT_CMD_ID_DEFAULT 0x0
+	/*[field] OP_RSLT*/
+	#define HOST_TBL_OP_RSLT_OP_RSLT
+	#define HOST_TBL_OP_RSLT_OP_RSLT_OFFSET  4
+	#define HOST_TBL_OP_RSLT_OP_RSLT_LEN     1
+	#define HOST_TBL_OP_RSLT_OP_RSLT_DEFAULT 0x0
+	/*[field] ENTRY_INDEX*/
+	#define HOST_TBL_OP_RSLT_ENTRY_INDEX
+	#define HOST_TBL_OP_RSLT_ENTRY_INDEX_OFFSET  5
+	#define HOST_TBL_OP_RSLT_ENTRY_INDEX_LEN     13
+	#define HOST_TBL_OP_RSLT_ENTRY_INDEX_DEFAULT 0x0
+	/*[field] VALID_CNT*/
+	#define HOST_TBL_OP_RSLT_VALID_CNT
+	#define HOST_TBL_OP_RSLT_VALID_CNT_OFFSET  18
+	#define HOST_TBL_OP_RSLT_VALID_CNT_LEN     4
+	#define HOST_TBL_OP_RSLT_VALID_CNT_DEFAULT 0x0
+
+struct host_tbl_op_rslt {
+	a_uint32_t  cmd_id:4;
+	a_uint32_t  op_rslt:1;
+	a_uint32_t  entry_index:13;
+	a_uint32_t  valid_cnt:4;
+	a_uint32_t  _reserved0:10;
+};
+
+union host_tbl_op_rslt_u {
+	a_uint32_t val;
+	struct host_tbl_op_rslt bf;
+};
+
+/*[register] HOST_TBL_RD_OP*/
+#define HOST_TBL_RD_OP
+#define HOST_TBL_RD_OP_ADDRESS 0x4ec
+#define HOST_TBL_RD_OP_NUM     1
+#define HOST_TBL_RD_OP_INC     0x4
+#define HOST_TBL_RD_OP_TYPE    REG_TYPE_RW
+#define HOST_TBL_RD_OP_DEFAULT 0x0
+	/*[field] CMD_ID*/
+	#define HOST_TBL_RD_OP_CMD_ID
+	#define HOST_TBL_RD_OP_CMD_ID_OFFSET  0
+	#define HOST_TBL_RD_OP_CMD_ID_LEN     4
+	#define HOST_TBL_RD_OP_CMD_ID_DEFAULT 0x0
+	/*[field] BYP_RSLT_EN*/
+	#define HOST_TBL_RD_OP_BYP_RSLT_EN
+	#define HOST_TBL_RD_OP_BYP_RSLT_EN_OFFSET  4
+	#define HOST_TBL_RD_OP_BYP_RSLT_EN_LEN     1
+	#define HOST_TBL_RD_OP_BYP_RSLT_EN_DEFAULT 0x0
+	/*[field] OP_TYPE*/
+	#define HOST_TBL_RD_OP_OP_TYPE
+	#define HOST_TBL_RD_OP_OP_TYPE_OFFSET  5
+	#define HOST_TBL_RD_OP_OP_TYPE_LEN     3
+	#define HOST_TBL_RD_OP_OP_TYPE_DEFAULT 0x0
+	/*[field] HASH_BLOCK_BITMAP*/
+	#define HOST_TBL_RD_OP_HASH_BLOCK_BITMAP
+	#define HOST_TBL_RD_OP_HASH_BLOCK_BITMAP_OFFSET  8
+	#define HOST_TBL_RD_OP_HASH_BLOCK_BITMAP_LEN     2
+	#define HOST_TBL_RD_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0
+	/*[field] OP_MODE*/
+	#define HOST_TBL_RD_OP_OP_MODE
+	#define HOST_TBL_RD_OP_OP_MODE_OFFSET  10
+	#define HOST_TBL_RD_OP_OP_MODE_LEN     1
+	#define HOST_TBL_RD_OP_OP_MODE_DEFAULT 0x0
+	/*[field] ENTRY_INDEX*/
+	#define HOST_TBL_RD_OP_ENTRY_INDEX
+	#define HOST_TBL_RD_OP_ENTRY_INDEX_OFFSET  11
+	#define HOST_TBL_RD_OP_ENTRY_INDEX_LEN     13
+	#define HOST_TBL_RD_OP_ENTRY_INDEX_DEFAULT 0x0
+	/*[field] OP_RESULT*/
+	#define HOST_TBL_RD_OP_OP_RESULT
+	#define HOST_TBL_RD_OP_OP_RESULT_OFFSET  24
+	#define HOST_TBL_RD_OP_OP_RESULT_LEN     1
+	#define HOST_TBL_RD_OP_OP_RESULT_DEFAULT 0x0
+	/*[field] BUSY*/
+	#define HOST_TBL_RD_OP_BUSY
+	#define HOST_TBL_RD_OP_BUSY_OFFSET  25
+	#define HOST_TBL_RD_OP_BUSY_LEN     1
+	#define HOST_TBL_RD_OP_BUSY_DEFAULT 0x0
+
+struct host_tbl_rd_op {
+	a_uint32_t  cmd_id:4;
+	a_uint32_t  byp_rslt_en:1;
+	a_uint32_t  op_type:3;
+	a_uint32_t  hash_block_bitmap:2;
+	a_uint32_t  op_mode:1;
+	a_uint32_t  entry_index:13;
+	a_uint32_t  op_result:1;
+	a_uint32_t  busy:1;
+	a_uint32_t  _reserved0:6;
+};
+
+union host_tbl_rd_op_u {
+	a_uint32_t val;
+	struct host_tbl_rd_op bf;
+};
+
+/*[register] HOST_TBL_RD_OP_DATA0*/
+#define HOST_TBL_RD_OP_DATA0
+#define HOST_TBL_RD_OP_DATA0_ADDRESS 0x4f0
+#define HOST_TBL_RD_OP_DATA0_NUM     1
+#define HOST_TBL_RD_OP_DATA0_INC     0x4
+#define HOST_TBL_RD_OP_DATA0_TYPE    REG_TYPE_RW
+#define HOST_TBL_RD_OP_DATA0_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_OP_DATA0_DATA
+	#define HOST_TBL_RD_OP_DATA0_DATA_OFFSET  0
+	#define HOST_TBL_RD_OP_DATA0_DATA_LEN     32
+	#define HOST_TBL_RD_OP_DATA0_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_op_data0 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_op_data0_u {
+	a_uint32_t val;
+	struct host_tbl_rd_op_data0 bf;
+};
+
+/*[register] HOST_TBL_RD_OP_DATA1*/
+#define HOST_TBL_RD_OP_DATA1
+#define HOST_TBL_RD_OP_DATA1_ADDRESS 0x4f4
+#define HOST_TBL_RD_OP_DATA1_NUM     1
+#define HOST_TBL_RD_OP_DATA1_INC     0x4
+#define HOST_TBL_RD_OP_DATA1_TYPE    REG_TYPE_RW
+#define HOST_TBL_RD_OP_DATA1_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_OP_DATA1_DATA
+	#define HOST_TBL_RD_OP_DATA1_DATA_OFFSET  0
+	#define HOST_TBL_RD_OP_DATA1_DATA_LEN     32
+	#define HOST_TBL_RD_OP_DATA1_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_op_data1 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_op_data1_u {
+	a_uint32_t val;
+	struct host_tbl_rd_op_data1 bf;
+};
+
+/*[register] HOST_TBL_RD_OP_DATA2*/
+#define HOST_TBL_RD_OP_DATA2
+#define HOST_TBL_RD_OP_DATA2_ADDRESS 0x4f8
+#define HOST_TBL_RD_OP_DATA2_NUM     1
+#define HOST_TBL_RD_OP_DATA2_INC     0x4
+#define HOST_TBL_RD_OP_DATA2_TYPE    REG_TYPE_RW
+#define HOST_TBL_RD_OP_DATA2_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_OP_DATA2_DATA
+	#define HOST_TBL_RD_OP_DATA2_DATA_OFFSET  0
+	#define HOST_TBL_RD_OP_DATA2_DATA_LEN     32
+	#define HOST_TBL_RD_OP_DATA2_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_op_data2 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_op_data2_u {
+	a_uint32_t val;
+	struct host_tbl_rd_op_data2 bf;
+};
+
+/*[register] HOST_TBL_RD_OP_DATA3*/
+#define HOST_TBL_RD_OP_DATA3
+#define HOST_TBL_RD_OP_DATA3_ADDRESS 0x4fc
+#define HOST_TBL_RD_OP_DATA3_NUM     1
+#define HOST_TBL_RD_OP_DATA3_INC     0x4
+#define HOST_TBL_RD_OP_DATA3_TYPE    REG_TYPE_RW
+#define HOST_TBL_RD_OP_DATA3_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_OP_DATA3_DATA
+	#define HOST_TBL_RD_OP_DATA3_DATA_OFFSET  0
+	#define HOST_TBL_RD_OP_DATA3_DATA_LEN     32
+	#define HOST_TBL_RD_OP_DATA3_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_op_data3 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_op_data3_u {
+	a_uint32_t val;
+	struct host_tbl_rd_op_data3 bf;
+};
+
+/*[register] HOST_TBL_RD_OP_DATA4*/
+#define HOST_TBL_RD_OP_DATA4
+#define HOST_TBL_RD_OP_DATA4_ADDRESS 0x500
+#define HOST_TBL_RD_OP_DATA4_NUM     1
+#define HOST_TBL_RD_OP_DATA4_INC     0x4
+#define HOST_TBL_RD_OP_DATA4_TYPE    REG_TYPE_RW
+#define HOST_TBL_RD_OP_DATA4_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_OP_DATA4_DATA
+	#define HOST_TBL_RD_OP_DATA4_DATA_OFFSET  0
+	#define HOST_TBL_RD_OP_DATA4_DATA_LEN     32
+	#define HOST_TBL_RD_OP_DATA4_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_op_data4 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_op_data4_u {
+	a_uint32_t val;
+	struct host_tbl_rd_op_data4 bf;
+};
+
+/*[register] HOST_TBL_RD_OP_DATA5*/
+#define HOST_TBL_RD_OP_DATA5
+#define HOST_TBL_RD_OP_DATA5_ADDRESS 0x504
+#define HOST_TBL_RD_OP_DATA5_NUM     1
+#define HOST_TBL_RD_OP_DATA5_INC     0x4
+#define HOST_TBL_RD_OP_DATA5_TYPE    REG_TYPE_RW
+#define HOST_TBL_RD_OP_DATA5_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_OP_DATA5_DATA
+	#define HOST_TBL_RD_OP_DATA5_DATA_OFFSET  0
+	#define HOST_TBL_RD_OP_DATA5_DATA_LEN     32
+	#define HOST_TBL_RD_OP_DATA5_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_op_data5 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_op_data5_u {
+	a_uint32_t val;
+	struct host_tbl_rd_op_data5 bf;
+};
+
+/*[register] HOST_TBL_RD_OP_DATA6*/
+#define HOST_TBL_RD_OP_DATA6
+#define HOST_TBL_RD_OP_DATA6_ADDRESS 0x508
+#define HOST_TBL_RD_OP_DATA6_NUM     1
+#define HOST_TBL_RD_OP_DATA6_INC     0x4
+#define HOST_TBL_RD_OP_DATA6_TYPE    REG_TYPE_RW
+#define HOST_TBL_RD_OP_DATA6_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_OP_DATA6_DATA
+	#define HOST_TBL_RD_OP_DATA6_DATA_OFFSET  0
+	#define HOST_TBL_RD_OP_DATA6_DATA_LEN     32
+	#define HOST_TBL_RD_OP_DATA6_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_op_data6 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_op_data6_u {
+	a_uint32_t val;
+	struct host_tbl_rd_op_data6 bf;
+};
+
+/*[register] HOST_TBL_RD_OP_DATA7*/
+#define HOST_TBL_RD_OP_DATA7
+#define HOST_TBL_RD_OP_DATA7_ADDRESS 0x50c
+#define HOST_TBL_RD_OP_DATA7_NUM     1
+#define HOST_TBL_RD_OP_DATA7_INC     0x4
+#define HOST_TBL_RD_OP_DATA7_TYPE    REG_TYPE_RW
+#define HOST_TBL_RD_OP_DATA7_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_OP_DATA7_DATA
+	#define HOST_TBL_RD_OP_DATA7_DATA_OFFSET  0
+	#define HOST_TBL_RD_OP_DATA7_DATA_LEN     32
+	#define HOST_TBL_RD_OP_DATA7_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_op_data7 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_op_data7_u {
+	a_uint32_t val;
+	struct host_tbl_rd_op_data7 bf;
+};
+
+/*[register] HOST_TBL_RD_OP_DATA8*/
+#define HOST_TBL_RD_OP_DATA8
+#define HOST_TBL_RD_OP_DATA8_ADDRESS 0x510
+#define HOST_TBL_RD_OP_DATA8_NUM     1
+#define HOST_TBL_RD_OP_DATA8_INC     0x4
+#define HOST_TBL_RD_OP_DATA8_TYPE    REG_TYPE_RW
+#define HOST_TBL_RD_OP_DATA8_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_OP_DATA8_DATA
+	#define HOST_TBL_RD_OP_DATA8_DATA_OFFSET  0
+	#define HOST_TBL_RD_OP_DATA8_DATA_LEN     32
+	#define HOST_TBL_RD_OP_DATA8_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_op_data8 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_op_data8_u {
+	a_uint32_t val;
+	struct host_tbl_rd_op_data8 bf;
+};
+
+/*[register] HOST_TBL_RD_OP_DATA9*/
+#define HOST_TBL_RD_OP_DATA9
+#define HOST_TBL_RD_OP_DATA9_ADDRESS 0x514
+#define HOST_TBL_RD_OP_DATA9_NUM     1
+#define HOST_TBL_RD_OP_DATA9_INC     0x4
+#define HOST_TBL_RD_OP_DATA9_TYPE    REG_TYPE_RW
+#define HOST_TBL_RD_OP_DATA9_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_OP_DATA9_DATA
+	#define HOST_TBL_RD_OP_DATA9_DATA_OFFSET  0
+	#define HOST_TBL_RD_OP_DATA9_DATA_LEN     32
+	#define HOST_TBL_RD_OP_DATA9_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_op_data9 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_op_data9_u {
+	a_uint32_t val;
+	struct host_tbl_rd_op_data9 bf;
+};
+
+/*[register] HOST_TBL_RD_OP_RSLT*/
+#define HOST_TBL_RD_OP_RSLT
+#define HOST_TBL_RD_OP_RSLT_ADDRESS 0x518
+#define HOST_TBL_RD_OP_RSLT_NUM     1
+#define HOST_TBL_RD_OP_RSLT_INC     0x4
+#define HOST_TBL_RD_OP_RSLT_TYPE    REG_TYPE_RO
+#define HOST_TBL_RD_OP_RSLT_DEFAULT 0x0
+	/*[field] CMD_ID*/
+	#define HOST_TBL_RD_OP_RSLT_CMD_ID
+	#define HOST_TBL_RD_OP_RSLT_CMD_ID_OFFSET  0
+	#define HOST_TBL_RD_OP_RSLT_CMD_ID_LEN     4
+	#define HOST_TBL_RD_OP_RSLT_CMD_ID_DEFAULT 0x0
+	/*[field] OP_RSLT*/
+	#define HOST_TBL_RD_OP_RSLT_OP_RSLT
+	#define HOST_TBL_RD_OP_RSLT_OP_RSLT_OFFSET  4
+	#define HOST_TBL_RD_OP_RSLT_OP_RSLT_LEN     1
+	#define HOST_TBL_RD_OP_RSLT_OP_RSLT_DEFAULT 0x0
+	/*[field] ENTRY_INDEX*/
+	#define HOST_TBL_RD_OP_RSLT_ENTRY_INDEX
+	#define HOST_TBL_RD_OP_RSLT_ENTRY_INDEX_OFFSET  5
+	#define HOST_TBL_RD_OP_RSLT_ENTRY_INDEX_LEN     13
+	#define HOST_TBL_RD_OP_RSLT_ENTRY_INDEX_DEFAULT 0x0
+	/*[field] VALID_CNT*/
+	#define HOST_TBL_RD_OP_RSLT_VALID_CNT
+	#define HOST_TBL_RD_OP_RSLT_VALID_CNT_OFFSET  18
+	#define HOST_TBL_RD_OP_RSLT_VALID_CNT_LEN     4
+	#define HOST_TBL_RD_OP_RSLT_VALID_CNT_DEFAULT 0x0
+
+struct host_tbl_rd_op_rslt {
+	a_uint32_t  cmd_id:4;
+	a_uint32_t  op_rslt:1;
+	a_uint32_t  entry_index:13;
+	a_uint32_t  valid_cnt:4;
+	a_uint32_t  _reserved0:10;
+};
+
+union host_tbl_rd_op_rslt_u {
+	a_uint32_t val;
+	struct host_tbl_rd_op_rslt bf;
+};
+
+/*[register] HOST_TBL_RD_RSLT_DATA0*/
+#define HOST_TBL_RD_RSLT_DATA0
+#define HOST_TBL_RD_RSLT_DATA0_ADDRESS 0x51c
+#define HOST_TBL_RD_RSLT_DATA0_NUM     1
+#define HOST_TBL_RD_RSLT_DATA0_INC     0x4
+#define HOST_TBL_RD_RSLT_DATA0_TYPE    REG_TYPE_RO
+#define HOST_TBL_RD_RSLT_DATA0_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_RSLT_DATA0_DATA
+	#define HOST_TBL_RD_RSLT_DATA0_DATA_OFFSET  0
+	#define HOST_TBL_RD_RSLT_DATA0_DATA_LEN     32
+	#define HOST_TBL_RD_RSLT_DATA0_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_rslt_data0 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_rslt_data0_u {
+	a_uint32_t val;
+	struct host_tbl_rd_rslt_data0 bf;
+};
+
+/*[register] HOST_TBL_RD_RSLT_DATA1*/
+#define HOST_TBL_RD_RSLT_DATA1
+#define HOST_TBL_RD_RSLT_DATA1_ADDRESS 0x520
+#define HOST_TBL_RD_RSLT_DATA1_NUM     1
+#define HOST_TBL_RD_RSLT_DATA1_INC     0x4
+#define HOST_TBL_RD_RSLT_DATA1_TYPE    REG_TYPE_RO
+#define HOST_TBL_RD_RSLT_DATA1_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_RSLT_DATA1_DATA
+	#define HOST_TBL_RD_RSLT_DATA1_DATA_OFFSET  0
+	#define HOST_TBL_RD_RSLT_DATA1_DATA_LEN     32
+	#define HOST_TBL_RD_RSLT_DATA1_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_rslt_data1 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_rslt_data1_u {
+	a_uint32_t val;
+	struct host_tbl_rd_rslt_data1 bf;
+};
+
+/*[register] HOST_TBL_RD_RSLT_DATA2*/
+#define HOST_TBL_RD_RSLT_DATA2
+#define HOST_TBL_RD_RSLT_DATA2_ADDRESS 0x524
+#define HOST_TBL_RD_RSLT_DATA2_NUM     1
+#define HOST_TBL_RD_RSLT_DATA2_INC     0x4
+#define HOST_TBL_RD_RSLT_DATA2_TYPE    REG_TYPE_RO
+#define HOST_TBL_RD_RSLT_DATA2_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_RSLT_DATA2_DATA
+	#define HOST_TBL_RD_RSLT_DATA2_DATA_OFFSET  0
+	#define HOST_TBL_RD_RSLT_DATA2_DATA_LEN     32
+	#define HOST_TBL_RD_RSLT_DATA2_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_rslt_data2 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_rslt_data2_u {
+	a_uint32_t val;
+	struct host_tbl_rd_rslt_data2 bf;
+};
+
+/*[register] HOST_TBL_RD_RSLT_DATA3*/
+#define HOST_TBL_RD_RSLT_DATA3
+#define HOST_TBL_RD_RSLT_DATA3_ADDRESS 0x528
+#define HOST_TBL_RD_RSLT_DATA3_NUM     1
+#define HOST_TBL_RD_RSLT_DATA3_INC     0x4
+#define HOST_TBL_RD_RSLT_DATA3_TYPE    REG_TYPE_RO
+#define HOST_TBL_RD_RSLT_DATA3_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_RSLT_DATA3_DATA
+	#define HOST_TBL_RD_RSLT_DATA3_DATA_OFFSET  0
+	#define HOST_TBL_RD_RSLT_DATA3_DATA_LEN     32
+	#define HOST_TBL_RD_RSLT_DATA3_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_rslt_data3 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_rslt_data3_u {
+	a_uint32_t val;
+	struct host_tbl_rd_rslt_data3 bf;
+};
+
+/*[register] HOST_TBL_RD_RSLT_DATA4*/
+#define HOST_TBL_RD_RSLT_DATA4
+#define HOST_TBL_RD_RSLT_DATA4_ADDRESS 0x52c
+#define HOST_TBL_RD_RSLT_DATA4_NUM     1
+#define HOST_TBL_RD_RSLT_DATA4_INC     0x4
+#define HOST_TBL_RD_RSLT_DATA4_TYPE    REG_TYPE_RO
+#define HOST_TBL_RD_RSLT_DATA4_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_RSLT_DATA4_DATA
+	#define HOST_TBL_RD_RSLT_DATA4_DATA_OFFSET  0
+	#define HOST_TBL_RD_RSLT_DATA4_DATA_LEN     32
+	#define HOST_TBL_RD_RSLT_DATA4_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_rslt_data4 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_rslt_data4_u {
+	a_uint32_t val;
+	struct host_tbl_rd_rslt_data4 bf;
+};
+
+/*[register] HOST_TBL_RD_RSLT_DATA5*/
+#define HOST_TBL_RD_RSLT_DATA5
+#define HOST_TBL_RD_RSLT_DATA5_ADDRESS 0x530
+#define HOST_TBL_RD_RSLT_DATA5_NUM     1
+#define HOST_TBL_RD_RSLT_DATA5_INC     0x4
+#define HOST_TBL_RD_RSLT_DATA5_TYPE    REG_TYPE_RO
+#define HOST_TBL_RD_RSLT_DATA5_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_RSLT_DATA5_DATA
+	#define HOST_TBL_RD_RSLT_DATA5_DATA_OFFSET  0
+	#define HOST_TBL_RD_RSLT_DATA5_DATA_LEN     32
+	#define HOST_TBL_RD_RSLT_DATA5_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_rslt_data5 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_rslt_data5_u {
+	a_uint32_t val;
+	struct host_tbl_rd_rslt_data5 bf;
+};
+
+/*[register] HOST_TBL_RD_RSLT_DATA6*/
+#define HOST_TBL_RD_RSLT_DATA6
+#define HOST_TBL_RD_RSLT_DATA6_ADDRESS 0x534
+#define HOST_TBL_RD_RSLT_DATA6_NUM     1
+#define HOST_TBL_RD_RSLT_DATA6_INC     0x4
+#define HOST_TBL_RD_RSLT_DATA6_TYPE    REG_TYPE_RO
+#define HOST_TBL_RD_RSLT_DATA6_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_RSLT_DATA6_DATA
+	#define HOST_TBL_RD_RSLT_DATA6_DATA_OFFSET  0
+	#define HOST_TBL_RD_RSLT_DATA6_DATA_LEN     32
+	#define HOST_TBL_RD_RSLT_DATA6_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_rslt_data6 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_rslt_data6_u {
+	a_uint32_t val;
+	struct host_tbl_rd_rslt_data6 bf;
+};
+
+/*[register] HOST_TBL_RD_RSLT_DATA7*/
+#define HOST_TBL_RD_RSLT_DATA7
+#define HOST_TBL_RD_RSLT_DATA7_ADDRESS 0x538
+#define HOST_TBL_RD_RSLT_DATA7_NUM     1
+#define HOST_TBL_RD_RSLT_DATA7_INC     0x4
+#define HOST_TBL_RD_RSLT_DATA7_TYPE    REG_TYPE_RO
+#define HOST_TBL_RD_RSLT_DATA7_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_RSLT_DATA7_DATA
+	#define HOST_TBL_RD_RSLT_DATA7_DATA_OFFSET  0
+	#define HOST_TBL_RD_RSLT_DATA7_DATA_LEN     32
+	#define HOST_TBL_RD_RSLT_DATA7_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_rslt_data7 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_rslt_data7_u {
+	a_uint32_t val;
+	struct host_tbl_rd_rslt_data7 bf;
+};
+
+/*[register] HOST_TBL_RD_RSLT_DATA8*/
+#define HOST_TBL_RD_RSLT_DATA8
+#define HOST_TBL_RD_RSLT_DATA8_ADDRESS 0x53c
+#define HOST_TBL_RD_RSLT_DATA8_NUM     1
+#define HOST_TBL_RD_RSLT_DATA8_INC     0x4
+#define HOST_TBL_RD_RSLT_DATA8_TYPE    REG_TYPE_RO
+#define HOST_TBL_RD_RSLT_DATA8_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_RSLT_DATA8_DATA
+	#define HOST_TBL_RD_RSLT_DATA8_DATA_OFFSET  0
+	#define HOST_TBL_RD_RSLT_DATA8_DATA_LEN     32
+	#define HOST_TBL_RD_RSLT_DATA8_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_rslt_data8 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_rslt_data8_u {
+	a_uint32_t val;
+	struct host_tbl_rd_rslt_data8 bf;
+};
+
+/*[register] HOST_TBL_RD_RSLT_DATA9*/
+#define HOST_TBL_RD_RSLT_DATA9
+#define HOST_TBL_RD_RSLT_DATA9_ADDRESS 0x540
+#define HOST_TBL_RD_RSLT_DATA9_NUM     1
+#define HOST_TBL_RD_RSLT_DATA9_INC     0x4
+#define HOST_TBL_RD_RSLT_DATA9_TYPE    REG_TYPE_RO
+#define HOST_TBL_RD_RSLT_DATA9_DEFAULT 0x0
+	/*[field] DATA*/
+	#define HOST_TBL_RD_RSLT_DATA9_DATA
+	#define HOST_TBL_RD_RSLT_DATA9_DATA_OFFSET  0
+	#define HOST_TBL_RD_RSLT_DATA9_DATA_LEN     32
+	#define HOST_TBL_RD_RSLT_DATA9_DATA_DEFAULT 0x0
+
+struct host_tbl_rd_rslt_data9 {
+	a_uint32_t  data:32;
+};
+
+union host_tbl_rd_rslt_data9_u {
+	a_uint32_t val;
+	struct host_tbl_rd_rslt_data9 bf;
+};
+
+/*[register] L3_DBG_CMD*/
+#define L3_DBG_CMD
+#define L3_DBG_CMD_ADDRESS 0xc04
+#define L3_DBG_CMD_NUM     1
+#define L3_DBG_CMD_INC     0x4
+#define L3_DBG_CMD_TYPE    REG_TYPE_RW
+#define L3_DBG_CMD_DEFAULT 0x0
+	/*[field] ADDR*/
+	#define L3_DBG_CMD_ADDR
+	#define L3_DBG_CMD_ADDR_OFFSET  0
+	#define L3_DBG_CMD_ADDR_LEN     8
+	#define L3_DBG_CMD_ADDR_DEFAULT 0x0
+	/*[field] TYPE*/
+	#define L3_DBG_CMD_TYPE_F
+	#define L3_DBG_CMD_TYPE_F_OFFSET  8
+	#define L3_DBG_CMD_TYPE_F_LEN     2
+	#define L3_DBG_CMD_TYPE_F_DEFAULT 0x0
+
+struct l3_dbg_cmd {
+	a_uint32_t  addr:8;
+	a_uint32_t  type:2;
+	a_uint32_t  _reserved0:22;
+};
+
+union l3_dbg_cmd_u {
+	a_uint32_t val;
+	struct l3_dbg_cmd bf;
+};
+
+/*[register] L3_DBG_WR_DATA*/
+#define L3_DBG_WR_DATA
+#define L3_DBG_WR_DATA_ADDRESS 0xc08
+#define L3_DBG_WR_DATA_NUM     1
+#define L3_DBG_WR_DATA_INC     0x4
+#define L3_DBG_WR_DATA_TYPE    REG_TYPE_RW
+#define L3_DBG_WR_DATA_DEFAULT 0x0
+	/*[field] DATA*/
+	#define L3_DBG_WR_DATA_DATA
+	#define L3_DBG_WR_DATA_DATA_OFFSET  0
+	#define L3_DBG_WR_DATA_DATA_LEN     32
+	#define L3_DBG_WR_DATA_DATA_DEFAULT 0x0
+
+struct l3_dbg_wr_data {
+	a_uint32_t  data:32;
+};
+
+union l3_dbg_wr_data_u {
+	a_uint32_t val;
+	struct l3_dbg_wr_data bf;
+};
+
+/*[register] L3_DBG_RD_DATA*/
+#define L3_DBG_RD_DATA
+#define L3_DBG_RD_DATA_ADDRESS 0xc0c
+#define L3_DBG_RD_DATA_NUM     1
+#define L3_DBG_RD_DATA_INC     0x4
+#define L3_DBG_RD_DATA_TYPE    REG_TYPE_RO
+#define L3_DBG_RD_DATA_DEFAULT 0x0
+	/*[field] DATA*/
+	#define L3_DBG_RD_DATA_DATA
+	#define L3_DBG_RD_DATA_DATA_OFFSET  0
+	#define L3_DBG_RD_DATA_DATA_LEN     32
+	#define L3_DBG_RD_DATA_DATA_DEFAULT 0x0
+
+struct l3_dbg_rd_data {
+	a_uint32_t  data:32;
+};
+
+union l3_dbg_rd_data_u {
+	a_uint32_t val;
+	struct l3_dbg_rd_data bf;
+};
+
+/*[register] IN_PUB_IP_ADDR_TBL*/
+#define IN_PUB_IP_ADDR_TBL
+#define IN_PUB_IP_ADDR_TBL_ADDRESS 0x378
+#define IN_PUB_IP_ADDR_TBL_NUM     16
+#define IN_PUB_IP_ADDR_TBL_INC     0x4
+#define IN_PUB_IP_ADDR_TBL_TYPE    REG_TYPE_RW
+#define IN_PUB_IP_ADDR_TBL_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define IN_PUB_IP_ADDR_TBL_IP_ADDR
+	#define IN_PUB_IP_ADDR_TBL_IP_ADDR_OFFSET  0
+	#define IN_PUB_IP_ADDR_TBL_IP_ADDR_LEN     32
+	#define IN_PUB_IP_ADDR_TBL_IP_ADDR_DEFAULT 0x0
+
+struct in_pub_ip_addr_tbl {
+	a_uint32_t  ip_addr:32;
+};
+
+union in_pub_ip_addr_tbl_u {
+	a_uint32_t val;
+	struct in_pub_ip_addr_tbl bf;
+};
+
+/*[table] L3_VP_PORT_TBL*/
+#define L3_VP_PORT_TBL
+#define L3_VP_PORT_TBL_ADDRESS 0x1000
+#define L3_VP_PORT_TBL_NUM     256
+#define L3_VP_PORT_TBL_INC     0x10
+#define L3_VP_PORT_TBL_TYPE    REG_TYPE_RW
+#define L3_VP_PORT_TBL_DEFAULT 0x0
+	/*[field] L3_IF_VALID*/
+	#define L3_VP_PORT_TBL_L3_IF_VALID
+	#define L3_VP_PORT_TBL_L3_IF_VALID_OFFSET  0
+	#define L3_VP_PORT_TBL_L3_IF_VALID_LEN     1
+	#define L3_VP_PORT_TBL_L3_IF_VALID_DEFAULT 0x0
+	/*[field] L3_IF_INDEX*/
+	#define L3_VP_PORT_TBL_L3_IF_INDEX
+	#define L3_VP_PORT_TBL_L3_IF_INDEX_OFFSET  1
+	#define L3_VP_PORT_TBL_L3_IF_INDEX_LEN     8
+	#define L3_VP_PORT_TBL_L3_IF_INDEX_DEFAULT 0x0
+	/*[field] IPV4_SG_EN*/
+	#define L3_VP_PORT_TBL_IPV4_SG_EN
+	#define L3_VP_PORT_TBL_IPV4_SG_EN_OFFSET  9
+	#define L3_VP_PORT_TBL_IPV4_SG_EN_LEN     1
+	#define L3_VP_PORT_TBL_IPV4_SG_EN_DEFAULT 0x0
+	/*[field] IPV4_SG_VIO_CMD*/
+	#define L3_VP_PORT_TBL_IPV4_SG_VIO_CMD
+	#define L3_VP_PORT_TBL_IPV4_SG_VIO_CMD_OFFSET  10
+	#define L3_VP_PORT_TBL_IPV4_SG_VIO_CMD_LEN     2
+	#define L3_VP_PORT_TBL_IPV4_SG_VIO_CMD_DEFAULT 0x0
+	/*[field] IPV4_SG_PORT_EN*/
+	#define L3_VP_PORT_TBL_IPV4_SG_PORT_EN
+	#define L3_VP_PORT_TBL_IPV4_SG_PORT_EN_OFFSET  12
+	#define L3_VP_PORT_TBL_IPV4_SG_PORT_EN_LEN     1
+	#define L3_VP_PORT_TBL_IPV4_SG_PORT_EN_DEFAULT 0x0
+	/*[field] IPV4_SG_SVLAN_EN*/
+	#define L3_VP_PORT_TBL_IPV4_SG_SVLAN_EN
+	#define L3_VP_PORT_TBL_IPV4_SG_SVLAN_EN_OFFSET  13
+	#define L3_VP_PORT_TBL_IPV4_SG_SVLAN_EN_LEN     1
+	#define L3_VP_PORT_TBL_IPV4_SG_SVLAN_EN_DEFAULT 0x0
+	/*[field] IPV4_SG_CVLAN_EN*/
+	#define L3_VP_PORT_TBL_IPV4_SG_CVLAN_EN
+	#define L3_VP_PORT_TBL_IPV4_SG_CVLAN_EN_OFFSET  14
+	#define L3_VP_PORT_TBL_IPV4_SG_CVLAN_EN_LEN     1
+	#define L3_VP_PORT_TBL_IPV4_SG_CVLAN_EN_DEFAULT 0x0
+	/*[field] IPV4_SRC_UNK_CMD*/
+	#define L3_VP_PORT_TBL_IPV4_SRC_UNK_CMD
+	#define L3_VP_PORT_TBL_IPV4_SRC_UNK_CMD_OFFSET  15
+	#define L3_VP_PORT_TBL_IPV4_SRC_UNK_CMD_LEN     2
+	#define L3_VP_PORT_TBL_IPV4_SRC_UNK_CMD_DEFAULT 0x0
+	/*[field] IPV6_SG_EN*/
+	#define L3_VP_PORT_TBL_IPV6_SG_EN
+	#define L3_VP_PORT_TBL_IPV6_SG_EN_OFFSET  17
+	#define L3_VP_PORT_TBL_IPV6_SG_EN_LEN     1
+	#define L3_VP_PORT_TBL_IPV6_SG_EN_DEFAULT 0x0
+	/*[field] IPV6_SG_VIO_CMD*/
+	#define L3_VP_PORT_TBL_IPV6_SG_VIO_CMD
+	#define L3_VP_PORT_TBL_IPV6_SG_VIO_CMD_OFFSET  18
+	#define L3_VP_PORT_TBL_IPV6_SG_VIO_CMD_LEN     2
+	#define L3_VP_PORT_TBL_IPV6_SG_VIO_CMD_DEFAULT 0x0
+	/*[field] IPV6_SG_PORT_EN*/
+	#define L3_VP_PORT_TBL_IPV6_SG_PORT_EN
+	#define L3_VP_PORT_TBL_IPV6_SG_PORT_EN_OFFSET  20
+	#define L3_VP_PORT_TBL_IPV6_SG_PORT_EN_LEN     1
+	#define L3_VP_PORT_TBL_IPV6_SG_PORT_EN_DEFAULT 0x0
+	/*[field] IPV6_SG_SVLAN_EN*/
+	#define L3_VP_PORT_TBL_IPV6_SG_SVLAN_EN
+	#define L3_VP_PORT_TBL_IPV6_SG_SVLAN_EN_OFFSET  21
+	#define L3_VP_PORT_TBL_IPV6_SG_SVLAN_EN_LEN     1
+	#define L3_VP_PORT_TBL_IPV6_SG_SVLAN_EN_DEFAULT 0x0
+	/*[field] IPV6_SG_CVLAN_EN*/
+	#define L3_VP_PORT_TBL_IPV6_SG_CVLAN_EN
+	#define L3_VP_PORT_TBL_IPV6_SG_CVLAN_EN_OFFSET  22
+	#define L3_VP_PORT_TBL_IPV6_SG_CVLAN_EN_LEN     1
+	#define L3_VP_PORT_TBL_IPV6_SG_CVLAN_EN_DEFAULT 0x0
+	/*[field] IPV6_SRC_UNK_CMD*/
+	#define L3_VP_PORT_TBL_IPV6_SRC_UNK_CMD
+	#define L3_VP_PORT_TBL_IPV6_SRC_UNK_CMD_OFFSET  23
+	#define L3_VP_PORT_TBL_IPV6_SRC_UNK_CMD_LEN     2
+	#define L3_VP_PORT_TBL_IPV6_SRC_UNK_CMD_DEFAULT 0x0
+	/*[field] IP_ARP_SG_EN*/
+	#define L3_VP_PORT_TBL_IP_ARP_SG_EN
+	#define L3_VP_PORT_TBL_IP_ARP_SG_EN_OFFSET  25
+	#define L3_VP_PORT_TBL_IP_ARP_SG_EN_LEN     1
+	#define L3_VP_PORT_TBL_IP_ARP_SG_EN_DEFAULT 0x0
+	/*[field] IP_ARP_SG_VIO_CMD*/
+	#define L3_VP_PORT_TBL_IP_ARP_SG_VIO_CMD
+	#define L3_VP_PORT_TBL_IP_ARP_SG_VIO_CMD_OFFSET  26
+	#define L3_VP_PORT_TBL_IP_ARP_SG_VIO_CMD_LEN     2
+	#define L3_VP_PORT_TBL_IP_ARP_SG_VIO_CMD_DEFAULT 0x0
+	/*[field] IP_ARP_SG_PORT_EN*/
+	#define L3_VP_PORT_TBL_IP_ARP_SG_PORT_EN
+	#define L3_VP_PORT_TBL_IP_ARP_SG_PORT_EN_OFFSET  28
+	#define L3_VP_PORT_TBL_IP_ARP_SG_PORT_EN_LEN     1
+	#define L3_VP_PORT_TBL_IP_ARP_SG_PORT_EN_DEFAULT 0x0
+	/*[field] IP_ARP_SG_SVLAN_EN*/
+	#define L3_VP_PORT_TBL_IP_ARP_SG_SVLAN_EN
+	#define L3_VP_PORT_TBL_IP_ARP_SG_SVLAN_EN_OFFSET  29
+	#define L3_VP_PORT_TBL_IP_ARP_SG_SVLAN_EN_LEN     1
+	#define L3_VP_PORT_TBL_IP_ARP_SG_SVLAN_EN_DEFAULT 0x0
+	/*[field] IP_ARP_SRC_UNK_CMD*/
+	#define L3_VP_PORT_TBL_IP_ARP_SRC_UNK_CMD
+	#define L3_VP_PORT_TBL_IP_ARP_SRC_UNK_CMD_OFFSET  30
+	#define L3_VP_PORT_TBL_IP_ARP_SRC_UNK_CMD_LEN     2
+	#define L3_VP_PORT_TBL_IP_ARP_SRC_UNK_CMD_DEFAULT 0x0
+	/*[field] IP_ARP_SG_CVLAN_EN*/
+	#define L3_VP_PORT_TBL_IP_ARP_SG_CVLAN_EN
+	#define L3_VP_PORT_TBL_IP_ARP_SG_CVLAN_EN_OFFSET  32
+	#define L3_VP_PORT_TBL_IP_ARP_SG_CVLAN_EN_LEN     1
+	#define L3_VP_PORT_TBL_IP_ARP_SG_CVLAN_EN_DEFAULT 0x0
+	/*[field] IP_ND_SG_EN*/
+	#define L3_VP_PORT_TBL_IP_ND_SG_EN
+	#define L3_VP_PORT_TBL_IP_ND_SG_EN_OFFSET  33
+	#define L3_VP_PORT_TBL_IP_ND_SG_EN_LEN     1
+	#define L3_VP_PORT_TBL_IP_ND_SG_EN_DEFAULT 0x0
+	/*[field] IP_ND_SG_VIO_CMD*/
+	#define L3_VP_PORT_TBL_IP_ND_SG_VIO_CMD
+	#define L3_VP_PORT_TBL_IP_ND_SG_VIO_CMD_OFFSET  34
+	#define L3_VP_PORT_TBL_IP_ND_SG_VIO_CMD_LEN     2
+	#define L3_VP_PORT_TBL_IP_ND_SG_VIO_CMD_DEFAULT 0x0
+	/*[field] IP_ND_SG_PORT_EN*/
+	#define L3_VP_PORT_TBL_IP_ND_SG_PORT_EN
+	#define L3_VP_PORT_TBL_IP_ND_SG_PORT_EN_OFFSET  36
+	#define L3_VP_PORT_TBL_IP_ND_SG_PORT_EN_LEN     1
+	#define L3_VP_PORT_TBL_IP_ND_SG_PORT_EN_DEFAULT 0x0
+	/*[field] IP_ND_SG_SVLAN_EN*/
+	#define L3_VP_PORT_TBL_IP_ND_SG_SVLAN_EN
+	#define L3_VP_PORT_TBL_IP_ND_SG_SVLAN_EN_OFFSET  37
+	#define L3_VP_PORT_TBL_IP_ND_SG_SVLAN_EN_LEN     1
+	#define L3_VP_PORT_TBL_IP_ND_SG_SVLAN_EN_DEFAULT 0x0
+	/*[field] IP_ND_SG_CVLAN_EN*/
+	#define L3_VP_PORT_TBL_IP_ND_SG_CVLAN_EN
+	#define L3_VP_PORT_TBL_IP_ND_SG_CVLAN_EN_OFFSET  38
+	#define L3_VP_PORT_TBL_IP_ND_SG_CVLAN_EN_LEN     1
+	#define L3_VP_PORT_TBL_IP_ND_SG_CVLAN_EN_DEFAULT 0x0
+	/*[field] IP_ND_SRC_UNK_CMD*/
+	#define L3_VP_PORT_TBL_IP_ND_SRC_UNK_CMD
+	#define L3_VP_PORT_TBL_IP_ND_SRC_UNK_CMD_OFFSET  39
+	#define L3_VP_PORT_TBL_IP_ND_SRC_UNK_CMD_LEN     2
+	#define L3_VP_PORT_TBL_IP_ND_SRC_UNK_CMD_DEFAULT 0x0
+	/*[field] VSI_VALID*/
+	#define L3_VP_PORT_TBL_VSI_VALID
+	#define L3_VP_PORT_TBL_VSI_VALID_OFFSET  41
+	#define L3_VP_PORT_TBL_VSI_VALID_LEN     1
+	#define L3_VP_PORT_TBL_VSI_VALID_DEFAULT 0x0
+	/*[field] VSI*/
+	#define L3_VP_PORT_TBL_VSI
+	#define L3_VP_PORT_TBL_VSI_OFFSET  42
+	#define L3_VP_PORT_TBL_VSI_LEN     5
+	#define L3_VP_PORT_TBL_VSI_DEFAULT 0x0
+	/*[field] MAC_VALID*/
+	#define L3_VP_PORT_TBL_MAC_VALID
+	#define L3_VP_PORT_TBL_MAC_VALID_OFFSET  47
+	#define L3_VP_PORT_TBL_MAC_VALID_LEN     1
+	#define L3_VP_PORT_TBL_MAC_VALID_DEFAULT 0x0
+	/*[field] MAC_DA*/
+	#define L3_VP_PORT_TBL_MAC_DA
+	#define L3_VP_PORT_TBL_MAC_DA_OFFSET  48
+	#define L3_VP_PORT_TBL_MAC_DA_LEN     48
+	#define L3_VP_PORT_TBL_MAC_DA_DEFAULT 0x0
+
+struct l3_vp_port_tbl {
+	a_uint32_t  l3_if_valid:1;
+	a_uint32_t  l3_if_index:8;
+	a_uint32_t  ipv4_sg_en:1;
+	a_uint32_t  ipv4_sg_vio_cmd:2;
+	a_uint32_t  ipv4_sg_port_en:1;
+	a_uint32_t  ipv4_sg_svlan_en:1;
+	a_uint32_t  ipv4_sg_cvlan_en:1;
+	a_uint32_t  ipv4_src_unk_cmd:2;
+	a_uint32_t  ipv6_sg_en:1;
+	a_uint32_t  ipv6_sg_vio_cmd:2;
+	a_uint32_t  ipv6_sg_port_en:1;
+	a_uint32_t  ipv6_sg_svlan_en:1;
+	a_uint32_t  ipv6_sg_cvlan_en:1;
+	a_uint32_t  ipv6_src_unk_cmd:2;
+	a_uint32_t  ip_arp_sg_en:1;
+	a_uint32_t  ip_arp_sg_vio_cmd:2;
+	a_uint32_t  ip_arp_sg_port_en:1;
+	a_uint32_t  ip_arp_sg_svlan_en:1;
+	a_uint32_t  ip_arp_src_unk_cmd:2;
+	a_uint32_t  ip_arp_sg_cvlan_en:1;
+	a_uint32_t  ip_nd_sg_en:1;
+	a_uint32_t  ip_nd_sg_vio_cmd:2;
+	a_uint32_t  ip_nd_sg_port_en:1;
+	a_uint32_t  ip_nd_sg_svlan_en:1;
+	a_uint32_t  ip_nd_sg_cvlan_en:1;
+	a_uint32_t  ip_nd_src_unk_cmd:2;
+	a_uint32_t  vsi_valid:1;
+	a_uint32_t  vsi:5;
+	a_uint32_t  mac_valid:1;
+	a_uint32_t  mac_da_0:16;
+	a_uint32_t  mac_da_1:32;
+};
+
+union l3_vp_port_tbl_u {
+	a_uint32_t val[3];
+	struct l3_vp_port_tbl bf;
+};
+
+/*[table] IN_L3_IF_TBL*/
+#define IN_L3_IF_TBL
+#define IN_L3_IF_TBL_ADDRESS 0x2000
+#define IN_L3_IF_TBL_NUM     256
+#define IN_L3_IF_TBL_INC     0x8
+#define IN_L3_IF_TBL_TYPE    REG_TYPE_RW
+#define IN_L3_IF_TBL_DEFAULT 0x0
+	/*[field] MRU*/
+	#define IN_L3_IF_TBL_MRU
+	#define IN_L3_IF_TBL_MRU_OFFSET  0
+	#define IN_L3_IF_TBL_MRU_LEN     14
+	#define IN_L3_IF_TBL_MRU_DEFAULT 0x0
+	/*[field] MTU*/
+	#define IN_L3_IF_TBL_MTU
+	#define IN_L3_IF_TBL_MTU_OFFSET  14
+	#define IN_L3_IF_TBL_MTU_LEN     14
+	#define IN_L3_IF_TBL_MTU_DEFAULT 0x0
+	/*[field] TTL_DEC_BYPASS*/
+	#define IN_L3_IF_TBL_TTL_DEC_BYPASS
+	#define IN_L3_IF_TBL_TTL_DEC_BYPASS_OFFSET  28
+	#define IN_L3_IF_TBL_TTL_DEC_BYPASS_LEN     1
+	#define IN_L3_IF_TBL_TTL_DEC_BYPASS_DEFAULT 0x0
+	/*[field] IPV4_UC_ROUTE_EN*/
+	#define IN_L3_IF_TBL_IPV4_UC_ROUTE_EN
+	#define IN_L3_IF_TBL_IPV4_UC_ROUTE_EN_OFFSET  29
+	#define IN_L3_IF_TBL_IPV4_UC_ROUTE_EN_LEN     1
+	#define IN_L3_IF_TBL_IPV4_UC_ROUTE_EN_DEFAULT 0x0
+	/*[field] IPV6_UC_ROUTE_EN*/
+	#define IN_L3_IF_TBL_IPV6_UC_ROUTE_EN
+	#define IN_L3_IF_TBL_IPV6_UC_ROUTE_EN_OFFSET  30
+	#define IN_L3_IF_TBL_IPV6_UC_ROUTE_EN_LEN     1
+	#define IN_L3_IF_TBL_IPV6_UC_ROUTE_EN_DEFAULT 0x0
+	/*[field] ICMP_TRIGGER_EN*/
+	#define IN_L3_IF_TBL_ICMP_TRIGGER_EN
+	#define IN_L3_IF_TBL_ICMP_TRIGGER_EN_OFFSET  31
+	#define IN_L3_IF_TBL_ICMP_TRIGGER_EN_LEN     1
+	#define IN_L3_IF_TBL_ICMP_TRIGGER_EN_DEFAULT 0x0
+	/*[field] TTL_EXCEED_CMD*/
+	#define IN_L3_IF_TBL_TTL_EXCEED_CMD
+	#define IN_L3_IF_TBL_TTL_EXCEED_CMD_OFFSET  32
+	#define IN_L3_IF_TBL_TTL_EXCEED_CMD_LEN     2
+	#define IN_L3_IF_TBL_TTL_EXCEED_CMD_DEFAULT 0x0
+	/*[field] TTL_EXCEED_DE_ACCE*/
+	#define IN_L3_IF_TBL_TTL_EXCEED_DE_ACCE
+	#define IN_L3_IF_TBL_TTL_EXCEED_DE_ACCE_OFFSET  34
+	#define IN_L3_IF_TBL_TTL_EXCEED_DE_ACCE_LEN     1
+	#define IN_L3_IF_TBL_TTL_EXCEED_DE_ACCE_DEFAULT 0x0
+	/*[field] MAC_BITMAP*/
+	#define IN_L3_IF_TBL_MAC_BITMAP
+	#define IN_L3_IF_TBL_MAC_BITMAP_OFFSET  35
+	#define IN_L3_IF_TBL_MAC_BITMAP_LEN     8
+	#define IN_L3_IF_TBL_MAC_BITMAP_DEFAULT 0x0
+	/*[field] PPPOE_EN*/
+	#define IN_L3_IF_TBL_PPPOE_EN
+	#define IN_L3_IF_TBL_PPPOE_EN_OFFSET  43
+	#define IN_L3_IF_TBL_PPPOE_EN_LEN     1
+	#define IN_L3_IF_TBL_PPPOE_EN_DEFAULT 0x0
+
+struct in_l3_if_tbl {
+	a_uint32_t  mru:14;
+	a_uint32_t  mtu:14;
+	a_uint32_t  ttl_dec_bypass:1;
+	a_uint32_t  ipv4_uc_route_en:1;
+	a_uint32_t  ipv6_uc_route_en:1;
+	a_uint32_t  icmp_trigger_en:1;
+	a_uint32_t  ttl_exceed_cmd:2;
+	a_uint32_t  ttl_exceed_de_acce:1;
+	a_uint32_t  mac_bitmap:8;
+	a_uint32_t  pppoe_en:1;
+	a_uint32_t  _reserved0:20;
+};
+
+union in_l3_if_tbl_u {
+	a_uint32_t val[2];
+	struct in_l3_if_tbl bf;
+};
+
+/*[table] HOST_IPV6_MCAST_TBL*/
+#define HOST_IPV6_MCAST_TBL
+#define HOST_IPV6_MCAST_TBL_ADDRESS 0x20000
+#define HOST_IPV6_MCAST_TBL_NUM     1536
+#define HOST_IPV6_MCAST_TBL_INC     0x40
+#define HOST_IPV6_MCAST_TBL_TYPE    REG_TYPE_RW
+#define HOST_IPV6_MCAST_TBL_DEFAULT 0x0
+	/*[field] VALID*/
+	#define HOST_IPV6_MCAST_TBL_VALID
+	#define HOST_IPV6_MCAST_TBL_VALID_OFFSET  0
+	#define HOST_IPV6_MCAST_TBL_VALID_LEN     1
+	#define HOST_IPV6_MCAST_TBL_VALID_DEFAULT 0x0
+	/*[field] KEY_TYPE*/
+	#define HOST_IPV6_MCAST_TBL_KEY_TYPE
+	#define HOST_IPV6_MCAST_TBL_KEY_TYPE_OFFSET  1
+	#define HOST_IPV6_MCAST_TBL_KEY_TYPE_LEN     2
+	#define HOST_IPV6_MCAST_TBL_KEY_TYPE_DEFAULT 0x0
+	/*[field] FWD_CMD*/
+	#define HOST_IPV6_MCAST_TBL_FWD_CMD
+	#define HOST_IPV6_MCAST_TBL_FWD_CMD_OFFSET  3
+	#define HOST_IPV6_MCAST_TBL_FWD_CMD_LEN     2
+	#define HOST_IPV6_MCAST_TBL_FWD_CMD_DEFAULT 0x0
+	/*[field] SYN_TOGGLE*/
+	#define HOST_IPV6_MCAST_TBL_SYN_TOGGLE
+	#define HOST_IPV6_MCAST_TBL_SYN_TOGGLE_OFFSET  5
+	#define HOST_IPV6_MCAST_TBL_SYN_TOGGLE_LEN     1
+	#define HOST_IPV6_MCAST_TBL_SYN_TOGGLE_DEFAULT 0x0
+	/*[field] DST_INFO*/
+	#define HOST_IPV6_MCAST_TBL_DST_INFO
+	#define HOST_IPV6_MCAST_TBL_DST_INFO_OFFSET  6
+	#define HOST_IPV6_MCAST_TBL_DST_INFO_LEN     14
+	#define HOST_IPV6_MCAST_TBL_DST_INFO_DEFAULT 0x0
+	/*[field] LAN_WAN*/
+	#define HOST_IPV6_MCAST_TBL_LAN_WAN
+	#define HOST_IPV6_MCAST_TBL_LAN_WAN_OFFSET  20
+	#define HOST_IPV6_MCAST_TBL_LAN_WAN_LEN     1
+	#define HOST_IPV6_MCAST_TBL_LAN_WAN_DEFAULT 0x0
+	/*[field] VSI*/
+	#define HOST_IPV6_MCAST_TBL_VSI
+	#define HOST_IPV6_MCAST_TBL_VSI_OFFSET  21
+	#define HOST_IPV6_MCAST_TBL_VSI_LEN     5
+	#define HOST_IPV6_MCAST_TBL_VSI_DEFAULT 0x0
+	/*[field] SIPV6_ADDR*/
+	#define HOST_IPV6_MCAST_TBL_SIPV6_ADDR
+	#define HOST_IPV6_MCAST_TBL_SIPV6_ADDR_OFFSET  44
+	#define HOST_IPV6_MCAST_TBL_SIPV6_ADDR_LEN     128
+	#define HOST_IPV6_MCAST_TBL_SIPV6_ADDR_DEFAULT 0x0
+	/*[field] GIPV6_ADDR*/
+	#define HOST_IPV6_MCAST_TBL_GIPV6_ADDR
+	#define HOST_IPV6_MCAST_TBL_GIPV6_ADDR_OFFSET  172
+	#define HOST_IPV6_MCAST_TBL_GIPV6_ADDR_LEN     128
+	#define HOST_IPV6_MCAST_TBL_GIPV6_ADDR_DEFAULT 0x0
+
+struct host_tbl {
+	a_uint32_t  valid:1;
+	a_uint32_t  key_type:2;
+	a_uint32_t  fwd_cmd:2;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  dst_info:14;
+	a_uint32_t  lan_wan:1;
+	a_uint32_t  _reserved0:11;
+	a_uint32_t  ip_addr:32;
+	a_uint32_t  _reserved1:32;
+};
+
+union host_tbl_u {
+	a_uint32_t val[3];
+	struct host_tbl bf;
+};
+
+/*[table] HOST_IPV4_MCAST_TBL*/
+#define HOST_IPV4_MCAST_TBL
+#define HOST_IPV4_MCAST_TBL_ADDRESS 0x20000
+#define HOST_IPV4_MCAST_TBL_NUM     3072
+#define HOST_IPV4_MCAST_TBL_INC     0x20
+#define HOST_IPV4_MCAST_TBL_TYPE    REG_TYPE_RW
+#define HOST_IPV4_MCAST_TBL_DEFAULT 0x0
+	/*[field] VALID*/
+	#define HOST_IPV4_MCAST_TBL_VALID
+	#define HOST_IPV4_MCAST_TBL_VALID_OFFSET  0
+	#define HOST_IPV4_MCAST_TBL_VALID_LEN     1
+	#define HOST_IPV4_MCAST_TBL_VALID_DEFAULT 0x0
+	/*[field] KEY_TYPE*/
+	#define HOST_IPV4_MCAST_TBL_KEY_TYPE
+	#define HOST_IPV4_MCAST_TBL_KEY_TYPE_OFFSET  1
+	#define HOST_IPV4_MCAST_TBL_KEY_TYPE_LEN     2
+	#define HOST_IPV4_MCAST_TBL_KEY_TYPE_DEFAULT 0x0
+	/*[field] FWD_CMD*/
+	#define HOST_IPV4_MCAST_TBL_FWD_CMD
+	#define HOST_IPV4_MCAST_TBL_FWD_CMD_OFFSET  3
+	#define HOST_IPV4_MCAST_TBL_FWD_CMD_LEN     2
+	#define HOST_IPV4_MCAST_TBL_FWD_CMD_DEFAULT 0x0
+	/*[field] SYN_TOGGLE*/
+	#define HOST_IPV4_MCAST_TBL_SYN_TOGGLE
+	#define HOST_IPV4_MCAST_TBL_SYN_TOGGLE_OFFSET  5
+	#define HOST_IPV4_MCAST_TBL_SYN_TOGGLE_LEN     1
+	#define HOST_IPV4_MCAST_TBL_SYN_TOGGLE_DEFAULT 0x0
+	/*[field] DST_INFO*/
+	#define HOST_IPV4_MCAST_TBL_DST_INFO
+	#define HOST_IPV4_MCAST_TBL_DST_INFO_OFFSET  6
+	#define HOST_IPV4_MCAST_TBL_DST_INFO_LEN     14
+	#define HOST_IPV4_MCAST_TBL_DST_INFO_DEFAULT 0x0
+	/*[field] LAN_WAN*/
+	#define HOST_IPV4_MCAST_TBL_LAN_WAN
+	#define HOST_IPV4_MCAST_TBL_LAN_WAN_OFFSET  20
+	#define HOST_IPV4_MCAST_TBL_LAN_WAN_LEN     1
+	#define HOST_IPV4_MCAST_TBL_LAN_WAN_DEFAULT 0x0
+	/*[field] VSI*/
+	#define HOST_IPV4_MCAST_TBL_VSI
+	#define HOST_IPV4_MCAST_TBL_VSI_OFFSET  21
+	#define HOST_IPV4_MCAST_TBL_VSI_LEN     5
+	#define HOST_IPV4_MCAST_TBL_VSI_DEFAULT 0x0
+	/*[field] SIP_ADDR*/
+	#define HOST_IPV4_MCAST_TBL_SIP_ADDR
+	#define HOST_IPV4_MCAST_TBL_SIP_ADDR_OFFSET  85
+	#define HOST_IPV4_MCAST_TBL_SIP_ADDR_LEN     32
+	#define HOST_IPV4_MCAST_TBL_SIP_ADDR_DEFAULT 0x0
+	/*[field] GIP_ADDR*/
+	#define HOST_IPV4_MCAST_TBL_GIP_ADDR
+	#define HOST_IPV4_MCAST_TBL_GIP_ADDR_OFFSET  117
+	#define HOST_IPV4_MCAST_TBL_GIP_ADDR_LEN     32
+	#define HOST_IPV4_MCAST_TBL_GIP_ADDR_DEFAULT 0x0
+
+struct host_ipv6_tbl {
+	a_uint32_t  valid:1;
+	a_uint32_t  key_type:2;
+	a_uint32_t  fwd_cmd:2;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  dst_info:14;
+	a_uint32_t  lan_wan:1;
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  ipv6_addr_0:10;
+	a_uint32_t  ipv6_addr_1:32;
+	a_uint32_t  ipv6_addr_2:32;
+	a_uint32_t  ipv6_addr_3:32;
+	a_uint32_t  ipv6_addr_4:22;
+	a_uint32_t  _reserved1:10;
+};
+
+union host_ipv6_tbl_u {
+	a_uint32_t val[5];
+	struct host_ipv6_tbl bf;
+};
+
+/*[table] HOST_TBL*/
+#define HOST_TBL
+#define HOST_TBL_ADDRESS 0x20000
+#define HOST_TBL_NUM     6144
+#define HOST_TBL_INC     0x10
+#define HOST_TBL_TYPE    REG_TYPE_RW
+#define HOST_TBL_DEFAULT 0x0
+	/*[field] VALID*/
+	#define HOST_TBL_VALID
+	#define HOST_TBL_VALID_OFFSET  0
+	#define HOST_TBL_VALID_LEN     1
+	#define HOST_TBL_VALID_DEFAULT 0x0
+	/*[field] KEY_TYPE*/
+	#define HOST_TBL_KEY_TYPE
+	#define HOST_TBL_KEY_TYPE_OFFSET  1
+	#define HOST_TBL_KEY_TYPE_LEN     2
+	#define HOST_TBL_KEY_TYPE_DEFAULT 0x0
+	/*[field] FWD_CMD*/
+	#define HOST_TBL_FWD_CMD
+	#define HOST_TBL_FWD_CMD_OFFSET  3
+	#define HOST_TBL_FWD_CMD_LEN     2
+	#define HOST_TBL_FWD_CMD_DEFAULT 0x0
+	/*[field] SYN_TOGGLE*/
+	#define HOST_TBL_SYN_TOGGLE
+	#define HOST_TBL_SYN_TOGGLE_OFFSET  5
+	#define HOST_TBL_SYN_TOGGLE_LEN     1
+	#define HOST_TBL_SYN_TOGGLE_DEFAULT 0x0
+	/*[field] DST_INFO*/
+	#define HOST_TBL_DST_INFO
+	#define HOST_TBL_DST_INFO_OFFSET  6
+	#define HOST_TBL_DST_INFO_LEN     14
+	#define HOST_TBL_DST_INFO_DEFAULT 0x0
+	/*[field] LAN_WAN*/
+	#define HOST_TBL_LAN_WAN
+	#define HOST_TBL_LAN_WAN_OFFSET  20
+	#define HOST_TBL_LAN_WAN_LEN     1
+	#define HOST_TBL_LAN_WAN_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define HOST_TBL_IP_ADDR
+	#define HOST_TBL_IP_ADDR_OFFSET  32
+	#define HOST_TBL_IP_ADDR_LEN     32
+	#define HOST_TBL_IP_ADDR_DEFAULT 0x0
+
+struct host_ipv4_mcast_tbl {
+	a_uint32_t  valid:1;
+	a_uint32_t  key_type:2;
+	a_uint32_t  fwd_cmd:2;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  dst_info:14;
+	a_uint32_t  lan_wan:1;
+	a_uint32_t  vsi:5;
+	a_uint32_t  _reserved0_0:6;
+	a_uint32_t  _reserved0_1:32;
+	a_uint32_t  _reserved0_2:21;
+	a_uint32_t  sip_addr_0:11;
+	a_uint32_t  sip_addr_1:21;
+	a_uint32_t  gip_addr_0:11;
+	a_uint32_t  gip_addr_1:21;
+	a_uint32_t  _reserved1:11;
+};
+
+union host_ipv4_mcast_tbl_u {
+	a_uint32_t val[5];
+	struct host_ipv4_mcast_tbl bf;
+};
+
+/*[table] HOST_IPV6_TBL*/
+#define HOST_IPV6_TBL
+#define HOST_IPV6_TBL_ADDRESS 0x20000
+#define HOST_IPV6_TBL_NUM     3072
+#define HOST_IPV6_TBL_INC     0x20
+#define HOST_IPV6_TBL_TYPE    REG_TYPE_RW
+#define HOST_IPV6_TBL_DEFAULT 0x0
+	/*[field] VALID*/
+	#define HOST_IPV6_TBL_VALID
+	#define HOST_IPV6_TBL_VALID_OFFSET  0
+	#define HOST_IPV6_TBL_VALID_LEN     1
+	#define HOST_IPV6_TBL_VALID_DEFAULT 0x0
+	/*[field] KEY_TYPE*/
+	#define HOST_IPV6_TBL_KEY_TYPE
+	#define HOST_IPV6_TBL_KEY_TYPE_OFFSET  1
+	#define HOST_IPV6_TBL_KEY_TYPE_LEN     2
+	#define HOST_IPV6_TBL_KEY_TYPE_DEFAULT 0x0
+	/*[field] FWD_CMD*/
+	#define HOST_IPV6_TBL_FWD_CMD
+	#define HOST_IPV6_TBL_FWD_CMD_OFFSET  3
+	#define HOST_IPV6_TBL_FWD_CMD_LEN     2
+	#define HOST_IPV6_TBL_FWD_CMD_DEFAULT 0x0
+	/*[field] SYN_TOGGLE*/
+	#define HOST_IPV6_TBL_SYN_TOGGLE
+	#define HOST_IPV6_TBL_SYN_TOGGLE_OFFSET  5
+	#define HOST_IPV6_TBL_SYN_TOGGLE_LEN     1
+	#define HOST_IPV6_TBL_SYN_TOGGLE_DEFAULT 0x0
+	/*[field] DST_INFO*/
+	#define HOST_IPV6_TBL_DST_INFO
+	#define HOST_IPV6_TBL_DST_INFO_OFFSET  6
+	#define HOST_IPV6_TBL_DST_INFO_LEN     14
+	#define HOST_IPV6_TBL_DST_INFO_DEFAULT 0x0
+	/*[field] LAN_WAN*/
+	#define HOST_IPV6_TBL_LAN_WAN
+	#define HOST_IPV6_TBL_LAN_WAN_OFFSET  20
+	#define HOST_IPV6_TBL_LAN_WAN_LEN     1
+	#define HOST_IPV6_TBL_LAN_WAN_DEFAULT 0x0
+	/*[field] IPV6_ADDR*/
+	#define HOST_IPV6_TBL_IPV6_ADDR
+	#define HOST_IPV6_TBL_IPV6_ADDR_OFFSET  22
+	#define HOST_IPV6_TBL_IPV6_ADDR_LEN     128
+	#define HOST_IPV6_TBL_IPV6_ADDR_DEFAULT 0x0
+
+struct host_ipv6_mcast_tbl {
+	a_uint32_t  valid:1;
+	a_uint32_t  key_type:2;
+	a_uint32_t  fwd_cmd:2;
+	a_uint32_t  syn_toggle:1;
+	a_uint32_t  dst_info:14;
+	a_uint32_t  lan_wan:1;
+	a_uint32_t  vsi:5;
+	a_uint32_t  _reserved0_0:6;
+	a_uint32_t  _reserved0_1:12;
+	a_uint32_t  sipv6_addr_0:20;
+	a_uint32_t  sipv6_addr_1:32;
+	a_uint32_t  sipv6_addr_2:32;
+	a_uint32_t  sipv6_addr_3:32;
+	a_uint32_t  sipv6_addr_4:12;
+	a_uint32_t  gipv6_addr_0:20;
+	a_uint32_t  gipv6_addr_1:32;
+	a_uint32_t  gipv6_addr_2:32;
+	a_uint32_t  gipv6_addr_3:32;
+	a_uint32_t  gipv6_addr_4:12;
+	a_uint32_t  _reserved1:20;
+};
+
+union host_ipv6_mcast_tbl_u {
+	a_uint32_t val[10];
+	struct host_ipv6_mcast_tbl bf;
+};
+
+/*[table] IN_NEXTHOP_TBL*/
+#define IN_NEXTHOP_TBL
+#define IN_NEXTHOP_TBL_ADDRESS 0x60000
+#define IN_NEXTHOP_TBL_NUM     2560
+#define IN_NEXTHOP_TBL_INC     0x10
+#define IN_NEXTHOP_TBL_TYPE    REG_TYPE_RW
+#define IN_NEXTHOP_TBL_DEFAULT 0x0
+	/*[field] TYPE*/
+	#define IN_NEXTHOP_TBL_TYPE_F
+	#define IN_NEXTHOP_TBL_TYPE_F_OFFSET  0
+	#define IN_NEXTHOP_TBL_TYPE_F_LEN     1
+	#define IN_NEXTHOP_TBL_TYPE_F_DEFAULT 0x0
+	/*[field] PORT reuse TYPE[0]*/
+	#define IN_NEXTHOP_TBL_PORT
+	#define IN_NEXTHOP_TBL_PORT_OFFSET  1
+	#define IN_NEXTHOP_TBL_PORT_LEN     8
+	#define IN_NEXTHOP_TBL_PORT_DEFAULT 0x0
+	/*[field] VSI reuse TYPE[1]*/
+	#define IN_NEXTHOP_TBL_VSI
+	#define IN_NEXTHOP_TBL_VSI_OFFSET  1
+	#define IN_NEXTHOP_TBL_VSI_LEN     5
+	#define IN_NEXTHOP_TBL_VSI_DEFAULT 0x0
+	/*[field] POST_L3_IF*/
+	#define IN_NEXTHOP_TBL_POST_L3_IF
+	#define IN_NEXTHOP_TBL_POST_L3_IF_OFFSET  9
+	#define IN_NEXTHOP_TBL_POST_L3_IF_LEN     8
+	#define IN_NEXTHOP_TBL_POST_L3_IF_DEFAULT 0x0
+	/*[field] IP_TO_ME*/
+	#define IN_NEXTHOP_TBL_IP_TO_ME
+	#define IN_NEXTHOP_TBL_IP_TO_ME_OFFSET  17
+	#define IN_NEXTHOP_TBL_IP_TO_ME_LEN     1
+	#define IN_NEXTHOP_TBL_IP_TO_ME_DEFAULT 0x0
+	/*[field] STAG_FMT*/
+	#define IN_NEXTHOP_TBL_STAG_FMT
+	#define IN_NEXTHOP_TBL_STAG_FMT_OFFSET  18
+	#define IN_NEXTHOP_TBL_STAG_FMT_LEN     1
+	#define IN_NEXTHOP_TBL_STAG_FMT_DEFAULT 0x0
+	/*[field] SVID*/
+	#define IN_NEXTHOP_TBL_SVID
+	#define IN_NEXTHOP_TBL_SVID_OFFSET  19
+	#define IN_NEXTHOP_TBL_SVID_LEN     12
+	#define IN_NEXTHOP_TBL_SVID_DEFAULT 0x0
+	/*[field] CTAG_FMT*/
+	#define IN_NEXTHOP_TBL_CTAG_FMT
+	#define IN_NEXTHOP_TBL_CTAG_FMT_OFFSET  31
+	#define IN_NEXTHOP_TBL_CTAG_FMT_LEN     1
+	#define IN_NEXTHOP_TBL_CTAG_FMT_DEFAULT 0x0
+	/*[field] CVID*/
+	#define IN_NEXTHOP_TBL_CVID
+	#define IN_NEXTHOP_TBL_CVID_OFFSET  32
+	#define IN_NEXTHOP_TBL_CVID_LEN     12
+	#define IN_NEXTHOP_TBL_CVID_DEFAULT 0x0
+	/*[field] IP_PUB_ADDR_INDEX*/
+	#define IN_NEXTHOP_TBL_IP_PUB_ADDR_INDEX
+	#define IN_NEXTHOP_TBL_IP_PUB_ADDR_INDEX_OFFSET  44
+	#define IN_NEXTHOP_TBL_IP_PUB_ADDR_INDEX_LEN     4
+	#define IN_NEXTHOP_TBL_IP_PUB_ADDR_INDEX_DEFAULT 0x0
+	/*[field] MAC_ADDR*/
+	#define IN_NEXTHOP_TBL_MAC_ADDR
+	#define IN_NEXTHOP_TBL_MAC_ADDR_OFFSET  48
+	#define IN_NEXTHOP_TBL_MAC_ADDR_LEN     48
+	#define IN_NEXTHOP_TBL_MAC_ADDR_DEFAULT 0x0
+	/*[field] IP_ADDR_DNAT*/
+	#define IN_NEXTHOP_TBL_IP_ADDR_DNAT
+	#define IN_NEXTHOP_TBL_IP_ADDR_DNAT_OFFSET  96
+	#define IN_NEXTHOP_TBL_IP_ADDR_DNAT_LEN     32
+	#define IN_NEXTHOP_TBL_IP_ADDR_DNAT_DEFAULT 0x0
+
+struct in_nexthop_tbl_1 {
+	a_uint32_t  type:1;
+	a_uint32_t  vsi:5;
+	a_uint32_t  _reserved0:3;
+	a_uint32_t  post_l3_if:8;
+	a_uint32_t  ip_to_me:1;
+	a_uint32_t  stag_fmt:1;
+	a_uint32_t  svid:12;
+	a_uint32_t  ctag_fmt:1;
+	a_uint32_t  cvid:12;
+	a_uint32_t  ip_pub_addr_index:4;
+	a_uint32_t  mac_addr_0:16;
+	a_uint32_t  mac_addr_1:32;
+	a_uint32_t  ip_addr_dnat:32;
+};
+
+struct in_nexthop_tbl_0 {
+	a_uint32_t  type:1;
+	a_uint32_t  port:8;
+	a_uint32_t  post_l3_if:8;
+	a_uint32_t  ip_to_me:1;
+	a_uint32_t  stag_fmt:1;
+	a_uint32_t  svid:12;
+	a_uint32_t  ctag_fmt:1;
+	a_uint32_t  cvid:12;
+	a_uint32_t  ip_pub_addr_index:4;
+	a_uint32_t  mac_addr_0:16;
+	a_uint32_t  mac_addr_1:32;
+	a_uint32_t  ip_addr_dnat:32;
+};
+
+union in_nexthop_tbl_u {
+	a_uint32_t val[4];
+	struct in_nexthop_tbl_0 bf0;
+	struct in_nexthop_tbl_1 bf1;
+};
+
+/*[table] EG_L3_IF_TBL*/
+#define EG_L3_IF_TBL
+#define EG_L3_IF_TBL_ADDRESS 0xe000
+#define EG_L3_IF_TBL_NUM     256
+#define EG_L3_IF_TBL_INC     0x10
+#define EG_L3_IF_TBL_TYPE    REG_TYPE_RW
+#define EG_L3_IF_TBL_DEFAULT 0x0
+	/*[field] MAC_ADDR*/
+	#define EG_L3_IF_TBL_MAC_ADDR
+	#define EG_L3_IF_TBL_MAC_ADDR_OFFSET  0
+	#define EG_L3_IF_TBL_MAC_ADDR_LEN     48
+	#define EG_L3_IF_TBL_MAC_ADDR_DEFAULT 0x0
+	/*[field] SESSION_ID*/
+	#define EG_L3_IF_TBL_SESSION_ID
+	#define EG_L3_IF_TBL_SESSION_ID_OFFSET  48
+	#define EG_L3_IF_TBL_SESSION_ID_LEN     16
+	#define EG_L3_IF_TBL_SESSION_ID_DEFAULT 0x0
+	/*[field] PPPOE_EN*/
+	#define EG_L3_IF_TBL_PPPOE_EN
+	#define EG_L3_IF_TBL_PPPOE_EN_OFFSET  64
+	#define EG_L3_IF_TBL_PPPOE_EN_LEN     1
+	#define EG_L3_IF_TBL_PPPOE_EN_DEFAULT 0x0
+
+struct eg_l3_if_tbl {
+	a_uint32_t  mac_addr_0:32;
+	a_uint32_t  mac_addr_1:16;
+	a_uint32_t  session_id:16;
+	a_uint32_t  pppoe_en:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union eg_l3_if_tbl_u {
+	a_uint32_t val[3];
+	struct eg_l3_if_tbl bf;
+};
+
+/*[table] RT_INTERFACE_CNT_TBL*/
+#define RT_INTERFACE_CNT_TBL
+#define RT_INTERFACE_CNT_TBL_ADDRESS 0x40000
+#define RT_INTERFACE_CNT_TBL_NUM     512
+#define RT_INTERFACE_CNT_TBL_INC     0x20
+#define RT_INTERFACE_CNT_TBL_TYPE    REG_TYPE_RW
+#define RT_INTERFACE_CNT_TBL_DEFAULT 0x0
+	/*[field] PKT_CNT*/
+	#define RT_INTERFACE_CNT_TBL_PKT_CNT
+	#define RT_INTERFACE_CNT_TBL_PKT_CNT_OFFSET  0
+	#define RT_INTERFACE_CNT_TBL_PKT_CNT_LEN     32
+	#define RT_INTERFACE_CNT_TBL_PKT_CNT_DEFAULT 0x0
+	/*[field] BYTE_CNT*/
+	#define RT_INTERFACE_CNT_TBL_BYTE_CNT
+	#define RT_INTERFACE_CNT_TBL_BYTE_CNT_OFFSET  32
+	#define RT_INTERFACE_CNT_TBL_BYTE_CNT_LEN     40
+	#define RT_INTERFACE_CNT_TBL_BYTE_CNT_DEFAULT 0x0
+	/*[field] DROP_PKT_CNT*/
+	#define RT_INTERFACE_CNT_TBL_DROP_PKT_CNT
+	#define RT_INTERFACE_CNT_TBL_DROP_PKT_CNT_OFFSET  72
+	#define RT_INTERFACE_CNT_TBL_DROP_PKT_CNT_LEN     32
+	#define RT_INTERFACE_CNT_TBL_DROP_PKT_CNT_DEFAULT 0x0
+	/*[field] DROP_BYTE_CNT*/
+	#define RT_INTERFACE_CNT_TBL_DROP_BYTE_CNT
+	#define RT_INTERFACE_CNT_TBL_DROP_BYTE_CNT_OFFSET  104
+	#define RT_INTERFACE_CNT_TBL_DROP_BYTE_CNT_LEN     40
+	#define RT_INTERFACE_CNT_TBL_DROP_BYTE_CNT_DEFAULT 0x0
+
+struct rt_interface_cnt_tbl {
+	a_uint32_t  pkt_cnt:32;
+	a_uint32_t  byte_cnt_0:32;
+	a_uint32_t  byte_cnt_1:8;
+	a_uint32_t  drop_pkt_cnt_0:24;
+	a_uint32_t  drop_pkt_cnt_1:8;
+	a_uint32_t  drop_byte_cnt_0:24;
+	a_uint32_t  drop_byte_cnt_1:16;
+	a_uint32_t  _reserved0:16;
+};
+
+union rt_interface_cnt_tbl_u {
+	a_uint32_t val[5];
+	struct rt_interface_cnt_tbl bf;
+};
+
+
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_mib.h b/qca-ssdk/include/hsl/hppe/hppe_mib.h
new file mode 100755
index 0000000..a80dd30
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_mib.h
@@ -0,0 +1,1150 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_MIB_H_
+#define _HPPE_MIB_H_
+
+#define MAC_MIB_CTRL_MAX_ENTRY	6
+#define RXBROAD_MAX_ENTRY	6
+#define RXPAUSE_MAX_ENTRY	6
+#define RXMULTI_MAX_ENTRY	6
+#define RXFCSERR_MAX_ENTRY	6
+#define RXALIGNERR_MAX_ENTRY	6
+#define RXRUNT_MAX_ENTRY	6
+#define RXFRAG_MAX_ENTRY	6
+#define RXJUMBOFCSERR_MAX_ENTRY	6
+#define RXJUMBOALIGNERR_MAX_ENTRY	6
+#define RXPKT64_MAX_ENTRY	6
+#define RXPKT65TO127_MAX_ENTRY	6
+#define RXPKT128TO255_MAX_ENTRY	6
+#define RXPKT256TO511_MAX_ENTRY	6
+#define RXPKT512TO1023_MAX_ENTRY	6
+#define RXPKT1024TO1518_MAX_ENTRY	6
+#define RXPKT1519TOX_MAX_ENTRY	6
+#define RXTOOLONG_MAX_ENTRY	6
+#define RXGOODBYTE_L_MAX_ENTRY	6
+#define RXGOODBYTE_H_MAX_ENTRY	6
+#define RXBADBYTE_L_MAX_ENTRY	6
+#define RXBADBYTE_H_MAX_ENTRY	6
+#define RXUNI_MAX_ENTRY	6
+#define TXBROAD_MAX_ENTRY	6
+#define TXPAUSE_MAX_ENTRY	6
+#define TXMULTI_MAX_ENTRY	6
+#define TXUNDERRUN_MAX_ENTRY	6
+#define TXPKT64_MAX_ENTRY	6
+#define TXPKT65TO127_MAX_ENTRY	6
+#define TXPKT128TO255_MAX_ENTRY	6
+#define TXPKT256TO511_MAX_ENTRY	6
+#define TXPKT512TO1023_MAX_ENTRY	6
+#define TXPKT1024TO1518_MAX_ENTRY	6
+#define TXPKT1519TOX_MAX_ENTRY	6
+#define TXBYTE_L_MAX_ENTRY	6
+#define TXBYTE_H_MAX_ENTRY	6
+#define TXCOLLISIONS_MAX_ENTRY	6
+#define TXABORTCOL_MAX_ENTRY	6
+#define TXMULTICOL_MAX_ENTRY	6
+#define TXSINGLECOL_MAX_ENTRY	6
+#define TXEXCESSIVEDEFER_MAX_ENTRY	6
+#define TXDEFER_MAX_ENTRY	6
+#define TXLATECOL_MAX_ENTRY	6
+#define TXUNI_MAX_ENTRY	6
+
+
+sw_error_t
+hppe_mac_mib_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_mib_ctrl_u *value);
+
+sw_error_t
+hppe_mac_mib_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_mib_ctrl_u *value);
+
+sw_error_t
+hppe_rxbroad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxbroad_u *value);
+
+sw_error_t
+hppe_rxbroad_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxbroad_u *value);
+
+sw_error_t
+hppe_rxpause_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpause_u *value);
+
+sw_error_t
+hppe_rxpause_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpause_u *value);
+
+sw_error_t
+hppe_rxmulti_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxmulti_u *value);
+
+sw_error_t
+hppe_rxmulti_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxmulti_u *value);
+
+sw_error_t
+hppe_rxfcserr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxfcserr_u *value);
+
+sw_error_t
+hppe_rxfcserr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxfcserr_u *value);
+
+sw_error_t
+hppe_rxalignerr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxalignerr_u *value);
+
+sw_error_t
+hppe_rxalignerr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxalignerr_u *value);
+
+sw_error_t
+hppe_rxrunt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxrunt_u *value);
+
+sw_error_t
+hppe_rxrunt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxrunt_u *value);
+
+sw_error_t
+hppe_rxfrag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxfrag_u *value);
+
+sw_error_t
+hppe_rxfrag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxfrag_u *value);
+
+sw_error_t
+hppe_rxjumbofcserr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxjumbofcserr_u *value);
+
+sw_error_t
+hppe_rxjumbofcserr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxjumbofcserr_u *value);
+
+sw_error_t
+hppe_rxjumboalignerr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxjumboalignerr_u *value);
+
+sw_error_t
+hppe_rxjumboalignerr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxjumboalignerr_u *value);
+
+sw_error_t
+hppe_rxpkt64_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt64_u *value);
+
+sw_error_t
+hppe_rxpkt64_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt64_u *value);
+
+sw_error_t
+hppe_rxpkt65to127_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt65to127_u *value);
+
+sw_error_t
+hppe_rxpkt65to127_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt65to127_u *value);
+
+sw_error_t
+hppe_rxpkt128to255_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt128to255_u *value);
+
+sw_error_t
+hppe_rxpkt128to255_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt128to255_u *value);
+
+sw_error_t
+hppe_rxpkt256to511_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt256to511_u *value);
+
+sw_error_t
+hppe_rxpkt256to511_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt256to511_u *value);
+
+sw_error_t
+hppe_rxpkt512to1023_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt512to1023_u *value);
+
+sw_error_t
+hppe_rxpkt512to1023_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt512to1023_u *value);
+
+sw_error_t
+hppe_rxpkt1024to1518_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt1024to1518_u *value);
+
+sw_error_t
+hppe_rxpkt1024to1518_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt1024to1518_u *value);
+
+sw_error_t
+hppe_rxpkt1519tox_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt1519tox_u *value);
+
+sw_error_t
+hppe_rxpkt1519tox_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt1519tox_u *value);
+
+sw_error_t
+hppe_rxtoolong_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxtoolong_u *value);
+
+sw_error_t
+hppe_rxtoolong_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxtoolong_u *value);
+
+sw_error_t
+hppe_rxgoodbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxgoodbyte_l_u *value);
+
+sw_error_t
+hppe_rxgoodbyte_l_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxgoodbyte_l_u *value);
+
+sw_error_t
+hppe_rxgoodbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxgoodbyte_h_u *value);
+
+sw_error_t
+hppe_rxgoodbyte_h_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxgoodbyte_h_u *value);
+
+sw_error_t
+hppe_rxbadbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxbadbyte_l_u *value);
+
+sw_error_t
+hppe_rxbadbyte_l_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxbadbyte_l_u *value);
+
+sw_error_t
+hppe_rxbadbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxbadbyte_h_u *value);
+
+sw_error_t
+hppe_rxbadbyte_h_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxbadbyte_h_u *value);
+
+sw_error_t
+hppe_rxuni_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxuni_u *value);
+
+sw_error_t
+hppe_rxuni_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxuni_u *value);
+
+sw_error_t
+hppe_txbroad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txbroad_u *value);
+
+sw_error_t
+hppe_txbroad_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txbroad_u *value);
+
+sw_error_t
+hppe_txpause_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpause_u *value);
+
+sw_error_t
+hppe_txpause_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpause_u *value);
+
+sw_error_t
+hppe_txmulti_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txmulti_u *value);
+
+sw_error_t
+hppe_txmulti_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txmulti_u *value);
+
+sw_error_t
+hppe_txunderrun_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txunderrun_u *value);
+
+sw_error_t
+hppe_txunderrun_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txunderrun_u *value);
+
+sw_error_t
+hppe_txpkt64_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt64_u *value);
+
+sw_error_t
+hppe_txpkt64_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt64_u *value);
+
+sw_error_t
+hppe_txpkt65to127_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt65to127_u *value);
+
+sw_error_t
+hppe_txpkt65to127_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt65to127_u *value);
+
+sw_error_t
+hppe_txpkt128to255_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt128to255_u *value);
+
+sw_error_t
+hppe_txpkt128to255_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt128to255_u *value);
+
+sw_error_t
+hppe_txpkt256to511_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt256to511_u *value);
+
+sw_error_t
+hppe_txpkt256to511_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt256to511_u *value);
+
+sw_error_t
+hppe_txpkt512to1023_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt512to1023_u *value);
+
+sw_error_t
+hppe_txpkt512to1023_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt512to1023_u *value);
+
+sw_error_t
+hppe_txpkt1024to1518_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt1024to1518_u *value);
+
+sw_error_t
+hppe_txpkt1024to1518_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt1024to1518_u *value);
+
+sw_error_t
+hppe_txpkt1519tox_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt1519tox_u *value);
+
+sw_error_t
+hppe_txpkt1519tox_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt1519tox_u *value);
+
+sw_error_t
+hppe_txbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txbyte_l_u *value);
+
+sw_error_t
+hppe_txbyte_l_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txbyte_l_u *value);
+
+sw_error_t
+hppe_txbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txbyte_h_u *value);
+
+sw_error_t
+hppe_txbyte_h_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txbyte_h_u *value);
+
+sw_error_t
+hppe_txcollisions_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txcollisions_u *value);
+
+sw_error_t
+hppe_txcollisions_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txcollisions_u *value);
+
+sw_error_t
+hppe_txabortcol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txabortcol_u *value);
+
+sw_error_t
+hppe_txabortcol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txabortcol_u *value);
+
+sw_error_t
+hppe_txmulticol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txmulticol_u *value);
+
+sw_error_t
+hppe_txmulticol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txmulticol_u *value);
+
+sw_error_t
+hppe_txsinglecol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txsinglecol_u *value);
+
+sw_error_t
+hppe_txsinglecol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txsinglecol_u *value);
+
+sw_error_t
+hppe_txexcessivedefer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txexcessivedefer_u *value);
+
+sw_error_t
+hppe_txexcessivedefer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txexcessivedefer_u *value);
+
+sw_error_t
+hppe_txdefer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txdefer_u *value);
+
+sw_error_t
+hppe_txdefer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txdefer_u *value);
+
+sw_error_t
+hppe_txlatecol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txlatecol_u *value);
+
+sw_error_t
+hppe_txlatecol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txlatecol_u *value);
+
+sw_error_t
+hppe_txuni_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txuni_u *value);
+
+sw_error_t
+hppe_txuni_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txuni_u *value);
+
+sw_error_t
+hppe_mac_mib_ctrl_mib_reset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_mib_ctrl_mib_reset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_mib_ctrl_mib_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_mib_ctrl_mib_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_mib_ctrl_mib_rd_clr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_mib_ctrl_mib_rd_clr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxbroad_rxbroad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxbroad_rxbroad_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxpause_rxpause_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxpause_rxpause_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxmulti_rxmulti_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxmulti_rxmulti_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxfcserr_rxfcserr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxfcserr_rxfcserr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxalignerr_rxalignerr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxalignerr_rxalignerr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxrunt_rxrunt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxrunt_rxrunt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxfrag_rxfrag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxfrag_rxfrag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxjumbofcserr_rxjumbofcserr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxjumbofcserr_rxjumbofcserr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxjumboalignerr_rxjumboalignerr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxjumboalignerr_rxjumboalignerr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxpkt64_rxpkt64_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxpkt64_rxpkt64_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxpkt65to127_rxpkt65to127_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxpkt65to127_rxpkt65to127_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxpkt128to255_rxpkt128to255_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxpkt128to255_rxpkt128to255_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxpkt256to511_rxpkt256to511_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxpkt256to511_rxpkt256to511_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxpkt512to1023_rxpkt512to1023_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxpkt512to1023_rxpkt512to1023_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxpkt1024to1518_rxpkt1024to1518_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxpkt1024to1518_rxpkt1024to1518_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxpkt1519tox_rxpkt1519tox_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxpkt1519tox_rxpkt1519tox_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxtoolong_rxtoolong_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxtoolong_rxtoolong_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxgoodbyte_l_rxgoodbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxgoodbyte_l_rxgoodbyte_l_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxgoodbyte_h_rxgoodbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxgoodbyte_h_rxgoodbyte_h_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxbadbyte_l_rxbadbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxbadbyte_l_rxbadbyte_l_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxbadbyte_h_rxbadbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxbadbyte_h_rxbadbyte_h_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rxuni_rxuni_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rxuni_rxuni_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txbroad_txbroad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txbroad_txbroad_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txpause_txpause_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txpause_txpause_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txmulti_txmulti_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txmulti_txmulti_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txunderrun_txunderrun_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txunderrun_txunderrun_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txpkt64_txpkt64_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txpkt64_txpkt64_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txpkt65to127_txpkt65to127_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txpkt65to127_txpkt65to127_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txpkt128to255_txpkt128to255_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txpkt128to255_txpkt128to255_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txpkt256to511_txpkt256to511_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txpkt256to511_txpkt256to511_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txpkt512to1023_txpkt512to1023_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txpkt512to1023_txpkt512to1023_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txpkt1024to1518_txpkt1024to1518_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txpkt1024to1518_txpkt1024to1518_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txpkt1519tox_txpkt1519tox_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txpkt1519tox_txpkt1519tox_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txbyte_l_txbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txbyte_l_txbyte_l_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txbyte_h_txbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txbyte_h_txbyte_h_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txcollisions_txcollisions_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txcollisions_txcollisions_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txabortcol_txabortcol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txabortcol_txabortcol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txmulticol_txmulticol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txmulticol_txmulticol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txsinglecol_txsinglecol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txsinglecol_txsinglecol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txexcessivedefer_txexcessivedefer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txexcessivedefer_txexcessivedefer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txdefer_txdefer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txdefer_txdefer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txlatecol_txlatecol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txlatecol_txlatecol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_txuni_txuni_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_txuni_txuni_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_mib_reg.h b/qca-ssdk/include/hsl/hppe/hppe_mib_reg.h
new file mode 100755
index 0000000..476d5e8
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_mib_reg.h
@@ -0,0 +1,1006 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_MIB_REG_H
+#define HPPE_MIB_REG_H
+
+/*[register] MAC_MIB_CTRL*/
+#define MAC_MIB_CTRL
+#define MAC_MIB_CTRL_ADDRESS 0x34
+#define MAC_MIB_CTRL_NUM     6
+#define MAC_MIB_CTRL_INC     0x200
+#define MAC_MIB_CTRL_TYPE    REG_TYPE_RW
+#define MAC_MIB_CTRL_DEFAULT 0x0
+	/*[field] MIB_EN*/
+	#define MAC_MIB_CTRL_MIB_EN
+	#define MAC_MIB_CTRL_MIB_EN_OFFSET  0
+	#define MAC_MIB_CTRL_MIB_EN_LEN     1
+	#define MAC_MIB_CTRL_MIB_EN_DEFAULT 0x0
+	/*[field] MIB_RESET*/
+	#define MAC_MIB_CTRL_MIB_RESET
+	#define MAC_MIB_CTRL_MIB_RESET_OFFSET  1
+	#define MAC_MIB_CTRL_MIB_RESET_LEN     1
+	#define MAC_MIB_CTRL_MIB_RESET_DEFAULT 0x0
+	/*[field] MIB_RD_CLR*/
+	#define MAC_MIB_CTRL_MIB_RD_CLR
+	#define MAC_MIB_CTRL_MIB_RD_CLR_OFFSET  2
+	#define MAC_MIB_CTRL_MIB_RD_CLR_LEN     1
+	#define MAC_MIB_CTRL_MIB_RD_CLR_DEFAULT 0x0
+
+struct mac_mib_ctrl {
+	a_uint32_t  mib_en:1;
+	a_uint32_t  mib_reset:1;
+	a_uint32_t  mib_rd_clr:1;
+	a_uint32_t  _reserved0:29;
+};
+
+union mac_mib_ctrl_u {
+	a_uint32_t val;
+	struct mac_mib_ctrl bf;
+};
+
+/*[register] RXBROAD*/
+#define RXBROAD
+#define RXBROAD_ADDRESS 0x40
+#define RXBROAD_NUM     6
+#define RXBROAD_INC     0x200
+#define RXBROAD_TYPE    REG_TYPE_RO
+#define RXBROAD_DEFAULT 0x0
+	/*[field] RXBROAD*/
+	#define RXBROAD_RXBROAD
+	#define RXBROAD_RXBROAD_OFFSET  0
+	#define RXBROAD_RXBROAD_LEN     32
+	#define RXBROAD_RXBROAD_DEFAULT 0x0
+
+struct rxbroad {
+	a_uint32_t  rxbroad:32;
+};
+
+union rxbroad_u {
+	a_uint32_t val;
+	struct rxbroad bf;
+};
+
+/*[register] RXPAUSE*/
+#define RXPAUSE
+#define RXPAUSE_ADDRESS 0x44
+#define RXPAUSE_NUM     6
+#define RXPAUSE_INC     0x200
+#define RXPAUSE_TYPE    REG_TYPE_RO
+#define RXPAUSE_DEFAULT 0x0
+	/*[field] RXPAUSE*/
+	#define RXPAUSE_RXPAUSE
+	#define RXPAUSE_RXPAUSE_OFFSET  0
+	#define RXPAUSE_RXPAUSE_LEN     32
+	#define RXPAUSE_RXPAUSE_DEFAULT 0x0
+
+struct rxpause {
+	a_uint32_t  rxpause:32;
+};
+
+union rxpause_u {
+	a_uint32_t val;
+	struct rxpause bf;
+};
+
+/*[register] RXMULTI*/
+#define RXMULTI
+#define RXMULTI_ADDRESS 0x48
+#define RXMULTI_NUM     6
+#define RXMULTI_INC     0x200
+#define RXMULTI_TYPE    REG_TYPE_RO
+#define RXMULTI_DEFAULT 0x0
+	/*[field] RXMULTI*/
+	#define RXMULTI_RXMULTI
+	#define RXMULTI_RXMULTI_OFFSET  0
+	#define RXMULTI_RXMULTI_LEN     32
+	#define RXMULTI_RXMULTI_DEFAULT 0x0
+
+struct rxmulti {
+	a_uint32_t  rxmulti:32;
+};
+
+union rxmulti_u {
+	a_uint32_t val;
+	struct rxmulti bf;
+};
+
+/*[register] RXFCSERR*/
+#define RXFCSERR
+#define RXFCSERR_ADDRESS 0x4c
+#define RXFCSERR_NUM     6
+#define RXFCSERR_INC     0x200
+#define RXFCSERR_TYPE    REG_TYPE_RO
+#define RXFCSERR_DEFAULT 0x0
+	/*[field] RXFCSERR*/
+	#define RXFCSERR_RXFCSERR
+	#define RXFCSERR_RXFCSERR_OFFSET  0
+	#define RXFCSERR_RXFCSERR_LEN     32
+	#define RXFCSERR_RXFCSERR_DEFAULT 0x0
+
+struct rxfcserr {
+	a_uint32_t  rxfcserr:32;
+};
+
+union rxfcserr_u {
+	a_uint32_t val;
+	struct rxfcserr bf;
+};
+
+/*[register] RXALIGNERR*/
+#define RXALIGNERR
+#define RXALIGNERR_ADDRESS 0x50
+#define RXALIGNERR_NUM     6
+#define RXALIGNERR_INC     0x200
+#define RXALIGNERR_TYPE    REG_TYPE_RO
+#define RXALIGNERR_DEFAULT 0x0
+	/*[field] RXALIGNERR*/
+	#define RXALIGNERR_RXALIGNERR
+	#define RXALIGNERR_RXALIGNERR_OFFSET  0
+	#define RXALIGNERR_RXALIGNERR_LEN     32
+	#define RXALIGNERR_RXALIGNERR_DEFAULT 0x0
+
+struct rxalignerr {
+	a_uint32_t  rxalignerr:32;
+};
+
+union rxalignerr_u {
+	a_uint32_t val;
+	struct rxalignerr bf;
+};
+
+/*[register] RXRUNT*/
+#define RXRUNT
+#define RXRUNT_ADDRESS 0x54
+#define RXRUNT_NUM     6
+#define RXRUNT_INC     0x200
+#define RXRUNT_TYPE    REG_TYPE_RO
+#define RXRUNT_DEFAULT 0x0
+	/*[field] RXRUNT*/
+	#define RXRUNT_RXRUNT
+	#define RXRUNT_RXRUNT_OFFSET  0
+	#define RXRUNT_RXRUNT_LEN     32
+	#define RXRUNT_RXRUNT_DEFAULT 0x0
+
+struct rxrunt {
+	a_uint32_t  rxrunt:32;
+};
+
+union rxrunt_u {
+	a_uint32_t val;
+	struct rxrunt bf;
+};
+
+/*[register] RXFRAG*/
+#define RXFRAG
+#define RXFRAG_ADDRESS 0x58
+#define RXFRAG_NUM     6
+#define RXFRAG_INC     0x200
+#define RXFRAG_TYPE    REG_TYPE_RO
+#define RXFRAG_DEFAULT 0x0
+	/*[field] RXFRAG*/
+	#define RXFRAG_RXFRAG
+	#define RXFRAG_RXFRAG_OFFSET  0
+	#define RXFRAG_RXFRAG_LEN     32
+	#define RXFRAG_RXFRAG_DEFAULT 0x0
+
+struct rxfrag {
+	a_uint32_t  rxfrag:32;
+};
+
+union rxfrag_u {
+	a_uint32_t val;
+	struct rxfrag bf;
+};
+
+/*[register] RXJUMBOFCSERR*/
+#define RXJUMBOFCSERR
+#define RXJUMBOFCSERR_ADDRESS 0x5c
+#define RXJUMBOFCSERR_NUM     6
+#define RXJUMBOFCSERR_INC     0x200
+#define RXJUMBOFCSERR_TYPE    REG_TYPE_RO
+#define RXJUMBOFCSERR_DEFAULT 0x0
+	/*[field] RXJUMBOFCSERR*/
+	#define RXJUMBOFCSERR_RXJUMBOFCSERR
+	#define RXJUMBOFCSERR_RXJUMBOFCSERR_OFFSET  0
+	#define RXJUMBOFCSERR_RXJUMBOFCSERR_LEN     32
+	#define RXJUMBOFCSERR_RXJUMBOFCSERR_DEFAULT 0x0
+
+struct rxjumbofcserr {
+	a_uint32_t  rxjumbofcserr:32;
+};
+
+union rxjumbofcserr_u {
+	a_uint32_t val;
+	struct rxjumbofcserr bf;
+};
+
+/*[register] RXJUMBOALIGNERR*/
+#define RXJUMBOALIGNERR
+#define RXJUMBOALIGNERR_ADDRESS 0x60
+#define RXJUMBOALIGNERR_NUM     6
+#define RXJUMBOALIGNERR_INC     0x200
+#define RXJUMBOALIGNERR_TYPE    REG_TYPE_RO
+#define RXJUMBOALIGNERR_DEFAULT 0x0
+	/*[field] RXJUMBOALIGNERR*/
+	#define RXJUMBOALIGNERR_RXJUMBOALIGNERR
+	#define RXJUMBOALIGNERR_RXJUMBOALIGNERR_OFFSET  0
+	#define RXJUMBOALIGNERR_RXJUMBOALIGNERR_LEN     32
+	#define RXJUMBOALIGNERR_RXJUMBOALIGNERR_DEFAULT 0x0
+
+struct rxjumboalignerr {
+	a_uint32_t  rxjumboalignerr:32;
+};
+
+union rxjumboalignerr_u {
+	a_uint32_t val;
+	struct rxjumboalignerr bf;
+};
+
+/*[register] RXPKT64*/
+#define RXPKT64
+#define RXPKT64_ADDRESS 0x64
+#define RXPKT64_NUM     6
+#define RXPKT64_INC     0x200
+#define RXPKT64_TYPE    REG_TYPE_RO
+#define RXPKT64_DEFAULT 0x0
+	/*[field] RXPKT64*/
+	#define RXPKT64_RXPKT64
+	#define RXPKT64_RXPKT64_OFFSET  0
+	#define RXPKT64_RXPKT64_LEN     32
+	#define RXPKT64_RXPKT64_DEFAULT 0x0
+
+struct rxpkt64 {
+	a_uint32_t  rxpkt64:32;
+};
+
+union rxpkt64_u {
+	a_uint32_t val;
+	struct rxpkt64 bf;
+};
+
+/*[register] RXPKT65TO127*/
+#define RXPKT65TO127
+#define RXPKT65TO127_ADDRESS 0x68
+#define RXPKT65TO127_NUM     6
+#define RXPKT65TO127_INC     0x200
+#define RXPKT65TO127_TYPE    REG_TYPE_RO
+#define RXPKT65TO127_DEFAULT 0x0
+	/*[field] RXPKT65TO127*/
+	#define RXPKT65TO127_RXPKT65TO127
+	#define RXPKT65TO127_RXPKT65TO127_OFFSET  0
+	#define RXPKT65TO127_RXPKT65TO127_LEN     32
+	#define RXPKT65TO127_RXPKT65TO127_DEFAULT 0x0
+
+struct rxpkt65to127 {
+	a_uint32_t  rxpkt65to127:32;
+};
+
+union rxpkt65to127_u {
+	a_uint32_t val;
+	struct rxpkt65to127 bf;
+};
+
+/*[register] RXPKT128TO255*/
+#define RXPKT128TO255
+#define RXPKT128TO255_ADDRESS 0x6c
+#define RXPKT128TO255_NUM     6
+#define RXPKT128TO255_INC     0x200
+#define RXPKT128TO255_TYPE    REG_TYPE_RO
+#define RXPKT128TO255_DEFAULT 0x0
+	/*[field] RXPKT128TO255*/
+	#define RXPKT128TO255_RXPKT128TO255
+	#define RXPKT128TO255_RXPKT128TO255_OFFSET  0
+	#define RXPKT128TO255_RXPKT128TO255_LEN     32
+	#define RXPKT128TO255_RXPKT128TO255_DEFAULT 0x0
+
+struct rxpkt128to255 {
+	a_uint32_t  rxpkt128to255:32;
+};
+
+union rxpkt128to255_u {
+	a_uint32_t val;
+	struct rxpkt128to255 bf;
+};
+
+/*[register] RXPKT256TO511*/
+#define RXPKT256TO511
+#define RXPKT256TO511_ADDRESS 0x70
+#define RXPKT256TO511_NUM     6
+#define RXPKT256TO511_INC     0x200
+#define RXPKT256TO511_TYPE    REG_TYPE_RO
+#define RXPKT256TO511_DEFAULT 0x0
+	/*[field] RXPKT256TO511*/
+	#define RXPKT256TO511_RXPKT256TO511
+	#define RXPKT256TO511_RXPKT256TO511_OFFSET  0
+	#define RXPKT256TO511_RXPKT256TO511_LEN     32
+	#define RXPKT256TO511_RXPKT256TO511_DEFAULT 0x0
+
+struct rxpkt256to511 {
+	a_uint32_t  rxpkt256to511:32;
+};
+
+union rxpkt256to511_u {
+	a_uint32_t val;
+	struct rxpkt256to511 bf;
+};
+
+/*[register] RXPKT512TO1023*/
+#define RXPKT512TO1023
+#define RXPKT512TO1023_ADDRESS 0x74
+#define RXPKT512TO1023_NUM     6
+#define RXPKT512TO1023_INC     0x200
+#define RXPKT512TO1023_TYPE    REG_TYPE_RO
+#define RXPKT512TO1023_DEFAULT 0x0
+	/*[field] RXPKT512TO1023*/
+	#define RXPKT512TO1023_RXPKT512TO1023
+	#define RXPKT512TO1023_RXPKT512TO1023_OFFSET  0
+	#define RXPKT512TO1023_RXPKT512TO1023_LEN     32
+	#define RXPKT512TO1023_RXPKT512TO1023_DEFAULT 0x0
+
+struct rxpkt512to1023 {
+	a_uint32_t  rxpkt512to1023:32;
+};
+
+union rxpkt512to1023_u {
+	a_uint32_t val;
+	struct rxpkt512to1023 bf;
+};
+
+/*[register] RXPKT1024TO1518*/
+#define RXPKT1024TO1518
+#define RXPKT1024TO1518_ADDRESS 0x78
+#define RXPKT1024TO1518_NUM     6
+#define RXPKT1024TO1518_INC     0x200
+#define RXPKT1024TO1518_TYPE    REG_TYPE_RO
+#define RXPKT1024TO1518_DEFAULT 0x0
+	/*[field] RXPKT1024TO1518*/
+	#define RXPKT1024TO1518_RXPKT1024TO1518
+	#define RXPKT1024TO1518_RXPKT1024TO1518_OFFSET  0
+	#define RXPKT1024TO1518_RXPKT1024TO1518_LEN     32
+	#define RXPKT1024TO1518_RXPKT1024TO1518_DEFAULT 0x0
+
+struct rxpkt1024to1518 {
+	a_uint32_t  rxpkt1024to1518:32;
+};
+
+union rxpkt1024to1518_u {
+	a_uint32_t val;
+	struct rxpkt1024to1518 bf;
+};
+
+/*[register] RXPKT1519TOX*/
+#define RXPKT1519TOX
+#define RXPKT1519TOX_ADDRESS 0x7c
+#define RXPKT1519TOX_NUM     6
+#define RXPKT1519TOX_INC     0x200
+#define RXPKT1519TOX_TYPE    REG_TYPE_RO
+#define RXPKT1519TOX_DEFAULT 0x0
+	/*[field] RXPKT1519TOX*/
+	#define RXPKT1519TOX_RXPKT1519TOX
+	#define RXPKT1519TOX_RXPKT1519TOX_OFFSET  0
+	#define RXPKT1519TOX_RXPKT1519TOX_LEN     32
+	#define RXPKT1519TOX_RXPKT1519TOX_DEFAULT 0x0
+
+struct rxpkt1519tox {
+	a_uint32_t  rxpkt1519tox:32;
+};
+
+union rxpkt1519tox_u {
+	a_uint32_t val;
+	struct rxpkt1519tox bf;
+};
+
+/*[register] RXTOOLONG*/
+#define RXTOOLONG
+#define RXTOOLONG_ADDRESS 0x80
+#define RXTOOLONG_NUM     6
+#define RXTOOLONG_INC     0x200
+#define RXTOOLONG_TYPE    REG_TYPE_RO
+#define RXTOOLONG_DEFAULT 0x0
+	/*[field] RXTOOLONG*/
+	#define RXTOOLONG_RXTOOLONG
+	#define RXTOOLONG_RXTOOLONG_OFFSET  0
+	#define RXTOOLONG_RXTOOLONG_LEN     32
+	#define RXTOOLONG_RXTOOLONG_DEFAULT 0x0
+
+struct rxtoolong {
+	a_uint32_t  rxtoolong:32;
+};
+
+union rxtoolong_u {
+	a_uint32_t val;
+	struct rxtoolong bf;
+};
+
+/*[register] RXGOODBYTE_L*/
+#define RXGOODBYTE_L
+#define RXGOODBYTE_L_ADDRESS 0x84
+#define RXGOODBYTE_L_NUM     6
+#define RXGOODBYTE_L_INC     0x200
+#define RXGOODBYTE_L_TYPE    REG_TYPE_RO
+#define RXGOODBYTE_L_DEFAULT 0x0
+	/*[field] RXGOODBYTE_L*/
+	#define RXGOODBYTE_L_RXGOODBYTE_L
+	#define RXGOODBYTE_L_RXGOODBYTE_L_OFFSET  0
+	#define RXGOODBYTE_L_RXGOODBYTE_L_LEN     32
+	#define RXGOODBYTE_L_RXGOODBYTE_L_DEFAULT 0x0
+
+struct rxgoodbyte_l {
+	a_uint32_t  rxgoodbyte_l:32;
+};
+
+union rxgoodbyte_l_u {
+	a_uint32_t val;
+	struct rxgoodbyte_l bf;
+};
+
+/*[register] RXGOODBYTE_H*/
+#define RXGOODBYTE_H
+#define RXGOODBYTE_H_ADDRESS 0x88
+#define RXGOODBYTE_H_NUM     6
+#define RXGOODBYTE_H_INC     0x200
+#define RXGOODBYTE_H_TYPE    REG_TYPE_RO
+#define RXGOODBYTE_H_DEFAULT 0x0
+	/*[field] RXGOODBYTE_H*/
+	#define RXGOODBYTE_H_RXGOODBYTE_H
+	#define RXGOODBYTE_H_RXGOODBYTE_H_OFFSET  0
+	#define RXGOODBYTE_H_RXGOODBYTE_H_LEN     32
+	#define RXGOODBYTE_H_RXGOODBYTE_H_DEFAULT 0x0
+
+struct rxgoodbyte_h {
+	a_uint32_t  rxgoodbyte_h:32;
+};
+
+union rxgoodbyte_h_u {
+	a_uint32_t val;
+	struct rxgoodbyte_h bf;
+};
+
+/*[register] RXBADBYTE_L*/
+#define RXBADBYTE_L
+#define RXBADBYTE_L_ADDRESS 0x8c
+#define RXBADBYTE_L_NUM     6
+#define RXBADBYTE_L_INC     0x200
+#define RXBADBYTE_L_TYPE    REG_TYPE_RO
+#define RXBADBYTE_L_DEFAULT 0x0
+	/*[field] RXBADBYTE_L*/
+	#define RXBADBYTE_L_RXBADBYTE_L
+	#define RXBADBYTE_L_RXBADBYTE_L_OFFSET  0
+	#define RXBADBYTE_L_RXBADBYTE_L_LEN     32
+	#define RXBADBYTE_L_RXBADBYTE_L_DEFAULT 0x0
+
+struct rxbadbyte_l {
+	a_uint32_t  rxbadbyte_l:32;
+};
+
+union rxbadbyte_l_u {
+	a_uint32_t val;
+	struct rxbadbyte_l bf;
+};
+
+/*[register] RXBADBYTE_H*/
+#define RXBADBYTE_H
+#define RXBADBYTE_H_ADDRESS 0x90
+#define RXBADBYTE_H_NUM     6
+#define RXBADBYTE_H_INC     0x200
+#define RXBADBYTE_H_TYPE    REG_TYPE_RO
+#define RXBADBYTE_H_DEFAULT 0x0
+	/*[field] RXBADBYTE_H*/
+	#define RXBADBYTE_H_RXBADBYTE_H
+	#define RXBADBYTE_H_RXBADBYTE_H_OFFSET  0
+	#define RXBADBYTE_H_RXBADBYTE_H_LEN     32
+	#define RXBADBYTE_H_RXBADBYTE_H_DEFAULT 0x0
+
+struct rxbadbyte_h {
+	a_uint32_t  rxbadbyte_h:32;
+};
+
+union rxbadbyte_h_u {
+	a_uint32_t val;
+	struct rxbadbyte_h bf;
+};
+
+/*[register] RXUNI*/
+#define RXUNI
+#define RXUNI_ADDRESS 0x94
+#define RXUNI_NUM     6
+#define RXUNI_INC     0x200
+#define RXUNI_TYPE    REG_TYPE_RO
+#define RXUNI_DEFAULT 0x0
+	/*[field] RXUNI*/
+	#define RXUNI_RXUNI
+	#define RXUNI_RXUNI_OFFSET  0
+	#define RXUNI_RXUNI_LEN     32
+	#define RXUNI_RXUNI_DEFAULT 0x0
+
+struct rxuni {
+	a_uint32_t  rxuni:32;
+};
+
+union rxuni_u {
+	a_uint32_t val;
+	struct rxuni bf;
+};
+
+/*[register] TXBROAD*/
+#define TXBROAD
+#define TXBROAD_ADDRESS 0xa0
+#define TXBROAD_NUM     6
+#define TXBROAD_INC     0x200
+#define TXBROAD_TYPE    REG_TYPE_RO
+#define TXBROAD_DEFAULT 0x0
+	/*[field] TXBROAD*/
+	#define TXBROAD_TXBROAD
+	#define TXBROAD_TXBROAD_OFFSET  0
+	#define TXBROAD_TXBROAD_LEN     32
+	#define TXBROAD_TXBROAD_DEFAULT 0x0
+
+struct txbroad {
+	a_uint32_t  txbroad:32;
+};
+
+union txbroad_u {
+	a_uint32_t val;
+	struct txbroad bf;
+};
+
+/*[register] TXPAUSE*/
+#define TXPAUSE
+#define TXPAUSE_ADDRESS 0xa4
+#define TXPAUSE_NUM     6
+#define TXPAUSE_INC     0x200
+#define TXPAUSE_TYPE    REG_TYPE_RO
+#define TXPAUSE_DEFAULT 0x0
+	/*[field] TXPAUSE*/
+	#define TXPAUSE_TXPAUSE
+	#define TXPAUSE_TXPAUSE_OFFSET  0
+	#define TXPAUSE_TXPAUSE_LEN     32
+	#define TXPAUSE_TXPAUSE_DEFAULT 0x0
+
+struct txpause {
+	a_uint32_t  txpause:32;
+};
+
+union txpause_u {
+	a_uint32_t val;
+	struct txpause bf;
+};
+
+/*[register] TXMULTI*/
+#define TXMULTI
+#define TXMULTI_ADDRESS 0xa8
+#define TXMULTI_NUM     6
+#define TXMULTI_INC     0x200
+#define TXMULTI_TYPE    REG_TYPE_RO
+#define TXMULTI_DEFAULT 0x0
+	/*[field] TXMULTI*/
+	#define TXMULTI_TXMULTI
+	#define TXMULTI_TXMULTI_OFFSET  0
+	#define TXMULTI_TXMULTI_LEN     32
+	#define TXMULTI_TXMULTI_DEFAULT 0x0
+
+struct txmulti {
+	a_uint32_t  txmulti:32;
+};
+
+union txmulti_u {
+	a_uint32_t val;
+	struct txmulti bf;
+};
+
+/*[register] TXUNDERRUN*/
+#define TXUNDERRUN
+#define TXUNDERRUN_ADDRESS 0xac
+#define TXUNDERRUN_NUM     6
+#define TXUNDERRUN_INC     0x200
+#define TXUNDERRUN_TYPE    REG_TYPE_RO
+#define TXUNDERRUN_DEFAULT 0x0
+	/*[field] TXUNDERRUN*/
+	#define TXUNDERRUN_TXUNDERRUN
+	#define TXUNDERRUN_TXUNDERRUN_OFFSET  0
+	#define TXUNDERRUN_TXUNDERRUN_LEN     32
+	#define TXUNDERRUN_TXUNDERRUN_DEFAULT 0x0
+
+struct txunderrun {
+	a_uint32_t  txunderrun:32;
+};
+
+union txunderrun_u {
+	a_uint32_t val;
+	struct txunderrun bf;
+};
+
+/*[register] TXPKT64*/
+#define TXPKT64
+#define TXPKT64_ADDRESS 0xb0
+#define TXPKT64_NUM     6
+#define TXPKT64_INC     0x200
+#define TXPKT64_TYPE    REG_TYPE_RO
+#define TXPKT64_DEFAULT 0x0
+	/*[field] TXPKT64*/
+	#define TXPKT64_TXPKT64
+	#define TXPKT64_TXPKT64_OFFSET  0
+	#define TXPKT64_TXPKT64_LEN     32
+	#define TXPKT64_TXPKT64_DEFAULT 0x0
+
+struct txpkt64 {
+	a_uint32_t  txpkt64:32;
+};
+
+union txpkt64_u {
+	a_uint32_t val;
+	struct txpkt64 bf;
+};
+
+/*[register] TXPKT65TO127*/
+#define TXPKT65TO127
+#define TXPKT65TO127_ADDRESS 0xb4
+#define TXPKT65TO127_NUM     6
+#define TXPKT65TO127_INC     0x200
+#define TXPKT65TO127_TYPE    REG_TYPE_RO
+#define TXPKT65TO127_DEFAULT 0x0
+	/*[field] TXPKT65TO127*/
+	#define TXPKT65TO127_TXPKT65TO127
+	#define TXPKT65TO127_TXPKT65TO127_OFFSET  0
+	#define TXPKT65TO127_TXPKT65TO127_LEN     32
+	#define TXPKT65TO127_TXPKT65TO127_DEFAULT 0x0
+
+struct txpkt65to127 {
+	a_uint32_t  txpkt65to127:32;
+};
+
+union txpkt65to127_u {
+	a_uint32_t val;
+	struct txpkt65to127 bf;
+};
+
+/*[register] TXPKT128TO255*/
+#define TXPKT128TO255
+#define TXPKT128TO255_ADDRESS 0xb8
+#define TXPKT128TO255_NUM     6
+#define TXPKT128TO255_INC     0x200
+#define TXPKT128TO255_TYPE    REG_TYPE_RO
+#define TXPKT128TO255_DEFAULT 0x0
+	/*[field] TXPKT128TO255*/
+	#define TXPKT128TO255_TXPKT128TO255
+	#define TXPKT128TO255_TXPKT128TO255_OFFSET  0
+	#define TXPKT128TO255_TXPKT128TO255_LEN     32
+	#define TXPKT128TO255_TXPKT128TO255_DEFAULT 0x0
+
+struct txpkt128to255 {
+	a_uint32_t  txpkt128to255:32;
+};
+
+union txpkt128to255_u {
+	a_uint32_t val;
+	struct txpkt128to255 bf;
+};
+
+/*[register] TXPKT256TO511*/
+#define TXPKT256TO511
+#define TXPKT256TO511_ADDRESS 0xbc
+#define TXPKT256TO511_NUM     6
+#define TXPKT256TO511_INC     0x200
+#define TXPKT256TO511_TYPE    REG_TYPE_RO
+#define TXPKT256TO511_DEFAULT 0x0
+	/*[field] TXPKT256TO511*/
+	#define TXPKT256TO511_TXPKT256TO511
+	#define TXPKT256TO511_TXPKT256TO511_OFFSET  0
+	#define TXPKT256TO511_TXPKT256TO511_LEN     32
+	#define TXPKT256TO511_TXPKT256TO511_DEFAULT 0x0
+
+struct txpkt256to511 {
+	a_uint32_t  txpkt256to511:32;
+};
+
+union txpkt256to511_u {
+	a_uint32_t val;
+	struct txpkt256to511 bf;
+};
+
+/*[register] TXPKT512TO1023*/
+#define TXPKT512TO1023
+#define TXPKT512TO1023_ADDRESS 0xc0
+#define TXPKT512TO1023_NUM     6
+#define TXPKT512TO1023_INC     0x200
+#define TXPKT512TO1023_TYPE    REG_TYPE_RO
+#define TXPKT512TO1023_DEFAULT 0x0
+	/*[field] TXPKT512TO1023*/
+	#define TXPKT512TO1023_TXPKT512TO1023
+	#define TXPKT512TO1023_TXPKT512TO1023_OFFSET  0
+	#define TXPKT512TO1023_TXPKT512TO1023_LEN     32
+	#define TXPKT512TO1023_TXPKT512TO1023_DEFAULT 0x0
+
+struct txpkt512to1023 {
+	a_uint32_t  txpkt512to1023:32;
+};
+
+union txpkt512to1023_u {
+	a_uint32_t val;
+	struct txpkt512to1023 bf;
+};
+
+/*[register] TXPKT1024TO1518*/
+#define TXPKT1024TO1518
+#define TXPKT1024TO1518_ADDRESS 0xc4
+#define TXPKT1024TO1518_NUM     6
+#define TXPKT1024TO1518_INC     0x200
+#define TXPKT1024TO1518_TYPE    REG_TYPE_RO
+#define TXPKT1024TO1518_DEFAULT 0x0
+	/*[field] TXPKT1024TO1518*/
+	#define TXPKT1024TO1518_TXPKT1024TO1518
+	#define TXPKT1024TO1518_TXPKT1024TO1518_OFFSET  0
+	#define TXPKT1024TO1518_TXPKT1024TO1518_LEN     32
+	#define TXPKT1024TO1518_TXPKT1024TO1518_DEFAULT 0x0
+
+struct txpkt1024to1518 {
+	a_uint32_t  txpkt1024to1518:32;
+};
+
+union txpkt1024to1518_u {
+	a_uint32_t val;
+	struct txpkt1024to1518 bf;
+};
+
+/*[register] TXPKT1519TOX*/
+#define TXPKT1519TOX
+#define TXPKT1519TOX_ADDRESS 0xc8
+#define TXPKT1519TOX_NUM     6
+#define TXPKT1519TOX_INC     0x200
+#define TXPKT1519TOX_TYPE    REG_TYPE_RO
+#define TXPKT1519TOX_DEFAULT 0x0
+	/*[field] TXPKT1519TOX*/
+	#define TXPKT1519TOX_TXPKT1519TOX
+	#define TXPKT1519TOX_TXPKT1519TOX_OFFSET  0
+	#define TXPKT1519TOX_TXPKT1519TOX_LEN     32
+	#define TXPKT1519TOX_TXPKT1519TOX_DEFAULT 0x0
+
+struct txpkt1519tox {
+	a_uint32_t  txpkt1519tox:32;
+};
+
+union txpkt1519tox_u {
+	a_uint32_t val;
+	struct txpkt1519tox bf;
+};
+
+/*[register] TXBYTE_L*/
+#define TXBYTE_L
+#define TXBYTE_L_ADDRESS 0xcc
+#define TXBYTE_L_NUM     6
+#define TXBYTE_L_INC     0x200
+#define TXBYTE_L_TYPE    REG_TYPE_RO
+#define TXBYTE_L_DEFAULT 0x0
+	/*[field] TXBYTE_L*/
+	#define TXBYTE_L_TXBYTE_L
+	#define TXBYTE_L_TXBYTE_L_OFFSET  0
+	#define TXBYTE_L_TXBYTE_L_LEN     32
+	#define TXBYTE_L_TXBYTE_L_DEFAULT 0x0
+
+struct txbyte_l {
+	a_uint32_t  txbyte_l:32;
+};
+
+union txbyte_l_u {
+	a_uint32_t val;
+	struct txbyte_l bf;
+};
+
+/*[register] TXBYTE_H*/
+#define TXBYTE_H
+#define TXBYTE_H_ADDRESS 0xd0
+#define TXBYTE_H_NUM     6
+#define TXBYTE_H_INC     0x200
+#define TXBYTE_H_TYPE    REG_TYPE_RO
+#define TXBYTE_H_DEFAULT 0x0
+	/*[field] TXBYTE_H*/
+	#define TXBYTE_H_TXBYTE_H
+	#define TXBYTE_H_TXBYTE_H_OFFSET  0
+	#define TXBYTE_H_TXBYTE_H_LEN     32
+	#define TXBYTE_H_TXBYTE_H_DEFAULT 0x0
+
+struct txbyte_h {
+	a_uint32_t  txbyte_h:32;
+};
+
+union txbyte_h_u {
+	a_uint32_t val;
+	struct txbyte_h bf;
+};
+
+/*[register] TXCOLLISIONS*/
+#define TXCOLLISIONS
+#define TXCOLLISIONS_ADDRESS 0xd4
+#define TXCOLLISIONS_NUM     6
+#define TXCOLLISIONS_INC     0x200
+#define TXCOLLISIONS_TYPE    REG_TYPE_RO
+#define TXCOLLISIONS_DEFAULT 0x0
+	/*[field] TXCOLLISIONS*/
+	#define TXCOLLISIONS_TXCOLLISIONS
+	#define TXCOLLISIONS_TXCOLLISIONS_OFFSET  0
+	#define TXCOLLISIONS_TXCOLLISIONS_LEN     32
+	#define TXCOLLISIONS_TXCOLLISIONS_DEFAULT 0x0
+
+struct txcollisions {
+	a_uint32_t  txcollisions:32;
+};
+
+union txcollisions_u {
+	a_uint32_t val;
+	struct txcollisions bf;
+};
+
+/*[register] TXABORTCOL*/
+#define TXABORTCOL
+#define TXABORTCOL_ADDRESS 0xd8
+#define TXABORTCOL_NUM     6
+#define TXABORTCOL_INC     0x200
+#define TXABORTCOL_TYPE    REG_TYPE_RO
+#define TXABORTCOL_DEFAULT 0x0
+	/*[field] TXABORTCOL*/
+	#define TXABORTCOL_TXABORTCOL
+	#define TXABORTCOL_TXABORTCOL_OFFSET  0
+	#define TXABORTCOL_TXABORTCOL_LEN     32
+	#define TXABORTCOL_TXABORTCOL_DEFAULT 0x0
+
+struct txabortcol {
+	a_uint32_t  txabortcol:32;
+};
+
+union txabortcol_u {
+	a_uint32_t val;
+	struct txabortcol bf;
+};
+
+/*[register] TXMULTICOL*/
+#define TXMULTICOL
+#define TXMULTICOL_ADDRESS 0xdc
+#define TXMULTICOL_NUM     6
+#define TXMULTICOL_INC     0x200
+#define TXMULTICOL_TYPE    REG_TYPE_RO
+#define TXMULTICOL_DEFAULT 0x0
+	/*[field] TXMULTICOL*/
+	#define TXMULTICOL_TXMULTICOL
+	#define TXMULTICOL_TXMULTICOL_OFFSET  0
+	#define TXMULTICOL_TXMULTICOL_LEN     32
+	#define TXMULTICOL_TXMULTICOL_DEFAULT 0x0
+
+struct txmulticol {
+	a_uint32_t  txmulticol:32;
+};
+
+union txmulticol_u {
+	a_uint32_t val;
+	struct txmulticol bf;
+};
+
+/*[register] TXSINGLECOL*/
+#define TXSINGLECOL
+#define TXSINGLECOL_ADDRESS 0xe0
+#define TXSINGLECOL_NUM     6
+#define TXSINGLECOL_INC     0x200
+#define TXSINGLECOL_TYPE    REG_TYPE_RO
+#define TXSINGLECOL_DEFAULT 0x0
+	/*[field] TXSINGLECOL*/
+	#define TXSINGLECOL_TXSINGLECOL
+	#define TXSINGLECOL_TXSINGLECOL_OFFSET  0
+	#define TXSINGLECOL_TXSINGLECOL_LEN     32
+	#define TXSINGLECOL_TXSINGLECOL_DEFAULT 0x0
+
+struct txsinglecol {
+	a_uint32_t  txsinglecol:32;
+};
+
+union txsinglecol_u {
+	a_uint32_t val;
+	struct txsinglecol bf;
+};
+
+/*[register] TXEXCESSIVEDEFER*/
+#define TXEXCESSIVEDEFER
+#define TXEXCESSIVEDEFER_ADDRESS 0xe4
+#define TXEXCESSIVEDEFER_NUM     6
+#define TXEXCESSIVEDEFER_INC     0x200
+#define TXEXCESSIVEDEFER_TYPE    REG_TYPE_RO
+#define TXEXCESSIVEDEFER_DEFAULT 0x0
+	/*[field] TXEXCESSIVEDEFER*/
+	#define TXEXCESSIVEDEFER_TXEXCESSIVEDEFER
+	#define TXEXCESSIVEDEFER_TXEXCESSIVEDEFER_OFFSET  0
+	#define TXEXCESSIVEDEFER_TXEXCESSIVEDEFER_LEN     32
+	#define TXEXCESSIVEDEFER_TXEXCESSIVEDEFER_DEFAULT 0x0
+
+struct txexcessivedefer {
+	a_uint32_t  txexcessivedefer:32;
+};
+
+union txexcessivedefer_u {
+	a_uint32_t val;
+	struct txexcessivedefer bf;
+};
+
+/*[register] TXDEFER*/
+#define TXDEFER
+#define TXDEFER_ADDRESS 0xe8
+#define TXDEFER_NUM     6
+#define TXDEFER_INC     0x200
+#define TXDEFER_TYPE    REG_TYPE_RO
+#define TXDEFER_DEFAULT 0x0
+	/*[field] TXDEFER*/
+	#define TXDEFER_TXDEFER
+	#define TXDEFER_TXDEFER_OFFSET  0
+	#define TXDEFER_TXDEFER_LEN     32
+	#define TXDEFER_TXDEFER_DEFAULT 0x0
+
+struct txdefer {
+	a_uint32_t  txdefer:32;
+};
+
+union txdefer_u {
+	a_uint32_t val;
+	struct txdefer bf;
+};
+
+/*[register] TXLATECOL*/
+#define TXLATECOL
+#define TXLATECOL_ADDRESS 0xec
+#define TXLATECOL_NUM     6
+#define TXLATECOL_INC     0x200
+#define TXLATECOL_TYPE    REG_TYPE_RO
+#define TXLATECOL_DEFAULT 0x0
+	/*[field] TXLATECOL*/
+	#define TXLATECOL_TXLATECOL
+	#define TXLATECOL_TXLATECOL_OFFSET  0
+	#define TXLATECOL_TXLATECOL_LEN     32
+	#define TXLATECOL_TXLATECOL_DEFAULT 0x0
+
+struct txlatecol {
+	a_uint32_t  txlatecol:32;
+};
+
+union txlatecol_u {
+	a_uint32_t val;
+	struct txlatecol bf;
+};
+
+/*[register] TXUNI*/
+#define TXUNI
+#define TXUNI_ADDRESS 0xf0
+#define TXUNI_NUM     6
+#define TXUNI_INC     0x200
+#define TXUNI_TYPE    REG_TYPE_RO
+#define TXUNI_DEFAULT 0x0
+	/*[field] TXUNI*/
+	#define TXUNI_TXUNI
+	#define TXUNI_TXUNI_OFFSET  0
+	#define TXUNI_TXUNI_LEN     32
+	#define TXUNI_TXUNI_DEFAULT 0x0
+
+struct txuni {
+	a_uint32_t  txuni:32;
+};
+
+union txuni_u {
+	a_uint32_t val;
+	struct txuni bf;
+};
+
+
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_mirror.h b/qca-ssdk/include/hsl/hppe/hppe_mirror.h
new file mode 100755
index 0000000..c8f3994
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_mirror.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_MIRROR_H_
+#define _HPPE_MIRROR_H_
+
+#define PORT_MIRROR_MAX_ENTRY	8
+
+sw_error_t
+hppe_mirror_analyzer_get(
+		a_uint32_t dev_id,
+		union mirror_analyzer_u *value);
+
+sw_error_t
+hppe_mirror_analyzer_set(
+		a_uint32_t dev_id,
+		union mirror_analyzer_u *value);
+
+sw_error_t
+hppe_port_mirror_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_mirror_u *value);
+
+sw_error_t
+hppe_port_mirror_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_mirror_u *value);
+
+sw_error_t
+hppe_mirror_analyzer_in_analyzer_port_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_mirror_analyzer_in_analyzer_port_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_mirror_analyzer_eg_analyzer_port_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_mirror_analyzer_eg_analyzer_port_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_mirror_in_mirr_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_mirror_in_mirr_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_mirror_eg_mirr_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_mirror_eg_mirr_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_mirror_reg.h b/qca-ssdk/include/hsl/hppe/hppe_mirror_reg.h
new file mode 100755
index 0000000..45b69a7
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_mirror_reg.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_MIRROR_REG_H
+#define HPPE_MIRROR_REG_H
+
+/*[register] MIRROR_ANALYZER*/
+#define MIRROR_ANALYZER
+#define MIRROR_ANALYZER_ADDRESS 0x40
+#define MIRROR_ANALYZER_NUM     1
+#define MIRROR_ANALYZER_INC     0x4
+#define MIRROR_ANALYZER_TYPE    REG_TYPE_RW
+#define MIRROR_ANALYZER_DEFAULT 0x0
+	/*[field] IN_ANALYZER_PORT*/
+	#define MIRROR_ANALYZER_IN_ANALYZER_PORT
+	#define MIRROR_ANALYZER_IN_ANALYZER_PORT_OFFSET  0
+	#define MIRROR_ANALYZER_IN_ANALYZER_PORT_LEN     6
+	#define MIRROR_ANALYZER_IN_ANALYZER_PORT_DEFAULT 0x0
+	/*[field] EG_ANALYZER_PORT*/
+	#define MIRROR_ANALYZER_EG_ANALYZER_PORT
+	#define MIRROR_ANALYZER_EG_ANALYZER_PORT_OFFSET  8
+	#define MIRROR_ANALYZER_EG_ANALYZER_PORT_LEN     6
+	#define MIRROR_ANALYZER_EG_ANALYZER_PORT_DEFAULT 0x0
+
+struct mirror_analyzer {
+	a_uint32_t  in_analyzer_port:6;
+	a_uint32_t  _reserved0:2;
+	a_uint32_t  eg_analyzer_port:6;
+	a_uint32_t  _reserved1:18;
+};
+
+union mirror_analyzer_u {
+	a_uint32_t val;
+	struct mirror_analyzer bf;
+};
+
+/*[register] PORT_MIRROR*/
+#define PORT_MIRROR
+#define PORT_MIRROR_ADDRESS 0x800
+#define PORT_MIRROR_NUM     8
+#define PORT_MIRROR_INC     0x4
+#define PORT_MIRROR_TYPE    REG_TYPE_RW
+#define PORT_MIRROR_DEFAULT 0x0
+	/*[field] IN_MIRR_EN*/
+	#define PORT_MIRROR_IN_MIRR_EN
+	#define PORT_MIRROR_IN_MIRR_EN_OFFSET  0
+	#define PORT_MIRROR_IN_MIRR_EN_LEN     1
+	#define PORT_MIRROR_IN_MIRR_EN_DEFAULT 0x0
+	/*[field] EG_MIRR_EN*/
+	#define PORT_MIRROR_EG_MIRR_EN
+	#define PORT_MIRROR_EG_MIRR_EN_OFFSET  1
+	#define PORT_MIRROR_EG_MIRR_EN_LEN     1
+	#define PORT_MIRROR_EG_MIRR_EN_DEFAULT 0x0
+
+struct port_mirror {
+	a_uint32_t  in_mirr_en:1;
+	a_uint32_t  eg_mirr_en:1;
+	a_uint32_t  _reserved0:30;
+};
+
+union port_mirror_u {
+	a_uint32_t val;
+	struct port_mirror bf;
+};
+
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_policer.h b/qca-ssdk/include/hsl/hppe/hppe_policer.h
new file mode 100755
index 0000000..92ca036
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_policer.h
@@ -0,0 +1,1173 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_POLICER_H_
+#define _HPPE_POLICER_H_
+
+#define METER_CMPST_LENGTH_REG_MAX_ENTRY	8
+#define IN_ACL_METER_CFG_TBL_MAX_ENTRY	512
+#define IN_ACL_METER_CRDT_TBL_MAX_ENTRY	512
+#define IN_PORT_METER_CFG_TBL_MAX_ENTRY	8
+#define IN_PORT_METER_CRDT_TBL_MAX_ENTRY	8
+#define IN_PORT_METER_CNT_TBL_MAX_ENTRY	24
+#define IN_ACL_METER_CNT_TBL_MAX_ENTRY	1536
+#define PC_GLOBAL_CNT_TBL_MAX_ENTRY	3
+#define DROP_CPU_CNT_TBL_MAX_ENTRY	1280
+#define CPU_CODE_CNT_TBL_MAX_ENTRY	256
+#define PORT_TX_DROP_CNT_TBL_MAX_ENTRY	8
+#define VP_TX_DROP_CNT_TBL_MAX_ENTRY	256
+#define VLAN_DEV_CNT_TBL_MAX_ENTRY	64
+
+
+sw_error_t
+hppe_meter_cmpst_length_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union meter_cmpst_length_reg_u *value);
+
+sw_error_t
+hppe_meter_cmpst_length_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union meter_cmpst_length_reg_u *value);
+
+sw_error_t
+hppe_pc_drop_bypass_reg_get(
+		a_uint32_t dev_id,
+		union pc_drop_bypass_reg_u *value);
+
+sw_error_t
+hppe_pc_drop_bypass_reg_set(
+		a_uint32_t dev_id,
+		union pc_drop_bypass_reg_u *value);
+
+sw_error_t
+hppe_pc_spare_reg_get(
+		a_uint32_t dev_id,
+		union pc_spare_reg_u *value);
+
+sw_error_t
+hppe_pc_spare_reg_set(
+		a_uint32_t dev_id,
+		union pc_spare_reg_u *value);
+
+sw_error_t
+hppe_time_slot_reg_get(
+		a_uint32_t dev_id,
+		union time_slot_reg_u *value);
+
+sw_error_t
+hppe_time_slot_reg_set(
+		a_uint32_t dev_id,
+		union time_slot_reg_u *value);
+
+sw_error_t
+hppe_pc_dbg_addr_reg_get(
+		a_uint32_t dev_id,
+		union pc_dbg_addr_reg_u *value);
+
+sw_error_t
+hppe_pc_dbg_addr_reg_set(
+		a_uint32_t dev_id,
+		union pc_dbg_addr_reg_u *value);
+
+sw_error_t
+hppe_pc_dbg_data_reg_get(
+		a_uint32_t dev_id,
+		union pc_dbg_data_reg_u *value);
+
+sw_error_t
+hppe_pc_dbg_data_reg_set(
+		a_uint32_t dev_id,
+		union pc_dbg_data_reg_u *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_acl_meter_cfg_tbl_u *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_acl_meter_cfg_tbl_u *value);
+
+sw_error_t
+hppe_in_acl_meter_crdt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_acl_meter_crdt_tbl_u *value);
+
+sw_error_t
+hppe_in_acl_meter_crdt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_acl_meter_crdt_tbl_u *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_port_meter_cfg_tbl_u *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_port_meter_cfg_tbl_u *value);
+
+sw_error_t
+hppe_in_port_meter_crdt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_port_meter_crdt_tbl_u *value);
+
+sw_error_t
+hppe_in_port_meter_crdt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_port_meter_crdt_tbl_u *value);
+
+sw_error_t
+hppe_in_port_meter_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_port_meter_cnt_tbl_u *value);
+
+sw_error_t
+hppe_in_port_meter_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_port_meter_cnt_tbl_u *value);
+
+sw_error_t
+hppe_in_acl_meter_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_acl_meter_cnt_tbl_u *value);
+
+sw_error_t
+hppe_in_acl_meter_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_acl_meter_cnt_tbl_u *value);
+
+
+sw_error_t
+hppe_pc_global_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pc_global_cnt_tbl_u *value);
+
+sw_error_t
+hppe_pc_global_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pc_global_cnt_tbl_u *value);
+
+sw_error_t
+hppe_drop_cpu_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union drop_cpu_cnt_tbl_u *value);
+
+sw_error_t
+hppe_drop_cpu_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union drop_cpu_cnt_tbl_u *value);
+
+sw_error_t
+hppe_port_tx_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_tx_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_port_tx_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_tx_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_vp_tx_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vp_tx_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_vp_tx_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vp_tx_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_vlan_dev_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vlan_dev_cnt_tbl_u *value);
+
+sw_error_t
+hppe_vlan_dev_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vlan_dev_cnt_tbl_u *value);
+
+sw_error_t
+hppe_meter_cmpst_length_reg_cmpst_length_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_meter_cmpst_length_reg_cmpst_length_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pc_drop_bypass_reg_drop_bypass_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_pc_drop_bypass_reg_drop_bypass_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_pc_spare_reg_spare_reg_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_pc_spare_reg_spare_reg_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_time_slot_reg_time_slot_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_time_slot_reg_time_slot_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_pc_dbg_addr_reg_dbg_addr_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_pc_dbg_addr_reg_dbg_addr_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_pc_dbg_data_reg_dbg_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_pc_dbg_data_reg_dbg_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_meter_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_meter_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_color_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_color_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_pcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_pcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_pri_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_pri_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_dp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_dp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_dp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_dp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_cbs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_cbs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_dei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_dei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_pcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_pcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_cir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_cir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_pri_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_pri_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_meter_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_meter_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_meter_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_meter_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_dp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_dp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_eir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_eir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_dp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_dp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_dei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_dei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_token_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_token_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_coupling_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_coupling_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_ebs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_ebs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_crdt_tbl_c_crdt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_crdt_tbl_c_crdt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_crdt_tbl_e_crdt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_crdt_tbl_e_crdt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_color_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_color_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_pcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_pcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_pri_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_pri_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_dp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_dp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_dp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_dp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_cbs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_cbs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_dei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_dei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_pcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_pcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_cir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_cir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_pri_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_pri_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_dp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_dp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_eir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_eir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_dp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_dp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_dei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_dei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_token_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_token_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_coupling_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_coupling_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_ebs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_ebs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_crdt_tbl_c_crdt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_crdt_tbl_c_crdt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_crdt_tbl_e_crdt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_crdt_tbl_e_crdt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_port_meter_cnt_tbl_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_in_port_meter_cnt_tbl_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_in_port_meter_cnt_tbl_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_port_meter_cnt_tbl_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_acl_meter_cnt_tbl_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cnt_tbl_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_in_acl_meter_cnt_tbl_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_acl_meter_cnt_tbl_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+
+sw_error_t
+hppe_pc_global_cnt_tbl_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_pc_global_cnt_tbl_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_pc_global_cnt_tbl_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pc_global_cnt_tbl_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_drop_cpu_cnt_tbl_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_drop_cpu_cnt_tbl_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_drop_cpu_cnt_tbl_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_drop_cpu_cnt_tbl_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_tx_drop_cnt_tbl_tx_drop_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_port_tx_drop_cnt_tbl_tx_drop_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_port_tx_drop_cnt_tbl_tx_drop_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_tx_drop_cnt_tbl_tx_drop_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vp_tx_drop_cnt_tbl_tx_drop_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_vp_tx_drop_cnt_tbl_tx_drop_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_vp_tx_drop_cnt_tbl_tx_drop_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vp_tx_drop_cnt_tbl_tx_drop_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vlan_dev_cnt_tbl_rx_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_vlan_dev_cnt_tbl_rx_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_vlan_dev_cnt_tbl_rx_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vlan_dev_cnt_tbl_rx_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_policer_reg.h b/qca-ssdk/include/hsl/hppe/hppe_policer_reg.h
new file mode 100755
index 0000000..bcd4ba4
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_policer_reg.h
@@ -0,0 +1,795 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_POLICER_REG_H
+#define HPPE_POLICER_REG_H
+
+/*[register] METER_CMPST_LENGTH_REG*/
+#define METER_CMPST_LENGTH_REG
+#define METER_CMPST_LENGTH_REG_ADDRESS 0x0
+#define METER_CMPST_LENGTH_REG_NUM     8
+#define METER_CMPST_LENGTH_REG_INC     0x4
+#define METER_CMPST_LENGTH_REG_TYPE    REG_TYPE_RW
+#define METER_CMPST_LENGTH_REG_DEFAULT 0x0
+	/*[field] CMPST_LENGTH*/
+	#define METER_CMPST_LENGTH_REG_CMPST_LENGTH
+	#define METER_CMPST_LENGTH_REG_CMPST_LENGTH_OFFSET  0
+	#define METER_CMPST_LENGTH_REG_CMPST_LENGTH_LEN     5
+	#define METER_CMPST_LENGTH_REG_CMPST_LENGTH_DEFAULT 0x0
+
+struct meter_cmpst_length_reg {
+	a_uint32_t  cmpst_length:5;
+	a_uint32_t  _reserved0:27;
+};
+
+union meter_cmpst_length_reg_u {
+	a_uint32_t val;
+	struct meter_cmpst_length_reg bf;
+};
+
+/*[register] PC_DROP_BYPASS_REG*/
+#define PC_DROP_BYPASS_REG
+#define PC_DROP_BYPASS_REG_ADDRESS 0x20
+#define PC_DROP_BYPASS_REG_NUM     1
+#define PC_DROP_BYPASS_REG_INC     0x4
+#define PC_DROP_BYPASS_REG_TYPE    REG_TYPE_RW
+#define PC_DROP_BYPASS_REG_DEFAULT 0x0
+	/*[field] DROP_BYPASS_EN*/
+	#define PC_DROP_BYPASS_REG_DROP_BYPASS_EN
+	#define PC_DROP_BYPASS_REG_DROP_BYPASS_EN_OFFSET  0
+	#define PC_DROP_BYPASS_REG_DROP_BYPASS_EN_LEN     1
+	#define PC_DROP_BYPASS_REG_DROP_BYPASS_EN_DEFAULT 0x0
+
+struct pc_drop_bypass_reg {
+	a_uint32_t  drop_bypass_en:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union pc_drop_bypass_reg_u {
+	a_uint32_t val;
+	struct pc_drop_bypass_reg bf;
+};
+
+/*[register] PC_SPARE_REG*/
+#define PC_SPARE_REG
+#define PC_SPARE_REG_ADDRESS 0x30
+#define PC_SPARE_REG_NUM     1
+#define PC_SPARE_REG_INC     0x4
+#define PC_SPARE_REG_TYPE    REG_TYPE_RW
+#define PC_SPARE_REG_DEFAULT 0x0
+	/*[field] SPARE_REG*/
+	#define PC_SPARE_REG_SPARE_REG
+	#define PC_SPARE_REG_SPARE_REG_OFFSET  0
+	#define PC_SPARE_REG_SPARE_REG_LEN     32
+	#define PC_SPARE_REG_SPARE_REG_DEFAULT 0x0
+
+struct pc_spare_reg {
+	a_uint32_t  spare_reg:32;
+};
+
+union pc_spare_reg_u {
+	a_uint32_t val;
+	struct pc_spare_reg bf;
+};
+
+/*[register] TIME_SLOT_REG*/
+#define TIME_SLOT_REG
+#define TIME_SLOT_REG_ADDRESS 0x40
+#define TIME_SLOT_REG_NUM     1
+#define TIME_SLOT_REG_INC     0x4
+#define TIME_SLOT_REG_TYPE    REG_TYPE_RW
+#define TIME_SLOT_REG_DEFAULT 0x0
+	/*[field] TIME_SLOT*/
+	#define TIME_SLOT_REG_TIME_SLOT
+	#define TIME_SLOT_REG_TIME_SLOT_OFFSET  0
+	#define TIME_SLOT_REG_TIME_SLOT_LEN     10
+	#define TIME_SLOT_REG_TIME_SLOT_DEFAULT 0x0
+
+struct time_slot_reg {
+	a_uint32_t  time_slot:10;
+	a_uint32_t  _reserved0:22;
+};
+
+union time_slot_reg_u {
+	a_uint32_t val;
+	struct time_slot_reg bf;
+};
+
+/*[register] PC_DBG_ADDR_REG*/
+#define PC_DBG_ADDR_REG
+#define PC_DBG_ADDR_REG_ADDRESS 0x80
+#define PC_DBG_ADDR_REG_NUM     1
+#define PC_DBG_ADDR_REG_INC     0x4
+#define PC_DBG_ADDR_REG_TYPE    REG_TYPE_RW
+#define PC_DBG_ADDR_REG_DEFAULT 0x0
+	/*[field] DBG_ADDR*/
+	#define PC_DBG_ADDR_REG_DBG_ADDR
+	#define PC_DBG_ADDR_REG_DBG_ADDR_OFFSET  24
+	#define PC_DBG_ADDR_REG_DBG_ADDR_LEN     8
+	#define PC_DBG_ADDR_REG_DBG_ADDR_DEFAULT 0x0
+
+struct pc_dbg_addr_reg {
+	a_uint32_t  dbg_addr:8;
+};
+
+union pc_dbg_addr_reg_u {
+	a_uint32_t val;
+	struct pc_dbg_addr_reg bf;
+};
+
+/*[register] PC_DBG_DATA_REG*/
+#define PC_DBG_DATA_REG
+#define PC_DBG_DATA_REG_ADDRESS 0x84
+#define PC_DBG_DATA_REG_NUM     1
+#define PC_DBG_DATA_REG_INC     0x4
+#define PC_DBG_DATA_REG_TYPE    REG_TYPE_RO
+#define PC_DBG_DATA_REG_DEFAULT 0x0
+	/*[field] DBG_DATA*/
+	#define PC_DBG_DATA_REG_DBG_DATA
+	#define PC_DBG_DATA_REG_DBG_DATA_OFFSET  0
+	#define PC_DBG_DATA_REG_DBG_DATA_LEN     32
+	#define PC_DBG_DATA_REG_DBG_DATA_DEFAULT 0x0
+
+struct pc_dbg_data_reg {
+	a_uint32_t  dbg_data:32;
+};
+
+union pc_dbg_data_reg_u {
+	a_uint32_t val;
+	struct pc_dbg_data_reg bf;
+};
+
+/*[table] IN_ACL_METER_CFG_TBL*/
+#define IN_ACL_METER_CFG_TBL
+#define IN_ACL_METER_CFG_TBL_ADDRESS 0x4000
+#define IN_ACL_METER_CFG_TBL_NUM     512
+#define IN_ACL_METER_CFG_TBL_INC     0x10
+#define IN_ACL_METER_CFG_TBL_TYPE    REG_TYPE_RW
+#define IN_ACL_METER_CFG_TBL_DEFAULT 0x0
+	/*[field] METER_EN*/
+	#define IN_ACL_METER_CFG_TBL_METER_EN
+	#define IN_ACL_METER_CFG_TBL_METER_EN_OFFSET  0
+	#define IN_ACL_METER_CFG_TBL_METER_EN_LEN     1
+	#define IN_ACL_METER_CFG_TBL_METER_EN_DEFAULT 0x0
+	/*[field] COLOR_MODE*/
+	#define IN_ACL_METER_CFG_TBL_COLOR_MODE
+	#define IN_ACL_METER_CFG_TBL_COLOR_MODE_OFFSET  1
+	#define IN_ACL_METER_CFG_TBL_COLOR_MODE_LEN     1
+	#define IN_ACL_METER_CFG_TBL_COLOR_MODE_DEFAULT 0x0
+	/*[field] COUPLING_FLAG*/
+	#define IN_ACL_METER_CFG_TBL_COUPLING_FLAG
+	#define IN_ACL_METER_CFG_TBL_COUPLING_FLAG_OFFSET  2
+	#define IN_ACL_METER_CFG_TBL_COUPLING_FLAG_LEN     1
+	#define IN_ACL_METER_CFG_TBL_COUPLING_FLAG_DEFAULT 0x0
+	/*[field] METER_MODE*/
+	#define IN_ACL_METER_CFG_TBL_METER_MODE
+	#define IN_ACL_METER_CFG_TBL_METER_MODE_OFFSET  3
+	#define IN_ACL_METER_CFG_TBL_METER_MODE_LEN     1
+	#define IN_ACL_METER_CFG_TBL_METER_MODE_DEFAULT 0x0
+	/*[field] TOKEN_UNIT*/
+	#define IN_ACL_METER_CFG_TBL_TOKEN_UNIT
+	#define IN_ACL_METER_CFG_TBL_TOKEN_UNIT_OFFSET  4
+	#define IN_ACL_METER_CFG_TBL_TOKEN_UNIT_LEN     3
+	#define IN_ACL_METER_CFG_TBL_TOKEN_UNIT_DEFAULT 0x0
+	/*[field] METER_UNIT*/
+	#define IN_ACL_METER_CFG_TBL_METER_UNIT
+	#define IN_ACL_METER_CFG_TBL_METER_UNIT_OFFSET  7
+	#define IN_ACL_METER_CFG_TBL_METER_UNIT_LEN     1
+	#define IN_ACL_METER_CFG_TBL_METER_UNIT_DEFAULT 0x0
+	/*[field] CBS*/
+	#define IN_ACL_METER_CFG_TBL_CBS
+	#define IN_ACL_METER_CFG_TBL_CBS_OFFSET  8
+	#define IN_ACL_METER_CFG_TBL_CBS_LEN     16
+	#define IN_ACL_METER_CFG_TBL_CBS_DEFAULT 0x0
+	/*[field] CIR*/
+	#define IN_ACL_METER_CFG_TBL_CIR
+	#define IN_ACL_METER_CFG_TBL_CIR_OFFSET  24
+	#define IN_ACL_METER_CFG_TBL_CIR_LEN     18
+	#define IN_ACL_METER_CFG_TBL_CIR_DEFAULT 0x0
+	/*[field] EBS*/
+	#define IN_ACL_METER_CFG_TBL_EBS
+	#define IN_ACL_METER_CFG_TBL_EBS_OFFSET  42
+	#define IN_ACL_METER_CFG_TBL_EBS_LEN     16
+	#define IN_ACL_METER_CFG_TBL_EBS_DEFAULT 0x0
+	/*[field] EIR*/
+	#define IN_ACL_METER_CFG_TBL_EIR
+	#define IN_ACL_METER_CFG_TBL_EIR_OFFSET  58
+	#define IN_ACL_METER_CFG_TBL_EIR_LEN     18
+	#define IN_ACL_METER_CFG_TBL_EIR_DEFAULT 0x0
+	/*[field] EXCEED_CHG_PRI_CMD*/
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PRI_CMD
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PRI_CMD_OFFSET  76
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PRI_CMD_LEN     1
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PRI_CMD_DEFAULT 0x0
+	/*[field] EXCEED_CHG_DP_CMD*/
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DP_CMD
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DP_CMD_OFFSET  77
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DP_CMD_LEN     1
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DP_CMD_DEFAULT 0x0
+	/*[field] EXCEED_CHG_PCP_CMD*/
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PCP_CMD
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PCP_CMD_OFFSET  78
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PCP_CMD_LEN     1
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PCP_CMD_DEFAULT 0x0
+	/*[field] EXCEED_CHG_DEI_CMD*/
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DEI_CMD
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DEI_CMD_OFFSET  79
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DEI_CMD_LEN     1
+	#define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DEI_CMD_DEFAULT 0x0
+	/*[field] EXCEED_PRI*/
+	#define IN_ACL_METER_CFG_TBL_EXCEED_PRI
+	#define IN_ACL_METER_CFG_TBL_EXCEED_PRI_OFFSET  80
+	#define IN_ACL_METER_CFG_TBL_EXCEED_PRI_LEN     4
+	#define IN_ACL_METER_CFG_TBL_EXCEED_PRI_DEFAULT 0x0
+	/*[field] EXCEED_DP*/
+	#define IN_ACL_METER_CFG_TBL_EXCEED_DP
+	#define IN_ACL_METER_CFG_TBL_EXCEED_DP_OFFSET  84
+	#define IN_ACL_METER_CFG_TBL_EXCEED_DP_LEN     2
+	#define IN_ACL_METER_CFG_TBL_EXCEED_DP_DEFAULT 0x0
+	/*[field] EXCEED_PCP*/
+	#define IN_ACL_METER_CFG_TBL_EXCEED_PCP
+	#define IN_ACL_METER_CFG_TBL_EXCEED_PCP_OFFSET  86
+	#define IN_ACL_METER_CFG_TBL_EXCEED_PCP_LEN     3
+	#define IN_ACL_METER_CFG_TBL_EXCEED_PCP_DEFAULT 0x0
+	/*[field] EXCEED_DEI*/
+	#define IN_ACL_METER_CFG_TBL_EXCEED_DEI
+	#define IN_ACL_METER_CFG_TBL_EXCEED_DEI_OFFSET  89
+	#define IN_ACL_METER_CFG_TBL_EXCEED_DEI_LEN     1
+	#define IN_ACL_METER_CFG_TBL_EXCEED_DEI_DEFAULT 0x0
+	/*[field] VIOLATE_CMD*/
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CMD
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CMD_OFFSET  90
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CMD_LEN     1
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CMD_DEFAULT 0x0
+	/*[field] VIOLATE_CHG_PRI_CMD*/
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD_OFFSET  91
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD_LEN     1
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD_DEFAULT 0x0
+	/*[field] VIOLATE_CHG_DP_CMD*/
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DP_CMD
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DP_CMD_OFFSET  92
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DP_CMD_LEN     1
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DP_CMD_DEFAULT 0x0
+	/*[field] VIOLATE_CHG_PCP_CMD*/
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD_OFFSET  93
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD_LEN     1
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD_DEFAULT 0x0
+	/*[field] VIOLATE_CHG_DEI_CMD*/
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD_OFFSET  94
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD_LEN     1
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD_DEFAULT 0x0
+	/*[field] VIOLATE_PRI*/
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_PRI
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_PRI_OFFSET  95
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_PRI_LEN     4
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_PRI_DEFAULT 0x0
+	/*[field] VIOLATE_DP*/
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_DP
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_DP_OFFSET  99
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_DP_LEN     2
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_DP_DEFAULT 0x0
+	/*[field] VIOLATE_PCP*/
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_PCP
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_PCP_OFFSET  101
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_PCP_LEN     3
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_PCP_DEFAULT 0x0
+	/*[field] VIOLATE_DEI*/
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_DEI
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_DEI_OFFSET  104
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_DEI_LEN     1
+	#define IN_ACL_METER_CFG_TBL_VIOLATE_DEI_DEFAULT 0x0
+
+struct in_acl_meter_cfg_tbl {
+	a_uint32_t  meter_en:1;
+	a_uint32_t  color_mode:1;
+	a_uint32_t  coupling_flag:1;
+	a_uint32_t  meter_mode:1;
+	a_uint32_t  token_unit:3;
+	a_uint32_t  meter_unit:1;
+	a_uint32_t  cbs:16;
+	a_uint32_t  cir_0:8;
+	a_uint32_t  cir_1:10;
+	a_uint32_t  ebs:16;
+	a_uint32_t  eir_0:6;
+	a_uint32_t  eir_1:12;
+	a_uint32_t  exceed_chg_pri_cmd:1;
+	a_uint32_t  exceed_chg_dp_cmd:1;
+	a_uint32_t  exceed_chg_pcp_cmd:1;
+	a_uint32_t  exceed_chg_dei_cmd:1;
+	a_uint32_t  exceed_pri:4;
+	a_uint32_t  exceed_dp:2;
+	a_uint32_t  exceed_pcp:3;
+	a_uint32_t  exceed_dei:1;
+	a_uint32_t  violate_cmd:1;
+	a_uint32_t  violate_chg_pri_cmd:1;
+	a_uint32_t  violate_chg_dp_cmd:1;
+	a_uint32_t  violate_chg_pcp_cmd:1;
+	a_uint32_t  violate_chg_dei_cmd:1;
+	a_uint32_t  violate_pri_0:1;
+	a_uint32_t  violate_pri_1:3;
+	a_uint32_t  violate_dp:2;
+	a_uint32_t  violate_pcp:3;
+	a_uint32_t  violate_dei:1;
+	a_uint32_t  _reserved0:23;
+};
+
+union in_acl_meter_cfg_tbl_u {
+	a_uint32_t val[4];
+	struct in_acl_meter_cfg_tbl bf;
+};
+
+/*[table] IN_ACL_METER_CRDT_TBL*/
+#define IN_ACL_METER_CRDT_TBL
+#define IN_ACL_METER_CRDT_TBL_ADDRESS 0x8000
+#define IN_ACL_METER_CRDT_TBL_NUM     512
+#define IN_ACL_METER_CRDT_TBL_INC     0x10
+#define IN_ACL_METER_CRDT_TBL_TYPE    REG_TYPE_RW
+#define IN_ACL_METER_CRDT_TBL_DEFAULT 0x0
+	/*[field] C_CRDT*/
+	#define IN_ACL_METER_CRDT_TBL_C_CRDT
+	#define IN_ACL_METER_CRDT_TBL_C_CRDT_OFFSET  0
+	#define IN_ACL_METER_CRDT_TBL_C_CRDT_LEN     32
+	#define IN_ACL_METER_CRDT_TBL_C_CRDT_DEFAULT 0x0
+	/*[field] E_CRDT*/
+	#define IN_ACL_METER_CRDT_TBL_E_CRDT
+	#define IN_ACL_METER_CRDT_TBL_E_CRDT_OFFSET  32
+	#define IN_ACL_METER_CRDT_TBL_E_CRDT_LEN     32
+	#define IN_ACL_METER_CRDT_TBL_E_CRDT_DEFAULT 0x0
+
+struct in_acl_meter_crdt_tbl {
+	a_uint32_t  c_crdt:32;
+	a_uint32_t  e_crdt:32;
+};
+
+union in_acl_meter_crdt_tbl_u {
+	a_uint32_t val[2];
+	struct in_acl_meter_crdt_tbl bf;
+};
+
+/*[table] IN_PORT_METER_CFG_TBL*/
+#define IN_PORT_METER_CFG_TBL
+#define IN_PORT_METER_CFG_TBL_ADDRESS 0xc000
+#define IN_PORT_METER_CFG_TBL_NUM     8
+#define IN_PORT_METER_CFG_TBL_INC     0x10
+#define IN_PORT_METER_CFG_TBL_TYPE    REG_TYPE_RW
+#define IN_PORT_METER_CFG_TBL_DEFAULT 0x0
+	/*[field] METER_EN*/
+	#define IN_PORT_METER_CFG_TBL_METER_EN
+	#define IN_PORT_METER_CFG_TBL_METER_EN_OFFSET  0
+	#define IN_PORT_METER_CFG_TBL_METER_EN_LEN     1
+	#define IN_PORT_METER_CFG_TBL_METER_EN_DEFAULT 0x0
+	/*[field] COLOR_MODE*/
+	#define IN_PORT_METER_CFG_TBL_COLOR_MODE
+	#define IN_PORT_METER_CFG_TBL_COLOR_MODE_OFFSET  1
+	#define IN_PORT_METER_CFG_TBL_COLOR_MODE_LEN     1
+	#define IN_PORT_METER_CFG_TBL_COLOR_MODE_DEFAULT 0x0
+	/*[field] METER_FLAG*/
+	#define IN_PORT_METER_CFG_TBL_METER_FLAG
+	#define IN_PORT_METER_CFG_TBL_METER_FLAG_OFFSET  2
+	#define IN_PORT_METER_CFG_TBL_METER_FLAG_LEN     5
+	#define IN_PORT_METER_CFG_TBL_METER_FLAG_DEFAULT 0x0
+	/*[field] COUPLING_FLAG*/
+	#define IN_PORT_METER_CFG_TBL_COUPLING_FLAG
+	#define IN_PORT_METER_CFG_TBL_COUPLING_FLAG_OFFSET  7
+	#define IN_PORT_METER_CFG_TBL_COUPLING_FLAG_LEN     1
+	#define IN_PORT_METER_CFG_TBL_COUPLING_FLAG_DEFAULT 0x0
+	/*[field] METER_MODE*/
+	#define IN_PORT_METER_CFG_TBL_METER_MODE
+	#define IN_PORT_METER_CFG_TBL_METER_MODE_OFFSET  8
+	#define IN_PORT_METER_CFG_TBL_METER_MODE_LEN     1
+	#define IN_PORT_METER_CFG_TBL_METER_MODE_DEFAULT 0x0
+	/*[field] TOKEN_UNIT*/
+	#define IN_PORT_METER_CFG_TBL_TOKEN_UNIT
+	#define IN_PORT_METER_CFG_TBL_TOKEN_UNIT_OFFSET  9
+	#define IN_PORT_METER_CFG_TBL_TOKEN_UNIT_LEN     3
+	#define IN_PORT_METER_CFG_TBL_TOKEN_UNIT_DEFAULT 0x0
+	/*[field] METER_UNIT*/
+	#define IN_PORT_METER_CFG_TBL_METER_UNIT
+	#define IN_PORT_METER_CFG_TBL_METER_UNIT_OFFSET  12
+	#define IN_PORT_METER_CFG_TBL_METER_UNIT_LEN     1
+	#define IN_PORT_METER_CFG_TBL_METER_UNIT_DEFAULT 0x0
+	/*[field] CBS*/
+	#define IN_PORT_METER_CFG_TBL_CBS
+	#define IN_PORT_METER_CFG_TBL_CBS_OFFSET  13
+	#define IN_PORT_METER_CFG_TBL_CBS_LEN     16
+	#define IN_PORT_METER_CFG_TBL_CBS_DEFAULT 0x0
+	/*[field] CIR*/
+	#define IN_PORT_METER_CFG_TBL_CIR
+	#define IN_PORT_METER_CFG_TBL_CIR_OFFSET  29
+	#define IN_PORT_METER_CFG_TBL_CIR_LEN     18
+	#define IN_PORT_METER_CFG_TBL_CIR_DEFAULT 0x0
+	/*[field] EBS*/
+	#define IN_PORT_METER_CFG_TBL_EBS
+	#define IN_PORT_METER_CFG_TBL_EBS_OFFSET  47
+	#define IN_PORT_METER_CFG_TBL_EBS_LEN     16
+	#define IN_PORT_METER_CFG_TBL_EBS_DEFAULT 0x0
+	/*[field] EIR*/
+	#define IN_PORT_METER_CFG_TBL_EIR
+	#define IN_PORT_METER_CFG_TBL_EIR_OFFSET  63
+	#define IN_PORT_METER_CFG_TBL_EIR_LEN     18
+	#define IN_PORT_METER_CFG_TBL_EIR_DEFAULT 0x0
+	/*[field] EXCEED_CHG_PRI_CMD*/
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PRI_CMD
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PRI_CMD_OFFSET  81
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PRI_CMD_LEN     1
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PRI_CMD_DEFAULT 0x0
+	/*[field] EXCEED_CHG_DP_CMD*/
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DP_CMD
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DP_CMD_OFFSET  82
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DP_CMD_LEN     1
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DP_CMD_DEFAULT 0x0
+	/*[field] EXCEED_CHG_PCP_CMD*/
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PCP_CMD
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PCP_CMD_OFFSET  83
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PCP_CMD_LEN     1
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PCP_CMD_DEFAULT 0x0
+	/*[field] EXCEED_CHG_DEI_CMD*/
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DEI_CMD
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DEI_CMD_OFFSET  84
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DEI_CMD_LEN     1
+	#define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DEI_CMD_DEFAULT 0x0
+	/*[field] EXCEED_PRI*/
+	#define IN_PORT_METER_CFG_TBL_EXCEED_PRI
+	#define IN_PORT_METER_CFG_TBL_EXCEED_PRI_OFFSET  85
+	#define IN_PORT_METER_CFG_TBL_EXCEED_PRI_LEN     4
+	#define IN_PORT_METER_CFG_TBL_EXCEED_PRI_DEFAULT 0x0
+	/*[field] EXCEED_DP*/
+	#define IN_PORT_METER_CFG_TBL_EXCEED_DP
+	#define IN_PORT_METER_CFG_TBL_EXCEED_DP_OFFSET  89
+	#define IN_PORT_METER_CFG_TBL_EXCEED_DP_LEN     2
+	#define IN_PORT_METER_CFG_TBL_EXCEED_DP_DEFAULT 0x0
+	/*[field] EXCEED_PCP*/
+	#define IN_PORT_METER_CFG_TBL_EXCEED_PCP
+	#define IN_PORT_METER_CFG_TBL_EXCEED_PCP_OFFSET  91
+	#define IN_PORT_METER_CFG_TBL_EXCEED_PCP_LEN     3
+	#define IN_PORT_METER_CFG_TBL_EXCEED_PCP_DEFAULT 0x0
+	/*[field] EXCEED_DEI*/
+	#define IN_PORT_METER_CFG_TBL_EXCEED_DEI
+	#define IN_PORT_METER_CFG_TBL_EXCEED_DEI_OFFSET  94
+	#define IN_PORT_METER_CFG_TBL_EXCEED_DEI_LEN     1
+	#define IN_PORT_METER_CFG_TBL_EXCEED_DEI_DEFAULT 0x0
+	/*[field] VIOLATE_CMD*/
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CMD
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CMD_OFFSET  95
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CMD_LEN     1
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CMD_DEFAULT 0x0
+	/*[field] VIOLATE_CHG_PRI_CMD*/
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD_OFFSET  96
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD_LEN     1
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD_DEFAULT 0x0
+	/*[field] VIOLATE_CHG_DP_CMD*/
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DP_CMD
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DP_CMD_OFFSET  97
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DP_CMD_LEN     1
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DP_CMD_DEFAULT 0x0
+	/*[field] VIOLATE_CHG_PCP_CMD*/
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD_OFFSET  98
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD_LEN     1
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD_DEFAULT 0x0
+	/*[field] VIOLATE_CHG_DEI_CMD*/
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD_OFFSET  99
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD_LEN     1
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD_DEFAULT 0x0
+	/*[field] VIOLATE_PRI*/
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_PRI
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_PRI_OFFSET  100
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_PRI_LEN     4
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_PRI_DEFAULT 0x0
+	/*[field] VIOLATE_DP*/
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_DP
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_DP_OFFSET  104
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_DP_LEN     2
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_DP_DEFAULT 0x0
+	/*[field] VIOLATE_PCP*/
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_PCP
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_PCP_OFFSET  106
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_PCP_LEN     3
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_PCP_DEFAULT 0x0
+	/*[field] VIOLATE_DEI*/
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_DEI
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_DEI_OFFSET  109
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_DEI_LEN     1
+	#define IN_PORT_METER_CFG_TBL_VIOLATE_DEI_DEFAULT 0x0
+
+struct in_port_meter_cfg_tbl {
+	a_uint32_t  meter_en:1;
+	a_uint32_t  color_mode:1;
+	a_uint32_t  meter_flag:5;
+	a_uint32_t  coupling_flag:1;
+	a_uint32_t  meter_mode:1;
+	a_uint32_t  token_unit:3;
+	a_uint32_t  meter_unit:1;
+	a_uint32_t  cbs:16;
+	a_uint32_t  cir_0:3;
+	a_uint32_t  cir_1:15;
+	a_uint32_t  ebs:16;
+	a_uint32_t  eir_0:1;
+	a_uint32_t  eir_1:17;
+	a_uint32_t  exceed_chg_pri_cmd:1;
+	a_uint32_t  exceed_chg_dp_cmd:1;
+	a_uint32_t  exceed_chg_pcp_cmd:1;
+	a_uint32_t  exceed_chg_dei_cmd:1;
+	a_uint32_t  exceed_pri:4;
+	a_uint32_t  exceed_dp:2;
+	a_uint32_t  exceed_pcp:3;
+	a_uint32_t  exceed_dei:1;
+	a_uint32_t  violate_cmd:1;
+	a_uint32_t  violate_chg_pri_cmd:1;
+	a_uint32_t  violate_chg_dp_cmd:1;
+	a_uint32_t  violate_chg_pcp_cmd:1;
+	a_uint32_t  violate_chg_dei_cmd:1;
+	a_uint32_t  violate_pri:4;
+	a_uint32_t  violate_dp:2;
+	a_uint32_t  violate_pcp:3;
+	a_uint32_t  violate_dei:1;
+	a_uint32_t  _reserved0:18;
+};
+
+union in_port_meter_cfg_tbl_u {
+	a_uint32_t val[4];
+	struct in_port_meter_cfg_tbl bf;
+};
+
+/*[table] IN_PORT_METER_CRDT_TBL*/
+#define IN_PORT_METER_CRDT_TBL
+#define IN_PORT_METER_CRDT_TBL_ADDRESS 0xd000
+#define IN_PORT_METER_CRDT_TBL_NUM     8
+#define IN_PORT_METER_CRDT_TBL_INC     0x10
+#define IN_PORT_METER_CRDT_TBL_TYPE    REG_TYPE_RW
+#define IN_PORT_METER_CRDT_TBL_DEFAULT 0x0
+	/*[field] C_CRDT*/
+	#define IN_PORT_METER_CRDT_TBL_C_CRDT
+	#define IN_PORT_METER_CRDT_TBL_C_CRDT_OFFSET  0
+	#define IN_PORT_METER_CRDT_TBL_C_CRDT_LEN     32
+	#define IN_PORT_METER_CRDT_TBL_C_CRDT_DEFAULT 0x0
+	/*[field] E_CRDT*/
+	#define IN_PORT_METER_CRDT_TBL_E_CRDT
+	#define IN_PORT_METER_CRDT_TBL_E_CRDT_OFFSET  32
+	#define IN_PORT_METER_CRDT_TBL_E_CRDT_LEN     32
+	#define IN_PORT_METER_CRDT_TBL_E_CRDT_DEFAULT 0x0
+
+struct in_port_meter_crdt_tbl {
+	a_uint32_t  c_crdt:32;
+	a_uint32_t  e_crdt:32;
+};
+
+union in_port_meter_crdt_tbl_u {
+	a_uint32_t val[2];
+	struct in_port_meter_crdt_tbl bf;
+};
+
+/*[table] IN_PORT_METER_CNT_TBL*/
+#define IN_PORT_METER_CNT_TBL
+#define IN_PORT_METER_CNT_TBL_ADDRESS 0xe000
+#define IN_PORT_METER_CNT_TBL_NUM     24
+#define IN_PORT_METER_CNT_TBL_INC     0x10
+#define IN_PORT_METER_CNT_TBL_TYPE    REG_TYPE_RW
+#define IN_PORT_METER_CNT_TBL_DEFAULT 0x0
+	/*[field] PKT_CNT*/
+	#define IN_PORT_METER_CNT_TBL_PKT_CNT
+	#define IN_PORT_METER_CNT_TBL_PKT_CNT_OFFSET  0
+	#define IN_PORT_METER_CNT_TBL_PKT_CNT_LEN     32
+	#define IN_PORT_METER_CNT_TBL_PKT_CNT_DEFAULT 0x0
+	/*[field] BYTE_CNT*/
+	#define IN_PORT_METER_CNT_TBL_BYTE_CNT
+	#define IN_PORT_METER_CNT_TBL_BYTE_CNT_OFFSET  32
+	#define IN_PORT_METER_CNT_TBL_BYTE_CNT_LEN     40
+	#define IN_PORT_METER_CNT_TBL_BYTE_CNT_DEFAULT 0x0
+
+struct in_port_meter_cnt_tbl {
+	a_uint32_t  pkt_cnt:32;
+	a_uint32_t  byte_cnt_0:32;
+	a_uint32_t  byte_cnt_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union in_port_meter_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct in_port_meter_cnt_tbl bf;
+};
+
+/*[table] IN_ACL_METER_CNT_TBL*/
+#define IN_ACL_METER_CNT_TBL
+#define IN_ACL_METER_CNT_TBL_ADDRESS 0x10000
+#define IN_ACL_METER_CNT_TBL_NUM     1536
+#define IN_ACL_METER_CNT_TBL_INC     0x10
+#define IN_ACL_METER_CNT_TBL_TYPE    REG_TYPE_RW
+#define IN_ACL_METER_CNT_TBL_DEFAULT 0x0
+	/*[field] PKT_CNT*/
+	#define IN_ACL_METER_CNT_TBL_PKT_CNT
+	#define IN_ACL_METER_CNT_TBL_PKT_CNT_OFFSET  0
+	#define IN_ACL_METER_CNT_TBL_PKT_CNT_LEN     32
+	#define IN_ACL_METER_CNT_TBL_PKT_CNT_DEFAULT 0x0
+	/*[field] BYTE_CNT*/
+	#define IN_ACL_METER_CNT_TBL_BYTE_CNT
+	#define IN_ACL_METER_CNT_TBL_BYTE_CNT_OFFSET  32
+	#define IN_ACL_METER_CNT_TBL_BYTE_CNT_LEN     40
+	#define IN_ACL_METER_CNT_TBL_BYTE_CNT_DEFAULT 0x0
+
+struct in_acl_meter_cnt_tbl {
+	a_uint32_t  pkt_cnt:32;
+	a_uint32_t  byte_cnt_0:32;
+	a_uint32_t  byte_cnt_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union in_acl_meter_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct in_acl_meter_cnt_tbl bf;
+};
+
+/*[table] PC_GLOBAL_CNT_TBL*/
+#define PC_GLOBAL_CNT_TBL
+#define PC_GLOBAL_CNT_TBL_ADDRESS 0x58000
+#define PC_GLOBAL_CNT_TBL_NUM     3
+#define PC_GLOBAL_CNT_TBL_INC     0x10
+#define PC_GLOBAL_CNT_TBL_TYPE    REG_TYPE_RW
+#define PC_GLOBAL_CNT_TBL_DEFAULT 0x0
+	/*[field] PKT_CNT*/
+	#define PC_GLOBAL_CNT_TBL_PKT_CNT
+	#define PC_GLOBAL_CNT_TBL_PKT_CNT_OFFSET  0
+	#define PC_GLOBAL_CNT_TBL_PKT_CNT_LEN     32
+	#define PC_GLOBAL_CNT_TBL_PKT_CNT_DEFAULT 0x0
+	/*[field] BYTE_CNT*/
+	#define PC_GLOBAL_CNT_TBL_BYTE_CNT
+	#define PC_GLOBAL_CNT_TBL_BYTE_CNT_OFFSET  32
+	#define PC_GLOBAL_CNT_TBL_BYTE_CNT_LEN     40
+	#define PC_GLOBAL_CNT_TBL_BYTE_CNT_DEFAULT 0x0
+
+struct pc_global_cnt_tbl {
+	a_uint32_t  pkt_cnt:32;
+	a_uint32_t  byte_cnt_0:32;
+	a_uint32_t  byte_cnt_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union pc_global_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct pc_global_cnt_tbl bf;
+};
+
+/*[table] DROP_CPU_CNT_TBL*/
+#define DROP_CPU_CNT_TBL
+#define DROP_CPU_CNT_TBL_ADDRESS 0x60000
+#define DROP_CPU_CNT_TBL_NUM     1280
+#define DROP_CPU_CNT_TBL_INC     0x10
+#define DROP_CPU_CNT_TBL_TYPE    REG_TYPE_RW
+#define DROP_CPU_CNT_TBL_DEFAULT 0x0
+	/*[field] PKT_CNT*/
+	#define DROP_CPU_CNT_TBL_PKT_CNT
+	#define DROP_CPU_CNT_TBL_PKT_CNT_OFFSET  0
+	#define DROP_CPU_CNT_TBL_PKT_CNT_LEN     32
+	#define DROP_CPU_CNT_TBL_PKT_CNT_DEFAULT 0x0
+	/*[field] BYTE_CNT*/
+	#define DROP_CPU_CNT_TBL_BYTE_CNT
+	#define DROP_CPU_CNT_TBL_BYTE_CNT_OFFSET  32
+	#define DROP_CPU_CNT_TBL_BYTE_CNT_LEN     40
+	#define DROP_CPU_CNT_TBL_BYTE_CNT_DEFAULT 0x0
+
+struct drop_cpu_cnt_tbl {
+	a_uint32_t  pkt_cnt:32;
+	a_uint32_t  byte_cnt_0:32;
+	a_uint32_t  byte_cnt_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union drop_cpu_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct drop_cpu_cnt_tbl bf;
+};
+
+/*[table] PORT_TX_DROP_CNT_TBL*/
+#define PORT_TX_DROP_CNT_TBL
+#define PORT_TX_DROP_CNT_TBL_ADDRESS 0x7d000
+#define PORT_TX_DROP_CNT_TBL_NUM     8
+#define PORT_TX_DROP_CNT_TBL_INC     0x10
+#define PORT_TX_DROP_CNT_TBL_TYPE    REG_TYPE_RW
+#define PORT_TX_DROP_CNT_TBL_DEFAULT 0x0
+	/*[field] TX_DROP_PKT_CNT*/
+	#define PORT_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT
+	#define PORT_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT_OFFSET  0
+	#define PORT_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT_LEN     32
+	#define PORT_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT_DEFAULT 0x0
+	/*[field] TX_DROP_BYTE_CNT*/
+	#define PORT_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT
+	#define PORT_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT_OFFSET  32
+	#define PORT_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT_LEN     40
+	#define PORT_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT_DEFAULT 0x0
+
+struct port_tx_drop_cnt_tbl {
+	a_uint32_t  tx_drop_pkt_cnt:32;
+	a_uint32_t  tx_drop_byte_cnt_0:32;
+	a_uint32_t  tx_drop_byte_cnt_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union port_tx_drop_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct port_tx_drop_cnt_tbl bf;
+};
+
+/*[table] VP_TX_DROP_CNT_TBL*/
+#define VP_TX_DROP_CNT_TBL
+#define VP_TX_DROP_CNT_TBL_ADDRESS 0x7e000
+#define VP_TX_DROP_CNT_TBL_NUM     256
+#define VP_TX_DROP_CNT_TBL_INC     0x10
+#define VP_TX_DROP_CNT_TBL_TYPE    REG_TYPE_RW
+#define VP_TX_DROP_CNT_TBL_DEFAULT 0x0
+	/*[field] TX_DROP_PKT_CNT*/
+	#define VP_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT
+	#define VP_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT_OFFSET  0
+	#define VP_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT_LEN     32
+	#define VP_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT_DEFAULT 0x0
+	/*[field] TX_DROP_BYTE_CNT*/
+	#define VP_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT
+	#define VP_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT_OFFSET  32
+	#define VP_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT_LEN     40
+	#define VP_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT_DEFAULT 0x0
+
+struct vp_tx_drop_cnt_tbl {
+	a_uint32_t  tx_drop_pkt_cnt:32;
+	a_uint32_t  tx_drop_byte_cnt_0:32;
+	a_uint32_t  tx_drop_byte_cnt_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union vp_tx_drop_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct vp_tx_drop_cnt_tbl bf;
+};
+
+/*[table] VLAN_DEV_CNT_TBL*/
+#define VLAN_DEV_CNT_TBL
+#define VLAN_DEV_CNT_TBL_ADDRESS 0x7f000
+#define VLAN_DEV_CNT_TBL_NUM     64
+#define VLAN_DEV_CNT_TBL_INC     0x10
+#define VLAN_DEV_CNT_TBL_TYPE    REG_TYPE_RW
+#define VLAN_DEV_CNT_TBL_DEFAULT 0x0
+	/*[field] RX_PKT_CNT*/
+	#define VLAN_DEV_CNT_TBL_RX_PKT_CNT
+	#define VLAN_DEV_CNT_TBL_RX_PKT_CNT_OFFSET  0
+	#define VLAN_DEV_CNT_TBL_RX_PKT_CNT_LEN     32
+	#define VLAN_DEV_CNT_TBL_RX_PKT_CNT_DEFAULT 0x0
+	/*[field] RX_BYTE_CNT*/
+	#define VLAN_DEV_CNT_TBL_RX_BYTE_CNT
+	#define VLAN_DEV_CNT_TBL_RX_BYTE_CNT_OFFSET  32
+	#define VLAN_DEV_CNT_TBL_RX_BYTE_CNT_LEN     40
+	#define VLAN_DEV_CNT_TBL_RX_BYTE_CNT_DEFAULT 0x0
+
+struct vlan_dev_cnt_tbl {
+	a_uint32_t  rx_pkt_cnt:32;
+	a_uint32_t  rx_byte_cnt_0:32;
+	a_uint32_t  rx_byte_cnt_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union vlan_dev_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct vlan_dev_cnt_tbl bf;
+};
+
+
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_portctrl.h b/qca-ssdk/include/hsl/hppe/hppe_portctrl.h
new file mode 100755
index 0000000..e14ed31
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_portctrl.h
@@ -0,0 +1,1413 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_PORTCTRL_H_
+#define _HPPE_PORTCTRL_H_
+
+
+#define MAC_ENABLE_MAX_ENTRY	6
+#define MAC_SPEED_MAX_ENTRY	6
+#define GOL_MAC_ADDR0_MAX_ENTRY	6
+#define GOL_MAC_ADDR1_MAX_ENTRY	6
+#define MAC_CTRL0_MAX_ENTRY	6
+#define MAC_CTRL1_MAX_ENTRY	6
+#define MAC_CTRL2_MAX_ENTRY	6
+#define MAC_DBG_CTRL_MAX_ENTRY	6
+#define MAC_DBG_ADDR_MAX_ENTRY	6
+#define MAC_DBG_DATA_MAX_ENTRY	6
+#define MAC_JUMBO_SIZE_MAX_ENTRY	6
+#define MC_MTU_CTRL_TBL_MAX_ENTRY	8
+#define MRU_MTU_CTRL_TBL_MAX_ENTRY	256
+#define RX_FIFO_CFG_MAX_ENTRY	8
+#define TDM_CFG_MAX_ENTRY	128
+#define PORT_IN_FORWARD_MAX_ENTRY	8
+#define PORT_TX_COUNTER_TBL_REG_MAX_ENTRY	8
+#define VP_TX_COUNTER_TBL_REG_MAX_ENTRY	256
+#define IPR_PKT_NUM_TBL_REG_MAX_ENTRY	8
+#define IPR_BYTE_LOW_REG_REG_MAX_ENTRY	8
+#define IPR_BYTE_HIGH_REG_MAX_ENTRY	8
+#define DROP_CNT_MAX_ENTRY	8
+#define DROP_PKT_STAT_MAX_ENTRY	30
+
+
+sw_error_t
+hppe_mac_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_enable_u *value);
+
+sw_error_t
+hppe_mac_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_enable_u *value);
+
+sw_error_t
+hppe_mac_speed_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_speed_u *value);
+
+sw_error_t
+hppe_mac_speed_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_speed_u *value);
+
+sw_error_t
+hppe_gol_mac_addr0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union gol_mac_addr0_u *value);
+
+sw_error_t
+hppe_gol_mac_addr0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union gol_mac_addr0_u *value);
+
+sw_error_t
+hppe_gol_mac_addr1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union gol_mac_addr1_u *value);
+
+sw_error_t
+hppe_gol_mac_addr1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union gol_mac_addr1_u *value);
+
+sw_error_t
+hppe_mac_ctrl0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_ctrl0_u *value);
+
+sw_error_t
+hppe_mac_ctrl0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_ctrl0_u *value);
+
+sw_error_t
+hppe_mac_ctrl1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_ctrl1_u *value);
+
+sw_error_t
+hppe_mac_ctrl1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_ctrl1_u *value);
+
+sw_error_t
+hppe_mac_ctrl2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_ctrl2_u *value);
+
+sw_error_t
+hppe_mac_ctrl2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_ctrl2_u *value);
+
+sw_error_t
+hppe_mac_dbg_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_dbg_ctrl_u *value);
+
+sw_error_t
+hppe_mac_dbg_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_dbg_ctrl_u *value);
+
+sw_error_t
+hppe_mac_dbg_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_dbg_addr_u *value);
+
+sw_error_t
+hppe_mac_dbg_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_dbg_addr_u *value);
+
+sw_error_t
+hppe_mac_dbg_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_dbg_data_u *value);
+
+sw_error_t
+hppe_mac_dbg_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_dbg_data_u *value);
+
+sw_error_t
+hppe_mac_jumbo_size_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_jumbo_size_u *value);
+
+sw_error_t
+hppe_mac_jumbo_size_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_jumbo_size_u *value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mru_mtu_ctrl_tbl_u *value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mru_mtu_ctrl_tbl_u *value);
+
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mc_mtu_ctrl_tbl_u *value);
+
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mc_mtu_ctrl_tbl_u *value);
+
+sw_error_t
+hppe_tdm_ctrl_get(
+		a_uint32_t dev_id,
+		union tdm_ctrl_u *value);
+
+sw_error_t
+hppe_tdm_ctrl_set(
+		a_uint32_t dev_id,
+		union tdm_ctrl_u *value);
+
+sw_error_t
+hppe_rx_fifo_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_fifo_cfg_u *value);
+
+sw_error_t
+hppe_rx_fifo_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_fifo_cfg_u *value);
+
+sw_error_t
+hppe_tdm_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tdm_cfg_u *value);
+
+sw_error_t
+hppe_tdm_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tdm_cfg_u *value);
+
+sw_error_t
+hppe_drop_stat_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union drop_stat_u *value);
+
+sw_error_t
+hppe_drop_stat_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union drop_stat_u *value);
+
+sw_error_t
+hppe_mac_enable_txmac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_enable_txmac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_enable_rxmac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_enable_rxmac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_enable_tx_flow_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_enable_tx_flow_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_enable_rx_flow_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_enable_rx_flow_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_enable_duplex_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_enable_duplex_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_speed_mac_speed_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_speed_mac_speed_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_gol_mac_addr0_mac_addr_byte4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_gol_mac_addr0_mac_addr_byte4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_gol_mac_addr0_mac_addr_byte5_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_gol_mac_addr0_mac_addr_byte5_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte3_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte3_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl0_amaxc_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl0_amaxc_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl0_ipgt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl0_ipgt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl0_nobo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl0_nobo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl0_half_thdf_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl0_half_thdf_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl0_hugen_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl0_hugen_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl0_bpnb_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl0_bpnb_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl0_flchk_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl0_flchk_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl0_ipgr2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl0_ipgr2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl0_drbnib_rxok_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl0_drbnib_rxok_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl0_huge_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl0_huge_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl0_abebe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl0_abebe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl1_povr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl1_povr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl1_simr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl1_simr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl1_jam_ipg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl1_jam_ipg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl1_lcol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl1_lcol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl1_tctl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl1_tctl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl1_retry_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl1_retry_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl1_prlen_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl1_prlen_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl1_ppad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl1_ppad_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl1_long_jam_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl1_long_jam_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl1_phug_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl1_phug_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl1_sstct_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl1_sstct_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl1_mbof_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl1_mbof_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl1_tpause_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl1_tpause_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl2_ipg_dec_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl2_ipg_dec_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl2_mac_rsv_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl2_mac_rsv_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl2_mac_tx_thd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl2_mac_tx_thd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl2_crc_rsv_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl2_crc_rsv_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl2_crs_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl2_crs_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl2_ipg_dec_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl2_ipg_dec_len_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl2_maxfr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl2_maxfr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl2_mac_lpi_tx_idle_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl2_mac_lpi_tx_idle_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl2_mac_loop_back_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl2_mac_loop_back_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_ctrl2_test_pause_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_ctrl2_test_pause_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_dbg_ctrl_edxsdfr_transmit_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_dbg_ctrl_edxsdfr_transmit_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_dbg_ctrl_hihg_ipg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_dbg_ctrl_hihg_ipg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_dbg_ctrl_mac_ipg_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_dbg_ctrl_mac_ipg_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_dbg_ctrl_mac_len_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_dbg_ctrl_mac_len_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_dbg_ctrl_ipgr1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_dbg_ctrl_ipgr1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_dbg_addr_mac_debug_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_dbg_addr_mac_debug_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_dbg_data_mac_debug_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_dbg_data_mac_debug_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_jumbo_size_mac_jumbo_size_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_jumbo_size_mac_jumbo_size_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_mtu_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_mtu_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_rx_cnt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_rx_cnt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_tx_cnt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_tx_cnt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_mru_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_mru_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_mru_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_mru_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_src_profile_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_src_profile_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_mtu_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_mtu_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_mtu_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_mtu_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_tx_cnt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_tx_cnt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_mtu_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_mtu_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+sw_error_t
+hppe_tdm_ctrl_tdm_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_tdm_ctrl_tdm_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_tdm_ctrl_tdm_offset_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_tdm_ctrl_tdm_offset_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_tdm_ctrl_tdm_depth_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_tdm_ctrl_tdm_depth_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_rx_fifo_cfg_rx_fifo_thres_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_fifo_cfg_rx_fifo_thres_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tdm_cfg_port_num_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tdm_cfg_port_num_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tdm_cfg_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tdm_cfg_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tdm_cfg_dir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tdm_cfg_dir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_in_forward_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_in_forward_u *value);
+
+sw_error_t
+hppe_port_in_forward_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_in_forward_u *value);
+
+sw_error_t
+hppe_port_in_forward_source_filtering_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_in_forward_source_filtering_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+sw_error_t
+hppe_port_tx_counter_tbl_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_tx_counter_tbl_reg_u *value);
+
+sw_error_t
+hppe_port_tx_counter_tbl_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_tx_counter_tbl_reg_u *value);
+
+sw_error_t
+hppe_vp_tx_counter_tbl_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vp_tx_counter_tbl_reg_u *value);
+
+sw_error_t
+hppe_vp_tx_counter_tbl_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vp_tx_counter_tbl_reg_u *value);
+
+sw_error_t
+hppe_epe_dbg_in_cnt_reg_get(
+		a_uint32_t dev_id,
+		union epe_dbg_in_cnt_reg_u *value);
+
+sw_error_t
+hppe_epe_dbg_in_cnt_reg_set(
+		a_uint32_t dev_id,
+		union epe_dbg_in_cnt_reg_u *value);
+
+sw_error_t
+hppe_epe_dbg_out_cnt_reg_get(
+		a_uint32_t dev_id,
+		union epe_dbg_out_cnt_reg_u *value);
+
+sw_error_t
+hppe_epe_dbg_out_cnt_reg_set(
+		a_uint32_t dev_id,
+		union epe_dbg_out_cnt_reg_u *value);
+
+sw_error_t
+hppe_port_tx_counter_tbl_reg_tx_bytes_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_port_tx_counter_tbl_reg_tx_bytes_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_port_tx_counter_tbl_reg_tx_packets_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_tx_counter_tbl_reg_tx_packets_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vp_tx_counter_tbl_reg_tx_bytes_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_vp_tx_counter_tbl_reg_tx_bytes_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_vp_tx_counter_tbl_reg_tx_packets_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vp_tx_counter_tbl_reg_tx_packets_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_epe_dbg_in_cnt_reg_counter_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_epe_dbg_in_cnt_reg_counter_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_epe_dbg_out_cnt_reg_counter_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_epe_dbg_out_cnt_reg_counter_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_drop_stat_bytes_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_drop_stat_bytes_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_drop_stat_pkts_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_drop_stat_pkts_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_lpi_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_enable_u *value);
+
+sw_error_t
+hppe_lpi_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_enable_u *value);
+
+sw_error_t
+hppe_lpi_timer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_port_timer_u *value);
+
+sw_error_t
+hppe_lpi_timer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_port_timer_u *value);
+
+sw_error_t
+hppe_lpi_dbg_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_dbg_addr_u *value);
+
+sw_error_t
+hppe_lpi_adb_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_dbg_addr_u *value);
+
+sw_error_t
+hppe_lpi_dbg_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_dbg_data_u *value);
+
+sw_error_t
+hppe_lpi_adb_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_dbg_data_u *value);
+
+sw_error_t
+hppe_lpi_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_cnt_u *value);
+
+sw_error_t
+hppe_lpi_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_cnt_u *value);
+
+sw_error_t
+hppe_drop_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union drop_cnt_u *value);
+
+sw_error_t
+hppe_drop_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union drop_cnt_u *value);
+
+sw_error_t
+hppe_drop_cnt_drop_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_drop_cnt_drop_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipr_pkt_num_tbl_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipr_pkt_num_tbl_reg_u *value);
+
+sw_error_t
+hppe_ipr_pkt_num_tbl_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipr_pkt_num_tbl_reg_u *value);
+
+sw_error_t
+hppe_ipr_byte_low_reg_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipr_byte_low_reg_reg_u *value);
+
+sw_error_t
+hppe_ipr_byte_low_reg_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipr_byte_low_reg_reg_u *value);
+
+sw_error_t
+hppe_ipr_byte_high_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipr_byte_high_reg_u *value);
+
+sw_error_t
+hppe_ipr_byte_high_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipr_byte_high_reg_u *value);
+
+sw_error_t
+hppe_ipr_pkt_num_tbl_reg_packets_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipr_pkt_num_tbl_reg_packets_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipr_byte_low_reg_reg_bytes_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipr_byte_low_reg_reg_bytes_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ipr_byte_high_reg_bytes_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ipr_byte_high_reg_bytes_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_portctrl_reg.h b/qca-ssdk/include/hsl/hppe/hppe_portctrl_reg.h
new file mode 100755
index 0000000..ecef92a
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_portctrl_reg.h
@@ -0,0 +1,1119 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_PORTCTRL_REG_H
+#define HPPE_PORTCTRL_REG_H
+
+/*[register] MAC_ENABLE*/
+#define MAC_ENABLE
+#define MAC_ENABLE_ADDRESS 0x0
+#define MAC_ENABLE_NUM     6
+#define MAC_ENABLE_INC     0x200
+#define MAC_ENABLE_TYPE    REG_TYPE_RW
+#define MAC_ENABLE_DEFAULT 0x10
+	/*[field] RXMAC_EN*/
+	#define MAC_ENABLE_RXMAC_EN
+	#define MAC_ENABLE_RXMAC_EN_OFFSET  0
+	#define MAC_ENABLE_RXMAC_EN_LEN     1
+	#define MAC_ENABLE_RXMAC_EN_DEFAULT 0x0
+	/*[field] TXMAC_EN*/
+	#define MAC_ENABLE_TXMAC_EN
+	#define MAC_ENABLE_TXMAC_EN_OFFSET  1
+	#define MAC_ENABLE_TXMAC_EN_LEN     1
+	#define MAC_ENABLE_TXMAC_EN_DEFAULT 0x0
+	/*[field] DUPLEX*/
+	#define MAC_ENABLE_DUPLEX
+	#define MAC_ENABLE_DUPLEX_OFFSET  4
+	#define MAC_ENABLE_DUPLEX_LEN     1
+	#define MAC_ENABLE_DUPLEX_DEFAULT 0x1
+	/*[field] RX_FLOW_EN*/
+	#define MAC_ENABLE_RX_FLOW_EN
+	#define MAC_ENABLE_RX_FLOW_EN_OFFSET  5
+	#define MAC_ENABLE_RX_FLOW_EN_LEN     1
+	#define MAC_ENABLE_RX_FLOW_EN_DEFAULT 0x0
+	/*[field] TX_FLOW_EN*/
+	#define MAC_ENABLE_TX_FLOW_EN
+	#define MAC_ENABLE_TX_FLOW_EN_OFFSET  6
+	#define MAC_ENABLE_TX_FLOW_EN_LEN     1
+	#define MAC_ENABLE_TX_FLOW_EN_DEFAULT 0x0
+
+struct mac_enable {
+	a_uint32_t  rxmac_en:1;
+	a_uint32_t  txmac_en:1;
+	a_uint32_t  _reserved0:2;
+	a_uint32_t  duplex:1;
+	a_uint32_t  rx_flow_en:1;
+	a_uint32_t  tx_flow_en:1;
+	a_uint32_t  _reserved1:25;
+};
+
+union mac_enable_u {
+	a_uint32_t val;
+	struct mac_enable bf;
+};
+
+/*[register] MAC_SPEED*/
+#define MAC_SPEED
+#define MAC_SPEED_ADDRESS 0x4
+#define MAC_SPEED_NUM     6
+#define MAC_SPEED_INC     0x200
+#define MAC_SPEED_TYPE    REG_TYPE_RW
+#define MAC_SPEED_DEFAULT 0x0
+	/*[field] MAC_SPEED*/
+	#define MAC_SPEED_MAC_SPEED
+	#define MAC_SPEED_MAC_SPEED_OFFSET  0
+	#define MAC_SPEED_MAC_SPEED_LEN     2
+	#define MAC_SPEED_MAC_SPEED_DEFAULT 0x0
+
+struct mac_speed {
+	a_uint32_t  mac_speed:2;
+	a_uint32_t  _reserved0:30;
+};
+
+union mac_speed_u {
+	a_uint32_t val;
+	struct mac_speed bf;
+};
+
+/*[register] GOL_MAC_ADDR0*/
+#define GOL_MAC_ADDR0
+#define GOL_MAC_ADDR0_ADDRESS 0x8
+#define GOL_MAC_ADDR0_NUM     6
+#define GOL_MAC_ADDR0_INC     0x200
+#define GOL_MAC_ADDR0_TYPE    REG_TYPE_RW
+#define GOL_MAC_ADDR0_DEFAULT 0x1
+	/*[field] MAC_ADDR_BYTE4*/
+	#define GOL_MAC_ADDR0_MAC_ADDR_BYTE4
+	#define GOL_MAC_ADDR0_MAC_ADDR_BYTE4_OFFSET  0
+	#define GOL_MAC_ADDR0_MAC_ADDR_BYTE4_LEN     8
+	#define GOL_MAC_ADDR0_MAC_ADDR_BYTE4_DEFAULT 0x1
+	/*[field] MAC_ADDR_BYTE5*/
+	#define GOL_MAC_ADDR0_MAC_ADDR_BYTE5
+	#define GOL_MAC_ADDR0_MAC_ADDR_BYTE5_OFFSET  8
+	#define GOL_MAC_ADDR0_MAC_ADDR_BYTE5_LEN     8
+	#define GOL_MAC_ADDR0_MAC_ADDR_BYTE5_DEFAULT 0x0
+
+struct gol_mac_addr0 {
+	a_uint32_t  mac_addr_byte4:8;
+	a_uint32_t  mac_addr_byte5:8;
+	a_uint32_t  _reserved0:16;
+};
+
+union gol_mac_addr0_u {
+	a_uint32_t val;
+	struct gol_mac_addr0 bf;
+};
+
+/*[register] GOL_MAC_ADDR1*/
+#define GOL_MAC_ADDR1
+#define GOL_MAC_ADDR1_ADDRESS 0xc
+#define GOL_MAC_ADDR1_NUM     6
+#define GOL_MAC_ADDR1_INC     0x200
+#define GOL_MAC_ADDR1_TYPE    REG_TYPE_RW
+#define GOL_MAC_ADDR1_DEFAULT 0x0
+	/*[field] MAC_ADDR_BYTE3*/
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE3
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE3_OFFSET  0
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE3_LEN     8
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE3_DEFAULT 0x0
+	/*[field] MAC_ADDR_BYTE2*/
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE2
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE2_OFFSET  8
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE2_LEN     8
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE2_DEFAULT 0x0
+	/*[field] MAC_ADDR_BYTE1*/
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE1
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE1_OFFSET  16
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE1_LEN     8
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE1_DEFAULT 0x0
+	/*[field] MAC_ADDR_BYTE0*/
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE0
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE0_OFFSET  24
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE0_LEN     8
+	#define GOL_MAC_ADDR1_MAC_ADDR_BYTE0_DEFAULT 0x0
+
+struct gol_mac_addr1 {
+	a_uint32_t  mac_addr_byte3:8;
+	a_uint32_t  mac_addr_byte2:8;
+	a_uint32_t  mac_addr_byte1:8;
+	a_uint32_t  mac_addr_byte0:8;
+};
+
+union gol_mac_addr1_u {
+	a_uint32_t val;
+	struct gol_mac_addr1 bf;
+};
+
+/*[register] MAC_CTRL0*/
+#define MAC_CTRL0
+#define MAC_CTRL0_ADDRESS 0x10
+#define MAC_CTRL0_NUM     6
+#define MAC_CTRL0_INC     0x200
+#define MAC_CTRL0_TYPE    REG_TYPE_RW
+#define MAC_CTRL0_DEFAULT 0xb00e6060
+	/*[field] IPGT*/
+	#define MAC_CTRL0_IPGT
+	#define MAC_CTRL0_IPGT_OFFSET  0
+	#define MAC_CTRL0_IPGT_LEN     7
+	#define MAC_CTRL0_IPGT_DEFAULT 0x60
+	/*[field] IPGR2*/
+	#define MAC_CTRL0_IPGR2
+	#define MAC_CTRL0_IPGR2_OFFSET  8
+	#define MAC_CTRL0_IPGR2_LEN     7
+	#define MAC_CTRL0_IPGR2_DEFAULT 0x60
+	/*[field] HALF_THDF_CTRL*/
+	#define MAC_CTRL0_HALF_THDF_CTRL
+	#define MAC_CTRL0_HALF_THDF_CTRL_OFFSET  15
+	#define MAC_CTRL0_HALF_THDF_CTRL_LEN     1
+	#define MAC_CTRL0_HALF_THDF_CTRL_DEFAULT 0x0
+	/*[field] HUGEN*/
+	#define MAC_CTRL0_HUGEN
+	#define MAC_CTRL0_HUGEN_OFFSET  16
+	#define MAC_CTRL0_HUGEN_LEN     1
+	#define MAC_CTRL0_HUGEN_DEFAULT 0x0
+	/*[field] HUGE*/
+	#define MAC_CTRL0_HUGE
+	#define MAC_CTRL0_HUGE_OFFSET  17
+	#define MAC_CTRL0_HUGE_LEN     1
+	#define MAC_CTRL0_HUGE_DEFAULT 0x1
+	/*[field] FLCHK*/
+	#define MAC_CTRL0_FLCHK
+	#define MAC_CTRL0_FLCHK_OFFSET  18
+	#define MAC_CTRL0_FLCHK_LEN     1
+	#define MAC_CTRL0_FLCHK_DEFAULT 0x1
+	/*[field] ABEBE*/
+	#define MAC_CTRL0_ABEBE
+	#define MAC_CTRL0_ABEBE_OFFSET  19
+	#define MAC_CTRL0_ABEBE_LEN     1
+	#define MAC_CTRL0_ABEBE_DEFAULT 0x1
+	/*[field] AMAXC_EN*/
+	#define MAC_CTRL0_AMAXC_EN
+	#define MAC_CTRL0_AMAXC_EN_OFFSET  28
+	#define MAC_CTRL0_AMAXC_EN_LEN     1
+	#define MAC_CTRL0_AMAXC_EN_DEFAULT 0x1
+	/*[field] BPNB*/
+	#define MAC_CTRL0_BPNB
+	#define MAC_CTRL0_BPNB_OFFSET  29
+	#define MAC_CTRL0_BPNB_LEN     1
+	#define MAC_CTRL0_BPNB_DEFAULT 0x1
+	/*[field] NOBO*/
+	#define MAC_CTRL0_NOBO
+	#define MAC_CTRL0_NOBO_OFFSET  30
+	#define MAC_CTRL0_NOBO_LEN     1
+	#define MAC_CTRL0_NOBO_DEFAULT 0x0
+	/*[field] DRBNIB_RXOK_EN*/
+	#define MAC_CTRL0_DRBNIB_RXOK_EN
+	#define MAC_CTRL0_DRBNIB_RXOK_EN_OFFSET  31
+	#define MAC_CTRL0_DRBNIB_RXOK_EN_LEN     1
+	#define MAC_CTRL0_DRBNIB_RXOK_EN_DEFAULT 0x1
+
+struct mac_ctrl0 {
+	a_uint32_t  ipgt:7;
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  ipgr2:7;
+	a_uint32_t  half_thdf_ctrl:1;
+	a_uint32_t  hugen:1;
+	a_uint32_t  huge:1;
+	a_uint32_t  flchk:1;
+	a_uint32_t  abebe:1;
+	a_uint32_t  _reserved1:8;
+	a_uint32_t  amaxc_en:1;
+	a_uint32_t  bpnb:1;
+	a_uint32_t  nobo:1;
+	a_uint32_t  drbnib_rxok_en:1;
+};
+
+union mac_ctrl0_u {
+	a_uint32_t val;
+	struct mac_ctrl0 bf;
+};
+
+/*[register] MAC_CTRL1*/
+#define MAC_CTRL1
+#define MAC_CTRL1_ADDRESS 0x14
+#define MAC_CTRL1_NUM     6
+#define MAC_CTRL1_INC     0x200
+#define MAC_CTRL1_TYPE    REG_TYPE_RW
+#define MAC_CTRL1_DEFAULT 0x3707f07
+	/*[field] JAM_IPG*/
+	#define MAC_CTRL1_JAM_IPG
+	#define MAC_CTRL1_JAM_IPG_OFFSET  0
+	#define MAC_CTRL1_JAM_IPG_LEN     4
+	#define MAC_CTRL1_JAM_IPG_DEFAULT 0x7
+	/*[field] TPAUSE*/
+	#define MAC_CTRL1_TPAUSE
+	#define MAC_CTRL1_TPAUSE_OFFSET  4
+	#define MAC_CTRL1_TPAUSE_LEN     1
+	#define MAC_CTRL1_TPAUSE_DEFAULT 0x0
+	/*[field] TCTL*/
+	#define MAC_CTRL1_TCTL
+	#define MAC_CTRL1_TCTL_OFFSET  5
+	#define MAC_CTRL1_TCTL_LEN     1
+	#define MAC_CTRL1_TCTL_DEFAULT 0x0
+	/*[field] SSTCT*/
+	#define MAC_CTRL1_SSTCT
+	#define MAC_CTRL1_SSTCT_OFFSET  6
+	#define MAC_CTRL1_SSTCT_LEN     1
+	#define MAC_CTRL1_SSTCT_DEFAULT 0x0
+	/*[field] SIMR*/
+	#define MAC_CTRL1_SIMR
+	#define MAC_CTRL1_SIMR_OFFSET  7
+	#define MAC_CTRL1_SIMR_LEN     1
+	#define MAC_CTRL1_SIMR_DEFAULT 0x0
+	/*[field] RETRY*/
+	#define MAC_CTRL1_RETRY
+	#define MAC_CTRL1_RETRY_OFFSET  8
+	#define MAC_CTRL1_RETRY_LEN     4
+	#define MAC_CTRL1_RETRY_DEFAULT 0xf
+	/*[field] PRLEN*/
+	#define MAC_CTRL1_PRLEN
+	#define MAC_CTRL1_PRLEN_OFFSET  12
+	#define MAC_CTRL1_PRLEN_LEN     4
+	#define MAC_CTRL1_PRLEN_DEFAULT 0x7
+	/*[field] PPAD*/
+	#define MAC_CTRL1_PPAD
+	#define MAC_CTRL1_PPAD_OFFSET  16
+	#define MAC_CTRL1_PPAD_LEN     1
+	#define MAC_CTRL1_PPAD_DEFAULT 0x0
+	/*[field] POVR*/
+	#define MAC_CTRL1_POVR
+	#define MAC_CTRL1_POVR_OFFSET  17
+	#define MAC_CTRL1_POVR_LEN     1
+	#define MAC_CTRL1_POVR_DEFAULT 0x0
+	/*[field] PHUG*/
+	#define MAC_CTRL1_PHUG
+	#define MAC_CTRL1_PHUG_OFFSET  18
+	#define MAC_CTRL1_PHUG_LEN     1
+	#define MAC_CTRL1_PHUG_DEFAULT 0x0
+	/*[field] MBOF*/
+	#define MAC_CTRL1_MBOF
+	#define MAC_CTRL1_MBOF_OFFSET  19
+	#define MAC_CTRL1_MBOF_LEN     1
+	#define MAC_CTRL1_MBOF_DEFAULT 0x0
+	/*[field] LCOL*/
+	#define MAC_CTRL1_LCOL
+	#define MAC_CTRL1_LCOL_OFFSET  20
+	#define MAC_CTRL1_LCOL_LEN     8
+	#define MAC_CTRL1_LCOL_DEFAULT 0x37
+	/*[field] LONG_JAM_EN*/
+	#define MAC_CTRL1_LONG_JAM_EN
+	#define MAC_CTRL1_LONG_JAM_EN_OFFSET  28
+	#define MAC_CTRL1_LONG_JAM_EN_LEN     1
+	#define MAC_CTRL1_LONG_JAM_EN_DEFAULT 0x0
+
+struct mac_ctrl1 {
+	a_uint32_t  jam_ipg:4;
+	a_uint32_t  tpause:1;
+	a_uint32_t  tctl:1;
+	a_uint32_t  sstct:1;
+	a_uint32_t  simr:1;
+	a_uint32_t  retry:4;
+	a_uint32_t  prlen:4;
+	a_uint32_t  ppad:1;
+	a_uint32_t  povr:1;
+	a_uint32_t  phug:1;
+	a_uint32_t  mbof:1;
+	a_uint32_t  lcol:8;
+	a_uint32_t  long_jam_en:1;
+	a_uint32_t  _reserved0:3;
+};
+
+union mac_ctrl1_u {
+	a_uint32_t val;
+	struct mac_ctrl1 bf;
+};
+
+/*[register] MAC_CTRL2*/
+#define MAC_CTRL2
+#define MAC_CTRL2_ADDRESS 0x18
+#define MAC_CTRL2_NUM     6
+#define MAC_CTRL2_INC     0x200
+#define MAC_CTRL2_TYPE    REG_TYPE_RW
+#define MAC_CTRL2_DEFAULT 0xc271c40
+	/*[field] IPG_DEC_LEN*/
+	#define MAC_CTRL2_IPG_DEC_LEN
+	#define MAC_CTRL2_IPG_DEC_LEN_OFFSET  1
+	#define MAC_CTRL2_IPG_DEC_LEN_LEN     1
+	#define MAC_CTRL2_IPG_DEC_LEN_DEFAULT 0x0
+	/*[field] TEST_PAUSE*/
+	#define MAC_CTRL2_TEST_PAUSE
+	#define MAC_CTRL2_TEST_PAUSE_OFFSET  2
+	#define MAC_CTRL2_TEST_PAUSE_LEN     1
+	#define MAC_CTRL2_TEST_PAUSE_DEFAULT 0x0
+	/*[field] MAC_LPI_TX_IDLE*/
+	#define MAC_CTRL2_MAC_LPI_TX_IDLE
+	#define MAC_CTRL2_MAC_LPI_TX_IDLE_OFFSET  3
+	#define MAC_CTRL2_MAC_LPI_TX_IDLE_LEN     1
+	#define MAC_CTRL2_MAC_LPI_TX_IDLE_DEFAULT 0x0
+	/*[field] MAC_LOOP_BACK*/
+	#define MAC_CTRL2_MAC_LOOP_BACK
+	#define MAC_CTRL2_MAC_LOOP_BACK_OFFSET  4
+	#define MAC_CTRL2_MAC_LOOP_BACK_LEN     1
+	#define MAC_CTRL2_MAC_LOOP_BACK_DEFAULT 0x0
+	/*[field] IPG_DEC_EN*/
+	#define MAC_CTRL2_IPG_DEC_EN
+	#define MAC_CTRL2_IPG_DEC_EN_OFFSET  5
+	#define MAC_CTRL2_IPG_DEC_EN_LEN     1
+	#define MAC_CTRL2_IPG_DEC_EN_DEFAULT 0x0
+	/*[field] CRS_SEL*/
+	#define MAC_CTRL2_CRS_SEL
+	#define MAC_CTRL2_CRS_SEL_OFFSET  6
+	#define MAC_CTRL2_CRS_SEL_LEN     1
+	#define MAC_CTRL2_CRS_SEL_DEFAULT 0x1
+	/*[field] CRC_RSV_EN*/
+	#define MAC_CTRL2_CRC_RSV_EN
+	#define MAC_CTRL2_CRC_RSV_EN_OFFSET  7
+	#define MAC_CTRL2_CRC_RSV_EN_LEN     1
+	#define MAC_CTRL2_CRC_RSV_EN_DEFAULT 0x0
+	/*[field] MAXFR*/
+	#define MAC_CTRL2_MAXFR
+	#define MAC_CTRL2_MAXFR_OFFSET  8
+	#define MAC_CTRL2_MAXFR_LEN     14
+	#define MAC_CTRL2_MAXFR_DEFAULT 0x271c
+	/*[field] MAC_TX_THD*/
+	#define MAC_CTRL2_MAC_TX_THD
+	#define MAC_CTRL2_MAC_TX_THD_OFFSET  24
+	#define MAC_CTRL2_MAC_TX_THD_LEN     4
+	#define MAC_CTRL2_MAC_TX_THD_DEFAULT 0xc
+	/*[field] MAC_RSV*/
+	#define MAC_CTRL2_MAC_RSV
+	#define MAC_CTRL2_MAC_RSV_OFFSET  28
+	#define MAC_CTRL2_MAC_RSV_LEN     4
+	#define MAC_CTRL2_MAC_RSV_DEFAULT 0x0
+
+struct mac_ctrl2 {
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  ipg_dec_len:1;
+	a_uint32_t  test_pause:1;
+	a_uint32_t  mac_lpi_tx_idle:1;
+	a_uint32_t  mac_loop_back:1;
+	a_uint32_t  ipg_dec_en:1;
+	a_uint32_t  crs_sel:1;
+	a_uint32_t  crc_rsv_en:1;
+	a_uint32_t  maxfr:14;
+	a_uint32_t  _reserved1:2;
+	a_uint32_t  mac_tx_thd:4;
+	a_uint32_t  mac_rsv:4;
+};
+
+union mac_ctrl2_u {
+	a_uint32_t val;
+	struct mac_ctrl2 bf;
+};
+
+/*[register] MAC_DBG_CTRL*/
+#define MAC_DBG_CTRL
+#define MAC_DBG_CTRL_ADDRESS 0x1c
+#define MAC_DBG_CTRL_NUM     6
+#define MAC_DBG_CTRL_INC     0x200
+#define MAC_DBG_CTRL_TYPE    REG_TYPE_RW
+#define MAC_DBG_CTRL_DEFAULT 0x80701040
+	/*[field] IPGR1*/
+	#define MAC_DBG_CTRL_IPGR1
+	#define MAC_DBG_CTRL_IPGR1_OFFSET  0
+	#define MAC_DBG_CTRL_IPGR1_LEN     7
+	#define MAC_DBG_CTRL_IPGR1_DEFAULT 0x40
+	/*[field] HIHG_IPG*/
+	#define MAC_DBG_CTRL_HIHG_IPG
+	#define MAC_DBG_CTRL_HIHG_IPG_OFFSET  8
+	#define MAC_DBG_CTRL_HIHG_IPG_LEN     8
+	#define MAC_DBG_CTRL_HIHG_IPG_DEFAULT 0x10
+	/*[field] MAC_IPG_CTRL*/
+	#define MAC_DBG_CTRL_MAC_IPG_CTRL
+	#define MAC_DBG_CTRL_MAC_IPG_CTRL_OFFSET  20
+	#define MAC_DBG_CTRL_MAC_IPG_CTRL_LEN     4
+	#define MAC_DBG_CTRL_MAC_IPG_CTRL_DEFAULT 0x7
+	/*[field] MAC_LEN_CTRL*/
+	#define MAC_DBG_CTRL_MAC_LEN_CTRL
+	#define MAC_DBG_CTRL_MAC_LEN_CTRL_OFFSET  30
+	#define MAC_DBG_CTRL_MAC_LEN_CTRL_LEN     1
+	#define MAC_DBG_CTRL_MAC_LEN_CTRL_DEFAULT 0x0
+	/*[field] EDXSDFR_TRANSMIT_EN*/
+	#define MAC_DBG_CTRL_EDXSDFR_TRANSMIT_EN
+	#define MAC_DBG_CTRL_EDXSDFR_TRANSMIT_EN_OFFSET  31
+	#define MAC_DBG_CTRL_EDXSDFR_TRANSMIT_EN_LEN     1
+	#define MAC_DBG_CTRL_EDXSDFR_TRANSMIT_EN_DEFAULT 0x1
+
+struct mac_dbg_ctrl {
+	a_uint32_t  ipgr1:7;
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  hihg_ipg:8;
+	a_uint32_t  _reserved1:4;
+	a_uint32_t  mac_ipg_ctrl:4;
+	a_uint32_t  _reserved2:6;
+	a_uint32_t  mac_len_ctrl:1;
+	a_uint32_t  edxsdfr_transmit_en:1;
+};
+
+union mac_dbg_ctrl_u {
+	a_uint32_t val;
+	struct mac_dbg_ctrl bf;
+};
+
+/*[register] MAC_DBG_ADDR*/
+#define MAC_DBG_ADDR
+#define MAC_DBG_ADDR_ADDRESS 0x20
+#define MAC_DBG_ADDR_NUM     6
+#define MAC_DBG_ADDR_INC     0x200
+#define MAC_DBG_ADDR_TYPE    REG_TYPE_RW
+#define MAC_DBG_ADDR_DEFAULT 0x0
+	/*[field] MAC_DEBUG_ADDR*/
+	#define MAC_DBG_ADDR_MAC_DEBUG_ADDR
+	#define MAC_DBG_ADDR_MAC_DEBUG_ADDR_OFFSET  0
+	#define MAC_DBG_ADDR_MAC_DEBUG_ADDR_LEN     8
+	#define MAC_DBG_ADDR_MAC_DEBUG_ADDR_DEFAULT 0x0
+
+struct mac_dbg_addr {
+	a_uint32_t  mac_debug_addr:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union mac_dbg_addr_u {
+	a_uint32_t val;
+	struct mac_dbg_addr bf;
+};
+
+/*[register] MAC_DBG_DATA*/
+#define MAC_DBG_DATA
+#define MAC_DBG_DATA_ADDRESS 0x24
+#define MAC_DBG_DATA_NUM     6
+#define MAC_DBG_DATA_INC     0x200
+#define MAC_DBG_DATA_TYPE    REG_TYPE_RO
+#define MAC_DBG_DATA_DEFAULT 0x0
+	/*[field] MAC_DEBUG_DATA*/
+	#define MAC_DBG_DATA_MAC_DEBUG_DATA
+	#define MAC_DBG_DATA_MAC_DEBUG_DATA_OFFSET  0
+	#define MAC_DBG_DATA_MAC_DEBUG_DATA_LEN     32
+	#define MAC_DBG_DATA_MAC_DEBUG_DATA_DEFAULT 0x0
+
+struct mac_dbg_data {
+	a_uint32_t  mac_debug_data:32;
+};
+
+union mac_dbg_data_u {
+	a_uint32_t val;
+	struct mac_dbg_data bf;
+};
+
+/*[register] MAC_JUMBO_SIZE*/
+#define MAC_JUMBO_SIZE
+#define MAC_JUMBO_SIZE_ADDRESS 0x30
+#define MAC_JUMBO_SIZE_NUM     6
+#define MAC_JUMBO_SIZE_INC     0x200
+#define MAC_JUMBO_SIZE_TYPE    REG_TYPE_RW
+#define MAC_JUMBO_SIZE_DEFAULT 0x271c
+	/*[field] MAC_JUMBO_SIZE*/
+	#define MAC_JUMBO_SIZE_MAC_JUMBO_SIZE
+	#define MAC_JUMBO_SIZE_MAC_JUMBO_SIZE_OFFSET  0
+	#define MAC_JUMBO_SIZE_MAC_JUMBO_SIZE_LEN     14
+	#define MAC_JUMBO_SIZE_MAC_JUMBO_SIZE_DEFAULT 0x271c
+
+struct mac_jumbo_size {
+	a_uint32_t  mac_jumbo_size:14;
+	a_uint32_t  _reserved0:18;
+};
+
+union mac_jumbo_size_u {
+	a_uint32_t val;
+	struct mac_jumbo_size bf;
+};
+
+/*[register] PORT_IN_FORWARD*/
+#define PORT_IN_FORWARD
+#define PORT_IN_FORWARD_ADDRESS 0x700
+#define PORT_IN_FORWARD_NUM     8
+#define PORT_IN_FORWARD_INC     0x4
+#define PORT_IN_FORWARD_TYPE    REG_TYPE_RW
+#define PORT_IN_FORWARD_DEFAULT 0x0
+	/*[field] SOURCE_FILTERING_BYPASS*/
+	#define PORT_IN_FORWARD_SOURCE_FILTERING_BYPASS
+	#define PORT_IN_FORWARD_SOURCE_FILTERING_BYPASS_OFFSET  0
+	#define PORT_IN_FORWARD_SOURCE_FILTERING_BYPASS_LEN     1
+	#define PORT_IN_FORWARD_SOURCE_FILTERING_BYPASS_DEFAULT 0x0
+
+struct port_in_forward {
+	a_uint32_t  source_filtering_bypass:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union port_in_forward_u {
+	a_uint32_t val;
+	struct port_in_forward bf;
+};
+
+/*[table] MRU_MTU_CTRL_TBL*/
+#define MRU_MTU_CTRL_TBL
+#define MRU_MTU_CTRL_TBL_ADDRESS 0x3000
+#define MRU_MTU_CTRL_TBL_NUM     256
+#define MRU_MTU_CTRL_TBL_INC     0x8
+#define MRU_MTU_CTRL_TBL_TYPE    REG_TYPE_RW
+#define MRU_MTU_CTRL_TBL_DEFAULT 0x0
+	/*[field] MRU*/
+	#define MRU_MTU_CTRL_TBL_MRU
+	#define MRU_MTU_CTRL_TBL_MRU_OFFSET  0
+	#define MRU_MTU_CTRL_TBL_MRU_LEN     14
+	#define MRU_MTU_CTRL_TBL_MRU_DEFAULT 0x0
+	/*[field] MRU_CMD*/
+	#define MRU_MTU_CTRL_TBL_MRU_CMD
+	#define MRU_MTU_CTRL_TBL_MRU_CMD_OFFSET  14
+	#define MRU_MTU_CTRL_TBL_MRU_CMD_LEN     2
+	#define MRU_MTU_CTRL_TBL_MRU_CMD_DEFAULT 0x0
+	/*[field] MTU*/
+	#define MRU_MTU_CTRL_TBL_MTU
+	#define MRU_MTU_CTRL_TBL_MTU_OFFSET  16
+	#define MRU_MTU_CTRL_TBL_MTU_LEN     14
+	#define MRU_MTU_CTRL_TBL_MTU_DEFAULT 0x0
+	/*[field] MTU_CMD*/
+	#define MRU_MTU_CTRL_TBL_MTU_CMD
+	#define MRU_MTU_CTRL_TBL_MTU_CMD_OFFSET  30
+	#define MRU_MTU_CTRL_TBL_MTU_CMD_LEN     2
+	#define MRU_MTU_CTRL_TBL_MTU_CMD_DEFAULT 0x0
+	/*[field] RX_CNT_EN*/
+	#define MRU_MTU_CTRL_TBL_RX_CNT_EN
+	#define MRU_MTU_CTRL_TBL_RX_CNT_EN_OFFSET  32
+	#define MRU_MTU_CTRL_TBL_RX_CNT_EN_LEN     1
+	#define MRU_MTU_CTRL_TBL_RX_CNT_EN_DEFAULT 0x0
+	/*[field] TX_CNT_EN*/
+	#define MRU_MTU_CTRL_TBL_TX_CNT_EN
+	#define MRU_MTU_CTRL_TBL_TX_CNT_EN_OFFSET  33
+	#define MRU_MTU_CTRL_TBL_TX_CNT_EN_LEN     1
+	#define MRU_MTU_CTRL_TBL_TX_CNT_EN_DEFAULT 0x0
+	/*[field] SRC_PROFILE*/
+	#define MRU_MTU_CTRL_TBL_SRC_PROFILE
+	#define MRU_MTU_CTRL_TBL_SRC_PROFILE_OFFSET  34
+	#define MRU_MTU_CTRL_TBL_SRC_PROFILE_LEN     2
+	#define MRU_MTU_CTRL_TBL_SRC_PROFILE_DEFAULT 0x0
+
+struct mru_mtu_ctrl_tbl {
+	a_uint32_t  mru:14;
+	a_uint32_t  mru_cmd:2;
+	a_uint32_t  mtu:14;
+	a_uint32_t  mtu_cmd:2;
+	a_uint32_t  rx_cnt_en:1;
+	a_uint32_t  tx_cnt_en:1;
+	a_uint32_t  src_profile:2;
+	a_uint32_t  _reserved0:28;
+};
+
+union mru_mtu_ctrl_tbl_u {
+	a_uint32_t val[2];
+	struct mru_mtu_ctrl_tbl bf;
+};
+
+/*[register] MC_MTU_CTRL_TBL*/
+#define MC_MTU_CTRL_TBL
+#define MC_MTU_CTRL_TBL_ADDRESS 0xa00
+#define MC_MTU_CTRL_TBL_NUM     8
+#define MC_MTU_CTRL_TBL_INC     0x4
+#define MC_MTU_CTRL_TBL_TYPE    REG_TYPE_RW
+#define MC_MTU_CTRL_TBL_DEFAULT 0x5ea
+	/*[field] MTU*/
+	#define MC_MTU_CTRL_TBL_MTU
+	#define MC_MTU_CTRL_TBL_MTU_OFFSET  0
+	#define MC_MTU_CTRL_TBL_MTU_LEN     14
+	#define MC_MTU_CTRL_TBL_MTU_DEFAULT 0x5ea
+	/*[field] MTU_CMD*/
+	#define MC_MTU_CTRL_TBL_MTU_CMD
+	#define MC_MTU_CTRL_TBL_MTU_CMD_OFFSET  14
+	#define MC_MTU_CTRL_TBL_MTU_CMD_LEN     2
+	#define MC_MTU_CTRL_TBL_MTU_CMD_DEFAULT 0x0
+	/*[field] TX_CNT_EN*/
+	#define MC_MTU_CTRL_TBL_TX_CNT_EN
+	#define MC_MTU_CTRL_TBL_TX_CNT_EN_OFFSET  16
+	#define MC_MTU_CTRL_TBL_TX_CNT_EN_LEN     1
+	#define MC_MTU_CTRL_TBL_TX_CNT_EN_DEFAULT 0x0
+
+struct mc_mtu_ctrl_tbl {
+	a_uint32_t  mtu:14;
+	a_uint32_t  mtu_cmd:2;
+	a_uint32_t  tx_cnt_en:1;
+	a_uint32_t  _reserved0:15;
+};
+
+union mc_mtu_ctrl_tbl_u {
+	a_uint32_t val;
+	struct mc_mtu_ctrl_tbl bf;
+};
+
+/*[register] TDM_CTRL*/
+#define TDM_CTRL
+#define TDM_CTRL_ADDRESS 0x0
+#define TDM_CTRL_NUM     1
+#define TDM_CTRL_INC     0x4
+#define TDM_CTRL_TYPE    REG_TYPE_RW
+#define TDM_CTRL_DEFAULT 0x80000050
+	/*[field] TDM_DEPTH*/
+	#define TDM_CTRL_TDM_DEPTH
+	#define TDM_CTRL_TDM_DEPTH_OFFSET  0
+	#define TDM_CTRL_TDM_DEPTH_LEN     8
+	#define TDM_CTRL_TDM_DEPTH_DEFAULT 0x50
+	/*[field] TDM_OFFSET*/
+	#define TDM_CTRL_TDM_OFFSET
+	#define TDM_CTRL_TDM_OFFSET_OFFSET  8
+	#define TDM_CTRL_TDM_OFFSET_LEN     7
+	#define TDM_CTRL_TDM_OFFSET_DEFAULT 0x0
+	/*[field] TDM_EN*/
+	#define TDM_CTRL_TDM_EN
+	#define TDM_CTRL_TDM_EN_OFFSET  31
+	#define TDM_CTRL_TDM_EN_LEN     1
+	#define TDM_CTRL_TDM_EN_DEFAULT 0x1
+
+struct tdm_ctrl {
+	a_uint32_t  tdm_depth:8;
+	a_uint32_t  tdm_offset:7;
+	a_uint32_t  _reserved0:16;
+	a_uint32_t  tdm_en:1;
+};
+
+union tdm_ctrl_u {
+	a_uint32_t val;
+	struct tdm_ctrl bf;
+};
+
+/*[register] RX_FIFO_CFG*/
+#define RX_FIFO_CFG
+#define RX_FIFO_CFG_ADDRESS 0x4
+#define RX_FIFO_CFG_NUM     8
+#define RX_FIFO_CFG_INC     0x4
+#define RX_FIFO_CFG_TYPE    REG_TYPE_RW
+#define RX_FIFO_CFG_DEFAULT 0x4
+	/*[field] RX_FIFO_THRES*/
+	#define RX_FIFO_CFG_RX_FIFO_THRES
+	#define RX_FIFO_CFG_RX_FIFO_THRES_OFFSET  0
+	#define RX_FIFO_CFG_RX_FIFO_THRES_LEN     3
+	#define RX_FIFO_CFG_RX_FIFO_THRES_DEFAULT 0x4
+
+struct rx_fifo_cfg {
+	a_uint32_t  rx_fifo_thres:3;
+	a_uint32_t  _reserved0:29;
+};
+
+union rx_fifo_cfg_u {
+	a_uint32_t val;
+	struct rx_fifo_cfg bf;
+};
+
+/*[table] TDM_CFG*/
+#define TDM_CFG
+#define TDM_CFG_ADDRESS 0x1000
+#define TDM_CFG_NUM     128
+#define TDM_CFG_INC     0x10
+#define TDM_CFG_TYPE    REG_TYPE_RW
+#define TDM_CFG_DEFAULT 0x0
+	/*[field] PORT_NUM*/
+	#define TDM_CFG_PORT_NUM
+	#define TDM_CFG_PORT_NUM_OFFSET  0
+	#define TDM_CFG_PORT_NUM_LEN     4
+	#define TDM_CFG_PORT_NUM_DEFAULT 0x0
+	/*[field] DIR*/
+	#define TDM_CFG_DIR
+	#define TDM_CFG_DIR_OFFSET  4
+	#define TDM_CFG_DIR_LEN     1
+	#define TDM_CFG_DIR_DEFAULT 0x0
+	/*[field] VALID*/
+	#define TDM_CFG_VALID
+	#define TDM_CFG_VALID_OFFSET  5
+	#define TDM_CFG_VALID_LEN     1
+	#define TDM_CFG_VALID_DEFAULT 0x0
+
+struct tdm_cfg {
+	a_uint32_t  port_num:4;
+	a_uint32_t  dir:1;
+	a_uint32_t  valid:1;
+	a_uint32_t  _reserved0:26;
+};
+
+union tdm_cfg_u {
+	a_uint32_t val;
+	struct tdm_cfg bf;
+};
+
+/*[table] DROP_STAT*/
+#define DROP_STAT
+#define DROP_STAT_ADDRESS 0x3000
+#define DROP_STAT_NUM     30
+#define DROP_STAT_INC     0x10
+#define DROP_STAT_TYPE    REG_TYPE_RW
+#define DROP_STAT_DEFAULT 0x0
+	/*[field] PKTS*/
+	#define DROP_STAT_PKTS
+	#define DROP_STAT_PKTS_OFFSET  0
+	#define DROP_STAT_PKTS_LEN     32
+	#define DROP_STAT_PKTS_DEFAULT 0x0
+	/*[field] BYTES*/
+	#define DROP_STAT_BYTES
+	#define DROP_STAT_BYTES_OFFSET  32
+	#define DROP_STAT_BYTES_LEN     40
+	#define DROP_STAT_BYTES_DEFAULT 0x0
+
+struct drop_stat {
+	a_uint32_t  pkts:32;
+	a_uint32_t  bytes_0:32;
+	a_uint32_t  bytes_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union drop_stat_u {
+	a_uint32_t val[3];
+	struct drop_stat bf;
+};
+
+/*[register] PORT_TX_COUNTER_TBL_REG*/
+#define PORT_TX_COUNTER_TBL_REG
+#define PORT_TX_COUNTER_TBL_REG_ADDRESS 0x900
+#define PORT_TX_COUNTER_TBL_REG_NUM     8
+#define PORT_TX_COUNTER_TBL_REG_INC     0x10
+#define PORT_TX_COUNTER_TBL_REG_TYPE    REG_TYPE_RW
+#define PORT_TX_COUNTER_TBL_REG_DEFAULT 0x0
+	/*[field] TX_PACKETS*/
+	#define PORT_TX_COUNTER_TBL_REG_TX_PACKETS
+	#define PORT_TX_COUNTER_TBL_REG_TX_PACKETS_OFFSET  0
+	#define PORT_TX_COUNTER_TBL_REG_TX_PACKETS_LEN     32
+	#define PORT_TX_COUNTER_TBL_REG_TX_PACKETS_DEFAULT 0x0
+	/*[field] TX_BYTES*/
+	#define PORT_TX_COUNTER_TBL_REG_TX_BYTES
+	#define PORT_TX_COUNTER_TBL_REG_TX_BYTES_OFFSET  32
+	#define PORT_TX_COUNTER_TBL_REG_TX_BYTES_LEN     40
+	#define PORT_TX_COUNTER_TBL_REG_TX_BYTES_DEFAULT 0x0
+
+struct port_tx_counter_tbl_reg {
+	a_uint32_t  tx_packets:32;
+	a_uint32_t  tx_bytes_0:32;
+	a_uint32_t  tx_bytes_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union port_tx_counter_tbl_reg_u {
+	a_uint32_t val[3];
+	struct port_tx_counter_tbl_reg bf;
+};
+
+/*[register] VP_TX_COUNTER_TBL_REG*/
+#define VP_TX_COUNTER_TBL_REG
+#define VP_TX_COUNTER_TBL_REG_ADDRESS 0x1000
+#define VP_TX_COUNTER_TBL_REG_NUM     256
+#define VP_TX_COUNTER_TBL_REG_INC     0x10
+#define VP_TX_COUNTER_TBL_REG_TYPE    REG_TYPE_RW
+#define VP_TX_COUNTER_TBL_REG_DEFAULT 0x0
+	/*[field] TX_PACKETS*/
+	#define VP_TX_COUNTER_TBL_REG_TX_PACKETS
+	#define VP_TX_COUNTER_TBL_REG_TX_PACKETS_OFFSET  0
+	#define VP_TX_COUNTER_TBL_REG_TX_PACKETS_LEN     32
+	#define VP_TX_COUNTER_TBL_REG_TX_PACKETS_DEFAULT 0x0
+	/*[field] TX_BYTES*/
+	#define VP_TX_COUNTER_TBL_REG_TX_BYTES
+	#define VP_TX_COUNTER_TBL_REG_TX_BYTES_OFFSET  32
+	#define VP_TX_COUNTER_TBL_REG_TX_BYTES_LEN     40
+	#define VP_TX_COUNTER_TBL_REG_TX_BYTES_DEFAULT 0x0
+
+struct vp_tx_counter_tbl_reg {
+	a_uint32_t  tx_packets:32;
+	a_uint32_t  tx_bytes_0:32;
+	a_uint32_t  tx_bytes_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union vp_tx_counter_tbl_reg_u {
+	a_uint32_t val[3];
+	struct vp_tx_counter_tbl_reg bf;
+};
+
+/*[register] EPE_DBG_IN_CNT_REG*/
+#define EPE_DBG_IN_CNT_REG
+#define EPE_DBG_IN_CNT_REG_ADDRESS 0x6054
+#define EPE_DBG_IN_CNT_REG_NUM     1
+#define EPE_DBG_IN_CNT_REG_INC     0x4
+#define EPE_DBG_IN_CNT_REG_TYPE    REG_TYPE_RW
+#define EPE_DBG_IN_CNT_REG_DEFAULT 0x0
+	/*[field] COUNTER*/
+	#define EPE_DBG_IN_CNT_REG_COUNTER
+	#define EPE_DBG_IN_CNT_REG_COUNTER_OFFSET  0
+	#define EPE_DBG_IN_CNT_REG_COUNTER_LEN     32
+	#define EPE_DBG_IN_CNT_REG_COUNTER_DEFAULT 0x0
+
+struct epe_dbg_in_cnt_reg {
+	a_uint32_t  counter:32;
+};
+
+union epe_dbg_in_cnt_reg_u {
+	a_uint32_t val;
+	struct epe_dbg_in_cnt_reg bf;
+};
+
+/*[register] EPE_DBG_OUT_CNT_REG*/
+#define EPE_DBG_OUT_CNT_REG
+#define EPE_DBG_OUT_CNT_REG_ADDRESS 0x6070
+#define EPE_DBG_OUT_CNT_REG_NUM     1
+#define EPE_DBG_OUT_CNT_REG_INC     0x4
+#define EPE_DBG_OUT_CNT_REG_TYPE    REG_TYPE_RW
+#define EPE_DBG_OUT_CNT_REG_DEFAULT 0x0
+	/*[field] COUNTER*/
+	#define EPE_DBG_OUT_CNT_REG_COUNTER
+	#define EPE_DBG_OUT_CNT_REG_COUNTER_OFFSET  0
+	#define EPE_DBG_OUT_CNT_REG_COUNTER_LEN     32
+	#define EPE_DBG_OUT_CNT_REG_COUNTER_DEFAULT 0x0
+
+struct epe_dbg_out_cnt_reg {
+	a_uint32_t  counter:32;
+};
+
+union epe_dbg_out_cnt_reg_u {
+	a_uint32_t val;
+	struct epe_dbg_out_cnt_reg bf;
+};
+
+/*[register] LPI_ENABLE*/
+#define LPI_ENABLE
+#define LPI_ENABLE_ADDRESS 0x0
+#define LPI_ENABLE_NUM     1
+#define LPI_ENABLE_INC     0x0
+#define LPI_ENABLE_TYPE    REG_TYPE_RW
+#define LPI_ENABLE_DEFAULT 0x0
+	/*[field] LPI_PORT1_EN*/
+	#define LPI_PORT1_EN
+	#define LPI_PORT1_EN_OFFSET  0
+	#define LPI_PORT1_EN_LEN     1
+	#define LPI_PORT1_EN_DEFAULT 0x0
+	/*[field] LPI_PORT2_EN*/
+	#define LPI_PORT2_EN
+	#define LPI_PORT2_EN_OFFSET  1
+	#define LPI_PORT2_EN_LEN     1
+	#define LPI_PORT2_EN_DEFAULT 0x0
+	/*[field] LPI_PORT3_EN*/
+	#define LPI_PORT3_EN
+	#define LPI_PORT3_EN_OFFSET  2
+	#define LPI_PORT3_EN_LEN     1
+	#define LPI_PORT3_EN_DEFAULT 0x0
+	/*[field] LPI_PORT4_EN*/
+	#define LPI_PORT4_EN
+	#define LPI_PORT4_EN_OFFSET  3
+	#define LPI_PORT4_EN_LEN     1
+	#define LPI_PORT4_EN_DEFAULT 0x0
+	/*[field] LPI_PORT5_EN*/
+	#define LPI_PORT5_EN
+	#define LPI_PORT5_EN_OFFSET  4
+	#define LPI_PORT5_EN_LEN     1
+	#define LPI_PORT5_EN_DEFAULT 0x0
+	/*[field] LPI_LPI_PORT6_EN*/
+	#define LPI_PORT6_EN
+	#define LPI_PORT6_EN_OFFSET  5
+	#define LPI_PORT6_EN_LEN     1
+	#define LPI_LPI_PORT6_EN_DEFAULT 0x0
+struct lpi_enable {
+	a_uint32_t  lpi_port1_en:1;
+	a_uint32_t  lpi_port2_en:1;
+	a_uint32_t  lpi_port3_en:1;
+	a_uint32_t  lpi_port4_en:1;
+	a_uint32_t  lpi_port5_en:1;
+	a_uint32_t  lpi_port6_en:1;
+	a_uint32_t  _reserved0:26;
+};
+
+union lpi_enable_u {
+	a_uint32_t val;
+	struct lpi_enable bf;
+};
+
+/*[register] LPI_PORT_TIMER*/
+#define LPI_PORT_TIMER_ENABLE
+#define LPI_PORT_TIMER_ADDRESS 0x0
+#define LPI_PORT_TIMER_NUM     6
+#define LPI_PORT_TIMER_INC     0x4
+#define LPI_PORT_TIMER_TYPE    REG_TYPE_RW
+#define LPI_PORT_TIMER_DEFAULT 0x0
+	/*[field] LPI_PORT_WAKEUP_TIMER*/
+	#define LPI_PORT_WAKEUP_TIMER
+	#define LPI_PORT_WAKEUP_TIMER_OFFSET  0
+	#define LPI_PORT_WAKEUP_TIMER_LEN     16
+	#define LPI_PORT_WAKEUP_TIMER_DEFAULT 0x0
+	/*[field] LPI_PORT_SLEEP_TIMER*/
+	#define LPI_PORT_SLEEP_TIMER
+	#define LPI_PORT_SLEEP_TIMER_OFFSET  16
+	#define LPI_PORT_SLEEP_TIMER_LEN     16
+	#define LPI_PORT_SLEEP_TIMER_DEFAULT 0x0
+
+struct lpi_port_timer {
+	a_uint32_t  lpi_port_wakeup_timer:16;
+	a_uint32_t  lpi_port_sleep_timer:16;
+};
+
+union lpi_port_timer_u {
+	a_uint32_t val;
+	struct lpi_port_timer bf;
+};
+
+/*[register] LPI_DBG_ADDR*/
+#define LPI_DBG_ADDR
+#define LPI_DBG_ADDR_ADDRESS 0x1C
+#define LPI_DBG_ADDR_NUM     1
+#define LPI_DBG_ADDR_INC     0x1
+#define LPI_DBG_ADDR_TYPE    REG_TYPE_RW
+#define LPI_DBG_ADDR_DEFAULT 0x0
+	/*[field] LPI_DBG_ADDR*/
+	#define LPI_DBG_ADDR
+	#define IIP_DBG_ADDR_OFFSET  0
+	#define LPI_DBG_ADDR_LEN     8
+	#define LPI_DBG_ADDR_DEFAULT 0x0
+
+struct lpi_dbg_addr {
+	a_uint32_t  lpi_debug_addr:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union lpi_dbg_addr_u {
+	a_uint32_t val;
+	struct lpi_dbg_addr bf;
+};
+
+/*[register] LPI_DBG_DATA*/
+#define LPI_DBG_DATA
+#define LPI_DBG_DATA_ADDRESS 0x20
+#define LPI_DBG_DATA_NUM     1
+#define LPI_DBG_DATA_INC     0x1
+#define LPI_DBG_DATA_TYPE    REG_TYPE_RW
+#define LPI_DBG_DATA_DEFAULT 0x0
+	/*[field] LPI_DBG_DATA*/
+	#define LPI_DBG_DATA
+	#define LPI_DBG_DATA_OFFSET  0
+	#define LPI_DBG_DATA_LEN     32
+	#define LPI_DBG_DATA_DEFAULT 0x0
+
+struct lpi_dbg_data {
+	a_uint32_t  lpi_debug_data:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union lpi_dbg_data_u {
+	a_uint32_t val;
+	struct lpi_dbg_data bf;
+};
+
+/*[register] LPI_CNT*/
+#define LPI_CNT
+#define LPI_CNT_ADDRESS 0x30
+#define LPI_CNT_NUM     1
+#define LPI_CNT_INC     0x1
+#define LPI_CNT_TYPE    REG_TYPE_RW
+#define LPI_CNT_DEFAULT 0x0
+	/*[field] LPI_CNT*/
+	#define LPI_CNT
+	#define LPI_CNT_OFFSET  0
+	#define LPI_CNT_LEN     9
+	#define LPI_CNT_DEFAULT 0x0
+
+struct lpi_cnt {
+	a_uint32_t  lpi_cnt_val:9;
+	a_uint32_t  _reserved0:23;
+};
+
+union lpi_cnt_u {
+	a_uint32_t val;
+	struct lpi_cnt bf;
+};
+
+/*[register] DROP_CNT*/
+#define DROP_CNT
+#define DROP_CNT_ADDRESS 0x24
+#define DROP_CNT_NUM     8
+#define DROP_CNT_INC     0x4
+#define DROP_CNT_TYPE    REG_TYPE_RW
+#define DROP_CNT_DEFAULT 0x0
+	/*[field] DROP_CNT*/
+	#define DROP_CNT_DROP_CNT
+	#define DROP_CNT_DROP_CNT_OFFSET  0
+	#define DROP_CNT_DROP_CNT_LEN     32
+	#define DROP_CNT_DROP_CNT_DEFAULT 0x0
+
+struct drop_cnt {
+	a_uint32_t  drop_cnt:32;
+};
+
+union drop_cnt_u {
+	a_uint32_t val;
+	struct drop_cnt bf;
+};
+
+/*[register] IPR_PKT_NUM_TBL_REG*/
+#define IPR_PKT_NUM_TBL_REG
+#define IPR_PKT_NUM_TBL_REG_ADDRESS 0x80
+#define IPR_PKT_NUM_TBL_REG_NUM     8
+#define IPR_PKT_NUM_TBL_REG_INC     0x4
+#define IPR_PKT_NUM_TBL_REG_TYPE    REG_TYPE_RW
+#define IPR_PKT_NUM_TBL_REG_DEFAULT 0x0
+	/*[field] PACKETS*/
+	#define IPR_PKT_NUM_TBL_REG_PACKETS
+	#define IPR_PKT_NUM_TBL_REG_PACKETS_OFFSET  0
+	#define IPR_PKT_NUM_TBL_REG_PACKETS_LEN     32
+	#define IPR_PKT_NUM_TBL_REG_PACKETS_DEFAULT 0x0
+
+struct ipr_pkt_num_tbl_reg {
+	a_uint32_t  packets:32;
+};
+
+union ipr_pkt_num_tbl_reg_u {
+	a_uint32_t val;
+	struct ipr_pkt_num_tbl_reg bf;
+};
+
+/*[register] IPR_BYTE_LOW_REG_REG*/
+#define IPR_BYTE_LOW_REG_REG
+#define IPR_BYTE_LOW_REG_REG_ADDRESS 0xa0
+#define IPR_BYTE_LOW_REG_REG_NUM     8
+#define IPR_BYTE_LOW_REG_REG_INC     0x4
+#define IPR_BYTE_LOW_REG_REG_TYPE    REG_TYPE_RW
+#define IPR_BYTE_LOW_REG_REG_DEFAULT 0x0
+	/*[field] BYTES*/
+	#define IPR_BYTE_LOW_REG_REG_BYTES
+	#define IPR_BYTE_LOW_REG_REG_BYTES_OFFSET  0
+	#define IPR_BYTE_LOW_REG_REG_BYTES_LEN     32
+	#define IPR_BYTE_LOW_REG_REG_BYTES_DEFAULT 0x0
+
+struct ipr_byte_low_reg_reg {
+	a_uint32_t  bytes:32;
+};
+
+union ipr_byte_low_reg_reg_u {
+	a_uint32_t val;
+	struct ipr_byte_low_reg_reg bf;
+};
+
+/*[register] IPR_BYTE_HIGH_REG*/
+#define IPR_BYTE_HIGH_REG
+#define IPR_BYTE_HIGH_REG_ADDRESS 0xc0
+#define IPR_BYTE_HIGH_REG_NUM     8
+#define IPR_BYTE_HIGH_REG_INC     0x4
+#define IPR_BYTE_HIGH_REG_TYPE    REG_TYPE_RW
+#define IPR_BYTE_HIGH_REG_DEFAULT 0x0
+	/*[field] BYTES*/
+	#define IPR_BYTE_HIGH_REG_BYTES
+	#define IPR_BYTE_HIGH_REG_BYTES_OFFSET  0
+	#define IPR_BYTE_HIGH_REG_BYTES_LEN     32
+	#define IPR_BYTE_HIGH_REG_BYTES_DEFAULT 0x0
+
+struct ipr_byte_high_reg {
+	a_uint32_t  bytes:32;
+};
+
+union ipr_byte_high_reg_u {
+	a_uint32_t val;
+	struct ipr_byte_high_reg bf;
+};
+
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_portvlan.h b/qca-ssdk/include/hsl/hppe/hppe_portvlan.h
new file mode 100755
index 0000000..2a4a779
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_portvlan.h
@@ -0,0 +1,1627 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_PORTVLAN_H_
+#define _HPPE_PORTVLAN_H_
+
+#include "hppe_portvlan_reg.h"
+
+#define XLT_RULE_TBL_MAX_ENTRY	64
+#define XLT_ACTION_TBL_MAX_ENTRY	64
+#define PORT_PARSING_REG_MAX_ENTRY	8
+#define EG_VLAN_XLT_RULE_MAX_ENTRY	64
+#define PORT_EG_DEF_VID_MAX_ENTRY	8
+#define PORT_EG_VLAN_MAX_ENTRY	8
+#define EG_VLAN_XLT_ACTION_MAX_ENTRY	64
+
+
+sw_error_t
+hppe_port_parsing_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_parsing_reg_u *value);
+
+sw_error_t
+hppe_port_parsing_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_parsing_reg_u *value);
+
+sw_error_t
+hppe_edma_vlan_tpid_reg_get(
+		a_uint32_t dev_id,
+		union edma_vlan_tpid_reg_u *value);
+
+sw_error_t
+hppe_edma_vlan_tpid_reg_set(
+		a_uint32_t dev_id,
+		union edma_vlan_tpid_reg_u *value);
+
+sw_error_t
+hppe_vlan_tpid_reg_get(
+		a_uint32_t dev_id,
+		union vlan_tpid_reg_u *value);
+
+sw_error_t
+hppe_vlan_tpid_reg_set(
+		a_uint32_t dev_id,
+		union vlan_tpid_reg_u *value);
+
+sw_error_t
+hppe_port_parsing_reg_port_role_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_parsing_reg_port_role_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vlan_tpid_reg_stag_tpid_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_vlan_tpid_reg_stag_tpid_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_vlan_tpid_reg_ctag_tpid_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_vlan_tpid_reg_ctag_tpid_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_bridge_config_get(
+		a_uint32_t dev_id,
+		union bridge_config_u *value);
+
+sw_error_t
+hppe_bridge_config_set(
+		a_uint32_t dev_id,
+		union bridge_config_u *value);
+
+sw_error_t
+hppe_port_def_vid_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		union port_def_vid_u *value);
+
+sw_error_t
+hppe_port_def_vid_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		union port_def_vid_u *value);
+
+sw_error_t
+hppe_port_def_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		union port_def_pcp_u *value);
+
+sw_error_t
+hppe_port_def_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		union port_def_pcp_u *value);
+
+sw_error_t
+hppe_port_vlan_config_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		union port_vlan_config_u *value);
+
+sw_error_t
+hppe_port_vlan_config_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		union port_vlan_config_u *value);
+
+sw_error_t
+hppe_iv_dbg_addr_get(
+		a_uint32_t dev_id,
+		union iv_dbg_addr_u *value);
+
+sw_error_t
+hppe_iv_dbg_addr_set(
+		a_uint32_t dev_id,
+		union iv_dbg_addr_u *value);
+
+sw_error_t
+hppe_iv_dbg_data_get(
+		a_uint32_t dev_id,
+		union iv_dbg_data_u *value);
+
+sw_error_t
+hppe_iv_dbg_data_set(
+		a_uint32_t dev_id,
+		union iv_dbg_data_u *value);
+
+sw_error_t
+hppe_eco_reserve_get(
+		a_uint32_t dev_id,
+		union eco_reserve_u *value);
+
+sw_error_t
+hppe_eco_reserve_set(
+		a_uint32_t dev_id,
+		union eco_reserve_u *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union xlt_rule_tbl_u *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union xlt_rule_tbl_u *value);
+
+sw_error_t
+hppe_xlt_action_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union xlt_action_tbl_u *value);
+
+sw_error_t
+hppe_xlt_action_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union xlt_action_tbl_u *value);
+
+sw_error_t
+hppe_bridge_config_bridge_type_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_bridge_config_bridge_type_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_def_vid_port_def_cvid_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_def_vid_port_def_cvid_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_def_vid_port_def_svid_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_def_vid_port_def_svid_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_def_vid_port_def_cvid_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_def_vid_port_def_cvid_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_def_vid_port_def_svid_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_def_vid_port_def_svid_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_def_pcp_port_def_sdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_def_pcp_port_def_sdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_def_pcp_port_def_spcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_def_pcp_port_def_spcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_def_pcp_port_def_cdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_def_pcp_port_def_cdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_def_pcp_port_def_cpcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_def_pcp_port_def_cpcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_vlan_config_port_in_dei_prop_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_vlan_config_port_in_dei_prop_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_vlan_config_port_in_pcp_prop_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_vlan_config_port_in_pcp_prop_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_vlan_config_port_untag_fltr_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_vlan_config_port_untag_fltr_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_vlan_config_port_in_vlan_fltr_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_vlan_config_port_in_vlan_fltr_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_vlan_config_port_pri_tag_fltr_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_vlan_config_port_pri_tag_fltr_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_vlan_config_port_vlan_xlt_miss_fwd_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_vlan_config_port_vlan_xlt_miss_fwd_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int value);
+
+sw_error_t
+hppe_port_vlan_config_port_tag_fltr_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_port_vlan_config_port_tag_fltr_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		unsigned int value);
+
+sw_error_t
+hppe_iv_dbg_addr_dbg_addr_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_iv_dbg_addr_dbg_addr_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_iv_dbg_data_dbg_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_iv_dbg_data_dbg_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_eco_reserve_eco_res_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_eco_reserve_eco_res_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_vid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_vid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_frm_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_frm_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_prot_value_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_prot_value_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_frm_type_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_frm_type_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_vid_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_vid_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_dei_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_dei_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_port_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_port_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_prot_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_prot_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_pcp_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_pcp_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_vid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_vid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_pcp_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_pcp_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_dei_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_dei_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_vid_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_vid_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_dei_swap_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_dei_swap_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cvid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cvid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cpcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cpcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_spcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_spcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_sdei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_sdei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cvid_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cvid_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_vsi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_vsi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_spcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_spcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_counter_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_counter_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_vid_swap_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_vid_swap_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_sdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_sdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_counter_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_counter_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_svid_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_svid_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_svid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_svid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_vsi_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_vsi_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cpcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cpcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cdei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cdei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_pcp_swap_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_pcp_swap_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vlan_xlt_rule_u *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vlan_xlt_rule_u *value);
+
+sw_error_t
+hppe_eg_vsi_tag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vsi_tag_u *value);
+
+sw_error_t
+hppe_eg_vsi_tag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vsi_tag_u *value);
+
+sw_error_t
+hppe_port_eg_def_vid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_eg_def_vid_u *value);
+
+sw_error_t
+hppe_port_eg_def_vid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_eg_def_vid_u *value);
+
+sw_error_t
+hppe_port_eg_vlan_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_eg_vlan_u *value);
+
+sw_error_t
+hppe_port_eg_vlan_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_eg_vlan_u *value);
+
+sw_error_t
+hppe_eg_vlan_tpid_get(
+		a_uint32_t dev_id,
+		union eg_vlan_tpid_u *value);
+
+sw_error_t
+hppe_eg_vlan_tpid_set(
+		a_uint32_t dev_id,
+		union eg_vlan_tpid_u *value);
+
+sw_error_t
+hppe_eg_bridge_config_get(
+		a_uint32_t dev_id,
+		union eg_bridge_config_u *value);
+
+sw_error_t
+hppe_eg_bridge_config_set(
+		a_uint32_t dev_id,
+		union eg_bridge_config_u *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vlan_xlt_action_u *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vlan_xlt_action_u *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_vid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_vid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_vsi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_vsi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_vid_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_vid_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_dei_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_dei_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_vsi_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_vsi_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_port_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_port_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_pcp_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_pcp_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_vid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_vid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_pcp_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_pcp_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_vid_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_vid_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_dei_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_dei_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_vsi_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_vsi_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vsi_tag_tagged_mode_port_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vsi_tag_tagged_mode_port_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_svid_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_svid_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_svid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_svid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_cvid_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_cvid_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_cvid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_cvid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_eg_vlan_tx_counting_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_eg_vlan_tx_counting_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_vlan_ctag_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_vlan_ctag_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_pcp_prop_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_pcp_prop_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_eg_vlan_vsi_tag_mode_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_eg_vlan_vsi_tag_mode_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_vlan_stag_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_vlan_stag_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_dei_prop_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_dei_prop_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_eg_vlan_port_vlan_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_eg_vlan_port_vlan_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_tpid_ctpid_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_eg_vlan_tpid_ctpid_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_eg_vlan_tpid_stpid_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_eg_vlan_tpid_stpid_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_eg_bridge_config_bridge_type_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_eg_bridge_config_bridge_type_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_eg_bridge_config_pkt_l2_edit_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value);
+sw_error_t
+hppe_eg_bridge_config_pkt_l2_edit_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value);
+sw_error_t
+hppe_eg_bridge_config_queue_cnt_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_eg_bridge_config_queue_cnt_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_dei_swap_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_dei_swap_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cvid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cvid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cpcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cpcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_spcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_spcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_sdei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_sdei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cvid_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cvid_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_spcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_spcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_counter_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_counter_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_vid_swap_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_vid_swap_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_sdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_sdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_counter_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_counter_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_svid_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_svid_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_svid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_svid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cpcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cpcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cdei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cdei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_pcp_swap_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_pcp_swap_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vlan_dev_tx_counter_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vlan_dev_tx_counter_tbl_u *value);
+
+sw_error_t
+hppe_vlan_dev_tx_counter_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vlan_dev_tx_counter_tbl_u *value);
+
+sw_error_t
+hppe_vlan_dev_tx_counter_tbl_tx_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_vlan_dev_tx_counter_tbl_tx_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_vlan_dev_tx_counter_tbl_tx_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vlan_dev_tx_counter_tbl_tx_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_portvlan_reg.h b/qca-ssdk/include/hsl/hppe/hppe_portvlan_reg.h
new file mode 100755
index 0000000..1a79643
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_portvlan_reg.h
@@ -0,0 +1,1073 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_PORTVLAN_REG_H
+#define HPPE_PORTVLAN_REG_H
+
+/*[register] PORT_PARSING_REG*/
+#define PORT_PARSING_REG
+#define PORT_PARSING_REG_ADDRESS 0x0
+#define PORT_PARSING_REG_NUM     8
+#define PORT_PARSING_REG_INC     0x4
+#define PORT_PARSING_REG_TYPE    REG_TYPE_RW
+#define PORT_PARSING_REG_DEFAULT 0x0
+	/*[field] PORT_ROLE*/
+	#define PORT_PARSING_REG_PORT_ROLE
+	#define PORT_PARSING_REG_PORT_ROLE_OFFSET  0
+	#define PORT_PARSING_REG_PORT_ROLE_LEN     1
+	#define PORT_PARSING_REG_PORT_ROLE_DEFAULT 0x0
+
+struct port_parsing_reg {
+	a_uint32_t  port_role:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union port_parsing_reg_u {
+	a_uint32_t val;
+	struct port_parsing_reg bf;
+};
+
+/*[register] EDMA_VLAN_TPID_REG*/
+#define EDMA_VLAN_TPID_REG
+#define EDMA_VLAN_TPID_REG_ADDRESS 0x8
+#define EDMA_VLAN_TPID_REG_NUM     1
+#define EDMA_VLAN_TPID_REG_INC     0x4
+#define EDMA_VLAN_TPID_REG_TYPE    REG_TYPE_RW
+#define EDMA_VLAN_TPID_REG_DEFAULT 0x810088a8
+	/*[field] STAG_TPID*/
+	#define EDMA_VLAN_TPID_REG_STAG_TPID
+	#define EDMA_VLAN_TPID_REG_STAG_TPID_OFFSET  0
+	#define EDMA_VLAN_TPID_REG_STAG_TPID_LEN     16
+	#define EDMA_VLAN_TPID_REG_STAG_TPID_DEFAULT 0x88a8
+	/*[field] CTAG_TPID*/
+	#define EDMA_VLAN_TPID_REG_CTAG_TPID
+	#define EDMA_VLAN_TPID_REG_CTAG_TPID_OFFSET  16
+	#define EDMA_VLAN_TPID_REG_CTAG_TPID_LEN     16
+	#define EDMA_VLAN_TPID_REG_CTAG_TPID_DEFAULT 0x8100
+
+struct edma_vlan_tpid_reg {
+	a_uint32_t  stag_tpid:16;
+	a_uint32_t  ctag_tpid:16;
+};
+
+union edma_vlan_tpid_reg_u {
+	a_uint32_t val;
+	struct edma_vlan_tpid_reg bf;
+};
+
+/*[register] VLAN_TPID_REG*/
+#define VLAN_TPID_REG
+#define VLAN_TPID_REG_ADDRESS 0x20
+#define VLAN_TPID_REG_NUM     1
+#define VLAN_TPID_REG_INC     0x4
+#define VLAN_TPID_REG_TYPE    REG_TYPE_RW
+#define VLAN_TPID_REG_DEFAULT 0x88a88100
+	/*[field] CTAG_TPID*/
+	#define VLAN_TPID_REG_CTAG_TPID
+	#define VLAN_TPID_REG_CTAG_TPID_OFFSET  0
+	#define VLAN_TPID_REG_CTAG_TPID_LEN     16
+	#define VLAN_TPID_REG_CTAG_TPID_DEFAULT 0x8100
+	/*[field] STAG_TPID*/
+	#define VLAN_TPID_REG_STAG_TPID
+	#define VLAN_TPID_REG_STAG_TPID_OFFSET  16
+	#define VLAN_TPID_REG_STAG_TPID_LEN     16
+	#define VLAN_TPID_REG_STAG_TPID_DEFAULT 0x88a8
+
+struct vlan_tpid_reg {
+	a_uint32_t  ctag_tpid:16;
+	a_uint32_t  stag_tpid:16;
+};
+
+union vlan_tpid_reg_u {
+	a_uint32_t val;
+	struct vlan_tpid_reg bf;
+};
+
+/*[register] BRIDGE_CONFIG*/
+#define BRIDGE_CONFIG
+#define BRIDGE_CONFIG_ADDRESS 0x0
+#define BRIDGE_CONFIG_NUM     1
+#define BRIDGE_CONFIG_INC     0x4
+#define BRIDGE_CONFIG_TYPE    REG_TYPE_RW
+#define BRIDGE_CONFIG_DEFAULT 0x0
+	/*[field] BRIDGE_TYPE*/
+	#define BRIDGE_CONFIG_BRIDGE_TYPE
+	#define BRIDGE_CONFIG_BRIDGE_TYPE_OFFSET  0
+	#define BRIDGE_CONFIG_BRIDGE_TYPE_LEN     1
+	#define BRIDGE_CONFIG_BRIDGE_TYPE_DEFAULT 0x0
+
+struct bridge_config {
+	a_uint32_t  bridge_type:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union bridge_config_u {
+	a_uint32_t val;
+	struct bridge_config bf;
+};
+
+/*[register] PORT_DEF_VID*/
+#define PORT_DEF_VID
+#define PORT_DEF_VID_ADDRESS 0x10
+#define PORT_DEF_VID_NUM     1
+#define PORT_DEF_VID_INC     0x4
+#define PORT_DEF_VID_TYPE    REG_TYPE_RW
+#define PORT_DEF_VID_DEFAULT 0x0
+	/*[field] PORT_DEF_SVID*/
+	#define PORT_DEF_VID_PORT_DEF_SVID
+	#define PORT_DEF_VID_PORT_DEF_SVID_OFFSET  0
+	#define PORT_DEF_VID_PORT_DEF_SVID_LEN     12
+	#define PORT_DEF_VID_PORT_DEF_SVID_DEFAULT 0x0
+	/*[field] PORT_DEF_SVID_EN*/
+	#define PORT_DEF_VID_PORT_DEF_SVID_EN
+	#define PORT_DEF_VID_PORT_DEF_SVID_EN_OFFSET  12
+	#define PORT_DEF_VID_PORT_DEF_SVID_EN_LEN     1
+	#define PORT_DEF_VID_PORT_DEF_SVID_EN_DEFAULT 0x0
+	/*[field] PORT_DEF_CVID*/
+	#define PORT_DEF_VID_PORT_DEF_CVID
+	#define PORT_DEF_VID_PORT_DEF_CVID_OFFSET  16
+	#define PORT_DEF_VID_PORT_DEF_CVID_LEN     12
+	#define PORT_DEF_VID_PORT_DEF_CVID_DEFAULT 0x0
+	/*[field] PORT_DEF_CVID_EN*/
+	#define PORT_DEF_VID_PORT_DEF_CVID_EN
+	#define PORT_DEF_VID_PORT_DEF_CVID_EN_OFFSET  28
+	#define PORT_DEF_VID_PORT_DEF_CVID_EN_LEN     1
+	#define PORT_DEF_VID_PORT_DEF_CVID_EN_DEFAULT 0x0
+
+struct port_def_vid {
+	a_uint32_t  port_def_svid:12;
+	a_uint32_t  port_def_svid_en:1;
+	a_uint32_t  _reserved0:3;
+	a_uint32_t  port_def_cvid:12;
+	a_uint32_t  port_def_cvid_en:1;
+	a_uint32_t  _reserved1:3;
+};
+
+union port_def_vid_u {
+	a_uint32_t val;
+	struct port_def_vid bf;
+};
+
+/*[register] PORT_DEF_PCP*/
+#define PORT_DEF_PCP
+#define PORT_DEF_PCP_ADDRESS 0x30
+#define PORT_DEF_PCP_NUM     1
+#define PORT_DEF_PCP_INC     0x4
+#define PORT_DEF_PCP_TYPE    REG_TYPE_RW
+#define PORT_DEF_PCP_DEFAULT 0x0
+	/*[field] PORT_DEF_SPCP*/
+	#define PORT_DEF_PCP_PORT_DEF_SPCP
+	#define PORT_DEF_PCP_PORT_DEF_SPCP_OFFSET  0
+	#define PORT_DEF_PCP_PORT_DEF_SPCP_LEN     3
+	#define PORT_DEF_PCP_PORT_DEF_SPCP_DEFAULT 0x0
+	/*[field] PORT_DEF_SDEI*/
+	#define PORT_DEF_PCP_PORT_DEF_SDEI
+	#define PORT_DEF_PCP_PORT_DEF_SDEI_OFFSET  3
+	#define PORT_DEF_PCP_PORT_DEF_SDEI_LEN     1
+	#define PORT_DEF_PCP_PORT_DEF_SDEI_DEFAULT 0x0
+	/*[field] PORT_DEF_CPCP*/
+	#define PORT_DEF_PCP_PORT_DEF_CPCP
+	#define PORT_DEF_PCP_PORT_DEF_CPCP_OFFSET  4
+	#define PORT_DEF_PCP_PORT_DEF_CPCP_LEN     3
+	#define PORT_DEF_PCP_PORT_DEF_CPCP_DEFAULT 0x0
+	/*[field] PORT_DEF_CDEI*/
+	#define PORT_DEF_PCP_PORT_DEF_CDEI
+	#define PORT_DEF_PCP_PORT_DEF_CDEI_OFFSET  7
+	#define PORT_DEF_PCP_PORT_DEF_CDEI_LEN     1
+	#define PORT_DEF_PCP_PORT_DEF_CDEI_DEFAULT 0x0
+
+struct port_def_pcp {
+	a_uint32_t  port_def_spcp:3;
+	a_uint32_t  port_def_sdei:1;
+	a_uint32_t  port_def_cpcp:3;
+	a_uint32_t  port_def_cdei:1;
+	a_uint32_t  _reserved0:24;
+};
+
+union port_def_pcp_u {
+	a_uint32_t val;
+	struct port_def_pcp bf;
+};
+
+/*[register] PORT_VLAN_CONFIG*/
+#define PORT_VLAN_CONFIG
+#define PORT_VLAN_CONFIG_ADDRESS 0x50
+#define PORT_VLAN_CONFIG_NUM     1
+#define PORT_VLAN_CONFIG_INC     0x4
+#define PORT_VLAN_CONFIG_TYPE    REG_TYPE_RW
+#define PORT_VLAN_CONFIG_DEFAULT 0x0
+	/*[field] PORT_IN_PCP_PROP_CMD*/
+	#define PORT_VLAN_CONFIG_PORT_IN_PCP_PROP_CMD
+	#define PORT_VLAN_CONFIG_PORT_IN_PCP_PROP_CMD_OFFSET  0
+	#define PORT_VLAN_CONFIG_PORT_IN_PCP_PROP_CMD_LEN     1
+	#define PORT_VLAN_CONFIG_PORT_IN_PCP_PROP_CMD_DEFAULT 0x0
+	/*[field] PORT_IN_DEI_PROP_CMD*/
+	#define PORT_VLAN_CONFIG_PORT_IN_DEI_PROP_CMD
+	#define PORT_VLAN_CONFIG_PORT_IN_DEI_PROP_CMD_OFFSET  1
+	#define PORT_VLAN_CONFIG_PORT_IN_DEI_PROP_CMD_LEN     1
+	#define PORT_VLAN_CONFIG_PORT_IN_DEI_PROP_CMD_DEFAULT 0x0
+	/*[field] PORT_UNTAG_FLTR_CMD*/
+	#define PORT_VLAN_CONFIG_PORT_UNTAG_FLTR_CMD
+	#define PORT_VLAN_CONFIG_PORT_UNTAG_FLTR_CMD_OFFSET  2
+	#define PORT_VLAN_CONFIG_PORT_UNTAG_FLTR_CMD_LEN     1
+	#define PORT_VLAN_CONFIG_PORT_UNTAG_FLTR_CMD_DEFAULT 0x0
+	/*[field] PORT_PRI_TAG_FLTR_CMD*/
+	#define PORT_VLAN_CONFIG_PORT_PRI_TAG_FLTR_CMD
+	#define PORT_VLAN_CONFIG_PORT_PRI_TAG_FLTR_CMD_OFFSET  3
+	#define PORT_VLAN_CONFIG_PORT_PRI_TAG_FLTR_CMD_LEN     1
+	#define PORT_VLAN_CONFIG_PORT_PRI_TAG_FLTR_CMD_DEFAULT 0x0
+	/*[field] PORT_TAG_FLTR_CMD*/
+	#define PORT_VLAN_CONFIG_PORT_TAG_FLTR_CMD
+	#define PORT_VLAN_CONFIG_PORT_TAG_FLTR_CMD_OFFSET  4
+	#define PORT_VLAN_CONFIG_PORT_TAG_FLTR_CMD_LEN     1
+	#define PORT_VLAN_CONFIG_PORT_TAG_FLTR_CMD_DEFAULT 0x0
+	/*[field] PORT_VLAN_XLT_MISS_FWD_CMD*/
+	#define PORT_VLAN_CONFIG_PORT_VLAN_XLT_MISS_FWD_CMD
+	#define PORT_VLAN_CONFIG_PORT_VLAN_XLT_MISS_FWD_CMD_OFFSET  5
+	#define PORT_VLAN_CONFIG_PORT_VLAN_XLT_MISS_FWD_CMD_LEN     2
+	#define PORT_VLAN_CONFIG_PORT_VLAN_XLT_MISS_FWD_CMD_DEFAULT 0x0
+	/*[field] PORT_IN_VLAN_FLTR_CMD*/
+	#define PORT_VLAN_CONFIG_PORT_IN_VLAN_FLTR_CMD
+	#define PORT_VLAN_CONFIG_PORT_IN_VLAN_FLTR_CMD_OFFSET  7
+	#define PORT_VLAN_CONFIG_PORT_IN_VLAN_FLTR_CMD_LEN     1
+	#define PORT_VLAN_CONFIG_PORT_IN_VLAN_FLTR_CMD_DEFAULT 0x0
+
+struct port_vlan_config {
+	a_uint32_t  port_in_pcp_prop_cmd:1;
+	a_uint32_t  port_in_dei_prop_cmd:1;
+	a_uint32_t  port_untag_fltr_cmd:1;
+	a_uint32_t  port_pri_tag_fltr_cmd:1;
+	a_uint32_t  port_tag_fltr_cmd:1;
+	a_uint32_t  port_vlan_xlt_miss_fwd_cmd:2;
+	a_uint32_t  port_in_vlan_fltr_cmd:1;
+	a_uint32_t  _reserved0:24;
+};
+
+union port_vlan_config_u {
+	a_uint32_t val;
+	struct port_vlan_config bf;
+};
+
+/*[register] IV_DBG_ADDR*/
+#define IV_DBG_ADDR
+#define IV_DBG_ADDR_ADDRESS 0x70
+#define IV_DBG_ADDR_NUM     1
+#define IV_DBG_ADDR_INC     0x4
+#define IV_DBG_ADDR_TYPE    REG_TYPE_RW
+#define IV_DBG_ADDR_DEFAULT 0x0
+	/*[field] DBG_ADDR*/
+	#define IV_DBG_ADDR_DBG_ADDR
+	#define IV_DBG_ADDR_DBG_ADDR_OFFSET  0
+	#define IV_DBG_ADDR_DBG_ADDR_LEN     8
+	#define IV_DBG_ADDR_DBG_ADDR_DEFAULT 0x0
+
+struct iv_dbg_addr {
+	a_uint32_t  dbg_addr:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union iv_dbg_addr_u {
+	a_uint32_t val;
+	struct iv_dbg_addr bf;
+};
+
+/*[register] IV_DBG_DATA*/
+#define IV_DBG_DATA
+#define IV_DBG_DATA_ADDRESS 0x74
+#define IV_DBG_DATA_NUM     1
+#define IV_DBG_DATA_INC     0x4
+#define IV_DBG_DATA_TYPE    REG_TYPE_RO
+#define IV_DBG_DATA_DEFAULT 0x0
+	/*[field] DBG_DATA*/
+	#define IV_DBG_DATA_DBG_DATA
+	#define IV_DBG_DATA_DBG_DATA_OFFSET  0
+	#define IV_DBG_DATA_DBG_DATA_LEN     32
+	#define IV_DBG_DATA_DBG_DATA_DEFAULT 0x0
+
+struct iv_dbg_data {
+	a_uint32_t  dbg_data:32;
+};
+
+union iv_dbg_data_u {
+	a_uint32_t val;
+	struct iv_dbg_data bf;
+};
+
+/*[register] ECO_RESERVE*/
+#define ECO_RESERVE
+#define ECO_RESERVE_ADDRESS 0x78
+#define ECO_RESERVE_NUM     1
+#define ECO_RESERVE_INC     0x4
+#define ECO_RESERVE_TYPE    REG_TYPE_RW
+#define ECO_RESERVE_DEFAULT 0x0
+	/*[field] ECO_RES*/
+	#define ECO_RESERVE_ECO_RES
+	#define ECO_RESERVE_ECO_RES_OFFSET  0
+	#define ECO_RESERVE_ECO_RES_LEN     32
+	#define ECO_RESERVE_ECO_RES_DEFAULT 0x0
+
+struct eco_reserve {
+	a_uint32_t  eco_res:32;
+};
+
+union eco_reserve_u {
+	a_uint32_t val;
+	struct eco_reserve bf;
+};
+
+/*[table] XLT_RULE_TBL*/
+#define XLT_RULE_TBL
+#define XLT_RULE_TBL_ADDRESS 0x2000
+#define XLT_RULE_TBL_NUM     64
+#define XLT_RULE_TBL_INC     0x10
+#define XLT_RULE_TBL_TYPE    REG_TYPE_RW
+#define XLT_RULE_TBL_DEFAULT 0x0
+	/*[field] VALID*/
+	#define XLT_RULE_TBL_VALID
+	#define XLT_RULE_TBL_VALID_OFFSET  0
+	#define XLT_RULE_TBL_VALID_LEN     1
+	#define XLT_RULE_TBL_VALID_DEFAULT 0x0
+	/*[field] PORT_BITMAP*/
+	#define XLT_RULE_TBL_PORT_BITMAP
+	#define XLT_RULE_TBL_PORT_BITMAP_OFFSET  1
+	#define XLT_RULE_TBL_PORT_BITMAP_LEN     8
+	#define XLT_RULE_TBL_PORT_BITMAP_DEFAULT 0x0
+	/*[field] SKEY_FMT*/
+	#define XLT_RULE_TBL_SKEY_FMT
+	#define XLT_RULE_TBL_SKEY_FMT_OFFSET  9
+	#define XLT_RULE_TBL_SKEY_FMT_LEN     3
+	#define XLT_RULE_TBL_SKEY_FMT_DEFAULT 0x0
+	/*[field] SKEY_VID_INCL*/
+	#define XLT_RULE_TBL_SKEY_VID_INCL
+	#define XLT_RULE_TBL_SKEY_VID_INCL_OFFSET  12
+	#define XLT_RULE_TBL_SKEY_VID_INCL_LEN     1
+	#define XLT_RULE_TBL_SKEY_VID_INCL_DEFAULT 0x0
+	/*[field] SKEY_VID*/
+	#define XLT_RULE_TBL_SKEY_VID
+	#define XLT_RULE_TBL_SKEY_VID_OFFSET  13
+	#define XLT_RULE_TBL_SKEY_VID_LEN     12
+	#define XLT_RULE_TBL_SKEY_VID_DEFAULT 0x0
+	/*[field] SKEY_PCP_INCL*/
+	#define XLT_RULE_TBL_SKEY_PCP_INCL
+	#define XLT_RULE_TBL_SKEY_PCP_INCL_OFFSET  25
+	#define XLT_RULE_TBL_SKEY_PCP_INCL_LEN     1
+	#define XLT_RULE_TBL_SKEY_PCP_INCL_DEFAULT 0x0
+	/*[field] SKEY_PCP*/
+	#define XLT_RULE_TBL_SKEY_PCP
+	#define XLT_RULE_TBL_SKEY_PCP_OFFSET  26
+	#define XLT_RULE_TBL_SKEY_PCP_LEN     3
+	#define XLT_RULE_TBL_SKEY_PCP_DEFAULT 0x0
+	/*[field] SKEY_DEI_INCL*/
+	#define XLT_RULE_TBL_SKEY_DEI_INCL
+	#define XLT_RULE_TBL_SKEY_DEI_INCL_OFFSET  29
+	#define XLT_RULE_TBL_SKEY_DEI_INCL_LEN     1
+	#define XLT_RULE_TBL_SKEY_DEI_INCL_DEFAULT 0x0
+	/*[field] SKEY_DEI*/
+	#define XLT_RULE_TBL_SKEY_DEI
+	#define XLT_RULE_TBL_SKEY_DEI_OFFSET  30
+	#define XLT_RULE_TBL_SKEY_DEI_LEN     1
+	#define XLT_RULE_TBL_SKEY_DEI_DEFAULT 0x0
+	/*[field] CKEY_FMT*/
+	#define XLT_RULE_TBL_CKEY_FMT
+	#define XLT_RULE_TBL_CKEY_FMT_OFFSET  31
+	#define XLT_RULE_TBL_CKEY_FMT_LEN     3
+	#define XLT_RULE_TBL_CKEY_FMT_DEFAULT 0x0
+	/*[field] CKEY_VID_INCL*/
+	#define XLT_RULE_TBL_CKEY_VID_INCL
+	#define XLT_RULE_TBL_CKEY_VID_INCL_OFFSET  34
+	#define XLT_RULE_TBL_CKEY_VID_INCL_LEN     1
+	#define XLT_RULE_TBL_CKEY_VID_INCL_DEFAULT 0x0
+	/*[field] CKEY_VID*/
+	#define XLT_RULE_TBL_CKEY_VID
+	#define XLT_RULE_TBL_CKEY_VID_OFFSET  35
+	#define XLT_RULE_TBL_CKEY_VID_LEN     12
+	#define XLT_RULE_TBL_CKEY_VID_DEFAULT 0x0
+	/*[field] CKEY_PCP_INCL*/
+	#define XLT_RULE_TBL_CKEY_PCP_INCL
+	#define XLT_RULE_TBL_CKEY_PCP_INCL_OFFSET  47
+	#define XLT_RULE_TBL_CKEY_PCP_INCL_LEN     1
+	#define XLT_RULE_TBL_CKEY_PCP_INCL_DEFAULT 0x0
+	/*[field] CKEY_PCP*/
+	#define XLT_RULE_TBL_CKEY_PCP
+	#define XLT_RULE_TBL_CKEY_PCP_OFFSET  48
+	#define XLT_RULE_TBL_CKEY_PCP_LEN     3
+	#define XLT_RULE_TBL_CKEY_PCP_DEFAULT 0x0
+	/*[field] CKEY_DEI_INCL*/
+	#define XLT_RULE_TBL_CKEY_DEI_INCL
+	#define XLT_RULE_TBL_CKEY_DEI_INCL_OFFSET  51
+	#define XLT_RULE_TBL_CKEY_DEI_INCL_LEN     1
+	#define XLT_RULE_TBL_CKEY_DEI_INCL_DEFAULT 0x0
+	/*[field] CKEY_DEI*/
+	#define XLT_RULE_TBL_CKEY_DEI
+	#define XLT_RULE_TBL_CKEY_DEI_OFFSET  52
+	#define XLT_RULE_TBL_CKEY_DEI_LEN     1
+	#define XLT_RULE_TBL_CKEY_DEI_DEFAULT 0x0
+	/*[field] FRM_TYPE_INCL*/
+	#define XLT_RULE_TBL_FRM_TYPE_INCL
+	#define XLT_RULE_TBL_FRM_TYPE_INCL_OFFSET  53
+	#define XLT_RULE_TBL_FRM_TYPE_INCL_LEN     1
+	#define XLT_RULE_TBL_FRM_TYPE_INCL_DEFAULT 0x0
+	/*[field] FRM_TYPE*/
+	#define XLT_RULE_TBL_FRM_TYPE
+	#define XLT_RULE_TBL_FRM_TYPE_OFFSET  54
+	#define XLT_RULE_TBL_FRM_TYPE_LEN     2
+	#define XLT_RULE_TBL_FRM_TYPE_DEFAULT 0x0
+	/*[field] PROT_INCL*/
+	#define XLT_RULE_TBL_PROT_INCL
+	#define XLT_RULE_TBL_PROT_INCL_OFFSET  56
+	#define XLT_RULE_TBL_PROT_INCL_LEN     1
+	#define XLT_RULE_TBL_PROT_INCL_DEFAULT 0x0
+	/*[field] PROT_VALUE*/
+	#define XLT_RULE_TBL_PROT_VALUE
+	#define XLT_RULE_TBL_PROT_VALUE_OFFSET  57
+	#define XLT_RULE_TBL_PROT_VALUE_LEN     16
+	#define XLT_RULE_TBL_PROT_VALUE_DEFAULT 0x0
+
+struct xlt_rule_tbl {
+	a_uint32_t  valid:1;
+	a_uint32_t  port_bitmap:8;
+	a_uint32_t  skey_fmt:3;
+	a_uint32_t  skey_vid_incl:1;
+	a_uint32_t  skey_vid:12;
+	a_uint32_t  skey_pcp_incl:1;
+	a_uint32_t  skey_pcp:3;
+	a_uint32_t  skey_dei_incl:1;
+	a_uint32_t  skey_dei:1;
+	a_uint32_t  ckey_fmt_0:1;
+	a_uint32_t  ckey_fmt_1:2;
+	a_uint32_t  ckey_vid_incl:1;
+	a_uint32_t  ckey_vid:12;
+	a_uint32_t  ckey_pcp_incl:1;
+	a_uint32_t  ckey_pcp:3;
+	a_uint32_t  ckey_dei_incl:1;
+	a_uint32_t  ckey_dei:1;
+	a_uint32_t  frm_type_incl:1;
+	a_uint32_t  frm_type:2;
+	a_uint32_t  prot_incl:1;
+	a_uint32_t  prot_value_0:7;
+	a_uint32_t  prot_value_1:9;
+	a_uint32_t  _reserved0:23;
+};
+
+union xlt_rule_tbl_u {
+	a_uint32_t val[3];
+	struct xlt_rule_tbl bf;
+};
+
+/*[table] XLT_ACTION_TBL*/
+#define XLT_ACTION_TBL
+#define XLT_ACTION_TBL_ADDRESS 0x4000
+#define XLT_ACTION_TBL_NUM     64
+#define XLT_ACTION_TBL_INC     0x10
+#define XLT_ACTION_TBL_TYPE    REG_TYPE_RW
+#define XLT_ACTION_TBL_DEFAULT 0x0
+	/*[field] VID_SWAP_CMD*/
+	#define XLT_ACTION_TBL_VID_SWAP_CMD
+	#define XLT_ACTION_TBL_VID_SWAP_CMD_OFFSET  0
+	#define XLT_ACTION_TBL_VID_SWAP_CMD_LEN     1
+	#define XLT_ACTION_TBL_VID_SWAP_CMD_DEFAULT 0x0
+	/*[field] XLT_SVID_CMD*/
+	#define XLT_ACTION_TBL_XLT_SVID_CMD
+	#define XLT_ACTION_TBL_XLT_SVID_CMD_OFFSET  1
+	#define XLT_ACTION_TBL_XLT_SVID_CMD_LEN     2
+	#define XLT_ACTION_TBL_XLT_SVID_CMD_DEFAULT 0x0
+	/*[field] XLT_SVID*/
+	#define XLT_ACTION_TBL_XLT_SVID
+	#define XLT_ACTION_TBL_XLT_SVID_OFFSET  3
+	#define XLT_ACTION_TBL_XLT_SVID_LEN     12
+	#define XLT_ACTION_TBL_XLT_SVID_DEFAULT 0x0
+	/*[field] XLT_CVID_CMD*/
+	#define XLT_ACTION_TBL_XLT_CVID_CMD
+	#define XLT_ACTION_TBL_XLT_CVID_CMD_OFFSET  15
+	#define XLT_ACTION_TBL_XLT_CVID_CMD_LEN     2
+	#define XLT_ACTION_TBL_XLT_CVID_CMD_DEFAULT 0x0
+	/*[field] XLT_CVID*/
+	#define XLT_ACTION_TBL_XLT_CVID
+	#define XLT_ACTION_TBL_XLT_CVID_OFFSET  17
+	#define XLT_ACTION_TBL_XLT_CVID_LEN     12
+	#define XLT_ACTION_TBL_XLT_CVID_DEFAULT 0x0
+	/*[field] PCP_SWAP_CMD*/
+	#define XLT_ACTION_TBL_PCP_SWAP_CMD
+	#define XLT_ACTION_TBL_PCP_SWAP_CMD_OFFSET  29
+	#define XLT_ACTION_TBL_PCP_SWAP_CMD_LEN     1
+	#define XLT_ACTION_TBL_PCP_SWAP_CMD_DEFAULT 0x0
+	/*[field] XLT_SPCP_CMD*/
+	#define XLT_ACTION_TBL_XLT_SPCP_CMD
+	#define XLT_ACTION_TBL_XLT_SPCP_CMD_OFFSET  30
+	#define XLT_ACTION_TBL_XLT_SPCP_CMD_LEN     1
+	#define XLT_ACTION_TBL_XLT_SPCP_CMD_DEFAULT 0x0
+	/*[field] XLT_SPCP*/
+	#define XLT_ACTION_TBL_XLT_SPCP
+	#define XLT_ACTION_TBL_XLT_SPCP_OFFSET  31
+	#define XLT_ACTION_TBL_XLT_SPCP_LEN     3
+	#define XLT_ACTION_TBL_XLT_SPCP_DEFAULT 0x0
+	/*[field] XLT_CPCP_CMD*/
+	#define XLT_ACTION_TBL_XLT_CPCP_CMD
+	#define XLT_ACTION_TBL_XLT_CPCP_CMD_OFFSET  34
+	#define XLT_ACTION_TBL_XLT_CPCP_CMD_LEN     1
+	#define XLT_ACTION_TBL_XLT_CPCP_CMD_DEFAULT 0x0
+	/*[field] XLT_CPCP*/
+	#define XLT_ACTION_TBL_XLT_CPCP
+	#define XLT_ACTION_TBL_XLT_CPCP_OFFSET  35
+	#define XLT_ACTION_TBL_XLT_CPCP_LEN     3
+	#define XLT_ACTION_TBL_XLT_CPCP_DEFAULT 0x0
+	/*[field] DEI_SWAP_CMD*/
+	#define XLT_ACTION_TBL_DEI_SWAP_CMD
+	#define XLT_ACTION_TBL_DEI_SWAP_CMD_OFFSET  38
+	#define XLT_ACTION_TBL_DEI_SWAP_CMD_LEN     1
+	#define XLT_ACTION_TBL_DEI_SWAP_CMD_DEFAULT 0x0
+	/*[field] XLT_SDEI_CMD*/
+	#define XLT_ACTION_TBL_XLT_SDEI_CMD
+	#define XLT_ACTION_TBL_XLT_SDEI_CMD_OFFSET  39
+	#define XLT_ACTION_TBL_XLT_SDEI_CMD_LEN     1
+	#define XLT_ACTION_TBL_XLT_SDEI_CMD_DEFAULT 0x0
+	/*[field] XLT_SDEI*/
+	#define XLT_ACTION_TBL_XLT_SDEI
+	#define XLT_ACTION_TBL_XLT_SDEI_OFFSET  40
+	#define XLT_ACTION_TBL_XLT_SDEI_LEN     1
+	#define XLT_ACTION_TBL_XLT_SDEI_DEFAULT 0x0
+	/*[field] XLT_CDEI_CMD*/
+	#define XLT_ACTION_TBL_XLT_CDEI_CMD
+	#define XLT_ACTION_TBL_XLT_CDEI_CMD_OFFSET  41
+	#define XLT_ACTION_TBL_XLT_CDEI_CMD_LEN     1
+	#define XLT_ACTION_TBL_XLT_CDEI_CMD_DEFAULT 0x0
+	/*[field] XLT_CDEI*/
+	#define XLT_ACTION_TBL_XLT_CDEI
+	#define XLT_ACTION_TBL_XLT_CDEI_OFFSET  42
+	#define XLT_ACTION_TBL_XLT_CDEI_LEN     1
+	#define XLT_ACTION_TBL_XLT_CDEI_DEFAULT 0x0
+	/*[field] VSI_CMD*/
+	#define XLT_ACTION_TBL_VSI_CMD
+	#define XLT_ACTION_TBL_VSI_CMD_OFFSET  43
+	#define XLT_ACTION_TBL_VSI_CMD_LEN     1
+	#define XLT_ACTION_TBL_VSI_CMD_DEFAULT 0x0
+	/*[field] VSI*/
+	#define XLT_ACTION_TBL_VSI
+	#define XLT_ACTION_TBL_VSI_OFFSET  44
+	#define XLT_ACTION_TBL_VSI_LEN     5
+	#define XLT_ACTION_TBL_VSI_DEFAULT 0x0
+	/*[field] COUNTER_EN*/
+	#define XLT_ACTION_TBL_COUNTER_EN
+	#define XLT_ACTION_TBL_COUNTER_EN_OFFSET  49
+	#define XLT_ACTION_TBL_COUNTER_EN_LEN     1
+	#define XLT_ACTION_TBL_COUNTER_EN_DEFAULT 0x0
+	/*[field] COUNTER_ID*/
+	#define XLT_ACTION_TBL_COUNTER_ID
+	#define XLT_ACTION_TBL_COUNTER_ID_OFFSET  50
+	#define XLT_ACTION_TBL_COUNTER_ID_LEN     6
+	#define XLT_ACTION_TBL_COUNTER_ID_DEFAULT 0x0
+
+struct xlt_action_tbl {
+	a_uint32_t  vid_swap_cmd:1;
+	a_uint32_t  xlt_svid_cmd:2;
+	a_uint32_t  xlt_svid:12;
+	a_uint32_t  xlt_cvid_cmd:2;
+	a_uint32_t  xlt_cvid:12;
+	a_uint32_t  pcp_swap_cmd:1;
+	a_uint32_t  xlt_spcp_cmd:1;
+	a_uint32_t  xlt_spcp_0:1;
+	a_uint32_t  xlt_spcp_1:2;
+	a_uint32_t  xlt_cpcp_cmd:1;
+	a_uint32_t  xlt_cpcp:3;
+	a_uint32_t  dei_swap_cmd:1;
+	a_uint32_t  xlt_sdei_cmd:1;
+	a_uint32_t  xlt_sdei:1;
+	a_uint32_t  xlt_cdei_cmd:1;
+	a_uint32_t  xlt_cdei:1;
+	a_uint32_t  vsi_cmd:1;
+	a_uint32_t  vsi:5;
+	a_uint32_t  counter_en:1;
+	a_uint32_t  counter_id:6;
+	a_uint32_t  _reserved0:8;
+};
+
+union xlt_action_tbl_u {
+	a_uint32_t val[2];
+	struct xlt_action_tbl bf;
+};
+
+/*[table] EG_VLAN_XLT_RULE*/
+#define EG_VLAN_XLT_RULE
+#define EG_VLAN_XLT_RULE_ADDRESS 0x200
+#define EG_VLAN_XLT_RULE_NUM     64
+#define EG_VLAN_XLT_RULE_INC     0x8
+#define EG_VLAN_XLT_RULE_TYPE    REG_TYPE_RW
+#define EG_VLAN_XLT_RULE_DEFAULT 0x0
+	/*[field] VALID*/
+	#define EG_VLAN_XLT_RULE_VALID
+	#define EG_VLAN_XLT_RULE_VALID_OFFSET  0
+	#define EG_VLAN_XLT_RULE_VALID_LEN     1
+	#define EG_VLAN_XLT_RULE_VALID_DEFAULT 0x0
+	/*[field] PORT_BITMAP*/
+	#define EG_VLAN_XLT_RULE_PORT_BITMAP
+	#define EG_VLAN_XLT_RULE_PORT_BITMAP_OFFSET  1
+	#define EG_VLAN_XLT_RULE_PORT_BITMAP_LEN     8
+	#define EG_VLAN_XLT_RULE_PORT_BITMAP_DEFAULT 0x0
+	/*[field] VSI_INCL*/
+	#define EG_VLAN_XLT_RULE_VSI_INCL
+	#define EG_VLAN_XLT_RULE_VSI_INCL_OFFSET  9
+	#define EG_VLAN_XLT_RULE_VSI_INCL_LEN     1
+	#define EG_VLAN_XLT_RULE_VSI_INCL_DEFAULT 0x0
+	/*[field] VSI*/
+	#define EG_VLAN_XLT_RULE_VSI
+	#define EG_VLAN_XLT_RULE_VSI_OFFSET  10
+	#define EG_VLAN_XLT_RULE_VSI_LEN     5
+	#define EG_VLAN_XLT_RULE_VSI_DEFAULT 0x0
+	/*[field] VSI_VALID*/
+	#define EG_VLAN_XLT_RULE_VSI_VALID
+	#define EG_VLAN_XLT_RULE_VSI_VALID_OFFSET  15
+	#define EG_VLAN_XLT_RULE_VSI_VALID_LEN     1
+	#define EG_VLAN_XLT_RULE_VSI_VALID_DEFAULT 0x0
+	/*[field] SKEY_FMT*/
+	#define EG_VLAN_XLT_RULE_SKEY_FMT
+	#define EG_VLAN_XLT_RULE_SKEY_FMT_OFFSET  16
+	#define EG_VLAN_XLT_RULE_SKEY_FMT_LEN     3
+	#define EG_VLAN_XLT_RULE_SKEY_FMT_DEFAULT 0x0
+	/*[field] SKEY_VID_INCL*/
+	#define EG_VLAN_XLT_RULE_SKEY_VID_INCL
+	#define EG_VLAN_XLT_RULE_SKEY_VID_INCL_OFFSET  19
+	#define EG_VLAN_XLT_RULE_SKEY_VID_INCL_LEN     1
+	#define EG_VLAN_XLT_RULE_SKEY_VID_INCL_DEFAULT 0x0
+	/*[field] SKEY_VID*/
+	#define EG_VLAN_XLT_RULE_SKEY_VID
+	#define EG_VLAN_XLT_RULE_SKEY_VID_OFFSET  20
+	#define EG_VLAN_XLT_RULE_SKEY_VID_LEN     12
+	#define EG_VLAN_XLT_RULE_SKEY_VID_DEFAULT 0x0
+	/*[field] SKEY_PCP_INCL*/
+	#define EG_VLAN_XLT_RULE_SKEY_PCP_INCL
+	#define EG_VLAN_XLT_RULE_SKEY_PCP_INCL_OFFSET  32
+	#define EG_VLAN_XLT_RULE_SKEY_PCP_INCL_LEN     1
+	#define EG_VLAN_XLT_RULE_SKEY_PCP_INCL_DEFAULT 0x0
+	/*[field] SKEY_PCP*/
+	#define EG_VLAN_XLT_RULE_SKEY_PCP
+	#define EG_VLAN_XLT_RULE_SKEY_PCP_OFFSET  33
+	#define EG_VLAN_XLT_RULE_SKEY_PCP_LEN     3
+	#define EG_VLAN_XLT_RULE_SKEY_PCP_DEFAULT 0x0
+	/*[field] SKEY_DEI_INCL*/
+	#define EG_VLAN_XLT_RULE_SKEY_DEI_INCL
+	#define EG_VLAN_XLT_RULE_SKEY_DEI_INCL_OFFSET  36
+	#define EG_VLAN_XLT_RULE_SKEY_DEI_INCL_LEN     1
+	#define EG_VLAN_XLT_RULE_SKEY_DEI_INCL_DEFAULT 0x0
+	/*[field] SKEY_DEI*/
+	#define EG_VLAN_XLT_RULE_SKEY_DEI
+	#define EG_VLAN_XLT_RULE_SKEY_DEI_OFFSET  37
+	#define EG_VLAN_XLT_RULE_SKEY_DEI_LEN     1
+	#define EG_VLAN_XLT_RULE_SKEY_DEI_DEFAULT 0x0
+	/*[field] CKEY_FMT*/
+	#define EG_VLAN_XLT_RULE_CKEY_FMT
+	#define EG_VLAN_XLT_RULE_CKEY_FMT_OFFSET  38
+	#define EG_VLAN_XLT_RULE_CKEY_FMT_LEN     3
+	#define EG_VLAN_XLT_RULE_CKEY_FMT_DEFAULT 0x0
+	/*[field] CKEY_VID_INCL*/
+	#define EG_VLAN_XLT_RULE_CKEY_VID_INCL
+	#define EG_VLAN_XLT_RULE_CKEY_VID_INCL_OFFSET  41
+	#define EG_VLAN_XLT_RULE_CKEY_VID_INCL_LEN     1
+	#define EG_VLAN_XLT_RULE_CKEY_VID_INCL_DEFAULT 0x0
+	/*[field] CKEY_VID*/
+	#define EG_VLAN_XLT_RULE_CKEY_VID
+	#define EG_VLAN_XLT_RULE_CKEY_VID_OFFSET  42
+	#define EG_VLAN_XLT_RULE_CKEY_VID_LEN     12
+	#define EG_VLAN_XLT_RULE_CKEY_VID_DEFAULT 0x0
+	/*[field] CKEY_PCP_INCL*/
+	#define EG_VLAN_XLT_RULE_CKEY_PCP_INCL
+	#define EG_VLAN_XLT_RULE_CKEY_PCP_INCL_OFFSET  54
+	#define EG_VLAN_XLT_RULE_CKEY_PCP_INCL_LEN     1
+	#define EG_VLAN_XLT_RULE_CKEY_PCP_INCL_DEFAULT 0x0
+	/*[field] CKEY_PCP*/
+	#define EG_VLAN_XLT_RULE_CKEY_PCP
+	#define EG_VLAN_XLT_RULE_CKEY_PCP_OFFSET  55
+	#define EG_VLAN_XLT_RULE_CKEY_PCP_LEN     3
+	#define EG_VLAN_XLT_RULE_CKEY_PCP_DEFAULT 0x0
+	/*[field] CKEY_DEI_INCL*/
+	#define EG_VLAN_XLT_RULE_CKEY_DEI_INCL
+	#define EG_VLAN_XLT_RULE_CKEY_DEI_INCL_OFFSET  58
+	#define EG_VLAN_XLT_RULE_CKEY_DEI_INCL_LEN     1
+	#define EG_VLAN_XLT_RULE_CKEY_DEI_INCL_DEFAULT 0x0
+	/*[field] CKEY_DEI*/
+	#define EG_VLAN_XLT_RULE_CKEY_DEI
+	#define EG_VLAN_XLT_RULE_CKEY_DEI_OFFSET  59
+	#define EG_VLAN_XLT_RULE_CKEY_DEI_LEN     1
+	#define EG_VLAN_XLT_RULE_CKEY_DEI_DEFAULT 0x0
+
+struct eg_vlan_xlt_rule {
+	a_uint32_t  valid:1;
+	a_uint32_t  port_bitmap:8;
+	a_uint32_t  vsi_incl:1;
+	a_uint32_t  vsi:5;
+	a_uint32_t  vsi_valid:1;
+	a_uint32_t  skey_fmt:3;
+	a_uint32_t  skey_vid_incl:1;
+	a_uint32_t  skey_vid:12;
+	a_uint32_t  skey_pcp_incl:1;
+	a_uint32_t  skey_pcp:3;
+	a_uint32_t  skey_dei_incl:1;
+	a_uint32_t  skey_dei:1;
+	a_uint32_t  ckey_fmt:3;
+	a_uint32_t  ckey_vid_incl:1;
+	a_uint32_t  ckey_vid:12;
+	a_uint32_t  ckey_pcp_incl:1;
+	a_uint32_t  ckey_pcp:3;
+	a_uint32_t  ckey_dei_incl:1;
+	a_uint32_t  ckey_dei:1;
+	a_uint32_t  _reserved0:4;
+};
+
+union eg_vlan_xlt_rule_u {
+	a_uint32_t val[2];
+	struct eg_vlan_xlt_rule bf;
+};
+
+/*[register] EG_VSI_TAG*/
+#define EG_VSI_TAG
+#define EG_VSI_TAG_ADDRESS	0x0
+#define EG_VSI_TAG_NUM		32
+#define EG_VSI_TAG_INC		0x4
+#define EG_VSI_TAG_TYPE		REG_TYPE_RW
+#define EG_VSI_TAG_DEFAULT	0xaaaa
+	/*[field] TAGGED_MODE_PORT_BITMAP*/
+	#define EG_VSI_TAG_TAGGED_MODE_PORT_BITMAP
+	#define EG_VSI_TAG_TAGGED_MODE_PORT_BITMAP_OFFSET	0
+	#define EG_VSI_TAG_TAGGED_MODE_PORT_BITMAP_LEN		16
+	#define EG_VSI_TAG_TAGGED_MODE_PORT_BITMAP_DEFAULT	0xaaaa
+
+struct eg_vsi_tag {
+	a_uint32_t tagged_mode_port_bitmap:16;
+	a_uint32_t _reserved0:16;
+};
+
+union eg_vsi_tag_u {
+	a_uint32_t val;
+	struct eg_vsi_tag bf;
+};
+
+/*[register] PORT_EG_DEF_VID*/
+#define PORT_EG_DEF_VID
+#define PORT_EG_DEF_VID_ADDRESS 0x400
+#define PORT_EG_DEF_VID_NUM     8
+#define PORT_EG_DEF_VID_INC     0x4
+#define PORT_EG_DEF_VID_TYPE    REG_TYPE_RW
+#define PORT_EG_DEF_VID_DEFAULT 0x0
+	/*[field] PORT_DEF_SVID*/
+	#define PORT_EG_DEF_VID_PORT_DEF_SVID
+	#define PORT_EG_DEF_VID_PORT_DEF_SVID_OFFSET  0
+	#define PORT_EG_DEF_VID_PORT_DEF_SVID_LEN     12
+	#define PORT_EG_DEF_VID_PORT_DEF_SVID_DEFAULT 0x0
+	/*[field] PORT_DEF_SVID_EN*/
+	#define PORT_EG_DEF_VID_PORT_DEF_SVID_EN
+	#define PORT_EG_DEF_VID_PORT_DEF_SVID_EN_OFFSET  12
+	#define PORT_EG_DEF_VID_PORT_DEF_SVID_EN_LEN     1
+	#define PORT_EG_DEF_VID_PORT_DEF_SVID_EN_DEFAULT 0x0
+	/*[field] PORT_DEF_CVID*/
+	#define PORT_EG_DEF_VID_PORT_DEF_CVID
+	#define PORT_EG_DEF_VID_PORT_DEF_CVID_OFFSET  16
+	#define PORT_EG_DEF_VID_PORT_DEF_CVID_LEN     12
+	#define PORT_EG_DEF_VID_PORT_DEF_CVID_DEFAULT 0x0
+	/*[field] PORT_DEF_CVID_EN*/
+	#define PORT_EG_DEF_VID_PORT_DEF_CVID_EN
+	#define PORT_EG_DEF_VID_PORT_DEF_CVID_EN_OFFSET  28
+	#define PORT_EG_DEF_VID_PORT_DEF_CVID_EN_LEN     1
+	#define PORT_EG_DEF_VID_PORT_DEF_CVID_EN_DEFAULT 0x0
+
+struct port_eg_def_vid {
+	a_uint32_t  port_def_svid:12;
+	a_uint32_t  port_def_svid_en:1;
+	a_uint32_t  _reserved0:3;
+	a_uint32_t  port_def_cvid:12;
+	a_uint32_t  port_def_cvid_en:1;
+	a_uint32_t  _reserved1:3;
+};
+
+union port_eg_def_vid_u {
+	a_uint32_t val;
+	struct port_eg_def_vid bf;
+};
+
+/*[register] PORT_EG_VLAN*/
+#define PORT_EG_VLAN
+#define PORT_EG_VLAN_ADDRESS 0x420
+#define PORT_EG_VLAN_NUM     8
+#define PORT_EG_VLAN_INC     0x4
+#define PORT_EG_VLAN_TYPE    REG_TYPE_RW
+#define PORT_EG_VLAN_DEFAULT 0x14
+	/*[field] PORT_VLAN_TYPE*/
+	#define PORT_EG_VLAN_PORT_VLAN_TYPE
+	#define PORT_EG_VLAN_PORT_VLAN_TYPE_OFFSET  0
+	#define PORT_EG_VLAN_PORT_VLAN_TYPE_LEN     1
+	#define PORT_EG_VLAN_PORT_VLAN_TYPE_DEFAULT 0x0
+	/*[field] PORT_EG_VLAN_CTAG_MODE*/
+	#define PORT_EG_VLAN_PORT_EG_VLAN_CTAG_MODE
+	#define PORT_EG_VLAN_PORT_EG_VLAN_CTAG_MODE_OFFSET  1
+	#define PORT_EG_VLAN_PORT_EG_VLAN_CTAG_MODE_LEN     2
+	#define PORT_EG_VLAN_PORT_EG_VLAN_CTAG_MODE_DEFAULT 0x2
+	/*[field] PORT_EG_VLAN_STAG_MODE*/
+	#define PORT_EG_VLAN_PORT_EG_VLAN_STAG_MODE
+	#define PORT_EG_VLAN_PORT_EG_VLAN_STAG_MODE_OFFSET  3
+	#define PORT_EG_VLAN_PORT_EG_VLAN_STAG_MODE_LEN     2
+	#define PORT_EG_VLAN_PORT_EG_VLAN_STAG_MODE_DEFAULT 0x2
+	/*[field] VSI_TAG_MODE_EN*/
+	#define PORT_EG_VLAN_VSI_TAG_MODE_EN
+	#define PORT_EG_VLAN_VSI_TAG_MODE_EN_OFFSET  5
+	#define PORT_EG_VLAN_VSI_TAG_MODE_EN_LEN     1
+	#define PORT_EG_VLAN_VSI_TAG_MODE_EN_DEFAULT 0x0
+	/*[field] PORT_EG_PCP_PROP_CMD*/
+	#define PORT_EG_VLAN_PORT_EG_PCP_PROP_CMD
+	#define PORT_EG_VLAN_PORT_EG_PCP_PROP_CMD_OFFSET  6
+	#define PORT_EG_VLAN_PORT_EG_PCP_PROP_CMD_LEN     1
+	#define PORT_EG_VLAN_PORT_EG_PCP_PROP_CMD_DEFAULT 0x0
+	/*[field] PORT_EG_DEI_PROP_CMD*/
+	#define PORT_EG_VLAN_PORT_EG_DEI_PROP_CMD
+	#define PORT_EG_VLAN_PORT_EG_DEI_PROP_CMD_OFFSET  7
+	#define PORT_EG_VLAN_PORT_EG_DEI_PROP_CMD_LEN     1
+	#define PORT_EG_VLAN_PORT_EG_DEI_PROP_CMD_DEFAULT 0x0
+	/*[field] TX_COUNTING_EN*/
+	#define PORT_EG_VLAN_TX_COUNTING_EN
+	#define PORT_EG_VLAN_TX_COUNTING_EN_OFFSET  8
+	#define PORT_EG_VLAN_TX_COUNTING_EN_LEN     1
+	#define PORT_EG_VLAN_TX_COUNTING_EN_DEFAULT 0x0
+
+struct port_eg_vlan {
+	a_uint32_t  port_vlan_type:1;
+	a_uint32_t  port_eg_vlan_ctag_mode:2;
+	a_uint32_t  port_eg_vlan_stag_mode:2;
+	a_uint32_t  vsi_tag_mode_en:1;
+	a_uint32_t  port_eg_pcp_prop_cmd:1;
+	a_uint32_t  port_eg_dei_prop_cmd:1;
+	a_uint32_t  tx_counting_en:1;
+	a_uint32_t  _reserved0:23;
+};
+
+union port_eg_vlan_u {
+	a_uint32_t val;
+	struct port_eg_vlan bf;
+};
+
+/*[register] EG_VLAN_TPID*/
+#define EG_VLAN_TPID
+#define EG_VLAN_TPID_ADDRESS 0x440
+#define EG_VLAN_TPID_NUM     1
+#define EG_VLAN_TPID_INC     0x4
+#define EG_VLAN_TPID_TYPE    REG_TYPE_RW
+#define EG_VLAN_TPID_DEFAULT 0x810088a8
+	/*[field] STPID*/
+	#define EG_VLAN_TPID_STPID
+	#define EG_VLAN_TPID_STPID_OFFSET  0
+	#define EG_VLAN_TPID_STPID_LEN     16
+	#define EG_VLAN_TPID_STPID_DEFAULT 0x88a8
+	/*[field] CTPID*/
+	#define EG_VLAN_TPID_CTPID
+	#define EG_VLAN_TPID_CTPID_OFFSET  16
+	#define EG_VLAN_TPID_CTPID_LEN     16
+	#define EG_VLAN_TPID_CTPID_DEFAULT 0x8100
+
+struct eg_vlan_tpid {
+	a_uint32_t  stpid:16;
+	a_uint32_t  ctpid:16;
+};
+
+union eg_vlan_tpid_u {
+	a_uint32_t val;
+	struct eg_vlan_tpid bf;
+};
+
+/*[register] EG_BRIDGE_CONFIG*/
+#define EG_BRIDGE_CONFIG
+#define EG_BRIDGE_CONFIG_ADDRESS 0x6000
+#define EG_BRIDGE_CONFIG_NUM     1
+#define EG_BRIDGE_CONFIG_INC     0x4
+#define EG_BRIDGE_CONFIG_TYPE    REG_TYPE_RW
+#define EG_BRIDGE_CONFIG_DEFAULT 0x0
+	/*[field] BRIDGE_TYPE*/
+	#define EG_BRIDGE_CONFIG_BRIDGE_TYPE
+	#define EG_BRIDGE_CONFIG_BRIDGE_TYPE_OFFSET  0
+	#define EG_BRIDGE_CONFIG_BRIDGE_TYPE_LEN     1
+	#define EG_BRIDGE_CONFIG_BRIDGE_TYPE_DEFAULT 0x0
+	/*[field] PKT_L2_EDIT_EN*/
+	#define EG_BRIDGE_CONFIG_PKT_L2_EDIT_EN
+	#define EG_BRIDGE_CONFIG_PKT_L2_EDIT_EN_OFFSET  1
+	#define EG_BRIDGE_CONFIG_PKT_L2_EDIT_EN_LEN     1
+	#define EG_BRIDGE_CONFIG_PKT_L2_EDIT_EN_DEFAULT 0x0
+	/*[field] QUEUE_CNT_EN*/
+	#define EG_BRIDGE_CONFIG_QUEUE_CNT_EN
+	#define EG_BRIDGE_CONFIG_QUEUE_CNT_EN_OFFSET  2
+	#define EG_BRIDGE_CONFIG_QUEUE_CNT_EN_LEN     1
+	#define EG_BRIDGE_CONFIG_QUEUE_CNT_EN_DEFAULT 0x0
+
+struct eg_bridge_config {
+	a_uint32_t  bridge_type:1;
+	a_uint32_t  pkt_l2_edit_en:1;
+	a_uint32_t  queue_cnt_en:1;
+	a_uint32_t  _reserved0:29;
+};
+
+union eg_bridge_config_u {
+	a_uint32_t val;
+	struct eg_bridge_config bf;
+};
+
+/*[table] EG_VLAN_XLT_ACTION*/
+#define EG_VLAN_XLT_ACTION
+#define EG_VLAN_XLT_ACTION_ADDRESS 0xd000
+#define EG_VLAN_XLT_ACTION_NUM     64
+#define EG_VLAN_XLT_ACTION_INC     0x8
+#define EG_VLAN_XLT_ACTION_TYPE    REG_TYPE_RW
+#define EG_VLAN_XLT_ACTION_DEFAULT 0x0
+	/*[field] VID_SWAP_CMD*/
+	#define EG_VLAN_XLT_ACTION_VID_SWAP_CMD
+	#define EG_VLAN_XLT_ACTION_VID_SWAP_CMD_OFFSET  0
+	#define EG_VLAN_XLT_ACTION_VID_SWAP_CMD_LEN     1
+	#define EG_VLAN_XLT_ACTION_VID_SWAP_CMD_DEFAULT 0x0
+	/*[field] XLT_SVID_CMD*/
+	#define EG_VLAN_XLT_ACTION_XLT_SVID_CMD
+	#define EG_VLAN_XLT_ACTION_XLT_SVID_CMD_OFFSET  1
+	#define EG_VLAN_XLT_ACTION_XLT_SVID_CMD_LEN     2
+	#define EG_VLAN_XLT_ACTION_XLT_SVID_CMD_DEFAULT 0x0
+	/*[field] XLT_SVID*/
+	#define EG_VLAN_XLT_ACTION_XLT_SVID
+	#define EG_VLAN_XLT_ACTION_XLT_SVID_OFFSET  3
+	#define EG_VLAN_XLT_ACTION_XLT_SVID_LEN     12
+	#define EG_VLAN_XLT_ACTION_XLT_SVID_DEFAULT 0x0
+	/*[field] XLT_CVID_CMD*/
+	#define EG_VLAN_XLT_ACTION_XLT_CVID_CMD
+	#define EG_VLAN_XLT_ACTION_XLT_CVID_CMD_OFFSET  15
+	#define EG_VLAN_XLT_ACTION_XLT_CVID_CMD_LEN     2
+	#define EG_VLAN_XLT_ACTION_XLT_CVID_CMD_DEFAULT 0x0
+	/*[field] XLT_CVID*/
+	#define EG_VLAN_XLT_ACTION_XLT_CVID
+	#define EG_VLAN_XLT_ACTION_XLT_CVID_OFFSET  17
+	#define EG_VLAN_XLT_ACTION_XLT_CVID_LEN     12
+	#define EG_VLAN_XLT_ACTION_XLT_CVID_DEFAULT 0x0
+	/*[field] PCP_SWAP_CMD*/
+	#define EG_VLAN_XLT_ACTION_PCP_SWAP_CMD
+	#define EG_VLAN_XLT_ACTION_PCP_SWAP_CMD_OFFSET  29
+	#define EG_VLAN_XLT_ACTION_PCP_SWAP_CMD_LEN     1
+	#define EG_VLAN_XLT_ACTION_PCP_SWAP_CMD_DEFAULT 0x0
+	/*[field] XLT_SPCP_CMD*/
+	#define EG_VLAN_XLT_ACTION_XLT_SPCP_CMD
+	#define EG_VLAN_XLT_ACTION_XLT_SPCP_CMD_OFFSET  30
+	#define EG_VLAN_XLT_ACTION_XLT_SPCP_CMD_LEN     1
+	#define EG_VLAN_XLT_ACTION_XLT_SPCP_CMD_DEFAULT 0x0
+	/*[field] XLT_SPCP*/
+	#define EG_VLAN_XLT_ACTION_XLT_SPCP
+	#define EG_VLAN_XLT_ACTION_XLT_SPCP_OFFSET  31
+	#define EG_VLAN_XLT_ACTION_XLT_SPCP_LEN     3
+	#define EG_VLAN_XLT_ACTION_XLT_SPCP_DEFAULT 0x0
+	/*[field] XLT_CPCP_CMD*/
+	#define EG_VLAN_XLT_ACTION_XLT_CPCP_CMD
+	#define EG_VLAN_XLT_ACTION_XLT_CPCP_CMD_OFFSET  34
+	#define EG_VLAN_XLT_ACTION_XLT_CPCP_CMD_LEN     1
+	#define EG_VLAN_XLT_ACTION_XLT_CPCP_CMD_DEFAULT 0x0
+	/*[field] XLT_CPCP*/
+	#define EG_VLAN_XLT_ACTION_XLT_CPCP
+	#define EG_VLAN_XLT_ACTION_XLT_CPCP_OFFSET  35
+	#define EG_VLAN_XLT_ACTION_XLT_CPCP_LEN     3
+	#define EG_VLAN_XLT_ACTION_XLT_CPCP_DEFAULT 0x0
+	/*[field] DEI_SWAP_CMD*/
+	#define EG_VLAN_XLT_ACTION_DEI_SWAP_CMD
+	#define EG_VLAN_XLT_ACTION_DEI_SWAP_CMD_OFFSET  38
+	#define EG_VLAN_XLT_ACTION_DEI_SWAP_CMD_LEN     1
+	#define EG_VLAN_XLT_ACTION_DEI_SWAP_CMD_DEFAULT 0x0
+	/*[field] XLT_SDEI_CMD*/
+	#define EG_VLAN_XLT_ACTION_XLT_SDEI_CMD
+	#define EG_VLAN_XLT_ACTION_XLT_SDEI_CMD_OFFSET  39
+	#define EG_VLAN_XLT_ACTION_XLT_SDEI_CMD_LEN     1
+	#define EG_VLAN_XLT_ACTION_XLT_SDEI_CMD_DEFAULT 0x0
+	/*[field] XLT_SDEI*/
+	#define EG_VLAN_XLT_ACTION_XLT_SDEI
+	#define EG_VLAN_XLT_ACTION_XLT_SDEI_OFFSET  40
+	#define EG_VLAN_XLT_ACTION_XLT_SDEI_LEN     1
+	#define EG_VLAN_XLT_ACTION_XLT_SDEI_DEFAULT 0x0
+	/*[field] XLT_CDEI_CMD*/
+	#define EG_VLAN_XLT_ACTION_XLT_CDEI_CMD
+	#define EG_VLAN_XLT_ACTION_XLT_CDEI_CMD_OFFSET  41
+	#define EG_VLAN_XLT_ACTION_XLT_CDEI_CMD_LEN     1
+	#define EG_VLAN_XLT_ACTION_XLT_CDEI_CMD_DEFAULT 0x0
+	/*[field] XLT_CDEI*/
+	#define EG_VLAN_XLT_ACTION_XLT_CDEI
+	#define EG_VLAN_XLT_ACTION_XLT_CDEI_OFFSET  42
+	#define EG_VLAN_XLT_ACTION_XLT_CDEI_LEN     1
+	#define EG_VLAN_XLT_ACTION_XLT_CDEI_DEFAULT 0x0
+	/*[field] COUNTER_EN*/
+	#define EG_VLAN_XLT_ACTION_COUNTER_EN
+	#define EG_VLAN_XLT_ACTION_COUNTER_EN_OFFSET  43
+	#define EG_VLAN_XLT_ACTION_COUNTER_EN_LEN     1
+	#define EG_VLAN_XLT_ACTION_COUNTER_EN_DEFAULT 0x0
+	/*[field] COUNTER_ID*/
+	#define EG_VLAN_XLT_ACTION_COUNTER_ID
+	#define EG_VLAN_XLT_ACTION_COUNTER_ID_OFFSET  44
+	#define EG_VLAN_XLT_ACTION_COUNTER_ID_LEN     6
+	#define EG_VLAN_XLT_ACTION_COUNTER_ID_DEFAULT 0x0
+
+struct eg_vlan_xlt_action {
+	a_uint32_t  vid_swap_cmd:1;
+	a_uint32_t  xlt_svid_cmd:2;
+	a_uint32_t  xlt_svid:12;
+	a_uint32_t  xlt_cvid_cmd:2;
+	a_uint32_t  xlt_cvid:12;
+	a_uint32_t  pcp_swap_cmd:1;
+	a_uint32_t  xlt_spcp_cmd:1;
+	a_uint32_t  xlt_spcp_0:1;
+	a_uint32_t  xlt_spcp_1:2;
+	a_uint32_t  xlt_cpcp_cmd:1;
+	a_uint32_t  xlt_cpcp:3;
+	a_uint32_t  dei_swap_cmd:1;
+	a_uint32_t  xlt_sdei_cmd:1;
+	a_uint32_t  xlt_sdei:1;
+	a_uint32_t  xlt_cdei_cmd:1;
+	a_uint32_t  xlt_cdei:1;
+	a_uint32_t  counter_en:1;
+	a_uint32_t  counter_id:6;
+	a_uint32_t  _reserved0:14;
+};
+
+union eg_vlan_xlt_action_u {
+	a_uint32_t val[2];
+	struct eg_vlan_xlt_action bf;
+};
+
+/*[table] VLAN_DEV_TX_COUNTER_TBL*/
+#define VLAN_DEV_TX_COUNTER_TBL
+#define VLAN_DEV_TX_COUNTER_TBL_ADDRESS 0x2000
+#define VLAN_DEV_TX_COUNTER_TBL_NUM     64
+#define VLAN_DEV_TX_COUNTER_TBL_INC     0x10
+#define VLAN_DEV_TX_COUNTER_TBL_TYPE    REG_TYPE_RW
+#define VLAN_DEV_TX_COUNTER_TBL_DEFAULT 0x0
+	/*[field] TX_PKT_CNT*/
+	#define VLAN_DEV_TX_COUNTER_TBL_TX_PKT_CNT
+	#define VLAN_DEV_TX_COUNTER_TBL_TX_PKT_CNT_OFFSET  0
+	#define VLAN_DEV_TX_COUNTER_TBL_TX_PKT_CNT_LEN     32
+	#define VLAN_DEV_TX_COUNTER_TBL_TX_PKT_CNT_DEFAULT 0x0
+	/*[field] TX_BYTE_CNT*/
+	#define VLAN_DEV_TX_COUNTER_TBL_TX_BYTE_CNT
+	#define VLAN_DEV_TX_COUNTER_TBL_TX_BYTE_CNT_OFFSET  32
+	#define VLAN_DEV_TX_COUNTER_TBL_TX_BYTE_CNT_LEN     40
+	#define VLAN_DEV_TX_COUNTER_TBL_TX_BYTE_CNT_DEFAULT 0x0
+
+struct vlan_dev_tx_counter_tbl {
+	a_uint32_t  tx_pkt_cnt:32;
+	a_uint32_t  tx_byte_cnt_0:32;
+	a_uint32_t  tx_byte_cnt_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union vlan_dev_tx_counter_tbl_u {
+	a_uint32_t val[3];
+	struct vlan_dev_tx_counter_tbl bf;
+};
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_pppoe.h b/qca-ssdk/include/hsl/hppe/hppe_pppoe.h
new file mode 100755
index 0000000..051e596
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_pppoe.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_PPPOE_H_
+#define _HPPE_PPPOE_H_
+
+#define PPPOE_SESSION_MAX_ENTRY	16
+#define PPPOE_SESSION_EXT_MAX_ENTRY	16
+#define PPPOE_SESSION_EXT1_MAX_ENTRY	16
+
+sw_error_t
+hppe_pppoe_session_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pppoe_session_u *value);
+
+sw_error_t
+hppe_pppoe_session_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pppoe_session_u *value);
+
+sw_error_t
+hppe_pppoe_session_ext_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pppoe_session_ext_u *value);
+
+sw_error_t
+hppe_pppoe_session_ext_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pppoe_session_ext_u *value);
+
+sw_error_t
+hppe_pppoe_session_ext1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pppoe_session_ext1_u *value);
+
+sw_error_t
+hppe_pppoe_session_ext1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pppoe_session_ext1_u *value);
+
+sw_error_t
+hppe_pppoe_session_session_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pppoe_session_session_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pppoe_session_l3_if_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pppoe_session_l3_if_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pppoe_session_port_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pppoe_session_port_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pppoe_session_ext_uc_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pppoe_session_ext_uc_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pppoe_session_ext_mc_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pppoe_session_ext_mc_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pppoe_session_ext_smac_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pppoe_session_ext_smac_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pppoe_session_ext_l3_if_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pppoe_session_ext_l3_if_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pppoe_session_ext_smac_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pppoe_session_ext_smac_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pppoe_session_ext1_smac_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pppoe_session_ext1_smac_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_pppoe_reg.h b/qca-ssdk/include/hsl/hppe/hppe_pppoe_reg.h
new file mode 100755
index 0000000..715c828
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_pppoe_reg.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_PPPOE_REG_H
+#define HPPE_PPPOE_REG_H
+
+
+/*[register] PPPOE_SESSION*/
+#define PPPOE_SESSION
+#define PPPOE_SESSION_ADDRESS 0xc20
+#define PPPOE_SESSION_NUM     16
+#define PPPOE_SESSION_INC     0x4
+#define PPPOE_SESSION_TYPE    REG_TYPE_RW
+#define PPPOE_SESSION_DEFAULT 0x0
+	/*[field] SESSION_ID*/
+	#define PPPOE_SESSION_SESSION_ID
+	#define PPPOE_SESSION_SESSION_ID_OFFSET  0
+	#define PPPOE_SESSION_SESSION_ID_LEN     16
+	#define PPPOE_SESSION_SESSION_ID_DEFAULT 0x0
+	/*[field] PORT_BITMAP*/
+	#define PPPOE_SESSION_PORT_BITMAP
+	#define PPPOE_SESSION_PORT_BITMAP_OFFSET  16
+	#define PPPOE_SESSION_PORT_BITMAP_LEN     8
+	#define PPPOE_SESSION_PORT_BITMAP_DEFAULT 0x0
+	/*[field] L3_IF_INDEX*/
+	#define PPPOE_SESSION_L3_IF_INDEX
+	#define PPPOE_SESSION_L3_IF_INDEX_OFFSET  24
+	#define PPPOE_SESSION_L3_IF_INDEX_LEN     8
+	#define PPPOE_SESSION_L3_IF_INDEX_DEFAULT 0x0
+
+struct pppoe_session {
+	a_uint32_t  session_id:16;
+	a_uint32_t  port_bitmap:8;
+	a_uint32_t  l3_if_index:8;
+};
+
+union pppoe_session_u {
+	a_uint32_t val;
+	struct pppoe_session bf;
+};
+
+/*[register] PPPOE_SESSION_EXT*/
+#define PPPOE_SESSION_EXT
+#define PPPOE_SESSION_EXT_ADDRESS 0xc60
+#define PPPOE_SESSION_EXT_NUM     16
+#define PPPOE_SESSION_EXT_INC     0x4
+#define PPPOE_SESSION_EXT_TYPE    REG_TYPE_RW
+#define PPPOE_SESSION_EXT_DEFAULT 0x0
+	/*[field] L3_IF_VALID*/
+	#define PPPOE_SESSION_EXT_L3_IF_VALID
+	#define PPPOE_SESSION_EXT_L3_IF_VALID_OFFSET  0
+	#define PPPOE_SESSION_EXT_L3_IF_VALID_LEN     1
+	#define PPPOE_SESSION_EXT_L3_IF_VALID_DEFAULT 0x0
+	/*[field] MC_VALID*/
+	#define PPPOE_SESSION_EXT_MC_VALID
+	#define PPPOE_SESSION_EXT_MC_VALID_OFFSET  1
+	#define PPPOE_SESSION_EXT_MC_VALID_LEN     1
+	#define PPPOE_SESSION_EXT_MC_VALID_DEFAULT 0x0
+	/*[field] UC_VALID*/
+	#define PPPOE_SESSION_EXT_UC_VALID
+	#define PPPOE_SESSION_EXT_UC_VALID_OFFSET  2
+	#define PPPOE_SESSION_EXT_UC_VALID_LEN     1
+	#define PPPOE_SESSION_EXT_UC_VALID_DEFAULT 0x0
+	/*[field] SMAC_VALID*/
+	#define PPPOE_SESSION_EXT_SMAC_VALID
+	#define PPPOE_SESSION_EXT_SMAC_VALID_OFFSET  3
+	#define PPPOE_SESSION_EXT_SMAC_VALID_LEN     1
+	#define PPPOE_SESSION_EXT_SMAC_VALID_DEFAULT 0x0
+	/*[field] SMAC*/
+	#define PPPOE_SESSION_EXT_SMAC
+	#define PPPOE_SESSION_EXT_SMAC_OFFSET  16
+	#define PPPOE_SESSION_EXT_SMAC_LEN     16
+	#define PPPOE_SESSION_EXT_SMAC_DEFAULT 0x0
+
+struct pppoe_session_ext {
+	a_uint32_t  l3_if_valid:1;
+	a_uint32_t  mc_valid:1;
+	a_uint32_t  uc_valid:1;
+	a_uint32_t  smac_valid:1;
+	a_uint32_t  _reserved0:12;
+	a_uint32_t  smac:16;
+};
+
+union pppoe_session_ext_u {
+	a_uint32_t val;
+	struct pppoe_session_ext bf;
+};
+
+/*[register] PPPOE_SESSION_EXT1*/
+#define PPPOE_SESSION_EXT1
+#define PPPOE_SESSION_EXT1_ADDRESS 0xca0
+#define PPPOE_SESSION_EXT1_NUM     16
+#define PPPOE_SESSION_EXT1_INC     0x4
+#define PPPOE_SESSION_EXT1_TYPE    REG_TYPE_RW
+#define PPPOE_SESSION_EXT1_DEFAULT 0x0
+	/*[field] SMAC*/
+	#define PPPOE_SESSION_EXT1_SMAC
+	#define PPPOE_SESSION_EXT1_SMAC_OFFSET  0
+	#define PPPOE_SESSION_EXT1_SMAC_LEN     32
+	#define PPPOE_SESSION_EXT1_SMAC_DEFAULT 0x0
+
+struct pppoe_session_ext1 {
+	a_uint32_t  smac:32;
+};
+
+union pppoe_session_ext1_u {
+	a_uint32_t val;
+	struct pppoe_session_ext1 bf;
+};
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_qm.h b/qca-ssdk/include/hsl/hppe/hppe_qm.h
new file mode 100755
index 0000000..383a07c
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_qm.h
@@ -0,0 +1,3811 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_QM_H_
+#define _HPPE_QM_H_
+
+#define MCAST_PRIORITY_MAP0_MAX_ENTRY	16
+#define MCAST_PRIORITY_MAP1_MAX_ENTRY	16
+#define MCAST_PRIORITY_MAP2_MAX_ENTRY	16
+#define MCAST_PRIORITY_MAP3_MAX_ENTRY	16
+#define MCAST_PRIORITY_MAP4_MAX_ENTRY	16
+#define MCAST_PRIORITY_MAP5_MAX_ENTRY	16
+#define MCAST_PRIORITY_MAP6_MAX_ENTRY	16
+#define MCAST_PRIORITY_MAP7_MAX_ENTRY	16
+#define UQ_AGG_PROFILE_CFG_MAX_ENTRY	8
+#define MQ_AGG_PROFILE_CFG_MAX_ENTRY	8
+#define GRP_AGG_PROFILE_CFG_MAX_ENTRY	4
+#define UQ_AGG_IN_PROFILE_CNT_MAX_ENTRY	8
+#define UQ_AGG_OUT_PROFILE_CNT_MAX_ENTRY	8
+#define MQ_AGG_IN_PROFILE_CNT_MAX_ENTRY	8
+#define MQ_AGG_OUT_PROFILE_CNT_MAX_ENTRY	8
+#define GRP_AGG_IN_PROFILE_CNT_MAX_ENTRY	4
+#define GRP_AGG_OUT_PROFILE_CNT_MAX_ENTRY	4
+#define UCAST_QUEUE_MAP_TBL_MAX_ENTRY	3072
+#define UCAST_HASH_MAP_TBL_MAX_ENTRY	4096
+#define UCAST_PRIORITY_MAP_TBL_MAX_ENTRY	256
+#define MCAST_QUEUE_MAP_TBL_MAX_ENTRY	256
+#define AC_MSEQ_TBL_MAX_ENTRY	256
+#define AC_UNI_QUEUE_CFG_TBL_MAX_ENTRY	256
+#define AC_MUL_QUEUE_CFG_TBL_MAX_ENTRY	44
+#define AC_GRP_CFG_TBL_MAX_ENTRY	4
+#define AC_UNI_QUEUE_CNT_TBL_MAX_ENTRY	256
+#define AC_MUL_QUEUE_CNT_TBL_MAX_ENTRY	44
+#define AC_GRP_CNT_TBL_MAX_ENTRY	4
+#define AC_UNI_QUEUE_DROP_STATE_TBL_MAX_ENTRY	256
+#define AC_MUL_QUEUE_DROP_STATE_TBL_MAX_ENTRY	44
+#define AC_GRP_DROP_STATE_TBL_MAX_ENTRY	4
+#define OQ_ENQ_OPR_TBL_MAX_ENTRY	300
+#define OQ_DEQ_OPR_TBL_MAX_ENTRY	300
+#define OQ_HEAD_UNI_TBL_MAX_ENTRY	256
+#define OQ_HEAD_MUL_TBL_MAX_ENTRY	44
+#define OQ_LL_UNI_TBL_MAX_ENTRY	2048
+#define OQ_LL_MUL_P0_TBL_MAX_ENTRY	2048
+#define OQ_LL_MUL_P1_TBL_MAX_ENTRY	2048
+#define OQ_LL_MUL_P2_TBL_MAX_ENTRY	2048
+#define OQ_LL_MUL_P3_TBL_MAX_ENTRY	2048
+#define OQ_LL_MUL_P4_TBL_MAX_ENTRY	2048
+#define OQ_LL_MUL_P5_TBL_MAX_ENTRY	2048
+#define OQ_LL_MUL_P6_TBL_MAX_ENTRY	2048
+#define OQ_LL_MUL_P7_TBL_MAX_ENTRY	2048
+#define PKT_DESP_TBL_MAX_ENTRY	2048
+#define UNI_DROP_CNT_TBL_MAX_ENTRY	1536
+#define MUL_P0_DROP_CNT_TBL_MAX_ENTRY	48
+#define MUL_P1_DROP_CNT_TBL_MAX_ENTRY	12
+#define MUL_P2_DROP_CNT_TBL_MAX_ENTRY	12
+#define MUL_P3_DROP_CNT_TBL_MAX_ENTRY	12
+#define MUL_P4_DROP_CNT_TBL_MAX_ENTRY	12
+#define MUL_P5_DROP_CNT_TBL_MAX_ENTRY	12
+#define MUL_P6_DROP_CNT_TBL_MAX_ENTRY	12
+#define MUL_P7_DROP_CNT_TBL_MAX_ENTRY	12
+#define UQ_AGG_PROFILE_MAP_MAX_ENTRY	256
+#define QUEUE_TX_COUNTER_TBL_MAX_ENTRY	300
+
+sw_error_t
+hppe_queue_tx_counter_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union queue_tx_counter_tbl_u *value);
+
+sw_error_t
+hppe_queue_tx_counter_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union queue_tx_counter_tbl_u *value);
+
+sw_error_t
+hppe_flush_cfg_get(
+		a_uint32_t dev_id,
+		union flush_cfg_u *value);
+
+sw_error_t
+hppe_flush_cfg_set(
+		a_uint32_t dev_id,
+		union flush_cfg_u *value);
+
+sw_error_t
+hppe_in_mirror_priority_ctrl_get(
+		a_uint32_t dev_id,
+		union in_mirror_priority_ctrl_u *value);
+
+sw_error_t
+hppe_in_mirror_priority_ctrl_set(
+		a_uint32_t dev_id,
+		union in_mirror_priority_ctrl_u *value);
+
+sw_error_t
+hppe_eg_mirror_priority_ctrl_get(
+		a_uint32_t dev_id,
+		union eg_mirror_priority_ctrl_u *value);
+
+sw_error_t
+hppe_eg_mirror_priority_ctrl_set(
+		a_uint32_t dev_id,
+		union eg_mirror_priority_ctrl_u *value);
+
+sw_error_t
+hppe_ucast_default_hash_get(
+		a_uint32_t dev_id,
+		union ucast_default_hash_u *value);
+
+sw_error_t
+hppe_ucast_default_hash_set(
+		a_uint32_t dev_id,
+		union ucast_default_hash_u *value);
+
+sw_error_t
+hppe_spare_reg0_get(
+		a_uint32_t dev_id,
+		union spare_reg0_u *value);
+
+sw_error_t
+hppe_spare_reg0_set(
+		a_uint32_t dev_id,
+		union spare_reg0_u *value);
+
+sw_error_t
+hppe_spare_reg1_get(
+		a_uint32_t dev_id,
+		union spare_reg1_u *value);
+
+sw_error_t
+hppe_spare_reg1_set(
+		a_uint32_t dev_id,
+		union spare_reg1_u *value);
+
+sw_error_t
+hppe_qm_dbg_addr_get(
+		a_uint32_t dev_id,
+		union qm_dbg_addr_u *value);
+
+sw_error_t
+hppe_qm_dbg_addr_set(
+		a_uint32_t dev_id,
+		union qm_dbg_addr_u *value);
+
+sw_error_t
+hppe_qm_dbg_data_get(
+		a_uint32_t dev_id,
+		union qm_dbg_data_u *value);
+
+sw_error_t
+hppe_qm_dbg_data_set(
+		a_uint32_t dev_id,
+		union qm_dbg_data_u *value);
+
+sw_error_t
+hppe_mcast_priority_map0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map0_u *value);
+
+sw_error_t
+hppe_mcast_priority_map0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map0_u *value);
+
+sw_error_t
+hppe_mcast_priority_map1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map1_u *value);
+
+sw_error_t
+hppe_mcast_priority_map1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map1_u *value);
+
+sw_error_t
+hppe_mcast_priority_map2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map2_u *value);
+
+sw_error_t
+hppe_mcast_priority_map2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map2_u *value);
+
+sw_error_t
+hppe_mcast_priority_map3_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map3_u *value);
+
+sw_error_t
+hppe_mcast_priority_map3_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map3_u *value);
+
+sw_error_t
+hppe_mcast_priority_map4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map4_u *value);
+
+sw_error_t
+hppe_mcast_priority_map4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map4_u *value);
+
+sw_error_t
+hppe_mcast_priority_map5_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map5_u *value);
+
+sw_error_t
+hppe_mcast_priority_map5_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map5_u *value);
+
+sw_error_t
+hppe_mcast_priority_map6_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map6_u *value);
+
+sw_error_t
+hppe_mcast_priority_map6_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map6_u *value);
+
+sw_error_t
+hppe_mcast_priority_map7_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map7_u *value);
+
+sw_error_t
+hppe_mcast_priority_map7_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map7_u *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_get(
+		a_uint32_t dev_id,
+		union agg_profile_cnt_en_u *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_set(
+		a_uint32_t dev_id,
+		union agg_profile_cnt_en_u *value);
+
+sw_error_t
+hppe_uq_agg_profile_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_profile_cfg_u *value);
+
+sw_error_t
+hppe_uq_agg_profile_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_profile_cfg_u *value);
+
+sw_error_t
+hppe_mq_agg_profile_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mq_agg_profile_cfg_u *value);
+
+sw_error_t
+hppe_mq_agg_profile_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mq_agg_profile_cfg_u *value);
+
+sw_error_t
+hppe_grp_agg_profile_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_agg_profile_cfg_u *value);
+
+sw_error_t
+hppe_grp_agg_profile_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_agg_profile_cfg_u *value);
+
+sw_error_t
+hppe_uq_agg_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_in_profile_cnt_u *value);
+
+sw_error_t
+hppe_uq_agg_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_in_profile_cnt_u *value);
+
+sw_error_t
+hppe_uq_agg_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_out_profile_cnt_u *value);
+
+sw_error_t
+hppe_uq_agg_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_out_profile_cnt_u *value);
+
+sw_error_t
+hppe_mq_agg_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mq_agg_in_profile_cnt_u *value);
+
+sw_error_t
+hppe_mq_agg_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mq_agg_in_profile_cnt_u *value);
+
+sw_error_t
+hppe_mq_agg_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mq_agg_out_profile_cnt_u *value);
+
+sw_error_t
+hppe_mq_agg_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mq_agg_out_profile_cnt_u *value);
+
+sw_error_t
+hppe_grp_agg_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_agg_in_profile_cnt_u *value);
+
+sw_error_t
+hppe_grp_agg_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_agg_in_profile_cnt_u *value);
+
+sw_error_t
+hppe_grp_agg_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_agg_out_profile_cnt_u *value);
+
+sw_error_t
+hppe_grp_agg_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_agg_out_profile_cnt_u *value);
+
+sw_error_t
+hppe_ucast_queue_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ucast_queue_map_tbl_u *value);
+
+sw_error_t
+hppe_ucast_queue_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ucast_queue_map_tbl_u *value);
+
+sw_error_t
+hppe_ucast_hash_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ucast_hash_map_tbl_u *value);
+
+sw_error_t
+hppe_ucast_hash_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ucast_hash_map_tbl_u *value);
+
+sw_error_t
+hppe_ucast_priority_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ucast_priority_map_tbl_u *value);
+
+sw_error_t
+hppe_ucast_priority_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ucast_priority_map_tbl_u *value);
+
+sw_error_t
+hppe_mcast_queue_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_queue_map_tbl_u *value);
+
+sw_error_t
+hppe_mcast_queue_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_queue_map_tbl_u *value);
+
+sw_error_t
+hppe_ac_mseq_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mseq_tbl_u *value);
+
+sw_error_t
+hppe_ac_mseq_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mseq_tbl_u *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_uni_queue_cfg_tbl_u *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_uni_queue_cfg_tbl_u *value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mul_queue_cfg_tbl_u *value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mul_queue_cfg_tbl_u *value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_grp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_grp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_ac_uni_queue_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_uni_queue_cnt_tbl_u *value);
+
+sw_error_t
+hppe_ac_uni_queue_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_uni_queue_cnt_tbl_u *value);
+
+sw_error_t
+hppe_ac_mul_queue_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mul_queue_cnt_tbl_u *value);
+
+sw_error_t
+hppe_ac_mul_queue_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mul_queue_cnt_tbl_u *value);
+
+sw_error_t
+hppe_ac_grp_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_grp_cnt_tbl_u *value);
+
+sw_error_t
+hppe_ac_grp_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_grp_cnt_tbl_u *value);
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_uni_queue_drop_state_tbl_u *value);
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_uni_queue_drop_state_tbl_u *value);
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mul_queue_drop_state_tbl_u *value);
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mul_queue_drop_state_tbl_u *value);
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_grp_drop_state_tbl_u *value);
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_grp_drop_state_tbl_u *value);
+
+sw_error_t
+hppe_oq_enq_opr_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_enq_opr_tbl_u *value);
+
+sw_error_t
+hppe_oq_enq_opr_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_enq_opr_tbl_u *value);
+
+sw_error_t
+hppe_oq_deq_opr_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_deq_opr_tbl_u *value);
+
+sw_error_t
+hppe_oq_deq_opr_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_deq_opr_tbl_u *value);
+
+sw_error_t
+hppe_oq_head_uni_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_head_uni_tbl_u *value);
+
+sw_error_t
+hppe_oq_head_uni_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_head_uni_tbl_u *value);
+
+sw_error_t
+hppe_oq_head_mul_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_head_mul_tbl_u *value);
+
+sw_error_t
+hppe_oq_head_mul_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_head_mul_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_uni_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_uni_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_uni_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_uni_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p0_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p0_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p1_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p1_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p2_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p2_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p3_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p3_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p4_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p4_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p5_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p5_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p6_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p6_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p7_tbl_u *value);
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p7_tbl_u *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pkt_desp_tbl_u *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pkt_desp_tbl_u *value);
+
+sw_error_t
+hppe_uni_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uni_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_uni_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uni_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p0_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p0_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p0_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p0_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p1_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p1_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p1_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p1_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p2_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p2_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p2_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p2_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p3_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p3_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p3_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p3_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p4_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p4_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p4_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p4_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p5_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p5_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p5_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p5_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p6_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p6_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p6_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p6_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p7_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p7_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_mul_p7_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p7_drop_cnt_tbl_u *value);
+
+sw_error_t
+hppe_uq_agg_profile_map_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_profile_map_u *value);
+
+sw_error_t
+hppe_uq_agg_profile_map_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_profile_map_u *value);
+
+sw_error_t
+hppe_flush_cfg_flush_busy_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flush_cfg_flush_busy_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flush_cfg_flush_qid_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flush_cfg_flush_qid_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flush_cfg_flush_dst_port_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flush_cfg_flush_dst_port_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flush_cfg_flush_all_queues_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flush_cfg_flush_all_queues_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flush_cfg_flush_wt_time_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flush_cfg_flush_wt_time_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_flush_cfg_flush_status_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_flush_cfg_flush_status_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_in_mirror_priority_ctrl_priority_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_in_mirror_priority_ctrl_priority_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_eg_mirror_priority_ctrl_priority_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_eg_mirror_priority_ctrl_priority_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_ucast_default_hash_hash_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ucast_default_hash_hash_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_spare_reg0_spare_reg0_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_spare_reg0_spare_reg0_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_spare_reg1_spare_reg1_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_spare_reg1_spare_reg1_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_qm_dbg_addr_dbg_addr_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_qm_dbg_addr_dbg_addr_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_qm_dbg_data_dbg_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_qm_dbg_data_dbg_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_mcast_priority_map0_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mcast_priority_map0_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mcast_priority_map1_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mcast_priority_map1_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mcast_priority_map2_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mcast_priority_map2_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mcast_priority_map3_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mcast_priority_map3_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mcast_priority_map4_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mcast_priority_map4_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mcast_priority_map5_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mcast_priority_map5_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mcast_priority_map6_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mcast_priority_map6_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mcast_priority_map7_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mcast_priority_map7_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p2_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p2_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_1_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_1_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p0_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p0_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_1_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_1_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_0_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_0_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p6_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p6_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_3_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_3_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p4_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p4_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_2_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_2_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_5_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_5_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_6_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_6_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_3_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_3_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_2_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_2_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_4_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_4_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p7_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p7_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_7_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_7_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_global_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_global_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p5_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p5_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p1_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p1_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_0_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_0_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p3_en_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p3_en_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_uq_agg_profile_cfg_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uq_agg_profile_cfg_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mq_agg_profile_cfg_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mq_agg_profile_cfg_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_grp_agg_profile_cfg_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_grp_agg_profile_cfg_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uq_agg_in_profile_cnt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uq_agg_in_profile_cnt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uq_agg_out_profile_cnt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uq_agg_out_profile_cnt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mq_agg_in_profile_cnt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mq_agg_in_profile_cnt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mq_agg_out_profile_cnt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mq_agg_out_profile_cnt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_grp_agg_in_profile_cnt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_grp_agg_in_profile_cnt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_grp_agg_out_profile_cnt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_grp_agg_out_profile_cnt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ucast_queue_map_tbl_profile_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ucast_queue_map_tbl_profile_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ucast_queue_map_tbl_queue_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ucast_queue_map_tbl_queue_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ucast_hash_map_tbl_hash_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ucast_hash_map_tbl_hash_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ucast_priority_map_tbl_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ucast_priority_map_tbl_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mcast_queue_map_tbl_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mcast_queue_map_tbl_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mseq_tbl_ac_mseq_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mseq_tbl_ac_mseq_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_max_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_max_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_wred_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_wred_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_ac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_ac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_red_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_red_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_grp_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_grp_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_color_aware_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_color_aware_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_yel_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_yel_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_min_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_min_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_weight_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_weight_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_dynamic_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_dynamic_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_max_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_max_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_pre_alloc_limit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_pre_alloc_limit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_force_ac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_force_ac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_min_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_min_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_grn_min_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_grn_min_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_ceiling_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_ceiling_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_grn_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_grn_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_ac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_ac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_red_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_red_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_grp_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_grp_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_color_aware_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_color_aware_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_yel_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_yel_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_pre_alloc_limit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_pre_alloc_limit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_force_ac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_force_ac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_shared_ceiling_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_shared_ceiling_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_grn_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_grn_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_yel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_yel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_red_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_red_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_grn_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_grn_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_dp_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_dp_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_cfg_ac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_cfg_ac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_palloc_limit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_palloc_limit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_cfg_color_aware_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_cfg_color_aware_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_red_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_red_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_yel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_yel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_cfg_force_ac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_cfg_force_ac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_yel_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_yel_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_red_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_red_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_limit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_limit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_cnt_tbl_ac_uni_queue_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_cnt_tbl_ac_uni_queue_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_cnt_tbl_ac_mul_queue_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_cnt_tbl_ac_mul_queue_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_cnt_tbl_ac_grp_alloc_used_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_cnt_tbl_ac_grp_alloc_used_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_cnt_tbl_ac_grp_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_cnt_tbl_ac_grp_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_red_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_red_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_red_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_red_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_yel_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_yel_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_grn_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_grn_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_yel_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_yel_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_grn_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_grn_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_red_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_red_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_red_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_red_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_yel_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_yel_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_grn_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_grn_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_yel_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_yel_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_grn_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_grn_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_red_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_red_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_red_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_red_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_yel_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_yel_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_grn_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_grn_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_yel_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_yel_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_grn_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_grn_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_enq_opr_tbl_enq_disable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_enq_opr_tbl_enq_disable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_deq_opr_tbl_deq_drop_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_deq_opr_tbl_deq_drop_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_head_uni_tbl_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_head_uni_tbl_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_head_uni_tbl_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_head_uni_tbl_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_head_uni_tbl_empty_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_head_uni_tbl_empty_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_head_mul_tbl_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_head_mul_tbl_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_head_mul_tbl_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_head_mul_tbl_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_head_mul_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_head_mul_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_head_mul_tbl_empty_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_head_mul_tbl_empty_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_head_mul_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_head_mul_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_head_mul_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_head_mul_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_uni_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_uni_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_route_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_route_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_cpcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_cpcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_pkt_l3_edit_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_pkt_l3_edit_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_ctag_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_ctag_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_fake_mac_header_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_fake_mac_header_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_acl_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_acl_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_l4_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_l4_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_svid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_svid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_sdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_sdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_fc_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_fc_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_packet_length_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_packet_length_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_rx_ts_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_rx_ts_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ts_dir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ts_dir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_chg_port_vp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_chg_port_vp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_one_enq_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_one_enq_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_fc_grp_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_fc_grp_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_fake_l2_prot_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_fake_l2_prot_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_org_src_port_vp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_org_src_port_vp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_hash_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_hash_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_stag_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_stag_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_service_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_service_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_rx_ptp_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_rx_ptp_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_mac_da_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_mac_da_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_cpu_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_cpu_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_eg_vlan_tag_fmt_bypass_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_eg_vlan_tag_fmt_bypass_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_cvid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_cvid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_eg_vlan_xlt_bypass_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_eg_vlan_xlt_bypass_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_hash_value_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_hash_value_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_stag_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_stag_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_dst_l3_if_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_dst_l3_if_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_cdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_cdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_edma_vp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_edma_vp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ac_group_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ac_group_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_vp_tx_cnt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_vp_tx_cnt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_src_port_vp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_src_port_vp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_nat_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_nat_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_dscp_update_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_dscp_update_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_pppoe_strip_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_pppoe_strip_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_snap_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_snap_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_vsi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_vsi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_pkt_l2_edit_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_pkt_l2_edit_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_tx_ptp_tag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_tx_ptp_tag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_dp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_dp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_src_pn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_src_pn_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_tx_ts_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_tx_ts_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_l4_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_l4_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ttl_update_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ttl_update_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_napt_port_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_napt_port_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_napt_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_napt_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_copy_cpu_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_copy_cpu_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ttl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ttl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_l3_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_l3_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_rsv0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_rsv0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_next_header_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_next_header_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_acl_index_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_acl_index_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_rx_ts_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_rx_ts_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_dscp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_dscp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_acl_index_toggle_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_acl_index_toggle_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ctag_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ctag_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_toggle_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_toggle_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_tx_os_correction_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_tx_os_correction_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_spcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_int_spcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_pppoe_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_pppoe_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_l3_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_l3_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pkt_desp_tbl_vsi_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pkt_desp_tbl_vsi_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uni_drop_cnt_tbl_uni_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_uni_drop_cnt_tbl_uni_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_uni_drop_cnt_tbl_uni_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uni_drop_cnt_tbl_uni_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_uq_agg_profile_map_qid_2_agg_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uq_agg_profile_map_qid_2_agg_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uq_agg_profile_map_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uq_agg_profile_map_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_queue_tx_counter_tbl_tx_bytes_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_queue_tx_counter_tbl_tx_bytes_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_queue_tx_counter_tbl_tx_packets_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_queue_tx_counter_tbl_tx_packets_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_qm_reg.h b/qca-ssdk/include/hsl/hppe/hppe_qm_reg.h
new file mode 100755
index 0000000..504d3c2
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_qm_reg.h
@@ -0,0 +1,2748 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_QM_REG_H
+#define HPPE_QM_REG_H
+
+/*[register] FLUSH_CFG*/
+#define FLUSH_CFG
+#define FLUSH_CFG_ADDRESS 0x0
+#define FLUSH_CFG_NUM     1
+#define FLUSH_CFG_INC     0x4
+#define FLUSH_CFG_TYPE    REG_TYPE_RW
+#define FLUSH_CFG_DEFAULT 0x80000
+	/*[field] FLUSH_QID*/
+	#define FLUSH_CFG_FLUSH_QID
+	#define FLUSH_CFG_FLUSH_QID_OFFSET  0
+	#define FLUSH_CFG_FLUSH_QID_LEN     9
+	#define FLUSH_CFG_FLUSH_QID_DEFAULT 0x0
+	/*[field] FLUSH_STATUS*/
+	#define FLUSH_CFG_FLUSH_STATUS
+	#define FLUSH_CFG_FLUSH_STATUS_OFFSET  10
+	#define FLUSH_CFG_FLUSH_STATUS_LEN     1
+	#define FLUSH_CFG_FLUSH_STATUS_DEFAULT 0x0
+	/*[field] FLUSH_WT_TIME*/
+	#define FLUSH_CFG_FLUSH_WT_TIME
+	#define FLUSH_CFG_FLUSH_WT_TIME_OFFSET  11
+	#define FLUSH_CFG_FLUSH_WT_TIME_LEN     10
+	#define FLUSH_CFG_FLUSH_WT_TIME_DEFAULT 0x100
+	/*[field] FLUSH_DST_PORT*/
+	#define FLUSH_CFG_FLUSH_DST_PORT
+	#define FLUSH_CFG_FLUSH_DST_PORT_OFFSET  21
+	#define FLUSH_CFG_FLUSH_DST_PORT_LEN     3
+	#define FLUSH_CFG_FLUSH_DST_PORT_DEFAULT 0x0
+	/*[field] FLUSH_ALL_QUEUES*/
+	#define FLUSH_CFG_FLUSH_ALL_QUEUES
+	#define FLUSH_CFG_FLUSH_ALL_QUEUES_OFFSET  24
+	#define FLUSH_CFG_FLUSH_ALL_QUEUES_LEN     1
+	#define FLUSH_CFG_FLUSH_ALL_QUEUES_DEFAULT 0x0
+	/*[field] FLUSH_BUSY*/
+	#define FLUSH_CFG_FLUSH_BUSY
+	#define FLUSH_CFG_FLUSH_BUSY_OFFSET  31
+	#define FLUSH_CFG_FLUSH_BUSY_LEN     1
+	#define FLUSH_CFG_FLUSH_BUSY_DEFAULT 0x0
+
+struct flush_cfg {
+	a_uint32_t  flush_qid:9;
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  flush_status:1;
+	a_uint32_t  flush_wt_time:10;
+	a_uint32_t  flush_dst_port:3;
+	a_uint32_t  flush_all_queues:1;
+	a_uint32_t  _reserved1:6;
+	a_uint32_t  flush_busy:1;
+};
+
+union flush_cfg_u {
+	a_uint32_t val;
+	struct flush_cfg bf;
+};
+
+/*[register] IN_MIRROR_PRIORITY_CTRL*/
+#define IN_MIRROR_PRIORITY_CTRL
+#define IN_MIRROR_PRIORITY_CTRL_ADDRESS 0x4
+#define IN_MIRROR_PRIORITY_CTRL_NUM     1
+#define IN_MIRROR_PRIORITY_CTRL_INC     0x4
+#define IN_MIRROR_PRIORITY_CTRL_TYPE    REG_TYPE_RW
+#define IN_MIRROR_PRIORITY_CTRL_DEFAULT 0x0
+	/*[field] PRIORITY*/
+	#define IN_MIRROR_PRIORITY_CTRL_PRIORITY
+	#define IN_MIRROR_PRIORITY_CTRL_PRIORITY_OFFSET  0
+	#define IN_MIRROR_PRIORITY_CTRL_PRIORITY_LEN     4
+	#define IN_MIRROR_PRIORITY_CTRL_PRIORITY_DEFAULT 0x0
+
+struct in_mirror_priority_ctrl {
+	a_uint32_t  priority:4;
+	a_uint32_t  _reserved0:28;
+};
+
+union in_mirror_priority_ctrl_u {
+	a_uint32_t val;
+	struct in_mirror_priority_ctrl bf;
+};
+
+/*[register] EG_MIRROR_PRIORITY_CTRL*/
+#define EG_MIRROR_PRIORITY_CTRL
+#define EG_MIRROR_PRIORITY_CTRL_ADDRESS 0x8
+#define EG_MIRROR_PRIORITY_CTRL_NUM     1
+#define EG_MIRROR_PRIORITY_CTRL_INC     0x4
+#define EG_MIRROR_PRIORITY_CTRL_TYPE    REG_TYPE_RW
+#define EG_MIRROR_PRIORITY_CTRL_DEFAULT 0x0
+	/*[field] PRIORITY*/
+	#define EG_MIRROR_PRIORITY_CTRL_PRIORITY
+	#define EG_MIRROR_PRIORITY_CTRL_PRIORITY_OFFSET  0
+	#define EG_MIRROR_PRIORITY_CTRL_PRIORITY_LEN     4
+	#define EG_MIRROR_PRIORITY_CTRL_PRIORITY_DEFAULT 0x0
+
+struct eg_mirror_priority_ctrl {
+	a_uint32_t  priority:4;
+	a_uint32_t  _reserved0:28;
+};
+
+union eg_mirror_priority_ctrl_u {
+	a_uint32_t val;
+	struct eg_mirror_priority_ctrl bf;
+};
+
+/*[register] UCAST_DEFAULT_HASH*/
+#define UCAST_DEFAULT_HASH
+#define UCAST_DEFAULT_HASH_ADDRESS 0x60
+#define UCAST_DEFAULT_HASH_NUM     1
+#define UCAST_DEFAULT_HASH_INC     0x4
+#define UCAST_DEFAULT_HASH_TYPE    REG_TYPE_RW
+#define UCAST_DEFAULT_HASH_DEFAULT 0x0
+	/*[field] HASH*/
+	#define UCAST_DEFAULT_HASH_HASH
+	#define UCAST_DEFAULT_HASH_HASH_OFFSET  0
+	#define UCAST_DEFAULT_HASH_HASH_LEN     8
+	#define UCAST_DEFAULT_HASH_HASH_DEFAULT 0x0
+
+struct ucast_default_hash {
+	a_uint32_t  hash:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union ucast_default_hash_u {
+	a_uint32_t val;
+	struct ucast_default_hash bf;
+};
+
+/*[register] SPARE_REG0*/
+#define SPARE_REG0
+#define SPARE_REG0_ADDRESS 0x70
+#define SPARE_REG0_NUM     1
+#define SPARE_REG0_INC     0x4
+#define SPARE_REG0_TYPE    REG_TYPE_RW
+#define SPARE_REG0_DEFAULT 0x0
+	/*[field] SPARE_REG0*/
+	#define SPARE_REG0_SPARE_REG0
+	#define SPARE_REG0_SPARE_REG0_OFFSET  0
+	#define SPARE_REG0_SPARE_REG0_LEN     32
+	#define SPARE_REG0_SPARE_REG0_DEFAULT 0x0
+
+struct spare_reg0 {
+	a_uint32_t  spare_reg0:32;
+};
+
+union spare_reg0_u {
+	a_uint32_t val;
+	struct spare_reg0 bf;
+};
+
+/*[register] SPARE_REG1*/
+#define SPARE_REG1
+#define SPARE_REG1_ADDRESS 0x74
+#define SPARE_REG1_NUM     1
+#define SPARE_REG1_INC     0x4
+#define SPARE_REG1_TYPE    REG_TYPE_RW
+#define SPARE_REG1_DEFAULT 0x0
+	/*[field] SPARE_REG1*/
+	#define SPARE_REG1_SPARE_REG1
+	#define SPARE_REG1_SPARE_REG1_OFFSET  0
+	#define SPARE_REG1_SPARE_REG1_LEN     32
+	#define SPARE_REG1_SPARE_REG1_DEFAULT 0x0
+
+struct spare_reg1 {
+	a_uint32_t  spare_reg1:32;
+};
+
+union spare_reg1_u {
+	a_uint32_t val;
+	struct spare_reg1 bf;
+};
+
+/*[register] QM_DBG_ADDR*/
+#define QM_DBG_ADDR
+#define QM_DBG_ADDR_ADDRESS 0x80
+#define QM_DBG_ADDR_NUM     1
+#define QM_DBG_ADDR_INC     0x4
+#define QM_DBG_ADDR_TYPE    REG_TYPE_RW
+#define QM_DBG_ADDR_DEFAULT 0x0
+	/*[field] DBG_ADDR*/
+	#define QM_DBG_ADDR_DBG_ADDR
+	#define QM_DBG_ADDR_DBG_ADDR_OFFSET  0
+	#define QM_DBG_ADDR_DBG_ADDR_LEN     8
+	#define QM_DBG_ADDR_DBG_ADDR_DEFAULT 0x0
+
+struct qm_dbg_addr {
+	a_uint32_t  dbg_addr:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union qm_dbg_addr_u {
+	a_uint32_t val;
+	struct qm_dbg_addr bf;
+};
+
+/*[register] QM_DBG_DATA*/
+#define QM_DBG_DATA
+#define QM_DBG_DATA_ADDRESS 0x84
+#define QM_DBG_DATA_NUM     1
+#define QM_DBG_DATA_INC     0x4
+#define QM_DBG_DATA_TYPE    REG_TYPE_RO
+#define QM_DBG_DATA_DEFAULT 0x0
+	/*[field] DBG_DATA*/
+	#define QM_DBG_DATA_DBG_DATA
+	#define QM_DBG_DATA_DBG_DATA_OFFSET  0
+	#define QM_DBG_DATA_DBG_DATA_LEN     32
+	#define QM_DBG_DATA_DBG_DATA_DEFAULT 0x0
+
+struct qm_dbg_data {
+	a_uint32_t  dbg_data:32;
+};
+
+union qm_dbg_data_u {
+	a_uint32_t val;
+	struct qm_dbg_data bf;
+};
+
+/*[register] MCAST_PRIORITY_MAP0*/
+#define MCAST_PRIORITY_MAP0
+#define MCAST_PRIORITY_MAP0_ADDRESS 0x100
+#define MCAST_PRIORITY_MAP0_NUM     16
+#define MCAST_PRIORITY_MAP0_INC     0x4
+#define MCAST_PRIORITY_MAP0_TYPE    REG_TYPE_RW
+#define MCAST_PRIORITY_MAP0_DEFAULT 0x0
+	/*[field] CLASS*/
+	#define MCAST_PRIORITY_MAP0_CLASS
+	#define MCAST_PRIORITY_MAP0_CLASS_OFFSET  0
+	#define MCAST_PRIORITY_MAP0_CLASS_LEN     4
+	#define MCAST_PRIORITY_MAP0_CLASS_DEFAULT 0x0
+
+struct mcast_priority_map0 {
+	a_uint32_t  class:4;
+	a_uint32_t  _reserved0:28;
+};
+
+union mcast_priority_map0_u {
+	a_uint32_t val;
+	struct mcast_priority_map0 bf;
+};
+
+/*[register] MCAST_PRIORITY_MAP1*/
+#define MCAST_PRIORITY_MAP1
+#define MCAST_PRIORITY_MAP1_ADDRESS 0x140
+#define MCAST_PRIORITY_MAP1_NUM     16
+#define MCAST_PRIORITY_MAP1_INC     0x4
+#define MCAST_PRIORITY_MAP1_TYPE    REG_TYPE_RW
+#define MCAST_PRIORITY_MAP1_DEFAULT 0x0
+	/*[field] CLASS*/
+	#define MCAST_PRIORITY_MAP1_CLASS
+	#define MCAST_PRIORITY_MAP1_CLASS_OFFSET  0
+	#define MCAST_PRIORITY_MAP1_CLASS_LEN     2
+	#define MCAST_PRIORITY_MAP1_CLASS_DEFAULT 0x0
+
+struct mcast_priority_map1 {
+	a_uint32_t  class:2;
+	a_uint32_t  _reserved0:30;
+};
+
+union mcast_priority_map1_u {
+	a_uint32_t val;
+	struct mcast_priority_map1 bf;
+};
+
+/*[register] MCAST_PRIORITY_MAP2*/
+#define MCAST_PRIORITY_MAP2
+#define MCAST_PRIORITY_MAP2_ADDRESS 0x180
+#define MCAST_PRIORITY_MAP2_NUM     16
+#define MCAST_PRIORITY_MAP2_INC     0x4
+#define MCAST_PRIORITY_MAP2_TYPE    REG_TYPE_RW
+#define MCAST_PRIORITY_MAP2_DEFAULT 0x0
+	/*[field] CLASS*/
+	#define MCAST_PRIORITY_MAP2_CLASS
+	#define MCAST_PRIORITY_MAP2_CLASS_OFFSET  0
+	#define MCAST_PRIORITY_MAP2_CLASS_LEN     2
+	#define MCAST_PRIORITY_MAP2_CLASS_DEFAULT 0x0
+
+struct mcast_priority_map2 {
+	a_uint32_t  class:2;
+	a_uint32_t  _reserved0:30;
+};
+
+union mcast_priority_map2_u {
+	a_uint32_t val;
+	struct mcast_priority_map2 bf;
+};
+
+/*[register] MCAST_PRIORITY_MAP3*/
+#define MCAST_PRIORITY_MAP3
+#define MCAST_PRIORITY_MAP3_ADDRESS 0x1c0
+#define MCAST_PRIORITY_MAP3_NUM     16
+#define MCAST_PRIORITY_MAP3_INC     0x4
+#define MCAST_PRIORITY_MAP3_TYPE    REG_TYPE_RW
+#define MCAST_PRIORITY_MAP3_DEFAULT 0x0
+	/*[field] CLASS*/
+	#define MCAST_PRIORITY_MAP3_CLASS
+	#define MCAST_PRIORITY_MAP3_CLASS_OFFSET  0
+	#define MCAST_PRIORITY_MAP3_CLASS_LEN     2
+	#define MCAST_PRIORITY_MAP3_CLASS_DEFAULT 0x0
+
+struct mcast_priority_map3 {
+	a_uint32_t  class:2;
+	a_uint32_t  _reserved0:30;
+};
+
+union mcast_priority_map3_u {
+	a_uint32_t val;
+	struct mcast_priority_map3 bf;
+};
+
+/*[register] MCAST_PRIORITY_MAP4*/
+#define MCAST_PRIORITY_MAP4
+#define MCAST_PRIORITY_MAP4_ADDRESS 0x200
+#define MCAST_PRIORITY_MAP4_NUM     16
+#define MCAST_PRIORITY_MAP4_INC     0x4
+#define MCAST_PRIORITY_MAP4_TYPE    REG_TYPE_RW
+#define MCAST_PRIORITY_MAP4_DEFAULT 0x0
+	/*[field] CLASS*/
+	#define MCAST_PRIORITY_MAP4_CLASS
+	#define MCAST_PRIORITY_MAP4_CLASS_OFFSET  0
+	#define MCAST_PRIORITY_MAP4_CLASS_LEN     2
+	#define MCAST_PRIORITY_MAP4_CLASS_DEFAULT 0x0
+
+struct mcast_priority_map4 {
+	a_uint32_t  class:2;
+	a_uint32_t  _reserved0:30;
+};
+
+union mcast_priority_map4_u {
+	a_uint32_t val;
+	struct mcast_priority_map4 bf;
+};
+
+/*[register] MCAST_PRIORITY_MAP5*/
+#define MCAST_PRIORITY_MAP5
+#define MCAST_PRIORITY_MAP5_ADDRESS 0x240
+#define MCAST_PRIORITY_MAP5_NUM     16
+#define MCAST_PRIORITY_MAP5_INC     0x4
+#define MCAST_PRIORITY_MAP5_TYPE    REG_TYPE_RW
+#define MCAST_PRIORITY_MAP5_DEFAULT 0x0
+	/*[field] CLASS*/
+	#define MCAST_PRIORITY_MAP5_CLASS
+	#define MCAST_PRIORITY_MAP5_CLASS_OFFSET  0
+	#define MCAST_PRIORITY_MAP5_CLASS_LEN     2
+	#define MCAST_PRIORITY_MAP5_CLASS_DEFAULT 0x0
+
+struct mcast_priority_map5 {
+	a_uint32_t  class:2;
+	a_uint32_t  _reserved0:30;
+};
+
+union mcast_priority_map5_u {
+	a_uint32_t val;
+	struct mcast_priority_map5 bf;
+};
+
+/*[register] MCAST_PRIORITY_MAP6*/
+#define MCAST_PRIORITY_MAP6
+#define MCAST_PRIORITY_MAP6_ADDRESS 0x280
+#define MCAST_PRIORITY_MAP6_NUM     16
+#define MCAST_PRIORITY_MAP6_INC     0x4
+#define MCAST_PRIORITY_MAP6_TYPE    REG_TYPE_RW
+#define MCAST_PRIORITY_MAP6_DEFAULT 0x0
+	/*[field] CLASS*/
+	#define MCAST_PRIORITY_MAP6_CLASS
+	#define MCAST_PRIORITY_MAP6_CLASS_OFFSET  0
+	#define MCAST_PRIORITY_MAP6_CLASS_LEN     2
+	#define MCAST_PRIORITY_MAP6_CLASS_DEFAULT 0x0
+
+struct mcast_priority_map6 {
+	a_uint32_t  class:2;
+	a_uint32_t  _reserved0:30;
+};
+
+union mcast_priority_map6_u {
+	a_uint32_t val;
+	struct mcast_priority_map6 bf;
+};
+
+/*[register] MCAST_PRIORITY_MAP7*/
+#define MCAST_PRIORITY_MAP7
+#define MCAST_PRIORITY_MAP7_ADDRESS 0x2c0
+#define MCAST_PRIORITY_MAP7_NUM     16
+#define MCAST_PRIORITY_MAP7_INC     0x4
+#define MCAST_PRIORITY_MAP7_TYPE    REG_TYPE_RW
+#define MCAST_PRIORITY_MAP7_DEFAULT 0x0
+	/*[field] CLASS*/
+	#define MCAST_PRIORITY_MAP7_CLASS
+	#define MCAST_PRIORITY_MAP7_CLASS_OFFSET  0
+	#define MCAST_PRIORITY_MAP7_CLASS_LEN     2
+	#define MCAST_PRIORITY_MAP7_CLASS_DEFAULT 0x0
+
+struct mcast_priority_map7 {
+	a_uint32_t  class:2;
+	a_uint32_t  _reserved0:30;
+};
+
+union mcast_priority_map7_u {
+	a_uint32_t val;
+	struct mcast_priority_map7 bf;
+};
+
+/*[register] AGG_PROFILE_CNT_EN*/
+#define AGG_PROFILE_CNT_EN
+#define AGG_PROFILE_CNT_EN_ADDRESS 0x300
+#define AGG_PROFILE_CNT_EN_NUM     1
+#define AGG_PROFILE_CNT_EN_INC     0x4
+#define AGG_PROFILE_CNT_EN_TYPE    REG_TYPE_RW
+#define AGG_PROFILE_CNT_EN_DEFAULT 0xfffff
+	/*[field] UQ_EN_0*/
+	#define AGG_PROFILE_CNT_EN_UQ_EN_0
+	#define AGG_PROFILE_CNT_EN_UQ_EN_0_OFFSET  0
+	#define AGG_PROFILE_CNT_EN_UQ_EN_0_LEN     1
+	#define AGG_PROFILE_CNT_EN_UQ_EN_0_DEFAULT 0x1
+	/*[field] UQ_EN_1*/
+	#define AGG_PROFILE_CNT_EN_UQ_EN_1
+	#define AGG_PROFILE_CNT_EN_UQ_EN_1_OFFSET  1
+	#define AGG_PROFILE_CNT_EN_UQ_EN_1_LEN     1
+	#define AGG_PROFILE_CNT_EN_UQ_EN_1_DEFAULT 0x1
+	/*[field] UQ_EN_2*/
+	#define AGG_PROFILE_CNT_EN_UQ_EN_2
+	#define AGG_PROFILE_CNT_EN_UQ_EN_2_OFFSET  2
+	#define AGG_PROFILE_CNT_EN_UQ_EN_2_LEN     1
+	#define AGG_PROFILE_CNT_EN_UQ_EN_2_DEFAULT 0x1
+	/*[field] UQ_EN_3*/
+	#define AGG_PROFILE_CNT_EN_UQ_EN_3
+	#define AGG_PROFILE_CNT_EN_UQ_EN_3_OFFSET  3
+	#define AGG_PROFILE_CNT_EN_UQ_EN_3_LEN     1
+	#define AGG_PROFILE_CNT_EN_UQ_EN_3_DEFAULT 0x1
+	/*[field] UQ_EN_4*/
+	#define AGG_PROFILE_CNT_EN_UQ_EN_4
+	#define AGG_PROFILE_CNT_EN_UQ_EN_4_OFFSET  4
+	#define AGG_PROFILE_CNT_EN_UQ_EN_4_LEN     1
+	#define AGG_PROFILE_CNT_EN_UQ_EN_4_DEFAULT 0x1
+	/*[field] UQ_EN_5*/
+	#define AGG_PROFILE_CNT_EN_UQ_EN_5
+	#define AGG_PROFILE_CNT_EN_UQ_EN_5_OFFSET  5
+	#define AGG_PROFILE_CNT_EN_UQ_EN_5_LEN     1
+	#define AGG_PROFILE_CNT_EN_UQ_EN_5_DEFAULT 0x1
+	/*[field] UQ_EN_6*/
+	#define AGG_PROFILE_CNT_EN_UQ_EN_6
+	#define AGG_PROFILE_CNT_EN_UQ_EN_6_OFFSET  6
+	#define AGG_PROFILE_CNT_EN_UQ_EN_6_LEN     1
+	#define AGG_PROFILE_CNT_EN_UQ_EN_6_DEFAULT 0x1
+	/*[field] UQ_EN_7*/
+	#define AGG_PROFILE_CNT_EN_UQ_EN_7
+	#define AGG_PROFILE_CNT_EN_UQ_EN_7_OFFSET  7
+	#define AGG_PROFILE_CNT_EN_UQ_EN_7_LEN     1
+	#define AGG_PROFILE_CNT_EN_UQ_EN_7_DEFAULT 0x1
+	/*[field] MQ_P0_EN*/
+	#define AGG_PROFILE_CNT_EN_MQ_P0_EN
+	#define AGG_PROFILE_CNT_EN_MQ_P0_EN_OFFSET  8
+	#define AGG_PROFILE_CNT_EN_MQ_P0_EN_LEN     1
+	#define AGG_PROFILE_CNT_EN_MQ_P0_EN_DEFAULT 0x1
+	/*[field] MQ_P1_EN*/
+	#define AGG_PROFILE_CNT_EN_MQ_P1_EN
+	#define AGG_PROFILE_CNT_EN_MQ_P1_EN_OFFSET  9
+	#define AGG_PROFILE_CNT_EN_MQ_P1_EN_LEN     1
+	#define AGG_PROFILE_CNT_EN_MQ_P1_EN_DEFAULT 0x1
+	/*[field] MQ_P2_EN*/
+	#define AGG_PROFILE_CNT_EN_MQ_P2_EN
+	#define AGG_PROFILE_CNT_EN_MQ_P2_EN_OFFSET  10
+	#define AGG_PROFILE_CNT_EN_MQ_P2_EN_LEN     1
+	#define AGG_PROFILE_CNT_EN_MQ_P2_EN_DEFAULT 0x1
+	/*[field] MQ_P3_EN*/
+	#define AGG_PROFILE_CNT_EN_MQ_P3_EN
+	#define AGG_PROFILE_CNT_EN_MQ_P3_EN_OFFSET  11
+	#define AGG_PROFILE_CNT_EN_MQ_P3_EN_LEN     1
+	#define AGG_PROFILE_CNT_EN_MQ_P3_EN_DEFAULT 0x1
+	/*[field] MQ_P4_EN*/
+	#define AGG_PROFILE_CNT_EN_MQ_P4_EN
+	#define AGG_PROFILE_CNT_EN_MQ_P4_EN_OFFSET  12
+	#define AGG_PROFILE_CNT_EN_MQ_P4_EN_LEN     1
+	#define AGG_PROFILE_CNT_EN_MQ_P4_EN_DEFAULT 0x1
+	/*[field] MQ_P5_EN*/
+	#define AGG_PROFILE_CNT_EN_MQ_P5_EN
+	#define AGG_PROFILE_CNT_EN_MQ_P5_EN_OFFSET  13
+	#define AGG_PROFILE_CNT_EN_MQ_P5_EN_LEN     1
+	#define AGG_PROFILE_CNT_EN_MQ_P5_EN_DEFAULT 0x1
+	/*[field] MQ_P6_EN*/
+	#define AGG_PROFILE_CNT_EN_MQ_P6_EN
+	#define AGG_PROFILE_CNT_EN_MQ_P6_EN_OFFSET  14
+	#define AGG_PROFILE_CNT_EN_MQ_P6_EN_LEN     1
+	#define AGG_PROFILE_CNT_EN_MQ_P6_EN_DEFAULT 0x1
+	/*[field] MQ_P7_EN*/
+	#define AGG_PROFILE_CNT_EN_MQ_P7_EN
+	#define AGG_PROFILE_CNT_EN_MQ_P7_EN_OFFSET  15
+	#define AGG_PROFILE_CNT_EN_MQ_P7_EN_LEN     1
+	#define AGG_PROFILE_CNT_EN_MQ_P7_EN_DEFAULT 0x1
+	/*[field] GRP_0_EN*/
+	#define AGG_PROFILE_CNT_EN_GRP_0_EN
+	#define AGG_PROFILE_CNT_EN_GRP_0_EN_OFFSET  16
+	#define AGG_PROFILE_CNT_EN_GRP_0_EN_LEN     1
+	#define AGG_PROFILE_CNT_EN_GRP_0_EN_DEFAULT 0x1
+	/*[field] GRP_1_EN*/
+	#define AGG_PROFILE_CNT_EN_GRP_1_EN
+	#define AGG_PROFILE_CNT_EN_GRP_1_EN_OFFSET  17
+	#define AGG_PROFILE_CNT_EN_GRP_1_EN_LEN     1
+	#define AGG_PROFILE_CNT_EN_GRP_1_EN_DEFAULT 0x1
+	/*[field] GRP_2_EN*/
+	#define AGG_PROFILE_CNT_EN_GRP_2_EN
+	#define AGG_PROFILE_CNT_EN_GRP_2_EN_OFFSET  18
+	#define AGG_PROFILE_CNT_EN_GRP_2_EN_LEN     1
+	#define AGG_PROFILE_CNT_EN_GRP_2_EN_DEFAULT 0x1
+	/*[field] GRP_3_EN*/
+	#define AGG_PROFILE_CNT_EN_GRP_3_EN
+	#define AGG_PROFILE_CNT_EN_GRP_3_EN_OFFSET  19
+	#define AGG_PROFILE_CNT_EN_GRP_3_EN_LEN     1
+	#define AGG_PROFILE_CNT_EN_GRP_3_EN_DEFAULT 0x1
+	/*[field] GLOBAL_EN*/
+	#define AGG_PROFILE_CNT_EN_GLOBAL_EN
+	#define AGG_PROFILE_CNT_EN_GLOBAL_EN_OFFSET  31
+	#define AGG_PROFILE_CNT_EN_GLOBAL_EN_LEN     1
+	#define AGG_PROFILE_CNT_EN_GLOBAL_EN_DEFAULT 0x0
+
+struct agg_profile_cnt_en {
+	a_uint32_t  uq_en_0:1;
+	a_uint32_t  uq_en_1:1;
+	a_uint32_t  uq_en_2:1;
+	a_uint32_t  uq_en_3:1;
+	a_uint32_t  uq_en_4:1;
+	a_uint32_t  uq_en_5:1;
+	a_uint32_t  uq_en_6:1;
+	a_uint32_t  uq_en_7:1;
+	a_uint32_t  mq_p0_en:1;
+	a_uint32_t  mq_p1_en:1;
+	a_uint32_t  mq_p2_en:1;
+	a_uint32_t  mq_p3_en:1;
+	a_uint32_t  mq_p4_en:1;
+	a_uint32_t  mq_p5_en:1;
+	a_uint32_t  mq_p6_en:1;
+	a_uint32_t  mq_p7_en:1;
+	a_uint32_t  grp_0_en:1;
+	a_uint32_t  grp_1_en:1;
+	a_uint32_t  grp_2_en:1;
+	a_uint32_t  grp_3_en:1;
+	a_uint32_t  _reserved0:11;
+	a_uint32_t  global_en:1;
+};
+
+union agg_profile_cnt_en_u {
+	a_uint32_t val;
+	struct agg_profile_cnt_en bf;
+};
+
+/*[register] UQ_AGG_PROFILE_CFG*/
+#define UQ_AGG_PROFILE_CFG
+#define UQ_AGG_PROFILE_CFG_ADDRESS 0x320
+#define UQ_AGG_PROFILE_CFG_NUM     8
+#define UQ_AGG_PROFILE_CFG_INC     0x4
+#define UQ_AGG_PROFILE_CFG_TYPE    REG_TYPE_RW
+#define UQ_AGG_PROFILE_CFG_DEFAULT 0x0
+	/*[field] TH_CFG*/
+	#define UQ_AGG_PROFILE_CFG_TH_CFG
+	#define UQ_AGG_PROFILE_CFG_TH_CFG_OFFSET  0
+	#define UQ_AGG_PROFILE_CFG_TH_CFG_LEN     11
+	#define UQ_AGG_PROFILE_CFG_TH_CFG_DEFAULT 0x0
+
+struct uq_agg_profile_cfg {
+	a_uint32_t  th_cfg:11;
+	a_uint32_t  _reserved0:21;
+};
+
+union uq_agg_profile_cfg_u {
+	a_uint32_t val;
+	struct uq_agg_profile_cfg bf;
+};
+
+/*[register] MQ_AGG_PROFILE_CFG*/
+#define MQ_AGG_PROFILE_CFG
+#define MQ_AGG_PROFILE_CFG_ADDRESS 0x340
+#define MQ_AGG_PROFILE_CFG_NUM     8
+#define MQ_AGG_PROFILE_CFG_INC     0x4
+#define MQ_AGG_PROFILE_CFG_TYPE    REG_TYPE_RW
+#define MQ_AGG_PROFILE_CFG_DEFAULT 0x0
+	/*[field] TH_CFG*/
+	#define MQ_AGG_PROFILE_CFG_TH_CFG
+	#define MQ_AGG_PROFILE_CFG_TH_CFG_OFFSET  0
+	#define MQ_AGG_PROFILE_CFG_TH_CFG_LEN     11
+	#define MQ_AGG_PROFILE_CFG_TH_CFG_DEFAULT 0x0
+
+struct mq_agg_profile_cfg {
+	a_uint32_t  th_cfg:11;
+	a_uint32_t  _reserved0:21;
+};
+
+union mq_agg_profile_cfg_u {
+	a_uint32_t val;
+	struct mq_agg_profile_cfg bf;
+};
+
+/*[register] GRP_AGG_PROFILE_CFG*/
+#define GRP_AGG_PROFILE_CFG
+#define GRP_AGG_PROFILE_CFG_ADDRESS 0x360
+#define GRP_AGG_PROFILE_CFG_NUM     4
+#define GRP_AGG_PROFILE_CFG_INC     0x4
+#define GRP_AGG_PROFILE_CFG_TYPE    REG_TYPE_RW
+#define GRP_AGG_PROFILE_CFG_DEFAULT 0x0
+	/*[field] TH_CFG*/
+	#define GRP_AGG_PROFILE_CFG_TH_CFG
+	#define GRP_AGG_PROFILE_CFG_TH_CFG_OFFSET  0
+	#define GRP_AGG_PROFILE_CFG_TH_CFG_LEN     11
+	#define GRP_AGG_PROFILE_CFG_TH_CFG_DEFAULT 0x0
+
+struct grp_agg_profile_cfg {
+	a_uint32_t  th_cfg:11;
+	a_uint32_t  _reserved0:21;
+};
+
+union grp_agg_profile_cfg_u {
+	a_uint32_t val;
+	struct grp_agg_profile_cfg bf;
+};
+
+/*[register] UQ_AGG_IN_PROFILE_CNT*/
+#define UQ_AGG_IN_PROFILE_CNT
+#define UQ_AGG_IN_PROFILE_CNT_ADDRESS 0x380
+#define UQ_AGG_IN_PROFILE_CNT_NUM     8
+#define UQ_AGG_IN_PROFILE_CNT_INC     0x4
+#define UQ_AGG_IN_PROFILE_CNT_TYPE    REG_TYPE_RW
+#define UQ_AGG_IN_PROFILE_CNT_DEFAULT 0x0
+	/*[field] CNT*/
+	#define UQ_AGG_IN_PROFILE_CNT_CNT
+	#define UQ_AGG_IN_PROFILE_CNT_CNT_OFFSET  0
+	#define UQ_AGG_IN_PROFILE_CNT_CNT_LEN     32
+	#define UQ_AGG_IN_PROFILE_CNT_CNT_DEFAULT 0x0
+
+struct uq_agg_in_profile_cnt {
+	a_uint32_t  cnt:32;
+};
+
+union uq_agg_in_profile_cnt_u {
+	a_uint32_t val;
+	struct uq_agg_in_profile_cnt bf;
+};
+
+/*[register] UQ_AGG_OUT_PROFILE_CNT*/
+#define UQ_AGG_OUT_PROFILE_CNT
+#define UQ_AGG_OUT_PROFILE_CNT_ADDRESS 0x3a0
+#define UQ_AGG_OUT_PROFILE_CNT_NUM     8
+#define UQ_AGG_OUT_PROFILE_CNT_INC     0x4
+#define UQ_AGG_OUT_PROFILE_CNT_TYPE    REG_TYPE_RW
+#define UQ_AGG_OUT_PROFILE_CNT_DEFAULT 0x0
+	/*[field] CNT*/
+	#define UQ_AGG_OUT_PROFILE_CNT_CNT
+	#define UQ_AGG_OUT_PROFILE_CNT_CNT_OFFSET  0
+	#define UQ_AGG_OUT_PROFILE_CNT_CNT_LEN     32
+	#define UQ_AGG_OUT_PROFILE_CNT_CNT_DEFAULT 0x0
+
+struct uq_agg_out_profile_cnt {
+	a_uint32_t  cnt:32;
+};
+
+union uq_agg_out_profile_cnt_u {
+	a_uint32_t val;
+	struct uq_agg_out_profile_cnt bf;
+};
+
+/*[register] MQ_AGG_IN_PROFILE_CNT*/
+#define MQ_AGG_IN_PROFILE_CNT
+#define MQ_AGG_IN_PROFILE_CNT_ADDRESS 0x3c0
+#define MQ_AGG_IN_PROFILE_CNT_NUM     8
+#define MQ_AGG_IN_PROFILE_CNT_INC     0x4
+#define MQ_AGG_IN_PROFILE_CNT_TYPE    REG_TYPE_RW
+#define MQ_AGG_IN_PROFILE_CNT_DEFAULT 0x0
+	/*[field] CNT*/
+	#define MQ_AGG_IN_PROFILE_CNT_CNT
+	#define MQ_AGG_IN_PROFILE_CNT_CNT_OFFSET  0
+	#define MQ_AGG_IN_PROFILE_CNT_CNT_LEN     32
+	#define MQ_AGG_IN_PROFILE_CNT_CNT_DEFAULT 0x0
+
+struct mq_agg_in_profile_cnt {
+	a_uint32_t  cnt:32;
+};
+
+union mq_agg_in_profile_cnt_u {
+	a_uint32_t val;
+	struct mq_agg_in_profile_cnt bf;
+};
+
+/*[register] MQ_AGG_OUT_PROFILE_CNT*/
+#define MQ_AGG_OUT_PROFILE_CNT
+#define MQ_AGG_OUT_PROFILE_CNT_ADDRESS 0x3e0
+#define MQ_AGG_OUT_PROFILE_CNT_NUM     8
+#define MQ_AGG_OUT_PROFILE_CNT_INC     0x4
+#define MQ_AGG_OUT_PROFILE_CNT_TYPE    REG_TYPE_RW
+#define MQ_AGG_OUT_PROFILE_CNT_DEFAULT 0x0
+	/*[field] CNT*/
+	#define MQ_AGG_OUT_PROFILE_CNT_CNT
+	#define MQ_AGG_OUT_PROFILE_CNT_CNT_OFFSET  0
+	#define MQ_AGG_OUT_PROFILE_CNT_CNT_LEN     32
+	#define MQ_AGG_OUT_PROFILE_CNT_CNT_DEFAULT 0x0
+
+struct mq_agg_out_profile_cnt {
+	a_uint32_t  cnt:32;
+};
+
+union mq_agg_out_profile_cnt_u {
+	a_uint32_t val;
+	struct mq_agg_out_profile_cnt bf;
+};
+
+/*[register] GRP_AGG_IN_PROFILE_CNT*/
+#define GRP_AGG_IN_PROFILE_CNT
+#define GRP_AGG_IN_PROFILE_CNT_ADDRESS 0x400
+#define GRP_AGG_IN_PROFILE_CNT_NUM     4
+#define GRP_AGG_IN_PROFILE_CNT_INC     0x4
+#define GRP_AGG_IN_PROFILE_CNT_TYPE    REG_TYPE_RW
+#define GRP_AGG_IN_PROFILE_CNT_DEFAULT 0x0
+	/*[field] CNT*/
+	#define GRP_AGG_IN_PROFILE_CNT_CNT
+	#define GRP_AGG_IN_PROFILE_CNT_CNT_OFFSET  0
+	#define GRP_AGG_IN_PROFILE_CNT_CNT_LEN     32
+	#define GRP_AGG_IN_PROFILE_CNT_CNT_DEFAULT 0x0
+
+struct grp_agg_in_profile_cnt {
+	a_uint32_t  cnt:32;
+};
+
+union grp_agg_in_profile_cnt_u {
+	a_uint32_t val;
+	struct grp_agg_in_profile_cnt bf;
+};
+
+/*[register] GRP_AGG_OUT_PROFILE_CNT*/
+#define GRP_AGG_OUT_PROFILE_CNT
+#define GRP_AGG_OUT_PROFILE_CNT_ADDRESS 0x410
+#define GRP_AGG_OUT_PROFILE_CNT_NUM     4
+#define GRP_AGG_OUT_PROFILE_CNT_INC     0x4
+#define GRP_AGG_OUT_PROFILE_CNT_TYPE    REG_TYPE_RW
+#define GRP_AGG_OUT_PROFILE_CNT_DEFAULT 0x0
+	/*[field] CNT*/
+	#define GRP_AGG_OUT_PROFILE_CNT_CNT
+	#define GRP_AGG_OUT_PROFILE_CNT_CNT_OFFSET  0
+	#define GRP_AGG_OUT_PROFILE_CNT_CNT_LEN     32
+	#define GRP_AGG_OUT_PROFILE_CNT_CNT_DEFAULT 0x0
+
+struct grp_agg_out_profile_cnt {
+	a_uint32_t  cnt:32;
+};
+
+union grp_agg_out_profile_cnt_u {
+	a_uint32_t val;
+	struct grp_agg_out_profile_cnt bf;
+};
+
+/*[table] UCAST_QUEUE_MAP_TBL*/
+#define UCAST_QUEUE_MAP_TBL
+#define UCAST_QUEUE_MAP_TBL_ADDRESS 0x10000
+#define UCAST_QUEUE_MAP_TBL_NUM     3072
+#define UCAST_QUEUE_MAP_TBL_INC     0x10
+#define UCAST_QUEUE_MAP_TBL_TYPE    REG_TYPE_RW
+#define UCAST_QUEUE_MAP_TBL_DEFAULT 0x0
+	/*[field] PROFILE_ID*/
+	#define UCAST_QUEUE_MAP_TBL_PROFILE_ID
+	#define UCAST_QUEUE_MAP_TBL_PROFILE_ID_OFFSET  0
+	#define UCAST_QUEUE_MAP_TBL_PROFILE_ID_LEN     4
+	#define UCAST_QUEUE_MAP_TBL_PROFILE_ID_DEFAULT 0x0
+	/*[field] QUEUE_ID*/
+	#define UCAST_QUEUE_MAP_TBL_QUEUE_ID
+	#define UCAST_QUEUE_MAP_TBL_QUEUE_ID_OFFSET  4
+	#define UCAST_QUEUE_MAP_TBL_QUEUE_ID_LEN     8
+	#define UCAST_QUEUE_MAP_TBL_QUEUE_ID_DEFAULT 0x0
+
+struct ucast_queue_map_tbl {
+	a_uint32_t  profile_id:4;
+	a_uint32_t  queue_id:8;
+	a_uint32_t  _reserved0:20;
+};
+
+union ucast_queue_map_tbl_u {
+	a_uint32_t val;
+	struct ucast_queue_map_tbl bf;
+};
+
+/*[table] UCAST_HASH_MAP_TBL*/
+#define UCAST_HASH_MAP_TBL
+#define UCAST_HASH_MAP_TBL_ADDRESS 0x30000
+#define UCAST_HASH_MAP_TBL_NUM     4096
+#define UCAST_HASH_MAP_TBL_INC     0x10
+#define UCAST_HASH_MAP_TBL_TYPE    REG_TYPE_RW
+#define UCAST_HASH_MAP_TBL_DEFAULT 0x0
+	/*[field] HASH*/
+	#define UCAST_HASH_MAP_TBL_HASH
+	#define UCAST_HASH_MAP_TBL_HASH_OFFSET  0
+	#define UCAST_HASH_MAP_TBL_HASH_LEN     8
+	#define UCAST_HASH_MAP_TBL_HASH_DEFAULT 0x0
+
+struct ucast_hash_map_tbl {
+	a_uint32_t  hash:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union ucast_hash_map_tbl_u {
+	a_uint32_t val;
+	struct ucast_hash_map_tbl bf;
+};
+
+/*[table] UCAST_PRIORITY_MAP_TBL*/
+#define UCAST_PRIORITY_MAP_TBL
+#define UCAST_PRIORITY_MAP_TBL_ADDRESS 0x42000
+#define UCAST_PRIORITY_MAP_TBL_NUM     256
+#define UCAST_PRIORITY_MAP_TBL_INC     0x10
+#define UCAST_PRIORITY_MAP_TBL_TYPE    REG_TYPE_RW
+#define UCAST_PRIORITY_MAP_TBL_DEFAULT 0x0
+	/*[field] CLASS*/
+	#define UCAST_PRIORITY_MAP_TBL_CLASS
+	#define UCAST_PRIORITY_MAP_TBL_CLASS_OFFSET  0
+	#define UCAST_PRIORITY_MAP_TBL_CLASS_LEN     4
+	#define UCAST_PRIORITY_MAP_TBL_CLASS_DEFAULT 0x0
+
+struct ucast_priority_map_tbl {
+	a_uint32_t  class:4;
+	a_uint32_t  _reserved0:28;
+};
+
+union ucast_priority_map_tbl_u {
+	a_uint32_t val;
+	struct ucast_priority_map_tbl bf;
+};
+
+/*[table] MCAST_QUEUE_MAP_TBL*/
+#define MCAST_QUEUE_MAP_TBL
+#define MCAST_QUEUE_MAP_TBL_ADDRESS 0x44000
+#define MCAST_QUEUE_MAP_TBL_NUM     256
+#define MCAST_QUEUE_MAP_TBL_INC     0x10
+#define MCAST_QUEUE_MAP_TBL_TYPE    REG_TYPE_RW
+#define MCAST_QUEUE_MAP_TBL_DEFAULT 0x0
+	/*[field] CLASS*/
+	#define MCAST_QUEUE_MAP_TBL_CLASS
+	#define MCAST_QUEUE_MAP_TBL_CLASS_OFFSET  0
+	#define MCAST_QUEUE_MAP_TBL_CLASS_LEN     4
+	#define MCAST_QUEUE_MAP_TBL_CLASS_DEFAULT 0x0
+
+struct mcast_queue_map_tbl {
+	a_uint32_t  class:4;
+	a_uint32_t  _reserved0:28;
+};
+
+union mcast_queue_map_tbl_u {
+	a_uint32_t val;
+	struct mcast_queue_map_tbl bf;
+};
+
+/*[table] AC_MSEQ_TBL*/
+#define AC_MSEQ_TBL
+#define AC_MSEQ_TBL_ADDRESS 0x46000
+#define AC_MSEQ_TBL_NUM     256
+#define AC_MSEQ_TBL_INC     0x10
+#define AC_MSEQ_TBL_TYPE    REG_TYPE_RW
+#define AC_MSEQ_TBL_DEFAULT 0x0
+	/*[field] AC_MSEQ*/
+	#define AC_MSEQ_TBL_AC_MSEQ
+	#define AC_MSEQ_TBL_AC_MSEQ_OFFSET  0
+	#define AC_MSEQ_TBL_AC_MSEQ_LEN     15
+	#define AC_MSEQ_TBL_AC_MSEQ_DEFAULT 0x0
+
+struct ac_mseq_tbl {
+	a_uint32_t  ac_mseq:15;
+	a_uint32_t  _reserved0:17;
+};
+
+union ac_mseq_tbl_u {
+	a_uint32_t val;
+	struct ac_mseq_tbl bf;
+};
+
+/*[table] AC_UNI_QUEUE_CFG_TBL*/
+#define AC_UNI_QUEUE_CFG_TBL
+#define AC_UNI_QUEUE_CFG_TBL_ADDRESS 0x48000
+#define AC_UNI_QUEUE_CFG_TBL_NUM     256
+#define AC_UNI_QUEUE_CFG_TBL_INC     0x10
+#define AC_UNI_QUEUE_CFG_TBL_TYPE    REG_TYPE_RW
+#define AC_UNI_QUEUE_CFG_TBL_DEFAULT 0x0
+	/*[field] AC_CFG_AC_EN*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_AC_EN
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_AC_EN_OFFSET  0
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_AC_EN_LEN     1
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_AC_EN_DEFAULT 0x0
+	/*[field] AC_CFG_WRED_EN*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_WRED_EN
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_WRED_EN_OFFSET  1
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_WRED_EN_LEN     1
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_WRED_EN_DEFAULT 0x0
+	/*[field] AC_CFG_FORCE_AC_EN*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN_OFFSET  2
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN_LEN     1
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN_DEFAULT 0x0
+	/*[field] AC_CFG_COLOR_AWARE*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE_OFFSET  3
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE_LEN     1
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE_DEFAULT 0x0
+	/*[field] AC_CFG_GRP_ID*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRP_ID
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRP_ID_OFFSET  4
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRP_ID_LEN     2
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRP_ID_DEFAULT 0x0
+	/*[field] AC_CFG_PRE_ALLOC_LIMIT*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT_OFFSET  6
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT_LEN     11
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT_DEFAULT 0x0
+	/*[field] AC_CFG_SHARED_DYNAMIC*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_DYNAMIC
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_DYNAMIC_OFFSET  17
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_DYNAMIC_LEN     1
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_DYNAMIC_DEFAULT 0x0
+	/*[field] AC_CFG_SHARED_WEIGHT*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_WEIGHT
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_WEIGHT_OFFSET  18
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_WEIGHT_LEN     3
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_WEIGHT_DEFAULT 0x0
+	/*[field] AC_CFG_SHARED_CEILING*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING_OFFSET  21
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING_LEN     11
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING_DEFAULT 0x0
+	/*[field] AC_CFG_GAP_GRN_GRN_MIN*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_GRN_MIN
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_GRN_MIN_OFFSET  32
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_GRN_MIN_LEN     11
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_GRN_MIN_DEFAULT 0x0
+	/*[field] AC_CFG_GAP_GRN_YEL_MAX*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MAX
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MAX_OFFSET  43
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MAX_LEN     11
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MAX_DEFAULT 0x0
+	/*[field] AC_CFG_GAP_GRN_YEL_MIN*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MIN
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MIN_OFFSET  54
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MIN_LEN     11
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MIN_DEFAULT 0x0
+	/*[field] AC_CFG_GAP_GRN_RED_MAX*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MAX
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MAX_OFFSET  65
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MAX_LEN     11
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MAX_DEFAULT 0x0
+	/*[field] AC_CFG_GAP_GRN_RED_MIN*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MIN
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MIN_OFFSET  76
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MIN_LEN     11
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MIN_DEFAULT 0x0
+	/*[field] AC_CFG_RED_RESUME_OFFSET*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET_OFFSET  87
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET_LEN     11
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET_DEFAULT 0x0
+	/*[field] AC_CFG_YEL_RESUME_OFFSET*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET_OFFSET  98
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET_LEN     11
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET_DEFAULT 0x0
+	/*[field] AC_CFG_GRN_RESUME_OFFSET*/
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET_OFFSET  109
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET_LEN     11
+	#define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET_DEFAULT 0x0
+
+struct ac_uni_queue_cfg_tbl {
+	a_uint32_t  ac_cfg_ac_en:1;
+	a_uint32_t  ac_cfg_wred_en:1;
+	a_uint32_t  ac_cfg_force_ac_en:1;
+	a_uint32_t  ac_cfg_color_aware:1;
+	a_uint32_t  ac_cfg_grp_id:2;
+	a_uint32_t  ac_cfg_pre_alloc_limit:11;
+	a_uint32_t  ac_cfg_shared_dynamic:1;
+	a_uint32_t  ac_cfg_shared_weight:3;
+	a_uint32_t  ac_cfg_shared_ceiling:11;
+	a_uint32_t  ac_cfg_gap_grn_grn_min:11;
+	a_uint32_t  ac_cfg_gap_grn_yel_max:11;
+	a_uint32_t  ac_cfg_gap_grn_yel_min_0:10;
+	a_uint32_t  ac_cfg_gap_grn_yel_min_1:1;
+	a_uint32_t  ac_cfg_gap_grn_red_max:11;
+	a_uint32_t  ac_cfg_gap_grn_red_min:11;
+	a_uint32_t  ac_cfg_red_resume_offset_0:9;
+	a_uint32_t  ac_cfg_red_resume_offset_1:2;
+	a_uint32_t  ac_cfg_yel_resume_offset:11;
+	a_uint32_t  ac_cfg_grn_resume_offset:11;
+	a_uint32_t  _reserved0:8;
+};
+
+union ac_uni_queue_cfg_tbl_u {
+	a_uint32_t val[4];
+	struct ac_uni_queue_cfg_tbl bf;
+};
+
+/*[table] AC_MUL_QUEUE_CFG_TBL*/
+#define AC_MUL_QUEUE_CFG_TBL
+#define AC_MUL_QUEUE_CFG_TBL_ADDRESS 0x4a000
+#define AC_MUL_QUEUE_CFG_TBL_NUM     44
+#define AC_MUL_QUEUE_CFG_TBL_INC     0x10
+#define AC_MUL_QUEUE_CFG_TBL_TYPE    REG_TYPE_RW
+#define AC_MUL_QUEUE_CFG_TBL_DEFAULT 0x0
+	/*[field] AC_CFG_AC_EN*/
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_AC_EN
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_AC_EN_OFFSET  0
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_AC_EN_LEN     1
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_AC_EN_DEFAULT 0x0
+	/*[field] AC_CFG_FORCE_AC_EN*/
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN_OFFSET  1
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN_LEN     1
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN_DEFAULT 0x0
+	/*[field] AC_CFG_COLOR_AWARE*/
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE_OFFSET  2
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE_LEN     1
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE_DEFAULT 0x0
+	/*[field] AC_CFG_GRP_ID*/
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRP_ID
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRP_ID_OFFSET  3
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRP_ID_LEN     2
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRP_ID_DEFAULT 0x0
+	/*[field] AC_CFG_PRE_ALLOC_LIMIT*/
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT_OFFSET  5
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT_LEN     11
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT_DEFAULT 0x0
+	/*[field] AC_CFG_SHARED_CEILING*/
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING_OFFSET  16
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING_LEN     11
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING_DEFAULT 0x0
+	/*[field] AC_CFG_GAP_GRN_YEL*/
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_OFFSET  27
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_LEN     11
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_DEFAULT 0x0
+	/*[field] AC_CFG_GAP_GRN_RED*/
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_OFFSET  38
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_LEN     11
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_DEFAULT 0x0
+	/*[field] AC_CFG_RED_RESUME_OFFSET*/
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET_OFFSET  49
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET_LEN     11
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET_DEFAULT 0x0
+	/*[field] AC_CFG_YEL_RESUME_OFFSET*/
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET_OFFSET  60
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET_LEN     11
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET_DEFAULT 0x0
+	/*[field] AC_CFG_GRN_RESUME_OFFSET*/
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET_OFFSET  71
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET_LEN     11
+	#define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET_DEFAULT 0x0
+
+struct ac_mul_queue_cfg_tbl {
+	a_uint32_t  ac_cfg_ac_en:1;
+	a_uint32_t  ac_cfg_force_ac_en:1;
+	a_uint32_t  ac_cfg_color_aware:1;
+	a_uint32_t  ac_cfg_grp_id:2;
+	a_uint32_t  ac_cfg_pre_alloc_limit:11;
+	a_uint32_t  ac_cfg_shared_ceiling:11;
+	a_uint32_t  ac_cfg_gap_grn_yel_0:5;
+	a_uint32_t  ac_cfg_gap_grn_yel_1:6;
+	a_uint32_t  ac_cfg_gap_grn_red:11;
+	a_uint32_t  ac_cfg_red_resume_offset:11;
+	a_uint32_t  ac_cfg_yel_resume_offset_0:4;
+	a_uint32_t  ac_cfg_yel_resume_offset_1:7;
+	a_uint32_t  ac_cfg_grn_resume_offset:11;
+	a_uint32_t  _reserved0:14;
+};
+
+union ac_mul_queue_cfg_tbl_u {
+	a_uint32_t val[3];
+	struct ac_mul_queue_cfg_tbl bf;
+};
+
+/*[table] AC_GRP_CFG_TBL*/
+#define AC_GRP_CFG_TBL
+#define AC_GRP_CFG_TBL_ADDRESS 0x4c000
+#define AC_GRP_CFG_TBL_NUM     4
+#define AC_GRP_CFG_TBL_INC     0x10
+#define AC_GRP_CFG_TBL_TYPE    REG_TYPE_RW
+#define AC_GRP_CFG_TBL_DEFAULT 0x0
+	/*[field] AC_CFG_AC_EN*/
+	#define AC_GRP_CFG_TBL_AC_CFG_AC_EN
+	#define AC_GRP_CFG_TBL_AC_CFG_AC_EN_OFFSET  0
+	#define AC_GRP_CFG_TBL_AC_CFG_AC_EN_LEN     1
+	#define AC_GRP_CFG_TBL_AC_CFG_AC_EN_DEFAULT 0x0
+	/*[field] AC_CFG_FORCE_AC_EN*/
+	#define AC_GRP_CFG_TBL_AC_CFG_FORCE_AC_EN
+	#define AC_GRP_CFG_TBL_AC_CFG_FORCE_AC_EN_OFFSET  1
+	#define AC_GRP_CFG_TBL_AC_CFG_FORCE_AC_EN_LEN     1
+	#define AC_GRP_CFG_TBL_AC_CFG_FORCE_AC_EN_DEFAULT 0x0
+	/*[field] AC_CFG_COLOR_AWARE*/
+	#define AC_GRP_CFG_TBL_AC_CFG_COLOR_AWARE
+	#define AC_GRP_CFG_TBL_AC_CFG_COLOR_AWARE_OFFSET  2
+	#define AC_GRP_CFG_TBL_AC_CFG_COLOR_AWARE_LEN     1
+	#define AC_GRP_CFG_TBL_AC_CFG_COLOR_AWARE_DEFAULT 0x0
+	/*[field] AC_GRP_GAP_GRN_RED*/
+	#define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_RED
+	#define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_RED_OFFSET  3
+	#define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_RED_LEN     11
+	#define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_RED_DEFAULT 0x0
+	/*[field] AC_GRP_GAP_GRN_YEL*/
+	#define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_YEL
+	#define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_YEL_OFFSET  14
+	#define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_YEL_LEN     11
+	#define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_YEL_DEFAULT 0x0
+	/*[field] AC_GRP_DP_THRD*/
+	#define AC_GRP_CFG_TBL_AC_GRP_DP_THRD
+	#define AC_GRP_CFG_TBL_AC_GRP_DP_THRD_OFFSET  25
+	#define AC_GRP_CFG_TBL_AC_GRP_DP_THRD_LEN     11
+	#define AC_GRP_CFG_TBL_AC_GRP_DP_THRD_DEFAULT 0x0
+	/*[field] AC_GRP_LIMIT*/
+	#define AC_GRP_CFG_TBL_AC_GRP_LIMIT
+	#define AC_GRP_CFG_TBL_AC_GRP_LIMIT_OFFSET  36
+	#define AC_GRP_CFG_TBL_AC_GRP_LIMIT_LEN     11
+	#define AC_GRP_CFG_TBL_AC_GRP_LIMIT_DEFAULT 0x0
+	/*[field] AC_GRP_RED_RESUME_OFFSET*/
+	#define AC_GRP_CFG_TBL_AC_GRP_RED_RESUME_OFFSET
+	#define AC_GRP_CFG_TBL_AC_GRP_RED_RESUME_OFFSET_OFFSET  47
+	#define AC_GRP_CFG_TBL_AC_GRP_RED_RESUME_OFFSET_LEN     11
+	#define AC_GRP_CFG_TBL_AC_GRP_RED_RESUME_OFFSET_DEFAULT 0x0
+	/*[field] AC_GRP_YEL_RESUME_OFFSET*/
+	#define AC_GRP_CFG_TBL_AC_GRP_YEL_RESUME_OFFSET
+	#define AC_GRP_CFG_TBL_AC_GRP_YEL_RESUME_OFFSET_OFFSET  58
+	#define AC_GRP_CFG_TBL_AC_GRP_YEL_RESUME_OFFSET_LEN     11
+	#define AC_GRP_CFG_TBL_AC_GRP_YEL_RESUME_OFFSET_DEFAULT 0x0
+	/*[field] AC_GRP_GRN_RESUME_OFFSET*/
+	#define AC_GRP_CFG_TBL_AC_GRP_GRN_RESUME_OFFSET
+	#define AC_GRP_CFG_TBL_AC_GRP_GRN_RESUME_OFFSET_OFFSET  69
+	#define AC_GRP_CFG_TBL_AC_GRP_GRN_RESUME_OFFSET_LEN     11
+	#define AC_GRP_CFG_TBL_AC_GRP_GRN_RESUME_OFFSET_DEFAULT 0x0
+	/*[field] AC_GRP_PALLOC_LIMIT*/
+	#define AC_GRP_CFG_TBL_AC_GRP_PALLOC_LIMIT
+	#define AC_GRP_CFG_TBL_AC_GRP_PALLOC_LIMIT_OFFSET  80
+	#define AC_GRP_CFG_TBL_AC_GRP_PALLOC_LIMIT_LEN     11
+	#define AC_GRP_CFG_TBL_AC_GRP_PALLOC_LIMIT_DEFAULT 0x0
+
+struct ac_grp_cfg_tbl {
+	a_uint32_t  ac_cfg_ac_en:1;
+	a_uint32_t  ac_cfg_force_ac_en:1;
+	a_uint32_t  ac_cfg_color_aware:1;
+	a_uint32_t  ac_grp_gap_grn_red:11;
+	a_uint32_t  ac_grp_gap_grn_yel:11;
+	a_uint32_t  ac_grp_dp_thrd_0:7;
+	a_uint32_t  ac_grp_dp_thrd_1:4;
+	a_uint32_t  ac_grp_limit:11;
+	a_uint32_t  ac_grp_red_resume_offset:11;
+	a_uint32_t  ac_grp_yel_resume_offset_0:6;
+	a_uint32_t  ac_grp_yel_resume_offset_1:5;
+	a_uint32_t  ac_grp_grn_resume_offset:11;
+	a_uint32_t  ac_grp_palloc_limit:11;
+	a_uint32_t  _reserved0:5;
+};
+
+union ac_grp_cfg_tbl_u {
+	a_uint32_t val[3];
+	struct ac_grp_cfg_tbl bf;
+};
+
+/*[table] AC_UNI_QUEUE_CNT_TBL*/
+#define AC_UNI_QUEUE_CNT_TBL
+#define AC_UNI_QUEUE_CNT_TBL_ADDRESS 0x4e000
+#define AC_UNI_QUEUE_CNT_TBL_NUM     256
+#define AC_UNI_QUEUE_CNT_TBL_INC     0x10
+#define AC_UNI_QUEUE_CNT_TBL_TYPE    REG_TYPE_RW
+#define AC_UNI_QUEUE_CNT_TBL_DEFAULT 0x0
+	/*[field] AC_UNI_QUEUE_CNT*/
+	#define AC_UNI_QUEUE_CNT_TBL_AC_UNI_QUEUE_CNT
+	#define AC_UNI_QUEUE_CNT_TBL_AC_UNI_QUEUE_CNT_OFFSET  0
+	#define AC_UNI_QUEUE_CNT_TBL_AC_UNI_QUEUE_CNT_LEN     12
+	#define AC_UNI_QUEUE_CNT_TBL_AC_UNI_QUEUE_CNT_DEFAULT 0x0
+
+struct ac_uni_queue_cnt_tbl {
+	a_uint32_t  ac_uni_queue_cnt:12;
+	a_uint32_t  _reserved0:20;
+};
+
+union ac_uni_queue_cnt_tbl_u {
+	a_uint32_t val;
+	struct ac_uni_queue_cnt_tbl bf;
+};
+
+/*[table] AC_MUL_QUEUE_CNT_TBL*/
+#define AC_MUL_QUEUE_CNT_TBL
+#define AC_MUL_QUEUE_CNT_TBL_ADDRESS 0x52000
+#define AC_MUL_QUEUE_CNT_TBL_NUM     44
+#define AC_MUL_QUEUE_CNT_TBL_INC     0x10
+#define AC_MUL_QUEUE_CNT_TBL_TYPE    REG_TYPE_RW
+#define AC_MUL_QUEUE_CNT_TBL_DEFAULT 0x0
+	/*[field] AC_MUL_QUEUE_CNT*/
+	#define AC_MUL_QUEUE_CNT_TBL_AC_MUL_QUEUE_CNT
+	#define AC_MUL_QUEUE_CNT_TBL_AC_MUL_QUEUE_CNT_OFFSET  0
+	#define AC_MUL_QUEUE_CNT_TBL_AC_MUL_QUEUE_CNT_LEN     13
+	#define AC_MUL_QUEUE_CNT_TBL_AC_MUL_QUEUE_CNT_DEFAULT 0x0
+
+struct ac_mul_queue_cnt_tbl {
+	a_uint32_t  ac_mul_queue_cnt:13;
+	a_uint32_t  _reserved0:19;
+};
+
+union ac_mul_queue_cnt_tbl_u {
+	a_uint32_t val;
+	struct ac_mul_queue_cnt_tbl bf;
+};
+
+/*[table] AC_GRP_CNT_TBL*/
+#define AC_GRP_CNT_TBL
+#define AC_GRP_CNT_TBL_ADDRESS 0x54000
+#define AC_GRP_CNT_TBL_NUM     4
+#define AC_GRP_CNT_TBL_INC     0x10
+#define AC_GRP_CNT_TBL_TYPE    REG_TYPE_RW
+#define AC_GRP_CNT_TBL_DEFAULT 0x0
+	/*[field] AC_GRP_CNT*/
+	#define AC_GRP_CNT_TBL_AC_GRP_CNT
+	#define AC_GRP_CNT_TBL_AC_GRP_CNT_OFFSET  0
+	#define AC_GRP_CNT_TBL_AC_GRP_CNT_LEN     16
+	#define AC_GRP_CNT_TBL_AC_GRP_CNT_DEFAULT 0x0
+	/*[field] AC_GRP_ALLOC_USED*/
+	#define AC_GRP_CNT_TBL_AC_GRP_ALLOC_USED
+	#define AC_GRP_CNT_TBL_AC_GRP_ALLOC_USED_OFFSET  16
+	#define AC_GRP_CNT_TBL_AC_GRP_ALLOC_USED_LEN     16
+	#define AC_GRP_CNT_TBL_AC_GRP_ALLOC_USED_DEFAULT 0x0
+
+struct ac_grp_cnt_tbl {
+	a_uint32_t  ac_grp_cnt:16;
+	a_uint32_t  ac_grp_alloc_used:16;
+};
+
+union ac_grp_cnt_tbl_u {
+	a_uint32_t val;
+	struct ac_grp_cnt_tbl bf;
+};
+
+/*[table] AC_UNI_QUEUE_DROP_STATE_TBL*/
+#define AC_UNI_QUEUE_DROP_STATE_TBL
+#define AC_UNI_QUEUE_DROP_STATE_TBL_ADDRESS 0x56000
+#define AC_UNI_QUEUE_DROP_STATE_TBL_NUM     256
+#define AC_UNI_QUEUE_DROP_STATE_TBL_INC     0x10
+#define AC_UNI_QUEUE_DROP_STATE_TBL_TYPE    REG_TYPE_RW
+#define AC_UNI_QUEUE_DROP_STATE_TBL_DEFAULT 0x0
+	/*[field] RED_RESUME_THRD*/
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD_OFFSET  0
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD_LEN     11
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD_DEFAULT 0x0
+	/*[field] YEL_RESUME_THRD*/
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD_OFFSET  11
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD_LEN     11
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD_DEFAULT 0x0
+	/*[field] GRN_RESUME_THRD*/
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD_OFFSET  22
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD_LEN     11
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD_DEFAULT 0x0
+	/*[field] RED_DROP_STATE*/
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_RED_DROP_STATE
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_RED_DROP_STATE_OFFSET  33
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_RED_DROP_STATE_LEN     4
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_RED_DROP_STATE_DEFAULT 0x0
+	/*[field] YEL_DROP_STATE*/
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE_OFFSET  37
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE_LEN     4
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE_DEFAULT 0x0
+	/*[field] GRN_DROP_STATE*/
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE_OFFSET  41
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE_LEN     4
+	#define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE_DEFAULT 0x0
+
+struct ac_uni_queue_drop_state_tbl {
+	a_uint32_t  red_resume_thrd:11;
+	a_uint32_t  yel_resume_thrd:11;
+	a_uint32_t  grn_resume_thrd_0:10;
+	a_uint32_t  grn_resume_thrd_1:1;
+	a_uint32_t  red_drop_state:4;
+	a_uint32_t  yel_drop_state:4;
+	a_uint32_t  grn_drop_state:4;
+	a_uint32_t  _reserved0:19;
+};
+
+union ac_uni_queue_drop_state_tbl_u {
+	a_uint32_t val[2];
+	struct ac_uni_queue_drop_state_tbl bf;
+};
+
+/*[table] AC_MUL_QUEUE_DROP_STATE_TBL*/
+#define AC_MUL_QUEUE_DROP_STATE_TBL
+#define AC_MUL_QUEUE_DROP_STATE_TBL_ADDRESS 0x58000
+#define AC_MUL_QUEUE_DROP_STATE_TBL_NUM     44
+#define AC_MUL_QUEUE_DROP_STATE_TBL_INC     0x10
+#define AC_MUL_QUEUE_DROP_STATE_TBL_TYPE    REG_TYPE_RW
+#define AC_MUL_QUEUE_DROP_STATE_TBL_DEFAULT 0x0
+	/*[field] RED_RESUME_THRD*/
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD_OFFSET  0
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD_LEN     11
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD_DEFAULT 0x0
+	/*[field] YEL_RESUME_THRD*/
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD_OFFSET  11
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD_LEN     11
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD_DEFAULT 0x0
+	/*[field] GRN_RESUME_THRD*/
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD_OFFSET  22
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD_LEN     11
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD_DEFAULT 0x0
+	/*[field] RED_DROP_STATE*/
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_RED_DROP_STATE
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_RED_DROP_STATE_OFFSET  33
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_RED_DROP_STATE_LEN     1
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_RED_DROP_STATE_DEFAULT 0x0
+	/*[field] YEL_DROP_STATE*/
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE_OFFSET  34
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE_LEN     1
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE_DEFAULT 0x0
+	/*[field] GRN_DROP_STATE*/
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE_OFFSET  35
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE_LEN     1
+	#define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE_DEFAULT 0x0
+
+struct ac_mul_queue_drop_state_tbl {
+	a_uint32_t  red_resume_thrd:11;
+	a_uint32_t  yel_resume_thrd:11;
+	a_uint32_t  grn_resume_thrd_0:10;
+	a_uint32_t  grn_resume_thrd_1:1;
+	a_uint32_t  red_drop_state:1;
+	a_uint32_t  yel_drop_state:1;
+	a_uint32_t  grn_drop_state:1;
+	a_uint32_t  _reserved0:28;
+};
+
+union ac_mul_queue_drop_state_tbl_u {
+	a_uint32_t val[2];
+	struct ac_mul_queue_drop_state_tbl bf;
+};
+
+/*[table] AC_GRP_DROP_STATE_TBL*/
+#define AC_GRP_DROP_STATE_TBL
+#define AC_GRP_DROP_STATE_TBL_ADDRESS 0x5a000
+#define AC_GRP_DROP_STATE_TBL_NUM     4
+#define AC_GRP_DROP_STATE_TBL_INC     0x10
+#define AC_GRP_DROP_STATE_TBL_TYPE    REG_TYPE_RW
+#define AC_GRP_DROP_STATE_TBL_DEFAULT 0x0
+	/*[field] RED_RESUME_THRD*/
+	#define AC_GRP_DROP_STATE_TBL_RED_RESUME_THRD
+	#define AC_GRP_DROP_STATE_TBL_RED_RESUME_THRD_OFFSET  0
+	#define AC_GRP_DROP_STATE_TBL_RED_RESUME_THRD_LEN     11
+	#define AC_GRP_DROP_STATE_TBL_RED_RESUME_THRD_DEFAULT 0x0
+	/*[field] YEL_RESUME_THRD*/
+	#define AC_GRP_DROP_STATE_TBL_YEL_RESUME_THRD
+	#define AC_GRP_DROP_STATE_TBL_YEL_RESUME_THRD_OFFSET  11
+	#define AC_GRP_DROP_STATE_TBL_YEL_RESUME_THRD_LEN     11
+	#define AC_GRP_DROP_STATE_TBL_YEL_RESUME_THRD_DEFAULT 0x0
+	/*[field] GRN_RESUME_THRD*/
+	#define AC_GRP_DROP_STATE_TBL_GRN_RESUME_THRD
+	#define AC_GRP_DROP_STATE_TBL_GRN_RESUME_THRD_OFFSET  22
+	#define AC_GRP_DROP_STATE_TBL_GRN_RESUME_THRD_LEN     11
+	#define AC_GRP_DROP_STATE_TBL_GRN_RESUME_THRD_DEFAULT 0x0
+	/*[field] RED_DROP_STATE*/
+	#define AC_GRP_DROP_STATE_TBL_RED_DROP_STATE
+	#define AC_GRP_DROP_STATE_TBL_RED_DROP_STATE_OFFSET  33
+	#define AC_GRP_DROP_STATE_TBL_RED_DROP_STATE_LEN     1
+	#define AC_GRP_DROP_STATE_TBL_RED_DROP_STATE_DEFAULT 0x0
+	/*[field] YEL_DROP_STATE*/
+	#define AC_GRP_DROP_STATE_TBL_YEL_DROP_STATE
+	#define AC_GRP_DROP_STATE_TBL_YEL_DROP_STATE_OFFSET  34
+	#define AC_GRP_DROP_STATE_TBL_YEL_DROP_STATE_LEN     1
+	#define AC_GRP_DROP_STATE_TBL_YEL_DROP_STATE_DEFAULT 0x0
+	/*[field] GRN_DROP_STATE*/
+	#define AC_GRP_DROP_STATE_TBL_GRN_DROP_STATE
+	#define AC_GRP_DROP_STATE_TBL_GRN_DROP_STATE_OFFSET  35
+	#define AC_GRP_DROP_STATE_TBL_GRN_DROP_STATE_LEN     1
+	#define AC_GRP_DROP_STATE_TBL_GRN_DROP_STATE_DEFAULT 0x0
+
+struct ac_grp_drop_state_tbl {
+	a_uint32_t  red_resume_thrd:11;
+	a_uint32_t  yel_resume_thrd:11;
+	a_uint32_t  grn_resume_thrd_0:10;
+	a_uint32_t  grn_resume_thrd_1:1;
+	a_uint32_t  red_drop_state:1;
+	a_uint32_t  yel_drop_state:1;
+	a_uint32_t  grn_drop_state:1;
+	a_uint32_t  _reserved0:28;
+};
+
+union ac_grp_drop_state_tbl_u {
+	a_uint32_t val[2];
+	struct ac_grp_drop_state_tbl bf;
+};
+
+/*[table] OQ_ENQ_OPR_TBL*/
+#define OQ_ENQ_OPR_TBL
+#define OQ_ENQ_OPR_TBL_ADDRESS 0x5c000
+#define OQ_ENQ_OPR_TBL_NUM     300
+#define OQ_ENQ_OPR_TBL_INC     0x10
+#define OQ_ENQ_OPR_TBL_TYPE    REG_TYPE_RW
+#define OQ_ENQ_OPR_TBL_DEFAULT 0x0
+	/*[field] ENQ_DISABLE*/
+	#define OQ_ENQ_OPR_TBL_ENQ_DISABLE
+	#define OQ_ENQ_OPR_TBL_ENQ_DISABLE_OFFSET  0
+	#define OQ_ENQ_OPR_TBL_ENQ_DISABLE_LEN     1
+	#define OQ_ENQ_OPR_TBL_ENQ_DISABLE_DEFAULT 0x0
+
+struct oq_enq_opr_tbl {
+	a_uint32_t  enq_disable:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union oq_enq_opr_tbl_u {
+	a_uint32_t val;
+	struct oq_enq_opr_tbl bf;
+};
+
+/*[table] OQ_DEQ_OPR_TBL*/
+#define OQ_DEQ_OPR_TBL
+#define OQ_DEQ_OPR_TBL_ADDRESS 0x64000
+#define OQ_DEQ_OPR_TBL_NUM     300
+#define OQ_DEQ_OPR_TBL_INC     0x10
+#define OQ_DEQ_OPR_TBL_TYPE    REG_TYPE_RW
+#define OQ_DEQ_OPR_TBL_DEFAULT 0x0
+	/*[field] DEQ_DROP*/
+	#define OQ_DEQ_OPR_TBL_DEQ_DROP
+	#define OQ_DEQ_OPR_TBL_DEQ_DROP_OFFSET  0
+	#define OQ_DEQ_OPR_TBL_DEQ_DROP_LEN     1
+	#define OQ_DEQ_OPR_TBL_DEQ_DROP_DEFAULT 0x0
+
+struct oq_deq_opr_tbl {
+	a_uint32_t  deq_drop:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union oq_deq_opr_tbl_u {
+	a_uint32_t val;
+	struct oq_deq_opr_tbl bf;
+};
+
+/*[table] OQ_HEAD_UNI_TBL*/
+#define OQ_HEAD_UNI_TBL
+#define OQ_HEAD_UNI_TBL_ADDRESS 0x6c000
+#define OQ_HEAD_UNI_TBL_NUM     256
+#define OQ_HEAD_UNI_TBL_INC     0x10
+#define OQ_HEAD_UNI_TBL_TYPE    REG_TYPE_RW
+#define OQ_HEAD_UNI_TBL_DEFAULT 0x0
+	/*[field] EMPTY*/
+	#define OQ_HEAD_UNI_TBL_EMPTY
+	#define OQ_HEAD_UNI_TBL_EMPTY_OFFSET  0
+	#define OQ_HEAD_UNI_TBL_EMPTY_LEN     1
+	#define OQ_HEAD_UNI_TBL_EMPTY_DEFAULT 0x0
+	/*[field] TAIL*/
+	#define OQ_HEAD_UNI_TBL_TAIL
+	#define OQ_HEAD_UNI_TBL_TAIL_OFFSET  1
+	#define OQ_HEAD_UNI_TBL_TAIL_LEN     11
+	#define OQ_HEAD_UNI_TBL_TAIL_DEFAULT 0x0
+	/*[field] HEAD*/
+	#define OQ_HEAD_UNI_TBL_HEAD
+	#define OQ_HEAD_UNI_TBL_HEAD_OFFSET  12
+	#define OQ_HEAD_UNI_TBL_HEAD_LEN     11
+	#define OQ_HEAD_UNI_TBL_HEAD_DEFAULT 0x0
+
+struct oq_head_uni_tbl {
+	a_uint32_t  empty:1;
+	a_uint32_t  tail:11;
+	a_uint32_t  head:11;
+	a_uint32_t  _reserved0:9;
+};
+
+union oq_head_uni_tbl_u {
+	a_uint32_t val;
+	struct oq_head_uni_tbl bf;
+};
+
+/*[table] OQ_HEAD_MUL_TBL*/
+#define OQ_HEAD_MUL_TBL
+#define OQ_HEAD_MUL_TBL_ADDRESS 0x74000
+#define OQ_HEAD_MUL_TBL_NUM     44
+#define OQ_HEAD_MUL_TBL_INC     0x10
+#define OQ_HEAD_MUL_TBL_TYPE    REG_TYPE_RW
+#define OQ_HEAD_MUL_TBL_DEFAULT 0x0
+	/*[field] NORMAL_FWD*/
+	#define OQ_HEAD_MUL_TBL_NORMAL_FWD
+	#define OQ_HEAD_MUL_TBL_NORMAL_FWD_OFFSET  0
+	#define OQ_HEAD_MUL_TBL_NORMAL_FWD_LEN     1
+	#define OQ_HEAD_MUL_TBL_NORMAL_FWD_DEFAULT 0x0
+	/*[field] EGRESS_MIRR*/
+	#define OQ_HEAD_MUL_TBL_EGRESS_MIRR
+	#define OQ_HEAD_MUL_TBL_EGRESS_MIRR_OFFSET  1
+	#define OQ_HEAD_MUL_TBL_EGRESS_MIRR_LEN     1
+	#define OQ_HEAD_MUL_TBL_EGRESS_MIRR_DEFAULT 0x0
+	/*[field] INGRESS_MIRR*/
+	#define OQ_HEAD_MUL_TBL_INGRESS_MIRR
+	#define OQ_HEAD_MUL_TBL_INGRESS_MIRR_OFFSET  2
+	#define OQ_HEAD_MUL_TBL_INGRESS_MIRR_LEN     1
+	#define OQ_HEAD_MUL_TBL_INGRESS_MIRR_DEFAULT 0x0
+	/*[field] EMPTY*/
+	#define OQ_HEAD_MUL_TBL_EMPTY
+	#define OQ_HEAD_MUL_TBL_EMPTY_OFFSET  3
+	#define OQ_HEAD_MUL_TBL_EMPTY_LEN     1
+	#define OQ_HEAD_MUL_TBL_EMPTY_DEFAULT 0x0
+	/*[field] TAIL*/
+	#define OQ_HEAD_MUL_TBL_TAIL
+	#define OQ_HEAD_MUL_TBL_TAIL_OFFSET  4
+	#define OQ_HEAD_MUL_TBL_TAIL_LEN     11
+	#define OQ_HEAD_MUL_TBL_TAIL_DEFAULT 0x0
+	/*[field] HEAD*/
+	#define OQ_HEAD_MUL_TBL_HEAD
+	#define OQ_HEAD_MUL_TBL_HEAD_OFFSET  15
+	#define OQ_HEAD_MUL_TBL_HEAD_LEN     11
+	#define OQ_HEAD_MUL_TBL_HEAD_DEFAULT 0x0
+
+struct oq_head_mul_tbl {
+	a_uint32_t  normal_fwd:1;
+	a_uint32_t  egress_mirr:1;
+	a_uint32_t  ingress_mirr:1;
+	a_uint32_t  empty:1;
+	a_uint32_t  tail:11;
+	a_uint32_t  head:11;
+	a_uint32_t  _reserved0:6;
+};
+
+union oq_head_mul_tbl_u {
+	a_uint32_t val;
+	struct oq_head_mul_tbl bf;
+};
+
+/*[table] OQ_LL_UNI_TBL*/
+#define OQ_LL_UNI_TBL
+#define OQ_LL_UNI_TBL_ADDRESS 0x90000
+#define OQ_LL_UNI_TBL_NUM     2048
+#define OQ_LL_UNI_TBL_INC     0x10
+#define OQ_LL_UNI_TBL_TYPE    REG_TYPE_RW
+#define OQ_LL_UNI_TBL_DEFAULT 0x0
+	/*[field] NEXT_POINTER*/
+	#define OQ_LL_UNI_TBL_NEXT_POINTER
+	#define OQ_LL_UNI_TBL_NEXT_POINTER_OFFSET  0
+	#define OQ_LL_UNI_TBL_NEXT_POINTER_LEN     11
+	#define OQ_LL_UNI_TBL_NEXT_POINTER_DEFAULT 0x0
+
+struct oq_ll_uni_tbl {
+	a_uint32_t  next_pointer:11;
+	a_uint32_t  _reserved0:21;
+};
+
+union oq_ll_uni_tbl_u {
+	a_uint32_t val;
+	struct oq_ll_uni_tbl bf;
+};
+
+/*[table] OQ_LL_MUL_P0_TBL*/
+#define OQ_LL_MUL_P0_TBL
+#define OQ_LL_MUL_P0_TBL_ADDRESS 0xb0000
+#define OQ_LL_MUL_P0_TBL_NUM     2048
+#define OQ_LL_MUL_P0_TBL_INC     0x10
+#define OQ_LL_MUL_P0_TBL_TYPE    REG_TYPE_RW
+#define OQ_LL_MUL_P0_TBL_DEFAULT 0x0
+	/*[field] NORMAL_FWD*/
+	#define OQ_LL_MUL_P0_TBL_NORMAL_FWD
+	#define OQ_LL_MUL_P0_TBL_NORMAL_FWD_OFFSET  0
+	#define OQ_LL_MUL_P0_TBL_NORMAL_FWD_LEN     1
+	#define OQ_LL_MUL_P0_TBL_NORMAL_FWD_DEFAULT 0x0
+	/*[field] EGRESS_MIRR*/
+	#define OQ_LL_MUL_P0_TBL_EGRESS_MIRR
+	#define OQ_LL_MUL_P0_TBL_EGRESS_MIRR_OFFSET  1
+	#define OQ_LL_MUL_P0_TBL_EGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P0_TBL_EGRESS_MIRR_DEFAULT 0x0
+	/*[field] INGRESS_MIRR*/
+	#define OQ_LL_MUL_P0_TBL_INGRESS_MIRR
+	#define OQ_LL_MUL_P0_TBL_INGRESS_MIRR_OFFSET  2
+	#define OQ_LL_MUL_P0_TBL_INGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P0_TBL_INGRESS_MIRR_DEFAULT 0x0
+	/*[field] NEXT_POINTER*/
+	#define OQ_LL_MUL_P0_TBL_NEXT_POINTER
+	#define OQ_LL_MUL_P0_TBL_NEXT_POINTER_OFFSET  3
+	#define OQ_LL_MUL_P0_TBL_NEXT_POINTER_LEN     11
+	#define OQ_LL_MUL_P0_TBL_NEXT_POINTER_DEFAULT 0x0
+
+struct oq_ll_mul_p0_tbl {
+	a_uint32_t  normal_fwd:1;
+	a_uint32_t  egress_mirr:1;
+	a_uint32_t  ingress_mirr:1;
+	a_uint32_t  next_pointer:11;
+	a_uint32_t  _reserved0:18;
+};
+
+union oq_ll_mul_p0_tbl_u {
+	a_uint32_t val;
+	struct oq_ll_mul_p0_tbl bf;
+};
+
+/*[table] OQ_LL_MUL_P1_TBL*/
+#define OQ_LL_MUL_P1_TBL
+#define OQ_LL_MUL_P1_TBL_ADDRESS 0xd0000
+#define OQ_LL_MUL_P1_TBL_NUM     2048
+#define OQ_LL_MUL_P1_TBL_INC     0x10
+#define OQ_LL_MUL_P1_TBL_TYPE    REG_TYPE_RW
+#define OQ_LL_MUL_P1_TBL_DEFAULT 0x0
+	/*[field] NORMAL_FWD*/
+	#define OQ_LL_MUL_P1_TBL_NORMAL_FWD
+	#define OQ_LL_MUL_P1_TBL_NORMAL_FWD_OFFSET  0
+	#define OQ_LL_MUL_P1_TBL_NORMAL_FWD_LEN     1
+	#define OQ_LL_MUL_P1_TBL_NORMAL_FWD_DEFAULT 0x0
+	/*[field] EGRESS_MIRR*/
+	#define OQ_LL_MUL_P1_TBL_EGRESS_MIRR
+	#define OQ_LL_MUL_P1_TBL_EGRESS_MIRR_OFFSET  1
+	#define OQ_LL_MUL_P1_TBL_EGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P1_TBL_EGRESS_MIRR_DEFAULT 0x0
+	/*[field] INGRESS_MIRR*/
+	#define OQ_LL_MUL_P1_TBL_INGRESS_MIRR
+	#define OQ_LL_MUL_P1_TBL_INGRESS_MIRR_OFFSET  2
+	#define OQ_LL_MUL_P1_TBL_INGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P1_TBL_INGRESS_MIRR_DEFAULT 0x0
+	/*[field] NEXT_POINTER*/
+	#define OQ_LL_MUL_P1_TBL_NEXT_POINTER
+	#define OQ_LL_MUL_P1_TBL_NEXT_POINTER_OFFSET  3
+	#define OQ_LL_MUL_P1_TBL_NEXT_POINTER_LEN     11
+	#define OQ_LL_MUL_P1_TBL_NEXT_POINTER_DEFAULT 0x0
+
+struct oq_ll_mul_p1_tbl {
+	a_uint32_t  normal_fwd:1;
+	a_uint32_t  egress_mirr:1;
+	a_uint32_t  ingress_mirr:1;
+	a_uint32_t  next_pointer:11;
+	a_uint32_t  _reserved0:18;
+};
+
+union oq_ll_mul_p1_tbl_u {
+	a_uint32_t val;
+	struct oq_ll_mul_p1_tbl bf;
+};
+
+/*[table] OQ_LL_MUL_P2_TBL*/
+#define OQ_LL_MUL_P2_TBL
+#define OQ_LL_MUL_P2_TBL_ADDRESS 0x110000
+#define OQ_LL_MUL_P2_TBL_NUM     2048
+#define OQ_LL_MUL_P2_TBL_INC     0x10
+#define OQ_LL_MUL_P2_TBL_TYPE    REG_TYPE_RW
+#define OQ_LL_MUL_P2_TBL_DEFAULT 0x0
+	/*[field] NORMAL_FWD*/
+	#define OQ_LL_MUL_P2_TBL_NORMAL_FWD
+	#define OQ_LL_MUL_P2_TBL_NORMAL_FWD_OFFSET  0
+	#define OQ_LL_MUL_P2_TBL_NORMAL_FWD_LEN     1
+	#define OQ_LL_MUL_P2_TBL_NORMAL_FWD_DEFAULT 0x0
+	/*[field] EGRESS_MIRR*/
+	#define OQ_LL_MUL_P2_TBL_EGRESS_MIRR
+	#define OQ_LL_MUL_P2_TBL_EGRESS_MIRR_OFFSET  1
+	#define OQ_LL_MUL_P2_TBL_EGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P2_TBL_EGRESS_MIRR_DEFAULT 0x0
+	/*[field] INGRESS_MIRR*/
+	#define OQ_LL_MUL_P2_TBL_INGRESS_MIRR
+	#define OQ_LL_MUL_P2_TBL_INGRESS_MIRR_OFFSET  2
+	#define OQ_LL_MUL_P2_TBL_INGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P2_TBL_INGRESS_MIRR_DEFAULT 0x0
+	/*[field] NEXT_POINTER*/
+	#define OQ_LL_MUL_P2_TBL_NEXT_POINTER
+	#define OQ_LL_MUL_P2_TBL_NEXT_POINTER_OFFSET  3
+	#define OQ_LL_MUL_P2_TBL_NEXT_POINTER_LEN     11
+	#define OQ_LL_MUL_P2_TBL_NEXT_POINTER_DEFAULT 0x0
+
+struct oq_ll_mul_p2_tbl {
+	a_uint32_t  normal_fwd:1;
+	a_uint32_t  egress_mirr:1;
+	a_uint32_t  ingress_mirr:1;
+	a_uint32_t  next_pointer:11;
+	a_uint32_t  _reserved0:18;
+};
+
+union oq_ll_mul_p2_tbl_u {
+	a_uint32_t val;
+	struct oq_ll_mul_p2_tbl bf;
+};
+
+/*[table] OQ_LL_MUL_P3_TBL*/
+#define OQ_LL_MUL_P3_TBL
+#define OQ_LL_MUL_P3_TBL_ADDRESS 0x130000
+#define OQ_LL_MUL_P3_TBL_NUM     2048
+#define OQ_LL_MUL_P3_TBL_INC     0x10
+#define OQ_LL_MUL_P3_TBL_TYPE    REG_TYPE_RW
+#define OQ_LL_MUL_P3_TBL_DEFAULT 0x0
+	/*[field] NORMAL_FWD*/
+	#define OQ_LL_MUL_P3_TBL_NORMAL_FWD
+	#define OQ_LL_MUL_P3_TBL_NORMAL_FWD_OFFSET  0
+	#define OQ_LL_MUL_P3_TBL_NORMAL_FWD_LEN     1
+	#define OQ_LL_MUL_P3_TBL_NORMAL_FWD_DEFAULT 0x0
+	/*[field] EGRESS_MIRR*/
+	#define OQ_LL_MUL_P3_TBL_EGRESS_MIRR
+	#define OQ_LL_MUL_P3_TBL_EGRESS_MIRR_OFFSET  1
+	#define OQ_LL_MUL_P3_TBL_EGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P3_TBL_EGRESS_MIRR_DEFAULT 0x0
+	/*[field] INGRESS_MIRR*/
+	#define OQ_LL_MUL_P3_TBL_INGRESS_MIRR
+	#define OQ_LL_MUL_P3_TBL_INGRESS_MIRR_OFFSET  2
+	#define OQ_LL_MUL_P3_TBL_INGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P3_TBL_INGRESS_MIRR_DEFAULT 0x0
+	/*[field] NEXT_POINTER*/
+	#define OQ_LL_MUL_P3_TBL_NEXT_POINTER
+	#define OQ_LL_MUL_P3_TBL_NEXT_POINTER_OFFSET  3
+	#define OQ_LL_MUL_P3_TBL_NEXT_POINTER_LEN     11
+	#define OQ_LL_MUL_P3_TBL_NEXT_POINTER_DEFAULT 0x0
+
+struct oq_ll_mul_p3_tbl {
+	a_uint32_t  normal_fwd:1;
+	a_uint32_t  egress_mirr:1;
+	a_uint32_t  ingress_mirr:1;
+	a_uint32_t  next_pointer:11;
+	a_uint32_t  _reserved0:18;
+};
+
+union oq_ll_mul_p3_tbl_u {
+	a_uint32_t val;
+	struct oq_ll_mul_p3_tbl bf;
+};
+
+/*[table] OQ_LL_MUL_P4_TBL*/
+#define OQ_LL_MUL_P4_TBL
+#define OQ_LL_MUL_P4_TBL_ADDRESS 0x150000
+#define OQ_LL_MUL_P4_TBL_NUM     2048
+#define OQ_LL_MUL_P4_TBL_INC     0x10
+#define OQ_LL_MUL_P4_TBL_TYPE    REG_TYPE_RW
+#define OQ_LL_MUL_P4_TBL_DEFAULT 0x0
+	/*[field] NORMAL_FWD*/
+	#define OQ_LL_MUL_P4_TBL_NORMAL_FWD
+	#define OQ_LL_MUL_P4_TBL_NORMAL_FWD_OFFSET  0
+	#define OQ_LL_MUL_P4_TBL_NORMAL_FWD_LEN     1
+	#define OQ_LL_MUL_P4_TBL_NORMAL_FWD_DEFAULT 0x0
+	/*[field] EGRESS_MIRR*/
+	#define OQ_LL_MUL_P4_TBL_EGRESS_MIRR
+	#define OQ_LL_MUL_P4_TBL_EGRESS_MIRR_OFFSET  1
+	#define OQ_LL_MUL_P4_TBL_EGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P4_TBL_EGRESS_MIRR_DEFAULT 0x0
+	/*[field] INGRESS_MIRR*/
+	#define OQ_LL_MUL_P4_TBL_INGRESS_MIRR
+	#define OQ_LL_MUL_P4_TBL_INGRESS_MIRR_OFFSET  2
+	#define OQ_LL_MUL_P4_TBL_INGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P4_TBL_INGRESS_MIRR_DEFAULT 0x0
+	/*[field] NEXT_POINTER*/
+	#define OQ_LL_MUL_P4_TBL_NEXT_POINTER
+	#define OQ_LL_MUL_P4_TBL_NEXT_POINTER_OFFSET  3
+	#define OQ_LL_MUL_P4_TBL_NEXT_POINTER_LEN     11
+	#define OQ_LL_MUL_P4_TBL_NEXT_POINTER_DEFAULT 0x0
+
+struct oq_ll_mul_p4_tbl {
+	a_uint32_t  normal_fwd:1;
+	a_uint32_t  egress_mirr:1;
+	a_uint32_t  ingress_mirr:1;
+	a_uint32_t  next_pointer:11;
+	a_uint32_t  _reserved0:18;
+};
+
+union oq_ll_mul_p4_tbl_u {
+	a_uint32_t val;
+	struct oq_ll_mul_p4_tbl bf;
+};
+
+/*[table] OQ_LL_MUL_P5_TBL*/
+#define OQ_LL_MUL_P5_TBL
+#define OQ_LL_MUL_P5_TBL_ADDRESS 0x170000
+#define OQ_LL_MUL_P5_TBL_NUM     2048
+#define OQ_LL_MUL_P5_TBL_INC     0x10
+#define OQ_LL_MUL_P5_TBL_TYPE    REG_TYPE_RW
+#define OQ_LL_MUL_P5_TBL_DEFAULT 0x0
+	/*[field] NORMAL_FWD*/
+	#define OQ_LL_MUL_P5_TBL_NORMAL_FWD
+	#define OQ_LL_MUL_P5_TBL_NORMAL_FWD_OFFSET  0
+	#define OQ_LL_MUL_P5_TBL_NORMAL_FWD_LEN     1
+	#define OQ_LL_MUL_P5_TBL_NORMAL_FWD_DEFAULT 0x0
+	/*[field] EGRESS_MIRR*/
+	#define OQ_LL_MUL_P5_TBL_EGRESS_MIRR
+	#define OQ_LL_MUL_P5_TBL_EGRESS_MIRR_OFFSET  1
+	#define OQ_LL_MUL_P5_TBL_EGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P5_TBL_EGRESS_MIRR_DEFAULT 0x0
+	/*[field] INGRESS_MIRR*/
+	#define OQ_LL_MUL_P5_TBL_INGRESS_MIRR
+	#define OQ_LL_MUL_P5_TBL_INGRESS_MIRR_OFFSET  2
+	#define OQ_LL_MUL_P5_TBL_INGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P5_TBL_INGRESS_MIRR_DEFAULT 0x0
+	/*[field] NEXT_POINTER*/
+	#define OQ_LL_MUL_P5_TBL_NEXT_POINTER
+	#define OQ_LL_MUL_P5_TBL_NEXT_POINTER_OFFSET  3
+	#define OQ_LL_MUL_P5_TBL_NEXT_POINTER_LEN     11
+	#define OQ_LL_MUL_P5_TBL_NEXT_POINTER_DEFAULT 0x0
+
+struct oq_ll_mul_p5_tbl {
+	a_uint32_t  normal_fwd:1;
+	a_uint32_t  egress_mirr:1;
+	a_uint32_t  ingress_mirr:1;
+	a_uint32_t  next_pointer:11;
+	a_uint32_t  _reserved0:18;
+};
+
+union oq_ll_mul_p5_tbl_u {
+	a_uint32_t val;
+	struct oq_ll_mul_p5_tbl bf;
+};
+
+/*[table] OQ_LL_MUL_P6_TBL*/
+#define OQ_LL_MUL_P6_TBL
+#define OQ_LL_MUL_P6_TBL_ADDRESS 0x190000
+#define OQ_LL_MUL_P6_TBL_NUM     2048
+#define OQ_LL_MUL_P6_TBL_INC     0x10
+#define OQ_LL_MUL_P6_TBL_TYPE    REG_TYPE_RW
+#define OQ_LL_MUL_P6_TBL_DEFAULT 0x0
+	/*[field] NORMAL_FWD*/
+	#define OQ_LL_MUL_P6_TBL_NORMAL_FWD
+	#define OQ_LL_MUL_P6_TBL_NORMAL_FWD_OFFSET  0
+	#define OQ_LL_MUL_P6_TBL_NORMAL_FWD_LEN     1
+	#define OQ_LL_MUL_P6_TBL_NORMAL_FWD_DEFAULT 0x0
+	/*[field] EGRESS_MIRR*/
+	#define OQ_LL_MUL_P6_TBL_EGRESS_MIRR
+	#define OQ_LL_MUL_P6_TBL_EGRESS_MIRR_OFFSET  1
+	#define OQ_LL_MUL_P6_TBL_EGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P6_TBL_EGRESS_MIRR_DEFAULT 0x0
+	/*[field] INGRESS_MIRR*/
+	#define OQ_LL_MUL_P6_TBL_INGRESS_MIRR
+	#define OQ_LL_MUL_P6_TBL_INGRESS_MIRR_OFFSET  2
+	#define OQ_LL_MUL_P6_TBL_INGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P6_TBL_INGRESS_MIRR_DEFAULT 0x0
+	/*[field] NEXT_POINTER*/
+	#define OQ_LL_MUL_P6_TBL_NEXT_POINTER
+	#define OQ_LL_MUL_P6_TBL_NEXT_POINTER_OFFSET  3
+	#define OQ_LL_MUL_P6_TBL_NEXT_POINTER_LEN     11
+	#define OQ_LL_MUL_P6_TBL_NEXT_POINTER_DEFAULT 0x0
+
+struct oq_ll_mul_p6_tbl {
+	a_uint32_t  normal_fwd:1;
+	a_uint32_t  egress_mirr:1;
+	a_uint32_t  ingress_mirr:1;
+	a_uint32_t  next_pointer:11;
+	a_uint32_t  _reserved0:18;
+};
+
+union oq_ll_mul_p6_tbl_u {
+	a_uint32_t val;
+	struct oq_ll_mul_p6_tbl bf;
+};
+
+/*[table] OQ_LL_MUL_P7_TBL*/
+#define OQ_LL_MUL_P7_TBL
+#define OQ_LL_MUL_P7_TBL_ADDRESS 0x1b0000
+#define OQ_LL_MUL_P7_TBL_NUM     2048
+#define OQ_LL_MUL_P7_TBL_INC     0x10
+#define OQ_LL_MUL_P7_TBL_TYPE    REG_TYPE_RW
+#define OQ_LL_MUL_P7_TBL_DEFAULT 0x0
+	/*[field] NORMAL_FWD*/
+	#define OQ_LL_MUL_P7_TBL_NORMAL_FWD
+	#define OQ_LL_MUL_P7_TBL_NORMAL_FWD_OFFSET  0
+	#define OQ_LL_MUL_P7_TBL_NORMAL_FWD_LEN     1
+	#define OQ_LL_MUL_P7_TBL_NORMAL_FWD_DEFAULT 0x0
+	/*[field] EGRESS_MIRR*/
+	#define OQ_LL_MUL_P7_TBL_EGRESS_MIRR
+	#define OQ_LL_MUL_P7_TBL_EGRESS_MIRR_OFFSET  1
+	#define OQ_LL_MUL_P7_TBL_EGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P7_TBL_EGRESS_MIRR_DEFAULT 0x0
+	/*[field] INGRESS_MIRR*/
+	#define OQ_LL_MUL_P7_TBL_INGRESS_MIRR
+	#define OQ_LL_MUL_P7_TBL_INGRESS_MIRR_OFFSET  2
+	#define OQ_LL_MUL_P7_TBL_INGRESS_MIRR_LEN     1
+	#define OQ_LL_MUL_P7_TBL_INGRESS_MIRR_DEFAULT 0x0
+	/*[field] NEXT_POINTER*/
+	#define OQ_LL_MUL_P7_TBL_NEXT_POINTER
+	#define OQ_LL_MUL_P7_TBL_NEXT_POINTER_OFFSET  3
+	#define OQ_LL_MUL_P7_TBL_NEXT_POINTER_LEN     11
+	#define OQ_LL_MUL_P7_TBL_NEXT_POINTER_DEFAULT 0x0
+
+struct oq_ll_mul_p7_tbl {
+	a_uint32_t  normal_fwd:1;
+	a_uint32_t  egress_mirr:1;
+	a_uint32_t  ingress_mirr:1;
+	a_uint32_t  next_pointer:11;
+	a_uint32_t  _reserved0:18;
+};
+
+union oq_ll_mul_p7_tbl_u {
+	a_uint32_t val;
+	struct oq_ll_mul_p7_tbl bf;
+};
+
+/*[table] PKT_DESP_TBL*/
+#define PKT_DESP_TBL
+#define PKT_DESP_TBL_ADDRESS 0x1c0000
+#define PKT_DESP_TBL_NUM     2048
+#define PKT_DESP_TBL_INC     0x40
+#define PKT_DESP_TBL_TYPE    REG_TYPE_RW
+#define PKT_DESP_TBL_DEFAULT 0x0
+	/*[field] ORG_SRC_PORT_VP*/
+	#define PKT_DESP_TBL_ORG_SRC_PORT_VP
+	#define PKT_DESP_TBL_ORG_SRC_PORT_VP_OFFSET  0
+	#define PKT_DESP_TBL_ORG_SRC_PORT_VP_LEN     12
+	#define PKT_DESP_TBL_ORG_SRC_PORT_VP_DEFAULT 0x0
+	/*[field] SRC_PORT_VP*/
+	#define PKT_DESP_TBL_SRC_PORT_VP
+	#define PKT_DESP_TBL_SRC_PORT_VP_OFFSET  12
+	#define PKT_DESP_TBL_SRC_PORT_VP_LEN     12
+	#define PKT_DESP_TBL_SRC_PORT_VP_DEFAULT 0x0
+	/*[field] PACKET_LENGTH*/
+	#define PKT_DESP_TBL_PACKET_LENGTH
+	#define PKT_DESP_TBL_PACKET_LENGTH_OFFSET  24
+	#define PKT_DESP_TBL_PACKET_LENGTH_LEN     14
+	#define PKT_DESP_TBL_PACKET_LENGTH_DEFAULT 0x0
+	/*[field] TS_DIR*/
+	#define PKT_DESP_TBL_TS_DIR
+	#define PKT_DESP_TBL_TS_DIR_OFFSET  38
+	#define PKT_DESP_TBL_TS_DIR_LEN     1
+	#define PKT_DESP_TBL_TS_DIR_DEFAULT 0x0
+	/*[field] TX_TS_EN reuse TS_DIR[0]*/
+	#define PKT_DESP_TBL_TX_TS_EN
+	#define PKT_DESP_TBL_TX_TS_EN_OFFSET  39
+	#define PKT_DESP_TBL_TX_TS_EN_LEN     1
+	#define PKT_DESP_TBL_TX_TS_EN_DEFAULT 0x0
+	/*[field] RX_TS_VALID reuse TS_DIR[1]*/
+	#define PKT_DESP_TBL_RX_TS_VALID
+	#define PKT_DESP_TBL_RX_TS_VALID_OFFSET  39
+	#define PKT_DESP_TBL_RX_TS_VALID_LEN     1
+	#define PKT_DESP_TBL_RX_TS_VALID_DEFAULT 0x0
+	/*[field] RX_TS reuse TS_DIR[1]*/
+	#define PKT_DESP_TBL_RX_TS
+	#define PKT_DESP_TBL_RX_TS_OFFSET  40
+	#define PKT_DESP_TBL_RX_TS_LEN     40
+	#define PKT_DESP_TBL_RX_TS_DEFAULT 0x0
+	/*[field] TX_OS_CORRECTION_EN reuse TS_DIR[0]*/
+	#define PKT_DESP_TBL_TX_OS_CORRECTION_EN
+	#define PKT_DESP_TBL_TX_OS_CORRECTION_EN_OFFSET  40
+	#define PKT_DESP_TBL_TX_OS_CORRECTION_EN_LEN     1
+	#define PKT_DESP_TBL_TX_OS_CORRECTION_EN_DEFAULT 0x0
+	/*[field] TX_PTP_TAG reuse TS_DIR[0]*/
+	#define PKT_DESP_TBL_TX_PTP_TAG
+	#define PKT_DESP_TBL_TX_PTP_TAG_OFFSET  41
+	#define PKT_DESP_TBL_TX_PTP_TAG_LEN     10
+	#define PKT_DESP_TBL_TX_PTP_TAG_DEFAULT 0x0
+	/*[field] INT_PRI*/
+	#define PKT_DESP_TBL_INT_PRI
+	#define PKT_DESP_TBL_INT_PRI_OFFSET  80
+	#define PKT_DESP_TBL_INT_PRI_LEN     4
+	#define PKT_DESP_TBL_INT_PRI_DEFAULT 0x0
+	/*[field] INT_DP*/
+	#define PKT_DESP_TBL_INT_DP
+	#define PKT_DESP_TBL_INT_DP_OFFSET  84
+	#define PKT_DESP_TBL_INT_DP_LEN     2
+	#define PKT_DESP_TBL_INT_DP_DEFAULT 0x0
+	/*[field] CPU_CODE*/
+	#define PKT_DESP_TBL_CPU_CODE
+	#define PKT_DESP_TBL_CPU_CODE_OFFSET  86
+	#define PKT_DESP_TBL_CPU_CODE_LEN     8
+	#define PKT_DESP_TBL_CPU_CODE_DEFAULT 0x0
+	/*[field] SERVICE_CODE*/
+	#define PKT_DESP_TBL_SERVICE_CODE
+	#define PKT_DESP_TBL_SERVICE_CODE_OFFSET  94
+	#define PKT_DESP_TBL_SERVICE_CODE_LEN     8
+	#define PKT_DESP_TBL_SERVICE_CODE_DEFAULT 0x0
+	/*[field] DST_L3_IF*/
+	#define PKT_DESP_TBL_DST_L3_IF
+	#define PKT_DESP_TBL_DST_L3_IF_OFFSET  102
+	#define PKT_DESP_TBL_DST_L3_IF_LEN     8
+	#define PKT_DESP_TBL_DST_L3_IF_DEFAULT 0x0
+	/*[field] MAC_DA*/
+	#define PKT_DESP_TBL_MAC_DA
+	#define PKT_DESP_TBL_MAC_DA_OFFSET  110
+	#define PKT_DESP_TBL_MAC_DA_LEN     48
+	#define PKT_DESP_TBL_MAC_DA_DEFAULT 0x0
+	/*[field] ROUTE_FLAG*/
+	#define PKT_DESP_TBL_ROUTE_FLAG
+	#define PKT_DESP_TBL_ROUTE_FLAG_OFFSET  158
+	#define PKT_DESP_TBL_ROUTE_FLAG_LEN     1
+	#define PKT_DESP_TBL_ROUTE_FLAG_DEFAULT 0x0
+	/*[field] PPPOE_STRIP_FLAG*/
+	#define PKT_DESP_TBL_PPPOE_STRIP_FLAG
+	#define PKT_DESP_TBL_PPPOE_STRIP_FLAG_OFFSET  159
+	#define PKT_DESP_TBL_PPPOE_STRIP_FLAG_LEN     1
+	#define PKT_DESP_TBL_PPPOE_STRIP_FLAG_DEFAULT 0x0
+	/*[field] NAT_ACTION*/
+	#define PKT_DESP_TBL_NAT_ACTION
+	#define PKT_DESP_TBL_NAT_ACTION_OFFSET  160
+	#define PKT_DESP_TBL_NAT_ACTION_LEN     3
+	#define PKT_DESP_TBL_NAT_ACTION_DEFAULT 0x0
+	/*[field] NAPT_PORT*/
+	#define PKT_DESP_TBL_NAPT_PORT
+	#define PKT_DESP_TBL_NAPT_PORT_OFFSET  163
+	#define PKT_DESP_TBL_NAPT_PORT_LEN     16
+	#define PKT_DESP_TBL_NAPT_PORT_DEFAULT 0x0
+	/*[field] NAPT_ADDR*/
+	#define PKT_DESP_TBL_NAPT_ADDR
+	#define PKT_DESP_TBL_NAPT_ADDR_OFFSET  179
+	#define PKT_DESP_TBL_NAPT_ADDR_LEN     32
+	#define PKT_DESP_TBL_NAPT_ADDR_DEFAULT 0x0
+	/*[field] DSCP_UPDATE*/
+	#define PKT_DESP_TBL_DSCP_UPDATE
+	#define PKT_DESP_TBL_DSCP_UPDATE_OFFSET  211
+	#define PKT_DESP_TBL_DSCP_UPDATE_LEN     1
+	#define PKT_DESP_TBL_DSCP_UPDATE_DEFAULT 0x0
+	/*[field] DSCP*/
+	#define PKT_DESP_TBL_DSCP
+	#define PKT_DESP_TBL_DSCP_OFFSET  212
+	#define PKT_DESP_TBL_DSCP_LEN     8
+	#define PKT_DESP_TBL_DSCP_DEFAULT 0x0
+	/*[field] TTL_UPDATE*/
+	#define PKT_DESP_TBL_TTL_UPDATE
+	#define PKT_DESP_TBL_TTL_UPDATE_OFFSET  220
+	#define PKT_DESP_TBL_TTL_UPDATE_LEN     1
+	#define PKT_DESP_TBL_TTL_UPDATE_DEFAULT 0x0
+	/*[field] TTL*/
+	#define PKT_DESP_TBL_TTL
+	#define PKT_DESP_TBL_TTL_OFFSET  221
+	#define PKT_DESP_TBL_TTL_LEN     8
+	#define PKT_DESP_TBL_TTL_DEFAULT 0x0
+	/*[field] STAG_FLAG*/
+	#define PKT_DESP_TBL_STAG_FLAG
+	#define PKT_DESP_TBL_STAG_FLAG_OFFSET  229
+	#define PKT_DESP_TBL_STAG_FLAG_LEN     1
+	#define PKT_DESP_TBL_STAG_FLAG_DEFAULT 0x0
+	/*[field] CTAG_FLAG*/
+	#define PKT_DESP_TBL_CTAG_FLAG
+	#define PKT_DESP_TBL_CTAG_FLAG_OFFSET  230
+	#define PKT_DESP_TBL_CTAG_FLAG_LEN     1
+	#define PKT_DESP_TBL_CTAG_FLAG_DEFAULT 0x0
+	/*[field] SNAP_FLAG*/
+	#define PKT_DESP_TBL_SNAP_FLAG
+	#define PKT_DESP_TBL_SNAP_FLAG_OFFSET  231
+	#define PKT_DESP_TBL_SNAP_FLAG_LEN     1
+	#define PKT_DESP_TBL_SNAP_FLAG_DEFAULT 0x0
+	/*[field] PPPOE_FLAG*/
+	#define PKT_DESP_TBL_PPPOE_FLAG
+	#define PKT_DESP_TBL_PPPOE_FLAG_OFFSET  232
+	#define PKT_DESP_TBL_PPPOE_FLAG_LEN     1
+	#define PKT_DESP_TBL_PPPOE_FLAG_DEFAULT 0x0
+	/*[field] INT_STAG_FMT*/
+	#define PKT_DESP_TBL_INT_STAG_FMT
+	#define PKT_DESP_TBL_INT_STAG_FMT_OFFSET  233
+	#define PKT_DESP_TBL_INT_STAG_FMT_LEN     1
+	#define PKT_DESP_TBL_INT_STAG_FMT_DEFAULT 0x0
+	/*[field] INT_CTAG_FMT*/
+	#define PKT_DESP_TBL_INT_CTAG_FMT
+	#define PKT_DESP_TBL_INT_CTAG_FMT_OFFSET  234
+	#define PKT_DESP_TBL_INT_CTAG_FMT_LEN     1
+	#define PKT_DESP_TBL_INT_CTAG_FMT_DEFAULT 0x0
+	/*[field] INT_SVID*/
+	#define PKT_DESP_TBL_INT_SVID
+	#define PKT_DESP_TBL_INT_SVID_OFFSET  235
+	#define PKT_DESP_TBL_INT_SVID_LEN     12
+	#define PKT_DESP_TBL_INT_SVID_DEFAULT 0x0
+	/*[field] INT_CVID*/
+	#define PKT_DESP_TBL_INT_CVID
+	#define PKT_DESP_TBL_INT_CVID_OFFSET  247
+	#define PKT_DESP_TBL_INT_CVID_LEN     12
+	#define PKT_DESP_TBL_INT_CVID_DEFAULT 0x0
+	/*[field] INT_SPCP*/
+	#define PKT_DESP_TBL_INT_SPCP
+	#define PKT_DESP_TBL_INT_SPCP_OFFSET  259
+	#define PKT_DESP_TBL_INT_SPCP_LEN     3
+	#define PKT_DESP_TBL_INT_SPCP_DEFAULT 0x0
+	/*[field] INT_CPCP*/
+	#define PKT_DESP_TBL_INT_CPCP
+	#define PKT_DESP_TBL_INT_CPCP_OFFSET  262
+	#define PKT_DESP_TBL_INT_CPCP_LEN     3
+	#define PKT_DESP_TBL_INT_CPCP_DEFAULT 0x0
+	/*[field] INT_SDEI*/
+	#define PKT_DESP_TBL_INT_SDEI
+	#define PKT_DESP_TBL_INT_SDEI_OFFSET  265
+	#define PKT_DESP_TBL_INT_SDEI_LEN     1
+	#define PKT_DESP_TBL_INT_SDEI_DEFAULT 0x0
+	/*[field] INT_CDEI*/
+	#define PKT_DESP_TBL_INT_CDEI
+	#define PKT_DESP_TBL_INT_CDEI_OFFSET  266
+	#define PKT_DESP_TBL_INT_CDEI_LEN     1
+	#define PKT_DESP_TBL_INT_CDEI_DEFAULT 0x0
+	/*[field] VSI*/
+	#define PKT_DESP_TBL_VSI
+	#define PKT_DESP_TBL_VSI_OFFSET  267
+	#define PKT_DESP_TBL_VSI_LEN     5
+	#define PKT_DESP_TBL_VSI_DEFAULT 0x0
+	/*[field] L3_OFFSET*/
+	#define PKT_DESP_TBL_L3_OFFSET
+	#define PKT_DESP_TBL_L3_OFFSET_OFFSET  272
+	#define PKT_DESP_TBL_L3_OFFSET_LEN     8
+	#define PKT_DESP_TBL_L3_OFFSET_DEFAULT 0x0
+	/*[field] L3_TYPE*/
+	#define PKT_DESP_TBL_L3_TYPE
+	#define PKT_DESP_TBL_L3_TYPE_OFFSET  280
+	#define PKT_DESP_TBL_L3_TYPE_LEN     2
+	#define PKT_DESP_TBL_L3_TYPE_DEFAULT 0x0
+	/*[field] L4_OFFSET*/
+	#define PKT_DESP_TBL_L4_OFFSET
+	#define PKT_DESP_TBL_L4_OFFSET_OFFSET  282
+	#define PKT_DESP_TBL_L4_OFFSET_LEN     8
+	#define PKT_DESP_TBL_L4_OFFSET_DEFAULT 0x0
+	/*[field] L4_TYPE*/
+	#define PKT_DESP_TBL_L4_TYPE
+	#define PKT_DESP_TBL_L4_TYPE_OFFSET  290
+	#define PKT_DESP_TBL_L4_TYPE_LEN     3
+	#define PKT_DESP_TBL_L4_TYPE_DEFAULT 0x0
+	/*[field] NEXT_HEADER*/
+	#define PKT_DESP_TBL_NEXT_HEADER
+	#define PKT_DESP_TBL_NEXT_HEADER_OFFSET  293
+	#define PKT_DESP_TBL_NEXT_HEADER_LEN     8
+	#define PKT_DESP_TBL_NEXT_HEADER_DEFAULT 0x0
+	/*[field] EG_VLAN_TAG_FMT_BYPASS_EN*/
+	#define PKT_DESP_TBL_EG_VLAN_TAG_FMT_BYPASS_EN
+	#define PKT_DESP_TBL_EG_VLAN_TAG_FMT_BYPASS_EN_OFFSET  301
+	#define PKT_DESP_TBL_EG_VLAN_TAG_FMT_BYPASS_EN_LEN     1
+	#define PKT_DESP_TBL_EG_VLAN_TAG_FMT_BYPASS_EN_DEFAULT 0x0
+	/*[field] EG_VLAN_XLT_BYPASS_EN*/
+	#define PKT_DESP_TBL_EG_VLAN_XLT_BYPASS_EN
+	#define PKT_DESP_TBL_EG_VLAN_XLT_BYPASS_EN_OFFSET  302
+	#define PKT_DESP_TBL_EG_VLAN_XLT_BYPASS_EN_LEN     1
+	#define PKT_DESP_TBL_EG_VLAN_XLT_BYPASS_EN_DEFAULT 0x0
+	/*[field] PKT_L2_EDIT_BYPASS*/
+	#define PKT_DESP_TBL_PKT_L2_EDIT_BYPASS
+	#define PKT_DESP_TBL_PKT_L2_EDIT_BYPASS_OFFSET  303
+	#define PKT_DESP_TBL_PKT_L2_EDIT_BYPASS_LEN     1
+	#define PKT_DESP_TBL_PKT_L2_EDIT_BYPASS_DEFAULT 0x0
+	/*[field] PKT_L3_EDIT_BYPASS*/
+	#define PKT_DESP_TBL_PKT_L3_EDIT_BYPASS
+	#define PKT_DESP_TBL_PKT_L3_EDIT_BYPASS_OFFSET  304
+	#define PKT_DESP_TBL_PKT_L3_EDIT_BYPASS_LEN     1
+	#define PKT_DESP_TBL_PKT_L3_EDIT_BYPASS_DEFAULT 0x0
+	/*[field] ACL_INDEX_TOGGLE*/
+	#define PKT_DESP_TBL_ACL_INDEX_TOGGLE
+	#define PKT_DESP_TBL_ACL_INDEX_TOGGLE_OFFSET  305
+	#define PKT_DESP_TBL_ACL_INDEX_TOGGLE_LEN     1
+	#define PKT_DESP_TBL_ACL_INDEX_TOGGLE_DEFAULT 0x0
+	/*[field] ACL_INDEX_VALID*/
+	#define PKT_DESP_TBL_ACL_INDEX_VALID
+	#define PKT_DESP_TBL_ACL_INDEX_VALID_OFFSET  306
+	#define PKT_DESP_TBL_ACL_INDEX_VALID_LEN     1
+	#define PKT_DESP_TBL_ACL_INDEX_VALID_DEFAULT 0x0
+	/*[field] ACL_INDEX*/
+	#define PKT_DESP_TBL_ACL_INDEX
+	#define PKT_DESP_TBL_ACL_INDEX_OFFSET  307
+	#define PKT_DESP_TBL_ACL_INDEX_LEN     9
+	#define PKT_DESP_TBL_ACL_INDEX_DEFAULT 0x0
+	/*[field] IP_ADDR_INDEX_TYPE*/
+	#define PKT_DESP_TBL_IP_ADDR_INDEX_TYPE
+	#define PKT_DESP_TBL_IP_ADDR_INDEX_TYPE_OFFSET  316
+	#define PKT_DESP_TBL_IP_ADDR_INDEX_TYPE_LEN     1
+	#define PKT_DESP_TBL_IP_ADDR_INDEX_TYPE_DEFAULT 0x0
+	/*[field] IP_ADDR_INDEX_TOGGLE*/
+	#define PKT_DESP_TBL_IP_ADDR_INDEX_TOGGLE
+	#define PKT_DESP_TBL_IP_ADDR_INDEX_TOGGLE_OFFSET  317
+	#define PKT_DESP_TBL_IP_ADDR_INDEX_TOGGLE_LEN     1
+	#define PKT_DESP_TBL_IP_ADDR_INDEX_TOGGLE_DEFAULT 0x0
+	/*[field] IP_ADDR_INDEX_VALID*/
+	#define PKT_DESP_TBL_IP_ADDR_INDEX_VALID
+	#define PKT_DESP_TBL_IP_ADDR_INDEX_VALID_OFFSET  318
+	#define PKT_DESP_TBL_IP_ADDR_INDEX_VALID_LEN     1
+	#define PKT_DESP_TBL_IP_ADDR_INDEX_VALID_DEFAULT 0x0
+	/*[field] IP_ADDR_INDEX*/
+	#define PKT_DESP_TBL_IP_ADDR_INDEX
+	#define PKT_DESP_TBL_IP_ADDR_INDEX_OFFSET  319
+	#define PKT_DESP_TBL_IP_ADDR_INDEX_LEN     13
+	#define PKT_DESP_TBL_IP_ADDR_INDEX_DEFAULT 0x0
+	/*[field] CHG_PORT_VP*/
+	#define PKT_DESP_TBL_CHG_PORT_VP
+	#define PKT_DESP_TBL_CHG_PORT_VP_OFFSET  332
+	#define PKT_DESP_TBL_CHG_PORT_VP_LEN     12
+	#define PKT_DESP_TBL_CHG_PORT_VP_DEFAULT 0x0
+	/*[field] HASH_FLAG*/
+	#define PKT_DESP_TBL_HASH_FLAG
+	#define PKT_DESP_TBL_HASH_FLAG_OFFSET  344
+	#define PKT_DESP_TBL_HASH_FLAG_LEN     3
+	#define PKT_DESP_TBL_HASH_FLAG_DEFAULT 0x0
+	/*[field] HASH_VALUE*/
+	#define PKT_DESP_TBL_HASH_VALUE
+	#define PKT_DESP_TBL_HASH_VALUE_OFFSET  347
+	#define PKT_DESP_TBL_HASH_VALUE_LEN     21
+	#define PKT_DESP_TBL_HASH_VALUE_DEFAULT 0x0
+	/*[field] COPY_CPU_FLAG*/
+	#define PKT_DESP_TBL_COPY_CPU_FLAG
+	#define PKT_DESP_TBL_COPY_CPU_FLAG_OFFSET  368
+	#define PKT_DESP_TBL_COPY_CPU_FLAG_LEN     1
+	#define PKT_DESP_TBL_COPY_CPU_FLAG_DEFAULT 0x0
+	/*[field] SRC_PN*/
+	#define PKT_DESP_TBL_SRC_PN
+	#define PKT_DESP_TBL_SRC_PN_OFFSET  369
+	#define PKT_DESP_TBL_SRC_PN_LEN     4
+	#define PKT_DESP_TBL_SRC_PN_DEFAULT 0x0
+	/*[field] RX_PTP_TYPE*/
+	#define PKT_DESP_TBL_RX_PTP_TYPE
+	#define PKT_DESP_TBL_RX_PTP_TYPE_OFFSET  373
+	#define PKT_DESP_TBL_RX_PTP_TYPE_LEN     4
+	#define PKT_DESP_TBL_RX_PTP_TYPE_DEFAULT 0x0
+	/*[field] FAKE_L2_PROT*/
+	#define PKT_DESP_TBL_FAKE_L2_PROT
+	#define PKT_DESP_TBL_FAKE_L2_PROT_OFFSET  377
+	#define PKT_DESP_TBL_FAKE_L2_PROT_LEN     1
+	#define PKT_DESP_TBL_FAKE_L2_PROT_DEFAULT 0x0
+	/*[field] FAKE_MAC_HEADER*/
+	#define PKT_DESP_TBL_FAKE_MAC_HEADER
+	#define PKT_DESP_TBL_FAKE_MAC_HEADER_OFFSET  378
+	#define PKT_DESP_TBL_FAKE_MAC_HEADER_LEN     1
+	#define PKT_DESP_TBL_FAKE_MAC_HEADER_DEFAULT 0x0
+	/*[field] VSI_VALID*/
+	#define PKT_DESP_TBL_VSI_VALID
+	#define PKT_DESP_TBL_VSI_VALID_OFFSET  379
+	#define PKT_DESP_TBL_VSI_VALID_LEN     1
+	#define PKT_DESP_TBL_VSI_VALID_DEFAULT 0x0
+	/*[field] VP_TX_CNT_EN*/
+	#define PKT_DESP_TBL_VP_TX_CNT_EN
+	#define PKT_DESP_TBL_VP_TX_CNT_EN_OFFSET  380
+	#define PKT_DESP_TBL_VP_TX_CNT_EN_LEN     1
+	#define PKT_DESP_TBL_VP_TX_CNT_EN_DEFAULT 0x0
+	/*[field] RSV0*/
+	#define PKT_DESP_TBL_RSV0
+	#define PKT_DESP_TBL_RSV0_OFFSET  381
+	#define PKT_DESP_TBL_RSV0_LEN     7
+	#define PKT_DESP_TBL_RSV0_DEFAULT 0x0
+	/*[field] AC_GROUP_BITMAP*/
+	#define PKT_DESP_TBL_AC_GROUP_BITMAP
+	#define PKT_DESP_TBL_AC_GROUP_BITMAP_OFFSET  388
+	#define PKT_DESP_TBL_AC_GROUP_BITMAP_LEN     4
+	#define PKT_DESP_TBL_AC_GROUP_BITMAP_DEFAULT 0x0
+	/*[field] ONE_ENQ_FLAG*/
+	#define PKT_DESP_TBL_ONE_ENQ_FLAG
+	#define PKT_DESP_TBL_ONE_ENQ_FLAG_OFFSET  392
+	#define PKT_DESP_TBL_ONE_ENQ_FLAG_LEN     1
+	#define PKT_DESP_TBL_ONE_ENQ_FLAG_DEFAULT 0x0
+	/*[field] EDMA_VP*/
+	#define PKT_DESP_TBL_EDMA_VP
+	#define PKT_DESP_TBL_EDMA_VP_OFFSET  393
+	#define PKT_DESP_TBL_EDMA_VP_LEN     3
+	#define PKT_DESP_TBL_EDMA_VP_DEFAULT 0x0
+	/*[field] FC_GRP_ID*/
+	#define PKT_DESP_TBL_FC_GRP_ID
+	#define PKT_DESP_TBL_FC_GRP_ID_OFFSET  396
+	#define PKT_DESP_TBL_FC_GRP_ID_LEN     3
+	#define PKT_DESP_TBL_FC_GRP_ID_DEFAULT 0x0
+	/*[field] FC_EN*/
+	#define PKT_DESP_TBL_FC_EN
+	#define PKT_DESP_TBL_FC_EN_OFFSET  399
+	#define PKT_DESP_TBL_FC_EN_LEN     1
+	#define PKT_DESP_TBL_FC_EN_DEFAULT 0x0
+
+struct pkt_desp_tbl_0 {
+	a_uint32_t  org_src_port_vp:12;
+	a_uint32_t  src_port_vp:12;
+	a_uint32_t  packet_length_0:8;
+	a_uint32_t  packet_length_1:6;
+	a_uint32_t  ts_dir:1;
+	a_uint32_t  tx_ts_en:1;
+	a_uint32_t  tx_os_correction_en:1;
+	a_uint32_t  tx_ptp_tag:10;
+	a_uint32_t  _reserved0_0:13;
+	a_uint32_t  _reserved0_1:16;
+	a_uint32_t  int_pri:4;
+	a_uint32_t  int_dp:2;
+	a_uint32_t  cpu_code:8;
+	a_uint32_t  service_code_0:2;
+	a_uint32_t  service_code_1:6;
+	a_uint32_t  dst_l3_if:8;
+	a_uint32_t  mac_da_0:18;
+	a_uint32_t  mac_da_1:30;
+	a_uint32_t  route_flag:1;
+	a_uint32_t  pppoe_strip_flag:1;
+	a_uint32_t  nat_action:3;
+	a_uint32_t  napt_port:16;
+	a_uint32_t  napt_addr_0:13;
+	a_uint32_t  napt_addr_1:19;
+	a_uint32_t  dscp_update:1;
+	a_uint32_t  dscp:8;
+	a_uint32_t  ttl_update:1;
+	a_uint32_t  ttl_0:3;
+	a_uint32_t  ttl_1:5;
+	a_uint32_t  stag_flag:1;
+	a_uint32_t  ctag_flag:1;
+	a_uint32_t  snap_flag:1;
+	a_uint32_t  pppoe_flag:1;
+	a_uint32_t  int_stag_fmt:1;
+	a_uint32_t  int_ctag_fmt:1;
+	a_uint32_t  int_svid:12;
+	a_uint32_t  int_cvid_0:9;
+	a_uint32_t  int_cvid_1:3;
+	a_uint32_t  int_spcp:3;
+	a_uint32_t  int_cpcp:3;
+	a_uint32_t  int_sdei:1;
+	a_uint32_t  int_cdei:1;
+	a_uint32_t  vsi:5;
+	a_uint32_t  l3_offset:8;
+	a_uint32_t  l3_type:2;
+	a_uint32_t  l4_offset_0:6;
+	a_uint32_t  l4_offset_1:2;
+	a_uint32_t  l4_type:3;
+	a_uint32_t  next_header:8;
+	a_uint32_t  eg_vlan_tag_fmt_bypass_en:1;
+	a_uint32_t  eg_vlan_xlt_bypass_en:1;
+	a_uint32_t  pkt_l2_edit_bypass:1;
+	a_uint32_t  pkt_l3_edit_bypass:1;
+	a_uint32_t  acl_index_toggle:1;
+	a_uint32_t  acl_index_valid:1;
+	a_uint32_t  acl_index:9;
+	a_uint32_t  ip_addr_index_type:1;
+	a_uint32_t  ip_addr_index_toggle:1;
+	a_uint32_t  ip_addr_index_valid:1;
+	a_uint32_t  ip_addr_index_0:1;
+	a_uint32_t  ip_addr_index_1:12;
+	a_uint32_t  chg_port_vp:12;
+	a_uint32_t  hash_flag:3;
+	a_uint32_t  hash_value_0:5;
+	a_uint32_t  hash_value_1:16;
+	a_uint32_t  copy_cpu_flag:1;
+	a_uint32_t  src_pn:4;
+	a_uint32_t  rx_ptp_type:4;
+	a_uint32_t  fake_l2_prot:1;
+	a_uint32_t  fake_mac_header:1;
+	a_uint32_t  vsi_valid:1;
+	a_uint32_t  vp_tx_cnt_en:1;
+	a_uint32_t  rsv0_0:3;
+	a_uint32_t  rsv0_1:4;
+	a_uint32_t  ac_group_bitmap:4;
+	a_uint32_t  one_enq_flag:1;
+	a_uint32_t  edma_vp:3;
+	a_uint32_t  fc_grp_id:3;
+	a_uint32_t  fc_en:1;
+	a_uint32_t  _reserved1:16;
+};
+
+struct pkt_desp_tbl_1 {
+	a_uint32_t  org_src_port_vp:12;
+	a_uint32_t  src_port_vp:12;
+	a_uint32_t  packet_length_0:8;
+	a_uint32_t  packet_length_1:6;
+	a_uint32_t  ts_dir:1;
+	a_uint32_t  rx_ts_valid:1;
+	a_uint32_t  rx_ts_0:24;
+	a_uint32_t  rx_ts_1:16;
+	a_uint32_t  int_pri:4;
+	a_uint32_t  int_dp:2;
+	a_uint32_t  cpu_code:8;
+	a_uint32_t  service_code_0:2;
+	a_uint32_t  service_code_1:6;
+	a_uint32_t  dst_l3_if:8;
+	a_uint32_t  mac_da_0:18;
+	a_uint32_t  mac_da_1:30;
+	a_uint32_t  route_flag:1;
+	a_uint32_t  pppoe_strip_flag:1;
+	a_uint32_t  nat_action:3;
+	a_uint32_t  napt_port:16;
+	a_uint32_t  napt_addr_0:13;
+	a_uint32_t  napt_addr_1:19;
+	a_uint32_t  dscp_update:1;
+	a_uint32_t  dscp:8;
+	a_uint32_t  ttl_update:1;
+	a_uint32_t  ttl_0:3;
+	a_uint32_t  ttl_1:5;
+	a_uint32_t  stag_flag:1;
+	a_uint32_t  ctag_flag:1;
+	a_uint32_t  snap_flag:1;
+	a_uint32_t  pppoe_flag:1;
+	a_uint32_t  int_stag_fmt:1;
+	a_uint32_t  int_ctag_fmt:1;
+	a_uint32_t  int_svid:12;
+	a_uint32_t  int_cvid_0:9;
+	a_uint32_t  int_cvid_1:3;
+	a_uint32_t  int_spcp:3;
+	a_uint32_t  int_cpcp:3;
+	a_uint32_t  int_sdei:1;
+	a_uint32_t  int_cdei:1;
+	a_uint32_t  vsi:5;
+	a_uint32_t  l3_offset:8;
+	a_uint32_t  l3_type:2;
+	a_uint32_t  l4_offset_0:6;
+	a_uint32_t  l4_offset_1:2;
+	a_uint32_t  l4_type:3;
+	a_uint32_t  next_header:8;
+	a_uint32_t  eg_vlan_tag_fmt_bypass_en:1;
+	a_uint32_t  eg_vlan_xlt_bypass_en:1;
+	a_uint32_t  pkt_l2_edit_bypass:1;
+	a_uint32_t  pkt_l3_edit_bypass:1;
+	a_uint32_t  acl_index_toggle:1;
+	a_uint32_t  acl_index_valid:1;
+	a_uint32_t  acl_index:9;
+	a_uint32_t  ip_addr_index_type:1;
+	a_uint32_t  ip_addr_index_toggle:1;
+	a_uint32_t  ip_addr_index_valid:1;
+	a_uint32_t  ip_addr_index_0:1;
+	a_uint32_t  ip_addr_index_1:12;
+	a_uint32_t  chg_port_vp:12;
+	a_uint32_t  hash_flag:3;
+	a_uint32_t  hash_value_0:5;
+	a_uint32_t  hash_value_1:16;
+	a_uint32_t  copy_cpu_flag:1;
+	a_uint32_t  src_pn:4;
+	a_uint32_t  rx_ptp_type:4;
+	a_uint32_t  fake_l2_prot:1;
+	a_uint32_t  fake_mac_header:1;
+	a_uint32_t  vsi_valid:1;
+	a_uint32_t  vp_tx_cnt_en:1;
+	a_uint32_t  rsv0_0:3;
+	a_uint32_t  rsv0_1:4;
+	a_uint32_t  ac_group_bitmap:4;
+	a_uint32_t  one_enq_flag:1;
+	a_uint32_t  edma_vp:3;
+	a_uint32_t  fc_grp_id:3;
+	a_uint32_t  fc_en:1;
+	a_uint32_t  _reserved0:16;
+};
+
+union pkt_desp_tbl_u {
+	a_uint32_t val[13];
+	struct pkt_desp_tbl_0 bf0;
+	struct pkt_desp_tbl_1 bf1;
+};
+
+/*[table] UNI_DROP_CNT_TBL*/
+#define UNI_DROP_CNT_TBL
+#define UNI_DROP_CNT_TBL_ADDRESS 0x1e0000
+#define UNI_DROP_CNT_TBL_NUM     1536
+#define UNI_DROP_CNT_TBL_INC     0x10
+#define UNI_DROP_CNT_TBL_TYPE    REG_TYPE_RW
+#define UNI_DROP_CNT_TBL_DEFAULT 0x0
+	/*[field] UNI_DROP_PKT*/
+	#define UNI_DROP_CNT_TBL_UNI_DROP_PKT
+	#define UNI_DROP_CNT_TBL_UNI_DROP_PKT_OFFSET  0
+	#define UNI_DROP_CNT_TBL_UNI_DROP_PKT_LEN     32
+	#define UNI_DROP_CNT_TBL_UNI_DROP_PKT_DEFAULT 0x0
+	/*[field] UNI_DROP_BYTE*/
+	#define UNI_DROP_CNT_TBL_UNI_DROP_BYTE
+	#define UNI_DROP_CNT_TBL_UNI_DROP_BYTE_OFFSET  32
+	#define UNI_DROP_CNT_TBL_UNI_DROP_BYTE_LEN     40
+	#define UNI_DROP_CNT_TBL_UNI_DROP_BYTE_DEFAULT 0x0
+
+struct uni_drop_cnt_tbl {
+	a_uint32_t  uni_drop_pkt:32;
+	a_uint32_t  uni_drop_byte_0:32;
+	a_uint32_t  uni_drop_byte_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union uni_drop_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct uni_drop_cnt_tbl bf;
+};
+
+/*[table] MUL_P0_DROP_CNT_TBL*/
+#define MUL_P0_DROP_CNT_TBL
+#define MUL_P0_DROP_CNT_TBL_ADDRESS 0x1f0000
+#define MUL_P0_DROP_CNT_TBL_NUM     48
+#define MUL_P0_DROP_CNT_TBL_INC     0x10
+#define MUL_P0_DROP_CNT_TBL_TYPE    REG_TYPE_RW
+#define MUL_P0_DROP_CNT_TBL_DEFAULT 0x0
+	/*[field] MUL_P0_DROP_PKT*/
+	#define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_PKT
+	#define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_PKT_OFFSET  0
+	#define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_PKT_LEN     32
+	#define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_PKT_DEFAULT 0x0
+	/*[field] MUL_P0_DROP_BYTE*/
+	#define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_BYTE
+	#define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_BYTE_OFFSET  32
+	#define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_BYTE_LEN     40
+	#define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_BYTE_DEFAULT 0x0
+
+struct mul_p0_drop_cnt_tbl {
+	a_uint32_t  mul_p0_drop_pkt:32;
+	a_uint32_t  mul_p0_drop_byte_0:32;
+	a_uint32_t  mul_p0_drop_byte_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union mul_p0_drop_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct mul_p0_drop_cnt_tbl bf;
+};
+
+/*[table] MUL_P1_DROP_CNT_TBL*/
+#define MUL_P1_DROP_CNT_TBL
+#define MUL_P1_DROP_CNT_TBL_ADDRESS 0x1f1000
+#define MUL_P1_DROP_CNT_TBL_NUM     12
+#define MUL_P1_DROP_CNT_TBL_INC     0x10
+#define MUL_P1_DROP_CNT_TBL_TYPE    REG_TYPE_RW
+#define MUL_P1_DROP_CNT_TBL_DEFAULT 0x0
+	/*[field] MUL_P1_DROP_PKT*/
+	#define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_PKT
+	#define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_PKT_OFFSET  0
+	#define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_PKT_LEN     32
+	#define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_PKT_DEFAULT 0x0
+	/*[field] MUL_P1_DROP_BYTE*/
+	#define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_BYTE
+	#define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_BYTE_OFFSET  32
+	#define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_BYTE_LEN     40
+	#define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_BYTE_DEFAULT 0x0
+
+struct mul_p1_drop_cnt_tbl {
+	a_uint32_t  mul_p1_drop_pkt:32;
+	a_uint32_t  mul_p1_drop_byte_0:32;
+	a_uint32_t  mul_p1_drop_byte_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union mul_p1_drop_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct mul_p1_drop_cnt_tbl bf;
+};
+
+/*[table] MUL_P2_DROP_CNT_TBL*/
+#define MUL_P2_DROP_CNT_TBL
+#define MUL_P2_DROP_CNT_TBL_ADDRESS 0x1f2000
+#define MUL_P2_DROP_CNT_TBL_NUM     12
+#define MUL_P2_DROP_CNT_TBL_INC     0x10
+#define MUL_P2_DROP_CNT_TBL_TYPE    REG_TYPE_RW
+#define MUL_P2_DROP_CNT_TBL_DEFAULT 0x0
+	/*[field] MUL_P2_DROP_PKT*/
+	#define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_PKT
+	#define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_PKT_OFFSET  0
+	#define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_PKT_LEN     32
+	#define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_PKT_DEFAULT 0x0
+	/*[field] MUL_P2_DROP_BYTE*/
+	#define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_BYTE
+	#define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_BYTE_OFFSET  32
+	#define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_BYTE_LEN     40
+	#define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_BYTE_DEFAULT 0x0
+
+struct mul_p2_drop_cnt_tbl {
+	a_uint32_t  mul_p2_drop_pkt:32;
+	a_uint32_t  mul_p2_drop_byte_0:32;
+	a_uint32_t  mul_p2_drop_byte_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union mul_p2_drop_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct mul_p2_drop_cnt_tbl bf;
+};
+
+/*[table] MUL_P3_DROP_CNT_TBL*/
+#define MUL_P3_DROP_CNT_TBL
+#define MUL_P3_DROP_CNT_TBL_ADDRESS 0x1f3000
+#define MUL_P3_DROP_CNT_TBL_NUM     12
+#define MUL_P3_DROP_CNT_TBL_INC     0x10
+#define MUL_P3_DROP_CNT_TBL_TYPE    REG_TYPE_RW
+#define MUL_P3_DROP_CNT_TBL_DEFAULT 0x0
+	/*[field] MUL_P3_DROP_PKT*/
+	#define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_PKT
+	#define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_PKT_OFFSET  0
+	#define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_PKT_LEN     32
+	#define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_PKT_DEFAULT 0x0
+	/*[field] MUL_P3_DROP_BYTE*/
+	#define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_BYTE
+	#define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_BYTE_OFFSET  32
+	#define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_BYTE_LEN     40
+	#define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_BYTE_DEFAULT 0x0
+
+struct mul_p3_drop_cnt_tbl {
+	a_uint32_t  mul_p3_drop_pkt:32;
+	a_uint32_t  mul_p3_drop_byte_0:32;
+	a_uint32_t  mul_p3_drop_byte_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union mul_p3_drop_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct mul_p3_drop_cnt_tbl bf;
+};
+
+/*[table] MUL_P4_DROP_CNT_TBL*/
+#define MUL_P4_DROP_CNT_TBL
+#define MUL_P4_DROP_CNT_TBL_ADDRESS 0x1f4000
+#define MUL_P4_DROP_CNT_TBL_NUM     12
+#define MUL_P4_DROP_CNT_TBL_INC     0x10
+#define MUL_P4_DROP_CNT_TBL_TYPE    REG_TYPE_RW
+#define MUL_P4_DROP_CNT_TBL_DEFAULT 0x0
+	/*[field] MUL_P4_DROP_PKT*/
+	#define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_PKT
+	#define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_PKT_OFFSET  0
+	#define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_PKT_LEN     32
+	#define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_PKT_DEFAULT 0x0
+	/*[field] MUL_P4_DROP_BYTE*/
+	#define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_BYTE
+	#define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_BYTE_OFFSET  32
+	#define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_BYTE_LEN     40
+	#define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_BYTE_DEFAULT 0x0
+
+struct mul_p4_drop_cnt_tbl {
+	a_uint32_t  mul_p4_drop_pkt:32;
+	a_uint32_t  mul_p4_drop_byte_0:32;
+	a_uint32_t  mul_p4_drop_byte_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union mul_p4_drop_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct mul_p4_drop_cnt_tbl bf;
+};
+
+/*[table] MUL_P5_DROP_CNT_TBL*/
+#define MUL_P5_DROP_CNT_TBL
+#define MUL_P5_DROP_CNT_TBL_ADDRESS 0x1f5000
+#define MUL_P5_DROP_CNT_TBL_NUM     12
+#define MUL_P5_DROP_CNT_TBL_INC     0x10
+#define MUL_P5_DROP_CNT_TBL_TYPE    REG_TYPE_RW
+#define MUL_P5_DROP_CNT_TBL_DEFAULT 0x0
+	/*[field] MUL_P5_DROP_PKT*/
+	#define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_PKT
+	#define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_PKT_OFFSET  0
+	#define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_PKT_LEN     32
+	#define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_PKT_DEFAULT 0x0
+	/*[field] MUL_P5_DROP_BYTE*/
+	#define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_BYTE
+	#define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_BYTE_OFFSET  32
+	#define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_BYTE_LEN     40
+	#define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_BYTE_DEFAULT 0x0
+
+struct mul_p5_drop_cnt_tbl {
+	a_uint32_t  mul_p5_drop_pkt:32;
+	a_uint32_t  mul_p5_drop_byte_0:32;
+	a_uint32_t  mul_p5_drop_byte_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union mul_p5_drop_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct mul_p5_drop_cnt_tbl bf;
+};
+
+/*[table] MUL_P6_DROP_CNT_TBL*/
+#define MUL_P6_DROP_CNT_TBL
+#define MUL_P6_DROP_CNT_TBL_ADDRESS 0x1f6000
+#define MUL_P6_DROP_CNT_TBL_NUM     12
+#define MUL_P6_DROP_CNT_TBL_INC     0x10
+#define MUL_P6_DROP_CNT_TBL_TYPE    REG_TYPE_RW
+#define MUL_P6_DROP_CNT_TBL_DEFAULT 0x0
+	/*[field] MUL_P6_DROP_PKT*/
+	#define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_PKT
+	#define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_PKT_OFFSET  0
+	#define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_PKT_LEN     32
+	#define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_PKT_DEFAULT 0x0
+	/*[field] MUL_P6_DROP_BYTE*/
+	#define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_BYTE
+	#define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_BYTE_OFFSET  32
+	#define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_BYTE_LEN     40
+	#define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_BYTE_DEFAULT 0x0
+
+struct mul_p6_drop_cnt_tbl {
+	a_uint32_t  mul_p6_drop_pkt:32;
+	a_uint32_t  mul_p6_drop_byte_0:32;
+	a_uint32_t  mul_p6_drop_byte_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union mul_p6_drop_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct mul_p6_drop_cnt_tbl bf;
+};
+
+/*[table] MUL_P7_DROP_CNT_TBL*/
+#define MUL_P7_DROP_CNT_TBL
+#define MUL_P7_DROP_CNT_TBL_ADDRESS 0x1f7000
+#define MUL_P7_DROP_CNT_TBL_NUM     12
+#define MUL_P7_DROP_CNT_TBL_INC     0x10
+#define MUL_P7_DROP_CNT_TBL_TYPE    REG_TYPE_RW
+#define MUL_P7_DROP_CNT_TBL_DEFAULT 0x0
+	/*[field] MUL_P7_DROP_PKT*/
+	#define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_PKT
+	#define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_PKT_OFFSET  0
+	#define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_PKT_LEN     32
+	#define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_PKT_DEFAULT 0x0
+	/*[field] MUL_P7_DROP_BYTE*/
+	#define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_BYTE
+	#define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_BYTE_OFFSET  32
+	#define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_BYTE_LEN     40
+	#define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_BYTE_DEFAULT 0x0
+
+struct mul_p7_drop_cnt_tbl {
+	a_uint32_t  mul_p7_drop_pkt:32;
+	a_uint32_t  mul_p7_drop_byte_0:32;
+	a_uint32_t  mul_p7_drop_byte_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union mul_p7_drop_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct mul_p7_drop_cnt_tbl bf;
+};
+
+/*[table] UQ_AGG_PROFILE_MAP*/
+#define UQ_AGG_PROFILE_MAP
+#define UQ_AGG_PROFILE_MAP_ADDRESS 0x1f8000
+#define UQ_AGG_PROFILE_MAP_NUM     256
+#define UQ_AGG_PROFILE_MAP_INC     0x10
+#define UQ_AGG_PROFILE_MAP_TYPE    REG_TYPE_RW
+#define UQ_AGG_PROFILE_MAP_DEFAULT 0x0
+	/*[field] QID_2_AGG_ID*/
+	#define UQ_AGG_PROFILE_MAP_QID_2_AGG_ID
+	#define UQ_AGG_PROFILE_MAP_QID_2_AGG_ID_OFFSET  0
+	#define UQ_AGG_PROFILE_MAP_QID_2_AGG_ID_LEN     3
+	#define UQ_AGG_PROFILE_MAP_QID_2_AGG_ID_DEFAULT 0x0
+	/*[field] ENABLE*/
+	#define UQ_AGG_PROFILE_MAP_ENABLE
+	#define UQ_AGG_PROFILE_MAP_ENABLE_OFFSET  3
+	#define UQ_AGG_PROFILE_MAP_ENABLE_LEN     1
+	#define UQ_AGG_PROFILE_MAP_ENABLE_DEFAULT 0x0
+
+struct uq_agg_profile_map {
+	a_uint32_t  qid_2_agg_id:3;
+	a_uint32_t  enable:1;
+	a_uint32_t  _reserved0:28;
+};
+
+union uq_agg_profile_map_u {
+	a_uint32_t val;
+	struct uq_agg_profile_map bf;
+};
+
+/*[table] QUEUE_TX_COUNTER_TBL*/
+#define QUEUE_TX_COUNTER_TBL
+#define QUEUE_TX_COUNTER_TBL_ADDRESS 0x4000
+#define QUEUE_TX_COUNTER_TBL_NUM     300
+#define QUEUE_TX_COUNTER_TBL_INC     0x10
+#define QUEUE_TX_COUNTER_TBL_TYPE    REG_TYPE_RW
+#define QUEUE_TX_COUNTER_TBL_DEFAULT 0x0
+	/*[field] TX_PACKETS*/
+	#define QUEUE_TX_COUNTER_TBL_TX_PACKETS
+	#define QUEUE_TX_COUNTER_TBL_TX_PACKETS_OFFSET  0
+	#define QUEUE_TX_COUNTER_TBL_TX_PACKETS_LEN     32
+	#define QUEUE_TX_COUNTER_TBL_TX_PACKETS_DEFAULT 0x0
+	/*[field] TX_BYTES*/
+	#define QUEUE_TX_COUNTER_TBL_TX_BYTES
+	#define QUEUE_TX_COUNTER_TBL_TX_BYTES_OFFSET  32
+	#define QUEUE_TX_COUNTER_TBL_TX_BYTES_LEN     40
+	#define QUEUE_TX_COUNTER_TBL_TX_BYTES_DEFAULT 0x0
+
+struct queue_tx_counter_tbl {
+	a_uint32_t  tx_packets:32;
+	a_uint32_t  tx_bytes_0:32;
+	a_uint32_t  tx_bytes_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union queue_tx_counter_tbl_u {
+	a_uint32_t val[3];
+	struct queue_tx_counter_tbl bf;
+};
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_qos.h b/qca-ssdk/include/hsl/hppe/hppe_qos.h
new file mode 100755
index 0000000..353290b
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_qos.h
@@ -0,0 +1,2163 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_QOS_H_
+#define _HPPE_QOS_H_
+
+#define L0_FLOW_MAP_TBL_MAX_ENTRY	300
+#define L0_C_SP_CFG_TBL_MAX_ENTRY	512
+#define L0_E_SP_CFG_TBL_MAX_ENTRY	512
+#define L0_FLOW_PORT_MAP_TBL_MAX_ENTRY	300
+#define L0_C_DRR_HEAD_TBL_MAX_ENTRY	160
+#define L0_E_DRR_HEAD_TBL_MAX_ENTRY	160
+#define L0_DRR_CREDIT_TBL_MAX_ENTRY	300
+#define L0_C_DRR_LL_TBL_MAX_ENTRY	300
+#define L0_C_DRR_REVERSE_LL_TBL_MAX_ENTRY	300
+#define L0_E_DRR_LL_TBL_MAX_ENTRY	300
+#define L0_E_DRR_REVERSE_LL_TBL_MAX_ENTRY	300
+#define L0_SP_ENTRY_TBL_MAX_ENTRY	64
+#define L0_ENS_Q_LL_TBL_MAX_ENTRY	300
+#define L0_ENS_Q_HEAD_TBL_MAX_ENTRY	8
+#define L0_ENS_Q_ENTRY_TBL_MAX_ENTRY	300
+#define L0_FLOW_STATUS_TBL_MAX_ENTRY	300
+#define RING_Q_MAP_TBL_MAX_ENTRY	16
+#define RFC_BLOCK_TBL_MAX_ENTRY	300
+#define RFC_STATUS_TBL_MAX_ENTRY	300
+#define DEQ_DIS_TBL_MAX_ENTRY	300
+#define L1_FLOW_MAP_TBL_MAX_ENTRY	64
+#define L1_C_SP_CFG_TBL_MAX_ENTRY	64
+#define L1_E_SP_CFG_TBL_MAX_ENTRY	64
+#define L1_FLOW_PORT_MAP_TBL_MAX_ENTRY	64
+#define L1_C_DRR_HEAD_TBL_MAX_ENTRY	36
+#define L1_E_DRR_HEAD_TBL_MAX_ENTRY	36
+#define L1_DRR_CREDIT_TBL_MAX_ENTRY	64
+#define L1_C_DRR_LL_TBL_MAX_ENTRY	64
+#define L1_C_DRR_REVERSE_LL_TBL_MAX_ENTRY	64
+#define L1_E_DRR_LL_TBL_MAX_ENTRY	64
+#define L1_E_DRR_REVERSE_LL_TBL_MAX_ENTRY	64
+#define L1_A_FLOW_ENTRY_TBL_MAX_ENTRY	64
+#define L1_B_FLOW_ENTRY_TBL_MAX_ENTRY	64
+#define L1_SP_ENTRY_TBL_MAX_ENTRY	8
+
+#define L1_ENS_Q_LL_TBL_MAX_ENTRY	64
+#define L1_ENS_Q_HEAD_TBL_MAX_ENTRY	8
+#define L1_ENS_Q_ENTRY_TBL_MAX_ENTRY	64
+#define L1_FLOW_STATUS_TBL_MAX_ENTRY	64
+#define PSCH_TDM_CFG_TBL_MAX_ENTRY	128
+
+#define PORT_QOS_CTRL_MAX_ENTRY	8
+#define PCP_QOS_GROUP_0_MAX_ENTRY	16
+#define PCP_QOS_GROUP_1_MAX_ENTRY	16
+#define FLOW_QOS_GROUP_0_MAX_ENTRY	32
+#define FLOW_QOS_GROUP_1_MAX_ENTRY	32
+#define DSCP_QOS_GROUP_0_MAX_ENTRY	64
+#define DSCP_QOS_GROUP_1_MAX_ENTRY	64
+
+sw_error_t
+hppe_dscp_qos_group_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union dscp_qos_group_0_u *value);
+
+sw_error_t
+hppe_dscp_qos_group_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union dscp_qos_group_0_u *value);
+
+sw_error_t
+hppe_dscp_qos_group_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union dscp_qos_group_1_u *value);
+
+sw_error_t
+hppe_dscp_qos_group_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union dscp_qos_group_1_u *value);
+
+
+sw_error_t
+hppe_pcp_qos_group_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pcp_qos_group_0_u *value);
+
+sw_error_t
+hppe_pcp_qos_group_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pcp_qos_group_0_u *value);
+
+sw_error_t
+hppe_pcp_qos_group_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pcp_qos_group_1_u *value);
+
+sw_error_t
+hppe_pcp_qos_group_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pcp_qos_group_1_u *value);
+
+sw_error_t
+hppe_flow_qos_group_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union flow_qos_group_0_u *value);
+
+sw_error_t
+hppe_flow_qos_group_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union flow_qos_group_0_u *value);
+
+sw_error_t
+hppe_flow_qos_group_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union flow_qos_group_1_u *value);
+
+sw_error_t
+hppe_flow_qos_group_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union flow_qos_group_1_u *value);
+
+sw_error_t
+hppe_port_qos_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_qos_ctrl_u *value);
+
+sw_error_t
+hppe_port_qos_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_qos_ctrl_u *value);
+
+sw_error_t
+hppe_tdm_depth_cfg_get(
+		a_uint32_t dev_id,
+		union tdm_depth_cfg_u *value);
+
+sw_error_t
+hppe_tdm_depth_cfg_set(
+		a_uint32_t dev_id,
+		union tdm_depth_cfg_u *value);
+
+sw_error_t
+hppe_min_max_mode_cfg_get(
+		a_uint32_t dev_id,
+		union min_max_mode_cfg_u *value);
+
+sw_error_t
+hppe_min_max_mode_cfg_set(
+		a_uint32_t dev_id,
+		union min_max_mode_cfg_u *value);
+
+sw_error_t
+hppe_tm_dbg_addr_get(
+		a_uint32_t dev_id,
+		union tm_dbg_addr_u *value);
+
+sw_error_t
+hppe_tm_dbg_addr_set(
+		a_uint32_t dev_id,
+		union tm_dbg_addr_u *value);
+
+sw_error_t
+hppe_tm_dbg_data_get(
+		a_uint32_t dev_id,
+		union tm_dbg_data_u *value);
+
+sw_error_t
+hppe_tm_dbg_data_set(
+		a_uint32_t dev_id,
+		union tm_dbg_data_u *value);
+
+sw_error_t
+hppe_eco_reserve_0_get(
+		a_uint32_t dev_id,
+		union eco_reserve_0_u *value);
+
+sw_error_t
+hppe_eco_reserve_0_set(
+		a_uint32_t dev_id,
+		union eco_reserve_0_u *value);
+
+sw_error_t
+hppe_eco_reserve_1_get(
+		a_uint32_t dev_id,
+		union eco_reserve_1_u *value);
+
+sw_error_t
+hppe_eco_reserve_1_set(
+		a_uint32_t dev_id,
+		union eco_reserve_1_u *value);
+
+sw_error_t
+hppe_l0_flow_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_flow_map_tbl_u *value);
+
+sw_error_t
+hppe_l0_flow_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_flow_map_tbl_u *value);
+
+sw_error_t
+hppe_l0_c_sp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_sp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_l0_c_sp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_sp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_l0_e_sp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_sp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_l0_e_sp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_sp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_l0_flow_port_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_flow_port_map_tbl_u *value);
+
+sw_error_t
+hppe_l0_flow_port_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_flow_port_map_tbl_u *value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_drr_head_tbl_u *value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_drr_head_tbl_u *value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_drr_head_tbl_u *value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_drr_head_tbl_u *value);
+
+sw_error_t
+hppe_l0_drr_credit_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_drr_credit_tbl_u *value);
+
+sw_error_t
+hppe_l0_drr_credit_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_drr_credit_tbl_u *value);
+
+sw_error_t
+hppe_l0_c_drr_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_drr_ll_tbl_u *value);
+
+sw_error_t
+hppe_l0_c_drr_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_drr_ll_tbl_u *value);
+
+sw_error_t
+hppe_l0_c_drr_reverse_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_drr_reverse_ll_tbl_u *value);
+
+sw_error_t
+hppe_l0_c_drr_reverse_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_drr_reverse_ll_tbl_u *value);
+
+sw_error_t
+hppe_l0_e_drr_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_drr_ll_tbl_u *value);
+
+sw_error_t
+hppe_l0_e_drr_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_drr_ll_tbl_u *value);
+
+sw_error_t
+hppe_l0_e_drr_reverse_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_drr_reverse_ll_tbl_u *value);
+
+sw_error_t
+hppe_l0_e_drr_reverse_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_drr_reverse_ll_tbl_u *value);
+
+sw_error_t
+hppe_l0_sp_entry_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_sp_entry_tbl_u *value);
+
+sw_error_t
+hppe_l0_sp_entry_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_sp_entry_tbl_u *value);
+
+sw_error_t
+hppe_l0_ens_q_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_ens_q_ll_tbl_u *value);
+
+sw_error_t
+hppe_l0_ens_q_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_ens_q_ll_tbl_u *value);
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_ens_q_head_tbl_u *value);
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_ens_q_head_tbl_u *value);
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_ens_q_entry_tbl_u *value);
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_ens_q_entry_tbl_u *value);
+
+sw_error_t
+hppe_l0_flow_status_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_flow_status_tbl_u *value);
+
+sw_error_t
+hppe_l0_flow_status_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_flow_status_tbl_u *value);
+
+sw_error_t
+hppe_ring_q_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ring_q_map_tbl_u *value);
+
+sw_error_t
+hppe_ring_q_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ring_q_map_tbl_u *value);
+
+sw_error_t
+hppe_rfc_block_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rfc_block_tbl_u *value);
+
+sw_error_t
+hppe_rfc_block_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rfc_block_tbl_u *value);
+
+sw_error_t
+hppe_rfc_status_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rfc_status_tbl_u *value);
+
+sw_error_t
+hppe_rfc_status_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rfc_status_tbl_u *value);
+
+sw_error_t
+hppe_deq_dis_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union deq_dis_tbl_u *value);
+
+sw_error_t
+hppe_deq_dis_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union deq_dis_tbl_u *value);
+
+sw_error_t
+hppe_l1_flow_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_flow_map_tbl_u *value);
+
+sw_error_t
+hppe_l1_flow_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_flow_map_tbl_u *value);
+
+sw_error_t
+hppe_l1_c_sp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_sp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_l1_c_sp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_sp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_l1_e_sp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_sp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_l1_e_sp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_sp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_l1_flow_port_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_flow_port_map_tbl_u *value);
+
+sw_error_t
+hppe_l1_flow_port_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_flow_port_map_tbl_u *value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_drr_head_tbl_u *value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_drr_head_tbl_u *value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_drr_head_tbl_u *value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_drr_head_tbl_u *value);
+
+sw_error_t
+hppe_l1_drr_credit_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_drr_credit_tbl_u *value);
+
+sw_error_t
+hppe_l1_drr_credit_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_drr_credit_tbl_u *value);
+
+sw_error_t
+hppe_l1_c_drr_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_drr_ll_tbl_u *value);
+
+sw_error_t
+hppe_l1_c_drr_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_drr_ll_tbl_u *value);
+
+sw_error_t
+hppe_l1_c_drr_reverse_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_drr_reverse_ll_tbl_u *value);
+
+sw_error_t
+hppe_l1_c_drr_reverse_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_drr_reverse_ll_tbl_u *value);
+
+sw_error_t
+hppe_l1_e_drr_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_drr_ll_tbl_u *value);
+
+sw_error_t
+hppe_l1_e_drr_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_drr_ll_tbl_u *value);
+
+sw_error_t
+hppe_l1_e_drr_reverse_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_drr_reverse_ll_tbl_u *value);
+
+sw_error_t
+hppe_l1_e_drr_reverse_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_drr_reverse_ll_tbl_u *value);
+
+sw_error_t
+hppe_l1_a_flow_entry_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_a_flow_entry_tbl_u *value);
+
+sw_error_t
+hppe_l1_a_flow_entry_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_a_flow_entry_tbl_u *value);
+
+sw_error_t
+hppe_l1_b_flow_entry_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_b_flow_entry_tbl_u *value);
+
+sw_error_t
+hppe_l1_b_flow_entry_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_b_flow_entry_tbl_u *value);
+
+sw_error_t
+hppe_l1_sp_entry_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_sp_entry_tbl_u *value);
+
+sw_error_t
+hppe_l1_sp_entry_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_sp_entry_tbl_u *value);
+
+sw_error_t
+hppe_l1_ens_q_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_ens_q_ll_tbl_u *value);
+
+sw_error_t
+hppe_l1_ens_q_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_ens_q_ll_tbl_u *value);
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_ens_q_head_tbl_u *value);
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_ens_q_head_tbl_u *value);
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_ens_q_entry_tbl_u *value);
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_ens_q_entry_tbl_u *value);
+
+sw_error_t
+hppe_l1_flow_status_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_flow_status_tbl_u *value);
+
+sw_error_t
+hppe_l1_flow_status_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_flow_status_tbl_u *value);
+
+sw_error_t
+hppe_psch_tdm_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_tdm_cfg_tbl_u *value);
+
+sw_error_t
+hppe_psch_tdm_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_tdm_cfg_tbl_u *value);
+
+sw_error_t
+hppe_tdm_depth_cfg_tdm_depth_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_tdm_depth_cfg_tdm_depth_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_min_max_mode_cfg_min_max_mode_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_min_max_mode_cfg_min_max_mode_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_tm_dbg_addr_dbg_addr_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_tm_dbg_addr_dbg_addr_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_tm_dbg_data_dbg_data_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_tm_dbg_data_dbg_data_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_eco_reserve_0_eco_res_0_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_eco_reserve_0_eco_res_0_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_eco_reserve_1_eco_res_1_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_eco_reserve_1_eco_res_1_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l0_flow_map_tbl_e_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_flow_map_tbl_e_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_flow_map_tbl_c_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_flow_map_tbl_c_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_flow_map_tbl_e_drr_wt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_flow_map_tbl_e_drr_wt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_flow_map_tbl_c_drr_wt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_flow_map_tbl_c_drr_wt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_flow_map_tbl_sp_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_flow_map_tbl_sp_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_c_sp_cfg_tbl_drr_credit_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_c_sp_cfg_tbl_drr_credit_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_c_sp_cfg_tbl_drr_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_c_sp_cfg_tbl_drr_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_e_sp_cfg_tbl_drr_credit_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_e_sp_cfg_tbl_drr_credit_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_e_sp_cfg_tbl_drr_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_e_sp_cfg_tbl_drr_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_flow_port_map_tbl_port_num_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_flow_port_map_tbl_port_num_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_drr_credit_tbl_e_drr_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_drr_credit_tbl_e_drr_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_drr_credit_tbl_c_drr_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_drr_credit_tbl_c_drr_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_drr_credit_tbl_c_drr_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_drr_credit_tbl_c_drr_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_drr_credit_tbl_e_drr_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_drr_credit_tbl_e_drr_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_c_drr_ll_tbl_next_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_c_drr_ll_tbl_next_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_c_drr_reverse_ll_tbl_pre_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_c_drr_reverse_ll_tbl_pre_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_e_drr_ll_tbl_next_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_e_drr_ll_tbl_next_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_e_drr_reverse_ll_tbl_pre_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_e_drr_reverse_ll_tbl_pre_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_sp_entry_tbl_entry_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_sp_entry_tbl_entry_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_sp_entry_tbl_entry_path_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_l0_sp_entry_tbl_entry_path_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_l0_ens_q_ll_tbl_next_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_ens_q_ll_tbl_next_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_entry_ens_in_q_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_entry_ens_in_q_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_entry_ens_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_entry_ens_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_entry_ens_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_entry_ens_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_flow_status_tbl_en_cdrr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_flow_status_tbl_en_cdrr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_flow_status_tbl_en_edrr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_flow_status_tbl_en_edrr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_flow_status_tbl_en_level_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_flow_status_tbl_en_level_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ring_q_map_tbl_queue_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_ring_q_map_tbl_queue_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_rfc_block_tbl_rfc_block_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rfc_block_tbl_rfc_block_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rfc_status_tbl_rfc_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rfc_status_tbl_rfc_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_deq_dis_tbl_deq_dis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_deq_dis_tbl_deq_dis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_flow_map_tbl_e_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_flow_map_tbl_e_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_flow_map_tbl_c_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_flow_map_tbl_c_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_flow_map_tbl_e_drr_wt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_flow_map_tbl_e_drr_wt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_flow_map_tbl_c_drr_wt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_flow_map_tbl_c_drr_wt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_flow_map_tbl_sp_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_flow_map_tbl_sp_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_c_sp_cfg_tbl_drr_credit_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_c_sp_cfg_tbl_drr_credit_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_c_sp_cfg_tbl_drr_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_c_sp_cfg_tbl_drr_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_e_sp_cfg_tbl_drr_credit_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_e_sp_cfg_tbl_drr_credit_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_e_sp_cfg_tbl_drr_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_e_sp_cfg_tbl_drr_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_flow_port_map_tbl_port_num_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_flow_port_map_tbl_port_num_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_drr_credit_tbl_e_drr_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_drr_credit_tbl_e_drr_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_drr_credit_tbl_c_drr_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_drr_credit_tbl_c_drr_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_drr_credit_tbl_c_drr_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_drr_credit_tbl_c_drr_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_drr_credit_tbl_e_drr_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_drr_credit_tbl_e_drr_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_c_drr_ll_tbl_next_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_c_drr_ll_tbl_next_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_c_drr_reverse_ll_tbl_pre_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_c_drr_reverse_ll_tbl_pre_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_e_drr_ll_tbl_next_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_e_drr_ll_tbl_next_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_e_drr_reverse_ll_tbl_pre_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_e_drr_reverse_ll_tbl_pre_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_a_flow_entry_tbl_entry_path_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_a_flow_entry_tbl_entry_path_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_b_flow_entry_tbl_entry_path_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_b_flow_entry_tbl_entry_path_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_sp_entry_tbl_entry_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_sp_entry_tbl_entry_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_sp_entry_tbl_entry_path_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_l1_sp_entry_tbl_entry_path_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_l1_ens_q_ll_tbl_next_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_ens_q_ll_tbl_next_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_entry_ens_in_q_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_entry_ens_in_q_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_entry_ens_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_entry_ens_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_entry_ens_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_entry_ens_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_flow_status_tbl_en_cdrr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_flow_status_tbl_en_cdrr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_flow_status_tbl_en_edrr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_flow_status_tbl_en_edrr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_flow_status_tbl_en_level_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_flow_status_tbl_en_level_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_psch_tdm_cfg_tbl_ens_port_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_psch_tdm_cfg_tbl_ens_port_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_psch_tdm_cfg_tbl_des_port_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_psch_tdm_cfg_tbl_des_port_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_psch_tdm_cfg_tbl_ens_port_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_psch_tdm_cfg_tbl_ens_port_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_flow_qos_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_flow_qos_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_dscp_qos_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_dscp_qos_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_dscp_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_dscp_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_pcp_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_pcp_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_acl_qos_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_acl_qos_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_qos_ctrl_flow_qos_group_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_qos_ctrl_flow_qos_group_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_preheader_qos_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_preheader_qos_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_qos_ctrl_pcp_qos_group_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_qos_ctrl_pcp_qos_group_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_qos_ctrl_dscp_qos_group_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_qos_ctrl_dscp_qos_group_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_pcp_qos_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_pcp_qos_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_dei_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_qos_ctrl_port_dei_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pcp_qos_group_0_qos_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pcp_qos_group_0_qos_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pcp_qos_group_1_qos_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pcp_qos_group_1_qos_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_qos_group_0_qos_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_qos_group_0_qos_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_flow_qos_group_1_qos_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_flow_qos_group_1_qos_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_dscp_qos_group_0_qos_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_dscp_qos_group_0_qos_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_dscp_qos_group_1_qos_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_dscp_qos_group_1_qos_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_qos_reg.h b/qca-ssdk/include/hsl/hppe/hppe_qos_reg.h
new file mode 100755
index 0000000..59decb6
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_qos_reg.h
@@ -0,0 +1,1676 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_QOS_REG_H
+#define HPPE_QOS_REG_H
+
+/*[register] TDM_DEPTH_CFG*/
+#define TDM_DEPTH_CFG
+#define TDM_DEPTH_CFG_ADDRESS 0x0
+#define TDM_DEPTH_CFG_NUM     1
+#define TDM_DEPTH_CFG_INC     0x4
+#define TDM_DEPTH_CFG_TYPE    REG_TYPE_RW
+#define TDM_DEPTH_CFG_DEFAULT 0x28
+	/*[field] TDM_DEPTH*/
+	#define TDM_DEPTH_CFG_TDM_DEPTH
+	#define TDM_DEPTH_CFG_TDM_DEPTH_OFFSET  0
+	#define TDM_DEPTH_CFG_TDM_DEPTH_LEN     8
+	#define TDM_DEPTH_CFG_TDM_DEPTH_DEFAULT 0x28
+
+struct tdm_depth_cfg {
+	a_uint32_t  tdm_depth:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union tdm_depth_cfg_u {
+	a_uint32_t val;
+	struct tdm_depth_cfg bf;
+};
+
+/*[register] MIN_MAX_MODE_CFG*/
+#define MIN_MAX_MODE_CFG
+#define MIN_MAX_MODE_CFG_ADDRESS 0x4
+#define MIN_MAX_MODE_CFG_NUM     1
+#define MIN_MAX_MODE_CFG_INC     0x4
+#define MIN_MAX_MODE_CFG_TYPE    REG_TYPE_RW
+#define MIN_MAX_MODE_CFG_DEFAULT 0x0
+	/*[field] MIN_MAX_MODE*/
+	#define MIN_MAX_MODE_CFG_MIN_MAX_MODE
+	#define MIN_MAX_MODE_CFG_MIN_MAX_MODE_OFFSET  0
+	#define MIN_MAX_MODE_CFG_MIN_MAX_MODE_LEN     1
+	#define MIN_MAX_MODE_CFG_MIN_MAX_MODE_DEFAULT 0x0
+
+struct min_max_mode_cfg {
+	a_uint32_t  min_max_mode:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union min_max_mode_cfg_u {
+	a_uint32_t val;
+	struct min_max_mode_cfg bf;
+};
+
+
+/*[register] TM_DBG_ADDR*/
+#define TM_DBG_ADDR
+#define TM_DBG_ADDR_ADDRESS 0x20
+#define TM_DBG_ADDR_NUM     1
+#define TM_DBG_ADDR_INC     0x4
+#define TM_DBG_ADDR_TYPE    REG_TYPE_RW
+#define TM_DBG_ADDR_DEFAULT 0x0
+	/*[field] DBG_ADDR*/
+	#define TM_DBG_ADDR_DBG_ADDR
+	#define TM_DBG_ADDR_DBG_ADDR_OFFSET  0
+	#define TM_DBG_ADDR_DBG_ADDR_LEN     8
+	#define TM_DBG_ADDR_DBG_ADDR_DEFAULT 0x0
+
+struct tm_dbg_addr {
+	a_uint32_t  dbg_addr:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union tm_dbg_addr_u {
+	a_uint32_t val;
+	struct tm_dbg_addr bf;
+};
+
+/*[register] TM_DBG_DATA*/
+#define TM_DBG_DATA
+#define TM_DBG_DATA_ADDRESS 0x24
+#define TM_DBG_DATA_NUM     1
+#define TM_DBG_DATA_INC     0x4
+#define TM_DBG_DATA_TYPE    REG_TYPE_RO
+#define TM_DBG_DATA_DEFAULT 0x0
+	/*[field] DBG_DATA*/
+	#define TM_DBG_DATA_DBG_DATA
+	#define TM_DBG_DATA_DBG_DATA_OFFSET  0
+	#define TM_DBG_DATA_DBG_DATA_LEN     32
+	#define TM_DBG_DATA_DBG_DATA_DEFAULT 0x0
+
+struct tm_dbg_data {
+	a_uint32_t  dbg_data:32;
+};
+
+union tm_dbg_data_u {
+	a_uint32_t val;
+	struct tm_dbg_data bf;
+};
+
+/*[register] ECO_RESERVE_0*/
+#define ECO_RESERVE_0
+#define ECO_RESERVE_0_ADDRESS 0x28
+#define ECO_RESERVE_0_NUM     1
+#define ECO_RESERVE_0_INC     0x4
+#define ECO_RESERVE_0_TYPE    REG_TYPE_RW
+#define ECO_RESERVE_0_DEFAULT 0x0
+	/*[field] ECO_RES_0*/
+	#define ECO_RESERVE_0_ECO_RES_0
+	#define ECO_RESERVE_0_ECO_RES_0_OFFSET  0
+	#define ECO_RESERVE_0_ECO_RES_0_LEN     32
+	#define ECO_RESERVE_0_ECO_RES_0_DEFAULT 0x0
+
+struct eco_reserve_0 {
+	a_uint32_t  eco_res_0:32;
+};
+
+union eco_reserve_0_u {
+	a_uint32_t val;
+	struct eco_reserve_0 bf;
+};
+
+/*[register] ECO_RESERVE_1*/
+#define ECO_RESERVE_1
+#define ECO_RESERVE_1_ADDRESS 0x2c
+#define ECO_RESERVE_1_NUM     1
+#define ECO_RESERVE_1_INC     0x4
+#define ECO_RESERVE_1_TYPE    REG_TYPE_RW
+#define ECO_RESERVE_1_DEFAULT 0x0
+	/*[field] ECO_RES_1*/
+	#define ECO_RESERVE_1_ECO_RES_1
+	#define ECO_RESERVE_1_ECO_RES_1_OFFSET  0
+	#define ECO_RESERVE_1_ECO_RES_1_LEN     32
+	#define ECO_RESERVE_1_ECO_RES_1_DEFAULT 0x0
+
+struct eco_reserve_1 {
+	a_uint32_t  eco_res_1:32;
+};
+
+union eco_reserve_1_u {
+	a_uint32_t val;
+	struct eco_reserve_1 bf;
+};
+
+/*[table] L0_FLOW_MAP_TBL*/
+#define L0_FLOW_MAP_TBL
+#define L0_FLOW_MAP_TBL_ADDRESS 0x2000
+#define L0_FLOW_MAP_TBL_NUM     300
+#define L0_FLOW_MAP_TBL_INC     0x10
+#define L0_FLOW_MAP_TBL_TYPE    REG_TYPE_RW
+#define L0_FLOW_MAP_TBL_DEFAULT 0x0
+	/*[field] SP_ID*/
+	#define L0_FLOW_MAP_TBL_SP_ID
+	#define L0_FLOW_MAP_TBL_SP_ID_OFFSET  0
+	#define L0_FLOW_MAP_TBL_SP_ID_LEN     6
+	#define L0_FLOW_MAP_TBL_SP_ID_DEFAULT 0x0
+	/*[field] C_PRI*/
+	#define L0_FLOW_MAP_TBL_C_PRI
+	#define L0_FLOW_MAP_TBL_C_PRI_OFFSET  6
+	#define L0_FLOW_MAP_TBL_C_PRI_LEN     3
+	#define L0_FLOW_MAP_TBL_C_PRI_DEFAULT 0x0
+	/*[field] E_PRI*/
+	#define L0_FLOW_MAP_TBL_E_PRI
+	#define L0_FLOW_MAP_TBL_E_PRI_OFFSET  9
+	#define L0_FLOW_MAP_TBL_E_PRI_LEN     3
+	#define L0_FLOW_MAP_TBL_E_PRI_DEFAULT 0x0
+	/*[field] C_DRR_WT*/
+	#define L0_FLOW_MAP_TBL_C_DRR_WT
+	#define L0_FLOW_MAP_TBL_C_DRR_WT_OFFSET  12
+	#define L0_FLOW_MAP_TBL_C_DRR_WT_LEN     10
+	#define L0_FLOW_MAP_TBL_C_DRR_WT_DEFAULT 0x0
+	/*[field] E_DRR_WT*/
+	#define L0_FLOW_MAP_TBL_E_DRR_WT
+	#define L0_FLOW_MAP_TBL_E_DRR_WT_OFFSET  22
+	#define L0_FLOW_MAP_TBL_E_DRR_WT_LEN     10
+	#define L0_FLOW_MAP_TBL_E_DRR_WT_DEFAULT 0x0
+
+struct l0_flow_map_tbl {
+	a_uint32_t  sp_id:6;
+	a_uint32_t  c_pri:3;
+	a_uint32_t  e_pri:3;
+	a_uint32_t  c_drr_wt:10;
+	a_uint32_t  e_drr_wt:10;
+};
+
+union l0_flow_map_tbl_u {
+	a_uint32_t val;
+	struct l0_flow_map_tbl bf;
+};
+
+/*[table] L0_C_SP_CFG_TBL*/
+#define L0_C_SP_CFG_TBL
+#define L0_C_SP_CFG_TBL_ADDRESS 0x4000
+#define L0_C_SP_CFG_TBL_NUM     512
+#define L0_C_SP_CFG_TBL_INC     0x10
+#define L0_C_SP_CFG_TBL_TYPE    REG_TYPE_RW
+#define L0_C_SP_CFG_TBL_DEFAULT 0x0
+	/*[field] DRR_ID*/
+	#define L0_C_SP_CFG_TBL_DRR_ID
+	#define L0_C_SP_CFG_TBL_DRR_ID_OFFSET  0
+	#define L0_C_SP_CFG_TBL_DRR_ID_LEN     8
+	#define L0_C_SP_CFG_TBL_DRR_ID_DEFAULT 0x0
+	/*[field] DRR_CREDIT_UNIT*/
+	#define L0_C_SP_CFG_TBL_DRR_CREDIT_UNIT
+	#define L0_C_SP_CFG_TBL_DRR_CREDIT_UNIT_OFFSET  8
+	#define L0_C_SP_CFG_TBL_DRR_CREDIT_UNIT_LEN     1
+	#define L0_C_SP_CFG_TBL_DRR_CREDIT_UNIT_DEFAULT 0x0
+
+struct l0_c_sp_cfg_tbl {
+	a_uint32_t  drr_id:8;
+	a_uint32_t  drr_credit_unit:1;
+	a_uint32_t  _reserved0:23;
+};
+
+union l0_c_sp_cfg_tbl_u {
+	a_uint32_t val;
+	struct l0_c_sp_cfg_tbl bf;
+};
+
+/*[table] L0_E_SP_CFG_TBL*/
+#define L0_E_SP_CFG_TBL
+#define L0_E_SP_CFG_TBL_ADDRESS 0x6000
+#define L0_E_SP_CFG_TBL_NUM     512
+#define L0_E_SP_CFG_TBL_INC     0x10
+#define L0_E_SP_CFG_TBL_TYPE    REG_TYPE_RW
+#define L0_E_SP_CFG_TBL_DEFAULT 0x0
+	/*[field] DRR_ID*/
+	#define L0_E_SP_CFG_TBL_DRR_ID
+	#define L0_E_SP_CFG_TBL_DRR_ID_OFFSET  0
+	#define L0_E_SP_CFG_TBL_DRR_ID_LEN     8
+	#define L0_E_SP_CFG_TBL_DRR_ID_DEFAULT 0x0
+	/*[field] DRR_CREDIT_UNIT*/
+	#define L0_E_SP_CFG_TBL_DRR_CREDIT_UNIT
+	#define L0_E_SP_CFG_TBL_DRR_CREDIT_UNIT_OFFSET  8
+	#define L0_E_SP_CFG_TBL_DRR_CREDIT_UNIT_LEN     1
+	#define L0_E_SP_CFG_TBL_DRR_CREDIT_UNIT_DEFAULT 0x0
+
+struct l0_e_sp_cfg_tbl {
+	a_uint32_t  drr_id:8;
+	a_uint32_t  drr_credit_unit:1;
+	a_uint32_t  _reserved0:23;
+};
+
+union l0_e_sp_cfg_tbl_u {
+	a_uint32_t val;
+	struct l0_e_sp_cfg_tbl bf;
+};
+
+/*[table] L0_FLOW_PORT_MAP_TBL*/
+#define L0_FLOW_PORT_MAP_TBL
+#define L0_FLOW_PORT_MAP_TBL_ADDRESS 0x8000
+#define L0_FLOW_PORT_MAP_TBL_NUM     300
+#define L0_FLOW_PORT_MAP_TBL_INC     0x10
+#define L0_FLOW_PORT_MAP_TBL_TYPE    REG_TYPE_RW
+#define L0_FLOW_PORT_MAP_TBL_DEFAULT 0x0
+	/*[field] PORT_NUM*/
+	#define L0_FLOW_PORT_MAP_TBL_PORT_NUM
+	#define L0_FLOW_PORT_MAP_TBL_PORT_NUM_OFFSET  0
+	#define L0_FLOW_PORT_MAP_TBL_PORT_NUM_LEN     4
+	#define L0_FLOW_PORT_MAP_TBL_PORT_NUM_DEFAULT 0x0
+
+struct l0_flow_port_map_tbl {
+	a_uint32_t  port_num:4;
+	a_uint32_t  _reserved0:28;
+};
+
+union l0_flow_port_map_tbl_u {
+	a_uint32_t val;
+	struct l0_flow_port_map_tbl bf;
+};
+
+/*[table] L0_C_DRR_HEAD_TBL*/
+#define L0_C_DRR_HEAD_TBL
+#define L0_C_DRR_HEAD_TBL_ADDRESS 0xa000
+#define L0_C_DRR_HEAD_TBL_NUM     160
+#define L0_C_DRR_HEAD_TBL_INC     0x10
+#define L0_C_DRR_HEAD_TBL_TYPE    REG_TYPE_RO
+#define L0_C_DRR_HEAD_TBL_DEFAULT 0x0
+	/*[field] BACKUP_TAIL*/
+	#define L0_C_DRR_HEAD_TBL_BACKUP_TAIL
+	#define L0_C_DRR_HEAD_TBL_BACKUP_TAIL_OFFSET  0
+	#define L0_C_DRR_HEAD_TBL_BACKUP_TAIL_LEN     9
+	#define L0_C_DRR_HEAD_TBL_BACKUP_TAIL_DEFAULT 0x0
+	/*[field] BACKUP_HEAD*/
+	#define L0_C_DRR_HEAD_TBL_BACKUP_HEAD
+	#define L0_C_DRR_HEAD_TBL_BACKUP_HEAD_OFFSET  9
+	#define L0_C_DRR_HEAD_TBL_BACKUP_HEAD_LEN     9
+	#define L0_C_DRR_HEAD_TBL_BACKUP_HEAD_DEFAULT 0x0
+	/*[field] BACKUP_VLD*/
+	#define L0_C_DRR_HEAD_TBL_BACKUP_VLD
+	#define L0_C_DRR_HEAD_TBL_BACKUP_VLD_OFFSET  18
+	#define L0_C_DRR_HEAD_TBL_BACKUP_VLD_LEN     1
+	#define L0_C_DRR_HEAD_TBL_BACKUP_VLD_DEFAULT 0x0
+	/*[field] BACKUP_MAX_N*/
+	#define L0_C_DRR_HEAD_TBL_BACKUP_MAX_N
+	#define L0_C_DRR_HEAD_TBL_BACKUP_MAX_N_OFFSET  19
+	#define L0_C_DRR_HEAD_TBL_BACKUP_MAX_N_LEN     5
+	#define L0_C_DRR_HEAD_TBL_BACKUP_MAX_N_DEFAULT 0x0
+	/*[field] ACTIVE_TAIL*/
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_TAIL
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_TAIL_OFFSET  24
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_TAIL_LEN     9
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_TAIL_DEFAULT 0x0
+	/*[field] ACTIVE_HEAD*/
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_HEAD
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_HEAD_OFFSET  33
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_HEAD_LEN     9
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_HEAD_DEFAULT 0x0
+	/*[field] ACTIVE_VLD*/
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_VLD
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_VLD_OFFSET  42
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_VLD_LEN     1
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_VLD_DEFAULT 0x0
+	/*[field] ACTIVE_MAX_N*/
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_MAX_N
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_MAX_N_OFFSET  43
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_MAX_N_LEN     5
+	#define L0_C_DRR_HEAD_TBL_ACTIVE_MAX_N_DEFAULT 0x0
+
+struct l0_c_drr_head_tbl {
+	a_uint32_t  backup_tail:9;
+	a_uint32_t  backup_head:9;
+	a_uint32_t  backup_vld:1;
+	a_uint32_t  backup_max_n:5;
+	a_uint32_t  active_tail_0:8;
+	a_uint32_t  active_tail_1:1;
+	a_uint32_t  active_head:9;
+	a_uint32_t  active_vld:1;
+	a_uint32_t  active_max_n:5;
+	a_uint32_t  _reserved0:16;
+};
+
+union l0_c_drr_head_tbl_u {
+	a_uint32_t val[2];
+	struct l0_c_drr_head_tbl bf;
+};
+
+/*[table] L0_E_DRR_HEAD_TBL*/
+#define L0_E_DRR_HEAD_TBL
+#define L0_E_DRR_HEAD_TBL_ADDRESS 0xc000
+#define L0_E_DRR_HEAD_TBL_NUM     160
+#define L0_E_DRR_HEAD_TBL_INC     0x10
+#define L0_E_DRR_HEAD_TBL_TYPE    REG_TYPE_RO
+#define L0_E_DRR_HEAD_TBL_DEFAULT 0x0
+	/*[field] BACKUP_TAIL*/
+	#define L0_E_DRR_HEAD_TBL_BACKUP_TAIL
+	#define L0_E_DRR_HEAD_TBL_BACKUP_TAIL_OFFSET  0
+	#define L0_E_DRR_HEAD_TBL_BACKUP_TAIL_LEN     9
+	#define L0_E_DRR_HEAD_TBL_BACKUP_TAIL_DEFAULT 0x0
+	/*[field] BACKUP_HEAD*/
+	#define L0_E_DRR_HEAD_TBL_BACKUP_HEAD
+	#define L0_E_DRR_HEAD_TBL_BACKUP_HEAD_OFFSET  9
+	#define L0_E_DRR_HEAD_TBL_BACKUP_HEAD_LEN     9
+	#define L0_E_DRR_HEAD_TBL_BACKUP_HEAD_DEFAULT 0x0
+	/*[field] BACKUP_VLD*/
+	#define L0_E_DRR_HEAD_TBL_BACKUP_VLD
+	#define L0_E_DRR_HEAD_TBL_BACKUP_VLD_OFFSET  18
+	#define L0_E_DRR_HEAD_TBL_BACKUP_VLD_LEN     1
+	#define L0_E_DRR_HEAD_TBL_BACKUP_VLD_DEFAULT 0x0
+	/*[field] BACKUP_MAX_N*/
+	#define L0_E_DRR_HEAD_TBL_BACKUP_MAX_N
+	#define L0_E_DRR_HEAD_TBL_BACKUP_MAX_N_OFFSET  19
+	#define L0_E_DRR_HEAD_TBL_BACKUP_MAX_N_LEN     5
+	#define L0_E_DRR_HEAD_TBL_BACKUP_MAX_N_DEFAULT 0x0
+	/*[field] ACTIVE_TAIL*/
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_TAIL
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_TAIL_OFFSET  24
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_TAIL_LEN     9
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_TAIL_DEFAULT 0x0
+	/*[field] ACTIVE_HEAD*/
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_HEAD
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_HEAD_OFFSET  33
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_HEAD_LEN     9
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_HEAD_DEFAULT 0x0
+	/*[field] ACTIVE_VLD*/
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_VLD
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_VLD_OFFSET  42
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_VLD_LEN     1
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_VLD_DEFAULT 0x0
+	/*[field] ACTIVE_MAX_N*/
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_MAX_N
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_MAX_N_OFFSET  43
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_MAX_N_LEN     5
+	#define L0_E_DRR_HEAD_TBL_ACTIVE_MAX_N_DEFAULT 0x0
+
+struct l0_e_drr_head_tbl {
+	a_uint32_t  backup_tail:9;
+	a_uint32_t  backup_head:9;
+	a_uint32_t  backup_vld:1;
+	a_uint32_t  backup_max_n:5;
+	a_uint32_t  active_tail_0:8;
+	a_uint32_t  active_tail_1:1;
+	a_uint32_t  active_head:9;
+	a_uint32_t  active_vld:1;
+	a_uint32_t  active_max_n:5;
+	a_uint32_t  _reserved0:16;
+};
+
+union l0_e_drr_head_tbl_u {
+	a_uint32_t val[2];
+	struct l0_e_drr_head_tbl bf;
+};
+
+/*[table] L0_DRR_CREDIT_TBL*/
+#define L0_DRR_CREDIT_TBL
+#define L0_DRR_CREDIT_TBL_ADDRESS 0xe000
+#define L0_DRR_CREDIT_TBL_NUM     300
+#define L0_DRR_CREDIT_TBL_INC     0x10
+#define L0_DRR_CREDIT_TBL_TYPE    REG_TYPE_RO
+#define L0_DRR_CREDIT_TBL_DEFAULT 0x0
+	/*[field] C_DRR_CREDIT*/
+	#define L0_DRR_CREDIT_TBL_C_DRR_CREDIT
+	#define L0_DRR_CREDIT_TBL_C_DRR_CREDIT_OFFSET  0
+	#define L0_DRR_CREDIT_TBL_C_DRR_CREDIT_LEN     24
+	#define L0_DRR_CREDIT_TBL_C_DRR_CREDIT_DEFAULT 0x0
+	/*[field] C_DRR_CREDIT_NEG*/
+	#define L0_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG
+	#define L0_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG_OFFSET  24
+	#define L0_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG_LEN     1
+	#define L0_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG_DEFAULT 0x0
+	/*[field] E_DRR_CREDIT*/
+	#define L0_DRR_CREDIT_TBL_E_DRR_CREDIT
+	#define L0_DRR_CREDIT_TBL_E_DRR_CREDIT_OFFSET  25
+	#define L0_DRR_CREDIT_TBL_E_DRR_CREDIT_LEN     24
+	#define L0_DRR_CREDIT_TBL_E_DRR_CREDIT_DEFAULT 0x0
+	/*[field] E_DRR_CREDIT_NEG*/
+	#define L0_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG
+	#define L0_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG_OFFSET  49
+	#define L0_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG_LEN     1
+	#define L0_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG_DEFAULT 0x0
+
+struct l0_drr_credit_tbl {
+	a_uint32_t  c_drr_credit:24;
+	a_uint32_t  c_drr_credit_neg:1;
+	a_uint32_t  e_drr_credit_0:7;
+	a_uint32_t  e_drr_credit_1:17;
+	a_uint32_t  e_drr_credit_neg:1;
+	a_uint32_t  _reserved0:14;
+};
+
+union l0_drr_credit_tbl_u {
+	a_uint32_t val[2];
+	struct l0_drr_credit_tbl bf;
+};
+
+/*[table] L0_C_DRR_LL_TBL*/
+#define L0_C_DRR_LL_TBL
+#define L0_C_DRR_LL_TBL_ADDRESS 0x10000
+#define L0_C_DRR_LL_TBL_NUM     300
+#define L0_C_DRR_LL_TBL_INC     0x10
+#define L0_C_DRR_LL_TBL_TYPE    REG_TYPE_RO
+#define L0_C_DRR_LL_TBL_DEFAULT 0x0
+	/*[field] NEXT_PTR*/
+	#define L0_C_DRR_LL_TBL_NEXT_PTR
+	#define L0_C_DRR_LL_TBL_NEXT_PTR_OFFSET  0
+	#define L0_C_DRR_LL_TBL_NEXT_PTR_LEN     9
+	#define L0_C_DRR_LL_TBL_NEXT_PTR_DEFAULT 0x0
+
+struct l0_c_drr_ll_tbl {
+	a_uint32_t  next_ptr:9;
+	a_uint32_t  _reserved0:23;
+};
+
+union l0_c_drr_ll_tbl_u {
+	a_uint32_t val;
+	struct l0_c_drr_ll_tbl bf;
+};
+
+/*[table] L0_C_DRR_REVERSE_LL_TBL*/
+#define L0_C_DRR_REVERSE_LL_TBL
+#define L0_C_DRR_REVERSE_LL_TBL_ADDRESS 0x12000
+#define L0_C_DRR_REVERSE_LL_TBL_NUM     300
+#define L0_C_DRR_REVERSE_LL_TBL_INC     0x10
+#define L0_C_DRR_REVERSE_LL_TBL_TYPE    REG_TYPE_RO
+#define L0_C_DRR_REVERSE_LL_TBL_DEFAULT 0x0
+	/*[field] PRE_PTR*/
+	#define L0_C_DRR_REVERSE_LL_TBL_PRE_PTR
+	#define L0_C_DRR_REVERSE_LL_TBL_PRE_PTR_OFFSET  0
+	#define L0_C_DRR_REVERSE_LL_TBL_PRE_PTR_LEN     9
+	#define L0_C_DRR_REVERSE_LL_TBL_PRE_PTR_DEFAULT 0x0
+
+struct l0_c_drr_reverse_ll_tbl {
+	a_uint32_t  pre_ptr:9;
+	a_uint32_t  _reserved0:23;
+};
+
+union l0_c_drr_reverse_ll_tbl_u {
+	a_uint32_t val;
+	struct l0_c_drr_reverse_ll_tbl bf;
+};
+
+/*[table] L0_E_DRR_LL_TBL*/
+#define L0_E_DRR_LL_TBL
+#define L0_E_DRR_LL_TBL_ADDRESS 0x14000
+#define L0_E_DRR_LL_TBL_NUM     300
+#define L0_E_DRR_LL_TBL_INC     0x10
+#define L0_E_DRR_LL_TBL_TYPE    REG_TYPE_RO
+#define L0_E_DRR_LL_TBL_DEFAULT 0x0
+	/*[field] NEXT_PTR*/
+	#define L0_E_DRR_LL_TBL_NEXT_PTR
+	#define L0_E_DRR_LL_TBL_NEXT_PTR_OFFSET  0
+	#define L0_E_DRR_LL_TBL_NEXT_PTR_LEN     9
+	#define L0_E_DRR_LL_TBL_NEXT_PTR_DEFAULT 0x0
+
+struct l0_e_drr_ll_tbl {
+	a_uint32_t  next_ptr:9;
+	a_uint32_t  _reserved0:23;
+};
+
+union l0_e_drr_ll_tbl_u {
+	a_uint32_t val;
+	struct l0_e_drr_ll_tbl bf;
+};
+
+/*[table] L0_E_DRR_REVERSE_LL_TBL*/
+#define L0_E_DRR_REVERSE_LL_TBL
+#define L0_E_DRR_REVERSE_LL_TBL_ADDRESS 0x16000
+#define L0_E_DRR_REVERSE_LL_TBL_NUM     300
+#define L0_E_DRR_REVERSE_LL_TBL_INC     0x10
+#define L0_E_DRR_REVERSE_LL_TBL_TYPE    REG_TYPE_RO
+#define L0_E_DRR_REVERSE_LL_TBL_DEFAULT 0x0
+	/*[field] PRE_PTR*/
+	#define L0_E_DRR_REVERSE_LL_TBL_PRE_PTR
+	#define L0_E_DRR_REVERSE_LL_TBL_PRE_PTR_OFFSET  0
+	#define L0_E_DRR_REVERSE_LL_TBL_PRE_PTR_LEN     9
+	#define L0_E_DRR_REVERSE_LL_TBL_PRE_PTR_DEFAULT 0x0
+
+struct l0_e_drr_reverse_ll_tbl {
+	a_uint32_t  pre_ptr:9;
+	a_uint32_t  _reserved0:23;
+};
+
+union l0_e_drr_reverse_ll_tbl_u {
+	a_uint32_t val;
+	struct l0_e_drr_reverse_ll_tbl bf;
+};
+
+/*[table] L0_SP_ENTRY_TBL*/
+#define L0_SP_ENTRY_TBL
+#define L0_SP_ENTRY_TBL_ADDRESS 0x18000
+#define L0_SP_ENTRY_TBL_NUM     64
+#define L0_SP_ENTRY_TBL_INC     0x20
+#define L0_SP_ENTRY_TBL_TYPE    REG_TYPE_RO
+#define L0_SP_ENTRY_TBL_DEFAULT 0x0
+	/*[field] ENTRY_PATH_ID*/
+	#define L0_SP_ENTRY_TBL_ENTRY_PATH_ID
+	#define L0_SP_ENTRY_TBL_ENTRY_PATH_ID_OFFSET  0
+	#define L0_SP_ENTRY_TBL_ENTRY_PATH_ID_LEN     144
+	#define L0_SP_ENTRY_TBL_ENTRY_PATH_ID_DEFAULT 0x0
+	/*[field] ENTRY_VLD*/
+	#define L0_SP_ENTRY_TBL_ENTRY_VLD
+	#define L0_SP_ENTRY_TBL_ENTRY_VLD_OFFSET  144
+	#define L0_SP_ENTRY_TBL_ENTRY_VLD_LEN     16
+	#define L0_SP_ENTRY_TBL_ENTRY_VLD_DEFAULT 0x0
+
+struct l0_sp_entry_tbl {
+	a_uint32_t  entry_path_id_0:32;
+	a_uint32_t  entry_path_id_1:32;
+	a_uint32_t  entry_path_id_2:32;
+	a_uint32_t  entry_path_id_3:32;
+	a_uint32_t  entry_path_id_4:16;
+	a_uint32_t  entry_vld:16;
+};
+
+union l0_sp_entry_tbl_u {
+	a_uint32_t val[5];
+	struct l0_sp_entry_tbl bf;
+};
+
+
+/*[table] L0_ENS_Q_LL_TBL*/
+#define L0_ENS_Q_LL_TBL
+#define L0_ENS_Q_LL_TBL_ADDRESS 0x1e000
+#define L0_ENS_Q_LL_TBL_NUM     300
+#define L0_ENS_Q_LL_TBL_INC     0x10
+#define L0_ENS_Q_LL_TBL_TYPE    REG_TYPE_RO
+#define L0_ENS_Q_LL_TBL_DEFAULT 0x0
+	/*[field] NEXT_PTR*/
+	#define L0_ENS_Q_LL_TBL_NEXT_PTR
+	#define L0_ENS_Q_LL_TBL_NEXT_PTR_OFFSET  0
+	#define L0_ENS_Q_LL_TBL_NEXT_PTR_LEN     9
+	#define L0_ENS_Q_LL_TBL_NEXT_PTR_DEFAULT 0x0
+
+struct l0_ens_q_ll_tbl {
+	a_uint32_t  next_ptr:9;
+	a_uint32_t  _reserved0:23;
+};
+
+union l0_ens_q_ll_tbl_u {
+	a_uint32_t val;
+	struct l0_ens_q_ll_tbl bf;
+};
+
+/*[table] L0_ENS_Q_HEAD_TBL*/
+#define L0_ENS_Q_HEAD_TBL
+#define L0_ENS_Q_HEAD_TBL_ADDRESS 0x20000
+#define L0_ENS_Q_HEAD_TBL_NUM     8
+#define L0_ENS_Q_HEAD_TBL_INC     0x10
+#define L0_ENS_Q_HEAD_TBL_TYPE    REG_TYPE_RO
+#define L0_ENS_Q_HEAD_TBL_DEFAULT 0x0
+	/*[field] TAIL*/
+	#define L0_ENS_Q_HEAD_TBL_TAIL
+	#define L0_ENS_Q_HEAD_TBL_TAIL_OFFSET  0
+	#define L0_ENS_Q_HEAD_TBL_TAIL_LEN     9
+	#define L0_ENS_Q_HEAD_TBL_TAIL_DEFAULT 0x0
+	/*[field] HEAD*/
+	#define L0_ENS_Q_HEAD_TBL_HEAD
+	#define L0_ENS_Q_HEAD_TBL_HEAD_OFFSET  9
+	#define L0_ENS_Q_HEAD_TBL_HEAD_LEN     9
+	#define L0_ENS_Q_HEAD_TBL_HEAD_DEFAULT 0x0
+	/*[field] VLD*/
+	#define L0_ENS_Q_HEAD_TBL_VLD
+	#define L0_ENS_Q_HEAD_TBL_VLD_OFFSET  18
+	#define L0_ENS_Q_HEAD_TBL_VLD_LEN     1
+	#define L0_ENS_Q_HEAD_TBL_VLD_DEFAULT 0x0
+
+struct l0_ens_q_head_tbl {
+	a_uint32_t  tail:9;
+	a_uint32_t  head:9;
+	a_uint32_t  vld:1;
+	a_uint32_t  _reserved0:13;
+};
+
+union l0_ens_q_head_tbl_u {
+	a_uint32_t val;
+	struct l0_ens_q_head_tbl bf;
+};
+
+/*[table] L0_ENS_Q_ENTRY_TBL*/
+#define L0_ENS_Q_ENTRY_TBL
+#define L0_ENS_Q_ENTRY_TBL_ADDRESS 0x22000
+#define L0_ENS_Q_ENTRY_TBL_NUM     300
+#define L0_ENS_Q_ENTRY_TBL_INC     0x10
+#define L0_ENS_Q_ENTRY_TBL_TYPE    REG_TYPE_RO
+#define L0_ENS_Q_ENTRY_TBL_DEFAULT 0x0
+	/*[field] ENTRY_ENS_TYPE*/
+	#define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE
+	#define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE_OFFSET  0
+	#define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE_LEN     2
+	#define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE_DEFAULT 0x0
+	/*[field] ENTRY_ENS_VLD*/
+	#define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD
+	#define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD_OFFSET  2
+	#define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD_LEN     1
+	#define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD_DEFAULT 0x0
+	/*[field] ENTRY_ENS_IN_Q*/
+	#define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q
+	#define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q_OFFSET  3
+	#define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q_LEN     1
+	#define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q_DEFAULT 0x0
+
+struct l0_ens_q_entry_tbl {
+	a_uint32_t  entry_ens_type:2;
+	a_uint32_t  entry_ens_vld:1;
+	a_uint32_t  entry_ens_in_q:1;
+	a_uint32_t  _reserved0:28;
+};
+
+union l0_ens_q_entry_tbl_u {
+	a_uint32_t val;
+	struct l0_ens_q_entry_tbl bf;
+};
+
+/*[table] L0_FLOW_STATUS_TBL*/
+#define L0_FLOW_STATUS_TBL
+#define L0_FLOW_STATUS_TBL_ADDRESS 0x24000
+#define L0_FLOW_STATUS_TBL_NUM     300
+#define L0_FLOW_STATUS_TBL_INC     0x10
+#define L0_FLOW_STATUS_TBL_TYPE    REG_TYPE_RO
+#define L0_FLOW_STATUS_TBL_DEFAULT 0x0
+	/*[field] EN_LEVEL*/
+	#define L0_FLOW_STATUS_TBL_EN_LEVEL
+	#define L0_FLOW_STATUS_TBL_EN_LEVEL_OFFSET  0
+	#define L0_FLOW_STATUS_TBL_EN_LEVEL_LEN     1
+	#define L0_FLOW_STATUS_TBL_EN_LEVEL_DEFAULT 0x0
+	/*[field] EN_CDRR*/
+	#define L0_FLOW_STATUS_TBL_EN_CDRR
+	#define L0_FLOW_STATUS_TBL_EN_CDRR_OFFSET  1
+	#define L0_FLOW_STATUS_TBL_EN_CDRR_LEN     1
+	#define L0_FLOW_STATUS_TBL_EN_CDRR_DEFAULT 0x0
+	/*[field] EN_EDRR*/
+	#define L0_FLOW_STATUS_TBL_EN_EDRR
+	#define L0_FLOW_STATUS_TBL_EN_EDRR_OFFSET  2
+	#define L0_FLOW_STATUS_TBL_EN_EDRR_LEN     1
+	#define L0_FLOW_STATUS_TBL_EN_EDRR_DEFAULT 0x0
+
+struct l0_flow_status_tbl {
+	a_uint32_t  en_level:1;
+	a_uint32_t  en_cdrr:1;
+	a_uint32_t  en_edrr:1;
+	a_uint32_t  _reserved0:29;
+};
+
+union l0_flow_status_tbl_u {
+	a_uint32_t val;
+	struct l0_flow_status_tbl bf;
+};
+
+
+/*[table] RING_Q_MAP_TBL*/
+#define RING_Q_MAP_TBL
+#define RING_Q_MAP_TBL_ADDRESS 0x2a000
+#define RING_Q_MAP_TBL_NUM     16
+#define RING_Q_MAP_TBL_INC     0x40
+#define RING_Q_MAP_TBL_TYPE    REG_TYPE_RW
+#define RING_Q_MAP_TBL_DEFAULT 0x0
+	/*[field] QUEUE_BITMAP*/
+	#define RING_Q_MAP_TBL_QUEUE_BITMAP
+	#define RING_Q_MAP_TBL_QUEUE_BITMAP_OFFSET  0
+	#define RING_Q_MAP_TBL_QUEUE_BITMAP_LEN     300
+	#define RING_Q_MAP_TBL_QUEUE_BITMAP_DEFAULT 0x0
+
+struct ring_q_map_tbl {
+	a_uint32_t  queue_bitmap_0:32;
+	a_uint32_t  queue_bitmap_1:32;
+	a_uint32_t  queue_bitmap_2:32;
+	a_uint32_t  queue_bitmap_3:32;
+	a_uint32_t  queue_bitmap_4:32;
+	a_uint32_t  queue_bitmap_5:32;
+	a_uint32_t  queue_bitmap_6:32;
+	a_uint32_t  queue_bitmap_7:32;
+	a_uint32_t  queue_bitmap_8:32;
+	a_uint32_t  queue_bitmap_9:12;
+	a_uint32_t  _reserved0:20;
+};
+
+union ring_q_map_tbl_u {
+	a_uint32_t val[10];
+	struct ring_q_map_tbl bf;
+};
+
+/*[table] RFC_BLOCK_TBL*/
+#define RFC_BLOCK_TBL
+#define RFC_BLOCK_TBL_ADDRESS 0x2c000
+#define RFC_BLOCK_TBL_NUM     300
+#define RFC_BLOCK_TBL_INC     0x10
+#define RFC_BLOCK_TBL_TYPE    REG_TYPE_RO
+#define RFC_BLOCK_TBL_DEFAULT 0x0
+	/*[field] RFC_BLOCK*/
+	#define RFC_BLOCK_TBL_RFC_BLOCK
+	#define RFC_BLOCK_TBL_RFC_BLOCK_OFFSET  0
+	#define RFC_BLOCK_TBL_RFC_BLOCK_LEN     1
+	#define RFC_BLOCK_TBL_RFC_BLOCK_DEFAULT 0x0
+
+struct rfc_block_tbl {
+	a_uint32_t  rfc_block:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union rfc_block_tbl_u {
+	a_uint32_t val;
+	struct rfc_block_tbl bf;
+};
+
+/*[table] RFC_STATUS_TBL*/
+#define RFC_STATUS_TBL
+#define RFC_STATUS_TBL_ADDRESS 0x2e000
+#define RFC_STATUS_TBL_NUM     300
+#define RFC_STATUS_TBL_INC     0x10
+#define RFC_STATUS_TBL_TYPE    REG_TYPE_RO
+#define RFC_STATUS_TBL_DEFAULT 0x0
+	/*[field] RFC_STATUS*/
+	#define RFC_STATUS_TBL_RFC_STATUS
+	#define RFC_STATUS_TBL_RFC_STATUS_OFFSET  0
+	#define RFC_STATUS_TBL_RFC_STATUS_LEN     1
+	#define RFC_STATUS_TBL_RFC_STATUS_DEFAULT 0x0
+
+struct rfc_status_tbl {
+	a_uint32_t  rfc_status:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union rfc_status_tbl_u {
+	a_uint32_t val;
+	struct rfc_status_tbl bf;
+};
+
+/*[table] DEQ_DIS_TBL*/
+#define DEQ_DIS_TBL
+#define DEQ_DIS_TBL_ADDRESS 0x30000
+#define DEQ_DIS_TBL_NUM     300
+#define DEQ_DIS_TBL_INC     0x10
+#define DEQ_DIS_TBL_TYPE    REG_TYPE_RW
+#define DEQ_DIS_TBL_DEFAULT 0x0
+	/*[field] DEQ_DIS*/
+	#define DEQ_DIS_TBL_DEQ_DIS
+	#define DEQ_DIS_TBL_DEQ_DIS_OFFSET  0
+	#define DEQ_DIS_TBL_DEQ_DIS_LEN     1
+	#define DEQ_DIS_TBL_DEQ_DIS_DEFAULT 0x0
+
+struct deq_dis_tbl {
+	a_uint32_t  deq_dis:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union deq_dis_tbl_u {
+	a_uint32_t val;
+	struct deq_dis_tbl bf;
+};
+
+/*[table] L1_FLOW_MAP_TBL*/
+#define L1_FLOW_MAP_TBL
+#define L1_FLOW_MAP_TBL_ADDRESS 0x40000
+#define L1_FLOW_MAP_TBL_NUM     64
+#define L1_FLOW_MAP_TBL_INC     0x10
+#define L1_FLOW_MAP_TBL_TYPE    REG_TYPE_RW
+#define L1_FLOW_MAP_TBL_DEFAULT 0x0
+	/*[field] SP_ID*/
+	#define L1_FLOW_MAP_TBL_SP_ID
+	#define L1_FLOW_MAP_TBL_SP_ID_OFFSET  0
+	#define L1_FLOW_MAP_TBL_SP_ID_LEN     4
+	#define L1_FLOW_MAP_TBL_SP_ID_DEFAULT 0x0
+	/*[field] C_PRI*/
+	#define L1_FLOW_MAP_TBL_C_PRI
+	#define L1_FLOW_MAP_TBL_C_PRI_OFFSET  4
+	#define L1_FLOW_MAP_TBL_C_PRI_LEN     3
+	#define L1_FLOW_MAP_TBL_C_PRI_DEFAULT 0x0
+	/*[field] E_PRI*/
+	#define L1_FLOW_MAP_TBL_E_PRI
+	#define L1_FLOW_MAP_TBL_E_PRI_OFFSET  7
+	#define L1_FLOW_MAP_TBL_E_PRI_LEN     3
+	#define L1_FLOW_MAP_TBL_E_PRI_DEFAULT 0x0
+	/*[field] C_DRR_WT*/
+	#define L1_FLOW_MAP_TBL_C_DRR_WT
+	#define L1_FLOW_MAP_TBL_C_DRR_WT_OFFSET  10
+	#define L1_FLOW_MAP_TBL_C_DRR_WT_LEN     10
+	#define L1_FLOW_MAP_TBL_C_DRR_WT_DEFAULT 0x0
+	/*[field] E_DRR_WT*/
+	#define L1_FLOW_MAP_TBL_E_DRR_WT
+	#define L1_FLOW_MAP_TBL_E_DRR_WT_OFFSET  20
+	#define L1_FLOW_MAP_TBL_E_DRR_WT_LEN     10
+	#define L1_FLOW_MAP_TBL_E_DRR_WT_DEFAULT 0x0
+
+struct l1_flow_map_tbl {
+	a_uint32_t  sp_id:4;
+	a_uint32_t  c_pri:3;
+	a_uint32_t  e_pri:3;
+	a_uint32_t  c_drr_wt:10;
+	a_uint32_t  e_drr_wt:10;
+	a_uint32_t  _reserved0:2;
+};
+
+union l1_flow_map_tbl_u {
+	a_uint32_t val;
+	struct l1_flow_map_tbl bf;
+};
+
+/*[table] L1_C_SP_CFG_TBL*/
+#define L1_C_SP_CFG_TBL
+#define L1_C_SP_CFG_TBL_ADDRESS 0x42000
+#define L1_C_SP_CFG_TBL_NUM     64
+#define L1_C_SP_CFG_TBL_INC     0x10
+#define L1_C_SP_CFG_TBL_TYPE    REG_TYPE_RW
+#define L1_C_SP_CFG_TBL_DEFAULT 0x0
+	/*[field] DRR_ID*/
+	#define L1_C_SP_CFG_TBL_DRR_ID
+	#define L1_C_SP_CFG_TBL_DRR_ID_OFFSET  0
+	#define L1_C_SP_CFG_TBL_DRR_ID_LEN     6
+	#define L1_C_SP_CFG_TBL_DRR_ID_DEFAULT 0x0
+	/*[field] DRR_CREDIT_UNIT*/
+	#define L1_C_SP_CFG_TBL_DRR_CREDIT_UNIT
+	#define L1_C_SP_CFG_TBL_DRR_CREDIT_UNIT_OFFSET  6
+	#define L1_C_SP_CFG_TBL_DRR_CREDIT_UNIT_LEN     1
+	#define L1_C_SP_CFG_TBL_DRR_CREDIT_UNIT_DEFAULT 0x0
+
+struct l1_c_sp_cfg_tbl {
+	a_uint32_t  drr_id:6;
+	a_uint32_t  drr_credit_unit:1;
+	a_uint32_t  _reserved0:25;
+};
+
+union l1_c_sp_cfg_tbl_u {
+	a_uint32_t val;
+	struct l1_c_sp_cfg_tbl bf;
+};
+
+/*[table] L1_E_SP_CFG_TBL*/
+#define L1_E_SP_CFG_TBL
+#define L1_E_SP_CFG_TBL_ADDRESS 0x44000
+#define L1_E_SP_CFG_TBL_NUM     64
+#define L1_E_SP_CFG_TBL_INC     0x10
+#define L1_E_SP_CFG_TBL_TYPE    REG_TYPE_RW
+#define L1_E_SP_CFG_TBL_DEFAULT 0x0
+	/*[field] DRR_ID*/
+	#define L1_E_SP_CFG_TBL_DRR_ID
+	#define L1_E_SP_CFG_TBL_DRR_ID_OFFSET  0
+	#define L1_E_SP_CFG_TBL_DRR_ID_LEN     6
+	#define L1_E_SP_CFG_TBL_DRR_ID_DEFAULT 0x0
+	/*[field] DRR_CREDIT_UNIT*/
+	#define L1_E_SP_CFG_TBL_DRR_CREDIT_UNIT
+	#define L1_E_SP_CFG_TBL_DRR_CREDIT_UNIT_OFFSET  6
+	#define L1_E_SP_CFG_TBL_DRR_CREDIT_UNIT_LEN     1
+	#define L1_E_SP_CFG_TBL_DRR_CREDIT_UNIT_DEFAULT 0x0
+
+struct l1_e_sp_cfg_tbl {
+	a_uint32_t  drr_id:6;
+	a_uint32_t  drr_credit_unit:1;
+	a_uint32_t  _reserved0:25;
+};
+
+union l1_e_sp_cfg_tbl_u {
+	a_uint32_t val;
+	struct l1_e_sp_cfg_tbl bf;
+};
+
+/*[table] L1_FLOW_PORT_MAP_TBL*/
+#define L1_FLOW_PORT_MAP_TBL
+#define L1_FLOW_PORT_MAP_TBL_ADDRESS 0x46000
+#define L1_FLOW_PORT_MAP_TBL_NUM     64
+#define L1_FLOW_PORT_MAP_TBL_INC     0x10
+#define L1_FLOW_PORT_MAP_TBL_TYPE    REG_TYPE_RW
+#define L1_FLOW_PORT_MAP_TBL_DEFAULT 0x0
+	/*[field] PORT_NUM*/
+	#define L1_FLOW_PORT_MAP_TBL_PORT_NUM
+	#define L1_FLOW_PORT_MAP_TBL_PORT_NUM_OFFSET  0
+	#define L1_FLOW_PORT_MAP_TBL_PORT_NUM_LEN     4
+	#define L1_FLOW_PORT_MAP_TBL_PORT_NUM_DEFAULT 0x0
+
+struct l1_flow_port_map_tbl {
+	a_uint32_t  port_num:4;
+	a_uint32_t  _reserved0:28;
+};
+
+union l1_flow_port_map_tbl_u {
+	a_uint32_t val;
+	struct l1_flow_port_map_tbl bf;
+};
+
+/*[table] L1_C_DRR_HEAD_TBL*/
+#define L1_C_DRR_HEAD_TBL
+#define L1_C_DRR_HEAD_TBL_ADDRESS 0x48000
+#define L1_C_DRR_HEAD_TBL_NUM     36
+#define L1_C_DRR_HEAD_TBL_INC     0x10
+#define L1_C_DRR_HEAD_TBL_TYPE    REG_TYPE_RO
+#define L1_C_DRR_HEAD_TBL_DEFAULT 0x0
+	/*[field] BACKUP_TAIL*/
+	#define L1_C_DRR_HEAD_TBL_BACKUP_TAIL
+	#define L1_C_DRR_HEAD_TBL_BACKUP_TAIL_OFFSET  0
+	#define L1_C_DRR_HEAD_TBL_BACKUP_TAIL_LEN     6
+	#define L1_C_DRR_HEAD_TBL_BACKUP_TAIL_DEFAULT 0x0
+	/*[field] BACKUP_HEAD*/
+	#define L1_C_DRR_HEAD_TBL_BACKUP_HEAD
+	#define L1_C_DRR_HEAD_TBL_BACKUP_HEAD_OFFSET  6
+	#define L1_C_DRR_HEAD_TBL_BACKUP_HEAD_LEN     6
+	#define L1_C_DRR_HEAD_TBL_BACKUP_HEAD_DEFAULT 0x0
+	/*[field] BACKUP_VLD*/
+	#define L1_C_DRR_HEAD_TBL_BACKUP_VLD
+	#define L1_C_DRR_HEAD_TBL_BACKUP_VLD_OFFSET  12
+	#define L1_C_DRR_HEAD_TBL_BACKUP_VLD_LEN     1
+	#define L1_C_DRR_HEAD_TBL_BACKUP_VLD_DEFAULT 0x0
+	/*[field] BACKUP_MAX_N*/
+	#define L1_C_DRR_HEAD_TBL_BACKUP_MAX_N
+	#define L1_C_DRR_HEAD_TBL_BACKUP_MAX_N_OFFSET  13
+	#define L1_C_DRR_HEAD_TBL_BACKUP_MAX_N_LEN     5
+	#define L1_C_DRR_HEAD_TBL_BACKUP_MAX_N_DEFAULT 0x0
+	/*[field] ACTIVE_TAIL*/
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_TAIL
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_TAIL_OFFSET  18
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_TAIL_LEN     6
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_TAIL_DEFAULT 0x0
+	/*[field] ACTIVE_HEAD*/
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_HEAD
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_HEAD_OFFSET  24
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_HEAD_LEN     6
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_HEAD_DEFAULT 0x0
+	/*[field] ACTIVE_VLD*/
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_VLD
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_VLD_OFFSET  30
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_VLD_LEN     1
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_VLD_DEFAULT 0x0
+	/*[field] ACTIVE_MAX_N*/
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_MAX_N
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_MAX_N_OFFSET  31
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_MAX_N_LEN     5
+	#define L1_C_DRR_HEAD_TBL_ACTIVE_MAX_N_DEFAULT 0x0
+
+struct l1_c_drr_head_tbl {
+	a_uint32_t  backup_tail:6;
+	a_uint32_t  backup_head:6;
+	a_uint32_t  backup_vld:1;
+	a_uint32_t  backup_max_n:5;
+	a_uint32_t  active_tail:6;
+	a_uint32_t  active_head:6;
+	a_uint32_t  active_vld:1;
+	a_uint32_t  active_max_n_0:1;
+	a_uint32_t  active_max_n_1:4;
+	a_uint32_t  _reserved0:28;
+};
+
+union l1_c_drr_head_tbl_u {
+	a_uint32_t val[2];
+	struct l1_c_drr_head_tbl bf;
+};
+
+/*[table] L1_E_DRR_HEAD_TBL*/
+#define L1_E_DRR_HEAD_TBL
+#define L1_E_DRR_HEAD_TBL_ADDRESS 0x4a000
+#define L1_E_DRR_HEAD_TBL_NUM     36
+#define L1_E_DRR_HEAD_TBL_INC     0x10
+#define L1_E_DRR_HEAD_TBL_TYPE    REG_TYPE_RO
+#define L1_E_DRR_HEAD_TBL_DEFAULT 0x0
+	/*[field] BACKUP_TAIL*/
+	#define L1_E_DRR_HEAD_TBL_BACKUP_TAIL
+	#define L1_E_DRR_HEAD_TBL_BACKUP_TAIL_OFFSET  0
+	#define L1_E_DRR_HEAD_TBL_BACKUP_TAIL_LEN     6
+	#define L1_E_DRR_HEAD_TBL_BACKUP_TAIL_DEFAULT 0x0
+	/*[field] BACKUP_HEAD*/
+	#define L1_E_DRR_HEAD_TBL_BACKUP_HEAD
+	#define L1_E_DRR_HEAD_TBL_BACKUP_HEAD_OFFSET  6
+	#define L1_E_DRR_HEAD_TBL_BACKUP_HEAD_LEN     6
+	#define L1_E_DRR_HEAD_TBL_BACKUP_HEAD_DEFAULT 0x0
+	/*[field] BACKUP_VLD*/
+	#define L1_E_DRR_HEAD_TBL_BACKUP_VLD
+	#define L1_E_DRR_HEAD_TBL_BACKUP_VLD_OFFSET  12
+	#define L1_E_DRR_HEAD_TBL_BACKUP_VLD_LEN     1
+	#define L1_E_DRR_HEAD_TBL_BACKUP_VLD_DEFAULT 0x0
+	/*[field] BACKUP_MAX_N*/
+	#define L1_E_DRR_HEAD_TBL_BACKUP_MAX_N
+	#define L1_E_DRR_HEAD_TBL_BACKUP_MAX_N_OFFSET  13
+	#define L1_E_DRR_HEAD_TBL_BACKUP_MAX_N_LEN     5
+	#define L1_E_DRR_HEAD_TBL_BACKUP_MAX_N_DEFAULT 0x0
+	/*[field] ACTIVE_TAIL*/
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_TAIL
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_TAIL_OFFSET  18
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_TAIL_LEN     6
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_TAIL_DEFAULT 0x0
+	/*[field] ACTIVE_HEAD*/
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_HEAD
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_HEAD_OFFSET  24
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_HEAD_LEN     6
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_HEAD_DEFAULT 0x0
+	/*[field] ACTIVE_VLD*/
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_VLD
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_VLD_OFFSET  30
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_VLD_LEN     1
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_VLD_DEFAULT 0x0
+	/*[field] ACTIVE_MAX_N*/
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_MAX_N
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_MAX_N_OFFSET  31
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_MAX_N_LEN     5
+	#define L1_E_DRR_HEAD_TBL_ACTIVE_MAX_N_DEFAULT 0x0
+
+struct l1_e_drr_head_tbl {
+	a_uint32_t  backup_tail:6;
+	a_uint32_t  backup_head:6;
+	a_uint32_t  backup_vld:1;
+	a_uint32_t  backup_max_n:5;
+	a_uint32_t  active_tail:6;
+	a_uint32_t  active_head:6;
+	a_uint32_t  active_vld:1;
+	a_uint32_t  active_max_n_0:1;
+	a_uint32_t  active_max_n_1:4;
+	a_uint32_t  _reserved0:28;
+};
+
+union l1_e_drr_head_tbl_u {
+	a_uint32_t val[2];
+	struct l1_e_drr_head_tbl bf;
+};
+
+/*[table] L1_DRR_CREDIT_TBL*/
+#define L1_DRR_CREDIT_TBL
+#define L1_DRR_CREDIT_TBL_ADDRESS 0x4c000
+#define L1_DRR_CREDIT_TBL_NUM     64
+#define L1_DRR_CREDIT_TBL_INC     0x10
+#define L1_DRR_CREDIT_TBL_TYPE    REG_TYPE_RO
+#define L1_DRR_CREDIT_TBL_DEFAULT 0x0
+	/*[field] C_DRR_CREDIT*/
+	#define L1_DRR_CREDIT_TBL_C_DRR_CREDIT
+	#define L1_DRR_CREDIT_TBL_C_DRR_CREDIT_OFFSET  0
+	#define L1_DRR_CREDIT_TBL_C_DRR_CREDIT_LEN     24
+	#define L1_DRR_CREDIT_TBL_C_DRR_CREDIT_DEFAULT 0x0
+	/*[field] C_DRR_CREDIT_NEG*/
+	#define L1_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG
+	#define L1_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG_OFFSET  24
+	#define L1_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG_LEN     1
+	#define L1_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG_DEFAULT 0x0
+	/*[field] E_DRR_CREDIT*/
+	#define L1_DRR_CREDIT_TBL_E_DRR_CREDIT
+	#define L1_DRR_CREDIT_TBL_E_DRR_CREDIT_OFFSET  25
+	#define L1_DRR_CREDIT_TBL_E_DRR_CREDIT_LEN     24
+	#define L1_DRR_CREDIT_TBL_E_DRR_CREDIT_DEFAULT 0x0
+	/*[field] E_DRR_CREDIT_NEG*/
+	#define L1_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG
+	#define L1_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG_OFFSET  49
+	#define L1_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG_LEN     1
+	#define L1_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG_DEFAULT 0x0
+
+struct l1_drr_credit_tbl {
+	a_uint32_t  c_drr_credit:24;
+	a_uint32_t  c_drr_credit_neg:1;
+	a_uint32_t  e_drr_credit_0:7;
+	a_uint32_t  e_drr_credit_1:17;
+	a_uint32_t  e_drr_credit_neg:1;
+	a_uint32_t  _reserved0:14;
+};
+
+union l1_drr_credit_tbl_u {
+	a_uint32_t val[2];
+	struct l1_drr_credit_tbl bf;
+};
+
+/*[table] L1_C_DRR_LL_TBL*/
+#define L1_C_DRR_LL_TBL
+#define L1_C_DRR_LL_TBL_ADDRESS 0x4e000
+#define L1_C_DRR_LL_TBL_NUM     64
+#define L1_C_DRR_LL_TBL_INC     0x10
+#define L1_C_DRR_LL_TBL_TYPE    REG_TYPE_RO
+#define L1_C_DRR_LL_TBL_DEFAULT 0x0
+	/*[field] NEXT_PTR*/
+	#define L1_C_DRR_LL_TBL_NEXT_PTR
+	#define L1_C_DRR_LL_TBL_NEXT_PTR_OFFSET  0
+	#define L1_C_DRR_LL_TBL_NEXT_PTR_LEN     6
+	#define L1_C_DRR_LL_TBL_NEXT_PTR_DEFAULT 0x0
+
+struct l1_c_drr_ll_tbl {
+	a_uint32_t  next_ptr:6;
+	a_uint32_t  _reserved0:26;
+};
+
+union l1_c_drr_ll_tbl_u {
+	a_uint32_t val;
+	struct l1_c_drr_ll_tbl bf;
+};
+
+/*[table] L1_C_DRR_REVERSE_LL_TBL*/
+#define L1_C_DRR_REVERSE_LL_TBL
+#define L1_C_DRR_REVERSE_LL_TBL_ADDRESS 0x50000
+#define L1_C_DRR_REVERSE_LL_TBL_NUM     64
+#define L1_C_DRR_REVERSE_LL_TBL_INC     0x10
+#define L1_C_DRR_REVERSE_LL_TBL_TYPE    REG_TYPE_RO
+#define L1_C_DRR_REVERSE_LL_TBL_DEFAULT 0x0
+	/*[field] PRE_PTR*/
+	#define L1_C_DRR_REVERSE_LL_TBL_PRE_PTR
+	#define L1_C_DRR_REVERSE_LL_TBL_PRE_PTR_OFFSET  0
+	#define L1_C_DRR_REVERSE_LL_TBL_PRE_PTR_LEN     6
+	#define L1_C_DRR_REVERSE_LL_TBL_PRE_PTR_DEFAULT 0x0
+
+struct l1_c_drr_reverse_ll_tbl {
+	a_uint32_t  pre_ptr:6;
+	a_uint32_t  _reserved0:26;
+};
+
+union l1_c_drr_reverse_ll_tbl_u {
+	a_uint32_t val;
+	struct l1_c_drr_reverse_ll_tbl bf;
+};
+
+/*[table] L1_E_DRR_LL_TBL*/
+#define L1_E_DRR_LL_TBL
+#define L1_E_DRR_LL_TBL_ADDRESS 0x52000
+#define L1_E_DRR_LL_TBL_NUM     64
+#define L1_E_DRR_LL_TBL_INC     0x10
+#define L1_E_DRR_LL_TBL_TYPE    REG_TYPE_RO
+#define L1_E_DRR_LL_TBL_DEFAULT 0x0
+	/*[field] NEXT_PTR*/
+	#define L1_E_DRR_LL_TBL_NEXT_PTR
+	#define L1_E_DRR_LL_TBL_NEXT_PTR_OFFSET  0
+	#define L1_E_DRR_LL_TBL_NEXT_PTR_LEN     6
+	#define L1_E_DRR_LL_TBL_NEXT_PTR_DEFAULT 0x0
+
+struct l1_e_drr_ll_tbl {
+	a_uint32_t  next_ptr:6;
+	a_uint32_t  _reserved0:26;
+};
+
+union l1_e_drr_ll_tbl_u {
+	a_uint32_t val;
+	struct l1_e_drr_ll_tbl bf;
+};
+
+/*[table] L1_E_DRR_REVERSE_LL_TBL*/
+#define L1_E_DRR_REVERSE_LL_TBL
+#define L1_E_DRR_REVERSE_LL_TBL_ADDRESS 0x54000
+#define L1_E_DRR_REVERSE_LL_TBL_NUM     64
+#define L1_E_DRR_REVERSE_LL_TBL_INC     0x10
+#define L1_E_DRR_REVERSE_LL_TBL_TYPE    REG_TYPE_RO
+#define L1_E_DRR_REVERSE_LL_TBL_DEFAULT 0x0
+	/*[field] PRE_PTR*/
+	#define L1_E_DRR_REVERSE_LL_TBL_PRE_PTR
+	#define L1_E_DRR_REVERSE_LL_TBL_PRE_PTR_OFFSET  0
+	#define L1_E_DRR_REVERSE_LL_TBL_PRE_PTR_LEN     6
+	#define L1_E_DRR_REVERSE_LL_TBL_PRE_PTR_DEFAULT 0x0
+
+struct l1_e_drr_reverse_ll_tbl {
+	a_uint32_t  pre_ptr:6;
+	a_uint32_t  _reserved0:26;
+};
+
+union l1_e_drr_reverse_ll_tbl_u {
+	a_uint32_t val;
+	struct l1_e_drr_reverse_ll_tbl bf;
+};
+
+/*[table] L1_A_FLOW_ENTRY_TBL*/
+#define L1_A_FLOW_ENTRY_TBL
+#define L1_A_FLOW_ENTRY_TBL_ADDRESS 0x56000
+#define L1_A_FLOW_ENTRY_TBL_NUM     64
+#define L1_A_FLOW_ENTRY_TBL_INC     0x10
+#define L1_A_FLOW_ENTRY_TBL_TYPE    REG_TYPE_RO
+#define L1_A_FLOW_ENTRY_TBL_DEFAULT 0x0
+	/*[field] ENTRY_PATH_ID*/
+	#define L1_A_FLOW_ENTRY_TBL_ENTRY_PATH_ID
+	#define L1_A_FLOW_ENTRY_TBL_ENTRY_PATH_ID_OFFSET  0
+	#define L1_A_FLOW_ENTRY_TBL_ENTRY_PATH_ID_LEN     10
+	#define L1_A_FLOW_ENTRY_TBL_ENTRY_PATH_ID_DEFAULT 0x0
+
+struct l1_a_flow_entry_tbl {
+	a_uint32_t  entry_path_id:10;
+	a_uint32_t  _reserved0:22;
+};
+
+union l1_a_flow_entry_tbl_u {
+	a_uint32_t val;
+	struct l1_a_flow_entry_tbl bf;
+};
+
+/*[table] L1_B_FLOW_ENTRY_TBL*/
+#define L1_B_FLOW_ENTRY_TBL
+#define L1_B_FLOW_ENTRY_TBL_ADDRESS 0x58000
+#define L1_B_FLOW_ENTRY_TBL_NUM     64
+#define L1_B_FLOW_ENTRY_TBL_INC     0x10
+#define L1_B_FLOW_ENTRY_TBL_TYPE    REG_TYPE_RO
+#define L1_B_FLOW_ENTRY_TBL_DEFAULT 0x0
+	/*[field] ENTRY_PATH_ID*/
+	#define L1_B_FLOW_ENTRY_TBL_ENTRY_PATH_ID
+	#define L1_B_FLOW_ENTRY_TBL_ENTRY_PATH_ID_OFFSET  0
+	#define L1_B_FLOW_ENTRY_TBL_ENTRY_PATH_ID_LEN     10
+	#define L1_B_FLOW_ENTRY_TBL_ENTRY_PATH_ID_DEFAULT 0x0
+
+struct l1_b_flow_entry_tbl {
+	a_uint32_t  entry_path_id:10;
+	a_uint32_t  _reserved0:22;
+};
+
+union l1_b_flow_entry_tbl_u {
+	a_uint32_t val;
+	struct l1_b_flow_entry_tbl bf;
+};
+
+/*[table] L1_SP_ENTRY_TBL*/
+#define L1_SP_ENTRY_TBL
+#define L1_SP_ENTRY_TBL_ADDRESS 0x5a000
+#define L1_SP_ENTRY_TBL_NUM     8
+#define L1_SP_ENTRY_TBL_INC     0x40
+#define L1_SP_ENTRY_TBL_TYPE    REG_TYPE_RO
+#define L1_SP_ENTRY_TBL_DEFAULT 0x0
+	/*[field] ENTRY_PATH_ID*/
+	#define L1_SP_ENTRY_TBL_ENTRY_PATH_ID
+	#define L1_SP_ENTRY_TBL_ENTRY_PATH_ID_OFFSET  0
+	#define L1_SP_ENTRY_TBL_ENTRY_PATH_ID_LEN     256
+	#define L1_SP_ENTRY_TBL_ENTRY_PATH_ID_DEFAULT 0x0
+	/*[field] ENTRY_VLD*/
+	#define L1_SP_ENTRY_TBL_ENTRY_VLD
+	#define L1_SP_ENTRY_TBL_ENTRY_VLD_OFFSET  256
+	#define L1_SP_ENTRY_TBL_ENTRY_VLD_LEN     16
+	#define L1_SP_ENTRY_TBL_ENTRY_VLD_DEFAULT 0x0
+
+struct l1_sp_entry_tbl {
+	a_uint32_t  entry_path_id_0:32;
+	a_uint32_t  entry_path_id_1:32;
+	a_uint32_t  entry_path_id_2:32;
+	a_uint32_t  entry_path_id_3:32;
+	a_uint32_t  entry_path_id_4:32;
+	a_uint32_t  entry_path_id_5:32;
+	a_uint32_t  entry_path_id_6:32;
+	a_uint32_t  entry_path_id_7:32;
+	a_uint32_t  entry_vld:16;
+	a_uint32_t  _reserved0:16;
+};
+
+union l1_sp_entry_tbl_u {
+	a_uint32_t val[9];
+	struct l1_sp_entry_tbl bf;
+};
+
+
+/*[table] L1_ENS_Q_LL_TBL*/
+#define L1_ENS_Q_LL_TBL
+#define L1_ENS_Q_LL_TBL_ADDRESS 0x60000
+#define L1_ENS_Q_LL_TBL_NUM     64
+#define L1_ENS_Q_LL_TBL_INC     0x10
+#define L1_ENS_Q_LL_TBL_TYPE    REG_TYPE_RO
+#define L1_ENS_Q_LL_TBL_DEFAULT 0x0
+	/*[field] NEXT_PTR*/
+	#define L1_ENS_Q_LL_TBL_NEXT_PTR
+	#define L1_ENS_Q_LL_TBL_NEXT_PTR_OFFSET  0
+	#define L1_ENS_Q_LL_TBL_NEXT_PTR_LEN     6
+	#define L1_ENS_Q_LL_TBL_NEXT_PTR_DEFAULT 0x0
+
+struct l1_ens_q_ll_tbl {
+	a_uint32_t  next_ptr:6;
+	a_uint32_t  _reserved0:26;
+};
+
+union l1_ens_q_ll_tbl_u {
+	a_uint32_t val;
+	struct l1_ens_q_ll_tbl bf;
+};
+
+/*[table] L1_ENS_Q_HEAD_TBL*/
+#define L1_ENS_Q_HEAD_TBL
+#define L1_ENS_Q_HEAD_TBL_ADDRESS 0x62000
+#define L1_ENS_Q_HEAD_TBL_NUM     8
+#define L1_ENS_Q_HEAD_TBL_INC     0x10
+#define L1_ENS_Q_HEAD_TBL_TYPE    REG_TYPE_RO
+#define L1_ENS_Q_HEAD_TBL_DEFAULT 0x0
+	/*[field] TAIL*/
+	#define L1_ENS_Q_HEAD_TBL_TAIL
+	#define L1_ENS_Q_HEAD_TBL_TAIL_OFFSET  0
+	#define L1_ENS_Q_HEAD_TBL_TAIL_LEN     6
+	#define L1_ENS_Q_HEAD_TBL_TAIL_DEFAULT 0x0
+	/*[field] HEAD*/
+	#define L1_ENS_Q_HEAD_TBL_HEAD
+	#define L1_ENS_Q_HEAD_TBL_HEAD_OFFSET  6
+	#define L1_ENS_Q_HEAD_TBL_HEAD_LEN     6
+	#define L1_ENS_Q_HEAD_TBL_HEAD_DEFAULT 0x0
+	/*[field] VLD*/
+	#define L1_ENS_Q_HEAD_TBL_VLD
+	#define L1_ENS_Q_HEAD_TBL_VLD_OFFSET  12
+	#define L1_ENS_Q_HEAD_TBL_VLD_LEN     1
+	#define L1_ENS_Q_HEAD_TBL_VLD_DEFAULT 0x0
+
+struct l1_ens_q_head_tbl {
+	a_uint32_t  tail:6;
+	a_uint32_t  head:6;
+	a_uint32_t  vld:1;
+	a_uint32_t  _reserved0:19;
+};
+
+union l1_ens_q_head_tbl_u {
+	a_uint32_t val;
+	struct l1_ens_q_head_tbl bf;
+};
+
+/*[table] L1_ENS_Q_ENTRY_TBL*/
+#define L1_ENS_Q_ENTRY_TBL
+#define L1_ENS_Q_ENTRY_TBL_ADDRESS 0x64000
+#define L1_ENS_Q_ENTRY_TBL_NUM     64
+#define L1_ENS_Q_ENTRY_TBL_INC     0x10
+#define L1_ENS_Q_ENTRY_TBL_TYPE    REG_TYPE_RO
+#define L1_ENS_Q_ENTRY_TBL_DEFAULT 0x0
+	/*[field] ENTRY_ENS_TYPE*/
+	#define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE
+	#define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE_OFFSET  0
+	#define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE_LEN     2
+	#define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE_DEFAULT 0x0
+	/*[field] ENTRY_ENS_VLD*/
+	#define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD
+	#define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD_OFFSET  2
+	#define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD_LEN     1
+	#define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD_DEFAULT 0x0
+	/*[field] ENTRY_ENS_IN_Q*/
+	#define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q
+	#define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q_OFFSET  3
+	#define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q_LEN     1
+	#define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q_DEFAULT 0x0
+
+struct l1_ens_q_entry_tbl {
+	a_uint32_t  entry_ens_type:2;
+	a_uint32_t  entry_ens_vld:1;
+	a_uint32_t  entry_ens_in_q:1;
+	a_uint32_t  _reserved0:28;
+};
+
+union l1_ens_q_entry_tbl_u {
+	a_uint32_t val;
+	struct l1_ens_q_entry_tbl bf;
+};
+
+/*[table] L1_FLOW_STATUS_TBL*/
+#define L1_FLOW_STATUS_TBL
+#define L1_FLOW_STATUS_TBL_ADDRESS 0x66000
+#define L1_FLOW_STATUS_TBL_NUM     64
+#define L1_FLOW_STATUS_TBL_INC     0x10
+#define L1_FLOW_STATUS_TBL_TYPE    REG_TYPE_RO
+#define L1_FLOW_STATUS_TBL_DEFAULT 0x0
+	/*[field] EN_LEVEL*/
+	#define L1_FLOW_STATUS_TBL_EN_LEVEL
+	#define L1_FLOW_STATUS_TBL_EN_LEVEL_OFFSET  0
+	#define L1_FLOW_STATUS_TBL_EN_LEVEL_LEN     1
+	#define L1_FLOW_STATUS_TBL_EN_LEVEL_DEFAULT 0x0
+	/*[field] EN_CDRR*/
+	#define L1_FLOW_STATUS_TBL_EN_CDRR
+	#define L1_FLOW_STATUS_TBL_EN_CDRR_OFFSET  1
+	#define L1_FLOW_STATUS_TBL_EN_CDRR_LEN     1
+	#define L1_FLOW_STATUS_TBL_EN_CDRR_DEFAULT 0x0
+	/*[field] EN_EDRR*/
+	#define L1_FLOW_STATUS_TBL_EN_EDRR
+	#define L1_FLOW_STATUS_TBL_EN_EDRR_OFFSET  2
+	#define L1_FLOW_STATUS_TBL_EN_EDRR_LEN     1
+	#define L1_FLOW_STATUS_TBL_EN_EDRR_DEFAULT 0x0
+
+struct l1_flow_status_tbl {
+	a_uint32_t  en_level:1;
+	a_uint32_t  en_cdrr:1;
+	a_uint32_t  en_edrr:1;
+	a_uint32_t  _reserved0:29;
+};
+
+union l1_flow_status_tbl_u {
+	a_uint32_t val;
+	struct l1_flow_status_tbl bf;
+};
+
+/*[table] PSCH_TDM_CFG_TBL*/
+#define PSCH_TDM_CFG_TBL
+#define PSCH_TDM_CFG_TBL_ADDRESS 0x7a000
+#define PSCH_TDM_CFG_TBL_NUM     128
+#define PSCH_TDM_CFG_TBL_INC     0x10
+#define PSCH_TDM_CFG_TBL_TYPE    REG_TYPE_RW
+#define PSCH_TDM_CFG_TBL_DEFAULT 0x0
+	/*[field] DES_PORT*/
+	#define PSCH_TDM_CFG_TBL_DES_PORT
+	#define PSCH_TDM_CFG_TBL_DES_PORT_OFFSET  0
+	#define PSCH_TDM_CFG_TBL_DES_PORT_LEN     4
+	#define PSCH_TDM_CFG_TBL_DES_PORT_DEFAULT 0x0
+	/*[field] ENS_PORT*/
+	#define PSCH_TDM_CFG_TBL_ENS_PORT
+	#define PSCH_TDM_CFG_TBL_ENS_PORT_OFFSET  4
+	#define PSCH_TDM_CFG_TBL_ENS_PORT_LEN     4
+	#define PSCH_TDM_CFG_TBL_ENS_PORT_DEFAULT 0x0
+	/*[field] ENS_PORT_BITMAP*/
+	#define PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP
+	#define PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP_OFFSET  8
+	#define PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP_LEN     8
+	#define PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP_DEFAULT 0x0
+
+struct psch_tdm_cfg_tbl {
+	a_uint32_t  des_port:4;
+	a_uint32_t  ens_port:4;
+	a_uint32_t  ens_port_bitmap:8;
+	a_uint32_t  _reserved0:16;
+};
+
+union psch_tdm_cfg_tbl_u {
+	a_uint32_t val;
+	struct psch_tdm_cfg_tbl bf;
+};
+
+/*[register] PORT_QOS_CTRL*/
+#define PORT_QOS_CTRL
+#define PORT_QOS_CTRL_ADDRESS 0x900
+#define PORT_QOS_CTRL_NUM     8
+#define PORT_QOS_CTRL_INC     0x10
+#define PORT_QOS_CTRL_TYPE    REG_TYPE_RW
+#define PORT_QOS_CTRL_DEFAULT 0x23440
+	/*[field] PCP_QOS_GROUP_ID*/
+	#define PORT_QOS_CTRL_PCP_QOS_GROUP_ID
+	#define PORT_QOS_CTRL_PCP_QOS_GROUP_ID_OFFSET  0
+	#define PORT_QOS_CTRL_PCP_QOS_GROUP_ID_LEN     1
+	#define PORT_QOS_CTRL_PCP_QOS_GROUP_ID_DEFAULT 0x0
+	/*[field] DSCP_QOS_GROUP_ID*/
+	#define PORT_QOS_CTRL_DSCP_QOS_GROUP_ID
+	#define PORT_QOS_CTRL_DSCP_QOS_GROUP_ID_OFFSET  1
+	#define PORT_QOS_CTRL_DSCP_QOS_GROUP_ID_LEN     1
+	#define PORT_QOS_CTRL_DSCP_QOS_GROUP_ID_DEFAULT 0x0
+	/*[field] FLOW_QOS_GROUP_ID*/
+	#define PORT_QOS_CTRL_FLOW_QOS_GROUP_ID
+	#define PORT_QOS_CTRL_FLOW_QOS_GROUP_ID_OFFSET  2
+	#define PORT_QOS_CTRL_FLOW_QOS_GROUP_ID_LEN     1
+	#define PORT_QOS_CTRL_FLOW_QOS_GROUP_ID_DEFAULT 0x0
+	/*[field] PORT_DSCP_QOS_PRI*/
+	#define PORT_QOS_CTRL_PORT_DSCP_QOS_PRI
+	#define PORT_QOS_CTRL_PORT_DSCP_QOS_PRI_OFFSET  3
+	#define PORT_QOS_CTRL_PORT_DSCP_QOS_PRI_LEN     3
+	#define PORT_QOS_CTRL_PORT_DSCP_QOS_PRI_DEFAULT 0x0
+	/*[field] PORT_PCP_QOS_PRI*/
+	#define PORT_QOS_CTRL_PORT_PCP_QOS_PRI
+	#define PORT_QOS_CTRL_PORT_PCP_QOS_PRI_OFFSET  6
+	#define PORT_QOS_CTRL_PORT_PCP_QOS_PRI_LEN     3
+	#define PORT_QOS_CTRL_PORT_PCP_QOS_PRI_DEFAULT 0x1
+	/*[field] PORT_PREHEADER_QOS_PRI*/
+	#define PORT_QOS_CTRL_PORT_PREHEADER_QOS_PRI
+	#define PORT_QOS_CTRL_PORT_PREHEADER_QOS_PRI_OFFSET  9
+	#define PORT_QOS_CTRL_PORT_PREHEADER_QOS_PRI_LEN     3
+	#define PORT_QOS_CTRL_PORT_PREHEADER_QOS_PRI_DEFAULT 0x2
+	/*[field] PORT_FLOW_QOS_PRI*/
+	#define PORT_QOS_CTRL_PORT_FLOW_QOS_PRI
+	#define PORT_QOS_CTRL_PORT_FLOW_QOS_PRI_OFFSET  12
+	#define PORT_QOS_CTRL_PORT_FLOW_QOS_PRI_LEN     3
+	#define PORT_QOS_CTRL_PORT_FLOW_QOS_PRI_DEFAULT 0x3
+	/*[field] PORT_ACL_QOS_PRI*/
+	#define PORT_QOS_CTRL_PORT_ACL_QOS_PRI
+	#define PORT_QOS_CTRL_PORT_ACL_QOS_PRI_OFFSET  15
+	#define PORT_QOS_CTRL_PORT_ACL_QOS_PRI_LEN     3
+	#define PORT_QOS_CTRL_PORT_ACL_QOS_PRI_DEFAULT 0x4
+	/*[field] PORT_PCP_CHANGE_EN*/
+	#define PORT_QOS_CTRL_PORT_PCP_CHANGE_EN
+	#define PORT_QOS_CTRL_PORT_PCP_CHANGE_EN_OFFSET  18
+	#define PORT_QOS_CTRL_PORT_PCP_CHANGE_EN_LEN     1
+	#define PORT_QOS_CTRL_PORT_PCP_CHANGE_EN_DEFAULT 0x0
+	/*[field] PORT_DEI_CHANGE_EN*/
+	#define PORT_QOS_CTRL_PORT_DEI_CHANGE_EN
+	#define PORT_QOS_CTRL_PORT_DEI_CHANGE_EN_OFFSET  19
+	#define PORT_QOS_CTRL_PORT_DEI_CHANGE_EN_LEN     1
+	#define PORT_QOS_CTRL_PORT_DEI_CHANGE_EN_DEFAULT 0x0
+	/*[field] PORT_DSCP_CHANGE_EN*/
+	#define PORT_QOS_CTRL_PORT_DSCP_CHANGE_EN
+	#define PORT_QOS_CTRL_PORT_DSCP_CHANGE_EN_OFFSET  20
+	#define PORT_QOS_CTRL_PORT_DSCP_CHANGE_EN_LEN     1
+	#define PORT_QOS_CTRL_PORT_DSCP_CHANGE_EN_DEFAULT 0x0
+
+struct port_qos_ctrl {
+	a_uint32_t  pcp_qos_group_id:1;
+	a_uint32_t  dscp_qos_group_id:1;
+	a_uint32_t  flow_qos_group_id:1;
+	a_uint32_t  port_dscp_qos_pri:3;
+	a_uint32_t  port_pcp_qos_pri:3;
+	a_uint32_t  port_preheader_qos_pri:3;
+	a_uint32_t  port_flow_qos_pri:3;
+	a_uint32_t  port_acl_qos_pri:3;
+	a_uint32_t  port_pcp_change_en:1;
+	a_uint32_t  port_dei_change_en:1;
+	a_uint32_t  port_dscp_change_en:1;
+	a_uint32_t  _reserved0:11;
+};
+
+union port_qos_ctrl_u {
+	a_uint32_t val;
+	struct port_qos_ctrl bf;
+};
+
+/*[register] PCP_QOS_GROUP_0*/
+#define PCP_QOS_GROUP_0
+#define PCP_QOS_GROUP_0_ADDRESS 0xb00
+#define PCP_QOS_GROUP_0_NUM     16
+#define PCP_QOS_GROUP_0_INC     0x4
+#define PCP_QOS_GROUP_0_TYPE    REG_TYPE_RW
+#define PCP_QOS_GROUP_0_DEFAULT 0x0
+	/*[field] QOS_INFO*/
+	#define PCP_QOS_GROUP_0_QOS_INFO
+	#define PCP_QOS_GROUP_0_QOS_INFO_OFFSET  0
+	#define PCP_QOS_GROUP_0_QOS_INFO_LEN     16
+	#define PCP_QOS_GROUP_0_QOS_INFO_DEFAULT 0x0
+
+struct pcp_qos_group_0 {
+	a_uint32_t  qos_info:16;
+	a_uint32_t  _reserved0:16;
+};
+
+union pcp_qos_group_0_u {
+	a_uint32_t val;
+	struct pcp_qos_group_0 bf;
+};
+
+/*[register] PCP_QOS_GROUP_1*/
+#define PCP_QOS_GROUP_1
+#define PCP_QOS_GROUP_1_ADDRESS 0xc00
+#define PCP_QOS_GROUP_1_NUM     16
+#define PCP_QOS_GROUP_1_INC     0x4
+#define PCP_QOS_GROUP_1_TYPE    REG_TYPE_RW
+#define PCP_QOS_GROUP_1_DEFAULT 0x0
+	/*[field] QOS_INFO*/
+	#define PCP_QOS_GROUP_1_QOS_INFO
+	#define PCP_QOS_GROUP_1_QOS_INFO_OFFSET  0
+	#define PCP_QOS_GROUP_1_QOS_INFO_LEN     16
+	#define PCP_QOS_GROUP_1_QOS_INFO_DEFAULT 0x0
+
+struct pcp_qos_group_1 {
+	a_uint32_t  qos_info:16;
+	a_uint32_t  _reserved0:16;
+};
+
+union pcp_qos_group_1_u {
+	a_uint32_t val;
+	struct pcp_qos_group_1 bf;
+};
+
+/*[register] FLOW_QOS_GROUP_0*/
+#define FLOW_QOS_GROUP_0
+#define FLOW_QOS_GROUP_0_ADDRESS 0xd00
+#define FLOW_QOS_GROUP_0_NUM     32
+#define FLOW_QOS_GROUP_0_INC     0x4
+#define FLOW_QOS_GROUP_0_TYPE    REG_TYPE_RW
+#define FLOW_QOS_GROUP_0_DEFAULT 0x0
+	/*[field] QOS_INFO*/
+	#define FLOW_QOS_GROUP_0_QOS_INFO
+	#define FLOW_QOS_GROUP_0_QOS_INFO_OFFSET  0
+	#define FLOW_QOS_GROUP_0_QOS_INFO_LEN     16
+	#define FLOW_QOS_GROUP_0_QOS_INFO_DEFAULT 0x0
+
+struct flow_qos_group_0 {
+	a_uint32_t  qos_info:16;
+	a_uint32_t  _reserved0:16;
+};
+
+union flow_qos_group_0_u {
+	a_uint32_t val;
+	struct flow_qos_group_0 bf;
+};
+
+/*[register] FLOW_QOS_GROUP_1*/
+#define FLOW_QOS_GROUP_1
+#define FLOW_QOS_GROUP_1_ADDRESS 0xe00
+#define FLOW_QOS_GROUP_1_NUM     32
+#define FLOW_QOS_GROUP_1_INC     0x4
+#define FLOW_QOS_GROUP_1_TYPE    REG_TYPE_RW
+#define FLOW_QOS_GROUP_1_DEFAULT 0x0
+	/*[field] QOS_INFO*/
+	#define FLOW_QOS_GROUP_1_QOS_INFO
+	#define FLOW_QOS_GROUP_1_QOS_INFO_OFFSET  0
+	#define FLOW_QOS_GROUP_1_QOS_INFO_LEN     16
+	#define FLOW_QOS_GROUP_1_QOS_INFO_DEFAULT 0x0
+
+struct flow_qos_group_1 {
+	a_uint32_t  qos_info:16;
+	a_uint32_t  _reserved0:16;
+};
+
+union flow_qos_group_1_u {
+	a_uint32_t val;
+	struct flow_qos_group_1 bf;
+};
+
+/*[register] DSCP_QOS_GROUP_0*/
+#define DSCP_QOS_GROUP_0
+#define DSCP_QOS_GROUP_0_ADDRESS 0x2000
+#define DSCP_QOS_GROUP_0_NUM     64
+#define DSCP_QOS_GROUP_0_INC     0x10
+#define DSCP_QOS_GROUP_0_TYPE    REG_TYPE_RW
+#define DSCP_QOS_GROUP_0_DEFAULT 0x0
+	/*[field] QOS_INFO*/
+	#define DSCP_QOS_GROUP_0_QOS_INFO
+	#define DSCP_QOS_GROUP_0_QOS_INFO_OFFSET  0
+	#define DSCP_QOS_GROUP_0_QOS_INFO_LEN     16
+	#define DSCP_QOS_GROUP_0_QOS_INFO_DEFAULT 0x0
+
+struct dscp_qos_group_0 {
+	a_uint32_t  qos_info:16;
+	a_uint32_t  _reserved0:16;
+};
+
+union dscp_qos_group_0_u {
+	a_uint32_t val;
+	struct dscp_qos_group_0 bf;
+};
+
+/*[register] DSCP_QOS_GROUP_1*/
+#define DSCP_QOS_GROUP_1
+#define DSCP_QOS_GROUP_1_ADDRESS 0x2800
+#define DSCP_QOS_GROUP_1_NUM     64
+#define DSCP_QOS_GROUP_1_INC     0x10
+#define DSCP_QOS_GROUP_1_TYPE    REG_TYPE_RW
+#define DSCP_QOS_GROUP_1_DEFAULT 0x0
+	/*[field] QOS_INFO*/
+	#define DSCP_QOS_GROUP_1_QOS_INFO
+	#define DSCP_QOS_GROUP_1_QOS_INFO_OFFSET  0
+	#define DSCP_QOS_GROUP_1_QOS_INFO_LEN     16
+	#define DSCP_QOS_GROUP_1_QOS_INFO_DEFAULT 0x0
+
+struct dscp_qos_group_1 {
+	a_uint32_t  qos_info:16;
+	a_uint32_t  _reserved0:16;
+};
+
+union dscp_qos_group_1_u {
+	a_uint32_t val;
+	struct dscp_qos_group_1 bf;
+};
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_reg_access.h b/qca-ssdk/include/hsl/hppe/hppe_reg_access.h
new file mode 100755
index 0000000..9ecc4c8
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_reg_access.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HPPE_REG_ACCESS_H_
+#define _HPPE_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "sw.h"
+
+#define EDMA_CSR_BASE_ADDR           0xb00000
+#define IPE_L3_BASE_ADDR             0x200000
+#define QUEUE_MANAGER_BASE_ADDR      0x800000
+#define TRAFFIC_MANAGER_BASE_ADDR    0x400000
+#define INGRESS_POLICER_BASE_ADDR    0x100000
+#define INGRESS_VLAN_BASE_ADDR       0x00f000
+#define IPE_L2_BASE_ADDR             0x060000
+#define IPO_CSR_BASE_ADDR            0x0b0000
+#define IPR_CSR_BASE_ADDR            0x002000
+#define NSS_MAC_CSR_BASE_ADDR        0x001000
+#define NSS_PRX_CSR_BASE_ADDR        0x00b000
+#define NSS_PTX_CSR_BASE_ADDR        0x020000
+#define NSS_BM_CSR_BASE_ADDR         0x600000
+#define NSS_XGMAC_CSR_BASE_ADDR      0x003000
+#define NSS_GLOBAL_BASE_ADDR    	 0x0
+#define NSS_UNIPHY_BASE_ADDR    0x0
+#define NSS_LPI_BASE_ADDR    0x400
+
+sw_error_t hppe_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t *val);
+sw_error_t hppe_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t val);
+sw_error_t hppe_reg_tbl_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t *val, a_uint32_t num);
+sw_error_t hppe_reg_tbl_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t *val, a_uint32_t num);
+sw_error_t hppe_uniphy_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t index, a_uint32_t *val);
+sw_error_t hppe_uniphy_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t index, a_uint32_t val);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HPPE_REG_ACCESS_H_ */
diff --git a/qca-ssdk/include/hsl/hppe/hppe_rss.h b/qca-ssdk/include/hsl/hppe/hppe_rss.h
new file mode 100755
index 0000000..3be8a95
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_rss.h
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_RSS_H_
+#define _HPPE_RSS_H_
+
+#define RSS_HASH_MIX_REG_MAX_ENTRY	11
+#define RSS_HASH_FIN_REG_MAX_ENTRY	5
+#define RSS_HASH_MIX_IPV4_REG_MAX_ENTRY	5
+#define RSS_HASH_FIN_IPV4_REG_MAX_ENTRY	5
+
+sw_error_t
+hppe_rss_hash_mask_reg_get(
+		a_uint32_t dev_id,
+		union rss_hash_mask_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_mask_reg_set(
+		a_uint32_t dev_id,
+		union rss_hash_mask_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_seed_reg_get(
+		a_uint32_t dev_id,
+		union rss_hash_seed_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_seed_reg_set(
+		a_uint32_t dev_id,
+		union rss_hash_seed_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_mix_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_mix_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_mix_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_mix_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_fin_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_fin_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_fin_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_fin_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_mask_ipv4_reg_get(
+		a_uint32_t dev_id,
+		union rss_hash_mask_ipv4_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_mask_ipv4_reg_set(
+		a_uint32_t dev_id,
+		union rss_hash_mask_ipv4_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_seed_ipv4_reg_get(
+		a_uint32_t dev_id,
+		union rss_hash_seed_ipv4_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_seed_ipv4_reg_set(
+		a_uint32_t dev_id,
+		union rss_hash_seed_ipv4_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_mix_ipv4_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_mix_ipv4_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_mix_ipv4_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_mix_ipv4_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_fin_ipv4_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_fin_ipv4_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_fin_ipv4_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_fin_ipv4_reg_u *value);
+
+sw_error_t
+hppe_rss_hash_mask_reg_fragment_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_rss_hash_mask_reg_fragment_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_rss_hash_mask_reg_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_rss_hash_mask_reg_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_rss_hash_seed_reg_seed_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_rss_hash_seed_reg_seed_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_rss_hash_mix_reg_hash_mix_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rss_hash_mix_reg_hash_mix_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rss_hash_fin_reg_fin_outer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rss_hash_fin_reg_fin_outer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rss_hash_fin_reg_fin_inner_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rss_hash_fin_reg_fin_inner_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rss_hash_mask_ipv4_reg_fragment_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_rss_hash_mask_ipv4_reg_fragment_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_rss_hash_mask_ipv4_reg_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_rss_hash_mask_ipv4_reg_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_rss_hash_seed_ipv4_reg_seed_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_rss_hash_seed_ipv4_reg_seed_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_rss_hash_mix_ipv4_reg_hash_mix_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rss_hash_mix_ipv4_reg_hash_mix_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rss_hash_fin_ipv4_reg_fin_outer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rss_hash_fin_ipv4_reg_fin_outer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rss_hash_fin_ipv4_reg_fin_inner_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rss_hash_fin_ipv4_reg_fin_inner_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_rss_reg.h b/qca-ssdk/include/hsl/hppe/hppe_rss_reg.h
new file mode 100755
index 0000000..189cb7b
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_rss_reg.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_RSS_REG_H
+#define HPPE_RSS_REG_H
+
+/*[register] RSS_HASH_MASK_REG*/
+#define RSS_HASH_MASK_REG
+#define RSS_HASH_MASK_REG_ADDRESS 0x4318
+#define RSS_HASH_MASK_REG_NUM     1
+#define RSS_HASH_MASK_REG_INC     0x4
+#define RSS_HASH_MASK_REG_TYPE    REG_TYPE_RW
+#define RSS_HASH_MASK_REG_DEFAULT 0x0
+	/*[field] MASK*/
+	#define RSS_HASH_MASK_REG_MASK
+	#define RSS_HASH_MASK_REG_MASK_OFFSET  0
+	#define RSS_HASH_MASK_REG_MASK_LEN     21
+	#define RSS_HASH_MASK_REG_MASK_DEFAULT 0x0
+	/*[field] FRAGMENT*/
+	#define RSS_HASH_MASK_REG_FRAGMENT
+	#define RSS_HASH_MASK_REG_FRAGMENT_OFFSET  28
+	#define RSS_HASH_MASK_REG_FRAGMENT_LEN     1
+	#define RSS_HASH_MASK_REG_FRAGMENT_DEFAULT 0x0
+
+struct rss_hash_mask_reg {
+	a_uint32_t  mask:21;
+	a_uint32_t  _reserved0:7;
+	a_uint32_t  fragment:1;
+	a_uint32_t  _reserved1:3;
+};
+
+union rss_hash_mask_reg_u {
+	a_uint32_t val;
+	struct rss_hash_mask_reg bf;
+};
+
+/*[register] RSS_HASH_SEED_REG*/
+#define RSS_HASH_SEED_REG
+#define RSS_HASH_SEED_REG_ADDRESS 0x431c
+#define RSS_HASH_SEED_REG_NUM     1
+#define RSS_HASH_SEED_REG_INC     0x4
+#define RSS_HASH_SEED_REG_TYPE    REG_TYPE_RW
+#define RSS_HASH_SEED_REG_DEFAULT 0x0
+	/*[field] SEED*/
+	#define RSS_HASH_SEED_REG_SEED
+	#define RSS_HASH_SEED_REG_SEED_OFFSET  0
+	#define RSS_HASH_SEED_REG_SEED_LEN     32
+	#define RSS_HASH_SEED_REG_SEED_DEFAULT 0x0
+
+struct rss_hash_seed_reg {
+	a_uint32_t  seed:32;
+};
+
+union rss_hash_seed_reg_u {
+	a_uint32_t val;
+	struct rss_hash_seed_reg bf;
+};
+
+/*[register] RSS_HASH_MIX_REG*/
+#define RSS_HASH_MIX_REG
+#define RSS_HASH_MIX_REG_ADDRESS 0x4320
+#define RSS_HASH_MIX_REG_NUM     11
+#define RSS_HASH_MIX_REG_INC     0x4
+#define RSS_HASH_MIX_REG_TYPE    REG_TYPE_RW
+#define RSS_HASH_MIX_REG_DEFAULT 0x0
+	/*[field] HASH_MIX*/
+	#define RSS_HASH_MIX_REG_HASH_MIX
+	#define RSS_HASH_MIX_REG_HASH_MIX_OFFSET  0
+	#define RSS_HASH_MIX_REG_HASH_MIX_LEN     5
+	#define RSS_HASH_MIX_REG_HASH_MIX_DEFAULT 0x0
+
+struct rss_hash_mix_reg {
+	a_uint32_t  hash_mix:5;
+	a_uint32_t  _reserved0:27;
+};
+
+union rss_hash_mix_reg_u {
+	a_uint32_t val;
+	struct rss_hash_mix_reg bf;
+};
+
+/*[register] RSS_HASH_FIN_REG*/
+#define RSS_HASH_FIN_REG
+#define RSS_HASH_FIN_REG_ADDRESS 0x4350
+#define RSS_HASH_FIN_REG_NUM     5
+#define RSS_HASH_FIN_REG_INC     0x4
+#define RSS_HASH_FIN_REG_TYPE    REG_TYPE_RW
+#define RSS_HASH_FIN_REG_DEFAULT 0x0
+	/*[field] FIN_INNER*/
+	#define RSS_HASH_FIN_REG_FIN_INNER
+	#define RSS_HASH_FIN_REG_FIN_INNER_OFFSET  0
+	#define RSS_HASH_FIN_REG_FIN_INNER_LEN     5
+	#define RSS_HASH_FIN_REG_FIN_INNER_DEFAULT 0x0
+	/*[field] FIN_OUTER*/
+	#define RSS_HASH_FIN_REG_FIN_OUTER
+	#define RSS_HASH_FIN_REG_FIN_OUTER_OFFSET  5
+	#define RSS_HASH_FIN_REG_FIN_OUTER_LEN     5
+	#define RSS_HASH_FIN_REG_FIN_OUTER_DEFAULT 0x0
+
+struct rss_hash_fin_reg {
+	a_uint32_t  fin_inner:5;
+	a_uint32_t  fin_outer:5;
+	a_uint32_t  _reserved0:22;
+};
+
+union rss_hash_fin_reg_u {
+	a_uint32_t val;
+	struct rss_hash_fin_reg bf;
+};
+
+/*[register] RSS_HASH_MASK_IPV4_REG*/
+#define RSS_HASH_MASK_IPV4_REG
+#define RSS_HASH_MASK_IPV4_REG_ADDRESS 0x4380
+#define RSS_HASH_MASK_IPV4_REG_NUM     1
+#define RSS_HASH_MASK_IPV4_REG_INC     0x4
+#define RSS_HASH_MASK_IPV4_REG_TYPE    REG_TYPE_RW
+#define RSS_HASH_MASK_IPV4_REG_DEFAULT 0x0
+	/*[field] MASK*/
+	#define RSS_HASH_MASK_IPV4_REG_MASK
+	#define RSS_HASH_MASK_IPV4_REG_MASK_OFFSET  0
+	#define RSS_HASH_MASK_IPV4_REG_MASK_LEN     21
+	#define RSS_HASH_MASK_IPV4_REG_MASK_DEFAULT 0x0
+	/*[field] FRAGMENT*/
+	#define RSS_HASH_MASK_IPV4_REG_FRAGMENT
+	#define RSS_HASH_MASK_IPV4_REG_FRAGMENT_OFFSET  28
+	#define RSS_HASH_MASK_IPV4_REG_FRAGMENT_LEN     1
+	#define RSS_HASH_MASK_IPV4_REG_FRAGMENT_DEFAULT 0x0
+
+struct rss_hash_mask_ipv4_reg {
+	a_uint32_t  mask:21;
+	a_uint32_t  _reserved0:7;
+	a_uint32_t  fragment:1;
+	a_uint32_t  _reserved1:3;
+};
+
+union rss_hash_mask_ipv4_reg_u {
+	a_uint32_t val;
+	struct rss_hash_mask_ipv4_reg bf;
+};
+
+/*[register] RSS_HASH_SEED_IPV4_REG*/
+#define RSS_HASH_SEED_IPV4_REG
+#define RSS_HASH_SEED_IPV4_REG_ADDRESS 0x4384
+#define RSS_HASH_SEED_IPV4_REG_NUM     1
+#define RSS_HASH_SEED_IPV4_REG_INC     0x4
+#define RSS_HASH_SEED_IPV4_REG_TYPE    REG_TYPE_RW
+#define RSS_HASH_SEED_IPV4_REG_DEFAULT 0x0
+	/*[field] SEED*/
+	#define RSS_HASH_SEED_IPV4_REG_SEED
+	#define RSS_HASH_SEED_IPV4_REG_SEED_OFFSET  0
+	#define RSS_HASH_SEED_IPV4_REG_SEED_LEN     32
+	#define RSS_HASH_SEED_IPV4_REG_SEED_DEFAULT 0x0
+
+struct rss_hash_seed_ipv4_reg {
+	a_uint32_t  seed:32;
+};
+
+union rss_hash_seed_ipv4_reg_u {
+	a_uint32_t val;
+	struct rss_hash_seed_ipv4_reg bf;
+};
+
+/*[register] RSS_HASH_MIX_IPV4_REG*/
+#define RSS_HASH_MIX_IPV4_REG
+#define RSS_HASH_MIX_IPV4_REG_ADDRESS 0x4390
+#define RSS_HASH_MIX_IPV4_REG_NUM     5
+#define RSS_HASH_MIX_IPV4_REG_INC     0x4
+#define RSS_HASH_MIX_IPV4_REG_TYPE    REG_TYPE_RW
+#define RSS_HASH_MIX_IPV4_REG_DEFAULT 0x0
+	/*[field] HASH_MIX*/
+	#define RSS_HASH_MIX_IPV4_REG_HASH_MIX
+	#define RSS_HASH_MIX_IPV4_REG_HASH_MIX_OFFSET  0
+	#define RSS_HASH_MIX_IPV4_REG_HASH_MIX_LEN     5
+	#define RSS_HASH_MIX_IPV4_REG_HASH_MIX_DEFAULT 0x0
+
+struct rss_hash_mix_ipv4_reg {
+	a_uint32_t  hash_mix:5;
+	a_uint32_t  _reserved0:27;
+};
+
+union rss_hash_mix_ipv4_reg_u {
+	a_uint32_t val;
+	struct rss_hash_mix_ipv4_reg bf;
+};
+
+/*[register] RSS_HASH_FIN_IPV4_REG*/
+#define RSS_HASH_FIN_IPV4_REG
+#define RSS_HASH_FIN_IPV4_REG_ADDRESS 0x43b0
+#define RSS_HASH_FIN_IPV4_REG_NUM     5
+#define RSS_HASH_FIN_IPV4_REG_INC     0x4
+#define RSS_HASH_FIN_IPV4_REG_TYPE    REG_TYPE_RW
+#define RSS_HASH_FIN_IPV4_REG_DEFAULT 0x0
+	/*[field] FIN_INNER*/
+	#define RSS_HASH_FIN_IPV4_REG_FIN_INNER
+	#define RSS_HASH_FIN_IPV4_REG_FIN_INNER_OFFSET  0
+	#define RSS_HASH_FIN_IPV4_REG_FIN_INNER_LEN     5
+	#define RSS_HASH_FIN_IPV4_REG_FIN_INNER_DEFAULT 0x0
+	/*[field] FIN_OUTER*/
+	#define RSS_HASH_FIN_IPV4_REG_FIN_OUTER
+	#define RSS_HASH_FIN_IPV4_REG_FIN_OUTER_OFFSET  5
+	#define RSS_HASH_FIN_IPV4_REG_FIN_OUTER_LEN     5
+	#define RSS_HASH_FIN_IPV4_REG_FIN_OUTER_DEFAULT 0x0
+
+struct rss_hash_fin_ipv4_reg {
+	a_uint32_t  fin_inner:5;
+	a_uint32_t  fin_outer:5;
+	a_uint32_t  _reserved0:22;
+};
+
+union rss_hash_fin_ipv4_reg_u {
+	a_uint32_t val;
+	struct rss_hash_fin_ipv4_reg bf;
+};
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_sec.h b/qca-ssdk/include/hsl/hppe/hppe_sec.h
new file mode 100755
index 0000000..e546189
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_sec.h
@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_SEC_H_
+#define _HPPE_SEC_H_
+
+#define L3_EXCEPTION_CMD_MAX_ENTRY	72
+#define L3_EXP_L3_ONLY_CTRL_MAX_ENTRY	72
+#define L3_EXP_L2_ONLY_CTRL_MAX_ENTRY	72
+#define L3_EXP_L2_FLOW_CTRL_MAX_ENTRY	72
+#define L3_EXP_L3_FLOW_CTRL_MAX_ENTRY	72
+#define L3_EXP_MULTICAST_CTRL_MAX_ENTRY	72
+
+sw_error_t
+hppe_l3_exception_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exception_cmd_u *value);
+
+sw_error_t
+hppe_l3_exception_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exception_cmd_u *value);
+
+sw_error_t
+hppe_l3_exp_l3_only_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l3_only_ctrl_u *value);
+
+sw_error_t
+hppe_l3_exp_l3_only_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l3_only_ctrl_u *value);
+
+sw_error_t
+hppe_l3_exp_l2_only_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l2_only_ctrl_u *value);
+
+sw_error_t
+hppe_l3_exp_l2_only_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l2_only_ctrl_u *value);
+
+sw_error_t
+hppe_l3_exp_l2_flow_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l2_flow_ctrl_u *value);
+
+sw_error_t
+hppe_l3_exp_l2_flow_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l2_flow_ctrl_u *value);
+
+sw_error_t
+hppe_l3_exp_l3_flow_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l3_flow_ctrl_u *value);
+
+sw_error_t
+hppe_l3_exp_l3_flow_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l3_flow_ctrl_u *value);
+
+sw_error_t
+hppe_l3_exp_multicast_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_multicast_ctrl_u *value);
+
+sw_error_t
+hppe_l3_exp_multicast_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_multicast_ctrl_u *value);
+
+sw_error_t
+hppe_l3_exception_cmd_l3_excep_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_exception_cmd_l3_excep_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_exception_cmd_de_acce_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_exception_cmd_de_acce_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_exp_l3_only_ctrl_excep_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_exp_l3_only_ctrl_excep_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_exp_l2_only_ctrl_excep_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_exp_l2_only_ctrl_excep_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_exp_l2_flow_ctrl_excep_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_exp_l2_flow_ctrl_excep_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_exp_l3_flow_ctrl_excep_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_exp_l3_flow_ctrl_excep_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_exp_multicast_ctrl_excep_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l3_exp_multicast_ctrl_excep_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l3_exception_parsing_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union l3_exception_parsing_ctrl_reg_u *value);
+
+sw_error_t
+hppe_l3_exception_parsing_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union l3_exception_parsing_ctrl_reg_u *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_get(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_0_reg_u *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_set(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_0_reg_u *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_get(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_1_reg_u *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_set(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_1_reg_u *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_get(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_2_reg_u *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_set(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_2_reg_u *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_get(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_3_reg_u *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_set(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_3_reg_u *value);
+
+sw_error_t
+hppe_l3_exception_parsing_ctrl_reg_small_hop_limit_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_exception_parsing_ctrl_reg_small_hop_limit_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l3_exception_parsing_ctrl_reg_small_ttl_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l3_exception_parsing_ctrl_reg_small_ttl_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_mask_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_mask_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_sec_reg.h b/qca-ssdk/include/hsl/hppe/hppe_sec_reg.h
new file mode 100755
index 0000000..d2ab841
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_sec_reg.h
@@ -0,0 +1,373 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_SEC_REG_H_
+#define _HPPE_SEC_REG_H_
+
+
+/*[register] L3_EXCEPTION_CMD*/
+#define L3_EXCEPTION_CMD
+#define L3_EXCEPTION_CMD_ADDRESS 0x544
+#define L3_EXCEPTION_CMD_NUM     72
+#define L3_EXCEPTION_CMD_INC     0x4
+#define L3_EXCEPTION_CMD_TYPE    REG_TYPE_RW
+#define L3_EXCEPTION_CMD_DEFAULT 0x0
+	/*[field] L3_EXCEP_CMD*/
+	#define L3_EXCEPTION_CMD_L3_EXCEP_CMD
+	#define L3_EXCEPTION_CMD_L3_EXCEP_CMD_OFFSET  0
+	#define L3_EXCEPTION_CMD_L3_EXCEP_CMD_LEN     2
+	#define L3_EXCEPTION_CMD_L3_EXCEP_CMD_DEFAULT 0x0
+	/*[field] DE_ACCE*/
+	#define L3_EXCEPTION_CMD_DE_ACCE
+	#define L3_EXCEPTION_CMD_DE_ACCE_OFFSET  2
+	#define L3_EXCEPTION_CMD_DE_ACCE_LEN     1
+	#define L3_EXCEPTION_CMD_DE_ACCE_DEFAULT 0x0
+
+struct l3_exception_cmd {
+	a_uint32_t  l3_excep_cmd:2;
+	a_uint32_t  de_acce:1;
+	a_uint32_t  _reserved0:29;
+};
+
+union l3_exception_cmd_u {
+	a_uint32_t val;
+	struct l3_exception_cmd bf;
+};
+
+/*[register] L3_EXP_L3_ONLY_CTRL*/
+#define L3_EXP_L3_ONLY_CTRL
+#define L3_EXP_L3_ONLY_CTRL_ADDRESS 0x664
+#define L3_EXP_L3_ONLY_CTRL_NUM     72
+#define L3_EXP_L3_ONLY_CTRL_INC     0x4
+#define L3_EXP_L3_ONLY_CTRL_TYPE    REG_TYPE_RW
+#define L3_EXP_L3_ONLY_CTRL_DEFAULT 0x0
+	/*[field] EXCEP_EN*/
+	#define L3_EXP_L3_ONLY_CTRL_EXCEP_EN
+	#define L3_EXP_L3_ONLY_CTRL_EXCEP_EN_OFFSET  0
+	#define L3_EXP_L3_ONLY_CTRL_EXCEP_EN_LEN     1
+	#define L3_EXP_L3_ONLY_CTRL_EXCEP_EN_DEFAULT 0x0
+
+struct l3_exp_l3_only_ctrl {
+	a_uint32_t  excep_en:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union l3_exp_l3_only_ctrl_u {
+	a_uint32_t val;
+	struct l3_exp_l3_only_ctrl bf;
+};
+
+/*[register] L3_EXP_L2_ONLY_CTRL*/
+#define L3_EXP_L2_ONLY_CTRL
+#define L3_EXP_L2_ONLY_CTRL_ADDRESS 0x784
+#define L3_EXP_L2_ONLY_CTRL_NUM     72
+#define L3_EXP_L2_ONLY_CTRL_INC     0x4
+#define L3_EXP_L2_ONLY_CTRL_TYPE    REG_TYPE_RW
+#define L3_EXP_L2_ONLY_CTRL_DEFAULT 0x0
+	/*[field] EXCEP_EN*/
+	#define L3_EXP_L2_ONLY_CTRL_EXCEP_EN
+	#define L3_EXP_L2_ONLY_CTRL_EXCEP_EN_OFFSET  0
+	#define L3_EXP_L2_ONLY_CTRL_EXCEP_EN_LEN     1
+	#define L3_EXP_L2_ONLY_CTRL_EXCEP_EN_DEFAULT 0x0
+
+struct l3_exp_l2_only_ctrl {
+	a_uint32_t  excep_en:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union l3_exp_l2_only_ctrl_u {
+	a_uint32_t val;
+	struct l3_exp_l2_only_ctrl bf;
+};
+
+/*[register] L3_EXP_L2_FLOW_CTRL*/
+#define L3_EXP_L2_FLOW_CTRL
+#define L3_EXP_L2_FLOW_CTRL_ADDRESS 0x8a4
+#define L3_EXP_L2_FLOW_CTRL_NUM     72
+#define L3_EXP_L2_FLOW_CTRL_INC     0x4
+#define L3_EXP_L2_FLOW_CTRL_TYPE    REG_TYPE_RW
+#define L3_EXP_L2_FLOW_CTRL_DEFAULT 0x0
+	/*[field] EXCEP_EN*/
+	#define L3_EXP_L2_FLOW_CTRL_EXCEP_EN
+	#define L3_EXP_L2_FLOW_CTRL_EXCEP_EN_OFFSET  0
+	#define L3_EXP_L2_FLOW_CTRL_EXCEP_EN_LEN     1
+	#define L3_EXP_L2_FLOW_CTRL_EXCEP_EN_DEFAULT 0x0
+
+struct l3_exp_l2_flow_ctrl {
+	a_uint32_t  excep_en:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union l3_exp_l2_flow_ctrl_u {
+	a_uint32_t val;
+	struct l3_exp_l2_flow_ctrl bf;
+};
+
+/*[register] L3_EXP_L3_FLOW_CTRL*/
+#define L3_EXP_L3_FLOW_CTRL
+#define L3_EXP_L3_FLOW_CTRL_ADDRESS 0x9c4
+#define L3_EXP_L3_FLOW_CTRL_NUM     72
+#define L3_EXP_L3_FLOW_CTRL_INC     0x4
+#define L3_EXP_L3_FLOW_CTRL_TYPE    REG_TYPE_RW
+#define L3_EXP_L3_FLOW_CTRL_DEFAULT 0x0
+	/*[field] EXCEP_EN*/
+	#define L3_EXP_L3_FLOW_CTRL_EXCEP_EN
+	#define L3_EXP_L3_FLOW_CTRL_EXCEP_EN_OFFSET  0
+	#define L3_EXP_L3_FLOW_CTRL_EXCEP_EN_LEN     1
+	#define L3_EXP_L3_FLOW_CTRL_EXCEP_EN_DEFAULT 0x0
+
+struct l3_exp_l3_flow_ctrl {
+	a_uint32_t  excep_en:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union l3_exp_l3_flow_ctrl_u {
+	a_uint32_t val;
+	struct l3_exp_l3_flow_ctrl bf;
+};
+
+/*[register] L3_EXP_MULTICAST_CTRL*/
+#define L3_EXP_MULTICAST_CTRL
+#define L3_EXP_MULTICAST_CTRL_ADDRESS 0xae4
+#define L3_EXP_MULTICAST_CTRL_NUM     72
+#define L3_EXP_MULTICAST_CTRL_INC     0x4
+#define L3_EXP_MULTICAST_CTRL_TYPE    REG_TYPE_RW
+#define L3_EXP_MULTICAST_CTRL_DEFAULT 0x0
+	/*[field] EXCEP_EN*/
+	#define L3_EXP_MULTICAST_CTRL_EXCEP_EN
+	#define L3_EXP_MULTICAST_CTRL_EXCEP_EN_OFFSET  0
+	#define L3_EXP_MULTICAST_CTRL_EXCEP_EN_LEN     1
+	#define L3_EXP_MULTICAST_CTRL_EXCEP_EN_DEFAULT 0x0
+
+struct l3_exp_multicast_ctrl {
+	a_uint32_t  excep_en:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union l3_exp_multicast_ctrl_u {
+	a_uint32_t val;
+	struct l3_exp_multicast_ctrl bf;
+};
+
+/*[register] L3_EXCEPTION_PARSING_CTRL_REG*/
+#define L3_EXCEPTION_PARSING_CTRL_REG
+#define L3_EXCEPTION_PARSING_CTRL_REG_ADDRESS 0x24
+#define L3_EXCEPTION_PARSING_CTRL_REG_NUM     1
+#define L3_EXCEPTION_PARSING_CTRL_REG_INC     0x4
+#define L3_EXCEPTION_PARSING_CTRL_REG_TYPE    REG_TYPE_RW
+#define L3_EXCEPTION_PARSING_CTRL_REG_DEFAULT 0x0
+	/*[field] SMALL_TTL*/
+	#define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_TTL
+	#define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_TTL_OFFSET  0
+	#define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_TTL_LEN     8
+	#define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_TTL_DEFAULT 0x0
+	/*[field] SMALL_HOP_LIMIT*/
+	#define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_HOP_LIMIT
+	#define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_HOP_LIMIT_OFFSET  8
+	#define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_HOP_LIMIT_LEN     8
+	#define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_HOP_LIMIT_DEFAULT 0x0
+
+struct l3_exception_parsing_ctrl_reg {
+	a_uint32_t  small_ttl:8;
+	a_uint32_t  small_hop_limit:8;
+	a_uint32_t  _reserved0:16;
+};
+
+union l3_exception_parsing_ctrl_reg_u {
+	a_uint32_t val;
+	struct l3_exception_parsing_ctrl_reg bf;
+};
+
+/*[register] L4_EXCEPTION_PARSING_CTRL_0_REG*/
+#define L4_EXCEPTION_PARSING_CTRL_0_REG
+#define L4_EXCEPTION_PARSING_CTRL_0_REG_ADDRESS 0x28
+#define L4_EXCEPTION_PARSING_CTRL_0_REG_NUM     1
+#define L4_EXCEPTION_PARSING_CTRL_0_REG_INC     0x4
+#define L4_EXCEPTION_PARSING_CTRL_0_REG_TYPE    REG_TYPE_RW
+#define L4_EXCEPTION_PARSING_CTRL_0_REG_DEFAULT 0x0
+	/*[field] TCP_FLAGS0*/
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0_OFFSET  0
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0_DEFAULT 0x0
+	/*[field] TCP_FLAGS0_MASK*/
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0_MASK
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0_MASK_OFFSET  8
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0_MASK_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0_MASK_DEFAULT 0x0
+	/*[field] TCP_FLAGS1*/
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1_OFFSET  16
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1_DEFAULT 0x0
+	/*[field] TCP_FLAGS1_MASK*/
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1_MASK
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1_MASK_OFFSET  24
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1_MASK_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1_MASK_DEFAULT 0x0
+
+struct l4_exception_parsing_ctrl_0_reg {
+	a_uint32_t  tcp_flags0:6;
+	a_uint32_t  _reserved0:2;
+	a_uint32_t  tcp_flags0_mask:6;
+	a_uint32_t  _reserved1:2;
+	a_uint32_t  tcp_flags1:6;
+	a_uint32_t  _reserved2:2;
+	a_uint32_t  tcp_flags1_mask:6;
+	a_uint32_t  _reserved3:2;
+};
+
+union l4_exception_parsing_ctrl_0_reg_u {
+	a_uint32_t val;
+	struct l4_exception_parsing_ctrl_0_reg bf;
+};
+
+/*[register] L4_EXCEPTION_PARSING_CTRL_1_REG*/
+#define L4_EXCEPTION_PARSING_CTRL_1_REG
+#define L4_EXCEPTION_PARSING_CTRL_1_REG_ADDRESS 0x2c
+#define L4_EXCEPTION_PARSING_CTRL_1_REG_NUM     1
+#define L4_EXCEPTION_PARSING_CTRL_1_REG_INC     0x4
+#define L4_EXCEPTION_PARSING_CTRL_1_REG_TYPE    REG_TYPE_RW
+#define L4_EXCEPTION_PARSING_CTRL_1_REG_DEFAULT 0x0
+	/*[field] TCP_FLAGS2*/
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2_OFFSET  0
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2_DEFAULT 0x0
+	/*[field] TCP_FLAGS2_MASK*/
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2_MASK
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2_MASK_OFFSET  8
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2_MASK_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2_MASK_DEFAULT 0x0
+	/*[field] TCP_FLAGS3*/
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3_OFFSET  16
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3_DEFAULT 0x0
+	/*[field] TCP_FLAGS3_MASK*/
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3_MASK
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3_MASK_OFFSET  24
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3_MASK_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3_MASK_DEFAULT 0x0
+
+struct l4_exception_parsing_ctrl_1_reg {
+	a_uint32_t  tcp_flags2:6;
+	a_uint32_t  _reserved0:2;
+	a_uint32_t  tcp_flags2_mask:6;
+	a_uint32_t  _reserved1:2;
+	a_uint32_t  tcp_flags3:6;
+	a_uint32_t  _reserved2:2;
+	a_uint32_t  tcp_flags3_mask:6;
+	a_uint32_t  _reserved3:2;
+};
+
+union l4_exception_parsing_ctrl_1_reg_u {
+	a_uint32_t val;
+	struct l4_exception_parsing_ctrl_1_reg bf;
+};
+
+/*[register] L4_EXCEPTION_PARSING_CTRL_2_REG*/
+#define L4_EXCEPTION_PARSING_CTRL_2_REG
+#define L4_EXCEPTION_PARSING_CTRL_2_REG_ADDRESS 0x30
+#define L4_EXCEPTION_PARSING_CTRL_2_REG_NUM     1
+#define L4_EXCEPTION_PARSING_CTRL_2_REG_INC     0x4
+#define L4_EXCEPTION_PARSING_CTRL_2_REG_TYPE    REG_TYPE_RW
+#define L4_EXCEPTION_PARSING_CTRL_2_REG_DEFAULT 0x0
+	/*[field] TCP_FLAGS4*/
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4_OFFSET  0
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4_DEFAULT 0x0
+	/*[field] TCP_FLAGS4_MASK*/
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4_MASK
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4_MASK_OFFSET  8
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4_MASK_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4_MASK_DEFAULT 0x0
+	/*[field] TCP_FLAGS5*/
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5_OFFSET  16
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5_DEFAULT 0x0
+	/*[field] TCP_FLAGS5_MASK*/
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5_MASK
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5_MASK_OFFSET  24
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5_MASK_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5_MASK_DEFAULT 0x0
+
+struct l4_exception_parsing_ctrl_2_reg {
+	a_uint32_t  tcp_flags4:6;
+	a_uint32_t  _reserved0:2;
+	a_uint32_t  tcp_flags4_mask:6;
+	a_uint32_t  _reserved1:2;
+	a_uint32_t  tcp_flags5:6;
+	a_uint32_t  _reserved2:2;
+	a_uint32_t  tcp_flags5_mask:6;
+	a_uint32_t  _reserved3:2;
+};
+
+union l4_exception_parsing_ctrl_2_reg_u {
+	a_uint32_t val;
+	struct l4_exception_parsing_ctrl_2_reg bf;
+};
+
+/*[register] L4_EXCEPTION_PARSING_CTRL_3_REG*/
+#define L4_EXCEPTION_PARSING_CTRL_3_REG
+#define L4_EXCEPTION_PARSING_CTRL_3_REG_ADDRESS 0x34
+#define L4_EXCEPTION_PARSING_CTRL_3_REG_NUM     1
+#define L4_EXCEPTION_PARSING_CTRL_3_REG_INC     0x4
+#define L4_EXCEPTION_PARSING_CTRL_3_REG_TYPE    REG_TYPE_RW
+#define L4_EXCEPTION_PARSING_CTRL_3_REG_DEFAULT 0x0
+	/*[field] TCP_FLAGS6*/
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6_OFFSET  0
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6_DEFAULT 0x0
+	/*[field] TCP_FLAGS6_MASK*/
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6_MASK
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6_MASK_OFFSET  8
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6_MASK_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6_MASK_DEFAULT 0x0
+	/*[field] TCP_FLAGS7*/
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7_OFFSET  16
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7_DEFAULT 0x0
+	/*[field] TCP_FLAGS7_MASK*/
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7_MASK
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7_MASK_OFFSET  24
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7_MASK_LEN     6
+	#define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7_MASK_DEFAULT 0x0
+
+struct l4_exception_parsing_ctrl_3_reg {
+	a_uint32_t  tcp_flags6:6;
+	a_uint32_t  _reserved0:2;
+	a_uint32_t  tcp_flags6_mask:6;
+	a_uint32_t  _reserved1:2;
+	a_uint32_t  tcp_flags7:6;
+	a_uint32_t  _reserved2:2;
+	a_uint32_t  tcp_flags7_mask:6;
+	a_uint32_t  _reserved3:2;
+};
+
+union l4_exception_parsing_ctrl_3_reg_u {
+	a_uint32_t val;
+	struct l4_exception_parsing_ctrl_3_reg bf;
+};
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_servcode.h b/qca-ssdk/include/hsl/hppe/hppe_servcode.h
new file mode 100755
index 0000000..bbeda36
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_servcode.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_SERVCODE_H_
+#define _HPPE_SERVCODE_H_
+
+#define IN_L2_SERVICE_TBL_MAX_ENTRY	256
+#define EG_SERVICE_TBL_MAX_ENTRY	256
+
+sw_error_t
+hppe_service_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union service_tbl_u *value);
+
+sw_error_t
+hppe_service_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union service_tbl_u *value);
+
+sw_error_t
+hppe_service_tbl_rx_counting_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_service_tbl_rx_counting_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_service_tbl_bypass_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_service_tbl_bypass_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l2_service_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_l2_service_tbl_u *value);
+
+sw_error_t
+hppe_in_l2_service_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_l2_service_tbl_u *value);
+
+sw_error_t
+hppe_in_l2_service_tbl_direction_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l2_service_tbl_direction_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l2_service_tbl_rx_cnt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l2_service_tbl_rx_cnt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l2_service_tbl_tx_cnt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l2_service_tbl_tx_cnt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l2_service_tbl_bypass_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l2_service_tbl_bypass_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l2_service_tbl_dst_port_id_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l2_service_tbl_dst_port_id_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_in_l2_service_tbl_dst_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_in_l2_service_tbl_dst_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+		sw_error_t
+hppe_eg_service_tbl_next_service_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_service_tbl_next_service_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_service_tbl_tx_counting_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_service_tbl_tx_counting_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_service_tbl_field_update_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_service_tbl_field_update_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_service_tbl_offset_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_service_tbl_offset_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_service_tbl_hw_services_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_service_tbl_hw_services_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_service_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_service_tbl_u *value);
+
+sw_error_t
+hppe_eg_service_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_service_tbl_u *value);
+
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_servcode_reg.h b/qca-ssdk/include/hsl/hppe/hppe_servcode_reg.h
new file mode 100755
index 0000000..82f794b
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_servcode_reg.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_SERVCODE_REG_H
+#define HPPE_SERVCODE_REG_H
+
+/*[table] SERVICE_TBL*/
+#define SERVICE_TBL
+#define SERVICE_TBL_ADDRESS 0x6000
+#define SERVICE_TBL_NUM     256
+#define SERVICE_TBL_INC     0x10
+#define SERVICE_TBL_TYPE    REG_TYPE_RW
+#define SERVICE_TBL_DEFAULT 0x0
+	/*[field] BYPASS_BITMAP*/
+	#define SERVICE_TBL_BYPASS_BITMAP
+	#define SERVICE_TBL_BYPASS_BITMAP_OFFSET  0
+	#define SERVICE_TBL_BYPASS_BITMAP_LEN     32
+	#define SERVICE_TBL_BYPASS_BITMAP_DEFAULT 0x0
+	/*[field] RX_COUNTING_EN*/
+	#define SERVICE_TBL_RX_COUNTING_EN
+	#define SERVICE_TBL_RX_COUNTING_EN_OFFSET  32
+	#define SERVICE_TBL_RX_COUNTING_EN_LEN     1
+	#define SERVICE_TBL_RX_COUNTING_EN_DEFAULT 0x0
+
+struct service_tbl {
+	a_uint32_t  bypass_bitmap:32;
+	a_uint32_t  rx_counting_en:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union service_tbl_u {
+	a_uint32_t val[2];
+	struct service_tbl bf;
+};
+
+/*[table] IN_L2_SERVICE_TBL*/
+#define IN_L2_SERVICE_TBL
+#define IN_L2_SERVICE_TBL_ADDRESS 0x4000
+#define IN_L2_SERVICE_TBL_NUM     256
+#define IN_L2_SERVICE_TBL_INC     0x10
+#define IN_L2_SERVICE_TBL_TYPE    REG_TYPE_RW
+#define IN_L2_SERVICE_TBL_DEFAULT 0x0
+	/*[field] DST_PORT_ID_VALID*/
+	#define IN_L2_SERVICE_TBL_DST_PORT_ID_VALID
+	#define IN_L2_SERVICE_TBL_DST_PORT_ID_VALID_OFFSET  0
+	#define IN_L2_SERVICE_TBL_DST_PORT_ID_VALID_LEN     1
+	#define IN_L2_SERVICE_TBL_DST_PORT_ID_VALID_DEFAULT 0x0
+	/*[field] DST_PORT_ID*/
+	#define IN_L2_SERVICE_TBL_DST_PORT_ID
+	#define IN_L2_SERVICE_TBL_DST_PORT_ID_OFFSET  1
+	#define IN_L2_SERVICE_TBL_DST_PORT_ID_LEN     4
+	#define IN_L2_SERVICE_TBL_DST_PORT_ID_DEFAULT 0x0
+	/*[field] DIRECTION*/
+	#define IN_L2_SERVICE_TBL_DIRECTION
+	#define IN_L2_SERVICE_TBL_DIRECTION_OFFSET  5
+	#define IN_L2_SERVICE_TBL_DIRECTION_LEN     1
+	#define IN_L2_SERVICE_TBL_DIRECTION_DEFAULT 0x0
+	/*[field] BYPASS_BITMAP*/
+	#define IN_L2_SERVICE_TBL_BYPASS_BITMAP
+	#define IN_L2_SERVICE_TBL_BYPASS_BITMAP_OFFSET  6
+	#define IN_L2_SERVICE_TBL_BYPASS_BITMAP_LEN     24
+	#define IN_L2_SERVICE_TBL_BYPASS_BITMAP_DEFAULT 0x0
+	/*[field] RX_CNT_EN*/
+	#define IN_L2_SERVICE_TBL_RX_CNT_EN
+	#define IN_L2_SERVICE_TBL_RX_CNT_EN_OFFSET  30
+	#define IN_L2_SERVICE_TBL_RX_CNT_EN_LEN     1
+	#define IN_L2_SERVICE_TBL_RX_CNT_EN_DEFAULT 0x0
+	/*[field] TX_CNT_EN*/
+	#define IN_L2_SERVICE_TBL_TX_CNT_EN
+	#define IN_L2_SERVICE_TBL_TX_CNT_EN_OFFSET  31
+	#define IN_L2_SERVICE_TBL_TX_CNT_EN_LEN     1
+	#define IN_L2_SERVICE_TBL_TX_CNT_EN_DEFAULT 0x0
+
+struct in_l2_service_tbl {
+	a_uint32_t  dst_port_id_valid:1;
+	a_uint32_t  dst_port_id:4;
+	a_uint32_t  direction:1;
+	a_uint32_t  bypass_bitmap:24;
+	a_uint32_t  rx_cnt_en:1;
+	a_uint32_t  tx_cnt_en:1;
+};
+
+union in_l2_service_tbl_u {
+	a_uint32_t val;
+	struct in_l2_service_tbl bf;
+};
+
+/*[table] EG_SERVICE_TBL*/
+#define EG_SERVICE_TBL
+#define EG_SERVICE_TBL_ADDRESS 0xc000
+#define EG_SERVICE_TBL_NUM     256
+#define EG_SERVICE_TBL_INC     0x8
+#define EG_SERVICE_TBL_TYPE    REG_TYPE_RW
+#define EG_SERVICE_TBL_DEFAULT 0x0
+	/*[field] FIELD_UPDATE_ACTION*/
+	#define EG_SERVICE_TBL_FIELD_UPDATE_ACTION
+	#define EG_SERVICE_TBL_FIELD_UPDATE_ACTION_OFFSET  0
+	#define EG_SERVICE_TBL_FIELD_UPDATE_ACTION_LEN     32
+	#define EG_SERVICE_TBL_FIELD_UPDATE_ACTION_DEFAULT 0x0
+	/*[field] NEXT_SERVICE_CODE*/
+	#define EG_SERVICE_TBL_NEXT_SERVICE_CODE
+	#define EG_SERVICE_TBL_NEXT_SERVICE_CODE_OFFSET  32
+	#define EG_SERVICE_TBL_NEXT_SERVICE_CODE_LEN     8
+	#define EG_SERVICE_TBL_NEXT_SERVICE_CODE_DEFAULT 0x0
+	/*[field] HW_SERVICES*/
+	#define EG_SERVICE_TBL_HW_SERVICES
+	#define EG_SERVICE_TBL_HW_SERVICES_OFFSET  40
+	#define EG_SERVICE_TBL_HW_SERVICES_LEN     6
+	#define EG_SERVICE_TBL_HW_SERVICES_DEFAULT 0x0
+	/*[field] OFFSET_SEL*/
+	#define EG_SERVICE_TBL_OFFSET_SEL
+	#define EG_SERVICE_TBL_OFFSET_SEL_OFFSET  46
+	#define EG_SERVICE_TBL_OFFSET_SEL_LEN     1
+	#define EG_SERVICE_TBL_OFFSET_SEL_DEFAULT 0x0
+	/*[field] TX_COUNTING_EN*/
+	#define EG_SERVICE_TBL_TX_COUNTING_EN
+	#define EG_SERVICE_TBL_TX_COUNTING_EN_OFFSET  47
+	#define EG_SERVICE_TBL_TX_COUNTING_EN_LEN     1
+	#define EG_SERVICE_TBL_TX_COUNTING_EN_DEFAULT 0x0
+
+struct eg_service_tbl {
+	a_uint32_t  field_update_action:32;
+	a_uint32_t  next_service_code:8;
+	a_uint32_t  hw_services:6;
+	a_uint32_t  offset_sel:1;
+	a_uint32_t  tx_counting_en:1;
+	a_uint32_t  _reserved0:16;
+};
+
+union eg_service_tbl_u {
+	a_uint32_t val[2];
+	struct eg_service_tbl bf;
+};
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_shaper.h b/qca-ssdk/include/hsl/hppe/hppe_shaper.h
new file mode 100755
index 0000000..4f8c74f
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_shaper.h
@@ -0,0 +1,1055 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_SHAPER_H_
+#define _HPPE_SHAPER_H_
+
+#define L0_SHP_CREDIT_TBL_MAX_ENTRY	300
+#define L0_SHP_CFG_TBL_MAX_ENTRY	300
+#define L0_COMP_TBL_MAX_ENTRY	300
+#define L0_COMP_CFG_TBL_MAX_ENTRY	300
+#define L1_SHP_CREDIT_TBL_MAX_ENTRY	64
+#define L1_SHP_CFG_TBL_MAX_ENTRY	64
+#define L1_COMP_TBL_MAX_ENTRY	64
+#define L1_COMP_CFG_TBL_MAX_ENTRY	64
+#define PSCH_SHP_SIGN_TBL_MAX_ENTRY	8
+#define PSCH_SHP_CREDIT_TBL_MAX_ENTRY	8
+#define PSCH_SHP_CFG_TBL_MAX_ENTRY	8
+#define PSCH_COMP_TBL_MAX_ENTRY	8
+#define PSCH_COMP_CFG_TBL_MAX_ENTRY	8
+
+sw_error_t
+hppe_shp_slot_cfg_l0_get(
+		a_uint32_t dev_id,
+		union shp_slot_cfg_l0_u *value);
+
+sw_error_t
+hppe_shp_slot_cfg_l0_set(
+		a_uint32_t dev_id,
+		union shp_slot_cfg_l0_u *value);
+
+sw_error_t
+hppe_shp_slot_cfg_l1_get(
+		a_uint32_t dev_id,
+		union shp_slot_cfg_l1_u *value);
+
+sw_error_t
+hppe_shp_slot_cfg_l1_set(
+		a_uint32_t dev_id,
+		union shp_slot_cfg_l1_u *value);
+
+sw_error_t
+hppe_shp_slot_cfg_port_get(
+		a_uint32_t dev_id,
+		union shp_slot_cfg_port_u *value);
+
+sw_error_t
+hppe_shp_slot_cfg_port_set(
+		a_uint32_t dev_id,
+		union shp_slot_cfg_port_u *value);
+
+sw_error_t
+hppe_l0_shp_credit_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_shp_credit_tbl_u *value);
+
+sw_error_t
+hppe_l0_shp_credit_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_shp_credit_tbl_u *value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_shp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_shp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_l0_comp_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_comp_tbl_u *value);
+
+sw_error_t
+hppe_l0_comp_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_comp_tbl_u *value);
+
+sw_error_t
+hppe_l0_comp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_comp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_l0_comp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_comp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_l1_shp_credit_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_shp_credit_tbl_u *value);
+
+sw_error_t
+hppe_l1_shp_credit_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_shp_credit_tbl_u *value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_shp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_shp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_l1_comp_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_comp_tbl_u *value);
+
+sw_error_t
+hppe_l1_comp_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_comp_tbl_u *value);
+
+sw_error_t
+hppe_l1_comp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_comp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_l1_comp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_comp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_psch_shp_sign_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_shp_sign_tbl_u *value);
+
+sw_error_t
+hppe_psch_shp_sign_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_shp_sign_tbl_u *value);
+
+sw_error_t
+hppe_psch_shp_credit_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_shp_credit_tbl_u *value);
+
+sw_error_t
+hppe_psch_shp_credit_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_shp_credit_tbl_u *value);
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_shp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_shp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_psch_comp_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_comp_tbl_u *value);
+
+sw_error_t
+hppe_psch_comp_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_comp_tbl_u *value);
+
+sw_error_t
+hppe_psch_comp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_comp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_psch_comp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_comp_cfg_tbl_u *value);
+
+sw_error_t
+hppe_ipg_pre_len_cfg_get(
+		a_uint32_t dev_id,
+		union ipg_pre_len_cfg_u *value);
+
+sw_error_t
+hppe_ipg_pre_len_cfg_set(
+		a_uint32_t dev_id,
+		union ipg_pre_len_cfg_u *value);
+
+sw_error_t
+hppe_ipg_pre_len_cfg_ipg_pre_len_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_ipg_pre_len_cfg_ipg_pre_len_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_shp_slot_cfg_l0_l0_shp_slot_time_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_shp_slot_cfg_l0_l0_shp_slot_time_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_shp_slot_cfg_l1_l1_shp_slot_time_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_shp_slot_cfg_l1_l1_shp_slot_time_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_shp_slot_cfg_port_port_shp_slot_time_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_shp_slot_cfg_port_port_shp_slot_time_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_l0_shp_credit_tbl_e_shaper_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_shp_credit_tbl_e_shaper_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_shp_credit_tbl_e_shaper_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_shp_credit_tbl_e_shaper_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_shp_credit_tbl_c_shaper_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_shp_credit_tbl_c_shaper_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_shp_credit_tbl_c_shaper_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_shp_credit_tbl_c_shaper_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_cir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_cir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_cf_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_cf_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_meter_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_meter_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_e_shaper_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_e_shaper_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_c_shaper_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_c_shaper_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_eir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_eir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_token_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_token_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_cbs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_cbs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_ebs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_ebs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_comp_tbl_c_drr_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_comp_tbl_c_drr_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_comp_tbl_e_drr_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_comp_tbl_e_drr_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_comp_tbl_c_shaper_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_comp_tbl_c_shaper_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_comp_tbl_c_shaper_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_comp_tbl_c_shaper_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_comp_tbl_c_shaper_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_comp_tbl_c_shaper_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_comp_tbl_e_shaper_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_comp_tbl_e_shaper_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_comp_tbl_e_drr_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_comp_tbl_e_drr_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_comp_tbl_e_drr_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_comp_tbl_e_drr_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_comp_tbl_c_drr_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_comp_tbl_c_drr_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_comp_tbl_c_drr_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_comp_tbl_c_drr_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_comp_tbl_e_shaper_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_comp_tbl_e_shaper_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_comp_tbl_e_shaper_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_comp_tbl_e_shaper_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_comp_cfg_tbl_drr_meter_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_comp_cfg_tbl_drr_meter_len_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l0_comp_cfg_tbl_shaper_meter_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l0_comp_cfg_tbl_shaper_meter_len_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_shp_credit_tbl_e_shaper_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_shp_credit_tbl_e_shaper_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_shp_credit_tbl_e_shaper_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_shp_credit_tbl_e_shaper_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_shp_credit_tbl_c_shaper_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_shp_credit_tbl_c_shaper_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_shp_credit_tbl_c_shaper_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_shp_credit_tbl_c_shaper_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_cir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_cir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_cf_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_cf_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_meter_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_meter_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_e_shaper_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_e_shaper_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_c_shaper_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_c_shaper_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_eir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_eir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_token_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_token_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_cbs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_cbs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_ebs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_ebs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_comp_tbl_c_drr_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_comp_tbl_c_drr_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_comp_tbl_e_drr_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_comp_tbl_e_drr_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_comp_tbl_c_shaper_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_comp_tbl_c_shaper_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_comp_tbl_c_shaper_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_comp_tbl_c_shaper_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_comp_tbl_c_shaper_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_comp_tbl_c_shaper_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_comp_tbl_e_shaper_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_comp_tbl_e_shaper_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_comp_tbl_e_drr_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_comp_tbl_e_drr_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_comp_tbl_e_drr_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_comp_tbl_e_drr_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_comp_tbl_c_drr_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_comp_tbl_c_drr_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_comp_tbl_c_drr_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_comp_tbl_c_drr_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_comp_tbl_e_shaper_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_comp_tbl_e_shaper_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_comp_tbl_e_shaper_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_comp_tbl_e_shaper_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_comp_cfg_tbl_drr_meter_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_comp_cfg_tbl_drr_meter_len_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_l1_comp_cfg_tbl_shaper_meter_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_l1_comp_cfg_tbl_shaper_meter_len_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+
+sw_error_t
+hppe_psch_shp_sign_tbl_shaper_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_psch_shp_sign_tbl_shaper_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_psch_shp_credit_tbl_shaper_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_psch_shp_credit_tbl_shaper_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_cir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_cir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_meter_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_meter_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_token_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_token_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_cbs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_cbs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_shaper_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_shaper_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_psch_comp_tbl_shaper_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_psch_comp_tbl_shaper_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_psch_comp_tbl_shaper_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_psch_comp_tbl_shaper_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_psch_comp_tbl_shaper_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_psch_comp_tbl_shaper_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_psch_comp_cfg_tbl_shaper_meter_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_psch_comp_cfg_tbl_shaper_meter_len_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_shaper_reg.h b/qca-ssdk/include/hsl/hppe/hppe_shaper_reg.h
new file mode 100755
index 0000000..fe7b0af
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_shaper_reg.h
@@ -0,0 +1,730 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_SHAPER_REG_H
+#define HPPE_SHAPER_REG_H
+
+/*[register] SHP_SLOT_CFG_L0*/
+#define SHP_SLOT_CFG_L0
+#define SHP_SLOT_CFG_L0_ADDRESS 0x10
+#define SHP_SLOT_CFG_L0_NUM     1
+#define SHP_SLOT_CFG_L0_INC     0x4
+#define SHP_SLOT_CFG_L0_TYPE    REG_TYPE_RW
+#define SHP_SLOT_CFG_L0_DEFAULT 0x12c
+	/*[field] L0_SHP_SLOT_TIME*/
+	#define SHP_SLOT_CFG_L0_L0_SHP_SLOT_TIME
+	#define SHP_SLOT_CFG_L0_L0_SHP_SLOT_TIME_OFFSET  0
+	#define SHP_SLOT_CFG_L0_L0_SHP_SLOT_TIME_LEN     12
+	#define SHP_SLOT_CFG_L0_L0_SHP_SLOT_TIME_DEFAULT 0x12c
+
+struct shp_slot_cfg_l0 {
+	a_uint32_t  l0_shp_slot_time:12;
+	a_uint32_t  _reserved0:20;
+};
+
+union shp_slot_cfg_l0_u {
+	a_uint32_t val;
+	struct shp_slot_cfg_l0 bf;
+};
+
+/*[register] SHP_SLOT_CFG_L1*/
+#define SHP_SLOT_CFG_L1
+#define SHP_SLOT_CFG_L1_ADDRESS 0x14
+#define SHP_SLOT_CFG_L1_NUM     1
+#define SHP_SLOT_CFG_L1_INC     0x4
+#define SHP_SLOT_CFG_L1_TYPE    REG_TYPE_RW
+#define SHP_SLOT_CFG_L1_DEFAULT 0x40
+	/*[field] L1_SHP_SLOT_TIME*/
+	#define SHP_SLOT_CFG_L1_L1_SHP_SLOT_TIME
+	#define SHP_SLOT_CFG_L1_L1_SHP_SLOT_TIME_OFFSET  0
+	#define SHP_SLOT_CFG_L1_L1_SHP_SLOT_TIME_LEN     12
+	#define SHP_SLOT_CFG_L1_L1_SHP_SLOT_TIME_DEFAULT 0x40
+
+struct shp_slot_cfg_l1 {
+	a_uint32_t  l1_shp_slot_time:12;
+	a_uint32_t  _reserved0:20;
+};
+
+union shp_slot_cfg_l1_u {
+	a_uint32_t val;
+	struct shp_slot_cfg_l1 bf;
+};
+
+/*[register] SHP_SLOT_CFG_PORT*/
+#define SHP_SLOT_CFG_PORT
+#define SHP_SLOT_CFG_PORT_ADDRESS 0x18
+#define SHP_SLOT_CFG_PORT_NUM     1
+#define SHP_SLOT_CFG_PORT_INC     0x4
+#define SHP_SLOT_CFG_PORT_TYPE    REG_TYPE_RW
+#define SHP_SLOT_CFG_PORT_DEFAULT 0x8
+	/*[field] PORT_SHP_SLOT_TIME*/
+	#define SHP_SLOT_CFG_PORT_PORT_SHP_SLOT_TIME
+	#define SHP_SLOT_CFG_PORT_PORT_SHP_SLOT_TIME_OFFSET  0
+	#define SHP_SLOT_CFG_PORT_PORT_SHP_SLOT_TIME_LEN     12
+	#define SHP_SLOT_CFG_PORT_PORT_SHP_SLOT_TIME_DEFAULT 0x8
+
+struct shp_slot_cfg_port {
+	a_uint32_t  port_shp_slot_time:12;
+	a_uint32_t  _reserved0:20;
+};
+
+union shp_slot_cfg_port_u {
+	a_uint32_t val;
+	struct shp_slot_cfg_port bf;
+};
+
+/*[table] L0_SHP_CREDIT_TBL*/
+#define L0_SHP_CREDIT_TBL
+#define L0_SHP_CREDIT_TBL_ADDRESS 0x1a000
+#define L0_SHP_CREDIT_TBL_NUM     300
+#define L0_SHP_CREDIT_TBL_INC     0x10
+#define L0_SHP_CREDIT_TBL_TYPE    REG_TYPE_RW
+#define L0_SHP_CREDIT_TBL_DEFAULT 0x0
+	/*[field] C_SHAPER_CREDIT*/
+	#define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT
+	#define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT_OFFSET  0
+	#define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT_LEN     30
+	#define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT_DEFAULT 0x0
+	/*[field] C_SHAPER_CREDIT_NEG*/
+	#define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG
+	#define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG_OFFSET  30
+	#define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG_LEN     1
+	#define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG_DEFAULT 0x0
+	/*[field] E_SHAPER_CREDIT*/
+	#define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT
+	#define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT_OFFSET  31
+	#define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT_LEN     30
+	#define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT_DEFAULT 0x0
+	/*[field] E_SHAPER_CREDIT_NEG*/
+	#define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG
+	#define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG_OFFSET  61
+	#define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG_LEN     1
+	#define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG_DEFAULT 0x0
+
+struct l0_shp_credit_tbl {
+	a_uint32_t  c_shaper_credit:30;
+	a_uint32_t  c_shaper_credit_neg:1;
+	a_uint32_t  e_shaper_credit_0:1;
+	a_uint32_t  e_shaper_credit_1:29;
+	a_uint32_t  e_shaper_credit_neg:1;
+	a_uint32_t  _reserved0:2;
+};
+
+union l0_shp_credit_tbl_u {
+	a_uint32_t val[2];
+	struct l0_shp_credit_tbl bf;
+};
+
+/*[table] L0_SHP_CFG_TBL*/
+#define L0_SHP_CFG_TBL
+#define L0_SHP_CFG_TBL_ADDRESS 0x1c000
+#define L0_SHP_CFG_TBL_NUM     300
+#define L0_SHP_CFG_TBL_INC     0x10
+#define L0_SHP_CFG_TBL_TYPE    REG_TYPE_RW
+#define L0_SHP_CFG_TBL_DEFAULT 0x0
+	/*[field] CIR*/
+	#define L0_SHP_CFG_TBL_CIR
+	#define L0_SHP_CFG_TBL_CIR_OFFSET  0
+	#define L0_SHP_CFG_TBL_CIR_LEN     18
+	#define L0_SHP_CFG_TBL_CIR_DEFAULT 0x0
+	/*[field] CBS*/
+	#define L0_SHP_CFG_TBL_CBS
+	#define L0_SHP_CFG_TBL_CBS_OFFSET  18
+	#define L0_SHP_CFG_TBL_CBS_LEN     14
+	#define L0_SHP_CFG_TBL_CBS_DEFAULT 0x0
+	/*[field] EIR*/
+	#define L0_SHP_CFG_TBL_EIR
+	#define L0_SHP_CFG_TBL_EIR_OFFSET  32
+	#define L0_SHP_CFG_TBL_EIR_LEN     18
+	#define L0_SHP_CFG_TBL_EIR_DEFAULT 0x0
+	/*[field] EBS*/
+	#define L0_SHP_CFG_TBL_EBS
+	#define L0_SHP_CFG_TBL_EBS_OFFSET  50
+	#define L0_SHP_CFG_TBL_EBS_LEN     14
+	#define L0_SHP_CFG_TBL_EBS_DEFAULT 0x0
+	/*[field] TOKEN_UNIT*/
+	#define L0_SHP_CFG_TBL_TOKEN_UNIT
+	#define L0_SHP_CFG_TBL_TOKEN_UNIT_OFFSET  64
+	#define L0_SHP_CFG_TBL_TOKEN_UNIT_LEN     3
+	#define L0_SHP_CFG_TBL_TOKEN_UNIT_DEFAULT 0x0
+	/*[field] METER_UNIT*/
+	#define L0_SHP_CFG_TBL_METER_UNIT
+	#define L0_SHP_CFG_TBL_METER_UNIT_OFFSET  67
+	#define L0_SHP_CFG_TBL_METER_UNIT_LEN     1
+	#define L0_SHP_CFG_TBL_METER_UNIT_DEFAULT 0x0
+	/*[field] C_SHAPER_ENABLE*/
+	#define L0_SHP_CFG_TBL_C_SHAPER_ENABLE
+	#define L0_SHP_CFG_TBL_C_SHAPER_ENABLE_OFFSET  68
+	#define L0_SHP_CFG_TBL_C_SHAPER_ENABLE_LEN     1
+	#define L0_SHP_CFG_TBL_C_SHAPER_ENABLE_DEFAULT 0x0
+	/*[field] E_SHAPER_ENABLE*/
+	#define L0_SHP_CFG_TBL_E_SHAPER_ENABLE
+	#define L0_SHP_CFG_TBL_E_SHAPER_ENABLE_OFFSET  69
+	#define L0_SHP_CFG_TBL_E_SHAPER_ENABLE_LEN     1
+	#define L0_SHP_CFG_TBL_E_SHAPER_ENABLE_DEFAULT 0x0
+	/*[field] CF*/
+	#define L0_SHP_CFG_TBL_CF
+	#define L0_SHP_CFG_TBL_CF_OFFSET  70
+	#define L0_SHP_CFG_TBL_CF_LEN     1
+	#define L0_SHP_CFG_TBL_CF_DEFAULT 0x0
+
+struct l0_shp_cfg_tbl {
+	a_uint32_t  cir:18;
+	a_uint32_t  cbs:14;
+	a_uint32_t  eir:18;
+	a_uint32_t  ebs:14;
+	a_uint32_t  token_unit:3;
+	a_uint32_t  meter_unit:1;
+	a_uint32_t  c_shaper_enable:1;
+	a_uint32_t  e_shaper_enable:1;
+	a_uint32_t  cf:1;
+	a_uint32_t  _reserved0:25;
+};
+
+union l0_shp_cfg_tbl_u {
+	a_uint32_t val[3];
+	struct l0_shp_cfg_tbl bf;
+};
+
+/*[table] L0_COMP_TBL*/
+#define L0_COMP_TBL
+#define L0_COMP_TBL_ADDRESS 0x26000
+#define L0_COMP_TBL_NUM     300
+#define L0_COMP_TBL_INC     0x10
+#define L0_COMP_TBL_TYPE    REG_TYPE_RO
+#define L0_COMP_TBL_DEFAULT 0x0
+	/*[field] C_SHAPER_COMPENSATE_BYTE_CNT*/
+	#define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT
+	#define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT_OFFSET  0
+	#define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT_LEN     18
+	#define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT_DEFAULT 0x0
+	/*[field] C_SHAPER_COMPENSATE_BYTE_NEG*/
+	#define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG
+	#define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG_OFFSET  18
+	#define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG_LEN     1
+	#define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG_DEFAULT 0x0
+	/*[field] C_SHAPER_COMPENSATE_PKT_CNT*/
+	#define L0_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT
+	#define L0_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT_OFFSET  19
+	#define L0_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT_LEN     4
+	#define L0_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT_DEFAULT 0x0
+	/*[field] C_DRR_COMPENSATE_BYTE_CNT*/
+	#define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT
+	#define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT_OFFSET  23
+	#define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT_LEN     18
+	#define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT_DEFAULT 0x0
+	/*[field] C_DRR_COMPENSATE_BYTE_NEG*/
+	#define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG
+	#define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG_OFFSET  41
+	#define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG_LEN     1
+	#define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG_DEFAULT 0x0
+	/*[field] C_DRR_COMPENSATE_PKT_CNT*/
+	#define L0_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT
+	#define L0_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT_OFFSET  42
+	#define L0_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT_LEN     4
+	#define L0_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT_DEFAULT 0x0
+	/*[field] E_SHAPER_COMPENSATE_BYTE_CNT*/
+	#define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT
+	#define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT_OFFSET  46
+	#define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT_LEN     18
+	#define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT_DEFAULT 0x0
+	/*[field] E_SHAPER_COMPENSATE_BYTE_NEG*/
+	#define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG
+	#define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG_OFFSET  64
+	#define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG_LEN     1
+	#define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG_DEFAULT 0x0
+	/*[field] E_SHAPER_COMPENSATE_PKT_CNT*/
+	#define L0_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT
+	#define L0_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT_OFFSET  65
+	#define L0_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT_LEN     4
+	#define L0_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT_DEFAULT 0x0
+	/*[field] E_DRR_COMPENSATE_BYTE_CNT*/
+	#define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT
+	#define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT_OFFSET  69
+	#define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT_LEN     18
+	#define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT_DEFAULT 0x0
+	/*[field] E_DRR_COMPENSATE_BYTE_NEG*/
+	#define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG
+	#define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG_OFFSET  87
+	#define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG_LEN     1
+	#define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG_DEFAULT 0x0
+	/*[field] E_DRR_COMPENSATE_PKT_CNT*/
+	#define L0_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT
+	#define L0_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT_OFFSET  88
+	#define L0_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT_LEN     4
+	#define L0_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT_DEFAULT 0x0
+
+struct l0_comp_tbl {
+	a_uint32_t  c_shaper_compensate_byte_cnt:18;
+	a_uint32_t  c_shaper_compensate_byte_neg:1;
+	a_uint32_t  c_shaper_compensate_pkt_cnt:4;
+	a_uint32_t  c_drr_compensate_byte_cnt_0:9;
+	a_uint32_t  c_drr_compensate_byte_cnt_1:9;
+	a_uint32_t  c_drr_compensate_byte_neg:1;
+	a_uint32_t  c_drr_compensate_pkt_cnt:4;
+	a_uint32_t  e_shaper_compensate_byte_cnt:18;
+	a_uint32_t  e_shaper_compensate_byte_neg:1;
+	a_uint32_t  e_shaper_compensate_pkt_cnt:4;
+	a_uint32_t  e_drr_compensate_byte_cnt:18;
+	a_uint32_t  e_drr_compensate_byte_neg:1;
+	a_uint32_t  e_drr_compensate_pkt_cnt:4;
+	a_uint32_t  _reserved0:4;
+};
+
+union l0_comp_tbl_u {
+	a_uint32_t val[3];
+	struct l0_comp_tbl bf;
+};
+
+/*[table] L0_COMP_CFG_TBL*/
+#define L0_COMP_CFG_TBL
+#define L0_COMP_CFG_TBL_ADDRESS 0x28000
+#define L0_COMP_CFG_TBL_NUM     300
+#define L0_COMP_CFG_TBL_INC     0x10
+#define L0_COMP_CFG_TBL_TYPE    REG_TYPE_RW
+#define L0_COMP_CFG_TBL_DEFAULT 0x0
+	/*[field] SHAPER_METER_LEN*/
+	#define L0_COMP_CFG_TBL_SHAPER_METER_LEN
+	#define L0_COMP_CFG_TBL_SHAPER_METER_LEN_OFFSET  0
+	#define L0_COMP_CFG_TBL_SHAPER_METER_LEN_LEN     2
+	#define L0_COMP_CFG_TBL_SHAPER_METER_LEN_DEFAULT 0x0
+	/*[field] DRR_METER_LEN*/
+	#define L0_COMP_CFG_TBL_DRR_METER_LEN
+	#define L0_COMP_CFG_TBL_DRR_METER_LEN_OFFSET  2
+	#define L0_COMP_CFG_TBL_DRR_METER_LEN_LEN     2
+	#define L0_COMP_CFG_TBL_DRR_METER_LEN_DEFAULT 0x0
+
+struct l0_comp_cfg_tbl {
+	a_uint32_t  shaper_meter_len:2;
+	a_uint32_t  drr_meter_len:2;
+	a_uint32_t  _reserved0:28;
+};
+
+union l0_comp_cfg_tbl_u {
+	a_uint32_t val;
+	struct l0_comp_cfg_tbl bf;
+};
+
+/*[table] L1_SHP_CREDIT_TBL*/
+#define L1_SHP_CREDIT_TBL
+#define L1_SHP_CREDIT_TBL_ADDRESS 0x5c000
+#define L1_SHP_CREDIT_TBL_NUM     64
+#define L1_SHP_CREDIT_TBL_INC     0x10
+#define L1_SHP_CREDIT_TBL_TYPE    REG_TYPE_RW
+#define L1_SHP_CREDIT_TBL_DEFAULT 0x0
+	/*[field] C_SHAPER_CREDIT*/
+	#define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT
+	#define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT_OFFSET  0
+	#define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT_LEN     30
+	#define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT_DEFAULT 0x0
+	/*[field] C_SHAPER_CREDIT_NEG*/
+	#define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG
+	#define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG_OFFSET  30
+	#define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG_LEN     1
+	#define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG_DEFAULT 0x0
+	/*[field] E_SHAPER_CREDIT*/
+	#define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT
+	#define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT_OFFSET  31
+	#define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT_LEN     30
+	#define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT_DEFAULT 0x0
+	/*[field] E_SHAPER_CREDIT_NEG*/
+	#define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG
+	#define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG_OFFSET  61
+	#define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG_LEN     1
+	#define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG_DEFAULT 0x0
+
+struct l1_shp_credit_tbl {
+	a_uint32_t  c_shaper_credit:30;
+	a_uint32_t  c_shaper_credit_neg:1;
+	a_uint32_t  e_shaper_credit_0:1;
+	a_uint32_t  e_shaper_credit_1:29;
+	a_uint32_t  e_shaper_credit_neg:1;
+	a_uint32_t  _reserved0:2;
+};
+
+union l1_shp_credit_tbl_u {
+	a_uint32_t val[2];
+	struct l1_shp_credit_tbl bf;
+};
+
+/*[table] L1_SHP_CFG_TBL*/
+#define L1_SHP_CFG_TBL
+#define L1_SHP_CFG_TBL_ADDRESS 0x5e000
+#define L1_SHP_CFG_TBL_NUM     64
+#define L1_SHP_CFG_TBL_INC     0x10
+#define L1_SHP_CFG_TBL_TYPE    REG_TYPE_RW
+#define L1_SHP_CFG_TBL_DEFAULT 0x0
+	/*[field] CIR*/
+	#define L1_SHP_CFG_TBL_CIR
+	#define L1_SHP_CFG_TBL_CIR_OFFSET  0
+	#define L1_SHP_CFG_TBL_CIR_LEN     18
+	#define L1_SHP_CFG_TBL_CIR_DEFAULT 0x0
+	/*[field] CBS*/
+	#define L1_SHP_CFG_TBL_CBS
+	#define L1_SHP_CFG_TBL_CBS_OFFSET  18
+	#define L1_SHP_CFG_TBL_CBS_LEN     14
+	#define L1_SHP_CFG_TBL_CBS_DEFAULT 0x0
+	/*[field] EIR*/
+	#define L1_SHP_CFG_TBL_EIR
+	#define L1_SHP_CFG_TBL_EIR_OFFSET  32
+	#define L1_SHP_CFG_TBL_EIR_LEN     18
+	#define L1_SHP_CFG_TBL_EIR_DEFAULT 0x0
+	/*[field] EBS*/
+	#define L1_SHP_CFG_TBL_EBS
+	#define L1_SHP_CFG_TBL_EBS_OFFSET  50
+	#define L1_SHP_CFG_TBL_EBS_LEN     14
+	#define L1_SHP_CFG_TBL_EBS_DEFAULT 0x0
+	/*[field] TOKEN_UNIT*/
+	#define L1_SHP_CFG_TBL_TOKEN_UNIT
+	#define L1_SHP_CFG_TBL_TOKEN_UNIT_OFFSET  64
+	#define L1_SHP_CFG_TBL_TOKEN_UNIT_LEN     3
+	#define L1_SHP_CFG_TBL_TOKEN_UNIT_DEFAULT 0x0
+	/*[field] METER_UNIT*/
+	#define L1_SHP_CFG_TBL_METER_UNIT
+	#define L1_SHP_CFG_TBL_METER_UNIT_OFFSET  67
+	#define L1_SHP_CFG_TBL_METER_UNIT_LEN     1
+	#define L1_SHP_CFG_TBL_METER_UNIT_DEFAULT 0x0
+	/*[field] C_SHAPER_ENABLE*/
+	#define L1_SHP_CFG_TBL_C_SHAPER_ENABLE
+	#define L1_SHP_CFG_TBL_C_SHAPER_ENABLE_OFFSET  68
+	#define L1_SHP_CFG_TBL_C_SHAPER_ENABLE_LEN     1
+	#define L1_SHP_CFG_TBL_C_SHAPER_ENABLE_DEFAULT 0x0
+	/*[field] E_SHAPER_ENABLE*/
+	#define L1_SHP_CFG_TBL_E_SHAPER_ENABLE
+	#define L1_SHP_CFG_TBL_E_SHAPER_ENABLE_OFFSET  69
+	#define L1_SHP_CFG_TBL_E_SHAPER_ENABLE_LEN     1
+	#define L1_SHP_CFG_TBL_E_SHAPER_ENABLE_DEFAULT 0x0
+	/*[field] CF*/
+	#define L1_SHP_CFG_TBL_CF
+	#define L1_SHP_CFG_TBL_CF_OFFSET  70
+	#define L1_SHP_CFG_TBL_CF_LEN     1
+	#define L1_SHP_CFG_TBL_CF_DEFAULT 0x0
+
+struct l1_shp_cfg_tbl {
+	a_uint32_t  cir:18;
+	a_uint32_t  cbs:14;
+	a_uint32_t  eir:18;
+	a_uint32_t  ebs:14;
+	a_uint32_t  token_unit:3;
+	a_uint32_t  meter_unit:1;
+	a_uint32_t  c_shaper_enable:1;
+	a_uint32_t  e_shaper_enable:1;
+	a_uint32_t  cf:1;
+	a_uint32_t  _reserved0:25;
+};
+
+union l1_shp_cfg_tbl_u {
+	a_uint32_t val[3];
+	struct l1_shp_cfg_tbl bf;
+};
+
+/*[table] L1_COMP_TBL*/
+#define L1_COMP_TBL
+#define L1_COMP_TBL_ADDRESS 0x68000
+#define L1_COMP_TBL_NUM     64
+#define L1_COMP_TBL_INC     0x10
+#define L1_COMP_TBL_TYPE    REG_TYPE_RO
+#define L1_COMP_TBL_DEFAULT 0x0
+	/*[field] C_SHAPER_COMPENSATE_BYTE_CNT*/
+	#define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT
+	#define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT_OFFSET  0
+	#define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT_LEN     18
+	#define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT_DEFAULT 0x0
+	/*[field] C_SHAPER_COMPENSATE_BYTE_NEG*/
+	#define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG
+	#define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG_OFFSET  18
+	#define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG_LEN     1
+	#define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG_DEFAULT 0x0
+	/*[field] C_SHAPER_COMPENSATE_PKT_CNT*/
+	#define L1_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT
+	#define L1_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT_OFFSET  19
+	#define L1_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT_LEN     4
+	#define L1_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT_DEFAULT 0x0
+	/*[field] C_DRR_COMPENSATE_BYTE_CNT*/
+	#define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT
+	#define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT_OFFSET  23
+	#define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT_LEN     18
+	#define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT_DEFAULT 0x0
+	/*[field] C_DRR_COMPENSATE_BYTE_NEG*/
+	#define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG
+	#define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG_OFFSET  41
+	#define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG_LEN     1
+	#define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG_DEFAULT 0x0
+	/*[field] C_DRR_COMPENSATE_PKT_CNT*/
+	#define L1_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT
+	#define L1_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT_OFFSET  42
+	#define L1_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT_LEN     4
+	#define L1_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT_DEFAULT 0x0
+	/*[field] E_SHAPER_COMPENSATE_BYTE_CNT*/
+	#define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT
+	#define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT_OFFSET  46
+	#define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT_LEN     18
+	#define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT_DEFAULT 0x0
+	/*[field] E_SHAPER_COMPENSATE_BYTE_NEG*/
+	#define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG
+	#define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG_OFFSET  64
+	#define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG_LEN     1
+	#define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG_DEFAULT 0x0
+	/*[field] E_SHAPER_COMPENSATE_PKT_CNT*/
+	#define L1_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT
+	#define L1_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT_OFFSET  65
+	#define L1_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT_LEN     4
+	#define L1_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT_DEFAULT 0x0
+	/*[field] E_DRR_COMPENSATE_BYTE_CNT*/
+	#define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT
+	#define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT_OFFSET  69
+	#define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT_LEN     18
+	#define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT_DEFAULT 0x0
+	/*[field] E_DRR_COMPENSATE_BYTE_NEG*/
+	#define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG
+	#define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG_OFFSET  87
+	#define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG_LEN     1
+	#define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG_DEFAULT 0x0
+	/*[field] E_DRR_COMPENSATE_PKT_CNT*/
+	#define L1_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT
+	#define L1_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT_OFFSET  88
+	#define L1_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT_LEN     4
+	#define L1_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT_DEFAULT 0x0
+
+struct l1_comp_tbl {
+	a_uint32_t  c_shaper_compensate_byte_cnt:18;
+	a_uint32_t  c_shaper_compensate_byte_neg:1;
+	a_uint32_t  c_shaper_compensate_pkt_cnt:4;
+	a_uint32_t  c_drr_compensate_byte_cnt_0:9;
+	a_uint32_t  c_drr_compensate_byte_cnt_1:9;
+	a_uint32_t  c_drr_compensate_byte_neg:1;
+	a_uint32_t  c_drr_compensate_pkt_cnt:4;
+	a_uint32_t  e_shaper_compensate_byte_cnt:18;
+	a_uint32_t  e_shaper_compensate_byte_neg:1;
+	a_uint32_t  e_shaper_compensate_pkt_cnt:4;
+	a_uint32_t  e_drr_compensate_byte_cnt:18;
+	a_uint32_t  e_drr_compensate_byte_neg:1;
+	a_uint32_t  e_drr_compensate_pkt_cnt:4;
+	a_uint32_t  _reserved0:4;
+};
+
+union l1_comp_tbl_u {
+	a_uint32_t val[3];
+	struct l1_comp_tbl bf;
+};
+
+/*[table] L1_COMP_CFG_TBL*/
+#define L1_COMP_CFG_TBL
+#define L1_COMP_CFG_TBL_ADDRESS 0x6a000
+#define L1_COMP_CFG_TBL_NUM     64
+#define L1_COMP_CFG_TBL_INC     0x10
+#define L1_COMP_CFG_TBL_TYPE    REG_TYPE_RW
+#define L1_COMP_CFG_TBL_DEFAULT 0x0
+	/*[field] SHAPER_METER_LEN*/
+	#define L1_COMP_CFG_TBL_SHAPER_METER_LEN
+	#define L1_COMP_CFG_TBL_SHAPER_METER_LEN_OFFSET  0
+	#define L1_COMP_CFG_TBL_SHAPER_METER_LEN_LEN     2
+	#define L1_COMP_CFG_TBL_SHAPER_METER_LEN_DEFAULT 0x0
+	/*[field] DRR_METER_LEN*/
+	#define L1_COMP_CFG_TBL_DRR_METER_LEN
+	#define L1_COMP_CFG_TBL_DRR_METER_LEN_OFFSET  2
+	#define L1_COMP_CFG_TBL_DRR_METER_LEN_LEN     2
+	#define L1_COMP_CFG_TBL_DRR_METER_LEN_DEFAULT 0x0
+
+struct l1_comp_cfg_tbl {
+	a_uint32_t  shaper_meter_len:2;
+	a_uint32_t  drr_meter_len:2;
+	a_uint32_t  _reserved0:28;
+};
+
+union l1_comp_cfg_tbl_u {
+	a_uint32_t val;
+	struct l1_comp_cfg_tbl bf;
+};
+
+/*[table] PSCH_SHP_SIGN_TBL*/
+#define PSCH_SHP_SIGN_TBL
+#define PSCH_SHP_SIGN_TBL_ADDRESS 0x70000
+#define PSCH_SHP_SIGN_TBL_NUM     8
+#define PSCH_SHP_SIGN_TBL_INC     0x10
+#define PSCH_SHP_SIGN_TBL_TYPE    REG_TYPE_RW
+#define PSCH_SHP_SIGN_TBL_DEFAULT 0x0
+	/*[field] SHAPER_CREDIT_NEG*/
+	#define PSCH_SHP_SIGN_TBL_SHAPER_CREDIT_NEG
+	#define PSCH_SHP_SIGN_TBL_SHAPER_CREDIT_NEG_OFFSET  0
+	#define PSCH_SHP_SIGN_TBL_SHAPER_CREDIT_NEG_LEN     1
+	#define PSCH_SHP_SIGN_TBL_SHAPER_CREDIT_NEG_DEFAULT 0x0
+
+struct psch_shp_sign_tbl {
+	a_uint32_t  shaper_credit_neg:1;
+	a_uint32_t  _reserved0:31;
+};
+
+union psch_shp_sign_tbl_u {
+	a_uint32_t val;
+	struct psch_shp_sign_tbl bf;
+};
+
+/*[table] PSCH_SHP_CREDIT_TBL*/
+#define PSCH_SHP_CREDIT_TBL
+#define PSCH_SHP_CREDIT_TBL_ADDRESS 0x72000
+#define PSCH_SHP_CREDIT_TBL_NUM     8
+#define PSCH_SHP_CREDIT_TBL_INC     0x10
+#define PSCH_SHP_CREDIT_TBL_TYPE    REG_TYPE_RW
+#define PSCH_SHP_CREDIT_TBL_DEFAULT 0x0
+	/*[field] SHAPER_CREDIT*/
+	#define PSCH_SHP_CREDIT_TBL_SHAPER_CREDIT
+	#define PSCH_SHP_CREDIT_TBL_SHAPER_CREDIT_OFFSET  0
+	#define PSCH_SHP_CREDIT_TBL_SHAPER_CREDIT_LEN     30
+	#define PSCH_SHP_CREDIT_TBL_SHAPER_CREDIT_DEFAULT 0x0
+
+struct psch_shp_credit_tbl {
+	a_uint32_t  shaper_credit:30;
+	a_uint32_t  _reserved0:2;
+};
+
+union psch_shp_credit_tbl_u {
+	a_uint32_t val;
+	struct psch_shp_credit_tbl bf;
+};
+
+/*[table] PSCH_SHP_CFG_TBL*/
+#define PSCH_SHP_CFG_TBL
+#define PSCH_SHP_CFG_TBL_ADDRESS 0x74000
+#define PSCH_SHP_CFG_TBL_NUM     8
+#define PSCH_SHP_CFG_TBL_INC     0x10
+#define PSCH_SHP_CFG_TBL_TYPE    REG_TYPE_RW
+#define PSCH_SHP_CFG_TBL_DEFAULT 0x0
+	/*[field] CIR*/
+	#define PSCH_SHP_CFG_TBL_CIR
+	#define PSCH_SHP_CFG_TBL_CIR_OFFSET  0
+	#define PSCH_SHP_CFG_TBL_CIR_LEN     18
+	#define PSCH_SHP_CFG_TBL_CIR_DEFAULT 0x0
+	/*[field] CBS*/
+	#define PSCH_SHP_CFG_TBL_CBS
+	#define PSCH_SHP_CFG_TBL_CBS_OFFSET  18
+	#define PSCH_SHP_CFG_TBL_CBS_LEN     14
+	#define PSCH_SHP_CFG_TBL_CBS_DEFAULT 0x0
+	/*[field] TOKEN_UNIT*/
+	#define PSCH_SHP_CFG_TBL_TOKEN_UNIT
+	#define PSCH_SHP_CFG_TBL_TOKEN_UNIT_OFFSET  32
+	#define PSCH_SHP_CFG_TBL_TOKEN_UNIT_LEN     3
+	#define PSCH_SHP_CFG_TBL_TOKEN_UNIT_DEFAULT 0x0
+	/*[field] METER_UNIT*/
+	#define PSCH_SHP_CFG_TBL_METER_UNIT
+	#define PSCH_SHP_CFG_TBL_METER_UNIT_OFFSET  35
+	#define PSCH_SHP_CFG_TBL_METER_UNIT_LEN     1
+	#define PSCH_SHP_CFG_TBL_METER_UNIT_DEFAULT 0x0
+	/*[field] SHAPER_ENABLE*/
+	#define PSCH_SHP_CFG_TBL_SHAPER_ENABLE
+	#define PSCH_SHP_CFG_TBL_SHAPER_ENABLE_OFFSET  36
+	#define PSCH_SHP_CFG_TBL_SHAPER_ENABLE_LEN     1
+	#define PSCH_SHP_CFG_TBL_SHAPER_ENABLE_DEFAULT 0x0
+
+struct psch_shp_cfg_tbl {
+	a_uint32_t  cir:18;
+	a_uint32_t  cbs:14;
+	a_uint32_t  token_unit:3;
+	a_uint32_t  meter_unit:1;
+	a_uint32_t  shaper_enable:1;
+	a_uint32_t  _reserved0:27;
+};
+
+union psch_shp_cfg_tbl_u {
+	a_uint32_t val[2];
+	struct psch_shp_cfg_tbl bf;
+};
+
+/*[table] PSCH_COMP_TBL*/
+#define PSCH_COMP_TBL
+#define PSCH_COMP_TBL_ADDRESS 0x76000
+#define PSCH_COMP_TBL_NUM     8
+#define PSCH_COMP_TBL_INC     0x10
+#define PSCH_COMP_TBL_TYPE    REG_TYPE_RO
+#define PSCH_COMP_TBL_DEFAULT 0x0
+	/*[field] SHAPER_COMPENSATE_BYTE_CNT*/
+	#define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_CNT
+	#define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_CNT_OFFSET  0
+	#define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_CNT_LEN     18
+	#define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_CNT_DEFAULT 0x0
+	/*[field] SHAPER_COMPENSATE_BYTE_NEG*/
+	#define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_NEG
+	#define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_NEG_OFFSET  18
+	#define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_NEG_LEN     1
+	#define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_NEG_DEFAULT 0x0
+	/*[field] SHAPER_COMPENSATE_PKT_CNT*/
+	#define PSCH_COMP_TBL_SHAPER_COMPENSATE_PKT_CNT
+	#define PSCH_COMP_TBL_SHAPER_COMPENSATE_PKT_CNT_OFFSET  19
+	#define PSCH_COMP_TBL_SHAPER_COMPENSATE_PKT_CNT_LEN     4
+	#define PSCH_COMP_TBL_SHAPER_COMPENSATE_PKT_CNT_DEFAULT 0x0
+
+struct psch_comp_tbl {
+	a_uint32_t  shaper_compensate_byte_cnt:18;
+	a_uint32_t  shaper_compensate_byte_neg:1;
+	a_uint32_t  shaper_compensate_pkt_cnt:4;
+	a_uint32_t  _reserved0:9;
+};
+
+union psch_comp_tbl_u {
+	a_uint32_t val;
+	struct psch_comp_tbl bf;
+};
+
+/*[table] PSCH_COMP_CFG_TBL*/
+#define PSCH_COMP_CFG_TBL
+#define PSCH_COMP_CFG_TBL_ADDRESS 0x78000
+#define PSCH_COMP_CFG_TBL_NUM     8
+#define PSCH_COMP_CFG_TBL_INC     0x10
+#define PSCH_COMP_CFG_TBL_TYPE    REG_TYPE_RW
+#define PSCH_COMP_CFG_TBL_DEFAULT 0x0
+	/*[field] SHAPER_METER_LEN*/
+	#define PSCH_COMP_CFG_TBL_SHAPER_METER_LEN
+	#define PSCH_COMP_CFG_TBL_SHAPER_METER_LEN_OFFSET  0
+	#define PSCH_COMP_CFG_TBL_SHAPER_METER_LEN_LEN     2
+	#define PSCH_COMP_CFG_TBL_SHAPER_METER_LEN_DEFAULT 0x0
+
+struct psch_comp_cfg_tbl {
+	a_uint32_t  shaper_meter_len:2;
+	a_uint32_t  _reserved0:30;
+};
+
+union psch_comp_cfg_tbl_u {
+	a_uint32_t val;
+	struct psch_comp_cfg_tbl bf;
+};
+
+/*[register] IPG_PRE_LEN_CFG*/
+#define IPG_PRE_LEN_CFG
+#define IPG_PRE_LEN_CFG_ADDRESS 0x8
+#define IPG_PRE_LEN_CFG_NUM     1
+#define IPG_PRE_LEN_CFG_INC     0x4
+#define IPG_PRE_LEN_CFG_TYPE    REG_TYPE_RW
+#define IPG_PRE_LEN_CFG_DEFAULT 0x0
+	/*[field] IPG_PRE_LEN*/
+	#define IPG_PRE_LEN_CFG_IPG_PRE_LEN
+	#define IPG_PRE_LEN_CFG_IPG_PRE_LEN_OFFSET  0
+	#define IPG_PRE_LEN_CFG_IPG_PRE_LEN_LEN     5
+	#define IPG_PRE_LEN_CFG_IPG_PRE_LEN_DEFAULT 0x0
+
+struct ipg_pre_len_cfg {
+	a_uint32_t  ipg_pre_len:5;
+	a_uint32_t  _reserved0:27;
+};
+
+union ipg_pre_len_cfg_u {
+	a_uint32_t val;
+	struct ipg_pre_len_cfg bf;
+};
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_stp.h b/qca-ssdk/include/hsl/hppe/hppe_stp.h
new file mode 100755
index 0000000..76443dd
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_stp.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_STP_H_
+#define _HPPE_STP_H_
+
+#define CST_STATE_MAX_ENTRY	8
+
+sw_error_t
+hppe_cst_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union cst_state_u *value);
+
+sw_error_t
+hppe_cst_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union cst_state_u *value);
+
+sw_error_t
+hppe_cst_state_port_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_cst_state_port_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_stp_reg.h b/qca-ssdk/include/hsl/hppe/hppe_stp_reg.h
new file mode 100755
index 0000000..c472b7b
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_stp_reg.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_STP_REG_H
+#define HPPE_STP_REG_H
+
+/*[register] CST_STATE*/
+#define CST_STATE
+#define CST_STATE_ADDRESS 0x100
+#define CST_STATE_NUM     8
+#define CST_STATE_INC     0x4
+#define CST_STATE_TYPE    REG_TYPE_RW
+#define CST_STATE_DEFAULT 0x3
+	/*[field] PORT_STATE*/
+	#define CST_STATE_PORT_STATE
+	#define CST_STATE_PORT_STATE_OFFSET  0
+	#define CST_STATE_PORT_STATE_LEN     2
+	#define CST_STATE_PORT_STATE_DEFAULT 0x3
+
+struct cst_state {
+	a_uint32_t  port_state:2;
+	a_uint32_t  _reserved0:30;
+};
+
+union cst_state_u {
+	a_uint32_t val;
+	struct cst_state bf;
+};
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_trunk.h b/qca-ssdk/include/hsl/hppe/hppe_trunk.h
new file mode 100755
index 0000000..279b5d9
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_trunk.h
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_TRUNK_H_
+#define _HPPE_TRUNK_H_
+
+
+#define PORT_PARSING_REG_MAX_ENTRY	8
+
+#define PC_GLOBAL_CNT_TBL_MAX_ENTRY	3
+#define TRUNK_FILTER_MAX_ENTRY	2
+#define TRUNK_MEMBER_MAX_ENTRY	2
+#define PORT_TRUNK_ID_MAX_ENTRY	8
+
+sw_error_t
+hppe_trunk_hash_field_reg_get(
+		a_uint32_t dev_id,
+		union trunk_hash_field_reg_u *value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_set(
+		a_uint32_t dev_id,
+		union trunk_hash_field_reg_u *value);
+
+sw_error_t
+hppe_trunk_filter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union trunk_filter_u *value);
+
+sw_error_t
+hppe_trunk_filter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union trunk_filter_u *value);
+
+sw_error_t
+hppe_trunk_member_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union trunk_member_u *value);
+
+sw_error_t
+hppe_trunk_member_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union trunk_member_u *value);
+
+sw_error_t
+hppe_port_trunk_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_trunk_id_u *value);
+
+sw_error_t
+hppe_port_trunk_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_trunk_id_u *value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf2_incl_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf2_incl_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_mac_da_incl_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_mac_da_incl_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_src_port_incl_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_src_port_incl_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf3_incl_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf3_incl_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_l4_dst_port_incl_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_l4_dst_port_incl_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf0_incl_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf0_incl_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_dst_ip_incl_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_dst_ip_incl_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_l4_src_port_incl_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_l4_src_port_incl_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_src_ip_incl_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_src_ip_incl_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf1_incl_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf1_incl_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_mac_sa_incl_get(
+		a_uint32_t dev_id,
+		unsigned int *value);
+
+sw_error_t
+hppe_trunk_hash_field_reg_mac_sa_incl_set(
+		a_uint32_t dev_id,
+		unsigned int value);
+
+sw_error_t
+hppe_trunk_filter_mem_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_trunk_filter_mem_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_trunk_member_member_2_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_trunk_member_member_2_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_trunk_member_member_0_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_trunk_member_member_0_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_trunk_member_member_1_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_trunk_member_member_1_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_trunk_member_member_6_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_trunk_member_member_6_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_trunk_member_member_4_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_trunk_member_member_4_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_trunk_member_member_3_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_trunk_member_member_3_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_trunk_member_member_5_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_trunk_member_member_5_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_trunk_member_member_7_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_trunk_member_member_7_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_trunk_id_trunk_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_trunk_id_trunk_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_port_trunk_id_trunk_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_port_trunk_id_trunk_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_trunk_reg.h b/qca-ssdk/include/hsl/hppe/hppe_trunk_reg.h
new file mode 100755
index 0000000..7f9af5c
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_trunk_reg.h
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_TRUNK_REG_H
+#define HPPE_TRUNK_REG_H
+
+/*[register] TRUNK_HASH_FIELD_REG*/
+#define TRUNK_HASH_FIELD_REG
+#define TRUNK_HASH_FIELD_REG_ADDRESS 0x68
+#define TRUNK_HASH_FIELD_REG_NUM     1
+#define TRUNK_HASH_FIELD_REG_INC     0x4
+#define TRUNK_HASH_FIELD_REG_TYPE    REG_TYPE_RW
+#define TRUNK_HASH_FIELD_REG_DEFAULT 0x0
+	/*[field] SRC_PORT_INCL*/
+	#define TRUNK_HASH_FIELD_REG_SRC_PORT_INCL
+	#define TRUNK_HASH_FIELD_REG_SRC_PORT_INCL_OFFSET  0
+	#define TRUNK_HASH_FIELD_REG_SRC_PORT_INCL_LEN     1
+	#define TRUNK_HASH_FIELD_REG_SRC_PORT_INCL_DEFAULT 0x0
+	/*[field] MAC_DA_INCL*/
+	#define TRUNK_HASH_FIELD_REG_MAC_DA_INCL
+	#define TRUNK_HASH_FIELD_REG_MAC_DA_INCL_OFFSET  1
+	#define TRUNK_HASH_FIELD_REG_MAC_DA_INCL_LEN     1
+	#define TRUNK_HASH_FIELD_REG_MAC_DA_INCL_DEFAULT 0x0
+	/*[field] MAC_SA_INCL*/
+	#define TRUNK_HASH_FIELD_REG_MAC_SA_INCL
+	#define TRUNK_HASH_FIELD_REG_MAC_SA_INCL_OFFSET  2
+	#define TRUNK_HASH_FIELD_REG_MAC_SA_INCL_LEN     1
+	#define TRUNK_HASH_FIELD_REG_MAC_SA_INCL_DEFAULT 0x0
+	/*[field] SRC_IP_INCL*/
+	#define TRUNK_HASH_FIELD_REG_SRC_IP_INCL
+	#define TRUNK_HASH_FIELD_REG_SRC_IP_INCL_OFFSET  3
+	#define TRUNK_HASH_FIELD_REG_SRC_IP_INCL_LEN     1
+	#define TRUNK_HASH_FIELD_REG_SRC_IP_INCL_DEFAULT 0x0
+	/*[field] DST_IP_INCL*/
+	#define TRUNK_HASH_FIELD_REG_DST_IP_INCL
+	#define TRUNK_HASH_FIELD_REG_DST_IP_INCL_OFFSET  4
+	#define TRUNK_HASH_FIELD_REG_DST_IP_INCL_LEN     1
+	#define TRUNK_HASH_FIELD_REG_DST_IP_INCL_DEFAULT 0x0
+	/*[field] L4_SRC_PORT_INCL*/
+	#define TRUNK_HASH_FIELD_REG_L4_SRC_PORT_INCL
+	#define TRUNK_HASH_FIELD_REG_L4_SRC_PORT_INCL_OFFSET  5
+	#define TRUNK_HASH_FIELD_REG_L4_SRC_PORT_INCL_LEN     1
+	#define TRUNK_HASH_FIELD_REG_L4_SRC_PORT_INCL_DEFAULT 0x0
+	/*[field] L4_DST_PORT_INCL*/
+	#define TRUNK_HASH_FIELD_REG_L4_DST_PORT_INCL
+	#define TRUNK_HASH_FIELD_REG_L4_DST_PORT_INCL_OFFSET  6
+	#define TRUNK_HASH_FIELD_REG_L4_DST_PORT_INCL_LEN     1
+	#define TRUNK_HASH_FIELD_REG_L4_DST_PORT_INCL_DEFAULT 0x0
+	/*[field] UDF0_INCL*/
+	#define TRUNK_HASH_FIELD_REG_UDF0_INCL
+	#define TRUNK_HASH_FIELD_REG_UDF0_INCL_OFFSET  7
+	#define TRUNK_HASH_FIELD_REG_UDF0_INCL_LEN     1
+	#define TRUNK_HASH_FIELD_REG_UDF0_INCL_DEFAULT 0x0
+	/*[field] UDF1_INCL*/
+	#define TRUNK_HASH_FIELD_REG_UDF1_INCL
+	#define TRUNK_HASH_FIELD_REG_UDF1_INCL_OFFSET  8
+	#define TRUNK_HASH_FIELD_REG_UDF1_INCL_LEN     1
+	#define TRUNK_HASH_FIELD_REG_UDF1_INCL_DEFAULT 0x0
+	/*[field] UDF2_INCL*/
+	#define TRUNK_HASH_FIELD_REG_UDF2_INCL
+	#define TRUNK_HASH_FIELD_REG_UDF2_INCL_OFFSET  9
+	#define TRUNK_HASH_FIELD_REG_UDF2_INCL_LEN     1
+	#define TRUNK_HASH_FIELD_REG_UDF2_INCL_DEFAULT 0x0
+	/*[field] UDF3_INCL*/
+	#define TRUNK_HASH_FIELD_REG_UDF3_INCL
+	#define TRUNK_HASH_FIELD_REG_UDF3_INCL_OFFSET  10
+	#define TRUNK_HASH_FIELD_REG_UDF3_INCL_LEN     1
+	#define TRUNK_HASH_FIELD_REG_UDF3_INCL_DEFAULT 0x0
+
+struct trunk_hash_field_reg {
+	a_uint32_t  src_port_incl:1;
+	a_uint32_t  mac_da_incl:1;
+	a_uint32_t  mac_sa_incl:1;
+	a_uint32_t  src_ip_incl:1;
+	a_uint32_t  dst_ip_incl:1;
+	a_uint32_t  l4_src_port_incl:1;
+	a_uint32_t  l4_dst_port_incl:1;
+	a_uint32_t  udf0_incl:1;
+	a_uint32_t  udf1_incl:1;
+	a_uint32_t  udf2_incl:1;
+	a_uint32_t  udf3_incl:1;
+	a_uint32_t  _reserved0:21;
+};
+
+union trunk_hash_field_reg_u {
+	a_uint32_t val;
+	struct trunk_hash_field_reg bf;
+};
+
+/*[register] TRUNK_FILTER*/
+#define TRUNK_FILTER
+#define TRUNK_FILTER_ADDRESS 0x50
+#define TRUNK_FILTER_NUM     2
+#define TRUNK_FILTER_INC     0x4
+#define TRUNK_FILTER_TYPE    REG_TYPE_RW
+#define TRUNK_FILTER_DEFAULT 0x0
+	/*[field] MEM_BITMAP*/
+	#define TRUNK_FILTER_MEM_BITMAP
+	#define TRUNK_FILTER_MEM_BITMAP_OFFSET  0
+	#define TRUNK_FILTER_MEM_BITMAP_LEN     8
+	#define TRUNK_FILTER_MEM_BITMAP_DEFAULT 0x0
+
+struct trunk_filter {
+	a_uint32_t  mem_bitmap:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union trunk_filter_u {
+	a_uint32_t val;
+	struct trunk_filter bf;
+};
+
+/*[register] TRUNK_MEMBER*/
+#define TRUNK_MEMBER
+#define TRUNK_MEMBER_ADDRESS 0x60
+#define TRUNK_MEMBER_NUM     2
+#define TRUNK_MEMBER_INC     0x4
+#define TRUNK_MEMBER_TYPE    REG_TYPE_RW
+#define TRUNK_MEMBER_DEFAULT 0x0
+	/*[field] MEMBER_0_PORT_ID*/
+	#define TRUNK_MEMBER_MEMBER_0_PORT_ID
+	#define TRUNK_MEMBER_MEMBER_0_PORT_ID_OFFSET  0
+	#define TRUNK_MEMBER_MEMBER_0_PORT_ID_LEN     3
+	#define TRUNK_MEMBER_MEMBER_0_PORT_ID_DEFAULT 0x0
+	/*[field] MEMBER_1_PORT_ID*/
+	#define TRUNK_MEMBER_MEMBER_1_PORT_ID
+	#define TRUNK_MEMBER_MEMBER_1_PORT_ID_OFFSET  4
+	#define TRUNK_MEMBER_MEMBER_1_PORT_ID_LEN     3
+	#define TRUNK_MEMBER_MEMBER_1_PORT_ID_DEFAULT 0x0
+	/*[field] MEMBER_2_PORT_ID*/
+	#define TRUNK_MEMBER_MEMBER_2_PORT_ID
+	#define TRUNK_MEMBER_MEMBER_2_PORT_ID_OFFSET  8
+	#define TRUNK_MEMBER_MEMBER_2_PORT_ID_LEN     3
+	#define TRUNK_MEMBER_MEMBER_2_PORT_ID_DEFAULT 0x0
+	/*[field] MEMBER_3_PORT_ID*/
+	#define TRUNK_MEMBER_MEMBER_3_PORT_ID
+	#define TRUNK_MEMBER_MEMBER_3_PORT_ID_OFFSET  12
+	#define TRUNK_MEMBER_MEMBER_3_PORT_ID_LEN     3
+	#define TRUNK_MEMBER_MEMBER_3_PORT_ID_DEFAULT 0x0
+	/*[field] MEMBER_4_PORT_ID*/
+	#define TRUNK_MEMBER_MEMBER_4_PORT_ID
+	#define TRUNK_MEMBER_MEMBER_4_PORT_ID_OFFSET  16
+	#define TRUNK_MEMBER_MEMBER_4_PORT_ID_LEN     3
+	#define TRUNK_MEMBER_MEMBER_4_PORT_ID_DEFAULT 0x0
+	/*[field] MEMBER_5_PORT_ID*/
+	#define TRUNK_MEMBER_MEMBER_5_PORT_ID
+	#define TRUNK_MEMBER_MEMBER_5_PORT_ID_OFFSET  20
+	#define TRUNK_MEMBER_MEMBER_5_PORT_ID_LEN     3
+	#define TRUNK_MEMBER_MEMBER_5_PORT_ID_DEFAULT 0x0
+	/*[field] MEMBER_6_PORT_ID*/
+	#define TRUNK_MEMBER_MEMBER_6_PORT_ID
+	#define TRUNK_MEMBER_MEMBER_6_PORT_ID_OFFSET  24
+	#define TRUNK_MEMBER_MEMBER_6_PORT_ID_LEN     3
+	#define TRUNK_MEMBER_MEMBER_6_PORT_ID_DEFAULT 0x0
+	/*[field] MEMBER_7_PORT_ID*/
+	#define TRUNK_MEMBER_MEMBER_7_PORT_ID
+	#define TRUNK_MEMBER_MEMBER_7_PORT_ID_OFFSET  28
+	#define TRUNK_MEMBER_MEMBER_7_PORT_ID_LEN     3
+	#define TRUNK_MEMBER_MEMBER_7_PORT_ID_DEFAULT 0x0
+
+struct trunk_member {
+	a_uint32_t  member_0_port_id:3;
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  member_1_port_id:3;
+	a_uint32_t  _reserved1:1;
+	a_uint32_t  member_2_port_id:3;
+	a_uint32_t  _reserved2:1;
+	a_uint32_t  member_3_port_id:3;
+	a_uint32_t  _reserved3:1;
+	a_uint32_t  member_4_port_id:3;
+	a_uint32_t  _reserved4:1;
+	a_uint32_t  member_5_port_id:3;
+	a_uint32_t  _reserved5:1;
+	a_uint32_t  member_6_port_id:3;
+	a_uint32_t  _reserved6:1;
+	a_uint32_t  member_7_port_id:3;
+	a_uint32_t  _reserved7:1;
+};
+
+union trunk_member_u {
+	a_uint32_t val;
+	struct trunk_member bf;
+};
+
+/*[register] PORT_TRUNK_ID*/
+#define PORT_TRUNK_ID
+#define PORT_TRUNK_ID_ADDRESS 0x600
+#define PORT_TRUNK_ID_NUM     8
+#define PORT_TRUNK_ID_INC     0x4
+#define PORT_TRUNK_ID_TYPE    REG_TYPE_RW
+#define PORT_TRUNK_ID_DEFAULT 0x0
+	/*[field] TRUNK_EN*/
+	#define PORT_TRUNK_ID_TRUNK_EN
+	#define PORT_TRUNK_ID_TRUNK_EN_OFFSET  0
+	#define PORT_TRUNK_ID_TRUNK_EN_LEN     1
+	#define PORT_TRUNK_ID_TRUNK_EN_DEFAULT 0x0
+	/*[field] TRUNK_ID*/
+	#define PORT_TRUNK_ID_TRUNK_ID
+	#define PORT_TRUNK_ID_TRUNK_ID_OFFSET  1
+	#define PORT_TRUNK_ID_TRUNK_ID_LEN     1
+	#define PORT_TRUNK_ID_TRUNK_ID_DEFAULT 0x0
+
+struct port_trunk_id {
+	a_uint32_t  trunk_en:1;
+	a_uint32_t  trunk_id:1;
+	a_uint32_t  _reserved0:30;
+};
+
+union port_trunk_id_u {
+	a_uint32_t val;
+	struct port_trunk_id bf;
+};
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_uniphy.h b/qca-ssdk/include/hsl/hppe/hppe_uniphy.h
new file mode 100755
index 0000000..c41c5bb
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_uniphy.h
@@ -0,0 +1,2440 @@
+/*
+ * Copyright (c) 2017, 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_UNIPHY_H_
+#define _HPPE_UNIPHY_H_
+
+#define UNIPHY_OFFSET_CALIB_4_MAX_ENTRY                 3
+#define UNIPHY_MODE_CTRL_MAX_ENTRY                      3
+#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_MAX_ENTRY        3
+#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_MAX_ENTRY        3
+#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_MAX_ENTRY        3
+#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_MAX_ENTRY        3
+#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_MAX_ENTRY        3
+#define SR_XS_PCS_KR_STS1_MAX_ENTRY                     3
+#define VR_XS_PCS_DIG_CTRL1_MAX_ENTRY                   3
+#define SR_MII_CTRL_MAX_ENTRY                           3
+#define VR_MII_AN_CTRL_MAX_ENTRY                        3
+#define VR_MII_AN_INTR_STS_MAX_ENTRY                    3
+
+#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MAX_ENTRY      3
+#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MAX_ENTRY        3
+#define UNIPHY_RESISTOR_CALIBRATION_1_MAX_ENTRY         3
+#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MAX_ENTRY      3
+#define UNIPHY_RX_AFE_2_MAX_ENTRY                       3
+#define BANDGAP_IP_MBIAS_2_MAX_ENTRY                    4
+#define LDO_0P9V_RELATED_1_MAX_ENTRY                    4
+#define OTP_VTT_LDO_RELATED_MAX_ENTRY                   4
+#define OTP_TEMPERATURE_COMPENSATE_1_MAX_ENTRY          4
+#define PLL_VCO_RELATED_CONTROL_1_MAX_ENTRY             4
+#define PLL_CONTROL_VCO_RELATED_SELECTION_2_MAX_ENTRY   4
+#define UNIPHY_MISC2_PHY_MODE_MAX_ENTRY                 4
+#define UNIPHY_PLL_POWER_ON_AND_RESET_INC_MAX_ENTRY     4
+
+sw_error_t
+hppe_uniphy_offset_calib_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_offset_calib_4_u *value);
+
+sw_error_t
+hppe_uniphy_offset_calib_4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_offset_calib_4_u *value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_mode_ctrl_u *value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_mode_ctrl_u *value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel0_input_output_4_u *value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel0_input_output_4_u *value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel1_input_output_4_u *value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel1_input_output_4_u *value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel2_input_output_4_u *value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel2_input_output_4_u *value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel3_input_output_4_u *value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel3_input_output_4_u *value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel4_input_output_4_u *value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel4_input_output_4_u *value);
+
+sw_error_t
+hppe_uniphy_instance_link_detect_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_instance_link_detect_u *value);
+
+sw_error_t
+hppe_uniphy_instance_link_detect_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_instance_link_detect_u *value);
+
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sr_xs_pcs_kr_sts1_u *value);
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sr_xs_pcs_kr_sts1_u *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vr_xs_pcs_dig_ctrl1_u *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vr_xs_pcs_dig_ctrl1_u *value);
+
+sw_error_t
+hppe_sr_mii_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sr_mii_ctrl_u *value);
+
+sw_error_t
+hppe_sr_mii_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sr_mii_ctrl_u *value);
+
+sw_error_t
+hppe_vr_mii_an_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vr_mii_an_ctrl_u *value);
+
+sw_error_t
+hppe_vr_mii_an_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vr_mii_an_ctrl_u *value);
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vr_mii_an_intr_sts_u *value);
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vr_mii_an_intr_sts_u *value);
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_cal_rep_time_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_cal_rep_time_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_pll_locked_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_pll_locked_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_clr_sampler_calib_timeout_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_clr_sampler_calib_timeout_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_lockdet_lckdt_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_lockdet_lckdt_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_cal_detect_time_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_cal_detect_time_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_calibration_done_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_calibration_done_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_smpl_cal_ready_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_smpl_cal_ready_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch1_ch0_sgmii_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch1_ch0_sgmii_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_usxg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_usxg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch4_ch1_0_sgmii_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch4_ch1_0_sgmii_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sgplus_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sgplus_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_xpcs_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_xpcs_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_psgmii_qsgmii_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_psgmii_qsgmii_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_autoneg_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_autoneg_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sw_v17_v18_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sw_v17_v18_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_mode_ctrl_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_mode_ctrl_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sgmii_even_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sgmii_even_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_qsgmii_sgmii_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_qsgmii_sgmii_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sg_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sg_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_restart_an_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_restart_an_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_rem_phy_lpbk_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_rem_phy_lpbk_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_reg4_ch_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_reg4_ch_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_power_on_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_power_on_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_main_reset_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_main_reset_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel0_force_speed_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel0_force_speed_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_adp_sw_rstn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_adp_sw_rstn_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_an_enable_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_an_enable_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_np_loaded_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_np_loaded_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_loopback_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_loopback_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_adp_sw_rstn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_adp_sw_rstn_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_power_on_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_power_on_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_main_reset_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_main_reset_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_an_enable_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_an_enable_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_rem_phy_lpbk_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_rem_phy_lpbk_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_reg4_ch_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_reg4_ch_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_np_loaded_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_np_loaded_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_force_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_force_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_restart_an_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_restart_an_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_loopback_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_loopback_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_rem_phy_lpbk_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_rem_phy_lpbk_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_adp_sw_rstn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_adp_sw_rstn_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_main_reset_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_main_reset_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_loopback_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_loopback_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_restart_an_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_restart_an_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_np_loaded_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_np_loaded_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_force_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_force_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_an_enable_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_an_enable_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_power_on_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_power_on_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_reg4_ch_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_reg4_ch_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_main_reset_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_main_reset_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_np_loaded_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_np_loaded_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_adp_sw_rstn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_adp_sw_rstn_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_power_on_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_power_on_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_an_enable_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_an_enable_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_reg4_ch_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_reg4_ch_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_restart_an_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_restart_an_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_rem_phy_lpbk_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_rem_phy_lpbk_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_force_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_force_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_loopback_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_loopback_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_loopback_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_loopback_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_reg4_ch_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_reg4_ch_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_restart_an_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_restart_an_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_an_enable_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_an_enable_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_force_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_force_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_main_reset_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_main_reset_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_power_on_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_power_on_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_rem_phy_lpbk_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_rem_phy_lpbk_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_np_loaded_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_np_loaded_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_adp_sw_rstn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_adp_sw_rstn_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_plu_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_plu_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_prbs31abl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_prbs31abl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_rpcs_bklk_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_rpcs_bklk_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_prcs_hiber_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_prcs_hiber_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_prbs9abl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_prbs9abl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_vr_rst_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_vr_rst_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_usra_rst_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_usra_rst_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_en_2_5g_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_en_2_5g_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_dskbyp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_dskbyp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_en_vsmmd1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_en_vsmmd1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_init_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_init_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_cl37_bp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_cl37_bp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_pwrsv_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_pwrsv_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_3_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_3_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_usxg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_usxg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_r2tlbe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_r2tlbe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_cr_cjn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_cr_cjn_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_byp_pwrup_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_byp_pwrup_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_sr_mii_ctrl_lpm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_sr_mii_ctrl_lpm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_sr_mii_ctrl_duplex_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_sr_mii_ctrl_duplex_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_sr_mii_ctrl_ss6_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_sr_mii_ctrl_ss6_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_sr_mii_ctrl_ss5_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_sr_mii_ctrl_ss5_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_sr_mii_ctrl_ss13_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_sr_mii_ctrl_ss13_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_sr_mii_ctrl_an_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_sr_mii_ctrl_an_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_sr_mii_ctrl_restart_an_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_sr_mii_ctrl_restart_an_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_sr_mii_ctrl_rst_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_sr_mii_ctrl_rst_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_sr_mii_ctrl_lbe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_sr_mii_ctrl_lbe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_mii_an_ctrl_pcs_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_mii_an_ctrl_pcs_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_mii_an_ctrl_mii_an_intr_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_mii_an_ctrl_mii_an_intr_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_mii_an_ctrl_sgmii_link_sts_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_mii_an_ctrl_sgmii_link_sts_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_mii_an_ctrl_tx_config_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_mii_an_ctrl_tx_config_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_mii_an_ctrl_mii_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_mii_an_ctrl_mii_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_usxg_an_sts_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_usxg_an_sts_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_cl37_ansgm_sts_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_cl37_ansgm_sts_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_cl37_ancmplt_intr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_cl37_ancmplt_intr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_pll_control_vco_related_selection_u *value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_pll_control_vco_related_selection_u *value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_tx_ac_jtag_mux_driver_selection_u *value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_tx_ac_jtag_mux_driver_selection_u *value);
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_resistor_calibration_1_u *value);
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_resistor_calibration_1_u *value);
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_pll_vco_related_control_1_u *value);
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_pll_vco_related_control_1_u *value);
+
+sw_error_t
+hppe_uniphy_rx_afe_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_rx_afe_2_u *value);
+
+sw_error_t
+hppe_uniphy_rx_afe_2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_rx_afe_2_u *value);
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union bandgap_ip_mbias_2_u *value);
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union bandgap_ip_mbias_2_u *value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ldo_0p9v_related_1_u *value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ldo_0p9v_related_1_u *value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union otp_vtt_ldo_related_u *value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union otp_vtt_ldo_related_u *value);
+
+sw_error_t
+hppe_otp_temperature_compensate_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union otp_temperature_compensate_1_u *value);
+
+sw_error_t
+hppe_otp_temperature_compensate_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union otp_temperature_compensate_1_u *value);
+
+sw_error_t
+hppe_pll_vco_related_control_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pll_vco_related_control_1_u *value);
+
+sw_error_t
+hppe_pll_vco_related_control_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pll_vco_related_control_1_u *value);
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pll_control_vco_related_selection_2_u *value);
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pll_control_vco_related_selection_2_u *value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_gain_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_gain_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_temp_cmp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_temp_cmp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_c2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_c2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_amp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_amp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_dc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_dc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_cp_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_cp_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_res_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_res_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_vcm_delta_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_vcm_delta_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lsb_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lsb_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lvl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lvl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_acjtag_beacon_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_acjtag_beacon_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_txd_bit_width_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_txd_bit_width_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_rescal_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_rescal_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_amp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_amp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_disable_load_res_txrx_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_disable_load_res_txrx_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_tx_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_tx_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_rx_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_rx_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_vref_lvl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_vref_lvl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_uphy_pll_lckdt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_uphy_pll_lckdt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_autoload_sel_pll_vco_calib_ready_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_autoload_sel_pll_vco_calib_ready_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_calib_ready_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_calib_ready_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_temp_cmp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_temp_cmp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_amp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_amp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_gain_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_gain_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_res1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_res1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_cap1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_cap1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_rescal_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_rescal_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_mbias_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_mbias_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_icc_rescode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_icc_rescode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_bg_rsv_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_bg_rsv_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_load_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_load_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_res_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_res_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_vout_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_vout_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_current_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_current_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_vtt_ldo_biasgen_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_vtt_ldo_biasgen_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_comp_current_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_comp_current_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_bias_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_bias_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_ana_isolation_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_ana_isolation_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_bias_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_bias_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_rsv_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_rsv_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_current_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_current_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_int_load_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_int_load_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_cmn_pll_ictat100u_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_cmn_pll_ictat100u_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_calib_ready_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_calib_ready_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_temp_cmp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_temp_cmp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_cmn_pll_lckdt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_cmn_pll_lckdt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_amp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_amp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_autoload_sel_pll_vco_calib_ready_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_autoload_sel_pll_vco_calib_ready_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_ready_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_ready_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_temp_cmp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_temp_cmp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_amp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_amp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_start_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_start_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_fbclk_div_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_fbclk_div_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_uniphy_phy_mode_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_misc2_phy_mode_u *value);
+
+sw_error_t
+hppe_uniphy_phy_mode_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_misc2_phy_mode_u *value);
+
+sw_error_t
+hppe_uniphy_pll_reset_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pll_power_on_and_reset_u *value);
+
+sw_error_t
+hppe_uniphy_pll_reset_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pll_power_on_and_reset_u *value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_uniphy_reg.h b/qca-ssdk/include/hsl/hppe/hppe_uniphy_reg.h
new file mode 100755
index 0000000..773a3fe
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_uniphy_reg.h
@@ -0,0 +1,1594 @@
+/*
+ * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_UNIPHY_REG_H
+#define HPPE_UNIPHY_REG_H
+
+/*[register] UNIPHY_OFFSET_CALIB_4*/
+#define UNIPHY_OFFSET_CALIB_4
+#define UNIPHY_OFFSET_CALIB_4_ADDRESS 0x1e0
+#define UNIPHY_OFFSET_CALIB_4_NUM     3
+#define UNIPHY_OFFSET_CALIB_4_INC     0x1
+#define UNIPHY_OFFSET_CALIB_4_TYPE    REG_TYPE_RW
+#define UNIPHY_OFFSET_CALIB_4_DEFAULT 0x0
+	/*[field] MMD1_REG_SMPL_CAL_READY*/
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_SMPL_CAL_READY
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_SMPL_CAL_READY_OFFSET  0
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_SMPL_CAL_READY_LEN     1
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_SMPL_CAL_READY_DEFAULT 0x0
+	/*[field] MMD1_REG_CLR_SAMPLER_CALIB_TIMEOUT*/
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CLR_SAMPLER_CALIB_TIMEOUT
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CLR_SAMPLER_CALIB_TIMEOUT_OFFSET  1
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CLR_SAMPLER_CALIB_TIMEOUT_LEN     1
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CLR_SAMPLER_CALIB_TIMEOUT_DEFAULT 0x0
+	/*[field] MMD1_REG_LOCKDET_LCKDT_REG*/
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_LOCKDET_LCKDT_REG
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_LOCKDET_LCKDT_REG_OFFSET  4
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_LOCKDET_LCKDT_REG_LEN     1
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_LOCKDET_LCKDT_REG_DEFAULT 0x0
+	/*[field] MMD1_REG_PLL_LOCKED_REG*/
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_PLL_LOCKED_REG
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_PLL_LOCKED_REG_OFFSET  6
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_PLL_LOCKED_REG_LEN     1
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_PLL_LOCKED_REG_DEFAULT 0x0
+	/*[field] MMD1_REG_CALIBRATION_DONE_REG*/
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CALIBRATION_DONE_REG
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CALIBRATION_DONE_REG_OFFSET  7
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CALIBRATION_DONE_REG_LEN     1
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CALIBRATION_DONE_REG_DEFAULT 0x0
+	/*[field] MMD1_REG_CAL_DETECT_TIME*/
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_DETECT_TIME
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_DETECT_TIME_OFFSET  8
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_DETECT_TIME_LEN     5
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_DETECT_TIME_DEFAULT 0x0
+	/*[field] MMD1_REG_CAL_REP_TIME*/
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_REP_TIME
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_REP_TIME_OFFSET  13
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_REP_TIME_LEN     3
+	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_REP_TIME_DEFAULT 0x0
+
+struct uniphy_offset_calib_4 {
+	a_uint32_t  mmd1_reg_smpl_cal_ready:1;
+	a_uint32_t  mmd1_reg_clr_sampler_calib_timeout:1;
+	a_uint32_t  _reserved0:2;
+	a_uint32_t  mmd1_reg_lockdet_lckdt_reg:1;
+	a_uint32_t  _reserved1:1;
+	a_uint32_t  mmd1_reg_pll_locked_reg:1;
+	a_uint32_t  mmd1_reg_calibration_done_reg:1;
+	a_uint32_t  mmd1_reg_cal_detect_time:5;
+	a_uint32_t  mmd1_reg_cal_rep_time:3;
+	a_uint32_t  _reserved2:16;
+};
+
+union uniphy_offset_calib_4_u {
+	a_uint32_t val;
+	struct uniphy_offset_calib_4 bf;
+};
+
+/*[register] UNIPHY_MODE_CTRL*/
+#define UNIPHY_MODE_CTRL
+#define UNIPHY_MODE_CTRL_ADDRESS 0x46c
+#define UNIPHY_MODE_CTRL_NUM     3
+#define UNIPHY_MODE_CTRL_INC     0x1
+#define UNIPHY_MODE_CTRL_TYPE    REG_TYPE_RW
+#define UNIPHY_MODE_CTRL_DEFAULT 0x221
+	/*[field] NEWADDEDFROMHERE_CH0_AUTONEG_MODE*/
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE_OFFSET  0
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE_LEN     1
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE_DEFAULT 0x1
+	/*[field] NEWADDEDFROMHERE_CH1_CH0_SGMII*/
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH1_CH0_SGMII
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH1_CH0_SGMII_OFFSET  1
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH1_CH0_SGMII_LEN     1
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH1_CH0_SGMII_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH4_CH1_0_SGMII*/
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH4_CH1_0_SGMII
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH4_CH1_0_SGMII_OFFSET  2
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH4_CH1_0_SGMII_LEN     1
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH4_CH1_0_SGMII_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_SGMII_EVEN_LOW*/
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGMII_EVEN_LOW
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGMII_EVEN_LOW_OFFSET  3
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGMII_EVEN_LOW_LEN     1
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGMII_EVEN_LOW_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH0_MODE_CTRL_25M*/
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_MODE_CTRL_25M
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_MODE_CTRL_25M_OFFSET  4
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_MODE_CTRL_25M_LEN     3
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_MODE_CTRL_25M_DEFAULT 0x2
+	/*[field] NEWADDEDFROMHERE_CH0_QSGMII_SGMII*/
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_QSGMII_SGMII
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_QSGMII_SGMII_OFFSET  8
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_QSGMII_SGMII_LEN     1
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_QSGMII_SGMII_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH0_PSGMII_QSGMII*/
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_PSGMII_QSGMII
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_PSGMII_QSGMII_OFFSET  9
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_PSGMII_QSGMII_LEN     1
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_PSGMII_QSGMII_DEFAULT 0x1
+	/*[field] NEWADDEDFROMHERE_SG_MODE*/
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SG_MODE
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SG_MODE_OFFSET  10
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SG_MODE_LEN     1
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SG_MODE_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_SGPLUS_MODE*/
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGPLUS_MODE
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGPLUS_MODE_OFFSET  11
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGPLUS_MODE_LEN     1
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGPLUS_MODE_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_XPCS_MODE*/
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_XPCS_MODE
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_XPCS_MODE_OFFSET  12
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_XPCS_MODE_LEN     1
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_XPCS_MODE_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_USXG_EN*/
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_USXG_EN
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_USXG_EN_OFFSET  13
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_USXG_EN_LEN     1
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_USXG_EN_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_SW_V17_V18*/
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SW_V17_V18
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SW_V17_V18_OFFSET  15
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SW_V17_V18_LEN     1
+	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SW_V17_V18_DEFAULT 0x0
+
+struct uniphy_mode_ctrl {
+	a_uint32_t  newaddedfromhere_ch0_autoneg_mode:1;
+	a_uint32_t  newaddedfromhere_ch1_ch0_sgmii:1;
+	a_uint32_t  newaddedfromhere_ch4_ch1_0_sgmii:1;
+	a_uint32_t  newaddedfromhere_sgmii_even_low:1;
+	a_uint32_t  newaddedfromhere_ch0_mode_ctrl_25m:3;
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  newaddedfromhere_ch0_qsgmii_sgmii:1;
+	a_uint32_t  newaddedfromhere_ch0_psgmii_qsgmii:1;
+	a_uint32_t  newaddedfromhere_sg_mode:1;
+	a_uint32_t  newaddedfromhere_sgplus_mode:1;
+	a_uint32_t  newaddedfromhere_xpcs_mode:1;
+	a_uint32_t  newaddedfromhere_usxg_en:1;
+	a_uint32_t  _reserved1:1;
+	a_uint32_t  newaddedfromhere_sw_v17_v18:1;
+	a_uint32_t  _reserved2:16;
+};
+
+union uniphy_mode_ctrl_u {
+	a_uint32_t val;
+	struct uniphy_mode_ctrl bf;
+};
+
+/*[register] UNIPHY_CHANNEL0_INPUT_OUTPUT_4*/
+#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4
+#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_ADDRESS 0x480
+#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NUM     3
+#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_INC     0x1
+#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_TYPE    REG_TYPE_RW
+#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_DEFAULT 0x844
+	/*[field] NEWADDEDFROMHERE_CH0_REM_PHY_LPBK*/
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_REM_PHY_LPBK
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_REM_PHY_LPBK_OFFSET  0
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_REM_PHY_LPBK_LEN     1
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_REM_PHY_LPBK_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH0_SPEED_25M*/
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_SPEED_25M
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_SPEED_25M_OFFSET  1
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_SPEED_25M_LEN     2
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_SPEED_25M_DEFAULT 0x2
+	/*[field] NEWADDEDFROMHERE_CH0_FORCE_SPEED_25M*/
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_FORCE_SPEED_25M
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_FORCE_SPEED_25M_OFFSET  3
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_FORCE_SPEED_25M_LEN     1
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_FORCE_SPEED_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH0_MR_NP_LOADED_25M*/
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_NP_LOADED_25M
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_NP_LOADED_25M_OFFSET  4
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_NP_LOADED_25M_LEN     1
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_NP_LOADED_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH0_MR_REG4_CH_25M*/
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_REG4_CH_25M
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_REG4_CH_25M_OFFSET  5
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_REG4_CH_25M_LEN     1
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_REG4_CH_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH0_MR_AN_ENABLE_25M*/
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_AN_ENABLE_25M
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_AN_ENABLE_25M_OFFSET  6
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_AN_ENABLE_25M_LEN     1
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_AN_ENABLE_25M_DEFAULT 0x1
+	/*[field] NEWADDEDFROMHERE_CH0_MR_RESTART_AN_25M*/
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_RESTART_AN_25M
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_RESTART_AN_25M_OFFSET  7
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_RESTART_AN_25M_LEN     1
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_RESTART_AN_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH0_MR_LOOPBACK_25M*/
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_LOOPBACK_25M
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_LOOPBACK_25M_OFFSET  8
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_LOOPBACK_25M_LEN     1
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_LOOPBACK_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH0_MR_MAIN_RESET_25M*/
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_MAIN_RESET_25M
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_MAIN_RESET_25M_OFFSET  9
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_MAIN_RESET_25M_LEN     1
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_MAIN_RESET_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH0_POWER_ON_25M*/
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_POWER_ON_25M
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_POWER_ON_25M_OFFSET  10
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_POWER_ON_25M_LEN     1
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_POWER_ON_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH0_ADP_SW_RSTN*/
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_ADP_SW_RSTN
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_ADP_SW_RSTN_OFFSET  11
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_ADP_SW_RSTN_LEN     1
+	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_ADP_SW_RSTN_DEFAULT 0x1
+
+struct uniphy_channel0_input_output_4 {
+	a_uint32_t  newaddedfromhere_ch0_rem_phy_lpbk:1;
+	a_uint32_t  newaddedfromhere_ch0_speed_25m:2;
+	a_uint32_t  newaddedfromhere_ch0_force_speed_25m:1;
+	a_uint32_t  newaddedfromhere_ch0_mr_np_loaded_25m:1;
+	a_uint32_t  newaddedfromhere_ch0_mr_reg4_ch_25m:1;
+	a_uint32_t  newaddedfromhere_ch0_mr_an_enable_25m:1;
+	a_uint32_t  newaddedfromhere_ch0_mr_restart_an_25m:1;
+	a_uint32_t  newaddedfromhere_ch0_mr_loopback_25m:1;
+	a_uint32_t  newaddedfromhere_ch0_mr_main_reset_25m:1;
+	a_uint32_t  newaddedfromhere_ch0_power_on_25m:1;
+	a_uint32_t  newaddedfromhere_ch0_adp_sw_rstn:1;
+	a_uint32_t  _reserved0:20;
+};
+
+union uniphy_channel0_input_output_4_u {
+	a_uint32_t val;
+	struct uniphy_channel0_input_output_4 bf;
+};
+
+/*[register] UNIPHY_CHANNEL1_INPUT_OUTPUT_4*/
+#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4
+#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_ADDRESS 0x498
+#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NUM     3
+#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_INC     0x1
+#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_TYPE    REG_TYPE_RW
+#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_DEFAULT 0x844
+	/*[field] NEWADDEDFROMHERE_CH1_REM_PHY_LPBK*/
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_REM_PHY_LPBK
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_REM_PHY_LPBK_OFFSET  0
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_REM_PHY_LPBK_LEN     1
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_REM_PHY_LPBK_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH1_SPEED_25M*/
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_SPEED_25M
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_SPEED_25M_OFFSET  1
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_SPEED_25M_LEN     2
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_SPEED_25M_DEFAULT 0x2
+	/*[field] NEWADDEDFROMHERE_CH1_FORCE_SPEED_25M*/
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_FORCE_SPEED_25M
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_FORCE_SPEED_25M_OFFSET  3
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_FORCE_SPEED_25M_LEN     1
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_FORCE_SPEED_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH1_MR_NP_LOADED_25M*/
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_NP_LOADED_25M
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_NP_LOADED_25M_OFFSET  4
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_NP_LOADED_25M_LEN     1
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_NP_LOADED_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH1_MR_REG4_CH_25M*/
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_REG4_CH_25M
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_REG4_CH_25M_OFFSET  5
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_REG4_CH_25M_LEN     1
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_REG4_CH_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH1_MR_AN_ENABLE_25M*/
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_AN_ENABLE_25M
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_AN_ENABLE_25M_OFFSET  6
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_AN_ENABLE_25M_LEN     1
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_AN_ENABLE_25M_DEFAULT 0x1
+	/*[field] NEWADDEDFROMHERE_CH1_MR_RESTART_AN_25M*/
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_RESTART_AN_25M
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_RESTART_AN_25M_OFFSET  7
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_RESTART_AN_25M_LEN     1
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_RESTART_AN_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH1_MR_LOOPBACK_25M*/
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_LOOPBACK_25M
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_LOOPBACK_25M_OFFSET  8
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_LOOPBACK_25M_LEN     1
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_LOOPBACK_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH1_MR_MAIN_RESET_25M*/
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_MAIN_RESET_25M
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_MAIN_RESET_25M_OFFSET  9
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_MAIN_RESET_25M_LEN     1
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_MAIN_RESET_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH1_POWER_ON_25M*/
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_POWER_ON_25M
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_POWER_ON_25M_OFFSET  10
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_POWER_ON_25M_LEN     1
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_POWER_ON_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH1_ADP_SW_RSTN*/
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_ADP_SW_RSTN
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_ADP_SW_RSTN_OFFSET  11
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_ADP_SW_RSTN_LEN     1
+	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_ADP_SW_RSTN_DEFAULT 0x1
+
+struct uniphy_channel1_input_output_4 {
+	a_uint32_t  newaddedfromhere_ch1_rem_phy_lpbk:1;
+	a_uint32_t  newaddedfromhere_ch1_speed_25m:2;
+	a_uint32_t  newaddedfromhere_ch1_force_speed_25m:1;
+	a_uint32_t  newaddedfromhere_ch1_mr_np_loaded_25m:1;
+	a_uint32_t  newaddedfromhere_ch1_mr_reg4_ch_25m:1;
+	a_uint32_t  newaddedfromhere_ch1_mr_an_enable_25m:1;
+	a_uint32_t  newaddedfromhere_ch1_mr_restart_an_25m:1;
+	a_uint32_t  newaddedfromhere_ch1_mr_loopback_25m:1;
+	a_uint32_t  newaddedfromhere_ch1_mr_main_reset_25m:1;
+	a_uint32_t  newaddedfromhere_ch1_power_on_25m:1;
+	a_uint32_t  newaddedfromhere_ch1_adp_sw_rstn:1;
+	a_uint32_t  _reserved0:20;
+};
+
+union uniphy_channel1_input_output_4_u {
+	a_uint32_t val;
+	struct uniphy_channel1_input_output_4 bf;
+};
+
+/*[register] UNIPHY_CHANNEL2_INPUT_OUTPUT_4*/
+#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4
+#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_ADDRESS 0x4b0
+#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NUM     3
+#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_INC     0x1
+#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_TYPE    REG_TYPE_RW
+#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_DEFAULT 0x844
+	/*[field] NEWADDEDFROMHERE_CH2_REM_PHY_LPBK*/
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_REM_PHY_LPBK
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_REM_PHY_LPBK_OFFSET  0
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_REM_PHY_LPBK_LEN     1
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_REM_PHY_LPBK_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH2_SPEED_25M*/
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_SPEED_25M
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_SPEED_25M_OFFSET  1
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_SPEED_25M_LEN     2
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_SPEED_25M_DEFAULT 0x2
+	/*[field] NEWADDEDFROMHERE_CH2_FORCE_SPEED_25M*/
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_FORCE_SPEED_25M
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_FORCE_SPEED_25M_OFFSET  3
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_FORCE_SPEED_25M_LEN     1
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_FORCE_SPEED_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH2_MR_NP_LOADED_25M*/
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_NP_LOADED_25M
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_NP_LOADED_25M_OFFSET  4
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_NP_LOADED_25M_LEN     1
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_NP_LOADED_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH2_MR_REG4_CH_25M*/
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_REG4_CH_25M
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_REG4_CH_25M_OFFSET  5
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_REG4_CH_25M_LEN     1
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_REG4_CH_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH2_MR_AN_ENABLE_25M*/
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_AN_ENABLE_25M
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_AN_ENABLE_25M_OFFSET  6
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_AN_ENABLE_25M_LEN     1
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_AN_ENABLE_25M_DEFAULT 0x1
+	/*[field] NEWADDEDFROMHERE_CH2_MR_RESTART_AN_25M*/
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_RESTART_AN_25M
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_RESTART_AN_25M_OFFSET  7
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_RESTART_AN_25M_LEN     1
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_RESTART_AN_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH2_MR_LOOPBACK_25M*/
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_LOOPBACK_25M
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_LOOPBACK_25M_OFFSET  8
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_LOOPBACK_25M_LEN     1
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_LOOPBACK_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH2_MR_MAIN_RESET_25M*/
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_MAIN_RESET_25M
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_MAIN_RESET_25M_OFFSET  9
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_MAIN_RESET_25M_LEN     1
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_MAIN_RESET_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH2_POWER_ON_25M*/
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_POWER_ON_25M
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_POWER_ON_25M_OFFSET  10
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_POWER_ON_25M_LEN     1
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_POWER_ON_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH2_ADP_SW_RSTN*/
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_ADP_SW_RSTN
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_ADP_SW_RSTN_OFFSET  11
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_ADP_SW_RSTN_LEN     1
+	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_ADP_SW_RSTN_DEFAULT 0x1
+
+struct uniphy_channel2_input_output_4 {
+	a_uint32_t  newaddedfromhere_ch2_rem_phy_lpbk:1;
+	a_uint32_t  newaddedfromhere_ch2_speed_25m:2;
+	a_uint32_t  newaddedfromhere_ch2_force_speed_25m:1;
+	a_uint32_t  newaddedfromhere_ch2_mr_np_loaded_25m:1;
+	a_uint32_t  newaddedfromhere_ch2_mr_reg4_ch_25m:1;
+	a_uint32_t  newaddedfromhere_ch2_mr_an_enable_25m:1;
+	a_uint32_t  newaddedfromhere_ch2_mr_restart_an_25m:1;
+	a_uint32_t  newaddedfromhere_ch2_mr_loopback_25m:1;
+	a_uint32_t  newaddedfromhere_ch2_mr_main_reset_25m:1;
+	a_uint32_t  newaddedfromhere_ch2_power_on_25m:1;
+	a_uint32_t  newaddedfromhere_ch2_adp_sw_rstn:1;
+	a_uint32_t  _reserved0:20;
+};
+
+union uniphy_channel2_input_output_4_u {
+	a_uint32_t val;
+	struct uniphy_channel2_input_output_4 bf;
+};
+
+/*[register] UNIPHY_CHANNEL3_INPUT_OUTPUT_4*/
+#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4
+#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_ADDRESS 0x4c8
+#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NUM     3
+#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_INC     0x1
+#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_TYPE    REG_TYPE_RW
+#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_DEFAULT 0x844
+	/*[field] NEWADDEDFROMHERE_CH3_REM_PHY_LPBK*/
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_REM_PHY_LPBK
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_REM_PHY_LPBK_OFFSET  0
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_REM_PHY_LPBK_LEN     1
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_REM_PHY_LPBK_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH3_SPEED_25M*/
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_SPEED_25M
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_SPEED_25M_OFFSET  1
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_SPEED_25M_LEN     2
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_SPEED_25M_DEFAULT 0x2
+	/*[field] NEWADDEDFROMHERE_CH3_FORCE_SPEED_25M*/
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_FORCE_SPEED_25M
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_FORCE_SPEED_25M_OFFSET  3
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_FORCE_SPEED_25M_LEN     1
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_FORCE_SPEED_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH3_MR_NP_LOADED_25M*/
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_NP_LOADED_25M
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_NP_LOADED_25M_OFFSET  4
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_NP_LOADED_25M_LEN     1
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_NP_LOADED_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH3_MR_REG4_CH_25M*/
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_REG4_CH_25M
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_REG4_CH_25M_OFFSET  5
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_REG4_CH_25M_LEN     1
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_REG4_CH_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH3_MR_AN_ENABLE_25M*/
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_AN_ENABLE_25M
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_AN_ENABLE_25M_OFFSET  6
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_AN_ENABLE_25M_LEN     1
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_AN_ENABLE_25M_DEFAULT 0x1
+	/*[field] NEWADDEDFROMHERE_CH3_MR_RESTART_AN_25M*/
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_RESTART_AN_25M
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_RESTART_AN_25M_OFFSET  7
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_RESTART_AN_25M_LEN     1
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_RESTART_AN_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH3_MR_LOOPBACK_25M*/
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_LOOPBACK_25M
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_LOOPBACK_25M_OFFSET  8
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_LOOPBACK_25M_LEN     1
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_LOOPBACK_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH3_MR_MAIN_RESET_25M*/
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_MAIN_RESET_25M
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_MAIN_RESET_25M_OFFSET  9
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_MAIN_RESET_25M_LEN     1
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_MAIN_RESET_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH3_POWER_ON_25M*/
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_POWER_ON_25M
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_POWER_ON_25M_OFFSET  10
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_POWER_ON_25M_LEN     1
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_POWER_ON_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH3_ADP_SW_RSTN*/
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_ADP_SW_RSTN
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_ADP_SW_RSTN_OFFSET  11
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_ADP_SW_RSTN_LEN     1
+	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_ADP_SW_RSTN_DEFAULT 0x1
+
+struct uniphy_channel3_input_output_4 {
+	a_uint32_t  newaddedfromhere_ch3_rem_phy_lpbk:1;
+	a_uint32_t  newaddedfromhere_ch3_speed_25m:2;
+	a_uint32_t  newaddedfromhere_ch3_force_speed_25m:1;
+	a_uint32_t  newaddedfromhere_ch3_mr_np_loaded_25m:1;
+	a_uint32_t  newaddedfromhere_ch3_mr_reg4_ch_25m:1;
+	a_uint32_t  newaddedfromhere_ch3_mr_an_enable_25m:1;
+	a_uint32_t  newaddedfromhere_ch3_mr_restart_an_25m:1;
+	a_uint32_t  newaddedfromhere_ch3_mr_loopback_25m:1;
+	a_uint32_t  newaddedfromhere_ch3_mr_main_reset_25m:1;
+	a_uint32_t  newaddedfromhere_ch3_power_on_25m:1;
+	a_uint32_t  newaddedfromhere_ch3_adp_sw_rstn:1;
+	a_uint32_t  _reserved0:20;
+};
+
+union uniphy_channel3_input_output_4_u {
+	a_uint32_t val;
+	struct uniphy_channel3_input_output_4 bf;
+};
+
+/*[register] UNIPHY_CHANNEL4_INPUT_OUTPUT_4*/
+#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4
+#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_ADDRESS 0x4e0
+#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NUM     3
+#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_INC     0x1
+#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_TYPE    REG_TYPE_RW
+#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_DEFAULT 0x844
+	/*[field] NEWADDEDFROMHERE_CH4_REM_PHY_LPBK*/
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_REM_PHY_LPBK
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_REM_PHY_LPBK_OFFSET  0
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_REM_PHY_LPBK_LEN     1
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_REM_PHY_LPBK_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH4_SPEED_25M*/
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_SPEED_25M
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_SPEED_25M_OFFSET  1
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_SPEED_25M_LEN     2
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_SPEED_25M_DEFAULT 0x2
+	/*[field] NEWADDEDFROMHERE_CH4_FORCE_SPEED_25M*/
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_FORCE_SPEED_25M
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_FORCE_SPEED_25M_OFFSET  3
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_FORCE_SPEED_25M_LEN     1
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_FORCE_SPEED_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH4_MR_NP_LOADED_25M*/
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_NP_LOADED_25M
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_NP_LOADED_25M_OFFSET  4
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_NP_LOADED_25M_LEN     1
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_NP_LOADED_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH4_MR_REG4_CH_25M*/
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_REG4_CH_25M
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_REG4_CH_25M_OFFSET  5
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_REG4_CH_25M_LEN     1
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_REG4_CH_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH4_MR_AN_ENABLE_25M*/
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_AN_ENABLE_25M
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_AN_ENABLE_25M_OFFSET  6
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_AN_ENABLE_25M_LEN     1
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_AN_ENABLE_25M_DEFAULT 0x1
+	/*[field] NEWADDEDFROMHERE_CH4_MR_RESTART_AN_25M*/
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_RESTART_AN_25M
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_RESTART_AN_25M_OFFSET  7
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_RESTART_AN_25M_LEN     1
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_RESTART_AN_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH4_MR_LOOPBACK_25M*/
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_LOOPBACK_25M
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_LOOPBACK_25M_OFFSET  8
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_LOOPBACK_25M_LEN     1
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_LOOPBACK_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH4_MR_MAIN_RESET_25M*/
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_MAIN_RESET_25M
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_MAIN_RESET_25M_OFFSET  9
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_MAIN_RESET_25M_LEN     1
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_MAIN_RESET_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH4_POWER_ON_25M*/
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_POWER_ON_25M
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_POWER_ON_25M_OFFSET  10
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_POWER_ON_25M_LEN     1
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_POWER_ON_25M_DEFAULT 0x0
+	/*[field] NEWADDEDFROMHERE_CH4_ADP_SW_RSTN*/
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_ADP_SW_RSTN
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_ADP_SW_RSTN_OFFSET  11
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_ADP_SW_RSTN_LEN     1
+	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_ADP_SW_RSTN_DEFAULT 0x1
+
+struct uniphy_channel4_input_output_4 {
+	a_uint32_t  newaddedfromhere_ch4_rem_phy_lpbk:1;
+	a_uint32_t  newaddedfromhere_ch4_speed_25m:2;
+	a_uint32_t  newaddedfromhere_ch4_force_speed_25m:1;
+	a_uint32_t  newaddedfromhere_ch4_mr_np_loaded_25m:1;
+	a_uint32_t  newaddedfromhere_ch4_mr_reg4_ch_25m:1;
+	a_uint32_t  newaddedfromhere_ch4_mr_an_enable_25m:1;
+	a_uint32_t  newaddedfromhere_ch4_mr_restart_an_25m:1;
+	a_uint32_t  newaddedfromhere_ch4_mr_loopback_25m:1;
+	a_uint32_t  newaddedfromhere_ch4_mr_main_reset_25m:1;
+	a_uint32_t  newaddedfromhere_ch4_power_on_25m:1;
+	a_uint32_t  newaddedfromhere_ch4_adp_sw_rstn:1;
+	a_uint32_t  _reserved0:20;
+};
+
+union uniphy_channel4_input_output_4_u {
+	a_uint32_t val;
+	struct uniphy_channel4_input_output_4 bf;
+};
+
+/*[register] UNIPHY_INSTANCE_LINK_DETECT*/
+#define UNIPHY_INSTANCE_LINK_DETECT
+#define UNIPHY_INSTANCE_LINK_DETECT_ADDRESS 0x570
+#define UNIPHY_INSTANCE_LINK_DETECT_NUM     3
+#define UNIPHY_INSTANCE_LINK_DETECT_INC     0x1
+#define UNIPHY_INSTANCE_LINK_DETECT_TYPE    REG_TYPE_RW
+#define UNIPHY_INSTANCE_LINK_DETECT_DEFAULT 0x0
+
+struct uniphy_instance_link_detect {
+	a_uint32_t  _reserved0:6;
+	a_uint32_t  detect_los_from_sfp:3;
+	a_uint32_t  _reserved1:23;
+};
+
+union uniphy_instance_link_detect_u {
+	a_uint32_t val;
+	struct uniphy_instance_link_detect  bf;
+};
+
+/*[register] SR_XS_PCS_KR_STS1*/
+#define SR_XS_PCS_KR_STS1
+#define SR_XS_PCS_KR_STS1_ADDRESS 0x30020
+#define SR_XS_PCS_KR_STS1_NUM     3
+#define SR_XS_PCS_KR_STS1_INC     0x1
+#define SR_XS_PCS_KR_STS1_TYPE    REG_TYPE_RW
+#define SR_XS_PCS_KR_STS1_DEFAULT 0x0
+	/*[field] RPCS_BKLK*/
+	#define SR_XS_PCS_KR_STS1_RPCS_BKLK
+	#define SR_XS_PCS_KR_STS1_RPCS_BKLK_OFFSET  0
+	#define SR_XS_PCS_KR_STS1_RPCS_BKLK_LEN     1
+	#define SR_XS_PCS_KR_STS1_RPCS_BKLK_DEFAULT 0x0
+	/*[field] PRCS_HIBER*/
+	#define SR_XS_PCS_KR_STS1_PRCS_HIBER
+	#define SR_XS_PCS_KR_STS1_PRCS_HIBER_OFFSET  1
+	#define SR_XS_PCS_KR_STS1_PRCS_HIBER_LEN     1
+	#define SR_XS_PCS_KR_STS1_PRCS_HIBER_DEFAULT 0x0
+	/*[field] PRBS31ABL*/
+	#define SR_XS_PCS_KR_STS1_PRBS31ABL
+	#define SR_XS_PCS_KR_STS1_PRBS31ABL_OFFSET  2
+	#define SR_XS_PCS_KR_STS1_PRBS31ABL_LEN     1
+	#define SR_XS_PCS_KR_STS1_PRBS31ABL_DEFAULT 0x0
+	/*[field] PRBS9ABL*/
+	#define SR_XS_PCS_KR_STS1_PRBS9ABL
+	#define SR_XS_PCS_KR_STS1_PRBS9ABL_OFFSET  3
+	#define SR_XS_PCS_KR_STS1_PRBS9ABL_LEN     1
+	#define SR_XS_PCS_KR_STS1_PRBS9ABL_DEFAULT 0x0
+	/*[field] PLU*/
+	#define SR_XS_PCS_KR_STS1_PLU
+	#define SR_XS_PCS_KR_STS1_PLU_OFFSET  12
+	#define SR_XS_PCS_KR_STS1_PLU_LEN     1
+	#define SR_XS_PCS_KR_STS1_PLU_DEFAULT 0x0
+
+struct sr_xs_pcs_kr_sts1 {
+	a_uint32_t  rpcs_bklk:1;
+	a_uint32_t  prcs_hiber:1;
+	a_uint32_t  prbs31abl:1;
+	a_uint32_t  prbs9abl:1;
+	a_uint32_t  _reserved0:8;
+	a_uint32_t  plu:1;
+	a_uint32_t  _reserved1:19;
+};
+
+union sr_xs_pcs_kr_sts1_u {
+	a_uint32_t val;
+	struct sr_xs_pcs_kr_sts1 bf;
+};
+
+/*[register] VR_XS_PCS_DIG_CTRL1*/
+#define VR_XS_PCS_DIG_CTRL1
+#define VR_XS_PCS_DIG_CTRL1_ADDRESS 0x38000
+#define VR_XS_PCS_DIG_CTRL1_NUM     3
+#define VR_XS_PCS_DIG_CTRL1_INC     0x1
+#define VR_XS_PCS_DIG_CTRL1_TYPE    REG_TYPE_RW
+#define VR_XS_PCS_DIG_CTRL1_DEFAULT 0x0
+	/*[field] DSKBYP*/
+	#define VR_XS_PCS_DIG_CTRL1_DSKBYP
+	#define VR_XS_PCS_DIG_CTRL1_DSKBYP_OFFSET  0
+	#define VR_XS_PCS_DIG_CTRL1_DSKBYP_LEN     1
+	#define VR_XS_PCS_DIG_CTRL1_DSKBYP_DEFAULT 0x0
+	/*[field] BYP_PWRUP*/
+	#define VR_XS_PCS_DIG_CTRL1_BYP_PWRUP
+	#define VR_XS_PCS_DIG_CTRL1_BYP_PWRUP_OFFSET  1
+	#define VR_XS_PCS_DIG_CTRL1_BYP_PWRUP_LEN     1
+	#define VR_XS_PCS_DIG_CTRL1_BYP_PWRUP_DEFAULT 0x0
+	/*[field] EN_2_5G_MODE*/
+	#define VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE
+	#define VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE_OFFSET  2
+	#define VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE_LEN     1
+	#define VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE_DEFAULT 0x0
+	/*[field] CR_CJN*/
+	#define VR_XS_PCS_DIG_CTRL1_CR_CJN
+	#define VR_XS_PCS_DIG_CTRL1_CR_CJN_OFFSET  3
+	#define VR_XS_PCS_DIG_CTRL1_CR_CJN_LEN     1
+	#define VR_XS_PCS_DIG_CTRL1_CR_CJN_DEFAULT 0x0
+	/*[field] DTXLANED_0*/
+	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_0
+	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_0_OFFSET  4
+	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_0_LEN     1
+	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_0_DEFAULT 0x0
+	/*[field] DTXLANED_3_1*/
+	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_3_1
+	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_3_1_OFFSET  5
+	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_3_1_LEN     3
+	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_3_1_DEFAULT 0x0
+	/*[field] INIT*/
+	#define VR_XS_PCS_DIG_CTRL1_INIT
+	#define VR_XS_PCS_DIG_CTRL1_INIT_OFFSET  8
+	#define VR_XS_PCS_DIG_CTRL1_INIT_LEN     1
+	#define VR_XS_PCS_DIG_CTRL1_INIT_DEFAULT 0x0
+	/*[field] USXG_EN*/
+	#define VR_XS_PCS_DIG_CTRL1_USXG_EN
+	#define VR_XS_PCS_DIG_CTRL1_USXG_EN_OFFSET  9
+	#define VR_XS_PCS_DIG_CTRL1_USXG_EN_LEN     1
+	#define VR_XS_PCS_DIG_CTRL1_USXG_EN_DEFAULT 0x0
+	/*[field] USRA_RST*/
+	#define VR_XS_PCS_DIG_CTRL1_USRA_RST
+	#define VR_XS_PCS_DIG_CTRL1_USRA_RST_OFFSET  10
+	#define VR_XS_PCS_DIG_CTRL1_USRA_RST_LEN     1
+	#define VR_XS_PCS_DIG_CTRL1_USRA_RST_DEFAULT 0x0
+	/*[field] PWRSV*/
+	#define VR_XS_PCS_DIG_CTRL1_PWRSV
+	#define VR_XS_PCS_DIG_CTRL1_PWRSV_OFFSET  11
+	#define VR_XS_PCS_DIG_CTRL1_PWRSV_LEN     1
+	#define VR_XS_PCS_DIG_CTRL1_PWRSV_DEFAULT 0x0
+	/*[field] CL37_BP*/
+	#define VR_XS_PCS_DIG_CTRL1_CL37_BP
+	#define VR_XS_PCS_DIG_CTRL1_CL37_BP_OFFSET  12
+	#define VR_XS_PCS_DIG_CTRL1_CL37_BP_LEN     1
+	#define VR_XS_PCS_DIG_CTRL1_CL37_BP_DEFAULT 0x0
+	/*[field] EN_VSMMD1*/
+	#define VR_XS_PCS_DIG_CTRL1_EN_VSMMD1
+	#define VR_XS_PCS_DIG_CTRL1_EN_VSMMD1_OFFSET  13
+	#define VR_XS_PCS_DIG_CTRL1_EN_VSMMD1_LEN     1
+	#define VR_XS_PCS_DIG_CTRL1_EN_VSMMD1_DEFAULT 0x0
+	/*[field] R2TLBE*/
+	#define VR_XS_PCS_DIG_CTRL1_R2TLBE
+	#define VR_XS_PCS_DIG_CTRL1_R2TLBE_OFFSET  14
+	#define VR_XS_PCS_DIG_CTRL1_R2TLBE_LEN     1
+	#define VR_XS_PCS_DIG_CTRL1_R2TLBE_DEFAULT 0x0
+	/*[field] VR_RST*/
+	#define VR_XS_PCS_DIG_CTRL1_VR_RST
+	#define VR_XS_PCS_DIG_CTRL1_VR_RST_OFFSET  15
+	#define VR_XS_PCS_DIG_CTRL1_VR_RST_LEN     1
+	#define VR_XS_PCS_DIG_CTRL1_VR_RST_DEFAULT 0x0
+
+struct vr_xs_pcs_dig_ctrl1 {
+	a_uint32_t  dskbyp:1;
+	a_uint32_t  byp_pwrup:1;
+	a_uint32_t  en_2_5g_mode:1;
+	a_uint32_t  cr_cjn:1;
+	a_uint32_t  dtxlaned_0:1;
+	a_uint32_t  dtxlaned_3_1:3;
+	a_uint32_t  init:1;
+	a_uint32_t  usxg_en:1;
+	a_uint32_t  usra_rst:1;
+	a_uint32_t  pwrsv:1;
+	a_uint32_t  cl37_bp:1;
+	a_uint32_t  en_vsmmd1:1;
+	a_uint32_t  r2tlbe:1;
+	a_uint32_t  vr_rst:1;
+	a_uint32_t  _reserved0:16;
+};
+
+union vr_xs_pcs_dig_ctrl1_u {
+	a_uint32_t val;
+	struct vr_xs_pcs_dig_ctrl1 bf;
+};
+
+/*[register] SR_MII_CTRL*/
+#define SR_MII_CTRL
+#define SR_MII_CTRL_ADDRESS 0x1f0000
+#define SR_MII_CTRL_NUM     3
+#define SR_MII_CTRL_INC     0x1
+#define SR_MII_CTRL_TYPE    REG_TYPE_RW
+#define SR_MII_CTRL_DEFAULT 0x0
+	/*[field] SS5*/
+	#define SR_MII_CTRL_SS5
+	#define SR_MII_CTRL_SS5_OFFSET  5
+	#define SR_MII_CTRL_SS5_LEN     1
+	#define SR_MII_CTRL_SS5_DEFAULT 0x0
+	/*[field] SS6*/
+	#define SR_MII_CTRL_SS6
+	#define SR_MII_CTRL_SS6_OFFSET  6
+	#define SR_MII_CTRL_SS6_LEN     1
+	#define SR_MII_CTRL_SS6_DEFAULT 0x0
+	/*[field] DUPLEX_MODE*/
+	#define SR_MII_CTRL_DUPLEX_MODE
+	#define SR_MII_CTRL_DUPLEX_MODE_OFFSET  8
+	#define SR_MII_CTRL_DUPLEX_MODE_LEN     1
+	#define SR_MII_CTRL_DUPLEX_MODE_DEFAULT 0x0
+	/*[field] RESTART_AN*/
+	#define SR_MII_CTRL_RESTART_AN
+	#define SR_MII_CTRL_RESTART_AN_OFFSET  9
+	#define SR_MII_CTRL_RESTART_AN_LEN     1
+	#define SR_MII_CTRL_RESTART_AN_DEFAULT 0x0
+	/*[field] LPM*/
+	#define SR_MII_CTRL_LPM
+	#define SR_MII_CTRL_LPM_OFFSET  11
+	#define SR_MII_CTRL_LPM_LEN     1
+	#define SR_MII_CTRL_LPM_DEFAULT 0x0
+	/*[field] AN_ENABLE*/
+	#define SR_MII_CTRL_AN_ENABLE
+	#define SR_MII_CTRL_AN_ENABLE_OFFSET  12
+	#define SR_MII_CTRL_AN_ENABLE_LEN     1
+	#define SR_MII_CTRL_AN_ENABLE_DEFAULT 0x0
+	/*[field] SS13*/
+	#define SR_MII_CTRL_SS13
+	#define SR_MII_CTRL_SS13_OFFSET  13
+	#define SR_MII_CTRL_SS13_LEN     1
+	#define SR_MII_CTRL_SS13_DEFAULT 0x0
+	/*[field] LBE*/
+	#define SR_MII_CTRL_LBE
+	#define SR_MII_CTRL_LBE_OFFSET  14
+	#define SR_MII_CTRL_LBE_LEN     1
+	#define SR_MII_CTRL_LBE_DEFAULT 0x0
+	/*[field] RST*/
+	#define SR_MII_CTRL_RST
+	#define SR_MII_CTRL_RST_OFFSET  15
+	#define SR_MII_CTRL_RST_LEN     1
+	#define SR_MII_CTRL_RST_DEFAULT 0x0
+
+struct sr_mii_ctrl {
+	a_uint32_t  _reserved0:5;
+	a_uint32_t  ss5:1;
+	a_uint32_t  ss6:1;
+	a_uint32_t  _reserved1:1;
+	a_uint32_t  duplex_mode:1;
+	a_uint32_t  restart_an:1;
+	a_uint32_t  _reserved2:1;
+	a_uint32_t  lpm:1;
+	a_uint32_t  an_enable:1;
+	a_uint32_t  ss13:1;
+	a_uint32_t  lbe:1;
+	a_uint32_t  rst:1;
+	a_uint32_t  _reserved3:16;
+};
+
+union sr_mii_ctrl_u {
+	a_uint32_t val;
+	struct sr_mii_ctrl bf;
+};
+
+/*[register] VR_MII_AN_CTRL*/
+#define VR_MII_AN_CTRL
+#define VR_MII_AN_CTRL_ADDRESS 0x1f8001
+#define VR_MII_AN_CTRL_NUM     3
+#define VR_MII_AN_CTRL_INC     0x1
+#define VR_MII_AN_CTRL_TYPE    REG_TYPE_RW
+#define VR_MII_AN_CTRL_DEFAULT 0x0
+	/*[field] MII_AN_INTR_EN*/
+	#define VR_MII_AN_CTRL_MII_AN_INTR_EN
+	#define VR_MII_AN_CTRL_MII_AN_INTR_EN_OFFSET  0
+	#define VR_MII_AN_CTRL_MII_AN_INTR_EN_LEN     1
+	#define VR_MII_AN_CTRL_MII_AN_INTR_EN_DEFAULT 0x0
+	/*[field] PCS_MODE*/
+	#define VR_MII_AN_CTRL_PCS_MODE
+	#define VR_MII_AN_CTRL_PCS_MODE_OFFSET  1
+	#define VR_MII_AN_CTRL_PCS_MODE_LEN     2
+	#define VR_MII_AN_CTRL_PCS_MODE_DEFAULT 0x0
+	/*[field] TX_CONFIG*/
+	#define VR_MII_AN_CTRL_TX_CONFIG
+	#define VR_MII_AN_CTRL_TX_CONFIG_OFFSET  3
+	#define VR_MII_AN_CTRL_TX_CONFIG_LEN     1
+	#define VR_MII_AN_CTRL_TX_CONFIG_DEFAULT 0x0
+	/*[field] SGMII_LINK_STS*/
+	#define VR_MII_AN_CTRL_SGMII_LINK_STS
+	#define VR_MII_AN_CTRL_SGMII_LINK_STS_OFFSET  4
+	#define VR_MII_AN_CTRL_SGMII_LINK_STS_LEN     1
+	#define VR_MII_AN_CTRL_SGMII_LINK_STS_DEFAULT 0x0
+	/*[field] MII_CTRL*/
+	#define VR_MII_AN_CTRL_MII_CTRL
+	#define VR_MII_AN_CTRL_MII_CTRL_OFFSET  8
+	#define VR_MII_AN_CTRL_MII_CTRL_LEN     1
+	#define VR_MII_AN_CTRL_MII_CTRL_DEFAULT 0x0
+
+struct vr_mii_an_ctrl {
+	a_uint32_t  mii_an_intr_en:1;
+	a_uint32_t  pcs_mode:2;
+	a_uint32_t  tx_config:1;
+	a_uint32_t  sgmii_link_sts:1;
+	a_uint32_t  _reserved0:3;
+	a_uint32_t  mii_ctrl:1;
+	a_uint32_t  _reserved1:23;
+};
+
+union vr_mii_an_ctrl_u {
+	a_uint32_t val;
+	struct vr_mii_an_ctrl bf;
+};
+
+/*[register] VR_MII_AN_INTR_STS*/
+#define VR_MII_AN_INTR_STS
+#define VR_MII_AN_INTR_STS_ADDRESS 0x1f8002
+#define VR_MII_AN_INTR_STS_NUM     3
+#define VR_MII_AN_INTR_STS_INC     0x1
+#define VR_MII_AN_INTR_STS_TYPE    REG_TYPE_RW
+#define VR_MII_AN_INTR_STS_DEFAULT 0x0
+	/*[field] CL37_ANCMPLT_INTR*/
+	#define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR
+	#define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_OFFSET  0
+	#define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_LEN     1
+	#define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_DEFAULT 0x0
+	/*[field] CL37_ANSGM_STS*/
+	#define VR_MII_AN_INTR_STS_CL37_ANSGM_STS
+	#define VR_MII_AN_INTR_STS_CL37_ANSGM_STS_OFFSET  1
+	#define VR_MII_AN_INTR_STS_CL37_ANSGM_STS_LEN     4
+	#define VR_MII_AN_INTR_STS_CL37_ANSGM_STS_DEFAULT 0x0
+	/*[field] USXG_AN_STS*/
+	#define VR_MII_AN_INTR_STS_USXG_AN_STS
+	#define VR_MII_AN_INTR_STS_USXG_AN_STS_OFFSET  8
+	#define VR_MII_AN_INTR_STS_USXG_AN_STS_LEN     7
+	#define VR_MII_AN_INTR_STS_USXG_AN_STS_DEFAULT 0x0
+
+struct vr_mii_an_intr_sts {
+	a_uint32_t  cl37_ancmplt_intr:1;
+	a_uint32_t  cl37_ansgm_sts:4;
+	a_uint32_t  _reserved0:3;
+	a_uint32_t  usxg_an_sts:7;
+	a_uint32_t  _reserved1:17;
+};
+
+union vr_mii_an_intr_sts_u {
+	a_uint32_t val;
+	struct vr_mii_an_intr_sts bf;
+};
+
+/*[register] UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION*/
+#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION
+#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_ADDRESS 0x14
+#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_NUM     3
+#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_INC     0x1
+#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_TYPE    REG_TYPE_RW
+#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_DEFAULT 0x0
+	/*[field] MMD1_REG_SRC_UPHY_PLL_VCO_TEMP_CMP*/
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_TEMP_CMP
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_TEMP_CMP_OFFSET  2
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_TEMP_CMP_LEN     2
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_TEMP_CMP_DEFAULT 0x0
+	/*[field] MMD1_REG_SRC_UPHY_PLL_VCO_AMP*/
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_AMP
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_AMP_OFFSET  4
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_AMP_LEN     2
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_AMP_DEFAULT 0x0
+	/*[field] MMD1_REG_SRC_UPHY_PLL_VCO_GAIN*/
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_GAIN
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_GAIN_OFFSET  6
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_GAIN_LEN     2
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_GAIN_DEFAULT 0x0
+	/*[field] MMD1_REG_SRC_UPHY_PLL_LPF_C2*/
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_C2
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_C2_OFFSET  8
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_C2_LEN     2
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_C2_DEFAULT 0x0
+	/*[field] MMD1_REG_SRC_UPHY_PLL_LPF_RES*/
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_RES
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_RES_OFFSET  10
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_RES_LEN     2
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_RES_DEFAULT 0x0
+	/*[field] MMD1_REG_SRC_UPHY_PLL_CP_SEL*/
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_CP_SEL
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_CP_SEL_OFFSET  12
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_CP_SEL_LEN     2
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_CP_SEL_DEFAULT 0x0
+	/*[field] MMD1_REG_SRC_UPHY_PLL_LPF_DC*/
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_DC
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_DC_OFFSET  14
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_DC_LEN     2
+	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_DC_DEFAULT 0x0
+
+struct uniphy_pll_control_vco_related_selection {
+	a_uint32_t  mmd1_reg_src_uphy_pll_vco_temp_cmp:2;
+	a_uint32_t  mmd1_reg_src_uphy_pll_vco_amp:2;
+	a_uint32_t  mmd1_reg_src_uphy_pll_vco_gain:2;
+	a_uint32_t  mmd1_reg_src_uphy_pll_lpf_c2:2;
+	a_uint32_t  mmd1_reg_src_uphy_pll_lpf_res:2;
+	a_uint32_t  mmd1_reg_src_uphy_pll_cp_sel:2;
+	a_uint32_t  mmd1_reg_src_uphy_pll_lpf_dc:2;
+	a_uint32_t  _reserved0:16;
+};
+
+union uniphy_pll_control_vco_related_selection_u {
+	a_uint32_t val;
+	struct uniphy_pll_control_vco_related_selection bf;
+};
+
+/*[register] UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION*/
+#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION
+#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_ADDRESS 0x24
+#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_NUM     3
+#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_INC     0x1
+#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_TYPE    REG_TYPE_RW
+#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_DEFAULT 0x0
+	/*[field] MMD1_REG_SRC_UPHY_TX_EMP_LSB_EN*/
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LSB_EN
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LSB_EN_OFFSET  0
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LSB_EN_LEN     2
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LSB_EN_DEFAULT 0x0
+	/*[field] MMD1_REG_SRC_UPHY_TX_RESCAL_CODE*/
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_RESCAL_CODE
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_RESCAL_CODE_OFFSET  2
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_RESCAL_CODE_LEN     2
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_RESCAL_CODE_DEFAULT 0x0
+	/*[field] MMD1_REG_SRC_UPHY_TX_EMP_LVL*/
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LVL
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LVL_OFFSET  4
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LVL_LEN     2
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LVL_DEFAULT 0x0
+	/*[field] MMD1_REG_SRC_UPHY_TX_AMP*/
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_AMP
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_AMP_OFFSET  6
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_AMP_LEN     2
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_AMP_DEFAULT 0x0
+	/*[field] MMD1_REG_SRC_UPHY_TX_VCM_DELTA*/
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_VCM_DELTA
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_VCM_DELTA_OFFSET  8
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_VCM_DELTA_LEN     2
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_VCM_DELTA_DEFAULT 0x0
+	/*[field] MMD1_REG_SRC_UPHY_TX_EN*/
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EN
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EN_OFFSET  10
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EN_LEN     2
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EN_DEFAULT 0x0
+	/*[field] MMD1_REG_SRC_UPHY_TXD_BIT_WIDTH*/
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TXD_BIT_WIDTH
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TXD_BIT_WIDTH_OFFSET  12
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TXD_BIT_WIDTH_LEN     2
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TXD_BIT_WIDTH_DEFAULT 0x0
+	/*[field] MMD1_REG_SRC_UPHY_TX_ACJTAG_BEACON_EN*/
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_ACJTAG_BEACON_EN
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_ACJTAG_BEACON_EN_OFFSET  14
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_ACJTAG_BEACON_EN_LEN     2
+	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_ACJTAG_BEACON_EN_DEFAULT 0x0
+
+struct uniphy_tx_ac_jtag_mux_driver_selection {
+	a_uint32_t  mmd1_reg_src_uphy_tx_emp_lsb_en:2;
+	a_uint32_t  mmd1_reg_src_uphy_tx_rescal_code:2;
+	a_uint32_t  mmd1_reg_src_uphy_tx_emp_lvl:2;
+	a_uint32_t  mmd1_reg_src_uphy_tx_amp:2;
+	a_uint32_t  mmd1_reg_src_uphy_tx_vcm_delta:2;
+	a_uint32_t  mmd1_reg_src_uphy_tx_en:2;
+	a_uint32_t  mmd1_reg_src_uphy_txd_bit_width:2;
+	a_uint32_t  mmd1_reg_src_uphy_tx_acjtag_beacon_en:2;
+	a_uint32_t  _reserved0:16;
+};
+
+union uniphy_tx_ac_jtag_mux_driver_selection_u {
+	a_uint32_t val;
+	struct uniphy_tx_ac_jtag_mux_driver_selection bf;
+};
+
+/*[register] UNIPHY_RESISTOR_CALIBRATION_1*/
+#define UNIPHY_RESISTOR_CALIBRATION_1
+#define UNIPHY_RESISTOR_CALIBRATION_1_ADDRESS 0x170
+#define UNIPHY_RESISTOR_CALIBRATION_1_NUM     3
+#define UNIPHY_RESISTOR_CALIBRATION_1_INC     0x1
+#define UNIPHY_RESISTOR_CALIBRATION_1_TYPE    REG_TYPE_RW
+#define UNIPHY_RESISTOR_CALIBRATION_1_DEFAULT 0x0
+	/*[field] MMD1_REG_CALIB_RX_REG*/
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_RX_REG
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_RX_REG_OFFSET  0
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_RX_REG_LEN     5
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_RX_REG_DEFAULT 0x0
+	/*[field] MMD1_REG_CALIB_TX_REG*/
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_TX_REG
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_TX_REG_OFFSET  5
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_TX_REG_LEN     5
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_TX_REG_DEFAULT 0x0
+	/*[field] MMD1_REG_VREF_LVL*/
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_VREF_LVL
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_VREF_LVL_OFFSET  10
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_VREF_LVL_LEN     5
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_VREF_LVL_DEFAULT 0x0
+	/*[field] MMD1_REG_DISABLE_LOAD_RES_TXRX*/
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_DISABLE_LOAD_RES_TXRX
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_DISABLE_LOAD_RES_TXRX_OFFSET  15
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_DISABLE_LOAD_RES_TXRX_LEN     1
+	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_DISABLE_LOAD_RES_TXRX_DEFAULT 0x0
+
+struct uniphy_resistor_calibration_1 {
+	a_uint32_t  mmd1_reg_calib_rx_reg:5;
+	a_uint32_t  mmd1_reg_calib_tx_reg:5;
+	a_uint32_t  mmd1_reg_vref_lvl:5;
+	a_uint32_t  mmd1_reg_disable_load_res_txrx:1;
+	a_uint32_t  _reserved0:16;
+};
+
+union uniphy_resistor_calibration_1_u {
+	a_uint32_t val;
+	struct uniphy_resistor_calibration_1 bf;
+};
+
+/*[register] UNIPHY_PLL_VCO_RELATED_CONTROL_1*/
+#define UNIPHY_PLL_VCO_RELATED_CONTROL_1
+#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_ADDRESS 0x78c
+#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_NUM     3
+#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_INC     0x1
+#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_TYPE    REG_TYPE_RW
+#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_DEFAULT 0x0
+	/*[field] MIIREG_REG_UPHY_PLL_VCO_TEMP_CMP*/
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_TEMP_CMP
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_TEMP_CMP_OFFSET  0
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_TEMP_CMP_LEN     6
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_TEMP_CMP_DEFAULT 0x0
+	/*[field] MIIREG_REG_UPHY_PLL_VCO_CALIB_READY*/
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_CALIB_READY
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_CALIB_READY_OFFSET  6
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_CALIB_READY_LEN     1
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_CALIB_READY_DEFAULT 0x0
+	/*[field] MIIREG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY*/
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_OFFSET  7
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_LEN     1
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_DEFAULT 0x0
+	/*[field] MIIREG_REG_UPHY_PLL_VCO_AMP*/
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_AMP
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_AMP_OFFSET  8
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_AMP_LEN     4
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_AMP_DEFAULT 0x0
+	/*[field] MIIREG_REG_UPHY_PLL_VCO_GAIN*/
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_GAIN
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_GAIN_OFFSET  12
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_GAIN_LEN     3
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_GAIN_DEFAULT 0x0
+	/*[field] MIIREG_UPHY_PLL_LCKDT_EN*/
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_UPHY_PLL_LCKDT_EN
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_UPHY_PLL_LCKDT_EN_OFFSET  15
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_UPHY_PLL_LCKDT_EN_LEN     1
+	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_UPHY_PLL_LCKDT_EN_DEFAULT 0x0
+
+struct uniphy_pll_vco_related_control_1 {
+	a_uint32_t  miireg_reg_uphy_pll_vco_temp_cmp:6;
+	a_uint32_t  miireg_reg_uphy_pll_vco_calib_ready:1;
+	a_uint32_t  miireg_autoload_sel_pll_vco_calib_ready:1;
+	a_uint32_t  miireg_reg_uphy_pll_vco_amp:4;
+	a_uint32_t  miireg_reg_uphy_pll_vco_gain:3;
+	a_uint32_t  miireg_uphy_pll_lckdt_en:1;
+	a_uint32_t  _reserved0:16;
+};
+
+union uniphy_pll_vco_related_control_1_u {
+	a_uint32_t val;
+	struct uniphy_pll_vco_related_control_1 bf;
+};
+
+/*[register] UNIPHY_RX_AFE_2*/
+#define UNIPHY_RX_AFE_2
+#define UNIPHY_RX_AFE_2_ADDRESS 0x7c4
+#define UNIPHY_RX_AFE_2_NUM     3
+#define UNIPHY_RX_AFE_2_INC     0x1
+#define UNIPHY_RX_AFE_2_TYPE    REG_TYPE_RW
+#define UNIPHY_RX_AFE_2_DEFAULT 0x0
+	/*[field] MIIREG_REG_UPHY_RX_AFE_RES1*/
+	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_RES1
+	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_RES1_OFFSET  0
+	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_RES1_LEN     4
+	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_RES1_DEFAULT 0x0
+	/*[field] MIIREG_REG_UPHY_RX_AFE_CAP1*/
+	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_CAP1
+	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_CAP1_OFFSET  4
+	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_CAP1_LEN     3
+	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_CAP1_DEFAULT 0x0
+	/*[field] MIIREG_REG_UPHY_RX_RESCAL_CODE*/
+	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_RESCAL_CODE
+	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_RESCAL_CODE_OFFSET  8
+	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_RESCAL_CODE_LEN     5
+	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_RESCAL_CODE_DEFAULT 0x0
+
+struct uniphy_rx_afe_2 {
+	a_uint32_t  miireg_reg_uphy_rx_afe_res1:4;
+	a_uint32_t  miireg_reg_uphy_rx_afe_cap1:3;
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  miireg_reg_uphy_rx_rescal_code:5;
+	a_uint32_t  _reserved1:19;
+};
+
+union uniphy_rx_afe_2_u {
+	a_uint32_t val;
+	struct uniphy_rx_afe_2 bf;
+};
+
+/*[register] BANDGAP_IP_MBIAS_2*/
+#define BANDGAP_IP_MBIAS_2
+#define BANDGAP_IP_MBIAS_2_ADDRESS 0x9b004
+#define BANDGAP_IP_MBIAS_2_NUM     4
+#define BANDGAP_IP_MBIAS_2_INC     0x1
+#define BANDGAP_IP_MBIAS_2_TYPE    REG_TYPE_RW
+#define BANDGAP_IP_MBIAS_2_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_BG_RSV*/
+	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_BG_RSV
+	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_BG_RSV_OFFSET  0
+	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_BG_RSV_LEN     8
+	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_BG_RSV_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_ICC_RESCODE*/
+	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_ICC_RESCODE
+	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_ICC_RESCODE_OFFSET  8
+	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_ICC_RESCODE_LEN     7
+	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_ICC_RESCODE_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_MBIAS_EN*/
+	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_MBIAS_EN
+	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_MBIAS_EN_OFFSET  15
+	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_MBIAS_EN_LEN     1
+	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_MBIAS_EN_DEFAULT 0x0
+
+struct bandgap_ip_mbias_2 {
+	a_uint32_t  cmn_mmd1_reg_cmn_bg_rsv:8;
+	a_uint32_t  cmn_mmd1_reg_cmn_icc_rescode:7;
+	a_uint32_t  cmn_mmd1_reg_mbias_en:1;
+	a_uint32_t  _reserved0:16;
+};
+
+union bandgap_ip_mbias_2_u {
+	a_uint32_t val;
+	struct bandgap_ip_mbias_2 bf;
+};
+
+/*[register] LDO_0P9V_RELATED_1*/
+#define LDO_0P9V_RELATED_1
+#define LDO_0P9V_RELATED_1_ADDRESS 0x9b054
+#define LDO_0P9V_RELATED_1_NUM     4
+#define LDO_0P9V_RELATED_1_INC     0x1
+#define LDO_0P9V_RELATED_1_TYPE    REG_TYPE_RW
+#define LDO_0P9V_RELATED_1_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_LDO_INT_RES_CTRL*/
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_RES_CTRL
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_RES_CTRL_OFFSET  0
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_RES_CTRL_LEN     2
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_RES_CTRL_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_LDO_INT_LOAD_EN*/
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_LOAD_EN
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_LOAD_EN_OFFSET  2
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_LOAD_EN_LEN     1
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_LOAD_EN_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_LDO_OCP_CURRENT_SEL*/
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_CURRENT_SEL
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_CURRENT_SEL_OFFSET  3
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_CURRENT_SEL_LEN     1
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_CURRENT_SEL_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_LDO_OCP_EN*/
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_EN
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_EN_OFFSET  4
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_EN_LEN     1
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_EN_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_LDO_BIAS_CTRL*/
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_BIAS_CTRL
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_BIAS_CTRL_OFFSET  5
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_BIAS_CTRL_LEN     2
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_BIAS_CTRL_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_LDO_VOUT_CTRL*/
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_VOUT_CTRL
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_VOUT_CTRL_OFFSET  7
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_VOUT_CTRL_LEN     4
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_VOUT_CTRL_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_LDO_EN*/
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_EN
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_EN_OFFSET  11
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_EN_LEN     1
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_EN_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_LDO_COMP_CURRENT_EN*/
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_COMP_CURRENT_EN
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_COMP_CURRENT_EN_OFFSET  12
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_COMP_CURRENT_EN_LEN     1
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_COMP_CURRENT_EN_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_VTT_LDO_BIASGEN_SEL*/
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_VTT_LDO_BIASGEN_SEL
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_VTT_LDO_BIASGEN_SEL_OFFSET  13
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_VTT_LDO_BIASGEN_SEL_LEN     3
+	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_VTT_LDO_BIASGEN_SEL_DEFAULT 0x0
+
+struct ldo_0p9v_related_1 {
+	a_uint32_t  cmn_mmd1_reg_cmn_ldo_int_res_ctrl:2;
+	a_uint32_t  cmn_mmd1_reg_cmn_ldo_int_load_en:1;
+	a_uint32_t  cmn_mmd1_reg_cmn_ldo_ocp_current_sel:1;
+	a_uint32_t  cmn_mmd1_reg_cmn_ldo_ocp_en:1;
+	a_uint32_t  cmn_mmd1_reg_cmn_ldo_bias_ctrl:2;
+	a_uint32_t  cmn_mmd1_reg_cmn_ldo_vout_ctrl:4;
+	a_uint32_t  cmn_mmd1_reg_cmn_ldo_en:1;
+	a_uint32_t  cmn_mmd1_reg_cmn_ldo_comp_current_en:1;
+	a_uint32_t  cmn_mmd1_reg_cmn_vtt_ldo_biasgen_sel:3;
+	a_uint32_t  _reserved0:16;
+};
+
+union ldo_0p9v_related_1_u {
+	a_uint32_t val;
+	struct ldo_0p9v_related_1 bf;
+};
+
+/*[register] OTP_VTT_LDO_RELATED*/
+#define OTP_VTT_LDO_RELATED
+#define OTP_VTT_LDO_RELATED_ADDRESS 0x9b05c
+#define OTP_VTT_LDO_RELATED_NUM     4
+#define OTP_VTT_LDO_RELATED_INC     0x1
+#define OTP_VTT_LDO_RELATED_TYPE    REG_TYPE_RW
+#define OTP_VTT_LDO_RELATED_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_VTT_LDO_RSV*/
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_RSV
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_RSV_OFFSET  0
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_RSV_LEN     8
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_RSV_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_VTT_LDO_INT_LOAD_CTRL*/
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_INT_LOAD_CTRL
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_INT_LOAD_CTRL_OFFSET  8
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_INT_LOAD_CTRL_LEN     2
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_INT_LOAD_CTRL_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_VTT_LDO_OCP_CURRENT_SEL*/
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_CURRENT_SEL
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_CURRENT_SEL_OFFSET  10
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_CURRENT_SEL_LEN     1
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_CURRENT_SEL_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_VTT_LDO_OCP_EN*/
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_EN
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_EN_OFFSET  11
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_EN_LEN     1
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_EN_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_VTT_LDO_BIAS_CTRL*/
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_BIAS_CTRL
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_BIAS_CTRL_OFFSET  12
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_BIAS_CTRL_LEN     2
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_BIAS_CTRL_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_VTT_LDO_EN*/
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_EN
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_EN_OFFSET  14
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_EN_LEN     1
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_EN_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_ANA_ISOLATION*/
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_ANA_ISOLATION
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_ANA_ISOLATION_OFFSET  15
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_ANA_ISOLATION_LEN     1
+	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_ANA_ISOLATION_DEFAULT 0x0
+
+struct otp_vtt_ldo_related {
+	a_uint32_t  cmn_mmd1_reg_cmn_vtt_ldo_rsv:8;
+	a_uint32_t  cmn_mmd1_reg_cmn_vtt_ldo_int_load_ctrl:2;
+	a_uint32_t  cmn_mmd1_reg_cmn_vtt_ldo_ocp_current_sel:1;
+	a_uint32_t  cmn_mmd1_reg_cmn_vtt_ldo_ocp_en:1;
+	a_uint32_t  cmn_mmd1_reg_cmn_vtt_ldo_bias_ctrl:2;
+	a_uint32_t  cmn_mmd1_reg_cmn_vtt_ldo_en:1;
+	a_uint32_t  cmn_mmd1_reg_cmn_ana_isolation:1;
+	a_uint32_t  _reserved0:16;
+};
+
+union otp_vtt_ldo_related_u {
+	a_uint32_t val;
+	struct otp_vtt_ldo_related bf;
+};
+
+/*[register] OTP_TEMPERATURE_COMPENSATE_1*/
+#define OTP_TEMPERATURE_COMPENSATE_1
+#define OTP_TEMPERATURE_COMPENSATE_1_ADDRESS 0x9b08c
+#define OTP_TEMPERATURE_COMPENSATE_1_NUM     4
+#define OTP_TEMPERATURE_COMPENSATE_1_INC     0x1
+#define OTP_TEMPERATURE_COMPENSATE_1_TYPE    REG_TYPE_RW
+#define OTP_TEMPERATURE_COMPENSATE_1_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_UPHY_ICTAT100U_CTRL0*/
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL0
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL0_OFFSET  0
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL0_LEN     3
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL0_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_UPHY_ICTAT100U_CTRL1*/
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL1
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL1_OFFSET  4
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL1_LEN     3
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL1_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_UPHY_ICTAT100U_CTRL2*/
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL2
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL2_OFFSET  8
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL2_LEN     3
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL2_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_UPHY_ICTAT100U_EN*/
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_EN
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_EN_OFFSET  12
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_EN_LEN     3
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_EN_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_CMN_PLL_ICTAT100U_EN*/
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_CMN_PLL_ICTAT100U_EN
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_CMN_PLL_ICTAT100U_EN_OFFSET  15
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_CMN_PLL_ICTAT100U_EN_LEN     1
+	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_CMN_PLL_ICTAT100U_EN_DEFAULT 0x0
+
+struct otp_temperature_compensate_1 {
+	a_uint32_t  cmn_mmd1_reg_uphy_ictat100u_ctrl0:3;
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  cmn_mmd1_reg_uphy_ictat100u_ctrl1:3;
+	a_uint32_t  _reserved1:1;
+	a_uint32_t  cmn_mmd1_reg_uphy_ictat100u_ctrl2:3;
+	a_uint32_t  _reserved2:1;
+	a_uint32_t  cmn_mmd1_reg_uphy_ictat100u_en:3;
+	a_uint32_t  cmn_mmd1_reg_cmn_pll_ictat100u_en:1;
+	a_uint32_t  _reserved3:16;
+};
+
+union otp_temperature_compensate_1_u {
+	a_uint32_t val;
+	struct otp_temperature_compensate_1 bf;
+};
+
+/*[register] PLL_VCO_RELATED_CONTROL_1*/
+#define PLL_VCO_RELATED_CONTROL_1
+#define PLL_VCO_RELATED_CONTROL_1_ADDRESS 0x9b78c
+#define PLL_VCO_RELATED_CONTROL_1_NUM     4
+#define PLL_VCO_RELATED_CONTROL_1_INC     0x1
+#define PLL_VCO_RELATED_CONTROL_1_TYPE    REG_TYPE_RW
+#define PLL_VCO_RELATED_CONTROL_1_DEFAULT 0x0
+	/*[field] CMN_MII_REG_REG_CMN_PLL_VCO_TEMP_CMP*/
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_TEMP_CMP
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_TEMP_CMP_OFFSET  0
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_TEMP_CMP_LEN     6
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_TEMP_CMP_DEFAULT 0x0
+	/*[field] CMN_MII_REG_REG_CMN_PLL_VCO_CALIB_READY*/
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_CALIB_READY
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_CALIB_READY_OFFSET  6
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_CALIB_READY_LEN     1
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_CALIB_READY_DEFAULT 0x0
+	/*[field] CMN_MII_REG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY*/
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_OFFSET  7
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_LEN     1
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_DEFAULT 0x0
+	/*[field] CMN_MII_REG_REG_CMN_PLL_VCO_AMP*/
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_AMP
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_AMP_OFFSET  8
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_AMP_LEN     4
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_AMP_DEFAULT 0x0
+	/*[field] CMN_MII_REG_CMN_PLL_LCKDT_EN*/
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_CMN_PLL_LCKDT_EN
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_CMN_PLL_LCKDT_EN_OFFSET  15
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_CMN_PLL_LCKDT_EN_LEN     1
+	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_CMN_PLL_LCKDT_EN_DEFAULT 0x0
+
+struct pll_vco_related_control_1 {
+	a_uint32_t  cmn_mii_reg_reg_cmn_pll_vco_temp_cmp:6;
+	a_uint32_t  cmn_mii_reg_reg_cmn_pll_vco_calib_ready:1;
+	a_uint32_t  cmn_mii_reg_autoload_sel_pll_vco_calib_ready:1;
+	a_uint32_t  cmn_mii_reg_reg_cmn_pll_vco_amp:4;
+	a_uint32_t  _reserved0:3;
+	a_uint32_t  cmn_mii_reg_cmn_pll_lckdt_en:1;
+	a_uint32_t  _reserved1:16;
+};
+
+union pll_vco_related_control_1_u {
+	a_uint32_t val;
+	struct pll_vco_related_control_1 bf;
+};
+
+/*[register] PLL_CONTROL_VCO_RELATED_SELECTION_2*/
+#define PLL_CONTROL_VCO_RELATED_SELECTION_2
+#define PLL_CONTROL_VCO_RELATED_SELECTION_2_ADDRESS 0x9b02c
+#define PLL_CONTROL_VCO_RELATED_SELECTION_2_NUM     4
+#define PLL_CONTROL_VCO_RELATED_SELECTION_2_INC     0x1
+#define PLL_CONTROL_VCO_RELATED_SELECTION_2_TYPE    REG_TYPE_RW
+#define PLL_CONTROL_VCO_RELATED_SELECTION_2_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_SRC_CMN_PLL_VCO_TEMP_CMP*/
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_TEMP_CMP
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_TEMP_CMP_OFFSET  0
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_TEMP_CMP_LEN     2
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_TEMP_CMP_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_SRC_CMN_PLL_VCO_AMP*/
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_AMP
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_AMP_OFFSET  2
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_AMP_LEN     2
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_AMP_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_SRC_CMN_PLL_FBCLK_DIV*/
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_FBCLK_DIV
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_FBCLK_DIV_OFFSET  4
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_FBCLK_DIV_LEN     2
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_FBCLK_DIV_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_READY*/
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_READY
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_READY_OFFSET  6
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_READY_LEN     2
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_READY_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_CODE*/
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_CODE
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_CODE_OFFSET  8
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_CODE_LEN     2
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_CODE_DEFAULT 0x0
+	/*[field] CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_START*/
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_START
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_START_OFFSET  10
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_START_LEN     2
+	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_START_DEFAULT 0x0
+
+struct pll_control_vco_related_selection_2 {
+	a_uint32_t  cmn_mmd1_reg_src_cmn_pll_vco_temp_cmp:2;
+	a_uint32_t  cmn_mmd1_reg_src_cmn_pll_vco_amp:2;
+	a_uint32_t  cmn_mmd1_reg_src_cmn_pll_fbclk_div:2;
+	a_uint32_t  cmn_mmd1_reg_src_cmn_pll_vco_calib_ready:2;
+	a_uint32_t  cmn_mmd1_reg_src_cmn_pll_vco_calib_code:2;
+	a_uint32_t  cmn_mmd1_reg_src_cmn_pll_vco_calib_start:2;
+	a_uint32_t  _reserved0:20;
+};
+
+union pll_control_vco_related_selection_2_u {
+	a_uint32_t val;
+	struct pll_control_vco_related_selection_2 bf;
+};
+
+/*[register] PLL_POWER_ON_AND_RESET*/
+#define PLL_POWER_ON_AND_RESET
+#define PLL_POWER_ON_AND_RESET_ADDRESS 0x780
+#define PLL_POWER_ON_AND_RESET_NUM     4
+#define PLL_POWER_ON_AND_RESET_INC     0x1
+#define PLL_POWER_ON_AND_RESET_TYPE    REG_TYPE_RW
+#define PLL_POWER_ON_AND_RESET_DEFAULT 0x2ff
+	/*[field] MIIREG_UPHY_PLL_RSTN*/
+	#define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN
+	#define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN_OFFSET  0
+	#define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN_LEN     1
+	#define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN_DEFAULT 0x1
+	/*[field] MIIREG_REG_UPHY_PLL_EN*/
+	#define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN
+	#define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN_OFFSET  1
+	#define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN_LEN     1
+	#define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN_DEFAULT 0x1
+	/*[field] MIIREG_UPHY_RXCLK_SW_RSTN*/
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN_OFFSET  2
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN_LEN     1
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN_DEFAULT 0x1
+	/*[field] MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN*/
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN_OFFSET  3
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN_LEN     1
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN_DEFAULT 0x1
+	/*[field] MIIREG_UPHY_TXCLK_SW_RSTN*/
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN_OFFSET  4
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN_LEN     1
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN_DEFAULT 0x0
+	/*[field] MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN*/
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN_OFFSET  5
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN_LEN     1
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN_DEFAULT 0x0
+	/*[field] MIIREG_UPHY_ANA_EN_SW_RSTN*/
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN_OFFSET  6
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN_LEN     1
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN_DEFAULT 0x0
+	/*[field] MIIREG_UPHY_PLL_MMDIV_RSTN*/
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN_OFFSET  7
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN_LEN     1
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN_DEFAULT 0x0
+	/*[field] MIIREG_UPHY_CMN_12GPLL_ISOLATION*/
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION_OFFSET  8
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION_LEN     1
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION_DEFAULT 0x0
+	/*[field] MIIREG_UPHY_PCS_SW_RSTN*/
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN_OFFSET  9
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN_LEN     1
+	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN_DEFAULT 0x0
+
+struct pll_power_on_and_reset {
+	a_uint32_t  pll_reset:1;
+	a_uint32_t  pll_power_on:1;
+	a_uint32_t  software_reset_rxclk:1;
+	a_uint32_t  software_reset_rxclk_floop:1;
+	a_uint32_t  software_reset_txclk:1;
+	a_uint32_t  software_reset_ctrlclk:1;
+	a_uint32_t  software_reset_analog_reset:1;
+	a_uint32_t  reference_clock_reset:1;
+	a_uint32_t  cmn_12gpll_isolation:1;
+	a_uint32_t  pqsgmii_pcs_reset:1;
+	a_uint32_t  _reserved0:22;
+};
+
+union pll_power_on_and_reset_u {
+	a_uint32_t val;
+	struct pll_power_on_and_reset bf;
+};
+
+/*[register] UNIPHY_MISC2_PHY_MODE*/
+#define UNIPHY_MISC2_PHY_MODE
+#define UNIPHY_MISC2_PHY_MODE_ADDRESS 0x218
+#define UNIPHY_MISC2_PHY_MODE_NUM     4
+#define UNIPHY_MISC2_PHY_MODE_INC     0x1
+#define UNIPHY_MISC2_PHY_MODE_TYPE    REG_TYPE_RW
+#define UNIPHY_MISC2_PHY_MODE_DEFAULT 0x0
+	/*[field] MMD1_REG_REG_RATE*/
+	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE
+	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE_OFFSET  0
+	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE_LEN     2
+	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE_DEFAULT 0x1
+	/*[field] MMD1_REG_REG_PHY_MODE*/
+	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE
+	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE_OFFSET  4
+	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE_LEN     3
+	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE_DEFAULT 0x1
+
+
+struct uniphy_misc2_phy_mode {
+	a_uint32_t  phy_rate:2;
+	a_uint32_t  _reserved0:2;
+	a_uint32_t  phy_mode:3;
+	a_uint32_t  _reserved1:25;
+};
+
+union uniphy_misc2_phy_mode_u {
+	a_uint32_t val;
+	struct uniphy_misc2_phy_mode bf;
+};
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_vsi.h b/qca-ssdk/include/hsl/hppe/hppe_vsi.h
new file mode 100755
index 0000000..b8f9b5f
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_vsi.h
@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_VSI_H_
+#define _HPPE_VSI_H_
+
+#define VSI_TBL_MAX_ENTRY	32
+#define VLAN_CNT_TBL_MAX_ENTRY	32
+#define EG_VSI_COUNTER_TBL_MAX_ENTRY	32
+#define PRE_L2_CNT_TBL_MAX_ENTRY	32
+
+sw_error_t
+hppe_vsi_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vsi_tbl_u *value);
+
+sw_error_t
+hppe_vsi_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vsi_tbl_u *value);
+
+sw_error_t
+hppe_vsi_tbl_umc_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vsi_tbl_umc_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vsi_tbl_station_move_lrn_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vsi_tbl_station_move_lrn_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vsi_tbl_new_addr_fwd_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vsi_tbl_new_addr_fwd_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vsi_tbl_uuc_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vsi_tbl_uuc_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vsi_tbl_member_port_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vsi_tbl_member_port_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vsi_tbl_new_addr_lrn_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vsi_tbl_new_addr_lrn_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vsi_tbl_bc_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vsi_tbl_bc_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vsi_tbl_station_move_fwd_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vsi_tbl_station_move_fwd_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_vlan_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vlan_cnt_tbl_u *value);
+
+sw_error_t
+hppe_vlan_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vlan_cnt_tbl_u *value);
+
+sw_error_t
+hppe_vlan_cnt_tbl_rx_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_vlan_cnt_tbl_rx_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_vlan_cnt_tbl_rx_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_vlan_cnt_tbl_rx_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_eg_vsi_counter_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vsi_counter_tbl_u *value);
+
+sw_error_t
+hppe_eg_vsi_counter_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vsi_counter_tbl_u *value);
+
+
+sw_error_t
+hppe_eg_vsi_counter_tbl_tx_bytes_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_eg_vsi_counter_tbl_tx_bytes_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_eg_vsi_counter_tbl_tx_packets_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_eg_vsi_counter_tbl_tx_packets_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pre_l2_cnt_tbl_u *value);
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pre_l2_cnt_tbl_u *value);
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_drop_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_drop_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value);
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value);
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_drop_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_drop_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_vsi_reg.h b/qca-ssdk/include/hsl/hppe/hppe_vsi_reg.h
new file mode 100755
index 0000000..7a94bc3
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_vsi_reg.h
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_VSI_REG_H
+#define HPPE_VSI_REG_H
+
+/*[table] VSI_TBL*/
+#define VSI_TBL
+#define VSI_TBL_ADDRESS 0x1800
+#define VSI_TBL_NUM     32
+#define VSI_TBL_INC     0x10
+#define VSI_TBL_TYPE    REG_TYPE_RW
+#define VSI_TBL_DEFAULT 0x0
+	/*[field] MEMBER_PORT_BITMAP*/
+	#define VSI_TBL_MEMBER_PORT_BITMAP
+	#define VSI_TBL_MEMBER_PORT_BITMAP_OFFSET  0
+	#define VSI_TBL_MEMBER_PORT_BITMAP_LEN     8
+	#define VSI_TBL_MEMBER_PORT_BITMAP_DEFAULT 0x0
+	/*[field] UUC_BITMAP*/
+	#define VSI_TBL_UUC_BITMAP
+	#define VSI_TBL_UUC_BITMAP_OFFSET  8
+	#define VSI_TBL_UUC_BITMAP_LEN     8
+	#define VSI_TBL_UUC_BITMAP_DEFAULT 0x0
+	/*[field] UMC_BITMAP*/
+	#define VSI_TBL_UMC_BITMAP
+	#define VSI_TBL_UMC_BITMAP_OFFSET  16
+	#define VSI_TBL_UMC_BITMAP_LEN     8
+	#define VSI_TBL_UMC_BITMAP_DEFAULT 0x0
+	/*[field] BC_BITMAP*/
+	#define VSI_TBL_BC_BITMAP
+	#define VSI_TBL_BC_BITMAP_OFFSET  24
+	#define VSI_TBL_BC_BITMAP_LEN     8
+	#define VSI_TBL_BC_BITMAP_DEFAULT 0x0
+	/*[field] NEW_ADDR_LRN_EN*/
+	#define VSI_TBL_NEW_ADDR_LRN_EN
+	#define VSI_TBL_NEW_ADDR_LRN_EN_OFFSET  32
+	#define VSI_TBL_NEW_ADDR_LRN_EN_LEN     1
+	#define VSI_TBL_NEW_ADDR_LRN_EN_DEFAULT 0x0
+	/*[field] NEW_ADDR_FWD_CMD*/
+	#define VSI_TBL_NEW_ADDR_FWD_CMD
+	#define VSI_TBL_NEW_ADDR_FWD_CMD_OFFSET  33
+	#define VSI_TBL_NEW_ADDR_FWD_CMD_LEN     2
+	#define VSI_TBL_NEW_ADDR_FWD_CMD_DEFAULT 0x0
+	/*[field] STATION_MOVE_LRN_EN*/
+	#define VSI_TBL_STATION_MOVE_LRN_EN
+	#define VSI_TBL_STATION_MOVE_LRN_EN_OFFSET  35
+	#define VSI_TBL_STATION_MOVE_LRN_EN_LEN     1
+	#define VSI_TBL_STATION_MOVE_LRN_EN_DEFAULT 0x0
+	/*[field] STATION_MOVE_FWD_CMD*/
+	#define VSI_TBL_STATION_MOVE_FWD_CMD
+	#define VSI_TBL_STATION_MOVE_FWD_CMD_OFFSET  36
+	#define VSI_TBL_STATION_MOVE_FWD_CMD_LEN     2
+	#define VSI_TBL_STATION_MOVE_FWD_CMD_DEFAULT 0x0
+
+struct vsi_tbl {
+	a_uint32_t  member_port_bitmap:8;
+	a_uint32_t  uuc_bitmap:8;
+	a_uint32_t  umc_bitmap:8;
+	a_uint32_t  bc_bitmap:8;
+	a_uint32_t  new_addr_lrn_en:1;
+	a_uint32_t  new_addr_fwd_cmd:2;
+	a_uint32_t  station_move_lrn_en:1;
+	a_uint32_t  station_move_fwd_cmd:2;
+	a_uint32_t  _reserved0:26;
+};
+
+union vsi_tbl_u {
+	a_uint32_t val[2];
+	struct vsi_tbl bf;
+};
+
+/*[table] VLAN_CNT_TBL*/
+#define VLAN_CNT_TBL
+#define VLAN_CNT_TBL_ADDRESS 0x78000
+#define VLAN_CNT_TBL_NUM     32
+#define VLAN_CNT_TBL_INC     0x10
+#define VLAN_CNT_TBL_TYPE    REG_TYPE_RW
+#define VLAN_CNT_TBL_DEFAULT 0x0
+	/*[field] RX_PKT_CNT*/
+	#define VLAN_CNT_TBL_RX_PKT_CNT
+	#define VLAN_CNT_TBL_RX_PKT_CNT_OFFSET  0
+	#define VLAN_CNT_TBL_RX_PKT_CNT_LEN     32
+	#define VLAN_CNT_TBL_RX_PKT_CNT_DEFAULT 0x0
+	/*[field] RX_BYTE_CNT*/
+	#define VLAN_CNT_TBL_RX_BYTE_CNT
+	#define VLAN_CNT_TBL_RX_BYTE_CNT_OFFSET  32
+	#define VLAN_CNT_TBL_RX_BYTE_CNT_LEN     40
+	#define VLAN_CNT_TBL_RX_BYTE_CNT_DEFAULT 0x0
+
+struct vlan_cnt_tbl {
+	a_uint32_t  rx_pkt_cnt:32;
+	a_uint32_t  rx_byte_cnt_0:32;
+	a_uint32_t  rx_byte_cnt_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union vlan_cnt_tbl_u {
+	a_uint32_t val[3];
+	struct vlan_cnt_tbl bf;
+};
+
+/*[table] EG_VSI_COUNTER_TBL*/
+#define EG_VSI_COUNTER_TBL
+#define EG_VSI_COUNTER_TBL_ADDRESS 0x600
+#define EG_VSI_COUNTER_TBL_NUM     32
+#define EG_VSI_COUNTER_TBL_INC     0x10
+#define EG_VSI_COUNTER_TBL_TYPE    REG_TYPE_RW
+#define EG_VSI_COUNTER_TBL_DEFAULT 0x0
+	/*[field] TX_PACKETS*/
+	#define EG_VSI_COUNTER_TBL_TX_PACKETS
+	#define EG_VSI_COUNTER_TBL_TX_PACKETS_OFFSET  0
+	#define EG_VSI_COUNTER_TBL_TX_PACKETS_LEN     32
+	#define EG_VSI_COUNTER_TBL_TX_PACKETS_DEFAULT 0x0
+	/*[field] TX_BYTES*/
+	#define EG_VSI_COUNTER_TBL_TX_BYTES
+	#define EG_VSI_COUNTER_TBL_TX_BYTES_OFFSET  32
+	#define EG_VSI_COUNTER_TBL_TX_BYTES_LEN     40
+	#define EG_VSI_COUNTER_TBL_TX_BYTES_DEFAULT 0x0
+
+struct eg_vsi_counter_tbl {
+	a_uint32_t  tx_packets:32;
+	a_uint32_t  tx_bytes_0:32;
+	a_uint32_t  tx_bytes_1:8;
+	a_uint32_t  _reserved0:24;
+};
+
+union eg_vsi_counter_tbl_u {
+	a_uint32_t val[3];
+	struct eg_vsi_counter_tbl bf;
+};
+
+/*[table] PRE_L2_CNT_TBL*/
+#define PRE_L2_CNT_TBL
+#define PRE_L2_CNT_TBL_ADDRESS 0x7c000
+#define PRE_L2_CNT_TBL_NUM     32
+#define PRE_L2_CNT_TBL_INC     0x20
+#define PRE_L2_CNT_TBL_TYPE    REG_TYPE_RW
+#define PRE_L2_CNT_TBL_DEFAULT 0x0
+	/*[field] RX_PKT_CNT*/
+	#define PRE_L2_CNT_TBL_RX_PKT_CNT
+	#define PRE_L2_CNT_TBL_RX_PKT_CNT_OFFSET  0
+	#define PRE_L2_CNT_TBL_RX_PKT_CNT_LEN     32
+	#define PRE_L2_CNT_TBL_RX_PKT_CNT_DEFAULT 0x0
+	/*[field] RX_BYTE_CNT*/
+	#define PRE_L2_CNT_TBL_RX_BYTE_CNT
+	#define PRE_L2_CNT_TBL_RX_BYTE_CNT_OFFSET  32
+	#define PRE_L2_CNT_TBL_RX_BYTE_CNT_LEN     40
+	#define PRE_L2_CNT_TBL_RX_BYTE_CNT_DEFAULT 0x0
+	/*[field] RX_DROP_PKT_CNT*/
+	#define PRE_L2_CNT_TBL_RX_DROP_PKT_CNT
+	#define PRE_L2_CNT_TBL_RX_DROP_PKT_CNT_OFFSET  72
+	#define PRE_L2_CNT_TBL_RX_DROP_PKT_CNT_LEN     32
+	#define PRE_L2_CNT_TBL_RX_DROP_PKT_CNT_DEFAULT 0x0
+	/*[field] RX_DROP_BYTE_CNT*/
+	#define PRE_L2_CNT_TBL_RX_DROP_BYTE_CNT
+	#define PRE_L2_CNT_TBL_RX_DROP_BYTE_CNT_OFFSET  104
+	#define PRE_L2_CNT_TBL_RX_DROP_BYTE_CNT_LEN     40
+	#define PRE_L2_CNT_TBL_RX_DROP_BYTE_CNT_DEFAULT 0x0
+
+struct pre_l2_cnt_tbl {
+	a_uint32_t  rx_pkt_cnt:32;
+	a_uint32_t  rx_byte_cnt_0:32;
+	a_uint32_t  rx_byte_cnt_1:8;
+	a_uint32_t  rx_drop_pkt_cnt_0:24;
+	a_uint32_t  rx_drop_pkt_cnt_1:8;
+	a_uint32_t  rx_drop_byte_cnt_0:24;
+	a_uint32_t  rx_drop_byte_cnt_1:16;
+	a_uint32_t  _reserved0:16;
+};
+
+union pre_l2_cnt_tbl_u {
+	a_uint32_t val[5];
+	struct pre_l2_cnt_tbl bf;
+};
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_xgmacmib.h b/qca-ssdk/include/hsl/hppe/hppe_xgmacmib.h
new file mode 100755
index 0000000..40997c6
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_xgmacmib.h
@@ -0,0 +1,2252 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_XGMACMIB_H_
+#define _HPPE_XGMACMIB_H_
+
+#define MMC_CONTROL_MAX_ENTRY	2
+#define MMC_RECEIVE_INTERRUPT_MAX_ENTRY	2
+#define MMC_TRANSMIT_INTERRUPT_MAX_ENTRY	2
+#define MMC_RECEIVE_INTERRUPT_ENABLE_MAX_ENTRY	2
+#define MMC_TRANSMIT_INTERRUPT_ENABLE_MAX_ENTRY	2
+#define TX_OCTET_COUNT_GOOD_BAD_LOW_MAX_ENTRY	2
+#define TX_OCTET_COUNT_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define TX_FRAME_COUNT_GOOD_BAD_LOW_MAX_ENTRY	2
+#define TX_FRAME_COUNT_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define TX_BROADCAST_FRAMES_GOOD_LOW_MAX_ENTRY	2
+#define TX_BROADCAST_FRAMES_GOOD_HIGH_MAX_ENTRY	 2
+#define TX_MULTICAST_FRAMES_GOOD_LOW_MAX_ENTRY	2
+#define TX_MULTICAST_FRAMES_GOOD_HIGH_MAX_ENTRY	2
+#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define TX_UNDERFLOW_ERROR_FRAMES_LOW_MAX_ENTRY	2
+#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_MAX_ENTRY	2
+#define TX_OCTET_COUNT_GOOD_LOW_MAX_ENTRY	 2
+#define TX_OCTET_COUNT_GOOD_HIGH_MAX_ENTRY	2
+#define TX_FRAME_COUNT_GOOD_LOW_MAX_ENTRY	 2
+#define TX_FRAME_COUNT_GOOD_HIGH_MAX_ENTRY	2
+#define TX_PAUSE_FRAMES_LOW_MAX_ENTRY	 2
+#define TX_PAUSE_FRAMES_HIGH_MAX_ENTRY	2
+#define TX_VLAN_FRAMES_GOOD_LOW_MAX_ENTRY	2
+#define TX_VLAN_FRAMES_GOOD_HIGH_MAX_ENTRY	2
+#define TX_LPI_USEC_CNTR_MAX_ENTRY	2
+#define TX_LPI_TRAN_CNTR_MAX_ENTRY	2
+#define RX_FRAME_COUNT_GOOD_BAD_LOW_MAX_ENTRY	2
+#define RX_FRAME_COUNT_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define RX_OCTET_COUNT_GOOD_BAD_LOW_MAX_ENTRY	2
+#define RX_OCTET_COUNT_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define RX_OCTET_COUNT_GOOD_LOW_MAX_ENTRY	2
+#define RX_OCTET_COUNT_GOOD_HIGH_MAX_ENTRY	2
+#define RX_BROADCAST_FRAMES_GOOD_LOW_MAX_ENTRY	2
+#define RX_BROADCAST_FRAMES_GOOD_HIGH_MAX_ENTRY	2
+#define RX_MULTICAST_FRAMES_GOOD_LOW_MAX_ENTRY	2
+#define RX_MULTICAST_FRAMES_GOOD_HIGH_MAX_ENTRY	2
+#define RX_CRC_ERROR_FRAMES_LOW_MAX_ENTRY	2
+#define RX_CRC_ERROR_FRAMES_HIGH_MAX_ENTRY	2
+#define RX_RUNT_ERROR_FRAMES_MAX_ENTRY	2
+#define RX_JABBER_ERROR_FRAMES_MAX_ENTRY	2
+#define RX_UNDERSIZE_FRAMES_GOOD_MAX_ENTRY	2
+#define RX_OVERSIZE_FRAMES_GOOD_MAX_ENTRY	2
+#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define RX_UNICAST_FRAMES_GOOD_LOW_MAX_ENTRY	2
+#define RX_UNICAST_FRAMES_GOOD_HIGH_MAX_ENTRY	2
+#define RX_LENGTH_ERROR_FRAMES_LOW_MAX_ENTRY	2
+#define RX_LENGTH_ERROR_FRAMES_HIGH_MAX_ENTRY	2
+#define RX_OUTOFRANGE_FRAMES_LOW_MAX_ENTRY	2
+#define RX_OUTOFRANGE_FRAMES_HIGH_MAX_ENTRY	2
+#define RX_PAUSE_FRAMES_LOW_MAX_ENTRY	2
+#define RX_PAUSE_FRAMES_HIGH_MAX_ENTRY	2
+#define RX_FIFOOVERFLOW_FRAMES_LOW_MAX_ENTRY	2
+#define RX_FIFOOVERFLOW_FRAMES_HIGH_MAX_ENTRY	2
+#define RX_VLAN_FRAMES_GOOD_BAD_LOW_MAX_ENTRY	2
+#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define RX_WATCHDOG_ERROR_FRAMES_MAX_ENTRY	2
+#define RX_LPI_USEC_CNTR_MAX_ENTRY	2
+#define RX_LPI_TRAN_CNTR_MAX_ENTRY	2
+#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_MAX_ENTRY	2
+#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_MAX_ENTRY	2
+#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_MAX_ENTRY	2
+#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_MAX_ENTRY	2
+
+sw_error_t
+hppe_mmc_control_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_control_u *value);
+
+sw_error_t
+hppe_mmc_control_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_control_u *value);
+
+sw_error_t
+hppe_tx_octet_count_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_octet_count_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_octet_count_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_octet_count_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_frame_count_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_frame_count_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_frame_count_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_frame_count_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_low_u *value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_low_u *value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_high_u *value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_high_u *value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_low_u *value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_low_u *value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_high_u *value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_high_u *value);
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_64octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_64octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_64octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_64octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_65to127octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_65to127octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_65to127octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_65to127octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_128to255octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_128to255octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_128to255octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_128to255octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_256to511octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_256to511octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_256to511octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_256to511octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_512to1023octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_512to1023octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_512to1023octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_512to1023octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_1024tomaxoctets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_1024tomaxoctets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_1024tomaxoctets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_1024tomaxoctets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_unicast_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_unicast_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_unicast_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_unicast_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_tx_underflow_error_frames_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_underflow_error_frames_low_u *value);
+
+sw_error_t
+hppe_tx_underflow_error_frames_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_underflow_error_frames_low_u *value);
+
+sw_error_t
+hppe_tx_underflow_error_frames_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_underflow_error_frames_high_u *value);
+
+sw_error_t
+hppe_tx_underflow_error_frames_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_underflow_error_frames_high_u *value);
+
+sw_error_t
+hppe_tx_octet_count_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_low_u *value);
+
+sw_error_t
+hppe_tx_octet_count_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_low_u *value);
+
+sw_error_t
+hppe_tx_octet_count_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_high_u *value);
+
+sw_error_t
+hppe_tx_octet_count_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_high_u *value);
+
+sw_error_t
+hppe_tx_frame_count_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_low_u *value);
+
+sw_error_t
+hppe_tx_frame_count_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_low_u *value);
+
+sw_error_t
+hppe_tx_frame_count_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_high_u *value);
+
+sw_error_t
+hppe_tx_frame_count_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_high_u *value);
+
+sw_error_t
+hppe_tx_pause_frames_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_pause_frames_low_u *value);
+
+sw_error_t
+hppe_tx_pause_frames_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_pause_frames_low_u *value);
+
+sw_error_t
+hppe_tx_pause_frames_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_pause_frames_high_u *value);
+
+sw_error_t
+hppe_tx_pause_frames_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_pause_frames_high_u *value);
+
+sw_error_t
+hppe_tx_vlan_frames_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_vlan_frames_good_low_u *value);
+
+sw_error_t
+hppe_tx_vlan_frames_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_vlan_frames_good_low_u *value);
+
+sw_error_t
+hppe_tx_vlan_frames_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_vlan_frames_good_high_u *value);
+
+sw_error_t
+hppe_tx_vlan_frames_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_vlan_frames_good_high_u *value);
+
+sw_error_t
+hppe_tx_lpi_usec_cntr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_lpi_usec_cntr_u *value);
+
+sw_error_t
+hppe_tx_lpi_usec_cntr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_lpi_usec_cntr_u *value);
+
+sw_error_t
+hppe_tx_lpi_tran_cntr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_lpi_tran_cntr_u *value);
+
+sw_error_t
+hppe_tx_lpi_tran_cntr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_lpi_tran_cntr_u *value);
+
+sw_error_t
+hppe_rx_frame_count_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_frame_count_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_frame_count_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_frame_count_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_frame_count_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_frame_count_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_frame_count_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_frame_count_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_octet_count_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_octet_count_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_octet_count_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_octet_count_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_octet_count_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_low_u *value);
+
+sw_error_t
+hppe_rx_octet_count_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_low_u *value);
+
+sw_error_t
+hppe_rx_octet_count_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_high_u *value);
+
+sw_error_t
+hppe_rx_octet_count_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_high_u *value);
+
+sw_error_t
+hppe_rx_broadcast_frames_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_broadcast_frames_good_low_u *value);
+
+sw_error_t
+hppe_rx_broadcast_frames_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_broadcast_frames_good_low_u *value);
+
+sw_error_t
+hppe_rx_broadcast_frames_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_broadcast_frames_good_high_u *value);
+
+sw_error_t
+hppe_rx_broadcast_frames_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_broadcast_frames_good_high_u *value);
+
+sw_error_t
+hppe_rx_multicast_frames_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_multicast_frames_good_low_u *value);
+
+sw_error_t
+hppe_rx_multicast_frames_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_multicast_frames_good_low_u *value);
+
+sw_error_t
+hppe_rx_multicast_frames_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_multicast_frames_good_high_u *value);
+
+sw_error_t
+hppe_rx_multicast_frames_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_multicast_frames_good_high_u *value);
+
+sw_error_t
+hppe_rx_crc_error_frames_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_crc_error_frames_low_u *value);
+
+sw_error_t
+hppe_rx_crc_error_frames_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_crc_error_frames_low_u *value);
+
+sw_error_t
+hppe_rx_crc_error_frames_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_crc_error_frames_high_u *value);
+
+sw_error_t
+hppe_rx_crc_error_frames_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_crc_error_frames_high_u *value);
+
+sw_error_t
+hppe_rx_runt_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_runt_error_frames_u *value);
+
+sw_error_t
+hppe_rx_runt_error_frames_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_runt_error_frames_u *value);
+
+sw_error_t
+hppe_rx_jabber_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_jabber_error_frames_u *value);
+
+sw_error_t
+hppe_rx_jabber_error_frames_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_jabber_error_frames_u *value);
+
+sw_error_t
+hppe_rx_undersize_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_undersize_frames_good_u *value);
+
+sw_error_t
+hppe_rx_undersize_frames_good_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_undersize_frames_good_u *value);
+
+sw_error_t
+hppe_rx_oversize_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_oversize_frames_good_u *value);
+
+sw_error_t
+hppe_rx_oversize_frames_good_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_oversize_frames_good_u *value);
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_64octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_64octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_64octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_64octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_65to127octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_65to127octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_65to127octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_65to127octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_128to255octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_128to255octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_128to255octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_128to255octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_256to511octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_256to511octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_256to511octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_256to511octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_512to1023octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_512to1023octets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_512to1023octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_512to1023octets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_1024tomaxoctets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_1024tomaxoctets_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_1024tomaxoctets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_1024tomaxoctets_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_unicast_frames_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_unicast_frames_good_low_u *value);
+
+sw_error_t
+hppe_rx_unicast_frames_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_unicast_frames_good_low_u *value);
+
+sw_error_t
+hppe_rx_unicast_frames_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_unicast_frames_good_high_u *value);
+
+sw_error_t
+hppe_rx_unicast_frames_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_unicast_frames_good_high_u *value);
+
+sw_error_t
+hppe_rx_length_error_frames_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_length_error_frames_low_u *value);
+
+sw_error_t
+hppe_rx_length_error_frames_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_length_error_frames_low_u *value);
+
+sw_error_t
+hppe_rx_length_error_frames_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_length_error_frames_high_u *value);
+
+sw_error_t
+hppe_rx_length_error_frames_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_length_error_frames_high_u *value);
+
+sw_error_t
+hppe_rx_outofrange_frames_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_outofrange_frames_low_u *value);
+
+sw_error_t
+hppe_rx_outofrange_frames_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_outofrange_frames_low_u *value);
+
+sw_error_t
+hppe_rx_outofrange_frames_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_outofrange_frames_high_u *value);
+
+sw_error_t
+hppe_rx_outofrange_frames_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_outofrange_frames_high_u *value);
+
+sw_error_t
+hppe_rx_pause_frames_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_pause_frames_low_u *value);
+
+sw_error_t
+hppe_rx_pause_frames_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_pause_frames_low_u *value);
+
+sw_error_t
+hppe_rx_pause_frames_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_pause_frames_high_u *value);
+
+sw_error_t
+hppe_rx_pause_frames_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_pause_frames_high_u *value);
+
+sw_error_t
+hppe_rx_fifooverflow_frames_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_fifooverflow_frames_low_u *value);
+
+sw_error_t
+hppe_rx_fifooverflow_frames_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_fifooverflow_frames_low_u *value);
+
+sw_error_t
+hppe_rx_fifooverflow_frames_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_fifooverflow_frames_high_u *value);
+
+sw_error_t
+hppe_rx_fifooverflow_frames_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_fifooverflow_frames_high_u *value);
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_vlan_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_vlan_frames_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_vlan_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_vlan_frames_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_watchdog_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_watchdog_error_frames_u *value);
+
+sw_error_t
+hppe_rx_watchdog_error_frames_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_watchdog_error_frames_u *value);
+
+sw_error_t
+hppe_rx_lpi_usec_cntr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_lpi_usec_cntr_u *value);
+
+sw_error_t
+hppe_rx_lpi_usec_cntr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_lpi_usec_cntr_u *value);
+
+sw_error_t
+hppe_rx_lpi_tran_cntr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_lpi_tran_cntr_u *value);
+
+sw_error_t
+hppe_rx_lpi_tran_cntr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_lpi_tran_cntr_u *value);
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_frame_count_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_frame_count_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_frame_count_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_frame_count_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_octet_count_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_octet_count_good_bad_low_u *value);
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_octet_count_good_bad_high_u *value);
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_octet_count_good_bad_high_u *value);
+
+
+sw_error_t
+hppe_mmc_control_cntrst_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_control_cntrst_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_control_rstonrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_control_rstonrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_control_cntstopro_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_control_cntstopro_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_control_mct_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_control_mct_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_control_pr_mmc_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_control_pr_mmc_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_control_cntprst_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_control_cntprst_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_control_mcf_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_control_mcf_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_octet_count_good_bad_low_txoctgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_octet_count_good_bad_low_txoctgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_octet_count_good_bad_high_txoctgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_octet_count_good_bad_high_txoctgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_frame_count_good_bad_low_txfrmgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_frame_count_good_bad_low_txfrmgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_frame_count_good_bad_high_txfrmgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_frame_count_good_bad_high_txfrmgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_low_txbcastglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_low_txbcastglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_high_txbcastghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_high_txbcastghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_low_txmcastglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_low_txmcastglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_high_txmcastghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_high_txmcastghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_low_tx64octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_low_tx64octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_high_tx64octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_high_tx64octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_low_tx65_127octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_low_tx65_127octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_high_tx65_127octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_high_tx65_127octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_low_tx128_255octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_low_tx128_255octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_high_tx128_255octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_high_tx128_255octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_low_tx256_511octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_low_tx256_511octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_high_tx256_511octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_high_tx256_511octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_low_tx512_1023octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_low_tx512_1023octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_high_tx512_1023octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_high_tx512_1023octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_low_tx1024_maxoctgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_low_tx1024_maxoctgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_high_tx1024_maxoctgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_high_tx1024_maxoctgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_low_txucastgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_low_txucastgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_high_txucastgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_high_txucastgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_low_txmcastgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_low_txmcastgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_high_txmcastgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_high_txmcastgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_low_txbcastgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_low_txbcastgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_high_txbcastgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_high_txbcastgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_underflow_error_frames_low_txundrflwlo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_underflow_error_frames_low_txundrflwlo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_underflow_error_frames_high_txundrflwhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_underflow_error_frames_high_txundrflwhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_octet_count_good_low_txoctglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_octet_count_good_low_txoctglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_octet_count_good_high_txoctghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_octet_count_good_high_txoctghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_frame_count_good_low_txfrmglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_frame_count_good_low_txfrmglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_frame_count_good_high_txfrmghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_frame_count_good_high_txfrmghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_pause_frames_low_txpauseglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_pause_frames_low_txpauseglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_pause_frames_high_txpauseghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_pause_frames_high_txpauseghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_vlan_frames_good_low_txvlanglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_vlan_frames_good_low_txvlanglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_vlan_frames_good_high_txvlanghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_vlan_frames_good_high_txvlanghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_lpi_usec_cntr_txlpiusc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_lpi_usec_cntr_txlpiusc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_tx_lpi_tran_cntr_txlpitrc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_tx_lpi_tran_cntr_txlpitrc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_frame_count_good_bad_low_rxfrmgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_frame_count_good_bad_low_rxfrmgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_frame_count_good_bad_high_rxfrmgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_frame_count_good_bad_high_rxfrmgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_octet_count_good_bad_low_rxoctgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_octet_count_good_bad_low_rxoctgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_octet_count_good_bad_high_rxoctgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_octet_count_good_bad_high_rxoctgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_octet_count_good_low_rxoctglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_octet_count_good_low_rxoctglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_octet_count_good_high_rxoctghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_octet_count_good_high_rxoctghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_broadcast_frames_good_low_rxbcastglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_broadcast_frames_good_low_rxbcastglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_broadcast_frames_good_high_rxbcastghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_broadcast_frames_good_high_rxbcastghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_multicast_frames_good_low_rxmcastglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_multicast_frames_good_low_rxmcastglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_multicast_frames_good_high_rxmcastghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_multicast_frames_good_high_rxmcastghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_crc_error_frames_low_rxcrcerlo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_crc_error_frames_low_rxcrcerlo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_crc_error_frames_high_rxcrcerhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_crc_error_frames_high_rxcrcerhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_runt_error_frames_rxrunter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_runt_error_frames_rxrunter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_jabber_error_frames_rxjaberer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_jabber_error_frames_rxjaberer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_undersize_frames_good_rxusizeg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_undersize_frames_good_rxusizeg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_oversize_frames_good_rxosizeg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_oversize_frames_good_rxosizeg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_low_rx64octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_low_rx64octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_high_rx64octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_high_rx64octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_low_rx65_127octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_low_rx65_127octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_high_rx65_127octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_high_rx65_127octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_low_rx128_255octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_low_rx128_255octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_high_rx128_255octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_high_rx128_255octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_low_rx256_511octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_low_rx256_511octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_high_rx256_511octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_high_rx256_511octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_low_rx512_1023octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_low_rx512_1023octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_high_rx512_1023octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_high_rx512_1023octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_low_rx1024_maxgboctlo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_low_rx1024_maxgboctlo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_high_rx1024_maxgbocthi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_high_rx1024_maxgbocthi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_unicast_frames_good_low_rxucastglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_unicast_frames_good_low_rxucastglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_unicast_frames_good_high_rxucastghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_unicast_frames_good_high_rxucastghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_length_error_frames_low_rxlenerrlo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_length_error_frames_low_rxlenerrlo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_length_error_frames_high_rxlenerrhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_length_error_frames_high_rxlenerrhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_outofrange_frames_low_rxorangelo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_outofrange_frames_low_rxorangelo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_outofrange_frames_high_rxorangehi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_outofrange_frames_high_rxorangehi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_pause_frames_low_rxpauselo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_pause_frames_low_rxpauselo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_pause_frames_high_rxpausehi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_pause_frames_high_rxpausehi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_fifooverflow_frames_low_rxfovflo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_fifooverflow_frames_low_rxfovflo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_fifooverflow_frames_high_rxfovfhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_fifooverflow_frames_high_rxfovfhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_low_rxvlangblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_low_rxvlangblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_high_rxvlangbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_high_rxvlangbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_watchdog_error_frames_rxwdogerr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_watchdog_error_frames_rxwdogerr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_lpi_usec_cntr_rxlpiusc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_lpi_usec_cntr_rxlpiusc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_lpi_tran_cntr_rxlpitrc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_lpi_tran_cntr_rxlpitrc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_low_rxdfcntgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_low_rxdfcntgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_high_rxdfcntgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_high_rxdfcntgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_low_rxdocntgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_low_rxdocntgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_high_rxdocntgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_high_rxdocntgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_xgmacmib_reg.h b/qca-ssdk/include/hsl/hppe/hppe_xgmacmib_reg.h
new file mode 100755
index 0000000..8059aeb
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_xgmacmib_reg.h
@@ -0,0 +1,1956 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_XGMACMIB_REG_H
+#define HPPE_XGMACMIB_REG_H
+
+/*[register] MMC_CONTROL*/
+#define MMC_CONTROL
+#define MMC_CONTROL_ADDRESS 0x800
+#define MMC_CONTROL_NUM     2
+#define MMC_CONTROL_INC     0x4000
+#define MMC_CONTROL_TYPE    REG_TYPE_RO
+#define MMC_CONTROL_DEFAULT 0x0
+	/*[field] CNTRST*/
+	#define MMC_CONTROL_CNTRST
+	#define MMC_CONTROL_CNTRST_OFFSET  0
+	#define MMC_CONTROL_CNTRST_LEN     1
+	#define MMC_CONTROL_CNTRST_DEFAULT 0x0
+	/*[field] CNTSTOPRO*/
+	#define MMC_CONTROL_CNTSTOPRO
+	#define MMC_CONTROL_CNTSTOPRO_OFFSET  1
+	#define MMC_CONTROL_CNTSTOPRO_LEN     1
+	#define MMC_CONTROL_CNTSTOPRO_DEFAULT 0x0
+	/*[field] RSTONRD*/
+	#define MMC_CONTROL_RSTONRD
+	#define MMC_CONTROL_RSTONRD_OFFSET  2
+	#define MMC_CONTROL_RSTONRD_LEN     1
+	#define MMC_CONTROL_RSTONRD_DEFAULT 0x0
+	/*[field] MCF*/
+	#define MMC_CONTROL_MCF
+	#define MMC_CONTROL_MCF_OFFSET  3
+	#define MMC_CONTROL_MCF_LEN     1
+	#define MMC_CONTROL_MCF_DEFAULT 0x0
+	/*[field] MCT*/
+	#define MMC_CONTROL_MCT
+	#define MMC_CONTROL_MCT_OFFSET  4
+	#define MMC_CONTROL_MCT_LEN     2
+	#define MMC_CONTROL_MCT_DEFAULT 0x0
+	/*[field] CNTPRST*/
+	#define MMC_CONTROL_CNTPRST
+	#define MMC_CONTROL_CNTPRST_OFFSET  7
+	#define MMC_CONTROL_CNTPRST_LEN     1
+	#define MMC_CONTROL_CNTPRST_DEFAULT 0x0
+	/*[field] PR_MMC_SEL*/
+	#define MMC_CONTROL_PR_MMC_SEL
+	#define MMC_CONTROL_PR_MMC_SEL_OFFSET  16
+	#define MMC_CONTROL_PR_MMC_SEL_LEN     3
+	#define MMC_CONTROL_PR_MMC_SEL_DEFAULT 0x0
+
+struct mmc_control {
+	a_uint32_t  cntrst:1;
+	a_uint32_t  cntstopro:1;
+	a_uint32_t  rstonrd:1;
+	a_uint32_t  mcf:1;
+	a_uint32_t  mct:2;
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  cntprst:1;
+	a_uint32_t  _reserved1:8;
+	a_uint32_t  pr_mmc_sel:3;
+	a_uint32_t  _reserved2:13;
+};
+
+union mmc_control_u {
+	a_uint32_t val;
+	struct mmc_control bf;
+};
+
+/*[register] TX_OCTET_COUNT_GOOD_BAD_LOW*/
+#define TX_OCTET_COUNT_GOOD_BAD_LOW
+#define TX_OCTET_COUNT_GOOD_BAD_LOW_ADDRESS 0x814
+#define TX_OCTET_COUNT_GOOD_BAD_LOW_NUM     2
+#define TX_OCTET_COUNT_GOOD_BAD_LOW_INC     0x4000
+#define TX_OCTET_COUNT_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define TX_OCTET_COUNT_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] TXOCTGBLO*/
+	#define TX_OCTET_COUNT_GOOD_BAD_LOW_TXOCTGBLO
+	#define TX_OCTET_COUNT_GOOD_BAD_LOW_TXOCTGBLO_OFFSET  0
+	#define TX_OCTET_COUNT_GOOD_BAD_LOW_TXOCTGBLO_LEN     32
+	#define TX_OCTET_COUNT_GOOD_BAD_LOW_TXOCTGBLO_DEFAULT 0x0
+
+struct tx_octet_count_good_bad_low {
+	a_uint32_t  txoctgblo:32;
+};
+
+union tx_octet_count_good_bad_low_u {
+	a_uint32_t val;
+	struct tx_octet_count_good_bad_low bf;
+};
+
+/*[register] TX_OCTET_COUNT_GOOD_BAD_HIGH*/
+#define TX_OCTET_COUNT_GOOD_BAD_HIGH
+#define TX_OCTET_COUNT_GOOD_BAD_HIGH_ADDRESS 0x818
+#define TX_OCTET_COUNT_GOOD_BAD_HIGH_NUM     2
+#define TX_OCTET_COUNT_GOOD_BAD_HIGH_INC     0x4000
+#define TX_OCTET_COUNT_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define TX_OCTET_COUNT_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] TXOCTGBHI*/
+	#define TX_OCTET_COUNT_GOOD_BAD_HIGH_TXOCTGBHI
+	#define TX_OCTET_COUNT_GOOD_BAD_HIGH_TXOCTGBHI_OFFSET  0
+	#define TX_OCTET_COUNT_GOOD_BAD_HIGH_TXOCTGBHI_LEN     32
+	#define TX_OCTET_COUNT_GOOD_BAD_HIGH_TXOCTGBHI_DEFAULT 0x0
+
+struct tx_octet_count_good_bad_high {
+	a_uint32_t  txoctgbhi:32;
+};
+
+union tx_octet_count_good_bad_high_u {
+	a_uint32_t val;
+	struct tx_octet_count_good_bad_high bf;
+};
+
+/*[register] TX_FRAME_COUNT_GOOD_BAD_LOW*/
+#define TX_FRAME_COUNT_GOOD_BAD_LOW
+#define TX_FRAME_COUNT_GOOD_BAD_LOW_ADDRESS 0x81c
+#define TX_FRAME_COUNT_GOOD_BAD_LOW_NUM     2
+#define TX_FRAME_COUNT_GOOD_BAD_LOW_INC     0x4000
+#define TX_FRAME_COUNT_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define TX_FRAME_COUNT_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] TXFRMGBLO*/
+	#define TX_FRAME_COUNT_GOOD_BAD_LOW_TXFRMGBLO
+	#define TX_FRAME_COUNT_GOOD_BAD_LOW_TXFRMGBLO_OFFSET  0
+	#define TX_FRAME_COUNT_GOOD_BAD_LOW_TXFRMGBLO_LEN     32
+	#define TX_FRAME_COUNT_GOOD_BAD_LOW_TXFRMGBLO_DEFAULT 0x0
+
+struct tx_frame_count_good_bad_low {
+	a_uint32_t  txfrmgblo:32;
+};
+
+union tx_frame_count_good_bad_low_u {
+	a_uint32_t val;
+	struct tx_frame_count_good_bad_low bf;
+};
+
+/*[register] TX_FRAME_COUNT_GOOD_BAD_HIGH*/
+#define TX_FRAME_COUNT_GOOD_BAD_HIGH
+#define TX_FRAME_COUNT_GOOD_BAD_HIGH_ADDRESS 0x820
+#define TX_FRAME_COUNT_GOOD_BAD_HIGH_NUM     2
+#define TX_FRAME_COUNT_GOOD_BAD_HIGH_INC     0x4000
+#define TX_FRAME_COUNT_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define TX_FRAME_COUNT_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] TXFRMGBHI*/
+	#define TX_FRAME_COUNT_GOOD_BAD_HIGH_TXFRMGBHI
+	#define TX_FRAME_COUNT_GOOD_BAD_HIGH_TXFRMGBHI_OFFSET  0
+	#define TX_FRAME_COUNT_GOOD_BAD_HIGH_TXFRMGBHI_LEN     32
+	#define TX_FRAME_COUNT_GOOD_BAD_HIGH_TXFRMGBHI_DEFAULT 0x0
+
+struct tx_frame_count_good_bad_high {
+	a_uint32_t  txfrmgbhi:32;
+};
+
+union tx_frame_count_good_bad_high_u {
+	a_uint32_t val;
+	struct tx_frame_count_good_bad_high bf;
+};
+
+/*[register] TX_BROADCAST_FRAMES_GOOD_LOW*/
+#define TX_BROADCAST_FRAMES_GOOD_LOW
+#define TX_BROADCAST_FRAMES_GOOD_LOW_ADDRESS 0x824
+#define TX_BROADCAST_FRAMES_GOOD_LOW_NUM     2
+#define TX_BROADCAST_FRAMES_GOOD_LOW_INC     0x4000
+#define TX_BROADCAST_FRAMES_GOOD_LOW_TYPE    REG_TYPE_RO
+#define TX_BROADCAST_FRAMES_GOOD_LOW_DEFAULT 0x0
+	/*[field] TXBCASTGLO*/
+	#define TX_BROADCAST_FRAMES_GOOD_LOW_TXBCASTGLO
+	#define TX_BROADCAST_FRAMES_GOOD_LOW_TXBCASTGLO_OFFSET  0
+	#define TX_BROADCAST_FRAMES_GOOD_LOW_TXBCASTGLO_LEN     32
+	#define TX_BROADCAST_FRAMES_GOOD_LOW_TXBCASTGLO_DEFAULT 0x0
+
+struct tx_broadcast_frames_good_low {
+	a_uint32_t  txbcastglo:32;
+};
+
+union tx_broadcast_frames_good_low_u {
+	a_uint32_t val;
+	struct tx_broadcast_frames_good_low bf;
+};
+
+/*[register] TX_BROADCAST_FRAMES_GOOD_HIGH*/
+#define TX_BROADCAST_FRAMES_GOOD_HIGH
+#define TX_BROADCAST_FRAMES_GOOD_HIGH_ADDRESS 0x828
+#define TX_BROADCAST_FRAMES_GOOD_HIGH_NUM     2
+#define TX_BROADCAST_FRAMES_GOOD_HIGH_INC     0x4000
+#define TX_BROADCAST_FRAMES_GOOD_HIGH_TYPE    REG_TYPE_RO
+#define TX_BROADCAST_FRAMES_GOOD_HIGH_DEFAULT 0x0
+	/*[field] TXBCASTGHI*/
+	#define TX_BROADCAST_FRAMES_GOOD_HIGH_TXBCASTGHI
+	#define TX_BROADCAST_FRAMES_GOOD_HIGH_TXBCASTGHI_OFFSET  0
+	#define TX_BROADCAST_FRAMES_GOOD_HIGH_TXBCASTGHI_LEN     32
+	#define TX_BROADCAST_FRAMES_GOOD_HIGH_TXBCASTGHI_DEFAULT 0x0
+
+struct tx_broadcast_frames_good_high {
+	a_uint32_t  txbcastghi:32;
+};
+
+union tx_broadcast_frames_good_high_u {
+	a_uint32_t val;
+	struct tx_broadcast_frames_good_high bf;
+};
+
+/*[register] TX_MULTICAST_FRAMES_GOOD_LOW*/
+#define TX_MULTICAST_FRAMES_GOOD_LOW
+#define TX_MULTICAST_FRAMES_GOOD_LOW_ADDRESS 0x82c
+#define TX_MULTICAST_FRAMES_GOOD_LOW_NUM     2
+#define TX_MULTICAST_FRAMES_GOOD_LOW_INC     0x4000
+#define TX_MULTICAST_FRAMES_GOOD_LOW_TYPE    REG_TYPE_RO
+#define TX_MULTICAST_FRAMES_GOOD_LOW_DEFAULT 0x0
+	/*[field] TXMCASTGLO*/
+	#define TX_MULTICAST_FRAMES_GOOD_LOW_TXMCASTGLO
+	#define TX_MULTICAST_FRAMES_GOOD_LOW_TXMCASTGLO_OFFSET  0
+	#define TX_MULTICAST_FRAMES_GOOD_LOW_TXMCASTGLO_LEN     32
+	#define TX_MULTICAST_FRAMES_GOOD_LOW_TXMCASTGLO_DEFAULT 0x0
+
+struct tx_multicast_frames_good_low {
+	a_uint32_t  txmcastglo:32;
+};
+
+union tx_multicast_frames_good_low_u {
+	a_uint32_t val;
+	struct tx_multicast_frames_good_low bf;
+};
+
+/*[register] TX_MULTICAST_FRAMES_GOOD_HIGH*/
+#define TX_MULTICAST_FRAMES_GOOD_HIGH
+#define TX_MULTICAST_FRAMES_GOOD_HIGH_ADDRESS 0x830
+#define TX_MULTICAST_FRAMES_GOOD_HIGH_NUM     2
+#define TX_MULTICAST_FRAMES_GOOD_HIGH_INC     0x4000
+#define TX_MULTICAST_FRAMES_GOOD_HIGH_TYPE    REG_TYPE_RO
+#define TX_MULTICAST_FRAMES_GOOD_HIGH_DEFAULT 0x0
+	/*[field] TXMCASTGHI*/
+	#define TX_MULTICAST_FRAMES_GOOD_HIGH_TXMCASTGHI
+	#define TX_MULTICAST_FRAMES_GOOD_HIGH_TXMCASTGHI_OFFSET  0
+	#define TX_MULTICAST_FRAMES_GOOD_HIGH_TXMCASTGHI_LEN     32
+	#define TX_MULTICAST_FRAMES_GOOD_HIGH_TXMCASTGHI_DEFAULT 0x0
+
+struct tx_multicast_frames_good_high {
+	a_uint32_t  txmcastghi:32;
+};
+
+union tx_multicast_frames_good_high_u {
+	a_uint32_t val;
+	struct tx_multicast_frames_good_high bf;
+};
+
+/*[register] TX_64OCTETS_FRAMES_GOOD_BAD_LOW*/
+#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW
+#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x834
+#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_NUM     2
+#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] TX64OCTGBLO*/
+	#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_TX64OCTGBLO
+	#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_TX64OCTGBLO_OFFSET  0
+	#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_TX64OCTGBLO_LEN     32
+	#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_TX64OCTGBLO_DEFAULT 0x0
+
+struct tx_64octets_frames_good_bad_low {
+	a_uint32_t  tx64octgblo:32;
+};
+
+union tx_64octets_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct tx_64octets_frames_good_bad_low bf;
+};
+
+/*[register] TX_64OCTETS_FRAMES_GOOD_BAD_HIGH*/
+#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH
+#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x838
+#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_NUM     2
+#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] TX64OCTGBHI*/
+	#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_TX64OCTGBHI
+	#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_TX64OCTGBHI_OFFSET  0
+	#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_TX64OCTGBHI_LEN     32
+	#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_TX64OCTGBHI_DEFAULT 0x0
+
+struct tx_64octets_frames_good_bad_high {
+	a_uint32_t  tx64octgbhi:32;
+};
+
+union tx_64octets_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct tx_64octets_frames_good_bad_high bf;
+};
+
+/*[register] TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW*/
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x83c
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_NUM     2
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] TX65_127OCTGBLO*/
+	#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_TX65_127OCTGBLO
+	#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_TX65_127OCTGBLO_OFFSET  0
+	#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_TX65_127OCTGBLO_LEN     32
+	#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_TX65_127OCTGBLO_DEFAULT 0x0
+
+struct tx_65to127octets_frames_good_bad_low {
+	a_uint32_t  tx65_127octgblo:32;
+};
+
+union tx_65to127octets_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct tx_65to127octets_frames_good_bad_low bf;
+};
+
+/*[register] TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH*/
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x840
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_NUM     2
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] TX65_127OCTGBHI*/
+	#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_TX65_127OCTGBHI
+	#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_TX65_127OCTGBHI_OFFSET  0
+	#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_TX65_127OCTGBHI_LEN     32
+	#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_TX65_127OCTGBHI_DEFAULT 0x0
+
+struct tx_65to127octets_frames_good_bad_high {
+	a_uint32_t  tx65_127octgbhi:32;
+};
+
+union tx_65to127octets_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct tx_65to127octets_frames_good_bad_high bf;
+};
+
+/*[register] TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW*/
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x844
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_NUM     2
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] TX128_255OCTGBLO*/
+	#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_TX128_255OCTGBLO
+	#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_TX128_255OCTGBLO_OFFSET  0
+	#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_TX128_255OCTGBLO_LEN     32
+	#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_TX128_255OCTGBLO_DEFAULT 0x0
+
+struct tx_128to255octets_frames_good_bad_low {
+	a_uint32_t  tx128_255octgblo:32;
+};
+
+union tx_128to255octets_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct tx_128to255octets_frames_good_bad_low bf;
+};
+
+/*[register] TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH*/
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x848
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_NUM     2
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] TX128_255OCTGBHI*/
+	#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_TX128_255OCTGBHI
+	#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_TX128_255OCTGBHI_OFFSET  0
+	#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_TX128_255OCTGBHI_LEN     32
+	#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_TX128_255OCTGBHI_DEFAULT 0x0
+
+struct tx_128to255octets_frames_good_bad_high {
+	a_uint32_t  tx128_255octgbhi:32;
+};
+
+union tx_128to255octets_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct tx_128to255octets_frames_good_bad_high bf;
+};
+
+/*[register] TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW*/
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x84c
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_NUM     1
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] TX256_511OCTGBLO*/
+	#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_TX256_511OCTGBLO
+	#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_TX256_511OCTGBLO_OFFSET  0
+	#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_TX256_511OCTGBLO_LEN     32
+	#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_TX256_511OCTGBLO_DEFAULT 0x0
+
+struct tx_256to511octets_frames_good_bad_low {
+	a_uint32_t  tx256_511octgblo:32;
+};
+
+union tx_256to511octets_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct tx_256to511octets_frames_good_bad_low bf;
+};
+
+/*[register] TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH*/
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x850
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_NUM     1
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] TX256_511OCTGBHI*/
+	#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_TX256_511OCTGBHI
+	#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_TX256_511OCTGBHI_OFFSET  0
+	#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_TX256_511OCTGBHI_LEN     32
+	#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_TX256_511OCTGBHI_DEFAULT 0x0
+
+struct tx_256to511octets_frames_good_bad_high {
+	a_uint32_t  tx256_511octgbhi:32;
+};
+
+union tx_256to511octets_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct tx_256to511octets_frames_good_bad_high bf;
+};
+
+/*[register] TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW*/
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x854
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_NUM     1
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] TX512_1023OCTGBLO*/
+	#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_TX512_1023OCTGBLO
+	#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_TX512_1023OCTGBLO_OFFSET  0
+	#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_TX512_1023OCTGBLO_LEN     32
+	#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_TX512_1023OCTGBLO_DEFAULT 0x0
+
+struct tx_512to1023octets_frames_good_bad_low {
+	a_uint32_t  tx512_1023octgblo:32;
+};
+
+union tx_512to1023octets_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct tx_512to1023octets_frames_good_bad_low bf;
+};
+
+/*[register] TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH*/
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x858
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_NUM     1
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] TX512_1023OCTGBHI*/
+	#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_TX512_1023OCTGBHI
+	#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_TX512_1023OCTGBHI_OFFSET  0
+	#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_TX512_1023OCTGBHI_LEN     32
+	#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_TX512_1023OCTGBHI_DEFAULT 0x0
+
+struct tx_512to1023octets_frames_good_bad_high {
+	a_uint32_t  tx512_1023octgbhi:32;
+};
+
+union tx_512to1023octets_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct tx_512to1023octets_frames_good_bad_high bf;
+};
+
+/*[register] TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW*/
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x85c
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_NUM     1
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] TX1024_MAXOCTGBLO*/
+	#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_TX1024_MAXOCTGBLO
+	#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_TX1024_MAXOCTGBLO_OFFSET  0
+	#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_TX1024_MAXOCTGBLO_LEN     32
+	#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_TX1024_MAXOCTGBLO_DEFAULT 0x0
+
+struct tx_1024tomaxoctets_frames_good_bad_low {
+	a_uint32_t  tx1024_maxoctgblo:32;
+};
+
+union tx_1024tomaxoctets_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct tx_1024tomaxoctets_frames_good_bad_low bf;
+};
+
+/*[register] TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH*/
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x860
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_NUM     1
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] TX1024_MAXOCTGBHI*/
+	#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_TX1024_MAXOCTGBHI
+	#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_TX1024_MAXOCTGBHI_OFFSET  0
+	#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_TX1024_MAXOCTGBHI_LEN     32
+	#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_TX1024_MAXOCTGBHI_DEFAULT 0x0
+
+struct tx_1024tomaxoctets_frames_good_bad_high {
+	a_uint32_t  tx1024_maxoctgbhi:32;
+};
+
+union tx_1024tomaxoctets_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct tx_1024tomaxoctets_frames_good_bad_high bf;
+};
+
+/*[register] TX_UNICAST_FRAMES_GOOD_BAD_LOW*/
+#define TX_UNICAST_FRAMES_GOOD_BAD_LOW
+#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_ADDRESS 0x864
+#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_NUM     1
+#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] TXUCASTGBLO*/
+	#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_TXUCASTGBLO
+	#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_TXUCASTGBLO_OFFSET  0
+	#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_TXUCASTGBLO_LEN     32
+	#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_TXUCASTGBLO_DEFAULT 0x0
+
+struct tx_unicast_frames_good_bad_low {
+	a_uint32_t  txucastgblo:32;
+};
+
+union tx_unicast_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct tx_unicast_frames_good_bad_low bf;
+};
+
+/*[register] TX_UNICAST_FRAMES_GOOD_BAD_HIGH*/
+#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH
+#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x868
+#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_NUM     1
+#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] TXUCASTGBHI*/
+	#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_TXUCASTGBHI
+	#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_TXUCASTGBHI_OFFSET  0
+	#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_TXUCASTGBHI_LEN     32
+	#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_TXUCASTGBHI_DEFAULT 0x0
+
+struct tx_unicast_frames_good_bad_high {
+	a_uint32_t  txucastgbhi:32;
+};
+
+union tx_unicast_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct tx_unicast_frames_good_bad_high bf;
+};
+
+/*[register] TX_MULTICAST_FRAMES_GOOD_BAD_LOW*/
+#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW
+#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_ADDRESS 0x86c
+#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_NUM     1
+#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] TXMCASTGBLO*/
+	#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_TXMCASTGBLO
+	#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_TXMCASTGBLO_OFFSET  0
+	#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_TXMCASTGBLO_LEN     32
+	#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_TXMCASTGBLO_DEFAULT 0x0
+
+struct tx_multicast_frames_good_bad_low {
+	a_uint32_t  txmcastgblo:32;
+};
+
+union tx_multicast_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct tx_multicast_frames_good_bad_low bf;
+};
+
+/*[register] TX_MULTICAST_FRAMES_GOOD_BAD_HIGH*/
+#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH
+#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x870
+#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_NUM     1
+#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] TXMCASTGBHI*/
+	#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_TXMCASTGBHI
+	#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_TXMCASTGBHI_OFFSET  0
+	#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_TXMCASTGBHI_LEN     32
+	#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_TXMCASTGBHI_DEFAULT 0x0
+
+struct tx_multicast_frames_good_bad_high {
+	a_uint32_t  txmcastgbhi:32;
+};
+
+union tx_multicast_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct tx_multicast_frames_good_bad_high bf;
+};
+
+/*[register] TX_BROADCAST_FRAMES_GOOD_BAD_LOW*/
+#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW
+#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_ADDRESS 0x874
+#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_NUM     1
+#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] TXBCASTGBLO*/
+	#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_TXBCASTGBLO
+	#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_TXBCASTGBLO_OFFSET  0
+	#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_TXBCASTGBLO_LEN     32
+	#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_TXBCASTGBLO_DEFAULT 0x0
+
+struct tx_broadcast_frames_good_bad_low {
+	a_uint32_t  txbcastgblo:32;
+};
+
+union tx_broadcast_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct tx_broadcast_frames_good_bad_low bf;
+};
+
+/*[register] TX_BROADCAST_FRAMES_GOOD_BAD_HIGH*/
+#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH
+#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x878
+#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_NUM     1
+#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] TXBCASTGBHI*/
+	#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_TXBCASTGBHI
+	#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_TXBCASTGBHI_OFFSET  0
+	#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_TXBCASTGBHI_LEN     32
+	#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_TXBCASTGBHI_DEFAULT 0x0
+
+struct tx_broadcast_frames_good_bad_high {
+	a_uint32_t  txbcastgbhi:32;
+};
+
+union tx_broadcast_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct tx_broadcast_frames_good_bad_high bf;
+};
+
+/*[register] TX_UNDERFLOW_ERROR_FRAMES_LOW*/
+#define TX_UNDERFLOW_ERROR_FRAMES_LOW
+#define TX_UNDERFLOW_ERROR_FRAMES_LOW_ADDRESS 0x87c
+#define TX_UNDERFLOW_ERROR_FRAMES_LOW_NUM     1
+#define TX_UNDERFLOW_ERROR_FRAMES_LOW_INC     0x4000
+#define TX_UNDERFLOW_ERROR_FRAMES_LOW_TYPE    REG_TYPE_RO
+#define TX_UNDERFLOW_ERROR_FRAMES_LOW_DEFAULT 0x0
+	/*[field] TXUNDRFLWLO*/
+	#define TX_UNDERFLOW_ERROR_FRAMES_LOW_TXUNDRFLWLO
+	#define TX_UNDERFLOW_ERROR_FRAMES_LOW_TXUNDRFLWLO_OFFSET  0
+	#define TX_UNDERFLOW_ERROR_FRAMES_LOW_TXUNDRFLWLO_LEN     32
+	#define TX_UNDERFLOW_ERROR_FRAMES_LOW_TXUNDRFLWLO_DEFAULT 0x0
+
+struct tx_underflow_error_frames_low {
+	a_uint32_t  txundrflwlo:32;
+};
+
+union tx_underflow_error_frames_low_u {
+	a_uint32_t val;
+	struct tx_underflow_error_frames_low bf;
+};
+
+/*[register] TX_UNDERFLOW_ERROR_FRAMES_HIGH*/
+#define TX_UNDERFLOW_ERROR_FRAMES_HIGH
+#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_ADDRESS 0x880
+#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_NUM     1
+#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_INC     0x4000
+#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_TYPE    REG_TYPE_RO
+#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_DEFAULT 0x0
+	/*[field] TXUNDRFLWHI*/
+	#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_TXUNDRFLWHI
+	#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_TXUNDRFLWHI_OFFSET  0
+	#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_TXUNDRFLWHI_LEN     32
+	#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_TXUNDRFLWHI_DEFAULT 0x0
+
+struct tx_underflow_error_frames_high {
+	a_uint32_t  txundrflwhi:32;
+};
+
+union tx_underflow_error_frames_high_u {
+	a_uint32_t val;
+	struct tx_underflow_error_frames_high bf;
+};
+
+/*[register] TX_OCTET_COUNT_GOOD_LOW*/
+#define TX_OCTET_COUNT_GOOD_LOW
+#define TX_OCTET_COUNT_GOOD_LOW_ADDRESS 0x884
+#define TX_OCTET_COUNT_GOOD_LOW_NUM     1
+#define TX_OCTET_COUNT_GOOD_LOW_INC     0x4000
+#define TX_OCTET_COUNT_GOOD_LOW_TYPE    REG_TYPE_RO
+#define TX_OCTET_COUNT_GOOD_LOW_DEFAULT 0x0
+	/*[field] TXOCTGLO*/
+	#define TX_OCTET_COUNT_GOOD_LOW_TXOCTGLO
+	#define TX_OCTET_COUNT_GOOD_LOW_TXOCTGLO_OFFSET  0
+	#define TX_OCTET_COUNT_GOOD_LOW_TXOCTGLO_LEN     32
+	#define TX_OCTET_COUNT_GOOD_LOW_TXOCTGLO_DEFAULT 0x0
+
+struct tx_octet_count_good_low {
+	a_uint32_t  txoctglo:32;
+};
+
+union tx_octet_count_good_low_u {
+	a_uint32_t val;
+	struct tx_octet_count_good_low bf;
+};
+
+/*[register] TX_OCTET_COUNT_GOOD_HIGH*/
+#define TX_OCTET_COUNT_GOOD_HIGH
+#define TX_OCTET_COUNT_GOOD_HIGH_ADDRESS 0x888
+#define TX_OCTET_COUNT_GOOD_HIGH_NUM     1
+#define TX_OCTET_COUNT_GOOD_HIGH_INC     0x4000
+#define TX_OCTET_COUNT_GOOD_HIGH_TYPE    REG_TYPE_RO
+#define TX_OCTET_COUNT_GOOD_HIGH_DEFAULT 0x0
+	/*[field] TXOCTGHI*/
+	#define TX_OCTET_COUNT_GOOD_HIGH_TXOCTGHI
+	#define TX_OCTET_COUNT_GOOD_HIGH_TXOCTGHI_OFFSET  0
+	#define TX_OCTET_COUNT_GOOD_HIGH_TXOCTGHI_LEN     32
+	#define TX_OCTET_COUNT_GOOD_HIGH_TXOCTGHI_DEFAULT 0x0
+
+struct tx_octet_count_good_high {
+	a_uint32_t  txoctghi:32;
+};
+
+union tx_octet_count_good_high_u {
+	a_uint32_t val;
+	struct tx_octet_count_good_high bf;
+};
+
+/*[register] TX_FRAME_COUNT_GOOD_LOW*/
+#define TX_FRAME_COUNT_GOOD_LOW
+#define TX_FRAME_COUNT_GOOD_LOW_ADDRESS 0x88c
+#define TX_FRAME_COUNT_GOOD_LOW_NUM     1
+#define TX_FRAME_COUNT_GOOD_LOW_INC     0x4000
+#define TX_FRAME_COUNT_GOOD_LOW_TYPE    REG_TYPE_RO
+#define TX_FRAME_COUNT_GOOD_LOW_DEFAULT 0x0
+	/*[field] TXFRMGLO*/
+	#define TX_FRAME_COUNT_GOOD_LOW_TXFRMGLO
+	#define TX_FRAME_COUNT_GOOD_LOW_TXFRMGLO_OFFSET  0
+	#define TX_FRAME_COUNT_GOOD_LOW_TXFRMGLO_LEN     32
+	#define TX_FRAME_COUNT_GOOD_LOW_TXFRMGLO_DEFAULT 0x0
+
+struct tx_frame_count_good_low {
+	a_uint32_t  txfrmglo:32;
+};
+
+union tx_frame_count_good_low_u {
+	a_uint32_t val;
+	struct tx_frame_count_good_low bf;
+};
+
+/*[register] TX_FRAME_COUNT_GOOD_HIGH*/
+#define TX_FRAME_COUNT_GOOD_HIGH
+#define TX_FRAME_COUNT_GOOD_HIGH_ADDRESS 0x890
+#define TX_FRAME_COUNT_GOOD_HIGH_NUM     1
+#define TX_FRAME_COUNT_GOOD_HIGH_INC     0x4000
+#define TX_FRAME_COUNT_GOOD_HIGH_TYPE    REG_TYPE_RO
+#define TX_FRAME_COUNT_GOOD_HIGH_DEFAULT 0x0
+	/*[field] TXFRMGHI*/
+	#define TX_FRAME_COUNT_GOOD_HIGH_TXFRMGHI
+	#define TX_FRAME_COUNT_GOOD_HIGH_TXFRMGHI_OFFSET  0
+	#define TX_FRAME_COUNT_GOOD_HIGH_TXFRMGHI_LEN     32
+	#define TX_FRAME_COUNT_GOOD_HIGH_TXFRMGHI_DEFAULT 0x0
+
+struct tx_frame_count_good_high {
+	a_uint32_t  txfrmghi:32;
+};
+
+union tx_frame_count_good_high_u {
+	a_uint32_t val;
+	struct tx_frame_count_good_high bf;
+};
+
+/*[register] TX_PAUSE_FRAMES_LOW*/
+#define TX_PAUSE_FRAMES_LOW
+#define TX_PAUSE_FRAMES_LOW_ADDRESS 0x894
+#define TX_PAUSE_FRAMES_LOW_NUM     1
+#define TX_PAUSE_FRAMES_LOW_INC     0x4000
+#define TX_PAUSE_FRAMES_LOW_TYPE    REG_TYPE_RO
+#define TX_PAUSE_FRAMES_LOW_DEFAULT 0x0
+	/*[field] TXPAUSEGLO*/
+	#define TX_PAUSE_FRAMES_LOW_TXPAUSEGLO
+	#define TX_PAUSE_FRAMES_LOW_TXPAUSEGLO_OFFSET  0
+	#define TX_PAUSE_FRAMES_LOW_TXPAUSEGLO_LEN     32
+	#define TX_PAUSE_FRAMES_LOW_TXPAUSEGLO_DEFAULT 0x0
+
+struct tx_pause_frames_low {
+	a_uint32_t  txpauseglo:32;
+};
+
+union tx_pause_frames_low_u {
+	a_uint32_t val;
+	struct tx_pause_frames_low bf;
+};
+
+/*[register] TX_PAUSE_FRAMES_HIGH*/
+#define TX_PAUSE_FRAMES_HIGH
+#define TX_PAUSE_FRAMES_HIGH_ADDRESS 0x898
+#define TX_PAUSE_FRAMES_HIGH_NUM     1
+#define TX_PAUSE_FRAMES_HIGH_INC     0x4000
+#define TX_PAUSE_FRAMES_HIGH_TYPE    REG_TYPE_RO
+#define TX_PAUSE_FRAMES_HIGH_DEFAULT 0x0
+	/*[field] TXPAUSEGHI*/
+	#define TX_PAUSE_FRAMES_HIGH_TXPAUSEGHI
+	#define TX_PAUSE_FRAMES_HIGH_TXPAUSEGHI_OFFSET  0
+	#define TX_PAUSE_FRAMES_HIGH_TXPAUSEGHI_LEN     32
+	#define TX_PAUSE_FRAMES_HIGH_TXPAUSEGHI_DEFAULT 0x0
+
+struct tx_pause_frames_high {
+	a_uint32_t  txpauseghi:32;
+};
+
+union tx_pause_frames_high_u {
+	a_uint32_t val;
+	struct tx_pause_frames_high bf;
+};
+
+/*[register] TX_VLAN_FRAMES_GOOD_LOW*/
+#define TX_VLAN_FRAMES_GOOD_LOW
+#define TX_VLAN_FRAMES_GOOD_LOW_ADDRESS 0x89c
+#define TX_VLAN_FRAMES_GOOD_LOW_NUM     1
+#define TX_VLAN_FRAMES_GOOD_LOW_INC     0x4000
+#define TX_VLAN_FRAMES_GOOD_LOW_TYPE    REG_TYPE_RO
+#define TX_VLAN_FRAMES_GOOD_LOW_DEFAULT 0x0
+	/*[field] TXVLANGLO*/
+	#define TX_VLAN_FRAMES_GOOD_LOW_TXVLANGLO
+	#define TX_VLAN_FRAMES_GOOD_LOW_TXVLANGLO_OFFSET  0
+	#define TX_VLAN_FRAMES_GOOD_LOW_TXVLANGLO_LEN     32
+	#define TX_VLAN_FRAMES_GOOD_LOW_TXVLANGLO_DEFAULT 0x0
+
+struct tx_vlan_frames_good_low {
+	a_uint32_t  txvlanglo:32;
+};
+
+union tx_vlan_frames_good_low_u {
+	a_uint32_t val;
+	struct tx_vlan_frames_good_low bf;
+};
+
+/*[register] TX_VLAN_FRAMES_GOOD_HIGH*/
+#define TX_VLAN_FRAMES_GOOD_HIGH
+#define TX_VLAN_FRAMES_GOOD_HIGH_ADDRESS 0x8a0
+#define TX_VLAN_FRAMES_GOOD_HIGH_NUM     1
+#define TX_VLAN_FRAMES_GOOD_HIGH_INC     0x4000
+#define TX_VLAN_FRAMES_GOOD_HIGH_TYPE    REG_TYPE_RO
+#define TX_VLAN_FRAMES_GOOD_HIGH_DEFAULT 0x0
+	/*[field] TXVLANGHI*/
+	#define TX_VLAN_FRAMES_GOOD_HIGH_TXVLANGHI
+	#define TX_VLAN_FRAMES_GOOD_HIGH_TXVLANGHI_OFFSET  0
+	#define TX_VLAN_FRAMES_GOOD_HIGH_TXVLANGHI_LEN     32
+	#define TX_VLAN_FRAMES_GOOD_HIGH_TXVLANGHI_DEFAULT 0x0
+
+struct tx_vlan_frames_good_high {
+	a_uint32_t  txvlanghi:32;
+};
+
+union tx_vlan_frames_good_high_u {
+	a_uint32_t val;
+	struct tx_vlan_frames_good_high bf;
+};
+
+/*[register] TX_LPI_USEC_CNTR*/
+#define TX_LPI_USEC_CNTR
+#define TX_LPI_USEC_CNTR_ADDRESS 0x8a4
+#define TX_LPI_USEC_CNTR_NUM     1
+#define TX_LPI_USEC_CNTR_INC     0x4000
+#define TX_LPI_USEC_CNTR_TYPE    REG_TYPE_RO
+#define TX_LPI_USEC_CNTR_DEFAULT 0x0
+	/*[field] TXLPIUSC*/
+	#define TX_LPI_USEC_CNTR_TXLPIUSC
+	#define TX_LPI_USEC_CNTR_TXLPIUSC_OFFSET  0
+	#define TX_LPI_USEC_CNTR_TXLPIUSC_LEN     32
+	#define TX_LPI_USEC_CNTR_TXLPIUSC_DEFAULT 0x0
+
+struct tx_lpi_usec_cntr {
+	a_uint32_t  txlpiusc:32;
+};
+
+union tx_lpi_usec_cntr_u {
+	a_uint32_t val;
+	struct tx_lpi_usec_cntr bf;
+};
+
+/*[register] TX_LPI_TRAN_CNTR*/
+#define TX_LPI_TRAN_CNTR
+#define TX_LPI_TRAN_CNTR_ADDRESS 0x8a8
+#define TX_LPI_TRAN_CNTR_NUM     1
+#define TX_LPI_TRAN_CNTR_INC     0x4000
+#define TX_LPI_TRAN_CNTR_TYPE    REG_TYPE_RO
+#define TX_LPI_TRAN_CNTR_DEFAULT 0x0
+	/*[field] TXLPITRC*/
+	#define TX_LPI_TRAN_CNTR_TXLPITRC
+	#define TX_LPI_TRAN_CNTR_TXLPITRC_OFFSET  0
+	#define TX_LPI_TRAN_CNTR_TXLPITRC_LEN     32
+	#define TX_LPI_TRAN_CNTR_TXLPITRC_DEFAULT 0x0
+
+struct tx_lpi_tran_cntr {
+	a_uint32_t  txlpitrc:32;
+};
+
+union tx_lpi_tran_cntr_u {
+	a_uint32_t val;
+	struct tx_lpi_tran_cntr bf;
+};
+
+/*[register] RX_FRAME_COUNT_GOOD_BAD_LOW*/
+#define RX_FRAME_COUNT_GOOD_BAD_LOW
+#define RX_FRAME_COUNT_GOOD_BAD_LOW_ADDRESS 0x900
+#define RX_FRAME_COUNT_GOOD_BAD_LOW_NUM     1
+#define RX_FRAME_COUNT_GOOD_BAD_LOW_INC     0x4000
+#define RX_FRAME_COUNT_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define RX_FRAME_COUNT_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] RXFRMGBLO*/
+	#define RX_FRAME_COUNT_GOOD_BAD_LOW_RXFRMGBLO
+	#define RX_FRAME_COUNT_GOOD_BAD_LOW_RXFRMGBLO_OFFSET  0
+	#define RX_FRAME_COUNT_GOOD_BAD_LOW_RXFRMGBLO_LEN     32
+	#define RX_FRAME_COUNT_GOOD_BAD_LOW_RXFRMGBLO_DEFAULT 0x0
+
+struct rx_frame_count_good_bad_low {
+	a_uint32_t  rxfrmgblo:32;
+};
+
+union rx_frame_count_good_bad_low_u {
+	a_uint32_t val;
+	struct rx_frame_count_good_bad_low bf;
+};
+
+/*[register] RX_FRAME_COUNT_GOOD_BAD_HIGH*/
+#define RX_FRAME_COUNT_GOOD_BAD_HIGH
+#define RX_FRAME_COUNT_GOOD_BAD_HIGH_ADDRESS 0x904
+#define RX_FRAME_COUNT_GOOD_BAD_HIGH_NUM     1
+#define RX_FRAME_COUNT_GOOD_BAD_HIGH_INC     0x4000
+#define RX_FRAME_COUNT_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define RX_FRAME_COUNT_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] RXFRMGBHI*/
+	#define RX_FRAME_COUNT_GOOD_BAD_HIGH_RXFRMGBHI
+	#define RX_FRAME_COUNT_GOOD_BAD_HIGH_RXFRMGBHI_OFFSET  0
+	#define RX_FRAME_COUNT_GOOD_BAD_HIGH_RXFRMGBHI_LEN     32
+	#define RX_FRAME_COUNT_GOOD_BAD_HIGH_RXFRMGBHI_DEFAULT 0x0
+
+struct rx_frame_count_good_bad_high {
+	a_uint32_t  rxfrmgbhi:32;
+};
+
+union rx_frame_count_good_bad_high_u {
+	a_uint32_t val;
+	struct rx_frame_count_good_bad_high bf;
+};
+
+/*[register] RX_OCTET_COUNT_GOOD_BAD_LOW*/
+#define RX_OCTET_COUNT_GOOD_BAD_LOW
+#define RX_OCTET_COUNT_GOOD_BAD_LOW_ADDRESS 0x908
+#define RX_OCTET_COUNT_GOOD_BAD_LOW_NUM     1
+#define RX_OCTET_COUNT_GOOD_BAD_LOW_INC     0x4000
+#define RX_OCTET_COUNT_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define RX_OCTET_COUNT_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] RXOCTGBLO*/
+	#define RX_OCTET_COUNT_GOOD_BAD_LOW_RXOCTGBLO
+	#define RX_OCTET_COUNT_GOOD_BAD_LOW_RXOCTGBLO_OFFSET  0
+	#define RX_OCTET_COUNT_GOOD_BAD_LOW_RXOCTGBLO_LEN     32
+	#define RX_OCTET_COUNT_GOOD_BAD_LOW_RXOCTGBLO_DEFAULT 0x0
+
+struct rx_octet_count_good_bad_low {
+	a_uint32_t  rxoctgblo:32;
+};
+
+union rx_octet_count_good_bad_low_u {
+	a_uint32_t val;
+	struct rx_octet_count_good_bad_low bf;
+};
+
+/*[register] RX_OCTET_COUNT_GOOD_BAD_HIGH*/
+#define RX_OCTET_COUNT_GOOD_BAD_HIGH
+#define RX_OCTET_COUNT_GOOD_BAD_HIGH_ADDRESS 0x90c
+#define RX_OCTET_COUNT_GOOD_BAD_HIGH_NUM     1
+#define RX_OCTET_COUNT_GOOD_BAD_HIGH_INC     0x4000
+#define RX_OCTET_COUNT_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define RX_OCTET_COUNT_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] RXOCTGBHI*/
+	#define RX_OCTET_COUNT_GOOD_BAD_HIGH_RXOCTGBHI
+	#define RX_OCTET_COUNT_GOOD_BAD_HIGH_RXOCTGBHI_OFFSET  0
+	#define RX_OCTET_COUNT_GOOD_BAD_HIGH_RXOCTGBHI_LEN     32
+	#define RX_OCTET_COUNT_GOOD_BAD_HIGH_RXOCTGBHI_DEFAULT 0x0
+
+struct rx_octet_count_good_bad_high {
+	a_uint32_t  rxoctgbhi:32;
+};
+
+union rx_octet_count_good_bad_high_u {
+	a_uint32_t val;
+	struct rx_octet_count_good_bad_high bf;
+};
+
+/*[register] RX_OCTET_COUNT_GOOD_LOW*/
+#define RX_OCTET_COUNT_GOOD_LOW
+#define RX_OCTET_COUNT_GOOD_LOW_ADDRESS 0x910
+#define RX_OCTET_COUNT_GOOD_LOW_NUM     1
+#define RX_OCTET_COUNT_GOOD_LOW_INC     0x4000
+#define RX_OCTET_COUNT_GOOD_LOW_TYPE    REG_TYPE_RO
+#define RX_OCTET_COUNT_GOOD_LOW_DEFAULT 0x0
+	/*[field] RXOCTGLO*/
+	#define RX_OCTET_COUNT_GOOD_LOW_RXOCTGLO
+	#define RX_OCTET_COUNT_GOOD_LOW_RXOCTGLO_OFFSET  0
+	#define RX_OCTET_COUNT_GOOD_LOW_RXOCTGLO_LEN     32
+	#define RX_OCTET_COUNT_GOOD_LOW_RXOCTGLO_DEFAULT 0x0
+
+struct rx_octet_count_good_low {
+	a_uint32_t  rxoctglo:32;
+};
+
+union rx_octet_count_good_low_u {
+	a_uint32_t val;
+	struct rx_octet_count_good_low bf;
+};
+
+/*[register] RX_OCTET_COUNT_GOOD_HIGH*/
+#define RX_OCTET_COUNT_GOOD_HIGH
+#define RX_OCTET_COUNT_GOOD_HIGH_ADDRESS 0x914
+#define RX_OCTET_COUNT_GOOD_HIGH_NUM     1
+#define RX_OCTET_COUNT_GOOD_HIGH_INC     0x4000
+#define RX_OCTET_COUNT_GOOD_HIGH_TYPE    REG_TYPE_RO
+#define RX_OCTET_COUNT_GOOD_HIGH_DEFAULT 0x0
+	/*[field] RXOCTGHI*/
+	#define RX_OCTET_COUNT_GOOD_HIGH_RXOCTGHI
+	#define RX_OCTET_COUNT_GOOD_HIGH_RXOCTGHI_OFFSET  0
+	#define RX_OCTET_COUNT_GOOD_HIGH_RXOCTGHI_LEN     32
+	#define RX_OCTET_COUNT_GOOD_HIGH_RXOCTGHI_DEFAULT 0x0
+
+struct rx_octet_count_good_high {
+	a_uint32_t  rxoctghi:32;
+};
+
+union rx_octet_count_good_high_u {
+	a_uint32_t val;
+	struct rx_octet_count_good_high bf;
+};
+
+/*[register] RX_BROADCAST_FRAMES_GOOD_LOW*/
+#define RX_BROADCAST_FRAMES_GOOD_LOW
+#define RX_BROADCAST_FRAMES_GOOD_LOW_ADDRESS 0x918
+#define RX_BROADCAST_FRAMES_GOOD_LOW_NUM     1
+#define RX_BROADCAST_FRAMES_GOOD_LOW_INC     0x4000
+#define RX_BROADCAST_FRAMES_GOOD_LOW_TYPE    REG_TYPE_RO
+#define RX_BROADCAST_FRAMES_GOOD_LOW_DEFAULT 0x0
+	/*[field] RXBCASTGLO*/
+	#define RX_BROADCAST_FRAMES_GOOD_LOW_RXBCASTGLO
+	#define RX_BROADCAST_FRAMES_GOOD_LOW_RXBCASTGLO_OFFSET  0
+	#define RX_BROADCAST_FRAMES_GOOD_LOW_RXBCASTGLO_LEN     32
+	#define RX_BROADCAST_FRAMES_GOOD_LOW_RXBCASTGLO_DEFAULT 0x0
+
+struct rx_broadcast_frames_good_low {
+	a_uint32_t  rxbcastglo:32;
+};
+
+union rx_broadcast_frames_good_low_u {
+	a_uint32_t val;
+	struct rx_broadcast_frames_good_low bf;
+};
+
+/*[register] RX_BROADCAST_FRAMES_GOOD_HIGH*/
+#define RX_BROADCAST_FRAMES_GOOD_HIGH
+#define RX_BROADCAST_FRAMES_GOOD_HIGH_ADDRESS 0x91c
+#define RX_BROADCAST_FRAMES_GOOD_HIGH_NUM     1
+#define RX_BROADCAST_FRAMES_GOOD_HIGH_INC     0x4000
+#define RX_BROADCAST_FRAMES_GOOD_HIGH_TYPE    REG_TYPE_RO
+#define RX_BROADCAST_FRAMES_GOOD_HIGH_DEFAULT 0x0
+	/*[field] RXBCASTGHI*/
+	#define RX_BROADCAST_FRAMES_GOOD_HIGH_RXBCASTGHI
+	#define RX_BROADCAST_FRAMES_GOOD_HIGH_RXBCASTGHI_OFFSET  0
+	#define RX_BROADCAST_FRAMES_GOOD_HIGH_RXBCASTGHI_LEN     32
+	#define RX_BROADCAST_FRAMES_GOOD_HIGH_RXBCASTGHI_DEFAULT 0x0
+
+struct rx_broadcast_frames_good_high {
+	a_uint32_t  rxbcastghi:32;
+};
+
+union rx_broadcast_frames_good_high_u {
+	a_uint32_t val;
+	struct rx_broadcast_frames_good_high bf;
+};
+
+/*[register] RX_MULTICAST_FRAMES_GOOD_LOW*/
+#define RX_MULTICAST_FRAMES_GOOD_LOW
+#define RX_MULTICAST_FRAMES_GOOD_LOW_ADDRESS 0x920
+#define RX_MULTICAST_FRAMES_GOOD_LOW_NUM     1
+#define RX_MULTICAST_FRAMES_GOOD_LOW_INC     0x4000
+#define RX_MULTICAST_FRAMES_GOOD_LOW_TYPE    REG_TYPE_RO
+#define RX_MULTICAST_FRAMES_GOOD_LOW_DEFAULT 0x0
+	/*[field] RXMCASTGLO*/
+	#define RX_MULTICAST_FRAMES_GOOD_LOW_RXMCASTGLO
+	#define RX_MULTICAST_FRAMES_GOOD_LOW_RXMCASTGLO_OFFSET  0
+	#define RX_MULTICAST_FRAMES_GOOD_LOW_RXMCASTGLO_LEN     32
+	#define RX_MULTICAST_FRAMES_GOOD_LOW_RXMCASTGLO_DEFAULT 0x0
+
+struct rx_multicast_frames_good_low {
+	a_uint32_t  rxmcastglo:32;
+};
+
+union rx_multicast_frames_good_low_u {
+	a_uint32_t val;
+	struct rx_multicast_frames_good_low bf;
+};
+
+/*[register] RX_MULTICAST_FRAMES_GOOD_HIGH*/
+#define RX_MULTICAST_FRAMES_GOOD_HIGH
+#define RX_MULTICAST_FRAMES_GOOD_HIGH_ADDRESS 0x924
+#define RX_MULTICAST_FRAMES_GOOD_HIGH_NUM     1
+#define RX_MULTICAST_FRAMES_GOOD_HIGH_INC     0x4000
+#define RX_MULTICAST_FRAMES_GOOD_HIGH_TYPE    REG_TYPE_RO
+#define RX_MULTICAST_FRAMES_GOOD_HIGH_DEFAULT 0x0
+	/*[field] RXMCASTGHI*/
+	#define RX_MULTICAST_FRAMES_GOOD_HIGH_RXMCASTGHI
+	#define RX_MULTICAST_FRAMES_GOOD_HIGH_RXMCASTGHI_OFFSET  0
+	#define RX_MULTICAST_FRAMES_GOOD_HIGH_RXMCASTGHI_LEN     32
+	#define RX_MULTICAST_FRAMES_GOOD_HIGH_RXMCASTGHI_DEFAULT 0x0
+
+struct rx_multicast_frames_good_high {
+	a_uint32_t  rxmcastghi:32;
+};
+
+union rx_multicast_frames_good_high_u {
+	a_uint32_t val;
+	struct rx_multicast_frames_good_high bf;
+};
+
+/*[register] RX_CRC_ERROR_FRAMES_LOW*/
+#define RX_CRC_ERROR_FRAMES_LOW
+#define RX_CRC_ERROR_FRAMES_LOW_ADDRESS 0x928
+#define RX_CRC_ERROR_FRAMES_LOW_NUM     1
+#define RX_CRC_ERROR_FRAMES_LOW_INC     0x4000
+#define RX_CRC_ERROR_FRAMES_LOW_TYPE    REG_TYPE_RO
+#define RX_CRC_ERROR_FRAMES_LOW_DEFAULT 0x0
+	/*[field] RXCRCERLO*/
+	#define RX_CRC_ERROR_FRAMES_LOW_RXCRCERLO
+	#define RX_CRC_ERROR_FRAMES_LOW_RXCRCERLO_OFFSET  0
+	#define RX_CRC_ERROR_FRAMES_LOW_RXCRCERLO_LEN     32
+	#define RX_CRC_ERROR_FRAMES_LOW_RXCRCERLO_DEFAULT 0x0
+
+struct rx_crc_error_frames_low {
+	a_uint32_t  rxcrcerlo:32;
+};
+
+union rx_crc_error_frames_low_u {
+	a_uint32_t val;
+	struct rx_crc_error_frames_low bf;
+};
+
+/*[register] RX_CRC_ERROR_FRAMES_HIGH*/
+#define RX_CRC_ERROR_FRAMES_HIGH
+#define RX_CRC_ERROR_FRAMES_HIGH_ADDRESS 0x92c
+#define RX_CRC_ERROR_FRAMES_HIGH_NUM     1
+#define RX_CRC_ERROR_FRAMES_HIGH_INC     0x4000
+#define RX_CRC_ERROR_FRAMES_HIGH_TYPE    REG_TYPE_RO
+#define RX_CRC_ERROR_FRAMES_HIGH_DEFAULT 0x0
+	/*[field] RXCRCERHI*/
+	#define RX_CRC_ERROR_FRAMES_HIGH_RXCRCERHI
+	#define RX_CRC_ERROR_FRAMES_HIGH_RXCRCERHI_OFFSET  0
+	#define RX_CRC_ERROR_FRAMES_HIGH_RXCRCERHI_LEN     32
+	#define RX_CRC_ERROR_FRAMES_HIGH_RXCRCERHI_DEFAULT 0x0
+
+struct rx_crc_error_frames_high {
+	a_uint32_t  rxcrcerhi:32;
+};
+
+union rx_crc_error_frames_high_u {
+	a_uint32_t val;
+	struct rx_crc_error_frames_high bf;
+};
+
+/*[register] RX_RUNT_ERROR_FRAMES*/
+#define RX_RUNT_ERROR_FRAMES
+#define RX_RUNT_ERROR_FRAMES_ADDRESS 0x930
+#define RX_RUNT_ERROR_FRAMES_NUM     1
+#define RX_RUNT_ERROR_FRAMES_INC     0x4000
+#define RX_RUNT_ERROR_FRAMES_TYPE    REG_TYPE_RO
+#define RX_RUNT_ERROR_FRAMES_DEFAULT 0x0
+	/*[field] RXRUNTER*/
+	#define RX_RUNT_ERROR_FRAMES_RXRUNTER
+	#define RX_RUNT_ERROR_FRAMES_RXRUNTER_OFFSET  0
+	#define RX_RUNT_ERROR_FRAMES_RXRUNTER_LEN     32
+	#define RX_RUNT_ERROR_FRAMES_RXRUNTER_DEFAULT 0x0
+
+struct rx_runt_error_frames {
+	a_uint32_t  rxrunter:32;
+};
+
+union rx_runt_error_frames_u {
+	a_uint32_t val;
+	struct rx_runt_error_frames bf;
+};
+
+/*[register] RX_JABBER_ERROR_FRAMES*/
+#define RX_JABBER_ERROR_FRAMES
+#define RX_JABBER_ERROR_FRAMES_ADDRESS 0x934
+#define RX_JABBER_ERROR_FRAMES_NUM     1
+#define RX_JABBER_ERROR_FRAMES_INC     0x4000
+#define RX_JABBER_ERROR_FRAMES_TYPE    REG_TYPE_RO
+#define RX_JABBER_ERROR_FRAMES_DEFAULT 0x0
+	/*[field] RXJABERER*/
+	#define RX_JABBER_ERROR_FRAMES_RXJABERER
+	#define RX_JABBER_ERROR_FRAMES_RXJABERER_OFFSET  0
+	#define RX_JABBER_ERROR_FRAMES_RXJABERER_LEN     32
+	#define RX_JABBER_ERROR_FRAMES_RXJABERER_DEFAULT 0x0
+
+struct rx_jabber_error_frames {
+	a_uint32_t  rxjaberer:32;
+};
+
+union rx_jabber_error_frames_u {
+	a_uint32_t val;
+	struct rx_jabber_error_frames bf;
+};
+
+/*[register] RX_UNDERSIZE_FRAMES_GOOD*/
+#define RX_UNDERSIZE_FRAMES_GOOD
+#define RX_UNDERSIZE_FRAMES_GOOD_ADDRESS 0x938
+#define RX_UNDERSIZE_FRAMES_GOOD_NUM     1
+#define RX_UNDERSIZE_FRAMES_GOOD_INC     0x4000
+#define RX_UNDERSIZE_FRAMES_GOOD_TYPE    REG_TYPE_RO
+#define RX_UNDERSIZE_FRAMES_GOOD_DEFAULT 0x0
+	/*[field] RXUSIZEG*/
+	#define RX_UNDERSIZE_FRAMES_GOOD_RXUSIZEG
+	#define RX_UNDERSIZE_FRAMES_GOOD_RXUSIZEG_OFFSET  0
+	#define RX_UNDERSIZE_FRAMES_GOOD_RXUSIZEG_LEN     32
+	#define RX_UNDERSIZE_FRAMES_GOOD_RXUSIZEG_DEFAULT 0x0
+
+struct rx_undersize_frames_good {
+	a_uint32_t  rxusizeg:32;
+};
+
+union rx_undersize_frames_good_u {
+	a_uint32_t val;
+	struct rx_undersize_frames_good bf;
+};
+
+/*[register] RX_OVERSIZE_FRAMES_GOOD*/
+#define RX_OVERSIZE_FRAMES_GOOD
+#define RX_OVERSIZE_FRAMES_GOOD_ADDRESS 0x93c
+#define RX_OVERSIZE_FRAMES_GOOD_NUM     1
+#define RX_OVERSIZE_FRAMES_GOOD_INC     0x4000
+#define RX_OVERSIZE_FRAMES_GOOD_TYPE    REG_TYPE_RO
+#define RX_OVERSIZE_FRAMES_GOOD_DEFAULT 0x0
+	/*[field] RXOSIZEG*/
+	#define RX_OVERSIZE_FRAMES_GOOD_RXOSIZEG
+	#define RX_OVERSIZE_FRAMES_GOOD_RXOSIZEG_OFFSET  0
+	#define RX_OVERSIZE_FRAMES_GOOD_RXOSIZEG_LEN     32
+	#define RX_OVERSIZE_FRAMES_GOOD_RXOSIZEG_DEFAULT 0x0
+
+struct rx_oversize_frames_good {
+	a_uint32_t  rxosizeg:32;
+};
+
+union rx_oversize_frames_good_u {
+	a_uint32_t val;
+	struct rx_oversize_frames_good bf;
+};
+
+/*[register] RX_64OCTETS_FRAMES_GOOD_BAD_LOW*/
+#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW
+#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x940
+#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_NUM     1
+#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] RX64OCTGBLO*/
+	#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_RX64OCTGBLO
+	#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_RX64OCTGBLO_OFFSET  0
+	#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_RX64OCTGBLO_LEN     32
+	#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_RX64OCTGBLO_DEFAULT 0x0
+
+struct rx_64octets_frames_good_bad_low {
+	a_uint32_t  rx64octgblo:32;
+};
+
+union rx_64octets_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct rx_64octets_frames_good_bad_low bf;
+};
+
+/*[register] RX_64OCTETS_FRAMES_GOOD_BAD_HIGH*/
+#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH
+#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x944
+#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_NUM     1
+#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] RX64OCTGBHI*/
+	#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_RX64OCTGBHI
+	#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_RX64OCTGBHI_OFFSET  0
+	#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_RX64OCTGBHI_LEN     32
+	#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_RX64OCTGBHI_DEFAULT 0x0
+
+struct rx_64octets_frames_good_bad_high {
+	a_uint32_t  rx64octgbhi:32;
+};
+
+union rx_64octets_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct rx_64octets_frames_good_bad_high bf;
+};
+
+/*[register] RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW*/
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x948
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_NUM     1
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] RX65_127OCTGBLO*/
+	#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_RX65_127OCTGBLO
+	#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_RX65_127OCTGBLO_OFFSET  0
+	#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_RX65_127OCTGBLO_LEN     32
+	#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_RX65_127OCTGBLO_DEFAULT 0x0
+
+struct rx_65to127octets_frames_good_bad_low {
+	a_uint32_t  rx65_127octgblo:32;
+};
+
+union rx_65to127octets_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct rx_65to127octets_frames_good_bad_low bf;
+};
+
+/*[register] RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH*/
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x94c
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_NUM     1
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] RX65_127OCTGBHI*/
+	#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_RX65_127OCTGBHI
+	#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_RX65_127OCTGBHI_OFFSET  0
+	#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_RX65_127OCTGBHI_LEN     32
+	#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_RX65_127OCTGBHI_DEFAULT 0x0
+
+struct rx_65to127octets_frames_good_bad_high {
+	a_uint32_t  rx65_127octgbhi:32;
+};
+
+union rx_65to127octets_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct rx_65to127octets_frames_good_bad_high bf;
+};
+
+/*[register] RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW*/
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x950
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_NUM     1
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] RX128_255OCTGBLO*/
+	#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_RX128_255OCTGBLO
+	#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_RX128_255OCTGBLO_OFFSET  0
+	#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_RX128_255OCTGBLO_LEN     32
+	#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_RX128_255OCTGBLO_DEFAULT 0x0
+
+struct rx_128to255octets_frames_good_bad_low {
+	a_uint32_t  rx128_255octgblo:32;
+};
+
+union rx_128to255octets_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct rx_128to255octets_frames_good_bad_low bf;
+};
+
+/*[register] RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH*/
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x954
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_NUM     1
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] RX128_255OCTGBHI*/
+	#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_RX128_255OCTGBHI
+	#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_RX128_255OCTGBHI_OFFSET  0
+	#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_RX128_255OCTGBHI_LEN     32
+	#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_RX128_255OCTGBHI_DEFAULT 0x0
+
+struct rx_128to255octets_frames_good_bad_high {
+	a_uint32_t  rx128_255octgbhi:32;
+};
+
+union rx_128to255octets_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct rx_128to255octets_frames_good_bad_high bf;
+};
+
+/*[register] RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW*/
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x958
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_NUM     1
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] RX256_511OCTGBLO*/
+	#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_RX256_511OCTGBLO
+	#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_RX256_511OCTGBLO_OFFSET  0
+	#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_RX256_511OCTGBLO_LEN     32
+	#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_RX256_511OCTGBLO_DEFAULT 0x0
+
+struct rx_256to511octets_frames_good_bad_low {
+	a_uint32_t  rx256_511octgblo:32;
+};
+
+union rx_256to511octets_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct rx_256to511octets_frames_good_bad_low bf;
+};
+
+/*[register] RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH*/
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x95c
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_NUM     1
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] RX256_511OCTGBHI*/
+	#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_RX256_511OCTGBHI
+	#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_RX256_511OCTGBHI_OFFSET  0
+	#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_RX256_511OCTGBHI_LEN     32
+	#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_RX256_511OCTGBHI_DEFAULT 0x0
+
+struct rx_256to511octets_frames_good_bad_high {
+	a_uint32_t  rx256_511octgbhi:32;
+};
+
+union rx_256to511octets_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct rx_256to511octets_frames_good_bad_high bf;
+};
+
+/*[register] RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW*/
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x960
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_NUM     1
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] RX512_1023OCTGBLO*/
+	#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_RX512_1023OCTGBLO
+	#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_RX512_1023OCTGBLO_OFFSET  0
+	#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_RX512_1023OCTGBLO_LEN     32
+	#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_RX512_1023OCTGBLO_DEFAULT 0x0
+
+struct rx_512to1023octets_frames_good_bad_low {
+	a_uint32_t  rx512_1023octgblo:32;
+};
+
+union rx_512to1023octets_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct rx_512to1023octets_frames_good_bad_low bf;
+};
+
+/*[register] RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH*/
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x964
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_NUM     1
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] RX512_1023OCTGBHI*/
+	#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_RX512_1023OCTGBHI
+	#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_RX512_1023OCTGBHI_OFFSET  0
+	#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_RX512_1023OCTGBHI_LEN     32
+	#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_RX512_1023OCTGBHI_DEFAULT 0x0
+
+struct rx_512to1023octets_frames_good_bad_high {
+	a_uint32_t  rx512_1023octgbhi:32;
+};
+
+union rx_512to1023octets_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct rx_512to1023octets_frames_good_bad_high bf;
+};
+
+/*[register] RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW*/
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x968
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_NUM     1
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] RX1024_MAXGBOCTLO*/
+	#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_RX1024_MAXGBOCTLO
+	#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_RX1024_MAXGBOCTLO_OFFSET  0
+	#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_RX1024_MAXGBOCTLO_LEN     32
+	#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_RX1024_MAXGBOCTLO_DEFAULT 0x0
+
+struct rx_1024tomaxoctets_frames_good_bad_low {
+	a_uint32_t  rx1024_maxgboctlo:32;
+};
+
+union rx_1024tomaxoctets_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct rx_1024tomaxoctets_frames_good_bad_low bf;
+};
+
+/*[register] RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH*/
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x96c
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_NUM     1
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] RX1024_MAXGBOCTHI*/
+	#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_RX1024_MAXGBOCTHI
+	#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_RX1024_MAXGBOCTHI_OFFSET  0
+	#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_RX1024_MAXGBOCTHI_LEN     32
+	#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_RX1024_MAXGBOCTHI_DEFAULT 0x0
+
+struct rx_1024tomaxoctets_frames_good_bad_high {
+	a_uint32_t  rx1024_maxgbocthi:32;
+};
+
+union rx_1024tomaxoctets_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct rx_1024tomaxoctets_frames_good_bad_high bf;
+};
+
+/*[register] RX_UNICAST_FRAMES_GOOD_LOW*/
+#define RX_UNICAST_FRAMES_GOOD_LOW
+#define RX_UNICAST_FRAMES_GOOD_LOW_ADDRESS 0x970
+#define RX_UNICAST_FRAMES_GOOD_LOW_NUM     1
+#define RX_UNICAST_FRAMES_GOOD_LOW_INC     0x4000
+#define RX_UNICAST_FRAMES_GOOD_LOW_TYPE    REG_TYPE_RO
+#define RX_UNICAST_FRAMES_GOOD_LOW_DEFAULT 0x0
+	/*[field] RXUCASTGLO*/
+	#define RX_UNICAST_FRAMES_GOOD_LOW_RXUCASTGLO
+	#define RX_UNICAST_FRAMES_GOOD_LOW_RXUCASTGLO_OFFSET  0
+	#define RX_UNICAST_FRAMES_GOOD_LOW_RXUCASTGLO_LEN     32
+	#define RX_UNICAST_FRAMES_GOOD_LOW_RXUCASTGLO_DEFAULT 0x0
+
+struct rx_unicast_frames_good_low {
+	a_uint32_t  rxucastglo:32;
+};
+
+union rx_unicast_frames_good_low_u {
+	a_uint32_t val;
+	struct rx_unicast_frames_good_low bf;
+};
+
+/*[register] RX_UNICAST_FRAMES_GOOD_HIGH*/
+#define RX_UNICAST_FRAMES_GOOD_HIGH
+#define RX_UNICAST_FRAMES_GOOD_HIGH_ADDRESS 0x974
+#define RX_UNICAST_FRAMES_GOOD_HIGH_NUM     1
+#define RX_UNICAST_FRAMES_GOOD_HIGH_INC     0x4000
+#define RX_UNICAST_FRAMES_GOOD_HIGH_TYPE    REG_TYPE_RO
+#define RX_UNICAST_FRAMES_GOOD_HIGH_DEFAULT 0x0
+	/*[field] RXUCASTGHI*/
+	#define RX_UNICAST_FRAMES_GOOD_HIGH_RXUCASTGHI
+	#define RX_UNICAST_FRAMES_GOOD_HIGH_RXUCASTGHI_OFFSET  0
+	#define RX_UNICAST_FRAMES_GOOD_HIGH_RXUCASTGHI_LEN     32
+	#define RX_UNICAST_FRAMES_GOOD_HIGH_RXUCASTGHI_DEFAULT 0x0
+
+struct rx_unicast_frames_good_high {
+	a_uint32_t  rxucastghi:32;
+};
+
+union rx_unicast_frames_good_high_u {
+	a_uint32_t val;
+	struct rx_unicast_frames_good_high bf;
+};
+
+/*[register] RX_LENGTH_ERROR_FRAMES_LOW*/
+#define RX_LENGTH_ERROR_FRAMES_LOW
+#define RX_LENGTH_ERROR_FRAMES_LOW_ADDRESS 0x978
+#define RX_LENGTH_ERROR_FRAMES_LOW_NUM     1
+#define RX_LENGTH_ERROR_FRAMES_LOW_INC     0x4000
+#define RX_LENGTH_ERROR_FRAMES_LOW_TYPE    REG_TYPE_RO
+#define RX_LENGTH_ERROR_FRAMES_LOW_DEFAULT 0x0
+	/*[field] RXLENERRLO*/
+	#define RX_LENGTH_ERROR_FRAMES_LOW_RXLENERRLO
+	#define RX_LENGTH_ERROR_FRAMES_LOW_RXLENERRLO_OFFSET  0
+	#define RX_LENGTH_ERROR_FRAMES_LOW_RXLENERRLO_LEN     32
+	#define RX_LENGTH_ERROR_FRAMES_LOW_RXLENERRLO_DEFAULT 0x0
+
+struct rx_length_error_frames_low {
+	a_uint32_t  rxlenerrlo:32;
+};
+
+union rx_length_error_frames_low_u {
+	a_uint32_t val;
+	struct rx_length_error_frames_low bf;
+};
+
+/*[register] RX_LENGTH_ERROR_FRAMES_HIGH*/
+#define RX_LENGTH_ERROR_FRAMES_HIGH
+#define RX_LENGTH_ERROR_FRAMES_HIGH_ADDRESS 0x97c
+#define RX_LENGTH_ERROR_FRAMES_HIGH_NUM     1
+#define RX_LENGTH_ERROR_FRAMES_HIGH_INC     0x4000
+#define RX_LENGTH_ERROR_FRAMES_HIGH_TYPE    REG_TYPE_RO
+#define RX_LENGTH_ERROR_FRAMES_HIGH_DEFAULT 0x0
+	/*[field] RXLENERRHI*/
+	#define RX_LENGTH_ERROR_FRAMES_HIGH_RXLENERRHI
+	#define RX_LENGTH_ERROR_FRAMES_HIGH_RXLENERRHI_OFFSET  0
+	#define RX_LENGTH_ERROR_FRAMES_HIGH_RXLENERRHI_LEN     32
+	#define RX_LENGTH_ERROR_FRAMES_HIGH_RXLENERRHI_DEFAULT 0x0
+
+struct rx_length_error_frames_high {
+	a_uint32_t  rxlenerrhi:32;
+};
+
+union rx_length_error_frames_high_u {
+	a_uint32_t val;
+	struct rx_length_error_frames_high bf;
+};
+
+/*[register] RX_OUTOFRANGE_FRAMES_LOW*/
+#define RX_OUTOFRANGE_FRAMES_LOW
+#define RX_OUTOFRANGE_FRAMES_LOW_ADDRESS 0x980
+#define RX_OUTOFRANGE_FRAMES_LOW_NUM     1
+#define RX_OUTOFRANGE_FRAMES_LOW_INC     0x4000
+#define RX_OUTOFRANGE_FRAMES_LOW_TYPE    REG_TYPE_RO
+#define RX_OUTOFRANGE_FRAMES_LOW_DEFAULT 0x0
+	/*[field] RXORANGELO*/
+	#define RX_OUTOFRANGE_FRAMES_LOW_RXORANGELO
+	#define RX_OUTOFRANGE_FRAMES_LOW_RXORANGELO_OFFSET  0
+	#define RX_OUTOFRANGE_FRAMES_LOW_RXORANGELO_LEN     32
+	#define RX_OUTOFRANGE_FRAMES_LOW_RXORANGELO_DEFAULT 0x0
+
+struct rx_outofrange_frames_low {
+	a_uint32_t  rxorangelo:32;
+};
+
+union rx_outofrange_frames_low_u {
+	a_uint32_t val;
+	struct rx_outofrange_frames_low bf;
+};
+
+/*[register] RX_OUTOFRANGE_FRAMES_HIGH*/
+#define RX_OUTOFRANGE_FRAMES_HIGH
+#define RX_OUTOFRANGE_FRAMES_HIGH_ADDRESS 0x984
+#define RX_OUTOFRANGE_FRAMES_HIGH_NUM     1
+#define RX_OUTOFRANGE_FRAMES_HIGH_INC     0x4000
+#define RX_OUTOFRANGE_FRAMES_HIGH_TYPE    REG_TYPE_RO
+#define RX_OUTOFRANGE_FRAMES_HIGH_DEFAULT 0x0
+	/*[field] RXORANGEHI*/
+	#define RX_OUTOFRANGE_FRAMES_HIGH_RXORANGEHI
+	#define RX_OUTOFRANGE_FRAMES_HIGH_RXORANGEHI_OFFSET  0
+	#define RX_OUTOFRANGE_FRAMES_HIGH_RXORANGEHI_LEN     32
+	#define RX_OUTOFRANGE_FRAMES_HIGH_RXORANGEHI_DEFAULT 0x0
+
+struct rx_outofrange_frames_high {
+	a_uint32_t  rxorangehi:32;
+};
+
+union rx_outofrange_frames_high_u {
+	a_uint32_t val;
+	struct rx_outofrange_frames_high bf;
+};
+
+/*[register] RX_PAUSE_FRAMES_LOW*/
+#define RX_PAUSE_FRAMES_LOW
+#define RX_PAUSE_FRAMES_LOW_ADDRESS 0x988
+#define RX_PAUSE_FRAMES_LOW_NUM     1
+#define RX_PAUSE_FRAMES_LOW_INC     0x4000
+#define RX_PAUSE_FRAMES_LOW_TYPE    REG_TYPE_RO
+#define RX_PAUSE_FRAMES_LOW_DEFAULT 0x0
+	/*[field] RXPAUSELO*/
+	#define RX_PAUSE_FRAMES_LOW_RXPAUSELO
+	#define RX_PAUSE_FRAMES_LOW_RXPAUSELO_OFFSET  0
+	#define RX_PAUSE_FRAMES_LOW_RXPAUSELO_LEN     32
+	#define RX_PAUSE_FRAMES_LOW_RXPAUSELO_DEFAULT 0x0
+
+struct rx_pause_frames_low {
+	a_uint32_t  rxpauselo:32;
+};
+
+union rx_pause_frames_low_u {
+	a_uint32_t val;
+	struct rx_pause_frames_low bf;
+};
+
+/*[register] RX_PAUSE_FRAMES_HIGH*/
+#define RX_PAUSE_FRAMES_HIGH
+#define RX_PAUSE_FRAMES_HIGH_ADDRESS 0x98c
+#define RX_PAUSE_FRAMES_HIGH_NUM     1
+#define RX_PAUSE_FRAMES_HIGH_INC     0x4000
+#define RX_PAUSE_FRAMES_HIGH_TYPE    REG_TYPE_RO
+#define RX_PAUSE_FRAMES_HIGH_DEFAULT 0x0
+	/*[field] RXPAUSEHI*/
+	#define RX_PAUSE_FRAMES_HIGH_RXPAUSEHI
+	#define RX_PAUSE_FRAMES_HIGH_RXPAUSEHI_OFFSET  0
+	#define RX_PAUSE_FRAMES_HIGH_RXPAUSEHI_LEN     32
+	#define RX_PAUSE_FRAMES_HIGH_RXPAUSEHI_DEFAULT 0x0
+
+struct rx_pause_frames_high {
+	a_uint32_t  rxpausehi:32;
+};
+
+union rx_pause_frames_high_u {
+	a_uint32_t val;
+	struct rx_pause_frames_high bf;
+};
+
+/*[register] RX_FIFOOVERFLOW_FRAMES_LOW*/
+#define RX_FIFOOVERFLOW_FRAMES_LOW
+#define RX_FIFOOVERFLOW_FRAMES_LOW_ADDRESS 0x990
+#define RX_FIFOOVERFLOW_FRAMES_LOW_NUM     1
+#define RX_FIFOOVERFLOW_FRAMES_LOW_INC     0x4000
+#define RX_FIFOOVERFLOW_FRAMES_LOW_TYPE    REG_TYPE_RO
+#define RX_FIFOOVERFLOW_FRAMES_LOW_DEFAULT 0x0
+	/*[field] RXFOVFLO*/
+	#define RX_FIFOOVERFLOW_FRAMES_LOW_RXFOVFLO
+	#define RX_FIFOOVERFLOW_FRAMES_LOW_RXFOVFLO_OFFSET  0
+	#define RX_FIFOOVERFLOW_FRAMES_LOW_RXFOVFLO_LEN     32
+	#define RX_FIFOOVERFLOW_FRAMES_LOW_RXFOVFLO_DEFAULT 0x0
+
+struct rx_fifooverflow_frames_low {
+	a_uint32_t  rxfovflo:32;
+};
+
+union rx_fifooverflow_frames_low_u {
+	a_uint32_t val;
+	struct rx_fifooverflow_frames_low bf;
+};
+
+/*[register] RX_FIFOOVERFLOW_FRAMES_HIGH*/
+#define RX_FIFOOVERFLOW_FRAMES_HIGH
+#define RX_FIFOOVERFLOW_FRAMES_HIGH_ADDRESS 0x994
+#define RX_FIFOOVERFLOW_FRAMES_HIGH_NUM     1
+#define RX_FIFOOVERFLOW_FRAMES_HIGH_INC     0x4000
+#define RX_FIFOOVERFLOW_FRAMES_HIGH_TYPE    REG_TYPE_RO
+#define RX_FIFOOVERFLOW_FRAMES_HIGH_DEFAULT 0x0
+	/*[field] RXFOVFHI*/
+	#define RX_FIFOOVERFLOW_FRAMES_HIGH_RXFOVFHI
+	#define RX_FIFOOVERFLOW_FRAMES_HIGH_RXFOVFHI_OFFSET  0
+	#define RX_FIFOOVERFLOW_FRAMES_HIGH_RXFOVFHI_LEN     32
+	#define RX_FIFOOVERFLOW_FRAMES_HIGH_RXFOVFHI_DEFAULT 0x0
+
+struct rx_fifooverflow_frames_high {
+	a_uint32_t  rxfovfhi:32;
+};
+
+union rx_fifooverflow_frames_high_u {
+	a_uint32_t val;
+	struct rx_fifooverflow_frames_high bf;
+};
+
+/*[register] RX_VLAN_FRAMES_GOOD_BAD_LOW*/
+#define RX_VLAN_FRAMES_GOOD_BAD_LOW
+#define RX_VLAN_FRAMES_GOOD_BAD_LOW_ADDRESS 0x998
+#define RX_VLAN_FRAMES_GOOD_BAD_LOW_NUM     1
+#define RX_VLAN_FRAMES_GOOD_BAD_LOW_INC     0x4000
+#define RX_VLAN_FRAMES_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define RX_VLAN_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] RXVLANGBLO*/
+	#define RX_VLAN_FRAMES_GOOD_BAD_LOW_RXVLANGBLO
+	#define RX_VLAN_FRAMES_GOOD_BAD_LOW_RXVLANGBLO_OFFSET  0
+	#define RX_VLAN_FRAMES_GOOD_BAD_LOW_RXVLANGBLO_LEN     32
+	#define RX_VLAN_FRAMES_GOOD_BAD_LOW_RXVLANGBLO_DEFAULT 0x0
+
+struct rx_vlan_frames_good_bad_low {
+	a_uint32_t  rxvlangblo:32;
+};
+
+union rx_vlan_frames_good_bad_low_u {
+	a_uint32_t val;
+	struct rx_vlan_frames_good_bad_low bf;
+};
+
+/*[register] RX_VLAN_FRAMES_GOOD_BAD_HIGH*/
+#define RX_VLAN_FRAMES_GOOD_BAD_HIGH
+#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x99c
+#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_NUM     1
+#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_INC     0x4000
+#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] RXVLANGBHI*/
+	#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_RXVLANGBHI
+	#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_RXVLANGBHI_OFFSET  0
+	#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_RXVLANGBHI_LEN     32
+	#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_RXVLANGBHI_DEFAULT 0x0
+
+struct rx_vlan_frames_good_bad_high {
+	a_uint32_t  rxvlangbhi:32;
+};
+
+union rx_vlan_frames_good_bad_high_u {
+	a_uint32_t val;
+	struct rx_vlan_frames_good_bad_high bf;
+};
+
+/*[register] RX_WATCHDOG_ERROR_FRAMES*/
+#define RX_WATCHDOG_ERROR_FRAMES
+#define RX_WATCHDOG_ERROR_FRAMES_ADDRESS 0x9a0
+#define RX_WATCHDOG_ERROR_FRAMES_NUM     1
+#define RX_WATCHDOG_ERROR_FRAMES_INC     0x4000
+#define RX_WATCHDOG_ERROR_FRAMES_TYPE    REG_TYPE_RO
+#define RX_WATCHDOG_ERROR_FRAMES_DEFAULT 0x0
+	/*[field] RXWDOGERR*/
+	#define RX_WATCHDOG_ERROR_FRAMES_RXWDOGERR
+	#define RX_WATCHDOG_ERROR_FRAMES_RXWDOGERR_OFFSET  0
+	#define RX_WATCHDOG_ERROR_FRAMES_RXWDOGERR_LEN     32
+	#define RX_WATCHDOG_ERROR_FRAMES_RXWDOGERR_DEFAULT 0x0
+
+struct rx_watchdog_error_frames {
+	a_uint32_t  rxwdogerr:32;
+};
+
+union rx_watchdog_error_frames_u {
+	a_uint32_t val;
+	struct rx_watchdog_error_frames bf;
+};
+
+/*[register] RX_LPI_USEC_CNTR*/
+#define RX_LPI_USEC_CNTR
+#define RX_LPI_USEC_CNTR_ADDRESS 0x9a4
+#define RX_LPI_USEC_CNTR_NUM     1
+#define RX_LPI_USEC_CNTR_INC     0x4000
+#define RX_LPI_USEC_CNTR_TYPE    REG_TYPE_RO
+#define RX_LPI_USEC_CNTR_DEFAULT 0x0
+	/*[field] RXLPIUSC*/
+	#define RX_LPI_USEC_CNTR_RXLPIUSC
+	#define RX_LPI_USEC_CNTR_RXLPIUSC_OFFSET  0
+	#define RX_LPI_USEC_CNTR_RXLPIUSC_LEN     32
+	#define RX_LPI_USEC_CNTR_RXLPIUSC_DEFAULT 0x0
+
+struct rx_lpi_usec_cntr {
+	a_uint32_t  rxlpiusc:32;
+};
+
+union rx_lpi_usec_cntr_u {
+	a_uint32_t val;
+	struct rx_lpi_usec_cntr bf;
+};
+
+/*[register] RX_LPI_TRAN_CNTR*/
+#define RX_LPI_TRAN_CNTR
+#define RX_LPI_TRAN_CNTR_ADDRESS 0x9a8
+#define RX_LPI_TRAN_CNTR_NUM     1
+#define RX_LPI_TRAN_CNTR_INC     0x4000
+#define RX_LPI_TRAN_CNTR_TYPE    REG_TYPE_RO
+#define RX_LPI_TRAN_CNTR_DEFAULT 0x0
+	/*[field] RXLPITRC*/
+	#define RX_LPI_TRAN_CNTR_RXLPITRC
+	#define RX_LPI_TRAN_CNTR_RXLPITRC_OFFSET  0
+	#define RX_LPI_TRAN_CNTR_RXLPITRC_LEN     32
+	#define RX_LPI_TRAN_CNTR_RXLPITRC_DEFAULT 0x0
+
+struct rx_lpi_tran_cntr {
+	a_uint32_t  rxlpitrc:32;
+};
+
+union rx_lpi_tran_cntr_u {
+	a_uint32_t val;
+	struct rx_lpi_tran_cntr bf;
+};
+
+/*[register] RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW*/
+#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW
+#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_ADDRESS 0x9ac
+#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_NUM     1
+#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_INC     0x4000
+#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] RXDFCNTGBLO*/
+	#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_RXDFCNTGBLO
+	#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_RXDFCNTGBLO_OFFSET  0
+	#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_RXDFCNTGBLO_LEN     32
+	#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_RXDFCNTGBLO_DEFAULT 0x0
+
+struct rx_discard_frame_count_good_bad_low {
+	a_uint32_t  rxdfcntgblo:32;
+};
+
+union rx_discard_frame_count_good_bad_low_u {
+	a_uint32_t val;
+	struct rx_discard_frame_count_good_bad_low bf;
+};
+
+/*[register] RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH*/
+#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH
+#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_ADDRESS 0x9b0
+#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_NUM     1
+#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_INC     0x4000
+#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] RXDFCNTGBHI*/
+	#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_RXDFCNTGBHI
+	#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_RXDFCNTGBHI_OFFSET  0
+	#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_RXDFCNTGBHI_LEN     32
+	#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_RXDFCNTGBHI_DEFAULT 0x0
+
+struct rx_discard_frame_count_good_bad_high {
+	a_uint32_t  rxdfcntgbhi:32;
+};
+
+union rx_discard_frame_count_good_bad_high_u {
+	a_uint32_t val;
+	struct rx_discard_frame_count_good_bad_high bf;
+};
+
+/*[register] RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW*/
+#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW
+#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_ADDRESS 0x9b4
+#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_NUM     1
+#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_INC     0x4000
+#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_TYPE    REG_TYPE_RO
+#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_DEFAULT 0x0
+	/*[field] RXDOCNTGBLO*/
+	#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_RXDOCNTGBLO
+	#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_RXDOCNTGBLO_OFFSET  0
+	#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_RXDOCNTGBLO_LEN     32
+	#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_RXDOCNTGBLO_DEFAULT 0x0
+
+struct rx_discard_octet_count_good_bad_low {
+	a_uint32_t  rxdocntgblo:32;
+};
+
+union rx_discard_octet_count_good_bad_low_u {
+	a_uint32_t val;
+	struct rx_discard_octet_count_good_bad_low bf;
+};
+
+/*[register] RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH*/
+#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH
+#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_ADDRESS 0x9b8
+#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_NUM     1
+#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_INC     0x4000
+#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_TYPE    REG_TYPE_RO
+#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_DEFAULT 0x0
+	/*[field] RXDOCNTGBHI*/
+	#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_RXDOCNTGBHI
+	#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_RXDOCNTGBHI_OFFSET  0
+	#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_RXDOCNTGBHI_LEN     32
+	#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_RXDOCNTGBHI_DEFAULT 0x0
+
+struct rx_discard_octet_count_good_bad_high {
+	a_uint32_t  rxdocntgbhi:32;
+};
+
+union rx_discard_octet_count_good_bad_high_u {
+	a_uint32_t val;
+	struct rx_discard_octet_count_good_bad_high bf;
+};
+
+
+
+#endif
diff --git a/qca-ssdk/include/hsl/hppe/hppe_xgportctrl.h b/qca-ssdk/include/hsl/hppe/hppe_xgportctrl.h
new file mode 100755
index 0000000..c55a104
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_xgportctrl.h
@@ -0,0 +1,2758 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _HPPE_XGPORTCTRL_H_
+#define _HPPE_XGPORTCTRL_H_
+
+#define MAC_TX_CONFIGURATION_MAX_ENTRY	2
+#define MAC_RX_CONFIGURATION_MAX_ENTRY	2
+#define MAC_PACKET_FILTER_MAX_ENTRY	2
+#define MAC_WATCHDOG_TIMEOUT_MAX_ENTRY	2
+#define MAC_VLAN_TAG_MAX_ENTRY	2
+#define MAC_RX_ETH_TYPE_MATCH_MAX_ENTRY	2
+#define MAC_Q0_TX_FLOW_CTRL_MAX_ENTRY	2
+#define MAC_RX_FLOW_CTRL_MAX_ENTRY	2
+#define MAC_INTERRUPT_STATUS_MAX_ENTRY	2
+#define MAC_INTERRUPT_ENABLE_MAX_ENTRY	2
+#define MAC_RX_TX_STATUS_MAX_ENTRY	2
+#define MAC_LPI_CONTROL_STATUS_MAX_ENTRY	2
+#define MAC_LPI_TIMERS_CONTROL_MAX_ENTRY	2
+#define MAC_LPI_AUTO_ENTRY_TIMER_MAX_ENTRY	2
+#define MAC_1US_TIC_COUNTER_MAX_ENTRY	2
+#define MAC_ADDRESS0_HIGH_MAX_ENTRY	2
+#define MAC_ADDRESS0_LOW_MAX_ENTRY	2
+#define MMC_RECEIVE_INTERRUPT_MAX_ENTRY	2
+#define MMC_TRANSMIT_INTERRUPT_MAX_ENTRY	2
+#define MMC_RECEIVE_INTERRUPT_ENABLE_MAX_ENTRY	2
+#define MMC_TRANSMIT_INTERRUPT_ENABLE_MAX_ENTRY	2
+
+sw_error_t
+hppe_mac_tx_configuration_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_tx_configuration_u *value);
+
+sw_error_t
+hppe_mac_tx_configuration_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_tx_configuration_u *value);
+
+sw_error_t
+hppe_mac_rx_configuration_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_configuration_u *value);
+
+sw_error_t
+hppe_mac_rx_configuration_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_configuration_u *value);
+
+sw_error_t
+hppe_mac_packet_filter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_packet_filter_u *value);
+
+sw_error_t
+hppe_mac_packet_filter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_packet_filter_u *value);
+
+sw_error_t
+hppe_mac_watchdog_timeout_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_watchdog_timeout_u *value);
+
+sw_error_t
+hppe_mac_watchdog_timeout_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_watchdog_timeout_u *value);
+
+sw_error_t
+hppe_mac_vlan_tag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_vlan_tag_u *value);
+
+sw_error_t
+hppe_mac_vlan_tag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_vlan_tag_u *value);
+
+sw_error_t
+hppe_mac_rx_eth_type_match_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_eth_type_match_u *value);
+
+sw_error_t
+hppe_mac_rx_eth_type_match_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_eth_type_match_u *value);
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_q0_tx_flow_ctrl_u *value);
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_q0_tx_flow_ctrl_u *value);
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_flow_ctrl_u *value);
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_flow_ctrl_u *value);
+
+sw_error_t
+hppe_mac_interrupt_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_interrupt_status_u *value);
+
+sw_error_t
+hppe_mac_interrupt_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_interrupt_status_u *value);
+
+sw_error_t
+hppe_mac_interrupt_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_interrupt_enable_u *value);
+
+sw_error_t
+hppe_mac_interrupt_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_interrupt_enable_u *value);
+
+sw_error_t
+hppe_mac_rx_tx_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_tx_status_u *value);
+
+sw_error_t
+hppe_mac_rx_tx_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_tx_status_u *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_lpi_control_status_u *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_lpi_control_status_u *value);
+
+sw_error_t
+hppe_mac_lpi_timers_control_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_lpi_timers_control_u *value);
+
+sw_error_t
+hppe_mac_lpi_timers_control_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_lpi_timers_control_u *value);
+
+sw_error_t
+hppe_mac_lpi_auto_entry_timer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_lpi_auto_entry_timer_u *value);
+
+sw_error_t
+hppe_mac_lpi_auto_entry_timer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_lpi_auto_entry_timer_u *value);
+
+sw_error_t
+hppe_mac_1us_tic_counter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_1us_tic_counter_u *value);
+
+sw_error_t
+hppe_mac_1us_tic_counter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_1us_tic_counter_u *value);
+
+sw_error_t
+hppe_mac_address0_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_address0_high_u *value);
+
+sw_error_t
+hppe_mac_address0_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_address0_high_u *value);
+
+sw_error_t
+hppe_mac_address0_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_address0_low_u *value);
+
+sw_error_t
+hppe_mac_address0_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_address0_low_u *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_receive_interrupt_u *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_receive_interrupt_u *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_transmit_interrupt_u *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_transmit_interrupt_u *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_receive_interrupt_enable_u *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_receive_interrupt_enable_u *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_transmit_interrupt_enable_u *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_transmit_interrupt_enable_u *value);
+
+sw_error_t
+hppe_mac_tx_configuration_vne_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_tx_configuration_vne_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_tx_configuration_ddic_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_tx_configuration_ddic_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_tx_configuration_te_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_tx_configuration_te_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_tx_configuration_ipg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_tx_configuration_ipg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_tx_configuration_ism_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_tx_configuration_ism_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_tx_configuration_ifp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_tx_configuration_ifp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_tx_configuration_sarc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_tx_configuration_sarc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_tx_configuration_isr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_tx_configuration_isr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_tx_configuration_ss_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_tx_configuration_ss_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_tx_configuration_g9991en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_tx_configuration_g9991en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_tx_configuration_uss_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_tx_configuration_uss_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_tx_configuration_vnm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_tx_configuration_vnm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_tx_configuration_jd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_tx_configuration_jd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_lm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_lm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_je_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_je_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_arpen_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_arpen_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_elen_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_elen_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_gmpslce_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_gmpslce_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_hdsms_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_hdsms_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_spen_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_spen_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_usp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_usp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_ipc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_ipc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_gpsl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_gpsl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_re_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_re_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_cst_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_cst_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_dcrcc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_dcrcc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_wd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_wd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_acs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_acs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_configuration_s2kp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_configuration_s2kp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_packet_filter_pcf_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_packet_filter_pcf_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_packet_filter_hmc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_packet_filter_hmc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_packet_filter_dntu_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_packet_filter_dntu_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_packet_filter_saf_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_packet_filter_saf_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_packet_filter_dbf_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_packet_filter_dbf_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_packet_filter_huc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_packet_filter_huc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_packet_filter_vtfe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_packet_filter_vtfe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_packet_filter_daif_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_packet_filter_daif_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_packet_filter_ra_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_packet_filter_ra_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_packet_filter_hpf_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_packet_filter_hpf_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_packet_filter_pm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_packet_filter_pm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_packet_filter_vucc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_packet_filter_vucc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_packet_filter_pr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_packet_filter_pr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_packet_filter_ipfe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_packet_filter_ipfe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_packet_filter_saif_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_packet_filter_saif_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_watchdog_timeout_pwe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_watchdog_timeout_pwe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_watchdog_timeout_wto_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_watchdog_timeout_wto_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_vlan_tag_eivls_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_vlan_tag_eivls_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_vlan_tag_vthm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_vlan_tag_vthm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_vlan_tag_vl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_vlan_tag_vl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_vlan_tag_dovltc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_vlan_tag_dovltc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_vlan_tag_etv_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_vlan_tag_etv_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_vlan_tag_erivlt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_vlan_tag_erivlt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_vlan_tag_eivlrxs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_vlan_tag_eivlrxs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_vlan_tag_vtim_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_vlan_tag_vtim_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_vlan_tag_edvlp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_vlan_tag_edvlp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_vlan_tag_evlrxs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_vlan_tag_evlrxs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_vlan_tag_evls_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_vlan_tag_evls_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_vlan_tag_esvl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_vlan_tag_esvl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_vlan_tag_ersvlm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_vlan_tag_ersvlm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_eth_type_match_et_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_eth_type_match_et_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_pt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_pt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_plt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_plt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_tfe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_tfe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_fcb_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_fcb_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_dapq_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_dapq_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_pfce_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_pfce_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_up_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_up_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_rfe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_rfe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_interrupt_status_txesis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_interrupt_status_txesis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_interrupt_status_gpiis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_interrupt_status_gpiis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_interrupt_status_tsis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_interrupt_status_tsis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_interrupt_status_mmctxis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_interrupt_status_mmctxis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_interrupt_status_ls_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_interrupt_status_ls_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_interrupt_status_mmcrxis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_interrupt_status_mmcrxis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_interrupt_status_smi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_interrupt_status_smi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_interrupt_status_pmtis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_interrupt_status_pmtis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_interrupt_status_rxesis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_interrupt_status_rxesis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_interrupt_status_lpiis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_interrupt_status_lpiis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_interrupt_enable_tsie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_interrupt_enable_tsie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_interrupt_enable_lpiie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_interrupt_enable_lpiie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_interrupt_enable_txesie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_interrupt_enable_txesie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_interrupt_enable_pmtie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_interrupt_enable_pmtie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_interrupt_enable_rxesie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_interrupt_enable_rxesie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_tx_status_tjt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_tx_status_tjt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_rx_tx_status_rwt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_rx_tx_status_rwt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_control_status_tlpien_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_tlpien_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_control_status_lpitcse_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_lpitcse_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_control_status_rxrstp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_rxrstp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_control_status_lpite_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_lpite_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_control_status_pls_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_pls_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_control_status_rlpiex_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_rlpiex_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_control_status_rlpien_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_rlpien_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_control_status_rlpist_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_rlpist_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_control_status_tlpist_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_tlpist_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_control_status_txrstp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_txrstp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_control_status_plsdis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_plsdis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_control_status_lpitxa_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_lpitxa_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_control_status_tlpiex_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_tlpiex_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_control_status_lpitxen_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_control_status_lpitxen_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_timers_control_lst_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_timers_control_lst_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_timers_control_twt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_timers_control_twt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_lpi_auto_entry_timer_lpiet_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_lpi_auto_entry_timer_lpiet_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_1us_tic_counter_tic_1us_cntr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_1us_tic_counter_tic_1us_cntr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_address0_high_addrhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_address0_high_addrhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_address0_high_ae_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_address0_high_ae_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_address0_high_dcs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_address0_high_dcs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mac_address0_low_addrlo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mac_address0_low_addrlo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxorangefis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxorangefis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxlenerfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxlenerfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx65t127octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx65t127octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxprmmcis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxprmmcis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx512t1023octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx512t1023octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxgboctis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxgboctis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxlpiuscis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxlpiuscis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxjaberfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxjaberfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxvlangbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxvlangbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxpausfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxpausfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxcrcerfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxcrcerfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxdisocgbis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxdisocgbis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxwdogfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxwdogfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx128t255octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx128t255octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxdisfcgbis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxdisfcgbis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxosizegfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxosizegfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx1024tmaxoctgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx1024tmaxoctgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxruntfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxruntfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxmcgfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxmcgfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx256t511octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx256t511octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx64octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx64octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxfovfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxfovfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxgoctis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxgoctis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxgbfrmis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxgbfrmis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxlpitrcis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxlpitrcis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxbcgfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxbcgfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxusizegfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxusizegfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxucgfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxucgfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgbfrmis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgbfrmis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txprmmcis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txprmmcis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx1024tmaxoctgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx1024tmaxoctgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx256t511octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx256t511octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txlpitrcis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txlpitrcis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txbcgfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txbcgfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx64octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx64octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txlpiuscis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txlpiuscis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txuflowerfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txuflowerfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txbcgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txbcgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txpausfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txpausfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txvlangfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txvlangfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgboctis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgboctis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgfrmis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgfrmis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx512t1023octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx512t1023octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txmcgfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txmcgfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txucgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txucgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx65t127octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx65t127octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txmcgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txmcgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx128t255octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx128t255octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgoctis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgoctis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxprmmcise_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxprmmcise_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx65t127octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx65t127octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxruntfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxruntfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxcrcerfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxcrcerfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx256t511octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx256t511octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxlenerfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxlenerfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxusizegfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxusizegfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxosizegfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxosizegfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxfovfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxfovfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxmcgfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxmcgfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxvlangbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxvlangbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxwdogfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxwdogfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxdisocie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxdisocie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxgbfrmie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxgbfrmie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxjaberfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxjaberfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxlpiuscie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxlpiuscie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxucgfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxucgfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx1024tmaxoctgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx1024tmaxoctgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxpausfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxpausfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxdisfcie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxdisfcie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxgoctie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxgoctie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxgboctie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxgboctie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx128t255octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx128t255octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxlpitrcie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxlpitrcie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxbcgfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxbcgfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx64octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx64octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxorangefie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxorangefie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx512t1023octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx512t1023octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txucgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txucgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx64octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx64octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txbcgfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txbcgfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgbfrmie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgbfrmie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgfrmie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgfrmie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgoctie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgoctie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txbcgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txbcgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txlpitrcie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txlpitrcie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txvlangfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txvlangfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txpausfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txpausfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgboctie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgboctie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txmcgfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txmcgfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txuflowerfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txuflowerfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txlpiuscie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txlpiuscie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx256t511octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx256t511octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx65t127octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx65t127octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx128t255octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx128t255octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx512t1023octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx512t1023octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx1024tmaxoctgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx1024tmaxoctgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txprmmcise_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txprmmcise_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txmcgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value);
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txmcgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/hppe/hppe_xgportctrl_reg.h b/qca-ssdk/include/hsl/hppe/hppe_xgportctrl_reg.h
new file mode 100755
index 0000000..2adf063
--- /dev/null
+++ b/qca-ssdk/include/hsl/hppe/hppe_xgportctrl_reg.h
@@ -0,0 +1,1627 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef HPPE_XGPORTCTRL_REG_H
+#define HPPE_XGPORTCTRL_REG_H
+
+/*[register] MAC_TX_CONFIGURATION*/
+#define MAC_TX_CONFIGURATION
+#define MAC_TX_CONFIGURATION_ADDRESS 0x0
+#define MAC_TX_CONFIGURATION_NUM     2
+#define MAC_TX_CONFIGURATION_INC     0x4000
+#define MAC_TX_CONFIGURATION_TYPE    REG_TYPE_RW
+#define MAC_TX_CONFIGURATION_DEFAULT 0x4000000
+	/*[field] TE*/
+	#define MAC_TX_CONFIGURATION_TE
+	#define MAC_TX_CONFIGURATION_TE_OFFSET  0
+	#define MAC_TX_CONFIGURATION_TE_LEN     1
+	#define MAC_TX_CONFIGURATION_TE_DEFAULT 0x0
+	/*[field] DDIC*/
+	#define MAC_TX_CONFIGURATION_DDIC
+	#define MAC_TX_CONFIGURATION_DDIC_OFFSET  1
+	#define MAC_TX_CONFIGURATION_DDIC_LEN     1
+	#define MAC_TX_CONFIGURATION_DDIC_DEFAULT 0x0
+	/*[field] ISM*/
+	#define MAC_TX_CONFIGURATION_ISM
+	#define MAC_TX_CONFIGURATION_ISM_OFFSET  3
+	#define MAC_TX_CONFIGURATION_ISM_LEN     1
+	#define MAC_TX_CONFIGURATION_ISM_DEFAULT 0x0
+	/*[field] ISR*/
+	#define MAC_TX_CONFIGURATION_ISR
+	#define MAC_TX_CONFIGURATION_ISR_OFFSET  4
+	#define MAC_TX_CONFIGURATION_ISR_LEN     4
+	#define MAC_TX_CONFIGURATION_ISR_DEFAULT 0x0
+	/*[field] IPG*/
+	#define MAC_TX_CONFIGURATION_IPG
+	#define MAC_TX_CONFIGURATION_IPG_OFFSET  8
+	#define MAC_TX_CONFIGURATION_IPG_LEN     3
+	#define MAC_TX_CONFIGURATION_IPG_DEFAULT 0x0
+	/*[field] IFP*/
+	#define MAC_TX_CONFIGURATION_IFP
+	#define MAC_TX_CONFIGURATION_IFP_OFFSET  11
+	#define MAC_TX_CONFIGURATION_IFP_LEN     1
+	#define MAC_TX_CONFIGURATION_IFP_DEFAULT 0x0
+	/*[field] JD*/
+	#define MAC_TX_CONFIGURATION_JD
+	#define MAC_TX_CONFIGURATION_JD_OFFSET  16
+	#define MAC_TX_CONFIGURATION_JD_LEN     1
+	#define MAC_TX_CONFIGURATION_JD_DEFAULT 0x0
+	/*[field] SARC*/
+	#define MAC_TX_CONFIGURATION_SARC
+	#define MAC_TX_CONFIGURATION_SARC_OFFSET  20
+	#define MAC_TX_CONFIGURATION_SARC_LEN     3
+	#define MAC_TX_CONFIGURATION_SARC_DEFAULT 0x0
+	/*[field] VNE*/
+	#define MAC_TX_CONFIGURATION_VNE
+	#define MAC_TX_CONFIGURATION_VNE_OFFSET  24
+	#define MAC_TX_CONFIGURATION_VNE_LEN     1
+	#define MAC_TX_CONFIGURATION_VNE_DEFAULT 0x0
+	/*[field] VNM*/
+	#define MAC_TX_CONFIGURATION_VNM
+	#define MAC_TX_CONFIGURATION_VNM_OFFSET  25
+	#define MAC_TX_CONFIGURATION_VNM_LEN     1
+	#define MAC_TX_CONFIGURATION_VNM_DEFAULT 0x0
+	/*[field] G9991EN*/
+	#define MAC_TX_CONFIGURATION_G9991EN
+	#define MAC_TX_CONFIGURATION_G9991EN_OFFSET  28
+	#define MAC_TX_CONFIGURATION_G9991EN_LEN     1
+	#define MAC_TX_CONFIGURATION_G9991EN_DEFAULT 0x0
+	/*[field] SS*/
+	#define MAC_TX_CONFIGURATION_SS
+	#define MAC_TX_CONFIGURATION_SS_OFFSET  29
+	#define MAC_TX_CONFIGURATION_SS_LEN     2
+	#define MAC_TX_CONFIGURATION_SS_DEFAULT 0x0
+	/*[field] USS*/
+	#define MAC_TX_CONFIGURATION_USS
+	#define MAC_TX_CONFIGURATION_USS_OFFSET  31
+	#define MAC_TX_CONFIGURATION_USS_LEN     1
+	#define MAC_TX_CONFIGURATION_USS_DEFAULT 0x0
+
+struct mac_tx_configuration {
+	a_uint32_t  te:1;
+	a_uint32_t  ddic:1;
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  ism:1;
+	a_uint32_t  isr:4;
+	a_uint32_t  ipg:3;
+	a_uint32_t  ifp:1;
+	a_uint32_t  _reserved1:4;
+	a_uint32_t  jd:1;
+	a_uint32_t  _reserved2:3;
+	a_uint32_t  sarc:3;
+	a_uint32_t  _reserved3:1;
+	a_uint32_t  vne:1;
+	a_uint32_t  vnm:1;
+	a_uint32_t  _reserved4:2;
+	a_uint32_t  g9991en:1;
+	a_uint32_t  ss:2;
+	a_uint32_t  uss:1;
+};
+
+union mac_tx_configuration_u {
+	a_uint32_t val;
+	struct mac_tx_configuration bf;
+};
+
+/*[register] MAC_RX_CONFIGURATION*/
+#define MAC_RX_CONFIGURATION
+#define MAC_RX_CONFIGURATION_ADDRESS 0x4
+#define MAC_RX_CONFIGURATION_NUM     2
+#define MAC_RX_CONFIGURATION_INC     0x4000
+#define MAC_RX_CONFIGURATION_TYPE    REG_TYPE_RW
+#define MAC_RX_CONFIGURATION_DEFAULT 0x0
+	/*[field] RE*/
+	#define MAC_RX_CONFIGURATION_RE
+	#define MAC_RX_CONFIGURATION_RE_OFFSET  0
+	#define MAC_RX_CONFIGURATION_RE_LEN     1
+	#define MAC_RX_CONFIGURATION_RE_DEFAULT 0x0
+	/*[field] ACS*/
+	#define MAC_RX_CONFIGURATION_ACS
+	#define MAC_RX_CONFIGURATION_ACS_OFFSET  1
+	#define MAC_RX_CONFIGURATION_ACS_LEN     1
+	#define MAC_RX_CONFIGURATION_ACS_DEFAULT 0x0
+	/*[field] CST*/
+	#define MAC_RX_CONFIGURATION_CST
+	#define MAC_RX_CONFIGURATION_CST_OFFSET  2
+	#define MAC_RX_CONFIGURATION_CST_LEN     1
+	#define MAC_RX_CONFIGURATION_CST_DEFAULT 0x0
+	/*[field] DCRCC*/
+	#define MAC_RX_CONFIGURATION_DCRCC
+	#define MAC_RX_CONFIGURATION_DCRCC_OFFSET  3
+	#define MAC_RX_CONFIGURATION_DCRCC_LEN     1
+	#define MAC_RX_CONFIGURATION_DCRCC_DEFAULT 0x0
+	/*[field] SPEN*/
+	#define MAC_RX_CONFIGURATION_SPEN
+	#define MAC_RX_CONFIGURATION_SPEN_OFFSET  4
+	#define MAC_RX_CONFIGURATION_SPEN_LEN     1
+	#define MAC_RX_CONFIGURATION_SPEN_DEFAULT 0x0
+	/*[field] USP*/
+	#define MAC_RX_CONFIGURATION_USP
+	#define MAC_RX_CONFIGURATION_USP_OFFSET  5
+	#define MAC_RX_CONFIGURATION_USP_LEN     1
+	#define MAC_RX_CONFIGURATION_USP_DEFAULT 0x0
+	/*[field] GMPSLCE*/
+	#define MAC_RX_CONFIGURATION_GMPSLCE
+	#define MAC_RX_CONFIGURATION_GMPSLCE_OFFSET  6
+	#define MAC_RX_CONFIGURATION_GMPSLCE_LEN     1
+	#define MAC_RX_CONFIGURATION_GMPSLCE_DEFAULT 0x0
+	/*[field] WD*/
+	#define MAC_RX_CONFIGURATION_WD
+	#define MAC_RX_CONFIGURATION_WD_OFFSET  7
+	#define MAC_RX_CONFIGURATION_WD_LEN     1
+	#define MAC_RX_CONFIGURATION_WD_DEFAULT 0x0
+	/*[field] JE*/
+	#define MAC_RX_CONFIGURATION_JE
+	#define MAC_RX_CONFIGURATION_JE_OFFSET  8
+	#define MAC_RX_CONFIGURATION_JE_LEN     1
+	#define MAC_RX_CONFIGURATION_JE_DEFAULT 0x0
+	/*[field] IPC*/
+	#define MAC_RX_CONFIGURATION_IPC
+	#define MAC_RX_CONFIGURATION_IPC_OFFSET  9
+	#define MAC_RX_CONFIGURATION_IPC_LEN     1
+	#define MAC_RX_CONFIGURATION_IPC_DEFAULT 0x0
+	/*[field] LM*/
+	#define MAC_RX_CONFIGURATION_LM
+	#define MAC_RX_CONFIGURATION_LM_OFFSET  10
+	#define MAC_RX_CONFIGURATION_LM_LEN     1
+	#define MAC_RX_CONFIGURATION_LM_DEFAULT 0x0
+	/*[field] S2KP*/
+	#define MAC_RX_CONFIGURATION_S2KP
+	#define MAC_RX_CONFIGURATION_S2KP_OFFSET  11
+	#define MAC_RX_CONFIGURATION_S2KP_LEN     1
+	#define MAC_RX_CONFIGURATION_S2KP_DEFAULT 0x0
+	/*[field] HDSMS*/
+	#define MAC_RX_CONFIGURATION_HDSMS
+	#define MAC_RX_CONFIGURATION_HDSMS_OFFSET  12
+	#define MAC_RX_CONFIGURATION_HDSMS_LEN     3
+	#define MAC_RX_CONFIGURATION_HDSMS_DEFAULT 0x0
+	/*[field] GPSL*/
+	#define MAC_RX_CONFIGURATION_GPSL
+	#define MAC_RX_CONFIGURATION_GPSL_OFFSET  16
+	#define MAC_RX_CONFIGURATION_GPSL_LEN     14
+	#define MAC_RX_CONFIGURATION_GPSL_DEFAULT 0x0
+	/*[field] ELEN*/
+	#define MAC_RX_CONFIGURATION_ELEN
+	#define MAC_RX_CONFIGURATION_ELEN_OFFSET  30
+	#define MAC_RX_CONFIGURATION_ELEN_LEN     1
+	#define MAC_RX_CONFIGURATION_ELEN_DEFAULT 0x0
+	/*[field] ARPEN*/
+	#define MAC_RX_CONFIGURATION_ARPEN
+	#define MAC_RX_CONFIGURATION_ARPEN_OFFSET  31
+	#define MAC_RX_CONFIGURATION_ARPEN_LEN     1
+	#define MAC_RX_CONFIGURATION_ARPEN_DEFAULT 0x0
+
+struct mac_rx_configuration {
+	a_uint32_t  re:1;
+	a_uint32_t  acs:1;
+	a_uint32_t  cst:1;
+	a_uint32_t  dcrcc:1;
+	a_uint32_t  spen:1;
+	a_uint32_t  usp:1;
+	a_uint32_t  gmpslce:1;
+	a_uint32_t  wd:1;
+	a_uint32_t  je:1;
+	a_uint32_t  ipc:1;
+	a_uint32_t  lm:1;
+	a_uint32_t  s2kp:1;
+	a_uint32_t  hdsms:3;
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  gpsl:14;
+	a_uint32_t  elen:1;
+	a_uint32_t  arpen:1;
+};
+
+union mac_rx_configuration_u {
+	a_uint32_t val;
+	struct mac_rx_configuration bf;
+};
+
+/*[register] MAC_PACKET_FILTER*/
+#define MAC_PACKET_FILTER
+#define MAC_PACKET_FILTER_ADDRESS 0x8
+#define MAC_PACKET_FILTER_NUM     2
+#define MAC_PACKET_FILTER_INC     0x4000
+#define MAC_PACKET_FILTER_TYPE    REG_TYPE_RW
+#define MAC_PACKET_FILTER_DEFAULT 0x0
+	/*[field] PR*/
+	#define MAC_PACKET_FILTER_PR
+	#define MAC_PACKET_FILTER_PR_OFFSET  0
+	#define MAC_PACKET_FILTER_PR_LEN     1
+	#define MAC_PACKET_FILTER_PR_DEFAULT 0x0
+	/*[field] HUC*/
+	#define MAC_PACKET_FILTER_HUC
+	#define MAC_PACKET_FILTER_HUC_OFFSET  1
+	#define MAC_PACKET_FILTER_HUC_LEN     1
+	#define MAC_PACKET_FILTER_HUC_DEFAULT 0x0
+	/*[field] HMC*/
+	#define MAC_PACKET_FILTER_HMC
+	#define MAC_PACKET_FILTER_HMC_OFFSET  2
+	#define MAC_PACKET_FILTER_HMC_LEN     1
+	#define MAC_PACKET_FILTER_HMC_DEFAULT 0x0
+	/*[field] DAIF*/
+	#define MAC_PACKET_FILTER_DAIF
+	#define MAC_PACKET_FILTER_DAIF_OFFSET  3
+	#define MAC_PACKET_FILTER_DAIF_LEN     1
+	#define MAC_PACKET_FILTER_DAIF_DEFAULT 0x0
+	/*[field] PM*/
+	#define MAC_PACKET_FILTER_PM
+	#define MAC_PACKET_FILTER_PM_OFFSET  4
+	#define MAC_PACKET_FILTER_PM_LEN     1
+	#define MAC_PACKET_FILTER_PM_DEFAULT 0x0
+	/*[field] DBF*/
+	#define MAC_PACKET_FILTER_DBF
+	#define MAC_PACKET_FILTER_DBF_OFFSET  5
+	#define MAC_PACKET_FILTER_DBF_LEN     1
+	#define MAC_PACKET_FILTER_DBF_DEFAULT 0x0
+	/*[field] PCF*/
+	#define MAC_PACKET_FILTER_PCF
+	#define MAC_PACKET_FILTER_PCF_OFFSET  6
+	#define MAC_PACKET_FILTER_PCF_LEN     2
+	#define MAC_PACKET_FILTER_PCF_DEFAULT 0x0
+	/*[field] SAIF*/
+	#define MAC_PACKET_FILTER_SAIF
+	#define MAC_PACKET_FILTER_SAIF_OFFSET  8
+	#define MAC_PACKET_FILTER_SAIF_LEN     1
+	#define MAC_PACKET_FILTER_SAIF_DEFAULT 0x0
+	/*[field] SAF*/
+	#define MAC_PACKET_FILTER_SAF
+	#define MAC_PACKET_FILTER_SAF_OFFSET  9
+	#define MAC_PACKET_FILTER_SAF_LEN     1
+	#define MAC_PACKET_FILTER_SAF_DEFAULT 0x0
+	/*[field] HPF*/
+	#define MAC_PACKET_FILTER_HPF
+	#define MAC_PACKET_FILTER_HPF_OFFSET  10
+	#define MAC_PACKET_FILTER_HPF_LEN     1
+	#define MAC_PACKET_FILTER_HPF_DEFAULT 0x0
+	/*[field] VTFE*/
+	#define MAC_PACKET_FILTER_VTFE
+	#define MAC_PACKET_FILTER_VTFE_OFFSET  16
+	#define MAC_PACKET_FILTER_VTFE_LEN     1
+	#define MAC_PACKET_FILTER_VTFE_DEFAULT 0x0
+	/*[field] IPFE*/
+	#define MAC_PACKET_FILTER_IPFE
+	#define MAC_PACKET_FILTER_IPFE_OFFSET  20
+	#define MAC_PACKET_FILTER_IPFE_LEN     1
+	#define MAC_PACKET_FILTER_IPFE_DEFAULT 0x0
+	/*[field] DNTU*/
+	#define MAC_PACKET_FILTER_DNTU
+	#define MAC_PACKET_FILTER_DNTU_OFFSET  21
+	#define MAC_PACKET_FILTER_DNTU_LEN     1
+	#define MAC_PACKET_FILTER_DNTU_DEFAULT 0x0
+	/*[field] VUCC*/
+	#define MAC_PACKET_FILTER_VUCC
+	#define MAC_PACKET_FILTER_VUCC_OFFSET  22
+	#define MAC_PACKET_FILTER_VUCC_LEN     1
+	#define MAC_PACKET_FILTER_VUCC_DEFAULT 0x0
+	/*[field] RA*/
+	#define MAC_PACKET_FILTER_RA
+	#define MAC_PACKET_FILTER_RA_OFFSET  31
+	#define MAC_PACKET_FILTER_RA_LEN     1
+	#define MAC_PACKET_FILTER_RA_DEFAULT 0x0
+
+struct mac_packet_filter {
+	a_uint32_t  pr:1;
+	a_uint32_t  huc:1;
+	a_uint32_t  hmc:1;
+	a_uint32_t  daif:1;
+	a_uint32_t  pm:1;
+	a_uint32_t  dbf:1;
+	a_uint32_t  pcf:2;
+	a_uint32_t  saif:1;
+	a_uint32_t  saf:1;
+	a_uint32_t  hpf:1;
+	a_uint32_t  _reserved0:5;
+	a_uint32_t  vtfe:1;
+	a_uint32_t  _reserved1:3;
+	a_uint32_t  ipfe:1;
+	a_uint32_t  dntu:1;
+	a_uint32_t  vucc:1;
+	a_uint32_t  _reserved2:8;
+	a_uint32_t  ra:1;
+};
+
+union mac_packet_filter_u {
+	a_uint32_t val;
+	struct mac_packet_filter bf;
+};
+
+/*[register] MAC_WATCHDOG_TIMEOUT*/
+#define MAC_WATCHDOG_TIMEOUT
+#define MAC_WATCHDOG_TIMEOUT_ADDRESS 0xc
+#define MAC_WATCHDOG_TIMEOUT_NUM     2
+#define MAC_WATCHDOG_TIMEOUT_INC     0x4000
+#define MAC_WATCHDOG_TIMEOUT_TYPE    REG_TYPE_RW
+#define MAC_WATCHDOG_TIMEOUT_DEFAULT 0x0
+	/*[field] WTO*/
+	#define MAC_WATCHDOG_TIMEOUT_WTO
+	#define MAC_WATCHDOG_TIMEOUT_WTO_OFFSET  0
+	#define MAC_WATCHDOG_TIMEOUT_WTO_LEN     4
+	#define MAC_WATCHDOG_TIMEOUT_WTO_DEFAULT 0x0
+	/*[field] PWE*/
+	#define MAC_WATCHDOG_TIMEOUT_PWE
+	#define MAC_WATCHDOG_TIMEOUT_PWE_OFFSET  8
+	#define MAC_WATCHDOG_TIMEOUT_PWE_LEN     1
+	#define MAC_WATCHDOG_TIMEOUT_PWE_DEFAULT 0x0
+
+struct mac_watchdog_timeout {
+	a_uint32_t  wto:4;
+	a_uint32_t  _reserved0:4;
+	a_uint32_t  pwe:1;
+	a_uint32_t  _reserved1:23;
+};
+
+union mac_watchdog_timeout_u {
+	a_uint32_t val;
+	struct mac_watchdog_timeout bf;
+};
+
+/*[register] MAC_VLAN_TAG*/
+#define MAC_VLAN_TAG
+#define MAC_VLAN_TAG_ADDRESS 0x50
+#define MAC_VLAN_TAG_NUM     2
+#define MAC_VLAN_TAG_INC     0x4000
+#define MAC_VLAN_TAG_TYPE    REG_TYPE_RW
+#define MAC_VLAN_TAG_DEFAULT 0x1b800000
+	/*[field] VL*/
+	#define MAC_VLAN_TAG_VL
+	#define MAC_VLAN_TAG_VL_OFFSET  0
+	#define MAC_VLAN_TAG_VL_LEN     16
+	#define MAC_VLAN_TAG_VL_DEFAULT 0x0
+	/*[field] ETV*/
+	#define MAC_VLAN_TAG_ETV
+	#define MAC_VLAN_TAG_ETV_OFFSET  16
+	#define MAC_VLAN_TAG_ETV_LEN     1
+	#define MAC_VLAN_TAG_ETV_DEFAULT 0x0
+	/*[field] VTIM*/
+	#define MAC_VLAN_TAG_VTIM
+	#define MAC_VLAN_TAG_VTIM_OFFSET  17
+	#define MAC_VLAN_TAG_VTIM_LEN     1
+	#define MAC_VLAN_TAG_VTIM_DEFAULT 0x0
+	/*[field] ESVL*/
+	#define MAC_VLAN_TAG_ESVL
+	#define MAC_VLAN_TAG_ESVL_OFFSET  18
+	#define MAC_VLAN_TAG_ESVL_LEN     1
+	#define MAC_VLAN_TAG_ESVL_DEFAULT 0x0
+	/*[field] ERSVLM*/
+	#define MAC_VLAN_TAG_ERSVLM
+	#define MAC_VLAN_TAG_ERSVLM_OFFSET  19
+	#define MAC_VLAN_TAG_ERSVLM_LEN     1
+	#define MAC_VLAN_TAG_ERSVLM_DEFAULT 0x0
+	/*[field] DOVLTC*/
+	#define MAC_VLAN_TAG_DOVLTC
+	#define MAC_VLAN_TAG_DOVLTC_OFFSET  20
+	#define MAC_VLAN_TAG_DOVLTC_LEN     1
+	#define MAC_VLAN_TAG_DOVLTC_DEFAULT 0x0
+	/*[field] EVLS*/
+	#define MAC_VLAN_TAG_EVLS
+	#define MAC_VLAN_TAG_EVLS_OFFSET  21
+	#define MAC_VLAN_TAG_EVLS_LEN     2
+	#define MAC_VLAN_TAG_EVLS_DEFAULT 0x0
+	/*[field] EVLRXS*/
+	#define MAC_VLAN_TAG_EVLRXS
+	#define MAC_VLAN_TAG_EVLRXS_OFFSET  24
+	#define MAC_VLAN_TAG_EVLRXS_LEN     1
+	#define MAC_VLAN_TAG_EVLRXS_DEFAULT 0x1
+	/*[field] VTHM*/
+	#define MAC_VLAN_TAG_VTHM
+	#define MAC_VLAN_TAG_VTHM_OFFSET  25
+	#define MAC_VLAN_TAG_VTHM_LEN     1
+	#define MAC_VLAN_TAG_VTHM_DEFAULT 0x1
+	/*[field] EDVLP*/
+	#define MAC_VLAN_TAG_EDVLP
+	#define MAC_VLAN_TAG_EDVLP_OFFSET  26
+	#define MAC_VLAN_TAG_EDVLP_LEN     1
+	#define MAC_VLAN_TAG_EDVLP_DEFAULT 0x0
+	/*[field] ERIVLT*/
+	#define MAC_VLAN_TAG_ERIVLT
+	#define MAC_VLAN_TAG_ERIVLT_OFFSET  27
+	#define MAC_VLAN_TAG_ERIVLT_LEN     1
+	#define MAC_VLAN_TAG_ERIVLT_DEFAULT 0x1
+	/*[field] EIVLS*/
+	#define MAC_VLAN_TAG_EIVLS
+	#define MAC_VLAN_TAG_EIVLS_OFFSET  28
+	#define MAC_VLAN_TAG_EIVLS_LEN     2
+	#define MAC_VLAN_TAG_EIVLS_DEFAULT 0x1
+	/*[field] EIVLRXS*/
+	#define MAC_VLAN_TAG_EIVLRXS
+	#define MAC_VLAN_TAG_EIVLRXS_OFFSET  31
+	#define MAC_VLAN_TAG_EIVLRXS_LEN     1
+	#define MAC_VLAN_TAG_EIVLRXS_DEFAULT 0x0
+
+struct mac_vlan_tag {
+	a_uint32_t  vl:16;
+	a_uint32_t  etv:1;
+	a_uint32_t  vtim:1;
+	a_uint32_t  esvl:1;
+	a_uint32_t  ersvlm:1;
+	a_uint32_t  dovltc:1;
+	a_uint32_t  evls:2;
+	a_uint32_t  _reserved0:1;
+	a_uint32_t  evlrxs:1;
+	a_uint32_t  vthm:1;
+	a_uint32_t  edvlp:1;
+	a_uint32_t  erivlt:1;
+	a_uint32_t  eivls:2;
+	a_uint32_t  _reserved1:1;
+	a_uint32_t  eivlrxs:1;
+};
+
+union mac_vlan_tag_u {
+	a_uint32_t val;
+	struct mac_vlan_tag bf;
+};
+
+/*[register] MAC_RX_ETH_TYPE_MATCH*/
+#define MAC_RX_ETH_TYPE_MATCH
+#define MAC_RX_ETH_TYPE_MATCH_ADDRESS 0x6c
+#define MAC_RX_ETH_TYPE_MATCH_NUM     2
+#define MAC_RX_ETH_TYPE_MATCH_INC     0x4000
+#define MAC_RX_ETH_TYPE_MATCH_TYPE    REG_TYPE_RW
+#define MAC_RX_ETH_TYPE_MATCH_DEFAULT 0x0
+	/*[field] ET*/
+	#define MAC_RX_ETH_TYPE_MATCH_ET
+	#define MAC_RX_ETH_TYPE_MATCH_ET_OFFSET  0
+	#define MAC_RX_ETH_TYPE_MATCH_ET_LEN     16
+	#define MAC_RX_ETH_TYPE_MATCH_ET_DEFAULT 0x0
+
+struct mac_rx_eth_type_match {
+	a_uint32_t  et:16;
+	a_uint32_t  _reserved0:16;
+};
+
+union mac_rx_eth_type_match_u {
+	a_uint32_t val;
+	struct mac_rx_eth_type_match bf;
+};
+
+/*[register] MAC_Q0_TX_FLOW_CTRL*/
+#define MAC_Q0_TX_FLOW_CTRL
+#define MAC_Q0_TX_FLOW_CTRL_ADDRESS 0x70
+#define MAC_Q0_TX_FLOW_CTRL_NUM     2
+#define MAC_Q0_TX_FLOW_CTRL_INC     0x4000
+#define MAC_Q0_TX_FLOW_CTRL_TYPE    REG_TYPE_RW
+#define MAC_Q0_TX_FLOW_CTRL_DEFAULT 0x2
+	/*[field] FCB*/
+	#define MAC_Q0_TX_FLOW_CTRL_FCB
+	#define MAC_Q0_TX_FLOW_CTRL_FCB_OFFSET  0
+	#define MAC_Q0_TX_FLOW_CTRL_FCB_LEN     1
+	#define MAC_Q0_TX_FLOW_CTRL_FCB_DEFAULT 0x0
+	/*[field] TFE*/
+	#define MAC_Q0_TX_FLOW_CTRL_TFE
+	#define MAC_Q0_TX_FLOW_CTRL_TFE_OFFSET  1
+	#define MAC_Q0_TX_FLOW_CTRL_TFE_LEN     1
+	#define MAC_Q0_TX_FLOW_CTRL_TFE_DEFAULT 0x1
+	/*[field] PLT*/
+	#define MAC_Q0_TX_FLOW_CTRL_PLT
+	#define MAC_Q0_TX_FLOW_CTRL_PLT_OFFSET  4
+	#define MAC_Q0_TX_FLOW_CTRL_PLT_LEN     3
+	#define MAC_Q0_TX_FLOW_CTRL_PLT_DEFAULT 0x0
+	/*[field] DAPQ*/
+	#define MAC_Q0_TX_FLOW_CTRL_DAPQ
+	#define MAC_Q0_TX_FLOW_CTRL_DAPQ_OFFSET  7
+	#define MAC_Q0_TX_FLOW_CTRL_DAPQ_LEN     1
+	#define MAC_Q0_TX_FLOW_CTRL_DAPQ_DEFAULT 0x0
+	/*[field] PT*/
+	#define MAC_Q0_TX_FLOW_CTRL_PT
+	#define MAC_Q0_TX_FLOW_CTRL_PT_OFFSET  16
+	#define MAC_Q0_TX_FLOW_CTRL_PT_LEN     16
+	#define MAC_Q0_TX_FLOW_CTRL_PT_DEFAULT 0x0
+
+struct mac_q0_tx_flow_ctrl {
+	a_uint32_t  fcb:1;
+	a_uint32_t  tfe:1;
+	a_uint32_t  _reserved0:2;
+	a_uint32_t  plt:3;
+	a_uint32_t  dapq:1;
+	a_uint32_t  _reserved1:8;
+	a_uint32_t  pt:16;
+};
+
+union mac_q0_tx_flow_ctrl_u {
+	a_uint32_t val;
+	struct mac_q0_tx_flow_ctrl bf;
+};
+
+/*[register] MAC_RX_FLOW_CTRL*/
+#define MAC_RX_FLOW_CTRL
+#define MAC_RX_FLOW_CTRL_ADDRESS 0x90
+#define MAC_RX_FLOW_CTRL_NUM     2
+#define MAC_RX_FLOW_CTRL_INC     0x4000
+#define MAC_RX_FLOW_CTRL_TYPE    REG_TYPE_RW
+#define MAC_RX_FLOW_CTRL_DEFAULT 0x80e
+	/*[field] RFE*/
+	#define MAC_RX_FLOW_CTRL_RFE
+	#define MAC_RX_FLOW_CTRL_RFE_OFFSET  0
+	#define MAC_RX_FLOW_CTRL_RFE_LEN     1
+	#define MAC_RX_FLOW_CTRL_RFE_DEFAULT 0x0
+	/*[field] UP*/
+	#define MAC_RX_FLOW_CTRL_UP
+	#define MAC_RX_FLOW_CTRL_UP_OFFSET  1
+	#define MAC_RX_FLOW_CTRL_UP_LEN     1
+	#define MAC_RX_FLOW_CTRL_UP_DEFAULT 0x7
+	/*[field] PFCE*/
+	#define MAC_RX_FLOW_CTRL_PFCE
+	#define MAC_RX_FLOW_CTRL_PFCE_OFFSET  8
+	#define MAC_RX_FLOW_CTRL_PFCE_LEN     1
+	#define MAC_RX_FLOW_CTRL_PFCE_DEFAULT 0x0
+
+struct mac_rx_flow_ctrl {
+	a_uint32_t  rfe:1;
+	a_uint32_t  up:1;
+	a_uint32_t  _reserved0:6;
+	a_uint32_t  pfce:1;
+	a_uint32_t  _reserved1:23;
+};
+
+union mac_rx_flow_ctrl_u {
+	a_uint32_t val;
+	struct mac_rx_flow_ctrl bf;
+};
+
+/*[register] MAC_INTERRUPT_STATUS*/
+#define MAC_INTERRUPT_STATUS
+#define MAC_INTERRUPT_STATUS_ADDRESS 0xb0
+#define MAC_INTERRUPT_STATUS_NUM     2
+#define MAC_INTERRUPT_STATUS_INC     0x4000
+#define MAC_INTERRUPT_STATUS_TYPE    REG_TYPE_RW
+#define MAC_INTERRUPT_STATUS_DEFAULT 0x0
+	/*[field] SMI*/
+	#define MAC_INTERRUPT_STATUS_SMI
+	#define MAC_INTERRUPT_STATUS_SMI_OFFSET  1
+	#define MAC_INTERRUPT_STATUS_SMI_LEN     1
+	#define MAC_INTERRUPT_STATUS_SMI_DEFAULT 0x0
+	/*[field] PMTIS*/
+	#define MAC_INTERRUPT_STATUS_PMTIS
+	#define MAC_INTERRUPT_STATUS_PMTIS_OFFSET  4
+	#define MAC_INTERRUPT_STATUS_PMTIS_LEN     1
+	#define MAC_INTERRUPT_STATUS_PMTIS_DEFAULT 0x0
+	/*[field] LPIIS*/
+	#define MAC_INTERRUPT_STATUS_LPIIS
+	#define MAC_INTERRUPT_STATUS_LPIIS_OFFSET  5
+	#define MAC_INTERRUPT_STATUS_LPIIS_LEN     1
+	#define MAC_INTERRUPT_STATUS_LPIIS_DEFAULT 0x0
+	/*[field] MMCRXIS*/
+	#define MAC_INTERRUPT_STATUS_MMCRXIS
+	#define MAC_INTERRUPT_STATUS_MMCRXIS_OFFSET  9
+	#define MAC_INTERRUPT_STATUS_MMCRXIS_LEN     1
+	#define MAC_INTERRUPT_STATUS_MMCRXIS_DEFAULT 0x0
+	/*[field] MMCTXIS*/
+	#define MAC_INTERRUPT_STATUS_MMCTXIS
+	#define MAC_INTERRUPT_STATUS_MMCTXIS_OFFSET  10
+	#define MAC_INTERRUPT_STATUS_MMCTXIS_LEN     1
+	#define MAC_INTERRUPT_STATUS_MMCTXIS_DEFAULT 0x0
+	/*[field] TSIS*/
+	#define MAC_INTERRUPT_STATUS_TSIS
+	#define MAC_INTERRUPT_STATUS_TSIS_OFFSET  12
+	#define MAC_INTERRUPT_STATUS_TSIS_LEN     1
+	#define MAC_INTERRUPT_STATUS_TSIS_DEFAULT 0x0
+	/*[field] TXESIS*/
+	#define MAC_INTERRUPT_STATUS_TXESIS
+	#define MAC_INTERRUPT_STATUS_TXESIS_OFFSET  13
+	#define MAC_INTERRUPT_STATUS_TXESIS_LEN     1
+	#define MAC_INTERRUPT_STATUS_TXESIS_DEFAULT 0x0
+	/*[field] RXESIS*/
+	#define MAC_INTERRUPT_STATUS_RXESIS
+	#define MAC_INTERRUPT_STATUS_RXESIS_OFFSET  14
+	#define MAC_INTERRUPT_STATUS_RXESIS_LEN     1
+	#define MAC_INTERRUPT_STATUS_RXESIS_DEFAULT 0x0
+	/*[field] GPIIS*/
+	#define MAC_INTERRUPT_STATUS_GPIIS
+	#define MAC_INTERRUPT_STATUS_GPIIS_OFFSET  15
+	#define MAC_INTERRUPT_STATUS_GPIIS_LEN     1
+	#define MAC_INTERRUPT_STATUS_GPIIS_DEFAULT 0x0
+	/*[field] LS*/
+	#define MAC_INTERRUPT_STATUS_LS
+	#define MAC_INTERRUPT_STATUS_LS_OFFSET  24
+	#define MAC_INTERRUPT_STATUS_LS_LEN     2
+	#define MAC_INTERRUPT_STATUS_LS_DEFAULT 0x0
+
+struct mac_interrupt_status {
+	a_uint32_t  smi:1;
+	a_uint32_t  _reserved0:2;
+	a_uint32_t  pmtis:1;
+	a_uint32_t  lpiis:1;
+	a_uint32_t  _reserved1:3;
+	a_uint32_t  mmcrxis:1;
+	a_uint32_t  mmctxis:1;
+	a_uint32_t  _reserved2:1;
+	a_uint32_t  tsis:1;
+	a_uint32_t  txesis:1;
+	a_uint32_t  rxesis:1;
+	a_uint32_t  gpiis:1;
+	a_uint32_t  _reserved3:8;
+	a_uint32_t  ls:2;
+	a_uint32_t  _reserved4:6;
+};
+
+union mac_interrupt_status_u {
+	a_uint32_t val;
+	struct mac_interrupt_status bf;
+};
+
+/*[register] MAC_INTERRUPT_ENABLE*/
+#define MAC_INTERRUPT_ENABLE
+#define MAC_INTERRUPT_ENABLE_ADDRESS 0xb4
+#define MAC_INTERRUPT_ENABLE_NUM     2
+#define MAC_INTERRUPT_ENABLE_INC     0x4000
+#define MAC_INTERRUPT_ENABLE_TYPE    REG_TYPE_RO
+#define MAC_INTERRUPT_ENABLE_DEFAULT 0x0
+	/*[field] PMTIE*/
+	#define MAC_INTERRUPT_ENABLE_PMTIE
+	#define MAC_INTERRUPT_ENABLE_PMTIE_OFFSET  4
+	#define MAC_INTERRUPT_ENABLE_PMTIE_LEN     1
+	#define MAC_INTERRUPT_ENABLE_PMTIE_DEFAULT 0x0
+	/*[field] LPIIE*/
+	#define MAC_INTERRUPT_ENABLE_LPIIE
+	#define MAC_INTERRUPT_ENABLE_LPIIE_OFFSET  5
+	#define MAC_INTERRUPT_ENABLE_LPIIE_LEN     1
+	#define MAC_INTERRUPT_ENABLE_LPIIE_DEFAULT 0x0
+	/*[field] TSIE*/
+	#define MAC_INTERRUPT_ENABLE_TSIE
+	#define MAC_INTERRUPT_ENABLE_TSIE_OFFSET  12
+	#define MAC_INTERRUPT_ENABLE_TSIE_LEN     1
+	#define MAC_INTERRUPT_ENABLE_TSIE_DEFAULT 0x0
+	/*[field] TXESIE*/
+	#define MAC_INTERRUPT_ENABLE_TXESIE
+	#define MAC_INTERRUPT_ENABLE_TXESIE_OFFSET  13
+	#define MAC_INTERRUPT_ENABLE_TXESIE_LEN     1
+	#define MAC_INTERRUPT_ENABLE_TXESIE_DEFAULT 0x0
+	/*[field] RXESIE*/
+	#define MAC_INTERRUPT_ENABLE_RXESIE
+	#define MAC_INTERRUPT_ENABLE_RXESIE_OFFSET  14
+	#define MAC_INTERRUPT_ENABLE_RXESIE_LEN     1
+	#define MAC_INTERRUPT_ENABLE_RXESIE_DEFAULT 0x0
+
+struct mac_interrupt_enable {
+	a_uint32_t  pmtie:1;
+	a_uint32_t  lpiie:1;
+	a_uint32_t  _reserved0:6;
+	a_uint32_t  tsie:1;
+	a_uint32_t  txesie:1;
+	a_uint32_t  rxesie:1;
+	a_uint32_t  _reserved1:17;
+};
+
+union mac_interrupt_enable_u {
+	a_uint32_t val;
+	struct mac_interrupt_enable bf;
+};
+
+/*[register] MAC_RX_TX_STATUS*/
+#define MAC_RX_TX_STATUS
+#define MAC_RX_TX_STATUS_ADDRESS 0xb8
+#define MAC_RX_TX_STATUS_NUM     2
+#define MAC_RX_TX_STATUS_INC     0x4000
+#define MAC_RX_TX_STATUS_TYPE    REG_TYPE_RW
+#define MAC_RX_TX_STATUS_DEFAULT 0x0
+	/*[field] TJT*/
+	#define MAC_RX_TX_STATUS_TJT
+	#define MAC_RX_TX_STATUS_TJT_OFFSET  0
+	#define MAC_RX_TX_STATUS_TJT_LEN     1
+	#define MAC_RX_TX_STATUS_TJT_DEFAULT 0x0
+	/*[field] RWT*/
+	#define MAC_RX_TX_STATUS_RWT
+	#define MAC_RX_TX_STATUS_RWT_OFFSET  8
+	#define MAC_RX_TX_STATUS_RWT_LEN     1
+	#define MAC_RX_TX_STATUS_RWT_DEFAULT 0x0
+
+struct mac_rx_tx_status {
+	a_uint32_t  tjt:1;
+	a_uint32_t  _reserved0:7;
+	a_uint32_t  rwt:1;
+	a_uint32_t  _reserved1:23;
+};
+
+union mac_rx_tx_status_u {
+	a_uint32_t val;
+	struct mac_rx_tx_status bf;
+};
+
+/*[register] MAC_LPI_CONTROL_STATUS*/
+#define MAC_LPI_CONTROL_STATUS
+#define MAC_LPI_CONTROL_STATUS_ADDRESS 0xd0
+#define MAC_LPI_CONTROL_STATUS_NUM     2
+#define MAC_LPI_CONTROL_STATUS_INC     0x4000
+#define MAC_LPI_CONTROL_STATUS_TYPE    REG_TYPE_RW
+#define MAC_LPI_CONTROL_STATUS_DEFAULT 0x0
+	/*[field] TLPIEN*/
+	#define MAC_LPI_CONTROL_STATUS_TLPIEN
+	#define MAC_LPI_CONTROL_STATUS_TLPIEN_OFFSET  0
+	#define MAC_LPI_CONTROL_STATUS_TLPIEN_LEN     1
+	#define MAC_LPI_CONTROL_STATUS_TLPIEN_DEFAULT 0x0
+	/*[field] TLPIEX*/
+	#define MAC_LPI_CONTROL_STATUS_TLPIEX
+	#define MAC_LPI_CONTROL_STATUS_TLPIEX_OFFSET  1
+	#define MAC_LPI_CONTROL_STATUS_TLPIEX_LEN     1
+	#define MAC_LPI_CONTROL_STATUS_TLPIEX_DEFAULT 0x0
+	/*[field] RLPIEN*/
+	#define MAC_LPI_CONTROL_STATUS_RLPIEN
+	#define MAC_LPI_CONTROL_STATUS_RLPIEN_OFFSET  2
+	#define MAC_LPI_CONTROL_STATUS_RLPIEN_LEN     1
+	#define MAC_LPI_CONTROL_STATUS_RLPIEN_DEFAULT 0x0
+	/*[field] RLPIEX*/
+	#define MAC_LPI_CONTROL_STATUS_RLPIEX
+	#define MAC_LPI_CONTROL_STATUS_RLPIEX_OFFSET  3
+	#define MAC_LPI_CONTROL_STATUS_RLPIEX_LEN     1
+	#define MAC_LPI_CONTROL_STATUS_RLPIEX_DEFAULT 0x0
+	/*[field] TLPIST*/
+	#define MAC_LPI_CONTROL_STATUS_TLPIST
+	#define MAC_LPI_CONTROL_STATUS_TLPIST_OFFSET  8
+	#define MAC_LPI_CONTROL_STATUS_TLPIST_LEN     1
+	#define MAC_LPI_CONTROL_STATUS_TLPIST_DEFAULT 0x0
+	/*[field] RLPIST*/
+	#define MAC_LPI_CONTROL_STATUS_RLPIST
+	#define MAC_LPI_CONTROL_STATUS_RLPIST_OFFSET  9
+	#define MAC_LPI_CONTROL_STATUS_RLPIST_LEN     1
+	#define MAC_LPI_CONTROL_STATUS_RLPIST_DEFAULT 0x0
+	/*[field] RXRSTP*/
+	#define MAC_LPI_CONTROL_STATUS_RXRSTP
+	#define MAC_LPI_CONTROL_STATUS_RXRSTP_OFFSET  10
+	#define MAC_LPI_CONTROL_STATUS_RXRSTP_LEN     1
+	#define MAC_LPI_CONTROL_STATUS_RXRSTP_DEFAULT 0x0
+	/*[field] TXRSTP*/
+	#define MAC_LPI_CONTROL_STATUS_TXRSTP
+	#define MAC_LPI_CONTROL_STATUS_TXRSTP_OFFSET  11
+	#define MAC_LPI_CONTROL_STATUS_TXRSTP_LEN     1
+	#define MAC_LPI_CONTROL_STATUS_TXRSTP_DEFAULT 0x0
+	/*[field] LPITXEN*/
+	#define MAC_LPI_CONTROL_STATUS_LPITXEN
+	#define MAC_LPI_CONTROL_STATUS_LPITXEN_OFFSET  16
+	#define MAC_LPI_CONTROL_STATUS_LPITXEN_LEN     1
+	#define MAC_LPI_CONTROL_STATUS_LPITXEN_DEFAULT 0x0
+	/*[field] PLS*/
+	#define MAC_LPI_CONTROL_STATUS_PLS
+	#define MAC_LPI_CONTROL_STATUS_PLS_OFFSET  17
+	#define MAC_LPI_CONTROL_STATUS_PLS_LEN     1
+	#define MAC_LPI_CONTROL_STATUS_PLS_DEFAULT 0x0
+	/*[field] PLSDIS*/
+	#define MAC_LPI_CONTROL_STATUS_PLSDIS
+	#define MAC_LPI_CONTROL_STATUS_PLSDIS_OFFSET  18
+	#define MAC_LPI_CONTROL_STATUS_PLSDIS_LEN     1
+	#define MAC_LPI_CONTROL_STATUS_PLSDIS_DEFAULT 0x0
+	/*[field] LPITXA*/
+	#define MAC_LPI_CONTROL_STATUS_LPITXA
+	#define MAC_LPI_CONTROL_STATUS_LPITXA_OFFSET  19
+	#define MAC_LPI_CONTROL_STATUS_LPITXA_LEN     1
+	#define MAC_LPI_CONTROL_STATUS_LPITXA_DEFAULT 0x0
+	/*[field] LPITE*/
+	#define MAC_LPI_CONTROL_STATUS_LPITE
+	#define MAC_LPI_CONTROL_STATUS_LPITE_OFFSET  20
+	#define MAC_LPI_CONTROL_STATUS_LPITE_LEN     1
+	#define MAC_LPI_CONTROL_STATUS_LPITE_DEFAULT 0x0
+	/*[field] LPITCSE*/
+	#define MAC_LPI_CONTROL_STATUS_LPITCSE
+	#define MAC_LPI_CONTROL_STATUS_LPITCSE_OFFSET  21
+	#define MAC_LPI_CONTROL_STATUS_LPITCSE_LEN     1
+	#define MAC_LPI_CONTROL_STATUS_LPITCSE_DEFAULT 0x0
+
+struct mac_lpi_control_status {
+	a_uint32_t  tlpien:1;
+	a_uint32_t  tlpiex:1;
+	a_uint32_t  rlpien:1;
+	a_uint32_t  rlpiex:1;
+	a_uint32_t  _reserved0:4;
+	a_uint32_t  tlpist:1;
+	a_uint32_t  rlpist:1;
+	a_uint32_t  rxrstp:1;
+	a_uint32_t  txrstp:1;
+	a_uint32_t  _reserved1:4;
+	a_uint32_t  lpitxen:1;
+	a_uint32_t  pls:1;
+	a_uint32_t  plsdis:1;
+	a_uint32_t  lpitxa:1;
+	a_uint32_t  lpite:1;
+	a_uint32_t  lpitcse:1;
+	a_uint32_t  _reserved2:10;
+};
+
+union mac_lpi_control_status_u {
+	a_uint32_t val;
+	struct mac_lpi_control_status bf;
+};
+
+/*[register] MAC_LPI_TIMERS_CONTROL*/
+#define MAC_LPI_TIMERS_CONTROL
+#define MAC_LPI_TIMERS_CONTROL_ADDRESS 0xd4
+#define MAC_LPI_TIMERS_CONTROL_NUM     2
+#define MAC_LPI_TIMERS_CONTROL_INC     0x4000
+#define MAC_LPI_TIMERS_CONTROL_TYPE    REG_TYPE_RO
+#define MAC_LPI_TIMERS_CONTROL_DEFAULT 0x0
+	/*[field] TWT*/
+	#define MAC_LPI_TIMERS_CONTROL_TWT
+	#define MAC_LPI_TIMERS_CONTROL_TWT_OFFSET  0
+	#define MAC_LPI_TIMERS_CONTROL_TWT_LEN     16
+	#define MAC_LPI_TIMERS_CONTROL_TWT_DEFAULT 0x0
+	/*[field] LST*/
+	#define MAC_LPI_TIMERS_CONTROL_LST
+	#define MAC_LPI_TIMERS_CONTROL_LST_OFFSET  16
+	#define MAC_LPI_TIMERS_CONTROL_LST_LEN     10
+	#define MAC_LPI_TIMERS_CONTROL_LST_DEFAULT 0x0
+
+struct mac_lpi_timers_control {
+	a_uint32_t  twt:16;
+	a_uint32_t  lst:10;
+	a_uint32_t  _reserved0:6;
+};
+
+union mac_lpi_timers_control_u {
+	a_uint32_t val;
+	struct mac_lpi_timers_control bf;
+};
+
+/*[register] MAC_LPI_AUTO_ENTRY_TIMER*/
+#define MAC_LPI_AUTO_ENTRY_TIMER
+#define MAC_LPI_AUTO_ENTRY_TIMER_ADDRESS 0xd8
+#define MAC_LPI_AUTO_ENTRY_TIMER_NUM     2
+#define MAC_LPI_AUTO_ENTRY_TIMER_INC     0x4000
+#define MAC_LPI_AUTO_ENTRY_TIMER_TYPE    REG_TYPE_RO
+#define MAC_LPI_AUTO_ENTRY_TIMER_DEFAULT 0x0
+	/*[field] LPIET*/
+	#define MAC_LPI_AUTO_ENTRY_TIMER_LPIET
+	#define MAC_LPI_AUTO_ENTRY_TIMER_LPIET_OFFSET  3
+	#define MAC_LPI_AUTO_ENTRY_TIMER_LPIET_LEN     17
+	#define MAC_LPI_AUTO_ENTRY_TIMER_LPIET_DEFAULT 0x0
+
+struct mac_lpi_auto_entry_timer {
+	a_uint32_t  lpiet:17;
+	a_uint32_t  _reserved0:12;
+};
+
+union mac_lpi_auto_entry_timer_u {
+	a_uint32_t val;
+	struct mac_lpi_auto_entry_timer bf;
+};
+
+/*[register] MAC_1US_TIC_COUNTER*/
+#define MAC_1US_TIC_COUNTER
+#define MAC_1US_TIC_COUNTER_ADDRESS 0xdc
+#define MAC_1US_TIC_COUNTER_NUM     2
+#define MAC_1US_TIC_COUNTER_INC     0x4000
+#define MAC_1US_TIC_COUNTER_TYPE    REG_TYPE_RO
+#define MAC_1US_TIC_COUNTER_DEFAULT 0x0
+	/*[field] TIC_1US_CNTR*/
+	#define MAC_1US_TIC_COUNTER_TIC_1US_CNTR
+	#define MAC_1US_TIC_COUNTER_TIC_1US_CNTR_OFFSET  0
+	#define MAC_1US_TIC_COUNTER_TIC_1US_CNTR_LEN     12
+	#define MAC_1US_TIC_COUNTER_TIC_1US_CNTR_DEFAULT 0x0
+
+struct mac_1us_tic_counter {
+	a_uint32_t  tic_1us_cntr:12;
+	a_uint32_t  _reserved0:20;
+};
+
+union mac_1us_tic_counter_u {
+	a_uint32_t val;
+	struct mac_1us_tic_counter bf;
+};
+
+/*[register] MAC_ADDRESS0_HIGH*/
+#define MAC_ADDRESS0_HIGH
+#define MAC_ADDRESS0_HIGH_ADDRESS 0x300
+#define MAC_ADDRESS0_HIGH_NUM     2
+#define MAC_ADDRESS0_HIGH_INC     0x4000
+#define MAC_ADDRESS0_HIGH_TYPE    REG_TYPE_RO
+#define MAC_ADDRESS0_HIGH_DEFAULT 0x0
+	/*[field] ADDRHI*/
+	#define MAC_ADDRESS0_HIGH_ADDRHI
+	#define MAC_ADDRESS0_HIGH_ADDRHI_OFFSET  0
+	#define MAC_ADDRESS0_HIGH_ADDRHI_LEN     16
+	#define MAC_ADDRESS0_HIGH_ADDRHI_DEFAULT 0x0
+	/*[field] DCS*/
+	#define MAC_ADDRESS0_HIGH_DCS
+	#define MAC_ADDRESS0_HIGH_DCS_OFFSET  16
+	#define MAC_ADDRESS0_HIGH_DCS_LEN     1
+	#define MAC_ADDRESS0_HIGH_DCS_DEFAULT 0x0
+	/*[field] AE*/
+	#define MAC_ADDRESS0_HIGH_AE
+	#define MAC_ADDRESS0_HIGH_AE_OFFSET  31
+	#define MAC_ADDRESS0_HIGH_AE_LEN     1
+	#define MAC_ADDRESS0_HIGH_AE_DEFAULT 0x0
+
+struct mac_address0_high {
+	a_uint32_t  addrhi:16;
+	a_uint32_t  dcs:1;
+	a_uint32_t  _reserved0:14;
+	a_uint32_t  ae:1;
+};
+
+union mac_address0_high_u {
+	a_uint32_t val;
+	struct mac_address0_high bf;
+};
+
+/*[register] MAC_ADDRESS0_LOW*/
+#define MAC_ADDRESS0_LOW
+#define MAC_ADDRESS0_LOW_ADDRESS 0x304
+#define MAC_ADDRESS0_LOW_NUM     2
+#define MAC_ADDRESS0_LOW_INC     0x4000
+#define MAC_ADDRESS0_LOW_TYPE    REG_TYPE_RO
+#define MAC_ADDRESS0_LOW_DEFAULT 0x0
+	/*[field] ADDRLO*/
+	#define MAC_ADDRESS0_LOW_ADDRLO
+	#define MAC_ADDRESS0_LOW_ADDRLO_OFFSET  0
+	#define MAC_ADDRESS0_LOW_ADDRLO_LEN     32
+	#define MAC_ADDRESS0_LOW_ADDRLO_DEFAULT 0x0
+
+struct mac_address0_low {
+	a_uint32_t  addrlo:32;
+};
+
+union mac_address0_low_u {
+	a_uint32_t val;
+	struct mac_address0_low bf;
+};
+
+/*[register] MMC_RECEIVE_INTERRUPT*/
+#define MMC_RECEIVE_INTERRUPT
+#define MMC_RECEIVE_INTERRUPT_ADDRESS 0x804
+#define MMC_RECEIVE_INTERRUPT_NUM     2
+#define MMC_RECEIVE_INTERRUPT_INC     0x4000
+#define MMC_RECEIVE_INTERRUPT_TYPE    REG_TYPE_RO
+#define MMC_RECEIVE_INTERRUPT_DEFAULT 0x0
+	/*[field] RXGBFRMIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXGBFRMIS
+	#define MMC_RECEIVE_INTERRUPT_RXGBFRMIS_OFFSET  0
+	#define MMC_RECEIVE_INTERRUPT_RXGBFRMIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXGBFRMIS_DEFAULT 0x0
+	/*[field] RXGBOCTIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXGBOCTIS
+	#define MMC_RECEIVE_INTERRUPT_RXGBOCTIS_OFFSET  1
+	#define MMC_RECEIVE_INTERRUPT_RXGBOCTIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXGBOCTIS_DEFAULT 0x0
+	/*[field] RXGOCTIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXGOCTIS
+	#define MMC_RECEIVE_INTERRUPT_RXGOCTIS_OFFSET  2
+	#define MMC_RECEIVE_INTERRUPT_RXGOCTIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXGOCTIS_DEFAULT 0x0
+	/*[field] RXBCGFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXBCGFIS
+	#define MMC_RECEIVE_INTERRUPT_RXBCGFIS_OFFSET  3
+	#define MMC_RECEIVE_INTERRUPT_RXBCGFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXBCGFIS_DEFAULT 0x0
+	/*[field] RXMCGFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXMCGFIS
+	#define MMC_RECEIVE_INTERRUPT_RXMCGFIS_OFFSET  4
+	#define MMC_RECEIVE_INTERRUPT_RXMCGFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXMCGFIS_DEFAULT 0x0
+	/*[field] RXCRCERFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXCRCERFIS
+	#define MMC_RECEIVE_INTERRUPT_RXCRCERFIS_OFFSET  5
+	#define MMC_RECEIVE_INTERRUPT_RXCRCERFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXCRCERFIS_DEFAULT 0x0
+	/*[field] RXRUNTFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXRUNTFIS
+	#define MMC_RECEIVE_INTERRUPT_RXRUNTFIS_OFFSET  6
+	#define MMC_RECEIVE_INTERRUPT_RXRUNTFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXRUNTFIS_DEFAULT 0x0
+	/*[field] RXJABERFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXJABERFIS
+	#define MMC_RECEIVE_INTERRUPT_RXJABERFIS_OFFSET  7
+	#define MMC_RECEIVE_INTERRUPT_RXJABERFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXJABERFIS_DEFAULT 0x0
+	/*[field] RXUSIZEGFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS
+	#define MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_OFFSET  8
+	#define MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_DEFAULT 0x0
+	/*[field] RXOSIZEGFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS
+	#define MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_OFFSET  9
+	#define MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_DEFAULT 0x0
+	/*[field] RX64OCTGBFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS
+	#define MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_OFFSET  10
+	#define MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_DEFAULT 0x0
+	/*[field] RX65T127OCTGBFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS
+	#define MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_OFFSET  11
+	#define MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_DEFAULT 0x0
+	/*[field] RX128T255OCTGBFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS
+	#define MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_OFFSET  12
+	#define MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_DEFAULT 0x0
+	/*[field] RX256T511OCTGBFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS
+	#define MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_OFFSET  13
+	#define MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_DEFAULT 0x0
+	/*[field] RX512T1023OCTGBFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS
+	#define MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_OFFSET  14
+	#define MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_DEFAULT 0x0
+	/*[field] RX1024TMAXOCTGBFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS
+	#define MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_OFFSET  15
+	#define MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_DEFAULT 0x0
+	/*[field] RXUCGFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXUCGFIS
+	#define MMC_RECEIVE_INTERRUPT_RXUCGFIS_OFFSET  16
+	#define MMC_RECEIVE_INTERRUPT_RXUCGFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXUCGFIS_DEFAULT 0x0
+	/*[field] RXLENERFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXLENERFIS
+	#define MMC_RECEIVE_INTERRUPT_RXLENERFIS_OFFSET  17
+	#define MMC_RECEIVE_INTERRUPT_RXLENERFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXLENERFIS_DEFAULT 0x0
+	/*[field] RXORANGEFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXORANGEFIS
+	#define MMC_RECEIVE_INTERRUPT_RXORANGEFIS_OFFSET  18
+	#define MMC_RECEIVE_INTERRUPT_RXORANGEFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXORANGEFIS_DEFAULT 0x0
+	/*[field] RXPAUSFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXPAUSFIS
+	#define MMC_RECEIVE_INTERRUPT_RXPAUSFIS_OFFSET  19
+	#define MMC_RECEIVE_INTERRUPT_RXPAUSFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXPAUSFIS_DEFAULT 0x0
+	/*[field] RXFOVFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXFOVFIS
+	#define MMC_RECEIVE_INTERRUPT_RXFOVFIS_OFFSET  20
+	#define MMC_RECEIVE_INTERRUPT_RXFOVFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXFOVFIS_DEFAULT 0x0
+	/*[field] RXVLANGBFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXVLANGBFIS
+	#define MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_OFFSET  21
+	#define MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_DEFAULT 0x0
+	/*[field] RXWDOGFIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXWDOGFIS
+	#define MMC_RECEIVE_INTERRUPT_RXWDOGFIS_OFFSET  22
+	#define MMC_RECEIVE_INTERRUPT_RXWDOGFIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXWDOGFIS_DEFAULT 0x0
+	/*[field] RXDISFCGBIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXDISFCGBIS
+	#define MMC_RECEIVE_INTERRUPT_RXDISFCGBIS_OFFSET  23
+	#define MMC_RECEIVE_INTERRUPT_RXDISFCGBIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXDISFCGBIS_DEFAULT 0x0
+	/*[field] RXDISOCGBIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXDISOCGBIS
+	#define MMC_RECEIVE_INTERRUPT_RXDISOCGBIS_OFFSET  24
+	#define MMC_RECEIVE_INTERRUPT_RXDISOCGBIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXDISOCGBIS_DEFAULT 0x0
+	/*[field] RXLPIUSCIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXLPIUSCIS
+	#define MMC_RECEIVE_INTERRUPT_RXLPIUSCIS_OFFSET  25
+	#define MMC_RECEIVE_INTERRUPT_RXLPIUSCIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXLPIUSCIS_DEFAULT 0x0
+	/*[field] RXLPITRCIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXLPITRCIS
+	#define MMC_RECEIVE_INTERRUPT_RXLPITRCIS_OFFSET  26
+	#define MMC_RECEIVE_INTERRUPT_RXLPITRCIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXLPITRCIS_DEFAULT 0x0
+	/*[field] RXPRMMCIS*/
+	#define MMC_RECEIVE_INTERRUPT_RXPRMMCIS
+	#define MMC_RECEIVE_INTERRUPT_RXPRMMCIS_OFFSET  31
+	#define MMC_RECEIVE_INTERRUPT_RXPRMMCIS_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_RXPRMMCIS_DEFAULT 0x0
+
+struct mmc_receive_interrupt {
+	a_uint32_t  rxgbfrmis:1;
+	a_uint32_t  rxgboctis:1;
+	a_uint32_t  rxgoctis:1;
+	a_uint32_t  rxbcgfis:1;
+	a_uint32_t  rxmcgfis:1;
+	a_uint32_t  rxcrcerfis:1;
+	a_uint32_t  rxruntfis:1;
+	a_uint32_t  rxjaberfis:1;
+	a_uint32_t  rxusizegfis:1;
+	a_uint32_t  rxosizegfis:1;
+	a_uint32_t  rx64octgbfis:1;
+	a_uint32_t  rx65t127octgbfis:1;
+	a_uint32_t  rx128t255octgbfis:1;
+	a_uint32_t  rx256t511octgbfis:1;
+	a_uint32_t  rx512t1023octgbfis:1;
+	a_uint32_t  rx1024tmaxoctgbfis:1;
+	a_uint32_t  rxucgfis:1;
+	a_uint32_t  rxlenerfis:1;
+	a_uint32_t  rxorangefis:1;
+	a_uint32_t  rxpausfis:1;
+	a_uint32_t  rxfovfis:1;
+	a_uint32_t  rxvlangbfis:1;
+	a_uint32_t  rxwdogfis:1;
+	a_uint32_t  rxdisfcgbis:1;
+	a_uint32_t  rxdisocgbis:1;
+	a_uint32_t  rxlpiuscis:1;
+	a_uint32_t  rxlpitrcis:1;
+	a_uint32_t  _reserved0:4;
+	a_uint32_t  rxprmmcis:1;
+};
+
+union mmc_receive_interrupt_u {
+	a_uint32_t val;
+	struct mmc_receive_interrupt bf;
+};
+
+/*[register] MMC_TRANSMIT_INTERRUPT*/
+#define MMC_TRANSMIT_INTERRUPT
+#define MMC_TRANSMIT_INTERRUPT_ADDRESS 0x808
+#define MMC_TRANSMIT_INTERRUPT_NUM     2
+#define MMC_TRANSMIT_INTERRUPT_INC     0x4000
+#define MMC_TRANSMIT_INTERRUPT_TYPE    REG_TYPE_RO
+#define MMC_TRANSMIT_INTERRUPT_DEFAULT 0x0
+	/*[field] TXGBOCTIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TXGBOCTIS
+	#define MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_OFFSET  0
+	#define MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_DEFAULT 0x0
+	/*[field] TXGBFRMIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TXGBFRMIS
+	#define MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_OFFSET  1
+	#define MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_DEFAULT 0x0
+	/*[field] TXBCGFIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TXBCGFIS
+	#define MMC_TRANSMIT_INTERRUPT_TXBCGFIS_OFFSET  2
+	#define MMC_TRANSMIT_INTERRUPT_TXBCGFIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TXBCGFIS_DEFAULT 0x0
+	/*[field] TXMCGFIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TXMCGFIS
+	#define MMC_TRANSMIT_INTERRUPT_TXMCGFIS_OFFSET  3
+	#define MMC_TRANSMIT_INTERRUPT_TXMCGFIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TXMCGFIS_DEFAULT 0x0
+	/*[field] TX64OCTGBFIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS
+	#define MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_OFFSET  4
+	#define MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_DEFAULT 0x0
+	/*[field] TX65T127OCTGBFIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS
+	#define MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_OFFSET  5
+	#define MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_DEFAULT 0x0
+	/*[field] TX128T255OCTGBFIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS
+	#define MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_OFFSET  6
+	#define MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_DEFAULT 0x0
+	/*[field] TX256T511OCTGBFIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS
+	#define MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_OFFSET  7
+	#define MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_DEFAULT 0x0
+	/*[field] TX512T1023OCTGBFIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS
+	#define MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_OFFSET  8
+	#define MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_DEFAULT 0x0
+	/*[field] TX1024TMAXOCTGBFIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS
+	#define MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_OFFSET  9
+	#define MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_DEFAULT 0x0
+	/*[field] TXUCGBFIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TXUCGBFIS
+	#define MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_OFFSET  10
+	#define MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_DEFAULT 0x0
+	/*[field] TXMCGBFIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TXMCGBFIS
+	#define MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_OFFSET  11
+	#define MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_DEFAULT 0x0
+	/*[field] TXBCGBFIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TXBCGBFIS
+	#define MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_OFFSET  12
+	#define MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_DEFAULT 0x0
+	/*[field] TXUFLOWERFIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS
+	#define MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_OFFSET  13
+	#define MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_DEFAULT 0x0
+	/*[field] TXGOCTIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TXGOCTIS
+	#define MMC_TRANSMIT_INTERRUPT_TXGOCTIS_OFFSET  14
+	#define MMC_TRANSMIT_INTERRUPT_TXGOCTIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TXGOCTIS_DEFAULT 0x0
+	/*[field] TXGFRMIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TXGFRMIS
+	#define MMC_TRANSMIT_INTERRUPT_TXGFRMIS_OFFSET  15
+	#define MMC_TRANSMIT_INTERRUPT_TXGFRMIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TXGFRMIS_DEFAULT 0x0
+	/*[field] TXPAUSFIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TXPAUSFIS
+	#define MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_OFFSET  16
+	#define MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_DEFAULT 0x0
+	/*[field] TXVLANGFIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TXVLANGFIS
+	#define MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_OFFSET  17
+	#define MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_DEFAULT 0x0
+	/*[field] TXLPIUSCIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TXLPIUSCIS
+	#define MMC_TRANSMIT_INTERRUPT_TXLPIUSCIS_OFFSET  18
+	#define MMC_TRANSMIT_INTERRUPT_TXLPIUSCIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TXLPIUSCIS_DEFAULT 0x0
+	/*[field] TXLPITRCIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TXLPITRCIS
+	#define MMC_TRANSMIT_INTERRUPT_TXLPITRCIS_OFFSET  19
+	#define MMC_TRANSMIT_INTERRUPT_TXLPITRCIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TXLPITRCIS_DEFAULT 0x0
+	/*[field] TXPRMMCIS*/
+	#define MMC_TRANSMIT_INTERRUPT_TXPRMMCIS
+	#define MMC_TRANSMIT_INTERRUPT_TXPRMMCIS_OFFSET  31
+	#define MMC_TRANSMIT_INTERRUPT_TXPRMMCIS_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_TXPRMMCIS_DEFAULT 0x0
+
+struct mmc_transmit_interrupt {
+	a_uint32_t  txgboctis:1;
+	a_uint32_t  txgbfrmis:1;
+	a_uint32_t  txbcgfis:1;
+	a_uint32_t  txmcgfis:1;
+	a_uint32_t  tx64octgbfis:1;
+	a_uint32_t  tx65t127octgbfis:1;
+	a_uint32_t  tx128t255octgbfis:1;
+	a_uint32_t  tx256t511octgbfis:1;
+	a_uint32_t  tx512t1023octgbfis:1;
+	a_uint32_t  tx1024tmaxoctgbfis:1;
+	a_uint32_t  txucgbfis:1;
+	a_uint32_t  txmcgbfis:1;
+	a_uint32_t  txbcgbfis:1;
+	a_uint32_t  txuflowerfis:1;
+	a_uint32_t  txgoctis:1;
+	a_uint32_t  txgfrmis:1;
+	a_uint32_t  txpausfis:1;
+	a_uint32_t  txvlangfis:1;
+	a_uint32_t  txlpiuscis:1;
+	a_uint32_t  txlpitrcis:1;
+	a_uint32_t  _reserved0:11;
+	a_uint32_t  txprmmcis:1;
+};
+
+union mmc_transmit_interrupt_u {
+	a_uint32_t val;
+	struct mmc_transmit_interrupt bf;
+};
+
+/*[register] MMC_RECEIVE_INTERRUPT_ENABLE*/
+#define MMC_RECEIVE_INTERRUPT_ENABLE
+#define MMC_RECEIVE_INTERRUPT_ENABLE_ADDRESS 0x80c
+#define MMC_RECEIVE_INTERRUPT_ENABLE_NUM     2
+#define MMC_RECEIVE_INTERRUPT_ENABLE_INC     0x4000
+#define MMC_RECEIVE_INTERRUPT_ENABLE_TYPE    REG_TYPE_RO
+#define MMC_RECEIVE_INTERRUPT_ENABLE_DEFAULT 0x0
+	/*[field] RXGBFRMIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBFRMIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBFRMIE_OFFSET  0
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBFRMIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBFRMIE_DEFAULT 0x0
+	/*[field] RXGBOCTIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBOCTIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBOCTIE_OFFSET  1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBOCTIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBOCTIE_DEFAULT 0x0
+	/*[field] RXGOCTIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXGOCTIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXGOCTIE_OFFSET  2
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXGOCTIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXGOCTIE_DEFAULT 0x0
+	/*[field] RXBCGFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXBCGFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXBCGFIE_OFFSET  3
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXBCGFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXBCGFIE_DEFAULT 0x0
+	/*[field] RXMCGFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXMCGFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXMCGFIE_OFFSET  4
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXMCGFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXMCGFIE_DEFAULT 0x0
+	/*[field] RXCRCERFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXCRCERFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXCRCERFIE_OFFSET  5
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXCRCERFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXCRCERFIE_DEFAULT 0x0
+	/*[field] RXRUNTFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXRUNTFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXRUNTFIE_OFFSET  6
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXRUNTFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXRUNTFIE_DEFAULT 0x0
+	/*[field] RXJABERFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXJABERFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXJABERFIE_OFFSET  7
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXJABERFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXJABERFIE_DEFAULT 0x0
+	/*[field] RXUSIZEGFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXUSIZEGFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXUSIZEGFIE_OFFSET  8
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXUSIZEGFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXUSIZEGFIE_DEFAULT 0x0
+	/*[field] RXOSIZEGFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXOSIZEGFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXOSIZEGFIE_OFFSET  9
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXOSIZEGFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXOSIZEGFIE_DEFAULT 0x0
+	/*[field] RX64OCTGBFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX64OCTGBFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX64OCTGBFIE_OFFSET  10
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX64OCTGBFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX64OCTGBFIE_DEFAULT 0x0
+	/*[field] RX65T127OCTGBFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX65T127OCTGBFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX65T127OCTGBFIE_OFFSET  11
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX65T127OCTGBFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX65T127OCTGBFIE_DEFAULT 0x0
+	/*[field] RX128T255OCTGBFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX128T255OCTGBFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX128T255OCTGBFIE_OFFSET  12
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX128T255OCTGBFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX128T255OCTGBFIE_DEFAULT 0x0
+	/*[field] RX256T511OCTGBFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX256T511OCTGBFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX256T511OCTGBFIE_OFFSET  13
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX256T511OCTGBFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX256T511OCTGBFIE_DEFAULT 0x0
+	/*[field] RX512T1023OCTGBFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX512T1023OCTGBFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX512T1023OCTGBFIE_OFFSET  14
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX512T1023OCTGBFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX512T1023OCTGBFIE_DEFAULT 0x0
+	/*[field] RX1024TMAXOCTGBFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX1024TMAXOCTGBFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX1024TMAXOCTGBFIE_OFFSET  15
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX1024TMAXOCTGBFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RX1024TMAXOCTGBFIE_DEFAULT 0x0
+	/*[field] RXUCGFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXUCGFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXUCGFIE_OFFSET  16
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXUCGFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXUCGFIE_DEFAULT 0x0
+	/*[field] RXLENERFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXLENERFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXLENERFIE_OFFSET  17
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXLENERFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXLENERFIE_DEFAULT 0x0
+	/*[field] RXORANGEFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXORANGEFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXORANGEFIE_OFFSET  18
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXORANGEFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXORANGEFIE_DEFAULT 0x0
+	/*[field] RXPAUSFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXPAUSFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXPAUSFIE_OFFSET  19
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXPAUSFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXPAUSFIE_DEFAULT 0x0
+	/*[field] RXFOVFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXFOVFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXFOVFIE_OFFSET  20
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXFOVFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXFOVFIE_DEFAULT 0x0
+	/*[field] RXVLANGBFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXVLANGBFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXVLANGBFIE_OFFSET  21
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXVLANGBFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXVLANGBFIE_DEFAULT 0x0
+	/*[field] RXWDOGFIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXWDOGFIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXWDOGFIE_OFFSET  22
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXWDOGFIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXWDOGFIE_DEFAULT 0x0
+	/*[field] RXDISFCIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISFCIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISFCIE_OFFSET  23
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISFCIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISFCIE_DEFAULT 0x0
+	/*[field] RXDISOCIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISOCIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISOCIE_OFFSET  24
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISOCIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISOCIE_DEFAULT 0x0
+	/*[field] RXLPIUSCIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPIUSCIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPIUSCIE_OFFSET  25
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPIUSCIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPIUSCIE_DEFAULT 0x0
+	/*[field] RXLPITRCIE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPITRCIE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPITRCIE_OFFSET  26
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPITRCIE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPITRCIE_DEFAULT 0x0
+	/*[field] RXPRMMCISE*/
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXPRMMCISE
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXPRMMCISE_OFFSET  31
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXPRMMCISE_LEN     1
+	#define MMC_RECEIVE_INTERRUPT_ENABLE_RXPRMMCISE_DEFAULT 0x0
+
+struct mmc_receive_interrupt_enable {
+	a_uint32_t  rxgbfrmie:1;
+	a_uint32_t  rxgboctie:1;
+	a_uint32_t  rxgoctie:1;
+	a_uint32_t  rxbcgfie:1;
+	a_uint32_t  rxmcgfie:1;
+	a_uint32_t  rxcrcerfie:1;
+	a_uint32_t  rxruntfie:1;
+	a_uint32_t  rxjaberfie:1;
+	a_uint32_t  rxusizegfie:1;
+	a_uint32_t  rxosizegfie:1;
+	a_uint32_t  rx64octgbfie:1;
+	a_uint32_t  rx65t127octgbfie:1;
+	a_uint32_t  rx128t255octgbfie:1;
+	a_uint32_t  rx256t511octgbfie:1;
+	a_uint32_t  rx512t1023octgbfie:1;
+	a_uint32_t  rx1024tmaxoctgbfie:1;
+	a_uint32_t  rxucgfie:1;
+	a_uint32_t  rxlenerfie:1;
+	a_uint32_t  rxorangefie:1;
+	a_uint32_t  rxpausfie:1;
+	a_uint32_t  rxfovfie:1;
+	a_uint32_t  rxvlangbfie:1;
+	a_uint32_t  rxwdogfie:1;
+	a_uint32_t  rxdisfcie:1;
+	a_uint32_t  rxdisocie:1;
+	a_uint32_t  rxlpiuscie:1;
+	a_uint32_t  rxlpitrcie:1;
+	a_uint32_t  _reserved0:4;
+	a_uint32_t  rxprmmcise:1;
+};
+
+union mmc_receive_interrupt_enable_u {
+	a_uint32_t val;
+	struct mmc_receive_interrupt_enable bf;
+};
+
+/*[register] MMC_TRANSMIT_INTERRUPT_ENABLE*/
+#define MMC_TRANSMIT_INTERRUPT_ENABLE
+#define MMC_TRANSMIT_INTERRUPT_ENABLE_ADDRESS 0x810
+#define MMC_TRANSMIT_INTERRUPT_ENABLE_NUM     2
+#define MMC_TRANSMIT_INTERRUPT_ENABLE_INC     0x4000
+#define MMC_TRANSMIT_INTERRUPT_ENABLE_TYPE    REG_TYPE_RO
+#define MMC_TRANSMIT_INTERRUPT_ENABLE_DEFAULT 0x0
+	/*[field] TXGBOCTIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBOCTIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBOCTIE_OFFSET  0
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBOCTIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBOCTIE_DEFAULT 0x0
+	/*[field] TXGBFRMIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBFRMIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBFRMIE_OFFSET  1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBFRMIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBFRMIE_DEFAULT 0x0
+	/*[field] TXBCGFIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGFIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGFIE_OFFSET  2
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGFIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGFIE_DEFAULT 0x0
+	/*[field] TXMCGFIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGFIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGFIE_OFFSET  3
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGFIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGFIE_DEFAULT 0x0
+	/*[field] TX64OCTGBFIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX64OCTGBFIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX64OCTGBFIE_OFFSET  4
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX64OCTGBFIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX64OCTGBFIE_DEFAULT 0x0
+	/*[field] TX65T127OCTGBFIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX65T127OCTGBFIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX65T127OCTGBFIE_OFFSET  5
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX65T127OCTGBFIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX65T127OCTGBFIE_DEFAULT 0x0
+	/*[field] TX128T255OCTGBFIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX128T255OCTGBFIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX128T255OCTGBFIE_OFFSET  6
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX128T255OCTGBFIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX128T255OCTGBFIE_DEFAULT 0x0
+	/*[field] TX256T511OCTGBFIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX256T511OCTGBFIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX256T511OCTGBFIE_OFFSET  7
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX256T511OCTGBFIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX256T511OCTGBFIE_DEFAULT 0x0
+	/*[field] TX512T1023OCTGBFIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX512T1023OCTGBFIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX512T1023OCTGBFIE_OFFSET  8
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX512T1023OCTGBFIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX512T1023OCTGBFIE_DEFAULT 0x0
+	/*[field] TX1024TMAXOCTGBFIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX1024TMAXOCTGBFIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX1024TMAXOCTGBFIE_OFFSET  9
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX1024TMAXOCTGBFIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TX1024TMAXOCTGBFIE_DEFAULT 0x0
+	/*[field] TXUCGBFIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUCGBFIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUCGBFIE_OFFSET  10
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUCGBFIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUCGBFIE_DEFAULT 0x0
+	/*[field] TXMCGBFIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGBFIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGBFIE_OFFSET  11
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGBFIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGBFIE_DEFAULT 0x0
+	/*[field] TXBCGBFIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGBFIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGBFIE_OFFSET  12
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGBFIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGBFIE_DEFAULT 0x0
+	/*[field] TXUFLOWERFIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUFLOWERFIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUFLOWERFIE_OFFSET  13
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUFLOWERFIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUFLOWERFIE_DEFAULT 0x0
+	/*[field] TXGOCTIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGOCTIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGOCTIE_OFFSET  14
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGOCTIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGOCTIE_DEFAULT 0x0
+	/*[field] TXGFRMIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGFRMIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGFRMIE_OFFSET  15
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGFRMIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGFRMIE_DEFAULT 0x0
+	/*[field] TXPAUSFIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPAUSFIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPAUSFIE_OFFSET  16
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPAUSFIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPAUSFIE_DEFAULT 0x0
+	/*[field] TXVLANGFIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXVLANGFIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXVLANGFIE_OFFSET  17
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXVLANGFIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXVLANGFIE_DEFAULT 0x0
+	/*[field] TXLPIUSCIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPIUSCIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPIUSCIE_OFFSET  18
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPIUSCIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPIUSCIE_DEFAULT 0x0
+	/*[field] TXLPITRCIE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPITRCIE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPITRCIE_OFFSET  19
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPITRCIE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPITRCIE_DEFAULT 0x0
+	/*[field] TXPRMMCISE*/
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPRMMCISE
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPRMMCISE_OFFSET  31
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPRMMCISE_LEN     1
+	#define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPRMMCISE_DEFAULT 0x0
+
+struct mmc_transmit_interrupt_enable {
+	a_uint32_t  txgboctie:1;
+	a_uint32_t  txgbfrmie:1;
+	a_uint32_t  txbcgfie:1;
+	a_uint32_t  txmcgfie:1;
+	a_uint32_t  tx64octgbfie:1;
+	a_uint32_t  tx65t127octgbfie:1;
+	a_uint32_t  tx128t255octgbfie:1;
+	a_uint32_t  tx256t511octgbfie:1;
+	a_uint32_t  tx512t1023octgbfie:1;
+	a_uint32_t  tx1024tmaxoctgbfie:1;
+	a_uint32_t  txucgbfie:1;
+	a_uint32_t  txmcgbfie:1;
+	a_uint32_t  txbcgbfie:1;
+	a_uint32_t  txuflowerfie:1;
+	a_uint32_t  txgoctie:1;
+	a_uint32_t  txgfrmie:1;
+	a_uint32_t  txpausfie:1;
+	a_uint32_t  txvlangfie:1;
+	a_uint32_t  txlpiuscie:1;
+	a_uint32_t  txlpitrcie:1;
+	a_uint32_t  _reserved0:11;
+	a_uint32_t  txprmmcise:1;
+};
+
+union mmc_transmit_interrupt_enable_u {
+	a_uint32_t val;
+	struct mmc_transmit_interrupt_enable bf;
+};
+
+#endif
diff --git a/qca-ssdk/include/hsl/hsl.h b/qca-ssdk/include/hsl/hsl.h
new file mode 100755
index 0000000..1bb923a
--- /dev/null
+++ b/qca-ssdk/include/hsl/hsl.h
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/*qca808x_start*/
+#ifndef _HSL_H
+#define _HSL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "ssdk_init.h"
+
+    typedef sw_error_t
+    (*hsl_acl_rule_copy) (a_uint32_t dev_id, a_uint32_t src_addr,
+                          a_uint32_t dest_addr, a_uint32_t size);
+
+    typedef sw_error_t
+    (*hsl_acl_rule_invalid) (a_uint32_t dev_id, a_uint32_t addr,
+                             a_uint32_t size);
+
+    typedef sw_error_t
+    (*hsl_acl_addr_update) (a_uint32_t dev_id, a_uint32_t old_addr,
+                            a_uint32_t new_addr, a_uint32_t info);
+
+    typedef struct
+    {
+        hsl_acl_rule_copy     acl_rule_copy;
+        hsl_acl_rule_invalid  acl_rule_invalid;
+        hsl_acl_addr_update   acl_addr_update;
+    } hsl_acl_func_t;
+/*qca808x_end*/
+
+#if 1
+extern sw_error_t reduce_hsl_reg_entry_get(a_uint32_t dev,a_uint32_t reg,a_uint8_t* value,a_uint8_t val_len);
+#define HSL_REG_ENTRY_GET(rv, dev, reg, index, value, val_len) \
+	rv = reduce_hsl_reg_entry_get(dev,reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,value,val_len);
+
+
+extern sw_error_t reduce_hsl_reg_entry_set(a_uint32_t dev,a_uint32_t reg,a_uint8_t* value,a_uint8_t val_len);
+#define HSL_REG_ENTRY_SET(rv, dev, reg, index, value, val_len) \
+	rv = reduce_hsl_reg_entry_set(dev,reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,value,val_len);
+
+extern sw_error_t reduce_hsl_reg_field_get(a_uint32_t dev,a_uint32_t reg,a_uint32_t reg_offset,
+						a_uint32_t reg_offset_len,a_uint8_t* value,a_uint8_t val_len);
+#define HSL_REG_FIELD_GET(rv, dev, reg, index, field, value, val_len) \
+	rv = reduce_hsl_reg_field_get(dev,reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\
+	reg##_##field##_BOFFSET, \
+	reg##_##field##_BLEN,value,val_len);
+
+extern sw_error_t reduce_hsl_reg_field_set(a_uint32_t dev,a_uint32_t reg,a_uint32_t reg_offset,
+						a_uint32_t reg_offset_len,a_uint8_t* value,a_uint8_t val_len);
+
+#define HSL_REG_FIELD_SET(rv, dev, reg, index, field, value, val_len) \
+		rv = reduce_hsl_reg_field_set(dev,reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\
+		reg##_##field##_BOFFSET, \
+		reg##_##field##_BLEN,value,val_len);
+
+
+
+extern sw_error_t reduce_hsl_reg_entry_gen_get(a_uint32_t dev,a_uint32_t addr,a_uint8_t* value,a_uint8_t val_len);
+#define HSL_REG_ENTRY_GEN_GET(rv, dev, addr, reg_len, value, val_len) \
+		rv = reduce_hsl_reg_entry_gen_get(dev,addr,(a_uint8_t*)value,val_len);
+
+
+extern sw_error_t reduce_hsl_reg_entry_gen_set(a_uint32_t dev,a_uint32_t addr,a_uint8_t* value,a_uint8_t val_len);
+#define HSL_REG_ENTRY_GEN_SET(rv, dev, addr, reg_len, value, val_len) \
+		rv = reduce_hsl_reg_entry_gen_set(dev,addr,(a_uint8_t*)value,val_len);
+
+
+
+
+extern sw_error_t reduce_hsl_reg_field_gen_get(a_uint32_t dev,a_uint32_t reg_addr,
+						a_uint32_t bitoffset, a_uint32_t field_len, a_uint8_t* value,a_uint8_t val_len);
+#define HSL_REG_FIELD_GEN_GET(rv, dev, regaddr, bitlength, bitoffset, value, val_len) \
+	rv = reduce_hsl_reg_field_gen_get(dev, regaddr, bitoffset, bitlength, (a_uint8_t*)value, val_len);
+
+extern sw_error_t reduce_hsl_reg_field_gen_set(a_uint32_t dev,a_uint32_t regaddr,a_uint32_t bitoffset,
+						a_uint32_t bitlength,a_uint8_t* value,a_uint8_t val_len);
+
+#define HSL_REG_FIELD_GEN_SET(rv, dev, regaddr, bitlength, bitoffset, value, val_len) \
+		rv = reduce_hsl_reg_field_gen_set(dev,regaddr,bitoffset,bitlength, (a_uint8_t*)value,val_len);
+
+
+/*qca808x_start*/
+extern sw_error_t reduce_hsl_phy_get(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t* value);
+#define HSL_PHY_GET(rv, dev, phy_addr, reg, value) \
+		rv = reduce_hsl_phy_get(dev,phy_addr,reg,value);
+
+
+extern sw_error_t reduce_hsl_phy_set(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t value);
+#define HSL_PHY_SET(rv, dev, phy_addr, reg, value) \
+		rv = reduce_hsl_phy_set(dev,phy_addr,reg,value);
+
+extern sw_error_t hsl_phy_i2c_get(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t* value);
+#define HSL_PHY_I2C_GET(rv, dev, phy_addr, reg, value) \
+		rv = hsl_phy_i2c_get(dev,phy_addr,reg,value);
+
+
+extern sw_error_t hsl_phy_i2c_set(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t value);
+#define HSL_PHY_I2C_SET(rv, dev, phy_addr, reg, value) \
+		rv = hsl_phy_i2c_set(dev,phy_addr,reg,value);
+/*qca808x_end*/
+
+
+
+
+#else
+#define HSL_REG_ENTRY_GET(rv, dev, reg, index, value, val_len) \
+do { \
+    hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+    if (p_api) { \
+        rv = p_api->reg_get(dev, reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\
+                                   (a_uint8_t*)value, (a_uint8_t)val_len); \
+    } else { \
+        rv = SW_NOT_INITIALIZED; \
+    } \
+} while (0);
+
+#define HSL_REG_ENTRY_SET(rv, dev, reg, index, value, val_len) \
+do { \
+    hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+    if (p_api) { \
+        rv = p_api->reg_set (dev, reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\
+                                   (a_uint8_t*)value, (a_uint8_t)val_len); \
+    } else { \
+        rv = SW_NOT_INITIALIZED; \
+    } \
+} while (0);
+
+#define HSL_REG_FIELD_GET(rv, dev, reg, index, field, value, val_len) \
+do { \
+    hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+    if (p_api) { \
+        rv = p_api->reg_field_get(dev, reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\
+                                  reg##_##field##_BOFFSET, \
+                                  reg##_##field##_BLEN, (a_uint8_t*)value, val_len);\
+    } else { \
+        rv = SW_NOT_INITIALIZED; \
+    } \
+} while (0);
+
+#define HSL_REG_FIELD_SET(rv, dev, reg, index, field, value, val_len) \
+do { \
+    hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+    if (p_api){ \
+        rv = p_api->reg_field_set(dev, reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\
+                                  reg##_##field##_BOFFSET, \
+                                  reg##_##field##_BLEN, (a_uint8_t*)value, val_len);\
+    } else { \
+        rv = SW_NOT_INITIALIZED; \
+    } \
+} while (0);
+
+#define HSL_REG_ENTRY_GEN_GET(rv, dev, addr, reg_len, value, val_len) \
+do { \
+    hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+    if (p_api) { \
+        rv = p_api->reg_get(dev, addr, (a_uint8_t*)value, val_len);\
+    } else { \
+        rv = SW_NOT_INITIALIZED; \
+    } \
+} while (0);
+
+#define HSL_REG_ENTRY_GEN_SET(rv, dev, addr, reg_len, value, val_len) \
+do { \
+    hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+    if (p_api) { \
+        rv = p_api->reg_set(dev, addr, (a_uint8_t*)value, val_len); \
+    } else { \
+        rv = SW_NOT_INITIALIZED; \
+    } \
+} while (0);
+
+#define HSL_REG_FIELD_GEN_GET(rv, dev, regaddr, bitlength, bitoffset, value, val_len) \
+do { \
+    hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+    if (p_api) { \
+        rv = p_api->reg_field_get(dev, regaddr, bitoffset, bitlength, \
+                                   (a_uint8_t *) value, val_len);\
+    } else { \
+        rv = SW_NOT_INITIALIZED; \
+    } \
+} while (0);
+
+#define HSL_REG_FIELD_GEN_SET(rv, dev, regaddr, bitlength, bitoffset, value, val_len) \
+do { \
+    hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+    if (p_api) {\
+        rv = p_api->reg_field_set(dev, regaddr, bitoffset, bitlength, \
+                                   (a_uint8_t *) value, val_len);\
+    } else { \
+        rv = SW_NOT_INITIALIZED; \
+    } \
+} while (0);
+
+#define HSL_PHY_GET(rv, dev, phy_addr, reg, value) \
+do { \
+    hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+    if (p_api) { \
+        rv = p_api->phy_get(dev, phy_addr, reg, value); \
+    } else { \
+        rv = SW_NOT_INITIALIZED; \
+    } \
+} while (0);
+
+#define HSL_PHY_SET(rv, dev, phy_addr, reg, value) \
+do { \
+    hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+    if (p_api) { \
+        rv = p_api->phy_set(dev, phy_addr, reg, value); \
+    } else { \
+        rv = SW_NOT_INITIALIZED; \
+    } \
+} while (0);
+#endif
+/*qca808x_start*/
+#if (defined(API_LOCK) \
+&& (defined(HSL_STANDALONG) || (defined(KERNEL_MODULE) && defined(USER_MODE))))
+    extern  aos_lock_t sw_hsl_api_lock;
+#define HSL_API_LOCK    aos_lock(&sw_hsl_api_lock)
+#define HSL_API_UNLOCK  aos_unlock(&sw_hsl_api_lock)
+#else
+#define HSL_API_LOCK
+#define HSL_API_UNLOCK
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _HSL_H */
+/*qca808x_end*/
diff --git a/qca-ssdk/include/hsl/hsl_acl.h b/qca-ssdk/include/hsl/hsl_acl.h
new file mode 100755
index 0000000..ab95185
--- /dev/null
+++ b/qca-ssdk/include/hsl/hsl_acl.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HSL_ACL_H_
+#define _HSL_ACL_H_
+
+#ifdef __cplusplus
+extern "c" {
+#endif
+
+    sw_error_t
+    hsl_acl_pool_creat(a_uint32_t dev_id, a_uint32_t blk_nr, a_uint32_t rsc_nr);
+
+    sw_error_t
+    hsl_acl_pool_destroy(a_uint32_t dev_id);
+
+    sw_error_t
+    hsl_acl_blk_alloc(a_uint32_t dev_id, a_uint32_t pri, a_uint32_t size,
+                      a_uint32_t info, a_uint32_t * addr);
+
+    sw_error_t
+    hsl_acl_blk_free(a_uint32_t dev_id, a_uint32_t addr);
+
+    sw_error_t
+    hsl_acl_blk_resize(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t new_size);
+
+    sw_error_t
+    hsl_acl_free_rsc_get(a_uint32_t dev_id, a_uint32_t * free_rsc);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /*_HSL_ACL_H_ */
diff --git a/qca-ssdk/include/hsl/hsl_api.h b/qca-ssdk/include/hsl/hsl_api.h
new file mode 100755
index 0000000..7ea0cc3
--- /dev/null
+++ b/qca-ssdk/include/hsl/hsl_api.h
@@ -0,0 +1,2619 @@
+/*
+ * Copyright (c) 2012, 2015, 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/*qca808x_start*/
+#ifndef _HSL_API_H
+#define _HSL_API_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif				/* __cplusplus */
+
+#include "fal.h"
+/*qca808x_end*/
+
+  /* Misc */
+#define MISC_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_arp_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_arp_status_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_frame_max_size_set) (a_uint32_t dev_id, a_uint32_t size);
+
+  typedef sw_error_t
+    (*hsl_frame_max_size_get) (a_uint32_t dev_id, a_uint32_t * size);
+
+  typedef sw_error_t
+    (*hsl_port_unk_sa_cmd_set) (a_uint32_t dev_id, fal_port_t port_id,
+				fal_fwd_cmd_t cmd);
+
+  typedef sw_error_t
+    (*hsl_port_unk_sa_cmd_get) (a_uint32_t dev_id, fal_port_t port_id,
+				fal_fwd_cmd_t * cmd);
+
+  typedef sw_error_t
+    (*hsl_port_unk_uc_filter_set) (a_uint32_t dev_id, fal_port_t port_id,
+				   a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_unk_uc_filter_get) (a_uint32_t dev_id, fal_port_t port_id,
+				   a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_unk_mc_filter_set) (a_uint32_t dev_id, fal_port_t port_id,
+				   a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_unk_mc_filter_get) (a_uint32_t dev_id, fal_port_t port_id,
+				   a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_bc_filter_set) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_bc_filter_get) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_cpu_port_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_cpu_port_status_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_bc_to_cpu_port_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_bc_to_cpu_port_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_dhcp_set) (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_pppoe_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+  typedef sw_error_t
+    (*hsl_pppoe_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+  typedef sw_error_t
+    (*hsl_pppoe_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_pppoe_status_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_dhcp_get) (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_arp_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+  typedef sw_error_t
+    (*hsl_arp_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+  typedef sw_error_t
+    (*hsl_eapol_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+  typedef sw_error_t
+    (*hsl_eapol_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+  typedef sw_error_t
+    (*hsl_pppoe_session_add) (a_uint32_t dev_id, a_uint32_t session_id,
+			      a_bool_t strip_hdr);
+
+  typedef sw_error_t
+    (*hsl_pppoe_session_del) (a_uint32_t dev_id, a_uint32_t session_id);
+
+  typedef sw_error_t
+    (*hsl_pppoe_session_get) (a_uint32_t dev_id, a_uint32_t session_id,
+			      a_bool_t * strip_hdr);
+
+  typedef sw_error_t
+    (*hsl_eapol_status_set) (a_uint32_t dev_id, a_uint32_t port_id,
+			     a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_eapol_status_get) (a_uint32_t dev_id, a_uint32_t port_id,
+			     a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_ripv1_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_ripv1_status_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_arp_req_status_set) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_arp_req_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_arp_ack_status_set) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_arp_ack_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_pppoe_session_table_add) (a_uint32_t dev_id,
+				    fal_pppoe_session_t * session_tbl);
+
+  typedef sw_error_t
+    (*hsl_pppoe_session_table_del) (a_uint32_t dev_id,
+				    fal_pppoe_session_t * session_tbl);
+
+  typedef sw_error_t
+    (*hsl_pppoe_session_table_get) (a_uint32_t dev_id,
+				    fal_pppoe_session_t * session_tbl);
+
+  typedef sw_error_t
+    (*hsl_pppoe_session_id_set) (a_uint32_t dev_id, a_uint32_t index,
+				 a_uint32_t id);
+
+  typedef sw_error_t
+    (*hsl_pppoe_session_id_get) (a_uint32_t dev_id, a_uint32_t index,
+				 a_uint32_t * id);
+
+  typedef sw_error_t
+    (*hsl_intr_mask_set) (a_uint32_t dev_id, a_uint32_t intr_mask);
+
+  typedef sw_error_t
+    (*hsl_intr_mask_get) (a_uint32_t dev_id, a_uint32_t * intr_mask);
+
+  typedef sw_error_t
+    (*hsl_intr_status_get) (a_uint32_t dev_id, a_uint32_t * intr_status);
+
+  typedef sw_error_t
+    (*hsl_intr_status_clear) (a_uint32_t dev_id, a_uint32_t intr_status);
+
+  typedef sw_error_t
+    (*hsl_intr_port_link_mask_set) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_uint32_t intr_mask);
+
+  typedef sw_error_t
+    (*hsl_intr_port_link_mask_get) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_uint32_t * intr_mask);
+
+  typedef sw_error_t
+    (*hsl_intr_port_link_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+				      a_uint32_t * intr_mask);
+
+  typedef sw_error_t
+    (*hsl_intr_mask_mac_linkchg_set) (a_uint32_t dev_id, fal_port_t port_id,
+				      a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_intr_mask_mac_linkchg_get) (a_uint32_t dev_id, fal_port_t port_id,
+				      a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_intr_status_mac_linkchg_get) (a_uint32_t dev_id,
+					fal_pbmp_t * port_bitmap);
+
+  typedef sw_error_t (*hsl_intr_status_mac_linkchg_clear) (a_uint32_t dev_id);
+
+  typedef sw_error_t
+    (*hsl_cpu_vid_en_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_cpu_vid_en_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_rtd_pppoe_en_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_rtd_pppoe_en_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_global_macaddr_set) (a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+  typedef sw_error_t
+    (*hsl_global_macaddr_get) (a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+  typedef sw_error_t
+    (*hsl_lldp_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_lldp_status_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_frame_crc_reserve_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_frame_crc_reserve_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+
+  typedef sw_error_t
+    (*hsl_register_dump) (a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump);
+
+  typedef sw_error_t
+    (*hsl_debug_register_dump) (a_uint32_t dev_id, fal_debug_reg_dump_t * reg_dump);
+ /*qca808x_start*/
+
+  /* Port Control */
+#define PORT_CONTROL_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_port_duplex_get) (a_uint32_t dev_id, fal_port_t port_id,
+			    fal_port_duplex_t * pduplex);
+
+  typedef sw_error_t
+    (*hsl_port_duplex_set) (a_uint32_t dev_id, fal_port_t port_id,
+			    fal_port_duplex_t duplex);
+
+  typedef sw_error_t
+    (*hsl_port_speed_get) (a_uint32_t dev_id, fal_port_t port_id,
+			   fal_port_speed_t * pspeed);
+
+  typedef sw_error_t
+    (*hsl_port_autoneg_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_bool_t * status);
+
+  typedef sw_error_t
+    (*hsl_port_speed_set) (a_uint32_t dev_id, fal_port_t port_id,
+			   fal_port_speed_t speed);
+
+  typedef sw_error_t
+    (*hsl_port_autoneg_enable) (a_uint32_t dev_id, fal_port_t port_id);
+
+  typedef sw_error_t
+    (*hsl_port_autoneg_restart) (a_uint32_t dev_id, fal_port_t port_id);
+
+  typedef sw_error_t
+    (*hsl_port_autoneg_adv_get) (a_uint32_t dev_id, fal_port_t port_id,
+				 a_uint32_t * autoadv);
+
+  typedef sw_error_t
+    (*hsl_port_autoneg_adv_set) (a_uint32_t dev_id, fal_port_t port_id,
+				 a_uint32_t autoadv);
+
+  typedef sw_error_t
+    (*hsl_port_hdr_status_set) (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_hdr_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_flowctrl_set) (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_flowctrl_get) (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * enable);
+typedef sw_error_t
+    (*hsl_port_flowctrl_thresh_set) (a_uint32_t dev_id, fal_port_t port_id,
+			      a_uint8_t  on, a_uint8_t  off);
+
+  typedef sw_error_t
+    (*hsl_port_flowctrl_forcemode_set) (a_uint32_t dev_id, fal_port_t port_id,
+					a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_flowctrl_forcemode_get) (a_uint32_t dev_id, fal_port_t port_id,
+					a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_powersave_set) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable);
+
+
+  typedef sw_error_t
+    (*hsl_port_powersave_get) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable);
+
+
+  typedef sw_error_t
+    (*hsl_port_hibernate_set) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable);
+
+
+  typedef sw_error_t
+    (*hsl_port_hibernate_get) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable);
+
+
+  typedef sw_error_t
+    (*hsl_port_cdt) (a_uint32_t dev_id, fal_port_t port_id,
+		     a_uint32_t mdi_pair, fal_cable_status_t * cable_status,
+		     a_uint32_t * cable_len);
+
+  typedef sw_error_t
+    (*hsl_port_rxhdr_mode_set) (a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_header_mode_t mode);
+
+  typedef sw_error_t
+    (*hsl_port_rxhdr_mode_get) (a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_header_mode_t * mode);
+
+  typedef sw_error_t
+    (*hsl_port_txhdr_mode_set) (a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_header_mode_t mode);
+
+  typedef sw_error_t
+    (*hsl_port_txhdr_mode_get) (a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_header_mode_t * mode);
+
+  typedef sw_error_t
+    (*hsl_header_type_set) (a_uint32_t dev_id, a_bool_t enable,
+			    a_uint32_t type);
+
+  typedef sw_error_t
+    (*hsl_header_type_get) (a_uint32_t dev_id, a_bool_t * enable,
+			    a_uint32_t * type);
+
+  typedef sw_error_t
+    (*hsl_port_txmac_status_set) (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_txmac_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_rxmac_status_set) (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_rxmac_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_txfc_status_set) (a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_txfc_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_rxfc_status_set) (a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_rxfc_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_bp_status_set) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_bp_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_link_forcemode_set) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_link_forcemode_get) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_link_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t * status);
+
+  typedef sw_error_t
+    (*hsl_ports_link_status_get) (a_uint32_t dev_id, a_uint32_t * status);
+
+  typedef sw_error_t
+    (*hsl_port_mac_loopback_set) (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_mac_loopback_get) (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_congestion_drop_set) (a_uint32_t dev_id, fal_port_t port_id,
+				     a_uint32_t queue_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_congestion_drop_get) (a_uint32_t dev_id, fal_port_t port_id,
+				     a_uint32_t queue_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_ring_flow_ctrl_thres_set) (a_uint32_t dev_id, a_uint32_t ring_id,
+				     a_uint8_t on_thres, a_uint8_t off_thres);
+
+  typedef sw_error_t
+    (*hsl_ring_flow_ctrl_thres_get) (a_uint32_t dev_id, a_uint32_t ring_id,
+				     a_uint8_t * on_thres,
+				     a_uint8_t * off_thres);
+
+  typedef sw_error_t
+    (*hsl_port_8023az_set) (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t enable);
+
+
+  typedef sw_error_t
+    (*hsl_port_8023az_get) (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_mdix_set) (a_uint32_t dev_id, fal_port_t port_id,
+			  fal_port_mdix_mode_t mode);
+
+  typedef sw_error_t
+    (*hsl_port_mdix_get) (a_uint32_t dev_id, fal_port_t port_id,
+			  fal_port_mdix_mode_t * mode);
+
+  typedef sw_error_t
+    (*hsl_port_mdix_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+				 fal_port_mdix_status_t * mode);
+
+  typedef sw_error_t
+    (*hsl_port_combo_prefer_medium_set) (a_uint32_t dev_id,
+					 fal_port_t port_id,
+					 fal_port_medium_t medium);
+
+  typedef sw_error_t
+    (*hsl_port_combo_prefer_medium_get) (a_uint32_t dev_id,
+					 fal_port_t port_id,
+					 fal_port_medium_t * medium);
+
+  typedef sw_error_t
+    (*hsl_port_combo_medium_status_get) (a_uint32_t dev_id,
+					 fal_port_t port_id,
+					 fal_port_medium_t * medium);
+
+  typedef sw_error_t
+    (*hsl_port_combo_fiber_mode_set) (a_uint32_t dev_id, fal_port_t port_id,
+				      fal_port_fiber_mode_t mode);
+
+  typedef sw_error_t
+    (*hsl_port_combo_fiber_mode_get) (a_uint32_t dev_id, fal_port_t port_id,
+				      fal_port_fiber_mode_t * mode);
+
+  typedef sw_error_t
+    (*hsl_port_local_loopback_set) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_local_loopback_get) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_remote_loopback_set) (a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_remote_loopback_get) (a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_reset) (a_uint32_t dev_id, fal_port_t port_id);
+
+  typedef sw_error_t
+    (*hsl_port_power_off) (a_uint32_t dev_id, fal_port_t port_id);
+
+  typedef sw_error_t
+    (*hsl_port_power_on) (a_uint32_t dev_id, fal_port_t port_id);
+
+  typedef sw_error_t
+    (*hsl_port_phy_id_get) (a_uint32_t dev_id, fal_port_t port_id,a_uint16_t * org_id, a_uint16_t * rev_id);
+
+  typedef sw_error_t
+    (*hsl_port_wol_status_set) (a_uint32_t dev_id, fal_port_t port_id,a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_wol_status_get) (a_uint32_t dev_id, fal_port_t port_id,a_bool_t *enable);
+
+  typedef sw_error_t
+    (*hsl_port_magic_frame_mac_set) (a_uint32_t dev_id, fal_port_t port_id,fal_mac_addr_t * mac);
+
+  typedef sw_error_t
+    (*hsl_port_magic_frame_mac_get) (a_uint32_t dev_id, fal_port_t port_id,fal_mac_addr_t * mac);
+
+  typedef sw_error_t
+    (*hsl_port_interface_mode_set) (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t mode);
+
+  typedef sw_error_t
+    (*hsl_port_interface_mode_get) (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t * mode);
+    typedef sw_error_t
+    (*hsl_port_interface_mode_apply) (a_uint32_t dev_id);
+
+  typedef sw_error_t
+    (*hsl_port_interface_mode_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t * mode);
+   typedef sw_error_t
+    (*hsl_port_counter_set) (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t enable);
+  typedef sw_error_t
+    (*hsl_port_counter_get) (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t * enable);
+    typedef sw_error_t
+    (*hsl_port_counter_show) (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_counter_info_t * counter_info);
+/*qca808x_end*/
+
+  /* VLAN */
+#define VLAN_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_vlan_entry_append) (a_uint32_t dev_id,
+			      const fal_vlan_t * vlan_entry);
+
+  typedef sw_error_t
+    (*hsl_vlan_create) (a_uint32_t dev_id, a_uint32_t vlan_id);
+
+  typedef sw_error_t
+    (*hsl_vlan_next) (a_uint32_t dev_id, a_uint32_t vlan_id,
+		      fal_vlan_t * p_vlan);
+
+  typedef sw_error_t
+    (*hsl_vlan_find) (a_uint32_t dev_id, a_uint32_t vlan_id,
+		      fal_vlan_t * p_vlan);
+
+  typedef sw_error_t
+    (*hsl_vlan_member_update) (a_uint32_t dev_id, a_uint32_t vlan_id,
+			       fal_pbmp_t member, fal_pbmp_t u_member);
+
+  typedef sw_error_t
+    (*hsl_vlan_delete) (a_uint32_t dev_id, a_uint32_t vlan_id);
+
+  typedef sw_error_t (*hsl_vlan_flush) (a_uint32_t dev_id);
+
+  typedef sw_error_t
+    (*hsl_vlan_fid_set) (a_uint32_t dev_id, a_uint32_t vlan_id,
+			 a_uint32_t fid);
+
+  typedef sw_error_t
+    (*hsl_vlan_fid_get) (a_uint32_t dev_id, a_uint32_t vlan_id,
+			 a_uint32_t * fid);
+
+  typedef sw_error_t
+    (*hsl_vlan_member_add) (a_uint32_t dev_id, a_uint32_t vlan_id,
+			    fal_port_t port_id, fal_pt_1q_egmode_t port_info);
+
+  typedef sw_error_t
+    (*hsl_vlan_member_del) (a_uint32_t dev_id, a_uint32_t vlan_id,
+			    fal_port_t port_id);
+
+  typedef sw_error_t
+    (*hsl_vlan_learning_state_set) (a_uint32_t dev_id, a_uint32_t vlan_id,
+				    a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_vlan_learning_state_get) (a_uint32_t dev_id, a_uint32_t vlan_id,
+				    a_bool_t * enable);
+
+  /* Port Vlan */
+#define PORT_VLAN_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_port_1qmode_get) (a_uint32_t dev_id, fal_port_t port_id,
+			    fal_pt_1qmode_t * pport_1qmode);
+
+  typedef sw_error_t
+    (*hsl_port_1qmode_set) (a_uint32_t dev_id, fal_port_t port_id,
+			    fal_pt_1qmode_t port_1qmode);
+
+  typedef sw_error_t
+    (*hsl_port_egvlanmode_get) (a_uint32_t dev_id, fal_port_t port_id,
+				fal_pt_1q_egmode_t * pport_egvlanmode);
+
+  typedef sw_error_t
+    (*hsl_port_egvlanmode_set) (a_uint32_t dev_id, fal_port_t port_id,
+				fal_pt_1q_egmode_t port_egvlanmode);
+
+  typedef sw_error_t
+    (*hsl_portvlan_member_add) (a_uint32_t dev_id, fal_port_t port_id,
+				a_uint32_t mem_port_id);
+
+  typedef sw_error_t
+    (*hsl_portvlan_member_del) (a_uint32_t dev_id, fal_port_t port_id,
+				a_uint32_t mem_port_id);
+
+  typedef sw_error_t
+    (*hsl_portvlan_member_update) (a_uint32_t dev_id, fal_port_t port_id,
+				   fal_pbmp_t mem_port_map);
+
+  typedef sw_error_t
+    (*hsl_portvlan_member_get) (a_uint32_t dev_id, fal_port_t port_id,
+				fal_pbmp_t * mem_port_map);
+
+  typedef sw_error_t
+    (*hsl_port_nestvlan_set) (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_nestvlan_get) (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_nestvlan_tpid_set) (a_uint32_t dev_id, a_uint32_t tpid);
+
+  typedef sw_error_t
+    (*hsl_nestvlan_tpid_get) (a_uint32_t dev_id, a_uint32_t * tpid);
+
+  typedef sw_error_t
+    (*hsl_port_default_vid_set) (a_uint32_t dev_id, fal_port_t port_id,
+				 a_uint32_t vid);
+
+  typedef sw_error_t
+    (*hsl_port_default_vid_get) (a_uint32_t dev_id, fal_port_t port_id,
+				 a_uint32_t * vid);
+
+  typedef sw_error_t
+    (*hsl_port_force_default_vid_set) (a_uint32_t dev_id,
+				       fal_port_t port_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_force_default_vid_get) (a_uint32_t dev_id,
+				       fal_port_t port_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_force_portvlan_set) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_force_portvlan_get) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_invlan_mode_set) (a_uint32_t dev_id, fal_port_t port_id,
+				 fal_pt_invlan_mode_t mode);
+
+  typedef sw_error_t
+    (*hsl_port_invlan_mode_get) (a_uint32_t dev_id, fal_port_t port_id,
+				 fal_pt_invlan_mode_t * mode);
+
+  typedef sw_error_t
+    (*hsl_port_tls_set) (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_tls_get) (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_pri_propagation_set) (a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_pri_propagation_get) (a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_default_svid_set) (a_uint32_t dev_id, fal_port_t port_id,
+				  a_uint32_t vid);
+
+  typedef sw_error_t
+    (*hsl_port_default_svid_get) (a_uint32_t dev_id, fal_port_t port_id,
+				  a_uint32_t * vid);
+
+  typedef sw_error_t
+    (*hsl_port_default_cvid_set) (a_uint32_t dev_id, fal_port_t port_id,
+				  a_uint32_t vid);
+
+  typedef sw_error_t
+    (*hsl_port_default_cvid_get) (a_uint32_t dev_id, fal_port_t port_id,
+				  a_uint32_t * vid);
+
+  typedef sw_error_t
+    (*hsl_port_vlan_propagation_set) (a_uint32_t dev_id, fal_port_t port_id,
+				      fal_vlan_propagation_mode_t mode);
+
+  typedef sw_error_t
+    (*hsl_port_vlan_propagation_get) (a_uint32_t dev_id, fal_port_t port_id,
+				      fal_vlan_propagation_mode_t * mode);
+
+  typedef sw_error_t
+    (*hsl_port_vlan_trans_add) (a_uint32_t dev_id, fal_port_t port_id,
+				fal_vlan_trans_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_port_vlan_trans_del) (a_uint32_t dev_id, fal_port_t port_id,
+				fal_vlan_trans_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_port_vlan_trans_get) (a_uint32_t dev_id, fal_port_t port_id,
+				fal_vlan_trans_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_qinq_mode_set) (a_uint32_t dev_id, fal_qinq_mode_t mode);
+
+  typedef sw_error_t
+    (*hsl_qinq_mode_get) (a_uint32_t dev_id, fal_qinq_mode_t * mode);
+
+  typedef sw_error_t
+    (*hsl_port_qinq_role_set) (a_uint32_t dev_id, fal_port_t port_id,
+			       fal_qinq_port_role_t role);
+
+  typedef sw_error_t
+    (*hsl_port_qinq_role_get) (a_uint32_t dev_id, fal_port_t port_id,
+			       fal_qinq_port_role_t * role);
+
+  typedef sw_error_t
+    (*hsl_port_vlan_trans_iterate) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_uint32_t * iterator,
+				    fal_vlan_trans_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_port_mac_vlan_xlt_set) (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_mac_vlan_xlt_get) (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_netisolate_set) (a_uint32_t dev_id, a_uint32_t enable);
+
+  typedef sw_error_t
+    (*hsl_netisolate_get) (a_uint32_t dev_id, a_uint32_t * enable);
+
+  typedef sw_error_t
+    (*hsl_eg_trans_filter_bypass_en_set) (a_uint32_t dev_id,
+					  a_uint32_t enable);
+
+  typedef sw_error_t
+    (*hsl_eg_trans_filter_bypass_en_get) (a_uint32_t dev_id,
+					  a_uint32_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_vrf_id_set) (a_uint32_t dev_id, fal_port_t port_id,
+			    a_uint32_t vrf_id);
+
+  typedef sw_error_t
+    (*hsl_port_vrf_id_get) (a_uint32_t dev_id, fal_port_t port_id,
+			    a_uint32_t * vrf_id);
+
+  /* FDB */
+#define FDB_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_fdb_add) (a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_fdb_rfs_set) (a_uint32_t dev_id, const fal_fdb_rfs_t * entry);
+
+  typedef sw_error_t
+    (*hsl_fdb_rfs_del) (a_uint32_t dev_id, const fal_fdb_rfs_t * entry);
+
+  typedef sw_error_t (*hsl_fdb_del_all) (a_uint32_t dev_id, a_uint32_t flag);
+
+  typedef sw_error_t
+    (*hsl_fdb_del_by_port) (a_uint32_t dev_id, a_uint32_t port_id,
+			    a_uint32_t flag);
+
+  typedef sw_error_t
+    (*hsl_fdb_del_by_mac) (a_uint32_t dev_id, const fal_fdb_entry_t * addr);
+
+  typedef sw_error_t
+    (*hsl_fdb_first) (a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_fdb_next) (a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_fdb_find) (a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_fdb_port_learn_set) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_fdb_port_learn_get) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_fdb_age_ctrl_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_fdb_age_ctrl_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_fdb_vlan_ivl_svl_set) (a_uint32_t dev_id, fal_fdb_smode smode);
+
+  typedef sw_error_t
+    (*hsl_fdb_vlan_ivl_svl_get) (a_uint32_t dev_id, fal_fdb_smode * smode);
+
+  typedef sw_error_t
+    (*hsl_fdb_age_time_set) (a_uint32_t dev_id, a_uint32_t * time);
+
+  typedef sw_error_t
+    (*hsl_fdb_age_time_get) (a_uint32_t dev_id, a_uint32_t * time);
+
+  typedef sw_error_t
+    (*hsl_fdb_iterate) (a_uint32_t dev_id, a_uint32_t * iterator,
+			fal_fdb_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_fdb_extend_next) (a_uint32_t dev_id, fal_fdb_op_t * op,
+			    fal_fdb_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_fdb_extend_first) (a_uint32_t dev_id, fal_fdb_op_t * option,
+			     fal_fdb_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_fdb_transfer) (a_uint32_t dev_id, fal_port_t old_port,
+			 fal_port_t new_port, a_uint32_t fid,
+			 fal_fdb_op_t * option);
+
+  typedef sw_error_t
+    (*hsl_port_fdb_learn_limit_set) (a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t enable, a_uint32_t cnt);
+
+  typedef sw_error_t
+    (*hsl_port_fdb_learn_limit_get) (a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t * enable, a_uint32_t * cnt);
+
+  typedef sw_error_t
+    (*hsl_port_fdb_learn_exceed_cmd_set) (a_uint32_t dev_id,
+					  fal_port_t port_id,
+					  fal_fwd_cmd_t cmd);
+
+  typedef sw_error_t
+    (*hsl_port_fdb_learn_exceed_cmd_get) (a_uint32_t dev_id,
+					  fal_port_t port_id,
+					  fal_fwd_cmd_t * cmd);
+
+  typedef sw_error_t
+    (*hsl_fdb_learn_limit_set) (a_uint32_t dev_id, a_bool_t enable,
+				a_uint32_t cnt);
+
+  typedef sw_error_t
+    (*hsl_fdb_learn_limit_get) (a_uint32_t dev_id, a_bool_t * enable,
+				a_uint32_t * cnt);
+
+  typedef sw_error_t
+    (*hsl_fdb_learn_exceed_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+  typedef sw_error_t
+    (*hsl_fdb_learn_exceed_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+  typedef sw_error_t
+    (*hsl_fdb_resv_add) (a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_fdb_resv_del) (a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_fdb_resv_find) (a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_fdb_resv_iterate) (a_uint32_t dev_id, a_uint32_t * iterator,
+			     fal_fdb_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_fdb_port_learn_static_set) (a_uint32_t dev_id, fal_port_t port_id,
+				      a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_fdb_port_learn_static_get) (a_uint32_t dev_id, fal_port_t port_id,
+				      a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_fdb_port_add) (a_uint32_t dev_id, a_uint32_t fid,
+			 fal_mac_addr_t * addr, fal_port_t port_id);
+
+  typedef sw_error_t
+    (*hsl_fdb_port_del) (a_uint32_t dev_id, a_uint32_t fid,
+			 fal_mac_addr_t * addr, fal_port_t port_id);
+
+  /* QOS */
+#define QOS_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_cosmap_up_queue_set) (a_uint32_t dev_id, a_uint32_t up,
+				fal_queue_t queue);
+
+  typedef sw_error_t
+    (*hsl_cosmap_up_queue_get) (a_uint32_t dev_id, a_uint32_t up,
+				fal_queue_t * queue);
+
+  typedef sw_error_t
+    (*hsl_cosmap_dscp_queue_set) (a_uint32_t dev_id, a_uint32_t dscp,
+				  fal_queue_t queue);
+
+  typedef sw_error_t
+    (*hsl_cosmap_dscp_queue_get) (a_uint32_t dev_id, a_uint32_t dscp,
+				  fal_queue_t * queue);
+
+  typedef sw_error_t
+    (*hsl_qos_port_mode_set) (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_qos_mode_t mode, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_qos_port_mode_get) (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_qos_mode_t mode, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_qos_port_mode_pri_set) (a_uint32_t dev_id, fal_port_t port_id,
+				  fal_qos_mode_t mode, a_uint32_t pri);
+
+  typedef sw_error_t
+    (*hsl_qos_port_mode_pri_get) (a_uint32_t dev_id, fal_port_t port_id,
+				  fal_qos_mode_t mode, a_uint32_t * pri);
+
+  typedef sw_error_t
+    (*hsl_qos_port_default_up_set) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_uint32_t up);
+
+  typedef sw_error_t
+    (*hsl_qos_port_default_up_get) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_uint32_t * up);
+
+  typedef sw_error_t
+    (*hsl_qos_sch_mode_set) (a_uint32_t dev_id,
+			     fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+  typedef sw_error_t
+    (*hsl_qos_sch_mode_get) (a_uint32_t dev_id,
+			     fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+  typedef sw_error_t
+    (*hsl_qos_queue_tx_buf_status_set) (a_uint32_t dev_id, fal_port_t port_id,
+					a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_qos_queue_tx_buf_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+					a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_qos_queue_tx_buf_nr_set) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_uint32_t queue_id, a_uint32_t * number);
+
+  typedef sw_error_t
+    (*hsl_qos_queue_tx_buf_nr_get) (a_uint32_t dev_id, fal_port_t port_id,
+				    a_uint32_t queue_id, a_uint32_t * number);
+
+  typedef sw_error_t
+    (*hsl_qos_port_tx_buf_status_set) (a_uint32_t dev_id, fal_port_t port_id,
+				       a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_qos_port_tx_buf_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+				       a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_qos_port_red_en_set) (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_qos_port_red_en_get) (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_qos_port_tx_buf_nr_set) (a_uint32_t dev_id, fal_port_t port_id,
+				   a_uint32_t * number);
+
+  typedef sw_error_t
+    (*hsl_qos_port_tx_buf_nr_get) (a_uint32_t dev_id, fal_port_t port_id,
+				   a_uint32_t * number);
+
+  typedef sw_error_t
+    (*hsl_qos_port_rx_buf_nr_set) (a_uint32_t dev_id, fal_port_t port_id,
+				   a_uint32_t * number);
+
+  typedef sw_error_t
+    (*hsl_qos_port_rx_buf_nr_get) (a_uint32_t dev_id, fal_port_t port_id,
+				   a_uint32_t * number);
+
+  typedef sw_error_t
+    (*hsl_qos_port_sch_mode_set) (a_uint32_t dev_id, a_uint32_t port_id,
+				  fal_sch_mode_t mode,
+				  const a_uint32_t weight[]);
+
+  typedef sw_error_t
+    (*hsl_qos_port_sch_mode_get) (a_uint32_t dev_id, a_uint32_t port_id,
+				  fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+  typedef sw_error_t
+    (*hsl_qos_port_default_spri_set) (a_uint32_t dev_id, fal_port_t port_id,
+				      a_uint32_t spri);
+
+  typedef sw_error_t
+    (*hsl_qos_port_default_spri_get) (a_uint32_t dev_id, fal_port_t port_id,
+				      a_uint32_t * spri);
+
+  typedef sw_error_t
+    (*hsl_qos_port_default_cpri_set) (a_uint32_t dev_id, fal_port_t port_id,
+				      a_uint32_t cpri);
+
+  typedef sw_error_t
+    (*hsl_qos_port_default_cpri_get) (a_uint32_t dev_id, fal_port_t port_id,
+				      a_uint32_t * cpri);
+
+  typedef sw_error_t
+    (*hsl_qos_port_force_spri_status_set) (a_uint32_t dev_id,
+					   fal_port_t port_id,
+					   a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_qos_port_force_spri_status_get) (a_uint32_t dev_id,
+					   fal_port_t port_id,
+					   a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_qos_port_force_cpri_status_set) (a_uint32_t dev_id,
+					   fal_port_t port_id,
+					   a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_qos_port_force_cpri_status_get) (a_uint32_t dev_id,
+					   fal_port_t port_id,
+					   a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_qos_queue_remark_table_set) (a_uint32_t dev_id, fal_port_t port_id,
+				       fal_queue_t queue_id,
+				       a_uint32_t tbl_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_qos_queue_remark_table_get) (a_uint32_t dev_id, fal_port_t port_id,
+				       fal_queue_t queue_id,
+				       a_uint32_t * tbl_id,
+				       a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_static_thresh_get)(a_uint32_t dev_id, fal_port_t port,
+                                       fal_bm_static_cfg_t *cfg);
+
+  typedef sw_error_t
+    (*hsl_port_static_thresh_set)(a_uint32_t dev_id, fal_port_t port,
+                                       fal_bm_static_cfg_t *cfg);
+
+  /* Rate */
+#define RATE_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_rate_queue_egrl_set) (a_uint32_t dev_id, fal_port_t port_id,
+				a_uint32_t queue_id, a_uint32_t * speed,
+				a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_rate_queue_egrl_get) (a_uint32_t dev_id, fal_port_t port_id,
+				a_uint32_t queue_id, a_uint32_t * speed,
+				a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_rate_port_egrl_set) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_uint32_t * speed, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_rate_port_egrl_get) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_uint32_t * speed, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_rate_port_inrl_set) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_uint32_t * speed, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_rate_port_inrl_get) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_uint32_t * speed, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_storm_ctrl_frame_set) (a_uint32_t dev_id, fal_port_t port_id,
+				 fal_storm_type_t storm_type,
+				 a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_storm_ctrl_frame_get) (a_uint32_t dev_id, fal_port_t port_id,
+				 fal_storm_type_t storm_type,
+				 a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_storm_ctrl_rate_set) (a_uint32_t dev_id, fal_port_t port_id,
+				a_uint32_t * rate);
+
+  typedef sw_error_t
+    (*hsl_storm_ctrl_rate_get) (a_uint32_t dev_id, fal_port_t port_id,
+				a_uint32_t * rate);
+
+  typedef sw_error_t
+    (*hsl_rate_port_policer_set) (a_uint32_t dev_id, fal_port_t port_id,
+				  fal_port_policer_t * policer);
+
+  typedef sw_error_t
+    (*hsl_rate_port_policer_get) (a_uint32_t dev_id, fal_port_t port_id,
+				  fal_port_policer_t * policer);
+
+  typedef sw_error_t
+    (*hsl_rate_port_shaper_set) (a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t enable,
+				 fal_egress_shaper_t * shaper);
+
+  typedef sw_error_t
+    (*hsl_rate_port_shaper_get) (a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t * enable,
+				 fal_egress_shaper_t * shaper);
+
+  typedef sw_error_t
+    (*hsl_rate_queue_shaper_set) (a_uint32_t dev_id, fal_port_t port_id,
+				  fal_queue_t queue_id, a_bool_t enable,
+				  fal_egress_shaper_t * shaper);
+
+  typedef sw_error_t
+    (*hsl_rate_queue_shaper_get) (a_uint32_t dev_id, fal_port_t port_id,
+				  fal_queue_t queue_id, a_bool_t * enable,
+				  fal_egress_shaper_t * shaper);
+
+  typedef sw_error_t
+    (*hsl_rate_acl_policer_set) (a_uint32_t dev_id, a_uint32_t policer_id,
+				 fal_acl_policer_t * policer);
+
+  typedef sw_error_t
+    (*hsl_rate_acl_policer_get) (a_uint32_t dev_id, a_uint32_t policer_id,
+				 fal_acl_policer_t * policer);
+
+  typedef sw_error_t
+    (*hsl_rate_port_add_rate_byte_set) (a_uint32_t dev_id, fal_port_t port_id,
+					a_uint32_t number);
+
+  typedef sw_error_t
+    (*hsl_rate_port_add_rate_byte_get) (a_uint32_t dev_id, fal_port_t port_id,
+					a_uint32_t * number);
+  typedef sw_error_t
+    (*hsl_rate_port_gol_flow_en_set) (a_uint32_t dev_id, fal_port_t port_id,
+				      a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_rate_port_gol_flow_en_get) (a_uint32_t dev_id, fal_port_t port_id,
+				      a_bool_t * enable);
+
+  /* Mirror */
+#define MIRROR_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_mirr_analysis_port_set) (a_uint32_t dev_id, fal_port_t port_id);
+
+  typedef sw_error_t
+    (*hsl_mirr_analysis_port_get) (a_uint32_t dev_id, fal_port_t * port_id);
+
+  typedef sw_error_t
+    (*hsl_mirr_port_in_set) (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_mirr_port_in_get) (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_mirr_port_eg_set) (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_mirr_port_eg_get) (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t * enable);
+
+  /* STP */
+#define STP_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_stp_port_state_set) (a_uint32_t dev_id, a_uint32_t st_id,
+			       fal_port_t port_id, fal_stp_state_t state);
+
+  typedef sw_error_t
+    (*hsl_stp_port_state_get) (a_uint32_t dev_id, a_uint32_t st_id,
+			       fal_port_t port_id, fal_stp_state_t * state);
+  /* IGMP */
+#define IGMP_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_port_igmps_status_set) (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_igmps_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_igmp_mld_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+  typedef sw_error_t
+    (*hsl_igmp_mld_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+  typedef sw_error_t
+    (*hsl_port_igmp_join_set) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_igmp_join_get) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_igmp_leave_set) (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_igmp_leave_get) (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t * enable);
+
+  typedef sw_error_t (*hsl_igmp_rp_set) (a_uint32_t dev_id, fal_pbmp_t pts);
+
+  typedef sw_error_t (*hsl_igmp_rp_get) (a_uint32_t dev_id, fal_pbmp_t * pts);
+
+  typedef sw_error_t
+    (*hsl_igmp_entry_creat_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_igmp_entry_creat_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_igmp_entry_static_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_igmp_entry_static_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_igmp_entry_leaky_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_igmp_entry_leaky_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_igmp_entry_v3_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_igmp_entry_v3_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_igmp_entry_queue_set) (a_uint32_t dev_id, a_bool_t enable,
+				 a_uint32_t queue);
+
+  typedef sw_error_t
+    (*hsl_igmp_entry_queue_get) (a_uint32_t dev_id, a_bool_t * enable,
+				 a_uint32_t * queue);
+
+  typedef sw_error_t
+    (*hsl_port_igmp_mld_learn_limit_set) (a_uint32_t dev_id,
+					  fal_port_t port_id, a_bool_t enable,
+					  a_uint32_t cnt);
+
+  typedef sw_error_t
+    (*hsl_port_igmp_mld_learn_limit_get) (a_uint32_t dev_id,
+					  fal_port_t port_id,
+					  a_bool_t * enable,
+					  a_uint32_t * cnt);
+
+  typedef sw_error_t
+    (*hsl_port_igmp_mld_learn_exceed_cmd_set) (a_uint32_t dev_id,
+					       fal_port_t port_id,
+					       fal_fwd_cmd_t cmd);
+
+  typedef sw_error_t
+    (*hsl_port_igmp_mld_learn_exceed_cmd_get) (a_uint32_t dev_id,
+					       fal_port_t port_id,
+					       fal_fwd_cmd_t * cmd);
+  typedef sw_error_t (*hsl_igmp_sg_entry_set) (a_uint32_t dev_id,
+					       fal_igmp_sg_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_igmp_sg_entry_clear) (a_uint32_t dev_id,
+				fal_igmp_sg_entry_t * entry);
+
+  typedef sw_error_t (*hsl_igmp_sg_entry_show) (a_uint32_t dev_id);
+
+  typedef sw_error_t
+    (*hsl_igmp_sg_entry_query) (a_uint32_t dev_id, fal_igmp_sg_info_t * info);
+
+  /* Leaky */
+#define LEAKY_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_uc_leaky_mode_set) (a_uint32_t dev_id,
+			      fal_leaky_ctrl_mode_t ctrl_mode);
+
+  typedef sw_error_t
+    (*hsl_uc_leaky_mode_get) (a_uint32_t dev_id,
+			      fal_leaky_ctrl_mode_t * ctrl_mode);
+
+  typedef sw_error_t
+    (*hsl_mc_leaky_mode_set) (a_uint32_t dev_id,
+			      fal_leaky_ctrl_mode_t ctrl_mode);
+
+  typedef sw_error_t
+    (*hsl_mc_leaky_mode_get) (a_uint32_t dev_id,
+			      fal_leaky_ctrl_mode_t * ctrl_mode);
+
+  typedef sw_error_t
+    (*hsl_port_arp_leaky_set) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_arp_leaky_get) (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_uc_leaky_set) (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_uc_leaky_get) (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_port_mc_leaky_set) (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_mc_leaky_get) (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * enable);
+
+  /* Mib */
+#define MIB_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_get_mib_info) (a_uint32_t dev_id, fal_port_t port_id,
+			 fal_mib_info_t * mib_info);
+
+  typedef sw_error_t
+    (*hsl_get_rx_mib_info) (a_uint32_t dev_id, fal_port_t port_id,
+			    fal_mib_info_t * mib_info);
+
+  typedef sw_error_t
+    (*hsl_get_tx_mib_info) (a_uint32_t dev_id, fal_port_t port_id,
+			    fal_mib_info_t * mib_info);
+
+  typedef sw_error_t
+    (*hsl_mib_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_mib_status_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_mib_port_flush_counters) (a_uint32_t dev_id, fal_port_t port_id);
+
+  typedef sw_error_t
+    (*hsl_mib_cpukeep_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_mib_cpukeep_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  /* Acl */
+#define ACL_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_acl_list_creat) (a_uint32_t dev_id, a_uint32_t list_id,
+			   a_uint32_t list_pri);
+
+  typedef sw_error_t
+    (*hsl_acl_list_destroy) (a_uint32_t dev_id, a_uint32_t list_id);
+
+  typedef sw_error_t
+    (*hsl_acl_rule_add) (a_uint32_t dev_id, a_uint32_t list_id,
+			 a_uint32_t rule_id, a_uint32_t rule_nr,
+			 fal_acl_rule_t * rule);
+
+  typedef sw_error_t
+    (*hsl_acl_rule_delete) (a_uint32_t dev_id, a_uint32_t list_id,
+			    a_uint32_t rule_id, a_uint32_t rule_nr);
+
+  typedef sw_error_t
+    (*hsl_acl_rule_query) (a_uint32_t dev_id, a_uint32_t list_id,
+			   a_uint32_t rule_id, fal_acl_rule_t * rule);
+
+  typedef sw_error_t
+    (*hsl_acl_list_bind) (a_uint32_t dev_id, a_uint32_t list_id,
+			  fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+			  a_uint32_t obj_idx);
+
+  typedef sw_error_t
+    (*hsl_acl_list_unbind) (a_uint32_t dev_id, a_uint32_t list_id,
+			    fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+			    a_uint32_t obj_idx);
+
+  typedef sw_error_t
+    (*hsl_acl_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_acl_status_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t (*hsl_acl_list_dump) (a_uint32_t dev_id);
+
+  typedef sw_error_t (*hsl_acl_rule_dump) (a_uint32_t dev_id);
+
+  typedef sw_error_t
+    (*hsl_acl_port_udf_profile_set) (a_uint32_t dev_id, fal_port_t port_id,
+				     fal_acl_udf_type_t udf_type,
+				     a_uint32_t offset, a_uint32_t length);
+
+  typedef sw_error_t
+    (*hsl_acl_port_udf_profile_get) (a_uint32_t dev_id, fal_port_t port_id,
+				     fal_acl_udf_type_t udf_type,
+				     a_uint32_t * offset,
+				     a_uint32_t * length);
+
+  typedef sw_error_t
+    (*hsl_acl_rule_active) (a_uint32_t dev_id, a_uint32_t list_id,
+			    a_uint32_t rule_id, a_uint32_t rule_nr);
+
+  typedef sw_error_t
+    (*hsl_acl_rule_deactive) (a_uint32_t dev_id, a_uint32_t list_id,
+			      a_uint32_t rule_id, a_uint32_t rule_nr);
+
+  typedef sw_error_t
+    (*hsl_acl_rule_src_filter_sts_set) (a_uint32_t dev_id,
+					a_uint32_t rule_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_acl_rule_src_filter_sts_get) (a_uint32_t dev_id,
+					a_uint32_t rule_id,
+					a_bool_t * enable);
+
+  typedef a_uint32_t
+    (*hsl_acl_rule_get_offset) (a_uint32_t dev_id, a_uint32_t list_id,
+				a_uint32_t rule_id);
+
+  typedef sw_error_t
+    (*hsl_acl_rule_sync_multi_portmap) (a_uint32_t dev_id, a_uint32_t pos,
+					a_uint32_t * act);
+/*qca808x_start*/
+
+  typedef sw_error_t (*hsl_dev_reset) (a_uint32_t dev_id);
+
+  typedef sw_error_t (*hsl_dev_clean) (a_uint32_t dev_id);
+
+  typedef sw_error_t
+    (*hsl_dev_access_set) (a_uint32_t dev_id, hsl_access_mode mode);
+/*qca808x_end*/
+
+  /* LED */
+#define LED_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_led_ctrl_pattern_set) (a_uint32_t dev_id, led_pattern_group_t group,
+				 led_pattern_id_t id,
+				 led_ctrl_pattern_t * pattern);
+
+  typedef sw_error_t
+    (*hsl_led_ctrl_pattern_get) (a_uint32_t dev_id, led_pattern_group_t group,
+				 led_pattern_id_t id,
+				 led_ctrl_pattern_t * pattern);
+
+  typedef sw_error_t
+    (*hsl_led_ctrl_source_set) (a_uint32_t dev_id, a_uint32_t source_id,
+				 led_ctrl_pattern_t * pattern);
+
+  /* CoSMAP */
+#define COSMAP_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_cosmap_dscp_to_pri_set) (a_uint32_t dev_id, a_uint32_t dscp,
+				   a_uint32_t pri);
+
+  typedef sw_error_t
+    (*hsl_cosmap_dscp_to_pri_get) (a_uint32_t dev_id, a_uint32_t dscp,
+				   a_uint32_t * pri);
+
+  typedef sw_error_t
+    (*hsl_cosmap_dscp_to_dp_set) (a_uint32_t dev_id, a_uint32_t dscp,
+				  a_uint32_t dp);
+
+  typedef sw_error_t
+    (*hsl_cosmap_dscp_to_dp_get) (a_uint32_t dev_id, a_uint32_t dscp,
+				  a_uint32_t * dp);
+
+  typedef sw_error_t
+    (*hsl_cosmap_up_to_pri_set) (a_uint32_t dev_id, a_uint32_t up,
+				 a_uint32_t pri);
+
+  typedef sw_error_t
+    (*hsl_cosmap_up_to_pri_get) (a_uint32_t dev_id, a_uint32_t up,
+				 a_uint32_t * pri);
+
+  typedef sw_error_t
+    (*hsl_cosmap_up_to_dp_set) (a_uint32_t dev_id, a_uint32_t up,
+				a_uint32_t dp);
+
+  typedef sw_error_t
+    (*hsl_cosmap_up_to_dp_get) (a_uint32_t dev_id, a_uint32_t up,
+				a_uint32_t * dp);
+
+  typedef sw_error_t
+    (*hsl_cosmap_dscp_to_ehpri_set) (a_uint32_t dev_id, a_uint32_t dscp,
+				     a_uint32_t pri);
+
+  typedef sw_error_t
+    (*hsl_cosmap_dscp_to_ehpri_get) (a_uint32_t dev_id, a_uint32_t dscp,
+				     a_uint32_t * pri);
+
+  typedef sw_error_t
+    (*hsl_cosmap_dscp_to_ehdp_set) (a_uint32_t dev_id, a_uint32_t dscp,
+				    a_uint32_t dp);
+
+  typedef sw_error_t
+    (*hsl_cosmap_dscp_to_ehdp_get) (a_uint32_t dev_id, a_uint32_t dscp,
+				    a_uint32_t * dp);
+
+  typedef sw_error_t
+    (*hsl_cosmap_up_to_ehpri_set) (a_uint32_t dev_id, a_uint32_t up,
+				   a_uint32_t pri);
+
+  typedef sw_error_t
+    (*hsl_cosmap_up_to_ehpri_get) (a_uint32_t dev_id, a_uint32_t up,
+				   a_uint32_t * pri);
+
+  typedef sw_error_t
+    (*hsl_cosmap_up_to_ehdp_set) (a_uint32_t dev_id, a_uint32_t up,
+				  a_uint32_t dp);
+
+  typedef sw_error_t
+    (*hsl_cosmap_up_to_ehdp_get) (a_uint32_t dev_id, a_uint32_t up,
+				  a_uint32_t * dp);
+
+  typedef sw_error_t
+    (*hsl_cosmap_pri_to_queue_set) (a_uint32_t dev_id, a_uint32_t pri,
+				    a_uint32_t queue);
+
+  typedef sw_error_t
+    (*hsl_cosmap_pri_to_queue_get) (a_uint32_t dev_id, a_uint32_t pri,
+				    a_uint32_t * queue);
+
+  typedef sw_error_t
+    (*hsl_cosmap_pri_to_ehqueue_set) (a_uint32_t dev_id, a_uint32_t pri,
+				      a_uint32_t queue);
+
+  typedef sw_error_t
+    (*hsl_cosmap_pri_to_ehqueue_get) (a_uint32_t dev_id, a_uint32_t pri,
+				      a_uint32_t * queue);
+
+  typedef sw_error_t
+    (*hsl_cosmap_egress_remark_set) (a_uint32_t dev_id, a_uint32_t tbl_id,
+				     fal_egress_remark_table_t * tbl);
+
+  typedef sw_error_t
+    (*hsl_cosmap_egress_remark_get) (a_uint32_t dev_id, a_uint32_t tbl_id,
+				     fal_egress_remark_table_t * tbl);
+
+
+  /* IP */
+#define IP_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_ip_host_add) (a_uint32_t dev_id, fal_host_entry_t * host_entry);
+
+  typedef sw_error_t
+    (*hsl_ip_host_del) (a_uint32_t dev_id, a_uint32_t del_mode,
+			fal_host_entry_t * host_entry);
+
+  typedef sw_error_t
+    (*hsl_ip_host_get) (a_uint32_t dev_id, a_uint32_t get_mode,
+			fal_host_entry_t * host_entry);
+
+  typedef sw_error_t
+    (*hsl_ip_host_next) (a_uint32_t dev_id, a_uint32_t next_mode,
+			 fal_host_entry_t * host_entry);
+
+  typedef sw_error_t
+    (*hsl_ip_host_counter_bind) (a_uint32_t dev_id, a_uint32_t entry_id,
+				 a_uint32_t cnt_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_ip_host_pppoe_bind) (a_uint32_t dev_id, a_uint32_t entry_id,
+			       a_uint32_t pppoe_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_ip_pt_arp_learn_set) (a_uint32_t dev_id, fal_port_t port_id,
+				a_uint32_t flags);
+
+  typedef sw_error_t
+    (*hsl_ip_pt_arp_learn_get) (a_uint32_t dev_id, fal_port_t port_id,
+				a_uint32_t * flags);
+
+  typedef sw_error_t
+    (*hsl_ip_arp_learn_set) (a_uint32_t dev_id, fal_arp_learn_mode_t mode);
+
+  typedef sw_error_t
+    (*hsl_ip_arp_learn_get) (a_uint32_t dev_id, fal_arp_learn_mode_t * mode);
+
+  typedef sw_error_t
+    (*hsl_ip_source_guard_set) (a_uint32_t dev_id, fal_port_t port_id,
+				fal_source_guard_mode_t mode);
+
+  typedef sw_error_t
+    (*hsl_ip_source_guard_get) (a_uint32_t dev_id, fal_port_t port_id,
+				fal_source_guard_mode_t * mode);
+
+  typedef sw_error_t
+    (*hsl_ip_unk_source_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+  typedef sw_error_t
+    (*hsl_ip_unk_source_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+  typedef sw_error_t
+    (*hsl_ip_arp_guard_set) (a_uint32_t dev_id, fal_port_t port_id,
+			     fal_source_guard_mode_t mode);
+
+  typedef sw_error_t
+    (*hsl_ip_arp_guard_get) (a_uint32_t dev_id, fal_port_t port_id,
+			     fal_source_guard_mode_t * mode);
+
+  typedef sw_error_t
+    (*hsl_arp_unk_source_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+  typedef sw_error_t
+    (*hsl_arp_unk_source_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+  typedef sw_error_t
+    (*hsl_ip_route_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_ip_route_status_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_ip_intf_entry_add) (a_uint32_t dev_id,
+			      fal_intf_mac_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_ip_intf_entry_del) (a_uint32_t dev_id, a_uint32_t del_mode,
+			      fal_intf_mac_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_ip_intf_entry_next) (a_uint32_t dev_id, a_uint32_t next_mode,
+			       fal_intf_mac_entry_t * entry);
+
+  typedef sw_error_t
+    (*hsl_ip_age_time_set) (a_uint32_t dev_id, a_uint32_t * time);
+
+  typedef sw_error_t
+    (*hsl_ip_age_time_get) (a_uint32_t dev_id, a_uint32_t * time);
+
+  typedef sw_error_t
+    (*hsl_ip_wcmp_hash_mode_set) (a_uint32_t dev_id, a_uint32_t hash_mode);
+
+  typedef sw_error_t
+    (*hsl_ip_wcmp_hash_mode_get) (a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+  typedef sw_error_t
+    (*hsl_ip_vrf_base_addr_set) (a_uint32_t dev_id,
+				 a_uint32_t vrf_id, fal_ip4_addr_t addr);
+
+  typedef sw_error_t
+    (*hsl_ip_vrf_base_addr_get) (a_uint32_t dev_id,
+				 a_uint32_t vrf_id, fal_ip4_addr_t * addr);
+
+  typedef sw_error_t
+    (*hsl_ip_vrf_base_mask_set) (a_uint32_t dev_id,
+				 a_uint32_t vrf_id, fal_ip4_addr_t addr);
+
+  typedef sw_error_t
+    (*hsl_ip_vrf_base_mask_get) (a_uint32_t dev_id,
+				 a_uint32_t vrf_id, fal_ip4_addr_t * addr);
+
+  typedef sw_error_t
+    (*hsl_ip_default_route_set) (a_uint32_t dev_id,
+				 a_uint32_t droute_id,
+				 fal_default_route_t * entry);
+
+  typedef sw_error_t
+    (*hsl_ip_default_route_get) (a_uint32_t dev_id,
+				 a_uint32_t droute_id,
+				 fal_default_route_t * entry);
+
+  typedef sw_error_t
+    (*hsl_ip_host_route_set) (a_uint32_t dev_id,
+			      a_uint32_t hroute_id, fal_host_route_t * entry);
+
+  typedef sw_error_t
+    (*hsl_ip_host_route_get) (a_uint32_t dev_id,
+			      a_uint32_t hroute_id, fal_host_route_t * entry);
+
+  typedef sw_error_t
+    (*hsl_ip_wcmp_entry_set) (a_uint32_t dev_id,
+			      a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+
+  typedef sw_error_t
+    (*hsl_ip_wcmp_entry_get) (a_uint32_t dev_id,
+			      a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+  typedef sw_error_t
+    (*hsl_ip_rfs_ip4_set) (a_uint32_t dev_id, fal_ip4_rfs_t * rfs);
+
+  typedef sw_error_t
+    (*hsl_ip_rfs_ip6_set) (a_uint32_t dev_id, fal_ip6_rfs_t * rfs);
+  typedef sw_error_t
+    (*hsl_ip_rfs_ip4_del) (a_uint32_t dev_id, fal_ip4_rfs_t * rfs);
+
+  typedef sw_error_t
+    (*hsl_ip_rfs_ip6_del) (a_uint32_t dev_id, fal_ip6_rfs_t * rfs);
+
+  typedef sw_error_t
+    (*hsl_default_flow_cmd_set) (a_uint32_t dev_id,
+				 a_uint32_t vrf_id, fal_flow_type_t type,
+				 fal_default_flow_cmd_t cmd);
+
+  typedef sw_error_t
+    (*hsl_default_flow_cmd_get) (a_uint32_t dev_id,
+				 a_uint32_t vrf_id, fal_flow_type_t type,
+				 fal_default_flow_cmd_t * cmd);
+
+  typedef sw_error_t
+    (*hsl_default_rt_flow_cmd_set) (a_uint32_t dev_id,
+				    a_uint32_t vrf_id, fal_flow_type_t type,
+				    fal_default_flow_cmd_t cmd);
+
+  typedef sw_error_t
+    (*hsl_default_rt_flow_cmd_get) (a_uint32_t dev_id,
+				    a_uint32_t vrf_id, fal_flow_type_t type,
+				    fal_default_flow_cmd_t * cmd);
+
+typedef sw_error_t
+	(*hsl_ip_glb_lock_time_set) (a_uint32_t dev_id, fal_glb_lock_time_t lock_time);
+
+  /* NAT */
+#define NAT_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_nat_add) (a_uint32_t dev_id, fal_nat_entry_t * nat_entry);
+
+  typedef sw_error_t
+    (*hsl_nat_del) (a_uint32_t dev_id, a_uint32_t del_mode,
+		    fal_nat_entry_t * nat_entry);
+
+  typedef sw_error_t
+    (*hsl_nat_get) (a_uint32_t dev_id, a_uint32_t get_mode,
+		    fal_nat_entry_t * nat_entry);
+
+  typedef sw_error_t
+    (*hsl_nat_next) (a_uint32_t dev_id, a_uint32_t next_mode,
+		     fal_nat_entry_t * nat_entry);
+
+  typedef sw_error_t
+    (*hsl_nat_counter_bind) (a_uint32_t dev_id, a_uint32_t entry_id,
+			     a_uint32_t cnt_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_napt_add) (a_uint32_t dev_id, fal_napt_entry_t * napt_entry);
+
+  typedef sw_error_t
+    (*hsl_napt_del) (a_uint32_t dev_id, a_uint32_t del_mode,
+		     fal_napt_entry_t * napt_entry);
+
+  typedef sw_error_t
+    (*hsl_napt_get) (a_uint32_t dev_id, a_uint32_t get_mode,
+		     fal_napt_entry_t * napt_entry);
+
+  typedef sw_error_t
+    (*hsl_napt_next) (a_uint32_t dev_id, a_uint32_t next_mode,
+		      fal_napt_entry_t * napt_entry);
+
+  typedef sw_error_t
+    (*hsl_napt_counter_bind) (a_uint32_t dev_id, a_uint32_t entry_id,
+			      a_uint32_t cnt_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_nat_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_nat_status_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_nat_hash_mode_set) (a_uint32_t dev_id, a_uint32_t mode);
+
+  typedef sw_error_t
+    (*hsl_nat_hash_mode_get) (a_uint32_t dev_id, a_uint32_t * mode);
+
+  typedef sw_error_t
+    (*hsl_napt_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_napt_status_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_napt_mode_set) (a_uint32_t dev_id, fal_napt_mode_t mode);
+
+  typedef sw_error_t
+    (*hsl_napt_mode_get) (a_uint32_t dev_id, fal_napt_mode_t * mode);
+
+  typedef sw_error_t
+    (*hsl_nat_prv_base_addr_set) (a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+  typedef sw_error_t
+    (*hsl_nat_prv_base_addr_get) (a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+  typedef sw_error_t
+    (*hsl_nat_prv_base_mask_set) (a_uint32_t dev_id, fal_ip4_addr_t mask);
+
+  typedef sw_error_t
+    (*hsl_nat_prv_base_mask_get) (a_uint32_t dev_id, fal_ip4_addr_t * mask);
+
+  typedef sw_error_t
+    (*hsl_nat_prv_addr_mode_set) (a_uint32_t dev_id, a_bool_t map_en);
+
+  typedef sw_error_t
+    (*hsl_nat_prv_addr_mode_get) (a_uint32_t dev_id, a_bool_t * map_en);
+
+  typedef sw_error_t
+    (*hsl_nat_pub_addr_add) (a_uint32_t dev_id, fal_nat_pub_addr_t * entry);
+
+  typedef sw_error_t
+    (*hsl_nat_pub_addr_del) (a_uint32_t dev_id, a_uint32_t del_mode,
+			     fal_nat_pub_addr_t * entry);
+
+  typedef sw_error_t
+    (*hsl_nat_pub_addr_next) (a_uint32_t dev_id, a_uint32_t next_mode,
+			      fal_nat_pub_addr_t * entry);
+
+  typedef sw_error_t
+    (*hsl_nat_unk_session_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+  typedef sw_error_t
+    (*hsl_nat_unk_session_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+  typedef sw_error_t
+    (*hsl_nat_global_set) (a_uint32_t dev_id, a_bool_t enable, a_uint32_t portbmp);
+
+  typedef sw_error_t
+    (*hsl_flow_cookie_set) (a_uint32_t dev_id,
+			    fal_flow_cookie_t * flow_cookie);
+
+  typedef sw_error_t
+    (*hsl_flow_rfs_set) (a_uint32_t dev_id, a_uint8_t action,
+			 fal_flow_rfs_t * rfs);
+
+  /* SEC */
+#define SEC_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_sec_norm_item_set) (a_uint32_t dev_id, fal_norm_item_t item,
+			      void *value);
+
+  typedef sw_error_t
+    (*hsl_sec_norm_item_get) (a_uint32_t dev_id, fal_norm_item_t item,
+			      void *value);
+
+
+  /* Trunk */
+#define TRUNK_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_trunk_group_set) (a_uint32_t dev_id, a_uint32_t trunk_id,
+			    a_bool_t enable, fal_pbmp_t member);
+
+  typedef sw_error_t
+    (*hsl_trunk_group_get) (a_uint32_t dev_id, a_uint32_t trunk_id,
+			    a_bool_t * enable, fal_pbmp_t * member);
+
+  typedef sw_error_t
+    (*hsl_trunk_hash_mode_set) (a_uint32_t dev_id, a_uint32_t hash_mode);
+
+  typedef sw_error_t
+    (*hsl_trunk_hash_mode_get) (a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+  typedef sw_error_t
+    (*hsl_trunk_manipulate_sa_set) (a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+  typedef sw_error_t
+    (*hsl_trunk_manipulate_sa_get) (a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+  /* Interface Control */
+#define INTERFACE_CONTROL_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_interface_mac_mode_set) (a_uint32_t dev_id, fal_port_t port_id,
+				   fal_mac_config_t * config);
+
+  typedef sw_error_t
+    (*hsl_interface_mac_mode_get) (a_uint32_t dev_id, fal_port_t port_id,
+				   fal_mac_config_t * config);
+
+  typedef sw_error_t
+    (*hsl_port_3az_status_set) (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_port_3az_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_interface_phy_mode_set) (a_uint32_t dev_id, a_uint32_t phy_id,
+				   fal_phy_config_t * config);
+
+  typedef sw_error_t
+    (*hsl_interface_phy_mode_get) (a_uint32_t dev_id, a_uint32_t phy_id,
+				   fal_phy_config_t * config);
+
+  typedef sw_error_t
+    (*hsl_interface_fx100_ctrl_set) (a_uint32_t dev_id,
+				     fal_fx100_ctrl_config_t * config);
+
+  typedef sw_error_t
+    (*hsl_interface_fx100_ctrl_get) (a_uint32_t dev_id,
+				     fal_fx100_ctrl_config_t * config);
+
+  typedef sw_error_t
+    (*hsl_interface_fx100_status_get) (a_uint32_t dev_id,
+				       a_uint32_t * status);
+
+  typedef sw_error_t
+    (*hsl_interface_mac06_exch_set) (a_uint32_t dev_id, a_bool_t enable);
+
+  typedef sw_error_t
+    (*hsl_interface_mac06_exch_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+  typedef sw_error_t
+    (*hsl_interface_pad_get) (a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t *value);
+
+  typedef sw_error_t
+    (*hsl_interface_pad_set) (a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t value);
+
+  typedef sw_error_t
+    (*hsl_interface_sgmii_get) (a_uint32_t dev_id, a_uint32_t * value);
+
+  typedef sw_error_t
+    (*hsl_interface_sgmii_set) (a_uint32_t dev_id, a_uint32_t value);
+
+
+  /* REG */
+/*qca808x_start*/
+#define REG_FUNC_PROTOTYPE_DEF
+  typedef sw_error_t
+    (*hsl_phy_get) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
+		    a_uint16_t * value);
+
+  typedef sw_error_t
+    (*hsl_phy_set) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
+		    a_uint16_t value);
+/*qca808x_end*/
+  typedef sw_error_t
+    (*hsl_reg_get) (a_uint32_t dev_id, a_uint32_t reg_addr,
+		    a_uint8_t value[], a_uint32_t value_len);
+
+  typedef sw_error_t
+    (*hsl_reg_set) (a_uint32_t dev_id, a_uint32_t reg_addr,
+		    a_uint8_t value[], a_uint32_t value_len);
+
+  typedef sw_error_t
+    (*hsl_psgmii_reg_get) (a_uint32_t dev_id, a_uint32_t reg_addr,
+		    a_uint8_t *value, a_uint32_t value_len);
+
+  typedef sw_error_t
+    (*hsl_psgmii_reg_set) (a_uint32_t dev_id, a_uint32_t reg_addr,
+		    a_uint8_t *value, a_uint32_t value_len);
+
+  typedef sw_error_t
+    (*hsl_reg_field_get) (a_uint32_t dev_id, a_uint32_t reg_addr,
+			  a_uint32_t bit_offset, a_uint32_t field_len,
+			  a_uint8_t value[], a_uint32_t value_len);
+
+  typedef sw_error_t
+    (*hsl_reg_field_set) (a_uint32_t dev_id, a_uint32_t reg_addr,
+			  a_uint32_t bit_offset, a_uint32_t field_len,
+			  const a_uint8_t value[], a_uint32_t value_len);
+
+  typedef sw_error_t
+    (*hsl_reg_entries_get) (a_uint32_t dev_id, a_uint32_t reg_addr,
+			    a_uint32_t entry_len, a_uint8_t value[],
+			    a_uint32_t value_len);
+
+  typedef sw_error_t
+    (*hsl_reg_entries_set) (a_uint32_t dev_id, a_uint32_t reg_addr,
+			    a_uint32_t entry_len, const a_uint8_t value[],
+			    a_uint32_t value_len);
+
+  typedef sw_error_t
+    (*hsl_debug_psgmii_self_test) (a_uint32_t dev_id, a_bool_t enable,
+			    a_uint32_t times, a_uint32_t *result);
+  typedef sw_error_t
+    (*hsl_phy_dump)(a_uint32_t dev_id, a_uint32_t phy_addr,
+			a_uint32_t idx,fal_phy_dump_t *phy_dump);
+
+  typedef sw_error_t
+    (*hsl_uniphy_reg_get) (a_uint32_t dev_id, a_uint32_t index,
+		    a_uint32_t reg_addr, a_uint8_t value[], a_uint32_t value_len);
+
+  typedef sw_error_t
+    (*hsl_uniphy_reg_set) (a_uint32_t dev_id, a_uint32_t index,
+    a_uint32_t reg_addr, a_uint8_t value[], a_uint32_t value_len);
+/*qca808x_start*/
+
+  typedef struct
+  {
+/*qca808x_end*/
+#if (!(defined(USER_MODE) && defined(KERNEL_MODULE)))
+#ifndef HSL_STANDALONG
+
+    /* Misc */
+    hsl_arp_status_set arp_status_set;
+    hsl_arp_status_get arp_status_get;
+    hsl_frame_max_size_set frame_max_size_set;
+    hsl_frame_max_size_get frame_max_size_get;
+    hsl_port_unk_sa_cmd_set port_unk_sa_cmd_set;
+    hsl_port_unk_sa_cmd_get port_unk_sa_cmd_get;
+    hsl_port_unk_uc_filter_set port_unk_uc_filter_set;
+    hsl_port_unk_uc_filter_get port_unk_uc_filter_get;
+    hsl_port_unk_mc_filter_set port_unk_mc_filter_set;
+    hsl_port_unk_mc_filter_get port_unk_mc_filter_get;
+    hsl_port_bc_filter_set port_bc_filter_set;
+    hsl_port_bc_filter_get port_bc_filter_get;
+    hsl_nestvlan_tpid_set nestvlan_tpid_set;
+    hsl_nestvlan_tpid_get nestvlan_tpid_get;
+    hsl_cpu_port_status_set cpu_port_status_set;
+    hsl_cpu_port_status_get cpu_port_status_get;
+    hsl_bc_to_cpu_port_set bc_to_cpu_port_set;
+    hsl_bc_to_cpu_port_get bc_to_cpu_port_get;
+    hsl_pppoe_cmd_set pppoe_cmd_set;
+    hsl_pppoe_cmd_get pppoe_cmd_get;
+    hsl_pppoe_status_set pppoe_status_set;
+    hsl_pppoe_status_get pppoe_status_get;
+    hsl_port_dhcp_set port_dhcp_set;
+    hsl_port_dhcp_get port_dhcp_get;
+    hsl_arp_cmd_set arp_cmd_set;
+    hsl_arp_cmd_get arp_cmd_get;
+    hsl_eapol_cmd_set eapol_cmd_set;
+    hsl_eapol_cmd_get eapol_cmd_get;
+    hsl_pppoe_session_add pppoe_session_add;
+    hsl_pppoe_session_del pppoe_session_del;
+    hsl_pppoe_session_get pppoe_session_get;
+    hsl_eapol_status_set eapol_status_set;
+    hsl_eapol_status_get eapol_status_get;
+    hsl_ripv1_status_set ripv1_status_set;
+    hsl_ripv1_status_get ripv1_status_get;
+    hsl_port_arp_req_status_set port_arp_req_status_set;
+    hsl_port_arp_req_status_get port_arp_req_status_get;
+    hsl_port_arp_ack_status_set port_arp_ack_status_set;
+    hsl_port_arp_ack_status_get port_arp_ack_status_get;
+    hsl_pppoe_session_table_add pppoe_session_table_add;
+    hsl_pppoe_session_table_del pppoe_session_table_del;
+    hsl_pppoe_session_table_get pppoe_session_table_get;
+    hsl_pppoe_session_id_set pppoe_session_id_set;
+    hsl_pppoe_session_id_get pppoe_session_id_get;
+    hsl_intr_mask_set intr_mask_set;
+    hsl_intr_mask_get intr_mask_get;
+    hsl_intr_status_get intr_status_get;
+    hsl_intr_status_clear intr_status_clear;
+    hsl_intr_port_link_mask_set intr_port_link_mask_set;
+    hsl_intr_port_link_mask_get intr_port_link_mask_get;
+    hsl_intr_port_link_status_get intr_port_link_status_get;
+    hsl_intr_mask_mac_linkchg_set intr_mask_mac_linkchg_set;
+    hsl_intr_mask_mac_linkchg_get intr_mask_mac_linkchg_get;
+    hsl_intr_status_mac_linkchg_get intr_status_mac_linkchg_get;
+    hsl_cpu_vid_en_set cpu_vid_en_set;
+    hsl_cpu_vid_en_get cpu_vid_en_get;
+    hsl_rtd_pppoe_en_set rtd_pppoe_en_set;
+    hsl_rtd_pppoe_en_get rtd_pppoe_en_get;
+    hsl_intr_status_mac_linkchg_clear intr_status_mac_linkchg_clear;
+    hsl_global_macaddr_set global_macaddr_set;
+    hsl_global_macaddr_get global_macaddr_get;
+    hsl_lldp_status_set lldp_status_set;
+    hsl_lldp_status_get lldp_status_get;
+    hsl_frame_crc_reserve_set frame_crc_reserve_set;
+    hsl_frame_crc_reserve_get frame_crc_reserve_get;
+
+/*qca808x_start*/
+    /* Port control */
+    hsl_port_duplex_set port_duplex_set;
+    hsl_port_duplex_get port_duplex_get;
+    hsl_port_speed_set port_speed_set;
+    hsl_port_speed_get port_speed_get;
+    hsl_port_autoneg_status_get port_autoneg_status_get;
+    hsl_port_autoneg_enable port_autoneg_enable;
+    hsl_port_autoneg_restart port_autoneg_restart;
+    hsl_port_autoneg_adv_get port_autoneg_adv_get;
+    hsl_port_autoneg_adv_set port_autoneg_adv_set;
+/*qca808x_end*/
+    hsl_port_hdr_status_set port_hdr_status_set;
+    hsl_port_hdr_status_get port_hdr_status_get;
+/*qca808x_start*/
+    hsl_port_flowctrl_set port_flowctrl_set;
+    hsl_port_flowctrl_get port_flowctrl_get;
+/*qca808x_end*/
+	hsl_port_flowctrl_thresh_set port_flowctrl_thresh_set;
+    hsl_port_flowctrl_forcemode_set port_flowctrl_forcemode_set;
+    hsl_port_flowctrl_forcemode_get port_flowctrl_forcemode_get;
+/*qca808x_start*/
+    hsl_port_powersave_set port_powersave_set;
+    hsl_port_powersave_get port_powersave_get;
+    hsl_port_hibernate_set port_hibernate_set;
+    hsl_port_hibernate_get port_hibernate_get;
+    hsl_port_cdt port_cdt;
+/*qca808x_end*/
+    hsl_port_rxhdr_mode_set port_rxhdr_mode_set;
+    hsl_port_rxhdr_mode_get port_rxhdr_mode_get;
+    hsl_port_txhdr_mode_set port_txhdr_mode_set;
+    hsl_port_txhdr_mode_get port_txhdr_mode_get;
+    hsl_header_type_set header_type_set;
+    hsl_header_type_get header_type_get;
+    hsl_port_txmac_status_set port_txmac_status_set;
+    hsl_port_txmac_status_get port_txmac_status_get;
+    hsl_port_rxmac_status_set port_rxmac_status_set;
+    hsl_port_rxmac_status_get port_rxmac_status_get;
+    hsl_port_txfc_status_set port_txfc_status_set;
+    hsl_port_txfc_status_get port_txfc_status_get;
+    hsl_port_rxfc_status_set port_rxfc_status_set;
+    hsl_port_rxfc_status_get port_rxfc_status_get;
+    hsl_port_bp_status_set port_bp_status_set;
+    hsl_port_bp_status_get port_bp_status_get;
+    hsl_port_link_forcemode_set port_link_forcemode_set;
+    hsl_port_link_forcemode_get port_link_forcemode_get;
+/*qca808x_start*/
+    hsl_port_link_status_get port_link_status_get;
+    hsl_ports_link_status_get ports_link_status_get;
+/*qca808x_end*/
+    hsl_port_mac_loopback_set port_mac_loopback_set;
+    hsl_port_mac_loopback_get port_mac_loopback_get;
+    hsl_port_congestion_drop_set port_congestion_drop_set;
+    hsl_port_congestion_drop_get port_congestion_drop_get;
+    hsl_ring_flow_ctrl_thres_set ring_flow_ctrl_thres_set;
+    hsl_ring_flow_ctrl_thres_get ring_flow_ctrl_thres_get;
+/*qca808x_start*/
+    hsl_port_8023az_set port_8023az_set;
+    hsl_port_8023az_get port_8023az_get;
+    hsl_port_mdix_set port_mdix_set;
+    hsl_port_mdix_get port_mdix_get;
+    hsl_port_mdix_status_get port_mdix_status_get;
+/*qca808x_end*/
+    hsl_port_combo_prefer_medium_set port_combo_prefer_medium_set;
+    hsl_port_combo_prefer_medium_get port_combo_prefer_medium_get;
+    hsl_port_combo_medium_status_get port_combo_medium_status_get;
+    hsl_port_combo_fiber_mode_set port_combo_fiber_mode_set;
+    hsl_port_combo_fiber_mode_get port_combo_fiber_mode_get;
+/*qca808x_start*/
+    hsl_port_local_loopback_set port_local_loopback_set;
+    hsl_port_local_loopback_get port_local_loopback_get;
+    hsl_port_remote_loopback_set port_remote_loopback_set;
+    hsl_port_remote_loopback_get port_remote_loopback_get;
+    hsl_port_reset port_reset;
+    hsl_port_power_off port_power_off;
+    hsl_port_power_on port_power_on;
+    hsl_port_phy_id_get port_phy_id_get;
+    hsl_port_wol_status_set port_wol_status_set;
+    hsl_port_wol_status_get port_wol_status_get;
+    hsl_port_magic_frame_mac_set port_magic_frame_mac_set;
+    hsl_port_magic_frame_mac_get port_magic_frame_mac_get;
+/*qca808x_end*/
+    hsl_port_interface_mode_set port_interface_mode_set;
+    hsl_port_interface_mode_get port_interface_mode_get;
+    hsl_port_interface_mode_apply port_interface_mode_apply;
+/*qca808x_start*/
+    hsl_port_interface_mode_status_get port_interface_mode_status_get;
+    hsl_port_counter_set port_counter_set;
+    hsl_port_counter_get port_counter_get;
+    hsl_port_counter_show port_counter_show;
+/*qca808x_end*/
+
+    /* VLAN */
+    hsl_vlan_entry_append vlan_entry_append;
+    hsl_vlan_create vlan_creat;
+    hsl_vlan_member_update vlan_member_update;
+    hsl_vlan_delete vlan_delete;
+    hsl_vlan_find vlan_find;
+    hsl_vlan_next vlan_next;
+    hsl_vlan_flush vlan_flush;
+    hsl_vlan_fid_set vlan_fid_set;
+    hsl_vlan_fid_get vlan_fid_get;
+    hsl_vlan_member_add vlan_member_add;
+    hsl_vlan_member_del vlan_member_del;
+    hsl_vlan_learning_state_set vlan_learning_state_set;
+    hsl_vlan_learning_state_get vlan_learning_state_get;
+
+    /* Port VLAN */
+    hsl_port_1qmode_set port_1qmode_set;
+    hsl_port_1qmode_get port_1qmode_get;
+    hsl_port_egvlanmode_get port_egvlanmode_get;
+    hsl_port_egvlanmode_set port_egvlanmode_set;
+    hsl_portvlan_member_add portvlan_member_add;
+    hsl_portvlan_member_del portvlan_member_del;
+    hsl_portvlan_member_update portvlan_member_update;
+    hsl_portvlan_member_get portvlan_member_get;
+    hsl_port_default_vid_set port_default_vid_set;
+    hsl_port_default_vid_get port_default_vid_get;
+    hsl_port_force_default_vid_set port_force_default_vid_set;
+    hsl_port_force_default_vid_get port_force_default_vid_get;
+    hsl_port_force_portvlan_set port_force_portvlan_set;
+    hsl_port_force_portvlan_get port_force_portvlan_get;
+    hsl_port_nestvlan_set port_nestvlan_set;
+    hsl_port_nestvlan_get port_nestvlan_get;
+    hsl_port_invlan_mode_set port_invlan_mode_set;
+    hsl_port_invlan_mode_get port_invlan_mode_get;
+    hsl_port_tls_set port_tls_set;
+    hsl_port_tls_get port_tls_get;
+    hsl_port_pri_propagation_set port_pri_propagation_set;
+    hsl_port_pri_propagation_get port_pri_propagation_get;
+    hsl_port_default_svid_set port_default_svid_set;
+    hsl_port_default_svid_get port_default_svid_get;
+    hsl_port_default_cvid_set port_default_cvid_set;
+    hsl_port_default_cvid_get port_default_cvid_get;
+    hsl_port_vlan_propagation_set port_vlan_propagation_set;
+    hsl_port_vlan_propagation_get port_vlan_propagation_get;
+    hsl_port_vlan_trans_add port_vlan_trans_add;
+    hsl_port_vlan_trans_del port_vlan_trans_del;
+    hsl_port_vlan_trans_get port_vlan_trans_get;
+    hsl_qinq_mode_set qinq_mode_set;
+    hsl_qinq_mode_get qinq_mode_get;
+    hsl_port_qinq_role_set port_qinq_role_set;
+    hsl_port_qinq_role_get port_qinq_role_get;
+    hsl_port_vlan_trans_iterate port_vlan_trans_iterate;
+    hsl_port_mac_vlan_xlt_set port_mac_vlan_xlt_set;
+    hsl_port_mac_vlan_xlt_get port_mac_vlan_xlt_get;
+    hsl_netisolate_set netisolate_set;
+    hsl_netisolate_get netisolate_get;
+    hsl_eg_trans_filter_bypass_en_set eg_trans_filter_bypass_en_set;
+    hsl_eg_trans_filter_bypass_en_get eg_trans_filter_bypass_en_get;
+    hsl_port_vrf_id_set port_vrf_id_set;
+    hsl_port_vrf_id_get port_vrf_id_get;
+
+    /* FDB */
+    hsl_fdb_add fdb_add;
+    hsl_fdb_del_all fdb_del_all;
+    hsl_fdb_del_by_port fdb_del_by_port;
+    hsl_fdb_del_by_mac fdb_del_by_mac;
+    hsl_fdb_first fdb_first;
+    hsl_fdb_next fdb_next;
+    hsl_fdb_find fdb_find;
+    hsl_fdb_port_learn_set port_learn_set;
+    hsl_fdb_port_learn_get port_learn_get;
+    hsl_fdb_age_ctrl_set age_ctrl_set;
+    hsl_fdb_age_ctrl_get age_ctrl_get;
+    hsl_fdb_vlan_ivl_svl_set vlan_ivl_svl_set;
+    hsl_fdb_vlan_ivl_svl_get vlan_ivl_svl_get;
+    hsl_fdb_age_time_set age_time_set;
+    hsl_fdb_age_time_get age_time_get;
+    hsl_fdb_iterate fdb_iterate;
+    hsl_fdb_extend_next fdb_extend_next;
+    hsl_fdb_extend_first fdb_extend_first;
+    hsl_fdb_transfer fdb_transfer;
+    hsl_port_fdb_learn_limit_set port_fdb_learn_limit_set;
+    hsl_port_fdb_learn_limit_get port_fdb_learn_limit_get;
+    hsl_port_fdb_learn_exceed_cmd_set port_fdb_learn_exceed_cmd_set;
+    hsl_port_fdb_learn_exceed_cmd_get port_fdb_learn_exceed_cmd_get;
+    hsl_fdb_learn_limit_set fdb_learn_limit_set;
+    hsl_fdb_learn_limit_get fdb_learn_limit_get;
+    hsl_fdb_learn_exceed_cmd_set fdb_learn_exceed_cmd_set;
+    hsl_fdb_learn_exceed_cmd_get fdb_learn_exceed_cmd_get;
+    hsl_fdb_resv_add fdb_resv_add;
+    hsl_fdb_resv_del fdb_resv_del;
+    hsl_fdb_resv_find fdb_resv_find;
+    hsl_fdb_resv_iterate fdb_resv_iterate;
+    hsl_fdb_port_learn_static_set fdb_port_learn_static_set;
+    hsl_fdb_port_learn_static_get fdb_port_learn_static_get;
+    hsl_fdb_port_add fdb_port_add;
+    hsl_fdb_port_del fdb_port_del;
+    hsl_fdb_rfs_set fdb_rfs_set;
+    hsl_fdb_rfs_del fdb_rfs_del;
+
+    /* QOS */
+    hsl_qos_sch_mode_set qos_sch_mode_set;
+    hsl_qos_sch_mode_get qos_sch_mode_get;
+    hsl_qos_queue_tx_buf_status_set qos_queue_tx_buf_status_set;
+    hsl_qos_queue_tx_buf_status_get qos_queue_tx_buf_status_get;
+    hsl_qos_port_tx_buf_status_set qos_port_tx_buf_status_set;
+    hsl_qos_port_tx_buf_status_get qos_port_tx_buf_status_get;
+    hsl_qos_port_red_en_set qos_port_red_en_set;
+    hsl_qos_port_red_en_get qos_port_red_en_get;
+    hsl_qos_queue_tx_buf_nr_set qos_queue_tx_buf_nr_set;
+    hsl_qos_queue_tx_buf_nr_get qos_queue_tx_buf_nr_get;
+    hsl_qos_port_tx_buf_nr_set qos_port_tx_buf_nr_set;
+    hsl_qos_port_tx_buf_nr_get qos_port_tx_buf_nr_get;
+    hsl_qos_port_rx_buf_nr_set qos_port_rx_buf_nr_set;
+    hsl_qos_port_rx_buf_nr_get qos_port_rx_buf_nr_get;
+    hsl_cosmap_up_queue_set cosmap_up_queue_set;
+    hsl_cosmap_up_queue_get cosmap_up_queue_get;
+    hsl_cosmap_dscp_queue_set cosmap_dscp_queue_set;
+    hsl_cosmap_dscp_queue_get cosmap_dscp_queue_get;
+    hsl_qos_port_mode_set qos_port_mode_set;
+    hsl_qos_port_mode_get qos_port_mode_get;
+    hsl_qos_port_mode_pri_set qos_port_mode_pri_set;
+    hsl_qos_port_mode_pri_get qos_port_mode_pri_get;
+    hsl_qos_port_default_up_set qos_port_default_up_set;
+    hsl_qos_port_default_up_get qos_port_default_up_get;
+    hsl_qos_port_sch_mode_set qos_port_sch_mode_set;
+    hsl_qos_port_sch_mode_get qos_port_sch_mode_get;
+    hsl_qos_port_default_spri_set qos_port_default_spri_set;
+    hsl_qos_port_default_spri_get qos_port_default_spri_get;
+    hsl_qos_port_default_cpri_set qos_port_default_cpri_set;
+    hsl_qos_port_default_cpri_get qos_port_default_cpri_get;
+    hsl_qos_port_force_spri_status_set qos_port_force_spri_status_set;
+    hsl_qos_port_force_spri_status_get qos_port_force_spri_status_get;
+    hsl_qos_port_force_cpri_status_set qos_port_force_cpri_status_set;
+    hsl_qos_port_force_cpri_status_get qos_port_force_cpri_status_get;
+
+    hsl_qos_queue_remark_table_set qos_queue_remark_table_set;
+    hsl_qos_queue_remark_table_get qos_queue_remark_table_get;
+    hsl_port_static_thresh_get port_static_thresh_get;
+    hsl_port_static_thresh_set port_static_thresh_set;
+
+    /* Rate */
+    hsl_storm_ctrl_frame_set storm_ctrl_frame_set;
+    hsl_storm_ctrl_frame_get storm_ctrl_frame_get;
+    hsl_storm_ctrl_rate_set storm_ctrl_rate_set;
+    hsl_storm_ctrl_rate_get storm_ctrl_rate_get;
+    hsl_rate_queue_egrl_set rate_queue_egrl_set;
+    hsl_rate_queue_egrl_get rate_queue_egrl_get;
+    hsl_rate_port_egrl_set rate_port_egrl_set;
+    hsl_rate_port_egrl_get rate_port_egrl_get;
+    hsl_rate_port_inrl_set rate_port_inrl_set;
+    hsl_rate_port_inrl_get rate_port_inrl_get;
+    hsl_rate_port_policer_set rate_port_policer_set;
+    hsl_rate_port_policer_get rate_port_policer_get;
+    hsl_rate_port_shaper_set rate_port_shaper_set;
+    hsl_rate_port_shaper_get rate_port_shaper_get;
+    hsl_rate_queue_shaper_set rate_queue_shaper_set;
+    hsl_rate_queue_shaper_get rate_queue_shaper_get;
+    hsl_rate_acl_policer_set rate_acl_policer_set;
+    hsl_rate_acl_policer_get rate_acl_policer_get;
+    hsl_rate_port_add_rate_byte_set rate_port_add_rate_byte_set;
+    hsl_rate_port_add_rate_byte_get rate_port_add_rate_byte_get;
+    hsl_rate_port_gol_flow_en_set rate_port_gol_flow_en_set;
+    hsl_rate_port_gol_flow_en_get rate_port_gol_flow_en_get;
+
+    /* Mirror */
+    hsl_mirr_analysis_port_set mirr_analysis_port_set;
+    hsl_mirr_analysis_port_get mirr_analysis_port_get;
+    hsl_mirr_port_in_set mirr_port_in_set;
+    hsl_mirr_port_in_get mirr_port_in_get;
+    hsl_mirr_port_eg_set mirr_port_eg_set;
+    hsl_mirr_port_eg_get mirr_port_eg_get;
+
+    /* Stp */
+    hsl_stp_port_state_set stp_port_state_set;
+    hsl_stp_port_state_get stp_port_state_get;
+
+    /* IGMP */
+    hsl_port_igmps_status_set port_igmps_status_set;
+    hsl_port_igmps_status_get port_igmps_status_get;
+    hsl_igmp_mld_cmd_set igmp_mld_cmd_set;
+    hsl_igmp_mld_cmd_get igmp_mld_cmd_get;
+    hsl_port_igmp_join_set port_igmp_join_set;
+    hsl_port_igmp_join_get port_igmp_join_get;
+    hsl_port_igmp_leave_set port_igmp_leave_set;
+    hsl_port_igmp_leave_get port_igmp_leave_get;
+    hsl_igmp_rp_set igmp_rp_set;
+    hsl_igmp_rp_get igmp_rp_get;
+    hsl_igmp_entry_creat_set igmp_entry_creat_set;
+    hsl_igmp_entry_creat_get igmp_entry_creat_get;
+    hsl_igmp_entry_static_set igmp_entry_static_set;
+    hsl_igmp_entry_static_get igmp_entry_static_get;
+    hsl_igmp_entry_leaky_set igmp_entry_leaky_set;
+    hsl_igmp_entry_leaky_get igmp_entry_leaky_get;
+    hsl_igmp_entry_v3_set igmp_entry_v3_set;
+    hsl_igmp_entry_v3_get igmp_entry_v3_get;
+    hsl_igmp_entry_queue_set igmp_entry_queue_set;
+    hsl_igmp_entry_queue_get igmp_entry_queue_get;
+    hsl_port_igmp_mld_learn_limit_set port_igmp_mld_learn_limit_set;
+    hsl_port_igmp_mld_learn_limit_get port_igmp_mld_learn_limit_get;
+    hsl_port_igmp_mld_learn_exceed_cmd_set port_igmp_mld_learn_exceed_cmd_set;
+    hsl_port_igmp_mld_learn_exceed_cmd_get port_igmp_mld_learn_exceed_cmd_get;
+    hsl_igmp_sg_entry_set igmp_sg_entry_set;
+    hsl_igmp_sg_entry_clear igmp_sg_entry_clear;
+    hsl_igmp_sg_entry_show igmp_sg_entry_show;
+    hsl_igmp_sg_entry_query igmp_sg_entry_query;
+
+    /* Leaky */
+    hsl_uc_leaky_mode_set uc_leaky_mode_set;
+    hsl_uc_leaky_mode_get uc_leaky_mode_get;
+    hsl_mc_leaky_mode_set mc_leaky_mode_set;
+    hsl_mc_leaky_mode_get mc_leaky_mode_get;
+    hsl_port_arp_leaky_set port_arp_leaky_set;
+    hsl_port_arp_leaky_get port_arp_leaky_get;
+    hsl_port_uc_leaky_set port_uc_leaky_set;
+    hsl_port_uc_leaky_get port_uc_leaky_get;
+    hsl_port_mc_leaky_set port_mc_leaky_set;
+    hsl_port_mc_leaky_get port_mc_leaky_get;
+
+    /* MIB API */
+    hsl_get_mib_info get_mib_info;
+    hsl_get_rx_mib_info get_rx_mib_info;
+    hsl_get_tx_mib_info get_tx_mib_info;
+    hsl_mib_status_set mib_status_set;
+    hsl_mib_status_get mib_status_get;
+    hsl_mib_port_flush_counters mib_port_flush_counters;
+    hsl_mib_cpukeep_set mib_cpukeep_set;
+    hsl_mib_cpukeep_get mib_cpukeep_get;
+
+
+    /* Acl */
+    hsl_acl_list_creat acl_list_creat;
+    hsl_acl_list_destroy acl_list_destroy;
+    hsl_acl_rule_add acl_rule_add;
+    hsl_acl_rule_delete acl_rule_delete;
+    hsl_acl_rule_query acl_rule_query;
+    hsl_acl_list_bind acl_list_bind;
+    hsl_acl_list_unbind acl_list_unbind;
+    hsl_acl_status_set acl_status_set;
+    hsl_acl_status_get acl_status_get;
+    hsl_acl_list_dump acl_list_dump;
+    hsl_acl_rule_dump acl_rule_dump;
+    hsl_acl_port_udf_profile_set acl_port_udf_profile_set;
+    hsl_acl_port_udf_profile_get acl_port_udf_profile_get;
+    hsl_acl_rule_active acl_rule_active;
+    hsl_acl_rule_deactive acl_rule_deactive;
+    hsl_acl_rule_src_filter_sts_set acl_rule_src_filter_sts_set;
+    hsl_acl_rule_src_filter_sts_get acl_rule_src_filter_sts_get;
+    hsl_acl_rule_get_offset acl_rule_get_offset;
+    hsl_acl_rule_sync_multi_portmap acl_rule_sync_multi_portmap;
+
+    /* LED */
+    hsl_led_ctrl_pattern_set led_ctrl_pattern_set;
+    hsl_led_ctrl_pattern_get led_ctrl_pattern_get;
+    hsl_led_ctrl_source_set led_ctrl_source_set;
+
+    /* CoSMap */
+    hsl_cosmap_dscp_to_pri_set cosmap_dscp_to_pri_set;
+    hsl_cosmap_dscp_to_pri_get cosmap_dscp_to_pri_get;
+    hsl_cosmap_dscp_to_dp_set cosmap_dscp_to_dp_set;
+    hsl_cosmap_dscp_to_dp_get cosmap_dscp_to_dp_get;
+    hsl_cosmap_up_to_pri_set cosmap_up_to_pri_set;
+    hsl_cosmap_up_to_pri_get cosmap_up_to_pri_get;
+    hsl_cosmap_up_to_dp_set cosmap_up_to_dp_set;
+    hsl_cosmap_up_to_dp_get cosmap_up_to_dp_get;
+    hsl_cosmap_dscp_to_ehpri_set cosmap_dscp_to_ehpri_set;
+    hsl_cosmap_dscp_to_ehpri_get cosmap_dscp_to_ehpri_get;
+    hsl_cosmap_dscp_to_ehdp_set cosmap_dscp_to_ehdp_set;
+    hsl_cosmap_dscp_to_ehdp_get cosmap_dscp_to_ehdp_get;
+    hsl_cosmap_up_to_ehpri_set cosmap_up_to_ehpri_set;
+    hsl_cosmap_up_to_ehpri_get cosmap_up_to_ehpri_get;
+    hsl_cosmap_up_to_ehdp_set cosmap_up_to_ehdp_set;
+    hsl_cosmap_up_to_ehdp_get cosmap_up_to_ehdp_get;
+    hsl_cosmap_pri_to_queue_set cosmap_pri_to_queue_set;
+    hsl_cosmap_pri_to_queue_get cosmap_pri_to_queue_get;
+    hsl_cosmap_pri_to_ehqueue_set cosmap_pri_to_ehqueue_set;
+    hsl_cosmap_pri_to_ehqueue_get cosmap_pri_to_ehqueue_get;
+    hsl_cosmap_egress_remark_set cosmap_egress_remark_set;
+    hsl_cosmap_egress_remark_get cosmap_egress_remark_get;
+
+    /* IP */
+    hsl_ip_host_add ip_host_add;
+    hsl_ip_host_del ip_host_del;
+    hsl_ip_host_get ip_host_get;
+    hsl_ip_host_next ip_host_next;
+    hsl_ip_host_counter_bind ip_host_counter_bind;
+    hsl_ip_host_pppoe_bind ip_host_pppoe_bind;
+    hsl_ip_pt_arp_learn_set ip_pt_arp_learn_set;
+    hsl_ip_pt_arp_learn_get ip_pt_arp_learn_get;
+    hsl_ip_arp_learn_set ip_arp_learn_set;
+    hsl_ip_arp_learn_get ip_arp_learn_get;
+    hsl_ip_source_guard_set ip_source_guard_set;
+    hsl_ip_source_guard_get ip_source_guard_get;
+    hsl_ip_unk_source_cmd_set ip_unk_source_cmd_set;
+    hsl_ip_unk_source_cmd_get ip_unk_source_cmd_get;
+    hsl_ip_arp_guard_set ip_arp_guard_set;
+    hsl_ip_arp_guard_get ip_arp_guard_get;
+    hsl_arp_unk_source_cmd_set arp_unk_source_cmd_set;
+    hsl_arp_unk_source_cmd_get arp_unk_source_cmd_get;
+    hsl_ip_route_status_set ip_route_status_set;
+    hsl_ip_route_status_get ip_route_status_get;
+    hsl_ip_intf_entry_add ip_intf_entry_add;
+    hsl_ip_intf_entry_del ip_intf_entry_del;
+    hsl_ip_intf_entry_next ip_intf_entry_next;
+    hsl_ip_age_time_set ip_age_time_set;
+    hsl_ip_age_time_get ip_age_time_get;
+    hsl_ip_wcmp_hash_mode_set ip_wcmp_hash_mode_set;
+    hsl_ip_wcmp_hash_mode_get ip_wcmp_hash_mode_get;
+    hsl_ip_vrf_base_addr_set ip_vrf_base_addr_set;
+    hsl_ip_vrf_base_addr_get ip_vrf_base_addr_get;
+    hsl_ip_vrf_base_mask_set ip_vrf_base_mask_set;
+    hsl_ip_vrf_base_mask_get ip_vrf_base_mask_get;
+    hsl_ip_default_route_set ip_default_route_set;
+    hsl_ip_default_route_get ip_default_route_get;
+    hsl_ip_host_route_set ip_host_route_set;
+    hsl_ip_host_route_get ip_host_route_get;
+    hsl_ip_wcmp_entry_set ip_wcmp_entry_set;
+    hsl_ip_wcmp_entry_get ip_wcmp_entry_get;
+    hsl_ip_rfs_ip4_set ip_rfs_ip4_set;
+    hsl_ip_rfs_ip6_set ip_rfs_ip6_set;
+    hsl_ip_rfs_ip4_del ip_rfs_ip4_del;
+    hsl_ip_rfs_ip6_del ip_rfs_ip6_del;
+    hsl_default_flow_cmd_set ip_default_flow_cmd_set;
+    hsl_default_flow_cmd_get ip_default_flow_cmd_get;
+    hsl_default_rt_flow_cmd_set ip_default_rt_flow_cmd_set;
+    hsl_default_rt_flow_cmd_get ip_default_rt_flow_cmd_get;
+	hsl_ip_glb_lock_time_set ip_glb_lock_time_set;
+
+    /* NAT */
+    hsl_nat_add nat_add;
+    hsl_nat_del nat_del;
+    hsl_nat_get nat_get;
+    hsl_nat_next nat_next;
+    hsl_nat_counter_bind nat_counter_bind;
+    hsl_napt_add napt_add;
+    hsl_napt_del napt_del;
+    hsl_napt_get napt_get;
+    hsl_napt_next napt_next;
+    hsl_napt_counter_bind napt_counter_bind;
+    hsl_napt_add flow_add;
+    hsl_napt_del flow_del;
+    hsl_napt_get flow_get;
+    hsl_napt_next flow_next;
+    hsl_napt_counter_bind flow_counter_bind;
+    hsl_nat_status_set nat_status_set;
+    hsl_nat_status_get nat_status_get;
+    hsl_nat_hash_mode_set nat_hash_mode_set;
+    hsl_nat_hash_mode_get nat_hash_mode_get;
+    hsl_napt_status_set napt_status_set;
+    hsl_napt_status_get napt_status_get;
+    hsl_napt_mode_set napt_mode_set;
+    hsl_napt_mode_get napt_mode_get;
+    hsl_nat_prv_base_addr_set nat_prv_base_addr_set;
+    hsl_nat_prv_base_addr_get nat_prv_base_addr_get;
+    hsl_nat_prv_base_mask_set nat_prv_base_mask_set;
+    hsl_nat_prv_base_mask_get nat_prv_base_mask_get;
+    hsl_nat_prv_addr_mode_set nat_prv_addr_mode_set;
+    hsl_nat_prv_addr_mode_get nat_prv_addr_mode_get;
+    hsl_nat_pub_addr_add nat_pub_addr_add;
+    hsl_nat_pub_addr_del nat_pub_addr_del;
+    hsl_nat_pub_addr_next nat_pub_addr_next;
+    hsl_nat_unk_session_cmd_set nat_unk_session_cmd_set;
+    hsl_nat_unk_session_cmd_get nat_unk_session_cmd_get;
+    hsl_nat_global_set nat_global_set;
+    hsl_flow_cookie_set flow_cookie_set;
+    hsl_flow_rfs_set flow_rfs_set;
+
+    /* SEC */
+    hsl_sec_norm_item_set sec_norm_item_set;
+    hsl_sec_norm_item_get sec_norm_item_get;
+
+    /* Trunk */
+    hsl_trunk_group_set trunk_group_set;
+    hsl_trunk_group_get trunk_group_get;
+    hsl_trunk_hash_mode_set trunk_hash_mode_set;
+    hsl_trunk_hash_mode_get trunk_hash_mode_get;
+    hsl_trunk_manipulate_sa_set trunk_manipulate_sa_set;
+    hsl_trunk_manipulate_sa_get trunk_manipulate_sa_get;
+
+    /* Interface Control */
+    hsl_interface_mac_mode_set interface_mac_mode_set;
+    hsl_interface_mac_mode_get interface_mac_mode_get;
+    hsl_port_3az_status_set port_3az_status_set;
+    hsl_port_3az_status_get port_3az_status_get;
+    hsl_interface_phy_mode_set interface_phy_mode_set;
+    hsl_interface_phy_mode_get interface_phy_mode_get;
+    hsl_interface_fx100_ctrl_set interface_fx100_ctrl_set;
+    hsl_interface_fx100_ctrl_get interface_fx100_ctrl_get;
+    hsl_interface_fx100_status_get interface_fx100_status_get;
+    hsl_interface_mac06_exch_set interface_mac06_exch_set;
+    hsl_interface_mac06_exch_get interface_mac06_exch_get;
+    hsl_interface_pad_get	interface_mac_pad_get;
+    hsl_interface_pad_set	interface_mac_pad_set;
+    hsl_interface_sgmii_get	interface_mac_sgmii_get;
+    hsl_interface_sgmii_set	interface_mac_sgmii_set;
+#endif
+#endif
+/*qca808x_start*/
+    /* REG Access */
+    hsl_phy_get phy_get;
+    hsl_phy_set phy_set;
+/*qca808x_end*/
+    hsl_reg_get reg_get;
+    hsl_reg_set reg_set;
+    hsl_reg_field_get reg_field_get;
+    hsl_reg_field_set reg_field_set;
+    hsl_reg_entries_get reg_entries_get;
+    hsl_reg_entries_set reg_entries_set;
+    hsl_psgmii_reg_get psgmii_reg_get;
+    hsl_psgmii_reg_set psgmii_reg_set;
+	hsl_register_dump	register_dump;
+	hsl_debug_register_dump	debug_register_dump;
+	hsl_debug_psgmii_self_test	debug_psgmii_self_test;
+	hsl_phy_dump	 phy_dump;
+    hsl_uniphy_reg_get uniphy_reg_get;
+    hsl_uniphy_reg_set uniphy_reg_set;
+/*qca808x_start*/
+      /*INIT*/ hsl_dev_reset dev_reset;
+    hsl_dev_clean dev_clean;
+/*qca808x_end*/
+    hsl_dev_access_set dev_access_set;
+/*qca808x_start*/
+    hsl_phy_get phy_i2c_get;
+    hsl_phy_set phy_i2c_set;
+  } hsl_api_t;
+
+  hsl_api_t *hsl_api_ptr_get (a_uint32_t dev_id);
+
+    sw_error_t hsl_api_init (a_uint32_t dev_id);
+
+#if defined(SW_API_LOCK) && (!defined(HSL_STANDALONG))
+  extern aos_lock_t sw_hsl_api_lock;
+#define FAL_API_LOCK    aos_lock(&sw_hsl_api_lock)
+#define FAL_API_UNLOCK  aos_unlock(&sw_hsl_api_lock)
+#else
+#define FAL_API_LOCK
+#define FAL_API_UNLOCK
+#endif
+
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* _SW_API_H */
+/*qca808x_end*/
diff --git a/qca-ssdk/include/hsl/hsl_dev.h b/qca-ssdk/include/hsl/hsl_dev.h
new file mode 100755
index 0000000..48d3eb5
--- /dev/null
+++ b/qca-ssdk/include/hsl/hsl_dev.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2012, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/*qca808x_start*/
+#ifndef _HSL_DEV_H
+#define _HSL_DEV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "hsl_api.h"
+#include "ssdk_init.h"
+
+#define HSL_DEV_ID_CHECK(dev_id) \
+do { \
+    if (dev_id >= SW_MAX_NR_DEV) \
+        return SW_OUT_OF_RANGE; \
+} while (0)
+
+#define HSL_PORT_ID_CHECK(port_id) \
+do { \
+    if (port_id >= SW_MAX_NR_PORT) \
+        return SW_OUT_OF_RANGE; \
+} while (0)
+
+    typedef struct
+    {
+        a_uint32_t dev_id;
+        a_uint8_t cpu_port_nr;
+        a_uint8_t nr_ports;
+        a_uint8_t nr_phy;
+        a_uint8_t nr_queue;
+        a_uint16_t nr_vlans;
+		a_bool_t hw_vlan_query;
+        hsl_acl_func_t acl_func;
+        hsl_init_mode  cpu_mode;
+		a_uint32_t wan_bmp;
+    } hsl_dev_t;
+
+    hsl_dev_t *hsl_dev_ptr_get(a_uint32_t dev_id);
+/*qca808x_end*/
+    hsl_acl_func_t *hsl_acl_ptr_get(a_uint32_t dev_id);
+/*qca808x_start*/
+    sw_error_t
+    hsl_dev_init(a_uint32_t dev_id, ssdk_init_cfg * cfg);
+
+    sw_error_t
+    hsl_dev_cleanup(void);
+
+/*qca808x_end*/
+    sw_error_t
+    hsl_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg);
+
+    sw_error_t
+    hsl_access_mode_set(a_uint32_t dev_id, hsl_access_mode reg_mode);
+
+    a_uint32_t hsl_dev_inner_ports_get(a_uint32_t dev_id);
+
+/*qca808x_start*/
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _HSL_DEV_H */
+/*qca808x_end*/
+
diff --git a/qca-ssdk/include/hsl/hsl_lock.h b/qca-ssdk/include/hsl/hsl_lock.h
new file mode 100755
index 0000000..db79fd5
--- /dev/null
+++ b/qca-ssdk/include/hsl/hsl_lock.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HSL_LOCK_H_
+#define _HSL_LOCK_H_
+
+#ifdef __cplusplus
+extern "c" {
+#endif
+    sw_error_t hsl_api_lock_init(void);
+
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /*_HSL_LOCK_H_ */
diff --git a/qca-ssdk/include/hsl/hsl_port_prop.h b/qca-ssdk/include/hsl/hsl_port_prop.h
new file mode 100755
index 0000000..9b2c419
--- /dev/null
+++ b/qca-ssdk/include/hsl/hsl_port_prop.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2012, 2017, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HSL_PORT_PROPERTY_H_
+#define _HSL_PORT_PROPERTY_H_
+
+#ifdef __cplusplus
+extern "c" {
+#endif
+
+    typedef enum {
+        HSL_PP_PHY = 0,    /* setting concerning phy */
+        HSL_PP_INCL_CPU,   /* setting may include cpu port */
+        HSL_PP_EXCL_CPU,   /* setting exclude cpu port */
+        HSL_PP_INNER,   /* setting inner ports */
+        HSL_PP_CPU, /* setting cpu ports */
+        HSL_PP_BUTT
+    }
+    hsl_port_prop_t;
+
+    a_bool_t
+    hsl_port_prop_check(a_uint32_t dev_id, fal_port_t port_id,
+                        hsl_port_prop_t p_type);
+
+    a_bool_t
+    hsl_mports_prop_check(a_uint32_t dev_id, fal_pbmp_t port_bitmap,
+                          hsl_port_prop_t p_type);
+    a_bool_t
+    hsl_port_validity_check(a_uint32_t dev_id, fal_port_t port_id);
+
+    a_bool_t
+    hsl_mports_validity_check(a_uint32_t dev_id, fal_pbmp_t port_bitmap);
+
+    sw_error_t
+    hsl_port_prop_portmap_get(a_uint32_t dev_id, fal_pbmp_t port_bitmap);
+
+    sw_error_t
+    hsl_port_prop_set(a_uint32_t dev_id, fal_port_t port_id,
+                      hsl_port_prop_t p_type);
+
+    sw_error_t
+    hsl_port_prop_portmap_set(a_uint32_t dev_id,  fal_port_t port_id);
+
+    sw_error_t
+    hsl_port_prop_clr(a_uint32_t dev_id, fal_port_t port_id,
+                      hsl_port_prop_t p_type);
+
+    sw_error_t
+    hsl_port_prop_get_phyid(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t *phy_id);
+
+    sw_error_t
+    hsl_port_prop_set_phyid(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t phy_id);
+
+    sw_error_t
+    hsl_port_prop_init_by_dev(a_uint32_t dev_id);
+
+    sw_error_t
+    hsl_port_prop_cleanup_by_dev(a_uint32_t dev_id);
+
+    sw_error_t
+    hsl_port_prop_init(a_uint32_t dev_id);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /*_HSL_PORT_PROPERTY_H_ */
diff --git a/qca-ssdk/include/hsl/hsl_shared_api.h b/qca-ssdk/include/hsl/hsl_shared_api.h
new file mode 100755
index 0000000..cbf7294
--- /dev/null
+++ b/qca-ssdk/include/hsl/hsl_shared_api.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _HSL_SHARED_API_H
+#define _HSL_SHARED_API_H
+
+#include "hsl.h"
+#include "hsl_api.h"
+#include "ssdk_init.h"
+
+extern ssdk_chip_type SSDK_CURRENT_CHIP_TYPE;  /*running chip type*/
+
+#if !defined (HSL_STANDALONG)
+/*MISC API*/
+#define PORT_BC_FILTER_SET fal_port_bc_filter_set
+#define PORT_UNK_MC_FILTER_SET fal_port_unk_mc_filter_set
+#define PORT_UNK_UC_FILTER_SET fal_port_unk_uc_filter_set
+
+/*ACL API*/
+#define ACL_RULE_QUERY fal_acl_rule_query
+
+/*VLAN API */
+#define VLAN_CREATE fal_vlan_create
+#define VLAN_DEL fal_vlan_delete
+#define VLAN_FIND fal_vlan_find
+#define VLAN_MEMBER_ADD fal_vlan_member_add
+
+/*RATE API*/
+#define RATE_ACL_POLICER_SET fal_rate_acl_policer_set
+
+/*MIB API*/
+#define MIB_STATUS_SET fal_mib_status_set
+#define GET_MIB_INFO fal_get_mib_info
+
+/* PORT_CTRL API */
+#define PORT_TXMAC_STATUS_SET fal_port_txmac_status_set
+#define PORT_RXMAC_STATUS_SET fal_port_rxmac_status_set
+
+#elif defined(ISISC)
+/* NAT API*/
+#include "isisc_nat.h"
+#define NAPT_ADD isisc_napt_add
+#define NAT_PUB_ADDR_ADD isisc_nat_pub_addr_add
+#define NAPT_NEXT isisc_napt_next
+#define NAT_PRV_BASE_ADDR_SET isisc_nat_prv_base_addr_set
+#define NAT_PRV_BASE_MASK_SET isisc_nat_prv_base_mask_set
+#define NAPT_DEL isisc_napt_del
+#define NAT_DEL isisc_nat_del
+#define NAT_PUB_ADDR_DEL isisc_nat_pub_addr_del
+#define NAT_ADD isisc_nat_add
+#define NAT_PRV_ADDR_MODE_GET isisc_nat_prv_addr_mode_get
+
+/*IP API*/
+#include "isisc_ip.h"
+#define IP_INTF_ENTRY_ADD isisc_ip_intf_entry_add
+#define IP_HOST_ADD isisc_ip_host_add
+#define IP_HOST_DEL isisc_ip_host_del
+#define IP_HOST_GET isisc_ip_host_get
+#define IP_HOST_NEXT isisc_ip_host_next
+#define IP_INTF_ENTRY_DEL isisc_ip_intf_entry_del
+#define IP_HOST_PPPOE_BIND isisc_ip_host_pppoe_bind
+#define IP_ROUTE_STATUS_SET isisc_ip_route_status_set
+
+/*MISC API*/
+#include "isisc_misc.h"
+#define PPPOE_STATUS_GET isisc_pppoe_status_get
+#define PPPOE_STATUS_SET isisc_pppoe_status_set
+#define PPPOE_SESSION_ID_SET isisc_pppoe_session_id_set
+#define PPPOE_SESSION_TABLE_ADD isisc_pppoe_session_table_add
+#define PPPOE_SESSION_TABLE_DEL isisc_pppoe_session_table_del
+#define PORT_BC_FILTER_SET  isisc_port_bc_filter_set
+#define PORT_UNK_MC_FILTER_SET  isisc_port_unk_mc_filter_set
+#define PORT_UNK_UC_FILTER_SET isisc_port_unk_uc_filter_set
+#define PORT_RXMAC_STATUS_SET isisc_port_rxmac_status_set
+#define MISC_ARP_CMD_SET isisc_arp_cmd_set
+#define MISC_ARP_SP_NOT_FOUND_SET isisc_arp_unk_source_cmd_set
+#define MISC_ARP_GUARD_SET isisc_ip_arp_guard_set
+#define CPU_VID_EN_SET isisc_cpu_vid_en_set
+#define RTD_PPPOE_EN_SET isisc_rtd_pppoe_en_set
+#define PORT_ARP_ACK_STATUS_SET isisc_port_arp_ack_status_set
+#define CPU_PORT_STATUS_SET isisc_cpu_port_status_set
+
+/*ACL API*/
+#include "isisc_acl.h"
+#define ACL_RULE_ADD isisc_acl_rule_add
+#define ACL_RULE_DEL isisc_acl_rule_delete
+#define ACL_LIST_CREATE  isisc_acl_list_creat
+#define ACL_LIST_DESTROY isisc_acl_list_destroy
+#define ACL_LIST_BIND isisc_acl_list_bind
+#define ACL_LIST_UNBIND  isisc_acl_list_unbind
+#define ACL_RULE_GET_OFFSET isisc_acl_rule_get_offset
+#define ACL_RULE_QUERY isisc_acl_rule_query
+#define ACL_RULE_SYNC_MULTI_PORTMAP isisc_acl_rule_sync_multi_portmap
+#define ACL_STATUS_GET isisc_acl_status_get
+#define ACL_STATUS_SET isisc_acl_status_set
+#define ACL_PORT_UDF_PROFILE_SET isisc_acl_port_udf_profile_set
+
+/*VLAN API */
+#include "isisc_vlan.h"
+#define VLAN_CREATE isisc_vlan_create
+#define VLAN_DEL isisc_vlan_delete
+#define VLAN_FIND isisc_vlan_find
+#define VLAN_MEMBER_ADD isisc_vlan_member_add
+
+/*RATE API*/
+#include "isisc_rate.h"
+#define RATE_ACL_POLICER_SET isisc_rate_acl_policer_set
+
+/*MIB API*/
+#include "isisc_mib.h"
+#define MIB_STATUS_SET isisc_mib_status_set
+#define GET_MIB_INFO isisc_get_mib_info
+
+/* PORTVLAN API */
+#include "isisc_portvlan.h"
+#define PORTVLAN_ROUTE_DEFV_SET isisc_port_route_defv_set
+#define NETISOLATE_SET isisc_netisolate_set
+
+/* PORT_CTRL API */
+#include "isisc_port_ctrl.h"
+#define HEADER_TYPE_SET isisc_header_type_set
+#define PORT_TXHDR_MODE_SET isisc_port_txhdr_mode_set
+#define PORT_TXMAC_STATUS_SET isisc_port_txmac_status_set
+
+#elif defined(ISIS)
+/* NAT API*/
+#include "isis_nat.h"
+#define NAPT_ADD isis_napt_add
+#define NAT_PUB_ADDR_ADD isis_nat_pub_addr_add
+#define NAPT_NEXT isis_napt_next
+#define NAT_PRV_BASE_ADDR_SET isis_nat_prv_base_addr_set
+#define NAT_PRV_BASE_MASK_SET isis_nat_prv_base_mask_set
+#define NAPT_DEL isis_napt_del
+#define NAT_DEL isis_nat_del
+#define NAT_PUB_ADDR_DEL isis_nat_pub_addr_del
+#define NAT_ADD isis_nat_add
+#define NAT_PRV_ADDR_MODE_GET isis_nat_prv_addr_mode_get
+
+/*IP API*/
+#include "isis_ip.h"
+#define IP_INTF_ENTRY_ADD isis_ip_intf_entry_add
+#define IP_HOST_ADD isis_ip_host_add
+#define IP_HOST_DEL isis_ip_host_del
+#define IP_HOST_GET isis_ip_host_get
+#define IP_HOST_NEXT isis_ip_host_next
+#define IP_INTF_ENTRY_DEL isis_ip_intf_entry_del
+#define IP_HOST_PPPOE_BIND isis_ip_host_pppoe_bind
+#define IP_ROUTE_STATUS_SET isis_ip_route_status_set
+
+/*MISC API*/
+#include "isis_misc.h"
+#define PPPOE_STATUS_GET isis_pppoe_status_get
+#define PPPOE_STATUS_SET isis_pppoe_status_set
+#define PPPOE_SESSION_ID_SET isis_pppoe_session_id_set
+#define PPPOE_SESSION_TABLE_ADD isis_pppoe_session_table_add
+#define PPPOE_SESSION_TABLE_DEL isis_pppoe_session_table_del
+#define PORT_BC_FILTER_SET  isis_port_bc_filter_set
+#define PORT_UNK_MC_FILTER_SET  isis_port_unk_mc_filter_set
+#define PORT_UNK_UC_FILTER_SET isis_port_unk_uc_filter_set
+#define PORT_RXMAC_STATUS_SET isis_port_rxmac_status_set
+#define MISC_ARP_CMD_SET isis_arp_cmd_set
+#define CPU_VID_EN_SET isis_cpu_vid_en_set
+#define RTD_PPPOE_EN_SET isis_rtd_pppoe_en_set
+#define PORT_ARP_ACK_STATUS_SET isis_port_arp_ack_status_set
+#define CPU_PORT_STATUS_SET isis_cpu_port_status_set
+
+/*ACL API*/
+#include "isis_acl.h"
+#define ACL_RULE_ADD isis_acl_rule_add
+#define ACL_RULE_DEL isis_acl_rule_delete
+#define ACL_LIST_CREATE  isis_acl_list_creat
+#define ACL_LIST_DESTROY isis_acl_list_destroy
+#define ACL_LIST_BIND isis_acl_list_bind
+#define ACL_LIST_UNBIND  isis_acl_list_unbind
+#define ACL_RULE_GET_OFFSET isis_acl_rule_get_offset
+#define ACL_RULE_QUERY isis_acl_rule_query
+#define ACL_RULE_SYNC_MULTI_PORTMAP isis_acl_rule_sync_multi_portmap
+#define ACL_STATUS_GET isis_acl_status_get
+#define ACL_STATUS_SET isis_acl_status_set
+#define ACL_PORT_UDF_PROFILE_SET isis_acl_port_udf_profile_set
+
+/*VLAN API */
+#include "isis_vlan.h"
+#define VLAN_CREATE isis_vlan_create
+#define VLAN_DEL isis_vlan_delete
+#define VLAN_FIND isis_vlan_find
+#define VLAN_MEMBER_ADD isis_vlan_member_add
+
+/*RATE API*/
+#include "isis_rate.h"
+#define RATE_ACL_POLICER_SET isis_rate_acl_policer_set
+
+/*MIB API*/
+#include "isis_mib.h"
+#define MIB_STATUS_SET isis_mib_status_set
+#define GET_MIB_INFO isis_get_mib_info
+
+/* PORTVLAN API */
+#include "isis_portvlan.h"
+#define PORTVLAN_ROUTE_DEFV_SET isis_port_route_defv_set
+
+/* PORT_CTRL API */
+#include "isis_port_ctrl.h"
+#define HEADER_TYPE_SET isis_header_type_set
+#define PORT_TXHDR_MODE_SET isis_port_txhdr_mode_set
+#define PORT_TXMAC_STATUS_SET isis_port_txmac_status_set
+#endif
+
+#endif
diff --git a/qca-ssdk/include/hsl/isis/isis_acl.h b/qca-ssdk/include/hsl/isis/isis_acl.h
new file mode 100755
index 0000000..8f34225
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_acl.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_acl ISIS_ACL
+ * @{
+ */
+#ifndef _ISIS_ACL_H_
+#define _ISIS_ACL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_acl.h"
+
+    sw_error_t isis_acl_init(a_uint32_t dev_id);
+
+    sw_error_t isis_acl_reset(a_uint32_t dev_id);
+
+    sw_error_t isis_acl_cleanup(a_uint32_t dev_id);
+
+#ifdef IN_ACL
+#define ISIS_ACL_INIT(rv, dev_id) \
+    { \
+        rv = isis_acl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define ISIS_ACL_RESET(rv, dev_id) \
+    { \
+        rv = isis_acl_reset(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#define ISIS_ACL_CLEANUP(rv, dev_id) \
+    { \
+        rv = isis_acl_cleanup(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_ACL_INIT(rv, dev_id)
+#define ISIS_ACL_RESET(rv, dev_id)
+#define ISIS_ACL_CLEANUP(rv, dev_id)
+#endif
+
+    sw_error_t
+    isis_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+                        a_uint32_t list_pri);
+
+    sw_error_t
+    isis_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+                        a_uint32_t rule_id, fal_acl_rule_t * rule);
+
+    sw_error_t
+    isis_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+                      a_uint32_t rule_id, a_uint32_t rule_nr,
+                      fal_acl_rule_t * rule);
+
+    sw_error_t
+    isis_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+                         a_uint32_t rule_id, a_uint32_t rule_nr);
+
+    a_uint32_t
+    isis_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id);
+
+    sw_error_t
+    isis_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act);
+
+    sw_error_t
+    isis_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                       fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                       a_uint32_t obj_idx);
+
+    sw_error_t
+    isis_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                         fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                         a_uint32_t obj_idx);
+
+    sw_error_t
+    isis_acl_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isis_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id);
+
+    HSL_LOCAL sw_error_t
+    isis_acl_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isis_acl_list_dump(a_uint32_t dev_id);
+
+    HSL_LOCAL sw_error_t
+    isis_acl_rule_dump(a_uint32_t dev_id);
+
+    HSL_LOCAL sw_error_t
+    isis_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_acl_udf_type_t udf_type,
+                                  a_uint32_t offset, a_uint32_t length);
+
+    HSL_LOCAL sw_error_t
+    isis_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_acl_udf_type_t udf_type,
+                                  a_uint32_t * offset, a_uint32_t * length);
+
+    HSL_LOCAL sw_error_t
+    isis_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+                         a_uint32_t rule_id, a_uint32_t rule_nr);
+
+    HSL_LOCAL sw_error_t
+    isis_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+                           a_uint32_t rule_id, a_uint32_t rule_nr);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_ACL_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/isis/isis_api.h b/qca-ssdk/include/hsl/isis/isis_api.h
new file mode 100755
index 0000000..7fbc03f
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_api.h
@@ -0,0 +1,992 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _ISIS_API_H_
+#define _ISIS_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#ifdef IN_PORTCONTROL
+#define PORTCONTROL_API \
+    SW_API_DEF(SW_API_PT_DUPLEX_GET, isis_port_duplex_get), \
+    SW_API_DEF(SW_API_PT_DUPLEX_SET, isis_port_duplex_set), \
+    SW_API_DEF(SW_API_PT_SPEED_GET, isis_port_speed_get), \
+    SW_API_DEF(SW_API_PT_SPEED_SET, isis_port_speed_set), \
+    SW_API_DEF(SW_API_PT_AN_GET, isis_port_autoneg_status_get), \
+    SW_API_DEF(SW_API_PT_AN_ENABLE, isis_port_autoneg_enable), \
+    SW_API_DEF(SW_API_PT_AN_RESTART, isis_port_autoneg_restart), \
+    SW_API_DEF(SW_API_PT_AN_ADV_GET, isis_port_autoneg_adv_get), \
+    SW_API_DEF(SW_API_PT_AN_ADV_SET, isis_port_autoneg_adv_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_SET, isis_port_flowctrl_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_GET, isis_port_flowctrl_get), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, isis_port_flowctrl_forcemode_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, isis_port_flowctrl_forcemode_get), \
+    SW_API_DEF(SW_API_PT_POWERSAVE_SET, isis_port_powersave_set), \
+    SW_API_DEF(SW_API_PT_POWERSAVE_GET, isis_port_powersave_get), \
+    SW_API_DEF(SW_API_PT_HIBERNATE_SET, isis_port_hibernate_set), \
+    SW_API_DEF(SW_API_PT_HIBERNATE_GET, isis_port_hibernate_get), \
+    SW_API_DEF(SW_API_PT_CDT, isis_port_cdt), \
+    SW_API_DEF(SW_API_PT_TXHDR_SET, isis_port_txhdr_mode_set), \
+    SW_API_DEF(SW_API_PT_TXHDR_GET, isis_port_txhdr_mode_get), \
+    SW_API_DEF(SW_API_PT_RXHDR_SET, isis_port_rxhdr_mode_set), \
+    SW_API_DEF(SW_API_PT_RXHDR_GET, isis_port_rxhdr_mode_get), \
+    SW_API_DEF(SW_API_HEADER_TYPE_SET, isis_header_type_set),  \
+    SW_API_DEF(SW_API_HEADER_TYPE_GET, isis_header_type_get), \
+    SW_API_DEF(SW_API_TXMAC_STATUS_SET, isis_port_txmac_status_set), \
+    SW_API_DEF(SW_API_TXMAC_STATUS_GET, isis_port_txmac_status_get), \
+    SW_API_DEF(SW_API_RXMAC_STATUS_SET, isis_port_rxmac_status_set), \
+    SW_API_DEF(SW_API_RXMAC_STATUS_GET, isis_port_rxmac_status_get), \
+    SW_API_DEF(SW_API_TXFC_STATUS_SET, isis_port_txfc_status_set),   \
+    SW_API_DEF(SW_API_TXFC_STATUS_GET, isis_port_txfc_status_get),   \
+    SW_API_DEF(SW_API_RXFC_STATUS_SET, isis_port_rxfc_status_set),   \
+    SW_API_DEF(SW_API_RXFC_STATUS_GET, isis_port_rxfc_status_get),   \
+    SW_API_DEF(SW_API_BP_STATUS_SET, isis_port_bp_status_set),   \
+    SW_API_DEF(SW_API_BP_STATUS_GET, isis_port_bp_status_get),   \
+    SW_API_DEF(SW_API_PT_LINK_MODE_SET, isis_port_link_forcemode_set),   \
+    SW_API_DEF(SW_API_PT_LINK_MODE_GET, isis_port_link_forcemode_get), \
+    SW_API_DEF(SW_API_PT_LINK_STATUS_GET, isis_port_link_status_get), \
+    SW_API_DEF(SW_API_PT_MAC_LOOPBACK_SET, isis_port_mac_loopback_set), \
+    SW_API_DEF(SW_API_PT_MAC_LOOPBACK_GET, isis_port_mac_loopback_get), \
+    SW_API_DEF(SW_API_PT_8023AZ_SET, isis_port_8023az_set), \
+    SW_API_DEF(SW_API_PT_8023AZ_GET, isis_port_8023az_get),
+
+#define PORTCONTROL_API_PARAM \
+    SW_API_DESC(SW_API_PT_DUPLEX_GET) \
+    SW_API_DESC(SW_API_PT_DUPLEX_SET) \
+    SW_API_DESC(SW_API_PT_SPEED_GET)  \
+    SW_API_DESC(SW_API_PT_SPEED_SET)  \
+    SW_API_DESC(SW_API_PT_AN_GET)  \
+    SW_API_DESC(SW_API_PT_AN_ENABLE)   \
+    SW_API_DESC(SW_API_PT_AN_RESTART)  \
+    SW_API_DESC(SW_API_PT_AN_ADV_GET)  \
+    SW_API_DESC(SW_API_PT_AN_ADV_SET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_SET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_GET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \
+    SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
+    SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
+    SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
+    SW_API_DESC(SW_API_PT_HIBERNATE_GET) \
+    SW_API_DESC(SW_API_PT_CDT) \
+    SW_API_DESC(SW_API_PT_TXHDR_SET) \
+    SW_API_DESC(SW_API_PT_TXHDR_GET) \
+    SW_API_DESC(SW_API_PT_RXHDR_SET) \
+    SW_API_DESC(SW_API_PT_RXHDR_GET) \
+    SW_API_DESC(SW_API_HEADER_TYPE_SET) \
+    SW_API_DESC(SW_API_HEADER_TYPE_GET) \
+    SW_API_DESC(SW_API_TXMAC_STATUS_SET) \
+    SW_API_DESC(SW_API_TXMAC_STATUS_GET) \
+    SW_API_DESC(SW_API_RXMAC_STATUS_SET) \
+    SW_API_DESC(SW_API_RXMAC_STATUS_GET) \
+    SW_API_DESC(SW_API_TXFC_STATUS_SET) \
+    SW_API_DESC(SW_API_TXFC_STATUS_GET) \
+    SW_API_DESC(SW_API_RXFC_STATUS_SET) \
+    SW_API_DESC(SW_API_RXFC_STATUS_GET) \
+    SW_API_DESC(SW_API_BP_STATUS_SET) \
+    SW_API_DESC(SW_API_BP_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_LINK_MODE_SET) \
+    SW_API_DESC(SW_API_PT_LINK_MODE_GET) \
+    SW_API_DESC(SW_API_PT_LINK_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_MAC_LOOPBACK_SET) \
+    SW_API_DESC(SW_API_PT_MAC_LOOPBACK_GET) \
+    SW_API_DESC(SW_API_PT_8023AZ_SET) \
+    SW_API_DESC(SW_API_PT_8023AZ_GET)
+#else
+#define PORTCONTROL_API
+#define PORTCONTROL_API_PARAM
+#endif
+
+#ifdef IN_VLAN
+#define VLAN_API \
+    SW_API_DEF(SW_API_VLAN_ADD, isis_vlan_create), \
+    SW_API_DEF(SW_API_VLAN_DEL, isis_vlan_delete), \
+    SW_API_DEF(SW_API_VLAN_FIND, isis_vlan_find), \
+    SW_API_DEF(SW_API_VLAN_NEXT, isis_vlan_next), \
+    SW_API_DEF(SW_API_VLAN_APPEND, isis_vlan_entry_append), \
+    SW_API_DEF(SW_API_VLAN_FLUSH, isis_vlan_flush), \
+    SW_API_DEF(SW_API_VLAN_FID_SET, isis_vlan_fid_set), \
+    SW_API_DEF(SW_API_VLAN_FID_GET, isis_vlan_fid_get), \
+    SW_API_DEF(SW_API_VLAN_MEMBER_ADD, isis_vlan_member_add), \
+    SW_API_DEF(SW_API_VLAN_MEMBER_DEL, isis_vlan_member_del), \
+    SW_API_DEF(SW_API_VLAN_LEARN_STATE_SET, isis_vlan_learning_state_set), \
+    SW_API_DEF(SW_API_VLAN_LEARN_STATE_GET, isis_vlan_learning_state_get),
+
+#define VLAN_API_PARAM \
+    SW_API_DESC(SW_API_VLAN_ADD)     \
+    SW_API_DESC(SW_API_VLAN_DEL)     \
+    SW_API_DESC(SW_API_VLAN_FIND)    \
+    SW_API_DESC(SW_API_VLAN_NEXT)    \
+    SW_API_DESC(SW_API_VLAN_APPEND)  \
+    SW_API_DESC(SW_API_VLAN_FLUSH)   \
+    SW_API_DESC(SW_API_VLAN_FID_SET) \
+    SW_API_DESC(SW_API_VLAN_FID_GET) \
+    SW_API_DESC(SW_API_VLAN_MEMBER_ADD) \
+    SW_API_DESC(SW_API_VLAN_MEMBER_DEL) \
+    SW_API_DESC(SW_API_VLAN_LEARN_STATE_SET) \
+    SW_API_DESC(SW_API_VLAN_LEARN_STATE_GET)
+#else
+#define VLAN_API
+#define VLAN_API_PARAM
+#endif
+
+#ifdef IN_PORTVLAN
+#define PORTVLAN_API \
+    SW_API_DEF(SW_API_PT_ING_MODE_GET, isis_port_1qmode_get), \
+    SW_API_DEF(SW_API_PT_ING_MODE_SET, isis_port_1qmode_set), \
+    SW_API_DEF(SW_API_PT_EG_MODE_GET, isis_port_egvlanmode_get), \
+    SW_API_DEF(SW_API_PT_EG_MODE_SET, isis_port_egvlanmode_set), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, isis_portvlan_member_add), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, isis_portvlan_member_del), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, isis_portvlan_member_update), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_GET, isis_portvlan_member_get), \
+    SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, isis_port_force_default_vid_set), \
+    SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, isis_port_force_default_vid_get), \
+    SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, isis_port_force_portvlan_set), \
+    SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, isis_port_force_portvlan_get), \
+    SW_API_DEF(SW_API_NESTVLAN_TPID_SET, isis_nestvlan_tpid_set), \
+    SW_API_DEF(SW_API_NESTVLAN_TPID_GET, isis_nestvlan_tpid_get), \
+    SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, isis_port_invlan_mode_set), \
+    SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, isis_port_invlan_mode_get), \
+    SW_API_DEF(SW_API_PT_TLS_SET, isis_port_tls_set), \
+    SW_API_DEF(SW_API_PT_TLS_GET, isis_port_tls_get), \
+    SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, isis_port_pri_propagation_set), \
+    SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, isis_port_pri_propagation_get), \
+    SW_API_DEF(SW_API_PT_DEF_SVID_SET, isis_port_default_svid_set), \
+    SW_API_DEF(SW_API_PT_DEF_SVID_GET, isis_port_default_svid_get), \
+    SW_API_DEF(SW_API_PT_DEF_CVID_SET, isis_port_default_cvid_set), \
+    SW_API_DEF(SW_API_PT_DEF_CVID_GET, isis_port_default_cvid_get), \
+    SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_SET, isis_port_vlan_propagation_set), \
+    SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_GET, isis_port_vlan_propagation_get), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, isis_port_vlan_trans_add), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_DEL, isis_port_vlan_trans_del), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_GET, isis_port_vlan_trans_get), \
+    SW_API_DEF(SW_API_QINQ_MODE_SET, isis_qinq_mode_set), \
+    SW_API_DEF(SW_API_QINQ_MODE_GET, isis_qinq_mode_get), \
+    SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, isis_port_qinq_role_set), \
+    SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, isis_port_qinq_role_get), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ITERATE, isis_port_vlan_trans_iterate), \
+    SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_SET, isis_port_mac_vlan_xlt_set), \
+    SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_GET, isis_port_mac_vlan_xlt_get),
+
+#define PORTVLAN_API_PARAM \
+    SW_API_DESC(SW_API_PT_ING_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_ING_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_EG_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_EG_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE)  \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_GET)     \
+    SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET)    \
+    SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET)    \
+    SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET)   \
+    SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET)   \
+    SW_API_DESC(SW_API_NESTVLAN_TPID_SET)    \
+    SW_API_DESC(SW_API_NESTVLAN_TPID_GET)    \
+    SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET)    \
+    SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET)    \
+    SW_API_DESC(SW_API_PT_TLS_SET)    \
+    SW_API_DESC(SW_API_PT_TLS_GET)    \
+    SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET)    \
+    SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET)    \
+    SW_API_DESC(SW_API_PT_DEF_SVID_SET)    \
+    SW_API_DESC(SW_API_PT_DEF_SVID_GET)    \
+    SW_API_DESC(SW_API_PT_DEF_CVID_SET)    \
+    SW_API_DESC(SW_API_PT_DEF_CVID_GET)    \
+    SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_SET)    \
+    SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_GET)    \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD)  \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_DEL)  \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_GET)  \
+    SW_API_DESC(SW_API_QINQ_MODE_SET)      \
+    SW_API_DESC(SW_API_QINQ_MODE_GET)      \
+    SW_API_DESC(SW_API_PT_QINQ_ROLE_SET)   \
+    SW_API_DESC(SW_API_PT_QINQ_ROLE_GET)   \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ITERATE) \
+    SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_SET)   \
+    SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_GET)
+#else
+#define PORTVLAN_API
+#define PORTVLAN_API_PARAM
+#endif
+
+#ifdef IN_FDB
+#define FDB_API \
+    SW_API_DEF(SW_API_FDB_ADD, isis_fdb_add), \
+    SW_API_DEF(SW_API_FDB_DELALL, isis_fdb_del_all), \
+    SW_API_DEF(SW_API_FDB_DELPORT,isis_fdb_del_by_port), \
+    SW_API_DEF(SW_API_FDB_DELMAC, isis_fdb_del_by_mac), \
+    SW_API_DEF(SW_API_FDB_FIND,   isis_fdb_find), \
+    SW_API_DEF(SW_API_FDB_EXTEND_NEXT,    isis_fdb_extend_next),  \
+    SW_API_DEF(SW_API_FDB_EXTEND_FIRST,   isis_fdb_extend_first),  \
+    SW_API_DEF(SW_API_FDB_TRANSFER,       isis_fdb_transfer),  \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_SET,   isis_fdb_port_learn_set), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_GET,   isis_fdb_port_learn_get), \
+    SW_API_DEF(SW_API_FDB_AGE_CTRL_SET,   isis_fdb_age_ctrl_set), \
+    SW_API_DEF(SW_API_FDB_AGE_CTRL_GET,   isis_fdb_age_ctrl_get), \
+    SW_API_DEF(SW_API_FDB_AGE_TIME_SET,   isis_fdb_age_time_set), \
+    SW_API_DEF(SW_API_FDB_AGE_TIME_GET,   isis_fdb_age_time_get), \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET,    isis_port_fdb_learn_limit_set),  \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET,    isis_port_fdb_learn_limit_get),  \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET,    isis_port_fdb_learn_exceed_cmd_set),  \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET,    isis_port_fdb_learn_exceed_cmd_get), \
+    SW_API_DEF(SW_API_FDB_LEARN_LIMIT_SET,    isis_fdb_learn_limit_set),  \
+    SW_API_DEF(SW_API_FDB_LEARN_LIMIT_GET,    isis_fdb_learn_limit_get),  \
+    SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET,    isis_fdb_learn_exceed_cmd_set),  \
+    SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET,    isis_fdb_learn_exceed_cmd_get),  \
+    SW_API_DEF(SW_API_FDB_RESV_ADD, isis_fdb_resv_add), \
+    SW_API_DEF(SW_API_FDB_RESV_DEL, isis_fdb_resv_del), \
+    SW_API_DEF(SW_API_FDB_RESV_FIND, isis_fdb_resv_find), \
+    SW_API_DEF(SW_API_FDB_RESV_ITERATE, isis_fdb_resv_iterate), \
+    SW_API_DEF(SW_API_FDB_EXTEND_FIRST, isis_fdb_extend_first), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_SET,   isis_fdb_port_learn_static_set), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_GET,   isis_fdb_port_learn_static_get), \
+    SW_API_DEF(SW_API_FDB_PORT_ADD,   isis_fdb_port_add), \
+    SW_API_DEF(SW_API_FDB_PORT_DEL,   isis_fdb_port_del),
+
+#define FDB_API_PARAM \
+    SW_API_DESC(SW_API_FDB_ADD) \
+    SW_API_DESC(SW_API_FDB_DELALL)  \
+    SW_API_DESC(SW_API_FDB_DELPORT) \
+    SW_API_DESC(SW_API_FDB_DELMAC) \
+    SW_API_DESC(SW_API_FDB_FIND) \
+    SW_API_DESC(SW_API_FDB_EXTEND_NEXT)  \
+    SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \
+    SW_API_DESC(SW_API_FDB_TRANSFER) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \
+    SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \
+    SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \
+    SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \
+    SW_API_DESC(SW_API_FDB_AGE_TIME_GET) \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_SET)  \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_GET)  \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET)  \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_LIMIT_SET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_LIMIT_GET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_SET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_GET)  \
+    SW_API_DESC(SW_API_FDB_RESV_ADD)  \
+    SW_API_DESC(SW_API_FDB_RESV_DEL)  \
+    SW_API_DESC(SW_API_FDB_RESV_FIND) \
+    SW_API_DESC(SW_API_FDB_RESV_ITERATE) \
+    SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_SET) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_GET) \
+    SW_API_DESC(SW_API_FDB_PORT_ADD)  \
+    SW_API_DESC(SW_API_FDB_PORT_DEL)
+
+#else
+#define FDB_API
+#define FDB_API_PARAM
+#endif
+
+
+#ifdef IN_ACL
+#define ACL_API \
+    SW_API_DEF(SW_API_ACL_LIST_CREAT, isis_acl_list_creat), \
+    SW_API_DEF(SW_API_ACL_LIST_DESTROY, isis_acl_list_destroy), \
+    SW_API_DEF(SW_API_ACL_RULE_ADD, isis_acl_rule_add), \
+    SW_API_DEF(SW_API_ACL_RULE_DELETE, isis_acl_rule_delete), \
+    SW_API_DEF(SW_API_ACL_RULE_QUERY, isis_acl_rule_query), \
+    SW_API_DEF(SW_API_ACL_LIST_BIND, isis_acl_list_bind), \
+    SW_API_DEF(SW_API_ACL_LIST_UNBIND, isis_acl_list_unbind), \
+    SW_API_DEF(SW_API_ACL_STATUS_SET, isis_acl_status_set), \
+    SW_API_DEF(SW_API_ACL_STATUS_GET, isis_acl_status_get), \
+    SW_API_DEF(SW_API_ACL_LIST_DUMP, isis_acl_list_dump), \
+    SW_API_DEF(SW_API_ACL_RULE_DUMP, isis_acl_rule_dump), \
+    SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, isis_acl_port_udf_profile_set), \
+    SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, isis_acl_port_udf_profile_get), \
+    SW_API_DEF(SW_API_ACL_RULE_ACTIVE, isis_acl_rule_active), \
+    SW_API_DEF(SW_API_ACL_RULE_DEACTIVE, isis_acl_rule_deactive),\
+    SW_API_DEF(SW_API_ACL_RULE_GET_OFFSET, isis_acl_rule_get_offset),
+
+#define ACL_API_PARAM \
+    SW_API_DESC(SW_API_ACL_LIST_CREAT)   \
+    SW_API_DESC(SW_API_ACL_LIST_DESTROY) \
+    SW_API_DESC(SW_API_ACL_RULE_ADD)     \
+    SW_API_DESC(SW_API_ACL_RULE_DELETE)  \
+    SW_API_DESC(SW_API_ACL_RULE_QUERY)   \
+    SW_API_DESC(SW_API_ACL_LIST_BIND)    \
+    SW_API_DESC(SW_API_ACL_LIST_UNBIND)  \
+    SW_API_DESC(SW_API_ACL_STATUS_SET)   \
+    SW_API_DESC(SW_API_ACL_STATUS_GET)   \
+    SW_API_DESC(SW_API_ACL_LIST_DUMP)    \
+    SW_API_DESC(SW_API_ACL_RULE_DUMP)    \
+    SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_SET)    \
+    SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_GET)    \
+    SW_API_DESC(SW_API_ACL_RULE_ACTIVE)    \
+    SW_API_DESC(SW_API_ACL_RULE_DEACTIVE)
+#else
+#define ACL_API
+#define ACL_API_PARAM
+#endif
+
+
+#ifdef IN_QOS
+#define QOS_API \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, isis_qos_queue_tx_buf_status_set), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, isis_qos_queue_tx_buf_status_get), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, isis_qos_queue_tx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, isis_qos_queue_tx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, isis_qos_port_tx_buf_status_set), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, isis_qos_port_tx_buf_status_get), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, isis_qos_port_tx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, isis_qos_port_tx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, isis_qos_port_rx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, isis_qos_port_rx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_SET, isis_qos_port_mode_set), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_GET, isis_qos_port_mode_get), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, isis_qos_port_mode_pri_set), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, isis_qos_port_mode_pri_get), \
+    SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, isis_qos_port_sch_mode_set), \
+    SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, isis_qos_port_sch_mode_get), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_SET, isis_qos_port_default_spri_set), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_GET, isis_qos_port_default_spri_get), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_SET, isis_qos_port_default_cpri_set), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_GET, isis_qos_port_default_cpri_get), \
+    SW_API_DEF(SW_API_QOS_QUEUE_REMARK_SET, isis_qos_queue_remark_table_set), \
+    SW_API_DEF(SW_API_QOS_QUEUE_REMARK_GET, isis_qos_queue_remark_table_get),
+
+
+#define QOS_API_PARAM \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_SET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_GET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET) \
+    SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_SET)  \
+    SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_GET)  \
+    SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_SET)  \
+    SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_GET)  \
+    SW_API_DESC(SW_API_QOS_QUEUE_REMARK_SET) \
+    SW_API_DESC(SW_API_QOS_QUEUE_REMARK_GET)
+#else
+#define QOS_API
+#define QOS_API_PARAM
+#endif
+
+
+#ifdef IN_IGMP
+#define IGMP_API \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, isis_port_igmps_status_set), \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, isis_port_igmps_status_get), \
+    SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, isis_igmp_mld_cmd_set), \
+    SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, isis_igmp_mld_cmd_get), \
+    SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, isis_port_igmp_mld_join_set), \
+    SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, isis_port_igmp_mld_join_get), \
+    SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, isis_port_igmp_mld_leave_set), \
+    SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, isis_port_igmp_mld_leave_get), \
+    SW_API_DEF(SW_API_IGMP_RP_SET, isis_igmp_mld_rp_set), \
+    SW_API_DEF(SW_API_IGMP_RP_GET, isis_igmp_mld_rp_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, isis_igmp_mld_entry_creat_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, isis_igmp_mld_entry_creat_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, isis_igmp_mld_entry_static_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, isis_igmp_mld_entry_static_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, isis_igmp_mld_entry_leaky_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, isis_igmp_mld_entry_leaky_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, isis_igmp_mld_entry_v3_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, isis_igmp_mld_entry_v3_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, isis_igmp_mld_entry_queue_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, isis_igmp_mld_entry_queue_get), \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET,    isis_port_igmp_mld_learn_limit_set),  \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET,    isis_port_igmp_mld_learn_limit_get),  \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET,    isis_port_igmp_mld_learn_exceed_cmd_set),  \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET,    isis_port_igmp_mld_learn_exceed_cmd_get), \
+    SW_API_DEF(SW_API_IGMP_SG_ENTRY_SET,    isis_igmp_sg_entry_set),  \
+    SW_API_DEF(SW_API_IGMP_SG_ENTRY_CLEAR,    isis_igmp_sg_entry_clear),  \
+    SW_API_DEF(SW_API_IGMP_SG_ENTRY_SHOW,    isis_igmp_sg_entry_show),
+
+#define IGMP_API_PARAM \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
+    SW_API_DESC(SW_API_IGMP_MLD_CMD_SET)  \
+    SW_API_DESC(SW_API_IGMP_MLD_CMD_GET)  \
+    SW_API_DESC(SW_API_IGMP_PT_JOIN_SET)  \
+    SW_API_DESC(SW_API_IGMP_PT_JOIN_GET)  \
+    SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \
+    SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \
+    SW_API_DESC(SW_API_IGMP_RP_SET)  \
+    SW_API_DESC(SW_API_IGMP_RP_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_SET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_GET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET) \
+    SW_API_DESC(SW_API_IGMP_SG_ENTRY_SET) \
+    SW_API_DESC(SW_API_IGMP_SG_ENTRY_CLEAR) \
+    SW_API_DESC(SW_API_IGMP_SG_ENTRY_SHOW)
+#else
+#define IGMP_API
+#define IGMP_API_PARAM
+#endif
+
+
+#ifdef IN_LEAKY
+#define LEAKY_API \
+    SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, isis_uc_leaky_mode_set), \
+    SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, isis_uc_leaky_mode_get), \
+    SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, isis_mc_leaky_mode_set), \
+    SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, isis_mc_leaky_mode_get), \
+    SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, isis_port_arp_leaky_set), \
+    SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, isis_port_arp_leaky_get), \
+    SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, isis_port_uc_leaky_set), \
+    SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, isis_port_uc_leaky_get), \
+    SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, isis_port_mc_leaky_set), \
+    SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, isis_port_mc_leaky_get),
+
+#define LEAKY_API_PARAM \
+    SW_API_DESC(SW_API_UC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_UC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_MC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_MC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \
+    SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \
+    SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET)
+#else
+#define LEAKY_API
+#define LEAKY_API_PARAM
+#endif
+
+
+#ifdef IN_MIRROR
+#define MIRROR_API \
+    SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, isis_mirr_analysis_port_set), \
+    SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, isis_mirr_analysis_port_get), \
+    SW_API_DEF(SW_API_MIRROR_IN_PT_SET, isis_mirr_port_in_set), \
+    SW_API_DEF(SW_API_MIRROR_IN_PT_GET, isis_mirr_port_in_get), \
+    SW_API_DEF(SW_API_MIRROR_EG_PT_SET, isis_mirr_port_eg_set), \
+    SW_API_DEF(SW_API_MIRROR_EG_PT_GET, isis_mirr_port_eg_get),
+
+#define MIRROR_API_PARAM \
+    SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET)  \
+    SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET)  \
+    SW_API_DESC(SW_API_MIRROR_IN_PT_SET)  \
+    SW_API_DESC(SW_API_MIRROR_IN_PT_GET)  \
+    SW_API_DESC(SW_API_MIRROR_EG_PT_SET)  \
+    SW_API_DESC(SW_API_MIRROR_EG_PT_GET)
+#else
+#define MIRROR_API
+#define MIRROR_API_PARAM
+#endif
+
+
+#ifdef IN_RATE
+#define RATE_API \
+    SW_API_DEF(SW_API_RATE_PORT_POLICER_SET, isis_rate_port_policer_set), \
+    SW_API_DEF(SW_API_RATE_PORT_POLICER_GET, isis_rate_port_policer_get), \
+    SW_API_DEF(SW_API_RATE_PORT_SHAPER_SET, isis_rate_port_shaper_set), \
+    SW_API_DEF(SW_API_RATE_PORT_SHAPER_GET, isis_rate_port_shaper_get), \
+    SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_SET, isis_rate_queue_shaper_set), \
+    SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_GET, isis_rate_queue_shaper_get), \
+    SW_API_DEF(SW_API_RATE_ACL_POLICER_SET, isis_rate_acl_policer_set), \
+    SW_API_DEF(SW_API_RATE_ACL_POLICER_GET, isis_rate_acl_policer_get), \
+    SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, isis_rate_port_add_rate_byte_set), \
+    SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, isis_rate_port_add_rate_byte_get),
+
+#define RATE_API_PARAM \
+    SW_API_DESC(SW_API_RATE_PORT_POLICER_SET) \
+    SW_API_DESC(SW_API_RATE_PORT_POLICER_GET) \
+    SW_API_DESC(SW_API_RATE_PORT_SHAPER_SET) \
+    SW_API_DESC(SW_API_RATE_PORT_SHAPER_GET) \
+    SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_SET) \
+    SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_GET) \
+    SW_API_DESC(SW_API_RATE_ACL_POLICER_SET) \
+    SW_API_DESC(SW_API_RATE_ACL_POLICER_GET) \
+    SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_SET) \
+    SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_GET)
+#else
+#define RATE_API
+#define RATE_API_PARAM
+#endif
+
+
+#ifdef IN_STP
+#define STP_API \
+    SW_API_DEF(SW_API_STP_PT_STATE_SET, isis_stp_port_state_set), \
+    SW_API_DEF(SW_API_STP_PT_STATE_GET, isis_stp_port_state_get),
+
+#define STP_API_PARAM \
+    SW_API_DESC(SW_API_STP_PT_STATE_SET) \
+    SW_API_DESC(SW_API_STP_PT_STATE_GET)
+#else
+#define STP_API
+#define STP_API_PARAM
+#endif
+
+
+#ifdef IN_MIB
+#define MIB_API \
+    SW_API_DEF(SW_API_PT_MIB_GET, isis_get_mib_info), \
+    SW_API_DEF(SW_API_MIB_STATUS_SET, isis_mib_status_set), \
+    SW_API_DEF(SW_API_MIB_STATUS_GET, isis_mib_status_get),
+
+#define MIB_API_PARAM \
+    SW_API_DESC(SW_API_PT_MIB_GET)  \
+    SW_API_DESC(SW_API_MIB_STATUS_SET) \
+    SW_API_DESC(SW_API_MIB_STATUS_GET)
+#else
+#define MIB_API
+#define MIB_API_PARAM
+#endif
+
+
+#ifdef IN_MISC
+#define MISC_API \
+    SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, isis_frame_max_size_set), \
+    SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, isis_frame_max_size_get), \
+    SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, isis_port_unk_uc_filter_set), \
+    SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, isis_port_unk_uc_filter_get), \
+    SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, isis_port_unk_mc_filter_set), \
+    SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, isis_port_unk_mc_filter_get), \
+    SW_API_DEF(SW_API_PT_BC_FILTER_SET, isis_port_bc_filter_set), \
+    SW_API_DEF(SW_API_PT_BC_FILTER_GET, isis_port_bc_filter_get), \
+    SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, isis_cpu_port_status_set), \
+    SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, isis_cpu_port_status_get), \
+    SW_API_DEF(SW_API_PPPOE_CMD_SET, isis_pppoe_cmd_set), \
+    SW_API_DEF(SW_API_PPPOE_CMD_GET, isis_pppoe_cmd_get), \
+    SW_API_DEF(SW_API_PPPOE_STATUS_SET, isis_pppoe_status_set), \
+    SW_API_DEF(SW_API_PPPOE_STATUS_GET, isis_pppoe_status_get), \
+    SW_API_DEF(SW_API_PT_DHCP_SET, isis_port_dhcp_set), \
+    SW_API_DEF(SW_API_PT_DHCP_GET, isis_port_dhcp_get), \
+    SW_API_DEF(SW_API_ARP_CMD_SET, isis_arp_cmd_set), \
+    SW_API_DEF(SW_API_ARP_CMD_GET, isis_arp_cmd_get), \
+    SW_API_DEF(SW_API_EAPOL_CMD_SET, isis_eapol_cmd_set), \
+    SW_API_DEF(SW_API_EAPOL_CMD_GET, isis_eapol_cmd_get), \
+    SW_API_DEF(SW_API_EAPOL_STATUS_SET, isis_eapol_status_set), \
+    SW_API_DEF(SW_API_EAPOL_STATUS_GET, isis_eapol_status_get), \
+    SW_API_DEF(SW_API_RIPV1_STATUS_SET, isis_ripv1_status_set), \
+    SW_API_DEF(SW_API_RIPV1_STATUS_GET, isis_ripv1_status_get), \
+    SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_SET, isis_port_arp_req_status_set), \
+    SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_GET, isis_port_arp_req_status_get), \
+    SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_SET, isis_port_arp_ack_status_set), \
+    SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_GET, isis_port_arp_ack_status_get), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, isis_pppoe_session_table_add), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, isis_pppoe_session_table_del), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_GET, isis_pppoe_session_table_get), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_ID_SET, isis_pppoe_session_id_set), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_ID_GET, isis_pppoe_session_id_get), \
+    SW_API_DEF(SW_API_INTR_MASK_SET, isis_intr_mask_set), \
+    SW_API_DEF(SW_API_INTR_MASK_GET, isis_intr_mask_get), \
+    SW_API_DEF(SW_API_INTR_STATUS_GET, isis_intr_status_get),   \
+    SW_API_DEF(SW_API_INTR_STATUS_CLEAR, isis_intr_status_clear), \
+    SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_SET, isis_intr_port_link_mask_set), \
+    SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_GET, isis_intr_port_link_mask_get), \
+    SW_API_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, isis_intr_port_link_status_get),
+
+#define MISC_API_PARAM \
+    SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET)  \
+    SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET)  \
+    SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET)  \
+    SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET)  \
+    SW_API_DESC(SW_API_PT_BC_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_BC_FILTER_GET)  \
+    SW_API_DESC(SW_API_CPU_PORT_STATUS_SET)  \
+    SW_API_DESC(SW_API_CPU_PORT_STATUS_GET)  \
+    SW_API_DESC(SW_API_PPPOE_CMD_SET)  \
+    SW_API_DESC(SW_API_PPPOE_CMD_GET)  \
+    SW_API_DESC(SW_API_PPPOE_STATUS_SET)  \
+    SW_API_DESC(SW_API_PPPOE_STATUS_GET)  \
+    SW_API_DESC(SW_API_PT_DHCP_SET)  \
+    SW_API_DESC(SW_API_PT_DHCP_GET)  \
+    SW_API_DESC(SW_API_ARP_CMD_SET)  \
+    SW_API_DESC(SW_API_ARP_CMD_GET)  \
+    SW_API_DESC(SW_API_EAPOL_CMD_SET) \
+    SW_API_DESC(SW_API_EAPOL_CMD_GET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_ADD)  \
+    SW_API_DESC(SW_API_PPPOE_SESSION_DEL)  \
+    SW_API_DESC(SW_API_PPPOE_SESSION_GET)  \
+    SW_API_DESC(SW_API_EAPOL_STATUS_SET)  \
+    SW_API_DESC(SW_API_EAPOL_STATUS_GET)  \
+    SW_API_DESC(SW_API_RIPV1_STATUS_SET)  \
+    SW_API_DESC(SW_API_RIPV1_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_SET) \
+    SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_SET) \
+    SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_GET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_ADD) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_DEL) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_GET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_ID_SET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_ID_GET) \
+    SW_API_DESC(SW_API_INTR_MASK_SET) \
+    SW_API_DESC(SW_API_INTR_MASK_GET) \
+    SW_API_DESC(SW_API_INTR_STATUS_GET)   \
+    SW_API_DESC(SW_API_INTR_STATUS_CLEAR) \
+    SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_SET) \
+    SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_GET) \
+    SW_API_DESC(SW_API_INTR_PORT_LINK_STATUS_GET)
+#else
+#define MISC_API
+#define MISC_API_PARAM
+#endif
+
+
+#ifdef IN_LED
+#define LED_API \
+    SW_API_DEF(SW_API_LED_PATTERN_SET, isis_led_ctrl_pattern_set), \
+    SW_API_DEF(SW_API_LED_PATTERN_GET, isis_led_ctrl_pattern_get),
+
+#define LED_API_PARAM \
+    SW_API_DESC(SW_API_LED_PATTERN_SET) \
+    SW_API_DESC(SW_API_LED_PATTERN_GET)
+#else
+#define LED_API
+#define LED_API_PARAM
+#endif
+
+#ifdef IN_COSMAP
+#define COSMAP_API \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, isis_cosmap_dscp_to_pri_set), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, isis_cosmap_dscp_to_pri_get), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, isis_cosmap_dscp_to_dp_set), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, isis_cosmap_dscp_to_dp_get), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_SET, isis_cosmap_up_to_pri_set), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_GET, isis_cosmap_up_to_pri_get), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_DP_SET, isis_cosmap_up_to_dp_set), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_DP_GET, isis_cosmap_up_to_dp_get), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_SET, isis_cosmap_pri_to_queue_set), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_GET, isis_cosmap_pri_to_queue_get), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, isis_cosmap_pri_to_ehqueue_set), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, isis_cosmap_pri_to_ehqueue_get),
+
+#define COSMAP_API_PARAM \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_SET)  \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_GET)  \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_SET)  \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_GET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_SET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_GET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_DP_SET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_DP_GET)  \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_SET)  \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_GET)  \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_SET) \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_GET)
+#else
+#define COSMAP_API
+#define COSMAP_API_PARAM
+#endif
+
+#ifdef IN_SEC
+#define SEC_API \
+    SW_API_DEF(SW_API_SEC_NORM_SET, isis_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_NORM_GET, isis_sec_norm_item_get),
+
+#define SEC_API_PARAM \
+    SW_API_DESC(SW_API_SEC_NORM_SET) \
+    SW_API_DESC(SW_API_SEC_NORM_GET)
+#else
+#define SEC_API
+#define SEC_API_PARAM
+#endif
+
+#ifdef IN_IP
+#define IP_API \
+    SW_API_DEF(SW_API_IP_HOST_ADD, isis_ip_host_add), \
+    SW_API_DEF(SW_API_IP_HOST_DEL, isis_ip_host_del), \
+    SW_API_DEF(SW_API_IP_HOST_GET, isis_ip_host_get), \
+    SW_API_DEF(SW_API_IP_HOST_NEXT, isis_ip_host_next), \
+    SW_API_DEF(SW_API_IP_HOST_COUNTER_BIND, isis_ip_host_counter_bind), \
+    SW_API_DEF(SW_API_IP_HOST_PPPOE_BIND, isis_ip_host_pppoe_bind), \
+    SW_API_DEF(SW_API_IP_PT_ARP_LEARN_SET, isis_ip_pt_arp_learn_set), \
+    SW_API_DEF(SW_API_IP_PT_ARP_LEARN_GET, isis_ip_pt_arp_learn_get), \
+    SW_API_DEF(SW_API_IP_ARP_LEARN_SET, isis_ip_arp_learn_set), \
+    SW_API_DEF(SW_API_IP_ARP_LEARN_GET, isis_ip_arp_learn_get), \
+    SW_API_DEF(SW_API_IP_SOURCE_GUARD_SET, isis_ip_source_guard_set), \
+    SW_API_DEF(SW_API_IP_SOURCE_GUARD_GET, isis_ip_source_guard_get), \
+    SW_API_DEF(SW_API_IP_ARP_GUARD_SET, isis_ip_arp_guard_set), \
+    SW_API_DEF(SW_API_IP_ARP_GUARD_GET, isis_ip_arp_guard_get), \
+    SW_API_DEF(SW_API_IP_ROUTE_STATUS_SET, isis_ip_route_status_set), \
+    SW_API_DEF(SW_API_IP_ROUTE_STATUS_GET, isis_ip_route_status_get), \
+    SW_API_DEF(SW_API_IP_INTF_ENTRY_ADD, isis_ip_intf_entry_add), \
+    SW_API_DEF(SW_API_IP_INTF_ENTRY_DEL, isis_ip_intf_entry_del), \
+    SW_API_DEF(SW_API_IP_INTF_ENTRY_NEXT, isis_ip_intf_entry_next), \
+    SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, isis_ip_unk_source_cmd_set),  \
+    SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, isis_ip_unk_source_cmd_get), \
+    SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, isis_arp_unk_source_cmd_set), \
+    SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, isis_arp_unk_source_cmd_get), \
+    SW_API_DEF(SW_API_IP_AGE_TIME_SET, isis_ip_age_time_set), \
+    SW_API_DEF(SW_API_IP_AGE_TIME_GET, isis_ip_age_time_get), \
+    SW_API_DEF(SW_API_WCMP_HASH_MODE_SET, isis_ip_wcmp_hash_mode_set), \
+    SW_API_DEF(SW_API_WCMP_HASH_MODE_GET, isis_ip_wcmp_hash_mode_get),
+
+#define IP_API_PARAM \
+    SW_API_DESC(SW_API_IP_HOST_ADD) \
+    SW_API_DESC(SW_API_IP_HOST_DEL) \
+    SW_API_DESC(SW_API_IP_HOST_GET) \
+    SW_API_DESC(SW_API_IP_HOST_NEXT) \
+    SW_API_DESC(SW_API_IP_HOST_COUNTER_BIND) \
+    SW_API_DESC(SW_API_IP_HOST_PPPOE_BIND) \
+    SW_API_DESC(SW_API_IP_PT_ARP_LEARN_SET) \
+    SW_API_DESC(SW_API_IP_PT_ARP_LEARN_GET) \
+    SW_API_DESC(SW_API_IP_ARP_LEARN_SET) \
+    SW_API_DESC(SW_API_IP_ARP_LEARN_GET) \
+    SW_API_DESC(SW_API_IP_SOURCE_GUARD_SET) \
+    SW_API_DESC(SW_API_IP_SOURCE_GUARD_GET) \
+    SW_API_DESC(SW_API_IP_ARP_GUARD_SET) \
+    SW_API_DESC(SW_API_IP_ARP_GUARD_GET) \
+    SW_API_DESC(SW_API_IP_ROUTE_STATUS_SET) \
+    SW_API_DESC(SW_API_IP_ROUTE_STATUS_GET) \
+    SW_API_DESC(SW_API_IP_INTF_ENTRY_ADD)  \
+    SW_API_DESC(SW_API_IP_INTF_ENTRY_DEL)  \
+    SW_API_DESC(SW_API_IP_INTF_ENTRY_NEXT) \
+    SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_SET)  \
+    SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_GET)  \
+    SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_SET) \
+    SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_GET) \
+    SW_API_DESC(SW_API_IP_AGE_TIME_SET) \
+    SW_API_DESC(SW_API_IP_AGE_TIME_GET) \
+    SW_API_DESC(SW_API_WCMP_HASH_MODE_SET) \
+    SW_API_DESC(SW_API_WCMP_HASH_MODE_GET)
+
+#else
+#define IP_API
+#define IP_API_PARAM
+#endif
+
+#ifdef IN_NAT
+#define NAT_API \
+    SW_API_DEF(SW_API_NAT_ADD, isis_nat_add), \
+    SW_API_DEF(SW_API_NAT_DEL, isis_nat_del), \
+    SW_API_DEF(SW_API_NAT_GET, isis_nat_get), \
+    SW_API_DEF(SW_API_NAT_NEXT, isis_nat_next), \
+    SW_API_DEF(SW_API_NAT_COUNTER_BIND, isis_nat_counter_bind), \
+    SW_API_DEF(SW_API_NAPT_ADD, isis_napt_add), \
+    SW_API_DEF(SW_API_NAPT_DEL, isis_napt_del), \
+    SW_API_DEF(SW_API_NAPT_GET, isis_napt_get), \
+    SW_API_DEF(SW_API_NAPT_NEXT, isis_napt_next), \
+    SW_API_DEF(SW_API_NAPT_COUNTER_BIND, isis_napt_counter_bind), \
+    SW_API_DEF(SW_API_NAT_STATUS_SET, isis_nat_status_set), \
+    SW_API_DEF(SW_API_NAT_STATUS_GET, isis_nat_status_get), \
+    SW_API_DEF(SW_API_NAT_HASH_MODE_SET, isis_nat_hash_mode_set), \
+    SW_API_DEF(SW_API_NAT_HASH_MODE_GET, isis_nat_hash_mode_get), \
+    SW_API_DEF(SW_API_NAPT_STATUS_SET, isis_napt_status_set), \
+    SW_API_DEF(SW_API_NAPT_STATUS_GET, isis_napt_status_get), \
+    SW_API_DEF(SW_API_NAPT_MODE_SET, isis_napt_mode_set), \
+    SW_API_DEF(SW_API_NAPT_MODE_GET, isis_napt_mode_get), \
+    SW_API_DEF(SW_API_PRV_BASE_ADDR_SET, isis_nat_prv_base_addr_set), \
+    SW_API_DEF(SW_API_PRV_BASE_ADDR_GET, isis_nat_prv_base_addr_get), \
+    SW_API_DEF(SW_API_PRV_ADDR_MODE_SET, isis_nat_prv_addr_mode_set), \
+    SW_API_DEF(SW_API_PRV_ADDR_MODE_GET, isis_nat_prv_addr_mode_get), \
+    SW_API_DEF(SW_API_PUB_ADDR_ENTRY_ADD, isis_nat_pub_addr_add), \
+    SW_API_DEF(SW_API_PUB_ADDR_ENTRY_DEL, isis_nat_pub_addr_del), \
+    SW_API_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, isis_nat_pub_addr_next), \
+    SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, isis_nat_unk_session_cmd_set), \
+    SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, isis_nat_unk_session_cmd_get), \
+    SW_API_DEF(SW_API_NAT_GLOBAL_SET, isis_nat_global_set),
+
+#define NAT_API_PARAM \
+    SW_API_DESC(SW_API_NAT_ADD) \
+    SW_API_DESC(SW_API_NAT_DEL) \
+    SW_API_DESC(SW_API_NAT_GET) \
+    SW_API_DESC(SW_API_NAT_NEXT) \
+    SW_API_DESC(SW_API_NAT_COUNTER_BIND) \
+    SW_API_DESC(SW_API_NAPT_ADD) \
+    SW_API_DESC(SW_API_NAPT_DEL) \
+    SW_API_DESC(SW_API_NAPT_GET) \
+    SW_API_DESC(SW_API_NAPT_NEXT) \
+    SW_API_DESC(SW_API_NAPT_COUNTER_BIND) \
+    SW_API_DESC(SW_API_NAT_STATUS_SET) \
+    SW_API_DESC(SW_API_NAT_STATUS_GET) \
+    SW_API_DESC(SW_API_NAT_HASH_MODE_SET) \
+    SW_API_DESC(SW_API_NAT_HASH_MODE_GET) \
+    SW_API_DESC(SW_API_NAPT_STATUS_SET) \
+    SW_API_DESC(SW_API_NAPT_STATUS_GET) \
+    SW_API_DESC(SW_API_NAPT_MODE_SET) \
+    SW_API_DESC(SW_API_NAPT_MODE_GET) \
+    SW_API_DESC(SW_API_PRV_BASE_ADDR_SET) \
+    SW_API_DESC(SW_API_PRV_BASE_ADDR_GET) \
+    SW_API_DESC(SW_API_PRV_ADDR_MODE_SET) \
+    SW_API_DESC(SW_API_PRV_ADDR_MODE_GET) \
+    SW_API_DESC(SW_API_PUB_ADDR_ENTRY_ADD) \
+    SW_API_DESC(SW_API_PUB_ADDR_ENTRY_DEL) \
+    SW_API_DESC(SW_API_PUB_ADDR_ENTRY_NEXT) \
+    SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_SET) \
+    SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_GET) \
+    SW_API_DESC(SW_API_NAT_GLOBAL_SET)
+#else
+#define NAT_API
+#define NAT_API_PARAM
+#endif
+
+#ifdef IN_TRUNK
+#define TRUNK_API \
+    SW_API_DEF(SW_API_TRUNK_GROUP_SET, isis_trunk_group_set), \
+    SW_API_DEF(SW_API_TRUNK_GROUP_GET, isis_trunk_group_get), \
+    SW_API_DEF(SW_API_TRUNK_HASH_SET, isis_trunk_hash_mode_set), \
+    SW_API_DEF(SW_API_TRUNK_HASH_GET, isis_trunk_hash_mode_get), \
+    SW_API_DEF(SW_API_TRUNK_MAN_SA_SET, isis_trunk_manipulate_sa_set), \
+    SW_API_DEF(SW_API_TRUNK_MAN_SA_GET, isis_trunk_manipulate_sa_get),
+
+#define TRUNK_API_PARAM \
+    SW_API_DESC(SW_API_TRUNK_GROUP_SET) \
+    SW_API_DESC(SW_API_TRUNK_GROUP_GET) \
+    SW_API_DESC(SW_API_TRUNK_HASH_SET)  \
+    SW_API_DESC(SW_API_TRUNK_HASH_GET)  \
+    SW_API_DESC(SW_API_TRUNK_MAN_SA_SET)\
+    SW_API_DESC(SW_API_TRUNK_MAN_SA_GET)
+#else
+#define TRUNK_API
+#define TRUNK_API_PARAM
+#endif
+
+#ifdef IN_INTERFACECONTROL
+#define INTERFACECTRL_API \
+    SW_API_DEF(SW_API_MAC_MODE_SET, isis_interface_mac_mode_set), \
+    SW_API_DEF(SW_API_MAC_MODE_GET, isis_interface_mac_mode_get), \
+    SW_API_DEF(SW_API_PORT_3AZ_STATUS_SET, isis_port_3az_status_set), \
+    SW_API_DEF(SW_API_PORT_3AZ_STATUS_GET, isis_port_3az_status_get), \
+    SW_API_DEF(SW_API_PHY_MODE_SET, isis_interface_phy_mode_set), \
+    SW_API_DEF(SW_API_PHY_MODE_GET, isis_interface_phy_mode_get),
+
+#define INTERFACECTRL_API_PARAM \
+    SW_API_DESC(SW_API_MAC_MODE_SET)  \
+    SW_API_DESC(SW_API_MAC_MODE_GET)  \
+    SW_API_DESC(SW_API_PORT_3AZ_STATUS_SET)  \
+    SW_API_DESC(SW_API_PORT_3AZ_STATUS_GET)  \
+    SW_API_DESC(SW_API_PHY_MODE_SET)  \
+    SW_API_DESC(SW_API_PHY_MODE_GET)
+
+#else
+#define INTERFACECTRL_API
+#define INTERFACECTRL_API_PARAM
+#endif
+
+#define REG_API \
+    SW_API_DEF(SW_API_PHY_GET, isis_phy_get), \
+    SW_API_DEF(SW_API_PHY_SET, isis_phy_set), \
+    SW_API_DEF(SW_API_REG_GET, isis_reg_get), \
+    SW_API_DEF(SW_API_REG_SET, isis_reg_set), \
+    SW_API_DEF(SW_API_REG_FIELD_GET, isis_reg_field_get), \
+    SW_API_DEF(SW_API_REG_FIELD_SET, isis_reg_field_set), \
+    SW_API_DEF(SW_API_REG_DUMP, isis_regsiter_dump), \
+    SW_API_DEF(SW_API_DBG_REG_DUMP, isis_debug_regsiter_dump),
+
+#define REG_API_PARAM \
+    SW_API_DESC(SW_API_PHY_GET) \
+    SW_API_DESC(SW_API_PHY_SET) \
+    SW_API_DESC(SW_API_REG_GET) \
+    SW_API_DESC(SW_API_REG_SET) \
+    SW_API_DESC(SW_API_REG_FIELD_GET) \
+    SW_API_DESC(SW_API_REG_FIELD_SET) \
+    SW_API_DESC(SW_API_REG_DUMP)  \
+    SW_API_DESC(SW_API_DBG_REG_DUMP)
+
+
+#define SSDK_API \
+    SW_API_DEF(SW_API_SWITCH_RESET, isis_reset), \
+    SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \
+    PORTCONTROL_API \
+    VLAN_API \
+    PORTVLAN_API \
+    FDB_API    \
+    ACL_API    \
+    QOS_API    \
+    IGMP_API   \
+    LEAKY_API  \
+    MIRROR_API \
+    RATE_API \
+    STP_API  \
+    MIB_API  \
+    MISC_API \
+    LED_API  \
+    COSMAP_API \
+    SEC_API  \
+    IP_API \
+    NAT_API \
+    TRUNK_API \
+    INTERFACECTRL_API \
+    REG_API  \
+    SW_API_DEF(SW_API_MAX, NULL),
+
+
+#define SSDK_PARAM  \
+    SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
+    MIB_API_PARAM    \
+    LEAKY_API_PARAM  \
+    MISC_API_PARAM   \
+    IGMP_API_PARAM   \
+    MIRROR_API_PARAM \
+    PORTCONTROL_API_PARAM \
+    PORTVLAN_API_PARAM    \
+    VLAN_API_PARAM \
+    FDB_API_PARAM  \
+    QOS_API_PARAM  \
+    RATE_API_PARAM \
+    STP_API_PARAM  \
+    ACL_API_PARAM  \
+    LED_API_PARAM  \
+    COSMAP_API_PARAM \
+    SEC_API_PARAM  \
+    IP_API_PARAM \
+    NAT_API_PARAM \
+    TRUNK_API_PARAM \
+    INTERFACECTRL_API_PARAM \
+    REG_API_PARAM  \
+    SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#if (defined(USER_MODE) && defined(KERNEL_MODULE))
+#undef SSDK_API
+#undef SSDK_PARAM
+
+#define SSDK_API \
+    REG_API \
+    SW_API_DEF(SW_API_MAX, NULL),
+
+#define SSDK_PARAM  \
+    REG_API_PARAM \
+    SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _ISIS_API_H_ */
diff --git a/qca-ssdk/include/hsl/isis/isis_cosmap.h b/qca-ssdk/include/hsl/isis/isis_cosmap.h
new file mode 100755
index 0000000..c55ce7a
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_cosmap.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_cosmap ISIS_COSMAP
+ * @{
+ */
+#ifndef _ISIS_COSMAP_H_
+#define _ISIS_COSMAP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_cosmap.h"
+
+    sw_error_t isis_cosmap_init(a_uint32_t dev_id);
+
+#ifdef IN_COSMAP
+#define ISIS_COSMAP_INIT(rv, dev_id) \
+    { \
+        rv = isis_cosmap_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_COSMAP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isis_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp,
+                                a_uint32_t pri);
+
+    HSL_LOCAL sw_error_t
+    isis_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+                                a_uint32_t * pri);
+
+    HSL_LOCAL sw_error_t
+    isis_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp,
+                               a_uint32_t dp);
+
+    HSL_LOCAL sw_error_t
+    isis_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp,
+                               a_uint32_t * dp);
+
+    HSL_LOCAL sw_error_t
+    isis_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up,
+                              a_uint32_t pri);
+
+    HSL_LOCAL sw_error_t
+    isis_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up,
+                              a_uint32_t * pri);
+
+    HSL_LOCAL sw_error_t
+    isis_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up,
+                             a_uint32_t dp);
+
+    HSL_LOCAL sw_error_t
+    isis_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up,
+                             a_uint32_t * dp);
+
+    HSL_LOCAL sw_error_t
+    isis_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+                                 a_uint32_t queue);
+
+    HSL_LOCAL sw_error_t
+    isis_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+                                 a_uint32_t * queue);
+
+    HSL_LOCAL sw_error_t
+    isis_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+                                   a_uint32_t queue);
+
+    HSL_LOCAL sw_error_t
+    isis_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+                                   a_uint32_t * queue);
+
+    HSL_LOCAL sw_error_t
+    isis_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+                                  fal_egress_remark_table_t * tbl);
+
+    HSL_LOCAL sw_error_t
+    isis_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+                                  fal_egress_remark_table_t * tbl);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_COSMAP_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_fdb.h b/qca-ssdk/include/hsl/isis/isis_fdb.h
new file mode 100755
index 0000000..3399eea
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_fdb.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_fdb ISIS_FDB
+ * @{
+ */
+#ifndef _ISIS_FDB_H_
+#define _ISIS_FDB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_fdb.h"
+
+    sw_error_t isis_fdb_init(a_uint32_t dev_id);
+
+#ifdef IN_FDB
+#define ISIS_FDB_INIT(rv, dev_id) \
+    { \
+        rv = isis_fdb_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_FDB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t flag);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * op,
+                         fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+                          fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port,
+                      fal_port_t new_port, a_uint32_t fid,
+                      fal_fdb_op_t * option);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+    HSL_LOCAL sw_error_t
+    isis_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable, a_uint32_t cnt);
+
+    HSL_LOCAL sw_error_t
+    isis_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable, a_uint32_t * cnt);
+
+    HSL_LOCAL sw_error_t
+    isis_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id,
+                                       fal_port_t port_id,
+                                       fal_fwd_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    isis_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id,
+                                       fal_port_t port_id,
+                                       fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable,
+                             a_uint32_t cnt);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable,
+                             a_uint32_t * cnt);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+                          fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+    HSL_LOCAL sw_error_t
+    isis_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_FDB_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_igmp.h b/qca-ssdk/include/hsl/isis/isis_igmp.h
new file mode 100755
index 0000000..db29378
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_igmp.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_igmp ISIS_IGMP
+ * @{
+ */
+#ifndef _ISIS_IGMP_H_
+#define _ISIS_IGMP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_igmp.h"
+#include "fal/fal_multi.h"
+
+    sw_error_t
+    isis_igmp_init(a_uint32_t dev_id);
+
+#ifdef IN_IGMP
+#define ISIS_IGMP_INIT(rv, dev_id) \
+    { \
+        rv = isis_igmp_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_IGMP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isis_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts);
+
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts);
+
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue);
+
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                       a_bool_t enable, a_uint32_t cnt);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                       a_bool_t * enable, a_uint32_t * cnt);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                            fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                            fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_igmp_sg_entry_show(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _ISIS_IGMP_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/isis/isis_init.h b/qca-ssdk/include/hsl/isis/isis_init.h
new file mode 100755
index 0000000..8c31c41
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_init.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_init ISIS_INIT
+ * @{
+ */
+#ifndef _ISIS_INIT_H_
+#define _ISIS_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+
+    sw_error_t
+    isis_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+
+    sw_error_t
+    isis_cleanup(a_uint32_t dev_id);
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isis_reset(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISIS_INIT_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/isis/isis_interface_ctrl.h b/qca-ssdk/include/hsl/isis/isis_interface_ctrl.h
new file mode 100755
index 0000000..c3618cc
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_interface_ctrl.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_INTERFACE_CTRL_H_
+#define _ISIS_INTERFACE_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_interface_ctrl.h"
+
+    sw_error_t isis_interface_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_INTERFACECONTROL
+#define ISIS_INTERFACE_CTRL_INIT(rv, dev_id) \
+    { \
+        rv = isis_interface_ctrl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_INTERFACE_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isis_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isis_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isis_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+
+
+    HSL_LOCAL sw_error_t
+    isis_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+
+    HSL_LOCAL sw_error_t
+    isis_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
+
+    HSL_LOCAL sw_error_t
+    isis_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_INTERFACE_CTRL_H_ */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_ip.h b/qca-ssdk/include/hsl/isis/isis_ip.h
new file mode 100755
index 0000000..409414d
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_ip.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_IP_H_
+#define _ISIS_IP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_ip.h"
+
+    sw_error_t isis_ip_init(a_uint32_t dev_id);
+
+    sw_error_t isis_ip_reset(a_uint32_t dev_id);
+
+#ifdef IN_IP
+#define ISIS_IP_INIT(rv, dev_id) \
+    { \
+        rv = isis_ip_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define ISIS_IP_RESET(rv, dev_id) \
+    { \
+        rv = isis_ip_reset(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_IP_INIT(rv, dev_id)
+#define ISIS_IP_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isis_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                     fal_host_entry_t * host_entry);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                     fal_host_entry_t * host_entry);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                      fal_host_entry_t * host_entry);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                              a_uint32_t cnt_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                            a_uint32_t pppoe_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t flags);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * flags);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_source_guard_mode_t mode);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_source_guard_mode_t * mode);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_source_guard_mode_t mode);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_source_guard_mode_t * mode);
+
+    HSL_LOCAL sw_error_t
+    isis_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    isis_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                           fal_intf_mac_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                            fal_intf_mac_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+    HSL_LOCAL sw_error_t
+    isis_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_IP_H_ */
diff --git a/qca-ssdk/include/hsl/isis/isis_leaky.h b/qca-ssdk/include/hsl/isis/isis_leaky.h
new file mode 100755
index 0000000..02192aa
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_leaky.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_LEAKY_H_
+#define _ISIS_LEAKY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_leaky.h"
+
+    sw_error_t isis_leaky_init(a_uint32_t dev_id);
+
+#ifdef IN_LEAKY
+#define ISIS_LEAKY_INIT(rv, dev_id) \
+    { \
+        rv = isis_leaky_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_LEAKY_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isis_uc_leaky_mode_set(a_uint32_t dev_id,
+                           fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_uc_leaky_mode_get(a_uint32_t dev_id,
+                           fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_mc_leaky_mode_set(a_uint32_t dev_id,
+                           fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_mc_leaky_mode_get(a_uint32_t dev_id,
+                           fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_LEAKY_H_ */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_led.h b/qca-ssdk/include/hsl/isis/isis_led.h
new file mode 100755
index 0000000..d11b29f
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_led.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_LED_H_
+#define _ISIS_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_led.h"
+
+    sw_error_t
+    isis_led_init(a_uint32_t dev_id);
+
+#ifdef IN_LED
+#define ISIS_LED_INIT(rv, dev_id) \
+    { \
+        rv = isis_led_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_LED_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isis_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                              led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+
+    HSL_LOCAL sw_error_t
+    isis_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                              led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISIS_LED_H_ */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_mib.h b/qca-ssdk/include/hsl/isis/isis_mib.h
new file mode 100755
index 0000000..b043890
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_mib.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_MIB_H_
+#define _ISIS_MIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mib.h"
+
+    sw_error_t
+    isis_mib_init(a_uint32_t dev_id);
+
+#ifdef IN_MIB
+#define ISIS_MIB_INIT(rv, dev_id) \
+    { \
+        rv = isis_mib_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_MIB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isis_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_mib_info_t * mib_info );
+
+
+    HSL_LOCAL sw_error_t
+    isis_mib_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_mib_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISIS_MIB_H_ */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_mirror.h b/qca-ssdk/include/hsl/isis/isis_mirror.h
new file mode 100755
index 0000000..7933168
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_mirror.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_MIRROR_H_
+#define _ISIS_MIRROR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_mirror.h"
+#define  MIRROR_ANALYZER_NONE  0xf
+
+    sw_error_t isis_mirr_init(a_uint32_t dev_id);
+
+#ifdef IN_MIRROR
+#define ISIS_MIRR_INIT(rv, dev_id) \
+    { \
+        rv = isis_mirr_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_MIRR_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isis_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    isis_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id);
+
+
+    HSL_LOCAL sw_error_t
+    isis_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_MIRROR_H_ */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_misc.h b/qca-ssdk/include/hsl/isis/isis_misc.h
new file mode 100755
index 0000000..c0a70f0
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_misc.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_MISC_H_
+#define _ISIS_MISC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_misc.h"
+
+    sw_error_t isis_misc_init(a_uint32_t dev_id);
+
+#ifdef IN_MISC
+#define ISIS_MISC_INIT(rv, dev_id) \
+    { \
+        rv = isis_misc_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_MISC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isis_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size);
+
+
+    HSL_LOCAL sw_error_t
+    isis_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isis_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isis_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isis_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isis_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isis_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isis_pppoe_session_table_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+    HSL_LOCAL sw_error_t
+    isis_pppoe_session_table_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+    HSL_LOCAL sw_error_t
+    isis_pppoe_session_table_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+    HSL_LOCAL sw_error_t
+    isis_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+                              a_uint32_t id);
+
+
+    HSL_LOCAL sw_error_t
+    isis_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+                              a_uint32_t * id);
+
+
+    HSL_LOCAL sw_error_t
+    isis_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isis_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isis_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isis_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask);
+
+
+    HSL_LOCAL sw_error_t
+    isis_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask);
+
+
+    HSL_LOCAL sw_error_t
+    isis_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status);
+
+
+    HSL_LOCAL sw_error_t
+    isis_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status);
+
+
+    HSL_LOCAL sw_error_t
+    isis_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag);
+
+
+    HSL_LOCAL sw_error_t
+    isis_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag);
+
+
+    HSL_LOCAL sw_error_t
+    isis_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/isis/isis_nat.h b/qca-ssdk/include/hsl/isis/isis_nat.h
new file mode 100755
index 0000000..2dcb93c
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_nat.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_NAT_H_
+#define _ISIS_NAT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_nat.h"
+
+    sw_error_t isis_nat_init(a_uint32_t dev_id);
+
+    sw_error_t isis_nat_reset(a_uint32_t dev_id);
+
+#ifdef IN_NAT
+#define ISIS_NAT_INIT(rv, dev_id) \
+    { \
+        rv = isis_nat_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define ISIS_NAT_RESET(rv, dev_id) \
+    { \
+        rv = isis_nat_reset(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_NAT_INIT(rv, dev_id)
+#define ISIS_NAT_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isis_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                   fal_napt_entry_t * napt_entry);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+    HSL_LOCAL sw_error_t
+    isis_napt_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                  fal_napt_entry_t * napt_entry);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                 fal_nat_entry_t * nat_entry);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                          fal_nat_pub_addr_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                 fal_nat_entry_t * nat_entry);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                  fal_nat_entry_t * nat_entry);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                          a_uint32_t cnt_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isis_napt_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                  fal_napt_entry_t * napt_entry);
+
+    HSL_LOCAL sw_error_t
+    isis_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                           a_uint32_t cnt_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode);
+
+    HSL_LOCAL sw_error_t
+    isis_napt_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isis_napt_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isis_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode);
+
+    HSL_LOCAL sw_error_t
+    isis_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                           fal_nat_pub_addr_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+    HSL_LOCAL sw_error_t
+    isis_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+	HSL_LOCAL sw_error_t
+    isis_nat_global_set(a_uint32_t dev_id, a_bool_t enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_NAT_H_ */
diff --git a/qca-ssdk/include/hsl/isis/isis_nat_helper.h b/qca-ssdk/include/hsl/isis/isis_nat_helper.h
new file mode 100755
index 0000000..945079e
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_nat_helper.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_NAT_HELPER_H_
+#define _ISIS_NAT_HELPER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_nat.h"
+
+    sw_error_t nat_helper_init(a_uint32_t dev_id, a_uint32_t portbmp);
+
+    sw_error_t nat_helper_cleanup(a_uint32_t dev_id);
+
+#ifdef IN_NAT_HELPER
+#define ISIS_NAT_HELPER_INIT(rv, dev_id, portbmp) \
+    { \
+        rv = nat_helper_init(dev_id, portbmp); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define ISIS_NAT_HELPER_CLEANUP(rv, dev_id) \
+    { \
+        rv = nat_helper_cleanup(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_NAT_HELPER_INIT(rv, dev_id, portbmp)
+#define ISIS_NAT_HELPER_CLEANUP(rv, dev_id)
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_NAT_HELPER_H_ */
diff --git a/qca-ssdk/include/hsl/isis/isis_port_ctrl.h b/qca-ssdk/include/hsl/isis/isis_port_ctrl.h
new file mode 100755
index 0000000..dd136d6
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_port_ctrl.h
@@ -0,0 +1,224 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_PORT_CTRL_H_
+#define _ISIS_PORT_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_port_ctrl.h"
+
+    sw_error_t isis_port_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTCONTROL
+#define ISIS_PORT_CTRL_INIT(rv, dev_id) \
+    { \
+        rv = isis_port_ctrl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_PORT_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_duplex_t duplex);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_duplex_t * pduplex);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_port_speed_t speed);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_port_speed_t * pspeed);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * status);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t autoadv);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * autoadv);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_flowctrl_forcemode_set(a_uint32_t dev_id,
+                                     fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_flowctrl_forcemode_get(a_uint32_t dev_id,
+                                     fal_port_t port_id,
+                                     a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+                  fal_cable_status_t *cable_status, a_uint32_t *cable_len);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_port_header_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_port_header_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_port_header_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_port_header_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type);
+
+
+    HSL_LOCAL sw_error_t
+    isis_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status);
+
+    HSL_LOCAL sw_error_t
+    isis_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isis_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isis_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_PORT_CTRL_H_ */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_portvlan.h b/qca-ssdk/include/hsl/isis/isis_portvlan.h
new file mode 100755
index 0000000..a4ef074
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_portvlan.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_PORTVLAN_H_
+#define _ISIS_PORTVLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_portvlan.h"
+
+    sw_error_t isis_portvlan_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTVLAN
+#define ISIS_PORTVLAN_INIT(rv, dev_id) \
+    { \
+        rv = isis_portvlan_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_PORTVLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_1qmode_t port_1qmode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_1qmode_t * pport_1qmode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pt_1q_egmode_t port_egvlanmode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pt_1q_egmode_t * pport_egvlanmode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t mem_port_id);
+
+
+    HSL_LOCAL sw_error_t
+    isis_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t mem_port_id);
+
+
+    HSL_LOCAL sw_error_t
+    isis_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_pbmp_t mem_port_map);
+
+
+    HSL_LOCAL sw_error_t
+    isis_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pbmp_t * mem_port_map);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid);
+
+
+    HSL_LOCAL sw_error_t
+    isis_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pt_invlan_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pt_invlan_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+                      a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+                      a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t vid);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * vid);
+
+    HSL_LOCAL sw_error_t
+    isis_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t vid);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * vid);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_vlan_propagation_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_vlan_propagation_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t * iterator, fal_vlan_trans_entry_t * entry);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isis_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_PORTVLAN_H */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_qos.h b/qca-ssdk/include/hsl/isis/isis_qos.h
new file mode 100755
index 0000000..58c022a
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_qos.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_QOS_H_
+#define _ISIS_QOS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_qos.h"
+
+    sw_error_t isis_qos_init(a_uint32_t dev_id);
+
+#ifdef IN_QOS
+#define ISIS_QOS_INIT(rv, dev_id) \
+    { \
+        rv = isis_qos_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_QOS_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_queue_tx_buf_status_set(a_uint32_t dev_id,
+                                     fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_queue_tx_buf_status_get(a_uint32_t dev_id,
+                                     fal_port_t port_id,
+                                     a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_queue_t queue_id,
+                                 a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_queue_t queue_id,
+                                 a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_qos_mode_t mode, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_qos_mode_t mode, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_qos_mode_t mode, a_uint32_t pri);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_qos_mode_t mode, a_uint32_t * pri);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                               fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                               fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_uint32_t spri);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_uint32_t * spri);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_uint32_t cpri);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_uint32_t * cpri);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_QOS_H_ */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_rate.h b/qca-ssdk/include/hsl/isis/isis_rate.h
new file mode 100755
index 0000000..375e1fa
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_rate.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_RATE_H_
+#define _ISIS_RATE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_rate.h"
+
+    sw_error_t isis_rate_init(a_uint32_t dev_id);
+
+#ifdef IN_RATE
+#define ISIS_RATE_INIT(rv, dev_id) \
+    { \
+        rv = isis_rate_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_RATE_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isis_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_port_policer_t * policer);
+
+    HSL_LOCAL sw_error_t
+    isis_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_port_policer_t * policer);
+
+    HSL_LOCAL sw_error_t
+    isis_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable,
+                              fal_egress_shaper_t * shaper);
+
+    HSL_LOCAL sw_error_t
+    isis_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable,
+                              fal_egress_shaper_t * shaper);
+
+    HSL_LOCAL sw_error_t
+    isis_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_bool_t enable,
+                               fal_egress_shaper_t * shaper);
+
+    HSL_LOCAL sw_error_t
+    isis_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_bool_t * enable,
+                               fal_egress_shaper_t * shaper);
+
+    HSL_LOCAL sw_error_t
+    isis_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+                              fal_acl_policer_t * policer);
+
+    HSL_LOCAL sw_error_t
+    isis_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+                              fal_acl_policer_t * policer);
+
+    HSL_LOCAL sw_error_t
+    isis_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_uint32_t  number);
+
+    HSL_LOCAL sw_error_t
+    isis_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_uint32_t  *number);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_RATE_H_ */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_reg.h b/qca-ssdk/include/hsl/isis/isis_reg.h
new file mode 100755
index 0000000..d45975b
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_reg.h
@@ -0,0 +1,5229 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _ISIS_REG_H_
+#define _ISIS_REG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#define S16E_DEVICE_ID  0x11
+#define S17_DEVICE_ID   0x12
+#define S17_REVISION_A  0x01
+
+#define MAX_ENTRY_LEN   128
+
+#define HSL_RW 1
+#define HSL_RO 0
+
+
+    /* ISIS Mask Control Register */
+#define MASK_CTL
+#define MASK_CTL_ID               0
+#define MASK_CTL_OFFSET           0x0000
+#define MASK_CTL_E_LENGTH         4
+#define MASK_CTL_E_OFFSET         0
+#define MASK_CTL_NR_E             1
+
+#define SOFT_RST
+#define MASK_CTL_SOFT_RST_BOFFSET             31
+#define MASK_CTL_SOFT_RST_BLEN                1
+#define MASK_CTL_SOFT_RST_FLAG                HSL_RW
+
+#define LOAD_EEPROM
+#define MASK_CTL_LOAD_EEPROM_BOFFSET          16
+#define MASK_CTL_LOAD_EEPROM_BLEN             1
+#define MASK_CTL_LOAD_EEPROM_FLAG             HSL_RW
+
+#define DEVICE_ID
+#define MASK_CTL_DEVICE_ID_BOFFSET            8
+#define MASK_CTL_DEVICE_ID_BLEN               8
+#define MASK_CTL_DEVICE_ID_FLAG               HSL_RO
+
+#define REV_ID
+#define MASK_CTL_REV_ID_BOFFSET               0
+#define MASK_CTL_REV_ID_BLEN                  8
+#define MASK_CTL_REV_ID_FLAG                  HSL_RO
+
+
+
+
+    /* Port0 Pad Control Register */
+#define PORT0_PAD_CTRL
+#define PORT0_PAD_CTRL_ID                                      0
+#define PORT0_PAD_CTRL_OFFSET                                  0x0004
+#define PORT0_PAD_CTRL_E_LENGTH                                4
+#define PORT0_PAD_CTRL_E_OFFSET                                0
+#define PORT0_PAD_CTRL_NR_E                                    1
+
+#define MAC0_RGMII_EN
+#define PORT0_PAD_CTRL_MAC0_RGMII_EN_BOFFSET                   26
+#define PORT0_PAD_CTRL_MAC0_RGMII_EN_BLEN                      1
+#define PORT0_PAD_CTRL_MAC0_RGMII_EN_FLAG                      HSL_RW
+
+#define MAC0_RGMII_TXCLK_DELAY_EN
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_BOFFSET       25
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_BLEN          1
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_FLAG          HSL_RW
+
+#define MAC0_RGMII_RXCLK_DELAY_EN
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_BOFFSET       24
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_BLEN          1
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_FLAG          HSL_RW
+
+#define MAC0_RGMII_TXCLK_DELAY_SEL
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_BOFFSET      22
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_BLEN         2
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_FLAG         HSL_RW
+
+#define MAC0_RGMII_RXCLK_DELAY_SEL
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_BOFFSET      20
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_BLEN         2
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_FLAG         HSL_RW
+
+#define SGMII_CLK125M_RX_SEL
+#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_BOFFSET            19
+#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_BLEN               1
+#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_FLAG               HSL_RW
+
+#define SGMII_CLK125M_TX_SEL
+#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_BOFFSET            18
+#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_BLEN               1
+#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_FLAG               HSL_RW
+
+#define MAC0_PHY_GMII_EN
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_BOFFSET                14
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_BLEN                   1
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_FLAG                   HSL_RW
+
+#define MAC0_PHY_GMII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_BOFFSET         13
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_BLEN            1
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_FLAG            HSL_RW
+
+#define MAC0_PHY_GMII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_BOFFSET         12
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_BLEN            1
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_FLAG            HSL_RW
+
+#define MAC0_PHY_MII_PIPE_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_BOFFSET     11
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_BLEN        1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_FLAG        HSL_RW
+
+#define MAC0_PHY_MII_EN
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_BOFFSET                 10
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_BLEN                    1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_FLAG                    HSL_RW
+
+#define MAC0_PHY_MII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_BOFFSET          9
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_BLEN             1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_FLAG             HSL_RW
+
+#define MAC0_PHY_MII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_BOFFSET          8
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_BLEN             1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_FLAG             HSL_RW
+
+#define MAC0_SGMII_EN
+#define PORT0_PAD_CTRL_MAC0_SGMII_EN_BOFFSET                   7
+#define PORT0_PAD_CTRL_MAC0_SGMII_EN_BLEN                      1
+#define PORT0_PAD_CTRL_MAC0_SGMII_EN_FLAG                      HSL_RW
+
+#define MAC0_MAC_GMII_EN
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_BOFFSET                6
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_BLEN                   1
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_FLAG                   HSL_RW
+
+#define MAC0_MAC_GMII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_BOFFSET         5
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_BLEN            1
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_FLAG            HSL_RW
+
+#define MAC0_MAC_GMII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_BOFFSET         4
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_BLEN            1
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_FLAG            HSL_RW
+
+#define MAC0_MAC_MII_EN
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_BOFFSET                 2
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_BLEN                    1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_FLAG                    HSL_RW
+
+#define MAC0_MAC_MII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BOFFSET          1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BLEN             1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_FLAG             HSL_RW
+
+#define MAC0_MAC_MII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_BOFFSET          0
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_BLEN             1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_FLAG             HSL_RW
+
+
+
+
+    /* Port5 Pad Control Register */
+#define PORT5_PAD_CTRL
+#define PORT5_PAD_CTRL_ID                                      0
+#define PORT5_PAD_CTRL_OFFSET                                  0x0008
+#define PORT5_PAD_CTRL_E_LENGTH                                4
+#define PORT5_PAD_CTRL_E_OFFSET                                0
+#define PORT5_PAD_CTRL_NR_E                                    1
+
+#define MAC5_RGMII_EN
+#define PORT5_PAD_CTRL_MAC5_RGMII_EN_BOFFSET                   26
+#define PORT5_PAD_CTRL_MAC5_RGMII_EN_BLEN                      1
+#define PORT5_PAD_CTRL_MAC5_RGMII_EN_FLAG                      HSL_RW
+
+#define MAC5_RGMII_TXCLK_DELAY_EN
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_BOFFSET       25
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_BLEN          1
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_FLAG          HSL_RW
+
+#define MAC5_RGMII_RXCLK_DELAY_EN
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_BOFFSET       24
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_BLEN          1
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_FLAG          HSL_RW
+
+#define MAC5_RGMII_TXCLK_DELAY_SEL
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_BOFFSET      22
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_BLEN         2
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_FLAG         HSL_RW
+
+#define MAC5_RGMII_RXCLK_DELAY_SEL
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_BOFFSET      20
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_BLEN         2
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_FLAG         HSL_RW
+
+#define MAC5_PHY_MII_PIPE_RXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_BOFFSET     11
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_BLEN        1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_FLAG        HSL_RW
+
+#define MAC5_PHY_MII_EN
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_BOFFSET                 10
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_BLEN                    1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_FLAG                    HSL_RW
+
+#define MAC5_PHY_MII_TXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_BOFFSET          9
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_BLEN             1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_FLAG             HSL_RW
+
+#define MAC5_PHY_MII_RXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_BOFFSET          8
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_BLEN             1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_FLAG             HSL_RW
+
+#define MAC5_MAC_MII_EN
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_BOFFSET                 2
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_BLEN                    1
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_FLAG                    HSL_RW
+
+#define MAC5_MAC_MII_TXCLK_SEL
+#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BOFFSET          1
+#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BLEN             1
+#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_FLAG             HSL_RW
+
+#define MAC5_MAC_MII_RXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_BOFFSET          0
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_BLEN             1
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_FLAG             HSL_RW
+
+
+
+
+    /* Port6 Pad Control Register */
+#define PORT6_PAD_CTRL
+#define PORT6_PAD_CTRL_ID                                      0
+#define PORT6_PAD_CTRL_OFFSET                                  0x000c
+#define PORT6_PAD_CTRL_E_LENGTH                                4
+#define PORT6_PAD_CTRL_E_OFFSET                                0
+#define PORT6_PAD_CTRL_NR_E                                    1
+
+#define MAC6_RGMII_EN
+#define PORT6_PAD_CTRL_MAC6_RGMII_EN_BOFFSET                   26
+#define PORT6_PAD_CTRL_MAC6_RGMII_EN_BLEN                      1
+#define PORT6_PAD_CTRL_MAC6_RGMII_EN_FLAG                      HSL_RW
+
+#define MAC6_RGMII_TXCLK_DELAY_EN
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_BOFFSET       25
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_BLEN          1
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_FLAG          HSL_RW
+
+#define MAC6_RGMII_RXCLK_DELAY_EN
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_BOFFSET       24
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_BLEN          1
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_FLAG          HSL_RW
+
+#define MAC6_RGMII_TXCLK_DELAY_SEL
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_BOFFSET      22
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_BLEN         2
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_FLAG         HSL_RW
+
+#define MAC6_RGMII_RXCLK_DELAY_SEL
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_BOFFSET      20
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_BLEN         2
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_FLAG         HSL_RW
+
+#define PHY4_MII_EN
+#define PORT6_PAD_CTRL_PHY4_MII_EN_BOFFSET                     18
+#define PORT6_PAD_CTRL_PHY4_MII_EN_BLEN                        1
+#define PORT6_PAD_CTRL_PHY4_MII_EN_FLAG                        HSL_RW
+
+#define PHY4_RGMII_EN
+#define PORT6_PAD_CTRL_PHY4_RGMII_EN_BOFFSET                   17
+#define PORT6_PAD_CTRL_PHY4_RGMII_EN_BLEN                      1
+#define PORT6_PAD_CTRL_PHY4_RGMII_EN_FLAG                      HSL_RW
+
+#define PHY4_GMII_EN
+#define PORT6_PAD_CTRL_PHY4_GMII_EN_BOFFSET                    16
+#define PORT6_PAD_CTRL_PHY4_GMII_EN_BLEN                       1
+#define PORT6_PAD_CTRL_PHY4_GMII_EN_FLAG                       HSL_RW
+
+#define MAC6_PHY_GMII_EN
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_BOFFSET                14
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_BLEN                   1
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_FLAG                   HSL_RW
+
+#define MAC6_PHY_GMII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_BOFFSET         13
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_BLEN            1
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_FLAG            HSL_RW
+
+#define MAC6_PHY_GMII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_BOFFSET         12
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_BLEN            1
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_FLAG            HSL_RW
+
+#define MAC6_PHY_MII_PIPE_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_BOFFSET     11
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_BLEN        1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_FLAG        HSL_RW
+
+#define MAC6_PHY_MII_EN
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_BOFFSET                 10
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_BLEN                    1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_FLAG                    HSL_RW
+
+#define MAC6_PHY_MII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_BOFFSET          9
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_BLEN             1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_FLAG             HSL_RW
+
+#define MAC6_PHY_MII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_BOFFSET          8
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_BLEN             1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_FLAG             HSL_RW
+
+#define MAC6_SGMII_EN
+#define PORT6_PAD_CTRL_MAC6_SGMII_EN_BOFFSET                   7
+#define PORT6_PAD_CTRL_MAC6_SGMII_EN_BLEN                      1
+#define PORT6_PAD_CTRL_MAC6_SGMII_EN_FLAG                      HSL_RW
+
+#define MAC6_MAC_GMII_EN
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_BOFFSET                6
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_BLEN                   1
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_FLAG                   HSL_RW
+
+#define MAC6_MAC_GMII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_BOFFSET         5
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_BLEN            1
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_FLAG            HSL_RW
+
+#define MAC6_MAC_GMII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_BOFFSET         4
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_BLEN            1
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_FLAG            HSL_RW
+
+#define MAC6_MAC_MII_EN
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_BOFFSET                 2
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_BLEN                    1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_FLAG                    HSL_RW
+
+#define MAC6_MAC_MII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_BOFFSET          1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_BLEN             1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_FLAG             HSL_RW
+
+#define MAC6_MAC_MII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_BOFFSET          0
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_BLEN             1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_FLAG             HSL_RW
+
+
+
+
+    /* SGMII Control Register */
+#define SGMII_CTRL
+#define SGMII_CTRL_ID                                          0
+#define SGMII_CTRL_OFFSET                                      0x00e0
+#define SGMII_CTRL_E_LENGTH                                    4
+#define SGMII_CTRL_E_OFFSET                                    0
+#define SGMII_CTRL_NR_E                                        1
+
+#define FULL_25M
+#define SGMII_CTRL_FULL_25M_BOFFSET                            31
+#define SGMII_CTRL_FULL_25M_BLEN                               1
+#define SGMII_CTRL_FULL_25M_FLAG                               HSL_RW
+
+#define HALF_25M
+#define SGMII_CTRL_HALF_25M_BOFFSET                            30
+#define SGMII_CTRL_HALF_25M_BLEN                               1
+#define SGMII_CTRL_HALF_25M_FLAG                               HSL_RW
+
+#define REMOTE_25M
+#define SGMII_CTRL_REMOTE_25M_BOFFSET                          28
+#define SGMII_CTRL_REMOTE_25M_BLEN                             2
+#define SGMII_CTRL_REMOTE_25M_FLAG                             HSL_RW
+
+#define NEXT_PAGE_25M
+#define SGMII_CTRL_NEXT_PAGE_25M_BOFFSET                       27
+#define SGMII_CTRL_NEXT_PAGE_25M_BLEN                          1
+#define SGMII_CTRL_NEXT_PAGE_25M_FLAG                          HSL_RW
+
+#define PAUSE_25M
+#define SGMII_CTRL_PAUSE_25M_BOFFSET                           26
+#define SGMII_CTRL_PAUSE_25M_BLEN                              1
+#define SGMII_CTRL_PAUSE_25M_FLAG                              HSL_RW
+
+#define ASYM_PAUSE_25M
+#define SGMII_CTRL_ASYM_PAUSE_25M_BOFFSET                      25
+#define SGMII_CTRL_ASYM_PAUSE_25M_BLEN                         1
+#define SGMII_CTRL_ASYM_PAUSE_25M_FLAG                         HSL_RW
+
+#define PAUSE_SG_25M
+#define SGMII_CTRL_PAUSE_SG_25M_BOFFSET                        24
+#define SGMII_CTRL_PAUSE_SG_25M_BLEN                           1
+#define SGMII_CTRL_PAUSE_SG_25M_FLAG                           HSL_RW
+
+#define PAUSE_SG_25M
+#define SGMII_CTRL_PAUSE_SG_25M_BOFFSET                        24
+#define SGMII_CTRL_PAUSE_SG_25M_BLEN                           1
+#define SGMII_CTRL_PAUSE_SG_25M_FLAG                           HSL_RW
+
+#define MODE_CTRL_25M
+#define SGMII_CTRL_MODE_CTRL_25M_BOFFSET                       22
+#define SGMII_CTRL_MODE_CTRL_25M_BLEN                          2
+#define SGMII_CTRL_MODE_CTRL_25M_FLAG                          HSL_RW
+
+#define MR_LOOPBACK
+#define SGMII_CTRL_MR_LOOPBACK_BOFFSET                         21
+#define SGMII_CTRL_MR_LOOPBACK_BLEN                            1
+#define SGMII_CTRL_MR_LOOPBACK_FLAG                            HSL_RW
+
+#define MR_REG4_25M
+#define SGMII_CTRL_MR_REG4_25M_BOFFSET                         20
+#define SGMII_CTRL_MR_REG4_25M_BLEN                            1
+#define SGMII_CTRL_MR_REG4_25M_FLAG                            HSL_RW
+
+#define AUTO_LPI_25M
+#define SGMII_CTRL_AUTO_LPI_25M_BOFFSET                        19
+#define SGMII_CTRL_AUTO_LPI_25M_BLEN                           1
+#define SGMII_CTRL_AUTO_LPI_25M_FLAG                           HSL_RW
+
+#define PRBS_EN
+#define SGMII_CTRL_PRBS_EN_BOFFSET                             18
+#define SGMII_CTRL_PRBS_EN_BLEN                                1
+#define SGMII_CTRL_PRBS_EN_FLAG                                HSL_RW
+
+#define SGMII_TH_LOS1
+#define SGMII_CTRL_SGMII_TH_LOS1_BOFFSET                       17
+#define SGMII_CTRL_SGMII_TH_LOS1_BLEN                          1
+#define SGMII_CTRL_SGMII_TH_LOS1_FLAG                          HSL_RW
+
+#define DIS_AUTO_LPI_25M
+#define SGMII_CTRL_DIS_AUTO_LPI_25M_BOFFSET                    16
+#define SGMII_CTRL_DIS_AUTO_LPI_25M_BLEN                       1
+#define SGMII_CTRL_DIS_AUTO_LPI_25M_FLAG                       HSL_RW
+
+#define SGMII_TH_LOS0
+#define SGMII_CTRL_SGMII_TH_LOS0_BOFFSET                       15
+#define SGMII_CTRL_SGMII_TH_LOS0_BLEN                          1
+#define SGMII_CTRL_SGMII_TH_LOS0_FLAG                          HSL_RW
+
+#define SGMII_CDR_BW
+#define SGMII_CTRL_SGMII_CDR_BW_BOFFSET                        13
+#define SGMII_CTRL_SGMII_CDR_BW_BLEN                           2
+#define SGMII_CTRL_SGMII_CDR_BW_FLAG                           HSL_RW
+
+#define SGMII_TXDR_CTRL
+#define SGMII_CTRL_SGMII_TXDR_CTRL_BOFFSET                     10
+#define SGMII_CTRL_SGMII_TXDR_CTRL_BLEN                        3
+#define SGMII_CTRL_SGMII_TXDR_CTRL_FLAG                        HSL_RW
+
+#define SGMII_FIBER_MODE
+#define SGMII_CTRL_SGMII_FIBER_MODE_BOFFSET                    8
+#define SGMII_CTRL_SGMII_FIBER_MODE_BLEN                       2
+#define SGMII_CTRL_SGMII_FIBER_MODE_FLAG                       HSL_RW
+
+#define SGMII_SEL_125M
+#define SGMII_CTRL_SGMII_SEL_125M_BOFFSET                      7
+#define SGMII_CTRL_SGMII_SEL_125M_BLEN                         1
+#define SGMII_CTRL_SGMII_SEL_125M_FLAG                         HSL_RW
+
+#define SGMII_PLL_BW
+#define SGMII_CTRL_SGMII_PLL_BW_BOFFSET                        6
+#define SGMII_CTRL_SGMII_PLL_BW_BLEN                           1
+#define SGMII_CTRL_SGMII_PLL_BW_FLAG                           HSL_RW
+
+#define SGMII_HALFTX
+#define SGMII_CTRL_SGMII_HALFTX_BOFFSET                        5
+#define SGMII_CTRL_SGMII_HALFTX_BLEN                           1
+#define SGMII_CTRL_SGMII_HALFTX_FLAG                           HSL_RW
+
+#define SGMII_EN_SD
+#define SGMII_CTRL_SGMII_EN_SD_BOFFSET                         4
+#define SGMII_CTRL_SGMII_EN_SD_BLEN                            1
+#define SGMII_CTRL_SGMII_EN_SD_FLAG                            HSL_RW
+
+#define SGMII_EN_TX
+#define SGMII_CTRL_SGMII_EN_TX_BOFFSET                         3
+#define SGMII_CTRL_SGMII_EN_TX_BLEN                            1
+#define SGMII_CTRL_SGMII_EN_TX_FLAG                            HSL_RW
+
+#define SGMII_EN_RX
+#define SGMII_CTRL_SGMII_EN_RX_BOFFSET                         2
+#define SGMII_CTRL_SGMII_EN_RX_BLEN                            1
+#define SGMII_CTRL_SGMII_EN_RX_FLAG                            HSL_RW
+
+#define SGMII_EN_PLL
+#define SGMII_CTRL_SGMII_EN_PLL_BOFFSET                        1
+#define SGMII_CTRL_SGMII_EN_PLL_BLEN                           1
+#define SGMII_CTRL_SGMII_EN_PLL_FLAG                           HSL_RW
+
+#define SGMII_EN_LCKDT
+#define SGMII_CTRL_SGMII_EN_LCKDT_BOFFSET                      0
+#define SGMII_CTRL_SGMII_EN_LCKDT_BLEN                         1
+#define SGMII_CTRL_SGMII_EN_LCKDT_FLAG                         HSL_RW
+
+
+
+
+    /* Power On Strip Register */
+#define POWER_STRIP
+#define POWER_STRIP_ID                                         0
+#define POWER_STRIP_OFFSET                                     0x0010
+#define POWER_STRIP_E_LENGTH                                   4
+#define POWER_STRIP_E_OFFSET                                   0
+#define POWER_STRIP_NR_E                                       1
+
+#define POWER_ON_SEL
+#define POWER_STRIP_POWER_ON_SEL_BOFFSET                       31
+#define POWER_STRIP_POWER_ON_SEL_BLEN                          1
+#define POWER_STRIP_POWER_ON_SEL_FLAG                          HSL_RW
+
+#define PKG128_EN
+#define POWER_STRIP_PKG128_EN_BOFFSET                          30
+#define POWER_STRIP_PKG128_EN_BLEN                             1
+#define POWER_STRIP_PKG128_EN_FLAG                             HSL_RW
+
+#define PKG128_EN_LED
+#define POWER_STRIP_PKG128_EN_LED_BOFFSET                      29
+#define POWER_STRIP_PKG128_EN_LED_BLEN                         1
+#define POWER_STRIP_PKG128_EN_LED_FLAG                         HSL_RW
+
+#define S16_MODE
+#define POWER_STRIP_S16_MODE_BOFFSET                           28
+#define POWER_STRIP_S16_MODE_BLEN                              1
+#define POWER_STRIP_S16_MODE_FLAG                              HSL_RW
+
+#define INPUT_MODE
+#define POWER_STRIP_INPUT_MODE_BOFFSET                         27
+#define POWER_STRIP_INPUT_MODE_BLEN                            1
+#define POWER_STRIP_INPUT_MODE_FLAG                            HSL_RW
+
+#define SGMII_POWER_ON_SEL
+#define POWER_STRIP_SGMII_POWER_ON_SEL_BOFFSET                 26
+#define POWER_STRIP_SGMII_POWER_ON_SEL_BLEN                    1
+#define POWER_STRIP_SGMII_POWER_ON_SEL_FLAG                    HSL_RW
+
+#define SPI_EN
+#define POWER_STRIP_SPI_EN_BOFFSET                             25
+#define POWER_STRIP_SPI_EN_BLEN                                1
+#define POWER_STRIP_SPI_EN_FLAG                                HSL_RW
+
+#define LED_OPEN_EN
+#define POWER_STRIP_LED_OPEN_EN_BOFFSET                        24
+#define POWER_STRIP_LED_OPEN_EN_BLEN                           1
+#define POWER_STRIP_LED_OPEN_EN_FLAG                           HSL_RW
+
+#define SGMII_RXIMP_50_70
+#define POWER_STRIP_SGMII_RXIMP_50_70_BOFFSET                  23
+#define POWER_STRIP_SGMII_RXIMP_50_70_BLEN                     1
+#define POWER_STRIP_SGMII_RXIMP_50_70_FLAG                     HSL_RW
+
+#define SGMII_TXIMP_50_70
+#define POWER_STRIP_SGMII_TXIMP_50_70_BOFFSET                  22
+#define POWER_STRIP_SGMII_TXIMP_50_70_BLEN                     1
+#define POWER_STRIP_SGMII_TXIMP_50_70_FLAG                     HSL_RW
+
+#define SGMII_SIGNAL_DETECT
+#define POWER_STRIP_SGMII_SIGNAL_DETECT_BOFFSET                21
+#define POWER_STRIP_SGMII_SIGNAL_DETECT_BLEN                   1
+#define POWER_STRIP_SGMII_SIGNAL_DETECT_FLAG                   HSL_RW
+
+#define LPW_EXIT
+#define POWER_STRIP_LPW_EXIT_BOFFSET                           20
+#define POWER_STRIP_LPW_EXIT_BLEN                              1
+#define POWER_STRIP_LPW_EXIT_FLAG                              HSL_RW
+
+#define MAN_EN
+#define POWER_STRIP_MAN_EN_BOFFSET                             18
+#define POWER_STRIP_MAN_EN_BLEN                                1
+#define POWER_STRIP_MAN_EN_FLAG                                HSL_RW
+
+#define HIB_EN
+#define POWER_STRIP_HIB_EN_BOFFSET                             17
+#define POWER_STRIP_HIB_EN_BLEN                                1
+#define POWER_STRIP_HIB_EN_FLAG                                HSL_RW
+
+#define POWER_DOWN_HW
+#define POWER_STRIP_POWER_DOWN_HW_BOFFSET                      16
+#define POWER_STRIP_POWER_DOWN_HW_BLEN                         1
+#define POWER_STRIP_POWER_DOWN_HW_FLAG                         HSL_RW
+
+#define BIST_BYPASS_CEL
+#define POWER_STRIP_BIST_BYPASS_CEL_BOFFSET                    15
+#define POWER_STRIP_BIST_BYPASS_CEL_BLEN                       1
+#define POWER_STRIP_BIST_BYPASS_CEL_FLAG                       HSL_RW
+
+#define BIST_BYPASS_CSR
+#define POWER_STRIP_BIST_BYPASS_CSR_BOFFSET                    14
+#define POWER_STRIP_BIST_BYPASS_CSR_BLEN                       1
+#define POWER_STRIP_BIST_BYPASS_CSR_FLAG                       HSL_RW
+
+#define HIB_PULSE_HW
+#define POWER_STRIP_HIB_PULSE_HW_BOFFSET                       12
+#define POWER_STRIP_HIB_PULSE_HW_BLEN                          1
+#define POWER_STRIP_HIB_PULSE_HW_FLAG                          HSL_RW
+
+#define GATE_25M_EN
+#define POWER_STRIP_GATE_25M_EN_BOFFSET                        10
+#define POWER_STRIP_GATE_25M_EN_BLEN                           1
+#define POWER_STRIP_GATE_25M_EN_FLAG                           HSL_RW
+
+#define SEL_ANA_RST
+#define POWER_STRIP_SEL_ANA_RST_BOFFSET                        9
+#define POWER_STRIP_SEL_ANA_RST_BLEN                           1
+#define POWER_STRIP_SEL_ANA_RST_FLAG                           HSL_RW
+
+#define SERDES_EN
+#define POWER_STRIP_SERDES_EN_BOFFSET                          8
+#define POWER_STRIP_SERDES_EN_BLEN                             1
+#define POWER_STRIP_SERDES_EN_FLAG                             HSL_RW
+
+#define SERDES_AN_EN
+#define POWER_STRIP_SERDES_AN_EN_BOFFSET                       7
+#define POWER_STRIP_SERDES_AN_EN_BLEN                          1
+#define POWER_STRIP_SERDES_AN_EN_FLAG                          HSL_RW
+
+#define RTL_MODE
+#define POWER_STRIP_RTL_MODE_BOFFSET                           5
+#define POWER_STRIP_RTL_MODE_BLEN                              1
+#define POWER_STRIP_RTL_MODE_FLAG                              HSL_RW
+
+#define PAD_CTRL_FOR25M
+#define POWER_STRIP_PAD_CTRL_FOR25M_BOFFSET                    3
+#define POWER_STRIP_PAD_CTRL_FOR25M_BLEN                       2
+#define POWER_STRIP_PAD_CTRL_FOR25M_FLAG                       HSL_RW
+
+#define PAD_CTRL
+#define POWER_STRIP_PAD_CTRL_BOFFSET                           0
+#define POWER_STRIP_PAD_CTRL_BLEN                              2
+#define POWER_STRIP_PAD_CTRL_FLAG                              HSL_RW
+
+
+
+
+    /* Global Interrupt Status Register1 */
+#define GBL_INT_STATUS1
+#define GBL_INT_STATUS1_ID             1
+#define GBL_INT_STATUS1_OFFSET         0x0024
+#define GBL_INT_STATUS1_E_LENGTH       4
+#define GBL_INT_STATUS1_E_OFFSET       0
+#define GBL_INT_STATUS1_NR_E           1
+
+#define PHY_INT_S
+#define GBL_INT_STATUS1_PHY_INT_S_BOFFSET         15
+#define GBL_INT_STATUS1_PHY_INT_S_BLEN            1
+#define GBL_INT_STATUS1_PHY_INT_S_FLAG            HSL_RO
+
+
+
+
+    /* Global Interrupt Mask Register1 */
+#define GBL_INT_MASK1
+#define GBL_INT_MASK1_ID             1
+#define GBL_INT_MASK1_OFFSET         0x002c
+#define GBL_INT_MASK1_E_LENGTH       4
+#define GBL_INT_MASK1_E_OFFSET       0
+#define GBL_INT_MASK1_NR_E           1
+
+#define PHY_INT_M
+#define GBL_INT_MASK1_PHY_INT_M_BOFFSET           15
+#define GBL_INT_MASK1_PHY_INT_M_BLEN              1
+#define GBL_INT_MASK1_PHY_INT_M_FLAG              HSL_RO
+
+
+
+
+    /* Module Enable Register */
+#define MOD_ENABLE
+#define MOD_ENABLE_OFFSET           0x0030
+#define MOD_ENABLE_E_LENGTH         4
+#define MOD_ENABLE_E_OFFSET         0
+#define MOD_ENABLE_NR_E             1
+
+#define L3_EN
+#define MOD_ENABLE_L3_EN_BOFFSET                  2
+#define MOD_ENABLE_L3_EN_BLEN                     1
+#define MOD_ENABLE_L3_EN_FLAG                     HSL_RW
+
+#define ACL_EN
+#define MOD_ENABLE_ACL_EN_BOFFSET                 1
+#define MOD_ENABLE_ACL_EN_BLEN                    1
+#define MOD_ENABLE_ACL_EN_FLAG                    HSL_RW
+
+#define MIB_EN
+#define MOD_ENABLE_MIB_EN_BOFFSET                 0
+#define MOD_ENABLE_MIB_EN_BLEN                    1
+#define MOD_ENABLE_MIB_EN_FLAG                    HSL_RW
+
+
+
+
+    /* MIB Function Register */
+#define MIB_FUNC
+#define MIB_FUNC_OFFSET           0x0034
+#define MIB_FUNC_E_LENGTH         4
+#define MIB_FUNC_E_OFFSET         0
+#define MIB_FUNC_NR_E             1
+
+#define MIB_FUN
+#define MIB_FUNC_MIB_FUN_BOFFSET               24
+#define MIB_FUNC_MIB_FUN_BLEN                  3
+#define MIB_FUNC_MIB_FUN_FLAG                  HSL_RW
+
+#define MIB_BUSY
+#define MIB_FUNC_MIB_BUSY_BOFFSET              17
+#define MIB_FUNC_MIB_BUSY_BLEN                 1
+#define MIB_FUNC_MIB_BUSY_FLAG                 HSL_RW
+
+#define MIB_AT_HALF_EN
+#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET        16
+#define MIB_FUNC_MIB_AT_HALF_EN_BLEN           1
+#define MIB_FUNC_MIB_AT_HALF_EN_FLAG           HSL_RW
+
+#define MIB_TIMER
+#define MIB_FUNC_MIB_TIMER_BOFFSET             0
+#define MIB_FUNC_MIB_TIMER_BLEN                16
+#define MIB_FUNC_MIB_TIMER_FLAG                HSL_RW
+
+
+
+
+    /* Service tag Register */
+#define SERVICE_TAG
+#define SERVICE_TAG_OFFSET           0x0048
+#define SERVICE_TAG_E_LENGTH         4
+#define SERVICE_TAG_E_OFFSET         0
+#define SERVICE_TAG_NR_E             1
+
+#define STAG_MODE
+#define SERVICE_TAG_STAG_MODE_BOFFSET    17
+#define SERVICE_TAG_STAG_MODE_BLEN       1
+#define SERVICE_TAG_STAG_MODE_FLAG       HSL_RW
+
+#define TAG_VALUE
+#define SERVICE_TAG_TAG_VALUE_BOFFSET    0
+#define SERVICE_TAG_TAG_VALUE_BLEN       16
+#define SERVICE_TAG_TAG_VALUE_FLAG       HSL_RW
+
+
+
+
+    /* Global MAC Address Register */
+#define GLOBAL_MAC_ADDR0
+#define GLOBAL_MAC_ADDR0_OFFSET    0x0060
+#define GLOBAL_MAC_ADDR0_E_LENGTH  4
+#define GLOBAL_MAC_ADDR0_E_OFFSET  0
+#define GLOBAL_MAC_ADDR0_NR_E      1
+
+#define GLB_BYTE4
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET         8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN            8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG            HSL_RW
+
+#define GLB_BYTE5
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET         0
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN            8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG            HSL_RW
+
+#define GLOBAL_MAC_ADDR1
+#define GLOBAL_MAC_ADDR1_ID        4
+#define GLOBAL_MAC_ADDR1_OFFSET    0x0064
+#define GLOBAL_MAC_ADDR1_E_LENGTH  4
+#define GLOBAL_MAC_ADDR1_E_OFFSET  0
+#define GLOBAL_MAC_ADDR1_NR_E      1
+
+#define GLB_BYTE0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET         24
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG            HSL_RW
+
+#define GLB_BYTE1
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET         16
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG            HSL_RW
+
+#define GLB_BYTE2
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET         8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG            HSL_RW
+
+#define GLB_BYTE3
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET         0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG            HSL_RW
+
+
+
+
+    /* Max Size Register */
+#define MAX_SIZE
+#define MAX_SIZE_OFFSET        0x0078
+#define MAX_SIZE_E_LENGTH      4
+#define MAX_SIZE_E_OFFSET      0
+#define MAX_SIZE_NR_E          1
+
+#define MAX_FRAME_SIZE
+#define MAX_SIZE_MAX_FRAME_SIZE_BOFFSET     0
+#define MAX_SIZE_MAX_FRAME_SIZE_BLEN        14
+#define MAX_SIZE_MAX_FRAME_SIZE_FLAG        HSL_RW
+
+
+
+
+    /* Flow Control Register */
+#define FLOW_CTL0                  "fctl"
+#define FLOW_CTL0_ID               6
+#define FLOW_CTL0_OFFSET           0x0034
+#define FLOW_CTL0_E_LENGTH         4
+#define FLOW_CTL0_E_OFFSET         0
+#define FLOW_CTL0_NR_E             1
+
+#define TEST_PAUSE                             "fctl_tps"
+#define FLOW_CTL0_TEST_PAUSE_BOFFSET           31
+#define FLOW_CTL0_TEST_PAUSE_BLEN              1
+#define FLOW_CTL0_TEST_PAUSE_FLAG              HSL_RW
+
+
+#define GOL_PAUSE_ON_THRES                     "fctl_gont"
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BOFFSET   16
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BLEN      8
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_FLAG      HSL_RW
+
+#define GOL_PAUSE_OFF_THRES                    "fctl_gofft"
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BOFFSET  0
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BLEN     8
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_FLAG     HSL_RW
+
+
+
+
+    /* Flow Control1 Register */
+#define FLOW_CTL1                  "fctl1"
+#define FLOW_CTL1_ID               6
+#define FLOW_CTL1_OFFSET           0x0038
+#define FLOW_CTL1_E_LENGTH         4
+#define FLOW_CTL1_E_OFFSET         0
+#define FLOW_CTL1_NR_E             1
+
+#define PORT_PAUSE_ON_THRES                    "fctl1_pont"
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BOFFSET  16
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BLEN     8
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_FLAG     HSL_RW
+
+#define PORT_PAUSE_OFF_THRES                   "fctl1_pofft"
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BOFFSET 0
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BLEN    8
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_FLAG    HSL_RW
+
+
+
+
+    /* Port Status Register */
+#define PORT_STATUS
+#define PORT_STATUS_OFFSET        0x007c
+#define PORT_STATUS_E_LENGTH      4
+#define PORT_STATUS_E_OFFSET      0x0004
+#define PORT_STATUS_NR_E          7
+
+#define FLOW_LINK_EN
+#define PORT_STATUS_FLOW_LINK_EN_BOFFSET        12
+#define PORT_STATUS_FLOW_LINK_EN_BLEN           1
+#define PORT_STATUS_FLOW_LINK_EN_FLAG           HSL_RW
+
+#define AUTO_RX_FLOW
+#define PORT_STATUS_AUTO_RX_FLOW_BOFFSET        11
+#define PORT_STATUS_AUTO_RX_FLOW_BLEN           1
+#define PORT_STATUS_AUTO_RX_FLOW_FLAG           HSL_RO
+
+#define AUTO_TX_FLOW
+#define PORT_STATUS_AUTO_TX_FLOW_BOFFSET        10
+#define PORT_STATUS_AUTO_TX_FLOW_BLEN           1
+#define PORT_STATUS_AUTO_TX_FLOW_FLAG           HSL_RO
+
+#define LINK_EN
+#define PORT_STATUS_LINK_EN_BOFFSET             9
+#define PORT_STATUS_LINK_EN_BLEN                1
+#define PORT_STATUS_LINK_EN_FLAG                HSL_RW
+
+#define LINK
+#define PORT_STATUS_LINK_BOFFSET                8
+#define PORT_STATUS_LINK_BLEN                   1
+#define PORT_STATUS_LINK_FLAG                   HSL_RO
+
+#define TX_HALF_FLOW_EN
+#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET     7
+#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN        1
+#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG        HSL_RW
+
+#define DUPLEX_MODE
+#define PORT_STATUS_DUPLEX_MODE_BOFFSET         6
+#define PORT_STATUS_DUPLEX_MODE_BLEN            1
+#define PORT_STATUS_DUPLEX_MODE_FLAG            HSL_RW
+
+#define RX_FLOW_EN
+#define PORT_STATUS_RX_FLOW_EN_BOFFSET          5
+#define PORT_STATUS_RX_FLOW_EN_BLEN             1
+#define PORT_STATUS_RX_FLOW_EN_FLAG             HSL_RW
+
+#define TX_FLOW_EN
+#define PORT_STATUS_TX_FLOW_EN_BOFFSET          4
+#define PORT_STATUS_TX_FLOW_EN_BLEN             1
+#define PORT_STATUS_TX_FLOW_EN_FLAG             HSL_RW
+
+#define RXMAC_EN
+#define PORT_STATUS_RXMAC_EN_BOFFSET            3
+#define PORT_STATUS_RXMAC_EN_BLEN               1
+#define PORT_STATUS_RXMAC_EN_FLAG               HSL_RW
+
+#define TXMAC_EN
+#define PORT_STATUS_TXMAC_EN_BOFFSET            2
+#define PORT_STATUS_TXMAC_EN_BLEN               1
+#define PORT_STATUS_TXMAC_EN_FLAG               HSL_RW
+
+#define SPEED_MODE
+#define PORT_STATUS_SPEED_MODE_BOFFSET          0
+#define PORT_STATUS_SPEED_MODE_BLEN             2
+#define PORT_STATUS_SPEED_MODE_FLAG             HSL_RW
+
+
+
+
+    /* Header Ctl Register */
+#define HEADER_CTL
+#define HEADER_CTL_OFFSET        0x0098
+#define HEADER_CTL_E_LENGTH      4
+#define HEADER_CTL_E_OFFSET      0x0004
+#define HEADER_CTL_NR_E          1
+
+#define TYPE_LEN
+#define HEADER_CTL_TYPE_LEN_BOFFSET          16
+#define HEADER_CTL_TYPE_LEN_BLEN             1
+#define HEADER_CTL_TYPE_LEN_FLAG             HSL_RW
+
+#define TYPE_VAL
+#define HEADER_CTL_TYPE_VAL_BOFFSET         0
+#define HEADER_CTL_TYPE_VAL_BLEN            16
+#define HEADER_CTL_TYPE_VAL_FLAG            HSL_RW
+
+
+
+
+    /* Port Header Ctl Register */
+#define PORT_HDR_CTL
+#define PORT_HDR_CTL_OFFSET        0x009c
+#define PORT_HDR_CTL_E_LENGTH      4
+#define PORT_HDR_CTL_E_OFFSET      0x0004
+#define PORT_HDR_CTL_NR_E          7
+
+#define IPG_DEC_EN
+#define PORT_HDR_CTL_IPG_DEC_EN_BOFFSET          5
+#define PORT_HDR_CTL_IPG_DEC_EN_BLEN             1
+#define PORT_HDR_CTL_IPG_DEC_EN_FLAG             HSL_RW
+
+#define LOOPBACK_EN
+#define PORT_HDR_CTL_LOOPBACK_EN_BOFFSET         4
+#define PORT_HDR_CTL_LOOPBACK_EN_BLEN            1
+#define PORT_HDR_CTL_LOOPBACK_EN_FLAG            HSL_RW
+
+#define RXHDR_MODE
+#define PORT_HDR_CTL_RXHDR_MODE_BOFFSET          2
+#define PORT_HDR_CTL_RXHDR_MODE_BLEN             2
+#define PORT_HDR_CTL_RXHDR_MODE_FLAG             HSL_RW
+
+#define TXHDR_MODE
+#define PORT_HDR_CTL_TXHDR_MODE_BOFFSET          0
+#define PORT_HDR_CTL_TXHDR_MODE_BLEN             2
+#define PORT_HDR_CTL_TXHDR_MODE_FLAG             HSL_RW
+
+
+
+
+    /* EEE control Register */
+#define EEE_CTL
+#define EEE_CTL_OFFSET    0x0100
+#define EEE_CTL_E_LENGTH  4
+#define EEE_CTL_E_OFFSET  0
+#define EEE_CTL_NR_E      1
+
+#define LPI_STATE_REMAP_EN_5
+#define EEE_CTL_LPI_STATE_REMAP_EN_5_BOFFSET                   13
+#define EEE_CTL_LPI_STATE_REMAP_EN_5_BLEN                      1
+#define EEE_CTL_LPI_STATE_REMAP_EN_5_FLAG                      HSL_RW
+
+#define LPI_EN_5
+#define EEE_CTL_LPI_EN_5_BOFFSET                               12
+#define EEE_CTL_LPI_EN_5_BLEN                                  1
+#define EEE_CTL_LPI_EN_5_FLAG                                  HSL_RW
+
+#define LPI_STATE_REMAP_EN_4
+#define EEE_CTL_LPI_STATE_REMAP_EN_4_BOFFSET                   11
+#define EEE_CTL_LPI_STATE_REMAP_EN_4_BLEN                      1
+#define EEE_CTL_LPI_STATE_REMAP_EN_4_FLAG                      HSL_RW
+
+#define LPI_EN_4
+#define EEE_CTL_LPI_EN_4_BOFFSET                               10
+#define EEE_CTL_LPI_EN_4_BLEN                                  1
+#define EEE_CTL_LPI_EN_4_FLAG                                  HSL_RW
+
+#define LPI_STATE_REMAP_EN_3
+#define EEE_CTL_LPI_STATE_REMAP_EN_3_BOFFSET                   9
+#define EEE_CTL_LPI_STATE_REMAP_EN_3_BLEN                      1
+#define EEE_CTL_LPI_STATE_REMAP_EN_3_FLAG                      HSL_RW
+
+#define LPI_EN_3
+#define EEE_CTL_LPI_EN_3_BOFFSET                               8
+#define EEE_CTL_LPI_EN_3_BLEN                                  1
+#define EEE_CTL_LPI_EN_3_FLAG                                  HSL_RW
+
+#define LPI_STATE_REMAP_EN_2
+#define EEE_CTL_LPI_STATE_REMAP_EN_2_BOFFSET                   7
+#define EEE_CTL_LPI_STATE_REMAP_EN_2_BLEN                      1
+#define EEE_CTL_LPI_STATE_REMAP_EN_2_FLAG                      HSL_RW
+
+#define LPI_EN_2
+#define EEE_CTL_LPI_EN_2_BOFFSET                               6
+#define EEE_CTL_LPI_EN_2_BLEN                                  1
+#define EEE_CTL_LPI_EN_2_FLAG                                  HSL_RW
+
+#define LPI_STATE_REMAP_EN_1
+#define EEE_CTL_LPI_STATE_REMAP_EN_1_BOFFSET                   5
+#define EEE_CTL_LPI_STATE_REMAP_EN_1_BLEN                      1
+#define EEE_CTL_LPI_STATE_REMAP_EN_1_FLAG                      HSL_RW
+
+#define LPI_EN_1
+#define EEE_CTL_LPI_EN_1_BOFFSET                               4
+#define EEE_CTL_LPI_EN_1_BLEN                                  1
+#define EEE_CTL_LPI_EN_1_FLAG                                  HSL_RW
+
+
+
+
+    /* Frame Ack Ctl0 Register */
+#define FRAME_ACK_CTL0
+#define FRAME_ACK_CTL0_OFFSET    0x0210
+#define FRAME_ACK_CTL0_E_LENGTH  4
+#define FRAME_ACK_CTL0_E_OFFSET  0
+#define FRAME_ACK_CTL0_NR_E      1
+
+#define ARP_REQ_EN
+#define FRAME_ACK_CTL0_ARP_REQ_EN_BOFFSET             6
+#define FRAME_ACK_CTL0_ARP_REQ_EN_BLEN                1
+#define FRAME_ACK_CTL0_ARP_REQ_EN_FLAG                HSL_RW
+
+#define ARP_REP_EN
+#define FRAME_ACK_CTL0_ARP_REP_EN_BOFFSET             5
+#define FRAME_ACK_CTL0_ARP_REP_EN_BLEN                1
+#define FRAME_ACK_CTL0_ARP_REP_EN_FLAG                HSL_RW
+
+#define DHCP_EN
+#define FRAME_ACK_CTL0_DHCP_EN_BOFFSET                4
+#define FRAME_ACK_CTL0_DHCP_EN_BLEN                   1
+#define FRAME_ACK_CTL0_DHCP_EN_FLAG                   HSL_RW
+
+#define EAPOL_EN
+#define FRAME_ACK_CTL0_EAPOL_EN_BOFFSET               3
+#define FRAME_ACK_CTL0_EAPOL_EN_BLEN                  1
+#define FRAME_ACK_CTL0_EAPOL_EN_FLAG                  HSL_RW
+
+#define LEAVE_EN
+#define FRAME_ACK_CTL0_LEAVE_EN_BOFFSET               2
+#define FRAME_ACK_CTL0_LEAVE_EN_BLEN                  1
+#define FRAME_ACK_CTL0_LEAVE_EN_FLAG                  HSL_RW
+
+#define JOIN_EN
+#define FRAME_ACK_CTL0_JOIN_EN_BOFFSET                1
+#define FRAME_ACK_CTL0_JOIN_EN_BLEN                   1
+#define FRAME_ACK_CTL0_JOIN_EN_FLAG                   HSL_RW
+
+#define IGMP_MLD_EN
+#define FRAME_ACK_CTL0_IGMP_MLD_EN_BOFFSET            0
+#define FRAME_ACK_CTL0_IGMP_MLD_EN_BLEN               1
+#define FRAME_ACK_CTL0_IGMP_MLD_EN_FLAG               HSL_RW
+
+
+
+
+    /* Frame Ack Ctl1 Register */
+#define FRAME_ACK_CTL1
+#define FRAME_ACK_CTL1_OFFSET    0x0214
+#define FRAME_ACK_CTL1_E_LENGTH  4
+#define FRAME_ACK_CTL1_E_OFFSET  0
+#define FRAME_ACK_CTL1_NR_E      1
+
+#define PPPOE_EN
+#define FRAME_ACK_CTL1_PPPOE_EN_BOFFSET               25
+#define FRAME_ACK_CTL1_PPPOE_EN_BLEN                  1
+#define FRAME_ACK_CTL1_PPPOE_EN_FLAG                  HSL_RW
+
+#define IGMP_V3_EN
+#define FRAME_ACK_CTL1_IGMP_V3_EN_BOFFSET             24
+#define FRAME_ACK_CTL1_IGMP_V3_EN_BLEN                1
+#define FRAME_ACK_CTL1_IGMP_V3_EN_FLAG                HSL_RW
+
+
+
+
+    /* Window Rule Ctl0 Register */
+#define WIN_RULE_CTL0
+#define WIN_RULE_CTL0_OFFSET               0x0218
+#define WIN_RULE_CTL0_E_LENGTH             4
+#define WIN_RULE_CTL0_E_OFFSET             0x4
+#define WIN_RULE_CTL0_NR_E                 7
+
+#define L4_LENGTH
+#define WIN_RULE_CTL0_L4_LENGTH_BOFFSET    24
+#define WIN_RULE_CTL0_L4_LENGTH_BLEN       4
+#define WIN_RULE_CTL0_L4_LENGTH_FLAG       HSL_RW
+
+#define L3_LENGTH
+#define WIN_RULE_CTL0_L3_LENGTH_BOFFSET    20
+#define WIN_RULE_CTL0_L3_LENGTH_BLEN       4
+#define WIN_RULE_CTL0_L3_LENGTH_FLAG       HSL_RW
+
+#define L2_LENGTH
+#define WIN_RULE_CTL0_L2_LENGTH_BOFFSET    16
+#define WIN_RULE_CTL0_L2_LENGTH_BLEN       4
+#define WIN_RULE_CTL0_L2_LENGTH_FLAG       HSL_RW
+
+#define L4_OFFSET
+#define WIN_RULE_CTL0_L4_OFFSET_BOFFSET    10
+#define WIN_RULE_CTL0_L4_OFFSET_BLEN       5
+#define WIN_RULE_CTL0_L4_OFFSET_FLAG       HSL_RW
+
+#define L3_OFFSET
+#define WIN_RULE_CTL0_L3_OFFSET_BOFFSET    5
+#define WIN_RULE_CTL0_L3_OFFSET_BLEN       5
+#define WIN_RULE_CTL0_L3_OFFSET_FLAG       HSL_RW
+
+#define L2_OFFSET
+#define WIN_RULE_CTL0_L2_OFFSET_BOFFSET    0
+#define WIN_RULE_CTL0_L2_OFFSET_BLEN       5
+#define WIN_RULE_CTL0_L2_OFFSET_FLAG       HSL_RW
+
+
+
+
+    /* Window Rule Ctl1 Register */
+#define WIN_RULE_CTL1
+#define WIN_RULE_CTL1_OFFSET               0x0234
+#define WIN_RULE_CTL1_E_LENGTH             4
+#define WIN_RULE_CTL1_E_OFFSET             0x4
+#define WIN_RULE_CTL1_NR_E                 7
+
+#define L3P_LENGTH
+#define WIN_RULE_CTL1_L3P_LENGTH_BOFFSET   20
+#define WIN_RULE_CTL1_L3P_LENGTH_BLEN      4
+#define WIN_RULE_CTL1_L3P_LENGTH_FLAG      HSL_RW
+
+#define L2S_LENGTH
+#define WIN_RULE_CTL1_L2S_LENGTH_BOFFSET   16
+#define WIN_RULE_CTL1_L2S_LENGTH_BLEN      4
+#define WIN_RULE_CTL1_L2S_LENGTH_FLAG      HSL_RW
+
+#define L3P_OFFSET
+#define WIN_RULE_CTL1_L3P_OFFSET_BOFFSET   5
+#define WIN_RULE_CTL1_L3P_OFFSET_BLEN      5
+#define WIN_RULE_CTL1_L3P_OFFSET_FLAG      HSL_RW
+
+#define L2S_OFFSET
+#define WIN_RULE_CTL1_L2S_OFFSET_BOFFSET   0
+#define WIN_RULE_CTL1_L2S_OFFSET_BLEN      5
+#define WIN_RULE_CTL1_L2S_OFFSET_FLAG      HSL_RW
+
+
+
+
+    /* Trunk Hash Mode Register */
+#define TRUNK_HASH_MODE
+#define TRUNK_HASH_MODE_OFFSET               0x0270
+#define TRUNK_HASH_MODE_E_LENGTH             4
+#define TRUNK_HASH_MODE_E_OFFSET             0x4
+#define TRUNK_HASH_MODE_NR_E                 1
+
+#define SIP_EN
+#define TRUNK_HASH_MODE_SIP_EN_BOFFSET       3
+#define TRUNK_HASH_MODE_SIP_EN_BLEN          1
+#define TRUNK_HASH_MODE_SIP_EN_FLAG          HSL_RW
+
+#define DIP_EN
+#define TRUNK_HASH_MODE_DIP_EN_BOFFSET       2
+#define TRUNK_HASH_MODE_DIP_EN_BLEN          1
+#define TRUNK_HASH_MODE_DIP_EN_FLAG          HSL_RW
+
+#define SA_EN
+#define TRUNK_HASH_MODE_SA_EN_BOFFSET        1
+#define TRUNK_HASH_MODE_SA_EN_BLEN           1
+#define TRUNK_HASH_MODE_SA_EN_FLAG           HSL_RW
+
+#define DA_EN
+#define TRUNK_HASH_MODE_DA_EN_BOFFSET        0
+#define TRUNK_HASH_MODE_DA_EN_BLEN           1
+#define TRUNK_HASH_MODE_DA_EN_FLAG           HSL_RW
+
+
+
+
+    /* Vlan Table Function0 Register */
+#define VLAN_TABLE_FUNC0
+#define VLAN_TABLE_FUNC0_OFFSET    0x0610
+#define VLAN_TABLE_FUNC0_E_LENGTH  4
+#define VLAN_TABLE_FUNC0_E_OFFSET  0
+#define VLAN_TABLE_FUNC0_NR_E      1
+
+#define VT_VALID
+#define VLAN_TABLE_FUNC0_VT_VALID_BOFFSET      20
+#define VLAN_TABLE_FUNC0_VT_VALID_BLEN         1
+#define VLAN_TABLE_FUNC0_VT_VALID_FLAG         HSL_RW
+
+#define IVL_EN
+#define VLAN_TABLE_FUNC0_IVL_EN_BOFFSET        19
+#define VLAN_TABLE_FUNC0_IVL_EN_BLEN           1
+#define VLAN_TABLE_FUNC0_IVL_EN_FLAG           HSL_RW
+
+#define LEARN_DIS
+#define VLAN_TABLE_FUNC0_LEARN_DIS_BOFFSET     18
+#define VLAN_TABLE_FUNC0_LEARN_DIS_BLEN        1
+#define VLAN_TABLE_FUNC0_LEARN_DIS_FLAG        HSL_RW
+
+#define VID_MEM
+#define VLAN_TABLE_FUNC0_VID_MEM_BOFFSET       4
+#define VLAN_TABLE_FUNC0_VID_MEM_BLEN          14
+#define VLAN_TABLE_FUNC0_VID_MEM_FLAG          HSL_RW
+
+#define VT_PRI_EN
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET     3
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN        1
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG        HSL_RW
+
+#define VT_PRI
+#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET        0
+#define VLAN_TABLE_FUNC0_VT_PRI_BLEN           3
+#define VLAN_TABLE_FUNC0_VT_PRI_FLAG           HSL_RW
+
+    /* Vlan Table Function1 Register */
+#define VLAN_TABLE_FUNC1
+#define VLAN_TABLE_FUNC1_OFFSET    0x0614
+#define VLAN_TABLE_FUNC1_E_LENGTH  4
+#define VLAN_TABLE_FUNC1_E_OFFSET  0
+#define VLAN_TABLE_FUNC1_NR_E      1
+
+#define VT_BUSY
+#define VLAN_TABLE_FUNC1_VT_BUSY_BOFFSET       31
+#define VLAN_TABLE_FUNC1_VT_BUSY_BLEN          1
+#define VLAN_TABLE_FUNC1_VT_BUSY_FLAG          HSL_RW
+
+#define VLAN_ID
+#define VLAN_TABLE_FUNC1_VLAN_ID_BOFFSET       16
+#define VLAN_TABLE_FUNC1_VLAN_ID_BLEN          12
+#define VLAN_TABLE_FUNC1_VLAN_ID_FLAG          HSL_RW
+
+#define VT_PORT_NUM
+#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BOFFSET   8
+#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BLEN      4
+#define VLAN_TABLE_FUNC1_VT_PORT_NUM_FLAG      HSL_RW
+
+#define VT_FULL_VIO
+#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BOFFSET   4
+#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BLEN      1
+#define VLAN_TABLE_FUNC1_VT_FULL_VIO_FLAG      HSL_RW
+
+#define VT_FUNC
+#define VLAN_TABLE_FUNC1_VT_FUNC_BOFFSET       0
+#define VLAN_TABLE_FUNC1_VT_FUNC_BLEN          3
+#define VLAN_TABLE_FUNC1_VT_FUNC_FLAG          HSL_RW
+
+
+
+
+    /* Address Table Function0 Register */
+#define ADDR_TABLE_FUNC0
+#define ADDR_TABLE_FUNC0_OFFSET    0x0600
+#define ADDR_TABLE_FUNC0_E_LENGTH  4
+#define ADDR_TABLE_FUNC0_E_OFFSET  0
+#define ADDR_TABLE_FUNC0_NR_E      1
+
+
+#define AT_ADDR_BYTE2
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BOFFSET 24
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE3
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BOFFSET 16
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE4
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE5
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 0
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG    HSL_RW
+
+    /* Address Table Function1 Register */
+#define ADDR_TABLE_FUNC1
+#define ADDR_TABLE_FUNC1_OFFSET    0x0604
+#define ADDR_TABLE_FUNC1_E_LENGTH  4
+#define ADDR_TABLE_FUNC1_E_OFFSET  0
+#define ADDR_TABLE_FUNC1_NR_E      1
+
+#define SA_DROP_EN
+#define ADDR_TABLE_FUNC1_SA_DROP_EN_BOFFSET    30
+#define ADDR_TABLE_FUNC1_SA_DROP_EN_BLEN       1
+#define ADDR_TABLE_FUNC1_SA_DROP_EN_FLAG       HSL_RW
+
+#define MIRROR_EN
+#define ADDR_TABLE_FUNC1_MIRROR_EN_BOFFSET     29
+#define ADDR_TABLE_FUNC1_MIRROR_EN_BLEN        1
+#define ADDR_TABLE_FUNC1_MIRROR_EN_FLAG        HSL_RW
+
+#define AT_PRI_EN
+#define ADDR_TABLE_FUNC1_AT_PRI_EN_BOFFSET     28
+#define ADDR_TABLE_FUNC1_AT_PRI_EN_BLEN        1
+#define ADDR_TABLE_FUNC1_AT_PRI_EN_FLAG        HSL_RW
+
+#define AT_SVL_EN
+#define ADDR_TABLE_FUNC1_AT_SVL_EN_BOFFSET     27
+#define ADDR_TABLE_FUNC1_AT_SVL_EN_BLEN        1
+#define ADDR_TABLE_FUNC1_AT_SVL_EN_FLAG        HSL_RW
+
+#define AT_PRI
+#define ADDR_TABLE_FUNC1_AT_PRI_BOFFSET        24
+#define ADDR_TABLE_FUNC1_AT_PRI_BLEN           3
+#define ADDR_TABLE_FUNC1_AT_PRI_FLAG           HSL_RW
+
+#define CROSS_PT
+#define ADDR_TABLE_FUNC1_CROSS_PT_BOFFSET      23
+#define ADDR_TABLE_FUNC1_CROSS_PT_BLEN         1
+#define ADDR_TABLE_FUNC1_CROSS_PT_FLAG         HSL_RW
+
+#define DES_PORT
+#define ADDR_TABLE_FUNC1_DES_PORT_BOFFSET      16
+#define ADDR_TABLE_FUNC1_DES_PORT_BLEN         7
+#define ADDR_TABLE_FUNC1_DES_PORT_FLAG         HSL_RW
+
+#define AT_ADDR_BYTE0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE1
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG    HSL_RW
+
+    /* Address Table Function2 Register */
+#define ADDR_TABLE_FUNC2
+#define ADDR_TABLE_FUNC2_OFFSET    0x0608
+#define ADDR_TABLE_FUNC2_E_LENGTH  4
+#define ADDR_TABLE_FUNC2_E_OFFSET  0
+#define ADDR_TABLE_FUNC2_NR_E      1
+
+#define WL_EN
+#define ADDR_TABLE_FUNC2_WL_EN_BOFFSET         20
+#define ADDR_TABLE_FUNC2_WL_EN_BLEN            1
+#define ADDR_TABLE_FUNC2_WL_EN_FLAG            HSL_RW
+
+#define AT_VID
+#define ADDR_TABLE_FUNC2_AT_VID_BOFFSET        8
+#define ADDR_TABLE_FUNC2_AT_VID_BLEN           12
+#define ADDR_TABLE_FUNC2_AT_VID_FLAG           HSL_RW
+
+#define SHORT_LOOP
+#define ADDR_TABLE_FUNC2_SHORT_LOOP_BOFFSET    7
+#define ADDR_TABLE_FUNC2_SHORT_LOOP_BLEN       1
+#define ADDR_TABLE_FUNC2_SHORT_LOOP_FLAG       HSL_RW
+
+#define COPY_TO_CPU
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET   6
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN      1
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG      HSL_RW
+
+#define REDRCT_TO_CPU
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 5
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN    1
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG    HSL_RW
+
+#define LEAKY_EN
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET      4
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN         1
+#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG         HSL_RW
+
+#define AT_STATUS
+#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET     0
+#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN        4
+#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG        HSL_RW
+
+    /* Address Table Function3 Register */
+#define ADDR_TABLE_FUNC3
+#define ADDR_TABLE_FUNC3_OFFSET    0x060c
+#define ADDR_TABLE_FUNC3_E_LENGTH  4
+#define ADDR_TABLE_FUNC3_E_OFFSET  0
+#define ADDR_TABLE_FUNC3_NR_E      1
+
+#define AT_BUSY
+#define ADDR_TABLE_FUNC3_AT_BUSY_BOFFSET       31
+#define ADDR_TABLE_FUNC3_AT_BUSY_BLEN          1
+#define ADDR_TABLE_FUNC3_AT_BUSY_FLAG          HSL_RW
+
+#define NEW_PORT_NUM
+#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BOFFSET  22
+#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BLEN     3
+#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_FLAG     HSL_RW
+
+#define AT_INDEX
+#define ADDR_TABLE_FUNC3_AT_INDEX_BOFFSET      16
+#define ADDR_TABLE_FUNC3_AT_INDEX_BLEN         5
+#define ADDR_TABLE_FUNC3_AT_INDEX_FLAG         HSL_RW
+
+#define AT_VID_EN
+#define ADDR_TABLE_FUNC3_AT_VID_EN_BOFFSET     15
+#define ADDR_TABLE_FUNC3_AT_VID_EN_BLEN        1
+#define ADDR_TABLE_FUNC3_AT_VID_EN_FLAG        HSL_RW
+
+#define AT_PORT_EN
+#define ADDR_TABLE_FUNC3_AT_PORT_EN_BOFFSET    14
+#define ADDR_TABLE_FUNC3_AT_PORT_EN_BLEN       1
+#define ADDR_TABLE_FUNC3_AT_PORT_EN_FLAG       HSL_RW
+
+#define AT_MULTI_EN
+#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BOFFSET   13
+#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BLEN      1
+#define ADDR_TABLE_FUNC3_AT_MULTI_EN_FLAG      HSL_RW
+
+#define AT_FULL_VIO
+#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BOFFSET   12
+#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BLEN      1
+#define ADDR_TABLE_FUNC3_AT_FULL_VIO_FLAG      HSL_RW
+
+#define AT_PORT_NUM
+#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BOFFSET   8
+#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BLEN      4
+#define ADDR_TABLE_FUNC3_AT_PORT_NUM_FLAG      HSL_RW
+
+#define FLUSH_ST_EN
+#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BOFFSET   4
+#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BLEN      1
+#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_FLAG      HSL_RW
+
+#define AT_FUNC
+#define ADDR_TABLE_FUNC3_AT_FUNC_BOFFSET       0
+#define ADDR_TABLE_FUNC3_AT_FUNC_BLEN          4
+#define ADDR_TABLE_FUNC3_AT_FUNC_FLAG          HSL_RW
+
+
+
+
+    /* Reserve Address Table0 Register */
+#define RESV_ADDR_TBL0
+#define RESV_ADDR_TBL0_OFFSET    0x3c000
+#define RESV_ADDR_TBL0_E_LENGTH  4
+#define RESV_ADDR_TBL0_E_OFFSET  0
+#define RESV_ADDR_TBL0_NR_E      1
+
+#define RESV_ADDR_BYTE2
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BOFFSET 24
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BLEN    8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_FLAG    HSL_RW
+
+#define RESV_ADDR_BYTE3
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BOFFSET 16
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BLEN    8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_FLAG    HSL_RW
+
+#define RESV_ADDR_BYTE4
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BOFFSET 8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BLEN    8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_FLAG    HSL_RW
+
+#define RESV_ADDR_BYTE5
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BOFFSET 0
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BLEN    8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_FLAG    HSL_RW
+
+    /* Reserve Address Table1 Register */
+#define RESV_ADDR_TBL1
+#define RESV_ADDR_TBL1_OFFSET    0x3c004
+#define RESV_ADDR_TBL1_E_LENGTH  4
+#define RESV_ADDR_TBL1_E_OFFSET  0
+#define RESV_ADDR_TBL1_NR_E      1
+
+#define RESV_COPY_TO_CPU
+#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BOFFSET   31
+#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BLEN      1
+#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_FLAG      HSL_RW
+
+#define RESV_REDRCT_TO_CPU
+#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BOFFSET 30
+#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BLEN    1
+#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_FLAG    HSL_RW
+
+#define RESV_LEAKY_EN
+#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BOFFSET      29
+#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BLEN         1
+#define RESV_ADDR_TBL1_RESV_LEAKY_EN_FLAG         HSL_RW
+
+#define RESV_MIRROR_EN
+#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BOFFSET     28
+#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BLEN        1
+#define RESV_ADDR_TBL1_RESV_MIRROR_EN_FLAG        HSL_RW
+
+#define RESV_PRI_EN
+#define RESV_ADDR_TBL1_RESV_PRI_EN_BOFFSET     27
+#define RESV_ADDR_TBL1_RESV_PRI_EN_BLEN        1
+#define RESV_ADDR_TBL1_RESV_PRI_EN_FLAG        HSL_RW
+
+#define RESV_PRI
+#define RESV_ADDR_TBL1_RESV_PRI_BOFFSET        24
+#define RESV_ADDR_TBL1_RESV_PRI_BLEN           3
+#define RESV_ADDR_TBL1_RESV_PRI_FLAG           HSL_RW
+
+#define RESV_CROSS_PT
+#define RESV_ADDR_TBL1_RESV_CROSS_PT_BOFFSET      23
+#define RESV_ADDR_TBL1_RESV_CROSS_PT_BLEN         1
+#define RESV_ADDR_TBL1_RESV_CROSS_PT_FLAG         HSL_RW
+
+#define RESV_DES_PORT
+#define RESV_ADDR_TBL1_RESV_DES_PORT_BOFFSET      16
+#define RESV_ADDR_TBL1_RESV_DES_PORT_BLEN         7
+#define RESV_ADDR_TBL1_RESV_DES_PORT_FLAG         HSL_RW
+
+#define RESV_ADDR_BYTE0
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BOFFSET 8
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BLEN    8
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_FLAG    HSL_RW
+
+#define RESV_ADDR_BYTE1
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BOFFSET 0
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BLEN    8
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_FLAG    HSL_RW
+
+    /* Reserve Address Table2 Register */
+#define RESV_ADDR_TBL2
+#define RESV_ADDR_TBL2_OFFSET    0x3c008
+#define RESV_ADDR_TBL2_E_LENGTH  4
+#define RESV_ADDR_TBL2_E_OFFSET  0
+#define RESV_ADDR_TBL2_NR_E      1
+
+#define RESV_STATUS
+#define RESV_ADDR_TBL2_RESV_STATUS_BOFFSET     0
+#define RESV_ADDR_TBL2_RESV_STATUS_BLEN        1
+#define RESV_ADDR_TBL2_RESV_STATUS_FLAG        HSL_RW
+
+
+
+
+    /* Address Table Control Register */
+#define ADDR_TABLE_CTL
+#define ADDR_TABLE_CTL_OFFSET     0x0618
+#define ADDR_TABLE_CTL_E_LENGTH   4
+#define ADDR_TABLE_CTL_E_OFFSET   0
+#define ADDR_TABLE_CTL_NR_E       1
+
+#define ARL_INI_EN
+#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET        31
+#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN           1
+#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG           HSL_RW
+
+#define LEARN_CHANGE_EN
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET   30
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN      1
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG      HSL_RW
+
+#define IGMP_JOIN_LEAKY
+#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BOFFSET   29
+#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BLEN      1
+#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_FLAG      HSL_RW
+
+#define IGMP_CREAT_EN
+#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BOFFSET     28
+#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BLEN        1
+#define ADDR_TABLE_CTL_IGMP_CREAT_EN_FLAG        HSL_RW
+
+#define IGMP_PRI_EN
+#define ADDR_TABLE_CTL_IGMP_PRI_EN_BOFFSET       27
+#define ADDR_TABLE_CTL_IGMP_PRI_EN_BLEN          1
+#define ADDR_TABLE_CTL_IGMP_PRI_EN_FLAG          HSL_RW
+
+#define IGMP_PRI
+#define ADDR_TABLE_CTL_IGMP_PRI_BOFFSET          24
+#define ADDR_TABLE_CTL_IGMP_PRI_BLEN             3
+#define ADDR_TABLE_CTL_IGMP_PRI_FLAG             HSL_RW
+
+#define IGMP_JOIN_STATIC
+#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BOFFSET  20
+#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BLEN     4
+#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_FLAG     HSL_RW
+
+#define AGE_EN
+#define ADDR_TABLE_CTL_AGE_EN_BOFFSET            19
+#define ADDR_TABLE_CTL_AGE_EN_BLEN               1
+#define ADDR_TABLE_CTL_AGE_EN_FLAG               HSL_RW
+
+#define LOOP_CHECK_TIMER
+#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BOFFSET  16
+#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BLEN     3
+#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_FLAG     HSL_RW
+
+#define AGE_TIME
+#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET          0
+#define ADDR_TABLE_CTL_AGE_TIME_BLEN             16
+#define ADDR_TABLE_CTL_AGE_TIME_FLAG             HSL_RW
+
+
+
+
+    /* Global Forward Control0 Register */
+#define FORWARD_CTL0
+#define FORWARD_CTL0_OFFSET             0x0620
+#define FORWARD_CTL0_E_LENGTH           4
+#define FORWARD_CTL0_E_OFFSET           0
+#define FORWARD_CTL0_NR_E               1
+
+#define ARP_CMD
+#define FORWARD_CTL0_ARP_CMD_BOFFSET                26
+#define FORWARD_CTL0_ARP_CMD_BLEN                   2
+#define FORWARD_CTL0_ARP_CMD_FLAG                   HSL_RW
+
+#define IP_NOT_FOUND
+#define FORWARD_CTL0_IP_NOT_FOUND_BOFFSET           24
+#define FORWARD_CTL0_IP_NOT_FOUND_BLEN              2
+#define FORWARD_CTL0_IP_NOT_FOUND_FLAG              HSL_RW
+
+#define ARP_NOT_FOUND
+#define FORWARD_CTL0_ARP_NOT_FOUND_BOFFSET          22
+#define FORWARD_CTL0_ARP_NOT_FOUND_BLEN             2
+#define FORWARD_CTL0_ARP_NOT_FOUND_FLAG             HSL_RW
+
+#define HASH_MODE
+#define FORWARD_CTL0_HASH_MODE_BOFFSET              20
+#define FORWARD_CTL0_HASH_MODE_BLEN                 2
+#define FORWARD_CTL0_HASH_MODE_FLAG                 HSL_RW
+
+#define NAT_NOT_FOUND_DROP
+#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BOFFSET     17
+#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BLEN        1
+#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_FLAG        HSL_RW
+
+#define SP_NOT_FOUND_DROP
+#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BOFFSET      16
+#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BLEN         1
+#define FORWARD_CTL0_SP_NOT_FOUND_DROP_FLAG         HSL_RW
+
+#define IGMP_LEAVE_DROP
+#define FORWARD_CTL0_IGMP_LEAVE_DROP_BOFFSET        14
+#define FORWARD_CTL0_IGMP_LEAVE_DROP_BLEN           1
+#define FORWARD_CTL0_IGMP_LEAVE_DROP_FLAG           HSL_RW
+
+#define ARL_UNI_LEAKY
+#define FORWARD_CTL0_ARL_UNI_LEAKY_BOFFSET          13
+#define FORWARD_CTL0_ARL_UNI_LEAKY_BLEN             1
+#define FORWARD_CTL0_ARL_UNI_LEAKY_FLAG             HSL_RW
+
+#define ARL_MUL_LEAKY
+#define FORWARD_CTL0_ARL_MUL_LEAKY_BOFFSET          12
+#define FORWARD_CTL0_ARL_MUL_LEAKY_BLEN             1
+#define FORWARD_CTL0_ARL_MUL_LEAKY_FLAG             HSL_RW
+
+#define MANAGE_VID_VIO_DROP_EN
+#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BOFFSET 11
+#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BLEN    1
+#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_FLAG    HSL_RW
+
+#define CPU_PORT_EN
+#define FORWARD_CTL0_CPU_PORT_EN_BOFFSET            10
+#define FORWARD_CTL0_CPU_PORT_EN_BLEN               1
+#define FORWARD_CTL0_CPU_PORT_EN_FLAG               HSL_RW
+
+#define PPPOE_RDT_EN
+#define FORWARD_CTL0_PPPOE_RDT_EN_BOFFSET           8
+#define FORWARD_CTL0_PPPOE_RDT_EN_BLEN              1
+#define FORWARD_CTL0_PPPOE_RDT_EN_FLAG              HSL_RW
+
+#define MIRROR_PORT_NUM
+#define FORWARD_CTL0_MIRROR_PORT_NUM_BOFFSET        4
+#define FORWARD_CTL0_MIRROR_PORT_NUM_BLEN           4
+#define FORWARD_CTL0_MIRROR_PORT_NUM_FLAG           HSL_RW
+
+#define IGMP_COPY_EN
+#define FORWARD_CTL0_IGMP_COPY_EN_BOFFSET           3
+#define FORWARD_CTL0_IGMP_COPY_EN_BLEN              1
+#define FORWARD_CTL0_IGMP_COPY_EN_FLAG              HSL_RW
+
+#define RIP_CPY_EN
+#define FORWARD_CTL0_RIP_CPY_EN_BOFFSET             2
+#define FORWARD_CTL0_RIP_CPY_EN_BLEN                1
+#define FORWARD_CTL0_RIP_CPY_EN_FLAG                HSL_RW
+
+#define EAPOL_CMD
+#define FORWARD_CTL0_EAPOL_CMD_BOFFSET              0
+#define FORWARD_CTL0_EAPOL_CMD_BLEN                 1
+#define FORWARD_CTL0_EAPOL_CMD_FLAG                 HSL_RW
+
+    /* Global Forward Control1 Register */
+#define FORWARD_CTL1
+#define FORWARD_CTL1_OFFSET             0x0624
+#define FORWARD_CTL1_E_LENGTH           4
+#define FORWARD_CTL1_E_OFFSET           0
+#define FORWARD_CTL1_NR_E               1
+
+#define IGMP_DP
+#define FORWARD_CTL1_IGMP_DP_BOFFSET          24
+#define FORWARD_CTL1_IGMP_DP_BLEN             7
+#define FORWARD_CTL1_IGMP_DP_FLAG             HSL_RW
+
+#define BC_FLOOD_DP
+#define FORWARD_CTL1_BC_FLOOD_DP_BOFFSET      16
+#define FORWARD_CTL1_BC_FLOOD_DP_BLEN         7
+#define FORWARD_CTL1_BC_FLOOD_DP_FLAG         HSL_RW
+
+#define MUL_FLOOD_DP
+#define FORWARD_CTL1_MUL_FLOOD_DP_BOFFSET     8
+#define FORWARD_CTL1_MUL_FLOOD_DP_BLEN        7
+#define FORWARD_CTL1_MUL_FLOOD_DP_FLAG        HSL_RW
+
+#define UNI_FLOOD_DP
+#define FORWARD_CTL1_UNI_FLOOD_DP_BOFFSET     0
+#define FORWARD_CTL1_UNI_FLOOD_DP_BLEN        7
+#define FORWARD_CTL1_UNI_FLOOD_DP_FLAG        HSL_RW
+
+
+
+
+    /* Global Learn Limit Ctl Register */
+#define GLOBAL_LEARN_LIMIT_CTL
+#define GLOBAL_LEARN_LIMIT_CTL_OFFSET            0x0628
+#define GLOBAL_LEARN_LIMIT_CTL_E_LENGTH          4
+#define GLOBAL_LEARN_LIMIT_CTL_E_OFFSET          0
+#define GLOBAL_LEARN_LIMIT_CTL_NR_E              1
+
+#define GOL_SA_LEARN_LIMIT_EN
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BOFFSET          12
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BLEN             1
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_FLAG             HSL_RW
+
+#define GOL_SA_LEARN_LIMIT_DROP_EN
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BOFFSET     11
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BLEN        1
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_FLAG        HSL_RW
+
+#define GOL_SA_LEARN_CNT
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BOFFSET               0
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BLEN                  11
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_FLAG                  HSL_RW
+
+
+
+
+    /* DSCP To Priority Register */
+#define DSCP_TO_PRI
+#define DSCP_TO_PRI_OFFSET     0x0630
+#define DSCP_TO_PRI_E_LENGTH   4
+#define DSCP_TO_PRI_E_OFFSET   0x0004
+#define DSCP_TO_PRI_NR_E       8
+
+
+
+
+    /* UP To Priority Register */
+#define UP_TO_PRI
+#define UP_TO_PRI_OFFSET     0x0650
+#define UP_TO_PRI_E_LENGTH   4
+#define UP_TO_PRI_E_OFFSET   0x0004
+#define UP_TO_PRI_NR_E       1
+
+
+
+
+    /* Port Lookup control Register */
+#define PORT_LOOKUP_CTL
+#define PORT_LOOKUP_CTL_OFFSET     0x0660
+#define PORT_LOOKUP_CTL_E_LENGTH   4
+#define PORT_LOOKUP_CTL_E_OFFSET   0x000c
+#define PORT_LOOKUP_CTL_NR_E       7
+
+#define MULTI_DROP_EN
+#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BOFFSET    31
+#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BLEN       1
+#define PORT_LOOKUP_CTL_MULTI_DROP_EN_FLAG       HSL_RW
+
+#define UNI_LEAKY_EN
+#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BOFFSET     28
+#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BLEN        1
+#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_FLAG        HSL_RW
+
+#define MUL_LEAKY_EN
+#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BOFFSET     27
+#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BLEN        1
+#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_FLAG        HSL_RW
+
+#define ARP_LEAKY_EN
+#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BOFFSET     26
+#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BLEN        1
+#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_FLAG        HSL_RW
+
+#define ING_MIRROR_EN
+#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BOFFSET    25
+#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BLEN       1
+#define PORT_LOOKUP_CTL_ING_MIRROR_EN_FLAG       HSL_RW
+
+#define PORT_LOOP_BACK
+#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BOFFSET   21
+#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BLEN      1
+#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_FLAG      HSL_RW
+
+#define LEARN_EN
+#define PORT_LOOKUP_CTL_LEARN_EN_BOFFSET         20
+#define PORT_LOOKUP_CTL_LEARN_EN_BLEN            1
+#define PORT_LOOKUP_CTL_LEARN_EN_FLAG            HSL_RW
+
+#define PORT_STATE
+#define PORT_LOOKUP_CTL_PORT_STATE_BOFFSET       16
+#define PORT_LOOKUP_CTL_PORT_STATE_BLEN          3
+#define PORT_LOOKUP_CTL_PORT_STATE_FLAG          HSL_RW
+
+#define FORCE_PVLAN
+#define PORT_LOOKUP_CTL_FORCE_PVLAN_BOFFSET      10
+#define PORT_LOOKUP_CTL_FORCE_PVLAN_BLEN         1
+#define PORT_LOOKUP_CTL_FORCE_PVLAN_FLAG         HSL_RW
+
+#define DOT1Q_MODE
+#define PORT_LOOKUP_CTL_DOT1Q_MODE_BOFFSET       8
+#define PORT_LOOKUP_CTL_DOT1Q_MODE_BLEN          2
+#define PORT_LOOKUP_CTL_DOT1Q_MODE_FLAG          HSL_RW
+
+#define PORT_VID_MEM
+#define PORT_LOOKUP_CTL_PORT_VID_MEM_BOFFSET     0
+#define PORT_LOOKUP_CTL_PORT_VID_MEM_BLEN        7
+#define PORT_LOOKUP_CTL_PORT_VID_MEM_FLAG        HSL_RW
+
+
+
+
+    /* Priority Control Register */
+#define PRI_CTL
+#define PRI_CTL_OFFSET            0x0664
+#define PRI_CTL_E_LENGTH          4
+#define PRI_CTL_E_OFFSET          0x000c
+#define PRI_CTL_NR_E              7
+
+#define EG_MAC_BASE_VLAN_EN
+#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BOFFSET     20
+#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BLEN        1
+#define PRI_CTL_EG_MAC_BASE_VLAN_EN_FLAG        HSL_RW
+
+#define DA_PRI_EN
+#define PRI_CTL_DA_PRI_EN_BOFFSET               18
+#define PRI_CTL_DA_PRI_EN_BLEN                  1
+#define PRI_CTL_DA_PRI_EN_FLAG                  HSL_RW
+
+#define VLAN_PRI_EN
+#define PRI_CTL_VLAN_PRI_EN_BOFFSET             17
+#define PRI_CTL_VLAN_PRI_EN_BLEN                1
+#define PRI_CTL_VLAN_PRI_EN_FLAG                HSL_RW
+
+#define IP_PRI_EN
+#define PRI_CTL_IP_PRI_EN_BOFFSET               16
+#define PRI_CTL_IP_PRI_EN_BLEN                  1
+#define PRI_CTL_IP_PRI_EN_FLAG                  HSL_RW
+
+#define DA_PRI_SEL
+#define PRI_CTL_DA_PRI_SEL_BOFFSET              6
+#define PRI_CTL_DA_PRI_SEL_BLEN                 2
+#define PRI_CTL_DA_PRI_SEL_FLAG                 HSL_RW
+
+#define VLAN_PRI_SEL
+#define PRI_CTL_VLAN_PRI_SEL_BOFFSET            4
+#define PRI_CTL_VLAN_PRI_SEL_BLEN               2
+#define PRI_CTL_VLAN_PRI_SEL_FLAG               HSL_RW
+
+#define IP_PRI_SEL
+#define PRI_CTL_IP_PRI_SEL_BOFFSET              2
+#define PRI_CTL_IP_PRI_SEL_BLEN                 2
+#define PRI_CTL_IP_PRI_SEL_FLAG                 HSL_RW
+
+
+
+    /* Port Learn Limit Ctl Register */
+#define PORT_LEARN_LIMIT_CTL
+#define PORT_LEARN_LIMIT_CTL_OFFSET            0x0668
+#define PORT_LEARN_LIMIT_CTL_E_LENGTH          4
+#define PORT_LEARN_LIMIT_CTL_E_OFFSET          0x000c
+#define PORT_LEARN_LIMIT_CTL_NR_E              7
+
+#define IGMP_JOIN_LIMIT_EN
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BOFFSET         27
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BLEN            1
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_FLAG            HSL_RW
+
+#define IGMP_JOIN_LIMIT_DROP_EN
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BOFFSET    26
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BLEN       1
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_FLAG       HSL_RW
+
+#define IGMP_JOIN_CNT
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BOFFSET              16
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BLEN                 10
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_FLAG                 HSL_RW
+
+#define SA_LEARN_STATUS
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BOFFSET            12
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BLEN               4
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_FLAG               HSL_RW
+
+#define SA_LEARN_LIMIT_EN
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BOFFSET          11
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BLEN             1
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_FLAG             HSL_RW
+
+#define SA_LEARN_LIMIT_DROP_EN
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BOFFSET     10
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BLEN        1
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_FLAG        HSL_RW
+
+#define SA_LEARN_CNT
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BOFFSET               0
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BLEN                  10
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_FLAG                  HSL_RW
+
+
+
+    /* Global Trunk Ctl0 Register */
+#define GOL_TRUNK_CTL0
+#define GOL_TRUNK_CTL0_OFFSET               0x0700
+#define GOL_TRUNK_CTL0_E_LENGTH             4
+#define GOL_TRUNK_CTL0_E_OFFSET             0x4
+#define GOL_TRUNK_CTL0_NR_E                 1
+
+
+    /* Global Trunk Ctl1 Register */
+#define GOL_TRUNK_CTL1
+#define GOL_TRUNK_CTL1_OFFSET               0x0704
+#define GOL_TRUNK_CTL1_E_LENGTH             4
+#define GOL_TRUNK_CTL1_E_OFFSET             0x4
+#define GOL_TRUNK_CTL1_NR_E                 2
+
+
+
+
+    /* Port vlan0 Register */
+#define PORT_VLAN0
+#define PORT_VLAN0_OFFSET     0x0420
+#define PORT_VLAN0_E_LENGTH   4
+#define PORT_VLAN0_E_OFFSET   0x0008
+#define PORT_VLAN0_NR_E       7
+
+#define ING_CPRI
+#define PORT_VLAN0_ING_CPRI_BOFFSET       29
+#define PORT_VLAN0_ING_CPRI_BLEN          3
+#define PORT_VLAN0_ING_CPRI_FLAG          HSL_RW
+
+#define DEF_CVID
+#define PORT_VLAN0_DEF_CVID_BOFFSET       16
+#define PORT_VLAN0_DEF_CVID_BLEN          12
+#define PORT_VLAN0_DEF_CVID_FLAG          HSL_RW
+
+#define ING_SPRI
+#define PORT_VLAN0_ING_SPRI_BOFFSET       13
+#define PORT_VLAN0_ING_SPRI_BLEN          3
+#define PORT_VLAN0_ING_SPRI_FLAG          HSL_RW
+
+#define DEF_SVID
+#define PORT_VLAN0_DEF_SVID_BOFFSET       0
+#define PORT_VLAN0_DEF_SVID_BLEN          12
+#define PORT_VLAN0_DEF_SVID_FLAG          HSL_RW
+
+    /* Port vlan1 Register */
+#define PORT_VLAN1
+#define PORT_VLAN1_OFFSET     0x0424
+#define PORT_VLAN1_E_LENGTH   4
+#define PORT_VLAN1_E_OFFSET   0x0008
+#define PORT_VLAN1_NR_E       7
+
+#define EG_VLAN_MODE
+#define PORT_VLAN1_EG_VLAN_MODE_BOFFSET   12
+#define PORT_VLAN1_EG_VLAN_MODE_BLEN      2
+#define PORT_VLAN1_EG_VLAN_MODE_FLAG      HSL_RW
+
+#define VLAN_DIS
+#define PORT_VLAN1_VLAN_DIS_BOFFSET       11
+#define PORT_VLAN1_VLAN_DIS_BLEN          1
+#define PORT_VLAN1_VLAN_DIS_FLAG          HSL_RW
+
+#define SP_CHECK_EN
+#define PORT_VLAN1_SP_CHECK_EN_BOFFSET    10
+#define PORT_VLAN1_SP_CHECK_EN_BLEN       1
+#define PORT_VLAN1_SP_CHECK_EN_FLAG       HSL_RW
+
+#define COREP_EN
+#define PORT_VLAN1_COREP_EN_BOFFSET       9
+#define PORT_VLAN1_COREP_EN_BLEN          1
+#define PORT_VLAN1_COREP_EN_FLAG          HSL_RW
+
+#define FORCE_DEF_VID
+#define PORT_VLAN1_FORCE_DEF_VID_BOFFSET  8
+#define PORT_VLAN1_FORCE_DEF_VID_BLEN     1
+#define PORT_VLAN1_FORCE_DEF_VID_FLAG     HSL_RW
+
+#define TLS_EN
+#define PORT_VLAN1_TLS_EN_BOFFSET         7
+#define PORT_VLAN1_TLS_EN_BLEN            1
+#define PORT_VLAN1_TLS_EN_FLAG            HSL_RW
+
+#define PROPAGATION_EN
+#define PORT_VLAN1_PROPAGATION_EN_BOFFSET 6
+#define PORT_VLAN1_PROPAGATION_EN_BLEN    1
+#define PORT_VLAN1_PROPAGATION_EN_FLAG    HSL_RW
+
+#define CLONE
+#define PORT_VLAN1_CLONE_BOFFSET          5
+#define PORT_VLAN1_CLONE_BLEN             1
+#define PORT_VLAN1_CLONE_FLAG             HSL_RW
+
+#define PRI_PROPAGATION
+#define PORT_VLAN1_PRI_PROPAGATION_BOFFSET   4
+#define PORT_VLAN1_PRI_PROPAGATION_BLEN      1
+#define PORT_VLAN1_VLAN_PRI_PROPAGATION_FLAG HSL_RW
+
+#define IN_VLAN_MODE
+#define PORT_VLAN1_IN_VLAN_MODE_BOFFSET      2
+#define PORT_VLAN1_IN_VLAN_MODE_BLEN         2
+#define PORT_VLAN1_IN_VLAN_MODE_FLAG         HSL_RW
+
+
+    /* Route Default VID Register */
+#define ROUTER_DEFV
+#define ROUTER_DEFV_OFFSET     0x0c70
+#define ROUTER_DEFV_E_LENGTH   4
+#define ROUTER_DEFV_E_OFFSET   0x0004
+#define ROUTER_DEFV_NR_E       4
+
+
+    /* Route Egress VLAN Mode Register */
+#define ROUTER_EG
+#define ROUTER_EG_OFFSET     0x0c80
+#define ROUTER_EG_E_LENGTH   4
+#define ROUTER_EG_E_OFFSET   0x0004
+#define ROUTER_EG_NR_E       1
+
+
+
+
+    /* Mdio control Register */
+#define MDIO_CTRL               "mctrl"
+#define MDIO_CTRL_ID            24
+#define MDIO_CTRL_OFFSET        0x0098
+#define MDIO_CTRL_E_LENGTH      4
+#define MDIO_CTRL_E_OFFSET      0
+#define MDIO_CTRL_NR_E          1
+
+#define MSTER_EN                        "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET      30
+#define MDIO_CTRL_MSTER_EN_BLEN         1
+#define MDIO_CTRL_MSTER_EN_FLAG         HSL_RW
+
+#define MSTER_EN                        "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET      30
+#define MDIO_CTRL_MSTER_EN_BLEN         1
+#define MDIO_CTRL_MSTER_EN_FLAG         HSL_RW
+
+#define CMD                             "mctrl_cmd"
+#define MDIO_CTRL_CMD_BOFFSET           27
+#define MDIO_CTRL_CMD_BLEN              1
+#define MDIO_CTRL_CMD_FLAG              HSL_RW
+
+#define SUP_PRE                         "mctrl_spre"
+#define MDIO_CTRL_SUP_PRE_BOFFSET       26
+#define MDIO_CTRL_SUP_PRE_BLEN          1
+#define MDIO_CTRL_SUP_PRE_FLAG          HSL_RW
+
+#define PHY_ADDR                        "mctrl_phyaddr"
+#define MDIO_CTRL_PHY_ADDR_BOFFSET      21
+#define MDIO_CTRL_PHY_ADDR_BLEN         5
+#define MDIO_CTRL_PHY_ADDR_FLAG         HSL_RW
+
+#define REG_ADDR                        "mctrl_regaddr"
+#define MDIO_CTRL_REG_ADDR_BOFFSET      16
+#define MDIO_CTRL_REG_ADDR_BLEN         5
+#define MDIO_CTRL_REG_ADDR_FLAG         HSL_RW
+
+#define DATA                            "mctrl_data"
+#define MDIO_CTRL_DATA_BOFFSET          0
+#define MDIO_CTRL_DATA_BLEN             16
+#define MDIO_CTRL_DATA_FLAG             HSL_RW
+
+
+
+
+    /* BIST control Register */
+#define BIST_CTRL               "bctrl"
+#define BIST_CTRL_ID            24
+#define BIST_CTRL_OFFSET        0x00a0
+#define BIST_CTRL_E_LENGTH      4
+#define BIST_CTRL_E_OFFSET      0
+#define BIST_CTRL_NR_E          1
+
+#define BIST_BUSY                        "bctrl_bb"
+#define BIST_CTRL_BIST_BUSY_BOFFSET      31
+#define BIST_CTRL_BIST_BUSY_BLEN         1
+#define BIST_CTRL_BIST_BUSY_FLAG         HSL_RW
+
+#define ONE_ERR                          "bctrl_oe"
+#define BIST_CTRL_ONE_ERR_BOFFSET        30
+#define BIST_CTRL_ONE_ERR_BLEN           1
+#define BIST_CTRL_ONE_ERR_FLAG           HSL_RO
+
+#define ERR_MEM                          "bctrl_em"
+#define BIST_CTRL_ERR_MEM_BOFFSET        24
+#define BIST_CTRL_ERR_MEM_BLEN           4
+#define BIST_CTRL_ERR_MEM_FLAG           HSL_RO
+
+#define PTN_EN2                          "bctrl_pe2"
+#define BIST_CTRL_PTN_EN2_BOFFSET        22
+#define BIST_CTRL_PTN_EN2_BLEN           1
+#define BIST_CTRL_PTN_EN2_FLAG           HSL_RW
+
+#define PTN_EN1                          "bctrl_pe1"
+#define BIST_CTRL_PTN_EN1_BOFFSET        21
+#define BIST_CTRL_PTN_EN1_BLEN           1
+#define BIST_CTRL_PTN_EN1_FLAG           HSL_RW
+
+#define PTN_EN0                          "bctrl_pe0"
+#define BIST_CTRL_PTN_EN0_BOFFSET        20
+#define BIST_CTRL_PTN_EN0_BLEN           1
+#define BIST_CTRL_PTN_EN0_FLAG           HSL_RW
+
+#define ERR_PTN                          "bctrl_ep"
+#define BIST_CTRL_ERR_PTN_BOFFSET        16
+#define BIST_CTRL_ERR_PTN_BLEN           2
+#define BIST_CTRL_ERR_PTN_FLAG           HSL_RO
+
+#define ERR_CNT                          "bctrl_ec"
+#define BIST_CTRL_ERR_CNT_BOFFSET        13
+#define BIST_CTRL_ERR_CNT_BLEN           2
+#define BIST_CTRL_ERR_CNT_FLAG           HSL_RO
+
+#define ERR_ADDR                         "bctrl_ea"
+#define BIST_CTRL_ERR_ADDR_BOFFSET       0
+#define BIST_CTRL_ERR_ADDR_BLEN          12
+#define BIST_CTRL_ERR_ADDR_FLAG          HSL_RO
+
+
+
+
+    /* BIST recover Register */
+#define BIST_RCV               "brcv"
+#define BIST_RCV_ID            24
+#define BIST_RCV_OFFSET        0x00a4
+#define BIST_RCV_E_LENGTH      4
+#define BIST_RCV_E_OFFSET      0
+#define BIST_RCV_NR_E          1
+
+#define RCV_EN                           "brcv_en"
+#define BIST_RCV_RCV_EN_BOFFSET          31
+#define BIST_RCV_RCV_EN_BLEN             1
+#define BIST_RCV_RCV_EN_FLAG             HSL_RW
+
+#define RCV_ADDR                         "brcv_addr"
+#define BIST_RCV_RCV_ADDR_BOFFSET        0
+#define BIST_RCV_RCV_ADDR_BLEN           12
+#define BIST_RCV_RCV_ADDR_FLAG           HSL_RW
+
+
+
+
+    /* LED control Register */
+#define LED_CTRL               "ledctrl"
+#define LED_CTRL_ID            25
+#define LED_CTRL_OFFSET        0x0050
+#define LED_CTRL_E_LENGTH      4
+#define LED_CTRL_E_OFFSET      0
+#define LED_CTRL_NR_E          3
+
+#define PATTERN_EN                           "lctrl_pen"
+#define LED_CTRL_PATTERN_EN_BOFFSET          14
+#define LED_CTRL_PATTERN_EN_BLEN             2
+#define LED_CTRL_PATTERN_EN_FLAG             HSL_RW
+
+#define FULL_LIGHT_EN                        "lctrl_fen"
+#define LED_CTRL_FULL_LIGHT_EN_BOFFSET       13
+#define LED_CTRL_FULL_LIGHT_EN_BLEN          1
+#define LED_CTRL_FULL_LIGHT_EN_FLAG          HSL_RW
+
+#define HALF_LIGHT_EN                        "lctrl_hen"
+#define LED_CTRL_HALF_LIGHT_EN_BOFFSET       12
+#define LED_CTRL_HALF_LIGHT_EN_BLEN          1
+#define LED_CTRL_HALF_LIGHT_EN_FLAG          HSL_RW
+
+#define POWERON_LIGHT_EN                     "lctrl_poen"
+#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET    11
+#define LED_CTRL_POWERON_LIGHT_EN_BLEN       1
+#define LED_CTRL_POWERON_LIGHT_EN_FLAG       HSL_RW
+
+#define GE_LIGHT_EN                          "lctrl_geen"
+#define LED_CTRL_GE_LIGHT_EN_BOFFSET         10
+#define LED_CTRL_GE_LIGHT_EN_BLEN            1
+#define LED_CTRL_GE_LIGHT_EN_FLAG            HSL_RW
+
+#define FE_LIGHT_EN                          "lctrl_feen"
+#define LED_CTRL_FE_LIGHT_EN_BOFFSET         9
+#define LED_CTRL_FE_LIGHT_EN_BLEN            1
+#define LED_CTRL_FE_LIGHT_EN_FLAG            HSL_RW
+
+#define ETH_LIGHT_EN                         "lctrl_ethen"
+#define LED_CTRL_ETH_LIGHT_EN_BOFFSET        8
+#define LED_CTRL_ETH_LIGHT_EN_BLEN           1
+#define LED_CTRL_ETH_LIGHT_EN_FLAG           HSL_RW
+
+#define COL_BLINK_EN                         "lctrl_cen"
+#define LED_CTRL_COL_BLINK_EN_BOFFSET        7
+#define LED_CTRL_COL_BLINK_EN_BLEN           1
+#define LED_CTRL_COL_BLINK_EN_FLAG           HSL_RW
+
+#define RX_BLINK_EN                          "lctrl_rxen"
+#define LED_CTRL_RX_BLINK_EN_BOFFSET         5
+#define LED_CTRL_RX_BLINK_EN_BLEN            1
+#define LED_CTRL_RX_BLINK_EN_FLAG            HSL_RW
+
+#define TX_BLINK_EN                          "lctrl_txen"
+#define LED_CTRL_TX_BLINK_EN_BOFFSET         4
+#define LED_CTRL_TX_BLINK_EN_BLEN            1
+#define LED_CTRL_TX_BLINK_EN_FLAG            HSL_RW
+
+#define LINKUP_OVER_EN                       "lctrl_loen"
+#define LED_CTRL_LINKUP_OVER_EN_BOFFSET      2
+#define LED_CTRL_LINKUP_OVER_EN_BLEN         1
+#define LED_CTRL_LINKUP_OVER_EN_FLAG         HSL_RW
+
+#define BLINK_FREQ                           "lctrl_bfreq"
+#define LED_CTRL_BLINK_FREQ_BOFFSET          0
+#define LED_CTRL_BLINK_FREQ_BLEN             2
+#define LED_CTRL_BLINK_FREQ_FLAG             HSL_RW
+
+    /* LED control Register */
+#define LED_PATTERN               "ledpatten"
+#define LED_PATTERN_ID            25
+#define LED_PATTERN_OFFSET        0x005c
+#define LED_PATTERN_E_LENGTH      4
+#define LED_PATTERN_E_OFFSET      0
+#define LED_PATTERN_NR_E          1
+
+
+#define P3L2_MODE
+#define LED_PATTERN_P3L2_MODE_BOFFSET       24
+#define LED_PATTERN_P3L2_MODE_BLEN          2
+#define LED_PATTERN_P3L2_MODE_FLAG          HSL_RW
+
+#define P3L1_MODE
+#define LED_PATTERN_P3L1_MODE_BOFFSET       22
+#define LED_PATTERN_P3L1_MODE_BLEN          2
+#define LED_PATTERN_P3L1_MODE_FLAG          HSL_RW
+
+#define P3L0_MODE
+#define LED_PATTERN_P3L0_MODE_BOFFSET       20
+#define LED_PATTERN_P3L0_MODE_BLEN          2
+#define LED_PATTERN_P3L0_MODE_FLAG          HSL_RW
+
+#define P2L2_MODE
+#define LED_PATTERN_P2L2_MODE_BOFFSET       18
+#define LED_PATTERN_P2L2_MODE_BLEN          2
+#define LED_PATTERN_P2L2_MODE_FLAG          HSL_RW
+
+#define P2L1_MODE
+#define LED_PATTERN_P2L1_MODE_BOFFSET       16
+#define LED_PATTERN_P2L1_MODE_BLEN          2
+#define LED_PATTERN_P2L1_MODE_FLAG          HSL_RW
+
+#define P2L0_MODE
+#define LED_PATTERN_P2L0_MODE_BOFFSET       14
+#define LED_PATTERN_P2L0_MODE_BLEN          2
+#define LED_PATTERN_P2L0_MODE_FLAG          HSL_RW
+
+#define P1L2_MODE
+#define LED_PATTERN_P1L2_MODE_BOFFSET       12
+#define LED_PATTERN_P1L2_MODE_BLEN          2
+#define LED_PATTERN_P1L2_MODE_FLAG          HSL_RW
+
+#define P1L1_MODE
+#define LED_PATTERN_P1L1_MODE_BOFFSET       10
+#define LED_PATTERN_P1L1_MODE_BLEN          2
+#define LED_PATTERN_P1L1_MODE_FLAG          HSL_RW
+
+#define P1L0_MODE
+#define LED_PATTERN_P1L0_MODE_BOFFSET       8
+#define LED_PATTERN_P1L0_MODE_BLEN          2
+#define LED_PATTERN_P1L0_MODE_FLAG          HSL_RW
+
+
+
+
+    /* Pri To Queue Register */
+#define PRI_TO_QUEUE
+#define PRI_TO_QUEUE_OFFSET         0x0814
+#define PRI_TO_QUEUE_E_LENGTH       4
+#define PRI_TO_QUEUE_E_OFFSET       0x0004
+#define PRI_TO_QUEUE_NR_E           1
+
+
+
+
+    /* Pri To EhQueue Register */
+#define PRI_TO_EHQUEUE
+#define PRI_TO_EHQUEUE_OFFSET         0x0810
+#define PRI_TO_EHQUEUE_E_LENGTH       4
+#define PRI_TO_EHQUEUE_E_OFFSET       0x0004
+#define PRI_TO_EHQUEUE_NR_E           1
+
+
+
+
+    /* Port HOL CTL0 Register */
+#define PORT_HOL_CTL0
+#define PORT_HOL_CTL0_OFFSET         0x0970
+#define PORT_HOL_CTL0_E_LENGTH       4
+#define PORT_HOL_CTL0_E_OFFSET       0x0008
+#define PORT_HOL_CTL0_NR_E           7
+
+#define PORT_DESC_NR
+#define PORT_HOL_CTL0_PORT_DESC_NR_BOFFSET           24
+#define PORT_HOL_CTL0_PORT_DESC_NR_BLEN              6
+#define PORT_HOL_CTL0_PORT_DESC_NR_FLAG              HSL_RW
+
+#define QUEUE5_DESC_NR
+#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BOFFSET         20
+#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE5_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE4_DESC_NR
+#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BOFFSET         16
+#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE4_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE3_DESC_NR
+#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BOFFSET         12
+#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE3_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE2_DESC_NR
+#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BOFFSET         8
+#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE2_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE1_DESC_NR
+#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BOFFSET         4
+#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE1_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE0_DESC_NR
+#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BOFFSET         0
+#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE0_DESC_NR_FLAG            HSL_RW
+
+    /* Port HOL CTL1 Register */
+#define PORT_HOL_CTL1
+#define PORT_HOL_CTL1_OFFSET         0x0974
+#define PORT_HOL_CTL1_E_LENGTH       4
+#define PORT_HOL_CTL1_E_OFFSET       0x0008
+#define PORT_HOL_CTL1_NR_E           7
+
+#define EG_MIRROR_EN
+#define PORT_HOL_CTL1_EG_MIRROR_EN_BOFFSET           16
+#define PORT_HOL_CTL1_EG_MIRROR_EN_BLEN              1
+#define PORT_HOL_CTL1_EG_MIRROR_EN_FLAG              HSL_RW
+
+#define PORT_DESC_EN
+#define PORT_HOL_CTL1_PORT_DESC_EN_BOFFSET           7
+#define PORT_HOL_CTL1_PORT_DESC_EN_BLEN              1
+#define PORT_HOL_CTL1_PORT_DESC_EN_FLAG              HSL_RW
+
+#define QUEUE_DESC_EN
+#define PORT_HOL_CTL1_QUEUE_DESC_EN_BOFFSET          6
+#define PORT_HOL_CTL1_QUEUE_DESC_EN_BLEN             1
+#define PORT_HOL_CTL1_QUEUE_DESC_EN_FLAG             HSL_RW
+
+#define PORT_IN_DESC_EN
+#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BOFFSET        0
+#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BLEN           4
+#define PORT_HOL_CTL1_PORT_IN_DESC_EN_FLAG           HSL_RW
+
+    /* PORT FLOW CTRL THRESHOLD REGISTER  */
+#define PORT_FLOW_CTRL_THRESHOLD
+#define PORT_FLOW_CTRL_THRESHOLD_OFFSET		0x09B0
+#define PORT_FLOW_CTRL_THRESHOLD_E_LENGTH	4
+#define PORT_FLOW_CTRL_THRESHOLD_E_OFFSET	0x0004
+#define PORT_FLOW_CTRL_THRESHOLD_NR_E		7
+
+#define XON_THRES
+#define PORT_FLOW_CTRL_THRESHOLD_XON_THRES_BOFFSET	16
+#define PORT_FLOW_CTRL_THRESHOLD_XON_THRES_BLEN		8
+#define PORT_FLOW_CTRL_THRESHOLD_XON_THRES_FLAG		HSL_RW
+
+#define XOFF_THRES
+#define PORT_FLOW_CTRL_THRESHOLD_XOFF_THRES_BOFFSET	0
+#define PORT_FLOW_CTRL_THRESHOLD_XOFF_THRES_BLEN	8
+#define PORT_FLOW_CTRL_THRESHOLD_XOFF_THRES_FLAG	HSL_RW
+
+    /* Port Rate Limit0 Register */
+#define RATE_LIMIT0                "rlmt0"
+#define RATE_LIMIT0_ID             32
+#define RATE_LIMIT0_OFFSET         0x0110
+#define RATE_LIMIT0_E_LENGTH       4
+#define RATE_LIMIT0_E_OFFSET       0x0100
+#define RATE_LIMIT0_NR_E           7
+
+
+#define EG_RATE_EN                             "rlmt_egen"
+#define RATE_LIMIT0_EG_RATE_EN_BOFFSET         23
+#define RATE_LIMIT0_EG_RATE_EN_BLEN            1
+#define RATE_LIMIT0_EG_RATE_EN_FLAG            HSL_RW
+
+#define EG_MNG_RATE_EN                         "rlmt_egmngen"
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET     22
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN        1
+#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG        HSL_RW
+
+#define IN_MNG_RATE_EN                         "rlmt_inmngen"
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET     21
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN        1
+#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG        HSL_RW
+
+#define IN_MUL_RATE_EN                         "rlmt_inmulen"
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET     20
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN        1
+#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG        HSL_RW
+
+#define ING_RATE                               "rlmt_ingrate"
+#define RATE_LIMIT0_ING_RATE_BOFFSET           0
+#define RATE_LIMIT0_ING_RATE_BLEN              15
+#define RATE_LIMIT0_ING_RATE_FLAG              HSL_RW
+
+
+
+
+
+
+
+
+
+
+    /* mib memory info */
+#define MIB_RXBROAD
+#define MIB_RXBROAD_OFFSET                0x01000
+#define MIB_RXBROAD_E_LENGTH              4
+#define MIB_RXBROAD_E_OFFSET              0x100
+#define MIB_RXBROAD_NR_E                  7
+
+#define MIB_RXPAUSE
+#define MIB_RXPAUSE_OFFSET                0x01004
+#define MIB_RXPAUSE_E_LENGTH              4
+#define MIB_RXPAUSE_E_OFFSET              0x100
+#define MIB_RXPAUSE_NR_E                  7
+
+#define MIB_RXMULTI
+#define MIB_RXMULTI_OFFSET                0x01008
+#define MIB_RXMULTI_E_LENGTH              4
+#define MIB_RXMULTI_E_OFFSET              0x100
+#define MIB_RXMULTI_NR_E                  7
+
+#define MIB_RXFCSERR
+#define MIB_RXFCSERR_OFFSET               0x0100c
+#define MIB_RXFCSERR_E_LENGTH             4
+#define MIB_RXFCSERR_E_OFFSET             0x100
+#define MIB_RXFCSERR_NR_E                 7
+
+#define MIB_RXALLIGNERR
+#define MIB_RXALLIGNERR_OFFSET            0x01010
+#define MIB_RXALLIGNERR_E_LENGTH          4
+#define MIB_RXALLIGNERR_E_OFFSET          0x100
+#define MIB_RXALLIGNERR_NR_E              7
+
+#define MIB_RXRUNT
+#define MIB_RXRUNT_OFFSET                 0x01014
+#define MIB_RXRUNT_E_LENGTH               4
+#define MIB_RXRUNT_E_OFFSET               0x100
+#define MIB_RXRUNT_NR_E                   7
+
+#define MIB_RXFRAGMENT
+#define MIB_RXFRAGMENT_OFFSET             0x01018
+#define MIB_RXFRAGMENT_E_LENGTH           4
+#define MIB_RXFRAGMENT_E_OFFSET           0x100
+#define MIB_RXFRAGMENT_NR_E               7
+
+#define MIB_RX64BYTE
+#define MIB_RX64BYTE_OFFSET               0x0101c
+#define MIB_RX64BYTE_E_LENGTH             4
+#define MIB_RX64BYTE_E_OFFSET             0x100
+#define MIB_RX64BYTE_NR_E                 7
+
+#define MIB_RX128BYTE
+#define MIB_RX128BYTE_OFFSET              0x01020
+#define MIB_RX128BYTE_E_LENGTH            4
+#define MIB_RX128BYTE_E_OFFSET            0x100
+#define MIB_RX128BYTE_NR_E                7
+
+#define MIB_RX256BYTE
+#define MIB_RX256BYTE_OFFSET              0x01024
+#define MIB_RX256BYTE_E_LENGTH            4
+#define MIB_RX256BYTE_E_OFFSET            0x100
+#define MIB_RX256BYTE_NR_E                7
+
+#define MIB_RX512BYTE
+#define MIB_RX512BYTE_OFFSET              0x01028
+#define MIB_RX512BYTE_E_LENGTH            4
+#define MIB_RX512BYTE_E_OFFSET            0x100
+#define MIB_RX512BYTE_NR_E                7
+
+#define MIB_RX1024BYTE
+#define MIB_RX1024BYTE_OFFSET             0x0102c
+#define MIB_RX1024BYTE_E_LENGTH           4
+#define MIB_RX1024BYTE_E_OFFSET           0x100
+#define MIB_RX1024BYTE_NR_E               7
+
+#define MIB_RX1518BYTE
+#define MIB_RX1518BYTE_OFFSET             0x01030
+#define MIB_RX1518BYTE_E_LENGTH           4
+#define MIB_RX1518BYTE_E_OFFSET           0x100
+#define MIB_RX1518BYTE_NR_E               7
+
+#define MIB_RXMAXBYTE
+#define MIB_RXMAXBYTE_OFFSET              0x01034
+#define MIB_RXMAXBYTE_E_LENGTH            4
+#define MIB_RXMAXBYTE_E_OFFSET            0x100
+#define MIB_RXMAXBYTE_NR_E                7
+
+#define MIB_RXTOOLONG
+#define MIB_RXTOOLONG_OFFSET              0x01038
+#define MIB_RXTOOLONG_E_LENGTH            4
+#define MIB_RXTOOLONG_E_OFFSET            0x100
+#define MIB_RXTOOLONG_NR_E                7
+
+#define MIB_RXGOODBYTE_LO
+#define MIB_RXGOODBYTE_LO_OFFSET          0x0103c
+#define MIB_RXGOODBYTE_LO_E_LENGTH        4
+#define MIB_RXGOODBYTE_LO_E_OFFSET        0x100
+#define MIB_RXGOODBYTE_LO_NR_E            7
+
+#define MIB_RXGOODBYTE_HI
+#define MIB_RXGOODBYTE_HI_OFFSET          0x01040
+#define MIB_RXGOODBYTE_HI_E_LENGTH        4
+#define MIB_RXGOODBYTE_HI_E_OFFSET        0x100
+#define MIB_RXGOODBYTE_HI_NR_E            7
+
+#define MIB_RXBADBYTE_LO
+#define MIB_RXBADBYTE_LO_OFFSET           0x01044
+#define MIB_RXBADBYTE_LO_E_LENGTH         4
+#define MIB_RXBADBYTE_LO_E_OFFSET         0x100
+#define MIB_RXBADBYTE_LO_NR_E             7
+
+#define MIB_RXBADBYTE_HI
+#define MIB_RXBADBYTE_HI_OFFSET           0x01048
+#define MIB_RXBADBYTE_HI_E_LENGTH         4
+#define MIB_RXBADBYTE_HI_E_OFFSET         0x100
+#define MIB_RXBADBYTE_HI_NR_E             7
+
+#define MIB_RXOVERFLOW
+#define MIB_RXOVERFLOW_OFFSET             0x0104c
+#define MIB_RXOVERFLOW_E_LENGTH           4
+#define MIB_RXOVERFLOW_E_OFFSET           0x100
+#define MIB_RXOVERFLOW_NR_E               7
+
+#define MIB_FILTERED
+#define MIB_FILTERED_OFFSET               0x01050
+#define MIB_FILTERED_E_LENGTH             4
+#define MIB_FILTERED_E_OFFSET             0x100
+#define MIB_FILTERED_NR_E                 7
+
+#define MIB_TXBROAD
+#define MIB_TXBROAD_OFFSET                0x01054
+#define MIB_TXBROAD_E_LENGTH              4
+#define MIB_TXBROAD_E_OFFSET              0x100
+#define MIB_TXBROAD_NR_E                  7
+
+#define MIB_TXPAUSE
+#define MIB_TXPAUSE_OFFSET                0x01058
+#define MIB_TXPAUSE_E_LENGTH              4
+#define MIB_TXPAUSE_E_OFFSET              0x100
+#define MIB_TXPAUSE_NR_E                  7
+
+#define MIB_TXMULTI
+#define MIB_TXMULTI_OFFSET                0x0105c
+#define MIB_TXMULTI_E_LENGTH              4
+#define MIB_TXMULTI_E_OFFSET              0x100
+#define MIB_TXMULTI_NR_E                  7
+
+#define MIB_TXUNDERRUN
+#define MIB_TXUNDERRUN_OFFSET             0x01060
+#define MIB_TXUNDERRUN_E_LENGTH           4
+#define MIB_TXUNDERRUN_E_OFFSET           0x100
+#define MIB_TXUNDERRUN_NR_E               7
+
+#define MIB_TX64BYTE
+#define MIB_TX64BYTE_OFFSET               0x01064
+#define MIB_TX64BYTE_E_LENGTH             4
+#define MIB_TX64BYTE_E_OFFSET             0x100
+#define MIB_TX64BYTE_NR_E                 7
+
+#define MIB_TX128BYTE
+#define MIB_TX128BYTE_OFFSET              0x01068
+#define MIB_TX128BYTE_E_LENGTH            4
+#define MIB_TX128BYTE_E_OFFSET            0x100
+#define MIB_TX128BYTE_NR_E                7
+
+#define MIB_TX256BYTE
+#define MIB_TX256BYTE_OFFSET              0x0106c
+#define MIB_TX256BYTE_E_LENGTH            4
+#define MIB_TX256BYTE_E_OFFSET            0x100
+#define MIB_TX256BYTE_NR_E                7
+
+#define MIB_TX512BYTE
+#define MIB_TX512BYTE_OFFSET              0x01070
+#define MIB_TX512BYTE_E_LENGTH            4
+#define MIB_TX512BYTE_E_OFFSET            0x100
+#define MIB_TX512BYTE_NR_E                7
+
+#define MIB_TX1024BYTE
+#define MIB_TX1024BYTE_OFFSET             0x01074
+#define MIB_TX1024BYTE_E_LENGTH           4
+#define MIB_TX1024BYTE_E_OFFSET           0x100
+#define MIB_TX1024BYTE_NR_E               7
+
+#define MIB_TX1518BYTE
+#define MIB_TX1518BYTE_OFFSET             0x01078
+#define MIB_TX1518BYTE_E_LENGTH           4
+#define MIB_TX1518BYTE_E_OFFSET           0x100
+#define MIB_TX1518BYTE_NR_E               7
+
+#define MIB_TXMAXBYTE
+#define MIB_TXMAXBYTE_OFFSET              0x0107c
+#define MIB_TXMAXBYTE_E_LENGTH            4
+#define MIB_TXMAXBYTE_E_OFFSET            0x100
+#define MIB_TXMAXBYTE_NR_E                7
+
+#define MIB_TXOVERSIZE
+#define MIB_TXOVERSIZE_OFFSET             0x01080
+#define MIB_TXOVERSIZE_E_LENGTH           4
+#define MIB_TXOVERSIZE_E_OFFSET           0x100
+#define MIB_TXOVERSIZE_NR_E               7
+
+#define MIB_TXBYTE_LO
+#define MIB_TXBYTE_LO_OFFSET              0x01084
+#define MIB_TXBYTE_LO_E_LENGTH            4
+#define MIB_TXBYTE_LO_E_OFFSET            0x100
+#define MIB_TXBYTE_LO_NR_E                7
+
+#define MIB_TXBYTE_HI
+#define MIB_TXBYTE_HI_OFFSET              0x01088
+#define MIB_TXBYTE_HI_E_LENGTH            4
+#define MIB_TXBYTE_HI_E_OFFSET            0x100
+#define MIB_TXBYTE_HI_NR_E                7
+
+#define MIB_TXCOLLISION
+#define MIB_TXCOLLISION_OFFSET            0x0108c
+#define MIB_TXCOLLISION_E_LENGTH          4
+#define MIB_TXCOLLISION_E_OFFSET          0x100
+#define MIB_TXCOLLISION_NR_E              7
+
+#define MIB_TXABORTCOL
+#define MIB_TXABORTCOL_OFFSET             0x01090
+#define MIB_TXABORTCOL_E_LENGTH           4
+#define MIB_TXABORTCOL_E_OFFSET           0x100
+#define MIB_TXABORTCOL_NR_E               7
+
+#define MIB_TXMULTICOL
+#define MIB_TXMULTICOL_OFFSET             0x01094
+#define MIB_TXMULTICOL_E_LENGTH           4
+#define MIB_TXMULTICOL_E_OFFSET           0x100
+#define MIB_TXMULTICOL_NR_E               7
+
+#define MIB_TXSINGALCOL
+#define MIB_TXSINGALCOL_OFFSET            0x01098
+#define MIB_TXSINGALCOL_E_LENGTH          4
+#define MIB_TXSINGALCOL_E_OFFSET          0x100
+#define MIB_TXSINGALCOL_NR_E              7
+
+#define MIB_TXEXCDEFER
+#define MIB_TXEXCDEFER_OFFSET             0x0109c
+#define MIB_TXEXCDEFER_E_LENGTH           4
+#define MIB_TXEXCDEFER_E_OFFSET           0x100
+#define MIB_TXEXCDEFER_NR_E               7
+
+#define MIB_TXDEFER
+#define MIB_TXDEFER_OFFSET                0x010a0
+#define MIB_TXDEFER_E_LENGTH              4
+#define MIB_TXDEFER_E_OFFSET              0x100
+#define MIB_TXDEFER_NR_E                  7
+
+#define MIB_TXLATECOL
+#define MIB_TXLATECOL_OFFSET              0x010a4
+#define MIB_TXLATECOL_E_LENGTH            4
+#define MIB_TXLATECOL_E_OFFSET            0x100
+#define MIB_TXLATECOL_NR_E                7
+
+
+
+    /* ACL Action Register */
+#define ACL_RSLT0                         10
+#define ACL_RSLT0_OFFSET                  0x5a000
+#define ACL_RSLT0_E_LENGTH                4
+#define ACL_RSLT0_E_OFFSET                0x10
+#define ACL_RSLT0_NR_E                    96
+
+#define CTAGPRI
+#define ACL_RSLT0_CTAGPRI_BOFFSET         29
+#define ACL_RSLT0_CTAGPRI_BLEN            3
+#define ACL_RSLT0_CTAGPRI_FLAG            HSL_RW
+
+#define CTAGCFI
+#define ACL_RSLT0_CTAGCFI_BOFFSET         28
+#define ACL_RSLT0_CTAGCFI_BLEN            1
+#define ACL_RSLT0_CTAGCFI_FLAG            HSL_RW
+
+#define CTAGVID
+#define ACL_RSLT0_CTAGVID_BOFFSET         16
+#define ACL_RSLT0_CTAGVID_BLEN            12
+#define ACL_RSLT0_CTAGVID_FLAG            HSL_RW
+
+#define STAGPRI
+#define ACL_RSLT0_STAGPRI_BOFFSET         13
+#define ACL_RSLT0_STAGPRI_BLEN            3
+#define ACL_RSLT0_STAGPRI_FLAG            HSL_RW
+
+#define STAGDEI
+#define ACL_RSLT0_STAGDEI_BOFFSET         12
+#define ACL_RSLT0_STAGDEI_BLEN            1
+#define ACL_RSLT0_STAGDEI_FLAG            HSL_RW
+
+#define STAGVID
+#define ACL_RSLT0_STAGVID_BOFFSET         0
+#define ACL_RSLT0_STAGVID_BLEN            12
+#define ACL_RSLT0_STAGVID_FLAG            HSL_RW
+
+
+#define ACL_RSLT1                         11
+#define ACL_RSLT1_OFFSET                  0x5a004
+#define ACL_RSLT1_E_LENGTH                4
+#define ACL_RSLT1_E_OFFSET                0x10
+#define ACL_RSLT1_NR_E                    96
+
+#define DES_PORT0
+#define ACL_RSLT1_DES_PORT0_BOFFSET       29
+#define ACL_RSLT1_DES_PORT0_BLEN          3
+#define ACL_RSLT1_DES_PORT0_FLAG          HSL_RW
+
+#define PRI_QU_EN
+#define ACL_RSLT1_PRI_QU_EN_BOFFSET       28
+#define ACL_RSLT1_PRI_QU_EN_BLEN          1
+#define ACL_RSLT1_PRI_QU_EN_FLAG          HSL_RW
+
+#define PRI_QU
+#define ACL_RSLT1_PRI_QU_BOFFSET          25
+#define ACL_RSLT1_PRI_QU_BLEN             3
+#define ACL_RSLT1_PRI_QU_FLAG             HSL_RW
+
+#define WCMP_EN
+#define ACL_RSLT1_WCMP_EN_BOFFSET         24
+#define ACL_RSLT1_WCMP_EN_BLEN            1
+#define ACL_RSLT1_WCMP_EN_FLAG            HSL_RW
+
+#define ARP_PTR
+#define ACL_RSLT1_ARP_PTR_BOFFSET         17
+#define ACL_RSLT1_ARP_PTR_BLEN            7
+#define ACL_RSLT1_ARP_PTR_FLAG            HSL_RW
+
+#define ARP_PTR_EN
+#define ACL_RSLT1_ARP_PTR_EN_BOFFSET      16
+#define ACL_RSLT1_ARP_PTR_EN_BLEN         1
+#define ACL_RSLT1_ARP_PTR_EN_FLAG         HSL_RW
+
+#define FORCE_L3_MODE
+#define ACL_RSLT1_FORCE_L3_MODE_BOFFSET   14
+#define ACL_RSLT1_FORCE_L3_MODE_BLEN      2
+#define ACL_RSLT1_FORCE_L3_MODE_FLAG      HSL_RW
+
+#define LOOK_VID_CHG
+#define ACL_RSLT1_LOOK_VID_CHG_BOFFSET    13
+#define ACL_RSLT1_LOOK_VID_CHG_BLEN       1
+#define ACL_RSLT1_LOOK_VID_CHG_FLAG       HSL_RW
+
+#define TRANS_CVID_CHG
+#define ACL_RSLT1_TRANS_CVID_CHG_BOFFSET  12
+#define ACL_RSLT1_TRANS_CVID_CHG_BLEN     1
+#define ACL_RSLT1_TRANS_CVID_CHG_FLAG     HSL_RW
+
+#define TRANS_SVID_CHG
+#define ACL_RSLT1_TRANS_SVID_CHG_BOFFSET  11
+#define ACL_RSLT1_TRANS_SVID_CHG_BLEN     1
+#define ACL_RSLT1_TRANS_SVID_CHG_FLAG     HSL_RW
+
+#define CTAG_CFI_CHG
+#define ACL_RSLT1_CTAG_CFI_CHG_BOFFSET    10
+#define ACL_RSLT1_CTAG_CFI_CHG_BLEN       1
+#define ACL_RSLT1_CTAG_CFI_CHG_FLAG       HSL_RW
+
+#define CTAG_PRI_REMAP
+#define ACL_RSLT1_CTAG_PRI_REMAP_BOFFSET  9
+#define ACL_RSLT1_CTAG_PRI_REMAP_BLEN     1
+#define ACL_RSLT1_CTAG_PRI_REMAP_FLAG     HSL_RW
+
+#define STAG_DEI_CHG
+#define ACL_RSLT1_STAG_DEI_CHG_BOFFSET    8
+#define ACL_RSLT1_STAG_DEI_CHG_BLEN       1
+#define ACL_RSLT1_STAG_DEI_CHG_FLAG       HSL_RW
+
+#define STAG_PRI_REMAP
+#define ACL_RSLT1_STAG_PRI_REMAP_BOFFSET  7
+#define ACL_RSLT1_STAG_PRI_REMAP_BLEN     1
+#define ACL_RSLT1_STAG_PRI_REMAP_FLAG     HSL_RW
+
+#define DSCP_REMAP
+#define ACL_RSLT1_DSCP_REMAP_BOFFSET      6
+#define ACL_RSLT1_DSCP_REMAP_BLEN         1
+#define ACL_RSLT1_DSCP_REMAP_FLAG         HSL_RW
+
+#define DSCPV
+#define ACL_RSLT1_DSCPV_BOFFSET           0
+#define ACL_RSLT1_DSCPV_BLEN              6
+#define ACL_RSLT1_DSCPV_FLAG              HSL_RW
+
+#define ACL_RSLT2                         12
+#define ACL_RSLT2_OFFSET                  0x5a008
+#define ACL_RSLT2_E_LENGTH                4
+#define ACL_RSLT2_E_OFFSET                0x10
+#define ACL_RSLT2_NR_E                    96
+
+#define TRIGGER_INTR
+#define ACL_RSLT2_TRIGGER_INTR_BOFFSET    16
+#define ACL_RSLT2_TRIGGER_INTR_BLEN       1
+#define ACL_RSLT2_TRIGGER_INTR_FLAG       HSL_RW
+
+#define EG_BYPASS
+#define ACL_RSLT2_EG_BYPASS_BOFFSET       15
+#define ACL_RSLT2_EG_BYPASS_BLEN          1
+#define ACL_RSLT2_EG_BYPASS_FLAG          HSL_RW
+
+#define POLICER_EN
+#define ACL_RSLT2_POLICER_EN_BOFFSET      14
+#define ACL_RSLT2_POLICER_EN_BLEN         1
+#define ACL_RSLT2_POLICER_EN_FLAG         HSL_RW
+
+#define POLICER_PTR
+#define ACL_RSLT2_POLICER_PTR_BOFFSET     9
+#define ACL_RSLT2_POLICER_PTR_BLEN        5
+#define ACL_RSLT2_POLICER_PTR_FLAG        HSL_RW
+
+#define FWD_CMD
+#define ACL_RSLT2_FWD_CMD_BOFFSET         6
+#define ACL_RSLT2_FWD_CMD_BLEN            3
+#define ACL_RSLT2_FWD_CMD_FLAG            HSL_RW
+
+#define MIRR_EN
+#define ACL_RSLT2_MIRR_EN_BOFFSET         5
+#define ACL_RSLT2_MIRR_EN_BLEN            1
+#define ACL_RSLT2_MIRR_EN_FLAG            HSL_RW
+
+#define DES_PORT_EN
+#define ACL_RSLT2_DES_PORT_EN_BOFFSET     4
+#define ACL_RSLT2_DES_PORT_EN_BLEN        1
+#define ACL_RSLT2_DES_PORT_EN_FLAG        HSL_RW
+
+#define DES_PORT1
+#define ACL_RSLT2_DES_PORT1_BOFFSET       0
+#define ACL_RSLT2_DES_PORT1_BLEN          4
+#define ACL_RSLT2_DES_PORT1_FLAG          HSL_RW
+
+
+
+
+    /* MAC Type Rule Field Define */
+#define MAC_RUL_V0                         0
+#define MAC_RUL_V0_OFFSET                  0x58000
+#define MAC_RUL_V0_E_LENGTH                4
+#define MAC_RUL_V0_E_OFFSET                0x20
+#define MAC_RUL_V0_NR_E                    96
+
+#define DAV_BYTE2
+#define MAC_RUL_V0_DAV_BYTE2_BOFFSET       24
+#define MAC_RUL_V0_DAV_BYTE2_BLEN          8
+#define MAC_RUL_V0_DAV_BYTE2_FLAG          HSL_RW
+
+#define DAV_BYTE3
+#define MAC_RUL_V0_DAV_BYTE3_BOFFSET       16
+#define MAC_RUL_V0_DAV_BYTE3_BLEN          8
+#define MAC_RUL_V0_DAV_BYTE3_FLAG          HSL_RW
+
+#define DAV_BYTE4
+#define MAC_RUL_V0_DAV_BYTE4_BOFFSET       8
+#define MAC_RUL_V0_DAV_BYTE4_BLEN          8
+#define MAC_RUL_V0_DAV_BYTE4_FLAG          HSL_RW
+
+#define DAV_BYTE5
+#define MAC_RUL_V0_DAV_BYTE5_BOFFSET       0
+#define MAC_RUL_V0_DAV_BYTE5_BLEN          8
+#define MAC_RUL_V0_DAV_BYTE5_FLAG          HSL_RW
+
+
+#define MAC_RUL_V1                         1
+#define MAC_RUL_V1_OFFSET                  0x58004
+#define MAC_RUL_V1_E_LENGTH                4
+#define MAC_RUL_V1_E_OFFSET                0x20
+#define MAC_RUL_V1_NR_E                    96
+
+#define SAV_BYTE4
+#define MAC_RUL_V1_SAV_BYTE4_BOFFSET       24
+#define MAC_RUL_V1_SAV_BYTE4_BLEN          8
+#define MAC_RUL_V1_SAV_BYTE4_FLAG          HSL_RW
+
+#define SAV_BYTE5
+#define MAC_RUL_V1_SAV_BYTE5_BOFFSET       16
+#define MAC_RUL_V1_SAV_BYTE5_BLEN          8
+#define MAC_RUL_V1_SAV_BYTE5_FLAG          HSL_RW
+
+#define DAV_BYTE0
+#define MAC_RUL_V1_DAV_BYTE0_BOFFSET       8
+#define MAC_RUL_V1_DAV_BYTE0_BLEN          8
+#define MAC_RUL_V1_DAV_BYTE0_FLAG          HSL_RW
+
+#define DAV_BYTE1
+#define MAC_RUL_V1_DAV_BYTE1_BOFFSET       0
+#define MAC_RUL_V1_DAV_BYTE1_BLEN          8
+#define MAC_RUL_V1_DAV_BYTE1_FLAG          HSL_RW
+
+
+#define MAC_RUL_V2                         2
+#define MAC_RUL_V2_OFFSET                  0x58008
+#define MAC_RUL_V2_E_LENGTH                4
+#define MAC_RUL_V2_E_OFFSET                0x20
+#define MAC_RUL_V2_NR_E                    96
+
+#define SAV_BYTE0
+#define MAC_RUL_V2_SAV_BYTE0_BOFFSET       24
+#define MAC_RUL_V2_SAV_BYTE0_BLEN          8
+#define MAC_RUL_V2_SAV_BYTE0_FLAG          HSL_RW
+
+#define SAV_BYTE1
+#define MAC_RUL_V2_SAV_BYTE1_BOFFSET       16
+#define MAC_RUL_V2_SAV_BYTE1_BLEN          8
+#define MAC_RUL_V2_SAV_BYTE1_FLAG          HSL_RW
+
+#define SAV_BYTE2
+#define MAC_RUL_V2_SAV_BYTE2_BOFFSET       8
+#define MAC_RUL_V2_SAV_BYTE2_BLEN          8
+#define MAC_RUL_V2_SAV_BYTE2_FLAG          HSL_RW
+
+#define SAV_BYTE3
+#define MAC_RUL_V2_SAV_BYTE3_BOFFSET       0
+#define MAC_RUL_V2_SAV_BYTE3_BLEN          8
+#define MAC_RUL_V2_SAV_BYTE3_FLAG          HSL_RW
+
+
+#define MAC_RUL_V3                         3
+#define MAC_RUL_V3_ID                      13
+#define MAC_RUL_V3_OFFSET                  0x5800c
+#define MAC_RUL_V3_E_LENGTH                4
+#define MAC_RUL_V3_E_OFFSET                0x20
+#define MAC_RUL_V3_NR_E                    96
+
+#define ETHTYPV
+#define MAC_RUL_V3_ETHTYPV_BOFFSET         16
+#define MAC_RUL_V3_ETHTYPV_BLEN            16
+#define MAC_RUL_V3_ETHTYPV_FLAG            HSL_RW
+
+#define VLANPRIV
+#define MAC_RUL_V3_VLANPRIV_BOFFSET        13
+#define MAC_RUL_V3_VLANPRIV_BLEN           3
+#define MAC_RUL_V3_VLANPRIV_FLAG           HSL_RW
+
+#define VLANCFIV
+#define MAC_RUL_V3_VLANCFIV_BOFFSET        12
+#define MAC_RUL_V3_VLANCFIV_BLEN           1
+#define MAC_RUL_V3_VLANCFIV_FLAG           HSL_RW
+
+#define VLANIDV
+#define MAC_RUL_V3_VLANIDV_BOFFSET         0
+#define MAC_RUL_V3_VLANIDV_BLEN            12
+#define MAC_RUL_V3_VLANIDV_FLAG            HSL_RW
+
+
+#define MAC_RUL_V4                         4
+#define MAC_RUL_V4_OFFSET                  0x58010
+#define MAC_RUL_V4_E_LENGTH                4
+#define MAC_RUL_V4_E_OFFSET                0x20
+#define MAC_RUL_V4_NR_E                    96
+
+#define RULE_INV
+#define MAC_RUL_V4_RULE_INV_BOFFSET        7
+#define MAC_RUL_V4_RULE_INV_BLEN           1
+#define MAC_RUL_V4_RULE_INV_FLAG           HSL_RW
+
+#define SRC_PT
+#define MAC_RUL_V4_SRC_PT_BOFFSET          0
+#define MAC_RUL_V4_SRC_PT_BLEN             7
+#define MAC_RUL_V4_SRC_PT_FLAG             HSL_RW
+
+
+#define MAC_RUL_M0                         5
+#define MAC_RUL_M0_OFFSET                  0x59000
+#define MAC_RUL_M0_E_LENGTH                4
+#define MAC_RUL_M0_E_OFFSET                0x20
+#define MAC_RUL_M0_NR_E                    96
+
+#define DAM_BYTE2
+#define MAC_RUL_M0_DAM_BYTE2_BOFFSET       24
+#define MAC_RUL_M0_DAM_BYTE2_BLEN          8
+#define MAC_RUL_M0_DAM_BYTE2_FLAG          HSL_RW
+
+#define DAM_BYTE3
+#define MAC_RUL_M0_DAM_BYTE3_BOFFSET       16
+#define MAC_RUL_M0_DAM_BYTE3_BLEN          8
+#define MAC_RUL_M0_DAM_BYTE3_FLAG          HSL_RW
+
+#define DAM_BYTE4
+#define MAC_RUL_M0_DAM_BYTE4_BOFFSET       8
+#define MAC_RUL_M0_DAM_BYTE4_BLEN          8
+#define MAC_RUL_M0_DAM_BYTE4_FLAG          HSL_RW
+
+#define DAM_BYTE5
+#define MAC_RUL_M0_DAM_BYTE5_BOFFSET       0
+#define MAC_RUL_M0_DAM_BYTE5_BLEN          8
+#define MAC_RUL_M0_DAM_BYTE5_FLAG          HSL_RW
+
+
+#define MAC_RUL_M1                         6
+#define MAC_RUL_M1_OFFSET                  0x59004
+#define MAC_RUL_M1_E_LENGTH                4
+#define MAC_RUL_M1_E_OFFSET                0x20
+#define MAC_RUL_M1_NR_E                    96
+
+#define SAM_BYTE4
+#define MAC_RUL_M1_SAM_BYTE4_BOFFSET       24
+#define MAC_RUL_M1_SAM_BYTE4_BLEN          8
+#define MAC_RUL_M1_SAM_BYTE4_FLAG          HSL_RW
+
+#define SAM_BYTE5
+#define MAC_RUL_M1_SAM_BYTE5_BOFFSET       16
+#define MAC_RUL_M1_SAM_BYTE5_BLEN          8
+#define MAC_RUL_M1_SAM_BYTE5_FLAG          HSL_RW
+
+#define DAM_BYTE0
+#define MAC_RUL_M1_DAM_BYTE0_BOFFSET       8
+#define MAC_RUL_M1_DAM_BYTE0_BLEN          8
+#define MAC_RUL_M1_DAM_BYTE0_FLAG          HSL_RW
+
+#define DAM_BYTE1
+#define MAC_RUL_M1_DAM_BYTE1_BOFFSET       0
+#define MAC_RUL_M1_DAM_BYTE1_BLEN          8
+#define MAC_RUL_M1_DAM_BYTE1_FLAG          HSL_RW
+
+
+#define MAC_RUL_M2                         7
+#define MAC_RUL_M2_OFFSET                  0x59008
+#define MAC_RUL_M2_E_LENGTH                4
+#define MAC_RUL_M2_E_OFFSET                0x20
+#define MAC_RUL_M2_NR_E                    96
+
+#define SAM_BYTE0
+#define MAC_RUL_M2_SAM_BYTE0_BOFFSET       24
+#define MAC_RUL_M2_SAM_BYTE0_BLEN          8
+#define MAC_RUL_M2_SAM_BYTE0_FLAG          HSL_RW
+
+#define SAM_BYTE1
+#define MAC_RUL_M2_SAM_BYTE1_BOFFSET       16
+#define MAC_RUL_M2_SAM_BYTE1_BLEN          8
+#define MAC_RUL_M2_SAM_BYTE1_FLAG          HSL_RW
+
+#define SAM_BYTE2
+#define MAC_RUL_M2_SAM_BYTE2_BOFFSET       8
+#define MAC_RUL_M2_SAM_BYTE2_BLEN          8
+#define MAC_RUL_M2_SAM_BYTE2_FLAG          HSL_RW
+
+#define SAM_BYTE3
+#define MAC_RUL_M2_SAM_BYTE3_BOFFSET       0
+#define MAC_RUL_M2_SAM_BYTE3_BLEN          8
+#define MAC_RUL_M2_SAM_BYTE3_FLAG          HSL_RW
+
+
+#define MAC_RUL_M3                         8
+#define MAC_RUL_M3_OFFSET                  0x5900c
+#define MAC_RUL_M3_E_LENGTH                4
+#define MAC_RUL_M3_E_OFFSET                0x20
+#define MAC_RUL_M3_NR_E                    96
+
+#define ETHTYPM
+#define MAC_RUL_M3_ETHTYPM_BOFFSET         16
+#define MAC_RUL_M3_ETHTYPM_BLEN            16
+#define MAC_RUL_M3_ETHTYPM_FLAG            HSL_RW
+
+#define VLANPRIM
+#define MAC_RUL_M3_VLANPRIM_BOFFSET        13
+#define MAC_RUL_M3_VLANPRIM_BLEN           3
+#define MAC_RUL_M3_VLANPRIM_FLAG           HSL_RW
+
+#define VLANCFIM
+#define MAC_RUL_M3_VLANCFIM_BOFFSET        12
+#define MAC_RUL_M3_VLANCFIM_BLEN           1
+#define MAC_RUL_M3_VLANCFIM_FLAG           HSL_RW
+
+#define VLANIDM
+#define MAC_RUL_M3_VLANIDM_BOFFSET         0
+#define MAC_RUL_M3_VLANIDM_BLEN            12
+#define MAC_RUL_M3_VLANIDM_FLAG            HSL_RW
+
+
+#define MAC_RUL_M4                         9
+#define MAC_RUL_M4_OFFSET                  0x59010
+#define MAC_RUL_M4_E_LENGTH                4
+#define MAC_RUL_M4_E_OFFSET                0x20
+#define MAC_RUL_M4_NR_E                    96
+
+#define RULE_VALID
+#define MAC_RUL_M4_RULE_VALID_BOFFSET      6
+#define MAC_RUL_M4_RULE_VALID_BLEN         2
+#define MAC_RUL_M4_RULE_VALID_FLAG         HSL_RW
+
+#define TAGGEDM
+#define MAC_RUL_M4_TAGGEDM_BOFFSET         5
+#define MAC_RUL_M4_TAGGEDM_BLEN            1
+#define MAC_RUL_M4_TAGGEDM_FLAG            HSL_RW
+
+#define TAGGEDV
+#define MAC_RUL_M4_TAGGEDV_BOFFSET         4
+#define MAC_RUL_M4_TAGGEDV_BLEN            1
+#define MAC_RUL_M4_TAGGEDV_FLAG            HSL_RW
+
+#define VIDMSK
+#define MAC_RUL_M4_VIDMSK_BOFFSET          3
+#define MAC_RUL_M4_VIDMSK_BLEN             1
+#define MAC_RUL_M4_VIDMSK_FLAG             HSL_RW
+
+#define RULE_TYP
+#define MAC_RUL_M4_RULE_TYP_BOFFSET        0
+#define MAC_RUL_M4_RULE_TYP_BLEN           3
+#define MAC_RUL_M4_RULE_TYP_FLAG           HSL_RW
+
+
+
+
+    /* IP4 Type Rule Field Define */
+#define IP4_RUL_V0                         0
+#define IP4_RUL_V0_OFFSET                  0x58000
+#define IP4_RUL_V0_E_LENGTH                4
+#define IP4_RUL_V0_E_OFFSET                0x20
+#define IP4_RUL_V0_NR_E                    96
+
+#define DIPV
+#define IP4_RUL_V0_DIPV_BOFFSET            0
+#define IP4_RUL_V0_DIPV_BLEN               32
+#define IP4_RUL_V0_DIPV_FLAG               HSL_RW
+
+
+#define IP4_RUL_V1                         1
+#define IP4_RUL_V1_OFFSET                  0x58004
+#define IP4_RUL_V1_E_LENGTH                4
+#define IP4_RUL_V1_E_OFFSET                0x20
+#define IP4_RUL_V1_NR_E                    96
+
+#define SIPV
+#define IP4_RUL_V1_SIPV_BOFFSET            0
+#define IP4_RUL_V1_SIPV_BLEN               32
+#define IP4_RUL_V1_SIPV_FLAG               HSL_RW
+
+
+#define IP4_RUL_V2                         2
+#define IP4_RUL_V2_OFFSET                  0x58008
+#define IP4_RUL_V2_E_LENGTH                4
+#define IP4_RUL_V2_E_OFFSET                0x20
+#define IP4_RUL_V2_NR_E                    96
+
+#define IP4PROTV
+#define IP4_RUL_V2_IP4PROTV_BOFFSET        0
+#define IP4_RUL_V2_IP4PROTV_BLEN           8
+#define IP4_RUL_V2_IP4PROTV_FLAG           HSL_RW
+
+#define IP4DSCPV
+#define IP4_RUL_V2_IP4DSCPV_BOFFSET        8
+#define IP4_RUL_V2_IP4DSCPV_BLEN           8
+#define IP4_RUL_V2_IP4DSCPV_FLAG           HSL_RW
+
+#define IP4DPORTV
+#define IP4_RUL_V2_IP4DPORTV_BOFFSET       16
+#define IP4_RUL_V2_IP4DPORTV_BLEN          16
+#define IP4_RUL_V2_IP4DPORTV_FLAG          HSL_RW
+
+
+#define IP4_RUL_V3                         3
+#define IP4_RUL_V3_OFFSET                  0x5800c
+#define IP4_RUL_V3_E_LENGTH                4
+#define IP4_RUL_V3_E_OFFSET                0x20
+#define IP4_RUL_V3_NR_E                    96
+
+#define IP4TCPFLAGV
+#define IP4_RUL_V3_IP4TCPFLAGV_BOFFSET     24
+#define IP4_RUL_V3_IP4TCPFLAGV_BLEN        6
+#define IP4_RUL_V3_IP4TCPFLAGV_FLAG        HSL_RW
+
+#define IP4DHCPV
+#define IP4_RUL_V3_IP4DHCPV_BOFFSET        22
+#define IP4_RUL_V3_IP4DHCPV_BLEN           1
+#define IP4_RUL_V3_IP4DHCPV_FLAG           HSL_RW
+
+#define IP4RIPV
+#define IP4_RUL_V3_IP4RIPV_BOFFSET         21
+#define IP4_RUL_V3_IP4RIPV_BLEN            1
+#define IP4_RUL_V3_IP4RIPV_FLAG            HSL_RW
+
+#define ICMP_EN
+#define IP4_RUL_V3_ICMP_EN_BOFFSET         20
+#define IP4_RUL_V3_ICMP_EN_BLEN            1
+#define IP4_RUL_V3_ICMP_EN_FLAG            HSL_RW
+
+#define IP4SPORTV
+#define IP4_RUL_V3_IP4SPORTV_BOFFSET       0
+#define IP4_RUL_V3_IP4SPORTV_BLEN          16
+#define IP4_RUL_V3_IP4SPORTV_FLAG          HSL_RW
+
+#define IP4ICMPTYPV
+#define IP4_RUL_V3_IP4ICMPTYPV_BOFFSET     8
+#define IP4_RUL_V3_IP4ICMPTYPV_BLEN        8
+#define IP4_RUL_V3_IP4ICMPTYPV_FLAG        HSL_RW
+
+#define IP4ICMPCODEV
+#define IP4_RUL_V3_IP4ICMPCODEV_BOFFSET    0
+#define IP4_RUL_V3_IP4ICMPCODEV_BLEN       8
+#define IP4_RUL_V3_IP4ICMPCODEV_FLAG       HSL_RW
+
+
+#define IP4_RUL_V4                         4
+#define IP4_RUL_V4_OFFSET                  0x58010
+#define IP4_RUL_V4_E_LENGTH                4
+#define IP4_RUL_V4_E_OFFSET                0x20
+#define IP4_RUL_V4_NR_E                    96
+
+
+#define IP4_RUL_M0                         5
+#define IP4_RUL_M0_OFFSET                  0x59000
+#define IP4_RUL_M0_E_LENGTH                4
+#define IP4_RUL_M0_E_OFFSET                0x20
+#define IP4_RUL_M0_NR_E                    96
+
+#define DIPM
+#define IP4_RUL_M0_DIPM_BOFFSET            0
+#define IP4_RUL_M0_DIPM_BLEN               32
+#define IP4_RUL_M0_DIPM_FLAG               HSL_RW
+
+
+#define IP4_RUL_M1                         6
+#define IP4_RUL_M1_OFFSET                  0x59004
+#define IP4_RUL_M1_E_LENGTH                4
+#define IP4_RUL_M1_E_OFFSET                0x20
+#define IP4_RUL_M1_NR_E                    96
+
+#define SIPM
+#define IP4_RUL_M1_SIPM_BOFFSET            0
+#define IP4_RUL_M1_SIPM_BLEN               32
+#define IP4_RUL_M1_SIPM_FLAG               HSL_RW
+
+
+#define IP4_RUL_M2                         7
+#define IP4_RUL_M2_OFFSET                  0x59008
+#define IP4_RUL_M2_E_LENGTH                4
+#define IP4_RUL_M2_E_OFFSET                0x20
+#define IP4_RUL_M2_NR_E                    96
+
+#define IP4PROTM
+#define IP4_RUL_M2_IP4PROTM_BOFFSET        0
+#define IP4_RUL_M2_IP4PROTM_BLEN           8
+#define IP4_RUL_M2_IP4PROTM_FLAG           HSL_RW
+
+#define IP4DSCPM
+#define IP4_RUL_M2_IP4DSCPM_BOFFSET        8
+#define IP4_RUL_M2_IP4DSCPM_BLEN           8
+#define IP4_RUL_M2_IP4DSCPM_FLAG           HSL_RW
+
+#define IP4DPORTM
+#define IP4_RUL_M2_IP4DPORTM_BOFFSET       16
+#define IP4_RUL_M2_IP4DPORTM_BLEN          16
+#define IP4_RUL_M2_IP4DPORTM_FLAG          HSL_RW
+
+
+#define IP4_RUL_M3                         8
+#define IP4_RUL_M3_OFFSET                  0x5900c
+#define IP4_RUL_M3_E_LENGTH                4
+#define IP4_RUL_M3_E_OFFSET                0x20
+#define IP4_RUL_M3_NR_E                    96
+
+#define IP4TCPFLAGM
+#define IP4_RUL_M3_IP4TCPFLAGM_BOFFSET     24
+#define IP4_RUL_M3_IP4TCPFLAGM_BLEN        6
+#define IP4_RUL_M3_IP4TCPFLAGM_FLAG        HSL_RW
+
+#define IP4DHCPM
+#define IP4_RUL_M3_IP4DHCPM_BOFFSET        22
+#define IP4_RUL_M3_IP4DHCPM_BLEN           1
+#define IP4_RUL_M3_IP4DHCPM_FLAG           HSL_RW
+
+#define IP4RIPM
+#define IP4_RUL_M3_IP4RIPM_BOFFSET         21
+#define IP4_RUL_M3_IP4RIPM_BLEN            1
+#define IP4_RUL_M3_IP4RIPM_FLAG            HSL_RW
+
+#define IP4DPORTM_EN
+#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET    17
+#define IP4_RUL_M3_IP4DPORTM_EN_BLEN       1
+#define IP4_RUL_M3_IP4DPORTM_EN_FLAG       HSL_RW
+
+#define IP4SPORTM_EN
+#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET    16
+#define IP4_RUL_M3_IP4SPORTM_EN_BLEN       1
+#define IP4_RUL_M3_IP4SPORTM_EN_FLAG       HSL_RW
+
+#define IP4SPORTM
+#define IP4_RUL_M3_IP4SPORTM_BOFFSET       0
+#define IP4_RUL_M3_IP4SPORTM_BLEN          16
+#define IP4_RUL_M3_IP4SPORTM_FLAG          HSL_RW
+
+#define IP4ICMPTYPM
+#define IP4_RUL_M3_IP4ICMPTYPM_BOFFSET     8
+#define IP4_RUL_M3_IP4ICMPTYPM_BLEN        8
+#define IP4_RUL_M3_IP4ICMPTYPM_FLAG        HSL_RW
+
+#define IP4ICMPCODEM
+#define IP4_RUL_M3_IP4ICMPCODEM_BOFFSET    0
+#define IP4_RUL_M3_IP4ICMPCODEM_BLEN       8
+#define IP4_RUL_M3_IP4ICMPCODEM_FLAG       HSL_RW
+
+
+#define IP4_RUL_M4                         9
+#define IP4_RUL_M4_OFFSET                  0x59010
+#define IP4_RUL_M4_E_LENGTH                4
+#define IP4_RUL_M4_E_OFFSET                0x20
+#define IP4_RUL_M4_NR_E                    32
+
+
+
+
+    /* IP6 Type1 Rule Field Define */
+#define IP6_RUL1_V0                        0
+#define IP6_RUL1_V0_OFFSET                 0x58000
+#define IP6_RUL1_V0_E_LENGTH               4
+#define IP6_RUL1_V0_E_OFFSET               0x20
+#define IP6_RUL1_V0_NR_E                   96
+
+#define IP6_DIPV0
+#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET      0
+#define IP6_RUL1_V0_IP6_DIPV0_BLEN         32
+#define IP6_RUL1_V0_IP6_DIPV0_FLAG         HSL_RW
+
+
+#define IP6_RUL1_V1                        1
+#define IP6_RUL1_V1_OFFSET                 0x58004
+#define IP6_RUL1_V1_E_LENGTH               4
+#define IP6_RUL1_V1_E_OFFSET               0x20
+#define IP6_RUL1_V1_NR_E                   96
+
+#define IP6_DIPV1
+#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET      0
+#define IP6_RUL1_V1_IP6_DIPv1_BLEN         32
+#define IP6_RUL1_V1_IP6_DIPV1_FLAG         HSL_RW
+
+
+#define IP6_RUL1_V2                        2
+#define IP6_RUL1_V2_OFFSET                 0x58008
+#define IP6_RUL1_V2_E_LENGTH               4
+#define IP6_RUL1_V2_E_OFFSET               0x20
+#define IP6_RUL1_V2_NR_E                   96
+
+#define IP6_DIPV2
+#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET      0
+#define IP6_RUL1_V2_IP6_DIPv2_BLEN         32
+#define IP6_RUL1_V2_IP6_DIPV2_FLAG         HSL_RW
+
+
+#define IP6_RUL1_V3                        3
+#define IP6_RUL1_V3_OFFSET                 0x5800c
+#define IP6_RUL1_V3_E_LENGTH               4
+#define IP6_RUL1_V3_E_OFFSET               0x20
+#define IP6_RUL1_V3_NR_E                   96
+
+#define IP6_DIPV3
+#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET      0
+#define IP6_RUL1_V3_IP6_DIPv3_BLEN         32
+#define IP6_RUL1_V3_IP6_DIPV3_FLAG         HSL_RW
+
+
+#define IP6_RUL1_V4                        4
+#define IP6_RUL1_V4_OFFSET                 0x58010
+#define IP6_RUL1_V4_E_LENGTH               4
+#define IP6_RUL1_V4_E_OFFSET               0x20
+#define IP6_RUL1_V4_NR_E                   96
+
+
+#define IP6_RUL1_M0                        5
+#define IP6_RUL1_M0_OFFSET                 0x59000
+#define IP6_RUL1_M0_E_LENGTH               4
+#define IP6_RUL1_M0_E_OFFSET               0x20
+#define IP6_RUL1_M0_NR_E                   96
+
+#define IP6_DIPM0
+#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET      0
+#define IP6_RUL1_M0_IP6_DIPM0_BLEN         32
+#define IP6_RUL1_M0_IP6_DIPM0_FLAG         HSL_RW
+
+
+#define IP6_RUL1_M1                        6
+#define IP6_RUL1_M1_OFFSET                 0x59004
+#define IP6_RUL1_M1_E_LENGTH               4
+#define IP6_RUL1_M1_E_OFFSET               0x20
+#define IP6_RUL1_M1_NR_E                   96
+
+#define IP6_DIPM1
+#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET      0
+#define IP6_RUL1_M1_IP6_DIPM1_BLEN         32
+#define IP6_RUL1_M1_IP6_DIPM1_FLAG         HSL_RW
+
+
+#define IP6_RUL1_M2                        7
+#define IP6_RUL1_M2_OFFSET                 0x59008
+#define IP6_RUL1_M2_E_LENGTH               4
+#define IP6_RUL1_M2_E_OFFSET               0x20
+#define IP6_RUL1_M2_NR_E                   96
+
+#define IP6_DIPM2
+#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET      0
+#define IP6_RUL1_M2_IP6_DIPM2_BLEN         32
+#define IP6_RUL1_M2_IP6_DIPM2_FLAG         HSL_RW
+
+
+#define IP6_RUL1_M3                        8
+#define IP6_RUL1_M3_OFFSET                 0x5900c
+#define IP6_RUL1_M3_E_LENGTH               4
+#define IP6_RUL1_M3_E_OFFSET               0x20
+#define IP6_RUL1_M3_NR_E                   96
+
+#define IP6_DIPM3
+#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET      0
+#define IP6_RUL1_M3_IP6_DIPM3_BLEN         32
+#define IP6_RUL1_M3_IP6_DIPM3_FLAG         HSL_RW
+
+
+#define IP6_RUL1_M4                        9
+#define IP6_RUL1_M4_OFFSET                 0x59010
+#define IP6_RUL1_M4_E_LENGTH               4
+#define IP6_RUL1_M4_E_OFFSET               0x20
+#define IP6_RUL1_M4_NR_E                   96
+
+
+
+
+    /* IP6 Type2 Rule Field Define */
+#define IP6_RUL2_V0                        0
+#define IP6_RUL2_V0_OFFSET                 0x58000
+#define IP6_RUL2_V0_E_LENGTH               4
+#define IP6_RUL2_V0_E_OFFSET               0x20
+#define IP6_RUL2_V0_NR_E                   96
+
+#define IP6_SIPV0
+#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET      0
+#define IP6_RUL2_V0_IP6_SIPv0_BLEN         32
+#define IP6_RUL2_V0_IP6_SIPV0_FLAG         HSL_RW
+
+
+#define IP6_RUL2_V1                        1
+#define IP6_RUL2_V1_OFFSET                 0x58004
+#define IP6_RUL2_V1_E_LENGTH               4
+#define IP6_RUL2_V1_E_OFFSET               0x20
+#define IP6_RUL2_V1_NR_E                   96
+
+#define IP6_SIPV1
+#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET      0
+#define IP6_RUL2_V1_IP6_SIPv1_BLEN         32
+#define IP6_RUL2_V1_IP6_SIPV1_FLAG         HSL_RW
+
+
+#define IP6_RUL2_V2                        2
+#define IP6_RUL2_V2_OFFSET                 0x58008
+#define IP6_RUL2_V2_E_LENGTH               4
+#define IP6_RUL2_V2_E_OFFSET               0x20
+#define IP6_RUL2_V2_NR_E                   96
+
+#define IP6_SIPV2
+#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET      0
+#define IP6_RUL2_V2_IP6_SIPv2_BLEN         32
+#define IP6_RUL2_V2_IP6_SIPV2_FLAG         HSL_RW
+
+
+#define IP6_RUL2_V3                        3
+#define IP6_RUL2_V3_OFFSET                 0x5800c
+#define IP6_RUL2_V3_E_LENGTH               4
+#define IP6_RUL2_V3_E_OFFSET               0x20
+#define IP6_RUL2_V3_NR_E                   96
+
+#define IP6_SIPV3
+#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET      0
+#define IP6_RUL2_V3_IP6_SIPv3_BLEN         32
+#define IP6_RUL2_V3_IP6_SIPV3_FLAG         HSL_RW
+
+
+#define IP6_RUL2_V4                        4
+#define IP6_RUL2_V4_OFFSET                 0x58010
+#define IP6_RUL2_V4_E_LENGTH               4
+#define IP6_RUL2_V4_E_OFFSET               0x20
+#define IP6_RUL2_V4_NR_E                   96
+
+
+#define IP6_RUL2_M0                        5
+#define IP6_RUL2_M0_OFFSET                 0x59000
+#define IP6_RUL2_M0_E_LENGTH               4
+#define IP6_RUL2_M0_E_OFFSET               0x20
+#define IP6_RUL2_M0_NR_E                   96
+
+#define IP6_SIPM0
+#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET      0
+#define IP6_RUL2_M0_IP6_SIPM0_BLEN         32
+#define IP6_RUL2_M0_IP6_SIPM0_FLAG         HSL_RW
+
+
+#define IP6_RUL2_M1                        6
+#define IP6_RUL2_M1_OFFSET                 0x59004
+#define IP6_RUL2_M1_E_LENGTH               4
+#define IP6_RUL2_M1_E_OFFSET               0x20
+#define IP6_RUL2_M1_NR_E                   96
+
+#define IP6_SIPM1
+#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET      0
+#define IP6_RUL2_M1_IP6_DIPM1_BLEN         32
+#define IP6_RUL2_M1_IP6_DIPM1_FLAG         HSL_RW
+
+
+#define IP6_RUL2_M2                        7
+#define IP6_RUL2_M2_OFFSET                 0x59008
+#define IP6_RUL2_M2_E_LENGTH               4
+#define IP6_RUL2_M2_E_OFFSET               0x20
+#define IP6_RUL2_M2_NR_E                   96
+
+#define IP6_SIPM2
+#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET      0
+#define IP6_RUL2_M2_IP6_DIPM2_BLEN         32
+#define IP6_RUL2_M2_IP6_DIPM2_FLAG         HSL_RW
+
+
+#define IP6_RUL2_M3                        8
+#define IP6_RUL2_M3_OFFSET                 0x5900c
+#define IP6_RUL2_M3_E_LENGTH               4
+#define IP6_RUL2_M3_E_OFFSET               0x20
+#define IP6_RUL2_M3_NR_E                   96
+
+#define IP6_SIPM3
+#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET      0
+#define IP6_RUL2_M3_IP6_SIPM3_BLEN         32
+#define IP6_RUL2_M3_IP6_SIPM3_FLAG         HSL_RW
+
+
+#define IP6_RUL2_M4                        9
+#define IP6_RUL2_M4_OFFSET                 0x59010
+#define IP6_RUL2_M4_E_LENGTH               4
+#define IP6_RUL2_M4_E_OFFSET               0x20
+#define IP6_RUL2_M4_NR_E                   96
+
+
+
+
+    /* IP6 Type3 Rule Field Define */
+#define IP6_RUL3_V0                        0
+#define IP6_RUL3_V0_OFFSET                 0x58000
+#define IP6_RUL3_V0_E_LENGTH               4
+#define IP6_RUL3_V0_E_OFFSET               0x20
+#define IP6_RUL3_V0_NR_E                   96
+
+#define IP6PROTV
+#define IP6_RUL3_V0_IP6PROTV_BOFFSET       0
+#define IP6_RUL3_V0_IP6PROTV_BLEN          8
+#define IP6_RUL3_V0_IP6PROTV_FLAG          HSL_RW
+
+#define IP6DSCPV
+#define IP6_RUL3_V0_IP6DSCPV_BOFFSET       8
+#define IP6_RUL3_V0_IP6DSCPV_BLEN          8
+#define IP6_RUL3_V0_IP6DSCPV_FLAG          HSL_RW
+
+
+#define IP6_RUL3_V1                        1
+#define IP6_RUL3_V1_OFFSET                 0x58004
+#define IP6_RUL3_V1_E_LENGTH               4
+#define IP6_RUL3_V1_E_OFFSET               0x20
+#define IP6_RUL3_V1_NR_E                   96
+
+#define IP6LABEL1V
+#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET     16
+#define IP6_RUL3_V1_IP6LABEL1V_BLEN        16
+#define IP6_RUL3_V1_IP6LABEL1V_FLAG        HSL_RW
+
+
+#define IP6_RUL3_V2                        2
+#define IP6_RUL3_V2_OFFSET                 0x58008
+#define IP6_RUL3_V2_E_LENGTH               4
+#define IP6_RUL3_V2_E_OFFSET               0x20
+#define IP6_RUL3_V2_NR_E                   96
+
+#define IP6LABEL2V
+#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET     0
+#define IP6_RUL3_V2_IP6LABEL2V_BLEN        4
+#define IP6_RUL3_V2_IP6LABEL2V_FLAG        HSL_RW
+
+#define IP6DPORTV
+#define IP6_RUL3_V2_IP6DPORTV_BOFFSET      16
+#define IP6_RUL3_V2_IP6DPORTV_BLEN         16
+#define IP6_RUL3_V2_IP6DPORTV_FLAG         HSL_RW
+
+
+#define IP6_RUL3_V3                        3
+#define IP6_RUL3_V3_OFFSET                 0x5800c
+#define IP6_RUL3_V3_E_LENGTH               4
+#define IP6_RUL3_V3_E_OFFSET               0x20
+#define IP6_RUL3_V3_NR_E                   96
+
+#define IP6TCPFLAGV
+#define IP6_RUL3_V3_IP6TCPFLAGV_BOFFSET    24
+#define IP6_RUL3_V3_IP6TCPFLAGV_BLEN       6
+#define IP6_RUL3_V3_IP6TCPFLAGV_FLAG       HSL_RW
+
+#define IP6FWDTYPV
+#define IP6_RUL3_V3_IP6FWDTYPV_BOFFSET     23
+#define IP6_RUL3_V3_IP6FWDTYPV_BLEN        1
+#define IP6_RUL3_V3_IP6FWDTYPV_FLAG        HSL_RW
+
+#define IP6DHCPV
+#define IP6_RUL3_V3_IP6DHCPV_BOFFSET       22
+#define IP6_RUL3_V3_IP6DHCPV_BLEN          1
+#define IP6_RUL3_V3_IP6DHCPV_FLAG          HSL_RW
+
+#define ICMP6_EN
+#define IP6_RUL3_V3_ICMP6_EN_BOFFSET       20
+#define IP6_RUL3_V3_ICMP6_EN_BLEN          1
+#define IP6_RUL3_V3_ICMP6_EN_FLAG          HSL_RW
+
+#define IP6SPORTV
+#define IP6_RUL3_V3_IP6SPORTV_BOFFSET      0
+#define IP6_RUL3_V3_IP6SPORTV_BLEN         16
+#define IP6_RUL3_V3_IP6SPORTV_FLAG         HSL_RW
+
+#define IP6ICMPTYPV
+#define IP6_RUL3_V3_IP6ICMPTYPV_BOFFSET    8
+#define IP6_RUL3_V3_IP6ICMPTYPV_BLEN       8
+#define IP6_RUL3_V3_IP6ICMPTYPV_FLAG       HSL_RW
+
+#define IP6ICMPCODEV
+#define IP6_RUL3_V3_IP6ICMPCODEV_BOFFSET   0
+#define IP6_RUL3_V3_IP6ICMPCODEV_BLEN      8
+#define IP6_RUL3_V3_IP6ICMPCODEV_FLAG      HSL_RW
+
+
+#define IP6_RUL3_V4                        4
+#define IP6_RUL3_V4_OFFSET                 0x58010
+#define IP6_RUL3_V4_E_LENGTH               4
+#define IP6_RUL3_V4_E_OFFSET               0x20
+#define IP6_RUL3_V4_NR_E                   96
+
+
+#define IP6_RUL3_M0                        5
+#define IP6_RUL3_M0_OFFSET                 0x59000
+#define IP6_RUL3_M0_E_LENGTH               4
+#define IP6_RUL3_M0_E_OFFSET               0x20
+#define IP6_RUL3_M0_NR_E                   96
+
+#define IP6PROTM
+#define IP6_RUL3_M0_IP6PROTM_BOFFSET       0
+#define IP6_RUL3_M0_IP6PROTM_BLEN          8
+#define IP6_RUL3_M0_IP6PROTM_FLAG          HSL_RW
+
+#define IP6DSCPM
+#define IP6_RUL3_M0_IP6DSCPM_BOFFSET       8
+#define IP6_RUL3_M0_IP6DSCPM_BLEN          8
+#define IP6_RUL3_M0_IP6DSCPM_FLAG          HSL_RW
+
+
+#define IP6_RUL3_M1                        6
+#define IP6_RUL3_M1_OFFSET                 0x59004
+#define IP6_RUL3_M1_E_LENGTH               4
+#define IP6_RUL3_M1_E_OFFSET               0x20
+#define IP6_RUL3_M1_NR_E                   96
+
+#define IP6LABEL1M
+#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET     16
+#define IP6_RUL3_M1_IP6LABEL1M_BLEN        16
+#define IP6_RUL3_M1_IP6LABEL1M_FLAG        HSL_RW
+
+
+#define IP6_RUL3_M2                        7
+#define IP6_RUL3_M2_OFFSET                 0x59008
+#define IP6_RUL3_M2_E_LENGTH               4
+#define IP6_RUL3_M2_E_OFFSET               0x20
+#define IP6_RUL3_M2_NR_E                   96
+
+#define IP6LABEL2M
+#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET     0
+#define IP6_RUL3_M2_IP6LABEL2M_BLEN        4
+#define IP6_RUL3_M2_IP6LABEL21M_FLAG       HSL_RW
+
+#define IP6DPORTM
+#define IP6_RUL3_M2_IP6DPORTM_BOFFSET      16
+#define IP6_RUL3_M2_IP6DPORTM_BLEN         16
+#define IP6_RUL3_M2_IP6DPORTM_FLAG         HSL_RW
+
+
+#define IP6_RUL3_M3                        8
+#define IP6_RUL3_M3_OFFSET                 0x5900c
+#define IP6_RUL3_M3_E_LENGTH               4
+#define IP6_RUL3_M3_E_OFFSET               0x20
+#define IP6_RUL3_M3_NR_E                   96
+
+#define IP6TCPFLAGM
+#define IP6_RUL3_M3_IP6TCPFLAGM_BOFFSET    24
+#define IP6_RUL3_M3_IP6TCPFLAGM_BLEN       6
+#define IP6_RUL3_M3_IP6TCPFLAGM_FLAG       HSL_RW
+
+#define IP6RWDTYPM
+#define IP6_RUL3_M3_IP6RWDTYPV_BOFFSET     23
+#define IP6_RUL3_M3_IP6RWDTYPV_BLEN        1
+#define IP6_RUL3_M3_IP6RWDTYPV_FLAG        HSL_RW
+
+#define IP6DHCPM
+#define IP6_RUL3_M3_IP6DHCPM_BOFFSET       22
+#define IP6_RUL3_M3_IP6DHCPM_BLEN          1
+#define IP6_RUL3_M3_IP6DHCPM_FLAG          HSL_RW
+
+#define IP6DPORTM_EN
+#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET   17
+#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN      1
+#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG      HSL_RW
+
+#define IP6SPORTM_EN
+#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET   16
+#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN      1
+#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG      HSL_RW
+
+#define IP6SPORTM
+#define IP6_RUL3_M3_IP6SPORTM_BOFFSET      0
+#define IP6_RUL3_M3_IP6SPORTM_BLEN         16
+#define IP6_RUL3_M3_IP6SPORTM_FLAG         HSL_RW
+
+#define IP6ICMPTYPM
+#define IP6_RUL3_M3_IP6ICMPTYPM_BOFFSET     8
+#define IP6_RUL3_M3_IP6ICMPTYPM_BLEN        8
+#define IP6_RUL3_M3_IP6ICMPTYPM_FLAG        HSL_RW
+
+#define IP6ICMPCODEM
+#define IP6_RUL3_M3_IP6ICMPCODEM_BOFFSET    0
+#define IP6_RUL3_M3_IP6ICMPCODEM_BLEN       8
+#define IP6_RUL3_M3_IP6ICMPCODEM_FLAG       HSL_RW
+
+
+#define IP6_RUL3_M4                        9
+#define IP6_RUL3_M4_OFFSET                 0x59010
+#define IP6_RUL3_M4_E_LENGTH               4
+#define IP6_RUL3_M4_E_OFFSET               0x20
+#define IP6_RUL3_M4_NR_E                   96
+
+
+
+
+    /* Enhanced MAC Type Rule Field Define */
+#define EHMAC_RUL_V0                         0
+#define EHMAC_RUL_V0_OFFSET                  0x58000
+#define EHMAC_RUL_V0_E_LENGTH                4
+#define EHMAC_RUL_V0_E_OFFSET                0x20
+#define EHMAC_RUL_V0_NR_E                    96
+
+#define DAV_BYTE2
+#define EHMAC_RUL_V0_DAV_BYTE2_BOFFSET       24
+#define EHMAC_RUL_V0_DAV_BYTE2_BLEN          8
+#define EHMAC_RUL_V0_DAV_BYTE2_FLAG          HSL_RW
+
+#define DAV_BYTE3
+#define EHMAC_RUL_V0_DAV_BYTE3_BOFFSET       16
+#define EHMAC_RUL_V0_DAV_BYTE3_BLEN          8
+#define EHMAC_RUL_V0_DAV_BYTE3_FLAG          HSL_RW
+
+#define DAV_BYTE4
+#define EHMAC_RUL_V0_DAV_BYTE4_BOFFSET       8
+#define EHMAC_RUL_V0_DAV_BYTE4_BLEN          8
+#define EHMAC_RUL_V0_DAV_BYTE4_FLAG          HSL_RW
+
+#define DAV_BYTE5
+#define EHMAC_RUL_V0_DAV_BYTE5_BOFFSET       0
+#define EHMAC_RUL_V0_DAV_BYTE5_BLEN          8
+#define EHMAC_RUL_V0_DAV_BYTE5_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_V1                         1
+#define EHMAC_RUL_V1_OFFSET                  0x58004
+#define EHMAC_RUL_V1_E_LENGTH                4
+#define EHMAC_RUL_V1_E_OFFSET                0x20
+#define EHMAC_RUL_V1_NR_E                    96
+
+#define SAV_BYTE4
+#define EHMAC_RUL_V1_SAV_BYTE4_BOFFSET       24
+#define EHMAC_RUL_V1_SAV_BYTE4_BLEN          8
+#define EHMAC_RUL_V1_SAV_BYTE4_FLAG          HSL_RW
+
+#define SAV_BYTE5
+#define EHMAC_RUL_V1_SAV_BYTE5_BOFFSET       16
+#define EHMAC_RUL_V1_SAV_BYTE5_BLEN          8
+#define EHMAC_RUL_V1_SAV_BYTE5_FLAG          HSL_RW
+
+#define DAV_BYTE0
+#define EHMAC_RUL_V1_DAV_BYTE0_BOFFSET       8
+#define EHMAC_RUL_V1_DAV_BYTE0_BLEN          8
+#define EHMAC_RUL_V1_DAV_BYTE0_FLAG          HSL_RW
+
+#define DAV_BYTE1
+#define EHMAC_RUL_V1_DAV_BYTE1_BOFFSET       0
+#define EHMAC_RUL_V1_DAV_BYTE1_BLEN          8
+#define EHMAC_RUL_V1_DAV_BYTE1_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_V2                         2
+#define EHMAC_RUL_V2_OFFSET                  0x58008
+#define EHMAC_RUL_V2_E_LENGTH                4
+#define EHMAC_RUL_V2_E_OFFSET                0x20
+#define EHMAC_RUL_V2_NR_E                    96
+
+#define CTAG_VIDLV
+#define EHMAC_RUL_V2_CTAG_VIDLV_BOFFSET      24
+#define EHMAC_RUL_V2_CTAG_VIDLV_BLEN         8
+#define EHMAC_RUL_V2_CTAG_VIDLV_FLAG         HSL_RW
+
+#define STAG_PRIV
+#define EHMAC_RUL_V2_STAG_PRIV_BOFFSET       21
+#define EHMAC_RUL_V2_STAG_PRIV_BLEN          3
+#define EHMAC_RUL_V2_STAG_PRIV_FLAG          HSL_RW
+
+#define STAG_DEIV
+#define EHMAC_RUL_V2_STAG_DEIV_BOFFSET       20
+#define EHMAC_RUL_V2_STAG_DEIV_BLEN          1
+#define EHMAC_RUL_V2_STAG_DEIV_FLAG          HSL_RW
+
+#define STAG_VIDV
+#define EHMAC_RUL_V2_STAG_VIDV_BOFFSET       8
+#define EHMAC_RUL_V2_STAG_VIDV_BLEN          12
+#define EHMAC_RUL_V2_STAG_VIDV_FLAG          HSL_RW
+
+#define SAV_BYTE3
+#define EHMAC_RUL_V2_SAV_BYTE3_BOFFSET       0
+#define EHMAC_RUL_V2_SAV_BYTE3_BLEN          8
+#define EHMAC_RUL_V2_SAV_BYTE3_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_V3                         3
+#define EHMAC_RUL_V3_ID                      13
+#define EHMAC_RUL_V3_OFFSET                  0x5800c
+#define EHMAC_RUL_V3_E_LENGTH                4
+#define EHMAC_RUL_V3_E_OFFSET                0x20
+#define EHMAC_RUL_V3_NR_E                    96
+
+#define STAGGEDM
+#define EHMAC_RUL_V3_STAGGEDM_BOFFSET         31
+#define EHMAC_RUL_V3_STAGGEDM_BLEN            1
+#define EHMAC_RUL_V3_STAGGEDM_FLAG            HSL_RW
+
+#define STAGGEDV
+#define EHMAC_RUL_V3_STAGGEDV_BOFFSET         30
+#define EHMAC_RUL_V3_STAGGEDV_BLEN            1
+#define EHMAC_RUL_V3_STAGGEDV_FLAG            HSL_RW
+
+#define DA_EN
+#define EHMAC_RUL_V3_DA_EN_BOFFSET          25
+#define EHMAC_RUL_V3_DA_EN_BLEN             1
+#define EHMAC_RUL_V3_DA_EN_FLAG             HSL_RW
+
+#define SVIDMSK
+#define EHMAC_RUL_V3_SVIDMSK_BOFFSET          24
+#define EHMAC_RUL_V3_SVIDMSK_BLEN             1
+#define EHMAC_RUL_V3_SVIDMSK_FLAG             HSL_RW
+
+#define ETHTYPV
+#define EHMAC_RUL_V3_ETHTYPV_BOFFSET         8
+#define EHMAC_RUL_V3_ETHTYPV_BLEN            16
+#define EHMAC_RUL_V3_ETHTYPV_FLAG            HSL_RW
+
+#define CTAG_PRIV
+#define EHMAC_RUL_V3_CTAG_PRIV_BOFFSET       5
+#define EHMAC_RUL_V3_CTAG_PRIV_BLEN          3
+#define EHMAC_RUL_V3_CTAG_PRIV_FLAG          HSL_RW
+
+#define CTAG_CFIV
+#define EHMAC_RUL_V3_CTAG_CFIV_BOFFSET       4
+#define EHMAC_RUL_V3_CTAG_CFIV_BLEN          1
+#define EHMAC_RUL_V3_CTAG_CFIV_FLAG          HSL_RW
+
+#define CTAG_VIDHV
+#define EHMAC_RUL_V3_CTAG_VIDHV_BOFFSET      0
+#define EHMAC_RUL_V3_CTAG_VIDHV_BLEN         4
+#define EHMAC_RUL_V3_CTAG_VIDHV_FLAG         HSL_RW
+
+
+#define EHMAC_RUL_V4                         4
+#define EHMAC_RUL_V4_OFFSET                  0x58010
+#define EHMAC_RUL_V4_E_LENGTH                4
+#define EHMAC_RUL_V4_E_OFFSET                0x20
+#define EHMAC_RUL_V4_NR_E                    96
+
+
+#define EHMAC_RUL_M0                         5
+#define EHMAC_RUL_M0_OFFSET                  0x59000
+#define EHMAC_RUL_M0_E_LENGTH                4
+#define EHMAC_RUL_M0_E_OFFSET                0x20
+#define EHMAC_RUL_M0_NR_E                    96
+
+#define DAM_BYTE2
+#define EHMAC_RUL_M0_DAM_BYTE2_BOFFSET       24
+#define EHMAC_RUL_M0_DAM_BYTE2_BLEN          8
+#define EHMAC_RUL_M0_DAM_BYTE2_FLAG          HSL_RW
+
+#define DAM_BYTE3
+#define EHMAC_RUL_M0_DAM_BYTE3_BOFFSET       16
+#define EHMAC_RUL_M0_DAM_BYTE3_BLEN          8
+#define EHMAC_RUL_M0_DAM_BYTE3_FLAG          HSL_RW
+
+#define DAM_BYTE4
+#define EHMAC_RUL_M0_DAM_BYTE4_BOFFSET       8
+#define EHMAC_RUL_M0_DAM_BYTE4_BLEN          8
+#define EHMAC_RUL_M0_DAM_BYTE4_FLAG          HSL_RW
+
+#define DAM_BYTE5
+#define EHMAC_RUL_M0_DAM_BYTE5_BOFFSET       0
+#define EHMAC_RUL_M0_DAM_BYTE5_BLEN          8
+#define EHMAC_RUL_M0_DAM_BYTE5_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_M1                         6
+#define EHMAC_RUL_M1_OFFSET                  0x59004
+#define EHMAC_RUL_M1_E_LENGTH                4
+#define EHMAC_RUL_M1_E_OFFSET                0x20
+#define EHMAC_RUL_M1_NR_E                    96
+
+#define SAM_BYTE4
+#define EHMAC_RUL_M1_SAM_BYTE4_BOFFSET       24
+#define EHMAC_RUL_M1_SAM_BYTE4_BLEN          8
+#define EHMAC_RUL_M1_SAM_BYTE4_FLAG          HSL_RW
+
+#define SAM_BYTE5
+#define EHMAC_RUL_M1_SAM_BYTE5_BOFFSET       16
+#define EHMAC_RUL_M1_SAM_BYTE5_BLEN          8
+#define EHMAC_RUL_M1_SAM_BYTE5_FLAG          HSL_RW
+
+#define DAM_BYTE0
+#define EHMAC_RUL_M1_DAM_BYTE0_BOFFSET       8
+#define EHMAC_RUL_M1_DAM_BYTE0_BLEN          8
+#define EHMAC_RUL_M1_DAM_BYTE0_FLAG          HSL_RW
+
+#define DAM_BYTE1
+#define EHMAC_RUL_M1_DAM_BYTE1_BOFFSET       0
+#define EHMAC_RUL_M1_DAM_BYTE1_BLEN          8
+#define EHMAC_RUL_M1_DAM_BYTE1_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_M2                         7
+#define EHMAC_RUL_M2_OFFSET                  0x59008
+#define EHMAC_RUL_M2_E_LENGTH                4
+#define EHMAC_RUL_M2_E_OFFSET                0x20
+#define EHMAC_RUL_M2_NR_E                    96
+
+#define CTAG_VIDLM
+#define EHMAC_RUL_M2_CTAG_VIDLM_BOFFSET      24
+#define EHMAC_RUL_M2_CTAG_VIDLM_BLEN         8
+#define EHMAC_RUL_M2_CTAG_VIDLM_FLAG         HSL_RW
+
+#define STAG_PRIM
+#define EHMAC_RUL_M2_STAG_PRIM_BOFFSET       21
+#define EHMAC_RUL_M2_STAG_PRIM_BLEN          3
+#define EHMAC_RUL_M2_STAG_PRIM_FLAG          HSL_RW
+
+#define STAG_DEIM
+#define EHMAC_RUL_M2_STAG_DEIM_BOFFSET       20
+#define EHMAC_RUL_M2_STAG_DEIM_BLEN          1
+#define EHMAC_RUL_M2_STAG_DEIM_FLAG          HSL_RW
+
+#define STAG_VIDM
+#define EHMAC_RUL_M2_STAG_VIDM_BOFFSET       8
+#define EHMAC_RUL_M2_STAG_VIDM_BLEN          12
+#define EHMAC_RUL_M2_STAG_VIDM_FLAG          HSL_RW
+
+#define SAM_BYTE3
+#define EHMAC_RUL_M2_SAM_BYTE3_BOFFSET       0
+#define EHMAC_RUL_M2_SAM_BYTE3_BLEN          8
+#define EHMAC_RUL_M2_SAM_BYTE3_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_M3                         8
+#define EHMAC_RUL_M3_OFFSET                  0x5900c
+#define EHMAC_RUL_M3_E_LENGTH                4
+#define EHMAC_RUL_M3_E_OFFSET                0x20
+#define EHMAC_RUL_M3_NR_E                    96
+
+#define ETHTYPM
+#define EHMAC_RUL_M3_ETHTYPM_BOFFSET         8
+#define EHMAC_RUL_M3_ETHTYPM_BLEN            16
+#define EHMAC_RUL_M3_ETHTYPM_FLAG            HSL_RW
+
+#define CTAG_PRIM
+#define EHMAC_RUL_M3_CTAG_PRIM_BOFFSET       5
+#define EHMAC_RUL_M3_CTAG_PRIM_BLEN          3
+#define EHMAC_RUL_M3_CTAG_PRIM_FLAG          HSL_RW
+
+#define CTAG_CFIM
+#define EHMAC_RUL_M3_CTAG_CFIM_BOFFSET       4
+#define EHMAC_RUL_M3_CTAG_CFIM_BLEN          1
+#define EHMAC_RUL_M3_CTAG_CFIM_FLAG          HSL_RW
+
+#define CTAG_VIDHM
+#define EHMAC_RUL_M3_CTAG_VIDHM_BOFFSET      0
+#define EHMAC_RUL_M3_CTAG_VIDHM_BLEN         4
+#define EHMAC_RUL_M3_CTAG_VIDHM_FLAG         HSL_RW
+
+
+#define EHMAC_RUL_M4                         9
+#define EHMAC_RUL_M4_OFFSET                  0x59010
+#define EHMAC_RUL_M4_E_LENGTH                4
+#define EHMAC_RUL_M4_E_OFFSET                0x20
+#define EHMAC_RUL_M4_NR_E                    96
+
+#define CTAGGEDM
+#define EHMAC_RUL_M4_CTAGGEDM_BOFFSET        5
+#define EHMAC_RUL_M4_CTAGGEDM_BLEN           1
+#define EHMAC_RUL_M4_CTAGGEDM_FLAG           HSL_RW
+
+#define CTAGGEDV
+#define EHMAC_RUL_M4_CTAGGEDV_BOFFSET        4
+#define EHMAC_RUL_M4_CTAGGEDV_BLEN           1
+#define EHMAC_RUL_M4_CTAGGEDV_FLAG           HSL_RW
+
+#define CVIDMSK
+#define EHMAC_RUL_M4_CVIDMSK_BOFFSET         3
+#define EHMAC_RUL_M4_CVIDMSK_BLEN            1
+#define EHMAC_RUL_M4_CVIDMSK_FLAG            HSL_RW
+
+
+
+
+    /* PPPoE Session Table Define */
+#define PPPOE_SESSION
+#define PPPOE_SESSION_OFFSET                       0x5f000
+#define PPPOE_SESSION_E_LENGTH                     4
+#define PPPOE_SESSION_E_OFFSET                     0x4
+#define PPPOE_SESSION_NR_E                         16
+
+#define ENTRY_VALID
+#define PPPOE_SESSION_ENTRY_VALID_BOFFSET          16
+#define PPPOE_SESSION_ENTRY_VALID_BLEN             2
+#define PPPOE_SESSION_ENTRY_VALID_FLAG             HSL_RW
+
+#define SEESION_ID
+#define PPPOE_SESSION_SEESION_ID_BOFFSET           0
+#define PPPOE_SESSION_SEESION_ID_BLEN              16
+#define PPPOE_SESSION_SEESION_ID_FLAG              HSL_RW
+
+
+#define PPPOE_EDIT
+#define PPPOE_EDIT_OFFSET                       0x02200
+#define PPPOE_EDIT_E_LENGTH                     4
+#define PPPOE_EDIT_E_OFFSET                     0x10
+#define PPPOE_EDIT_NR_E                         16
+
+#define EDIT_ID
+#define PPPOE_EDIT_EDIT_ID_BOFFSET              0
+#define PPPOE_EDIT_EDIT_ID_BLEN                 16
+#define PPPOE_EDIT_EDIT_ID_FLAG                 HSL_RW
+
+
+
+
+    /* L3 Host Entry Defile */
+#define HOST_ENTRY0
+#define HOST_ENTRY0_OFFSET                       0x0e48
+#define HOST_ENTRY0_E_LENGTH                     4
+#define HOST_ENTRY0_E_OFFSET                     0x0
+#define HOST_ENTRY0_NR_E                         1
+
+#define IP_ADDR
+#define HOST_ENTRY0_IP_ADDR_BOFFSET              0
+#define HOST_ENTRY0_IP_ADDR_BLEN                 32
+#define HOST_ENTRY0_IP_ADDR_FLAG                 HSL_RW
+
+#define HOST_ENTRY1
+#define HOST_ENTRY1_OFFSET                       0x0e4c
+#define HOST_ENTRY1_E_LENGTH                     4
+#define HOST_ENTRY1_E_OFFSET                     0x0
+#define HOST_ENTRY1_NR_E                         1
+
+#define MAC_ADDR2
+#define HOST_ENTRY1_MAC_ADDR2_BOFFSET            24
+#define HOST_ENTRY1_MAC_ADDR2_BLEN               8
+#define HOST_ENTRY1_MAC_ADDR2_FLAG               HSL_RW
+
+#define MAC_ADDR3
+#define HOST_ENTRY1_MAC_ADDR3_BOFFSET            16
+#define HOST_ENTRY1_MAC_ADDR3_BLEN               8
+#define HOST_ENTRY1_MAC_ADDR3_FLAG               HSL_RW
+
+#define MAC_ADDR4
+#define HOST_ENTRY1_MAC_ADDR4_BOFFSET            8
+#define HOST_ENTRY1_MAC_ADDR4_BLEN               8
+#define HOST_ENTRY1_MAC_ADDR4_FLAG               HSL_RW
+
+#define MAC_ADDR5
+#define HOST_ENTRY1_MAC_ADDR5_BOFFSET            0
+#define HOST_ENTRY1_MAC_ADDR5_BLEN               8
+#define HOST_ENTRY1_MAC_ADDR5_FLAG               HSL_RW
+
+#define HOST_ENTRY2
+#define HOST_ENTRY2_OFFSET                       0x0e50
+#define HOST_ENTRY2_E_LENGTH                     4
+#define HOST_ENTRY2_E_OFFSET                     0x0
+#define HOST_ENTRY2_NR_E                         1
+
+#define CPU_ADDR
+#define HOST_ENTRY2_CPU_ADDR_BOFFSET             31
+#define HOST_ENTRY2_CPU_ADDR_BLEN                1
+#define HOST_ENTRY2_CPU_ADDR_FLAG                HSL_RW
+
+#define SRC_PORT
+#define HOST_ENTRY2_SRC_PORT_BOFFSET             28
+#define HOST_ENTRY2_SRC_PORT_BLEN                3
+#define HOST_ENTRY2_SRC_PORT_FLAG                HSL_RW
+
+#define INTF_ID
+#define HOST_ENTRY2_INTF_ID_BOFFSET              16
+#define HOST_ENTRY2_INTF_ID_BLEN                 12
+#define HOST_ENTRY2_INTF_ID_FLAG                 HSL_RW
+
+#define MAC_ADDR0
+#define HOST_ENTRY2_MAC_ADDR0_BOFFSET            8
+#define HOST_ENTRY2_MAC_ADDR0_BLEN               8
+#define HOST_ENTRY2_MAC_ADDR0_FLAG               HSL_RW
+
+#define MAC_ADDR1
+#define HOST_ENTRY2_MAC_ADDR1_BOFFSET            0
+#define HOST_ENTRY2_MAC_ADDR1_BLEN               8
+#define HOST_ENTRY2_MAC_ADDR1_FLAG               HSL_RW
+
+
+#define HOST_ENTRY3
+#define HOST_ENTRY3_OFFSET                       0x0e54
+#define HOST_ENTRY3_E_LENGTH                     4
+#define HOST_ENTRY3_E_OFFSET                     0x0
+#define HOST_ENTRY3_NR_E                         1
+
+#define IP_VER
+#define HOST_ENTRY3_IP_VER_BOFFSET               15
+#define HOST_ENTRY3_IP_VER_BLEN                  1
+#define HOST_ENTRY3_IP_VER_FLAG                  HSL_RW
+
+#define AGE_FLAG
+#define HOST_ENTRY3_AGE_FLAG_BOFFSET             12
+#define HOST_ENTRY3_AGE_FLAG_BLEN                3
+#define HOST_ENTRY3_AGE_FLAG_FLAG                HSL_RW
+
+#define PPPOE_EN
+#define HOST_ENTRY3_PPPOE_EN_BOFFSET             11
+#define HOST_ENTRY3_PPPOE_EN_BLEN                1
+#define HOST_ENTRY3_PPPOE_EN_FLAG                HSL_RW
+
+#define PPPOE_IDX
+#define HOST_ENTRY3_PPPOE_IDX_BOFFSET            7
+#define HOST_ENTRY3_PPPOE_IDX_BLEN               4
+#define HOST_ENTRY3_PPPOE_IDX_FLAG               HSL_RW
+
+#define CNT_EN
+#define HOST_ENTRY3_CNT_EN_BOFFSET               6
+#define HOST_ENTRY3_CNT_EN_BLEN                  1
+#define HOST_ENTRY3_CNT_EN_FLAG                  HSL_RW
+
+#define CNT_IDX
+#define HOST_ENTRY3_CNT_IDX_BOFFSET              2
+#define HOST_ENTRY3_CNT_IDX_BLEN                 4
+#define HOST_ENTRY3_CNT_IDX_FLAG                 HSL_RW
+
+#define ACTION
+#define HOST_ENTRY3_ACTION_BOFFSET               0
+#define HOST_ENTRY3_ACTION_BLEN                  2
+#define HOST_ENTRY3_ACTION_FLAG                  HSL_RW
+
+
+#define HOST_ENTRY4
+#define HOST_ENTRY4_OFFSET                       0x0e58
+#define HOST_ENTRY4_E_LENGTH                     4
+#define HOST_ENTRY4_E_OFFSET                     0x0
+#define HOST_ENTRY4_NR_E                         1
+
+#define TBL_BUSY
+#define HOST_ENTRY4_TBL_BUSY_BOFFSET             31
+#define HOST_ENTRY4_TBL_BUSY_BLEN                1
+#define HOST_ENTRY4_TBL_BUSY_FLAG                HSL_RW
+
+#define SPEC_SP
+#define HOST_ENTRY4_SPEC_SP_BOFFSET              22
+#define HOST_ENTRY4_SPEC_SP_BLEN                 1
+#define HOST_ENTRY4_SPEC_SP_FLAG                 HSL_RW
+
+#define SPEC_VID
+#define HOST_ENTRY4_SPEC_VID_BOFFSET             21
+#define HOST_ENTRY4_SPEC_VID_BLEN                1
+#define HOST_ENTRY4_SPEC_VID_FLAG                HSL_RW
+
+#define SPEC_PIP
+#define HOST_ENTRY4_SPEC_PIP_BOFFSET             20
+#define HOST_ENTRY4_SPEC_PIP_BLEN                1
+#define HOST_ENTRY4_SPEC_PIP_FLAG                HSL_RW
+
+#define SPEC_SIP
+#define HOST_ENTRY4_SPEC_SIP_BOFFSET             19
+#define HOST_ENTRY4_SPEC_SIP_BLEN                1
+#define HOST_ENTRY4_SPEC_SIP_FLAG                HSL_RW
+
+#define SPEC_STATUS
+#define HOST_ENTRY4_SPEC_STATUS_BOFFSET          18
+#define HOST_ENTRY4_SPEC_STATUS_BLEN             1
+#define HOST_ENTRY4_SPEC_STATUS_FLAG             HSL_RW
+
+#define TBL_IDX
+#define HOST_ENTRY4_TBL_IDX_BOFFSET              8
+#define HOST_ENTRY4_TBL_IDX_BLEN                 10
+#define HOST_ENTRY4_TBL_IDX_FLAG                 HSL_RW
+
+#define TBL_STAUS
+#define HOST_ENTRY4_TBL_STAUS_BOFFSET            7
+#define HOST_ENTRY4_TBL_STAUS_BLEN               1
+#define HOST_ENTRY4_TBL_STAUS_FLAG               HSL_RW
+
+#define TBL_SEL
+#define HOST_ENTRY4_TBL_SEL_BOFFSET              4
+#define HOST_ENTRY4_TBL_SEL_BLEN                 2
+#define HOST_ENTRY4_TBL_SEL_FLAG                 HSL_RW
+
+#define ENTRY_FUNC
+#define HOST_ENTRY4_ENTRY_FUNC_BOFFSET           0
+#define HOST_ENTRY4_ENTRY_FUNC_BLEN              3
+#define HOST_ENTRY4_ENTRY_FUNC_FLAG              HSL_RW
+
+
+
+
+#define NAT_ENTRY0
+#define NAT_ENTRY0_OFFSET                       0x0e48
+#define NAT_ENTRY0_E_LENGTH                     4
+#define NAT_ENTRY0_E_OFFSET                     0x0
+#define NAT_ENTRY0_NR_E                         1
+
+#define IP_ADDR
+#define NAT_ENTRY0_IP_ADDR_BOFFSET              0
+#define NAT_ENTRY0_IP_ADDR_BLEN                 32
+#define NAT_ENTRY0_IP_ADDR_FLAG                 HSL_RW
+
+
+#define NAT_ENTRY1
+#define NAT_ENTRY1_OFFSET                       0x0e4c
+#define NAT_ENTRY1_E_LENGTH                     4
+#define NAT_ENTRY1_E_OFFSET                     0x0
+#define NAT_ENTRY1_NR_E                         1
+
+#define PRV_IPADDR0
+#define NAT_ENTRY1_PRV_IPADDR0_BOFFSET          24
+#define NAT_ENTRY1_PRV_IPADDR0_BLEN             8
+#define NAT_ENTRY1_PRV_IPADDR0_FLAG             HSL_RW
+
+#define PORT_RANGE
+#define NAT_ENTRY1_PORT_RANGE_BOFFSET            16
+#define NAT_ENTRY1_PORT_RANGE_BLEN               8
+#define NAT_ENTRY1_PORT_RANGE_FLAG               HSL_RW
+
+#define PORT_NUM
+#define NAT_ENTRY1_PORT_NUM_BOFFSET              0
+#define NAT_ENTRY1_PORT_NUM_BLEN                 16
+#define NAT_ENTRY1_PORT_NUM_FLAG                 HSL_RW
+
+
+#define NAT_ENTRY2
+#define NAT_ENTRY2_OFFSET                       0x0e50
+#define NAT_ENTRY2_E_LENGTH                     4
+#define NAT_ENTRY2_E_OFFSET                     0x0
+#define NAT_ENTRY2_NR_E                         1
+
+#define ENTRY_VALID
+#define NAT_ENTRY2_ENTRY_VALID_BOFFSET          15
+#define NAT_ENTRY2_ENTRY_VALID_BLEN             1
+#define NAT_ENTRY2_ENTRY_VALID_FLAG             HSL_RW
+
+#define PORT_EN
+#define NAT_ENTRY2_PORT_EN_BOFFSET              14
+#define NAT_ENTRY2_PORT_EN_BLEN                 1
+#define NAT_ENTRY2_PORT_EN_FLAG                 HSL_RW
+
+#define PRO_TYP
+#define NAT_ENTRY2_PRO_TYP_BOFFSET              12
+#define NAT_ENTRY2_PRO_TYP_BLEN                 2
+#define NAT_ENTRY2_PRO_TYP_FLAG                 HSL_RW
+
+#define HASH_KEY
+#define NAT_ENTRY2_HASH_KEY_BOFFSET             10
+#define NAT_ENTRY2_HASH_KEY_BLEN                2
+#define NAT_ENTRY2_HASH_KEY_FLAG                HSL_RW
+
+#define ACTION
+#define NAT_ENTRY2_ACTION_BOFFSET               8
+#define NAT_ENTRY2_ACTION_BLEN                  2
+#define NAT_ENTRY2_ACTION_FLAG                  HSL_RW
+
+#define CNT_EN
+#define NAT_ENTRY2_CNT_EN_BOFFSET               7
+#define NAT_ENTRY2_CNT_EN_BLEN                  1
+#define NAT_ENTRY2_CNT_EN_FLAG                  HSL_RW
+
+#define CNT_IDX
+#define NAT_ENTRY2_CNT_IDX_BOFFSET              4
+#define NAT_ENTRY2_CNT_IDX_BLEN                 3
+#define NAT_ENTRY2_CNT_IDX_FLAG                 HSL_RW
+
+#define PRV_IPADDR1
+#define NAT_ENTRY2_PRV_IPADDR1_BOFFSET          0
+#define NAT_ENTRY2_PRV_IPADDR1_BLEN             4
+#define NAT_ENTRY2_PRV_IPADDR1_FLAG             HSL_RW
+
+
+
+
+#define NAPT_ENTRY0
+#define NAPT_ENTRY0_OFFSET                       0x0e48
+#define NAPT_ENTRY0_E_LENGTH                     4
+#define NAPT_ENTRY0_E_OFFSET                     0x0
+#define NAPT_ENTRY0_NR_E                         1
+
+#define DST_IPADDR
+#define NAPT_ENTRY0_DST_IPADDR_BOFFSET           0
+#define NAPT_ENTRY0_DST_IPADDR_BLEN              32
+#define NAPT_ENTRY0_DST_IPADDR_FLAG              HSL_RW
+
+
+#define NAPT_ENTRY1
+#define NAPT_ENTRY1_OFFSET                       0x0e4c
+#define NAPT_ENTRY1_E_LENGTH                     4
+#define NAPT_ENTRY1_E_OFFSET                     0x0
+#define NAPT_ENTRY1_NR_E                         1
+
+#define SRC_PORT
+#define NAPT_ENTRY1_SRC_PORT_BOFFSET            16
+#define NAPT_ENTRY1_SRC_PORT_BLEN              16
+#define NAPT_ENTRY1_SRC_PORT_FLAG              HSL_RW
+
+#define DST_PORT
+#define NAPT_ENTRY1_DST_PORT_BOFFSET           0
+#define NAPT_ENTRY1_DST_PORT_BLEN              16
+#define NAPT_ENTRY1_DST_PORT_FLAG              HSL_RW
+
+
+#define NAPT_ENTRY2
+#define NAPT_ENTRY2_OFFSET                       0x0e50
+#define NAPT_ENTRY2_E_LENGTH                     4
+#define NAPT_ENTRY2_E_OFFSET                     0x0
+#define NAPT_ENTRY2_NR_E                         1
+
+#define SRC_IPADDR
+#define NAPT_ENTRY2_SRC_IPADDR_BOFFSET           20
+#define NAPT_ENTRY2_SRC_IPADDR_BLEN              12
+#define NAPT_ENTRY2_SRC_IPADDR_FLAG              HSL_RW
+
+#define TRANS_IPADDR
+#define NAPT_ENTRY2_TRANS_IPADDR_BOFFSET           16
+#define NAPT_ENTRY2_TRANS_IPADDR_BLEN              4
+#define NAPT_ENTRY2_TRANS_IPADDR_FLAG              HSL_RW
+
+#define TRANS_PORT
+#define NAPT_ENTRY2_TRANS_PORT_BOFFSET           0
+#define NAPT_ENTRY2_TRANS_PORT_BLEN              16
+#define NAPT_ENTRY2_TRANS_PORT_FLAG              HSL_RW
+
+
+#define NAPT_ENTRY3
+#define NAPT_ENTRY3_OFFSET                       0x0e54
+#define NAPT_ENTRY3_E_LENGTH                     4
+#define NAPT_ENTRY3_E_OFFSET                     0x0
+#define NAPT_ENTRY3_NR_E                         1
+
+#define AGE_FLAG
+#define NAPT_ENTRY3_AGE_FLAG_BOFFSET             12
+#define NAPT_ENTRY3_AGE_FLAG_BLEN                4
+#define NAPT_ENTRY3_AGE_FLAG_FLAG                HSL_RW
+
+#define CNT_EN
+#define NAPT_ENTRY3_CNT_EN_BOFFSET               7
+#define NAPT_ENTRY3_CNT_EN_BLEN                  1
+#define NAPT_ENTRY3_CNT_EN_FLAG                  HSL_RW
+
+#define CNT_IDX
+#define NAPT_ENTRY3_CNT_IDX_BOFFSET              4
+#define NAPT_ENTRY3_CNT_IDX_BLEN                 3
+#define NAPT_ENTRY3_CNT_IDX_FLAG                 HSL_RW
+
+#define PROT_TYP
+#define NAPT_ENTRY3_PROT_TYP_BOFFSET             2
+#define NAPT_ENTRY3_PROT_TYP_BLEN                2
+#define NAPT_ENTRY3_PROT_TYP_FLAG                HSL_RW
+
+#define ACTION
+#define NAPT_ENTRY3_ACTION_BOFFSET               0
+#define NAPT_ENTRY3_ACTION_BLEN                  2
+#define NAPT_ENTRY3_ACTION_FLAG                  HSL_RW
+
+
+
+
+#define ROUTER_CTRL
+#define ROUTER_CTRL_OFFSET                       0x0e00
+#define ROUTER_CTRL_E_LENGTH                     4
+#define ROUTER_CTRL_E_OFFSET                     0x0
+#define ROUTER_CTRL_NR_E                         1
+
+#define ARP_LEARN_MODE
+#define ROUTER_CTRL_ARP_LEARN_MODE_BOFFSET       19
+#define ROUTER_CTRL_ARP_LEARN_MODE_BLEN          1
+#define ROUTER_CTRL_ARP_LEARN_MODE_FLAG          HSL_RW
+
+#define GLB_LOCKTIME
+#define ROUTER_CTRL_GLB_LOCKTIME_BOFFSET       16
+#define ROUTER_CTRL_GLB_LOCKTIME_BLEN          2
+#define ROUTER_CTRL_GLB_LOCKTIME_FLAG          HSL_RW
+
+#define ARP_AGE_TIME
+#define ROUTER_CTRL_ARP_AGE_TIME_BOFFSET         8
+#define ROUTER_CTRL_ARP_AGE_TIME_BLEN            8
+#define ROUTER_CTRL_ARP_AGE_TIME_FLAG            HSL_RW
+
+#define WCMP_HAHS_DP
+#define ROUTER_CTRL_WCMP_HAHS_DP_BOFFSET         7
+#define ROUTER_CTRL_WCMP_HAHS_DP_BLEN            1
+#define ROUTER_CTRL_WCMP_HAHS_DP_FLAG            HSL_RW
+
+#define WCMP_HAHS_DIP
+#define ROUTER_CTRL_WCMP_HAHS_DIP_BOFFSET        6
+#define ROUTER_CTRL_WCMP_HAHS_DIP_BLEN           1
+#define ROUTER_CTRL_WCMP_HAHS_DIP_FLAG           HSL_RW
+
+#define WCMP_HAHS_SP
+#define ROUTER_CTRL_WCMP_HAHS_SP_BOFFSET         5
+#define ROUTER_CTRL_WCMP_HAHS_SP_BLEN            1
+#define ROUTER_CTRL_WCMP_HAHS_SP_FLAG            HSL_RW
+
+#define WCMP_HAHS_SIP
+#define ROUTER_CTRL_WCMP_HAHS_SIP_BOFFSET        4
+#define ROUTER_CTRL_WCMP_HAHS_SIP_BLEN           1
+#define ROUTER_CTRL_WCMP_HAHS_SIP_FLAG           HSL_RW
+
+#define ARP_AGE_MODE
+#define ROUTER_CTRL_ARP_AGE_MODE_BOFFSET         1
+#define ROUTER_CTRL_ARP_AGE_MODE_BLEN            1
+#define ROUTER_CTRL_ARP_AGE_MODE_FLAG            HSL_RW
+
+#define ROUTER_EN
+#define ROUTER_CTRL_ROUTER_EN_BOFFSET            0
+#define ROUTER_CTRL_ROUTER_EN_BLEN               1
+#define ROUTER_CTRL_ROUTER_EN_FLAG               HSL_RW
+
+
+
+
+#define ROUTER_PTCTRL0
+#define ROUTER_PTCTRL0_OFFSET                       0x0e04
+#define ROUTER_PTCTRL0_E_LENGTH                     4
+#define ROUTER_PTCTRL0_E_OFFSET                     0x0
+#define ROUTER_PTCTRL0_NR_E                         1
+
+
+
+
+#define ROUTER_PTCTRL1
+#define ROUTER_PTCTRL1_OFFSET                       0x0e08
+#define ROUTER_PTCTRL1_E_LENGTH                     4
+#define ROUTER_PTCTRL1_E_OFFSET                     0x0
+#define ROUTER_PTCTRL1_NR_E                         1
+
+
+
+#define ROUTER_PTCTRL2
+#define ROUTER_PTCTRL2_OFFSET                       0x0e0c
+#define ROUTER_PTCTRL2_E_LENGTH                     4
+#define ROUTER_PTCTRL2_E_OFFSET                     0x0
+#define ROUTER_PTCTRL2_NR_E                         1
+
+#define ARP_PT_UP
+#define ROUTER_PTCTRL2_ARP_PT_UP_BOFFSET               16
+#define ROUTER_PTCTRL2_ARP_PT_UP_BLEN                  7
+#define ROUTER_PTCTRL2_ARP_PT_UP_FLAG                  HSL_RW
+
+#define ARP_LEARN_ACK
+#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET               8
+#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BLEN                  7
+#define ROUTER_PTCTRL2_ARP_LEARN_ACK_FLAG                  HSL_RW
+
+#define ARP_LEARN_REQ
+#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BOFFSET               0
+#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BLEN                  7
+#define ROUTER_PTCTRL2_ARP_LEARN_REQ_FLAG                  HSL_RW
+
+
+
+
+#define NAT_CTRL
+#define NAT_CTRL_OFFSET                       0x0e38
+#define NAT_CTRL_E_LENGTH                     4
+#define NAT_CTRL_E_OFFSET                     0x0
+#define NAT_CTRL_NR_E                         1
+
+#define NAT_HASH_MODE
+#define NAT_CTRL_NAT_HASH_MODE_BOFFSET        5
+#define NAT_CTRL_NAT_HASH_MODE_BLEN           2
+#define NAT_CTRL_NAT_HASH_MODE_FLAG           HSL_RW
+
+#define NAPT_OVERRIDE
+#define NAT_CTRL_NAPT_OVERRIDE_BOFFSET        4
+#define NAT_CTRL_NAPT_OVERRIDE_BLEN           1
+#define NAT_CTRL_NAPT_OVERRIDE_FLAG           HSL_RW
+
+#define NAPT_MODE
+#define NAT_CTRL_NAPT_MODE_BOFFSET            2
+#define NAT_CTRL_NAPT_MODE_BLEN               2
+#define NAT_CTRL_NAPT_MODE_FLAG               HSL_RW
+
+#define NAT_EN
+#define NAT_CTRL_NAT_EN_BOFFSET               1
+#define NAT_CTRL_NAT_EN_BLEN                  1
+#define NAT_CTRL_NAT_EN_FLAG                  HSL_RW
+
+#define NAPT_EN
+#define NAT_CTRL_NAPT_EN_BOFFSET              0
+#define NAT_CTRL_NAPT_EN_BLEN                 1
+#define NAT_CTRL_NAPT_EN_FLAG                 HSL_RW
+
+
+
+
+#define PRV_BASEADDR
+#define PRV_BASEADDR_OFFSET                       0x0e5c
+#define PRV_BASEADDR_E_LENGTH                     4
+#define PRV_BASEADDR_E_OFFSET                     0x0
+#define PRV_BASEADDR_NR_E                         1
+
+#define IP4_ADDR
+#define PRV_BASEADDR_IP4_ADDR_BOFFSET             0
+#define PRV_BASEADDR_IP4_ADDR_BLEN                20
+#define PRV_BASEADDR_IP4_ADDR_FLAG                HSL_RW
+
+
+
+
+#define PRVIP_CTL
+#define PRVIP_CTL_OFFSET                       0x0418
+#define PRVIP_CTL_E_LENGTH                     4
+#define PRVIP_CTL_E_OFFSET                     0x0
+#define PRVIP_CTL_NR_E                         1
+
+#define BASEADDR_SEL
+#define PRVIP_CTL_BASEADDR_SEL_BOFFSET         28
+#define PRVIP_CTL_BASEADDR_SEL_BLEN            1
+#define PRVIP_CTL_BASEADDR_SEL_FLAG            HSL_RW
+
+#define IP4_BASEADDR
+#define PRVIP_CTL_IP4_BASEADDR_BOFFSET         0
+#define PRVIP_CTL_IP4_BASEADDR_BLEN            20
+#define PRVIP_CTL_IP4_BASEADDR_FLAG            HSL_RW
+
+
+#define OFFLOAD_PRVIP_CTL
+#define OFFLOAD_PRVIP_CTL_OFFSET               0x0e5c
+#define OFFLOAD_PRVIP_CTL_E_LENGTH             4
+#define OFFLOAD_PRVIP_CTL_E_OFFSET             0x0
+#define OFFLOAD_PRVIP_CTL_NR_E                 1
+
+#define IP4_BASEADDR
+#define OFFLOAD_PRVIP_CTL_IP4_BASEADDR_BOFFSET 0
+#define OFFLOAD_PRVIP_CTL_IP4_BASEADDR_BLEN    20
+#define OFFLOAD_PRVIP_CTL_IP4_BASEADDR_FLAG    HSL_RW
+
+
+
+
+#define PUB_ADDR0
+#define PUB_ADDR0_OFFSET                       0x5aa00
+#define PUB_ADDR0_E_LENGTH                     4
+#define PUB_ADDR0_E_OFFSET                     0x0
+#define PUB_ADDR0_NR_E                         1
+
+#define IP4_ADDR
+#define PUB_ADDR0_IP4_ADDR_BOFFSET             0
+#define PUB_ADDR0_IP4_ADDR_BLEN                32
+#define PUB_ADDR0_IP4_ADDR_FLAG                HSL_RW
+
+
+#define PUB_ADDR1
+#define PUB_ADDR1_OFFSET                       0x5aa04
+#define PUB_ADDR1_E_LENGTH                     4
+#define PUB_ADDR1_E_OFFSET                     0x0
+#define PUB_ADDR1_NR_E                         1
+
+#define ADDR_VALID
+#define PUB_ADDR1_ADDR_VALID_BOFFSET           0
+#define PUB_ADDR1_ADDR_VALID_BLEN              1
+#define PUB_ADDR1_ADDR_VALID_FLAG              HSL_RW
+
+
+
+
+#define INTF_ADDR_ENTRY0
+#define INTF_ADDR_ENTRY0_OFFSET                     0x5aa00
+#define INTF_ADDR_ENTRY0_E_LENGTH                   4
+#define INTF_ADDR_ENTRY0_E_OFFSET                   0x0
+#define INTF_ADDR_ENTRY0_NR_E                       8
+
+#define MAC_ADDR2
+#define INTF_ADDR_ENTRY0_MAC_ADDR2_BOFFSET          24
+#define INTF_ADDR_ENTRY0_MAC_ADDR2_BLEN             8
+#define INTF_ADDR_ENTRY0_MAC_ADDR2_FLAG             HSL_RW
+
+#define MAC_ADDR3
+#define INTF_ADDR_ENTRY0_MAC_ADDR3_BOFFSET          16
+#define INTF_ADDR_ENTRY0_MAC_ADDR3_BLEN             8
+#define INTF_ADDR_ENTRY0_MAC_ADDR3_FLAG             HSL_RW
+
+#define MAC_ADDR4
+#define INTF_ADDR_ENTRY0_MAC_ADDR4_BOFFSET          8
+#define INTF_ADDR_ENTRY0_MAC_ADDR4_BLEN             8
+#define INTF_ADDR_ENTRY0_MAC_ADDR4_FLAG             HSL_RW
+
+#define MAC_ADDR5
+#define INTF_ADDR_ENTRY0_MAC_ADDR5_BOFFSET          0
+#define INTF_ADDR_ENTRY0_MAC_ADDR5_BLEN             8
+#define INTF_ADDR_ENTRY0_MAC_ADDR5_FLAG             HSL_RW
+
+
+#define INTF_ADDR_ENTRY1
+#define INTF_ADDR_ENTRY1_OFFSET                     0x5aa04
+#define INTF_ADDR_ENTRY1_E_LENGTH                   4
+#define INTF_ADDR_ENTRY1_E_OFFSET                   0x0
+#define INTF_ADDR_ENTRY1_NR_E                       8
+
+#define VID_HIGH0
+#define INTF_ADDR_ENTRY1_VID_HIGH0_BOFFSET          28
+#define INTF_ADDR_ENTRY1_VID_HIGH0_BLEN             4
+#define INTF_ADDR_ENTRY1_VID_HIGH0_FLAG             HSL_RW
+
+#define VID_LOW
+#define INTF_ADDR_ENTRY1_VID_LOW_BOFFSET            16
+#define INTF_ADDR_ENTRY1_VID_LOW_BLEN               12
+#define INTF_ADDR_ENTRY1_VID_LOW_FLAG               HSL_RW
+
+#define MAC_ADDR0
+#define INTF_ADDR_ENTRY1_MAC_ADDR0_BOFFSET          8
+#define INTF_ADDR_ENTRY1_MAC_ADDR0_BLEN             8
+#define INTF_ADDR_ENTRY1_MAC_ADDR0_FLAG             HSL_RW
+
+#define MAC_ADDR1
+#define INTF_ADDR_ENTRY1_MAC_ADDR1_BOFFSET          0
+#define INTF_ADDR_ENTRY1_MAC_ADDR1_BLEN             8
+#define INTF_ADDR_ENTRY1_MAC_ADDR1_FLAG             HSL_RW
+
+
+#define INTF_ADDR_ENTRY2
+#define INTF_ADDR_ENTRY2_OFFSET                     0x5aa08
+#define INTF_ADDR_ENTRY2_E_LENGTH                   4
+#define INTF_ADDR_ENTRY2_E_OFFSET                   0x0
+#define INTF_ADDR_ENTRY2_NR_E                       8
+
+#define IP6_ROUTE
+#define INTF_ADDR_ENTRY2_IP6_ROUTE_BOFFSET          9
+#define INTF_ADDR_ENTRY2_IP6_ROUTE_BLEN             1
+#define INTF_ADDR_ENTRY2_IP6_ROUTE_FLAG             HSL_RW
+
+#define IP4_ROUTE
+#define INTF_ADDR_ENTRY2_IP4_ROUTE_BOFFSET          8
+#define INTF_ADDR_ENTRY2_IP4_ROUTE_BLEN             1
+#define INTF_ADDR_ENTRY2_IP4_ROUTE_FLAG             HSL_RW
+
+#define VID_HIGH1
+#define INTF_ADDR_ENTRY2_VID_HIGH1_BOFFSET          0
+#define INTF_ADDR_ENTRY2_VID_HIGH1_BLEN             8
+#define INTF_ADDR_ENTRY2_VID_HIGH1_FLAG             HSL_RW
+
+
+
+
+    /* Port Shaper Register0 */
+#define EG_SHAPER0
+#define EG_SHAPER0_OFFSET         0x0890
+#define EG_SHAPER0_E_LENGTH       4
+#define EG_SHAPER0_E_OFFSET       0x0020
+#define EG_SHAPER0_NR_E           7
+
+#define EG_Q1_CIR
+#define EG_SHAPER0_EG_Q1_CIR_BOFFSET          16
+#define EG_SHAPER0_EG_Q1_CIR_BLEN             15
+#define EG_SHAPER0_EG_Q1_CIR_FLAG             HSL_RW
+
+#define EG_Q0_CIR
+#define EG_SHAPER0_EG_Q0_CIR_BOFFSET          0
+#define EG_SHAPER0_EG_Q0_CIR_BLEN             15
+#define EG_SHAPER0_EG_Q0_CIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register1 */
+#define EG_SHAPER1
+#define EG_SHAPER1_OFFSET         0x0894
+#define EG_SHAPER1_E_LENGTH       4
+#define EG_SHAPER1_E_OFFSET       0x0020
+#define EG_SHAPER1_NR_E           7
+
+#define EG_Q3_CIR
+#define EG_SHAPER1_EG_Q3_CIR_BOFFSET          16
+#define EG_SHAPER1_EG_Q3_CIR_BLEN             15
+#define EG_SHAPER1_EG_Q3_CIR_FLAG             HSL_RW
+
+#define EG_Q2_CIR
+#define EG_SHAPER1_EG_Q2_CIR_BOFFSET          0
+#define EG_SHAPER1_EG_Q2_CIR_BLEN             15
+#define EG_SHAPER1_EG_Q2_CIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register2 */
+#define EG_SHAPER2
+#define EG_SHAPER2_OFFSET         0x0898
+#define EG_SHAPER2_E_LENGTH       4
+#define EG_SHAPER2_E_OFFSET       0x0020
+#define EG_SHAPER2_NR_E           7
+
+#define EG_Q5_CIR
+#define EG_SHAPER2_EG_Q5_CIR_BOFFSET          16
+#define EG_SHAPER2_EG_Q5_CIR_BLEN             15
+#define EG_SHAPER2_EG_Q5_CIR_FLAG             HSL_RW
+
+#define EG_Q4_CIR
+#define EG_SHAPER2_EG_Q4_CIR_BOFFSET          0
+#define EG_SHAPER2_EG_Q4_CIR_BLEN             15
+#define EG_SHAPER2_EG_Q4_CIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register3 */
+#define EG_SHAPER3
+#define EG_SHAPER3_OFFSET         0x089c
+#define EG_SHAPER3_E_LENGTH       4
+#define EG_SHAPER3_E_OFFSET       0x0020
+#define EG_SHAPER3_NR_E           7
+
+#define EG_Q1_EIR
+#define EG_SHAPER3_EG_Q1_EIR_BOFFSET          16
+#define EG_SHAPER3_EG_Q1_EIR_BLEN             15
+#define EG_SHAPER3_EG_Q1_EIR_FLAG             HSL_RW
+
+#define EG_Q0_EIR
+#define EG_SHAPER3_EG_Q0_EIR_BOFFSET          0
+#define EG_SHAPER3_EG_Q0_EIR_BLEN             15
+#define EG_SHAPER3_EG_Q0_EIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register4 */
+#define EG_SHAPER4
+#define EG_SHAPER4_OFFSET         0x08a0
+#define EG_SHAPER4_E_LENGTH       4
+#define EG_SHAPER4_E_OFFSET       0x0020
+#define EG_SHAPER4_NR_E           7
+
+#define EG_Q3_EIR
+#define EG_SHAPER4_EG_Q3_EIR_BOFFSET          16
+#define EG_SHAPER4_EG_Q3_EIR_BLEN             15
+#define EG_SHAPER4_EG_Q3_EIR_FLAG             HSL_RW
+
+#define EG_Q2_EIR
+#define EG_SHAPER4_EG_Q2_EIR_BOFFSET          0
+#define EG_SHAPER4_EG_Q2_EIR_BLEN             15
+#define EG_SHAPER4_EG_Q2_EIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register5 */
+#define EG_SHAPER5
+#define EG_SHAPER5_OFFSET         0x08a4
+#define EG_SHAPER5_E_LENGTH       4
+#define EG_SHAPER5_E_OFFSET       0x0020
+#define EG_SHAPER5_NR_E           7
+
+#define EG_Q5_EIR
+#define EG_SHAPER5_EG_Q5_EIR_BOFFSET          16
+#define EG_SHAPER5_EG_Q5_EIR_BLEN             15
+#define EG_SHAPER5_EG_Q5_EIR_FLAG             HSL_RW
+
+#define EG_Q4_EIR
+#define EG_SHAPER5_EG_Q4_EIR_BOFFSET          0
+#define EG_SHAPER5_EG_Q4_EIR_BLEN             15
+#define EG_SHAPER5_EG_Q4_EIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register6 */
+#define EG_SHAPER6
+#define EG_SHAPER6_OFFSET         0x08a8
+#define EG_SHAPER6_E_LENGTH       4
+#define EG_SHAPER6_E_OFFSET       0x0020
+#define EG_SHAPER6_NR_E           7
+
+#define EG_Q3_CBS
+#define EG_SHAPER6_EG_Q3_CBS_BOFFSET          28
+#define EG_SHAPER6_EG_Q3_CBS_BLEN             3
+#define EG_SHAPER6_EG_Q3_CBS_FLAG             HSL_RW
+
+#define EG_Q3_EBS
+#define EG_SHAPER6_EG_Q3_EBS_BOFFSET          24
+#define EG_SHAPER6_EG_Q3_EBS_BLEN             3
+#define EG_SHAPER6_EG_Q3_EBS_FLAG             HSL_RW
+
+#define EG_Q2_CBS
+#define EG_SHAPER6_EG_Q2_CBS_BOFFSET          20
+#define EG_SHAPER6_EG_Q2_CBS_BLEN             3
+#define EG_SHAPER6_EG_Q2_CBS_FLAG             HSL_RW
+
+#define EG_Q2_EBS
+#define EG_SHAPER6_EG_Q2_EBS_BOFFSET          16
+#define EG_SHAPER6_EG_Q2_EBS_BLEN             3
+#define EG_SHAPER6_EG_Q2_EBS_FLAG             HSL_RW
+
+#define EG_Q1_CBS
+#define EG_SHAPER6_EG_Q1_CBS_BOFFSET          12
+#define EG_SHAPER6_EG_Q1_CBS_BLEN             3
+#define EG_SHAPER6_EG_Q1_CBS_FLAG             HSL_RW
+
+#define EG_Q1_EBS
+#define EG_SHAPER6_EG_Q1_EBS_BOFFSET          8
+#define EG_SHAPER6_EG_Q1_EBS_BLEN             3
+#define EG_SHAPER6_EG_Q1_EBS_FLAG             HSL_RW
+
+#define EG_Q0_CBS
+#define EG_SHAPER6_EG_Q0_CBS_BOFFSET          4
+#define EG_SHAPER6_EG_Q0_CBS_BLEN             3
+#define EG_SHAPER6_EG_Q0_CBS_FLAG             HSL_RW
+
+#define EG_Q0_EBS
+#define EG_SHAPER6_EG_Q0_EBS_BOFFSET          0
+#define EG_SHAPER6_EG_Q0_EBS_BLEN             3
+#define EG_SHAPER6_EG_Q0_EBS_FLAG             HSL_RW
+
+
+    /* Port Shaper Register7 */
+#define EG_SHAPER7
+#define EG_SHAPER7_OFFSET         0x08ac
+#define EG_SHAPER7_E_LENGTH       4
+#define EG_SHAPER7_E_OFFSET       0x0020
+#define EG_SHAPER7_NR_E           7
+
+#define EG_Q5_CBS
+#define EG_SHAPER7_EG_Q5_CBS_BOFFSET          28
+#define EG_SHAPER7_EG_Q5_CBS_BLEN             3
+#define EG_SHAPER7_EG_Q5_CBS_FLAG             HSL_RW
+
+#define EG_Q5_EBS
+#define EG_SHAPER7_EG_Q5_EBS_BOFFSET          24
+#define EG_SHAPER7_EG_Q5_EBS_BLEN             3
+#define EG_SHAPER7_EG_Q5_EBS_FLAG             HSL_RW
+
+#define EG_Q4_CBS
+#define EG_SHAPER7_EG_Q4_CBS_BOFFSET          20
+#define EG_SHAPER7_EG_Q4_CBS_BLEN             3
+#define EG_SHAPER7_EG_Q4_CBS_FLAG             HSL_RW
+
+#define EG_Q4_EBS
+#define EG_SHAPER7_EG_Q4_EBS_BOFFSET          16
+#define EG_SHAPER7_EG_Q4_EBS_BLEN             3
+#define EG_SHAPER7_EG_Q4_EBS_FLAG             HSL_RW
+
+#define EG_Q5_UNIT
+#define EG_SHAPER7_EG_Q5_UNIT_BOFFSET          13
+#define EG_SHAPER7_EG_Q5_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q5_UNIT_FLAG             HSL_RW
+
+#define EG_Q4_UNIT
+#define EG_SHAPER7_EG_Q4_UNIT_BOFFSET          12
+#define EG_SHAPER7_EG_Q4_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q4_UNIT_FLAG             HSL_RW
+
+#define EG_Q3_UNIT
+#define EG_SHAPER7_EG_Q3_UNIT_BOFFSET          11
+#define EG_SHAPER7_EG_Q3_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q3_UNIT_FLAG             HSL_RW
+
+#define EG_Q2_UNIT
+#define EG_SHAPER7_EG_Q2_UNIT_BOFFSET          10
+#define EG_SHAPER7_EG_Q2_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q2_UNIT_FLAG             HSL_RW
+
+#define EG_Q1_UNIT
+#define EG_SHAPER7_EG_Q1_UNIT_BOFFSET          9
+#define EG_SHAPER7_EG_Q1_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q1_UNIT_FLAG             HSL_RW
+
+#define EG_Q0_UNIT
+#define EG_SHAPER7_EG_Q0_UNIT_BOFFSET          8
+#define EG_SHAPER7_EG_Q0_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q0_UNIT_FLAG             HSL_RW
+
+#define EG_PT
+#define EG_SHAPER7_EG_PT_BOFFSET          3
+#define EG_SHAPER7_EG_PT_BLEN             1
+#define EG_SHAPER7_EG_PT_FLAG             HSL_RW
+
+#define EG_TS
+#define EG_SHAPER7_EG_TS_BOFFSET          0
+#define EG_SHAPER7_EG_TS_BLEN             3
+#define EG_SHAPER7_EG_TS_FLAG             HSL_RW
+
+
+
+    /* ACL Policer Register0 */
+#define ACL_POLICER0
+#define ACL_POLICER0_OFFSET         0x0a00
+#define ACL_POLICER0_E_LENGTH       4
+#define ACL_POLICER0_E_OFFSET       0x0008
+#define ACL_POLICER0_NR_E           32
+
+#define ACL_CBS
+#define ACL_POLICER0_ACL_CBS_BOFFSET          15
+#define ACL_POLICER0_ACL_CBS_BLEN             3
+#define ACL_POLICER0_ACL_CBS_FLAG             HSL_RW
+
+#define ACL_CIR
+#define ACL_POLICER0_ACL_CIR_BOFFSET          0
+#define ACL_POLICER0_ACL_CIR_BLEN             15
+#define ACL_POLICER0_ACL_CIR_FLAG             HSL_RW
+
+
+    /* ACL Policer Register1 */
+#define ACL_POLICER1
+#define ACL_POLICER1_OFFSET         0x0a04
+#define ACL_POLICER1_E_LENGTH       4
+#define ACL_POLICER1_E_OFFSET       0x0008
+#define ACL_POLICER1_NR_E           32
+
+#define ACL_BORROW
+#define ACL_POLICER1_ACL_BORROW_BOFFSET          23
+#define ACL_POLICER1_ACL_BORROW_BLEN             1
+#define ACL_POLICER1_ACL_BORROW_FLAG             HSL_RW
+
+#define ACL_UNIT
+#define ACL_POLICER1_ACL_UNIT_BOFFSET          22
+#define ACL_POLICER1_ACL_UNIT_BLEN             1
+#define ACL_POLICER1_ACL_UNIT_FLAG             HSL_RW
+
+#define ACL_CF
+#define ACL_POLICER1_ACL_CF_BOFFSET          21
+#define ACL_POLICER1_ACL_CF_BLEN             1
+#define ACL_POLICER1_ACL_CF_FLAG             HSL_RW
+
+#define ACL_CM
+#define ACL_POLICER1_ACL_CM_BOFFSET          20
+#define ACL_POLICER1_ACL_CM_BLEN             1
+#define ACL_POLICER1_ACL_CM_FLAG             HSL_RW
+
+#define ACL_TS
+#define ACL_POLICER1_ACL_TS_BOFFSET          18
+#define ACL_POLICER1_ACL_TS_BLEN             2
+#define ACL_POLICER1_ACL_TS_FLAG             HSL_RW
+
+#define ACL_EBS
+#define ACL_POLICER1_ACL_EBS_BOFFSET          15
+#define ACL_POLICER1_ACL_EBS_BLEN             3
+#define ACL_POLICER1_ACL_EBS_FLAG             HSL_RW
+
+#define ACL_EIR
+#define ACL_POLICER1_ACL_EIR_BOFFSET          0
+#define ACL_POLICER1_ACL_EIR_BLEN             15
+#define ACL_POLICER1_ACL_EIR_FLAG             HSL_RW
+
+
+    /* ACL Counter Register0 */
+#define ACL_COUNTER0
+#define ACL_COUNTER0_OFFSET         0x1c000
+#define ACL_COUNTER0_E_LENGTH       4
+#define ACL_COUNTER0_E_OFFSET       0x0008
+#define ACL_COUNTER0_NR_E           32
+
+    /* ACL Counter Register1 */
+#define ACL_COUNTER1
+#define ACL_COUNTER1_OFFSET         0x1c004
+#define ACL_COUNTER1_E_LENGTH       4
+#define ACL_COUNTER1_E_OFFSET       0x0008
+#define ACL_COUNTER1_NR_E           32
+
+
+
+
+    /* INGRESS Policer Register0 */
+#define INGRESS_POLICER0
+#define INGRESS_POLICER0_OFFSET         0x0b00
+#define INGRESS_POLICER0_E_LENGTH       4
+#define INGRESS_POLICER0_E_OFFSET       0x0010
+#define INGRESS_POLICER0_NR_E           7
+
+#define ADD_RATE_BYTE
+#define INGRESS_POLICER0_ADD_RATE_BYTE_BOFFSET 24
+#define INGRESS_POLICER0_ADD_RATE_BYTE_BLEN 8
+#define INGRESS_POLICER0_ADD_RATE_BYTE_FLAG HSL_RW
+
+#define C_ING_TS
+#define INGRESS_POLICER0_C_ING_TS_BOFFSET          22
+#define INGRESS_POLICER0_C_ING_TS_BLEN             2
+#define INGRESS_POLICER0_C_ING_TS_FLAG             HSL_RW
+
+#define RATE_MODE
+#define INGRESS_POLICER0_RATE_MODE_BOFFSET          20
+#define INGRESS_POLICER0_RATE_MODE_BLEN             1
+#define INGRESS_POLICER0_RATE_MODE_FLAG             HSL_RW
+
+#define INGRESS_CBS
+#define INGRESS_POLICER0_INGRESS_CBS_BOFFSET          15
+#define INGRESS_POLICER0_INGRESS_CBS_BLEN             3
+#define INGRESS_POLICER0_INGRESS_CBS_FLAG             HSL_RW
+
+#define INGRESS_CIR
+#define INGRESS_POLICER0_INGRESS_CIR_BOFFSET          0
+#define INGRESS_POLICER0_INGRESS_CIR_BLEN             15
+#define INGRESS_POLICER0_INGRESS_CIR_FLAG             HSL_RW
+
+
+    /* INGRESS Policer Register1 */
+#define INGRESS_POLICER1
+#define INGRESS_POLICER1_OFFSET         0x0b04
+#define INGRESS_POLICER1_E_LENGTH       4
+#define INGRESS_POLICER1_E_OFFSET       0x0010
+#define INGRESS_POLICER1_NR_E           7
+
+#define INGRESS_BORROW
+#define INGRESS_POLICER1_INGRESS_BORROW_BOFFSET          23
+#define INGRESS_POLICER1_INGRESS_BORROW_BLEN             1
+#define INGRESS_POLICER1_INGRESS_BORROW_FLAG             HSL_RW
+
+#define INGRESS_UNIT
+#define INGRESS_POLICER1_INGRESS_UNIT_BOFFSET          22
+#define INGRESS_POLICER1_INGRESS_UNIT_BLEN             1
+#define INGRESS_POLICER1_INGRESS_UNIT_FLAG             HSL_RW
+
+#define INGRESS_CF
+#define INGRESS_POLICER1_INGRESS_CF_BOFFSET          21
+#define INGRESS_POLICER1_INGRESS_CF_BLEN             1
+#define INGRESS_POLICER1_INGRESS_CF_FLAG             HSL_RW
+
+#define INGRESS_CM
+#define INGRESS_POLICER1_INGRESS_CM_BOFFSET          20
+#define INGRESS_POLICER1_INGRESS_CM_BLEN             1
+#define INGRESS_POLICER1_INGRESS_CM_FLAG             HSL_RW
+
+#define E_ING_TS
+#define INGRESS_POLICER1_E_ING_TS_BOFFSET          18
+#define INGRESS_POLICER1_E_ING_TS_BLEN             2
+#define INGRESS_POLICER1_E_ING_TS_FLAG             HSL_RW
+
+#define INGRESS_EBS
+#define INGRESS_POLICER1_INGRESS_EBS_BOFFSET          15
+#define INGRESS_POLICER1_INGRESS_EBS_BLEN             3
+#define INGRESS_POLICER1_INGRESS_EBS_FLAG             HSL_RW
+
+#define INGRESS_EIR
+#define INGRESS_POLICER1_INGRESS_EIR_BOFFSET          0
+#define INGRESS_POLICER1_INGRESS_EIR_BLEN             15
+#define INGRESS_POLICER1_INGRESS_EIR_FLAG             HSL_RW
+
+
+    /* INGRESS Policer Register2 */
+#define INGRESS_POLICER2
+#define INGRESS_POLICER2_OFFSET                 0x0b08
+#define INGRESS_POLICER2_E_LENGTH               4
+#define INGRESS_POLICER2_E_OFFSET               0x0010
+#define INGRESS_POLICER2_NR_E                   7
+
+#define C_MUL
+#define INGRESS_POLICER2_C_MUL_BOFFSET          15
+#define INGRESS_POLICER2_C_MUL_BLEN             1
+#define INGRESS_POLICER2_C_UNK_MUL_FLAG         HSL_RW
+
+#define C_UNI
+#define INGRESS_POLICER2_C_UNI_BOFFSET          14
+#define INGRESS_POLICER2_C_UNI_BLEN             1
+#define INGRESS_POLICER2_C_UNI_FLAG             HSL_RW
+
+#define C_UNK_MUL
+#define INGRESS_POLICER2_C_UNK_MUL_BOFFSET      13
+#define INGRESS_POLICER2_C_UNK_MUL_BLEN         1
+#define INGRESS_POLICER2_C_UNK_MUL_FLAG         HSL_RW
+
+#define C_UNK_UNI
+#define INGRESS_POLICER2_C_UNK_UNI_BOFFSET      12
+#define INGRESS_POLICER2_C_UNK_UNI_BLEN         1
+#define INGRESS_POLICER2_C_UNK_UNI_FLAG         HSL_RW
+
+#define C_BROAD
+#define INGRESS_POLICER2_C_BROAD_BOFFSET        11
+#define INGRESS_POLICER2_C_BROAD_BLEN           1
+#define INGRESS_POLICER2_C_BROAD_FLAG           HSL_RW
+
+#define C_MANAGE
+#define INGRESS_POLICER2_C_MANAGC_BOFFSET       10
+#define INGRESS_POLICER2_C_MANAGC_BLEN          1
+#define INGRESS_POLICER2_C_MANAGC_FLAG          HSL_RW
+
+#define C_TCP
+#define INGRESS_POLICER2_C_TCP_BOFFSET          9
+#define INGRESS_POLICER2_C_TCP_BLEN             1
+#define INGRESS_POLICER2_C_TCP_FLAG             HSL_RW
+
+#define C_MIRR
+#define INGRESS_POLICER2_C_MIRR_BOFFSET         8
+#define INGRESS_POLICER2_C_MIRR_BLEN            1
+#define INGRESS_POLICER2_C_MIRR_FLAG            HSL_RW
+
+#define E_MUL
+#define INGRESS_POLICER2_E_MUL_BOFFSET          7
+#define INGRESS_POLICER2_E_MUL_BLEN             1
+#define INGRESS_POLICER2_E_UNK_MUL_FLAG         HSL_RW
+
+#define E_UNI
+#define INGRESS_POLICER2_E_UNI_BOFFSET          6
+#define INGRESS_POLICER2_E_UNI_BLEN             1
+#define INGRESS_POLICER2_E_UNI_FLAG             HSL_RW
+
+#define E_UNK_MUL
+#define INGRESS_POLICER2_E_UNK_MUL_BOFFSET      5
+#define INGRESS_POLICER2_E_UNK_MUL_BLEN         1
+#define INGRESS_POLICER2_E_UNK_MUL_FLAG         HSL_RW
+
+#define E_UNK_UNI
+#define INGRESS_POLICER2_E_UNK_UNI_BOFFSET      4
+#define INGRESS_POLICER2_E_UNK_UNI_BLEN         1
+#define INGRESS_POLICER2_E_UNK_UNI_FLAG         HSL_RW
+
+#define E_BROAD
+#define INGRESS_POLICER2_E_BROAD_BOFFSET        3
+#define INGRESS_POLICER2_E_BROAD_BLEN           1
+#define INGRESS_POLICER2_E_BROAD_FLAG           HSL_RW
+
+#define E_MANAGE
+#define INGRESS_POLICER2_E_MANAGE_BOFFSET       2
+#define INGRESS_POLICER2_E_MANAGE_BLEN          1
+#define INGRESS_POLICER2_E_MANAGE_FLAG          HSL_RW
+
+#define E_TCP
+#define INGRESS_POLICER2_E_TCP_BOFFSET          1
+#define INGRESS_POLICER2_E_TCP_BLEN             1
+#define INGRESS_POLICER2_E_TCP_FLAG             HSL_RW
+
+#define E_MIRR
+#define INGRESS_POLICER2_E_MIRR_BOFFSET         0
+#define INGRESS_POLICER2_E_MIRR_BLEN            1
+#define INGRESS_POLICER2_E_MIRR_FLAG            HSL_RW
+
+
+
+
+    /* Port Rate Limit2 Register */
+#define WRR_CTRL
+#define WRR_CTRL_OFFSET                         0x0830
+#define WRR_CTRL_E_LENGTH                       4
+#define WRR_CTRL_E_OFFSET                       0x0004
+#define WRR_CTRL_NR_E                           7
+
+#define SCH_MODE
+#define WRR_CTRL_SCH_MODE_BOFFSET               30
+#define WRR_CTRL_SCH_MODE_BLEN                  2
+#define WRR_CTRL_SCH_MODE_FLAG                  HSL_RW
+
+#define Q5_W
+#define WRR_CTRL_Q5_W_BOFFSET                   25
+#define WRR_CTRL_Q5_W_BLEN                      5
+#define WRR_CTRL_Q5_W_FLAG                      HSL_RW
+
+#define Q4_W
+#define WRR_CTRL_Q4_W_BOFFSET                   20
+#define WRR_CTRL_Q4_W_BLEN                      5
+#define WRR_CTRL_Q4_W_FLAG                      HSL_RW
+
+#define Q3_W
+#define WRR_CTRL_Q3_W_BOFFSET                   15
+#define WRR_CTRL_Q3_W_BLEN                      5
+#define WRR_CTRL_Q3_W_FLAG                      HSL_RW
+
+#define Q2_W
+#define WRR_CTRL_Q2_W_BOFFSET                   10
+#define WRR_CTRL_Q2_W_BLEN                      5
+#define WRR_CTRL_Q2_W_FLAG                      HSL_RW
+
+#define Q1_W
+#define WRR_CTRL_Q1_W_BOFFSET                   5
+#define WRR_CTRL_Q1_W_BLEN                      5
+#define WRR_CTRL_Q1_W_FLAG                      HSL_RW
+
+#define Q0_W
+#define WRR_CTRL_Q0_W_BOFFSET                   0
+#define WRR_CTRL_Q0_W_BLEN                      5
+#define WRR_CTRL_Q0_W_FLAG                      HSL_RW
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_REG_H_ */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_reg_access.h b/qca-ssdk/include/hsl/isis/isis_reg_access.h
new file mode 100755
index 0000000..22fc6ca
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_reg_access.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _ISIS_REG_ACCESS_H_
+#define _ISIS_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "sw.h"
+
+#define ISIS_HEADER_CMD_LEN 8
+#define ISIS_HEADER_DATA_LEN 4
+#define ISIS_HEADER_LEN   4
+#define ISIS_HEADER_MAX_DATA_LEN 16
+#define VID_LEN   2
+#define ATHRS_HEADER_4BYTE_VAL 0xaaaa
+
+    typedef enum {
+        NORMAL_PACKET,
+        RESERVED0,
+        MIB_1ST,
+        RESERVED1,
+        RESERVED2,
+        READ_WRITE_REG,
+        READ_WRITE_REG_ACK,
+        RESERVED3
+    }
+    ATHRS_HEADER_TYPE;
+
+    typedef struct
+    {
+        a_uint8_t    version;
+        a_uint8_t    priority;
+        a_uint8_t    type ;
+        a_uint8_t    broadcast;
+        a_uint8_t    from_cpu;
+        a_uint8_t    port_num;
+    } athrs_header_t;
+
+    typedef struct
+    {
+        a_uint32_t    reg_addr;
+        a_uint8_t    cmd_len;
+        a_uint8_t    cmd;
+        a_uint16_t    check_code;
+        a_uint32_t    seq_num;
+    } athrs_header_regcmd_t;
+
+    typedef struct
+    {
+        a_uint8_t data[ISIS_HEADER_MAX_DATA_LEN];
+        a_uint8_t len;
+        a_uint16_t athrs_4byte_value;
+        volatile a_uint32_t seq;
+    } athrs_cmd_resp_t;
+
+    sw_error_t
+    isis_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+                 a_uint32_t reg, a_uint16_t * value);
+
+    sw_error_t
+    isis_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+                 a_uint32_t reg, a_uint16_t value);
+
+    sw_error_t
+    isis_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                 a_uint32_t value_len);
+
+    sw_error_t
+    isis_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                 a_uint32_t value_len);
+
+    sw_error_t
+    isis_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                       a_uint32_t bit_offset, a_uint32_t field_len,
+                       a_uint8_t value[], a_uint32_t value_len);
+
+    sw_error_t
+    isis_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                       a_uint32_t bit_offset, a_uint32_t field_len,
+                       const a_uint8_t value[], a_uint32_t value_len);
+
+	sw_error_t
+	isis_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump);
+
+	sw_error_t
+	isis_debug_regsiter_dump(a_uint32_t dev_id, fal_debug_reg_dump_t * dbg_reg_dump);
+
+
+    sw_error_t
+    isis_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode);
+
+    sw_error_t
+    isis_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode);
+
+    int
+    isis_reg_config_header (a_uint8_t *header,  a_uint8_t wr_flag,
+                            a_uint32_t reg_addr, a_uint8_t cmd_len,
+                            a_uint8_t *val, a_uint32_t seq_num);
+
+    sw_error_t isis_reg_parser_header_skb(a_uint8_t *header_buf, athrs_cmd_resp_t *cmd_resp);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISIS_REG_ACCESS_H_ */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_sec.h b/qca-ssdk/include/hsl/isis/isis_sec.h
new file mode 100755
index 0000000..c671d41
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_sec.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_SEC_H_
+#define _ISIS_SEC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_sec.h"
+
+    sw_error_t isis_sec_init(a_uint32_t dev_id);
+
+#ifdef IN_SEC
+#define ISIS_SEC_INIT(rv, dev_id) \
+    { \
+        rv = isis_sec_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_SEC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isis_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item,
+                           void *value);
+
+    HSL_LOCAL sw_error_t
+    isis_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item,
+                           void *value);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_SEC_H_ */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_stp.h b/qca-ssdk/include/hsl/isis/isis_stp.h
new file mode 100755
index 0000000..407017d
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_stp.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_STP_H_
+#define _ISIS_STP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_stp.h"
+
+    sw_error_t isis_stp_init(a_uint32_t dev_id);
+
+#ifdef IN_STP
+#define ISIS_STP_INIT(rv, dev_id) \
+    { \
+        rv = isis_stp_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_STP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isis_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                            fal_port_t port_id, fal_stp_state_t state);
+
+
+    HSL_LOCAL sw_error_t
+    isis_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                            fal_port_t port_id, fal_stp_state_t * state);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_STP_H_ */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_trunk.h b/qca-ssdk/include/hsl/isis/isis_trunk.h
new file mode 100755
index 0000000..66c602c
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_trunk.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_TRUNK_H_
+#define _ISIS_TRUNK_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_trunk.h"
+
+    sw_error_t isis_trunk_init(a_uint32_t dev_id);
+
+#ifdef IN_TRUNK
+#define ISIS_TRUNK_INIT(rv, dev_id) \
+    { \
+        rv = isis_trunk_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_TRUNK_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isis_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+                         a_bool_t enable, fal_pbmp_t member);
+
+    HSL_LOCAL sw_error_t
+    isis_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+                         a_bool_t * enable, fal_pbmp_t * member);
+
+    HSL_LOCAL sw_error_t
+    isis_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+    HSL_LOCAL sw_error_t
+    isis_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+    HSL_LOCAL sw_error_t
+    isis_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+    HSL_LOCAL sw_error_t
+    isis_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+    HSL_LOCAL sw_error_t
+    isis_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header,
+                             a_uint32_t len, fal_pbmp_t dp_member);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISIS_TRUNK_H_ */
+
diff --git a/qca-ssdk/include/hsl/isis/isis_vlan.h b/qca-ssdk/include/hsl/isis/isis_vlan.h
new file mode 100755
index 0000000..245d595
--- /dev/null
+++ b/qca-ssdk/include/hsl/isis/isis_vlan.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISIS_VLAN_H_
+#define _ISIS_VLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_vlan.h"
+
+    sw_error_t
+    isis_vlan_init(a_uint32_t dev_id);
+
+#ifdef IN_VLAN
+#define ISIS_VLAN_INIT(rv, dev_id) \
+    { \
+        rv = isis_vlan_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISIS_VLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isis_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry);
+
+
+    HSL_LOCAL sw_error_t
+    isis_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+    HSL_LOCAL sw_error_t
+    isis_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+    HSL_LOCAL sw_error_t
+    isis_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+    HSL_LOCAL sw_error_t
+    isis_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+    HSL_LOCAL sw_error_t
+    isis_vlan_flush(a_uint32_t dev_id);
+
+
+    HSL_LOCAL sw_error_t
+    isis_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid);
+
+
+    HSL_LOCAL sw_error_t
+    isis_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid);
+
+
+    HSL_LOCAL sw_error_t
+    isis_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+                         fal_port_t port_id, fal_pt_1q_egmode_t port_info);
+
+
+    HSL_LOCAL sw_error_t
+    isis_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    isis_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+                                 a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isis_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+                                 a_bool_t * enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISIS_VLAN_H_ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_acl.h b/qca-ssdk/include/hsl/isisc/isisc_acl.h
new file mode 100755
index 0000000..704b047
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_acl.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_acl ISISC_ACL
+ * @{
+ */
+#ifndef _ISISC_ACL_H_
+#define _ISISC_ACL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_acl.h"
+
+    sw_error_t isisc_acl_init(a_uint32_t dev_id);
+
+    sw_error_t isisc_acl_reset(a_uint32_t dev_id);
+
+    sw_error_t isisc_acl_cleanup(a_uint32_t dev_id);
+
+
+#ifdef IN_ACL
+#define ISISC_ACL_INIT(rv, dev_id) \
+    { \
+        rv = isisc_acl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define ISISC_ACL_RESET(rv, dev_id) \
+    { \
+        rv = isisc_acl_reset(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#define ISISC_ACL_CLEANUP(rv, dev_id) \
+    { \
+        rv = isisc_acl_cleanup(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_ACL_INIT(rv, dev_id)
+#define ISISC_ACL_RESET(rv, dev_id)
+#define ISISC_ACL_CLEANUP(rv, dev_id)
+#endif
+
+    sw_error_t
+    isisc_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+                        a_uint32_t list_pri);
+
+    sw_error_t
+    isisc_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+                      a_uint32_t rule_id, a_uint32_t rule_nr,
+                      fal_acl_rule_t * rule);
+
+    sw_error_t
+    isisc_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+                         a_uint32_t rule_id, a_uint32_t rule_nr);
+
+    sw_error_t
+    isisc_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+                        a_uint32_t rule_id, fal_acl_rule_t * rule);
+
+    a_uint32_t
+    isisc_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id);
+
+    sw_error_t
+    isisc_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act);
+
+    sw_error_t
+    isisc_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                       fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                       a_uint32_t obj_idx);
+
+    sw_error_t
+    isisc_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                         fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                         a_uint32_t obj_idx);
+
+    sw_error_t
+    isisc_acl_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isisc_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id);
+
+    HSL_LOCAL sw_error_t
+    isisc_acl_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_acl_list_dump(a_uint32_t dev_id);
+
+    HSL_LOCAL sw_error_t
+    isisc_acl_rule_dump(a_uint32_t dev_id);
+
+    HSL_LOCAL sw_error_t
+    isisc_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_acl_udf_type_t udf_type,
+                                  a_uint32_t offset, a_uint32_t length);
+
+    HSL_LOCAL sw_error_t
+    isisc_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_acl_udf_type_t udf_type,
+                                  a_uint32_t * offset, a_uint32_t * length);
+
+    HSL_LOCAL sw_error_t
+    isisc_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+                         a_uint32_t rule_id, a_uint32_t rule_nr);
+
+    HSL_LOCAL sw_error_t
+    isisc_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+                           a_uint32_t rule_id, a_uint32_t rule_nr);
+    HSL_LOCAL sw_error_t
+    isisc_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+                                     a_uint32_t rule_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
+                                     a_uint32_t rule_id, a_bool_t* enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_ACL_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/isisc/isisc_api.h b/qca-ssdk/include/hsl/isisc/isisc_api.h
new file mode 100755
index 0000000..4e9d753
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_api.h
@@ -0,0 +1,1093 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _ISISC_API_H_
+#define _ISISC_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#ifdef IN_PORTCONTROL
+#define PORTCONTROL_API \
+    SW_API_DEF(SW_API_PT_DUPLEX_GET, isisc_port_duplex_get), \
+    SW_API_DEF(SW_API_PT_DUPLEX_SET, isisc_port_duplex_set), \
+    SW_API_DEF(SW_API_PT_SPEED_GET, isisc_port_speed_get), \
+    SW_API_DEF(SW_API_PT_SPEED_SET, isisc_port_speed_set), \
+    SW_API_DEF(SW_API_PT_AN_GET, isisc_port_autoneg_status_get), \
+    SW_API_DEF(SW_API_PT_AN_ENABLE, isisc_port_autoneg_enable), \
+    SW_API_DEF(SW_API_PT_AN_RESTART, isisc_port_autoneg_restart), \
+    SW_API_DEF(SW_API_PT_AN_ADV_GET, isisc_port_autoneg_adv_get), \
+    SW_API_DEF(SW_API_PT_AN_ADV_SET, isisc_port_autoneg_adv_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_SET, isisc_port_flowctrl_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_GET, isisc_port_flowctrl_get), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, isisc_port_flowctrl_forcemode_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, isisc_port_flowctrl_forcemode_get), \
+    SW_API_DEF(SW_API_PT_POWERSAVE_SET, isisc_port_powersave_set), \
+    SW_API_DEF(SW_API_PT_POWERSAVE_GET, isisc_port_powersave_get), \
+    SW_API_DEF(SW_API_PT_HIBERNATE_SET, isisc_port_hibernate_set), \
+    SW_API_DEF(SW_API_PT_HIBERNATE_GET, isisc_port_hibernate_get), \
+    SW_API_DEF(SW_API_PT_CDT, isisc_port_cdt), \
+    SW_API_DEF(SW_API_PT_TXHDR_SET, isisc_port_txhdr_mode_set), \
+    SW_API_DEF(SW_API_PT_TXHDR_GET, isisc_port_txhdr_mode_get), \
+    SW_API_DEF(SW_API_PT_RXHDR_SET, isisc_port_rxhdr_mode_set), \
+    SW_API_DEF(SW_API_PT_RXHDR_GET, isisc_port_rxhdr_mode_get), \
+    SW_API_DEF(SW_API_HEADER_TYPE_SET, isisc_header_type_set),  \
+    SW_API_DEF(SW_API_HEADER_TYPE_GET, isisc_header_type_get), \
+    SW_API_DEF(SW_API_TXMAC_STATUS_SET, isisc_port_txmac_status_set), \
+    SW_API_DEF(SW_API_TXMAC_STATUS_GET, isisc_port_txmac_status_get), \
+    SW_API_DEF(SW_API_RXMAC_STATUS_SET, isisc_port_rxmac_status_set), \
+    SW_API_DEF(SW_API_RXMAC_STATUS_GET, isisc_port_rxmac_status_get), \
+    SW_API_DEF(SW_API_TXFC_STATUS_SET, isisc_port_txfc_status_set),   \
+    SW_API_DEF(SW_API_TXFC_STATUS_GET, isisc_port_txfc_status_get),   \
+    SW_API_DEF(SW_API_RXFC_STATUS_SET, isisc_port_rxfc_status_set),   \
+    SW_API_DEF(SW_API_RXFC_STATUS_GET, isisc_port_rxfc_status_get),   \
+    SW_API_DEF(SW_API_BP_STATUS_SET, isisc_port_bp_status_set),   \
+    SW_API_DEF(SW_API_BP_STATUS_GET, isisc_port_bp_status_get),   \
+    SW_API_DEF(SW_API_PT_LINK_MODE_SET, isisc_port_link_forcemode_set),   \
+    SW_API_DEF(SW_API_PT_LINK_MODE_GET, isisc_port_link_forcemode_get), \
+    SW_API_DEF(SW_API_PT_LINK_STATUS_GET, isisc_port_link_status_get), \
+    SW_API_DEF(SW_API_PT_MAC_LOOPBACK_SET, isisc_port_mac_loopback_set), \
+    SW_API_DEF(SW_API_PT_MAC_LOOPBACK_GET, isisc_port_mac_loopback_get), \
+    SW_API_DEF(SW_API_PT_8023AZ_SET, isisc_port_8023az_set), \
+    SW_API_DEF(SW_API_PT_8023AZ_GET, isisc_port_8023az_get),
+
+#define PORTCONTROL_API_PARAM \
+    SW_API_DESC(SW_API_PT_DUPLEX_GET) \
+    SW_API_DESC(SW_API_PT_DUPLEX_SET) \
+    SW_API_DESC(SW_API_PT_SPEED_GET)  \
+    SW_API_DESC(SW_API_PT_SPEED_SET)  \
+    SW_API_DESC(SW_API_PT_AN_GET)  \
+    SW_API_DESC(SW_API_PT_AN_ENABLE)   \
+    SW_API_DESC(SW_API_PT_AN_RESTART)  \
+    SW_API_DESC(SW_API_PT_AN_ADV_GET)  \
+    SW_API_DESC(SW_API_PT_AN_ADV_SET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_SET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_GET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \
+    SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
+    SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
+    SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
+    SW_API_DESC(SW_API_PT_HIBERNATE_GET) \
+    SW_API_DESC(SW_API_PT_CDT) \
+    SW_API_DESC(SW_API_PT_TXHDR_SET) \
+    SW_API_DESC(SW_API_PT_TXHDR_GET) \
+    SW_API_DESC(SW_API_PT_RXHDR_SET) \
+    SW_API_DESC(SW_API_PT_RXHDR_GET) \
+    SW_API_DESC(SW_API_HEADER_TYPE_SET) \
+    SW_API_DESC(SW_API_HEADER_TYPE_GET) \
+    SW_API_DESC(SW_API_TXMAC_STATUS_SET) \
+    SW_API_DESC(SW_API_TXMAC_STATUS_GET) \
+    SW_API_DESC(SW_API_RXMAC_STATUS_SET) \
+    SW_API_DESC(SW_API_RXMAC_STATUS_GET) \
+    SW_API_DESC(SW_API_TXFC_STATUS_SET) \
+    SW_API_DESC(SW_API_TXFC_STATUS_GET) \
+    SW_API_DESC(SW_API_RXFC_STATUS_SET) \
+    SW_API_DESC(SW_API_RXFC_STATUS_GET) \
+    SW_API_DESC(SW_API_BP_STATUS_SET) \
+    SW_API_DESC(SW_API_BP_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_LINK_MODE_SET) \
+    SW_API_DESC(SW_API_PT_LINK_MODE_GET) \
+    SW_API_DESC(SW_API_PT_LINK_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_MAC_LOOPBACK_SET) \
+    SW_API_DESC(SW_API_PT_MAC_LOOPBACK_GET) \
+    SW_API_DESC(SW_API_PT_8023AZ_SET) \
+    SW_API_DESC(SW_API_PT_8023AZ_GET)
+#else
+#define PORTCONTROL_API
+#define PORTCONTROL_API_PARAM
+#endif
+
+#ifdef IN_VLAN
+#define VLAN_API \
+    SW_API_DEF(SW_API_VLAN_ADD, isisc_vlan_create), \
+    SW_API_DEF(SW_API_VLAN_DEL, isisc_vlan_delete), \
+    SW_API_DEF(SW_API_VLAN_FIND, isisc_vlan_find), \
+    SW_API_DEF(SW_API_VLAN_NEXT, isisc_vlan_next), \
+    SW_API_DEF(SW_API_VLAN_APPEND, isisc_vlan_entry_append), \
+    SW_API_DEF(SW_API_VLAN_FLUSH, isisc_vlan_flush), \
+    SW_API_DEF(SW_API_VLAN_FID_SET, isisc_vlan_fid_set), \
+    SW_API_DEF(SW_API_VLAN_FID_GET, isisc_vlan_fid_get), \
+    SW_API_DEF(SW_API_VLAN_MEMBER_ADD, isisc_vlan_member_add), \
+    SW_API_DEF(SW_API_VLAN_MEMBER_DEL, isisc_vlan_member_del), \
+    SW_API_DEF(SW_API_VLAN_LEARN_STATE_SET, isisc_vlan_learning_state_set), \
+    SW_API_DEF(SW_API_VLAN_LEARN_STATE_GET, isisc_vlan_learning_state_get),
+
+#define VLAN_API_PARAM \
+    SW_API_DESC(SW_API_VLAN_ADD)     \
+    SW_API_DESC(SW_API_VLAN_DEL)     \
+    SW_API_DESC(SW_API_VLAN_FIND)    \
+    SW_API_DESC(SW_API_VLAN_NEXT)    \
+    SW_API_DESC(SW_API_VLAN_APPEND)  \
+    SW_API_DESC(SW_API_VLAN_FLUSH)   \
+    SW_API_DESC(SW_API_VLAN_FID_SET) \
+    SW_API_DESC(SW_API_VLAN_FID_GET) \
+    SW_API_DESC(SW_API_VLAN_MEMBER_ADD) \
+    SW_API_DESC(SW_API_VLAN_MEMBER_DEL) \
+    SW_API_DESC(SW_API_VLAN_LEARN_STATE_SET) \
+    SW_API_DESC(SW_API_VLAN_LEARN_STATE_GET)
+#else
+#define VLAN_API
+#define VLAN_API_PARAM
+#endif
+
+#ifdef IN_PORTVLAN
+#define PORTVLAN_API \
+    SW_API_DEF(SW_API_PT_ING_MODE_GET, isisc_port_1qmode_get), \
+    SW_API_DEF(SW_API_PT_ING_MODE_SET, isisc_port_1qmode_set), \
+    SW_API_DEF(SW_API_PT_EG_MODE_GET, isisc_port_egvlanmode_get), \
+    SW_API_DEF(SW_API_PT_EG_MODE_SET, isisc_port_egvlanmode_set), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, isisc_portvlan_member_add), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, isisc_portvlan_member_del), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, isisc_portvlan_member_update), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_GET, isisc_portvlan_member_get), \
+    SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, isisc_port_force_default_vid_set), \
+    SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, isisc_port_force_default_vid_get), \
+    SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, isisc_port_force_portvlan_set), \
+    SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, isisc_port_force_portvlan_get), \
+    SW_API_DEF(SW_API_NESTVLAN_TPID_SET, isisc_nestvlan_tpid_set), \
+    SW_API_DEF(SW_API_NESTVLAN_TPID_GET, isisc_nestvlan_tpid_get), \
+    SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, isisc_port_invlan_mode_set), \
+    SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, isisc_port_invlan_mode_get), \
+    SW_API_DEF(SW_API_PT_TLS_SET, isisc_port_tls_set), \
+    SW_API_DEF(SW_API_PT_TLS_GET, isisc_port_tls_get), \
+    SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, isisc_port_pri_propagation_set), \
+    SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, isisc_port_pri_propagation_get), \
+    SW_API_DEF(SW_API_PT_DEF_SVID_SET, isisc_port_default_svid_set), \
+    SW_API_DEF(SW_API_PT_DEF_SVID_GET, isisc_port_default_svid_get), \
+    SW_API_DEF(SW_API_PT_DEF_CVID_SET, isisc_port_default_cvid_set), \
+    SW_API_DEF(SW_API_PT_DEF_CVID_GET, isisc_port_default_cvid_get), \
+    SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_SET, isisc_port_vlan_propagation_set), \
+    SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_GET, isisc_port_vlan_propagation_get), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, isisc_port_vlan_trans_add), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_DEL, isisc_port_vlan_trans_del), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_GET, isisc_port_vlan_trans_get), \
+    SW_API_DEF(SW_API_QINQ_MODE_SET, isisc_qinq_mode_set), \
+    SW_API_DEF(SW_API_QINQ_MODE_GET, isisc_qinq_mode_get), \
+    SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, isisc_port_qinq_role_set), \
+    SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, isisc_port_qinq_role_get), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ITERATE, isisc_port_vlan_trans_iterate), \
+    SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_SET, isisc_port_mac_vlan_xlt_set), \
+    SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_GET, isisc_port_mac_vlan_xlt_get), \
+    SW_API_DEF(SW_API_NETISOLATE_SET, isisc_netisolate_set), \
+    SW_API_DEF(SW_API_NETISOLATE_GET, isisc_netisolate_get),\
+    SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_SET, isisc_eg_trans_filter_bypass_en_set), \
+    SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_GET, isisc_eg_trans_filter_bypass_en_get),
+
+
+#define PORTVLAN_API_PARAM \
+    SW_API_DESC(SW_API_PT_ING_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_ING_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_EG_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_EG_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE)  \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_GET)     \
+    SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET)    \
+    SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET)    \
+    SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET)   \
+    SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET)   \
+    SW_API_DESC(SW_API_NESTVLAN_TPID_SET)    \
+    SW_API_DESC(SW_API_NESTVLAN_TPID_GET)    \
+    SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET)    \
+    SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET)    \
+    SW_API_DESC(SW_API_PT_TLS_SET)    \
+    SW_API_DESC(SW_API_PT_TLS_GET)    \
+    SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET)    \
+    SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET)    \
+    SW_API_DESC(SW_API_PT_DEF_SVID_SET)    \
+    SW_API_DESC(SW_API_PT_DEF_SVID_GET)    \
+    SW_API_DESC(SW_API_PT_DEF_CVID_SET)    \
+    SW_API_DESC(SW_API_PT_DEF_CVID_GET)    \
+    SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_SET)    \
+    SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_GET)    \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD)  \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_DEL)  \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_GET)  \
+    SW_API_DESC(SW_API_QINQ_MODE_SET)      \
+    SW_API_DESC(SW_API_QINQ_MODE_GET)      \
+    SW_API_DESC(SW_API_PT_QINQ_ROLE_SET)   \
+    SW_API_DESC(SW_API_PT_QINQ_ROLE_GET)   \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ITERATE) \
+    SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_SET)   \
+    SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_GET)  \
+    SW_API_DESC(SW_API_NETISOLATE_SET)   \
+    SW_API_DESC(SW_API_NETISOLATE_GET)   \
+    SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_SET) \
+    SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_GET)
+
+#else
+#define PORTVLAN_API
+#define PORTVLAN_API_PARAM
+#endif
+
+#ifdef IN_FDB
+#define FDB_API \
+    SW_API_DEF(SW_API_FDB_ADD, isisc_fdb_add), \
+    SW_API_DEF(SW_API_FDB_DELALL, isisc_fdb_del_all), \
+    SW_API_DEF(SW_API_FDB_DELPORT,isisc_fdb_del_by_port), \
+    SW_API_DEF(SW_API_FDB_DELMAC, isisc_fdb_del_by_mac), \
+    SW_API_DEF(SW_API_FDB_FIND,   isisc_fdb_find), \
+    SW_API_DEF(SW_API_FDB_EXTEND_NEXT,    isisc_fdb_extend_next),  \
+    SW_API_DEF(SW_API_FDB_EXTEND_FIRST,   isisc_fdb_extend_first),  \
+    SW_API_DEF(SW_API_FDB_TRANSFER,       isisc_fdb_transfer),  \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_SET,   isisc_fdb_port_learn_set), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_GET,   isisc_fdb_port_learn_get), \
+    SW_API_DEF(SW_API_FDB_AGE_CTRL_SET,   isisc_fdb_age_ctrl_set), \
+    SW_API_DEF(SW_API_FDB_AGE_CTRL_GET,   isisc_fdb_age_ctrl_get), \
+    SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_SET, isisc_fdb_vlan_ivl_svl_set),\
+    SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_GET, isisc_fdb_vlan_ivl_svl_get),\
+    SW_API_DEF(SW_API_FDB_AGE_TIME_SET,   isisc_fdb_age_time_set), \
+    SW_API_DEF(SW_API_FDB_AGE_TIME_GET,   isisc_fdb_age_time_get), \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET,    isisc_port_fdb_learn_limit_set),  \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET,    isisc_port_fdb_learn_limit_get),  \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET,    isisc_port_fdb_learn_exceed_cmd_set),  \
+    SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET,    isisc_port_fdb_learn_exceed_cmd_get), \
+    SW_API_DEF(SW_API_FDB_LEARN_LIMIT_SET,    isisc_fdb_learn_limit_set),  \
+    SW_API_DEF(SW_API_FDB_LEARN_LIMIT_GET,    isisc_fdb_learn_limit_get),  \
+    SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET,    isisc_fdb_learn_exceed_cmd_set),  \
+    SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET,    isisc_fdb_learn_exceed_cmd_get),  \
+    SW_API_DEF(SW_API_FDB_RESV_ADD, isisc_fdb_resv_add), \
+    SW_API_DEF(SW_API_FDB_RESV_DEL, isisc_fdb_resv_del), \
+    SW_API_DEF(SW_API_FDB_RESV_FIND, isisc_fdb_resv_find), \
+    SW_API_DEF(SW_API_FDB_RESV_ITERATE, isisc_fdb_resv_iterate), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_SET,   isisc_fdb_port_learn_static_set), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_GET,   isisc_fdb_port_learn_static_get), \
+    SW_API_DEF(SW_API_FDB_PORT_ADD,   isisc_fdb_port_add), \
+    SW_API_DEF(SW_API_FDB_PORT_DEL,   isisc_fdb_port_del),
+
+#define FDB_API_PARAM \
+    SW_API_DESC(SW_API_FDB_ADD) \
+    SW_API_DESC(SW_API_FDB_DELALL)  \
+    SW_API_DESC(SW_API_FDB_DELPORT) \
+    SW_API_DESC(SW_API_FDB_DELMAC) \
+    SW_API_DESC(SW_API_FDB_FIND) \
+    SW_API_DESC(SW_API_FDB_EXTEND_NEXT)  \
+    SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \
+    SW_API_DESC(SW_API_FDB_TRANSFER) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \
+    SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \
+    SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \
+    SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_SET) \
+    SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_GET) \
+    SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \
+    SW_API_DESC(SW_API_FDB_AGE_TIME_GET) \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_SET)  \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_GET)  \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET)  \
+    SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_LIMIT_SET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_LIMIT_GET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_SET)  \
+    SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_GET)  \
+    SW_API_DESC(SW_API_FDB_RESV_ADD)  \
+    SW_API_DESC(SW_API_FDB_RESV_DEL)  \
+    SW_API_DESC(SW_API_FDB_RESV_FIND) \
+    SW_API_DESC(SW_API_FDB_RESV_ITERATE) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_SET) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_GET) \
+    SW_API_DESC(SW_API_FDB_PORT_ADD)  \
+    SW_API_DESC(SW_API_FDB_PORT_DEL)
+
+#else
+#define FDB_API
+#define FDB_API_PARAM
+#endif
+
+
+#ifdef IN_ACL
+#define ACL_API \
+    SW_API_DEF(SW_API_ACL_LIST_CREAT, isisc_acl_list_creat), \
+    SW_API_DEF(SW_API_ACL_LIST_DESTROY, isisc_acl_list_destroy), \
+    SW_API_DEF(SW_API_ACL_RULE_ADD, isisc_acl_rule_add), \
+    SW_API_DEF(SW_API_ACL_RULE_DELETE, isisc_acl_rule_delete), \
+    SW_API_DEF(SW_API_ACL_RULE_QUERY, isisc_acl_rule_query), \
+    SW_API_DEF(SW_API_ACL_LIST_BIND, isisc_acl_list_bind), \
+    SW_API_DEF(SW_API_ACL_LIST_UNBIND, isisc_acl_list_unbind), \
+    SW_API_DEF(SW_API_ACL_STATUS_SET, isisc_acl_status_set), \
+    SW_API_DEF(SW_API_ACL_STATUS_GET, isisc_acl_status_get), \
+    SW_API_DEF(SW_API_ACL_LIST_DUMP, isisc_acl_list_dump), \
+    SW_API_DEF(SW_API_ACL_RULE_DUMP, isisc_acl_rule_dump), \
+    SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, isisc_acl_port_udf_profile_set), \
+    SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, isisc_acl_port_udf_profile_get), \
+    SW_API_DEF(SW_API_ACL_RULE_ACTIVE, isisc_acl_rule_active), \
+    SW_API_DEF(SW_API_ACL_RULE_DEACTIVE, isisc_acl_rule_deactive),\
+    SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, isisc_acl_rule_src_filter_sts_set),\
+    SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, isisc_acl_rule_src_filter_sts_get), \
+    SW_API_DEF(SW_API_ACL_RULE_GET_OFFSET, isisc_acl_rule_get_offset),
+
+#define ACL_API_PARAM \
+    SW_API_DESC(SW_API_ACL_LIST_CREAT)   \
+    SW_API_DESC(SW_API_ACL_LIST_DESTROY) \
+    SW_API_DESC(SW_API_ACL_RULE_ADD)     \
+    SW_API_DESC(SW_API_ACL_RULE_DELETE)  \
+    SW_API_DESC(SW_API_ACL_RULE_QUERY)   \
+    SW_API_DESC(SW_API_ACL_LIST_BIND)    \
+    SW_API_DESC(SW_API_ACL_LIST_UNBIND)  \
+    SW_API_DESC(SW_API_ACL_STATUS_SET)   \
+    SW_API_DESC(SW_API_ACL_STATUS_GET)   \
+    SW_API_DESC(SW_API_ACL_LIST_DUMP)    \
+    SW_API_DESC(SW_API_ACL_RULE_DUMP)    \
+    SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_SET)    \
+    SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_GET)    \
+    SW_API_DESC(SW_API_ACL_RULE_ACTIVE)    \
+    SW_API_DESC(SW_API_ACL_RULE_DEACTIVE) \
+    SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_SET) \
+    SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_GET)
+#else
+#define ACL_API
+#define ACL_API_PARAM
+#endif
+
+
+#ifdef IN_QOS
+#define QOS_API \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, isisc_qos_queue_tx_buf_status_set), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, isisc_qos_queue_tx_buf_status_get), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, isisc_qos_queue_tx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, isisc_qos_queue_tx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, isisc_qos_port_tx_buf_status_set), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, isisc_qos_port_tx_buf_status_get), \
+    SW_API_DEF(SW_API_QOS_PT_RED_EN_SET, isisc_qos_port_red_en_set),\
+    SW_API_DEF(SW_API_QOS_PT_RED_EN_GET, isisc_qos_port_red_en_get),\
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, isisc_qos_port_tx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, isisc_qos_port_tx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, isisc_qos_port_rx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, isisc_qos_port_rx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_SET, isisc_qos_port_mode_set), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_GET, isisc_qos_port_mode_get), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, isisc_qos_port_mode_pri_set), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, isisc_qos_port_mode_pri_get), \
+    SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, isisc_qos_port_sch_mode_set), \
+    SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, isisc_qos_port_sch_mode_get), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_SET, isisc_qos_port_default_spri_set), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_GET, isisc_qos_port_default_spri_get), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_SET, isisc_qos_port_default_cpri_set), \
+    SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_GET, isisc_qos_port_default_cpri_get), \
+    SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, isisc_qos_port_force_spri_status_set), \
+    SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, isisc_qos_port_force_spri_status_get), \
+    SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, isisc_qos_port_force_cpri_status_set), \
+    SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, isisc_qos_port_force_cpri_status_get), \
+    SW_API_DEF(SW_API_QOS_QUEUE_REMARK_SET, isisc_qos_queue_remark_table_set), \
+    SW_API_DEF(SW_API_QOS_QUEUE_REMARK_GET, isisc_qos_queue_remark_table_get),
+
+
+#define QOS_API_PARAM \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \
+    SW_API_DESC(SW_API_QOS_PT_RED_EN_SET) \
+    SW_API_DESC(SW_API_QOS_PT_RED_EN_GET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_SET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_GET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET) \
+    SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_SET)  \
+    SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_GET)  \
+    SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_SET)  \
+    SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_GET)  \
+    SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_SET)  \
+    SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_GET)  \
+    SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_SET)  \
+    SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_GET)  \
+    SW_API_DESC(SW_API_QOS_QUEUE_REMARK_SET) \
+    SW_API_DESC(SW_API_QOS_QUEUE_REMARK_GET)
+#else
+#define QOS_API
+#define QOS_API_PARAM
+#endif
+
+
+#ifdef IN_IGMP
+#define IGMP_API \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, isisc_port_igmps_status_set), \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, isisc_port_igmps_status_get), \
+    SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, isisc_igmp_mld_cmd_set), \
+    SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, isisc_igmp_mld_cmd_get), \
+    SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, isisc_port_igmp_mld_join_set), \
+    SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, isisc_port_igmp_mld_join_get), \
+    SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, isisc_port_igmp_mld_leave_set), \
+    SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, isisc_port_igmp_mld_leave_get), \
+    SW_API_DEF(SW_API_IGMP_RP_SET, isisc_igmp_mld_rp_set), \
+    SW_API_DEF(SW_API_IGMP_RP_GET, isisc_igmp_mld_rp_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, isisc_igmp_mld_entry_creat_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, isisc_igmp_mld_entry_creat_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, isisc_igmp_mld_entry_static_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, isisc_igmp_mld_entry_static_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, isisc_igmp_mld_entry_leaky_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, isisc_igmp_mld_entry_leaky_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, isisc_igmp_mld_entry_v3_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, isisc_igmp_mld_entry_v3_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, isisc_igmp_mld_entry_queue_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, isisc_igmp_mld_entry_queue_get), \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET,    isisc_port_igmp_mld_learn_limit_set),  \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET,    isisc_port_igmp_mld_learn_limit_get),  \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET,    isisc_port_igmp_mld_learn_exceed_cmd_set),  \
+    SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET,    isisc_port_igmp_mld_learn_exceed_cmd_get), \
+    SW_API_DEF(SW_API_IGMP_SG_ENTRY_SET,    isisc_igmp_sg_entry_set),  \
+    SW_API_DEF(SW_API_IGMP_SG_ENTRY_CLEAR,    isisc_igmp_sg_entry_clear),  \
+    SW_API_DEF(SW_API_IGMP_SG_ENTRY_SHOW,    isisc_igmp_sg_entry_show),
+
+#define IGMP_API_PARAM \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
+    SW_API_DESC(SW_API_IGMP_MLD_CMD_SET)  \
+    SW_API_DESC(SW_API_IGMP_MLD_CMD_GET)  \
+    SW_API_DESC(SW_API_IGMP_PT_JOIN_SET)  \
+    SW_API_DESC(SW_API_IGMP_PT_JOIN_GET)  \
+    SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \
+    SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \
+    SW_API_DESC(SW_API_IGMP_RP_SET)  \
+    SW_API_DESC(SW_API_IGMP_RP_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_SET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_GET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET) \
+    SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET) \
+    SW_API_DESC(SW_API_IGMP_SG_ENTRY_SET) \
+    SW_API_DESC(SW_API_IGMP_SG_ENTRY_CLEAR) \
+    SW_API_DESC(SW_API_IGMP_SG_ENTRY_SHOW)
+#else
+#define IGMP_API
+#define IGMP_API_PARAM
+#endif
+
+
+#ifdef IN_LEAKY
+#define LEAKY_API \
+    SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, isisc_uc_leaky_mode_set), \
+    SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, isisc_uc_leaky_mode_get), \
+    SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, isisc_mc_leaky_mode_set), \
+    SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, isisc_mc_leaky_mode_get), \
+    SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, isisc_port_arp_leaky_set), \
+    SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, isisc_port_arp_leaky_get), \
+    SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, isisc_port_uc_leaky_set), \
+    SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, isisc_port_uc_leaky_get), \
+    SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, isisc_port_mc_leaky_set), \
+    SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, isisc_port_mc_leaky_get),
+
+#define LEAKY_API_PARAM \
+    SW_API_DESC(SW_API_UC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_UC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_MC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_MC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \
+    SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \
+    SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET)
+#else
+#define LEAKY_API
+#define LEAKY_API_PARAM
+#endif
+
+
+#ifdef IN_MIRROR
+#define MIRROR_API \
+    SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, isisc_mirr_analysis_port_set), \
+    SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, isisc_mirr_analysis_port_get), \
+    SW_API_DEF(SW_API_MIRROR_IN_PT_SET, isisc_mirr_port_in_set), \
+    SW_API_DEF(SW_API_MIRROR_IN_PT_GET, isisc_mirr_port_in_get), \
+    SW_API_DEF(SW_API_MIRROR_EG_PT_SET, isisc_mirr_port_eg_set), \
+    SW_API_DEF(SW_API_MIRROR_EG_PT_GET, isisc_mirr_port_eg_get),
+
+#define MIRROR_API_PARAM \
+    SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET)  \
+    SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET)  \
+    SW_API_DESC(SW_API_MIRROR_IN_PT_SET)  \
+    SW_API_DESC(SW_API_MIRROR_IN_PT_GET)  \
+    SW_API_DESC(SW_API_MIRROR_EG_PT_SET)  \
+    SW_API_DESC(SW_API_MIRROR_EG_PT_GET)
+#else
+#define MIRROR_API
+#define MIRROR_API_PARAM
+#endif
+
+
+#ifdef IN_RATE
+#define RATE_API \
+    SW_API_DEF(SW_API_RATE_PORT_POLICER_SET, isisc_rate_port_policer_set), \
+    SW_API_DEF(SW_API_RATE_PORT_POLICER_GET, isisc_rate_port_policer_get), \
+    SW_API_DEF(SW_API_RATE_PORT_SHAPER_SET, isisc_rate_port_shaper_set), \
+    SW_API_DEF(SW_API_RATE_PORT_SHAPER_GET, isisc_rate_port_shaper_get), \
+    SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_SET, isisc_rate_queue_shaper_set), \
+    SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_GET, isisc_rate_queue_shaper_get), \
+    SW_API_DEF(SW_API_RATE_ACL_POLICER_SET, isisc_rate_acl_policer_set), \
+    SW_API_DEF(SW_API_RATE_ACL_POLICER_GET, isisc_rate_acl_policer_get), \
+    SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, isisc_rate_port_add_rate_byte_set), \
+    SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, isisc_rate_port_add_rate_byte_get), \
+    SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, isisc_rate_port_gol_flow_en_set), \
+    SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, isisc_rate_port_gol_flow_en_get),
+
+#define RATE_API_PARAM \
+    SW_API_DESC(SW_API_RATE_PORT_POLICER_SET) \
+    SW_API_DESC(SW_API_RATE_PORT_POLICER_GET) \
+    SW_API_DESC(SW_API_RATE_PORT_SHAPER_SET) \
+    SW_API_DESC(SW_API_RATE_PORT_SHAPER_GET) \
+    SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_SET) \
+    SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_GET) \
+    SW_API_DESC(SW_API_RATE_ACL_POLICER_SET) \
+    SW_API_DESC(SW_API_RATE_ACL_POLICER_GET) \
+    SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_SET) \
+    SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_GET) \
+    SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_SET) \
+    SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_GET)
+#else
+#define RATE_API
+#define RATE_API_PARAM
+#endif
+
+
+#ifdef IN_STP
+#define STP_API \
+    SW_API_DEF(SW_API_STP_PT_STATE_SET, isisc_stp_port_state_set), \
+    SW_API_DEF(SW_API_STP_PT_STATE_GET, isisc_stp_port_state_get),
+
+#define STP_API_PARAM \
+    SW_API_DESC(SW_API_STP_PT_STATE_SET) \
+    SW_API_DESC(SW_API_STP_PT_STATE_GET)
+#else
+#define STP_API
+#define STP_API_PARAM
+#endif
+
+
+#ifdef IN_MIB
+#define MIB_API \
+    SW_API_DEF(SW_API_PT_MIB_GET, isisc_get_mib_info), \
+    SW_API_DEF(SW_API_MIB_STATUS_SET, isisc_mib_status_set), \
+    SW_API_DEF(SW_API_MIB_STATUS_GET, isisc_mib_status_get), \
+    SW_API_DEF(SW_API_PT_MIB_FLUSH_COUNTERS, isisc_mib_port_flush_counters), \
+    SW_API_DEF(SW_API_MIB_CPU_KEEP_SET, isisc_mib_cpukeep_set), \
+    SW_API_DEF(SW_API_MIB_CPU_KEEP_GET, isisc_mib_cpukeep_get),
+
+
+#define MIB_API_PARAM \
+    SW_API_DESC(SW_API_PT_MIB_GET)  \
+    SW_API_DESC(SW_API_MIB_STATUS_SET) \
+    SW_API_DESC(SW_API_MIB_STATUS_GET)\
+    SW_API_DESC(SW_API_PT_MIB_FLUSH_COUNTERS) \
+    SW_API_DESC(SW_API_MIB_CPU_KEEP_SET) \
+    SW_API_DESC(SW_API_MIB_CPU_KEEP_GET)
+#else
+#define MIB_API
+#define MIB_API_PARAM
+#endif
+
+
+#ifdef IN_MISC
+#define MISC_API \
+    SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, isisc_frame_max_size_set), \
+    SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, isisc_frame_max_size_get), \
+    SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, isisc_port_unk_uc_filter_set), \
+    SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, isisc_port_unk_uc_filter_get), \
+    SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, isisc_port_unk_mc_filter_set), \
+    SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, isisc_port_unk_mc_filter_get), \
+    SW_API_DEF(SW_API_PT_BC_FILTER_SET, isisc_port_bc_filter_set), \
+    SW_API_DEF(SW_API_PT_BC_FILTER_GET, isisc_port_bc_filter_get), \
+    SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, isisc_cpu_port_status_set), \
+    SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, isisc_cpu_port_status_get), \
+    SW_API_DEF(SW_API_PPPOE_CMD_SET, isisc_pppoe_cmd_set), \
+    SW_API_DEF(SW_API_PPPOE_CMD_GET, isisc_pppoe_cmd_get), \
+    SW_API_DEF(SW_API_PPPOE_STATUS_SET, isisc_pppoe_status_set), \
+    SW_API_DEF(SW_API_PPPOE_STATUS_GET, isisc_pppoe_status_get), \
+    SW_API_DEF(SW_API_PT_DHCP_SET, isisc_port_dhcp_set), \
+    SW_API_DEF(SW_API_PT_DHCP_GET, isisc_port_dhcp_get), \
+    SW_API_DEF(SW_API_ARP_CMD_SET, isisc_arp_cmd_set), \
+    SW_API_DEF(SW_API_ARP_CMD_GET, isisc_arp_cmd_get), \
+    SW_API_DEF(SW_API_EAPOL_CMD_SET, isisc_eapol_cmd_set), \
+    SW_API_DEF(SW_API_EAPOL_CMD_GET, isisc_eapol_cmd_get), \
+    SW_API_DEF(SW_API_EAPOL_STATUS_SET, isisc_eapol_status_set), \
+    SW_API_DEF(SW_API_EAPOL_STATUS_GET, isisc_eapol_status_get), \
+    SW_API_DEF(SW_API_RIPV1_STATUS_SET, isisc_ripv1_status_set), \
+    SW_API_DEF(SW_API_RIPV1_STATUS_GET, isisc_ripv1_status_get), \
+    SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_SET, isisc_port_arp_req_status_set), \
+    SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_GET, isisc_port_arp_req_status_get), \
+    SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_SET, isisc_port_arp_ack_status_set), \
+    SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_GET, isisc_port_arp_ack_status_get), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, isisc_pppoe_session_table_add), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, isisc_pppoe_session_table_del), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_GET, isisc_pppoe_session_table_get), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_ID_SET, isisc_pppoe_session_id_set), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_ID_GET, isisc_pppoe_session_id_get), \
+    SW_API_DEF(SW_API_INTR_MASK_SET, isisc_intr_mask_set), \
+    SW_API_DEF(SW_API_INTR_MASK_GET, isisc_intr_mask_get), \
+    SW_API_DEF(SW_API_INTR_STATUS_GET, isisc_intr_status_get),   \
+    SW_API_DEF(SW_API_INTR_STATUS_CLEAR, isisc_intr_status_clear), \
+    SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_SET, isisc_intr_port_link_mask_set), \
+    SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_GET, isisc_intr_port_link_mask_get), \
+    SW_API_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, isisc_intr_port_link_status_get),\
+    SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, isisc_intr_mask_mac_linkchg_set), \
+    SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, isisc_intr_mask_mac_linkchg_get), \
+    SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_GET, isisc_intr_status_mac_linkchg_get), \
+        SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, isisc_intr_status_mac_linkchg_clear), \
+    SW_API_DEF(SW_API_CPU_VID_EN_SET, isisc_cpu_vid_en_set), \
+    SW_API_DEF(SW_API_CPU_VID_EN_GET, isisc_cpu_vid_en_get), \
+    SW_API_DEF(SW_API_RTD_PPPOE_EN_SET, isisc_rtd_pppoe_en_set), \
+    SW_API_DEF(SW_API_RTD_PPPOE_EN_GET, isisc_rtd_pppoe_en_get),
+
+#define MISC_API_PARAM \
+    SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET)  \
+    SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET)  \
+    SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET)  \
+    SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET)  \
+    SW_API_DESC(SW_API_PT_BC_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_BC_FILTER_GET)  \
+    SW_API_DESC(SW_API_CPU_PORT_STATUS_SET)  \
+    SW_API_DESC(SW_API_CPU_PORT_STATUS_GET)  \
+    SW_API_DESC(SW_API_PPPOE_CMD_SET)  \
+    SW_API_DESC(SW_API_PPPOE_CMD_GET)  \
+    SW_API_DESC(SW_API_PPPOE_STATUS_SET)  \
+    SW_API_DESC(SW_API_PPPOE_STATUS_GET)  \
+    SW_API_DESC(SW_API_PT_DHCP_SET)  \
+    SW_API_DESC(SW_API_PT_DHCP_GET)  \
+    SW_API_DESC(SW_API_ARP_CMD_SET)  \
+    SW_API_DESC(SW_API_ARP_CMD_GET)  \
+    SW_API_DESC(SW_API_EAPOL_CMD_SET) \
+    SW_API_DESC(SW_API_EAPOL_CMD_GET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_ADD)  \
+    SW_API_DESC(SW_API_PPPOE_SESSION_DEL)  \
+    SW_API_DESC(SW_API_PPPOE_SESSION_GET)  \
+    SW_API_DESC(SW_API_EAPOL_STATUS_SET)  \
+    SW_API_DESC(SW_API_EAPOL_STATUS_GET)  \
+    SW_API_DESC(SW_API_RIPV1_STATUS_SET)  \
+    SW_API_DESC(SW_API_RIPV1_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_SET) \
+    SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_GET) \
+    SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_SET) \
+    SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_GET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_ADD) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_DEL) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_GET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_ID_SET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_ID_GET) \
+    SW_API_DESC(SW_API_INTR_MASK_SET) \
+    SW_API_DESC(SW_API_INTR_MASK_GET) \
+    SW_API_DESC(SW_API_INTR_STATUS_GET)   \
+    SW_API_DESC(SW_API_INTR_STATUS_CLEAR) \
+    SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_SET) \
+    SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_GET) \
+    SW_API_DESC(SW_API_INTR_PORT_LINK_STATUS_GET) \
+     SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_SET) \
+    SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_GET) \
+    SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_GET) \
+    SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR) \
+    SW_API_DESC(SW_API_CPU_VID_EN_SET)  \
+    SW_API_DESC(SW_API_CPU_VID_EN_GET)  \
+    SW_API_DESC(SW_API_RTD_PPPOE_EN_SET)  \
+    SW_API_DESC(SW_API_RTD_PPPOE_EN_GET)
+
+#else
+#define MISC_API
+#define MISC_API_PARAM
+#endif
+
+
+#ifdef IN_LED
+#define LED_API \
+    SW_API_DEF(SW_API_LED_PATTERN_SET, isisc_led_ctrl_pattern_set), \
+    SW_API_DEF(SW_API_LED_PATTERN_GET, isisc_led_ctrl_pattern_get),
+
+#define LED_API_PARAM \
+    SW_API_DESC(SW_API_LED_PATTERN_SET) \
+    SW_API_DESC(SW_API_LED_PATTERN_GET)
+#else
+#define LED_API
+#define LED_API_PARAM
+#endif
+
+#ifdef IN_COSMAP
+#define COSMAP_API \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, isisc_cosmap_dscp_to_pri_set), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, isisc_cosmap_dscp_to_pri_get), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, isisc_cosmap_dscp_to_dp_set), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, isisc_cosmap_dscp_to_dp_get), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_SET, isisc_cosmap_up_to_pri_set), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_GET, isisc_cosmap_up_to_pri_get), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_DP_SET, isisc_cosmap_up_to_dp_set), \
+    SW_API_DEF(SW_API_COSMAP_UP_TO_DP_GET, isisc_cosmap_up_to_dp_get), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_SET, isisc_cosmap_pri_to_queue_set), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_GET, isisc_cosmap_pri_to_queue_get), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, isisc_cosmap_pri_to_ehqueue_set), \
+    SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, isisc_cosmap_pri_to_ehqueue_get), \
+    SW_API_DEF(SW_API_COSMAP_EG_REMARK_SET, isisc_cosmap_egress_remark_set), \
+    SW_API_DEF(SW_API_COSMAP_EG_REMARK_GET, isisc_cosmap_egress_remark_get),
+
+#define COSMAP_API_PARAM \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_SET)  \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_GET)  \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_SET)  \
+    SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_GET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_SET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_GET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_DP_SET)  \
+    SW_API_DESC(SW_API_COSMAP_UP_TO_DP_GET)  \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_SET)  \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_GET)  \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_SET) \
+    SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_GET) \
+    SW_API_DESC(SW_API_COSMAP_EG_REMARK_SET) \
+    SW_API_DESC(SW_API_COSMAP_EG_REMARK_GET)
+#else
+#define COSMAP_API
+#define COSMAP_API_PARAM
+#endif
+
+#ifdef IN_SEC
+#define SEC_API \
+    SW_API_DEF(SW_API_SEC_NORM_SET, isisc_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_NORM_GET, isisc_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_MAC_SET, isisc_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_MAC_GET, isisc_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_IP_SET, isisc_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_IP_GET, isisc_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_IP4_SET, isisc_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_IP4_GET, isisc_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_IP6_SET, isisc_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_IP6_GET, isisc_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_TCP_SET, isisc_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_TCP_GET, isisc_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_UDP_SET, isisc_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_UDP_GET, isisc_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_ICMP4_SET, isisc_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_ICMP4_GET, isisc_sec_norm_item_get), \
+    SW_API_DEF(SW_API_SEC_ICMP6_SET, isisc_sec_norm_item_set), \
+    SW_API_DEF(SW_API_SEC_ICMP6_GET, isisc_sec_norm_item_get),
+
+#define SEC_API_PARAM \
+    SW_API_DESC(SW_API_SEC_NORM_SET) \
+    SW_API_DESC(SW_API_SEC_NORM_GET) \
+    SW_API_DESC(SW_API_SEC_MAC_SET) \
+    SW_API_DESC(SW_API_SEC_MAC_GET) \
+    SW_API_DESC(SW_API_SEC_IP_SET) \
+    SW_API_DESC(SW_API_SEC_IP_GET) \
+    SW_API_DESC(SW_API_SEC_IP4_SET) \
+    SW_API_DESC(SW_API_SEC_IP4_GET) \
+    SW_API_DESC(SW_API_SEC_IP6_SET) \
+    SW_API_DESC(SW_API_SEC_IP6_GET) \
+    SW_API_DESC(SW_API_SEC_TCP_SET) \
+    SW_API_DESC(SW_API_SEC_TCP_GET) \
+    SW_API_DESC(SW_API_SEC_UDP_SET) \
+    SW_API_DESC(SW_API_SEC_UDP_GET) \
+    SW_API_DESC(SW_API_SEC_ICMP4_SET) \
+    SW_API_DESC(SW_API_SEC_ICMP4_GET) \
+    SW_API_DESC(SW_API_SEC_ICMP6_SET) \
+    SW_API_DESC(SW_API_SEC_ICMP6_GET)
+#else
+#define SEC_API
+#define SEC_API_PARAM
+#endif
+
+#ifdef IN_IP
+#define IP_API \
+    SW_API_DEF(SW_API_IP_HOST_ADD, isisc_ip_host_add), \
+    SW_API_DEF(SW_API_IP_HOST_DEL, isisc_ip_host_del), \
+    SW_API_DEF(SW_API_IP_HOST_GET, isisc_ip_host_get), \
+    SW_API_DEF(SW_API_IP_HOST_NEXT, isisc_ip_host_next), \
+    SW_API_DEF(SW_API_IP_HOST_COUNTER_BIND, isisc_ip_host_counter_bind), \
+    SW_API_DEF(SW_API_IP_HOST_PPPOE_BIND, isisc_ip_host_pppoe_bind), \
+    SW_API_DEF(SW_API_IP_PT_ARP_LEARN_SET, isisc_ip_pt_arp_learn_set), \
+    SW_API_DEF(SW_API_IP_PT_ARP_LEARN_GET, isisc_ip_pt_arp_learn_get), \
+    SW_API_DEF(SW_API_IP_ARP_LEARN_SET, isisc_ip_arp_learn_set), \
+    SW_API_DEF(SW_API_IP_ARP_LEARN_GET, isisc_ip_arp_learn_get), \
+    SW_API_DEF(SW_API_IP_SOURCE_GUARD_SET, isisc_ip_source_guard_set), \
+    SW_API_DEF(SW_API_IP_SOURCE_GUARD_GET, isisc_ip_source_guard_get), \
+    SW_API_DEF(SW_API_IP_ARP_GUARD_SET, isisc_ip_arp_guard_set), \
+    SW_API_DEF(SW_API_IP_ARP_GUARD_GET, isisc_ip_arp_guard_get), \
+    SW_API_DEF(SW_API_IP_ROUTE_STATUS_SET, isisc_ip_route_status_set), \
+    SW_API_DEF(SW_API_IP_ROUTE_STATUS_GET, isisc_ip_route_status_get), \
+    SW_API_DEF(SW_API_IP_INTF_ENTRY_ADD, isisc_ip_intf_entry_add), \
+    SW_API_DEF(SW_API_IP_INTF_ENTRY_DEL, isisc_ip_intf_entry_del), \
+    SW_API_DEF(SW_API_IP_INTF_ENTRY_NEXT, isisc_ip_intf_entry_next), \
+    SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, isisc_ip_unk_source_cmd_set),  \
+    SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, isisc_ip_unk_source_cmd_get), \
+    SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, isisc_arp_unk_source_cmd_set), \
+    SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, isisc_arp_unk_source_cmd_get), \
+    SW_API_DEF(SW_API_IP_AGE_TIME_SET, isisc_ip_age_time_set), \
+    SW_API_DEF(SW_API_IP_AGE_TIME_GET, isisc_ip_age_time_get), \
+    SW_API_DEF(SW_API_WCMP_HASH_MODE_SET, isisc_ip_wcmp_hash_mode_set), \
+    SW_API_DEF(SW_API_WCMP_HASH_MODE_GET, isisc_ip_wcmp_hash_mode_get),
+
+#define IP_API_PARAM \
+    SW_API_DESC(SW_API_IP_HOST_ADD) \
+    SW_API_DESC(SW_API_IP_HOST_DEL) \
+    SW_API_DESC(SW_API_IP_HOST_GET) \
+    SW_API_DESC(SW_API_IP_HOST_NEXT) \
+    SW_API_DESC(SW_API_IP_HOST_COUNTER_BIND) \
+    SW_API_DESC(SW_API_IP_HOST_PPPOE_BIND) \
+    SW_API_DESC(SW_API_IP_PT_ARP_LEARN_SET) \
+    SW_API_DESC(SW_API_IP_PT_ARP_LEARN_GET) \
+    SW_API_DESC(SW_API_IP_ARP_LEARN_SET) \
+    SW_API_DESC(SW_API_IP_ARP_LEARN_GET) \
+    SW_API_DESC(SW_API_IP_SOURCE_GUARD_SET) \
+    SW_API_DESC(SW_API_IP_SOURCE_GUARD_GET) \
+    SW_API_DESC(SW_API_IP_ARP_GUARD_SET) \
+    SW_API_DESC(SW_API_IP_ARP_GUARD_GET) \
+    SW_API_DESC(SW_API_IP_ROUTE_STATUS_SET) \
+    SW_API_DESC(SW_API_IP_ROUTE_STATUS_GET) \
+    SW_API_DESC(SW_API_IP_INTF_ENTRY_ADD)  \
+    SW_API_DESC(SW_API_IP_INTF_ENTRY_DEL)  \
+    SW_API_DESC(SW_API_IP_INTF_ENTRY_NEXT) \
+    SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_SET)  \
+    SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_GET)  \
+    SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_SET) \
+    SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_GET) \
+    SW_API_DESC(SW_API_IP_AGE_TIME_SET) \
+    SW_API_DESC(SW_API_IP_AGE_TIME_GET) \
+    SW_API_DESC(SW_API_WCMP_HASH_MODE_SET) \
+    SW_API_DESC(SW_API_WCMP_HASH_MODE_GET)
+
+#else
+#define IP_API
+#define IP_API_PARAM
+#endif
+
+#ifdef IN_NAT
+#define NAT_API \
+    SW_API_DEF(SW_API_NAT_ADD, isisc_nat_add), \
+    SW_API_DEF(SW_API_NAT_DEL, isisc_nat_del), \
+    SW_API_DEF(SW_API_NAT_GET, isisc_nat_get), \
+    SW_API_DEF(SW_API_NAT_NEXT, isisc_nat_next), \
+    SW_API_DEF(SW_API_NAT_COUNTER_BIND, isisc_nat_counter_bind), \
+    SW_API_DEF(SW_API_NAPT_ADD, isisc_napt_add), \
+    SW_API_DEF(SW_API_NAPT_DEL, isisc_napt_del), \
+    SW_API_DEF(SW_API_NAPT_GET, isisc_napt_get), \
+    SW_API_DEF(SW_API_NAPT_NEXT, isisc_napt_next), \
+    SW_API_DEF(SW_API_NAPT_COUNTER_BIND, isisc_napt_counter_bind), \
+    SW_API_DEF(SW_API_NAT_STATUS_SET, isisc_nat_status_set), \
+    SW_API_DEF(SW_API_NAT_STATUS_GET, isisc_nat_status_get), \
+    SW_API_DEF(SW_API_NAT_HASH_MODE_SET, isisc_nat_hash_mode_set), \
+    SW_API_DEF(SW_API_NAT_HASH_MODE_GET, isisc_nat_hash_mode_get), \
+    SW_API_DEF(SW_API_NAPT_STATUS_SET, isisc_napt_status_set), \
+    SW_API_DEF(SW_API_NAPT_STATUS_GET, isisc_napt_status_get), \
+    SW_API_DEF(SW_API_NAPT_MODE_SET, isisc_napt_mode_set), \
+    SW_API_DEF(SW_API_NAPT_MODE_GET, isisc_napt_mode_get), \
+    SW_API_DEF(SW_API_PRV_BASE_ADDR_SET, isisc_nat_prv_base_addr_set), \
+    SW_API_DEF(SW_API_PRV_BASE_ADDR_GET, isisc_nat_prv_base_addr_get), \
+    SW_API_DEF(SW_API_PUB_ADDR_ENTRY_ADD, isisc_nat_pub_addr_add), \
+    SW_API_DEF(SW_API_PUB_ADDR_ENTRY_DEL, isisc_nat_pub_addr_del), \
+    SW_API_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, isisc_nat_pub_addr_next), \
+    SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, isisc_nat_unk_session_cmd_set), \
+    SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, isisc_nat_unk_session_cmd_get), \
+    SW_API_DEF(SW_API_PRV_BASE_MASK_SET, isisc_nat_prv_base_mask_set), \
+    SW_API_DEF(SW_API_PRV_BASE_MASK_GET, isisc_nat_prv_base_mask_get), \
+    SW_API_DEF(SW_API_NAT_GLOBAL_SET, isisc_nat_global_set),
+
+#define NAT_API_PARAM \
+    SW_API_DESC(SW_API_NAT_ADD) \
+    SW_API_DESC(SW_API_NAT_DEL) \
+    SW_API_DESC(SW_API_NAT_GET) \
+    SW_API_DESC(SW_API_NAT_NEXT) \
+    SW_API_DESC(SW_API_NAT_COUNTER_BIND) \
+    SW_API_DESC(SW_API_NAPT_ADD) \
+    SW_API_DESC(SW_API_NAPT_DEL) \
+    SW_API_DESC(SW_API_NAPT_GET) \
+    SW_API_DESC(SW_API_NAPT_NEXT) \
+    SW_API_DESC(SW_API_NAPT_COUNTER_BIND) \
+    SW_API_DESC(SW_API_NAT_STATUS_SET) \
+    SW_API_DESC(SW_API_NAT_STATUS_GET) \
+    SW_API_DESC(SW_API_NAT_HASH_MODE_SET) \
+    SW_API_DESC(SW_API_NAT_HASH_MODE_GET) \
+    SW_API_DESC(SW_API_NAPT_STATUS_SET) \
+    SW_API_DESC(SW_API_NAPT_STATUS_GET) \
+    SW_API_DESC(SW_API_NAPT_MODE_SET) \
+    SW_API_DESC(SW_API_NAPT_MODE_GET) \
+    SW_API_DESC(SW_API_PRV_BASE_ADDR_SET) \
+    SW_API_DESC(SW_API_PRV_BASE_ADDR_GET) \
+    SW_API_DESC(SW_API_PUB_ADDR_ENTRY_ADD) \
+    SW_API_DESC(SW_API_PUB_ADDR_ENTRY_DEL) \
+    SW_API_DESC(SW_API_PUB_ADDR_ENTRY_NEXT) \
+    SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_SET) \
+    SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_GET) \
+    SW_API_DESC(SW_API_PRV_BASE_MASK_SET) \
+    SW_API_DESC(SW_API_PRV_BASE_MASK_GET) \
+    SW_API_DESC(SW_API_NAT_GLOBAL_SET)
+#else
+#define NAT_API
+#define NAT_API_PARAM
+#endif
+
+#ifdef IN_TRUNK
+#define TRUNK_API \
+    SW_API_DEF(SW_API_TRUNK_GROUP_SET, isisc_trunk_group_set), \
+    SW_API_DEF(SW_API_TRUNK_GROUP_GET, isisc_trunk_group_get), \
+    SW_API_DEF(SW_API_TRUNK_HASH_SET, isisc_trunk_hash_mode_set), \
+    SW_API_DEF(SW_API_TRUNK_HASH_GET, isisc_trunk_hash_mode_get), \
+    SW_API_DEF(SW_API_TRUNK_MAN_SA_SET, isisc_trunk_manipulate_sa_set), \
+    SW_API_DEF(SW_API_TRUNK_MAN_SA_GET, isisc_trunk_manipulate_sa_get),
+
+#define TRUNK_API_PARAM \
+    SW_API_DESC(SW_API_TRUNK_GROUP_SET) \
+    SW_API_DESC(SW_API_TRUNK_GROUP_GET) \
+    SW_API_DESC(SW_API_TRUNK_HASH_SET)  \
+    SW_API_DESC(SW_API_TRUNK_HASH_GET)  \
+    SW_API_DESC(SW_API_TRUNK_MAN_SA_SET)\
+    SW_API_DESC(SW_API_TRUNK_MAN_SA_GET)
+#else
+#define TRUNK_API
+#define TRUNK_API_PARAM
+#endif
+
+#ifdef IN_INTERFACECONTROL
+#define INTERFACECTRL_API \
+    SW_API_DEF(SW_API_MAC_MODE_SET, isisc_interface_mac_mode_set), \
+    SW_API_DEF(SW_API_MAC_MODE_GET, isisc_interface_mac_mode_get), \
+    SW_API_DEF(SW_API_PORT_3AZ_STATUS_SET, isisc_port_3az_status_set), \
+    SW_API_DEF(SW_API_PORT_3AZ_STATUS_GET, isisc_port_3az_status_get), \
+    SW_API_DEF(SW_API_PHY_MODE_SET, isisc_interface_phy_mode_set), \
+    SW_API_DEF(SW_API_PHY_MODE_GET, isisc_interface_phy_mode_get), \
+    SW_API_DEF(SW_API_FX100_CTRL_SET, isisc_interface_fx100_ctrl_set), \
+    SW_API_DEF(SW_API_FX100_CTRL_GET, isisc_interface_fx100_ctrl_get), \
+    SW_API_DEF(SW_API_FX100_STATUS_GET, isisc_interface_fx100_status_get), \
+    SW_API_DEF(SW_API_MAC06_EXCH_SET, isisc_interface_mac06_exch_set), \
+    SW_API_DEF(SW_API_MAC06_EXCH_GET, isisc_interface_mac06_exch_get),
+
+#define INTERFACECTRL_API_PARAM \
+    SW_API_DESC(SW_API_MAC_MODE_SET)  \
+    SW_API_DESC(SW_API_MAC_MODE_GET)  \
+    SW_API_DESC(SW_API_PORT_3AZ_STATUS_SET)  \
+    SW_API_DESC(SW_API_PORT_3AZ_STATUS_GET)  \
+    SW_API_DESC(SW_API_PHY_MODE_SET)  \
+    SW_API_DESC(SW_API_PHY_MODE_GET)  \
+    SW_API_DESC(SW_API_FX100_CTRL_SET)  \
+    SW_API_DESC(SW_API_FX100_CTRL_GET)  \
+    SW_API_DESC(SW_API_FX100_STATUS_GET) \
+    SW_API_DESC(SW_API_MAC06_EXCH_SET) \
+    SW_API_DESC(SW_API_MAC06_EXCH_GET)
+
+#else
+#define INTERFACECTRL_API
+#define INTERFACECTRL_API_PARAM
+#endif
+
+#define REG_API \
+    SW_API_DEF(SW_API_PHY_GET, isisc_phy_get), \
+    SW_API_DEF(SW_API_PHY_SET, isisc_phy_set), \
+    SW_API_DEF(SW_API_REG_GET, isisc_reg_get), \
+    SW_API_DEF(SW_API_REG_SET, isisc_reg_set), \
+    SW_API_DEF(SW_API_REG_FIELD_GET, isisc_reg_field_get), \
+    SW_API_DEF(SW_API_REG_FIELD_SET, isisc_reg_field_set), \
+    SW_API_DEF(SW_API_REG_DUMP, isisc_regsiter_dump), \
+    SW_API_DEF(SW_API_DBG_REG_DUMP, isisc_debug_regsiter_dump),
+
+#define REG_API_PARAM \
+    SW_API_DESC(SW_API_PHY_GET) \
+    SW_API_DESC(SW_API_PHY_SET) \
+    SW_API_DESC(SW_API_REG_GET) \
+    SW_API_DESC(SW_API_REG_SET) \
+    SW_API_DESC(SW_API_REG_FIELD_GET) \
+    SW_API_DESC(SW_API_REG_FIELD_SET) \
+    SW_API_DESC(SW_API_REG_DUMP)  \
+    SW_API_DESC(SW_API_DBG_REG_DUMP)
+
+#define SSDK_API \
+    SW_API_DEF(SW_API_SWITCH_RESET, isisc_reset), \
+    SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \
+    PORTCONTROL_API \
+    VLAN_API \
+    PORTVLAN_API \
+    FDB_API    \
+    ACL_API    \
+    QOS_API    \
+    IGMP_API   \
+    LEAKY_API  \
+    MIRROR_API \
+    RATE_API \
+    STP_API  \
+    MIB_API  \
+    MISC_API \
+    LED_API  \
+    COSMAP_API \
+    SEC_API  \
+    IP_API \
+    NAT_API \
+    TRUNK_API \
+    INTERFACECTRL_API \
+    REG_API  \
+    SW_API_DEF(SW_API_MAX, NULL),
+
+
+#define SSDK_PARAM  \
+    SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
+    MIB_API_PARAM    \
+    LEAKY_API_PARAM  \
+    MISC_API_PARAM   \
+    IGMP_API_PARAM   \
+    MIRROR_API_PARAM \
+    PORTCONTROL_API_PARAM \
+    PORTVLAN_API_PARAM    \
+    VLAN_API_PARAM \
+    FDB_API_PARAM  \
+    QOS_API_PARAM  \
+    RATE_API_PARAM \
+    STP_API_PARAM  \
+    ACL_API_PARAM  \
+    LED_API_PARAM  \
+    COSMAP_API_PARAM \
+    SEC_API_PARAM  \
+    IP_API_PARAM \
+    NAT_API_PARAM \
+    TRUNK_API_PARAM \
+    INTERFACECTRL_API_PARAM \
+    REG_API_PARAM  \
+    SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#if (defined(USER_MODE) && defined(KERNEL_MODULE))
+#undef SSDK_API
+#undef SSDK_PARAM
+
+#define SSDK_API \
+    REG_API \
+    SW_API_DEF(SW_API_MAX, NULL),
+
+#define SSDK_PARAM  \
+    REG_API_PARAM \
+    SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _ISISC_API_H_ */
diff --git a/qca-ssdk/include/hsl/isisc/isisc_cosmap.h b/qca-ssdk/include/hsl/isisc/isisc_cosmap.h
new file mode 100755
index 0000000..d79a20b
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_cosmap.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_cosmap ISISC_COSMAP
+ * @{
+ */
+#ifndef _ISISC_COSMAP_H_
+#define _ISISC_COSMAP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_cosmap.h"
+
+    sw_error_t isisc_cosmap_init(a_uint32_t dev_id);
+
+#ifdef IN_COSMAP
+#define ISISC_COSMAP_INIT(rv, dev_id) \
+    { \
+        rv = isisc_cosmap_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_COSMAP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isisc_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp,
+                                a_uint32_t pri);
+
+    HSL_LOCAL sw_error_t
+    isisc_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+                                a_uint32_t * pri);
+
+    HSL_LOCAL sw_error_t
+    isisc_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp,
+                               a_uint32_t dp);
+
+    HSL_LOCAL sw_error_t
+    isisc_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp,
+                               a_uint32_t * dp);
+
+    HSL_LOCAL sw_error_t
+    isisc_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up,
+                              a_uint32_t pri);
+
+    HSL_LOCAL sw_error_t
+    isisc_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up,
+                              a_uint32_t * pri);
+
+    HSL_LOCAL sw_error_t
+    isisc_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up,
+                             a_uint32_t dp);
+
+    HSL_LOCAL sw_error_t
+    isisc_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up,
+                             a_uint32_t * dp);
+
+    HSL_LOCAL sw_error_t
+    isisc_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+                                 a_uint32_t queue);
+
+    HSL_LOCAL sw_error_t
+    isisc_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+                                 a_uint32_t * queue);
+
+    HSL_LOCAL sw_error_t
+    isisc_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+                                   a_uint32_t queue);
+
+    HSL_LOCAL sw_error_t
+    isisc_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+                                   a_uint32_t * queue);
+
+    HSL_LOCAL sw_error_t
+    isisc_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+                                  fal_egress_remark_table_t * tbl);
+
+    HSL_LOCAL sw_error_t
+    isisc_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+                                  fal_egress_remark_table_t * tbl);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_COSMAP_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_fdb.h b/qca-ssdk/include/hsl/isisc/isisc_fdb.h
new file mode 100755
index 0000000..13cd37c
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_fdb.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_fdb ISISC_FDB
+ * @{
+ */
+#ifndef _ISISC_FDB_H_
+#define _ISISC_FDB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_fdb.h"
+
+    sw_error_t isisc_fdb_init(a_uint32_t dev_id);
+
+#ifdef IN_FDB
+#define ISISC_FDB_INIT(rv, dev_id) \
+    { \
+        rv = isisc_fdb_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_FDB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t flag);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * op,
+                         fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+                          fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port,
+                      fal_port_t new_port, a_uint32_t fid,
+                      fal_fdb_op_t * option);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode * smode);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+    HSL_LOCAL sw_error_t
+    isisc_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable, a_uint32_t cnt);
+
+    HSL_LOCAL sw_error_t
+    isisc_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable, a_uint32_t * cnt);
+
+    HSL_LOCAL sw_error_t
+    isisc_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id,
+                                       fal_port_t port_id,
+                                       fal_fwd_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    isisc_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id,
+                                       fal_port_t port_id,
+                                       fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable,
+                             a_uint32_t cnt);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable,
+                             a_uint32_t * cnt);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+                          fal_fdb_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+    HSL_LOCAL sw_error_t
+    isisc_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_FDB_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_fdb_prv.h b/qca-ssdk/include/hsl/isisc/isisc_fdb_prv.h
new file mode 100755
index 0000000..a67e58d
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_fdb_prv.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_FDB_PRV_H_
+#define _ISISC_FDB_PRV_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+
+#define ARL_FLUSH_ALL             1
+#define ARL_LOAD_ENTRY            2
+#define ARL_PURGE_ENTRY           3
+#define ARL_FLUSH_ALL_UNLOCK      4
+#define ARL_FLUSH_PORT_UNICAST    5
+#define ARL_NEXT_ENTRY            6
+#define ARL_FIND_ENTRY            7
+#define ARL_TRANSFER_ENTRY        8
+
+#define ARL_FIRST_ENTRY           1001
+#define ARL_FLUSH_PORT_NO_STATIC  1002
+#define ARL_FLUSH_PORT_AND_STATIC 1003
+
+#define ISISC_MAX_FID                   4095
+#define ISISC_MAX_LEARN_LIMIT_CNT       2048
+#define ISISC_MAX_PORT_LEARN_LIMIT_CNT  1024
+
+    sw_error_t
+    inter_isisc_fdb_flush(a_uint32_t dev_id, a_uint32_t flag);
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_FDB_PRV_H_ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_igmp.h b/qca-ssdk/include/hsl/isisc/isisc_igmp.h
new file mode 100755
index 0000000..7d83f5d
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_igmp.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_igmp ISISC_IGMP
+ * @{
+ */
+#ifndef _ISISC_IGMP_H_
+#define _ISISC_IGMP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_igmp.h"
+#include "fal/fal_multi.h"
+
+    sw_error_t
+    isisc_igmp_init(a_uint32_t dev_id);
+
+#ifdef IN_IGMP
+#define ISISC_IGMP_INIT(rv, dev_id) \
+    { \
+        rv = isisc_igmp_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_IGMP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isisc_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                       a_bool_t enable, a_uint32_t cnt);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                       a_bool_t * enable, a_uint32_t * cnt);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                            fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                            fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_sg_entry_show(a_uint32_t dev_id);
+
+    HSL_LOCAL sw_error_t
+    isisc_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t * info);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _ISISC_IGMP_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/isisc/isisc_init.h b/qca-ssdk/include/hsl/isisc/isisc_init.h
new file mode 100755
index 0000000..18e8b07
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_init.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_init ISISC_INIT
+ * @{
+ */
+#ifndef _ISISC_INIT_H_
+#define _ISISC_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+
+    sw_error_t
+    isisc_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+
+    sw_error_t
+    isisc_cleanup(a_uint32_t dev_id);
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isisc_reset(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISISC_INIT_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/isisc/isisc_interface_ctrl.h b/qca-ssdk/include/hsl/isisc/isisc_interface_ctrl.h
new file mode 100755
index 0000000..2c9a9ab
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_interface_ctrl.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_INTERFACE_CTRL_H_
+#define _ISISC_INTERFACE_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_interface_ctrl.h"
+
+    sw_error_t isisc_interface_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_INTERFACECONTROL
+#define ISISC_INTERFACE_CTRL_INIT(rv, dev_id) \
+    { \
+        rv = isisc_interface_ctrl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_INTERFACE_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isisc_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+
+    HSL_LOCAL sw_error_t
+    isisc_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
+
+    HSL_LOCAL sw_error_t
+    isisc_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
+
+    HSL_LOCAL sw_error_t
+    isisc_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config);
+
+    HSL_LOCAL sw_error_t
+    isisc_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config);
+
+    HSL_LOCAL sw_error_t
+    isisc_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status);
+
+    HSL_LOCAL sw_error_t
+    isisc_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_INTERFACE_CTRL_H_ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_ip.h b/qca-ssdk/include/hsl/isisc/isisc_ip.h
new file mode 100755
index 0000000..bf90014
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_ip.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_IP_H_
+#define _ISISC_IP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_ip.h"
+
+    sw_error_t isisc_ip_init(a_uint32_t dev_id);
+
+    sw_error_t isisc_ip_reset(a_uint32_t dev_id);
+
+#ifdef IN_IP
+#define ISISC_IP_INIT(rv, dev_id) \
+    { \
+        rv = isisc_ip_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define ISISC_IP_RESET(rv, dev_id) \
+    { \
+        rv = isisc_ip_reset(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_IP_INIT(rv, dev_id)
+#define ISISC_IP_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                     fal_host_entry_t * host_entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                     fal_host_entry_t * host_entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                      fal_host_entry_t * host_entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                              a_uint32_t cnt_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                            a_uint32_t pppoe_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t flags);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * flags);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_source_guard_mode_t mode);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_source_guard_mode_t * mode);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_source_guard_mode_t mode);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_source_guard_mode_t * mode);
+
+    HSL_LOCAL sw_error_t
+    isisc_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    isisc_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                           fal_intf_mac_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                            fal_intf_mac_entry_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+    HSL_LOCAL sw_error_t
+    isisc_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_IP_H_ */
diff --git a/qca-ssdk/include/hsl/isisc/isisc_leaky.h b/qca-ssdk/include/hsl/isisc/isisc_leaky.h
new file mode 100755
index 0000000..5325cdd
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_leaky.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_LEAKY_H_
+#define _ISISC_LEAKY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_leaky.h"
+
+    sw_error_t isisc_leaky_init(a_uint32_t dev_id);
+
+#ifdef IN_LEAKY
+#define ISISC_LEAKY_INIT(rv, dev_id) \
+    { \
+        rv = isisc_leaky_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_LEAKY_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isisc_uc_leaky_mode_set(a_uint32_t dev_id,
+                           fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_uc_leaky_mode_get(a_uint32_t dev_id,
+                           fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_mc_leaky_mode_set(a_uint32_t dev_id,
+                           fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_mc_leaky_mode_get(a_uint32_t dev_id,
+                           fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_LEAKY_H_ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_led.h b/qca-ssdk/include/hsl/isisc/isisc_led.h
new file mode 100755
index 0000000..304763e
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_led.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_LED_H_
+#define _ISISC_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_led.h"
+
+    sw_error_t
+    isisc_led_init(a_uint32_t dev_id);
+
+#ifdef IN_LED
+#define ISISC_LED_INIT(rv, dev_id) \
+    { \
+        rv = isisc_led_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_LED_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isisc_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                              led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                              led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISISC_LED_H_ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_mib.h b/qca-ssdk/include/hsl/isisc/isisc_mib.h
new file mode 100755
index 0000000..3a1677d
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_mib.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_MIB_H_
+#define _ISISC_MIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mib.h"
+
+    sw_error_t
+    isisc_mib_init(a_uint32_t dev_id);
+
+#ifdef IN_MIB
+#define ISISC_MIB_INIT(rv, dev_id) \
+    { \
+        rv = isisc_mib_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_MIB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isisc_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_mib_info_t * mib_info );
+
+
+    HSL_LOCAL sw_error_t
+    isisc_mib_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_mib_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id);
+
+    HSL_LOCAL sw_error_t
+    isisc_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISISC_MIB_H_ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_mirror.h b/qca-ssdk/include/hsl/isisc/isisc_mirror.h
new file mode 100755
index 0000000..22e28c0
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_mirror.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_MIRROR_H_
+#define _ISISC_MIRROR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_mirror.h"
+#define  MIRROR_ANALYZER_NONE  0xf
+
+    sw_error_t isisc_mirr_init(a_uint32_t dev_id);
+
+#ifdef IN_MIRROR
+#define ISISC_MIRR_INIT(rv, dev_id) \
+    { \
+        rv = isisc_mirr_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_MIRR_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isisc_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_MIRROR_H_ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_misc.h b/qca-ssdk/include/hsl/isisc/isisc_misc.h
new file mode 100755
index 0000000..826105b
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_misc.h
@@ -0,0 +1,238 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_MISC_H_
+#define _ISISC_MISC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_misc.h"
+
+    sw_error_t isisc_misc_init(a_uint32_t dev_id);
+
+#ifdef IN_MISC
+#define ISISC_MISC_INIT(rv, dev_id) \
+    { \
+        rv = isisc_misc_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_MISC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isisc_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_pppoe_session_table_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_pppoe_session_table_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_pppoe_session_table_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+                              a_uint32_t id);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+                              a_uint32_t * id);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag);
+
+    HSL_LOCAL sw_error_t
+    isisc_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t *port_bitmap);
+
+    HSL_LOCAL sw_error_t
+    isisc_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_intr_status_mac_linkchg_clear(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_nat.h b/qca-ssdk/include/hsl/isisc/isisc_nat.h
new file mode 100755
index 0000000..7943ce9
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_nat.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_NAT_H_
+#define _ISISC_NAT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_nat.h"
+
+    sw_error_t isisc_nat_init(a_uint32_t dev_id);
+
+    sw_error_t isisc_nat_reset(a_uint32_t dev_id);
+
+#ifdef IN_NAT
+#define ISISC_NAT_INIT(rv, dev_id) \
+    { \
+        rv = isisc_nat_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define ISISC_NAT_RESET(rv, dev_id) \
+    { \
+        rv = isisc_nat_reset(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_NAT_INIT(rv, dev_id)
+#define ISISC_NAT_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isisc_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                   fal_napt_entry_t * napt_entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+    HSL_LOCAL sw_error_t
+    isisc_napt_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                  fal_napt_entry_t * napt_entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                 fal_nat_entry_t * nat_entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                          fal_nat_pub_addr_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                 fal_nat_entry_t * nat_entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                  fal_nat_entry_t * nat_entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                          a_uint32_t cnt_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_napt_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                  fal_napt_entry_t * napt_entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                           a_uint32_t cnt_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode);
+
+    HSL_LOCAL sw_error_t
+    isisc_napt_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_napt_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode);
+
+    HSL_LOCAL sw_error_t
+    isisc_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                           fal_nat_pub_addr_t * entry);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+    HSL_LOCAL sw_error_t
+    isisc_nat_global_set(a_uint32_t dev_id, a_bool_t enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_NAT_H_ */
diff --git a/qca-ssdk/include/hsl/isisc/isisc_nat_helper.h b/qca-ssdk/include/hsl/isisc/isisc_nat_helper.h
new file mode 100755
index 0000000..e7ff032
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_nat_helper.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_NAT_HELPER_H_
+#define _ISISC_NAT_HELPER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_nat.h"
+
+    sw_error_t nat_helper_init(a_uint32_t dev_id, a_uint32_t portbmp);
+
+    sw_error_t nat_helper_cleanup(a_uint32_t dev_id);
+
+#ifdef IN_NAT_HELPER
+#define ISISC_NAT_HELPER_INIT(rv, dev_id, portbmp) \
+    { \
+        rv = nat_helper_init(dev_id, portbmp); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define ISISC_NAT_HELPER_CLEANUP(rv, dev_id) \
+    { \
+        rv = nat_helper_cleanup(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_NAT_HELPER_INIT(rv, dev_id, portbmp)
+#define ISISC_NAT_HELPER_CLEANUP(rv, dev_id)
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_NAT_HELPER_H_ */
diff --git a/qca-ssdk/include/hsl/isisc/isisc_port_ctrl.h b/qca-ssdk/include/hsl/isisc/isisc_port_ctrl.h
new file mode 100755
index 0000000..19fc087
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_port_ctrl.h
@@ -0,0 +1,226 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_PORT_CTRL_H_
+#define _ISISC_PORT_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_port_ctrl.h"
+
+    sw_error_t isisc_port_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTCONTROL
+#define ISISC_PORT_CTRL_INIT(rv, dev_id) \
+    { \
+        rv = isisc_port_ctrl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_PORT_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_duplex_t duplex);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_duplex_t * pduplex);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_port_speed_t speed);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_port_speed_t * pspeed);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * status);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t autoadv);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * autoadv);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_flowctrl_forcemode_set(a_uint32_t dev_id,
+                                     fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_flowctrl_forcemode_get(a_uint32_t dev_id,
+                                     fal_port_t port_id,
+                                     a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+                  fal_cable_status_t *cable_status, a_uint32_t *cable_len);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_port_header_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_port_header_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_port_header_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_port_header_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status);
+
+    HSL_LOCAL sw_error_t
+    isisc_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status);
+
+    HSL_LOCAL sw_error_t
+    isisc_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_PORT_CTRL_H_ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_portvlan.h b/qca-ssdk/include/hsl/isisc/isisc_portvlan.h
new file mode 100755
index 0000000..248df0b
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_portvlan.h
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_PORTVLAN_H_
+#define _ISISC_PORTVLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_portvlan.h"
+
+    sw_error_t isisc_portvlan_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTVLAN
+#define ISISC_PORTVLAN_INIT(rv, dev_id) \
+    { \
+        rv = isisc_portvlan_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_PORTVLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_1qmode_t port_1qmode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_1qmode_t * pport_1qmode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pt_1q_egmode_t port_egvlanmode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pt_1q_egmode_t * pport_egvlanmode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t mem_port_id);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t mem_port_id);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_pbmp_t mem_port_map);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pbmp_t * mem_port_map);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pt_invlan_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pt_invlan_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+                      a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+                      a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t vid);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * vid);
+
+    HSL_LOCAL sw_error_t
+    isisc_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t vid);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * vid);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_vlan_propagation_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_vlan_propagation_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t * iterator, fal_vlan_trans_entry_t * entry);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_netisolate_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_netisolate_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_PORTVLAN_H */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_qos.h b/qca-ssdk/include/hsl/isisc/isisc_qos.h
new file mode 100755
index 0000000..e4d9323
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_qos.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_QOS_H_
+#define _ISISC_QOS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_qos.h"
+
+    sw_error_t isisc_qos_init(a_uint32_t dev_id);
+
+#ifdef IN_QOS
+#define ISISC_QOS_INIT(rv, dev_id) \
+    { \
+        rv = isisc_qos_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_QOS_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_queue_tx_buf_status_set(a_uint32_t dev_id,
+                                     fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_queue_tx_buf_status_get(a_uint32_t dev_id,
+                                     fal_port_t port_id,
+                                     a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t* enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_queue_t queue_id,
+                                 a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_queue_t queue_id,
+                                 a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_qos_mode_t mode, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_qos_mode_t mode, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_qos_mode_t mode, a_uint32_t pri);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_qos_mode_t mode, a_uint32_t * pri);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                               fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                               fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_uint32_t spri);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_uint32_t * spri);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_uint32_t cpri);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_uint32_t * cpri);
+
+    sw_error_t
+    isisc_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                        a_bool_t enable);
+
+    sw_error_t
+    isisc_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                        a_bool_t* enable);
+
+    sw_error_t
+    isisc_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                        a_bool_t enable);
+
+    sw_error_t
+    isisc_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                        a_bool_t* enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_QOS_H_ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_rate.h b/qca-ssdk/include/hsl/isisc/isisc_rate.h
new file mode 100755
index 0000000..4b4f48a
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_rate.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_RATE_H_
+#define _ISISC_RATE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_rate.h"
+
+    sw_error_t isisc_rate_init(a_uint32_t dev_id);
+
+#ifdef IN_RATE
+#define ISISC_RATE_INIT(rv, dev_id) \
+    { \
+        rv = isisc_rate_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_RATE_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isisc_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_port_policer_t * policer);
+
+    HSL_LOCAL sw_error_t
+    isisc_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_port_policer_t * policer);
+
+    HSL_LOCAL sw_error_t
+    isisc_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable,
+                              fal_egress_shaper_t * shaper);
+
+    HSL_LOCAL sw_error_t
+    isisc_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable,
+                              fal_egress_shaper_t * shaper);
+
+    HSL_LOCAL sw_error_t
+    isisc_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_bool_t enable,
+                               fal_egress_shaper_t * shaper);
+
+    HSL_LOCAL sw_error_t
+    isisc_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_bool_t * enable,
+                               fal_egress_shaper_t * shaper);
+
+    HSL_LOCAL sw_error_t
+    isisc_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+                              fal_acl_policer_t * policer);
+
+    HSL_LOCAL sw_error_t
+    isisc_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+                              fal_acl_policer_t * policer);
+
+    HSL_LOCAL sw_error_t
+    isisc_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_uint32_t  number);
+
+    HSL_LOCAL sw_error_t
+    isisc_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_uint32_t  *number);
+
+    HSL_LOCAL sw_error_t
+    isisc_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t  enable);
+
+    HSL_LOCAL sw_error_t
+    isisc_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t*  enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_RATE_H_ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_reg.h b/qca-ssdk/include/hsl/isisc/isisc_reg.h
new file mode 100755
index 0000000..1eb3d1b
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_reg.h
@@ -0,0 +1,5478 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _ISISC_REG_H_
+#define _ISISC_REG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#define S16E_DEVICE_ID  0x11
+#define S17C_DEVICE_ID   0x13 /* TBD */
+#define S17_REVISION_A  0x01
+
+#define MAX_ENTRY_LEN   128
+
+#define HSL_RW 1
+#define HSL_RO 0
+
+
+    /* ISIS Mask Control Register */
+#define MASK_CTL
+#define MASK_CTL_ID               0
+#define MASK_CTL_OFFSET           0x0000
+#define MASK_CTL_E_LENGTH         4
+#define MASK_CTL_E_OFFSET         0
+#define MASK_CTL_NR_E             1
+
+#define SOFT_RST
+#define MASK_CTL_SOFT_RST_BOFFSET             31
+#define MASK_CTL_SOFT_RST_BLEN                1
+#define MASK_CTL_SOFT_RST_FLAG                HSL_RW
+
+#define LOAD_EEPROM
+#define MASK_CTL_LOAD_EEPROM_BOFFSET          16
+#define MASK_CTL_LOAD_EEPROM_BLEN             1
+#define MASK_CTL_LOAD_EEPROM_FLAG             HSL_RW
+
+#define DEVICE_ID
+#define MASK_CTL_DEVICE_ID_BOFFSET            8
+#define MASK_CTL_DEVICE_ID_BLEN               8
+#define MASK_CTL_DEVICE_ID_FLAG               HSL_RO
+
+#define REV_ID
+#define MASK_CTL_REV_ID_BOFFSET               0
+#define MASK_CTL_REV_ID_BLEN                  8
+#define MASK_CTL_REV_ID_FLAG                  HSL_RO
+
+
+
+
+    /* Port0 Pad Control Register */
+#define PORT0_PAD_CTRL
+#define PORT0_PAD_CTRL_ID                                      0
+#define PORT0_PAD_CTRL_OFFSET                                  0x0004
+#define PORT0_PAD_CTRL_E_LENGTH                                4
+#define PORT0_PAD_CTRL_E_OFFSET                                0
+#define PORT0_PAD_CTRL_NR_E                                    1
+
+#define RMII_MAC06_EXCH_EN
+#define PORT0_PAD_CTRL_RMII_MAC06_EXCH_EN_BOFFSET              31
+#define PORT0_PAD_CTRL_RMII_MAC06_EXCH_EN_BLEN                 1
+#define PORT0_PAD_CTRL_RMII_MAC06_EXCH_EN_FLAG                 HSL_RW
+
+#define RMII_MASTER_EN
+#define PORT0_PAD_CTRL_RMII_MASTER_EN_BOFFSET                  30
+#define PORT0_PAD_CTRL_RMII_MASTER_EN_BLEN                     1
+#define PORT0_PAD_CTRL_RMII_MASTER_EN_FLAG                     HSL_RW
+
+#define RMII_SLAVE_EN
+#define PORT0_PAD_CTRL_RMII_SLAVE_EN_BOFFSET                   29
+#define PORT0_PAD_CTRL_RMII_SLAVE_EN_BLEN                      1
+#define PORT0_PAD_CTRL_RMII_SLAVE_EN_FLAG                      HSL_RW
+
+#define RMII_SEL
+#define PORT0_PAD_CTRL_RMII_SEL_BOFFSET                        28
+#define PORT0_PAD_CTRL_RMII_SEL_BLEN                           1
+#define PORT0_PAD_CTRL_RMII_SEL_FLAG                           HSL_RW
+
+#define RMII_PIPE_RXCLK_SEL
+#define PORT0_PAD_CTRL_RMII_PIPE_RXCLK_SEL_BOFFSET             27
+#define PORT0_PAD_CTRL_RMII_PIPE_RXCLK_SEL_BLEN                1
+#define PORT0_PAD_CTRL_RMII_PIPE_RXCLK_SEL_FLAG                HSL_RW
+
+#define MAC0_RGMII_EN
+#define PORT0_PAD_CTRL_MAC0_RGMII_EN_BOFFSET                   26
+#define PORT0_PAD_CTRL_MAC0_RGMII_EN_BLEN                      1
+#define PORT0_PAD_CTRL_MAC0_RGMII_EN_FLAG                      HSL_RW
+
+#define MAC0_RGMII_TXCLK_DELAY_EN
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_BOFFSET       25
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_BLEN          1
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_FLAG          HSL_RW
+
+#define MAC0_RGMII_RXCLK_DELAY_EN
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_BOFFSET       24
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_BLEN          1
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_FLAG          HSL_RW
+
+#define MAC0_RGMII_TXCLK_DELAY_SEL
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_BOFFSET      22
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_BLEN         2
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_FLAG         HSL_RW
+
+#define MAC0_RGMII_RXCLK_DELAY_SEL
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_BOFFSET      20
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_BLEN         2
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_FLAG         HSL_RW
+
+#define SGMII_CLK125M_RX_SEL
+#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_BOFFSET            19
+#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_BLEN               1
+#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_FLAG               HSL_RW
+
+#define SGMII_CLK125M_TX_SEL
+#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_BOFFSET            18
+#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_BLEN               1
+#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_FLAG               HSL_RW
+
+#define SGMII_FX100_EN
+#define PORT0_PAD_CTRL_SGMII_FX100_EN_BOFFSET                  17
+#define PORT0_PAD_CTRL_SGMII_FX100_EN_BLEN                     1
+#define PORT0_PAD_CTRL_SGMII_FX100_EN_FLAG                     HSL_RW
+
+#define SGMII_PRBS_BERT_EN
+#define PORT0_PAD_CTRL_SGMII_PRBS_BERT_EN_BOFFSET              16
+#define PORT0_PAD_CTRL_SGMII_PRBS_BERT_EN_BLEN                 1
+#define PORT0_PAD_CTRL_SGMII_PRBS_BERT_EN_FLAG                 HSL_RW
+
+#define SGMII_REM_PHY_LPBK_EN
+#define PORT0_PAD_CTRL_SGMII_REM_PHY_LPBK_EN_BOFFSET           15
+#define PORT0_PAD_CTRL_SGMII_REM_PHY_LPBK_EN_BLEN              1
+#define PORT0_PAD_CTRL_SGMII_REM_PHY_LPBK_EN_FLAG              HSL_RW
+
+#define MAC0_PHY_GMII_EN
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_BOFFSET                14
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_BLEN                   1
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_FLAG                   HSL_RW
+
+#define MAC0_PHY_GMII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_BOFFSET         13
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_BLEN            1
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_FLAG            HSL_RW
+
+#define MAC0_PHY_GMII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_BOFFSET         12
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_BLEN            1
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_FLAG            HSL_RW
+
+#define MAC0_PHY_MII_PIPE_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_BOFFSET     11
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_BLEN        1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_FLAG        HSL_RW
+
+#define MAC0_PHY_MII_EN
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_BOFFSET                 10
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_BLEN                    1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_FLAG                    HSL_RW
+
+#define MAC0_PHY_MII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_BOFFSET          9
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_BLEN             1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_FLAG             HSL_RW
+
+#define MAC0_PHY_MII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_BOFFSET          8
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_BLEN             1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_FLAG             HSL_RW
+
+#define MAC0_SGMII_EN
+#define PORT0_PAD_CTRL_MAC0_SGMII_EN_BOFFSET                   7
+#define PORT0_PAD_CTRL_MAC0_SGMII_EN_BLEN                      1
+#define PORT0_PAD_CTRL_MAC0_SGMII_EN_FLAG                      HSL_RW
+
+#define MAC0_MAC_GMII_EN
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_BOFFSET                6
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_BLEN                   1
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_FLAG                   HSL_RW
+
+#define MAC0_MAC_GMII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_BOFFSET         5
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_BLEN            1
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_FLAG            HSL_RW
+
+#define MAC0_MAC_GMII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_BOFFSET         4
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_BLEN            1
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_FLAG            HSL_RW
+
+#define MAC0_MAC_SGMII_FORCE_SPEED
+#define PORT0_PAD_CTRL_MAC0_MAC_SGMII_FORCE_SPEED_BOFFSET                 3
+#define PORT0_PAD_CTRL_MAC0_MAC_SGMII_FORCE_SPEED_BLEN                    1
+#define PORT0_PAD_CTRL_MAC0_MAC_SGMII_FORCE_SPEED_FLAG                    HSL_RW
+
+#define MAC0_MAC_MII_EN
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_BOFFSET                 2
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_BLEN                    1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_FLAG                    HSL_RW
+
+#define MAC0_MAC_MII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BOFFSET          1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BLEN             1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_FLAG             HSL_RW
+
+#define MAC0_MAC_MII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_BOFFSET          0
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_BLEN             1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_FLAG             HSL_RW
+
+
+
+
+    /* Port5 Pad Control Register */
+#define PORT5_PAD_CTRL
+#define PORT5_PAD_CTRL_ID                                      0
+#define PORT5_PAD_CTRL_OFFSET                                  0x0008
+#define PORT5_PAD_CTRL_E_LENGTH                                4
+#define PORT5_PAD_CTRL_E_OFFSET                                0
+#define PORT5_PAD_CTRL_NR_E                                    1
+
+#define MAC5_RGMII_EN
+#define PORT5_PAD_CTRL_MAC5_RGMII_EN_BOFFSET                   26
+#define PORT5_PAD_CTRL_MAC5_RGMII_EN_BLEN                      1
+#define PORT5_PAD_CTRL_MAC5_RGMII_EN_FLAG                      HSL_RW
+
+#define MAC5_RGMII_TXCLK_DELAY_EN
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_BOFFSET       25
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_BLEN          1
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_FLAG          HSL_RW
+
+#define MAC5_RGMII_RXCLK_DELAY_EN
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_BOFFSET       24
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_BLEN          1
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_FLAG          HSL_RW
+
+#define MAC5_RGMII_TXCLK_DELAY_SEL
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_BOFFSET      22
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_BLEN         2
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_FLAG         HSL_RW
+
+#define MAC5_RGMII_RXCLK_DELAY_SEL
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_BOFFSET      20
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_BLEN         2
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_FLAG         HSL_RW
+
+#define MAC5_PHY_MII_PIPE_RXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_BOFFSET     11
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_BLEN        1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_FLAG        HSL_RW
+
+#define MAC5_PHY_MII_EN
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_BOFFSET                 10
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_BLEN                    1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_FLAG                    HSL_RW
+
+#define MAC5_PHY_MII_TXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_BOFFSET          9
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_BLEN             1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_FLAG             HSL_RW
+
+#define MAC5_PHY_MII_RXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_BOFFSET          8
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_BLEN             1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_FLAG             HSL_RW
+
+#define MAC5_MAC_MII_EN
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_BOFFSET                 2
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_BLEN                    1
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_FLAG                    HSL_RW
+
+#define MAC5_MAC_MII_TXCLK_SEL
+#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BOFFSET          1
+#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BLEN             1
+#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_FLAG             HSL_RW
+
+#define MAC5_MAC_MII_RXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_BOFFSET          0
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_BLEN             1
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_FLAG             HSL_RW
+
+
+
+
+    /* Port6 Pad Control Register */
+#define PORT6_PAD_CTRL
+#define PORT6_PAD_CTRL_ID                                      0
+#define PORT6_PAD_CTRL_OFFSET                                  0x000c
+#define PORT6_PAD_CTRL_E_LENGTH                                4
+#define PORT6_PAD_CTRL_E_OFFSET                                0
+#define PORT6_PAD_CTRL_NR_E                                    1
+
+#define MAC6_RGMII_EN
+#define PORT6_PAD_CTRL_MAC6_RGMII_EN_BOFFSET                   26
+#define PORT6_PAD_CTRL_MAC6_RGMII_EN_BLEN                      1
+#define PORT6_PAD_CTRL_MAC6_RGMII_EN_FLAG                      HSL_RW
+
+#define MAC6_RGMII_TXCLK_DELAY_EN
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_BOFFSET       25
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_BLEN          1
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_FLAG          HSL_RW
+
+#define MAC6_RGMII_RXCLK_DELAY_EN
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_BOFFSET       24
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_BLEN          1
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_FLAG          HSL_RW
+
+#define MAC6_RGMII_TXCLK_DELAY_SEL
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_BOFFSET      22
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_BLEN         2
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_FLAG         HSL_RW
+
+#define MAC6_RGMII_RXCLK_DELAY_SEL
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_BOFFSET      20
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_BLEN         2
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_FLAG         HSL_RW
+
+#define PHY4_RGMII_EN
+#define PORT6_PAD_CTRL_PHY4_RGMII_EN_BOFFSET                   17
+#define PORT6_PAD_CTRL_PHY4_RGMII_EN_BLEN                      1
+#define PORT6_PAD_CTRL_PHY4_RGMII_EN_FLAG                      HSL_RW
+
+#define MAC6_PHY_GMII_EN
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_BOFFSET                14
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_BLEN                   1
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_FLAG                   HSL_RW
+
+#define MAC6_PHY_GMII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_BOFFSET         13
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_BLEN            1
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_FLAG            HSL_RW
+
+#define MAC6_PHY_GMII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_BOFFSET         12
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_BLEN            1
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_FLAG            HSL_RW
+
+#define MAC6_PHY_MII_PIPE_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_BOFFSET     11
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_BLEN        1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_FLAG        HSL_RW
+
+#define MAC6_PHY_MII_EN
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_BOFFSET                 10
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_BLEN                    1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_FLAG                    HSL_RW
+
+#define MAC6_PHY_MII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_BOFFSET          9
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_BLEN             1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_FLAG             HSL_RW
+
+#define MAC6_PHY_MII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_BOFFSET          8
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_BLEN             1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_FLAG             HSL_RW
+
+#define MAC6_SGMII_EN
+#define PORT6_PAD_CTRL_MAC6_SGMII_EN_BOFFSET                   7
+#define PORT6_PAD_CTRL_MAC6_SGMII_EN_BLEN                      1
+#define PORT6_PAD_CTRL_MAC6_SGMII_EN_FLAG                      HSL_RW
+
+#define MAC6_MAC_GMII_EN
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_BOFFSET                6
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_BLEN                   1
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_FLAG                   HSL_RW
+
+#define MAC6_MAC_GMII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_BOFFSET         5
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_BLEN            1
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_FLAG            HSL_RW
+
+#define MAC6_MAC_GMII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_BOFFSET         4
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_BLEN            1
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_FLAG            HSL_RW
+
+#define MAC6_MAC_MII_EN
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_BOFFSET                 2
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_BLEN                    1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_FLAG                    HSL_RW
+
+#define MAC6_MAC_MII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_BOFFSET          1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_BLEN             1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_FLAG             HSL_RW
+
+#define MAC6_MAC_MII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_BOFFSET          0
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_BLEN             1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_FLAG             HSL_RW
+
+
+
+
+    /* SGMII Control Register */
+#define SGMII_CTRL
+#define SGMII_CTRL_ID                                          0
+#define SGMII_CTRL_OFFSET                                      0x00e0
+#define SGMII_CTRL_E_LENGTH                                    4
+#define SGMII_CTRL_E_OFFSET                                    0
+#define SGMII_CTRL_NR_E                                        1
+
+#define FULL_25M
+#define SGMII_CTRL_FULL_25M_BOFFSET                            31
+#define SGMII_CTRL_FULL_25M_BLEN                               1
+#define SGMII_CTRL_FULL_25M_FLAG                               HSL_RW
+
+#define HALF_25M
+#define SGMII_CTRL_HALF_25M_BOFFSET                            30
+#define SGMII_CTRL_HALF_25M_BLEN                               1
+#define SGMII_CTRL_HALF_25M_FLAG                               HSL_RW
+
+#define REMOTE_25M
+#define SGMII_CTRL_REMOTE_25M_BOFFSET                          28
+#define SGMII_CTRL_REMOTE_25M_BLEN                             2
+#define SGMII_CTRL_REMOTE_25M_FLAG                             HSL_RW
+
+#define NEXT_PAGE_25M
+#define SGMII_CTRL_NEXT_PAGE_25M_BOFFSET                       27
+#define SGMII_CTRL_NEXT_PAGE_25M_BLEN                          1
+#define SGMII_CTRL_NEXT_PAGE_25M_FLAG                          HSL_RW
+
+#define PAUSE_25M
+#define SGMII_CTRL_PAUSE_25M_BOFFSET                           26
+#define SGMII_CTRL_PAUSE_25M_BLEN                              1
+#define SGMII_CTRL_PAUSE_25M_FLAG                              HSL_RW
+
+#define ASYM_PAUSE_25M
+#define SGMII_CTRL_ASYM_PAUSE_25M_BOFFSET                      25
+#define SGMII_CTRL_ASYM_PAUSE_25M_BLEN                         1
+#define SGMII_CTRL_ASYM_PAUSE_25M_FLAG                         HSL_RW
+
+#define PAUSE_SG_25M
+#define SGMII_CTRL_PAUSE_SG_25M_BOFFSET                        24
+#define SGMII_CTRL_PAUSE_SG_25M_BLEN                           1
+#define SGMII_CTRL_PAUSE_SG_25M_FLAG                           HSL_RW
+
+#define PAUSE_SG_25M
+#define SGMII_CTRL_PAUSE_SG_25M_BOFFSET                        24
+#define SGMII_CTRL_PAUSE_SG_25M_BLEN                           1
+#define SGMII_CTRL_PAUSE_SG_25M_FLAG                           HSL_RW
+
+#define MODE_CTRL_25M
+#define SGMII_CTRL_MODE_CTRL_25M_BOFFSET                       22
+#define SGMII_CTRL_MODE_CTRL_25M_BLEN                          2
+#define SGMII_CTRL_MODE_CTRL_25M_FLAG                          HSL_RW
+
+#define MR_LOOPBACK
+#define SGMII_CTRL_MR_LOOPBACK_BOFFSET                         21
+#define SGMII_CTRL_MR_LOOPBACK_BLEN                            1
+#define SGMII_CTRL_MR_LOOPBACK_FLAG                            HSL_RW
+
+#define MR_REG4_25M
+#define SGMII_CTRL_MR_REG4_25M_BOFFSET                         20
+#define SGMII_CTRL_MR_REG4_25M_BLEN                            1
+#define SGMII_CTRL_MR_REG4_25M_FLAG                            HSL_RW
+
+#define AUTO_LPI_25M
+#define SGMII_CTRL_AUTO_LPI_25M_BOFFSET                        19
+#define SGMII_CTRL_AUTO_LPI_25M_BLEN                           1
+#define SGMII_CTRL_AUTO_LPI_25M_FLAG                           HSL_RW
+
+#define PRBS_EN
+#define SGMII_CTRL_PRBS_EN_BOFFSET                             18
+#define SGMII_CTRL_PRBS_EN_BLEN                                1
+#define SGMII_CTRL_PRBS_EN_FLAG                                HSL_RW
+
+#define SGMII_TH_LOS1
+#define SGMII_CTRL_SGMII_TH_LOS1_BOFFSET                       17
+#define SGMII_CTRL_SGMII_TH_LOS1_BLEN                          1
+#define SGMII_CTRL_SGMII_TH_LOS1_FLAG                          HSL_RW
+
+#define DIS_AUTO_LPI_25M
+#define SGMII_CTRL_DIS_AUTO_LPI_25M_BOFFSET                    16
+#define SGMII_CTRL_DIS_AUTO_LPI_25M_BLEN                       1
+#define SGMII_CTRL_DIS_AUTO_LPI_25M_FLAG                       HSL_RW
+
+#define SGMII_TH_LOS0
+#define SGMII_CTRL_SGMII_TH_LOS0_BOFFSET                       15
+#define SGMII_CTRL_SGMII_TH_LOS0_BLEN                          1
+#define SGMII_CTRL_SGMII_TH_LOS0_FLAG                          HSL_RW
+
+#define SGMII_CDR_BW
+#define SGMII_CTRL_SGMII_CDR_BW_BOFFSET                        13
+#define SGMII_CTRL_SGMII_CDR_BW_BLEN                           2
+#define SGMII_CTRL_SGMII_CDR_BW_FLAG                           HSL_RW
+
+#define SGMII_TXDR_CTRL
+#define SGMII_CTRL_SGMII_TXDR_CTRL_BOFFSET                     10
+#define SGMII_CTRL_SGMII_TXDR_CTRL_BLEN                        3
+#define SGMII_CTRL_SGMII_TXDR_CTRL_FLAG                        HSL_RW
+
+#define SGMII_FIBER_MODE
+#define SGMII_CTRL_SGMII_FIBER_MODE_BOFFSET                    8
+#define SGMII_CTRL_SGMII_FIBER_MODE_BLEN                       2
+#define SGMII_CTRL_SGMII_FIBER_MODE_FLAG                       HSL_RW
+
+#define SGMII_SEL_125M
+#define SGMII_CTRL_SGMII_SEL_125M_BOFFSET                      7
+#define SGMII_CTRL_SGMII_SEL_125M_BLEN                         1
+#define SGMII_CTRL_SGMII_SEL_125M_FLAG                         HSL_RW
+
+#define SGMII_PLL_BW
+#define SGMII_CTRL_SGMII_PLL_BW_BOFFSET                        6
+#define SGMII_CTRL_SGMII_PLL_BW_BLEN                           1
+#define SGMII_CTRL_SGMII_PLL_BW_FLAG                           HSL_RW
+
+#define SGMII_HALFTX
+#define SGMII_CTRL_SGMII_HALFTX_BOFFSET                        5
+#define SGMII_CTRL_SGMII_HALFTX_BLEN                           1
+#define SGMII_CTRL_SGMII_HALFTX_FLAG                           HSL_RW
+
+#define SGMII_EN_SD
+#define SGMII_CTRL_SGMII_EN_SD_BOFFSET                         4
+#define SGMII_CTRL_SGMII_EN_SD_BLEN                            1
+#define SGMII_CTRL_SGMII_EN_SD_FLAG                            HSL_RW
+
+#define SGMII_EN_TX
+#define SGMII_CTRL_SGMII_EN_TX_BOFFSET                         3
+#define SGMII_CTRL_SGMII_EN_TX_BLEN                            1
+#define SGMII_CTRL_SGMII_EN_TX_FLAG                            HSL_RW
+
+#define SGMII_EN_RX
+#define SGMII_CTRL_SGMII_EN_RX_BOFFSET                         2
+#define SGMII_CTRL_SGMII_EN_RX_BLEN                            1
+#define SGMII_CTRL_SGMII_EN_RX_FLAG                            HSL_RW
+
+#define SGMII_EN_PLL
+#define SGMII_CTRL_SGMII_EN_PLL_BOFFSET                        1
+#define SGMII_CTRL_SGMII_EN_PLL_BLEN                           1
+#define SGMII_CTRL_SGMII_EN_PLL_FLAG                           HSL_RW
+
+#define SGMII_EN_LCKDT
+#define SGMII_CTRL_SGMII_EN_LCKDT_BOFFSET                      0
+#define SGMII_CTRL_SGMII_EN_LCKDT_BLEN                         1
+#define SGMII_CTRL_SGMII_EN_LCKDT_FLAG                         HSL_RW
+
+
+
+
+    /* Power On Strip Register */
+#define POWER_STRIP
+#define POWER_STRIP_ID                                         0
+#define POWER_STRIP_OFFSET                                     0x0010
+#define POWER_STRIP_E_LENGTH                                   4
+#define POWER_STRIP_E_OFFSET                                   0
+#define POWER_STRIP_NR_E                                       1
+
+#define POWER_ON_SEL
+#define POWER_STRIP_POWER_ON_SEL_BOFFSET                       31
+#define POWER_STRIP_POWER_ON_SEL_BLEN                          1
+#define POWER_STRIP_POWER_ON_SEL_FLAG                          HSL_RW
+
+#define PKG128_EN
+#define POWER_STRIP_PKG128_EN_BOFFSET                          30
+#define POWER_STRIP_PKG128_EN_BLEN                             1
+#define POWER_STRIP_PKG128_EN_FLAG                             HSL_RW
+
+#define PKG128_EN_LED
+#define POWER_STRIP_PKG128_EN_LED_BOFFSET                      29
+#define POWER_STRIP_PKG128_EN_LED_BLEN                         1
+#define POWER_STRIP_PKG128_EN_LED_FLAG                         HSL_RW
+
+#define S16_MODE
+#define POWER_STRIP_S16_MODE_BOFFSET                           28
+#define POWER_STRIP_S16_MODE_BLEN                              1
+#define POWER_STRIP_S16_MODE_FLAG                              HSL_RW
+
+#define INPUT_MODE
+#define POWER_STRIP_INPUT_MODE_BOFFSET                         27
+#define POWER_STRIP_INPUT_MODE_BLEN                            1
+#define POWER_STRIP_INPUT_MODE_FLAG                            HSL_RW
+
+#define SGMII_POWER_ON_SEL
+#define POWER_STRIP_SGMII_POWER_ON_SEL_BOFFSET                 26
+#define POWER_STRIP_SGMII_POWER_ON_SEL_BLEN                    1
+#define POWER_STRIP_SGMII_POWER_ON_SEL_FLAG                    HSL_RW
+
+#define SPI_EN
+#define POWER_STRIP_SPI_EN_BOFFSET                             25
+#define POWER_STRIP_SPI_EN_BLEN                                1
+#define POWER_STRIP_SPI_EN_FLAG                                HSL_RW
+
+#define LED_OPEN_EN
+#define POWER_STRIP_LED_OPEN_EN_BOFFSET                        24
+#define POWER_STRIP_LED_OPEN_EN_BLEN                           1
+#define POWER_STRIP_LED_OPEN_EN_FLAG                           HSL_RW
+
+#define SGMII_RXIMP_50_70
+#define POWER_STRIP_SGMII_RXIMP_50_70_BOFFSET                  23
+#define POWER_STRIP_SGMII_RXIMP_50_70_BLEN                     1
+#define POWER_STRIP_SGMII_RXIMP_50_70_FLAG                     HSL_RW
+
+#define SGMII_TXIMP_50_70
+#define POWER_STRIP_SGMII_TXIMP_50_70_BOFFSET                  22
+#define POWER_STRIP_SGMII_TXIMP_50_70_BLEN                     1
+#define POWER_STRIP_SGMII_TXIMP_50_70_FLAG                     HSL_RW
+
+#define SGMII_SIGNAL_DETECT
+#define POWER_STRIP_SGMII_SIGNAL_DETECT_BOFFSET                21
+#define POWER_STRIP_SGMII_SIGNAL_DETECT_BLEN                   1
+#define POWER_STRIP_SGMII_SIGNAL_DETECT_FLAG                   HSL_RW
+
+#define LPW_EXIT
+#define POWER_STRIP_LPW_EXIT_BOFFSET                           20
+#define POWER_STRIP_LPW_EXIT_BLEN                              1
+#define POWER_STRIP_LPW_EXIT_FLAG                              HSL_RW
+
+#define MAN_EN
+#define POWER_STRIP_MAN_EN_BOFFSET                             18
+#define POWER_STRIP_MAN_EN_BLEN                                1
+#define POWER_STRIP_MAN_EN_FLAG                                HSL_RW
+
+#define HIB_EN
+#define POWER_STRIP_HIB_EN_BOFFSET                             17
+#define POWER_STRIP_HIB_EN_BLEN                                1
+#define POWER_STRIP_HIB_EN_FLAG                                HSL_RW
+
+#define POWER_DOWN_HW
+#define POWER_STRIP_POWER_DOWN_HW_BOFFSET                      16
+#define POWER_STRIP_POWER_DOWN_HW_BLEN                         1
+#define POWER_STRIP_POWER_DOWN_HW_FLAG                         HSL_RW
+
+#define BIST_BYPASS_CEL
+#define POWER_STRIP_BIST_BYPASS_CEL_BOFFSET                    15
+#define POWER_STRIP_BIST_BYPASS_CEL_BLEN                       1
+#define POWER_STRIP_BIST_BYPASS_CEL_FLAG                       HSL_RW
+
+#define BIST_BYPASS_CSR
+#define POWER_STRIP_BIST_BYPASS_CSR_BOFFSET                    14
+#define POWER_STRIP_BIST_BYPASS_CSR_BLEN                       1
+#define POWER_STRIP_BIST_BYPASS_CSR_FLAG                       HSL_RW
+
+#define HIB_PULSE_HW
+#define POWER_STRIP_HIB_PULSE_HW_BOFFSET                       12
+#define POWER_STRIP_HIB_PULSE_HW_BLEN                          1
+#define POWER_STRIP_HIB_PULSE_HW_FLAG                          HSL_RW
+
+#define GATE_25M_EN
+#define POWER_STRIP_GATE_25M_EN_BOFFSET                        10
+#define POWER_STRIP_GATE_25M_EN_BLEN                           1
+#define POWER_STRIP_GATE_25M_EN_FLAG                           HSL_RW
+
+#define SEL_ANA_RST
+#define POWER_STRIP_SEL_ANA_RST_BOFFSET                        9
+#define POWER_STRIP_SEL_ANA_RST_BLEN                           1
+#define POWER_STRIP_SEL_ANA_RST_FLAG                           HSL_RW
+
+#define SERDES_EN
+#define POWER_STRIP_SERDES_EN_BOFFSET                          8
+#define POWER_STRIP_SERDES_EN_BLEN                             1
+#define POWER_STRIP_SERDES_EN_FLAG                             HSL_RW
+
+#define SERDES_AN_EN
+#define POWER_STRIP_SERDES_AN_EN_BOFFSET                       7
+#define POWER_STRIP_SERDES_AN_EN_BLEN                          1
+#define POWER_STRIP_SERDES_AN_EN_FLAG                          HSL_RW
+
+#define RTL_MODE
+#define POWER_STRIP_RTL_MODE_BOFFSET                           5
+#define POWER_STRIP_RTL_MODE_BLEN                              1
+#define POWER_STRIP_RTL_MODE_FLAG                              HSL_RW
+
+#define PAD_CTRL_FOR25M
+#define POWER_STRIP_PAD_CTRL_FOR25M_BOFFSET                    3
+#define POWER_STRIP_PAD_CTRL_FOR25M_BLEN                       2
+#define POWER_STRIP_PAD_CTRL_FOR25M_FLAG                       HSL_RW
+
+#define PAD_CTRL
+#define POWER_STRIP_PAD_CTRL_BOFFSET                           0
+#define POWER_STRIP_PAD_CTRL_BLEN                              2
+#define POWER_STRIP_PAD_CTRL_FLAG                              HSL_RW
+
+
+
+
+    /* Global Interrupt Status Register1 */
+#define GBL_INT_STATUS1
+#define GBL_INT_STATUS1_ID             1
+#define GBL_INT_STATUS1_OFFSET         0x0024
+#define GBL_INT_STATUS1_E_LENGTH       4
+#define GBL_INT_STATUS1_E_OFFSET       0
+#define GBL_INT_STATUS1_NR_E           1
+
+#define LINK_CHG_INT_S
+#define GBL_INT_STATUS1_LINK_CHG_INT_S_BOFFSET 1
+#define GBL_INT_STATUS1_LINK_CHG_INT_S_BLEN        7
+#define GBL_INT_STATUS1_LINK_CHG_INT_S_FLAG    HSL_RW
+
+#define PHY_INT_S
+#define GBL_INT_STATUS1_PHY_INT_S_BOFFSET         15
+#define GBL_INT_STATUS1_PHY_INT_S_BLEN            1
+#define GBL_INT_STATUS1_PHY_INT_S_FLAG            HSL_RO
+
+
+
+
+    /* Global Interrupt Mask Register1 */
+#define GBL_INT_MASK1
+#define GBL_INT_MASK1_ID             1
+#define GBL_INT_MASK1_OFFSET         0x002c
+#define GBL_INT_MASK1_E_LENGTH       4
+#define GBL_INT_MASK1_E_OFFSET       0
+#define GBL_INT_MASK1_NR_E           1
+
+#define LINK_CHG_INT_M
+#define GBL_INT_MASK1_LINK_CHG_INT_M_BOFFSET 1
+#define GBL_INT_MASK1_LINK_CHG_INT_M_BLEN        7
+#define GBL_INT_MASK1_LINK_CHG_INT_M_FLAG    HSL_RW
+
+#define PHY_INT_M
+#define GBL_INT_MASK1_PHY_INT_M_BOFFSET           15
+#define GBL_INT_MASK1_PHY_INT_M_BLEN              1
+#define GBL_INT_MASK1_PHY_INT_M_FLAG              HSL_RO
+
+
+
+
+    /* Module Enable Register */
+#define MOD_ENABLE
+#define MOD_ENABLE_OFFSET           0x0030
+#define MOD_ENABLE_E_LENGTH         4
+#define MOD_ENABLE_E_OFFSET         0
+#define MOD_ENABLE_NR_E             1
+
+#define L3_EN
+#define MOD_ENABLE_L3_EN_BOFFSET                  2
+#define MOD_ENABLE_L3_EN_BLEN                     1
+#define MOD_ENABLE_L3_EN_FLAG                     HSL_RW
+
+#define ACL_EN
+#define MOD_ENABLE_ACL_EN_BOFFSET                 1
+#define MOD_ENABLE_ACL_EN_BLEN                    1
+#define MOD_ENABLE_ACL_EN_FLAG                    HSL_RW
+
+#define MIB_EN
+#define MOD_ENABLE_MIB_EN_BOFFSET                 0
+#define MOD_ENABLE_MIB_EN_BLEN                    1
+#define MOD_ENABLE_MIB_EN_FLAG                    HSL_RW
+
+
+
+
+    /* MIB Function Register */
+#define MIB_FUNC
+#define MIB_FUNC_OFFSET           0x0034
+#define MIB_FUNC_E_LENGTH         4
+#define MIB_FUNC_E_OFFSET         0
+#define MIB_FUNC_NR_E             1
+
+#define MIB_FUN
+#define MIB_FUNC_MIB_FUN_BOFFSET               24
+#define MIB_FUNC_MIB_FUN_BLEN                  3
+#define MIB_FUNC_MIB_FUN_FLAG                  HSL_RW
+
+#define MIB_FLUSH_PORT
+#define MIB_FUNC_MIB_FLUSH_PORT_BOFFSET        21
+#define MIB_FUNC_MIB_FLUSH_PORT_BLEN            3
+#define MIB_FUNC_MIB_FLUSH_PORT_FLAG          HSL_RW
+
+#define MIB_CPU_KEEP
+#define MIB_FUNC_MIB_CPU_KEEP_BOFFSET     20
+#define MIB_FUNC_MIB_CPU_KEEP_BLEN          1
+#define MIB_FUNC_MIB_CPU_KEEP_FLAG         HSL_RW
+
+#define MIB_BUSY
+#define MIB_FUNC_MIB_BUSY_BOFFSET              17
+#define MIB_FUNC_MIB_BUSY_BLEN                 1
+#define MIB_FUNC_MIB_BUSY_FLAG                 HSL_RW
+
+#define MIB_AT_HALF_EN
+#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET        16
+#define MIB_FUNC_MIB_AT_HALF_EN_BLEN           1
+#define MIB_FUNC_MIB_AT_HALF_EN_FLAG           HSL_RW
+
+#define MIB_TIMER
+#define MIB_FUNC_MIB_TIMER_BOFFSET             0
+#define MIB_FUNC_MIB_TIMER_BLEN                16
+#define MIB_FUNC_MIB_TIMER_FLAG                HSL_RW
+
+
+
+
+    /* Service tag Register */
+#define SERVICE_TAG
+#define SERVICE_TAG_OFFSET           0x0048
+#define SERVICE_TAG_E_LENGTH         4
+#define SERVICE_TAG_E_OFFSET         0
+#define SERVICE_TAG_NR_E             1
+
+#define STAG_MODE
+#define SERVICE_TAG_STAG_MODE_BOFFSET    17
+#define SERVICE_TAG_STAG_MODE_BLEN       1
+#define SERVICE_TAG_STAG_MODE_FLAG       HSL_RW
+
+#define TAG_VALUE
+#define SERVICE_TAG_TAG_VALUE_BOFFSET    0
+#define SERVICE_TAG_TAG_VALUE_BLEN       16
+#define SERVICE_TAG_TAG_VALUE_FLAG       HSL_RW
+
+
+
+
+    /* Global MAC Address Register */
+#define GLOBAL_MAC_ADDR0
+#define GLOBAL_MAC_ADDR0_OFFSET    0x0060
+#define GLOBAL_MAC_ADDR0_E_LENGTH  4
+#define GLOBAL_MAC_ADDR0_E_OFFSET  0
+#define GLOBAL_MAC_ADDR0_NR_E      1
+
+#define GLB_BYTE4
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET         8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN            8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG            HSL_RW
+
+#define GLB_BYTE5
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET         0
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN            8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG            HSL_RW
+
+#define GLOBAL_MAC_ADDR1
+#define GLOBAL_MAC_ADDR1_ID        4
+#define GLOBAL_MAC_ADDR1_OFFSET    0x0064
+#define GLOBAL_MAC_ADDR1_E_LENGTH  4
+#define GLOBAL_MAC_ADDR1_E_OFFSET  0
+#define GLOBAL_MAC_ADDR1_NR_E      1
+
+#define GLB_BYTE0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET         24
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG            HSL_RW
+
+#define GLB_BYTE1
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET         16
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG            HSL_RW
+
+#define GLB_BYTE2
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET         8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG            HSL_RW
+
+#define GLB_BYTE3
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET         0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG            HSL_RW
+
+
+
+
+    /* Max Size Register */
+#define MAX_SIZE
+#define MAX_SIZE_OFFSET        0x0078
+#define MAX_SIZE_E_LENGTH      4
+#define MAX_SIZE_E_OFFSET      0
+#define MAX_SIZE_NR_E          1
+
+#define MAX_FRAME_SIZE
+#define MAX_SIZE_MAX_FRAME_SIZE_BOFFSET     0
+#define MAX_SIZE_MAX_FRAME_SIZE_BLEN        14
+#define MAX_SIZE_MAX_FRAME_SIZE_FLAG        HSL_RW
+
+
+
+
+    /* Flow Control Register */
+#define FLOW_CTL0                  "fctl"
+#define FLOW_CTL0_ID               6
+#define FLOW_CTL0_OFFSET           0x0034
+#define FLOW_CTL0_E_LENGTH         4
+#define FLOW_CTL0_E_OFFSET         0
+#define FLOW_CTL0_NR_E             1
+
+#define TEST_PAUSE                             "fctl_tps"
+#define FLOW_CTL0_TEST_PAUSE_BOFFSET           31
+#define FLOW_CTL0_TEST_PAUSE_BLEN              1
+#define FLOW_CTL0_TEST_PAUSE_FLAG              HSL_RW
+
+
+#define GOL_PAUSE_ON_THRES                     "fctl_gont"
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BOFFSET   16
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BLEN      8
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_FLAG      HSL_RW
+
+#define GOL_PAUSE_OFF_THRES                    "fctl_gofft"
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BOFFSET  0
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BLEN     8
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_FLAG     HSL_RW
+
+
+
+
+    /* Flow Control1 Register */
+#define FLOW_CTL1                  "fctl1"
+#define FLOW_CTL1_ID               6
+#define FLOW_CTL1_OFFSET           0x0038
+#define FLOW_CTL1_E_LENGTH         4
+#define FLOW_CTL1_E_OFFSET         0
+#define FLOW_CTL1_NR_E             1
+
+#define PORT_PAUSE_ON_THRES                    "fctl1_pont"
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BOFFSET  16
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BLEN     8
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_FLAG     HSL_RW
+
+#define PORT_PAUSE_OFF_THRES                   "fctl1_pofft"
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BOFFSET 0
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BLEN    8
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_FLAG    HSL_RW
+
+
+
+
+    /* Port Status Register */
+#define PORT_STATUS
+#define PORT_STATUS_OFFSET        0x007c
+#define PORT_STATUS_E_LENGTH      4
+#define PORT_STATUS_E_OFFSET      0x0004
+#define PORT_STATUS_NR_E          7
+
+#define FLOW_LINK_EN
+#define PORT_STATUS_FLOW_LINK_EN_BOFFSET        12
+#define PORT_STATUS_FLOW_LINK_EN_BLEN           1
+#define PORT_STATUS_FLOW_LINK_EN_FLAG           HSL_RW
+
+#define AUTO_RX_FLOW
+#define PORT_STATUS_AUTO_RX_FLOW_BOFFSET        11
+#define PORT_STATUS_AUTO_RX_FLOW_BLEN           1
+#define PORT_STATUS_AUTO_RX_FLOW_FLAG           HSL_RO
+
+#define AUTO_TX_FLOW
+#define PORT_STATUS_AUTO_TX_FLOW_BOFFSET        10
+#define PORT_STATUS_AUTO_TX_FLOW_BLEN           1
+#define PORT_STATUS_AUTO_TX_FLOW_FLAG           HSL_RO
+
+#define LINK_EN
+#define PORT_STATUS_LINK_EN_BOFFSET             9
+#define PORT_STATUS_LINK_EN_BLEN                1
+#define PORT_STATUS_LINK_EN_FLAG                HSL_RW
+
+#define LINK
+#define PORT_STATUS_LINK_BOFFSET                8
+#define PORT_STATUS_LINK_BLEN                   1
+#define PORT_STATUS_LINK_FLAG                   HSL_RO
+
+#define TX_HALF_FLOW_EN
+#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET     7
+#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN        1
+#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG        HSL_RW
+
+#define DUPLEX_MODE
+#define PORT_STATUS_DUPLEX_MODE_BOFFSET         6
+#define PORT_STATUS_DUPLEX_MODE_BLEN            1
+#define PORT_STATUS_DUPLEX_MODE_FLAG            HSL_RW
+
+#define RX_FLOW_EN
+#define PORT_STATUS_RX_FLOW_EN_BOFFSET          5
+#define PORT_STATUS_RX_FLOW_EN_BLEN             1
+#define PORT_STATUS_RX_FLOW_EN_FLAG             HSL_RW
+
+#define TX_FLOW_EN
+#define PORT_STATUS_TX_FLOW_EN_BOFFSET          4
+#define PORT_STATUS_TX_FLOW_EN_BLEN             1
+#define PORT_STATUS_TX_FLOW_EN_FLAG             HSL_RW
+
+#define RXMAC_EN
+#define PORT_STATUS_RXMAC_EN_BOFFSET            3
+#define PORT_STATUS_RXMAC_EN_BLEN               1
+#define PORT_STATUS_RXMAC_EN_FLAG               HSL_RW
+
+#define TXMAC_EN
+#define PORT_STATUS_TXMAC_EN_BOFFSET            2
+#define PORT_STATUS_TXMAC_EN_BLEN               1
+#define PORT_STATUS_TXMAC_EN_FLAG               HSL_RW
+
+#define SPEED_MODE
+#define PORT_STATUS_SPEED_MODE_BOFFSET          0
+#define PORT_STATUS_SPEED_MODE_BLEN             2
+#define PORT_STATUS_SPEED_MODE_FLAG             HSL_RW
+
+
+
+
+    /* Header Ctl Register */
+#define HEADER_CTL
+#define HEADER_CTL_OFFSET        0x0098
+#define HEADER_CTL_E_LENGTH      4
+#define HEADER_CTL_E_OFFSET      0x0004
+#define HEADER_CTL_NR_E          1
+
+#define TYPE_LEN
+#define HEADER_CTL_TYPE_LEN_BOFFSET          16
+#define HEADER_CTL_TYPE_LEN_BLEN             1
+#define HEADER_CTL_TYPE_LEN_FLAG             HSL_RW
+
+#define TYPE_VAL
+#define HEADER_CTL_TYPE_VAL_BOFFSET         0
+#define HEADER_CTL_TYPE_VAL_BLEN            16
+#define HEADER_CTL_TYPE_VAL_FLAG            HSL_RW
+
+
+
+
+    /* Port Header Ctl Register */
+#define PORT_HDR_CTL
+#define PORT_HDR_CTL_OFFSET        0x009c
+#define PORT_HDR_CTL_E_LENGTH      4
+#define PORT_HDR_CTL_E_OFFSET      0x0004
+#define PORT_HDR_CTL_NR_E          7
+
+#define IPG_DEC_EN
+#define PORT_HDR_CTL_IPG_DEC_EN_BOFFSET          5
+#define PORT_HDR_CTL_IPG_DEC_EN_BLEN             1
+#define PORT_HDR_CTL_IPG_DEC_EN_FLAG             HSL_RW
+
+#define LOOPBACK_EN
+#define PORT_HDR_CTL_LOOPBACK_EN_BOFFSET         4
+#define PORT_HDR_CTL_LOOPBACK_EN_BLEN            1
+#define PORT_HDR_CTL_LOOPBACK_EN_FLAG            HSL_RW
+
+#define RXHDR_MODE
+#define PORT_HDR_CTL_RXHDR_MODE_BOFFSET          2
+#define PORT_HDR_CTL_RXHDR_MODE_BLEN             2
+#define PORT_HDR_CTL_RXHDR_MODE_FLAG             HSL_RW
+
+#define TXHDR_MODE
+#define PORT_HDR_CTL_TXHDR_MODE_BOFFSET          0
+#define PORT_HDR_CTL_TXHDR_MODE_BLEN             2
+#define PORT_HDR_CTL_TXHDR_MODE_FLAG             HSL_RW
+
+
+
+
+    /* EEE control Register */
+#define EEE_CTL
+#define EEE_CTL_OFFSET    0x0100
+#define EEE_CTL_E_LENGTH  4
+#define EEE_CTL_E_OFFSET  0
+#define EEE_CTL_NR_E      1
+
+#define LPI_STATE_REMAP_EN_5
+#define EEE_CTL_LPI_STATE_REMAP_EN_5_BOFFSET                   13
+#define EEE_CTL_LPI_STATE_REMAP_EN_5_BLEN                      1
+#define EEE_CTL_LPI_STATE_REMAP_EN_5_FLAG                      HSL_RW
+
+#define LPI_EN_5
+#define EEE_CTL_LPI_EN_5_BOFFSET                               12
+#define EEE_CTL_LPI_EN_5_BLEN                                  1
+#define EEE_CTL_LPI_EN_5_FLAG                                  HSL_RW
+
+#define LPI_STATE_REMAP_EN_4
+#define EEE_CTL_LPI_STATE_REMAP_EN_4_BOFFSET                   11
+#define EEE_CTL_LPI_STATE_REMAP_EN_4_BLEN                      1
+#define EEE_CTL_LPI_STATE_REMAP_EN_4_FLAG                      HSL_RW
+
+#define LPI_EN_4
+#define EEE_CTL_LPI_EN_4_BOFFSET                               10
+#define EEE_CTL_LPI_EN_4_BLEN                                  1
+#define EEE_CTL_LPI_EN_4_FLAG                                  HSL_RW
+
+#define LPI_STATE_REMAP_EN_3
+#define EEE_CTL_LPI_STATE_REMAP_EN_3_BOFFSET                   9
+#define EEE_CTL_LPI_STATE_REMAP_EN_3_BLEN                      1
+#define EEE_CTL_LPI_STATE_REMAP_EN_3_FLAG                      HSL_RW
+
+#define LPI_EN_3
+#define EEE_CTL_LPI_EN_3_BOFFSET                               8
+#define EEE_CTL_LPI_EN_3_BLEN                                  1
+#define EEE_CTL_LPI_EN_3_FLAG                                  HSL_RW
+
+#define LPI_STATE_REMAP_EN_2
+#define EEE_CTL_LPI_STATE_REMAP_EN_2_BOFFSET                   7
+#define EEE_CTL_LPI_STATE_REMAP_EN_2_BLEN                      1
+#define EEE_CTL_LPI_STATE_REMAP_EN_2_FLAG                      HSL_RW
+
+#define LPI_EN_2
+#define EEE_CTL_LPI_EN_2_BOFFSET                               6
+#define EEE_CTL_LPI_EN_2_BLEN                                  1
+#define EEE_CTL_LPI_EN_2_FLAG                                  HSL_RW
+
+#define LPI_STATE_REMAP_EN_1
+#define EEE_CTL_LPI_STATE_REMAP_EN_1_BOFFSET                   5
+#define EEE_CTL_LPI_STATE_REMAP_EN_1_BLEN                      1
+#define EEE_CTL_LPI_STATE_REMAP_EN_1_FLAG                      HSL_RW
+
+#define LPI_EN_1
+#define EEE_CTL_LPI_EN_1_BOFFSET                               4
+#define EEE_CTL_LPI_EN_1_BLEN                                  1
+#define EEE_CTL_LPI_EN_1_FLAG                                  HSL_RW
+
+
+
+
+    /* Frame Ack Ctl0 Register */
+#define FRAME_ACK_CTL0
+#define FRAME_ACK_CTL0_OFFSET    0x0210
+#define FRAME_ACK_CTL0_E_LENGTH  4
+#define FRAME_ACK_CTL0_E_OFFSET  0
+#define FRAME_ACK_CTL0_NR_E      1
+
+#define ARP_REQ_EN
+#define FRAME_ACK_CTL0_ARP_REQ_EN_BOFFSET             6
+#define FRAME_ACK_CTL0_ARP_REQ_EN_BLEN                1
+#define FRAME_ACK_CTL0_ARP_REQ_EN_FLAG                HSL_RW
+
+#define ARP_REP_EN
+#define FRAME_ACK_CTL0_ARP_REP_EN_BOFFSET             5
+#define FRAME_ACK_CTL0_ARP_REP_EN_BLEN                1
+#define FRAME_ACK_CTL0_ARP_REP_EN_FLAG                HSL_RW
+
+#define DHCP_EN
+#define FRAME_ACK_CTL0_DHCP_EN_BOFFSET                4
+#define FRAME_ACK_CTL0_DHCP_EN_BLEN                   1
+#define FRAME_ACK_CTL0_DHCP_EN_FLAG                   HSL_RW
+
+#define EAPOL_EN
+#define FRAME_ACK_CTL0_EAPOL_EN_BOFFSET               3
+#define FRAME_ACK_CTL0_EAPOL_EN_BLEN                  1
+#define FRAME_ACK_CTL0_EAPOL_EN_FLAG                  HSL_RW
+
+#define LEAVE_EN
+#define FRAME_ACK_CTL0_LEAVE_EN_BOFFSET               2
+#define FRAME_ACK_CTL0_LEAVE_EN_BLEN                  1
+#define FRAME_ACK_CTL0_LEAVE_EN_FLAG                  HSL_RW
+
+#define JOIN_EN
+#define FRAME_ACK_CTL0_JOIN_EN_BOFFSET                1
+#define FRAME_ACK_CTL0_JOIN_EN_BLEN                   1
+#define FRAME_ACK_CTL0_JOIN_EN_FLAG                   HSL_RW
+
+#define IGMP_MLD_EN
+#define FRAME_ACK_CTL0_IGMP_MLD_EN_BOFFSET            0
+#define FRAME_ACK_CTL0_IGMP_MLD_EN_BLEN               1
+#define FRAME_ACK_CTL0_IGMP_MLD_EN_FLAG               HSL_RW
+
+
+
+
+    /* Frame Ack Ctl1 Register */
+#define FRAME_ACK_CTL1
+#define FRAME_ACK_CTL1_OFFSET    0x0214
+#define FRAME_ACK_CTL1_E_LENGTH  4
+#define FRAME_ACK_CTL1_E_OFFSET  0
+#define FRAME_ACK_CTL1_NR_E      1
+
+#define PPPOE_EN
+#define FRAME_ACK_CTL1_PPPOE_EN_BOFFSET               25
+#define FRAME_ACK_CTL1_PPPOE_EN_BLEN                  1
+#define FRAME_ACK_CTL1_PPPOE_EN_FLAG                  HSL_RW
+
+#define IGMP_V3_EN
+#define FRAME_ACK_CTL1_IGMP_V3_EN_BOFFSET             24
+#define FRAME_ACK_CTL1_IGMP_V3_EN_BLEN                1
+#define FRAME_ACK_CTL1_IGMP_V3_EN_FLAG                HSL_RW
+
+
+
+
+    /* Window Rule Ctl0 Register */
+#define WIN_RULE_CTL0
+#define WIN_RULE_CTL0_OFFSET               0x0218
+#define WIN_RULE_CTL0_E_LENGTH             4
+#define WIN_RULE_CTL0_E_OFFSET             0x4
+#define WIN_RULE_CTL0_NR_E                 7
+
+#define L4_LENGTH
+#define WIN_RULE_CTL0_L4_LENGTH_BOFFSET    24
+#define WIN_RULE_CTL0_L4_LENGTH_BLEN       4
+#define WIN_RULE_CTL0_L4_LENGTH_FLAG       HSL_RW
+
+#define L3_LENGTH
+#define WIN_RULE_CTL0_L3_LENGTH_BOFFSET    20
+#define WIN_RULE_CTL0_L3_LENGTH_BLEN       4
+#define WIN_RULE_CTL0_L3_LENGTH_FLAG       HSL_RW
+
+#define L2_LENGTH
+#define WIN_RULE_CTL0_L2_LENGTH_BOFFSET    16
+#define WIN_RULE_CTL0_L2_LENGTH_BLEN       4
+#define WIN_RULE_CTL0_L2_LENGTH_FLAG       HSL_RW
+
+#define L4_OFFSET
+#define WIN_RULE_CTL0_L4_OFFSET_BOFFSET    10
+#define WIN_RULE_CTL0_L4_OFFSET_BLEN       5
+#define WIN_RULE_CTL0_L4_OFFSET_FLAG       HSL_RW
+
+#define L3_OFFSET
+#define WIN_RULE_CTL0_L3_OFFSET_BOFFSET    5
+#define WIN_RULE_CTL0_L3_OFFSET_BLEN       5
+#define WIN_RULE_CTL0_L3_OFFSET_FLAG       HSL_RW
+
+#define L2_OFFSET
+#define WIN_RULE_CTL0_L2_OFFSET_BOFFSET    0
+#define WIN_RULE_CTL0_L2_OFFSET_BLEN       5
+#define WIN_RULE_CTL0_L2_OFFSET_FLAG       HSL_RW
+
+
+
+
+    /* Window Rule Ctl1 Register */
+#define WIN_RULE_CTL1
+#define WIN_RULE_CTL1_OFFSET               0x0234
+#define WIN_RULE_CTL1_E_LENGTH             4
+#define WIN_RULE_CTL1_E_OFFSET             0x4
+#define WIN_RULE_CTL1_NR_E                 7
+
+#define L3P_LENGTH
+#define WIN_RULE_CTL1_L3P_LENGTH_BOFFSET   20
+#define WIN_RULE_CTL1_L3P_LENGTH_BLEN      4
+#define WIN_RULE_CTL1_L3P_LENGTH_FLAG      HSL_RW
+
+#define L2S_LENGTH
+#define WIN_RULE_CTL1_L2S_LENGTH_BOFFSET   16
+#define WIN_RULE_CTL1_L2S_LENGTH_BLEN      4
+#define WIN_RULE_CTL1_L2S_LENGTH_FLAG      HSL_RW
+
+#define L3P_OFFSET
+#define WIN_RULE_CTL1_L3P_OFFSET_BOFFSET   5
+#define WIN_RULE_CTL1_L3P_OFFSET_BLEN      5
+#define WIN_RULE_CTL1_L3P_OFFSET_FLAG      HSL_RW
+
+#define L2S_OFFSET
+#define WIN_RULE_CTL1_L2S_OFFSET_BOFFSET   0
+#define WIN_RULE_CTL1_L2S_OFFSET_BLEN      5
+#define WIN_RULE_CTL1_L2S_OFFSET_FLAG      HSL_RW
+
+
+
+
+    /* Trunk Hash Mode Register */
+#define TRUNK_HASH_MODE
+#define TRUNK_HASH_MODE_OFFSET               0x0270
+#define TRUNK_HASH_MODE_E_LENGTH             4
+#define TRUNK_HASH_MODE_E_OFFSET             0x4
+#define TRUNK_HASH_MODE_NR_E                 1
+
+#define SIP_EN
+#define TRUNK_HASH_MODE_SIP_EN_BOFFSET       3
+#define TRUNK_HASH_MODE_SIP_EN_BLEN          1
+#define TRUNK_HASH_MODE_SIP_EN_FLAG          HSL_RW
+
+#define DIP_EN
+#define TRUNK_HASH_MODE_DIP_EN_BOFFSET       2
+#define TRUNK_HASH_MODE_DIP_EN_BLEN          1
+#define TRUNK_HASH_MODE_DIP_EN_FLAG          HSL_RW
+
+#define SA_EN
+#define TRUNK_HASH_MODE_SA_EN_BOFFSET        1
+#define TRUNK_HASH_MODE_SA_EN_BLEN           1
+#define TRUNK_HASH_MODE_SA_EN_FLAG           HSL_RW
+
+#define DA_EN
+#define TRUNK_HASH_MODE_DA_EN_BOFFSET        0
+#define TRUNK_HASH_MODE_DA_EN_BLEN           1
+#define TRUNK_HASH_MODE_DA_EN_FLAG           HSL_RW
+
+
+
+
+    /* Vlan Table Function0 Register */
+#define VLAN_TABLE_FUNC0
+#define VLAN_TABLE_FUNC0_OFFSET    0x0610
+#define VLAN_TABLE_FUNC0_E_LENGTH  4
+#define VLAN_TABLE_FUNC0_E_OFFSET  0
+#define VLAN_TABLE_FUNC0_NR_E      1
+
+#define VT_VALID
+#define VLAN_TABLE_FUNC0_VT_VALID_BOFFSET      20
+#define VLAN_TABLE_FUNC0_VT_VALID_BLEN         1
+#define VLAN_TABLE_FUNC0_VT_VALID_FLAG         HSL_RW
+
+#define IVL_EN
+#define VLAN_TABLE_FUNC0_IVL_EN_BOFFSET        19
+#define VLAN_TABLE_FUNC0_IVL_EN_BLEN           1
+#define VLAN_TABLE_FUNC0_IVL_EN_FLAG           HSL_RW
+
+#define LEARN_DIS
+#define VLAN_TABLE_FUNC0_LEARN_DIS_BOFFSET     18
+#define VLAN_TABLE_FUNC0_LEARN_DIS_BLEN        1
+#define VLAN_TABLE_FUNC0_LEARN_DIS_FLAG        HSL_RW
+
+#define VID_MEM
+#define VLAN_TABLE_FUNC0_VID_MEM_BOFFSET       4
+#define VLAN_TABLE_FUNC0_VID_MEM_BLEN          14
+#define VLAN_TABLE_FUNC0_VID_MEM_FLAG          HSL_RW
+
+#define VT_PRI_EN
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET     3
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN        1
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG        HSL_RW
+
+#define VT_PRI
+#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET        0
+#define VLAN_TABLE_FUNC0_VT_PRI_BLEN           3
+#define VLAN_TABLE_FUNC0_VT_PRI_FLAG           HSL_RW
+
+    /* Vlan Table Function1 Register */
+#define VLAN_TABLE_FUNC1
+#define VLAN_TABLE_FUNC1_OFFSET    0x0614
+#define VLAN_TABLE_FUNC1_E_LENGTH  4
+#define VLAN_TABLE_FUNC1_E_OFFSET  0
+#define VLAN_TABLE_FUNC1_NR_E      1
+
+#define VT_BUSY
+#define VLAN_TABLE_FUNC1_VT_BUSY_BOFFSET       31
+#define VLAN_TABLE_FUNC1_VT_BUSY_BLEN          1
+#define VLAN_TABLE_FUNC1_VT_BUSY_FLAG          HSL_RW
+
+#define VLAN_ID
+#define VLAN_TABLE_FUNC1_VLAN_ID_BOFFSET       16
+#define VLAN_TABLE_FUNC1_VLAN_ID_BLEN          12
+#define VLAN_TABLE_FUNC1_VLAN_ID_FLAG          HSL_RW
+
+#define VT_PORT_NUM
+#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BOFFSET   8
+#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BLEN      4
+#define VLAN_TABLE_FUNC1_VT_PORT_NUM_FLAG      HSL_RW
+
+#define VT_FULL_VIO
+#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BOFFSET   4
+#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BLEN      1
+#define VLAN_TABLE_FUNC1_VT_FULL_VIO_FLAG      HSL_RW
+
+#define VT_FUNC
+#define VLAN_TABLE_FUNC1_VT_FUNC_BOFFSET       0
+#define VLAN_TABLE_FUNC1_VT_FUNC_BLEN          3
+#define VLAN_TABLE_FUNC1_VT_FUNC_FLAG          HSL_RW
+
+
+
+
+    /* Address Table Function0 Register */
+#define ADDR_TABLE_FUNC0
+#define ADDR_TABLE_FUNC0_OFFSET    0x0600
+#define ADDR_TABLE_FUNC0_E_LENGTH  4
+#define ADDR_TABLE_FUNC0_E_OFFSET  0
+#define ADDR_TABLE_FUNC0_NR_E      1
+
+
+#define AT_ADDR_BYTE2
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BOFFSET 24
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE3
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BOFFSET 16
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE4
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE5
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 0
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG    HSL_RW
+
+    /* Address Table Function1 Register */
+#define ADDR_TABLE_FUNC1
+#define ADDR_TABLE_FUNC1_OFFSET    0x0604
+#define ADDR_TABLE_FUNC1_E_LENGTH  4
+#define ADDR_TABLE_FUNC1_E_OFFSET  0
+#define ADDR_TABLE_FUNC1_NR_E      1
+
+#define SA_DROP_EN
+#define ADDR_TABLE_FUNC1_SA_DROP_EN_BOFFSET    30
+#define ADDR_TABLE_FUNC1_SA_DROP_EN_BLEN       1
+#define ADDR_TABLE_FUNC1_SA_DROP_EN_FLAG       HSL_RW
+
+#define MIRROR_EN
+#define ADDR_TABLE_FUNC1_MIRROR_EN_BOFFSET     29
+#define ADDR_TABLE_FUNC1_MIRROR_EN_BLEN        1
+#define ADDR_TABLE_FUNC1_MIRROR_EN_FLAG        HSL_RW
+
+#define AT_PRI_EN
+#define ADDR_TABLE_FUNC1_AT_PRI_EN_BOFFSET     28
+#define ADDR_TABLE_FUNC1_AT_PRI_EN_BLEN        1
+#define ADDR_TABLE_FUNC1_AT_PRI_EN_FLAG        HSL_RW
+
+#define AT_SVL_EN
+#define ADDR_TABLE_FUNC1_AT_SVL_EN_BOFFSET     27
+#define ADDR_TABLE_FUNC1_AT_SVL_EN_BLEN        1
+#define ADDR_TABLE_FUNC1_AT_SVL_EN_FLAG        HSL_RW
+
+#define AT_PRI
+#define ADDR_TABLE_FUNC1_AT_PRI_BOFFSET        24
+#define ADDR_TABLE_FUNC1_AT_PRI_BLEN           3
+#define ADDR_TABLE_FUNC1_AT_PRI_FLAG           HSL_RW
+
+#define CROSS_PT
+#define ADDR_TABLE_FUNC1_CROSS_PT_BOFFSET      23
+#define ADDR_TABLE_FUNC1_CROSS_PT_BLEN         1
+#define ADDR_TABLE_FUNC1_CROSS_PT_FLAG         HSL_RW
+
+#define DES_PORT
+#define ADDR_TABLE_FUNC1_DES_PORT_BOFFSET      16
+#define ADDR_TABLE_FUNC1_DES_PORT_BLEN         7
+#define ADDR_TABLE_FUNC1_DES_PORT_FLAG         HSL_RW
+
+#define AT_ADDR_BYTE0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE1
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG    HSL_RW
+
+    /* Address Table Function2 Register */
+#define ADDR_TABLE_FUNC2
+#define ADDR_TABLE_FUNC2_OFFSET    0x0608
+#define ADDR_TABLE_FUNC2_E_LENGTH  4
+#define ADDR_TABLE_FUNC2_E_OFFSET  0
+#define ADDR_TABLE_FUNC2_NR_E      1
+
+#define WL_EN
+#define ADDR_TABLE_FUNC2_WL_EN_BOFFSET         20
+#define ADDR_TABLE_FUNC2_WL_EN_BLEN            1
+#define ADDR_TABLE_FUNC2_WL_EN_FLAG            HSL_RW
+
+#define AT_VID
+#define ADDR_TABLE_FUNC2_AT_VID_BOFFSET        8
+#define ADDR_TABLE_FUNC2_AT_VID_BLEN           12
+#define ADDR_TABLE_FUNC2_AT_VID_FLAG           HSL_RW
+
+#define SHORT_LOOP
+#define ADDR_TABLE_FUNC2_SHORT_LOOP_BOFFSET    7
+#define ADDR_TABLE_FUNC2_SHORT_LOOP_BLEN       1
+#define ADDR_TABLE_FUNC2_SHORT_LOOP_FLAG       HSL_RW
+
+#define COPY_TO_CPU
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET   6
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN      1
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG      HSL_RW
+
+#define REDRCT_TO_CPU
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 5
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN    1
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG    HSL_RW
+
+#define LEAKY_EN
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET      4
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN         1
+#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG         HSL_RW
+
+#define AT_STATUS
+#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET     0
+#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN        4
+#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG        HSL_RW
+
+    /* Address Table Function3 Register */
+#define ADDR_TABLE_FUNC3
+#define ADDR_TABLE_FUNC3_OFFSET    0x060c
+#define ADDR_TABLE_FUNC3_E_LENGTH  4
+#define ADDR_TABLE_FUNC3_E_OFFSET  0
+#define ADDR_TABLE_FUNC3_NR_E      1
+
+#define AT_BUSY
+#define ADDR_TABLE_FUNC3_AT_BUSY_BOFFSET       31
+#define ADDR_TABLE_FUNC3_AT_BUSY_BLEN          1
+#define ADDR_TABLE_FUNC3_AT_BUSY_FLAG          HSL_RW
+
+#define NEW_PORT_NUM
+#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BOFFSET  22
+#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BLEN     3
+#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_FLAG     HSL_RW
+
+#define AT_INDEX
+#define ADDR_TABLE_FUNC3_AT_INDEX_BOFFSET      16
+#define ADDR_TABLE_FUNC3_AT_INDEX_BLEN         5
+#define ADDR_TABLE_FUNC3_AT_INDEX_FLAG         HSL_RW
+
+#define AT_VID_EN
+#define ADDR_TABLE_FUNC3_AT_VID_EN_BOFFSET     15
+#define ADDR_TABLE_FUNC3_AT_VID_EN_BLEN        1
+#define ADDR_TABLE_FUNC3_AT_VID_EN_FLAG        HSL_RW
+
+#define AT_PORT_EN
+#define ADDR_TABLE_FUNC3_AT_PORT_EN_BOFFSET    14
+#define ADDR_TABLE_FUNC3_AT_PORT_EN_BLEN       1
+#define ADDR_TABLE_FUNC3_AT_PORT_EN_FLAG       HSL_RW
+
+#define AT_MULTI_EN
+#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BOFFSET   13
+#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BLEN      1
+#define ADDR_TABLE_FUNC3_AT_MULTI_EN_FLAG      HSL_RW
+
+#define AT_FULL_VIO
+#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BOFFSET   12
+#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BLEN      1
+#define ADDR_TABLE_FUNC3_AT_FULL_VIO_FLAG      HSL_RW
+
+#define AT_PORT_NUM
+#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BOFFSET   8
+#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BLEN      4
+#define ADDR_TABLE_FUNC3_AT_PORT_NUM_FLAG      HSL_RW
+
+#define FLUSH_ST_EN
+#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BOFFSET   4
+#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BLEN      1
+#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_FLAG      HSL_RW
+
+#define AT_FUNC
+#define ADDR_TABLE_FUNC3_AT_FUNC_BOFFSET       0
+#define ADDR_TABLE_FUNC3_AT_FUNC_BLEN          4
+#define ADDR_TABLE_FUNC3_AT_FUNC_FLAG          HSL_RW
+
+
+
+
+    /* Reserve Address Table0 Register */
+#define RESV_ADDR_TBL0
+#define RESV_ADDR_TBL0_OFFSET    0x3c000
+#define RESV_ADDR_TBL0_E_LENGTH  4
+#define RESV_ADDR_TBL0_E_OFFSET  0
+#define RESV_ADDR_TBL0_NR_E      1
+
+#define RESV_ADDR_BYTE2
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BOFFSET 24
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BLEN    8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_FLAG    HSL_RW
+
+#define RESV_ADDR_BYTE3
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BOFFSET 16
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BLEN    8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_FLAG    HSL_RW
+
+#define RESV_ADDR_BYTE4
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BOFFSET 8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BLEN    8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_FLAG    HSL_RW
+
+#define RESV_ADDR_BYTE5
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BOFFSET 0
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BLEN    8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_FLAG    HSL_RW
+
+    /* Reserve Address Table1 Register */
+#define RESV_ADDR_TBL1
+#define RESV_ADDR_TBL1_OFFSET    0x3c004
+#define RESV_ADDR_TBL1_E_LENGTH  4
+#define RESV_ADDR_TBL1_E_OFFSET  0
+#define RESV_ADDR_TBL1_NR_E      1
+
+#define RESV_COPY_TO_CPU
+#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BOFFSET   31
+#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BLEN      1
+#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_FLAG      HSL_RW
+
+#define RESV_REDRCT_TO_CPU
+#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BOFFSET 30
+#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BLEN    1
+#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_FLAG    HSL_RW
+
+#define RESV_LEAKY_EN
+#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BOFFSET      29
+#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BLEN         1
+#define RESV_ADDR_TBL1_RESV_LEAKY_EN_FLAG         HSL_RW
+
+#define RESV_MIRROR_EN
+#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BOFFSET     28
+#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BLEN        1
+#define RESV_ADDR_TBL1_RESV_MIRROR_EN_FLAG        HSL_RW
+
+#define RESV_PRI_EN
+#define RESV_ADDR_TBL1_RESV_PRI_EN_BOFFSET     27
+#define RESV_ADDR_TBL1_RESV_PRI_EN_BLEN        1
+#define RESV_ADDR_TBL1_RESV_PRI_EN_FLAG        HSL_RW
+
+#define RESV_PRI
+#define RESV_ADDR_TBL1_RESV_PRI_BOFFSET        24
+#define RESV_ADDR_TBL1_RESV_PRI_BLEN           3
+#define RESV_ADDR_TBL1_RESV_PRI_FLAG           HSL_RW
+
+#define RESV_CROSS_PT
+#define RESV_ADDR_TBL1_RESV_CROSS_PT_BOFFSET      23
+#define RESV_ADDR_TBL1_RESV_CROSS_PT_BLEN         1
+#define RESV_ADDR_TBL1_RESV_CROSS_PT_FLAG         HSL_RW
+
+#define RESV_DES_PORT
+#define RESV_ADDR_TBL1_RESV_DES_PORT_BOFFSET      16
+#define RESV_ADDR_TBL1_RESV_DES_PORT_BLEN         7
+#define RESV_ADDR_TBL1_RESV_DES_PORT_FLAG         HSL_RW
+
+#define RESV_ADDR_BYTE0
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BOFFSET 8
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BLEN    8
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_FLAG    HSL_RW
+
+#define RESV_ADDR_BYTE1
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BOFFSET 0
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BLEN    8
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_FLAG    HSL_RW
+
+    /* Reserve Address Table2 Register */
+#define RESV_ADDR_TBL2
+#define RESV_ADDR_TBL2_OFFSET    0x3c008
+#define RESV_ADDR_TBL2_E_LENGTH  4
+#define RESV_ADDR_TBL2_E_OFFSET  0
+#define RESV_ADDR_TBL2_NR_E      1
+
+#define RESV_STATUS
+#define RESV_ADDR_TBL2_RESV_STATUS_BOFFSET     0
+#define RESV_ADDR_TBL2_RESV_STATUS_BLEN        1
+#define RESV_ADDR_TBL2_RESV_STATUS_FLAG        HSL_RW
+
+
+
+
+    /* Address Table Control Register */
+#define ADDR_TABLE_CTL
+#define ADDR_TABLE_CTL_OFFSET     0x0618
+#define ADDR_TABLE_CTL_E_LENGTH   4
+#define ADDR_TABLE_CTL_E_OFFSET   0
+#define ADDR_TABLE_CTL_NR_E       1
+
+#define ARL_INI_EN
+#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET        31
+#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN           1
+#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG           HSL_RW
+
+#define LEARN_CHANGE_EN
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET   30
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN      1
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG      HSL_RW
+
+#define IGMP_JOIN_LEAKY
+#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BOFFSET   29
+#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BLEN      1
+#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_FLAG      HSL_RW
+
+#define IGMP_CREAT_EN
+#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BOFFSET     28
+#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BLEN        1
+#define ADDR_TABLE_CTL_IGMP_CREAT_EN_FLAG        HSL_RW
+
+#define IGMP_PRI_EN
+#define ADDR_TABLE_CTL_IGMP_PRI_EN_BOFFSET       27
+#define ADDR_TABLE_CTL_IGMP_PRI_EN_BLEN          1
+#define ADDR_TABLE_CTL_IGMP_PRI_EN_FLAG          HSL_RW
+
+#define IGMP_PRI
+#define ADDR_TABLE_CTL_IGMP_PRI_BOFFSET          24
+#define ADDR_TABLE_CTL_IGMP_PRI_BLEN             3
+#define ADDR_TABLE_CTL_IGMP_PRI_FLAG             HSL_RW
+
+#define IGMP_JOIN_STATIC
+#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BOFFSET  20
+#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BLEN     4
+#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_FLAG     HSL_RW
+
+#define AGE_EN
+#define ADDR_TABLE_CTL_AGE_EN_BOFFSET            19
+#define ADDR_TABLE_CTL_AGE_EN_BLEN               1
+#define ADDR_TABLE_CTL_AGE_EN_FLAG               HSL_RW
+
+#define LOOP_CHECK_TIMER
+#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BOFFSET  16
+#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BLEN     3
+#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_FLAG     HSL_RW
+
+#define AGE_TIME
+#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET          0
+#define ADDR_TABLE_CTL_AGE_TIME_BLEN             16
+#define ADDR_TABLE_CTL_AGE_TIME_FLAG             HSL_RW
+
+
+
+
+    /* Global Forward Control0 Register */
+#define FORWARD_CTL0
+#define FORWARD_CTL0_OFFSET             0x0620
+#define FORWARD_CTL0_E_LENGTH           4
+#define FORWARD_CTL0_E_OFFSET           0
+#define FORWARD_CTL0_NR_E               1
+
+#define ARP_CMD
+#define FORWARD_CTL0_ARP_CMD_BOFFSET                26
+#define FORWARD_CTL0_ARP_CMD_BLEN                   2
+#define FORWARD_CTL0_ARP_CMD_FLAG                   HSL_RW
+
+#define IP_NOT_FOUND
+#define FORWARD_CTL0_IP_NOT_FOUND_BOFFSET           24
+#define FORWARD_CTL0_IP_NOT_FOUND_BLEN              2
+#define FORWARD_CTL0_IP_NOT_FOUND_FLAG              HSL_RW
+
+#define ARP_NOT_FOUND
+#define FORWARD_CTL0_ARP_NOT_FOUND_BOFFSET          22
+#define FORWARD_CTL0_ARP_NOT_FOUND_BLEN             2
+#define FORWARD_CTL0_ARP_NOT_FOUND_FLAG             HSL_RW
+
+#define HASH_MODE
+#define FORWARD_CTL0_HASH_MODE_BOFFSET              20
+#define FORWARD_CTL0_HASH_MODE_BLEN                 2
+#define FORWARD_CTL0_HASH_MODE_FLAG                 HSL_RW
+
+#define NAT_NOT_FOUND_DROP
+#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BOFFSET     17
+#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BLEN        1
+#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_FLAG        HSL_RW
+
+#define SP_NOT_FOUND_DROP
+#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BOFFSET      16
+#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BLEN         1
+#define FORWARD_CTL0_SP_NOT_FOUND_DROP_FLAG         HSL_RW
+
+#define IGMP_LEAVE_DROP
+#define FORWARD_CTL0_IGMP_LEAVE_DROP_BOFFSET        14
+#define FORWARD_CTL0_IGMP_LEAVE_DROP_BLEN           1
+#define FORWARD_CTL0_IGMP_LEAVE_DROP_FLAG           HSL_RW
+
+#define ARL_UNI_LEAKY
+#define FORWARD_CTL0_ARL_UNI_LEAKY_BOFFSET          13
+#define FORWARD_CTL0_ARL_UNI_LEAKY_BLEN             1
+#define FORWARD_CTL0_ARL_UNI_LEAKY_FLAG             HSL_RW
+
+#define ARL_MUL_LEAKY
+#define FORWARD_CTL0_ARL_MUL_LEAKY_BOFFSET          12
+#define FORWARD_CTL0_ARL_MUL_LEAKY_BLEN             1
+#define FORWARD_CTL0_ARL_MUL_LEAKY_FLAG             HSL_RW
+
+#define MANAGE_VID_VIO_DROP_EN
+#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BOFFSET 11
+#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BLEN    1
+#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_FLAG    HSL_RW
+
+#define CPU_PORT_EN
+#define FORWARD_CTL0_CPU_PORT_EN_BOFFSET            10
+#define FORWARD_CTL0_CPU_PORT_EN_BLEN               1
+#define FORWARD_CTL0_CPU_PORT_EN_FLAG               HSL_RW
+
+#define PPPOE_RDT_EN
+#define FORWARD_CTL0_PPPOE_RDT_EN_BOFFSET           8
+#define FORWARD_CTL0_PPPOE_RDT_EN_BLEN              1
+#define FORWARD_CTL0_PPPOE_RDT_EN_FLAG              HSL_RW
+
+#define MIRROR_PORT_NUM
+#define FORWARD_CTL0_MIRROR_PORT_NUM_BOFFSET        4
+#define FORWARD_CTL0_MIRROR_PORT_NUM_BLEN           4
+#define FORWARD_CTL0_MIRROR_PORT_NUM_FLAG           HSL_RW
+
+#define IGMP_COPY_EN
+#define FORWARD_CTL0_IGMP_COPY_EN_BOFFSET           3
+#define FORWARD_CTL0_IGMP_COPY_EN_BLEN              1
+#define FORWARD_CTL0_IGMP_COPY_EN_FLAG              HSL_RW
+
+#define RIP_CPY_EN
+#define FORWARD_CTL0_RIP_CPY_EN_BOFFSET             2
+#define FORWARD_CTL0_RIP_CPY_EN_BLEN                1
+#define FORWARD_CTL0_RIP_CPY_EN_FLAG                HSL_RW
+
+#define EAPOL_CMD
+#define FORWARD_CTL0_EAPOL_CMD_BOFFSET              0
+#define FORWARD_CTL0_EAPOL_CMD_BLEN                 1
+#define FORWARD_CTL0_EAPOL_CMD_FLAG                 HSL_RW
+
+    /* Global Forward Control1 Register */
+#define FORWARD_CTL1
+#define FORWARD_CTL1_OFFSET             0x0624
+#define FORWARD_CTL1_E_LENGTH           4
+#define FORWARD_CTL1_E_OFFSET           0
+#define FORWARD_CTL1_NR_E               1
+
+#define IGMP_DP
+#define FORWARD_CTL1_IGMP_DP_BOFFSET          24
+#define FORWARD_CTL1_IGMP_DP_BLEN             7
+#define FORWARD_CTL1_IGMP_DP_FLAG             HSL_RW
+
+#define BC_FLOOD_DP
+#define FORWARD_CTL1_BC_FLOOD_DP_BOFFSET      16
+#define FORWARD_CTL1_BC_FLOOD_DP_BLEN         7
+#define FORWARD_CTL1_BC_FLOOD_DP_FLAG         HSL_RW
+
+#define MUL_FLOOD_DP
+#define FORWARD_CTL1_MUL_FLOOD_DP_BOFFSET     8
+#define FORWARD_CTL1_MUL_FLOOD_DP_BLEN        7
+#define FORWARD_CTL1_MUL_FLOOD_DP_FLAG        HSL_RW
+
+#define UNI_FLOOD_DP
+#define FORWARD_CTL1_UNI_FLOOD_DP_BOFFSET     0
+#define FORWARD_CTL1_UNI_FLOOD_DP_BLEN        7
+#define FORWARD_CTL1_UNI_FLOOD_DP_FLAG        HSL_RW
+
+
+
+
+    /* Global Learn Limit Ctl Register */
+#define GLOBAL_LEARN_LIMIT_CTL
+#define GLOBAL_LEARN_LIMIT_CTL_OFFSET            0x0628
+#define GLOBAL_LEARN_LIMIT_CTL_E_LENGTH          4
+#define GLOBAL_LEARN_LIMIT_CTL_E_OFFSET          0
+#define GLOBAL_LEARN_LIMIT_CTL_NR_E              1
+
+#define GOL_SA_LEARN_LIMIT_EN
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BOFFSET          12
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BLEN             1
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_FLAG             HSL_RW
+
+#define GOL_SA_LEARN_LIMIT_DROP_EN
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BOFFSET     13
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BLEN        1
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_FLAG        HSL_RW
+
+#define GOL_SA_LEARN_CNT
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BOFFSET               0
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BLEN                  12
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_FLAG                  HSL_RW
+
+
+
+
+    /* DSCP To Priority Register */
+#define DSCP_TO_PRI
+#define DSCP_TO_PRI_OFFSET     0x0630
+#define DSCP_TO_PRI_E_LENGTH   4
+#define DSCP_TO_PRI_E_OFFSET   0x0004
+#define DSCP_TO_PRI_NR_E       8
+
+
+
+
+    /* UP To Priority Register */
+#define UP_TO_PRI
+#define UP_TO_PRI_OFFSET     0x0650
+#define UP_TO_PRI_E_LENGTH   4
+#define UP_TO_PRI_E_OFFSET   0x0004
+#define UP_TO_PRI_NR_E       1
+
+
+
+
+    /* Port Lookup control Register */
+#define PORT_LOOKUP_CTL
+#define PORT_LOOKUP_CTL_OFFSET     0x0660
+#define PORT_LOOKUP_CTL_E_LENGTH   4
+#define PORT_LOOKUP_CTL_E_OFFSET   0x000c
+#define PORT_LOOKUP_CTL_NR_E       7
+
+#define MULTI_DROP_EN
+#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BOFFSET    31
+#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BLEN       1
+#define PORT_LOOKUP_CTL_MULTI_DROP_EN_FLAG       HSL_RW
+
+#define UNI_LEAKY_EN
+#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BOFFSET     28
+#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BLEN        1
+#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_FLAG        HSL_RW
+
+#define MUL_LEAKY_EN
+#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BOFFSET     27
+#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BLEN        1
+#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_FLAG        HSL_RW
+
+#define ARP_LEAKY_EN
+#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BOFFSET     26
+#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BLEN        1
+#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_FLAG        HSL_RW
+
+#define ING_MIRROR_EN
+#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BOFFSET    25
+#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BLEN       1
+#define PORT_LOOKUP_CTL_ING_MIRROR_EN_FLAG       HSL_RW
+
+#define PORT_LOOP_BACK
+#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BOFFSET   21
+#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BLEN      1
+#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_FLAG      HSL_RW
+
+#define LEARN_EN
+#define PORT_LOOKUP_CTL_LEARN_EN_BOFFSET         20
+#define PORT_LOOKUP_CTL_LEARN_EN_BLEN            1
+#define PORT_LOOKUP_CTL_LEARN_EN_FLAG            HSL_RW
+
+#define PORT_STATE
+#define PORT_LOOKUP_CTL_PORT_STATE_BOFFSET       16
+#define PORT_LOOKUP_CTL_PORT_STATE_BLEN          3
+#define PORT_LOOKUP_CTL_PORT_STATE_FLAG          HSL_RW
+
+#define FORCE_PVLAN
+#define PORT_LOOKUP_CTL_FORCE_PVLAN_BOFFSET      10
+#define PORT_LOOKUP_CTL_FORCE_PVLAN_BLEN         1
+#define PORT_LOOKUP_CTL_FORCE_PVLAN_FLAG         HSL_RW
+
+#define DOT1Q_MODE
+#define PORT_LOOKUP_CTL_DOT1Q_MODE_BOFFSET       8
+#define PORT_LOOKUP_CTL_DOT1Q_MODE_BLEN          2
+#define PORT_LOOKUP_CTL_DOT1Q_MODE_FLAG          HSL_RW
+
+#define PORT_VID_MEM
+#define PORT_LOOKUP_CTL_PORT_VID_MEM_BOFFSET     0
+#define PORT_LOOKUP_CTL_PORT_VID_MEM_BLEN        7
+#define PORT_LOOKUP_CTL_PORT_VID_MEM_FLAG        HSL_RW
+
+
+
+
+    /* Priority Control Register */
+#define PRI_CTL
+#define PRI_CTL_OFFSET            0x0664
+#define PRI_CTL_E_LENGTH          4
+#define PRI_CTL_E_OFFSET          0x000c
+#define PRI_CTL_NR_E              7
+
+#define EG_MAC_BASE_VLAN_EN
+#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BOFFSET     20
+#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BLEN        1
+#define PRI_CTL_EG_MAC_BASE_VLAN_EN_FLAG        HSL_RW
+
+#define DA_PRI_EN
+#define PRI_CTL_DA_PRI_EN_BOFFSET               18
+#define PRI_CTL_DA_PRI_EN_BLEN                  1
+#define PRI_CTL_DA_PRI_EN_FLAG                  HSL_RW
+
+#define VLAN_PRI_EN
+#define PRI_CTL_VLAN_PRI_EN_BOFFSET             17
+#define PRI_CTL_VLAN_PRI_EN_BLEN                1
+#define PRI_CTL_VLAN_PRI_EN_FLAG                HSL_RW
+
+#define IP_PRI_EN
+#define PRI_CTL_IP_PRI_EN_BOFFSET               16
+#define PRI_CTL_IP_PRI_EN_BLEN                  1
+#define PRI_CTL_IP_PRI_EN_FLAG                  HSL_RW
+
+#define DA_PRI_SEL
+#define PRI_CTL_DA_PRI_SEL_BOFFSET              6
+#define PRI_CTL_DA_PRI_SEL_BLEN                 2
+#define PRI_CTL_DA_PRI_SEL_FLAG                 HSL_RW
+
+#define VLAN_PRI_SEL
+#define PRI_CTL_VLAN_PRI_SEL_BOFFSET            4
+#define PRI_CTL_VLAN_PRI_SEL_BLEN               2
+#define PRI_CTL_VLAN_PRI_SEL_FLAG               HSL_RW
+
+#define IP_PRI_SEL
+#define PRI_CTL_IP_PRI_SEL_BOFFSET              2
+#define PRI_CTL_IP_PRI_SEL_BLEN                 2
+#define PRI_CTL_IP_PRI_SEL_FLAG                 HSL_RW
+
+
+
+    /* Port Learn Limit Ctl Register */
+#define PORT_LEARN_LIMIT_CTL
+#define PORT_LEARN_LIMIT_CTL_OFFSET            0x0668
+#define PORT_LEARN_LIMIT_CTL_E_LENGTH          4
+#define PORT_LEARN_LIMIT_CTL_E_OFFSET          0x000c
+#define PORT_LEARN_LIMIT_CTL_NR_E              7
+
+#define IGMP_JOIN_LIMIT_DROP_EN
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BOFFSET    29
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BLEN       1
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_FLAG       HSL_RW
+
+#define SA_LEARN_LIMIT_DROP_EN
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BOFFSET     28
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BLEN        1
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_FLAG        HSL_RW
+
+#define IGMP_JOIN_LIMIT_EN
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BOFFSET         27
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BLEN            1
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_FLAG            HSL_RW
+
+#define IGMP_JOIN_CNT
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BOFFSET              16
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BLEN                 11
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_FLAG                 HSL_RW
+
+#define SA_LEARN_STATUS
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BOFFSET            12
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BLEN               4
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_FLAG               HSL_RW
+
+#define SA_LEARN_LIMIT_EN
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BOFFSET          11
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BLEN             1
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_FLAG             HSL_RW
+
+#define SA_LEARN_CNT
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BOFFSET               0
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BLEN                  11
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_FLAG                  HSL_RW
+
+
+
+    /* Global Trunk Ctl0 Register */
+#define GOL_TRUNK_CTL0
+#define GOL_TRUNK_CTL0_OFFSET               0x0700
+#define GOL_TRUNK_CTL0_E_LENGTH             4
+#define GOL_TRUNK_CTL0_E_OFFSET             0x4
+#define GOL_TRUNK_CTL0_NR_E                 1
+
+
+    /* Global Trunk Ctl1 Register */
+#define GOL_TRUNK_CTL1
+#define GOL_TRUNK_CTL1_OFFSET               0x0704
+#define GOL_TRUNK_CTL1_E_LENGTH             4
+#define GOL_TRUNK_CTL1_E_OFFSET             0x4
+#define GOL_TRUNK_CTL1_NR_E                 2
+
+
+    /* ACL Forward source filter Register */
+#define ACL_FWD_SRC_FILTER_CTL0
+#define ACL_FWD_SRC_FILTER_CTL0_OFFSET               0x0710
+#define ACL_FWD_SRC_FILTER_CTL0_E_LENGTH             4
+#define ACL_FWD_SRC_FILTER_CTL0_E_OFFSET             0x4
+#define ACL_FWD_SRC_FILTER_CTL0_NR_E                 3
+
+
+    /* VLAN translation register */
+#define VLAN_TRANS
+#define VLAN_TRANS_OFFSET     0x0418
+#define VLAN_TRANS_E_LENGTH   4
+#define VLAN_TRANS_E_OFFSET   0
+#define VLAN_TRANS_NR_E       7
+
+#define EG_FLTR_BYPASS_EN
+#define VLAN_TRANS_EG_FLTR_BYPASS_EN_BOFFSET     1
+#define VLAN_TRANS_EG_FLTR_BYPASS_EN_BLEN        1
+#define VLAN_TRANS_EG_FLTR_BYPASS_EN_FLAG        HSL_RW
+
+#define NET_ISO
+#define VLAN_TRANS_NET_ISO_BOFFSET       0
+#define VLAN_TRANS_NET_ISO_BLEN          1
+#define VLAN_TRANS_NET_ISO_FLAG          HSL_RW
+
+
+    /* Port vlan0 Register */
+#define PORT_VLAN0
+#define PORT_VLAN0_OFFSET     0x0420
+#define PORT_VLAN0_E_LENGTH   4
+#define PORT_VLAN0_E_OFFSET   0x0008
+#define PORT_VLAN0_NR_E       7
+
+#define ING_CPRI
+#define PORT_VLAN0_ING_CPRI_BOFFSET       29
+#define PORT_VLAN0_ING_CPRI_BLEN          3
+#define PORT_VLAN0_ING_CPRI_FLAG          HSL_RW
+
+#define ING_FORCE_CPRI
+#define PORT_VLAN0_ING_FORCE_CPRI_BOFFSET       28
+#define PORT_VLAN0_ING_FORCE_CPRI_BLEN          1
+#define PORT_VLAN0_ING_FORCE_CPRI_FLAG          HSL_RW
+
+#define DEF_CVID
+#define PORT_VLAN0_DEF_CVID_BOFFSET       16
+#define PORT_VLAN0_DEF_CVID_BLEN          12
+#define PORT_VLAN0_DEF_CVID_FLAG          HSL_RW
+
+#define ING_SPRI
+#define PORT_VLAN0_ING_SPRI_BOFFSET       13
+#define PORT_VLAN0_ING_SPRI_BLEN          3
+#define PORT_VLAN0_ING_SPRI_FLAG          HSL_RW
+
+#define ING_FORCE_SPRI
+#define PORT_VLAN0_ING_FORCE_SPRI_BOFFSET       12
+#define PORT_VLAN0_ING_FORCE_SPRI_BLEN          1
+#define PORT_VLAN0_ING_FORCE_SPRI_FLAG          HSL_RW
+
+#define DEF_SVID
+#define PORT_VLAN0_DEF_SVID_BOFFSET       0
+#define PORT_VLAN0_DEF_SVID_BLEN          12
+#define PORT_VLAN0_DEF_SVID_FLAG          HSL_RW
+
+    /* Port vlan1 Register */
+#define PORT_VLAN1
+#define PORT_VLAN1_OFFSET     0x0424
+#define PORT_VLAN1_E_LENGTH   4
+#define PORT_VLAN1_E_OFFSET   0x0008
+#define PORT_VLAN1_NR_E       7
+
+#define EG_VLAN_MODE
+#define PORT_VLAN1_EG_VLAN_MODE_BOFFSET   12
+#define PORT_VLAN1_EG_VLAN_MODE_BLEN      2
+#define PORT_VLAN1_EG_VLAN_MODE_FLAG      HSL_RW
+
+#define VLAN_DIS
+#define PORT_VLAN1_VLAN_DIS_BOFFSET       11
+#define PORT_VLAN1_VLAN_DIS_BLEN          1
+#define PORT_VLAN1_VLAN_DIS_FLAG          HSL_RW
+
+#define SP_CHECK_EN
+#define PORT_VLAN1_SP_CHECK_EN_BOFFSET    10
+#define PORT_VLAN1_SP_CHECK_EN_BLEN       1
+#define PORT_VLAN1_SP_CHECK_EN_FLAG       HSL_RW
+
+#define COREP_EN
+#define PORT_VLAN1_COREP_EN_BOFFSET       9
+#define PORT_VLAN1_COREP_EN_BLEN          1
+#define PORT_VLAN1_COREP_EN_FLAG          HSL_RW
+
+#define FORCE_DEF_VID
+#define PORT_VLAN1_FORCE_DEF_VID_BOFFSET  8
+#define PORT_VLAN1_FORCE_DEF_VID_BLEN     1
+#define PORT_VLAN1_FORCE_DEF_VID_FLAG     HSL_RW
+
+#define TLS_EN
+#define PORT_VLAN1_TLS_EN_BOFFSET         7
+#define PORT_VLAN1_TLS_EN_BLEN            1
+#define PORT_VLAN1_TLS_EN_FLAG            HSL_RW
+
+#define PROPAGATION_EN
+#define PORT_VLAN1_PROPAGATION_EN_BOFFSET 6
+#define PORT_VLAN1_PROPAGATION_EN_BLEN    1
+#define PORT_VLAN1_PROPAGATION_EN_FLAG    HSL_RW
+
+#define CLONE
+#define PORT_VLAN1_CLONE_BOFFSET          5
+#define PORT_VLAN1_CLONE_BLEN             1
+#define PORT_VLAN1_CLONE_FLAG             HSL_RW
+
+#define PRI_PROPAGATION
+#define PORT_VLAN1_PRI_PROPAGATION_BOFFSET   4
+#define PORT_VLAN1_PRI_PROPAGATION_BLEN      1
+#define PORT_VLAN1_VLAN_PRI_PROPAGATION_FLAG HSL_RW
+
+#define IN_VLAN_MODE
+#define PORT_VLAN1_IN_VLAN_MODE_BOFFSET      2
+#define PORT_VLAN1_IN_VLAN_MODE_BLEN         2
+#define PORT_VLAN1_IN_VLAN_MODE_FLAG         HSL_RW
+
+
+    /* Route Default VID Register */
+#define ROUTER_DEFV
+#define ROUTER_DEFV_OFFSET     0x0c70
+#define ROUTER_DEFV_E_LENGTH   4
+#define ROUTER_DEFV_E_OFFSET   0x0004
+#define ROUTER_DEFV_NR_E       4
+
+
+    /* Route Egress VLAN Mode Register */
+#define ROUTER_EG
+#define ROUTER_EG_OFFSET     0x0c80
+#define ROUTER_EG_E_LENGTH   4
+#define ROUTER_EG_E_OFFSET   0x0004
+#define ROUTER_EG_NR_E       1
+
+
+
+
+    /* Mdio control Register */
+#define MDIO_CTRL               "mctrl"
+#define MDIO_CTRL_ID            24
+#define MDIO_CTRL_OFFSET        0x0098
+#define MDIO_CTRL_E_LENGTH      4
+#define MDIO_CTRL_E_OFFSET      0
+#define MDIO_CTRL_NR_E          1
+
+#define MSTER_EN                        "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET      30
+#define MDIO_CTRL_MSTER_EN_BLEN         1
+#define MDIO_CTRL_MSTER_EN_FLAG         HSL_RW
+
+#define MSTER_EN                        "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET      30
+#define MDIO_CTRL_MSTER_EN_BLEN         1
+#define MDIO_CTRL_MSTER_EN_FLAG         HSL_RW
+
+#define CMD                             "mctrl_cmd"
+#define MDIO_CTRL_CMD_BOFFSET           27
+#define MDIO_CTRL_CMD_BLEN              1
+#define MDIO_CTRL_CMD_FLAG              HSL_RW
+
+#define SUP_PRE                         "mctrl_spre"
+#define MDIO_CTRL_SUP_PRE_BOFFSET       26
+#define MDIO_CTRL_SUP_PRE_BLEN          1
+#define MDIO_CTRL_SUP_PRE_FLAG          HSL_RW
+
+#define PHY_ADDR                        "mctrl_phyaddr"
+#define MDIO_CTRL_PHY_ADDR_BOFFSET      21
+#define MDIO_CTRL_PHY_ADDR_BLEN         5
+#define MDIO_CTRL_PHY_ADDR_FLAG         HSL_RW
+
+#define REG_ADDR                        "mctrl_regaddr"
+#define MDIO_CTRL_REG_ADDR_BOFFSET      16
+#define MDIO_CTRL_REG_ADDR_BLEN         5
+#define MDIO_CTRL_REG_ADDR_FLAG         HSL_RW
+
+#define DATA                            "mctrl_data"
+#define MDIO_CTRL_DATA_BOFFSET          0
+#define MDIO_CTRL_DATA_BLEN             16
+#define MDIO_CTRL_DATA_FLAG             HSL_RW
+
+
+
+
+    /* BIST control Register */
+#define BIST_CTRL               "bctrl"
+#define BIST_CTRL_ID            24
+#define BIST_CTRL_OFFSET        0x00a0
+#define BIST_CTRL_E_LENGTH      4
+#define BIST_CTRL_E_OFFSET      0
+#define BIST_CTRL_NR_E          1
+
+#define BIST_BUSY                        "bctrl_bb"
+#define BIST_CTRL_BIST_BUSY_BOFFSET      31
+#define BIST_CTRL_BIST_BUSY_BLEN         1
+#define BIST_CTRL_BIST_BUSY_FLAG         HSL_RW
+
+#define ONE_ERR                          "bctrl_oe"
+#define BIST_CTRL_ONE_ERR_BOFFSET        30
+#define BIST_CTRL_ONE_ERR_BLEN           1
+#define BIST_CTRL_ONE_ERR_FLAG           HSL_RO
+
+#define ERR_MEM                          "bctrl_em"
+#define BIST_CTRL_ERR_MEM_BOFFSET        24
+#define BIST_CTRL_ERR_MEM_BLEN           4
+#define BIST_CTRL_ERR_MEM_FLAG           HSL_RO
+
+#define PTN_EN2                          "bctrl_pe2"
+#define BIST_CTRL_PTN_EN2_BOFFSET        22
+#define BIST_CTRL_PTN_EN2_BLEN           1
+#define BIST_CTRL_PTN_EN2_FLAG           HSL_RW
+
+#define PTN_EN1                          "bctrl_pe1"
+#define BIST_CTRL_PTN_EN1_BOFFSET        21
+#define BIST_CTRL_PTN_EN1_BLEN           1
+#define BIST_CTRL_PTN_EN1_FLAG           HSL_RW
+
+#define PTN_EN0                          "bctrl_pe0"
+#define BIST_CTRL_PTN_EN0_BOFFSET        20
+#define BIST_CTRL_PTN_EN0_BLEN           1
+#define BIST_CTRL_PTN_EN0_FLAG           HSL_RW
+
+#define ERR_PTN                          "bctrl_ep"
+#define BIST_CTRL_ERR_PTN_BOFFSET        16
+#define BIST_CTRL_ERR_PTN_BLEN           2
+#define BIST_CTRL_ERR_PTN_FLAG           HSL_RO
+
+#define ERR_CNT                          "bctrl_ec"
+#define BIST_CTRL_ERR_CNT_BOFFSET        13
+#define BIST_CTRL_ERR_CNT_BLEN           2
+#define BIST_CTRL_ERR_CNT_FLAG           HSL_RO
+
+#define ERR_ADDR                         "bctrl_ea"
+#define BIST_CTRL_ERR_ADDR_BOFFSET       0
+#define BIST_CTRL_ERR_ADDR_BLEN          12
+#define BIST_CTRL_ERR_ADDR_FLAG          HSL_RO
+
+
+
+
+    /* BIST recover Register */
+#define BIST_RCV               "brcv"
+#define BIST_RCV_ID            24
+#define BIST_RCV_OFFSET        0x00a4
+#define BIST_RCV_E_LENGTH      4
+#define BIST_RCV_E_OFFSET      0
+#define BIST_RCV_NR_E          1
+
+#define RCV_EN                           "brcv_en"
+#define BIST_RCV_RCV_EN_BOFFSET          31
+#define BIST_RCV_RCV_EN_BLEN             1
+#define BIST_RCV_RCV_EN_FLAG             HSL_RW
+
+#define RCV_ADDR                         "brcv_addr"
+#define BIST_RCV_RCV_ADDR_BOFFSET        0
+#define BIST_RCV_RCV_ADDR_BLEN           12
+#define BIST_RCV_RCV_ADDR_FLAG           HSL_RW
+
+
+
+
+    /* LED control Register */
+#define LED_CTRL               "ledctrl"
+#define LED_CTRL_ID            25
+#define LED_CTRL_OFFSET        0x0050
+#define LED_CTRL_E_LENGTH      4
+#define LED_CTRL_E_OFFSET      0
+#define LED_CTRL_NR_E          3
+
+#define PATTERN_EN                           "lctrl_pen"
+#define LED_CTRL_PATTERN_EN_BOFFSET          14
+#define LED_CTRL_PATTERN_EN_BLEN             2
+#define LED_CTRL_PATTERN_EN_FLAG             HSL_RW
+
+#define FULL_LIGHT_EN                        "lctrl_fen"
+#define LED_CTRL_FULL_LIGHT_EN_BOFFSET       13
+#define LED_CTRL_FULL_LIGHT_EN_BLEN          1
+#define LED_CTRL_FULL_LIGHT_EN_FLAG          HSL_RW
+
+#define HALF_LIGHT_EN                        "lctrl_hen"
+#define LED_CTRL_HALF_LIGHT_EN_BOFFSET       12
+#define LED_CTRL_HALF_LIGHT_EN_BLEN          1
+#define LED_CTRL_HALF_LIGHT_EN_FLAG          HSL_RW
+
+#define POWERON_LIGHT_EN                     "lctrl_poen"
+#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET    11
+#define LED_CTRL_POWERON_LIGHT_EN_BLEN       1
+#define LED_CTRL_POWERON_LIGHT_EN_FLAG       HSL_RW
+
+#define GE_LIGHT_EN                          "lctrl_geen"
+#define LED_CTRL_GE_LIGHT_EN_BOFFSET         10
+#define LED_CTRL_GE_LIGHT_EN_BLEN            1
+#define LED_CTRL_GE_LIGHT_EN_FLAG            HSL_RW
+
+#define FE_LIGHT_EN                          "lctrl_feen"
+#define LED_CTRL_FE_LIGHT_EN_BOFFSET         9
+#define LED_CTRL_FE_LIGHT_EN_BLEN            1
+#define LED_CTRL_FE_LIGHT_EN_FLAG            HSL_RW
+
+#define ETH_LIGHT_EN                         "lctrl_ethen"
+#define LED_CTRL_ETH_LIGHT_EN_BOFFSET        8
+#define LED_CTRL_ETH_LIGHT_EN_BLEN           1
+#define LED_CTRL_ETH_LIGHT_EN_FLAG           HSL_RW
+
+#define COL_BLINK_EN                         "lctrl_cen"
+#define LED_CTRL_COL_BLINK_EN_BOFFSET        7
+#define LED_CTRL_COL_BLINK_EN_BLEN           1
+#define LED_CTRL_COL_BLINK_EN_FLAG           HSL_RW
+
+#define RX_BLINK_EN                          "lctrl_rxen"
+#define LED_CTRL_RX_BLINK_EN_BOFFSET         5
+#define LED_CTRL_RX_BLINK_EN_BLEN            1
+#define LED_CTRL_RX_BLINK_EN_FLAG            HSL_RW
+
+#define TX_BLINK_EN                          "lctrl_txen"
+#define LED_CTRL_TX_BLINK_EN_BOFFSET         4
+#define LED_CTRL_TX_BLINK_EN_BLEN            1
+#define LED_CTRL_TX_BLINK_EN_FLAG            HSL_RW
+
+#define LINKUP_OVER_EN                       "lctrl_loen"
+#define LED_CTRL_LINKUP_OVER_EN_BOFFSET      2
+#define LED_CTRL_LINKUP_OVER_EN_BLEN         1
+#define LED_CTRL_LINKUP_OVER_EN_FLAG         HSL_RW
+
+#define BLINK_FREQ                           "lctrl_bfreq"
+#define LED_CTRL_BLINK_FREQ_BOFFSET          0
+#define LED_CTRL_BLINK_FREQ_BLEN             2
+#define LED_CTRL_BLINK_FREQ_FLAG             HSL_RW
+
+    /* LED control Register */
+#define LED_PATTERN               "ledpatten"
+#define LED_PATTERN_ID            25
+#define LED_PATTERN_OFFSET        0x005c
+#define LED_PATTERN_E_LENGTH      4
+#define LED_PATTERN_E_OFFSET      0
+#define LED_PATTERN_NR_E          1
+
+
+#define P3L2_MODE
+#define LED_PATTERN_P3L2_MODE_BOFFSET       24
+#define LED_PATTERN_P3L2_MODE_BLEN          2
+#define LED_PATTERN_P3L2_MODE_FLAG          HSL_RW
+
+#define P3L1_MODE
+#define LED_PATTERN_P3L1_MODE_BOFFSET       22
+#define LED_PATTERN_P3L1_MODE_BLEN          2
+#define LED_PATTERN_P3L1_MODE_FLAG          HSL_RW
+
+#define P3L0_MODE
+#define LED_PATTERN_P3L0_MODE_BOFFSET       20
+#define LED_PATTERN_P3L0_MODE_BLEN          2
+#define LED_PATTERN_P3L0_MODE_FLAG          HSL_RW
+
+#define P2L2_MODE
+#define LED_PATTERN_P2L2_MODE_BOFFSET       18
+#define LED_PATTERN_P2L2_MODE_BLEN          2
+#define LED_PATTERN_P2L2_MODE_FLAG          HSL_RW
+
+#define P2L1_MODE
+#define LED_PATTERN_P2L1_MODE_BOFFSET       16
+#define LED_PATTERN_P2L1_MODE_BLEN          2
+#define LED_PATTERN_P2L1_MODE_FLAG          HSL_RW
+
+#define P2L0_MODE
+#define LED_PATTERN_P2L0_MODE_BOFFSET       14
+#define LED_PATTERN_P2L0_MODE_BLEN          2
+#define LED_PATTERN_P2L0_MODE_FLAG          HSL_RW
+
+#define P1L2_MODE
+#define LED_PATTERN_P1L2_MODE_BOFFSET       12
+#define LED_PATTERN_P1L2_MODE_BLEN          2
+#define LED_PATTERN_P1L2_MODE_FLAG          HSL_RW
+
+#define P1L1_MODE
+#define LED_PATTERN_P1L1_MODE_BOFFSET       10
+#define LED_PATTERN_P1L1_MODE_BLEN          2
+#define LED_PATTERN_P1L1_MODE_FLAG          HSL_RW
+
+#define P1L0_MODE
+#define LED_PATTERN_P1L0_MODE_BOFFSET       8
+#define LED_PATTERN_P1L0_MODE_BLEN          2
+#define LED_PATTERN_P1L0_MODE_FLAG          HSL_RW
+
+
+
+
+    /* Pri To Queue Register */
+#define PRI_TO_QUEUE
+#define PRI_TO_QUEUE_OFFSET         0x0814
+#define PRI_TO_QUEUE_E_LENGTH       4
+#define PRI_TO_QUEUE_E_OFFSET       0x0004
+#define PRI_TO_QUEUE_NR_E           1
+
+
+
+
+    /* Pri To EhQueue Register */
+#define PRI_TO_EHQUEUE
+#define PRI_TO_EHQUEUE_OFFSET         0x0810
+#define PRI_TO_EHQUEUE_E_LENGTH       4
+#define PRI_TO_EHQUEUE_E_OFFSET       0x0004
+#define PRI_TO_EHQUEUE_NR_E           1
+
+
+
+
+    /*Global Flow Control Register*/
+#define QM_CTRL_REG
+#define QM_CTRL_REG_OFFSET       0X0808
+#define QM_CTRL_REG_E_LENGTH     4
+#define QM_CTRL_REG_E_OFFSET     0x0004
+#define QM_CTRL_REG_NR_E         1
+
+#define GOL_FLOW_EN
+#define QM_CTRL_REG_GOL_FLOW_EN_BOFFSET    16
+#define QM_CTRL_REG_GOL_FLOW_EN_BLEN       7
+#define QM_CTRL_REG_GOL_FLOW_EN_FLAG       HSL_RW
+
+#define QM_FUNC_TEST
+#define QM_CTRL_REG_QM_FUNC_TEST_BOFFSET   10
+#define QM_CTRL_REG_QM_FUNC_TEST_BLEN      1
+#define QM_CTRL_REG_QM_FUNC_TEST_FLAG      HSL_RW
+
+#define RATE_DROP_EN
+#define QM_CTRL_REG_RATE_DROP_EN_BOFFSET 7
+#define QM_CTRL_REG_RATE_DROP_EN_BLEN    1
+#define QM_CTRL_REG_RATE_DROP_EN_FLAG    HSL_RW
+
+#define FLOW_DROP_EN
+#define QM_CTRL_REG_FLOW_DROP_EN_BOFFSET 6
+#define QM_CTRL_REG_FLOW_DROP_EN_BLEN    1
+#define QM_CTRL_REG_FLOW_DROP_EN_FLAG    HSL_RW
+
+#define FLOW_DROP_CNT
+#define QM_CTRL_REG_FLOW_DROP_CNT_BOFFSET 0
+#define QM_CTRL_REG_FLOW_DROP_CNT_BLEN    6
+#define QM_CTRL_REG_FLOW_DROP_CNT_FLAG    HSL_RW
+
+
+
+
+    /* Port HOL CTL0 Register */
+#define PORT_HOL_CTL0
+#define PORT_HOL_CTL0_OFFSET         0x0970
+#define PORT_HOL_CTL0_E_LENGTH       4
+#define PORT_HOL_CTL0_E_OFFSET       0x0008
+#define PORT_HOL_CTL0_NR_E           7
+
+#define PORT_DESC_NR
+#define PORT_HOL_CTL0_PORT_DESC_NR_BOFFSET           24
+#define PORT_HOL_CTL0_PORT_DESC_NR_BLEN              6
+#define PORT_HOL_CTL0_PORT_DESC_NR_FLAG              HSL_RW
+
+#define QUEUE5_DESC_NR
+#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BOFFSET         20
+#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE5_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE4_DESC_NR
+#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BOFFSET         16
+#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE4_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE3_DESC_NR
+#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BOFFSET         12
+#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE3_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE2_DESC_NR
+#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BOFFSET         8
+#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE2_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE1_DESC_NR
+#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BOFFSET         4
+#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE1_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE0_DESC_NR
+#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BOFFSET         0
+#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BLEN            4
+#define PORT_HOL_CTL0_QUEUE0_DESC_NR_FLAG            HSL_RW
+
+    /* Port HOL CTL1 Register */
+#define PORT_HOL_CTL1
+#define PORT_HOL_CTL1_OFFSET         0x0974
+#define PORT_HOL_CTL1_E_LENGTH       4
+#define PORT_HOL_CTL1_E_OFFSET       0x0008
+#define PORT_HOL_CTL1_NR_E           7
+
+#define EG_MIRROR_EN
+#define PORT_HOL_CTL1_EG_MIRROR_EN_BOFFSET           16
+#define PORT_HOL_CTL1_EG_MIRROR_EN_BLEN              1
+#define PORT_HOL_CTL1_EG_MIRROR_EN_FLAG              HSL_RW
+
+#define PORT_RED_EN
+#define PORT_HOL_CTL1_PORT_RED_EN_BOFFSET            8
+#define PORT_HOL_CTL1_PORT_RED_EN_BLEN               1
+#define PORT_HOL_CTL1_PORT_RED_EN_FLAG               HSL_RW
+
+#define PORT_DESC_EN
+#define PORT_HOL_CTL1_PORT_DESC_EN_BOFFSET           7
+#define PORT_HOL_CTL1_PORT_DESC_EN_BLEN              1
+#define PORT_HOL_CTL1_PORT_DESC_EN_FLAG              HSL_RW
+
+#define QUEUE_DESC_EN
+#define PORT_HOL_CTL1_QUEUE_DESC_EN_BOFFSET          6
+#define PORT_HOL_CTL1_QUEUE_DESC_EN_BLEN             1
+#define PORT_HOL_CTL1_QUEUE_DESC_EN_FLAG             HSL_RW
+
+#define PORT_IN_DESC_EN
+#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BOFFSET        0
+#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BLEN           4
+#define PORT_HOL_CTL1_PORT_IN_DESC_EN_FLAG           HSL_RW
+
+    /* PORT FLOW CTRL THRESHOLD REGISTER  */
+#define PORT_FLOW_CTRL_THRESHOLD
+#define PORT_FLOW_CTRL_THRESHOLD_OFFSET		0x09B0
+#define PORT_FLOW_CTRL_THRESHOLD_E_LENGTH	4
+#define PORT_FLOW_CTRL_THRESHOLD_E_OFFSET	0x0004
+#define PORT_FLOW_CTRL_THRESHOLD_NR_E		7
+
+#define XON_THRES
+#define PORT_FLOW_CTRL_THRESHOLD_XON_THRES_BOFFSET	16
+#define PORT_FLOW_CTRL_THRESHOLD_XON_THRES_BLEN		8
+#define PORT_FLOW_CTRL_THRESHOLD_XON_THRES_FLAG		HSL_RW
+
+#define XOFF_THRES
+#define PORT_FLOW_CTRL_THRESHOLD_XOFF_THRES_BOFFSET	0
+#define PORT_FLOW_CTRL_THRESHOLD_XOFF_THRES_BLEN	8
+#define PORT_FLOW_CTRL_THRESHOLD_XOFF_THRES_FLAG	HSL_RW
+
+    /* FX100 CTRL  Register */
+#define FX100_CTRL
+#define FX100_CTRL_OFFSET          0x00fc
+#define FX100_CTRL_E_LENGTH        4
+#define FX100_CTRL_E_OFFSET        0X0004
+#define FX100_CTRL_NR_E            1
+
+#define FX100_STATUS
+#define FX100_CTRL_FX100_STATUS_BOFFSET  24
+#define FX100_CTRL_FX100_STATUS_BLEN     8
+#define FX100_CTRL_FX100_STATUS_FLAG     HSL_RO
+
+#define FX100_LOOP_EN
+#define FX100_CTRL_FX100_LOOP_EN_BOFFSET    23
+#define FX100_CTRL_FX100_LOOP_EN_BLEN       1
+#define FX100_CTRL_FX100_LOOP_EN_FLAG       HSL_Rw
+
+#define SGMII_FIBER
+#define FX100_CTRL_SGMII_FIBER_BOFFSET    15
+#define FX100_CTRL_SGMII_FIBER_BLEN       2
+#define FX100_CTRL_SGMII_FIBER_FLAG       HSL_Rw
+
+#define CRS_COL_100_CTRL
+#define FX100_CTRL_CRS_COL_100_CTRL_BOFFSET    14
+#define FX100_CTRL_CRS_COL_100_CTRL_BLEN       1
+#define FX100_CTRL_CRS_COL_100_CTRL_FLAG       HSL_Rw
+
+#define LOOPBACK_TEST
+#define FX100_CTRL_LOOPBACK_TEST_BOFFSET    13
+#define FX100_CTRL_LOOPBACK_TEST_BLEN       1
+#define FX100_CTRL_LOOPBACK_TEST_FLAG       HSL_Rw
+
+#define CRS_CTRL
+#define FX100_CTRL_CRS_CTRL_BOFFSET    12
+#define FX100_CTRL_CRS_CTRL_BLEN       1
+#define FX100_CTRL_CRS_CTRL_FLAG       HSL_Rw
+
+#define COL_TEST
+#define FX100_CTRL_COL_TEST_BOFFSET    11
+#define FX100_CTRL_COL_TEST_BLEN       1
+#define FX100_CTRL_COL_TEST_FLAG       HSL_Rw
+
+#define FD_MODE
+#define FX100_CTRL_FD_MODE_BOFFSET    10
+#define FX100_CTRL_FD_MODE_BLEN       1
+#define FX100_CTRL_FD_MODE_FLAG       HSL_Rw
+
+#define LINK_CTRL
+#define FX100_CTRL_LINK_CTRL_BOFFSET    8
+#define FX100_CTRL_LINK_CTRL_BLEN       2
+#define FX100_CTRL_LINK_CTRL_FLAG       HSL_Rw
+
+#define OVERSHOOT_MODE
+#define FX100_CTRL_OVERSHOOT_MODE_BOFFSET    6
+#define FX100_CTRL_OVERSHOOT_MODE_BLEN       1
+#define FX100_CTRL_OVERSHOOT_MODE_FLAG       HSL_Rw
+
+#define LOOPBACK_MODE
+#define FX100_CTRL_LOOPBACK_MODE_BOFFSET    3
+#define FX100_CTRL_LOOPBACK_MODE_BLEN       1
+#define FX100_CTRL_LOOPBACK_MODE_FLAG       HSL_Rw
+
+
+
+    /* Port Rate Limit0 Register */
+#define RATE_LIMIT0                "rlmt0"
+#define RATE_LIMIT0_ID             32
+#define RATE_LIMIT0_OFFSET         0x0110
+#define RATE_LIMIT0_E_LENGTH       4
+#define RATE_LIMIT0_E_OFFSET       0x0100
+#define RATE_LIMIT0_NR_E           7
+
+
+#define EG_RATE_EN                             "rlmt_egen"
+#define RATE_LIMIT0_EG_RATE_EN_BOFFSET         23
+#define RATE_LIMIT0_EG_RATE_EN_BLEN            1
+#define RATE_LIMIT0_EG_RATE_EN_FLAG            HSL_RW
+
+#define EG_MNG_RATE_EN                         "rlmt_egmngen"
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET     22
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN        1
+#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG        HSL_RW
+
+#define IN_MNG_RATE_EN                         "rlmt_inmngen"
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET     21
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN        1
+#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG        HSL_RW
+
+#define IN_MUL_RATE_EN                         "rlmt_inmulen"
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET     20
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN        1
+#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG        HSL_RW
+
+#define ING_RATE                               "rlmt_ingrate"
+#define RATE_LIMIT0_ING_RATE_BOFFSET           0
+#define RATE_LIMIT0_ING_RATE_BLEN              15
+#define RATE_LIMIT0_ING_RATE_FLAG              HSL_RW
+
+
+
+    /* PKT edit control register */
+#define PKT_CTRL
+#define PKT_CTRL_OFFSET     0x0c00
+#define PKT_CTRL_E_LENGTH   4
+#define PKT_CTRL_E_OFFSET   0
+#define PKT_CTRL_NR_E       7
+
+#define CPU_VID_EN
+#define PKT_CTRL_CPU_VID_EN_BOFFSET       1
+#define PKT_CTRL_CPU_VID_EN_BLEN          1
+#define PKT_CTRL_CPU_VID_EN_FLAG          HSL_RW
+
+
+#define RTD_PPPOE_EN
+#define PKT_CTRL_RTD_PPPOE_EN_BOFFSET       0
+#define PKT_CTRL_RTD_PPPOE_EN_BLEN          1
+#define PKT_CTRL_RTD_PPPOE_EN_FLAG          HSL_RW
+
+
+
+
+    /* mib memory info */
+#define MIB_RXBROAD
+#define MIB_RXBROAD_OFFSET                0x01000
+#define MIB_RXBROAD_E_LENGTH              4
+#define MIB_RXBROAD_E_OFFSET              0x100
+#define MIB_RXBROAD_NR_E                  7
+
+#define MIB_RXPAUSE
+#define MIB_RXPAUSE_OFFSET                0x01004
+#define MIB_RXPAUSE_E_LENGTH              4
+#define MIB_RXPAUSE_E_OFFSET              0x100
+#define MIB_RXPAUSE_NR_E                  7
+
+#define MIB_RXMULTI
+#define MIB_RXMULTI_OFFSET                0x01008
+#define MIB_RXMULTI_E_LENGTH              4
+#define MIB_RXMULTI_E_OFFSET              0x100
+#define MIB_RXMULTI_NR_E                  7
+
+#define MIB_RXFCSERR
+#define MIB_RXFCSERR_OFFSET               0x0100c
+#define MIB_RXFCSERR_E_LENGTH             4
+#define MIB_RXFCSERR_E_OFFSET             0x100
+#define MIB_RXFCSERR_NR_E                 7
+
+#define MIB_RXALLIGNERR
+#define MIB_RXALLIGNERR_OFFSET            0x01010
+#define MIB_RXALLIGNERR_E_LENGTH          4
+#define MIB_RXALLIGNERR_E_OFFSET          0x100
+#define MIB_RXALLIGNERR_NR_E              7
+
+#define MIB_RXRUNT
+#define MIB_RXRUNT_OFFSET                 0x01014
+#define MIB_RXRUNT_E_LENGTH               4
+#define MIB_RXRUNT_E_OFFSET               0x100
+#define MIB_RXRUNT_NR_E                   7
+
+#define MIB_RXFRAGMENT
+#define MIB_RXFRAGMENT_OFFSET             0x01018
+#define MIB_RXFRAGMENT_E_LENGTH           4
+#define MIB_RXFRAGMENT_E_OFFSET           0x100
+#define MIB_RXFRAGMENT_NR_E               7
+
+#define MIB_RX64BYTE
+#define MIB_RX64BYTE_OFFSET               0x0101c
+#define MIB_RX64BYTE_E_LENGTH             4
+#define MIB_RX64BYTE_E_OFFSET             0x100
+#define MIB_RX64BYTE_NR_E                 7
+
+#define MIB_RX128BYTE
+#define MIB_RX128BYTE_OFFSET              0x01020
+#define MIB_RX128BYTE_E_LENGTH            4
+#define MIB_RX128BYTE_E_OFFSET            0x100
+#define MIB_RX128BYTE_NR_E                7
+
+#define MIB_RX256BYTE
+#define MIB_RX256BYTE_OFFSET              0x01024
+#define MIB_RX256BYTE_E_LENGTH            4
+#define MIB_RX256BYTE_E_OFFSET            0x100
+#define MIB_RX256BYTE_NR_E                7
+
+#define MIB_RX512BYTE
+#define MIB_RX512BYTE_OFFSET              0x01028
+#define MIB_RX512BYTE_E_LENGTH            4
+#define MIB_RX512BYTE_E_OFFSET            0x100
+#define MIB_RX512BYTE_NR_E                7
+
+#define MIB_RX1024BYTE
+#define MIB_RX1024BYTE_OFFSET             0x0102c
+#define MIB_RX1024BYTE_E_LENGTH           4
+#define MIB_RX1024BYTE_E_OFFSET           0x100
+#define MIB_RX1024BYTE_NR_E               7
+
+#define MIB_RX1518BYTE
+#define MIB_RX1518BYTE_OFFSET             0x01030
+#define MIB_RX1518BYTE_E_LENGTH           4
+#define MIB_RX1518BYTE_E_OFFSET           0x100
+#define MIB_RX1518BYTE_NR_E               7
+
+#define MIB_RXMAXBYTE
+#define MIB_RXMAXBYTE_OFFSET              0x01034
+#define MIB_RXMAXBYTE_E_LENGTH            4
+#define MIB_RXMAXBYTE_E_OFFSET            0x100
+#define MIB_RXMAXBYTE_NR_E                7
+
+#define MIB_RXTOOLONG
+#define MIB_RXTOOLONG_OFFSET              0x01038
+#define MIB_RXTOOLONG_E_LENGTH            4
+#define MIB_RXTOOLONG_E_OFFSET            0x100
+#define MIB_RXTOOLONG_NR_E                7
+
+#define MIB_RXGOODBYTE_LO
+#define MIB_RXGOODBYTE_LO_OFFSET          0x0103c
+#define MIB_RXGOODBYTE_LO_E_LENGTH        4
+#define MIB_RXGOODBYTE_LO_E_OFFSET        0x100
+#define MIB_RXGOODBYTE_LO_NR_E            7
+
+#define MIB_RXGOODBYTE_HI
+#define MIB_RXGOODBYTE_HI_OFFSET          0x01040
+#define MIB_RXGOODBYTE_HI_E_LENGTH        4
+#define MIB_RXGOODBYTE_HI_E_OFFSET        0x100
+#define MIB_RXGOODBYTE_HI_NR_E            7
+
+#define MIB_RXBADBYTE_LO
+#define MIB_RXBADBYTE_LO_OFFSET           0x01044
+#define MIB_RXBADBYTE_LO_E_LENGTH         4
+#define MIB_RXBADBYTE_LO_E_OFFSET         0x100
+#define MIB_RXBADBYTE_LO_NR_E             7
+
+#define MIB_RXBADBYTE_HI
+#define MIB_RXBADBYTE_HI_OFFSET           0x01048
+#define MIB_RXBADBYTE_HI_E_LENGTH         4
+#define MIB_RXBADBYTE_HI_E_OFFSET         0x100
+#define MIB_RXBADBYTE_HI_NR_E             7
+
+#define MIB_RXOVERFLOW
+#define MIB_RXOVERFLOW_OFFSET             0x0104c
+#define MIB_RXOVERFLOW_E_LENGTH           4
+#define MIB_RXOVERFLOW_E_OFFSET           0x100
+#define MIB_RXOVERFLOW_NR_E               7
+
+#define MIB_FILTERED
+#define MIB_FILTERED_OFFSET               0x01050
+#define MIB_FILTERED_E_LENGTH             4
+#define MIB_FILTERED_E_OFFSET             0x100
+#define MIB_FILTERED_NR_E                 7
+
+#define MIB_TXBROAD
+#define MIB_TXBROAD_OFFSET                0x01054
+#define MIB_TXBROAD_E_LENGTH              4
+#define MIB_TXBROAD_E_OFFSET              0x100
+#define MIB_TXBROAD_NR_E                  7
+
+#define MIB_TXPAUSE
+#define MIB_TXPAUSE_OFFSET                0x01058
+#define MIB_TXPAUSE_E_LENGTH              4
+#define MIB_TXPAUSE_E_OFFSET              0x100
+#define MIB_TXPAUSE_NR_E                  7
+
+#define MIB_TXMULTI
+#define MIB_TXMULTI_OFFSET                0x0105c
+#define MIB_TXMULTI_E_LENGTH              4
+#define MIB_TXMULTI_E_OFFSET              0x100
+#define MIB_TXMULTI_NR_E                  7
+
+#define MIB_TXUNDERRUN
+#define MIB_TXUNDERRUN_OFFSET             0x01060
+#define MIB_TXUNDERRUN_E_LENGTH           4
+#define MIB_TXUNDERRUN_E_OFFSET           0x100
+#define MIB_TXUNDERRUN_NR_E               7
+
+#define MIB_TX64BYTE
+#define MIB_TX64BYTE_OFFSET               0x01064
+#define MIB_TX64BYTE_E_LENGTH             4
+#define MIB_TX64BYTE_E_OFFSET             0x100
+#define MIB_TX64BYTE_NR_E                 7
+
+#define MIB_TX128BYTE
+#define MIB_TX128BYTE_OFFSET              0x01068
+#define MIB_TX128BYTE_E_LENGTH            4
+#define MIB_TX128BYTE_E_OFFSET            0x100
+#define MIB_TX128BYTE_NR_E                7
+
+#define MIB_TX256BYTE
+#define MIB_TX256BYTE_OFFSET              0x0106c
+#define MIB_TX256BYTE_E_LENGTH            4
+#define MIB_TX256BYTE_E_OFFSET            0x100
+#define MIB_TX256BYTE_NR_E                7
+
+#define MIB_TX512BYTE
+#define MIB_TX512BYTE_OFFSET              0x01070
+#define MIB_TX512BYTE_E_LENGTH            4
+#define MIB_TX512BYTE_E_OFFSET            0x100
+#define MIB_TX512BYTE_NR_E                7
+
+#define MIB_TX1024BYTE
+#define MIB_TX1024BYTE_OFFSET             0x01074
+#define MIB_TX1024BYTE_E_LENGTH           4
+#define MIB_TX1024BYTE_E_OFFSET           0x100
+#define MIB_TX1024BYTE_NR_E               7
+
+#define MIB_TX1518BYTE
+#define MIB_TX1518BYTE_OFFSET             0x01078
+#define MIB_TX1518BYTE_E_LENGTH           4
+#define MIB_TX1518BYTE_E_OFFSET           0x100
+#define MIB_TX1518BYTE_NR_E               7
+
+#define MIB_TXMAXBYTE
+#define MIB_TXMAXBYTE_OFFSET              0x0107c
+#define MIB_TXMAXBYTE_E_LENGTH            4
+#define MIB_TXMAXBYTE_E_OFFSET            0x100
+#define MIB_TXMAXBYTE_NR_E                7
+
+#define MIB_TXOVERSIZE
+#define MIB_TXOVERSIZE_OFFSET             0x01080
+#define MIB_TXOVERSIZE_E_LENGTH           4
+#define MIB_TXOVERSIZE_E_OFFSET           0x100
+#define MIB_TXOVERSIZE_NR_E               7
+
+#define MIB_TXBYTE_LO
+#define MIB_TXBYTE_LO_OFFSET              0x01084
+#define MIB_TXBYTE_LO_E_LENGTH            4
+#define MIB_TXBYTE_LO_E_OFFSET            0x100
+#define MIB_TXBYTE_LO_NR_E                7
+
+#define MIB_TXBYTE_HI
+#define MIB_TXBYTE_HI_OFFSET              0x01088
+#define MIB_TXBYTE_HI_E_LENGTH            4
+#define MIB_TXBYTE_HI_E_OFFSET            0x100
+#define MIB_TXBYTE_HI_NR_E                7
+
+#define MIB_TXCOLLISION
+#define MIB_TXCOLLISION_OFFSET            0x0108c
+#define MIB_TXCOLLISION_E_LENGTH          4
+#define MIB_TXCOLLISION_E_OFFSET          0x100
+#define MIB_TXCOLLISION_NR_E              7
+
+#define MIB_TXABORTCOL
+#define MIB_TXABORTCOL_OFFSET             0x01090
+#define MIB_TXABORTCOL_E_LENGTH           4
+#define MIB_TXABORTCOL_E_OFFSET           0x100
+#define MIB_TXABORTCOL_NR_E               7
+
+#define MIB_TXMULTICOL
+#define MIB_TXMULTICOL_OFFSET             0x01094
+#define MIB_TXMULTICOL_E_LENGTH           4
+#define MIB_TXMULTICOL_E_OFFSET           0x100
+#define MIB_TXMULTICOL_NR_E               7
+
+#define MIB_TXSINGALCOL
+#define MIB_TXSINGALCOL_OFFSET            0x01098
+#define MIB_TXSINGALCOL_E_LENGTH          4
+#define MIB_TXSINGALCOL_E_OFFSET          0x100
+#define MIB_TXSINGALCOL_NR_E              7
+
+#define MIB_TXEXCDEFER
+#define MIB_TXEXCDEFER_OFFSET             0x0109c
+#define MIB_TXEXCDEFER_E_LENGTH           4
+#define MIB_TXEXCDEFER_E_OFFSET           0x100
+#define MIB_TXEXCDEFER_NR_E               7
+
+#define MIB_TXDEFER
+#define MIB_TXDEFER_OFFSET                0x010a0
+#define MIB_TXDEFER_E_LENGTH              4
+#define MIB_TXDEFER_E_OFFSET              0x100
+#define MIB_TXDEFER_NR_E                  7
+
+#define MIB_TXLATECOL
+#define MIB_TXLATECOL_OFFSET              0x010a4
+#define MIB_TXLATECOL_E_LENGTH            4
+#define MIB_TXLATECOL_E_OFFSET            0x100
+#define MIB_TXLATECOL_NR_E                7
+
+#define MIB_RXUNICAST
+#define MIB_RXUNICAST_OFFSET              0x010a8
+#define MIB_RXUNICAST_E_LENGTH            4
+#define MIB_RXUNICAST_E_OFFSET            0x100
+#define MIB_RXUNICAST_NR_E                7
+
+#define MIB_TXUNICAST
+#define MIB_TXUNICAST_OFFSET              0x010ac
+#define MIB_TXUNICAST_E_LENGTH            4
+#define MIB_TXUNICAST_E_OFFSET            0x100
+#define MIB_TXUNICAST_NR_E                7
+
+    /* ACL Action Register */
+#define ACL_RSLT0                         10
+#define ACL_RSLT0_OFFSET                  0x5a000
+#define ACL_RSLT0_E_LENGTH                4
+#define ACL_RSLT0_E_OFFSET                0x10
+#define ACL_RSLT0_NR_E                    96
+
+#define CTAGPRI
+#define ACL_RSLT0_CTAGPRI_BOFFSET         29
+#define ACL_RSLT0_CTAGPRI_BLEN            3
+#define ACL_RSLT0_CTAGPRI_FLAG            HSL_RW
+
+#define CTAGCFI
+#define ACL_RSLT0_CTAGCFI_BOFFSET         28
+#define ACL_RSLT0_CTAGCFI_BLEN            1
+#define ACL_RSLT0_CTAGCFI_FLAG            HSL_RW
+
+#define CTAGVID
+#define ACL_RSLT0_CTAGVID_BOFFSET         16
+#define ACL_RSLT0_CTAGVID_BLEN            12
+#define ACL_RSLT0_CTAGVID_FLAG            HSL_RW
+
+#define STAGPRI
+#define ACL_RSLT0_STAGPRI_BOFFSET         13
+#define ACL_RSLT0_STAGPRI_BLEN            3
+#define ACL_RSLT0_STAGPRI_FLAG            HSL_RW
+
+#define STAGDEI
+#define ACL_RSLT0_STAGDEI_BOFFSET         12
+#define ACL_RSLT0_STAGDEI_BLEN            1
+#define ACL_RSLT0_STAGDEI_FLAG            HSL_RW
+
+#define STAGVID
+#define ACL_RSLT0_STAGVID_BOFFSET         0
+#define ACL_RSLT0_STAGVID_BLEN            12
+#define ACL_RSLT0_STAGVID_FLAG            HSL_RW
+
+
+#define ACL_RSLT1                         11
+#define ACL_RSLT1_OFFSET                  0x5a004
+#define ACL_RSLT1_E_LENGTH                4
+#define ACL_RSLT1_E_OFFSET                0x10
+#define ACL_RSLT1_NR_E                    96
+
+#define DES_PORT0
+#define ACL_RSLT1_DES_PORT0_BOFFSET       29
+#define ACL_RSLT1_DES_PORT0_BLEN          3
+#define ACL_RSLT1_DES_PORT0_FLAG          HSL_RW
+
+#define PRI_QU_EN
+#define ACL_RSLT1_PRI_QU_EN_BOFFSET       28
+#define ACL_RSLT1_PRI_QU_EN_BLEN          1
+#define ACL_RSLT1_PRI_QU_EN_FLAG          HSL_RW
+
+#define PRI_QU
+#define ACL_RSLT1_PRI_QU_BOFFSET          25
+#define ACL_RSLT1_PRI_QU_BLEN             3
+#define ACL_RSLT1_PRI_QU_FLAG             HSL_RW
+
+#define WCMP_EN
+#define ACL_RSLT1_WCMP_EN_BOFFSET         24
+#define ACL_RSLT1_WCMP_EN_BLEN            1
+#define ACL_RSLT1_WCMP_EN_FLAG            HSL_RW
+
+#define ARP_PTR
+#define ACL_RSLT1_ARP_PTR_BOFFSET         17
+#define ACL_RSLT1_ARP_PTR_BLEN            7
+#define ACL_RSLT1_ARP_PTR_FLAG            HSL_RW
+
+#define ARP_PTR_EN
+#define ACL_RSLT1_ARP_PTR_EN_BOFFSET      16
+#define ACL_RSLT1_ARP_PTR_EN_BLEN         1
+#define ACL_RSLT1_ARP_PTR_EN_FLAG         HSL_RW
+
+#define FORCE_L3_MODE
+#define ACL_RSLT1_FORCE_L3_MODE_BOFFSET   14
+#define ACL_RSLT1_FORCE_L3_MODE_BLEN      2
+#define ACL_RSLT1_FORCE_L3_MODE_FLAG      HSL_RW
+
+#define LOOK_VID_CHG
+#define ACL_RSLT1_LOOK_VID_CHG_BOFFSET    13
+#define ACL_RSLT1_LOOK_VID_CHG_BLEN       1
+#define ACL_RSLT1_LOOK_VID_CHG_FLAG       HSL_RW
+
+#define TRANS_CVID_CHG
+#define ACL_RSLT1_TRANS_CVID_CHG_BOFFSET  12
+#define ACL_RSLT1_TRANS_CVID_CHG_BLEN     1
+#define ACL_RSLT1_TRANS_CVID_CHG_FLAG     HSL_RW
+
+#define TRANS_SVID_CHG
+#define ACL_RSLT1_TRANS_SVID_CHG_BOFFSET  11
+#define ACL_RSLT1_TRANS_SVID_CHG_BLEN     1
+#define ACL_RSLT1_TRANS_SVID_CHG_FLAG     HSL_RW
+
+#define CTAG_CFI_CHG
+#define ACL_RSLT1_CTAG_CFI_CHG_BOFFSET    10
+#define ACL_RSLT1_CTAG_CFI_CHG_BLEN       1
+#define ACL_RSLT1_CTAG_CFI_CHG_FLAG       HSL_RW
+
+#define CTAG_PRI_REMAP
+#define ACL_RSLT1_CTAG_PRI_REMAP_BOFFSET  9
+#define ACL_RSLT1_CTAG_PRI_REMAP_BLEN     1
+#define ACL_RSLT1_CTAG_PRI_REMAP_FLAG     HSL_RW
+
+#define STAG_DEI_CHG
+#define ACL_RSLT1_STAG_DEI_CHG_BOFFSET    8
+#define ACL_RSLT1_STAG_DEI_CHG_BLEN       1
+#define ACL_RSLT1_STAG_DEI_CHG_FLAG       HSL_RW
+
+#define STAG_PRI_REMAP
+#define ACL_RSLT1_STAG_PRI_REMAP_BOFFSET  7
+#define ACL_RSLT1_STAG_PRI_REMAP_BLEN     1
+#define ACL_RSLT1_STAG_PRI_REMAP_FLAG     HSL_RW
+
+#define DSCP_REMAP
+#define ACL_RSLT1_DSCP_REMAP_BOFFSET      6
+#define ACL_RSLT1_DSCP_REMAP_BLEN         1
+#define ACL_RSLT1_DSCP_REMAP_FLAG         HSL_RW
+
+#define DSCPV
+#define ACL_RSLT1_DSCPV_BOFFSET           0
+#define ACL_RSLT1_DSCPV_BLEN              6
+#define ACL_RSLT1_DSCPV_FLAG              HSL_RW
+
+#define ACL_RSLT2                         12
+#define ACL_RSLT2_OFFSET                  0x5a008
+#define ACL_RSLT2_E_LENGTH                4
+#define ACL_RSLT2_E_OFFSET                0x10
+#define ACL_RSLT2_NR_E                    96
+
+#define TRIGGER_INTR
+#define ACL_RSLT2_TRIGGER_INTR_BOFFSET    16
+#define ACL_RSLT2_TRIGGER_INTR_BLEN       1
+#define ACL_RSLT2_TRIGGER_INTR_FLAG       HSL_RW
+
+#define EG_BYPASS
+#define ACL_RSLT2_EG_BYPASS_BOFFSET       15
+#define ACL_RSLT2_EG_BYPASS_BLEN          1
+#define ACL_RSLT2_EG_BYPASS_FLAG          HSL_RW
+
+#define POLICER_EN
+#define ACL_RSLT2_POLICER_EN_BOFFSET      14
+#define ACL_RSLT2_POLICER_EN_BLEN         1
+#define ACL_RSLT2_POLICER_EN_FLAG         HSL_RW
+
+#define POLICER_PTR
+#define ACL_RSLT2_POLICER_PTR_BOFFSET     9
+#define ACL_RSLT2_POLICER_PTR_BLEN        5
+#define ACL_RSLT2_POLICER_PTR_FLAG        HSL_RW
+
+#define FWD_CMD
+#define ACL_RSLT2_FWD_CMD_BOFFSET         6
+#define ACL_RSLT2_FWD_CMD_BLEN            3
+#define ACL_RSLT2_FWD_CMD_FLAG            HSL_RW
+
+#define MIRR_EN
+#define ACL_RSLT2_MIRR_EN_BOFFSET         5
+#define ACL_RSLT2_MIRR_EN_BLEN            1
+#define ACL_RSLT2_MIRR_EN_FLAG            HSL_RW
+
+#define DES_PORT_EN
+#define ACL_RSLT2_DES_PORT_EN_BOFFSET     4
+#define ACL_RSLT2_DES_PORT_EN_BLEN        1
+#define ACL_RSLT2_DES_PORT_EN_FLAG        HSL_RW
+
+#define DES_PORT1
+#define ACL_RSLT2_DES_PORT1_BOFFSET       0
+#define ACL_RSLT2_DES_PORT1_BLEN          4
+#define ACL_RSLT2_DES_PORT1_FLAG          HSL_RW
+
+
+
+
+    /* MAC Type Rule Field Define */
+#define MAC_RUL_V0                         0
+#define MAC_RUL_V0_OFFSET                  0x58000
+#define MAC_RUL_V0_E_LENGTH                4
+#define MAC_RUL_V0_E_OFFSET                0x20
+#define MAC_RUL_V0_NR_E                    96
+
+#define DAV_BYTE2
+#define MAC_RUL_V0_DAV_BYTE2_BOFFSET       24
+#define MAC_RUL_V0_DAV_BYTE2_BLEN          8
+#define MAC_RUL_V0_DAV_BYTE2_FLAG          HSL_RW
+
+#define DAV_BYTE3
+#define MAC_RUL_V0_DAV_BYTE3_BOFFSET       16
+#define MAC_RUL_V0_DAV_BYTE3_BLEN          8
+#define MAC_RUL_V0_DAV_BYTE3_FLAG          HSL_RW
+
+#define DAV_BYTE4
+#define MAC_RUL_V0_DAV_BYTE4_BOFFSET       8
+#define MAC_RUL_V0_DAV_BYTE4_BLEN          8
+#define MAC_RUL_V0_DAV_BYTE4_FLAG          HSL_RW
+
+#define DAV_BYTE5
+#define MAC_RUL_V0_DAV_BYTE5_BOFFSET       0
+#define MAC_RUL_V0_DAV_BYTE5_BLEN          8
+#define MAC_RUL_V0_DAV_BYTE5_FLAG          HSL_RW
+
+
+#define MAC_RUL_V1                         1
+#define MAC_RUL_V1_OFFSET                  0x58004
+#define MAC_RUL_V1_E_LENGTH                4
+#define MAC_RUL_V1_E_OFFSET                0x20
+#define MAC_RUL_V1_NR_E                    96
+
+#define SAV_BYTE4
+#define MAC_RUL_V1_SAV_BYTE4_BOFFSET       24
+#define MAC_RUL_V1_SAV_BYTE4_BLEN          8
+#define MAC_RUL_V1_SAV_BYTE4_FLAG          HSL_RW
+
+#define SAV_BYTE5
+#define MAC_RUL_V1_SAV_BYTE5_BOFFSET       16
+#define MAC_RUL_V1_SAV_BYTE5_BLEN          8
+#define MAC_RUL_V1_SAV_BYTE5_FLAG          HSL_RW
+
+#define DAV_BYTE0
+#define MAC_RUL_V1_DAV_BYTE0_BOFFSET       8
+#define MAC_RUL_V1_DAV_BYTE0_BLEN          8
+#define MAC_RUL_V1_DAV_BYTE0_FLAG          HSL_RW
+
+#define DAV_BYTE1
+#define MAC_RUL_V1_DAV_BYTE1_BOFFSET       0
+#define MAC_RUL_V1_DAV_BYTE1_BLEN          8
+#define MAC_RUL_V1_DAV_BYTE1_FLAG          HSL_RW
+
+
+#define MAC_RUL_V2                         2
+#define MAC_RUL_V2_OFFSET                  0x58008
+#define MAC_RUL_V2_E_LENGTH                4
+#define MAC_RUL_V2_E_OFFSET                0x20
+#define MAC_RUL_V2_NR_E                    96
+
+#define SAV_BYTE0
+#define MAC_RUL_V2_SAV_BYTE0_BOFFSET       24
+#define MAC_RUL_V2_SAV_BYTE0_BLEN          8
+#define MAC_RUL_V2_SAV_BYTE0_FLAG          HSL_RW
+
+#define SAV_BYTE1
+#define MAC_RUL_V2_SAV_BYTE1_BOFFSET       16
+#define MAC_RUL_V2_SAV_BYTE1_BLEN          8
+#define MAC_RUL_V2_SAV_BYTE1_FLAG          HSL_RW
+
+#define SAV_BYTE2
+#define MAC_RUL_V2_SAV_BYTE2_BOFFSET       8
+#define MAC_RUL_V2_SAV_BYTE2_BLEN          8
+#define MAC_RUL_V2_SAV_BYTE2_FLAG          HSL_RW
+
+#define SAV_BYTE3
+#define MAC_RUL_V2_SAV_BYTE3_BOFFSET       0
+#define MAC_RUL_V2_SAV_BYTE3_BLEN          8
+#define MAC_RUL_V2_SAV_BYTE3_FLAG          HSL_RW
+
+
+#define MAC_RUL_V3                         3
+#define MAC_RUL_V3_ID                      13
+#define MAC_RUL_V3_OFFSET                  0x5800c
+#define MAC_RUL_V3_E_LENGTH                4
+#define MAC_RUL_V3_E_OFFSET                0x20
+#define MAC_RUL_V3_NR_E                    96
+
+#define ETHTYPV
+#define MAC_RUL_V3_ETHTYPV_BOFFSET         16
+#define MAC_RUL_V3_ETHTYPV_BLEN            16
+#define MAC_RUL_V3_ETHTYPV_FLAG            HSL_RW
+
+#define VLANPRIV
+#define MAC_RUL_V3_VLANPRIV_BOFFSET        13
+#define MAC_RUL_V3_VLANPRIV_BLEN           3
+#define MAC_RUL_V3_VLANPRIV_FLAG           HSL_RW
+
+#define VLANCFIV
+#define MAC_RUL_V3_VLANCFIV_BOFFSET        12
+#define MAC_RUL_V3_VLANCFIV_BLEN           1
+#define MAC_RUL_V3_VLANCFIV_FLAG           HSL_RW
+
+#define VLANIDV
+#define MAC_RUL_V3_VLANIDV_BOFFSET         0
+#define MAC_RUL_V3_VLANIDV_BLEN            12
+#define MAC_RUL_V3_VLANIDV_FLAG            HSL_RW
+
+
+#define MAC_RUL_V4                         4
+#define MAC_RUL_V4_OFFSET                  0x58010
+#define MAC_RUL_V4_E_LENGTH                4
+#define MAC_RUL_V4_E_OFFSET                0x20
+#define MAC_RUL_V4_NR_E                    96
+
+#define RULE_INV
+#define MAC_RUL_V4_RULE_INV_BOFFSET        7
+#define MAC_RUL_V4_RULE_INV_BLEN           1
+#define MAC_RUL_V4_RULE_INV_FLAG           HSL_RW
+
+#define SRC_PT
+#define MAC_RUL_V4_SRC_PT_BOFFSET          0
+#define MAC_RUL_V4_SRC_PT_BLEN             7
+#define MAC_RUL_V4_SRC_PT_FLAG             HSL_RW
+
+
+#define MAC_RUL_M0                         5
+#define MAC_RUL_M0_OFFSET                  0x59000
+#define MAC_RUL_M0_E_LENGTH                4
+#define MAC_RUL_M0_E_OFFSET                0x20
+#define MAC_RUL_M0_NR_E                    96
+
+#define DAM_BYTE2
+#define MAC_RUL_M0_DAM_BYTE2_BOFFSET       24
+#define MAC_RUL_M0_DAM_BYTE2_BLEN          8
+#define MAC_RUL_M0_DAM_BYTE2_FLAG          HSL_RW
+
+#define DAM_BYTE3
+#define MAC_RUL_M0_DAM_BYTE3_BOFFSET       16
+#define MAC_RUL_M0_DAM_BYTE3_BLEN          8
+#define MAC_RUL_M0_DAM_BYTE3_FLAG          HSL_RW
+
+#define DAM_BYTE4
+#define MAC_RUL_M0_DAM_BYTE4_BOFFSET       8
+#define MAC_RUL_M0_DAM_BYTE4_BLEN          8
+#define MAC_RUL_M0_DAM_BYTE4_FLAG          HSL_RW
+
+#define DAM_BYTE5
+#define MAC_RUL_M0_DAM_BYTE5_BOFFSET       0
+#define MAC_RUL_M0_DAM_BYTE5_BLEN          8
+#define MAC_RUL_M0_DAM_BYTE5_FLAG          HSL_RW
+
+
+#define MAC_RUL_M1                         6
+#define MAC_RUL_M1_OFFSET                  0x59004
+#define MAC_RUL_M1_E_LENGTH                4
+#define MAC_RUL_M1_E_OFFSET                0x20
+#define MAC_RUL_M1_NR_E                    96
+
+#define SAM_BYTE4
+#define MAC_RUL_M1_SAM_BYTE4_BOFFSET       24
+#define MAC_RUL_M1_SAM_BYTE4_BLEN          8
+#define MAC_RUL_M1_SAM_BYTE4_FLAG          HSL_RW
+
+#define SAM_BYTE5
+#define MAC_RUL_M1_SAM_BYTE5_BOFFSET       16
+#define MAC_RUL_M1_SAM_BYTE5_BLEN          8
+#define MAC_RUL_M1_SAM_BYTE5_FLAG          HSL_RW
+
+#define DAM_BYTE0
+#define MAC_RUL_M1_DAM_BYTE0_BOFFSET       8
+#define MAC_RUL_M1_DAM_BYTE0_BLEN          8
+#define MAC_RUL_M1_DAM_BYTE0_FLAG          HSL_RW
+
+#define DAM_BYTE1
+#define MAC_RUL_M1_DAM_BYTE1_BOFFSET       0
+#define MAC_RUL_M1_DAM_BYTE1_BLEN          8
+#define MAC_RUL_M1_DAM_BYTE1_FLAG          HSL_RW
+
+
+#define MAC_RUL_M2                         7
+#define MAC_RUL_M2_OFFSET                  0x59008
+#define MAC_RUL_M2_E_LENGTH                4
+#define MAC_RUL_M2_E_OFFSET                0x20
+#define MAC_RUL_M2_NR_E                    96
+
+#define SAM_BYTE0
+#define MAC_RUL_M2_SAM_BYTE0_BOFFSET       24
+#define MAC_RUL_M2_SAM_BYTE0_BLEN          8
+#define MAC_RUL_M2_SAM_BYTE0_FLAG          HSL_RW
+
+#define SAM_BYTE1
+#define MAC_RUL_M2_SAM_BYTE1_BOFFSET       16
+#define MAC_RUL_M2_SAM_BYTE1_BLEN          8
+#define MAC_RUL_M2_SAM_BYTE1_FLAG          HSL_RW
+
+#define SAM_BYTE2
+#define MAC_RUL_M2_SAM_BYTE2_BOFFSET       8
+#define MAC_RUL_M2_SAM_BYTE2_BLEN          8
+#define MAC_RUL_M2_SAM_BYTE2_FLAG          HSL_RW
+
+#define SAM_BYTE3
+#define MAC_RUL_M2_SAM_BYTE3_BOFFSET       0
+#define MAC_RUL_M2_SAM_BYTE3_BLEN          8
+#define MAC_RUL_M2_SAM_BYTE3_FLAG          HSL_RW
+
+
+#define MAC_RUL_M3                         8
+#define MAC_RUL_M3_OFFSET                  0x5900c
+#define MAC_RUL_M3_E_LENGTH                4
+#define MAC_RUL_M3_E_OFFSET                0x20
+#define MAC_RUL_M3_NR_E                    96
+
+#define ETHTYPM
+#define MAC_RUL_M3_ETHTYPM_BOFFSET         16
+#define MAC_RUL_M3_ETHTYPM_BLEN            16
+#define MAC_RUL_M3_ETHTYPM_FLAG            HSL_RW
+
+#define VLANPRIM
+#define MAC_RUL_M3_VLANPRIM_BOFFSET        13
+#define MAC_RUL_M3_VLANPRIM_BLEN           3
+#define MAC_RUL_M3_VLANPRIM_FLAG           HSL_RW
+
+#define VLANCFIM
+#define MAC_RUL_M3_VLANCFIM_BOFFSET        12
+#define MAC_RUL_M3_VLANCFIM_BLEN           1
+#define MAC_RUL_M3_VLANCFIM_FLAG           HSL_RW
+
+#define VLANIDM
+#define MAC_RUL_M3_VLANIDM_BOFFSET         0
+#define MAC_RUL_M3_VLANIDM_BLEN            12
+#define MAC_RUL_M3_VLANIDM_FLAG            HSL_RW
+
+
+#define MAC_RUL_M4                         9
+#define MAC_RUL_M4_OFFSET                  0x59010
+#define MAC_RUL_M4_E_LENGTH                4
+#define MAC_RUL_M4_E_OFFSET                0x20
+#define MAC_RUL_M4_NR_E                    96
+
+#define RULE_VALID
+#define MAC_RUL_M4_RULE_VALID_BOFFSET      6
+#define MAC_RUL_M4_RULE_VALID_BLEN         2
+#define MAC_RUL_M4_RULE_VALID_FLAG         HSL_RW
+
+#define TAGGEDM
+#define MAC_RUL_M4_TAGGEDM_BOFFSET         5
+#define MAC_RUL_M4_TAGGEDM_BLEN            1
+#define MAC_RUL_M4_TAGGEDM_FLAG            HSL_RW
+
+#define TAGGEDV
+#define MAC_RUL_M4_TAGGEDV_BOFFSET         4
+#define MAC_RUL_M4_TAGGEDV_BLEN            1
+#define MAC_RUL_M4_TAGGEDV_FLAG            HSL_RW
+
+#define VIDMSK
+#define MAC_RUL_M4_VIDMSK_BOFFSET          3
+#define MAC_RUL_M4_VIDMSK_BLEN             1
+#define MAC_RUL_M4_VIDMSK_FLAG             HSL_RW
+
+#define RULE_TYP
+#define MAC_RUL_M4_RULE_TYP_BOFFSET        0
+#define MAC_RUL_M4_RULE_TYP_BLEN           3
+#define MAC_RUL_M4_RULE_TYP_FLAG           HSL_RW
+
+
+
+
+    /* IP4 Type Rule Field Define */
+#define IP4_RUL_V0                         0
+#define IP4_RUL_V0_OFFSET                  0x58000
+#define IP4_RUL_V0_E_LENGTH                4
+#define IP4_RUL_V0_E_OFFSET                0x20
+#define IP4_RUL_V0_NR_E                    96
+
+#define DIPV
+#define IP4_RUL_V0_DIPV_BOFFSET            0
+#define IP4_RUL_V0_DIPV_BLEN               32
+#define IP4_RUL_V0_DIPV_FLAG               HSL_RW
+
+
+#define IP4_RUL_V1                         1
+#define IP4_RUL_V1_OFFSET                  0x58004
+#define IP4_RUL_V1_E_LENGTH                4
+#define IP4_RUL_V1_E_OFFSET                0x20
+#define IP4_RUL_V1_NR_E                    96
+
+#define SIPV
+#define IP4_RUL_V1_SIPV_BOFFSET            0
+#define IP4_RUL_V1_SIPV_BLEN               32
+#define IP4_RUL_V1_SIPV_FLAG               HSL_RW
+
+
+#define IP4_RUL_V2                         2
+#define IP4_RUL_V2_OFFSET                  0x58008
+#define IP4_RUL_V2_E_LENGTH                4
+#define IP4_RUL_V2_E_OFFSET                0x20
+#define IP4_RUL_V2_NR_E                    96
+
+#define IP4PROTV
+#define IP4_RUL_V2_IP4PROTV_BOFFSET        0
+#define IP4_RUL_V2_IP4PROTV_BLEN           8
+#define IP4_RUL_V2_IP4PROTV_FLAG           HSL_RW
+
+#define IP4DSCPV
+#define IP4_RUL_V2_IP4DSCPV_BOFFSET        8
+#define IP4_RUL_V2_IP4DSCPV_BLEN           8
+#define IP4_RUL_V2_IP4DSCPV_FLAG           HSL_RW
+
+#define IP4DPORTV
+#define IP4_RUL_V2_IP4DPORTV_BOFFSET       16
+#define IP4_RUL_V2_IP4DPORTV_BLEN          16
+#define IP4_RUL_V2_IP4DPORTV_FLAG          HSL_RW
+
+
+#define IP4_RUL_V3                         3
+#define IP4_RUL_V3_OFFSET                  0x5800c
+#define IP4_RUL_V3_E_LENGTH                4
+#define IP4_RUL_V3_E_OFFSET                0x20
+#define IP4_RUL_V3_NR_E                    96
+
+#define IP4TCPFLAGV
+#define IP4_RUL_V3_IP4TCPFLAGV_BOFFSET     24
+#define IP4_RUL_V3_IP4TCPFLAGV_BLEN        6
+#define IP4_RUL_V3_IP4TCPFLAGV_FLAG        HSL_RW
+
+#define IP4DHCPV
+#define IP4_RUL_V3_IP4DHCPV_BOFFSET        22
+#define IP4_RUL_V3_IP4DHCPV_BLEN           1
+#define IP4_RUL_V3_IP4DHCPV_FLAG           HSL_RW
+
+#define IP4RIPV
+#define IP4_RUL_V3_IP4RIPV_BOFFSET         21
+#define IP4_RUL_V3_IP4RIPV_BLEN            1
+#define IP4_RUL_V3_IP4RIPV_FLAG            HSL_RW
+
+#define ICMP_EN
+#define IP4_RUL_V3_ICMP_EN_BOFFSET         20
+#define IP4_RUL_V3_ICMP_EN_BLEN            1
+#define IP4_RUL_V3_ICMP_EN_FLAG            HSL_RW
+
+#define IP4SPORTV
+#define IP4_RUL_V3_IP4SPORTV_BOFFSET       0
+#define IP4_RUL_V3_IP4SPORTV_BLEN          16
+#define IP4_RUL_V3_IP4SPORTV_FLAG          HSL_RW
+
+#define IP4ICMPTYPV
+#define IP4_RUL_V3_IP4ICMPTYPV_BOFFSET     8
+#define IP4_RUL_V3_IP4ICMPTYPV_BLEN        8
+#define IP4_RUL_V3_IP4ICMPTYPV_FLAG        HSL_RW
+
+#define IP4ICMPCODEV
+#define IP4_RUL_V3_IP4ICMPCODEV_BOFFSET    0
+#define IP4_RUL_V3_IP4ICMPCODEV_BLEN       8
+#define IP4_RUL_V3_IP4ICMPCODEV_FLAG       HSL_RW
+
+
+#define IP4_RUL_V4                         4
+#define IP4_RUL_V4_OFFSET                  0x58010
+#define IP4_RUL_V4_E_LENGTH                4
+#define IP4_RUL_V4_E_OFFSET                0x20
+#define IP4_RUL_V4_NR_E                    96
+
+
+#define IP4_RUL_M0                         5
+#define IP4_RUL_M0_OFFSET                  0x59000
+#define IP4_RUL_M0_E_LENGTH                4
+#define IP4_RUL_M0_E_OFFSET                0x20
+#define IP4_RUL_M0_NR_E                    96
+
+#define DIPM
+#define IP4_RUL_M0_DIPM_BOFFSET            0
+#define IP4_RUL_M0_DIPM_BLEN               32
+#define IP4_RUL_M0_DIPM_FLAG               HSL_RW
+
+
+#define IP4_RUL_M1                         6
+#define IP4_RUL_M1_OFFSET                  0x59004
+#define IP4_RUL_M1_E_LENGTH                4
+#define IP4_RUL_M1_E_OFFSET                0x20
+#define IP4_RUL_M1_NR_E                    96
+
+#define SIPM
+#define IP4_RUL_M1_SIPM_BOFFSET            0
+#define IP4_RUL_M1_SIPM_BLEN               32
+#define IP4_RUL_M1_SIPM_FLAG               HSL_RW
+
+
+#define IP4_RUL_M2                         7
+#define IP4_RUL_M2_OFFSET                  0x59008
+#define IP4_RUL_M2_E_LENGTH                4
+#define IP4_RUL_M2_E_OFFSET                0x20
+#define IP4_RUL_M2_NR_E                    96
+
+#define IP4PROTM
+#define IP4_RUL_M2_IP4PROTM_BOFFSET        0
+#define IP4_RUL_M2_IP4PROTM_BLEN           8
+#define IP4_RUL_M2_IP4PROTM_FLAG           HSL_RW
+
+#define IP4DSCPM
+#define IP4_RUL_M2_IP4DSCPM_BOFFSET        8
+#define IP4_RUL_M2_IP4DSCPM_BLEN           8
+#define IP4_RUL_M2_IP4DSCPM_FLAG           HSL_RW
+
+#define IP4DPORTM
+#define IP4_RUL_M2_IP4DPORTM_BOFFSET       16
+#define IP4_RUL_M2_IP4DPORTM_BLEN          16
+#define IP4_RUL_M2_IP4DPORTM_FLAG          HSL_RW
+
+
+#define IP4_RUL_M3                         8
+#define IP4_RUL_M3_OFFSET                  0x5900c
+#define IP4_RUL_M3_E_LENGTH                4
+#define IP4_RUL_M3_E_OFFSET                0x20
+#define IP4_RUL_M3_NR_E                    96
+
+#define IP4TCPFLAGM
+#define IP4_RUL_M3_IP4TCPFLAGM_BOFFSET     24
+#define IP4_RUL_M3_IP4TCPFLAGM_BLEN        6
+#define IP4_RUL_M3_IP4TCPFLAGM_FLAG        HSL_RW
+
+#define IP4DHCPM
+#define IP4_RUL_M3_IP4DHCPM_BOFFSET        22
+#define IP4_RUL_M3_IP4DHCPM_BLEN           1
+#define IP4_RUL_M3_IP4DHCPM_FLAG           HSL_RW
+
+#define IP4RIPM
+#define IP4_RUL_M3_IP4RIPM_BOFFSET         21
+#define IP4_RUL_M3_IP4RIPM_BLEN            1
+#define IP4_RUL_M3_IP4RIPM_FLAG            HSL_RW
+
+#define IP4DPORTM_EN
+#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET    17
+#define IP4_RUL_M3_IP4DPORTM_EN_BLEN       1
+#define IP4_RUL_M3_IP4DPORTM_EN_FLAG       HSL_RW
+
+#define IP4SPORTM_EN
+#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET    16
+#define IP4_RUL_M3_IP4SPORTM_EN_BLEN       1
+#define IP4_RUL_M3_IP4SPORTM_EN_FLAG       HSL_RW
+
+#define IP4SPORTM
+#define IP4_RUL_M3_IP4SPORTM_BOFFSET       0
+#define IP4_RUL_M3_IP4SPORTM_BLEN          16
+#define IP4_RUL_M3_IP4SPORTM_FLAG          HSL_RW
+
+#define IP4ICMPTYPM
+#define IP4_RUL_M3_IP4ICMPTYPM_BOFFSET     8
+#define IP4_RUL_M3_IP4ICMPTYPM_BLEN        8
+#define IP4_RUL_M3_IP4ICMPTYPM_FLAG        HSL_RW
+
+#define IP4ICMPCODEM
+#define IP4_RUL_M3_IP4ICMPCODEM_BOFFSET    0
+#define IP4_RUL_M3_IP4ICMPCODEM_BLEN       8
+#define IP4_RUL_M3_IP4ICMPCODEM_FLAG       HSL_RW
+
+
+#define IP4_RUL_M4                         9
+#define IP4_RUL_M4_OFFSET                  0x59010
+#define IP4_RUL_M4_E_LENGTH                4
+#define IP4_RUL_M4_E_OFFSET                0x20
+#define IP4_RUL_M4_NR_E                    32
+
+
+
+
+    /* IP6 Type1 Rule Field Define */
+#define IP6_RUL1_V0                        0
+#define IP6_RUL1_V0_OFFSET                 0x58000
+#define IP6_RUL1_V0_E_LENGTH               4
+#define IP6_RUL1_V0_E_OFFSET               0x20
+#define IP6_RUL1_V0_NR_E                   96
+
+#define IP6_DIPV0
+#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET      0
+#define IP6_RUL1_V0_IP6_DIPV0_BLEN         32
+#define IP6_RUL1_V0_IP6_DIPV0_FLAG         HSL_RW
+
+
+#define IP6_RUL1_V1                        1
+#define IP6_RUL1_V1_OFFSET                 0x58004
+#define IP6_RUL1_V1_E_LENGTH               4
+#define IP6_RUL1_V1_E_OFFSET               0x20
+#define IP6_RUL1_V1_NR_E                   96
+
+#define IP6_DIPV1
+#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET      0
+#define IP6_RUL1_V1_IP6_DIPv1_BLEN         32
+#define IP6_RUL1_V1_IP6_DIPV1_FLAG         HSL_RW
+
+
+#define IP6_RUL1_V2                        2
+#define IP6_RUL1_V2_OFFSET                 0x58008
+#define IP6_RUL1_V2_E_LENGTH               4
+#define IP6_RUL1_V2_E_OFFSET               0x20
+#define IP6_RUL1_V2_NR_E                   96
+
+#define IP6_DIPV2
+#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET      0
+#define IP6_RUL1_V2_IP6_DIPv2_BLEN         32
+#define IP6_RUL1_V2_IP6_DIPV2_FLAG         HSL_RW
+
+
+#define IP6_RUL1_V3                        3
+#define IP6_RUL1_V3_OFFSET                 0x5800c
+#define IP6_RUL1_V3_E_LENGTH               4
+#define IP6_RUL1_V3_E_OFFSET               0x20
+#define IP6_RUL1_V3_NR_E                   96
+
+#define IP6_DIPV3
+#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET      0
+#define IP6_RUL1_V3_IP6_DIPv3_BLEN         32
+#define IP6_RUL1_V3_IP6_DIPV3_FLAG         HSL_RW
+
+
+#define IP6_RUL1_V4                        4
+#define IP6_RUL1_V4_OFFSET                 0x58010
+#define IP6_RUL1_V4_E_LENGTH               4
+#define IP6_RUL1_V4_E_OFFSET               0x20
+#define IP6_RUL1_V4_NR_E                   96
+
+
+#define IP6_RUL1_M0                        5
+#define IP6_RUL1_M0_OFFSET                 0x59000
+#define IP6_RUL1_M0_E_LENGTH               4
+#define IP6_RUL1_M0_E_OFFSET               0x20
+#define IP6_RUL1_M0_NR_E                   96
+
+#define IP6_DIPM0
+#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET      0
+#define IP6_RUL1_M0_IP6_DIPM0_BLEN         32
+#define IP6_RUL1_M0_IP6_DIPM0_FLAG         HSL_RW
+
+
+#define IP6_RUL1_M1                        6
+#define IP6_RUL1_M1_OFFSET                 0x59004
+#define IP6_RUL1_M1_E_LENGTH               4
+#define IP6_RUL1_M1_E_OFFSET               0x20
+#define IP6_RUL1_M1_NR_E                   96
+
+#define IP6_DIPM1
+#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET      0
+#define IP6_RUL1_M1_IP6_DIPM1_BLEN         32
+#define IP6_RUL1_M1_IP6_DIPM1_FLAG         HSL_RW
+
+
+#define IP6_RUL1_M2                        7
+#define IP6_RUL1_M2_OFFSET                 0x59008
+#define IP6_RUL1_M2_E_LENGTH               4
+#define IP6_RUL1_M2_E_OFFSET               0x20
+#define IP6_RUL1_M2_NR_E                   96
+
+#define IP6_DIPM2
+#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET      0
+#define IP6_RUL1_M2_IP6_DIPM2_BLEN         32
+#define IP6_RUL1_M2_IP6_DIPM2_FLAG         HSL_RW
+
+
+#define IP6_RUL1_M3                        8
+#define IP6_RUL1_M3_OFFSET                 0x5900c
+#define IP6_RUL1_M3_E_LENGTH               4
+#define IP6_RUL1_M3_E_OFFSET               0x20
+#define IP6_RUL1_M3_NR_E                   96
+
+#define IP6_DIPM3
+#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET      0
+#define IP6_RUL1_M3_IP6_DIPM3_BLEN         32
+#define IP6_RUL1_M3_IP6_DIPM3_FLAG         HSL_RW
+
+
+#define IP6_RUL1_M4                        9
+#define IP6_RUL1_M4_OFFSET                 0x59010
+#define IP6_RUL1_M4_E_LENGTH               4
+#define IP6_RUL1_M4_E_OFFSET               0x20
+#define IP6_RUL1_M4_NR_E                   96
+
+
+
+
+    /* IP6 Type2 Rule Field Define */
+#define IP6_RUL2_V0                        0
+#define IP6_RUL2_V0_OFFSET                 0x58000
+#define IP6_RUL2_V0_E_LENGTH               4
+#define IP6_RUL2_V0_E_OFFSET               0x20
+#define IP6_RUL2_V0_NR_E                   96
+
+#define IP6_SIPV0
+#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET      0
+#define IP6_RUL2_V0_IP6_SIPv0_BLEN         32
+#define IP6_RUL2_V0_IP6_SIPV0_FLAG         HSL_RW
+
+
+#define IP6_RUL2_V1                        1
+#define IP6_RUL2_V1_OFFSET                 0x58004
+#define IP6_RUL2_V1_E_LENGTH               4
+#define IP6_RUL2_V1_E_OFFSET               0x20
+#define IP6_RUL2_V1_NR_E                   96
+
+#define IP6_SIPV1
+#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET      0
+#define IP6_RUL2_V1_IP6_SIPv1_BLEN         32
+#define IP6_RUL2_V1_IP6_SIPV1_FLAG         HSL_RW
+
+
+#define IP6_RUL2_V2                        2
+#define IP6_RUL2_V2_OFFSET                 0x58008
+#define IP6_RUL2_V2_E_LENGTH               4
+#define IP6_RUL2_V2_E_OFFSET               0x20
+#define IP6_RUL2_V2_NR_E                   96
+
+#define IP6_SIPV2
+#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET      0
+#define IP6_RUL2_V2_IP6_SIPv2_BLEN         32
+#define IP6_RUL2_V2_IP6_SIPV2_FLAG         HSL_RW
+
+
+#define IP6_RUL2_V3                        3
+#define IP6_RUL2_V3_OFFSET                 0x5800c
+#define IP6_RUL2_V3_E_LENGTH               4
+#define IP6_RUL2_V3_E_OFFSET               0x20
+#define IP6_RUL2_V3_NR_E                   96
+
+#define IP6_SIPV3
+#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET      0
+#define IP6_RUL2_V3_IP6_SIPv3_BLEN         32
+#define IP6_RUL2_V3_IP6_SIPV3_FLAG         HSL_RW
+
+
+#define IP6_RUL2_V4                        4
+#define IP6_RUL2_V4_OFFSET                 0x58010
+#define IP6_RUL2_V4_E_LENGTH               4
+#define IP6_RUL2_V4_E_OFFSET               0x20
+#define IP6_RUL2_V4_NR_E                   96
+
+
+#define IP6_RUL2_M0                        5
+#define IP6_RUL2_M0_OFFSET                 0x59000
+#define IP6_RUL2_M0_E_LENGTH               4
+#define IP6_RUL2_M0_E_OFFSET               0x20
+#define IP6_RUL2_M0_NR_E                   96
+
+#define IP6_SIPM0
+#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET      0
+#define IP6_RUL2_M0_IP6_SIPM0_BLEN         32
+#define IP6_RUL2_M0_IP6_SIPM0_FLAG         HSL_RW
+
+
+#define IP6_RUL2_M1                        6
+#define IP6_RUL2_M1_OFFSET                 0x59004
+#define IP6_RUL2_M1_E_LENGTH               4
+#define IP6_RUL2_M1_E_OFFSET               0x20
+#define IP6_RUL2_M1_NR_E                   96
+
+#define IP6_SIPM1
+#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET      0
+#define IP6_RUL2_M1_IP6_DIPM1_BLEN         32
+#define IP6_RUL2_M1_IP6_DIPM1_FLAG         HSL_RW
+
+
+#define IP6_RUL2_M2                        7
+#define IP6_RUL2_M2_OFFSET                 0x59008
+#define IP6_RUL2_M2_E_LENGTH               4
+#define IP6_RUL2_M2_E_OFFSET               0x20
+#define IP6_RUL2_M2_NR_E                   96
+
+#define IP6_SIPM2
+#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET      0
+#define IP6_RUL2_M2_IP6_DIPM2_BLEN         32
+#define IP6_RUL2_M2_IP6_DIPM2_FLAG         HSL_RW
+
+
+#define IP6_RUL2_M3                        8
+#define IP6_RUL2_M3_OFFSET                 0x5900c
+#define IP6_RUL2_M3_E_LENGTH               4
+#define IP6_RUL2_M3_E_OFFSET               0x20
+#define IP6_RUL2_M3_NR_E                   96
+
+#define IP6_SIPM3
+#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET      0
+#define IP6_RUL2_M3_IP6_SIPM3_BLEN         32
+#define IP6_RUL2_M3_IP6_SIPM3_FLAG         HSL_RW
+
+
+#define IP6_RUL2_M4                        9
+#define IP6_RUL2_M4_OFFSET                 0x59010
+#define IP6_RUL2_M4_E_LENGTH               4
+#define IP6_RUL2_M4_E_OFFSET               0x20
+#define IP6_RUL2_M4_NR_E                   96
+
+
+
+
+    /* IP6 Type3 Rule Field Define */
+#define IP6_RUL3_V0                        0
+#define IP6_RUL3_V0_OFFSET                 0x58000
+#define IP6_RUL3_V0_E_LENGTH               4
+#define IP6_RUL3_V0_E_OFFSET               0x20
+#define IP6_RUL3_V0_NR_E                   96
+
+#define IP6PROTV
+#define IP6_RUL3_V0_IP6PROTV_BOFFSET       0
+#define IP6_RUL3_V0_IP6PROTV_BLEN          8
+#define IP6_RUL3_V0_IP6PROTV_FLAG          HSL_RW
+
+#define IP6DSCPV
+#define IP6_RUL3_V0_IP6DSCPV_BOFFSET       8
+#define IP6_RUL3_V0_IP6DSCPV_BLEN          8
+#define IP6_RUL3_V0_IP6DSCPV_FLAG          HSL_RW
+
+
+#define IP6_RUL3_V1                        1
+#define IP6_RUL3_V1_OFFSET                 0x58004
+#define IP6_RUL3_V1_E_LENGTH               4
+#define IP6_RUL3_V1_E_OFFSET               0x20
+#define IP6_RUL3_V1_NR_E                   96
+
+#define IP6LABEL1V
+#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET     16
+#define IP6_RUL3_V1_IP6LABEL1V_BLEN        16
+#define IP6_RUL3_V1_IP6LABEL1V_FLAG        HSL_RW
+
+
+#define IP6_RUL3_V2                        2
+#define IP6_RUL3_V2_OFFSET                 0x58008
+#define IP6_RUL3_V2_E_LENGTH               4
+#define IP6_RUL3_V2_E_OFFSET               0x20
+#define IP6_RUL3_V2_NR_E                   96
+
+#define IP6LABEL2V
+#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET     0
+#define IP6_RUL3_V2_IP6LABEL2V_BLEN        4
+#define IP6_RUL3_V2_IP6LABEL2V_FLAG        HSL_RW
+
+#define IP6DPORTV
+#define IP6_RUL3_V2_IP6DPORTV_BOFFSET      16
+#define IP6_RUL3_V2_IP6DPORTV_BLEN         16
+#define IP6_RUL3_V2_IP6DPORTV_FLAG         HSL_RW
+
+
+#define IP6_RUL3_V3                        3
+#define IP6_RUL3_V3_OFFSET                 0x5800c
+#define IP6_RUL3_V3_E_LENGTH               4
+#define IP6_RUL3_V3_E_OFFSET               0x20
+#define IP6_RUL3_V3_NR_E                   96
+
+#define IP6TCPFLAGV
+#define IP6_RUL3_V3_IP6TCPFLAGV_BOFFSET    24
+#define IP6_RUL3_V3_IP6TCPFLAGV_BLEN       6
+#define IP6_RUL3_V3_IP6TCPFLAGV_FLAG       HSL_RW
+
+#define IP6FWDTYPV
+#define IP6_RUL3_V3_IP6FWDTYPV_BOFFSET     23
+#define IP6_RUL3_V3_IP6FWDTYPV_BLEN        1
+#define IP6_RUL3_V3_IP6FWDTYPV_FLAG        HSL_RW
+
+#define IP6DHCPV
+#define IP6_RUL3_V3_IP6DHCPV_BOFFSET       22
+#define IP6_RUL3_V3_IP6DHCPV_BLEN          1
+#define IP6_RUL3_V3_IP6DHCPV_FLAG          HSL_RW
+
+#define ICMP6_EN
+#define IP6_RUL3_V3_ICMP6_EN_BOFFSET       20
+#define IP6_RUL3_V3_ICMP6_EN_BLEN          1
+#define IP6_RUL3_V3_ICMP6_EN_FLAG          HSL_RW
+
+#define IP6SPORTV
+#define IP6_RUL3_V3_IP6SPORTV_BOFFSET      0
+#define IP6_RUL3_V3_IP6SPORTV_BLEN         16
+#define IP6_RUL3_V3_IP6SPORTV_FLAG         HSL_RW
+
+#define IP6ICMPTYPV
+#define IP6_RUL3_V3_IP6ICMPTYPV_BOFFSET    8
+#define IP6_RUL3_V3_IP6ICMPTYPV_BLEN       8
+#define IP6_RUL3_V3_IP6ICMPTYPV_FLAG       HSL_RW
+
+#define IP6ICMPCODEV
+#define IP6_RUL3_V3_IP6ICMPCODEV_BOFFSET   0
+#define IP6_RUL3_V3_IP6ICMPCODEV_BLEN      8
+#define IP6_RUL3_V3_IP6ICMPCODEV_FLAG      HSL_RW
+
+
+#define IP6_RUL3_V4                        4
+#define IP6_RUL3_V4_OFFSET                 0x58010
+#define IP6_RUL3_V4_E_LENGTH               4
+#define IP6_RUL3_V4_E_OFFSET               0x20
+#define IP6_RUL3_V4_NR_E                   96
+
+
+#define IP6_RUL3_M0                        5
+#define IP6_RUL3_M0_OFFSET                 0x59000
+#define IP6_RUL3_M0_E_LENGTH               4
+#define IP6_RUL3_M0_E_OFFSET               0x20
+#define IP6_RUL3_M0_NR_E                   96
+
+#define IP6PROTM
+#define IP6_RUL3_M0_IP6PROTM_BOFFSET       0
+#define IP6_RUL3_M0_IP6PROTM_BLEN          8
+#define IP6_RUL3_M0_IP6PROTM_FLAG          HSL_RW
+
+#define IP6DSCPM
+#define IP6_RUL3_M0_IP6DSCPM_BOFFSET       8
+#define IP6_RUL3_M0_IP6DSCPM_BLEN          8
+#define IP6_RUL3_M0_IP6DSCPM_FLAG          HSL_RW
+
+
+#define IP6_RUL3_M1                        6
+#define IP6_RUL3_M1_OFFSET                 0x59004
+#define IP6_RUL3_M1_E_LENGTH               4
+#define IP6_RUL3_M1_E_OFFSET               0x20
+#define IP6_RUL3_M1_NR_E                   96
+
+#define IP6LABEL1M
+#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET     16
+#define IP6_RUL3_M1_IP6LABEL1M_BLEN        16
+#define IP6_RUL3_M1_IP6LABEL1M_FLAG        HSL_RW
+
+
+#define IP6_RUL3_M2                        7
+#define IP6_RUL3_M2_OFFSET                 0x59008
+#define IP6_RUL3_M2_E_LENGTH               4
+#define IP6_RUL3_M2_E_OFFSET               0x20
+#define IP6_RUL3_M2_NR_E                   96
+
+#define IP6LABEL2M
+#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET     0
+#define IP6_RUL3_M2_IP6LABEL2M_BLEN        4
+#define IP6_RUL3_M2_IP6LABEL21M_FLAG       HSL_RW
+
+#define IP6DPORTM
+#define IP6_RUL3_M2_IP6DPORTM_BOFFSET      16
+#define IP6_RUL3_M2_IP6DPORTM_BLEN         16
+#define IP6_RUL3_M2_IP6DPORTM_FLAG         HSL_RW
+
+
+#define IP6_RUL3_M3                        8
+#define IP6_RUL3_M3_OFFSET                 0x5900c
+#define IP6_RUL3_M3_E_LENGTH               4
+#define IP6_RUL3_M3_E_OFFSET               0x20
+#define IP6_RUL3_M3_NR_E                   96
+
+#define IP6TCPFLAGM
+#define IP6_RUL3_M3_IP6TCPFLAGM_BOFFSET    24
+#define IP6_RUL3_M3_IP6TCPFLAGM_BLEN       6
+#define IP6_RUL3_M3_IP6TCPFLAGM_FLAG       HSL_RW
+
+#define IP6RWDTYPM
+#define IP6_RUL3_M3_IP6RWDTYPV_BOFFSET     23
+#define IP6_RUL3_M3_IP6RWDTYPV_BLEN        1
+#define IP6_RUL3_M3_IP6RWDTYPV_FLAG        HSL_RW
+
+#define IP6DHCPM
+#define IP6_RUL3_M3_IP6DHCPM_BOFFSET       22
+#define IP6_RUL3_M3_IP6DHCPM_BLEN          1
+#define IP6_RUL3_M3_IP6DHCPM_FLAG          HSL_RW
+
+#define IP6DPORTM_EN
+#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET   17
+#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN      1
+#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG      HSL_RW
+
+#define IP6SPORTM_EN
+#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET   16
+#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN      1
+#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG      HSL_RW
+
+#define IP6SPORTM
+#define IP6_RUL3_M3_IP6SPORTM_BOFFSET      0
+#define IP6_RUL3_M3_IP6SPORTM_BLEN         16
+#define IP6_RUL3_M3_IP6SPORTM_FLAG         HSL_RW
+
+#define IP6ICMPTYPM
+#define IP6_RUL3_M3_IP6ICMPTYPM_BOFFSET     8
+#define IP6_RUL3_M3_IP6ICMPTYPM_BLEN        8
+#define IP6_RUL3_M3_IP6ICMPTYPM_FLAG        HSL_RW
+
+#define IP6ICMPCODEM
+#define IP6_RUL3_M3_IP6ICMPCODEM_BOFFSET    0
+#define IP6_RUL3_M3_IP6ICMPCODEM_BLEN       8
+#define IP6_RUL3_M3_IP6ICMPCODEM_FLAG       HSL_RW
+
+
+#define IP6_RUL3_M4                        9
+#define IP6_RUL3_M4_OFFSET                 0x59010
+#define IP6_RUL3_M4_E_LENGTH               4
+#define IP6_RUL3_M4_E_OFFSET               0x20
+#define IP6_RUL3_M4_NR_E                   96
+
+
+
+
+    /* Enhanced MAC Type Rule Field Define */
+#define EHMAC_RUL_V0                         0
+#define EHMAC_RUL_V0_OFFSET                  0x58000
+#define EHMAC_RUL_V0_E_LENGTH                4
+#define EHMAC_RUL_V0_E_OFFSET                0x20
+#define EHMAC_RUL_V0_NR_E                    96
+
+#define DAV_BYTE2
+#define EHMAC_RUL_V0_DAV_BYTE2_BOFFSET       24
+#define EHMAC_RUL_V0_DAV_BYTE2_BLEN          8
+#define EHMAC_RUL_V0_DAV_BYTE2_FLAG          HSL_RW
+
+#define DAV_BYTE3
+#define EHMAC_RUL_V0_DAV_BYTE3_BOFFSET       16
+#define EHMAC_RUL_V0_DAV_BYTE3_BLEN          8
+#define EHMAC_RUL_V0_DAV_BYTE3_FLAG          HSL_RW
+
+#define DAV_BYTE4
+#define EHMAC_RUL_V0_DAV_BYTE4_BOFFSET       8
+#define EHMAC_RUL_V0_DAV_BYTE4_BLEN          8
+#define EHMAC_RUL_V0_DAV_BYTE4_FLAG          HSL_RW
+
+#define DAV_BYTE5
+#define EHMAC_RUL_V0_DAV_BYTE5_BOFFSET       0
+#define EHMAC_RUL_V0_DAV_BYTE5_BLEN          8
+#define EHMAC_RUL_V0_DAV_BYTE5_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_V1                         1
+#define EHMAC_RUL_V1_OFFSET                  0x58004
+#define EHMAC_RUL_V1_E_LENGTH                4
+#define EHMAC_RUL_V1_E_OFFSET                0x20
+#define EHMAC_RUL_V1_NR_E                    96
+
+#define SAV_BYTE4
+#define EHMAC_RUL_V1_SAV_BYTE4_BOFFSET       24
+#define EHMAC_RUL_V1_SAV_BYTE4_BLEN          8
+#define EHMAC_RUL_V1_SAV_BYTE4_FLAG          HSL_RW
+
+#define SAV_BYTE5
+#define EHMAC_RUL_V1_SAV_BYTE5_BOFFSET       16
+#define EHMAC_RUL_V1_SAV_BYTE5_BLEN          8
+#define EHMAC_RUL_V1_SAV_BYTE5_FLAG          HSL_RW
+
+#define DAV_BYTE0
+#define EHMAC_RUL_V1_DAV_BYTE0_BOFFSET       8
+#define EHMAC_RUL_V1_DAV_BYTE0_BLEN          8
+#define EHMAC_RUL_V1_DAV_BYTE0_FLAG          HSL_RW
+
+#define DAV_BYTE1
+#define EHMAC_RUL_V1_DAV_BYTE1_BOFFSET       0
+#define EHMAC_RUL_V1_DAV_BYTE1_BLEN          8
+#define EHMAC_RUL_V1_DAV_BYTE1_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_V2                         2
+#define EHMAC_RUL_V2_OFFSET                  0x58008
+#define EHMAC_RUL_V2_E_LENGTH                4
+#define EHMAC_RUL_V2_E_OFFSET                0x20
+#define EHMAC_RUL_V2_NR_E                    96
+
+#define CTAG_VIDLV
+#define EHMAC_RUL_V2_CTAG_VIDLV_BOFFSET      24
+#define EHMAC_RUL_V2_CTAG_VIDLV_BLEN         8
+#define EHMAC_RUL_V2_CTAG_VIDLV_FLAG         HSL_RW
+
+#define STAG_PRIV
+#define EHMAC_RUL_V2_STAG_PRIV_BOFFSET       21
+#define EHMAC_RUL_V2_STAG_PRIV_BLEN          3
+#define EHMAC_RUL_V2_STAG_PRIV_FLAG          HSL_RW
+
+#define STAG_DEIV
+#define EHMAC_RUL_V2_STAG_DEIV_BOFFSET       20
+#define EHMAC_RUL_V2_STAG_DEIV_BLEN          1
+#define EHMAC_RUL_V2_STAG_DEIV_FLAG          HSL_RW
+
+#define STAG_VIDV
+#define EHMAC_RUL_V2_STAG_VIDV_BOFFSET       8
+#define EHMAC_RUL_V2_STAG_VIDV_BLEN          12
+#define EHMAC_RUL_V2_STAG_VIDV_FLAG          HSL_RW
+
+#define SAV_BYTE3
+#define EHMAC_RUL_V2_SAV_BYTE3_BOFFSET       0
+#define EHMAC_RUL_V2_SAV_BYTE3_BLEN          8
+#define EHMAC_RUL_V2_SAV_BYTE3_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_V3                         3
+#define EHMAC_RUL_V3_ID                      13
+#define EHMAC_RUL_V3_OFFSET                  0x5800c
+#define EHMAC_RUL_V3_E_LENGTH                4
+#define EHMAC_RUL_V3_E_OFFSET                0x20
+#define EHMAC_RUL_V3_NR_E                    96
+
+#define STAGGEDM
+#define EHMAC_RUL_V3_STAGGEDM_BOFFSET         31
+#define EHMAC_RUL_V3_STAGGEDM_BLEN            1
+#define EHMAC_RUL_V3_STAGGEDM_FLAG            HSL_RW
+
+#define STAGGEDV
+#define EHMAC_RUL_V3_STAGGEDV_BOFFSET         30
+#define EHMAC_RUL_V3_STAGGEDV_BLEN            1
+#define EHMAC_RUL_V3_STAGGEDV_FLAG            HSL_RW
+
+#define DA_EN
+#define EHMAC_RUL_V3_DA_EN_BOFFSET          25
+#define EHMAC_RUL_V3_DA_EN_BLEN             1
+#define EHMAC_RUL_V3_DA_EN_FLAG             HSL_RW
+
+#define SVIDMSK
+#define EHMAC_RUL_V3_SVIDMSK_BOFFSET          24
+#define EHMAC_RUL_V3_SVIDMSK_BLEN             1
+#define EHMAC_RUL_V3_SVIDMSK_FLAG             HSL_RW
+
+#define ETHTYPV
+#define EHMAC_RUL_V3_ETHTYPV_BOFFSET         8
+#define EHMAC_RUL_V3_ETHTYPV_BLEN            16
+#define EHMAC_RUL_V3_ETHTYPV_FLAG            HSL_RW
+
+#define CTAG_PRIV
+#define EHMAC_RUL_V3_CTAG_PRIV_BOFFSET       5
+#define EHMAC_RUL_V3_CTAG_PRIV_BLEN          3
+#define EHMAC_RUL_V3_CTAG_PRIV_FLAG          HSL_RW
+
+#define CTAG_CFIV
+#define EHMAC_RUL_V3_CTAG_CFIV_BOFFSET       4
+#define EHMAC_RUL_V3_CTAG_CFIV_BLEN          1
+#define EHMAC_RUL_V3_CTAG_CFIV_FLAG          HSL_RW
+
+#define CTAG_VIDHV
+#define EHMAC_RUL_V3_CTAG_VIDHV_BOFFSET      0
+#define EHMAC_RUL_V3_CTAG_VIDHV_BLEN         4
+#define EHMAC_RUL_V3_CTAG_VIDHV_FLAG         HSL_RW
+
+
+#define EHMAC_RUL_V4                         4
+#define EHMAC_RUL_V4_OFFSET                  0x58010
+#define EHMAC_RUL_V4_E_LENGTH                4
+#define EHMAC_RUL_V4_E_OFFSET                0x20
+#define EHMAC_RUL_V4_NR_E                    96
+
+
+#define EHMAC_RUL_M0                         5
+#define EHMAC_RUL_M0_OFFSET                  0x59000
+#define EHMAC_RUL_M0_E_LENGTH                4
+#define EHMAC_RUL_M0_E_OFFSET                0x20
+#define EHMAC_RUL_M0_NR_E                    96
+
+#define DAM_BYTE2
+#define EHMAC_RUL_M0_DAM_BYTE2_BOFFSET       24
+#define EHMAC_RUL_M0_DAM_BYTE2_BLEN          8
+#define EHMAC_RUL_M0_DAM_BYTE2_FLAG          HSL_RW
+
+#define DAM_BYTE3
+#define EHMAC_RUL_M0_DAM_BYTE3_BOFFSET       16
+#define EHMAC_RUL_M0_DAM_BYTE3_BLEN          8
+#define EHMAC_RUL_M0_DAM_BYTE3_FLAG          HSL_RW
+
+#define DAM_BYTE4
+#define EHMAC_RUL_M0_DAM_BYTE4_BOFFSET       8
+#define EHMAC_RUL_M0_DAM_BYTE4_BLEN          8
+#define EHMAC_RUL_M0_DAM_BYTE4_FLAG          HSL_RW
+
+#define DAM_BYTE5
+#define EHMAC_RUL_M0_DAM_BYTE5_BOFFSET       0
+#define EHMAC_RUL_M0_DAM_BYTE5_BLEN          8
+#define EHMAC_RUL_M0_DAM_BYTE5_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_M1                         6
+#define EHMAC_RUL_M1_OFFSET                  0x59004
+#define EHMAC_RUL_M1_E_LENGTH                4
+#define EHMAC_RUL_M1_E_OFFSET                0x20
+#define EHMAC_RUL_M1_NR_E                    96
+
+#define SAM_BYTE4
+#define EHMAC_RUL_M1_SAM_BYTE4_BOFFSET       24
+#define EHMAC_RUL_M1_SAM_BYTE4_BLEN          8
+#define EHMAC_RUL_M1_SAM_BYTE4_FLAG          HSL_RW
+
+#define SAM_BYTE5
+#define EHMAC_RUL_M1_SAM_BYTE5_BOFFSET       16
+#define EHMAC_RUL_M1_SAM_BYTE5_BLEN          8
+#define EHMAC_RUL_M1_SAM_BYTE5_FLAG          HSL_RW
+
+#define DAM_BYTE0
+#define EHMAC_RUL_M1_DAM_BYTE0_BOFFSET       8
+#define EHMAC_RUL_M1_DAM_BYTE0_BLEN          8
+#define EHMAC_RUL_M1_DAM_BYTE0_FLAG          HSL_RW
+
+#define DAM_BYTE1
+#define EHMAC_RUL_M1_DAM_BYTE1_BOFFSET       0
+#define EHMAC_RUL_M1_DAM_BYTE1_BLEN          8
+#define EHMAC_RUL_M1_DAM_BYTE1_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_M2                         7
+#define EHMAC_RUL_M2_OFFSET                  0x59008
+#define EHMAC_RUL_M2_E_LENGTH                4
+#define EHMAC_RUL_M2_E_OFFSET                0x20
+#define EHMAC_RUL_M2_NR_E                    96
+
+#define CTAG_VIDLM
+#define EHMAC_RUL_M2_CTAG_VIDLM_BOFFSET      24
+#define EHMAC_RUL_M2_CTAG_VIDLM_BLEN         8
+#define EHMAC_RUL_M2_CTAG_VIDLM_FLAG         HSL_RW
+
+#define STAG_PRIM
+#define EHMAC_RUL_M2_STAG_PRIM_BOFFSET       21
+#define EHMAC_RUL_M2_STAG_PRIM_BLEN          3
+#define EHMAC_RUL_M2_STAG_PRIM_FLAG          HSL_RW
+
+#define STAG_DEIM
+#define EHMAC_RUL_M2_STAG_DEIM_BOFFSET       20
+#define EHMAC_RUL_M2_STAG_DEIM_BLEN          1
+#define EHMAC_RUL_M2_STAG_DEIM_FLAG          HSL_RW
+
+#define STAG_VIDM
+#define EHMAC_RUL_M2_STAG_VIDM_BOFFSET       8
+#define EHMAC_RUL_M2_STAG_VIDM_BLEN          12
+#define EHMAC_RUL_M2_STAG_VIDM_FLAG          HSL_RW
+
+#define SAM_BYTE3
+#define EHMAC_RUL_M2_SAM_BYTE3_BOFFSET       0
+#define EHMAC_RUL_M2_SAM_BYTE3_BLEN          8
+#define EHMAC_RUL_M2_SAM_BYTE3_FLAG          HSL_RW
+
+
+#define EHMAC_RUL_M3                         8
+#define EHMAC_RUL_M3_OFFSET                  0x5900c
+#define EHMAC_RUL_M3_E_LENGTH                4
+#define EHMAC_RUL_M3_E_OFFSET                0x20
+#define EHMAC_RUL_M3_NR_E                    96
+
+#define ETHTYPM
+#define EHMAC_RUL_M3_ETHTYPM_BOFFSET         8
+#define EHMAC_RUL_M3_ETHTYPM_BLEN            16
+#define EHMAC_RUL_M3_ETHTYPM_FLAG            HSL_RW
+
+#define CTAG_PRIM
+#define EHMAC_RUL_M3_CTAG_PRIM_BOFFSET       5
+#define EHMAC_RUL_M3_CTAG_PRIM_BLEN          3
+#define EHMAC_RUL_M3_CTAG_PRIM_FLAG          HSL_RW
+
+#define CTAG_CFIM
+#define EHMAC_RUL_M3_CTAG_CFIM_BOFFSET       4
+#define EHMAC_RUL_M3_CTAG_CFIM_BLEN          1
+#define EHMAC_RUL_M3_CTAG_CFIM_FLAG          HSL_RW
+
+#define CTAG_VIDHM
+#define EHMAC_RUL_M3_CTAG_VIDHM_BOFFSET      0
+#define EHMAC_RUL_M3_CTAG_VIDHM_BLEN         4
+#define EHMAC_RUL_M3_CTAG_VIDHM_FLAG         HSL_RW
+
+
+#define EHMAC_RUL_M4                         9
+#define EHMAC_RUL_M4_OFFSET                  0x59010
+#define EHMAC_RUL_M4_E_LENGTH                4
+#define EHMAC_RUL_M4_E_OFFSET                0x20
+#define EHMAC_RUL_M4_NR_E                    96
+
+#define CTAGGEDM
+#define EHMAC_RUL_M4_CTAGGEDM_BOFFSET        5
+#define EHMAC_RUL_M4_CTAGGEDM_BLEN           1
+#define EHMAC_RUL_M4_CTAGGEDM_FLAG           HSL_RW
+
+#define CTAGGEDV
+#define EHMAC_RUL_M4_CTAGGEDV_BOFFSET        4
+#define EHMAC_RUL_M4_CTAGGEDV_BLEN           1
+#define EHMAC_RUL_M4_CTAGGEDV_FLAG           HSL_RW
+
+#define CVIDMSK
+#define EHMAC_RUL_M4_CVIDMSK_BOFFSET         3
+#define EHMAC_RUL_M4_CVIDMSK_BLEN            1
+#define EHMAC_RUL_M4_CVIDMSK_FLAG            HSL_RW
+
+
+
+
+    /* PPPoE Session Table Define */
+#define PPPOE_SESSION
+#define PPPOE_SESSION_OFFSET                       0x5f000
+#define PPPOE_SESSION_E_LENGTH                     4
+#define PPPOE_SESSION_E_OFFSET                     0x4
+#define PPPOE_SESSION_NR_E                         16
+
+#define ENTRY_VALID
+#define PPPOE_SESSION_ENTRY_VALID_BOFFSET          16
+#define PPPOE_SESSION_ENTRY_VALID_BLEN             2
+#define PPPOE_SESSION_ENTRY_VALID_FLAG             HSL_RW
+
+#define SEESION_ID
+#define PPPOE_SESSION_SEESION_ID_BOFFSET           0
+#define PPPOE_SESSION_SEESION_ID_BLEN              16
+#define PPPOE_SESSION_SEESION_ID_FLAG              HSL_RW
+
+
+#define PPPOE_EDIT
+#define PPPOE_EDIT_OFFSET                       0x02200
+#define PPPOE_EDIT_E_LENGTH                     4
+#define PPPOE_EDIT_E_OFFSET                     0x10
+#define PPPOE_EDIT_NR_E                         16
+
+#define EDIT_ID
+#define PPPOE_EDIT_EDIT_ID_BOFFSET              0
+#define PPPOE_EDIT_EDIT_ID_BLEN                 16
+#define PPPOE_EDIT_EDIT_ID_FLAG                 HSL_RW
+
+
+
+
+    /* L3 Host Entry Define */
+#define HOST_ENTRY0
+#define HOST_ENTRY0_OFFSET                       0x0e80
+#define HOST_ENTRY0_E_LENGTH                     4
+#define HOST_ENTRY0_E_OFFSET                     0x0
+#define HOST_ENTRY0_NR_E                         1
+
+#define IP_ADDR
+#define HOST_ENTRY0_IP_ADDR_BOFFSET              0
+#define HOST_ENTRY0_IP_ADDR_BLEN                 32
+#define HOST_ENTRY0_IP_ADDR_FLAG                 HSL_RW
+
+
+#define HOST_ENTRY1
+#define HOST_ENTRY1_OFFSET                       0x0e84
+#define HOST_ENTRY1_E_LENGTH                     4
+#define HOST_ENTRY1_E_OFFSET                     0x0
+#define HOST_ENTRY1_NR_E                         1
+
+
+#define HOST_ENTRY2
+#define HOST_ENTRY2_OFFSET                       0x0e88
+#define HOST_ENTRY2_E_LENGTH                     4
+#define HOST_ENTRY2_E_OFFSET                     0x0
+#define HOST_ENTRY2_NR_E                         1
+
+
+#define HOST_ENTRY3
+#define HOST_ENTRY3_OFFSET                       0x0e8c
+#define HOST_ENTRY3_E_LENGTH                     4
+#define HOST_ENTRY3_E_OFFSET                     0x0
+#define HOST_ENTRY3_NR_E                         1
+
+
+#define HOST_ENTRY4
+#define HOST_ENTRY4_OFFSET                       0x0e90
+#define HOST_ENTRY4_E_LENGTH                     4
+#define HOST_ENTRY4_E_OFFSET                     0x0
+#define HOST_ENTRY4_NR_E                         1
+
+#define MAC_ADDR2
+#define HOST_ENTRY4_MAC_ADDR2_BOFFSET            24
+#define HOST_ENTRY4_MAC_ADDR2_BLEN               8
+#define HOST_ENTRY4_MAC_ADDR2_FLAG               HSL_RW
+
+#define MAC_ADDR3
+#define HOST_ENTRY4_MAC_ADDR3_BOFFSET            16
+#define HOST_ENTRY4_MAC_ADDR3_BLEN               8
+#define HOST_ENTRY4_MAC_ADDR3_FLAG               HSL_RW
+
+#define MAC_ADDR4
+#define HOST_ENTRY4_MAC_ADDR4_BOFFSET            8
+#define HOST_ENTRY4_MAC_ADDR4_BLEN               8
+#define HOST_ENTRY4_MAC_ADDR4_FLAG               HSL_RW
+
+#define MAC_ADDR5
+#define HOST_ENTRY4_MAC_ADDR5_BOFFSET            0
+#define HOST_ENTRY4_MAC_ADDR5_BLEN               8
+#define HOST_ENTRY4_MAC_ADDR5_FLAG               HSL_RW
+
+#define HOST_ENTRY5
+#define HOST_ENTRY5_OFFSET                       0x0e94
+#define HOST_ENTRY5_E_LENGTH                     4
+#define HOST_ENTRY5_E_OFFSET                     0x0
+#define HOST_ENTRY5_NR_E                         1
+
+#define CPU_ADDR
+#define HOST_ENTRY5_CPU_ADDR_BOFFSET             31
+#define HOST_ENTRY5_CPU_ADDR_BLEN                1
+#define HOST_ENTRY5_CPU_ADDR_FLAG                HSL_RW
+
+#define SRC_PORT
+#define HOST_ENTRY5_SRC_PORT_BOFFSET             28
+#define HOST_ENTRY5_SRC_PORT_BLEN                3
+#define HOST_ENTRY5_SRC_PORT_FLAG                HSL_RW
+
+#define INTF_ID
+#define HOST_ENTRY5_INTF_ID_BOFFSET              16
+#define HOST_ENTRY5_INTF_ID_BLEN                 12
+#define HOST_ENTRY5_INTF_ID_FLAG                 HSL_RW
+
+#define MAC_ADDR0
+#define HOST_ENTRY5_MAC_ADDR0_BOFFSET            8
+#define HOST_ENTRY5_MAC_ADDR0_BLEN               8
+#define HOST_ENTRY5_MAC_ADDR0_FLAG               HSL_RW
+
+#define MAC_ADDR1
+#define HOST_ENTRY5_MAC_ADDR1_BOFFSET            0
+#define HOST_ENTRY5_MAC_ADDR1_BLEN               8
+#define HOST_ENTRY5_MAC_ADDR1_FLAG               HSL_RW
+
+
+#define HOST_ENTRY6
+#define HOST_ENTRY6_OFFSET                       0x0e98
+#define HOST_ENTRY6_E_LENGTH                     4
+#define HOST_ENTRY6_E_OFFSET                     0x0
+#define HOST_ENTRY6_NR_E                         1
+
+#define IP_VER
+#define HOST_ENTRY6_IP_VER_BOFFSET               15
+#define HOST_ENTRY6_IP_VER_BLEN                  1
+#define HOST_ENTRY6_IP_VER_FLAG                  HSL_RW
+
+#define AGE_FLAG
+#define HOST_ENTRY6_AGE_FLAG_BOFFSET             12
+#define HOST_ENTRY6_AGE_FLAG_BLEN                3
+#define HOST_ENTRY6_AGE_FLAG_FLAG                HSL_RW
+
+#define PPPOE_EN
+#define HOST_ENTRY6_PPPOE_EN_BOFFSET             11
+#define HOST_ENTRY6_PPPOE_EN_BLEN                1
+#define HOST_ENTRY6_PPPOE_EN_FLAG                HSL_RW
+
+#define PPPOE_IDX
+#define HOST_ENTRY6_PPPOE_IDX_BOFFSET            7
+#define HOST_ENTRY6_PPPOE_IDX_BLEN               4
+#define HOST_ENTRY6_PPPOE_IDX_FLAG               HSL_RW
+
+#define CNT_EN
+#define HOST_ENTRY6_CNT_EN_BOFFSET               6
+#define HOST_ENTRY6_CNT_EN_BLEN                  1
+#define HOST_ENTRY6_CNT_EN_FLAG                  HSL_RW
+
+#define CNT_IDX
+#define HOST_ENTRY6_CNT_IDX_BOFFSET              2
+#define HOST_ENTRY6_CNT_IDX_BLEN                 4
+#define HOST_ENTRY6_CNT_IDX_FLAG                 HSL_RW
+
+#define ACTION
+#define HOST_ENTRY6_ACTION_BOFFSET               0
+#define HOST_ENTRY6_ACTION_BLEN                  2
+#define HOST_ENTRY6_ACTION_FLAG                  HSL_RW
+
+
+#define HOST_ENTRY7
+#define HOST_ENTRY7_OFFSET                       0x0e58
+#define HOST_ENTRY7_E_LENGTH                     4
+#define HOST_ENTRY7_E_OFFSET                     0x0
+#define HOST_ENTRY7_NR_E                         1
+
+#define TBL_BUSY
+#define HOST_ENTRY7_TBL_BUSY_BOFFSET             31
+#define HOST_ENTRY7_TBL_BUSY_BLEN                1
+#define HOST_ENTRY7_TBL_BUSY_FLAG                HSL_RW
+
+#define SPEC_SP
+#define HOST_ENTRY7_SPEC_SP_BOFFSET              22
+#define HOST_ENTRY7_SPEC_SP_BLEN                 1
+#define HOST_ENTRY7_SPEC_SP_FLAG                 HSL_RW
+
+#define SPEC_VID
+#define HOST_ENTRY7_SPEC_VID_BOFFSET             21
+#define HOST_ENTRY7_SPEC_VID_BLEN                1
+#define HOST_ENTRY7_SPEC_VID_FLAG                HSL_RW
+
+#define SPEC_PIP
+#define HOST_ENTRY7_SPEC_PIP_BOFFSET             20
+#define HOST_ENTRY7_SPEC_PIP_BLEN                1
+#define HOST_ENTRY7_SPEC_PIP_FLAG                HSL_RW
+
+#define SPEC_SIP
+#define HOST_ENTRY7_SPEC_SIP_BOFFSET             19
+#define HOST_ENTRY7_SPEC_SIP_BLEN                1
+#define HOST_ENTRY7_SPEC_SIP_FLAG                HSL_RW
+
+#define SPEC_STATUS
+#define HOST_ENTRY7_SPEC_STATUS_BOFFSET          18
+#define HOST_ENTRY7_SPEC_STATUS_BLEN             1
+#define HOST_ENTRY7_SPEC_STATUS_FLAG             HSL_RW
+
+#define TBL_IDX
+#define HOST_ENTRY7_TBL_IDX_BOFFSET              8
+#define HOST_ENTRY7_TBL_IDX_BLEN                 10
+#define HOST_ENTRY7_TBL_IDX_FLAG                 HSL_RW
+
+#define TBL_STAUS
+#define HOST_ENTRY7_TBL_STAUS_BOFFSET            7
+#define HOST_ENTRY7_TBL_STAUS_BLEN               1
+#define HOST_ENTRY7_TBL_STAUS_FLAG               HSL_RW
+
+#define TBL_SEL
+#define HOST_ENTRY7_TBL_SEL_BOFFSET              4
+#define HOST_ENTRY7_TBL_SEL_BLEN                 2
+#define HOST_ENTRY7_TBL_SEL_FLAG                 HSL_RW
+
+#define ENTRY_FUNC
+#define HOST_ENTRY7_ENTRY_FUNC_BOFFSET           0
+#define HOST_ENTRY7_ENTRY_FUNC_BLEN              3
+#define HOST_ENTRY7_ENTRY_FUNC_FLAG              HSL_RW
+
+
+
+
+#define NAT_ENTRY0
+#define NAT_ENTRY0_OFFSET                       0x0e80
+#define NAT_ENTRY0_E_LENGTH                     4
+#define NAT_ENTRY0_E_OFFSET                     0x0
+#define NAT_ENTRY0_NR_E                         1
+
+#define IP_ADDR
+#define NAT_ENTRY0_IP_ADDR_BOFFSET              0
+#define NAT_ENTRY0_IP_ADDR_BLEN                 32
+#define NAT_ENTRY0_IP_ADDR_FLAG                 HSL_RW
+
+
+#define NAT_ENTRY1
+#define NAT_ENTRY1_OFFSET                       0x0e84
+#define NAT_ENTRY1_E_LENGTH                     4
+#define NAT_ENTRY1_E_OFFSET                     0x0
+#define NAT_ENTRY1_NR_E                         1
+
+#define PRV_IPADDR0
+#define NAT_ENTRY1_PRV_IPADDR0_BOFFSET          24
+#define NAT_ENTRY1_PRV_IPADDR0_BLEN             8
+#define NAT_ENTRY1_PRV_IPADDR0_FLAG             HSL_RW
+
+#define PORT_RANGE
+#define NAT_ENTRY1_PORT_RANGE_BOFFSET            16
+#define NAT_ENTRY1_PORT_RANGE_BLEN               8
+#define NAT_ENTRY1_PORT_RANGE_FLAG               HSL_RW
+
+#define PORT_NUM
+#define NAT_ENTRY1_PORT_NUM_BOFFSET              0
+#define NAT_ENTRY1_PORT_NUM_BLEN                 16
+#define NAT_ENTRY1_PORT_NUM_FLAG                 HSL_RW
+
+
+#define NAT_ENTRY2
+#define NAT_ENTRY2_OFFSET                       0x0e88
+#define NAT_ENTRY2_E_LENGTH                     4
+#define NAT_ENTRY2_E_OFFSET                     0x0
+#define NAT_ENTRY2_NR_E                         1
+
+#define HASH_KEY
+#define NAT_ENTRY2_HASH_KEY_BOFFSET             30
+#define NAT_ENTRY2_HASH_KEY_BLEN                2
+#define NAT_ENTRY2_HASH_KEY_FLAG                HSL_RW
+
+#define ACTION
+#define NAT_ENTRY2_ACTION_BOFFSET               28
+#define NAT_ENTRY2_ACTION_BLEN                  2
+#define NAT_ENTRY2_ACTION_FLAG                  HSL_RW
+
+#define CNT_EN
+#define NAT_ENTRY2_CNT_EN_BOFFSET               27
+#define NAT_ENTRY2_CNT_EN_BLEN                  1
+#define NAT_ENTRY2_CNT_EN_FLAG                  HSL_RW
+
+#define CNT_IDX
+#define NAT_ENTRY2_CNT_IDX_BOFFSET              24
+#define NAT_ENTRY2_CNT_IDX_BLEN                 3
+#define NAT_ENTRY2_CNT_IDX_FLAG                 HSL_RW
+
+#define PRV_IPADDR1
+#define NAT_ENTRY2_PRV_IPADDR1_BOFFSET          0
+#define NAT_ENTRY2_PRV_IPADDR1_BLEN             24
+#define NAT_ENTRY2_PRV_IPADDR1_FLAG             HSL_RW
+
+
+#define NAT_ENTRY3
+#define NAT_ENTRY3_OFFSET                       0x0e8c
+#define NAT_ENTRY3_E_LENGTH                     4
+#define NAT_ENTRY3_E_OFFSET                     0x0
+#define NAT_ENTRY3_NR_E                         1
+
+#define ENTRY_VALID
+#define NAT_ENTRY3_ENTRY_VALID_BOFFSET          3
+#define NAT_ENTRY3_ENTRY_VALID_BLEN             1
+#define NAT_ENTRY3_ENTRY_VALID_FLAG             HSL_RW
+
+#define PORT_EN
+#define NAT_ENTRY3_PORT_EN_BOFFSET              2
+#define NAT_ENTRY3_PORT_EN_BLEN                 1
+#define NAT_ENTRY3_PORT_EN_FLAG                 HSL_RW
+
+#define PRO_TYP
+#define NAT_ENTRY3_PRO_TYP_BOFFSET              0
+#define NAT_ENTRY3_PRO_TYP_BLEN                 2
+#define NAT_ENTRY3_PRO_TYP_FLAG                 HSL_RW
+
+
+#define NAPT_ENTRY0
+#define NAPT_ENTRY0_OFFSET                       0x0e80
+#define NAPT_ENTRY0_E_LENGTH                     4
+#define NAPT_ENTRY0_E_OFFSET                     0x0
+#define NAPT_ENTRY0_NR_E                         1
+
+#define DST_IPADDR
+#define NAPT_ENTRY0_DST_IPADDR_BOFFSET           0
+#define NAPT_ENTRY0_DST_IPADDR_BLEN              32
+#define NAPT_ENTRY0_DST_IPADDR_FLAG              HSL_RW
+
+
+#define NAPT_ENTRY1
+#define NAPT_ENTRY1_OFFSET                       0x0e84
+#define NAPT_ENTRY1_E_LENGTH                     4
+#define NAPT_ENTRY1_E_OFFSET                     0x0
+#define NAPT_ENTRY1_NR_E                         1
+
+#define SRC_PORT
+#define NAPT_ENTRY1_SRC_PORT_BOFFSET            16
+#define NAPT_ENTRY1_SRC_PORT_BLEN              16
+#define NAPT_ENTRY1_SRC_PORT_FLAG              HSL_RW
+
+#define DST_PORT
+#define NAPT_ENTRY1_DST_PORT_BOFFSET           0
+#define NAPT_ENTRY1_DST_PORT_BLEN              16
+#define NAPT_ENTRY1_DST_PORT_FLAG              HSL_RW
+
+
+#define NAPT_ENTRY2
+#define NAPT_ENTRY2_OFFSET                       0x0e88
+#define NAPT_ENTRY2_E_LENGTH                     4
+#define NAPT_ENTRY2_E_OFFSET                     0x0
+#define NAPT_ENTRY2_NR_E                         1
+
+#define SRC_IPADDR0
+#define NAPT_ENTRY2_SRC_IPADDR0_BOFFSET           20
+#define NAPT_ENTRY2_SRC_IPADDR0_BLEN              12
+#define NAPT_ENTRY2_SRC_IPADDR0_FLAG              HSL_RW
+
+#define TRANS_IPADDR
+#define NAPT_ENTRY2_TRANS_IPADDR_BOFFSET           16
+#define NAPT_ENTRY2_TRANS_IPADDR_BLEN              4
+#define NAPT_ENTRY2_TRANS_IPADDR_FLAG              HSL_RW
+
+#define TRANS_PORT
+#define NAPT_ENTRY2_TRANS_PORT_BOFFSET           0
+#define NAPT_ENTRY2_TRANS_PORT_BLEN              16
+#define NAPT_ENTRY2_TRANS_PORT_FLAG              HSL_RW
+
+
+#define NAPT_ENTRY3
+#define NAPT_ENTRY3_OFFSET                       0x0e8c
+#define NAPT_ENTRY3_E_LENGTH                     4
+#define NAPT_ENTRY3_E_OFFSET                     0x0
+#define NAPT_ENTRY3_NR_E                         1
+
+#define CNT_EN
+#define NAPT_ENTRY3_CNT_EN_BOFFSET               27
+#define NAPT_ENTRY3_CNT_EN_BLEN                  1
+#define NAPT_ENTRY3_CNT_EN_FLAG                  HSL_RW
+
+#define CNT_IDX
+#define NAPT_ENTRY3_CNT_IDX_BOFFSET              24
+#define NAPT_ENTRY3_CNT_IDX_BLEN                 3
+#define NAPT_ENTRY3_CNT_IDX_FLAG                 HSL_RW
+
+#define PROT_TYP
+#define NAPT_ENTRY3_PROT_TYP_BOFFSET             22
+#define NAPT_ENTRY3_PROT_TYP_BLEN                2
+#define NAPT_ENTRY3_PROT_TYP_FLAG                HSL_RW
+
+#define ACTION
+#define NAPT_ENTRY3_ACTION_BOFFSET               20
+#define NAPT_ENTRY3_ACTION_BLEN                  2
+#define NAPT_ENTRY3_ACTION_FLAG                  HSL_RW
+
+#define SRC_IPADDR1
+#define NAPT_ENTRY3_SRC_IPADDR1_BOFFSET           0
+#define NAPT_ENTRY3_SRC_IPADDR1_BLEN              20
+#define NAPT_ENTRY3_SRC_IPADDR1_FLAG              HSL_RW
+
+
+#define NAPT_ENTRY4
+#define NAPT_ENTRY4_OFFSET                       0x0e90
+#define NAPT_ENTRY4_E_LENGTH                     4
+#define NAPT_ENTRY4_E_OFFSET                     0x0
+#define NAPT_ENTRY4_NR_E                         1
+
+#define AGE_FLAG
+#define NAPT_ENTRY4_AGE_FLAG_BOFFSET             0
+#define NAPT_ENTRY4_AGE_FLAG_BLEN                4
+#define NAPT_ENTRY4_AGE_FLAG_FLAG                HSL_RW
+
+
+#define ROUTER_CTRL
+#define ROUTER_CTRL_OFFSET                       0x0e00
+#define ROUTER_CTRL_E_LENGTH                     4
+#define ROUTER_CTRL_E_OFFSET                     0x0
+#define ROUTER_CTRL_NR_E                         1
+
+#define ARP_LEARN_MODE
+#define ROUTER_CTRL_ARP_LEARN_MODE_BOFFSET       19
+#define ROUTER_CTRL_ARP_LEARN_MODE_BLEN          1
+#define ROUTER_CTRL_ARP_LEARN_MODE_FLAG          HSL_RW
+
+#define GLB_LOCKTIME
+#define ROUTER_CTRL_GLB_LOCKTIME_BOFFSET       16
+#define ROUTER_CTRL_GLB_LOCKTIME_BLEN          2
+#define ROUTER_CTRL_GLB_LOCKTIME_FLAG          HSL_RW
+
+#define ARP_AGE_TIME
+#define ROUTER_CTRL_ARP_AGE_TIME_BOFFSET         8
+#define ROUTER_CTRL_ARP_AGE_TIME_BLEN            8
+#define ROUTER_CTRL_ARP_AGE_TIME_FLAG            HSL_RW
+
+#define WCMP_HAHS_DP
+#define ROUTER_CTRL_WCMP_HAHS_DP_BOFFSET         7
+#define ROUTER_CTRL_WCMP_HAHS_DP_BLEN            1
+#define ROUTER_CTRL_WCMP_HAHS_DP_FLAG            HSL_RW
+
+#define WCMP_HAHS_DIP
+#define ROUTER_CTRL_WCMP_HAHS_DIP_BOFFSET        6
+#define ROUTER_CTRL_WCMP_HAHS_DIP_BLEN           1
+#define ROUTER_CTRL_WCMP_HAHS_DIP_FLAG           HSL_RW
+
+#define WCMP_HAHS_SP
+#define ROUTER_CTRL_WCMP_HAHS_SP_BOFFSET         5
+#define ROUTER_CTRL_WCMP_HAHS_SP_BLEN            1
+#define ROUTER_CTRL_WCMP_HAHS_SP_FLAG            HSL_RW
+
+#define WCMP_HAHS_SIP
+#define ROUTER_CTRL_WCMP_HAHS_SIP_BOFFSET        4
+#define ROUTER_CTRL_WCMP_HAHS_SIP_BLEN           1
+#define ROUTER_CTRL_WCMP_HAHS_SIP_FLAG           HSL_RW
+
+#define ARP_AGE_MODE
+#define ROUTER_CTRL_ARP_AGE_MODE_BOFFSET         1
+#define ROUTER_CTRL_ARP_AGE_MODE_BLEN            1
+#define ROUTER_CTRL_ARP_AGE_MODE_FLAG            HSL_RW
+
+#define ROUTER_EN
+#define ROUTER_CTRL_ROUTER_EN_BOFFSET            0
+#define ROUTER_CTRL_ROUTER_EN_BLEN               1
+#define ROUTER_CTRL_ROUTER_EN_FLAG               HSL_RW
+
+
+
+
+#define ROUTER_PTCTRL0
+#define ROUTER_PTCTRL0_OFFSET                       0x0e04
+#define ROUTER_PTCTRL0_E_LENGTH                     4
+#define ROUTER_PTCTRL0_E_OFFSET                     0x0
+#define ROUTER_PTCTRL0_NR_E                         1
+
+
+
+
+#define ROUTER_PTCTRL1
+#define ROUTER_PTCTRL1_OFFSET                       0x0e08
+#define ROUTER_PTCTRL1_E_LENGTH                     4
+#define ROUTER_PTCTRL1_E_OFFSET                     0x0
+#define ROUTER_PTCTRL1_NR_E                         1
+
+
+
+#define ROUTER_PTCTRL2
+#define ROUTER_PTCTRL2_OFFSET                       0x0e0c
+#define ROUTER_PTCTRL2_E_LENGTH                     4
+#define ROUTER_PTCTRL2_E_OFFSET                     0x0
+#define ROUTER_PTCTRL2_NR_E                         1
+
+#define ARP_PT_UP
+#define ROUTER_PTCTRL2_ARP_PT_UP_BOFFSET               16
+#define ROUTER_PTCTRL2_ARP_PT_UP_BLEN                  7
+#define ROUTER_PTCTRL2_ARP_PT_UP_FLAG                  HSL_RW
+
+#define ARP_LEARN_ACK
+#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET               8
+#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BLEN                  7
+#define ROUTER_PTCTRL2_ARP_LEARN_ACK_FLAG                  HSL_RW
+
+#define ARP_LEARN_REQ
+#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BOFFSET               0
+#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BLEN                  7
+#define ROUTER_PTCTRL2_ARP_LEARN_REQ_FLAG                  HSL_RW
+
+
+
+
+#define NAT_CTRL
+#define NAT_CTRL_OFFSET                       0x0e38
+#define NAT_CTRL_E_LENGTH                     4
+#define NAT_CTRL_E_OFFSET                     0x0
+#define NAT_CTRL_NR_E                         1
+
+#define NAT_HASH_MODE
+#define NAT_CTRL_NAT_HASH_MODE_BOFFSET        5
+#define NAT_CTRL_NAT_HASH_MODE_BLEN           2
+#define NAT_CTRL_NAT_HASH_MODE_FLAG           HSL_RW
+
+#define NAPT_OVERRIDE
+#define NAT_CTRL_NAPT_OVERRIDE_BOFFSET        4
+#define NAT_CTRL_NAPT_OVERRIDE_BLEN           1
+#define NAT_CTRL_NAPT_OVERRIDE_FLAG           HSL_RW
+
+#define NAPT_MODE
+#define NAT_CTRL_NAPT_MODE_BOFFSET            2
+#define NAT_CTRL_NAPT_MODE_BLEN               2
+#define NAT_CTRL_NAPT_MODE_FLAG               HSL_RW
+
+#define NAT_EN
+#define NAT_CTRL_NAT_EN_BOFFSET               1
+#define NAT_CTRL_NAT_EN_BLEN                  1
+#define NAT_CTRL_NAT_EN_FLAG                  HSL_RW
+
+#define NAPT_EN
+#define NAT_CTRL_NAPT_EN_BOFFSET              0
+#define NAT_CTRL_NAPT_EN_BLEN                 1
+#define NAT_CTRL_NAPT_EN_FLAG                 HSL_RW
+
+
+
+
+#define PRV_BASEADDR
+#define PRV_BASEADDR_OFFSET                       0x0e5c
+#define PRV_BASEADDR_E_LENGTH                     4
+#define PRV_BASEADDR_E_OFFSET                     0x0
+#define PRV_BASEADDR_NR_E                         1
+
+#define IP4_ADDR
+#define PRV_BASEADDR_IP4_ADDR_BOFFSET             0
+#define PRV_BASEADDR_IP4_ADDR_BLEN                20
+#define PRV_BASEADDR_IP4_ADDR_FLAG                HSL_RW
+
+
+
+
+#define PRVIP_ADDR
+#define PRVIP_ADDR_OFFSET                         0x0470
+#define PRVIP_ADDR_E_LENGTH                       4
+#define PRVIP_ADDR_E_OFFSET                       0x0
+#define PRVIP_ADDR_NR_E                           1
+
+#define IP4_BASEADDR
+#define PRVIP_ADDR_IP4_BASEADDR_BOFFSET           0
+#define PRVIP_ADDR_IP4_BASEADDR_BLEN              32
+#define PRVIP_ADDR_IP4_BASEADDR_FLAG              HSL_RW
+
+
+#define PRVIP_MASK
+#define PRVIP_MASK_OFFSET                         0x0474
+#define PRVIP_MASK_E_LENGTH                       4
+#define PRVIP_MASK_E_OFFSET                       0x0
+#define PRVIP_MASK_NR_E                           1
+
+#define IP4_BASEMASK
+#define PRVIP_MASK_IP4_BASEMASK_BOFFSET           0
+#define PRVIP_MASK_IP4_BASEMASK_BLEN              32
+#define PRVIP_MASK_IP4_BASEMASK_FLAG              HSL_RW
+
+
+
+
+#define PUB_ADDR0
+#define PUB_ADDR0_OFFSET                       0x5aa00
+#define PUB_ADDR0_E_LENGTH                     4
+#define PUB_ADDR0_E_OFFSET                     0x0
+#define PUB_ADDR0_NR_E                         1
+
+#define IP4_ADDR
+#define PUB_ADDR0_IP4_ADDR_BOFFSET             0
+#define PUB_ADDR0_IP4_ADDR_BLEN                32
+#define PUB_ADDR0_IP4_ADDR_FLAG                HSL_RW
+
+
+#define PUB_ADDR1
+#define PUB_ADDR1_OFFSET                       0x5aa04
+#define PUB_ADDR1_E_LENGTH                     4
+#define PUB_ADDR1_E_OFFSET                     0x0
+#define PUB_ADDR1_NR_E                         1
+
+#define ADDR_VALID
+#define PUB_ADDR1_ADDR_VALID_BOFFSET           0
+#define PUB_ADDR1_ADDR_VALID_BLEN              1
+#define PUB_ADDR1_ADDR_VALID_FLAG              HSL_RW
+
+
+
+
+#define INTF_ADDR_ENTRY0
+#define INTF_ADDR_ENTRY0_OFFSET                     0x5aa00
+#define INTF_ADDR_ENTRY0_E_LENGTH                   4
+#define INTF_ADDR_ENTRY0_E_OFFSET                   0x0
+#define INTF_ADDR_ENTRY0_NR_E                       8
+
+#define MAC_ADDR2
+#define INTF_ADDR_ENTRY0_MAC_ADDR2_BOFFSET          24
+#define INTF_ADDR_ENTRY0_MAC_ADDR2_BLEN             8
+#define INTF_ADDR_ENTRY0_MAC_ADDR2_FLAG             HSL_RW
+
+#define MAC_ADDR3
+#define INTF_ADDR_ENTRY0_MAC_ADDR3_BOFFSET          16
+#define INTF_ADDR_ENTRY0_MAC_ADDR3_BLEN             8
+#define INTF_ADDR_ENTRY0_MAC_ADDR3_FLAG             HSL_RW
+
+#define MAC_ADDR4
+#define INTF_ADDR_ENTRY0_MAC_ADDR4_BOFFSET          8
+#define INTF_ADDR_ENTRY0_MAC_ADDR4_BLEN             8
+#define INTF_ADDR_ENTRY0_MAC_ADDR4_FLAG             HSL_RW
+
+#define MAC_ADDR5
+#define INTF_ADDR_ENTRY0_MAC_ADDR5_BOFFSET          0
+#define INTF_ADDR_ENTRY0_MAC_ADDR5_BLEN             8
+#define INTF_ADDR_ENTRY0_MAC_ADDR5_FLAG             HSL_RW
+
+
+#define INTF_ADDR_ENTRY1
+#define INTF_ADDR_ENTRY1_OFFSET                     0x5aa04
+#define INTF_ADDR_ENTRY1_E_LENGTH                   4
+#define INTF_ADDR_ENTRY1_E_OFFSET                   0x0
+#define INTF_ADDR_ENTRY1_NR_E                       8
+
+#define VID_HIGH0
+#define INTF_ADDR_ENTRY1_VID_HIGH0_BOFFSET          28
+#define INTF_ADDR_ENTRY1_VID_HIGH0_BLEN             4
+#define INTF_ADDR_ENTRY1_VID_HIGH0_FLAG             HSL_RW
+
+#define VID_LOW
+#define INTF_ADDR_ENTRY1_VID_LOW_BOFFSET            16
+#define INTF_ADDR_ENTRY1_VID_LOW_BLEN               12
+#define INTF_ADDR_ENTRY1_VID_LOW_FLAG               HSL_RW
+
+#define MAC_ADDR0
+#define INTF_ADDR_ENTRY1_MAC_ADDR0_BOFFSET          8
+#define INTF_ADDR_ENTRY1_MAC_ADDR0_BLEN             8
+#define INTF_ADDR_ENTRY1_MAC_ADDR0_FLAG             HSL_RW
+
+#define MAC_ADDR1
+#define INTF_ADDR_ENTRY1_MAC_ADDR1_BOFFSET          0
+#define INTF_ADDR_ENTRY1_MAC_ADDR1_BLEN             8
+#define INTF_ADDR_ENTRY1_MAC_ADDR1_FLAG             HSL_RW
+
+
+#define INTF_ADDR_ENTRY2
+#define INTF_ADDR_ENTRY2_OFFSET                     0x5aa08
+#define INTF_ADDR_ENTRY2_E_LENGTH                   4
+#define INTF_ADDR_ENTRY2_E_OFFSET                   0x0
+#define INTF_ADDR_ENTRY2_NR_E                       8
+
+#define IP6_ROUTE
+#define INTF_ADDR_ENTRY2_IP6_ROUTE_BOFFSET          9
+#define INTF_ADDR_ENTRY2_IP6_ROUTE_BLEN             1
+#define INTF_ADDR_ENTRY2_IP6_ROUTE_FLAG             HSL_RW
+
+#define IP4_ROUTE
+#define INTF_ADDR_ENTRY2_IP4_ROUTE_BOFFSET          8
+#define INTF_ADDR_ENTRY2_IP4_ROUTE_BLEN             1
+#define INTF_ADDR_ENTRY2_IP4_ROUTE_FLAG             HSL_RW
+
+#define VID_HIGH1
+#define INTF_ADDR_ENTRY2_VID_HIGH1_BOFFSET          0
+#define INTF_ADDR_ENTRY2_VID_HIGH1_BLEN             8
+#define INTF_ADDR_ENTRY2_VID_HIGH1_FLAG             HSL_RW
+
+
+
+
+    /* Port Shaper Register0 */
+#define EG_SHAPER0
+#define EG_SHAPER0_OFFSET         0x0890
+#define EG_SHAPER0_E_LENGTH       4
+#define EG_SHAPER0_E_OFFSET       0x0020
+#define EG_SHAPER0_NR_E           7
+
+#define EG_Q1_CIR
+#define EG_SHAPER0_EG_Q1_CIR_BOFFSET          16
+#define EG_SHAPER0_EG_Q1_CIR_BLEN             15
+#define EG_SHAPER0_EG_Q1_CIR_FLAG             HSL_RW
+
+#define EG_Q0_CIR
+#define EG_SHAPER0_EG_Q0_CIR_BOFFSET          0
+#define EG_SHAPER0_EG_Q0_CIR_BLEN             15
+#define EG_SHAPER0_EG_Q0_CIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register1 */
+#define EG_SHAPER1
+#define EG_SHAPER1_OFFSET         0x0894
+#define EG_SHAPER1_E_LENGTH       4
+#define EG_SHAPER1_E_OFFSET       0x0020
+#define EG_SHAPER1_NR_E           7
+
+#define EG_Q3_CIR
+#define EG_SHAPER1_EG_Q3_CIR_BOFFSET          16
+#define EG_SHAPER1_EG_Q3_CIR_BLEN             15
+#define EG_SHAPER1_EG_Q3_CIR_FLAG             HSL_RW
+
+#define EG_Q2_CIR
+#define EG_SHAPER1_EG_Q2_CIR_BOFFSET          0
+#define EG_SHAPER1_EG_Q2_CIR_BLEN             15
+#define EG_SHAPER1_EG_Q2_CIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register2 */
+#define EG_SHAPER2
+#define EG_SHAPER2_OFFSET         0x0898
+#define EG_SHAPER2_E_LENGTH       4
+#define EG_SHAPER2_E_OFFSET       0x0020
+#define EG_SHAPER2_NR_E           7
+
+#define EG_Q5_CIR
+#define EG_SHAPER2_EG_Q5_CIR_BOFFSET          16
+#define EG_SHAPER2_EG_Q5_CIR_BLEN             15
+#define EG_SHAPER2_EG_Q5_CIR_FLAG             HSL_RW
+
+#define EG_Q4_CIR
+#define EG_SHAPER2_EG_Q4_CIR_BOFFSET          0
+#define EG_SHAPER2_EG_Q4_CIR_BLEN             15
+#define EG_SHAPER2_EG_Q4_CIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register3 */
+#define EG_SHAPER3
+#define EG_SHAPER3_OFFSET         0x089c
+#define EG_SHAPER3_E_LENGTH       4
+#define EG_SHAPER3_E_OFFSET       0x0020
+#define EG_SHAPER3_NR_E           7
+
+#define EG_Q1_EIR
+#define EG_SHAPER3_EG_Q1_EIR_BOFFSET          16
+#define EG_SHAPER3_EG_Q1_EIR_BLEN             15
+#define EG_SHAPER3_EG_Q1_EIR_FLAG             HSL_RW
+
+#define EG_Q0_EIR
+#define EG_SHAPER3_EG_Q0_EIR_BOFFSET          0
+#define EG_SHAPER3_EG_Q0_EIR_BLEN             15
+#define EG_SHAPER3_EG_Q0_EIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register4 */
+#define EG_SHAPER4
+#define EG_SHAPER4_OFFSET         0x08a0
+#define EG_SHAPER4_E_LENGTH       4
+#define EG_SHAPER4_E_OFFSET       0x0020
+#define EG_SHAPER4_NR_E           7
+
+#define EG_Q3_EIR
+#define EG_SHAPER4_EG_Q3_EIR_BOFFSET          16
+#define EG_SHAPER4_EG_Q3_EIR_BLEN             15
+#define EG_SHAPER4_EG_Q3_EIR_FLAG             HSL_RW
+
+#define EG_Q2_EIR
+#define EG_SHAPER4_EG_Q2_EIR_BOFFSET          0
+#define EG_SHAPER4_EG_Q2_EIR_BLEN             15
+#define EG_SHAPER4_EG_Q2_EIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register5 */
+#define EG_SHAPER5
+#define EG_SHAPER5_OFFSET         0x08a4
+#define EG_SHAPER5_E_LENGTH       4
+#define EG_SHAPER5_E_OFFSET       0x0020
+#define EG_SHAPER5_NR_E           7
+
+#define EG_Q5_EIR
+#define EG_SHAPER5_EG_Q5_EIR_BOFFSET          16
+#define EG_SHAPER5_EG_Q5_EIR_BLEN             15
+#define EG_SHAPER5_EG_Q5_EIR_FLAG             HSL_RW
+
+#define EG_Q4_EIR
+#define EG_SHAPER5_EG_Q4_EIR_BOFFSET          0
+#define EG_SHAPER5_EG_Q4_EIR_BLEN             15
+#define EG_SHAPER5_EG_Q4_EIR_FLAG             HSL_RW
+
+
+    /* Port Shaper Register6 */
+#define EG_SHAPER6
+#define EG_SHAPER6_OFFSET         0x08a8
+#define EG_SHAPER6_E_LENGTH       4
+#define EG_SHAPER6_E_OFFSET       0x0020
+#define EG_SHAPER6_NR_E           7
+
+#define EG_Q3_CBS
+#define EG_SHAPER6_EG_Q3_CBS_BOFFSET          28
+#define EG_SHAPER6_EG_Q3_CBS_BLEN             3
+#define EG_SHAPER6_EG_Q3_CBS_FLAG             HSL_RW
+
+#define EG_Q3_EBS
+#define EG_SHAPER6_EG_Q3_EBS_BOFFSET          24
+#define EG_SHAPER6_EG_Q3_EBS_BLEN             3
+#define EG_SHAPER6_EG_Q3_EBS_FLAG             HSL_RW
+
+#define EG_Q2_CBS
+#define EG_SHAPER6_EG_Q2_CBS_BOFFSET          20
+#define EG_SHAPER6_EG_Q2_CBS_BLEN             3
+#define EG_SHAPER6_EG_Q2_CBS_FLAG             HSL_RW
+
+#define EG_Q2_EBS
+#define EG_SHAPER6_EG_Q2_EBS_BOFFSET          16
+#define EG_SHAPER6_EG_Q2_EBS_BLEN             3
+#define EG_SHAPER6_EG_Q2_EBS_FLAG             HSL_RW
+
+#define EG_Q1_CBS
+#define EG_SHAPER6_EG_Q1_CBS_BOFFSET          12
+#define EG_SHAPER6_EG_Q1_CBS_BLEN             3
+#define EG_SHAPER6_EG_Q1_CBS_FLAG             HSL_RW
+
+#define EG_Q1_EBS
+#define EG_SHAPER6_EG_Q1_EBS_BOFFSET          8
+#define EG_SHAPER6_EG_Q1_EBS_BLEN             3
+#define EG_SHAPER6_EG_Q1_EBS_FLAG             HSL_RW
+
+#define EG_Q0_CBS
+#define EG_SHAPER6_EG_Q0_CBS_BOFFSET          4
+#define EG_SHAPER6_EG_Q0_CBS_BLEN             3
+#define EG_SHAPER6_EG_Q0_CBS_FLAG             HSL_RW
+
+#define EG_Q0_EBS
+#define EG_SHAPER6_EG_Q0_EBS_BOFFSET          0
+#define EG_SHAPER6_EG_Q0_EBS_BLEN             3
+#define EG_SHAPER6_EG_Q0_EBS_FLAG             HSL_RW
+
+
+    /* Port Shaper Register7 */
+#define EG_SHAPER7
+#define EG_SHAPER7_OFFSET         0x08ac
+#define EG_SHAPER7_E_LENGTH       4
+#define EG_SHAPER7_E_OFFSET       0x0020
+#define EG_SHAPER7_NR_E           7
+
+#define EG_Q5_CBS
+#define EG_SHAPER7_EG_Q5_CBS_BOFFSET          28
+#define EG_SHAPER7_EG_Q5_CBS_BLEN             3
+#define EG_SHAPER7_EG_Q5_CBS_FLAG             HSL_RW
+
+#define EG_Q5_EBS
+#define EG_SHAPER7_EG_Q5_EBS_BOFFSET          24
+#define EG_SHAPER7_EG_Q5_EBS_BLEN             3
+#define EG_SHAPER7_EG_Q5_EBS_FLAG             HSL_RW
+
+#define EG_Q4_CBS
+#define EG_SHAPER7_EG_Q4_CBS_BOFFSET          20
+#define EG_SHAPER7_EG_Q4_CBS_BLEN             3
+#define EG_SHAPER7_EG_Q4_CBS_FLAG             HSL_RW
+
+#define EG_Q4_EBS
+#define EG_SHAPER7_EG_Q4_EBS_BOFFSET          16
+#define EG_SHAPER7_EG_Q4_EBS_BLEN             3
+#define EG_SHAPER7_EG_Q4_EBS_FLAG             HSL_RW
+
+#define EG_Q5_UNIT
+#define EG_SHAPER7_EG_Q5_UNIT_BOFFSET          13
+#define EG_SHAPER7_EG_Q5_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q5_UNIT_FLAG             HSL_RW
+
+#define EG_Q4_UNIT
+#define EG_SHAPER7_EG_Q4_UNIT_BOFFSET          12
+#define EG_SHAPER7_EG_Q4_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q4_UNIT_FLAG             HSL_RW
+
+#define EG_Q3_UNIT
+#define EG_SHAPER7_EG_Q3_UNIT_BOFFSET          11
+#define EG_SHAPER7_EG_Q3_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q3_UNIT_FLAG             HSL_RW
+
+#define EG_Q2_UNIT
+#define EG_SHAPER7_EG_Q2_UNIT_BOFFSET          10
+#define EG_SHAPER7_EG_Q2_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q2_UNIT_FLAG             HSL_RW
+
+#define EG_Q1_UNIT
+#define EG_SHAPER7_EG_Q1_UNIT_BOFFSET          9
+#define EG_SHAPER7_EG_Q1_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q1_UNIT_FLAG             HSL_RW
+
+#define EG_Q0_UNIT
+#define EG_SHAPER7_EG_Q0_UNIT_BOFFSET          8
+#define EG_SHAPER7_EG_Q0_UNIT_BLEN             1
+#define EG_SHAPER7_EG_Q0_UNIT_FLAG             HSL_RW
+
+#define EG_PT
+#define EG_SHAPER7_EG_PT_BOFFSET          3
+#define EG_SHAPER7_EG_PT_BLEN             1
+#define EG_SHAPER7_EG_PT_FLAG             HSL_RW
+
+#define EG_TS
+#define EG_SHAPER7_EG_TS_BOFFSET          0
+#define EG_SHAPER7_EG_TS_BLEN             3
+#define EG_SHAPER7_EG_TS_FLAG             HSL_RW
+
+
+
+    /* ACL Policer Register0 */
+#define ACL_POLICER0
+#define ACL_POLICER0_OFFSET         0x0a00
+#define ACL_POLICER0_E_LENGTH       4
+#define ACL_POLICER0_E_OFFSET       0x0008
+#define ACL_POLICER0_NR_E           32
+
+#define ACL_CBS
+#define ACL_POLICER0_ACL_CBS_BOFFSET          15
+#define ACL_POLICER0_ACL_CBS_BLEN             3
+#define ACL_POLICER0_ACL_CBS_FLAG             HSL_RW
+
+#define ACL_CIR
+#define ACL_POLICER0_ACL_CIR_BOFFSET          0
+#define ACL_POLICER0_ACL_CIR_BLEN             15
+#define ACL_POLICER0_ACL_CIR_FLAG             HSL_RW
+
+
+    /* ACL Policer Register1 */
+#define ACL_POLICER1
+#define ACL_POLICER1_OFFSET         0x0a04
+#define ACL_POLICER1_E_LENGTH       4
+#define ACL_POLICER1_E_OFFSET       0x0008
+#define ACL_POLICER1_NR_E           32
+
+#define ACL_BORROW
+#define ACL_POLICER1_ACL_BORROW_BOFFSET          23
+#define ACL_POLICER1_ACL_BORROW_BLEN             1
+#define ACL_POLICER1_ACL_BORROW_FLAG             HSL_RW
+
+#define ACL_UNIT
+#define ACL_POLICER1_ACL_UNIT_BOFFSET          22
+#define ACL_POLICER1_ACL_UNIT_BLEN             1
+#define ACL_POLICER1_ACL_UNIT_FLAG             HSL_RW
+
+#define ACL_CF
+#define ACL_POLICER1_ACL_CF_BOFFSET          21
+#define ACL_POLICER1_ACL_CF_BLEN             1
+#define ACL_POLICER1_ACL_CF_FLAG             HSL_RW
+
+#define ACL_CM
+#define ACL_POLICER1_ACL_CM_BOFFSET          20
+#define ACL_POLICER1_ACL_CM_BLEN             1
+#define ACL_POLICER1_ACL_CM_FLAG             HSL_RW
+
+#define ACL_TS
+#define ACL_POLICER1_ACL_TS_BOFFSET          18
+#define ACL_POLICER1_ACL_TS_BLEN             2
+#define ACL_POLICER1_ACL_TS_FLAG             HSL_RW
+
+#define ACL_EBS
+#define ACL_POLICER1_ACL_EBS_BOFFSET          15
+#define ACL_POLICER1_ACL_EBS_BLEN             3
+#define ACL_POLICER1_ACL_EBS_FLAG             HSL_RW
+
+#define ACL_EIR
+#define ACL_POLICER1_ACL_EIR_BOFFSET          0
+#define ACL_POLICER1_ACL_EIR_BLEN             15
+#define ACL_POLICER1_ACL_EIR_FLAG             HSL_RW
+
+
+    /* ACL Counter Register0 */
+#define ACL_COUNTER0
+#define ACL_COUNTER0_OFFSET         0x1c000
+#define ACL_COUNTER0_E_LENGTH       4
+#define ACL_COUNTER0_E_OFFSET       0x0008
+#define ACL_COUNTER0_NR_E           32
+
+    /* ACL Counter Register1 */
+#define ACL_COUNTER1
+#define ACL_COUNTER1_OFFSET         0x1c004
+#define ACL_COUNTER1_E_LENGTH       4
+#define ACL_COUNTER1_E_OFFSET       0x0008
+#define ACL_COUNTER1_NR_E           32
+
+
+
+
+    /* INGRESS Policer Register0 */
+#define INGRESS_POLICER0
+#define INGRESS_POLICER0_OFFSET         0x0b00
+#define INGRESS_POLICER0_E_LENGTH       4
+#define INGRESS_POLICER0_E_OFFSET       0x0010
+#define INGRESS_POLICER0_NR_E           7
+
+#define ADD_RATE_BYTE
+#define INGRESS_POLICER0_ADD_RATE_BYTE_BOFFSET 24
+#define INGRESS_POLICER0_ADD_RATE_BYTE_BLEN 8
+#define INGRESS_POLICER0_ADD_RATE_BYTE_FLAG HSL_RW
+
+#define C_ING_TS
+#define INGRESS_POLICER0_C_ING_TS_BOFFSET          22
+#define INGRESS_POLICER0_C_ING_TS_BLEN             2
+#define INGRESS_POLICER0_C_ING_TS_FLAG             HSL_RW
+
+#define RATE_MODE
+#define INGRESS_POLICER0_RATE_MODE_BOFFSET          20
+#define INGRESS_POLICER0_RATE_MODE_BLEN             1
+#define INGRESS_POLICER0_RATE_MODE_FLAG             HSL_RW
+
+#define INGRESS_CBS
+#define INGRESS_POLICER0_INGRESS_CBS_BOFFSET          15
+#define INGRESS_POLICER0_INGRESS_CBS_BLEN             3
+#define INGRESS_POLICER0_INGRESS_CBS_FLAG             HSL_RW
+
+#define INGRESS_CIR
+#define INGRESS_POLICER0_INGRESS_CIR_BOFFSET          0
+#define INGRESS_POLICER0_INGRESS_CIR_BLEN             15
+#define INGRESS_POLICER0_INGRESS_CIR_FLAG             HSL_RW
+
+
+    /* INGRESS Policer Register1 */
+#define INGRESS_POLICER1
+#define INGRESS_POLICER1_OFFSET         0x0b04
+#define INGRESS_POLICER1_E_LENGTH       4
+#define INGRESS_POLICER1_E_OFFSET       0x0010
+#define INGRESS_POLICER1_NR_E           7
+
+#define INGRESS_BORROW
+#define INGRESS_POLICER1_INGRESS_BORROW_BOFFSET          23
+#define INGRESS_POLICER1_INGRESS_BORROW_BLEN             1
+#define INGRESS_POLICER1_INGRESS_BORROW_FLAG             HSL_RW
+
+#define INGRESS_UNIT
+#define INGRESS_POLICER1_INGRESS_UNIT_BOFFSET          22
+#define INGRESS_POLICER1_INGRESS_UNIT_BLEN             1
+#define INGRESS_POLICER1_INGRESS_UNIT_FLAG             HSL_RW
+
+#define INGRESS_CF
+#define INGRESS_POLICER1_INGRESS_CF_BOFFSET          21
+#define INGRESS_POLICER1_INGRESS_CF_BLEN             1
+#define INGRESS_POLICER1_INGRESS_CF_FLAG             HSL_RW
+
+#define INGRESS_CM
+#define INGRESS_POLICER1_INGRESS_CM_BOFFSET          20
+#define INGRESS_POLICER1_INGRESS_CM_BLEN             1
+#define INGRESS_POLICER1_INGRESS_CM_FLAG             HSL_RW
+
+#define E_ING_TS
+#define INGRESS_POLICER1_E_ING_TS_BOFFSET          18
+#define INGRESS_POLICER1_E_ING_TS_BLEN             2
+#define INGRESS_POLICER1_E_ING_TS_FLAG             HSL_RW
+
+#define INGRESS_EBS
+#define INGRESS_POLICER1_INGRESS_EBS_BOFFSET          15
+#define INGRESS_POLICER1_INGRESS_EBS_BLEN             3
+#define INGRESS_POLICER1_INGRESS_EBS_FLAG             HSL_RW
+
+#define INGRESS_EIR
+#define INGRESS_POLICER1_INGRESS_EIR_BOFFSET          0
+#define INGRESS_POLICER1_INGRESS_EIR_BLEN             15
+#define INGRESS_POLICER1_INGRESS_EIR_FLAG             HSL_RW
+
+
+    /* INGRESS Policer Register2 */
+#define INGRESS_POLICER2
+#define INGRESS_POLICER2_OFFSET                 0x0b08
+#define INGRESS_POLICER2_E_LENGTH               4
+#define INGRESS_POLICER2_E_OFFSET               0x0010
+#define INGRESS_POLICER2_NR_E                   7
+
+#define C_MUL
+#define INGRESS_POLICER2_C_MUL_BOFFSET          15
+#define INGRESS_POLICER2_C_MUL_BLEN             1
+#define INGRESS_POLICER2_C_UNK_MUL_FLAG         HSL_RW
+
+#define C_UNI
+#define INGRESS_POLICER2_C_UNI_BOFFSET          14
+#define INGRESS_POLICER2_C_UNI_BLEN             1
+#define INGRESS_POLICER2_C_UNI_FLAG             HSL_RW
+
+#define C_UNK_MUL
+#define INGRESS_POLICER2_C_UNK_MUL_BOFFSET      13
+#define INGRESS_POLICER2_C_UNK_MUL_BLEN         1
+#define INGRESS_POLICER2_C_UNK_MUL_FLAG         HSL_RW
+
+#define C_UNK_UNI
+#define INGRESS_POLICER2_C_UNK_UNI_BOFFSET      12
+#define INGRESS_POLICER2_C_UNK_UNI_BLEN         1
+#define INGRESS_POLICER2_C_UNK_UNI_FLAG         HSL_RW
+
+#define C_BROAD
+#define INGRESS_POLICER2_C_BROAD_BOFFSET        11
+#define INGRESS_POLICER2_C_BROAD_BLEN           1
+#define INGRESS_POLICER2_C_BROAD_FLAG           HSL_RW
+
+#define C_MANAGE
+#define INGRESS_POLICER2_C_MANAGC_BOFFSET       10
+#define INGRESS_POLICER2_C_MANAGC_BLEN          1
+#define INGRESS_POLICER2_C_MANAGC_FLAG          HSL_RW
+
+#define C_TCP
+#define INGRESS_POLICER2_C_TCP_BOFFSET          9
+#define INGRESS_POLICER2_C_TCP_BLEN             1
+#define INGRESS_POLICER2_C_TCP_FLAG             HSL_RW
+
+#define C_MIRR
+#define INGRESS_POLICER2_C_MIRR_BOFFSET         8
+#define INGRESS_POLICER2_C_MIRR_BLEN            1
+#define INGRESS_POLICER2_C_MIRR_FLAG            HSL_RW
+
+#define E_MUL
+#define INGRESS_POLICER2_E_MUL_BOFFSET          7
+#define INGRESS_POLICER2_E_MUL_BLEN             1
+#define INGRESS_POLICER2_E_UNK_MUL_FLAG         HSL_RW
+
+#define E_UNI
+#define INGRESS_POLICER2_E_UNI_BOFFSET          6
+#define INGRESS_POLICER2_E_UNI_BLEN             1
+#define INGRESS_POLICER2_E_UNI_FLAG             HSL_RW
+
+#define E_UNK_MUL
+#define INGRESS_POLICER2_E_UNK_MUL_BOFFSET      5
+#define INGRESS_POLICER2_E_UNK_MUL_BLEN         1
+#define INGRESS_POLICER2_E_UNK_MUL_FLAG         HSL_RW
+
+#define E_UNK_UNI
+#define INGRESS_POLICER2_E_UNK_UNI_BOFFSET      4
+#define INGRESS_POLICER2_E_UNK_UNI_BLEN         1
+#define INGRESS_POLICER2_E_UNK_UNI_FLAG         HSL_RW
+
+#define E_BROAD
+#define INGRESS_POLICER2_E_BROAD_BOFFSET        3
+#define INGRESS_POLICER2_E_BROAD_BLEN           1
+#define INGRESS_POLICER2_E_BROAD_FLAG           HSL_RW
+
+#define E_MANAGE
+#define INGRESS_POLICER2_E_MANAGE_BOFFSET       2
+#define INGRESS_POLICER2_E_MANAGE_BLEN          1
+#define INGRESS_POLICER2_E_MANAGE_FLAG          HSL_RW
+
+#define E_TCP
+#define INGRESS_POLICER2_E_TCP_BOFFSET          1
+#define INGRESS_POLICER2_E_TCP_BLEN             1
+#define INGRESS_POLICER2_E_TCP_FLAG             HSL_RW
+
+#define E_MIRR
+#define INGRESS_POLICER2_E_MIRR_BOFFSET         0
+#define INGRESS_POLICER2_E_MIRR_BLEN            1
+#define INGRESS_POLICER2_E_MIRR_FLAG            HSL_RW
+
+
+
+
+    /* Port Rate Limit2 Register */
+#define WRR_CTRL
+#define WRR_CTRL_OFFSET                         0x0830
+#define WRR_CTRL_E_LENGTH                       4
+#define WRR_CTRL_E_OFFSET                       0x0004
+#define WRR_CTRL_NR_E                           7
+
+#define SCH_MODE
+#define WRR_CTRL_SCH_MODE_BOFFSET               30
+#define WRR_CTRL_SCH_MODE_BLEN                  2
+#define WRR_CTRL_SCH_MODE_FLAG                  HSL_RW
+
+#define Q5_W
+#define WRR_CTRL_Q5_W_BOFFSET                   25
+#define WRR_CTRL_Q5_W_BLEN                      5
+#define WRR_CTRL_Q5_W_FLAG                      HSL_RW
+
+#define Q4_W
+#define WRR_CTRL_Q4_W_BOFFSET                   20
+#define WRR_CTRL_Q4_W_BLEN                      5
+#define WRR_CTRL_Q4_W_FLAG                      HSL_RW
+
+#define Q3_W
+#define WRR_CTRL_Q3_W_BOFFSET                   15
+#define WRR_CTRL_Q3_W_BLEN                      5
+#define WRR_CTRL_Q3_W_FLAG                      HSL_RW
+
+#define Q2_W
+#define WRR_CTRL_Q2_W_BOFFSET                   10
+#define WRR_CTRL_Q2_W_BLEN                      5
+#define WRR_CTRL_Q2_W_FLAG                      HSL_RW
+
+#define Q1_W
+#define WRR_CTRL_Q1_W_BOFFSET                   5
+#define WRR_CTRL_Q1_W_BLEN                      5
+#define WRR_CTRL_Q1_W_FLAG                      HSL_RW
+
+#define Q0_W
+#define WRR_CTRL_Q0_W_BOFFSET                   0
+#define WRR_CTRL_Q0_W_BLEN                      5
+#define WRR_CTRL_Q0_W_FLAG                      HSL_RW
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_REG_H_ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_reg_access.h b/qca-ssdk/include/hsl/isisc/isisc_reg_access.h
new file mode 100755
index 0000000..5f6ea31
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_reg_access.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _ISISC_REG_ACCESS_H_
+#define _ISISC_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "sw.h"
+
+    sw_error_t
+    isisc_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+                 a_uint32_t reg, a_uint16_t * value);
+
+    sw_error_t
+    isisc_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+                 a_uint32_t reg, a_uint16_t value);
+
+    sw_error_t
+    isisc_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                 a_uint32_t value_len);
+
+    sw_error_t
+    isisc_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                 a_uint32_t value_len);
+
+    sw_error_t
+    isisc_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                       a_uint32_t bit_offset, a_uint32_t field_len,
+                       a_uint8_t value[], a_uint32_t value_len);
+
+    sw_error_t
+    isisc_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                       a_uint32_t bit_offset, a_uint32_t field_len,
+                       const a_uint8_t value[], a_uint32_t value_len);
+
+    sw_error_t
+    isisc_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump);
+
+    sw_error_t
+    isisc_debug_regsiter_dump(a_uint32_t dev_id, fal_debug_reg_dump_t * reg_dump);
+
+    sw_error_t
+    isisc_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode);
+
+    sw_error_t
+    isisc_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISISC_REG_ACCESS_H_ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_sec.h b/qca-ssdk/include/hsl/isisc/isisc_sec.h
new file mode 100755
index 0000000..93849b4
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_sec.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_SEC_H_
+#define _ISISC_SEC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_sec.h"
+
+    sw_error_t isisc_sec_init(a_uint32_t dev_id);
+
+#ifdef IN_SEC
+#define ISISC_SEC_INIT(rv, dev_id) \
+    { \
+        rv = isisc_sec_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_SEC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isisc_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item,
+                           void *value);
+
+    HSL_LOCAL sw_error_t
+    isisc_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item,
+                           void *value);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_SEC_H_ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_stp.h b/qca-ssdk/include/hsl/isisc/isisc_stp.h
new file mode 100755
index 0000000..cb4b9c6
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_stp.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_STP_H_
+#define _ISISC_STP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_stp.h"
+
+    sw_error_t isisc_stp_init(a_uint32_t dev_id);
+
+#ifdef IN_STP
+#define ISISC_STP_INIT(rv, dev_id) \
+    { \
+        rv = isisc_stp_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_STP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isisc_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                            fal_port_t port_id, fal_stp_state_t state);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                            fal_port_t port_id, fal_stp_state_t * state);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_STP_H_ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_trunk.h b/qca-ssdk/include/hsl/isisc/isisc_trunk.h
new file mode 100755
index 0000000..4346e08
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_trunk.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_TRUNK_H_
+#define _ISISC_TRUNK_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_trunk.h"
+
+    sw_error_t isisc_trunk_init(a_uint32_t dev_id);
+
+#ifdef IN_TRUNK
+#define ISISC_TRUNK_INIT(rv, dev_id) \
+    { \
+        rv = isisc_trunk_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_TRUNK_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    isisc_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+                         a_bool_t enable, fal_pbmp_t member);
+
+    HSL_LOCAL sw_error_t
+    isisc_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+                         a_bool_t * enable, fal_pbmp_t * member);
+
+    HSL_LOCAL sw_error_t
+    isisc_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+    HSL_LOCAL sw_error_t
+    isisc_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+    HSL_LOCAL sw_error_t
+    isisc_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+    HSL_LOCAL sw_error_t
+    isisc_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+    HSL_LOCAL sw_error_t
+    isisc_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header,
+                              a_uint32_t len, fal_pbmp_t dp_member);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _ISISC_TRUNK_H_ */
+
diff --git a/qca-ssdk/include/hsl/isisc/isisc_vlan.h b/qca-ssdk/include/hsl/isisc/isisc_vlan.h
new file mode 100755
index 0000000..c198a72
--- /dev/null
+++ b/qca-ssdk/include/hsl/isisc/isisc_vlan.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ISISC_VLAN_H_
+#define _ISISC_VLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_vlan.h"
+
+    sw_error_t
+    isisc_vlan_init(a_uint32_t dev_id);
+
+#ifdef IN_VLAN
+#define ISISC_VLAN_INIT(rv, dev_id) \
+    { \
+        rv = isisc_vlan_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define ISISC_VLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    isisc_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_vlan_flush(a_uint32_t dev_id);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+                         fal_port_t port_id, fal_pt_1q_egmode_t port_info);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+                                 a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    isisc_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+                                 a_bool_t * enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISISC_VLAN_H_ */
+
diff --git a/qca-ssdk/include/hsl/mp/mp_mib.h b/qca-ssdk/include/hsl/mp/mp_mib.h
new file mode 100755
index 0000000..f79a761
--- /dev/null
+++ b/qca-ssdk/include/hsl/mp/mp_mib.h
@@ -0,0 +1,392 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _MP_MIB_H_
+#define _MP_MIB_H_
+
+#define MMC_CONTROL_MAX_ENTRY	2
+#define TX_OCTET_COUNT_GOOD_BAD_MAX_ENTRY	2
+#define TX_FRAME_COUNT_GOOD_BAD_MAX_ENTRY	2
+#define TX_BROADCAST_FRAMES_GOOD_MAX_ENTRY	2
+#define TX_MULTICAST_FRAMES_GOOD_MAX_ENTRY	2
+#define TX_64OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define TX_UNICAST_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define TX_MULTICAST_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define TX_BROADCAST_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define TX_UNDERFERROR_FRAMES_MAX_ENTRY	2
+#define TX_SINGLE_COLLISION_GOOD_FRAMES_MAX_ENTRY	2
+#define TX_MULTIPLE_COLLISION_GOOD_FRAMES_MAX_ENTRY	2
+#define TX_DEFERRED_FRAMES_MAX_ENTRY	2
+#define TX_LATE_COLLISION_FRAMES_MAX_ENTRY	2
+#define TX_EXCESSIVE_COLLISION_FRAMES_MAX_ENTRY	2
+#define TX_CARRIER_ERROR_FRAMES_MAX_ENTRY	2
+#define TX_OCTET_COUNT_GOOD_MAX_ENTRY	2
+#define TX_FRAME_COUNT_GOOD_MAX_ENTRY	2
+#define TX_PAUSE_FRAMES_MAX_ENTRY	2
+#define TX_VLAN_FRAMES_GOOD_MAX_ENTRY	2
+#define TX_OSIZE_FRAMES_GOOD_MAX_ENTRY 2
+#define RX_FRAME_COUNT_GOOD_BAD_MAX_ENTRY	2
+#define RX_OCTET_COUNT_GOOD_BAD_MAX_ENTRY	2
+#define RX_OCTET_COUNT_GOOD_MAX_ENTRY	2
+#define RX_BROADCAST_FRAMES_GOOD_MAX_ENTRY	2
+#define RX_MULTICAST_FRAMES_GOOD_MAX_ENTRY	2
+#define RX_CRC_ERROR_FRAMES_MAX_ENTRY	2
+#define RX_ALIGNMENT_ERROR_FRAMES_MAX_ENTRY	2
+#define RX_RUNT_ERROR_FRAMES_MAX_ENTRY	2
+#define RX_JABBER_ERROR_FRAMES_MAX_ENTRY	2
+#define RX_UNDERSIZE_FRAMES_GOOD_MAX_ENTRY	2
+#define RX_OVERSIZE_FRAMES_GOOD_MAX_ENTRY	2
+#define RX_64OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define RX_UNICAST_FRAMES_GOOD_MAX_ENTRY	2
+#define RX_LENGTH_ERROR_FRAMES_MAX_ENTRY	2
+#define RX_OUTOFRANGE_FRAMES_MAX_ENTRY	2
+#define RX_PAUSE_FRAMES_MAX_ENTRY	2
+#define RX_FIFO_OVER_FLOW_FRAMES_MAX_ENTRY	2
+#define RX_VLAN_FRAMES_GOOD_BAD_MAX_ENTRY	2
+#define RX_WATCHDOG_ERROR_FRAMES_MAX_ENTRY	2
+#define RX_RECEIVE_ERROR_FRAMES_MAX_ENTRY	2
+#define RX_CONTROL_FRAMES_GOOD_MAX_ENTRY	2
+
+sw_error_t
+mp_mmc_control_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_control_u *value);
+
+sw_error_t
+mp_mmc_control_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_control_u *value);
+
+sw_error_t
+mp_tx_octet_count_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_bad_u *value);
+
+sw_error_t
+mp_tx_frame_count_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_bad_u *value);
+
+sw_error_t
+mp_tx_broadcast_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_u *value);
+
+sw_error_t
+mp_tx_multicast_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_u *value);
+
+sw_error_t
+mp_tx_64octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_64octets_frames_good_bad_u *value);
+
+sw_error_t
+mp_tx_65to127octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_65to127octets_frames_good_bad_u *value);
+
+sw_error_t
+mp_tx_128to255octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_128to255octets_frames_good_bad_u *value);
+
+sw_error_t
+mp_tx_256to511octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_256to511octets_frames_good_bad_u *value);
+
+sw_error_t
+mp_tx_512to1023octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_512to1023octets_frames_good_bad_u *value);
+
+sw_error_t
+mp_tx_1024tomaxoctets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_1024tomaxoctets_frames_good_bad_u *value);
+
+sw_error_t
+mp_tx_unicast_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_unicast_frames_good_bad_u *value);
+
+sw_error_t
+mp_tx_multicast_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_bad_u *value);
+
+sw_error_t
+mp_tx_broadcast_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_bad_u *value);
+
+sw_error_t
+mp_tx_underflow_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_underflow_error_frames_u *value);
+
+sw_error_t
+mp_tx_single_col_good_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_single_collision_good_frames_u *value);
+
+
+sw_error_t
+mp_t_multi_col_good_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multiple_collision_good_frames_u *value);
+
+sw_error_t
+mp_tx_defer_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_deferred_frames_u *value);
+
+sw_error_t
+mp_tx_late_col_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_late_collision_frames_u *value);
+
+sw_error_t
+mp_tx_excessive_col_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_excessive_collision_frames_u *value);
+
+sw_error_t
+mp_tx_carrier_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_carrier_error_frames_u *value);
+
+sw_error_t
+mp_tx_octet_count_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_u *value);
+
+sw_error_t
+mp_tx_frame_count_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_u *value);
+
+sw_error_t
+mp_tx_pause_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_pause_frames_u *value);
+
+sw_error_t
+mp_tx_vlan_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_vlan_frames_good_u *value);
+
+sw_error_t
+mp_tx_osize_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_osize_frames_good_u *value);
+
+sw_error_t
+mp_rx_frame_count_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_frame_count_good_bad_u *value);
+
+sw_error_t
+mp_rx_octet_count_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_bad_u *value);
+
+sw_error_t
+mp_rx_octet_count_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_u *value);
+
+sw_error_t
+mp_rx_broadcast_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_broadcast_frames_good_u *value);
+
+sw_error_t
+mp_rx_multicast_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_multicast_frames_good_u *value);
+
+sw_error_t
+mp_rx_crc_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_crc_error_frames_u *value);
+
+sw_error_t
+mp_rx_alignment_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_crc_error_frames_u *value);
+
+sw_error_t
+mp_rx_runt_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_runt_error_frames_u *value);
+
+sw_error_t
+mp_rx_jabber_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_jabber_error_frames_u *value);
+
+sw_error_t
+mp_rx_undersize_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_undersize_frames_good_u *value);
+
+sw_error_t
+mp_rx_oversize_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_oversize_frames_good_u *value);
+
+sw_error_t
+mp_rx_64octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_64octets_frames_good_bad_u *value);
+
+sw_error_t
+mp_rx_65to127octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_65to127octets_frames_good_bad_u *value);
+
+sw_error_t
+mp_rx_128to255octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_128to255octets_frames_good_bad_u *value);
+
+sw_error_t
+mp_rx_256to511octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_256to511octets_frames_good_bad_u *value);
+
+sw_error_t
+mp_rx_512to1023octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_512to1023octets_frames_good_bad_u *value);
+
+sw_error_t
+mp_rx_1024tomaxoctets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_1024tomaxoctets_frames_good_bad_u *value);
+
+sw_error_t
+mp_rx_unicast_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_unicast_frames_good_u *value);
+
+sw_error_t
+mp_rx_length_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_length_error_frames_u *value);
+
+sw_error_t
+mp_rx_outofrange_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_outofrange_frames_u *value);
+
+sw_error_t
+mp_rx_pause_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_pause_frames_u *value);
+
+sw_error_t
+mp_rx_fifo_over_flow_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_fifo_over_flow_frames_u *value);
+
+sw_error_t
+mp_rx_vlan_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_vlan_frames_good_bad_u *value);
+
+sw_error_t
+mp_rx_watchdog_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_watchdog_error_frames_u *value);
+
+sw_error_t
+mp_rx_receive_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_receive_error_frames_u *value);
+
+sw_error_t
+mp_rx_control_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_control_frames_good_u *value);
+#endif
+
diff --git a/qca-ssdk/include/hsl/mp/mp_mib_reg.h b/qca-ssdk/include/hsl/mp/mp_mib_reg.h
new file mode 100755
index 0000000..45929f1
--- /dev/null
+++ b/qca-ssdk/include/hsl/mp/mp_mib_reg.h
@@ -0,0 +1,875 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef MP_MIB_REG_H
+#define MP_MIB_REG_H
+
+/*[register] MMC_CONTROL*/
+#define MMC_CONTROL
+#define MMC_CONTROL_ADDRESS 0x100
+#define MMC_CONTROL_NUM     2
+#define MMC_CONTROL_INC     0x100000
+#define MMC_CONTROL_DEFAULT 0x0
+
+struct mmc_control {
+	a_uint32_t  cntrst:1;
+	a_uint32_t  cntstopro:1;
+	a_uint32_t  rstonrd:1;
+	a_uint32_t  cntfreez:1;
+	a_uint32_t  cntprst:1;
+	a_uint32_t  cntprstlvl:1;
+	a_uint32_t  _reserved1:2;
+	a_uint32_t  ucdbc:8;
+	a_uint32_t  _reserved2:23;
+};
+
+union mmc_control_u {
+	a_uint32_t val;
+	struct mmc_control bf;
+};
+
+/*[register] TX_OCTET_COUNT_GOOD_BAD*/
+#define TX_OCTET_COUNT_GOOD_BAD
+#define TX_OCTET_COUNT_GOOD_BAD_ADDRESS 0x114
+#define TX_OCTET_COUNT_GOOD_BAD_NUM     2
+#define TX_OCTET_COUNT_GOOD_BAD_INC     0x100000
+#define TX_OCTET_COUNT_GOOD_BAD_DEFAULT 0x0
+
+struct tx_octet_count_good_bad {
+	a_uint32_t  txoctgb:32;
+};
+
+union tx_octet_count_good_bad_u {
+	a_uint32_t val;
+	struct tx_octet_count_good_bad bf;
+};
+
+/*[register] TX_FRAME_COUNT_GOOD_BAD*/
+#define TX_FRAME_COUNT_GOOD_BAD
+#define TX_FRAME_COUNT_GOOD_BAD_ADDRESS 0x118
+#define TX_FRAME_COUNT_GOOD_BAD_NUM     2
+#define TX_FRAME_COUNT_GOOD_BAD_INC     0x100000
+#define TX_FRAME_COUNT_GOOD_BAD_DEFAULT 0x0
+
+struct tx_frame_count_good_bad {
+	a_uint32_t  txfrmgb:32;
+};
+
+union tx_frame_count_good_bad_u {
+	a_uint32_t val;
+	struct tx_frame_count_good_bad bf;
+};
+
+/*[register] TX_BROADCAST_FRAMES_GOOD*/
+#define TX_BROADCAST_FRAMES_GOOD
+#define TX_BROADCAST_FRAMES_GOOD_ADDRESS 0x11c
+#define TX_BROADCAST_FRAMES_GOOD_NUM     2
+#define TX_BROADCAST_FRAMES_GOOD_INC     0x100000
+#define TX_BROADCAST_FRAMES_GOOD_DEFAULT 0x0
+
+struct tx_broadcast_frames_good {
+	a_uint32_t  txbcastg:32;
+};
+
+union tx_broadcast_frames_good_u {
+	a_uint32_t val;
+	struct tx_broadcast_frames_good bf;
+};
+
+/*[register] TX_MULTICAST_FRAMES_GOOD*/
+#define TX_MULTICAST_FRAMES_GOOD
+#define TX_MULTICAST_FRAMES_GOOD_ADDRESS 0x120
+#define TX_MULTICAST_FRAMES_GOOD_NUM     2
+#define TX_MULTICAST_FRAMES_GOOD_INC     0x100000
+#define TX_MULTICAST_FRAMES_GOOD_DEFAULT 0x0
+
+struct tx_multicast_frames_good {
+	a_uint32_t  txmcastg:32;
+};
+
+union tx_multicast_frames_good_u {
+	a_uint32_t val;
+	struct tx_multicast_frames_good bf;
+};
+
+/*[register] TX_64OCTETS_FRAMES_GOOD_BAD*/
+#define TX_64OCTETS_FRAMES_GOOD_BAD
+#define TX_64OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x124
+#define TX_64OCTETS_FRAMES_GOOD_BAD_NUM     2
+#define TX_64OCTETS_FRAMES_GOOD_BAD_INC     0x100000
+#define TX_64OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct tx_64octets_frames_good_bad {
+	a_uint32_t  tx64octgb:32;
+};
+
+union tx_64octets_frames_good_bad_u {
+	a_uint32_t val;
+	struct tx_64octets_frames_good_bad bf;
+};
+
+/*[register] TX_65TO127OCTETS_FRAMES_GOOD_BAD*/
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x128
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_NUM     2
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_INC     0x100000
+#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct tx_65to127octets_frames_good_bad {
+	a_uint32_t  tx65_127octgb:32;
+};
+
+union tx_65to127octets_frames_good_bad_u {
+	a_uint32_t val;
+	struct tx_65to127octets_frames_good_bad bf;
+};
+
+/*[register] TX_128TO255OCTETS_FRAMES_GOOD_BAD*/
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x12c
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_NUM     2
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_INC     0x100000
+#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct tx_128to255octets_frames_good_bad {
+	a_uint32_t  tx128_255octgb:32;
+};
+
+union tx_128to255octets_frames_good_bad_u {
+	a_uint32_t val;
+	struct tx_128to255octets_frames_good_bad bf;
+};
+
+/*[register] TX_256TO511OCTETS_FRAMES_GOOD_BAD*/
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x130
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_NUM     2
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_INC     0x100000
+#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct tx_256to511octets_frames_good_bad {
+	a_uint32_t  tx256_511octgb:32;
+};
+
+union tx_256to511octets_frames_good_bad_u {
+	a_uint32_t val;
+	struct tx_256to511octets_frames_good_bad bf;
+};
+
+/*[register] TX_512TO1023OCTETS_FRAMES_GOOD_BAD*/
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x134
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_NUM     2
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_INC     0x100000
+#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct tx_512to1023octets_frames_good_bad {
+	a_uint32_t  tx512_1023octgb:32;
+};
+
+union tx_512to1023octets_frames_good_bad_u {
+	a_uint32_t val;
+	struct tx_512to1023octets_frames_good_bad bf;
+};
+
+/*[register] TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD*/
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_ADDRESS 0x138
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_NUM     2
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_INC     0x100000
+#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct tx_1024tomaxoctets_frames_good_bad {
+	a_uint32_t  tx1024_maxoctgb:32;
+};
+
+union tx_1024tomaxoctets_frames_good_bad_u {
+	a_uint32_t val;
+	struct tx_1024tomaxoctets_frames_good_bad bf;
+};
+
+/*[register] TX_UNICAST_FRAMES_GOOD_BAD*/
+#define TX_UNICAST_FRAMES_GOOD_BAD
+#define TX_UNICAST_FRAMES_GOOD_BAD_ADDRESS 0x13c
+#define TX_UNICAST_FRAMES_GOOD_BAD_NUM     2
+#define TX_UNICAST_FRAMES_GOOD_BAD_INC     0x100000
+#define TX_UNICAST_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct tx_unicast_frames_good_bad {
+	a_uint32_t  txucastgb:32;
+};
+
+union tx_unicast_frames_good_bad_u {
+	a_uint32_t val;
+	struct tx_unicast_frames_good_bad bf;
+};
+
+/*[register] TX_MULTICAST_FRAMES_GOOD_BAD*/
+#define TX_MULTICAST_FRAMES_GOOD_BAD
+#define TX_MULTICAST_FRAMES_GOOD_BAD_ADDRESS 0x140
+#define TX_MULTICAST_FRAMES_GOOD_BAD_NUM     2
+#define TX_MULTICAST_FRAMES_GOOD_BAD_INC     0x100000
+#define TX_MULTICAST_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct tx_multicast_frames_good_bad {
+	a_uint32_t  txmcastgb:32;
+};
+
+union tx_multicast_frames_good_bad_u {
+	a_uint32_t val;
+	struct tx_multicast_frames_good_bad bf;
+};
+
+/*[register] TX_BROADCAST_FRAMES_GOOD_BAD*/
+#define TX_BROADCAST_FRAMES_GOOD_BAD
+#define TX_BROADCAST_FRAMES_GOOD_BAD_ADDRESS 0x144
+#define TX_BROADCAST_FRAMES_GOOD_BAD_NUM     2
+#define TX_BROADCAST_FRAMES_GOOD_BAD_INC     0x100000
+#define TX_BROADCAST_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct tx_broadcast_frames_good_bad {
+	a_uint32_t  txbcastgb:32;
+};
+
+union tx_broadcast_frames_good_bad_u {
+	a_uint32_t val;
+	struct tx_broadcast_frames_good_bad bf;
+};
+
+/*[register] TX_UNDERFLOW_ERROR_FRAMES*/
+#define TX_UNDERFLOW_ERROR_FRAMES
+#define TX_UNDERFLOW_ERROR_FRAMES_ADDRESS 0x148
+#define TX_UNDERFLOW_ERROR_FRAMES_NUM     2
+#define TX_UNDERFLOW_ERROR_FRAMES_INC     0x100000
+#define TX_UNDERFLOW_ERROR_FRAMES_DEFAULT 0x0
+
+struct tx_underflow_error_frames {
+	a_uint32_t  txundrflw:32;
+};
+
+union tx_underflow_error_frames_u {
+	a_uint32_t val;
+	struct tx_underflow_error_frames bf;
+};
+
+/*[register] TX_SINGLE_COLLISION_GOOD_FRAMES*/
+#define TX_SINGLE_COLLISION_GOOD_FRAMES
+#define TX_SINGLE_COLLISION_GOOD_FRAMES_ADDRESS 0x14c
+#define TX_SINGLE_COLLISION_GOOD_FRAMES_NUM     2
+#define TX_SINGLE_COLLISION_GOOD_FRAMES_INC     0x100000
+#define TX_SINGLE_COLLISION_GOOD_FRAMES_DEFAULT 0x0
+
+struct tx_single_collision_good_frames {
+	a_uint32_t  txsnglcolg:32;
+};
+
+union tx_single_collision_good_frames_u {
+	a_uint32_t val;
+	struct tx_single_collision_good_frames bf;
+};
+
+/*[register] TX_MULTIPLE_COLLISION_GOOD_FRAMES*/
+#define TX_MULTIPLE_COLLISION_GOOD_FRAMES
+#define TX_MULTIPLE_COLLISION_GOOD_FRAMES_ADDRESS 0x150
+#define TX_MULTIPLE_COLLISION_GOOD_FRAMES_NUM     2
+#define TX_MULTIPLE_COLLISION_GOOD_FRAMES_INC     0x100000
+#define TX_MULTIPLE_COLLISION_GOOD_FRAMES_DEFAULT 0x0
+
+struct tx_multiple_collision_good_frames {
+	a_uint32_t  txmultcolg:32;
+};
+
+union tx_multiple_collision_good_frames_u {
+	a_uint32_t val;
+	struct tx_multiple_collision_good_frames bf;
+};
+
+/*[register] TX_DEFERRED_FRAMES*/
+#define TX_DEFERRED_FRAMES
+#define TX_DEFERRED_FRAMES_ADDRESS 0x154
+#define TX_DEFERRED_FRAMES_NUM     2
+#define TX_DEFERRED_FRAMES_INC     0x100000
+#define TX_DEFERRED_FRAMES_DEFAULT 0x0
+
+struct tx_deferred_frames {
+	a_uint32_t  txdefrd:32;
+};
+
+union tx_deferred_frames_u {
+	a_uint32_t val;
+	struct tx_deferred_frames bf;
+};
+
+/*[register] TX_LATE_COLLISION_FRAMES*/
+#define TX_LATE_COLLISION_FRAMES
+#define TX_LATE_COLLISION_FRAMES_ADDRESS 0x158
+#define TX_LATE_COLLISION_FRAMES_NUM     2
+#define TX_LATE_COLLISION_FRAMES_INC     0x100000
+#define TX_LATE_COLLISION_FRAMES_DEFAULT 0x0
+
+struct tx_late_collision_frames {
+	a_uint32_t  txlatecol:32;
+};
+
+union tx_late_collision_frames_u {
+	a_uint32_t val;
+	struct tx_late_collision_frames bf;
+};
+
+/*[register] TX_EXCESSIVE_COLLISION_FRAMES*/
+#define TX_EXCESSIVE_COLLISION_FRAMES
+#define TX_EXCESSIVE_COLLISION_FRAMES_ADDRESS 0x15c
+#define TX_EXCESSIVE_COLLISION_FRAMES_NUM     2
+#define TX_EXCESSIVE_COLLISION_FRAMES_INC     0x100000
+#define TX_EXCESSIVE_COLLISION_FRAMES_DEFAULT 0x0
+
+struct tx_excessive_collision_frames {
+	a_uint32_t  txexscol:32;
+};
+
+union tx_excessive_collision_frames_u {
+	a_uint32_t val;
+	struct tx_excessive_collision_frames bf;
+};
+
+/*[register] TX_CARRIER_ERROR_FRAMES*/
+#define TX_CARRIER_ERROR_FRAMES
+#define TX_CARRIER_ERROR_FRAMES_ADDRESS 0x160
+#define TX_CARRIER_ERROR_FRAMES_NUM     2
+#define TX_CARRIER_ERROR_FRAMES_INC     0x100000
+#define TX_CARRIER_ERROR_FRAMES_DEFAULT 0x0
+
+struct tx_carrier_error_frames {
+	a_uint32_t  txexscol:32;
+};
+
+union tx_carrier_error_frames_u {
+	a_uint32_t val;
+	struct tx_carrier_error_frames bf;
+};
+
+/*[register] TX_OCTET_COUNT_GOOD*/
+#define TX_OCTET_COUNT_GOOD
+#define TX_OCTET_COUNT_GOOD_ADDRESS 0x164
+#define TX_OCTET_COUNT_GOOD_NUM     2
+#define TX_OCTET_COUNT_GOOD_INC     0x100000
+#define TX_OCTET_COUNT_GOOD_DEFAULT 0x0
+
+struct tx_octet_count_good {
+	a_uint32_t  txoctg:32;
+};
+
+union tx_octet_count_good_u {
+	a_uint32_t val;
+	struct tx_octet_count_good bf;
+};
+
+/*[register] TX_FRAME_COUNT_GOOD*/
+#define TX_FRAME_COUNT_GOOD
+#define TX_FRAME_COUNT_GOOD_ADDRESS 0x168
+#define TX_FRAME_COUNT_GOOD_NUM     2
+#define TX_FRAME_COUNT_GOOD_INC     0x100000
+#define TX_FRAME_COUNT_GOOD_DEFAULT 0x0
+
+struct tx_frame_count_good {
+	a_uint32_t  txfrmg:32;
+};
+
+union tx_frame_count_good_u {
+	a_uint32_t val;
+	struct tx_frame_count_good bf;
+};
+
+/*[register] TX_EXCESSIVE_DEFERRAL_ERROR*/
+#define TX_EXCESSIVE_DEFERRAL_ERROR
+#define TX_EXCESSIVE_DEFERRAL_ERROR_ADDRESS 0x16c
+#define TX_EXCESSIVE_DEFERRAL_ERROR_NUM     2
+#define TX_EXCESSIVE_DEFERRAL_ERROR_INC     0x100000
+#define TX_EXCESSIVE_DEFERRAL_ERRORD_DEFAULT 0x0
+
+struct tx_excessive_deferral_error {
+	a_uint32_t  txexsdef:32;
+};
+
+union tx_excessive_deferral_error_u {
+	a_uint32_t val;
+	struct tx_excessive_deferral_error bf;
+};
+
+/*[register] TX_PAUSE_FRAMES*/
+#define TX_PAUSE_FRAMES
+#define TX_PAUSE_FRAMES_ADDRESS 0x170
+#define TX_PAUSE_FRAMES_NUM     2
+#define TX_PAUSE_FRAMES_INC     0x100000
+#define TX_PAUSE_FRAMES_DEFAULT 0x0
+
+struct tx_pause_frames {
+	a_uint32_t  txpauseg:32;
+};
+
+union tx_pause_frames_u {
+	a_uint32_t val;
+	struct tx_pause_frames bf;
+};
+
+/*[register] TX_VLAN_FRAMES_GOOD*/
+#define TX_VLAN_FRAMES_GOOD
+#define TX_VLAN_FRAMES_GOOD_ADDRESS 0x174
+#define TX_VLAN_FRAMES_GOOD_NUM     2
+#define TX_VLAN_FRAMES_GOOD_INC     0x100000
+#define TX_VLAN_FRAMES_GOOD_DEFAULT 0x0
+
+struct tx_vlan_frames_good {
+	a_uint32_t  txvlang:32;
+};
+
+union tx_vlan_frames_good_u {
+	a_uint32_t val;
+	struct tx_vlan_frames_good bf;
+};
+
+/*[register] TX_OSIZE_FRAMES_GOOD*/
+#define TX_OSIZE_FRAMES_GOOD
+#define TX_OSIZE_FRAMES_GOOD_ADDRESS 0x178
+#define TX_OSIZE_FRAMES_GOOD_NUM     2
+#define TX_OSIZE_FRAMES_GOOD_INC     0x100000
+#define TX_OSIZE_FRAMES_GOOD_DEFAULT 0x0
+
+struct tx_osize_frames_good {
+	a_uint32_t  txosize:32;
+};
+
+union tx_osize_frames_good_u {
+	a_uint32_t val;
+	struct tx_osize_frames_good bf;
+};
+
+/*[register] RX_FRAME_COUNT_GOOD_BAD*/
+#define RX_FRAME_COUNT_GOOD_BAD
+#define RX_FRAME_COUNT_GOOD_BAD_ADDRESS 0x180
+#define RX_FRAME_COUNT_GOOD_BAD_NUM     2
+#define RX_FRAME_COUNT_GOOD_BAD_INC     0x100000
+#define RX_FRAME_COUNT_GOOD_BAD_DEFAULT 0x0
+
+struct rx_frame_count_good_bad {
+	a_uint32_t  rxfrmgb:32;
+};
+
+union rx_frame_count_good_bad_u {
+	a_uint32_t val;
+	struct rx_frame_count_good_bad bf;
+};
+
+/*[register] RX_OCTET_COUNT_GOOD_BAD*/
+#define RX_OCTET_COUNT_GOOD_BAD
+#define RX_OCTET_COUNT_GOOD_BAD_ADDRESS 0x184
+#define RX_OCTET_COUNT_GOOD_BAD_NUM     2
+#define RX_OCTET_COUNT_GOOD_BAD_INC     0x100000
+#define RX_OCTET_COUNT_GOOD_BAD_DEFAULT 0x0
+
+struct rx_octet_count_good_bad {
+	a_uint32_t  rxoctgb:32;
+};
+
+union rx_octet_count_good_bad_u {
+	a_uint32_t val;
+	struct rx_octet_count_good_bad bf;
+};
+
+/*[register] RX_OCTET_COUNT_GOOD*/
+#define RX_OCTET_COUNT_GOOD
+#define RX_OCTET_COUNT_GOOD_ADDRESS 0x188
+#define RX_OCTET_COUNT_GOOD_NUM     2
+#define RX_OCTET_COUNT_GOOD_INC     0x100000
+#define RX_OCTET_COUNT_GOOD_DEFAULT 0x0
+
+struct rx_octet_count_good {
+	a_uint32_t  rxoctg:32;
+};
+
+union rx_octet_count_good_u {
+	a_uint32_t val;
+	struct rx_octet_count_good bf;
+};
+
+/*[register] RX_BROADCAST_FRAMES_GOOD*/
+#define RX_BROADCAST_FRAMES_GOOD
+#define RX_BROADCAST_FRAMES_GOOD_ADDRESS 0x18c
+#define RX_BROADCAST_FRAMES_GOOD_NUM     2
+#define RX_BROADCAST_FRAMES_GOOD_INC     0x100000
+#define RX_BROADCAST_FRAMES_GOOD_DEFAULT 0x0
+
+struct rx_broadcast_frames_good {
+	a_uint32_t  rxbcastg:32;
+};
+
+union rx_broadcast_frames_good_u {
+	a_uint32_t val;
+	struct rx_broadcast_frames_good bf;
+};
+
+/*[register] RX_MULTICAST_FRAMES_GOOD*/
+#define RX_MULTICAST_FRAMES_GOOD
+#define RX_MULTICAST_FRAMES_GOOD_ADDRESS 0x190
+#define RX_MULTICAST_FRAMES_GOOD_NUM     2
+#define RX_MULTICAST_FRAMES_GOOD_INC     0x100000
+#define RX_MULTICAST_FRAMES_GOOD_DEFAULT 0x0
+
+struct rx_multicast_frames_good {
+	a_uint32_t  rxmcastg:32;
+};
+
+union rx_multicast_frames_good_u {
+	a_uint32_t val;
+	struct rx_multicast_frames_good bf;
+};
+
+/*[register] RX_CRC_ERROR_FRAMES*/
+#define RX_CRC_ERROR_FRAMES
+#define RX_CRC_ERROR_FRAMES_ADDRESS 0x194
+#define RX_CRC_ERROR_FRAMES_NUM     2
+#define RX_CRC_ERROR_FRAMES_INC     0x100000
+#define RX_CRC_ERROR_FRAMES_DEFAULT 0x0
+
+struct rx_crc_error_frames {
+	a_uint32_t  rxcrcer:32;
+};
+
+union rx_crc_error_frames_u {
+	a_uint32_t val;
+	struct rx_crc_error_frames bf;
+};
+
+/*[register] RX_ALIGNMENT_ERROR_FRAMES*/
+#define RX_ALIGNMENT_ERROR_FRAMES
+#define RX_ALIGNMENT_ERROR_FRAMES_ADDRESS 0x198
+#define RX_ALIGNMENT_ERROR_FRAMES_NUM     2
+#define RX_ALIGNMENT_ERROR_FRAMES_INC     0x100000
+#define RX_ALIGNMENT_ERROR_FRAMES_DEFAULT 0x0
+
+struct rx_alignment_error_frames {
+	a_uint32_t  rxalgnerr:32;
+};
+
+union rx_alignment_error_frames_u {
+	a_uint32_t val;
+	struct rx_alignment_error_frames bf;
+};
+
+/*[register] RX_RUNT_ERROR_FRAMES*/
+#define RX_RUNT_ERROR_FRAMES
+#define RX_RUNT_ERROR_FRAMES_ADDRESS 0x19c
+#define RX_RUNT_ERROR_FRAMES_NUM     2
+#define RX_RUNT_ERROR_FRAMES_INC     0x100000
+#define RX_RUNT_ERROR_FRAMES_DEFAULT 0x0
+
+struct rx_runt_error_frames {
+	a_uint32_t  rxrunter:32;
+};
+
+union rx_runt_error_frames_u {
+	a_uint32_t val;
+	struct rx_runt_error_frames bf;
+};
+
+/*[register] RX_JABBER_ERROR_FRAMES*/
+#define RX_JABBER_ERROR_FRAMES
+#define RX_JABBER_ERROR_FRAMES_ADDRESS 0x1a0
+#define RX_JABBER_ERROR_FRAMES_NUM     2
+#define RX_JABBER_ERROR_FRAMES_INC     0x100000
+#define RX_JABBER_ERROR_FRAMES_DEFAULT 0x0
+
+struct rx_jabber_error_frames {
+	a_uint32_t  rxjaberer:32;
+};
+
+union rx_jabber_error_frames_u {
+	a_uint32_t val;
+	struct rx_jabber_error_frames bf;
+};
+
+/*[register] RX_UNDERSIZE_FRAMES_GOOD*/
+#define RX_UNDERSIZE_FRAMES_GOOD
+#define RX_UNDERSIZE_FRAMES_GOOD_ADDRESS 0x1a4
+#define RX_UNDERSIZE_FRAMES_GOOD_NUM     2
+#define RX_UNDERSIZE_FRAMES_GOOD_INC     0x100000
+#define RX_UNDERSIZE_FRAMES_GOOD_DEFAULT 0x0
+
+struct rx_undersize_frames_good {
+	a_uint32_t  rxusizeg:32;
+};
+
+union rx_undersize_frames_good_u {
+	a_uint32_t val;
+	struct rx_undersize_frames_good bf;
+};
+
+/*[register] RX_OVERSIZE_FRAMES_GOOD*/
+#define RX_OVERSIZE_FRAMES_GOOD
+#define RX_OVERSIZE_FRAMES_GOOD_ADDRESS 0x1a8
+#define RX_OVERSIZE_FRAMES_GOOD_NUM     2
+#define RX_OVERSIZE_FRAMES_GOOD_INC     0x100000
+#define RX_OVERSIZE_FRAMES_GOOD_DEFAULT 0x0
+
+struct rx_oversize_frames_good {
+	a_uint32_t  rxosizeg:32;
+};
+
+union rx_oversize_frames_good_u {
+	a_uint32_t val;
+	struct rx_oversize_frames_good bf;
+};
+
+/*[register] RX_64OCTETS_FRAMES_GOOD_BAD*/
+#define RX_64OCTETS_FRAMES_GOOD_BAD
+#define RX_64OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x1ac
+#define RX_64OCTETS_FRAMES_GOOD_BAD_NUM     2
+#define RX_64OCTETS_FRAMES_GOOD_BAD_INC     0x100000
+#define RX_64OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct rx_64octets_frames_good_bad {
+	a_uint32_t  rx64octgb:32;
+};
+
+union rx_64octets_frames_good_bad_u {
+	a_uint32_t val;
+	struct rx_64octets_frames_good_bad bf;
+};
+
+/*[register] RX_65TO127OCTETS_FRAMES_GOOD_BAD*/
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x1b0
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_NUM     2
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_INC     0x100000
+#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct rx_65to127octets_frames_good_bad {
+	a_uint32_t  rx65_127octgb:32;
+};
+
+union rx_65to127octets_frames_good_bad_u {
+	a_uint32_t val;
+	struct rx_65to127octets_frames_good_bad bf;
+};
+
+/*[register] RX_128TO255OCTETS_FRAMES_GOOD_BAD*/
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x1b4
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_NUM     2
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_INC     0x100000
+#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct rx_128to255octets_frames_good_bad {
+	a_uint32_t  rx128_255octgb:32;
+};
+
+union rx_128to255octets_frames_good_bad_u {
+	a_uint32_t val;
+	struct rx_128to255octets_frames_good_bad bf;
+};
+
+/*[register] RX_256TO511OCTETS_FRAMES_GOOD_BAD*/
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x1b8
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_NUM     2
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_INC     0x100000
+#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct rx_256to511octets_frames_good_bad {
+	a_uint32_t  rx256_511octgb:32;
+};
+
+union rx_256to511octets_frames_good_bad_u {
+	a_uint32_t val;
+	struct rx_256to511octets_frames_good_bad bf;
+};
+
+/*[register] RX_512TO1023OCTETS_FRAMES_GOOD_BAD*/
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x1bc
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_NUM     2
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_INC     0x100000
+#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct rx_512to1023octets_frames_good_bad {
+	a_uint32_t  rx512_1023octgb:32;
+};
+
+union rx_512to1023octets_frames_good_bad_u {
+	a_uint32_t val;
+	struct rx_512to1023octets_frames_good_bad bf;
+};
+
+/*[register] RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD*/
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_ADDRESS 0x1c0
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_NUM     2
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_INC     0x100000
+#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct rx_1024tomaxoctets_frames_good_bad {
+	a_uint32_t  rx1024_maxgboct:32;
+};
+
+union rx_1024tomaxoctets_frames_good_bad_u {
+	a_uint32_t val;
+	struct rx_1024tomaxoctets_frames_good_bad bf;
+};
+
+/*[register] RX_UNICAST_FRAMES_GOOD*/
+#define RX_UNICAST_FRAMES_GOOD
+#define RX_UNICAST_FRAMES_GOOD_ADDRESS 0x1c4
+#define RX_UNICAST_FRAMES_GOOD_NUM     2
+#define RX_UNICAST_FRAMES_GOOD_INC     0x100000
+#define RX_UNICAST_FRAMES_GOOD_DEFAULT 0x0
+
+struct rx_unicast_frames_good {
+	a_uint32_t  rxucastg:32;
+};
+
+union rx_unicast_frames_good_u {
+	a_uint32_t val;
+	struct rx_unicast_frames_good bf;
+};
+
+/*[register] RX_LENGTH_ERROR_FRAMES*/
+#define RX_LENGTH_ERROR_FRAMES
+#define RX_LENGTH_ERROR_FRAMES_ADDRESS 0x1c8
+#define RX_LENGTH_ERROR_FRAMES_NUM     2
+#define RX_LENGTH_ERROR_FRAMES_INC     0x100000
+#define RX_LENGTH_ERROR_FRAMES_DEFAULT 0x0
+
+struct rx_length_error_frames {
+	a_uint32_t  rxlenerr:32;
+};
+
+union rx_length_error_frames_u {
+	a_uint32_t val;
+	struct rx_length_error_frames bf;
+};
+
+/*[register] RX_OUTOFRANGE_FRAMES*/
+#define RX_OUTOFRANGE_FRAMES
+#define RX_OUTOFRANGE_FRAMES_ADDRESS 0x1cc
+#define RX_OUTOFRANGE_FRAMES_NUM     2
+#define RX_OUTOFRANGE_FRAMES_INC     0x100000
+#define RX_OUTOFRANGE_FRAMES_DEFAULT 0x0
+
+struct rx_outofrange_frames {
+	a_uint32_t  rxorange:32;
+};
+
+union rx_outofrange_frames_u {
+	a_uint32_t val;
+	struct rx_outofrange_frames bf;
+};
+
+/*[register] RX_PAUSE_FRAMES*/
+#define RX_PAUSE_FRAMES
+#define RX_PAUSE_FRAMES_ADDRESS 0x1d0
+#define RX_PAUSE_FRAMES_NUM     2
+#define RX_PAUSE_FRAMES_INC     0x100000
+#define RX_PAUSE_FRAMES_DEFAULT 0x0
+
+struct rx_pause_frames {
+	a_uint32_t  rxpause:32;
+};
+
+union rx_pause_frames_u {
+	a_uint32_t val;
+	struct rx_pause_frames bf;
+};
+
+/*[register] RX_FIFOOVERFW_FRAMES*/
+#define RX_FIFOOVERFW_FRAMES
+#define RX_FIFOOVERFW_FRAMES_ADDRESS 0x1d4
+#define RX_FIFOOVERFW_FRAMES_NUM     2
+#define RX_FIFOOVERFW_FRAMES_INC     0x100000
+#define RX_FIFOOVERFW_FRAMES_DEFAULT 0x0
+
+struct rx_fifo_over_flow_frames {
+	a_uint32_t  rxfovf:32;
+};
+
+union rx_fifo_over_flow_frames_u {
+	a_uint32_t val;
+	struct rx_fifo_over_flow_frames bf;
+};
+
+/*[register] RX_VLAN_FRAMES_GOOD_BAD*/
+#define RX_VLAN_FRAMES_GOOD_BAD
+#define RX_VLAN_FRAMES_GOOD_BAD_ADDRESS 0x1d8
+#define RX_VLAN_FRAMES_GOOD_BAD_NUM     2
+#define RX_VLAN_FRAMES_GOOD_BAD_INC     0x100000
+#define RX_VLAN_FRAMES_GOOD_BAD_DEFAULT 0x0
+
+struct rx_vlan_frames_good_bad {
+	a_uint32_t  rxvlangb:32;
+};
+
+union rx_vlan_frames_good_bad_u {
+	a_uint32_t val;
+	struct rx_vlan_frames_good_bad bf;
+};
+
+/*[register] RX_WATCHDOG_ERROR_FRAMES*/
+#define RX_WATCHDOG_ERROR_FRAMES
+#define RX_WATCHDOG_ERROR_FRAMES_ADDRESS 0x1dc
+#define RX_WATCHDOG_ERROR_FRAMES_NUM     2
+#define RX_WATCHDOG_ERROR_FRAMES_INC     0x100000
+#define RX_WATCHDOG_ERROR_FRAMES_DEFAULT 0x0
+
+struct rx_watchdog_error_frames {
+	a_uint32_t  rxwdogerr:32;
+};
+
+union rx_watchdog_error_frames_u {
+	a_uint32_t val;
+	struct rx_watchdog_error_frames bf;
+};
+
+/*[register] GMAC0_RX_RECEIVE_ERROR_FRAMES*/
+#define RX_RECEIVE_ERROR_FRAMES
+#define RX_RECEIVE_ERROR_FRAMES_ADDRESS 0x1e0
+#define RX_RECEIVE_ERROR_FRAMES_NUM     2
+#define RX_RECEIVE_ERROR_FRAMES_INC     0x100000
+#define RX_RECEIVE_ERROR_FRAMES_DEFAULT 0x0
+
+struct rx_receive_error_frames {
+	a_uint32_t  rxrcverr:32;
+};
+
+union rx_receive_error_frames_u {
+	a_uint32_t val;
+	struct rx_receive_error_frames bf;
+};
+
+/*[register] RX_CONTROL_FRAMES_GOOD*/
+#define RX_CONTROL_FRAMES_GOOD
+#define RX_CONTROL_FRAMES_GOOD_ADDRESS 0x1e4
+#define RX_CONTROL_FRAMES_GOOD_NUM     2
+#define RX_CONTROL_FRAMES_GOOD_INC     0x100000
+#define RX_CONTROL_FRAMES_GOOD_DEFAULT 0x0
+
+struct rx_control_frames_good {
+	a_uint32_t  rxctlg:32;
+};
+
+union rx_control_frames_good_u {
+	a_uint32_t val;
+	struct rx_control_frames_good bf;
+};
+#endif
diff --git a/qca-ssdk/include/hsl/mp/mp_portctrl.h b/qca-ssdk/include/hsl/mp/mp_portctrl.h
new file mode 100755
index 0000000..32c95ca
--- /dev/null
+++ b/qca-ssdk/include/hsl/mp/mp_portctrl.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef MAPLE_PORTCTRL_H
+#define MAPLE_PORTCTRL_H
+
+#define MAC_CONFIGURATION_MAX_ENTRY          2
+#define MAC_FRAME_FILTER_MAX_ENTRY           2
+#define MAC_FLOW_CTRL_MAX_ENTRY              2
+#define MAC_LPI_CTRL_STATUS_MAX_ENTRY        2
+#define MAC_LPI_TIMER_CTRL_MAX_ENTRY         2
+#define MAC_MAX_FRAME_CTRL_MAX_ENTRY         2
+#define MAC_OPERATION_MODE_CTRL_MAX_ENTRY    2
+
+sw_error_t
+mp_mac_configuration_get(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_configuration_u *value);
+
+sw_error_t
+mp_mac_configuration_set(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_configuration_u *value);
+
+
+sw_error_t
+mp_mac_frame_filter_get(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_frame_filter_u *value);
+
+sw_error_t
+mp_mac_frame_filter_set(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_frame_filter_u *value);
+
+sw_error_t
+mp_mac_flowctrl_get(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_flow_ctrl_u *value);
+
+sw_error_t
+mp_mac_flowctrl_set(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_flow_ctrl_u *value);
+
+sw_error_t
+mp_mac_lpi_ctrl_status_get(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_lpi_ctrl_status_u *value);
+
+sw_error_t
+mp_mac_lpi_ctrl_status_set(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_lpi_ctrl_status_u *value);
+
+sw_error_t
+mp_mac_lpi_timer_ctrl_get(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_lpi_timer_ctrl_u *value);
+
+sw_error_t
+mp_mac_lpi_timer_ctrl_set(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_lpi_timer_ctrl_u *value);
+
+sw_error_t
+mp_mac_max_frame_ctrl_get(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_max_frame_ctrl_u *value);
+
+sw_error_t
+mp_mac_max_frame_ctrl_set(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_max_frame_ctrl_u *value);
+
+sw_error_t
+mp_mac_operation_mode_ctrl_get(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_operation_mode_ctrl_u *value);
+
+sw_error_t
+mp_mac_operation_mode_ctrl_set(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_operation_mode_ctrl_u *value);
+#endif
+
diff --git a/qca-ssdk/include/hsl/mp/mp_portctrl_reg.h b/qca-ssdk/include/hsl/mp/mp_portctrl_reg.h
new file mode 100755
index 0000000..9ead6b6
--- /dev/null
+++ b/qca-ssdk/include/hsl/mp/mp_portctrl_reg.h
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef MAPLE_PORTCTRL_REG_H
+#define MAPLE_PORTCTRL_REG_H
+
+/*[register] MAC_CONFIGURATION*/
+#define MAC_CONFIGURATION
+#define MAC_CONFIGURATION_ADDRESS 0x0
+#define MAC_CONFIGURATION_NUM     2
+#define MAC_CONFIGURATION_INC     0x100000
+#define MAC_CONFIGURATION_DEFAULT 0x0
+
+struct mac_configuration {
+	a_uint32_t  preamble_length:2;
+	a_uint32_t  rx_enable:1;
+	a_uint32_t  tx_enable:1;
+	a_uint32_t  deferral_check:1;
+	a_uint32_t  back_off_limit:2;
+	a_uint32_t  acs:1;
+	a_uint32_t  link_status:1;
+	a_uint32_t  disable_retry:1;
+	a_uint32_t  checksum_offload:1;
+	a_uint32_t  duplex:1;
+	a_uint32_t  loopback:1;
+	a_uint32_t  disable_receive_own:1;
+	a_uint32_t  mii_speed:1;
+	a_uint32_t  port_select:1;
+	a_uint32_t  disable_carrier_sense:1;
+	a_uint32_t  ipg:3;
+	a_uint32_t  jumbo_frame_enable:1;
+	a_uint32_t  frame_burst_enable:1;
+	a_uint32_t  jabber_disable:1;
+	a_uint32_t  watchdog_disable:1;
+	a_uint32_t  tc:1;
+	a_uint32_t  crc_strpping:1;
+	a_uint32_t  sfterr:1;
+	a_uint32_t  twokpe:1;
+	a_uint32_t  sarc:3;
+	a_uint32_t  reserved:1;
+
+};
+
+union mac_configuration_u {
+	a_uint32_t val;
+	struct mac_configuration bf;
+};
+
+/*[register] MAC_FRAME_FILTER*/
+#define MAC_FRAME_FILTER
+#define MAC_FRAME_FILTER_ADDRESS 0x4
+#define MAC_FRAME_FILTER_NUM     2
+#define MAC_FRAME_FILTER_INC     0x100000
+#define MAC_FRAME_FILTER_DEFAULT 0x0
+
+struct mac_frame_filter {
+	a_uint32_t  promiscuous_mode:1;
+	a_uint32_t  hash_unicast:1;
+	a_uint32_t  hash_multicast:1;
+	a_uint32_t  da_inverse_filtering:1;
+	a_uint32_t  pass_multicast:1;
+	a_uint32_t  disable_broadcast:1;
+	a_uint32_t  pass_control_frame:2;
+	a_uint32_t  sa_inverse_filtering:1;
+	a_uint32_t  source_addr_filter_enable:1;
+	a_uint32_t  perfect_filter:1;
+	a_uint32_t  reserved_0:5;
+	a_uint32_t  vlan_tag_filter_enable:1;
+	a_uint32_t  resereved_1:3;
+	a_uint32_t  layer_3_4_filter_enable:1;
+	a_uint32_t  drop_non_tcp_udp:1;
+	a_uint32_t  reserved_2:9;
+	a_uint32_t  receive_all:1;
+};
+
+union mac_frame_filter_u {
+	a_uint32_t val;
+	struct mac_frame_filter bf;
+};
+
+/*[register] MAC_FLOW_CTRL*/
+#define MAC_FLOW_CTRL
+#define MAC_FLOW_CTRL_ADDRESS 0x18
+#define MAC_FLOW_CTRL_NUM     2
+#define MAC_FLOW_CTRL_INC     0x100000
+#define MAC_FLOW_CTRL_DEFAULT 0x0
+
+struct mac_flow_ctrl {
+	a_uint32_t  flowctrl_busy:1;
+	a_uint32_t  flowctrl_tx_enable:1;
+	a_uint32_t  flowctrl_rx_enable:1;
+	a_uint32_t  unicast_pause_frame_detect:1;
+	a_uint32_t  pause_low_threshold:2;
+	a_uint32_t  reserved_0:1;
+	a_uint32_t  disable_zero_quanta_pause:1;
+	a_uint32_t  reserved_1:8;
+	a_uint32_t  pause_time:16;
+};
+
+union mac_flow_ctrl_u {
+	a_uint32_t val;
+	struct mac_flow_ctrl bf;
+};
+
+/*[register] LPI_CONTROL_STATUS*/
+#define MAC_LPI_CTRL_STATUS
+#define MAC_LPI_CTRL_STATUS_ADDRESS 0x30
+#define MAC_LPI_CTRL_STATUS_NUM     2
+#define MAC_LPI_CTRL_STATUS_INC     0x100000
+#define MAC_LPI_CTRL_STATUS_DEFAULT 0x0
+
+struct mac_lpi_ctrl_status {
+	a_uint32_t  tx_lpi_entry:1;
+	a_uint32_t  tx_lpi_exit:1;
+	a_uint32_t  rx_lpi_entry:1;
+	a_uint32_t  rx_lpi_exit:1;
+	a_uint32_t  reserved_0:4;
+	a_uint32_t  tx_lpi_state:1;
+	a_uint32_t  rx_lpi_state:1;
+	a_uint32_t  reserved_1:6;
+	a_uint32_t  lpi_enable:1;
+	a_uint32_t  link_status:1;
+	a_uint32_t  link_status_enable:1;
+	a_uint32_t  lpi_tx_auto_enable:1;
+	a_uint32_t  reserved_2:12;
+};
+
+union mac_lpi_ctrl_status_u {
+	a_uint32_t val;
+	struct mac_lpi_ctrl_status bf;
+};
+
+/*[register] LPI_TIMER_CONTROL*/
+#define MAC_LPI_TIMER_CTRL
+#define MAC_LPI_TIMER_CTRL_ADDRESS 0x34
+#define MAC_LPI_TIMER_CTRL_NUM     2
+#define MAC_LPI_TIMER_CTRL_INC     0x100000
+#define MAC_LPI_TIMER_CTRL_DEFAULT 0x0
+
+struct mac_lpi_timer_ctrl {
+	a_uint32_t  lpi_tw_timer:16;
+	a_uint32_t  lpi_ls_timer:10;
+	a_uint32_t  reserved_0:6;
+};
+
+union mac_lpi_timer_ctrl_u {
+	a_uint32_t val;
+	struct mac_lpi_timer_ctrl bf;
+};
+
+/*[register] MAX_FRAME_CONTROL*/
+#define MAC_MAX_FRAME_CTRL
+#define MAC_MAX_FRAME_CTRL_ADDRESS 0xDC
+#define MAC_MAX_FRAME_CTRL_NUM     2
+#define MAC_MAX_FRAME_CTRL_INC     0x100000
+#define MAC_MAX_FRAME_CTRL_DEFAULT 0x0
+
+struct mac_max_frame_ctrl {
+	a_uint32_t  max_frame_ctrl:14;
+	a_uint32_t  reserved_0:2;
+	a_uint32_t  max_frame_ctrl_enable:1;
+};
+
+union mac_max_frame_ctrl_u {
+	a_uint32_t val;
+	struct mac_max_frame_ctrl bf;
+};
+
+/*[register] OPERATION_MODE*/
+#define MAC_OPERATION_MODE_CTRL
+#define MAC_OPERATION_MODE_CTRL_ADDRESS 0x01018
+#define MAC_OPERATION_MODE_CTRL_NUM     2
+#define MAC_OPERATION_MODE_CTRL_INC     0x100000
+#define MAC_OPERATION_MODE_CTRL_DEFAULT 0x0
+
+struct mac_operation_mode_ctrl {
+	a_uint32_t  reserved_0:1;
+	a_uint32_t  stop_receive:1;
+	a_uint32_t  second_frame:1;
+	a_uint32_t  receive_threshold_ctrl:2;
+	a_uint32_t  drop_gaint_frame:1;
+	a_uint32_t  forwad_good_undersize_frame:1;
+	a_uint32_t  forward_error_frame:1;
+	a_uint32_t  enable_hw_flowctrl:1;
+	a_uint32_t  threshold_of_activating:2;
+	a_uint32_t  threshold_of_deactivating:2;
+	a_uint32_t  stop_transmission_command:1;
+	a_uint32_t  transmit_threshold_ctrl:3;
+	a_uint32_t  reserved_1:3;
+	a_uint32_t  flush_transmit_fifo:1;
+	a_uint32_t  transmit_store_and_foward:1;
+	a_uint32_t  msb_threshold_of_deactivating:1;
+	a_uint32_t  msb_threshold_of_activating:1;
+	a_uint32_t  disable_flushing_receiving_frame:1;
+	a_uint32_t  receive_store_and_foward:1;
+	a_uint32_t  disable_dropping_checking_error_frame:1;
+	a_uint32_t  reserved_2:5;
+};
+
+union mac_operation_mode_ctrl_u {
+	a_uint32_t val;
+	struct mac_operation_mode_ctrl bf;
+};
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/mp/mp_uniphy.h b/qca-ssdk/include/hsl/mp/mp_uniphy.h
new file mode 100755
index 0000000..5c3920c
--- /dev/null
+++ b/qca-ssdk/include/hsl/mp/mp_uniphy.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/**
+ * @defgroup
+ * @{
+ */
+
+#ifndef _MP_UNIPHY_H_
+#define _MP_UNIPHY_H_
+
+#define UNIPHY_CLK_DIV_25M                              1
+#define UNIPHY_CLK_DIV_50M                              0
+#define UNIPHY_CLK_DRV_1                                1
+
+sw_error_t
+mp_uniphy_clock_output_control_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_clock_output_control_u *value);
+sw_error_t
+mp_uniphy_clock_output_control_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_clock_output_control_u *value);
+#endif
+
diff --git a/qca-ssdk/include/hsl/mp/mp_uniphy_reg.h b/qca-ssdk/include/hsl/mp/mp_uniphy_reg.h
new file mode 100755
index 0000000..8a50909
--- /dev/null
+++ b/qca-ssdk/include/hsl/mp/mp_uniphy_reg.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/**
+ * @defgroup
+ * @{
+ */
+
+#ifndef MP_UNIPHY_REG_H
+#define MP_UNIPHY_REG_H
+
+#define UNIPHY_CLOCK_OUTPUT_CONTROL_MAX_ENTRY                   1
+/*[register] UNIPHY_ALLREG_DEC_REFCLKOUTPUTCONTROLREGISTERS*/
+#define UNIPHY_CLOCK_OUTPUT_CONTROL
+#define UNIPHY_CLOCK_OUTPUT_CONTROL_ADDRESS                     0x74
+#define UNIPHY_CLOCK_OUTPUT_CONTROL_NUM                         0x1
+#define UNIPHY_CLOCK_OUTPUT_CONTROL_INC                         0x1
+#define UNIPHY_CLOCK_OUTPUT_CONTROL_TYPE                        REG_TYPE_RW
+#define UNIPHY_CLOCK_OUTPUT_CONTROL_DEFAULT                     0x5
+	/*[field] MMD1_REG_REFCLK_OUTPUT_EN*/
+	#define MMD1_REG_REFCLK_OUTPUT_EN
+	#define MMD1_REG_REFCLK_OUTPUT_EN_OFFSET                    0
+	#define MMD1_REG_REFCLK_OUTPUT_EN_LEN                       1
+	#define MMD1_REG_REFCLK_OUTPUT_EN_DEFAULT                   0x1
+	/*[field] MMD1_REG_REFCLK_OUTPUT_DIV*/
+	#define MMD1_REG_REFCLK_OUTPUT_DIV
+	#define MMD1_REG_REFCLK_OUTPUT_DIV_OFFSET                   1
+	#define MMD1_REG_REFCLK_OUTPUT_DIV_LEN                      1
+	#define MMD1_REG_REFCLK_OUTPUT_DIV_DEFAULT                  0x0
+	/*[field] MMD1_REG_REFCLK_OUTPUT_DRV*/
+	#define MMD1_REG_REFCLK_OUTPUT_DRV
+	#define MMD1_REG_REFCLK_OUTPUT_DRV_OFFSET                   2
+	#define MMD1_REG_REFCLK_OUTPUT_DRV_LEN                      2
+	#define MMD1_REG_REFCLK_OUTPUT_DRV_DEFAULT                  0x1
+
+struct uniphy_clock_output_control {
+	a_uint32_t  ref_clk_output_en:1;
+	a_uint32_t  ref_clk_output_div:1;
+	a_uint32_t  ref_clk_output_drv:2;
+	a_uint32_t  _reserved1:28;
+};
+
+union uniphy_clock_output_control_u {
+	a_uint32_t val;
+	struct uniphy_clock_output_control bf;
+};
+#endif
diff --git a/qca-ssdk/include/hsl/phy/aquantia_phy.h b/qca-ssdk/include/hsl/phy/aquantia_phy.h
new file mode 100755
index 0000000..71930d1
--- /dev/null
+++ b/qca-ssdk/include/hsl/phy/aquantia_phy.h
@@ -0,0 +1,394 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _AQUANTIA_PHY_H_
+#define _AQUANTIA_PHY_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif				/* __cplusplus */
+#define PHY_ID_AQ1202	0x03a1b445
+#define PHY_ID_AQ2104	0x03a1b460
+#define PHY_ID_AQR105	0x03a1b4a2
+#define PHY_ID_AQR405	0x03a1b4b0
+#define PHY_ID_AQR107	0x03a1b4e1
+
+#define AQUANTIA_MII_ADDR_C45  (1<<30)
+#define AQUANTIA_REG_ADDRESS(dev_ad, reg_num) (AQUANTIA_MII_ADDR_C45 |\
+			((dev_ad & 0x1f) << 16) | (reg_num & 0xFFFF))
+#define AQUANTIA_MMD_AUTONEG 0x7
+#define AQUANTIA_MMD_PHY_XS_REGISTERS 4
+#define AQUANTIA_MMD_GLOBAL_REGISTERS 0x1E
+#define AQUANTIA_MMD_GBE_STANDARD_REGISTERS 0x1D
+#define AQUANTIA_MMD_PCS_REGISTERS 0x3
+  /* PHY Registers */
+#define AQUANTIA_GLOBAL_STANDARD_CONTROL1        0
+#define AQUANTIA_EEE_ADVERTISTMENT_REGISTER        0x3C
+#define AQUANTIA_EEE_ADVERTISTMENT_REGISTER1        0x3E
+#define AQUANTIA_EEE_PARTNER_ADVERTISTMENT_REGISTER        0x3D
+#define AQUANTIA_EEE_PARTNER_ADVERTISTMENT_REGISTER1        0x3F
+#define AQUANTIA_EEE_CAPABILITY_REGISTER        0x14
+#define AQUANTIA_EEE_CAPABILITY_REGISTER1        0x15
+
+#define AQUANTIA_REG_AUTONEG_VENDOR_STATUS  0xC800
+#define AQUANTIA_AUTONEG_STANDARD_STATUS1  0x1
+#define AQUANTIA_AUTONEG_STANDARD_CONTROL1  0
+#define AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK 0xD401
+#define AQUANTIA_GLOBAL_INTR_STANDARD_MASK 0xff00
+#define AQUANTIA_GLOBAL_INTR_VENDOR_MASK 0xff01
+#define AQUANTIA_PHY_XS_USX_TRANSMIT 0xc441
+#define AQUANTIA_PHY_INTR_STATUS                  19
+#define AQUANTIA_RESERVED_VENDOR_PROVISIONING1  0xC410
+#define AQUANTIA_RESERVED_VENDOR_STATUS1  0xC810
+#define AQUANTIA_GLOBAL_RESERVED_PROVISIONING 0xC47a
+#define AQUANTIA_GLOBAL_RESERVED_PROVISIONING6 0xC475
+#define AQUANTIA_PHY_XS_TRANAMIT_RESERVED_VENDOR_PROVISION5 0xC444
+#define AQUANTIA_CHIP_WIDE_VENDORT_INTERRUPT_FLAGS 0xFC01
+#define AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER 0x10
+#define AQUANTIA_AUTONEG_VENDOR_PROVISION1 0xC400
+#define AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER 0x20
+#define AQUANTIA_AUTONEG_LINK_PARTNER_ABILITY 0x13
+#define AQUANTIA_AUTONEG_LINK_PARTNER_5G_ABILITY 0xE820
+#define AQUANTIA_AUTONEG_LINK_PARTNER_10G_ABILITY 0x21
+
+#define AQUANTIA_GLOBAL_CDT_CONTROL  0xC470
+#define AQUANTIA_GLOBAL_GENERAL_STATUS  0xC831
+#define AQUANTIA_NORMAL_CABLE_DIAGNOSTICS 0x10
+#define AQUANTIA_CABLE_DIAGNOSTICS_STATUS 0x8000
+/*AQUANTIA PHY  LINE SIDE PACKETS COUNTER REGISTER*/
+#define AQUANTIA_LINE_SIDE_TRANSMIT_GOOD_FRAME_COUNTER2 0xc821
+#define AQUANTIA_LINE_SIDE_TRANSMIT_GOOD_FRAME_COUNTER1 0xc820
+#define AQUANTIA_LINE_SIDE_TRANSMIT_ERROR_FRAME_COUNTER2 0xc823
+#define AQUANTIA_LINE_SIDE_TRANSMIT_ERROR_FRAME_COUNTER1 0xc822
+
+#define AQUANTIA_LINE_SIDE_RECEIVE_GOOD_FRAME_COUNTER2 0xe813
+#define AQUANTIA_LINE_SIDE_RECEIVE_GOOD_FRAME_COUNTER1 0xe812
+#define AQUANTIA_LINE_SIDE_RECEIVE_ERROR_FRAME_COUNTER2 0xe815
+#define AQUANTIA_LINE_SIDE_RECEIVE_ERROR_FRAME_COUNTER1 0xe814
+
+/*AQUANTIA PHY  SYSTEM SIDE PACKETS COUNTER REGISTER*/
+#define AQUANTIA_SYSTEM_SIDE_TRANSMIT_GOOD_FRAME_COUNTER2 0xc861
+#define AQUANTIA_SYSTEM_SIDE_TRANSMIT_GOOD_FRAME_COUNTER1 0xc860
+#define AQUANTIA_SYSTEM_SIDE_TRANSMIT_ERROR_FRAME_COUNTER2 0xc863
+#define AQUANTIA_SYSTEM_SIDE_TRANSMIT_ERROR_FRAME_COUNTER1 0xc862
+
+#define AQUANTIA_SYSTEM_SIDE_RECEIVE_GOOD_FRAME_COUNTER2 0xe861
+#define AQUANTIA_SYSTEM_SIDE_RECEIVE_GOOD_FRAME_COUNTER1 0xe860
+#define AQUANTIA_SYSTEM_SIDE_RECEIVE_ERROR_FRAME_COUNTER2 0xe863
+#define AQUANTIA_SYSTEM_SIDE_RECEIVE_ERROR_FRAME_COUNTER1 0xe862
+
+#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS1 0xC800
+#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRA 0x7000/*0XC800, BITC:E*/
+#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRB 0x0700/*0XC800, BITA:8*/
+#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRC 0x0070/*0XC800, BIT6:4*/
+#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRD 0x0007/*0XC800, BIT2:0*/
+
+
+#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS2 0xC801
+#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS4 0xC803
+#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS6 0xC805
+#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS8 0xC807
+#define AQUANTIA_ACT_LED_STATUS 0xc430
+#define AQUANTIA_LINK_LED_STATUS 0xc431
+#define AQUANTIA_ACT_LED_VALUE 0xc0ef
+#define AQUANTIA_LINK_LED_VALUE 0xc0e0
+
+
+#define AQUANTIA_PHY_ID1  0x2
+#define AQUANTIA_PHY_ID2  0x3
+#define AQUANTIA_MAGIC_FRAME_MAC0  0xC339
+#define AQUANTIA_MAGIC_FRAME_MAC1  0xC33a
+#define AQUANTIA_MAGIC_FRAME_MAC2  0xC33b
+#define AQUANTIA_MAGIC_ENGINE_REGISTER1 0xC355
+#define AQUANTIA_MAGIC_ENGINE_REGISTER2 0xC356
+
+#define AQUANTIA_GLOBAL_SYS_CONFIG_FOR_100M 0x31B
+#define AQUANTIA_GLOBAL_SYS_CONFIG_FOR_1000M 0x31C
+#define AQUANTIA_GLOBAL_SYS_CONFIG_FOR_2500M 0x31D
+#define AQUANTIA_GLOBAL_SYS_CONFIG_FOR_5000M 0x31E
+#define AQUANTIA_GLOBAL_SYS_CONFIG_FOR_10000M 0x31F
+
+
+  /* PHY Registers Field */
+#define AQUANTIA_SERDES_MODE_XFI  0
+#define AQUANTIA_SERDES_MODE_SGMII  0x3
+#define AQUANTIA_SERDES_MODE_OCSGMII 0X4
+
+#define AQUANTIA_MAGIC_PACKETS_ENABLE 0x0001
+#define AQUANTIA_PHY_MDIX_CONTRO_BIT  3
+#define AQUANTIA_PHY_MDIX_AUTO  0
+#define AQUANTIA_PHY_MDI  1
+#define AQUANTIA_PHY_MDIX  2
+#define  AQUANTIA_PHY_MDIX_STATUS     0x0100
+#define AQUANTIA_PHY_WOL_ENABLE 0x0040
+#define AQUANTIA_PHY_REMOTE_LOOPBACK 0x1800
+#define AQUANTIA_COMMON_CTRL  0x1040
+#define AQUANTIA_INTERNAL_LOOPBACK 0x4800
+#define AQUANTIA_100M_LOOPBACK  0x0001
+#define AQUANTIA_1000M_LOOPBACK  0x0002
+#define AQUANTIA_10000M_LOOPBACK  0x0003
+#define AQUANTIA_2500M_LOOPBACK  0x0004
+#define AQUANTIA_5000M_LOOPBACK  0x0005
+#define AQUANTIA_POWER_DOWN  0x0800
+#define AQUANTIA_ALL_SPEED_LOOPBACK  (AQUANTIA_100M_LOOPBACK |\
+	AQUANTIA_1000M_LOOPBACK | AQUANTIA_1000M_LOOPBACK |AQUANTIA_2500M_LOOPBACK |\
+	AQUANTIA_5000M_LOOPBACK | AQUANTIA_10000M_LOOPBACK)
+
+#define AQUANTIA_POWER_SAVE  0x0004
+#define AQUANTIA_STATUS_LINK 0x0004
+#define AQUANTIA_EEE_ADV_1000M 0x0004
+#define AQUANTIA_EEE_ADV_2500M 0x0001
+#define AQUANTIA_EEE_ADV_5000M 0x0002
+#define AQUANTIA_EEE_ADV_10000M 0x0008
+#define AQUANTIA_EEE_PARTNER_ADV_1000M 0x0004
+#define AQUANTIA_EEE_PARTNER_ADV_2500M 0x0001
+#define AQUANTIA_EEE_PARTNER_ADV_5000M 0x0002
+#define AQUANTIA_EEE_PARTNER_ADV_10000M 0x0008
+#define AQUANTIA_EEE_CAPABILITY_1000M 0x0004
+#define AQUANTIA_EEE_CAPABILITY_2500M 0x0001
+#define AQUANTIA_EEE_CAPABILITY_5000M 0x0002
+#define AQUANTIA_EEE_CAPABILITY_10000M 0x0008
+
+#define AQUANTIA_PHY_USX_AUTONEG_ENABLE	0x0008
+
+#define AQUANTIA_PHY_RX_FLOWCTRL_STATUS 0x0002
+#define AQUANTIA_PHY_TX_FLOWCTRL_STATUS 0x0001
+  /* FDX =1, half duplex =0 */
+#define AQUANTIA_CTRL_FULL_DUPLEX                 0x0100
+
+  /* Restart auto negotiation */
+#define AQUANTIA_CTRL_RESTART_AUTONEGOTIATION     0x0200
+
+  /* Power down */
+#define AQUANTIA_CTRL_POWER_DOWN                  0x0800
+
+  /* Auto Neg Enable */
+#define AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE      0x1000
+
+  /* Local Loopback Enable */
+#define AQUANTIA_LOCAL_LOOPBACK_ENABLE      0x4000
+
+  /* 0 = normal, 1 = loopback */
+#define AQUANTIA_CTRL_SOFTWARE_RESET              0x8000
+
+#define AQUANTIA_RESET_DONE(phy_control)                   \
+    (((phy_control) & (AQUANTIA_CTRL_SOFTWARE_RESET)) == 0)
+
+  /* Auto Neg Complete */
+#define AQUANTIA_STATUS_AUTO_NEG_DONE             0x0020
+
+#define AQUANTIA_AUTONEG_DONE(ip_phy_status) \
+    (((ip_phy_status) & (AQUANTIA_STATUS_AUTO_NEG_DONE)) ==  \
+        (AQUANTIA_STATUS_AUTO_NEG_DONE))
+
+/*AQUANTIA interrupt flag */
+#define AQUANTIA_INTR_DUPLEX_CHANGE             0x2000
+#define AQUANTIA_INTR_LINK_STATUS_CHANGE          0x0001
+#define AQUANTIA_ALL_VENDOR_ALARMS_INTR_MASK  0x0001
+#define AQUANTIA_AUTO_AND_ALARMS_INTR_MASK 0x1001
+
+  /* 10T   Half Duplex Capable */
+#define AQUANTIA_ADVERTISE_10HALF                 0x0020
+
+  /* 10T   Full Duplex Capable */
+#define AQUANTIA_ADVERTISE_10FULL                 0x0040
+
+  /* 100TX Half Duplex Capable */
+#define AQUANTIA_ADVERTISE_100HALF                0x0080
+
+  /* 100TX Full Duplex Capable */
+#define AQUANTIA_ADVERTISE_100FULL                0x0100
+
+  /* Pause operation desired */
+#define AQUANTIA_ADVERTISE_PAUSE                  0x0400
+
+  /* Asymmetric Pause Direction bit */
+#define AQUANTIA_ADVERTISE_ASYM_PAUSE             0x0800
+
+  /* Remote Fault detected */
+#define AQUANTIA_ADVERTISE_REMOTE_FAULT           0x2000
+
+  /* Next Page ability supported */
+#define AQUANTIA_ADVERTISE_NEXT_PAGE              0x8000
+
+  /* 1000TX Half Duplex Capable */
+#define AQUANTIA_ADVERTISE_1000HALF                0x4000
+
+  /* 1000TX Full Duplex Capable */
+#define AQUANTIA_ADVERTISE_1000FULL                0x8000
+
+  /* 2500TX Full Duplex Capable */
+#define AQUANTIA_ADVERTISE_2500FULL                0x0400
+#define AQUANTIA_ADVERTISE_8023BZ_2500FULL                0x80
+
+  /* 10000TX Full Duplex Capable */
+#define AQUANTIA_ADVERTISE_10000FULL                0x1000
+
+  /* 5000TX Full Duplex Capable */
+#define AQUANTIA_ADVERTISE_5000FULL                0x0800
+#define AQUANTIA_ADVERTISE_8023BZ_5000FULL                0x100
+
+#define AQUANTIA_ADVERTISE_ALL \
+    (AQUANTIA_ADVERTISE_10HALF | AQUANTIA_ADVERTISE_10FULL | \
+     AQUANTIA_ADVERTISE_100HALF | AQUANTIA_ADVERTISE_100FULL | \
+     AQUANTIA_ADVERTISE_1000HALF |AQUANTIA_ADVERTISE_1000FULL |\
+     AQUANTIA_ADVERTISE_10000FULL | AQUANTIA_ADVERTISE_2500FULL |\
+     AQUANTIA_ADVERTISE_5000FULL)
+
+#define AQUANTIA_ADVERTISE_MEGA_ALL \
+    (AQUANTIA_ADVERTISE_10HALF | AQUANTIA_ADVERTISE_10FULL | \
+     AQUANTIA_ADVERTISE_100HALF | AQUANTIA_ADVERTISE_100FULL)
+
+#define AQUANTIA_ADVERTISE_GIGA_ALL \
+  (AQUANTIA_ADVERTISE_1000HALF |AQUANTIA_ADVERTISE_1000FULL |\
+ AQUANTIA_ADVERTISE_2500FULL |  AQUANTIA_ADVERTISE_5000FULL)
+ 
+  #define AQUANTIA_ADVERTISE_GIGA_PLUS_ALL \
+	(AQUANTIA_ADVERTISE_10000FULL | AQUANTIA_ADVERTISE_8023BZ_2500FULL|\
+	AQUANTIA_ADVERTISE_8023BZ_5000FULL)
+
+
+#define AQUANTIA_BX_ADVERTISE_1000FULL                0x0020
+#define AQUANTIA_BX_ADVERTISE_1000HALF                0x0040
+#define AQUANTIA_BX_ADVERTISE_PAUSE                      0x0080
+#define AQUANTIA_BX_ADVERTISE_ASYM_PAUSE           0x0100
+
+#define AQUANTIA_BX_ADVERTISE_ALL \
+    (AQUANTIA_BX_ADVERTISE_ASYM_PAUSE | AQUANTIA_BX_ADVERTISE_PAUSE | \
+     AQUANTIA_BX_ADVERTISE_1000HALF | AQUANTIA_BX_ADVERTISE_1000FULL)
+
+  /* Link Partner ability offset:5 */
+  /* Same as advertise selector  */
+#define AQUANTIA_LINK_SLCT                        0x001f
+
+  /* Can do 10mbps half-duplex   */
+#define AQUANTIA_LINK_10BASETX_HALF_DUPLEX        0x0020
+
+  /* Can do 10mbps full-duplex   */
+#define AQUANTIA_LINK_10BASETX_FULL_DUPLEX        0x0040
+
+  /* Can do 100mbps half-duplex  */
+#define AQUANTIA_LINK_100BASETX_HALF_DUPLEX       0x0080
+#define AQUANTIA_LINK_100BASETX_FULL_DUPLEX       0x0100
+/*Can do 1G*/
+
+#define AQUANTIA_LINK_1000BASETX_FULL_DUPLEX       0x8000
+  /*Can do 5G*/
+#define AQUANTIA_LINK_5000BASETX_FULL_DUPLEX       0x0800
+/*Can do 2.5G*/
+#define AQUANTIA_LINK_2500BASETX_FULL_DUPLEX       0x0400
+/*Can do 10G*/
+#define AQUANTIA_LINK_10000BASETX_FULL_DUPLEX       0x1
+
+
+
+  /* 1=Duplex 0=Half Duplex */
+#define AQUANTIA_STATUS_FULL_DUPLEX               0x0001
+
+  /* Speed, bits 1 : 3*/
+#define AQUANTIA_STATUS_SPEED                   	     0xC000
+#define AQUANTIA_STATUS_SPEED_MASK               0x000E
+  /* 000=10Mbs */
+#define AQUANTIA_STATUS_SPEED_10MBS              0x0000
+  /* 001=100Mbs */
+#define AQUANTIA_STATUS_SPEED_100MBS           0x0001
+  /* 010=1000Mbs */
+#define AQUANTIA_STATUS_SPEED_1000MBS         0x0002
+  /* 011=10000Mbs */
+#define AQUANTIA_STATUS_SPEED_10000MBS      0x0003
+  /* 100=2500Mbs */
+#define AQUANTIA_STATUS_SPEED_2500MBS         0x0004
+  /* 101=5000Mbs */
+#define AQUANTIA_STATUS_SPEED_5000MBS         0x0005
+
+#define RUN_CDT 0x8000
+#define CABLE_LENGTH_UNIT 0x0400
+#define AQUANTIA_PHY_CDT_MODE0 0
+#define AQUANTIA_PHY_CDT_MODE1 1
+#define AQUANTIA_PHY_CDT_MODE2 2
+
+/** Phy pages */
+  typedef enum
+  {
+    AQUANTIA_PHY_SGBX_PAGES = 0,
+				       /**< sgbx pages */
+    AQUANTIA_PHY_COPPER_PAGES = 1
+				       /**< copper pages */
+  } AQUANTIA_PHY_reg_pages_t;
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+   aquantia_phy_set_powersave (a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_bool_t enable);
+
+sw_error_t
+   aquantia_phy_get_powersave (a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_bool_t * enable);
+
+sw_error_t
+   aquantia_phy_cdt (a_uint32_t dev_id, a_uint32_t phy_id,
+		    a_uint32_t mdi_pair,
+		    fal_cable_status_t * cable_status,
+		    a_uint32_t * cable_len);
+#endif
+sw_error_t
+   aquantia_phy_set_duplex (a_uint32_t dev_id, a_uint32_t phy_id,
+			   fal_port_duplex_t duplex);
+
+sw_error_t
+   aquantia_phy_get_duplex (a_uint32_t dev_id, a_uint32_t phy_id,
+			   fal_port_duplex_t * duplex);
+
+sw_error_t
+   aquantia_phy_set_speed (a_uint32_t dev_id, a_uint32_t phy_id,
+			  fal_port_speed_t speed);
+
+sw_error_t
+aquantia_phy_get_speed (a_uint32_t dev_id, a_uint32_t phy_id,
+			  fal_port_speed_t * speed);
+
+sw_error_t
+   aquantia_phy_restart_autoneg (a_uint32_t dev_id, a_uint32_t phy_id);
+
+sw_error_t
+   aquantia_phy_enable_autoneg (a_uint32_t dev_id, a_uint32_t phy_id);
+
+a_bool_t
+   aquantia_phy_get_link_status (a_uint32_t dev_id, a_uint32_t phy_id);
+
+sw_error_t
+   aquantia_phy_set_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id,
+				a_uint32_t autoneg);
+
+sw_error_t
+   aquantia_phy_get_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id,
+				a_uint32_t * autoneg);
+
+a_bool_t
+   aquantia_phy_autoneg_status (a_uint32_t dev_id, a_uint32_t phy_id);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+   aquantia_phy_intr_mask_set (a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_uint32_t intr_mask_flag);
+
+sw_error_t
+   aquantia_phy_intr_mask_get (a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_uint32_t * intr_mask_flag);
+#endif
+int aquantia_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp);
+
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* _AQUANTIA_PHY_H_ */
diff --git a/qca-ssdk/include/hsl/phy/f1_phy.h b/qca-ssdk/include/hsl/phy/f1_phy.h
new file mode 100755
index 0000000..b3f7ed2
--- /dev/null
+++ b/qca-ssdk/include/hsl/phy/f1_phy.h
@@ -0,0 +1,479 @@
+/*
+ * Copyright (c) 2012, 2015, 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _F1_PHY_H_
+#define _F1_PHY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+    /* PHY Registers */
+#define F1_PHY_CONTROL                      0
+#define F1_PHY_STATUS                       1
+#define F1_PHY_ID1                          2
+#define F1_PHY_ID2                          3
+#define F1_AUTONEG_ADVERT                   4
+#define F1_LINK_PARTNER_ABILITY             5
+#define F1_AUTONEG_EXPANSION                6
+#define F1_NEXT_PAGE_TRANSMIT               7
+#define F1_LINK_PARTNER_NEXT_PAGE           8
+#define F1_1000BASET_CONTROL                9
+#define F1_1000BASET_STATUS                 10
+#define F1_MMD_CTRL_REG                     13
+#define F1_MMD_DATA_REG                     14
+#define F1_EXTENDED_STATUS                  15
+#define F1_PHY_SPEC_CONTROL                 16
+#define F1_PHY_SPEC_STATUS                  17
+#define F1_PHY_INTR_MASK                    18
+#define F1_PHY_INTR_STATUS                  19
+#define F1_PHY_CDT_CONTROL                  22
+#define F1_PHY_CDT_STATUS                   28
+#define F1_DEBUG_PORT_ADDRESS               29
+#define F1_DEBUG_PORT_DATA                  30
+#define F1_PHY_8023AZ_EEE_CTRL	0x3c
+#define F1_PHY_MMD7_NUM	7
+#define F1_PHY_AZ_ENABLE	0x6
+
+    /*debug port*/
+#define F1_DEBUG_PORT_RGMII_MODE            18
+#define F1_DEBUG_PORT_RGMII_MODE_EN         0x0008
+
+#define F1_DEBUG_PORT_RX_DELAY            0
+#define F1_DEBUG_PORT_RX_DELAY_EN         0x8000
+
+#define F1_DEBUG_PORT_TX_DELAY            5
+#define F1_DEBUG_PORT_TX_DELAY_EN         0x0100
+
+    /* PHY Registers Field*/
+
+    /* Control Register fields  offset:0*/
+    /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define F1_CTRL_SPEED_MSB                   0x0040
+
+    /* Collision test enable */
+#define F1_CTRL_COLL_TEST_ENABLE            0x0080
+
+    /* FDX =1, half duplex =0 */
+#define F1_CTRL_FULL_DUPLEX                 0x0100
+
+    /* Restart auto negotiation */
+#define F1_CTRL_RESTART_AUTONEGOTIATION     0x0200
+
+    /* Isolate PHY from MII */
+#define F1_CTRL_ISOLATE                     0x0400
+
+    /* Power down */
+#define F1_CTRL_POWER_DOWN                  0x0800
+
+    /* Auto Neg Enable */
+#define F1_CTRL_AUTONEGOTIATION_ENABLE      0x1000
+
+    /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define F1_CTRL_SPEED_LSB                   0x2000
+
+    /* 0 = normal, 1 = loopback */
+#define F1_LOCAL_LOOPBACK_ENABLE            0x4000
+#define F1_COMMON_CTRL                      0x1040
+#define F1_10M_LOOPBACK                     0x4100
+#define F1_100M_LOOPBACK                    0x6100
+#define F1_1000M_LOOPBACK                   0x4140
+
+#define F1_PHY_MMD3_NUM  3
+#define F1_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL       0x805a
+#define F1_PHY_REMOTE_LOOPBACK_ENABLE       0x0001
+#define F1_CTRL_SOFTWARE_RESET              0x8000
+
+#define F1_CTRL_SPEED_MASK                  0x2040
+#define F1_CTRL_SPEED_1000                  0x0040
+#define F1_CTRL_SPEED_100                   0x2000
+#define F1_CTRL_SPEED_10                    0x0000
+
+#define F1_RESET_DONE(phy_control)                   \
+    (((phy_control) & (F1_CTRL_SOFTWARE_RESET)) == 0)
+
+    /* Status Register fields offset:1*/
+    /* Extended register capabilities */
+#define F1_STATUS_EXTENDED_CAPS             0x0001
+
+    /* Jabber Detected */
+#define F1_STATUS_JABBER_DETECT             0x0002
+
+    /* Link Status 1 = link */
+#define F1_STATUS_LINK_STATUS_UP            0x0004
+
+    /* Auto Neg Capable */
+#define F1_STATUS_AUTONEG_CAPS              0x0008
+
+    /* Remote Fault Detect */
+#define F1_STATUS_REMOTE_FAULT              0x0010
+
+    /* Auto Neg Complete */
+#define F1_STATUS_AUTO_NEG_DONE             0x0020
+
+    /* Preamble may be suppressed */
+#define F1_STATUS_PREAMBLE_SUPPRESS         0x0040
+
+    /* Ext. status info in Reg 0x0F */
+#define F1_STATUS_EXTENDED_STATUS           0x0100
+
+    /* 100T2 Half Duplex Capable */
+#define F1_STATUS_100T2_HD_CAPS             0x0200
+
+    /* 100T2 Full Duplex Capable */
+#define F1_STATUS_100T2_FD_CAPS             0x0400
+
+    /* 10T   Half Duplex Capable */
+#define F1_STATUS_10T_HD_CAPS               0x0800
+
+    /* 10T   Full Duplex Capable */
+#define F1_STATUS_10T_FD_CAPS               0x1000
+
+    /* 100X  Half Duplex Capable */
+#define F1_STATUS_100X_HD_CAPS              0x2000
+
+    /* 100X  Full Duplex Capable */
+#define F1_STATUS_100X_FD_CAPS              0x4000
+
+    /* 100T4 Capable */
+#define F1_STATUS_100T4_CAPS                0x8000
+
+    /* extended status register capabilities */
+
+#define F1_STATUS_1000T_HD_CAPS             0x1000
+
+#define F1_STATUS_1000T_FD_CAPS             0x2000
+
+#define F1_STATUS_1000X_HD_CAPS             0x4000
+
+#define F1_STATUS_1000X_FD_CAPS             0x8000
+
+#define F1_AUTONEG_DONE(ip_phy_status) \
+    (((ip_phy_status) & (F1_STATUS_AUTO_NEG_DONE)) ==  \
+        (F1_STATUS_AUTO_NEG_DONE))
+
+    /* PHY identifier1  offset:2*/
+//Organizationally Unique Identifier bits 3:18
+
+    /* PHY identifier2  offset:3*/
+//Organizationally Unique Identifier bits 19:24
+
+    /* Auto-Negotiation Advertisement register. offset:4*/
+    /* indicates IEEE 802.3 CSMA/CD */
+#define F1_ADVERTISE_SELECTOR_FIELD         0x0001
+
+    /* 10T   Half Duplex Capable */
+#define F1_ADVERTISE_10HALF                 0x0020
+
+    /* 10T   Full Duplex Capable */
+#define F1_ADVERTISE_10FULL                 0x0040
+
+    /* 100TX Half Duplex Capable */
+#define F1_ADVERTISE_100HALF                0x0080
+
+    /* 100TX Full Duplex Capable */
+#define F1_ADVERTISE_100FULL                0x0100
+
+    /* 100T4 Capable */
+#define F1_ADVERTISE_100T4                  0x0200
+
+    /* Pause operation desired */
+#define F1_ADVERTISE_PAUSE                  0x0400
+
+    /* Asymmetric Pause Direction bit */
+#define F1_ADVERTISE_ASYM_PAUSE             0x0800
+
+    /* Remote Fault detected */
+#define F1_ADVERTISE_REMOTE_FAULT           0x2000
+
+    /* Next Page ability supported */
+#define F1_ADVERTISE_NEXT_PAGE              0x8000
+
+    /* 100TX Half Duplex Capable */
+#define F1_ADVERTISE_1000HALF                0x0100
+
+    /* 100TX Full Duplex Capable */
+#define F1_ADVERTISE_1000FULL                0x0200
+
+#define F1_ADVERTISE_ALL \
+    (F1_ADVERTISE_10HALF | F1_ADVERTISE_10FULL | \
+     F1_ADVERTISE_100HALF | F1_ADVERTISE_100FULL | \
+     F1_ADVERTISE_1000FULL)
+
+#define F1_ADVERTISE_MEGA_ALL \
+    (F1_ADVERTISE_10HALF | F1_ADVERTISE_10FULL | \
+     F1_ADVERTISE_100HALF | F1_ADVERTISE_100FULL)
+
+    /* Link Partner ability offset:5*/
+    /* Same as advertise selector  */
+#define F1_LINK_SLCT                        0x001f
+
+    /* Can do 10mbps half-duplex   */
+#define F1_LINK_10BASETX_HALF_DUPLEX        0x0020
+
+    /* Can do 10mbps full-duplex   */
+#define F1_LINK_10BASETX_FULL_DUPLEX        0x0040
+
+    /* Can do 100mbps half-duplex  */
+#define F1_LINK_100BASETX_HALF_DUPLEX       0x0080
+
+    /* Can do 100mbps full-duplex  */
+#define F1_LINK_100BASETX_FULL_DUPLEX       0x0100
+
+    /* Can do 1000mbps full-duplex  */
+#define F1_LINK_1000BASETX_FULL_DUPLEX       0x0800
+
+    /* Can do 1000mbps half-duplex  */
+#define F1_LINK_1000BASETX_HALF_DUPLEX       0x0400
+
+    /* 100BASE-T4  */
+#define F1_LINK_100BASE4                    0x0200
+
+    /* PAUSE */
+#define F1_LINK_PAUSE                       0x0400
+
+    /* Asymmetrical PAUSE */
+#define F1_LINK_ASYPAUSE                    0x0800
+
+    /* Link partner faulted  */
+#define F1_LINK_RFAULT                      0x2000
+
+    /* Link partner acked us */
+#define F1_LINK_LPACK                       0x4000
+
+    /* Next page bit  */
+#define F1_LINK_NPAGE                       0x8000
+
+    /* Auto-Negotiation Expansion Register offset:6 */
+
+    /* Next Page Transmit Register offset:7 */
+
+    /* Link partner Next Page Register offset:8*/
+
+    /* 1000BASE-T Control Register offset:9*/
+    /* Advertise 1000T HD capability */
+#define F1_CTL_1000T_HD_CAPS                0x0100
+
+    /* Advertise 1000T FD capability  */
+#define F1_CTL_1000T_FD_CAPS                0x0200
+
+    /* 1=Repeater/switch device port 0=DTE device*/
+#define F1_CTL_1000T_REPEATER_DTE           0x0400
+
+    /* 1=Configure PHY as Master  0=Configure PHY as Slave */
+#define F1_CTL_1000T_MS_VALUE               0x0800
+
+    /* 1=Master/Slave manual config value  0=Automatic Master/Slave config */
+#define F1_CTL_1000T_MS_ENABLE              0x1000
+
+    /* Normal Operation */
+#define F1_CTL_1000T_TEST_MODE_NORMAL       0x0000
+
+    /* Transmit Waveform test */
+#define F1_CTL_1000T_TEST_MODE_1            0x2000
+
+    /* Master Transmit Jitter test */
+#define F1_CTL_1000T_TEST_MODE_2            0x4000
+
+    /* Slave Transmit Jitter test */
+#define F1_CTL_1000T_TEST_MODE_3            0x6000
+
+    /* Transmitter Distortion test */
+#define F1_CTL_1000T_TEST_MODE_4            0x8000
+#define F1_CTL_1000T_SPEED_MASK             0x0300
+#define F1_CTL_1000T_DEFAULT_CAP_MASK       0x0300
+
+    /* 1000BASE-T Status Register offset:10 */
+    /* LP is 1000T HD capable */
+#define F1_STATUS_1000T_LP_HD_CAPS          0x0400
+
+    /* LP is 1000T FD capable */
+#define F1_STATUS_1000T_LP_FD_CAPS          0x0800
+
+    /* Remote receiver OK */
+#define F1_STATUS_1000T_REMOTE_RX_STATUS    0x1000
+
+    /* Local receiver OK */
+#define F1_STATUS_1000T_LOCAL_RX_STATUS     0x2000
+
+    /* 1=Local TX is Master, 0=Slave */
+#define F1_STATUS_1000T_MS_CONFIG_RES       0x4000
+
+#define F1_STATUS_1000T_MS_CONFIG_FAULT     0x8000
+
+    /* Master/Slave config fault */
+#define F1_STATUS_1000T_REMOTE_RX_STATUS_SHIFT   12
+#define F1_STATUS_1000T_LOCAL_RX_STATUS_SHIFT    13
+
+    /* Phy Specific Control Register offset:16*/
+    /* 1=Jabber Function disabled */
+#define F1_CTL_JABBER_DISABLE               0x0001
+
+    /* 1=Polarity Reversal enabled */
+#define F1_CTL_POLARITY_REVERSAL            0x0002
+
+    /* 1=SQE Test enabled */
+#define F1_CTL_SQE_TEST                     0x0004
+#define F1_CTL_MAC_POWERDOWN                0x0008
+
+    /* 1=CLK125 low, 0=CLK125 toggling
+    #define F1_CTL_CLK125_DISABLE               0x0010
+     */
+    /* MDI Crossover Mode bits 6:5 */
+    /* Manual MDI configuration */
+#define F1_CTL_MDI_MANUAL_MODE              0x0000
+
+    /* Manual MDIX configuration */
+#define F1_CTL_MDIX_MANUAL_MODE             0x0020
+
+    /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
+#define F1_CTL_AUTO_X_1000T                 0x0040
+
+    /* Auto crossover enabled all speeds */
+#define F1_CTL_AUTO_X_MODE                  0x0060
+
+    /* 1=Enable Extended 10BASE-T distance
+      * (Lower 10BASE-T RX Threshold)
+     * 0=Normal 10BASE-T RX Threshold */
+#define F1_CTL_10BT_EXT_DIST_ENABLE         0x0080
+
+    /* 1=5-Bit interface in 100BASE-TX
+      * 0=MII interface in 100BASE-TX */
+#define F1_CTL_MII_5BIT_ENABLE              0x0100
+
+    /* 1=Scrambler disable */
+#define F1_CTL_SCRAMBLER_DISABLE            0x0200
+
+    /* 1=Force link good */
+#define F1_CTL_FORCE_LINK_GOOD              0x0400
+
+    /* 1=Assert CRS on Transmit */
+#define F1_CTL_ASSERT_CRS_ON_TX             0x0800
+
+#define F1_CTL_POLARITY_REVERSAL_SHIFT      1
+#define F1_CTL_AUTO_X_MODE_SHIFT            5
+#define F1_CTL_10BT_EXT_DIST_ENABLE_SHIFT   7
+
+    /* Phy Specific status fields offset:17*/
+    /* 1=Speed & Duplex resolved */
+#define F1_STATUS_LINK_PASS                 0x0400
+#define F1_STATUS_RESOVLED                  0x0800
+
+    /* 1=Duplex 0=Half Duplex */
+#define F1_STATUS_FULL_DUPLEX               0x2000
+
+    /* Speed, bits 14:15 */
+#define F1_STATUS_SPEED                    0xC000
+#define F1_STATUS_SPEED_MASK               0xC000
+
+    /* 00=10Mbs */
+#define F1_STATUS_SPEED_10MBS              0x0000
+
+    /* 01=100Mbs */
+#define F1_STATUS_SPEED_100MBS             0x4000
+
+    /* 10=1000Mbs */
+#define F1_STATUS_SPEED_1000MBS            0x8000
+#define F1_SPEED_DUPLEX_RESOVLED(phy_status)                   \
+    (((phy_status) &                                  \
+        (F1_STATUS_RESOVLED)) ==                    \
+        (F1_STATUS_RESOVLED))
+
+    /*phy debug port1 register offset:29*/
+    /*phy debug port2 register offset:30*/
+
+    /*F1 interrupt flag */
+#define F1_INTR_SPEED_CHANGE              0x4000
+#define F1_INTR_DUPLEX_CHANGE             0x2000
+#define F1_INTR_STATUS_UP_CHANGE          0x0400
+#define F1_INTR_STATUS_DOWN_CHANGE        0x0800
+
+    sw_error_t
+    f1_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable);
+
+    sw_error_t
+    f1_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable);
+
+    sw_error_t
+    f1_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable);
+
+    sw_error_t
+    f1_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable);
+
+    sw_error_t
+    f1_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+               fal_cable_status_t *cable_status, a_uint32_t *cable_len) ;
+
+    sw_error_t
+    f1_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+                      fal_port_duplex_t duplex);
+
+    sw_error_t
+    f1_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+                      fal_port_duplex_t * duplex);
+
+    sw_error_t
+    f1_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+                     fal_port_speed_t speed);
+
+    sw_error_t
+    f1_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+                     fal_port_speed_t * speed);
+
+    sw_error_t
+    f1_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id);
+
+    sw_error_t
+    f1_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id);
+
+    a_bool_t
+    f1_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id);
+
+    sw_error_t
+    f1_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+                           a_uint32_t autoneg);
+
+    sw_error_t
+    f1_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+                           a_uint32_t * autoneg);
+
+    a_bool_t f1_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id);
+
+    sw_error_t
+    f1_phy_intr_mask_set(a_uint32_t dev_id, a_uint32_t phy_id,
+                         a_uint32_t intr_mask_flag);
+
+    sw_error_t
+    f1_phy_intr_mask_get(a_uint32_t dev_id, a_uint32_t phy_id,
+                         a_uint32_t * intr_mask_flag);
+
+    sw_error_t
+    f1_phy_intr_status_get(a_uint32_t dev_id, a_uint32_t phy_id,
+                           a_uint32_t * intr_status_flag);
+
+    sw_error_t
+    f1_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable);
+
+    sw_error_t
+    f1_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable);
+
+    int
+    f1_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _F1_PHY_H_ */
diff --git a/qca-ssdk/include/hsl/phy/f2_phy.h b/qca-ssdk/include/hsl/phy/f2_phy.h
new file mode 100755
index 0000000..13ce278
--- /dev/null
+++ b/qca-ssdk/include/hsl/phy/f2_phy.h
@@ -0,0 +1,399 @@
+/*
+ * Copyright (c) 2012, 2015, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _F2_PHY_H_
+#define _F2_PHY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+    /* Athena PHY Registers */
+#define F2_PHY_CONTROL                      0
+#define F2_PHY_STATUS                       1
+#define F2_PHY_ID1                          2
+#define F2_PHY_ID2                          3
+#define F2_AUTONEG_ADVERT                   4
+#define F2_LINK_PARTNER_ABILITY             5
+#define F2_AUTONEG_EXPANSION                6
+#define F2_NEXT_PAGE_TRANSMIT               7
+#define F2_LINK_PARTNER_NEXT_PAGE           8
+#define F2_1000BASET_CONTROL                9
+#define F2_1000BASET_STATUS                 10
+#define F2_PHY_SPEC_CONTROL                 16
+#define F2_PHY_SPEC_STATUS                  17
+#define F2_PHY_CDT_CONTROL                  22
+#define F2_PHY_CDT_STATUS                   28
+#define F2_DEBUG_PORT_ADDRESS               29
+#define F2_DEBUG_PORT_DATA                  30
+
+    /* Athena PHY Registers Field*/
+
+    /* Control Register fields  offset:0*/
+    /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define F2_CTRL_SPEED_MSB                   0x0040
+
+    /* Collision test enable */
+#define F2_CTRL_COLL_TEST_ENABLE            0x0080
+
+    /* FDX =1, half duplex =0 */
+#define F2_CTRL_FULL_DUPLEX                 0x0100
+
+    /* Restart auto negotiation */
+#define F2_CTRL_RESTART_AUTONEGOTIATION     0x0200
+
+    /* Isolate PHY from MII */
+#define F2_CTRL_ISOLATE                     0x0400
+
+    /* Power down */
+#define F2_CTRL_POWER_DOWN                  0x0800
+
+    /* Auto Neg Enable */
+#define F2_CTRL_AUTONEGOTIATION_ENABLE      0x1000
+
+    /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define F2_CTRL_SPEED_LSB                   0x2000
+
+    /* 0 = normal, 1 = loopback */
+#define F2_CTRL_LOOPBACK                    0x4000
+#define F2_CTRL_SOFTWARE_RESET              0x8000
+
+#define F2_CTRL_SPEED_MASK                  0x2040
+#define F2_CTRL_SPEED_1000                  0x0040
+#define F2_CTRL_SPEED_100                   0x2000
+#define F2_CTRL_SPEED_10                    0x0000
+
+#define F2_RESET_DONE(phy_control)                   \
+    (((phy_control) & (F2_CTRL_SOFTWARE_RESET)) == 0)
+
+    /* Status Register fields offset:1*/
+    /* Extended register capabilities */
+#define F2_STATUS_EXTENDED_CAPS             0x0001
+
+    /* Jabber Detected */
+#define F2_STATUS_JABBER_DETECT             0x0002
+
+    /* Link Status 1 = link */
+#define F2_STATUS_LINK_STATUS_UP            0x0004
+
+    /* Auto Neg Capable */
+#define F2_STATUS_AUTONEG_CAPS              0x0008
+
+    /* Remote Fault Detect */
+#define F2_STATUS_REMOTE_FAULT              0x0010
+
+    /* Auto Neg Complete */
+#define F2_STATUS_AUTO_NEG_DONE             0x0020
+
+    /* Preamble may be suppressed */
+#define F2_STATUS_PREAMBLE_SUPPRESS         0x0040
+
+    /* Ext. status info in Reg 0x0F */
+#define F2_STATUS_EXTENDED_STATUS           0x0100
+
+    /* 100T2 Half Duplex Capable */
+#define F2_STATUS_100T2_HD_CAPS             0x0200
+
+    /* 100T2 Full Duplex Capable */
+#define F2_STATUS_100T2_FD_CAPS             0x0400
+
+    /* 10T   Half Duplex Capable */
+#define F2_STATUS_10T_HD_CAPS               0x0800
+
+    /* 10T   Full Duplex Capable */
+#define F2_STATUS_10T_FD_CAPS               0x1000
+
+    /* 100X  Half Duplex Capable */
+#define F2_STATUS_100X_HD_CAPS              0x2000
+
+    /* 100X  Full Duplex Capable */
+#define F2_STATUS_100X_FD_CAPS              0x4000
+
+    /* 100T4 Capable */
+#define F2_STATUS_100T4_CAPS                0x8000
+
+#define F2_AUTONEG_DONE(ip_phy_status) \
+    (((ip_phy_status) & (F2_STATUS_AUTO_NEG_DONE)) ==  \
+        (F2_STATUS_AUTO_NEG_DONE))
+
+    /* PHY identifier1  offset:2*/
+//Organizationally Unique Identifier bits 3:18
+
+    /* PHY identifier2  offset:3*/
+//Organizationally Unique Identifier bits 19:24
+
+    /* Auto-Negotiation Advertisement register. offset:4*/
+    /* indicates IEEE 802.3 CSMA/CD */
+#define F2_ADVERTISE_SELECTOR_FIELD         0x0001
+
+    /* 10T   Half Duplex Capable */
+#define F2_ADVERTISE_10HALF                 0x0020
+
+    /* 10T   Full Duplex Capable */
+#define F2_ADVERTISE_10FULL                 0x0040
+
+    /* 100TX Half Duplex Capable */
+#define F2_ADVERTISE_100HALF                0x0080
+
+    /* 100TX Full Duplex Capable */
+#define F2_ADVERTISE_100FULL                0x0100
+
+    /* 100T4 Capable */
+#define F2_ADVERTISE_100T4                  0x0200
+
+    /* Pause operation desired */
+#define F2_ADVERTISE_PAUSE                  0x0400
+
+    /* Asymmetric Pause Direction bit */
+#define F2_ADVERTISE_ASYM_PAUSE             0x0800
+
+    /* Remote Fault detected */
+#define F2_ADVERTISE_REMOTE_FAULT           0x2000
+
+    /* Next Page ability supported */
+#define F2_ADVERTISE_NEXT_PAGE              0x8000
+
+#define F2_ADVERTISE_ALL \
+    (F2_ADVERTISE_10HALF | F2_ADVERTISE_10FULL | \
+     F2_ADVERTISE_100HALF | F2_ADVERTISE_100FULL )
+
+    /* Link Partner ability offset:5*/
+    /* Same as advertise selector  */
+#define F2_LINK_SLCT                        0x001f
+
+    /* Can do 10mbps half-duplex   */
+#define F2_LINK_10BASETX_HALF_DUPLEX        0x0020
+
+    /* Can do 10mbps full-duplex   */
+#define F2_LINK_10BASETX_FULL_DUPLEX        0x0040
+
+    /* Can do 100mbps half-duplex  */
+#define F2_LINK_100BASETX_HALF_DUPLEX       0x0080
+
+    /* Can do 100mbps full-duplex  */
+#define F2_LINK_100BASETX_FULL_DUPLEX       0x0100
+
+    /* 100BASE-T4  */
+#define F2_LINK_100BASE4                    0x0200
+
+    /* PAUSE */
+#define F2_LINK_PAUSE                       0x0400
+
+    /* Asymmetrical PAUSE */
+#define F2_LINK_ASYPAUSE                    0x0800
+
+    /* Link partner faulted  */
+#define F2_LINK_RFAULT                      0x2000
+
+    /* Link partner acked us */
+#define F2_LINK_LPACK                       0x4000
+
+    /* Next page bit  */
+#define F2_LINK_NPAGE                       0x8000
+
+    /* Auto-Negotiation Expansion Register offset:6 */
+
+    /* Next Page Transmit Register offset:7 */
+
+    /* Link partner Next Page Register offset:8*/
+
+    /* 1000BASE-T Control Register offset:9*/
+    /* Advertise 1000T HD capability */
+#define F2_CTL_1000T_HD_CAPS                0x0100
+
+    /* Advertise 1000T FD capability  */
+#define F2_CTL_1000T_FD_CAPS                0x0200
+
+    /* 1=Repeater/switch device port 0=DTE device*/
+#define F2_CTL_1000T_REPEATER_DTE           0x0400
+
+    /* 1=Configure PHY as Master  0=Configure PHY as Slave */
+#define F2_CTL_1000T_MS_VALUE               0x0800
+
+    /* 1=Master/Slave manual config value  0=Automatic Master/Slave config */
+#define F2_CTL_1000T_MS_ENABLE              0x1000
+
+    /* Normal Operation */
+#define F2_CTL_1000T_TEST_MODE_NORMAL       0x0000
+
+    /* Transmit Waveform test */
+#define F2_CTL_1000T_TEST_MODE_1            0x2000
+
+    /* Master Transmit Jitter test */
+#define F2_CTL_1000T_TEST_MODE_2            0x4000
+
+    /* Slave Transmit Jitter test */
+#define F2_CTL_1000T_TEST_MODE_3            0x6000
+
+    /* Transmitter Distortion test */
+#define F2_CTL_1000T_TEST_MODE_4            0x8000
+#define F2_CTL_1000T_SPEED_MASK             0x0300
+#define F2_CTL_1000T_DEFAULT_CAP_MASK       0x0300
+
+    /* 1000BASE-T Status Register offset:10 */
+    /* LP is 1000T HD capable */
+#define F2_STATUS_1000T_LP_HD_CAPS          0x0400
+
+    /* LP is 1000T FD capable */
+#define F2_STATUS_1000T_LP_FD_CAPS          0x0800
+
+    /* Remote receiver OK */
+#define F2_STATUS_1000T_REMOTE_RX_STATUS    0x1000
+
+    /* Local receiver OK */
+#define F2_STATUS_1000T_LOCAL_RX_STATUS     0x2000
+
+    /* 1=Local TX is Master, 0=Slave */
+#define F2_STATUS_1000T_MS_CONFIG_RES       0x4000
+
+#define F2_STATUS_1000T_MS_CONFIG_FAULT     0x8000
+
+    /* Master/Slave config fault */
+#define F2_STATUS_1000T_REMOTE_RX_STATUS_SHIFT   12
+#define F2_STATUS_1000T_LOCAL_RX_STATUS_SHIFT    13
+
+    /* Phy Specific Control Register offset:16*/
+    /* 1=Jabber Function disabled */
+#define F2_CTL_JABBER_DISABLE               0x0001
+
+    /* 1=Polarity Reversal enabled */
+#define F2_CTL_POLARITY_REVERSAL            0x0002
+
+    /* 1=SQE Test enabled */
+#define F2_CTL_SQE_TEST                     0x0004
+#define F2_CTL_MAC_POWERDOWN                0x0008
+
+    /* 1=CLK125 low, 0=CLK125 toggling
+    #define F2_CTL_CLK125_DISABLE               0x0010
+     */
+    /* MDI Crossover Mode bits 6:5 */
+    /* Manual MDI configuration */
+#define F2_CTL_MDI_MANUAL_MODE              0x0000
+
+    /* Manual MDIX configuration */
+#define F2_CTL_MDIX_MANUAL_MODE             0x0020
+
+    /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
+#define F2_CTL_AUTO_X_1000T                 0x0040
+
+    /* Auto crossover enabled all speeds */
+#define F2_CTL_AUTO_X_MODE                  0x0060
+
+    /* 1=Enable Extended 10BASE-T distance
+      * (Lower 10BASE-T RX Threshold)
+     * 0=Normal 10BASE-T RX Threshold */
+#define F2_CTL_10BT_EXT_DIST_ENABLE         0x0080
+
+    /* 1=5-Bit interface in 100BASE-TX
+      * 0=MII interface in 100BASE-TX */
+#define F2_CTL_MII_5BIT_ENABLE              0x0100
+
+    /* 1=Scrambler disable */
+#define F2_CTL_SCRAMBLER_DISABLE            0x0200
+
+    /* 1=Force link good */
+#define F2_CTL_FORCE_LINK_GOOD              0x0400
+
+    /* 1=Assert CRS on Transmit */
+#define F2_CTL_ASSERT_CRS_ON_TX             0x0800
+
+#define F2_CTL_POLARITY_REVERSAL_SHIFT      1
+#define F2_CTL_AUTO_X_MODE_SHIFT            5
+#define F2_CTL_10BT_EXT_DIST_ENABLE_SHIFT   7
+
+    /* Phy Specific status fields offset:17*/
+    /* 1=Speed & Duplex resolved */
+#define F2_STATUS_RESOVLED                  0x0800
+
+    /* 1=Duplex 0=Half Duplex */
+#define F2_STATUS_FULL_DUPLEX               0x2000
+
+    /* Speed, bits 14:15 */
+#define F2_STATUS_SPEED                     0xC000
+#define F2_STATUS_SPEED_MASK                0xC000
+
+    /* 00=10Mbs */
+#define F2_STATUS_SPEED_10MBS              0x0000
+
+    /* 01=100Mbs */
+#define F2_STATUS_SPEED_100MBS             0x4000
+
+    /* 10=1000Mbs */
+#define F2_STATUS_SPEED_1000MBS            0x8000
+#define F2_SPEED_DUPLEX_RESOVLED(phy_status)                   \
+    (((phy_status) &                                  \
+        (F2_STATUS_RESOVLED)) ==                    \
+        (F2_STATUS_RESOVLED))
+
+    /*phy debug port1 register offset:29*/
+    /*phy debug port2 register offset:30*/
+
+    sw_error_t
+    f2_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable);
+
+    sw_error_t
+    f2_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable);
+
+    sw_error_t
+    f2_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable);
+
+    sw_error_t
+    f2_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable);
+
+    sw_error_t
+    f2_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+               fal_cable_status_t *cable_status, a_uint32_t *cable_len) ;
+
+    sw_error_t
+    f2_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+                      fal_port_duplex_t duplex);
+
+    sw_error_t
+    f2_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+                      fal_port_duplex_t * duplex);
+
+    sw_error_t
+    f2_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+                     fal_port_speed_t speed);
+
+    sw_error_t
+    f2_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+                     fal_port_speed_t * speed);
+
+    sw_error_t
+    f2_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id);
+
+    sw_error_t
+    f2_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id);
+
+    sw_error_t
+    f2_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+                           a_uint32_t autoneg);
+
+    sw_error_t
+    f2_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+                           a_uint32_t * autoneg);
+
+    a_bool_t
+    f2_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id);
+
+	int f2_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp);
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _F2_PHY_H_ */
diff --git a/qca-ssdk/include/hsl/phy/hsl_phy.h b/qca-ssdk/include/hsl/phy/hsl_phy.h
new file mode 100755
index 0000000..53926f1
--- /dev/null
+++ b/qca-ssdk/include/hsl/phy/hsl_phy.h
@@ -0,0 +1,729 @@
+/*
+ * Copyright (c) 2015, 2017-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+/*qca808x_start*/
+#ifndef _HSL_PHY_H_
+#define _HSL_PHY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif				/* __cplusplus */
+
+#include "fal.h"
+#include <linux/version.h>
+#include <linux/phy.h>
+
+	/** Phy function reset type */
+	typedef enum {
+		PHY_FIFO_RESET = 0,	/**< Phy fifo reset */
+	} hsl_phy_function_reset_t;
+
+	typedef sw_error_t(*hsl_phy_init) (a_uint32_t dev_id,
+					   a_uint32_t phy_id);
+	typedef sw_error_t(*hsl_phy_hibernation_set) (a_uint32_t dev_id,
+						      a_uint32_t phy_id,
+						      a_bool_t enable);
+	typedef sw_error_t(*hsl_phy_hibernation_get) (a_uint32_t dev_id,
+						      a_uint32_t phy_id,
+						      a_bool_t * enable);
+	typedef sw_error_t(*hsl_phy_speed_get) (a_uint32_t dev_id,
+						a_uint32_t phy_id,
+						fal_port_speed_t * speed);
+	typedef sw_error_t(*hsl_phy_speed_set) (a_uint32_t dev_id,
+						a_uint32_t phy_id,
+						fal_port_speed_t speed);
+	typedef sw_error_t(*hsl_phy_duplex_get) (a_uint32_t dev_id,
+						 a_uint32_t phy_id,
+						 fal_port_duplex_t * duplex);
+	typedef sw_error_t(*hsl_phy_duplex_set) (a_uint32_t dev_id,
+						 a_uint32_t phy_id,
+						 fal_port_duplex_t duplex);
+	typedef sw_error_t(*hsl_phy_autoneg_enable_set) (a_uint32_t dev_id,
+							 a_uint32_t phy_id);
+	typedef sw_error_t(*hsl_phy_autoneg_enable_get) (a_uint32_t dev_id,
+							 a_uint32_t phy_id,
+							 a_bool_t * enable);
+	typedef sw_error_t(*hsl_phy_restart_autoneg) (a_uint32_t dev_id,
+						      a_uint32_t phy_id);
+	typedef a_bool_t(*hsl_phy_autoneg_status_get) (a_uint32_t dev_id,
+							 a_uint32_t phy_id);
+	typedef sw_error_t(*hsl_phy_powersave_set) (a_uint32_t dev_id,
+						    a_uint32_t phy_id,
+						    a_bool_t enable);
+	typedef sw_error_t(*hsl_phy_powersave_get) (a_uint32_t dev_id,
+						    a_uint32_t phy_id,
+						    a_bool_t * enable);
+	typedef sw_error_t(*hsl_phy_cdt) (a_uint32_t dev_id, a_uint32_t phy_id,
+					  a_uint32_t mdi_pair,
+					  fal_cable_status_t * cable_status,
+					  a_uint32_t * cable_len);
+	typedef a_bool_t(*hsl_phy_link_status_get) (a_uint32_t dev_id,
+						      a_uint32_t phy_id);
+	typedef sw_error_t(*hsl_phy_get_ability) (a_uint32_t dev_id,
+						  a_uint32_t phy_id,
+						  a_uint32_t * ability);
+	typedef sw_error_t(*hsl_phy_mdix_set) (a_uint32_t dev_id,
+					       a_uint32_t phy_id,
+					       fal_port_mdix_mode_t mode);
+	typedef sw_error_t(*hsl_phy_mdix_get) (a_uint32_t dev_id,
+					       a_uint32_t phy_id,
+					       fal_port_mdix_mode_t * mode);
+	typedef sw_error_t(*hsl_phy_mdix_status_get) (a_uint32_t dev_id,
+						      a_uint32_t phy_id,
+						      fal_port_mdix_status_t *
+						      mode);
+	typedef sw_error_t(*hsl_phy_8023az_set) (a_uint32_t dev_id,
+						 a_uint32_t phy_id,
+						 a_bool_t enable);
+	typedef sw_error_t(*hsl_phy_8023az_get) (a_uint32_t dev_id,
+						 a_uint32_t phy_id,
+						 a_bool_t * enable);
+	typedef sw_error_t(*hsl_phy_local_loopback_set) (a_uint32_t dev_id,
+							 a_uint32_t phy_id,
+							 a_bool_t enable);
+	typedef sw_error_t(*hsl_phy_local_loopback_get) (a_uint32_t dev_id,
+							 a_uint32_t phy_id,
+							 a_bool_t * enable);
+	typedef sw_error_t(*hsl_phy_remote_loopback_set) (a_uint32_t dev_id,
+							  a_uint32_t phy_id,
+							  a_bool_t enable);
+	typedef sw_error_t(*hsl_phy_remote_loopback_get) (a_uint32_t dev_id,
+							  a_uint32_t phy_id,
+							  a_bool_t * enable);
+	typedef sw_error_t(*hsl_phy_master_set) (a_uint32_t dev_id,
+						 a_uint32_t phy_id,
+						 fal_port_master_t master);
+	typedef sw_error_t(*hsl_phy_master_get) (a_uint32_t dev_id,
+						 a_uint32_t phy_id,
+						 fal_port_master_t * master);
+/*qca808x_end*/
+	typedef sw_error_t(*hsl_phy_combo_prefer_medium_set) (a_uint32_t dev_id,
+							      a_uint32_t phy_id,
+							      fal_port_medium_t
+							      phy_medium);
+	typedef sw_error_t(*hsl_phy_combo_prefer_medium_get) (a_uint32_t dev_id,
+							      a_uint32_t phy_id,
+							      fal_port_medium_t
+							      * phy_medium);
+	typedef sw_error_t(*hsl_phy_combo_medium_status_get) (a_uint32_t dev_id,
+							      a_uint32_t phy_id,
+							      fal_port_medium_t
+							      * phy_medium);
+	typedef sw_error_t(*hsl_phy_combo_fiber_mode_set) (a_uint32_t dev_id,
+							   a_uint32_t phy_id,
+							   fal_port_fiber_mode_t
+							   fiber_mode);
+	typedef sw_error_t(*hsl_phy_combo_fiber_mode_get) (a_uint32_t dev_id,
+							   a_uint32_t phy_id,
+							   fal_port_fiber_mode_t
+							   * fiber_mode);
+	typedef sw_error_t (*hsl_phy_function_reset) (a_uint32_t dev_id,
+							   a_uint32_t phy_id,
+							   hsl_phy_function_reset_t
+							   phy_reset_type);
+/*qca808x_start*/
+	typedef sw_error_t(*hsl_phy_reset) (a_uint32_t dev_id,
+					    a_uint32_t phy_id);
+	typedef sw_error_t(*hsl_phy_reset_status_get) (a_uint32_t dev_id,
+						       a_uint32_t phy_id,
+						       fal_port_reset_status_t *
+						       status);
+	typedef sw_error_t(*hsl_phy_power_off) (a_uint32_t dev_id,
+					    a_uint32_t phy_id);
+	typedef sw_error_t(*hsl_phy_power_on) (a_uint32_t dev_id,
+					    a_uint32_t phy_id);
+	typedef sw_error_t(*hsl_phy_id_get) (a_uint32_t dev_id,
+					     a_uint32_t phy_id,
+					     a_uint32_t *phy_chip_id);
+	typedef sw_error_t(*hsl_phy_autoneg_adv_set) (a_uint32_t dev_id,
+						      a_uint32_t phy_id,
+						      a_uint32_t autoneg);
+	typedef sw_error_t(*hsl_phy_autoneg_adv_get) (a_uint32_t dev_id,
+						      a_uint32_t phy_id,
+						      a_uint32_t * autoneg);
+	typedef sw_error_t(*hsl_phy_reg_write) (a_uint32_t dev_id,
+						a_uint32_t phy_addr,
+						a_uint32_t reg,
+						a_uint16_t reg_val);
+	typedef a_uint16_t(*hsl_phy_reg_read) (a_uint32_t dev_id,
+					       a_uint32_t phy_addr,
+					       a_uint32_t reg);
+	typedef sw_error_t(*hsl_phy_debug_write) (a_uint32_t dev_id,
+						  a_uint32_t phy_id,
+						  a_uint16_t reg_id,
+						  a_uint16_t reg_val);
+	typedef a_uint16_t(*hsl_phy_debug_read) (a_uint32_t dev_id,
+						 a_uint32_t phy_id,
+						 a_uint16_t reg_id);
+	typedef sw_error_t(*hsl_phy_mmd_write) (a_uint32_t dev_id,
+						a_uint32_t phy_id,
+						a_uint16_t mmd_num,
+						a_uint16_t reg_id,
+						a_uint16_t reg_val);
+	typedef a_uint16_t(*hsl_phy_mmd_read) (a_uint32_t dev_id,
+					       a_uint32_t phy_id,
+					       a_uint16_t mmd_num,
+					       a_uint16_t reg_id);
+
+	typedef sw_error_t(*hsl_phy_magic_frame_mac_set) (a_uint32_t dev_id,
+							  a_uint32_t phy_id,
+							  fal_mac_addr_t * mac);
+
+	typedef sw_error_t(*hsl_phy_magic_frame_mac_get) (a_uint32_t dev_id,
+							  a_uint32_t phy_id,
+							  fal_mac_addr_t * mac);
+	typedef sw_error_t(*hsl_phy_wol_status_set) (a_uint32_t dev_id,
+							 a_uint32_t phy_id,
+							 a_bool_t enable);
+	typedef sw_error_t(*hsl_phy_wol_status_get) (a_uint32_t dev_id,
+							 a_uint32_t phy_id,
+							 a_bool_t * enable);
+	typedef sw_error_t(*hsl_phy_interface_mode_set) (a_uint32_t dev_id,
+							 a_uint32_t phy_id,
+							 fal_port_interface_mode_t
+							 interface_mode);
+	typedef sw_error_t(*hsl_phy_interface_mode_get) (a_uint32_t dev_id,
+							 a_uint32_t phy_id,
+							 fal_port_interface_mode_t
+							 * interface_mode);
+	typedef sw_error_t(*hsl_phy_interface_mode_status_get) (a_uint32_t dev_id,
+							 a_uint32_t phy_id,
+							 fal_port_interface_mode_t
+							 * interface_mode);
+	typedef sw_error_t(*hsl_phy_intr_mask_set) (a_uint32_t dev_id,
+						      a_uint32_t phy_id,
+						      a_uint32_t mask);
+	typedef sw_error_t(*hsl_phy_intr_mask_get) (a_uint32_t dev_id,
+						      a_uint32_t phy_id,
+						      a_uint32_t * mask);
+	typedef sw_error_t(*hsl_phy_intr_status_get) (a_uint32_t dev_id,
+						      a_uint32_t phy_id,
+						      a_uint32_t * status);
+	typedef sw_error_t(*hsl_phy_counter_set) (a_uint32_t dev_id,
+						      a_uint32_t phy_id,
+						      a_bool_t enable);
+	typedef sw_error_t(*hsl_phy_counter_get) (a_uint32_t dev_id,
+						      a_uint32_t phy_id,
+						      a_bool_t * enable);
+	typedef sw_error_t(*hsl_phy_counter_show) (a_uint32_t dev_id,
+						      a_uint32_t phy_id,
+						      fal_port_counter_info_t * counter_info);
+	typedef sw_error_t(*hsl_phy_serdes_reset) (a_uint32_t dev_id);
+
+	typedef sw_error_t(*hsl_phy_get_status) (a_uint32_t dev_id,
+				a_uint32_t phy_id, struct port_phy_status *phy_status);
+
+	typedef sw_error_t(*hsl_phy_eee_adv_set) (a_uint32_t dev_id,
+					      a_uint32_t phy_id,
+					      a_uint32_t adv);
+	typedef sw_error_t(*hsl_phy_eee_adv_get) (a_uint32_t dev_id,
+					      a_uint32_t phy_id,
+					      a_uint32_t * adv);
+	typedef sw_error_t(*hsl_phy_eee_partner_adv_get) (a_uint32_t dev_id,
+					      a_uint32_t phy_id,
+					      a_uint32_t * adv);
+	typedef sw_error_t(*hsl_phy_eee_cap_get) (a_uint32_t dev_id,
+					      a_uint32_t phy_id,
+					      a_uint32_t * cap);
+	typedef sw_error_t(*hsl_phy_eee_status_get) (a_uint32_t dev_id,
+					      a_uint32_t phy_id,
+					      a_uint32_t * status);
+/*qca808x_end*/
+	typedef sw_error_t(*hsl_phy_led_ctrl_pattern_set) (a_uint32_t dev_id,
+					      a_uint32_t phy_id,
+					      led_ctrl_pattern_t * pattern);
+	typedef sw_error_t(*hsl_phy_led_ctrl_pattern_get) (a_uint32_t dev_id,
+					      a_uint32_t phy_id,
+					      led_ctrl_pattern_t * pattern);
+	typedef sw_error_t(*hsl_phy_led_ctrl_source_set) (a_uint32_t dev_id,
+					      a_uint32_t phy_id,
+					      a_uint32_t source_id,
+					      led_ctrl_pattern_t * pattern);
+	typedef sw_error_t(*hsl_phy_ptp_security_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_security_t *sec);
+
+	typedef sw_error_t(*hsl_phy_ptp_link_delay_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_time_t *time);
+
+	typedef sw_error_t(*hsl_phy_ptp_rx_crc_recalc_status_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, a_bool_t *status);
+
+	typedef sw_error_t(*hsl_phy_ptp_tod_uart_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_tod_uart_t *tod_uart);
+
+	typedef sw_error_t(*hsl_phy_ptp_enhanced_timestamp_engine_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_direction_t direction,
+				fal_ptp_enhanced_ts_engine_t *ts_engine);
+
+	typedef sw_error_t(*hsl_phy_ptp_pps_signal_control_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_pps_signal_control_t *sig_control);
+
+	typedef sw_error_t(*hsl_phy_ptp_timestamp_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_direction_t direction,
+				fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time);
+
+	typedef sw_error_t(*hsl_phy_ptp_asym_correction_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_asym_correction_t* asym_cf);
+
+	typedef sw_error_t(*hsl_phy_ptp_rtc_time_snapshot_status_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, a_bool_t *status);
+
+	typedef sw_error_t(*hsl_phy_ptp_capture_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, a_uint32_t capture_id,
+				fal_ptp_capture_t *capture);
+
+	typedef sw_error_t(*hsl_phy_ptp_rtc_adjfreq_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_time_t *time);
+
+	typedef sw_error_t(*hsl_phy_ptp_asym_correction_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_asym_correction_t *asym_cf);
+
+	typedef sw_error_t(*hsl_phy_ptp_pkt_timestamp_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_time_t *time);
+
+	typedef sw_error_t(*hsl_phy_ptp_rtc_time_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_time_t *time);
+
+	typedef sw_error_t(*hsl_phy_ptp_rtc_time_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_time_t *time);
+
+	typedef sw_error_t(*hsl_phy_ptp_pkt_timestamp_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_time_t *time);
+
+	typedef sw_error_t(*hsl_phy_ptp_interrupt_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_interrupt_t *interrupt);
+
+	typedef sw_error_t(*hsl_phy_ptp_trigger_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, a_uint32_t trigger_id,
+				fal_ptp_trigger_t *triger);
+
+	typedef sw_error_t(*hsl_phy_ptp_pps_signal_control_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id,
+				fal_ptp_pps_signal_control_t *sig_control);
+
+	typedef sw_error_t(*hsl_phy_ptp_capture_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, a_uint32_t capture_id,
+				fal_ptp_capture_t *capture);
+
+	typedef sw_error_t(*hsl_phy_ptp_rx_crc_recalc_enable) (a_uint32_t dev_id,
+				a_uint32_t phy_id, a_bool_t status);
+
+	typedef sw_error_t(*hsl_phy_ptp_security_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_security_t *sec);
+
+	typedef sw_error_t(*hsl_phy_ptp_increment_sync_from_clock_status_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, a_bool_t *status);
+
+	typedef sw_error_t(*hsl_phy_ptp_tod_uart_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_tod_uart_t *tod_uart);
+
+	typedef sw_error_t(*hsl_phy_ptp_enhanced_timestamp_engine_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_direction_t direction,
+				fal_ptp_enhanced_ts_engine_t *ts_engine);
+
+	typedef sw_error_t(*hsl_phy_ptp_rtc_time_clear) (a_uint32_t dev_id,
+				a_uint32_t phy_id);
+
+	typedef sw_error_t(*hsl_phy_ptp_reference_clock_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_reference_clock_t ref_clock);
+
+	typedef sw_error_t(*hsl_phy_ptp_output_waveform_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_output_waveform_t *waveform);
+
+	typedef sw_error_t(*hsl_phy_ptp_rx_timestamp_mode_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_rx_timestamp_mode_t ts_mode);
+
+	typedef sw_error_t(*hsl_phy_ptp_grandmaster_mode_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_grandmaster_mode_t *gm_mode);
+
+	typedef sw_error_t(*hsl_phy_ptp_config_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_config_t *config);
+
+	typedef sw_error_t(*hsl_phy_ptp_trigger_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, a_uint32_t trigger_id,
+				fal_ptp_trigger_t *triger);
+
+	typedef sw_error_t(*hsl_phy_ptp_rtc_adjfreq_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_time_t *time);
+
+	typedef sw_error_t(*hsl_phy_ptp_grandmaster_mode_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_grandmaster_mode_t *gm_mode);
+
+	typedef sw_error_t(*hsl_phy_ptp_rx_timestamp_mode_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_rx_timestamp_mode_t *ts_mode);
+
+	typedef sw_error_t(*hsl_phy_ptp_rtc_adjtime_set) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_time_t *time);
+
+	typedef sw_error_t(*hsl_phy_ptp_link_delay_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_time_t *time);
+
+	typedef sw_error_t(*hsl_phy_ptp_increment_sync_from_clock_enable) (a_uint32_t dev_id,
+				a_uint32_t phy_id, a_bool_t status);
+
+	typedef sw_error_t(*hsl_phy_ptp_config_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_config_t *config);
+
+	typedef sw_error_t(*hsl_phy_ptp_output_waveform_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_output_waveform_t *waveform);
+
+	typedef sw_error_t(*hsl_phy_ptp_interrupt_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_interrupt_t *interrupt);
+
+	typedef sw_error_t(*hsl_phy_ptp_rtc_time_snapshot_enable) (a_uint32_t dev_id,
+				a_uint32_t phy_id, a_bool_t status);
+
+	typedef sw_error_t(*hsl_phy_ptp_reference_clock_get) (a_uint32_t dev_id,
+				a_uint32_t phy_id, fal_ptp_reference_clock_t *ref_clock);
+
+	typedef struct hsl_phy_ptp_ops_s {
+		hsl_phy_ptp_security_set phy_ptp_security_set;
+		hsl_phy_ptp_link_delay_set phy_ptp_link_delay_set;
+		hsl_phy_ptp_rx_crc_recalc_status_get phy_ptp_rx_crc_recalc_status_get;
+		hsl_phy_ptp_tod_uart_set phy_ptp_tod_uart_set;
+		hsl_phy_ptp_enhanced_timestamp_engine_get phy_ptp_enhanced_timestamp_engine_get;
+		hsl_phy_ptp_pps_signal_control_set phy_ptp_pps_signal_control_set;
+		hsl_phy_ptp_timestamp_get phy_ptp_timestamp_get;
+		hsl_phy_ptp_asym_correction_get phy_ptp_asym_correction_get;
+		hsl_phy_ptp_rtc_time_snapshot_status_get phy_ptp_rtc_time_snapshot_status_get;
+		hsl_phy_ptp_capture_set phy_ptp_capture_set;
+		hsl_phy_ptp_rtc_adjfreq_set phy_ptp_rtc_adjfreq_set;
+		hsl_phy_ptp_asym_correction_set phy_ptp_asym_correction_set;
+		hsl_phy_ptp_pkt_timestamp_set phy_ptp_pkt_timestamp_set;
+		hsl_phy_ptp_rtc_time_get phy_ptp_rtc_time_get;
+		hsl_phy_ptp_rtc_time_set phy_ptp_rtc_time_set;
+		hsl_phy_ptp_pkt_timestamp_get phy_ptp_pkt_timestamp_get;
+		hsl_phy_ptp_interrupt_set phy_ptp_interrupt_set;
+		hsl_phy_ptp_trigger_set phy_ptp_trigger_set;
+		hsl_phy_ptp_pps_signal_control_get phy_ptp_pps_signal_control_get;
+		hsl_phy_ptp_capture_get phy_ptp_capture_get;
+		hsl_phy_ptp_rx_crc_recalc_enable phy_ptp_rx_crc_recalc_enable;
+		hsl_phy_ptp_security_get phy_ptp_security_get;
+		hsl_phy_ptp_increment_sync_from_clock_status_get \
+			phy_ptp_increment_sync_from_clock_status_get;
+		hsl_phy_ptp_tod_uart_get phy_ptp_tod_uart_get;
+		hsl_phy_ptp_enhanced_timestamp_engine_set phy_ptp_enhanced_timestamp_engine_set;
+		hsl_phy_ptp_rtc_time_clear phy_ptp_rtc_time_clear;
+		hsl_phy_ptp_reference_clock_set phy_ptp_reference_clock_set;
+		hsl_phy_ptp_output_waveform_set phy_ptp_output_waveform_set;
+		hsl_phy_ptp_rx_timestamp_mode_set phy_ptp_rx_timestamp_mode_set;
+		hsl_phy_ptp_grandmaster_mode_set phy_ptp_grandmaster_mode_set;
+		hsl_phy_ptp_config_set phy_ptp_config_set;
+		hsl_phy_ptp_trigger_get phy_ptp_trigger_get;
+		hsl_phy_ptp_rtc_adjfreq_get phy_ptp_rtc_adjfreq_get;
+		hsl_phy_ptp_grandmaster_mode_get phy_ptp_grandmaster_mode_get;
+		hsl_phy_ptp_rx_timestamp_mode_get phy_ptp_rx_timestamp_mode_get;
+		hsl_phy_ptp_rtc_adjtime_set phy_ptp_rtc_adjtime_set;
+		hsl_phy_ptp_link_delay_get phy_ptp_link_delay_get;
+		hsl_phy_ptp_increment_sync_from_clock_enable \
+			phy_ptp_increment_sync_from_clock_enable;
+		hsl_phy_ptp_config_get phy_ptp_config_get;
+		hsl_phy_ptp_output_waveform_get phy_ptp_output_waveform_get;
+		hsl_phy_ptp_interrupt_get phy_ptp_interrupt_get;
+		hsl_phy_ptp_rtc_time_snapshot_enable phy_ptp_rtc_time_snapshot_enable;
+		hsl_phy_ptp_reference_clock_get phy_ptp_reference_clock_get;
+	} hsl_phy_ptp_ops_t;
+
+/*qca808x_start*/
+	typedef struct hsl_phy_ops_s {
+
+		hsl_phy_init phy_init;
+		hsl_phy_hibernation_set phy_hibernation_set;
+		hsl_phy_hibernation_get phy_hibernation_get;
+		hsl_phy_speed_get phy_speed_get;
+		hsl_phy_speed_set phy_speed_set;
+		hsl_phy_duplex_get phy_duplex_get;
+		hsl_phy_duplex_set phy_duplex_set;
+		hsl_phy_autoneg_enable_set phy_autoneg_enable_set;
+		hsl_phy_autoneg_enable_get phy_autoneg_enable_get;
+		hsl_phy_restart_autoneg phy_restart_autoneg;
+		hsl_phy_autoneg_status_get phy_autoneg_status_get;
+		hsl_phy_autoneg_adv_set phy_autoneg_adv_set;
+		hsl_phy_autoneg_adv_get phy_autoneg_adv_get;
+		hsl_phy_powersave_set phy_powersave_set;
+		hsl_phy_powersave_get phy_powersave_get;
+		hsl_phy_cdt phy_cdt;
+		hsl_phy_link_status_get phy_link_status_get;
+		hsl_phy_get_ability phy_get_ability;
+		hsl_phy_mdix_set phy_mdix_set;
+		hsl_phy_mdix_get phy_mdix_get;
+		hsl_phy_mdix_status_get phy_mdix_status_get;
+		hsl_phy_8023az_set phy_8023az_set;
+		hsl_phy_8023az_get phy_8023az_get;
+		hsl_phy_local_loopback_set phy_local_loopback_set;
+		hsl_phy_local_loopback_get phy_local_loopback_get;
+		hsl_phy_remote_loopback_set phy_remote_loopback_set;
+		hsl_phy_remote_loopback_get phy_remote_loopback_get;
+		hsl_phy_master_set phy_master_set;
+		hsl_phy_master_get phy_master_get;
+/*qca808x_end*/
+		hsl_phy_combo_prefer_medium_set phy_combo_prefer_medium_set;
+		hsl_phy_combo_prefer_medium_get phy_combo_prefer_medium_get;
+		hsl_phy_combo_medium_status_get phy_combo_medium_status_get;
+		hsl_phy_combo_fiber_mode_set phy_combo_fiber_mode_set;
+		hsl_phy_combo_fiber_mode_get phy_combo_fiber_mode_get;
+		hsl_phy_function_reset phy_function_reset;
+/*qca808x_start*/
+		hsl_phy_reset phy_reset;
+		hsl_phy_power_off phy_power_off;
+		hsl_phy_power_on phy_power_on;
+		hsl_phy_reset_status_get phy_reset_status_get;
+		hsl_phy_id_get phy_id_get;
+		hsl_phy_reg_write phy_reg_write;
+		hsl_phy_reg_read phy_reg_read;
+		hsl_phy_debug_write phy_debug_write;
+		hsl_phy_debug_read phy_debug_read;
+		hsl_phy_mmd_write phy_mmd_write;
+		hsl_phy_mmd_read phy_mmd_read;
+		hsl_phy_magic_frame_mac_set phy_magic_frame_mac_set;
+		hsl_phy_magic_frame_mac_get phy_magic_frame_mac_get;
+		hsl_phy_wol_status_set phy_wol_status_set;
+		hsl_phy_wol_status_get phy_wol_status_get;
+		hsl_phy_interface_mode_set phy_interface_mode_set;
+		hsl_phy_interface_mode_get phy_interface_mode_get;
+		hsl_phy_interface_mode_status_get phy_interface_mode_status_get;
+		hsl_phy_intr_mask_set  phy_intr_mask_set;
+		hsl_phy_intr_mask_get  phy_intr_mask_get;
+		hsl_phy_intr_status_get  phy_intr_status_get;
+		hsl_phy_counter_set  phy_counter_set;
+		hsl_phy_counter_get  phy_counter_get;
+		hsl_phy_counter_show  phy_counter_show;
+		hsl_phy_serdes_reset phy_serdes_reset;
+		hsl_phy_get_status phy_get_status;
+		hsl_phy_eee_adv_set phy_eee_adv_set;
+		hsl_phy_eee_adv_get phy_eee_adv_get;
+		hsl_phy_eee_partner_adv_get phy_eee_partner_adv_get;
+		hsl_phy_eee_cap_get phy_eee_cap_get;
+		hsl_phy_eee_status_get phy_eee_status_get;
+/*qca808x_end*/
+		hsl_phy_led_ctrl_pattern_set phy_led_ctrl_pattern_set;
+		hsl_phy_led_ctrl_pattern_get phy_led_ctrl_pattern_get;
+		hsl_phy_led_ctrl_source_set phy_led_ctrl_source_set;
+		hsl_phy_ptp_ops_t phy_ptp_ops;
+/*qca808x_start*/
+	} hsl_phy_ops_t;
+
+typedef struct phy_driver_instance {
+	a_uint32_t phy_type;
+	a_uint32_t port_bmp[SW_MAX_NR_DEV];
+	hsl_phy_ops_t *phy_ops;
+	int (*init)(a_uint32_t dev_id, a_uint32_t portbmp);
+	void (*exit)(a_uint32_t dev_id, a_uint32_t portbmp);
+} phy_driver_instance_t;
+
+typedef enum
+{
+/*qca808x_end*/
+	F1_PHY_CHIP = 0,
+	F2_PHY_CHIP,
+	MALIBU_PHY_CHIP,
+	AQUANTIA_PHY_CHIP,
+	QCA803X_PHY_CHIP,
+	SFP_PHY_CHIP,
+	MPGE_PHY_CHIP,
+/*qca808x_start*/
+	QCA808X_PHY_CHIP,
+	MAX_PHY_CHIP,
+} phy_type_t;
+
+#define PHY_INVALID_DAC        0
+
+typedef struct {
+	a_uint8_t mdac;
+	a_uint8_t edac;
+} phy_dac_t;
+
+typedef struct {
+	a_uint32_t phy_address[SW_MAX_NR_PORT];
+	a_uint32_t phy_type[SW_MAX_NR_PORT];
+	/* fake mdio address is used to register the phy device,
+	 * when the phy is not accessed by the MDIO bus.
+	 * */
+	a_uint32_t phy_mdio_fake_address[SW_MAX_NR_PORT];
+	a_uint8_t phy_access_type[SW_MAX_NR_PORT];
+	a_bool_t phy_c45[SW_MAX_NR_PORT];
+	a_bool_t phy_combo[SW_MAX_NR_PORT];
+	a_uint32_t phy_reset_gpio[SW_MAX_NR_PORT];
+	phy_dac_t phy_dac[SW_MAX_NR_PORT];
+} phy_info_t;
+/*qca808x_end*/
+#define MALIBU5PORT_PHY         0x004DD0B1
+#define MALIBU2PORT_PHY         0x004DD0B2
+#define QCA8030_PHY             0x004DD076
+#define QCA8033_PHY             0x004DD074
+#define QCA8035_PHY             0x004DD072
+/*qca808x_start*/
+#define QCA8081_PHY_V1_1        0x004DD101
+#define INVALID_PHY_ID          0xFFFFFFFF
+
+/*qca808x_end*/
+#define F1V1_PHY                0x004DD033
+#define F1V2_PHY                0x004DD034
+#define F1V3_PHY                0x004DD035
+#define F1V4_PHY                0x004DD036
+#define F2V1_PHY                0x004DD042
+#define AQUANTIA_PHY_107        0x03a1b4e2
+#define AQUANTIA_PHY_108        0x03a1b4f2
+#define AQUANTIA_PHY_109        0x03a1b502
+#define AQUANTIA_PHY_111        0x03a1b610
+#define AQUANTIA_PHY_111B0      0x03a1b612
+#define AQUANTIA_PHY_112        0x03a1b660
+#define AQUANTIA_PHY_113C_A0    0x31c31C10
+#define AQUANTIA_PHY_113C_A1    0x31c31C11
+#define AQUANTIA_PHY_112C       0x03a1b792
+
+#define PHY_805XV2              0x004DD082
+#define PHY_805XV1              0x004DD081
+/*qca808x_start*/
+#define SFP_PHY                 0xaaaabbbb
+/*qca808x_end*/
+#define MP_GEPHY                0x004DD0C0
+#define SFP_PHY_MASK            0xffffffff
+
+#define CABLE_PAIR_A            0
+#define CABLE_PAIR_B            1
+#define CABLE_PAIR_C            2
+#define CABLE_PAIR_D            3
+/*qca808x_start*/
+#define PHY_MDIO_ACCESS         0
+#define PHY_I2C_ACCESS          1
+
+#define INVALID_PHY_ADDR        0xff
+#define MAX_PHY_ADDR            0x1f
+#define QCA8072_PHY_NUM         0x2
+
+#define PHY_INVALID_DATA 0xffff
+
+#define PHY_RTN_ON_READ_ERROR(phy_data) \
+    do { if (phy_data == PHY_INVALID_DATA) return(SW_READ_ERROR); } while(0);
+
+#define PHY_RTN_ON_ERROR(rv) \
+    do { if (rv != SW_OK) return(rv); } while(0);
+
+sw_error_t
+hsl_phy_api_ops_register(phy_type_t phy_type, hsl_phy_ops_t * phy_api_ops);
+
+sw_error_t
+hsl_phy_api_ops_unregister(phy_type_t phy_type, hsl_phy_ops_t * phy_api_ops);
+
+hsl_phy_ops_t *hsl_phy_api_ops_get(a_uint32_t dev_id, a_uint32_t port_id);
+
+sw_error_t phy_api_ops_init(phy_type_t phy_type);
+
+int ssdk_phy_driver_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+int qca_ssdk_phy_info_init(a_uint32_t dev_id);
+
+void qca_ssdk_port_bmp_init(a_uint32_t dev_id);
+/*qca808x_end*/
+void hsl_phy_address_init(a_uint32_t dev_id, a_uint32_t i,
+				a_uint32_t value);
+/*qca808x_start*/
+a_uint32_t
+hsl_phyid_get(a_uint32_t dev_id, a_uint32_t port_id, ssdk_init_cfg *cfg);
+
+a_uint32_t
+qca_ssdk_port_to_phy_addr(a_uint32_t dev_id, a_uint32_t port_id);
+/*qca808x_end*/
+a_uint32_t
+qca_ssdk_port_to_phy_mdio_fake_addr(a_uint32_t dev_id, a_uint32_t port_id);
+
+a_uint32_t
+qca_ssdk_phy_mdio_fake_addr_to_port(a_uint32_t dev_id, a_uint32_t phy_addr);
+
+void qca_ssdk_phy_mdio_fake_address_set(a_uint32_t dev_id, a_uint32_t i,
+				a_uint32_t value);
+/*qca808x_start*/
+void qca_ssdk_port_bmp_set(a_uint32_t dev_id, a_uint32_t value);
+
+a_uint32_t qca_ssdk_port_bmp_get(a_uint32_t dev_id);
+/*qca808x_end*/
+a_uint32_t qca_ssdk_phy_type_port_bmp_get(a_uint32_t dev_id,
+				phy_type_t phy_type);
+/*qca808x_start*/
+a_uint32_t
+qca_ssdk_phy_addr_to_port(a_uint32_t dev_id, a_uint32_t phy_addr);
+/*qca808x_end*/
+void
+hsl_port_phy_c45_capability_set(a_uint32_t dev_id, a_uint32_t port_id,
+			a_bool_t enable);
+
+a_bool_t
+hsl_port_phy_combo_capability_get(a_uint32_t dev_id, a_uint32_t port_id);
+
+void
+hsl_port_phy_combo_capability_set(a_uint32_t dev_id, a_uint32_t port_id,
+		a_bool_t enable);
+/*qca808x_start*/
+a_uint8_t
+hsl_port_phy_access_type_get(a_uint32_t dev_id, a_uint32_t port_id);
+
+void
+hsl_port_phy_access_type_set(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint8_t access_type);
+/*qca808x_end*/
+sw_error_t
+hsl_port_phy_serdes_reset(a_uint32_t dev_id);
+
+sw_error_t
+hsl_port_phy_mode_set(a_uint32_t dev_id, fal_port_interface_mode_t mode);
+phy_type_t hsl_phy_type_get(a_uint32_t dev_id, a_uint32_t port_id);
+
+a_uint32_t
+hsl_port_phyid_get(a_uint32_t dev_id, fal_port_t port_id);
+
+a_uint32_t hsl_port_phy_reset_gpio_get(a_uint32_t dev_id, a_uint32_t port_id);
+
+void hsl_port_phy_reset_gpio_set(a_uint32_t dev_id, a_uint32_t port_id,
+	a_uint32_t phy_reset_gpio);
+
+void hsl_port_phy_gpio_reset(a_uint32_t dev_id, a_uint32_t port_id);
+
+void
+hsl_port_phy_dac_get(a_uint32_t dev_id, a_uint32_t port_id,
+	phy_dac_t *phy_dac);
+
+void
+hsl_port_phy_dac_set(a_uint32_t dev_id, a_uint32_t port_id,
+	phy_dac_t phy_dac);
+
+a_bool_t hsl_port_is_sfp(a_uint32_t dev_id, a_uint32_t port_id);
+/*qca808x_start*/
+sw_error_t ssdk_phy_driver_cleanup(void);
+/*qca808x_end*/
+sw_error_t
+hsl_phydriver_update(a_uint32_t dev_id, a_uint32_t port_id,
+	a_uint32_t mode);
+
+void
+qca_ssdk_phy_address_set(a_uint32_t dev_id, a_uint32_t port_id,
+	a_uint32_t phy_addr);
+
+sw_error_t
+hsl_port_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_id);
+
+sw_error_t
+hsl_port_phydev_get(a_uint32_t dev_id, a_uint32_t port_id,
+	struct phy_device **phydev);
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0))
+sw_error_t
+hsl_port_phydev_adv_update(a_uint32_t dev_id, a_uint32_t port_id,
+	a_uint32_t autoadv);
+#endif
+/*qca808x_start*/
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* _HSL_PHY_H_ */
+/*qca808x_end*/
diff --git a/qca-ssdk/include/hsl/phy/malibu_phy.h b/qca-ssdk/include/hsl/phy/malibu_phy.h
new file mode 100755
index 0000000..b735404
--- /dev/null
+++ b/qca-ssdk/include/hsl/phy/malibu_phy.h
@@ -0,0 +1,676 @@
+/*
+ * Copyright (c) 2015, 2017, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _MALIBU_PHY_H_
+#define _MALIBU_PHY_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif				/* __cplusplus */
+
+#define BIT_15                   15
+#define BIT_14                   14
+#define BIT_13                   13
+#define BIT_12                   12
+#define BIT_11                   11
+#define BIT_10                   10
+#define BIT_9                    9
+#define BIT_8                    8
+#define BIT_7                    7
+#define BIT_6                    6
+#define BIT_5                    5
+#define BIT_4                    4
+#define BIT_3                    3
+#define BIT_2                    2
+#define BIT_1                    1
+#define BIT_0                    0
+#define COMBO_PHY_ID 4
+#define PSGMII_ID 5
+
+#define MALIBU_COMMON_CTRL  0x1040
+#define MALIBU_10M_LOOPBACK  0x4100
+#define MALIBU_100M_LOOPBACK  0x6100
+#define MALIBU_1000M_LOOPBACK  0x4140
+
+#define MALIBU_1_0 0x004DD0B0
+#define MALIBU_1_1 0x004DD0B1
+#define MALIBU_1_1_2PORT 0x004DD0B2
+#define MALIBU_ORG_ID_OFFSET_LEN 16
+#define MALIBU_PHY_COPPER_MODE 0x8000
+
+  /* PHY Registers */
+#define MALIBU_PHY_CONTROL                      0
+#define MALIBU_PHY_STATUS                       1
+#define MALIBU_PHY_ID1                          2
+#define MALIBU_PHY_ID2                          3
+#define MALIBU_AUTONEG_ADVERT                   4
+#define MALIBU_LINK_PARTNER_ABILITY             5
+#define MALIBU_AUTONEG_EXPANSION                6
+#define MALIBU_NEXT_PAGE_TRANSMIT               7
+#define MALIBU_LINK_PARTNER_NEXT_PAGE           8
+#define MALIBU_1000BASET_CONTROL                9
+#define MALIBU_1000BASET_STATUS                 10
+#define MALIBU_MMD_CTRL_REG                     13
+#define MALIBU_MMD_DATA_REG                     14
+#define MALIBU_EXTENDED_STATUS                  15
+#define MALIBU_PHY_SPEC_CONTROL                 16
+#define MALIBU_PHY_SPEC_STATUS                  17
+#define MALIBU_PHY_INTR_MASK                    18
+#define MALIBU_PHY_INTR_STATUS                  19
+#define MALIBU_PHY_CDT_CONTROL                  22
+#define MALIBU_PHY_CDT_STATUS                   28
+#define MALIBU_DEBUG_PORT_ADDRESS               29
+#define MALIBU_DEBUG_PORT_DATA                  30
+
+#define MALIBU_DEBUG_PHY_HIBERNATION_CTRL  0xb
+#define MALIBU_DEBUG_PHY_POWER_SAVING_CTRL  0x29
+#define MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL       0x3c
+#define MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_PARTNER       0x3d
+#define MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_STATUS       0x8000
+#define MALIBU_PHY_MMD3_ADDR_8023AZ_EEE_CAPABILITY       0x14
+
+#define MALIBU_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL       0x805a
+#define MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL1   0x804a
+#define MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL2   0x804b
+#define MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL3   0x804c
+#define MALIBU_PHY_MMD3_WOL_CTRL  0x8012
+#define MALIBU_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL       0x804e
+#define MALIBU_PHY_MMD3_ADDR_8023AZ_CLD_CTRL       0x8007
+#define MALIBU_PHY_MMD3_ADDR_CLD_CTRL5       0x8005
+#define MALIBU_PHY_MMD3_ADDR_CLD_CTRL3       0x8003
+#define MALIBU_PHY_MMD7_DAC_CTRL  0x801a
+#define MALIBU_DAC_CTRL_MASK  0x380
+#define MALIBU_DAC_CTRL_VALUE  0x280
+#define MALIBU_LED_1000_CTRL1_100_10_MASK  0x30
+
+#define MALIBU_PHY_EEE_ADV_100M 0x0002
+#define MALIBU_PHY_EEE_ADV_1000M 0x0004
+#define MALIBU_PHY_EEE_PARTNER_ADV_100M 0x0002
+#define MALIBU_PHY_EEE_PARTNER_ADV_1000M 0x0004
+#define MALIBU_PHY_EEE_CAPABILITY_100M 0x0002
+#define MALIBU_PHY_EEE_CAPABILITY_1000M 0x0004
+#define MALIBU_PHY_EEE_STATUS_100M 0x0002
+#define MALIBU_PHY_EEE_STATUS_1000M 0x0004
+
+
+#define AZ_TIMER_CTRL_DEFAULT_VALUE    0x3062
+#define AZ_CLD_CTRL_DEFAULT_VALUE     0x83f6
+#define AZ_TIMER_CTRL_ADJUST_VALUE    0x7062
+#define AZ_CLD_CTRL_ADJUST_VALUE     0x8396
+
+
+#define MALIBU_PHY_MMD7_COUNTER_CTRL       0x8029
+#define MALIBU_PHY_MMD7_INGRESS_COUNTER_HIGH       0x802a
+#define MALIBU_PHY_MMD7_INGRESS_COUNTER_LOW       0x802b
+#define MALIBU_PHY_MMD7_INGRESS_ERROR_COUNTER       0x802c
+#define MALIBU_PHY_MMD7_EGRESS_COUNTER_HIGH       0x802d
+#define MALIBU_PHY_MMD7_EGRESS_COUNTER_LOW       0x802e
+#define MALIBU_PHY_MMD7_EGRESS_ERROR_COUNTER       0x802f
+#define MALIBU_PHY_MMD7_LED_1000_CTRL1       0x8076
+
+
+
+#define MALIBU_PSGMII_FIFI_CTRL  0x6e
+#define MALIBU_PSGMII_CALIB_CTRL  0x27
+#define MALIBU_PSGMII_MODE_CTRL  0x6d
+#define MALIBU_PSGMII_TX_DRIVER_1_CTRL 0xb
+
+#define MALIBU_PHY_PSGMII_MODE_CTRL_DEFAULT_VALUE       0x220d
+#define MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE        0x220c
+#define MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP	0x8a
+
+#define MALIBU_PHY_QSGMII 0x8504
+#define MALIBU_PHY_PSGMII_ADDR_INC 0x5
+#define MALIBU_PHY_MAX_ADDR_INC 0x4
+#define MALIBU_MODE_CHANAGE_RESET 0x0
+#define MALIBU_MODE_RESET_DEFAULT_VALUE 0x5f
+#define MALIBU_MODE_RESET_REG 0x0
+
+#define MALIBU_PHY_TX_FLOWCTRL_STATUS 0x8
+#define MALIBU_PHY_RX_FLOWCTRL_STATUS 0x4
+
+
+#define MALIBU_PHY_MMD7_NUM  7
+#define MALIBU_PHY_MMD3_NUM  3
+#define MALIBU_PHY_MMD1_NUM  1
+
+#define MALIBU_PHY_SGMII_STATUS            0x1a	/* sgmii_status  Register  */
+#define MALIBU_PHY4_AUTO_SGMII_SELECT   0x40
+#define MALIBU_PHY4_AUTO_COPPER_SELECT       0x20
+#define MALIBU_PHY4_AUTO_BX1000_SELECT     0x10
+#define MALIBU_PHY4_AUTO_FX100_SELECT   0x8
+
+#define MALIBU_PHY_CHIP_CONFIG          0x1f	/* Chip Configuration Register  */
+#define BT_BX_SG_REG_SELECT          BIT_15
+#define BT_BX_SG_REG_SELECT_OFFSET   15
+#define BT_BX_SG_REG_SELECT_LEN      1
+#define MALIBU_SG_BX_PAGES                  0x0
+#define MALIBU_SG_COPPER_PAGES              0x1
+
+#define MALIBU_PHY_PSGMII_BASET              0x0
+#define MALIBU_PHY_PSGMII_BX1000              0x1
+#define MALIBU_PHY_PSGMII_FX100              0x2
+#define MALIBU_PHY_PSGMII_AMDET              0x3
+#define MALIBU_PHY_SGMII_BASET              0x4
+
+#define MALIBU_PHY4_PREFER_FIBER  0x400
+#define PHY4_PREFER_COPPER                0x0
+#define PHY4_PREFER_FIBER                 0x1
+
+#define MALIBU_PHY4_FIBER_MODE_1000BX      0x100
+#define AUTO_100FX_FIBER             0x0
+#define AUTO_1000BX_FIBER            0x1
+
+#define MALIBU_PHY_MDIX     0x0020
+#define MALIBU_PHY_MDIX_AUTO     0x0060
+#define MALIBU_PHY_MDIX_STATUS     0x0040
+
+#define MODE_CFG_QUAL                BIT_4
+#define MODE_CFG_QUAL_OFFSET         4
+#define MODE_CFG_QUAL_LEN            4
+
+#define MODE_CFG                     BIT_0
+#define MODE_CFG_OFFSET              0
+#define MODE_CFG_LEN                 4
+
+#define MALIBU_MODECTRL_DFLT	0x533
+#define MALIBU_MIICTRL_DFLT	0x140
+
+  /*debug port */
+#define MALIBU_DEBUG_PORT_RGMII_MODE            18
+#define MALIBU_DEBUG_PORT_RGMII_MODE_EN         0x0008
+
+#define MALIBU_DEBUG_PORT_RX_DELAY            0
+#define MALIBU_DEBUG_PORT_RX_DELAY_EN         0x8000
+
+#define MALIBU_DEBUG_PORT_TX_DELAY            5
+#define MALIBU_DEBUG_PORT_TX_DELAY_EN         0x0100
+
+  /* PHY Registers Field */
+
+  /* Control Register fields  offset:0 */
+  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MALIBU_CTRL_SPEED_MSB                   0x0040
+
+  /* Collision test enable */
+#define MALIBU_CTRL_COLL_TEST_ENABLE            0x0080
+
+  /* FDX =1, half duplex =0 */
+#define MALIBU_CTRL_FULL_DUPLEX                 0x0100
+
+  /* Restart auto negotiation */
+#define MALIBU_CTRL_RESTART_AUTONEGOTIATION     0x0200
+
+  /* Isolate PHY from MII */
+#define MALIBU_CTRL_ISOLATE                     0x0400
+
+  /* Power down */
+#define MALIBU_CTRL_POWER_DOWN                  0x0800
+
+  /* Auto Neg Enable */
+#define MALIBU_CTRL_AUTONEGOTIATION_ENABLE      0x1000
+
+  /* Local Loopback Enable */
+#define MALIBU_LOCAL_LOOPBACK_ENABLE      0x4000
+
+  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MALIBU_CTRL_SPEED_LSB                   0x2000
+
+  /* 0 = normal, 1 = loopback */
+#define MALIBU_CTRL_LOOPBACK                    0x4000
+#define MALIBU_CTRL_SOFTWARE_RESET              0x8000
+
+#define MALIBU_CTRL_SPEED_MASK                  0x2040
+#define MALIBU_CTRL_SPEED_1000                  0x0040
+#define MALIBU_CTRL_SPEED_100                   0x2000
+#define MALIBU_CTRL_SPEED_10                    0x0000
+
+#define MALIBU_RESET_DONE(phy_control)                   \
+    (((phy_control) & (MALIBU_CTRL_SOFTWARE_RESET)) == 0)
+
+  /* Status Register fields offset:1 */
+  /* Extended register capabilities */
+#define MALIBU_STATUS_EXTENDED_CAPS             0x0001
+
+  /* Jabber Detected */
+#define MALIBU_STATUS_JABBER_DETECT             0x0002
+
+  /* Link Status 1 = link */
+#define MALIBU_STATUS_LINK_STATUS_UP            0x0004
+
+  /* Auto Neg Capable */
+#define MALIBU_STATUS_AUTONEG_CAPS              0x0008
+
+  /* Remote Fault Detect */
+#define MALIBU_STATUS_REMOTE_FAULT              0x0010
+
+  /* Auto Neg Complete */
+#define MALIBU_STATUS_AUTO_NEG_DONE             0x0020
+
+  /* Preamble may be suppressed */
+#define MALIBU_STATUS_PREAMBLE_SUPPRESS         0x0040
+
+  /* Ext. status info in Reg 0x0F */
+#define MALIBU_STATUS_EXTENDED_STATUS           0x0100
+
+  /* 100T2 Half Duplex Capable */
+#define MALIBU_STATUS_100T2_HD_CAPS             0x0200
+
+  /* 100T2 Full Duplex Capable */
+#define MALIBU_STATUS_100T2_FD_CAPS             0x0400
+
+  /* 10T   Half Duplex Capable */
+#define MALIBU_STATUS_10T_HD_CAPS               0x0800
+
+  /* 10T   Full Duplex Capable */
+#define MALIBU_STATUS_10T_FD_CAPS               0x1000
+
+  /* 100X  Half Duplex Capable */
+#define MALIBU_STATUS_100X_HD_CAPS              0x2000
+
+  /* 100X  Full Duplex Capable */
+#define MALIBU_STATUS_100X_FD_CAPS              0x4000
+
+  /* 100T4 Capable */
+#define MALIBU_STATUS_100T4_CAPS                0x8000
+
+  /* extended status register capabilities */
+
+#define MALIBU_STATUS_1000T_HD_CAPS             0x1000
+
+#define MALIBU_STATUS_1000T_FD_CAPS             0x2000
+
+#define MALIBU_STATUS_1000X_HD_CAPS             0x4000
+
+#define MALIBU_STATUS_1000X_FD_CAPS             0x8000
+
+#define MALIBU_AUTONEG_DONE(ip_phy_status) \
+    (((ip_phy_status) & (MALIBU_STATUS_AUTO_NEG_DONE)) ==  \
+        (MALIBU_STATUS_AUTO_NEG_DONE))
+
+  /* PHY identifier1  offset:2 */
+//Organizationally Unique Identifier bits 3:18
+
+  /* PHY identifier2  offset:3 */
+//Organizationally Unique Identifier bits 19:24
+
+  /* Auto-Negotiation Advertisement register. offset:4 */
+  /* indicates IEEE 802.3 CSMA/CD */
+#define MALIBU_ADVERTISE_SELECTOR_FIELD         0x0001
+
+  /* 10T   Half Duplex Capable */
+#define MALIBU_ADVERTISE_10HALF                 0x0020
+
+  /* 10T   Full Duplex Capable */
+#define MALIBU_ADVERTISE_10FULL                 0x0040
+
+  /* 100TX Half Duplex Capable */
+#define MALIBU_ADVERTISE_100HALF                0x0080
+
+  /* 100TX Full Duplex Capable */
+#define MALIBU_ADVERTISE_100FULL                0x0100
+
+  /* 100T4 Capable */
+#define MALIBU_ADVERTISE_100T4                  0x0200
+
+  /* Pause operation desired */
+#define MALIBU_ADVERTISE_PAUSE                  0x0400
+
+  /* Asymmetric Pause Direction bit */
+#define MALIBU_ADVERTISE_ASYM_PAUSE             0x0800
+
+  /* Remote Fault detected */
+#define MALIBU_ADVERTISE_REMOTE_FAULT           0x2000
+
+  /* Next Page ability supported */
+#define MALIBU_ADVERTISE_NEXT_PAGE              0x8000
+
+  /* 100TX Half Duplex Capable */
+#define MALIBU_ADVERTISE_1000HALF               0x0100
+
+  /* 100TX Full Duplex Capable */
+#define MALIBU_ADVERTISE_1000FULL               0x0200
+
+  /* Extended next page enable control  */
+#define MALIBU_EXTENDED_NEXT_PAGE_EN            0x1000
+
+#define MALIBU_ADVERTISE_ALL \
+    (MALIBU_ADVERTISE_10HALF | MALIBU_ADVERTISE_10FULL | \
+     MALIBU_ADVERTISE_100HALF | MALIBU_ADVERTISE_100FULL | \
+     MALIBU_ADVERTISE_1000FULL)
+
+#define MALIBU_ADVERTISE_MEGA_ALL \
+    (MALIBU_ADVERTISE_10HALF | MALIBU_ADVERTISE_10FULL | \
+     MALIBU_ADVERTISE_100HALF | MALIBU_ADVERTISE_100FULL)
+
+#define MALIBU_BX_ADVERTISE_1000FULL                0x0020
+#define MALIBU_BX_ADVERTISE_1000HALF                0x0040
+#define MALIBU_BX_ADVERTISE_PAUSE                      0x0080
+#define MALIBU_BX_ADVERTISE_ASYM_PAUSE           0x0100
+
+#define MALIBU_BX_ADVERTISE_ALL \
+    (MALIBU_BX_ADVERTISE_ASYM_PAUSE | MALIBU_BX_ADVERTISE_PAUSE | \
+     MALIBU_BX_ADVERTISE_1000HALF | MALIBU_BX_ADVERTISE_1000FULL)
+
+  /* Link Partner ability offset:5 */
+  /* Same as advertise selector  */
+#define MALIBU_LINK_SLCT                        0x001f
+
+  /* Can do 10mbps half-duplex   */
+#define MALIBU_LINK_10BASETX_HALF_DUPLEX        0x0020
+
+  /* Can do 10mbps full-duplex   */
+#define MALIBU_LINK_10BASETX_FULL_DUPLEX        0x0040
+
+  /* Can do 100mbps half-duplex  */
+#define MALIBU_LINK_100BASETX_HALF_DUPLEX       0x0080
+
+  /* Can do 100mbps full-duplex  */
+#define MALIBU_LINK_100BASETX_FULL_DUPLEX       0x0100
+
+  /* Can do 1000mbps full-duplex  */
+#define MALIBU_LINK_1000BASETX_FULL_DUPLEX       0x0800
+
+  /* Can do 1000mbps half-duplex  */
+#define MALIBU_LINK_1000BASETX_HALF_DUPLEX       0x0400
+
+  /* 100BASE-T4  */
+#define MALIBU_LINK_100BASE4                    0x0200
+
+  /* PAUSE */
+#define MALIBU_LINK_PAUSE                       0x0400
+
+  /* Asymmetrical PAUSE */
+#define MALIBU_LINK_ASYPAUSE                    0x0800
+
+  /* Link partner faulted  */
+#define MALIBU_LINK_RFAULT                      0x2000
+
+  /* Link partner acked us */
+#define MALIBU_LINK_LPACK                       0x4000
+
+  /* Next page bit  */
+#define MALIBU_LINK_NPAGE                       0x8000
+
+  /* Auto-Negotiation Expansion Register offset:6 */
+
+  /* Next Page Transmit Register offset:7 */
+
+  /* Link partner Next Page Register offset:8 */
+
+  /* 1000BASE-T Control Register offset:9 */
+  /* Advertise 1000T HD capability */
+#define MALIBU_CTL_1000T_HD_CAPS                0x0100
+
+  /* Advertise 1000T FD capability  */
+#define MALIBU_CTL_1000T_FD_CAPS                0x0200
+
+  /* 1=Repeater/switch device port 0=DTE device */
+#define MALIBU_CTL_1000T_REPEATER_DTE           0x0400
+
+  /* 1=Configure PHY as Master  0=Configure PHY as Slave */
+#define MALIBU_CTL_1000T_MS_VALUE               0x0800
+
+  /* 1=Master/Slave manual config value  0=Automatic Master/Slave config */
+#define MALIBU_CTL_1000T_MS_ENABLE              0x1000
+
+  /* Normal Operation */
+#define MALIBU_CTL_1000T_TEST_MODE_NORMAL       0x0000
+
+  /* Transmit Waveform test */
+#define MALIBU_CTL_1000T_TEST_MODE_1            0x2000
+
+  /* Master Transmit Jitter test */
+#define MALIBU_CTL_1000T_TEST_MODE_2            0x4000
+
+  /* Slave Transmit Jitter test */
+#define MALIBU_CTL_1000T_TEST_MODE_3            0x6000
+
+  /* Transmitter Distortion test */
+#define MALIBU_CTL_1000T_TEST_MODE_4            0x8000
+#define MALIBU_CTL_1000T_SPEED_MASK             0x0300
+#define MALIBU_CTL_1000T_DEFAULT_CAP_MASK       0x0300
+
+  /* 1000BASE-T Status Register offset:10 */
+  /* LP is 1000T HD capable */
+#define MALIBU_STATUS_1000T_LP_HD_CAPS          0x0400
+
+  /* LP is 1000T FD capable */
+#define MALIBU_STATUS_1000T_LP_FD_CAPS          0x0800
+
+  /* Remote receiver OK */
+#define MALIBU_STATUS_1000T_REMOTE_RX_STATUS    0x1000
+
+  /* Local receiver OK */
+#define MALIBU_STATUS_1000T_LOCAL_RX_STATUS     0x2000
+
+  /* 1=Local TX is Master, 0=Slave */
+#define MALIBU_STATUS_1000T_MS_CONFIG_RES       0x4000
+
+#define MALIBU_STATUS_1000T_MS_CONFIG_FAULT     0x8000
+
+  /* Master/Slave config fault */
+#define MALIBU_STATUS_1000T_REMOTE_RX_STATUS_SHIFT   12
+#define MALIBU_STATUS_1000T_LOCAL_RX_STATUS_SHIFT    13
+
+  /* Phy Specific Control Register offset:16 */
+  /* 1=Jabber Function disabled */
+#define MALIBU_CTL_JABBER_DISABLE               0x0001
+
+  /* 1=Polarity Reversal enabled */
+#define MALIBU_CTL_POLARITY_REVERSAL            0x0002
+
+  /* 1=SQE Test enabled */
+#define MALIBU_CTL_SQE_TEST                     0x0004
+#define MALIBU_CTL_MAC_POWERDOWN                0x0008
+
+  /* 1=CLK125 low, 0=CLK125 toggling
+     #define MALIBU_CTL_CLK125_DISABLE               0x0010
+   */
+  /* MDI Crossover Mode bits 6:5 */
+  /* Manual MDI configuration */
+#define MALIBU_CTL_MDI_MANUAL_MODE              0x0000
+
+  /* Manual MDIX configuration */
+#define MALIBU_CTL_MDIX_MANUAL_MODE             0x0020
+
+  /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
+#define MALIBU_CTL_AUTO_X_1000T                 0x0040
+
+  /* Auto crossover enabled all speeds */
+#define MALIBU_CTL_AUTO_X_MODE                  0x0060
+
+  /* 1=Enable Extended 10BASE-T distance
+   * (Lower 10BASE-T RX Threshold)
+   * 0=Normal 10BASE-T RX Threshold */
+#define MALIBU_CTL_10BT_EXT_DIST_ENABLE         0x0080
+
+  /* 1=5-Bit interface in 100BASE-TX
+   * 0=MII interface in 100BASE-TX */
+#define MALIBU_CTL_MII_5BIT_ENABLE              0x0100
+
+  /* 1=Scrambler disable */
+#define MALIBU_CTL_SCRAMBLER_DISABLE            0x0200
+
+  /* 1=Force link good */
+#define MALIBU_CTL_FORCE_LINK_GOOD              0x0400
+
+  /* 1=Assert CRS on Transmit */
+#define MALIBU_CTL_ASSERT_CRS_ON_TX             0x0800
+
+#define MALIBU_CTL_POLARITY_REVERSAL_SHIFT      1
+#define MALIBU_CTL_AUTO_X_MODE_SHIFT            5
+#define MALIBU_CTL_10BT_EXT_DIST_ENABLE_SHIFT   7
+
+  /* Phy Specific status fields offset:17 */
+  /* 1=Speed & Duplex resolved */
+#define MALIBU_STATUS_LINK_PASS                 0x0400
+#define MALIBU_STATUS_RESOVLED                  0x0800
+
+  /* 1=Duplex 0=Half Duplex */
+#define MALIBU_STATUS_FULL_DUPLEX               0x2000
+
+  /* Speed, bits 14:15 */
+#define MALIBU_STATUS_SPEED                    0xC000
+#define MALIBU_STATUS_SPEED_MASK               0xC000
+
+  /* 00=10Mbs */
+#define MALIBU_STATUS_SPEED_10MBS              0x0000
+
+  /* 01=100Mbs */
+#define MALIBU_STATUS_SPEED_100MBS             0x4000
+
+  /* 10=1000Mbs */
+#define MALIBU_STATUS_SPEED_1000MBS            0x8000
+#define MALIBU_SPEED_DUPLEX_RESOVLED(phy_status)                   \
+    (((phy_status) &                                  \
+        (MALIBU_STATUS_RESOVLED)) ==                    \
+        (MALIBU_STATUS_RESOVLED))
+
+  /*phy debug port1 register offset:29 */
+  /*phy debug port2 register offset:30 */
+
+  /*MALIBU interrupt flag */
+#define MALIBU_INTR_SPEED_CHANGE              0x4000
+#define MALIBU_INTR_DUPLEX_CHANGE             0x2000
+#define MALIBU_INTR_STATUS_UP_CHANGE          0x0400
+#define MALIBU_INTR_STATUS_DOWN_CHANGE        0x0800
+#define MALIBU_INTR_BX_FX_STATUS_DOWN_CHANGE        0x0100
+#define MALIBU_INTR_BX_FX_STATUS_UP_CHANGE        0x0080
+#define MALIBU_INTR_MEDIA_STATUS_CHANGE             0x1000
+#define MALIBU_INTR_WOL             0x0001
+#define MALIBU_INTR_POE             0x0002
+
+#define RUN_CDT 0x8000
+#define CABLE_LENGTH_UNIT 0x0400
+
+/** Phy preferred medium type */
+  typedef enum
+  {
+    MALIBU_PHY_MEDIUM_COPPER = 0,
+				       /**< Copper */
+    MALIBU_PHY_MEDIUM_FIBER = 1,
+				       /**< Fiber */
+
+  } malibu_phy_medium_t;
+
+/** Phy pages */
+  typedef enum
+  {
+    MALIBU_PHY_SGBX_PAGES = 0,
+				       /**< sgbx pages */
+    MALIBU_PHY_COPPER_PAGES = 1
+				       /**< copper pages */
+  } malibu_phy_reg_pages_t;
+#ifndef IN_PORTCONTROL_MINI
+    sw_error_t
+    malibu_phy_set_powersave (a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_bool_t enable);
+
+    sw_error_t
+    malibu_phy_get_powersave (a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_bool_t * enable);
+
+    sw_error_t
+    malibu_phy_set_hibernate (a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_bool_t enable);
+
+    sw_error_t
+    malibu_phy_get_hibernate (a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_bool_t * enable);
+
+    sw_error_t
+    malibu_phy_cdt (a_uint32_t dev_id, a_uint32_t phy_id,
+		    a_uint32_t mdi_pair,
+		    fal_cable_status_t * cable_status,
+		    a_uint32_t * cable_len);
+#endif
+    sw_error_t
+    malibu_phy_set_duplex (a_uint32_t dev_id, a_uint32_t phy_id,
+			   fal_port_duplex_t duplex);
+
+    sw_error_t
+    malibu_phy_get_duplex (a_uint32_t dev_id, a_uint32_t phy_id,
+			   fal_port_duplex_t * duplex);
+
+    sw_error_t
+    malibu_phy_set_speed (a_uint32_t dev_id, a_uint32_t phy_id,
+			  fal_port_speed_t speed);
+
+    sw_error_t
+    malibu_phy_get_speed (a_uint32_t dev_id, a_uint32_t phy_id,
+			  fal_port_speed_t * speed);
+
+    sw_error_t
+    malibu_phy_restart_autoneg (a_uint32_t dev_id, a_uint32_t phy_id);
+
+    sw_error_t
+    malibu_phy_enable_autoneg (a_uint32_t dev_id, a_uint32_t phy_id);
+
+    a_bool_t
+    malibu_phy_get_link_status (a_uint32_t dev_id, a_uint32_t phy_id);
+
+    sw_error_t
+    malibu_phy_set_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id,
+				a_uint32_t autoneg);
+
+    sw_error_t
+    malibu_phy_get_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id,
+				a_uint32_t * autoneg);
+
+    a_bool_t malibu_phy_autoneg_status (a_uint32_t dev_id, a_uint32_t phy_id);
+#ifndef IN_PORTCONTROL_MINI
+    sw_error_t
+    malibu_phy_intr_mask_set (a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_uint32_t intr_mask_flag);
+
+    sw_error_t
+    malibu_phy_intr_mask_get (a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_uint32_t * intr_mask_flag);
+
+    sw_error_t
+    malibu_phy_intr_status_get (a_uint32_t dev_id, a_uint32_t phy_id,
+				a_uint32_t * intr_status_flag);
+
+  sw_error_t
+  malibu_phy_set_counter (a_uint32_t dev_id, a_uint32_t phy_id,
+				a_bool_t enable);
+  
+  sw_error_t
+  malibu_phy_get_counter (a_uint32_t dev_id, a_uint32_t phy_id,
+				a_bool_t * enable);
+
+  sw_error_t
+  malibu_phy_show_counter (a_uint32_t dev_id, a_uint32_t phy_id,
+			 fal_port_counter_info_t * counter_info);
+#endif
+  sw_error_t
+  malibu_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id,
+			a_bool_t * enable);
+#ifndef IN_PORTCONTROL_MINI
+  sw_error_t
+  malibu_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id,
+			a_bool_t enable);
+
+  sw_error_t
+  malibu_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id,
+		  a_uint32_t *phy_data);
+#endif
+  int malibu_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp);
+
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* _MALIBU_PHY_H_ */
diff --git a/qca-ssdk/include/hsl/phy/mpge_led.h b/qca-ssdk/include/hsl/phy/mpge_led.h
new file mode 100644
index 0000000..81d4b5e
--- /dev/null
+++ b/qca-ssdk/include/hsl/phy/mpge_led.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _MPGE_LED_H_
+#define _MPGE_LED_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif				/* __cplusplus */
+
+sw_error_t
+mpge_phy_led_ctrl_pattern_set(a_uint32_t dev_id, a_uint32_t phy_id,
+	led_ctrl_pattern_t *pattern);
+
+sw_error_t
+mpge_phy_led_ctrl_pattern_get(a_uint32_t dev_id, a_uint32_t phy_id,
+	led_ctrl_pattern_t * pattern);
+
+sw_error_t
+mpge_phy_led_ctrl_source_set(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t source_id, led_ctrl_pattern_t * pattern);
+
+void mpge_phy_led_api_ops_init(hsl_phy_ops_t *mpge_phy_led_api_ops);
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* _MPGE_LED_H_ */
diff --git a/qca-ssdk/include/hsl/phy/mpge_phy.h b/qca-ssdk/include/hsl/phy/mpge_phy.h
new file mode 100644
index 0000000..7854389
--- /dev/null
+++ b/qca-ssdk/include/hsl/phy/mpge_phy.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MPGE_PHY_H_
+#define _MPGE_PHY_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif				/* __cplusplus */
+/*MII register*/
+#define MPGE_PHY_CONTROL                          0x0
+#define MPGE_PHY_FIFO_CONTROL                     0x19
+#define MPGE_PHY_INTR_MASK                        0x12
+#define MPGE_PHY_INTR_STATUS                      0x13
+
+    /*MII register field*/
+#define MPGE_CTRL_AUTONEGOTIATION_ENABLE          0x1000
+#define MPGE_CTRL_RESTART_AUTONEGOTIATION         0x0200
+#define MPGE_CTRL_FULL_DUPLEX                     0x0100
+#define MPGE_CONTROL_SPEED_MASK                   0x2040
+#define MPGE_CONTROL_100M                         0x2000
+#define MPGE_CONTROL_10M                          0x0
+#define MPGE_PHY_FIFO_RESET                       0x3
+#define MPGE_INTR_SPEED_CHANGE                    0x4000
+#define MPGE_INTR_DUPLEX_CHANGE                   0x2000
+#define MPGE_INTR_STATUS_LINK_DOWN                0x0800
+#define MPGE_INTR_STATUS_LINK_UP                  0x0400
+#define MPGE_INTR_DOWNSHIF                        0x0020
+#define MPGE_INTR_WOL                             0x0001
+#define MPGE_INTR_FAST_LINK_DOWN_STAT_10M         0x40
+#define MPGE_INTR_FAST_LINK_DOWN_STAT_100M        0x200
+#define MPGE_INTR_FAST_LINK_DOWN_STAT_1000M       0x240
+#define MPGE_COMMON_CTRL                          0x1040
+#define MPGE_10M_LOOPBACK                         0x4100
+#define MPGE_100M_LOOPBACK                        0x6100
+#define MPGE_1000M_LOOPBACK                       0x4140
+
+/*MMD1 register*/
+#define MPGE_PHY_MMD1_NUM                         0x1
+#define MPGE_PHY_MMD1_MSE_THRESH1                 0x1000
+#define MPGE_PHY_MMD1_MSE_THRESH2                 0x1001
+#define MPGE_PHY_MMD1_DAC                         0x8100
+/*MMD1 register field*/
+#define MPGE_PHY_MMD1_MSE_THRESH1_VAL             0xf1
+#define MPGE_PHY_MMD1_MSE_THRESH2_VAL             0x1f6
+
+/*MMD3 register*/
+#define MPGE_PHY_MMD3_NUM                         0x3
+#define MPGE_PHY_MMD3_AZ_CTRL1                    0x8008
+#define MPGE_PHY_MMD3_AZ_CTRL2                    0x8009
+#define MPGE_PHY_MMD3_CDT_THRESH_CTRL3            0x8074
+#define MPGE_PHY_MMD3_CDT_THRESH_CTRL4            0x8075
+#define MPGE_PHY_MMD3_CDT_THRESH_CTRL5            0x8076
+#define MPGE_PHY_MMD3_CDT_THRESH_CTRL6            0x8077
+#define MPGE_PHY_MMD3_CDT_THRESH_CTRL7            0x8078
+#define MPGE_PHY_MMD3_CDT_THRESH_CTRL9            0x807a
+#define MPGE_PHY_MMD3_CDT_THRESH_CTRL13           0x807e
+#define MPGE_PHY_MMD3_CDT_THRESH_CTRL14           0x807f
+
+/*MMD3 register field*/
+#define MPGE_PHY_MMD3_AZ_CTRL1_VAL                0x7880
+#define MPGE_PHY_MMD3_AZ_CTRL2_VAL                0xc8
+#define MPGE_PHY_MMD3_CDT_THRESH_CTRL3_VAL        0xc040
+#define MPGE_PHY_MMD3_CDT_THRESH_CTRL4_VAL        0xa060
+#define MPGE_PHY_MMD3_CDT_THRESH_CTRL5_VAL        0xc040
+#define MPGE_PHY_MMD3_CDT_THRESH_CTRL6_VAL        0xa060
+#define MPGE_PHY_MMD3_CDT_THRESH_CTRL7_VAL        0xc24c
+#define MPGE_PHY_MMD3_CDT_THRESH_CTRL9_VAL        0xc060
+#define MPGE_PHY_MMD3_CDT_THRESH_CTRL13_VAL       0xb060
+#define MPGE_PHY_MMD3_NEAR_ECHO_THRESH_VAL        0x90b0
+
+/*debug register*/
+#define MPGE_PHY_DEBUG_EDAC                       0x4380
+
+/*debug port analog*/
+#define MPGE_PHY_DEBUG_ANA_LDO_EFUSE              0x180
+#define MPGE_PHY_DEBUG_ANA_DAC_FILTER             0xa080
+
+#define MPGE_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT      0x50
+
+int mpge_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp);
+
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* _MPGE_PHY_H_ */
diff --git a/qca-ssdk/include/hsl/phy/qca803x_phy.h b/qca-ssdk/include/hsl/phy/qca803x_phy.h
new file mode 100755
index 0000000..33013cc
--- /dev/null
+++ b/qca-ssdk/include/hsl/phy/qca803x_phy.h
@@ -0,0 +1,425 @@
+/*
+ * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _QCA803X_PHY_H_
+#define _QCA803X_PHY_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif				/* __cplusplus */
+
+#define QCA803X_COMMON_CTRL  0x1040
+#define QCA803X_10M_LOOPBACK  0x4100
+#define QCA803X_100M_LOOPBACK  0x6100
+#define QCA803X_1000M_LOOPBACK  0x4140
+
+  /* PHY Registers */
+#define QCA803X_PHY_CONTROL                      0
+#define QCA803X_PHY_STATUS                       1
+#define QCA803X_PHY_SPEC_STATUS                  17
+
+#define QCA803X_PHY_ID1                          2
+#define QCA803X_PHY_ID2                          3
+#define QCA803X_AUTONEG_ADVERT                   4
+#define QCA803X_LINK_PARTNER_ABILITY             5
+#define QCA803X_1000BASET_CONTROL                9
+#define QCA803X_1000BASET_STATUS                 10
+#define QCA803X_MMD_CTRL_REG                     13
+#define QCA803X_MMD_DATA_REG                     14
+#define QCA803X_EXTENDED_STATUS                  15
+#define QCA803X_PHY_SPEC_CONTROL                 16
+#define QCA803X_PHY_INTR_MASK                    18
+#define QCA803X_PHY_INTR_STATUS                  19
+#define QCA803X_PHY_CDT_CONTROL                  22
+#define QCA803X_PHY_CDT_STATUS                   28
+#define QCA803X_DEBUG_PORT_ADDRESS               29
+#define QCA803X_DEBUG_PORT_DATA                  30
+#define QCA803X_PHY_CHIP_CONFIG                  31 /* Chip Configuration Register  */
+#define QCA803X_DEBUG_MSE_THRESH                 27
+#define QCA803X_DEBUG_MSE_OVER_THRESH_TIMES      28
+
+#define QCA803X_PHY_MSE_THRESH_MASK              0x3f8
+#define QCA803X_PHY_MSE_THRESH_LINK_DOWN         0x170
+#define QCA803X_PHY_MSE_THRESH_LINK_UP           0x2e8
+#define QCA803X_PHY_MSE_OVER_THRESH_TIMES_MAX    0x7000
+
+#define QCA803X_PHY_FIBER_MODE_1000BX	0x100
+
+#define QCA803X_PHY_COPPER_PAGE_SEL  0x8000
+#define QCA803X_PHY_PREFER_FIBER  0x400
+
+#define QCA803X_PHY_CHIP_MODE_CFG	0x000f
+#define QCA803X_PHY_CHIP_MODE_STAT	0x00f0
+
+#define QCA803X_DEBUG_PHY_HIBERNATION_CTRL  0xb
+#define QCA803X_DEBUG_PHY_POWER_SAVING_CTRL  0x29
+#define QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL       0x3c
+#define QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_PARTNER       0x3d
+#define QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_STATUS       0x8000
+#define QCA803X_PHY_MMD3_ADDR_8023AZ_EEE_CAPABILITY       0x14
+
+#define QCA803X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL       0x805a
+#define QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL1   0x804a
+#define QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL2   0x804b
+#define QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL3   0x804c
+#define QCA803X_PHY_MMD3_WOL_CTRL  0x8012
+#define QCA803X_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL       0x804e
+#define QCA803X_PHY_MMD3_ADDR_8023AZ_CLD_CTRL       0x8007
+#define QCA803X_PHY_MMD3_ADDR_CLD_CTRL5       0x8005
+#define QCA803X_PHY_MMD3_ADDR_CLD_CTRL3       0x8003
+
+#define QCA803X_PHY_MDIX     0x0020
+#define QCA803X_PHY_MDIX_AUTO     0x0060
+#define QCA803X_PHY_MDIX_STATUS     0x0040
+
+#define QCA803X_PHY_MMD7_NUM  7
+#define QCA803X_PHY_MMD3_NUM  3
+
+#define QCA803X_PWR_SAVE 0x29
+#define QCA803X_PWR_SAVE_EN 0x8000
+
+#define QCA803X_PHY_EEE_ADV_100M 0x0002
+#define QCA803X_PHY_EEE_ADV_1000M 0x0004
+#define QCA803X_PHY_EEE_PARTNER_ADV_100M 0x0002
+#define QCA803X_PHY_EEE_PARTNER_ADV_1000M 0x0004
+#define QCA803X_PHY_EEE_CAPABILITY_100M 0x0002
+#define QCA803X_PHY_EEE_CAPABILITY_1000M 0x0004
+#define QCA803X_PHY_EEE_STATUS_100M 0x0002
+#define QCA803X_PHY_EEE_STATUS_1000M 0x0004
+
+	/* CDT */
+#define QCA803X_MDI_PAIR_NUM 4
+#define QCA803X_RUN_CDT 0x1
+#define CDT_PAIR_MASK 0x0300
+
+  /* PHY Registers Field */
+#define QCA803X_STATUS_LINK_PASS                 0x0400
+
+  /* Control Register fields  offset:0 */
+  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define QCA803X_CTRL_SPEED_MSB                   0x0040
+
+  /* Collision test enable */
+#define QCA803X_CTRL_COLL_TEST_ENABLE            0x0080
+
+  /* FDX =1, half duplex =0 */
+#define QCA803X_CTRL_FULL_DUPLEX                 0x0100
+
+  /* Restart auto negotiation */
+#define QCA803X_CTRL_RESTART_AUTONEGOTIATION     0x0200
+
+  /* Power down */
+#define QCA803X_CTRL_POWER_DOWN                  0x0800
+
+  /* Auto Neg Enable */
+#define QCA803X_CTRL_AUTONEGOTIATION_ENABLE      0x1000
+
+  /* Local Loopback Enable */
+#define QCA803X_LOCAL_LOOPBACK_ENABLE      0x4000
+
+  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define QCA803X_CTRL_SPEED_LSB                   0x2000
+
+  /* 0 = normal, 1 = loopback */
+#define QCA803X_CTRL_LOOPBACK                    0x4000
+#define QCA803X_CTRL_SOFTWARE_RESET              0x8000
+
+#define QCA803X_CTRL_SPEED_MASK                  0x2040
+#define QCA803X_CTRL_SPEED_1000                  0x0040
+#define QCA803X_CTRL_SPEED_100                   0x2000
+#define QCA803X_CTRL_SPEED_10                    0x0000
+
+#define QCA803X_RESET_DONE(phy_control)                   \
+    (((phy_control) & (QCA803X_CTRL_SOFTWARE_RESET)) == 0)
+
+  /* Status Register fields offset:1 */
+#define QCA803X_STATUS_EXTENDED_CAPS             0x0001
+
+  /* Jabber Detected */
+#define QCA803X_STATUS_JABBER_DETECT             0x0002
+
+  /* Link Status 1 = link */
+#define QCA803X_STATUS_LINK_STATUS_UP            0x0004
+
+  /* Auto Neg Capable */
+#define QCA803X_STATUS_AUTONEG_CAPS              0x0008
+
+  /* Remote Fault Detect */
+#define QCA803X_STATUS_REMOTE_FAULT              0x0010
+
+  /* Auto Neg Complete */
+#define QCA803X_STATUS_AUTO_NEG_DONE             0x0020
+
+  /* Preamble may be suppressed */
+#define QCA803X_STATUS_PREAMBLE_SUPPRESS         0x0040
+
+  /* Ext. status info in Reg 0x0F */
+#define QCA803X_STATUS_EXTENDED_STATUS           0x0100
+
+  /* 100T2 Half Duplex Capable */
+#define QCA803X_STATUS_100T2_HD_CAPS             0x0200
+
+  /* 100T2 Full Duplex Capable */
+#define QCA803X_STATUS_100T2_FD_CAPS             0x0400
+
+  /* 10T   Half Duplex Capable */
+#define QCA803X_STATUS_10T_HD_CAPS               0x0800
+
+  /* 10T   Full Duplex Capable */
+#define QCA803X_STATUS_10T_FD_CAPS               0x1000
+
+  /* 100X  Half Duplex Capable */
+#define QCA803X_STATUS_100X_HD_CAPS              0x2000
+
+  /* 100X  Full Duplex Capable */
+#define QCA803X_STATUS_100X_FD_CAPS              0x4000
+
+  /* 100T4 Capable */
+#define QCA803X_STATUS_100T4_CAPS                0x8000
+
+  /* extended status register capabilities */
+
+#define QCA803X_STATUS_1000T_HD_CAPS             0x1000
+
+#define QCA803X_STATUS_1000T_FD_CAPS             0x2000
+
+#define QCA803X_STATUS_1000X_HD_CAPS             0x4000
+
+#define QCA803X_STATUS_1000X_FD_CAPS             0x8000
+
+  /* Link Partner ability offset:5 */
+#define QCA803X_LINK_SLCT                        0x001f
+
+  /* Can do 10mbps half-duplex   */
+#define QCA803X_LINK_10BASETX_HALF_DUPLEX        0x0020
+
+  /* Can do 10mbps full-duplex   */
+#define QCA803X_LINK_10BASETX_FULL_DUPLEX        0x0040
+
+  /* Can do 100mbps half-duplex  */
+#define QCA803X_LINK_100BASETX_HALF_DUPLEX       0x0080
+
+  /* Can do 100mbps full-duplex  */
+#define QCA803X_LINK_100BASETX_FULL_DUPLEX       0x0100
+
+  /* Can do 1000mbps full-duplex  */
+#define QCA803X_LINK_1000BASETX_FULL_DUPLEX       0x0800
+
+  /* Can do 1000mbps half-duplex  */
+#define QCA803X_LINK_1000BASETX_HALF_DUPLEX       0x0400
+
+  /* 100BASE-T4  */
+#define QCA803X_LINK_100BASE4                    0x0200
+
+  /* PAUSE */
+#define QCA803X_LINK_PAUSE                       0x0400
+
+  /* Asymmetrical PAUSE */
+#define QCA803X_LINK_ASYPAUSE                    0x0800
+
+  /* Link partner faulted  */
+#define QCA803X_LINK_RFAULT                      0x2000
+
+  /* Link partner acked us */
+#define QCA803X_LINK_LPACK                       0x4000
+
+  /* Next page bit  */
+#define QCA803X_LINK_NPAGE                       0x8000
+
+  /* Auto Neg Complete */
+#define QCA803X_STATUS_AUTO_NEG_DONE             0x0020
+#define QCA803X_AUTONEG_DONE(ip_phy_status) \
+    (((ip_phy_status) & (QCA803X_STATUS_AUTO_NEG_DONE)) ==  \
+        (QCA803X_STATUS_AUTO_NEG_DONE))
+
+#define QCA803X_STATUS_RESOVLED                  0x0800
+#define QCA803X_SPEED_DUPLEX_RESOVLED(phy_status)                   \
+    (((phy_status) &                                  \
+        (QCA803X_STATUS_RESOVLED)) ==                    \
+        (QCA803X_STATUS_RESOVLED))
+
+  /* Auto-Negotiation Advertisement register. offset:4 */
+#define QCA803X_ADVERTISE_SELECTOR_FIELD         0x0001
+
+  /* 10T   Half Duplex Capable */
+#define QCA803X_ADVERTISE_10HALF                 0x0020
+
+  /* 10T   Full Duplex Capable */
+#define QCA803X_ADVERTISE_10FULL                 0x0040
+
+  /* 100TX Half Duplex Capable */
+#define QCA803X_ADVERTISE_100HALF                0x0080
+
+  /* 100TX Full Duplex Capable */
+#define QCA803X_ADVERTISE_100FULL                0x0100
+
+  /* 100T4 Capable */
+#define QCA803X_ADVERTISE_100T4                  0x0200
+
+  /* Pause operation desired */
+#define QCA803X_ADVERTISE_PAUSE                  0x0400
+
+  /* Asymmetric Pause Direction bit */
+#define QCA803X_ADVERTISE_ASYM_PAUSE             0x0800
+
+  /* Remote Fault detected */
+#define QCA803X_ADVERTISE_REMOTE_FAULT           0x2000
+
+  /* 100TX Half Duplex Capable */
+#define QCA803X_ADVERTISE_1000HALF                0x0100
+
+  /* 100TX Full Duplex Capable */
+#define QCA803X_ADVERTISE_1000FULL                0x0200
+
+  /* Extended next page enable control  */
+#define QCA803X_EXTENDED_NEXT_PAGE_EN             0x1000
+
+#define QCA803X_ADVERTISE_ALL \
+    (QCA803X_ADVERTISE_10HALF | QCA803X_ADVERTISE_10FULL | \
+     QCA803X_ADVERTISE_100HALF | QCA803X_ADVERTISE_100FULL | \
+     QCA803X_ADVERTISE_1000FULL)
+
+#define QCA803X_ADVERTISE_MEGA_ALL \
+    (QCA803X_ADVERTISE_10HALF | QCA803X_ADVERTISE_10FULL | \
+     QCA803X_ADVERTISE_100HALF | QCA803X_ADVERTISE_100FULL | \
+     QCA803X_ADVERTISE_PAUSE | QCA803X_ADVERTISE_ASYM_PAUSE)
+
+#define QCA803X_BX_ADVERTISE_1000FULL                0x0020
+#define QCA803X_BX_ADVERTISE_1000HALF                0x0040
+#define QCA803X_BX_ADVERTISE_PAUSE                      0x0080
+#define QCA803X_BX_ADVERTISE_ASYM_PAUSE           0x0100
+
+#define QCA803X_BX_ADVERTISE_ALL \
+    (QCA803X_BX_ADVERTISE_ASYM_PAUSE | QCA803X_BX_ADVERTISE_PAUSE | \
+     QCA803X_BX_ADVERTISE_1000HALF | QCA803X_BX_ADVERTISE_1000FULL)
+
+  /* 1=Duplex 0=Half Duplex */
+#define QCA803X_STATUS_FULL_DUPLEX               0x2000
+
+  /* Speed, bits 14:15 */
+#define QCA803X_STATUS_SPEED                    0xC000
+#define QCA803X_STATUS_SPEED_MASK               0xC000
+
+  /* 00=10Mbs */
+#define QCA803X_STATUS_SPEED_10MBS              0x0000
+
+  /* 01=100Mbs */
+#define QCA803X_STATUS_SPEED_100MBS             0x4000
+
+  /* 10=1000Mbs */
+#define QCA803X_STATUS_SPEED_1000MBS            0x8000
+
+	/*pause status */
+#define QCA803X_PHY_RX_FLOWCTRL_STATUS		0x4
+#define QCA803X_PHY_TX_FLOWCTRL_STATUS		0x8
+
+  /*QCA803X interrupt flag */
+#define QCA803X_INTR_SPEED_CHANGE              0x4000
+#define QCA803X_INTR_DUPLEX_CHANGE             0x2000
+#define QCA803X_INTR_STATUS_UP_CHANGE          0x0400
+#define QCA803X_INTR_STATUS_DOWN_CHANGE        0x0800
+#define QCA803X_INTR_BX_FX_STATUS_DOWN_CHANGE        0x0100
+#define QCA803X_INTR_BX_FX_STATUS_UP_CHANGE        0x0080
+#define QCA803X_INTR_MEDIA_STATUS_CHANGE             0x1000
+#define QCA803X_INTR_WOL             0x0001
+#define QCA803X_INTR_POE             0x0002
+
+/*QCA803X phy counter*/
+#define QCA803X_PHY_MMD7_FRAME_CTRL        0x8020
+#define QCA803X_PHY_MMD7_FRAME_DATA        0x8021
+
+#define QCA803X_PHY_MMD7_FRAME_CHECK       0x2000
+#define QCA803X_PHY_MMD7_FRAME_DIR         0x4000
+#define QCA803X_PHY_FRAME_CNT              0x00FF
+#define QCA803X_PHY_FRAME_ERROR            0xFF00
+
+  /** phy chip config */
+  typedef enum {
+	  QCA803X_PHY_RGMII_BASET = 0,
+	  QCA803X_PHY_SGMII_BASET = 1,
+	  QCA803X_PHY_BX1000_RGMII_50 = 2,
+	  QCA803X_PHY_FX100_RGMII_50 = 6,
+	  QCA803X_PHY_RGMII_AMDET = 11
+  } qca803x_cfg_t;
+
+  typedef enum {
+	  QCA803X_CHIP_CFG_SET,
+	  QCA803X_CHIP_CFG_STAT
+  } qca803x_cfg_type_t;
+
+/** Phy preferred medium type */
+  typedef enum
+  {
+	  QCA803X_PHY_MEDIUM_COPPER = 0,	/* Copper */
+	  QCA803X_PHY_MEDIUM_FIBER = 1,		/* Fiber */
+	  QCA803X_PHY_MEDIUM_MAX
+  } qca803x_phy_medium_t;
+
+sw_error_t
+qca803x_phy_set_duplex (a_uint32_t dev_id, a_uint32_t phy_id,
+		   fal_port_duplex_t duplex);
+
+sw_error_t
+qca803x_phy_get_duplex (a_uint32_t dev_id, a_uint32_t phy_id,
+		   fal_port_duplex_t * duplex);
+
+sw_error_t
+qca803x_phy_set_speed (a_uint32_t dev_id, a_uint32_t phy_id,
+		  fal_port_speed_t speed);
+
+sw_error_t
+qca803x_phy_get_speed (a_uint32_t dev_id, a_uint32_t phy_id,
+		  fal_port_speed_t * speed);
+
+sw_error_t
+qca803x_phy_restart_autoneg (a_uint32_t dev_id, a_uint32_t phy_id);
+
+sw_error_t
+qca803x_phy_enable_autoneg (a_uint32_t dev_id, a_uint32_t phy_id);
+
+a_bool_t
+qca803x_phy_get_link_status (a_uint32_t dev_id, a_uint32_t phy_id);
+
+sw_error_t
+qca803x_phy_set_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id,
+			a_uint32_t autoneg);
+
+sw_error_t
+qca803x_phy_get_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id,
+			a_uint32_t * autoneg);
+
+a_bool_t qca803x_phy_autoneg_status (a_uint32_t dev_id, a_uint32_t phy_id);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+qca803x_phy_intr_mask_set (a_uint32_t dev_id, a_uint32_t phy_id,
+		      a_uint32_t intr_mask_flag);
+
+sw_error_t
+qca803x_phy_intr_mask_get (a_uint32_t dev_id, a_uint32_t phy_id,
+		      a_uint32_t * intr_mask_flag);
+
+sw_error_t
+qca803x_phy_intr_status_get (a_uint32_t dev_id, a_uint32_t phy_id,
+			a_uint32_t * intr_status_flag);
+#endif
+sw_error_t
+qca803x_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *phy_data);
+int qca803x_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp);
+
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* _qca803x_PHY_H_ */
diff --git a/qca-ssdk/include/hsl/phy/qca808x.h b/qca-ssdk/include/hsl/phy/qca808x.h
new file mode 100755
index 0000000..12fb3f4
--- /dev/null
+++ b/qca-ssdk/include/hsl/phy/qca808x.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/kconfig.h>
+#include <linux/version.h>
+#include <linux/phy.h>
+#include <linux/kthread.h>
+
+#include "hsl.h"
+#include "ssdk_plat.h"
+#include "hsl_phy.h"
+#include "qca808x_phy.h"
+
+#if defined(IN_LINUX_STD_PTP)
+#include <linux/ptp_clock_kernel.h>
+enum {
+	PTP_PKT_SEQID_UNMATCHED,
+	PTP_PKT_SEQID_MATCHED,
+	PTP_PKT_SEQID_MATCH_MAX
+};
+
+enum {
+	QCA808X_PTP_MSG_SYNC,
+	QCA808X_PTP_MSG_DREQ,
+	QCA808X_PTP_MSG_PREQ,
+	QCA808X_PTP_MSG_PRESP,
+	QCA808X_PTP_MSG_MAX
+};
+
+typedef struct {
+	/* ptp filter class */
+	a_int32_t ptp_type;
+	/* ptp frame type */
+	a_int32_t pkt_type;
+} qca808x_ptp_cb;
+
+/* statistics for the event packet*/
+typedef struct {
+	/* the counter saves the packet with sequence id
+	 * matched and unmatched */
+	a_uint64_t sync_cnt[PTP_PKT_SEQID_MATCH_MAX];
+	a_uint64_t delay_req_cnt[PTP_PKT_SEQID_MATCH_MAX];
+	a_uint64_t pdelay_req_cnt[PTP_PKT_SEQID_MATCH_MAX];
+	a_uint64_t pdelay_resp_cnt[PTP_PKT_SEQID_MATCH_MAX];
+	a_uint64_t event_pkt_cnt;
+} ptp_packet_stat;
+
+typedef struct {
+	a_uint8_t reserved0;
+	a_uint8_t reserved1;
+	a_uint8_t msg_type;
+	a_uint16_t seqid;
+	a_uint32_t reserved2;
+	a_int64_t correction;
+} qca808x_embeded_ts;
+
+struct qca808x_ptp_info {
+	a_int32_t hwts_tx_type;
+	a_int32_t hwts_rx_type;
+	struct qca808x_ptp_clock *clock;
+	struct delayed_work tx_ts_work;
+	struct delayed_work rx_ts_work;
+	/* work for writing ingress time to register */
+	struct delayed_work ingress_trig_work;
+	a_int32_t ingress_time;
+	struct sk_buff_head tx_queue;
+	struct sk_buff_head rx_queue;
+	qca808x_embeded_ts embeded_ts;
+};
+#endif
+
+struct qca808x_phy_info {
+	struct list_head list;
+	a_uint32_t dev_id;
+	/* phy real address,it is the mdio addr or the i2c slave addr */
+	a_uint32_t phy_addr;
+	/* the address of phy device, it is a fake addr for the i2c accessed phy */
+	a_uint32_t phydev_addr;
+#if defined(IN_LINUX_STD_PTP)
+	a_int32_t speed;
+	a_uint16_t clock_mode;
+	a_uint16_t step_mode;
+	/* work for gps sencond sync */
+	struct delayed_work ts_schedule_work;
+	a_bool_t gps_seconds_sync_en;
+	/*the statistics array records the counter of
+	 * rx and tx ptp event packet */
+	ptp_packet_stat pkt_stat[2];
+#endif
+};
+
+typedef struct {
+	struct phy_device *phydev;
+	struct qca808x_phy_info *phy_info;
+#if defined(IN_LINUX_STD_PTP)
+	struct qca808x_ptp_info ptp_info;
+#endif
+} qca808x_priv;
+
+#if defined(IN_LINUX_STD_PTP)
+struct qca808x_ptp_clock{
+	struct ptp_clock_info caps;
+	struct ptp_clock *ptp_clock;
+	struct mutex tsreg_lock;
+	qca808x_priv *priv;
+};
+
+struct qca808x_phy_info* qca808x_phy_info_get(a_uint32_t phy_addr);
+void qca808x_ptp_change_notify(struct phy_device *phydev);
+int qca808x_hwtstamp(struct phy_device *phydev, struct ifreq *ifr);
+bool qca808x_rxtstamp(struct phy_device *phydev, struct sk_buff *skb, int type);
+void qca808x_txtstamp(struct phy_device *phydev, struct sk_buff *skb, int type);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+int qca808x_ts_info(struct phy_device *phydev, struct ethtool_ts_info *info);
+#endif
+sw_error_t qca808x_ptp_config_init(struct phy_device *phydev);
+int qca808x_ptp_init(qca808x_priv *priv);
+void qca808x_ptp_deinit(qca808x_priv *priv);
+#endif
+
+void qca808x_phydev_init(a_uint32_t dev_id, a_uint32_t port_id);
+void qca808x_phydev_deinit(a_uint32_t dev_id, a_uint32_t port_id);
+a_int32_t qca808x_phy_driver_register(void);
+void qca808x_phy_driver_unregister(void);
diff --git a/qca-ssdk/include/hsl/phy/qca808x_led.h b/qca-ssdk/include/hsl/phy/qca808x_led.h
new file mode 100644
index 0000000..8991b09
--- /dev/null
+++ b/qca-ssdk/include/hsl/phy/qca808x_led.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _QCA808X_LED_H_
+#define _QCA808X_LED_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif				/* __cplusplus */
+#define QCA808X_PHY_MMD7_LED_POLARITY_MASK      0x40
+#define QCA808X_PHY_LINK_2500M_LIGHT_EN         0x8000
+#define QCA808X_PHY_LINK_1000M_LIGHT_EN         0x40
+#define QCA808X_PHY_LINK_100M_LIGHT_EN          0x20
+#define QCA808X_PHY_LINK_10M_LIGHT_EN           0x10
+#define QCA808X_PHY_RX_TRAFFIC_BLINK_EN         0x200
+#define QCA808X_PHY_TX_TRAFFIC_BLINK_EN         0x400
+
+#define QCA808X_PHY_LED_SOURCE0                 0x0
+#define QCA808X_PHY_LED_SOURCE1                 0x1
+#define QCA808X_PHY_LED_SOURCE2                 0x2
+
+sw_error_t
+qca808x_phy_led_ctrl_pattern_set(a_uint32_t dev_id, a_uint32_t phy_id,
+	led_ctrl_pattern_t *pattern);
+sw_error_t
+qca808x_phy_led_ctrl_pattern_get(a_uint32_t dev_id, a_uint32_t phy_id,
+	led_ctrl_pattern_t *pattern);
+sw_error_t
+qca808x_phy_led_ctrl_source_set(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t source_id, led_ctrl_pattern_t *pattern);
+sw_error_t
+qca808x_phy_led_ctrl_source_get(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t source_id, led_ctrl_pattern_t *pattern);
+void qca808x_phy_led_api_ops_init(hsl_phy_ops_t *qca808x_phy_led_api_ops);
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* _qca808x_LED_H_ */
diff --git a/qca-ssdk/include/hsl/phy/qca808x_phy.h b/qca-ssdk/include/hsl/phy/qca808x_phy.h
new file mode 100644
index 0000000..da92dae
--- /dev/null
+++ b/qca-ssdk/include/hsl/phy/qca808x_phy.h
@@ -0,0 +1,634 @@
+/*
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _QCA808X_PHY_H_
+#define _QCA808X_PHY_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif				/* __cplusplus */
+
+#define QCA808X_MII_ADDR_C45  (1<<30)
+#define QCA808X_REG_C45_ADDRESS(dev_type, reg_num) (QCA808X_MII_ADDR_C45 | \
+			((dev_type & 0x1f) << 16) | (reg_num & 0xffff))
+
+#define QCA808X_COMMON_CTRL  0x1040
+
+#define QCA808X_PHY_MMD1_PMA_CONTROL       0x0
+#define QCA808X_PMA_CONTROL_SPEED_MASK     0x2040
+#define QCA808X_PMA_CONTROL_2500M          0x2040
+#define QCA808X_PMA_CONTROL_1000M          0x40
+#define QCA808X_PMA_CONTROL_100M           0x2000
+#define QCA808X_PMA_CONTROL_10M            0x0
+
+#define QCA808X_PHY_MMD1_PMA_TYPE       0x7
+#define QCA808X_PMA_TYPE_MASK           0x3f
+#define QCA808X_PMA_TYPE_2500M          0x30
+#define QCA808X_PMA_TYPE_1000M          0xc
+#define QCA808X_PMA_TYPE_100M           0xe
+#define QCA808X_PMA_TYPE_10M            0xf
+
+  /* PHY Registers */
+#define QCA808X_PHY_CONTROL                      0
+#define QCA808X_PHY_STATUS                       1
+#define QCA808X_PHY_SPEC_STATUS                  17
+
+#define QCA808X_PHY_ID1                          2
+#define QCA808X_PHY_ID2                          3
+#define QCA808X_AUTONEG_ADVERT                   4
+#define QCA808X_LINK_PARTNER_ABILITY             5
+#define QCA808X_1000BASET_CONTROL                9
+#define QCA808X_1000BASET_STATUS                 10
+#define QCA808X_MMD_CTRL_REG                     13
+#define QCA808X_MMD_DATA_REG                     14
+#define QCA808X_EXTENDED_STATUS                  15
+#define QCA808X_PHY_SPEC_CONTROL                 16
+#define QCA808X_PHY_INTR_MASK                    18
+#define QCA808X_PHY_INTR_STATUS                  19
+#define QCA808X_PHY_CDT_CONTROL                  22
+#define QCA808X_DEBUG_PORT_ADDRESS               29
+#define QCA808X_DEBUG_PORT_DATA                  30
+#define QCA808X_DEBUG_LOCAL_SEED                 9
+
+/* Chip Configuration Register */
+#define QCA808X_PHY_CHIP_CONFIG                  31
+
+#define QCA808X_PHY_MODE_MASK              0x6000
+#define QCA808X_PHY_SGMII_MODE             0x0000
+#define QCA808X_PHY_SGMII_PLUS_MODE        0x2000
+#define QCA808X_PHY_SGMII_BASET            0x4
+#define QCA808X_PHY_CHIP_MODE_CFG          0xf
+
+#define QCA808X_DEBUG_PHY_HIBERNATION_CTRL          0xb
+#define QCA808X_DEBUG_PHY_HIBERNATION_STAT          0xc
+#define QCA808X_DEBUG_PHY_POWER_SAVING_CTRL         0x29
+#define QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL       0x3c
+#define QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_PARTNER    0x3d
+#define QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_STATUS     0x8000
+#define QCA808X_PHY_MMD3_ADDR_8023AZ_EEE_CAPABILITY 0x14
+#define QCA808X_PHY_MMD7_ADDR_EEE_LP_ADVERTISEMENT  0x40
+
+#define QCA808X_PHY_MMD3_ADDR_8023AZ_EEE_DB         0x800f
+#define QCA808X_PHY_8023AZ_EEE_LP_STAT              0x2000
+#define QCA808X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL  0x805a
+#define QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL1        0x804a
+#define QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL2        0x804b
+#define QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL3        0x804c
+#define QCA808X_PHY_MMD3_WOL_CTRL                   0x8012
+#define QCA808X_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL     0x804e
+#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7             0x8007
+#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL5             0x8005
+#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL3             0x8003
+#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL           0x8008
+
+#define QCA808X_PHY_HIBERNATION_CFG       0x8000
+#define QCA808X_PHY_HIBERNATION_STAT_EN   0x0800
+
+#define QCA808X_PHY_WOL_EN                0x0020
+
+#define QCA808X_PHY_REMOTE_LOOPBACK_EN    0x0001
+
+#define QCA808X_PHY_8023AZ_EEE_1000BT     0x0004
+#define QCA808X_PHY_8023AZ_EEE_100BT      0x0002
+#define QCA808X_PHY_MMD3_AZ_TRAINING_VAL  0x1c32
+
+#define QCA808X_PHY_MDIX          0x0020
+#define QCA808X_PHY_MDIX_AUTO     0x0060
+#define QCA808X_PHY_MDIX_STATUS   0x0040
+
+#define QCA808X_PHY_MMD7_NUM  7
+#define QCA808X_PHY_MMD3_NUM  3
+#define QCA808X_PHY_MMD1_NUM  1
+
+#define QCA808X_PHY_MMD1_FAST_RETRAIN_STATUS_CTL 0x93
+#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB      0x8014
+#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB      0x800E
+#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB      0x801E
+#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB      0x8020
+#define QCA808X_PHY_MMD7_TOP_OPTION1             0x901c
+#define QCA808X_PHY_EEE_ADV_100M 0x0002
+#define QCA808X_PHY_EEE_ADV_1000M 0x0004
+#define QCA808X_PHY_EEE_PARTNER_ADV_100M 0x0002
+#define QCA808X_PHY_EEE_PARTNER_ADV_1000M 0x0004
+#define QCA808X_PHY_EEE_CAPABILITY_100M 0x0002
+#define QCA808X_PHY_EEE_CAPABILITY_1000M 0x0004
+#define QCA808X_PHY_EEE_STATUS_100M 0x0002
+#define QCA808X_PHY_EEE_STATUS_1000M 0x0004
+
+#define QCA808X_PHY_FAST_RETRAIN_CTRL           0x1
+#define QCA808X_PHY_MSE_THRESHOLD_20DB_VALUE    0x529
+#define QCA808X_PHY_MSE_THRESHOLD_17DB_VALUE    0x341
+#define QCA808X_PHY_MSE_THRESHOLD_27DB_VALUE    0x419
+#define QCA808X_PHY_MSE_THRESHOLD_28DB_VALUE    0x341
+#define QCA808X_PHY_FAST_RETRAIN_2500BT         0x20
+#define QCA808X_PHY_ADV_LOOP_TIMING             0x1
+#define QCA808X_PHY_EEE_ADV_THP                 0x8
+#define QCA808X_PHY_TOP_OPTION1_DATA            0x0
+
+	/* CDT */
+#define QCA808X_MDI_PAIR_NUM            4
+#define QCA808X_RUN_CDT                 0x8000
+#define QCA808X_CABLE_LENGTH_UNIT       0x0400
+#define QCA808X_PHY_CDT_STATUS          0X8064
+#define QCA808X_PHY_CDT_DIAG_PAIR0      0X8065
+#define QCA808X_PHY_CDT_DIAG_PAIR1      0X8066
+#define QCA808X_PHY_CDT_DIAG_PAIR2      0X8067
+#define QCA808X_PHY_CDT_DIAG_PAIR3      0X8068
+
+	/* SYNCE CLOCK OUTPUT */
+#define QCA808X_DEBUG_ANA_CLOCK_CTRL_REG   0x3e80
+#define QCA808X_ANALOG_PHY_SYNCE_CLOCK_EN  0x20
+
+#define QCA808X_MMD7_CLOCK_CTRL_REG        0x8072
+#define QCA808X_DIGITAL_PHY_SYNCE_CLOCK_EN 0x1
+
+  /* PHY Registers Field */
+#define QCA808X_STATUS_LINK_PASS                 0x0400
+
+  /* Control Register fields  offset:0 */
+  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define QCA808X_CTRL_SPEED_MSB                   0x0040
+
+  /* Collision test enable */
+#define QCA808X_CTRL_COLL_TEST_ENABLE            0x0080
+/* FDX =1, half duplex =0 */
+#define QCA808X_CTRL_FULL_DUPLEX                 0x0100
+
+  /* Restart auto negotiation */
+#define QCA808X_CTRL_RESTART_AUTONEGOTIATION     0x0200
+
+  /* Power down */
+#define QCA808X_CTRL_POWER_DOWN                  0x0800
+
+  /* Auto Neg Enable */
+#define QCA808X_CTRL_AUTONEGOTIATION_ENABLE      0x1000
+
+  /* Local Loopback Enable */
+#define QCA808X_LOCAL_LOOPBACK_ENABLE            0x4000
+
+  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define QCA808X_CTRL_SPEED_LSB                   0x2000
+
+  /* 0 = normal, 1 = loopback */
+#define QCA808X_CTRL_LOOPBACK                    0x4000
+#define QCA808X_CTRL_SOFTWARE_RESET              0x8000
+
+#define QCA808X_PHY_MMD7_AUTONEGOTIATION_CONTROL 0x20
+
+#define QCA808X_CTRL_SPEED_MASK                  0x2040
+#define QCA808X_CTRL_SPEED_1000                  0x0040
+#define QCA808X_CTRL_SPEED_100                   0x2000
+#define QCA808X_CTRL_SPEED_10                    0x0000
+
+#define QCA808X_MASTER_SLAVE_SEED_ENABLE         0x2
+#define QCA808X_MASTER_SLAVE_SEED_CFG            0x1FFC
+#define QCA808X_MASTER_SLAVE_SEED_RANGE          0x32
+#define QCA808X_MASTER_SLAVE_CONFIG_FAULT        0x8000
+
+#define QCA808X_RESET_DONE(phy_control)                   \
+    (((phy_control) & (QCA808X_CTRL_SOFTWARE_RESET)) == 0)
+
+  /* Status Register fields offset:1 */
+#define QCA808X_STATUS_EXTENDED_CAPS             0x0001
+
+  /* Jabber Detected */
+#define QCA808X_STATUS_JABBER_DETECT             0x0002
+
+  /* Link Status 1 = link */
+#define QCA808X_STATUS_LINK_STATUS_UP            0x0004
+
+  /* Auto Neg Capable */
+#define QCA808X_STATUS_AUTONEG_CAPS              0x0008
+
+  /* Remote Fault Detect */
+#define QCA808X_STATUS_REMOTE_FAULT              0x0010
+
+  /* Auto Neg Complete */
+#define QCA808X_STATUS_AUTO_NEG_DONE             0x0020
+
+  /* Preamble may be suppressed */
+#define QCA808X_STATUS_PREAMBLE_SUPPRESS         0x0040
+
+  /* Ext. status info in Reg 0x0F */
+#define QCA808X_STATUS_EXTENDED_STATUS           0x0100
+
+  /* 100T2 Half Duplex Capable */
+#define QCA808X_STATUS_100T2_HD_CAPS             0x0200
+
+  /* 100T2 Full Duplex Capable */
+#define QCA808X_STATUS_100T2_FD_CAPS             0x0400
+
+  /* 10T   Half Duplex Capable */
+#define QCA808X_STATUS_10T_HD_CAPS               0x0800
+
+  /* 10T   Full Duplex Capable */
+#define QCA808X_STATUS_10T_FD_CAPS               0x1000
+
+  /* 100TX  Half Duplex Capable */
+#define QCA808X_STATUS_100TX_HD_CAPS              0x2000
+
+  /* 100TX  Full Duplex Capable */
+#define QCA808X_STATUS_100TX_FD_CAPS              0x4000
+
+  /* 100T4 Capable */
+#define QCA808X_STATUS_100T4_CAPS                0x8000
+
+  /* extended status register capabilities */
+
+#define QCA808X_STATUS_1000T_HD_CAPS             0x1000
+
+#define QCA808X_STATUS_1000T_FD_CAPS             0x2000
+
+#define QCA808X_STATUS_1000X_HD_CAPS             0x4000
+
+#define QCA808X_STATUS_1000X_FD_CAPS             0x8000
+
+#define QCA808X_MMD1_PMA_CAP_REG                 0x4
+	/* MMD1 2500T capabilities */
+#define QCA808X_STATUS_2500T_FD_CAPS             0x2000
+
+  /* Link Partner ability offset:5 */
+#define QCA808X_LINK_SLCT                        0x001f
+
+  /* Can do 10mbps half-duplex   */
+#define QCA808X_LINK_10BASETX_HALF_DUPLEX        0x0020
+
+  /* Can do 10mbps full-duplex   */
+#define QCA808X_LINK_10BASETX_FULL_DUPLEX        0x0040
+
+  /* Can do 100mbps half-duplex  */
+#define QCA808X_LINK_100BASETX_HALF_DUPLEX       0x0080
+
+  /* Can do 100mbps full-duplex  */
+#define QCA808X_LINK_100BASETX_FULL_DUPLEX       0x0100
+
+  /* Can do 1000mbps full-duplex  */
+#define QCA808X_LINK_1000BASETX_FULL_DUPLEX      0x0800
+
+  /* Can do 1000mbps half-duplex  */
+#define QCA808X_LINK_1000BASETX_HALF_DUPLEX      0x0400
+
+  /* Can do 2500mbps full-duplex  */
+#define QCA808X_LINK_2500BASETX_FULL_DUPLEX      0x0020
+
+  /* 100BASE-T4  */
+#define QCA808X_LINK_100BASE4                    0x0200
+
+  /* PAUSE */
+#define QCA808X_LINK_PAUSE                       0x0400
+
+  /* Asymmetrical PAUSE */
+#define QCA808X_LINK_ASYPAUSE                    0x0800
+
+  /* Link partner faulted  */
+#define QCA808X_LINK_RFAULT                      0x2000
+
+  /* Link partner acked us */
+#define QCA808X_LINK_LPACK                       0x4000
+
+  /* Next page bit  */
+#define QCA808X_LINK_NPAGE                       0x8000
+
+  /* Auto Neg Complete */
+#define QCA808X_STATUS_AUTO_NEG_DONE             0x0020
+#define QCA808X_AUTONEG_DONE(ip_phy_status) \
+    (((ip_phy_status) & (QCA808X_STATUS_AUTO_NEG_DONE)) ==  \
+        (QCA808X_STATUS_AUTO_NEG_DONE))
+
+#define QCA808X_STATUS_RESOVLED                  0x0800
+#define QCA808X_SPEED_DUPLEX_RESOVLED(phy_status)     \
+    (((phy_status) &                                  \
+        (QCA808X_STATUS_RESOVLED)) ==                 \
+        (QCA808X_STATUS_RESOVLED))
+
+  /* Auto-Negotiation Advertisement register. offset:4 */
+#define QCA808X_ADVERTISE_SELECTOR_FIELD         0x0001
+
+  /* 10T   Half Duplex Capable */
+#define QCA808X_ADVERTISE_10HALF                 0x0020
+
+  /* 10T   Full Duplex Capable */
+#define QCA808X_ADVERTISE_10FULL                 0x0040
+
+  /* 100TX Half Duplex Capable */
+#define QCA808X_ADVERTISE_100HALF                0x0080
+
+  /* 100TX Full Duplex Capable */
+#define QCA808X_ADVERTISE_100FULL                0x0100
+
+  /* 100T4 Capable */
+#define QCA808X_ADVERTISE_100T4                  0x0200
+
+  /* Pause operation desired */
+#define QCA808X_ADVERTISE_PAUSE                  0x0400
+
+  /* Asymmetric Pause Direction bit */
+#define QCA808X_ADVERTISE_ASYM_PAUSE             0x0800
+
+  /* Remote Fault detected */
+#define QCA808X_ADVERTISE_REMOTE_FAULT           0x2000
+
+  /* 1000TX Half Duplex Capable */
+#define QCA808X_ADVERTISE_1000HALF               0x0100
+
+  /* 1000TX Full Duplex Capable */
+#define QCA808X_ADVERTISE_1000FULL               0x0200
+
+  /* 2500TX Full Duplex Capable */
+#define QCA808X_ADVERTISE_2500FULL               0x80
+
+#define QCA808X_ADVERTISE_ALL \
+    (QCA808X_ADVERTISE_10HALF | QCA808X_ADVERTISE_10FULL | \
+     QCA808X_ADVERTISE_100HALF | QCA808X_ADVERTISE_100FULL | \
+     QCA808X_ADVERTISE_1000FULL)
+
+#define QCA808X_ADVERTISE_MEGA_ALL \
+    (QCA808X_ADVERTISE_10HALF | QCA808X_ADVERTISE_10FULL | \
+     QCA808X_ADVERTISE_100HALF | QCA808X_ADVERTISE_100FULL | \
+     QCA808X_ADVERTISE_PAUSE | QCA808X_ADVERTISE_ASYM_PAUSE)
+
+#define QCA808X_BX_ADVERTISE_1000FULL            0x0020
+#define QCA808X_BX_ADVERTISE_1000HALF            0x0040
+#define QCA808X_BX_ADVERTISE_PAUSE               0x0080
+#define QCA808X_BX_ADVERTISE_ASYM_PAUSE          0x0100
+
+#define QCA808X_BX_ADVERTISE_ALL \
+    (QCA808X_BX_ADVERTISE_ASYM_PAUSE | QCA808X_BX_ADVERTISE_PAUSE | \
+     QCA808X_BX_ADVERTISE_1000HALF | QCA808X_BX_ADVERTISE_1000FULL)
+
+  /* 1=Duplex 0=Half Duplex */
+#define QCA808X_STATUS_FULL_DUPLEX               0x2000
+#define QCA808X_PHY_RX_FLOWCTRL_STATUS           0x4
+#define QCA808X_PHY_TX_FLOWCTRL_STATUS           0x8
+
+  /* Speed, bits 9:7 */
+#define QCA808X_STATUS_SPEED_MASK               0x380
+
+  /* 000=10Mbs */
+#define QCA808X_STATUS_SPEED_10MBS              0x0000
+
+  /* 001=100Mbs */
+#define QCA808X_STATUS_SPEED_100MBS             0x80
+
+  /* 010=1000Mbs */
+#define QCA808X_STATUS_SPEED_1000MBS            0x100
+
+  /* 100=2500Mbs */
+#define QCA808X_STATUS_SPEED_2500MBS            0x200
+
+  /*QCA808X interrupt flag */
+#define QCA808X_INTR_FAST_LINK_DOWN             0x8000
+#define QCA808X_INTR_SPEED_CHANGE               0x4000
+#define QCA808X_INTR_SEC_ENA_CHANGE             0x2000
+#define QCA808X_INTR_STATUS_DOWN_CHANGE         0x0800
+#define QCA808X_INTR_STATUS_UP_CHANGE           0x0400
+#define QCA808X_INTR_FAST_LINK_DOWN_MASK        0x240
+#define QCA808X_INTR_FAST_LINK_DOWN_STAT_10M    0x40
+#define QCA808X_INTR_FAST_LINK_DOWN_STAT_100M   0x200
+#define QCA808X_INTR_FAST_LINK_DOWN_STAT_1000M  0x240
+#define QCA808X_INTR_LINK_FAIL_SG               0x0100
+#define QCA808X_INTR_LINK_SUCCESS_SG            0x0080
+#define QCA808X_INTR_DOWNSHIF                   0x0020
+#define QCA808X_INTR_10MS_PTP                   0x0010
+#define QCA808X_INTR_RX_PTP                     0x0008
+#define QCA808X_INTR_TX_PTP                     0x0004
+#define QCA808X_INTR_POE                        0x0002
+#define QCA808X_INTR_WOL                        0x0001
+
+  /* QCA808X counter */
+#define QCA808X_PHY_MMD7_COUNTER_CTRL           0x8029
+#define QCA808X_PHY_MMD7_INGRESS_COUNTER_HIGH   0x802a
+#define QCA808X_PHY_MMD7_INGRESS_COUNTER_LOW    0x802b
+#define QCA808X_PHY_MMD7_INGRESS_ERROR_COUNTER  0x802c
+#define QCA808X_PHY_MMD7_EGRESS_COUNTER_HIGH    0x802d
+#define QCA808X_PHY_MMD7_EGRESS_COUNTER_LOW     0x802e
+#define QCA808X_PHY_MMD7_EGRESS_ERROR_COUNTER   0x802f
+#define QCA808X_PHY_MMD7_LED_POLARITY_CTRL      0x901a
+#define QCA808X_PHY_MMD7_LED0_CTRL              0x8078
+#define QCA808X_PHY_MMD7_LED1_CTRL              0x8074
+#define QCA808X_PHY_MMD7_LED2_CTRL              0x8076
+#define QCA808X_PHY_MMD7_LED_POLARITY_ACTIVE_HIGH 0x46
+#define QCA808X_PHY_MMD7_LED0_CTRL_ENABLE       0x8670
+#define QCA808X_PHY_MMD7_LED1_CTRL_DISABLE      0x0
+#define QCA808X_PHY_MMD7_LED2_CTRL_DISABLE      0x0
+
+#define QCA808X_PHY_FRAME_CHECK_EN              0x0001
+#define QCA808X_PHY_XMIT_MAC_CNT_SELFCLR        0x0002
+
+#define QCA808X_PHY_ADC_THRESHOLD               0x2c80
+#define QCA808X_PHY_ADC_THRESHOLD_80MV          0
+#define QCA808X_PHY_ADC_THRESHOLD_100MV         0xf0
+#define QCA808X_PHY_ADC_THRESHOLD_200MV         0x0f
+#define QCA808X_PHY_ADC_THRESHOLD_300MV         0xff
+
+#define QCA808X_PHY_MMD7_CHIP_TYPE              0x901d
+#define QCA808X_PHY_1G_CHIP_TYPE                0x1
+
+a_uint16_t
+qca808x_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id);
+
+sw_error_t
+qca808x_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t reg_id, a_uint16_t reg_val);
+
+sw_error_t
+qca808x_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint16_t mmd_num, a_uint16_t reg_id,
+		a_uint16_t reg_val);
+
+a_uint16_t
+qca808x_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint16_t mmd_num, a_uint16_t reg_id);
+
+a_uint16_t
+qca808x_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id);
+
+sw_error_t
+qca808x_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t
+reg_id, a_uint16_t reg_val);
+
+sw_error_t
+qca808x_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id,
+		       a_uint16_t reg_val);
+a_uint16_t
+qca808x_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id);
+
+sw_error_t
+qca808x_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint16_t mmd_num, a_uint16_t reg_id, a_uint16_t
+reg_val);
+
+a_uint16_t
+qca808x_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint16_t mmd_num, a_uint16_t reg_id);
+
+#define QCA808X_PHY_8023AZ_AFE_CTRL_MASK        0x01f0
+#define QCA808X_PHY_8023AZ_AFE_EN               0x0090
+
+sw_error_t
+qca808x_phy_set_duplex (a_uint32_t dev_id, a_uint32_t phy_id,
+		   fal_port_duplex_t duplex);
+
+sw_error_t
+qca808x_phy_get_duplex (a_uint32_t dev_id, a_uint32_t phy_id,
+		   fal_port_duplex_t * duplex);
+
+sw_error_t
+qca808x_phy_set_speed (a_uint32_t dev_id, a_uint32_t phy_id,
+		  fal_port_speed_t speed);
+
+sw_error_t
+qca808x_phy_get_speed (a_uint32_t dev_id, a_uint32_t phy_id,
+		  fal_port_speed_t * speed);
+
+sw_error_t
+qca808x_phy_restart_autoneg (a_uint32_t dev_id, a_uint32_t phy_id);
+
+sw_error_t
+qca808x_phy_enable_autoneg (a_uint32_t dev_id, a_uint32_t phy_id);
+
+a_bool_t
+qca808x_phy_get_link_status (a_uint32_t dev_id, a_uint32_t phy_id);
+
+sw_error_t
+qca808x_phy_set_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id,
+			a_uint32_t autoneg);
+
+sw_error_t
+qca808x_phy_get_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id,
+			a_uint32_t * autoneg);
+
+a_bool_t qca808x_phy_autoneg_status (a_uint32_t dev_id, a_uint32_t phy_id);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+qca808x_phy_intr_mask_set (a_uint32_t dev_id, a_uint32_t phy_id,
+		      a_uint32_t intr_mask_flag);
+
+sw_error_t
+qca808x_phy_intr_mask_get (a_uint32_t dev_id, a_uint32_t phy_id,
+		      a_uint32_t * intr_mask_flag);
+
+sw_error_t
+qca808x_phy_intr_status_get (a_uint32_t dev_id, a_uint32_t phy_id,
+			a_uint32_t * intr_status_flag);
+#endif
+sw_error_t
+qca808x_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *phy_data);
+
+sw_error_t
+qca808x_phy_get_status(a_uint32_t dev_id, a_uint32_t phy_id,
+		struct port_phy_status *phy_status);
+
+sw_error_t
+qca808x_phy_interface_get_mode_status(a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_port_interface_mode_t *interface_mode_status);
+
+sw_error_t qca808x_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id);
+
+sw_error_t
+qca808x_phy_set_force_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+		     fal_port_speed_t speed);
+sw_error_t qca808x_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id);
+sw_error_t qca808x_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+qca808x_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable);
+sw_error_t
+qca808x_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_bool_t * enable);
+sw_error_t
+qca808x_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+	fal_cable_status_t * cable_status, a_uint32_t * cable_len);
+sw_error_t
+qca808x_phy_set_mdix(a_uint32_t dev_id, a_uint32_t phy_id,
+	fal_port_mdix_mode_t mode);
+sw_error_t
+qca808x_phy_get_mdix(a_uint32_t dev_id, a_uint32_t phy_id,
+	fal_port_mdix_mode_t * mode);
+sw_error_t
+qca808x_phy_get_mdix_status(a_uint32_t dev_id, a_uint32_t phy_id,
+	fal_port_mdix_status_t * mode);
+sw_error_t
+qca808x_phy_set_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_bool_t enable);
+sw_error_t
+qca808x_phy_get_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_bool_t * enable);
+sw_error_t
+qca808x_phy_set_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_bool_t enable);
+sw_error_t
+qca808x_phy_get_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_bool_t * enable);
+sw_error_t
+qca808x_phy_set_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable);
+sw_error_t
+qca808x_phy_get_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable);
+sw_error_t
+qca808x_phy_set_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id,
+	fal_mac_addr_t * mac);
+sw_error_t
+qca808x_phy_get_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id,
+	fal_mac_addr_t * mac);
+sw_error_t
+qca808x_phy_set_counter(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable);
+sw_error_t
+qca808x_phy_get_counter(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_bool_t * enable);
+sw_error_t
+qca808x_phy_show_counter(a_uint32_t dev_id, a_uint32_t phy_id,
+	fal_port_counter_info_t * counter_infor);
+sw_error_t
+qca808x_phy_set_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t intr_mask_flag);
+sw_error_t
+qca808x_phy_get_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t * intr_mask_flag);
+sw_error_t
+qca808x_phy_get_intr_status(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t * intr_status_flag);
+sw_error_t
+qca808x_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable);
+sw_error_t
+qca808x_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable);
+#endif
+sw_error_t
+qca808x_phy_set_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t adv);
+sw_error_t
+qca808x_phy_get_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *adv);
+sw_error_t
+qca808x_phy_get_eee_partner_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *adv);
+sw_error_t
+qca808x_phy_get_eee_cap(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *cap);
+sw_error_t
+qca808x_phy_get_eee_status(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *status);
+void qca808x_phy_lock_init(void);
+int qca808x_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp);
+
+void qca808x_phy_exit(a_uint32_t dev_id, a_uint32_t port_id);
+a_bool_t
+qca808x_phy_2500caps(a_uint32_t dev_id, a_uint32_t phy_id);
+
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* _qca808x_PHY_H_ */
diff --git a/qca-ssdk/include/hsl/phy/qca808x_ptp.h b/qca-ssdk/include/hsl/phy/qca808x_ptp.h
new file mode 100755
index 0000000..045c370
--- /dev/null
+++ b/qca-ssdk/include/hsl/phy/qca808x_ptp.h
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _QCA808X_PTP_H_
+#define _QCA808X_PTP_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif				/* __cplusplus */
+
+#define PTP_DEV_ID	0
+
+sw_error_t
+qca808x_phy_ptp_security_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_security_t *sec);
+
+sw_error_t
+qca808x_phy_ptp_link_delay_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time);
+
+sw_error_t
+qca808x_phy_ptp_rx_crc_recalc_status_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_bool_t *status);
+
+sw_error_t
+qca808x_phy_ptp_tod_uart_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_tod_uart_t *tod_uart);
+
+sw_error_t
+qca808x_phy_ptp_enhanced_timestamp_engine_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_direction_t direction,
+		fal_ptp_enhanced_ts_engine_t *ts_engine);
+
+sw_error_t
+qca808x_phy_ptp_pps_signal_control_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_pps_signal_control_t *sig_control);
+
+sw_error_t
+qca808x_phy_ptp_timestamp_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_direction_t direction,
+		fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time);
+
+sw_error_t
+qca808x_phy_ptp_asym_correction_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_asym_correction_t* asym_cf);
+
+sw_error_t
+qca808x_phy_ptp_rtc_time_snapshot_status_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_bool_t *status);
+
+sw_error_t
+qca808x_phy_ptp_capture_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_uint32_t capture_id,
+		fal_ptp_capture_t *capture);
+
+sw_error_t
+qca808x_phy_ptp_rtc_adjfreq_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time);
+
+sw_error_t
+qca808x_phy_ptp_asym_correction_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_asym_correction_t *asym_cf);
+
+sw_error_t
+qca808x_phy_ptp_pkt_timestamp_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time);
+
+sw_error_t
+qca808x_phy_ptp_rtc_time_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time);
+
+sw_error_t
+qca808x_phy_ptp_rtc_time_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time);
+
+sw_error_t
+qca808x_phy_ptp_pkt_timestamp_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time);
+
+sw_error_t
+qca808x_phy_ptp_interrupt_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_interrupt_t *interrupt);
+
+sw_error_t
+qca808x_phy_ptp_trigger_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_uint32_t trigger_id,
+		fal_ptp_trigger_t *triger);
+
+sw_error_t
+qca808x_phy_ptp_pps_signal_control_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_pps_signal_control_t *sig_control);
+
+sw_error_t
+qca808x_phy_ptp_capture_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_uint32_t capture_id,
+		fal_ptp_capture_t *capture);
+
+sw_error_t
+qca808x_phy_ptp_rx_crc_recalc_enable(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_bool_t status);
+
+sw_error_t
+qca808x_phy_ptp_security_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_security_t *sec);
+
+sw_error_t
+qca808x_phy_ptp_increment_sync_from_clock_status_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_bool_t *status);
+
+sw_error_t
+qca808x_phy_ptp_tod_uart_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_tod_uart_t *tod_uart);
+
+sw_error_t
+qca808x_phy_ptp_enhanced_timestamp_engine_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_direction_t direction,
+		fal_ptp_enhanced_ts_engine_t *ts_engine);
+
+sw_error_t
+qca808x_phy_ptp_rtc_time_clear(a_uint32_t dev_id,
+		a_uint32_t phy_id);
+
+sw_error_t
+qca808x_phy_ptp_reference_clock_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_reference_clock_t ref_clock);
+
+sw_error_t
+qca808x_phy_ptp_output_waveform_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_output_waveform_t *waveform);
+
+sw_error_t
+qca808x_phy_ptp_rx_timestamp_mode_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_rx_timestamp_mode_t ts_mode);
+
+sw_error_t
+qca808x_phy_ptp_grandmaster_mode_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_grandmaster_mode_t *gm_mode);
+
+sw_error_t
+qca808x_phy_ptp_config_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_config_t *config);
+
+sw_error_t
+qca808x_phy_ptp_trigger_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_uint32_t trigger_id,
+		fal_ptp_trigger_t *triger);
+
+sw_error_t
+qca808x_phy_ptp_rtc_adjfreq_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time);
+
+sw_error_t
+qca808x_phy_ptp_grandmaster_mode_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_grandmaster_mode_t *gm_mode);
+
+sw_error_t
+qca808x_phy_ptp_rx_timestamp_mode_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_rx_timestamp_mode_t *ts_mode);
+
+sw_error_t
+qca808x_phy_ptp_rtc_adjtime_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time);
+
+sw_error_t
+qca808x_phy_ptp_link_delay_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time);
+
+sw_error_t
+qca808x_phy_ptp_increment_sync_from_clock_enable(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_bool_t status);
+
+sw_error_t
+qca808x_phy_ptp_config_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_config_t *config);
+
+sw_error_t
+qca808x_phy_ptp_output_waveform_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_output_waveform_t *waveform);
+
+sw_error_t
+qca808x_phy_ptp_interrupt_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_interrupt_t *interrupt);
+
+sw_error_t
+qca808x_phy_ptp_rtc_time_snapshot_enable(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_bool_t status);
+
+sw_error_t
+qca808x_phy_ptp_reference_clock_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_reference_clock_t *ref_clock);
+
+void qca808x_phy_ptp_api_ops_init(hsl_phy_ptp_ops_t *phy_ptp_ops);
+
+#if defined(IN_LINUX_STD_PTP)
+void qca808x_ptp_gm_gps_seconds_sync_enable(a_uint32_t dev_id,
+		a_uint32_t phy_addr, a_bool_t en);
+
+a_bool_t qca808x_ptp_gm_gps_seconds_sync_status_get(a_uint32_t dev_id,
+		a_uint32_t phy_addr);
+
+void qca808x_ptp_clock_mode_config(a_uint32_t dev_id,
+		a_uint32_t phy_addr, a_uint16_t clock_mode, a_uint16_t step_mode);
+
+void qca808x_ptp_stat_get(void);
+
+void qca808x_ptp_stat_set(void);
+#endif
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* _qca808x_PTP_H_ */
diff --git a/qca-ssdk/include/hsl/phy/qca808x_ptp_api.h b/qca-ssdk/include/hsl/phy/qca808x_ptp_api.h
new file mode 100755
index 0000000..5e1464f
--- /dev/null
+++ b/qca-ssdk/include/hsl/phy/qca808x_ptp_api.h
@@ -0,0 +1,5858 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _PTP_REG_API_H_
+#define _PTP_REG_API_H_
+
+#define PTP_REG_BASE_ADDR    0x3000
+
+
+sw_error_t
+qca808x_ptp_imr_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_imr_reg_u *value);
+
+sw_error_t
+qca808x_ptp_imr_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_imr_reg_u *value);
+
+sw_error_t
+qca808x_ptp_isr_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_isr_reg_u *value);
+
+sw_error_t
+qca808x_ptp_isr_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_isr_reg_u *value);
+
+sw_error_t
+qca808x_ptp_hw_enable_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_hw_enable_reg_u *value);
+
+sw_error_t
+qca808x_ptp_hw_enable_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_hw_enable_reg_u *value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_main_conf_reg_u *value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_main_conf_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_seqid0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_seqid0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_clk_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_clk_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_clk_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_clk_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_5_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_5_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_6_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_6_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_seqid_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_seqid_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_seqid_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_seqid_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_portid0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_portid0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_portid1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_portid1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_portid2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_portid2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_portid3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_portid3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_portid4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_portid4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_ts0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_ts0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_ts1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_ts1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_ts2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_ts2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_ts3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_ts3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_ts4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_ts4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_ts5_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_ts5_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_ts6_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_ts6_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_orig_corr0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_orig_corr0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_orig_corr1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_orig_corr1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_orig_corr2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_orig_corr2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_orig_corr3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_orig_corr3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_in_trig0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_in_trig0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_in_trig1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_in_trig1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_in_trig2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_in_trig2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_in_trig3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_in_trig3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_latency_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_latency_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_latency_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_latency_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_inc0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_inc0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_inc0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_inc0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_inc1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_inc1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_inc1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_inc1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc5_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc5_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc6_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc6_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs_valid_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs_valid_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs_valid_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs_valid_reg_u *value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_misc_config_reg_u *value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_misc_config_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ext_imr_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ext_imr_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ext_imr_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ext_imr_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ext_isr_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ext_isr_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ext_isr_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ext_isr_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_ext_conf_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_ext_conf_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_gm_conf0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_gm_conf0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_gm_conf1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_gm_conf1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_gm_conf1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_gm_conf1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_hwpll_inc0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_hwpll_inc0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_hwpll_inc0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_hwpll_inc0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_hwpll_inc1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_hwpll_inc1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_hwpll_inc1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_hwpll_inc1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ppsin_latency_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_latency_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ppsin_latency_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_latency_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_config_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_config_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_status_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_status_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_config_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_config_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_status_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_status_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event0_config_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_config_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event0_config_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_config_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event0_status_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_status_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event0_status_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_status_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event1_config_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_config_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event1_config_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_config_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event1_status_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_status_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event1_status_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_status_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_seqid1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_seqid1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_5_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_5_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_6_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_6_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_seqid2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_seqid2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_5_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_5_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_6_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_6_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_seqid3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_seqid3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_5_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_5_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_6_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_6_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_imr_reg_mask_bmp_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_imr_reg_mask_bmp_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_isr_reg_status_bmp_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_isr_reg_status_bmp_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_hw_enable_reg_ptp_hw_enable_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_hw_enable_reg_ptp_hw_enable_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ts_attach_mode_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ts_attach_mode_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ptp_clk_sel_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ptp_clk_sel_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_disable_1588_phy_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_disable_1588_phy_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_attach_crc_recal_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_attach_crc_recal_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ipv4_force_checksum_zero_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ipv4_force_checksum_zero_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ipv6_embed_force_checksum_zero_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ipv6_embed_force_checksum_zero_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ptp_bypass_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ptp_bypass_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_wol_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_wol_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ptp_clock_mode_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ptp_clock_mode_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_seqid0_reg_rx_seqid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_seqid0_reg_rx_seqid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_0_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_0_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_1_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_1_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_2_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_2_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_3_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_3_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_4_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid0_4_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_clk_reg_rtc_clk_selection_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_clk_reg_rtc_clk_selection_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_0_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_0_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_1_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_1_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_2_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_2_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_3_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_3_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_4_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_4_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_5_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_5_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_5_reg_rx_msg_type_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_5_reg_rx_msg_type_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_6_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts0_6_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_seqid_reg_tx_seqid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_seqid_reg_tx_seqid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_portid0_reg_tx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_portid0_reg_tx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_portid1_reg_tx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_portid1_reg_tx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_portid2_reg_tx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_portid2_reg_tx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_portid3_reg_tx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_portid3_reg_tx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_portid4_reg_tx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_portid4_reg_tx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_ts0_reg_tx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_ts0_reg_tx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_ts1_reg_tx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_ts1_reg_tx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_ts2_reg_tx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_ts2_reg_tx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_ts3_reg_tx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_ts3_reg_tx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_ts4_reg_tx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_ts4_reg_tx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_ts5_reg_tx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_ts5_reg_tx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_ts5_reg_tx_msg_type_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_ts5_reg_tx_msg_type_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_ts6_reg_tx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_ts6_reg_tx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_orig_corr0_reg_ptp_orig_corr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_orig_corr0_reg_ptp_orig_corr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_orig_corr1_reg_ptp_orig_corr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_orig_corr1_reg_ptp_orig_corr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_orig_corr2_reg_ptp_orig_corr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_orig_corr2_reg_ptp_orig_corr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_orig_corr3_reg_ptp_orig_corr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_orig_corr3_reg_ptp_orig_corr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_in_trig0_reg_ptp_in_trig_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_in_trig0_reg_ptp_in_trig_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_in_trig1_reg_ptp_in_trig_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_in_trig1_reg_ptp_in_trig_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_in_trig2_reg_ptp_in_trig_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_in_trig2_reg_ptp_in_trig_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_in_trig3_reg_ptp_in_trig_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_in_trig3_reg_ptp_in_trig_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_latency_reg_ptp_tx_latency_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_latency_reg_ptp_tx_latency_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nis_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nis_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nfs_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nfs_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_inc1_reg_ptp_rtc_inc_nfs_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_inc1_reg_ptp_rtc_inc_nfs_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtcoffs0_reg_ptp_rtcoffs_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs0_reg_ptp_rtcoffs_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtcoffs1_reg_ptp_rtcoffs_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs1_reg_ptp_rtcoffs_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtcoffs2_reg_ptp_rtcoffs_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs2_reg_ptp_rtcoffs_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtcoffs3_reg_ptp_rtcoffs_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs3_reg_ptp_rtcoffs_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtcoffs4_reg_ptp_rtcoffs_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs4_reg_ptp_rtcoffs_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc0_reg_ptp_rtc_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc0_reg_ptp_rtc_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc1_reg_ptp_rtc_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc1_reg_ptp_rtc_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc2_reg_ptp_rtc_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc2_reg_ptp_rtc_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc3_reg_ptp_rtc_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc3_reg_ptp_rtc_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc4_reg_ptp_rtc_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc4_reg_ptp_rtc_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc5_reg_ptp_rtc_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc5_reg_ptp_rtc_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc6_reg_ptp_rtc_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc6_reg_ptp_rtc_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtcoffs_valid_reg_ptp_rtcoffs_valid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtcoffs_valid_reg_ptp_rtcoffs_valid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ptp_ver_chk_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ptp_ver_chk_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ipv6_udp_chk_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ipv6_udp_chk_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_cf_from_pkt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_cf_from_pkt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_embed_ingress_time_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_embed_ingress_time_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ptp_addr_chk_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ptp_addr_chk_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_crc_validate_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_crc_validate_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_pkt_one_step_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_pkt_one_step_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ptp_version_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ptp_version_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_appended_timestamp_size_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_appended_timestamp_size_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ts_rtc_select_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ts_rtc_select_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_ext_imr_reg_mask_bmp_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_ext_imr_reg_mask_bmp_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_ext_isr_reg_status_bmp_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_ext_isr_reg_status_bmp_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_rtc_snapshot_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_rtc_snapshot_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_set_incval_mode_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_set_incval_mode_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_load_rtc_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_load_rtc_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_clear_rtc_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_clear_rtc_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_rtc_read_mode_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_rtc_read_mode_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_select_output_waveform_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_select_output_waveform_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_set_incval_valid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_set_incval_valid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded0_reg_ptp_rtc_preloaded_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded0_reg_ptp_rtc_preloaded_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded1_reg_ptp_rtc_preloaded_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded1_reg_ptp_rtc_preloaded_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded2_reg_ptp_rtc_preloaded_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded2_reg_ptp_rtc_preloaded_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded3_reg_ptp_rtc_preloaded_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded3_reg_ptp_rtc_preloaded_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded4_reg_ptp_rtc_preloaded_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rtc_preloaded4_reg_ptp_rtc_preloaded_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_gm_pps_sync_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_gm_pps_sync_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_gm_pll_mode_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_gm_pll_mode_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_gm_maxfreq_offset_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_gm_maxfreq_offset_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_grandmaster_mode_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_grandmaster_mode_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_gm_conf1_reg_gm_kp_ldn_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_gm_conf1_reg_gm_kp_ldn_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_gm_conf1_reg_gm_ki_ldn_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_gm_conf1_reg_gm_ki_ldn_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts0_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts0_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts1_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts1_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts2_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts2_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts3_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts3_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts4_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_ppsin_ts4_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nfs1_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nfs1_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nis_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nis_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_hwpll_inc1_reg_ptp_rtc_inc_nfs0_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_hwpll_inc1_reg_ptp_rtc_inc_nfs0_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_sign_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_sign_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_value_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_value_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_force_value_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_force_value_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_pattern_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_pattern_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_status_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_status_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_force_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_force_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_setting_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_setting_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_notify_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_notify_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_if_late_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_if_late_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_error_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_error_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_active_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_active_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_finished_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_finished_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_force_value_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_force_value_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_pattern_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_pattern_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_status_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_status_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_force_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_force_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_setting_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_setting_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_notify_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_notify_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_if_late_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_if_late_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_error_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_error_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_active_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_active_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_finished_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_finished_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp0_reg_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp0_reg_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp1_reg_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp1_reg_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp2_reg_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp2_reg_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp3_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp3_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp4_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp4_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp0_reg_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp0_reg_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp1_reg_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp1_reg_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp2_reg_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp2_reg_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp3_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp3_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp4_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp4_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event0_config_reg_rise_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event0_config_reg_rise_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event0_config_reg_single_cap_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event0_config_reg_single_cap_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event0_config_reg_fall_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event0_config_reg_fall_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event0_config_reg_notify_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event0_config_reg_notify_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event0_config_reg_clear_stat_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event0_config_reg_clear_stat_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event0_status_reg_mul_event_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event0_status_reg_mul_event_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event0_status_reg_missed_count_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event0_status_reg_missed_count_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event0_status_reg_dir_detected_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event0_status_reg_dir_detected_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event0_status_reg_detected_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event0_status_reg_detected_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event1_config_reg_rise_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event1_config_reg_rise_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event1_config_reg_single_cap_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event1_config_reg_single_cap_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event1_config_reg_fall_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event1_config_reg_fall_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event1_config_reg_notify_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event1_config_reg_notify_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event1_config_reg_clear_stat_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event1_config_reg_clear_stat_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event1_status_reg_mul_event_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event1_status_reg_mul_event_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event1_status_reg_missed_count_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event1_status_reg_missed_count_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event1_status_reg_dir_detected_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event1_status_reg_dir_detected_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event1_status_reg_detected_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event1_status_reg_detected_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp0_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp0_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp1_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp1_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp2_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp2_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp3_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp3_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp4_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event0_timestamp4_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp0_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp0_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp1_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp1_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp2_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp2_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp3_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp3_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp4_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_event1_timestamp4_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_seqid1_reg_rx_seqid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_seqid1_reg_rx_seqid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_0_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_0_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_1_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_1_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_2_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_2_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_3_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_3_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_4_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid1_4_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_0_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_0_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_1_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_1_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_2_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_2_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_3_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_3_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_4_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_4_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_5_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_5_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_5_reg_rx_msg_type_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_5_reg_rx_msg_type_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_6_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts1_6_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_seqid2_reg_rx_seqid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_seqid2_reg_rx_seqid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_0_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_0_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_1_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_1_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_2_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_2_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_3_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_3_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_4_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid2_4_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_0_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_0_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_1_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_1_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_2_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_2_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_3_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_3_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_4_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_4_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_5_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_5_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_5_reg_rx_msg_type_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_5_reg_rx_msg_type_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_6_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts2_6_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_seqid3_reg_rx_seqid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_seqid3_reg_rx_seqid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_0_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_0_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_1_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_1_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_2_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_2_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_3_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_3_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_4_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_portid3_4_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_0_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_0_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_1_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_1_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_2_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_2_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_3_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_3_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_4_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_4_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_5_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_5_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_5_reg_rx_msg_type_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_5_reg_rx_msg_type_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_6_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_ts3_6_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_phase_adjust_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_phase_adjust_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_phase_adjust_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_phase_adjust_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_phase_adjust_0_reg_phase_value_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_phase_adjust_0_reg_phase_value_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_phase_adjust_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_phase_adjust_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_phase_adjust_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_phase_adjust_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_phase_adjust_1_reg_phase_value_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_phase_adjust_1_reg_phase_value_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_pps_pul_width_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_pps_pul_width_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_pps_pul_width_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_pps_pul_width_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_pps_pul_width_0_reg_pul_value_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_pps_pul_width_0_reg_pul_value_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_pps_pul_width_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_pps_pul_width_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_pps_pul_width_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_pps_pul_width_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_pps_pul_width_1_reg_pul_value_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_pps_pul_width_1_reg_pul_value_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_freq_waveform_period_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_freq_waveform_period_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_0_reg_wave_period_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_0_reg_wave_period_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_0_reg_phase_ali_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_0_reg_phase_ali_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_freq_waveform_period_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_freq_waveform_period_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_1_reg_wave_period_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_1_reg_wave_period_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_freq_waveform_period_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_freq_waveform_period_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_2_reg_wave_period_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_2_reg_wave_period_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_ts_ctrl_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_ts_ctrl_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_da0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_da0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_da1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_da1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_da2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_da2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv4_da0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv4_da0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv4_da1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv4_da1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da5_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da5_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da6_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da6_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da7_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da7_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da7_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da7_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_lengthtype_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_lengthtype_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_lengthtype_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_lengthtype_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_layer4_protocol_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_layer4_protocol_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_layer4_protocol_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_layer4_protocol_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_udp_port_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_udp_port_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_udp_port_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_udp_port_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_ts_status_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_ts_status_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_frac_nano_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_frac_nano_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_pre_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_frac_nano_pre_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_pre_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_frac_nano_pre_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_y1731_identify_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_y1731_identify_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_pre_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_y1731_identify_pre_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_pre_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_y1731_identify_pre_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_ts_ctrl_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_ts_ctrl_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_da0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_da0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_da1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_da1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_da2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_da2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv4_da0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv4_da0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv4_da1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv4_da1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da5_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da5_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da5_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da6_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da6_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da6_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da7_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da7_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da7_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da7_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_lengthtype_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_lengthtype_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_lengthtype_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_lengthtype_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_layer4_protocol_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_layer4_protocol_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_layer4_protocol_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_layer4_protocol_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_udp_port_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_udp_port_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_udp_port_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_udp_port_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_ts_status_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_ts_status_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp3_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp4_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_frac_nano_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_frac_nano_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_com_frac_nano_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_frac_nano_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_y1731_identify_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_y1731_identify_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_y1731_identify_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_y1731_identify_reg_u *value);
+
+sw_error_t
+qca808x_ptp_y1731_dm_control_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_y1731_dm_control_reg_u *value);
+
+sw_error_t
+qca808x_ptp_y1731_dm_control_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_y1731_dm_control_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_pre_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_ts_status_pre_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_pre_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_ts_status_pre_reg_u *value);
+
+sw_error_t
+qca808x_ptp_baud_config_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_baud_config_reg_u *value);
+
+sw_error_t
+qca808x_ptp_baud_config_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_baud_config_reg_u *value);
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_uart_configuration_reg_u *value);
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_uart_configuration_reg_u *value);
+
+sw_error_t
+qca808x_ptp_reset_buffer_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_reset_buffer_reg_u *value);
+
+sw_error_t
+qca808x_ptp_reset_buffer_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_reset_buffer_reg_u *value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_buffer_status_reg_u *value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_buffer_status_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_buffer_write_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_buffer_write_reg_u *value);
+
+sw_error_t
+qca808x_ptp_tx_buffer_write_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_buffer_write_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_buffer_read_reg_u *value);
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_buffer_read_reg_u *value);
+
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_da_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_da_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_mac_lengthtype_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_mac_lengthtype_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_y1731_da_chk_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_y1731_da_chk_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_pw_mac_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_pw_mac_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_udp_ptp_event_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_udp_ptp_event_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_udp_dport_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_udp_dport_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_mac_ptp_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_mac_ptp_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_da_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_da_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_next_header_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_next_header_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_y1731_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_y1731_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_ptp_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_ptp_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_ptp_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_ptp_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_y1731_insert_ts_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_y1731_insert_ts_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_mac_da_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_mac_da_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da0_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da0_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da1_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da1_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da2_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da2_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da0_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da0_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da1_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da1_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da0_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da0_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da1_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da1_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da2_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da2_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da3_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da3_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da4_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da4_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da5_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da5_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da6_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da6_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da7_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da7_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_lengthtype_reg_length_type_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_lengthtype_reg_length_type_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_layer4_protocol_reg_l4_protocol_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_layer4_protocol_reg_l4_protocol_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_filt_udp_port_reg_udp_port_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_filt_udp_port_reg_udp_port_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_ptp_pdelay_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_ptp_pdelay_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_da_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_da_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_pdelay_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_pdelay_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_lengthtype_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_lengthtype_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_udp_dport_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_udp_dport_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_layer4_protocol_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_layer4_protocol_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_udp_ptp_event_dport_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_udp_ptp_event_dport_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_da_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_da_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_prim_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_prim_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_da_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_da_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_pdelay_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_pdelay_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_prim_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_prim_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_next_header_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_next_header_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_y1731_mach_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_y1731_mach_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_ptp_prim_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_ptp_prim_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp0_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp0_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp1_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp1_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp2_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp2_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp3_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp3_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp4_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp4_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_reg_frac_nano_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_reg_frac_nano_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre0_reg_com_ts_pre_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre0_reg_com_ts_pre_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre1_reg_com_ts_pre_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre1_reg_com_ts_pre_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre2_reg_com_ts_pre_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre2_reg_com_ts_pre_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre3_reg_com_ts_pre_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre3_reg_com_ts_pre_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre4_reg_com_ts_pre_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre4_reg_com_ts_pre_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_pre_reg_frac_nano_pre_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_pre_reg_frac_nano_pre_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_reg_identify_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_reg_identify_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_pre_reg_identify_pre_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_pre_reg_identify_pre_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_da_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_da_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_mac_lengthtype_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_mac_lengthtype_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_da_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_da_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_pw_mac_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_pw_mac_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_udp_ptp_event_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_udp_ptp_event_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_udp_dport_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_udp_dport_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_mac_ptp_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_mac_ptp_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_next_header_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_next_header_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_y1731_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_y1731_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_ptp_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_ptp_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_ptp_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_ptp_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_y1731_insert_ts_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_y1731_insert_ts_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_mac_da_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_mac_da_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_y1731_sa_chk_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_y1731_sa_chk_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da0_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da0_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da1_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da1_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da2_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da2_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da0_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da0_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da1_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da1_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da0_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da0_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da1_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da1_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da2_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da2_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da3_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da3_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da4_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da4_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da5_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da5_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da6_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da6_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da7_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da7_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_lengthtype_reg_length_type_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_lengthtype_reg_length_type_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_layer4_protocol_reg_l4_protocol_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_layer4_protocol_reg_l4_protocol_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_filt_udp_port_reg_udp_port_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_filt_udp_port_reg_udp_port_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_ptp_pdelay_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_ptp_pdelay_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_da_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_da_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_pdelay_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_pdelay_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_lengthtype_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_lengthtype_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_udp_dport_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_udp_dport_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_layer4_protocol_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_layer4_protocol_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_udp_ptp_event_dport_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_udp_ptp_event_dport_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_da_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_da_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_prim_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_prim_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_da_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_da_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_pdelay_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_pdelay_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_prim_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_prim_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_next_header_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_next_header_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_y1731_mach_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_y1731_mach_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_ptp_prim_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_ptp_prim_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp0_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp0_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp1_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp1_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp2_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp2_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp3_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp3_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp4_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp4_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_com_frac_nano_reg_frac_nano_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_com_frac_nano_reg_frac_nano_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_y1731_identify_reg_identify_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_y1731_identify_reg_identify_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_y1731_dm_control_reg_y1731_dmm_lpbk_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_y1731_dm_control_reg_y1731_dmm_lpbk_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_y1731_dm_control_reg_valid_msg_lev_bmp_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_y1731_dm_control_reg_valid_msg_lev_bmp_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_baud_config_reg_baud_rate_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_baud_config_reg_baud_rate_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_start_polarity_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_start_polarity_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_msb_first_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_msb_first_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_parity_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_parity_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_auto_tod_out_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_auto_tod_out_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_auto_tod_in_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_auto_tod_in_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_reset_buffer_reg_reset_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_reset_buffer_reg_reset_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_almost_empty_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_almost_empty_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_almost_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_almost_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_half_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_half_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_almost_empty_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_almost_empty_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_almost_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_almost_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_half_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_half_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_data_present_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_data_present_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_tx_buffer_write_reg_tx_buffer_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_tx_buffer_write_reg_tx_buffer_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_data_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_data_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_empty_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_empty_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_half_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_half_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_data_present_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_data_present_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_loc_mac_addr_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_loc_mac_addr_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_loc_mac_addr_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_loc_mac_addr_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_loc_mac_addr_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_loc_mac_addr_2_reg_u *value);
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_0_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_0_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_1_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_1_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_2_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_2_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_link_delay_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_link_delay_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_link_delay_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_link_delay_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_link_delay_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_link_delay_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_link_delay_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_link_delay_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_link_delay_0_reg_link_delay_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_link_delay_0_reg_link_delay_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_link_delay_1_reg_link_delay_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value);
+
+sw_error_t
+qca808x_ptp_link_delay_1_reg_link_delay_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int value);
+
+sw_error_t
+qca808x_ptp_misc_control_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_misc_control_reg_u *value);
+
+sw_error_t
+qca808x_ptp_misc_control_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_misc_control_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ingress_asymmetry_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ingress_asymmetry_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ingress_asymmetry_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ingress_asymmetry_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ingress_asymmetry_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ingress_asymmetry_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_ingress_asymmetry_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ingress_asymmetry_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_egress_asymmetry_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_egress_asymmetry_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_egress_asymmetry_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_egress_asymmetry_0_reg_u *value);
+
+sw_error_t
+qca808x_ptp_egress_asymmetry_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_egress_asymmetry_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_egress_asymmetry_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_egress_asymmetry_1_reg_u *value);
+
+sw_error_t
+qca808x_ptp_backup_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_backup_reg_u *value);
+
+sw_error_t
+qca808x_ptp_backup_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_backup_reg_u *value);
+
+#endif
+
diff --git a/qca-ssdk/include/hsl/phy/qca808x_ptp_reg.h b/qca-ssdk/include/hsl/phy/qca808x_ptp_reg.h
new file mode 100755
index 0000000..4e8c4c0
--- /dev/null
+++ b/qca-ssdk/include/hsl/phy/qca808x_ptp_reg.h
@@ -0,0 +1,5853 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef PTP_REG_REG_H
+#define PTP_REG_REG_H
+
+#define PTP_REG_BIT_FALSE 0
+#define PTP_REG_BIT_TRUE  1
+
+/*[register] PTP_IMR_REG*/
+#define PTP_IMR_REG
+#define PTP_IMR_REG_ADDRESS 0x12
+#define PTP_IMR_REG_NUM     1
+#define PTP_IMR_REG_INC     0x1
+#define PTP_IMR_REG_TYPE    REG_TYPE_RW
+#define PTP_IMR_REG_DEFAULT 0x0
+	/*[field] MASK_BMP*/
+	#define PTP_IMR_REG_MASK_BMP
+	#define PTP_IMR_REG_MASK_BMP_OFFSET  0
+	#define PTP_IMR_REG_MASK_BMP_LEN     16
+	#define PTP_IMR_REG_MASK_BMP_DEFAULT 0x0
+
+struct ptp_imr_reg {
+	a_uint16_t  mask_bmp:16;
+};
+
+union ptp_imr_reg_u {
+	a_uint32_t val;
+	struct ptp_imr_reg bf;
+};
+
+/*[register] PTP_ISR_REG*/
+#define PTP_ISR_REG
+#define PTP_ISR_REG_ADDRESS 0x13
+#define PTP_ISR_REG_NUM     1
+#define PTP_ISR_REG_INC     0x1
+#define PTP_ISR_REG_TYPE    REG_TYPE_RW
+#define PTP_ISR_REG_DEFAULT 0x0
+	/*[field] STATUS_BMP*/
+	#define PTP_ISR_REG_STATUS_BMP
+	#define PTP_ISR_REG_STATUS_BMP_OFFSET  0
+	#define PTP_ISR_REG_STATUS_BMP_LEN     16
+	#define PTP_ISR_REG_STATUS_BMP_DEFAULT 0x0
+
+struct ptp_isr_reg {
+	a_uint16_t  status_bmp:16;
+};
+
+union ptp_isr_reg_u {
+	a_uint32_t val;
+	struct ptp_isr_reg bf;
+};
+
+/*[register] PTP_HW_ENABLE_REG*/
+#define PTP_HW_ENABLE_REG
+#define PTP_HW_ENABLE_REG_ADDRESS 0x1f
+#define PTP_HW_ENABLE_REG_NUM     1
+#define PTP_HW_ENABLE_REG_INC     0x1
+#define PTP_HW_ENABLE_REG_TYPE    REG_TYPE_RW
+#define PTP_HW_ENABLE_REG_DEFAULT 0x0
+	/*[field] PTP_HW_ENABLE*/
+	#define PTP_HW_ENABLE_REG_PTP_HW_ENABLE
+	#define PTP_HW_ENABLE_REG_PTP_HW_ENABLE_OFFSET  1
+	#define PTP_HW_ENABLE_REG_PTP_HW_ENABLE_LEN     1
+	#define PTP_HW_ENABLE_REG_PTP_HW_ENABLE_DEFAULT 0x0
+
+struct ptp_hw_enable_reg {
+	a_uint16_t  _reserved0:1;
+	a_uint16_t  ptp_hw_enable:1;
+};
+
+union ptp_hw_enable_reg_u {
+	a_uint32_t val;
+	struct ptp_hw_enable_reg bf;
+};
+
+/*[register] PTP_MAIN_CONF_REG*/
+#define PTP_MAIN_CONF_REG
+#define PTP_MAIN_CONF_REG_ADDRESS 0x8012
+#define PTP_MAIN_CONF_REG_NUM     1
+#define PTP_MAIN_CONF_REG_INC     0x1
+#define PTP_MAIN_CONF_REG_TYPE    REG_TYPE_RW
+#define PTP_MAIN_CONF_REG_DEFAULT 0x0
+	/*[field] PTP_CLOCK_MODE*/
+	#define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE
+	#define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_OFFSET  1
+	#define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_LEN     2
+	#define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_DEFAULT 0x0
+	#define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_OC_TWO_STEP 0x0
+	#define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_OC_ONE_STEP 0x1
+	#define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_TC_TWO_STEP 0x2
+	#define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_TC_ONE_STEP 0x3
+	/*[field] PTP_BYPASS*/
+	#define PTP_MAIN_CONF_REG_PTP_BYPASS
+	#define PTP_MAIN_CONF_REG_PTP_BYPASS_OFFSET  3
+	#define PTP_MAIN_CONF_REG_PTP_BYPASS_LEN     1
+	#define PTP_MAIN_CONF_REG_PTP_BYPASS_DEFAULT 0x0
+	/*[field] TS_ATTACH_MODE*/
+	#define PTP_MAIN_CONF_REG_TS_ATTACH_MODE
+	#define PTP_MAIN_CONF_REG_TS_ATTACH_MODE_OFFSET  4
+	#define PTP_MAIN_CONF_REG_TS_ATTACH_MODE_LEN     1
+	#define PTP_MAIN_CONF_REG_TS_ATTACH_MODE_DEFAULT 0x0
+	/*[field] WOL_EN*/
+	#define PTP_MAIN_CONF_REG_WOL_EN
+	#define PTP_MAIN_CONF_REG_WOL_EN_OFFSET  5
+	#define PTP_MAIN_CONF_REG_WOL_EN_LEN     1
+	#define PTP_MAIN_CONF_REG_WOL_EN_DEFAULT 0x0
+	/*[field] PTP_CLK_SEL*/
+	#define PTP_MAIN_CONF_REG_PTP_CLK_SEL
+	#define PTP_MAIN_CONF_REG_PTP_CLK_SEL_OFFSET  7
+	#define PTP_MAIN_CONF_REG_PTP_CLK_SEL_LEN     1
+	#define PTP_MAIN_CONF_REG_PTP_CLK_SEL_DEFAULT 0x0
+	/*[field] DISABLE_1588_PHY*/
+	#define PTP_MAIN_CONF_REG_DISABLE_1588_PHY
+	#define PTP_MAIN_CONF_REG_DISABLE_1588_PHY_OFFSET  8
+	#define PTP_MAIN_CONF_REG_DISABLE_1588_PHY_LEN     1
+	#define PTP_MAIN_CONF_REG_DISABLE_1588_PHY_DEFAULT 0x0
+	/*[field] ATTACH_CRC_RECAL*/
+	#define PTP_MAIN_CONF_REG_ATTACH_CRC_RECAL
+	#define PTP_MAIN_CONF_REG_ATTACH_CRC_RECAL_OFFSET  9
+	#define PTP_MAIN_CONF_REG_ATTACH_CRC_RECAL_LEN     1
+	#define PTP_MAIN_CONF_REG_ATTACH_CRC_RECAL_DEFAULT 0x0
+	/*[field] IPV4_FORCE_CHECKSUM_ZERO*/
+	#define PTP_MAIN_CONF_REG_IPV4_FORCE_CHECKSUM_ZERO
+	#define PTP_MAIN_CONF_REG_IPV4_FORCE_CHECKSUM_ZERO_OFFSET  10
+	#define PTP_MAIN_CONF_REG_IPV4_FORCE_CHECKSUM_ZERO_LEN     1
+	#define PTP_MAIN_CONF_REG_IPV4_FORCE_CHECKSUM_ZERO_DEFAULT 0x1
+	/*[field] IPV6_EMBED_FORCE_CHECKSUM_ZERO*/
+	#define PTP_MAIN_CONF_REG_IPV6_EMBED_FORCE_CHECKSUM_ZERO
+	#define PTP_MAIN_CONF_REG_IPV6_EMBED_FORCE_CHECKSUM_ZERO_OFFSET  11
+	#define PTP_MAIN_CONF_REG_IPV6_EMBED_FORCE_CHECKSUM_ZERO_LEN     1
+	#define PTP_MAIN_CONF_REG_IPV6_EMBED_FORCE_CHECKSUM_ZERO_DEFAULT 0x0
+
+struct ptp_main_conf_reg {
+	a_uint16_t  _reserved0:1;
+	a_uint16_t  ptp_clock_mode:2;
+	a_uint16_t  ptp_bypass:1;
+	a_uint16_t  ts_attach_mode:1;
+	a_uint16_t  wol_en:1;
+	a_uint16_t  _reserved1:1;
+	a_uint16_t  ptp_clk_sel:1;
+	a_uint16_t  disable_1588_phy:1;
+	a_uint16_t  attach_crc_recal:1;
+	a_uint16_t  ipv4_force_checksum_zero:1;
+	a_uint16_t  ipv6_embed_force_checksum_zero:1;
+};
+
+union ptp_main_conf_reg_u {
+	a_uint32_t val;
+	struct ptp_main_conf_reg bf;
+};
+
+/*[register] PTP_RX_SEQID0_REG*/
+#define PTP_RX_SEQID0_REG
+#define PTP_RX_SEQID0_REG_ADDRESS 0x8013
+#define PTP_RX_SEQID0_REG_NUM     1
+#define PTP_RX_SEQID0_REG_INC     0x1
+#define PTP_RX_SEQID0_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_SEQID0_REG_DEFAULT 0x0
+	/*[field] RX_SEQID*/
+	#define PTP_RX_SEQID0_REG_RX_SEQID
+	#define PTP_RX_SEQID0_REG_RX_SEQID_OFFSET  0
+	#define PTP_RX_SEQID0_REG_RX_SEQID_LEN     16
+	#define PTP_RX_SEQID0_REG_RX_SEQID_DEFAULT 0x0
+
+struct ptp_rx_seqid0_reg {
+	a_uint16_t  rx_seqid:16;
+};
+
+union ptp_rx_seqid0_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_seqid0_reg bf;
+};
+
+/*[register] PTP_RX_PORTID0_0_REG*/
+#define PTP_RX_PORTID0_0_REG
+#define PTP_RX_PORTID0_0_REG_ADDRESS 0x8014
+#define PTP_RX_PORTID0_0_REG_NUM     1
+#define PTP_RX_PORTID0_0_REG_INC     0x1
+#define PTP_RX_PORTID0_0_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID0_0_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID0_0_REG_RX_PORTID
+	#define PTP_RX_PORTID0_0_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID0_0_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID0_0_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid0_0_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid0_0_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid0_0_reg bf;
+};
+
+/*[register] PTP_RX_PORTID0_1_REG*/
+#define PTP_RX_PORTID0_1_REG
+#define PTP_RX_PORTID0_1_REG_ADDRESS 0x8015
+#define PTP_RX_PORTID0_1_REG_NUM     1
+#define PTP_RX_PORTID0_1_REG_INC     0x1
+#define PTP_RX_PORTID0_1_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID0_1_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID0_1_REG_RX_PORTID
+	#define PTP_RX_PORTID0_1_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID0_1_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID0_1_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid0_1_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid0_1_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid0_1_reg bf;
+};
+
+/*[register] PTP_RX_PORTID0_2_REG*/
+#define PTP_RX_PORTID0_2_REG
+#define PTP_RX_PORTID0_2_REG_ADDRESS 0x8016
+#define PTP_RX_PORTID0_2_REG_NUM     1
+#define PTP_RX_PORTID0_2_REG_INC     0x1
+#define PTP_RX_PORTID0_2_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID0_2_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID0_2_REG_RX_PORTID
+	#define PTP_RX_PORTID0_2_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID0_2_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID0_2_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid0_2_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid0_2_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid0_2_reg bf;
+};
+
+/*[register] PTP_RX_PORTID0_3_REG*/
+#define PTP_RX_PORTID0_3_REG
+#define PTP_RX_PORTID0_3_REG_ADDRESS 0x8017
+#define PTP_RX_PORTID0_3_REG_NUM     1
+#define PTP_RX_PORTID0_3_REG_INC     0x1
+#define PTP_RX_PORTID0_3_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID0_3_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID0_3_REG_RX_PORTID
+	#define PTP_RX_PORTID0_3_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID0_3_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID0_3_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid0_3_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid0_3_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid0_3_reg bf;
+};
+
+/*[register] PTP_RX_PORTID0_4_REG*/
+#define PTP_RX_PORTID0_4_REG
+#define PTP_RX_PORTID0_4_REG_ADDRESS 0x8018
+#define PTP_RX_PORTID0_4_REG_NUM     1
+#define PTP_RX_PORTID0_4_REG_INC     0x1
+#define PTP_RX_PORTID0_4_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID0_4_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID0_4_REG_RX_PORTID
+	#define PTP_RX_PORTID0_4_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID0_4_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID0_4_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid0_4_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid0_4_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid0_4_reg bf;
+};
+
+
+//
+/*[register] PTP_RTC_CLK_REG*/
+#define PTP_RTC_CLK_REG
+#define PTP_RTC_CLK_REG_ADDRESS 0x8017
+#define PTP_RTC_CLK_REG_NUM     1
+#define PTP_RTC_CLK_REG_INC     0x1
+#define PTP_RTC_CLK_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC_CLK_REG_DEFAULT 0x0
+	/*[field] RTC_CLK_SELECTION*/
+	#define PTP_RTC_CLK_REG_RTC_CLK_SELECTION
+	#define PTP_RTC_CLK_REG_RTC_CLK_SELECTION_OFFSET  11
+	#define PTP_RTC_CLK_REG_RTC_CLK_SELECTION_LEN     1
+	#define PTP_RTC_CLK_REG_RTC_CLK_SELECTION_DEFAULT 0x0
+
+struct ptp_rtc_clk_reg {
+	a_uint16_t  _reserved0:11;
+	a_uint16_t  rtc_clk_selection:1;
+};
+
+union ptp_rtc_clk_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc_clk_reg bf;
+};
+
+/*[register] PTP_RX_TS0_0_REG*/
+#define PTP_RX_TS0_0_REG
+#define PTP_RX_TS0_0_REG_ADDRESS 0x8019
+#define PTP_RX_TS0_0_REG_NUM     1
+#define PTP_RX_TS0_0_REG_INC     0x1
+#define PTP_RX_TS0_0_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS0_0_REG_DEFAULT 0x0
+	/*[field] RX_TS_SEC*/
+	#define PTP_RX_TS0_0_REG_RX_TS_SEC
+	#define PTP_RX_TS0_0_REG_RX_TS_SEC_OFFSET  0
+	#define PTP_RX_TS0_0_REG_RX_TS_SEC_LEN     16
+	#define PTP_RX_TS0_0_REG_RX_TS_SEC_DEFAULT 0x0
+
+struct ptp_rx_ts0_0_reg {
+	a_uint16_t  rx_ts_sec:16;
+};
+
+union ptp_rx_ts0_0_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts0_0_reg bf;
+};
+
+/*[register] PTP_RX_TS0_1_REG*/
+#define PTP_RX_TS0_1_REG
+#define PTP_RX_TS0_1_REG_ADDRESS 0x801a
+#define PTP_RX_TS0_1_REG_NUM     1
+#define PTP_RX_TS0_1_REG_INC     0x1
+#define PTP_RX_TS0_1_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS0_1_REG_DEFAULT 0x0
+	/*[field] RX_TS_SEC*/
+	#define PTP_RX_TS0_1_REG_RX_TS_SEC
+	#define PTP_RX_TS0_1_REG_RX_TS_SEC_OFFSET  0
+	#define PTP_RX_TS0_1_REG_RX_TS_SEC_LEN     16
+	#define PTP_RX_TS0_1_REG_RX_TS_SEC_DEFAULT 0x0
+
+struct ptp_rx_ts0_1_reg {
+	a_uint16_t  rx_ts_sec:16;
+};
+
+union ptp_rx_ts0_1_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts0_1_reg bf;
+};
+
+/*[register] PTP_RX_TS0_2_REG*/
+#define PTP_RX_TS0_2_REG
+#define PTP_RX_TS0_2_REG_ADDRESS 0x801b
+#define PTP_RX_TS0_2_REG_NUM     1
+#define PTP_RX_TS0_2_REG_INC     0x1
+#define PTP_RX_TS0_2_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS0_2_REG_DEFAULT 0x0
+	/*[field] RX_TS_SEC*/
+	#define PTP_RX_TS0_2_REG_RX_TS_SEC
+	#define PTP_RX_TS0_2_REG_RX_TS_SEC_OFFSET  0
+	#define PTP_RX_TS0_2_REG_RX_TS_SEC_LEN     16
+	#define PTP_RX_TS0_2_REG_RX_TS_SEC_DEFAULT 0x0
+
+struct ptp_rx_ts0_2_reg {
+	a_uint16_t  rx_ts_sec:16;
+};
+
+union ptp_rx_ts0_2_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts0_2_reg bf;
+};
+
+/*[register] PTP_RX_TS0_3_REG*/
+#define PTP_RX_TS0_3_REG
+#define PTP_RX_TS0_3_REG_ADDRESS 0x801c
+#define PTP_RX_TS0_3_REG_NUM     1
+#define PTP_RX_TS0_3_REG_INC     0x1
+#define PTP_RX_TS0_3_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS0_3_REG_DEFAULT 0x0
+	/*[field] RX_TS_NSEC*/
+	#define PTP_RX_TS0_3_REG_RX_TS_NSEC
+	#define PTP_RX_TS0_3_REG_RX_TS_NSEC_OFFSET  0
+	#define PTP_RX_TS0_3_REG_RX_TS_NSEC_LEN     16
+	#define PTP_RX_TS0_3_REG_RX_TS_NSEC_DEFAULT 0x0
+
+struct ptp_rx_ts0_3_reg {
+	a_uint16_t  rx_ts_nsec:16;
+};
+
+union ptp_rx_ts0_3_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts0_3_reg bf;
+};
+
+/*[register] PTP_RX_TS0_4_REG*/
+#define PTP_RX_TS0_4_REG
+#define PTP_RX_TS0_4_REG_ADDRESS 0x801d
+#define PTP_RX_TS0_4_REG_NUM     1
+#define PTP_RX_TS0_4_REG_INC     0x1
+#define PTP_RX_TS0_4_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS0_4_REG_DEFAULT 0x0
+	/*[field] RX_TS_NSEC*/
+	#define PTP_RX_TS0_4_REG_RX_TS_NSEC
+	#define PTP_RX_TS0_4_REG_RX_TS_NSEC_OFFSET  0
+	#define PTP_RX_TS0_4_REG_RX_TS_NSEC_LEN     16
+	#define PTP_RX_TS0_4_REG_RX_TS_NSEC_DEFAULT 0x0
+
+struct ptp_rx_ts0_4_reg {
+	a_uint16_t  rx_ts_nsec:16;
+};
+
+union ptp_rx_ts0_4_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts0_4_reg bf;
+};
+
+/*[register] PTP_RX_TS0_5_REG*/
+#define PTP_RX_TS0_5_REG
+#define PTP_RX_TS0_5_REG_ADDRESS 0x801e
+#define PTP_RX_TS0_5_REG_NUM     1
+#define PTP_RX_TS0_5_REG_INC     0x1
+#define PTP_RX_TS0_5_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS0_5_REG_DEFAULT 0x0
+	/*[field] RX_TS_NFSEC*/
+	#define PTP_RX_TS0_5_REG_RX_TS_NFSEC
+	#define PTP_RX_TS0_5_REG_RX_TS_NFSEC_OFFSET  0
+	#define PTP_RX_TS0_5_REG_RX_TS_NFSEC_LEN     12
+	#define PTP_RX_TS0_5_REG_RX_TS_NFSEC_DEFAULT 0x0
+	/*[field] RX_MSG_TYPE*/
+	#define PTP_RX_TS0_5_REG_RX_MSG_TYPE
+	#define PTP_RX_TS0_5_REG_RX_MSG_TYPE_OFFSET  12
+	#define PTP_RX_TS0_5_REG_RX_MSG_TYPE_LEN     4
+	#define PTP_RX_TS0_5_REG_RX_MSG_TYPE_DEFAULT 0x0
+
+struct ptp_rx_ts0_5_reg {
+	a_uint16_t  rx_ts_nfsec:12;
+	a_uint16_t  rx_msg_type:4;
+};
+
+union ptp_rx_ts0_5_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts0_5_reg bf;
+};
+
+/*[register] PTP_RX_TS0_6_REG*/
+#define PTP_RX_TS0_6_REG
+#define PTP_RX_TS0_6_REG_ADDRESS 0x801f
+#define PTP_RX_TS0_6_REG_NUM     1
+#define PTP_RX_TS0_6_REG_INC     0x1
+#define PTP_RX_TS0_6_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS0_6_REG_DEFAULT 0x0
+	/*[field] RX_TS_NFSEC*/
+	#define PTP_RX_TS0_6_REG_RX_TS_NFSEC
+	#define PTP_RX_TS0_6_REG_RX_TS_NFSEC_OFFSET  0
+	#define PTP_RX_TS0_6_REG_RX_TS_NFSEC_LEN     8
+	#define PTP_RX_TS0_6_REG_RX_TS_NFSEC_DEFAULT 0x0
+
+struct ptp_rx_ts0_6_reg {
+	a_uint16_t  rx_ts_nfsec:8;
+};
+
+union ptp_rx_ts0_6_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts0_6_reg bf;
+};
+
+/*[register] PTP_TX_SEQID_REG*/
+#define PTP_TX_SEQID_REG
+#define PTP_TX_SEQID_REG_ADDRESS 0x8020
+#define PTP_TX_SEQID_REG_NUM     1
+#define PTP_TX_SEQID_REG_INC     0x1
+#define PTP_TX_SEQID_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_SEQID_REG_DEFAULT 0x0
+	/*[field] TX_SEQID*/
+	#define PTP_TX_SEQID_REG_TX_SEQID
+	#define PTP_TX_SEQID_REG_TX_SEQID_OFFSET  0
+	#define PTP_TX_SEQID_REG_TX_SEQID_LEN     16
+	#define PTP_TX_SEQID_REG_TX_SEQID_DEFAULT 0x0
+
+struct ptp_tx_seqid_reg {
+	a_uint16_t  tx_seqid:16;
+};
+
+union ptp_tx_seqid_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_seqid_reg bf;
+};
+
+/*[register] PTP_TX_PORTID0_REG*/
+#define PTP_TX_PORTID0_REG
+#define PTP_TX_PORTID0_REG_ADDRESS 0x8021
+#define PTP_TX_PORTID0_REG_NUM     1
+#define PTP_TX_PORTID0_REG_INC     0x1
+#define PTP_TX_PORTID0_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_PORTID0_REG_DEFAULT 0x0
+	/*[field] TX_PORTID*/
+	#define PTP_TX_PORTID0_REG_TX_PORTID
+	#define PTP_TX_PORTID0_REG_TX_PORTID_OFFSET  0
+	#define PTP_TX_PORTID0_REG_TX_PORTID_LEN     16
+	#define PTP_TX_PORTID0_REG_TX_PORTID_DEFAULT 0x0
+
+struct ptp_tx_portid0_reg {
+	a_uint16_t  tx_portid:16;
+};
+
+union ptp_tx_portid0_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_portid0_reg bf;
+};
+
+/*[register] PTP_TX_PORTID1_REG*/
+#define PTP_TX_PORTID1_REG
+#define PTP_TX_PORTID1_REG_ADDRESS 0x8022
+#define PTP_TX_PORTID1_REG_NUM     1
+#define PTP_TX_PORTID1_REG_INC     0x1
+#define PTP_TX_PORTID1_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_PORTID1_REG_DEFAULT 0x0
+	/*[field] TX_PORTID*/
+	#define PTP_TX_PORTID1_REG_TX_PORTID
+	#define PTP_TX_PORTID1_REG_TX_PORTID_OFFSET  0
+	#define PTP_TX_PORTID1_REG_TX_PORTID_LEN     16
+	#define PTP_TX_PORTID1_REG_TX_PORTID_DEFAULT 0x0
+
+struct ptp_tx_portid1_reg {
+	a_uint16_t  tx_portid:16;
+};
+
+union ptp_tx_portid1_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_portid1_reg bf;
+};
+
+/*[register] PTP_TX_PORTID2_REG*/
+#define PTP_TX_PORTID2_REG
+#define PTP_TX_PORTID2_REG_ADDRESS 0x8023
+#define PTP_TX_PORTID2_REG_NUM     1
+#define PTP_TX_PORTID2_REG_INC     0x1
+#define PTP_TX_PORTID2_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_PORTID2_REG_DEFAULT 0x0
+	/*[field] TX_PORTID*/
+	#define PTP_TX_PORTID2_REG_TX_PORTID
+	#define PTP_TX_PORTID2_REG_TX_PORTID_OFFSET  0
+	#define PTP_TX_PORTID2_REG_TX_PORTID_LEN     16
+	#define PTP_TX_PORTID2_REG_TX_PORTID_DEFAULT 0x0
+
+struct ptp_tx_portid2_reg {
+	a_uint16_t  tx_portid:16;
+};
+
+union ptp_tx_portid2_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_portid2_reg bf;
+};
+
+/*[register] PTP_TX_PORTID3_REG*/
+#define PTP_TX_PORTID3_REG
+#define PTP_TX_PORTID3_REG_ADDRESS 0x8024
+#define PTP_TX_PORTID3_REG_NUM     1
+#define PTP_TX_PORTID3_REG_INC     0x1
+#define PTP_TX_PORTID3_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_PORTID3_REG_DEFAULT 0x0
+	/*[field] TX_PORTID*/
+	#define PTP_TX_PORTID3_REG_TX_PORTID
+	#define PTP_TX_PORTID3_REG_TX_PORTID_OFFSET  0
+	#define PTP_TX_PORTID3_REG_TX_PORTID_LEN     16
+	#define PTP_TX_PORTID3_REG_TX_PORTID_DEFAULT 0x0
+
+struct ptp_tx_portid3_reg {
+	a_uint16_t  tx_portid:16;
+};
+
+union ptp_tx_portid3_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_portid3_reg bf;
+};
+
+/*[register] PTP_TX_PORTID4_REG*/
+#define PTP_TX_PORTID4_REG
+#define PTP_TX_PORTID4_REG_ADDRESS 0x8025
+#define PTP_TX_PORTID4_REG_NUM     1
+#define PTP_TX_PORTID4_REG_INC     0x1
+#define PTP_TX_PORTID4_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_PORTID4_REG_DEFAULT 0x0
+	/*[field] TX_PORTID*/
+	#define PTP_TX_PORTID4_REG_TX_PORTID
+	#define PTP_TX_PORTID4_REG_TX_PORTID_OFFSET  0
+	#define PTP_TX_PORTID4_REG_TX_PORTID_LEN     16
+	#define PTP_TX_PORTID4_REG_TX_PORTID_DEFAULT 0x0
+
+struct ptp_tx_portid4_reg {
+	a_uint16_t  tx_portid:16;
+};
+
+union ptp_tx_portid4_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_portid4_reg bf;
+};
+
+/*[register] PTP_TX_TS0_REG*/
+#define PTP_TX_TS0_REG
+#define PTP_TX_TS0_REG_ADDRESS 0x8026
+#define PTP_TX_TS0_REG_NUM     1
+#define PTP_TX_TS0_REG_INC     0x1
+#define PTP_TX_TS0_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_TS0_REG_DEFAULT 0x0
+	/*[field] TX_TS_SEC*/
+	#define PTP_TX_TS0_REG_TX_TS_SEC
+	#define PTP_TX_TS0_REG_TX_TS_SEC_OFFSET  0
+	#define PTP_TX_TS0_REG_TX_TS_SEC_LEN     16
+	#define PTP_TX_TS0_REG_TX_TS_SEC_DEFAULT 0x0
+
+struct ptp_tx_ts0_reg {
+	a_uint16_t  tx_ts_sec:16;
+};
+
+union ptp_tx_ts0_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_ts0_reg bf;
+};
+
+/*[register] PTP_TX_TS1_REG*/
+#define PTP_TX_TS1_REG
+#define PTP_TX_TS1_REG_ADDRESS 0x8027
+#define PTP_TX_TS1_REG_NUM     1
+#define PTP_TX_TS1_REG_INC     0x1
+#define PTP_TX_TS1_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_TS1_REG_DEFAULT 0x0
+	/*[field] TX_TS_SEC*/
+	#define PTP_TX_TS1_REG_TX_TS_SEC
+	#define PTP_TX_TS1_REG_TX_TS_SEC_OFFSET  0
+	#define PTP_TX_TS1_REG_TX_TS_SEC_LEN     16
+	#define PTP_TX_TS1_REG_TX_TS_SEC_DEFAULT 0x0
+
+struct ptp_tx_ts1_reg {
+	a_uint16_t  tx_ts_sec:16;
+};
+
+union ptp_tx_ts1_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_ts1_reg bf;
+};
+
+/*[register] PTP_TX_TS2_REG*/
+#define PTP_TX_TS2_REG
+#define PTP_TX_TS2_REG_ADDRESS 0x8028
+#define PTP_TX_TS2_REG_NUM     1
+#define PTP_TX_TS2_REG_INC     0x1
+#define PTP_TX_TS2_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_TS2_REG_DEFAULT 0x0
+	/*[field] TX_TS_SEC*/
+	#define PTP_TX_TS2_REG_TX_TS_SEC
+	#define PTP_TX_TS2_REG_TX_TS_SEC_OFFSET  0
+	#define PTP_TX_TS2_REG_TX_TS_SEC_LEN     16
+	#define PTP_TX_TS2_REG_TX_TS_SEC_DEFAULT 0x0
+
+struct ptp_tx_ts2_reg {
+	a_uint16_t  tx_ts_sec:16;
+};
+
+union ptp_tx_ts2_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_ts2_reg bf;
+};
+
+/*[register] PTP_TX_TS3_REG*/
+#define PTP_TX_TS3_REG
+#define PTP_TX_TS3_REG_ADDRESS 0x8029
+#define PTP_TX_TS3_REG_NUM     1
+#define PTP_TX_TS3_REG_INC     0x1
+#define PTP_TX_TS3_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_TS3_REG_DEFAULT 0x0
+	/*[field] TX_TS_NSEC*/
+	#define PTP_TX_TS3_REG_TX_TS_NSEC
+	#define PTP_TX_TS3_REG_TX_TS_NSEC_OFFSET  0
+	#define PTP_TX_TS3_REG_TX_TS_NSEC_LEN     16
+	#define PTP_TX_TS3_REG_TX_TS_NSEC_DEFAULT 0x0
+
+struct ptp_tx_ts3_reg {
+	a_uint16_t  tx_ts_nsec:16;
+};
+
+union ptp_tx_ts3_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_ts3_reg bf;
+};
+
+/*[register] PTP_TX_TS4_REG*/
+#define PTP_TX_TS4_REG
+#define PTP_TX_TS4_REG_ADDRESS 0x802a
+#define PTP_TX_TS4_REG_NUM     1
+#define PTP_TX_TS4_REG_INC     0x1
+#define PTP_TX_TS4_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_TS4_REG_DEFAULT 0x0
+	/*[field] TX_TS_NSEC*/
+	#define PTP_TX_TS4_REG_TX_TS_NSEC
+	#define PTP_TX_TS4_REG_TX_TS_NSEC_OFFSET  0
+	#define PTP_TX_TS4_REG_TX_TS_NSEC_LEN     16
+	#define PTP_TX_TS4_REG_TX_TS_NSEC_DEFAULT 0x0
+
+struct ptp_tx_ts4_reg {
+	a_uint16_t  tx_ts_nsec:16;
+};
+
+union ptp_tx_ts4_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_ts4_reg bf;
+};
+
+/*[register] PTP_TX_TS5_REG*/
+#define PTP_TX_TS5_REG
+#define PTP_TX_TS5_REG_ADDRESS 0x802b
+#define PTP_TX_TS5_REG_NUM     1
+#define PTP_TX_TS5_REG_INC     0x1
+#define PTP_TX_TS5_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_TS5_REG_DEFAULT 0x0
+	/*[field] TX_TS_NFSEC*/
+	#define PTP_TX_TS5_REG_TX_TS_NFSEC
+	#define PTP_TX_TS5_REG_TX_TS_NFSEC_OFFSET  0
+	#define PTP_TX_TS5_REG_TX_TS_NFSEC_LEN     12
+	#define PTP_TX_TS5_REG_TX_TS_NFSEC_DEFAULT 0x0
+	/*[field] TX_MSG_TYPE*/
+	#define PTP_TX_TS5_REG_TX_MSG_TYPE
+	#define PTP_TX_TS5_REG_TX_MSG_TYPE_OFFSET  12
+	#define PTP_TX_TS5_REG_TX_MSG_TYPE_LEN     4
+	#define PTP_TX_TS5_REG_TX_MSG_TYPE_DEFAULT 0x0
+
+struct ptp_tx_ts5_reg {
+	a_uint16_t  tx_ts_nfsec:12;
+	a_uint16_t  tx_msg_type:4;
+};
+
+union ptp_tx_ts5_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_ts5_reg bf;
+};
+
+/*[register] PTP_TX_TS6_REG*/
+#define PTP_TX_TS6_REG
+#define PTP_TX_TS6_REG_ADDRESS 0x802c
+#define PTP_TX_TS6_REG_NUM     1
+#define PTP_TX_TS6_REG_INC     0x1
+#define PTP_TX_TS6_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_TS6_REG_DEFAULT 0x0
+	/*[field] TX_TS_NFSEC*/
+	#define PTP_TX_TS6_REG_TX_TS_NFSEC
+	#define PTP_TX_TS6_REG_TX_TS_NFSEC_OFFSET  0
+	#define PTP_TX_TS6_REG_TX_TS_NFSEC_LEN     8
+	#define PTP_TX_TS6_REG_TX_TS_NFSEC_DEFAULT 0x0
+
+struct ptp_tx_ts6_reg {
+	a_uint16_t  tx_ts_nfsec:8;
+};
+
+union ptp_tx_ts6_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_ts6_reg bf;
+};
+
+/*[register] PTP_ORIG_CORR0_REG*/
+#define PTP_ORIG_CORR0_REG
+#define PTP_ORIG_CORR0_REG_ADDRESS 0x802d
+#define PTP_ORIG_CORR0_REG_NUM     1
+#define PTP_ORIG_CORR0_REG_INC     0x1
+#define PTP_ORIG_CORR0_REG_TYPE    REG_TYPE_RW
+#define PTP_ORIG_CORR0_REG_DEFAULT 0x0
+	/*[field] PTP_ORIG_CORR*/
+	#define PTP_ORIG_CORR0_REG_PTP_ORIG_CORR
+	#define PTP_ORIG_CORR0_REG_PTP_ORIG_CORR_OFFSET  0
+	#define PTP_ORIG_CORR0_REG_PTP_ORIG_CORR_LEN     16
+	#define PTP_ORIG_CORR0_REG_PTP_ORIG_CORR_DEFAULT 0x0
+
+struct ptp_orig_corr0_reg {
+	a_uint16_t  ptp_orig_corr:16;
+};
+
+union ptp_orig_corr0_reg_u {
+	a_uint32_t val;
+	struct ptp_orig_corr0_reg bf;
+};
+
+/*[register] PTP_ORIG_CORR1_REG*/
+#define PTP_ORIG_CORR1_REG
+#define PTP_ORIG_CORR1_REG_ADDRESS 0x802e
+#define PTP_ORIG_CORR1_REG_NUM     1
+#define PTP_ORIG_CORR1_REG_INC     0x1
+#define PTP_ORIG_CORR1_REG_TYPE    REG_TYPE_RW
+#define PTP_ORIG_CORR1_REG_DEFAULT 0x0
+	/*[field] PTP_ORIG_CORR*/
+	#define PTP_ORIG_CORR1_REG_PTP_ORIG_CORR
+	#define PTP_ORIG_CORR1_REG_PTP_ORIG_CORR_OFFSET  0
+	#define PTP_ORIG_CORR1_REG_PTP_ORIG_CORR_LEN     16
+	#define PTP_ORIG_CORR1_REG_PTP_ORIG_CORR_DEFAULT 0x0
+
+struct ptp_orig_corr1_reg {
+	a_uint16_t  ptp_orig_corr:16;
+};
+
+union ptp_orig_corr1_reg_u {
+	a_uint32_t val;
+	struct ptp_orig_corr1_reg bf;
+};
+
+/*[register] PTP_ORIG_CORR2_REG*/
+#define PTP_ORIG_CORR2_REG
+#define PTP_ORIG_CORR2_REG_ADDRESS 0x802f
+#define PTP_ORIG_CORR2_REG_NUM     1
+#define PTP_ORIG_CORR2_REG_INC     0x1
+#define PTP_ORIG_CORR2_REG_TYPE    REG_TYPE_RW
+#define PTP_ORIG_CORR2_REG_DEFAULT 0x0
+	/*[field] PTP_ORIG_CORR*/
+	#define PTP_ORIG_CORR2_REG_PTP_ORIG_CORR
+	#define PTP_ORIG_CORR2_REG_PTP_ORIG_CORR_OFFSET  0
+	#define PTP_ORIG_CORR2_REG_PTP_ORIG_CORR_LEN     16
+	#define PTP_ORIG_CORR2_REG_PTP_ORIG_CORR_DEFAULT 0x0
+
+struct ptp_orig_corr2_reg {
+	a_uint16_t  ptp_orig_corr:16;
+};
+
+union ptp_orig_corr2_reg_u {
+	a_uint32_t val;
+	struct ptp_orig_corr2_reg bf;
+};
+
+/*[register] PTP_ORIG_CORR3_REG*/
+#define PTP_ORIG_CORR3_REG
+#define PTP_ORIG_CORR3_REG_ADDRESS 0x8030
+#define PTP_ORIG_CORR3_REG_NUM     1
+#define PTP_ORIG_CORR3_REG_INC     0x1
+#define PTP_ORIG_CORR3_REG_TYPE    REG_TYPE_RW
+#define PTP_ORIG_CORR3_REG_DEFAULT 0x0
+	/*[field] PTP_ORIG_CORR*/
+	#define PTP_ORIG_CORR3_REG_PTP_ORIG_CORR
+	#define PTP_ORIG_CORR3_REG_PTP_ORIG_CORR_OFFSET  0
+	#define PTP_ORIG_CORR3_REG_PTP_ORIG_CORR_LEN     16
+	#define PTP_ORIG_CORR3_REG_PTP_ORIG_CORR_DEFAULT 0x0
+
+struct ptp_orig_corr3_reg {
+	a_uint16_t  ptp_orig_corr:16;
+};
+
+union ptp_orig_corr3_reg_u {
+	a_uint32_t val;
+	struct ptp_orig_corr3_reg bf;
+};
+
+/*[register] PTP_IN_TRIG0_REG*/
+#define PTP_IN_TRIG0_REG
+#define PTP_IN_TRIG0_REG_ADDRESS 0x8031
+#define PTP_IN_TRIG0_REG_NUM     1
+#define PTP_IN_TRIG0_REG_INC     0x1
+#define PTP_IN_TRIG0_REG_TYPE    REG_TYPE_RW
+#define PTP_IN_TRIG0_REG_DEFAULT 0x0
+	/*[field] PTP_IN_TRIG_NISEC*/
+	#define PTP_IN_TRIG0_REG_PTP_IN_TRIG_NISEC
+	#define PTP_IN_TRIG0_REG_PTP_IN_TRIG_NISEC_OFFSET  0
+	#define PTP_IN_TRIG0_REG_PTP_IN_TRIG_NISEC_LEN     16
+	#define PTP_IN_TRIG0_REG_PTP_IN_TRIG_NISEC_DEFAULT 0x0
+
+struct ptp_in_trig0_reg {
+	a_uint16_t  ptp_in_trig_nisec:16;
+};
+
+union ptp_in_trig0_reg_u {
+	a_uint32_t val;
+	struct ptp_in_trig0_reg bf;
+};
+
+/*[register] PTP_IN_TRIG1_REG*/
+#define PTP_IN_TRIG1_REG
+#define PTP_IN_TRIG1_REG_ADDRESS 0x8032
+#define PTP_IN_TRIG1_REG_NUM     1
+#define PTP_IN_TRIG1_REG_INC     0x1
+#define PTP_IN_TRIG1_REG_TYPE    REG_TYPE_RW
+#define PTP_IN_TRIG1_REG_DEFAULT 0x0
+	/*[field] PTP_IN_TRIG_NISEC*/
+	#define PTP_IN_TRIG1_REG_PTP_IN_TRIG_NISEC
+	#define PTP_IN_TRIG1_REG_PTP_IN_TRIG_NISEC_OFFSET  0
+	#define PTP_IN_TRIG1_REG_PTP_IN_TRIG_NISEC_LEN     16
+	#define PTP_IN_TRIG1_REG_PTP_IN_TRIG_NISEC_DEFAULT 0x0
+
+struct ptp_in_trig1_reg {
+	a_uint16_t  ptp_in_trig_nisec:16;
+};
+
+union ptp_in_trig1_reg_u {
+	a_uint32_t val;
+	struct ptp_in_trig1_reg bf;
+};
+
+/*[register] PTP_IN_TRIG2_REG*/
+#define PTP_IN_TRIG2_REG
+#define PTP_IN_TRIG2_REG_ADDRESS 0x8033
+#define PTP_IN_TRIG2_REG_NUM     1
+#define PTP_IN_TRIG2_REG_INC     0x1
+#define PTP_IN_TRIG2_REG_TYPE    REG_TYPE_RW
+#define PTP_IN_TRIG2_REG_DEFAULT 0x0
+	/*[field] PTP_IN_TRIG_NISEC*/
+	#define PTP_IN_TRIG2_REG_PTP_IN_TRIG_NISEC
+	#define PTP_IN_TRIG2_REG_PTP_IN_TRIG_NISEC_OFFSET  0
+	#define PTP_IN_TRIG2_REG_PTP_IN_TRIG_NISEC_LEN     16
+	#define PTP_IN_TRIG2_REG_PTP_IN_TRIG_NISEC_DEFAULT 0x0
+
+struct ptp_in_trig2_reg {
+	a_uint16_t  ptp_in_trig_nisec:16;
+};
+
+union ptp_in_trig2_reg_u {
+	a_uint32_t val;
+	struct ptp_in_trig2_reg bf;
+};
+
+/*[register] PTP_IN_TRIG3_REG*/
+#define PTP_IN_TRIG3_REG
+#define PTP_IN_TRIG3_REG_ADDRESS 0x8034
+#define PTP_IN_TRIG3_REG_NUM     1
+#define PTP_IN_TRIG3_REG_INC     0x1
+#define PTP_IN_TRIG3_REG_TYPE    REG_TYPE_RW
+#define PTP_IN_TRIG3_REG_DEFAULT 0x0
+	/*[field] PTP_IN_TRIG_NISEC*/
+	#define PTP_IN_TRIG3_REG_PTP_IN_TRIG_NISEC
+	#define PTP_IN_TRIG3_REG_PTP_IN_TRIG_NISEC_OFFSET  0
+	#define PTP_IN_TRIG3_REG_PTP_IN_TRIG_NISEC_LEN     4
+	#define PTP_IN_TRIG3_REG_PTP_IN_TRIG_NISEC_DEFAULT 0x0
+
+struct ptp_in_trig3_reg {
+	a_uint16_t  ptp_in_trig_nisec:4;
+};
+
+union ptp_in_trig3_reg_u {
+	a_uint32_t val;
+	struct ptp_in_trig3_reg bf;
+};
+
+/*[register] PTP_TX_LATENCY_REG*/
+#define PTP_TX_LATENCY_REG
+#define PTP_TX_LATENCY_REG_ADDRESS 0x8035
+#define PTP_TX_LATENCY_REG_NUM     1
+#define PTP_TX_LATENCY_REG_INC     0x1
+#define PTP_TX_LATENCY_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_LATENCY_REG_DEFAULT 0x0
+	/*[field] PTP_TX_LATENCY*/
+	#define PTP_TX_LATENCY_REG_PTP_TX_LATENCY
+	#define PTP_TX_LATENCY_REG_PTP_TX_LATENCY_OFFSET  0
+	#define PTP_TX_LATENCY_REG_PTP_TX_LATENCY_LEN     16
+	#define PTP_TX_LATENCY_REG_PTP_TX_LATENCY_DEFAULT 0x0
+
+struct ptp_tx_latency_reg {
+	a_uint16_t  ptp_tx_latency:16;
+};
+
+union ptp_tx_latency_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_latency_reg bf;
+};
+
+/*[register] PTP_RTC_INC0_REG*/
+#define PTP_RTC_INC0_REG
+#define PTP_RTC_INC0_REG_ADDRESS 0x8036
+#define PTP_RTC_INC0_REG_NUM     1
+#define PTP_RTC_INC0_REG_INC     0x1
+#define PTP_RTC_INC0_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC_INC0_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_INC_NFS*/
+	#define PTP_RTC_INC0_REG_PTP_RTC_INC_NFS
+	#define PTP_RTC_INC0_REG_PTP_RTC_INC_NFS_OFFSET  0
+	#define PTP_RTC_INC0_REG_PTP_RTC_INC_NFS_LEN     10
+	#define PTP_RTC_INC0_REG_PTP_RTC_INC_NFS_DEFAULT 0x0
+	/*[field] PTP_RTC_INC_NIS*/
+	#define PTP_RTC_INC0_REG_PTP_RTC_INC_NIS
+	#define PTP_RTC_INC0_REG_PTP_RTC_INC_NIS_OFFSET  10
+	#define PTP_RTC_INC0_REG_PTP_RTC_INC_NIS_LEN     6
+	#define PTP_RTC_INC0_REG_PTP_RTC_INC_NIS_DEFAULT 0x0
+
+struct ptp_rtc_inc0_reg {
+	a_uint16_t  ptp_rtc_inc_nfs:10;
+	a_uint16_t  ptp_rtc_inc_nis:6;
+};
+
+union ptp_rtc_inc0_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc_inc0_reg bf;
+};
+
+/*[register] PTP_RTC_INC1_REG*/
+#define PTP_RTC_INC1_REG
+#define PTP_RTC_INC1_REG_ADDRESS 0x8037
+#define PTP_RTC_INC1_REG_NUM     1
+#define PTP_RTC_INC1_REG_INC     0x1
+#define PTP_RTC_INC1_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC_INC1_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_INC_NFS*/
+	#define PTP_RTC_INC1_REG_PTP_RTC_INC_NFS
+	#define PTP_RTC_INC1_REG_PTP_RTC_INC_NFS_OFFSET  0
+	#define PTP_RTC_INC1_REG_PTP_RTC_INC_NFS_LEN     16
+	#define PTP_RTC_INC1_REG_PTP_RTC_INC_NFS_DEFAULT 0x0
+
+struct ptp_rtc_inc1_reg {
+	a_uint16_t  ptp_rtc_inc_nfs:16;
+};
+
+union ptp_rtc_inc1_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc_inc1_reg bf;
+};
+
+/*[register] PTP_RTCOFFS0_REG*/
+#define PTP_RTCOFFS0_REG
+#define PTP_RTCOFFS0_REG_ADDRESS 0x8038
+#define PTP_RTCOFFS0_REG_NUM     1
+#define PTP_RTCOFFS0_REG_INC     0x1
+#define PTP_RTCOFFS0_REG_TYPE    REG_TYPE_RW
+#define PTP_RTCOFFS0_REG_DEFAULT 0x0
+	/*[field] PTP_RTCOFFS_NSEC*/
+	#define PTP_RTCOFFS0_REG_PTP_RTCOFFS_NSEC
+	#define PTP_RTCOFFS0_REG_PTP_RTCOFFS_NSEC_OFFSET  0
+	#define PTP_RTCOFFS0_REG_PTP_RTCOFFS_NSEC_LEN     16
+	#define PTP_RTCOFFS0_REG_PTP_RTCOFFS_NSEC_DEFAULT 0x0
+
+struct ptp_rtcoffs0_reg {
+	a_uint16_t  ptp_rtcoffs_nsec:16;
+};
+
+union ptp_rtcoffs0_reg_u {
+	a_uint32_t val;
+	struct ptp_rtcoffs0_reg bf;
+};
+
+/*[register] PTP_RTCOFFS1_REG*/
+#define PTP_RTCOFFS1_REG
+#define PTP_RTCOFFS1_REG_ADDRESS 0x8039
+#define PTP_RTCOFFS1_REG_NUM     1
+#define PTP_RTCOFFS1_REG_INC     0x1
+#define PTP_RTCOFFS1_REG_TYPE    REG_TYPE_RW
+#define PTP_RTCOFFS1_REG_DEFAULT 0x0
+	/*[field] PTP_RTCOFFS_NSEC*/
+	#define PTP_RTCOFFS1_REG_PTP_RTCOFFS_NSEC
+	#define PTP_RTCOFFS1_REG_PTP_RTCOFFS_NSEC_OFFSET  0
+	#define PTP_RTCOFFS1_REG_PTP_RTCOFFS_NSEC_LEN     16
+	#define PTP_RTCOFFS1_REG_PTP_RTCOFFS_NSEC_DEFAULT 0x0
+
+struct ptp_rtcoffs1_reg {
+	a_uint16_t  ptp_rtcoffs_nsec:16;
+};
+
+union ptp_rtcoffs1_reg_u {
+	a_uint32_t val;
+	struct ptp_rtcoffs1_reg bf;
+};
+
+/*[register] PTP_RTCOFFS2_REG*/
+#define PTP_RTCOFFS2_REG
+#define PTP_RTCOFFS2_REG_ADDRESS 0x803a
+#define PTP_RTCOFFS2_REG_NUM     1
+#define PTP_RTCOFFS2_REG_INC     0x1
+#define PTP_RTCOFFS2_REG_TYPE    REG_TYPE_RW
+#define PTP_RTCOFFS2_REG_DEFAULT 0x0
+	/*[field] PTP_RTCOFFS_SEC*/
+	#define PTP_RTCOFFS2_REG_PTP_RTCOFFS_SEC
+	#define PTP_RTCOFFS2_REG_PTP_RTCOFFS_SEC_OFFSET  0
+	#define PTP_RTCOFFS2_REG_PTP_RTCOFFS_SEC_LEN     16
+	#define PTP_RTCOFFS2_REG_PTP_RTCOFFS_SEC_DEFAULT 0x0
+
+struct ptp_rtcoffs2_reg {
+	a_uint16_t  ptp_rtcoffs_sec:16;
+};
+
+union ptp_rtcoffs2_reg_u {
+	a_uint32_t val;
+	struct ptp_rtcoffs2_reg bf;
+};
+
+/*[register] PTP_RTCOFFS3_REG*/
+#define PTP_RTCOFFS3_REG
+#define PTP_RTCOFFS3_REG_ADDRESS 0x803b
+#define PTP_RTCOFFS3_REG_NUM     1
+#define PTP_RTCOFFS3_REG_INC     0x1
+#define PTP_RTCOFFS3_REG_TYPE    REG_TYPE_RW
+#define PTP_RTCOFFS3_REG_DEFAULT 0x0
+	/*[field] PTP_RTCOFFS_SEC*/
+	#define PTP_RTCOFFS3_REG_PTP_RTCOFFS_SEC
+	#define PTP_RTCOFFS3_REG_PTP_RTCOFFS_SEC_OFFSET  0
+	#define PTP_RTCOFFS3_REG_PTP_RTCOFFS_SEC_LEN     16
+	#define PTP_RTCOFFS3_REG_PTP_RTCOFFS_SEC_DEFAULT 0x0
+
+struct ptp_rtcoffs3_reg {
+	a_uint16_t  ptp_rtcoffs_sec:16;
+};
+
+union ptp_rtcoffs3_reg_u {
+	a_uint32_t val;
+	struct ptp_rtcoffs3_reg bf;
+};
+
+/*[register] PTP_RTCOFFS4_REG*/
+#define PTP_RTCOFFS4_REG
+#define PTP_RTCOFFS4_REG_ADDRESS 0x803c
+#define PTP_RTCOFFS4_REG_NUM     1
+#define PTP_RTCOFFS4_REG_INC     0x1
+#define PTP_RTCOFFS4_REG_TYPE    REG_TYPE_RW
+#define PTP_RTCOFFS4_REG_DEFAULT 0x0
+	/*[field] PTP_RTCOFFS_SEC*/
+	#define PTP_RTCOFFS4_REG_PTP_RTCOFFS_SEC
+	#define PTP_RTCOFFS4_REG_PTP_RTCOFFS_SEC_OFFSET  0
+	#define PTP_RTCOFFS4_REG_PTP_RTCOFFS_SEC_LEN     16
+	#define PTP_RTCOFFS4_REG_PTP_RTCOFFS_SEC_DEFAULT 0x0
+
+struct ptp_rtcoffs4_reg {
+	a_uint16_t  ptp_rtcoffs_sec:16;
+};
+
+union ptp_rtcoffs4_reg_u {
+	a_uint32_t val;
+	struct ptp_rtcoffs4_reg bf;
+};
+
+/*[register] PTP_RTC0_REG*/
+#define PTP_RTC0_REG
+#define PTP_RTC0_REG_ADDRESS 0x803d
+#define PTP_RTC0_REG_NUM     1
+#define PTP_RTC0_REG_INC     0x1
+#define PTP_RTC0_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC0_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_SEC*/
+	#define PTP_RTC0_REG_PTP_RTC_SEC
+	#define PTP_RTC0_REG_PTP_RTC_SEC_OFFSET  0
+	#define PTP_RTC0_REG_PTP_RTC_SEC_LEN     16
+	#define PTP_RTC0_REG_PTP_RTC_SEC_DEFAULT 0x0
+
+struct ptp_rtc0_reg {
+	a_uint16_t  ptp_rtc_sec:16;
+};
+
+union ptp_rtc0_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc0_reg bf;
+};
+
+/*[register] PTP_RTC1_REG*/
+#define PTP_RTC1_REG
+#define PTP_RTC1_REG_ADDRESS 0x803e
+#define PTP_RTC1_REG_NUM     1
+#define PTP_RTC1_REG_INC     0x1
+#define PTP_RTC1_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC1_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_SEC*/
+	#define PTP_RTC1_REG_PTP_RTC_SEC
+	#define PTP_RTC1_REG_PTP_RTC_SEC_OFFSET  0
+	#define PTP_RTC1_REG_PTP_RTC_SEC_LEN     16
+	#define PTP_RTC1_REG_PTP_RTC_SEC_DEFAULT 0x0
+
+struct ptp_rtc1_reg {
+	a_uint16_t  ptp_rtc_sec:16;
+};
+
+union ptp_rtc1_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc1_reg bf;
+};
+
+/*[register] PTP_RTC2_REG*/
+#define PTP_RTC2_REG
+#define PTP_RTC2_REG_ADDRESS 0x803f
+#define PTP_RTC2_REG_NUM     1
+#define PTP_RTC2_REG_INC     0x1
+#define PTP_RTC2_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC2_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_SEC*/
+	#define PTP_RTC2_REG_PTP_RTC_SEC
+	#define PTP_RTC2_REG_PTP_RTC_SEC_OFFSET  0
+	#define PTP_RTC2_REG_PTP_RTC_SEC_LEN     16
+	#define PTP_RTC2_REG_PTP_RTC_SEC_DEFAULT 0x0
+
+struct ptp_rtc2_reg {
+	a_uint16_t  ptp_rtc_sec:16;
+};
+
+union ptp_rtc2_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc2_reg bf;
+};
+
+/*[register] PTP_RTC3_REG*/
+#define PTP_RTC3_REG
+#define PTP_RTC3_REG_ADDRESS 0x8040
+#define PTP_RTC3_REG_NUM     1
+#define PTP_RTC3_REG_INC     0x1
+#define PTP_RTC3_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC3_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_NISEC*/
+	#define PTP_RTC3_REG_PTP_RTC_NISEC
+	#define PTP_RTC3_REG_PTP_RTC_NISEC_OFFSET  0
+	#define PTP_RTC3_REG_PTP_RTC_NISEC_LEN     16
+	#define PTP_RTC3_REG_PTP_RTC_NISEC_DEFAULT 0x0
+
+struct ptp_rtc3_reg {
+	a_uint16_t  ptp_rtc_nisec:16;
+};
+
+union ptp_rtc3_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc3_reg bf;
+};
+
+/*[register] PTP_RTC4_REG*/
+#define PTP_RTC4_REG
+#define PTP_RTC4_REG_ADDRESS 0x8041
+#define PTP_RTC4_REG_NUM     1
+#define PTP_RTC4_REG_INC     0x1
+#define PTP_RTC4_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC4_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_NISEC*/
+	#define PTP_RTC4_REG_PTP_RTC_NISEC
+	#define PTP_RTC4_REG_PTP_RTC_NISEC_OFFSET  0
+	#define PTP_RTC4_REG_PTP_RTC_NISEC_LEN     16
+	#define PTP_RTC4_REG_PTP_RTC_NISEC_DEFAULT 0x0
+
+struct ptp_rtc4_reg {
+	a_uint16_t  ptp_rtc_nisec:16;
+};
+
+union ptp_rtc4_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc4_reg bf;
+};
+
+/*[register] PTP_RTC5_REG*/
+#define PTP_RTC5_REG
+#define PTP_RTC5_REG_ADDRESS 0x8042
+#define PTP_RTC5_REG_NUM     1
+#define PTP_RTC5_REG_INC     0x1
+#define PTP_RTC5_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC5_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_NFSEC*/
+	#define PTP_RTC5_REG_PTP_RTC_NFSEC
+	#define PTP_RTC5_REG_PTP_RTC_NFSEC_OFFSET  0
+	#define PTP_RTC5_REG_PTP_RTC_NFSEC_LEN     16
+	#define PTP_RTC5_REG_PTP_RTC_NFSEC_DEFAULT 0x0
+
+struct ptp_rtc5_reg {
+	a_uint16_t  ptp_rtc_nfsec:16;
+};
+
+union ptp_rtc5_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc5_reg bf;
+};
+
+/*[register] PTP_RTC6_REG*/
+#define PTP_RTC6_REG
+#define PTP_RTC6_REG_ADDRESS 0x8043
+#define PTP_RTC6_REG_NUM     1
+#define PTP_RTC6_REG_INC     0x1
+#define PTP_RTC6_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC6_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_NFSEC*/
+	#define PTP_RTC6_REG_PTP_RTC_NFSEC
+	#define PTP_RTC6_REG_PTP_RTC_NFSEC_OFFSET  0
+	#define PTP_RTC6_REG_PTP_RTC_NFSEC_LEN     4
+	#define PTP_RTC6_REG_PTP_RTC_NFSEC_DEFAULT 0x0
+
+struct ptp_rtc6_reg {
+	a_uint16_t  ptp_rtc_nfsec:4;
+};
+
+union ptp_rtc6_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc6_reg bf;
+};
+
+/*[register] PTP_RTCOFFS_VALID_REG*/
+#define PTP_RTCOFFS_VALID_REG
+#define PTP_RTCOFFS_VALID_REG_ADDRESS 0x8044
+#define PTP_RTCOFFS_VALID_REG_NUM     1
+#define PTP_RTCOFFS_VALID_REG_INC     0x1
+#define PTP_RTCOFFS_VALID_REG_TYPE    REG_TYPE_RW
+#define PTP_RTCOFFS_VALID_REG_DEFAULT 0x0
+	/*[field] PTP_RTCOFFS_VALID*/
+	#define PTP_RTCOFFS_VALID_REG_PTP_RTCOFFS_VALID
+	#define PTP_RTCOFFS_VALID_REG_PTP_RTCOFFS_VALID_OFFSET  0
+	#define PTP_RTCOFFS_VALID_REG_PTP_RTCOFFS_VALID_LEN     1
+	#define PTP_RTCOFFS_VALID_REG_PTP_RTCOFFS_VALID_DEFAULT 0x0
+
+struct ptp_rtcoffs_valid_reg {
+	a_uint16_t  ptp_rtcoffs_valid:1;
+};
+
+union ptp_rtcoffs_valid_reg_u {
+	a_uint32_t val;
+	struct ptp_rtcoffs_valid_reg bf;
+};
+
+/*[register] PTP_MISC_CONFIG_REG*/
+#define PTP_MISC_CONFIG_REG
+#define PTP_MISC_CONFIG_REG_ADDRESS 0x80f0
+#define PTP_MISC_CONFIG_REG_NUM     1
+#define PTP_MISC_CONFIG_REG_INC     0x1
+#define PTP_MISC_CONFIG_REG_TYPE    REG_TYPE_RW
+#define PTP_MISC_CONFIG_REG_DEFAULT 0x4
+	/*[field] IPV6_UDP_CHK_EN*/
+	#define PTP_MISC_CONFIG_REG_IPV6_UDP_CHK_EN
+	#define PTP_MISC_CONFIG_REG_IPV6_UDP_CHK_EN_OFFSET  0
+	#define PTP_MISC_CONFIG_REG_IPV6_UDP_CHK_EN_LEN     1
+	#define PTP_MISC_CONFIG_REG_IPV6_UDP_CHK_EN_DEFAULT 0x0
+	/*[field] PTP_VERSION*/
+	#define PTP_MISC_CONFIG_REG_PTP_VERSION
+	#define PTP_MISC_CONFIG_REG_PTP_VERSION_OFFSET  1
+	#define PTP_MISC_CONFIG_REG_PTP_VERSION_LEN     4
+	#define PTP_MISC_CONFIG_REG_PTP_VERSION_DEFAULT 0x2
+	/*[field] PTP_VER_CHK_EN*/
+	#define PTP_MISC_CONFIG_REG_PTP_VER_CHK_EN
+	#define PTP_MISC_CONFIG_REG_PTP_VER_CHK_EN_OFFSET  5
+	#define PTP_MISC_CONFIG_REG_PTP_VER_CHK_EN_LEN     1
+	#define PTP_MISC_CONFIG_REG_PTP_VER_CHK_EN_DEFAULT 0x0
+	/*[field] PTP_ADDR_CHK_EN*/
+	#define PTP_MISC_CONFIG_REG_PTP_ADDR_CHK_EN
+	#define PTP_MISC_CONFIG_REG_PTP_ADDR_CHK_EN_OFFSET  6
+	#define PTP_MISC_CONFIG_REG_PTP_ADDR_CHK_EN_LEN     1
+	#define PTP_MISC_CONFIG_REG_PTP_ADDR_CHK_EN_DEFAULT 0x0
+	/*[field] CRC_VALIDATE_EN*/
+	#define PTP_MISC_CONFIG_REG_CRC_VALIDATE_EN
+	#define PTP_MISC_CONFIG_REG_CRC_VALIDATE_EN_OFFSET  7
+	#define PTP_MISC_CONFIG_REG_CRC_VALIDATE_EN_LEN     1
+	#define PTP_MISC_CONFIG_REG_CRC_VALIDATE_EN_DEFAULT 0x0
+	/*[field] APPENDED_TIMESTAMP_SIZE*/
+	#define PTP_MISC_CONFIG_REG_APPENDED_TIMESTAMP_SIZE
+	#define PTP_MISC_CONFIG_REG_APPENDED_TIMESTAMP_SIZE_OFFSET  8
+	#define PTP_MISC_CONFIG_REG_APPENDED_TIMESTAMP_SIZE_LEN     2
+	#define PTP_MISC_CONFIG_REG_APPENDED_TIMESTAMP_SIZE_DEFAULT 0x0
+	/*[field] TS_RTC_SELECT*/
+	#define PTP_MISC_CONFIG_REG_TS_RTC_SELECT
+	#define PTP_MISC_CONFIG_REG_TS_RTC_SELECT_OFFSET  10
+	#define PTP_MISC_CONFIG_REG_TS_RTC_SELECT_LEN     1
+	#define PTP_MISC_CONFIG_REG_TS_RTC_SELECT_DEFAULT 0x0
+	/*[field] PKT_ONE_STEP_EN*/
+	#define PTP_MISC_CONFIG_REG_PKT_ONE_STEP_EN
+	#define PTP_MISC_CONFIG_REG_PKT_ONE_STEP_EN_OFFSET  11
+	#define PTP_MISC_CONFIG_REG_PKT_ONE_STEP_EN_LEN     1
+	#define PTP_MISC_CONFIG_REG_PKT_ONE_STEP_EN_DEFAULT 0x0
+	/*[field] CF_FROM_PKT_EN*/
+	#define PTP_MISC_CONFIG_REG_CF_FROM_PKT_EN
+	#define PTP_MISC_CONFIG_REG_CF_FROM_PKT_EN_OFFSET  12
+	#define PTP_MISC_CONFIG_REG_CF_FROM_PKT_EN_LEN     1
+	#define PTP_MISC_CONFIG_REG_CF_FROM_PKT_EN_DEFAULT 0x0
+	/*[field] EMBED_INGRESS_TIME_EN*/
+	#define PTP_MISC_CONFIG_REG_EMBED_INGRESS_TIME_EN
+	#define PTP_MISC_CONFIG_REG_EMBED_INGRESS_TIME_EN_OFFSET  13
+	#define PTP_MISC_CONFIG_REG_EMBED_INGRESS_TIME_EN_LEN     1
+	#define PTP_MISC_CONFIG_REG_EMBED_INGRESS_TIME_EN_DEFAULT 0x0
+	/*[field] DROP_NEXT_PREAMBLE_EN*/
+	#define PTP_MISC_CONFIG_REG_DROP_NEXT_PREAMBLE_EN
+	#define PTP_MISC_CONFIG_REG_DROP_NEXT_PREAMBLE_EN_OFFSET  14
+	#define PTP_MISC_CONFIG_REG_DROP_NEXT_PREAMBLE_EN_LEN     1
+	#define PTP_MISC_CONFIG_REG_DROP_NEXT_PREAMBLE_EN_DEFAULT 0x0
+	/*[field] P2P_TC_OFFLOAD*/
+	#define PTP_MISC_CONFIG_REG_P2P_TC_OFFLOAD
+	#define PTP_MISC_CONFIG_REG_P2P_TC_OFFLOAD_OFFSET  15
+	#define PTP_MISC_CONFIG_REG_P2P_TC_OFFLOAD_LEN     1
+	#define PTP_MISC_CONFIG_REG_P2P_TC_OFFLOAD_DEFAULT 0x0
+
+struct ptp_misc_config_reg {
+	a_uint16_t  ipv6_udp_chk_en:1;
+	a_uint16_t  ptp_version:4;
+	a_uint16_t  ptp_ver_chk_en:1;
+	a_uint16_t  ptp_addr_chk_en:1;
+	a_uint16_t  crc_validate_en:1;
+	a_uint16_t  appended_timestamp_size:2;
+	a_uint16_t  ts_rtc_select:1;
+	a_uint16_t  pkt_one_step_en:1;
+	a_uint16_t  cf_from_pkt_en:1;
+	a_uint16_t  embed_ingress_time_en:1;
+	a_uint16_t  drop_next_preamble_en:1;
+	a_uint16_t  tc_offload:1;
+};
+
+union ptp_misc_config_reg_u {
+	a_uint32_t val;
+	struct ptp_misc_config_reg bf;
+};
+
+/*[register] PTP_EXT_IMR_REG*/
+#define PTP_EXT_IMR_REG
+#define PTP_EXT_IMR_REG_ADDRESS 0x80f1
+#define PTP_EXT_IMR_REG_NUM     1
+#define PTP_EXT_IMR_REG_INC     0x1
+#define PTP_EXT_IMR_REG_TYPE    REG_TYPE_RW
+#define PTP_EXT_IMR_REG_DEFAULT 0x0
+	/*[field] MASK_BMP*/
+	#define PTP_EXT_IMR_REG_MASK_BMP
+	#define PTP_EXT_IMR_REG_MASK_BMP_OFFSET  0
+	#define PTP_EXT_IMR_REG_MASK_BMP_LEN     5
+	#define PTP_EXT_IMR_REG_MASK_BMP_DEFAULT 0x0
+
+struct ptp_ext_imr_reg {
+	a_uint16_t  mask_bmp:16;
+};
+
+union ptp_ext_imr_reg_u {
+	a_uint32_t val;
+	struct ptp_ext_imr_reg bf;
+};
+
+/*[register] PTP_EXT_ISR_REG*/
+#define PTP_EXT_ISR_REG
+#define PTP_EXT_ISR_REG_ADDRESS 0x80f2
+#define PTP_EXT_ISR_REG_NUM     1
+#define PTP_EXT_ISR_REG_INC     0x1
+#define PTP_EXT_ISR_REG_TYPE    REG_TYPE_RW
+#define PTP_EXT_ISR_REG_DEFAULT 0x0
+	/*[field] STATUS_BMP*/
+	#define PTP_EXT_ISR_REG_STATUS_BMP
+	#define PTP_EXT_ISR_REG_STATUS_BMP_OFFSET  0
+	#define PTP_EXT_ISR_REG_STATUS_BMP_LEN     5
+	#define PTP_EXT_ISR_REG_STATUS_BMP_DEFAULT 0x0
+
+struct ptp_ext_isr_reg {
+	a_uint16_t  status_bmp:16;
+};
+
+union ptp_ext_isr_reg_u {
+	a_uint32_t val;
+	struct ptp_ext_isr_reg bf;
+};
+
+/*[register] PTP_RTC_EXT_CONF_REG*/
+#define PTP_RTC_EXT_CONF_REG
+#define PTP_RTC_EXT_CONF_REG_ADDRESS 0x8100
+#define PTP_RTC_EXT_CONF_REG_NUM     1
+#define PTP_RTC_EXT_CONF_REG_INC     0x1
+#define PTP_RTC_EXT_CONF_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC_EXT_CONF_REG_DEFAULT 0x0
+	/*[field] LOAD_RTC*/
+	#define PTP_RTC_EXT_CONF_REG_LOAD_RTC
+	#define PTP_RTC_EXT_CONF_REG_LOAD_RTC_OFFSET  0
+	#define PTP_RTC_EXT_CONF_REG_LOAD_RTC_LEN     1
+	#define PTP_RTC_EXT_CONF_REG_LOAD_RTC_DEFAULT 0x0
+	/*[field] CLEAR_RTC*/
+	#define PTP_RTC_EXT_CONF_REG_CLEAR_RTC
+	#define PTP_RTC_EXT_CONF_REG_CLEAR_RTC_OFFSET  1
+	#define PTP_RTC_EXT_CONF_REG_CLEAR_RTC_LEN     1
+	#define PTP_RTC_EXT_CONF_REG_CLEAR_RTC_DEFAULT 0x0
+	/*[field] SET_INCVAL_VALID*/
+	#define PTP_RTC_EXT_CONF_REG_SET_INCVAL_VALID
+	#define PTP_RTC_EXT_CONF_REG_SET_INCVAL_VALID_OFFSET  2
+	#define PTP_RTC_EXT_CONF_REG_SET_INCVAL_VALID_LEN     1
+	#define PTP_RTC_EXT_CONF_REG_SET_INCVAL_VALID_DEFAULT 0x0
+	/*[field] SET_INCVAL_MODE*/
+	#define PTP_RTC_EXT_CONF_REG_SET_INCVAL_MODE
+	#define PTP_RTC_EXT_CONF_REG_SET_INCVAL_MODE_OFFSET  3
+	#define PTP_RTC_EXT_CONF_REG_SET_INCVAL_MODE_LEN     1
+	#define PTP_RTC_EXT_CONF_REG_SET_INCVAL_MODE_DEFAULT 0x0
+	/*[field] RTC_SNAPSHOT*/
+	#define PTP_RTC_EXT_CONF_REG_RTC_SNAPSHOT
+	#define PTP_RTC_EXT_CONF_REG_RTC_SNAPSHOT_OFFSET  4
+	#define PTP_RTC_EXT_CONF_REG_RTC_SNAPSHOT_LEN     1
+	#define PTP_RTC_EXT_CONF_REG_RTC_SNAPSHOT_DEFAULT 0x0
+	/*[field] RTC_READ_MODE*/
+	#define PTP_RTC_EXT_CONF_REG_RTC_READ_MODE
+	#define PTP_RTC_EXT_CONF_REG_RTC_READ_MODE_OFFSET  5
+	#define PTP_RTC_EXT_CONF_REG_RTC_READ_MODE_LEN     1
+	#define PTP_RTC_EXT_CONF_REG_RTC_READ_MODE_DEFAULT 0x0
+	/*[field] SELECT_OUTPUT_WAVEFORM*/
+	#define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM
+	#define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_OFFSET  6
+	#define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_LEN     3
+	#define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_DEFAULT 0x0
+
+#define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_FREQ       0
+#define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_PULSE_10MS 2
+#define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_TRIG0_GPIO 5
+#define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_RXTS_VALID 7
+
+struct ptp_rtc_ext_conf_reg {
+	a_uint16_t  load_rtc:1;
+	a_uint16_t  clear_rtc:1;
+	a_uint16_t  set_incval_valid:1;
+	a_uint16_t  set_incval_mode:1;
+	a_uint16_t  rtc_snapshot:1;
+	a_uint16_t  rtc_read_mode:1;
+	a_uint16_t  select_output_waveform:3;
+};
+
+union ptp_rtc_ext_conf_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc_ext_conf_reg bf;
+};
+
+/*[register] PTP_RTC_PRELOADED0_REG*/
+#define PTP_RTC_PRELOADED0_REG
+#define PTP_RTC_PRELOADED0_REG_ADDRESS 0x8101
+#define PTP_RTC_PRELOADED0_REG_NUM     1
+#define PTP_RTC_PRELOADED0_REG_INC     0x1
+#define PTP_RTC_PRELOADED0_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC_PRELOADED0_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_PRELOADED_SEC*/
+	#define PTP_RTC_PRELOADED0_REG_PTP_RTC_PRELOADED_SEC
+	#define PTP_RTC_PRELOADED0_REG_PTP_RTC_PRELOADED_SEC_OFFSET  0
+	#define PTP_RTC_PRELOADED0_REG_PTP_RTC_PRELOADED_SEC_LEN     16
+	#define PTP_RTC_PRELOADED0_REG_PTP_RTC_PRELOADED_SEC_DEFAULT 0x0
+
+struct ptp_rtc_preloaded0_reg {
+	a_uint16_t  ptp_rtc_preloaded_sec:16;
+};
+
+union ptp_rtc_preloaded0_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc_preloaded0_reg bf;
+};
+
+/*[register] PTP_RTC_PRELOADED1_REG*/
+#define PTP_RTC_PRELOADED1_REG
+#define PTP_RTC_PRELOADED1_REG_ADDRESS 0x8102
+#define PTP_RTC_PRELOADED1_REG_NUM     1
+#define PTP_RTC_PRELOADED1_REG_INC     0x1
+#define PTP_RTC_PRELOADED1_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC_PRELOADED1_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_PRELOADED_SEC*/
+	#define PTP_RTC_PRELOADED1_REG_PTP_RTC_PRELOADED_SEC
+	#define PTP_RTC_PRELOADED1_REG_PTP_RTC_PRELOADED_SEC_OFFSET  0
+	#define PTP_RTC_PRELOADED1_REG_PTP_RTC_PRELOADED_SEC_LEN     16
+	#define PTP_RTC_PRELOADED1_REG_PTP_RTC_PRELOADED_SEC_DEFAULT 0x0
+
+struct ptp_rtc_preloaded1_reg {
+	a_uint16_t  ptp_rtc_preloaded_sec:16;
+};
+
+union ptp_rtc_preloaded1_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc_preloaded1_reg bf;
+};
+
+/*[register] PTP_RTC_PRELOADED2_REG*/
+#define PTP_RTC_PRELOADED2_REG
+#define PTP_RTC_PRELOADED2_REG_ADDRESS 0x8103
+#define PTP_RTC_PRELOADED2_REG_NUM     1
+#define PTP_RTC_PRELOADED2_REG_INC     0x1
+#define PTP_RTC_PRELOADED2_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC_PRELOADED2_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_PRELOADED_SEC*/
+	#define PTP_RTC_PRELOADED2_REG_PTP_RTC_PRELOADED_SEC
+	#define PTP_RTC_PRELOADED2_REG_PTP_RTC_PRELOADED_SEC_OFFSET  0
+	#define PTP_RTC_PRELOADED2_REG_PTP_RTC_PRELOADED_SEC_LEN     16
+	#define PTP_RTC_PRELOADED2_REG_PTP_RTC_PRELOADED_SEC_DEFAULT 0x0
+
+struct ptp_rtc_preloaded2_reg {
+	a_uint16_t  ptp_rtc_preloaded_sec:16;
+};
+
+union ptp_rtc_preloaded2_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc_preloaded2_reg bf;
+};
+
+/*[register] PTP_RTC_PRELOADED3_REG*/
+#define PTP_RTC_PRELOADED3_REG
+#define PTP_RTC_PRELOADED3_REG_ADDRESS 0x8104
+#define PTP_RTC_PRELOADED3_REG_NUM     1
+#define PTP_RTC_PRELOADED3_REG_INC     0x1
+#define PTP_RTC_PRELOADED3_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC_PRELOADED3_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_PRELOADED_NISEC*/
+	#define PTP_RTC_PRELOADED3_REG_PTP_RTC_PRELOADED_NISEC
+	#define PTP_RTC_PRELOADED3_REG_PTP_RTC_PRELOADED_NISEC_OFFSET  0
+	#define PTP_RTC_PRELOADED3_REG_PTP_RTC_PRELOADED_NISEC_LEN     16
+	#define PTP_RTC_PRELOADED3_REG_PTP_RTC_PRELOADED_NISEC_DEFAULT 0x0
+
+struct ptp_rtc_preloaded3_reg {
+	a_uint16_t  ptp_rtc_preloaded_nisec:16;
+};
+
+union ptp_rtc_preloaded3_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc_preloaded3_reg bf;
+};
+
+/*[register] PTP_RTC_PRELOADED4_REG*/
+#define PTP_RTC_PRELOADED4_REG
+#define PTP_RTC_PRELOADED4_REG_ADDRESS 0x8105
+#define PTP_RTC_PRELOADED4_REG_NUM     1
+#define PTP_RTC_PRELOADED4_REG_INC     0x1
+#define PTP_RTC_PRELOADED4_REG_TYPE    REG_TYPE_RW
+#define PTP_RTC_PRELOADED4_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_PRELOADED_NISEC*/
+	#define PTP_RTC_PRELOADED4_REG_PTP_RTC_PRELOADED_NISEC
+	#define PTP_RTC_PRELOADED4_REG_PTP_RTC_PRELOADED_NISEC_OFFSET  0
+	#define PTP_RTC_PRELOADED4_REG_PTP_RTC_PRELOADED_NISEC_LEN     16
+	#define PTP_RTC_PRELOADED4_REG_PTP_RTC_PRELOADED_NISEC_DEFAULT 0x0
+
+struct ptp_rtc_preloaded4_reg {
+	a_uint16_t  ptp_rtc_preloaded_nisec:16;
+};
+
+union ptp_rtc_preloaded4_reg_u {
+	a_uint32_t val;
+	struct ptp_rtc_preloaded4_reg bf;
+};
+
+/*[register] PTP_GM_CONF0_REG*/
+#define PTP_GM_CONF0_REG
+#define PTP_GM_CONF0_REG_ADDRESS 0x8200
+#define PTP_GM_CONF0_REG_NUM     1
+#define PTP_GM_CONF0_REG_INC     0x1
+#define PTP_GM_CONF0_REG_TYPE    REG_TYPE_RW
+#define PTP_GM_CONF0_REG_DEFAULT 0x0
+	/*[field] GM_MAXFREQ_OFFSET*/
+	#define PTP_GM_CONF0_REG_GM_MAXFREQ_OFFSET
+	#define PTP_GM_CONF0_REG_GM_MAXFREQ_OFFSET_OFFSET  0
+	#define PTP_GM_CONF0_REG_GM_MAXFREQ_OFFSET_LEN     4
+	#define PTP_GM_CONF0_REG_GM_MAXFREQ_OFFSET_DEFAULT 0x0
+	/*[field] GM_PLL_MODE*/
+	#define PTP_GM_CONF0_REG_GM_PLL_MODE
+	#define PTP_GM_CONF0_REG_GM_PLL_MODE_OFFSET  4
+	#define PTP_GM_CONF0_REG_GM_PLL_MODE_LEN     1
+	#define PTP_GM_CONF0_REG_GM_PLL_MODE_DEFAULT 0x0
+	/*[field] GM_PPS_SYNC*/
+	#define PTP_GM_CONF0_REG_GM_PPS_SYNC
+	#define PTP_GM_CONF0_REG_GM_PPS_SYNC_OFFSET  5
+	#define PTP_GM_CONF0_REG_GM_PPS_SYNC_LEN     1
+	#define PTP_GM_CONF0_REG_GM_PPS_SYNC_DEFAULT 0x0
+	/*[field] GRANDMASTER_MODE*/
+	#define PTP_GM_CONF0_REG_GRANDMASTER_MODE
+	#define PTP_GM_CONF0_REG_GRANDMASTER_MODE_OFFSET  6
+	#define PTP_GM_CONF0_REG_GRANDMASTER_MODE_LEN     1
+	#define PTP_GM_CONF0_REG_GRANDMASTER_MODE_DEFAULT 0x0
+
+struct ptp_gm_conf0_reg {
+	a_uint16_t  gm_maxfreq_offset:4;
+	a_uint16_t  gm_pll_mode:1;
+	a_uint16_t  gm_pps_sync:1;
+	a_uint16_t  grandmaster_mode:1;
+};
+
+union ptp_gm_conf0_reg_u {
+	a_uint32_t val;
+	struct ptp_gm_conf0_reg bf;
+};
+
+/*[register] PTP_GM_CONF1_REG*/
+#define PTP_GM_CONF1_REG
+#define PTP_GM_CONF1_REG_ADDRESS 0x8201
+#define PTP_GM_CONF1_REG_NUM     1
+#define PTP_GM_CONF1_REG_INC     0x1
+#define PTP_GM_CONF1_REG_TYPE    REG_TYPE_RW
+#define PTP_GM_CONF1_REG_DEFAULT 0x0
+	/*[field] GM_KI_LDN*/
+	#define PTP_GM_CONF1_REG_GM_KI_LDN
+	#define PTP_GM_CONF1_REG_GM_KI_LDN_OFFSET  0
+	#define PTP_GM_CONF1_REG_GM_KI_LDN_LEN     6
+	#define PTP_GM_CONF1_REG_GM_KI_LDN_DEFAULT 0x0
+	/*[field] GM_KP_LDN*/
+	#define PTP_GM_CONF1_REG_GM_KP_LDN
+	#define PTP_GM_CONF1_REG_GM_KP_LDN_OFFSET  6
+	#define PTP_GM_CONF1_REG_GM_KP_LDN_LEN     6
+	#define PTP_GM_CONF1_REG_GM_KP_LDN_DEFAULT 0x0
+
+struct ptp_gm_conf1_reg {
+	a_uint16_t  gm_ki_ldn:6;
+	a_uint16_t  gm_kp_ldn:6;
+};
+
+union ptp_gm_conf1_reg_u {
+	a_uint32_t val;
+	struct ptp_gm_conf1_reg bf;
+};
+
+/*[register] PTP_PPSIN_TS0_REG*/
+#define PTP_PPSIN_TS0_REG
+#define PTP_PPSIN_TS0_REG_ADDRESS 0x8202
+#define PTP_PPSIN_TS0_REG_NUM     1
+#define PTP_PPSIN_TS0_REG_INC     0x1
+#define PTP_PPSIN_TS0_REG_TYPE    REG_TYPE_RW
+#define PTP_PPSIN_TS0_REG_DEFAULT 0x0
+	/*[field] RX_TS_SEC*/
+	#define PTP_PPSIN_TS0_REG_RX_TS_SEC
+	#define PTP_PPSIN_TS0_REG_RX_TS_SEC_OFFSET  0
+	#define PTP_PPSIN_TS0_REG_RX_TS_SEC_LEN     16
+	#define PTP_PPSIN_TS0_REG_RX_TS_SEC_DEFAULT 0x0
+
+struct ptp_ppsin_ts0_reg {
+	a_uint16_t  rx_ts_sec:16;
+};
+
+union ptp_ppsin_ts0_reg_u {
+	a_uint32_t val;
+	struct ptp_ppsin_ts0_reg bf;
+};
+
+/*[register] PTP_PPSIN_TS1_REG*/
+#define PTP_PPSIN_TS1_REG
+#define PTP_PPSIN_TS1_REG_ADDRESS 0x8203
+#define PTP_PPSIN_TS1_REG_NUM     1
+#define PTP_PPSIN_TS1_REG_INC     0x1
+#define PTP_PPSIN_TS1_REG_TYPE    REG_TYPE_RW
+#define PTP_PPSIN_TS1_REG_DEFAULT 0x0
+	/*[field] RX_TS_SEC*/
+	#define PTP_PPSIN_TS1_REG_RX_TS_SEC
+	#define PTP_PPSIN_TS1_REG_RX_TS_SEC_OFFSET  0
+	#define PTP_PPSIN_TS1_REG_RX_TS_SEC_LEN     16
+	#define PTP_PPSIN_TS1_REG_RX_TS_SEC_DEFAULT 0x0
+
+struct ptp_ppsin_ts1_reg {
+	a_uint16_t  rx_ts_sec:16;
+};
+
+union ptp_ppsin_ts1_reg_u {
+	a_uint32_t val;
+	struct ptp_ppsin_ts1_reg bf;
+};
+
+/*[register] PTP_PPSIN_TS2_REG*/
+#define PTP_PPSIN_TS2_REG
+#define PTP_PPSIN_TS2_REG_ADDRESS 0x8204
+#define PTP_PPSIN_TS2_REG_NUM     1
+#define PTP_PPSIN_TS2_REG_INC     0x1
+#define PTP_PPSIN_TS2_REG_TYPE    REG_TYPE_RW
+#define PTP_PPSIN_TS2_REG_DEFAULT 0x0
+	/*[field] RX_TS_SEC*/
+	#define PTP_PPSIN_TS2_REG_RX_TS_SEC
+	#define PTP_PPSIN_TS2_REG_RX_TS_SEC_OFFSET  0
+	#define PTP_PPSIN_TS2_REG_RX_TS_SEC_LEN     16
+	#define PTP_PPSIN_TS2_REG_RX_TS_SEC_DEFAULT 0x0
+
+struct ptp_ppsin_ts2_reg {
+	a_uint16_t  rx_ts_sec:16;
+};
+
+union ptp_ppsin_ts2_reg_u {
+	a_uint32_t val;
+	struct ptp_ppsin_ts2_reg bf;
+};
+
+/*[register] PTP_PPSIN_TS3_REG*/
+#define PTP_PPSIN_TS3_REG
+#define PTP_PPSIN_TS3_REG_ADDRESS 0x8205
+#define PTP_PPSIN_TS3_REG_NUM     1
+#define PTP_PPSIN_TS3_REG_INC     0x1
+#define PTP_PPSIN_TS3_REG_TYPE    REG_TYPE_RW
+#define PTP_PPSIN_TS3_REG_DEFAULT 0x0
+	/*[field] RX_TS_NSEC*/
+	#define PTP_PPSIN_TS3_REG_RX_TS_NSEC
+	#define PTP_PPSIN_TS3_REG_RX_TS_NSEC_OFFSET  0
+	#define PTP_PPSIN_TS3_REG_RX_TS_NSEC_LEN     16
+	#define PTP_PPSIN_TS3_REG_RX_TS_NSEC_DEFAULT 0x0
+
+struct ptp_ppsin_ts3_reg {
+	a_uint16_t  rx_ts_nsec:16;
+};
+
+union ptp_ppsin_ts3_reg_u {
+	a_uint32_t val;
+	struct ptp_ppsin_ts3_reg bf;
+};
+
+/*[register] PTP_PPSIN_TS4_REG*/
+#define PTP_PPSIN_TS4_REG
+#define PTP_PPSIN_TS4_REG_ADDRESS 0x8206
+#define PTP_PPSIN_TS4_REG_NUM     1
+#define PTP_PPSIN_TS4_REG_INC     0x1
+#define PTP_PPSIN_TS4_REG_TYPE    REG_TYPE_RW
+#define PTP_PPSIN_TS4_REG_DEFAULT 0x0
+	/*[field] RX_TS_NSEC*/
+	#define PTP_PPSIN_TS4_REG_RX_TS_NSEC
+	#define PTP_PPSIN_TS4_REG_RX_TS_NSEC_OFFSET  0
+	#define PTP_PPSIN_TS4_REG_RX_TS_NSEC_LEN     16
+	#define PTP_PPSIN_TS4_REG_RX_TS_NSEC_DEFAULT 0x0
+
+struct ptp_ppsin_ts4_reg {
+	a_uint16_t  rx_ts_nsec:16;
+};
+
+union ptp_ppsin_ts4_reg_u {
+	a_uint32_t val;
+	struct ptp_ppsin_ts4_reg bf;
+};
+
+/*[register] PTP_HWPLL_INC0_REG*/
+#define PTP_HWPLL_INC0_REG
+#define PTP_HWPLL_INC0_REG_ADDRESS 0x8207
+#define PTP_HWPLL_INC0_REG_NUM     1
+#define PTP_HWPLL_INC0_REG_INC     0x1
+#define PTP_HWPLL_INC0_REG_TYPE    REG_TYPE_RW
+#define PTP_HWPLL_INC0_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_INC_NFS1*/
+	#define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NFS1
+	#define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NFS1_OFFSET  0
+	#define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NFS1_LEN     10
+	#define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NFS1_DEFAULT 0x0
+	/*[field] PTP_RTC_INC_NIS*/
+	#define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NIS
+	#define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NIS_OFFSET  10
+	#define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NIS_LEN     6
+	#define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NIS_DEFAULT 0x0
+
+struct ptp_hwpll_inc0_reg {
+	a_uint16_t  ptp_rtc_inc_nfs1:10;
+	a_uint16_t  ptp_rtc_inc_nis:6;
+};
+
+union ptp_hwpll_inc0_reg_u {
+	a_uint32_t val;
+	struct ptp_hwpll_inc0_reg bf;
+};
+
+/*[register] PTP_HWPLL_INC1_REG*/
+#define PTP_HWPLL_INC1_REG
+#define PTP_HWPLL_INC1_REG_ADDRESS 0x8208
+#define PTP_HWPLL_INC1_REG_NUM     1
+#define PTP_HWPLL_INC1_REG_INC     0x1
+#define PTP_HWPLL_INC1_REG_TYPE    REG_TYPE_RW
+#define PTP_HWPLL_INC1_REG_DEFAULT 0x0
+	/*[field] PTP_RTC_INC_NFS0*/
+	#define PTP_HWPLL_INC1_REG_PTP_RTC_INC_NFS0
+	#define PTP_HWPLL_INC1_REG_PTP_RTC_INC_NFS0_OFFSET  0
+	#define PTP_HWPLL_INC1_REG_PTP_RTC_INC_NFS0_LEN     16
+	#define PTP_HWPLL_INC1_REG_PTP_RTC_INC_NFS0_DEFAULT 0x0
+
+struct ptp_hwpll_inc1_reg {
+	a_uint16_t  ptp_rtc_inc_nfs0:16;
+};
+
+union ptp_hwpll_inc1_reg_u {
+	a_uint32_t val;
+	struct ptp_hwpll_inc1_reg bf;
+};
+
+/*[register] PTP_PPSIN_LATENCY_REG*/
+#define PTP_PPSIN_LATENCY_REG
+#define PTP_PPSIN_LATENCY_REG_ADDRESS 0x8209
+#define PTP_PPSIN_LATENCY_REG_NUM     1
+#define PTP_PPSIN_LATENCY_REG_INC     0x1
+#define PTP_PPSIN_LATENCY_REG_TYPE    REG_TYPE_RW
+#define PTP_PPSIN_LATENCY_REG_DEFAULT 0x0
+	/*[field] PTP_PPSIN_LATENCY_VALUE*/
+	#define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_VALUE
+	#define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_VALUE_OFFSET  0
+	#define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_VALUE_LEN     7
+	#define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_VALUE_DEFAULT 0x0
+	/*[field] PTP_PPSIN_LATENCY_SIGN*/
+	#define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_SIGN
+	#define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_SIGN_OFFSET  7
+	#define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_SIGN_LEN     1
+	#define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_SIGN_DEFAULT 0x0
+
+struct ptp_ppsin_latency_reg {
+	a_uint16_t  ptp_ppsin_latency_value:7;
+	a_uint16_t  ptp_ppsin_latency_sign:1;
+};
+
+union ptp_ppsin_latency_reg_u {
+	a_uint32_t val;
+	struct ptp_ppsin_latency_reg bf;
+};
+
+/*[register] PTP_TRIGGER0_CONFIG_REG*/
+#define PTP_TRIGGER0_CONFIG_REG
+#define PTP_TRIGGER0_CONFIG_REG_ADDRESS 0x8400
+#define PTP_TRIGGER0_CONFIG_REG_NUM     1
+#define PTP_TRIGGER0_CONFIG_REG_INC     0x1
+#define PTP_TRIGGER0_CONFIG_REG_TYPE    REG_TYPE_RW
+#define PTP_TRIGGER0_CONFIG_REG_DEFAULT 0x0
+	/*[field] STATUS*/
+	#define PTP_TRIGGER0_CONFIG_REG_STATUS
+	#define PTP_TRIGGER0_CONFIG_REG_STATUS_OFFSET  0
+	#define PTP_TRIGGER0_CONFIG_REG_STATUS_LEN     1
+	#define PTP_TRIGGER0_CONFIG_REG_STATUS_DEFAULT 0x0
+	/*[field] FORCE_EN*/
+	#define PTP_TRIGGER0_CONFIG_REG_FORCE_EN
+	#define PTP_TRIGGER0_CONFIG_REG_FORCE_EN_OFFSET  1
+	#define PTP_TRIGGER0_CONFIG_REG_FORCE_EN_LEN     1
+	#define PTP_TRIGGER0_CONFIG_REG_FORCE_EN_DEFAULT 0x0
+	/*[field] FORCE_VALUE*/
+	#define PTP_TRIGGER0_CONFIG_REG_FORCE_VALUE
+	#define PTP_TRIGGER0_CONFIG_REG_FORCE_VALUE_OFFSET  2
+	#define PTP_TRIGGER0_CONFIG_REG_FORCE_VALUE_LEN     1
+	#define PTP_TRIGGER0_CONFIG_REG_FORCE_VALUE_DEFAULT 0x0
+	/*[field] PATTERN*/
+	#define PTP_TRIGGER0_CONFIG_REG_PATTERN
+	#define PTP_TRIGGER0_CONFIG_REG_PATTERN_OFFSET  3
+	#define PTP_TRIGGER0_CONFIG_REG_PATTERN_LEN     3
+	#define PTP_TRIGGER0_CONFIG_REG_PATTERN_DEFAULT 0x0
+	/*[field] IF_LATE*/
+	#define PTP_TRIGGER0_CONFIG_REG_IF_LATE
+	#define PTP_TRIGGER0_CONFIG_REG_IF_LATE_OFFSET  6
+	#define PTP_TRIGGER0_CONFIG_REG_IF_LATE_LEN     1
+	#define PTP_TRIGGER0_CONFIG_REG_IF_LATE_DEFAULT 0x0
+	/*[field] NOTIFY*/
+	#define PTP_TRIGGER0_CONFIG_REG_NOTIFY
+	#define PTP_TRIGGER0_CONFIG_REG_NOTIFY_OFFSET  7
+	#define PTP_TRIGGER0_CONFIG_REG_NOTIFY_LEN     1
+	#define PTP_TRIGGER0_CONFIG_REG_NOTIFY_DEFAULT 0x0
+	/*[field] SETTING*/
+	#define PTP_TRIGGER0_CONFIG_REG_SETTING
+	#define PTP_TRIGGER0_CONFIG_REG_SETTING_OFFSET  8
+	#define PTP_TRIGGER0_CONFIG_REG_SETTING_LEN     1
+	#define PTP_TRIGGER0_CONFIG_REG_SETTING_DEFAULT 0x0
+
+struct ptp_trigger0_config_reg {
+	a_uint16_t  status:1;
+	a_uint16_t  force_en:1;
+	a_uint16_t  force_value:1;
+	a_uint16_t  pattern:3;
+	a_uint16_t  if_late:1;
+	a_uint16_t  notify:1;
+	a_uint16_t  setting:1;
+};
+
+union ptp_trigger0_config_reg_u {
+	a_uint32_t val;
+	struct ptp_trigger0_config_reg bf;
+};
+
+/*[register] PTP_TRIGGER0_STATUS_REG*/
+#define PTP_TRIGGER0_STATUS_REG
+#define PTP_TRIGGER0_STATUS_REG_ADDRESS 0x8401
+#define PTP_TRIGGER0_STATUS_REG_NUM     1
+#define PTP_TRIGGER0_STATUS_REG_INC     0x1
+#define PTP_TRIGGER0_STATUS_REG_TYPE    REG_TYPE_RW
+#define PTP_TRIGGER0_STATUS_REG_DEFAULT 0x0
+	/*[field] FINISHED*/
+	#define PTP_TRIGGER0_STATUS_REG_FINISHED
+	#define PTP_TRIGGER0_STATUS_REG_FINISHED_OFFSET  0
+	#define PTP_TRIGGER0_STATUS_REG_FINISHED_LEN     1
+	#define PTP_TRIGGER0_STATUS_REG_FINISHED_DEFAULT 0x0
+	/*[field] ACTIVE*/
+	#define PTP_TRIGGER0_STATUS_REG_ACTIVE
+	#define PTP_TRIGGER0_STATUS_REG_ACTIVE_OFFSET  1
+	#define PTP_TRIGGER0_STATUS_REG_ACTIVE_LEN     1
+	#define PTP_TRIGGER0_STATUS_REG_ACTIVE_DEFAULT 0x0
+	/*[field] ERROR*/
+	#define PTP_TRIGGER0_STATUS_REG_ERROR
+	#define PTP_TRIGGER0_STATUS_REG_ERROR_OFFSET  2
+	#define PTP_TRIGGER0_STATUS_REG_ERROR_LEN     2
+	#define PTP_TRIGGER0_STATUS_REG_ERROR_DEFAULT 0x0
+
+struct ptp_trigger0_status_reg {
+	a_uint16_t  finished:1;
+	a_uint16_t  active:1;
+	a_uint16_t  error:2;
+};
+
+union ptp_trigger0_status_reg_u {
+	a_uint32_t val;
+	struct ptp_trigger0_status_reg bf;
+};
+
+/*[register] PTP_TRIGGER1_CONFIG_REG*/
+#define PTP_TRIGGER1_CONFIG_REG
+#define PTP_TRIGGER1_CONFIG_REG_ADDRESS 0x8402
+#define PTP_TRIGGER1_CONFIG_REG_NUM     1
+#define PTP_TRIGGER1_CONFIG_REG_INC     0x1
+#define PTP_TRIGGER1_CONFIG_REG_TYPE    REG_TYPE_RW
+#define PTP_TRIGGER1_CONFIG_REG_DEFAULT 0x0
+	/*[field] STATUS*/
+	#define PTP_TRIGGER1_CONFIG_REG_STATUS
+	#define PTP_TRIGGER1_CONFIG_REG_STATUS_OFFSET  0
+	#define PTP_TRIGGER1_CONFIG_REG_STATUS_LEN     1
+	#define PTP_TRIGGER1_CONFIG_REG_STATUS_DEFAULT 0x0
+	/*[field] FORCE_EN*/
+	#define PTP_TRIGGER1_CONFIG_REG_FORCE_EN
+	#define PTP_TRIGGER1_CONFIG_REG_FORCE_EN_OFFSET  1
+	#define PTP_TRIGGER1_CONFIG_REG_FORCE_EN_LEN     1
+	#define PTP_TRIGGER1_CONFIG_REG_FORCE_EN_DEFAULT 0x0
+	/*[field] FORCE_VALUE*/
+	#define PTP_TRIGGER1_CONFIG_REG_FORCE_VALUE
+	#define PTP_TRIGGER1_CONFIG_REG_FORCE_VALUE_OFFSET  2
+	#define PTP_TRIGGER1_CONFIG_REG_FORCE_VALUE_LEN     1
+	#define PTP_TRIGGER1_CONFIG_REG_FORCE_VALUE_DEFAULT 0x0
+	/*[field] PATTERN*/
+	#define PTP_TRIGGER1_CONFIG_REG_PATTERN
+	#define PTP_TRIGGER1_CONFIG_REG_PATTERN_OFFSET  3
+	#define PTP_TRIGGER1_CONFIG_REG_PATTERN_LEN     3
+	#define PTP_TRIGGER1_CONFIG_REG_PATTERN_DEFAULT 0x0
+	/*[field] IF_LATE*/
+	#define PTP_TRIGGER1_CONFIG_REG_IF_LATE
+	#define PTP_TRIGGER1_CONFIG_REG_IF_LATE_OFFSET  6
+	#define PTP_TRIGGER1_CONFIG_REG_IF_LATE_LEN     1
+	#define PTP_TRIGGER1_CONFIG_REG_IF_LATE_DEFAULT 0x0
+	/*[field] NOTIFY*/
+	#define PTP_TRIGGER1_CONFIG_REG_NOTIFY
+	#define PTP_TRIGGER1_CONFIG_REG_NOTIFY_OFFSET  7
+	#define PTP_TRIGGER1_CONFIG_REG_NOTIFY_LEN     1
+	#define PTP_TRIGGER1_CONFIG_REG_NOTIFY_DEFAULT 0x0
+	/*[field] SETTING*/
+	#define PTP_TRIGGER1_CONFIG_REG_SETTING
+	#define PTP_TRIGGER1_CONFIG_REG_SETTING_OFFSET  8
+	#define PTP_TRIGGER1_CONFIG_REG_SETTING_LEN     1
+	#define PTP_TRIGGER1_CONFIG_REG_SETTING_DEFAULT 0x0
+
+struct ptp_trigger1_config_reg {
+	a_uint16_t  status:1;
+	a_uint16_t  force_en:1;
+	a_uint16_t  force_value:1;
+	a_uint16_t  pattern:3;
+	a_uint16_t  if_late:1;
+	a_uint16_t  notify:1;
+	a_uint16_t  setting:1;
+};
+
+union ptp_trigger1_config_reg_u {
+	a_uint32_t val;
+	struct ptp_trigger1_config_reg bf;
+};
+
+/*[register] PTP_TRIGGER1_STATUS_REG*/
+#define PTP_TRIGGER1_STATUS_REG
+#define PTP_TRIGGER1_STATUS_REG_ADDRESS 0x8403
+#define PTP_TRIGGER1_STATUS_REG_NUM     1
+#define PTP_TRIGGER1_STATUS_REG_INC     0x1
+#define PTP_TRIGGER1_STATUS_REG_TYPE    REG_TYPE_RW
+#define PTP_TRIGGER1_STATUS_REG_DEFAULT 0x0
+	/*[field] FINISHED*/
+	#define PTP_TRIGGER1_STATUS_REG_FINISHED
+	#define PTP_TRIGGER1_STATUS_REG_FINISHED_OFFSET  0
+	#define PTP_TRIGGER1_STATUS_REG_FINISHED_LEN     1
+	#define PTP_TRIGGER1_STATUS_REG_FINISHED_DEFAULT 0x0
+	/*[field] ACTIVE*/
+	#define PTP_TRIGGER1_STATUS_REG_ACTIVE
+	#define PTP_TRIGGER1_STATUS_REG_ACTIVE_OFFSET  1
+	#define PTP_TRIGGER1_STATUS_REG_ACTIVE_LEN     1
+	#define PTP_TRIGGER1_STATUS_REG_ACTIVE_DEFAULT 0x0
+	/*[field] ERROR*/
+	#define PTP_TRIGGER1_STATUS_REG_ERROR
+	#define PTP_TRIGGER1_STATUS_REG_ERROR_OFFSET  2
+	#define PTP_TRIGGER1_STATUS_REG_ERROR_LEN     2
+	#define PTP_TRIGGER1_STATUS_REG_ERROR_DEFAULT 0x0
+
+struct ptp_trigger1_status_reg {
+	a_uint16_t  finished:1;
+	a_uint16_t  active:1;
+	a_uint16_t  error:2;
+};
+
+union ptp_trigger1_status_reg_u {
+	a_uint32_t val;
+	struct ptp_trigger1_status_reg bf;
+};
+
+/*[register] PTP_TRIGGER0_TIMESTAMP0_REG*/
+#define PTP_TRIGGER0_TIMESTAMP0_REG
+#define PTP_TRIGGER0_TIMESTAMP0_REG_ADDRESS 0x8404
+#define PTP_TRIGGER0_TIMESTAMP0_REG_NUM     1
+#define PTP_TRIGGER0_TIMESTAMP0_REG_INC     0x1
+#define PTP_TRIGGER0_TIMESTAMP0_REG_TYPE    REG_TYPE_RW
+#define PTP_TRIGGER0_TIMESTAMP0_REG_DEFAULT 0x0
+	/*[field] TS_SEC*/
+	#define PTP_TRIGGER0_TIMESTAMP0_REG_TS_SEC
+	#define PTP_TRIGGER0_TIMESTAMP0_REG_TS_SEC_OFFSET  0
+	#define PTP_TRIGGER0_TIMESTAMP0_REG_TS_SEC_LEN     16
+	#define PTP_TRIGGER0_TIMESTAMP0_REG_TS_SEC_DEFAULT 0x0
+
+struct ptp_trigger0_timestamp0_reg {
+	a_uint16_t  ts_sec:16;
+};
+
+union ptp_trigger0_timestamp0_reg_u {
+	a_uint32_t val;
+	struct ptp_trigger0_timestamp0_reg bf;
+};
+
+/*[register] PTP_TRIGGER0_TIMESTAMP1_REG*/
+#define PTP_TRIGGER0_TIMESTAMP1_REG
+#define PTP_TRIGGER0_TIMESTAMP1_REG_ADDRESS 0x8405
+#define PTP_TRIGGER0_TIMESTAMP1_REG_NUM     1
+#define PTP_TRIGGER0_TIMESTAMP1_REG_INC     0x1
+#define PTP_TRIGGER0_TIMESTAMP1_REG_TYPE    REG_TYPE_RW
+#define PTP_TRIGGER0_TIMESTAMP1_REG_DEFAULT 0x0
+	/*[field] TS_SEC*/
+	#define PTP_TRIGGER0_TIMESTAMP1_REG_TS_SEC
+	#define PTP_TRIGGER0_TIMESTAMP1_REG_TS_SEC_OFFSET  0
+	#define PTP_TRIGGER0_TIMESTAMP1_REG_TS_SEC_LEN     16
+	#define PTP_TRIGGER0_TIMESTAMP1_REG_TS_SEC_DEFAULT 0x0
+
+struct ptp_trigger0_timestamp1_reg {
+	a_uint16_t  ts_sec:16;
+};
+
+union ptp_trigger0_timestamp1_reg_u {
+	a_uint32_t val;
+	struct ptp_trigger0_timestamp1_reg bf;
+};
+
+/*[register] PTP_TRIGGER0_TIMESTAMP2_REG*/
+#define PTP_TRIGGER0_TIMESTAMP2_REG
+#define PTP_TRIGGER0_TIMESTAMP2_REG_ADDRESS 0x8406
+#define PTP_TRIGGER0_TIMESTAMP2_REG_NUM     1
+#define PTP_TRIGGER0_TIMESTAMP2_REG_INC     0x1
+#define PTP_TRIGGER0_TIMESTAMP2_REG_TYPE    REG_TYPE_RW
+#define PTP_TRIGGER0_TIMESTAMP2_REG_DEFAULT 0x0
+	/*[field] TS_SEC*/
+	#define PTP_TRIGGER0_TIMESTAMP2_REG_TS_SEC
+	#define PTP_TRIGGER0_TIMESTAMP2_REG_TS_SEC_OFFSET  0
+	#define PTP_TRIGGER0_TIMESTAMP2_REG_TS_SEC_LEN     16
+	#define PTP_TRIGGER0_TIMESTAMP2_REG_TS_SEC_DEFAULT 0x0
+
+struct ptp_trigger0_timestamp2_reg {
+	a_uint16_t  ts_sec:16;
+};
+
+union ptp_trigger0_timestamp2_reg_u {
+	a_uint32_t val;
+	struct ptp_trigger0_timestamp2_reg bf;
+};
+
+/*[register] PTP_TRIGGER0_TIMESTAMP3_REG*/
+#define PTP_TRIGGER0_TIMESTAMP3_REG
+#define PTP_TRIGGER0_TIMESTAMP3_REG_ADDRESS 0x8407
+#define PTP_TRIGGER0_TIMESTAMP3_REG_NUM     1
+#define PTP_TRIGGER0_TIMESTAMP3_REG_INC     0x1
+#define PTP_TRIGGER0_TIMESTAMP3_REG_TYPE    REG_TYPE_RW
+#define PTP_TRIGGER0_TIMESTAMP3_REG_DEFAULT 0x0
+	/*[field] TS_NSEC*/
+	#define PTP_TRIGGER0_TIMESTAMP3_REG_TS_NSEC
+	#define PTP_TRIGGER0_TIMESTAMP3_REG_TS_NSEC_OFFSET  0
+	#define PTP_TRIGGER0_TIMESTAMP3_REG_TS_NSEC_LEN     16
+	#define PTP_TRIGGER0_TIMESTAMP3_REG_TS_NSEC_DEFAULT 0x0
+
+struct ptp_trigger0_timestamp3_reg {
+	a_uint16_t  ts_nsec:16;
+};
+
+union ptp_trigger0_timestamp3_reg_u {
+	a_uint32_t val;
+	struct ptp_trigger0_timestamp3_reg bf;
+};
+
+/*[register] PTP_TRIGGER0_TIMESTAMP4_REG*/
+#define PTP_TRIGGER0_TIMESTAMP4_REG
+#define PTP_TRIGGER0_TIMESTAMP4_REG_ADDRESS 0x8408
+#define PTP_TRIGGER0_TIMESTAMP4_REG_NUM     1
+#define PTP_TRIGGER0_TIMESTAMP4_REG_INC     0x1
+#define PTP_TRIGGER0_TIMESTAMP4_REG_TYPE    REG_TYPE_RW
+#define PTP_TRIGGER0_TIMESTAMP4_REG_DEFAULT 0x0
+	/*[field] TS_NSEC*/
+	#define PTP_TRIGGER0_TIMESTAMP4_REG_TS_NSEC
+	#define PTP_TRIGGER0_TIMESTAMP4_REG_TS_NSEC_OFFSET  0
+	#define PTP_TRIGGER0_TIMESTAMP4_REG_TS_NSEC_LEN     16
+	#define PTP_TRIGGER0_TIMESTAMP4_REG_TS_NSEC_DEFAULT 0x0
+
+struct ptp_trigger0_timestamp4_reg {
+	a_uint16_t  ts_nsec:16;
+};
+
+union ptp_trigger0_timestamp4_reg_u {
+	a_uint32_t val;
+	struct ptp_trigger0_timestamp4_reg bf;
+};
+
+/*[register] PTP_TRIGGER1_TIMESTAMP0_REG*/
+#define PTP_TRIGGER1_TIMESTAMP0_REG
+#define PTP_TRIGGER1_TIMESTAMP0_REG_ADDRESS 0x8409
+#define PTP_TRIGGER1_TIMESTAMP0_REG_NUM     1
+#define PTP_TRIGGER1_TIMESTAMP0_REG_INC     0x1
+#define PTP_TRIGGER1_TIMESTAMP0_REG_TYPE    REG_TYPE_RW
+#define PTP_TRIGGER1_TIMESTAMP0_REG_DEFAULT 0x0
+	/*[field] TS_SEC*/
+	#define PTP_TRIGGER1_TIMESTAMP0_REG_TS_SEC
+	#define PTP_TRIGGER1_TIMESTAMP0_REG_TS_SEC_OFFSET  0
+	#define PTP_TRIGGER1_TIMESTAMP0_REG_TS_SEC_LEN     16
+	#define PTP_TRIGGER1_TIMESTAMP0_REG_TS_SEC_DEFAULT 0x0
+
+struct ptp_trigger1_timestamp0_reg {
+	a_uint16_t  ts_sec:16;
+};
+
+union ptp_trigger1_timestamp0_reg_u {
+	a_uint32_t val;
+	struct ptp_trigger1_timestamp0_reg bf;
+};
+
+/*[register] PTP_TRIGGER1_TIMESTAMP1_REG*/
+#define PTP_TRIGGER1_TIMESTAMP1_REG
+#define PTP_TRIGGER1_TIMESTAMP1_REG_ADDRESS 0x840a
+#define PTP_TRIGGER1_TIMESTAMP1_REG_NUM     1
+#define PTP_TRIGGER1_TIMESTAMP1_REG_INC     0x1
+#define PTP_TRIGGER1_TIMESTAMP1_REG_TYPE    REG_TYPE_RW
+#define PTP_TRIGGER1_TIMESTAMP1_REG_DEFAULT 0x0
+	/*[field] TS_SEC*/
+	#define PTP_TRIGGER1_TIMESTAMP1_REG_TS_SEC
+	#define PTP_TRIGGER1_TIMESTAMP1_REG_TS_SEC_OFFSET  0
+	#define PTP_TRIGGER1_TIMESTAMP1_REG_TS_SEC_LEN     16
+	#define PTP_TRIGGER1_TIMESTAMP1_REG_TS_SEC_DEFAULT 0x0
+
+struct ptp_trigger1_timestamp1_reg {
+	a_uint16_t  ts_sec:16;
+};
+
+union ptp_trigger1_timestamp1_reg_u {
+	a_uint32_t val;
+	struct ptp_trigger1_timestamp1_reg bf;
+};
+
+/*[register] PTP_TRIGGER1_TIMESTAMP2_REG*/
+#define PTP_TRIGGER1_TIMESTAMP2_REG
+#define PTP_TRIGGER1_TIMESTAMP2_REG_ADDRESS 0x840b
+#define PTP_TRIGGER1_TIMESTAMP2_REG_NUM     1
+#define PTP_TRIGGER1_TIMESTAMP2_REG_INC     0x1
+#define PTP_TRIGGER1_TIMESTAMP2_REG_TYPE    REG_TYPE_RW
+#define PTP_TRIGGER1_TIMESTAMP2_REG_DEFAULT 0x0
+	/*[field] TS_SEC*/
+	#define PTP_TRIGGER1_TIMESTAMP2_REG_TS_SEC
+	#define PTP_TRIGGER1_TIMESTAMP2_REG_TS_SEC_OFFSET  0
+	#define PTP_TRIGGER1_TIMESTAMP2_REG_TS_SEC_LEN     16
+	#define PTP_TRIGGER1_TIMESTAMP2_REG_TS_SEC_DEFAULT 0x0
+
+struct ptp_trigger1_timestamp2_reg {
+	a_uint16_t  ts_sec:16;
+};
+
+union ptp_trigger1_timestamp2_reg_u {
+	a_uint32_t val;
+	struct ptp_trigger1_timestamp2_reg bf;
+};
+
+/*[register] PTP_TRIGGER1_TIMESTAMP3_REG*/
+#define PTP_TRIGGER1_TIMESTAMP3_REG
+#define PTP_TRIGGER1_TIMESTAMP3_REG_ADDRESS 0x840c
+#define PTP_TRIGGER1_TIMESTAMP3_REG_NUM     1
+#define PTP_TRIGGER1_TIMESTAMP3_REG_INC     0x1
+#define PTP_TRIGGER1_TIMESTAMP3_REG_TYPE    REG_TYPE_RW
+#define PTP_TRIGGER1_TIMESTAMP3_REG_DEFAULT 0x0
+	/*[field] TS_NSEC*/
+	#define PTP_TRIGGER1_TIMESTAMP3_REG_TS_NSEC
+	#define PTP_TRIGGER1_TIMESTAMP3_REG_TS_NSEC_OFFSET  0
+	#define PTP_TRIGGER1_TIMESTAMP3_REG_TS_NSEC_LEN     16
+	#define PTP_TRIGGER1_TIMESTAMP3_REG_TS_NSEC_DEFAULT 0x0
+
+struct ptp_trigger1_timestamp3_reg {
+	a_uint16_t  ts_nsec:16;
+};
+
+union ptp_trigger1_timestamp3_reg_u {
+	a_uint32_t val;
+	struct ptp_trigger1_timestamp3_reg bf;
+};
+
+/*[register] PTP_TRIGGER1_TIMESTAMP4_REG*/
+#define PTP_TRIGGER1_TIMESTAMP4_REG
+#define PTP_TRIGGER1_TIMESTAMP4_REG_ADDRESS 0x840d
+#define PTP_TRIGGER1_TIMESTAMP4_REG_NUM     1
+#define PTP_TRIGGER1_TIMESTAMP4_REG_INC     0x1
+#define PTP_TRIGGER1_TIMESTAMP4_REG_TYPE    REG_TYPE_RW
+#define PTP_TRIGGER1_TIMESTAMP4_REG_DEFAULT 0x0
+	/*[field] TS_NSEC*/
+	#define PTP_TRIGGER1_TIMESTAMP4_REG_TS_NSEC
+	#define PTP_TRIGGER1_TIMESTAMP4_REG_TS_NSEC_OFFSET  0
+	#define PTP_TRIGGER1_TIMESTAMP4_REG_TS_NSEC_LEN     16
+	#define PTP_TRIGGER1_TIMESTAMP4_REG_TS_NSEC_DEFAULT 0x0
+
+struct ptp_trigger1_timestamp4_reg {
+	a_uint16_t  ts_nsec:16;
+};
+
+union ptp_trigger1_timestamp4_reg_u {
+	a_uint32_t val;
+	struct ptp_trigger1_timestamp4_reg bf;
+};
+
+/*[register] PTP_EVENT0_CONFIG_REG*/
+#define PTP_EVENT0_CONFIG_REG
+#define PTP_EVENT0_CONFIG_REG_ADDRESS 0x840e
+#define PTP_EVENT0_CONFIG_REG_NUM     1
+#define PTP_EVENT0_CONFIG_REG_INC     0x1
+#define PTP_EVENT0_CONFIG_REG_TYPE    REG_TYPE_RW
+#define PTP_EVENT0_CONFIG_REG_DEFAULT 0x0
+	/*[field] CLEAR_STAT*/
+	#define PTP_EVENT0_CONFIG_REG_CLEAR_STAT
+	#define PTP_EVENT0_CONFIG_REG_CLEAR_STAT_OFFSET  0
+	#define PTP_EVENT0_CONFIG_REG_CLEAR_STAT_LEN     1
+	#define PTP_EVENT0_CONFIG_REG_CLEAR_STAT_DEFAULT 0x0
+	/*[field] NOTIFY*/
+	#define PTP_EVENT0_CONFIG_REG_NOTIFY
+	#define PTP_EVENT0_CONFIG_REG_NOTIFY_OFFSET  1
+	#define PTP_EVENT0_CONFIG_REG_NOTIFY_LEN     1
+	#define PTP_EVENT0_CONFIG_REG_NOTIFY_DEFAULT 0x0
+	/*[field] SINGLE_CAP*/
+	#define PTP_EVENT0_CONFIG_REG_SINGLE_CAP
+	#define PTP_EVENT0_CONFIG_REG_SINGLE_CAP_OFFSET  2
+	#define PTP_EVENT0_CONFIG_REG_SINGLE_CAP_LEN     1
+	#define PTP_EVENT0_CONFIG_REG_SINGLE_CAP_DEFAULT 0x0
+	/*[field] FALL_EN*/
+	#define PTP_EVENT0_CONFIG_REG_FALL_EN
+	#define PTP_EVENT0_CONFIG_REG_FALL_EN_OFFSET  3
+	#define PTP_EVENT0_CONFIG_REG_FALL_EN_LEN     1
+	#define PTP_EVENT0_CONFIG_REG_FALL_EN_DEFAULT 0x0
+	/*[field] RISE_EN*/
+	#define PTP_EVENT0_CONFIG_REG_RISE_EN
+	#define PTP_EVENT0_CONFIG_REG_RISE_EN_OFFSET  4
+	#define PTP_EVENT0_CONFIG_REG_RISE_EN_LEN     1
+	#define PTP_EVENT0_CONFIG_REG_RISE_EN_DEFAULT 0x0
+
+struct ptp_event0_config_reg {
+	a_uint16_t  clear_stat:1;
+	a_uint16_t  notify:1;
+	a_uint16_t  single_cap:1;
+	a_uint16_t  fall_en:1;
+	a_uint16_t  rise_en:1;
+};
+
+union ptp_event0_config_reg_u {
+	a_uint32_t val;
+	struct ptp_event0_config_reg bf;
+};
+
+/*[register] PTP_EVENT0_STATUS_REG*/
+#define PTP_EVENT0_STATUS_REG
+#define PTP_EVENT0_STATUS_REG_ADDRESS 0x840f
+#define PTP_EVENT0_STATUS_REG_NUM     1
+#define PTP_EVENT0_STATUS_REG_INC     0x1
+#define PTP_EVENT0_STATUS_REG_TYPE    REG_TYPE_RW
+#define PTP_EVENT0_STATUS_REG_DEFAULT 0x0
+	/*[field] DETECTED*/
+	#define PTP_EVENT0_STATUS_REG_DETECTED
+	#define PTP_EVENT0_STATUS_REG_DETECTED_OFFSET  0
+	#define PTP_EVENT0_STATUS_REG_DETECTED_LEN     1
+	#define PTP_EVENT0_STATUS_REG_DETECTED_DEFAULT 0x0
+	/*[field] DIR_DETECTED*/
+	#define PTP_EVENT0_STATUS_REG_DIR_DETECTED
+	#define PTP_EVENT0_STATUS_REG_DIR_DETECTED_OFFSET  1
+	#define PTP_EVENT0_STATUS_REG_DIR_DETECTED_LEN     1
+	#define PTP_EVENT0_STATUS_REG_DIR_DETECTED_DEFAULT 0x0
+	/*[field] MUL_EVENT*/
+	#define PTP_EVENT0_STATUS_REG_MUL_EVENT
+	#define PTP_EVENT0_STATUS_REG_MUL_EVENT_OFFSET  2
+	#define PTP_EVENT0_STATUS_REG_MUL_EVENT_LEN     1
+	#define PTP_EVENT0_STATUS_REG_MUL_EVENT_DEFAULT 0x0
+	/*[field] MISSED_COUNT*/
+	#define PTP_EVENT0_STATUS_REG_MISSED_COUNT
+	#define PTP_EVENT0_STATUS_REG_MISSED_COUNT_OFFSET  3
+	#define PTP_EVENT0_STATUS_REG_MISSED_COUNT_LEN     4
+	#define PTP_EVENT0_STATUS_REG_MISSED_COUNT_DEFAULT 0x0
+
+struct ptp_event0_status_reg {
+	a_uint16_t  detected:1;
+	a_uint16_t  dir_detected:1;
+	a_uint16_t  mul_event:1;
+	a_uint16_t  missed_count:4;
+};
+
+union ptp_event0_status_reg_u {
+	a_uint32_t val;
+	struct ptp_event0_status_reg bf;
+};
+
+/*[register] PTP_EVENT1_CONFIG_REG*/
+#define PTP_EVENT1_CONFIG_REG
+#define PTP_EVENT1_CONFIG_REG_ADDRESS 0x8410
+#define PTP_EVENT1_CONFIG_REG_NUM     1
+#define PTP_EVENT1_CONFIG_REG_INC     0x1
+#define PTP_EVENT1_CONFIG_REG_TYPE    REG_TYPE_RW
+#define PTP_EVENT1_CONFIG_REG_DEFAULT 0x0
+	/*[field] CLEAR_STAT*/
+	#define PTP_EVENT1_CONFIG_REG_CLEAR_STAT
+	#define PTP_EVENT1_CONFIG_REG_CLEAR_STAT_OFFSET  0
+	#define PTP_EVENT1_CONFIG_REG_CLEAR_STAT_LEN     1
+	#define PTP_EVENT1_CONFIG_REG_CLEAR_STAT_DEFAULT 0x0
+	/*[field] NOTIFY*/
+	#define PTP_EVENT1_CONFIG_REG_NOTIFY
+	#define PTP_EVENT1_CONFIG_REG_NOTIFY_OFFSET  1
+	#define PTP_EVENT1_CONFIG_REG_NOTIFY_LEN     1
+	#define PTP_EVENT1_CONFIG_REG_NOTIFY_DEFAULT 0x0
+	/*[field] SINGLE_CAP*/
+	#define PTP_EVENT1_CONFIG_REG_SINGLE_CAP
+	#define PTP_EVENT1_CONFIG_REG_SINGLE_CAP_OFFSET  2
+	#define PTP_EVENT1_CONFIG_REG_SINGLE_CAP_LEN     1
+	#define PTP_EVENT1_CONFIG_REG_SINGLE_CAP_DEFAULT 0x0
+	/*[field] FALL_EN*/
+	#define PTP_EVENT1_CONFIG_REG_FALL_EN
+	#define PTP_EVENT1_CONFIG_REG_FALL_EN_OFFSET  3
+	#define PTP_EVENT1_CONFIG_REG_FALL_EN_LEN     1
+	#define PTP_EVENT1_CONFIG_REG_FALL_EN_DEFAULT 0x0
+	/*[field] RISE_EN*/
+	#define PTP_EVENT1_CONFIG_REG_RISE_EN
+	#define PTP_EVENT1_CONFIG_REG_RISE_EN_OFFSET  4
+	#define PTP_EVENT1_CONFIG_REG_RISE_EN_LEN     1
+	#define PTP_EVENT1_CONFIG_REG_RISE_EN_DEFAULT 0x0
+
+struct ptp_event1_config_reg {
+	a_uint16_t  clear_stat:1;
+	a_uint16_t  notify:1;
+	a_uint16_t  single_cap:1;
+	a_uint16_t  fall_en:1;
+	a_uint16_t  rise_en:1;
+};
+
+union ptp_event1_config_reg_u {
+	a_uint32_t val;
+	struct ptp_event1_config_reg bf;
+};
+
+/*[register] PTP_EVENT1_STATUS_REG*/
+#define PTP_EVENT1_STATUS_REG
+#define PTP_EVENT1_STATUS_REG_ADDRESS 0x8411
+#define PTP_EVENT1_STATUS_REG_NUM     1
+#define PTP_EVENT1_STATUS_REG_INC     0x1
+#define PTP_EVENT1_STATUS_REG_TYPE    REG_TYPE_RW
+#define PTP_EVENT1_STATUS_REG_DEFAULT 0x0
+	/*[field] DETECTED*/
+	#define PTP_EVENT1_STATUS_REG_DETECTED
+	#define PTP_EVENT1_STATUS_REG_DETECTED_OFFSET  0
+	#define PTP_EVENT1_STATUS_REG_DETECTED_LEN     1
+	#define PTP_EVENT1_STATUS_REG_DETECTED_DEFAULT 0x0
+	/*[field] DIR_DETECTED*/
+	#define PTP_EVENT1_STATUS_REG_DIR_DETECTED
+	#define PTP_EVENT1_STATUS_REG_DIR_DETECTED_OFFSET  1
+	#define PTP_EVENT1_STATUS_REG_DIR_DETECTED_LEN     1
+	#define PTP_EVENT1_STATUS_REG_DIR_DETECTED_DEFAULT 0x0
+	/*[field] MUL_EVENT*/
+	#define PTP_EVENT1_STATUS_REG_MUL_EVENT
+	#define PTP_EVENT1_STATUS_REG_MUL_EVENT_OFFSET  2
+	#define PTP_EVENT1_STATUS_REG_MUL_EVENT_LEN     1
+	#define PTP_EVENT1_STATUS_REG_MUL_EVENT_DEFAULT 0x0
+	/*[field] MISSED_COUNT*/
+	#define PTP_EVENT1_STATUS_REG_MISSED_COUNT
+	#define PTP_EVENT1_STATUS_REG_MISSED_COUNT_OFFSET  3
+	#define PTP_EVENT1_STATUS_REG_MISSED_COUNT_LEN     4
+	#define PTP_EVENT1_STATUS_REG_MISSED_COUNT_DEFAULT 0x0
+
+struct ptp_event1_status_reg {
+	a_uint16_t  detected:1;
+	a_uint16_t  dir_detected:1;
+	a_uint16_t  mul_event:1;
+	a_uint16_t  missed_count:4;
+};
+
+union ptp_event1_status_reg_u {
+	a_uint32_t val;
+	struct ptp_event1_status_reg bf;
+};
+
+/*[register] PTP_EVENT0_TIMESTAMP0_REG*/
+#define PTP_EVENT0_TIMESTAMP0_REG
+#define PTP_EVENT0_TIMESTAMP0_REG_ADDRESS 0x8412
+#define PTP_EVENT0_TIMESTAMP0_REG_NUM     1
+#define PTP_EVENT0_TIMESTAMP0_REG_INC     0x1
+#define PTP_EVENT0_TIMESTAMP0_REG_TYPE    REG_TYPE_RW
+#define PTP_EVENT0_TIMESTAMP0_REG_DEFAULT 0x0
+	/*[field] TS_NSEC*/
+	#define PTP_EVENT0_TIMESTAMP0_REG_TS_NSEC
+	#define PTP_EVENT0_TIMESTAMP0_REG_TS_NSEC_OFFSET  0
+	#define PTP_EVENT0_TIMESTAMP0_REG_TS_NSEC_LEN     16
+	#define PTP_EVENT0_TIMESTAMP0_REG_TS_NSEC_DEFAULT 0x0
+
+struct ptp_event0_timestamp0_reg {
+	a_uint16_t  ts_nsec:16;
+};
+
+union ptp_event0_timestamp0_reg_u {
+	a_uint32_t val;
+	struct ptp_event0_timestamp0_reg bf;
+};
+
+/*[register] PTP_EVENT0_TIMESTAMP1_REG*/
+#define PTP_EVENT0_TIMESTAMP1_REG
+#define PTP_EVENT0_TIMESTAMP1_REG_ADDRESS 0x8413
+#define PTP_EVENT0_TIMESTAMP1_REG_NUM     1
+#define PTP_EVENT0_TIMESTAMP1_REG_INC     0x1
+#define PTP_EVENT0_TIMESTAMP1_REG_TYPE    REG_TYPE_RW
+#define PTP_EVENT0_TIMESTAMP1_REG_DEFAULT 0x0
+	/*[field] TS_NSEC*/
+	#define PTP_EVENT0_TIMESTAMP1_REG_TS_NSEC
+	#define PTP_EVENT0_TIMESTAMP1_REG_TS_NSEC_OFFSET  0
+	#define PTP_EVENT0_TIMESTAMP1_REG_TS_NSEC_LEN     16
+	#define PTP_EVENT0_TIMESTAMP1_REG_TS_NSEC_DEFAULT 0x0
+
+struct ptp_event0_timestamp1_reg {
+	a_uint16_t  ts_nsec:16;
+};
+
+union ptp_event0_timestamp1_reg_u {
+	a_uint32_t val;
+	struct ptp_event0_timestamp1_reg bf;
+};
+
+/*[register] PTP_EVENT0_TIMESTAMP2_REG*/
+#define PTP_EVENT0_TIMESTAMP2_REG
+#define PTP_EVENT0_TIMESTAMP2_REG_ADDRESS 0x8414
+#define PTP_EVENT0_TIMESTAMP2_REG_NUM     1
+#define PTP_EVENT0_TIMESTAMP2_REG_INC     0x1
+#define PTP_EVENT0_TIMESTAMP2_REG_TYPE    REG_TYPE_RW
+#define PTP_EVENT0_TIMESTAMP2_REG_DEFAULT 0x0
+	/*[field] TS_NSEC*/
+	#define PTP_EVENT0_TIMESTAMP2_REG_TS_NSEC
+	#define PTP_EVENT0_TIMESTAMP2_REG_TS_NSEC_OFFSET  0
+	#define PTP_EVENT0_TIMESTAMP2_REG_TS_NSEC_LEN     16
+	#define PTP_EVENT0_TIMESTAMP2_REG_TS_NSEC_DEFAULT 0x0
+
+struct ptp_event0_timestamp2_reg {
+	a_uint16_t  ts_nsec:16;
+};
+
+union ptp_event0_timestamp2_reg_u {
+	a_uint32_t val;
+	struct ptp_event0_timestamp2_reg bf;
+};
+
+/*[register] PTP_EVENT0_TIMESTAMP3_REG*/
+#define PTP_EVENT0_TIMESTAMP3_REG
+#define PTP_EVENT0_TIMESTAMP3_REG_ADDRESS 0x8415
+#define PTP_EVENT0_TIMESTAMP3_REG_NUM     1
+#define PTP_EVENT0_TIMESTAMP3_REG_INC     0x1
+#define PTP_EVENT0_TIMESTAMP3_REG_TYPE    REG_TYPE_RW
+#define PTP_EVENT0_TIMESTAMP3_REG_DEFAULT 0x0
+	/*[field] TS_NSEC*/
+	#define PTP_EVENT0_TIMESTAMP3_REG_TS_NSEC
+	#define PTP_EVENT0_TIMESTAMP3_REG_TS_NSEC_OFFSET  0
+	#define PTP_EVENT0_TIMESTAMP3_REG_TS_NSEC_LEN     16
+	#define PTP_EVENT0_TIMESTAMP3_REG_TS_NSEC_DEFAULT 0x0
+
+struct ptp_event0_timestamp3_reg {
+	a_uint16_t  ts_nsec:16;
+};
+
+union ptp_event0_timestamp3_reg_u {
+	a_uint32_t val;
+	struct ptp_event0_timestamp3_reg bf;
+};
+
+/*[register] PTP_EVENT0_TIMESTAMP4_REG*/
+#define PTP_EVENT0_TIMESTAMP4_REG
+#define PTP_EVENT0_TIMESTAMP4_REG_ADDRESS 0x8416
+#define PTP_EVENT0_TIMESTAMP4_REG_NUM     1
+#define PTP_EVENT0_TIMESTAMP4_REG_INC     0x1
+#define PTP_EVENT0_TIMESTAMP4_REG_TYPE    REG_TYPE_RW
+#define PTP_EVENT0_TIMESTAMP4_REG_DEFAULT 0x0
+	/*[field] TS_NSEC*/
+	#define PTP_EVENT0_TIMESTAMP4_REG_TS_NSEC
+	#define PTP_EVENT0_TIMESTAMP4_REG_TS_NSEC_OFFSET  0
+	#define PTP_EVENT0_TIMESTAMP4_REG_TS_NSEC_LEN     16
+	#define PTP_EVENT0_TIMESTAMP4_REG_TS_NSEC_DEFAULT 0x0
+
+struct ptp_event0_timestamp4_reg {
+	a_uint16_t  ts_nsec:16;
+};
+
+union ptp_event0_timestamp4_reg_u {
+	a_uint32_t val;
+	struct ptp_event0_timestamp4_reg bf;
+};
+
+/*[register] PTP_EVENT1_TIMESTAMP0_REG*/
+#define PTP_EVENT1_TIMESTAMP0_REG
+#define PTP_EVENT1_TIMESTAMP0_REG_ADDRESS 0x8417
+#define PTP_EVENT1_TIMESTAMP0_REG_NUM     1
+#define PTP_EVENT1_TIMESTAMP0_REG_INC     0x1
+#define PTP_EVENT1_TIMESTAMP0_REG_TYPE    REG_TYPE_RW
+#define PTP_EVENT1_TIMESTAMP0_REG_DEFAULT 0x0
+	/*[field] TS_NSEC*/
+	#define PTP_EVENT1_TIMESTAMP0_REG_TS_NSEC
+	#define PTP_EVENT1_TIMESTAMP0_REG_TS_NSEC_OFFSET  0
+	#define PTP_EVENT1_TIMESTAMP0_REG_TS_NSEC_LEN     16
+	#define PTP_EVENT1_TIMESTAMP0_REG_TS_NSEC_DEFAULT 0x0
+
+struct ptp_event1_timestamp0_reg {
+	a_uint16_t  ts_nsec:16;
+};
+
+union ptp_event1_timestamp0_reg_u {
+	a_uint32_t val;
+	struct ptp_event1_timestamp0_reg bf;
+};
+
+/*[register] PTP_EVENT1_TIMESTAMP1_REG*/
+#define PTP_EVENT1_TIMESTAMP1_REG
+#define PTP_EVENT1_TIMESTAMP1_REG_ADDRESS 0x8418
+#define PTP_EVENT1_TIMESTAMP1_REG_NUM     1
+#define PTP_EVENT1_TIMESTAMP1_REG_INC     0x1
+#define PTP_EVENT1_TIMESTAMP1_REG_TYPE    REG_TYPE_RW
+#define PTP_EVENT1_TIMESTAMP1_REG_DEFAULT 0x0
+	/*[field] TS_NSEC*/
+	#define PTP_EVENT1_TIMESTAMP1_REG_TS_NSEC
+	#define PTP_EVENT1_TIMESTAMP1_REG_TS_NSEC_OFFSET  0
+	#define PTP_EVENT1_TIMESTAMP1_REG_TS_NSEC_LEN     16
+	#define PTP_EVENT1_TIMESTAMP1_REG_TS_NSEC_DEFAULT 0x0
+
+struct ptp_event1_timestamp1_reg {
+	a_uint16_t  ts_nsec:16;
+};
+
+union ptp_event1_timestamp1_reg_u {
+	a_uint32_t val;
+	struct ptp_event1_timestamp1_reg bf;
+};
+
+/*[register] PTP_EVENT1_TIMESTAMP2_REG*/
+#define PTP_EVENT1_TIMESTAMP2_REG
+#define PTP_EVENT1_TIMESTAMP2_REG_ADDRESS 0x8419
+#define PTP_EVENT1_TIMESTAMP2_REG_NUM     1
+#define PTP_EVENT1_TIMESTAMP2_REG_INC     0x1
+#define PTP_EVENT1_TIMESTAMP2_REG_TYPE    REG_TYPE_RW
+#define PTP_EVENT1_TIMESTAMP2_REG_DEFAULT 0x0
+	/*[field] TS_NSEC*/
+	#define PTP_EVENT1_TIMESTAMP2_REG_TS_NSEC
+	#define PTP_EVENT1_TIMESTAMP2_REG_TS_NSEC_OFFSET  0
+	#define PTP_EVENT1_TIMESTAMP2_REG_TS_NSEC_LEN     16
+	#define PTP_EVENT1_TIMESTAMP2_REG_TS_NSEC_DEFAULT 0x0
+
+struct ptp_event1_timestamp2_reg {
+	a_uint16_t  ts_nsec:16;
+};
+
+union ptp_event1_timestamp2_reg_u {
+	a_uint32_t val;
+	struct ptp_event1_timestamp2_reg bf;
+};
+
+/*[register] PTP_EVENT1_TIMESTAMP3_REG*/
+#define PTP_EVENT1_TIMESTAMP3_REG
+#define PTP_EVENT1_TIMESTAMP3_REG_ADDRESS 0x841a
+#define PTP_EVENT1_TIMESTAMP3_REG_NUM     1
+#define PTP_EVENT1_TIMESTAMP3_REG_INC     0x4
+#define PTP_EVENT1_TIMESTAMP3_REG_TYPE    REG_TYPE_RW
+#define PTP_EVENT1_TIMESTAMP3_REG_DEFAULT 0x0
+	/*[field] TS_NSEC*/
+	#define PTP_EVENT1_TIMESTAMP3_REG_TS_NSEC
+	#define PTP_EVENT1_TIMESTAMP3_REG_TS_NSEC_OFFSET  0
+	#define PTP_EVENT1_TIMESTAMP3_REG_TS_NSEC_LEN     16
+	#define PTP_EVENT1_TIMESTAMP3_REG_TS_NSEC_DEFAULT 0x0
+
+struct ptp_event1_timestamp3_reg {
+	a_uint16_t  ts_nsec:16;
+};
+
+union ptp_event1_timestamp3_reg_u {
+	a_uint32_t val;
+	struct ptp_event1_timestamp3_reg bf;
+};
+
+/*[register] PTP_EVENT1_TIMESTAMP4_REG*/
+#define PTP_EVENT1_TIMESTAMP4_REG
+#define PTP_EVENT1_TIMESTAMP4_REG_ADDRESS 0x841b
+#define PTP_EVENT1_TIMESTAMP4_REG_NUM     1
+#define PTP_EVENT1_TIMESTAMP4_REG_INC     0x1
+#define PTP_EVENT1_TIMESTAMP4_REG_TYPE    REG_TYPE_RW
+#define PTP_EVENT1_TIMESTAMP4_REG_DEFAULT 0x0
+	/*[field] TS_NSEC*/
+	#define PTP_EVENT1_TIMESTAMP4_REG_TS_NSEC
+	#define PTP_EVENT1_TIMESTAMP4_REG_TS_NSEC_OFFSET  0
+	#define PTP_EVENT1_TIMESTAMP4_REG_TS_NSEC_LEN     16
+	#define PTP_EVENT1_TIMESTAMP4_REG_TS_NSEC_DEFAULT 0x0
+
+struct ptp_event1_timestamp4_reg {
+	a_uint16_t  ts_nsec:16;
+};
+
+union ptp_event1_timestamp4_reg_u {
+	a_uint32_t val;
+	struct ptp_event1_timestamp4_reg bf;
+};
+
+/*[register] PTP_RX_SEQID1_REG*/
+#define PTP_RX_SEQID1_REG
+#define PTP_RX_SEQID1_REG_ADDRESS 0x8500
+#define PTP_RX_SEQID1_REG_NUM     1
+#define PTP_RX_SEQID1_REG_INC     0x1
+#define PTP_RX_SEQID1_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_SEQID1_REG_DEFAULT 0x0
+	/*[field] RX_SEQID*/
+	#define PTP_RX_SEQID1_REG_RX_SEQID
+	#define PTP_RX_SEQID1_REG_RX_SEQID_OFFSET  0
+	#define PTP_RX_SEQID1_REG_RX_SEQID_LEN     16
+	#define PTP_RX_SEQID1_REG_RX_SEQID_DEFAULT 0x0
+
+struct ptp_rx_seqid1_reg {
+	a_uint16_t  rx_seqid:16;
+};
+
+union ptp_rx_seqid1_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_seqid1_reg bf;
+};
+
+/*[register] PTP_RX_PORTID1_0_REG*/
+#define PTP_RX_PORTID1_0_REG
+#define PTP_RX_PORTID1_0_REG_ADDRESS 0x8501
+#define PTP_RX_PORTID1_0_REG_NUM     1
+#define PTP_RX_PORTID1_0_REG_INC     0x1
+#define PTP_RX_PORTID1_0_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID1_0_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID1_0_REG_RX_PORTID
+	#define PTP_RX_PORTID1_0_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID1_0_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID1_0_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid1_0_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid1_0_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid1_0_reg bf;
+};
+
+/*[register] PTP_RX_PORTID1_1_REG*/
+#define PTP_RX_PORTID1_1_REG
+#define PTP_RX_PORTID1_1_REG_ADDRESS 0x8502
+#define PTP_RX_PORTID1_1_REG_NUM     1
+#define PTP_RX_PORTID1_1_REG_INC     0x1
+#define PTP_RX_PORTID1_1_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID1_1_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID1_1_REG_RX_PORTID
+	#define PTP_RX_PORTID1_1_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID1_1_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID1_1_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid1_1_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid1_1_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid1_1_reg bf;
+};
+
+/*[register] PTP_RX_PORTID1_2_REG*/
+#define PTP_RX_PORTID1_2_REG
+#define PTP_RX_PORTID1_2_REG_ADDRESS 0x8503
+#define PTP_RX_PORTID1_2_REG_NUM     1
+#define PTP_RX_PORTID1_2_REG_INC     0x1
+#define PTP_RX_PORTID1_2_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID1_2_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID1_2_REG_RX_PORTID
+	#define PTP_RX_PORTID1_2_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID1_2_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID1_2_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid1_2_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid1_2_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid1_2_reg bf;
+};
+
+/*[register] PTP_RX_PORTID1_3_REG*/
+#define PTP_RX_PORTID1_3_REG
+#define PTP_RX_PORTID1_3_REG_ADDRESS 0x8504
+#define PTP_RX_PORTID1_3_REG_NUM     1
+#define PTP_RX_PORTID1_3_REG_INC     0x1
+#define PTP_RX_PORTID1_3_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID1_3_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID1_3_REG_RX_PORTID
+	#define PTP_RX_PORTID1_3_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID1_3_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID1_3_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid1_3_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid1_3_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid1_3_reg bf;
+};
+
+/*[register] PTP_RX_PORTID1_4_REG*/
+#define PTP_RX_PORTID1_4_REG
+#define PTP_RX_PORTID1_4_REG_ADDRESS 0x8505
+#define PTP_RX_PORTID1_4_REG_NUM     1
+#define PTP_RX_PORTID1_4_REG_INC     0x1
+#define PTP_RX_PORTID1_4_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID1_4_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID1_4_REG_RX_PORTID
+	#define PTP_RX_PORTID1_4_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID1_4_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID1_4_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid1_4_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid1_4_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid1_4_reg bf;
+};
+
+/*[register] PTP_RX_TS1_0_REG*/
+#define PTP_RX_TS1_0_REG
+#define PTP_RX_TS1_0_REG_ADDRESS 0x8506
+#define PTP_RX_TS1_0_REG_NUM     1
+#define PTP_RX_TS1_0_REG_INC     0x1
+#define PTP_RX_TS1_0_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS1_0_REG_DEFAULT 0x0
+	/*[field] RX_TS_SEC*/
+	#define PTP_RX_TS1_0_REG_RX_TS_SEC
+	#define PTP_RX_TS1_0_REG_RX_TS_SEC_OFFSET  0
+	#define PTP_RX_TS1_0_REG_RX_TS_SEC_LEN     16
+	#define PTP_RX_TS1_0_REG_RX_TS_SEC_DEFAULT 0x0
+
+struct ptp_rx_ts1_0_reg {
+	a_uint16_t  rx_ts_sec:16;
+};
+
+union ptp_rx_ts1_0_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts1_0_reg bf;
+};
+
+/*[register] PTP_RX_TS1_1_REG*/
+#define PTP_RX_TS1_1_REG
+#define PTP_RX_TS1_1_REG_ADDRESS 0x8507
+#define PTP_RX_TS1_1_REG_NUM     1
+#define PTP_RX_TS1_1_REG_INC     0x1
+#define PTP_RX_TS1_1_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS1_1_REG_DEFAULT 0x0
+	/*[field] RX_TS_SEC*/
+	#define PTP_RX_TS1_1_REG_RX_TS_SEC
+	#define PTP_RX_TS1_1_REG_RX_TS_SEC_OFFSET  0
+	#define PTP_RX_TS1_1_REG_RX_TS_SEC_LEN     16
+	#define PTP_RX_TS1_1_REG_RX_TS_SEC_DEFAULT 0x0
+
+struct ptp_rx_ts1_1_reg {
+	a_uint16_t  rx_ts_sec:16;
+};
+
+union ptp_rx_ts1_1_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts1_1_reg bf;
+};
+
+/*[register] PTP_RX_TS1_2_REG*/
+#define PTP_RX_TS1_2_REG
+#define PTP_RX_TS1_2_REG_ADDRESS 0x8508
+#define PTP_RX_TS1_2_REG_NUM     1
+#define PTP_RX_TS1_2_REG_INC     0x1
+#define PTP_RX_TS1_2_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS1_2_REG_DEFAULT 0x0
+	/*[field] RX_TS_SEC*/
+	#define PTP_RX_TS1_2_REG_RX_TS_SEC
+	#define PTP_RX_TS1_2_REG_RX_TS_SEC_OFFSET  0
+	#define PTP_RX_TS1_2_REG_RX_TS_SEC_LEN     16
+	#define PTP_RX_TS1_2_REG_RX_TS_SEC_DEFAULT 0x0
+
+struct ptp_rx_ts1_2_reg {
+	a_uint16_t  rx_ts_sec:16;
+};
+
+union ptp_rx_ts1_2_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts1_2_reg bf;
+};
+
+/*[register] PTP_RX_TS1_3_REG*/
+#define PTP_RX_TS1_3_REG
+#define PTP_RX_TS1_3_REG_ADDRESS 0x8509
+#define PTP_RX_TS1_3_REG_NUM     1
+#define PTP_RX_TS1_3_REG_INC     0x1
+#define PTP_RX_TS1_3_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS1_3_REG_DEFAULT 0x0
+	/*[field] RX_TS_NSEC*/
+	#define PTP_RX_TS1_3_REG_RX_TS_NSEC
+	#define PTP_RX_TS1_3_REG_RX_TS_NSEC_OFFSET  0
+	#define PTP_RX_TS1_3_REG_RX_TS_NSEC_LEN     16
+	#define PTP_RX_TS1_3_REG_RX_TS_NSEC_DEFAULT 0x0
+
+struct ptp_rx_ts1_3_reg {
+	a_uint16_t  rx_ts_nsec:16;
+};
+
+union ptp_rx_ts1_3_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts1_3_reg bf;
+};
+
+/*[register] PTP_RX_TS1_4_REG*/
+#define PTP_RX_TS1_4_REG
+#define PTP_RX_TS1_4_REG_ADDRESS 0x850a
+#define PTP_RX_TS1_4_REG_NUM     1
+#define PTP_RX_TS1_4_REG_INC     0x1
+#define PTP_RX_TS1_4_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS1_4_REG_DEFAULT 0x0
+	/*[field] RX_TS_NSEC*/
+	#define PTP_RX_TS1_4_REG_RX_TS_NSEC
+	#define PTP_RX_TS1_4_REG_RX_TS_NSEC_OFFSET  0
+	#define PTP_RX_TS1_4_REG_RX_TS_NSEC_LEN     16
+	#define PTP_RX_TS1_4_REG_RX_TS_NSEC_DEFAULT 0x0
+
+struct ptp_rx_ts1_4_reg {
+	a_uint16_t  rx_ts_nsec:16;
+};
+
+union ptp_rx_ts1_4_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts1_4_reg bf;
+};
+
+/*[register] PTP_RX_TS1_5_REG*/
+#define PTP_RX_TS1_5_REG
+#define PTP_RX_TS1_5_REG_ADDRESS 0x850b
+#define PTP_RX_TS1_5_REG_NUM     1
+#define PTP_RX_TS1_5_REG_INC     0x1
+#define PTP_RX_TS1_5_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS1_5_REG_DEFAULT 0x0
+	/*[field] RX_TS_NFSEC*/
+	#define PTP_RX_TS1_5_REG_RX_TS_NFSEC
+	#define PTP_RX_TS1_5_REG_RX_TS_NFSEC_OFFSET  0
+	#define PTP_RX_TS1_5_REG_RX_TS_NFSEC_LEN     12
+	#define PTP_RX_TS1_5_REG_RX_TS_NFSEC_DEFAULT 0x0
+	/*[field] RX_MSG_TYPE*/
+	#define PTP_RX_TS1_5_REG_RX_MSG_TYPE
+	#define PTP_RX_TS1_5_REG_RX_MSG_TYPE_OFFSET  12
+	#define PTP_RX_TS1_5_REG_RX_MSG_TYPE_LEN     4
+	#define PTP_RX_TS1_5_REG_RX_MSG_TYPE_DEFAULT 0x0
+
+struct ptp_rx_ts1_5_reg {
+	a_uint16_t  rx_ts_nfsec:12;
+	a_uint16_t  rx_msg_type:4;
+};
+
+union ptp_rx_ts1_5_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts1_5_reg bf;
+};
+
+/*[register] PTP_RX_TS1_6_REG*/
+#define PTP_RX_TS1_6_REG
+#define PTP_RX_TS1_6_REG_ADDRESS 0x850c
+#define PTP_RX_TS1_6_REG_NUM     1
+#define PTP_RX_TS1_6_REG_INC     0x1
+#define PTP_RX_TS1_6_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS1_6_REG_DEFAULT 0x0
+	/*[field] RX_TS_NFSEC*/
+	#define PTP_RX_TS1_6_REG_RX_TS_NFSEC
+	#define PTP_RX_TS1_6_REG_RX_TS_NFSEC_OFFSET  0
+	#define PTP_RX_TS1_6_REG_RX_TS_NFSEC_LEN     8
+	#define PTP_RX_TS1_6_REG_RX_TS_NFSEC_DEFAULT 0x0
+
+struct ptp_rx_ts1_6_reg {
+	a_uint16_t  rx_ts_nfsec:8;
+};
+
+union ptp_rx_ts1_6_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts1_6_reg bf;
+};
+
+/*[register] PTP_RX_SEQID2_REG*/
+#define PTP_RX_SEQID2_REG
+#define PTP_RX_SEQID2_REG_ADDRESS 0x851a
+#define PTP_RX_SEQID2_REG_NUM     1
+#define PTP_RX_SEQID2_REG_INC     0x1
+#define PTP_RX_SEQID2_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_SEQID2_REG_DEFAULT 0x0
+	/*[field] RX_SEQID*/
+	#define PTP_RX_SEQID2_REG_RX_SEQID
+	#define PTP_RX_SEQID2_REG_RX_SEQID_OFFSET  0
+	#define PTP_RX_SEQID2_REG_RX_SEQID_LEN     16
+	#define PTP_RX_SEQID2_REG_RX_SEQID_DEFAULT 0x0
+
+struct ptp_rx_seqid2_reg {
+	a_uint16_t  rx_seqid:16;
+};
+
+union ptp_rx_seqid2_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_seqid2_reg bf;
+};
+
+/*[register] PTP_RX_PORTID2_0_REG*/
+#define PTP_RX_PORTID2_0_REG
+#define PTP_RX_PORTID2_0_REG_ADDRESS 0x851b
+#define PTP_RX_PORTID2_0_REG_NUM     1
+#define PTP_RX_PORTID2_0_REG_INC     0x1
+#define PTP_RX_PORTID2_0_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID2_0_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID2_0_REG_RX_PORTID
+	#define PTP_RX_PORTID2_0_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID2_0_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID2_0_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid2_0_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid2_0_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid2_0_reg bf;
+};
+
+/*[register] PTP_RX_PORTID2_1_REG*/
+#define PTP_RX_PORTID2_1_REG
+#define PTP_RX_PORTID2_1_REG_ADDRESS 0x851c
+#define PTP_RX_PORTID2_1_REG_NUM     1
+#define PTP_RX_PORTID2_1_REG_INC     0x1
+#define PTP_RX_PORTID2_1_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID2_1_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID2_1_REG_RX_PORTID
+	#define PTP_RX_PORTID2_1_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID2_1_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID2_1_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid2_1_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid2_1_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid2_1_reg bf;
+};
+
+/*[register] PTP_RX_PORTID2_2_REG*/
+#define PTP_RX_PORTID2_2_REG
+#define PTP_RX_PORTID2_2_REG_ADDRESS 0x851d
+#define PTP_RX_PORTID2_2_REG_NUM     1
+#define PTP_RX_PORTID2_2_REG_INC     0x1
+#define PTP_RX_PORTID2_2_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID2_2_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID2_2_REG_RX_PORTID
+	#define PTP_RX_PORTID2_2_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID2_2_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID2_2_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid2_2_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid2_2_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid2_2_reg bf;
+};
+
+/*[register] PTP_RX_PORTID2_3_REG*/
+#define PTP_RX_PORTID2_3_REG
+#define PTP_RX_PORTID2_3_REG_ADDRESS 0x851e
+#define PTP_RX_PORTID2_3_REG_NUM     1
+#define PTP_RX_PORTID2_3_REG_INC     0x1
+#define PTP_RX_PORTID2_3_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID2_3_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID2_3_REG_RX_PORTID
+	#define PTP_RX_PORTID2_3_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID2_3_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID2_3_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid2_3_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid2_3_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid2_3_reg bf;
+};
+
+/*[register] PTP_RX_PORTID2_4_REG*/
+#define PTP_RX_PORTID2_4_REG
+#define PTP_RX_PORTID2_4_REG_ADDRESS 0x851f
+#define PTP_RX_PORTID2_4_REG_NUM     1
+#define PTP_RX_PORTID2_4_REG_INC     0x1
+#define PTP_RX_PORTID2_4_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID2_4_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID2_4_REG_RX_PORTID
+	#define PTP_RX_PORTID2_4_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID2_4_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID2_4_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid2_4_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid2_4_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid2_4_reg bf;
+};
+
+/*[register] PTP_RX_TS2_0_REG*/
+#define PTP_RX_TS2_0_REG
+#define PTP_RX_TS2_0_REG_ADDRESS 0x8520
+#define PTP_RX_TS2_0_REG_NUM     1
+#define PTP_RX_TS2_0_REG_INC     0x1
+#define PTP_RX_TS2_0_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS2_0_REG_DEFAULT 0x0
+	/*[field] RX_TS_SEC*/
+	#define PTP_RX_TS2_0_REG_RX_TS_SEC
+	#define PTP_RX_TS2_0_REG_RX_TS_SEC_OFFSET  0
+	#define PTP_RX_TS2_0_REG_RX_TS_SEC_LEN     16
+	#define PTP_RX_TS2_0_REG_RX_TS_SEC_DEFAULT 0x0
+
+struct ptp_rx_ts2_0_reg {
+	a_uint16_t  rx_ts_sec:16;
+};
+
+union ptp_rx_ts2_0_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts2_0_reg bf;
+};
+
+/*[register] PTP_RX_TS2_1_REG*/
+#define PTP_RX_TS2_1_REG
+#define PTP_RX_TS2_1_REG_ADDRESS 0x8521
+#define PTP_RX_TS2_1_REG_NUM     1
+#define PTP_RX_TS2_1_REG_INC     0x1
+#define PTP_RX_TS2_1_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS2_1_REG_DEFAULT 0x0
+	/*[field] RX_TS_SEC*/
+	#define PTP_RX_TS2_1_REG_RX_TS_SEC
+	#define PTP_RX_TS2_1_REG_RX_TS_SEC_OFFSET  0
+	#define PTP_RX_TS2_1_REG_RX_TS_SEC_LEN     16
+	#define PTP_RX_TS2_1_REG_RX_TS_SEC_DEFAULT 0x0
+
+struct ptp_rx_ts2_1_reg {
+	a_uint16_t  rx_ts_sec:16;
+};
+
+union ptp_rx_ts2_1_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts2_1_reg bf;
+};
+
+/*[register] PTP_RX_TS2_2_REG*/
+#define PTP_RX_TS2_2_REG
+#define PTP_RX_TS2_2_REG_ADDRESS 0x8522
+#define PTP_RX_TS2_2_REG_NUM     1
+#define PTP_RX_TS2_2_REG_INC     0x1
+#define PTP_RX_TS2_2_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS2_2_REG_DEFAULT 0x0
+	/*[field] RX_TS_SEC*/
+	#define PTP_RX_TS2_2_REG_RX_TS_SEC
+	#define PTP_RX_TS2_2_REG_RX_TS_SEC_OFFSET  0
+	#define PTP_RX_TS2_2_REG_RX_TS_SEC_LEN     16
+	#define PTP_RX_TS2_2_REG_RX_TS_SEC_DEFAULT 0x0
+
+struct ptp_rx_ts2_2_reg {
+	a_uint16_t  rx_ts_sec:16;
+};
+
+union ptp_rx_ts2_2_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts2_2_reg bf;
+};
+
+/*[register] PTP_RX_TS2_3_REG*/
+#define PTP_RX_TS2_3_REG
+#define PTP_RX_TS2_3_REG_ADDRESS 0x8523
+#define PTP_RX_TS2_3_REG_NUM     1
+#define PTP_RX_TS2_3_REG_INC     0x1
+#define PTP_RX_TS2_3_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS2_3_REG_DEFAULT 0x0
+	/*[field] RX_TS_NSEC*/
+	#define PTP_RX_TS2_3_REG_RX_TS_NSEC
+	#define PTP_RX_TS2_3_REG_RX_TS_NSEC_OFFSET  0
+	#define PTP_RX_TS2_3_REG_RX_TS_NSEC_LEN     16
+	#define PTP_RX_TS2_3_REG_RX_TS_NSEC_DEFAULT 0x0
+
+struct ptp_rx_ts2_3_reg {
+	a_uint16_t  rx_ts_nsec:16;
+};
+
+union ptp_rx_ts2_3_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts2_3_reg bf;
+};
+
+/*[register] PTP_RX_TS2_4_REG*/
+#define PTP_RX_TS2_4_REG
+#define PTP_RX_TS2_4_REG_ADDRESS 0x8524
+#define PTP_RX_TS2_4_REG_NUM     1
+#define PTP_RX_TS2_4_REG_INC     0x1
+#define PTP_RX_TS2_4_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS2_4_REG_DEFAULT 0x0
+	/*[field] RX_TS_NSEC*/
+	#define PTP_RX_TS2_4_REG_RX_TS_NSEC
+	#define PTP_RX_TS2_4_REG_RX_TS_NSEC_OFFSET  0
+	#define PTP_RX_TS2_4_REG_RX_TS_NSEC_LEN     16
+	#define PTP_RX_TS2_4_REG_RX_TS_NSEC_DEFAULT 0x0
+
+struct ptp_rx_ts2_4_reg {
+	a_uint16_t  rx_ts_nsec:16;
+};
+
+union ptp_rx_ts2_4_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts2_4_reg bf;
+};
+
+/*[register] PTP_RX_TS2_5_REG*/
+#define PTP_RX_TS2_5_REG
+#define PTP_RX_TS2_5_REG_ADDRESS 0x8525
+#define PTP_RX_TS2_5_REG_NUM     1
+#define PTP_RX_TS2_5_REG_INC     0x1
+#define PTP_RX_TS2_5_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS2_5_REG_DEFAULT 0x0
+	/*[field] RX_TS_NFSEC*/
+	#define PTP_RX_TS2_5_REG_RX_TS_NFSEC
+	#define PTP_RX_TS2_5_REG_RX_TS_NFSEC_OFFSET  0
+	#define PTP_RX_TS2_5_REG_RX_TS_NFSEC_LEN     12
+	#define PTP_RX_TS2_5_REG_RX_TS_NFSEC_DEFAULT 0x0
+	/*[field] RX_MSG_TYPE*/
+	#define PTP_RX_TS2_5_REG_RX_MSG_TYPE
+	#define PTP_RX_TS2_5_REG_RX_MSG_TYPE_OFFSET  12
+	#define PTP_RX_TS2_5_REG_RX_MSG_TYPE_LEN     4
+	#define PTP_RX_TS2_5_REG_RX_MSG_TYPE_DEFAULT 0x0
+
+struct ptp_rx_ts2_5_reg {
+	a_uint16_t  rx_ts_nfsec:12;
+	a_uint16_t  rx_msg_type:4;
+};
+
+union ptp_rx_ts2_5_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts2_5_reg bf;
+};
+
+/*[register] PTP_RX_TS2_6_REG*/
+#define PTP_RX_TS2_6_REG
+#define PTP_RX_TS2_6_REG_ADDRESS 0x8526
+#define PTP_RX_TS2_6_REG_NUM     1
+#define PTP_RX_TS2_6_REG_INC     0x1
+#define PTP_RX_TS2_6_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS2_6_REG_DEFAULT 0x0
+	/*[field] RX_TS_NFSEC*/
+	#define PTP_RX_TS2_6_REG_RX_TS_NFSEC
+	#define PTP_RX_TS2_6_REG_RX_TS_NFSEC_OFFSET  0
+	#define PTP_RX_TS2_6_REG_RX_TS_NFSEC_LEN     8
+	#define PTP_RX_TS2_6_REG_RX_TS_NFSEC_DEFAULT 0x0
+
+struct ptp_rx_ts2_6_reg {
+	a_uint16_t  rx_ts_nfsec:8;
+};
+
+union ptp_rx_ts2_6_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts2_6_reg bf;
+};
+
+/*[register] PTP_RX_SEQID3_REG*/
+#define PTP_RX_SEQID3_REG
+#define PTP_RX_SEQID3_REG_ADDRESS 0x8534
+#define PTP_RX_SEQID3_REG_NUM     1
+#define PTP_RX_SEQID3_REG_INC     0x1
+#define PTP_RX_SEQID3_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_SEQID3_REG_DEFAULT 0x0
+	/*[field] RX_SEQID*/
+	#define PTP_RX_SEQID3_REG_RX_SEQID
+	#define PTP_RX_SEQID3_REG_RX_SEQID_OFFSET  0
+	#define PTP_RX_SEQID3_REG_RX_SEQID_LEN     16
+	#define PTP_RX_SEQID3_REG_RX_SEQID_DEFAULT 0x0
+
+struct ptp_rx_seqid3_reg {
+	a_uint16_t  rx_seqid:16;
+};
+
+union ptp_rx_seqid3_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_seqid3_reg bf;
+};
+
+/*[register] PTP_RX_PORTID3_0_REG*/
+#define PTP_RX_PORTID3_0_REG
+#define PTP_RX_PORTID3_0_REG_ADDRESS 0x8535
+#define PTP_RX_PORTID3_0_REG_NUM     1
+#define PTP_RX_PORTID3_0_REG_INC     0x1
+#define PTP_RX_PORTID3_0_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID3_0_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID3_0_REG_RX_PORTID
+	#define PTP_RX_PORTID3_0_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID3_0_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID3_0_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid3_0_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid3_0_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid3_0_reg bf;
+};
+
+/*[register] PTP_RX_PORTID3_1_REG*/
+#define PTP_RX_PORTID3_1_REG
+#define PTP_RX_PORTID3_1_REG_ADDRESS 0x8536
+#define PTP_RX_PORTID3_1_REG_NUM     1
+#define PTP_RX_PORTID3_1_REG_INC     0x1
+#define PTP_RX_PORTID3_1_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID3_1_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID3_1_REG_RX_PORTID
+	#define PTP_RX_PORTID3_1_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID3_1_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID3_1_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid3_1_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid3_1_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid3_1_reg bf;
+};
+
+/*[register] PTP_RX_PORTID3_2_REG*/
+#define PTP_RX_PORTID3_2_REG
+#define PTP_RX_PORTID3_2_REG_ADDRESS 0x8537
+#define PTP_RX_PORTID3_2_REG_NUM     1
+#define PTP_RX_PORTID3_2_REG_INC     0x1
+#define PTP_RX_PORTID3_2_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID3_2_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID3_2_REG_RX_PORTID
+	#define PTP_RX_PORTID3_2_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID3_2_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID3_2_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid3_2_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid3_2_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid3_2_reg bf;
+};
+
+/*[register] PTP_RX_PORTID3_3_REG*/
+#define PTP_RX_PORTID3_3_REG
+#define PTP_RX_PORTID3_3_REG_ADDRESS 0x8538
+#define PTP_RX_PORTID3_3_REG_NUM     1
+#define PTP_RX_PORTID3_3_REG_INC     0x1
+#define PTP_RX_PORTID3_3_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID3_3_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID3_3_REG_RX_PORTID
+	#define PTP_RX_PORTID3_3_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID3_3_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID3_3_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid3_3_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid3_3_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid3_3_reg bf;
+};
+
+/*[register] PTP_RX_PORTID3_4_REG*/
+#define PTP_RX_PORTID3_4_REG
+#define PTP_RX_PORTID3_4_REG_ADDRESS 0x8539
+#define PTP_RX_PORTID3_4_REG_NUM     1
+#define PTP_RX_PORTID3_4_REG_INC     0x1
+#define PTP_RX_PORTID3_4_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_PORTID3_4_REG_DEFAULT 0x0
+	/*[field] RX_PORTID*/
+	#define PTP_RX_PORTID3_4_REG_RX_PORTID
+	#define PTP_RX_PORTID3_4_REG_RX_PORTID_OFFSET  0
+	#define PTP_RX_PORTID3_4_REG_RX_PORTID_LEN     16
+	#define PTP_RX_PORTID3_4_REG_RX_PORTID_DEFAULT 0x0
+
+struct ptp_rx_portid3_4_reg {
+	a_uint16_t  rx_portid:16;
+};
+
+union ptp_rx_portid3_4_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_portid3_4_reg bf;
+};
+
+/*[register] PTP_RX_TS3_0_REG*/
+#define PTP_RX_TS3_0_REG
+#define PTP_RX_TS3_0_REG_ADDRESS 0x853a
+#define PTP_RX_TS3_0_REG_NUM     1
+#define PTP_RX_TS3_0_REG_INC     0x1
+#define PTP_RX_TS3_0_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS3_0_REG_DEFAULT 0x0
+	/*[field] RX_TS_SEC*/
+	#define PTP_RX_TS3_0_REG_RX_TS_SEC
+	#define PTP_RX_TS3_0_REG_RX_TS_SEC_OFFSET  0
+	#define PTP_RX_TS3_0_REG_RX_TS_SEC_LEN     16
+	#define PTP_RX_TS3_0_REG_RX_TS_SEC_DEFAULT 0x0
+
+struct ptp_rx_ts3_0_reg {
+	a_uint16_t  rx_ts_sec:16;
+};
+
+union ptp_rx_ts3_0_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts3_0_reg bf;
+};
+
+/*[register] PTP_RX_TS3_1_REG*/
+#define PTP_RX_TS3_1_REG
+#define PTP_RX_TS3_1_REG_ADDRESS 0x853b
+#define PTP_RX_TS3_1_REG_NUM     1
+#define PTP_RX_TS3_1_REG_INC     0x1
+#define PTP_RX_TS3_1_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS3_1_REG_DEFAULT 0x0
+	/*[field] RX_TS_SEC*/
+	#define PTP_RX_TS3_1_REG_RX_TS_SEC
+	#define PTP_RX_TS3_1_REG_RX_TS_SEC_OFFSET  0
+	#define PTP_RX_TS3_1_REG_RX_TS_SEC_LEN     16
+	#define PTP_RX_TS3_1_REG_RX_TS_SEC_DEFAULT 0x0
+
+struct ptp_rx_ts3_1_reg {
+	a_uint16_t  rx_ts_sec:16;
+};
+
+union ptp_rx_ts3_1_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts3_1_reg bf;
+};
+
+/*[register] PTP_RX_TS3_2_REG*/
+#define PTP_RX_TS3_2_REG
+#define PTP_RX_TS3_2_REG_ADDRESS 0x853c
+#define PTP_RX_TS3_2_REG_NUM     1
+#define PTP_RX_TS3_2_REG_INC     0x1
+#define PTP_RX_TS3_2_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS3_2_REG_DEFAULT 0x0
+	/*[field] RX_TS_SEC*/
+	#define PTP_RX_TS3_2_REG_RX_TS_SEC
+	#define PTP_RX_TS3_2_REG_RX_TS_SEC_OFFSET  0
+	#define PTP_RX_TS3_2_REG_RX_TS_SEC_LEN     16
+	#define PTP_RX_TS3_2_REG_RX_TS_SEC_DEFAULT 0x0
+
+struct ptp_rx_ts3_2_reg {
+	a_uint16_t  rx_ts_sec:16;
+};
+
+union ptp_rx_ts3_2_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts3_2_reg bf;
+};
+
+/*[register] PTP_RX_TS3_3_REG*/
+#define PTP_RX_TS3_3_REG
+#define PTP_RX_TS3_3_REG_ADDRESS 0x853d
+#define PTP_RX_TS3_3_REG_NUM     1
+#define PTP_RX_TS3_3_REG_INC     0x1
+#define PTP_RX_TS3_3_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS3_3_REG_DEFAULT 0x0
+	/*[field] RX_TS_NSEC*/
+	#define PTP_RX_TS3_3_REG_RX_TS_NSEC
+	#define PTP_RX_TS3_3_REG_RX_TS_NSEC_OFFSET  0
+	#define PTP_RX_TS3_3_REG_RX_TS_NSEC_LEN     16
+	#define PTP_RX_TS3_3_REG_RX_TS_NSEC_DEFAULT 0x0
+
+struct ptp_rx_ts3_3_reg {
+	a_uint16_t  rx_ts_nsec:16;
+};
+
+union ptp_rx_ts3_3_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts3_3_reg bf;
+};
+
+/*[register] PTP_RX_TS3_4_REG*/
+#define PTP_RX_TS3_4_REG
+#define PTP_RX_TS3_4_REG_ADDRESS 0x853e
+#define PTP_RX_TS3_4_REG_NUM     1
+#define PTP_RX_TS3_4_REG_INC     0x1
+#define PTP_RX_TS3_4_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS3_4_REG_DEFAULT 0x0
+	/*[field] RX_TS_NSEC*/
+	#define PTP_RX_TS3_4_REG_RX_TS_NSEC
+	#define PTP_RX_TS3_4_REG_RX_TS_NSEC_OFFSET  0
+	#define PTP_RX_TS3_4_REG_RX_TS_NSEC_LEN     16
+	#define PTP_RX_TS3_4_REG_RX_TS_NSEC_DEFAULT 0x0
+
+struct ptp_rx_ts3_4_reg {
+	a_uint16_t  rx_ts_nsec:16;
+};
+
+union ptp_rx_ts3_4_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts3_4_reg bf;
+};
+
+/*[register] PTP_RX_TS3_5_REG*/
+#define PTP_RX_TS3_5_REG
+#define PTP_RX_TS3_5_REG_ADDRESS 0x853f
+#define PTP_RX_TS3_5_REG_NUM     1
+#define PTP_RX_TS3_5_REG_INC     0x1
+#define PTP_RX_TS3_5_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS3_5_REG_DEFAULT 0x0
+	/*[field] RX_TS_NFSEC*/
+	#define PTP_RX_TS3_5_REG_RX_TS_NFSEC
+	#define PTP_RX_TS3_5_REG_RX_TS_NFSEC_OFFSET  0
+	#define PTP_RX_TS3_5_REG_RX_TS_NFSEC_LEN     12
+	#define PTP_RX_TS3_5_REG_RX_TS_NFSEC_DEFAULT 0x0
+	/*[field] RX_MSG_TYPE*/
+	#define PTP_RX_TS3_5_REG_RX_MSG_TYPE
+	#define PTP_RX_TS3_5_REG_RX_MSG_TYPE_OFFSET  12
+	#define PTP_RX_TS3_5_REG_RX_MSG_TYPE_LEN     4
+	#define PTP_RX_TS3_5_REG_RX_MSG_TYPE_DEFAULT 0x0
+
+struct ptp_rx_ts3_5_reg {
+	a_uint16_t  rx_ts_nfsec:12;
+	a_uint16_t  rx_msg_type:4;
+};
+
+union ptp_rx_ts3_5_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts3_5_reg bf;
+};
+
+/*[register] PTP_RX_TS3_6_REG*/
+#define PTP_RX_TS3_6_REG
+#define PTP_RX_TS3_6_REG_ADDRESS 0x8540
+#define PTP_RX_TS3_6_REG_NUM     1
+#define PTP_RX_TS3_6_REG_INC     0x1
+#define PTP_RX_TS3_6_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_TS3_6_REG_DEFAULT 0x0
+	/*[field] RX_TS_NFSEC*/
+	#define PTP_RX_TS3_6_REG_RX_TS_NFSEC
+	#define PTP_RX_TS3_6_REG_RX_TS_NFSEC_OFFSET  0
+	#define PTP_RX_TS3_6_REG_RX_TS_NFSEC_LEN     8
+	#define PTP_RX_TS3_6_REG_RX_TS_NFSEC_DEFAULT 0x0
+
+struct ptp_rx_ts3_6_reg {
+	a_uint16_t  rx_ts_nfsec:8;
+};
+
+union ptp_rx_ts3_6_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_ts3_6_reg bf;
+};
+
+/*[register] PTP_PHASE_ADJUST_0*/
+#define PTP_PHASE_ADJUST_0_REG
+#define PTP_PHASE_ADJUST_0_REG_ADDRESS 0x8300
+#define PTP_PHASE_ADJUST_0_REG_NUM     1
+#define PTP_PHASE_ADJUST_0_REG_INC     0x1
+#define PTP_PHASE_ADJUST_0_REG_TYPE    REG_TYPE_RW
+#define PTP_PHASE_ADJUST_0_REG_DEFAULT 0x0
+	/*[field] PTP_PHASE_ADJUST_0*/
+	#define PTP_PHASE_ADJUST_0_REG_PHASE_VALUE
+	#define PTP_PHASE_ADJUST_0_REG_PHASE_VALUE_OFFSET  0
+	#define PTP_PHASE_ADJUST_0_REG_PHASE_VALUE_LEN     16
+	#define PTP_PHASE_ADJUST_0_REG_PHASE_VALUE_DEFAULT 0x0
+
+struct ptp_phase_adjust_0_reg {
+	a_uint16_t  phase_value:16;
+};
+
+union ptp_phase_adjust_0_reg_u {
+	a_uint32_t val;
+	struct ptp_phase_adjust_0_reg bf;
+};
+
+/*[register] PTP_PHASE_ADJUST_1*/
+#define PTP_PHASE_ADJUST_1_REG
+#define PTP_PHASE_ADJUST_1_REG_ADDRESS 0x8301
+#define PTP_PHASE_ADJUST_1_REG_NUM     1
+#define PTP_PHASE_ADJUST_1_REG_INC     0x1
+#define PTP_PHASE_ADJUST_1_REG_TYPE    REG_TYPE_RW
+#define PTP_PHASE_ADJUST_1_REG_DEFAULT 0x0
+	/*[field] PTP_PHASE_ADJUST_1*/
+	#define PTP_PHASE_ADJUST_1_REG_PHASE_VALUE
+	#define PTP_PHASE_ADJUST_1_REG_PHASE_VALUE_OFFSET  0
+	#define PTP_PHASE_ADJUST_1_REG_PHASE_VALUE_LEN     16
+	#define PTP_PHASE_ADJUST_1_REG_PHASE_VALUE_DEFAULT 0x0
+
+struct ptp_phase_adjust_1_reg {
+	a_uint16_t  phase_value:16;
+};
+
+union ptp_phase_adjust_1_reg_u {
+	a_uint32_t val;
+	struct ptp_phase_adjust_1_reg bf;
+};
+
+/*[register] PTP_PPS_PUL_WIDTH_0*/
+#define PTP_PPS_PUL_WIDTH_0_REG
+#define PTP_PPS_PUL_WIDTH_0_REG_ADDRESS 0x8303
+#define PTP_PPS_PUL_WIDTH_0_REG_NUM     1
+#define PTP_PPS_PUL_WIDTH_0_REG_INC     0x1
+#define PTP_PPS_PUL_WIDTH_0_REG_TYPE    REG_TYPE_RW
+#define PTP_PPS_PUL_WIDTH_0_REG_DEFAULT 0x0
+	/*[field] PTP_PPS_PUL_WIDTH_0*/
+	#define PTP_PPS_PUL_WIDTH_0_REG_PUL_VALUE
+	#define PTP_PPS_PUL_WIDTH_0_REG_PUL_VALUE_OFFSET  0
+	#define PTP_PPS_PUL_WIDTH_0_REG_PUL_VALUE_LEN     16
+	#define PTP_PPS_PUL_WIDTH_0_REG_PUL_VALUE_DEFAULT 0x0
+
+struct ptp_pps_pul_width_0_reg {
+	a_uint16_t  pul_value:16;
+};
+
+union ptp_pps_pul_width_0_reg_u {
+	a_uint32_t val;
+	struct ptp_pps_pul_width_0_reg bf;
+};
+
+/*[register] PTP_PPS_PUL_WIDTH_1*/
+#define PTP_PPS_PUL_WIDTH_1_REG
+#define PTP_PPS_PUL_WIDTH_1_REG_ADDRESS 0x8304
+#define PTP_PPS_PUL_WIDTH_1_REG_NUM     1
+#define PTP_PPS_PUL_WIDTH_1_REG_INC     0x1
+#define PTP_PPS_PUL_WIDTH_1_REG_TYPE    REG_TYPE_RW
+#define PTP_PPS_PUL_WIDTH_1_REG_DEFAULT 0x0
+	/*[field] PTP_PPS_PUL_WIDTH_1*/
+	#define PTP_PPS_PUL_WIDTH_1_REG_PUL_VALUE
+	#define PTP_PPS_PUL_WIDTH_1_REG_PUL_VALUE_OFFSET  0
+	#define PTP_PPS_PUL_WIDTH_1_REG_PUL_VALUE_LEN     16
+	#define PTP_PPS_PUL_WIDTH_1_REG_PUL_VALUE_DEFAULT 0x0
+
+struct ptp_pps_pul_width_1_reg {
+	a_uint16_t  pul_value:16;
+};
+
+union ptp_pps_pul_width_1_reg_u {
+	a_uint32_t val;
+	struct ptp_pps_pul_width_1_reg bf;
+};
+
+/*[register] PTP_FREQ_WAVEFORM_PERIOD_0_REG*/
+#define PTP_FREQ_WAVEFORM_PERIOD_0_REG
+#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_ADDRESS 0x8305
+#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_NUM     1
+#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_INC     0x1
+#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_TYPE    REG_TYPE_RW
+#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_DEFAULT 0x0
+	/*[field] WAVE_PERIOD*/
+	#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_WAVE_PERIOD
+	#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_WAVE_PERIOD_OFFSET  0
+	#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_WAVE_PERIOD_LEN     15
+	#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_WAVE_PERIOD_DEFAULT 0x0
+	/*[field] PHASE_ALI*/
+	#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_PHASE_ALI
+	#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_PHASE_ALI_OFFSET  15
+	#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_PHASE_ALI_LEN     1
+	#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_PHASE_ALI_DEFAULT 0x0
+
+struct ptp_freq_waveform_period_0_reg {
+	a_uint16_t  wave_period:15;
+	a_uint16_t  phase_ali:1;
+};
+
+union ptp_freq_waveform_period_0_reg_u {
+	a_uint32_t val;
+	struct ptp_freq_waveform_period_0_reg bf;
+};
+
+/*[register] PTP_FREQ_WAVEFORM_PERIOD_1_REG*/
+#define PTP_FREQ_WAVEFORM_PERIOD_1_REG
+#define PTP_FREQ_WAVEFORM_PERIOD_1_REG_ADDRESS 0x8306
+#define PTP_FREQ_WAVEFORM_PERIOD_1_REG_NUM     1
+#define PTP_FREQ_WAVEFORM_PERIOD_1_REG_INC     0x1
+#define PTP_FREQ_WAVEFORM_PERIOD_1_REG_TYPE    REG_TYPE_RW
+#define PTP_FREQ_WAVEFORM_PERIOD_1_REG_DEFAULT 0x0
+	/*[field] WAVE_PERIOD*/
+	#define PTP_FREQ_WAVEFORM_PERIOD_1_REG_WAVE_PERIOD
+	#define PTP_FREQ_WAVEFORM_PERIOD_1_REG_WAVE_PERIOD_OFFSET  0
+	#define PTP_FREQ_WAVEFORM_PERIOD_1_REG_WAVE_PERIOD_LEN     16
+	#define PTP_FREQ_WAVEFORM_PERIOD_1_REG_WAVE_PERIOD_DEFAULT 0x0
+
+struct ptp_freq_waveform_period_1_reg {
+	a_uint16_t  wave_period:16;
+};
+
+union ptp_freq_waveform_period_1_reg_u {
+	a_uint32_t val;
+	struct ptp_freq_waveform_period_1_reg bf;
+};
+
+/*[register] PTP_FREQ_WAVEFORM_PERIOD_2_REG*/
+#define PTP_FREQ_WAVEFORM_PERIOD_2_REG
+#define PTP_FREQ_WAVEFORM_PERIOD_2_REG_ADDRESS 0x8307
+#define PTP_FREQ_WAVEFORM_PERIOD_2_REG_NUM     1
+#define PTP_FREQ_WAVEFORM_PERIOD_2_REG_INC     0x1
+#define PTP_FREQ_WAVEFORM_PERIOD_2_REG_TYPE    REG_TYPE_RW
+#define PTP_FREQ_WAVEFORM_PERIOD_2_REG_DEFAULT 0x0
+	/*[field] WAVE_PERIOD*/
+	#define PTP_FREQ_WAVEFORM_PERIOD_2_REG_WAVE_PERIOD
+	#define PTP_FREQ_WAVEFORM_PERIOD_2_REG_WAVE_PERIOD_OFFSET  0
+	#define PTP_FREQ_WAVEFORM_PERIOD_2_REG_WAVE_PERIOD_LEN     16
+	#define PTP_FREQ_WAVEFORM_PERIOD_2_REG_WAVE_PERIOD_DEFAULT 0x0
+
+struct ptp_freq_waveform_period_2_reg {
+	a_uint16_t  wave_period:16;
+};
+
+union ptp_freq_waveform_period_2_reg_u {
+	a_uint32_t val;
+	struct ptp_freq_waveform_period_2_reg bf;
+};
+
+/*[register] PTP_RX_COM_TS_CTRL_REG*/
+#define PTP_RX_COM_TS_CTRL_REG
+#define PTP_RX_COM_TS_CTRL_REG_ADDRESS 0x8600
+#define PTP_RX_COM_TS_CTRL_REG_NUM     1
+#define PTP_RX_COM_TS_CTRL_REG_INC     0x1
+#define PTP_RX_COM_TS_CTRL_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_COM_TS_CTRL_REG_DEFAULT 0x0
+	/*[field] FILT_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_FILT_EN
+	#define PTP_RX_COM_TS_CTRL_REG_FILT_EN_OFFSET  0
+	#define PTP_RX_COM_TS_CTRL_REG_FILT_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_FILT_EN_DEFAULT 0x0
+	/*[field] MAC_LENGTHTYPE_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN
+	#define PTP_RX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN_OFFSET  1
+	#define PTP_RX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN_DEFAULT 0x0
+	/*[field] MAC_DA_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_MAC_DA_EN
+	#define PTP_RX_COM_TS_CTRL_REG_MAC_DA_EN_OFFSET  2
+	#define PTP_RX_COM_TS_CTRL_REG_MAC_DA_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_MAC_DA_EN_DEFAULT 0x0
+	/*[field] MAC_PTP_FILT_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN
+	#define PTP_RX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_OFFSET  3
+	#define PTP_RX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_DEFAULT 0x0
+	/*[field] IPV4_LAYER4_PROTOCOL_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN
+	#define PTP_RX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_OFFSET  4
+	#define PTP_RX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_DEFAULT 0x0
+	/*[field] IPV4_DA_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_IPV4_DA_EN
+	#define PTP_RX_COM_TS_CTRL_REG_IPV4_DA_EN_OFFSET  5
+	#define PTP_RX_COM_TS_CTRL_REG_IPV4_DA_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_IPV4_DA_EN_DEFAULT 0x0
+	/*[field] IPV4_PTP_FILT_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN
+	#define PTP_RX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_OFFSET  6
+	#define PTP_RX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_DEFAULT 0x0
+	/*[field] IPV6_NEXT_HEADER_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN
+	#define PTP_RX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_OFFSET  7
+	#define PTP_RX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_DEFAULT 0x0
+	/*[field] IPV6_DA_FILT_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_IPV6_DA_FILT_EN
+	#define PTP_RX_COM_TS_CTRL_REG_IPV6_DA_FILT_EN_OFFSET  8
+	#define PTP_RX_COM_TS_CTRL_REG_IPV6_DA_FILT_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_IPV6_DA_FILT_EN_DEFAULT 0x0
+	/*[field] IPV6_PTP_FILT_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN
+	#define PTP_RX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_OFFSET  9
+	#define PTP_RX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_DEFAULT 0x0
+	/*[field] UDP_DPORT_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_UDP_DPORT_EN
+	#define PTP_RX_COM_TS_CTRL_REG_UDP_DPORT_EN_OFFSET  10
+	#define PTP_RX_COM_TS_CTRL_REG_UDP_DPORT_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_UDP_DPORT_EN_DEFAULT 0x0
+	/*[field] UDP_PTP_EVENT_FILT_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN
+	#define PTP_RX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_OFFSET  11
+	#define PTP_RX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_DEFAULT 0x0
+	/*[field] Y1731_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_Y1731_EN
+	#define PTP_RX_COM_TS_CTRL_REG_Y1731_EN_OFFSET  12
+	#define PTP_RX_COM_TS_CTRL_REG_Y1731_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_Y1731_EN_DEFAULT 0x0
+	/*[field] Y1731_INSERT_TS_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN
+	#define PTP_RX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_OFFSET  13
+	#define PTP_RX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_DEFAULT 0x0
+	/*[field] Y1731_DA_CHK_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_Y1731_DA_CHK_EN
+	#define PTP_RX_COM_TS_CTRL_REG_Y1731_DA_CHK_EN_OFFSET  14
+	#define PTP_RX_COM_TS_CTRL_REG_Y1731_DA_CHK_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_Y1731_DA_CHK_EN_DEFAULT 0x0
+	/*[field] PW_MAC_EN*/
+	#define PTP_RX_COM_TS_CTRL_REG_PW_MAC_EN
+	#define PTP_RX_COM_TS_CTRL_REG_PW_MAC_EN_OFFSET  15
+	#define PTP_RX_COM_TS_CTRL_REG_PW_MAC_EN_LEN     1
+	#define PTP_RX_COM_TS_CTRL_REG_PW_MAC_EN_DEFAULT 0x0
+
+struct ptp_rx_com_ts_ctrl_reg {
+	a_uint32_t  filt_en:1;
+	a_uint32_t  mac_lengthtype_en:1;
+	a_uint32_t  mac_da_en:1;
+	a_uint32_t  mac_ptp_filt_en:1;
+	a_uint32_t  ipv4_layer4_protocol_en:1;
+	a_uint32_t  ipv4_da_en:1;
+	a_uint32_t  ipv4_ptp_filt_en:1;
+	a_uint32_t  ipv6_next_header_en:1;
+	a_uint32_t  ipv6_da_filt_en:1;
+	a_uint32_t  ipv6_ptp_filt_en:1;
+	a_uint32_t  udp_dport_en:1;
+	a_uint32_t  udp_ptp_event_filt_en:1;
+	a_uint32_t  y1731_en:1;
+	a_uint32_t  y1731_insert_ts_en:1;
+	a_uint32_t  y1731_da_chk_en:1;
+	a_uint32_t  pw_mac_en:1;
+};
+
+union ptp_rx_com_ts_ctrl_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_com_ts_ctrl_reg bf;
+};
+
+/*[register] PTP_RX_FILT_MAC_DA0_REG*/
+#define PTP_RX_FILT_MAC_DA0_REG
+#define PTP_RX_FILT_MAC_DA0_REG_ADDRESS 0x8601
+#define PTP_RX_FILT_MAC_DA0_REG_NUM     1
+#define PTP_RX_FILT_MAC_DA0_REG_INC     0x1
+#define PTP_RX_FILT_MAC_DA0_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_MAC_DA0_REG_DEFAULT 0x0
+	/*[field] MAC_ADDR*/
+	#define PTP_RX_FILT_MAC_DA0_REG_MAC_ADDR
+	#define PTP_RX_FILT_MAC_DA0_REG_MAC_ADDR_OFFSET  0
+	#define PTP_RX_FILT_MAC_DA0_REG_MAC_ADDR_LEN     16
+	#define PTP_RX_FILT_MAC_DA0_REG_MAC_ADDR_DEFAULT 0x0
+
+struct ptp_rx_filt_mac_da0_reg {
+	a_uint32_t  mac_addr:16;
+};
+
+union ptp_rx_filt_mac_da0_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_mac_da0_reg bf;
+};
+
+/*[register] PTP_RX_FILT_MAC_DA1_REG*/
+#define PTP_RX_FILT_MAC_DA1_REG
+#define PTP_RX_FILT_MAC_DA1_REG_ADDRESS 0x8602
+#define PTP_RX_FILT_MAC_DA1_REG_NUM     1
+#define PTP_RX_FILT_MAC_DA1_REG_INC     0x1
+#define PTP_RX_FILT_MAC_DA1_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_MAC_DA1_REG_DEFAULT 0x0
+	/*[field] MAC_ADDR*/
+	#define PTP_RX_FILT_MAC_DA1_REG_MAC_ADDR
+	#define PTP_RX_FILT_MAC_DA1_REG_MAC_ADDR_OFFSET  0
+	#define PTP_RX_FILT_MAC_DA1_REG_MAC_ADDR_LEN     16
+	#define PTP_RX_FILT_MAC_DA1_REG_MAC_ADDR_DEFAULT 0x0
+
+struct ptp_rx_filt_mac_da1_reg {
+	a_uint32_t  mac_addr:16;
+};
+
+union ptp_rx_filt_mac_da1_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_mac_da1_reg bf;
+};
+
+/*[register] PTP_RX_FILT_MAC_DA2_REG*/
+#define PTP_RX_FILT_MAC_DA2_REG
+#define PTP_RX_FILT_MAC_DA2_REG_ADDRESS 0x8603
+#define PTP_RX_FILT_MAC_DA2_REG_NUM     1
+#define PTP_RX_FILT_MAC_DA2_REG_INC     0x1
+#define PTP_RX_FILT_MAC_DA2_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_MAC_DA2_REG_DEFAULT 0x0
+	/*[field] MAC_ADDR*/
+	#define PTP_RX_FILT_MAC_DA2_REG_MAC_ADDR
+	#define PTP_RX_FILT_MAC_DA2_REG_MAC_ADDR_OFFSET  0
+	#define PTP_RX_FILT_MAC_DA2_REG_MAC_ADDR_LEN     16
+	#define PTP_RX_FILT_MAC_DA2_REG_MAC_ADDR_DEFAULT 0x0
+
+struct ptp_rx_filt_mac_da2_reg {
+	a_uint32_t  mac_addr:16;
+};
+
+union ptp_rx_filt_mac_da2_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_mac_da2_reg bf;
+};
+
+/*[register] PTP_RX_FILT_IPV4_DA0_REG*/
+#define PTP_RX_FILT_IPV4_DA0_REG
+#define PTP_RX_FILT_IPV4_DA0_REG_ADDRESS 0x8604
+#define PTP_RX_FILT_IPV4_DA0_REG_NUM     1
+#define PTP_RX_FILT_IPV4_DA0_REG_INC     0x1
+#define PTP_RX_FILT_IPV4_DA0_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_IPV4_DA0_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_RX_FILT_IPV4_DA0_REG_IP_ADDR
+	#define PTP_RX_FILT_IPV4_DA0_REG_IP_ADDR_OFFSET  0
+	#define PTP_RX_FILT_IPV4_DA0_REG_IP_ADDR_LEN     16
+	#define PTP_RX_FILT_IPV4_DA0_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_rx_filt_ipv4_da0_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_rx_filt_ipv4_da0_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_ipv4_da0_reg bf;
+};
+
+/*[register] PTP_RX_FILT_IPV4_DA1_REG*/
+#define PTP_RX_FILT_IPV4_DA1_REG
+#define PTP_RX_FILT_IPV4_DA1_REG_ADDRESS 0x8605
+#define PTP_RX_FILT_IPV4_DA1_REG_NUM     1
+#define PTP_RX_FILT_IPV4_DA1_REG_INC     0x1
+#define PTP_RX_FILT_IPV4_DA1_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_IPV4_DA1_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_RX_FILT_IPV4_DA1_REG_IP_ADDR
+	#define PTP_RX_FILT_IPV4_DA1_REG_IP_ADDR_OFFSET  0
+	#define PTP_RX_FILT_IPV4_DA1_REG_IP_ADDR_LEN     16
+	#define PTP_RX_FILT_IPV4_DA1_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_rx_filt_ipv4_da1_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_rx_filt_ipv4_da1_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_ipv4_da1_reg bf;
+};
+
+/*[register] PTP_RX_FILT_IPV6_DA0_REG*/
+#define PTP_RX_FILT_IPV6_DA0_REG
+#define PTP_RX_FILT_IPV6_DA0_REG_ADDRESS 0x8606
+#define PTP_RX_FILT_IPV6_DA0_REG_NUM     1
+#define PTP_RX_FILT_IPV6_DA0_REG_INC     0x1
+#define PTP_RX_FILT_IPV6_DA0_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_IPV6_DA0_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_RX_FILT_IPV6_DA0_REG_IP_ADDR
+	#define PTP_RX_FILT_IPV6_DA0_REG_IP_ADDR_OFFSET  0
+	#define PTP_RX_FILT_IPV6_DA0_REG_IP_ADDR_LEN     16
+	#define PTP_RX_FILT_IPV6_DA0_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_rx_filt_ipv6_da0_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_rx_filt_ipv6_da0_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_ipv6_da0_reg bf;
+};
+
+/*[register] PTP_RX_FILT_IPV6_DA1_REG*/
+#define PTP_RX_FILT_IPV6_DA1_REG
+#define PTP_RX_FILT_IPV6_DA1_REG_ADDRESS 0x8607
+#define PTP_RX_FILT_IPV6_DA1_REG_NUM     1
+#define PTP_RX_FILT_IPV6_DA1_REG_INC     0x1
+#define PTP_RX_FILT_IPV6_DA1_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_IPV6_DA1_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_RX_FILT_IPV6_DA1_REG_IP_ADDR
+	#define PTP_RX_FILT_IPV6_DA1_REG_IP_ADDR_OFFSET  0
+	#define PTP_RX_FILT_IPV6_DA1_REG_IP_ADDR_LEN     16
+	#define PTP_RX_FILT_IPV6_DA1_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_rx_filt_ipv6_da1_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_rx_filt_ipv6_da1_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_ipv6_da1_reg bf;
+};
+
+/*[register] PTP_RX_FILT_IPV6_DA2_REG*/
+#define PTP_RX_FILT_IPV6_DA2_REG
+#define PTP_RX_FILT_IPV6_DA2_REG_ADDRESS 0x8608
+#define PTP_RX_FILT_IPV6_DA2_REG_NUM     1
+#define PTP_RX_FILT_IPV6_DA2_REG_INC     0x1
+#define PTP_RX_FILT_IPV6_DA2_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_IPV6_DA2_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_RX_FILT_IPV6_DA2_REG_IP_ADDR
+	#define PTP_RX_FILT_IPV6_DA2_REG_IP_ADDR_OFFSET  0
+	#define PTP_RX_FILT_IPV6_DA2_REG_IP_ADDR_LEN     16
+	#define PTP_RX_FILT_IPV6_DA2_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_rx_filt_ipv6_da2_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_rx_filt_ipv6_da2_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_ipv6_da2_reg bf;
+};
+
+/*[register] PTP_RX_FILT_IPV6_DA3_REG*/
+#define PTP_RX_FILT_IPV6_DA3_REG
+#define PTP_RX_FILT_IPV6_DA3_REG_ADDRESS 0x8609
+#define PTP_RX_FILT_IPV6_DA3_REG_NUM     1
+#define PTP_RX_FILT_IPV6_DA3_REG_INC     0x1
+#define PTP_RX_FILT_IPV6_DA3_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_IPV6_DA3_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_RX_FILT_IPV6_DA3_REG_IP_ADDR
+	#define PTP_RX_FILT_IPV6_DA3_REG_IP_ADDR_OFFSET  0
+	#define PTP_RX_FILT_IPV6_DA3_REG_IP_ADDR_LEN     16
+	#define PTP_RX_FILT_IPV6_DA3_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_rx_filt_ipv6_da3_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_rx_filt_ipv6_da3_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_ipv6_da3_reg bf;
+};
+
+/*[register] PTP_RX_FILT_IPV6_DA4_REG*/
+#define PTP_RX_FILT_IPV6_DA4_REG
+#define PTP_RX_FILT_IPV6_DA4_REG_ADDRESS 0x860a
+#define PTP_RX_FILT_IPV6_DA4_REG_NUM     1
+#define PTP_RX_FILT_IPV6_DA4_REG_INC     0x1
+#define PTP_RX_FILT_IPV6_DA4_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_IPV6_DA4_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_RX_FILT_IPV6_DA4_REG_IP_ADDR
+	#define PTP_RX_FILT_IPV6_DA4_REG_IP_ADDR_OFFSET  0
+	#define PTP_RX_FILT_IPV6_DA4_REG_IP_ADDR_LEN     16
+	#define PTP_RX_FILT_IPV6_DA4_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_rx_filt_ipv6_da4_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_rx_filt_ipv6_da4_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_ipv6_da4_reg bf;
+};
+
+/*[register] PTP_RX_FILT_IPV6_DA5_REG*/
+#define PTP_RX_FILT_IPV6_DA5_REG
+#define PTP_RX_FILT_IPV6_DA5_REG_ADDRESS 0x860b
+#define PTP_RX_FILT_IPV6_DA5_REG_NUM     1
+#define PTP_RX_FILT_IPV6_DA5_REG_INC     0x1
+#define PTP_RX_FILT_IPV6_DA5_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_IPV6_DA5_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_RX_FILT_IPV6_DA5_REG_IP_ADDR
+	#define PTP_RX_FILT_IPV6_DA5_REG_IP_ADDR_OFFSET  0
+	#define PTP_RX_FILT_IPV6_DA5_REG_IP_ADDR_LEN     16
+	#define PTP_RX_FILT_IPV6_DA5_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_rx_filt_ipv6_da5_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_rx_filt_ipv6_da5_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_ipv6_da5_reg bf;
+};
+
+/*[register] PTP_RX_FILT_IPV6_DA6_REG*/
+#define PTP_RX_FILT_IPV6_DA6_REG
+#define PTP_RX_FILT_IPV6_DA6_REG_ADDRESS 0x860c
+#define PTP_RX_FILT_IPV6_DA6_REG_NUM     1
+#define PTP_RX_FILT_IPV6_DA6_REG_INC     0x1
+#define PTP_RX_FILT_IPV6_DA6_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_IPV6_DA6_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_RX_FILT_IPV6_DA6_REG_IP_ADDR
+	#define PTP_RX_FILT_IPV6_DA6_REG_IP_ADDR_OFFSET  0
+	#define PTP_RX_FILT_IPV6_DA6_REG_IP_ADDR_LEN     16
+	#define PTP_RX_FILT_IPV6_DA6_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_rx_filt_ipv6_da6_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_rx_filt_ipv6_da6_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_ipv6_da6_reg bf;
+};
+
+/*[register] PTP_RX_FILT_IPV6_DA7_REG*/
+#define PTP_RX_FILT_IPV6_DA7_REG
+#define PTP_RX_FILT_IPV6_DA7_REG_ADDRESS 0x860d
+#define PTP_RX_FILT_IPV6_DA7_REG_NUM     1
+#define PTP_RX_FILT_IPV6_DA7_REG_INC     0x1
+#define PTP_RX_FILT_IPV6_DA7_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_IPV6_DA7_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_RX_FILT_IPV6_DA7_REG_IP_ADDR
+	#define PTP_RX_FILT_IPV6_DA7_REG_IP_ADDR_OFFSET  0
+	#define PTP_RX_FILT_IPV6_DA7_REG_IP_ADDR_LEN     16
+	#define PTP_RX_FILT_IPV6_DA7_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_rx_filt_ipv6_da7_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_rx_filt_ipv6_da7_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_ipv6_da7_reg bf;
+};
+
+/*[register] PTP_RX_FILT_MAC_LENGTHTYPE_REG*/
+#define PTP_RX_FILT_MAC_LENGTHTYPE_REG
+#define PTP_RX_FILT_MAC_LENGTHTYPE_REG_ADDRESS 0x860e
+#define PTP_RX_FILT_MAC_LENGTHTYPE_REG_NUM     1
+#define PTP_RX_FILT_MAC_LENGTHTYPE_REG_INC     0x1
+#define PTP_RX_FILT_MAC_LENGTHTYPE_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_MAC_LENGTHTYPE_REG_DEFAULT 0x0
+	/*[field] LENGTH_TYPE*/
+	#define PTP_RX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE
+	#define PTP_RX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE_OFFSET  0
+	#define PTP_RX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE_LEN     16
+	#define PTP_RX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE_DEFAULT 0x0
+
+struct ptp_rx_filt_mac_lengthtype_reg {
+	a_uint32_t  length_type:16;
+};
+
+union ptp_rx_filt_mac_lengthtype_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_mac_lengthtype_reg bf;
+};
+
+/*[register] PTP_RX_FILT_LAYER4_PROTOCOL_REG*/
+#define PTP_RX_FILT_LAYER4_PROTOCOL_REG
+#define PTP_RX_FILT_LAYER4_PROTOCOL_REG_ADDRESS 0x860f
+#define PTP_RX_FILT_LAYER4_PROTOCOL_REG_NUM     1
+#define PTP_RX_FILT_LAYER4_PROTOCOL_REG_INC     0x1
+#define PTP_RX_FILT_LAYER4_PROTOCOL_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_LAYER4_PROTOCOL_REG_DEFAULT 0x0
+	/*[field] L4_PROTOCOL*/
+	#define PTP_RX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL
+	#define PTP_RX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL_OFFSET  0
+	#define PTP_RX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL_LEN     16
+	#define PTP_RX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL_DEFAULT 0x0
+
+struct ptp_rx_filt_layer4_protocol_reg {
+	a_uint32_t  l4_protocol:16;
+};
+
+union ptp_rx_filt_layer4_protocol_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_layer4_protocol_reg bf;
+};
+
+/*[register] PTP_RX_FILT_UDP_PORT_REG*/
+#define PTP_RX_FILT_UDP_PORT_REG
+#define PTP_RX_FILT_UDP_PORT_REG_ADDRESS 0x8610
+#define PTP_RX_FILT_UDP_PORT_REG_NUM     1
+#define PTP_RX_FILT_UDP_PORT_REG_INC     0x1
+#define PTP_RX_FILT_UDP_PORT_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_FILT_UDP_PORT_REG_DEFAULT 0x0
+	/*[field] UDP_PORT*/
+	#define PTP_RX_FILT_UDP_PORT_REG_UDP_PORT
+	#define PTP_RX_FILT_UDP_PORT_REG_UDP_PORT_OFFSET  0
+	#define PTP_RX_FILT_UDP_PORT_REG_UDP_PORT_LEN     16
+	#define PTP_RX_FILT_UDP_PORT_REG_UDP_PORT_DEFAULT 0x0
+
+struct ptp_rx_filt_udp_port_reg {
+	a_uint32_t  udp_port:16;
+};
+
+union ptp_rx_filt_udp_port_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_filt_udp_port_reg bf;
+};
+
+/*[register] PTP_RX_COM_TS_STATUS_REG*/
+#define PTP_RX_COM_TS_STATUS_REG
+#define PTP_RX_COM_TS_STATUS_REG_ADDRESS 0x8611
+#define PTP_RX_COM_TS_STATUS_REG_NUM     1
+#define PTP_RX_COM_TS_STATUS_REG_INC     0x1
+#define PTP_RX_COM_TS_STATUS_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_COM_TS_STATUS_REG_DEFAULT 0x0
+	/*[field] MAC_LENGTHTYPE*/
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_LENGTHTYPE
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_LENGTHTYPE_OFFSET  0
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_LENGTHTYPE_LEN     1
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_LENGTHTYPE_DEFAULT 0x0
+	/*[field] MAC_DA*/
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_DA
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_DA_OFFSET  1
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_DA_LEN     1
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_DA_DEFAULT 0x0
+	/*[field] MAC_PTP_PRIM_ADDR*/
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_OFFSET  2
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_LEN     1
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_DEFAULT 0x0
+	/*[field] MAC_PTP_PDELAY_ADDR*/
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_OFFSET  3
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_LEN     1
+	#define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_DEFAULT 0x0
+	/*[field] IPV4_LAYER4_PROTOCOL*/
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_OFFSET  4
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_LEN     1
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_DEFAULT 0x0
+	/*[field] IPV4_DA*/
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_DA
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_DA_OFFSET  5
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_DA_LEN     1
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_DA_DEFAULT 0x0
+	/*[field] IPV4_PTP_PRIM_ADDR*/
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_OFFSET  6
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_LEN     1
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_DEFAULT 0x0
+	/*[field] IPV4_PTP_PDELAY_ADDR*/
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_OFFSET  7
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_LEN     1
+	#define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_DEFAULT 0x0
+	/*[field] IPV6_NEXT_HEADER*/
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_OFFSET  8
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_LEN     1
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_DEFAULT 0x0
+	/*[field] IPV6_DA*/
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_DA
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_DA_OFFSET  9
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_DA_LEN     1
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_DA_DEFAULT 0x0
+	/*[field] IPV6_PTP_PRIM_ADDR*/
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_OFFSET  10
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_LEN     1
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_DEFAULT 0x0
+	/*[field] IPV6_PTP_PDELAY_ADDR*/
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_OFFSET  11
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_LEN     1
+	#define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_DEFAULT 0x0
+	/*[field] UDP_DPORT*/
+	#define PTP_RX_COM_TS_STATUS_REG_UDP_DPORT
+	#define PTP_RX_COM_TS_STATUS_REG_UDP_DPORT_OFFSET  12
+	#define PTP_RX_COM_TS_STATUS_REG_UDP_DPORT_LEN     1
+	#define PTP_RX_COM_TS_STATUS_REG_UDP_DPORT_DEFAULT 0x0
+	/*[field] UDP_PTP_EVENT_DPORT*/
+	#define PTP_RX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT
+	#define PTP_RX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_OFFSET  13
+	#define PTP_RX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_LEN     1
+	#define PTP_RX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_DEFAULT 0x0
+	/*[field] Y1731_MACH*/
+	#define PTP_RX_COM_TS_STATUS_REG_Y1731_MACH
+	#define PTP_RX_COM_TS_STATUS_REG_Y1731_MACH_OFFSET  14
+	#define PTP_RX_COM_TS_STATUS_REG_Y1731_MACH_LEN     1
+	#define PTP_RX_COM_TS_STATUS_REG_Y1731_MACH_DEFAULT 0x0
+
+struct ptp_rx_com_ts_status_reg {
+	a_uint32_t  mac_lengthtype:1;
+	a_uint32_t  mac_da:1;
+	a_uint32_t  mac_ptp_prim_addr:1;
+	a_uint32_t  mac_ptp_pdelay_addr:1;
+	a_uint32_t  ipv4_layer4_protocol:1;
+	a_uint32_t  ipv4_da:1;
+	a_uint32_t  ipv4_ptp_prim_addr:1;
+	a_uint32_t  ipv4_ptp_pdelay_addr:1;
+	a_uint32_t  ipv6_next_header:1;
+	a_uint32_t  ipv6_da:1;
+	a_uint32_t  ipv6_ptp_prim_addr:1;
+	a_uint32_t  ipv6_ptp_pdelay_addr:1;
+	a_uint32_t  udp_dport:1;
+	a_uint32_t  udp_ptp_event_dport:1;
+	a_uint32_t  y1731_mach:1;
+};
+
+union ptp_rx_com_ts_status_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_com_ts_status_reg bf;
+};
+
+/*[register] PTP_RX_COM_TIMESTAMP0_REG*/
+#define PTP_RX_COM_TIMESTAMP0_REG
+#define PTP_RX_COM_TIMESTAMP0_REG_ADDRESS 0x8612
+#define PTP_RX_COM_TIMESTAMP0_REG_NUM     1
+#define PTP_RX_COM_TIMESTAMP0_REG_INC     0x1
+#define PTP_RX_COM_TIMESTAMP0_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_COM_TIMESTAMP0_REG_DEFAULT 0x0
+	/*[field] COM_TS*/
+	#define PTP_RX_COM_TIMESTAMP0_REG_COM_TS
+	#define PTP_RX_COM_TIMESTAMP0_REG_COM_TS_OFFSET  0
+	#define PTP_RX_COM_TIMESTAMP0_REG_COM_TS_LEN     16
+	#define PTP_RX_COM_TIMESTAMP0_REG_COM_TS_DEFAULT 0x0
+
+struct ptp_rx_com_timestamp0_reg {
+	a_uint32_t  com_ts:16;
+};
+
+union ptp_rx_com_timestamp0_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_com_timestamp0_reg bf;
+};
+
+/*[register] PTP_RX_COM_TIMESTAMP1_REG*/
+#define PTP_RX_COM_TIMESTAMP1_REG
+#define PTP_RX_COM_TIMESTAMP1_REG_ADDRESS 0x8613
+#define PTP_RX_COM_TIMESTAMP1_REG_NUM     1
+#define PTP_RX_COM_TIMESTAMP1_REG_INC     0x1
+#define PTP_RX_COM_TIMESTAMP1_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_COM_TIMESTAMP1_REG_DEFAULT 0x0
+	/*[field] COM_TS*/
+	#define PTP_RX_COM_TIMESTAMP1_REG_COM_TS
+	#define PTP_RX_COM_TIMESTAMP1_REG_COM_TS_OFFSET  0
+	#define PTP_RX_COM_TIMESTAMP1_REG_COM_TS_LEN     16
+	#define PTP_RX_COM_TIMESTAMP1_REG_COM_TS_DEFAULT 0x0
+
+struct ptp_rx_com_timestamp1_reg {
+	a_uint32_t  com_ts:16;
+};
+
+union ptp_rx_com_timestamp1_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_com_timestamp1_reg bf;
+};
+
+/*[register] PTP_RX_COM_TIMESTAMP2_REG*/
+#define PTP_RX_COM_TIMESTAMP2_REG
+#define PTP_RX_COM_TIMESTAMP2_REG_ADDRESS 0x8614
+#define PTP_RX_COM_TIMESTAMP2_REG_NUM     1
+#define PTP_RX_COM_TIMESTAMP2_REG_INC     0x1
+#define PTP_RX_COM_TIMESTAMP2_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_COM_TIMESTAMP2_REG_DEFAULT 0x0
+	/*[field] COM_TS*/
+	#define PTP_RX_COM_TIMESTAMP2_REG_COM_TS
+	#define PTP_RX_COM_TIMESTAMP2_REG_COM_TS_OFFSET  0
+	#define PTP_RX_COM_TIMESTAMP2_REG_COM_TS_LEN     16
+	#define PTP_RX_COM_TIMESTAMP2_REG_COM_TS_DEFAULT 0x0
+
+struct ptp_rx_com_timestamp2_reg {
+	a_uint32_t  com_ts:16;
+};
+
+union ptp_rx_com_timestamp2_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_com_timestamp2_reg bf;
+};
+
+/*[register] PTP_RX_COM_TIMESTAMP3_REG*/
+#define PTP_RX_COM_TIMESTAMP3_REG
+#define PTP_RX_COM_TIMESTAMP3_REG_ADDRESS 0x8615
+#define PTP_RX_COM_TIMESTAMP3_REG_NUM     1
+#define PTP_RX_COM_TIMESTAMP3_REG_INC     0x1
+#define PTP_RX_COM_TIMESTAMP3_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_COM_TIMESTAMP3_REG_DEFAULT 0x0
+	/*[field] COM_TS*/
+	#define PTP_RX_COM_TIMESTAMP3_REG_COM_TS
+	#define PTP_RX_COM_TIMESTAMP3_REG_COM_TS_OFFSET  0
+	#define PTP_RX_COM_TIMESTAMP3_REG_COM_TS_LEN     16
+	#define PTP_RX_COM_TIMESTAMP3_REG_COM_TS_DEFAULT 0x0
+
+struct ptp_rx_com_timestamp3_reg {
+	a_uint32_t  com_ts:16;
+};
+
+union ptp_rx_com_timestamp3_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_com_timestamp3_reg bf;
+};
+
+/*[register] PTP_RX_COM_TIMESTAMP4_REG*/
+#define PTP_RX_COM_TIMESTAMP4_REG
+#define PTP_RX_COM_TIMESTAMP4_REG_ADDRESS 0x8616
+#define PTP_RX_COM_TIMESTAMP4_REG_NUM     1
+#define PTP_RX_COM_TIMESTAMP4_REG_INC     0x1
+#define PTP_RX_COM_TIMESTAMP4_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_COM_TIMESTAMP4_REG_DEFAULT 0x0
+	/*[field] COM_TS*/
+	#define PTP_RX_COM_TIMESTAMP4_REG_COM_TS
+	#define PTP_RX_COM_TIMESTAMP4_REG_COM_TS_OFFSET  0
+	#define PTP_RX_COM_TIMESTAMP4_REG_COM_TS_LEN     16
+	#define PTP_RX_COM_TIMESTAMP4_REG_COM_TS_DEFAULT 0x0
+
+struct ptp_rx_com_timestamp4_reg {
+	a_uint32_t  com_ts:16;
+};
+
+union ptp_rx_com_timestamp4_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_com_timestamp4_reg bf;
+};
+
+/*[register] PTP_RX_COM_FRAC_NANO_REG*/
+#define PTP_RX_COM_FRAC_NANO_REG
+#define PTP_RX_COM_FRAC_NANO_REG_ADDRESS 0x8617
+#define PTP_RX_COM_FRAC_NANO_REG_NUM     1
+#define PTP_RX_COM_FRAC_NANO_REG_INC     0x1
+#define PTP_RX_COM_FRAC_NANO_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_COM_FRAC_NANO_REG_DEFAULT 0x0
+	/*[field] FRAC_NANO*/
+	#define PTP_RX_COM_FRAC_NANO_REG_FRAC_NANO
+	#define PTP_RX_COM_FRAC_NANO_REG_FRAC_NANO_OFFSET  0
+	#define PTP_RX_COM_FRAC_NANO_REG_FRAC_NANO_LEN     16
+	#define PTP_RX_COM_FRAC_NANO_REG_FRAC_NANO_DEFAULT 0x0
+
+struct ptp_rx_com_frac_nano_reg {
+	a_uint32_t  frac_nano:16;
+};
+
+union ptp_rx_com_frac_nano_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_com_frac_nano_reg bf;
+};
+
+/*[register] PTP_RX_COM_TIMESTAMP_PRE0_REG*/
+#define PTP_RX_COM_TIMESTAMP_PRE0_REG
+#define PTP_RX_COM_TIMESTAMP_PRE0_REG_ADDRESS 0x8618
+#define PTP_RX_COM_TIMESTAMP_PRE0_REG_NUM     1
+#define PTP_RX_COM_TIMESTAMP_PRE0_REG_INC     0x1
+#define PTP_RX_COM_TIMESTAMP_PRE0_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_COM_TIMESTAMP_PRE0_REG_DEFAULT 0x0
+	/*[field] COM_TS_PRE*/
+	#define PTP_RX_COM_TIMESTAMP_PRE0_REG_COM_TS_PRE
+	#define PTP_RX_COM_TIMESTAMP_PRE0_REG_COM_TS_PRE_OFFSET  0
+	#define PTP_RX_COM_TIMESTAMP_PRE0_REG_COM_TS_PRE_LEN     16
+	#define PTP_RX_COM_TIMESTAMP_PRE0_REG_COM_TS_PRE_DEFAULT 0x0
+
+struct ptp_rx_com_timestamp_pre0_reg {
+	a_uint32_t  com_ts_pre:16;
+};
+
+union ptp_rx_com_timestamp_pre0_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_com_timestamp_pre0_reg bf;
+};
+
+/*[register] PTP_RX_COM_TIMESTAMP_PRE1_REG*/
+#define PTP_RX_COM_TIMESTAMP_PRE1_REG
+#define PTP_RX_COM_TIMESTAMP_PRE1_REG_ADDRESS 0x8619
+#define PTP_RX_COM_TIMESTAMP_PRE1_REG_NUM     1
+#define PTP_RX_COM_TIMESTAMP_PRE1_REG_INC     0x1
+#define PTP_RX_COM_TIMESTAMP_PRE1_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_COM_TIMESTAMP_PRE1_REG_DEFAULT 0x0
+	/*[field] COM_TS_PRE*/
+	#define PTP_RX_COM_TIMESTAMP_PRE1_REG_COM_TS_PRE
+	#define PTP_RX_COM_TIMESTAMP_PRE1_REG_COM_TS_PRE_OFFSET  0
+	#define PTP_RX_COM_TIMESTAMP_PRE1_REG_COM_TS_PRE_LEN     16
+	#define PTP_RX_COM_TIMESTAMP_PRE1_REG_COM_TS_PRE_DEFAULT 0x0
+
+struct ptp_rx_com_timestamp_pre1_reg {
+	a_uint32_t  com_ts_pre:16;
+};
+
+union ptp_rx_com_timestamp_pre1_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_com_timestamp_pre1_reg bf;
+};
+
+/*[register] PTP_RX_COM_TIMESTAMP_PRE2_REG*/
+#define PTP_RX_COM_TIMESTAMP_PRE2_REG
+#define PTP_RX_COM_TIMESTAMP_PRE2_REG_ADDRESS 0x861a
+#define PTP_RX_COM_TIMESTAMP_PRE2_REG_NUM     1
+#define PTP_RX_COM_TIMESTAMP_PRE2_REG_INC     0x1
+#define PTP_RX_COM_TIMESTAMP_PRE2_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_COM_TIMESTAMP_PRE2_REG_DEFAULT 0x0
+	/*[field] COM_TS_PRE*/
+	#define PTP_RX_COM_TIMESTAMP_PRE2_REG_COM_TS_PRE
+	#define PTP_RX_COM_TIMESTAMP_PRE2_REG_COM_TS_PRE_OFFSET  0
+	#define PTP_RX_COM_TIMESTAMP_PRE2_REG_COM_TS_PRE_LEN     16
+	#define PTP_RX_COM_TIMESTAMP_PRE2_REG_COM_TS_PRE_DEFAULT 0x0
+
+struct ptp_rx_com_timestamp_pre2_reg {
+	a_uint32_t  com_ts_pre:16;
+};
+
+union ptp_rx_com_timestamp_pre2_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_com_timestamp_pre2_reg bf;
+};
+
+/*[register] PTP_RX_COM_TIMESTAMP_PRE3_REG*/
+#define PTP_RX_COM_TIMESTAMP_PRE3_REG
+#define PTP_RX_COM_TIMESTAMP_PRE3_REG_ADDRESS 0x861b
+#define PTP_RX_COM_TIMESTAMP_PRE3_REG_NUM     1
+#define PTP_RX_COM_TIMESTAMP_PRE3_REG_INC     0x1
+#define PTP_RX_COM_TIMESTAMP_PRE3_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_COM_TIMESTAMP_PRE3_REG_DEFAULT 0x0
+	/*[field] COM_TS_PRE*/
+	#define PTP_RX_COM_TIMESTAMP_PRE3_REG_COM_TS_PRE
+	#define PTP_RX_COM_TIMESTAMP_PRE3_REG_COM_TS_PRE_OFFSET  0
+	#define PTP_RX_COM_TIMESTAMP_PRE3_REG_COM_TS_PRE_LEN     16
+	#define PTP_RX_COM_TIMESTAMP_PRE3_REG_COM_TS_PRE_DEFAULT 0x0
+
+struct ptp_rx_com_timestamp_pre3_reg {
+	a_uint32_t  com_ts_pre:16;
+};
+
+union ptp_rx_com_timestamp_pre3_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_com_timestamp_pre3_reg bf;
+};
+
+/*[register] PTP_RX_COM_TIMESTAMP_PRE4_REG*/
+#define PTP_RX_COM_TIMESTAMP_PRE4_REG
+#define PTP_RX_COM_TIMESTAMP_PRE4_REG_ADDRESS 0x861c
+#define PTP_RX_COM_TIMESTAMP_PRE4_REG_NUM     1
+#define PTP_RX_COM_TIMESTAMP_PRE4_REG_INC     0x1
+#define PTP_RX_COM_TIMESTAMP_PRE4_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_COM_TIMESTAMP_PRE4_REG_DEFAULT 0x0
+	/*[field] COM_TS_PRE*/
+	#define PTP_RX_COM_TIMESTAMP_PRE4_REG_COM_TS_PRE
+	#define PTP_RX_COM_TIMESTAMP_PRE4_REG_COM_TS_PRE_OFFSET  0
+	#define PTP_RX_COM_TIMESTAMP_PRE4_REG_COM_TS_PRE_LEN     16
+	#define PTP_RX_COM_TIMESTAMP_PRE4_REG_COM_TS_PRE_DEFAULT 0x0
+
+struct ptp_rx_com_timestamp_pre4_reg {
+	a_uint32_t  com_ts_pre:16;
+};
+
+union ptp_rx_com_timestamp_pre4_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_com_timestamp_pre4_reg bf;
+};
+
+/*[register] PTP_RX_COM_FRAC_NANO_PRE_REG*/
+#define PTP_RX_COM_FRAC_NANO_PRE_REG
+#define PTP_RX_COM_FRAC_NANO_PRE_REG_ADDRESS 0x861d
+#define PTP_RX_COM_FRAC_NANO_PRE_REG_NUM     1
+#define PTP_RX_COM_FRAC_NANO_PRE_REG_INC     0x1
+#define PTP_RX_COM_FRAC_NANO_PRE_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_COM_FRAC_NANO_PRE_REG_DEFAULT 0x0
+	/*[field] FRAC_NANO_PRE*/
+	#define PTP_RX_COM_FRAC_NANO_PRE_REG_FRAC_NANO_PRE
+	#define PTP_RX_COM_FRAC_NANO_PRE_REG_FRAC_NANO_PRE_OFFSET  0
+	#define PTP_RX_COM_FRAC_NANO_PRE_REG_FRAC_NANO_PRE_LEN     16
+	#define PTP_RX_COM_FRAC_NANO_PRE_REG_FRAC_NANO_PRE_DEFAULT 0x0
+
+struct ptp_rx_com_frac_nano_pre_reg {
+	a_uint32_t  frac_nano_pre:16;
+};
+
+union ptp_rx_com_frac_nano_pre_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_com_frac_nano_pre_reg bf;
+};
+
+/*[register] PTP_RX_Y1731_IDENTIFY_REG*/
+#define PTP_RX_Y1731_IDENTIFY_REG
+#define PTP_RX_Y1731_IDENTIFY_REG_ADDRESS 0x861e
+#define PTP_RX_Y1731_IDENTIFY_REG_NUM     1
+#define PTP_RX_Y1731_IDENTIFY_REG_INC     0x1
+#define PTP_RX_Y1731_IDENTIFY_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_Y1731_IDENTIFY_REG_DEFAULT 0x0
+	/*[field] IDENTIFY*/
+	#define PTP_RX_Y1731_IDENTIFY_REG_IDENTIFY
+	#define PTP_RX_Y1731_IDENTIFY_REG_IDENTIFY_OFFSET  0
+	#define PTP_RX_Y1731_IDENTIFY_REG_IDENTIFY_LEN     16
+	#define PTP_RX_Y1731_IDENTIFY_REG_IDENTIFY_DEFAULT 0x0
+
+struct ptp_rx_y1731_identify_reg {
+	a_uint32_t  identify:16;
+};
+
+union ptp_rx_y1731_identify_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_y1731_identify_reg bf;
+};
+
+/*[register] PTP_RX_Y1731_IDENTIFY_PRE_REG*/
+#define PTP_RX_Y1731_IDENTIFY_PRE_REG
+#define PTP_RX_Y1731_IDENTIFY_PRE_REG_ADDRESS 0x861f
+#define PTP_RX_Y1731_IDENTIFY_PRE_REG_NUM     1
+#define PTP_RX_Y1731_IDENTIFY_PRE_REG_INC     0x1
+#define PTP_RX_Y1731_IDENTIFY_PRE_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_Y1731_IDENTIFY_PRE_REG_DEFAULT 0x0
+	/*[field] IDENTIFY_PRE*/
+	#define PTP_RX_Y1731_IDENTIFY_PRE_REG_IDENTIFY_PRE
+	#define PTP_RX_Y1731_IDENTIFY_PRE_REG_IDENTIFY_PRE_OFFSET  0
+	#define PTP_RX_Y1731_IDENTIFY_PRE_REG_IDENTIFY_PRE_LEN     16
+	#define PTP_RX_Y1731_IDENTIFY_PRE_REG_IDENTIFY_PRE_DEFAULT 0x0
+
+struct ptp_rx_y1731_identify_pre_reg {
+	a_uint32_t  identify_pre:16;
+};
+
+union ptp_rx_y1731_identify_pre_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_y1731_identify_pre_reg bf;
+};
+
+/*[register] PTP_TX_COM_TS_CTRL_REG*/
+#define PTP_TX_COM_TS_CTRL_REG
+#define PTP_TX_COM_TS_CTRL_REG_ADDRESS 0x8620
+#define PTP_TX_COM_TS_CTRL_REG_NUM     1
+#define PTP_TX_COM_TS_CTRL_REG_INC     0x1
+#define PTP_TX_COM_TS_CTRL_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_COM_TS_CTRL_REG_DEFAULT 0x0
+	/*[field] FILT_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_FILT_EN
+	#define PTP_TX_COM_TS_CTRL_REG_FILT_EN_OFFSET  0
+	#define PTP_TX_COM_TS_CTRL_REG_FILT_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_FILT_EN_DEFAULT 0x0
+	/*[field] MAC_LENGTHTYPE_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN
+	#define PTP_TX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN_OFFSET  1
+	#define PTP_TX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN_DEFAULT 0x0
+	/*[field] MAC_DA_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_MAC_DA_EN
+	#define PTP_TX_COM_TS_CTRL_REG_MAC_DA_EN_OFFSET  2
+	#define PTP_TX_COM_TS_CTRL_REG_MAC_DA_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_MAC_DA_EN_DEFAULT 0x0
+	/*[field] MAC_PTP_FILT_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN
+	#define PTP_TX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_OFFSET  3
+	#define PTP_TX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_DEFAULT 0x0
+	/*[field] IPV4_LAYER4_PROTOCOL_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN
+	#define PTP_TX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_OFFSET  4
+	#define PTP_TX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_DEFAULT 0x0
+	/*[field] IPV4_DA_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_IPV4_DA_EN
+	#define PTP_TX_COM_TS_CTRL_REG_IPV4_DA_EN_OFFSET  5
+	#define PTP_TX_COM_TS_CTRL_REG_IPV4_DA_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_IPV4_DA_EN_DEFAULT 0x0
+	/*[field] IPV4_PTP_FILT_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN
+	#define PTP_TX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_OFFSET  6
+	#define PTP_TX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_DEFAULT 0x0
+	/*[field] IPV6_NEXT_HEADER_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN
+	#define PTP_TX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_OFFSET  7
+	#define PTP_TX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_DEFAULT 0x0
+	/*[field] IPV6_DA_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_IPV6_DA_EN
+	#define PTP_TX_COM_TS_CTRL_REG_IPV6_DA_EN_OFFSET  8
+	#define PTP_TX_COM_TS_CTRL_REG_IPV6_DA_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_IPV6_DA_EN_DEFAULT 0x0
+	/*[field] IPV6_PTP_FILT_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN
+	#define PTP_TX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_OFFSET  9
+	#define PTP_TX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_DEFAULT 0x0
+	/*[field] UDP_DPORT_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_UDP_DPORT_EN
+	#define PTP_TX_COM_TS_CTRL_REG_UDP_DPORT_EN_OFFSET  10
+	#define PTP_TX_COM_TS_CTRL_REG_UDP_DPORT_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_UDP_DPORT_EN_DEFAULT 0x0
+	/*[field] UDP_PTP_EVENT_FILT_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN
+	#define PTP_TX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_OFFSET  11
+	#define PTP_TX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_DEFAULT 0x0
+	/*[field] Y1731_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_Y1731_EN
+	#define PTP_TX_COM_TS_CTRL_REG_Y1731_EN_OFFSET  12
+	#define PTP_TX_COM_TS_CTRL_REG_Y1731_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_Y1731_EN_DEFAULT 0x0
+	/*[field] Y1731_INSERT_TS_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN
+	#define PTP_TX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_OFFSET  13
+	#define PTP_TX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_DEFAULT 0x0
+	/*[field] Y1731_SA_CHK_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_Y1731_SA_CHK_EN
+	#define PTP_TX_COM_TS_CTRL_REG_Y1731_SA_CHK_EN_OFFSET  14
+	#define PTP_TX_COM_TS_CTRL_REG_Y1731_SA_CHK_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_Y1731_SA_CHK_EN_DEFAULT 0x0
+	/*[field] PW_MAC_EN*/
+	#define PTP_TX_COM_TS_CTRL_REG_PW_MAC_EN
+	#define PTP_TX_COM_TS_CTRL_REG_PW_MAC_EN_OFFSET  15
+	#define PTP_TX_COM_TS_CTRL_REG_PW_MAC_EN_LEN     1
+	#define PTP_TX_COM_TS_CTRL_REG_PW_MAC_EN_DEFAULT 0x0
+
+struct ptp_tx_com_ts_ctrl_reg {
+	a_uint32_t  filt_en:1;
+	a_uint32_t  mac_lengthtype_en:1;
+	a_uint32_t  mac_da_en:1;
+	a_uint32_t  mac_ptp_filt_en:1;
+	a_uint32_t  ipv4_layer4_protocol_en:1;
+	a_uint32_t  ipv4_da_en:1;
+	a_uint32_t  ipv4_ptp_filt_en:1;
+	a_uint32_t  ipv6_next_header_en:1;
+	a_uint32_t  ipv6_da_en:1;
+	a_uint32_t  ipv6_ptp_filt_en:1;
+	a_uint32_t  udp_dport_en:1;
+	a_uint32_t  udp_ptp_event_filt_en:1;
+	a_uint32_t  y1731_en:1;
+	a_uint32_t  y1731_insert_ts_en:1;
+	a_uint32_t  y1731_sa_chk_en:1;
+	a_uint32_t  pw_mac_en:1;
+};
+
+union ptp_tx_com_ts_ctrl_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_com_ts_ctrl_reg bf;
+};
+
+/*[register] PTP_TX_FILT_MAC_DA0_REG*/
+#define PTP_TX_FILT_MAC_DA0_REG
+#define PTP_TX_FILT_MAC_DA0_REG_ADDRESS 0x8621
+#define PTP_TX_FILT_MAC_DA0_REG_NUM     1
+#define PTP_TX_FILT_MAC_DA0_REG_INC     0x1
+#define PTP_TX_FILT_MAC_DA0_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_MAC_DA0_REG_DEFAULT 0x0
+	/*[field] MAC_ADDR*/
+	#define PTP_TX_FILT_MAC_DA0_REG_MAC_ADDR
+	#define PTP_TX_FILT_MAC_DA0_REG_MAC_ADDR_OFFSET  0
+	#define PTP_TX_FILT_MAC_DA0_REG_MAC_ADDR_LEN     16
+	#define PTP_TX_FILT_MAC_DA0_REG_MAC_ADDR_DEFAULT 0x0
+
+struct ptp_tx_filt_mac_da0_reg {
+	a_uint32_t  mac_addr:16;
+};
+
+union ptp_tx_filt_mac_da0_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_mac_da0_reg bf;
+};
+
+/*[register] PTP_TX_FILT_MAC_DA1_REG*/
+#define PTP_TX_FILT_MAC_DA1_REG
+#define PTP_TX_FILT_MAC_DA1_REG_ADDRESS 0x8622
+#define PTP_TX_FILT_MAC_DA1_REG_NUM     1
+#define PTP_TX_FILT_MAC_DA1_REG_INC     0x1
+#define PTP_TX_FILT_MAC_DA1_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_MAC_DA1_REG_DEFAULT 0x0
+	/*[field] MAC_ADDR*/
+	#define PTP_TX_FILT_MAC_DA1_REG_MAC_ADDR
+	#define PTP_TX_FILT_MAC_DA1_REG_MAC_ADDR_OFFSET  0
+	#define PTP_TX_FILT_MAC_DA1_REG_MAC_ADDR_LEN     16
+	#define PTP_TX_FILT_MAC_DA1_REG_MAC_ADDR_DEFAULT 0x0
+
+struct ptp_tx_filt_mac_da1_reg {
+	a_uint32_t  mac_addr:16;
+};
+
+union ptp_tx_filt_mac_da1_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_mac_da1_reg bf;
+};
+
+/*[register] PTP_TX_FILT_MAC_DA2_REG*/
+#define PTP_TX_FILT_MAC_DA2_REG
+#define PTP_TX_FILT_MAC_DA2_REG_ADDRESS 0x8623
+#define PTP_TX_FILT_MAC_DA2_REG_NUM     1
+#define PTP_TX_FILT_MAC_DA2_REG_INC     0x1
+#define PTP_TX_FILT_MAC_DA2_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_MAC_DA2_REG_DEFAULT 0x0
+	/*[field] MAC_ADDR*/
+	#define PTP_TX_FILT_MAC_DA2_REG_MAC_ADDR
+	#define PTP_TX_FILT_MAC_DA2_REG_MAC_ADDR_OFFSET  0
+	#define PTP_TX_FILT_MAC_DA2_REG_MAC_ADDR_LEN     16
+	#define PTP_TX_FILT_MAC_DA2_REG_MAC_ADDR_DEFAULT 0x0
+
+struct ptp_tx_filt_mac_da2_reg {
+	a_uint32_t  mac_addr:16;
+};
+
+union ptp_tx_filt_mac_da2_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_mac_da2_reg bf;
+};
+
+/*[register] PTP_TX_FILT_IPV4_DA0_REG*/
+#define PTP_TX_FILT_IPV4_DA0_REG
+#define PTP_TX_FILT_IPV4_DA0_REG_ADDRESS 0x8624
+#define PTP_TX_FILT_IPV4_DA0_REG_NUM     1
+#define PTP_TX_FILT_IPV4_DA0_REG_INC     0x1
+#define PTP_TX_FILT_IPV4_DA0_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_IPV4_DA0_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_TX_FILT_IPV4_DA0_REG_IP_ADDR
+	#define PTP_TX_FILT_IPV4_DA0_REG_IP_ADDR_OFFSET  0
+	#define PTP_TX_FILT_IPV4_DA0_REG_IP_ADDR_LEN     16
+	#define PTP_TX_FILT_IPV4_DA0_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_tx_filt_ipv4_da0_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_tx_filt_ipv4_da0_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_ipv4_da0_reg bf;
+};
+
+/*[register] PTP_TX_FILT_IPV4_DA1_REG*/
+#define PTP_TX_FILT_IPV4_DA1_REG
+#define PTP_TX_FILT_IPV4_DA1_REG_ADDRESS 0x8625
+#define PTP_TX_FILT_IPV4_DA1_REG_NUM     1
+#define PTP_TX_FILT_IPV4_DA1_REG_INC     0x1
+#define PTP_TX_FILT_IPV4_DA1_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_IPV4_DA1_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_TX_FILT_IPV4_DA1_REG_IP_ADDR
+	#define PTP_TX_FILT_IPV4_DA1_REG_IP_ADDR_OFFSET  0
+	#define PTP_TX_FILT_IPV4_DA1_REG_IP_ADDR_LEN     16
+	#define PTP_TX_FILT_IPV4_DA1_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_tx_filt_ipv4_da1_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_tx_filt_ipv4_da1_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_ipv4_da1_reg bf;
+};
+
+/*[register] PTP_TX_FILT_IPV6_DA0_REG*/
+#define PTP_TX_FILT_IPV6_DA0_REG
+#define PTP_TX_FILT_IPV6_DA0_REG_ADDRESS 0x8626
+#define PTP_TX_FILT_IPV6_DA0_REG_NUM     1
+#define PTP_TX_FILT_IPV6_DA0_REG_INC     0x1
+#define PTP_TX_FILT_IPV6_DA0_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_IPV6_DA0_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_TX_FILT_IPV6_DA0_REG_IP_ADDR
+	#define PTP_TX_FILT_IPV6_DA0_REG_IP_ADDR_OFFSET  0
+	#define PTP_TX_FILT_IPV6_DA0_REG_IP_ADDR_LEN     16
+	#define PTP_TX_FILT_IPV6_DA0_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_tx_filt_ipv6_da0_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_tx_filt_ipv6_da0_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_ipv6_da0_reg bf;
+};
+
+/*[register] PTP_TX_FILT_IPV6_DA1_REG*/
+#define PTP_TX_FILT_IPV6_DA1_REG
+#define PTP_TX_FILT_IPV6_DA1_REG_ADDRESS 0x8627
+#define PTP_TX_FILT_IPV6_DA1_REG_NUM     1
+#define PTP_TX_FILT_IPV6_DA1_REG_INC     0x1
+#define PTP_TX_FILT_IPV6_DA1_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_IPV6_DA1_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_TX_FILT_IPV6_DA1_REG_IP_ADDR
+	#define PTP_TX_FILT_IPV6_DA1_REG_IP_ADDR_OFFSET  0
+	#define PTP_TX_FILT_IPV6_DA1_REG_IP_ADDR_LEN     16
+	#define PTP_TX_FILT_IPV6_DA1_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_tx_filt_ipv6_da1_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_tx_filt_ipv6_da1_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_ipv6_da1_reg bf;
+};
+
+/*[register] PTP_TX_FILT_IPV6_DA2_REG*/
+#define PTP_TX_FILT_IPV6_DA2_REG
+#define PTP_TX_FILT_IPV6_DA2_REG_ADDRESS 0x8628
+#define PTP_TX_FILT_IPV6_DA2_REG_NUM     1
+#define PTP_TX_FILT_IPV6_DA2_REG_INC     0x1
+#define PTP_TX_FILT_IPV6_DA2_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_IPV6_DA2_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_TX_FILT_IPV6_DA2_REG_IP_ADDR
+	#define PTP_TX_FILT_IPV6_DA2_REG_IP_ADDR_OFFSET  0
+	#define PTP_TX_FILT_IPV6_DA2_REG_IP_ADDR_LEN     16
+	#define PTP_TX_FILT_IPV6_DA2_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_tx_filt_ipv6_da2_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_tx_filt_ipv6_da2_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_ipv6_da2_reg bf;
+};
+
+/*[register] PTP_TX_FILT_IPV6_DA3_REG*/
+#define PTP_TX_FILT_IPV6_DA3_REG
+#define PTP_TX_FILT_IPV6_DA3_REG_ADDRESS 0x8629
+#define PTP_TX_FILT_IPV6_DA3_REG_NUM     1
+#define PTP_TX_FILT_IPV6_DA3_REG_INC     0x1
+#define PTP_TX_FILT_IPV6_DA3_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_IPV6_DA3_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_TX_FILT_IPV6_DA3_REG_IP_ADDR
+	#define PTP_TX_FILT_IPV6_DA3_REG_IP_ADDR_OFFSET  0
+	#define PTP_TX_FILT_IPV6_DA3_REG_IP_ADDR_LEN     16
+	#define PTP_TX_FILT_IPV6_DA3_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_tx_filt_ipv6_da3_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_tx_filt_ipv6_da3_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_ipv6_da3_reg bf;
+};
+
+/*[register] PTP_TX_FILT_IPV6_DA4_REG*/
+#define PTP_TX_FILT_IPV6_DA4_REG
+#define PTP_TX_FILT_IPV6_DA4_REG_ADDRESS 0x862a
+#define PTP_TX_FILT_IPV6_DA4_REG_NUM     1
+#define PTP_TX_FILT_IPV6_DA4_REG_INC     0x1
+#define PTP_TX_FILT_IPV6_DA4_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_IPV6_DA4_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_TX_FILT_IPV6_DA4_REG_IP_ADDR
+	#define PTP_TX_FILT_IPV6_DA4_REG_IP_ADDR_OFFSET  0
+	#define PTP_TX_FILT_IPV6_DA4_REG_IP_ADDR_LEN     16
+	#define PTP_TX_FILT_IPV6_DA4_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_tx_filt_ipv6_da4_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_tx_filt_ipv6_da4_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_ipv6_da4_reg bf;
+};
+
+/*[register] PTP_TX_FILT_IPV6_DA5_REG*/
+#define PTP_TX_FILT_IPV6_DA5_REG
+#define PTP_TX_FILT_IPV6_DA5_REG_ADDRESS 0x862b
+#define PTP_TX_FILT_IPV6_DA5_REG_NUM     1
+#define PTP_TX_FILT_IPV6_DA5_REG_INC     0x1
+#define PTP_TX_FILT_IPV6_DA5_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_IPV6_DA5_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_TX_FILT_IPV6_DA5_REG_IP_ADDR
+	#define PTP_TX_FILT_IPV6_DA5_REG_IP_ADDR_OFFSET  0
+	#define PTP_TX_FILT_IPV6_DA5_REG_IP_ADDR_LEN     16
+	#define PTP_TX_FILT_IPV6_DA5_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_tx_filt_ipv6_da5_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_tx_filt_ipv6_da5_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_ipv6_da5_reg bf;
+};
+
+/*[register] PTP_TX_FILT_IPV6_DA6_REG*/
+#define PTP_TX_FILT_IPV6_DA6_REG
+#define PTP_TX_FILT_IPV6_DA6_REG_ADDRESS 0x862c
+#define PTP_TX_FILT_IPV6_DA6_REG_NUM     1
+#define PTP_TX_FILT_IPV6_DA6_REG_INC     0x1
+#define PTP_TX_FILT_IPV6_DA6_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_IPV6_DA6_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_TX_FILT_IPV6_DA6_REG_IP_ADDR
+	#define PTP_TX_FILT_IPV6_DA6_REG_IP_ADDR_OFFSET  0
+	#define PTP_TX_FILT_IPV6_DA6_REG_IP_ADDR_LEN     16
+	#define PTP_TX_FILT_IPV6_DA6_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_tx_filt_ipv6_da6_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_tx_filt_ipv6_da6_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_ipv6_da6_reg bf;
+};
+
+/*[register] PTP_TX_FILT_IPV6_DA7_REG*/
+#define PTP_TX_FILT_IPV6_DA7_REG
+#define PTP_TX_FILT_IPV6_DA7_REG_ADDRESS 0x862d
+#define PTP_TX_FILT_IPV6_DA7_REG_NUM     1
+#define PTP_TX_FILT_IPV6_DA7_REG_INC     0x1
+#define PTP_TX_FILT_IPV6_DA7_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_IPV6_DA7_REG_DEFAULT 0x0
+	/*[field] IP_ADDR*/
+	#define PTP_TX_FILT_IPV6_DA7_REG_IP_ADDR
+	#define PTP_TX_FILT_IPV6_DA7_REG_IP_ADDR_OFFSET  0
+	#define PTP_TX_FILT_IPV6_DA7_REG_IP_ADDR_LEN     16
+	#define PTP_TX_FILT_IPV6_DA7_REG_IP_ADDR_DEFAULT 0x0
+
+struct ptp_tx_filt_ipv6_da7_reg {
+	a_uint32_t  ip_addr:16;
+};
+
+union ptp_tx_filt_ipv6_da7_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_ipv6_da7_reg bf;
+};
+
+/*[register] PTP_TX_FILT_MAC_LENGTHTYPE_REG*/
+#define PTP_TX_FILT_MAC_LENGTHTYPE_REG
+#define PTP_TX_FILT_MAC_LENGTHTYPE_REG_ADDRESS 0x862e
+#define PTP_TX_FILT_MAC_LENGTHTYPE_REG_NUM     1
+#define PTP_TX_FILT_MAC_LENGTHTYPE_REG_INC     0x1
+#define PTP_TX_FILT_MAC_LENGTHTYPE_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_MAC_LENGTHTYPE_REG_DEFAULT 0x0
+	/*[field] LENGTH_TYPE*/
+	#define PTP_TX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE
+	#define PTP_TX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE_OFFSET  0
+	#define PTP_TX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE_LEN     16
+	#define PTP_TX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE_DEFAULT 0x0
+
+struct ptp_tx_filt_mac_lengthtype_reg {
+	a_uint32_t  length_type:16;
+};
+
+union ptp_tx_filt_mac_lengthtype_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_mac_lengthtype_reg bf;
+};
+
+/*[register] PTP_TX_FILT_LAYER4_PROTOCOL_REG*/
+#define PTP_TX_FILT_LAYER4_PROTOCOL_REG
+#define PTP_TX_FILT_LAYER4_PROTOCOL_REG_ADDRESS 0x862f
+#define PTP_TX_FILT_LAYER4_PROTOCOL_REG_NUM     1
+#define PTP_TX_FILT_LAYER4_PROTOCOL_REG_INC     0x1
+#define PTP_TX_FILT_LAYER4_PROTOCOL_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_LAYER4_PROTOCOL_REG_DEFAULT 0x0
+	/*[field] L4_PROTOCOL*/
+	#define PTP_TX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL
+	#define PTP_TX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL_OFFSET  0
+	#define PTP_TX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL_LEN     16
+	#define PTP_TX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL_DEFAULT 0x0
+
+struct ptp_tx_filt_layer4_protocol_reg {
+	a_uint32_t  l4_protocol:16;
+};
+
+union ptp_tx_filt_layer4_protocol_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_layer4_protocol_reg bf;
+};
+
+/*[register] PTP_TX_FILT_UDP_PORT_REG*/
+#define PTP_TX_FILT_UDP_PORT_REG
+#define PTP_TX_FILT_UDP_PORT_REG_ADDRESS 0x8630
+#define PTP_TX_FILT_UDP_PORT_REG_NUM     1
+#define PTP_TX_FILT_UDP_PORT_REG_INC     0x1
+#define PTP_TX_FILT_UDP_PORT_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_FILT_UDP_PORT_REG_DEFAULT 0x0
+	/*[field] UDP_PORT*/
+	#define PTP_TX_FILT_UDP_PORT_REG_UDP_PORT
+	#define PTP_TX_FILT_UDP_PORT_REG_UDP_PORT_OFFSET  0
+	#define PTP_TX_FILT_UDP_PORT_REG_UDP_PORT_LEN     16
+	#define PTP_TX_FILT_UDP_PORT_REG_UDP_PORT_DEFAULT 0x0
+
+struct ptp_tx_filt_udp_port_reg {
+	a_uint32_t  udp_port:16;
+};
+
+union ptp_tx_filt_udp_port_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_filt_udp_port_reg bf;
+};
+
+/*[register] PTP_TX_COM_TS_STATUS_REG*/
+#define PTP_TX_COM_TS_STATUS_REG
+#define PTP_TX_COM_TS_STATUS_REG_ADDRESS 0x8631
+#define PTP_TX_COM_TS_STATUS_REG_NUM     1
+#define PTP_TX_COM_TS_STATUS_REG_INC     0x1
+#define PTP_TX_COM_TS_STATUS_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_COM_TS_STATUS_REG_DEFAULT 0x0
+	/*[field] MAC_LENGTHTYPE*/
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_LENGTHTYPE
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_LENGTHTYPE_OFFSET  0
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_LENGTHTYPE_LEN     1
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_LENGTHTYPE_DEFAULT 0x0
+	/*[field] MAC_DA*/
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_DA
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_DA_OFFSET  1
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_DA_LEN     1
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_DA_DEFAULT 0x0
+	/*[field] MAC_PTP_PRIM_ADDR*/
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_OFFSET  2
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_LEN     1
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_DEFAULT 0x0
+	/*[field] MAC_PTP_PDELAY_ADDR*/
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_OFFSET  3
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_LEN     1
+	#define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_DEFAULT 0x0
+	/*[field] IPV4_LAYER4_PROTOCOL*/
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_OFFSET  4
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_LEN     1
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_DEFAULT 0x0
+	/*[field] IPV4_DA*/
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_DA
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_DA_OFFSET  5
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_DA_LEN     1
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_DA_DEFAULT 0x0
+	/*[field] IPV4_PTP_PRIM_ADDR*/
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_OFFSET  6
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_LEN     1
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_DEFAULT 0x0
+	/*[field] IPV4_PTP_PDELAY_ADDR*/
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_OFFSET  7
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_LEN     1
+	#define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_DEFAULT 0x0
+	/*[field] IPV6_NEXT_HEADER*/
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_OFFSET  8
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_LEN     1
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_DEFAULT 0x0
+	/*[field] IPV6_DA*/
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_DA
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_DA_OFFSET  9
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_DA_LEN     1
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_DA_DEFAULT 0x0
+	/*[field] IPV6_PTP_PRIM_ADDR*/
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_OFFSET  10
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_LEN     1
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_DEFAULT 0x0
+	/*[field] IPV6_PTP_PDELAY_ADDR*/
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_OFFSET  11
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_LEN     1
+	#define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_DEFAULT 0x0
+	/*[field] UDP_DPORT*/
+	#define PTP_TX_COM_TS_STATUS_REG_UDP_DPORT
+	#define PTP_TX_COM_TS_STATUS_REG_UDP_DPORT_OFFSET  12
+	#define PTP_TX_COM_TS_STATUS_REG_UDP_DPORT_LEN     1
+	#define PTP_TX_COM_TS_STATUS_REG_UDP_DPORT_DEFAULT 0x0
+	/*[field] UDP_PTP_EVENT_DPORT*/
+	#define PTP_TX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT
+	#define PTP_TX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_OFFSET  13
+	#define PTP_TX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_LEN     1
+	#define PTP_TX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_DEFAULT 0x0
+	/*[field] Y1731_MACH*/
+	#define PTP_TX_COM_TS_STATUS_REG_Y1731_MACH
+	#define PTP_TX_COM_TS_STATUS_REG_Y1731_MACH_OFFSET  14
+	#define PTP_TX_COM_TS_STATUS_REG_Y1731_MACH_LEN     1
+	#define PTP_TX_COM_TS_STATUS_REG_Y1731_MACH_DEFAULT 0x0
+
+struct ptp_tx_com_ts_status_reg {
+	a_uint32_t  mac_lengthtype:1;
+	a_uint32_t  mac_da:1;
+	a_uint32_t  mac_ptp_prim_addr:1;
+	a_uint32_t  mac_ptp_pdelay_addr:1;
+	a_uint32_t  ipv4_layer4_protocol:1;
+	a_uint32_t  ipv4_da:1;
+	a_uint32_t  ipv4_ptp_prim_addr:1;
+	a_uint32_t  ipv4_ptp_pdelay_addr:1;
+	a_uint32_t  ipv6_next_header:1;
+	a_uint32_t  ipv6_da:1;
+	a_uint32_t  ipv6_ptp_prim_addr:1;
+	a_uint32_t  ipv6_ptp_pdelay_addr:1;
+	a_uint32_t  udp_dport:1;
+	a_uint32_t  udp_ptp_event_dport:1;
+	a_uint32_t  y1731_mach:1;
+};
+
+union ptp_tx_com_ts_status_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_com_ts_status_reg bf;
+};
+
+/*[register] PTP_TX_COM_TIMESTAMP0_REG*/
+#define PTP_TX_COM_TIMESTAMP0_REG
+#define PTP_TX_COM_TIMESTAMP0_REG_ADDRESS 0x8632
+#define PTP_TX_COM_TIMESTAMP0_REG_NUM     1
+#define PTP_TX_COM_TIMESTAMP0_REG_INC     0x1
+#define PTP_TX_COM_TIMESTAMP0_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_COM_TIMESTAMP0_REG_DEFAULT 0x0
+	/*[field] COM_TS*/
+	#define PTP_TX_COM_TIMESTAMP0_REG_COM_TS
+	#define PTP_TX_COM_TIMESTAMP0_REG_COM_TS_OFFSET  0
+	#define PTP_TX_COM_TIMESTAMP0_REG_COM_TS_LEN     16
+	#define PTP_TX_COM_TIMESTAMP0_REG_COM_TS_DEFAULT 0x0
+
+struct ptp_tx_com_timestamp0_reg {
+	a_uint32_t  com_ts:16;
+};
+
+union ptp_tx_com_timestamp0_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_com_timestamp0_reg bf;
+};
+
+/*[register] PTP_TX_COM_TIMESTAMP1_REG*/
+#define PTP_TX_COM_TIMESTAMP1_REG
+#define PTP_TX_COM_TIMESTAMP1_REG_ADDRESS 0x8633
+#define PTP_TX_COM_TIMESTAMP1_REG_NUM     1
+#define PTP_TX_COM_TIMESTAMP1_REG_INC     0x1
+#define PTP_TX_COM_TIMESTAMP1_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_COM_TIMESTAMP1_REG_DEFAULT 0x0
+	/*[field] COM_TS*/
+	#define PTP_TX_COM_TIMESTAMP1_REG_COM_TS
+	#define PTP_TX_COM_TIMESTAMP1_REG_COM_TS_OFFSET  0
+	#define PTP_TX_COM_TIMESTAMP1_REG_COM_TS_LEN     16
+	#define PTP_TX_COM_TIMESTAMP1_REG_COM_TS_DEFAULT 0x0
+
+struct ptp_tx_com_timestamp1_reg {
+	a_uint32_t  com_ts:16;
+};
+
+union ptp_tx_com_timestamp1_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_com_timestamp1_reg bf;
+};
+
+/*[register] PTP_TX_COM_TIMESTAMP2_REG*/
+#define PTP_TX_COM_TIMESTAMP2_REG
+#define PTP_TX_COM_TIMESTAMP2_REG_ADDRESS 0x8634
+#define PTP_TX_COM_TIMESTAMP2_REG_NUM     1
+#define PTP_TX_COM_TIMESTAMP2_REG_INC     0x1
+#define PTP_TX_COM_TIMESTAMP2_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_COM_TIMESTAMP2_REG_DEFAULT 0x0
+	/*[field] COM_TS*/
+	#define PTP_TX_COM_TIMESTAMP2_REG_COM_TS
+	#define PTP_TX_COM_TIMESTAMP2_REG_COM_TS_OFFSET  0
+	#define PTP_TX_COM_TIMESTAMP2_REG_COM_TS_LEN     16
+	#define PTP_TX_COM_TIMESTAMP2_REG_COM_TS_DEFAULT 0x0
+
+struct ptp_tx_com_timestamp2_reg {
+	a_uint32_t  com_ts:16;
+};
+
+union ptp_tx_com_timestamp2_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_com_timestamp2_reg bf;
+};
+
+/*[register] PTP_TX_COM_TIMESTAMP3_REG*/
+#define PTP_TX_COM_TIMESTAMP3_REG
+#define PTP_TX_COM_TIMESTAMP3_REG_ADDRESS 0x8635
+#define PTP_TX_COM_TIMESTAMP3_REG_NUM     1
+#define PTP_TX_COM_TIMESTAMP3_REG_INC     0x1
+#define PTP_TX_COM_TIMESTAMP3_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_COM_TIMESTAMP3_REG_DEFAULT 0x0
+	/*[field] COM_TS*/
+	#define PTP_TX_COM_TIMESTAMP3_REG_COM_TS
+	#define PTP_TX_COM_TIMESTAMP3_REG_COM_TS_OFFSET  0
+	#define PTP_TX_COM_TIMESTAMP3_REG_COM_TS_LEN     16
+	#define PTP_TX_COM_TIMESTAMP3_REG_COM_TS_DEFAULT 0x0
+
+struct ptp_tx_com_timestamp3_reg {
+	a_uint32_t  com_ts:16;
+};
+
+union ptp_tx_com_timestamp3_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_com_timestamp3_reg bf;
+};
+
+/*[register] PTP_TX_COM_TIMESTAMP4_REG*/
+#define PTP_TX_COM_TIMESTAMP4_REG
+#define PTP_TX_COM_TIMESTAMP4_REG_ADDRESS 0x8636
+#define PTP_TX_COM_TIMESTAMP4_REG_NUM     1
+#define PTP_TX_COM_TIMESTAMP4_REG_INC     0x1
+#define PTP_TX_COM_TIMESTAMP4_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_COM_TIMESTAMP4_REG_DEFAULT 0x0
+	/*[field] COM_TS*/
+	#define PTP_TX_COM_TIMESTAMP4_REG_COM_TS
+	#define PTP_TX_COM_TIMESTAMP4_REG_COM_TS_OFFSET  0
+	#define PTP_TX_COM_TIMESTAMP4_REG_COM_TS_LEN     16
+	#define PTP_TX_COM_TIMESTAMP4_REG_COM_TS_DEFAULT 0x0
+
+struct ptp_tx_com_timestamp4_reg {
+	a_uint32_t  com_ts:16;
+};
+
+union ptp_tx_com_timestamp4_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_com_timestamp4_reg bf;
+};
+
+/*[register] PTP_TX_COM_FRAC_NANO_REG*/
+#define PTP_TX_COM_FRAC_NANO_REG
+#define PTP_TX_COM_FRAC_NANO_REG_ADDRESS 0x8637
+#define PTP_TX_COM_FRAC_NANO_REG_NUM     1
+#define PTP_TX_COM_FRAC_NANO_REG_INC     0x1
+#define PTP_TX_COM_FRAC_NANO_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_COM_FRAC_NANO_REG_DEFAULT 0x0
+	/*[field] FRAC_NANO*/
+	#define PTP_TX_COM_FRAC_NANO_REG_FRAC_NANO
+	#define PTP_TX_COM_FRAC_NANO_REG_FRAC_NANO_OFFSET  0
+	#define PTP_TX_COM_FRAC_NANO_REG_FRAC_NANO_LEN     16
+	#define PTP_TX_COM_FRAC_NANO_REG_FRAC_NANO_DEFAULT 0x0
+
+struct ptp_tx_com_frac_nano_reg {
+	a_uint32_t  frac_nano:16;
+};
+
+union ptp_tx_com_frac_nano_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_com_frac_nano_reg bf;
+};
+
+/*[register] PTP_TX_Y1731_IDENTIFY_REG*/
+#define PTP_TX_Y1731_IDENTIFY_REG
+#define PTP_TX_Y1731_IDENTIFY_REG_ADDRESS 0x863e
+#define PTP_TX_Y1731_IDENTIFY_REG_NUM     1
+#define PTP_TX_Y1731_IDENTIFY_REG_INC     0x1
+#define PTP_TX_Y1731_IDENTIFY_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_Y1731_IDENTIFY_REG_DEFAULT 0x0
+	/*[field] IDENTIFY*/
+	#define PTP_TX_Y1731_IDENTIFY_REG_IDENTIFY
+	#define PTP_TX_Y1731_IDENTIFY_REG_IDENTIFY_OFFSET  0
+	#define PTP_TX_Y1731_IDENTIFY_REG_IDENTIFY_LEN     16
+	#define PTP_TX_Y1731_IDENTIFY_REG_IDENTIFY_DEFAULT 0x0
+
+struct ptp_tx_y1731_identify_reg {
+	a_uint32_t  identify:16;
+};
+
+union ptp_tx_y1731_identify_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_y1731_identify_reg bf;
+};
+
+/*[register] PTP_Y1731_DM_CONTROL_REG*/
+#define PTP_Y1731_DM_CONTROL_REG
+#define PTP_Y1731_DM_CONTROL_REG_ADDRESS 0x8640
+#define PTP_Y1731_DM_CONTROL_REG_NUM     1
+#define PTP_Y1731_DM_CONTROL_REG_INC     0x1
+#define PTP_Y1731_DM_CONTROL_REG_TYPE    REG_TYPE_RW
+#define PTP_Y1731_DM_CONTROL_REG_DEFAULT 0x0
+	/*[field] VALID_MSG_LEV_BMP*/
+	#define PTP_Y1731_DM_CONTROL_REG_VALID_MSG_LEV_BMP
+	#define PTP_Y1731_DM_CONTROL_REG_VALID_MSG_LEV_BMP_OFFSET  0
+	#define PTP_Y1731_DM_CONTROL_REG_VALID_MSG_LEV_BMP_LEN     8
+	#define PTP_Y1731_DM_CONTROL_REG_VALID_MSG_LEV_BMP_DEFAULT 0x0
+	/*[field] Y1731_DMM_LPBK_EN*/
+	#define PTP_Y1731_DM_CONTROL_REG_Y1731_DMM_LPBK_EN
+	#define PTP_Y1731_DM_CONTROL_REG_Y1731_DMM_LPBK_EN_OFFSET  8
+	#define PTP_Y1731_DM_CONTROL_REG_Y1731_DMM_LPBK_EN_LEN     1
+	#define PTP_Y1731_DM_CONTROL_REG_Y1731_DMM_LPBK_EN_DEFAULT 0x0
+
+struct ptp_y1731_dm_control_reg {
+	a_uint32_t  valid_msg_lev_bmp:8;
+	a_uint32_t  y1731_dmm_lpbk_en:1;
+};
+
+union ptp_y1731_dm_control_reg_u {
+	a_uint32_t val;
+	struct ptp_y1731_dm_control_reg bf;
+};
+
+/*[register] PTP_RX_COM_TS_STATUS_PRE_REG*/
+#define PTP_RX_COM_TS_STATUS_PRE_REG
+#define PTP_RX_COM_TS_STATUS_PRE_REG_ADDRESS 0x8641
+#define PTP_RX_COM_TS_STATUS_PRE_REG_NUM     1
+#define PTP_RX_COM_TS_STATUS_PRE_REG_INC     0x1
+#define PTP_RX_COM_TS_STATUS_PRE_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_COM_TS_STATUS_PRE_REG_DEFAULT 0x0
+	/*[field] TS_STATUS*/
+	#define PTP_RX_COM_TS_STATUS_PRE_REG_TS_STATUS
+	#define PTP_RX_COM_TS_STATUS_PRE_REG_TS_STATUS_OFFSET  0
+	#define PTP_RX_COM_TS_STATUS_PRE_REG_TS_STATUS_LEN     15
+	#define PTP_RX_COM_TS_STATUS_PRE_REG_TS_STATUS_DEFAULT 0x0
+
+struct ptp_rx_com_ts_status_pre_reg {
+	a_uint32_t  mac_lengthtype:1;
+	a_uint32_t  mac_da:1;
+	a_uint32_t  mac_ptp_prim_addr:1;
+	a_uint32_t  mac_ptp_pdelay_addr:1;
+	a_uint32_t  ipv4_layer4_protocol:1;
+	a_uint32_t  ipv4_da:1;
+	a_uint32_t  ipv4_ptp_prim_addr:1;
+	a_uint32_t  ipv4_ptp_pdelay_addr:1;
+	a_uint32_t  ipv6_next_header:1;
+	a_uint32_t  ipv6_da:1;
+	a_uint32_t  ipv6_ptp_prim_addr:1;
+	a_uint32_t  ipv6_ptp_pdelay_addr:1;
+	a_uint32_t  udp_dport:1;
+	a_uint32_t  udp_ptp_event_dport:1;
+	a_uint32_t  y1731_mach:1;
+};
+
+union ptp_rx_com_ts_status_pre_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_com_ts_status_pre_reg bf;
+};
+
+/*[register] PTP_BAUD_CONFIG_REG*/
+#define PTP_BAUD_CONFIG_REG
+#define PTP_BAUD_CONFIG_REG_ADDRESS 0x8700
+#define PTP_BAUD_CONFIG_REG_NUM     1
+#define PTP_BAUD_CONFIG_REG_INC     0x1
+#define PTP_BAUD_CONFIG_REG_TYPE    REG_TYPE_RW
+#define PTP_BAUD_CONFIG_REG_DEFAULT 0x0
+	/*[field] BAUD_RATE*/
+	#define PTP_BAUD_CONFIG_REG_BAUD_RATE
+	#define PTP_BAUD_CONFIG_REG_BAUD_RATE_OFFSET  0
+	#define PTP_BAUD_CONFIG_REG_BAUD_RATE_LEN     16
+	#define PTP_BAUD_CONFIG_REG_BAUD_RATE_DEFAULT 0x0
+
+struct ptp_baud_config_reg {
+	a_uint32_t  baud_rate:16;
+};
+
+union ptp_baud_config_reg_u {
+	a_uint32_t val;
+	struct ptp_baud_config_reg bf;
+};
+
+/*[register] PTP_UART_CONFIGURATION_REG*/
+#define PTP_UART_CONFIGURATION_REG
+#define PTP_UART_CONFIGURATION_REG_ADDRESS 0x8701
+#define PTP_UART_CONFIGURATION_REG_NUM     1
+#define PTP_UART_CONFIGURATION_REG_INC     0x1
+#define PTP_UART_CONFIGURATION_REG_TYPE    REG_TYPE_RW
+#define PTP_UART_CONFIGURATION_REG_DEFAULT 0x0
+	/*[field] START_POLARITY*/
+	#define PTP_UART_CONFIGURATION_REG_START_POLARITY
+	#define PTP_UART_CONFIGURATION_REG_START_POLARITY_OFFSET  0
+	#define PTP_UART_CONFIGURATION_REG_START_POLARITY_LEN     1
+	#define PTP_UART_CONFIGURATION_REG_START_POLARITY_DEFAULT 0x0
+	/*[field] MSB_FIRST*/
+	#define PTP_UART_CONFIGURATION_REG_MSB_FIRST
+	#define PTP_UART_CONFIGURATION_REG_MSB_FIRST_OFFSET  1
+	#define PTP_UART_CONFIGURATION_REG_MSB_FIRST_LEN     1
+	#define PTP_UART_CONFIGURATION_REG_MSB_FIRST_DEFAULT 0x0
+	/*[field] PARITY_EN*/
+	#define PTP_UART_CONFIGURATION_REG_PARITY_EN
+	#define PTP_UART_CONFIGURATION_REG_PARITY_EN_OFFSET  2
+	#define PTP_UART_CONFIGURATION_REG_PARITY_EN_LEN     1
+	#define PTP_UART_CONFIGURATION_REG_PARITY_EN_DEFAULT 0x0
+	/*[field] AUTO_TOD_OUT_EN*/
+	#define PTP_UART_CONFIGURATION_REG_AUTO_TOD_OUT_EN
+	#define PTP_UART_CONFIGURATION_REG_AUTO_TOD_OUT_EN_OFFSET  3
+	#define PTP_UART_CONFIGURATION_REG_AUTO_TOD_OUT_EN_LEN     1
+	#define PTP_UART_CONFIGURATION_REG_AUTO_TOD_OUT_EN_DEFAULT 0x0
+	/*[field] AUTO_TOD_IN_EN*/
+	#define PTP_UART_CONFIGURATION_REG_AUTO_TOD_IN_EN
+	#define PTP_UART_CONFIGURATION_REG_AUTO_TOD_IN_EN_OFFSET  4
+	#define PTP_UART_CONFIGURATION_REG_AUTO_TOD_IN_EN_LEN     1
+	#define PTP_UART_CONFIGURATION_REG_AUTO_TOD_IN_EN_DEFAULT 0x0
+
+struct ptp_uart_configuration_reg {
+	a_uint32_t  start_polarity:1;
+	a_uint32_t  msb_first:1;
+	a_uint32_t  parity_en:1;
+	a_uint32_t  auto_tod_out_en:1;
+	a_uint32_t  auto_tod_in_en:1;
+};
+
+union ptp_uart_configuration_reg_u {
+	a_uint32_t val;
+	struct ptp_uart_configuration_reg bf;
+};
+
+/*[register] PTP_RESET_BUFFER_REG*/
+#define PTP_RESET_BUFFER_REG
+#define PTP_RESET_BUFFER_REG_ADDRESS 0x8702
+#define PTP_RESET_BUFFER_REG_NUM     1
+#define PTP_RESET_BUFFER_REG_INC     0x1
+#define PTP_RESET_BUFFER_REG_TYPE    REG_TYPE_RW
+#define PTP_RESET_BUFFER_REG_DEFAULT 0x0
+	/*[field] RESET*/
+	#define PTP_RESET_BUFFER_REG_RESET
+	#define PTP_RESET_BUFFER_REG_RESET_OFFSET  0
+	#define PTP_RESET_BUFFER_REG_RESET_LEN     1
+	#define PTP_RESET_BUFFER_REG_RESET_DEFAULT 0x0
+
+struct ptp_reset_buffer_reg {
+	a_uint32_t  reset:1;
+};
+
+union ptp_reset_buffer_reg_u {
+	a_uint32_t val;
+	struct ptp_reset_buffer_reg bf;
+};
+
+/*[register] PTP_BUFFER_STATUS_REG*/
+#define PTP_BUFFER_STATUS_REG
+#define PTP_BUFFER_STATUS_REG_ADDRESS 0x8703
+#define PTP_BUFFER_STATUS_REG_NUM     1
+#define PTP_BUFFER_STATUS_REG_INC     0x1
+#define PTP_BUFFER_STATUS_REG_TYPE    REG_TYPE_RW
+#define PTP_BUFFER_STATUS_REG_DEFAULT 0x0
+	/*[field] TX_BUFFER_ALMOST_EMPTY*/
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_EMPTY
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_EMPTY_OFFSET  0
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_EMPTY_LEN     1
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_EMPTY_DEFAULT 0x0
+	/*[field] TX_BUFFER_ALMOST_FULL*/
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_FULL
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_FULL_OFFSET  1
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_FULL_LEN     1
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_FULL_DEFAULT 0x0
+	/*[field] TX_BUFFER_HALF_FULL*/
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_HALF_FULL
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_HALF_FULL_OFFSET  2
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_HALF_FULL_LEN     1
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_HALF_FULL_DEFAULT 0x0
+	/*[field] TX_BUFFER_FULL*/
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_FULL
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_FULL_OFFSET  3
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_FULL_LEN     1
+	#define PTP_BUFFER_STATUS_REG_TX_BUFFER_FULL_DEFAULT 0x0
+	/*[field] RX_BUFFER_ALMOST_EMPTY*/
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_EMPTY
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_EMPTY_OFFSET  4
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_EMPTY_LEN     1
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_EMPTY_DEFAULT 0x0
+	/*[field] RX_BUFFER_ALMOST_FULL*/
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_FULL
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_FULL_OFFSET  5
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_FULL_LEN     1
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_FULL_DEFAULT 0x0
+	/*[field] RX_BUFFER_HALF_FULL*/
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_HALF_FULL
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_HALF_FULL_OFFSET  6
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_HALF_FULL_LEN     1
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_HALF_FULL_DEFAULT 0x0
+	/*[field] RX_BUFFER_FULL*/
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_FULL
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_FULL_OFFSET  7
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_FULL_LEN     1
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_FULL_DEFAULT 0x0
+	/*[field] RX_BUFFER_DATA_PRESENT*/
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_DATA_PRESENT
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_DATA_PRESENT_OFFSET  8
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_DATA_PRESENT_LEN     1
+	#define PTP_BUFFER_STATUS_REG_RX_BUFFER_DATA_PRESENT_DEFAULT 0x0
+
+struct ptp_buffer_status_reg {
+	a_uint32_t  tx_buffer_almost_empty:1;
+	a_uint32_t  tx_buffer_almost_full:1;
+	a_uint32_t  tx_buffer_half_full:1;
+	a_uint32_t  tx_buffer_full:1;
+	a_uint32_t  rx_buffer_almost_empty:1;
+	a_uint32_t  rx_buffer_almost_full:1;
+	a_uint32_t  rx_buffer_half_full:1;
+	a_uint32_t  rx_buffer_full:1;
+	a_uint32_t  rx_buffer_data_present:1;
+};
+
+union ptp_buffer_status_reg_u {
+	a_uint32_t val;
+	struct ptp_buffer_status_reg bf;
+};
+
+/*[register] PTP_TX_BUFFER_WRITE_REG*/
+#define PTP_TX_BUFFER_WRITE_REG
+#define PTP_TX_BUFFER_WRITE_REG_ADDRESS 0x8704
+#define PTP_TX_BUFFER_WRITE_REG_NUM     1
+#define PTP_TX_BUFFER_WRITE_REG_INC     0x1
+#define PTP_TX_BUFFER_WRITE_REG_TYPE    REG_TYPE_RW
+#define PTP_TX_BUFFER_WRITE_REG_DEFAULT 0x0
+	/*[field] TX_BUFFER*/
+	#define PTP_TX_BUFFER_WRITE_REG_TX_BUFFER
+	#define PTP_TX_BUFFER_WRITE_REG_TX_BUFFER_OFFSET  0
+	#define PTP_TX_BUFFER_WRITE_REG_TX_BUFFER_LEN     8
+	#define PTP_TX_BUFFER_WRITE_REG_TX_BUFFER_DEFAULT 0x0
+
+struct ptp_tx_buffer_write_reg {
+	a_uint32_t  tx_buffer:8;
+};
+
+union ptp_tx_buffer_write_reg_u {
+	a_uint32_t val;
+	struct ptp_tx_buffer_write_reg bf;
+};
+
+/*[register] PTP_RX_BUFFER_READ_REG*/
+#define PTP_RX_BUFFER_READ_REG
+#define PTP_RX_BUFFER_READ_REG_ADDRESS 0x8705
+#define PTP_RX_BUFFER_READ_REG_NUM     1
+#define PTP_RX_BUFFER_READ_REG_INC     0x1
+#define PTP_RX_BUFFER_READ_REG_TYPE    REG_TYPE_RW
+#define PTP_RX_BUFFER_READ_REG_DEFAULT 0x0
+	/*[field] RX_DATA*/
+	#define PTP_RX_BUFFER_READ_REG_RX_DATA
+	#define PTP_RX_BUFFER_READ_REG_RX_DATA_OFFSET  0
+	#define PTP_RX_BUFFER_READ_REG_RX_DATA_LEN     8
+	#define PTP_RX_BUFFER_READ_REG_RX_DATA_DEFAULT 0x0
+	/*[field] RX_BUFFER_ALMOST_EMPTY*/
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_EMPTY
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_EMPTY_OFFSET  8
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_EMPTY_LEN     1
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_EMPTY_DEFAULT 0x0
+	/*[field] RX_BUFFER_ALMOST_FULL*/
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_FULL
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_FULL_OFFSET  9
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_FULL_LEN     1
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_FULL_DEFAULT 0x0
+	/*[field] RX_BUFFER_HALF_FULL*/
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_HALF_FULL
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_HALF_FULL_OFFSET  10
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_HALF_FULL_LEN     1
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_HALF_FULL_DEFAULT 0x0
+	/*[field] RX_BUFFER_FULL*/
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_FULL
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_FULL_OFFSET  11
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_FULL_LEN     1
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_FULL_DEFAULT 0x0
+	/*[field] RX_BUFFER_DATA_PRESENT*/
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_DATA_PRESENT
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_DATA_PRESENT_OFFSET  12
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_DATA_PRESENT_LEN     1
+	#define PTP_RX_BUFFER_READ_REG_RX_BUFFER_DATA_PRESENT_DEFAULT 0x0
+
+struct ptp_rx_buffer_read_reg {
+	a_uint32_t  rx_data:8;
+	a_uint32_t  rx_buffer_almost_empty:1;
+	a_uint32_t  rx_buffer_almost_full:1;
+	a_uint32_t  rx_buffer_half_full:1;
+	a_uint32_t  rx_buffer_full:1;
+	a_uint32_t  rx_buffer_data_present:1;
+};
+
+union ptp_rx_buffer_read_reg_u {
+	a_uint32_t val;
+	struct ptp_rx_buffer_read_reg bf;
+};
+
+/*[register] PTP_LOC_MAC_ADDR_0_REG*/
+#define PTP_LOC_MAC_ADDR_0_REG
+#define PTP_LOC_MAC_ADDR_0_REG_ADDRESS 0x804a
+#define PTP_LOC_MAC_ADDR_0_REG_NUM     1
+#define PTP_LOC_MAC_ADDR_0_REG_INC     0x1
+#define PTP_LOC_MAC_ADDR_0_REG_TYPE    REG_TYPE_RW
+#define PTP_LOC_MAC_ADDR_0_REG_DEFAULT 0x0
+	/*[field] MAC_ADDR*/
+	#define PTP_LOC_MAC_ADDR_0_REG_MAC_ADDR
+	#define PTP_LOC_MAC_ADDR_0_REG_MAC_ADDR_OFFSET  0
+	#define PTP_LOC_MAC_ADDR_0_REG_MAC_ADDR_LEN     16
+	#define PTP_LOC_MAC_ADDR_0_REG_MAC_ADDR_DEFAULT 0x0
+
+struct ptp_loc_mac_addr_0_reg {
+	a_uint32_t  mac_addr:16;
+};
+
+union ptp_loc_mac_addr_0_reg_u {
+	a_uint32_t val;
+	struct ptp_loc_mac_addr_0_reg bf;
+};
+
+/*[register] PTP_LOC_MAC_ADDR_1_REG*/
+#define PTP_LOC_MAC_ADDR_1_REG
+#define PTP_LOC_MAC_ADDR_1_REG_ADDRESS 0x804b
+#define PTP_LOC_MAC_ADDR_1_REG_NUM     1
+#define PTP_LOC_MAC_ADDR_1_REG_INC     0x1
+#define PTP_LOC_MAC_ADDR_1_REG_TYPE    REG_TYPE_RW
+#define PTP_LOC_MAC_ADDR_1_REG_DEFAULT 0x0
+	/*[field] MAC_ADDR*/
+	#define PTP_LOC_MAC_ADDR_1_REG_MAC_ADDR
+	#define PTP_LOC_MAC_ADDR_1_REG_MAC_ADDR_OFFSET  0
+	#define PTP_LOC_MAC_ADDR_1_REG_MAC_ADDR_LEN     16
+	#define PTP_LOC_MAC_ADDR_1_REG_MAC_ADDR_DEFAULT 0x0
+
+struct ptp_loc_mac_addr_1_reg {
+	a_uint32_t  mac_addr:16;
+};
+
+union ptp_loc_mac_addr_1_reg_u {
+	a_uint32_t val;
+	struct ptp_loc_mac_addr_1_reg bf;
+};
+
+/*[register] PTP_LOC_MAC_ADDR_2_REG*/
+#define PTP_LOC_MAC_ADDR_2_REG
+#define PTP_LOC_MAC_ADDR_2_REG_ADDRESS 0x804c
+#define PTP_LOC_MAC_ADDR_2_REG_NUM     1
+#define PTP_LOC_MAC_ADDR_2_REG_INC     0x1
+#define PTP_LOC_MAC_ADDR_2_REG_TYPE    REG_TYPE_RW
+#define PTP_LOC_MAC_ADDR_2_REG_DEFAULT 0x0
+	/*[field] MAC_ADDR*/
+	#define PTP_LOC_MAC_ADDR_2_REG_MAC_ADDR
+	#define PTP_LOC_MAC_ADDR_2_REG_MAC_ADDR_OFFSET  0
+	#define PTP_LOC_MAC_ADDR_2_REG_MAC_ADDR_LEN     16
+	#define PTP_LOC_MAC_ADDR_2_REG_MAC_ADDR_DEFAULT 0x0
+
+struct ptp_loc_mac_addr_2_reg {
+	a_uint32_t  mac_addr:16;
+};
+
+union ptp_loc_mac_addr_2_reg_u {
+	a_uint32_t val;
+	struct ptp_loc_mac_addr_2_reg bf;
+};
+
+/*[register] PTP_LINK_DELAY_0_REG*/
+#define PTP_LINK_DELAY_0_REG
+#define PTP_LINK_DELAY_0_REG_ADDRESS 0x80f3
+#define PTP_LINK_DELAY_0_REG_NUM     1
+#define PTP_LINK_DELAY_0_REG_INC     0x1
+#define PTP_LINK_DELAY_0_REG_TYPE    REG_TYPE_RW
+#define PTP_LINK_DELAY_0_REG_DEFAULT 0x0
+	/*[field] LINK_DELAY*/
+	#define PTP_LINK_DELAY_0_REG_LINK_DELAY
+	#define PTP_LINK_DELAY_0_REG_LINK_DELAY_OFFSET  0
+	#define PTP_LINK_DELAY_0_REG_LINK_DELAY_LEN     16
+	#define PTP_LINK_DELAY_0_REG_LINK_DELAY_DEFAULT 0x0
+
+struct ptp_link_delay_0_reg {
+	a_uint32_t  link_delay:16;
+};
+
+union ptp_link_delay_0_reg_u {
+	a_uint32_t val;
+	struct ptp_link_delay_0_reg bf;
+};
+
+/*[register] PTP_LINK_DELAY_1_REG*/
+#define PTP_LINK_DELAY_1_REG
+#define PTP_LINK_DELAY_1_REG_ADDRESS 0x80f4
+#define PTP_LINK_DELAY_1_REG_NUM     1
+#define PTP_LINK_DELAY_1_REG_INC     0x1
+#define PTP_LINK_DELAY_1_REG_TYPE    REG_TYPE_RW
+#define PTP_LINK_DELAY_1_REG_DEFAULT 0x0
+	/*[field] LINK_DELAY*/
+	#define PTP_LINK_DELAY_1_REG_LINK_DELAY
+	#define PTP_LINK_DELAY_1_REG_LINK_DELAY_OFFSET  0
+	#define PTP_LINK_DELAY_1_REG_LINK_DELAY_LEN     16
+	#define PTP_LINK_DELAY_1_REG_LINK_DELAY_DEFAULT 0x0
+
+struct ptp_link_delay_1_reg {
+	a_uint32_t  link_delay:16;
+};
+
+union ptp_link_delay_1_reg_u {
+	a_uint32_t val;
+	struct ptp_link_delay_1_reg bf;
+};
+
+/*[register] PTP_MISC_CONTROL_REG*/
+#define PTP_MISC_CONTROL_REG
+#define PTP_MISC_CONTROL_REG_ADDRESS 0x80f5
+#define PTP_MISC_CONTROL_REG_NUM     1
+#define PTP_MISC_CONTROL_REG_INC     0x1
+#define PTP_MISC_CONTROL_REG_TYPE    REG_TYPE_RW
+#define PTP_MISC_CONTROL_REG_DEFAULT 0x0
+	/*[field] EG_ASYM_EN*/
+	#define PTP_MISC_CONTROL_REG_EG_ASYM_EN
+	#define PTP_MISC_CONTROL_REG_EG_ASYM_EN_OFFSET  0
+	#define PTP_MISC_CONTROL_REG_EG_ASYM_EN_LEN     1
+	#define PTP_MISC_CONTROL_REG_EG_ASYM_EN_DEFAULT 0x0
+	/*[field] IN_ASYM_EN*/
+	#define PTP_MISC_CONTROL_REG_IN_ASYM_EN
+	#define PTP_MISC_CONTROL_REG_IN_ASYM_EN_OFFSET  1
+	#define PTP_MISC_CONTROL_REG_IN_ASYM_EN_LEN     1
+	#define PTP_MISC_CONTROL_REG_IN_ASYM_EN_DEFAULT 0x0
+
+struct ptp_misc_control_reg {
+	a_uint32_t  eg_asym_en:1;
+	a_uint32_t  in_asym_en:1;
+};
+
+union ptp_misc_control_reg_u {
+	a_uint32_t val;
+	struct ptp_misc_control_reg bf;
+};
+
+/*[register] PTP_INGRESS_ASYMMETRY_0_REG*/
+#define PTP_INGRESS_ASYMMETRY_0_REG
+#define PTP_INGRESS_ASYMMETRY_0_REG_ADDRESS 0x80f6
+#define PTP_INGRESS_ASYMMETRY_0_REG_NUM     1
+#define PTP_INGRESS_ASYMMETRY_0_REG_INC     0x1
+#define PTP_INGRESS_ASYMMETRY_0_REG_TYPE    REG_TYPE_RW
+#define PTP_INGRESS_ASYMMETRY_0_REG_DEFAULT 0x0
+	/*[field] IN_ASYM*/
+	#define PTP_INGRESS_ASYMMETRY_0_REG_IN_ASYM
+	#define PTP_INGRESS_ASYMMETRY_0_REG_IN_ASYM_OFFSET  0
+	#define PTP_INGRESS_ASYMMETRY_0_REG_IN_ASYM_LEN     16
+	#define PTP_INGRESS_ASYMMETRY_0_REG_IN_ASYM_DEFAULT 0x0
+
+struct ptp_ingress_asymmetry_0_reg {
+	a_uint32_t  in_asym:16;
+};
+
+union ptp_ingress_asymmetry_0_reg_u {
+	a_uint32_t val;
+	struct ptp_ingress_asymmetry_0_reg bf;
+};
+
+/*[register] PTP_INGRESS_ASYMMETRY_1_REG*/
+#define PTP_INGRESS_ASYMMETRY_1_REG
+#define PTP_INGRESS_ASYMMETRY_1_REG_ADDRESS 0x80f7
+#define PTP_INGRESS_ASYMMETRY_1_REG_NUM     1
+#define PTP_INGRESS_ASYMMETRY_1_REG_INC     0x1
+#define PTP_INGRESS_ASYMMETRY_1_REG_TYPE    REG_TYPE_RW
+#define PTP_INGRESS_ASYMMETRY_1_REG_DEFAULT 0x0
+	/*[field] IN_ASYM*/
+	#define PTP_INGRESS_ASYMMETRY_1_REG_IN_ASYM
+	#define PTP_INGRESS_ASYMMETRY_1_REG_IN_ASYM_OFFSET  0
+	#define PTP_INGRESS_ASYMMETRY_1_REG_IN_ASYM_LEN     16
+	#define PTP_INGRESS_ASYMMETRY_1_REG_IN_ASYM_DEFAULT 0x0
+
+struct ptp_ingress_asymmetry_1_reg {
+	a_uint32_t  in_asym:16;
+};
+
+union ptp_ingress_asymmetry_1_reg_u {
+	a_uint32_t val;
+	struct ptp_ingress_asymmetry_1_reg bf;
+};
+
+/*[register] PTP_EGRESS_ASYMMETRY_0_REG*/
+#define PTP_EGRESS_ASYMMETRY_0_REG
+#define PTP_EGRESS_ASYMMETRY_0_REG_ADDRESS 0x80f8
+#define PTP_EGRESS_ASYMMETRY_0_REG_NUM     1
+#define PTP_EGRESS_ASYMMETRY_0_REG_INC     0x1
+#define PTP_EGRESS_ASYMMETRY_0_REG_TYPE    REG_TYPE_RW
+#define PTP_EGRESS_ASYMMETRY_0_REG_DEFAULT 0x0
+	/*[field] EG_ASYM*/
+	#define PTP_EGRESS_ASYMMETRY_0_REG_EG_ASYM
+	#define PTP_EGRESS_ASYMMETRY_0_REG_EG_ASYM_OFFSET  0
+	#define PTP_EGRESS_ASYMMETRY_0_REG_EG_ASYM_LEN     16
+	#define PTP_EGRESS_ASYMMETRY_0_REG_EG_ASYM_DEFAULT 0x0
+
+struct ptp_egress_asymmetry_0_reg {
+	a_uint32_t  eg_asym:16;
+};
+
+union ptp_egress_asymmetry_0_reg_u {
+	a_uint32_t val;
+	struct ptp_egress_asymmetry_0_reg bf;
+};
+
+/*[register] PTP_EGRESS_ASYMMETRY_1_REG*/
+#define PTP_EGRESS_ASYMMETRY_1_REG
+#define PTP_EGRESS_ASYMMETRY_1_REG_ADDRESS 0x80f9
+#define PTP_EGRESS_ASYMMETRY_1_REG_NUM     1
+#define PTP_EGRESS_ASYMMETRY_1_REG_INC     0x1
+#define PTP_EGRESS_ASYMMETRY_1_REG_TYPE    REG_TYPE_RW
+#define PTP_EGRESS_ASYMMETRY_1_REG_DEFAULT 0x0
+	/*[field] EG_ASYM*/
+	#define PTP_EGRESS_ASYMMETRY_1_REG_EG_ASYM
+	#define PTP_EGRESS_ASYMMETRY_1_REG_EG_ASYM_OFFSET  0
+	#define PTP_EGRESS_ASYMMETRY_1_REG_EG_ASYM_LEN     16
+	#define PTP_EGRESS_ASYMMETRY_1_REG_EG_ASYM_DEFAULT 0x0
+
+struct ptp_egress_asymmetry_1_reg {
+	a_uint32_t  eg_asym:16;
+};
+
+union ptp_egress_asymmetry_1_reg_u {
+	a_uint32_t val;
+	struct ptp_egress_asymmetry_1_reg bf;
+};
+
+/*[register] PTP_BACKUP_REG*/
+#define PTP_BACKUP_REG
+#define PTP_BACKUP_REG_ADDRESS 0x9036
+#define PTP_BACKUP_REG_NUM     1
+#define PTP_BACKUP_REG_INC     0x1
+#define PTP_BACKUP_REG_TYPE    REG_TYPE_RW
+#define PTP_BACKUP_REG_DEFAULT 0x0
+	/*[field] P2P_TC_EN*/
+	#define PTP_BACKUP_REG_P2P_TC_EN
+	#define PTP_BACKUP_REG_P2P_TC_EN_OFFSET  0
+	#define PTP_BACKUP_REG_P2P_TC_EN_LEN     1
+	#define PTP_BACKUP_REG_P2P_TC_EN_DEFAULT 0x0
+
+struct ptp_backup_reg {
+	a_uint32_t  p2p_tc_en:1;
+};
+
+union ptp_backup_reg_u {
+	a_uint32_t val;
+	struct ptp_backup_reg bf;
+};
+
+#endif
diff --git a/qca-ssdk/include/hsl/phy/sfp_phy.h b/qca-ssdk/include/hsl/phy/sfp_phy.h
new file mode 100755
index 0000000..34df2e1
--- /dev/null
+++ b/qca-ssdk/include/hsl/phy/sfp_phy.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _SFP_PHY_H_
+#define _SFP_PHY_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif				/* __cplusplus */
+
+
+#define SFP_ANEG_DONE          0x20
+#define SFP_E2PROM_ADDR        0x50
+#define SFP_SPEED_ADDR         0xc
+#define SFP_SPEED_1000M        10
+#define SFP_SPEED_2500M        25
+#define SFP_SPEED_5000M        50
+#define SFP_SPEED_10000M       100
+
+#define SFP_TO_SFP_SPEED(reg_data) ((reg_data >> 8) & 0xff)
+
+int sfp_phy_device_setup(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t phy_id);
+void sfp_phy_device_remove(a_uint32_t dev_id, a_uint32_t port);
+
+int sfp_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp);
+void sfp_phy_exit(a_uint32_t dev_id, a_uint32_t port_bmp);
+
+sw_error_t sfp_phy_interface_get_mode_status(a_uint32_t dev_id, a_uint32_t phy_id,
+	fal_port_interface_mode_t *interface_mode);
+
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* _SFP_PHY_H_ */
+
diff --git a/qca-ssdk/include/hsl/scomphy/scomphy_init.h b/qca-ssdk/include/hsl/scomphy/scomphy_init.h
new file mode 100755
index 0000000..decb909
--- /dev/null
+++ b/qca-ssdk/include/hsl/scomphy/scomphy_init.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup scomphy_init SCOMPHY_INIT
+ * @{
+ */
+#ifndef _SCOMPHY_INIT_H_
+#define _SCOMPHY_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "ssdk_init.h"
+
+sw_error_t
+scomphy_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+sw_error_t
+scomphy_cleanup(a_uint32_t dev_id);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SCOMPHY_INIT_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/scomphy/scomphy_port_ctrl.h b/qca-ssdk/include/hsl/scomphy/scomphy_port_ctrl.h
new file mode 100644
index 0000000..399e253
--- /dev/null
+++ b/qca-ssdk/include/hsl/scomphy/scomphy_port_ctrl.h
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*qca808x_start*/
+#ifndef _SCOMPHY_PORT_CTRL_H_
+#define _SCOMPHY_PORT_CTRL_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif				/* __cplusplus */
+
+#include "fal/fal_port_ctrl.h"
+
+sw_error_t scomphy_port_ctrl_init (a_uint32_t dev_id);
+
+sw_error_t
+scomphy_port_reset (a_uint32_t dev_id, fal_port_t port_id);
+
+/*qca808x_end*/
+#ifdef IN_PORTCONTROL
+/*qca808x_start*/
+#define SCOMPHY_PORT_CTRL_INIT(rv, dev_id) \
+    { \
+        rv = scomphy_port_ctrl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+/*qca808x_end*/
+#else
+#define SCOMPHY_PORT_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+HSL_LOCAL sw_error_t
+scomphy_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id,
+		fal_port_duplex_t duplex);
+
+
+HSL_LOCAL sw_error_t
+scomphy_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id,
+		fal_port_duplex_t * pduplex);
+
+
+HSL_LOCAL sw_error_t
+scomphy_port_speed_set (a_uint32_t dev_id, fal_port_t port_id,
+		fal_port_speed_t speed);
+
+
+HSL_LOCAL sw_error_t
+scomphy_port_speed_get (a_uint32_t dev_id, fal_port_t port_id,
+		fal_port_speed_t * pspeed);
+
+
+HSL_LOCAL sw_error_t
+scomphy_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t * status);
+
+
+HSL_LOCAL sw_error_t
+scomphy_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id);
+
+
+HSL_LOCAL sw_error_t
+scomphy_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id);
+
+
+HSL_LOCAL sw_error_t
+scomphy_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t autoadv);
+
+
+HSL_LOCAL sw_error_t
+scomphy_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t * autoadv);
+
+#ifndef IN_PORTCONTROL_MINI
+HSL_LOCAL sw_error_t
+scomphy_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t enable);
+
+
+HSL_LOCAL sw_error_t
+scomphy_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t * enable);
+
+
+HSL_LOCAL sw_error_t
+scomphy_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t enable);
+
+
+HSL_LOCAL sw_error_t
+scomphy_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t * enable);
+
+
+HSL_LOCAL sw_error_t
+scomphy_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+		fal_cable_status_t * cable_status, a_uint32_t * cable_len);
+#endif
+
+HSL_LOCAL sw_error_t
+scomphy_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t * status);
+#ifndef IN_PORTCONTROL_MINI
+
+HSL_LOCAL sw_error_t
+scomphy_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t enable);
+
+HSL_LOCAL sw_error_t
+scomphy_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t * enable);
+
+HSL_LOCAL sw_error_t
+scomphy_port_mdix_set (a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_port_mdix_mode_t mode);
+
+HSL_LOCAL sw_error_t
+scomphy_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id,
+		fal_port_mdix_mode_t * mode);
+
+HSL_LOCAL sw_error_t
+scomphy_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id,
+		fal_port_mdix_status_t * mode);
+
+HSL_LOCAL sw_error_t
+scomphy_port_combo_prefer_medium_set (a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_port_medium_t phy_medium);
+
+HSL_LOCAL sw_error_t
+scomphy_port_combo_prefer_medium_get (a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_port_medium_t * phy_medium);
+
+HSL_LOCAL sw_error_t
+scomphy_port_combo_medium_status_get (a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_port_medium_t * phy_medium);
+
+HSL_LOCAL sw_error_t
+scomphy_port_combo_fiber_mode_set (a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_port_fiber_mode_t fiber_mode);
+
+HSL_LOCAL sw_error_t
+scomphy_port_combo_fiber_mode_get (a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_port_fiber_mode_t * fiber_mode);
+
+HSL_LOCAL sw_error_t
+scomphy_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t enable);
+
+HSL_LOCAL sw_error_t
+scomphy_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t * enable);
+
+HSL_LOCAL sw_error_t
+scomphy_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t enable);
+
+HSL_LOCAL sw_error_t
+scomphy_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t * enable);
+
+HSL_LOCAL sw_error_t
+scomphy_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id,
+		fal_mac_addr_t * mac);
+
+HSL_LOCAL sw_error_t
+scomphy_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id,
+		fal_mac_addr_t * mac);
+
+HSL_LOCAL sw_error_t
+scomphy_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id,
+		a_uint16_t * org_id, a_uint16_t * rev_id);
+
+HSL_LOCAL sw_error_t
+scomphy_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t enable);
+
+HSL_LOCAL sw_error_t
+scomphy_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t * enable);
+#endif
+HSL_LOCAL sw_error_t
+scomphy_port_power_off (a_uint32_t dev_id, fal_port_t port_id);
+
+HSL_LOCAL sw_error_t
+scomphy_port_power_on (a_uint32_t dev_id, fal_port_t port_id);
+
+#ifndef IN_PORTCONTROL_MINI
+HSL_LOCAL sw_error_t
+scomphy_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+			fal_port_interface_mode_t mode);
+
+HSL_LOCAL sw_error_t
+scomphy_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+		fal_port_interface_mode_t * mode);
+
+HSL_LOCAL sw_error_t
+scomphy_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id,
+		fal_port_interface_mode_t * mode);
+
+HSL_LOCAL sw_error_t
+scomphy_port_counter_set (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t enable);
+
+HSL_LOCAL sw_error_t
+scomphy_port_counter_get (a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t * enable);
+
+HSL_LOCAL sw_error_t
+scomphy_port_counter_show (a_uint32_t dev_id, fal_port_t port_id,
+		fal_port_counter_info_t * counter_info);
+#endif
+#endif
+/*qca808x_start*/
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* _SCOMPHY_PORT_CTRL_H_ */
+/*qca808x_end*/
diff --git a/qca-ssdk/include/hsl/scomphy/scomphy_reg_access.h b/qca-ssdk/include/hsl/scomphy/scomphy_reg_access.h
new file mode 100755
index 0000000..995ff35
--- /dev/null
+++ b/qca-ssdk/include/hsl/scomphy/scomphy_reg_access.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/*qca808x_start*/
+
+#ifndef _SCOMPHY_REG_ACCESS_H_
+#define _SCOMPHY_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "sw.h"
+
+sw_error_t
+scomphy_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+		a_uint32_t reg, a_uint16_t * value);
+
+sw_error_t
+scomphy_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+		a_uint32_t reg, a_uint16_t value);
+/*qca808x_end*/
+
+sw_error_t
+scomphy_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+		a_uint8_t *val, a_uint32_t len);
+
+sw_error_t
+scomphy_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+		a_uint8_t *val, a_uint32_t len);
+
+sw_error_t
+scomphy_uniphy_reg_get(a_uint32_t dev_id, a_uint32_t index,
+		a_uint32_t reg_addr, a_uint8_t *val, a_uint32_t len);
+
+sw_error_t
+scomphy_uniphy_reg_set(a_uint32_t dev_id, a_uint32_t index,
+		a_uint32_t reg_addr, a_uint8_t *val, a_uint32_t len);
+
+/*qca808x_start*/
+sw_error_t
+scomphy_reg_access_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SCOMPHY_REG_ACCESS_H_ */
+/*qca808x_end*/
diff --git a/qca-ssdk/include/hsl/sfp/sfp.h b/qca-ssdk/include/hsl/sfp/sfp.h
new file mode 100644
index 0000000..1863326
--- /dev/null
+++ b/qca-ssdk/include/hsl/sfp/sfp.h
@@ -0,0 +1,956 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _SFP_H_
+#define _SFP_H_
+
+
+sw_error_t
+sfp_eeprom_data_get(a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t i2c_slave,
+		a_uint32_t offset, a_uint8_t *buf, a_uint32_t counter);
+
+sw_error_t
+sfp_eeprom_data_set(a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t i2c_slave,
+		a_uint32_t offset, a_uint8_t *buf, a_uint32_t counter);
+
+sw_error_t
+sfp_dev_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_dev_type_u *value);
+
+sw_error_t
+sfp_dev_type_ext_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_dev_type_ext_u *value);
+
+sw_error_t
+sfp_dev_connector_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_dev_connector_type_u *value);
+
+sw_error_t
+sfp_transc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_transc_u *value);
+
+sw_error_t
+sfp_encoding_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_encoding_u *value);
+
+sw_error_t
+sfp_br_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_br_u *value);
+
+sw_error_t
+sfp_rate_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_rate_u *value);
+
+sw_error_t
+sfp_link_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_link_len_u *value);
+
+sw_error_t
+sfp_vendor_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_vendor_u *value);
+
+sw_error_t
+sfp_laser_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_laser_u *value);
+
+sw_error_t
+sfp_base_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_base_u *value);
+
+sw_error_t
+sfp_option_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_option_u *value);
+
+sw_error_t
+sfp_rate_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_rate_ctrl_u *value);
+
+sw_error_t
+sfp_vendor_ext_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_vendor_ext_u *value);
+
+sw_error_t
+sfp_enhanced_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_enhanced_u *value);
+
+sw_error_t
+sfp_ext_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_ext_u *value);
+
+sw_error_t
+sfp_dev_type_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_dev_type_ext_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_dev_connector_type_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_transc_sonet_ccode_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_transc_fiber_ch_tech_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_transc_sonet_ccode_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_transc_fiber_ch_speed_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_transc_fiber_ch_tech_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_transc_cable_tech_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_transc_fiber_ch_link_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_transc_unallocated_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_transc_fiber_chan_tm_media_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_transc_escon_ccode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_transc_infiniband_ccode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_transc_eth_ccode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_transc_eth_10g_ccode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_encoding_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_br_bit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_rate_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_link_len_om3_mode_1m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_link_len_single_mode_100m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_link_len_om2_mode_10m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_link_len_copper_mode_1m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_link_len_om1_mode_10m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_link_len_single_mode_km_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_vendor_rev_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint8_t *value);
+
+sw_error_t
+sfp_vendor_name_get(
+		a_uint32_t dev_id, a_uint32_t index,
+		a_uint8_t *value);
+
+sw_error_t
+sfp_vendor_oui_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint8_t *value);
+
+sw_error_t
+sfp_vendor_pn_get(
+		a_uint32_t dev_id, a_uint32_t index,
+		a_uint8_t *value);
+
+sw_error_t
+sfp_laser_wavelength_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_base_check_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_option_linear_recv_output_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_option_pwr_level_declar_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_option_unallocated_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_option_unallocated_3_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_option_loss_signal_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_option_rate_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_option_unallocated_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_option_loss_invert_signal_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_option_tx_disable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_option_cool_transc_declar_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_option_tx_fault_signal_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_rate_ctrl_upper_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_rate_ctrl_lower_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_vendor_ext_date_code_get(
+		a_uint32_t dev_id, a_uint32_t index,
+		a_uint8_t *value);
+
+sw_error_t
+sfp_vendor_ext_sn_get(
+		a_uint32_t dev_id, a_uint32_t index,
+		a_uint8_t *value);
+
+sw_error_t
+sfp_enhanced_diag_mon_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_enhanced_rx_los_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_enhanced_cmpl_feature_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_enhanced_tx_disable_ctrl_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_enhanced_alarm_warning_flag_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_enhanced_addr_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_enhanced_unallocated_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_enhanced_soft_rate_sel_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_enhanced_external_cal_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_enhanced_internal_cal_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_enhanced_re_pwr_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_enhanced_soft_rate_ctrl_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_enhanced_app_sel_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_enhanced_legacy_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_enhanced_tx_fault_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_enhanced_unallocated_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_ext_check_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_diag_threshold_u *value);
+
+sw_error_t
+sfp_diag_cal_const_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_diag_cal_const_u *value);
+
+sw_error_t
+sfp_diag_dmi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_diag_dmi_u *value);
+
+sw_error_t
+sfp_diag_realtime_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_diag_realtime_u *value);
+
+sw_error_t
+sfp_diag_optional_ctrl_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_diag_optional_ctrl_status_u *value);
+
+sw_error_t
+sfp_diag_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_diag_flag_u *value);
+
+sw_error_t
+sfp_diag_extended_ctrl_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_diag_extended_ctrl_status_u *value);
+
+sw_error_t
+sfp_diag_threshold_rx_pwr_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_rx_pwr_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_temp_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_vol_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_tx_pwr_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_bias_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_bias_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_vol_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_bias_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_temp_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_rx_pwr_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_vol_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_tx_pwr_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_bias_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_temp_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_tx_pwr_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_vol_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_temp_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_rx_pwr_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_threshold_tx_pwr_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_cal_const_rx_pwr_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_cal_const_t_slope_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_cal_const_rx_pwr_3_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_cal_const_rx_pwr_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_cal_const_tx_i_slope_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_cal_const_v_slope_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_cal_const_tx_pwr_slope_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_cal_const_rx_pwr_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_cal_const_rx_pwr_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_dmi_check_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_realtime_vcc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_realtime_tx_pwr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_realtime_tx_bias_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_realtime_rx_pwr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_realtime_tmp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_optional_ctrl_status_rs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_optional_ctrl_status_tx_fault_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_optional_ctrl_status_rx_los_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_optional_ctrl_status_data_ready_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_optional_ctrl_status_soft_rate_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_optional_ctrl_status_soft_tx_disable_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_optional_ctrl_status_rate_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_optional_ctrl_status_tx_disable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_rx_pwr_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_rx_pwr_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_tx_bias_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_tmp_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_tmp_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_tx_pwr_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_vcc_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_vcc_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_rx_pwr_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_unallocated_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_tx_bias_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_vcc_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_tx_pwr_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_vcc_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_tmp_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_tx_bias_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_tx_bias_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_tmp_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_tx_pwr_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_rx_pwr_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_flag_tx_pwr_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_extended_ctrl_status_unallocated_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_extended_ctrl_status_pwr_level_op_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_extended_ctrl_status_soft_rs_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+sw_error_t
+sfp_diag_extended_ctrl_status_pwr_level_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		unsigned int *value);
+
+#endif
diff --git a/qca-ssdk/include/hsl/sfp/sfp_access.h b/qca-ssdk/include/hsl/sfp/sfp_access.h
new file mode 100755
index 0000000..d96c66e
--- /dev/null
+++ b/qca-ssdk/include/hsl/sfp/sfp_access.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _SFP_ACCESS_H_
+#define _SFP_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "sw.h"
+
+#define SFP_BASE_ADDR         0x0
+#define SFP_DIAG_BASE_ADDR    0x0
+
+#define SFP_EEPROM_BASE_A0    0x50
+#define SFP_EEPROM_DIAG_A2    0x51
+
+
+sw_error_t
+sfp_data_tbl_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave,
+		a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count);
+
+sw_error_t
+sfp_data_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave,
+		a_uint32_t data_addr, a_uint8_t *buf);
+
+sw_error_t
+sfp_data_tbl_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave,
+		a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count);
+
+sw_error_t
+sfp_data_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave,
+		a_uint32_t data_addr, a_uint8_t *buf);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _PPE_SFP_ACCESS_H_ */
diff --git a/qca-ssdk/include/hsl/sfp/sfp_reg.h b/qca-ssdk/include/hsl/sfp/sfp_reg.h
new file mode 100755
index 0000000..59fb4dc
--- /dev/null
+++ b/qca-ssdk/include/hsl/sfp/sfp_reg.h
@@ -0,0 +1,1319 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _SFP_REG_H_
+#define _SFP_REG_H_
+
+/*[register] SFP_DEV_TYPE*/
+#define SFP_DEV_TYPE
+#define SFP_DEV_TYPE_ADDRESS 0x0
+#define SFP_DEV_TYPE_NUM     1
+#define SFP_DEV_TYPE_INC     0x1
+#define SFP_DEV_TYPE_TYPE    REG_TYPE_RO
+#define SFP_DEV_TYPE_DEFAULT 0x0
+	/*[field] ID*/
+	#define SFP_DEV_TYPE_ID
+	#define SFP_DEV_TYPE_ID_OFFSET  0
+	#define SFP_DEV_TYPE_ID_LEN     8
+	#define SFP_DEV_TYPE_ID_DEFAULT 0x0
+
+struct sfp_dev_type {
+	a_uint8_t  id:8;
+};
+
+union sfp_dev_type_u {
+	a_uint8_t val;
+	struct sfp_dev_type bf;
+};
+
+/*[register] SFP_DEV_TYPE_EXT*/
+#define SFP_DEV_TYPE_EXT
+#define SFP_DEV_TYPE_EXT_ADDRESS 0x1
+#define SFP_DEV_TYPE_EXT_NUM     1
+#define SFP_DEV_TYPE_EXT_INC     0x1
+#define SFP_DEV_TYPE_EXT_TYPE    REG_TYPE_RO
+#define SFP_DEV_TYPE_EXT_DEFAULT 0x0
+	/*[field] ID*/
+	#define SFP_DEV_TYPE_EXT_ID
+	#define SFP_DEV_TYPE_EXT_ID_OFFSET  0
+	#define SFP_DEV_TYPE_EXT_ID_LEN     8
+	#define SFP_DEV_TYPE_EXT_ID_DEFAULT 0x0
+
+struct sfp_dev_type_ext {
+	a_uint8_t  id:8;
+};
+
+union sfp_dev_type_ext_u {
+	a_uint8_t val;
+	struct sfp_dev_type_ext bf;
+};
+
+/*[register] SFP_DEV_CONNECTOR_TYPE*/
+#define SFP_DEV_CONNECTOR_TYPE
+#define SFP_DEV_CONNECTOR_TYPE_ADDRESS 0x2
+#define SFP_DEV_CONNECTOR_TYPE_NUM     1
+#define SFP_DEV_CONNECTOR_TYPE_INC     0x1
+#define SFP_DEV_CONNECTOR_TYPE_TYPE    REG_TYPE_RO
+#define SFP_DEV_CONNECTOR_TYPE_DEFAULT 0x0
+	/*[field] CODE*/
+	#define SFP_DEV_CONNECTOR_TYPE_CODE
+	#define SFP_DEV_CONNECTOR_TYPE_CODE_OFFSET  0
+	#define SFP_DEV_CONNECTOR_TYPE_CODE_LEN     8
+	#define SFP_DEV_CONNECTOR_TYPE_CODE_DEFAULT 0x0
+
+struct sfp_dev_connector_type {
+	a_uint8_t  code:8;
+};
+
+union sfp_dev_connector_type_u {
+	a_uint8_t val;
+	struct sfp_dev_connector_type bf;
+};
+
+/*[register] SFP_TRANSC*/
+#define SFP_TRANSC
+#define SFP_TRANSC_ADDRESS 0x3
+#define SFP_TRANSC_NUM     1
+#define SFP_TRANSC_INC     0x8
+#define SFP_TRANSC_TYPE    REG_TYPE_RO
+#define SFP_TRANSC_DEFAULT 0x0
+	/*[field] INFINIBAND_CCODE*/
+	#define SFP_TRANSC_INFINIBAND_CCODE
+	#define SFP_TRANSC_INFINIBAND_CCODE_OFFSET  0
+	#define SFP_TRANSC_INFINIBAND_CCODE_LEN     4
+	#define SFP_TRANSC_INFINIBAND_CCODE_DEFAULT 0x0
+	/*[field] ETH_10G_CCODE*/
+	#define SFP_TRANSC_ETH_10G_CCODE
+	#define SFP_TRANSC_ETH_10G_CCODE_OFFSET  4
+	#define SFP_TRANSC_ETH_10G_CCODE_LEN     4
+	#define SFP_TRANSC_ETH_10G_CCODE_DEFAULT 0x0
+	/*[field] SONET_CCODE_1*/
+	#define SFP_TRANSC_SONET_CCODE_1
+	#define SFP_TRANSC_SONET_CCODE_1_OFFSET  8
+	#define SFP_TRANSC_SONET_CCODE_1_LEN     6
+	#define SFP_TRANSC_SONET_CCODE_1_DEFAULT 0x0
+	/*[field] ESCON_CCODE*/
+	#define SFP_TRANSC_ESCON_CCODE
+	#define SFP_TRANSC_ESCON_CCODE_OFFSET  14
+	#define SFP_TRANSC_ESCON_CCODE_LEN     2
+	#define SFP_TRANSC_ESCON_CCODE_DEFAULT 0x0
+	/*[field] SONET_CCODE_2*/
+	#define SFP_TRANSC_SONET_CCODE_2
+	#define SFP_TRANSC_SONET_CCODE_2_OFFSET  16
+	#define SFP_TRANSC_SONET_CCODE_2_LEN     8
+	#define SFP_TRANSC_SONET_CCODE_2_DEFAULT 0x0
+	/*[field] ETH_CCODE*/
+	#define SFP_TRANSC_ETH_CCODE
+	#define SFP_TRANSC_ETH_CCODE_OFFSET  24
+	#define SFP_TRANSC_ETH_CCODE_LEN     8
+	#define SFP_TRANSC_ETH_CCODE_DEFAULT 0x0
+	/*[field] FIBER_CH_TECH_1*/
+	#define SFP_TRANSC_FIBER_CH_TECH_1
+	#define SFP_TRANSC_FIBER_CH_TECH_1_OFFSET  32
+	#define SFP_TRANSC_FIBER_CH_TECH_1_LEN     3
+	#define SFP_TRANSC_FIBER_CH_TECH_1_DEFAULT 0x0
+	/*[field] FIBER_CH_LINK_LEN*/
+	#define SFP_TRANSC_FIBER_CH_LINK_LEN
+	#define SFP_TRANSC_FIBER_CH_LINK_LEN_OFFSET  35
+	#define SFP_TRANSC_FIBER_CH_LINK_LEN_LEN     5
+	#define SFP_TRANSC_FIBER_CH_LINK_LEN_DEFAULT 0x0
+	/*[field] UNALLOCATED*/
+	#define SFP_TRANSC_UNALLOCATED
+	#define SFP_TRANSC_UNALLOCATED_OFFSET  40
+	#define SFP_TRANSC_UNALLOCATED_LEN     2
+	#define SFP_TRANSC_UNALLOCATED_DEFAULT 0x0
+	/*[field] CABLE_TECH*/
+	#define SFP_TRANSC_CABLE_TECH
+	#define SFP_TRANSC_CABLE_TECH_OFFSET  42
+	#define SFP_TRANSC_CABLE_TECH_LEN     2
+	#define SFP_TRANSC_CABLE_TECH_DEFAULT 0x0
+	/*[field] FIBER_CH_TECH_2*/
+	#define SFP_TRANSC_FIBER_CH_TECH_2
+	#define SFP_TRANSC_FIBER_CH_TECH_2_OFFSET  44
+	#define SFP_TRANSC_FIBER_CH_TECH_2_LEN     4
+	#define SFP_TRANSC_FIBER_CH_TECH_2_DEFAULT 0x0
+	/*[field] FIBER_CHAN_TM_MEDIA*/
+	#define SFP_TRANSC_FIBER_CHAN_TM_MEDIA
+	#define SFP_TRANSC_FIBER_CHAN_TM_MEDIA_OFFSET  48
+	#define SFP_TRANSC_FIBER_CHAN_TM_MEDIA_LEN     8
+	#define SFP_TRANSC_FIBER_CHAN_TM_MEDIA_DEFAULT 0x0
+	/*[field] FIBER_CH_SPEED*/
+	#define SFP_TRANSC_FIBER_CH_SPEED
+	#define SFP_TRANSC_FIBER_CH_SPEED_OFFSET  56
+	#define SFP_TRANSC_FIBER_CH_SPEED_LEN     8
+	#define SFP_TRANSC_FIBER_CH_SPEED_DEFAULT 0x0
+
+struct sfp_transc {
+	a_uint8_t  infiniband_ccode:4;
+	a_uint8_t  eth_10g_ccode:4;
+	a_uint8_t  sonet_ccode_1:6;
+	a_uint8_t  escon_ccode:2;
+	a_uint8_t  sonet_ccode_2:8;
+	a_uint8_t  eth_ccode:8;
+	a_uint8_t  fiber_ch_tech_1:3;
+	a_uint8_t  fiber_ch_link_len:5;
+	a_uint8_t  unallocated:2;
+	a_uint8_t  cable_tech:2;
+	a_uint8_t  fiber_ch_tech_2:4;
+	a_uint8_t  fiber_chan_tm_media:8;
+	a_uint8_t  fiber_ch_speed:8;
+};
+
+union sfp_transc_u {
+	a_uint8_t val[8];
+	struct sfp_transc bf;
+};
+
+/*[register] SFP_ENCODING*/
+#define SFP_ENCODING
+#define SFP_ENCODING_ADDRESS 0xb
+#define SFP_ENCODING_NUM     1
+#define SFP_ENCODING_INC     0x1
+#define SFP_ENCODING_TYPE    REG_TYPE_RO
+#define SFP_ENCODING_DEFAULT 0x0
+	/*[field] CODE*/
+	#define SFP_ENCODING_CODE
+	#define SFP_ENCODING_CODE_OFFSET  0
+	#define SFP_ENCODING_CODE_LEN     8
+	#define SFP_ENCODING_CODE_DEFAULT 0x0
+
+struct sfp_encoding {
+	a_uint8_t  code:8;
+};
+
+union sfp_encoding_u {
+	a_uint8_t val;
+	struct sfp_encoding bf;
+};
+
+/*[register] SFP_BR*/
+#define SFP_BR
+#define SFP_BR_ADDRESS 0xc
+#define SFP_BR_NUM     1
+#define SFP_BR_INC     0x1
+#define SFP_BR_TYPE    REG_TYPE_RO
+#define SFP_BR_DEFAULT 0x0
+	/*[field] BIT*/
+	#define SFP_BR_BIT
+	#define SFP_BR_BIT_OFFSET  0
+	#define SFP_BR_BIT_LEN     8
+	#define SFP_BR_BIT_DEFAULT 0x0
+
+struct sfp_br {
+	a_uint8_t  bit:8;
+};
+
+union sfp_br_u {
+	a_uint8_t val;
+	struct sfp_br bf;
+};
+
+/*[register] SFP_RATE*/
+#define SFP_RATE
+#define SFP_RATE_ADDRESS 0xd
+#define SFP_RATE_NUM     1
+#define SFP_RATE_INC     0x1
+#define SFP_RATE_TYPE    REG_TYPE_RO
+#define SFP_RATE_DEFAULT 0x0
+	/*[field] ID*/
+	#define SFP_RATE_ID
+	#define SFP_RATE_ID_OFFSET  0
+	#define SFP_RATE_ID_LEN     8
+	#define SFP_RATE_ID_DEFAULT 0x0
+
+struct sfp_rate {
+	a_uint8_t  id:8;
+};
+
+union sfp_rate_u {
+	a_uint8_t val;
+	struct sfp_rate bf;
+};
+
+/*[register] SFP_LINK_LEN*/
+#define SFP_LINK_LEN
+#define SFP_LINK_LEN_ADDRESS 0xe
+#define SFP_LINK_LEN_NUM     1
+#define SFP_LINK_LEN_INC     0x6
+#define SFP_LINK_LEN_TYPE    REG_TYPE_RO
+#define SFP_LINK_LEN_DEFAULT 0x0
+	/*[field] SINGLE_MODE_KM*/
+	#define SFP_LINK_LEN_SINGLE_MODE_KM
+	#define SFP_LINK_LEN_SINGLE_MODE_KM_OFFSET  0
+	#define SFP_LINK_LEN_SINGLE_MODE_KM_LEN     8
+	#define SFP_LINK_LEN_SINGLE_MODE_KM_DEFAULT 0x0
+	/*[field] SINGLE_MODE_100M*/
+	#define SFP_LINK_LEN_SINGLE_MODE_100M
+	#define SFP_LINK_LEN_SINGLE_MODE_100M_OFFSET  8
+	#define SFP_LINK_LEN_SINGLE_MODE_100M_LEN     8
+	#define SFP_LINK_LEN_SINGLE_MODE_100M_DEFAULT 0x0
+	/*[field] OM2_MODE_10M*/
+	#define SFP_LINK_LEN_OM2_MODE_10M
+	#define SFP_LINK_LEN_OM2_MODE_10M_OFFSET  16
+	#define SFP_LINK_LEN_OM2_MODE_10M_LEN     8
+	#define SFP_LINK_LEN_OM2_MODE_10M_DEFAULT 0x0
+	/*[field] OM1_MODE_10M*/
+	#define SFP_LINK_LEN_OM1_MODE_10M
+	#define SFP_LINK_LEN_OM1_MODE_10M_OFFSET  24
+	#define SFP_LINK_LEN_OM1_MODE_10M_LEN     8
+	#define SFP_LINK_LEN_OM1_MODE_10M_DEFAULT 0x0
+	/*[field] COPPER_MODE_1M*/
+	#define SFP_LINK_LEN_COPPER_MODE_1M
+	#define SFP_LINK_LEN_COPPER_MODE_1M_OFFSET  32
+	#define SFP_LINK_LEN_COPPER_MODE_1M_LEN     8
+	#define SFP_LINK_LEN_COPPER_MODE_1M_DEFAULT 0x0
+	/*[field] OM3_MODE_1M*/
+	#define SFP_LINK_LEN_OM3_MODE_1M
+	#define SFP_LINK_LEN_OM3_MODE_1M_OFFSET  40
+	#define SFP_LINK_LEN_OM3_MODE_1M_LEN     8
+	#define SFP_LINK_LEN_OM3_MODE_1M_DEFAULT 0x0
+
+struct sfp_link_len {
+	a_uint8_t  single_mode_km:8;
+	a_uint8_t  single_mode_100m:8;
+	a_uint8_t  om2_mode_10m:8;
+	a_uint8_t  om1_mode_10m:8;
+	a_uint8_t  copper_mode_1m:8;
+	a_uint8_t  om3_mode_1m:8;
+};
+
+union sfp_link_len_u {
+	a_uint8_t val[6];
+	struct sfp_link_len bf;
+};
+
+/*[register] SFP_VENDOR*/
+#define SFP_VENDOR
+#define SFP_VENDOR_ADDRESS 0x14
+#define SFP_VENDOR_NUM     1
+#define SFP_VENDOR_INC     0x28
+#define SFP_VENDOR_TYPE    REG_TYPE_RO
+#define SFP_VENDOR_DEFAULT 0x0
+	/*[field] NAME*/
+	#define SFP_VENDOR_NAME
+	#define SFP_VENDOR_NAME_OFFSET  0
+	#define SFP_VENDOR_NAME_LEN     128
+	#define SFP_VENDOR_NAME_DEFAULT 0x0
+	/*[field] TRANSCODE*/
+	#define SFP_VENDOR_TRANSCODE
+	#define SFP_VENDOR_TRANSCODE_OFFSET  128
+	#define SFP_VENDOR_TRANSCODE_LEN     8
+	#define SFP_VENDOR_TRANSCODE_DEFAULT 0x0
+	/*[field] OUI*/
+	#define SFP_VENDOR_OUI
+	#define SFP_VENDOR_OUI_OFFSET  136
+	#define SFP_VENDOR_OUI_LEN     24
+	#define SFP_VENDOR_OUI_DEFAULT 0x0
+	/*[field] PN*/
+	#define SFP_VENDOR_PN
+	#define SFP_VENDOR_PN_OFFSET  160
+	#define SFP_VENDOR_PN_LEN     128
+	#define SFP_VENDOR_PN_DEFAULT 0x0
+	/*[field] REV*/
+	#define SFP_VENDOR_REV
+	#define SFP_VENDOR_REV_OFFSET  288
+	#define SFP_VENDOR_REV_LEN     32
+	#define SFP_VENDOR_REV_DEFAULT 0x0
+
+struct sfp_vendor {
+	a_uint8_t  name_0:8;
+	a_uint8_t  name_1:8;
+	a_uint8_t  name_2:8;
+	a_uint8_t  name_3:8;
+	a_uint8_t  name_4:8;
+	a_uint8_t  name_5:8;
+	a_uint8_t  name_6:8;
+	a_uint8_t  name_7:8;
+	a_uint8_t  name_8:8;
+	a_uint8_t  name_9:8;
+	a_uint8_t  name_10:8;
+	a_uint8_t  name_11:8;
+	a_uint8_t  name_12:8;
+	a_uint8_t  name_13:8;
+	a_uint8_t  name_14:8;
+	a_uint8_t  name_15:8;
+	a_uint8_t  transcode:8;
+	a_uint8_t  oui_0:8;
+	a_uint8_t  oui_1:8;
+	a_uint8_t  oui_2:8;
+	a_uint8_t  pn_0:8;
+	a_uint8_t  pn_1:8;
+	a_uint8_t  pn_2:8;
+	a_uint8_t  pn_3:8;
+	a_uint8_t  pn_4:8;
+	a_uint8_t  pn_5:8;
+	a_uint8_t  pn_6:8;
+	a_uint8_t  pn_7:8;
+	a_uint8_t  pn_8:8;
+	a_uint8_t  pn_9:8;
+	a_uint8_t  pn_10:8;
+	a_uint8_t  pn_11:8;
+	a_uint8_t  pn_12:8;
+	a_uint8_t  pn_13:8;
+	a_uint8_t  pn_14:8;
+	a_uint8_t  pn_15:8;
+	a_uint8_t  rev_0:8;
+	a_uint8_t  rev_1:8;
+	a_uint8_t  rev_2:8;
+	a_uint8_t  rev_3:8;
+};
+
+union sfp_vendor_u {
+	a_uint8_t val[40];
+	struct sfp_vendor bf;
+};
+
+/*[register] SFP_LASER*/
+#define SFP_LASER
+#define SFP_LASER_ADDRESS 0x3c
+#define SFP_LASER_NUM     1
+#define SFP_LASER_INC     0x2
+#define SFP_LASER_TYPE    REG_TYPE_RO
+#define SFP_LASER_DEFAULT 0x0
+	/*[field] WAVELENGTH*/
+	#define SFP_LASER_WAVELENGTH
+	#define SFP_LASER_WAVELENGTH_OFFSET  0
+	#define SFP_LASER_WAVELENGTH_LEN     16
+	#define SFP_LASER_WAVELENGTH_DEFAULT 0x0
+
+struct sfp_laser {
+	a_uint8_t  wavelength_0:8;
+	a_uint8_t  wavelength_1:8;
+};
+
+union sfp_laser_u {
+	a_uint8_t val[2];
+	struct sfp_laser bf;
+};
+
+/*[register] SFP_BASE*/
+#define SFP_BASE
+#define SFP_BASE_ADDRESS 0x3f
+#define SFP_BASE_NUM     1
+#define SFP_BASE_INC     0x1
+#define SFP_BASE_TYPE    REG_TYPE_RO
+#define SFP_BASE_DEFAULT 0x0
+	/*[field] CHECK_CODE*/
+	#define SFP_BASE_CHECK_CODE
+	#define SFP_BASE_CHECK_CODE_OFFSET  0
+	#define SFP_BASE_CHECK_CODE_LEN     8
+	#define SFP_BASE_CHECK_CODE_DEFAULT 0x0
+
+struct sfp_base {
+	a_uint8_t  check_code:8;
+};
+
+union sfp_base_u {
+	a_uint8_t val;
+	struct sfp_base bf;
+};
+
+/*[register] SFP_OPTION*/
+#define SFP_OPTION
+#define SFP_OPTION_ADDRESS 0x40
+#define SFP_OPTION_NUM     1
+#define SFP_OPTION_INC     0x2
+#define SFP_OPTION_TYPE    REG_TYPE_RO
+#define SFP_OPTION_DEFAULT 0x0
+	/*[field] LINEAR_RECV_OUTPUT*/
+	#define SFP_OPTION_LINEAR_RECV_OUTPUT
+	#define SFP_OPTION_LINEAR_RECV_OUTPUT_OFFSET  0
+	#define SFP_OPTION_LINEAR_RECV_OUTPUT_LEN     1
+	#define SFP_OPTION_LINEAR_RECV_OUTPUT_DEFAULT 0x0
+	/*[field] PWR_LEVEL_DECLAR*/
+	#define SFP_OPTION_PWR_LEVEL_DECLAR
+	#define SFP_OPTION_PWR_LEVEL_DECLAR_OFFSET  1
+	#define SFP_OPTION_PWR_LEVEL_DECLAR_LEN     1
+	#define SFP_OPTION_PWR_LEVEL_DECLAR_DEFAULT 0x0
+	/*[field] COOL_TRANSC_DECLAR*/
+	#define SFP_OPTION_COOL_TRANSC_DECLAR
+	#define SFP_OPTION_COOL_TRANSC_DECLAR_OFFSET  2
+	#define SFP_OPTION_COOL_TRANSC_DECLAR_LEN     1
+	#define SFP_OPTION_COOL_TRANSC_DECLAR_DEFAULT 0x0
+	/*[field] UNALLOCATED_1*/
+	#define SFP_OPTION_UNALLOCATED_1
+	#define SFP_OPTION_UNALLOCATED_1_OFFSET  3
+	#define SFP_OPTION_UNALLOCATED_1_LEN     5
+	#define SFP_OPTION_UNALLOCATED_1_DEFAULT 0x0
+	/*[field] UNALLOCATED_2*/
+	#define SFP_OPTION_UNALLOCATED_2
+	#define SFP_OPTION_UNALLOCATED_2_OFFSET  8
+	#define SFP_OPTION_UNALLOCATED_2_LEN     1
+	#define SFP_OPTION_UNALLOCATED_2_DEFAULT 0x0
+	/*[field] LOSS_SIGNAL*/
+	#define SFP_OPTION_LOSS_SIGNAL
+	#define SFP_OPTION_LOSS_SIGNAL_OFFSET  9
+	#define SFP_OPTION_LOSS_SIGNAL_LEN     1
+	#define SFP_OPTION_LOSS_SIGNAL_DEFAULT 0x0
+	/*[field] LOSS_INVERT_SIGNAL*/
+	#define SFP_OPTION_LOSS_INVERT_SIGNAL
+	#define SFP_OPTION_LOSS_INVERT_SIGNAL_OFFSET  10
+	#define SFP_OPTION_LOSS_INVERT_SIGNAL_LEN     1
+	#define SFP_OPTION_LOSS_INVERT_SIGNAL_DEFAULT 0x0
+	/*[field] TX_FAULT_SIGNAL*/
+	#define SFP_OPTION_TX_FAULT_SIGNAL
+	#define SFP_OPTION_TX_FAULT_SIGNAL_OFFSET  11
+	#define SFP_OPTION_TX_FAULT_SIGNAL_LEN     1
+	#define SFP_OPTION_TX_FAULT_SIGNAL_DEFAULT 0x0
+	/*[field] TX_DISABLE*/
+	#define SFP_OPTION_TX_DISABLE
+	#define SFP_OPTION_TX_DISABLE_OFFSET  12
+	#define SFP_OPTION_TX_DISABLE_LEN     1
+	#define SFP_OPTION_TX_DISABLE_DEFAULT 0x0
+	/*[field] RATE_SEL*/
+	#define SFP_OPTION_RATE_SEL
+	#define SFP_OPTION_RATE_SEL_OFFSET  13
+	#define SFP_OPTION_RATE_SEL_LEN     1
+	#define SFP_OPTION_RATE_SEL_DEFAULT 0x0
+	/*[field] UNALLOCATED_3*/
+	#define SFP_OPTION_UNALLOCATED_3
+	#define SFP_OPTION_UNALLOCATED_3_OFFSET  14
+	#define SFP_OPTION_UNALLOCATED_3_LEN     2
+	#define SFP_OPTION_UNALLOCATED_3_DEFAULT 0x0
+
+struct sfp_option {
+	a_uint8_t  linear_recv_output:1;
+	a_uint8_t  pwr_level_declar:1;
+	a_uint8_t  cool_transc_declar:1;
+	a_uint8_t  unallocated_1:5;
+	a_uint8_t  unallocated_2:1;
+	a_uint8_t  loss_signal:1;
+	a_uint8_t  loss_invert_signal:1;
+	a_uint8_t  tx_fault_signal:1;
+	a_uint8_t  tx_disable:1;
+	a_uint8_t  rate_sel:1;
+	a_uint8_t  unallocated_3:2;
+};
+
+union sfp_option_u {
+	a_uint8_t val[2];
+	struct sfp_option bf;
+};
+
+/*[register] SFP_RATE_CTRL*/
+#define SFP_RATE_CTRL
+#define SFP_RATE_CTRL_ADDRESS 0x42
+#define SFP_RATE_CTRL_NUM     1
+#define SFP_RATE_CTRL_INC     0x2
+#define SFP_RATE_CTRL_TYPE    REG_TYPE_RO
+#define SFP_RATE_CTRL_DEFAULT 0x0
+	/*[field] UPPER*/
+	#define SFP_RATE_CTRL_UPPER
+	#define SFP_RATE_CTRL_UPPER_OFFSET  0
+	#define SFP_RATE_CTRL_UPPER_LEN     8
+	#define SFP_RATE_CTRL_UPPER_DEFAULT 0x0
+	/*[field] LOWER*/
+	#define SFP_RATE_CTRL_LOWER
+	#define SFP_RATE_CTRL_LOWER_OFFSET  8
+	#define SFP_RATE_CTRL_LOWER_LEN     8
+	#define SFP_RATE_CTRL_LOWER_DEFAULT 0x0
+
+struct sfp_rate_ctrl {
+	a_uint8_t  upper:8;
+	a_uint8_t  lower:8;
+};
+
+union sfp_rate_ctrl_u {
+	a_uint8_t val[2];
+	struct sfp_rate_ctrl bf;
+};
+
+/*[register] SFP_VENDOR_EXT*/
+#define SFP_VENDOR_EXT
+#define SFP_VENDOR_EXT_ADDRESS 0x44
+#define SFP_VENDOR_EXT_NUM     1
+#define SFP_VENDOR_EXT_INC     0x18
+#define SFP_VENDOR_EXT_TYPE    REG_TYPE_RO
+#define SFP_VENDOR_EXT_DEFAULT 0x0
+	/*[field] SN*/
+	#define SFP_VENDOR_EXT_SN
+	#define SFP_VENDOR_EXT_SN_OFFSET  0
+	#define SFP_VENDOR_EXT_SN_LEN     128
+	#define SFP_VENDOR_EXT_SN_DEFAULT 0x0
+	/*[field] DATE_CODE*/
+	#define SFP_VENDOR_EXT_DATE_CODE
+	#define SFP_VENDOR_EXT_DATE_CODE_OFFSET  128
+	#define SFP_VENDOR_EXT_DATE_CODE_LEN     64
+	#define SFP_VENDOR_EXT_DATE_CODE_DEFAULT 0x0
+
+struct sfp_vendor_ext {
+	a_uint8_t  sn_0:8;
+	a_uint8_t  sn_1:8;
+	a_uint8_t  sn_2:8;
+	a_uint8_t  sn_3:8;
+	a_uint8_t  sn_4:8;
+	a_uint8_t  sn_5:8;
+	a_uint8_t  sn_6:8;
+	a_uint8_t  sn_7:8;
+	a_uint8_t  sn_8:8;
+	a_uint8_t  sn_9:8;
+	a_uint8_t  sn_10:8;
+	a_uint8_t  sn_11:8;
+	a_uint8_t  sn_12:8;
+	a_uint8_t  sn_13:8;
+	a_uint8_t  sn_14:8;
+	a_uint8_t  sn_15:8;
+	a_uint8_t  date_code_0:8;
+	a_uint8_t  date_code_1:8;
+	a_uint8_t  date_code_2:8;
+	a_uint8_t  date_code_3:8;
+	a_uint8_t  date_code_4:8;
+	a_uint8_t  date_code_5:8;
+	a_uint8_t  date_code_6:8;
+	a_uint8_t  date_code_7:8;
+};
+
+union sfp_vendor_ext_u {
+	a_uint8_t val[24];
+	struct sfp_vendor_ext bf;
+};
+
+/*[register] SFP_ENHANCED*/
+#define SFP_ENHANCED
+#define SFP_ENHANCED_ADDRESS 0x5c
+#define SFP_ENHANCED_NUM     1
+#define SFP_ENHANCED_INC     0x3
+#define SFP_ENHANCED_TYPE    REG_TYPE_RO
+#define SFP_ENHANCED_DEFAULT 0x0
+	/*[field] UNALLOCATED_TYPE*/
+	#define SFP_ENHANCED_UNALLOCATED_TYPE
+	#define SFP_ENHANCED_UNALLOCATED_TYPE_OFFSET  0
+	#define SFP_ENHANCED_UNALLOCATED_TYPE_LEN     2
+	#define SFP_ENHANCED_UNALLOCATED_TYPE_DEFAULT 0x0
+	/*[field] ADDR_MODE*/
+	#define SFP_ENHANCED_ADDR_MODE
+	#define SFP_ENHANCED_ADDR_MODE_OFFSET  2
+	#define SFP_ENHANCED_ADDR_MODE_LEN     1
+	#define SFP_ENHANCED_ADDR_MODE_DEFAULT 0x0
+	/*[field] RE_PWR_TYPE*/
+	#define SFP_ENHANCED_RE_PWR_TYPE
+	#define SFP_ENHANCED_RE_PWR_TYPE_OFFSET  3
+	#define SFP_ENHANCED_RE_PWR_TYPE_LEN     1
+	#define SFP_ENHANCED_RE_PWR_TYPE_DEFAULT 0x0
+	/*[field] EXTERNAL_CAL*/
+	#define SFP_ENHANCED_EXTERNAL_CAL
+	#define SFP_ENHANCED_EXTERNAL_CAL_OFFSET  4
+	#define SFP_ENHANCED_EXTERNAL_CAL_LEN     1
+	#define SFP_ENHANCED_EXTERNAL_CAL_DEFAULT 0x0
+	/*[field] INTERNAL_CAL*/
+	#define SFP_ENHANCED_INTERNAL_CAL
+	#define SFP_ENHANCED_INTERNAL_CAL_OFFSET  5
+	#define SFP_ENHANCED_INTERNAL_CAL_LEN     1
+	#define SFP_ENHANCED_INTERNAL_CAL_DEFAULT 0x0
+	/*[field] DIAG_MON_FLAG*/
+	#define SFP_ENHANCED_DIAG_MON_FLAG
+	#define SFP_ENHANCED_DIAG_MON_FLAG_OFFSET  6
+	#define SFP_ENHANCED_DIAG_MON_FLAG_LEN     1
+	#define SFP_ENHANCED_DIAG_MON_FLAG_DEFAULT 0x0
+	/*[field] LEGACY_TYPE*/
+	#define SFP_ENHANCED_LEGACY_TYPE
+	#define SFP_ENHANCED_LEGACY_TYPE_OFFSET  7
+	#define SFP_ENHANCED_LEGACY_TYPE_LEN     1
+	#define SFP_ENHANCED_LEGACY_TYPE_DEFAULT 0x0
+	/*[field] UNALLOCATED_OP*/
+	#define SFP_ENHANCED_UNALLOCATED_OP
+	#define SFP_ENHANCED_UNALLOCATED_OP_OFFSET  8
+	#define SFP_ENHANCED_UNALLOCATED_OP_LEN     1
+	#define SFP_ENHANCED_UNALLOCATED_OP_DEFAULT 0x0
+	/*[field] SOFT_RATE_SEL_OP*/
+	#define SFP_ENHANCED_SOFT_RATE_SEL_OP
+	#define SFP_ENHANCED_SOFT_RATE_SEL_OP_OFFSET  9
+	#define SFP_ENHANCED_SOFT_RATE_SEL_OP_LEN     1
+	#define SFP_ENHANCED_SOFT_RATE_SEL_OP_DEFAULT 0x0
+	/*[field] APP_SEL_OP*/
+	#define SFP_ENHANCED_APP_SEL_OP
+	#define SFP_ENHANCED_APP_SEL_OP_OFFSET  10
+	#define SFP_ENHANCED_APP_SEL_OP_LEN     1
+	#define SFP_ENHANCED_APP_SEL_OP_DEFAULT 0x0
+	/*[field] SOFT_RATE_CTRL_OP*/
+	#define SFP_ENHANCED_SOFT_RATE_CTRL_OP
+	#define SFP_ENHANCED_SOFT_RATE_CTRL_OP_OFFSET  11
+	#define SFP_ENHANCED_SOFT_RATE_CTRL_OP_LEN     1
+	#define SFP_ENHANCED_SOFT_RATE_CTRL_OP_DEFAULT 0x0
+	/*[field] RX_LOS_OP*/
+	#define SFP_ENHANCED_RX_LOS_OP
+	#define SFP_ENHANCED_RX_LOS_OP_OFFSET  12
+	#define SFP_ENHANCED_RX_LOS_OP_LEN     1
+	#define SFP_ENHANCED_RX_LOS_OP_DEFAULT 0x0
+	/*[field] TX_FAULT_OP*/
+	#define SFP_ENHANCED_TX_FAULT_OP
+	#define SFP_ENHANCED_TX_FAULT_OP_OFFSET  13
+	#define SFP_ENHANCED_TX_FAULT_OP_LEN     1
+	#define SFP_ENHANCED_TX_FAULT_OP_DEFAULT 0x0
+	/*[field] TX_DISABLE_CTRL_OP*/
+	#define SFP_ENHANCED_TX_DISABLE_CTRL_OP
+	#define SFP_ENHANCED_TX_DISABLE_CTRL_OP_OFFSET  14
+	#define SFP_ENHANCED_TX_DISABLE_CTRL_OP_LEN     1
+	#define SFP_ENHANCED_TX_DISABLE_CTRL_OP_DEFAULT 0x0
+	/*[field] ALARM_WARNING_FLAG_OP*/
+	#define SFP_ENHANCED_ALARM_WARNING_FLAG_OP
+	#define SFP_ENHANCED_ALARM_WARNING_FLAG_OP_OFFSET  15
+	#define SFP_ENHANCED_ALARM_WARNING_FLAG_OP_LEN     1
+	#define SFP_ENHANCED_ALARM_WARNING_FLAG_OP_DEFAULT 0x0
+	/*[field] CMPL_FEATURE*/
+	#define SFP_ENHANCED_CMPL_FEATURE
+	#define SFP_ENHANCED_CMPL_FEATURE_OFFSET  16
+	#define SFP_ENHANCED_CMPL_FEATURE_LEN     8
+	#define SFP_ENHANCED_CMPL_FEATURE_DEFAULT 0x0
+
+struct sfp_enhanced {
+	a_uint8_t  unallocated_type:2;
+	a_uint8_t  addr_mode:1;
+	a_uint8_t  re_pwr_type:1;
+	a_uint8_t  external_cal:1;
+	a_uint8_t  internal_cal:1;
+	a_uint8_t  diag_mon_flag:1;
+	a_uint8_t  legacy_type:1;
+	a_uint8_t  unallocated_op:1;
+	a_uint8_t  soft_rate_sel_op:1;
+	a_uint8_t  app_sel_op:1;
+	a_uint8_t  soft_rate_ctrl_op:1;
+	a_uint8_t  rx_los_op:1;
+	a_uint8_t  tx_fault_op:1;
+	a_uint8_t  tx_disable_ctrl_op:1;
+	a_uint8_t  alarm_warning_flag_op:1;
+	a_uint8_t  cmpl_feature:8;
+};
+
+union sfp_enhanced_u {
+	a_uint8_t val[3];
+	struct sfp_enhanced bf;
+};
+
+/*[register] SFP_EXT*/
+#define SFP_EXT
+#define SFP_EXT_ADDRESS 0x5f
+#define SFP_EXT_NUM     1
+#define SFP_EXT_INC     0x1
+#define SFP_EXT_TYPE    REG_TYPE_RO
+#define SFP_EXT_DEFAULT 0x0
+	/*[field] CHECK_CODE*/
+	#define SFP_EXT_CHECK_CODE
+	#define SFP_EXT_CHECK_CODE_OFFSET  0
+	#define SFP_EXT_CHECK_CODE_LEN     8
+	#define SFP_EXT_CHECK_CODE_DEFAULT 0x0
+
+struct sfp_ext {
+	a_uint8_t  check_code:8;
+};
+
+union sfp_ext_u {
+	a_uint8_t val;
+	struct sfp_ext bf;
+};
+
+/*[register] SFP_DIAG_THRESHOLD*/
+#define SFP_DIAG_THRESHOLD
+#define SFP_DIAG_THRESHOLD_ADDRESS 0x0
+#define SFP_DIAG_THRESHOLD_NUM     1
+#define SFP_DIAG_THRESHOLD_INC     0x28
+#define SFP_DIAG_THRESHOLD_TYPE    REG_TYPE_RO
+#define SFP_DIAG_THRESHOLD_DEFAULT 0x0
+	/*[field] TEMP_HIGH_ALARM*/
+	#define SFP_DIAG_THRESHOLD_TEMP_HIGH_ALARM
+	#define SFP_DIAG_THRESHOLD_TEMP_HIGH_ALARM_OFFSET  0
+	#define SFP_DIAG_THRESHOLD_TEMP_HIGH_ALARM_LEN     16
+	#define SFP_DIAG_THRESHOLD_TEMP_HIGH_ALARM_DEFAULT 0x0
+	/*[field] TEMP_LOW_ALARM*/
+	#define SFP_DIAG_THRESHOLD_TEMP_LOW_ALARM
+	#define SFP_DIAG_THRESHOLD_TEMP_LOW_ALARM_OFFSET  16
+	#define SFP_DIAG_THRESHOLD_TEMP_LOW_ALARM_LEN     16
+	#define SFP_DIAG_THRESHOLD_TEMP_LOW_ALARM_DEFAULT 0x0
+	/*[field] TEMP_HIGH_WARNING*/
+	#define SFP_DIAG_THRESHOLD_TEMP_HIGH_WARNING
+	#define SFP_DIAG_THRESHOLD_TEMP_HIGH_WARNING_OFFSET  32
+	#define SFP_DIAG_THRESHOLD_TEMP_HIGH_WARNING_LEN     16
+	#define SFP_DIAG_THRESHOLD_TEMP_HIGH_WARNING_DEFAULT 0x0
+	/*[field] TEMP_LOW_WARNING*/
+	#define SFP_DIAG_THRESHOLD_TEMP_LOW_WARNING
+	#define SFP_DIAG_THRESHOLD_TEMP_LOW_WARNING_OFFSET  48
+	#define SFP_DIAG_THRESHOLD_TEMP_LOW_WARNING_LEN     16
+	#define SFP_DIAG_THRESHOLD_TEMP_LOW_WARNING_DEFAULT 0x0
+	/*[field] VOL_HIGH_ALARM*/
+	#define SFP_DIAG_THRESHOLD_VOL_HIGH_ALARM
+	#define SFP_DIAG_THRESHOLD_VOL_HIGH_ALARM_OFFSET  64
+	#define SFP_DIAG_THRESHOLD_VOL_HIGH_ALARM_LEN     16
+	#define SFP_DIAG_THRESHOLD_VOL_HIGH_ALARM_DEFAULT 0x0
+	/*[field] VOL_LOW_ALARM*/
+	#define SFP_DIAG_THRESHOLD_VOL_LOW_ALARM
+	#define SFP_DIAG_THRESHOLD_VOL_LOW_ALARM_OFFSET  80
+	#define SFP_DIAG_THRESHOLD_VOL_LOW_ALARM_LEN     16
+	#define SFP_DIAG_THRESHOLD_VOL_LOW_ALARM_DEFAULT 0x0
+	/*[field] VOL_HIGH_WARNING*/
+	#define SFP_DIAG_THRESHOLD_VOL_HIGH_WARNING
+	#define SFP_DIAG_THRESHOLD_VOL_HIGH_WARNING_OFFSET  96
+	#define SFP_DIAG_THRESHOLD_VOL_HIGH_WARNING_LEN     16
+	#define SFP_DIAG_THRESHOLD_VOL_HIGH_WARNING_DEFAULT 0x0
+	/*[field] VOL_LOW_WARNING*/
+	#define SFP_DIAG_THRESHOLD_VOL_LOW_WARNING
+	#define SFP_DIAG_THRESHOLD_VOL_LOW_WARNING_OFFSET  112
+	#define SFP_DIAG_THRESHOLD_VOL_LOW_WARNING_LEN     16
+	#define SFP_DIAG_THRESHOLD_VOL_LOW_WARNING_DEFAULT 0x0
+	/*[field] BIAS_HIGH_ALARM*/
+	#define SFP_DIAG_THRESHOLD_BIAS_HIGH_ALARM
+	#define SFP_DIAG_THRESHOLD_BIAS_HIGH_ALARM_OFFSET  128
+	#define SFP_DIAG_THRESHOLD_BIAS_HIGH_ALARM_LEN     16
+	#define SFP_DIAG_THRESHOLD_BIAS_HIGH_ALARM_DEFAULT 0x0
+	/*[field] BIAS_LOW_ALARM*/
+	#define SFP_DIAG_THRESHOLD_BIAS_LOW_ALARM
+	#define SFP_DIAG_THRESHOLD_BIAS_LOW_ALARM_OFFSET  144
+	#define SFP_DIAG_THRESHOLD_BIAS_LOW_ALARM_LEN     16
+	#define SFP_DIAG_THRESHOLD_BIAS_LOW_ALARM_DEFAULT 0x0
+	/*[field] BIAS_HIGH_WARNING*/
+	#define SFP_DIAG_THRESHOLD_BIAS_HIGH_WARNING
+	#define SFP_DIAG_THRESHOLD_BIAS_HIGH_WARNING_OFFSET  160
+	#define SFP_DIAG_THRESHOLD_BIAS_HIGH_WARNING_LEN     16
+	#define SFP_DIAG_THRESHOLD_BIAS_HIGH_WARNING_DEFAULT 0x0
+	/*[field] BIAS_LOW_WARNING*/
+	#define SFP_DIAG_THRESHOLD_BIAS_LOW_WARNING
+	#define SFP_DIAG_THRESHOLD_BIAS_LOW_WARNING_OFFSET  176
+	#define SFP_DIAG_THRESHOLD_BIAS_LOW_WARNING_LEN     16
+	#define SFP_DIAG_THRESHOLD_BIAS_LOW_WARNING_DEFAULT 0x0
+	/*[field] TX_PWR_HIGH_ALARM*/
+	#define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_ALARM
+	#define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_ALARM_OFFSET  192
+	#define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_ALARM_LEN     16
+	#define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_ALARM_DEFAULT 0x0
+	/*[field] TX_PWR_LOW_ALARM*/
+	#define SFP_DIAG_THRESHOLD_TX_PWR_LOW_ALARM
+	#define SFP_DIAG_THRESHOLD_TX_PWR_LOW_ALARM_OFFSET  208
+	#define SFP_DIAG_THRESHOLD_TX_PWR_LOW_ALARM_LEN     16
+	#define SFP_DIAG_THRESHOLD_TX_PWR_LOW_ALARM_DEFAULT 0x0
+	/*[field] TX_PWR_HIGH_WARNING*/
+	#define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_WARNING
+	#define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_WARNING_OFFSET  224
+	#define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_WARNING_LEN     16
+	#define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_WARNING_DEFAULT 0x0
+	/*[field] TX_PWR_LOW_WARNING*/
+	#define SFP_DIAG_THRESHOLD_TX_PWR_LOW_WARNING
+	#define SFP_DIAG_THRESHOLD_TX_PWR_LOW_WARNING_OFFSET  240
+	#define SFP_DIAG_THRESHOLD_TX_PWR_LOW_WARNING_LEN     16
+	#define SFP_DIAG_THRESHOLD_TX_PWR_LOW_WARNING_DEFAULT 0x0
+	/*[field] RX_PWR_HIGH_ALARM*/
+	#define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_ALARM
+	#define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_ALARM_OFFSET  256
+	#define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_ALARM_LEN     16
+	#define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_ALARM_DEFAULT 0x0
+	/*[field] RX_PWR_LOW_ALARM*/
+	#define SFP_DIAG_THRESHOLD_RX_PWR_LOW_ALARM
+	#define SFP_DIAG_THRESHOLD_RX_PWR_LOW_ALARM_OFFSET  272
+	#define SFP_DIAG_THRESHOLD_RX_PWR_LOW_ALARM_LEN     16
+	#define SFP_DIAG_THRESHOLD_RX_PWR_LOW_ALARM_DEFAULT 0x0
+	/*[field] RX_PWR_HIGH_WARNING*/
+	#define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_WARNING
+	#define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_WARNING_OFFSET  288
+	#define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_WARNING_LEN     16
+	#define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_WARNING_DEFAULT 0x0
+	/*[field] RX_PWR_LOW_WARNING*/
+	#define SFP_DIAG_THRESHOLD_RX_PWR_LOW_WARNING
+	#define SFP_DIAG_THRESHOLD_RX_PWR_LOW_WARNING_OFFSET  304
+	#define SFP_DIAG_THRESHOLD_RX_PWR_LOW_WARNING_LEN     16
+	#define SFP_DIAG_THRESHOLD_RX_PWR_LOW_WARNING_DEFAULT 0x0
+
+struct sfp_diag_threshold {
+	a_uint8_t  temp_high_alarm_0:8;
+	a_uint8_t  temp_high_alarm_1:8;
+	a_uint8_t  temp_low_alarm_0:8;
+	a_uint8_t  temp_low_alarm_1:8;
+	a_uint8_t  temp_high_warning_0:8;
+	a_uint8_t  temp_high_warning_1:8;
+	a_uint8_t  temp_low_warning_0:8;
+	a_uint8_t  temp_low_warning_1:8;
+	a_uint8_t  vol_high_alarm_0:8;
+	a_uint8_t  vol_high_alarm_1:8;
+	a_uint8_t  vol_low_alarm_0:8;
+	a_uint8_t  vol_low_alarm_1:8;
+	a_uint8_t  vol_high_warning_0:8;
+	a_uint8_t  vol_high_warning_1:8;
+	a_uint8_t  vol_low_warning_0:8;
+	a_uint8_t  vol_low_warning_1:8;
+	a_uint8_t  bias_high_alarm_0:8;
+	a_uint8_t  bias_high_alarm_1:8;
+	a_uint8_t  bias_low_alarm_0:8;
+	a_uint8_t  bias_low_alarm_1:8;
+	a_uint8_t  bias_high_warning_0:8;
+	a_uint8_t  bias_high_warning_1:8;
+	a_uint8_t  bias_low_warning_0:8;
+	a_uint8_t  bias_low_warning_1:8;
+	a_uint8_t  tx_pwr_high_alarm_0:8;
+	a_uint8_t  tx_pwr_high_alarm_1:8;
+	a_uint8_t  tx_pwr_low_alarm_0:8;
+	a_uint8_t  tx_pwr_low_alarm_1:8;
+	a_uint8_t  tx_pwr_high_warning_0:8;
+	a_uint8_t  tx_pwr_high_warning_1:8;
+	a_uint8_t  tx_pwr_low_warning_0:8;
+	a_uint8_t  tx_pwr_low_warning_1:8;
+	a_uint8_t  rx_pwr_high_alarm_0:8;
+	a_uint8_t  rx_pwr_high_alarm_1:8;
+	a_uint8_t  rx_pwr_low_alarm_0:8;
+	a_uint8_t  rx_pwr_low_alarm_1:8;
+	a_uint8_t  rx_pwr_high_warning_0:8;
+	a_uint8_t  rx_pwr_high_warning_1:8;
+	a_uint8_t  rx_pwr_low_warning_0:8;
+	a_uint8_t  rx_pwr_low_warning_1:8;
+};
+
+union sfp_diag_threshold_u {
+	a_uint8_t val[40];
+	struct sfp_diag_threshold bf;
+};
+
+/*[register] SFP_DIAG_CAL_CONST*/
+#define SFP_DIAG_CAL_CONST
+#define SFP_DIAG_CAL_CONST_ADDRESS 0x38
+#define SFP_DIAG_CAL_CONST_NUM     1
+#define SFP_DIAG_CAL_CONST_INC     0x24
+#define SFP_DIAG_CAL_CONST_TYPE    REG_TYPE_RO
+#define SFP_DIAG_CAL_CONST_DEFAULT 0x0
+	/*[field] RX_PWR_4*/
+	#define SFP_DIAG_CAL_CONST_RX_PWR_4
+	#define SFP_DIAG_CAL_CONST_RX_PWR_4_OFFSET  0
+	#define SFP_DIAG_CAL_CONST_RX_PWR_4_LEN     32
+	#define SFP_DIAG_CAL_CONST_RX_PWR_4_DEFAULT 0x0
+	/*[field] RX_PWR_3*/
+	#define SFP_DIAG_CAL_CONST_RX_PWR_3
+	#define SFP_DIAG_CAL_CONST_RX_PWR_3_OFFSET  32
+	#define SFP_DIAG_CAL_CONST_RX_PWR_3_LEN     32
+	#define SFP_DIAG_CAL_CONST_RX_PWR_3_DEFAULT 0x0
+	/*[field] RX_PWR_2*/
+	#define SFP_DIAG_CAL_CONST_RX_PWR_2
+	#define SFP_DIAG_CAL_CONST_RX_PWR_2_OFFSET  64
+	#define SFP_DIAG_CAL_CONST_RX_PWR_2_LEN     32
+	#define SFP_DIAG_CAL_CONST_RX_PWR_2_DEFAULT 0x0
+	/*[field] RX_PWR_1*/
+	#define SFP_DIAG_CAL_CONST_RX_PWR_1
+	#define SFP_DIAG_CAL_CONST_RX_PWR_1_OFFSET  96
+	#define SFP_DIAG_CAL_CONST_RX_PWR_1_LEN     32
+	#define SFP_DIAG_CAL_CONST_RX_PWR_1_DEFAULT 0x0
+	/*[field] RX_PWR_0*/
+	#define SFP_DIAG_CAL_CONST_RX_PWR_0
+	#define SFP_DIAG_CAL_CONST_RX_PWR_0_OFFSET  128
+	#define SFP_DIAG_CAL_CONST_RX_PWR_0_LEN     32
+	#define SFP_DIAG_CAL_CONST_RX_PWR_0_DEFAULT 0x0
+	/*[field] TX_I_SLOPE*/
+	#define SFP_DIAG_CAL_CONST_TX_I_SLOPE
+	#define SFP_DIAG_CAL_CONST_TX_I_SLOPE_OFFSET  160
+	#define SFP_DIAG_CAL_CONST_TX_I_SLOPE_LEN     16
+	#define SFP_DIAG_CAL_CONST_TX_I_SLOPE_DEFAULT 0x0
+	/*[field] TX_I_OFFSET*/
+	#define SFP_DIAG_CAL_CONST_TX_I_OFFSET
+	#define SFP_DIAG_CAL_CONST_TX_I_OFFSET_OFFSET  176
+	#define SFP_DIAG_CAL_CONST_TX_I_OFFSET_LEN     16
+	#define SFP_DIAG_CAL_CONST_TX_I_OFFSET_DEFAULT 0x0
+	/*[field] TX_PWR_SLOPE*/
+	#define SFP_DIAG_CAL_CONST_TX_PWR_SLOPE
+	#define SFP_DIAG_CAL_CONST_TX_PWR_SLOPE_OFFSET  192
+	#define SFP_DIAG_CAL_CONST_TX_PWR_SLOPE_LEN     16
+	#define SFP_DIAG_CAL_CONST_TX_PWR_SLOPE_DEFAULT 0x0
+	/*[field] TX_PWR_OFFSET*/
+	#define SFP_DIAG_CAL_CONST_TX_PWR_OFFSET
+	#define SFP_DIAG_CAL_CONST_TX_PWR_OFFSET_OFFSET  208
+	#define SFP_DIAG_CAL_CONST_TX_PWR_OFFSET_LEN     16
+	#define SFP_DIAG_CAL_CONST_TX_PWR_OFFSET_DEFAULT 0x0
+	/*[field] T_SLOPE*/
+	#define SFP_DIAG_CAL_CONST_T_SLOPE
+	#define SFP_DIAG_CAL_CONST_T_SLOPE_OFFSET  224
+	#define SFP_DIAG_CAL_CONST_T_SLOPE_LEN     16
+	#define SFP_DIAG_CAL_CONST_T_SLOPE_DEFAULT 0x0
+	/*[field] T_OFFSET*/
+	#define SFP_DIAG_CAL_CONST_T_OFFSET
+	#define SFP_DIAG_CAL_CONST_T_OFFSET_OFFSET  240
+	#define SFP_DIAG_CAL_CONST_T_OFFSET_LEN     16
+	#define SFP_DIAG_CAL_CONST_T_OFFSET_DEFAULT 0x0
+	/*[field] V_SLOPE*/
+	#define SFP_DIAG_CAL_CONST_V_SLOPE
+	#define SFP_DIAG_CAL_CONST_V_SLOPE_OFFSET  256
+	#define SFP_DIAG_CAL_CONST_V_SLOPE_LEN     16
+	#define SFP_DIAG_CAL_CONST_V_SLOPE_DEFAULT 0x0
+	/*[field] V_OFFSET*/
+	#define SFP_DIAG_CAL_CONST_V_OFFSET
+	#define SFP_DIAG_CAL_CONST_V_OFFSET_OFFSET  272
+	#define SFP_DIAG_CAL_CONST_V_OFFSET_LEN     16
+	#define SFP_DIAG_CAL_CONST_V_OFFSET_DEFAULT 0x0
+
+struct sfp_diag_cal_const {
+	a_uint8_t  rx_pwr_4_0:8;
+	a_uint8_t  rx_pwr_4_1:8;
+	a_uint8_t  rx_pwr_4_2:8;
+	a_uint8_t  rx_pwr_4_3:8;
+	a_uint8_t  rx_pwr_3_0:8;
+	a_uint8_t  rx_pwr_3_1:8;
+	a_uint8_t  rx_pwr_3_2:8;
+	a_uint8_t  rx_pwr_3_3:8;
+	a_uint8_t  rx_pwr_2_0:8;
+	a_uint8_t  rx_pwr_2_1:8;
+	a_uint8_t  rx_pwr_2_2:8;
+	a_uint8_t  rx_pwr_2_3:8;
+	a_uint8_t  rx_pwr_1_0:8;
+	a_uint8_t  rx_pwr_1_1:8;
+	a_uint8_t  rx_pwr_1_2:8;
+	a_uint8_t  rx_pwr_1_3:8;
+	a_uint8_t  rx_pwr_0_0:8;
+	a_uint8_t  rx_pwr_0_1:8;
+	a_uint8_t  rx_pwr_0_2:8;
+	a_uint8_t  rx_pwr_0_3:8;
+	a_uint8_t  tx_i_slope_0:8;
+	a_uint8_t  tx_i_slope_1:8;
+	a_uint8_t  tx_i_offset_0:8;
+	a_uint8_t  tx_i_offset_1:8;
+	a_uint8_t  tx_pwr_slope_0:8;
+	a_uint8_t  tx_pwr_slope_1:8;
+	a_uint8_t  tx_pwr_offset_0:8;
+	a_uint8_t  tx_pwr_offset_1:8;
+	a_uint8_t  t_slope_0:8;
+	a_uint8_t  t_slope_1:8;
+	a_uint8_t  t_offset_0:8;
+	a_uint8_t  t_offset_1:8;
+	a_uint8_t  v_slope_0:8;
+	a_uint8_t  v_slope_1:8;
+	a_uint8_t  v_offset_0:8;
+	a_uint8_t  v_offset_1:8;
+};
+
+union sfp_diag_cal_const_u {
+	a_uint8_t val[36];
+	struct sfp_diag_cal_const bf;
+};
+
+/*[register] SFP_DIAG_DMI*/
+#define SFP_DIAG_DMI
+#define SFP_DIAG_DMI_ADDRESS 0x5f
+#define SFP_DIAG_DMI_NUM     1
+#define SFP_DIAG_DMI_INC     0x1
+#define SFP_DIAG_DMI_TYPE    REG_TYPE_RO
+#define SFP_DIAG_DMI_DEFAULT 0x0
+	/*[field] CHECK_CODE*/
+	#define SFP_DIAG_DMI_CHECK_CODE
+	#define SFP_DIAG_DMI_CHECK_CODE_OFFSET  0
+	#define SFP_DIAG_DMI_CHECK_CODE_LEN     8
+	#define SFP_DIAG_DMI_CHECK_CODE_DEFAULT 0x0
+
+struct sfp_diag_dmi {
+	a_uint8_t  check_code:8;
+};
+
+union sfp_diag_dmi_u {
+	a_uint8_t val;
+	struct sfp_diag_dmi bf;
+};
+
+/*[register] SFP_DIAG_REALTIME*/
+#define SFP_DIAG_REALTIME
+#define SFP_DIAG_REALTIME_ADDRESS 0x60
+#define SFP_DIAG_REALTIME_NUM     1
+#define SFP_DIAG_REALTIME_INC     0xa
+#define SFP_DIAG_REALTIME_TYPE    REG_TYPE_RO
+#define SFP_DIAG_REALTIME_DEFAULT 0x0
+	/*[field] TMP*/
+	#define SFP_DIAG_REALTIME_TMP
+	#define SFP_DIAG_REALTIME_TMP_OFFSET  0
+	#define SFP_DIAG_REALTIME_TMP_LEN     16
+	#define SFP_DIAG_REALTIME_TMP_DEFAULT 0x0
+	/*[field] VCC*/
+	#define SFP_DIAG_REALTIME_VCC
+	#define SFP_DIAG_REALTIME_VCC_OFFSET  16
+	#define SFP_DIAG_REALTIME_VCC_LEN     16
+	#define SFP_DIAG_REALTIME_VCC_DEFAULT 0x0
+	/*[field] TX_BIAS*/
+	#define SFP_DIAG_REALTIME_TX_BIAS
+	#define SFP_DIAG_REALTIME_TX_BIAS_OFFSET  32
+	#define SFP_DIAG_REALTIME_TX_BIAS_LEN     16
+	#define SFP_DIAG_REALTIME_TX_BIAS_DEFAULT 0x0
+	/*[field] TX_PWR*/
+	#define SFP_DIAG_REALTIME_TX_PWR
+	#define SFP_DIAG_REALTIME_TX_PWR_OFFSET  48
+	#define SFP_DIAG_REALTIME_TX_PWR_LEN     16
+	#define SFP_DIAG_REALTIME_TX_PWR_DEFAULT 0x0
+	/*[field] RX_PWR*/
+	#define SFP_DIAG_REALTIME_RX_PWR
+	#define SFP_DIAG_REALTIME_RX_PWR_OFFSET  64
+	#define SFP_DIAG_REALTIME_RX_PWR_LEN     16
+	#define SFP_DIAG_REALTIME_RX_PWR_DEFAULT 0x0
+
+struct sfp_diag_realtime {
+	a_uint8_t  tmp_0:8;
+	a_uint8_t  tmp_1:8;
+	a_uint8_t  vcc_0:8;
+	a_uint8_t  vcc_1:8;
+	a_uint8_t  tx_bias_0:8;
+	a_uint8_t  tx_bias_1:8;
+	a_uint8_t  tx_pwr_0:8;
+	a_uint8_t  tx_pwr_1:8;
+	a_uint8_t  rx_pwr_0:8;
+	a_uint8_t  rx_pwr_1:8;
+};
+
+union sfp_diag_realtime_u {
+	a_uint8_t val[10];
+	struct sfp_diag_realtime bf;
+};
+
+/*[register] SFP_DIAG_OPTIONAL_CTRL_STATUS*/
+#define SFP_DIAG_OPTIONAL_CTRL_STATUS
+#define SFP_DIAG_OPTIONAL_CTRL_STATUS_ADDRESS 0x6e
+#define SFP_DIAG_OPTIONAL_CTRL_STATUS_NUM     1
+#define SFP_DIAG_OPTIONAL_CTRL_STATUS_INC     0x2
+#define SFP_DIAG_OPTIONAL_CTRL_STATUS_TYPE    REG_TYPE_RO
+#define SFP_DIAG_OPTIONAL_CTRL_STATUS_DEFAULT 0x0
+	/*[field] DATA_READY*/
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_DATA_READY
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_DATA_READY_OFFSET  0
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_DATA_READY_LEN     1
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_DATA_READY_DEFAULT 0x0
+	/*[field] RX_LOS*/
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_RX_LOS
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_RX_LOS_OFFSET  1
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_RX_LOS_LEN     1
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_RX_LOS_DEFAULT 0x0
+	/*[field] TX_FAULT*/
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_FAULT
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_FAULT_OFFSET  2
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_FAULT_LEN     1
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_FAULT_DEFAULT 0x0
+	/*[field] SOFT_RATE_SEL*/
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_RATE_SEL
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_RATE_SEL_OFFSET  3
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_RATE_SEL_LEN     1
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_RATE_SEL_DEFAULT 0x0
+	/*[field] RATE_SEL*/
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_RATE_SEL
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_RATE_SEL_OFFSET  4
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_RATE_SEL_LEN     1
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_RATE_SEL_DEFAULT 0x0
+	/*[field] RS*/
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_RS
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_RS_OFFSET  5
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_RS_LEN     1
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_RS_DEFAULT 0x0
+	/*[field] SOFT_TX_DISABLE_SEL*/
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_TX_DISABLE_SEL
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_TX_DISABLE_SEL_OFFSET  6
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_TX_DISABLE_SEL_LEN     1
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_TX_DISABLE_SEL_DEFAULT 0x0
+	/*[field] TX_DISABLE*/
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_DISABLE
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_DISABLE_OFFSET  7
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_DISABLE_LEN     1
+	#define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_DISABLE_DEFAULT 0x0
+
+struct sfp_diag_optional_ctrl_status {
+	a_uint8_t  data_ready:1;
+	a_uint8_t  rx_los:1;
+	a_uint8_t  tx_fault:1;
+	a_uint8_t  soft_rate_sel:1;
+	a_uint8_t  rate_sel:1;
+	a_uint8_t  rs:1;
+	a_uint8_t  soft_tx_disable_sel:1;
+	a_uint8_t  tx_disable:1;
+	a_uint8_t  _reserved0:8;
+};
+
+union sfp_diag_optional_ctrl_status_u {
+	a_uint8_t val[2];
+	struct sfp_diag_optional_ctrl_status bf;
+};
+
+/*[register] SFP_DIAG_FLAG*/
+#define SFP_DIAG_FLAG
+#define SFP_DIAG_FLAG_ADDRESS 0x70
+#define SFP_DIAG_FLAG_NUM     1
+#define SFP_DIAG_FLAG_INC     0x6
+#define SFP_DIAG_FLAG_TYPE    REG_TYPE_RO
+#define SFP_DIAG_FLAG_DEFAULT 0x0
+	/*[field] TX_PWR_LOW_ALARM*/
+	#define SFP_DIAG_FLAG_TX_PWR_LOW_ALARM
+	#define SFP_DIAG_FLAG_TX_PWR_LOW_ALARM_OFFSET  0
+	#define SFP_DIAG_FLAG_TX_PWR_LOW_ALARM_LEN     1
+	#define SFP_DIAG_FLAG_TX_PWR_LOW_ALARM_DEFAULT 0x0
+	/*[field] TX_PWR_HIGH_ALARM*/
+	#define SFP_DIAG_FLAG_TX_PWR_HIGH_ALARM
+	#define SFP_DIAG_FLAG_TX_PWR_HIGH_ALARM_OFFSET  1
+	#define SFP_DIAG_FLAG_TX_PWR_HIGH_ALARM_LEN     1
+	#define SFP_DIAG_FLAG_TX_PWR_HIGH_ALARM_DEFAULT 0x0
+	/*[field] TX_BIAS_LOW_ALARM*/
+	#define SFP_DIAG_FLAG_TX_BIAS_LOW_ALARM
+	#define SFP_DIAG_FLAG_TX_BIAS_LOW_ALARM_OFFSET  2
+	#define SFP_DIAG_FLAG_TX_BIAS_LOW_ALARM_LEN     1
+	#define SFP_DIAG_FLAG_TX_BIAS_LOW_ALARM_DEFAULT 0x0
+	/*[field] TX_BIAS_HIGH_ALARM*/
+	#define SFP_DIAG_FLAG_TX_BIAS_HIGH_ALARM
+	#define SFP_DIAG_FLAG_TX_BIAS_HIGH_ALARM_OFFSET  3
+	#define SFP_DIAG_FLAG_TX_BIAS_HIGH_ALARM_LEN     1
+	#define SFP_DIAG_FLAG_TX_BIAS_HIGH_ALARM_DEFAULT 0x0
+	/*[field] VCC_LOW_ALARM*/
+	#define SFP_DIAG_FLAG_VCC_LOW_ALARM
+	#define SFP_DIAG_FLAG_VCC_LOW_ALARM_OFFSET  4
+	#define SFP_DIAG_FLAG_VCC_LOW_ALARM_LEN     1
+	#define SFP_DIAG_FLAG_VCC_LOW_ALARM_DEFAULT 0x0
+	/*[field] VCC_HIGH_ALARM*/
+	#define SFP_DIAG_FLAG_VCC_HIGH_ALARM
+	#define SFP_DIAG_FLAG_VCC_HIGH_ALARM_OFFSET  5
+	#define SFP_DIAG_FLAG_VCC_HIGH_ALARM_LEN     1
+	#define SFP_DIAG_FLAG_VCC_HIGH_ALARM_DEFAULT 0x0
+	/*[field] TMP_LOW_ALARM*/
+	#define SFP_DIAG_FLAG_TMP_LOW_ALARM
+	#define SFP_DIAG_FLAG_TMP_LOW_ALARM_OFFSET  6
+	#define SFP_DIAG_FLAG_TMP_LOW_ALARM_LEN     1
+	#define SFP_DIAG_FLAG_TMP_LOW_ALARM_DEFAULT 0x0
+	/*[field] TMP_HIGH_ALARM*/
+	#define SFP_DIAG_FLAG_TMP_HIGH_ALARM
+	#define SFP_DIAG_FLAG_TMP_HIGH_ALARM_OFFSET  7
+	#define SFP_DIAG_FLAG_TMP_HIGH_ALARM_LEN     1
+	#define SFP_DIAG_FLAG_TMP_HIGH_ALARM_DEFAULT 0x0
+	/*[field] RX_PWR_LOW_ALARM*/
+	#define SFP_DIAG_FLAG_RX_PWR_LOW_ALARM
+	#define SFP_DIAG_FLAG_RX_PWR_LOW_ALARM_OFFSET  14
+	#define SFP_DIAG_FLAG_RX_PWR_LOW_ALARM_LEN     1
+	#define SFP_DIAG_FLAG_RX_PWR_LOW_ALARM_DEFAULT 0x0
+	/*[field] RX_PWR_HIGH_ALARM*/
+	#define SFP_DIAG_FLAG_RX_PWR_HIGH_ALARM
+	#define SFP_DIAG_FLAG_RX_PWR_HIGH_ALARM_OFFSET  15
+	#define SFP_DIAG_FLAG_RX_PWR_HIGH_ALARM_LEN     1
+	#define SFP_DIAG_FLAG_RX_PWR_HIGH_ALARM_DEFAULT 0x0
+	/*[field] UNALLOCATED*/
+	#define SFP_DIAG_FLAG_UNALLOCATED
+	#define SFP_DIAG_FLAG_UNALLOCATED_OFFSET  16
+	#define SFP_DIAG_FLAG_UNALLOCATED_LEN     16
+	#define SFP_DIAG_FLAG_UNALLOCATED_DEFAULT 0x0
+	/*[field] TX_PWR_LOW_WARNING*/
+	#define SFP_DIAG_FLAG_TX_PWR_LOW_WARNING
+	#define SFP_DIAG_FLAG_TX_PWR_LOW_WARNING_OFFSET  32
+	#define SFP_DIAG_FLAG_TX_PWR_LOW_WARNING_LEN     1
+	#define SFP_DIAG_FLAG_TX_PWR_LOW_WARNING_DEFAULT 0x0
+	/*[field] TX_PWR_HIGH_WARNING*/
+	#define SFP_DIAG_FLAG_TX_PWR_HIGH_WARNING
+	#define SFP_DIAG_FLAG_TX_PWR_HIGH_WARNING_OFFSET  33
+	#define SFP_DIAG_FLAG_TX_PWR_HIGH_WARNING_LEN     1
+	#define SFP_DIAG_FLAG_TX_PWR_HIGH_WARNING_DEFAULT 0x0
+	/*[field] TX_BIAS_LOW_WARNING*/
+	#define SFP_DIAG_FLAG_TX_BIAS_LOW_WARNING
+	#define SFP_DIAG_FLAG_TX_BIAS_LOW_WARNING_OFFSET  34
+	#define SFP_DIAG_FLAG_TX_BIAS_LOW_WARNING_LEN     1
+	#define SFP_DIAG_FLAG_TX_BIAS_LOW_WARNING_DEFAULT 0x0
+	/*[field] TX_BIAS_HIGH_WARNING*/
+	#define SFP_DIAG_FLAG_TX_BIAS_HIGH_WARNING
+	#define SFP_DIAG_FLAG_TX_BIAS_HIGH_WARNING_OFFSET  35
+	#define SFP_DIAG_FLAG_TX_BIAS_HIGH_WARNING_LEN     1
+	#define SFP_DIAG_FLAG_TX_BIAS_HIGH_WARNING_DEFAULT 0x0
+	/*[field] VCC_LOW_WARNING*/
+	#define SFP_DIAG_FLAG_VCC_LOW_WARNING
+	#define SFP_DIAG_FLAG_VCC_LOW_WARNING_OFFSET  36
+	#define SFP_DIAG_FLAG_VCC_LOW_WARNING_LEN     1
+	#define SFP_DIAG_FLAG_VCC_LOW_WARNING_DEFAULT 0x0
+	/*[field] VCC_HIGH_WARNING*/
+	#define SFP_DIAG_FLAG_VCC_HIGH_WARNING
+	#define SFP_DIAG_FLAG_VCC_HIGH_WARNING_OFFSET  37
+	#define SFP_DIAG_FLAG_VCC_HIGH_WARNING_LEN     1
+	#define SFP_DIAG_FLAG_VCC_HIGH_WARNING_DEFAULT 0x0
+	/*[field] TMP_LOW_WARNING*/
+	#define SFP_DIAG_FLAG_TMP_LOW_WARNING
+	#define SFP_DIAG_FLAG_TMP_LOW_WARNING_OFFSET  38
+	#define SFP_DIAG_FLAG_TMP_LOW_WARNING_LEN     1
+	#define SFP_DIAG_FLAG_TMP_LOW_WARNING_DEFAULT 0x0
+	/*[field] TMP_HIGH_WARNING*/
+	#define SFP_DIAG_FLAG_TMP_HIGH_WARNING
+	#define SFP_DIAG_FLAG_TMP_HIGH_WARNING_OFFSET  39
+	#define SFP_DIAG_FLAG_TMP_HIGH_WARNING_LEN     1
+	#define SFP_DIAG_FLAG_TMP_HIGH_WARNING_DEFAULT 0x0
+	/*[field] RX_PWR_LOW_WARNING*/
+	#define SFP_DIAG_FLAG_RX_PWR_LOW_WARNING
+	#define SFP_DIAG_FLAG_RX_PWR_LOW_WARNING_OFFSET  46
+	#define SFP_DIAG_FLAG_RX_PWR_LOW_WARNING_LEN     1
+	#define SFP_DIAG_FLAG_RX_PWR_LOW_WARNING_DEFAULT 0x0
+	/*[field] RX_PWR_HIGH_WARNING*/
+	#define SFP_DIAG_FLAG_RX_PWR_HIGH_WARNING
+	#define SFP_DIAG_FLAG_RX_PWR_HIGH_WARNING_OFFSET  47
+	#define SFP_DIAG_FLAG_RX_PWR_HIGH_WARNING_LEN     1
+	#define SFP_DIAG_FLAG_RX_PWR_HIGH_WARNING_DEFAULT 0x0
+
+struct sfp_diag_flag {
+	a_uint8_t  tx_pwr_low_alarm:1;
+	a_uint8_t  tx_pwr_high_alarm:1;
+	a_uint8_t  tx_bias_low_alarm:1;
+	a_uint8_t  tx_bias_high_alarm:1;
+	a_uint8_t  vcc_low_alarm:1;
+	a_uint8_t  vcc_high_alarm:1;
+	a_uint8_t  tmp_low_alarm:1;
+	a_uint8_t  tmp_high_alarm:1;
+	a_uint8_t  _reserved0:6;
+	a_uint8_t  rx_pwr_low_alarm:1;
+	a_uint8_t  rx_pwr_high_alarm:1;
+	a_uint8_t  unallocated_0:8;
+	a_uint8_t  unallocated_1:8;
+	a_uint8_t  tx_pwr_low_warning:1;
+	a_uint8_t  tx_pwr_high_warning:1;
+	a_uint8_t  tx_bias_low_warning:1;
+	a_uint8_t  tx_bias_high_warning:1;
+	a_uint8_t  vcc_low_warning:1;
+	a_uint8_t  vcc_high_warning:1;
+	a_uint8_t  tmp_low_warning:1;
+	a_uint8_t  tmp_high_warning:1;
+	a_uint8_t  _reserved1:6;
+	a_uint8_t  rx_pwr_low_warning:1;
+	a_uint8_t  rx_pwr_high_warning:1;
+};
+
+union sfp_diag_flag_u {
+	a_uint8_t val[6];
+	struct sfp_diag_flag bf;
+};
+
+/*[register] SFP_DIAG_EXTENDED_CTRL_STATUS*/
+#define SFP_DIAG_EXTENDED_CTRL_STATUS
+#define SFP_DIAG_EXTENDED_CTRL_STATUS_ADDRESS 0x76
+#define SFP_DIAG_EXTENDED_CTRL_STATUS_NUM     1
+#define SFP_DIAG_EXTENDED_CTRL_STATUS_INC     0x2
+#define SFP_DIAG_EXTENDED_CTRL_STATUS_TYPE    REG_TYPE_RO
+#define SFP_DIAG_EXTENDED_CTRL_STATUS_DEFAULT 0x0
+	/*[field] PWR_LEVEL_SEL*/
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_SEL
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_SEL_OFFSET  0
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_SEL_LEN     1
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_SEL_DEFAULT 0x0
+	/*[field] PWR_LEVEL_OP_STATE*/
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_OP_STATE
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_OP_STATE_OFFSET  1
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_OP_STATE_LEN     1
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_OP_STATE_DEFAULT 0x0
+	/*[field] SOFT_RS_SEL*/
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_SOFT_RS_SEL
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_SOFT_RS_SEL_OFFSET  3
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_SOFT_RS_SEL_LEN     1
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_SOFT_RS_SEL_DEFAULT 0x0
+	/*[field] UNALLOCATED*/
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_UNALLOCATED
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_UNALLOCATED_OFFSET  4
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_UNALLOCATED_LEN     12
+	#define SFP_DIAG_EXTENDED_CTRL_STATUS_UNALLOCATED_DEFAULT 0x0
+
+struct sfp_diag_extended_ctrl_status {
+	a_uint8_t  pwr_level_sel:1;
+	a_uint8_t  pwr_level_op_state:1;
+	a_uint8_t  _reserved0:1;
+	a_uint8_t  soft_rs_sel:1;
+	a_uint8_t  unallocated_0:4;
+	a_uint8_t  unallocated_1:8;
+};
+
+union sfp_diag_extended_ctrl_status_u {
+	a_uint8_t val[2];
+	struct sfp_diag_extended_ctrl_status bf;
+};
+
+#endif
diff --git a/qca-ssdk/include/hsl/shiva/shiva_acl.h b/qca-ssdk/include/hsl/shiva/shiva_acl.h
new file mode 100755
index 0000000..7ad6d95
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_acl.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_acl SHIVA_ACL
+ * @{
+ */
+#ifndef _SHIVA_ACL_H_
+#define _SHIVA_ACL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_acl.h"
+
+    sw_error_t
+    shiva_acl_init(a_uint32_t dev_id);
+
+    sw_error_t
+    shiva_acl_reset(a_uint32_t dev_id);
+
+#ifdef IN_ACL
+#define SHIVA_ACL_INIT(rv, dev_id) \
+    { \
+        rv = shiva_acl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+
+#define SHIVA_ACL_RESET(rv, dev_id) \
+    { \
+        rv = shiva_acl_reset(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define SHIVA_ACL_INIT(rv, dev_id)
+#define SHIVA_ACL_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    shiva_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+                         a_uint32_t list_pri);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+                       a_uint32_t rule_id, a_uint32_t rule_nr,
+                       fal_acl_rule_t * rule);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+                          a_uint32_t rule_id, a_uint32_t rule_nr);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+                         a_uint32_t rule_id, fal_acl_rule_t * rule);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                        fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                        a_uint32_t obj_idx);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                          fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                          a_uint32_t obj_idx);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_acl_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_acl_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_acl_list_dump(a_uint32_t dev_id);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_acl_rule_dump(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SHIVA_ACL_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/shiva/shiva_api.h b/qca-ssdk/include/hsl/shiva/shiva_api.h
new file mode 100755
index 0000000..cdc428d
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_api.h
@@ -0,0 +1,609 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _SHIVA_API_H_
+#define _SHIVA_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#ifdef IN_PORTCONTROL
+#define PORTCONTROL_API \
+    SW_API_DEF(SW_API_PT_DUPLEX_GET, shiva_port_duplex_get), \
+    SW_API_DEF(SW_API_PT_DUPLEX_SET, shiva_port_duplex_set), \
+    SW_API_DEF(SW_API_PT_SPEED_GET, shiva_port_speed_get), \
+    SW_API_DEF(SW_API_PT_SPEED_SET, shiva_port_speed_set), \
+    SW_API_DEF(SW_API_PT_AN_GET, shiva_port_autoneg_status_get), \
+    SW_API_DEF(SW_API_PT_AN_ENABLE, shiva_port_autoneg_enable), \
+    SW_API_DEF(SW_API_PT_AN_RESTART, shiva_port_autoneg_restart), \
+    SW_API_DEF(SW_API_PT_AN_ADV_GET, shiva_port_autoneg_adv_get), \
+    SW_API_DEF(SW_API_PT_AN_ADV_SET, shiva_port_autoneg_adv_set), \
+    SW_API_DEF(SW_API_PT_HDR_SET, shiva_port_hdr_status_set), \
+    SW_API_DEF(SW_API_PT_HDR_GET, shiva_port_hdr_status_get), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_SET, shiva_port_flowctrl_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_GET, shiva_port_flowctrl_get), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, shiva_port_flowctrl_forcemode_set), \
+    SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, shiva_port_flowctrl_forcemode_get), \
+    SW_API_DEF(SW_API_PT_POWERSAVE_SET, shiva_port_powersave_set), \
+    SW_API_DEF(SW_API_PT_POWERSAVE_GET, shiva_port_powersave_get), \
+    SW_API_DEF(SW_API_PT_HIBERNATE_SET, shiva_port_hibernate_set), \
+    SW_API_DEF(SW_API_PT_HIBERNATE_GET, shiva_port_hibernate_get), \
+    SW_API_DEF(SW_API_PT_CDT, shiva_port_cdt),
+
+
+#define PORTCONTROL_API_PARAM \
+    SW_API_DESC(SW_API_PT_DUPLEX_GET) \
+    SW_API_DESC(SW_API_PT_DUPLEX_SET) \
+    SW_API_DESC(SW_API_PT_SPEED_GET)  \
+    SW_API_DESC(SW_API_PT_SPEED_SET)  \
+    SW_API_DESC(SW_API_PT_AN_GET)  \
+    SW_API_DESC(SW_API_PT_AN_ENABLE)   \
+    SW_API_DESC(SW_API_PT_AN_RESTART)  \
+    SW_API_DESC(SW_API_PT_AN_ADV_GET)  \
+    SW_API_DESC(SW_API_PT_AN_ADV_SET)  \
+    SW_API_DESC(SW_API_PT_HDR_SET)  \
+    SW_API_DESC(SW_API_PT_HDR_GET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_SET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_GET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \
+    SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
+    SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
+    SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
+    SW_API_DESC(SW_API_PT_HIBERNATE_GET) \
+    SW_API_DESC(SW_API_PT_CDT)
+
+#else
+#define PORTCONTROL_API
+#define PORTCONTROL_API_PARAM
+#endif
+
+#ifdef IN_VLAN
+#define VLAN_API \
+    SW_API_DEF(SW_API_VLAN_ADD, shiva_vlan_create), \
+    SW_API_DEF(SW_API_VLAN_DEL, shiva_vlan_delete), \
+    SW_API_DEF(SW_API_VLAN_MEM_UPDATE, shiva_vlan_member_update), \
+    SW_API_DEF(SW_API_VLAN_FIND, shiva_vlan_find), \
+    SW_API_DEF(SW_API_VLAN_NEXT, shiva_vlan_next), \
+    SW_API_DEF(SW_API_VLAN_APPEND, shiva_vlan_entry_append), \
+    SW_API_DEF(SW_API_VLAN_FLUSH, shiva_vlan_flush),
+
+#define VLAN_API_PARAM \
+    SW_API_DESC(SW_API_VLAN_ADD)  \
+    SW_API_DESC(SW_API_VLAN_DEL)  \
+    SW_API_DESC(SW_API_VLAN_MEM_UPDATE)  \
+    SW_API_DESC(SW_API_VLAN_FIND)  \
+    SW_API_DESC(SW_API_VLAN_NEXT)  \
+    SW_API_DESC(SW_API_VLAN_APPEND) \
+    SW_API_DESC(SW_API_VLAN_FLUSH)
+#else
+#define VLAN_API
+#define VLAN_API_PARAM
+#endif
+
+#ifdef IN_PORTVLAN
+#define PORTVLAN_API \
+    SW_API_DEF(SW_API_PT_ING_MODE_GET, shiva_port_1qmode_get), \
+    SW_API_DEF(SW_API_PT_ING_MODE_SET, shiva_port_1qmode_set), \
+    SW_API_DEF(SW_API_PT_EG_MODE_GET, shiva_port_egvlanmode_get), \
+    SW_API_DEF(SW_API_PT_EG_MODE_SET, shiva_port_egvlanmode_set), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, shiva_portvlan_member_add), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, shiva_portvlan_member_del), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, shiva_portvlan_member_update), \
+    SW_API_DEF(SW_API_PT_VLAN_MEM_GET, shiva_portvlan_member_get), \
+    SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, shiva_port_force_default_vid_set), \
+    SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, shiva_port_force_default_vid_get), \
+    SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, shiva_port_force_portvlan_set), \
+    SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, shiva_port_force_portvlan_get), \
+    SW_API_DEF(SW_API_NESTVLAN_TPID_SET, shiva_nestvlan_tpid_set), \
+    SW_API_DEF(SW_API_NESTVLAN_TPID_GET, shiva_nestvlan_tpid_get), \
+    SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, shiva_port_invlan_mode_set), \
+    SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, shiva_port_invlan_mode_get), \
+    SW_API_DEF(SW_API_PT_TLS_SET, shiva_port_tls_set), \
+    SW_API_DEF(SW_API_PT_TLS_GET, shiva_port_tls_get), \
+    SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, shiva_port_pri_propagation_set), \
+    SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, shiva_port_pri_propagation_get), \
+    SW_API_DEF(SW_API_PT_DEF_SVID_SET, shiva_port_default_svid_set), \
+    SW_API_DEF(SW_API_PT_DEF_SVID_GET, shiva_port_default_svid_get), \
+    SW_API_DEF(SW_API_PT_DEF_CVID_SET, shiva_port_default_cvid_set), \
+    SW_API_DEF(SW_API_PT_DEF_CVID_GET, shiva_port_default_cvid_get), \
+    SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_SET, shiva_port_vlan_propagation_set), \
+    SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_GET, shiva_port_vlan_propagation_get), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, shiva_port_vlan_trans_add), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_DEL, shiva_port_vlan_trans_del), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_GET, shiva_port_vlan_trans_get), \
+    SW_API_DEF(SW_API_QINQ_MODE_SET, shiva_qinq_mode_set), \
+    SW_API_DEF(SW_API_QINQ_MODE_GET, shiva_qinq_mode_get), \
+    SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, shiva_port_qinq_role_set), \
+    SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, shiva_port_qinq_role_get), \
+    SW_API_DEF(SW_API_PT_VLAN_TRANS_ITERATE, shiva_port_vlan_trans_iterate),
+
+#define PORTVLAN_API_PARAM \
+    SW_API_DESC(SW_API_PT_ING_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_ING_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_EG_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_EG_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE)  \
+    SW_API_DESC(SW_API_PT_VLAN_MEM_GET)     \
+    SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET)    \
+    SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET)    \
+    SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET)   \
+    SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET)   \
+    SW_API_DESC(SW_API_NESTVLAN_TPID_SET)    \
+    SW_API_DESC(SW_API_NESTVLAN_TPID_GET)    \
+    SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET)    \
+    SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET)    \
+    SW_API_DESC(SW_API_PT_TLS_SET)    \
+    SW_API_DESC(SW_API_PT_TLS_GET)    \
+    SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET)    \
+    SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET)    \
+    SW_API_DESC(SW_API_PT_DEF_SVID_SET)    \
+    SW_API_DESC(SW_API_PT_DEF_SVID_GET)    \
+    SW_API_DESC(SW_API_PT_DEF_CVID_SET)    \
+    SW_API_DESC(SW_API_PT_DEF_CVID_GET)    \
+    SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_SET)    \
+    SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_GET)    \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD)  \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_DEL)  \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_GET)  \
+    SW_API_DESC(SW_API_QINQ_MODE_SET)      \
+    SW_API_DESC(SW_API_QINQ_MODE_GET)      \
+    SW_API_DESC(SW_API_PT_QINQ_ROLE_SET)   \
+    SW_API_DESC(SW_API_PT_QINQ_ROLE_GET)   \
+    SW_API_DESC(SW_API_PT_VLAN_TRANS_ITERATE)
+#else
+#define PORTVLAN_API
+#define PORTVLAN_API_PARAM
+#endif
+
+#ifdef IN_FDB
+#define FDB_API \
+    SW_API_DEF(SW_API_FDB_ADD, shiva_fdb_add), \
+    SW_API_DEF(SW_API_FDB_DELALL, shiva_fdb_del_all), \
+    SW_API_DEF(SW_API_FDB_DELPORT,shiva_fdb_del_by_port), \
+    SW_API_DEF(SW_API_FDB_DELMAC, shiva_fdb_del_by_mac), \
+    SW_API_DEF(SW_API_FDB_FIRST,  shiva_fdb_first), \
+    SW_API_DEF(SW_API_FDB_FIND,   shiva_fdb_find), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_SET,   shiva_fdb_port_learn_set), \
+    SW_API_DEF(SW_API_FDB_PT_LEARN_GET,   shiva_fdb_port_learn_get), \
+    SW_API_DEF(SW_API_FDB_AGE_CTRL_SET,   shiva_fdb_age_ctrl_set), \
+    SW_API_DEF(SW_API_FDB_AGE_CTRL_GET,   shiva_fdb_age_ctrl_get), \
+    SW_API_DEF(SW_API_FDB_AGE_TIME_SET,   shiva_fdb_age_time_set), \
+    SW_API_DEF(SW_API_FDB_AGE_TIME_GET,   shiva_fdb_age_time_get), \
+    SW_API_DEF(SW_API_FDB_ITERATE,        shiva_fdb_iterate),
+
+#define FDB_API_PARAM \
+    SW_API_DESC(SW_API_FDB_ADD)  \
+    SW_API_DESC(SW_API_FDB_DELALL)  \
+    SW_API_DESC(SW_API_FDB_DELPORT) \
+    SW_API_DESC(SW_API_FDB_DELMAC)  \
+    SW_API_DESC(SW_API_FDB_FIRST)   \
+    SW_API_DESC(SW_API_FDB_FIND)    \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \
+    SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \
+    SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \
+    SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \
+    SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \
+    SW_API_DESC(SW_API_FDB_AGE_TIME_GET) \
+    SW_API_DESC(SW_API_FDB_ITERATE)
+#else
+#define FDB_API
+#define FDB_API_PARAM
+#endif
+
+#ifdef IN_ACL
+#define ACL_API \
+    SW_API_DEF(SW_API_ACL_LIST_CREAT, shiva_acl_list_creat), \
+    SW_API_DEF(SW_API_ACL_LIST_DESTROY, shiva_acl_list_destroy), \
+    SW_API_DEF(SW_API_ACL_RULE_ADD, shiva_acl_rule_add), \
+    SW_API_DEF(SW_API_ACL_RULE_DELETE, shiva_acl_rule_delete), \
+    SW_API_DEF(SW_API_ACL_RULE_QUERY, shiva_acl_rule_query), \
+    SW_API_DEF(SW_API_ACL_LIST_BIND, shiva_acl_list_bind), \
+    SW_API_DEF(SW_API_ACL_LIST_UNBIND, shiva_acl_list_unbind), \
+    SW_API_DEF(SW_API_ACL_STATUS_SET, shiva_acl_status_set), \
+    SW_API_DEF(SW_API_ACL_STATUS_GET, shiva_acl_status_get), \
+    SW_API_DEF(SW_API_ACL_LIST_DUMP, shiva_acl_list_dump), \
+    SW_API_DEF(SW_API_ACL_RULE_DUMP, shiva_acl_rule_dump),
+
+#define ACL_API_PARAM \
+    SW_API_DESC(SW_API_ACL_LIST_CREAT)   \
+    SW_API_DESC(SW_API_ACL_LIST_DESTROY) \
+    SW_API_DESC(SW_API_ACL_RULE_ADD)     \
+    SW_API_DESC(SW_API_ACL_RULE_DELETE)  \
+    SW_API_DESC(SW_API_ACL_RULE_QUERY)   \
+    SW_API_DESC(SW_API_ACL_LIST_BIND)    \
+    SW_API_DESC(SW_API_ACL_LIST_UNBIND)  \
+    SW_API_DESC(SW_API_ACL_STATUS_SET)   \
+    SW_API_DESC(SW_API_ACL_STATUS_GET)   \
+    SW_API_DESC(SW_API_ACL_LIST_DUMP)    \
+    SW_API_DESC(SW_API_ACL_RULE_DUMP)
+#else
+#define ACL_API
+#define ACL_API_PARAM
+#endif
+
+#ifdef IN_QOS
+#define QOS_API \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, shiva_qos_queue_tx_buf_status_set), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, shiva_qos_queue_tx_buf_status_get), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, shiva_qos_queue_tx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, shiva_qos_queue_tx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, shiva_qos_port_tx_buf_status_set), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, shiva_qos_port_tx_buf_status_get), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, shiva_qos_port_tx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, shiva_qos_port_tx_buf_nr_get), \
+    SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, shiva_qos_port_rx_buf_nr_set), \
+    SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, shiva_qos_port_rx_buf_nr_get), \
+    SW_API_DEF(SW_API_COSMAP_UP_QU_SET, shiva_cosmap_up_queue_set), \
+    SW_API_DEF(SW_API_COSMAP_UP_QU_GET, shiva_cosmap_up_queue_get), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_QU_SET, shiva_cosmap_dscp_queue_set), \
+    SW_API_DEF(SW_API_COSMAP_DSCP_QU_GET, shiva_cosmap_dscp_queue_get), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_SET, shiva_qos_port_mode_set), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_GET, shiva_qos_port_mode_get), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, shiva_qos_port_mode_pri_set), \
+    SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, shiva_qos_port_mode_pri_get), \
+    SW_API_DEF(SW_API_QOS_PORT_DEF_UP_SET, shiva_qos_port_default_up_set), \
+    SW_API_DEF(SW_API_QOS_PORT_DEF_UP_GET, shiva_qos_port_default_up_get), \
+    SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, shiva_qos_port_sch_mode_set), \
+    SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, shiva_qos_port_sch_mode_get),
+
+#define QOS_API_PARAM \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \
+    SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \
+    SW_API_DESC(SW_API_COSMAP_UP_QU_SET) \
+    SW_API_DESC(SW_API_COSMAP_UP_QU_GET) \
+    SW_API_DESC(SW_API_COSMAP_DSCP_QU_SET) \
+    SW_API_DESC(SW_API_COSMAP_DSCP_QU_GET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_SET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_GET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \
+    SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \
+    SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \
+    SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET)
+#else
+#define QOS_API
+#define QOS_API_PARAM
+#endif
+
+#ifdef IN_IGMP
+#define IGMP_API \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, shiva_port_igmps_status_set), \
+    SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, shiva_port_igmps_status_get), \
+    SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, shiva_igmp_mld_cmd_set), \
+    SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, shiva_igmp_mld_cmd_get), \
+    SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, shiva_port_igmp_mld_join_set), \
+    SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, shiva_port_igmp_mld_join_get), \
+    SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, shiva_port_igmp_mld_leave_set), \
+    SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, shiva_port_igmp_mld_leave_get), \
+    SW_API_DEF(SW_API_IGMP_RP_SET, shiva_igmp_mld_rp_set), \
+    SW_API_DEF(SW_API_IGMP_RP_GET, shiva_igmp_mld_rp_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, shiva_igmp_mld_entry_creat_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, shiva_igmp_mld_entry_creat_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, shiva_igmp_mld_entry_static_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, shiva_igmp_mld_entry_static_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, shiva_igmp_mld_entry_leaky_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, shiva_igmp_mld_entry_leaky_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, shiva_igmp_mld_entry_v3_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, shiva_igmp_mld_entry_v3_get), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, shiva_igmp_mld_entry_queue_set), \
+    SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, shiva_igmp_mld_entry_queue_get),
+
+#define IGMP_API_PARAM \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
+    SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
+    SW_API_DESC(SW_API_IGMP_MLD_CMD_SET)  \
+    SW_API_DESC(SW_API_IGMP_MLD_CMD_GET)  \
+    SW_API_DESC(SW_API_IGMP_PT_JOIN_SET)  \
+    SW_API_DESC(SW_API_IGMP_PT_JOIN_GET)  \
+    SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \
+    SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \
+    SW_API_DESC(SW_API_IGMP_RP_SET)  \
+    SW_API_DESC(SW_API_IGMP_RP_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \
+    SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET)  \
+    SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET)
+#else
+#define IGMP_API
+#define IGMP_API_PARAM
+#endif
+
+#ifdef IN_LEAKY
+#define LEAKY_API \
+    SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, shiva_uc_leaky_mode_set), \
+    SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, shiva_uc_leaky_mode_get), \
+    SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, shiva_mc_leaky_mode_set), \
+    SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, shiva_mc_leaky_mode_get), \
+    SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, shiva_port_arp_leaky_set), \
+    SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, shiva_port_arp_leaky_get), \
+    SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, shiva_port_uc_leaky_set), \
+    SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, shiva_port_uc_leaky_get), \
+    SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, shiva_port_mc_leaky_set), \
+    SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, shiva_port_mc_leaky_get),
+
+#define LEAKY_API_PARAM \
+    SW_API_DESC(SW_API_UC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_UC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_MC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_MC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \
+    SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \
+    SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET)  \
+    SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET)  \
+    SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET)
+#else
+#define LEAKY_API
+#define LEAKY_API_PARAM
+#endif
+
+#ifdef IN_MIRROR
+#define MIRROR_API \
+    SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, shiva_mirr_analysis_port_set), \
+    SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, shiva_mirr_analysis_port_get), \
+    SW_API_DEF(SW_API_MIRROR_IN_PT_SET, shiva_mirr_port_in_set), \
+    SW_API_DEF(SW_API_MIRROR_IN_PT_GET, shiva_mirr_port_in_get), \
+    SW_API_DEF(SW_API_MIRROR_EG_PT_SET, shiva_mirr_port_eg_set), \
+    SW_API_DEF(SW_API_MIRROR_EG_PT_GET, shiva_mirr_port_eg_get),
+
+#define MIRROR_API_PARAM \
+    SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET)  \
+    SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET)  \
+    SW_API_DESC(SW_API_MIRROR_IN_PT_SET)  \
+    SW_API_DESC(SW_API_MIRROR_IN_PT_GET)  \
+    SW_API_DESC(SW_API_MIRROR_EG_PT_SET)  \
+    SW_API_DESC(SW_API_MIRROR_EG_PT_GET)
+#else
+#define MIRROR_API
+#define MIRROR_API_PARAM
+#endif
+
+#ifdef IN_RATE
+#define RATE_API \
+    SW_API_DEF(SW_API_RATE_QU_EGRL_SET, shiva_rate_queue_egrl_set), \
+    SW_API_DEF(SW_API_RATE_QU_EGRL_GET, shiva_rate_queue_egrl_get), \
+    SW_API_DEF(SW_API_RATE_PT_EGRL_SET, shiva_rate_port_egrl_set), \
+    SW_API_DEF(SW_API_RATE_PT_EGRL_GET, shiva_rate_port_egrl_get), \
+    SW_API_DEF(SW_API_RATE_PT_INRL_SET, shiva_rate_port_inrl_set), \
+    SW_API_DEF(SW_API_RATE_PT_INRL_GET, shiva_rate_port_inrl_get), \
+    SW_API_DEF(SW_API_STORM_CTRL_FRAME_SET, shiva_storm_ctrl_frame_set), \
+    SW_API_DEF(SW_API_STORM_CTRL_FRAME_GET, shiva_storm_ctrl_frame_get), \
+    SW_API_DEF(SW_API_STORM_CTRL_RATE_SET, shiva_storm_ctrl_rate_set), \
+    SW_API_DEF(SW_API_STORM_CTRL_RATE_GET, shiva_storm_ctrl_rate_get),
+
+#define RATE_API_PARAM \
+    SW_API_DESC(SW_API_RATE_QU_EGRL_SET) \
+    SW_API_DESC(SW_API_RATE_QU_EGRL_GET) \
+    SW_API_DESC(SW_API_RATE_PT_EGRL_SET) \
+    SW_API_DESC(SW_API_RATE_PT_EGRL_GET) \
+    SW_API_DESC(SW_API_RATE_PT_INRL_SET) \
+    SW_API_DESC(SW_API_RATE_PT_INRL_GET) \
+    SW_API_DESC(SW_API_STORM_CTRL_FRAME_SET) \
+    SW_API_DESC(SW_API_STORM_CTRL_FRAME_GET) \
+    SW_API_DESC(SW_API_STORM_CTRL_RATE_SET)  \
+    SW_API_DESC(SW_API_STORM_CTRL_RATE_GET)
+#else
+#define RATE_API
+#define RATE_API_PARAM
+#endif
+
+#ifdef IN_STP
+#define STP_API \
+    SW_API_DEF(SW_API_STP_PT_STATE_SET, shiva_stp_port_state_set), \
+    SW_API_DEF(SW_API_STP_PT_STATE_GET, shiva_stp_port_state_get),
+
+#define STP_API_PARAM \
+    SW_API_DESC(SW_API_STP_PT_STATE_SET) \
+    SW_API_DESC(SW_API_STP_PT_STATE_GET)
+#else
+#define STP_API
+#define STP_API_PARAM
+#endif
+
+#ifdef IN_MIB
+#define MIB_API \
+    SW_API_DEF(SW_API_PT_MIB_GET, shiva_get_mib_info), \
+    SW_API_DEF(SW_API_MIB_STATUS_SET, shiva_mib_status_set), \
+    SW_API_DEF(SW_API_MIB_STATUS_GET, shiva_mib_status_get),
+
+#define MIB_API_PARAM \
+    SW_API_DESC(SW_API_PT_MIB_GET)  \
+    SW_API_DESC(SW_API_MIB_STATUS_SET) \
+    SW_API_DESC(SW_API_MIB_STATUS_GET)
+#else
+#define MIB_API
+#define MIB_API_PARAM
+#endif
+
+#ifdef IN_MISC
+#define MISC_API \
+    SW_API_DEF(SW_API_ARP_STATUS_SET, shiva_arp_status_set), \
+    SW_API_DEF(SW_API_ARP_STATUS_GET, shiva_arp_status_get), \
+    SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, shiva_frame_max_size_set), \
+    SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, shiva_frame_max_size_get), \
+    SW_API_DEF(SW_API_PT_UNK_SA_CMD_SET, shiva_port_unk_sa_cmd_set), \
+    SW_API_DEF(SW_API_PT_UNK_SA_CMD_GET, shiva_port_unk_sa_cmd_get), \
+    SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, shiva_port_unk_uc_filter_set), \
+    SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, shiva_port_unk_uc_filter_get), \
+    SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, shiva_port_unk_mc_filter_set), \
+    SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, shiva_port_unk_mc_filter_get), \
+    SW_API_DEF(SW_API_PT_BC_FILTER_SET, shiva_port_bc_filter_set), \
+    SW_API_DEF(SW_API_PT_BC_FILTER_GET, shiva_port_bc_filter_get), \
+    SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, shiva_cpu_port_status_set), \
+    SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, shiva_cpu_port_status_get), \
+    SW_API_DEF(SW_API_PPPOE_CMD_SET, shiva_pppoe_cmd_set), \
+    SW_API_DEF(SW_API_PPPOE_CMD_GET, shiva_pppoe_cmd_get), \
+    SW_API_DEF(SW_API_PPPOE_STATUS_SET, shiva_pppoe_status_set), \
+    SW_API_DEF(SW_API_PPPOE_STATUS_GET, shiva_pppoe_status_get), \
+    SW_API_DEF(SW_API_PT_DHCP_SET, shiva_port_dhcp_set), \
+    SW_API_DEF(SW_API_PT_DHCP_GET, shiva_port_dhcp_get), \
+    SW_API_DEF(SW_API_ARP_CMD_SET, shiva_arp_cmd_set), \
+    SW_API_DEF(SW_API_ARP_CMD_GET, shiva_arp_cmd_get), \
+    SW_API_DEF(SW_API_EAPOL_CMD_SET, shiva_eapol_cmd_set), \
+    SW_API_DEF(SW_API_EAPOL_CMD_GET, shiva_eapol_cmd_get), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_ADD, shiva_pppoe_session_add), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_DEL, shiva_pppoe_session_del), \
+    SW_API_DEF(SW_API_PPPOE_SESSION_GET, shiva_pppoe_session_get), \
+    SW_API_DEF(SW_API_EAPOL_STATUS_SET, shiva_eapol_status_set), \
+    SW_API_DEF(SW_API_EAPOL_STATUS_GET, shiva_eapol_status_get), \
+    SW_API_DEF(SW_API_RIPV1_STATUS_SET, shiva_ripv1_status_set), \
+    SW_API_DEF(SW_API_RIPV1_STATUS_GET, shiva_ripv1_status_get),
+
+#define MISC_API_PARAM \
+    SW_API_DESC(SW_API_ARP_STATUS_SET)  \
+    SW_API_DESC(SW_API_ARP_STATUS_GET)  \
+    SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET)  \
+    SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET)  \
+    SW_API_DESC(SW_API_PT_UNK_SA_CMD_SET)  \
+    SW_API_DESC(SW_API_PT_UNK_SA_CMD_GET)  \
+    SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET)  \
+    SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET)  \
+    SW_API_DESC(SW_API_PT_BC_FILTER_SET)  \
+    SW_API_DESC(SW_API_PT_BC_FILTER_GET)  \
+    SW_API_DESC(SW_API_CPU_PORT_STATUS_SET)  \
+    SW_API_DESC(SW_API_CPU_PORT_STATUS_GET)  \
+    SW_API_DESC(SW_API_PPPOE_CMD_SET)  \
+    SW_API_DESC(SW_API_PPPOE_CMD_GET)  \
+    SW_API_DESC(SW_API_PPPOE_STATUS_SET)  \
+    SW_API_DESC(SW_API_PPPOE_STATUS_GET)  \
+    SW_API_DESC(SW_API_PT_DHCP_SET)  \
+    SW_API_DESC(SW_API_PT_DHCP_GET)  \
+    SW_API_DESC(SW_API_ARP_CMD_SET)  \
+    SW_API_DESC(SW_API_ARP_CMD_GET)  \
+    SW_API_DESC(SW_API_EAPOL_CMD_SET) \
+    SW_API_DESC(SW_API_EAPOL_CMD_GET) \
+    SW_API_DESC(SW_API_PPPOE_SESSION_ADD)  \
+    SW_API_DESC(SW_API_PPPOE_SESSION_DEL)  \
+    SW_API_DESC(SW_API_PPPOE_SESSION_GET)  \
+    SW_API_DESC(SW_API_EAPOL_STATUS_SET)  \
+    SW_API_DESC(SW_API_EAPOL_STATUS_GET)  \
+    SW_API_DESC(SW_API_RIPV1_STATUS_SET)  \
+    SW_API_DESC(SW_API_RIPV1_STATUS_GET)
+#else
+#define MISC_API
+#define MISC_API_PARAM
+#endif
+
+#ifdef IN_LED
+#define LED_API \
+    SW_API_DEF(SW_API_LED_PATTERN_SET, shiva_led_ctrl_pattern_set), \
+    SW_API_DEF(SW_API_LED_PATTERN_GET, shiva_led_ctrl_pattern_get),
+
+#define LED_API_PARAM \
+    SW_API_DESC(SW_API_LED_PATTERN_SET) \
+    SW_API_DESC(SW_API_LED_PATTERN_GET)
+#else
+#define LED_API
+#define LED_API_PARAM
+#endif
+
+#define REG_API \
+    SW_API_DEF(SW_API_PHY_GET, shiva_phy_get), \
+    SW_API_DEF(SW_API_PHY_SET, shiva_phy_set), \
+    SW_API_DEF(SW_API_REG_GET, shiva_reg_get), \
+    SW_API_DEF(SW_API_REG_SET, shiva_reg_set), \
+    SW_API_DEF(SW_API_REG_FIELD_GET, shiva_reg_field_get), \
+    SW_API_DEF(SW_API_REG_FIELD_SET, shiva_reg_field_set),
+
+#define REG_API_PARAM \
+    SW_API_DESC(SW_API_PHY_GET) \
+    SW_API_DESC(SW_API_PHY_SET) \
+    SW_API_DESC(SW_API_REG_GET) \
+    SW_API_DESC(SW_API_REG_SET) \
+    SW_API_DESC(SW_API_REG_FIELD_GET) \
+    SW_API_DESC(SW_API_REG_FIELD_SET)
+
+#define SSDK_API \
+    SW_API_DEF(SW_API_SWITCH_RESET, shiva_reset), \
+    SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \
+    PORTCONTROL_API \
+    VLAN_API \
+    PORTVLAN_API \
+    FDB_API    \
+    ACL_API    \
+    QOS_API    \
+    IGMP_API   \
+    LEAKY_API  \
+    MIRROR_API \
+    RATE_API \
+    STP_API  \
+    MIB_API  \
+    MISC_API \
+    LED_API  \
+    REG_API  \
+    SW_API_DEF(SW_API_MAX, NULL),
+
+
+#define SSDK_PARAM  \
+    SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+    SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
+    MIB_API_PARAM    \
+    LEAKY_API_PARAM  \
+    MISC_API_PARAM   \
+    IGMP_API_PARAM   \
+    MIRROR_API_PARAM \
+    PORTCONTROL_API_PARAM \
+    PORTVLAN_API_PARAM    \
+    VLAN_API_PARAM \
+    FDB_API_PARAM  \
+    QOS_API_PARAM  \
+    RATE_API_PARAM \
+    STP_API_PARAM  \
+    ACL_API_PARAM  \
+    LED_API_PARAM  \
+    REG_API_PARAM  \
+    SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#if (defined(USER_MODE) && defined(KERNEL_MODULE))
+#undef SSDK_API
+#undef SSDK_PARAM
+
+#define SSDK_API \
+    REG_API \
+    SW_API_DEF(SW_API_MAX, NULL),
+
+#define SSDK_PARAM  \
+    REG_API_PARAM \
+    SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _SHIVA_API_H_ */
diff --git a/qca-ssdk/include/hsl/shiva/shiva_fdb.h b/qca-ssdk/include/hsl/shiva/shiva_fdb.h
new file mode 100755
index 0000000..f5e450e
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_fdb.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_fdb SHIVA_FDB
+ * @{
+ */
+#ifndef _SHIVA_FDB_H_
+#define _SHIVA_FDB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_fdb.h"
+
+    sw_error_t
+    shiva_fdb_init(a_uint32_t dev_id);
+
+#ifdef IN_FDB
+#define SHIVA_FDB_INIT(rv, dev_id) \
+    { \
+        rv = shiva_fdb_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define SHIVA_FDB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    shiva_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_fdb_del_by_mac(a_uint32_t dev_id,
+                         const fal_fdb_entry_t *entry);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHIVA_FDB_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/shiva/shiva_igmp.h b/qca-ssdk/include/hsl/shiva/shiva_igmp.h
new file mode 100755
index 0000000..cfae2f7
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_igmp.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_igmp SHIVA_IGMP
+ * @{
+ */
+#ifndef _SHIVA_IGMP_H_
+#define _SHIVA_IGMP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_igmp.h"
+
+    sw_error_t
+    shiva_igmp_init(a_uint32_t dev_id);
+
+#ifdef IN_IGMP
+#define SHIVA_IGMP_INIT(rv, dev_id) \
+    { \
+        rv = shiva_igmp_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define SHIVA_IGMP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    shiva_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _SHIVA_IGMP_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/shiva/shiva_init.h b/qca-ssdk/include/hsl/shiva/shiva_init.h
new file mode 100755
index 0000000..8610ec0
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_init.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_init SHIVA_INIT
+ * @{
+ */
+#ifndef _SHIVA_INIT_H_
+#define _SHIVA_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+
+    sw_error_t
+    shiva_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+
+    sw_error_t
+    shiva_cleanup(a_uint32_t dev_id);
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    shiva_reset(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHIVA_INIT_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/shiva/shiva_leaky.h b/qca-ssdk/include/hsl/shiva/shiva_leaky.h
new file mode 100755
index 0000000..6cd53b2
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_leaky.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_leaky SHIVA_LEAKY
+ * @{
+ */
+#ifndef _SHIVA_LEAKY_H_
+#define _SHIVA_LEAKY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_leaky.h"
+
+    sw_error_t shiva_leaky_init(a_uint32_t dev_id);
+
+#ifdef IN_LEAKY
+#define SHIVA_LEAKY_INIT(rv, dev_id) \
+    { \
+        rv = shiva_leaky_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define SHIVA_LEAKY_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    shiva_uc_leaky_mode_set(a_uint32_t dev_id,
+                            fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_uc_leaky_mode_get(a_uint32_t dev_id,
+                            fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_mc_leaky_mode_set(a_uint32_t dev_id,
+                            fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_mc_leaky_mode_get(a_uint32_t dev_id,
+                            fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SHIVA_LEAKY_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/shiva/shiva_led.h b/qca-ssdk/include/hsl/shiva/shiva_led.h
new file mode 100755
index 0000000..a75369f
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_led.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _SHIVA_LED_H_
+#define _SHIVA_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_led.h"
+
+    sw_error_t
+    shiva_led_init(a_uint32_t dev_id);
+
+#ifdef IN_LED
+#define SHIVA_LED_INIT(rv, dev_id) \
+    { \
+        rv = shiva_led_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define SHIVA_LED_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    shiva_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                               led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                               led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHIVA_LED_H_ */
diff --git a/qca-ssdk/include/hsl/shiva/shiva_mib.h b/qca-ssdk/include/hsl/shiva/shiva_mib.h
new file mode 100755
index 0000000..0b91b5b
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_mib.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_mib SHIVA_MIB
+ * @{
+ */
+#ifndef _SHIVA_MIB_H_
+#define _SHIVA_MIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mib.h"
+
+    sw_error_t
+    shiva_mib_init(a_uint32_t dev_id);
+
+#ifdef IN_MIB
+#define SHIVA_MIB_INIT(rv, dev_id) \
+    { \
+        rv = shiva_mib_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define SHIVA_MIB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    shiva_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_mib_info_t * mib_info );
+
+
+    HSL_LOCAL sw_error_t
+    shiva_mib_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_mib_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHIVA_MIB_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/shiva/shiva_mirror.h b/qca-ssdk/include/hsl/shiva/shiva_mirror.h
new file mode 100755
index 0000000..d889fd5
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_mirror.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_mirror SHIVA_MIRROR
+ * @{
+ */
+#ifndef _SHIVA_MIRROR_H_
+#define _SHIVA_MIRROR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_mirror.h"
+#define  MIRROR_ANALYZER_NONE  0xf
+
+    sw_error_t shiva_mirr_init(a_uint32_t dev_id);
+
+#ifdef IN_MIRROR
+#define SHIVA_MIRR_INIT(rv, dev_id) \
+    { \
+        rv = shiva_mirr_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define SHIVA_MIRR_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    shiva_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SHIVA_MIRROR_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/shiva/shiva_misc.h b/qca-ssdk/include/hsl/shiva/shiva_misc.h
new file mode 100755
index 0000000..5c4fdbd
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_misc.h
@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_misc SHIVA_MISC
+ * @{
+ */
+#ifndef _SHIVA_MISC_H_
+#define _SHIVA_MISC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_misc.h"
+
+    sw_error_t shiva_misc_init(a_uint32_t dev_id);
+
+#ifdef IN_MISC
+#define SHIVA_MISC_INIT(rv, dev_id) \
+    { \
+        rv = shiva_misc_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define SHIVA_MISC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+    HSL_LOCAL sw_error_t
+    shiva_arp_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_arp_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr);
+
+    HSL_LOCAL sw_error_t
+    shiva_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    shiva_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    shiva_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    shiva_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    shiva_loop_check_status_set(a_uint32_t dev_id, fal_loop_check_time_t time, a_bool_t enable);
+
+    HSL_LOCAL sw_error_t
+    shiva_loop_check_status_get(a_uint32_t dev_id, fal_loop_check_time_t * time, a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    shiva_loop_check_info_get(a_uint32_t dev_id, a_uint32_t * old_port_id, a_uint32_t * new_port_id);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SHIVA_GEN_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/shiva/shiva_port_ctrl.h b/qca-ssdk/include/hsl/shiva/shiva_port_ctrl.h
new file mode 100755
index 0000000..1690413
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_port_ctrl.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_port_ctrl SHIVA_PORT_CONTROL
+ * @{
+ */
+#ifndef _SHIVA_PORT_CTRL_H_
+#define _SHIVA_PORT_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_port_ctrl.h"
+
+#define RX_FC_EN 1
+#define TX_FC_FULL_EN 1
+#define TX_FC_HALF_EN 1
+
+sw_error_t shiva_port_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTCONTROL
+#define SHIVA_PORT_CTRL_INIT(rv, dev_id) \
+    { \
+        rv = shiva_port_ctrl_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define SHIVA_PORT_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_duplex_t duplex);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_duplex_t * pduplex);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_speed_t speed);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_speed_t * pspeed);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * status);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t autoadv);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * autoadv);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_flowctrl_forcemode_set(a_uint32_t dev_id,
+                                      fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_flowctrl_forcemode_get(a_uint32_t dev_id,
+                                      fal_port_t port_id,
+                                      a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+                   fal_cable_status_t *cable_status, a_uint32_t *cable_len);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SHIVA_PORT_CTRL_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/shiva/shiva_portvlan.h b/qca-ssdk/include/hsl/shiva/shiva_portvlan.h
new file mode 100755
index 0000000..fdfa27d
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_portvlan.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+ * @defgroup shiva_port_vlan SHIVA_PORT_VLAN
+ * @{
+ */
+#ifndef _SHIVA_PORTVLAN_H_
+#define _SHIVA_PORTVLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_portvlan.h"
+
+    sw_error_t shiva_portvlan_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTVLAN
+#define SHIVA_PORTVLAN_INIT(rv, dev_id) \
+    { \
+        rv = shiva_portvlan_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define SHIVA_PORTVLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_1qmode_t port_1qmode);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_1qmode_t * pport_1qmode);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pt_1q_egmode_t port_egvlanmode);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pt_1q_egmode_t * pport_egvlanmode);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t mem_port_id);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t mem_port_id);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_pbmp_t mem_port_map);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pbmp_t * mem_port_map);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_pt_invlan_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_pt_invlan_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t vid);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * vid);
+
+    HSL_LOCAL sw_error_t
+    shiva_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t vid);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * vid);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    fal_vlan_propagation_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    fal_vlan_propagation_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t * iterator, fal_vlan_trans_entry_t * entry);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SHIVA_PORTVLAN_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/shiva/shiva_qos.h b/qca-ssdk/include/hsl/shiva/shiva_qos.h
new file mode 100755
index 0000000..cd588ac
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_qos.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_qos SHIVA_QOS
+ * @{
+ */
+#ifndef _SHIVA_QOS_H_
+#define _SHIVA_QOS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_qos.h"
+
+    sw_error_t shiva_qos_init(a_uint32_t dev_id);
+
+#ifdef IN_QOS
+#define SHIVA_QOS_INIT(rv, dev_id) \
+    { \
+        rv = shiva_qos_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define SHIVA_QOS_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_queue_tx_buf_status_set(a_uint32_t dev_id,
+                                      fal_port_t port_id, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_queue_tx_buf_status_get(a_uint32_t dev_id,
+                                      fal_port_t port_id,
+                                      a_bool_t * enable);
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_queue_t queue_id,
+                                  a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_queue_t queue_id,
+                                  a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t * number);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+                              fal_queue_t queue);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+                              fal_queue_t * queue);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+                                fal_queue_t queue);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+                                fal_queue_t * queue);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_qos_mode_t mode, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_qos_mode_t mode, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_qos_mode_t mode, a_uint32_t pri);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_qos_mode_t mode, a_uint32_t * pri);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t up);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t * up);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                                fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                                fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SHIVA_QOS_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/shiva/shiva_rate.h b/qca-ssdk/include/hsl/shiva/shiva_rate.h
new file mode 100755
index 0000000..7648dbb
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_rate.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_rate SHIVA_RATE
+ * @{
+ */
+#ifndef _SHIVA_RATE_H_
+#define _SHIVA_RATE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_rate.h"
+
+    sw_error_t shiva_rate_init(a_uint32_t dev_id);
+
+#ifdef IN_RATE
+#define SHIVA_RATE_INIT(rv, dev_id) \
+    { \
+        rv = shiva_rate_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define SHIVA_RATE_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    shiva_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_queue_t queue_id, a_uint32_t * speed,
+                              a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_queue_t queue_id, a_uint32_t * speed,
+                              a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * speed, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * speed, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * speed, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * speed, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_storm_type_t storm_type, a_bool_t enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_storm_type_t storm_type, a_bool_t * enable);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * rate_in_pps);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * rate_in_pps);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SHIVA_RATE_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/shiva/shiva_reduced_acl.h b/qca-ssdk/include/hsl/shiva/shiva_reduced_acl.h
new file mode 100755
index 0000000..51fa9a1
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_reduced_acl.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _SHIVA_REDUCED_ACL_H_
+#define _SHIVA_REDUCED_ACL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+
+    sw_error_t
+    shiva_acl_rule_write(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+                         a_uint32_t msk[8]);
+
+    sw_error_t
+    shiva_acl_action_write(a_uint32_t dev_id, a_uint32_t act_idx,
+                           a_uint32_t act[3]);
+
+    sw_error_t
+    shiva_acl_slct_write(a_uint32_t dev_id, a_uint32_t slct_idx,
+                         a_uint32_t slct[8]);
+
+    sw_error_t
+    shiva_acl_rule_read(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+                        a_uint32_t msk[8]);
+
+    sw_error_t
+    shiva_acl_action_read(a_uint32_t dev_id, a_uint32_t act_idx,
+                          a_uint32_t act[3]);
+
+    sw_error_t
+    shiva_acl_slct_read(a_uint32_t dev_id, a_uint32_t slct_idx,
+                        a_uint32_t slct[8]);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SHIVA_REDUCED_ACL_H_ */
+
diff --git a/qca-ssdk/include/hsl/shiva/shiva_reg.h b/qca-ssdk/include/hsl/shiva/shiva_reg.h
new file mode 100755
index 0000000..48561c7
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_reg.h
@@ -0,0 +1,4075 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _SHIVA_REG_H_
+#define _SHIVA_REG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#define MAX_ENTRY_LEN 128
+
+#define HSL_RW 1
+#define HSL_RO 0
+
+
+    /* SHIVA Mask Control Register */
+#define MASK_CTL                  "mask"
+#define MASK_CTL_ID               0
+#define MASK_CTL_OFFSET           0x0000
+#define MASK_CTL_E_LENGTH         4
+#define MASK_CTL_E_OFFSET         0
+#define MASK_CTL_NR_E             1
+
+#define SOFT_RST                              "mask_rst"
+#define MASK_CTL_SOFT_RST_BOFFSET             31
+#define MASK_CTL_SOFT_RST_BLEN                1
+#define MASK_CTL_SOFT_RST_FLAG                HSL_RW
+
+#define MII_CLK5_SEL                          "mask_clk5s"
+#define MASK_CTL_MII_CLK5_SEL_BOFFSET         21
+#define MASK_CTL_MII_CLK5_SEL_BLEN            1
+#define MASK_CTL_MII_CLK5_SEL_FLAG            HSL_RW
+
+#define MII_CLK0_SEL                          "mask_clk0s"
+#define MASK_CTL_MII_CLK0_SEL_BOFFSET         20
+#define MASK_CTL_MII_CLK0_SEL_BLEN            1
+#define MASK_CTL_MII_CLK0_SEL_FLAG            HSL_RW
+
+#define LOAD_EEPROM                           "mask_ldro"
+#define MASK_CTL_LOAD_EEPROM_BOFFSET          16
+#define MASK_CTL_LOAD_EEPROM_BLEN             1
+#define MASK_CTL_LOAD_EEPROM_FLAG             HSL_RW
+
+#define DEVICE_ID                             "mask_did"
+#define MASK_CTL_DEVICE_ID_BOFFSET            8
+#define MASK_CTL_DEVICE_ID_BLEN               8
+#define MASK_CTL_DEVICE_ID_FLAG               HSL_RO
+
+#define REV_ID                                "mask_rid"
+#define MASK_CTL_REV_ID_BOFFSET               0
+#define MASK_CTL_REV_ID_BLEN                  8
+#define MASK_CTL_REV_ID_FLAG                  HSL_RO
+
+
+    /* SHIVA Mask Control Register */
+#define POSTRIP                  "postrip"
+#define POSTRIP_ID               0
+#define POSTRIP_OFFSET           0x0008
+#define POSTRIP_E_LENGTH         4
+#define POSTRIP_E_OFFSET         0
+#define POSTRIP_NR_E             1
+
+#define POWER_ON_SEL                           "postrip_sel"
+#define POSTRIP_POWER_ON_SEL_BOFFSET           31
+#define POSTRIP_POWER_ON_SEL_BLEN              1
+#define POSTRIP_POWER_ON_SEL_FLAG              HSL_RW
+
+#define RXDELAY_S1                             "postrip_rx_s1"
+#define POSTRIP_RXDELAY_S1_BOFFSET             26
+#define POSTRIP_RXDELAY_S1_BLEN                1
+#define POSTRIP_RXDELAY_S1_FLAG                HSL_RW
+
+#define SPI_EN                                 "postrip_spi"
+#define POSTRIP_SPI_EN_BOFFSET                 25
+#define POSTRIP_SPI_EN_BLEN                    1
+#define POSTRIP_SPI_EN_FLAG                    HSL_RW
+
+#define LED_OPEN_EN                            "postrip_led"
+#define POSTRIP_LED_OPEN_EN_BOFFSET            24
+#define POSTRIP_LED_OPEN_EN_BLEN               1
+#define POSTRIP_LED_OPEN_EN_FLAG               HSL_RW
+
+#define RXDELAY_S0                             "postrip_rx_s0"
+#define POSTRIP_RXDELAY_S0_BOFFSET             23
+#define POSTRIP_RXDELAY_S0_BLEN                1
+#define POSTRIP_RXDELAY_S0_FLAG                HSL_RW
+
+#define TXDELAY_S1                             "postrip_tx_s1"
+#define POSTRIP_TXDELAY_S1_BOFFSET             22
+#define POSTRIP_TXDELAY_S1_BLEN                1
+#define POSTRIP_TXDELAY_S1_FLAG                HSL_RW
+
+#define TXDELAY_S0                             "postrip_tx_s0"
+#define POSTRIP_TXDELAY_S0_BOFFSET             21
+#define POSTRIP_TXDELAY_S0_BLEN                1
+#define POSTRIP_TXDELAY_S0_FLAG                HSL_RW
+
+#define LPW_EXIT                               "postrip_lpw_exit"
+#define POSTRIP_LPW_EXIT_BOFFSET               20
+#define POSTRIP_LPW_EXIT_BLEN                  1
+#define POSTRIP_LPW_EXIT_FLAG                  HSL_RW
+
+#define PHY_PLL_ON                             "postrip_phy_pll"
+#define POSTRIP_PHY_PLL_ON_BOFFSET             19
+#define POSTRIP_PHY_PLL_ON_BLEN                1
+#define POSTRIP_PHY_PLL_ON_FLAG                HSL_RW
+
+#define MAN_ENABLE                             "postrip_man_en"
+#define POSTRIP_MAN_ENABLE_BOFFSET             18
+#define POSTRIP_MAN_ENABLE_BLEN                1
+#define POSTRIP_MAN_ENABLE_FLAG                HSL_RW
+
+#define LPW_STATE_EN                           "postrip_lpw_state"
+#define POSTRIP_LPW_STATE_EN_BOFFSET           17
+#define POSTRIP_LPW_STATE_EN_BLEN              1
+#define POSTRIP_LPW_STATE_EN_FLAG              HSL_RW
+
+#define POWER_DOWN_HW                          "postrip_power_down"
+#define POSTRIP_POWER_DOWN_HW_BOFFSET          16
+#define POSTRIP_POWER_DOWN_HW_BLEN             1
+#define POSTRIP_POWER_DOWN_HW_FLAG             HSL_RW
+
+#define MAC5_PHY_MODE                          "postrip_mac5_phy"
+#define POSTRIP_MAC5_PHY_MODE_BOFFSET          15
+#define POSTRIP_MAC5_PHY_MODE_BLEN             1
+#define POSTRIP_MAC5_PHY_MODE_FLAG             HSL_RW
+
+#define MAC5_MAC_MODE                          "postrip_mac5_mac"
+#define POSTRIP_MAC5_MAC_MODE_BOFFSET          14
+#define POSTRIP_MAC5_MAC_MODE_BLEN             1
+#define POSTRIP_MAC5_MAC_MODE_FLAG             HSL_RW
+
+#define DBG_MODE_I                             "postrip_dbg"
+#define POSTRIP_DBG_MODE_I_BOFFSET             13
+#define POSTRIP_DBG_MODE_I_BLEN                1
+#define POSTRIP_DBG_MODE_I_FLAG                HSL_RW
+
+#define HIB_PULSE_HW                           "postrip_hib"
+#define POSTRIP_HIB_PULSE_HW_BOFFSET           12
+#define POSTRIP_HIB_PULSE_HW_BLEN              1
+#define POSTRIP_HIB_PULSE_HW_FLAG              HSL_RW
+
+#define SEL_CLK25M                             "postrip_clk25"
+#define POSTRIP_SEL_CLK25M_BOFFSET             11
+#define POSTRIP_SEL_CLK25M_BLEN                1
+#define POSTRIP_SEL_CLK25M_FLAG                HSL_RW
+
+#define GATE_25M_EN                            "postrip_gate25"
+#define POSTRIP_GATE_25M_EN_BOFFSET            10
+#define POSTRIP_GATE_25M_EN_BLEN               1
+#define POSTRIP_GATE_25M_EN_FLAG               HSL_RW
+
+#define SEL_ANA_RST                            "postrip_sel_ana"
+#define POSTRIP_SEL_ANA_RST_BOFFSET            9
+#define POSTRIP_SEL_ANA_RST_BLEN               1
+#define POSTRIP_SEL_ANA_RST_FLAG               HSL_RW
+
+#define SERDES_EN                              "postrip_serdes_en"
+#define POSTRIP_SERDES_EN_BOFFSET              8
+#define POSTRIP_SERDES_EN_BLEN                 1
+#define POSTRIP_SERDES_EN_FLAG                 HSL_RW
+
+#define RGMII_TXCLK_DELAY_EN                   "postrip_tx_delay"
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_BOFFSET   7
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_BLEN      1
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_FLAG      HSL_RW
+
+#define RGMII_RXCLK_DELAY_EN                   "postrip_rx_delay"
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_BOFFSET   6
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_BLEN      1
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_FLAG      HSL_RW
+
+#define RTL_MODE                               "postrip_rtl"
+#define POSTRIP_RTL_MODE_BOFFSET               5
+#define POSTRIP_RTL_MODE_BLEN                  1
+#define POSTRIP_RTL_MODE_FLAG                  HSL_RW
+
+#define MAC0_MAC_MODE                          "postrip_mac0_mac"
+#define POSTRIP_MAC0_MAC_MODE_BOFFSET          4
+#define POSTRIP_MAC0_MAC_MODE_BLEN             1
+#define POSTRIP_MAC0_MAC_MODE_FLAG             HSL_RW
+
+#define PHY4_RGMII_EN                          "postrip_phy4_rgmii"
+#define POSTRIP_PHY4_RGMII_EN_BOFFSET          3
+#define POSTRIP_PHY4_RGMII_EN_BLEN             1
+#define POSTRIP_PHY4_RGMII_EN_FLAG             HSL_RW
+
+#define PHY4_GMII_EN                           "postrip_phy4_gmii"
+#define POSTRIP_PHY4_GMII_EN_BOFFSET           2
+#define POSTRIP_PHY4_GMII_EN_BLEN              1
+#define POSTRIP_PHY4_GMII_EN_FLAG              HSL_RW
+
+#define MAC0_RGMII_EN                          "postrip_mac0_rgmii"
+#define POSTRIP_MAC0_RGMII_EN_BOFFSET          1
+#define POSTRIP_MAC0_RGMII_EN_BLEN             1
+#define POSTRIP_MAC0_RGMII_EN_FLAG             HSL_RW
+
+#define MAC0_GMII_EN                           "postrip_mac0_gmii"
+#define POSTRIP_MAC0_GMII_EN_BOFFSET           0
+#define POSTRIP_MAC0_GMII_EN_BLEN              1
+#define POSTRIP_MAC0_GMII_EN_FLAG              HSL_RW
+
+
+
+    /* Global Interrupt Register */
+#define GLOBAL_INT                "gint"
+#define GLOBAL_INT_ID             1
+#define GLOBAL_INT_OFFSET         0x0014
+#define GLOBAL_INT_E_LENGTH       4
+#define GLOBAL_INT_E_OFFSET       0
+#define GLOBAL_INT_NR_E           1
+
+#define GLB_QM_ERR_CNT                            "gint_qmen"
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BOFFSET         24
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BLEN            8
+#define GLOBAL_INT_GLB_QM_ERR_CNT_FLAG            HSL_RO
+
+#define GLB_LOOKUP_ERR                            "gint_glblper"
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BOFFSET         17
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BLEN            1
+#define GLOBAL_INT_GLB_LOOKUP_ERR_FLAG            HSL_RW
+
+#define GLB_QM_ERR                                "gint_glbqmer"
+#define GLOBAL_INT_GLB_QM_ERR_BOFFSET             16
+#define GLOBAL_INT_GLB_QM_ERR_BLEN                1
+#define GLOBAL_INT_GLB_QM_ERR_FLAG                HSL_RW
+
+#define GLB_HW_INI_DONE                           "gint_hwid"
+#define GLOBAL_INT_GLB_HW_INI_DONE_BOFFSET        14
+#define GLOBAL_INT_GLB_HW_INI_DONE_BLEN           1
+#define GLOBAL_INT_GLB_HW_INI_DONE_FLAG           HSL_RW
+
+#define GLB_MIB_INI                               "gint_mibi"
+#define GLOBAL_INT_GLB_MIB_INI_BOFFSET            13
+#define GLOBAL_INT_GLB_MIB_INI_BLEN               1
+#define GLOBAL_INT_GLB_MIB_INI_FLAG               HSL_RW
+
+#define GLB_MIB_DONE                              "gint_mibd"
+#define GLOBAL_INT_GLB_MIB_DONE_BOFFSET           12
+#define GLOBAL_INT_GLB_MIB_DONE_BLEN              1
+#define GLOBAL_INT_GLB_MIB_DONE_FLAG              HSL_RW
+
+#define GLB_BIST_DONE                             "gint_bisd"
+#define GLOBAL_INT_GLB_BIST_DONE_BOFFSET          11
+#define GLOBAL_INT_GLB_BIST_DONE_BLEN             1
+#define GLOBAL_INT_GLB_BIST_DONE_FLAG             HSL_RW
+
+#define GLB_VT_MISS_VIO                           "gint_vtms"
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BOFFSET        10
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BLEN           1
+#define GLOBAL_INT_GLB_VT_MISS_VIO_FLAG           HSL_RW
+
+#define GLB_VT_MEM_VIO                            "gint_vtme"
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BOFFSET         9
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BLEN            1
+#define GLOBAL_INT_GLB_VT_MEM_VIO_FLAG            HSL_RW
+
+#define GLB_VT_DONE                               "gint_vtd"
+#define GLOBAL_INT_GLB_VT_DONE_BOFFSET            8
+#define GLOBAL_INT_GLB_VT_DONE_BLEN               1
+#define GLOBAL_INT_GLB_VT_DONE_FLAG               HSL_RW
+
+#define GLB_QM_INI                                "gint_qmin"
+#define GLOBAL_INT_GLB_QM_INI_BOFFSET             7
+#define GLOBAL_INT_GLB_QM_INI_BLEN                1
+#define GLOBAL_INT_GLB_QM_INI_FLAG                HSL_RW
+
+#define GLB_AT_INI                                "gint_atin"
+#define GLOBAL_INT_GLB_AT_INI_BOFFSET             6
+#define GLOBAL_INT_GLB_AT_INI_BLEN                1
+#define GLOBAL_INT_GLB_AT_INI_FLAG                HSL_RW
+
+#define GLB_ARL_FULL                              "gint_arlf"
+#define GLOBAL_INT_GLB_ARL_FULL_BOFFSET           5
+#define GLOBAL_INT_GLB_ARL_FULL_BLEN              1
+#define GLOBAL_INT_GLB_ARL_FULL_FLAG              HSL_RW
+
+#define GLB_ARL_DONE                              "gint_arld"
+#define GLOBAL_INT_GLB_ARL_DONE_BOFFSET           4
+#define GLOBAL_INT_GLB_ARL_DONE_BLEN              1
+#define GLOBAL_INT_GLB_ARL_DONE_FLAG              HSL_RW
+
+#define GLB_MDIO_DONE                             "gint_mdid"
+#define GLOBAL_INT_GLB_MDIO_DONE_BOFFSET          3
+#define GLOBAL_INT_GLB_MDIO_DONE_BLEN             1
+#define GLOBAL_INT_GLB_MDIO_DONE_FLAG             HSL_RW
+
+#define GLB_PHY_INT                               "gint_phyi"
+#define GLOBAL_INT_GLB_PHY_INT_BOFFSET            2
+#define GLOBAL_INT_GLB_PHY_INT_BLEN               1
+#define GLOBAL_INT_GLB_PHY_INT_FLAG               HSL_RW
+
+#define GLB_EEPROM_ERR                            "gint_epei"
+#define GLOBAL_INT_GLB_EEPROM_ERR_BOFFSET         1
+#define GLOBAL_INT_GLB_EEPROM_ERR_BLEN            1
+#define GLOBAL_INT_GLB_EEPROM_ERR_FLAG            HSL_RW
+
+#define GLB_EEPROM_INT                            "gint_epi"
+#define GLOBAL_INT_GLB_EEPROM_INT_BOFFSET         0
+#define GLOBAL_INT_GLB_EEPROM_INT_BLEN            1
+#define GLOBAL_INT_GLB_EEPROM_INT_FLAG            HSL_RW
+
+
+    /* Global Interrupt Mask Register */
+#define GLOBAL_INT_MASK           "gintm"
+#define GLOBAL_INT_MASK_ID        2
+#define GLOBAL_INT_MASK_OFFSET    0x0018
+#define GLOBAL_INT_MASK_E_LENGTH  4
+#define GLOBAL_INT_MASK_E_OFFSET  0
+#define GLOBAL_INT_MASK_NR_E      1
+
+#define GLBM_LOOP_CHECK                          "gintm_lc"
+#define GLOBAL_INT_MASK_GLBM_LOOP_CHECK_BOFFSET  18
+#define GLOBAL_INT_MASK_GLBM_LOOP_CHECK_BLEN     1
+#define GLOBAL_INT_MASK_GLBM_LOOP_CHECK_FLAG     HSL_RW
+
+#define GLBM_LOOKUP_ERR                          "gintm_lpe"
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BOFFSET  17
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BLEN     1
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_FLAG     HSL_RW
+
+#define GLBM_QM_ERR                                "gintm_qme"
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BOFFSET        16
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BLEN           1
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_FLAG           HSL_RW
+
+#define GLBM_HW_INI_DONE                           "gintm_hwid"
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BOFFSET   14
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BLEN      1
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_FLAG      HSL_RW
+
+#define GLBM_MIB_INI                               "gintm_mibi"
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BOFFSET       13
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BLEN          1
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_FLAG          HSL_RW
+
+#define GLBM_MIB_DONE                              "gintm_mibd"
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BOFFSET      12
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BLEN         1
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_FLAG         HSL_RW
+
+#define GLBM_BIST_DONE                             "gintm_bisd"
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BOFFSET     11
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BLEN        1
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_FLAG        HSL_RW
+
+#define GLBM_VT_MISS_VIO                           "gintm_vtms"
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BOFFSET   10
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BLEN      1
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_FLAG      HSL_RW
+
+#define GLBM_VT_MEM_VIO                            "gintm_vtme"
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BOFFSET    9
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BLEN       1
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_FLAG       HSL_RW
+
+#define GLBM_VT_DONE                               "gintm_vtd"
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BOFFSET       8
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BLEN          1
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_FLAG          HSL_RW
+
+#define GLBM_QM_INI                                "gintm_qmin"
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BOFFSET        7
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BLEN           1
+#define GLOBAL_INT_MASK_GLBM_QM_INI_FLAG           HSL_RW
+
+#define GLBM_AT_INI                                "gintm_atin"
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BOFFSET        6
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BLEN           1
+#define GLOBAL_INT_MASK_GLBM_AT_INI_FLAG           HSL_RW
+
+#define GLBM_ARL_FULL                              "gintm_arlf"
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BOFFSET      5
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BLEN         1
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_FLAG         HSL_RW
+
+#define GLBM_ARL_DONE                              "gintm_arld"
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BOFFSET      4
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BLEN         1
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_FLAG         HSL_RW
+
+#define GLBM_MDIO_DONE                             "gintm_mdid"
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BOFFSET     3
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BLEN        1
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_FLAG        HSL_RW
+
+#define GLBM_PHY_INT                               "gintm_phy"
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BOFFSET       2
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BLEN          1
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_FLAG          HSL_RW
+
+#define GLBM_EEPROM_ERR                            "gintm_epe"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BOFFSET    1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BLEN       1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_FLAG       HSL_RW
+
+#define GLBM_EEPROM_INT                            "gintm_ep"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BOFFSET    0
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BLEN       1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_FLAG       HSL_RW
+
+
+    /* Global MAC Address Register */
+#define GLOBAL_MAC_ADDR0           "gmac0"
+#define GLOBAL_MAC_ADDR0_ID        3
+#define GLOBAL_MAC_ADDR0_OFFSET    0x0020
+#define GLOBAL_MAC_ADDR0_E_LENGTH  4
+#define GLOBAL_MAC_ADDR0_E_OFFSET  0
+#define GLOBAL_MAC_ADDR0_NR_E      1
+
+#define GLB_BYTE4                                  "gmac_b4"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET         8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN            8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG            HSL_RW
+
+#define GLB_BYTE5                                  "gmac_b5"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET         0
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN            8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG            HSL_RW
+
+#define GLOBAL_MAC_ADDR1           "gmac1"
+#define GLOBAL_MAC_ADDR1_ID        4
+#define GLOBAL_MAC_ADDR1_OFFSET    0x0024
+#define GLOBAL_MAC_ADDR1_E_LENGTH  4
+#define GLOBAL_MAC_ADDR1_E_OFFSET  0
+#define GLOBAL_MAC_ADDR1_NR_E      1
+
+#define GLB_BYTE0                                  "gmac_b0"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET         24
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG            HSL_RW
+
+#define GLB_BYTE1                                  "gmac_b1"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET         16
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG            HSL_RW
+
+#define GLB_BYTE2                                  "gmac_b2"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET         8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG            HSL_RW
+
+#define GLB_BYTE3                                  "gmac_b3"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET         0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN            8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG            HSL_RW
+
+
+    /* Flood Mask Register */
+#define LOOP_CHECK                "loopc"
+#define LOOP_CHECK_ID             4
+#define LOOP_CHECK_OFFSET         0x0028
+#define LOOP_CHECK_E_LENGTH       4
+#define LOOP_CHECK_E_OFFSET       0
+#define LOOP_CHECK_NR_E           1
+
+#define NEW_PORT
+#define LOOP_CHECK_NEW_PORT_BOFFSET         4
+#define LOOP_CHECK_NEW_PORT_BLEN            4
+#define LOOP_CHECK_NEW_PORT_FLAG            HSL_RW
+
+#define OLD_PORT
+#define LOOP_CHECK_OLD_PORT_BOFFSET         0
+#define LOOP_CHECK_OLD_PORT_BLEN            4
+#define LOOP_CHECK_OLD_PORT_FLAG            HSL_RW
+
+
+    /* Flood Mask Register */
+#define FLOOD_MASK                "fmask"
+#define FLOOD_MASK_ID             5
+#define FLOOD_MASK_OFFSET         0x002c
+#define FLOOD_MASK_E_LENGTH       4
+#define FLOOD_MASK_E_OFFSET       0
+#define FLOOD_MASK_NR_E           1
+
+#define BC_FLOOD_DP                         "fmask_bfdp"
+#define FLOOD_MASK_BC_FLOOD_DP_BOFFSET      25
+#define FLOOD_MASK_BC_FLOOD_DP_BLEN         7
+#define FLOOD_MASK_BC_FLOOD_DP_FLAG         HSL_RW
+
+#define ARL_UNI_LEAKY                       "fmask_aulky"
+#define FLOOD_MASK_ARL_UNI_LEAKY_BOFFSET    24
+#define FLOOD_MASK_ARL_UNI_LEAKY_BLEN       1
+#define FLOOD_MASK_ARL_UNI_LEAKY_FLAG       HSL_RW
+
+#define ARL_MUL_LEAKY                       "fmask_amlky"
+#define FLOOD_MASK_ARL_MUL_LEAKY_BOFFSET    23
+#define FLOOD_MASK_ARL_MUL_LEAKY_BLEN       1
+#define FLOOD_MASK_ARL_MUL_LEAKY_FLAG       HSL_RW
+
+#define MUL_FLOOD_DP                        "fmask_mfdp"
+#define FLOOD_MASK_MUL_FLOOD_DP_BOFFSET     16
+#define FLOOD_MASK_MUL_FLOOD_DP_BLEN        7
+#define FLOOD_MASK_MUL_FLOOD_DP_FLAG        HSL_RW
+
+#define IGMP_DP                             "fmask_igmpdp"
+#define FLOOD_MASK_IGMP_DP_BOFFSET          8
+#define FLOOD_MASK_IGMP_DP_BLEN             7
+#define FLOOD_MASK_IGMP_DP_FLAG             HSL_RW
+
+#define UNI_FLOOD_DP                        "fmask_ufdp"
+#define FLOOD_MASK_UNI_FLOOD_DP_BOFFSET     0
+#define FLOOD_MASK_UNI_FLOOD_DP_BLEN        7
+#define FLOOD_MASK_UNI_FLOOD_DP_FLAG        HSL_RW
+
+
+    /* Global Control Register */
+#define GLOBAL_CTL                "gctl"
+#define GLOBAL_CTL_ID             5
+#define GLOBAL_CTL_OFFSET         0x0030
+#define GLOBAL_CTL_E_LENGTH       4
+#define GLOBAL_CTL_E_OFFSET       0
+#define GLOBAL_CTL_NR_E           1
+
+#define RATE_DROP_EN                          "gctl_rden"
+#define GLOBAL_CTL_RATE_DROP_EN_BOFFSET       29
+#define GLOBAL_CTL_RATE_DROP_EN_BLEN          1
+#define GLOBAL_CTL_RATE_DROP_EN_FLAG          HSL_RW
+
+#define QM_PRI_MODE                           "gctl_qmpm"
+#define GLOBAL_CTL_QM_PRI_MODE_BOFFSET        28
+#define GLOBAL_CTL_QM_PRI_MODE_BLEN           1
+#define GLOBAL_CTL_QM_PRI_MODE_FLAG           HSL_RW
+
+#define RATE_CRE_LIMIT                        "gctl_rcrl"
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BOFFSET     26
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BLEN        2
+#define GLOBAL_CTL_RATE_CRE_LIMIT_FLAG        HSL_RW
+
+#define RATE_TIME_SLOT                        "gctl_rtms"
+#define GLOBAL_CTL_RATE_TIME_SLOT_BOFFSET     24
+#define GLOBAL_CTL_RATE_TIME_SLOT_BLEN        2
+#define GLOBAL_CTL_RATE_TIME_SLOT_FLAG        HSL_RW
+
+#define RELOAD_TIMER                          "gctl_rdtm"
+#define GLOBAL_CTL_RELOAD_TIMER_BOFFSET       20
+#define GLOBAL_CTL_RELOAD_TIMER_BLEN          4
+#define GLOBAL_CTL_RELOAD_TIMER_FLAG          HSL_RW
+
+#define QM_CNT_LOCK                           "gctl_qmcl"
+#define GLOBAL_CTL_QM_CNT_LOCK_BOFFSET        19
+#define GLOBAL_CTL_QM_CNT_LOCK_BLEN           1
+#define GLOBAL_CTL_QM_CNT_LOCK_FLAG           HSL_RO
+
+#define BROAD_DROP_EN                         "gctl_bden"
+#define GLOBAL_CTL_BROAD_DROP_EN_BOFFSET      18
+#define GLOBAL_CTL_BROAD_DROP_EN_BLEN         1
+#define GLOBAL_CTL_BROAD_DROP_EN_FLAG         HSL_RW
+
+#define MAX_FRAME_SIZE                        "gctl_mfsz"
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BOFFSET     0
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BLEN        14
+#define GLOBAL_CTL_MAX_FRAME_SIZE_FLAG        HSL_RW
+
+
+    /* Flow Control Register */
+#define FLOW_CTL0                  "fctl"
+#define FLOW_CTL0_ID               6
+#define FLOW_CTL0_OFFSET           0x0034
+#define FLOW_CTL0_E_LENGTH         4
+#define FLOW_CTL0_E_OFFSET         0
+#define FLOW_CTL0_NR_E             1
+
+#define TEST_PAUSE                             "fctl_tps"
+#define FLOW_CTL0_TEST_PAUSE_BOFFSET           31
+#define FLOW_CTL0_TEST_PAUSE_BLEN              1
+#define FLOW_CTL0_TEST_PAUSE_FLAG              HSL_RW
+
+
+#define GOL_PAUSE_ON_THRES                     "fctl_gont"
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BOFFSET   16
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BLEN      8
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_FLAG      HSL_RW
+
+#define GOL_PAUSE_OFF_THRES                    "fctl_gofft"
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BOFFSET  0
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BLEN     8
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_FLAG     HSL_RW
+
+
+
+
+    /* Flow Control1 Register */
+#define FLOW_CTL1                  "fctl1"
+#define FLOW_CTL1_ID               6
+#define FLOW_CTL1_OFFSET           0x0038
+#define FLOW_CTL1_E_LENGTH         4
+#define FLOW_CTL1_E_OFFSET         0
+#define FLOW_CTL1_NR_E             1
+
+#define PORT_PAUSE_ON_THRES                    "fctl1_pont"
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BOFFSET  16
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BLEN     8
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_FLAG     HSL_RW
+
+#define PORT_PAUSE_OFF_THRES                   "fctl1_pofft"
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BOFFSET 0
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BLEN    8
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_FLAG    HSL_RW
+
+
+
+
+    /* QM Control Register */
+#define QM_CTL                    "qmct"
+#define QM_CTL_ID                 7
+#define QM_CTL_OFFSET             0x003c
+#define QM_CTL_E_LENGTH           4
+#define QM_CTL_E_OFFSET           0
+#define QM_CTL_NR_E               1
+
+#define QM_ERR_RST_EN                         "qmct_qeren"
+#define QM_CTL_QM_ERR_RST_EN_BOFFSET          31
+#define QM_CTL_QM_ERR_RST_EN_BLEN             1
+#define QM_CTL_QM_ERR_RST_EN_FLAG             HSL_RW
+
+#define LOOKUP_ERR_RST_EN                     "qmct_lpesen"
+#define QM_CTL_LOOKUP_ERR_RST_EN_BOFFSET      30
+#define QM_CTL_LOOKUP_ERR_RST_EN_BLEN         1
+#define QM_CTL_LOOKUP_ERR_RST_EN_FLAG         HSL_RW
+
+#define IGMP_JOIN_STATIC                      "qmct_igmpjs"
+#define QM_CTL_IGMP_JOIN_STATIC_BOFFSET       24
+#define QM_CTL_IGMP_JOIN_STATIC_BLEN          4
+#define QM_CTL_IGMP_JOIN_STATIC_FLAG          HSL_RW
+
+#define IGMP_JOIN_LEAKY                       "qmct_igmpjl"
+#define QM_CTL_IGMP_JOIN_LEAKY_BOFFSET        23
+#define QM_CTL_IGMP_JOIN_LEAKY_BLEN           1
+#define QM_CTL_IGMP_JOIN_LEAKY_FLAG           HSL_RW
+
+#define IGMP_CREAT_EN                         "qmct_igmpcrt"
+#define QM_CTL_IGMP_CREAT_EN_BOFFSET          22
+#define QM_CTL_IGMP_CREAT_EN_BLEN             1
+#define QM_CTL_IGMP_CREAT_EN_FLAG             HSL_RW
+
+#define ACL_EN                                "qmct_aclen"
+#define QM_CTL_ACL_EN_BOFFSET                 21
+#define QM_CTL_ACL_EN_BLEN                    1
+#define QM_CTL_ACL_EN_FLAG                    HSL_RW
+
+#define PPPOE_RDT_EN                          "qmct_pppoerdten"
+#define QM_CTL_PPPOE_RDT_EN_BOFFSET           20
+#define QM_CTL_PPPOE_RDT_EN_BLEN              1
+#define QM_CTL_PPPOE_RDT_EN_FLAG              HSL_RW
+
+#define IGMP_V3_EN                            "qmct_igmpv3e"
+#define QM_CTL_IGMP_V3_EN_BOFFSET             19
+#define QM_CTL_IGMP_V3_EN_BLEN                1
+#define QM_CTL_IGMP_V3_EN_FLAG                HSL_RW
+
+#define IGMP_PRI_EN                           "qmct_igmpprie"
+#define QM_CTL_IGMP_PRI_EN_BOFFSET            18
+#define QM_CTL_IGMP_PRI_EN_BLEN               1
+#define QM_CTL_IGMP_PRI_EN_FLAG               HSL_RW
+
+#define IGMP_PRI                              "qmct_igmppri"
+#define QM_CTL_IGMP_PRI_BOFFSET               16
+#define QM_CTL_IGMP_PRI_BLEN                  2
+#define QM_CTL_IGMP_PRI_FLAG                  HSL_RW
+
+#define ARP_EN                                "qmct_arpe"
+#define QM_CTL_ARP_EN_BOFFSET                 15
+#define QM_CTL_ARP_EN_BLEN                    1
+#define QM_CTL_ARP_EN_FLAG                    HSL_RW
+
+#define ARP_CMD                               "qmct_arpc"
+#define QM_CTL_ARP_CMD_BOFFSET                14
+#define QM_CTL_ARP_CMD_BLEN                   1
+#define QM_CTL_ARP_CMD_FLAG                   HSL_RW
+
+#define RIP_CPY_EN                            "qmct_ripcpyen"
+#define QM_CTL_RIP_CPY_EN_BOFFSET             13
+#define QM_CTL_RIP_CPY_EN_BLEN                1
+#define QM_CTL_RIP_CPY_EN_FLAG                HSL_RW
+
+#define EAPOL_CMD                             "qmct_eapolc"
+#define QM_CTL_EAPOL_CMD_BOFFSET              12
+#define QM_CTL_EAPOL_CMD_BLEN                 1
+#define QM_CTL_EAPOL_CMD_FLAG                 HSL_RW
+
+#define IGMP_COPY_EN                          "qmct_igmpcpy"
+#define QM_CTL_IGMP_COPY_EN_BOFFSET           11
+#define QM_CTL_IGMP_COPY_EN_BLEN              1
+#define QM_CTL_IGMP_COPY_EN_FLAG              HSL_RW
+
+#define PPPOE_EN                              "qmct_pppoeen"
+#define QM_CTL_PPPOE_EN_BOFFSET               10
+#define QM_CTL_PPPOE_EN_BLEN                  1
+#define QM_CTL_PPPOE_EN_FLAG                  HSL_RW
+
+#define QM_FUNC_TEST                          "qmct_qmft"
+#define QM_CTL_QM_FUNC_TEST_BOFFSET           9
+#define QM_CTL_QM_FUNC_TEST_BLEN              1
+#define QM_CTL_QM_FUNC_TEST_FLAG              HSL_RW
+
+#define MS_FC_EN                              "qmct_msfe"
+#define QM_CTL_MS_FC_EN_BOFFSET               8
+#define QM_CTL_MS_FC_EN_BLEN                  1
+#define QM_CTL_MS_FC_EN_FLAG                  HSL_RW
+
+#define FLOW_DROP_EN                          "qmct_fden"
+#define QM_CTL_FLOW_DROP_EN_BOFFSET           7
+#define QM_CTL_FLOW_DROP_EN_BLEN              1
+#define QM_CTL_FLOW_DROP_EN_FLAG              HSL_RW
+
+#define MANAGE_VID_VIO_DROP_EN                "qmct_mden"
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BOFFSET 6
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BLEN    1
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_FLAG    HSL_RW
+
+#define FLOW_DROP_CNT                         "qmct_fdcn"
+#define QM_CTL_FLOW_DROP_CNT_BOFFSET          0
+#define QM_CTL_FLOW_DROP_CNT_BLEN             6
+#define QM_CTL_FLOW_DROP_CNT_FLAG             HSL_RW
+
+
+    /* Vlan Table Function Register */
+#define VLAN_TABLE_FUNC0           "vtbf0"
+#define VLAN_TABLE_FUNC0_ID        9
+#define VLAN_TABLE_FUNC0_OFFSET    0x0040
+#define VLAN_TABLE_FUNC0_E_LENGTH  4
+#define VLAN_TABLE_FUNC0_E_OFFSET  0
+#define VLAN_TABLE_FUNC0_NR_E      1
+
+#define VT_PRI_EN                              "vtbf_vtpen"
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET     31
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN        1
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG        HSL_RW
+
+#define VT_PRI                                 "vtbf_vtpri"
+#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET        28
+#define VLAN_TABLE_FUNC0_VT_PRI_BLEN           3
+#define VLAN_TABLE_FUNC0_VT_PRI_FLAG           HSL_RW
+
+#define VLAN_ID                                "vtbf_vid"
+#define VLAN_TABLE_FUNC0_VLAN_ID_BOFFSET       16
+#define VLAN_TABLE_FUNC0_VLAN_ID_BLEN          12
+#define VLAN_TABLE_FUNC0_VLAN_ID_FLAG          HSL_RW
+
+#define VT_PORT_NUM                            "vtbf_vtpn"
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BOFFSET   8
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BLEN      4
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_FLAG      HSL_RW
+
+#define VT_FULL_VIO                            "vtbf_vtflv"
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BOFFSET   4
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BLEN      1
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_FLAG      HSL_RW
+
+#define VT_BUSY                                "vtbf_vtbs"
+#define VLAN_TABLE_FUNC0_VT_BUSY_BOFFSET       3
+#define VLAN_TABLE_FUNC0_VT_BUSY_BLEN          1
+#define VLAN_TABLE_FUNC0_VT_BUSY_FLAG          HSL_RW
+
+#define VT_FUNC                                "vtbf_vtfc"
+#define VLAN_TABLE_FUNC0_VT_FUNC_BOFFSET       0
+#define VLAN_TABLE_FUNC0_VT_FUNC_BLEN          3
+#define VLAN_TABLE_FUNC0_VT_FUNC_FLAG          HSL_RW
+
+#define VLAN_TABLE_FUNC1           "vtbf1"
+#define VLAN_TABLE_FUNC1_ID        10
+#define VLAN_TABLE_FUNC1_OFFSET    0x0044
+#define VLAN_TABLE_FUNC1_E_LENGTH  4
+#define VLAN_TABLE_FUNC1_E_OFFSET  0
+#define VLAN_TABLE_FUNC1_NR_E      1
+
+#define VT_VALID                               "vtbf_vtvd"
+#define VLAN_TABLE_FUNC1_VT_VALID_BOFFSET      11
+#define VLAN_TABLE_FUNC1_VT_VALID_BLEN         1
+#define VLAN_TABLE_FUNC1_VT_VALID_FLAG         HSL_RW
+
+#define VID_MEM                                "vtbf_vidm"
+#define VLAN_TABLE_FUNC1_VID_MEM_BOFFSET       0
+#define VLAN_TABLE_FUNC1_VID_MEM_BLEN          7
+#define VLAN_TABLE_FUNC1_VID_MEM_FLAG          HSL_RW
+
+
+    /* Address Table Function Register */
+#define ADDR_TABLE_FUNC0           "atbf0"
+#define ADDR_TABLE_FUNC0_ID        11
+#define ADDR_TABLE_FUNC0_OFFSET    0x0050
+#define ADDR_TABLE_FUNC0_E_LENGTH  4
+#define ADDR_TABLE_FUNC0_E_OFFSET  0
+#define ADDR_TABLE_FUNC0_NR_E      1
+
+#define AT_ADDR_BYTE4                          "atbf_adb4"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 24
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE5                          "atbf_adb5"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 16
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN    8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG    HSL_RW
+
+#define AT_FULL_VIO                            "atbf_atfv"
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BOFFSET   12
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BLEN      1
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_FLAG      HSL_RW
+
+#define AT_PORT_NUM                            "atbf_atpn"
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BOFFSET   8
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BLEN      4
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_FLAG      HSL_RW
+
+#define FLUSH_ST_EN                            "atbf_fsen"
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BOFFSET   4
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BLEN      1
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_FLAG      HSL_RW
+
+#define AT_BUSY                                "atbf_atbs"
+#define ADDR_TABLE_FUNC0_AT_BUSY_BOFFSET       3
+#define ADDR_TABLE_FUNC0_AT_BUSY_BLEN          1
+#define ADDR_TABLE_FUNC0_AT_BUSY_FLAG          HSL_RW
+
+#define AT_FUNC                                "atbf_atfc"
+#define ADDR_TABLE_FUNC0_AT_FUNC_BOFFSET       0
+#define ADDR_TABLE_FUNC0_AT_FUNC_BLEN          3
+#define ADDR_TABLE_FUNC0_AT_FUNC_FLAG          HSL_RW
+
+#define ADDR_TABLE_FUNC1           "atbf1"
+#define ADDR_TABLE_FUNC1_ID        12
+#define ADDR_TABLE_FUNC1_OFFSET    0x0054
+#define ADDR_TABLE_FUNC1_E_LENGTH  4
+#define ADDR_TABLE_FUNC1_E_OFFSET  0
+#define ADDR_TABLE_FUNC1_NR_E      0
+
+#define AT_ADDR_BYTE0                          "atbf_adb0"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 24
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE1                          "atbf_adb1"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 16
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE2                          "atbf_adb2"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BOFFSET 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_FLAG    HSL_RW
+
+#define AT_ADDR_BYTE3                          "atbf_adb3"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BOFFSET 0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BLEN    8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_FLAG    HSL_RW
+
+#define ADDR_TABLE_FUNC2           "atbf2"
+#define ADDR_TABLE_FUNC2_ID        13
+#define ADDR_TABLE_FUNC2_OFFSET    0x0058
+#define ADDR_TABLE_FUNC2_E_LENGTH  4
+#define ADDR_TABLE_FUNC2_E_OFFSET  0
+#define ADDR_TABLE_FUNC2_NR_E      0
+
+#define COPY_TO_CPU                            "atbf_cpcpu"
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET   26
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN      1
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG      HSL_RW
+
+#define REDRCT_TO_CPU                          "atbf_rdcpu"
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 25
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN    1
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG    HSL_RW
+
+#define LEAKY_EN                               "atbf_lkyen"
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET      24
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN         1
+#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG         HSL_RW
+
+#define AT_STATUS                              "atbf_atsts"
+#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET     16
+#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN        4
+#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG        HSL_RW
+
+#define CLONE_EN                               "atbf_clone"
+#define ADDR_TABLE_FUNC2_CLONE_EN_BOFFSET      15
+#define ADDR_TABLE_FUNC2_CLONE_EN_BLEN         1
+#define ADDR_TABLE_FUNC2_CLONE_EN_FLAG         HSL_RW
+
+#define SA_DROP_EN                             "atbf_saden"
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BOFFSET    14
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BLEN       1
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_FLAG       HSL_RW
+
+#define MIRROR_EN                              "atbf_miren"
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BOFFSET     13
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BLEN        1
+#define ADDR_TABLE_FUNC2_MIRROR_EN_FLAG        HSL_RW
+
+#define AT_PRI_EN                              "atbf_atpen"
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BOFFSET     12
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BLEN        1
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_FLAG        HSL_RW
+
+#define AT_PRI                                 "atbf_atpri"
+#define ADDR_TABLE_FUNC2_AT_PRI_BOFFSET        10
+#define ADDR_TABLE_FUNC2_AT_PRI_BLEN           2
+#define ADDR_TABLE_FUNC2_AT_PRI_FLAG           HSL_RW
+
+#define CROSS_PT                               "atbf_cpt"
+#define ADDR_TABLE_FUNC2_CROSS_PT_BOFFSET      8
+#define ADDR_TABLE_FUNC2_CROSS_PT_BLEN         1
+#define ADDR_TABLE_FUNC2_CROSS_PT_FLAG         HSL_RW
+
+#define DES_PORT                               "atbf_desp"
+#define ADDR_TABLE_FUNC2_DES_PORT_BOFFSET      0
+#define ADDR_TABLE_FUNC2_DES_PORT_BLEN         7
+#define ADDR_TABLE_FUNC2_DES_PORT_FLAG         HSL_RW
+
+
+    /* FDB entry Register0 */
+#define FDB_TABLE_FUNC0           "fdb0"
+#define FDB_TABLE_FUNC0_ID        11
+#define FDB_TABLE_FUNC0_OFFSET    0x30000
+#define FDB_TABLE_FUNC0_E_LENGTH  4
+#define FDB_TABLE_FUNC0_E_OFFSET  0
+#define FDB_TABLE_FUNC0_NR_E      1
+
+#define FDB_ADDR_BYTE2
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE2_BOFFSET 24
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE2_BLEN    8
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE2_FLAG    HSL_RW
+
+#define FDB_ADDR_BYTE3
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE3_BOFFSET 16
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE3_BLEN    8
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE3_FLAG    HSL_RW
+
+#define FDB_ADDR_BYTE4
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE4_BOFFSET 8
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE4_BLEN    8
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE4_FLAG    HSL_RW
+
+#define FDB_ADDR_BYTE5
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE5_BOFFSET 0
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE5_BLEN    8
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE5_FLAG    HSL_RW
+
+
+    /* FDB entry Register1 */
+#define FDB_TABLE_FUNC1           "fdb1"
+#define FDB_TABLE_FUNC1_ID        11
+#define FDB_TABLE_FUNC1_OFFSET    0x30004
+#define FDB_TABLE_FUNC1_E_LENGTH  4
+#define FDB_TABLE_FUNC1_E_OFFSET  0
+#define FDB_TABLE_FUNC1_NR_E      1
+
+#define FDB_MACCLONE_EN
+#define FDB_TABLE_FUNC1_FDB_MACCLONE_EN_BOFFSET   31
+#define FDB_TABLE_FUNC1_FDB_MACCLONE_EN_BLEN      1
+#define FDB_TABLE_FUNC1_FDB_MACCLONE_EN_FLAG      HSL_RW
+
+#define FDB_SADROP_EN
+#define FDB_TABLE_FUNC1_FDB_SADROP_EN_BOFFSET     30
+#define FDB_TABLE_FUNC1_FDB_SADROP_EN_BLEN        1
+#define FDB_TABLE_FUNC1_FDB_SADROP_EN_FLAG        HSL_RW
+
+#define FDB_MIRROR_EN
+#define FDB_TABLE_FUNC1_FDB_MIRROR_EN_BOFFSET     29
+#define FDB_TABLE_FUNC1_FDB_MIRROR_EN_BLEN        1
+#define FDB_TABLE_FUNC1_FDB_MIRROR_EN_FLAG        HSL_RW
+
+#define FDB_PRIORITY_EN
+#define FDB_TABLE_FUNC1_FDB_PRIORITY_EN_BOFFSET   28
+#define FDB_TABLE_FUNC1_FDB_PRIORITY_EN_BLEN      1
+#define FDB_TABLE_FUNC1_FDB_PRIORITY_EN_FLAG      HSL_RW
+
+#define FDB_PRIORITY
+#define FDB_TABLE_FUNC1_FDB_PRIORITY_BOFFSET      26
+#define FDB_TABLE_FUNC1_FDB_PRIORITY_BLEN         2
+#define FDB_TABLE_FUNC1_FDB_PRIORITY_FLAG         HSL_RW
+
+#define FDB_CROSS_STATE
+#define FDB_TABLE_FUNC1_FDB_CROSS_STATE_BOFFSET   24
+#define FDB_TABLE_FUNC1_FDB_CROSS_STATE_BLEN      1
+#define FDB_TABLE_FUNC1_FDB_CROSS_STATE_FLAG      HSL_RW
+
+#define FDB_DES_PORT
+#define FDB_TABLE_FUNC1_FDB_DES_PORT_BOFFSET      16
+#define FDB_TABLE_FUNC1_FDB_DES_PORT_BLEN         7
+#define FDB_TABLE_FUNC1_FDB_DES_PORT_FLAG         HSL_RW
+
+#define FDB_ADDR_BYTE0
+#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE0_BOFFSET    8
+#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE0_BLEN       8
+#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE0_FLAG       HSL_RW
+
+#define FDB_ADDR_BYTE1
+#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE1_BOFFSET    0
+#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE1_BLEN       8
+#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE1_FLAG       HSL_RW
+
+
+    /* FDB entry Register2 */
+#define FDB_TABLE_FUNC2           "fdb2"
+#define FDB_TABLE_FUNC2_ID        11
+#define FDB_TABLE_FUNC2_OFFSET    0x30008
+#define FDB_TABLE_FUNC2_E_LENGTH  4
+#define FDB_TABLE_FUNC2_E_OFFSET  0
+#define FDB_TABLE_FUNC2_NR_E      1
+
+#define FDB_CPYCPU_EN
+#define FDB_TABLE_FUNC2_FDB_CPYCPU_EN_BOFFSET   6
+#define FDB_TABLE_FUNC2_FDB_CPYCPU_EN_BLEN      1
+#define FDB_TABLE_FUNC2_FDB_CPYCPU_EN_FLAG      HSL_RW
+
+#define FDB_RDTCPU_EN
+#define FDB_TABLE_FUNC2_FDB_RDTCPU_EN_BOFFSET   5
+#define FDB_TABLE_FUNC2_FDB_RDTCPU_EN_BLEN      1
+#define FDB_TABLE_FUNC2_FDB_RDTCPU_EN_FLAG      HSL_RW
+
+#define FDB_LEANKY_EN
+#define FDB_TABLE_FUNC2_FDB_LEANKY_EN_BOFFSET   4
+#define FDB_TABLE_FUNC2_FDB_LEANKY_EN_BLEN      1
+#define FDB_TABLE_FUNC2_FDB_LEANKY_EN_FLAG      HSL_RW
+
+#define FDB_STATUS
+#define FDB_TABLE_FUNC2_FDB_STATUS_BOFFSET      0
+#define FDB_TABLE_FUNC2_FDB_STATUS_BLEN         4
+#define FDB_TABLE_FUNC2_FDB_STATUS_FLAG         HSL_RW
+
+
+    /* Address Table Control Register */
+#define ADDR_TABLE_CTL            "atbc"
+#define ADDR_TABLE_CTL_ID         14
+#define ADDR_TABLE_CTL_OFFSET     0x005C
+#define ADDR_TABLE_CTL_E_LENGTH   4
+#define ADDR_TABLE_CTL_E_OFFSET   0
+#define ADDR_TABLE_CTL_NR_E       1
+
+#define LOOP_CHK_TIME                          "atbc_lctime"
+#define ADDR_TABLE_CTL_LOOP_CHK_TIME_BOFFSET   24
+#define ADDR_TABLE_CTL_LOOP_CHK_TIME_BLEN      3
+#define ADDR_TABLE_CTL_LOOP_CHK_TIME_FLAG      HSL_RW
+
+#define RESVID_DROP                            "atbc_rviddrop"
+#define ADDR_TABLE_CTL_RESVID_DROP_BOFFSET     22
+#define ADDR_TABLE_CTL_RESVID_DROP_BLEN        1
+#define ADDR_TABLE_CTL_RESVID_DROP_FLAG        HSL_RW
+
+#define STAG_MODE                              "atbc_stag"
+#define ADDR_TABLE_CTL_STAG_MODE_BOFFSET       21
+#define ADDR_TABLE_CTL_STAG_MODE_BLEN          1
+#define ADDR_TABLE_CTL_STAG_MODE_FLAG          HSL_RW
+
+#define ARL_INI_EN                             "atbc_arlie"
+#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET      19
+#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN         1
+#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG         HSL_RW
+
+#define LEARN_CHANGE_EN                        "atbc_lcen"
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 18
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN    1
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG    HSL_RW
+
+#define AGE_EN                                 "atbc_agee"
+#define ADDR_TABLE_CTL_AGE_EN_BOFFSET          17
+#define ADDR_TABLE_CTL_AGE_EN_BLEN             1
+#define ADDR_TABLE_CTL_AGE_EN_FLAG             HSL_RW
+
+#define AGE_TIME                               "atbc_aget"
+#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET        0
+#define ADDR_TABLE_CTL_AGE_TIME_BLEN           16
+#define ADDR_TABLE_CTL_AGE_TIME_FLAG           HSL_RW
+
+
+    /* IP Priority Mapping Register */
+#define IP_PRI_MAPPING            "imap"
+#define IP_PRI_MAPPING_ID         15
+#define IP_PRI_MAPPING_OFFSET     0x0060
+#define IP_PRI_MAPPING_E_LENGTH   4
+#define IP_PRI_MAPPING_E_OFFSET   0
+#define IP_PRI_MAPPING_NR_E       1
+
+
+    /* IP Priority Mapping Register */
+#define IP_PRI_MAPPING0            "imap0"
+#define IP_PRI_MAPPING0_ID         15
+#define IP_PRI_MAPPING0_OFFSET     0x0060
+#define IP_PRI_MAPPING0_E_LENGTH   4
+#define IP_PRI_MAPPING0_E_OFFSET   0
+#define IP_PRI_MAPPING0_NR_E       0
+
+#define IP_0X3C                                "imap_ip3c"
+#define IP_PRI_MAPPING0_IP_0X3C_BOFFSET        30
+#define IP_PRI_MAPPING0_IP_0X3C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X3C_FLAG           HSL_RW
+
+#define IP_0X38                                "imap_ip38"
+#define IP_PRI_MAPPING0_IP_0X38_BOFFSET        28
+#define IP_PRI_MAPPING0_IP_0X38_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X38_FLAG           HSL_RW
+
+#define IP_0X34                                "imap_ip34"
+#define IP_PRI_MAPPING0_IP_0X34_BOFFSET        26
+#define IP_PRI_MAPPING0_IP_0X34_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X34_FLAG           HSL_RW
+
+#define IP_0X30                                "imap_ip30"
+#define IP_PRI_MAPPING0_IP_0X30_BOFFSET        24
+#define IP_PRI_MAPPING0_IP_0X30_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X30_FLAG           HSL_RW
+
+#define IP_0X2C                                "imap_ip2c"
+#define IP_PRI_MAPPING0_IP_0X2C_BOFFSET        22
+#define IP_PRI_MAPPING0_IP_0X2C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X2C_FLAG           HSL_RW
+
+#define IP_0X28                                "imap_ip28"
+#define IP_PRI_MAPPING0_IP_0X28_BOFFSET        20
+#define IP_PRI_MAPPING0_IP_0X28_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X28_FLAG           HSL_RW
+
+#define IP_0X24                                "imap_ip24"
+#define IP_PRI_MAPPING0_IP_0X24_BOFFSET        18
+#define IP_PRI_MAPPING0_IP_0X24_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X24_FLAG           HSL_RW
+
+#define IP_0X20                                "imap_ip20"
+#define IP_PRI_MAPPING0_IP_0X20_BOFFSET        16
+#define IP_PRI_MAPPING0_IP_0X20_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X20_FLAG           HSL_RW
+
+#define IP_0X1C                                "imap_ip1c"
+#define IP_PRI_MAPPING0_IP_0X1C_BOFFSET        14
+#define IP_PRI_MAPPING0_IP_0X1C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X1C_FLAG           HSL_RW
+
+#define IP_0X18                                "imap_ip18"
+#define IP_PRI_MAPPING0_IP_0X18_BOFFSET        12
+#define IP_PRI_MAPPING0_IP_0X18_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X18_FLAG           HSL_RW
+
+#define IP_0X14                                "imap_ip14"
+#define IP_PRI_MAPPING0_IP_0X14_BOFFSET        10
+#define IP_PRI_MAPPING0_IP_0X14_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X14_FLAG           HSL_RW
+
+#define IP_0X10                                "imap_ip10"
+#define IP_PRI_MAPPING0_IP_0X10_BOFFSET        8
+#define IP_PRI_MAPPING0_IP_0X10_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X10_FLAG           HSL_RW
+
+#define IP_0X0C                                "imap_ip0c"
+#define IP_PRI_MAPPING0_IP_0X0C_BOFFSET        6
+#define IP_PRI_MAPPING0_IP_0X0C_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X0C_FLAG           HSL_RW
+
+#define IP_0X08                                "imap_ip08"
+#define IP_PRI_MAPPING0_IP_0X08_BOFFSET        4
+#define IP_PRI_MAPPING0_IP_0X08_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X08_FLAG           HSL_RW
+
+#define IP_0X04                                "imap_ip04"
+#define IP_PRI_MAPPING0_IP_0X04_BOFFSET        2
+#define IP_PRI_MAPPING0_IP_0X04_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X04_FLAG           HSL_RW
+
+#define IP_0X00                                "imap_ip00"
+#define IP_PRI_MAPPING0_IP_0X00_BOFFSET        0
+#define IP_PRI_MAPPING0_IP_0X00_BLEN           2
+#define IP_PRI_MAPPING0_IP_0X00_FLAG           HSL_RW
+
+#define IP_PRI_MAPPING1            "imap1"
+#define IP_PRI_MAPPING1_ID         16
+#define IP_PRI_MAPPING1_OFFSET     0x0064
+#define IP_PRI_MAPPING1_E_LENGTH   4
+#define IP_PRI_MAPPING1_E_OFFSET   0
+#define IP_PRI_MAPPING1_NR_E       0
+
+#define IP_0X7C                                "imap_ip7c"
+#define IP_PRI_MAPPING1_IP_0X7C_BOFFSET        30
+#define IP_PRI_MAPPING1_IP_0X7C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X7C_FLAG           HSL_RW
+
+#define IP_0X78                                "imap_ip78"
+#define IP_PRI_MAPPING1_IP_0X78_BOFFSET        28
+#define IP_PRI_MAPPING1_IP_0X78_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X78_FLAG           HSL_RW
+
+#define IP_0X74                                "imap_ip74"
+#define IP_PRI_MAPPING1_IP_0X74_BOFFSET        26
+#define IP_PRI_MAPPING1_IP_0X74_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X74_FLAG           HSL_RW
+
+#define IP_0X70                                "imap_ip70"
+#define IP_PRI_MAPPING1_IP_0X70_BOFFSET        24
+#define IP_PRI_MAPPING1_IP_0X70_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X70_FLAG           HSL_RW
+
+#define IP_0X6C                                "imap_ip6c"
+#define IP_PRI_MAPPING1_IP_0X6C_BOFFSET        22
+#define IP_PRI_MAPPING1_IP_0X6C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X6C_FLAG           HSL_RW
+
+#define IP_0X68                                "imap_ip68"
+#define IP_PRI_MAPPING1_IP_0X68_BOFFSET        20
+#define IP_PRI_MAPPING1_IP_0X68_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X68_FLAG           HSL_RW
+
+#define IP_0X64                                "imap_ip64"
+#define IP_PRI_MAPPING1_IP_0X64_BOFFSET        18
+#define IP_PRI_MAPPING1_IP_0X64_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X64_FLAG           HSL_RW
+
+#define IP_0X60                                "imap_ip60"
+#define IP_PRI_MAPPING1_IP_0X60_BOFFSET        16
+#define IP_PRI_MAPPING1_IP_0X60_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X60_FLAG           HSL_RW
+
+#define IP_0X5C                                "imap_ip5c"
+#define IP_PRI_MAPPING1_IP_0X5C_BOFFSET        14
+#define IP_PRI_MAPPING1_IP_0X5C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X5C_FLAG           HSL_RW
+
+#define IP_0X58                                "imap_ip58"
+#define IP_PRI_MAPPING1_IP_0X58_BOFFSET        12
+#define IP_PRI_MAPPING1_IP_0X58_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X58_FLAG           HSL_RW
+
+#define IP_0X54                                "imap_ip54"
+#define IP_PRI_MAPPING1_IP_0X54_BOFFSET        10
+#define IP_PRI_MAPPING1_IP_0X54_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X54_FLAG           HSL_RW
+
+#define IP_0X50                                "imap_ip50"
+#define IP_PRI_MAPPING1_IP_0X50_BOFFSET        8
+#define IP_PRI_MAPPING1_IP_0X50_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X50_FLAG           HSL_RW
+
+#define IP_0X4C                                "imap_ip4c"
+#define IP_PRI_MAPPING1_IP_0X4C_BOFFSET        6
+#define IP_PRI_MAPPING1_IP_0X4C_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X4C_FLAG           HSL_RW
+
+#define IP_0X48                                "imap_ip48"
+#define IP_PRI_MAPPING1_IP_0X48_BOFFSET        4
+#define IP_PRI_MAPPING1_IP_0X48_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X48_FLAG           HSL_RW
+
+#define IP_0X44                                "imap_ip44"
+#define IP_PRI_MAPPING1_IP_0X44_BOFFSET        2
+#define IP_PRI_MAPPING1_IP_0X44_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X44_FLAG           HSL_RW
+
+#define IP_0X40                                "imap_ip40"
+#define IP_PRI_MAPPING1_IP_0X40_BOFFSET        0
+#define IP_PRI_MAPPING1_IP_0X40_BLEN           2
+#define IP_PRI_MAPPING1_IP_0X40_FLAG           HSL_RW
+
+
+#define IP_PRI_MAPPING2            "imap2"
+#define IP_PRI_MAPPING2_ID         17
+#define IP_PRI_MAPPING2_OFFSET     0x0068
+#define IP_PRI_MAPPING2_E_LENGTH   4
+#define IP_PRI_MAPPING2_E_OFFSET   0
+#define IP_PRI_MAPPING2_NR_E       0
+
+#define IP_0XBC                                "imap_ipbc"
+#define IP_PRI_MAPPING2_IP_0XBC_BOFFSET        30
+#define IP_PRI_MAPPING2_IP_0XBC_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XBC_FLAG           HSL_RW
+
+#define IP_0XB8                                "imap_ipb8"
+#define IP_PRI_MAPPING2_IP_0XB8_BOFFSET        28
+#define IP_PRI_MAPPING2_IP_0XB8_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XB8_FLAG           HSL_RW
+
+#define IP_0XB4                                "imap_ipb4"
+#define IP_PRI_MAPPING2_IP_0XB4_BOFFSET        26
+#define IP_PRI_MAPPING2_IP_0XB4_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XB4_FLAG           HSL_RW
+
+#define IP_0XB0                                "imap_ipb0"
+#define IP_PRI_MAPPING2_IP_0XB0_BOFFSET        24
+#define IP_PRI_MAPPING2_IP_0XB0_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XB0_FLAG           HSL_RW
+
+#define IP_0XAC                                "imap_ipac"
+#define IP_PRI_MAPPING2_IP_0XAC_BOFFSET        22
+#define IP_PRI_MAPPING2_IP_0XAC_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XAC_FLAG           HSL_RW
+
+#define IP_0XA8                                "imap_ipa8"
+#define IP_PRI_MAPPING2_IP_0XA8_BOFFSET        20
+#define IP_PRI_MAPPING2_IP_0XA8_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XA8_FLAG           HSL_RW
+
+#define IP_0XA4                                "imap_ipa4"
+#define IP_PRI_MAPPING2_IP_0XA4_BOFFSET        18
+#define IP_PRI_MAPPING2_IP_0XA4_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XA4_FLAG           HSL_RW
+
+#define IP_0XA0                                "imap_ipa0"
+#define IP_PRI_MAPPING2_IP_0XA0_BOFFSET        16
+#define IP_PRI_MAPPING2_IP_0XA0_BLEN           2
+#define IP_PRI_MAPPING2_IP_0XA0_FLAG           HSL_RW
+
+#define IP_0X9C                                "imap_ip9c"
+#define IP_PRI_MAPPING2_IP_0X9C_BOFFSET        14
+#define IP_PRI_MAPPING2_IP_0X9C_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X9C_FLAG           HSL_RW
+
+#define IP_0X98                                "imap_ip98"
+#define IP_PRI_MAPPING2_IP_0X98_BOFFSET        12
+#define IP_PRI_MAPPING2_IP_0X98_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X98_FLAG           HSL_RW
+
+#define IP_0X94                                "imap_ip94"
+#define IP_PRI_MAPPING2_IP_0X94_BOFFSET        10
+#define IP_PRI_MAPPING2_IP_0X94_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X94_FLAG           HSL_RW
+
+#define IP_0X90                                "imap_ip90"
+#define IP_PRI_MAPPING2_IP_0X90_BOFFSET        8
+#define IP_PRI_MAPPING2_IP_0X90_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X90_FLAG           HSL_RW
+
+#define IP_0X8C                                "imap_ip8c"
+#define IP_PRI_MAPPING2_IP_0X8C_BOFFSET        6
+#define IP_PRI_MAPPING2_IP_0X8C_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X8C_FLAG           HSL_RW
+
+#define IP_0X88                                "imap_ip88"
+#define IP_PRI_MAPPING2_IP_0X88_BOFFSET        4
+#define IP_PRI_MAPPING2_IP_0X88_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X88_FLAG           HSL_RW
+
+#define IP_0X84                                "imap_ip84"
+#define IP_PRI_MAPPING2_IP_0X84_BOFFSET        2
+#define IP_PRI_MAPPING2_IP_0X84_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X84_FLAG           HSL_RW
+
+#define IP_0X80                                "imap_ip80"
+#define IP_PRI_MAPPING2_IP_0X80_BOFFSET        0
+#define IP_PRI_MAPPING2_IP_0X80_BLEN           2
+#define IP_PRI_MAPPING2_IP_0X80_FLAG           HSL_RW
+
+#define IP_PRI_MAPPING3            "imap3"
+#define IP_PRI_MAPPING3_ID         18
+#define IP_PRI_MAPPING3_OFFSET     0x006C
+#define IP_PRI_MAPPING3_E_LENGTH   4
+#define IP_PRI_MAPPING3_E_OFFSET   0
+#define IP_PRI_MAPPING3_NR_E       0
+
+#define IP_0XFC                                "imap_ipfc"
+#define IP_PRI_MAPPING3_IP_0XFC_BOFFSET        30
+#define IP_PRI_MAPPING3_IP_0XFC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XFC_FLAG           HSL_RW
+
+#define IP_0XF8                                "imap_ipf8"
+#define IP_PRI_MAPPING3_IP_0XF8_BOFFSET        28
+#define IP_PRI_MAPPING3_IP_0XF8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XF8_FLAG           HSL_RW
+
+#define IP_0XF4                                "imap_ipf4"
+#define IP_PRI_MAPPING3_IP_0XF4_BOFFSET        26
+#define IP_PRI_MAPPING3_IP_0XF4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XF4_FLAG           HSL_RW
+
+#define IP_0XF0                                "imap_ipf0"
+#define IP_PRI_MAPPING3_IP_0XF0_BOFFSET        24
+#define IP_PRI_MAPPING3_IP_0XF0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XF0_FLAG           HSL_RW
+
+#define IP_0XEC                                "imap_ipec"
+#define IP_PRI_MAPPING3_IP_0XEC_BOFFSET        22
+#define IP_PRI_MAPPING3_IP_0XEC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XEC_FLAG           HSL_RW
+
+#define IP_0XE8                                "imap_ipe8"
+#define IP_PRI_MAPPING3_IP_0XE8_BOFFSET        20
+#define IP_PRI_MAPPING3_IP_0XE8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XE8_FLAG           HSL_RW
+
+#define IP_0XE4                                "imap_ipe4"
+#define IP_PRI_MAPPING3_IP_0XE4_BOFFSET        18
+#define IP_PRI_MAPPING3_IP_0XE4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XE4_FLAG           HSL_RW
+
+#define IP_0XE0                                "imap_ipe0"
+#define IP_PRI_MAPPING3_IP_0XE0_BOFFSET        16
+#define IP_PRI_MAPPING3_IP_0XE0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XE0_FLAG           HSL_RW
+
+#define IP_0XDC                                "imap_ipdc"
+#define IP_PRI_MAPPING3_IP_0XDC_BOFFSET        14
+#define IP_PRI_MAPPING3_IP_0XDC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XDC_FLAG           HSL_RW
+
+#define IP_0XD8                                "imap_ipd8"
+#define IP_PRI_MAPPING3_IP_0XD8_BOFFSET        12
+#define IP_PRI_MAPPING3_IP_0XD8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XD8_FLAG           HSL_RW
+
+#define IP_0XD4                                "imap_ipd4"
+#define IP_PRI_MAPPING3_IP_0XD4_BOFFSET        10
+#define IP_PRI_MAPPING3_IP_0XD4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XD4_FLAG           HSL_RW
+
+#define IP_0XD0                                "imap_ipd0"
+#define IP_PRI_MAPPING3_IP_0XD0_BOFFSET        8
+#define IP_PRI_MAPPING3_IP_0XD0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XD0_FLAG           HSL_RW
+
+#define IP_0XCC                                "imap_ipcc"
+#define IP_PRI_MAPPING3_IP_0XCC_BOFFSET        6
+#define IP_PRI_MAPPING3_IP_0XCC_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XCC_FLAG           HSL_RW
+
+#define IP_0XC8                                "imap_ipc8"
+#define IP_PRI_MAPPING3_IP_0XC8_BOFFSET        4
+#define IP_PRI_MAPPING3_IP_0XC8_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XC8_FLAG           HSL_RW
+
+#define IP_0XC4                                "imap_ipc4"
+#define IP_PRI_MAPPING3_IP_0XC4_BOFFSET        2
+#define IP_PRI_MAPPING3_IP_0XC4_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XC4_FLAG           HSL_RW
+
+#define IP_0XC0                                "imap_ipc0"
+#define IP_PRI_MAPPING3_IP_0XC0_BOFFSET        0
+#define IP_PRI_MAPPING3_IP_0XC0_BLEN           2
+#define IP_PRI_MAPPING3_IP_0XC0_FLAG           HSL_RW
+
+
+    /* Tag Priority Mapping Register */
+#define TAG_PRI_MAPPING           "tpmap"
+#define TAG_PRI_MAPPING_ID        19
+#define TAG_PRI_MAPPING_OFFSET    0x0070
+#define TAG_PRI_MAPPING_E_LENGTH  4
+#define TAG_PRI_MAPPING_E_OFFSET  0
+#define TAG_PRI_MAPPING_NR_E      1
+
+#define TAG_0X07                                "tpmap_tg07"
+#define TAG_PRI_MAPPING_TAG_0X07_BOFFSET      14
+#define TAG_PRI_MAPPING_TAG_0X07_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X07_FLAG         HSL_RW
+
+#define TAG_0X06                              "tpmap_tg06"
+#define TAG_PRI_MAPPING_TAG_0X06_BOFFSET      12
+#define TAG_PRI_MAPPING_TAG_0X06_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X06_FLAG         HSL_RW
+
+#define TAG_0X05                              "tpmap_tg05"
+#define TAG_PRI_MAPPING_TAG_0X05_BOFFSET      10
+#define TAG_PRI_MAPPING_TAG_0X05_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X05_FLAG         HSL_RW
+
+#define TAG_0X04                              "tpmap_tg04"
+#define TAG_PRI_MAPPING_TAG_0X04_BOFFSET      8
+#define TAG_PRI_MAPPING_TAG_0X04_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X04_FLAG         HSL_RW
+
+#define TAG_0X03                              "tpmap_tg03"
+#define TAG_PRI_MAPPING_TAG_0X03_BOFFSET      6
+#define TAG_PRI_MAPPING_TAG_0X03_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X03_FLAG         HSL_RW
+
+#define TAG_0X02                              "tpmap_tg02"
+#define TAG_PRI_MAPPING_TAG_0X02_BOFFSET      4
+#define TAG_PRI_MAPPING_TAG_0X02_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X02_FLAG         HSL_RW
+
+#define TAG_0X01                              "tpmap_tg01"
+#define TAG_PRI_MAPPING_TAG_0X01_BOFFSET      2
+#define TAG_PRI_MAPPING_TAG_0X01_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X01_FLAG         HSL_RW
+
+#define TAG_0X00                              "tpmap_tg00"
+#define TAG_PRI_MAPPING_TAG_0X00_BOFFSET      0
+#define TAG_PRI_MAPPING_TAG_0X00_BLEN         2
+#define TAG_PRI_MAPPING_TAG_0X00_FLAG         HSL_RW
+
+
+    /* Service tag Register */
+#define SERVICE_TAG                  "servicetag"
+#define SERVICE_TAG_ID               20
+#define SERVICE_TAG_OFFSET           0x0074
+#define SERVICE_TAG_E_LENGTH         4
+#define SERVICE_TAG_E_OFFSET         0
+#define SERVICE_TAG_NR_E             1
+
+#define TAG_VALUE                        "servicetag_val"
+#define SERVICE_TAG_TAG_VALUE_BOFFSET    0
+#define SERVICE_TAG_TAG_VALUE_BLEN       16
+#define SERVICE_TAG_TAG_VALUE_FLAG       HSL_RW
+
+
+    /* Cpu Port Register */
+#define CPU_PORT                  "cpup"
+#define CPU_PORT_ID               20
+#define CPU_PORT_OFFSET           0x0078
+#define CPU_PORT_E_LENGTH         4
+#define CPU_PORT_E_OFFSET         0
+#define CPU_PORT_NR_E             0
+
+#define CPU_PORT_EN                           "cpup_cpupe"
+#define CPU_PORT_CPU_PORT_EN_BOFFSET          8
+#define CPU_PORT_CPU_PORT_EN_BLEN             1
+#define CPU_PORT_CPU_PORT_EN_FLAG             HSL_RW
+
+#define MIRROR_PORT_NUM                       "cpup_mirpn"
+#define CPU_PORT_MIRROR_PORT_NUM_BOFFSET      4
+#define CPU_PORT_MIRROR_PORT_NUM_BLEN         4
+#define CPU_PORT_MIRROR_PORT_NUM_FLAG         HSL_RW
+
+
+    /* MIB Function Register */
+#define MIB_FUNC                  "mibfunc"
+#define MIB_FUNC_ID               21
+#define MIB_FUNC_OFFSET           0x0080
+#define MIB_FUNC_E_LENGTH         4
+#define MIB_FUNC_E_OFFSET         0
+#define MIB_FUNC_NR_E             1
+
+#define MAC_CRC_EN                            "mibfunc_crcen"
+#define MIB_FUNC_MAC_CRC_EN_BOFFSET            31
+#define MIB_FUNC_MAC_CRC_EN_BLEN               1
+#define MIB_FUNC_MAC_CRC_EN_FLAG               HSL_RW
+
+#define MIB_EN                               "mib_en"
+#define MIB_FUNC_MIB_EN_BOFFSET              30
+#define MIB_FUNC_MIB_EN_BLEN                 1
+#define MIB_FUNC_MIB_EN_FLAG                 HSL_RW
+
+#define MIB_FUN                              "mibfunc_mibf"
+#define MIB_FUNC_MIB_FUN_BOFFSET              24
+#define MIB_FUNC_MIB_FUN_BLEN                 3
+#define MIB_FUNC_MIB_FUN_FLAG                 HSL_RW
+
+#define MIB_BUSY                              "mibfunc_mibb"
+#define MIB_FUNC_MIB_BUSY_BOFFSET              17
+#define MIB_FUNC_MIB_BUSY_BLEN                 1
+#define MIB_FUNC_MIB_BUSY_FLAG                 HSL_RW
+
+#define MIB_AT_HALF_EN                        "mibfunc_mibhe"
+#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET        16
+#define MIB_FUNC_MIB_AT_HALF_EN_BLEN           1
+#define MIB_FUNC_MIB_AT_HALF_EN_FLAG           HSL_RW
+
+#define MIB_TIMER                             "mibfunc_mibt"
+#define MIB_FUNC_MIB_TIMER_BOFFSET             0
+#define MIB_FUNC_MIB_TIMER_BLEN                16
+#define MIB_FUNC_MIB_TIMER_FLAG                HSL_RW
+
+
+    /* Mdio control Register */
+#define MDIO_CTRL               "mctrl"
+#define MDIO_CTRL_ID            24
+#define MDIO_CTRL_OFFSET        0x0098
+#define MDIO_CTRL_E_LENGTH      4
+#define MDIO_CTRL_E_OFFSET      0
+#define MDIO_CTRL_NR_E          1
+
+#define MSTER_EN                        "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET      30
+#define MDIO_CTRL_MSTER_EN_BLEN         1
+#define MDIO_CTRL_MSTER_EN_FLAG         HSL_RW
+
+#define MSTER_EN                        "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET      30
+#define MDIO_CTRL_MSTER_EN_BLEN         1
+#define MDIO_CTRL_MSTER_EN_FLAG         HSL_RW
+
+#define CMD                             "mctrl_cmd"
+#define MDIO_CTRL_CMD_BOFFSET           27
+#define MDIO_CTRL_CMD_BLEN              1
+#define MDIO_CTRL_CMD_FLAG              HSL_RW
+
+#define SUP_PRE                         "mctrl_spre"
+#define MDIO_CTRL_SUP_PRE_BOFFSET       26
+#define MDIO_CTRL_SUP_PRE_BLEN          1
+#define MDIO_CTRL_SUP_PRE_FLAG          HSL_RW
+
+#define PHY_ADDR                        "mctrl_phyaddr"
+#define MDIO_CTRL_PHY_ADDR_BOFFSET      21
+#define MDIO_CTRL_PHY_ADDR_BLEN         5
+#define MDIO_CTRL_PHY_ADDR_FLAG         HSL_RW
+
+#define REG_ADDR                        "mctrl_regaddr"
+#define MDIO_CTRL_REG_ADDR_BOFFSET      16
+#define MDIO_CTRL_REG_ADDR_BLEN         5
+#define MDIO_CTRL_REG_ADDR_FLAG         HSL_RW
+
+#define DATA                            "mctrl_data"
+#define MDIO_CTRL_DATA_BOFFSET          0
+#define MDIO_CTRL_DATA_BLEN             16
+#define MDIO_CTRL_DATA_FLAG             HSL_RW
+
+
+
+
+    /* BIST control Register */
+#define BIST_CTRL               "bctrl"
+#define BIST_CTRL_ID            24
+#define BIST_CTRL_OFFSET        0x00a0
+#define BIST_CTRL_E_LENGTH      4
+#define BIST_CTRL_E_OFFSET      0
+#define BIST_CTRL_NR_E          1
+
+#define BIST_BUSY                        "bctrl_bb"
+#define BIST_CTRL_BIST_BUSY_BOFFSET      31
+#define BIST_CTRL_BIST_BUSY_BLEN         1
+#define BIST_CTRL_BIST_BUSY_FLAG         HSL_RW
+
+#define ONE_ERR                          "bctrl_oe"
+#define BIST_CTRL_ONE_ERR_BOFFSET        30
+#define BIST_CTRL_ONE_ERR_BLEN           1
+#define BIST_CTRL_ONE_ERR_FLAG           HSL_RO
+
+#define ERR_MEM                          "bctrl_em"
+#define BIST_CTRL_ERR_MEM_BOFFSET        24
+#define BIST_CTRL_ERR_MEM_BLEN           4
+#define BIST_CTRL_ERR_MEM_FLAG           HSL_RO
+
+#define PTN_EN2                          "bctrl_pe2"
+#define BIST_CTRL_PTN_EN2_BOFFSET        22
+#define BIST_CTRL_PTN_EN2_BLEN           1
+#define BIST_CTRL_PTN_EN2_FLAG           HSL_RW
+
+#define PTN_EN1                          "bctrl_pe1"
+#define BIST_CTRL_PTN_EN1_BOFFSET        21
+#define BIST_CTRL_PTN_EN1_BLEN           1
+#define BIST_CTRL_PTN_EN1_FLAG           HSL_RW
+
+#define PTN_EN0                          "bctrl_pe0"
+#define BIST_CTRL_PTN_EN0_BOFFSET        20
+#define BIST_CTRL_PTN_EN0_BLEN           1
+#define BIST_CTRL_PTN_EN0_FLAG           HSL_RW
+
+#define ERR_PTN                          "bctrl_ep"
+#define BIST_CTRL_ERR_PTN_BOFFSET        16
+#define BIST_CTRL_ERR_PTN_BLEN           2
+#define BIST_CTRL_ERR_PTN_FLAG           HSL_RO
+
+#define ERR_CNT                          "bctrl_ec"
+#define BIST_CTRL_ERR_CNT_BOFFSET        13
+#define BIST_CTRL_ERR_CNT_BLEN           2
+#define BIST_CTRL_ERR_CNT_FLAG           HSL_RO
+
+#define ERR_ADDR                         "bctrl_ea"
+#define BIST_CTRL_ERR_ADDR_BOFFSET       0
+#define BIST_CTRL_ERR_ADDR_BLEN          12
+#define BIST_CTRL_ERR_ADDR_FLAG          HSL_RO
+
+
+
+
+    /* BIST recover Register */
+#define BIST_RCV               "brcv"
+#define BIST_RCV_ID            24
+#define BIST_RCV_OFFSET        0x00a4
+#define BIST_RCV_E_LENGTH      4
+#define BIST_RCV_E_OFFSET      0
+#define BIST_RCV_NR_E          1
+
+#define RCV_EN                           "brcv_en"
+#define BIST_RCV_RCV_EN_BOFFSET          31
+#define BIST_RCV_RCV_EN_BLEN             1
+#define BIST_RCV_RCV_EN_FLAG             HSL_RW
+
+#define RCV_ADDR                         "brcv_addr"
+#define BIST_RCV_RCV_ADDR_BOFFSET        0
+#define BIST_RCV_RCV_ADDR_BLEN           12
+#define BIST_RCV_RCV_ADDR_FLAG           HSL_RW
+
+
+
+
+    /* LED control Register */
+#define LED_CTRL               "ledctrl"
+#define LED_CTRL_ID            25
+#define LED_CTRL_OFFSET        0x00b0
+#define LED_CTRL_E_LENGTH      4
+#define LED_CTRL_E_OFFSET      0
+#define LED_CTRL_NR_E          1
+
+#define PATTERN_EN                           "lctrl_pen"
+#define LED_CTRL_PATTERN_EN_BOFFSET          14
+#define LED_CTRL_PATTERN_EN_BLEN             2
+#define LED_CTRL_PATTERN_EN_FLAG             HSL_RW
+
+#define FULL_LIGHT_EN                        "lctrl_fen"
+#define LED_CTRL_FULL_LIGHT_EN_BOFFSET       13
+#define LED_CTRL_FULL_LIGHT_EN_BLEN          1
+#define LED_CTRL_FULL_LIGHT_EN_FLAG          HSL_RW
+
+#define HALF_LIGHT_EN                        "lctrl_hen"
+#define LED_CTRL_HALF_LIGHT_EN_BOFFSET       12
+#define LED_CTRL_HALF_LIGHT_EN_BLEN          1
+#define LED_CTRL_HALF_LIGHT_EN_FLAG          HSL_RW
+
+#define POWERON_LIGHT_EN                     "lctrl_poen"
+#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET    11
+#define LED_CTRL_POWERON_LIGHT_EN_BLEN       1
+#define LED_CTRL_POWERON_LIGHT_EN_FLAG       HSL_RW
+
+#define GE_LIGHT_EN                          "lctrl_geen"
+#define LED_CTRL_GE_LIGHT_EN_BOFFSET         10
+#define LED_CTRL_GE_LIGHT_EN_BLEN            1
+#define LED_CTRL_GE_LIGHT_EN_FLAG            HSL_RW
+
+#define FE_LIGHT_EN                          "lctrl_feen"
+#define LED_CTRL_FE_LIGHT_EN_BOFFSET         9
+#define LED_CTRL_FE_LIGHT_EN_BLEN            1
+#define LED_CTRL_FE_LIGHT_EN_FLAG            HSL_RW
+
+#define ETH_LIGHT_EN                         "lctrl_ethen"
+#define LED_CTRL_ETH_LIGHT_EN_BOFFSET        8
+#define LED_CTRL_ETH_LIGHT_EN_BLEN           1
+#define LED_CTRL_ETH_LIGHT_EN_FLAG           HSL_RW
+
+#define COL_BLINK_EN                         "lctrl_cen"
+#define LED_CTRL_COL_BLINK_EN_BOFFSET        7
+#define LED_CTRL_COL_BLINK_EN_BLEN           1
+#define LED_CTRL_COL_BLINK_EN_FLAG           HSL_RW
+
+#define RX_BLINK_EN                          "lctrl_rxen"
+#define LED_CTRL_RX_BLINK_EN_BOFFSET         5
+#define LED_CTRL_RX_BLINK_EN_BLEN            1
+#define LED_CTRL_RX_BLINK_EN_FLAG            HSL_RW
+
+#define TX_BLINK_EN                          "lctrl_txen"
+#define LED_CTRL_TX_BLINK_EN_BOFFSET         4
+#define LED_CTRL_TX_BLINK_EN_BLEN            1
+#define LED_CTRL_TX_BLINK_EN_FLAG            HSL_RW
+
+#define LINKUP_OVER_EN                       "lctrl_loen"
+#define LED_CTRL_LINKUP_OVER_EN_BOFFSET      2
+#define LED_CTRL_LINKUP_OVER_EN_BLEN         1
+#define LED_CTRL_LINKUP_OVER_EN_FLAG         HSL_RW
+
+#define BLINK_FREQ                           "lctrl_bfreq"
+#define LED_CTRL_BLINK_FREQ_BOFFSET          0
+#define LED_CTRL_BLINK_FREQ_BLEN             2
+#define LED_CTRL_BLINK_FREQ_FLAG             HSL_RW
+
+    /* LED control Register */
+#define LED_PATTERN               "ledpatten"
+#define LED_PATTERN_ID            25
+#define LED_PATTERN_OFFSET        0x00bc
+#define LED_PATTERN_E_LENGTH      4
+#define LED_PATTERN_E_OFFSET      0
+#define LED_PATTERN_NR_E          1
+
+#define P3L1_MODE                           "p3l1_mode"
+#define LED_PATTERN_P3L1_MODE_BOFFSET       24
+#define LED_PATTERN_P3L1_MODE_BLEN          2
+#define LED_PATTERN_P3L1_MODE_FLAG          HSL_RW
+
+#define P3L0_MODE                           "p3l0_mode"
+#define LED_PATTERN_P3L0_MODE_BOFFSET       22
+#define LED_PATTERN_P3L0_MODE_BLEN          2
+#define LED_PATTERN_P3L0_MODE_FLAG          HSL_RW
+
+#define P2L1_MODE                           "p2l1_mode"
+#define LED_PATTERN_P2L1_MODE_BOFFSET       20
+#define LED_PATTERN_P2L1_MODE_BLEN          2
+#define LED_PATTERN_P2L1_MODE_FLAG          HSL_RW
+
+#define P2L0_MODE                           "p2l0_mode"
+#define LED_PATTERN_P2L0_MODE_BOFFSET       18
+#define LED_PATTERN_P2L0_MODE_BLEN          2
+#define LED_PATTERN_P2L0_MODE_FLAG          HSL_RW
+
+#define P1L1_MODE                           "p1l1_mode"
+#define LED_PATTERN_P1L1_MODE_BOFFSET       16
+#define LED_PATTERN_P1L1_MODE_BLEN          2
+#define LED_PATTERN_P1L1_MODE_FLAG          HSL_RW
+
+#define P1L0_MODE                           "p1l0_mode"
+#define LED_PATTERN_P1L0_MODE_BOFFSET       14
+#define LED_PATTERN_P1L0_MODE_BLEN          2
+#define LED_PATTERN_P1L0_MODE_FLAG          HSL_RW
+
+#define M6_MODE                             "m6_mode"
+#define LED_PATTERN_M6_MODE_BOFFSET         12
+#define LED_PATTERN_M6_MODE_BLEN            2
+#define LED_PATTERN_M6_MODE_FLAG            HSL_RW
+
+#define M5_MODE                             "m5_mode"
+#define LED_PATTERN_M5_MODE_BOFFSET         10
+#define LED_PATTERN_M5_MODE_BLEN            2
+#define LED_PATTERN_M5_MODE_FLAG            HSL_RW
+
+
+    /* Port Status Register */
+#define PORT_STATUS               "ptsts"
+#define PORT_STATUS_ID            29
+#define PORT_STATUS_OFFSET        0x0100
+#define PORT_STATUS_E_LENGTH      4
+#define PORT_STATUS_E_OFFSET      0x0100
+#define PORT_STATUS_NR_E          7
+
+#define FLOW_LINK_EN                            "ptsts_flen"
+#define PORT_STATUS_FLOW_LINK_EN_BOFFSET        12
+#define PORT_STATUS_FLOW_LINK_EN_BLEN           1
+#define PORT_STATUS_FLOW_LINK_EN_FLAG           HSL_RW
+
+
+#define LINK_ASYN_PAUSE                         "ptsts_lasynp"
+#define PORT_STATUS_LINK_ASYN_PAUSE_BOFFSET     11
+#define PORT_STATUS_LINK_ASYN_PAUSE_BLEN        1
+#define PORT_STATUS_LINK_ASYN_PAUSE_FLAG        HSL_RO
+
+#define LINK_PAUSE                              "ptsts_lpause"
+#define PORT_STATUS_LINK_PAUSE_BOFFSET          10
+#define PORT_STATUS_LINK_PAUSE_BLEN             1
+#define PORT_STATUS_LINK_PAUSE_FLAG             HSL_RO
+
+#define LINK_EN                                 "ptsts_linken"
+#define PORT_STATUS_LINK_EN_BOFFSET             9
+#define PORT_STATUS_LINK_EN_BLEN                1
+#define PORT_STATUS_LINK_EN_FLAG                HSL_RW
+
+#define LINK                                    "ptsts_ptlink"
+#define PORT_STATUS_LINK_BOFFSET                8
+#define PORT_STATUS_LINK_BLEN                   1
+#define PORT_STATUS_LINK_FLAG                   HSL_RO
+
+#define TX_HALF_FLOW_EN
+#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET     7
+#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN        1
+#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG        HSL_RW
+
+#define DUPLEX_MODE                             "ptsts_dupmod"
+#define PORT_STATUS_DUPLEX_MODE_BOFFSET         6
+#define PORT_STATUS_DUPLEX_MODE_BLEN            1
+#define PORT_STATUS_DUPLEX_MODE_FLAG            HSL_RW
+
+#define RX_FLOW_EN                              "ptsts_rxfwen"
+#define PORT_STATUS_RX_FLOW_EN_BOFFSET          5
+#define PORT_STATUS_RX_FLOW_EN_BLEN             1
+#define PORT_STATUS_RX_FLOW_EN_FLAG             HSL_RW
+
+#define TX_FLOW_EN                              "ptsts_txfwen"
+#define PORT_STATUS_TX_FLOW_EN_BOFFSET          4
+#define PORT_STATUS_TX_FLOW_EN_BLEN             1
+#define PORT_STATUS_TX_FLOW_EN_FLAG             HSL_RW
+
+#define RXMAC_EN                                "ptsts_rxmacen"
+#define PORT_STATUS_RXMAC_EN_BOFFSET            3
+#define PORT_STATUS_RXMAC_EN_BLEN               1
+#define PORT_STATUS_RXMAC_EN_FLAG               HSL_RW
+
+#define TXMAC_EN                                "ptsts_txmacen"
+#define PORT_STATUS_TXMAC_EN_BOFFSET            2
+#define PORT_STATUS_TXMAC_EN_BLEN               1
+#define PORT_STATUS_TXMAC_EN_FLAG               HSL_RW
+
+#define SPEED_MODE                              "ptsts_speed"
+#define PORT_STATUS_SPEED_MODE_BOFFSET          0
+#define PORT_STATUS_SPEED_MODE_BLEN             2
+#define PORT_STATUS_SPEED_MODE_FLAG             HSL_RW
+
+
+    /* Port Control Register */
+#define PORT_CTL                  "pctl"
+#define PORT_CTL_ID               30
+#define PORT_CTL_OFFSET           0x0104
+#define PORT_CTL_E_LENGTH         4
+#define PORT_CTL_E_OFFSET         0x0100
+#define PORT_CTL_NR_E             7
+
+#define EAPOL_EN                                "pctl_eapolen"
+#define PORT_CTL_EAPOL_EN_BOFFSET               23
+#define PORT_CTL_EAPOL_EN_BLEN                  1
+#define PORT_CTL_EAPOL_EN_FLAG                  HSL_RW
+
+#define ARP_LEAKY_EN                            "pbvlan_alen"
+#define PORT_CTL_ARP_LEAKY_EN_BOFFSET           22
+#define PORT_CTL_ARP_LEAKY_EN_BLEN              1
+#define PORT_CTL_ARP_LEAKY_EN_FLAG              HSL_RW
+
+#define LEAVE_EN                                "pctl_leaveen"
+#define PORT_CTL_LEAVE_EN_BOFFSET               21
+#define PORT_CTL_LEAVE_EN_BLEN                  1
+#define PORT_CTL_LEAVE_EN_FLAG                  HSL_RW
+
+#define JOIN_EN                                 "pctl_joinen"
+#define PORT_CTL_JOIN_EN_BOFFSET                20
+#define PORT_CTL_JOIN_EN_BLEN                   1
+#define PORT_CTL_JOIN_EN_FLAG                   HSL_RW
+
+#define DHCP_EN                                 "pctl_dhcpen"
+#define PORT_CTL_DHCP_EN_BOFFSET                19
+#define PORT_CTL_DHCP_EN_BLEN                   1
+#define PORT_CTL_DHCP_EN_FLAG                   HSL_RW
+
+#define ING_MIRROR_EN                           "pctl_ingmiren"
+#define PORT_CTL_ING_MIRROR_EN_BOFFSET          17
+#define PORT_CTL_ING_MIRROR_EN_BLEN             1
+#define PORT_CTL_ING_MIRROR_EN_FLAG             HSL_RW
+
+#define EG_MIRROR_EN                            "pctl_egmiren"
+#define PORT_CTL_EG_MIRROR_EN_BOFFSET           16
+#define PORT_CTL_EG_MIRROR_EN_BLEN              1
+#define PORT_CTL_EG_MIRROR_EN_FLAG              HSL_RW
+
+#define DTAG_EN                                 "pctl_dtagen"
+#define PORT_CTL_DTAG_EN_BOFFSET                15
+#define PORT_CTL_DTAG_EN_BLEN                   1
+#define PORT_CTL_DTAG_EN_FLAG                   HSL_RW
+
+#define LEARN_EN                                "pctl_learnen"
+#define PORT_CTL_LEARN_EN_BOFFSET               14
+#define PORT_CTL_LEARN_EN_BLEN                  1
+#define PORT_CTL_LEARN_EN_FLAG                  HSL_RW
+
+#define SINGLE_VLAN_EN                          "pctl_svlanen"
+#define PORT_CTL_SINGLE_VLAN_EN_BOFFSET         13
+#define PORT_CTL_SINGLE_VLAN_EN_BLEN            1
+#define PORT_CTL_SINGLE_VLAN_EN_FLAG            HSL_RW
+
+#define MAC_LOOP_BACK                           "pctl_maclp"
+#define PORT_CTL_MAC_LOOP_BACK_BOFFSET          12
+#define PORT_CTL_MAC_LOOP_BACK_BLEN             1
+#define PORT_CTL_MAC_LOOP_BACK_FLAG             HSL_RW
+
+#define HEAD_EN                                 "pctl_headen"
+#define PORT_CTL_HEAD_EN_BOFFSET                11
+#define PORT_CTL_HEAD_EN_BLEN                   1
+#define PORT_CTL_HEAD_EN_FLAG                   HSL_RW
+
+#define IGMP_MLD_EN                             "pctl_imlden"
+#define PORT_CTL_IGMP_MLD_EN_BOFFSET            10
+#define PORT_CTL_IGMP_MLD_EN_BLEN               1
+#define PORT_CTL_IGMP_MLD_EN_FLAG               HSL_RW
+
+#define EG_VLAN_MODE                            "pctl_egvmode"
+#define PORT_CTL_EG_VLAN_MODE_BOFFSET           8
+#define PORT_CTL_EG_VLAN_MODE_BLEN              2
+#define PORT_CTL_EG_VLAN_MODE_FLAG              HSL_RW
+
+#define LEARN_ONE_LOCK                          "pctl_lonelck"
+#define PORT_CTL_LEARN_ONE_LOCK_BOFFSET         7
+#define PORT_CTL_LEARN_ONE_LOCK_BLEN            1
+#define PORT_CTL_LEARN_ONE_LOCK_FLAG            HSL_RW
+
+#define PORT_LOCK_EN                            "pctl_locken"
+#define PORT_CTL_PORT_LOCK_EN_BOFFSET           6
+#define PORT_CTL_PORT_LOCK_EN_BLEN              1
+#define PORT_CTL_PORT_LOCK_EN_FLAG              HSL_RW
+
+#define LOCK_DROP_EN                            "pctl_dropen"
+#define PORT_CTL_LOCK_DROP_EN_BOFFSET           5
+#define PORT_CTL_LOCK_DROP_EN_BLEN              1
+#define PORT_CTL_LOCK_DROP_EN_FLAG              HSL_RW
+
+#define PORT_STATE                              "pctl_pstate"
+#define PORT_CTL_PORT_STATE_BOFFSET             0
+#define PORT_CTL_PORT_STATE_BLEN                3
+#define PORT_CTL_PORT_STATE_FLAG                HSL_RW
+
+
+    /* Port dot1ad Register */
+#define PORT_DOT1AD            "pdot1ad"
+#define PORT_DOT1AD_ID         31
+#define PORT_DOT1AD_OFFSET     0x0108
+#define PORT_DOT1AD_E_LENGTH   4
+#define PORT_DOT1AD_E_OFFSET   0x0100
+#define PORT_DOT1AD_NR_E       7
+
+#define ING_PRI                              "pdot1ad_ingpri"
+#define PORT_DOT1AD_ING_PRI_BOFFSET          29
+#define PORT_DOT1AD_ING_PRI_BLEN             3
+#define PORT_DOT1AD_ING_PRI_FLAG             HSL_RW
+
+#define FORCE_PVLAN                          "pdot1ad_fpvlan"
+#define PORT_DOT1AD_FORCE_PVLAN_BOFFSET      28
+#define PORT_DOT1AD_FORCE_PVLAN_BLEN         1
+#define PORT_DOT1AD_FORCE_PVLAN_FLAG         HSL_RW
+
+#define DEF_CVID                             "pdot1ad_dcvid"
+#define PORT_DOT1AD_DEF_CVID_BOFFSET         16
+#define PORT_DOT1AD_DEF_CVID_BLEN            12
+#define PORT_DOT1AD_DEF_CVID_FLAG            HSL_RW
+
+#define CLONE                                "pdot1ad_clone"
+#define PORT_DOT1AD_CLONE_BOFFSET            15
+#define PORT_DOT1AD_CLONE_BLEN               1
+#define PORT_DOT1AD_CLONE_FLAG               HSL_RW
+
+#define PROPAGATION_EN                       "pdot1ad_pen"
+#define PORT_DOT1AD_PROPAGATION_EN_BOFFSET   14
+#define PORT_DOT1AD_PROPAGATION_EN_BLEN      1
+#define PORT_DOT1AD_PROPAGATION_EN_FLAG      HSL_RW
+
+#define TLS_EN                               "pdot1ad_tlsen"
+#define PORT_DOT1AD_TLS_EN_BOFFSET           13
+#define PORT_DOT1AD_TLS_EN_BLEN              1
+#define PORT_DOT1AD_TLS_EN_FLAG              HSL_RW
+
+#define FORCE_DEF_VID                        "pbot1ad_fdvid"
+#define PORT_DOT1AD_FORCE_DEF_VID_BOFFSET    12
+#define PORT_DOT1AD_FORCE_DEF_VID_BLEN       1
+#define PORT_DOT1AD_FORCE_DEF_VID_FLAG       HSL_RW
+
+#define DEF_SVID                             "pdot1ad_dsvid"
+#define PORT_DOT1AD_DEF_SVID_BOFFSET         0
+#define PORT_DOT1AD_DEF_SVID_BLEN            12
+#define PORT_DOT1AD_DEF_SVID_FLAG            HSL_RW
+
+
+    /* Port Based Vlan Register */
+#define PORT_BASE_VLAN            "pbvlan"
+#define PORT_BASE_VLAN_ID         31
+#define PORT_BASE_VLAN_OFFSET     0x010c
+#define PORT_BASE_VLAN_E_LENGTH   4
+#define PORT_BASE_VLAN_E_OFFSET   0x0100
+#define PORT_BASE_VLAN_NR_E       7
+
+#define DOT1Q_MODE                              "pbvlan_8021q"
+#define PORT_BASE_VLAN_DOT1Q_MODE_BOFFSET       30
+#define PORT_BASE_VLAN_DOT1Q_MODE_BLEN          2
+#define PORT_BASE_VLAN_DOT1Q_MODE_FLAG          HSL_RW
+
+#define COREP_EN                                "pbvlan_corepen"
+#define PORT_BASE_VLAN_COREP_EN_BOFFSET         29
+#define PORT_BASE_VLAN_COREP_EN_BLEN            1
+#define PORT_BASE_VLAN_COREP_EN_FLAG            HSL_RW
+
+#define IN_VLAN_MODE                            "pbvlan_imode"
+#define PORT_BASE_VLAN_IN_VLAN_MODE_BOFFSET     27
+#define PORT_BASE_VLAN_IN_VLAN_MODE_BLEN        2
+#define PORT_BASE_VLAN_IN_VLAN_MODE_FLAG        HSL_RW
+
+#define PRI_PROPAGATION                         "pbvlan_prip"
+#define PORT_BASE_VLAN_PRI_PROPAGATION_BOFFSET  23
+#define PORT_BASE_VLAN_PRI_PROPAGATION_BLEN     1
+#define PORT_BASE_VLAN_PRI_PROPAGATION_FLAG     HSL_RW
+
+#define PORT_VID_MEM                            "pbvlan_pvidm"
+#define PORT_BASE_VLAN_PORT_VID_MEM_BOFFSET     16
+#define PORT_BASE_VLAN_PORT_VID_MEM_BLEN        7
+#define PORT_BASE_VLAN_PORT_VID_MEM_FLAG        HSL_RW
+
+#define UNI_LEAKY_EN                            "pbvlan_ulen"
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_BOFFSET     14
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_BLEN        1
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_FLAG        HSL_RW
+
+#define MUL_LEAKY_EN                            "pbvlan_mlen"
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_BOFFSET     13
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_BLEN        1
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_FLAG        HSL_RW
+
+
+    /* Port Rate Limit0 Register */
+#define RATE_LIMIT0                "rlmt0"
+#define RATE_LIMIT0_ID             32
+#define RATE_LIMIT0_OFFSET         0x0110
+#define RATE_LIMIT0_E_LENGTH       4
+#define RATE_LIMIT0_E_OFFSET       0x0100
+#define RATE_LIMIT0_NR_E           7
+
+#define ADD_RATE_BYTE                          "rlmt_addbyte"
+#define RATE_LIMIT0_ADD_RATE_BYTE_BOFFSET      24
+#define RATE_LIMIT0_ADD_RATE_BYTE_BLEN         8
+#define RATE_LIMIT0_ADD_RATE_BYTE_FLAG         HSL_RW
+
+#define EG_RATE_EN                             "rlmt_egen"
+#define RATE_LIMIT0_EG_RATE_EN_BOFFSET         23
+#define RATE_LIMIT0_EG_RATE_EN_BLEN            1
+#define RATE_LIMIT0_EG_RATE_EN_FLAG            HSL_RW
+
+#define EG_MNG_RATE_EN                         "rlmt_egmngen"
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET     22
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN        1
+#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG        HSL_RW
+
+#define IN_MNG_RATE_EN                         "rlmt_inmngen"
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET     21
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN        1
+#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG        HSL_RW
+
+#define IN_MUL_RATE_EN                         "rlmt_inmulen"
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET     20
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN        1
+#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG        HSL_RW
+
+#define ING_RATE                               "rlmt_ingrate"
+#define RATE_LIMIT0_ING_RATE_BOFFSET           0
+#define RATE_LIMIT0_ING_RATE_BLEN              15
+#define RATE_LIMIT0_ING_RATE_FLAG              HSL_RW
+
+
+    /* Priority Control Register */
+#define PRI_CTL                   "prctl"
+#define PRI_CTL_ID                33
+#define PRI_CTL_OFFSET            0x0114
+#define PRI_CTL_E_LENGTH          4
+#define PRI_CTL_E_OFFSET          0x0100
+#define PRI_CTL_NR_E              7
+
+#define PORT_PRI_EN                             "prctl_ptprien"
+#define PRI_CTL_PORT_PRI_EN_BOFFSET             19
+#define PRI_CTL_PORT_PRI_EN_BLEN                1
+#define PRI_CTL_PORT_PRI_EN_FLAG                HSL_RW
+
+#define DA_PRI_EN                               "prctl_daprien"
+#define PRI_CTL_DA_PRI_EN_BOFFSET               18
+#define PRI_CTL_DA_PRI_EN_BLEN                  1
+#define PRI_CTL_DA_PRI_EN_FLAG                  HSL_RW
+
+#define VLAN_PRI_EN                             "prctl_vprien"
+#define PRI_CTL_VLAN_PRI_EN_BOFFSET             17
+#define PRI_CTL_VLAN_PRI_EN_BLEN                1
+#define PRI_CTL_VLAN_PRI_EN_FLAG                HSL_RW
+
+#define IP_PRI_EN                               "prctl_ipprien"
+#define PRI_CTL_IP_PRI_EN_BOFFSET               16
+#define PRI_CTL_IP_PRI_EN_BLEN                  1
+#define PRI_CTL_IP_PRI_EN_FLAG                  HSL_RW
+
+#define DA_PRI_SEL                              "prctl_dapris"
+#define PRI_CTL_DA_PRI_SEL_BOFFSET              6
+#define PRI_CTL_DA_PRI_SEL_BLEN                 2
+#define PRI_CTL_DA_PRI_SEL_FLAG                 HSL_RW
+
+#define VLAN_PRI_SEL                            "prctl_vpris"
+#define PRI_CTL_VLAN_PRI_SEL_BOFFSET            4
+#define PRI_CTL_VLAN_PRI_SEL_BLEN               2
+#define PRI_CTL_VLAN_PRI_SEL_FLAG               HSL_RW
+
+#define IP_PRI_SEL                              "prctl_ippris"
+#define PRI_CTL_IP_PRI_SEL_BOFFSET              2
+#define PRI_CTL_IP_PRI_SEL_BLEN                 2
+#define PRI_CTL_IP_PRI_SEL_FLAG                 HSL_RW
+
+#define PORT_PRI_SEL                            "prctl_ptpris"
+#define PRI_CTL_PORT_PRI_SEL_BOFFSET            0
+#define PRI_CTL_PORT_PRI_SEL_BLEN               2
+#define PRI_CTL_PORT_PRI_SEL_FLAG               HSL_RW
+
+
+    /* Storm Control Register */
+#define STORM_CTL                 "sctrl"
+#define STORM_CTL_ID                33
+#define STORM_CTL_OFFSET            0x0118
+#define STORM_CTL_E_LENGTH          4
+#define STORM_CTL_E_OFFSET          0x0100
+#define STORM_CTL_NR_E              7
+
+#define UNIT                             "sctrl_unit"
+#define STORM_CTL_UNIT_BOFFSET           24
+#define STORM_CTL_UNIT_BLEN              2
+#define STORM_CTL_UNIT_FLAG              HSL_RW
+
+#define MUL_EN                           "sctrl_mulen"
+#define STORM_CTL_MUL_EN_BOFFSET         10
+#define STORM_CTL_MUL_EN_BLEN            1
+#define STORM_CTL_MUL_EN_FLAG            HSL_RW
+
+#define UNI_EN                           "sctrl_unien"
+#define STORM_CTL_UNI_EN_BOFFSET         9
+#define STORM_CTL_UNI_EN_BLEN            1
+#define STORM_CTL_UNI_EN_FLAG            HSL_RW
+
+#define BRO_EN                           "sctrl_broen"
+#define STORM_CTL_BRO_EN_BOFFSET         8
+#define STORM_CTL_BRO_EN_BLEN            1
+#define STORM_CTL_BRO_EN_FLAG            HSL_RW
+
+#define RATE                             "sctrl_rate"
+#define STORM_CTL_RATE_BOFFSET           0
+#define STORM_CTL_RATE_BLEN              4
+#define STORM_CTL_RATE_FLAG              HSL_RW
+
+
+    /* Queue Control Register */
+#define QUEUE_CTL                   "qctl"
+#define QUEUE_CTL_ID                34
+#define QUEUE_CTL_OFFSET            0x011c
+#define QUEUE_CTL_E_LENGTH          4
+#define QUEUE_CTL_E_OFFSET          0x0100
+#define QUEUE_CTL_NR_E              7
+
+#define PORT_IN_DESC_EN                          "qctl_pdescen"
+#define QUEUE_CTL_PORT_IN_DESC_EN_BOFFSET        28
+#define QUEUE_CTL_PORT_IN_DESC_EN_BLEN           4
+#define QUEUE_CTL_PORT_IN_DESC_EN_FLAG           HSL_RW
+
+#define PORT_DESC_EN                             "qctl_pdescen"
+#define QUEUE_CTL_PORT_DESC_EN_BOFFSET           25
+#define QUEUE_CTL_PORT_DESC_EN_BLEN              1
+#define QUEUE_CTL_PORT_DESC_EN_FLAG              HSL_RW
+
+#define QUEUE_DESC_EN                            "qctl_qdescen"
+#define QUEUE_CTL_QUEUE_DESC_EN_BOFFSET          24
+#define QUEUE_CTL_QUEUE_DESC_EN_BLEN             1
+#define QUEUE_CTL_QUEUE_DESC_EN_FLAG             HSL_RW
+
+#define PORT_DESC_NR                             "qctl_pdscpnr"
+#define QUEUE_CTL_PORT_DESC_NR_BOFFSET           16
+#define QUEUE_CTL_PORT_DESC_NR_BLEN              6
+#define QUEUE_CTL_PORT_DESC_NR_FLAG              HSL_RW
+
+#define QUEUE3_DESC_NR                           "qctl_q3dscpnr"
+#define QUEUE_CTL_QUEUE3_DESC_NR_BOFFSET         12
+#define QUEUE_CTL_QUEUE3_DESC_NR_BLEN            4
+#define QUEUE_CTL_QUEUE3_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE2_DESC_NR                           "qctl_q2dscpnr"
+#define QUEUE_CTL_QUEUE2_DESC_NR_BOFFSET         8
+#define QUEUE_CTL_QUEUE2_DESC_NR_BLEN            4
+#define QUEUE_CTL_QUEUE2_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE1_DESC_NR                           "qctl_q1dscpnr"
+#define QUEUE_CTL_QUEUE1_DESC_NR_BOFFSET         4
+#define QUEUE_CTL_QUEUE1_DESC_NR_BLEN            4
+#define QUEUE_CTL_QUEUE1_DESC_NR_FLAG            HSL_RW
+
+#define QUEUE0_DESC_NR                           "qctl_q0dscpnr"
+#define QUEUE_CTL_QUEUE0_DESC_NR_BOFFSET         0
+#define QUEUE_CTL_QUEUE0_DESC_NR_BLEN            4
+#define QUEUE_CTL_QUEUE0_DESC_NR_FLAG            HSL_RW
+
+
+    /* Port Rate Limit1 Register */
+#define RATE_LIMIT1                "rlmt1"
+#define RATE_LIMIT1_ID             32
+#define RATE_LIMIT1_OFFSET         0x0120
+#define RATE_LIMIT1_E_LENGTH       4
+#define RATE_LIMIT1_E_OFFSET       0x0100
+#define RATE_LIMIT1_NR_E           7
+
+#define EG_Q1_RATE                              "rlmt_egq1rate"
+#define RATE_LIMIT1_EG_Q1_RATE_BOFFSET          16
+#define RATE_LIMIT1_EG_Q1_RATE_BLEN             15
+#define RATE_LIMIT1_EG_Q1_RATE_FLAG             HSL_RW
+
+#define EG_Q0_RATE                              "rlmt_egq0rate"
+#define RATE_LIMIT1_EG_Q0_RATE_BOFFSET          0
+#define RATE_LIMIT1_EG_Q0_RATE_BLEN             15
+#define RATE_LIMIT1_EG_Q0_RATE_FLAG             HSL_RW
+
+
+    /* Port Rate Limit2 Register */
+#define RATE_LIMIT2                "rlmt2"
+#define RATE_LIMIT2_ID             32
+#define RATE_LIMIT2_OFFSET         0x0124
+#define RATE_LIMIT2_E_LENGTH       4
+#define RATE_LIMIT2_E_OFFSET       0x0100
+#define RATE_LIMIT2_NR_E           7
+
+#define EG_Q3_RATE                              "rlmt_egq3rate"
+#define RATE_LIMIT2_EG_Q3_RATE_BOFFSET          16
+#define RATE_LIMIT2_EG_Q3_RATE_BLEN             15
+#define RATE_LIMIT2_EG_Q3_RATE_FLAG             HSL_RW
+
+#define EG_Q2_RATE                              "rlmt_egq2rate"
+#define RATE_LIMIT2_EG_Q2_RATE_BOFFSET          0
+#define RATE_LIMIT2_EG_Q2_RATE_BLEN             15
+#define RATE_LIMIT2_EG_Q2_RATE_FLAG             HSL_RW
+
+
+
+
+    /* Port Rate Limit3 Register */
+#define RATE_LIMIT3                "rlmt3"
+#define RATE_LIMIT3_ID             32
+#define RATE_LIMIT3_OFFSET         0x0128
+#define RATE_LIMIT3_E_LENGTH       4
+#define RATE_LIMIT3_E_OFFSET       0x0100
+#define RATE_LIMIT3_NR_E           7
+
+#define EG_Q3_CBS                              "rlmt_egq3cbs"
+#define RATE_LIMIT3_EG_Q3_CBS_BOFFSET          22
+#define RATE_LIMIT3_EG_Q3_CBS_BLEN             2
+#define RATE_LIMIT3_EG_Q3_CBS_FLAG             HSL_RW
+
+#define EG_Q2_CBS                              "rlmt_egq2cbs"
+#define RATE_LIMIT3_EG_Q2_CBS_BOFFSET          20
+#define RATE_LIMIT3_EG_Q2_CBS_BLEN             2
+#define RATE_LIMIT3_EG_Q2_CBS_FLAG             HSL_RW
+
+#define EG_Q1_CBS                              "rlmt_egq1cbs"
+#define RATE_LIMIT3_EG_Q1_CBS_BOFFSET          18
+#define RATE_LIMIT3_EG_Q1_CBS_BLEN             2
+#define RATE_LIMIT3_EG_Q1_CBS_FLAG             HSL_RW
+
+#define EG_Q0_CBS                              "rlmt_egq0cbs"
+#define RATE_LIMIT3_EG_Q0_CBS_BOFFSET          16
+#define RATE_LIMIT3_EG_Q0_CBS_BLEN             2
+#define RATE_LIMIT3_EG_Q0_CBS_FLAG             HSL_RW
+
+#define EG_TS                                  "rlmt_egts"
+#define RATE_LIMIT3_EG_TS_BOFFSET              0
+#define RATE_LIMIT3_EG_TS_BLEN                 3
+#define RATE_LIMIT3_EG_TS_FLAG                 HSL_RW
+
+
+
+
+    /* Port Rate Limit2 Register */
+#define WRR_CTRL                                "wrrc"
+#define WRR_CTRL_ID                             32
+#define WRR_CTRL_OFFSET                         0x012c
+#define WRR_CTRL_E_LENGTH                       4
+#define WRR_CTRL_E_OFFSET                       0x0100
+#define WRR_CTRL_NR_E                           7
+
+#define SCH_MODE                                "wrrc_mode"
+#define WRR_CTRL_SCH_MODE_BOFFSET               29
+#define WRR_CTRL_SCH_MODE_BLEN                  2
+#define WRR_CTRL_SCH_MODE_FLAG                  HSL_RW
+
+#define Q3_W                                    "wrrc_q3w"
+#define WRR_CTRL_Q3_W_BOFFSET                   24
+#define WRR_CTRL_Q3_W_BLEN                      5
+#define WRR_CTRL_Q3_W_FLAG                      HSL_RW
+
+#define Q2_W                                    "wrrc_q2w"
+#define WRR_CTRL_Q2_W_BOFFSET                   16
+#define WRR_CTRL_Q2_W_BLEN                      5
+#define WRR_CTRL_Q2_W_FLAG                      HSL_RW
+
+#define Q1_W                                    "wrrc_q1w"
+#define WRR_CTRL_Q1_W_BOFFSET                   8
+#define WRR_CTRL_Q1_W_BLEN                      5
+#define WRR_CTRL_Q1_W_FLAG                      HSL_RW
+
+#define Q0_W                                    "wrrc_q0w"
+#define WRR_CTRL_Q0_W_BOFFSET                   0
+#define WRR_CTRL_Q0_W_BLEN                      5
+#define WRR_CTRL_Q0_W_FLAG                      HSL_RW
+
+
+    /* mib memory info */
+#define MIB_RXBROAD                       "RxBroad"
+#define MIB_RXBROAD_ID                    34
+#define MIB_RXBROAD_OFFSET                0x20000
+#define MIB_RXBROAD_E_LENGTH              4
+#define MIB_RXBROAD_E_OFFSET              0x100
+#define MIB_RXBROAD_NR_E                  6
+
+#define MIB_RXPAUSE                       "RxPause"
+#define MIB_RXPAUSE_ID                    35
+#define MIB_RXPAUSE_OFFSET                0x20004
+#define MIB_RXPAUSE_E_LENGTH              4
+#define MIB_RXPAUSE_E_OFFSET              0x100
+#define MIB_RXPAUSE_NR_E                  6
+
+#define MIB_RXMULTI                       "RxMulti"
+#define MIB_RXMULTI_ID                    36
+#define MIB_RXMULTI_OFFSET                0x20008
+#define MIB_RXMULTI_E_LENGTH              4
+#define MIB_RXMULTI_E_OFFSET              0x100
+#define MIB_RXMULTI_NR_E                  6
+
+#define MIB_RXFCSERR                      "RxFcsErr"
+#define MIB_RXFCSERR_ID                   37
+#define MIB_RXFCSERR_OFFSET               0x2000c
+#define MIB_RXFCSERR_E_LENGTH             4
+#define MIB_RXFCSERR_E_OFFSET             0x100
+#define MIB_RXFCSERR_NR_E                 6
+
+#define MIB_RXALLIGNERR                   "RxAllignErr"
+#define MIB_RXALLIGNERR_ID                38
+#define MIB_RXALLIGNERR_OFFSET            0x20010
+#define MIB_RXALLIGNERR_E_LENGTH          4
+#define MIB_RXALLIGNERR_E_OFFSET          0x100
+#define MIB_RXALLIGNERR_NR_E              6
+
+#define MIB_RXRUNT                        "RxRunt"
+#define MIB_RXRUNT_ID                     39
+#define MIB_RXRUNT_OFFSET                 0x20014
+#define MIB_RXRUNT_E_LENGTH               4
+#define MIB_RXRUNT_E_OFFSET               0x100
+#define MIB_RXRUNT_NR_E                   6
+
+#define MIB_RXFRAGMENT                    "RxFragment"
+#define MIB_RXFRAGMENT_ID                 40
+#define MIB_RXFRAGMENT_OFFSET             0x20018
+#define MIB_RXFRAGMENT_E_LENGTH           4
+#define MIB_RXFRAGMENT_E_OFFSET           0x100
+#define MIB_RXFRAGMENT_NR_E               6
+
+#define MIB_RX64BYTE                      "Rx64Byte"
+#define MIB_RX64BYTE_ID                   41
+#define MIB_RX64BYTE_OFFSET               0x2001c
+#define MIB_RX64BYTE_E_LENGTH             4
+#define MIB_RX64BYTE_E_OFFSET             0x100
+#define MIB_RX64BYTE_NR_E                 6
+
+#define MIB_RX128BYTE                     "Rx128Byte"
+#define MIB_RX128BYTE_ID                  42
+#define MIB_RX128BYTE_OFFSET              0x20020
+#define MIB_RX128BYTE_E_LENGTH            4
+#define MIB_RX128BYTE_E_OFFSET            0x100
+#define MIB_RX128BYTE_NR_E                6
+
+#define MIB_RX256BYTE                     "Rx256Byte"
+#define MIB_RX256BYTE_ID                  43
+#define MIB_RX256BYTE_OFFSET              0x20024
+#define MIB_RX256BYTE_E_LENGTH            4
+#define MIB_RX256BYTE_E_OFFSET            0x100
+#define MIB_RX256BYTE_NR_E                6
+
+#define MIB_RX512BYTE                     "Rx512Byte"
+#define MIB_RX512BYTE_ID                  44
+#define MIB_RX512BYTE_OFFSET              0x20028
+#define MIB_RX512BYTE_E_LENGTH            4
+#define MIB_RX512BYTE_E_OFFSET            0x100
+#define MIB_RX512BYTE_NR_E                6
+
+#define MIB_RX1024BYTE                    "Rx1024Byte"
+#define MIB_RX1024BYTE_ID                 45
+#define MIB_RX1024BYTE_OFFSET             0x2002c
+#define MIB_RX1024BYTE_E_LENGTH           4
+#define MIB_RX1024BYTE_E_OFFSET           0x100
+#define MIB_RX1024BYTE_NR_E               6
+
+#define MIB_RX1518BYTE                    "Rx1518Byte"
+#define MIB_RX1518BYTE_ID                 45
+#define MIB_RX1518BYTE_OFFSET             0x20030
+#define MIB_RX1518BYTE_E_LENGTH           4
+#define MIB_RX1518BYTE_E_OFFSET           0x100
+#define MIB_RX1518BYTE_NR_E               6
+
+#define MIB_RXMAXBYTE                     "RxMaxByte"
+#define MIB_RXMAXBYTE_ID                  46
+#define MIB_RXMAXBYTE_OFFSET              0x20034
+#define MIB_RXMAXBYTE_E_LENGTH            4
+#define MIB_RXMAXBYTE_E_OFFSET            0x100
+#define MIB_RXMAXBYTE_NR_E                6
+
+#define MIB_RXTOOLONG                     "RxTooLong"
+#define MIB_RXTOOLONG_ID                  47
+#define MIB_RXTOOLONG_OFFSET              0x20038
+#define MIB_RXTOOLONG_E_LENGTH            4
+#define MIB_RXTOOLONG_E_OFFSET            0x100
+#define MIB_RXTOOLONG_NR_E                6
+
+#define MIB_RXGOODBYTE_LO                 "RxGoodByteLo"
+#define MIB_RXGOODBYTE_LO_ID              48
+#define MIB_RXGOODBYTE_LO_OFFSET          0x2003c
+#define MIB_RXGOODBYTE_LO_E_LENGTH        4
+#define MIB_RXGOODBYTE_LO_E_OFFSET        0x100
+#define MIB_RXGOODBYTE_LO_NR_E            6
+
+#define MIB_RXGOODBYTE_HI                 "RxGoodByteHi"
+#define MIB_RXGOODBYTE_HI_ID              49
+#define MIB_RXGOODBYTE_HI_OFFSET          0x20040
+#define MIB_RXGOODBYTE_HI_E_LENGTH        4
+#define MIB_RXGOODBYTE_HI_E_OFFSET        0x100
+#define MIB_RXGOODBYTE_HI_NR_E            6
+
+#define MIB_RXBADBYTE_LO                  "RxBadByteLo"
+#define MIB_RXBADBYTE_LO_ID               50
+#define MIB_RXBADBYTE_LO_OFFSET           0x20044
+#define MIB_RXBADBYTE_LO_E_LENGTH         4
+#define MIB_RXBADBYTE_LO_E_OFFSET         0x100
+#define MIB_RXBADBYTE_LO_NR_E             6
+
+#define MIB_RXBADBYTE_HI                  "RxBadByteHi"
+#define MIB_RXBADBYTE_HI_ID               51
+#define MIB_RXBADBYTE_HI_OFFSET           0x20048
+#define MIB_RXBADBYTE_HI_E_LENGTH         4
+#define MIB_RXBADBYTE_HI_E_OFFSET         0x100
+#define MIB_RXBADBYTE_HI_NR_E             6
+
+#define MIB_RXOVERFLOW                    "RxOverFlow"
+#define MIB_RXOVERFLOW_ID                 52
+#define MIB_RXOVERFLOW_OFFSET             0x2004c
+#define MIB_RXOVERFLOW_E_LENGTH           4
+#define MIB_RXOVERFLOW_E_OFFSET           0x100
+#define MIB_RXOVERFLOW_NR_E               6
+
+#define MIB_FILTERED                      "Filtered"
+#define MIB_FILTERED_ID                   53
+#define MIB_FILTERED_OFFSET               0x20050
+#define MIB_FILTERED_E_LENGTH             4
+#define MIB_FILTERED_E_OFFSET             0x100
+#define MIB_FILTERED_NR_E                 6
+
+#define MIB_TXBROAD                       "TxBroad"
+#define MIB_TXBROAD_ID                    54
+#define MIB_TXBROAD_OFFSET                0x20054
+#define MIB_TXBROAD_E_LENGTH              4
+#define MIB_TXBROAD_E_OFFSET              0x100
+#define MIB_TXBROAD_NR_E                  6
+
+#define MIB_TXPAUSE                       "TxPause"
+#define MIB_TXPAUSE_ID                    55
+#define MIB_TXPAUSE_OFFSET                0x20058
+#define MIB_TXPAUSE_E_LENGTH              4
+#define MIB_TXPAUSE_E_OFFSET              0x100
+#define MIB_TXPAUSE_NR_E                  6
+
+#define MIB_TXMULTI                       "TxMulti"
+#define MIB_TXMULTI_ID                    56
+#define MIB_TXMULTI_OFFSET                0x2005c
+#define MIB_TXMULTI_E_LENGTH              4
+#define MIB_TXMULTI_E_OFFSET              0x100
+#define MIB_TXMULTI_NR_E                  6
+
+#define MIB_TXUNDERRUN                    "TxUnderRun"
+#define MIB_TXUNDERRUN_ID                 57
+#define MIB_TXUNDERRUN_OFFSET             0x20060
+#define MIB_TXUNDERRUN_E_LENGTH           4
+#define MIB_TXUNDERRUN_E_OFFSET           0x100
+#define MIB_TXUNDERRUN_NR_E               6
+
+#define MIB_TX64BYTE                      "Tx64Byte"
+#define MIB_TX64BYTE_ID                   58
+#define MIB_TX64BYTE_OFFSET               0x20064
+#define MIB_TX64BYTE_E_LENGTH             4
+#define MIB_TX64BYTE_E_OFFSET             0x100
+#define MIB_TX64BYTE_NR_E                 6
+
+#define MIB_TX128BYTE                     "Tx128Byte"
+#define MIB_TX128BYTE_ID                  59
+#define MIB_TX128BYTE_OFFSET              0x20068
+#define MIB_TX128BYTE_E_LENGTH            4
+#define MIB_TX128BYTE_E_OFFSET            0x100
+#define MIB_TX128BYTE_NR_E                6
+
+#define MIB_TX256BYTE                     "Tx256Byte"
+#define MIB_TX256BYTE_ID                  60
+#define MIB_TX256BYTE_OFFSET              0x2006c
+#define MIB_TX256BYTE_E_LENGTH            4
+#define MIB_TX256BYTE_E_OFFSET            0x100
+#define MIB_TX256BYTE_NR_E                6
+
+#define MIB_TX512BYTE                     "Tx512Byte"
+#define MIB_TX512BYTE_ID                  61
+#define MIB_TX512BYTE_OFFSET              0x20070
+#define MIB_TX512BYTE_E_LENGTH            4
+#define MIB_TX512BYTE_E_OFFSET            0x100
+#define MIB_TX512BYTE_NR_E                6
+
+#define MIB_TX1024BYTE                    "Tx1024Byte"
+#define MIB_TX1024BYTE_ID                 62
+#define MIB_TX1024BYTE_OFFSET             0x20074
+#define MIB_TX1024BYTE_E_LENGTH           4
+#define MIB_TX1024BYTE_E_OFFSET           0x100
+#define MIB_TX1024BYTE_NR_E               6
+
+#define MIB_TX1518BYTE                    "Tx1518Byte"
+#define MIB_TX1518BYTE_ID                 62
+#define MIB_TX1518BYTE_OFFSET             0x20078
+#define MIB_TX1518BYTE_E_LENGTH           4
+#define MIB_TX1518BYTE_E_OFFSET           0x100
+#define MIB_TX1518BYTE_NR_E               6
+
+#define MIB_TXMAXBYTE                     "TxMaxByte"
+#define MIB_TXMAXBYTE_ID                  63
+#define MIB_TXMAXBYTE_OFFSET              0x2007c
+#define MIB_TXMAXBYTE_E_LENGTH            4
+#define MIB_TXMAXBYTE_E_OFFSET            0x100
+#define MIB_TXMAXBYTE_NR_E                6
+
+#define MIB_TXOVERSIZE                    "TxOverSize"
+#define MIB_TXOVERSIZE_ID                 64
+#define MIB_TXOVERSIZE_OFFSET             0x20080
+#define MIB_TXOVERSIZE_E_LENGTH           4
+#define MIB_TXOVERSIZE_E_OFFSET           0x100
+#define MIB_TXOVERSIZE_NR_E               6
+
+#define MIB_TXBYTE_LO                     "TxByteLo"
+#define MIB_TXBYTE_LO_ID                  65
+#define MIB_TXBYTE_LO_OFFSET              0x20084
+#define MIB_TXBYTE_LO_E_LENGTH            4
+#define MIB_TXBYTE_LO_E_OFFSET            0x100
+#define MIB_TXBYTE_LO_NR_E                6
+
+#define MIB_TXBYTE_HI                     "TxByteHi"
+#define MIB_TXBYTE_HI_ID                  66
+#define MIB_TXBYTE_HI_OFFSET              0x20088
+#define MIB_TXBYTE_HI_E_LENGTH            4
+#define MIB_TXBYTE_HI_E_OFFSET            0x100
+#define MIB_TXBYTE_HI_NR_E                6
+
+#define MIB_TXCOLLISION                   "TxCollision"
+#define MIB_TXCOLLISION_ID                67
+#define MIB_TXCOLLISION_OFFSET            0x2008c
+#define MIB_TXCOLLISION_E_LENGTH          4
+#define MIB_TXCOLLISION_E_OFFSET          0x100
+#define MIB_TXCOLLISION_NR_E              6
+
+#define MIB_TXABORTCOL                    "TxAbortCol"
+#define MIB_TXABORTCOL_ID                 68
+#define MIB_TXABORTCOL_OFFSET             0x20090
+#define MIB_TXABORTCOL_E_LENGTH           4
+#define MIB_TXABORTCOL_E_OFFSET           0x100
+#define MIB_TXABORTCOL_NR_E               6
+
+#define MIB_TXMULTICOL                    "TxMultiCol"
+#define MIB_TXMULTICOL_ID                 69
+#define MIB_TXMULTICOL_OFFSET             0x20094
+#define MIB_TXMULTICOL_E_LENGTH           4
+#define MIB_TXMULTICOL_E_OFFSET           0x100
+#define MIB_TXMULTICOL_NR_E               6
+
+#define MIB_TXSINGALCOL                   "TxSingalCol"
+#define MIB_TXSINGALCOL_ID                70
+#define MIB_TXSINGALCOL_OFFSET            0x20098
+#define MIB_TXSINGALCOL_E_LENGTH          4
+#define MIB_TXSINGALCOL_E_OFFSET          0x100
+#define MIB_TXSINGALCOL_NR_E              6
+
+#define MIB_TXEXCDEFER                    "TxExcDefer"
+#define MIB_TXEXCDEFER_ID                 71
+#define MIB_TXEXCDEFER_OFFSET             0x2009c
+#define MIB_TXEXCDEFER_E_LENGTH           4
+#define MIB_TXEXCDEFER_E_OFFSET           0x100
+#define MIB_TXEXCDEFER_NR_E               6
+
+#define MIB_TXDEFER                       "TxDefer"
+#define MIB_TXDEFER_ID                    72
+#define MIB_TXDEFER_OFFSET                0x200a0
+#define MIB_TXDEFER_E_LENGTH              4
+#define MIB_TXDEFER_E_OFFSET              0x100
+#define MIB_TXDEFER_NR_E                  6
+
+#define MIB_TXLATECOL                     "TxLateCol"
+#define MIB_TXLATECOL_ID                  73
+#define MIB_TXLATECOL_OFFSET              0x200a4
+#define MIB_TXLATECOL_E_LENGTH            4
+#define MIB_TXLATECOL_E_OFFSET            0x100
+#define MIB_TXLATECOL_NR_E                6
+
+#if 0
+    /* mib info second mem block */
+#define MIB_RXBROAD_2                     "RxBroad_2"
+#define MIB_RXBROAD_2_ID                  34
+#define MIB_RXBROAD_2_OFFSET              (MIB_RXBROAD_OFFSET + 0x400)
+#define MIB_RXBROAD_2_E_LENGTH            4
+#define MIB_RXBROAD_2_E_OFFSET            0xa8
+#define MIB_RXBROAD_2_NR_E                6
+
+#define MIB_RXPAUSE_2                     "RxPause_2"
+#define MIB_RXPAUSE_2_ID                  35
+#define MIB_RXPAUSE_2_OFFSET              (MIB_RXPAUSE_OFFSET + 0x400)
+#define MIB_RXPAUSE_2_E_LENGTH            4
+#define MIB_RXPAUSE_2_E_OFFSET            0xa8
+#define MIB_RXPAUSE_2_NR_E                6
+
+#define MIB_RXMULTI_2                     "RxMulti_2"
+#define MIB_RXMULTI_2_ID                  36
+#define MIB_RXMULTI_2_OFFSET              (MIB_RXMULTI_OFFSET + 0x400)
+#define MIB_RXMULTI_2_E_LENGTH            4
+#define MIB_RXMULTI_2_E_OFFSET            0xa8
+#define MIB_RXMULTI_2_NR_E                6
+
+#define MIB_RXFCSERR_2                    "RxFcsErr_2"
+#define MIB_RXFCSERR_2_ID                 37
+#define MIB_RXFCSERR_2_OFFSET             (MIB_RXFCSERR_OFFSET + 0x400)
+#define MIB_RXFCSERR_2_E_LENGTH           4
+#define MIB_RXFCSERR_2_E_OFFSET           0xa8
+#define MIB_RXFCSERR_2_NR_E               6
+
+#define MIB_RXALLIGNERR_2                 "RxAllignErr_2"
+#define MIB_RXALLIGNERR_2_ID              38
+#define MIB_RXALLIGNERR_2_OFFSET          (MIB_RXALLIGNERR_OFFSET + 0x400)
+#define MIB_RXALLIGNERR_2_E_LENGTH        4
+#define MIB_RXALLIGNERR_2_E_OFFSET        0xa8
+#define MIB_RXALLIGNERR_2_NR_E            6
+
+#define MIB_RXRUNT_2                      "RxRunt_2"
+#define MIB_RXRUNT_2_ID                   39
+#define MIB_RXRUNT_2_OFFSET               (MIB_RXRUNT_OFFSET + 0x400)
+#define MIB_RXRUNT_2_E_LENGTH             4
+#define MIB_RXRUNT_2_E_OFFSET             0xa8
+#define MIB_RXRUNT_2_NR_E                 6
+
+#define MIB_RXFRAGMENT_2                  "RxFragment_2"
+#define MIB_RXFRAGMENT_2_ID               40
+#define MIB_RXFRAGMENT_2_OFFSET           (MIB_RXFRAGMENT_OFFSET + 0x400)
+#define MIB_RXFRAGMENT_2_E_LENGTH         4
+#define MIB_RXFRAGMENT_2_E_OFFSET         0xa8
+#define MIB_RXFRAGMENT_2_NR_E             6
+
+#define MIB_RX64BYTE_2                    "Rx64Byte_2"
+#define MIB_RX64BYTE_2_ID                 41
+#define MIB_RX64BYTE_2_OFFSET             (MIB_RX64BYTE_OFFSET + 0x400)
+#define MIB_RX64BYTE_2_E_LENGTH           4
+#define MIB_RX64BYTE_2_E_OFFSET           0xa8
+#define MIB_RX64BYTE_2_NR_E               6
+
+#define MIB_RX128BYTE_2                   "Rx128Byte_2"
+#define MIB_RX128BYTE_2_ID                42
+#define MIB_RX128BYTE_2_OFFSET            (MIB_RX128BYTE_OFFSET + 0x400)
+#define MIB_RX128BYTE_2_E_LENGTH          4
+#define MIB_RX128BYTE_2_E_OFFSET          0xa8
+#define MIB_RX128BYTE_2_NR_E              6
+
+#define MIB_RX256BYTE_2                   "Rx256Byte_2"
+#define MIB_RX256BYTE_2_ID                43
+#define MIB_RX256BYTE_2_OFFSET            (MIB_RX256BYTE_OFFSET + 0x400)
+#define MIB_RX256BYTE_2_E_LENGTH          4
+#define MIB_RX256BYTE_2_E_OFFSET          0xa8
+#define MIB_RX256BYTE_2_NR_E              6
+
+#define MIB_RX512BYTE_2                   "Rx512Byte_2"
+#define MIB_RX512BYTE_2_ID                44
+#define MIB_RX512BYTE_2_OFFSET            (MIB_RX512BYTE_OFFSET + 0x400)
+#define MIB_RX512BYTE_2_E_LENGTH          4
+#define MIB_RX512BYTE_2_E_OFFSET          0xa8
+#define MIB_RX512BYTE_2_NR_E              6
+
+#define MIB_RX1024BYTE_2                  "Rx1024Byte_2"
+#define MIB_RX1024BYTE_2_ID               45
+#define MIB_RX1024BYTE_2_OFFSET           (MIB_RX1024BYTE_OFFSET + 0x400)
+#define MIB_RX1024BYTE_2_E_LENGTH         4
+#define MIB_RX1024BYTE_2_E_OFFSET         0xa8
+#define MIB_RX1024BYTE_2_NR_E             6
+
+#define MIB_RX1518BYTE_2                  "Rx1518Byte_2"
+#define MIB_RX1518BYTE_2_ID               45
+#define MIB_RX1518BYTE_2_OFFSET           (MIB_RX1518BYTE_OFFSET + 0x400)
+#define MIB_RX1518BYTE_2_E_LENGTH         4
+#define MIB_RX1518BYTE_2_E_OFFSET         0xa8
+#define MIB_RX1518BYTE_2_NR_E             6
+
+#define MIB_RXMAXBYTE_2                   "RxMaxByte_2"
+#define MIB_RXMAXBYTE_2_ID                46
+#define MIB_RXMAXBYTE_2_OFFSET            (MIB_RXMAXBYTE_OFFSET + 0x400)
+#define MIB_RXMAXBYTE_2_E_LENGTH          4
+#define MIB_RXMAXBYTE_2_E_OFFSET          0xa8
+#define MIB_RXMAXBYTE_2_NR_E              6
+
+#define MIB_RXTOOLONG_2                   "RxTooLong_2"
+#define MIB_RXTOOLONG_2_ID                47
+#define MIB_RXTOOLONG_2_OFFSET            (MIB_RXTOOLONG_OFFSET + 0x400)
+#define MIB_RXTOOLONG_2_E_LENGTH          4
+#define MIB_RXTOOLONG_2_E_OFFSET          0xa8
+#define MIB_RXTOOLONG_2_NR_E             6
+
+#define MIB_RXGOODBYTE_LO_2               "RxGoodByteLo_2"
+#define MIB_RXGOODBYTE_LO_2_ID            48
+#define MIB_RXGOODBYTE_LO_2_OFFSET        (MIB_RXGOODBYTE_LO_OFFSET + 0x400)
+#define MIB_RXGOODBYTE_LO_2_E_LENGTH      4
+#define MIB_RXGOODBYTE_LO_2_E_OFFSET      0xa8
+#define MIB_RXGOODBYTE_LO_2_NR_E          6
+
+#define MIB_RXGOODBYTE_HI_2               "RxGoodByteHi_2"
+#define MIB_RXGOODBYTE_HI_2_ID            49
+#define MIB_RXGOODBYTE_HI_2_OFFSET        (MIB_RXGOODBYTE_HI_OFFSET + 0x400)
+#define MIB_RXGOODBYTE_HI_2_E_LENGTH      4
+#define MIB_RXGOODBYTE_HI_2_E_OFFSET      0xa8
+#define MIB_RXGOODBYTE_HI_2_NR_E          6
+
+#define MIB_RXBADBYTE_LO_2                "RxBadByteLo_2"
+#define MIB_RXBADBYTE_LO_2_ID             50
+#define MIB_RXBADBYTE_LO_2_OFFSET         (MIB_RXBADBYTE_LO_OFFSET + 0x400)
+#define MIB_RXBADBYTE_LO_2_E_LENGTH       4
+#define MIB_RXBADBYTE_LO_2_E_OFFSET       0xa8
+#define MIB_RXBADBYTE_LO_2_NR_E           6
+
+#define MIB_RXBADBYTE_HI_2                "RxBadByteHi_2"
+#define MIB_RXBADBYTE_HI_2_ID             51
+#define MIB_RXBADBYTE_HI_2_OFFSET         (MIB_RXBADBYTE_HI_OFFSET + 0x400)
+#define MIB_RXBADBYTE_HI_2_E_LENGTH       4
+#define MIB_RXBADBYTE_HI_2_E_OFFSET       0xa8
+#define MIB_RXBADBYTE_HI_2_NR_E           6
+
+#define MIB_RXOVERFLOW_2                  "RxOverFlow_2"
+#define MIB_RXOVERFLOW_2_ID               52
+#define MIB_RXOVERFLOW_2_OFFSET           (MIB_RXOVERFLOW_OFFSET + 0x400)
+#define MIB_RXOVERFLOW_2_E_LENGTH         4
+#define MIB_RXOVERFLOW_2_E_OFFSET         0xa8
+#define MIB_RXOVERFLOW_2_NR_E             6
+
+#define MIB_FILTERED_2                    "Filtered_2"
+#define MIB_FILTERED_2_ID                 53
+#define MIB_FILTERED_2_OFFSET             (MIB_FILTERED_OFFSET + 0x400)
+#define MIB_FILTERED_2_E_LENGTH           4
+#define MIB_FILTERED_2_E_OFFSET           0xa8
+#define MIB_FILTERED_2_NR_E               6
+
+#define MIB_TXBROAD_2                     "TxBroad_2"
+#define MIB_TXBROAD_2_ID                  54
+#define MIB_TXBROAD_2_OFFSET              (MIB_TXBROAD_OFFSET + 0x400)
+#define MIB_TXBROAD_2_E_LENGTH            4
+#define MIB_TXBROAD_2_E_OFFSET            0xa8
+#define MIB_TXBROAD_2_NR_E                6
+
+#define MIB_TXPAUSE_2                     "TxPause_2"
+#define MIB_TXPAUSE_2_ID                  55
+#define MIB_TXPAUSE_2_OFFSET              (MIB_TXPAUSE_OFFSET + 0x400)
+#define MIB_TXPAUSE_2_E_LENGTH            4
+#define MIB_TXPAUSE_2_E_OFFSET            0xa8
+#define MIB_TXPAUSE_2_NR_E                6
+
+#define MIB_TXMULTI_2                     "TxMulti_2"
+#define MIB_TXMULTI_2_ID                  56
+#define MIB_TXMULTI_2_OFFSET              (MIB_TXMULTI_OFFSET + 0x400)
+#define MIB_TXMULTI_2_E_LENGTH            4
+#define MIB_TXMULTI_2_E_OFFSET            0xa8
+#define MIB_TXMULTI_2_NR_E                6
+
+#define MIB_TXUNDERRUN_2                  "TxUnderRun_2"
+#define MIB_TXUNDERRUN_2_ID               57
+#define MIB_TXUNDERRUN_2_OFFSET           (MIB_TXUNDERRUN_OFFSET + 0x400)
+#define MIB_TXUNDERRUN_2_E_LENGTH         4
+#define MIB_TXUNDERRUN_2_E_OFFSET         0xa8
+#define MIB_TXUNDERRUN_2_NR_E             6
+
+#define MIB_TX64BYTE_2                    "Tx64Byte_2"
+#define MIB_TX64BYTE_2_ID                 58
+#define MIB_TX64BYTE_2_OFFSET             (MIB_TX64BYTE_OFFSET + 0x400)
+#define MIB_TX64BYTE_2_E_LENGTH           4
+#define MIB_TX64BYTE_2_E_OFFSET           0xa8
+#define MIB_TX64BYTE_2_NR_E               6
+
+#define MIB_TX128BYTE_2                   "Tx128Byte_2"
+#define MIB_TX128BYTE_2_ID                59
+#define MIB_TX128BYTE_2_OFFSET            (MIB_TX128BYTE_OFFSET + 0x400)
+#define MIB_TX128BYTE_2_E_LENGTH          4
+#define MIB_TX128BYTE_2_E_OFFSET          0xa8
+#define MIB_TX128BYTE_2_NR_E              6
+
+#define MIB_TX256BYTE_2                   "Tx256Byte_2"
+#define MIB_TX256BYTE_2_ID                60
+#define MIB_TX256BYTE_2_OFFSET            (MIB_TX256BYTE_OFFSET + 0x400)
+#define MIB_TX256BYTE_2_E_LENGTH          4
+#define MIB_TX256BYTE_2_E_OFFSET          0xa8
+#define MIB_TX256BYTE_2_NR_E              6
+
+#define MIB_TX512BYTE_2                   "Tx512Byte_2"
+#define MIB_TX512BYTE_2_ID                61
+#define MIB_TX512BYTE_2_OFFSET            (MIB_TX512BYTE_OFFSET + 0x400)
+#define MIB_TX512BYTE_2_E_LENGTH          4
+#define MIB_TX512BYTE_2_E_OFFSET          0xa8
+#define MIB_TX512BYTE_2_NR_E              6
+
+#define MIB_TX1024BYTE_2                  "Tx1024Byte_2"
+#define MIB_TX1024BYTE_2_ID               62
+#define MIB_TX1024BYTE_2_OFFSET           (MIB_TX1024BYTE_OFFSET + 0x400)
+#define MIB_TX1024BYTE_2_E_LENGTH         4
+#define MIB_TX1024BYTE_2_E_OFFSET         0xa8
+#define MIB_TX1024BYTE_2_NR_E             6
+
+#define MIB_TX1518BYTE_2                  "Tx1518Byte_2"
+#define MIB_TX1518BYTE_2_ID               62
+#define MIB_TX1518BYTE_2_OFFSET           (MIB_TX1518BYTE_OFFSET + 0x400)
+#define MIB_TX1518BYTE_2_E_LENGTH         4
+#define MIB_TX1518BYTE_2_E_OFFSET         0xa8
+#define MIB_TX1518BYTE_2_NR_E             6
+
+#define MIB_TXMAXBYTE_2                   "TxMaxByte_2"
+#define MIB_TXMAXBYTE_2_ID                63
+#define MIB_TXMAXBYTE_2_OFFSET            (MIB_TXMAXBYTE_OFFSET + 0x400)
+#define MIB_TXMAXBYTE_2_E_LENGTH          4
+#define MIB_TXMAXBYTE_2_E_OFFSET          0xa8
+#define MIB_TXMAXBYTE_2_NR_E              6
+
+#define MIB_TXOVERSIZE_2                  "TxOverSize_2"
+#define MIB_TXOVERSIZE_2_ID               64
+#define MIB_TXOVERSIZE_2_OFFSET           (MIB_TXOVERSIZE_OFFSET + 0x400)
+#define MIB_TXOVERSIZE_2_E_LENGTH         4
+#define MIB_TXOVERSIZE_2_E_OFFSET         0xa8
+#define MIB_TXOVERSIZE_2_NR_E             6
+
+#define MIB_TXBYTE_LO_2                   "TxByteLo_2"
+#define MIB_TXBYTE_LO_2_ID                65
+#define MIB_TXBYTE_LO_2_OFFSET            (MIB_TXBYTE_LO_OFFSET + 0x400)
+#define MIB_TXBYTE_LO_2_E_LENGTH          4
+#define MIB_TXBYTE_LO_2_E_OFFSET          0xa8
+#define MIB_TXBYTE_LO_2_NR_E              6
+
+#define MIB_TXBYTE_HI_2                   "TxByteHi_2"
+#define MIB_TXBYTE_HI_2_ID                66
+#define MIB_TXBYTE_HI_2_OFFSET            (MIB_TXBYTE_HI_OFFSET + 0x400)
+#define MIB_TXBYTE_HI_2_E_LENGTH          4
+#define MIB_TXBYTE_HI_2_E_OFFSET          0xa8
+#define MIB_TXBYTE_HI_2_NR_E              6
+
+#define MIB_TXCOLLISION_2                 "TxCollision_2"
+#define MIB_TXCOLLISION_2_ID              67
+#define MIB_TXCOLLISION_2_OFFSET          (MIB_TXCOLLISION_OFFSET + 0x400)
+#define MIB_TXCOLLISION_2_E_LENGTH        4
+#define MIB_TXCOLLISION_2_E_OFFSET        0xa8
+#define MIB_TXCOLLISION_2_NR_E            6
+
+#define MIB_TXABORTCOL_2                  "TxAbortCol_2"
+#define MIB_TXABORTCOL_2_ID               68
+#define MIB_TXABORTCOL_2_OFFSET           (MIB_TXABORTCOL_OFFSET + 0x400)
+#define MIB_TXABORTCOL_2_E_LENGTH         4
+#define MIB_TXABORTCOL_2_E_OFFSET         0xa8
+#define MIB_TXABORTCOL_2_NR_E             6
+
+#define MIB_TXMULTICOL_2                  "TxMultiCol_2"
+#define MIB_TXMULTICOL_2_ID               69
+#define MIB_TXMULTICOL_2_OFFSET           (MIB_TXMULTICOL_OFFSET + 0x400)
+#define MIB_TXMULTICOL_2_E_LENGTH         4
+#define MIB_TXMULTICOL_2_E_OFFSET         0xa8
+#define MIB_TXMULTICOL_2_NR_E             6
+
+#define MIB_TXSINGALCOL_2                 "TxSingalCol_2"
+#define MIB_TXSINGALCOL_2_ID              70
+#define MIB_TXSINGALCOL_2_OFFSET          (MIB_TXSINGALCOL_OFFSET + 0x400)
+#define MIB_TXSINGALCOL_2_E_LENGTH        4
+#define MIB_TXSINGALCOL_2_E_OFFSET        0xa8
+#define MIB_TXSINGALCOL_2_NR_E            6
+
+#define MIB_TXEXCDEFER_2                  "TxExcDefer_2"
+#define MIB_TXEXCDEFER_2_ID               71
+#define MIB_TXEXCDEFER_2_OFFSET           (MIB_TXEXCDEFER_OFFSET + 0x400)
+#define MIB_TXEXCDEFER_2_E_LENGTH         4
+#define MIB_TXEXCDEFER_2_E_OFFSET         0xa8
+#define MIB_TXEXCDEFER_2_NR_E             6
+
+#define MIB_TXDEFER_2                     "TxDefer_2"
+#define MIB_TXDEFER_2_ID                  72
+#define MIB_TXDEFER_2_OFFSET              (MIB_TXDEFER_OFFSET + 0x400)
+#define MIB_TXDEFER_2_E_LENGTH            4
+#define MIB_TXDEFER_2_E_OFFSET            0xa8
+#define MIB_TXDEFER_2_NR_E                6
+
+#define MIB_TXLATECOL_2                   "TxLateCol_2"
+#define MIB_TXLATECOL_2_ID                73
+#define MIB_TXLATECOL_2_OFFSET            (MIB_TXLATECOL_OFFSET + 0x400)
+#define MIB_TXLATECOL_2_E_LENGTH          4
+#define MIB_TXLATECOL_2_E_OFFSET          0xa8
+#define MIB_TXLATECOL_2_NR_E              6
+#endif
+
+
+
+
+#define ACL_RSLT0                         "aclact0"
+#define ACL_RSLT0_ID                      13
+#define ACL_RSLT0_OFFSET                  0x58000
+#define ACL_RSLT0_E_LENGTH                4
+#define ACL_RSLT0_E_OFFSET                0x20
+#define ACL_RSLT0_NR_E                    32
+
+#define MATCH_CNT                         "aclact_cnt"
+#define ACL_RSLT0_MATCH_CNT_BOFFSET       0
+#define ACL_RSLT0_MATCH_CNT_BLEN          32
+#define ACL_RSLT0_MATCH_CNT_FLAG          HSL_RW
+
+
+
+
+#define ACL_RSLT1                         "aclact1"
+#define ACL_RSLT1_ID                      13
+#define ACL_RSLT1_OFFSET                  0x58004
+#define ACL_RSLT1_E_LENGTH                4
+#define ACL_RSLT1_E_OFFSET                0x20
+#define ACL_RSLT1_NR_E                    32
+
+#define MIRR_EN                          "aclact1_mirr"
+#define ACL_RSLT1_MIRR_EN_BOFFSET         31
+#define ACL_RSLT1_MIRR_EN_BLEN            1
+#define ACL_RSLT1_MIRR_EN_FLAG            HSL_RW
+
+#define STAG_CHG_EN                      "aclact1_rdcpu"
+#define ACL_RSLT1_STAG_CHG_EN_BOFFSET     30
+#define ACL_RSLT1_STAG_CHG_EN_BLEN        1
+#define ACL_RSLT1_STAG_CHG_EN_FLAG        HSL_RW
+
+#define VID_MEM_EN                       "aclact1_rdcpu"
+#define ACL_RSLT1_VID_MEM_EN_BOFFSET      29
+#define ACL_RSLT1_VID_MEM_EN_BLEN         1
+#define ACL_RSLT1_VID_MEM_EN_FLAG         HSL_RW
+
+#define DES_PORT_EN                      "aclact1_rdcpu"
+#define ACL_RSLT1_DES_PORT_EN_BOFFSET     28
+#define ACL_RSLT1_DES_PORT_EN_BLEN        1
+#define ACL_RSLT1_DES_PORT_EN_FLAG        HSL_RW
+
+#define PORT_MEM                         "aclact1_rdcpu"
+#define ACL_RSLT1_PORT_MEM_BOFFSET        20
+#define ACL_RSLT1_PORT_MEM_BLEN           7
+#define ACL_RSLT1_PORT_MEM_FLAG           HSL_RW
+
+#define REMARK_PRI_QU                    "aclact1_rdcpu"
+#define ACL_RSLT1_REMARK_PRI_QU_BOFFSET   19
+#define ACL_RSLT1_REMARK_PRI_QU_BLEN      1
+#define ACL_RSLT1_REMARK_PRI_QU_FLAG      HSL_RW
+
+#define DOT1P                            "aclact1_rdcpu"
+#define ACL_RSLT1_DOT1P_BOFFSET           16
+#define ACL_RSLT1_DOT1P_BLEN              3
+#define ACL_RSLT1_DOT1P_FLAG              HSL_RW
+
+#define PRI_QU                           "aclact1_rdcpu"
+#define ACL_RSLT1_PRI_QU_BOFFSET          14
+#define ACL_RSLT1_PRI_QU_BLEN             2
+#define ACL_RSLT1_PRI_QU_FLAG             HSL_RW
+
+#define REMARK_DOT1P                     "aclact1_rdcpu"
+#define ACL_RSLT1_REMARK_DOT1P_BOFFSET    13
+#define ACL_RSLT1_REMARK_DOT1P_BLEN       1
+#define ACL_RSLT1_REMARK_DOT1P_FLAG       HSL_RW
+
+#define CHG_VID_EN                       "aclact1_rdcpu"
+#define ACL_RSLT1_CHG_VID_EN_BOFFSET      12
+#define ACL_RSLT1_CHG_VID_EN_BLEN         1
+#define ACL_RSLT1_CHG_VID_EN_FLAG         HSL_RW
+
+#define VID                              "aclact1_rdcpu"
+#define ACL_RSLT1_VID_BOFFSET             0
+#define ACL_RSLT1_VID_BLEN                12
+#define ACL_RSLT1_VID_FLAG                HSL_RW
+
+
+
+
+#define ACL_RSLT2                         "aclact2"
+#define ACL_RSLT2_ID                      13
+#define ACL_RSLT2_OFFSET                  0x58008
+#define ACL_RSLT2_E_LENGTH                4
+#define ACL_RSLT2_E_OFFSET                0x20
+#define ACL_RSLT2_NR_E                    32
+
+#define RDTCPU                            "aclact2_rdtpu"
+#define ACL_RSLT2_RDTCPU_BOFFSET          1
+#define ACL_RSLT2_RDTCPU_BLEN             1
+#define ACL_RSLT2_RDTCPU_FLAG             HSL_RW
+
+#define CPYCPU                            "aclact2_cpcpu"
+#define ACL_RSLT2_CPYCPU_BOFFSET          0
+#define ACL_RSLT2_CPYCPU_BLEN             1
+#define ACL_RSLT2_CPYCPU_FLAG             HSL_RW
+
+
+
+
+
+#define RUL_SLCT0                         "rulslct0"
+#define RUL_SLCT0_ID                      13
+#define RUL_SLCT0_OFFSET                  0x58800
+#define RUL_SLCT0_E_LENGTH                4
+#define RUL_SLCT0_E_OFFSET                0x20
+#define RUL_SLCT0_NR_E                    32
+
+#define ADDR3_EN                         "rulslct_addr3en"
+#define RUL_SLCT0_ADDR3_EN_BOFFSET        3
+#define RUL_SLCT0_ADDR3_EN_BLEN           1
+#define RUL_SLCT0_ADDR3_EN_FLAG           HSL_RW
+
+#define ADDR2_EN                         "rulslct_addr2en"
+#define RUL_SLCT0_ADDR2_EN_BOFFSET        2
+#define RUL_SLCT0_ADDR2_EN_BLEN           1
+#define RUL_SLCT0_ADDR2_EN_FLAG           HSL_RW
+
+#define ADDR1_EN                         "rulslct_addr1en"
+#define RUL_SLCT0_ADDR1_EN_BOFFSET        1
+#define RUL_SLCT0_ADDR1_EN_BLEN           1
+#define RUL_SLCT0_ADDR1_EN_FLAG           HSL_RW
+
+#define ADDR0_EN                         "rulslct_addr0en"
+#define RUL_SLCT0_ADDR0_EN_BOFFSET        0
+#define RUL_SLCT0_ADDR0_EN_BLEN           1
+#define RUL_SLCT0_ADDR0_EN_FLAG           HSL_RW
+
+
+
+
+#define RUL_SLCT1                         "rulslct1"
+#define RUL_SLCT1_ID                      13
+#define RUL_SLCT1_OFFSET                  0x58804
+#define RUL_SLCT1_E_LENGTH                4
+#define RUL_SLCT1_E_OFFSET                0x20
+#define RUL_SLCT1_NR_E                    32
+
+#define ADDR0                            "rulslct1_addr0"
+#define RUL_SLCT1_ADDR0_BOFFSET           0
+#define RUL_SLCT1_ADDR0_BLEN              5
+#define RUL_SLCT1_ADDR0_FLAG              HSL_RW
+
+
+
+
+#define RUL_SLCT2                         "rulslct2"
+#define RUL_SLCT2_ID                      13
+#define RUL_SLCT2_OFFSET                  0x58808
+#define RUL_SLCT2_E_LENGTH                4
+#define RUL_SLCT2_E_OFFSET                0x20
+#define RUL_SLCT2_NR_E                    32
+
+#define ADDR1                            "rulslct2_addr1"
+#define RUL_SLCT2_ADDR1_BOFFSET           0
+#define RUL_SLCT2_ADDR1_BLEN              5
+#define RUL_SLCT2_ADDR1_FLAG              HSL_RW
+
+
+
+
+#define RUL_SLCT3                         "rulslct3"
+#define RUL_SLCT3_ID                      13
+#define RUL_SLCT3_OFFSET                  0x5880c
+#define RUL_SLCT3_E_LENGTH                4
+#define RUL_SLCT3_E_OFFSET                0x20
+#define RUL_SLCT3_NR_E                    32
+
+#define ADDR2                            "rulslct3_addr2"
+#define RUL_SLCT3_ADDR2_BOFFSET           0
+#define RUL_SLCT3_ADDR2_BLEN              5
+#define RUL_SLCT3_ADDR2_FLAG              HSL_RW
+
+
+
+
+#define RUL_SLCT4                         "rulslct4"
+#define RUL_SLCT4_ID                      13
+#define RUL_SLCT4_OFFSET                  0x58810
+#define RUL_SLCT4_E_LENGTH                4
+#define RUL_SLCT4_E_OFFSET                0x20
+#define RUL_SLCT4_NR_E                    32
+
+#define ADDR3                            "rulslct4_addr3"
+#define RUL_SLCT4_ADDR3_BOFFSET          0
+#define RUL_SLCT4_ADDR3_BLEN             5
+#define RUL_SLCT4_ADDR3_FLAG              HSL_RW
+
+
+
+
+#define RUL_SLCT5                         "rulslct5"
+#define RUL_SLCT5_ID                      13
+#define RUL_SLCT5_OFFSET                  0x58814
+#define RUL_SLCT5_E_LENGTH                4
+#define RUL_SLCT5_E_OFFSET                0x20
+#define RUL_SLCT5_NR_E                    32
+
+#define SRC_PT                            "rulslct5_srcpt"
+#define RUL_SLCT5_SRC_PT_BOFFSET          0
+#define RUL_SLCT5_SRC_PT_BLEN             7
+#define RUL_SLCT5_SRC_PT_FLAG             HSL_RW
+
+
+
+
+#define RUL_SLCT6                         "rulslct6"
+#define RUL_SLCT6_ID                      13
+#define RUL_SLCT6_OFFSET                  0x58818
+#define RUL_SLCT6_E_LENGTH                4
+#define RUL_SLCT6_E_OFFSET                0x20
+#define RUL_SLCT6_NR_E                    32
+
+#define RULE_LEN                           "rulslct6_rulelen"
+#define RUL_SLCT6_RULE_LEN_BOFFSET         0
+#define RUL_SLCT6_RULE_LEN_BLEN            8
+#define RUL_SLCT6_RULE_LEN_FLAG            HSL_RW
+
+
+
+
+#define RUL_SLCT7                         "rulslct7"
+#define RUL_SLCT7_ID                      13
+#define RUL_SLCT7_OFFSET                  0x5881c
+#define RUL_SLCT7_E_LENGTH                4
+#define RUL_SLCT7_E_OFFSET                0x20
+#define RUL_SLCT7_NR_E                    32
+
+#define RULE_TYP                           "rulslct7_ruletyp"
+#define RUL_SLCT7_RULE_TYP_BOFFSET         0
+#define RUL_SLCT7_RULE_TYP_BLEN            3
+#define RUL_SLCT7_RULE_TYP_FLAG            HSL_RW
+
+
+
+
+#define MAC_RUL_V0                         "macrv0"
+#define MAC_RUL_V0_ID                      13
+#define MAC_RUL_V0_OFFSET                  0x58400
+#define MAC_RUL_V0_E_LENGTH                4
+#define MAC_RUL_V0_E_OFFSET                0x20
+#define MAC_RUL_V0_NR_E                    32
+
+#define DAV_BYTE2                             "macrv0_dav2"
+#define MAC_RUL_V0_DAV_BYTE2_BOFFSET             24
+#define MAC_RUL_V0_DAV_BYTE2_BLEN                8
+#define MAC_RUL_V0_DAV_BYTE2_FLAG                HSL_RW
+
+#define DAV_BYTE3                             "macrv0_dav3"
+#define MAC_RUL_V0_DAV_BYTE3_BOFFSET             16
+#define MAC_RUL_V0_DAV_BYTE3_BLEN                8
+#define MAC_RUL_V0_DAV_BYTE3_FLAG                HSL_RW
+
+#define DAV_BYTE4                             "macrv0_dav4"
+#define MAC_RUL_V0_DAV_BYTE4_BOFFSET             8
+#define MAC_RUL_V0_DAV_BYTE4_BLEN                8
+#define MAC_RUL_V0_DAV_BYTE4_FLAG                HSL_RW
+
+#define DAV_BYTE5                             "macrv0_dav5"
+#define MAC_RUL_V0_DAV_BYTE5_BOFFSET             0
+#define MAC_RUL_V0_DAV_BYTE5_BLEN                8
+#define MAC_RUL_V0_DAV_BYTE5_FLAG                HSL_RW
+
+
+
+
+#define MAC_RUL_V1                         "macrv1"
+#define MAC_RUL_V1_ID                      13
+#define MAC_RUL_V1_OFFSET                  0x58404
+#define MAC_RUL_V1_E_LENGTH                4
+#define MAC_RUL_V1_E_OFFSET                0x20
+#define MAC_RUL_V1_NR_E                    32
+
+#define SAV_BYTE4                             "macrv1_sav4"
+#define MAC_RUL_V1_SAV_BYTE4_BOFFSET             24
+#define MAC_RUL_V1_SAV_BYTE4_BLEN                8
+#define MAC_RUL_V1_SAV_BYTE4_FLAG                HSL_RW
+
+#define SAV_BYTE5                             "macrv1_sav5"
+#define MAC_RUL_V1_SAV_BYTE5_BOFFSET             16
+#define MAC_RUL_V1_SAV_BYTE5_BLEN                8
+#define MAC_RUL_V1_SAV_BYTE5_FLAG                HSL_RW
+
+#define DAV_BYTE0                             "macrv1_dav0"
+#define MAC_RUL_V1_DAV_BYTE0_BOFFSET             8
+#define MAC_RUL_V1_DAV_BYTE0_BLEN                8
+#define MAC_RUL_V1_DAV_BYTE0_FLAG                HSL_RW
+
+#define DAV_BYTE1                             "macrv1_dav1"
+#define MAC_RUL_V1_DAV_BYTE1_BOFFSET             0
+#define MAC_RUL_V1_DAV_BYTE1_BLEN                8
+#define MAC_RUL_V1_DAV_BYTE1_FLAG                HSL_RW
+
+
+
+
+#define MAC_RUL_V2                         "macrv2"
+#define MAC_RUL_V2_ID                      13
+#define MAC_RUL_V2_OFFSET                  0x58408
+#define MAC_RUL_V2_E_LENGTH                4
+#define MAC_RUL_V2_E_OFFSET                0x20
+#define MAC_RUL_V2_NR_E                    32
+
+#define SAV_BYTE0                             "macrv2_sav0"
+#define MAC_RUL_V2_SAV_BYTE0_BOFFSET             24
+#define MAC_RUL_V2_SAV_BYTE0_BLEN                8
+#define MAC_RUL_V2_SAV_BYTE0_FLAG                HSL_RW
+
+#define SAV_BYTE1                             "macrv2_sav1"
+#define MAC_RUL_V2_SAV_BYTE1_BOFFSET             16
+#define MAC_RUL_V2_SAV_BYTE1_BLEN                8
+#define MAC_RUL_V2_SAV_BYTE1_FLAG                HSL_RW
+
+#define SAV_BYTE2                             "macrv2_sav2"
+#define MAC_RUL_V2_SAV_BYTE2_BOFFSET             8
+#define MAC_RUL_V2_SAV_BYTE2_BLEN                8
+#define MAC_RUL_V2_SAV_BYTE2_FLAG                HSL_RW
+
+#define SAV_BYTE3                             "macrv2_sav3"
+#define MAC_RUL_V2_SAV_BYTE3_BOFFSET             0
+#define MAC_RUL_V2_SAV_BYTE3_BLEN                8
+#define MAC_RUL_V2_SAV_BYTE3_FLAG                HSL_RW
+
+
+
+
+#define MAC_RUL_V3                         "macrv3"
+#define MAC_RUL_V3_ID                      13
+#define MAC_RUL_V3_OFFSET                  0x5840c
+#define MAC_RUL_V3_E_LENGTH                4
+#define MAC_RUL_V3_E_OFFSET                0x20
+#define MAC_RUL_V3_NR_E                    32
+
+#define ETHTYPV                             "macrv3_ethtypv"
+#define MAC_RUL_V3_ETHTYPV_BOFFSET             16
+#define MAC_RUL_V3_ETHTYPV_BLEN                16
+#define MAC_RUL_V3_ETHTYPV_FLAG                HSL_RW
+
+#define VLANPRIV                             "macrv3_vlanpriv"
+#define MAC_RUL_V3_VLANPRIV_BOFFSET             13
+#define MAC_RUL_V3_VLANPRIV_BLEN                3
+#define MAC_RUL_V3_VLANPRIV_FLAG                HSL_RW
+
+#define VLANCFIV                              "macrv3_vlancfiv"
+#define MAC_RUL_V3_VLANCFIV_BOFFSET             12
+#define MAC_RUL_V3_VLANCFIV_BLEN                1
+#define MAC_RUL_V3_VLANCFIV_FLAG                HSL_RW
+
+#define VLANIDV                             "macrv3_vlanidv"
+#define MAC_RUL_V3_VLANIDV_BOFFSET             0
+#define MAC_RUL_V3_VLANIDV_BLEN                12
+#define MAC_RUL_V3_VLANIDV_FLAG                HSL_RW
+
+
+
+
+#define MAC_RUL_V4                         "macrv4"
+#define MAC_RUL_V4_ID                      13
+#define MAC_RUL_V4_OFFSET                  0x58410
+#define MAC_RUL_V4_E_LENGTH                4
+#define MAC_RUL_V4_E_OFFSET                0x20
+#define MAC_RUL_V4_NR_E                    32
+
+#define TAGGEDM                           "macrv4_vlanid"
+#define MAC_RUL_V4_TAGGEDM_BOFFSET             7
+#define MAC_RUL_V4_TAGGEDM_BLEN                1
+#define MAC_RUL_V4_TAGGEDM_FLAG                HSL_RW
+
+#define TAGGEDV                           "macrv4_vlanid"
+#define MAC_RUL_V4_TAGGEDV_BOFFSET             6
+#define MAC_RUL_V4_TAGGEDV_BLEN                1
+#define MAC_RUL_V4_TAGGEDV_FLAG                HSL_RW
+
+#define VIDMSK                           "macrv4_vidmsk"
+#define MAC_RUL_V4_VIDMSK_BOFFSET         0
+#define MAC_RUL_V4_VIDMSK_BLEN            1
+#define MAC_RUL_V4_VIDMSK_FLAG            HSL_RW
+
+
+
+
+
+#define MAC_RUL_M0                         "macrv0"
+#define MAC_RUL_M0_ID                      13
+#define MAC_RUL_M0_OFFSET                  0x58c00
+#define MAC_RUL_M0_E_LENGTH                4
+#define MAC_RUL_M0_E_OFFSET                0x20
+#define MAC_RUL_M0_NR_E                    32
+
+#define DAM_BYTE2                             "macrv0_dam2"
+#define MAC_RUL_M0_DAM_BYTE2_BOFFSET             24
+#define MAC_RUL_M0_DAM_BYTE2_BLEN                8
+#define MAC_RUL_M0_DAM_BYTE2_FLAG                HSL_RW
+
+#define DAM_BYTE3                             "macrv0_dam3"
+#define MAC_RUL_M0_DAM_BYTE3_BOFFSET             16
+#define MAC_RUL_M0_DAM_BYTE3_BLEN                8
+#define MAC_RUL_M0_DAM_BYTE3_FLAG                HSL_RW
+
+#define DAM_BYTE4                             "macrv0_dam4"
+#define MAC_RUL_M0_DAM_BYTE4_BOFFSET             8
+#define MAC_RUL_M0_DAM_BYTE4_BLEN                8
+#define MAC_RUL_M0_DAM_BYTE4_FLAG                HSL_RW
+
+#define DAM_BYTE5                             "macrv0_dam5"
+#define MAC_RUL_M0_DAM_BYTE5_BOFFSET             0
+#define MAC_RUL_M0_DAM_BYTE5_BLEN                8
+#define MAC_RUL_M0_DAM_BYTE5_FLAG                HSL_RW
+
+
+
+
+#define MAC_RUL_M1                         "macrm1"
+#define MAC_RUL_M1_ID                      13
+#define MAC_RUL_M1_OFFSET                  0x58c04
+#define MAC_RUL_M1_E_LENGTH                4
+#define MAC_RUL_M1_E_OFFSET                0x20
+#define MAC_RUL_M1_NR_E                    32
+
+#define SAM_BYTE4                             "macrm1_sam4"
+#define MAC_RUL_M1_SAM_BYTE4_BOFFSET             24
+#define MAC_RUL_M1_SAM_BYTE4_BLEN                8
+#define MAC_RUL_M1_SAM_BYTE4_FLAG                HSL_RW
+
+#define SAM_BYTE5                             "macrm1_sam5"
+#define MAC_RUL_M1_SAM_BYTE5_BOFFSET             16
+#define MAC_RUL_M1_SAM_BYTE5_BLEN                8
+#define MAC_RUL_M1_SAM_BYTE5_FLAG                HSL_RW
+
+#define DAM_BYTE0                             "macrm1_dam0"
+#define MAC_RUL_M1_DAM_BYTE0_BOFFSET             8
+#define MAC_RUL_M1_DAM_BYTE0_BLEN                8
+#define MAC_RUL_M1_DAM_BYTE0_FLAG                HSL_RW
+
+#define DAM_BYTE1                             "macrm1_dam1"
+#define MAC_RUL_M1_DAM_BYTE1_BOFFSET             0
+#define MAC_RUL_M1_DAM_BYTE1_BLEN                8
+#define MAC_RUL_M1_DAM_BYTE1_FLAG                HSL_RW
+
+
+
+
+#define MAC_RUL_M2                         "macrm2"
+#define MAC_RUL_M2_ID                      13
+#define MAC_RUL_M2_OFFSET                  0x58c08
+#define MAC_RUL_M2_E_LENGTH                4
+#define MAC_RUL_M2_E_OFFSET                0x20
+#define MAC_RUL_M2_NR_E                    32
+
+#define SAM_BYTE0                             "macrm2_sam0"
+#define MAC_RUL_M2_SAM_BYTE0_BOFFSET             24
+#define MAC_RUL_M2_SAM_BYTE0_BLEN                8
+#define MAC_RUL_M2_SAM_BYTE0_FLAG                HSL_RW
+
+#define SAM_BYTE1                             "macrm2_samv1"
+#define MAC_RUL_M2_SAM_BYTE1_BOFFSET             16
+#define MAC_RUL_M2_SAM_BYTE1_BLEN                8
+#define MAC_RUL_M2_SAM_BYTE1_FLAG                HSL_RW
+
+#define SAM_BYTE2                             "macrm2_sam2"
+#define MAC_RUL_M2_SAM_BYTE2_BOFFSET             8
+#define MAC_RUL_M2_SAM_BYTE2_BLEN                8
+#define MAC_RUL_M2_SAM_BYTE2_FLAG                HSL_RW
+
+#define SAM_BYTE3                             "macrm2_sam3"
+#define MAC_RUL_M2_SAM_BYTE3_BOFFSET             0
+#define MAC_RUL_M2_SAM_BYTE3_BLEN                8
+#define MAC_RUL_M2_SAM_BYTE3_FLAG                HSL_RW
+
+
+
+
+#define MAC_RUL_M3                         "macrv3"
+#define MAC_RUL_M3_ID                      13
+#define MAC_RUL_M3_OFFSET                  0x58c0c
+#define MAC_RUL_M3_E_LENGTH                4
+#define MAC_RUL_M3_E_OFFSET                0x20
+#define MAC_RUL_M3_NR_E                    32
+
+#define ETHTYPM                             "macrm3_ethtypm"
+#define MAC_RUL_M3_ETHTYPM_BOFFSET             16
+#define MAC_RUL_M3_ETHTYPM_BLEN                16
+#define MAC_RUL_M3_ETHTYPM_FLAG                HSL_RW
+
+#define VLANPRIM                             "macrm3_vlanprim"
+#define MAC_RUL_M3_VLANPRIM_BOFFSET             13
+#define MAC_RUL_M3_VLANPRIM_BLEN                3
+#define MAC_RUL_M3_VLANPRIM_FLAG                HSL_RW
+
+#define VLANCFIM                             "macrm3_vlancfim"
+#define MAC_RUL_M3_VLANCFIM_BOFFSET             12
+#define MAC_RUL_M3_VLANCFIM_BLEN                1
+#define MAC_RUL_M3_VLANCFIM_FLAG                HSL_RW
+
+#define VLANIDM                             "macrm3_vlanidm"
+#define MAC_RUL_M3_VLANIDM_BOFFSET             0
+#define MAC_RUL_M3_VLANIDM_BLEN                12
+#define MAC_RUL_M3_VLANIDM_FLAG                HSL_RW
+
+
+
+
+#define IP4_RUL_V0                         "ip4v0"
+#define IP4_RUL_V0_ID                      13
+#define IP4_RUL_V0_OFFSET                  0x58400
+#define IP4_RUL_V0_E_LENGTH                4
+#define IP4_RUL_V0_E_OFFSET                0x20
+#define IP4_RUL_V0_NR_E                    32
+
+#define DIPV                                "ip4v0_dipv"
+#define IP4_RUL_V0_DIPV_BOFFSET             0
+#define IP4_RUL_V0_DIPV_BLEN                32
+#define IP4_RUL_V0_DIPV_FLAG                HSL_RW
+
+
+
+
+#define IP4_RUL_V1                         "ip4v1"
+#define IP4_RUL_V1_ID                      13
+#define IP4_RUL_V1_OFFSET                  0x58404
+#define IP4_RUL_V1_E_LENGTH                4
+#define IP4_RUL_V1_E_OFFSET                0x20
+#define IP4_RUL_V1_NR_E                    32
+
+#define SIPV                               "ip4v1_sipv"
+#define IP4_RUL_V1_SIPV_BOFFSET             0
+#define IP4_RUL_V1_SIPV_BLEN                32
+#define IP4_RUL_V1_SIPV_FLAG                HSL_RW
+
+
+
+
+#define IP4_RUL_V2                         "ip4v2"
+#define IP4_RUL_V2_ID                      13
+#define IP4_RUL_V2_OFFSET                  0x58408
+#define IP4_RUL_V2_E_LENGTH                4
+#define IP4_RUL_V2_E_OFFSET                0x20
+#define IP4_RUL_V2_NR_E                    32
+
+#define IP4PROTV                               "ip4v2_protv"
+#define IP4_RUL_V2_IP4PROTV_BOFFSET             0
+#define IP4_RUL_V2_IP4PROTV_BLEN                8
+#define IP4_RUL_V2_IP4PROTV_FLAG                HSL_RW
+
+#define IP4DSCPV                               "ip4v2_dscpv"
+#define IP4_RUL_V2_IP4DSCPV_BOFFSET             8
+#define IP4_RUL_V2_IP4DSCPV_BLEN                8
+#define IP4_RUL_V2_IP4DSCPV_FLAG                HSL_RW
+
+#define IP4DPORTV                               "ip4v2_dportv"
+#define IP4_RUL_V2_IP4DPORTV_BOFFSET             16
+#define IP4_RUL_V2_IP4DPORTV_BLEN                16
+#define IP4_RUL_V2_IP4DPORTV_FLAG                HSL_RW
+
+
+
+
+#define IP4_RUL_V3                         "ip4v3"
+#define IP4_RUL_V3_ID                      13
+#define IP4_RUL_V3_OFFSET                  0x5840c
+#define IP4_RUL_V3_E_LENGTH                4
+#define IP4_RUL_V3_E_OFFSET                0x20
+#define IP4_RUL_V3_NR_E                    32
+
+#define IP4SPORTV                          "ip4v3_sportv"
+#define IP4_RUL_V3_IP4SPORTV_BOFFSET       0
+#define IP4_RUL_V3_IP4SPORTV_BLEN          16
+#define IP4_RUL_V3_IP4SPORTV_FLAG          HSL_RW
+
+
+#define IP4_RUL_V4                         "ip4v2"
+#define IP4_RUL_V4_ID                      13
+#define IP4_RUL_V4_OFFSET                  0x58410
+#define IP4_RUL_V4_E_LENGTH                4
+#define IP4_RUL_V4_E_OFFSET                0x20
+#define IP4_RUL_V4_NR_E                    32
+
+#define IP4_INPT                            "ip4rv4_inpt"
+#define IP4_RUL_V4_IP4_INPT_BOFFSET             0
+#define IP4_RUL_V4_IP4_INPT_BLEN                6
+#define IP4_RUL_V4_IP4_INPT_FLAG                HSL_RW
+
+
+
+
+
+
+#define IP4_RUL_M0                         "ip4m0"
+#define IP4_RUL_M0_ID                      13
+#define IP4_RUL_M0_OFFSET                  0x58c00
+#define IP4_RUL_M0_E_LENGTH                4
+#define IP4_RUL_M0_E_OFFSET                0x20
+#define IP4_RUL_M0_NR_E                    32
+
+#define DIPM                             "ip4m0_dipm"
+#define IP4_RUL_M0_DIPM_BOFFSET             0
+#define IP4_RUL_M0_DIPM_BLEN                32
+#define IP4_RUL_M0_DIPM_FLAG                HSL_RW
+
+
+
+
+#define IP4_RUL_M1                         "ip4m1"
+#define IP4_RUL_M1_ID                      13
+#define IP4_RUL_M1_OFFSET                  0x58c04
+#define IP4_RUL_M1_E_LENGTH                4
+#define IP4_RUL_M1_E_OFFSET                0x20
+#define IP4_RUL_M1_NR_E                    32
+
+#define SIPM                               "ip4m1_sipm"
+#define IP4_RUL_M1_SIPM_BOFFSET             0
+#define IP4_RUL_M1_SIPM_BLEN                32
+#define IP4_RUL_M1_SIPM_FLAG                HSL_RW
+
+
+
+
+#define IP4_RUL_M2                         "ip4m2"
+#define IP4_RUL_M2_ID                      13
+#define IP4_RUL_M2_OFFSET                  0x58c08
+#define IP4_RUL_M2_E_LENGTH                4
+#define IP4_RUL_M2_E_OFFSET                0x20
+#define IP4_RUL_M2_NR_E                    32
+
+#define IP4PROTM                               "ip4m2_protm"
+#define IP4_RUL_M2_IP4PROTM_BOFFSET             0
+#define IP4_RUL_M2_IP4PROTM_BLEN                8
+#define IP4_RUL_M2_IP4PROTM_FLAG                HSL_RW
+
+#define IP4DSCPM                               "ip4m2_dscpm"
+#define IP4_RUL_M2_IP4DSCPM_BOFFSET             8
+#define IP4_RUL_M2_IP4DSCPM_BLEN                8
+#define IP4_RUL_M2_IP4DSCPM_FLAG                HSL_RW
+
+#define IP4DPORTM                               "ip4m2_dportm"
+#define IP4_RUL_M2_IP4DPORTM_BOFFSET             16
+#define IP4_RUL_M2_IP4DPORTM_BLEN                16
+#define IP4_RUL_M2_IP4DPORTM_FLAG                HSL_RW
+
+
+
+
+#define IP4_RUL_M3                         "ip4m3"
+#define IP4_RUL_M3_ID                      13
+#define IP4_RUL_M3_OFFSET                  0x58c0c
+#define IP4_RUL_M3_E_LENGTH                4
+#define IP4_RUL_M3_E_OFFSET                0x20
+#define IP4_RUL_M3_NR_E                    32
+
+#define IP4SPORTM                               "ip4m3_sportm"
+#define IP4_RUL_M3_IP4SPORTM_BOFFSET             0
+#define IP4_RUL_M3_IP4SPORTM_BLEN                16
+#define IP4_RUL_M3_IP4SPORTM_FLAG                HSL_RW
+
+#define IP4SPORTM_EN                             "ip4m3_sportmen"
+#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET           16
+#define IP4_RUL_M3_IP4SPORTM_EN_BLEN                1
+#define IP4_RUL_M3_IP4SPORTM_EN_FLAG                HSL_RW
+
+#define IP4DPORTM_EN                               "ip4m3_dportmen"
+#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET             17
+#define IP4_RUL_M3_IP4DPORTM_EN_BLEN                1
+#define IP4_RUL_M3_IP4DPORTM_EN_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL1_V0                        "ip6r1v0"
+#define IP6_RUL1_V0_ID                      13
+#define IP6_RUL1_V0_OFFSET                  0x58400
+#define IP6_RUL1_V0_E_LENGTH                4
+#define IP6_RUL1_V0_E_OFFSET                0x20
+#define IP6_RUL1_V0_NR_E                    32
+
+#define IP6_DIPV0                           "ip6r1v0_dipv0"
+#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET             0
+#define IP6_RUL1_V0_IP6_DIPV0_BLEN                32
+#define IP6_RUL1_V0_IP6_DIPV0_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL1_V1                        "ip6r1v1"
+#define IP6_RUL1_V1_ID                      13
+#define IP6_RUL1_V1_OFFSET                  0x58404
+#define IP6_RUL1_V1_E_LENGTH                4
+#define IP6_RUL1_V1_E_OFFSET                0x20
+#define IP6_RUL1_V1_NR_E                    32
+
+#define IP6_DIPV1                           "ip6r1v1_dipv1"
+#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET             0
+#define IP6_RUL1_V1_IP6_DIPv1_BLEN                32
+#define IP6_RUL1_V1_IP6_DIPV1_FLAG                HSL_RW
+
+
+
+#define IP6_RUL1_V2                        "ip6r1v2"
+#define IP6_RUL1_V2_ID                      13
+#define IP6_RUL1_V2_OFFSET                  0x58408
+#define IP6_RUL1_V2_E_LENGTH                4
+#define IP6_RUL1_V2_E_OFFSET                0x20
+#define IP6_RUL1_V2_NR_E                    32
+
+#define IP6_DIPV2                           "ip6r1v2_dipv2"
+#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET             0
+#define IP6_RUL1_V2_IP6_DIPv2_BLEN                32
+#define IP6_RUL1_V2_IP6_DIPV2_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL1_V3                        "ip6r1v3"
+#define IP6_RUL1_V3_ID                      13
+#define IP6_RUL1_V3_OFFSET                  0x5840c
+#define IP6_RUL1_V3_E_LENGTH                4
+#define IP6_RUL1_V3_E_OFFSET                0x20
+#define IP6_RUL1_V3_NR_E                    32
+
+#define IP6_DIPV3                           "ip6r1v3_dipv3"
+#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET             0
+#define IP6_RUL1_V3_IP6_DIPv3_BLEN                32
+#define IP6_RUL1_V3_IP6_DIPV3_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL1_V4                        "ip6r1v4"
+#define IP6_RUL1_V4_ID                      13
+#define IP6_RUL1_V4_OFFSET                  0x58410
+#define IP6_RUL1_V4_E_LENGTH                4
+#define IP6_RUL1_V4_E_OFFSET                0x20
+#define IP6_RUL1_V4_NR_E                    32
+
+#define IP6_RUL1_INPT                           "ip6r1v4_inpt"
+#define IP6_RUL1_V4_IP6_RUL1_INPT_BOFFSET             0
+#define IP6_RUL1_V4_IP6_RUL1_INPT_BLEN                6
+#define IP6_RUL1_V4_IP6_RUL1_INPT_FLAG                HSL_RW
+
+
+
+
+
+#define IP6_RUL1_M0                        "ip6r1m0"
+#define IP6_RUL1_M0_ID                      13
+#define IP6_RUL1_M0_OFFSET                  0x58c00
+#define IP6_RUL1_M0_E_LENGTH                4
+#define IP6_RUL1_M0_E_OFFSET                0x20
+#define IP6_RUL1_M0_NR_E                    32
+
+#define IP6_DIPM0                           "ip6r1m0_dipm0"
+#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET             0
+#define IP6_RUL1_M0_IP6_DIPM0_BLEN                32
+#define IP6_RUL1_M0_IP6_DIPM0_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL1_M1                        "ip6r1m1"
+#define IP6_RUL1_M1_ID                      13
+#define IP6_RUL1_M1_OFFSET                  0x58c04
+#define IP6_RUL1_M1_E_LENGTH                4
+#define IP6_RUL1_M1_E_OFFSET                0x20
+#define IP6_RUL1_M1_NR_E                    32
+
+#define IP6_DIPM1                           "ip6r1m1_dipm1"
+#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET             0
+#define IP6_RUL1_M1_IP6_DIPM1_BLEN                32
+#define IP6_RUL1_M1_IP6_DIPM1_FLAG                HSL_RW
+
+
+
+#define IP6_RUL1_M2                        "ip6r1m2"
+#define IP6_RUL1_M2_ID                      13
+#define IP6_RUL1_M2_OFFSET                  0x58c08
+#define IP6_RUL1_M2_E_LENGTH                4
+#define IP6_RUL1_M2_E_OFFSET                0x20
+#define IP6_RUL1_M2_NR_E                    32
+
+#define IP6_DIPM2                           "ip6r1m2_dipm2"
+#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET             0
+#define IP6_RUL1_M2_IP6_DIPM2_BLEN                32
+#define IP6_RUL1_M2_IP6_DIPM2_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL1_M3                        "ip6r1m3"
+#define IP6_RUL1_M3_ID                      13
+#define IP6_RUL1_M3_OFFSET                  0x58c0c
+#define IP6_RUL1_M3_E_LENGTH                4
+#define IP6_RUL1_M3_E_OFFSET                0x20
+#define IP6_RUL1_M3_NR_E                    32
+
+#define IP6_DIPM3                           "ip6r1m3_dipm3"
+#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET             0
+#define IP6_RUL1_M3_IP6_DIPM3_BLEN                32
+#define IP6_RUL1_M3_IP6_DIPM3_FLAG                HSL_RW
+
+
+
+
+
+#define IP6_RUL2_V0                        "ip6r2v0"
+#define IP6_RUL2_V0_ID                      13
+#define IP6_RUL2_V0_OFFSET                  0x58400
+#define IP6_RUL2_V0_E_LENGTH                4
+#define IP6_RUL2_V0_E_OFFSET                0x20
+#define IP6_RUL2_V0_NR_E                    32
+
+#define IP6_SIPV0                           "ip6r2v0_sipv0"
+#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET             0
+#define IP6_RUL2_V0_IP6_SIPv0_BLEN                32
+#define IP6_RUL2_V0_IP6_SIPV0_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL2_V1                        "ip6r2v1"
+#define IP6_RUL2_V1_ID                      13
+#define IP6_RUL2_V1_OFFSET                  0x58404
+#define IP6_RUL2_V1_E_LENGTH                4
+#define IP6_RUL2_V1_E_OFFSET                0x20
+#define IP6_RUL2_V1_NR_E                    32
+
+#define IP6_SIPV1                           "ip6r2v1_sipv1"
+#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET             0
+#define IP6_RUL2_V1_IP6_SIPv1_BLEN                32
+#define IP6_RUL2_V1_IP6_SIPV1_FLAG                HSL_RW
+
+
+
+#define IP6_RUL2_V2                        "ip6r2v2"
+#define IP6_RUL2_V2_ID                      13
+#define IP6_RUL2_V2_OFFSET                  0x58408
+#define IP6_RUL2_V2_E_LENGTH                4
+#define IP6_RUL2_V2_E_OFFSET                0x20
+#define IP6_RUL2_V2_NR_E                    32
+
+#define IP6_SIPV2                           "ip6r2v2_sipv2"
+#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET             0
+#define IP6_RUL2_V2_IP6_SIPv2_BLEN                32
+#define IP6_RUL2_V2_IP6_SIPV2_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL2_V3                        "ip6r2v3"
+#define IP6_RUL2_V3_ID                      13
+#define IP6_RUL2_V3_OFFSET                  0x5840c
+#define IP6_RUL2_V3_E_LENGTH                4
+#define IP6_RUL2_V3_E_OFFSET                0x20
+#define IP6_RUL2_V3_NR_E                    32
+
+#define IP6_SIPV3                           "ip6r2v3_sipv3"
+#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET             0
+#define IP6_RUL2_V3_IP6_SIPv3_BLEN                32
+#define IP6_RUL2_V3_IP6_SIPV3_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL2_V4                        "ip6r2v4"
+#define IP6_RUL2_V4_ID                      13
+#define IP6_RUL2_V4_OFFSET                  0x58410
+#define IP6_RUL2_V4_E_LENGTH                4
+#define IP6_RUL2_V4_E_OFFSET                0x20
+#define IP6_RUL2_V4_NR_E                    32
+
+#define IP6_RUL2_INPT                           "ip6r2v4_inptm"
+#define IP6_RUL2_V4_IP6_RUL2_INPT_BOFFSET             0
+#define IP6_RUL2_V4_IP6_RUL2_INPT_BLEN                6
+#define IP6_RUL2_V4_IP6_RUL2_INPT_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL2_M0                        "ip6r2m0"
+#define IP6_RUL2_M0_ID                      13
+#define IP6_RUL2_M0_OFFSET                  0x58c00
+#define IP6_RUL2_M0_E_LENGTH                4
+#define IP6_RUL2_M0_E_OFFSET                0x20
+#define IP6_RUL2_M0_NR_E                    32
+
+#define IP6_SIPM0                           "ip6r2m0_sipm0"
+#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET             0
+#define IP6_RUL2_M0_IP6_SIPM0_BLEN                32
+#define IP6_RUL2_M0_IP6_SIPM0_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL2_M1                        "ip6r2m1"
+#define IP6_RUL2_M1_ID                      13
+#define IP6_RUL2_M1_OFFSET                  0x58c04
+#define IP6_RUL2_M1_E_LENGTH                4
+#define IP6_RUL2_M1_E_OFFSET                0x20
+#define IP6_RUL2_M1_NR_E                    32
+
+#define IP6_SIPM1                           "ip6r2m1_sipm1"
+#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET             0
+#define IP6_RUL2_M1_IP6_DIPM1_BLEN                32
+#define IP6_RUL2_M1_IP6_DIPM1_FLAG                HSL_RW
+
+
+
+#define IP6_RUL2_M2                        "ip6r2m2"
+#define IP6_RUL2_M2_ID                      13
+#define IP6_RUL2_M2_OFFSET                  0x58c08
+#define IP6_RUL2_M2_E_LENGTH                4
+#define IP6_RUL2_M2_E_OFFSET                0x20
+#define IP6_RUL2_M2_NR_E                    32
+
+#define IP6_SIPM2                           "ip6r2m2_sipm2"
+#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET             0
+#define IP6_RUL2_M2_IP6_DIPM2_BLEN                32
+#define IP6_RUL2_M2_IP6_DIPM2_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL2_M3                        "ip6r2m3"
+#define IP6_RUL2_M3_ID                      13
+#define IP6_RUL2_M3_OFFSET                  0x58c0c
+#define IP6_RUL2_M3_E_LENGTH                4
+#define IP6_RUL2_M3_E_OFFSET                0x20
+#define IP6_RUL2_M3_NR_E                    32
+
+#define IP6_SIPM3                           "ip6r2m3_sipm3"
+#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET             0
+#define IP6_RUL2_M3_IP6_SIPM3_BLEN                32
+#define IP6_RUL2_M3_IP6_SIPM3_FLAG                HSL_RW
+
+
+
+
+
+#define IP6_RUL3_V0                        "ip6r3v0"
+#define IP6_RUL3_V0_ID                      13
+#define IP6_RUL3_V0_OFFSET                  0x58400
+#define IP6_RUL3_V0_E_LENGTH                4
+#define IP6_RUL3_V0_E_OFFSET                0x20
+#define IP6_RUL3_V0_NR_E                    32
+
+#define IP6PROTV                           "ip6r3v0_protv"
+#define IP6_RUL3_V0_IP6PROTV_BOFFSET             0
+#define IP6_RUL3_V0_IP6PROTV_BLEN                8
+#define IP6_RUL3_V0_IP6PROTV_FLAG                HSL_RW
+
+#define IP6DSCPV                           "ip6r3v0_dscpv"
+#define IP6_RUL3_V0_IP6DSCPV_BOFFSET             8
+#define IP6_RUL3_V0_IP6DSCPV_BLEN                8
+#define IP6_RUL3_V0_IP6DSCPV_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL3_V1                        "ip6r3v1"
+#define IP6_RUL3_V1_ID                      13
+#define IP6_RUL3_V1_OFFSET                  0x58404
+#define IP6_RUL3_V1_E_LENGTH                4
+#define IP6_RUL3_V1_E_OFFSET                0x20
+#define IP6_RUL3_V1_NR_E                    32
+
+#define IP6LABEL1V                           "ip6r3v1_label1v"
+#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET             16
+#define IP6_RUL3_V1_IP6LABEL1V_BLEN                16
+#define IP6_RUL3_V1_IP6LABEL1V_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL3_V2                        "ip6r3v2"
+#define IP6_RUL3_V2_ID                      13
+#define IP6_RUL3_V2_OFFSET                  0x58408
+#define IP6_RUL3_V2_E_LENGTH                4
+#define IP6_RUL3_V2_E_OFFSET                0x20
+#define IP6_RUL3_V2_NR_E                    32
+
+#define IP6LABEL2V                           "ip6r3v2_label2v"
+#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET             0
+#define IP6_RUL3_V2_IP6LABEL2V_BLEN                4
+#define IP6_RUL3_V2_IP6LABEL2V_FLAG                HSL_RW
+
+#define IP6DPORTV                           "ip6r3v2_dportv"
+#define IP6_RUL3_V2_IP6DPORTV_BOFFSET             16
+#define IP6_RUL3_V2_IP6DPORTV_BLEN                16
+#define IP6_RUL3_V2_IP6DPORTV_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL3_V3                        "ip6r3v3"
+#define IP6_RUL3_V3_ID                      13
+#define IP6_RUL3_V3_OFFSET                  0x5840c
+#define IP6_RUL3_V3_E_LENGTH                4
+#define IP6_RUL3_V3_E_OFFSET                0x20
+#define IP6_RUL3_V3_NR_E                    32
+
+#define IP6SPORTV                           "ip6r3v3_sportv"
+#define IP6_RUL3_V3_IP6SPORTV_BOFFSET             0
+#define IP6_RUL3_V3_IP6SPORTV_BLEN                16
+#define IP6_RUL3_V3_IP6SPORTV_FLAG                HSL_RW
+
+
+
+#define IP6_RUL3_M0                        "ip6r3m0"
+#define IP6_RUL3_M0_ID                      13
+#define IP6_RUL3_M0_OFFSET                  0x58c00
+#define IP6_RUL3_M0_E_LENGTH                4
+#define IP6_RUL3_M0_E_OFFSET                0x20
+#define IP6_RUL3_M0_NR_E                    32
+
+#define IP6PROTM                           "ip6r3m0_protm"
+#define IP6_RUL3_M0_IP6PROTM_BOFFSET             0
+#define IP6_RUL3_M0_IP6PROTM_BLEN                8
+#define IP6_RUL3_M0_IP6PROTM_FLAG                HSL_RW
+
+#define IP6DSCPM                           "ip6r3m0_dscpm"
+#define IP6_RUL3_M0_IP6DSCPM_BOFFSET             8
+#define IP6_RUL3_M0_IP6DSCPM_BLEN                8
+#define IP6_RUL3_M0_IP6DSCPM_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL3_M1                        "ip6r3m1"
+#define IP6_RUL3_M1_ID                      13
+#define IP6_RUL3_M1_OFFSET                  0x58c04
+#define IP6_RUL3_M1_E_LENGTH                4
+#define IP6_RUL3_M1_E_OFFSET                0x20
+#define IP6_RUL3_M1_NR_E                    32
+
+#define IP6LABEL1M                           "ip6r3m1_label1m"
+#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET             16
+#define IP6_RUL3_M1_IP6LABEL1M_BLEN                16
+#define IP6_RUL3_M1_IP6LABEL1M_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL3_M2                        "ip6r3m2"
+#define IP6_RUL3_M2_ID                      13
+#define IP6_RUL3_M2_OFFSET                  0x58c08
+#define IP6_RUL3_M2_E_LENGTH                4
+#define IP6_RUL3_M2_E_OFFSET                0x20
+#define IP6_RUL3_M2_NR_E                    32
+
+#define IP6LABEL2M                           "ip6r3m2_label2m"
+#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET             0
+#define IP6_RUL3_M2_IP6LABEL2M_BLEN                4
+#define IP6_RUL3_M2_IP6LABEL21M_FLAG                HSL_RW
+
+#define IP6DPORTM                           "ip6r3m2_dportm"
+#define IP6_RUL3_M2_IP6DPORTM_BOFFSET             16
+#define IP6_RUL3_M2_IP6DPORTM_BLEN                16
+#define IP6_RUL3_M2_IP6DPORTM_FLAG                HSL_RW
+
+
+
+
+#define IP6_RUL3_M3                        "ip6r3m3"
+#define IP6_RUL3_M3_ID                      13
+#define IP6_RUL3_M3_OFFSET                  0x58c0c
+#define IP6_RUL3_M3_E_LENGTH                4
+#define IP6_RUL3_M3_E_OFFSET                0x20
+#define IP6_RUL3_M3_NR_E                    32
+
+#define IP6SPORTM                           "ip6r3m3_sportm"
+#define IP6_RUL3_M3_IP6SPORTM_BOFFSET             0
+#define IP6_RUL3_M3_IP6SPORTM_BLEN                16
+#define IP6_RUL3_M3_IP6SPORTM_FLAG                HSL_RW
+
+#define IP6DPORTM_EN                               "ip6r3m3_dportmen"
+#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET             17
+#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN                1
+#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG                HSL_RW
+
+#define IP6SPORTM_EN                               "ip6r3m3_sportmen"
+#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET             16
+#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN                1
+#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG                HSL_RW
+
+
+
+
+#define UDF_RUL_V4                                  "udfv4"
+#define UDF_RUL_V4_ID                               13
+#define UDF_RUL_V4_OFFSET                           0x58410
+#define UDF_RUL_V4_E_LENGTH                         4
+#define UDF_RUL_V4_E_OFFSET                         0x20
+#define UDF_RUL_V4_NR_E                             32
+
+
+#define LAYER_TYP                                   "udfv4_typ"
+#define UDF_RUL_V4_LAYER_TYP_BOFFSET                7
+#define UDF_RUL_V4_LAYER_TYP_BLEN                   1
+#define UDF_RUL_V4_LAYER_TYP_FLAG                   HSL_RW
+
+#define LAYER_OFFSET                                "udfv4_offset"
+#define UDF_RUL_V4_LAYER_OFFSET_BOFFSET             0
+#define UDF_RUL_V4_LAYER_OFFSET_BLEN                7
+#define UDF_RUL_V4_LAYER_OFFSET_FLAG                HSL_RW
+
+
+
+
+#define PPPOE_SESSION                              "pppoes"
+#define PPPOE_SESSION_ID                           13
+#define PPPOE_SESSION_OFFSET                       0x59100
+#define PPPOE_SESSION_E_LENGTH                     4
+#define PPPOE_SESSION_E_OFFSET                     0x4
+#define PPPOE_SESSION_NR_E                         16
+
+#define ENTRY_VALID                                "pppoes_v"
+#define PPPOE_SESSION_ENTRY_VALID_BOFFSET          19
+#define PPPOE_SESSION_ENTRY_VALID_BLEN             1
+#define PPPOE_SESSION_ENTRY_VALID_FLAG             HSL_RW
+
+#define STRIP_EN                                   "pppoes_s"
+#define PPPOE_SESSION_STRIP_EN_BOFFSET             16
+#define PPPOE_SESSION_STRIP_EN_BLEN                1
+#define PPPOE_SESSION_STRIP_EN_FLAG                HSL_RW
+
+#define SEESION_ID                                 "pppoes_id"
+#define PPPOE_SESSION_SEESION_ID_BOFFSET           0
+#define PPPOE_SESSION_SEESION_ID_BLEN              16
+#define PPPOE_SESSION_SEESION_ID_FLAG              HSL_RW
+
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SHIVA_REG_H_ */
+
diff --git a/qca-ssdk/include/hsl/shiva/shiva_reg_access.h b/qca-ssdk/include/hsl/shiva/shiva_reg_access.h
new file mode 100755
index 0000000..5cb9df6
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_reg_access.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _SHIVA_REG_ACCESS_H_
+#define _SHIVA_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "sw.h"
+
+    sw_error_t
+    shiva_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+                  a_uint32_t reg, a_uint16_t * value);
+
+    sw_error_t
+    shiva_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+                  a_uint32_t reg, a_uint16_t value);
+
+    sw_error_t
+    shiva_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                  a_uint32_t value_len);
+
+    sw_error_t
+    shiva_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                  a_uint32_t value_len);
+
+    sw_error_t
+    shiva_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                        a_uint32_t bit_offset, a_uint32_t field_len,
+                        a_uint8_t value[], a_uint32_t value_len);
+
+    sw_error_t
+    shiva_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                        a_uint32_t bit_offset, a_uint32_t field_len,
+                        const a_uint8_t value[], a_uint32_t value_len);
+
+    sw_error_t
+    shiva_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode);
+
+    sw_error_t
+    shiva_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHIVA_REG_ACCESS_H_ */
+
diff --git a/qca-ssdk/include/hsl/shiva/shiva_stp.h b/qca-ssdk/include/hsl/shiva/shiva_stp.h
new file mode 100755
index 0000000..6d21955
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_stp.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_stp SHIVA_STP
+ * @{
+ */
+#ifndef _SHIVA_STP_H_
+#define _SHIVA_STP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "fal/fal_stp.h"
+
+    sw_error_t shiva_stp_init(a_uint32_t dev_id);
+
+#ifdef IN_STP
+#define SHIVA_STP_INIT(rv, dev_id) \
+    { \
+        rv = shiva_stp_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define SHIVA_STP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    shiva_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                             fal_port_t port_id, fal_stp_state_t state);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                             fal_port_t port_id, fal_stp_state_t * state);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SHIVA_STP_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/hsl/shiva/shiva_vlan.h b/qca-ssdk/include/hsl/shiva/shiva_vlan.h
new file mode 100755
index 0000000..5d50dfc
--- /dev/null
+++ b/qca-ssdk/include/hsl/shiva/shiva_vlan.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_vlan SHIVA_VLAN
+ * @{
+ */
+#ifndef _SHIVA_VLAN_H_
+#define _SHIVA_VLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_vlan.h"
+
+    sw_error_t
+    shiva_vlan_init(a_uint32_t dev_id);
+
+#ifdef IN_VLAN
+#define SHIVA_VLAN_INIT(rv, dev_id) \
+    { \
+        rv = shiva_vlan_init(dev_id); \
+        SW_RTN_ON_ERROR(rv); \
+    }
+#else
+#define SHIVA_VLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+    HSL_LOCAL sw_error_t
+    shiva_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                             fal_pbmp_t member, fal_pbmp_t u_member);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+    HSL_LOCAL sw_error_t
+    shiva_vlan_flush(a_uint32_t dev_id);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHIVA_VLAN_H_ */
+/**
+ * @}
+ */
diff --git a/qca-ssdk/include/init/ssdk_clk.h b/qca-ssdk/include/init/ssdk_clk.h
new file mode 100755
index 0000000..e03c76a
--- /dev/null
+++ b/qca-ssdk/include/init/ssdk_clk.h
@@ -0,0 +1,313 @@
+/*
+ * Copyright (c) 2017, 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+ #ifndef _SSDK_CLK_H_
+#define _SSDK_CLK_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#define PPE_RESET_ID	"ppe_rst"
+#define UNIPHY0_SOFT_RESET_ID	"uniphy0_soft_rst"
+#define UNIPHY0_XPCS_RESET_ID	"uniphy0_xpcs_rst"
+#define UNIPHY1_SOFT_RESET_ID	"uniphy1_soft_rst"
+#define UNIPHY1_XPCS_RESET_ID	"uniphy1_xpcs_rst"
+#define UNIPHY2_SOFT_RESET_ID	"uniphy2_soft_rst"
+#define UNIPHY2_XPCS_RESET_ID	"uniphy2_xpcs_rst"
+#define UNIPHY0_PORT1_DISABLE_ID	"uniphy0_port1_dis"
+#define UNIPHY0_PORT2_DISABLE_ID	"uniphy0_port2_dis"
+#define UNIPHY0_PORT3_DISABLE_ID	"uniphy0_port3_dis"
+#define UNIPHY0_PORT4_DISABLE_ID	"uniphy0_port4_dis"
+#define UNIPHY0_PORT5_DISABLE_ID	"uniphy0_port5_dis"
+#define UNIPHY0_PORT_4_5_RESET_ID	"uniphy0_port_4_5_rst"
+#define UNIPHY0_PORT_4_RESET_ID	"uniphy0_port_4_rst"
+
+#define SSDK_PORT1_RESET_ID	"nss_port1_rst"
+#define SSDK_PORT2_RESET_ID	"nss_port2_rst"
+#define SSDK_PORT3_RESET_ID	"nss_port3_rst"
+#define SSDK_PORT4_RESET_ID	"nss_port4_rst"
+#define SSDK_PORT5_RESET_ID	"nss_port5_rst"
+#define SSDK_PORT6_RESET_ID	"nss_port6_rst"
+
+enum ssdk_rst_action {
+        SSDK_RESET_DEASSERT      = 0,
+        SSDK_RESET_ASSERT        = 1
+};
+
+enum unphy_rst_type {
+	UNIPHY0_SOFT_RESET_E = 0,
+	UNIPHY0_XPCS_RESET_E,
+	UNIPHY1_SOFT_RESET_E,
+	UNIPHY1_XPCS_RESET_E,
+	UNIPHY2_SOFT_RESET_E,
+	UNIPHY2_XPCS_RESET_E,
+	UNIPHY0_PORT1_DISABLE_E,
+	UNIPHY0_PORT2_DISABLE_E,
+	UNIPHY0_PORT3_DISABLE_E,
+	UNIPHY0_PORT4_DISABLE_E,
+	UNIPHY0_PORT5_DISABLE_E,
+	UNIPHY0_PORT_4_5_RESET_E,
+	UNIPHY0_PORT_4_RESET_E,
+	UNIPHY_RST_MAX
+};
+
+#define CMN_AHB_CLK		"cmn_ahb_clk"
+#define CMN_SYS_CLK		"cmn_sys_clk"
+#define UNIPHY0_AHB_CLK	"uniphy0_ahb_clk"
+#define UNIPHY0_SYS_CLK	"uniphy0_sys_clk"
+#define UNIPHY1_AHB_CLK	"uniphy1_ahb_clk"
+#define UNIPHY1_SYS_CLK	"uniphy1_sys_clk"
+#define UNIPHY2_AHB_CLK	"uniphy2_ahb_clk"
+#define UNIPHY2_SYS_CLK	"uniphy2_sys_clk"
+#define PORT1_MAC_CLK		"port1_mac_clk"
+#define PORT2_MAC_CLK		"port2_mac_clk"
+#define PORT3_MAC_CLK		"port3_mac_clk"
+#define PORT4_MAC_CLK		"port4_mac_clk"
+#define PORT5_MAC_CLK		"port5_mac_clk"
+#define PORT6_MAC_CLK		"port6_mac_clk"
+#define NSS_PPE_CLK		"nss_ppe_clk"
+#define NSS_PPE_CFG_CLK	"nss_ppe_cfg_clk"
+#define NSSNOC_PPE_CLK		"nssnoc_ppe_clk"
+#define NSSNOC_PPE_CFG_CLK	"nssnoc_ppe_cfg_clk"
+#define NSS_EDMA_CLK		"nss_edma_clk"
+#define NSS_EDMA_CFG_CLK	"nss_edma_cfg_clk"
+#define NSS_PPE_IPE_CLK		"nss_ppe_ipe_clk"
+#define NSS_PPE_BTQ_CLK	"nss_ppe_btq_clk"
+#define MDIO_AHB_CLK		"gcc_mdio_ahb_clk"
+#define NSSNOC_CLK		"gcc_nss_noc_clk"
+#define NSSNOC_SNOC_CLK	"gcc_nssnoc_snoc_clk"
+#define MEM_NOC_NSSAXI_CLK	"gcc_mem_noc_nss_axi_clk"
+#define CRYPTO_PPE_CLK		"gcc_nss_crypto_clk"
+#define NSS_IMEM_CLK		"gcc_nss_imem_clk"
+#define NSS_PTP_REF_CLK	"gcc_nss_ptp_ref_clk"
+#define SNOC_NSSNOC_CLK	"gcc_snoc_nssnoc_clk"
+
+#define UNIPHY_AHB_CLK	"uniphy_ahb_clk"
+#define UNIPHY_SYS_CLK	"uniphy_sys_clk"
+#define MP_UNIPHY_SYS_CLK_RATE	24000000
+#define MDIO0_AHB_CLK		"gcc_mdio0_ahb_clk"
+#define MDIO1_AHB_CLK		"gcc_mdio1_ahb_clk"
+#define GMAC0_CFG_CLK		"gcc_gmac0_cfg_clk"
+#define GMAC0_SYS_CLK		"gcc_gmac0_sys_clk"
+#define GMAC1_CFG_CLK		"gcc_gmac1_cfg_clk"
+#define GMAC1_SYS_CLK		"gcc_gmac1_sys_clk"
+#define SNOC_GMAC0_AHB_CLK		"gcc_snoc_gmac0_ahb_clk"
+#define SNOC_GMAC1_AHB_CLK		"gcc_snoc_gmac1_ahb_clk"
+#define GMAC0_PTP_CLK		"gcc_gmac0_ptp_clk"
+#define GMAC1_PTP_CLK		"gcc_gmac1_ptp_clk"
+#define GMAC_CLK_RATE		240000000
+
+#define NSS_PORT1_RX_CLK	"nss_port1_rx_clk"
+#define NSS_PORT1_TX_CLK	"nss_port1_tx_clk"
+#define NSS_PORT2_RX_CLK	"nss_port2_rx_clk"
+#define NSS_PORT2_TX_CLK	"nss_port2_tx_clk"
+#define NSS_PORT3_RX_CLK	"nss_port3_rx_clk"
+#define NSS_PORT3_TX_CLK	"nss_port3_tx_clk"
+#define NSS_PORT4_RX_CLK	"nss_port4_rx_clk"
+#define NSS_PORT4_TX_CLK	"nss_port4_tx_clk"
+#define NSS_PORT5_RX_CLK	"nss_port5_rx_clk"
+#define NSS_PORT5_TX_CLK	"nss_port5_tx_clk"
+#define NSS_PORT6_RX_CLK	"nss_port6_rx_clk"
+#define NSS_PORT6_TX_CLK	"nss_port6_tx_clk"
+#define UNIPHY0_PORT1_RX_CLK	"uniphy0_port1_rx_clk"
+#define UNIPHY0_PORT1_TX_CLK	"uniphy0_port1_tx_clk"
+#define UNIPHY0_PORT2_RX_CLK	"uniphy0_port2_rx_clk"
+#define UNIPHY0_PORT2_TX_CLK	"uniphy0_port2_tx_clk"
+#define UNIPHY0_PORT3_RX_CLK	"uniphy0_port3_rx_clk"
+#define UNIPHY0_PORT3_TX_CLK	"uniphy0_port3_tx_clk"
+#define UNIPHY0_PORT4_RX_CLK	"uniphy0_port4_rx_clk"
+#define UNIPHY0_PORT4_TX_CLK	"uniphy0_port4_tx_clk"
+#define UNIPHY0_PORT5_RX_CLK	"uniphy0_port5_rx_clk"
+#define UNIPHY0_PORT5_TX_CLK	"uniphy0_port5_tx_clk"
+#define UNIPHY1_PORT5_RX_CLK	"uniphy1_port5_rx_clk"
+#define UNIPHY1_PORT5_TX_CLK	"uniphy1_port5_tx_clk"
+#define UNIPHY2_PORT6_RX_CLK	"uniphy2_port6_rx_clk"
+#define UNIPHY2_PORT6_TX_CLK	"uniphy2_port6_tx_clk"
+#define PORT5_RX_SRC		"nss_port5_rx_clk_src"
+#define PORT5_TX_SRC		"nss_port5_tx_clk_src"
+
+enum unphy_clk_type {
+	NSS_PORT1_RX_CLK_E = 0,
+	NSS_PORT1_TX_CLK_E,
+	NSS_PORT2_RX_CLK_E,
+	NSS_PORT2_TX_CLK_E,
+	NSS_PORT3_RX_CLK_E,
+	NSS_PORT3_TX_CLK_E,
+	NSS_PORT4_RX_CLK_E,
+	NSS_PORT4_TX_CLK_E,
+	NSS_PORT5_RX_CLK_E,
+	NSS_PORT5_TX_CLK_E,
+	NSS_PORT6_RX_CLK_E,
+	NSS_PORT6_TX_CLK_E,
+	UNIPHY0_PORT1_RX_CLK_E,
+	UNIPHY0_PORT1_TX_CLK_E,
+	UNIPHY0_PORT2_RX_CLK_E,
+	UNIPHY0_PORT2_TX_CLK_E,
+	UNIPHY0_PORT3_RX_CLK_E,
+	UNIPHY0_PORT3_TX_CLK_E,
+	UNIPHY0_PORT4_RX_CLK_E,
+	UNIPHY0_PORT4_TX_CLK_E,
+	UNIPHY0_PORT5_RX_CLK_E,
+	UNIPHY0_PORT5_TX_CLK_E,
+	UNIPHY1_PORT5_RX_CLK_E,
+	UNIPHY1_PORT5_TX_CLK_E,
+	UNIPHY2_PORT6_RX_CLK_E,
+	UNIPHY2_PORT6_TX_CLK_E,
+	PORT5_RX_SRC_E,
+	PORT5_TX_SRC_E,
+	UNIPHYT_CLK_MAX
+};
+
+enum cmnblk_clk_type {
+	INTERNAL_48MHZ = 0,
+	EXTERNAL_25MHZ,
+	EXTERNAL_31250KHZ,
+	EXTERNAL_40MHZ,
+	EXTERNAL_48MHZ,
+	EXTERNAL_50MHZ,
+	INTERNAL_96MHZ,
+};
+
+enum cmnblk_pll_src_type {
+	CMN_BLK_PLL_SRC_SEL_FROM_REG = 0,
+	CMN_BLK_PLL_SRC_SEL_FROM_LOGIC = 1,
+	CMN_BLK_PLL_SRC_SEL_FROM_PCS = 2,
+};
+
+enum mp_bcr_rst_type {
+	GEPHY_BCR_RESET_E = 0,
+	UNIPHY_BCR_RESET_E,
+	GMAC0_BCR_RESET_E,
+	GMAC1_BCR_RESET_E,
+	GEPHY_MISC_RESET_E,
+	MP_BCR_RST_MAX
+};
+
+#define GEHPY_BCR_RESET_ID	"gephy_bcr_rst"
+#define UNIPHY_BCR_RESET_ID	"uniphy_bcr_rst"
+#define GMAC0_BCR_RESET_ID	"gmac0_bcr_rst"
+#define GMAC1_BCR_RESET_ID	"gmac1_bcr_rst"
+#define GEPHY_MISC_RESET_ID	"gephy_misc_rst"
+
+#define CMN_BLK_ADDR                0x0009B780
+#define CMN_BLK_PLL_SRC_ADDR        0x0009B028
+#define CMN_BLK_SIZE                0x100
+#define PLL_CTRL_SRC_MASK           0xfffffcff
+#define PLL_REFCLK_DIV_MASK         0xfffffe0f
+#define PLL_REFCLK_DIV_2            0x20
+#define FREQUENCY_MASK              0xfffffdf0
+#define INTERNAL_48MHZ_CLOCK        0x7
+#define EXTERNAL_25MHZ_CLOCK        0x203
+#define EXTERNAL_31250KHZ_CLOCK     0x204
+#define EXTERNAL_40MHZ_CLOCK        0x206
+#define EXTERNAL_48MHZ_CLOCK        0x207
+#define EXTERNAL_50MHZ_CLOCK        0x208
+#define UNIPHY_AHB_CLK_RATE         100000000
+#define UNIPHY_SYS_CLK_RATE         19200000
+#define CPPE_UNIPHY_SYS_CLK_RATE    24000000
+#define PPE_CLK_RATE                300000000
+#define MDIO_AHB_RATE               100000000
+#define NSS_NOC_RATE                461500000
+#define NSSNOC_SNOC_RATE            266670000
+#define NSS_IMEM_RATE               400000000
+#define PTP_REF_RARE                150000000
+#define NSS_AXI_RATE                461500000
+#define NSS_PORT5_DFLT_RATE         19200000
+
+#define UNIPHY_CLK_RATE_25M         25000000
+#define UNIPHY_CLK_RATE_50M         50000000
+#define UNIPHY_CLK_RATE_125M        125000000
+#define UNIPHY_CLK_RATE_312M        312500000
+#define UNIPHY_DEFAULT_RATE         UNIPHY_CLK_RATE_125M
+
+#define PQSGMII_SPEED_10M_CLK       2500000
+#define PQSGMII_SPEED_100M_CLK      25000000
+#define PQSGMII_SPEED_1000M_CLK     125000000
+#define USXGMII_SPEED_10M_CLK       1250000
+#define USXGMII_SPEED_100M_CLK      12500000
+#define USXGMII_SPEED_1000M_CLK     125000000
+#define USXGMII_SPEED_2500M_CLK     78125000
+#define USXGMII_SPEED_5000M_CLK     156250000
+#define USXGMII_SPEED_10000M_CLK    312500000
+#define SGMII_PLUS_SPEED_2500M_CLK  312500000
+#define SGMII_SPEED_10M_CLK         2500000
+#define SGMII_SPEED_100M_CLK        25000000
+#define SGMII_SPEED_1000M_CLK       125000000
+
+#define CPPE_XGMAC_CLK_REG          0x0194900c
+#define CPPE_XGMAC_CLK_SIZE         0x10
+#define CPPE_XGMAC_CLK_ENABLE       0x20
+
+enum {
+	UNIPHY_RX = 0,
+	UNIPHY_TX,
+};
+
+void ssdk_uniphy_reset(
+	a_uint32_t dev_id,
+	enum unphy_rst_type rst_type,
+	a_uint32_t action);
+
+void ssdk_port_reset(
+	a_uint32_t dev_id,
+	a_uint32_t port_id,
+	a_uint32_t action);
+
+#if defined(HPPE) || defined(MP)
+void
+qca_gcc_mac_port_clock_set(a_uint32_t dev_id, a_uint32_t port_id,
+                                a_bool_t enable);
+
+void
+qca_gcc_uniphy_port_clock_set(a_uint32_t dev_id, a_uint32_t uniphy_index,
+                                a_uint32_t port_id, a_bool_t enable);
+void ssdk_gcc_clock_init(void);
+void
+ssdk_port_speed_clock_set(
+	a_uint32_t dev_id,
+	a_uint32_t port_id,
+	a_uint32_t rate);
+void ssdk_port_mac_clock_reset(
+	a_uint32_t dev_id,
+	a_uint32_t port_id);
+#endif
+
+#if defined(HPPE)
+void ssdk_ppe_reset_init(void);
+void ssdk_uniphy_raw_clock_reset(a_uint8_t uniphy_index);
+void ssdk_uniphy_raw_clock_set(
+	a_uint8_t uniphy_index,
+	a_uint8_t direction,
+	a_uint32_t clock);
+void ssdk_gcc_uniphy_sys_set(a_uint32_t dev_id, a_uint32_t uniphy_index,
+	a_bool_t enable);
+void ssdk_uniphy_port5_clock_source_set(void);
+#endif
+
+#if defined(MP)
+void ssdk_mp_raw_clock_set(
+	a_uint8_t uniphy_index,
+	a_uint8_t direction,
+	a_uint32_t clock);
+void ssdk_mp_gephy_icc_efuse_load_enable(
+	a_bool_t enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SSDK_CLK_H */
+
diff --git a/qca-ssdk/include/init/ssdk_dts.h b/qca-ssdk/include/init/ssdk_dts.h
new file mode 100644
index 0000000..d7ffe04
--- /dev/null
+++ b/qca-ssdk/include/init/ssdk_dts.h
@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+ #ifndef _SSDK_DTS_H_
+#define _SSDK_DTS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef BOARD_AR71XX
+#include <linux/version.h>
+#endif
+#include "ssdk_init.h"
+#include <linux/phy.h>
+
+typedef struct {
+	a_uint16_t ucastq_start;
+	a_uint16_t ucastq_end;
+	a_uint16_t mcastq_start;
+	a_uint16_t mcastq_end;
+	a_uint8_t l0sp_start;
+	a_uint8_t l0sp_end;
+	a_uint8_t l0cdrr_start;
+	a_uint8_t l0cdrr_end;
+	a_uint8_t l0edrr_start;
+	a_uint8_t l0edrr_end;
+	a_uint8_t l1cdrr_start;
+	a_uint8_t l1cdrr_end;
+	a_uint8_t l1edrr_start;
+	a_uint8_t l1edrr_end;
+} ssdk_dt_portscheduler_cfg;
+
+typedef struct {
+	a_uint8_t valid;
+	a_uint8_t port_id;
+	a_uint8_t cpri;
+	a_uint8_t cdrr_id;
+	a_uint8_t epri;
+	a_uint8_t edrr_id;
+	a_uint8_t sp_id;
+} ssdk_dt_l0scheduler_cfg;
+
+typedef struct {
+	a_uint8_t valid;
+	a_uint8_t port_id;
+	a_uint8_t cpri;
+	a_uint8_t cdrr_id;
+	a_uint8_t epri;
+	a_uint8_t edrr_id;
+} ssdk_dt_l1scheduler_cfg;
+
+typedef struct {
+	ssdk_dt_portscheduler_cfg pool[SSDK_MAX_PORT_NUM];
+	ssdk_dt_l0scheduler_cfg l0cfg[SSDK_L0SCHEDULER_CFG_MAX];
+	ssdk_dt_l1scheduler_cfg l1cfg[SSDK_L1SCHEDULER_CFG_MAX];
+} ssdk_dt_scheduler_cfg;
+
+typedef struct
+{
+	a_uint8_t port_id;
+	a_uint8_t phy_addr;
+	a_uint8_t port_duplex;
+	a_uint32_t port_speed;
+	phy_features_t phy_features;
+	struct mii_bus *miibus;
+} ssdk_port_phyinfo;
+
+typedef struct
+{
+	a_uint32_t switchreg_base_addr;
+	a_uint32_t switchreg_size;
+	a_uint32_t psgmiireg_base_addr;
+	a_uint32_t psgmiireg_size;
+	a_uint8_t *reg_access_mode;
+	a_uint8_t *psgmii_reg_access_str;
+	hsl_reg_mode switch_reg_access_mode;
+	hsl_reg_mode psgmii_reg_access_mode;
+	struct clk *ess_clk;
+	struct clk *cmnblk_clk;
+	ssdk_port_cfg   port_cfg;
+	a_uint32_t phyinfo_num;
+	ssdk_port_phyinfo *port_phyinfo;
+	a_uint32_t      mac_mode;
+	a_uint32_t      mac_mode1;
+	a_uint32_t      mac_mode2;
+	a_uint32_t uniphyreg_base_addr;
+	a_uint32_t uniphyreg_size;
+	a_uint8_t *uniphy_access_mode;
+	hsl_reg_mode uniphy_reg_access_mode;
+	ssdk_dt_scheduler_cfg scheduler_cfg;
+	a_uint8_t bm_tick_mode;
+	a_uint8_t tm_tick_mode;
+	a_bool_t ess_switch_flag;
+	a_uint32_t device_id;
+	struct device_node *of_node;
+	a_bool_t is_emulation;
+	a_uint32_t emu_chip_ver; /*only valid when is_emulation is true*/
+} ssdk_dt_cfg;
+
+#define SSDK_MAX_NR_ETH 6
+#define SSDK_PHY_RESET_GPIO_INDEX 0
+
+typedef struct
+{
+	a_uint32_t num_devices;
+	ssdk_dt_cfg **ssdk_dt_switch_nodes;
+	a_uint32_t num_intf_mac;
+	fal_mac_addr_t intf_mac[SSDK_MAX_NR_ETH];
+} ssdk_dt_global_t;
+
+typedef struct
+{
+	a_uint32_t base_addr;
+	a_uint32_t size;
+} ssdk_reg_map_info;
+
+/* DTS info for get */
+#ifdef HPPE
+#ifdef IN_QOS
+a_uint8_t ssdk_tm_tick_mode_get(a_uint32_t dev_id);
+ssdk_dt_scheduler_cfg* ssdk_bootup_shceduler_cfg_get(a_uint32_t dev_id);
+#endif
+#endif
+#ifdef IN_BM
+a_uint8_t ssdk_bm_tick_mode_get(a_uint32_t dev_id);
+#endif
+#ifdef IN_QM
+a_uint16_t ssdk_ucast_queue_start_get(a_uint32_t dev_id, a_uint32_t port);
+#endif
+a_uint32_t ssdk_intf_mac_num_get(void);
+a_uint8_t* ssdk_intf_macaddr_get(a_uint32_t index);
+a_uint32_t ssdk_dt_global_get_mac_mode(a_uint32_t dev_id, a_uint32_t index);
+a_uint32_t ssdk_dt_global_set_mac_mode(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode);
+a_uint32_t ssdk_cpu_bmp_get(a_uint32_t dev_id);
+a_uint32_t ssdk_lan_bmp_get(a_uint32_t dev_id);
+a_uint32_t ssdk_wan_bmp_get(a_uint32_t dev_id);
+sw_error_t ssdk_lan_bmp_set(a_uint32_t dev_id, a_uint32_t lan_bmp);
+sw_error_t ssdk_wan_bmp_set(a_uint32_t dev_id, a_uint32_t wan_bmp);
+a_uint32_t ssdk_inner_bmp_get(a_uint32_t dev_id);
+ssdk_port_phyinfo* ssdk_port_phyinfo_get(a_uint32_t dev_id, a_uint32_t port_id);
+a_bool_t ssdk_port_feature_get(a_uint32_t dev_id, a_uint32_t port_id, phy_features_t feature);
+a_uint32_t ssdk_port_force_speed_get(a_uint32_t dev_id, a_uint32_t port_id);
+struct mii_bus *
+ssdk_dts_miibus_get(a_uint32_t dev_id, a_uint32_t phy_addr);
+hsl_reg_mode ssdk_switch_reg_access_mode_get(a_uint32_t dev_id);
+void ssdk_switch_reg_map_info_get(a_uint32_t dev_id, ssdk_reg_map_info *info);
+#ifdef DESS
+hsl_reg_mode ssdk_psgmii_reg_access_mode_get(a_uint32_t dev_id);
+void ssdk_psgmii_reg_map_info_get(a_uint32_t dev_id, ssdk_reg_map_info *info);
+#endif
+#ifdef IN_UNIPHY
+hsl_reg_mode ssdk_uniphy_reg_access_mode_get(a_uint32_t dev_id);
+void ssdk_uniphy_reg_map_info_get(a_uint32_t dev_id, ssdk_reg_map_info *info);
+#endif
+a_bool_t ssdk_ess_switch_flag_get(a_uint32_t dev_id);
+a_uint32_t ssdk_device_id_get(a_uint32_t index);
+struct device_node *ssdk_dts_node_get(a_uint32_t dev_id);
+struct clk *ssdk_dts_essclk_get(a_uint32_t dev_id);
+struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id);
+
+int ssdk_switch_device_num_init(void);
+void ssdk_switch_device_num_exit(void);
+a_uint32_t ssdk_switch_device_num_get(void);
+a_bool_t ssdk_is_emulation(a_uint32_t dev_id);
+a_uint32_t ssdk_emu_chip_ver_get(a_uint32_t dev_id);
+
+#ifndef BOARD_AR71XX
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+sw_error_t ssdk_dt_parse(ssdk_init_cfg *cfg, a_uint32_t num, a_uint32_t *dev_id);
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SSDK_DTS_H */
diff --git a/qca-ssdk/include/init/ssdk_hppe.h b/qca-ssdk/include/init/ssdk_hppe.h
new file mode 100755
index 0000000..6e8c68c
--- /dev/null
+++ b/qca-ssdk/include/init/ssdk_hppe.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _SSDK_HPPE_H_
+#define _SSDK_HPPE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+sw_error_t qca_hppe_hw_init(ssdk_init_cfg *cfg, a_uint32_t dev_id);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SSDK_HPPE_H */
+
diff --git a/qca-ssdk/include/init/ssdk_init.h b/qca-ssdk/include/init/ssdk_init.h
new file mode 100755
index 0000000..e09d4a4
--- /dev/null
+++ b/qca-ssdk/include/init/ssdk_init.h
@@ -0,0 +1,392 @@
+/*
+ * Copyright (c) 2012, 2015-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/*qca808x_start*/
+#ifndef _SSDK_INIT_H_
+#define _SSDK_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+#include "fal_type.h"
+/*qca808x_end*/
+#include "fal/fal_led.h"
+/*qca808x_start*/
+#define SSDK_MAX_PORT_NUM               8
+/*qca808x_end*/
+#define SSDK_MAX_VIRTUAL_PORT_NUM       256
+#define SSDK_MAX_SERVICE_CODE_NUM       256
+#define SSDK_MAX_CPU_CODE_NUM           256
+#define SSDK_L0SCHEDULER_CFG_MAX        300
+#define SSDK_L0SCHEDULER_UCASTQ_CFG_MAX 256
+#define SSDK_L1SCHEDULER_CFG_MAX        64
+#define SSDK_SP_MAX_PRIORITY            8
+#define SSDK_MAX_FRAME_SIZE             0x3000
+
+#define PORT_GMAC_TYPE                  1
+#define PORT_XGMAC_TYPE                 2
+#define PORT_LINK_UP                    1
+#define PORT_LINK_DOWN                  0
+
+/*qca808x_start*/
+    typedef enum {
+        HSL_MDIO = 1,
+        HSL_HEADER,
+    }
+    hsl_access_mode;
+
+    typedef enum
+    {
+        HSL_NO_CPU = 0,
+        HSL_CPU_1,
+        HSL_CPU_2,
+        HSL_CPU_1_PLUS,
+    } hsl_init_mode;
+
+    typedef enum
+    {
+        HSL_REG_MDIO = 0,
+        HSL_REG_LOCAL_BUS,
+    } hsl_reg_mode;
+
+    typedef sw_error_t
+    (*mdio_reg_set) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
+                     a_uint16_t data);
+
+    typedef sw_error_t
+    (*mdio_reg_get) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
+                     a_uint16_t * data);
+
+    typedef sw_error_t
+    (*i2c_reg_set) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
+                     a_uint16_t data);
+
+    typedef sw_error_t
+    (*i2c_reg_get) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
+                     a_uint16_t * data);
+/*qca808x_end*/
+
+    typedef sw_error_t
+    (*hdr_reg_set) (a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len);
+
+    typedef sw_error_t
+    (*hdr_reg_get) (a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len);
+
+    typedef sw_error_t
+    (*psgmii_reg_set) (a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len);
+
+    typedef sw_error_t
+    (*psgmii_reg_get) (a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len);
+
+	typedef sw_error_t
+	(*uniphy_reg_set) (a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len);
+
+	typedef sw_error_t
+	(*uniphy_reg_get) (a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len);
+
+	typedef void (*mii_reg_set)(a_uint32_t dev_id, a_uint32_t reg, a_uint32_t val);
+
+	typedef a_uint32_t (*mii_reg_get)(a_uint32_t dev_id, a_uint32_t reg);
+/*qca808x_start*/
+enum ssdk_port_wrapper_cfg {
+	PORT_WRAPPER_PSGMII = 0,
+	PORT_WRAPPER_PSGMII_RGMII5,
+	PORT_WRAPPER_SGMII0_RGMII5,
+	PORT_WRAPPER_SGMII1_RGMII5,
+	PORT_WRAPPER_PSGMII_RMII0,
+	PORT_WRAPPER_PSGMII_RMII1,
+	PORT_WRAPPER_PSGMII_RMII0_RMII1,
+	PORT_WRAPPER_PSGMII_RGMII4,
+	PORT_WRAPPER_SGMII0_RGMII4,
+	PORT_WRAPPER_SGMII1_RGMII4,
+	PORT_WRAPPER_SGMII4_RGMII4,
+	PORT_WRAPPER_QSGMII,
+	PORT_WRAPPER_SGMII_PLUS,
+	PORT_WRAPPER_USXGMII,
+	PORT_WRAPPER_10GBASE_R,
+	PORT_WRAPPER_SGMII_CHANNEL0,
+	PORT_WRAPPER_SGMII_CHANNEL1,
+	PORT_WRAPPER_SGMII_CHANNEL4,
+	PORT_WRAPPER_RGMII,
+	PORT_WRAPPER_PSGMII_FIBER,
+	PORT_WRAPPER_SGMII_FIBER,
+	PORT_WRAPPER_MAX = 0xFF
+};
+
+    typedef struct
+    {
+        mdio_reg_set    mdio_set;
+        mdio_reg_get    mdio_get;
+/*qca808x_end*/
+        hdr_reg_set     header_reg_set;
+        hdr_reg_get     header_reg_get;
+        psgmii_reg_set     psgmii_reg_set;
+        psgmii_reg_get     psgmii_reg_get;
+        uniphy_reg_set     uniphy_reg_set;
+        uniphy_reg_get     uniphy_reg_get;
+	mii_reg_set	mii_reg_set;
+	mii_reg_get	mii_reg_get;
+/*qca808x_start*/
+        i2c_reg_set    i2c_set;
+        i2c_reg_get    i2c_get;
+    } hsl_reg_func;
+/*qca808x_end*/
+    typedef struct
+    {
+        a_bool_t  mac0_rgmii;
+        a_bool_t  mac5_rgmii;
+        a_bool_t  rx_delay_s0;
+        a_bool_t  rx_delay_s1;
+        a_bool_t  tx_delay_s0;
+        a_bool_t  tx_delay_s1;
+        a_bool_t  rgmii_rxclk_delay;
+        a_bool_t  rgmii_txclk_delay;
+        a_bool_t  phy4_rx_delay;
+        a_bool_t  phy4_tx_delay;
+    } garuda_init_spec_cfg;
+/*qca808x_start*/
+    typedef enum
+    {
+        CHIP_UNSPECIFIED = 0,
+        CHIP_ATHENA,
+        CHIP_GARUDA,
+        CHIP_SHIVA,
+        CHIP_HORUS,
+        CHIP_ISIS,
+        CHIP_ISISC,
+        CHIP_DESS,
+        CHIP_HPPE,
+	CHIP_SCOMPHY,
+    } ssdk_chip_type;
+/*qca808x_end*/
+	typedef struct
+	{
+		a_uint32_t cpu_bmp;
+		a_uint32_t lan_bmp;
+		a_uint32_t wan_bmp;
+		a_uint32_t inner_bmp;
+	} ssdk_port_cfg;
+
+	typedef struct
+	{
+		a_uint32_t led_num;
+		a_uint32_t led_source_id;
+		led_ctrl_pattern_t led_pattern;
+
+	} led_source_cfg_t;
+
+enum {
+	QCA_PHY_F_CLAUSE45_BIT,
+	QCA_PHY_F_COMBO_BIT,
+	QCA_PHY_F_QGMAC_BIT,
+	QCA_PHY_F_XGMAC_BIT,
+	QCA_PHY_F_I2C_BIT,
+	QCA_PHY_F_INIT_BIT,
+	QCA_PHY_F_FORCE_BIT,
+	QCA_PHY_F_SFP_BIT,
+	QCA_PHY_FEATURE_MAX
+};
+/*qca808x_start*/
+#define phy_features_t     a_uint16_t
+#define __PHY_F_BIT(bit)    ((phy_features_t)1 << (bit))
+#define _PHY_F(name)       __PHY_F_BIT(QCA_PHY_F_##name##_BIT)
+
+#define PHY_F_CLAUSE45     _PHY_F(CLAUSE45)
+#define PHY_F_COMBO        _PHY_F(COMBO)
+#define PHY_F_QGMAC        _PHY_F(QGMAC)
+#define PHY_F_XGMAC        _PHY_F(XGMAC)
+#define PHY_F_I2C          _PHY_F(I2C)
+#define PHY_F_INIT         _PHY_F(INIT)
+#define PHY_F_FORCE        _PHY_F(FORCE)
+#define PHY_F_SFP          _PHY_F(SFP)
+
+typedef struct
+{
+	hsl_init_mode   cpu_mode;
+	hsl_access_mode reg_mode;
+	hsl_reg_func    reg_func;
+
+	ssdk_chip_type  chip_type;
+	a_uint32_t      chip_revision;
+
+	/* os specific parameter */
+	/* when uk_if based on netlink, it's netlink protocol type*/
+	/* when uk_if based on ioctl, it's minor device number, major number
+	is always 10(misc device) */
+	a_uint32_t      nl_prot;
+
+	/* chip specific parameter */
+	void *          chip_spec_cfg;
+/*qca808x_end*/
+	/* port cfg */
+	ssdk_port_cfg   port_cfg;
+	a_uint32_t      mac_mode;
+	a_uint32_t led_source_num;
+	led_source_cfg_t led_source_cfg[15];
+/*qca808x_start*/
+	a_uint32_t      phy_id;
+	a_uint32_t      mac_mode1;
+	a_uint32_t      mac_mode2;
+} ssdk_init_cfg;
+/*qca808x_end*/
+
+#if defined ATHENA
+#define def_init_cfg  {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2};
+#elif defined GARUDA
+
+#define def_init_cfg_cpu2  {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2,};
+
+#define def_init_spec_cfg_cpu2 {.mac0_rgmii = A_TRUE, .mac5_rgmii = A_TRUE, \
+                    .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \
+                    .tx_delay_s0 = A_TRUE,  .tx_delay_s1 = A_FALSE,\
+                    .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE,\
+                    .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,}
+
+#define def_init_cfg_cpu1  {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_1,};
+
+#define def_init_spec_cfg_cpu1 {.mac0_rgmii = A_TRUE, .mac5_rgmii = A_FALSE, \
+                    .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \
+                    .tx_delay_s0 = A_TRUE,  .tx_delay_s1 = A_FALSE,\
+                    .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \
+                    .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,}
+
+#define def_init_cfg_cpu1plus  {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_1_PLUS,};
+
+#define def_init_spec_cfg_cpu1plus {.mac0_rgmii = A_TRUE, .mac5_rgmii = A_FALSE, \
+                    .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \
+                    .tx_delay_s0 = A_FALSE,  .tx_delay_s1 = A_FALSE,\
+                    .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \
+                    .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,}
+
+#define def_init_cfg_nocpu  {.reg_mode = HSL_MDIO, .cpu_mode = HSL_NO_CPU,};
+
+#define def_init_spec_cfg_nocpu { .mac0_rgmii = A_FALSE, .mac5_rgmii = A_FALSE, \
+                    .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \
+                    .tx_delay_s0 = A_FALSE,  .tx_delay_s1 = A_FALSE,\
+                    .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \
+                    .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,}
+
+#define def_init_cfg_cpu1_gmii  {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_1,};
+
+#define def_init_spec_cfg_cpu1_gmii {.mac0_rgmii = A_FALSE, .mac5_rgmii = A_FALSE, \
+                    .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \
+                    .tx_delay_s0 = A_TRUE,  .tx_delay_s1 = A_FALSE,\
+                    .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \
+                    .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,}
+
+#define def_init_cfg def_init_cfg_cpu2
+#define def_init_spec_cfg def_init_spec_cfg_cpu2
+
+#elif defined SHIVA
+#define def_init_cfg  {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2};
+#elif defined HORUS
+#define def_init_cfg  {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2};
+#elif defined ISIS
+#define def_init_cfg  {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2};
+#elif defined ISISC
+#define def_init_cfg  {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2};
+#endif
+
+    typedef struct
+    {
+        a_bool_t in_acl;
+        a_bool_t in_fdb;
+        a_bool_t in_igmp;
+        a_bool_t in_leaky;
+        a_bool_t in_led;
+        a_bool_t in_mib;
+        a_bool_t in_mirror;
+        a_bool_t in_misc;
+        a_bool_t in_portcontrol;
+        a_bool_t in_portvlan;
+        a_bool_t in_qos;
+        a_bool_t in_rate;
+        a_bool_t in_stp;
+        a_bool_t in_vlan;
+        a_bool_t in_reduced_acl;
+        a_bool_t in_ip;
+        a_bool_t in_nat;
+        a_bool_t in_cosmap;
+        a_bool_t in_sec;
+        a_bool_t in_trunk;
+        a_bool_t in_nathelper;
+        a_bool_t in_interfacectrl;
+    } ssdk_features;
+/*qca808x_start*/
+#define CFG_STR_SIZE 20
+    typedef struct
+    {
+        a_uint8_t build_ver[CFG_STR_SIZE];
+        a_uint8_t build_date[CFG_STR_SIZE];
+
+        a_uint8_t chip_type[CFG_STR_SIZE]; //GARUDA
+        a_uint8_t cpu_type[CFG_STR_SIZE];  //mips
+        a_uint8_t os_info[CFG_STR_SIZE];   //OS=linux OS_VER=2_6
+
+        a_bool_t  fal_mod;
+        a_bool_t  kernel_mode;
+        a_bool_t  uk_if;
+/*qca808x_end*/
+        ssdk_features features;
+/*qca808x_start*/
+        ssdk_init_cfg init_cfg;
+    } ssdk_cfg_t;
+
+#define SSDK_RFS_INTF_MAX	8
+typedef struct
+{
+	a_uint32_t if_idx; /*netdevic idx*/
+	fal_mac_addr_t macaddr;
+	a_uint16_t vid;
+	a_uint8_t hw_idx; /* HW table entry idx*/
+} ssdk_rfs_intf_t;
+
+sw_error_t
+ssdk_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+/*qca808x_end*/
+sw_error_t
+ssdk_hsl_access_mode_set(a_uint32_t dev_id, hsl_access_mode reg_mode);
+
+a_uint32_t ssdk_dt_global_get_mac_mode(a_uint32_t dev_id, a_uint32_t index);
+a_uint32_t ssdk_dt_global_set_mac_mode(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode);
+
+a_uint32_t
+qca_hppe_port_mac_type_get(a_uint32_t dev_id, a_uint32_t port_id);
+a_uint32_t
+qca_hppe_port_mac_type_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t port_type);
+
+void ssdk_portvlan_init(a_uint32_t dev_id);
+sw_error_t ssdk_dess_trunk_init(a_uint32_t dev_id, a_uint32_t wan_bitmap);
+
+void
+qca_mac_port_status_init(a_uint32_t dev_id, a_uint32_t port_id);
+void
+qca_mac_sw_sync_port_status_init(a_uint32_t dev_id);
+/*qca808x_start*/
+struct qca_phy_priv* ssdk_phy_priv_data_get(a_uint32_t dev_id);
+/*qca808x_end*/
+sw_error_t qca_switch_init(a_uint32_t dev_id);
+void qca_mac_sw_sync_work_stop(struct qca_phy_priv *priv);
+void qca_mac_sw_sync_work_resume(struct qca_phy_priv *priv);
+int qca_mac_sw_sync_work_start(struct qca_phy_priv *priv);
+/*qca808x_start*/
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _SSDK_INIT_H */
+/*qca808x_end*/
diff --git a/qca-ssdk/include/init/ssdk_interrupt.h b/qca-ssdk/include/init/ssdk_interrupt.h
new file mode 100755
index 0000000..fb5ed62
--- /dev/null
+++ b/qca-ssdk/include/init/ssdk_interrupt.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "ssdk_plat.h"
+
+#ifndef _SSDK_INTERRUPT_H_
+#define _SSDK_INTERRUPT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+int qca_mac_enable_intr(struct qca_phy_priv *priv);
+int qca_intr_init(struct qca_phy_priv *priv);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SSDK_INTERRUPT_H */
diff --git a/qca-ssdk/include/init/ssdk_led.h b/qca-ssdk/include/init/ssdk_led.h
new file mode 100644
index 0000000..748ea57
--- /dev/null
+++ b/qca-ssdk/include/init/ssdk_led.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2019,2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _SSDK_LED_H_
+#define _SSDK_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#define SRC_SELECTION_0           0x0
+#define SRC_SELECTION_1           0x1
+#define SRC_SELECTION_2           0x2
+#define LED_SRC_ID_1              0x1
+#define LED_SRC_ID_2              0x2
+#define LED_SRC_ID_3              0x3
+#define LED_SRC_ID_4              0x4
+#define LED_SRC_ID_5              0x5
+#define LED_SRC_ID_6              0x6
+#define LED_SRC_ID_7              0x7
+#define LED_SRC_ID_8              0x8
+#define LED_SRC_ID_9              0x9
+#define LED_SRC_ID_10             0xa
+#define LED_SRC_ID_11             0xb
+#define LED_SRC_ID_12             0xc
+#define LED_SRC_ID_13             0xd
+#define LED_SRC_ID_14             0xe
+#define LED_SRC_ID_15             0xf
+
+
+#ifdef DESS
+int ssdk_dess_led_init(ssdk_init_cfg *cfg);
+#endif
+
+#ifdef IN_LED
+sw_error_t ssdk_led_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+#endif
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SSDK_LED_H */
+
diff --git a/qca-ssdk/include/init/ssdk_mp.h b/qca-ssdk/include/init/ssdk_mp.h
new file mode 100644
index 0000000..90d6062
--- /dev/null
+++ b/qca-ssdk/include/init/ssdk_mp.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _SSDK_MP_H_
+#define _SSDK_MP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "sw.h"
+
+#define MP_LPI_WAKEUP_TIMER             0x46
+
+sw_error_t qca_mp_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SSDK_MP_H */
+
diff --git a/qca-ssdk/include/init/ssdk_phy_i2c.h b/qca-ssdk/include/init/ssdk_phy_i2c.h
new file mode 100755
index 0000000..e682c8a
--- /dev/null
+++ b/qca-ssdk/include/init/ssdk_phy_i2c.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _SSDK_PHY_I2C_H_
+#define _SSDK_PHY_I2C_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif				/* __cplusplus */
+
+#define QCA_PHY_I2C_MMD_OR_MII_SHIFT	6
+#define QCA_PHY_I2C_IS_MMD		1
+#define QCA_PHY_I2C_IS_MII		0
+#define QCA_PHY_I2C_MMD_ADDR_OR_DATA_SHIFT		5
+#define QCA_PHY_I2C_MMD_IS_ADDR		1
+#define QCA_PHY_I2C_MMD_IS_DATA		0
+
+#define QCA_PHY_MII_ADDR_C45  			(1<<30)
+#define QCA_PHY_MII_ADDR_C45_IS_MMD(reg_addr_c45) ((reg_addr_c45) & QCA_PHY_MII_ADDR_C45)
+#define QCA_PHY_MII_ADDR_C45_MMD_NUM(reg_addr_c45) (((reg_addr_c45) >> 16) & 0x1f)
+#define QCA_PHY_MII_ADDR_C45_REG_ADDR(reg_addr_c45) ((reg_addr_c45) & 0xffff)
+
+#define QCA_PHY_I2C_PHYCORE_DEVADDR		0x44
+#define QCA_PHY_I2C_SERDES_DEVADDR		0x45
+#define QCA_PHY_I2C_DEVADDR_MASK		0x47
+
+#define QCA_PHY_MMD1_NUM  1
+#define QCA_PHY_MMD3_NUM  3
+#define QCA_PHY_MMD7_NUM  7
+
+sw_error_t
+qca_phy_i2c_mii_read(a_uint32_t dev_id, a_uint32_t phy_addr,
+                          a_uint32_t reg_addr, a_uint16_t *reg_data);
+sw_error_t
+qca_phy_i2c_mii_write(a_uint32_t dev_id, a_uint32_t phy_addr,
+                           a_uint32_t reg_addr, a_uint16_t reg_data);
+sw_error_t
+qca_i2c_data_get(a_uint32_t dev_id, a_uint32_t i2c_slave,
+		a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count);
+
+sw_error_t
+qca_i2c_data_set(a_uint32_t dev_id, a_uint32_t i2c_slave,
+		a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count);
+
+#ifdef IN_PHY_I2C_MODE
+sw_error_t
+qca_phy_i2c_mmd_read(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint16_t mmd_num,
+                            a_uint32_t reg_addr, a_uint16_t *reg_data);
+sw_error_t
+qca_phy_i2c_mmd_write(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint16_t mmd_num,
+                            a_uint32_t reg_addr, a_uint16_t reg_data);
+a_bool_t
+qca_phy_is_i2c_addr(a_uint32_t phy_addr);
+sw_error_t
+qca_phy_i2c_read(a_uint32_t dev_id, a_uint32_t phy_addr,
+                           a_uint32_t reg_addr_c45, a_uint16_t *reg_data);
+sw_error_t
+qca_phy_i2c_write(a_uint32_t dev_id, a_uint32_t phy_addr,
+                            a_uint32_t reg_addr_c45, a_uint16_t reg_data);
+#endif
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* _SSDK_PHY_I2C_H_ */
diff --git a/qca-ssdk/include/init/ssdk_plat.h b/qca-ssdk/include/init/ssdk_plat.h
new file mode 100755
index 0000000..209e6ac
--- /dev/null
+++ b/qca-ssdk/include/init/ssdk_plat.h
@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2012, 2014-2015, 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+/*qca808x_start*/
+#ifndef __SSDK_PLAT_H
+#define __SSDK_PLAT_H
+
+#include "sw.h"
+/*qca808x_end*/
+#include <linux/kconfig.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#if defined(IN_SWCONFIG)
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#include <linux/switch.h>
+#else
+#include <net/switch.h>
+#endif
+#endif
+/*qca808x_start*/
+#include <linux/phy.h>
+
+#ifndef BIT
+#define BIT(_n)                                      (1UL << (_n))
+#endif
+
+
+#ifndef BITS
+#define BITS(_s, _n)                                 (((1UL << (_n)) - 1) << _s)
+#endif
+
+/* Atheros specific MII registers */
+#define QCA_MII_MMD_ADDR                             0x0d
+#define QCA_MII_MMD_DATA                             0x0e
+#define QCA_MII_DBG_ADDR                             0x1d
+#define QCA_MII_DBG_DATA                             0x1e
+/*qca808x_end*/
+#define AR8327_REG_CTRL                              0x0000
+#define   AR8327_CTRL_REVISION                       BITS(0, 8)
+#define   AR8327_CTRL_REVISION_S                     0
+#define   AR8327_CTRL_VERSION                        BITS(8, 8)
+#define   AR8327_CTRL_VERSION_S                      8
+#define   AR8327_CTRL_RESET                          BIT(31)
+
+#define AR8327_REG_LED_CTRL_0                        0x50
+#define AR8327_REG_LED_CTRL_1                        0x54
+#define AR8327_REG_LED_CTRL_2                        0x58
+#define AR8327_REG_LED_CTRL_3                        0x5c
+
+#define AR8327_REG_PORT_STATUS(_i)                   (0x07c + (_i) * 4)
+
+#define   AR8327_PORT_STATUS_SPEED                   BITS(0,2)
+#define   AR8327_PORT_STATUS_SPEED_S                 0
+#define   AR8327_PORT_STATUS_TXMAC                   BIT(2)
+#define   AR8327_PORT_STATUS_RXMAC                   BIT(3)
+#define   AR8327_PORT_STATUS_TXFLOW                  BIT(4)
+#define   AR8327_PORT_STATUS_RXFLOW                  BIT(5)
+#define   AR8327_PORT_STATUS_DUPLEX                  BIT(6)
+#define   AR8327_PORT_STATUS_LINK_UP                 BIT(8)
+#define   AR8327_PORT_STATUS_LINK_AUTO               BIT(9)
+#define   AR8327_PORT_STATUS_LINK_PAUSE              BIT(10)
+
+#define AR8327_REG_PAD0_CTRL                         0x4
+#define AR8327_REG_PAD5_CTRL                         0x8
+#define AR8327_REG_PAD6_CTRL                         0xc
+#define   AR8327_PAD_CTRL_MAC_MII_RXCLK_SEL          BIT(0)
+#define   AR8327_PAD_CTRL_MAC_MII_TXCLK_SEL          BIT(1)
+#define   AR8327_PAD_CTRL_MAC_MII_EN                 BIT(2)
+#define   AR8327_PAD_CTRL_MAC_GMII_RXCLK_SEL         BIT(4)
+#define   AR8327_PAD_CTRL_MAC_GMII_TXCLK_SEL         BIT(5)
+#define   AR8327_PAD_CTRL_MAC_GMII_EN                BIT(6)
+#define   AR8327_PAD_CTRL_SGMII_EN                   BIT(7)
+#define   AR8327_PAD_CTRL_PHY_MII_RXCLK_SEL          BIT(8)
+#define   AR8327_PAD_CTRL_PHY_MII_TXCLK_SEL          BIT(9)
+#define   AR8327_PAD_CTRL_PHY_MII_EN                 BIT(10)
+#define   AR8327_PAD_CTRL_PHY_GMII_PIPE_RXCLK_SEL    BIT(11)
+#define   AR8327_PAD_CTRL_PHY_GMII_RXCLK_SEL         BIT(12)
+#define   AR8327_PAD_CTRL_PHY_GMII_TXCLK_SEL         BIT(13)
+#define   AR8327_PAD_CTRL_PHY_GMII_EN                BIT(14)
+#define   AR8327_PAD_CTRL_PHYX_GMII_EN               BIT(16)
+#define   AR8327_PAD_CTRL_PHYX_RGMII_EN              BIT(17)
+#define   AR8327_PAD_CTRL_PHYX_MII_EN                BIT(18)
+#define   AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_SEL      BITS(20, 2)
+#define   AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_SEL_S    20
+#define   AR8327_PAD_CTRL_RGMII_TXCLK_DELAY_SEL      BITS(22, 2)
+#define   AR8327_PAD_CTRL_RGMII_TXCLK_DELAY_SEL_S    22
+#define   AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_EN       BIT(24)
+#define   AR8327_PAD_CTRL_RGMII_TXCLK_DELAY_EN       BIT(25)
+#define   AR8327_PAD_CTRL_RGMII_EN                   BIT(26)
+
+#define AR8327_PORT5_PHY_ADDR                        4
+/*AR8327 inner phy debug register for RGMII mode*/
+#define AR8327_PHY_REG_MODE_SEL                      0x12
+#define AR8327_PHY_RGMII_MODE                        BIT(3)
+#define AR8327_PHY_REG_TEST_CTRL                     0x0
+#define AR8327_PHY_RGMII_RX_DELAY                    BIT(15)
+#define AR8327_PHY_REG_SYS_CTRL                      0x5
+#define AR8327_PHY_RGMII_TX_DELAY                    BIT(8)
+
+
+#define AR8327_REG_POS                               0x10
+#define AR8327_REG_POS_HW_INIT                       0x261320
+#define   AR8327_POS_POWER_ON_SEL                    BIT(31)
+#define   AR8327_POS_LED_OPEN_EN                     BIT(24)
+#define   AR8327_POS_SERDES_AEN                      BIT(7)
+
+#define AR8327_REG_MODULE_EN                         0x30
+#define   AR8327_REG_MODULE_EN_QM_ERR                BIT(8)
+#define   AR8327_REG_MODULE_EN_LOOKUP_ERR            BIT(9)
+
+#define AR8327_REG_MAC_SFT_RST                       0x68
+
+#define AR8327_REG_PAD_SGMII_CTRL                    0xe0
+#define AR8327_REG_PAD_SGMII_CTRL_HW_INIT            0xc70164c0
+#define   AR8327_PAD_SGMII_CTRL_MODE_CTRL            BITS(22, 2)
+#define   AR8327_PAD_SGMII_CTRL_MODE_CTRL_S          22
+#define   AR8327_PAD_SGMII_CTRL_EN_SD                BIT(4)
+#define   AR8327_PAD_SGMII_CTRL_EN_TX                BIT(3)
+#define   AR8327_PAD_SGMII_CTRL_EN_RX                BIT(2)
+#define   AR8327_PAD_SGMII_CTRL_EN_PLL               BIT(1)
+#define   AR8327_PAD_SGMII_CTRL_EN_LCKDT             BIT(0)
+
+#define AR8327_REG_PAD_MAC_PWR_SEL                   0x0e4
+#define   AR8327_PAD_MAC_PWR_RGMII0_1_8V             BIT(18)
+#define   AR8327_PAD_MAC_PWR_RGMII1_1_8V             BIT(19)
+
+#define AR8327_REG_PORT_LOOKUP(_i)                   (0x660 + (_i) * 0xc)
+#define AR8327_REG_PORT_VLAN0(_i)                    (0x420 + (_i) * 0x8)
+
+#define DESS_PSGMII_MODE_CONTROL                     0x1b4
+#define   DESS_PSGMII_ATHR_CSCO_MODE_25M             BIT(0)
+
+#define DESS_PSGMIIPHY_TX_CONTROL                    0x288
+
+#define DESS_PSGMII_PLL_VCO_RELATED_CONTROL_1        0x78c
+#define   DESS_PSGMII_MII_REG_UPHY_PLL_LCKDT_EN      BIT(0)
+
+#define DESS_PSGMII_VCO_CALIBRATION_CONTROL_1        0x9c
+
+#define SSDK_PSGMII_ID                               5
+/*qca808x_start*/
+#define SSDK_PHY_BCAST_ID                            0x1f
+#define SSDK_PHY_MIN_ID                              0x0
+#define SSDK_PORT_CPU                                0
+/*qca808x_end*/
+#define SSDK_PORT0_FC_THRESH_ON_DFLT                 0x60
+#define SSDK_PORT0_FC_THRESH_OFF_DFLT                0x90
+
+#define AR8327_NUM_PHYS                              5
+#define AR8327_PORT_CPU                              0
+#define AR8327_NUM_PORTS                             7
+#define AR8327_MAX_VLANS                             128
+
+#define MII_PHYADDR_C45                              (1<<30)
+
+#define SSDK_GPIO_RESET                              0
+#define SSDK_GPIO_RELEASE                            1
+#define SSDK_INVALID_GPIO                            0
+
+enum {
+    AR8327_PORT_SPEED_10M = 0,
+    AR8327_PORT_SPEED_100M = 1,
+    AR8327_PORT_SPEED_1000M = 2,
+    AR8327_PORT_SPEED_NONE = 3,
+};
+/*qca808x_start*/
+enum {
+	QCA_VER_AR8216 = 0x01,
+	QCA_VER_AR8227 = 0x02,
+	QCA_VER_AR8236 = 0x03,
+	QCA_VER_AR8316 = 0x10,
+	QCA_VER_AR8327 = 0x12,
+	QCA_VER_AR8337 = 0x13,
+	QCA_VER_DESS = 0x14,
+	QCA_VER_HPPE = 0x15,
+	QCA_VER_SCOMPHY = 0xEE
+};
+/*qca808x_end*/
+/*poll mib per 120secs*/
+#define QCA_PHY_MIB_WORK_DELAY	120000
+#define QCA_MIB_ITEM_NUMBER \
+	(sizeof(fal_mib_counter_t)/sizeof(a_uint64_t))
+
+#define SSDK_MAX_UNIPHY_INSTANCE        3
+#define SSDK_UNIPHY_INSTANCE0           0
+#define SSDK_UNIPHY_INSTANCE1           1
+#define SSDK_UNIPHY_INSTANCE2           2
+#define SSDK_UNIPHY_CHANNEL0            0
+#define SSDK_UNIPHY_CHANNEL1            1
+#define SSDK_UNIPHY_CHANNEL2            2
+#define SSDK_UNIPHY_CHANNEL3            3
+#define SSDK_UNIPHY_CHANNEL4            4
+
+/*qca808x_start*/
+#define SSDK_PHYSICAL_PORT0             0
+#define SSDK_PHYSICAL_PORT1             1
+#define SSDK_PHYSICAL_PORT2             2
+#define SSDK_PHYSICAL_PORT3             3
+#define SSDK_PHYSICAL_PORT4             4
+#define SSDK_PHYSICAL_PORT5             5
+#define SSDK_PHYSICAL_PORT6             6
+#define SSDK_PHYSICAL_PORT7             7
+/*qca808x_end*/
+#define SSDK_GLOBAL_INT0_ACL_INI_INT        (1<<29)
+#define SSDK_GLOBAL_INT0_LOOKUP_INI_INT     (1<<28)
+#define SSDK_GLOBAL_INT0_QM_INI_INT         (1<<27)
+#define SSDK_GLOBAL_INT0_MIB_INI_INT        (1<<26)
+#define SSDK_GLOBAL_INT0_OFFLOAD_INI_INT    (1<<25)
+#define SSDK_GLOBAL_INT0_HARDWARE_INI_DONE  (1<<24)
+
+#define SSDK_GLOBAL_INITIALIZED_STATUS 				\
+			(					\
+			SSDK_GLOBAL_INT0_ACL_INI_INT | 		\
+			SSDK_GLOBAL_INT0_LOOKUP_INI_INT | 	\
+			SSDK_GLOBAL_INT0_QM_INI_INT | 		\
+			SSDK_GLOBAL_INT0_MIB_INI_INT | 		\
+			SSDK_GLOBAL_INT0_OFFLOAD_INI_INT |	\
+			SSDK_GLOBAL_INT0_HARDWARE_INI_DONE	\
+			)
+/*qca808x_start*/
+#define SSDK_LOG_LEVEL_ERROR    0
+#define SSDK_LOG_LEVEL_WARN     1
+#define SSDK_LOG_LEVEL_INFO     2
+#define SSDK_LOG_LEVEL_DEBUG    3
+#define SSDK_LOG_LEVEL_DEFAULT  SSDK_LOG_LEVEL_INFO
+
+extern a_uint32_t ssdk_log_level;
+
+#define __SSDK_LOG_FUN(lev, fmt, ...) \
+	do { \
+		if (SSDK_LOG_LEVEL_##lev <= ssdk_log_level) { \
+			printk("%s[%u]:"#lev":"fmt, \
+				 __FUNCTION__, __LINE__, ##__VA_ARGS__); \
+		} \
+	} while(0)
+#define SSDK_DUMP_BUF(lev, buf, len) \
+	do {\
+		if (SSDK_LOG_LEVEL_##lev <= ssdk_log_level) {\
+			a_uint32_t i_buf = 0;\
+			for(i_buf=0; i_buf<(len); i_buf++) {\
+				printk(KERN_CONT "%08lx ", *((buf)+i_buf));\
+			}\
+			printk(KERN_CONT "\n");\
+		}\
+	} while(0)
+
+#define SSDK_ERROR(fmt, ...) __SSDK_LOG_FUN(ERROR, fmt, ##__VA_ARGS__)
+#define SSDK_WARN(fmt, ...)  __SSDK_LOG_FUN(WARN, fmt, ##__VA_ARGS__)
+#define SSDK_INFO(fmt, ...)  __SSDK_LOG_FUN(INFO, fmt, ##__VA_ARGS__)
+#define SSDK_DEBUG(fmt, ...) __SSDK_LOG_FUN(DEBUG, fmt, ##__VA_ARGS__)
+
+struct qca_phy_priv {
+	struct phy_device *phy;
+#if defined(IN_SWCONFIG)
+	struct switch_dev sw_dev;
+#endif
+    a_uint8_t version;
+	a_uint8_t revision;
+	a_uint32_t (*mii_read)(a_uint32_t dev_id, a_uint32_t reg);
+	void (*mii_write)(a_uint32_t dev_id, a_uint32_t reg, a_uint32_t val);
+    void (*phy_dbg_write)(a_uint32_t dev_id, a_uint32_t phy_addr,
+                        a_uint16_t dbg_addr, a_uint16_t dbg_data);
+	void (*phy_dbg_read)(a_uint32_t dev_id, a_uint32_t phy_addr,
+                        a_uint16_t dbg_addr, a_uint16_t *dbg_data);
+    void (*phy_mmd_write)(a_uint32_t dev_id, a_uint32_t phy_addr,
+                          a_uint16_t addr, a_uint16_t data);
+    sw_error_t (*phy_write)(a_uint32_t dev_id, a_uint32_t phy_addr,
+                            a_uint32_t reg, a_uint16_t data);
+    sw_error_t (*phy_read)(a_uint32_t dev_id, a_uint32_t phy_addr,
+                           a_uint32_t reg, a_uint16_t* data);
+
+	bool init;
+/*qca808x_end*/
+	a_bool_t qca_ssdk_sw_dev_registered;
+	a_bool_t ess_switch_flag;
+	struct mutex reg_mutex;
+	struct mutex mib_lock;
+	struct delayed_work mib_dwork;
+	/*qm_err_check*/
+	struct mutex 	qm_lock;
+	a_uint32_t port_link_down[SW_MAX_NR_PORT];
+	a_uint32_t port_link_up[SW_MAX_NR_PORT];
+	a_uint32_t port_old_link[SW_MAX_NR_PORT];
+	a_uint32_t port_old_speed[SW_MAX_NR_PORT];
+	a_uint32_t port_old_duplex[SW_MAX_NR_PORT];
+	a_uint32_t port_old_phy_status[SW_MAX_NR_PORT];
+	a_uint32_t port_qm_buf[SW_MAX_NR_PORT];
+	a_bool_t port_old_tx_flowctrl[SW_MAX_NR_PORT];
+	a_bool_t port_old_rx_flowctrl[SW_MAX_NR_PORT];
+	a_bool_t port_tx_flowctrl_forcemode[SW_MAX_NR_PORT];
+	a_bool_t port_rx_flowctrl_forcemode[SW_MAX_NR_PORT];
+	struct delayed_work qm_dwork_polling;
+	struct work_struct	 intr_workqueue;
+	/*qm_err_check end*/
+/*qca808x_start*/
+	a_uint8_t device_id;
+	struct device_node *of_node;
+/*qca808x_end*/
+	/*dess_rgmii_mac*/
+	struct mutex rgmii_lock;
+	struct delayed_work rgmii_dwork;
+	/*dess_rgmii_mac end*/
+	/*hppe_mac_sw_sync*/
+	struct mutex mac_sw_sync_lock;
+	struct delayed_work mac_sw_sync_dwork;
+	/*hppe_mac_sw_sync end*/
+/*qca808x_start*/
+	struct mii_bus *miibus;
+/*qca808x_end*/
+	u64 *mib_counters;
+	/* dump buf */
+	a_uint8_t  buf[2048];
+	a_uint32_t link_polling_required;
+	/* it is valid only when link_polling_required is false*/
+	a_uint32_t link_interrupt_no;
+	a_uint32_t interrupt_flag;
+	char link_intr_name[IFNAMSIZ];
+	/* VLAN database */
+	bool       vlan;  /* True: 1q vlan mode, False: port vlan mode */
+	a_uint16_t vlan_id[AR8327_MAX_VLANS];
+	a_uint8_t  vlan_table[AR8327_MAX_VLANS];
+	a_uint8_t  vlan_tagged[AR8327_MAX_VLANS];
+	a_uint16_t pvid[SSDK_MAX_PORT_NUM];
+	a_uint32_t ports;
+	u8 __iomem *hw_addr;
+	u8 __iomem *psgmii_hw_addr;
+	u8 __iomem *uniphy_hw_addr;
+/*qca808x_start*/
+};
+
+struct ipq40xx_mdio_data {
+        struct mii_bus          *mii_bus;
+        void __iomem            *membase;
+        int phy_irq[PHY_MAX_ADDR];
+};
+
+#if defined(IN_SWCONFIG)
+#define qca_phy_priv_get(_dev) \
+		container_of(_dev, struct qca_phy_priv, sw_dev)
+#endif
+
+/*qca808x_end*/
+a_uint32_t
+qca_ar8216_mii_read(a_uint32_t dev_id, a_uint32_t reg);
+void
+qca_ar8216_mii_write(a_uint32_t dev_id, a_uint32_t reg, a_uint32_t val);
+/*qca808x_start*/
+sw_error_t
+qca_ar8327_phy_read(a_uint32_t dev_id, a_uint32_t phy_addr,
+			a_uint32_t reg, a_uint16_t* data);
+sw_error_t
+qca_ar8327_phy_write(a_uint32_t dev_id, a_uint32_t phy_addr,
+                            a_uint32_t reg, a_uint16_t data);
+void
+qca_ar8327_mmd_write(a_uint32_t dev_id, a_uint32_t phy_addr,
+                              a_uint16_t addr, a_uint16_t data);
+void
+qca_ar8327_phy_dbg_write(a_uint32_t dev_id, a_uint32_t phy_addr,
+		                          a_uint16_t dbg_addr, a_uint16_t dbg_data);
+void
+qca_ar8327_phy_dbg_read(a_uint32_t dev_id, a_uint32_t phy_addr,
+		                          a_uint16_t dbg_addr, a_uint16_t *dbg_data);
+
+void
+qca_phy_mmd_write(u32 dev_id, u32 phy_id,
+                     u16 mmd_num, u16 reg_id, u16 reg_val);
+
+u16
+qca_phy_mmd_read(u32 dev_id, u32 phy_id,
+		u16 mmd_num, u16 reg_id);
+/*qca808x_end*/
+sw_error_t
+qca_switch_reg_read(a_uint32_t dev_id, a_uint32_t reg_addr,
+			a_uint8_t * reg_data, a_uint32_t len);
+
+sw_error_t
+qca_switch_reg_write(a_uint32_t dev_id, a_uint32_t reg_addr,
+			a_uint8_t * reg_data, a_uint32_t len);
+
+sw_error_t
+qca_psgmii_reg_read(a_uint32_t dev_id, a_uint32_t reg_addr,
+			a_uint8_t * reg_data, a_uint32_t len);
+
+sw_error_t
+qca_psgmii_reg_write(a_uint32_t dev_id, a_uint32_t reg_addr,
+			a_uint8_t * reg_data, a_uint32_t len);
+
+sw_error_t
+qca_uniphy_reg_write(a_uint32_t dev_id, a_uint32_t uniphy_index,
+				a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len);
+
+sw_error_t
+qca_uniphy_reg_read(a_uint32_t dev_id, a_uint32_t uniphy_index,
+				a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len);
+
+struct mii_bus *ssdk_miibus_get_by_device(a_uint32_t dev_id);
+
+int ssdk_sysfs_init (void);
+void ssdk_sysfs_exit (void);
+/*qca808x_start*/
+int ssdk_plat_init(ssdk_init_cfg *cfg, a_uint32_t dev_id);
+void ssdk_plat_exit(a_uint32_t dev_id);
+
+#endif
+/*qca808x_end*/
diff --git a/qca-ssdk/include/init/ssdk_scomphy.h b/qca-ssdk/include/init/ssdk_scomphy.h
new file mode 100755
index 0000000..45ef0ff
--- /dev/null
+++ b/qca-ssdk/include/init/ssdk_scomphy.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _SSDK_SCOMPHY_H_
+#define _SSDK_SCOMPHY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include "ssdk_init.h"
+
+sw_error_t qca_scomphy_hw_init(ssdk_init_cfg *cfg, a_uint32_t dev_id);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SSDK_SCOMPY_H */
+
diff --git a/qca-ssdk/include/init/ssdk_uci.h b/qca-ssdk/include/init/ssdk_uci.h
new file mode 100755
index 0000000..52cc0a9
--- /dev/null
+++ b/qca-ssdk/include/init/ssdk_uci.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _SSDK_UCI_H_
+#define _SSDK_UCI_H_
+
+#ifdef BOARD_AR71XX
+int ssdk_uci_takeover_init(void);
+void ssdk_uci_takeover_exit(void);
+int ssdk_uci_sw_set_vlan(const struct switch_attr *attr,
+                       struct switch_val *val);
+int ssdk_uci_sw_set_vid(const struct switch_attr *attr,
+                       struct switch_val *val);
+int ssdk_uci_sw_set_pvid(int port, int vlan);
+int ssdk_uci_sw_set_ports(struct switch_val *val);
+
+
+#endif
+
+#endif
diff --git a/qca-ssdk/include/ref/ref_api.h b/qca-ssdk/include/ref/ref_api.h
new file mode 100755
index 0000000..ec3d937
--- /dev/null
+++ b/qca-ssdk/include/ref/ref_api.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REF_API_H_
+#define _REF_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#if defined(IN_VLAN) && !defined(IN_VLAN_MINI)
+#define REF_VLAN_API \
+    SW_API_DEF(SW_API_LAN_WAN_CFG_SET, qca_lan_wan_cfg_set), \
+    SW_API_DEF(SW_API_LAN_WAN_CFG_GET, qca_lan_wan_cfg_get),
+
+#define REF_VLAN_API_PARAM \
+    SW_API_DESC(SW_API_LAN_WAN_CFG_SET) \
+    SW_API_DESC(SW_API_LAN_WAN_CFG_GET)
+
+#else
+#define REF_VLAN_API
+#define REF_VLAN_API_PARAM
+#endif
+
+#define SSDK_REF_API \
+    REF_VLAN_API
+
+#define SSDK_REF_PARAM  \
+    REF_VLAN_API_PARAM
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _REF_API_H_ */
diff --git a/qca-ssdk/include/ref/ref_fdb.h b/qca-ssdk/include/ref/ref_fdb.h
new file mode 100755
index 0000000..31592c8
--- /dev/null
+++ b/qca-ssdk/include/ref/ref_fdb.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REF_FDB_H_
+#define _REF_FDB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include <linux/version.h>
+#if defined(IN_SWCONFIG)
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#include <linux/switch.h>
+#else
+#include <net/switch.h>
+#endif
+#endif
+
+#include <linux/notifier.h>
+#include "sw.h"
+#include "fal/fal_type.h"
+
+#if defined(IN_SWCONFIG)
+int
+	qca_ar8327_sw_atu_flush(struct switch_dev *dev,
+					const struct switch_attr *attr,
+					struct switch_val *val);
+
+int
+qca_ar8327_sw_atu_dump(struct switch_dev *dev,
+		       		const struct switch_attr *attr,
+		       		struct switch_val *val);
+#endif
+
+fal_port_t
+ref_fdb_get_port_by_mac(unsigned int vid, const char * addr);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _REF_FDB_H_ */
+
diff --git a/qca-ssdk/include/ref/ref_mib.h b/qca-ssdk/include/ref/ref_mib.h
new file mode 100755
index 0000000..6cb0639
--- /dev/null
+++ b/qca-ssdk/include/ref/ref_mib.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REF_MIB_H_
+#define _REF_MIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#if defined(IN_SWCONFIG)
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#include <linux/switch.h>
+#else
+#include <net/switch.h>
+#endif
+
+int
+qca_ar8327_sw_set_reset_mibs(struct switch_dev *dev,
+			 						const struct switch_attr *attr,
+			 						struct switch_val *val);
+
+int
+qca_ar8327_sw_set_port_reset_mib(struct switch_dev *dev,
+			     					const struct switch_attr *attr,
+			     					struct switch_val *val);
+
+
+int
+qca_ar8327_sw_get_port_mib(struct switch_dev *dev,
+		       						const struct switch_attr *attr,
+		       						struct switch_val *val);
+
+#endif
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _REF_MIB_H_ */
+
diff --git a/qca-ssdk/include/ref/ref_misc.h b/qca-ssdk/include/ref/ref_misc.h
new file mode 100755
index 0000000..70ab4b9
--- /dev/null
+++ b/qca-ssdk/include/ref/ref_misc.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REF_MISC_H_
+#define _REF_MISC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#if defined(IN_SWCONFIG)
+int
+qca_ar8327_sw_set_max_frame_size(struct switch_dev *dev,
+										const struct switch_attr *attr,
+		   								struct switch_val *val);
+
+int
+qca_ar8327_sw_get_max_frame_size(struct switch_dev *dev,
+										const struct switch_attr *attr,
+		   								struct switch_val *val);
+
+int
+qca_ar8327_sw_reset_switch(struct switch_dev *dev);
+#endif
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _REF_MISC_H_ */
+
diff --git a/qca-ssdk/include/ref/ref_port_ctrl.h b/qca-ssdk/include/ref/ref_port_ctrl.h
new file mode 100755
index 0000000..b614c95
--- /dev/null
+++ b/qca-ssdk/include/ref/ref_port_ctrl.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REF_PORT_CTRL_H_
+#define _REF_PORT_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#include <linux/version.h>
+#if defined(IN_SWCONFIG)
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#include <linux/switch.h>
+#else
+#include <net/switch.h>
+#endif
+#endif
+
+#include <linux/notifier.h>
+
+/**
+ * @brief QCA SSDK port link context
+ */
+
+typedef struct{
+    unsigned char port_id;/*port 1-5*/
+    unsigned char port_link; /*0:linkdown, 1:linkup*/
+    unsigned char speed; /*0:10M, 1:100M, 2:1000M*/
+    unsigned char duplex;/*0:half, 1:full*/
+}ssdk_port_status;
+
+#if defined(IN_SWCONFIG)
+int
+qca_ar8327_sw_get_port_link(struct switch_dev *dev, int port,
+	struct switch_port_link *link);
+int qca_ar8327_sw_set_eee(struct switch_dev *dev,
+	const struct switch_attr *attr, struct switch_val *val);
+int qca_ar8327_sw_get_eee(struct switch_dev *dev,
+	const struct switch_attr *attr, struct switch_val *val);
+#endif
+
+int ssdk_port_link_notify_register(struct notifier_block *nb);
+int ssdk_port_link_notify_unregister(struct notifier_block *nb);
+int ssdk_port_link_notify(unsigned char port_id,
+	unsigned char link, unsigned char speed, unsigned char duplex);
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _REF_PORT_CTRL_H_ */
+
diff --git a/qca-ssdk/include/ref/ref_uci.h b/qca-ssdk/include/ref/ref_uci.h
new file mode 100755
index 0000000..107a9e7
--- /dev/null
+++ b/qca-ssdk/include/ref/ref_uci.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REF_UCI_H_
+#define _REF_UCI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+
+#if defined(IN_SWCONFIG)
+int
+qca_ar8327_sw_switch_ext(struct switch_dev *dev,
+			 	const struct switch_attr *attr,
+			 	struct switch_val *val);
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _REF_FDB_H_ */
+
diff --git a/qca-ssdk/include/ref/ref_vlan.h b/qca-ssdk/include/ref/ref_vlan.h
new file mode 100755
index 0000000..e76bbac
--- /dev/null
+++ b/qca-ssdk/include/ref/ref_vlan.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REF_VLAN_H_
+#define _REF_VLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+#if defined(IN_SWCONFIG)
+#include <linux/version.h>
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#include <linux/switch.h>
+#else
+#include <net/switch.h>
+#endif
+
+int
+qca_ar8327_sw_set_vlan(struct switch_dev *dev,
+                       const struct switch_attr *attr,
+                       struct switch_val *val);
+
+int
+qca_ar8327_sw_get_vlan(struct switch_dev *dev,
+                       const struct switch_attr *attr,
+                       struct switch_val *val);
+
+int
+qca_ar8327_sw_set_vid(struct switch_dev *dev,
+                      const struct switch_attr *attr,
+                      struct switch_val *val);
+
+int
+qca_ar8327_sw_get_vid(struct switch_dev *dev,
+                      const struct switch_attr *attr,
+                      struct switch_val *val);
+
+int
+qca_ar8327_sw_get_pvid(struct switch_dev *dev, int port, int *vlan);
+
+int
+qca_ar8327_sw_set_pvid(struct switch_dev *dev, int port, int vlan);
+
+int
+qca_ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val);
+
+int
+qca_ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val);
+
+int
+qca_ar8327_sw_hw_apply(struct switch_dev *dev);
+#endif
+
+typedef struct {
+	fal_port_t port_id;        /* port id */
+	a_uint32_t vid;            /* vlan id */
+	a_bool_t   is_wan_port;    /* belong to wan port */
+	a_bool_t   valid;          /* valid or not */
+} qca_lan_wan_port_info;
+
+typedef struct {
+	a_bool_t lan_only_mode;
+	qca_lan_wan_port_info v_port_info[SW_MAX_NR_PORT];
+} qca_lan_wan_cfg_t;
+
+sw_error_t
+qca_lan_wan_cfg_set(a_uint32_t dev_id, qca_lan_wan_cfg_t *lan_wan_cfg);
+
+sw_error_t
+qca_lan_wan_cfg_get(a_uint32_t dev_id, qca_lan_wan_cfg_t *lan_wan_cfg);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _REF_VLAN_H_ */
+
diff --git a/qca-ssdk/include/ref/ref_vsi.h b/qca-ssdk/include/ref/ref_vsi.h
new file mode 100755
index 0000000..0698f93
--- /dev/null
+++ b/qca-ssdk/include/ref/ref_vsi.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef REF_VSI_H
+#define REF_VSI_H
+#include "sw.h"
+#include "fal/fal_type.h"
+#include "fal/fal_vsi.h"
+
+
+#define REF_DEV_ID_CHECK(dev_id) \
+do { \
+    if (dev_id >= SW_MAX_NR_DEV) \
+        return SW_OUT_OF_RANGE; \
+} while (0)
+
+#define REF_PORT_ID_CHECK(port_id) \
+do { \
+    if (port_id >= SW_MAX_NR_PORT) \
+        return SW_OUT_OF_RANGE; \
+} while (0)
+
+#define REF_NULL_POINT_CHECK(point) \
+do { \
+    if (point == NULL) \
+        return SW_BAD_PTR; \
+} while (0)
+
+
+enum{
+	PPE_VSI_ADD,
+	PPE_VSI_DEL
+};
+typedef struct REF_VLAN_INFO_T {
+	a_uint32_t stag_vid;
+	a_uint32_t ctag_vid;
+	a_uint32_t vport_bitmap; /*vlan based vsi*/
+	struct REF_VLAN_INFO_T *pNext;
+}ref_vlan_info_t;
+
+typedef struct{
+	a_uint32_t valid;
+	a_uint32_t pport_bitmap; /*port based vsi*/
+	ref_vlan_info_t *pHead;
+}ref_vsi_t;
+
+#define PPE_VSI_PPORT_NR 7
+#define PPE_VSI_INVALID FAL_VSI_INVALID
+
+sw_error_t ppe_port_vlan_vsi_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id);
+sw_error_t ppe_port_vlan_vsi_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t *vsi_id);
+sw_error_t ppe_port_vsi_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t vsi_id);
+sw_error_t ppe_port_vsi_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t *vsi_id);
+sw_error_t ppe_vsi_alloc(a_uint32_t dev_id, a_uint32_t *vsi);
+sw_error_t ppe_vsi_free(a_uint32_t dev_id, a_uint32_t vsi_id);
+sw_error_t ppe_vsi_tbl_dump(a_uint32_t dev_id);
+sw_error_t ppe_vsi_init(a_uint32_t dev_id);
+#endif
+
diff --git a/qca-ssdk/include/sal/os/aos_lock.h b/qca-ssdk/include/sal/os/aos_lock.h
new file mode 100755
index 0000000..830151e
--- /dev/null
+++ b/qca-ssdk/include/sal/os/aos_lock.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _AOS_LOCK_H
+#define _AOS_LOCK_H
+
+
+#include "aos_lock_pvt.h"
+
+
+typedef aos_lock_pvt_t aos_lock_t;
+
+
+#define aos_lock_init(lock)  __aos_lock_init(lock)
+
+
+#define aos_lock(lock) __aos_lock(lock)
+
+
+#define aos_unlock(lock) __aos_unlock(lock)
+
+#define aos_lock_bh(lock) __aos_lock_bh(lock)
+
+#define aos_unlock_bh(lock) __aos_unlock_bh(lock)
+
+
+#define aos_irq_save(flags) __aos_irq_save(flags)
+
+
+#define aos_irq_restore(flags) __aos_irq_restore(flags)
+
+
+#define aos_default_unlock  __aos_default_unlock
+
+
+#endif
diff --git a/qca-ssdk/include/sal/os/aos_mem.h b/qca-ssdk/include/sal/os/aos_mem.h
new file mode 100755
index 0000000..b9365b9
--- /dev/null
+++ b/qca-ssdk/include/sal/os/aos_mem.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _AOS_MEM_H
+#define _AOS_MEM_H
+
+#include "aos_types.h"
+#include "aos_mem_pvt.h"
+
+/**
+ * @g aos_mem mem
+ * @{
+ *
+ * @ig shim_ext
+ */
+
+/**
+ * @brief Allocate a memory buffer. Note it's a non-blocking call.
+ * This call can block.
+ *
+ * @param[in] size    buffer size
+ *
+ * @return Buffer pointer or NULL if there's not enough memory.
+ */
+static inline void *
+aos_mem_alloc(aos_size_t size)
+{
+    return __aos_mem_alloc(size);
+}
+
+/**
+ * @brief Free malloc'ed buffer
+ *
+ * @param[in] buf     buffer pointer allocated by aos_alloc()
+ * @param[in] size    buffer size
+ */
+static inline void
+aos_mem_free(void *buf)
+{
+    __aos_mem_free(buf);
+}
+
+/**
+ * @brief Move a memory buffer
+ *
+ * @param[in] dst     destination address
+ * @param[in] src     source address
+ * @param[in] size    buffer size
+ */
+static inline void
+aos_mem_copy(void *dst, void *src, aos_size_t size)
+{
+    __aos_mem_copy(dst, src, size);
+}
+
+/**
+ * @brief Fill a memory buffer
+ *
+ * @param[in] buf   buffer to be filled
+ * @param[in] b     byte to fill
+ * @param[in] size  buffer size
+ */
+static inline void
+aos_mem_set(void *buf, a_uint8_t b, aos_size_t size)
+{
+    __aos_mem_set(buf, b, size);
+}
+
+/**
+ * @brief Zero a memory buffer
+ *
+ * @param[in] buf   buffer to be zeroed
+ * @param[in] size  buffer size
+ */
+static inline void
+aos_mem_zero(void *buf, aos_size_t size)
+{
+    __aos_mem_zero(buf, size);
+}
+
+/**
+ * @brief Compare two memory buffers
+ *
+ * @param[in] buf1  first buffer
+ * @param[in] buf2  second buffer
+ * @param[in] size  buffer size
+ *
+ * @retval    0     equal
+ * @retval    1     not equal
+ */
+static inline int
+aos_mem_cmp(void *buf1, void *buf2, aos_size_t size)
+{
+    return __aos_mem_cmp(buf1, buf2, size);
+}
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/qca-ssdk/include/sal/os/aos_timer.h b/qca-ssdk/include/sal/os/aos_timer.h
new file mode 100755
index 0000000..3b4161b
--- /dev/null
+++ b/qca-ssdk/include/sal/os/aos_timer.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _AOS_TIMER_H
+#define _AOS_TIMER_H
+
+#include "aos_types.h"
+#include "aos_timer_pvt.h"
+
+
+typedef __aos_timer_t           aos_timer_t;
+
+
+/*
+ * Delay in microseconds
+ */
+static inline void
+aos_udelay(int usecs)
+{
+    return __aos_udelay(usecs);
+}
+
+/*
+ * Delay in milliseconds.
+ */
+static inline void
+aos_mdelay(int msecs)
+{
+    return __aos_mdelay(msecs);
+}
+
+
+#endif
+
diff --git a/qca-ssdk/include/sal/os/aos_types.h b/qca-ssdk/include/sal/os/aos_types.h
new file mode 100755
index 0000000..c26fb18
--- /dev/null
+++ b/qca-ssdk/include/sal/os/aos_types.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _AOS_TYPES_H
+#define _AOS_TYPES_H
+
+#include "aos_types_pvt.h"
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+/**
+ * @g aos_types types
+ * @{
+ *
+ * @ig shim_ext
+ */
+/*
+ *@ basic data types.
+ */
+typedef enum
+{
+    A_FALSE,
+    A_TRUE
+} a_bool_t;
+
+typedef __a_uint8_t    a_uint8_t;
+typedef __a_int8_t     a_int8_t;
+typedef __a_uint16_t   a_uint16_t;
+typedef __a_int16_t    a_int16_t;
+typedef __a_uint32_t   a_uint32_t;
+typedef __a_int32_t    a_int32_t;
+typedef __a_uint64_t   a_uint64_t;
+typedef __a_int64_t    a_int64_t;
+typedef unsigned long  a_ulong_t;
+
+
+typedef void *                   acore_t;
+
+/**
+ * @brief Platform/bus generic handle. Used for bus specific functions.
+ */
+typedef __aos_device_t              aos_device_t;
+
+/**
+ * @brief size of an object
+ */
+typedef __aos_size_t                aos_size_t;
+
+/**
+ * @brief Generic status to be used by acore.
+ */
+typedef enum
+{
+    A_STATUS_OK,
+    A_STATUS_FAILED,
+    A_STATUS_ENOENT,
+    A_STATUS_ENOMEM,
+    A_STATUS_EINVAL,
+    A_STATUS_EINPROGRESS,
+    A_STATUS_ENOTSUPP,
+    A_STATUS_EBUSY,
+} a_status_t;
+
+/*
+ * An ecore needs to provide a table of all pci device/vendor id's it
+ * supports
+ *
+ * This table should be terminated by a NULL entry , i.e. {0}
+ */
+typedef struct
+{
+    a_uint32_t vendor;
+    a_uint32_t device;
+    a_uint32_t subvendor;
+    a_uint32_t subdevice;
+} aos_pci_dev_id_t;
+
+#define AOS_PCI_ANY_ID  (~0)
+
+/*
+ * Typically core's can use this macro to create a table of various device
+ * ID's
+ */
+#define AOS_PCI_DEVICE(_vendor, _device)   \
+    (_vendor), (_device), AOS_PCI_ANY_ID, AOS_PCI_ANY_ID
+
+
+typedef __aos_iomem_t   aos_iomem_t;
+/*
+ * These define the hw resources the OS has allocated for the device
+ * Note that start defines a mapped area.
+ */
+typedef enum
+{
+    AOS_RESOURCE_TYPE_MEM,
+    AOS_RESOURCE_TYPE_IO,
+} aos_resource_type_t;
+
+typedef struct
+{
+    a_uint32_t          start;
+    a_uint32_t          end;
+    aos_resource_type_t type;
+} aos_resource_t;
+
+#define AOS_DEV_ID_TABLE_MAX    256
+
+typedef union
+{
+    aos_pci_dev_id_t  *pci;
+    void              *raw;
+} aos_bus_reg_data_t;
+
+typedef void *aos_attach_data_t;
+
+#define AOS_REGIONS_MAX     5
+
+typedef enum
+{
+    AOS_BUS_TYPE_PCI = 1,
+    AOS_BUS_TYPE_GENERIC,
+} aos_bus_type_t;
+
+typedef enum
+{
+    AOS_IRQ_NONE,
+    AOS_IRQ_HANDLED,
+} aos_irq_resp_t;
+
+typedef enum
+{
+    AOS_DMA_MASK_32BIT,
+    AOS_DMA_MASK_64BIT,
+} aos_dma_mask_t;
+
+
+/**
+ * @brief DMA directions
+ */
+typedef enum
+{
+    AOS_DMA_TO_DEVICE = 0,     /**< Data is transfered from device to memory  */
+    AOS_DMA_FROM_DEVICE,       /**< Data is transfered from memory to device  */
+} aos_dma_dir_t;
+
+/*
+ * Protoypes shared between public and private headers
+ */
+
+
+/*
+ * work queue(kernel thread) function callback
+ */
+typedef void (*aos_work_func_t)(void *);
+
+/**
+ * @brief Prototype of the critical region function that is to be
+ * executed with spinlock held and interrupt disalbed
+ */
+typedef a_bool_t (*aos_irqlocked_func_t)(void *);
+
+/**
+ * @brief Prototype of timer function
+ */
+typedef void (*aos_timer_func_t)(void *);
+
+#endif
diff --git a/qca-ssdk/include/sal/os/linux/aos_lock_pvt.h b/qca-ssdk/include/sal/os/linux/aos_lock_pvt.h
new file mode 100755
index 0000000..fe220ab
--- /dev/null
+++ b/qca-ssdk/include/sal/os/linux/aos_lock_pvt.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _AOS_LOCK_PVT_H
+#define _AOS_LOCK_PVT_H
+
+
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+
+
+typedef spinlock_t aos_lock_pvt_t;
+
+
+#define __aos_lock_init(lock)  spin_lock_init(lock)
+
+
+#define __aos_lock(lock) spin_lock(lock)
+
+
+#define __aos_unlock(lock) spin_unlock(lock)
+
+#define __aos_lock_bh(lock) spin_lock_bh(lock)
+
+#define __aos_unlock_bh(lock) spin_unlock_bh(lock)
+
+#define __aos_irq_save(flags) local_irq_save(flags)
+
+#define __aos_irq_restore(flags) local_irq_restore(flags)
+
+#ifndef KVER32
+#define __aos_default_unlock SPIN_LOCK_UNLOCKED
+#endif
+
+#endif /*_AOS_LOCK_PVT_H*/
+
diff --git a/qca-ssdk/include/sal/os/linux/aos_mem_pvt.h b/qca-ssdk/include/sal/os/linux/aos_mem_pvt.h
new file mode 100755
index 0000000..f81e23c
--- /dev/null
+++ b/qca-ssdk/include/sal/os/linux/aos_mem_pvt.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _AOS_MEM_PVT_H
+#define _AOS_MEM_PVT_H
+
+#include <linux/slab.h>
+
+static inline void *__aos_mem_alloc(aos_size_t size)
+{
+    return (kmalloc(size, GFP_KERNEL | __GFP_ZERO));
+}
+
+static inline void __aos_mem_free(void *buf)
+{
+    kfree(buf);
+}
+
+/* move a memory buffer */
+static inline void
+__aos_mem_copy(void *dst, void *src, aos_size_t size)
+{
+    memcpy(dst, src, size);
+}
+
+/* set a memory buffer */
+static inline void
+__aos_mem_set(void *buf, a_uint8_t b, aos_size_t size)
+{
+    memset(buf, b, size);
+}
+
+/* zero a memory buffer */
+static inline void
+__aos_mem_zero(void *buf, aos_size_t size)
+{
+    memset(buf, 0, size);
+}
+
+/* compare two memory buffers */
+static inline int
+__aos_mem_cmp(void *buf1, void *buf2, aos_size_t size)
+{
+    return (memcmp(buf1, buf2, size) == 0) ? 0 : 1;
+}
+
+
+
+#endif /*_AOS_MEM_PVT_H*/
diff --git a/qca-ssdk/include/sal/os/linux/aos_timer_pvt.h b/qca-ssdk/include/sal/os/linux/aos_timer_pvt.h
new file mode 100755
index 0000000..8bb49bc
--- /dev/null
+++ b/qca-ssdk/include/sal/os/linux/aos_timer_pvt.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _AOS_TIMER_PVT_H
+#define _AOS_TIMER_PVT_H
+
+#ifdef KVER26
+#include <linux/jiffies.h>
+#endif
+#include <linux/delay.h>
+#include <linux/timer.h>
+
+
+/*
+ * timer data type
+ */
+typedef struct timer_list       __aos_timer_t;
+
+
+static inline void
+__aos_udelay(int usecs)
+{
+    udelay(usecs);
+}
+
+static inline void
+__aos_mdelay(int msecs)
+{
+    mdelay(msecs);
+}
+
+#endif /*_AOS_TIMER_PVT_H*/
diff --git a/qca-ssdk/include/sal/os/linux/aos_types_pvt.h b/qca-ssdk/include/sal/os/linux/aos_types_pvt.h
new file mode 100755
index 0000000..6d85ecb
--- /dev/null
+++ b/qca-ssdk/include/sal/os/linux/aos_types_pvt.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _AOS_PVTTYPES_H
+#define _AOS_PVTTYPES_H
+
+#include <generated/autoconf.h>
+#include <asm/types.h>
+#include <linux/compiler.h>
+/*
+ * Private definitions of general data types
+ */
+
+/* generic data types */
+typedef struct device *   __aos_device_t;
+typedef int               __aos_size_t;
+
+#ifdef KVER26
+#ifdef LNX26_22
+typedef __u8 * __aos_iomem_t;
+#else
+typedef u8 __iomem * __aos_iomem_t;
+#endif
+#else /*Linux Kernel 2.4 */
+typedef   u8         * __aos_iomem_t;
+#endif
+
+#ifdef KVER32
+typedef u8 __iomem * __aos_iomem_t;
+#endif
+
+#ifdef LNX26_22 /* > Linux 2.6.22 */
+typedef   __u8              __a_uint8_t;
+typedef   __s8              __a_int8_t;
+typedef   __u16             __a_uint16_t;
+typedef   __s16             __a_int16_t;
+typedef   __u32             __a_uint32_t;
+typedef   __s32             __a_int32_t;
+typedef   __u64             __a_uint64_t;
+typedef   __s64             __a_int64_t;
+#else
+typedef   u8              __a_uint8_t;
+typedef   s8              __a_int8_t;
+typedef   u16             __a_uint16_t;
+typedef   s16             __a_int16_t;
+typedef   u32             __a_uint32_t;
+typedef   s32             __a_int32_t;
+typedef   u64             __a_uint64_t;
+typedef   s64             __a_int64_t;
+#endif
+
+#define aos_printk        printk
+
+#define AUTO_UPDATE_PPPOE_INFO 1
+#if 0
+#undef AUTO_UPDATE_PPPOE_INFO
+#endif
+
+#endif
diff --git a/qca-ssdk/include/sal/sd/linux/uk_interface/sw_api_ks.h b/qca-ssdk/include/sal/sd/linux/uk_interface/sw_api_ks.h
new file mode 100755
index 0000000..fcc0552
--- /dev/null
+++ b/qca-ssdk/include/sal/sd/linux/uk_interface/sw_api_ks.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _SW_API_KS_H
+#define _SW_API_KS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "sw.h"
+
+    sw_error_t sw_uk_init(a_uint32_t nl_prot);
+
+    sw_error_t sw_uk_cleanup(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SW_API_KS_H */
diff --git a/qca-ssdk/include/sal/sd/sd.h b/qca-ssdk/include/sal/sd/sd.h
new file mode 100755
index 0000000..ada85ac
--- /dev/null
+++ b/qca-ssdk/include/sal/sd/sd.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/*qca808x_start*/
+#ifndef _SD_H_
+#define _SD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+    sw_error_t
+    sd_reg_mdio_set(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg,
+                    a_uint16_t data);
+
+    sw_error_t
+    sd_reg_mdio_get(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg,
+                    a_uint16_t * data);
+
+    sw_error_t
+    sd_reg_i2c_set(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg,
+                    a_uint16_t data);
+
+    sw_error_t
+    sd_reg_i2c_get(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg,
+                    a_uint16_t * data);
+/*qca808x_end*/
+    sw_error_t
+    sd_reg_hdr_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint8_t * reg_data, a_uint32_t len);
+
+    sw_error_t
+    sd_reg_hdr_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint8_t * reg_data, a_uint32_t len);
+
+    sw_error_t
+    sd_reg_psgmii_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint8_t * reg_data, a_uint32_t len);
+
+    sw_error_t
+    sd_reg_psgmii_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint8_t * reg_data, a_uint32_t len);
+
+	sw_error_t
+	sd_reg_uniphy_set(a_uint32_t dev_id, a_uint32_t index,
+		a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len);
+
+	sw_error_t
+	sd_reg_uniphy_get(a_uint32_t dev_id, a_uint32_t index,
+		a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len);
+
+	void
+	sd_reg_mii_set(a_uint32_t dev_id, a_uint32_t reg, a_uint32_t val);
+
+	a_uint32_t
+	sd_reg_mii_get(a_uint32_t dev_id, a_uint32_t reg);
+/*qca808x_start*/
+    sw_error_t sd_init(a_uint32_t dev_id, ssdk_init_cfg * cfg);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* _SD_H_ */
+/*qca808x_end*/
+
diff --git a/qca-ssdk/include/shell_lib/shell.h b/qca-ssdk/include/shell_lib/shell.h
new file mode 100755
index 0000000..5bdcfb4
--- /dev/null
+++ b/qca-ssdk/include/shell_lib/shell.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _SW_SHELL_H
+#define _SW_SHELL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include "sw.h"
+#include "sw_api.h"
+#include "ssdk_init.h"
+
+
+#define IOCTL_BUF_SIZE 2048
+#define CMDSTR_BUF_SIZE 1024
+#define CMDSTR_ARGS_MAX 128
+#define dprintf 
+
+int cmd_run_one(char *cmd_str);
+extern void cmd_print(char *fmt, ...);
+void cmd_print_error(sw_error_t rtn);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _SW_SHELL_H */
diff --git a/qca-ssdk/include/shell_lib/shell_config.h b/qca-ssdk/include/shell_lib/shell_config.h
new file mode 100755
index 0000000..173c755
--- /dev/null
+++ b/qca-ssdk/include/shell_lib/shell_config.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _SHELL_CONFIG_H_
+#define _SHELL_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "sw_api.h"
+
+#define SW_CMD_SET_DEVID       (SW_API_MAX + 1)
+#define SW_CMD_VLAN_SHOW       (SW_API_MAX + 2)
+#define SW_CMD_FDB_SHOW        (SW_API_MAX + 3)
+#define SW_CMD_RESV_FDB_SHOW   (SW_API_MAX + 4)
+#define SW_CMD_HOST_SHOW       (SW_API_MAX + 5)
+#define SW_CMD_NAT_SHOW        (SW_API_MAX + 6)
+#define SW_CMD_NAPT_SHOW       (SW_API_MAX + 7)
+#define SW_CMD_INTFMAC_SHOW    (SW_API_MAX + 8)
+#define SW_CMD_PUBADDR_SHOW    (SW_API_MAX + 9)
+#define SW_CMD_FLOW_SHOW       (SW_API_MAX + 10)
+#define SW_CMD_MAX             (SW_API_MAX + 11)
+
+#define MAX_SUB_CMD_DES_NUM  40
+
+    struct sub_cmd_des_t
+    {
+        char *sub_name;
+        char *sub_act;
+        int   sub_api;
+        sw_error_t (*sub_func) (void);
+    };
+    struct cmd_des_t
+    {
+        char *name;
+        struct sub_cmd_des_t *sub_cmd_des;
+    };
+    extern struct cmd_des_t gcmd_des[];
+
+#define GCMD_DES gcmd_des
+
+#define GCMD_NAME(cmd_nr)  GCMD_DES[cmd_nr].name
+#define GCMD_MEMO(cmd_nr)  GCMD_DES[cmd_nr].memo
+
+#define GCMD_SUB_NAME(cmd_nr, sub_cmd_nr)  GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_name
+#define GCMD_SUB_ACT(cmd_nr, sub_cmd_nr)  GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_act
+#define GCMD_SUB_MEMO(cmd_nr, sub_cmd_nr)  GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_memo
+#define GCMD_SUB_USAGE(cmd_nr, sub_cmd_nr)  GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_usage
+#define GCMD_SUB_API(cmd_nr, sub_cmd_nr)  GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_api
+#define GCMD_SUB_FUNC(cmd_nr, sub_cmd_nr)  GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_func
+
+#define GCMD_DESC_VALID(cmd_nr)                    GCMD_NAME(cmd_nr)
+#define GCMD_SUB_DESC_VALID(cmd_nr, sub_cmd_nr)    GCMD_SUB_API(cmd_nr, sub_cmd_nr)
+
+
+#define GCMD_DESC_NO_MATCH      0xffffffff
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _SHELL_CONFIG_H_ */
diff --git a/qca-ssdk/include/shell_lib/shell_io.h b/qca-ssdk/include/shell_lib/shell_io.h
new file mode 100644
index 0000000..7a8d319
--- /dev/null
+++ b/qca-ssdk/include/shell_lib/shell_io.h
@@ -0,0 +1,484 @@
+/*
+ * Copyright (c) 2013, 2015-2017, 2019, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _SHELL_IO_H
+#define _SHELL_IO_H
+
+#include "sw.h"
+#include "sw_api.h"
+#include "fal.h"
+
+#define SW_TYPE_DEF(type, parser, show) {type, parser, show}
+typedef sw_error_t
+	(*param_check_t)(char *, a_uint32_t *, a_uint32_t);
+typedef sw_error_t
+	(*param_check_range_t)(char *, a_uint32_t *, a_uint32_t, a_uint32_t);
+typedef sw_error_t
+	(*param_check_boolean_t)(char *, a_bool_t, a_bool_t *, a_uint32_t);
+typedef struct
+{
+    sw_data_type_e data_type;
+    param_check_t param_check;
+    void (*show_func) (void);
+} sw_data_type_t;
+
+void  set_talk_mode(int mode);
+int get_talk_mode(void);
+void set_full_cmdstrp(char **cmdstrp);
+int get_jump(void);
+sw_data_type_t * cmd_data_type_find(sw_data_type_e type);
+void  cmd_strtol(char *str, a_uint32_t * arg_val);
+sw_error_t cmd_data_check_portmap(char *cmdstr, fal_pbmp_t * val, a_uint32_t size);
+sw_error_t cmd_data_check_confirm(char *cmdstr, a_bool_t def, a_bool_t * val, a_uint32_t size);
+
+sw_error_t cmd_data_check_uint32(char *cmd_str, a_uint32_t * arg_val,
+                                 a_uint32_t size);
+sw_error_t cmd_data_check_uint16(char *cmd_str, a_uint32_t * arg_val,
+                                 a_uint32_t size);
+sw_error_t cmd_data_check_uint8(char *cmd_str, a_uint32_t * arg_val,
+                                 a_uint32_t size);
+sw_error_t cmd_data_check_enable(char *cmd_str, a_uint32_t * arg_val,
+                                 a_uint32_t size);
+sw_error_t cmd_data_check_pbmp(char *cmd_str, a_uint32_t * arg_val,
+                               a_uint32_t size);
+#ifdef IN_PORTCONTROL
+sw_error_t cmd_data_check_duplex(char *cmd_str, a_uint32_t * arg_val,
+                                 a_uint32_t size);
+sw_error_t cmd_data_check_speed(char *cmd_str, a_uint32_t * arg_val,
+                                a_uint32_t size);
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+cmd_data_check_port_eee_config(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_switch_port_loopback_config(char *cmd_str, void * val,
+	a_uint32_t size);
+#endif
+#endif
+#ifdef IN_PORTVLAN
+sw_error_t cmd_data_check_1qmode(char *cmd_str, a_uint32_t * arg_val,
+                                 a_uint32_t size);
+sw_error_t cmd_data_check_egmode(char *cmd_str, a_uint32_t * arg_val,
+                                 a_uint32_t size);
+#ifdef HPPE
+sw_error_t
+cmd_data_check_global_qinqmode(char *info, void *val, a_uint32_t size);
+sw_error_t
+cmd_data_check_port_qinqmode(char *info, void *val, a_uint32_t size);
+sw_error_t
+cmd_data_check_tpid(char *info, void *val, a_uint32_t size);
+sw_error_t
+cmd_data_check_ingress_filter(char *info, void *val, a_uint32_t size);
+sw_error_t
+cmd_data_check_port_vlan_direction(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+sw_error_t
+cmd_data_check_port_default_vid_en(char *info, void *val, a_uint32_t size);
+sw_error_t
+cmd_data_check_port_vlan_tag(char *info, void *val, a_uint32_t size);
+sw_error_t
+cmd_data_check_tag_propagation(char *info, void *val, a_uint32_t size);
+sw_error_t
+cmd_data_check_egress_mode(char *info, void *val, a_uint32_t size);
+sw_error_t
+cmd_data_check_port_vlan_translation_adv_rule(char *info, void *val,
+				a_uint32_t size);
+sw_error_t
+cmd_data_check_port_vlan_translation_adv_action(char *info, void *val,
+				a_uint32_t size);
+#endif
+#endif
+#ifdef IN_PORTCONTROL
+sw_error_t cmd_data_check_capable(char *cmd_str, a_uint32_t * arg_val,
+                                  a_uint32_t size);
+#endif
+#ifdef IN_FDB
+sw_error_t cmd_data_check_fdbentry(char *cmdstr, void *val, a_uint32_t size);
+#ifndef IN_FDB_MINI
+sw_error_t cmd_data_check_maclimit_ctrl(char *info, void *val, a_uint32_t size);
+#endif
+#endif
+sw_error_t cmd_data_check_macaddr(char *cmdstr, void *val, a_uint32_t size);
+#ifdef IN_VLAN
+sw_error_t cmd_data_check_vlan(char *cmdstr, fal_vlan_t * val, a_uint32_t size);
+#endif
+#ifdef IN_QOS
+#ifndef IN_QOS_MINI
+sw_error_t cmd_data_check_qos_sch(char *cmdstr, fal_sch_mode_t * val,
+                                  a_uint32_t size);
+sw_error_t cmd_data_check_qos_pt(char *cmdstr, fal_qos_mode_t * val,
+                                 a_uint32_t size);
+sw_error_t
+cmd_data_check_port_group(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_port_pri(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_port_remark(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_cosmap(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_queue_scheduler(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_ring_queue(char *cmd_str, void * val, a_uint32_t size);
+#endif
+#endif
+#ifdef IN_RATE
+sw_error_t cmd_data_check_storm(char *cmdstr, fal_storm_type_t * val,
+                                a_uint32_t size);
+#endif
+#ifdef IN_STP
+sw_error_t cmd_data_check_stp_state(char *cmdstr, fal_stp_state_t * val,
+                                    a_uint32_t size);
+#endif
+#ifdef IN_LEAKY
+sw_error_t cmd_data_check_leaky(char *cmdstr, fal_leaky_ctrl_mode_t * val,
+                                a_uint32_t size);
+#endif
+sw_error_t cmd_data_check_uinta(char *cmdstr, a_uint32_t * val,
+                                a_uint32_t size);
+sw_error_t cmd_data_check_maccmd(char *cmdstr, fal_fwd_cmd_t * val,
+                                 a_uint32_t size);
+#ifdef IN_IP
+#ifndef IN_IP_MINI
+sw_error_t cmd_data_check_flowcmd(char *cmdstr, fal_default_flow_cmd_t * val,
+                                 a_uint32_t size);
+sw_error_t cmd_data_check_flowtype(char *cmdstr, fal_flow_type_t * val,
+                                 a_uint32_t size);
+#endif
+#endif
+#ifdef IN_LED
+sw_error_t cmd_data_check_ledpattern(char *info, void * val, a_uint32_t size);
+#endif
+#ifdef IN_PORTVLAN
+sw_error_t
+cmd_data_check_invlan_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+sw_error_t
+cmd_data_check_vlan_propagation(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+#ifndef IN_PORTVLAN_MINI
+sw_error_t
+cmd_data_check_vlan_translation(char *info, fal_vlan_trans_entry_t *val, a_uint32_t size);
+#endif
+sw_error_t
+cmd_data_check_qinq_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+sw_error_t
+cmd_data_check_qinq_role(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+#endif
+#ifdef IN_PORTCONTROL
+sw_error_t
+cmd_data_check_hdrmode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+#endif
+#ifdef IN_FDB
+sw_error_t
+cmd_data_check_fdboperation(char *cmd_str, void * val, a_uint32_t size);
+#endif
+#ifdef IN_PPPOE
+sw_error_t
+cmd_data_check_pppoe(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_pppoe_less(char *cmd_str, void * val, a_uint32_t size);
+#endif
+#if defined(IN_IP) || defined(IN_NAT)
+sw_error_t
+cmd_data_check_host_entry(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_arp_learn_mode(char *cmd_str, fal_arp_learn_mode_t * arg_val,
+                              a_uint32_t size);
+
+sw_error_t
+cmd_data_check_ip_guard_mode(char *cmd_str, fal_source_guard_mode_t * arg_val, a_uint32_t size);
+
+
+sw_error_t
+cmd_data_check_nat_entry(char *cmd_str, void * val, a_uint32_t size);
+
+
+sw_error_t
+cmd_data_check_napt_entry(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_flow_entry(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_napt_mode(char *cmd_str, fal_napt_mode_t * arg_val, a_uint32_t size);
+
+
+sw_error_t
+cmd_data_check_intf_mac_entry(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_pub_addr_entry(char *cmd_str, void * val, a_uint32_t size);
+#endif
+
+sw_error_t
+cmd_data_check_ip4addr(char *cmdstr, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_ip6addr(char *cmdstr, void * val, a_uint32_t size);
+
+
+sw_error_t
+cmd_data_check_egress_shaper(char *cmd_str, void * val, a_uint32_t size);
+
+#ifdef IN_RATE
+sw_error_t
+cmd_data_check_port_policer(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_policer_timesslot(char *cmd_str, a_uint32_t * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_acl_policer(char *cmd_str, void * val, a_uint32_t size);
+#endif
+#ifdef IN_FDB
+#ifndef IN_FDB_MINI
+sw_error_t
+cmd_data_check_fdb_smode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+#endif
+#endif
+#ifdef IN_IGMP
+sw_error_t
+cmd_data_check_multi(char *info, void *val, a_uint32_t size);
+#endif
+#ifdef IN_SEC
+sw_error_t
+cmd_data_check_sec_mac(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_sec_ip(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_sec_ip4(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_sec_ip6(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_sec_tcp(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_sec_udp(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_sec_icmp4(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_sec_icmp6(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+#ifdef HPPE
+sw_error_t
+cmd_data_check_l3_parser(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_l4_parser(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_exp_ctrl(char *cmd_str, void * val, a_uint32_t size);
+#endif
+#endif
+#ifdef IN_COSMAP
+#ifndef IN_COSMAP_MINI
+sw_error_t
+cmd_data_check_remark_entry(char *info, void *val, a_uint32_t size);
+#endif
+#endif
+#ifdef IN_IP
+#ifndef IN_IP_MINI
+sw_error_t
+cmd_data_check_default_route_entry(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_host_route_entry(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_ip4_rfs_entry(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_ip6_rfs_entry(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_arp_sg(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_network_route(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_intf(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_vsi_intf(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_nexthop(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_ip_sg(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_ip_pub(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_ip_portmac(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_ip_mcmode(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_ip_global(char *cmd_str, void * val, a_uint32_t size);
+#endif
+#endif
+#if defined(IN_IP) || defined(IN_NAT)
+sw_error_t
+cmd_data_check_flow_cookie(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_flow_rfs(char *cmd_str, void * val, a_uint32_t size);
+#endif
+#ifdef IN_PORTCONTROL
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+cmd_data_check_crossover_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_crossover_status(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_prefer_medium(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_fiber_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_src_filter_config(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_mtu_entry(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_mru_entry(char *cmd_str, void * val, a_uint32_t size);
+
+
+#endif
+#endif
+#ifdef IN_INTERFACECONTROL
+sw_error_t
+cmd_data_check_interface_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+#endif
+#ifdef IN_VSI
+sw_error_t
+cmd_data_check_newadr_lrn(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_stamove(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_vsi_member(char *cmd_str, void * val, a_uint32_t size);
+
+#endif
+#ifdef IN_BM
+sw_error_t
+cmd_data_check_bm_dynamic_thresh(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_bm_static_thresh(char *cmd_str, void * val, a_uint32_t size);
+#endif
+#ifdef IN_QM
+sw_error_t
+cmd_data_check_u_qmap(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_ac_static_thresh(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_ac_dynamic_thresh(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_ac_group_buff(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_ac_ctrl(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_ac_obj(char *cmd_str, void * val, a_uint32_t size);
+
+#endif
+#ifdef IN_FLOW
+sw_error_t
+cmd_data_check_flow_age(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_flow_ctrl(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_flow(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_flow_global(char *cmd_str, void * val, a_uint32_t size);
+sw_error_t
+cmd_data_check_flow_host(char *cmd_str, void * val, a_uint32_t size);
+#endif
+
+#ifdef IN_POLICER
+sw_error_t
+cmd_data_check_port_policer_config(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_policer_cmd_config(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_acl_policer_config(char *cmd_str, void * val, a_uint32_t size);
+
+#endif
+
+#ifdef IN_SHAPER
+sw_error_t
+cmd_data_check_port_shaper_token_config(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_shaper_token_config(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_port_shaper_config(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_shaper_config(char *cmd_str, void * val, a_uint32_t size);
+
+#endif
+
+#ifdef IN_SERVCODE
+sw_error_t
+cmd_data_check_servcode_config(char *info, fal_servcode_config_t *val, a_uint32_t size);
+#endif
+
+#ifdef IN_RSS_HASH
+sw_error_t
+cmd_data_check_rss_hash_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+sw_error_t
+cmd_data_check_rss_hash_config(char *info, fal_rss_hash_config_t *val, a_uint32_t size);
+#endif
+
+#ifdef IN_MIRROR
+sw_error_t
+cmd_data_check_mirr_analy_cfg(char *info, void *val, a_uint32_t size);
+sw_error_t
+cmd_data_check_mirr_direction(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+#endif
+sw_error_t
+cmd_data_check_integer(char *cmd_str, a_uint32_t * arg_val, a_uint32_t max_val, a_uint32_t min_val);
+#ifdef IN_CTRLPKT
+sw_error_t
+cmd_data_check_ctrlpkt_appprofile(char *info, void *val, a_uint32_t size);
+#endif
+#ifdef IN_ACL
+sw_error_t
+cmd_data_check_ruletype(char *cmd_str, fal_acl_rule_type_t * arg_val, a_uint32_t size);
+sw_error_t
+cmd_data_check_udf_pkt_type(char *cmdstr, fal_acl_udf_pkt_type_t * arg_val, a_uint32_t size);
+sw_error_t
+cmd_data_check_udf_type(char *cmdstr, fal_acl_udf_type_t * arg_val, a_uint32_t size);
+sw_error_t
+cmd_data_check_udf_element(char *cmdstr, a_uint8_t * val, a_uint32_t * len);
+sw_error_t
+cmd_data_check_fieldop(char *cmdstr, fal_acl_field_op_t def, fal_acl_field_op_t * val);
+
+#endif
+sw_error_t
+cmd_data_check_module(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+sw_error_t
+cmd_data_check_func_ctrl(char *cmd_str, void * val, a_uint32_t size);
+#endif
+
diff --git a/qca-ssdk/include/shell_lib/shell_sw.h b/qca-ssdk/include/shell_lib/shell_sw.h
new file mode 100755
index 0000000..80d3acb
--- /dev/null
+++ b/qca-ssdk/include/shell_lib/shell_sw.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2013, 2017, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _SHELL_SW_H_
+#define _SHELL_SW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+    int get_devid(void);
+    sw_error_t cmd_set_devid(a_uint32_t *arg_val);
+    sw_error_t uci_set_devid(a_uint32_t dev_id);
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+
+#endif                          /* _SHELL_SW_H_ */
diff --git a/qca-ssdk/ko_Makefile b/qca-ssdk/ko_Makefile
new file mode 100755
index 0000000..5cfb1f3
--- /dev/null
+++ b/qca-ssdk/ko_Makefile
@@ -0,0 +1,3 @@
+obj-m :=  qca-ssdk.o
+OBJ_LIST:=$(notdir $(wildcard $(PRJ_PATH)/temp/*.o))
+qca-ssdk-objs := $(OBJ_LIST)
diff --git a/qca-ssdk/make/.build_number b/qca-ssdk/make/.build_number
new file mode 100644
index 0000000..0cfbf08
--- /dev/null
+++ b/qca-ssdk/make/.build_number
@@ -0,0 +1 @@
+2
diff --git a/qca-ssdk/make/components.mk b/qca-ssdk/make/components.mk
new file mode 100755
index 0000000..0197065
--- /dev/null
+++ b/qca-ssdk/make/components.mk
@@ -0,0 +1,36 @@
+
+ifeq (linux, $(OS))
+  ifeq (KSLIB, $(MODULE_TYPE))
+    ifeq (TRUE, $(KERNEL_MODE))
+      COMPONENTS = HSL SAL INIT UTIL REF SHELIB
+      ifeq (TRUE, $(FAL))
+        COMPONENTS += FAL ADPT
+      endif
+    else
+      COMPONENTS = HSL SAL INIT REF
+    endif
+
+    ifeq (TRUE, $(UK_IF))
+      COMPONENTS += API
+    endif
+  endif
+  
+  ifeq (USLIB, $(MODULE_TYPE))
+    ifneq (TRUE, $(KERNEL_MODE))
+      COMPONENTS = HSL SAL INIT UTIL REF
+      ifeq (TRUE, $(FAL))
+        COMPONENTS += FAL ADPT
+      endif
+    else
+      COMPONENTS = UK_IF SAL
+    endif
+
+    ifeq (TRUE, $(UK_IF))
+      COMPONENTS += API
+    endif
+  endif
+
+  ifeq (SHELL, $(MODULE_TYPE))
+    COMPONENTS = SHELL
+  endif
+endif
diff --git a/qca-ssdk/make/config.mk b/qca-ssdk/make/config.mk
new file mode 100755
index 0000000..9886b0c
--- /dev/null
+++ b/qca-ssdk/make/config.mk
@@ -0,0 +1,118 @@
+
+include $(PRJ_PATH)/config
+-include $(SYS_PATH)/include/config/auto.conf
+
+ifndef SYS_PATH
+  $(error SYS_PATH isn't defined!)
+endif
+
+ifndef TOOL_PATH
+  $(error TOOL_PATH isn't defined!)
+endif
+
+#define cpu type such as PPC MIPS ARM X86
+ifndef CPU
+  CPU=mips
+endif
+
+#define os type such as linux netbsd vxworks
+ifndef OS
+  OS=linux
+endif
+
+ifndef OS_VER
+  OS_VER=2_6
+endif
+
+#support chip type such as ATHENA GARUDA
+ifndef CHIP_TYPE
+  SUPPORT_CHIP = GARUDA
+else
+  ifeq (GARUDA, $(CHIP_TYPE))
+    SUPPORT_CHIP = GARUDA
+  endif
+
+  ifeq (ATHENA, $(CHIP_TYPE))
+     SUPPORT_CHIP = ATHENA
+  endif
+
+  ifeq (SHIVA, $(CHIP_TYPE))
+     SUPPORT_CHIP = SHIVA
+  endif
+
+  ifeq (HORUS, $(CHIP_TYPE))
+     SUPPORT_CHIP = HORUS
+  endif
+
+  ifeq (ISIS, $(CHIP_TYPE))
+     SUPPORT_CHIP = ISIS
+  endif
+
+  ifeq (ISISC, $(CHIP_TYPE))
+     SUPPORT_CHIP = ISISC
+  endif
+
+  ifeq (DESS, $(CHIP_TYPE))
+     SUPPORT_CHIP = DESS
+  endif
+
+  ifeq (HPPE, $(CHIP_TYPE))
+     SUPPORT_CHIP = HPPE
+  endif
+
+  ifeq (CPPE, $(CHIP_TYPE))
+     SUPPORT_CHIP = HPPE CPPE
+  endif
+
+  ifeq (MP, $(CHIP_TYPE))
+     SUPPORT_CHIP = SCOMPHY MP
+  endif
+
+  ifeq ($(ISISC_ENABLE), enable)
+      SUPPORT_CHIP += ISISC
+  endif
+
+  ifeq (ALL_CHIP, $(CHIP_TYPE))
+     ifneq (TRUE, $(FAL))
+         $(error FAL must be TRUE when CHIP_TYPE is defined as ALL_CHIP!)
+     endif
+     SUPPORT_CHIP = ISIS ISISC SHIVA DESS HPPE CPPE SCOMPHY MP
+  endif
+
+  ifeq (NONHK_CHIP, $(CHIP_TYPE))
+     ifneq (TRUE, $(FAL))
+         $(error FAL must be TRUE when CHIP_TYPE is defined as ALL_CHIP!)
+     endif
+     SUPPORT_CHIP = ISIS ISISC SHIVA DESS
+  endif
+
+  ifndef SUPPORT_CHIP
+    $(error defined CHIP_TYPE isn't supported!)
+  endif
+endif
+
+#define compile tool prefix
+ifndef TOOLPREFIX
+  TOOLPREFIX=$(CPU)-$(OS)-uclibc-
+endif
+
+DEBUG_ON=FALSE
+OPT_FLAG=
+LD_FLAG=
+
+SHELLOBJ=ssdk_sh
+US_MOD=ssdk_us
+KS_MOD=ssdk_ks
+
+ifeq (TRUE, $(KERNEL_MODE))
+  RUNMODE=km
+else
+  RUNMODE=um
+endif
+
+BLD_DIR=$(PRJ_PATH)/build/$(OS)
+BIN_DIR=$(PRJ_PATH)/build/bin
+
+VER=2.0.0
+BUILD_NUMBER=$(shell cat $(PRJ_PATH)/make/.build_number)
+VERSION=$(VER).$(BUILD_NUMBER)
diff --git a/qca-ssdk/make/defs.mk b/qca-ssdk/make/defs.mk
new file mode 100755
index 0000000..7d1c75b
--- /dev/null
+++ b/qca-ssdk/make/defs.mk
@@ -0,0 +1,28 @@
+DST_DIR=$(BLD_DIR)/$(MODULE_TYPE)
+
+SUB_DIR=$(patsubst %/, %, $(dir $(wildcard ./*/Makefile)))
+
+ifeq (,$(findstring $(LIB), $(COMPONENTS)))
+  SRC_LIST=
+endif
+
+SRC_FILE=$(addprefix $(PRJ_PATH)/$(LOC_DIR)/, $(SRC_LIST))
+
+OBJ_LIST=$(SRC_LIST:.c=.o)
+OBJ_FILE=$(addprefix $(DST_DIR)/, $(OBJ_LIST))
+
+DEP_LIST=$(SRC_LIST:.c=.d)
+DEP_FILE=$(addprefix $(DST_DIR)/, $(DEP_LIST))
+
+vpath %.c $(PRJ_PATH)/$(LOC_DIR)
+vpath %.c $(PRJ_PATH)/app/nathelper/linux
+vpath %.c $(PRJ_PATH)/app/nathelper/linux/lib
+vpath %.o $(DST_DIR)
+vpath %.d $(DST_DIR)
+
+DEP_LOOP=$(foreach i, $(SUB_DIR), $(MAKE) -C $(i) dep || exit 1;)
+OBJ_LOOP=$(foreach i, $(SUB_DIR), $(MAKE) -C $(i) obj || exit 1;)
+CLEAN_LOOP=$(foreach i, $(SUB_DIR), $(MAKE) -C $(i) clean;)
+CLEAN_OBJ_LOOP=$(foreach i, $(SUB_DIR), $(MAKE) -C $(i) clean_o;)
+CLEAN_DEP_LOOP=$(foreach i, $(SUB_DIR), $(MAKE) -C $(i) clean_d;)
+
diff --git a/qca-ssdk/make/linux_opt.mk b/qca-ssdk/make/linux_opt.mk
new file mode 100755
index 0000000..81680f8
--- /dev/null
+++ b/qca-ssdk/make/linux_opt.mk
@@ -0,0 +1,702 @@
+MODULE_CFLAG :=
+LOCAL_CFLAGS :=
+
+ifeq (TRUE, $(SWCONFIG))
+  MODULE_CFLAG += -DIN_SWCONFIG
+endif
+
+ifeq (TRUE, $(IN_ACL))
+  MODULE_CFLAG += -DIN_ACL
+endif
+
+ifeq (TRUE, $(IN_FDB))
+  MODULE_CFLAG += -DIN_FDB
+endif
+
+ifeq (TRUE, $(IN_FDB_MINI))
+  MODULE_CFLAG += -DIN_FDB_MINI
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+  MODULE_CFLAG += -DIN_IGMP
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+  MODULE_CFLAG += -DIN_LEAKY
+endif
+
+ifeq (TRUE, $(IN_LED))
+  MODULE_CFLAG += -DIN_LED
+endif
+
+ifeq (TRUE, $(IN_MIB))
+  MODULE_CFLAG += -DIN_MIB
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+  MODULE_CFLAG += -DIN_MIRROR
+endif
+
+ifeq (TRUE, $(IN_MISC))
+  MODULE_CFLAG += -DIN_MISC
+endif
+
+ifeq (TRUE, $(IN_MISC_MINI))
+  MODULE_CFLAG += -DIN_MISC_MINI
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+  MODULE_CFLAG += -DIN_PORTCONTROL
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL_MINI))
+  MODULE_CFLAG += -DIN_PORTCONTROL_MINI
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+  MODULE_CFLAG += -DIN_PORTVLAN
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN_MINI))
+  MODULE_CFLAG += -DIN_PORTVLAN_MINI
+endif
+
+ifeq (TRUE, $(IN_QOS))
+  MODULE_CFLAG += -DIN_QOS
+endif
+
+ifeq (TRUE, $(IN_QOS_MINI))
+  MODULE_CFLAG += -DIN_QOS_MINI
+endif
+
+ifeq (TRUE, $(IN_RATE))
+  MODULE_CFLAG += -DIN_RATE
+endif
+
+ifeq (TRUE, $(IN_STP))
+  MODULE_CFLAG += -DIN_STP
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+  MODULE_CFLAG += -DIN_VLAN
+endif
+
+ifeq (TRUE, $(IN_VLAN_MINI))
+  MODULE_CFLAG += -DIN_VLAN_MINI
+endif
+
+ifeq (TRUE, $(IN_REDUCED_ACL))
+  MODULE_CFLAG += -DIN_REDUCED_ACL
+endif
+
+ifeq (TRUE, $(IN_COSMAP))
+  MODULE_CFLAG += -DIN_COSMAP
+endif
+
+ifeq (TRUE, $(IN_COSMAP_MINI))
+  MODULE_CFLAG += -DIN_COSMAP_MINI
+endif
+
+ifeq (TRUE, $(IN_IP))
+  MODULE_CFLAG += -DIN_IP
+endif
+
+ifeq (TRUE, $(IN_IP_MINI))
+  MODULE_CFLAG += -DIN_IP_MINI
+endif
+
+ifeq (TRUE, $(IN_NAT))
+  MODULE_CFLAG += -DIN_NAT
+endif
+
+ifeq (TRUE, $(IN_FLOW))
+  MODULE_CFLAG += -DIN_FLOW
+endif
+
+ifeq (TRUE, $(IN_FLOW_MINI))
+  MODULE_CFLAG += -DIN_FLOW_MINI
+endif
+
+ifeq (TRUE, $(IN_SFE))
+  MODULE_CFLAG += -DIN_SFE
+endif
+
+ifeq (TRUE, $(IN_TRUNK))
+  MODULE_CFLAG += -DIN_TRUNK
+endif
+
+ifeq (TRUE, $(IN_SEC))
+  MODULE_CFLAG += -DIN_SEC
+endif
+
+ifeq (TRUE, $(IN_QM))
+  MODULE_CFLAG += -DIN_QM
+endif
+
+ifeq (TRUE, $(IN_QM_MINI))
+  MODULE_CFLAG += -DIN_QM_MINI
+endif
+
+ifeq (TRUE, $(IN_NAT_HELPER))
+  MODULE_CFLAG += -DIN_NAT_HELPER
+endif
+
+ifeq (TRUE, $(IN_INTERFACECONTROL))
+  MODULE_CFLAG += -DIN_INTERFACECONTROL
+endif
+
+ifeq (TRUE, $(IN_CTRLPKT))
+  MODULE_CFLAG += -DIN_CTRLPKT
+endif
+
+ifeq (TRUE, $(IN_SERVCODE))
+  MODULE_CFLAG += -DIN_SERVCODE
+endif
+
+ifeq (TRUE, $(IN_RSS_HASH))
+  MODULE_CFLAG += -DIN_RSS_HASH
+endif
+
+ifeq (TRUE, $(IN_MACBLOCK))
+  MODULE_CFLAG += -DIN_MACBLOCK
+endif
+
+ifeq (TRUE, $(IN_RFS))
+  MODULE_CFLAG += -DIN_RFS
+endif
+
+ifeq (TRUE, $(IN_MALIBU_PHY))
+  MODULE_CFLAG += -DIN_MALIBU_PHY
+endif
+ifeq (TRUE, $(IN_AQUANTIA_PHY))
+  MODULE_CFLAG += -DIN_AQUANTIA_PHY
+endif
+
+ifeq (TRUE, $(IN_QCA803X_PHY))
+  MODULE_CFLAG += -DIN_QCA803X_PHY
+endif
+
+ifeq (TRUE, $(IN_QCA808X_PHY))
+  MODULE_CFLAG += -DIN_QCA808X_PHY
+endif
+ifeq (TRUE, $(IN_SFP_PHY))
+  MODULE_CFLAG += -DIN_SFP_PHY
+endif
+
+ifeq (TRUE, $(IN_PHY_I2C_MODE))
+  MODULE_CFLAG += -DIN_PHY_I2C_MODE
+endif
+
+ifeq (TRUE, $(IN_VSI))
+  MODULE_CFLAG += -DIN_VSI
+endif
+
+ifeq (TRUE, $(IN_VSI_MINI))
+  MODULE_CFLAG += -DIN_VSI_MINI
+endif
+
+ifeq (TRUE, $(IN_PPPOE))
+  MODULE_CFLAG += -DIN_PPPOE
+endif
+
+ifeq (TRUE, $(IN_BM))
+  MODULE_CFLAG += -DIN_BM
+endif
+
+ifeq (TRUE, $(IN_BM_MINI))
+  MODULE_CFLAG += -DIN_BM_MINI
+endif
+
+ifeq (TRUE, $(IN_SHAPER))
+  MODULE_CFLAG += -DIN_SHAPER
+endif
+
+ifeq (TRUE, $(IN_SHAPER_MINI))
+  MODULE_CFLAG += -DIN_SHAPER_MINI
+endif
+
+ifeq (TRUE, $(IN_POLICER))
+  MODULE_CFLAG += -DIN_POLICER
+endif
+
+ifeq (TRUE, $(IN_POLICER_MINI))
+  MODULE_CFLAG += -DIN_POLICER_MINI
+endif
+
+ifeq (TRUE, $(IN_UNIPHY))
+  MODULE_CFLAG += -DIN_UNIPHY
+endif
+
+ifeq (TRUE, $(IN_UNIPHY_MINI))
+  MODULE_CFLAG += -DIN_UNIPHY_MINI
+endif
+
+ifeq (TRUE, $(RUMI_EMULATION))
+  MODULE_CFLAG += -DRUMI_EMULATION
+endif
+
+ifeq (TRUE, $(IN_PTP))
+  MODULE_CFLAG += -DIN_PTP
+endif
+
+ifneq (TRUE, $(FAL))
+  MODULE_CFLAG += -DHSL_STANDALONG
+endif
+
+ifeq (TRUE, $(UK_IF))
+  MODULE_CFLAG += -DUK_IF
+endif
+
+#ifdef UK_NL_PROT
+  MODULE_CFLAG += -DUK_NL_PROT=$(UK_NL_PROT)
+#endif
+
+#ifdef UK_MINOR_DEV
+  MODULE_CFLAG += -DUK_MINOR_DEV=$(UK_MINOR_DEV)
+#endif
+
+ifeq (TRUE, $(API_LOCK))
+  MODULE_CFLAG += -DAPI_LOCK
+endif
+
+ifeq (TRUE, $(REG_ACCESS_SPEEDUP))
+  MODULE_CFLAG += -DREG_ACCESS_SPEEDUP
+endif
+
+ifeq (TRUE, $(DEBUG_ON))
+  MODULE_CFLAG += -g
+endif
+
+MODULE_CFLAG += $(OPT_FLAG) -Wall -DVERSION=\"$(VERSION)\" -DBUILD_DATE=\"$(BUILD_DATE)\" -DOS=\"$(OS)\" -D"KBUILD_STR(s)=\#s" -D"KBUILD_MODNAME=KBUILD_STR(qca-ssdk)"
+
+MODULE_CFLAG += -Wno-unused-function
+MODULE_CFLAG += -Wno-missing-attributes
+MODULE_INC += -isystem $(shell $(CC) -print-file-name=include)
+
+MODULE_INC += -I$(PRJ_PATH)/include \
+                   -I$(PRJ_PATH)/include/common \
+                   -I$(PRJ_PATH)/include/api \
+                   -I$(PRJ_PATH)/include/fal \
+                   -I$(PRJ_PATH)/include/ref \
+                   -I$(PRJ_PATH)/include/adpt \
+                   -I$(PRJ_PATH)/include/hsl \
+                   -I$(PRJ_PATH)/include/hsl/phy \
+                   -I$(PRJ_PATH)/include/sal/os \
+		   -I$(PRJ_PATH)/include/sal/os/linux \
+                   -I$(PRJ_PATH)/include/sal/sd \
+                   -I$(PRJ_PATH)/include/sal/sd/linux/hydra_howl \
+                   -I$(PRJ_PATH)/include/sal/sd/linux/uk_interface \
+                   -I$(PRJ_PATH)/include/init
+
+ifneq (,$(findstring ATHENA, $(SUPPORT_CHIP)))
+  MODULE_INC   += -I$(PRJ_PATH)/include/hsl/athena
+  MODULE_CFLAG += -DATHENA
+endif
+
+ifneq (,$(findstring GARUDA, $(SUPPORT_CHIP)))
+  MODULE_INC   += -I$(PRJ_PATH)/include/hsl/garuda
+  MODULE_CFLAG += -DGARUDA
+endif
+
+ifneq (,$(findstring SHIVA, $(SUPPORT_CHIP)))
+  MODULE_INC   += -I$(PRJ_PATH)/include/hsl/shiva
+  MODULE_CFLAG += -DSHIVA
+endif
+
+ifneq (,$(findstring HORUS, $(SUPPORT_CHIP)))
+  MODULE_INC   += -I$(PRJ_PATH)/include/hsl/horus
+  MODULE_CFLAG += -DHORUS
+endif
+
+ifneq (,$(filter ISIS, $(SUPPORT_CHIP)))
+     MODULE_INC   += -I$(PRJ_PATH)/include/hsl/isis
+     MODULE_CFLAG += -DISIS
+endif
+
+ifneq (,$(findstring ISISC, $(SUPPORT_CHIP)))
+  MODULE_INC   += -I$(PRJ_PATH)/include/hsl/isisc
+  MODULE_CFLAG += -DISISC
+endif
+
+ifneq (,$(findstring DESS, $(SUPPORT_CHIP)))
+  MODULE_INC   += -I$(PRJ_PATH)/include/hsl/dess
+  MODULE_CFLAG += -DDESS
+endif
+
+ifneq (,$(findstring HPPE, $(SUPPORT_CHIP)))
+  MODULE_INC   += -I$(PRJ_PATH)/include/hsl/hppe
+  MODULE_INC   += -I$(PRJ_PATH)/include/adpt/hppe
+  MODULE_CFLAG += -DHPPE
+endif
+
+ifneq (,$(filter MP, $(SUPPORT_CHIP)))
+  MODULE_INC   += -I$(PRJ_PATH)/include/hsl/hppe
+  MODULE_INC   += -I$(PRJ_PATH)/include/adpt/mp
+  MODULE_INC   += -I$(PRJ_PATH)/include/hsl/mp
+  MODULE_CFLAG += -DMP
+endif
+
+ifneq (,$(findstring CPPE, $(SUPPORT_CHIP)))
+  MODULE_INC   += -I$(PRJ_PATH)/include/hsl/cppe
+  MODULE_INC   += -I$(PRJ_PATH)/include/adpt/cppe
+  MODULE_CFLAG += -DCPPE
+endif
+
+
+ifneq (,$(findstring SCOMPHY, $(SUPPORT_CHIP)))
+  MODULE_INC   += -I$(PRJ_PATH)/include/hsl/scomphy
+  MODULE_CFLAG += -DSCOMPHY
+endif
+
+ifeq (TRUE, $(IN_SFP))
+  MODULE_INC   += -I$(PRJ_PATH)/include/hsl/sfp
+  MODULE_INC   += -I$(PRJ_PATH)/include/adpt/sfp
+  MODULE_CFLAG += -DIN_SFP
+endif
+
+# check for GCC version
+ifeq (4, $(GCC_VER))
+  MODULE_CFLAG += -DGCCV4
+endif
+
+ifeq (TRUE, $(IN_PTP))
+ifeq ($(CONFIG_PTP_1588_CLOCK), y)
+	MODULE_CFLAG += -DIN_LINUX_STD_PTP
+endif
+endif
+
+ifeq (KSLIB, $(MODULE_TYPE))
+
+  MODULE_INC += -I$(PRJ_PATH)/include/shell_lib
+  ifndef TARGET_NAME
+	TARGET_NAME=arm-openwrt-linux-$(TARGET_SUFFIX)
+  endif
+
+  ifeq ($(CONFIG_KASAN_INLINE),y)
+        CALL_THRESHOLD=10000
+  else
+        CALL_THRESHOLD=0
+  endif
+  ifneq ($(CONFIG_KASAN_SHADOW_OFFSET),)
+        SHADOW_OFFSET=$(CONFIG_KASAN_SHADOW_OFFSET)
+  else
+        SHADOW_OFFSET=0xdfffff9000000000
+  endif
+  KASAN_OPTION=-fsanitize=kernel-address -fasan-shadow-offset=$(SHADOW_OFFSET) \
+               --param asan-stack=1 --param asan-globals=1 \
+               --param asan-instrumentation-with-call-threshold=$(CALL_THRESHOLD)
+
+  ifeq ($(CONFIG_KASAN_SW_TAGS), y)
+      KASAN_SHADOW_SCALE_SHIFT := 4
+  else
+      KASAN_SHADOW_SCALE_SHIFT := 3
+  endif
+
+  ifeq (5_4, $(OS_VER))
+      ifeq ($(ARCH), arm64)
+          KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT)
+       endif
+  endif
+  ifeq ($(CONFIG_KASAN),y)
+      MODULE_CFLAG += $(KASAN_OPTION)
+  endif
+
+  ifeq (3_18, $(OS_VER))
+		MODULE_CFLAG += -DKVER34
+		MODULE_CFLAG += -DKVER32
+	    MODULE_CFLAG += -DLNX26_22
+	    MODULE_INC += -I$(SYS_PATH) \
+                  -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \
+	          -I$(SYS_PATH)/include \
+              -I$(SYS_PATH)/source/include \
+              -I$(SYS_PATH)/source/arch/arm/mach-msm/include \
+              -I$(SYS_PATH)/arch/arm/mach-msm/include \
+              -I$(SYS_PATH)/source/arch/arm/include \
+              -I$(SYS_PATH)/arch/arm/include \
+              -I$(SYS_PATH)/source/arch/arm/include/asm \
+              -I$(SYS_PATH)/arch/arm/include/generated \
+              -I$(SYS_PATH)/include/generated/uapi \
+              -I$(SYS_PATH)/include/uapi \
+              -I$(SYS_PATH)/arch/arm/include/uapi \
+              -I$(SYS_PATH)/source/arch/arm/include/asm/mach \
+	          -include $(SYS_PATH)/include/linux/kconfig.h
+
+  endif
+
+  ifeq ($(OS_VER),$(filter 4_4 5_4, $(OS_VER)))
+                MODULE_CFLAG += -DKVER34
+                MODULE_CFLAG += -DKVER32
+            MODULE_CFLAG += -DLNX26_22
+	    ifeq ($(ARCH), arm64)
+            MODULE_INC += -I$(SYS_PATH) \
+                  -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \
+                  -I$(SYS_PATH)/include \
+              -I$(SYS_PATH)/source \
+              -I$(SYS_PATH)/source/include \
+	      -I$(SYS_PATH)/source/arch/arm64/mach-msm/include \
+              -I$(SYS_PATH)/arch/arm64/mach-msm/include \
+              -I$(SYS_PATH)/source/arch/arm64/include \
+              -I$(SYS_PATH)/arch/arm64/include \
+              -I$(SYS_PATH)/source/arch/arm64/include/asm \
+              -I$(SYS_PATH)/arch/arm64/include/generated \
+              -I$(SYS_PATH)/include/generated/uapi \
+              -I$(SYS_PATH)/include/uapi \
+              -I$(SYS_PATH)/arch/arm64/include/uapi \
+              -I$(SYS_PATH)/source/arch/arm64/include/asm/mach
+
+	      ifneq ($(wildcard $(SYS_PATH)/include/linux/kconfig.h),)
+	          MODULE_INC += -include $(SYS_PATH)/include/linux/kconfig.h
+	      else
+	          MODULE_INC += -include $(KERNEL_SRC)/include/linux/kconfig.h
+	      endif
+
+	    else ifeq ($(ARCH), arm)
+	    MODULE_INC += -I$(SYS_PATH) \
+              -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \
+	      -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/7.5.0/include/ \
+              -I$(TOOL_PATH)/../../lib/armv7a-vfp-neon-rdk-linux-gnueabi/gcc/arm-rdk-linux-gnueabi/4.8.4/include/ \
+	      -I$(TOOL_PATH)/../../lib/arm-rdk-linux-musleabi/gcc/arm-rdk-linux-musleabi/6.4.0/include/ \
+              -I$(SYS_PATH)/include \
+              -I$(SYS_PATH)/source \
+              -I$(SYS_PATH)/source/include \
+              -I$(SYS_PATH)/source/arch/arm/mach-msm/include \
+              -I$(SYS_PATH)/arch/arm/mach-msm/include \
+              -I$(SYS_PATH)/source/arch/arm/include \
+              -I$(SYS_PATH)/arch/arm/include \
+              -I$(SYS_PATH)/source/arch/arm/include/asm \
+              -I$(SYS_PATH)/arch/arm/include/generated \
+	      -I$(SYS_PATH)/arch/arm/include/generated/uapi \
+	      -I$(SYS_PATH)/source/include/uapi \
+              -I$(SYS_PATH)/include/generated/uapi \
+              -I$(SYS_PATH)/include/uapi \
+              -I$(SYS_PATH)/arch/arm/include/uapi \
+              -I$(SYS_PATH)/source/arch/arm/include/asm/mach
+
+	      ifneq ($(wildcard $(SYS_PATH)/include/linux/kconfig.h),)
+	          MODULE_INC += -include $(SYS_PATH)/include/linux/kconfig.h
+	      else
+	          MODULE_INC += -include $(KERNEL_SRC)/include/linux/kconfig.h
+	      endif
+
+            else
+            MODULE_INC += -I$(SYS_PATH) \
+              -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \
+              -I$(SYS_PATH)/include \
+              -I$(SYS_PATH)/source \
+	      -I$(SYS_PATH)/source/include \
+              -I$(SYS_PATH)/source/arch/mips/mach-msm/include \
+	      -I$(SYS_PATH)/arch/mips/mach-msm/include \
+	      -I$(SYS_PATH)/source/arch/mips/include \
+              -I$(SYS_PATH)/arch/mips/include \
+	      -I$(SYS_PATH)/source/arch/mips/include/asm \
+	      -I$(SYS_PATH)/arch/mips/include/generated \
+              -I$(SYS_PATH)/include/generated/uapi \
+	      -I$(SYS_PATH)/include/uapi \
+	      -I$(SYS_PATH)/arch/mips/include/uapi \
+	      -I$(SYS_PATH)/source/arch/mips/include/asm/mach \
+	      -include $(SYS_PATH)/include/linux/kconfig.h \
+              -I$(SYS_PATH)/arch/mips/include/asm/mach-ar7240 \
+              -I$(SYS_PATH)/arch/mips/include/asm/mach-generic \
+              -I$(SYS_PATH)/arch/mips/include/asm/mach-ar7 \
+              -I$(SYS_PATH)/usr/include
+
+	    #CPU_CFLAG    = -G 0 -mno-abicalls -fno-pic -pipe -mabi=32 -march=mips32r2
+            ifndef CPU_CFLAG
+            CPU_CFLAG    = -Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing \
+			-O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB
+            endif
+            endif
+
+  endif
+
+  ifeq ($(OS_VER),$(filter 4_9 4_1, $(OS_VER)))
+                MODULE_CFLAG += -DKVER34
+                MODULE_CFLAG += -DKVER32
+            MODULE_CFLAG += -DLNX26_22
+	    ifeq ($(ARCH), arm64)
+	    KCONF_FILE = $(SYS_PATH)/source/include/linux/kconfig.h
+            MODULE_INC += -I$(SYS_PATH) \
+                  -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \
+                  -I$(SYS_PATH)/include \
+              -I$(SYS_PATH)/source/include \
+	      -I$(SYS_PATH)/source/arch/arm64/mach-msm/include \
+              -I$(SYS_PATH)/arch/arm64/mach-msm/include \
+              -I$(SYS_PATH)/source/arch/arm64/include \
+              -I$(SYS_PATH)/arch/arm64/include \
+              -I$(SYS_PATH)/source/arch/arm64/include/asm \
+              -I$(SYS_PATH)/arch/arm64/include/generated \
+              -I$(SYS_PATH)/include/generated/uapi \
+              -I$(SYS_PATH)/include/uapi \
+              -I$(SYS_PATH)/arch/arm64/include/uapi \
+	      -I$(SYS_PATH)/source/include/uapi \
+              -I$(SYS_PATH)/source/arch/arm64/include/asm/mach \
+	      -include $(KCONF_FILE)
+	    else ifeq ($(ARCH), arm)
+	    MODULE_INC += -I$(SYS_PATH) \
+              -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \
+              -I$(TOOL_PATH)/../../lib/armv7a-vfp-neon-rdk-linux-gnueabi/gcc/arm-rdk-linux-gnueabi/4.8.4/include/ \
+              -I$(SYS_PATH)/include \
+              -I$(SYS_PATH)/source/include \
+              -I$(SYS_PATH)/source/arch/arm/mach-msm/include \
+              -I$(SYS_PATH)/arch/arm/mach-msm/include \
+              -I$(SYS_PATH)/source/arch/arm/include \
+              -I$(SYS_PATH)/arch/arm/include \
+              -I$(SYS_PATH)/source/arch/arm/include/asm \
+              -I$(SYS_PATH)/arch/arm/include/generated \
+              -I$(SYS_PATH)/include/generated/uapi \
+              -I$(SYS_PATH)/include/uapi \
+              -I$(SYS_PATH)/arch/arm/include/uapi \
+              -I$(SYS_PATH)/source/arch/arm/include/asm/mach \
+	          -include $(SYS_PATH)/include/linux/kconfig.h
+	    endif
+  endif
+
+  ifeq (3_14, $(OS_VER))
+		MODULE_CFLAG += -DKVER34
+		MODULE_CFLAG += -DKVER32
+	    MODULE_CFLAG += -DLNX26_22
+	    MODULE_INC += -I$(SYS_PATH) \
+                  -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \
+		  -I$(TOOL_PATH)/../../lib/arm-poky-linux-gnueabi/gcc/arm-poky-linux-gnueabi/5.3.0/include/ \
+		  -I$(TOOL_PATH)/../../lib/armv7a-vfp-neon-rdk-linux-gnueabi/gcc/arm-rdk-linux-gnueabi/4.8.4/include/ \
+	          -I$(SYS_PATH)/include \
+              -I$(SYS_PATH)/source/ \
+              -I$(SYS_PATH)/source/include \
+              -I$(SYS_PATH)/source/arch/arm/mach-msm/include \
+              -I$(SYS_PATH)/arch/arm/mach-msm/include \
+              -I$(SYS_PATH)/source/arch/arm/include \
+              -I$(SYS_PATH)/arch/arm/include \
+              -I$(SYS_PATH)/source/arch/arm/include/asm \
+              -I$(SYS_PATH)/arch/arm/include/generated \
+              -I$(SYS_PATH)/include/generated/uapi \
+              -I$(SYS_PATH)/include/uapi \
+              -I$(SYS_PATH)/source/include/uapi \
+              -I$(SYS_PATH)/source/include/generated \
+              -I$(SYS_PATH)/include/genearted \
+              -I$(SYS_PATH)/arch/arm/include/uapi \
+              -I$(SYS_PATH)/source/arch/arm/include/uapi \
+              -I$(EXT_PATH) \
+              -I$(SYS_PATH)/source/arch/arm/include/asm/mach
+	ifneq ($(wildcard $(SYS_PATH)/include/linux/kconfig.h),)
+		MODULE_INC += \
+			-include $(SYS_PATH)/include/linux/kconfig.h
+	else
+		MODULE_INC += \
+			-include $(SYS_PATH)/source/include/linux/kconfig.h
+	endif
+
+  endif
+
+  ifeq (3_4, $(OS_VER))
+		MODULE_CFLAG += -DKVER34
+		MODULE_CFLAG += -DKVER32
+	    MODULE_CFLAG += -DLNX26_22
+	    MODULE_CFLAG += -Werror
+	    MODULE_INC += -I$(SYS_PATH) \
+	          -I$(SYS_PATH)/include \
+              -I$(SYS_PATH)/source/include \
+              -I$(SYS_PATH)/source/arch/arm/mach-msm/include \
+              -I$(SYS_PATH)/source/arch/arm/include \
+              -I$(SYS_PATH)/source/arch/arm/include/asm \
+              -I$(SYS_PATH)/arch/arm/include/generated \
+              -I$(SYS_PATH)/source/arch/arm/include/asm/mach \
+	      -I$(SYS_PATH)/usr/include
+
+  endif
+
+  ifeq (3_2, $(OS_VER))
+	MODULE_CFLAG += -DKVER32
+	MODULE_CFLAG += -DLNX26_22
+	ifeq (mips, $(CPU))
+	  MODULE_INC += -I$(SYS_PATH) \
+            -I$(SYS_PATH)/include \
+            -I$(SYS_PATH)/arch/mips/include \
+	    -I$(SYS_PATH)/arch/mips/include/asm/mach-ar7240 \
+	    -I$(SYS_PATH)/arch/mips/include/asm/mach-generic \
+		-I$(SYS_PATH)/arch/mips/include/asm/mach-ar7 \
+	    -I$(SYS_PATH)/usr/include \
+	    -I${KERN_SRC_PATH} \
+            -I${KERN_SRC_PATH}/include \
+            -I$(KERN_SRC_PATH)/arch/mips/include \
+            -I$(KERN_SRC_PATH)/arch/mips/include/asm/mach-ar7240 \
+            -I$(KERN_SRC_PATH)/arch/mips/include/asm/mach-generic \
+            -I$(KERN_SRC_PATH)/arch/mips/include/asm/mach-ar7 \
+            -I$(KERN_SRC_PATH)/usr/include
+
+	    #CPU_CFLAG    = -G 0 -mno-abicalls -fno-pic -pipe -mabi=32 -march=mips32r2
+          ifndef CPU_CFLAG
+	    CPU_CFLAG    = -Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing \
+                     -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB
+          endif
+    else
+	    MODULE_INC += -I$(SYS_PATH) \
+              -I$(SYS_PATH)/include \
+              -I$(SYS_PATH)/arch/arm/include \
+              -I$(SYS_PATH)/arch/arm/include/asm \
+              -I$(SYS_PATH)/arch/arm/mach-fv16xx/include \
+	      -I$(SYS_PATH)/arch/arm/include/generated \
+	      -I$(SYS_PATH)/include/generated \
+	      -I$(SYS_PATH)/usr/include
+        endif
+
+
+  endif
+
+  ifeq (2_6, $(OS_VER))
+        MODULE_CFLAG += -DKVER26
+        MODULE_CFLAG += -DLNX26_22
+        ifeq (mips, $(CPU))
+          MODULE_INC += -I$(SYS_PATH) \
+            -I$(SYS_PATH)/include \
+            -I$(SYS_PATH)/arch/mips/include \
+            -I$(SYS_PATH)/arch/mips/include/asm/mach-ar7240 \
+            -I$(SYS_PATH)/arch/mips/include/asm/mach-generic \
+            -I$(SYS_PATH)/usr/include
+
+            #CPU_CFLAG    = -G 0 -mno-abicalls -fno-pic -pipe -mabi=32 -march=mips32r2
+          ifndef CPU_CFLAG
+            CPU_CFLAG    = -Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing \
+                     -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB
+          endif
+        else
+	    MODULE_INC += -I$(SYS_PATH) \
+              -I$(SYS_PATH)/include \
+              -I$(SYS_PATH)/arch/arm/include \
+              -I$(SYS_PATH)/arch/arm/include/asm \
+              -I$(SYS_PATH)/arch/arm/mach-fv16xx/include \
+	      -I$(SYS_PATH)/arch/arm/include/generated \
+	      -I$(SYS_PATH)/include/generated \
+	      -I$(SYS_PATH)/usr/include
+        endif
+
+
+  endif
+
+  MODULE_CFLAG += -D__KERNEL__ -DKERNEL_MODULE $(CPU_CFLAG)
+
+
+endif
+
+ifeq (SHELL, $(MODULE_TYPE))
+  MODULE_INC += -I$(PRJ_PATH)/include/shell
+
+    ifeq (2_6, $(OS_VER))
+  	  MODULE_CFLAG += -DKVER26
+    else
+   	  MODULE_CFLAG += -DKVER24
+    endif
+
+    ifeq (TRUE, $(KERNEL_MODE))
+      MODULE_CFLAG += -static
+    else
+      MODULE_CFLAG += -static -DUSER_MODE
+    endif
+endif
+
+ifneq (TRUE, $(KERNEL_MODE))
+  ifneq (SHELL, $(MODULE_TYPE))
+    MODULE_CFLAG +=  -DUSER_MODE
+  endif
+endif
+
+LOCAL_CFLAGS += $(MODULE_INC) $(MODULE_CFLAG) $(EXTRA_CFLAGS)
diff --git a/qca-ssdk/make/target.mk b/qca-ssdk/make/target.mk
new file mode 100755
index 0000000..dd982bb
--- /dev/null
+++ b/qca-ssdk/make/target.mk
@@ -0,0 +1,48 @@
+
+include $(PRJ_PATH)/make/$(OS)_opt.mk
+
+include $(PRJ_PATH)/make/tools.mk
+
+obj: $(OBJ_LIST)
+	$(OBJ_LOOP)
+
+dep: build_dir $(DEP_LIST)
+	$(DEP_LOOP)
+
+$(OBJ_LIST): %.o : %.c %.d
+	$(CC) $(CFLAGS) $(LOCAL_CFLAGS) -c $< -o $(DST_DIR)/$@
+
+$(DEP_LIST) : %.d : %.c
+	$(CC) $(CFLAGS) $(LOCAL_CFLAGS) -MM $< > $(DST_DIR)/$@.tmp
+	sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $(DST_DIR)/$@.tmp > $(DST_DIR)/$@
+
+build_dir: $(DST_DIR)
+
+$(DST_DIR):
+	$(MKDIR) -p $(DST_DIR)
+
+.PHONY: clean
+clean: clean_o clean_d
+	$(CLEAN_LOOP)
+
+.PHONY: clean_o
+clean_o: clean_obj
+	$(CLEAN_OBJ_LOOP)
+
+.PHONY: clean_d
+clean_d: clean_dep
+	$(CLEAN_DEP_LOOP)
+
+clean_obj:
+ifneq (,$(word 1, $(OBJ_FILE)))
+	$(RM) -f $(OBJ_FILE)
+endif
+
+clean_dep:
+ifneq (,$(word 1, $(DEP_FILE)))
+	$(RM) -f $(DEP_FILE)
+endif
+
+ifneq (,$(word 1, $(DEP_FILE)))
+  sinclude $(DEP_FILE)
+endif	
diff --git a/qca-ssdk/make/tools.mk b/qca-ssdk/make/tools.mk
new file mode 100755
index 0000000..d6f6232
--- /dev/null
+++ b/qca-ssdk/make/tools.mk
@@ -0,0 +1,12 @@
+
+ifeq (linux, $(OS))
+  CC=$(TOOL_PATH)/$(TOOLPREFIX)gcc
+  AR=$(TOOL_PATH)/$(TOOLPREFIX)ar
+  LD?=$(TOOL_PATH)/$(TOOLPREFIX)ld
+  STRIP=$(TOOL_PATH)/$(TOOLPREFIX)strip
+  MAKE=make -S
+  CP=cp
+  MKDIR=mkdir
+  RM=rm
+  PERL=perl
+endif
diff --git a/qca-ssdk/src/adpt/Makefile b/qca-ssdk/src/adpt/Makefile
new file mode 100755
index 0000000..de3c0c0
--- /dev/null
+++ b/qca-ssdk/src/adpt/Makefile
@@ -0,0 +1,12 @@
+LOC_DIR=/src/adpt
+LIB=ADPT
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=adpt.c
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/adpt/adpt.c b/qca-ssdk/src/adpt/adpt.c
new file mode 100644
index 0000000..c0924d8
--- /dev/null
+++ b/qca-ssdk/src/adpt/adpt.c
@@ -0,0 +1,658 @@
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "adpt.h"
+#include "ssdk_init.h"
+#if defined(HPPE)
+#include "adpt_hppe.h"
+#endif
+#if defined(IN_SFP)
+#include "adpt_sfp.h"
+#endif
+#if defined(MP)
+#include "adpt_mp.h"
+#endif
+#include "hsl_phy.h"
+
+adpt_api_t *g_adpt_api[SW_MAX_NR_DEV] = {NULL};
+
+adpt_chip_ver_t g_chip_ver[SW_MAX_NR_DEV] = {{0}};
+
+adpt_api_t *adpt_api_ptr_get(a_uint32_t dev_id)
+{
+	if (dev_id >= SW_MAX_NR_DEV)
+		return NULL;
+
+	return g_adpt_api[dev_id];
+}
+#if defined (SCOMPHY)
+a_uint32_t adapt_scomphy_revision_get(a_uint32_t dev_id)
+{
+	return g_chip_ver[dev_id].chip_revision;
+}
+#endif
+#if defined(HPPE)
+a_uint32_t adpt_hppe_chip_revision_get(a_uint32_t dev_id)
+{
+	return g_chip_ver[dev_id].chip_revision;
+}
+
+static sw_error_t adpt_hppe_module_func_register(a_uint32_t dev_id, a_uint32_t module)
+{
+	sw_error_t rv= SW_OK;
+
+	switch (module)
+	{
+		case FAL_MODULE_ACL:
+#if defined(IN_ACL)
+			rv = adpt_hppe_acl_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_VSI:
+#if defined(IN_VSI)
+			rv = adpt_hppe_vsi_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_IP:
+#if defined(IN_IP)
+			rv = adpt_hppe_ip_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_FLOW:
+#if defined(IN_FLOW)
+			rv = adpt_hppe_flow_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_QM:
+#if defined(IN_QM)
+			rv = adpt_hppe_qm_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_QOS:
+#if defined(IN_QOS)
+			rv = adpt_hppe_qos_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_BM:
+#if defined(IN_BM)
+			rv = adpt_hppe_bm_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_SERVCODE:
+#if defined(IN_SERVCODE)
+			rv = adpt_hppe_servcode_init( dev_id);
+#endif
+			break;
+		case FAL_MODULE_RSS_HASH:
+#if defined(IN_RSS_HASH)
+			rv = adpt_hppe_rss_hash_init( dev_id);
+#endif
+			break;
+		case FAL_MODULE_PPPOE:
+#if defined(IN_PPPOE)
+			rv = adpt_hppe_pppoe_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_PORTCTRL:
+#if defined(IN_PORTCONTROL)
+			rv = adpt_hppe_port_ctrl_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_SHAPER:
+#if defined(IN_SHAPER)
+			rv = adpt_hppe_shaper_init( dev_id);
+#endif
+			break;
+		case FAL_MODULE_MIB:
+#if defined(IN_MIB)
+			rv = adpt_hppe_mib_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_MIRROR:
+#if defined(IN_MIRROR)
+			rv = adpt_hppe_mirror_init( dev_id);
+#endif
+			break;
+		case FAL_MODULE_FDB:
+#if defined(IN_FDB)
+			rv = adpt_hppe_fdb_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_STP:
+#if defined(IN_STP)
+			rv = adpt_hppe_stp_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_TRUNK:
+#if defined(IN_TRUNK)
+			rv = adpt_hppe_trunk_init( dev_id);
+#endif
+			break;
+		case FAL_MODULE_PORTVLAN:
+#if defined(IN_PORTVLAN)
+			rv = adpt_hppe_portvlan_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_CTRLPKT:
+#if defined(IN_CTRLPKT)
+			rv = adpt_hppe_ctrlpkt_init( dev_id);
+#endif
+			break;
+		case FAL_MODULE_SEC:
+#if defined(IN_SEC)
+			rv = adpt_hppe_sec_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_POLICER:
+#if defined(IN_POLICER)
+			rv = adpt_hppe_policer_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_MISC:
+#if defined(IN_MISC)
+			rv = adpt_hppe_misc_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_PTP:
+#if defined(IN_PTP)
+			rv = adpt_hppe_ptp_init(dev_id);
+#endif
+			break;
+		case FAL_MODULE_SFP:
+#if defined(IN_SFP)
+			rv = adpt_sfp_init(dev_id);
+#endif
+			break;
+		default:
+			break;
+	}
+
+	return rv;
+}
+#endif
+
+sw_error_t adpt_module_func_ctrl_set(a_uint32_t dev_id,
+		a_uint32_t module, fal_func_ctrl_t *func_ctrl)
+{
+	sw_error_t rv= SW_OK;
+
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	if(module == FAL_MODULE_ACL){
+		p_adpt_api->adpt_acl_func_bitmap = func_ctrl->bitmap[0];
+	} else if (module == FAL_MODULE_VSI) {
+		p_adpt_api->adpt_vsi_func_bitmap = func_ctrl->bitmap[0];
+	}else if (module == FAL_MODULE_IP) {
+		p_adpt_api->adpt_ip_func_bitmap[0] = func_ctrl->bitmap[0];
+		p_adpt_api->adpt_ip_func_bitmap[1] = func_ctrl->bitmap[1];
+	} else if (module == FAL_MODULE_FLOW) {
+		p_adpt_api->adpt_flow_func_bitmap = func_ctrl->bitmap[0];
+	} else if (module == FAL_MODULE_QM) {
+		p_adpt_api->adpt_qm_func_bitmap[0] = func_ctrl->bitmap[0];
+		p_adpt_api->adpt_qm_func_bitmap[1] = func_ctrl->bitmap[1];
+	} else if (module == FAL_MODULE_QOS) {
+		p_adpt_api->adpt_qos_func_bitmap = func_ctrl->bitmap[0];
+	} else if (module == FAL_MODULE_BM) {
+		p_adpt_api->adpt_bm_func_bitmap = func_ctrl->bitmap[0];
+	} else if (module == FAL_MODULE_SERVCODE) {
+		p_adpt_api->adpt_servcode_func_bitmap = func_ctrl->bitmap[0];
+	} else if (module == FAL_MODULE_RSS_HASH) {
+		p_adpt_api->adpt_rss_hash_func_bitmap = func_ctrl->bitmap[0];
+	} else if (module == FAL_MODULE_PPPOE) {
+		p_adpt_api->adpt_pppoe_func_bitmap = func_ctrl->bitmap[0];
+	} else if (module == FAL_MODULE_PORTCTRL) {
+		p_adpt_api->adpt_port_ctrl_func_bitmap[0] = func_ctrl->bitmap[0];
+		p_adpt_api->adpt_port_ctrl_func_bitmap[1] = func_ctrl->bitmap[1];
+		p_adpt_api->adpt_port_ctrl_func_bitmap[2] = func_ctrl->bitmap[2];
+	} else if (module == FAL_MODULE_SHAPER) {
+		p_adpt_api->adpt_shaper_func_bitmap = func_ctrl->bitmap[0];
+	} else if(module == FAL_MODULE_MIB){
+		p_adpt_api->adpt_mib_func_bitmap = func_ctrl->bitmap[0];
+	} else if(module == FAL_MODULE_MIRROR){
+		p_adpt_api->adpt_mirror_func_bitmap = func_ctrl->bitmap[0];
+	} else if(module == FAL_MODULE_FDB){
+		p_adpt_api->adpt_fdb_func_bitmap[0] = func_ctrl->bitmap[0];
+		p_adpt_api->adpt_fdb_func_bitmap[1] = func_ctrl->bitmap[1];
+	} else if(module == FAL_MODULE_STP){
+		p_adpt_api->adpt_stp_func_bitmap = func_ctrl->bitmap[0];
+	} else if(module == FAL_MODULE_TRUNK){
+		p_adpt_api->adpt_trunk_func_bitmap = func_ctrl->bitmap[0];
+	} else if(module == FAL_MODULE_PORTVLAN){
+		p_adpt_api->adpt_portvlan_func_bitmap[0] = func_ctrl->bitmap[0];
+		p_adpt_api->adpt_portvlan_func_bitmap[1] = func_ctrl->bitmap[1];
+	} else if(module == FAL_MODULE_CTRLPKT){
+		p_adpt_api->adpt_ctrlpkt_func_bitmap = func_ctrl->bitmap[0];
+	} else if(module == FAL_MODULE_SEC){
+		p_adpt_api->adpt_sec_func_bitmap = func_ctrl->bitmap[0];
+	} else if(module == FAL_MODULE_POLICER){
+		p_adpt_api->adpt_policer_func_bitmap = func_ctrl->bitmap[0];
+	}
+
+
+	switch (g_chip_ver[dev_id].chip_type)
+	{
+		#if defined(HPPE)
+		case CHIP_HPPE:
+			rv = adpt_hppe_module_func_register(dev_id, module);
+			break;
+		#endif
+		default:
+			break;
+	}
+
+	return rv;
+}
+
+sw_error_t adpt_module_func_ctrl_get(a_uint32_t dev_id,
+		a_uint32_t module, fal_func_ctrl_t *func_ctrl)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	if(module == FAL_MODULE_ACL){
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_acl_func_bitmap;
+	} else if (module == FAL_MODULE_VSI) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_vsi_func_bitmap;
+	} else if (module == FAL_MODULE_IP) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_ip_func_bitmap[0];
+		func_ctrl->bitmap[1] = p_adpt_api->adpt_ip_func_bitmap[1];
+	} else if (module == FAL_MODULE_FLOW) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_flow_func_bitmap;
+	} else if (module == FAL_MODULE_QM) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_qm_func_bitmap[0];
+		func_ctrl->bitmap[1] = p_adpt_api->adpt_qm_func_bitmap[1];
+	} else if (module == FAL_MODULE_QOS) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_qos_func_bitmap;
+	} else if (module == FAL_MODULE_BM) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_bm_func_bitmap;
+	} else if (module == FAL_MODULE_SERVCODE) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_servcode_func_bitmap;
+	} else if (module == FAL_MODULE_RSS_HASH) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_rss_hash_func_bitmap;
+	} else if (module == FAL_MODULE_PPPOE) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_pppoe_func_bitmap;
+	} else if (module == FAL_MODULE_PORTCTRL) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_port_ctrl_func_bitmap[0];
+		func_ctrl->bitmap[1] = p_adpt_api->adpt_port_ctrl_func_bitmap[1];
+		func_ctrl->bitmap[2] = p_adpt_api->adpt_port_ctrl_func_bitmap[2];
+	} else if (module == FAL_MODULE_SHAPER) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_shaper_func_bitmap;
+	} else if(module == FAL_MODULE_MIB) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_mib_func_bitmap;
+	} else if(module == FAL_MODULE_MIRROR) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_mirror_func_bitmap;
+	} else if(module == FAL_MODULE_FDB) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_fdb_func_bitmap[0];
+		func_ctrl->bitmap[1] = p_adpt_api->adpt_fdb_func_bitmap[1];
+	} else if(module == FAL_MODULE_STP) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_stp_func_bitmap;
+	} else if(module == FAL_MODULE_TRUNK) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_trunk_func_bitmap;
+	} else if(module == FAL_MODULE_PORTVLAN) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_portvlan_func_bitmap[0];
+		func_ctrl->bitmap[1] = p_adpt_api->adpt_portvlan_func_bitmap[1];
+	} else if(module == FAL_MODULE_CTRLPKT) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_ctrlpkt_func_bitmap;
+	} else if(module == FAL_MODULE_SEC) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_sec_func_bitmap;
+	} else if(module == FAL_MODULE_POLICER) {
+		func_ctrl->bitmap[0] = p_adpt_api->adpt_policer_func_bitmap;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t adpt_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+	sw_error_t rv= SW_OK;
+
+	switch (cfg->chip_type)
+	{
+#if defined(HPPE)
+		case CHIP_HPPE:
+			g_adpt_api[dev_id] = aos_mem_alloc(sizeof(adpt_api_t));
+			if(g_adpt_api[dev_id] == NULL)
+			{
+				printk("%s, %d:malloc fail for adpt api\n", __FUNCTION__, __LINE__);
+				return SW_FAIL;
+			}
+			aos_mem_zero(g_adpt_api[dev_id], sizeof(adpt_api_t));
+
+			g_chip_ver[dev_id].chip_type = cfg->chip_type;
+			g_chip_ver[dev_id].chip_revision = cfg->chip_revision;
+			g_adpt_api[dev_id]->adpt_mirror_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_MIRROR);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_fdb_func_bitmap[0] = 0xffffffff;
+			g_adpt_api[dev_id]->adpt_fdb_func_bitmap[1] = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_FDB);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_stp_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_STP);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_trunk_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_TRUNK);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_portvlan_func_bitmap[0] = 0xffffffff;
+			g_adpt_api[dev_id]->adpt_portvlan_func_bitmap[1] = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_PORTVLAN);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_ctrlpkt_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_CTRLPKT);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_sec_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_SEC);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_acl_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_ACL);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_vsi_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_VSI);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_ip_func_bitmap[0] = 0xffffffff;
+			g_adpt_api[dev_id]->adpt_ip_func_bitmap[1] = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_IP);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_flow_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_FLOW);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_qm_func_bitmap[0] = 0xffffffff;
+			g_adpt_api[dev_id]->adpt_qm_func_bitmap[1] = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_QM);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_qos_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_QOS);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_bm_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_BM);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_servcode_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_SERVCODE);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_rss_hash_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_RSS_HASH);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_pppoe_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_PPPOE);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_port_ctrl_func_bitmap[0] = 0xffffffff;
+			g_adpt_api[dev_id]->adpt_port_ctrl_func_bitmap[1] = 0xffffffff;
+			g_adpt_api[dev_id]->adpt_port_ctrl_func_bitmap[2] = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_PORTCTRL);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_shaper_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_SHAPER);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_mib_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_MIB);
+			SW_RTN_ON_ERROR(rv);
+
+			g_adpt_api[dev_id]->adpt_policer_func_bitmap = 0xffffffff;
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_POLICER);
+			SW_RTN_ON_ERROR(rv);
+
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_MISC);
+			SW_RTN_ON_ERROR(rv);
+
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_PTP);
+			SW_RTN_ON_ERROR(rv);
+
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_SFP);
+			SW_RTN_ON_ERROR(rv);
+
+			/* uniphy */
+			rv = adpt_hppe_uniphy_init(dev_id);
+			SW_RTN_ON_ERROR(rv);
+
+			break;
+#endif
+#if defined (SCOMPHY)
+		case CHIP_SCOMPHY:
+			g_chip_ver[dev_id].chip_type = cfg->chip_type;
+			g_chip_ver[dev_id].chip_revision = cfg->phy_id;
+#if defined (MP)
+			if(cfg->phy_id == MP_GEPHY)
+			{
+				g_adpt_api[dev_id] = aos_mem_alloc(sizeof(adpt_api_t));
+				if(g_adpt_api[dev_id] == NULL)
+				{
+					SSDK_ERROR("malloc fail for adpt api\n");
+					return SW_FAIL;
+				}
+				aos_mem_zero(g_adpt_api[dev_id], sizeof(adpt_api_t));
+				rv = adpt_mp_intr_init(dev_id);
+				SW_RTN_ON_ERROR(rv);
+#if defined (IN_MIB)
+				rv = adpt_mp_mib_init(dev_id);
+				SW_RTN_ON_ERROR(rv);
+#endif
+#if defined (IN_PORTCONTROL)
+				rv = adpt_mp_portctrl_init(dev_id);
+				SW_RTN_ON_ERROR(rv);
+#endif
+#if defined (IN_UNIPHY)
+				rv = adpt_mp_uniphy_init(dev_id);
+				SW_RTN_ON_ERROR(rv);
+#endif
+#if defined (IN_LED)
+				rv = adpt_mp_led_init(dev_id);
+				SW_RTN_ON_ERROR(rv);
+#endif
+			}
+#endif
+			break;
+#endif
+		default:
+			break;
+	}
+	return rv;
+}
+
+sw_error_t adpt_module_func_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+	sw_error_t rv= SW_OK;
+
+	switch (cfg->chip_type)
+	{
+		#if defined(HPPE)
+		case CHIP_HPPE:
+			g_adpt_api[dev_id]->adpt_mirror_func_bitmap = 0;
+#if defined(IN_MIRROR)
+			adpt_hppe_mirror_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_MIRROR);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_fdb_func_bitmap[0] = 0;
+			g_adpt_api[dev_id]->adpt_fdb_func_bitmap[1] = 0;
+#if defined(IN_FDB)
+			adpt_hppe_fdb_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_FDB);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_stp_func_bitmap = 0;
+#if defined(IN_STP)
+			adpt_hppe_stp_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_STP);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_trunk_func_bitmap = 0;
+#if defined(IN_TRUNK)
+			adpt_hppe_trunk_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_TRUNK);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_portvlan_func_bitmap[0] = 0;
+			g_adpt_api[dev_id]->adpt_portvlan_func_bitmap[1] = 0;
+#if defined(IN_PORTVLAN)
+			adpt_hppe_portvlan_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_PORTVLAN);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_ctrlpkt_func_bitmap = 0;
+#if defined(IN_CTRLPKT)
+			adpt_hppe_ctrlpkt_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_CTRLPKT);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_sec_func_bitmap = 0;
+#if defined(IN_SEC)
+			adpt_hppe_sec_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_SEC);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_acl_func_bitmap = 0;
+#if defined(IN_ACL)
+			adpt_hppe_acl_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_ACL);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_vsi_func_bitmap = 0;
+#if defined(IN_VSI)
+			adpt_hppe_vsi_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_VSI);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_ip_func_bitmap[0] = 0;
+			g_adpt_api[dev_id]->adpt_ip_func_bitmap[1] = 0;
+#if defined(IN_IP)
+			adpt_hppe_ip_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_IP);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_flow_func_bitmap = 0;
+#if defined(IN_FLOW)
+			adpt_hppe_flow_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_FLOW);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_qm_func_bitmap[0] = 0;
+			g_adpt_api[dev_id]->adpt_qm_func_bitmap[1] = 0;
+#if defined(IN_QM)
+			adpt_hppe_qm_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_QM);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_qos_func_bitmap = 0;
+#if defined(IN_QOS)
+			adpt_hppe_qos_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_QOS);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_bm_func_bitmap = 0;
+#if defined(IN_BM)
+			adpt_hppe_bm_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_BM);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_servcode_func_bitmap = 0;
+#if defined(IN_SERVCODE)
+			adpt_hppe_servcode_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_SERVCODE);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_rss_hash_func_bitmap = 0;
+#if defined(IN_RSS_HASH)
+			adpt_hppe_rss_hash_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_RSS_HASH);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_pppoe_func_bitmap = 0;
+#if defined(IN_PPPOE)
+			adpt_hppe_pppoe_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_PPPOE);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_port_ctrl_func_bitmap[0] = 0;
+			g_adpt_api[dev_id]->adpt_port_ctrl_func_bitmap[1] = 0;
+			g_adpt_api[dev_id]->adpt_port_ctrl_func_bitmap[2] = 0;
+#if defined(IN_PORTCONTROL)
+			adpt_hppe_port_ctrl_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_PORTCTRL);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_shaper_func_bitmap = 0;
+#if defined(IN_SHAPER)
+			adpt_hppe_shaper_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_SHAPER);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_mib_func_bitmap = 0;
+#if defined(IN_MIB)
+			adpt_hppe_mib_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_MIB);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			g_adpt_api[dev_id]->adpt_policer_func_bitmap = 0;
+#if defined(IN_POLICER)
+			adpt_hppe_policer_func_bitmap_init(dev_id);
+			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_POLICER);
+			SW_RTN_ON_ERROR(rv);
+#endif
+
+			break;
+		#endif
+		default:
+			break;
+	}
+	return rv;
+}
+
diff --git a/qca-ssdk/src/adpt/cppe/Makefile b/qca-ssdk/src/adpt/cppe/Makefile
new file mode 100755
index 0000000..990c629
--- /dev/null
+++ b/qca-ssdk/src/adpt/cppe/Makefile
@@ -0,0 +1,48 @@
+LOC_DIR=src/adpt/cppe
+LIB=ADPT
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+  SRC_LIST += adpt_cppe_portctrl.c
+endif
+
+ifeq (TRUE, $(IN_QM))
+  SRC_LIST += adpt_cppe_qm.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+  SRC_LIST += adpt_cppe_qos.c
+endif
+
+ifeq (TRUE, $(IN_UNIPHY))
+  SRC_LIST += adpt_cppe_uniphy.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+ifneq (TRUE, $(IN_MISC_MINI))
+  SRC_LIST += adpt_cppe_misc.c
+endif
+endif
+
+ifeq (TRUE, $(IN_FLOW))
+ifneq (TRUE, $(IN_FLOW_MINI))
+  SRC_LIST += adpt_cppe_flow.c
+endif
+endif
+
+ifeq (TRUE, $(IN_MIB))
+  SRC_LIST += adpt_cppe_mib.c
+endif
+
+ifeq (, $(findstring CPPE, $(SUPPORT_CHIP)))
+  SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/adpt/cppe/adpt_cppe_flow.c b/qca-ssdk/src/adpt/cppe/adpt_cppe_flow.c
new file mode 100755
index 0000000..ea3877d
--- /dev/null
+++ b/qca-ssdk/src/adpt/cppe/adpt_cppe_flow.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_fdb_reg.h"
+#include "hppe_fdb.h"
+#include "hppe_ip_reg.h"
+#include "hppe_ip.h"
+#include "adpt.h"
+
+sw_error_t
+adpt_cppe_flow_copy_escape_set(a_uint32_t dev_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union l2_global_conf_u l2_global_conf;
+	union l3_route_ctrl_ext_u l3_route_ctrl_ext;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	memset(&l2_global_conf, 0, sizeof(l2_global_conf));
+	rv = hppe_l2_global_conf_get(dev_id, &l2_global_conf);
+	SW_RTN_ON_ERROR(rv);
+	l2_global_conf.bf.l2_flow_copy_escape = enable;
+	rv = hppe_l2_global_conf_set(dev_id, &l2_global_conf);
+	SW_RTN_ON_ERROR(rv);
+
+	memset(&l3_route_ctrl_ext, 0, sizeof(l3_route_ctrl_ext));
+	rv = hppe_l3_route_ctrl_ext_get(dev_id, &l3_route_ctrl_ext);
+	SW_RTN_ON_ERROR(rv);
+	l3_route_ctrl_ext.bf.l3_flow_copy_escape = enable;
+	rv = hppe_l3_route_ctrl_ext_set(dev_id, &l3_route_ctrl_ext);
+
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_flow_copy_escape_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+
+	sw_error_t rv = SW_OK;
+	union l2_global_conf_u l2_global_conf;
+	union l3_route_ctrl_ext_u l3_route_ctrl_ext;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	memset(&l2_global_conf, 0, sizeof(l2_global_conf));
+	rv = hppe_l2_global_conf_get(dev_id, &l2_global_conf);
+	SW_RTN_ON_ERROR(rv);
+
+	memset(&l3_route_ctrl_ext, 0, sizeof(l3_route_ctrl_ext));
+	rv = hppe_l3_route_ctrl_ext_get(dev_id, &l3_route_ctrl_ext);
+	SW_RTN_ON_ERROR(rv);
+
+	*enable = l2_global_conf.bf.l2_flow_copy_escape & l3_route_ctrl_ext.bf.l3_flow_copy_escape;
+	return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/cppe/adpt_cppe_mib.c b/qca-ssdk/src/adpt/cppe/adpt_cppe_mib.c
new file mode 100755
index 0000000..60c4f62
--- /dev/null
+++ b/qca-ssdk/src/adpt/cppe/adpt_cppe_mib.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "adpt.h"
+#include "cppe_loopback_reg.h"
+#include "cppe_loopback.h"
+#include "hppe_init.h"
+
+sw_error_t
+adpt_cppe_lpbk_mib_cpukeep_get(a_uint32_t dev_id, a_uint32_t port_id,
+	a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	union lpbk_mib_ctrl_u reg_value;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	rv = cppe_lpbk_mib_ctrl_get(dev_id, port_id, &reg_value);
+	SW_RTN_ON_ERROR(rv);
+
+	if (reg_value.bf.mib_rd_clr == A_TRUE)
+	{
+		*enable = A_FALSE;
+	}
+	else
+	{
+		*enable = A_TRUE;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_cppe_lpbk_mib_cpukeep_set(a_uint32_t dev_id, a_uint32_t port_id,
+	a_bool_t enable)
+{
+	union lpbk_mib_ctrl_u reg_value;
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = cppe_lpbk_mib_ctrl_get(dev_id, port_id, &reg_value);
+	SW_RTN_ON_ERROR(rv);
+	if(!enable)
+	{
+		reg_value.bf.mib_rd_clr = A_TRUE;
+	}
+	else
+	{
+		reg_value.bf.mib_rd_clr = A_FALSE;
+	}
+	rv = cppe_lpbk_mib_ctrl_set(dev_id, port_id, &reg_value);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_lpbk_mib_status_get(a_uint32_t dev_id, a_uint32_t port_id,
+	a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	union lpbk_mib_ctrl_u reg_value;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	rv = cppe_lpbk_mib_ctrl_get(dev_id, port_id, &reg_value);
+	SW_RTN_ON_ERROR(rv);
+	*enable = reg_value.bf.mib_en;
+
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_lpbk_mib_status_set(a_uint32_t dev_id, a_uint32_t port_id,
+	a_bool_t enable)
+{
+	union lpbk_mib_ctrl_u reg_value;
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = cppe_lpbk_mib_ctrl_get(dev_id, port_id, &reg_value);
+	SW_RTN_ON_ERROR(rv);
+	reg_value.bf.mib_en = enable;
+	rv = cppe_lpbk_mib_ctrl_set(dev_id, port_id, &reg_value);
+
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_lpbk_mib_flush_counters(a_uint32_t dev_id, fal_port_t port_id)
+{
+	union lpbk_mib_ctrl_u reg_value;
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = cppe_lpbk_mib_ctrl_get(dev_id, port_id, &reg_value);
+	SW_RTN_ON_ERROR(rv);
+	reg_value.bf.mib_reset = A_TRUE;
+	rv = cppe_lpbk_mib_ctrl_set(dev_id, port_id, &reg_value);
+	SW_RTN_ON_ERROR(rv);
+	reg_value.bf.mib_reset = A_FALSE;
+	rv = cppe_lpbk_mib_ctrl_set(dev_id, port_id, &reg_value);
+
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_lpbk_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+	fal_mib_info_t * mib_info )
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mib_info);
+	memset(mib_info, 0, sizeof(*mib_info));
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	cppe_lpbk_mib_uni_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkuni_u *)&mib_info->RxUniCast);
+	cppe_lpbk_mib_multi_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkmulti_u *)&mib_info->RxMulti);
+	cppe_lpbk_mib_broad_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkbroad_u *)&mib_info->RxBroad);
+	cppe_lpbk_mib_pkt64_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkpkt64_u *)&mib_info->Rx64Byte);
+	cppe_lpbk_mib_pkt65to127_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkpkt65to127_u *)&mib_info->Rx128Byte);
+	cppe_lpbk_mib_pkt128to255_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkpkt128to255_u *)&mib_info->Rx256Byte);
+	cppe_lpbk_mib_pkt256to511_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkpkt256to511_u *)&mib_info->Rx512Byte);
+	cppe_lpbk_mib_pkt512to1023_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkpkt512to1023_u *)&mib_info->Rx1024Byte);
+	cppe_lpbk_mib_pkt1024to1518_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkpkt1024to1518_u *)&mib_info->Rx1518Byte);
+	cppe_lpbk_mib_pkt1519tox_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkpkt1519tox_u *)&mib_info->RxMaxByte);
+	cppe_lpbk_mib_toolong_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkpkttoolong_u *)&mib_info->RxTooLong);
+	cppe_lpbk_mib_byte_l_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkbyte_l_u *)&mib_info->RxGoodByte_lo);
+	cppe_lpbk_mib_byte_h_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkbyte_h_u *)&mib_info->RxGoodByte_hi);
+	cppe_lpbk_mib_drop_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkdropcounter_u *)&mib_info->Filtered);
+	cppe_lpbk_mib_tooshort_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkpkttooshort_u *)&mib_info->RxRunt);
+	cppe_lpbk_mib_pkt14to63_get(dev_id, (a_uint32_t)port_id,
+		(union lpbkpkt14to63_u *)&mib_info->Rx14To63);
+	cppe_lpbk_mib_toolongbyte_l_get(dev_id, (a_uint32_t)port_id,
+		(union lpbktoolongbyte_l_u *)&mib_info->RxTooLongByte_lo);
+	cppe_lpbk_mib_toolongbyte_h_get(dev_id, (a_uint32_t)port_id,
+		(union lpbktoolongbyte_h_u *)&mib_info->RxTooLongByte_hi);
+	cppe_lpbk_mib_tooshortbyte_l_get(dev_id, (a_uint32_t)port_id,
+		(union lpbktooshortbyte_l_u *)&mib_info->RxRuntByte_lo);
+	cppe_lpbk_mib_tooshortbyte_h_get(dev_id, (a_uint32_t)port_id,
+		(union lpbktooshortbyte_h_u *)&mib_info->RxRuntByte_hi);
+
+	return SW_OK;
+}
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/cppe/adpt_cppe_misc.c b/qca-ssdk/src/adpt/cppe/adpt_cppe_misc.c
new file mode 100755
index 0000000..f7c2576
--- /dev/null
+++ b/qca-ssdk/src/adpt/cppe/adpt_cppe_misc.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_portctrl_reg.h"
+#include "hppe_portctrl.h"
+#include "hppe_portvlan_reg.h"
+#include "hppe_portvlan.h"
+#include "cppe_portctrl_reg.h"
+#include "cppe_portctrl.h"
+#include "adpt.h"
+
+sw_error_t
+adpt_cppe_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id,
+		fal_counter_en_t *cnt_en)
+{
+	union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;
+	union mc_mtu_ctrl_tbl_u mc_mtu_ctrl_tbl;
+	union port_eg_vlan_u port_eg_vlan;
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cnt_en);
+
+	port_id = FAL_PORT_ID_VALUE(port_id);
+
+	if (port_id < SSDK_MAX_PORT_NUM) {
+		rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl);
+		SW_RTN_ON_ERROR(rv);
+		rv = hppe_mc_mtu_ctrl_tbl_get(dev_id, port_id, &mc_mtu_ctrl_tbl);
+		SW_RTN_ON_ERROR(rv);
+		rv = hppe_port_eg_vlan_get(dev_id, port_id, &port_eg_vlan);
+		SW_RTN_ON_ERROR(rv);
+
+		mru_mtu_ctrl_tbl.bf.rx_cnt_en = cnt_en->rx_counter_en;
+		mru_mtu_ctrl_tbl.bf.tx_cnt_en = cnt_en->vp_uni_tx_counter_en;
+		mc_mtu_ctrl_tbl.bf.tx_cnt_en = cnt_en->port_mc_tx_counter_en;
+		port_eg_vlan.bf.tx_counting_en = cnt_en->port_tx_counter_en;
+
+		rv = cppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &mru_mtu_ctrl_tbl);
+		SW_RTN_ON_ERROR(rv);
+		rv = hppe_mc_mtu_ctrl_tbl_set(dev_id, port_id, &mc_mtu_ctrl_tbl);
+		SW_RTN_ON_ERROR(rv);
+		rv = hppe_port_eg_vlan_set(dev_id, port_id, &port_eg_vlan);
+		SW_RTN_ON_ERROR(rv);
+	} else if (port_id >= SSDK_MAX_PORT_NUM &&
+			port_id < SSDK_MAX_VIRTUAL_PORT_NUM) {
+		rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl);
+		SW_RTN_ON_ERROR(rv);
+
+		mru_mtu_ctrl_tbl.bf.rx_cnt_en = cnt_en->rx_counter_en;
+		mru_mtu_ctrl_tbl.bf.tx_cnt_en = cnt_en->vp_uni_tx_counter_en;
+
+		rv = cppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &mru_mtu_ctrl_tbl);
+		SW_RTN_ON_ERROR(rv);
+	} else {
+		return SW_OUT_OF_RANGE;
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_counter_en_t *cnt_en)
+{
+	union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;
+	union mc_mtu_ctrl_tbl_u mc_mtu_ctrl_tbl;
+	union port_eg_vlan_u port_eg_vlan;
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cnt_en);
+
+	port_id = FAL_PORT_ID_VALUE(port_id);
+
+	if (port_id < SSDK_MAX_PORT_NUM) {
+		rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl);
+		SW_RTN_ON_ERROR(rv);
+		rv = hppe_mc_mtu_ctrl_tbl_get(dev_id, port_id, &mc_mtu_ctrl_tbl);
+		SW_RTN_ON_ERROR(rv);
+		rv = hppe_port_eg_vlan_get(dev_id, port_id, &port_eg_vlan);
+		SW_RTN_ON_ERROR(rv);
+
+		cnt_en->rx_counter_en = mru_mtu_ctrl_tbl.bf.rx_cnt_en;
+		cnt_en->vp_uni_tx_counter_en = mru_mtu_ctrl_tbl.bf.tx_cnt_en;
+		cnt_en->port_mc_tx_counter_en = mc_mtu_ctrl_tbl.bf.tx_cnt_en;
+		cnt_en->port_tx_counter_en = port_eg_vlan.bf.tx_counting_en;
+	} else if (port_id >= SSDK_MAX_PORT_NUM &&
+			port_id < SSDK_MAX_VIRTUAL_PORT_NUM) {
+		rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl);
+		SW_RTN_ON_ERROR(rv);
+
+		cnt_en->rx_counter_en = mru_mtu_ctrl_tbl.bf.rx_cnt_en;
+		cnt_en->vp_uni_tx_counter_en = mru_mtu_ctrl_tbl.bf.tx_cnt_en;
+	} else {
+		return SW_OUT_OF_RANGE;
+	}
+
+	return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/cppe/adpt_cppe_portctrl.c b/qca-ssdk/src/adpt/cppe/adpt_cppe_portctrl.c
new file mode 100755
index 0000000..aad289d
--- /dev/null
+++ b/qca-ssdk/src/adpt/cppe/adpt_cppe_portctrl.c
@@ -0,0 +1,541 @@
+/*
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_global_reg.h"
+#include "hppe_global.h"
+#include "hppe_portctrl_reg.h"
+#include "hppe_portctrl.h"
+#include "cppe_portctrl_reg.h"
+#include "cppe_portctrl.h"
+#include "hppe_fdb_reg.h"
+#include "hppe_fdb.h"
+#include "cppe_loopback_reg.h"
+#include "cppe_loopback.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_phy.h"
+#include "hsl_port_prop.h"
+#include "hppe_init.h"
+#include "adpt.h"
+#include "adpt_hppe.h"
+#include "adpt_cppe_portctrl.h"
+
+sw_error_t
+_adpt_cppe_port_mux_mac_set(a_uint32_t dev_id, fal_port_t port_id,
+	a_uint32_t port_type)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t mode0, mode1;
+	union cppe_port_mux_ctrl_u cppe_port_mux_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	memset(&cppe_port_mux_ctrl, 0, sizeof(cppe_port_mux_ctrl));
+
+	rv = cppe_port_mux_ctrl_get(dev_id, &cppe_port_mux_ctrl);
+	SW_RTN_ON_ERROR (rv);
+
+	mode0 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0);
+	mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1);
+
+	switch (port_id) {
+		case SSDK_PHYSICAL_PORT3:
+		case SSDK_PHYSICAL_PORT4:
+			if (mode0 == PORT_WRAPPER_PSGMII) {
+				if (hsl_port_phyid_get(dev_id,
+					SSDK_PHYSICAL_PORT3) == MALIBU2PORT_PHY) {
+					cppe_port_mux_ctrl.bf.port3_pcs_sel =
+						CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4;
+					cppe_port_mux_ctrl.bf.port4_pcs_sel =
+						CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
+				} else {
+					cppe_port_mux_ctrl.bf.port3_pcs_sel =
+						CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
+					cppe_port_mux_ctrl.bf.port4_pcs_sel =
+						CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
+				}
+			} else if (mode0 == PORT_WRAPPER_QSGMII) {
+				cppe_port_mux_ctrl.bf.port3_pcs_sel =
+					CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
+				cppe_port_mux_ctrl.bf.port4_pcs_sel =
+					CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
+			} else if (mode0 == PORT_WRAPPER_SGMII_PLUS) {
+				cppe_port_mux_ctrl.bf.port3_pcs_sel =
+					CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
+				cppe_port_mux_ctrl.bf.port4_pcs_sel =
+					CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS;
+			} else if (mode0 ==PORT_WRAPPER_SGMII_CHANNEL0) {
+				if (hsl_port_prop_check(dev_id, SSDK_PHYSICAL_PORT4,
+					HSL_PP_EXCL_CPU) == A_TRUE) {
+					cppe_port_mux_ctrl.bf.port3_pcs_sel =
+						CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
+					cppe_port_mux_ctrl.bf.port4_pcs_sel =
+						CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS;
+				} else {
+					cppe_port_mux_ctrl.bf.port3_pcs_sel =
+						CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
+					cppe_port_mux_ctrl.bf.port4_pcs_sel =
+						CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
+				}
+			} else if ((mode0 == PORT_WRAPPER_SGMII_CHANNEL4) ||
+				(mode0 == PORT_WRAPPER_SGMII0_RGMII4)) {
+				cppe_port_mux_ctrl.bf.port3_pcs_sel =
+					CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
+				cppe_port_mux_ctrl.bf.port4_pcs_sel =
+					CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
+				cppe_port_mux_ctrl.bf.port5_pcs_sel =
+					CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4;
+				cppe_port_mux_ctrl.bf.port5_gmac_sel =
+					CPPE_PORT5_GMAC_SEL_GMAC;
+			} else if ((mode0 == PORT_WRAPPER_SGMII_CHANNEL1) ||
+				(mode0 == PORT_WRAPPER_SGMII1_RGMII4)) {
+				cppe_port_mux_ctrl.bf.port3_pcs_sel =
+					CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
+				cppe_port_mux_ctrl.bf.port4_pcs_sel =
+					CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
+			}
+			break;
+		case SSDK_PHYSICAL_PORT5:
+			if (mode0 == PORT_WRAPPER_PSGMII) {
+				if (hsl_port_phyid_get(dev_id,
+					SSDK_PHYSICAL_PORT3) != MALIBU2PORT_PHY) {
+					cppe_port_mux_ctrl.bf.port5_pcs_sel =
+						CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4;
+					cppe_port_mux_ctrl.bf.port5_gmac_sel =
+						CPPE_PORT5_GMAC_SEL_GMAC;
+				}
+			}
+			if ((mode1 == PORT_WRAPPER_SGMII_PLUS) ||
+				(mode1 == PORT_WRAPPER_SGMII0_RGMII4) ||
+				(mode1 == PORT_WRAPPER_SGMII_CHANNEL0) ||
+				(mode1 == PORT_WRAPPER_SGMII_FIBER)) {
+				cppe_port_mux_ctrl.bf.port5_pcs_sel =
+					CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0;
+				cppe_port_mux_ctrl.bf.port5_gmac_sel =
+					CPPE_PORT5_GMAC_SEL_GMAC;
+			} else if ((mode1 == PORT_WRAPPER_USXGMII) ||
+				(mode1 == PORT_WRAPPER_10GBASE_R)) {
+				cppe_port_mux_ctrl.bf.port5_pcs_sel =
+					CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0;
+				cppe_port_mux_ctrl.bf.port5_gmac_sel =
+					CPPE_PORT5_GMAC_SEL_XGMAC;
+			}
+			break;
+		default:
+			break;
+	}
+
+	rv = cppe_port_mux_ctrl_set(dev_id, &cppe_port_mux_ctrl);
+
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_port_mru_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl)
+{
+	sw_error_t rv = SW_OK;
+	union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;
+
+	memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl);
+	SW_RTN_ON_ERROR (rv);
+
+	mru_mtu_ctrl_tbl.bf.mru = ctrl->mru_size;
+	mru_mtu_ctrl_tbl.bf.mru_cmd = (a_uint32_t)ctrl->action;
+	rv = cppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &mru_mtu_ctrl_tbl);
+
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_port_mru_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl)
+{
+	sw_error_t rv = SW_OK;
+	union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;
+
+	memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl);
+	SW_RTN_ON_ERROR (rv);
+
+	ctrl->mru_size = mru_mtu_ctrl_tbl.bf.mru;
+	ctrl->action = (fal_fwd_cmd_t)mru_mtu_ctrl_tbl.bf.mru_cmd;
+
+	return SW_OK;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_cppe_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl)
+{
+	sw_error_t rv = SW_OK;
+	union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;
+
+	memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl);
+	SW_RTN_ON_ERROR (rv);
+
+	mru_mtu_ctrl_tbl.bf.mtu = ctrl->mtu_size;
+	mru_mtu_ctrl_tbl.bf.mtu_cmd = (a_uint32_t)ctrl->action;
+	rv = cppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &mru_mtu_ctrl_tbl);
+	SW_RTN_ON_ERROR (rv);
+
+	if ((port_id >= SSDK_PHYSICAL_PORT0) && (port_id <= SSDK_PHYSICAL_PORT7))
+	{
+		rv = hppe_mc_mtu_ctrl_tbl_mtu_set(dev_id, port_id, ctrl->mtu_size);
+		SW_RTN_ON_ERROR (rv);
+		rv = hppe_mc_mtu_ctrl_tbl_mtu_cmd_set(dev_id, port_id, (a_uint32_t)ctrl->action);
+		SW_RTN_ON_ERROR (rv);
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl)
+{
+	sw_error_t rv = SW_OK;
+	union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;
+
+	memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl);
+	SW_RTN_ON_ERROR (rv);
+
+	ctrl->mtu_size = mru_mtu_ctrl_tbl.bf.mtu;
+	ctrl->action = (fal_fwd_cmd_t)mru_mtu_ctrl_tbl.bf.mtu_cmd;
+
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+adpt_cppe_port_to_channel_convert(a_uint32_t dev_id, a_uint32_t port_id,
+	a_uint32_t *channel_id)
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(channel_id);
+
+	*channel_id = port_id;
+
+	if (port_id == SSDK_PHYSICAL_PORT3) {
+		if (hsl_port_phyid_get(dev_id,
+				port_id) == MALIBU2PORT_PHY) {
+			*channel_id = SSDK_PHYSICAL_PORT5;
+		}
+	}
+	return SW_OK;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_cppe_port_source_filter_set(a_uint32_t dev_id,
+	fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	fal_src_filter_config_t src_filter_config;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = adpt_cppe_port_source_filter_config_get(dev_id,
+			port_id, &src_filter_config);
+	SW_RTN_ON_ERROR(rv);
+	src_filter_config.src_filter_enable = enable;
+	rv = adpt_cppe_port_source_filter_config_set(dev_id, port_id,
+			&src_filter_config);
+
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_port_source_filter_get(a_uint32_t dev_id,
+	fal_port_t port_id, a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	fal_src_filter_config_t src_filter_config;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	rv = adpt_cppe_port_source_filter_config_get(dev_id, port_id,
+			&src_filter_config);
+	SW_RTN_ON_ERROR(rv);
+	*enable = src_filter_config.src_filter_enable;
+
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_port_source_filter_config_set(a_uint32_t dev_id,
+	fal_port_t port_id, fal_src_filter_config_t *src_filter_config)
+{
+	sw_error_t rv = SW_OK;
+	a_bool_t src_filter_bypass;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(src_filter_config);
+
+	port_id = FAL_PORT_ID_VALUE(port_id);
+	if(src_filter_config->src_filter_enable == A_TRUE)
+	{
+		src_filter_bypass = A_FALSE;
+	}
+	else
+	{
+		src_filter_bypass = A_TRUE;
+	}
+	rv = cppe_mru_mtu_ctrl_tbl_source_filter_set(dev_id, port_id,
+			src_filter_bypass);
+	SW_RTN_ON_ERROR(rv);
+	rv = cppe_mru_mtu_ctrl_tbl_source_filter_mode_set(dev_id, port_id,
+			src_filter_config->src_filter_mode);
+
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_port_source_filter_config_get(a_uint32_t dev_id,
+	fal_port_t port_id, fal_src_filter_config_t *src_filter_config)
+{
+	sw_error_t rv = SW_OK;
+	a_bool_t src_filter_bypass;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(src_filter_config);
+
+	port_id = FAL_PORT_ID_VALUE(port_id);
+	rv = cppe_mru_mtu_ctrl_tbl_source_filter_get(dev_id, port_id,
+			&src_filter_bypass);
+	SW_RTN_ON_ERROR(rv);
+	if(src_filter_bypass == A_TRUE)
+	{
+		src_filter_config->src_filter_enable = A_FALSE;
+	}
+	else
+	{
+		src_filter_config->src_filter_enable = A_TRUE;
+	}
+
+	rv = cppe_mru_mtu_ctrl_tbl_source_filter_mode_get(dev_id,
+			port_id, &(src_filter_config->src_filter_mode));
+
+	return rv;
+}
+#endif
+
+static a_uint32_t port_loopback_rate[SW_MAX_NR_DEV][CPPE_LOOPBACK_PORT_NUM] = {
+	{14},
+	{14},
+	{14},
+}; /* unit is Mpps*/
+
+sw_error_t
+adpt_cppe_switch_port_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
+	fal_loopback_config_t *loopback_cfg)
+{
+	sw_error_t rv = SW_OK;
+	union lpbk_enable_u loopback_cfg_tbl;
+	union lpbk_pps_ctrl_u loopback_rate_ctrl_tbl;
+	union port_bridge_ctrl_u port_bridge_ctrl;
+	a_uint32_t physical_port = 0;
+
+	if (port_id != SSDK_PHYSICAL_PORT6) {
+		return SW_BAD_PARAM;
+	}
+
+	memset(&loopback_cfg_tbl, 0, sizeof(loopback_cfg_tbl));
+	memset(&loopback_rate_ctrl_tbl, 0, sizeof(loopback_rate_ctrl_tbl));
+	memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(loopback_cfg);
+
+	physical_port = port_id;
+	rv = hppe_port_bridge_ctrl_get(dev_id, physical_port, &port_bridge_ctrl);
+	SW_RTN_ON_ERROR (rv);
+	port_bridge_ctrl.bf.txmac_en = loopback_cfg->enable;
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = cppe_lpbk_pps_ctrl_get(dev_id, port_id, &loopback_rate_ctrl_tbl);
+	SW_RTN_ON_ERROR (rv);
+
+	loopback_rate_ctrl_tbl.bf.lpbk_pps_threshold =
+		CPPE_LOOPBACK_PORT_RATE_FREQUENCY / loopback_cfg->loopback_rate;
+
+	rv = cppe_lpbk_enable_get(dev_id, port_id, &loopback_cfg_tbl);
+	SW_RTN_ON_ERROR (rv);
+	loopback_cfg_tbl.bf.lpbk_en = loopback_cfg->enable;
+	loopback_cfg_tbl.bf.crc_strip_en = loopback_cfg->crc_stripped;
+
+	if (loopback_cfg->enable == A_TRUE) {
+		rv = cppe_lpbk_pps_ctrl_set(dev_id, port_id, &loopback_rate_ctrl_tbl);
+		SW_RTN_ON_ERROR (rv);
+		rv = cppe_lpbk_enable_set(dev_id, port_id, &loopback_cfg_tbl);
+		SW_RTN_ON_ERROR (rv);
+		msleep(100);
+		rv = hppe_port_bridge_ctrl_set(dev_id, physical_port,
+			&port_bridge_ctrl);
+		SW_RTN_ON_ERROR (rv);
+	} else {
+		rv = hppe_port_bridge_ctrl_set(dev_id, physical_port,
+			&port_bridge_ctrl);
+		SW_RTN_ON_ERROR (rv);
+		msleep(100);
+		rv = cppe_lpbk_pps_ctrl_set(dev_id, port_id, &loopback_rate_ctrl_tbl);
+		SW_RTN_ON_ERROR (rv);
+		rv = cppe_lpbk_enable_set(dev_id, port_id, &loopback_cfg_tbl);
+		SW_RTN_ON_ERROR (rv);
+	}
+
+	port_loopback_rate[dev_id][CPPE_LOOPBACK_PORT_NUM - 1] =
+		loopback_cfg->loopback_rate;
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_switch_port_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
+	fal_loopback_config_t *loopback_cfg)
+{
+	sw_error_t rv = SW_OK;
+	union lpbk_enable_u loopback_cfg_tbl;
+	union lpbk_pps_ctrl_u loopback_rate_ctrl_tbl;
+
+	if (port_id != SSDK_PHYSICAL_PORT6) {
+		return SW_BAD_PARAM;
+	}
+
+	memset(&loopback_cfg_tbl, 0, sizeof(loopback_cfg_tbl));
+	memset(&loopback_rate_ctrl_tbl, 0, sizeof(loopback_rate_ctrl_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(loopback_cfg);
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = cppe_lpbk_enable_get(dev_id, port_id, &loopback_cfg_tbl);
+	SW_RTN_ON_ERROR (rv);
+	rv = cppe_lpbk_pps_ctrl_get(dev_id, port_id, &loopback_rate_ctrl_tbl);
+	SW_RTN_ON_ERROR (rv);
+
+	loopback_cfg->enable = loopback_cfg_tbl.bf.lpbk_en;
+	loopback_cfg->crc_stripped = loopback_cfg_tbl.bf.crc_strip_en;
+	loopback_cfg->loopback_rate =
+		port_loopback_rate[dev_id][CPPE_LOOPBACK_PORT_NUM - 1];
+
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_switch_port_loopback_flowctrl_set(a_uint32_t dev_id,
+	fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union lpbk_enable_u loopback_cfg_tbl;
+
+	memset(&loopback_cfg_tbl, 0, sizeof(loopback_cfg_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (port_id != SSDK_PHYSICAL_PORT6) {
+		return SW_BAD_PARAM;
+	}
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = cppe_lpbk_enable_get(dev_id, port_id, &loopback_cfg_tbl);
+	SW_RTN_ON_ERROR (rv);
+	loopback_cfg_tbl.bf.flowctrl_en = enable;
+	rv = cppe_lpbk_enable_set(dev_id, port_id, &loopback_cfg_tbl);
+
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_switch_port_loopback_flowctrl_get(a_uint32_t dev_id,
+	fal_port_t port_id, a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	union lpbk_enable_u loopback_cfg_tbl;
+
+	memset(&loopback_cfg_tbl, 0, sizeof(loopback_cfg_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	if (port_id != SSDK_PHYSICAL_PORT6) {
+		return SW_BAD_PARAM;
+	}
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = cppe_lpbk_enable_get(dev_id, port_id, &loopback_cfg_tbl);
+	SW_RTN_ON_ERROR (rv);
+	*enable = loopback_cfg_tbl.bf.flowctrl_en;
+
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_lpbk_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
+	a_uint32_t *max_frame)
+{
+	sw_error_t rv = SW_OK;
+	union lpbk_mac_junmo_size_u lpbk_mac_junmo_size;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(max_frame);
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = cppe_lpbk_mac_junmo_size_get(dev_id, port_id, &lpbk_mac_junmo_size);
+	SW_RTN_ON_ERROR(rv);
+	*max_frame = lpbk_mac_junmo_size.bf.lpbk_mac_jumbo_size;
+
+	return rv;
+}
+
+sw_error_t
+adpt_cppe_lpbk_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
+	a_uint32_t max_frame)
+{
+	sw_error_t rv = SW_OK;
+	union lpbk_mac_junmo_size_u lpbk_mac_junmo_size;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	memset(&lpbk_mac_junmo_size, 0, sizeof(lpbk_mac_junmo_size));
+	if (max_frame > SSDK_MAX_FRAME_SIZE)
+	{
+		return SW_BAD_VALUE;
+	}
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = cppe_lpbk_mac_junmo_size_get(dev_id, port_id, &lpbk_mac_junmo_size);
+	SW_RTN_ON_ERROR(rv);
+	lpbk_mac_junmo_size.bf.lpbk_mac_jumbo_size = max_frame;
+	rv = cppe_lpbk_mac_junmo_size_set(dev_id, port_id, &lpbk_mac_junmo_size);
+
+	return rv;
+}
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/cppe/adpt_cppe_qm.c b/qca-ssdk/src/adpt/cppe/adpt_cppe_qm.c
new file mode 100755
index 0000000..d4317d5
--- /dev/null
+++ b/qca-ssdk/src/adpt/cppe/adpt_cppe_qm.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "fal_qos.h"
+#include "cppe_portctrl_reg.h"
+#include "cppe_portctrl.h"
+#include "adpt.h"
+
+#ifndef IN_QM_MINI
+sw_error_t
+adpt_cppe_qm_port_source_profile_set(
+		a_uint32_t dev_id, fal_port_t port, a_uint32_t src_profile)
+{
+	union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;
+	a_uint32_t index = FAL_PORT_ID_VALUE(port);
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl));
+
+
+	return cppe_mru_mtu_ctrl_tbl_src_profile_set(dev_id, index,
+				src_profile);
+}
+
+sw_error_t
+adpt_cppe_qm_port_source_profile_get(
+		a_uint32_t dev_id, fal_port_t port, a_uint32_t *src_profile)
+{
+	union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;
+	a_uint32_t index = FAL_PORT_ID_VALUE(port);
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(src_profile);
+	memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl));
+
+	return cppe_mru_mtu_ctrl_tbl_src_profile_get(dev_id, index,
+				src_profile);
+}
+#endif
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/cppe/adpt_cppe_qos.c b/qca-ssdk/src/adpt/cppe/adpt_cppe_qos.c
new file mode 100644
index 0000000..c0e0209
--- /dev/null
+++ b/qca-ssdk/src/adpt/cppe/adpt_cppe_qos.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "fal_qos.h"
+#include "cppe_portctrl_reg.h"
+#include "cppe_portctrl.h"
+#include "cppe_qos_reg.h"
+#include "cppe_qos.h"
+#include "adpt.h"
+
+static sw_error_t
+adpt_cppe_qos_mapping_get(a_uint32_t dev_id, a_uint32_t index,
+			fal_qos_cosmap_t *cosmap)
+{
+	sw_error_t rv = SW_OK;
+	union qos_mapping_tbl_u qos_mapping_tbl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cosmap);
+
+	rv = cppe_qos_mapping_tbl_get(dev_id, index, &qos_mapping_tbl);
+	if (rv != SW_OK)
+		return rv;
+
+	cosmap->internal_pcp = qos_mapping_tbl.bf.int_pcp;
+	cosmap->internal_dei = qos_mapping_tbl.bf.int_dei;
+	cosmap->internal_pri = qos_mapping_tbl.bf.int_pri;
+	cosmap->internal_dscp = qos_mapping_tbl.bf.int_dscp_tc;
+	cosmap->internal_dp = qos_mapping_tbl.bf.int_dp;
+	cosmap->dscp_mask = qos_mapping_tbl.bf.dscp_tc_mask;
+	cosmap->dscp_en = qos_mapping_tbl.bf.int_dscp_en;
+	cosmap->pcp_en = qos_mapping_tbl.bf.int_pcp_en;
+	cosmap->dei_en = qos_mapping_tbl.bf.int_dei_en;
+	cosmap->pri_en = qos_mapping_tbl.bf.int_pri_en;
+	cosmap->dp_en = qos_mapping_tbl.bf.int_dp_en;
+	cosmap->qos_prec = qos_mapping_tbl.bf.qos_res_prec_0 |
+			     qos_mapping_tbl.bf.qos_res_prec_1 << 1;
+
+	return SW_OK;
+}
+
+static sw_error_t
+adpt_cppe_qos_mapping_set(a_uint32_t dev_id, a_uint32_t index,
+			fal_qos_cosmap_t *cosmap)
+{
+	union qos_mapping_tbl_u qos_mapping_tbl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+        ADPT_NULL_POINT_CHECK(cosmap);
+
+	memset(&qos_mapping_tbl, 0, sizeof(qos_mapping_tbl));
+
+	qos_mapping_tbl.bf.int_pcp = cosmap->internal_pcp;
+	qos_mapping_tbl.bf.int_dei = cosmap->internal_dei;
+	qos_mapping_tbl.bf.int_pri = cosmap->internal_pri;
+	qos_mapping_tbl.bf.int_dscp_tc = cosmap->internal_dscp;
+	qos_mapping_tbl.bf.int_dp = cosmap->internal_dp;
+	qos_mapping_tbl.bf.dscp_tc_mask = cosmap->dscp_mask;
+	qos_mapping_tbl.bf.int_dscp_en = cosmap->dscp_en;
+	qos_mapping_tbl.bf.int_pcp_en = cosmap->pcp_en;
+	qos_mapping_tbl.bf.int_dei_en = cosmap->dei_en;
+	qos_mapping_tbl.bf.int_pri_en = cosmap->pri_en;
+	qos_mapping_tbl.bf.int_dp_en = cosmap->dp_en;
+	qos_mapping_tbl.bf.qos_res_prec_0 = cosmap->qos_prec & 1;
+	qos_mapping_tbl.bf.qos_res_prec_1 = (cosmap->qos_prec >> 1) & 3;
+
+	return cppe_qos_mapping_tbl_set(dev_id, index, &qos_mapping_tbl);
+}
+
+sw_error_t
+adpt_cppe_qos_port_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+			fal_qos_pri_precedence_t *pri)
+{
+	union cppe_mru_mtu_ctrl_tbl_u cppe_mru_mtu_ctrl;
+
+	memset(&cppe_mru_mtu_ctrl, 0, sizeof(cppe_mru_mtu_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(pri);
+
+	cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &cppe_mru_mtu_ctrl);
+
+	cppe_mru_mtu_ctrl.bf.pcp_res_prec = pri->pcp_pri;
+	cppe_mru_mtu_ctrl.bf.dscp_res_prec = pri->dscp_pri;
+	cppe_mru_mtu_ctrl.bf.preheader_res_prec = pri->preheader_pri;
+	cppe_mru_mtu_ctrl.bf.flow_res_prec = pri->flow_pri;
+	cppe_mru_mtu_ctrl.bf.pre_acl_res_prec = pri->acl_pri;
+	cppe_mru_mtu_ctrl.bf.post_acl_res_prec = pri->post_acl_pri;
+	cppe_mru_mtu_ctrl.bf.pcp_res_prec_force = pri->pcp_pri_force;
+	cppe_mru_mtu_ctrl.bf.dscp_res_prec_force = pri->dscp_pri_force;
+
+	return cppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &cppe_mru_mtu_ctrl);
+}
+
+sw_error_t
+adpt_cppe_qos_port_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+			fal_qos_pri_precedence_t *pri)
+{
+	sw_error_t rv = SW_OK;
+	union cppe_mru_mtu_ctrl_tbl_u cppe_mru_mtu_ctrl;
+
+	memset(&cppe_mru_mtu_ctrl, 0, sizeof(cppe_mru_mtu_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(pri);
+
+	rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &cppe_mru_mtu_ctrl);
+	if( rv != SW_OK )
+		return rv;
+
+	pri->pcp_pri = cppe_mru_mtu_ctrl.bf.pcp_res_prec;
+	pri->dscp_pri = cppe_mru_mtu_ctrl.bf.dscp_res_prec;
+	pri->preheader_pri = cppe_mru_mtu_ctrl.bf.preheader_res_prec;
+	pri->flow_pri = cppe_mru_mtu_ctrl.bf.flow_res_prec;
+	pri->acl_pri = cppe_mru_mtu_ctrl.bf.pre_acl_res_prec;
+	pri->post_acl_pri = cppe_mru_mtu_ctrl.bf.post_acl_res_prec;
+	pri->pcp_pri_force = cppe_mru_mtu_ctrl.bf.pcp_res_prec_force;
+	pri->dscp_pri_force = cppe_mru_mtu_ctrl.bf.dscp_res_prec_force;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_cppe_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id,
+			a_uint8_t pcp,
+			fal_qos_cosmap_t *cosmap)
+{
+	a_uint32_t index = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cosmap);
+
+	if (group_id >= QOS_MAPPING_TBL_MAX_GROUP)
+		return SW_BAD_PARAM;
+
+	index = QOS_MAPPING_FLOW_TBL_MAX_ENTRY +
+		2 * QOS_MAPPING_DSCP_TBL_MAX_ENTRY +
+		group_id * QOS_MAPPING_PCP_TBL_MAX_ENTRY + pcp;
+
+	return adpt_cppe_qos_mapping_get(dev_id, index, cosmap);
+}
+
+sw_error_t
+adpt_cppe_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id,
+			a_uint8_t pcp,
+			fal_qos_cosmap_t *cosmap)
+{
+	a_uint32_t index = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cosmap);
+
+	if (group_id >= QOS_MAPPING_TBL_MAX_GROUP)
+		return SW_BAD_PARAM;
+
+	index = QOS_MAPPING_FLOW_TBL_MAX_ENTRY +
+		2 * QOS_MAPPING_DSCP_TBL_MAX_ENTRY +
+		group_id * QOS_MAPPING_PCP_TBL_MAX_ENTRY + pcp;
+
+	return adpt_cppe_qos_mapping_set(dev_id, index, cosmap);
+}
+
+sw_error_t
+adpt_cppe_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id,
+			a_uint8_t dscp,
+			fal_qos_cosmap_t *cosmap)
+{
+	a_uint32_t index = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cosmap);
+
+	if (group_id >= QOS_MAPPING_TBL_MAX_GROUP)
+		return SW_BAD_PARAM;
+
+	index = QOS_MAPPING_FLOW_TBL_MAX_ENTRY +
+		group_id * QOS_MAPPING_DSCP_TBL_MAX_ENTRY +
+		dscp;
+
+	return adpt_cppe_qos_mapping_get(dev_id, index, cosmap);
+}
+
+sw_error_t
+adpt_cppe_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id,
+			a_uint16_t flow,
+			fal_qos_cosmap_t *cosmap)
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cosmap);
+
+	if (flow >= QOS_MAPPING_FLOW_TBL_MAX_ENTRY)
+		return SW_BAD_PARAM;
+
+	return adpt_cppe_qos_mapping_set(dev_id, flow, cosmap);
+}
+
+sw_error_t
+adpt_cppe_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id,
+			fal_qos_group_t *group)
+{
+	union cppe_mru_mtu_ctrl_tbl_u cppe_mru_mtu_ctrl;
+
+	memset(&cppe_mru_mtu_ctrl, 0, sizeof(cppe_mru_mtu_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(group);
+
+	cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &cppe_mru_mtu_ctrl);
+
+	cppe_mru_mtu_ctrl.bf.pcp_qos_group_id = group->pcp_group;
+	cppe_mru_mtu_ctrl.bf.dscp_qos_group_id = group->dscp_group;
+
+	return cppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &cppe_mru_mtu_ctrl);
+}
+
+sw_error_t
+adpt_cppe_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id,
+			a_uint8_t dscp,
+			fal_qos_cosmap_t *cosmap)
+{
+	a_uint32_t index = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cosmap);
+
+	if (group_id >= QOS_MAPPING_TBL_MAX_GROUP)
+		return SW_BAD_PARAM;
+
+	index = QOS_MAPPING_FLOW_TBL_MAX_ENTRY +
+		group_id * QOS_MAPPING_DSCP_TBL_MAX_ENTRY +
+		dscp;
+
+	return adpt_cppe_qos_mapping_set(dev_id, index, cosmap);
+}
+
+sw_error_t
+adpt_cppe_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id,
+			a_uint16_t flow,
+			fal_qos_cosmap_t *cosmap)
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cosmap);
+
+	if (flow >= QOS_MAPPING_FLOW_TBL_MAX_ENTRY)
+		return SW_BAD_PARAM;
+
+	return adpt_cppe_qos_mapping_get(dev_id, flow, cosmap);
+}
+
+sw_error_t
+adpt_cppe_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id,
+			fal_qos_group_t *group)
+{
+	sw_error_t rv = SW_OK;
+	union cppe_mru_mtu_ctrl_tbl_u cppe_mru_mtu_ctrl;
+
+	memset(&cppe_mru_mtu_ctrl, 0, sizeof(cppe_mru_mtu_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(group);
+
+	rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &cppe_mru_mtu_ctrl);
+	if( rv != SW_OK )
+		return rv;
+
+	group->pcp_group = cppe_mru_mtu_ctrl.bf.pcp_qos_group_id;
+	group->dscp_group = cppe_mru_mtu_ctrl.bf.dscp_qos_group_id;
+
+	return SW_OK;
+}
+
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/adpt/cppe/adpt_cppe_uniphy.c b/qca-ssdk/src/adpt/cppe/adpt_cppe_uniphy.c
new file mode 100755
index 0000000..cf38c00
--- /dev/null
+++ b/qca-ssdk/src/adpt/cppe/adpt_cppe_uniphy.c
@@ -0,0 +1,304 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_global_reg.h"
+#include "hppe_global.h"
+#include "hppe_uniphy_reg.h"
+#include "hppe_uniphy.h"
+#include "hppe_init.h"
+#include "ssdk_init.h"
+#include "ssdk_clk.h"
+#include "adpt_hppe.h"
+#include "adpt.h"
+#include "hppe_reg_access.h"
+#include "hsl_phy.h"
+#include "adpt_cppe_portctrl.h"
+#include "adpt_cppe_uniphy.h"
+
+static sw_error_t
+__adpt_cppe_uniphy_reset(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+	sw_error_t rv = SW_OK;
+	union pll_power_on_and_reset_u pll_software_reset;
+
+	memset(&pll_software_reset, 0, sizeof(pll_software_reset));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_uniphy_pll_reset_ctrl_get(dev_id, uniphy_index,
+		&pll_software_reset);
+	SW_RTN_ON_ERROR (rv);
+	pll_software_reset.bf.software_reset_analog_reset = 0;
+	rv = hppe_uniphy_pll_reset_ctrl_set(dev_id, uniphy_index,
+		&pll_software_reset);
+	SW_RTN_ON_ERROR (rv);
+	msleep(500);
+	pll_software_reset.bf.software_reset_analog_reset = 1;
+	rv = hppe_uniphy_pll_reset_ctrl_set(dev_id, uniphy_index,
+		&pll_software_reset);
+	SW_RTN_ON_ERROR (rv);
+	msleep(500);
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_cppe_uniphy_port_disable(a_uint32_t dev_id, a_uint32_t uniphy_index,
+	a_uint32_t port_id)
+{
+	enum unphy_rst_type rst_type = 0;
+
+	if (uniphy_index != SSDK_UNIPHY_INSTANCE0) {
+		return SW_BAD_VALUE;
+	}
+
+	switch (port_id) {
+		case SSDK_PHYSICAL_PORT1:
+			rst_type = UNIPHY0_PORT1_DISABLE_E;
+			break;
+		case SSDK_PHYSICAL_PORT2:
+			rst_type = UNIPHY0_PORT2_DISABLE_E;
+			break;
+		case SSDK_PHYSICAL_PORT3:
+			rst_type = UNIPHY0_PORT3_DISABLE_E;
+			break;
+		case SSDK_PHYSICAL_PORT4:
+			rst_type = UNIPHY0_PORT4_DISABLE_E;
+			break;
+		case SSDK_PHYSICAL_PORT5:
+			rst_type = UNIPHY0_PORT5_DISABLE_E;
+			break;
+		default:
+			break;
+	}
+	ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_ASSERT);
+
+	return SW_OK;
+}
+
+void
+__adpt_cppe_gcc_uniphy_software_reset(a_uint32_t dev_id,
+	a_uint32_t uniphy_index)
+{
+	a_uint32_t phy_type = 0;
+	enum unphy_rst_type rst_type = 0;
+
+	if (uniphy_index >= SSDK_UNIPHY_INSTANCE2) {
+		return;
+	}
+
+	if (uniphy_index == SSDK_UNIPHY_INSTANCE0) {
+		phy_type = hsl_port_phyid_get(dev_id, SSDK_PHYSICAL_PORT4);
+		if (phy_type == MALIBU2PORT_PHY) {
+			rst_type = UNIPHY0_PORT_4_5_RESET_E;
+		} else if (phy_type == QCA8081_PHY_V1_1) {
+			rst_type = UNIPHY0_PORT_4_RESET_E;
+		} else {
+			rst_type = UNIPHY0_SOFT_RESET_E;
+		}
+	} else {
+		rst_type = UNIPHY1_SOFT_RESET_E;
+	}
+
+	ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_ASSERT);
+
+	msleep(100);
+
+	ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_DEASSERT);
+
+	return;
+}
+
+sw_error_t
+__adpt_cppe_uniphy_channel_selection_set(a_uint32_t dev_id,
+	a_uint32_t ch0_selection, a_uint32_t ch4_selection)
+{
+	sw_error_t rv = SW_OK;
+	union cppe_port_mux_ctrl_u cppe_port_mux_ctrl;
+
+	memset(&cppe_port_mux_ctrl, 0, sizeof(cppe_port_mux_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = cppe_port_mux_ctrl_get(dev_id, &cppe_port_mux_ctrl);
+	SW_RTN_ON_ERROR (rv);
+	cppe_port_mux_ctrl.bf.pcs0_ch0_sel = ch0_selection;
+	cppe_port_mux_ctrl.bf.pcs0_ch4_sel = ch4_selection;
+	rv = cppe_port_mux_ctrl_set(dev_id, &cppe_port_mux_ctrl);
+	SW_RTN_ON_ERROR (rv);
+
+	return rv;
+}
+
+static sw_error_t
+__adpt_cppe_uniphy_mode_ctrl_set(a_uint32_t dev_id,
+	a_uint32_t uniphy_index, a_uint32_t mode)
+{
+	sw_error_t rv = SW_OK;
+	union uniphy_mode_ctrl_u uniphy_mode_ctrl;
+
+	memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
+
+	/* configure uniphy mode ctrl to psgmii/sgmii/sgmiiplus */
+	rv = hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
+	SW_RTN_ON_ERROR (rv);
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode =
+		UNIPHY_ATHEROS_NEGOTIATION;
+	if (mode == PORT_WRAPPER_PSGMII) {
+		uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+			UNIPHY_CH0_PSGMII_MODE;
+		uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+			UNIPHY_SGMII_MODE_DISABLE;
+		uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+			UNIPHY_SGMIIPLUS_MODE_DISABLE;
+	} else if (mode == PORT_WRAPPER_SGMII_CHANNEL0) {
+		uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+			UNIPHY_CH0_QSGMII_SGMII_MODE;
+		uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+			UNIPHY_SGMII_MODE_ENABLE;
+		uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+			UNIPHY_SGMIIPLUS_MODE_DISABLE;
+	} else {
+		uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+			UNIPHY_CH0_QSGMII_SGMII_MODE;
+		uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+			UNIPHY_SGMII_MODE_DISABLE;
+		uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+			UNIPHY_SGMIIPLUS_MODE_ENABLE;
+	}
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+		UNIPHY_CH0_SGMII_MODE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+		UNIPHY_XPCS_MODE_DISABLE;
+	rv = hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
+
+	return rv;
+}
+
+sw_error_t
+__adpt_cppe_uniphy_mode_set(a_uint32_t dev_id,
+		a_uint32_t uniphy_index, a_uint32_t mode)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t i = 0;
+	union uniphy_misc2_phy_mode_u uniphy_misc2_phy_mode;
+
+	memset(&uniphy_misc2_phy_mode, 0, sizeof(uniphy_misc2_phy_mode));
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (uniphy_index != SSDK_UNIPHY_INSTANCE0) {
+		SSDK_ERROR("uniphy index is %d\n", uniphy_index);
+		return SW_BAD_VALUE;
+	}
+
+	if ((mode == PORT_WRAPPER_SGMII_CHANNEL0) ||
+		(mode == PORT_WRAPPER_SGMII_PLUS)) {
+		/*set the PHY mode to SGMII or SGMIIPLUS*/
+		rv = hppe_uniphy_phy_mode_ctrl_get(dev_id, uniphy_index,
+			&uniphy_misc2_phy_mode);
+		SW_RTN_ON_ERROR (rv);
+		if (mode == PORT_WRAPPER_SGMII_CHANNEL0) {
+			uniphy_misc2_phy_mode.bf.phy_mode =
+				UNIPHY_PHY_SGMII_MODE;
+		} else {
+			uniphy_misc2_phy_mode.bf.phy_mode =
+				UNIPHY_PHY_SGMIIPLUS_MODE;
+		}
+		rv = hppe_uniphy_phy_mode_ctrl_set(dev_id, uniphy_index,
+			&uniphy_misc2_phy_mode);
+		SW_RTN_ON_ERROR (rv);
+
+		/*reset uniphy*/
+		rv = __adpt_cppe_uniphy_reset(dev_id, uniphy_index);
+		SW_RTN_ON_ERROR (rv);
+	}
+	/* keep xpcs to reset status */
+	__adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE);
+
+	SW_RTN_ON_ERROR (rv);
+	if (mode == PORT_WRAPPER_PSGMII) {
+		/* disable GCC_UNIPHY0_MISC port 1, 2 and 3*/
+		for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT4; i++) {
+		 	rv = __adpt_cppe_uniphy_port_disable(dev_id, uniphy_index, i);
+			SW_RTN_ON_ERROR (rv);
+		}
+
+		/* disable instance0 port 4 and 5 clock */
+		for (i = SSDK_PHYSICAL_PORT4; i < SSDK_PHYSICAL_PORT6; i++) {
+			qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+				i, A_FALSE);
+		}
+		rv = __adpt_cppe_uniphy_channel_selection_set(dev_id,
+			CPPE_PCS0_CHANNEL0_SEL_PSGMII,
+			CPPE_PCS0_CHANNEL4_SEL_PORT3_CLOCK);
+		SW_RTN_ON_ERROR (rv);
+	} else {
+		/* disable GCC_UNIPHY0_MISC port 2, 3 and 5*/
+		for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT6; i++) {
+			if ((i == SSDK_PHYSICAL_PORT1) || (i == SSDK_PHYSICAL_PORT4)) {
+				continue;
+			}
+			rv = __adpt_cppe_uniphy_port_disable(dev_id, uniphy_index, i);
+			SW_RTN_ON_ERROR (rv);
+		}
+		/* disable instance0 port 4 clock */
+		qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+					SSDK_PHYSICAL_PORT4, A_FALSE);
+		rv = __adpt_cppe_uniphy_channel_selection_set(dev_id,
+			CPPE_PCS0_CHANNEL0_SEL_SGMIIPLUS,
+			CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK);
+		SW_RTN_ON_ERROR (rv);
+	}
+
+	rv = __adpt_cppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, mode);
+	SW_RTN_ON_ERROR (rv);
+
+	__adpt_cppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
+
+	/* wait uniphy calibration done */
+	rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
+	SW_RTN_ON_ERROR (rv);
+
+	if (mode == PORT_WRAPPER_PSGMII) {
+		rv = hsl_port_phy_serdes_reset(dev_id);
+		SW_RTN_ON_ERROR (rv);
+		/* enable instance0 clock */
+		for (i = SSDK_PHYSICAL_PORT4; i < SSDK_PHYSICAL_PORT6; i++) {
+			qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+				i, A_TRUE);
+		}
+	} else {
+		/* enable instance clock */
+		qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+				SSDK_PHYSICAL_PORT4, A_TRUE);
+	}
+	if (mode == PORT_WRAPPER_PSGMII) {
+		SSDK_DEBUG("cypress uniphy %d psgmii configuration is done!\n", uniphy_index);
+	} else if (mode == PORT_WRAPPER_SGMII_CHANNEL0) {
+		SSDK_DEBUG("cypress uniphy %d sgmii configuration is done!\n", uniphy_index);
+	} else {
+		SSDK_DEBUG("cypress uniphy %d sgmiiplus configuration is done!\n", uniphy_index);
+	}
+
+	return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/Makefile b/qca-ssdk/src/adpt/hppe/Makefile
new file mode 100755
index 0000000..8a81fee
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/Makefile
@@ -0,0 +1,112 @@
+LOC_DIR=src/adpt/hppe
+LIB=ADPT
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=
+
+ifeq (TRUE, $(IN_FDB))
+  SRC_LIST += adpt_hppe_fdb.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+  SRC_LIST += adpt_hppe_mib.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+  SRC_LIST += adpt_hppe_stp.c
+endif
+
+ifeq (TRUE, $(IN_VSI))
+  SRC_LIST += adpt_hppe_vsi.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+  SRC_LIST += adpt_hppe_portctrl.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+  SRC_LIST += adpt_hppe_mirror.c
+endif
+
+ifeq (TRUE, $(IN_TRUNK))
+  SRC_LIST += adpt_hppe_trunk.c
+endif
+
+ifeq (TRUE, $(IN_IP))
+  SRC_LIST += adpt_hppe_ip.c
+endif
+
+ifeq (TRUE, $(IN_FLOW))
+  SRC_LIST += adpt_hppe_flow.c
+endif
+
+ifeq (TRUE, $(IN_QM))
+  SRC_LIST += adpt_hppe_qm.c
+endif
+
+ifeq (TRUE, $(IN_PPPOE))
+  SRC_LIST += adpt_hppe_pppoe.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+  SRC_LIST += adpt_hppe_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_CTRLPKT))
+  SRC_LIST += adpt_hppe_ctrlpkt.c
+endif
+
+ifeq (TRUE, $(IN_SERVCODE))
+  SRC_LIST += adpt_hppe_servcode.c
+endif
+
+ifeq (TRUE, $(IN_RSS_HASH))
+  SRC_LIST += adpt_hppe_rss_hash.c
+endif
+
+ifeq (TRUE, $(IN_SEC))
+  SRC_LIST += adpt_hppe_sec.c
+endif
+
+ifeq (TRUE, $(IN_ACL))
+  SRC_LIST += adpt_hppe_acl.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+  SRC_LIST += adpt_hppe_qos.c
+endif
+
+ifeq (TRUE, $(IN_BM))
+  SRC_LIST += adpt_hppe_bm.c
+endif
+
+ifeq (TRUE, $(IN_SHAPER))
+  SRC_LIST += adpt_hppe_shaper.c
+endif
+
+ifeq (TRUE, $(IN_POLICER))
+  SRC_LIST += adpt_hppe_policer.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+  SRC_LIST += adpt_hppe_misc.c
+endif
+
+ifeq (TRUE, $(IN_UNIPHY))
+  SRC_LIST += adpt_hppe_uniphy.c
+endif
+
+ifeq (TRUE, $(IN_PTP))
+  SRC_LIST += adpt_hppe_ptp.c
+endif
+
+ifeq (, $(findstring HPPE, $(SUPPORT_CHIP)))
+  SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_acl.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_acl.c
new file mode 100755
index 0000000..b0e682c
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_acl.c
@@ -0,0 +1,4013 @@
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "adpt.h"
+#include "adpt_hppe.h"
+#include "hppe_acl_reg.h"
+#include "hppe_acl.h"
+#include <linux/list.h>
+
+#define ADPT_ACL_HPPE_MAC_DA_RULE 0
+#define ADPT_ACL_HPPE_MAC_SA_RULE 1
+#define ADPT_ACL_HPPE_VLAN_RULE 2
+#define ADPT_ACL_HPPE_L2_MISC_RULE 3
+#define ADPT_ACL_HPPE_IPV4_DIP_RULE 4
+#define ADPT_ACL_HPPE_IPV4_SIP_RULE 5
+#define ADPT_ACL_HPPE_IPV6_DIP0_RULE 6
+#define ADPT_ACL_HPPE_IPV6_DIP1_RULE 7
+#define ADPT_ACL_HPPE_IPV6_DIP2_RULE 8
+#define ADPT_ACL_HPPE_IPV6_SIP0_RULE 9
+#define ADPT_ACL_HPPE_IPV6_SIP1_RULE 10
+#define ADPT_ACL_HPPE_IPV6_SIP2_RULE 11
+#define ADPT_ACL_HPPE_IPMISC_RULE 12
+#define ADPT_ACL_HPPE_UDF0_RULE 13
+#define ADPT_ACL_HPPE_UDF1_RULE 14
+#define ADPT_ACL_HPPE_RULE_TYPE_NUM 15
+
+
+#define ADPT_ACL_SW_LIST_NUM 512
+#define ADPT_ACL_HW_LIST_NUM 64
+#define ADPT_ACL_RULE_NUM_PER_LIST 8 /* can change this MACRO to support more rules per ACL list */
+#define ADPT_ACL_ENTRY_NUM_PER_LIST 8
+
+typedef struct{
+	struct list_head list;
+	a_uint16_t rule_id;
+	a_uint8_t rule_type;
+	a_uint8_t rule_hw_entry;
+	a_uint8_t rule_hw_list_id;
+	a_uint8_t ext1_val;
+	a_uint8_t ext2_val;
+	a_uint8_t ext4_val;
+}ADPT_HPPE_ACL_SW_RULE;
+
+typedef struct{
+	struct list_head list;
+	struct list_head list_sw_rule;
+	a_uint32_t list_pri;
+	a_uint16_t list_id;
+}ADPT_HPPE_ACL_SW_LIST;
+
+typedef struct{
+	struct list_head list_sw_list;
+}ADPT_HPPE_ACL_SW_LIST_HEAD;
+
+typedef struct{
+	a_bool_t hw_list_valid;
+	a_uint8_t hw_list_id;
+	a_uint8_t free_hw_entry_bitmap;
+	a_uint8_t free_hw_entry_count;
+}ADPT_HPPE_ACL_HW_LIST;
+
+typedef struct{
+	a_uint8_t mac[6];
+	a_uint32_t is_ip:1;
+	a_uint32_t is_ipv6:1;
+	a_uint32_t is_ethernet:1;
+	a_uint32_t is_snap:1;
+	a_uint32_t is_fake_mac_header:1;
+}ADPT_HPPE_ACL_MAC_RULE;
+typedef struct{
+	a_uint8_t mac_mask[6];
+	a_uint32_t is_ip_mask:1;
+	a_uint32_t is_ipv6_mask:1;
+	a_uint32_t is_ethernet_mask:1;
+	a_uint32_t is_snap_mask:1;
+	a_uint32_t is_fake_mac_header_mask:1;
+}ADPT_HPPE_ACL_MAC_RULE_MASK;
+
+typedef struct{
+	a_uint32_t cvid:12;/*it is min cvid when range is enable*/
+	a_uint32_t reserved:4;
+	a_uint32_t cpcp:3;
+	a_uint32_t cdei:1;
+	a_uint32_t svid:12;
+	a_uint32_t spcp:3;
+	a_uint32_t sdei:1;
+	a_uint32_t ctag_fmt:3;
+	a_uint32_t stag_fmt:3;
+	a_uint32_t vsi:5;
+	a_uint32_t vsi_valid:1;
+	a_uint32_t is_ip:1;
+	a_uint32_t is_ipv6:1;
+	a_uint32_t is_ethernet:1;
+	a_uint32_t is_snap:1;
+	a_uint32_t is_fake_mac_header:1;
+}ADPT_HPPE_ACL_VLAN_RULE;
+
+typedef struct{
+	a_uint32_t cvid_mask:12;/*it is max cvid when range is enable*/
+	a_uint32_t reserved:4;
+	a_uint32_t cpcp_mask:3;
+	a_uint32_t cdei_mask:1;
+	a_uint32_t svid_mask:12;
+	a_uint32_t spcp_mask:3;
+	a_uint32_t sdei_mask:1;
+	a_uint32_t ctag_fmt_mask:3;
+	a_uint32_t stag_fmt_mask:3;
+	a_uint32_t vsi_mask:5;
+	a_uint32_t vsi_valid_mask:1;
+	a_uint32_t is_ip_mask:1;
+	a_uint32_t is_ipv6_mask:1;
+	a_uint32_t is_ethernet_mask:1;
+	a_uint32_t is_snap_mask:1;
+	a_uint32_t is_fake_mac_header_mask:1;
+}ADPT_HPPE_ACL_VLAN_RULE_MASK;
+
+typedef struct{
+	a_uint32_t svid:12;/*it is min svid when range is enable*/
+	a_uint32_t reserved:4;
+	a_uint32_t l2prot:16;
+	a_uint32_t pppoe_sessionid:16;
+	a_uint32_t is_ip:1;
+	a_uint32_t is_ipv6:1;
+	a_uint32_t is_ethernet:1;
+	a_uint32_t is_snap:1;
+	a_uint32_t is_fake_mac_header:1;
+}ADPT_HPPE_ACL_L2MISC_RULE;
+
+typedef struct{
+	a_uint32_t svid_mask:12;/*it is max svid when range is enable*/
+	a_uint32_t reserved:4;
+	a_uint32_t l2prot_mask:16;
+	a_uint32_t pppoe_sessionid_mask:16;
+	a_uint32_t is_ip_mask:1;
+	a_uint32_t is_ipv6_mask:1;
+	a_uint32_t is_ethernet_mask:1;
+	a_uint32_t is_snap_mask:1;
+	a_uint32_t is_fake_mac_header_mask:1;
+}ADPT_HPPE_ACL_L2MISC_RULE_MASK;
+
+typedef struct{
+	a_uint32_t l4_port:16;/*it is min dport when range is enable*/
+	a_uint32_t ip_0:16;
+	a_uint32_t ip_1:16;
+	a_uint32_t l3_fragment:1;
+	a_uint32_t l3_packet_type:3;
+	a_uint32_t is_ip:1;
+	a_uint32_t reserved:11;
+}ADPT_HPPE_ACL_IPV4_RULE;
+
+typedef struct{
+	a_uint32_t l4_port_mask:16;/*it is min dport when range is enable*/
+	a_uint32_t ip_mask_0:16;
+	a_uint32_t ip_mask_1:16;
+	a_uint32_t l3_fragment_mask:1;
+	a_uint32_t l3_packet_type_mask:3;
+	a_uint32_t is_ip_mask:1;
+	a_uint32_t reserved:11;
+}ADPT_HPPE_ACL_IPV4_RULE_MASK;
+
+typedef struct{
+	a_uint32_t udf0:16;
+	a_uint32_t udf1:16;
+	a_uint32_t udf2:16;
+	a_uint32_t udf0_valid:1;
+	a_uint32_t udf1_valid:1;
+	a_uint32_t udf2_valid:1;
+	a_uint32_t is_ipv6:1;
+	a_uint32_t is_ip:1;
+}ADPT_HPPE_ACL_UDF_RULE;
+
+typedef struct{
+	a_uint32_t udf0_mask:16;
+	a_uint32_t udf1_mask:16;
+	a_uint32_t udf2_mask:16;
+	a_uint32_t udf0_valid:1;
+	a_uint32_t udf1_valid:1;
+	a_uint32_t udf2_valid:1;
+	a_uint32_t is_ipv6:1;
+	a_uint32_t is_ip:1;
+}ADPT_HPPE_ACL_UDF_RULE_MASK;
+
+
+typedef struct{
+	a_uint32_t ip_port:16; /*it is port when DIP_2_RULE or SIP_2_RULE*/
+	a_uint32_t ip_ext_1:16;
+	a_uint32_t ip_ext_2:16;
+	a_uint32_t l3_fragment:1;
+	a_uint32_t l3_packet_type:3;
+	a_uint32_t reserved:1;
+}ADPT_HPPE_ACL_IPV6_RULE;
+
+typedef struct{
+	a_uint32_t ip_port_mask:16; /*it is port when DIP_2_RULE or SIP_2_RULE*/
+	a_uint32_t ip_ext_1_mask:16;
+	a_uint32_t ip_ext_2_mask:16;
+	a_uint32_t l3_fragment_mask:1;
+	a_uint32_t l3_packet_type_mask:3;
+	a_uint32_t reserved:1;
+}ADPT_HPPE_ACL_IPV6_RULE_MASK;
+
+typedef struct{
+	a_uint32_t l3_length:16;/*it is min length when range is enable*/
+	a_uint32_t l3_prot:8; /*ipv4 protocol or ipv6 next header*/
+	a_uint32_t l3_dscp_tc:8;
+	a_uint32_t first_fragment:1;
+	a_uint32_t tcp_flags:6;
+	a_uint32_t ipv4_option_state:1;
+	a_uint32_t l3_ttl:2; /*ipv4 ttl, ipv6 hop limit*/
+	a_uint32_t ah_header:1;
+	a_uint32_t esp_header:1;
+	a_uint32_t mobility_header:1;
+	a_uint32_t fragment_header:1;
+	a_uint32_t other_header:1;
+	a_uint32_t reserved0:1;
+	a_uint32_t l3_fragment:1;
+	a_uint32_t is_ipv6:1;
+	a_uint32_t reserved1:3;
+}ADPT_HPPE_ACL_IPMISC_RULE;
+
+typedef struct{
+	a_uint32_t l3_length_mask:16;/*it is max length when range is enable*/
+	a_uint32_t l3_prot_mask:8; /*ipv4 protocol or ipv6 next header*/
+	a_uint32_t l3_dscp_tc_mask:8;
+	a_uint32_t first_fragment_mask:1;
+	a_uint32_t tcp_flags_mask:6;
+	a_uint32_t ipv4_option_state_mask:1;
+	a_uint32_t l3_ttl_mask:2; /*ipv4 ttl, ipv6 hop limit*/
+	a_uint32_t ah_header_mask:1;
+	a_uint32_t esp_header_mask:1;
+	a_uint32_t mobility_header_mask:1;
+	a_uint32_t fragment_header_mask:1;
+	a_uint32_t other_header_mask:1;
+	a_uint32_t reserved0:1;
+	a_uint32_t l3_fragment_mask:1;
+	a_uint32_t is_ipv6_mask:1;
+	a_uint32_t reserved1:3;
+}ADPT_HPPE_ACL_IPMISC_RULE_MASK;
+
+static ADPT_HPPE_ACL_SW_LIST_HEAD g_acl_sw_list[SW_MAX_NR_DEV];
+static ADPT_HPPE_ACL_HW_LIST g_acl_hw_list[SW_MAX_NR_DEV][ADPT_ACL_HW_LIST_NUM];
+static aos_lock_t hppe_acl_lock[SW_MAX_NR_DEV];
+
+const a_uint8_t s_acl_ext2[7][2] = {
+	{0,1},{2,3},{4,5},{6,7},{0,2},{4,6},{0,4}
+};
+typedef struct
+{
+	a_uint8_t num;
+	a_uint8_t ext_1;
+	a_uint8_t ext_2;
+	a_uint8_t ext_4;
+	a_uint8_t entries;
+}ADPT_HPPE_ACL_ENTRY_EXTEND_INFO;
+const ADPT_HPPE_ACL_ENTRY_EXTEND_INFO s_acl_entries[] = {
+	/*num ext_1 ext_2 ext_4 entries*/
+	{1, 0, 0, 0, 0x2},
+	{1, 0, 0, 0, 0x8},
+	{1, 0, 0, 0, 0x20},
+	{1, 0, 0, 0, 0x80},
+	{1, 0, 0, 0, 0x1},
+	{1, 0, 0, 0, 0x4},
+	{1, 0, 0, 0, 0x10},
+	{1, 0, 0, 0, 0x40},
+	{2, 0x1, 0, 0, 0x3},
+	{2, 0x2, 0, 0, 0xc},
+	{2, 0x4, 0, 0, 0x30},
+	{2, 0x8, 0, 0, 0xc0},
+	{2, 0, 0x1, 0, 0x5},
+	{2, 0, 0x2, 0, 0x50},
+	{2, 0, 0, 0x1, 0x11},
+	{3, 0x1, 0x1, 0x0, 0x7},
+	{3, 0x1, 0x0, 0x1, 0x13},
+	{3, 0x2, 0x1, 0x0, 0xd},
+	{3, 0x4, 0x2, 0x0, 0x70},
+	{3, 0x4, 0x0, 0x1, 0x31},
+	{3, 0x8, 0x2, 0x0, 0xd0},
+	{3, 0x0, 0x1, 0x1, 0x15},
+	{3, 0x0, 0x2, 0x1, 0x51},
+	{4, 0x3, 0x1, 0x0, 0xf},
+	{4, 0x5, 0x0, 0x1, 0x33},
+	{4, 0x2, 0x1, 0x1, 0x1d},
+	{4, 0xc, 0x2, 0x0, 0xf0},
+	{4, 0x4, 0x1, 0x1, 0x35},
+	{4, 0x8, 0x2, 0x1, 0xd1},
+	{4, 0x0, 0x3, 0x1, 0x55},
+	{5, 0x3, 0x1, 0x1, 0x1f},
+	{5, 0x6, 0x1, 0x1, 0x3d},
+	{5, 0xc, 0x2, 0x1, 0xf1},
+	{5, 0x8, 0x3, 0x1, 0xd5},
+	{6, 0x7, 0x1, 0x1, 0x3f},
+	{6, 0x6, 0x3, 0x1, 0x7d},
+	{6, 0xc, 0x3, 0x1, 0xf5},
+	{7, 0x7, 0x3, 0x1, 0x7f},
+	{7, 0xe, 0x3, 0x1, 0xfd},
+	{8, 0xf, 0x3, 0x1, 0xff},
+};
+
+static void _adpt_acl_reg_dump(a_uint8_t *reg, a_uint32_t len)
+{
+	a_int32_t i = 0;
+
+	for(i = 0; i < len; i++)
+	{
+		printk(KERN_CONT "%02x ", reg[i]);
+		if((i+1)%32 == 0 || (i == len-1))
+			printk(KERN_CONT "\n");
+	}
+
+	return;
+}
+
+/*type = 0, count all; type = 1 count odd; type = 2 count even*/
+static a_uint32_t _acl_bits_count(a_uint32_t bits, a_uint32_t max, a_uint32_t type)
+{
+	a_uint32_t i = 0, count = 0;
+	while(i < max)
+	{
+		if((bits >> i) &0x1)
+		{
+			if(type == 1)
+			{
+				if(i%2!=0)
+					count++;
+			}
+			else if(type == 2)
+			{
+				if(i%2==0)
+					count++;
+			}
+			else
+				count++;
+		}
+		i++;
+	}
+	return count;
+}
+
+/*type = 0, count all; type = 1 count odd; type = 2 count even*/
+static a_uint32_t _acl_bit_index(a_uint32_t bits, a_uint32_t max, a_uint32_t type)
+{
+	a_uint32_t i = 0;
+	while(i < max)
+	{
+		if((bits >> i) &0x1)
+		{
+			if(type == 1)/*odd*/
+			{
+				if(i%2!=0)
+					break;
+			}
+			else if(type == 2)/*even*/
+			{
+				if(i%2==0)
+					break;
+			}
+			else
+				break;
+		}
+		i++;
+	}
+	if(i<max)
+		return i;
+	return 0xff;
+}
+
+static a_bool_t
+_adpt_acl_zero_addr(const fal_mac_addr_t addr)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 6; i++)
+    {
+        if (addr.uc[i])
+        {
+            return A_FALSE;
+        }
+    }
+    return A_TRUE;
+}
+
+#if 0
+static void _acl_print_extend_slices(a_uint8_t extend,a_uint8_t extend_slices, u_int8_t slice_count)
+{
+	a_uint32_t i;
+	a_uint32_t ext_1=0, ext_2=0, ext_4=0;
+	for(i = 0; i < 8; i++)
+	{
+		if(extend & (1<<i))
+		{
+			if(i==6)
+				ext_4 = 0x1;
+			else if(i<4)
+				ext_1 |= (1<<i);
+			else
+				ext_2 |= (1<<(i%4));
+		}
+	}
+	printk("\n{%d, 0x%x, 0x%x, 0x%x, 0x%x},\n", slice_count, ext_1, ext_2, ext_4, extend_slices);
+}
+static void _acl_slice_ext_bitmap_gen(a_uint32_t ext_n)
+{
+	a_uint32_t i, j;
+	a_uint8_t extend = 0;
+	a_uint8_t full_extend = 0;
+	a_uint8_t extend_slices = 0;
+	a_uint8_t extend_count = 0;
+
+	printk("########ext_n = %d\n", ext_n);
+
+	for(i = 0; i < 7; i++)
+	{
+		extend = (1 << i);
+		extend_slices = (1<<s_acl_ext2[i][0])|(1<<s_acl_ext2[i][1]);
+		extend_count = 2;
+		full_extend = 0;
+		for(j = i+1; j < 7; j++)
+		{
+			int k;
+			if((extend & (1<<j))||(full_extend & (1<<j)))
+			{
+				//printk("extend = %x, full_extend = %x\n", extend, full_extend);
+				continue;
+			}
+			for(k = 0; k < extend_count; k++)
+			{
+				if(extend_slices &(1<<s_acl_ext2[j][0]))
+				{
+					extend |= (1<<j);
+					extend_slices |= (1<<s_acl_ext2[j][1]);
+					extend_count++;
+					break;
+				}
+				else if(extend_slices &(1<<s_acl_ext2[j][1]))
+				{
+					extend |= (1<<j);
+					extend_slices |= (1<<s_acl_ext2[j][0]);
+					extend_count++;
+					break;
+				}
+			}
+			if(extend_count == ext_n)
+			{
+				_acl_print_extend_slices(extend, extend_slices, extend_count);
+				full_extend |= extend;
+				extend_count = 2;
+				extend = (1 << i);
+				extend_slices = (1<<s_acl_ext2[i][0])|(1<<s_acl_ext2[i][1]);
+				j=i;
+			}
+			if(k < extend_count)
+			{
+				j=i;
+			}
+		}
+	}
+}
+#endif
+
+enum{
+	HPPE_ACL_TYPE_PORTBITMAP = 0,
+	HPPE_ACL_TYPE_PORT,
+	HPPE_ACL_TYPE_SERVICE_CODE,
+	HPPE_ACL_TYPE_L3_IF,
+	HPPE_ACL_TYPE_INVALID,
+};
+
+enum{
+	HPPE_ACL_ACTION_FWD = 0,
+	HPPE_ACL_ACTION_DROP,
+	HPPE_ACL_ACTION_COPYCPU,
+	HPPE_ACL_ACTION_RDTCPU,
+};
+
+enum{
+	HPPE_ACL_DEST_INVALID = 0,
+	HPPE_ACL_DEST_NEXTHOP,
+	HPPE_ACL_DEST_PORT_ID,
+	HPPE_ACL_DEST_PORT_BMP,
+};
+
+#define HPPE_ACL_DEST_INFO(type,value) (((type)<<12)|((value)&0xfff))
+#define HPPE_ACL_DEST_TYPE(dest) (((dest)>>12)&0x3)
+#define HPPE_ACL_DEST_VALUE(dest) ((dest)&0xfff)
+
+static a_uint32_t _adpt_hppe_acl_srctype_to_hw(fal_acl_bind_obj_t obj_t)
+{
+	a_uint32_t src_type = HPPE_ACL_TYPE_INVALID;
+
+	switch(obj_t)
+	{
+		case FAL_ACL_BIND_PORTBITMAP:
+			src_type = HPPE_ACL_TYPE_PORTBITMAP;
+			break;
+		case FAL_ACL_BIND_PORT:
+			src_type = HPPE_ACL_TYPE_PORT;
+			break;
+		case FAL_ACL_BIND_SERVICE_CODE:
+			src_type = HPPE_ACL_TYPE_SERVICE_CODE;
+			break;
+		case FAL_ACL_BIND_L3_IF:
+			src_type = HPPE_ACL_TYPE_L3_IF;
+			break;
+	}
+	return src_type;
+}
+
+static sw_error_t
+_adpt_hppe_acl_rule_bind(a_uint32_t dev_id, a_uint32_t list_id, ADPT_HPPE_ACL_SW_RULE *rule_entry,
+	fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx)
+{
+	a_uint32_t hw_index = 0, hw_entries = 0, hw_srctype = 0, hw_list_id = 0;
+	union ipo_rule_reg_u hw_reg = {0};
+
+	hw_entries = rule_entry->rule_hw_entry;
+	hw_list_id = rule_entry->rule_hw_list_id;
+	/* msg for debug */
+	SSDK_DEBUG("ACL bind rule: list_id=%d, rule_id=%d, hw_entries=0x%x, hw_list_id=%d\n",
+		list_id, rule_entry->rule_id, hw_entries, hw_list_id);
+
+	while(hw_entries != 0)
+	{
+		hw_index = _acl_bit_index(hw_entries, ADPT_ACL_ENTRY_NUM_PER_LIST, 0);
+		if(hw_index >= ADPT_ACL_ENTRY_NUM_PER_LIST)
+		{
+			break;
+		}
+
+		hppe_ipo_rule_reg_get(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index,
+			&hw_reg);
+
+		if(obj_t == FAL_ACL_BIND_PORT && obj_idx < SSDK_MAX_PORT_NUM)
+		{
+			/*convert port to bitmap if it is physical port*/
+			obj_t = FAL_ACL_BIND_PORTBITMAP;
+			obj_idx = (1<<obj_idx);
+		}
+
+		hw_srctype = _adpt_hppe_acl_srctype_to_hw(obj_t);
+
+		if(hw_srctype == HPPE_ACL_TYPE_INVALID)
+		{
+			SSDK_ERROR("Invalid source type %d\n", obj_t);
+			return SW_BAD_PARAM;
+		}
+		else if(hw_srctype == HPPE_ACL_TYPE_PORTBITMAP &&
+			hw_reg.bf.src_type == HPPE_ACL_TYPE_PORTBITMAP)
+		{
+			hw_reg.bf.src_0 |= obj_idx&0x7;
+			hw_reg.bf.src_1 |= (obj_idx>>3)&0x1f;
+		}
+		else
+		{
+			hw_reg.bf.src_0 = obj_idx&0x7;
+			hw_reg.bf.src_1 = (obj_idx>>3)&0x1f;
+		}
+		hw_reg.bf.src_type = hw_srctype;
+
+		hppe_ipo_rule_reg_set(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index,
+			&hw_reg);
+		SSDK_DEBUG("ACL bind entry %d source type %d, source value 0x%x\n",
+			hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, obj_t, obj_idx);
+		hw_entries &= (~(1<<hw_index));
+	}
+
+	return SW_OK;
+}
+
+static ADPT_HPPE_ACL_SW_LIST *
+_adpt_hppe_acl_list_entry_get(a_uint32_t dev_id, a_uint32_t list_id)
+{
+	ADPT_HPPE_ACL_SW_LIST *list_entry = NULL;
+	struct list_head *list_pos = NULL;
+
+	list_for_each(list_pos, &g_acl_sw_list[dev_id].list_sw_list)
+	{
+		list_entry = list_entry(list_pos, ADPT_HPPE_ACL_SW_LIST, list);
+		if(list_entry->list_id == list_id)
+		{
+			break;
+		}
+	}
+	if(list_pos == &g_acl_sw_list[dev_id].list_sw_list)
+	{
+		return NULL;
+	}
+	else
+	{
+		return list_entry;
+	}
+}
+
+sw_error_t
+adpt_hppe_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, fal_acl_direc_t direc,
+		fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx)
+{
+	struct list_head *rule_pos = NULL;
+	ADPT_HPPE_ACL_SW_RULE *rule_bind_entry = NULL;
+	ADPT_HPPE_ACL_SW_LIST *list_bind_entry = NULL;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if(list_id >= ADPT_ACL_SW_LIST_NUM)
+	{
+		return SW_OUT_OF_RANGE;
+	}
+
+	aos_lock_bh(&hppe_acl_lock[dev_id]);
+	list_bind_entry = _adpt_hppe_acl_list_entry_get(dev_id, list_id);
+	if(list_bind_entry == NULL)
+	{
+		aos_unlock_bh(&hppe_acl_lock[dev_id]);
+		return SW_NOT_FOUND;
+	}
+
+	list_for_each(rule_pos, &list_bind_entry->list_sw_rule)
+	{
+		rule_bind_entry = list_entry(rule_pos, ADPT_HPPE_ACL_SW_RULE, list);
+		if(rule_bind_entry->rule_hw_entry)
+		{
+			sw_error_t rc;
+			rc = _adpt_hppe_acl_rule_bind(dev_id, list_id, rule_bind_entry,
+					direc, obj_t, obj_idx);
+			if(rc != SW_OK)
+			{
+				SSDK_ERROR("rule %d bind fail\n", rule_bind_entry->rule_id);
+				aos_unlock_bh(&hppe_acl_lock[dev_id]);
+				return SW_FAIL;
+			}
+		}
+	}
+	aos_unlock_bh(&hppe_acl_lock[dev_id]);
+	return SW_OK;
+}
+
+static sw_error_t _adpt_hppe_acl_mac_rule_hw_2_sw(a_uint32_t is_mac_da,
+		union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask, fal_acl_rule_t * rule)
+{
+	ADPT_HPPE_ACL_MAC_RULE *macrule = (ADPT_HPPE_ACL_MAC_RULE *)hw_reg;
+	ADPT_HPPE_ACL_MAC_RULE_MASK *macrule_mask = (ADPT_HPPE_ACL_MAC_RULE_MASK *)hw_mask;
+
+	if(is_mac_da)
+	{
+		rule->dest_mac_val.uc[0] = macrule->mac[5];
+		rule->dest_mac_val.uc[1] = macrule->mac[4];
+		rule->dest_mac_val.uc[2] = macrule->mac[3];
+		rule->dest_mac_val.uc[3] = macrule->mac[2];
+		rule->dest_mac_val.uc[4] = macrule->mac[1];
+		rule->dest_mac_val.uc[5] = macrule->mac[0];
+		rule->dest_mac_mask.uc[0] = macrule_mask->mac_mask[5];
+		rule->dest_mac_mask.uc[1] = macrule_mask->mac_mask[4];
+		rule->dest_mac_mask.uc[2] = macrule_mask->mac_mask[3];
+		rule->dest_mac_mask.uc[3] = macrule_mask->mac_mask[2];
+		rule->dest_mac_mask.uc[4] = macrule_mask->mac_mask[1];
+		rule->dest_mac_mask.uc[5] = macrule_mask->mac_mask[0];
+	}
+	else
+	{
+		rule->src_mac_val.uc[0] = macrule->mac[5];
+		rule->src_mac_val.uc[1] = macrule->mac[4];
+		rule->src_mac_val.uc[2] = macrule->mac[3];
+		rule->src_mac_val.uc[3] = macrule->mac[2];
+		rule->src_mac_val.uc[4] = macrule->mac[1];
+		rule->src_mac_val.uc[5] = macrule->mac[0];
+		rule->src_mac_mask.uc[0] = macrule_mask->mac_mask[5];
+		rule->src_mac_mask.uc[1] = macrule_mask->mac_mask[4];
+		rule->src_mac_mask.uc[2] = macrule_mask->mac_mask[3];
+		rule->src_mac_mask.uc[3] = macrule_mask->mac_mask[2];
+		rule->src_mac_mask.uc[4] = macrule_mask->mac_mask[1];
+		rule->src_mac_mask.uc[5] = macrule_mask->mac_mask[0];
+	}
+	if(A_FALSE == _adpt_acl_zero_addr(rule->dest_mac_mask))
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_DA);
+	}
+	if(A_FALSE == _adpt_acl_zero_addr(rule->src_mac_mask))
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_SA);
+	}
+
+	if(macrule_mask->is_ip_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP);
+		rule->is_ip_val = macrule->is_ip;
+	}
+
+	if(macrule_mask->is_ipv6_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IPV6);
+		rule->is_ipv6_val = macrule->is_ipv6;
+	}
+
+	if(macrule_mask->is_ethernet_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_ETHERNET);
+		rule->is_ethernet_val = macrule->is_ethernet;
+	}
+
+	if(macrule_mask->is_snap_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_SNAP);
+		rule->is_snap_val = macrule->is_snap;
+	}
+
+	if(macrule_mask->is_fake_mac_header_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER);
+		rule->is_fake_mac_header_val = macrule->is_fake_mac_header;
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t _adpt_hppe_acl_vlan_rule_hw_2_sw(union ipo_rule_reg_u *hw_reg,
+		union ipo_mask_reg_u *hw_mask, fal_acl_rule_t * rule)
+{
+	ADPT_HPPE_ACL_VLAN_RULE * vlanrule = (ADPT_HPPE_ACL_VLAN_RULE *)hw_reg;
+	ADPT_HPPE_ACL_VLAN_RULE_MASK *vlanrule_mask = (ADPT_HPPE_ACL_VLAN_RULE_MASK *)hw_mask;
+
+	/*ctag*/
+	if(vlanrule_mask->cvid_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID);
+		rule->ctag_vid_mask = vlanrule_mask->cvid_mask;
+	}
+	if(hw_reg->bf.range_en)
+	{
+		if(vlanrule->cvid == 0)
+		{
+			rule->ctag_vid_op = FAL_ACL_FIELD_LE;
+			rule->ctag_vid_val = vlanrule_mask->cvid_mask;
+		}
+		else if(vlanrule_mask->cvid_mask == 0xfff)
+		{
+			rule->ctag_vid_op = FAL_ACL_FIELD_GE;
+			rule->ctag_vid_val = vlanrule->cvid;
+		}
+		else
+		{
+			rule->ctag_vid_op = FAL_ACL_FIELD_RANGE;
+			rule->ctag_vid_val = vlanrule->cvid;
+		}
+
+	}
+	else
+	{
+		rule->ctag_vid_op = FAL_ACL_FIELD_MASK;
+		rule->ctag_vid_val = vlanrule->cvid;
+	}
+
+	if(vlanrule_mask->cpcp_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI);
+		rule->ctag_pri_val = vlanrule->cpcp;
+		rule->ctag_pri_mask = vlanrule_mask->cpcp_mask;
+	}
+
+	if(vlanrule_mask->cdei_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI);
+		rule->ctag_cfi_val = vlanrule->cdei;
+		rule->ctag_cfi_mask = vlanrule_mask->cdei_mask;
+	}
+
+	if(vlanrule_mask->ctag_fmt_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_CTAGGED);
+		rule->ctagged_val = vlanrule->ctag_fmt;
+		rule->ctagged_mask = vlanrule_mask->ctag_fmt_mask;
+	}
+
+	/*stag*/
+	if(vlanrule_mask->svid_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_VID);
+		rule->stag_vid_val = vlanrule->svid;
+		rule->stag_vid_mask = vlanrule_mask->svid_mask;
+	}
+	if(vlanrule_mask->spcp_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI);
+		rule->stag_pri_val = vlanrule->spcp;
+		rule->stag_pri_mask = vlanrule_mask->spcp_mask;
+	}
+	if(vlanrule_mask->sdei_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI);
+		rule->stag_dei_val = vlanrule->sdei;
+		rule->stag_dei_mask = vlanrule_mask->sdei_mask;
+	}
+	if(vlanrule_mask->stag_fmt_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_STAGGED);
+		rule->stagged_val = vlanrule->stag_fmt;
+		rule->stagged_mask = vlanrule_mask->stag_fmt_mask;
+	}
+	/*vsi*/
+	if(vlanrule_mask->vsi_valid_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_VSI_VALID);
+		rule->vsi_valid = vlanrule->vsi_valid;
+		rule->vsi_valid_mask = vlanrule_mask->vsi_valid_mask;
+	}
+	if(vlanrule_mask->vsi_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_VSI);
+		rule->vsi = vlanrule->vsi;
+		rule->vsi_mask = vlanrule_mask->vsi_mask;
+	}
+
+	if(vlanrule_mask->is_ip_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP);
+		rule->is_ip_val = vlanrule->is_ip;
+	}
+
+	if(vlanrule_mask->is_ipv6_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IPV6);
+		rule->is_ipv6_val = vlanrule->is_ipv6;
+	}
+
+	if(vlanrule_mask->is_ethernet_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_ETHERNET);
+		rule->is_ethernet_val = vlanrule->is_ethernet;
+	}
+
+	if(vlanrule_mask->is_snap_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_SNAP);
+		rule->is_snap_val = vlanrule->is_snap;
+	}
+
+	if(vlanrule_mask->is_fake_mac_header_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER);
+		rule->is_fake_mac_header_val = vlanrule->is_fake_mac_header;
+	}
+
+	return SW_OK;
+}
+static sw_error_t _adpt_hppe_acl_l2_misc_rule_hw_2_sw(union ipo_rule_reg_u *hw_reg,
+		union ipo_mask_reg_u *hw_mask, fal_acl_rule_t * rule)
+{
+	ADPT_HPPE_ACL_L2MISC_RULE * l2misc_rule = (ADPT_HPPE_ACL_L2MISC_RULE *)hw_reg;
+	ADPT_HPPE_ACL_L2MISC_RULE_MASK *l2misc_mask = (ADPT_HPPE_ACL_L2MISC_RULE_MASK *)hw_mask;
+
+	/*stag*/
+	if(l2misc_mask->svid_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_VID);
+		rule->stag_vid_mask = l2misc_mask->svid_mask;
+	}
+	if(hw_reg->bf.range_en)
+	{
+		if(l2misc_rule->svid == 0)
+		{
+			rule->stag_vid_op = FAL_ACL_FIELD_LE;
+			rule->stag_vid_val = l2misc_mask->svid_mask;
+		}
+		else if(l2misc_mask->svid_mask == 0xfff)
+		{
+			rule->stag_vid_op = FAL_ACL_FIELD_GE;
+			rule->stag_vid_val = l2misc_rule->svid;
+		}
+		else
+		{
+			rule->stag_vid_op = FAL_ACL_FIELD_RANGE;
+			rule->stag_vid_val = l2misc_rule->svid;
+		}
+
+	}
+	else
+	{
+		rule->stag_vid_op = FAL_ACL_FIELD_MASK;
+		rule->stag_vid_val = l2misc_rule->svid;
+	}
+
+	if(l2misc_mask->l2prot_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+		rule->ethtype_val = l2misc_rule->l2prot;
+		rule->ethtype_mask = l2misc_mask->l2prot_mask;
+	}
+
+	if(l2misc_mask->pppoe_sessionid_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_PPPOE_SESSIONID);
+		rule->pppoe_sessionid = l2misc_rule->pppoe_sessionid;
+		rule->pppoe_sessionid_mask = l2misc_mask->pppoe_sessionid_mask;
+	}
+
+	if(l2misc_mask->is_ip_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP);
+		rule->is_ip_val = l2misc_rule->is_ip;
+	}
+
+	if(l2misc_mask->is_ipv6_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IPV6);
+		rule->is_ipv6_val = l2misc_rule->is_ipv6;
+	}
+
+	if(l2misc_mask->is_ethernet_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_ETHERNET);
+		rule->is_ethernet_val = l2misc_rule->is_ethernet;
+	}
+
+	if(l2misc_mask->is_snap_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_SNAP);
+		rule->is_snap_val = l2misc_rule->is_snap;
+	}
+
+	if(l2misc_mask->is_fake_mac_header_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER);
+		rule->is_fake_mac_header_val = l2misc_rule->is_fake_mac_header;
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t _adpt_hppe_acl_ipv4_rule_hw_2_sw(a_uint32_t is_ip_da,
+		union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask, fal_acl_rule_t *rule)
+{
+	ADPT_HPPE_ACL_IPV4_RULE * ipv4rule = (ADPT_HPPE_ACL_IPV4_RULE *)hw_reg;
+	ADPT_HPPE_ACL_IPV4_RULE_MASK *ipv4rule_mask = (ADPT_HPPE_ACL_IPV4_RULE_MASK *)hw_mask;
+
+	if(is_ip_da)
+	{
+		if(ipv4rule_mask->ip_mask_0 || ipv4rule_mask->ip_mask_1)
+		{
+			FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP4_DIP);
+			rule->dest_ip4_val = ipv4rule->ip_1<<16|ipv4rule->ip_0;
+			rule->dest_ip4_mask = (ipv4rule_mask->ip_mask_1<<16)|ipv4rule_mask->ip_mask_0;
+		}
+		if(ipv4rule_mask->l4_port_mask)
+		{
+			FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L4_DPORT);
+			rule->dest_l4port_mask = ipv4rule_mask->l4_port_mask;
+		}
+		if(hw_reg->bf.range_en)
+		{
+			if(ipv4rule->l4_port == 0)
+			{
+				rule->dest_l4port_op = FAL_ACL_FIELD_LE;
+				rule->dest_l4port_val = ipv4rule_mask->l4_port_mask;
+			}
+			else if(ipv4rule_mask->l4_port_mask == 0xffff)
+			{
+				rule->dest_l4port_op = FAL_ACL_FIELD_GE;
+				rule->dest_l4port_val = ipv4rule->l4_port;
+			}
+			else
+			{
+				rule->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+				rule->dest_l4port_val = ipv4rule->l4_port;
+			}
+		}
+		else
+		{
+			rule->dest_l4port_op = FAL_ACL_FIELD_MASK;
+			rule->dest_l4port_val = ipv4rule->l4_port;
+		}
+	}
+	else
+	{
+		if(ipv4rule_mask->ip_mask_0 || ipv4rule_mask->ip_mask_1)
+		{
+			FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP4_SIP);
+			rule->src_ip4_val = ipv4rule->ip_1<<16|ipv4rule->ip_0;
+			rule->src_ip4_mask = ipv4rule_mask->ip_mask_1<<16|ipv4rule_mask->ip_mask_0;
+		}
+		if(ipv4rule_mask->l4_port_mask)
+		{
+			FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L4_SPORT);
+			rule->src_l4port_mask = ipv4rule_mask->l4_port_mask;
+		}
+		if(hw_reg->bf.range_en)
+		{
+			if(ipv4rule->l4_port == 0)
+			{
+				rule->src_l4port_op = FAL_ACL_FIELD_LE;
+				rule->src_l4port_val = ipv4rule_mask->l4_port_mask;
+			}
+			else if(ipv4rule_mask->l4_port_mask == 0xffff)
+			{
+				rule->src_l4port_op = FAL_ACL_FIELD_GE;
+				rule->src_l4port_val = ipv4rule->l4_port;
+			}
+			else
+			{
+				rule->src_l4port_op = FAL_ACL_FIELD_RANGE;
+				rule->src_l4port_val = ipv4rule->l4_port;
+			}
+		}
+		else
+		{
+			rule->src_l4port_op = FAL_ACL_FIELD_MASK;
+			rule->src_l4port_val = ipv4rule->l4_port;
+		}
+	}
+
+	if(ipv4rule_mask->is_ip_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP);
+		rule->is_ip_val = ipv4rule->is_ip;
+	}
+	if(ipv4rule_mask->l3_fragment_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT);
+		rule->is_fragement_val = ipv4rule->l3_fragment;
+		rule->is_fragement_mask = ipv4rule_mask->l3_fragment_mask;
+	}
+	if(ipv4rule_mask->l3_packet_type_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP_PKT_TYPE);
+		rule->l3_pkt_type = ipv4rule->l3_packet_type;
+		rule->l3_pkt_type_mask = ipv4rule_mask->l3_packet_type_mask;
+	}
+
+	return SW_OK;
+}
+
+/*ip_bit_range: 0 mean DIP0 or SIP0, 1 mean DIP1 or SIP1, 2 mean DIP2 or SIP2,*/
+static sw_error_t _adpt_hppe_acl_ipv6_rule_hw_2_sw(a_uint32_t is_ip_da, a_uint32_t ip_bit_range,
+		union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask, fal_acl_rule_t *rule)
+{
+	ADPT_HPPE_ACL_IPV6_RULE * ipv6rule = (ADPT_HPPE_ACL_IPV6_RULE *)hw_reg;
+	ADPT_HPPE_ACL_IPV6_RULE_MASK *ipv6rule_mask = (ADPT_HPPE_ACL_IPV6_RULE_MASK *)hw_mask;
+
+	if(is_ip_da)
+	{
+		if(ip_bit_range == 0)
+		{
+			if(ipv6rule_mask->ip_port_mask
+				|| ipv6rule_mask->ip_ext_1_mask
+				|| ipv6rule_mask->ip_ext_2_mask)
+			{
+				FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP6_DIP);
+			}
+
+			rule->dest_ip6_val.ul[3] = ipv6rule->ip_ext_1<<16|ipv6rule->ip_port;
+			rule->dest_ip6_val.ul[2] |= (ipv6rule->ip_ext_2)&0xffff;
+			rule->dest_ip6_mask.ul[3] =
+				ipv6rule_mask->ip_ext_1_mask<<16|ipv6rule_mask->ip_port_mask;
+			rule->dest_ip6_mask.ul[2] |= (ipv6rule_mask->ip_ext_2_mask)&0xffff;
+		}
+		else if(ip_bit_range == 1)
+		{
+			if(ipv6rule_mask->ip_port_mask
+				|| ipv6rule_mask->ip_ext_1_mask
+				|| ipv6rule_mask->ip_ext_2_mask)
+			{
+				FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP6_DIP);
+			}
+			rule->dest_ip6_val.ul[2] |= (ipv6rule->ip_port<<16)&0xffff0000;
+			rule->dest_ip6_val.ul[1] = ipv6rule->ip_ext_2<<16|ipv6rule->ip_ext_1;
+			rule->dest_ip6_mask.ul[2] |= (ipv6rule_mask->ip_port_mask<<16)&0xffff0000;
+			rule->dest_ip6_mask.ul[1] =
+				ipv6rule_mask->ip_ext_2_mask<<16|ipv6rule_mask->ip_ext_1_mask;
+		}
+		else if(ip_bit_range == 2)
+		{
+			if(ipv6rule_mask->ip_ext_1_mask
+				|| ipv6rule_mask->ip_ext_2_mask)
+			{
+				FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP6_DIP);
+				rule->dest_ip6_val.ul[0] =
+					ipv6rule->ip_ext_2<<16|ipv6rule->ip_ext_1;
+				rule->dest_ip6_mask.ul[0] = ipv6rule_mask->ip_ext_2_mask<<16|
+					ipv6rule_mask->ip_ext_1_mask;
+			}
+			if(ipv6rule_mask->ip_port_mask)
+			{
+				FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L4_DPORT);
+				rule->dest_l4port_mask = ipv6rule_mask->ip_port_mask;
+			}
+			if(hw_reg->bf.range_en)
+			{
+				if(ipv6rule->ip_port == 0)
+				{
+					rule->dest_l4port_op = FAL_ACL_FIELD_LE;
+					rule->dest_l4port_val = ipv6rule_mask->ip_port_mask;
+				}
+				else if(ipv6rule_mask->ip_port_mask == 0xffff)
+				{
+					rule->dest_l4port_op = FAL_ACL_FIELD_GE;
+					rule->dest_l4port_val= ipv6rule->ip_port;
+				}
+				else
+				{
+					rule->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+					rule->dest_l4port_val= ipv6rule->ip_port;
+				}
+			}
+			else
+			{
+				rule->dest_l4port_op = FAL_ACL_FIELD_MASK;
+				rule->dest_l4port_val = ipv6rule->ip_port;
+			}
+
+		}
+	}
+	else
+	{
+		if(ip_bit_range == 0)
+		{
+			if(ipv6rule_mask->ip_port_mask
+				|| ipv6rule_mask->ip_ext_1_mask
+				|| ipv6rule_mask->ip_ext_2_mask)
+			{
+				FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP6_SIP);
+			}
+			rule->src_ip6_val.ul[3] = ipv6rule->ip_ext_1<<16|ipv6rule->ip_port;
+			rule->src_ip6_val.ul[2] |= (ipv6rule->ip_ext_2)&0xffff;
+			rule->src_ip6_mask.ul[3] =
+				ipv6rule_mask->ip_ext_1_mask<<16|ipv6rule_mask->ip_port_mask;
+			rule->src_ip6_mask.ul[2] |= (ipv6rule_mask->ip_ext_2_mask)&0xffff;
+		}
+		else if(ip_bit_range == 1)
+		{
+			if(ipv6rule_mask->ip_port_mask
+				|| ipv6rule_mask->ip_ext_1_mask
+				|| ipv6rule_mask->ip_ext_2_mask)
+			{
+				FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP6_SIP);
+			}
+			rule->src_ip6_val.ul[2] |= (ipv6rule->ip_port<<16)&0xffff0000;
+			rule->src_ip6_val.ul[1] = ipv6rule->ip_ext_2<<16|ipv6rule->ip_ext_1;
+			rule->src_ip6_mask.ul[2] |= (ipv6rule_mask->ip_port_mask<<16)&0xffff0000;
+			rule->src_ip6_mask.ul[1] =
+				ipv6rule_mask->ip_ext_2_mask<<16|ipv6rule_mask->ip_ext_1_mask;
+		}
+		else if(ip_bit_range == 2)
+		{
+			if(ipv6rule_mask->ip_ext_1_mask
+				|| ipv6rule_mask->ip_ext_2_mask)
+			{
+				FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP6_SIP);
+				rule->src_ip6_val.ul[0] = ipv6rule->ip_ext_2<<16|ipv6rule->ip_ext_1;
+				rule->src_ip6_mask.ul[0] = ipv6rule_mask->ip_ext_2_mask<<16|
+					ipv6rule_mask->ip_ext_1_mask;
+			}
+			if(ipv6rule_mask->ip_port_mask)
+			{
+				FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L4_SPORT);
+				rule->src_l4port_mask = ipv6rule_mask->ip_port_mask;
+			}
+			if(hw_reg->bf.range_en)
+			{
+				if(ipv6rule->ip_port == 0)
+				{
+					rule->src_l4port_op = FAL_ACL_FIELD_LE;
+					rule->src_l4port_val = ipv6rule_mask->ip_port_mask;
+				}
+				else if(ipv6rule_mask->ip_port_mask == 0xffff)
+				{
+					rule->src_l4port_op = FAL_ACL_FIELD_GE;
+					rule->src_l4port_val= ipv6rule->ip_port;
+				}
+				else
+				{
+					rule->src_l4port_op = FAL_ACL_FIELD_RANGE;
+					rule->src_l4port_val= ipv6rule->ip_port;
+				}
+			}
+			else
+			{
+				rule->src_l4port_op = FAL_ACL_FIELD_MASK;
+				rule->src_l4port_val = ipv6rule->ip_port;
+			}
+
+		}
+	}
+
+	if(ipv6rule_mask->l3_fragment_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT);
+		rule->is_fragement_val = ipv6rule->l3_fragment;
+		rule->is_fragement_mask = ipv6rule_mask->l3_fragment_mask;
+	}
+	if(ipv6rule_mask->l3_packet_type_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP_PKT_TYPE);
+		rule->l3_pkt_type = ipv6rule->l3_packet_type;
+		rule->l3_pkt_type_mask = ipv6rule_mask->l3_packet_type_mask;
+	}
+	return SW_OK;
+}
+
+static sw_error_t _adpt_hppe_acl_ipmisc_rule_hw_2_sw(union ipo_rule_reg_u *hw_reg,
+		union ipo_mask_reg_u *hw_mask, fal_acl_rule_t *rule)
+{
+	ADPT_HPPE_ACL_IPMISC_RULE * ipmisc_rule = (ADPT_HPPE_ACL_IPMISC_RULE *)hw_reg;
+	ADPT_HPPE_ACL_IPMISC_RULE_MASK *ipmisc_mask = (ADPT_HPPE_ACL_IPMISC_RULE_MASK *)hw_mask;
+
+	if(ipmisc_mask->l3_length_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L3_LENGTH);
+		rule->l3_length_mask = ipmisc_mask->l3_length_mask;
+	}
+	if(hw_reg->bf.range_en)
+	{
+		if(ipmisc_rule->l3_length == 0)
+		{
+			rule->l3_length_op = FAL_ACL_FIELD_LE;
+			rule->l3_length = ipmisc_mask->l3_length_mask;
+		}
+		else if(ipmisc_mask->l3_length_mask == 0xffff)
+		{
+			rule->l3_length_op = FAL_ACL_FIELD_GE;
+			rule->l3_length = ipmisc_rule->l3_length;
+		}
+		else
+		{
+			rule->l3_length_op = FAL_ACL_FIELD_RANGE;
+			rule->l3_length = ipmisc_rule->l3_length;
+		}
+	}
+	else
+	{
+		rule->l3_length_op = FAL_ACL_FIELD_MASK;
+		rule->l3_length = ipmisc_rule->l3_length;
+	}
+
+	if(ipmisc_mask->l3_prot_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP_PROTO);
+		rule->ip_proto_val = ipmisc_rule->l3_prot;
+		rule->ip_proto_mask = ipmisc_mask->l3_prot_mask;
+	}
+	if(ipmisc_mask->l3_dscp_tc_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP_DSCP);
+		rule->ip_dscp_val = ipmisc_rule->l3_dscp_tc;
+		rule->ip_dscp_mask = ipmisc_mask->l3_dscp_tc_mask;
+	}
+
+	if(ipmisc_mask->first_fragment_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_FIRST_FRAGMENT);
+		rule->is_first_frag_val = ipmisc_rule->first_fragment;
+	}
+	if(ipmisc_mask->tcp_flags_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_TCP_FLAG);
+		rule->tcp_flag_val = ipmisc_rule->tcp_flags;
+		rule->tcp_flag_mask = ipmisc_mask->tcp_flags_mask;
+	}
+	if(ipmisc_mask->ipv4_option_state_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IPV4_OPTION);
+		rule->is_ipv4_option_val = ipmisc_rule->ipv4_option_state;
+	}
+	if(ipmisc_mask->l3_ttl_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L3_TTL);
+		rule->l3_ttl = ipmisc_rule->l3_ttl;
+		rule->l3_ttl_mask = ipmisc_mask->l3_ttl_mask;
+	}
+	if(ipmisc_mask->ah_header_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_AH_HEADER);
+		rule->is_ah_header_val = ipmisc_rule->ah_header;
+	}
+	if(ipmisc_mask->esp_header_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_ESP_HEADER);
+		rule->is_esp_header_val = ipmisc_rule->esp_header;
+	}
+	if(ipmisc_mask->mobility_header_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MOBILITY_HEADER);
+		rule->is_mobility_header_val = ipmisc_rule->mobility_header;
+	}
+	if(ipmisc_mask->fragment_header_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_FRAGMENT_HEADER);
+		rule->is_fragment_header_val = ipmisc_rule->fragment_header;
+	}
+	if(ipmisc_mask->other_header_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_OTHER_EXT_HEADER);
+		rule->is_other_header_val = ipmisc_rule->other_header;
+	}
+	if(ipmisc_mask->is_ipv6_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IPV6);
+		rule->is_ipv6_val = ipmisc_rule->is_ipv6;
+	}
+	if(ipmisc_mask->l3_fragment_mask)
+	{
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT);
+		rule->is_fragement_val = ipmisc_rule->l3_fragment;
+	}
+	return SW_OK;
+}
+
+static sw_error_t _adpt_hppe_acl_udf_rule_hw_2_sw(union ipo_rule_reg_u *hw_reg, a_uint32_t is_win1,
+		union ipo_mask_reg_u *hw_mask, fal_acl_rule_t *rule)
+{
+	ADPT_HPPE_ACL_UDF_RULE * udfrule = (ADPT_HPPE_ACL_UDF_RULE *)hw_reg;
+	ADPT_HPPE_ACL_UDF_RULE_MASK *udfrule_mask = (ADPT_HPPE_ACL_UDF_RULE_MASK *)hw_mask;
+
+	if(is_win1)
+	{
+		if(udfrule->udf2_valid == 1)
+		{
+			FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_UDF3);
+			rule->udf3_val = udfrule->udf2;
+			rule->udf3_mask = udfrule_mask->udf2_mask;
+		}
+		if(udfrule->udf1_valid == 1)
+		{
+			FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_UDF2);
+			rule->udf2_val = udfrule->udf1;
+			rule->udf2_mask = udfrule_mask->udf1_mask;
+		}
+		if(udfrule->udf0_valid == 1)
+		{
+			FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_UDF1);
+			if(hw_reg->bf.range_en == 1)
+			{
+				if(udfrule->udf0 == 0)
+				{
+					rule->udf1_op = FAL_ACL_FIELD_LE;
+					rule->udf1_val = udfrule_mask->udf0_mask;
+				}
+				else if(rule->udf1_mask == 0xffff)
+				{
+					rule->udf1_op = FAL_ACL_FIELD_GE;
+					rule->udf1_val = udfrule->udf0;
+				}
+				else
+				{
+					rule->udf1_op = FAL_ACL_FIELD_RANGE;
+					rule->udf1_val = udfrule->udf0;
+					rule->udf1_mask = udfrule_mask->udf0_mask;
+				}
+			}
+			else
+			{
+				rule->udf1_op = FAL_ACL_FIELD_MASK;
+				rule->udf1_val = udfrule->udf0;
+				rule->udf1_mask = udfrule_mask->udf0_mask;
+			}
+
+		}
+	}
+	else
+	{
+		if(udfrule->udf2_valid == 1)
+		{
+			FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_UDF2);
+			rule->udf2_val = udfrule->udf2;
+			rule->udf2_mask = udfrule_mask->udf2_mask;
+		}
+		if(udfrule->udf1_valid == 1)
+		{
+			FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_UDF1);
+			rule->udf1_val = udfrule->udf1;
+			rule->udf1_mask = udfrule_mask->udf1_mask;
+		}
+		if(udfrule->udf0_valid == 1)
+		{
+			FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_UDF0);
+			if(hw_reg->bf.range_en == 1)
+			{
+				if(udfrule->udf0 == 0)
+				{
+					rule->udf0_op = FAL_ACL_FIELD_LE;
+					rule->udf0_val = udfrule_mask->udf0_mask;
+				}
+				else if(rule->udf0_mask == 0xffff)
+				{
+					rule->udf0_op = FAL_ACL_FIELD_GE;
+					rule->udf0_val = udfrule->udf0;
+				}
+				else
+				{
+					rule->udf0_op = FAL_ACL_FIELD_RANGE;
+					rule->udf0_val = udfrule->udf0;
+					rule->udf0_mask = udfrule_mask->udf0_mask;
+				}
+			}
+			else
+			{
+				rule->udf0_op = FAL_ACL_FIELD_MASK;
+				rule->udf0_val = udfrule->udf0;
+				rule->udf0_mask = udfrule_mask->udf0_mask;
+			}
+
+		}
+	}
+
+	if(udfrule_mask->is_ip)
+	{
+		rule->is_ip_val = udfrule->is_ip;
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP);
+	}
+	if(udfrule_mask->is_ipv6)
+	{
+		udfrule->is_ipv6= rule->is_ipv6_val;
+		FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IPV6);
+	}
+	return SW_OK;
+}
+
+static sw_error_t
+_adpt_hppe_acl_action_hw_2_sw(a_uint32_t dev_id,union ipo_action_u *hw_act, fal_acl_rule_t *rule)
+{
+	if(hw_act->bf.dest_info_change_en)
+	{
+		a_uint32_t dest_type = HPPE_ACL_DEST_TYPE(hw_act->bf.dest_info);
+		a_uint32_t dest_val = HPPE_ACL_DEST_VALUE(hw_act->bf.dest_info);
+		SSDK_DEBUG("hw_act->bf.dest_info = %x\n", hw_act->bf.dest_info);
+		if(dest_type == HPPE_ACL_DEST_NEXTHOP) /*nexthop*/
+		{
+			rule->ports = FAL_ACL_DEST_OFFSET(FAL_ACL_DEST_NEXTHOP,
+					dest_val);
+		}
+		else if(dest_type == HPPE_ACL_DEST_PORT_ID) /*vp or trunk*/
+		{
+			rule->ports = FAL_ACL_DEST_OFFSET(FAL_ACL_DEST_PORT_ID,
+					dest_val);
+		}
+		else if(dest_type == HPPE_ACL_DEST_PORT_BMP) /*bitmap*/
+		{
+			rule->ports = FAL_ACL_DEST_OFFSET(FAL_ACL_DEST_PORT_BMP,
+					dest_val);
+		}
+		if(rule->ports != 0)
+		{
+			FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REDPT);
+		}
+		else if(hw_act->bf.fwd_cmd == HPPE_ACL_ACTION_RDTCPU)
+		{
+			FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_RDTCPU);
+		}
+		else if(hw_act->bf.fwd_cmd == HPPE_ACL_ACTION_COPYCPU)
+		{
+			FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_CPYCPU);
+		}
+		else if(hw_act->bf.fwd_cmd == HPPE_ACL_ACTION_DROP)
+		{
+			FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_DENY);
+		}
+		else if(hw_act->bf.fwd_cmd == HPPE_ACL_ACTION_FWD)
+		{
+			FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_PERMIT);
+		}
+	}
+
+	if(hw_act->bf.mirror_en == 1)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_MIRROR);
+	}
+	if(hw_act->bf.bypass_bitmap_0 != 0 ||
+		hw_act->bf.bypass_bitmap_1 != 0)
+	{
+		rule->bypass_bitmap = (hw_act->bf.bypass_bitmap_1<<14)|hw_act->bf.bypass_bitmap_0;
+	}
+	if(hw_act->bf.svid_change_en == 1)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID);
+		rule->stag_fmt = hw_act->bf.stag_fmt;
+		rule->stag_vid = hw_act->bf.svid;
+	}
+	if(hw_act->bf.stag_pcp_change_en == 1)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI);
+		rule->stag_pri = hw_act->bf.stag_pcp;
+	}
+	if(hw_act->bf.stag_dei_change_en == 1)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI);
+		rule->stag_dei = hw_act->bf.stag_dei;
+	}
+	if(hw_act->bf.cvid_change_en == 1)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID);
+		rule->ctag_fmt = hw_act->bf.ctag_fmt;
+		rule->ctag_vid = hw_act->bf.cvid;
+	}
+	if(hw_act->bf.ctag_pcp_change_en == 1)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI);
+		rule->ctag_pri = (hw_act->bf.ctag_pcp_1<<2)|hw_act->bf.ctag_pcp_0;
+	}
+	if(hw_act->bf.ctag_dei_change_en == 1)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI);
+		rule->ctag_cfi = hw_act->bf.ctag_dei;
+	}
+	if(hw_act->bf.dscp_tc_change_en == 1)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_DSCP);
+		rule->dscp = hw_act->bf.dscp_tc;
+#if defined(CPPE)
+		if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
+		{
+			rule->dscp_mask = hw_act->bf.dscp_tc_mask;
+		}
+#endif
+	}
+	if(hw_act->bf.int_dp_change_en == 1)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_INT_DP);
+		rule->int_dp = hw_act->bf.int_dp;
+	}
+	if(hw_act->bf.policer_en == 1)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_POLICER_EN);
+		rule->policer_ptr = hw_act->bf.policer_index;
+	}
+	if(hw_act->bf.qid_en == 1)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_QUEUE);
+		rule->queue = hw_act->bf.qid;
+	}
+	if(hw_act->bf.enqueue_pri_change_en == 1)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_ENQUEUE_PRI);
+		rule->enqueue_pri = hw_act->bf.enqueue_pri;
+	}
+	if(hw_act->bf.service_code_en == 1)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_SERVICE_CODE);
+		rule->service_code = (hw_act->bf.service_code_1<<1)|hw_act->bf.service_code_0;
+	}
+	if(hw_act->bf.syn_toggle)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_SYN_TOGGLE);
+	}
+	if(hw_act->bf.cpu_code_en == 1)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_CPU_CODE);
+		rule->cpu_code = hw_act->bf.cpu_code;
+	}
+	if(hw_act->bf.metadata_en == 1)
+	{
+		FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_METADATA_EN);
+	}
+#if defined(CPPE)
+	if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
+	{
+		rule->qos_res_prec = hw_act->bf.qos_res_prec;
+	}
+#endif
+	return SW_OK;
+}
+sw_error_t
+adpt_hppe_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+		fal_acl_rule_t * rule)
+{
+	sw_error_t rv = 0;
+	a_uint32_t hw_index = 0, hw_entries = 0, hw_list_id = 0;
+	union ipo_rule_reg_u hw_reg = {0};
+	union ipo_mask_reg_u hw_mask = {0};
+	union ipo_action_u hw_act = {0};
+	union ipo_cnt_tbl_u hw_match = {0};
+	struct list_head *rule_pos = NULL;
+	ADPT_HPPE_ACL_SW_RULE *rule_query_entry = NULL;
+	ADPT_HPPE_ACL_SW_LIST *list_query_entry = NULL;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(rule);
+
+	if(list_id >= ADPT_ACL_SW_LIST_NUM)
+	{
+		return SW_OUT_OF_RANGE;
+	}
+
+	if(rule_id >= ADPT_ACL_RULE_NUM_PER_LIST)
+	{
+		return SW_OUT_OF_RANGE;
+	}
+
+	aos_lock_bh(&hppe_acl_lock[dev_id]);
+	list_query_entry = _adpt_hppe_acl_list_entry_get(dev_id, list_id);
+	if(list_query_entry == NULL)
+	{
+		aos_unlock_bh(&hppe_acl_lock[dev_id]);
+		return SW_NOT_FOUND;
+	}
+
+	list_for_each(rule_pos, &list_query_entry->list_sw_rule)
+	{
+		rule_query_entry = list_entry(rule_pos, ADPT_HPPE_ACL_SW_RULE, list);
+		if((rule_query_entry->rule_id == rule_id) && (rule_query_entry->rule_hw_entry != 0))
+		{
+			rule->rule_type = rule_query_entry->rule_type;
+			hw_entries = rule_query_entry->rule_hw_entry;
+			hw_list_id = rule_query_entry->rule_hw_list_id;
+			break;
+		}
+	}
+	if(rule_pos == &list_query_entry->list_sw_rule)
+	{
+		aos_unlock_bh(&hppe_acl_lock[dev_id]);
+		return SW_NOT_FOUND;
+	}
+	aos_unlock_bh(&hppe_acl_lock[dev_id]);
+
+	hw_index = _acl_bit_index(hw_entries, ADPT_ACL_ENTRY_NUM_PER_LIST, 0);
+	if(hw_index >= ADPT_ACL_ENTRY_NUM_PER_LIST)
+	{
+		return SW_FAIL;
+	}
+	hppe_ipo_cnt_tbl_get(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, &hw_match);
+
+	rule->match_cnt = hw_match.bf.hit_pkt_cnt;
+	rule->match_bytes = hw_match.bf.hit_byte_cnt_1;
+	rule->match_bytes = rule->match_bytes<<32|hw_match.bf.hit_byte_cnt_0;
+	while(hw_entries != 0)
+	{
+		hw_index = _acl_bit_index(hw_entries, ADPT_ACL_ENTRY_NUM_PER_LIST, 0);
+		if(hw_index >= ADPT_ACL_ENTRY_NUM_PER_LIST)
+		{
+			break;
+		}
+		rv |= hppe_ipo_rule_reg_get(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index,
+			&hw_reg);
+		rv |= hppe_ipo_mask_reg_get(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index,
+			&hw_mask);
+		rv |= hppe_ipo_action_get(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index,
+			&hw_act);
+		rule->post_routing = hw_reg.bf.post_routing_en;
+		rule->acl_pool = hw_reg.bf.res_chain;
+		rule->pri = hw_reg.bf.pri&0x7;
+
+		if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_MAC_DA_RULE)
+		{
+			_adpt_hppe_acl_mac_rule_hw_2_sw(1, &hw_reg, &hw_mask, rule);
+		}
+		if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_MAC_SA_RULE)
+		{
+			_adpt_hppe_acl_mac_rule_hw_2_sw(0, &hw_reg, &hw_mask, rule);
+		}
+		if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_VLAN_RULE)
+		{
+			_adpt_hppe_acl_vlan_rule_hw_2_sw(&hw_reg, &hw_mask, rule);
+		}
+		if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_L2_MISC_RULE)
+		{
+			_adpt_hppe_acl_l2_misc_rule_hw_2_sw(&hw_reg, &hw_mask, rule);
+		}
+		if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV4_DIP_RULE)
+		{
+			_adpt_hppe_acl_ipv4_rule_hw_2_sw(1, &hw_reg, &hw_mask, rule);
+		}
+		if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV4_SIP_RULE)
+		{
+			_adpt_hppe_acl_ipv4_rule_hw_2_sw(0, &hw_reg, &hw_mask, rule);
+		}
+		if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV6_DIP0_RULE)
+		{
+			_adpt_hppe_acl_ipv6_rule_hw_2_sw(1, 0, &hw_reg, &hw_mask, rule);
+		}
+		if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV6_DIP1_RULE)
+		{
+			_adpt_hppe_acl_ipv6_rule_hw_2_sw(1, 1, &hw_reg, &hw_mask, rule);
+		}
+		if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV6_DIP2_RULE)
+		{
+			_adpt_hppe_acl_ipv6_rule_hw_2_sw(1, 2, &hw_reg, &hw_mask, rule);
+		}
+		if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV6_SIP0_RULE)
+		{
+			_adpt_hppe_acl_ipv6_rule_hw_2_sw(0, 0, &hw_reg, &hw_mask, rule);
+		}
+		if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV6_SIP1_RULE)
+		{
+			_adpt_hppe_acl_ipv6_rule_hw_2_sw(0, 1, &hw_reg, &hw_mask, rule);
+		}
+		if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV6_SIP2_RULE)
+		{
+			_adpt_hppe_acl_ipv6_rule_hw_2_sw(0, 2, &hw_reg, &hw_mask, rule);
+		}
+		if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPMISC_RULE)
+		{
+			_adpt_hppe_acl_ipmisc_rule_hw_2_sw(&hw_reg, &hw_mask, rule);
+		}
+		if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_UDF0_RULE)
+		{
+			_adpt_hppe_acl_udf_rule_hw_2_sw(&hw_reg, 0, &hw_mask, rule);
+		}
+		if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_UDF1_RULE)
+		{
+			_adpt_hppe_acl_udf_rule_hw_2_sw(&hw_reg, 1, &hw_mask, rule);
+		}
+
+		if(hw_reg.bf.inverse_en == 1)
+		{
+			FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+		}
+
+		_adpt_hppe_acl_action_hw_2_sw(dev_id,&hw_act, rule);
+		hw_entries &= (~(1<<hw_index));
+	}
+
+	return SW_OK;
+}
+static sw_error_t
+_adpt_hppe_acl_rule_unbind(a_uint32_t dev_id, a_uint32_t list_id, ADPT_HPPE_ACL_SW_RULE *rule_entry,
+	fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx)
+{
+	a_uint32_t hw_index = 0, hw_entries = 0, hw_list_id = 0;
+	union ipo_rule_reg_u hw_reg = {0};
+
+	hw_entries = rule_entry->rule_hw_entry;
+	hw_list_id = rule_entry->rule_hw_list_id;
+	/* msg for debug */
+	SSDK_DEBUG("ACL unbind rule: list_id=%d, rule_id=%d, hw_entries=0x%x, hw_list_id=%d\n",
+		list_id, rule_entry->rule_id, hw_entries, hw_list_id);
+
+	while(hw_entries != 0)
+	{
+		hw_index = _acl_bit_index(hw_entries, ADPT_ACL_ENTRY_NUM_PER_LIST, 0);
+		if(hw_index >= ADPT_ACL_ENTRY_NUM_PER_LIST)
+		{
+			break;
+		}
+
+		hppe_ipo_rule_reg_get(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index,
+			&hw_reg);
+
+		if(obj_t == FAL_ACL_BIND_PORT && obj_idx < SSDK_MAX_PORT_NUM)
+		{
+			/*convert port to bitmap if it is physical port*/
+			obj_t = FAL_ACL_BIND_PORTBITMAP;
+			obj_idx = (1<<obj_idx);
+		}
+
+		if(hw_reg.bf.src_type != _adpt_hppe_acl_srctype_to_hw(obj_t))
+		{
+			SSDK_ERROR("ACL unbind fail obj_t %d\n", obj_t);
+			return SW_NOT_FOUND;
+		}
+		if(hw_reg.bf.src_type == HPPE_ACL_TYPE_PORTBITMAP)
+		{
+			hw_reg.bf.src_0 &= ((~obj_idx)&0x7);
+			hw_reg.bf.src_1 &= ((~(obj_idx>>3))&0x1f);
+		}
+		else
+		{
+			hw_reg.bf.src_type = HPPE_ACL_TYPE_PORTBITMAP;
+			hw_reg.bf.src_0 = 0;
+			hw_reg.bf.src_1 = 0;
+		}
+		hppe_ipo_rule_reg_set(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index,
+			&hw_reg);
+		SSDK_DEBUG("ACL unbind entry %d source type %d, source value 0x%x\n",
+			hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, obj_t, obj_idx);
+		hw_entries &= (~(1<<hw_index));
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, fal_acl_direc_t direc,
+		fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx)
+{
+	struct list_head *rule_pos = NULL;
+	ADPT_HPPE_ACL_SW_RULE *rule_unbind_entry = NULL;
+	ADPT_HPPE_ACL_SW_LIST *list_unbind_entry = NULL;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if(list_id >= ADPT_ACL_SW_LIST_NUM)
+	{
+		return SW_OUT_OF_RANGE;
+	}
+
+	aos_lock_bh(&hppe_acl_lock[dev_id]);
+	list_unbind_entry = _adpt_hppe_acl_list_entry_get(dev_id, list_id);
+	if(list_unbind_entry != NULL)
+	{
+		list_for_each(rule_pos, &list_unbind_entry->list_sw_rule)
+		{
+			rule_unbind_entry = list_entry(rule_pos, ADPT_HPPE_ACL_SW_RULE, list);
+			if(rule_unbind_entry->rule_hw_entry)
+			{
+				_adpt_hppe_acl_rule_unbind(dev_id, list_id, rule_unbind_entry,
+						direc, obj_t, obj_idx);
+			}
+		}
+	}
+	aos_unlock_bh(&hppe_acl_lock[dev_id]);
+	return SW_OK;
+}
+sw_error_t
+adpt_hppe_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+		a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	return SW_NOT_SUPPORTED;
+}
+
+static sw_error_t _adpt_hppe_acl_rule_range_match(a_uint32_t dev_id, a_uint32_t hw_list_index,
+		a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule, a_uint8_t entries)
+{
+	a_uint8_t rangecount = 0, even_entry_count = 0;
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_VID))
+	{
+		if (FAL_ACL_FIELD_MASK != rule->stag_vid_op)
+		{
+			rangecount++;
+		}
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID))
+	{
+		if (FAL_ACL_FIELD_MASK != rule->ctag_vid_op)
+		{
+			rangecount++;
+		}
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_DPORT))
+	{
+		if (FAL_ACL_FIELD_MASK != rule->dest_l4port_op)
+		{
+			rangecount++;
+		}
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_SPORT))
+	{
+		if (FAL_ACL_FIELD_MASK != rule->src_l4port_op)
+		{
+			rangecount++;
+		}
+	}
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_LENGTH))
+	{
+		if (FAL_ACL_FIELD_MASK != rule->l3_length_op)
+		{
+			rangecount++;
+		}
+	}
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF0))
+	{
+		if (FAL_ACL_FIELD_MASK != rule->udf0_op)
+		{
+			rangecount++;
+		}
+	}
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF1))
+	{
+		if (FAL_ACL_FIELD_MASK != rule->udf1_op)
+		{
+			rangecount++;
+		}
+	}
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+	{
+		if (FAL_ACL_FIELD_MASK != rule->icmp_type_code_op)
+		{
+			rangecount++;
+		}
+	}
+
+	even_entry_count = _acl_bits_count(entries, ADPT_ACL_ENTRY_NUM_PER_LIST, 2);
+
+	if(rangecount <= even_entry_count)
+	{
+		return SW_OK;
+	}
+	return SW_NO_RESOURCE;
+}
+sw_error_t _adpt_hppe_acl_alloc_entries(a_uint32_t dev_id, a_uint32_t *hw_list_index,
+			a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule,
+			a_uint32_t rule_type_map, a_uint32_t rule_type_count, a_uint32_t *index)
+{
+	a_uint8_t free_hw_entry_bitmap = 0, free_hw_entry_count = 0, i = 0;
+	a_uint32_t j = 0;
+	a_uint8_t map_info_count = sizeof(s_acl_entries)/sizeof(ADPT_HPPE_ACL_ENTRY_EXTEND_INFO);
+
+	for(j = 0 ; j < ADPT_ACL_HW_LIST_NUM; j++)
+	{
+		free_hw_entry_bitmap = g_acl_hw_list[dev_id][j].free_hw_entry_bitmap;
+		free_hw_entry_count = g_acl_hw_list[dev_id][j].free_hw_entry_count;
+		/* msg for debug */
+		SSDK_DEBUG("_adpt_hppe_acl_alloc_entries():hw_list_index=%d, hw_list_id=%d, "
+			"free_hw_entry_bitmap=0x%x, free_hw_entry_count=%d\n", j,
+			g_acl_hw_list[dev_id][j].hw_list_id, free_hw_entry_bitmap,
+			free_hw_entry_count);
+		if(free_hw_entry_count < rule_type_count)
+		{
+			continue;
+		}
+		for(i = 0; i < map_info_count; i++)
+		{
+			if((rule_type_count == s_acl_entries[i].num) &&
+				((free_hw_entry_bitmap & s_acl_entries[i].entries) ==
+				s_acl_entries[i].entries))
+			{
+				if(SW_OK == _adpt_hppe_acl_rule_range_match(dev_id, j,
+						rule_id, rule_nr, rule, s_acl_entries[i].entries))
+				{
+					SSDK_DEBUG("\n{%d, 0x%x, 0x%x, 0x%x, 0x%x},\n",
+						s_acl_entries[i].num, s_acl_entries[i].ext_1,
+						s_acl_entries[i].ext_2, s_acl_entries[i].ext_4,
+						s_acl_entries[i].entries);
+					*index = i;
+					*hw_list_index = j;
+					return SW_OK;
+				}
+			}
+		}
+	}
+	return SW_NO_RESOURCE;
+}
+
+static sw_error_t
+_adpt_hppe_acl_l2_fields_check(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr,
+				fal_acl_rule_t * rule, a_uint32_t *rule_type_map)
+{
+	a_uint32_t l2_rule_type_map = 0;
+	SSDK_DEBUG("fields[0] = 0x%x, fields[1] = 0x%x\n", rule->field_flg[0], rule->field_flg[1]);
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_DA))
+	{
+		SSDK_DEBUG("select MAC DA rule\n");
+		l2_rule_type_map |= (1<<ADPT_ACL_HPPE_MAC_DA_RULE);
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_SA))
+	{
+		SSDK_DEBUG("select MAC SA rule\n");
+		l2_rule_type_map |= (1<<ADPT_ACL_HPPE_MAC_SA_RULE);
+	}
+	if((FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI)) ||
+		(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI)) ||
+		(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAGGED)) ||
+		(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID)) ||
+		(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI)) ||
+		(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI)) ||
+		(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAGGED)) ||
+		(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_VSI)) ||
+		(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_VSI_VALID)))
+	{
+		SSDK_DEBUG("select VLAN rule\n");
+		l2_rule_type_map |= (1<<ADPT_ACL_HPPE_VLAN_RULE);
+	}
+
+	if((FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE)) ||
+		(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_PPPOE_SESSIONID)) ||
+		((FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_VID)) &&
+		(rule->stag_vid_op != FAL_ACL_FIELD_MASK)))
+	{
+		SSDK_DEBUG("select L2 MISC rule\n");
+		l2_rule_type_map |= (1<<ADPT_ACL_HPPE_L2_MISC_RULE);
+	}
+
+	if(!((l2_rule_type_map & (1<<ADPT_ACL_HPPE_VLAN_RULE))||
+		(l2_rule_type_map & (1<<ADPT_ACL_HPPE_L2_MISC_RULE))))
+	{
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_VID))
+		{
+				SSDK_DEBUG("select VLAN rule\n");
+				l2_rule_type_map |= (1<<ADPT_ACL_HPPE_VLAN_RULE);
+		}
+	}
+
+	if(l2_rule_type_map == 0)
+	{
+		if((FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_SNAP)) ||
+			(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ETHERNET)) ||
+			(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER)))
+		{
+			SSDK_DEBUG("select MAC DA rule\n");
+			l2_rule_type_map |= (1<<ADPT_ACL_HPPE_MAC_DA_RULE);
+		}
+	}
+
+	*rule_type_map |= l2_rule_type_map;
+	SSDK_DEBUG("rule_type_map = 0x%x\n", *rule_type_map);
+
+	return SW_OK;
+}
+static sw_error_t
+_adpt_hppe_acl_ipv4_fields_check(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr,
+				fal_acl_rule_t * rule, a_uint32_t *rule_type_map)
+{
+	SSDK_DEBUG("fields[0] = 0x%x, fields[1] = 0x%x\n",
+				rule->field_flg[0], rule->field_flg[1]);
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_SPORT) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP4_SIP) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_TYPE) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_CODE))
+	{
+		*rule_type_map |= (1<<ADPT_ACL_HPPE_IPV4_SIP_RULE);
+	}
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_DPORT) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP4_DIP))
+	{
+		*rule_type_map |= (1<<ADPT_ACL_HPPE_IPV4_DIP_RULE);
+	}
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_LENGTH) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_DSCP) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FIRST_FRAGMENT) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_TCP_FLAG) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IPV4_OPTION) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_TTL) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_AH_HEADER) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ESP_HEADER) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_PROTO))
+	{
+		*rule_type_map |= (1<<ADPT_ACL_HPPE_IPMISC_RULE);
+	}
+	if((!(*rule_type_map & (1<<ADPT_ACL_HPPE_IPV4_DIP_RULE))) &&
+		(!(*rule_type_map & (1<<ADPT_ACL_HPPE_IPV4_SIP_RULE))))
+	{/*both dip and sip rule are not selected, but ip_pkt_type field selected*/
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_PKT_TYPE))
+		{
+			*rule_type_map |= (1<<ADPT_ACL_HPPE_IPV4_DIP_RULE);
+		}
+	}
+	if(*rule_type_map == 0)
+	{
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT))
+		{
+			*rule_type_map |= (1<<ADPT_ACL_HPPE_IPV4_DIP_RULE);
+		}
+	}
+
+	SSDK_DEBUG("rule_type_map = 0x%x\n", *rule_type_map);
+	return SW_OK;
+}
+
+static sw_error_t
+_adpt_hppe_acl_ipv6_fields_check(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr,
+				fal_acl_rule_t * rule, a_uint32_t *rule_type_map)
+{
+	SSDK_DEBUG("fields[0] = 0x%x, fields[1] = 0x%x\n",
+				rule->field_flg[0], rule->field_flg[1]);
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_SPORT) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_TYPE) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_CODE))
+	{
+		*rule_type_map |= (1<<ADPT_ACL_HPPE_IPV6_SIP2_RULE);
+	}
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP6_SIP))
+	{
+		if(rule->src_ip6_mask.ul[3] != 0 || rule->src_ip6_mask.ul[2]&0x0000ffff)
+			*rule_type_map |= (1<<ADPT_ACL_HPPE_IPV6_SIP0_RULE);
+		if(rule->src_ip6_mask.ul[1] != 0 || rule->src_ip6_mask.ul[2]&0xffff0000)
+			*rule_type_map |= (1<<ADPT_ACL_HPPE_IPV6_SIP1_RULE);
+		if(rule->src_ip6_mask.ul[0] != 0 )
+			*rule_type_map |= (1<<ADPT_ACL_HPPE_IPV6_SIP2_RULE);
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_DPORT))
+	{
+		*rule_type_map |= (1<<ADPT_ACL_HPPE_IPV6_DIP2_RULE);
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP6_DIP))
+	{
+		if(rule->dest_ip6_mask.ul[3] != 0 || rule->dest_ip6_mask.ul[2]&0x0000ffff)
+			*rule_type_map |= (1<<ADPT_ACL_HPPE_IPV6_DIP0_RULE);
+		if(rule->dest_ip6_mask.ul[1] != 0 || rule->dest_ip6_mask.ul[2]&0xffff0000)
+			*rule_type_map |= (1<<ADPT_ACL_HPPE_IPV6_DIP1_RULE);
+		if(rule->dest_ip6_mask.ul[0] != 0 )
+			*rule_type_map |= (1<<ADPT_ACL_HPPE_IPV6_DIP2_RULE);
+	}
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_LENGTH) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_DSCP) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FIRST_FRAGMENT) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_TCP_FLAG) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_TTL) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT)||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ESP_HEADER) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MOBILITY_HEADER) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FRAGMENT_HEADER)||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_OTHER_EXT_HEADER)||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_AH_HEADER) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_PROTO))
+	{
+		*rule_type_map |= (1<<ADPT_ACL_HPPE_IPMISC_RULE);
+	}
+
+	if((!(*rule_type_map & (1<<ADPT_ACL_HPPE_IPV6_DIP0_RULE))) &&
+		(!(*rule_type_map & (1<<ADPT_ACL_HPPE_IPV6_DIP1_RULE))) &&
+		(!(*rule_type_map & (1<<ADPT_ACL_HPPE_IPV6_DIP2_RULE))) &&
+		(!(*rule_type_map & (1<<ADPT_ACL_HPPE_IPV6_SIP0_RULE))) &&
+		(!(*rule_type_map & (1<<ADPT_ACL_HPPE_IPV6_SIP1_RULE))) &&
+		(!(*rule_type_map & (1<<ADPT_ACL_HPPE_IPV6_SIP2_RULE))))
+	{/*both dip and sip rule are not selected, but ip_pkt_type field selected*/
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_PKT_TYPE))
+		{
+			*rule_type_map |= (1<<ADPT_ACL_HPPE_IPV6_DIP0_RULE);
+		}
+	}
+
+	if(*rule_type_map == 0)
+	{
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT))
+		{
+			*rule_type_map |= (1<<ADPT_ACL_HPPE_IPV6_DIP0_RULE);
+		}
+	}
+
+	SSDK_DEBUG("rule_type_map = 0x%x\n", *rule_type_map);
+
+	return SW_OK;
+}
+
+static sw_error_t
+_adpt_hppe_acl_udf_fields_check(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr,
+				fal_acl_rule_t * rule, a_uint32_t *rule_type_map)
+{
+	SSDK_DEBUG("fields[0] = 0x%x, fields[1] = 0x%x\n",
+				rule->field_flg[0], rule->field_flg[1]);
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF0))
+	{
+		*rule_type_map |= (1<<ADPT_ACL_HPPE_UDF0_RULE);
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF3))
+	{
+		*rule_type_map |= (1<<ADPT_ACL_HPPE_UDF1_RULE);
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF1) &&
+		rule->udf1_op != FAL_ACL_FIELD_MASK)
+	{
+		*rule_type_map |= (1<<ADPT_ACL_HPPE_UDF1_RULE);
+	}
+
+	if(*rule_type_map == 0)
+	{
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF1) ||
+			FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF2))
+		{
+			*rule_type_map |= (1<<ADPT_ACL_HPPE_UDF0_RULE);
+		}
+	}
+
+	SSDK_DEBUG("rule_type_map = 0x%x\n", *rule_type_map);
+
+	return SW_OK;
+}
+
+static sw_error_t _adpt_hppe_acl_mac_rule_sw_2_hw(fal_acl_rule_t *rule, a_uint32_t is_mac_da,
+		union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask)
+{
+	ADPT_HPPE_ACL_MAC_RULE * macrule = (ADPT_HPPE_ACL_MAC_RULE *)hw_reg;
+	ADPT_HPPE_ACL_MAC_RULE_MASK *macrule_mask = (ADPT_HPPE_ACL_MAC_RULE_MASK *)hw_mask;
+
+	if(is_mac_da)
+	{
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_DA))
+		{
+			macrule->mac[5] = rule->dest_mac_val.uc[0];
+			macrule->mac[4] = rule->dest_mac_val.uc[1];
+			macrule->mac[3] = rule->dest_mac_val.uc[2];
+			macrule->mac[2] = rule->dest_mac_val.uc[3];
+			macrule->mac[1] = rule->dest_mac_val.uc[4];
+			macrule->mac[0] = rule->dest_mac_val.uc[5];
+			macrule_mask->mac_mask[5] = rule->dest_mac_mask.uc[0];
+			macrule_mask->mac_mask[4] = rule->dest_mac_mask.uc[1];
+			macrule_mask->mac_mask[3] = rule->dest_mac_mask.uc[2];
+			macrule_mask->mac_mask[2] = rule->dest_mac_mask.uc[3];
+			macrule_mask->mac_mask[1] = rule->dest_mac_mask.uc[4];
+			macrule_mask->mac_mask[0] = rule->dest_mac_mask.uc[5];
+		}
+	}
+	else
+	{
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_SA))
+		{
+			macrule->mac[5] = rule->src_mac_val.uc[0];
+			macrule->mac[4] = rule->src_mac_val.uc[1];
+			macrule->mac[3] = rule->src_mac_val.uc[2];
+			macrule->mac[2] = rule->src_mac_val.uc[3];
+			macrule->mac[1] = rule->src_mac_val.uc[4];
+			macrule->mac[0] = rule->src_mac_val.uc[5];
+			macrule_mask->mac_mask[5] = rule->src_mac_mask.uc[0];
+			macrule_mask->mac_mask[4] = rule->src_mac_mask.uc[1];
+			macrule_mask->mac_mask[3] = rule->src_mac_mask.uc[2];
+			macrule_mask->mac_mask[2] = rule->src_mac_mask.uc[3];
+			macrule_mask->mac_mask[1] = rule->src_mac_mask.uc[4];
+			macrule_mask->mac_mask[0] = rule->src_mac_mask.uc[5];
+		}
+	}
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP))
+	{
+		macrule->is_ip = rule->is_ip_val;
+		macrule_mask->is_ip_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IPV6))
+	{
+		macrule->is_ipv6 = rule->is_ipv6_val;
+		macrule_mask->is_ipv6_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ETHERNET))
+	{
+		macrule->is_ethernet = rule->is_ethernet_val;
+		macrule_mask->is_ethernet_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_SNAP))
+	{
+		macrule->is_snap = rule->is_snap_val;
+		macrule_mask->is_snap_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER))
+	{
+		macrule->is_fake_mac_header = rule->is_fake_mac_header_val;
+		macrule_mask->is_fake_mac_header_mask = 1;
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t _adpt_hppe_acl_vlan_rule_sw_2_hw(fal_acl_rule_t *rule,
+		union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask)
+{
+	ADPT_HPPE_ACL_VLAN_RULE * vlanrule = (ADPT_HPPE_ACL_VLAN_RULE *)hw_reg;
+	ADPT_HPPE_ACL_VLAN_RULE_MASK *vlanrule_mask = (ADPT_HPPE_ACL_VLAN_RULE_MASK *)hw_mask;
+
+	/*ctag*/
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID))
+	{
+		if(FAL_ACL_FIELD_MASK == rule->ctag_vid_op)
+		{
+			vlanrule->cvid = rule->ctag_vid_val;
+			vlanrule_mask->cvid_mask = rule->ctag_vid_mask;
+		}
+		else
+		{
+			a_uint16_t min, max;
+			if(FAL_ACL_FIELD_LE == rule->ctag_vid_op)
+			{
+				min = 0;
+				max = rule->ctag_vid_val;
+			}
+			else if(FAL_ACL_FIELD_GE == rule->ctag_vid_op)
+			{
+				min = rule->ctag_vid_val;
+				max = 0xfff;
+			}
+			else if(FAL_ACL_FIELD_RANGE == rule->ctag_vid_op)
+			{
+				min = rule->ctag_vid_val;
+				max = rule->ctag_vid_mask;
+			}
+			else
+				return SW_NOT_SUPPORTED;
+			vlanrule->cvid = min;
+			vlanrule_mask->cvid_mask = max;
+			hw_reg->bf.range_en = 1;
+		}
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI))
+	{
+		vlanrule->cpcp = rule->ctag_pri_val;
+		vlanrule_mask->cpcp_mask = rule->ctag_pri_mask;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI))
+	{
+		vlanrule->cdei = rule->ctag_cfi_val;
+		vlanrule_mask->cdei_mask = rule->ctag_cfi_mask;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAGGED))
+	{
+		vlanrule->ctag_fmt = rule->ctagged_val;
+		vlanrule_mask->ctag_fmt_mask = rule->ctagged_mask;
+	}
+	/*stag*/
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_VID) &&
+		(rule->stag_vid_op == FAL_ACL_FIELD_MASK))
+	{
+		vlanrule->svid = rule->stag_vid_val;
+		vlanrule_mask->svid_mask = rule->stag_vid_mask;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI))
+	{
+		vlanrule->spcp = rule->stag_pri_val;
+		vlanrule_mask->spcp_mask = rule->stag_pri_mask;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI))
+	{
+		vlanrule->sdei = rule->stag_dei_val;
+		vlanrule_mask->sdei_mask = rule->stag_dei_mask;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAGGED))
+	{
+		vlanrule->stag_fmt = rule->stagged_val;
+		vlanrule_mask->stag_fmt_mask = rule->stagged_mask;
+	}
+	/*vsi*/
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_VSI_VALID))
+	{
+		vlanrule->vsi_valid= rule->vsi_valid;
+		vlanrule_mask->vsi_valid_mask = rule->vsi_valid_mask;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_VSI))
+	{
+		vlanrule->vsi= rule->vsi;
+		vlanrule_mask->vsi_mask = rule->vsi_mask;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP))
+	{
+		vlanrule->is_ip = rule->is_ip_val;
+		vlanrule_mask->is_ip_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IPV6))
+	{
+		vlanrule->is_ipv6 = rule->is_ipv6_val;
+		vlanrule_mask->is_ipv6_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ETHERNET))
+	{
+		vlanrule->is_ethernet = rule->is_ethernet_val;
+		vlanrule_mask->is_ethernet_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_SNAP))
+	{
+		vlanrule->is_snap = rule->is_snap_val;
+		vlanrule_mask->is_snap_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER))
+	{
+		vlanrule->is_fake_mac_header = rule->is_fake_mac_header_val;
+		vlanrule_mask->is_fake_mac_header_mask = 1;
+	}
+
+	return SW_OK;
+}
+
+
+static sw_error_t _adpt_hppe_acl_l2_misc_rule_sw_2_hw(fal_acl_rule_t *rule,
+		union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask)
+{
+	ADPT_HPPE_ACL_L2MISC_RULE * l2misc_rule = (ADPT_HPPE_ACL_L2MISC_RULE *)hw_reg;
+	ADPT_HPPE_ACL_L2MISC_RULE_MASK *l2misc_mask = (ADPT_HPPE_ACL_L2MISC_RULE_MASK *)hw_mask;
+
+	/*stag*/
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_VID))
+	{
+		if(FAL_ACL_FIELD_MASK == rule->stag_vid_op)
+		{
+			l2misc_rule->svid = rule->stag_vid_val;
+			l2misc_mask->svid_mask = rule->stag_vid_mask;
+		}
+		else
+		{
+			a_uint16_t min, max;
+			if(FAL_ACL_FIELD_LE == rule->stag_vid_op)
+			{
+				min = 0;
+				max = rule->stag_vid_val;
+			}
+			else if(FAL_ACL_FIELD_GE == rule->stag_vid_op)
+			{
+				min = rule->stag_vid_val;
+				max = 0xfff;
+			}
+			else if(FAL_ACL_FIELD_RANGE == rule->stag_vid_op)
+			{
+				min = rule->stag_vid_val;
+				max = rule->stag_vid_mask;
+			}
+			else
+			{
+				return SW_NOT_SUPPORTED;
+			}
+			l2misc_rule->svid = min;
+			l2misc_mask->svid_mask = max;
+			hw_reg->bf.range_en = 1;
+		}
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+	{
+		l2misc_rule->l2prot = rule->ethtype_val;
+		l2misc_mask->l2prot_mask = rule->ethtype_mask;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_PPPOE_SESSIONID))
+	{
+		l2misc_rule->pppoe_sessionid = rule->pppoe_sessionid;
+		l2misc_mask->pppoe_sessionid_mask = rule->pppoe_sessionid_mask;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP))
+	{
+		l2misc_rule->is_ip = rule->is_ip_val;
+		l2misc_mask->is_ip_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IPV6))
+	{
+		l2misc_rule->is_ipv6 = rule->is_ipv6_val;
+		l2misc_mask->is_ipv6_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ETHERNET))
+	{
+		l2misc_rule->is_ethernet = rule->is_ethernet_val;
+		l2misc_mask->is_ethernet_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_SNAP))
+	{
+		l2misc_rule->is_snap = rule->is_snap_val;
+		l2misc_mask->is_snap_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER))
+	{
+		l2misc_rule->is_fake_mac_header = rule->is_fake_mac_header_val;
+		l2misc_mask->is_fake_mac_header_mask = 1;
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t _adpt_hppe_acl_ipv4_rule_sw_2_hw(fal_acl_rule_t *rule, a_uint32_t is_ip_da,
+		union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask)
+{
+	ADPT_HPPE_ACL_IPV4_RULE * ipv4rule = (ADPT_HPPE_ACL_IPV4_RULE *)hw_reg;
+	ADPT_HPPE_ACL_IPV4_RULE_MASK *ipv4rule_mask = (ADPT_HPPE_ACL_IPV4_RULE_MASK *)hw_mask;
+
+	if(is_ip_da)
+	{
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP4_DIP))
+		{
+			ipv4rule->ip_0 = rule->dest_ip4_val&0xffff;
+			ipv4rule->ip_1 = (rule->dest_ip4_val>>16)&0xffff;
+			ipv4rule_mask->ip_mask_0 = rule->dest_ip4_mask&0xffff;
+			ipv4rule_mask->ip_mask_1 = (rule->dest_ip4_mask)>>16&0xffff;
+		}
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_DPORT))
+		{
+			if(FAL_ACL_FIELD_MASK == rule->dest_l4port_op)
+			{
+				ipv4rule->l4_port = rule->dest_l4port_val;
+				ipv4rule_mask->l4_port_mask = rule->dest_l4port_mask;
+			}
+			else
+			{
+				a_uint16_t min, max;
+				if(FAL_ACL_FIELD_LE == rule->dest_l4port_op)
+				{
+					min = 0;
+					max = rule->dest_l4port_val;
+				}
+				else if(FAL_ACL_FIELD_GE == rule->dest_l4port_op)
+				{
+					min = rule->dest_l4port_val;
+					max = 0xffff;
+				}
+				else if(FAL_ACL_FIELD_RANGE == rule->dest_l4port_op)
+				{
+					min = rule->dest_l4port_val;
+					max = rule->dest_l4port_mask;
+				}
+				else
+					return SW_NOT_SUPPORTED;
+				ipv4rule->l4_port = min;
+				ipv4rule_mask->l4_port_mask = max;
+				hw_reg->bf.range_en = 1;
+			}
+		}
+	}
+	else
+	{
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP4_SIP))
+		{
+			ipv4rule->ip_0 = rule->src_ip4_val&0xffff;
+			ipv4rule->ip_1 = (rule->src_ip4_val>>16)&0xffff;
+			ipv4rule_mask->ip_mask_0 = rule->src_ip4_mask&0xffff;
+			ipv4rule_mask->ip_mask_1 = (rule->src_ip4_mask>>16)&0xffff;
+		}
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_SPORT))
+		{
+			if(FAL_ACL_FIELD_MASK == rule->src_l4port_op)
+			{
+				ipv4rule->l4_port = rule->src_l4port_val;
+				ipv4rule_mask->l4_port_mask = rule->src_l4port_mask;
+			}
+			else
+			{
+				a_uint16_t min, max;
+				if(FAL_ACL_FIELD_LE == rule->src_l4port_op)
+				{
+					min = 0;
+					max = rule->src_l4port_val;
+				}
+				else if(FAL_ACL_FIELD_GE == rule->src_l4port_op)
+				{
+					min = rule->src_l4port_val;
+					max = 0xffff;
+				}
+				else if(FAL_ACL_FIELD_RANGE == rule->src_l4port_op)
+				{
+					min = rule->src_l4port_val;
+					max = rule->src_l4port_mask;
+				}
+				else
+					return SW_NOT_SUPPORTED;
+				ipv4rule->l4_port = min;
+				ipv4rule_mask->l4_port_mask = max;
+				hw_reg->bf.range_en = 1;
+			}
+		}
+	}
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_CODE) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+	{
+		if(FAL_ACL_FIELD_MASK == rule->icmp_type_code_op)
+		{
+			ipv4rule->l4_port = (rule->icmp_type_val<<8)|rule->icmp_code_val;
+			ipv4rule_mask->l4_port_mask = (rule->icmp_type_mask<<8)|rule->icmp_code_mask;
+		}
+		else
+		{
+			a_uint16_t min, max;
+			if(FAL_ACL_FIELD_LE == rule->icmp_type_code_op)
+			{
+				min = 0;
+				max = (rule->icmp_type_val<<8)|rule->icmp_code_val;
+			}
+			else if(FAL_ACL_FIELD_GE == rule->icmp_type_code_op)
+			{
+				min = (rule->icmp_type_val<<8)|rule->icmp_code_val;
+				max = 0xffff;
+			}
+			else if(FAL_ACL_FIELD_RANGE == rule->icmp_type_code_op)
+			{
+				min = (rule->icmp_type_val<<8)|rule->icmp_code_val;
+				max = (rule->icmp_type_mask<<8)|rule->icmp_code_mask;
+			}
+			else
+				return SW_NOT_SUPPORTED;
+			ipv4rule->l4_port = min;
+			ipv4rule_mask->l4_port_mask = max;
+			hw_reg->bf.range_en = 1;
+		}
+	}
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP))
+	{
+		ipv4rule->is_ip = rule->is_ip_val;
+		ipv4rule_mask->is_ip_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT))
+	{
+		ipv4rule->l3_fragment = rule->is_fragement_val;
+		ipv4rule_mask->l3_fragment_mask = rule->is_fragement_mask;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_PKT_TYPE))
+	{
+		ipv4rule->l3_packet_type = rule->l3_pkt_type;
+		ipv4rule_mask->l3_packet_type_mask = rule->l3_pkt_type_mask;
+	}
+
+	return SW_OK;
+}
+
+/*ip_bit_range: 0 mean DIP0 or SIP0, 1 mean DIP1 or SIP1, 2 mean DIP2 or SIP2,*/
+static sw_error_t _adpt_hppe_acl_ipv6_rule_sw_2_hw(fal_acl_rule_t *rule, a_uint32_t is_ip_da, a_uint32_t ip_bit_range,
+		union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask)
+{
+	ADPT_HPPE_ACL_IPV6_RULE * ipv6rule = (ADPT_HPPE_ACL_IPV6_RULE *)hw_reg;
+	ADPT_HPPE_ACL_IPV6_RULE_MASK *ipv6rule_mask = (ADPT_HPPE_ACL_IPV6_RULE_MASK *)hw_mask;
+
+	if(is_ip_da)
+	{
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP6_DIP))
+		{
+			if(ip_bit_range == 0)
+			{
+				ipv6rule->ip_port = rule->dest_ip6_val.ul[3]&0xffff;
+				ipv6rule->ip_ext_1 = (rule->dest_ip6_val.ul[3]>>16)&0xffff;
+				ipv6rule->ip_ext_2 = (rule->dest_ip6_val.ul[2])&0xffff;
+				ipv6rule_mask->ip_port_mask = rule->dest_ip6_mask.ul[3]&0xffff;
+				ipv6rule_mask->ip_ext_1_mask = (rule->dest_ip6_mask.ul[3]>>16)&0xffff;
+				ipv6rule_mask->ip_ext_2_mask = (rule->dest_ip6_mask.ul[2])&0xffff;
+			}
+			else if(ip_bit_range == 1)
+			{
+				ipv6rule->ip_port = (rule->dest_ip6_val.ul[2]>>16)&0xffff;
+				ipv6rule->ip_ext_1 = (rule->dest_ip6_val.ul[1])&0xffff;
+				ipv6rule->ip_ext_2 = (rule->dest_ip6_val.ul[1]>>16)&0xffff;
+				ipv6rule_mask->ip_port_mask = (rule->dest_ip6_mask.ul[2]>>16)&0xffff;
+				ipv6rule_mask->ip_ext_1_mask = (rule->dest_ip6_mask.ul[1])&0xffff;
+				ipv6rule_mask->ip_ext_2_mask = (rule->dest_ip6_mask.ul[1]>>16)&0xffff;
+			}
+			else if(ip_bit_range == 2)
+			{
+				ipv6rule->ip_ext_1 = (rule->dest_ip6_val.ul[0])&0xffff;
+				ipv6rule->ip_ext_2 = (rule->dest_ip6_val.ul[0]>>16)&0xffff;
+				ipv6rule_mask->ip_ext_1_mask = (rule->dest_ip6_mask.ul[0])&0xffff;
+				ipv6rule_mask->ip_ext_2_mask = (rule->dest_ip6_mask.ul[0]>>16)&0xffff;
+			}
+		}
+		if((ip_bit_range == 2) && (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_DPORT)))
+		{
+			if(FAL_ACL_FIELD_MASK == rule->dest_l4port_op)
+			{
+				ipv6rule->ip_port = rule->dest_l4port_val;
+				ipv6rule_mask->ip_port_mask = rule->dest_l4port_mask;
+			}
+			else
+			{
+				a_uint16_t min, max;
+				if(FAL_ACL_FIELD_LE == rule->dest_l4port_op)
+				{
+					min = 0;
+					max = rule->dest_l4port_val;
+				}
+				else if(FAL_ACL_FIELD_GE == rule->dest_l4port_op)
+				{
+					min = rule->dest_l4port_val;
+					max = 0xffff;
+				}
+				else if(FAL_ACL_FIELD_RANGE == rule->dest_l4port_op)
+				{
+					min = rule->dest_l4port_val;
+					max = rule->dest_l4port_mask;
+				}
+				else
+					return SW_NOT_SUPPORTED;
+				ipv6rule->ip_port = min;
+				ipv6rule_mask->ip_port_mask = max;
+				hw_reg->bf.range_en = 1;
+			}
+		}
+	}
+	else
+	{
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP6_SIP))
+		{
+			if(ip_bit_range == 0)
+			{
+				ipv6rule->ip_port = rule->src_ip6_val.ul[3]&0xffff;
+				ipv6rule->ip_ext_1 = (rule->src_ip6_val.ul[3]>>16)&0xffff;
+				ipv6rule->ip_ext_2 = (rule->src_ip6_val.ul[2])&0xffff;
+				ipv6rule_mask->ip_port_mask = rule->src_ip6_mask.ul[3]&0xffff;
+				ipv6rule_mask->ip_ext_1_mask = (rule->src_ip6_mask.ul[3]>>16)&0xffff;
+				ipv6rule_mask->ip_ext_2_mask = (rule->src_ip6_mask.ul[2])&0xffff;
+			}
+			else if(ip_bit_range == 1)
+			{
+				ipv6rule->ip_port = (rule->src_ip6_val.ul[2]>>16)&0xffff;
+				ipv6rule->ip_ext_1 = (rule->src_ip6_val.ul[1])&0xffff;
+				ipv6rule->ip_ext_2 = (rule->src_ip6_val.ul[1]>>16)&0xffff;
+				ipv6rule_mask->ip_port_mask = (rule->src_ip6_mask.ul[2]>>16)&0xffff;
+				ipv6rule_mask->ip_ext_1_mask = (rule->src_ip6_mask.ul[1])&0xffff;
+				ipv6rule_mask->ip_ext_2_mask = (rule->src_ip6_mask.ul[1]>>16)&0xffff;
+			}
+			else if(ip_bit_range == 2)
+			{
+				ipv6rule->ip_ext_1 = (rule->src_ip6_val.ul[0])&0xffff;
+				ipv6rule->ip_ext_2 = (rule->src_ip6_val.ul[0]>>16)&0xffff;
+				ipv6rule_mask->ip_ext_1_mask = (rule->src_ip6_mask.ul[0])&0xffff;
+				ipv6rule_mask->ip_ext_2_mask = (rule->src_ip6_mask.ul[0]>>16)&0xffff;
+			}
+		}
+		if((ip_bit_range == 2) && (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_SPORT)))
+		{
+			if(FAL_ACL_FIELD_MASK == rule->src_l4port_op)
+			{
+				ipv6rule->ip_port = rule->src_l4port_val;
+				ipv6rule_mask->ip_port_mask = rule->src_l4port_mask;
+			}
+			else
+			{
+				a_uint16_t min, max;
+				if(FAL_ACL_FIELD_LE == rule->src_l4port_op)
+				{
+					min = 0;
+					max = rule->src_l4port_val;
+				}
+				else if(FAL_ACL_FIELD_GE == rule->src_l4port_op)
+				{
+					min = rule->src_l4port_val;
+					max = 0xffff;
+				}
+				else if(FAL_ACL_FIELD_RANGE == rule->src_l4port_op)
+				{
+					min = rule->src_l4port_val;
+					max = rule->src_l4port_mask;
+				}
+				else
+					return SW_NOT_SUPPORTED;
+				ipv6rule->ip_port = min;
+				ipv6rule_mask->ip_port_mask = max;
+				hw_reg->bf.range_en = 1;
+			}
+		}
+	}
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_CODE) ||
+		FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+	{
+		if(FAL_ACL_FIELD_MASK == rule->icmp_type_code_op)
+		{
+			ipv6rule->ip_port = (rule->icmp_type_val<<8)|rule->icmp_code_val;
+			ipv6rule_mask->ip_port_mask = (rule->icmp_type_mask<<8)|rule->icmp_code_mask;
+		}
+		else
+		{
+			a_uint16_t min, max;
+			if(FAL_ACL_FIELD_LE == rule->icmp_type_code_op)
+			{
+				min = 0;
+				max = (rule->icmp_type_val<<8)|rule->icmp_code_val;
+			}
+			else if(FAL_ACL_FIELD_GE == rule->icmp_type_code_op)
+			{
+				min = (rule->icmp_type_val<<8)|rule->icmp_code_val;
+				max = 0xffff;
+			}
+			else if(FAL_ACL_FIELD_RANGE == rule->icmp_type_code_op)
+			{
+				min = (rule->icmp_type_val<<8)|rule->icmp_code_val;
+				max = (rule->icmp_type_mask<<8)|rule->icmp_code_mask;
+			}
+			else
+				return SW_NOT_SUPPORTED;
+			ipv6rule->ip_port = min;
+			ipv6rule_mask->ip_port_mask = max;
+			hw_reg->bf.range_en = 1;
+		}
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT))
+	{
+		ipv6rule->l3_fragment = rule->is_fragement_val;
+		ipv6rule_mask->l3_fragment_mask = rule->is_fragement_mask;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_PKT_TYPE))
+	{
+		ipv6rule->l3_packet_type = rule->l3_pkt_type;
+		ipv6rule_mask->l3_packet_type_mask = rule->l3_pkt_type_mask;
+	}
+	return SW_OK;
+}
+
+static sw_error_t _adpt_hppe_acl_ipmisc_rule_sw_2_hw(fal_acl_rule_t *rule,
+		union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask)
+{
+	ADPT_HPPE_ACL_IPMISC_RULE * ipmisc_rule = (ADPT_HPPE_ACL_IPMISC_RULE *)hw_reg;
+	ADPT_HPPE_ACL_IPMISC_RULE_MASK *ipmisc_mask = (ADPT_HPPE_ACL_IPMISC_RULE_MASK *)hw_mask;
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_LENGTH))
+	{
+		if(FAL_ACL_FIELD_MASK == rule->l3_length_op)
+		{
+			ipmisc_rule->l3_length = rule->l3_length;
+			ipmisc_mask->l3_length_mask = rule->l3_length_mask;
+		}
+		else
+		{
+			a_uint16_t min, max;
+			if(FAL_ACL_FIELD_LE == rule->l3_length_op)
+			{
+				min = 0;
+				max = rule->l3_length;
+			}
+			else if(FAL_ACL_FIELD_GE == rule->l3_length_op)
+			{
+				min = rule->l3_length;
+				max = 0xffff;
+			}
+			else if(FAL_ACL_FIELD_RANGE == rule->l3_length_op)
+			{
+				min = rule->l3_length;
+				max = rule->l3_length_mask;
+			}
+			else
+				return SW_NOT_SUPPORTED;
+			ipmisc_rule->l3_length = min;
+			ipmisc_mask->l3_length_mask = max;
+			hw_reg->bf.range_en = 1;
+		}
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_PROTO))
+	{
+		ipmisc_rule->l3_prot = rule->ip_proto_val;
+		ipmisc_mask->l3_prot_mask = rule->ip_proto_mask;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_DSCP))
+	{
+		ipmisc_rule->l3_dscp_tc = rule->ip_dscp_val;
+		ipmisc_mask->l3_dscp_tc_mask = rule->ip_dscp_mask;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FIRST_FRAGMENT))
+	{
+		ipmisc_rule->first_fragment = rule->is_first_frag_val;
+		ipmisc_mask->first_fragment_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_TCP_FLAG))
+	{
+		ipmisc_rule->tcp_flags = rule->tcp_flag_val;
+		ipmisc_mask->tcp_flags_mask = rule->tcp_flag_mask;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IPV4_OPTION))
+	{
+		ipmisc_rule->ipv4_option_state = rule->is_ipv4_option_val;
+		ipmisc_mask->ipv4_option_state_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_TTL))
+	{
+		ipmisc_rule->l3_ttl = rule->l3_ttl;
+		ipmisc_mask->l3_ttl_mask = rule->l3_ttl_mask;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_AH_HEADER))
+	{
+		ipmisc_rule->ah_header = rule->is_ah_header_val;
+		ipmisc_mask->ah_header_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ESP_HEADER))
+	{
+		ipmisc_rule->esp_header = rule->is_esp_header_val;
+		ipmisc_mask->esp_header_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MOBILITY_HEADER))
+	{
+		ipmisc_rule->mobility_header = rule->is_mobility_header_val;
+		ipmisc_mask->mobility_header_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FRAGMENT_HEADER))
+	{
+		ipmisc_rule->fragment_header = rule->is_fragment_header_val;
+		ipmisc_mask->fragment_header_mask= 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_OTHER_EXT_HEADER))
+	{
+		ipmisc_rule->other_header = rule->is_other_header_val;
+		ipmisc_mask->other_header_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IPV6))
+	{
+		ipmisc_rule->is_ipv6 = rule->is_ipv6_val;
+		ipmisc_mask->is_ipv6_mask = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT))
+	{
+		ipmisc_rule->l3_fragment = rule->is_fragement_val;
+		ipmisc_mask->l3_fragment_mask = 1;
+	}
+	return SW_OK;
+}
+
+static sw_error_t _adpt_hppe_acl_udf_rule_sw_2_hw(fal_acl_rule_t *rule, a_uint32_t is_win1,
+		union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask)
+{
+	ADPT_HPPE_ACL_UDF_RULE * udfrule = (ADPT_HPPE_ACL_UDF_RULE *)hw_reg;
+	ADPT_HPPE_ACL_UDF_RULE_MASK *udfrule_mask = (ADPT_HPPE_ACL_UDF_RULE_MASK *)hw_mask;
+
+	if(is_win1)
+	{
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF3))
+		{
+			udfrule->udf2_valid = 1;
+			udfrule->udf2 = rule->udf3_val;
+			udfrule_mask->udf2_valid = 1;
+			udfrule_mask->udf2_mask = rule->udf3_mask;
+		}
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF2))
+		{
+			udfrule->udf1_valid = 1;
+			udfrule->udf1 = rule->udf2_val;
+			udfrule_mask->udf1_valid = 1;
+			udfrule_mask->udf1_mask = rule->udf2_mask;
+		}
+
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF1))
+		{
+			udfrule->udf0_valid = 1;
+			udfrule_mask->udf0_valid = 1;
+			if(FAL_ACL_FIELD_MASK == rule->udf1_op)
+			{
+				udfrule->udf0 = rule->udf1_val;
+				udfrule_mask->udf0_mask = rule->udf1_mask;
+			}
+			else
+			{
+				a_uint16_t min, max;
+				if(FAL_ACL_FIELD_LE == rule->udf1_op)
+				{
+					min = 0;
+					max = rule->udf1_val;
+				}
+				else if(FAL_ACL_FIELD_GE == rule->udf1_op)
+				{
+					min = rule->udf1_val;
+					max = 0xffff;
+				}
+				else if(FAL_ACL_FIELD_RANGE == rule->udf1_op)
+				{
+					min = rule->udf1_val;
+					max = rule->udf1_mask;
+				}
+				else
+					return SW_NOT_SUPPORTED;
+				udfrule->udf0 = min;
+				udfrule_mask->udf0_mask = max;
+				hw_reg->bf.range_en = 1;
+			}
+		}
+	}
+	else
+	{
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF1) &&
+			FAL_ACL_FIELD_MASK == rule->udf1_op)
+		{
+			udfrule->udf1_valid = 1;
+			udfrule->udf1 = rule->udf1_val;
+			udfrule_mask->udf1_valid = 1;
+			udfrule_mask->udf1_mask = rule->udf1_mask;
+		}
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF2))
+		{
+			udfrule->udf2_valid = 1;
+			udfrule->udf2 = rule->udf2_val;
+			udfrule_mask->udf2_valid = 1;
+			udfrule_mask->udf2_mask = rule->udf2_mask;
+		}
+
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF0))
+		{
+			udfrule->udf0_valid = 1;
+			udfrule_mask->udf0_valid = 1;
+			if(FAL_ACL_FIELD_MASK == rule->udf0_op)
+			{
+				udfrule->udf0 = rule->udf0_val;
+				udfrule_mask->udf0_mask = rule->udf0_mask;
+			}
+			else
+			{
+				a_uint16_t min, max;
+				if(FAL_ACL_FIELD_LE == rule->udf0_op)
+				{
+					min = 0;
+					max = rule->udf0_val;
+				}
+				else if(FAL_ACL_FIELD_GE == rule->udf0_op)
+				{
+					min = rule->udf0_val;
+					max = 0xffff;
+				}
+				else if(FAL_ACL_FIELD_RANGE == rule->udf0_op)
+				{
+					min = rule->udf0_val;
+					max = rule->udf0_mask;
+				}
+				else
+					return SW_NOT_SUPPORTED;
+				udfrule->udf0 = min;
+				udfrule_mask->udf0_mask = max;
+				hw_reg->bf.range_en = 1;
+			}
+		}
+	}
+
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP))
+	{
+		udfrule->is_ip = rule->is_ip_val;
+		udfrule_mask->is_ip = 1;
+	}
+	if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IPV6))
+	{
+		udfrule->is_ipv6= rule->is_ipv6_val;
+		udfrule_mask->is_ipv6 = 1;
+	}
+	return SW_OK;
+}
+static sw_error_t
+_adpt_hppe_acl_action_sw_2_hw(a_uint32_t dev_id,fal_acl_rule_t *rule, union ipo_action_u *hw_act)
+{
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REDPT))
+	{
+		a_uint32_t dest_type = FAL_ACL_DEST_TYPE(rule->ports);
+		a_uint32_t dest_val = FAL_ACL_DEST_VALUE(rule->ports);
+
+		SSDK_DEBUG("rule->ports = %x\n", rule->ports);
+
+		hw_act->bf.dest_info_change_en = 1;
+		if(dest_type == FAL_ACL_DEST_NEXTHOP) /*nexthop*/
+		{
+			hw_act->bf.dest_info =
+				HPPE_ACL_DEST_INFO(HPPE_ACL_DEST_NEXTHOP, dest_val);
+		}
+		else if(FAL_ACL_DEST_TYPE(rule->ports) == FAL_ACL_DEST_PORT_ID)/*vp*/
+		{
+			hw_act->bf.dest_info =
+				HPPE_ACL_DEST_INFO(HPPE_ACL_DEST_PORT_ID, dest_val);
+		}
+		else if(FAL_ACL_DEST_TYPE(rule->ports) == FAL_ACL_DEST_PORT_BMP)/*bitmap*/
+		{
+			hw_act->bf.dest_info =
+				HPPE_ACL_DEST_INFO(HPPE_ACL_DEST_PORT_BMP, dest_val);
+		}
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_PERMIT))
+	{
+		hw_act->bf.dest_info_change_en = 1;
+		hw_act->bf.fwd_cmd = 0;/*forward*/
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_DENY))
+	{
+		hw_act->bf.dest_info_change_en = 1;
+		hw_act->bf.fwd_cmd = 1;/*drop*/
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_CPYCPU))
+	{
+		hw_act->bf.dest_info_change_en = 1;
+		hw_act->bf.fwd_cmd = 2;/*copy to cpu*/
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_RDTCPU))
+	{
+		hw_act->bf.dest_info_change_en = 1;
+		hw_act->bf.fwd_cmd = 3;/*redirect to cpu*/
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_MIRROR))
+	{
+		hw_act->bf.mirror_en= 1;
+	}
+	hw_act->bf.bypass_bitmap_0 = rule->bypass_bitmap & 0x3fff;
+	hw_act->bf.bypass_bitmap_1 = (rule->bypass_bitmap>>14) & 0x3ffff;
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID))
+	{
+		hw_act->bf.svid_change_en = 1;
+		hw_act->bf.stag_fmt = rule->stag_fmt;
+		hw_act->bf.svid = rule->stag_vid;
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI))
+	{
+		hw_act->bf.stag_pcp_change_en = 1;
+		hw_act->bf.stag_pcp = rule->stag_pri;
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI))
+	{
+		hw_act->bf.stag_dei_change_en = 1;
+		hw_act->bf.stag_dei = rule->stag_dei;
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID))
+	{
+		hw_act->bf.cvid_change_en = 1;
+		hw_act->bf.ctag_fmt = rule->ctag_fmt;
+		hw_act->bf.cvid = rule->ctag_vid;
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI))
+	{
+		hw_act->bf.ctag_pcp_change_en = 1;
+		hw_act->bf.ctag_pcp_0 = rule->ctag_pri&0x3;
+		hw_act->bf.ctag_pcp_1 = (rule->ctag_pri>>2)&0x1;
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI))
+	{
+		hw_act->bf.ctag_dei_change_en = 1;
+		hw_act->bf.ctag_dei = rule->ctag_cfi;
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_DSCP))
+	{
+		hw_act->bf.dscp_tc_change_en = 1;
+		hw_act->bf.dscp_tc = rule->dscp;
+#if defined(CPPE)
+		if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
+		{
+			hw_act->bf.dscp_tc_mask = rule->dscp_mask;
+		}
+#endif
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_INT_DP))
+	{
+		hw_act->bf.int_dp_change_en = 1;
+		hw_act->bf.int_dp = rule->int_dp;
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_POLICER_EN))
+	{
+		hw_act->bf.policer_en = 1;
+		hw_act->bf.policer_index = rule->policer_ptr;
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_QUEUE))
+	{
+		hw_act->bf.qid_en = 1;
+		hw_act->bf.qid = rule->queue;
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_ENQUEUE_PRI))
+	{
+		hw_act->bf.enqueue_pri_change_en = 1;
+		hw_act->bf.enqueue_pri = rule->enqueue_pri;
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_SERVICE_CODE))
+	{
+		hw_act->bf.service_code_en = 1;
+		hw_act->bf.service_code_0 = rule->service_code&0x1;
+		hw_act->bf.service_code_1 = (rule->service_code>>1)&0x7f;
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_SYN_TOGGLE))
+	{
+		hw_act->bf.syn_toggle = 1;
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_CPU_CODE))
+	{
+		hw_act->bf.cpu_code_en = 1;
+		hw_act->bf.cpu_code = rule->cpu_code;
+	}
+	if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_METADATA_EN))
+	{
+		hw_act->bf.metadata_en = 1;
+	}
+#if defined(CPPE)
+	if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
+	{
+		hw_act->bf.qos_res_prec = rule->qos_res_prec;
+	}
+#endif
+	return SW_OK;
+}
+
+sw_error_t
+_adpt_hppe_acl_rule_hw_add(a_uint32_t dev_id, ADPT_HPPE_ACL_SW_LIST *list_entry,
+		a_uint32_t hw_list_id, a_uint32_t rule_id, a_uint32_t rule_nr,
+		fal_acl_rule_t * rule, a_uint32_t rule_type_map, a_uint32_t allocated_entries)
+{
+	union ipo_rule_reg_u hw_reg = {0};
+	union ipo_mask_reg_u hw_mask = {0};
+	union ipo_action_u hw_act = {0};
+	sw_error_t rv = 0;
+	a_uint32_t hw_entry = 0;
+	a_uint32_t i = 0;
+
+	hw_reg.bf.post_routing_en = rule->post_routing;
+	hw_reg.bf.res_chain = rule->acl_pool;
+	hw_reg.bf.pri = ((list_entry->list_pri)<<3)|rule->pri;
+
+	for( i = 0; i < ADPT_ACL_HPPE_RULE_TYPE_NUM; i++)
+	{
+		if(!((1<<i)&rule_type_map))
+		{
+			continue;
+		}
+		hw_reg.bf.rule_field_0 = 0;
+		hw_reg.bf.rule_field_1 = 0;
+
+		memset(&hw_mask, 0, sizeof(hw_mask));
+		memset(&hw_act, 0, sizeof(hw_act));
+
+		if(i == ADPT_ACL_HPPE_VLAN_RULE)
+		{
+			hw_reg.bf.rule_type = 2;
+			_adpt_hppe_acl_vlan_rule_sw_2_hw(rule, &hw_reg, &hw_mask);
+		}
+		else if(i == ADPT_ACL_HPPE_MAC_DA_RULE)
+		{
+			hw_reg.bf.rule_type = 0;
+			_adpt_hppe_acl_mac_rule_sw_2_hw(rule, 1, &hw_reg, &hw_mask);
+		}
+		else if(i == ADPT_ACL_HPPE_MAC_SA_RULE)
+		{
+			hw_reg.bf.rule_type = 1;
+			_adpt_hppe_acl_mac_rule_sw_2_hw(rule, 0, &hw_reg, &hw_mask);
+		}
+		else if(i == ADPT_ACL_HPPE_L2_MISC_RULE)
+		{
+			hw_reg.bf.rule_type = 3;
+			_adpt_hppe_acl_l2_misc_rule_sw_2_hw(rule, &hw_reg, &hw_mask);
+		}
+		else if(i == ADPT_ACL_HPPE_IPV4_DIP_RULE)
+		{
+			hw_reg.bf.rule_type = 4;
+			_adpt_hppe_acl_ipv4_rule_sw_2_hw(rule, 1, &hw_reg, &hw_mask);
+		}
+		else if(i == ADPT_ACL_HPPE_IPV4_SIP_RULE)
+		{
+			hw_reg.bf.rule_type = 5;
+			_adpt_hppe_acl_ipv4_rule_sw_2_hw(rule, 0, &hw_reg, &hw_mask);
+		}
+		else if(i == ADPT_ACL_HPPE_IPV6_DIP0_RULE)
+		{
+			hw_reg.bf.rule_type = 6;
+			_adpt_hppe_acl_ipv6_rule_sw_2_hw(rule, 1, 0, &hw_reg, &hw_mask);
+		}
+		else if(i == ADPT_ACL_HPPE_IPV6_DIP1_RULE)
+		{
+			hw_reg.bf.rule_type = 7;
+			_adpt_hppe_acl_ipv6_rule_sw_2_hw(rule, 1, 1, &hw_reg, &hw_mask);
+		}
+		else if(i == ADPT_ACL_HPPE_IPV6_DIP2_RULE)
+		{
+			hw_reg.bf.rule_type = 8;
+			_adpt_hppe_acl_ipv6_rule_sw_2_hw(rule, 1, 2, &hw_reg, &hw_mask);
+		}
+		else if(i == ADPT_ACL_HPPE_IPV6_SIP0_RULE)
+		{
+			hw_reg.bf.rule_type = 9;
+			_adpt_hppe_acl_ipv6_rule_sw_2_hw(rule, 0, 0, &hw_reg, &hw_mask);
+		}
+		else if(i == ADPT_ACL_HPPE_IPV6_SIP1_RULE)
+		{
+			hw_reg.bf.rule_type = 10;
+			_adpt_hppe_acl_ipv6_rule_sw_2_hw(rule, 0, 1, &hw_reg, &hw_mask);
+		}
+		else if(i == ADPT_ACL_HPPE_IPV6_SIP2_RULE)
+		{
+			hw_reg.bf.rule_type = 11;
+			_adpt_hppe_acl_ipv6_rule_sw_2_hw(rule, 0, 2, &hw_reg, &hw_mask);
+		}
+		else if(i == ADPT_ACL_HPPE_IPMISC_RULE)
+		{
+			hw_reg.bf.rule_type = 12;
+			_adpt_hppe_acl_ipmisc_rule_sw_2_hw(rule, &hw_reg, &hw_mask);
+		}
+		else if(i == ADPT_ACL_HPPE_UDF0_RULE)
+		{
+			hw_reg.bf.rule_type = 13;
+			_adpt_hppe_acl_udf_rule_sw_2_hw(rule, 0, &hw_reg, &hw_mask);
+		}
+		else if(i == ADPT_ACL_HPPE_UDF1_RULE)
+		{
+			hw_reg.bf.rule_type = 14;
+			_adpt_hppe_acl_udf_rule_sw_2_hw(rule, 1, &hw_reg, &hw_mask);
+		}
+
+		if(!hw_reg.bf.range_en)
+		{
+			hw_entry = _acl_bit_index(allocated_entries, ADPT_ACL_ENTRY_NUM_PER_LIST, 1);
+		}
+		if(hw_entry == 0xff || hw_reg.bf.range_en)
+		{
+			hw_entry = _acl_bit_index(allocated_entries, ADPT_ACL_ENTRY_NUM_PER_LIST, 2);
+		}
+		if(hw_entry == 0xff)
+		{
+			printk("%s, %d, fail find hw_entry in 0x%x\n",
+				__FUNCTION__, __LINE__, allocated_entries);
+			return SW_NO_RESOURCE;
+		}
+		allocated_entries &= (~(1<<hw_entry));
+
+		if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+		{
+		    hw_reg.bf.inverse_en = 1;
+		}
+
+		SSDK_DEBUG("rule and mask set hw_entry = %d\n",
+				hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_entry);
+		SSDK_DEBUG("post_route %d, chain %d, pri %d, src_1 %d, src_0 %d, src_type %d "
+			"rule_type %d, inverse %d, range %d\n", hw_reg.bf.post_routing_en,
+			hw_reg.bf.res_chain, hw_reg.bf.pri, hw_reg.bf.src_1, hw_reg.bf.src_0,
+			hw_reg.bf.src_type, hw_reg.bf.rule_type, hw_reg.bf.inverse_en,
+			hw_reg.bf.range_en);
+		/*_adpt_acl_reg_dump((a_uint8_t *)&hw_reg, sizeof(hw_reg));*/
+		rv |= hppe_ipo_rule_reg_set(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_entry,
+			&hw_reg);
+		/*_adpt_acl_reg_dump((a_uint8_t *)&hw_mask, sizeof(hw_mask));*/
+		rv |= hppe_ipo_mask_reg_set(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_entry,
+			&hw_mask);
+		_adpt_hppe_acl_action_sw_2_hw(dev_id,rule, &hw_act);
+		/*_adpt_acl_reg_dump((a_uint8_t *)&hw_act, sizeof(hw_act));*/
+		rv |= hppe_ipo_action_set(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_entry,
+			&hw_act);
+
+		if(rv != SW_OK)
+		{
+			return rv;
+		}
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+_adpt_hppe_acl_hw_list_resort(a_uint32_t dev_id, a_uint32_t hw_list_index, a_bool_t move_up)
+{
+	a_uint32_t i = 0;
+	ADPT_HPPE_ACL_HW_LIST temp = {0};
+
+	if(hw_list_index >= ADPT_ACL_HW_LIST_NUM)
+	{
+		return SW_OUT_OF_RANGE;
+	}
+
+	if(move_up)
+	{
+		temp.hw_list_id = g_acl_hw_list[dev_id][hw_list_index].hw_list_id;
+		temp.free_hw_entry_bitmap =
+			g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_bitmap;
+		temp.free_hw_entry_count =
+			g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_count;
+		for(i = hw_list_index; i > 0; i--)
+		{
+			if(temp.free_hw_entry_count <
+				g_acl_hw_list[dev_id][i-1].free_hw_entry_count)
+			{
+				g_acl_hw_list[dev_id][i].hw_list_id =
+					g_acl_hw_list[dev_id][i-1].hw_list_id;
+				g_acl_hw_list[dev_id][i].free_hw_entry_bitmap =
+					g_acl_hw_list[dev_id][i-1].free_hw_entry_bitmap;
+				g_acl_hw_list[dev_id][i].free_hw_entry_count =
+					g_acl_hw_list[dev_id][i-1].free_hw_entry_count;
+			}
+			else
+			{
+				break;
+			}
+		}
+		g_acl_hw_list[dev_id][i].hw_list_id = temp.hw_list_id;
+		g_acl_hw_list[dev_id][i].free_hw_entry_bitmap = temp.free_hw_entry_bitmap;
+		g_acl_hw_list[dev_id][i].free_hw_entry_count = temp.free_hw_entry_count;
+	}
+	else
+	{
+		temp.hw_list_id = g_acl_hw_list[dev_id][hw_list_index].hw_list_id;
+		temp.free_hw_entry_bitmap =
+			g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_bitmap;
+		temp.free_hw_entry_count =
+			g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_count;
+		for(i = hw_list_index; i < ADPT_ACL_HW_LIST_NUM-1; i++)
+		{
+			if(temp.free_hw_entry_count >
+				g_acl_hw_list[dev_id][i+1].free_hw_entry_count)
+			{
+				g_acl_hw_list[dev_id][i].hw_list_id =
+					g_acl_hw_list[dev_id][i+1].hw_list_id;
+				g_acl_hw_list[dev_id][i].free_hw_entry_bitmap =
+					g_acl_hw_list[dev_id][i+1].free_hw_entry_bitmap;
+				g_acl_hw_list[dev_id][i].free_hw_entry_count =
+					g_acl_hw_list[dev_id][i+1].free_hw_entry_count;
+			}
+			else
+			{
+				break;
+			}
+		}
+		g_acl_hw_list[dev_id][i].hw_list_id = temp.hw_list_id;
+		g_acl_hw_list[dev_id][i].free_hw_entry_bitmap = temp.free_hw_entry_bitmap;
+		g_acl_hw_list[dev_id][i].free_hw_entry_count = temp.free_hw_entry_count;
+	}
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+		a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule)
+{
+	a_uint32_t rule_type_map = 0;
+	a_uint32_t rule_type_count = 0;
+	a_uint32_t index = 0, hw_list_index = 0, hw_list_id = 0;
+	sw_error_t rv = 0;
+	union rule_ext_1_reg_u ext_1 = {0};
+	union rule_ext_2_reg_u ext_2 = {0};
+	union rule_ext_4_reg_u ext_4 = {0};
+	struct list_head *rule_pos = NULL;
+	ADPT_HPPE_ACL_SW_RULE *rule_exist_entry = NULL, *rule_add_entry = NULL;
+	ADPT_HPPE_ACL_SW_LIST *list_find_entry = NULL;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(rule);
+
+	if(list_id >= ADPT_ACL_SW_LIST_NUM)
+	{
+		return SW_OUT_OF_RANGE;
+	}
+
+	if(rule_id >= ADPT_ACL_RULE_NUM_PER_LIST)
+	{
+		return SW_OUT_OF_RANGE;
+	}
+
+	aos_lock_bh(&hppe_acl_lock[dev_id]);
+	list_find_entry = _adpt_hppe_acl_list_entry_get(dev_id, list_id);
+	if(list_find_entry == NULL)
+	{
+		SSDK_ERROR("List %d not create, no resource to insert rules into it\n", list_id);
+		aos_unlock_bh(&hppe_acl_lock[dev_id]);
+		return SW_NO_RESOURCE;
+	}
+
+	list_for_each(rule_pos, &list_find_entry->list_sw_rule)
+	{
+		rule_exist_entry = list_entry(rule_pos, ADPT_HPPE_ACL_SW_RULE, list);
+		if((rule_exist_entry->rule_id == rule_id) && (rule_exist_entry->rule_hw_entry != 0))
+		{
+			aos_unlock_bh(&hppe_acl_lock[dev_id]);
+			return SW_ALREADY_EXIST;
+		}
+	}
+
+	SSDK_DEBUG("fields[0] = 0x%x, fields[1] = 0x%x\n",
+				rule->field_flg[0], rule->field_flg[1]);
+	if(rule->rule_type == FAL_ACL_RULE_IP4)/*input ipv4 type*/
+	{
+		_adpt_hppe_acl_ipv4_fields_check(dev_id, list_id, rule_id, rule_nr, rule,
+			&rule_type_map);
+	}
+	else if(rule->rule_type == FAL_ACL_RULE_IP6)/*input ipv6 type*/
+	{
+		_adpt_hppe_acl_ipv6_fields_check(dev_id, list_id, rule_id, rule_nr, rule,
+			&rule_type_map);
+	}
+	_adpt_hppe_acl_udf_fields_check(dev_id, list_id, rule_id, rule_nr, rule, &rule_type_map);
+	_adpt_hppe_acl_l2_fields_check(dev_id, list_id, rule_id, rule_nr, rule, &rule_type_map);
+
+	if(rule_type_map == 0)
+	{
+		rule_type_map |= (1<<ADPT_ACL_HPPE_MAC_DA_RULE);
+	}
+
+	SSDK_DEBUG("rule_type_map = 0x%x\n", rule_type_map);
+
+	rule_type_count = _acl_bits_count(rule_type_map, ADPT_ACL_HPPE_RULE_TYPE_NUM, 0);
+	SSDK_DEBUG("rule_type_count = %d\n", rule_type_count);
+
+	if(rule_type_count == 0 || rule_type_count > ADPT_ACL_ENTRY_NUM_PER_LIST)
+	{
+		SSDK_ERROR("rule_type_count = %d\n", rule_type_count);
+		aos_unlock_bh(&hppe_acl_lock[dev_id]);
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = _adpt_hppe_acl_alloc_entries(dev_id, &hw_list_index, rule_id, rule_nr, rule,
+		rule_type_map, rule_type_count, &index);
+	if(rv != SW_OK)
+	{
+		SSDK_ERROR("Alloc hw entries fail for rule %d\n", rule_id);
+		aos_unlock_bh(&hppe_acl_lock[dev_id]);
+		return rv;
+	}
+	/* msg for debug */
+	SSDK_DEBUG("ACL rule add before:list_id=%d, hw_list_index=%d, hw_list_id=%d, "
+		"free_hw_entry_bitmap=0x%x, free_hw_entry_count=%d\n", list_id, hw_list_index,
+		g_acl_hw_list[dev_id][hw_list_index].hw_list_id,
+		g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_bitmap,
+		g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_count);
+
+	hw_list_id = g_acl_hw_list[dev_id][hw_list_index].hw_list_id;
+	rv = _adpt_hppe_acl_rule_hw_add(dev_id, list_find_entry, hw_list_id, rule_id, rule_nr, rule,
+		rule_type_map, s_acl_entries[index].entries);
+	if(rv != SW_OK)
+	{
+		aos_unlock_bh(&hppe_acl_lock[dev_id]);
+		return rv;
+	}
+
+	if(s_acl_entries[index].ext_1 != 0)
+	{
+		rv |= hppe_rule_ext_1_reg_get(dev_id, hw_list_id, &ext_1);
+		ext_1.val |= s_acl_entries[index].ext_1;
+		SSDK_DEBUG("ext_1.val = 0x%x\n", ext_1.val);
+		rv |= hppe_rule_ext_1_reg_set(dev_id, hw_list_id, &ext_1);
+	}
+	if(s_acl_entries[index].ext_2 != 0)
+	{
+		rv |= hppe_rule_ext_2_reg_get(dev_id, hw_list_id, &ext_2);
+		ext_2.val |= s_acl_entries[index].ext_2;
+		SSDK_DEBUG("ext_2.val = 0x%x\n", ext_2.val);
+		rv |= hppe_rule_ext_2_reg_set(dev_id, hw_list_id, &ext_2);
+	}
+	if(s_acl_entries[index].ext_4 != 0)
+	{
+		rv |= hppe_rule_ext_4_reg_get(dev_id, hw_list_id, &ext_4);
+		ext_4.val |= s_acl_entries[index].ext_4;
+		SSDK_DEBUG("ext_4.val = 0x%x\n", ext_4.val);
+		rv |= hppe_rule_ext_4_reg_set(dev_id, hw_list_id, &ext_4);
+	}
+
+	/*record sw info and insert the sw rule entry to the sw list entry*/
+	rule_add_entry = (ADPT_HPPE_ACL_SW_RULE*)aos_mem_alloc(sizeof(ADPT_HPPE_ACL_SW_RULE));
+	if(rule_add_entry == NULL)
+	{
+		SSDK_ERROR("%s, %d:malloc fail for rule add entry\n", __FUNCTION__, __LINE__);
+		aos_unlock_bh(&hppe_acl_lock[dev_id]);
+		return SW_FAIL;
+	}
+	rule_add_entry->rule_id = rule_id;
+	rule_add_entry->rule_type = rule->rule_type;
+	rule_add_entry->rule_hw_entry = s_acl_entries[index].entries;
+	rule_add_entry->rule_hw_list_id = hw_list_id;
+	rule_add_entry->ext1_val = s_acl_entries[index].ext_1;
+	rule_add_entry->ext2_val = s_acl_entries[index].ext_2;
+	rule_add_entry->ext4_val = s_acl_entries[index].ext_4;
+	list_add(&rule_add_entry->list, &list_find_entry->list_sw_rule);
+
+	/*update hw list info */
+	g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_bitmap &=
+		(~(s_acl_entries[index].entries));
+	g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_count -= s_acl_entries[index].num;
+
+	/* msg for debug */
+	SSDK_DEBUG("ACL rule add after:list_id=%d, hw_list_index=%d, hw_list_id=%d, "
+		"free_hw_entry_bitmap=0x%x, free_hw_entry_count=%d\n", list_id, hw_list_index,
+		hw_list_id, g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_bitmap,
+		g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_count);
+	/*resort hw list */
+	 _adpt_hppe_acl_hw_list_resort(dev_id, hw_list_index, A_TRUE);
+
+	aos_unlock_bh(&hppe_acl_lock[dev_id]);
+	return SW_OK;
+}
+
+static sw_error_t
+_adpt_hppe_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+		ADPT_HPPE_ACL_SW_RULE *rule_entry, a_uint32_t rule_nr)
+{
+	sw_error_t rv = 0;
+	a_uint32_t hw_index = 0, hw_entries = 0, hw_list_id = 0, hw_list_index = 0, i = 0;
+	union ipo_rule_reg_u hw_reg = {0};
+	union ipo_mask_reg_u hw_mask = {0};
+	union ipo_action_u hw_act = {0};
+	union rule_ext_1_reg_u ext_1 = {0};
+	union rule_ext_2_reg_u ext_2 = {0};
+	union rule_ext_4_reg_u ext_4 = {0};
+
+	hw_entries = rule_entry->rule_hw_entry;
+	hw_list_id = rule_entry->rule_hw_list_id;
+	/* msg for debug */
+	SSDK_DEBUG("ACL delete rule entry before:list_id=%d, rule_id=%d, "
+		"hw_entries=0x%x, hw_list_id=%d\n", list_id,
+		rule_entry->rule_id, rule_entry->rule_hw_entry,
+		rule_entry->rule_hw_list_id);
+	while(hw_entries != 0)
+	{
+		union ipo_cnt_tbl_u counters = {0};
+		hw_index = _acl_bit_index(hw_entries, ADPT_ACL_ENTRY_NUM_PER_LIST, 0);
+		if(hw_index >= ADPT_ACL_ENTRY_NUM_PER_LIST)
+		{
+			break;
+		}
+
+		rv |= hppe_ipo_rule_reg_set(dev_id,
+			hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, &hw_reg);
+		rv |= hppe_ipo_mask_reg_set(dev_id,
+			hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, &hw_mask);
+		rv |= hppe_ipo_action_set(dev_id,
+			hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, &hw_act);
+		SSDK_DEBUG("ACL destroy entry %d\n",
+			hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index);
+		hw_entries &= (~(1<<hw_index));
+
+		/*clean counters*/
+		hppe_ipo_cnt_tbl_set(dev_id,
+			hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, &counters);
+	}
+
+	if(rule_entry->ext1_val)
+	{
+		rv |= hppe_rule_ext_1_reg_get(dev_id, hw_list_id, &ext_1);
+		ext_1.val &= (~rule_entry->ext1_val);
+		SSDK_DEBUG("ext_1.val = 0x%x\n", ext_1.val);
+		rv |= hppe_rule_ext_1_reg_set(dev_id, hw_list_id, &ext_1);
+	}
+	if(rule_entry->ext2_val)
+	{
+		rv |= hppe_rule_ext_2_reg_get(dev_id, hw_list_id, &ext_2);
+		ext_2.val &= (~rule_entry->ext2_val);
+		SSDK_DEBUG("ext_2.val = 0x%x\n", ext_2.val);
+		rv |= hppe_rule_ext_2_reg_set(dev_id, hw_list_id, &ext_2);
+	}
+	if(rule_entry->ext4_val)
+	{
+		rv |= hppe_rule_ext_4_reg_get(dev_id, hw_list_id, &ext_4);
+		ext_4.val &= (~rule_entry->ext4_val);
+		SSDK_DEBUG("ext_4.val = 0x%x\n", ext_4.val);
+		rv |= hppe_rule_ext_4_reg_set(dev_id, hw_list_id, &ext_4);
+	}
+
+	/*find hw_list_index*/
+	for(i = 0; i < ADPT_ACL_HW_LIST_NUM; i++)
+	{
+		if(g_acl_hw_list[dev_id][i].hw_list_id == hw_list_id)
+		{
+			hw_list_index = i;
+			break;
+		}
+	}
+
+	/*update hw list info and resort hw list*/
+	g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_bitmap |= rule_entry->rule_hw_entry;
+	g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_count +=
+		_acl_bits_count(rule_entry->rule_hw_entry, ADPT_ACL_ENTRY_NUM_PER_LIST, 0);
+	/* msg for debug */
+	SSDK_DEBUG("ACL delete rule entry after:hw_list_index=%d, list_id=%d, "
+		"rule_id=%d, hw_entries=0x%x, hw_list_id=%d\n", hw_list_index,
+		list_id, rule_entry->rule_id, rule_entry->rule_hw_entry,
+		rule_entry->rule_hw_list_id);
+	_adpt_hppe_acl_hw_list_resort(dev_id, hw_list_index, A_FALSE);
+
+	/*delete rule entry from the sw list*/
+	list_del(&rule_entry->list);
+	aos_mem_free(rule_entry);
+	rule_entry = NULL;
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+		a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+	struct list_head *rule_pos = NULL;
+	ADPT_HPPE_ACL_SW_RULE *rule_delete_entry = NULL;
+	ADPT_HPPE_ACL_SW_LIST *list_find_entry = NULL;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if(list_id >= ADPT_ACL_SW_LIST_NUM)
+	{
+		return SW_OUT_OF_RANGE;
+	}
+
+	if(rule_id >= ADPT_ACL_RULE_NUM_PER_LIST)
+	{
+		return SW_OUT_OF_RANGE;
+	}
+
+	aos_lock_bh(&hppe_acl_lock[dev_id]);
+	list_find_entry = _adpt_hppe_acl_list_entry_get(dev_id, list_id);
+	if(list_find_entry != NULL)
+	{
+		list_for_each(rule_pos, &list_find_entry->list_sw_rule)
+		{
+			rule_delete_entry = list_entry(rule_pos, ADPT_HPPE_ACL_SW_RULE, list);
+			if(rule_delete_entry->rule_id == rule_id)
+			{
+				_adpt_hppe_acl_rule_delete(dev_id, list_id,
+							rule_delete_entry, rule_nr);
+				break;
+			}
+		}
+	}
+	aos_unlock_bh(&hppe_acl_lock[dev_id]);
+	return SW_OK;
+}
+
+static sw_error_t
+_adpt_hppe_acl_rule_dump(a_uint32_t dev_id, a_uint32_t list_id, ADPT_HPPE_ACL_SW_RULE *rule_entry)
+{
+	a_uint8_t i = 0;
+	a_uint8_t hw_entries = rule_entry->rule_hw_entry;
+	a_uint32_t hw_list_id = rule_entry->rule_hw_list_id;
+	union ipo_rule_reg_u hw_reg = {0};
+	union ipo_mask_reg_u hw_mask = {0};
+	union ipo_action_u hw_act = {0};
+
+	if(hw_entries != 0)
+	{
+		printk("######list_id %d, rule_id %d, hw_list_id %d\n", list_id,
+			rule_entry->rule_id, hw_list_id);
+		for(i = 0; i < ADPT_ACL_ENTRY_NUM_PER_LIST; i++)
+		{
+			if((1<<i) & hw_entries)
+			{
+				hppe_ipo_rule_reg_get(dev_id,
+					hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+i, &hw_reg);
+				hppe_ipo_mask_reg_get(dev_id,
+					hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+i, &hw_mask);
+				hppe_ipo_action_get(dev_id,
+					hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+i, &hw_act);
+				printk("hw_entry %d\n", hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+i);
+				_adpt_acl_reg_dump((u_int8_t *)&hw_reg, sizeof(hw_reg));
+				printk("hw_entry_mask %d\n",
+					hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+i);
+				_adpt_acl_reg_dump((u_int8_t *)&hw_mask, sizeof(hw_mask));
+				printk("hw_action %d\n", hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+i);
+				_adpt_acl_reg_dump((u_int8_t *)&hw_act, sizeof(hw_act));
+			}
+		}
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_acl_rule_dump(a_uint32_t dev_id)
+{
+	a_uint8_t hw_list_index = 0;
+	struct list_head *list_pos = NULL, *rule_pos = NULL;
+	ADPT_HPPE_ACL_SW_LIST *list_dump_entry = NULL;
+	ADPT_HPPE_ACL_SW_RULE *rule_dump_entry = NULL;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	/*dump the hw list status for debug*/
+	for(hw_list_index = 0; hw_list_index < ADPT_ACL_HW_LIST_NUM; hw_list_index++)
+	{
+		SSDK_DEBUG("hw_list_index=%d, hw_list_valid=%d, hw_list_id=%d, "
+			"free_hw_entry_bitmap=0x%x, free_hw_entry_count=%d\n", hw_list_index,
+			g_acl_hw_list[dev_id][ hw_list_index].hw_list_valid,
+			g_acl_hw_list[dev_id][ hw_list_index].hw_list_id,
+			g_acl_hw_list[dev_id][ hw_list_index].free_hw_entry_bitmap,
+			g_acl_hw_list[dev_id][ hw_list_index].free_hw_entry_count);
+	}
+
+	aos_lock_bh(&hppe_acl_lock[dev_id]);
+	list_for_each(list_pos, &g_acl_sw_list[dev_id].list_sw_list)
+	{
+		list_dump_entry = list_entry(list_pos, ADPT_HPPE_ACL_SW_LIST, list);
+		list_for_each(rule_pos, &list_dump_entry->list_sw_rule)
+		{
+			rule_dump_entry = list_entry(rule_pos, ADPT_HPPE_ACL_SW_RULE, list);
+			_adpt_hppe_acl_rule_dump(dev_id, list_dump_entry->list_id, rule_dump_entry);
+		}
+	}
+	aos_unlock_bh(&hppe_acl_lock[dev_id]);
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_acl_list_dump(a_uint32_t dev_id)
+{
+	adpt_hppe_acl_rule_dump(dev_id);
+
+	return SW_OK;
+}
+
+
+sw_error_t
+adpt_hppe_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri)
+{
+	ADPT_HPPE_ACL_SW_LIST *list_create_entry = NULL;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if(list_id >= ADPT_ACL_SW_LIST_NUM)
+	{
+		return SW_OUT_OF_RANGE;
+	}
+
+	aos_lock_bh(&hppe_acl_lock[dev_id]);
+	list_create_entry = _adpt_hppe_acl_list_entry_get(dev_id, list_id);
+	if(list_create_entry != NULL)
+	{
+		aos_unlock_bh(&hppe_acl_lock[dev_id]);
+		return SW_ALREADY_EXIST;
+	}
+
+	list_create_entry = (ADPT_HPPE_ACL_SW_LIST*)aos_mem_alloc(sizeof(ADPT_HPPE_ACL_SW_LIST));
+	if(list_create_entry == NULL)
+	{
+		SSDK_ERROR("%s, %d:malloc fail for list create entry\n", __FUNCTION__, __LINE__);
+		aos_unlock_bh(&hppe_acl_lock[dev_id]);
+		return SW_FAIL;
+	}
+	INIT_LIST_HEAD(&list_create_entry->list_sw_rule);
+	list_create_entry->list_id = list_id;
+	list_create_entry->list_pri = list_pri;
+	list_add(&list_create_entry->list, &g_acl_sw_list[dev_id].list_sw_list);
+	aos_unlock_bh(&hppe_acl_lock[dev_id]);
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+	struct list_head *rule_pos=NULL, *rule_pos_temp = NULL;
+	ADPT_HPPE_ACL_SW_RULE *rule_delete_entry = NULL;
+	ADPT_HPPE_ACL_SW_LIST *list_destroy_entry = NULL;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if(list_id >= ADPT_ACL_SW_LIST_NUM)
+	{
+		return SW_OUT_OF_RANGE;
+	}
+
+	aos_lock_bh(&hppe_acl_lock[dev_id]);
+	list_destroy_entry = _adpt_hppe_acl_list_entry_get(dev_id, list_id);
+	if(list_destroy_entry != NULL)
+	{
+		list_for_each_safe(rule_pos, rule_pos_temp, &list_destroy_entry->list_sw_rule)
+		{
+			rule_delete_entry = list_entry(rule_pos, ADPT_HPPE_ACL_SW_RULE, list);
+			_adpt_hppe_acl_rule_delete(dev_id, list_id, rule_delete_entry, 1);
+		}
+		list_del(&list_destroy_entry->list);
+		aos_mem_free(list_destroy_entry);
+		list_destroy_entry = NULL;
+	}
+	aos_unlock_bh(&hppe_acl_lock[dev_id]);
+	return SW_OK;
+}
+
+typedef sw_error_t (*hppe_acl_udp_set_func)(a_uint32_t dev_id, union udf_ctrl_reg_u *udf_ctrl);
+typedef sw_error_t (*hppe_acl_udp_get_func)(a_uint32_t dev_id, union udf_ctrl_reg_u *udf_ctrl);
+
+hppe_acl_udp_set_func g_udf_set_func[FAL_ACL_UDF_BUTT][4] = {
+	{hppe_non_ip_udf0_ctrl_reg_set, hppe_non_ip_udf1_ctrl_reg_set,
+			hppe_non_ip_udf2_ctrl_reg_set, hppe_non_ip_udf3_ctrl_reg_set},
+	{hppe_ipv4_udf0_ctrl_reg_set, hppe_ipv4_udf1_ctrl_reg_set, hppe_ipv4_udf2_ctrl_reg_set,
+			hppe_ipv4_udf3_ctrl_reg_set},
+	{hppe_ipv6_udf0_ctrl_reg_set, hppe_ipv6_udf1_ctrl_reg_set, hppe_ipv6_udf2_ctrl_reg_set,
+			hppe_ipv6_udf3_ctrl_reg_set},
+};
+
+hppe_acl_udp_get_func g_udf_get_func[FAL_ACL_UDF_BUTT][4] = {
+	{hppe_non_ip_udf0_ctrl_reg_get, hppe_non_ip_udf1_ctrl_reg_get,
+			hppe_non_ip_udf2_ctrl_reg_get, hppe_non_ip_udf3_ctrl_reg_get},
+	{hppe_ipv4_udf0_ctrl_reg_get, hppe_ipv4_udf1_ctrl_reg_get, hppe_ipv4_udf2_ctrl_reg_get,
+			hppe_ipv4_udf3_ctrl_reg_get},
+	{hppe_ipv6_udf0_ctrl_reg_get, hppe_ipv6_udf1_ctrl_reg_get, hppe_ipv6_udf2_ctrl_reg_get,
+			hppe_ipv6_udf3_ctrl_reg_get},
+};
+
+sw_error_t
+adpt_hppe_acl_udf_profile_get(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx,
+			fal_acl_udf_type_t *udf_type, a_uint32_t *offset)
+{
+	union udf_ctrl_reg_u udf_ctrl = {0};
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(udf_type);
+	ADPT_NULL_POINT_CHECK(offset);
+
+	rv = g_udf_get_func[pkt_type][udf_idx](dev_id, &udf_ctrl);
+
+	if(rv != SW_OK)
+		return rv;
+
+	if(udf_ctrl.bf.udf_base == 0)
+	{
+		*udf_type = FAL_ACL_UDF_TYPE_L2;
+	}
+	else if(udf_ctrl.bf.udf_base == 1)
+	{
+		*udf_type = FAL_ACL_UDF_TYPE_L3;
+	}
+	else if(udf_ctrl.bf.udf_base == 2)
+	{
+		*udf_type = FAL_ACL_UDF_TYPE_L4;
+	}
+
+	*offset = udf_ctrl.bf.udf_offset*2;
+
+	return SW_OK;
+}
+
+
+sw_error_t
+adpt_hppe_acl_udf_profile_set(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx,
+			fal_acl_udf_type_t udf_type, a_uint32_t offset)
+{
+	union udf_ctrl_reg_u udf_ctrl = {0};
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if(udf_type == FAL_ACL_UDF_TYPE_L2)
+	{
+		udf_ctrl.bf.udf_base = 0;
+	}
+	else if(udf_type == FAL_ACL_UDF_TYPE_L3)
+	{
+		udf_ctrl.bf.udf_base = 1;
+	}
+	else if(udf_type == FAL_ACL_UDF_TYPE_L4)
+	{
+		udf_ctrl.bf.udf_base = 2;
+	}
+	else
+		return SW_NOT_SUPPORTED;
+
+	if(offset % 2)/*only support even data*/
+		return SW_BAD_VALUE;
+	udf_ctrl.bf.udf_offset = offset/2;
+
+	return g_udf_set_func[pkt_type][udf_idx](dev_id, &udf_ctrl);
+}
+
+void adpt_hppe_acl_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_acl_func_bitmap = ((1<<FUNC_ACL_LIST_CREAT)|
+						(1<<FUNC_ACL_LIST_DESTROY)|
+						(1<<FUNC_ACL_RULE_ADD)|
+						(1<<FUNC_ACL_RULE_DELETE)|
+						(1<<FUNC_ACL_RULE_QUERY)|
+						(1<<FUNC_ACL_RULE_DUMP)|
+						(1<<FUNC_ACL_LIST_BIND)|
+						(1<<FUNC_ACL_LIST_UNBIND)|
+						(1<<FUNC_ACL_UDF_PROFILE_SET)|
+						(1<<FUNC_ACL_UDF_PROFILE_GET));
+	return;
+}
+
+static void adpt_hppe_acl_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_acl_list_creat = NULL;
+	p_adpt_api->adpt_acl_list_destroy = NULL;
+	p_adpt_api->adpt_acl_rule_add = NULL;
+	p_adpt_api->adpt_acl_rule_delete = NULL;
+	p_adpt_api->adpt_acl_rule_query = NULL;
+	p_adpt_api->adpt_acl_rule_dump = NULL;
+	p_adpt_api->adpt_acl_list_dump = NULL;
+	p_adpt_api->adpt_acl_list_bind = NULL;
+	p_adpt_api->adpt_acl_list_unbind = NULL;
+	p_adpt_api->adpt_acl_udf_profile_set = NULL;
+	p_adpt_api->adpt_acl_udf_profile_get = NULL;
+
+	return;
+}
+
+sw_error_t adpt_hppe_acl_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+	a_uint8_t hw_list_index = 0;
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+	{
+		return SW_FAIL;
+	}
+
+	for(hw_list_index = 0; hw_list_index < ADPT_ACL_HW_LIST_NUM; hw_list_index++)
+	{
+		if(g_acl_hw_list[dev_id][hw_list_index].hw_list_valid == A_FALSE)
+		{
+			g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_bitmap = 0xff;
+			g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_count =
+				ADPT_ACL_ENTRY_NUM_PER_LIST;
+			g_acl_hw_list[dev_id][hw_list_index].hw_list_id =
+				ADPT_ACL_HW_LIST_NUM - 1 - hw_list_index;
+			g_acl_hw_list [dev_id][hw_list_index].hw_list_valid = A_TRUE;
+			INIT_LIST_HEAD(&g_acl_sw_list[dev_id].list_sw_list);
+		}
+	}
+
+	adpt_hppe_acl_func_unregister(dev_id, p_adpt_api);
+
+	if(p_adpt_api->adpt_acl_func_bitmap & (1<<FUNC_ACL_LIST_BIND))
+	{
+		p_adpt_api->adpt_acl_list_bind = adpt_hppe_acl_list_bind;
+	}
+	if(p_adpt_api->adpt_acl_func_bitmap & (1<<FUNC_ACL_LIST_DUMP))
+	{
+		p_adpt_api->adpt_acl_list_dump = adpt_hppe_acl_list_dump;
+	}
+	if(p_adpt_api->adpt_acl_func_bitmap & (1<<FUNC_ACL_RULE_QUERY))
+	{
+		p_adpt_api->adpt_acl_rule_query = adpt_hppe_acl_rule_query;
+	}
+	if(p_adpt_api->adpt_acl_func_bitmap & (1<<FUNC_ACL_LIST_UNBIND))
+	{
+		p_adpt_api->adpt_acl_list_unbind = adpt_hppe_acl_list_unbind;
+	}
+	if(p_adpt_api->adpt_acl_func_bitmap & (1<<FUNC_ACL_RULE_ADD))
+	{
+		p_adpt_api->adpt_acl_rule_add = adpt_hppe_acl_rule_add;
+	}
+	if(p_adpt_api->adpt_acl_func_bitmap & (1<<FUNC_ACL_RULE_DELETE))
+	{
+		p_adpt_api->adpt_acl_rule_delete = adpt_hppe_acl_rule_delete;
+	}
+	if(p_adpt_api->adpt_acl_func_bitmap & (1<<FUNC_ACL_RULE_DUMP))
+	{
+		p_adpt_api->adpt_acl_rule_dump = adpt_hppe_acl_rule_dump;
+	}
+	if(p_adpt_api->adpt_acl_func_bitmap & (1<<FUNC_ACL_LIST_CREAT))
+	{
+		p_adpt_api->adpt_acl_list_creat = adpt_hppe_acl_list_creat;
+	}
+	if(p_adpt_api->adpt_acl_func_bitmap & (1<<FUNC_ACL_LIST_DESTROY))
+	{
+		p_adpt_api->adpt_acl_list_destroy = adpt_hppe_acl_list_destroy;
+	}
+	if(p_adpt_api->adpt_acl_func_bitmap & (1<<FUNC_ACL_UDF_PROFILE_SET))
+	{
+		p_adpt_api->adpt_acl_udf_profile_set = adpt_hppe_acl_udf_profile_set;
+	}
+	if(p_adpt_api->adpt_acl_func_bitmap & (1<<FUNC_ACL_UDF_PROFILE_GET))
+	{
+		p_adpt_api->adpt_acl_udf_profile_get = adpt_hppe_acl_udf_profile_get;
+	}
+
+	aos_lock_init(&hppe_acl_lock[dev_id]);
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_bm.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_bm.c
new file mode 100755
index 0000000..1c6f087
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_bm.c
@@ -0,0 +1,452 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "fal_bm.h"
+#include "hppe_bm_reg.h"
+#include "hppe_bm.h"
+#include "hppe_portctrl_reg.h"
+#include "hppe_portctrl.h"
+#include "adpt.h"
+
+#ifndef IN_BM_MINI
+sw_error_t
+adpt_hppe_port_bufgroup_map_get(a_uint32_t dev_id, fal_port_t port,
+			a_uint8_t *group)
+{
+	sw_error_t rv = SW_OK;
+	union port_group_id_u port_group_id;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(group);
+	memset(&port_group_id, 0, sizeof(port_group_id));
+
+	rv = hppe_port_group_id_get(dev_id, port, &port_group_id);
+	if( rv != SW_OK )
+		return rv;
+
+	*group = port_group_id.bf.port_shared_group_id;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_bm_port_reserved_buffer_get(a_uint32_t dev_id, fal_port_t port,
+			a_uint16_t *prealloc_buff, a_uint16_t *react_buff)
+{
+	sw_error_t rv = SW_OK;
+	union port_fc_cfg_u port_fc_cfg;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(prealloc_buff);
+	ADPT_NULL_POINT_CHECK(react_buff);
+	memset(&port_fc_cfg, 0, sizeof(port_fc_cfg));
+
+	rv = hppe_port_fc_cfg_get(dev_id, port, &port_fc_cfg);
+	if (rv)
+		return rv;
+
+	*prealloc_buff = port_fc_cfg.bf.port_pre_alloc;
+	*react_buff = port_fc_cfg.bf.port_react_limit;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_bm_bufgroup_buffer_get(a_uint32_t dev_id, a_uint8_t group,
+			a_uint16_t *buff_num)
+{
+	sw_error_t rv = SW_OK;
+	union shared_group_cfg_u shared_group_cfg;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(buff_num);
+	memset(&shared_group_cfg, 0, sizeof(shared_group_cfg));
+
+	rv = hppe_shared_group_cfg_get(dev_id, group, &shared_group_cfg);
+	if( rv != SW_OK )
+		return rv;
+
+	*buff_num = shared_group_cfg.bf.shared_group_limit;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_bm_port_dynamic_thresh_get(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_dynamic_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+	union port_fc_cfg_u port_fc_cfg;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+	memset(&port_fc_cfg, 0, sizeof(port_fc_cfg));
+
+	rv = hppe_port_fc_cfg_get(dev_id, port, &port_fc_cfg);
+	if( rv != SW_OK )
+		return rv;
+
+	if (!port_fc_cfg.bf.port_shared_dynamic)
+		return SW_FAIL;
+
+	cfg->weight = port_fc_cfg.bf.port_shared_weight;
+	cfg->shared_ceiling = port_fc_cfg.bf.port_shared_ceiling_0 |
+				port_fc_cfg.bf.port_shared_ceiling_1 << 3;
+	cfg->resume_off = port_fc_cfg.bf.port_resume_offset;
+	cfg->resume_min_thresh = port_fc_cfg.bf.port_resume_floor_th;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_bm_ctrl_get(a_uint32_t dev_id, fal_port_t port, a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	union port_fc_mode_u port_fc_mode;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+	memset(&port_fc_mode, 0, sizeof(port_fc_mode));
+
+	rv = hppe_port_fc_mode_get(dev_id, port, &port_fc_mode);
+	if( rv != SW_OK )
+		return rv;
+
+	*enable =  port_fc_mode.bf.fc_en;
+
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+adpt_hppe_bm_bufgroup_buffer_set(a_uint32_t dev_id, a_uint8_t group,
+			a_uint16_t buff_num)
+{
+	sw_error_t rv = SW_OK;
+	union shared_group_cfg_u shared_group_cfg;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	memset(&shared_group_cfg, 0, sizeof(shared_group_cfg));
+
+	shared_group_cfg.bf.shared_group_limit = buff_num;
+	rv = hppe_shared_group_cfg_set(dev_id, group, &shared_group_cfg);
+	if( rv != SW_OK )
+		return rv;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_bufgroup_map_set(a_uint32_t dev_id, fal_port_t port,
+			a_uint8_t group)
+{
+	sw_error_t rv = SW_OK;
+	union port_group_id_u port_group_id;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	memset(&port_group_id, 0, sizeof(port_group_id));
+
+	port_group_id.bf.port_shared_group_id = group;
+	rv = hppe_port_group_id_set(dev_id, port, &port_group_id);
+	if( rv != SW_OK )
+		return rv;
+
+	return SW_OK;
+}
+
+#ifndef IN_BM_MINI
+sw_error_t
+adpt_hppe_bm_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_static_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+	union port_fc_cfg_u port_fc_cfg;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+	memset(&port_fc_cfg, 0, sizeof(port_fc_cfg));
+
+	rv = hppe_port_fc_cfg_get(dev_id, port, &port_fc_cfg);
+	if( rv != SW_OK )
+		return rv;
+
+	if (port_fc_cfg.bf.port_shared_dynamic)
+		return SW_FAIL;
+
+	cfg->resume_off = port_fc_cfg.bf.port_resume_offset;
+	cfg->max_thresh = port_fc_cfg.bf.port_shared_ceiling_0 |
+			port_fc_cfg.bf.port_shared_ceiling_1 << 3;
+
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+adpt_hppe_bm_port_reserved_buffer_set(a_uint32_t dev_id, fal_port_t port,
+			a_uint16_t prealloc_buff, a_uint16_t react_buff)
+{
+	sw_error_t rv = SW_OK;
+	union port_fc_cfg_u port_fc_cfg;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	memset(&port_fc_cfg, 0, sizeof(port_fc_cfg));
+
+	rv = hppe_port_fc_cfg_get(dev_id, port, &port_fc_cfg);
+	if (rv)
+		return rv;
+
+	port_fc_cfg.bf.port_pre_alloc = prealloc_buff;
+	port_fc_cfg.bf.port_react_limit = react_buff;
+
+	return hppe_port_fc_cfg_set(dev_id, port, &port_fc_cfg);
+}
+
+sw_error_t
+adpt_hppe_bm_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_static_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+	union port_fc_cfg_u port_fc_cfg;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+	memset(&port_fc_cfg, 0, sizeof(port_fc_cfg));
+
+	rv = hppe_port_fc_cfg_get(dev_id, port, &port_fc_cfg);
+	if( rv != SW_OK )
+		return rv;
+
+	port_fc_cfg.bf.port_resume_offset = cfg->resume_off;
+	port_fc_cfg.bf.port_shared_ceiling_0 = cfg->max_thresh;
+	port_fc_cfg.bf.port_shared_ceiling_1 = cfg->max_thresh >> 3;
+	port_fc_cfg.bf.port_shared_dynamic = 0;
+
+	return hppe_port_fc_cfg_set(dev_id, port, &port_fc_cfg);;
+}
+
+sw_error_t
+adpt_hppe_bm_port_dynamic_thresh_set(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_dynamic_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+	union port_fc_cfg_u port_fc_cfg;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+	memset(&port_fc_cfg, 0, sizeof(port_fc_cfg));
+
+	rv = hppe_port_fc_cfg_get(dev_id, port, &port_fc_cfg);
+	if( rv != SW_OK )
+		return rv;
+
+	port_fc_cfg.bf.port_shared_weight = cfg->weight;
+	port_fc_cfg.bf.port_shared_ceiling_0 = cfg->shared_ceiling;
+	port_fc_cfg.bf.port_shared_ceiling_1 = cfg->shared_ceiling >> 3;
+	port_fc_cfg.bf.port_resume_offset = cfg->resume_off;
+	port_fc_cfg.bf.port_resume_floor_th = cfg->resume_min_thresh;
+	port_fc_cfg.bf.port_shared_dynamic = 1;
+
+	return hppe_port_fc_cfg_set(dev_id, port, &port_fc_cfg);;
+}
+
+sw_error_t
+adpt_hppe_port_bm_ctrl_set(a_uint32_t dev_id, fal_port_t port, a_bool_t enable)
+{
+	union port_fc_mode_u port_fc_mode;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	memset(&port_fc_mode, 0, sizeof(port_fc_mode));
+
+	port_fc_mode.bf.fc_en = enable;
+	return hppe_port_fc_mode_set(dev_id, port, &port_fc_mode);
+}
+
+sw_error_t
+adpt_hppe_port_tdm_ctrl_set(a_uint32_t dev_id, fal_port_tdm_ctrl_t *ctrl)
+{
+	union tdm_ctrl_u tdm_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	memset(&tdm_ctrl, 0, sizeof(tdm_ctrl));
+
+	tdm_ctrl.bf.tdm_en = ctrl->enable;
+	tdm_ctrl.bf.tdm_offset = ctrl->offset;
+	tdm_ctrl.bf.tdm_depth = ctrl->depth;
+	return hppe_tdm_ctrl_set(dev_id, &tdm_ctrl);
+}
+
+sw_error_t
+adpt_hppe_port_tdm_tick_cfg_set(a_uint32_t dev_id, a_uint32_t tick_index,
+			fal_port_tdm_tick_cfg_t *cfg)
+{
+	union tdm_cfg_u tdm_cfg;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	memset(&tdm_cfg, 0, sizeof(tdm_cfg));
+
+	tdm_cfg.bf.valid = cfg->valid;
+	tdm_cfg.bf.dir = cfg->direction;
+	tdm_cfg.bf.port_num = cfg->port;
+	return hppe_tdm_cfg_set(dev_id, tick_index, &tdm_cfg);
+}
+
+#ifndef IN_BM_MINI
+sw_error_t
+adpt_hppe_bm_port_counter_get(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_port_counter_t *counter)
+{
+	sw_error_t rv = SW_OK;
+	union port_cnt_u port_cnt;
+	union port_reacted_cnt_u reacted_cnt;
+	union drop_stat_u drop_stat;
+	a_uint32_t index = FAL_PORT_ID_VALUE(port);
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(counter);
+	memset(&port_cnt, 0, sizeof(port_cnt));
+	memset(&reacted_cnt, 0, sizeof(reacted_cnt));
+
+	rv = hppe_port_cnt_get(dev_id, index, &port_cnt);
+	if( rv != SW_OK )
+		return rv;
+	counter->used_counter = port_cnt.bf.port_cnt;
+
+	rv = hppe_port_reacted_cnt_get(dev_id, index, &reacted_cnt);
+	if( rv != SW_OK )
+		return rv;
+	counter->react_counter = reacted_cnt.bf.port_reacted_cnt;
+
+	rv = hppe_drop_stat_get(dev_id, index, &drop_stat);
+	if( rv != SW_OK )
+		return rv;
+	counter->drop_byte_counter = drop_stat.bf.bytes_0 | ((a_uint64_t)drop_stat.bf.bytes_1 << 32);
+	counter->drop_packet_counter = drop_stat.bf.pkts;
+	rv = hppe_drop_stat_get(dev_id, index + 15, &drop_stat);
+	if( rv != SW_OK )
+		return rv;
+	counter->fc_drop_byte_counter = drop_stat.bf.bytes_0 | ((a_uint64_t)drop_stat.bf.bytes_1 << 32);
+	counter->fc_drop_packet_counter = drop_stat.bf.pkts;
+
+	return SW_OK;
+}
+#endif
+
+void adpt_hppe_bm_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_bm_func_bitmap = ((1 << FUNC_PORT_BUFGROUP_MAP_GET) |
+						(1 << FUNC_BM_PORT_RESERVED_BUFFER_GET) |
+						(1 << FUNC_BM_BUFGROUP_BUFFER_GET) |
+						(1 << FUNC_BM_PORT_DYNAMIC_THRESH_GET) |
+						(1 << FUNC_PORT_BM_CTRL_GET) |
+						(1 << FUNC_BM_BUFGROUP_BUFFER_SET) |
+						(1 << FUNC_PORT_BUFGROUP_MAP_SET) |
+						(1 << FUNC_BM_PORT_STATIC_THRESH_GET) |
+						(1 << FUNC_BM_PORT_RESERVED_BUFFER_SET) |
+						(1 << FUNC_BM_PORT_STATIC_THRESH_SET) |
+						(1 << FUNC_BM_PORT_DYNAMIC_THRESH_SET) |
+						(1 << FUNC_PORT_BM_CTRL_SET) |
+						(1 << FUNC_PORT_TDM_CTRL_SET) |
+						(1 << FUNC_PORT_TDM_TICK_CFG_SET) |
+						(1 << FUNC_BM_PORT_COUNTER_GET));
+	return;
+}
+
+static void adpt_hppe_bm_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_port_bufgroup_map_get = NULL;
+	p_adpt_api->adpt_bm_port_reserved_buffer_get = NULL;
+	p_adpt_api->adpt_bm_bufgroup_buffer_get = NULL;
+	p_adpt_api->adpt_bm_port_dynamic_thresh_get = NULL;
+	p_adpt_api->adpt_port_bm_ctrl_get = NULL;
+	p_adpt_api->adpt_bm_bufgroup_buffer_set = NULL;
+	p_adpt_api->adpt_port_bufgroup_map_set = NULL;
+	p_adpt_api->adpt_bm_port_static_thresh_get = NULL;
+	p_adpt_api->adpt_bm_port_reserved_buffer_set = NULL;
+	p_adpt_api->adpt_bm_port_static_thresh_set = NULL;
+	p_adpt_api->adpt_bm_port_dynamic_thresh_set = NULL;
+	p_adpt_api->adpt_port_bm_ctrl_set = NULL;
+	p_adpt_api->adpt_port_tdm_ctrl_set = NULL;
+	p_adpt_api->adpt_port_tdm_tick_cfg_set = NULL;
+	p_adpt_api->adpt_bm_port_counter_get = NULL;
+
+	return;
+}
+
+
+sw_error_t adpt_hppe_bm_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_bm_func_unregister(dev_id, p_adpt_api);
+
+#ifndef IN_BM_MINI
+	if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_PORT_BUFGROUP_MAP_GET))
+		p_adpt_api->adpt_port_bufgroup_map_get = adpt_hppe_port_bufgroup_map_get;
+	if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_PORT_RESERVED_BUFFER_GET))
+		p_adpt_api->adpt_bm_port_reserved_buffer_get = adpt_hppe_bm_port_reserved_buffer_get;
+	if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_BUFGROUP_BUFFER_GET))
+		p_adpt_api->adpt_bm_bufgroup_buffer_get = adpt_hppe_bm_bufgroup_buffer_get;
+	if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_PORT_DYNAMIC_THRESH_GET))
+		p_adpt_api->adpt_bm_port_dynamic_thresh_get = adpt_hppe_bm_port_dynamic_thresh_get;
+	if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_PORT_BM_CTRL_GET))
+		p_adpt_api->adpt_port_bm_ctrl_get = adpt_hppe_port_bm_ctrl_get;
+	if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_PORT_STATIC_THRESH_GET))
+		p_adpt_api->adpt_bm_port_static_thresh_get = adpt_hppe_bm_port_static_thresh_get;
+	if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_PORT_COUNTER_GET))
+		p_adpt_api->adpt_bm_port_counter_get = adpt_hppe_bm_port_counter_get;
+#endif
+	if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_BUFGROUP_BUFFER_SET))
+		p_adpt_api->adpt_bm_bufgroup_buffer_set = adpt_hppe_bm_bufgroup_buffer_set;
+	if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_PORT_BUFGROUP_MAP_SET))
+		p_adpt_api->adpt_port_bufgroup_map_set = adpt_hppe_port_bufgroup_map_set;
+	if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_PORT_RESERVED_BUFFER_SET))
+		p_adpt_api->adpt_bm_port_reserved_buffer_set = adpt_hppe_bm_port_reserved_buffer_set;
+	if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_PORT_STATIC_THRESH_SET))
+		p_adpt_api->adpt_bm_port_static_thresh_set = adpt_hppe_bm_port_static_thresh_set;
+	if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_PORT_DYNAMIC_THRESH_SET))
+		p_adpt_api->adpt_bm_port_dynamic_thresh_set = adpt_hppe_bm_port_dynamic_thresh_set;
+	if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_PORT_BM_CTRL_SET))
+		p_adpt_api->adpt_port_bm_ctrl_set = adpt_hppe_port_bm_ctrl_set;
+	if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_PORT_TDM_CTRL_SET))
+		p_adpt_api->adpt_port_tdm_ctrl_set = adpt_hppe_port_tdm_ctrl_set;
+	if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_PORT_TDM_TICK_CFG_SET))
+		p_adpt_api->adpt_port_tdm_tick_cfg_set = adpt_hppe_port_tdm_tick_cfg_set;
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_ctrlpkt.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_ctrlpkt.c
new file mode 100755
index 0000000..d4659f1
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_ctrlpkt.c
@@ -0,0 +1,385 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_ctrlpkt_reg.h"
+#include "hppe_ctrlpkt.h"
+#include "hppe_fdb_reg.h"
+#include "hppe_fdb.h"
+#include "adpt.h"
+
+a_uint32_t
+_get_mgmtctrl_ctrlpkt_profile_by_index(a_uint32_t dev_id, a_uint32_t index, fal_ctrlpkt_profile_t *ctrlpkt)
+{
+	union app_ctrl_u entry;
+
+	SW_RTN_ON_ERROR(hppe_app_ctrl_get(dev_id, index, &entry));
+
+	ctrlpkt->action.action = entry.bf.cmd;
+	ctrlpkt->action.sg_bypass = entry.bf.sg_byp;
+	ctrlpkt->action.l2_filter_bypass = entry.bf.l2_sec_byp;
+	ctrlpkt->action.in_stp_bypass = entry.bf.in_stg_byp;
+	ctrlpkt->action.in_vlan_fltr_bypass = entry.bf.in_vlan_fltr_byp;
+
+	if (entry.bf.portbitmap_include)
+		ctrlpkt->port_map = entry.bf.portbitmap;
+
+	if (entry.bf.ethertype_include)
+		ctrlpkt->ethtype_profile_bitmap = entry.bf.ethertype_index_bitmap_0 | (entry.bf.ethertype_index_bitmap_1 << 2);
+
+	if (entry.bf.rfdb_include)
+		ctrlpkt->rfdb_profile_bitmap = entry.bf.rfdb_index_bitmap_0| (entry.bf.rfdb_index_bitmap_1 << 30);
+
+	if (entry.bf.protocol_include) {
+		ctrlpkt->protocol_types.mgt_eapol = (entry.bf.protocol_bitmap & (0x1 << 0))?1:0;
+		ctrlpkt->protocol_types.mgt_pppoe = (entry.bf.protocol_bitmap & (0x1 << 1))?1:0;
+		ctrlpkt->protocol_types.mgt_igmp = (entry.bf.protocol_bitmap & (0x1 << 2))?1:0;
+		ctrlpkt->protocol_types.mgt_arp_req = (entry.bf.protocol_bitmap & (0x1 << 3))?1:0;
+		ctrlpkt->protocol_types.mgt_arp_rep = (entry.bf.protocol_bitmap & (0x1 << 4))?1:0;
+		ctrlpkt->protocol_types.mgt_dhcp4 = (entry.bf.protocol_bitmap & (0x1 << 5))?1:0;
+		ctrlpkt->protocol_types.mgt_mld = (entry.bf.protocol_bitmap & (0x1 << 6))?1:0;
+		ctrlpkt->protocol_types.mgt_ns = (entry.bf.protocol_bitmap & (0x1 << 7))?1:0;
+		ctrlpkt->protocol_types.mgt_na = (entry.bf.protocol_bitmap & (0x1 << 8))?1:0;
+		ctrlpkt->protocol_types.mgt_dhcp6 = (entry.bf.protocol_bitmap & (0x1 << 9))?1:0;
+	}
+
+	return entry.bf.valid;
+}
+
+a_uint32_t
+_check_if_ctrlpkt_equal(fal_ctrlpkt_profile_t *ctrlpkt1, fal_ctrlpkt_profile_t *ctrlpkt2)
+{
+	if (ctrlpkt1->action.action == ctrlpkt2->action.action &&
+		ctrlpkt1->action.sg_bypass == ctrlpkt2->action.sg_bypass &&
+		ctrlpkt1->action.l2_filter_bypass == ctrlpkt2->action.l2_filter_bypass &&
+		ctrlpkt1->action.in_stp_bypass == ctrlpkt2->action.in_stp_bypass &&
+		ctrlpkt1->action.in_vlan_fltr_bypass == ctrlpkt2->action.in_vlan_fltr_bypass &&
+		ctrlpkt1->port_map == ctrlpkt2->port_map &&
+		ctrlpkt1->ethtype_profile_bitmap == ctrlpkt2->ethtype_profile_bitmap &&
+		ctrlpkt1->rfdb_profile_bitmap == ctrlpkt2->rfdb_profile_bitmap &&
+		ctrlpkt1->protocol_types.mgt_eapol == ctrlpkt2->protocol_types.mgt_eapol &&
+		ctrlpkt1->protocol_types.mgt_pppoe == ctrlpkt2->protocol_types.mgt_pppoe &&
+		ctrlpkt1->protocol_types.mgt_igmp == ctrlpkt2->protocol_types.mgt_igmp &&
+		ctrlpkt1->protocol_types.mgt_arp_req == ctrlpkt2->protocol_types.mgt_arp_req &&
+		ctrlpkt1->protocol_types.mgt_arp_rep == ctrlpkt2->protocol_types.mgt_arp_rep &&
+		ctrlpkt1->protocol_types.mgt_dhcp4 == ctrlpkt2->protocol_types.mgt_dhcp4 &&
+		ctrlpkt1->protocol_types.mgt_mld == ctrlpkt2->protocol_types.mgt_mld &&
+		ctrlpkt1->protocol_types.mgt_ns == ctrlpkt2->protocol_types.mgt_ns &&
+		ctrlpkt1->protocol_types.mgt_na == ctrlpkt2->protocol_types.mgt_na &&
+		ctrlpkt1->protocol_types.mgt_dhcp6 == ctrlpkt2->protocol_types.mgt_dhcp6)
+		return 1;
+
+	return 0;
+}
+
+sw_error_t
+adpt_hppe_mgmtctrl_ethtype_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t ethtype)
+{
+	sw_error_t rtn = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	SW_RTN_ON_ERROR(hppe_ethertype_ctrl_ethertype_set(dev_id, profile_id, ethtype));
+	SW_RTN_ON_ERROR(hppe_ethertype_ctrl_ethertype_en_set(dev_id, profile_id, A_TRUE));
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_mgmtctrl_ethtype_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t *ethtype)
+{
+	sw_error_t rtn = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ethtype);
+
+	SW_RTN_ON_ERROR(hppe_ethertype_ctrl_ethertype_get(dev_id, profile_id, ethtype));
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_mgmtctrl_rfdb_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr)
+{
+	sw_error_t rtn = SW_OK;
+	a_uint64_t value = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (profile_id >= RFDB_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+
+	value = ((((a_uint64_t)(addr->uc[5])) << 0) |
+			(((a_uint64_t)(addr->uc[4])) << 8) |
+			(((a_uint64_t)(addr->uc[3])) << 16) |
+			(((a_uint64_t)(addr->uc[2])) << 24) |
+			(((a_uint64_t)(addr->uc[1])) << 32) |
+			(((a_uint64_t)(addr->uc[0])) << 40));
+
+	SW_RTN_ON_ERROR(hppe_rfdb_tbl_mac_addr_set(dev_id, profile_id, value));
+	SW_RTN_ON_ERROR(hppe_rfdb_tbl_valid_set(dev_id, profile_id, A_TRUE));
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_mgmtctrl_rfdb_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr)
+{
+	sw_error_t rtn = SW_OK;
+	a_uint64_t value = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(addr);
+
+	if (profile_id >= RFDB_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+
+	SW_RTN_ON_ERROR(hppe_rfdb_tbl_mac_addr_get(dev_id, profile_id, &value));
+	addr->uc[0] = (a_uint8_t)((value >> 40)& 0xff);
+	addr->uc[1] = (a_uint8_t)((value >> 32) & 0xff);
+	addr->uc[2] = (a_uint8_t)((value >> 24) & 0xff);
+	addr->uc[3] = (a_uint8_t)((value >> 16) & 0xff);
+	addr->uc[4] = (a_uint8_t)((value >> 8) & 0xff);
+	addr->uc[5] = (a_uint8_t)((value >> 0) & 0xff);
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_mgmtctrl_ctrlpkt_profile_add(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt)
+{
+	union app_ctrl_u entry;
+	a_uint32_t index, ctrlpkt_valid, entry_sign, entry_index;
+	fal_ctrlpkt_profile_t ctrlpkt_temp;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	entry_index = 0;
+	entry_sign = 0;
+	for (index = 0; index < APP_CTRL_MAX_ENTRY; index++)
+	{
+		memset(&ctrlpkt_temp, 0, sizeof(fal_ctrlpkt_profile_t));
+		ctrlpkt_valid = _get_mgmtctrl_ctrlpkt_profile_by_index(dev_id, index, &ctrlpkt_temp);
+		if (ctrlpkt_valid == 1)
+		{
+			if (_check_if_ctrlpkt_equal(&ctrlpkt_temp, ctrlpkt))
+				return SW_ALREADY_EXIST;
+		}
+		else
+		{
+			if (entry_sign == 0) {
+				entry_index = index;
+				entry_sign = 1;
+			}
+		}
+	}
+
+	if (entry_sign == 0)
+		return SW_NO_RESOURCE;
+
+	memset(&entry, 0, sizeof(union app_ctrl_u));
+
+	entry.bf.valid = A_TRUE;
+	entry.bf.rfdb_include = ctrlpkt->rfdb_profile_bitmap?1:0;
+	entry.bf.rfdb_index_bitmap_0 = (ctrlpkt->rfdb_profile_bitmap & 0x3fffffff);
+	entry.bf.rfdb_index_bitmap_1 = (ctrlpkt->rfdb_profile_bitmap >> 30);
+
+	if (ctrlpkt->protocol_types.mgt_eapol)
+		entry.bf.protocol_bitmap |= (0x1 << 0);
+	if (ctrlpkt->protocol_types.mgt_pppoe)
+		entry.bf.protocol_bitmap |= (0x1 << 1);
+	if (ctrlpkt->protocol_types.mgt_igmp)
+		entry.bf.protocol_bitmap |= (0x1 << 2);
+	if (ctrlpkt->protocol_types.mgt_arp_req)
+		entry.bf.protocol_bitmap |= (0x1 << 3);
+	if (ctrlpkt->protocol_types.mgt_arp_rep)
+		entry.bf.protocol_bitmap |= (0x1 << 4);
+	if (ctrlpkt->protocol_types.mgt_dhcp4)
+		entry.bf.protocol_bitmap |= (0x1 << 5);
+	if (ctrlpkt->protocol_types.mgt_mld)
+		entry.bf.protocol_bitmap |= (0x1 << 6);
+	if (ctrlpkt->protocol_types.mgt_ns)
+		entry.bf.protocol_bitmap |= (0x1 << 7);
+	if (ctrlpkt->protocol_types.mgt_na)
+		entry.bf.protocol_bitmap |= (0x1 << 8);
+	if (ctrlpkt->protocol_types.mgt_dhcp6)
+		entry.bf.protocol_bitmap |= (0x1 << 9);
+
+	entry.bf.protocol_include = entry.bf.protocol_bitmap?1:0;
+
+	entry.bf.ethertype_include = ctrlpkt->ethtype_profile_bitmap?1:0;
+	entry.bf.ethertype_index_bitmap_0 = (ctrlpkt->ethtype_profile_bitmap & 0x3);
+	entry.bf.ethertype_index_bitmap_1 = (ctrlpkt->ethtype_profile_bitmap >> 2);
+
+	entry.bf.portbitmap_include = ctrlpkt->port_map?1:0;
+	entry.bf.portbitmap = ctrlpkt->port_map;
+
+	entry.bf.in_vlan_fltr_byp = ctrlpkt->action.in_vlan_fltr_bypass?1:0;
+	entry.bf.in_stg_byp = ctrlpkt->action.in_stp_bypass?1:0;
+	entry.bf.l2_sec_byp = ctrlpkt->action.l2_filter_bypass?1:0;
+	entry.bf.sg_byp = ctrlpkt->action.sg_bypass?1:0;
+	entry.bf.cmd = (a_uint32_t)ctrlpkt->action.action;
+	SW_RTN_ON_ERROR(hppe_app_ctrl_set(dev_id, entry_index, &entry));
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_mgmtctrl_ctrlpkt_profile_del(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt)
+{
+	a_uint32_t index, ctrlpkt_valid;
+	union app_ctrl_u entry;
+	fal_ctrlpkt_profile_t ctrlpkt_temp;
+
+	memset(&entry, 0, sizeof(union app_ctrl_u));
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrlpkt);
+
+	for (index = 0; index < APP_CTRL_MAX_ENTRY; index++)
+	{
+		memset(&ctrlpkt_temp, 0, sizeof(fal_ctrlpkt_profile_t));
+		ctrlpkt_valid = _get_mgmtctrl_ctrlpkt_profile_by_index(dev_id, index, &ctrlpkt_temp);
+		if (ctrlpkt_valid == 1)
+		{
+			if (_check_if_ctrlpkt_equal(&ctrlpkt_temp, ctrlpkt))
+			{
+				SW_RTN_ON_ERROR(hppe_app_ctrl_set(dev_id, index, &entry));
+				return SW_OK;
+			}
+		}
+	}
+
+	return SW_NOT_FOUND;
+}
+
+sw_error_t
+adpt_hppe_mgmtctrl_ctrlpkt_profile_getfirst(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt)
+{
+	a_uint32_t index, ctrlpkt_valid;
+
+	for (index = 0; index < APP_CTRL_MAX_ENTRY; index++)
+	{
+		ctrlpkt_valid = _get_mgmtctrl_ctrlpkt_profile_by_index(dev_id, index, ctrlpkt);
+		if (ctrlpkt_valid == 1)
+			return SW_OK;
+	}
+
+	return SW_NO_MORE;
+}
+
+sw_error_t
+adpt_hppe_mgmtctrl_ctrlpkt_profile_getnext(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt)
+{
+	a_uint32_t index, ctrlpkt_valid, sign_tag;
+	fal_ctrlpkt_profile_t ctrlpkt_temp;
+
+	sign_tag = 0;
+
+	for (index = 0; index < APP_CTRL_MAX_ENTRY; index++)
+	{
+		memset(&ctrlpkt_temp, 0, sizeof(fal_ctrlpkt_profile_t));
+		ctrlpkt_valid = _get_mgmtctrl_ctrlpkt_profile_by_index(dev_id, index, &ctrlpkt_temp);
+		if (ctrlpkt_valid == 1)
+		{
+			if (sign_tag == 1) {
+				aos_mem_copy(ctrlpkt, &ctrlpkt_temp, sizeof(fal_ctrlpkt_profile_t));
+				return SW_OK;
+			}
+			if (_check_if_ctrlpkt_equal(&ctrlpkt_temp, ctrlpkt))
+				sign_tag = 1;
+		}
+	}
+
+	return SW_NO_MORE;
+}
+
+void adpt_hppe_ctrlpkt_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_ctrlpkt_func_bitmap = ((1 << FUNC_MGMTCTRL_ETHTYPE_PROFILE_SET) |
+						(1 << FUNC_MGMTCTRL_ETHTYPE_PROFILE_GET) |
+						(1 << FUNC_MGMTCTRL_RFDB_PROFILE_SET) |
+						(1 << FUNC_MGMTCTRL_RFDB_PROFILE_GET) |
+						(1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_ADD) |
+						(1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_DEL) |
+						(1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST) |
+						(1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT));
+
+	return;
+}
+
+static void adpt_hppe_ctrlpkt_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_mgmtctrl_ethtype_profile_set = NULL;
+	p_adpt_api->adpt_mgmtctrl_ethtype_profile_get = NULL;
+	p_adpt_api->adpt_mgmtctrl_rfdb_profile_set = NULL;
+	p_adpt_api->adpt_mgmtctrl_rfdb_profile_get = NULL;
+	p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_add = NULL;
+	p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_del = NULL;
+	p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_getfirst = NULL;
+	p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_getnext = NULL;
+
+	return;
+}
+
+sw_error_t adpt_hppe_ctrlpkt_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_ctrlpkt_func_unregister(dev_id, p_adpt_api);
+
+	if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_ETHTYPE_PROFILE_SET))
+		p_adpt_api->adpt_mgmtctrl_ethtype_profile_set = adpt_hppe_mgmtctrl_ethtype_profile_set;
+	if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_ETHTYPE_PROFILE_GET))
+		p_adpt_api->adpt_mgmtctrl_ethtype_profile_get = adpt_hppe_mgmtctrl_ethtype_profile_get;
+	if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_RFDB_PROFILE_SET))
+		p_adpt_api->adpt_mgmtctrl_rfdb_profile_set = adpt_hppe_mgmtctrl_rfdb_profile_set;
+	if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_RFDB_PROFILE_GET))
+		p_adpt_api->adpt_mgmtctrl_rfdb_profile_get = adpt_hppe_mgmtctrl_rfdb_profile_get;
+	if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_ADD))
+		p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_add = adpt_hppe_mgmtctrl_ctrlpkt_profile_add;
+	if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_DEL))
+		p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_del = adpt_hppe_mgmtctrl_ctrlpkt_profile_del;
+	if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST))
+		p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_getfirst = adpt_hppe_mgmtctrl_ctrlpkt_profile_getfirst;
+	if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT))
+		p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_getnext = adpt_hppe_mgmtctrl_ctrlpkt_profile_getnext;
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_fdb.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_fdb.c
new file mode 100755
index 0000000..2d8a635
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_fdb.c
@@ -0,0 +1,1520 @@
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_fdb_reg.h"
+#include "hppe_fdb.h"
+#include "adpt.h"
+
+#define OP_TYPE_ADD	0x0
+#define OP_TYPE_DEL	0x1
+#define OP_TYPE_GET	0x2
+#define OP_TYPE_FLUSH	0x4
+#define OP_TYPE_AGE	0x5
+
+#define OP_MODE_HASH	0x0
+#define OP_MODE_INDEX	0x1
+
+#define OP_CMD_ID_SIZE	0xf
+
+#define OP_FIFO_CNT_SIZE	0x8
+
+#define ARL_FIRST_ENTRY		0x0
+#define ARL_NEXT_ENTRY		0x1
+#define ARL_EXTENDFIRST_ENTRY	0x2
+#define ARL_EXTENDNEXT_ENTRY	0x3
+
+
+static aos_lock_t hppe_fdb_lock;
+
+/*
+ * Remove port type.
+ * Current fal_port_t format:
+ * 1) highest 8 bits is defined as port type.
+ * 2) lowest 24 bits for port id value.
+ * The range of physical port id is 0-7, the range of trunk id is 32-33, and the range of virtual port is 64-255.
+ * Port type: 0 is physical port, 1 is trunk port, 2 is virtual port.
+ */
+sw_error_t
+_remove_port_type(fal_port_t * port_id)
+{
+	*port_id = FAL_PORT_ID_VALUE(*port_id);
+	return SW_OK;
+}
+
+/*
+ * Add port type.
+ * Current fal_port_t format:
+ * 1) highest 8 bits is defined as port type.
+ * 2) lowest 24 bits for port id value.
+ * The range of physical port id is 0-7, the range of trunk id is 32-33, and the range of virtual port is 64-255.
+ * Port type: 0 is physical port, 1 is trunk port, 2 is virtual port.
+ */
+sw_error_t
+_add_port_type(a_bool_t bitmap, fal_port_t * port_id)
+{
+	if (bitmap == A_TRUE)
+		return SW_OK;
+
+	if (*port_id == 32 || *port_id == 33)
+		*port_id = FAL_PORT_ID(FAL_PORT_TYPE_TRUNK, *port_id);
+	else if (*port_id >= 64)
+		*port_id = FAL_PORT_ID(FAL_PORT_TYPE_VPORT, *port_id);
+	return SW_OK;
+}
+
+/*
+ * set values to register FDB_TBL_OP
+ */
+sw_error_t
+_adpt_hppe_fdb_tbl_op_reg_set(a_uint32_t dev_id, a_uint32_t cmd_id, a_uint32_t op_type)
+{
+	sw_error_t rv = SW_OK;
+	union fdb_tbl_op_u reg_val_op;
+	a_uint32_t op_mode = OP_MODE_HASH;
+	a_uint32_t entry_index = 0x0;
+
+	reg_val_op.bf.cmd_id = cmd_id;
+	reg_val_op.bf.byp_rslt_en = 0x0;
+	reg_val_op.bf.op_type = op_type;
+	reg_val_op.bf.hash_block_bitmap = 0x3;
+	reg_val_op.bf.op_mode = op_mode;
+	reg_val_op.bf.entry_index = entry_index;
+	rv = hppe_fdb_tbl_op_set(dev_id, &reg_val_op);
+
+	return rv;
+}
+
+/*
+ * get results from register FDB_TBL_OP_RSLT
+ */
+sw_error_t
+_adpt_hppe_fdb_tbl_op_rslt_reg_get(a_uint32_t dev_id, a_uint32_t cmd_id)
+{
+	sw_error_t rv = SW_OK;
+	union fdb_tbl_op_rslt_u reg_val_op_rslt;
+
+	rv = hppe_fdb_tbl_op_rslt_get(dev_id, &reg_val_op_rslt);
+
+	if (rv != SW_OK || reg_val_op_rslt.bf.cmd_id != cmd_id || reg_val_op_rslt.bf.valid_cnt > OP_FIFO_CNT_SIZE)
+		return SW_FAIL;
+
+	return SW_OK;
+}
+
+/*
+ * set values to register FDB_TBL_RD_OP
+ */
+sw_error_t
+_adpt_hppe_fdb_tbl_rd_op_reg_set(a_uint32_t dev_id, a_uint32_t cmd_id, a_uint32_t op_mode, a_uint32_t entry_index)
+{
+	sw_error_t rv = SW_OK;
+	union fdb_tbl_rd_op_u reg_val_rd_op;
+	a_uint32_t op_type = OP_TYPE_GET;
+
+	reg_val_rd_op.bf.cmd_id = cmd_id;
+	reg_val_rd_op.bf.byp_rslt_en = 0x0;
+	reg_val_rd_op.bf.op_type = op_type;
+	reg_val_rd_op.bf.hash_block_bitmap = 0x3;
+	reg_val_rd_op.bf.op_mode = op_mode;
+	reg_val_rd_op.bf.entry_index = entry_index;
+	rv = hppe_fdb_tbl_rd_op_set(dev_id, &reg_val_rd_op);
+
+	return rv;
+}
+
+/*
+ * get results from register FDB_TBL_RD_OP_RSLT
+ */
+sw_error_t
+_adpt_hppe_fdb_tbl_rd_op_rslt_reg_get(a_uint32_t dev_id, a_uint32_t cmd_id, a_uint32_t *entry_index)
+{
+	sw_error_t rv = SW_OK;
+	union fdb_tbl_rd_op_rslt_u reg_val_rd_op_rslt;
+
+	rv = hppe_fdb_tbl_rd_op_rslt_get(dev_id, &reg_val_rd_op_rslt);
+
+	if (rv != SW_OK || reg_val_rd_op_rslt.bf.cmd_id != cmd_id ||
+		reg_val_rd_op_rslt.bf.valid_cnt > OP_FIFO_CNT_SIZE)
+	{
+		return SW_FAIL;
+	}
+
+	*entry_index = reg_val_rd_op_rslt.bf.entry_index;
+
+	return SW_OK;
+}
+
+/*
+ * set values to register FDB_TBL_OP_DATA0/FDB_TBL_OP_DATA1/FDB_TBL_OP_DATA2
+ */
+sw_error_t
+_adpt_hppe_fdb_tbl_op_data_reg_set(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t i, port_value, dst_type = 0x0;
+	a_uint32_t reg_value[3] = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	for (i = 2; i < 6; i++)
+	{
+		reg_value[0] = (reg_value[0] << 8) + entry->addr.uc[i];
+	}
+	rv = hppe_fdb_tbl_op_data0_data_set(dev_id, reg_value[0]);
+	if (rv != SW_OK)
+		return rv;
+
+	for (i = 0; i < 2; i++)
+	{
+		reg_value[1] = (reg_value[1] << 8) + entry->addr.uc[i];
+	}
+	reg_value[1] += (0x1 << (FDB_TBL_ENTRY_VALID_OFFSET - 32)) + (0x1 << (FDB_TBL_LOOKUP_VALID_OFFSET -32)) +
+			(entry->fid << (FDB_TBL_VSI_OFFSET - 32));
+	if (entry->portmap_en == A_TRUE)
+	{
+		port_value = entry->port.map;
+		dst_type = 0x3;
+	}
+	else
+	{
+		port_value = entry->port.id;
+		dst_type = 0x2;
+	}
+	reg_value[1] += ((port_value & 0x1ff) << (FDB_TBL_DST_INFO_OFFSET - 32));
+	rv = hppe_fdb_tbl_op_data1_data_set(dev_id, reg_value[1]);
+	if (rv != SW_OK)
+		return rv;
+
+	reg_value[2] = ((port_value >> 0x9) & 0x7) + ((dst_type & 0x3) << 3) +
+			((entry->sacmd & 0x3) << (FDB_TBL_SA_CMD_OFFSET - 64)) +
+			((entry->dacmd & 0x3) << (FDB_TBL_DA_CMD_OFFSET - 64));
+	if (entry->static_en == A_TRUE)
+		reg_value[2] += (0x3 << (FDB_TBL_HIT_AGE_OFFSET - 64));
+	else
+		reg_value[2] += (0x2 << (FDB_TBL_HIT_AGE_OFFSET - 64));
+	rv = hppe_fdb_tbl_op_data2_data_set(dev_id, reg_value[2]);
+	if (rv != SW_OK)
+		return rv;
+
+	return SW_OK;
+}
+
+/*
+ * set values to register FDB_TBL_RD_OP_DATA0/FDB_TBL_RD_OP_DATA1/FDB_TBL_RD_OP_DATA2
+ */
+sw_error_t
+_adpt_hppe_fdb_tbl_rd_op_data_reg_set(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t i, reg_value[3] = {0};
+
+	for (i = 2; i < 6; i++)
+	{
+		reg_value[0] = (reg_value[0] << 8) + entry->addr.uc[i];
+	}
+	rv = hppe_fdb_tbl_rd_op_data0_data_set(dev_id, reg_value[0]);
+	if (rv != SW_OK)
+		return rv;
+
+	for (i = 0; i < 2; i++)
+	{
+		reg_value[1] = (reg_value[1] << 8) + entry->addr.uc[i];
+	}
+	reg_value[1] += (entry->fid << (FDB_TBL_VSI_OFFSET - 32));
+	rv = hppe_fdb_tbl_rd_op_data1_data_set(dev_id, reg_value[1]);
+	if (rv != SW_OK)
+		return rv;
+
+	rv = hppe_fdb_tbl_rd_op_data2_data_set(dev_id, reg_value[2]);
+	if (rv != SW_OK)
+		return rv;
+
+	return SW_OK;
+}
+
+/*
+ * get values from register FDB_TBL_RD_OP_RSLT_DATA0/FDB_TBL_RD_OP_RSLT_DATA1/FDB_TBL_RD_OP_RSLT_DATA2
+ */
+sw_error_t
+_adpt_hppe_fdb_tbl_rd_op_rslt_data_reg_get(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+	a_uint32_t rslt_data[3];
+	a_uint32_t entry_valid, lookup_valid;
+	a_uint32_t i, dst_info_encode;
+
+	hppe_fdb_tbl_rd_op_rslt_data0_data_get(dev_id, &rslt_data[0]);
+	hppe_fdb_tbl_rd_op_rslt_data1_data_get(dev_id, &rslt_data[1]);
+	hppe_fdb_tbl_rd_op_rslt_data2_data_get(dev_id, &rslt_data[2]);
+
+	entry_valid = (rslt_data[1] >> (FDB_TBL_ENTRY_VALID_OFFSET - 32)) & 0x1;
+	lookup_valid = (rslt_data[1] >> (FDB_TBL_LOOKUP_VALID_OFFSET - 32)) & 0x1;
+	dst_info_encode = (rslt_data[2] >> (FDB_TBL_DST_INFO_OFFSET + 12 -64)) & 0x3;
+
+	if (entry_valid == 0x0 || dst_info_encode == 0x0)
+	{
+		return SW_NOT_FOUND;
+	}
+	else
+	{
+		entry->entry_valid = A_TRUE;
+		if (lookup_valid == 0x1)
+			entry->lookup_valid = A_TRUE;
+		else
+			entry->lookup_valid = A_FALSE;
+		entry->fid = (rslt_data[1] >> (FDB_TBL_VSI_OFFSET - 32)) & 0x1f;
+		entry->sacmd = (rslt_data[2] >> (FDB_TBL_SA_CMD_OFFSET - 64)) & 0x3;
+		entry->dacmd = (rslt_data[2] >> (FDB_TBL_DA_CMD_OFFSET - 64)) & 0x3;
+		if (((rslt_data[2] >> (FDB_TBL_HIT_AGE_OFFSET - 64)) & 0x3) == 0x3)
+			entry->static_en = A_TRUE;
+		else
+			entry->static_en = A_FALSE;
+		if (dst_info_encode == 0x2)
+		{
+			entry->portmap_en = A_FALSE;
+			entry->port.id = ((rslt_data[2] & 0x7) << 9) + ((rslt_data[1] >> (FDB_TBL_DST_INFO_OFFSET - 32)) & 0x1ff);
+		}
+		else
+		{
+			entry->portmap_en = A_TRUE;
+			entry->port.map = ((rslt_data[2] & 0x7) << 9) + ((rslt_data[1] >> (FDB_TBL_DST_INFO_OFFSET - 32)) & 0x1ff);
+		}
+		for (i = 2; i < 6; i++)
+			entry->addr.uc[i] = (rslt_data[0] >> ((5 - i) << 3)) & 0xff;
+		for (i = 0; i < 2; i++)
+			entry->addr.uc[i] = (rslt_data[1] >> ((1 - i) << 3)) & 0xff;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+_get_fdb_table_entryindex_by_entry(a_uint32_t dev_id, fal_fdb_entry_t * entry,
+		a_uint32_t *entry_index, a_uint32_t cmd_id)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t init_entry_index = 0;
+	fal_fdb_entry_t temp_entry;
+
+	aos_lock_bh(&hppe_fdb_lock);
+	rv = _adpt_hppe_fdb_tbl_rd_op_data_reg_set(dev_id, entry);
+	if (rv != SW_OK)
+	{
+		aos_unlock_bh(&hppe_fdb_lock);
+		return rv;
+	}
+
+	rv = _adpt_hppe_fdb_tbl_rd_op_reg_set(dev_id, cmd_id, OP_MODE_HASH, init_entry_index);
+	if (rv != SW_OK)
+	{
+		aos_unlock_bh(&hppe_fdb_lock);
+		return rv;
+	}
+
+	rv = _adpt_hppe_fdb_tbl_rd_op_rslt_data_reg_get(dev_id, &temp_entry);
+
+	rv = _adpt_hppe_fdb_tbl_rd_op_rslt_reg_get(dev_id, cmd_id, entry_index);
+	if (rv != SW_OK)
+	{
+		aos_unlock_bh(&hppe_fdb_lock);
+		return rv;
+	}
+
+	aos_unlock_bh(&hppe_fdb_lock);
+
+	if (*entry_index == 0)
+	{
+		if (!(temp_entry.addr.uc[0] == entry->addr.uc[0] && temp_entry.addr.uc[1] == entry->addr.uc[1] &&
+			temp_entry.addr.uc[2] == entry->addr.uc[2] && temp_entry.addr.uc[3] == entry->addr.uc[3] &&
+			temp_entry.addr.uc[4] == entry->addr.uc[4] && temp_entry.addr.uc[5] == entry->addr.uc[5] &&
+			temp_entry.fid == entry->fid))
+			return SW_NOT_FOUND;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+_get_fdb_table_entry_by_entryindex(a_uint32_t dev_id, fal_fdb_entry_t * entry,
+		a_uint32_t entry_index, a_uint32_t cmd_id)
+{
+	sw_error_t rv = SW_OK, rv1 = SW_OK;
+	fal_fdb_entry_t init_entry;
+	a_uint32_t rslt_entry_index = 0;
+
+	aos_mem_zero(&init_entry, sizeof (fal_fdb_entry_t));
+
+	aos_lock_bh(&hppe_fdb_lock);
+	rv = _adpt_hppe_fdb_tbl_rd_op_data_reg_set(dev_id, &init_entry);
+	if (rv != SW_OK)
+	{
+		aos_unlock_bh(&hppe_fdb_lock);
+		return rv;
+	}
+
+	rv = _adpt_hppe_fdb_tbl_rd_op_reg_set(dev_id, cmd_id, OP_MODE_INDEX, entry_index);
+	if (rv != SW_OK)
+	{
+		aos_unlock_bh(&hppe_fdb_lock);
+		return rv;
+	}
+
+	rv = _adpt_hppe_fdb_tbl_rd_op_rslt_data_reg_get(dev_id, entry);
+	if (rv != SW_OK && rv != SW_NOT_FOUND)
+	{
+		aos_unlock_bh(&hppe_fdb_lock);
+		return rv;
+	}
+	else
+		rv1 = rv;
+
+	rv = _adpt_hppe_fdb_tbl_rd_op_rslt_reg_get(dev_id, cmd_id, &rslt_entry_index);
+	if (rv != SW_OK)
+	{
+		aos_unlock_bh(&hppe_fdb_lock);
+		return rv;
+	}
+
+	aos_unlock_bh(&hppe_fdb_lock);
+
+	return rv1;
+}
+
+sw_error_t
+_modify_fdb_table_entry(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op_type,
+	a_uint32_t cmd_id)
+{
+	sw_error_t rv = SW_OK;
+	fal_fdb_entry_t temp_entry;
+
+	aos_lock_bh(&hppe_fdb_lock);
+	rv = _adpt_hppe_fdb_tbl_op_data_reg_set(dev_id, entry);
+	if (rv != SW_OK)
+	{
+		aos_unlock_bh(&hppe_fdb_lock);
+		return rv;
+	}
+
+	rv = _adpt_hppe_fdb_tbl_op_reg_set(dev_id, cmd_id, op_type);
+	if (rv != SW_OK)
+	{
+		aos_unlock_bh(&hppe_fdb_lock);
+		return rv;
+	}
+
+	rv = _adpt_hppe_fdb_tbl_rd_op_rslt_data_reg_get(dev_id, &temp_entry);
+
+	rv = _adpt_hppe_fdb_tbl_op_rslt_reg_get(dev_id, cmd_id);
+	if (rv != SW_OK)
+	{
+		aos_unlock_bh(&hppe_fdb_lock);
+		return rv;
+	}
+
+	aos_unlock_bh(&hppe_fdb_lock);
+
+	return SW_OK;
+}
+
+sw_error_t
+_adpt_hppe_fdb_extend_first_next(a_uint32_t dev_id, fal_fdb_entry_t * entry, fal_fdb_op_t * option, a_uint32_t hwop)
+{
+	sw_error_t rv;
+	a_uint32_t cmd_id = 0x0;
+	a_uint32_t entry_index = 0x0;
+	fal_fdb_entry_t ori_entry;
+
+	aos_mem_zero(&ori_entry, sizeof (fal_fdb_entry_t));
+
+	if (hwop == ARL_EXTENDFIRST_ENTRY || hwop == ARL_EXTENDNEXT_ENTRY)
+	{
+		ori_entry.portmap_en = entry->portmap_en;
+		ori_entry.port.id = entry->port.id;
+		ori_entry.fid = entry->fid;
+	}
+
+	if (hwop == ARL_FIRST_ENTRY || hwop == ARL_EXTENDFIRST_ENTRY)
+		aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+	rv = _get_fdb_table_entryindex_by_entry(dev_id, entry, &entry_index, cmd_id);
+	if (rv != SW_OK && rv != SW_NOT_FOUND)
+		return rv;
+
+	if (rv != SW_NOT_FOUND)
+		entry_index += 1;
+
+	for (; entry_index < FDB_TBL_NUM; entry_index++)
+	{
+		cmd_id = entry_index % OP_CMD_ID_SIZE;
+		rv = _get_fdb_table_entry_by_entryindex(dev_id, entry, entry_index, cmd_id);
+		if (rv == SW_NOT_FOUND)
+			continue;
+		else if (rv == SW_OK)
+		{
+			if (hwop == ARL_EXTENDFIRST_ENTRY || hwop == ARL_EXTENDNEXT_ENTRY)
+			{
+				if (option->fid_en == A_TRUE && ori_entry.fid != entry->fid)
+					continue;
+				if (option->port_en == A_TRUE && !(ori_entry.portmap_en == entry->portmap_en &&
+					ori_entry.port.id == entry->port.id))
+					continue;
+			}
+			break;
+		}
+		else
+			return rv;
+	}
+
+	if (entry_index == FDB_TBL_NUM)
+		return SW_NO_MORE;
+	return SW_OK;
+}
+
+void _fdb_copy(fal_fdb_entry_t *new, const fal_fdb_entry_t *old)
+{
+	a_uint32_t i;
+
+	aos_mem_zero(new, sizeof (fal_fdb_entry_t));
+
+	for (i = 0; i < 6; i++)
+		new->addr.uc[i] = old->addr.uc[i];
+
+	new->fid = old->fid;
+	new->dacmd = old->dacmd;
+	new->sacmd = old->sacmd;
+	new->port.id = old->port.id;
+	new->portmap_en = old->portmap_en;
+	new->is_multicast = old->is_multicast;
+	new->static_en = old->static_en;
+
+}
+
+sw_error_t
+adpt_hppe_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+	fal_fdb_op_t option;
+	sw_error_t rv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	aos_mem_zero(&option, sizeof (fal_fdb_op_t));
+
+	_remove_port_type(&entry->port.id);
+	rv = _adpt_hppe_fdb_extend_first_next(dev_id, entry, &option, ARL_FIRST_ENTRY);
+	_add_port_type(entry->portmap_en, &entry->port.id);
+
+	return rv;
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+adpt_hppe_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+	fal_fdb_op_t option;
+	sw_error_t rv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	aos_mem_zero(&option, sizeof (fal_fdb_op_t));
+
+	_remove_port_type(&entry->port.id);
+	rv = _adpt_hppe_fdb_extend_first_next(dev_id, entry, &option, ARL_NEXT_ENTRY);
+	_add_port_type(entry->portmap_en, &entry->port.id);
+
+	return rv;
+}
+#endif
+sw_error_t
+adpt_hppe_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+	sw_error_t rv = SW_OK;
+	fal_fdb_entry_t entry_temp;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	_fdb_copy(&entry_temp, entry);
+
+	_remove_port_type(&entry_temp.port.id);
+	rv = _modify_fdb_table_entry(dev_id, &entry_temp, OP_TYPE_ADD, 0x0);
+	_add_port_type(entry_temp.portmap_en, &entry_temp.port.id);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t *entry)
+{
+	sw_error_t rv = SW_OK;
+	fal_fdb_entry_t entry_temp;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	_fdb_copy(&entry_temp, entry);
+	_remove_port_type(&entry_temp.port.id);
+	rv = _modify_fdb_table_entry(dev_id, &entry_temp, OP_TYPE_DEL, 0x0);
+	_add_port_type(entry_temp.portmap_en, &entry_temp.port.id);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag)
+{
+	a_uint32_t entry_index, id, cmd_id = 0;
+	sw_error_t rv = SW_OK;
+	fal_fdb_entry_t entry;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	_remove_port_type(&port_id);
+
+	for (entry_index = 0; entry_index < FDB_TBL_NUM; entry_index++)
+	{
+		cmd_id = entry_index % OP_CMD_ID_SIZE;
+		aos_mem_zero(&entry, sizeof (fal_fdb_entry_t));
+		rv = _get_fdb_table_entry_by_entryindex(dev_id, &entry, entry_index, cmd_id);
+
+		if (rv == SW_NOT_FOUND)
+			continue;
+		else if (rv == SW_OK)
+		{
+			if (entry.portmap_en == A_TRUE)
+			{
+				if (((entry.port.map >> port_id) & 0x1) == 1)
+				{
+					if ((!flag && entry.static_en == A_FALSE) || (flag & FAL_FDB_DEL_STATIC))
+					{
+						id = entry.port.map & (~(0x1 << port_id));
+						if (id == 0)
+						{
+							rv = _modify_fdb_table_entry(dev_id, &entry, OP_TYPE_DEL, 0x0);
+							if (rv != SW_OK)
+								return rv;
+						}
+						else
+						{
+							entry.port.map &= (~(0x1 << port_id));
+							rv = adpt_hppe_fdb_add(dev_id, &entry);
+							if (rv != SW_OK)
+								return rv;
+						}
+					}
+				}
+			}
+			else
+			{
+				if (entry.port.id == port_id &&
+					((!flag && entry.static_en == A_FALSE) || (flag & FAL_FDB_DEL_STATIC)))
+				{
+					rv = _modify_fdb_table_entry(dev_id, &entry, OP_TYPE_DEL, 0x0);
+					if (rv != SW_OK)
+						return rv;
+				}
+			}
+		}
+		else
+			return rv;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+	sw_error_t rv;
+	fal_fdb_entry_t entry;
+	a_uint32_t entry_index = 0, cmd_id;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (FAL_FDB_DEL_STATIC & flag)
+	{
+		aos_mem_zero(&entry, sizeof (fal_fdb_entry_t));
+		return _modify_fdb_table_entry(dev_id, &entry, OP_TYPE_FLUSH, 0x0);
+	}
+	else
+	{
+		for (entry_index = 0; entry_index < FDB_TBL_NUM; entry_index++)
+		{
+			cmd_id = entry_index % OP_CMD_ID_SIZE;
+			aos_mem_zero(&entry, sizeof (fal_fdb_entry_t));
+			rv = _get_fdb_table_entry_by_entryindex(dev_id, &entry, entry_index, cmd_id);
+			if (rv != SW_OK && rv != SW_NOT_FOUND)
+				return rv;
+
+			if (entry.static_en == A_FALSE)
+			{
+				rv = _modify_fdb_table_entry(dev_id, &entry, OP_TYPE_DEL, 0x0);
+				if (rv != SW_OK)
+					return rv;
+			}
+		}
+	}
+
+	return SW_OK;
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+adpt_hppe_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+                     a_uint32_t fid, fal_fdb_op_t * option)
+{
+	a_uint32_t entry_index, cmd_id = 0;
+	sw_error_t rv = SW_OK;
+	fal_fdb_entry_t entry;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(option);
+
+	if (option->port_en == A_TRUE)
+		return SW_NOT_SUPPORTED;
+
+	_remove_port_type(&old_port);
+	_remove_port_type(&new_port);
+
+	for (entry_index = 0; entry_index < FDB_TBL_NUM; entry_index++)
+	{
+		cmd_id = entry_index % OP_CMD_ID_SIZE;
+		aos_mem_zero(&entry, sizeof (fal_fdb_entry_t));
+		rv = _get_fdb_table_entry_by_entryindex(dev_id, &entry, entry_index, cmd_id);
+
+		if (rv == SW_NOT_FOUND)
+			continue;
+		else if (rv == SW_OK)
+		{
+			if (option->fid_en == A_TRUE && entry.fid != fid)
+				continue;
+			if (entry.portmap_en == A_TRUE)
+			{
+				if (((entry.port.map >> old_port) & 0x1) == 1)
+				{
+					entry.port.map &= (~(0x1 << old_port));
+					entry.port.map |= (0x1 << new_port);
+					rv = adpt_hppe_fdb_add(dev_id, &entry);
+					if (rv != SW_OK)
+						return rv;
+				}
+			}
+			else
+			{
+				if (entry.port.id == old_port)
+				{
+					entry.port.id = new_port;
+					rv = adpt_hppe_fdb_add(dev_id, &entry);
+					if (rv != SW_OK)
+						return rv;
+				}
+			}
+		}
+		else
+			return rv;
+	}
+
+	return SW_OK;
+}
+#endif
+sw_error_t
+adpt_hppe_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+	sw_error_t rv;
+	a_uint32_t cmd_id = 0x0;
+	a_uint32_t entry_index = 0x0;
+
+	_remove_port_type(&entry->port.id);
+	rv = _get_fdb_table_entryindex_by_entry(dev_id, entry, &entry_index, cmd_id);
+	if (rv != SW_OK)
+		return rv;
+
+	cmd_id = entry_index % OP_CMD_ID_SIZE;
+
+	rv = _get_fdb_table_entry_by_entryindex(dev_id, entry, entry_index, cmd_id);
+	_add_port_type(entry->portmap_en, &entry->port.id);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry)
+{
+	sw_error_t rv;
+	a_uint32_t cmd_id = 0x0;
+	a_uint32_t entry_index = 0x0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(iterator);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	_remove_port_type(&entry->port.id);
+	for (entry_index = *iterator; entry_index < FDB_TBL_NUM; entry_index++)
+	{
+		cmd_id = entry_index % OP_CMD_ID_SIZE;
+		rv = _get_fdb_table_entry_by_entryindex(dev_id, entry, entry_index, cmd_id);
+		if (rv == SW_NOT_FOUND)
+			continue;
+		else if (rv == SW_OK)
+			break;
+		else
+			return rv;
+	}
+
+	if (entry_index == FDB_TBL_NUM)
+		return SW_NO_MORE;
+
+	_add_port_type(entry->portmap_en, &entry->port.id);
+	*iterator = entry_index + 1;
+	return SW_OK;
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+adpt_hppe_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+	union age_timer_u age_timer = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time);
+
+	if (*time < 1 || *time > 1048575)
+		return SW_BAD_PARAM;
+
+	age_timer.bf.age_val = *time;
+
+	return hppe_age_timer_set(dev_id, &age_timer);
+}
+
+sw_error_t
+adpt_hppe_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+	sw_error_t rv = SW_OK;
+	union age_timer_u age_timer = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time);
+
+	rv = hppe_age_timer_get(dev_id, &age_timer);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*time = age_timer.bf.age_val;
+
+	return SW_OK;
+}
+#endif
+sw_error_t
+adpt_hppe_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+                         fal_fdb_entry_t * entry)
+{
+	sw_error_t rv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(option);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	_remove_port_type(&entry->port.id);
+	rv = _adpt_hppe_fdb_extend_first_next(dev_id, entry, option, ARL_EXTENDFIRST_ENTRY);
+	_add_port_type(entry->portmap_en, &entry->port.id);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option,
+                        fal_fdb_entry_t * entry)
+{
+	sw_error_t rv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(option);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	_remove_port_type(&entry->port.id);
+	rv = _adpt_hppe_fdb_extend_first_next(dev_id, entry, option, ARL_EXTENDNEXT_ENTRY);
+	_add_port_type(entry->portmap_en, &entry->port.id);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_fdb_learn_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union l2_global_conf_u l2_global_conf = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_l2_global_conf_get(dev_id, &l2_global_conf);
+
+	if( rv != SW_OK )
+		return rv;
+
+	l2_global_conf.bf.lrn_en = enable;
+
+	return hppe_l2_global_conf_set(dev_id, &l2_global_conf);
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+adpt_hppe_fdb_learn_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+	union l2_global_conf_u l2_global_conf = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+
+	rv = hppe_l2_global_conf_get(dev_id, &l2_global_conf);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*enable = l2_global_conf.bf.lrn_en;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_fdb_port_maclimit_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl)
+{
+	sw_error_t rv = SW_OK;
+	union port_lrn_limit_ctrl_u port_lrn_limit_ctrl = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_port_lrn_limit_ctrl_get(dev_id, port_id, &port_lrn_limit_ctrl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	port_lrn_limit_ctrl.bf.lrn_lmt_en = maclimit_ctrl->enable;
+	port_lrn_limit_ctrl.bf.lrn_lmt_cnt = maclimit_ctrl->limit_num;
+	port_lrn_limit_ctrl.bf.lrn_lmt_exceed_fwd = maclimit_ctrl->action;
+
+	return hppe_port_lrn_limit_ctrl_set(dev_id, port_id, &port_lrn_limit_ctrl);
+}
+
+sw_error_t
+adpt_hppe_fdb_port_maclimit_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl)
+{
+	sw_error_t rv = SW_OK;
+	union port_lrn_limit_ctrl_u port_lrn_limit_ctrl = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(maclimit_ctrl);
+
+	rv = hppe_port_lrn_limit_ctrl_get(dev_id, port_id, &port_lrn_limit_ctrl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	maclimit_ctrl->enable = port_lrn_limit_ctrl.bf.lrn_lmt_en;
+	maclimit_ctrl->limit_num = port_lrn_limit_ctrl.bf.lrn_lmt_cnt;
+	maclimit_ctrl->action = port_lrn_limit_ctrl.bf.lrn_lmt_exceed_fwd;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable, a_uint32_t cnt)
+{
+	sw_error_t rv = SW_OK;
+	fal_maclimit_ctrl_t maclimit_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = adpt_hppe_fdb_port_maclimit_ctrl_get(dev_id, port_id, &maclimit_ctrl);
+	if( rv != SW_OK )
+		return rv;
+
+	maclimit_ctrl.enable = enable;
+	maclimit_ctrl.limit_num = cnt;
+
+	return adpt_hppe_fdb_port_maclimit_ctrl_set(dev_id, port_id, &maclimit_ctrl);
+}
+
+sw_error_t
+adpt_hppe_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable, a_uint32_t * cnt)
+{
+	sw_error_t rv = SW_OK;
+	fal_maclimit_ctrl_t maclimit_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+	ADPT_NULL_POINT_CHECK(cnt);
+
+	rv = adpt_hppe_fdb_port_maclimit_ctrl_get(dev_id, port_id, &maclimit_ctrl);
+	if( rv != SW_OK )
+		return rv;
+
+	*enable = maclimit_ctrl.enable;
+	*cnt = maclimit_ctrl.limit_num;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+	sw_error_t rv = SW_OK;
+	fal_fdb_entry_t entry;
+	int i, cmd_id = 0x0, entry_index = 0x0, id;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(addr);
+
+	_remove_port_type(&port_id);
+
+	aos_mem_zero(&entry, sizeof (fal_fdb_entry_t));
+
+	entry.fid = fid;
+	for (i = 0; i < 6; i++)
+		entry.addr.uc[i] = addr->uc[i];
+
+	rv = _get_fdb_table_entryindex_by_entry(dev_id, &entry, &entry_index, cmd_id);
+	if (rv != SW_OK)
+		return rv;
+
+	cmd_id = entry_index % OP_CMD_ID_SIZE;
+	rv = _get_fdb_table_entry_by_entryindex(dev_id, &entry, entry_index, cmd_id);
+	if (rv != SW_OK)
+		return rv;
+
+	if (entry.portmap_en == A_TRUE)
+	{
+		if (port_id >= 12)
+			return SW_FAIL;
+		entry.port.map |= (0x1 << port_id);
+	}
+	else
+	{
+		if (port_id >= 12 || entry.port.id >= 12)
+			return SW_FAIL;
+		entry.portmap_en = A_TRUE;
+		id = entry.port.id;
+		entry.port.map = 0;
+		entry.port.map |= (0x1 << id);
+		entry.port.map |= (0x1 << port_id);
+	}
+
+	return adpt_hppe_fdb_add(dev_id, &entry);
+}
+
+sw_error_t
+adpt_hppe_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+	sw_error_t rv = SW_OK;
+	fal_fdb_entry_t entry;
+	int i, cmd_id = 0x0, entry_index = 0x0, id;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(addr);
+
+	_remove_port_type(&port_id);
+
+	aos_mem_zero(&entry, sizeof (fal_fdb_entry_t));
+
+	entry.fid = fid;
+	for (i = 0; i < 6; i++)
+		entry.addr.uc[i] = addr->uc[i];
+
+	rv = _get_fdb_table_entryindex_by_entry(dev_id, &entry, &entry_index, cmd_id);
+	if (rv != SW_OK)
+		return rv;
+
+	cmd_id = entry_index % OP_CMD_ID_SIZE;
+	rv = _get_fdb_table_entry_by_entryindex(dev_id, &entry, entry_index, cmd_id);
+	if (rv != SW_OK)
+		return rv;
+
+	if (entry.portmap_en == A_TRUE)
+	{
+		if (((entry.port.map >> port_id) & 0x1) == 1)
+		{
+			id = entry.port.map & (~(0x1 << port_id));
+			if (id == 0)
+			{
+				rv = _modify_fdb_table_entry(dev_id, &entry, OP_TYPE_DEL, 0x0);
+			}
+			else
+			{
+				entry.port.map &= (~(0x1 << port_id));
+				rv = adpt_hppe_fdb_add(dev_id, &entry);
+			}
+		}
+	}
+	else
+	{
+		if (entry.port.id == port_id)
+			rv = _modify_fdb_table_entry(dev_id, &entry, OP_TYPE_DEL, 0x0);
+	}
+
+	return rv;
+}
+#endif
+sw_error_t
+adpt_hppe_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union port_bridge_ctrl_u port_bridge_ctrl = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	port_bridge_ctrl.bf.new_addr_lrn_en = enable;
+	port_bridge_ctrl.bf.station_move_lrn_en = enable;
+
+	return hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl);
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+adpt_hppe_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	union port_bridge_ctrl_u port_bridge_ctrl = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*enable = port_bridge_ctrl.bf.new_addr_lrn_en;
+
+	return SW_OK;
+}
+#endif
+sw_error_t
+adpt_hppe_fdb_port_newaddr_lrn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd)
+{
+	sw_error_t rv = SW_OK;
+	union port_bridge_ctrl_u port_bridge_ctrl;
+
+	memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	port_bridge_ctrl.bf.new_addr_lrn_en = enable;
+	port_bridge_ctrl.bf.new_addr_fwd_cmd = cmd;
+
+	return hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl);
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+adpt_hppe_fdb_port_newaddr_lrn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd)
+{
+	sw_error_t rv = SW_OK;
+	union port_bridge_ctrl_u port_bridge_ctrl;
+
+	memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+	ADPT_NULL_POINT_CHECK(cmd);
+
+	rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*enable = port_bridge_ctrl.bf.new_addr_lrn_en;
+	*cmd = port_bridge_ctrl.bf.new_addr_fwd_cmd;
+
+	return SW_OK;
+}
+#endif
+sw_error_t
+adpt_hppe_fdb_port_stamove_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd)
+{
+	sw_error_t rv = SW_OK;
+	union port_bridge_ctrl_u port_bridge_ctrl;
+
+	memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	port_bridge_ctrl.bf.station_move_lrn_en = enable;
+	port_bridge_ctrl.bf.station_move_fwd_cmd = cmd;
+
+	return hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl);
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+adpt_hppe_fdb_port_stamove_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd)
+{
+	sw_error_t rv = SW_OK;
+	union port_bridge_ctrl_u port_bridge_ctrl;
+
+	memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+	ADPT_NULL_POINT_CHECK(cmd);
+
+	rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*enable = port_bridge_ctrl.bf.station_move_lrn_en;
+	*cmd = port_bridge_ctrl.bf.station_move_fwd_cmd;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_fdb_learn_counter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t * cnt)
+{
+	sw_error_t rv = SW_OK;
+	union port_lrn_limit_counter_u port_lrn_limit_counter = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cnt);
+
+	rv = hppe_port_lrn_limit_counter_get(dev_id, port_id, &port_lrn_limit_counter);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*cnt = port_lrn_limit_counter.bf.lrn_cnt;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                      fal_fwd_cmd_t cmd)
+{
+	sw_error_t rv = SW_OK;
+	fal_maclimit_ctrl_t maclimit_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = adpt_hppe_fdb_port_maclimit_ctrl_get(dev_id, port_id, &maclimit_ctrl);
+	if( rv != SW_OK )
+		return rv;
+
+	maclimit_ctrl.action = cmd;
+
+	return adpt_hppe_fdb_port_maclimit_ctrl_set(dev_id, port_id, &maclimit_ctrl);
+}
+
+sw_error_t
+adpt_hppe_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                      fal_fwd_cmd_t * cmd)
+{
+	sw_error_t rv = SW_OK;
+	fal_maclimit_ctrl_t maclimit_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cmd);
+
+	rv = adpt_hppe_fdb_port_maclimit_ctrl_get(dev_id, port_id, &maclimit_ctrl);
+	if( rv != SW_OK )
+		return rv;
+
+	*cmd = maclimit_ctrl.action;
+
+	return SW_OK;
+}
+#endif
+sw_error_t
+adpt_hppe_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union l2_global_conf_u l2_global_conf = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_l2_global_conf_get(dev_id, &l2_global_conf);
+
+	if( rv != SW_OK )
+		return rv;
+
+	l2_global_conf.bf.age_en = enable;
+
+	return hppe_l2_global_conf_set(dev_id, &l2_global_conf);
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+adpt_hppe_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+	union l2_global_conf_u l2_global_conf = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	rv = hppe_l2_global_conf_get(dev_id, &l2_global_conf);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*enable = l2_global_conf.bf.age_en;
+
+	return SW_OK;
+}
+#endif
+sw_error_t
+adpt_hppe_fdb_del_by_fid(a_uint32_t dev_id, a_uint16_t fid, a_uint32_t flag)
+{
+	a_uint32_t entry_index, cmd_id = 0;
+	sw_error_t rv = SW_OK;
+	fal_fdb_entry_t entry;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	for (entry_index = 0; entry_index < FDB_TBL_NUM; entry_index++)
+	{
+		cmd_id = entry_index % OP_CMD_ID_SIZE;
+		aos_mem_zero(&entry, sizeof (fal_fdb_entry_t));
+		rv = _get_fdb_table_entry_by_entryindex(dev_id, &entry, entry_index, cmd_id);
+
+		if (rv == SW_NOT_FOUND)
+		{
+			continue;
+		}
+		else if (rv == SW_OK)
+		{
+			if (entry.fid == fid &&
+				((!flag && entry.static_en == A_FALSE) || (flag & FAL_FDB_DEL_STATIC)))
+			{
+				rv = _modify_fdb_table_entry(dev_id, &entry, OP_TYPE_DEL, 0x0);
+				if (rv != SW_OK)
+				{
+					return rv;
+				}
+			}
+		}
+		else
+		{
+			return rv;
+		}
+	}
+
+	return SW_OK;
+}
+
+void adpt_hppe_fdb_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_fdb_func_bitmap[0] = ((1 << FUNC_FDB_ENTRY_ADD) |
+						(1 << FUNC_FDB_ENTRY_FLUSH) |
+						(1 << FUNC_FDB_ENTRY_DEL_BYPORT) |
+						(1 << FUNC_FDB_ENTRY_DEL_BYMAC) |
+						(1 << FUNC_FDB_ENTRY_GETFIRST) |
+						(1 << FUNC_FDB_ENTRY_GETNEXT) |
+						(1 << FUNC_FDB_ENTRY_SEARCH) |
+						(1 << FUNC_FDB_PORT_LEARN_SET) |
+						(1 << FUNC_FDB_PORT_LEARN_GET) |
+						(1 << FUNC_FDB_PORT_LEARNING_CTRL_SET) |
+						(1 << FUNC_FDB_PORT_LEARNING_CTRL_GET) |
+						(1 << FUNC_FDB_PORT_STAMOVE_CTRL_SET) |
+						(1 << FUNC_FDB_PORT_STAMOVE_CTRL_GET) |
+						(1 << FUNC_FDB_AGING_CTRL_SET) |
+						(1 << FUNC_FDB_AGING_CTRL_GET) |
+						(1 << FUNC_FDB_LEARNING_CTRL_SET) |
+						(1 << FUNC_FDB_LEARNING_CTRL_GET) |
+						(1 << FUNC_FDB_AGING_TIME_SET) |
+						(1 << FUNC_FDB_AGING_TIME_GET) |
+						(1 << FUNC_FDB_ENTRY_GETNEXT_BYINDEX) |
+						(1 << FUNC_FDB_ENTRY_EXTEND_GETNEXT) |
+						(1 << FUNC_FDB_ENTRY_EXTEND_GETFIRST) |
+						(1 << FUNC_FDB_ENTRY_UPDATE_BYPORT) |
+						(1 << FUNC_PORT_FDB_LEARN_LIMIT_SET) |
+						(1 << FUNC_PORT_FDB_LEARN_LIMIT_GET) |
+						(1 << FUNC_PORT_FDB_LEARN_EXCEED_CMD_SET) |
+						(1 << FUNC_PORT_FDB_LEARN_EXCEED_CMD_GET) |
+						(1 << FUNC_FDB_PORT_LEARNED_MAC_COUNTER_GET) |
+						(1 << FUNC_FDB_PORT_ADD) |
+						(1 << FUNC_FDB_PORT_DEL) |
+						(1 << FUNC_FDB_PORT_MACLIMIT_CTRL_SET) |
+						(1 << FUNC_FDB_PORT_MACLIMIT_CTRL_GET));
+	p_adpt_api->adpt_fdb_func_bitmap[1] = ((1 << (FUNC_FDB_DEL_BY_FID % 32)));
+
+	return;
+}
+
+static void adpt_hppe_fdb_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_fdb_first = NULL;
+	p_adpt_api->adpt_fdb_next = NULL;
+	p_adpt_api->adpt_fdb_add = NULL;
+	p_adpt_api->adpt_fdb_del_by_port = NULL;
+	p_adpt_api->adpt_fdb_del_by_mac = NULL;
+	p_adpt_api->adpt_fdb_del_all = NULL;
+	p_adpt_api->adpt_fdb_transfer = NULL;
+	p_adpt_api->adpt_fdb_find = NULL;
+	p_adpt_api->adpt_fdb_iterate = NULL;
+	p_adpt_api->adpt_fdb_age_time_set = NULL;
+	p_adpt_api->adpt_fdb_age_time_get = NULL;
+	p_adpt_api->adpt_fdb_extend_first = NULL;
+	p_adpt_api->adpt_fdb_extend_next = NULL;
+	p_adpt_api->adpt_fdb_learn_ctrl_set = NULL;
+	p_adpt_api->adpt_fdb_learn_ctrl_get = NULL;
+	p_adpt_api->adpt_port_fdb_learn_limit_set = NULL;
+	p_adpt_api->adpt_port_fdb_learn_limit_get = NULL;
+	p_adpt_api->adpt_fdb_port_add = NULL;
+	p_adpt_api->adpt_fdb_port_del = NULL;
+	p_adpt_api->adpt_fdb_port_learn_set = NULL;
+	p_adpt_api->adpt_fdb_port_learn_get = NULL;
+	p_adpt_api->adpt_fdb_port_newaddr_lrn_set = NULL;
+	p_adpt_api->adpt_fdb_port_newaddr_lrn_get = NULL;
+	p_adpt_api->adpt_fdb_port_stamove_set = NULL;
+	p_adpt_api->adpt_fdb_port_stamove_get = NULL;
+	p_adpt_api->adpt_port_fdb_learn_counter_get = NULL;
+	p_adpt_api->adpt_port_fdb_learn_exceed_cmd_set = NULL;
+	p_adpt_api->adpt_port_fdb_learn_exceed_cmd_get = NULL;
+	p_adpt_api->adpt_fdb_age_ctrl_set = NULL;
+	p_adpt_api->adpt_fdb_age_ctrl_get = NULL;
+	p_adpt_api->adpt_fdb_port_maclimit_ctrl_set = NULL;
+	p_adpt_api->adpt_fdb_port_maclimit_ctrl_get = NULL;
+	p_adpt_api->adpt_fdb_del_by_fid = NULL;
+
+	return;
+}
+
+sw_error_t adpt_hppe_fdb_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_fdb_func_unregister(dev_id, p_adpt_api);
+
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_GETFIRST))
+		p_adpt_api->adpt_fdb_first = adpt_hppe_fdb_first;
+#ifndef IN_FDB_MINI
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_GETNEXT))
+		p_adpt_api->adpt_fdb_next = adpt_hppe_fdb_next;
+#endif
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_ADD))
+		p_adpt_api->adpt_fdb_add = adpt_hppe_fdb_add;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_DEL_BYPORT))
+		p_adpt_api->adpt_fdb_del_by_port = adpt_hppe_fdb_del_by_port;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_DEL_BYMAC))
+		p_adpt_api->adpt_fdb_del_by_mac = adpt_hppe_fdb_del_by_mac;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_FLUSH))
+		p_adpt_api->adpt_fdb_del_all = adpt_hppe_fdb_del_all;
+#ifndef IN_FDB_MINI
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_UPDATE_BYPORT))
+		p_adpt_api->adpt_fdb_transfer = adpt_hppe_fdb_transfer;
+#endif
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_SEARCH))
+		p_adpt_api->adpt_fdb_find = adpt_hppe_fdb_find;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_GETNEXT_BYINDEX))
+		p_adpt_api->adpt_fdb_iterate = adpt_hppe_fdb_iterate;
+#ifndef IN_FDB_MINI
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_AGING_TIME_SET))
+		p_adpt_api->adpt_fdb_age_time_set = adpt_hppe_fdb_age_time_set;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_AGING_TIME_GET))
+		p_adpt_api->adpt_fdb_age_time_get = adpt_hppe_fdb_age_time_get;
+#endif
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_EXTEND_GETFIRST))
+		p_adpt_api->adpt_fdb_extend_first = adpt_hppe_fdb_extend_first;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_EXTEND_GETNEXT))
+		p_adpt_api->adpt_fdb_extend_next = adpt_hppe_fdb_extend_next;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_LEARNING_CTRL_SET))
+		p_adpt_api->adpt_fdb_learn_ctrl_set = adpt_hppe_fdb_learn_ctrl_set;
+#ifndef IN_FDB_MINI
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_LEARNING_CTRL_GET))
+		p_adpt_api->adpt_fdb_learn_ctrl_get = adpt_hppe_fdb_learn_ctrl_get;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_PORT_FDB_LEARN_LIMIT_SET))
+		p_adpt_api->adpt_port_fdb_learn_limit_set = adpt_hppe_port_fdb_learn_limit_set;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_PORT_FDB_LEARN_LIMIT_GET))
+		p_adpt_api->adpt_port_fdb_learn_limit_get = adpt_hppe_port_fdb_learn_limit_get;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_ADD))
+		p_adpt_api->adpt_fdb_port_add = adpt_hppe_fdb_port_add;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_DEL))
+		p_adpt_api->adpt_fdb_port_del = adpt_hppe_fdb_port_del;
+#endif
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_LEARN_SET))
+		p_adpt_api->adpt_fdb_port_learn_set = adpt_hppe_fdb_port_learn_set;
+#ifndef IN_FDB_MINI
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_LEARN_GET))
+		p_adpt_api->adpt_fdb_port_learn_get = adpt_hppe_fdb_port_learn_get;
+#endif
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_LEARNING_CTRL_SET))
+		p_adpt_api->adpt_fdb_port_newaddr_lrn_set = adpt_hppe_fdb_port_newaddr_lrn_set;
+#ifndef IN_FDB_MINI
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_LEARNING_CTRL_GET))
+		p_adpt_api->adpt_fdb_port_newaddr_lrn_get = adpt_hppe_fdb_port_newaddr_lrn_get;
+#endif
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_STAMOVE_CTRL_SET))
+		p_adpt_api->adpt_fdb_port_stamove_set = adpt_hppe_fdb_port_stamove_set;
+#ifndef IN_FDB_MINI
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_STAMOVE_CTRL_GET))
+		p_adpt_api->adpt_fdb_port_stamove_get = adpt_hppe_fdb_port_stamove_get;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_LEARNED_MAC_COUNTER_GET))
+		p_adpt_api->adpt_port_fdb_learn_counter_get = adpt_hppe_port_fdb_learn_counter_get;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_PORT_FDB_LEARN_EXCEED_CMD_SET))
+		p_adpt_api->adpt_port_fdb_learn_exceed_cmd_set = adpt_hppe_port_fdb_learn_exceed_cmd_set;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_PORT_FDB_LEARN_EXCEED_CMD_GET))
+		p_adpt_api->adpt_port_fdb_learn_exceed_cmd_get = adpt_hppe_port_fdb_learn_exceed_cmd_get;
+#endif
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_AGING_CTRL_SET))
+		p_adpt_api->adpt_fdb_age_ctrl_set = adpt_hppe_fdb_age_ctrl_set;
+#ifndef IN_FDB_MINI
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_AGING_CTRL_GET))
+		p_adpt_api->adpt_fdb_age_ctrl_get = adpt_hppe_fdb_age_ctrl_get;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_MACLIMIT_CTRL_SET))
+		p_adpt_api->adpt_fdb_port_maclimit_ctrl_set = adpt_hppe_fdb_port_maclimit_ctrl_set;
+	if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_MACLIMIT_CTRL_GET))
+		p_adpt_api->adpt_fdb_port_maclimit_ctrl_get = adpt_hppe_fdb_port_maclimit_ctrl_get;
+#endif
+	if (p_adpt_api->adpt_fdb_func_bitmap[1] & (1 << (FUNC_FDB_DEL_BY_FID % 32)))
+		p_adpt_api->adpt_fdb_del_by_fid = adpt_hppe_fdb_del_by_fid;
+
+	aos_lock_init(&hppe_fdb_lock);
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_flow.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_flow.c
new file mode 100755
index 0000000..9302a4c
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_flow.c
@@ -0,0 +1,1850 @@
+/*
+ * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "fal_flow.h"
+#include "hppe_ip_reg.h"
+#include "hppe_ip.h"
+#include "hppe_flow_reg.h"
+#include "hppe_flow.h"
+#include "adpt_hppe.h"
+#include "adpt.h"
+
+#if defined(CPPE)
+#include "adpt_cppe_flow.h"
+#endif
+
+
+#define FLOW_ENTRY_TYPE_IPV4 0
+#define FLOW_ENTRY_TYPE_IPV6 1
+#define FLOW_TUPLE_TYPE_3    0
+
+#ifndef IN_FLOW_MINI
+sw_error_t
+adpt_hppe_ip_flow_host_data_rd_add(a_uint32_t dev_id, fal_host_entry_t * host_entry)
+
+{
+	a_uint8_t mode = 0, type = 0;
+	sw_error_t rv = SW_OK;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(host_entry);
+
+	mode = host_entry->flags >> 24;
+	type = host_entry->flags & 0xff;
+
+	if ((type & FAL_IP_IP4_ADDR) == FAL_IP_IP4_ADDR) {
+		union host_tbl_u entry;
+		entry.bf.valid= host_entry->status;
+		entry.bf.key_type = 0;
+		entry.bf.fwd_cmd = host_entry->action;
+		entry.bf.syn_toggle = host_entry->syn_toggle;
+		entry.bf.dst_info = host_entry->port_id;
+		entry.bf.lan_wan = host_entry->lan_wan;
+		entry.bf.ip_addr = host_entry->ip4_addr;
+		rv = hppe_flow_host_ipv4_data_rd_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+	} else if ((type & FAL_IP_IP6_ADDR) == FAL_IP_IP6_ADDR) {
+		union host_ipv6_tbl_u entry;
+		entry.bf.valid= host_entry->status;
+		entry.bf.key_type = 2;
+		entry.bf.fwd_cmd = host_entry->action;
+		entry.bf.syn_toggle = host_entry->syn_toggle;
+		entry.bf.dst_info = host_entry->port_id;
+		entry.bf.lan_wan = host_entry->lan_wan;
+		entry.bf.ipv6_addr_0 = host_entry->ip6_addr.ul[3];
+		entry.bf.ipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 10 | \
+							host_entry->ip6_addr.ul[2] << 22;
+		entry.bf.ipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 10 | \
+							host_entry->ip6_addr.ul[1] << 22;
+		entry.bf.ipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 10 | \
+							host_entry->ip6_addr.ul[0] << 22;
+		entry.bf.ipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 10;
+		rv = hppe_flow_host_ipv6_data_rd_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_flow_host_data_add(a_uint32_t dev_id, fal_host_entry_t * host_entry)
+{
+	a_uint8_t mode = 0, type = 0;
+	sw_error_t rv = SW_OK;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(host_entry);
+
+	mode = host_entry->flags >> 24;
+	type = host_entry->flags & 0xff;
+
+	if ((type & FAL_IP_IP4_ADDR) == FAL_IP_IP4_ADDR) {
+		union host_tbl_u entry;
+		entry.bf.valid= host_entry->status;
+		entry.bf.key_type = 0;
+		entry.bf.fwd_cmd = host_entry->action;
+		entry.bf.syn_toggle = host_entry->syn_toggle;
+		entry.bf.dst_info = host_entry->port_id;
+		entry.bf.lan_wan = host_entry->lan_wan;
+		entry.bf.ip_addr = host_entry->ip4_addr;
+		rv = hppe_flow_host_ipv4_data_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+	} else if ((type & FAL_IP_IP6_ADDR) == FAL_IP_IP6_ADDR) {
+		union host_ipv6_tbl_u entry;
+		entry.bf.valid= host_entry->status;
+		entry.bf.key_type = 2;
+		entry.bf.fwd_cmd = host_entry->action;
+		entry.bf.syn_toggle = host_entry->syn_toggle;
+		entry.bf.dst_info = host_entry->port_id;
+		entry.bf.lan_wan = host_entry->lan_wan;
+		entry.bf.ipv6_addr_0 = host_entry->ip6_addr.ul[3];
+		entry.bf.ipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 10 | \
+							host_entry->ip6_addr.ul[2] << 22;
+		entry.bf.ipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 10 | \
+							host_entry->ip6_addr.ul[1] << 22;
+		entry.bf.ipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 10 | \
+							host_entry->ip6_addr.ul[0] << 22;
+		entry.bf.ipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 10;
+		rv = hppe_flow_host_ipv6_data_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_flow_host_data_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                    fal_host_entry_t *host_entry)
+{
+	a_uint8_t mode = 0, type = 0;
+	sw_error_t rv = SW_OK;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(host_entry);
+
+	mode = host_entry->flags >> 24;
+	type = host_entry->flags & 0xff;
+
+	if (get_mode & FAL_IP_ENTRY_ID_EN)
+		mode = 1;
+	else if (get_mode & FAL_IP_ENTRY_IPADDR_EN)
+		mode  = 0;
+
+	if ((type & FAL_IP_IP4_ADDR) == FAL_IP_IP4_ADDR) {
+		union host_tbl_u entry;
+		entry.bf.key_type = 0;
+		entry.bf.ip_addr = host_entry->ip4_addr;
+		rv = hppe_flow_host_ipv4_data_get(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+		host_entry->ip4_addr = entry.bf.ip_addr;
+		host_entry->lan_wan = entry.bf.lan_wan;
+		host_entry->port_id = entry.bf.dst_info;
+		host_entry->syn_toggle = entry.bf.syn_toggle;
+		host_entry->action = entry.bf.fwd_cmd;
+		host_entry->status = entry.bf.valid;
+	} else if ((type & FAL_IP_IP6_ADDR) == FAL_IP_IP6_ADDR) {
+		union host_ipv6_tbl_u entry;
+		entry.bf.key_type = 2;
+		entry.bf.ipv6_addr_0 = host_entry->ip6_addr.ul[3];
+		entry.bf.ipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 10 | \
+							host_entry->ip6_addr.ul[2] << 22;
+		entry.bf.ipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 10 | \
+							host_entry->ip6_addr.ul[1] << 22;
+		entry.bf.ipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 10 | \
+							host_entry->ip6_addr.ul[0] << 22;
+		entry.bf.ipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 10;
+		rv = hppe_flow_host_ipv6_data_get(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+		host_entry->ip6_addr.ul[3] = entry.bf.ipv6_addr_0 | entry.bf.ipv6_addr_1 << 10;
+		host_entry->ip6_addr.ul[2] = entry.bf.ipv6_addr_1 >> 22 | entry.bf.ipv6_addr_2 << 10;
+		host_entry->ip6_addr.ul[1] = entry.bf.ipv6_addr_2 >> 22 | entry.bf.ipv6_addr_3 << 10;
+		host_entry->ip6_addr.ul[0] = entry.bf.ipv6_addr_3 >> 22 | entry.bf.ipv6_addr_4 << 10;
+		host_entry->lan_wan = entry.bf.lan_wan;
+		host_entry->port_id = entry.bf.dst_info;
+		host_entry->syn_toggle = entry.bf.syn_toggle;
+		host_entry->action = entry.bf.fwd_cmd;
+		host_entry->status = entry.bf.valid;
+	}
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ip_flow_host_data_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                    fal_host_entry_t * host_entry)
+{
+	a_uint8_t mode = 0, type = 0;
+	sw_error_t rv = SW_OK;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(host_entry);
+
+	mode = host_entry->flags >> 24;
+	type = host_entry->flags & 0xff;
+
+	if (del_mode & FAL_IP_ENTRY_ID_EN)
+		mode = 1;
+	else if (del_mode & FAL_IP_ENTRY_IPADDR_EN)
+		mode  = 0;
+	else if (del_mode & FAL_IP_ENTRY_ALL_EN) {
+		return hppe_flow_host_flush_common(dev_id);
+	}
+
+	if ((type & FAL_IP_IP4_ADDR) == FAL_IP_IP4_ADDR) {
+		union host_tbl_u entry;
+		entry.bf.valid= 1;
+		entry.bf.key_type = 0;
+		entry.bf.fwd_cmd = host_entry->action;
+		entry.bf.syn_toggle = host_entry->syn_toggle;
+		entry.bf.dst_info = host_entry->port_id;
+		entry.bf.lan_wan = host_entry->lan_wan;
+		entry.bf.ip_addr = host_entry->ip4_addr;
+		rv = hppe_flow_host_ipv4_data_del(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+	} else if ((type & FAL_IP_IP6_ADDR) == FAL_IP_IP6_ADDR) {
+		union host_ipv6_tbl_u entry;
+		entry.bf.valid= 1;
+		entry.bf.key_type = 2;
+		entry.bf.fwd_cmd = host_entry->action;
+		entry.bf.syn_toggle = host_entry->syn_toggle;
+		entry.bf.dst_info = host_entry->port_id;
+		entry.bf.lan_wan = host_entry->lan_wan;
+		entry.bf.ipv6_addr_0 = host_entry->ip6_addr.ul[3];
+		entry.bf.ipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 10 | \
+							host_entry->ip6_addr.ul[2] << 22;
+		entry.bf.ipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 10 | \
+							host_entry->ip6_addr.ul[1] << 22;
+		entry.bf.ipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 10 | \
+							host_entry->ip6_addr.ul[0] << 22;
+		entry.bf.ipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 10;
+		rv = hppe_flow_host_ipv6_data_del(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+	}
+	return rv;
+}
+
+
+sw_error_t
+adpt_hppe_flow_entry_host_op_add(
+		a_uint32_t dev_id,
+		a_uint32_t add_mode, /*index or hash*/
+		fal_flow_entry_t *flow_entry)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t type = 0;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(flow_entry);
+
+	type = flow_entry->entry_type;
+	if ((type & FAL_FLOW_IP4_5TUPLE_ADDR) == FAL_FLOW_IP4_5TUPLE_ADDR) {
+		union in_flow_tbl_u entry;
+		entry.bf0.valid= 1;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf0.next_hop1 = flow_entry->snat_nexthop;
+			entry.bf0.l4_port1 = flow_entry->snat_srcport;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+			entry.bf3.l4_port2 = flow_entry->dnat_dstport;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf1.port_vp2 = flow_entry->bridge_port;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4;
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20;
+		entry.bf0.l4_sport = flow_entry->src_port;
+		entry.bf0.l4_dport_0 = flow_entry->dst_port;
+		entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4;
+		rv = hppe_flow_entry_host_op_ipv4_5tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry);
+	} else if ((type & FAL_FLOW_IP6_5TUPLE_ADDR) == FAL_FLOW_IP6_5TUPLE_ADDR) {
+		union in_flow_ipv6_5tuple_tbl_u entry;
+		entry.bf0.valid= 1;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf0.next_hop1 = flow_entry->snat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf1.port_vp2 = flow_entry->bridge_port;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3];
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[2] << 12;
+		entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[1] << 12;
+		entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[0] << 12;
+		entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20;
+		entry.bf0.l4_sport = flow_entry->src_port;
+		entry.bf0.l4_dport_0 = flow_entry->dst_port;
+		entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4;
+		rv = hppe_flow_entry_host_op_ipv6_5tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry);
+	} else if ((type & FAL_FLOW_IP4_3TUPLE_ADDR) == FAL_FLOW_IP4_3TUPLE_ADDR) {
+		union in_flow_3tuple_tbl_u entry;
+		entry.bf0.valid= 1;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf0.next_hop1 = flow_entry->snat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf1.port_vp2 = flow_entry->bridge_port;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4;
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20;
+		entry.bf0.ip_protocol = flow_entry->ip_type;
+		rv = hppe_flow_entry_host_op_ipv4_3tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry);
+	} else if ((type & FAL_FLOW_IP6_3TUPLE_ADDR) == FAL_FLOW_IP6_3TUPLE_ADDR) {
+		union in_flow_ipv6_3tuple_tbl_u entry;
+		entry.bf0.valid= 1;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf1.next_hop1 = flow_entry->snat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf0.port_vp2 = flow_entry->bridge_port;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3];
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[2] << 12;
+		entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[1] << 12;
+		entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[0] << 12;
+		entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20;
+		entry.bf0.ip_protocol = flow_entry->ip_type;
+		rv = hppe_flow_entry_host_op_ipv6_3tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry);
+	} else
+		return SW_FAIL;
+	if (rv == SW_OK) {
+		union eg_flow_tree_map_tbl_u eg_treemap;
+		eg_treemap.bf.tree_id = flow_entry->tree_id;
+		rv = hppe_eg_flow_tree_map_tbl_set(dev_id, flow_entry->entry_id, &eg_treemap);
+	}
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_flow_entry_host_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t get_mode,
+		fal_flow_entry_t *flow_entry)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t type = 0;
+	a_uint32_t entry_id = 0;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(flow_entry);
+
+	type = flow_entry->entry_type;
+	if ((type & FAL_FLOW_IP4_5TUPLE_ADDR) == FAL_FLOW_IP4_5TUPLE_ADDR) {
+		union in_flow_tbl_u entry;
+		entry.bf0.valid= 1;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4;
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20;
+		entry.bf0.l4_sport = flow_entry->src_port;
+		entry.bf0.l4_dport_0 = flow_entry->dst_port;
+		entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4;
+		rv = hppe_flow_entry_host_op_ipv4_5tuple_get(dev_id, get_mode, &entry_id, &entry);
+		flow_entry->entry_id = entry_id;
+		flow_entry->host_addr_type = entry.bf0.host_addr_index_type;
+		flow_entry->host_addr_index = entry.bf0.host_addr_index;
+		flow_entry->protocol = entry.bf0.protocol_type;
+		flow_entry->age = entry.bf0.age;
+		flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid;
+		flow_entry->src_intf_index = entry.bf0.src_l3_if;
+		flow_entry->fwd_type = entry.bf0.fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			flow_entry->snat_nexthop = entry.bf0.next_hop1;
+			flow_entry->snat_srcport = entry.bf0.l4_port1;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			flow_entry->dnat_nexthop = entry.bf3.next_hop2;
+			flow_entry->dnat_dstport = entry.bf3.l4_port2;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			flow_entry->route_nexthop = entry.bf2.next_hop3;
+			flow_entry->port_valid = entry.bf2.port_vp_valid1;
+			flow_entry->route_port = entry.bf2.port_vp1;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			flow_entry->bridge_port = entry.bf1.port_vp2;
+		}
+		flow_entry->deacclr_en = entry.bf0.de_acce;
+		flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en;
+		flow_entry->syn_toggle = entry.bf0.syn_toggle;
+		flow_entry->pri_profile = entry.bf0.pri_profile_0 |\
+								entry.bf0.pri_profile_1 << 1;
+		flow_entry->sevice_code = entry.bf0.service_code;
+		flow_entry->flow_ip.ipv4 = entry.bf0.ip_addr_0 |\
+					   entry.bf0.ip_addr_1 << 20;
+		flow_entry->src_port = entry.bf0.l4_sport;
+		flow_entry->dst_port = entry.bf0.l4_dport_0 |\
+					entry.bf0.l4_dport_1 << 4;
+	} else if ((type & FAL_FLOW_IP6_5TUPLE_ADDR) == FAL_FLOW_IP6_5TUPLE_ADDR) {
+		union in_flow_ipv6_5tuple_tbl_u entry;
+		entry.bf0.valid= 1;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3];
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[2] << 12;
+		entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[1] << 12;
+		entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[0] << 12;
+		entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20;
+		entry.bf0.l4_sport = flow_entry->src_port;
+		entry.bf0.l4_dport_0 = flow_entry->dst_port;
+		entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4;
+		rv = hppe_flow_entry_host_op_ipv6_5tuple_get(dev_id, get_mode, &entry_id, &entry);
+		flow_entry->entry_id = entry_id;
+		flow_entry->host_addr_type = entry.bf0.host_addr_index_type;
+		flow_entry->host_addr_index = entry.bf0.host_addr_index;
+		flow_entry->protocol = entry.bf0.protocol_type;
+		flow_entry->age = entry.bf0.age;
+		flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid;
+		flow_entry->src_intf_index = entry.bf0.src_l3_if;
+		flow_entry->fwd_type = entry.bf0.fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			flow_entry->snat_nexthop = entry.bf0.next_hop1;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			flow_entry->dnat_nexthop = entry.bf3.next_hop2;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			flow_entry->route_nexthop = entry.bf2.next_hop3;
+			flow_entry->port_valid = entry.bf2.port_vp_valid1;
+			flow_entry->route_port = entry.bf2.port_vp1;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			flow_entry->bridge_port = entry.bf1.port_vp2;
+		}
+		flow_entry->deacclr_en = entry.bf0.de_acce;
+		flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en;
+		flow_entry->syn_toggle = entry.bf0.syn_toggle;
+		flow_entry->pri_profile = entry.bf0.pri_profile_0 |\
+								entry.bf0.pri_profile_1 << 1;
+		flow_entry->sevice_code = entry.bf0.service_code;
+		flow_entry->flow_ip.ipv6.ul[3] = entry.bf0.ip_addr_0 |\
+					   entry.bf0.ip_addr_1 << 20;
+		flow_entry->flow_ip.ipv6.ul[2] = entry.bf0.ip_addr_1 >> 12 |\
+					   entry.bf0.ip_addr_2 << 20;
+		flow_entry->flow_ip.ipv6.ul[1] = entry.bf0.ip_addr_2 >> 12 |\
+					   entry.bf0.ip_addr_3 << 20;
+		flow_entry->flow_ip.ipv6.ul[0] = entry.bf0.ip_addr_3 >> 12 |\
+					   entry.bf0.ip_addr_4 << 20;
+		flow_entry->src_port = entry.bf0.l4_sport;
+		flow_entry->dst_port = entry.bf0.l4_dport_0 |\
+					entry.bf0.l4_dport_1 << 4;
+	} else if ((type & FAL_FLOW_IP4_3TUPLE_ADDR) == FAL_FLOW_IP4_3TUPLE_ADDR) {
+		union in_flow_3tuple_tbl_u entry;
+		entry.bf0.valid= 1;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4;
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20;
+		entry.bf0.ip_protocol = flow_entry->ip_type;
+		rv = hppe_flow_entry_host_op_ipv4_3tuple_get(dev_id, get_mode, &entry_id, &entry);
+		flow_entry->entry_id = entry_id;
+		flow_entry->host_addr_type = entry.bf0.host_addr_index_type;
+		flow_entry->host_addr_index = entry.bf0.host_addr_index;
+		flow_entry->protocol = entry.bf0.protocol_type;
+		flow_entry->age = entry.bf0.age;
+		flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid;
+		flow_entry->src_intf_index = entry.bf0.src_l3_if;
+		flow_entry->fwd_type = entry.bf0.fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			flow_entry->snat_nexthop = entry.bf0.next_hop1;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			flow_entry->dnat_nexthop = entry.bf3.next_hop2;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			flow_entry->route_nexthop = entry.bf2.next_hop3;
+			flow_entry->port_valid = entry.bf2.port_vp_valid1;
+			flow_entry->route_port = entry.bf2.port_vp1;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			flow_entry->bridge_port = entry.bf1.port_vp2;
+		}
+		flow_entry->deacclr_en = entry.bf0.de_acce;
+		flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en;
+		flow_entry->syn_toggle = entry.bf0.syn_toggle;
+		flow_entry->pri_profile = entry.bf0.pri_profile_0 |\
+								entry.bf0.pri_profile_1 << 1;
+		flow_entry->sevice_code = entry.bf0.service_code;
+		flow_entry->flow_ip.ipv4 = entry.bf0.ip_addr_0 |\
+					   entry.bf0.ip_addr_1 << 20;
+		flow_entry->ip_type = entry.bf0.ip_protocol;
+	} else if ((type & FAL_FLOW_IP6_3TUPLE_ADDR) == FAL_FLOW_IP6_3TUPLE_ADDR) {
+		union in_flow_ipv6_3tuple_tbl_u entry;
+		entry.bf0.valid= 1;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3];
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[2] << 12;
+		entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[1] << 12;
+		entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[0] << 12;
+		entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20;
+		entry.bf0.ip_protocol = flow_entry->ip_type;
+		rv = hppe_flow_entry_host_op_ipv6_3tuple_get(dev_id, get_mode, &entry_id, &entry);
+		flow_entry->entry_id = entry_id;
+		flow_entry->host_addr_type = entry.bf0.host_addr_index_type;
+		flow_entry->host_addr_index = entry.bf0.host_addr_index;
+		flow_entry->protocol = entry.bf0.protocol_type;
+		flow_entry->age = entry.bf0.age;
+		flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid;
+		flow_entry->src_intf_index = entry.bf0.src_l3_if;
+		flow_entry->fwd_type = entry.bf0.fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			flow_entry->snat_nexthop = entry.bf1.next_hop1;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			flow_entry->dnat_nexthop = entry.bf3.next_hop2;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			flow_entry->route_nexthop = entry.bf2.next_hop3;
+			flow_entry->port_valid = entry.bf2.port_vp_valid1;
+			flow_entry->route_port = entry.bf2.port_vp1;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			flow_entry->bridge_port = entry.bf0.port_vp2;
+		}
+		flow_entry->deacclr_en = entry.bf0.de_acce;
+		flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en;
+		flow_entry->syn_toggle = entry.bf0.syn_toggle;
+		flow_entry->pri_profile = entry.bf0.pri_profile_0 |\
+								entry.bf0.pri_profile_1 << 1;
+		flow_entry->sevice_code = entry.bf0.service_code;
+		flow_entry->flow_ip.ipv6.ul[3] = entry.bf0.ip_addr_0 |\
+					   entry.bf0.ip_addr_1 << 20;
+		flow_entry->flow_ip.ipv6.ul[2] = entry.bf0.ip_addr_1 >> 12 |\
+					   entry.bf0.ip_addr_2 << 20;
+		flow_entry->flow_ip.ipv6.ul[1] = entry.bf0.ip_addr_2 >> 12 |\
+					   entry.bf0.ip_addr_3 << 20;
+		flow_entry->flow_ip.ipv6.ul[0] = entry.bf0.ip_addr_3 >> 12 |\
+					   entry.bf0.ip_addr_4 << 20;
+		flow_entry->ip_type = entry.bf0.ip_protocol;
+	} else
+		return SW_FAIL;
+
+	if (rv == SW_OK) {
+		union eg_flow_tree_map_tbl_u eg_treemap;
+		union in_flow_cnt_tbl_u cnt;
+		rv = hppe_eg_flow_tree_map_tbl_get(dev_id, flow_entry->entry_id, &eg_treemap);
+		flow_entry->tree_id = eg_treemap.bf.tree_id;
+		rv = hppe_in_flow_cnt_tbl_get(dev_id, flow_entry->entry_id, &cnt);
+		flow_entry->pkt_counter = cnt.bf.hit_pkt_counter;
+		flow_entry->byte_counter = cnt.bf.hit_byte_counter_0 | \
+					((a_uint64_t)cnt.bf.hit_byte_counter_1 << 32);
+	}
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_flow_entry_host_op_del(
+		a_uint32_t dev_id,
+		a_uint32_t del_mode,
+		fal_flow_entry_t *flow_entry)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t type = 0;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(flow_entry);
+
+	if (del_mode == FAL_FLOW_OP_MODE_FLUSH)
+		return hppe_flow_host_flush_common(dev_id);
+		//return hppe_flow_flush_common(dev_id);
+
+	type = flow_entry->entry_type;
+	if ((type & FAL_FLOW_IP4_5TUPLE_ADDR) == FAL_FLOW_IP4_5TUPLE_ADDR) {
+		union in_flow_tbl_u entry;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf0.next_hop1 = flow_entry->snat_nexthop;
+			entry.bf0.l4_port1 = flow_entry->snat_srcport;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+			entry.bf3.l4_port2 = flow_entry->dnat_dstport;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf1.port_vp2 = flow_entry->bridge_port;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4;
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20;
+		entry.bf0.l4_sport = flow_entry->src_port;
+		entry.bf0.l4_dport_0 = flow_entry->dst_port;
+		entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4;
+		rv = hppe_flow_entry_host_op_ipv4_5tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry);
+	} else if ((type & FAL_FLOW_IP6_5TUPLE_ADDR) == FAL_FLOW_IP6_5TUPLE_ADDR) {
+		union in_flow_ipv6_5tuple_tbl_u entry;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf0.next_hop1 = flow_entry->snat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf1.port_vp2 = flow_entry->bridge_port;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3];
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[2] << 12;
+		entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[1] << 12;
+		entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[0] << 12;
+		entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20;
+		entry.bf0.l4_sport = flow_entry->src_port;
+		entry.bf0.l4_dport_0 = flow_entry->dst_port;
+		entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4;
+		rv = hppe_flow_entry_host_op_ipv6_5tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry);
+	} else if ((type & FAL_FLOW_IP4_3TUPLE_ADDR) == FAL_FLOW_IP4_3TUPLE_ADDR) {
+		union in_flow_3tuple_tbl_u entry;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf0.next_hop1 = flow_entry->snat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf1.port_vp2 = flow_entry->bridge_port;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4;
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20;
+		entry.bf0.ip_protocol = flow_entry->ip_type;
+		rv = hppe_flow_entry_host_op_ipv4_3tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry);
+	} else if ((type & FAL_FLOW_IP6_3TUPLE_ADDR) == FAL_FLOW_IP6_3TUPLE_ADDR) {
+		union in_flow_ipv6_3tuple_tbl_u entry;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf1.next_hop1 = flow_entry->snat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf0.port_vp2 = flow_entry->bridge_port;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3];
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[2] << 12;
+		entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[1] << 12;
+		entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[0] << 12;
+		entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20;
+		entry.bf0.ip_protocol = flow_entry->ip_type;
+		rv = hppe_flow_entry_host_op_ipv6_3tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry);
+	} else
+		return SW_FAIL;
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_flow_host_add(
+		a_uint32_t dev_id,
+		a_uint32_t add_mode,
+		fal_flow_host_entry_t *flow_host)
+{
+	sw_error_t rv = SW_OK;
+	fal_flow_entry_t *flow_entry = &(flow_host->flow_entry);
+	fal_host_entry_t *host_entry = &(flow_host->host_entry);
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(flow_host);
+
+	rv = adpt_hppe_ip_flow_host_data_add(dev_id, host_entry);
+	SW_RTN_ON_ERROR(rv);
+	rv = adpt_hppe_flow_entry_host_op_add(dev_id, add_mode, flow_entry);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = hppe_flow_host_tbl_op_rslt_host_entry_index_get(dev_id, &host_entry->entry_id);
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_flow_host_get(
+		a_uint32_t dev_id,
+		a_uint32_t get_mode,
+		fal_flow_host_entry_t *flow_host)
+{
+	sw_error_t rv = SW_OK;
+	fal_flow_entry_t *flow_entry = &(flow_host->flow_entry);
+	fal_host_entry_t *host_entry = &(flow_host->host_entry);
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(flow_host);
+
+	rv = adpt_hppe_ip_flow_host_data_rd_add(dev_id, host_entry);
+	rv = adpt_hppe_flow_entry_host_op_get(dev_id, get_mode, flow_entry);
+	if(rv != SW_OK)
+		return rv;
+
+	rv = hppe_flow_host_tbl_rd_op_rslt_host_entry_index_get(dev_id, &host_entry->entry_id);
+	if(rv != SW_OK)
+		return rv;
+
+	rv = adpt_hppe_ip_flow_host_data_get(dev_id, get_mode, host_entry);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_flow_host_del(
+		a_uint32_t dev_id,
+		a_uint32_t del_mode,
+		fal_flow_host_entry_t *flow_host)
+{
+	fal_flow_entry_t *flow_entry = &(flow_host->flow_entry);
+	fal_host_entry_t *host_entry = &(flow_host->host_entry);
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(flow_host);
+
+	adpt_hppe_ip_flow_host_data_del(dev_id, del_mode, host_entry);
+	adpt_hppe_flow_entry_host_op_del(dev_id, del_mode, flow_entry);
+	return SW_OK;
+}
+
+
+sw_error_t
+adpt_hppe_flow_entry_get(
+		a_uint32_t dev_id,
+		a_uint32_t get_mode,
+		fal_flow_entry_t *flow_entry)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t type = 0;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(flow_entry);
+
+
+	type = flow_entry->entry_type;
+	if ((type & FAL_FLOW_IP4_5TUPLE_ADDR) == FAL_FLOW_IP4_5TUPLE_ADDR) {
+		union in_flow_tbl_u entry;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4;
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20;
+		entry.bf0.l4_sport = flow_entry->src_port;
+		entry.bf0.l4_dport_0 = flow_entry->dst_port;
+		entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4;
+		rv = hppe_flow_ipv4_5tuple_get(dev_id, get_mode, &flow_entry->entry_id, &entry);
+		if (entry.bf0.entry_type != FLOW_ENTRY_TYPE_IPV4 ||
+				entry.bf0.protocol_type == FLOW_TUPLE_TYPE_3) {
+			return SW_BAD_VALUE;
+		}
+		flow_entry->host_addr_type = entry.bf0.host_addr_index_type;
+		flow_entry->host_addr_index = entry.bf0.host_addr_index;
+		flow_entry->protocol = entry.bf0.protocol_type;
+		flow_entry->age = entry.bf0.age;
+		flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid;
+		flow_entry->src_intf_index = entry.bf0.src_l3_if;
+		flow_entry->fwd_type = entry.bf0.fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			flow_entry->snat_nexthop = entry.bf0.next_hop1;
+			flow_entry->snat_srcport = entry.bf0.l4_port1;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			flow_entry->dnat_nexthop = entry.bf3.next_hop2;
+			flow_entry->dnat_dstport = entry.bf3.l4_port2;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			flow_entry->route_nexthop = entry.bf2.next_hop3;
+			flow_entry->port_valid = entry.bf2.port_vp_valid1;
+			flow_entry->route_port = entry.bf2.port_vp1;
+			if (entry.bf2.port_vp1 >= 64)
+				flow_entry->route_port |= 0x1000000;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			flow_entry->bridge_port = entry.bf1.port_vp2;
+			if (entry.bf1.port_vp2 >= 64)
+				flow_entry->bridge_port |= 0x1000000;
+		}
+		flow_entry->deacclr_en = entry.bf0.de_acce;
+		flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en;
+		flow_entry->syn_toggle = entry.bf0.syn_toggle;
+		flow_entry->pri_profile = entry.bf0.pri_profile_0 |\
+								entry.bf0.pri_profile_1 << 1;
+		flow_entry->sevice_code = entry.bf0.service_code;
+		flow_entry->flow_ip.ipv4 = entry.bf0.ip_addr_0 |\
+					   entry.bf0.ip_addr_1 << 20;
+		flow_entry->src_port = entry.bf0.l4_sport;
+		flow_entry->dst_port = entry.bf0.l4_dport_0 |\
+					entry.bf0.l4_dport_1 << 4;
+		
+	} else if ((type & FAL_FLOW_IP6_5TUPLE_ADDR) == FAL_FLOW_IP6_5TUPLE_ADDR) {
+		union in_flow_ipv6_5tuple_tbl_u entry;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3];
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[2] << 12;
+		entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[1] << 12;
+		entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[0] << 12;
+		entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20;
+		entry.bf0.l4_sport = flow_entry->src_port;
+		entry.bf0.l4_dport_0 = flow_entry->dst_port;
+		entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4;
+		rv = hppe_flow_ipv6_5tuple_get(dev_id, get_mode, &flow_entry->entry_id, &entry);
+		if (entry.bf0.entry_type != FLOW_ENTRY_TYPE_IPV6 ||
+				entry.bf0.protocol_type == FLOW_TUPLE_TYPE_3) {
+			return SW_BAD_VALUE;
+		}
+		flow_entry->host_addr_type = entry.bf0.host_addr_index_type;
+		flow_entry->host_addr_index = entry.bf0.host_addr_index;
+		flow_entry->protocol = entry.bf0.protocol_type;
+		flow_entry->age = entry.bf0.age;
+		flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid;
+		flow_entry->src_intf_index = entry.bf0.src_l3_if;
+		flow_entry->fwd_type = entry.bf0.fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			flow_entry->snat_nexthop = entry.bf0.next_hop1;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			flow_entry->dnat_nexthop = entry.bf3.next_hop2;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			flow_entry->route_nexthop = entry.bf2.next_hop3;
+			flow_entry->port_valid = entry.bf2.port_vp_valid1;
+			flow_entry->route_port = entry.bf2.port_vp1;
+			if (entry.bf2.port_vp1 >= 64)
+				flow_entry->route_port |= 0x1000000;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			flow_entry->bridge_port = entry.bf1.port_vp2;
+			if (entry.bf1.port_vp2 >= 64)
+				flow_entry->bridge_port |= 0x1000000;
+		}
+		flow_entry->deacclr_en = entry.bf0.de_acce;
+		flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en;
+		flow_entry->syn_toggle = entry.bf0.syn_toggle;
+		flow_entry->pri_profile = entry.bf0.pri_profile_0 |\
+								entry.bf0.pri_profile_1 << 1;
+		flow_entry->sevice_code = entry.bf0.service_code;
+		flow_entry->flow_ip.ipv6.ul[3] = entry.bf0.ip_addr_0 |\
+					   entry.bf0.ip_addr_1 << 20;
+		flow_entry->flow_ip.ipv6.ul[2] = entry.bf0.ip_addr_1 >> 12 |\
+					   entry.bf0.ip_addr_2 << 20;
+		flow_entry->flow_ip.ipv6.ul[1] = entry.bf0.ip_addr_2 >> 12 |\
+					   entry.bf0.ip_addr_3 << 20;
+		flow_entry->flow_ip.ipv6.ul[0] = entry.bf0.ip_addr_3 >> 12 |\
+					   entry.bf0.ip_addr_4 << 20;
+		flow_entry->src_port = entry.bf0.l4_sport;
+		flow_entry->dst_port = entry.bf0.l4_dport_0 |\
+					entry.bf0.l4_dport_1 << 4;
+		
+	} else if ((type & FAL_FLOW_IP4_3TUPLE_ADDR) == FAL_FLOW_IP4_3TUPLE_ADDR) {
+		union in_flow_3tuple_tbl_u entry;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4;
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20;
+		entry.bf0.ip_protocol = flow_entry->ip_type;
+		rv = hppe_flow_ipv4_3tuple_get(dev_id, get_mode, &flow_entry->entry_id, &entry);
+		if (entry.bf0.entry_type != FLOW_ENTRY_TYPE_IPV4 ||
+				entry.bf0.protocol_type != FLOW_TUPLE_TYPE_3) {
+			return SW_BAD_VALUE;
+		}
+		flow_entry->host_addr_type = entry.bf0.host_addr_index_type;
+		flow_entry->host_addr_index = entry.bf0.host_addr_index;
+		flow_entry->protocol = entry.bf0.protocol_type;
+		flow_entry->age = entry.bf0.age;
+		flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid;
+		flow_entry->src_intf_index = entry.bf0.src_l3_if;
+		flow_entry->fwd_type = entry.bf0.fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			flow_entry->snat_nexthop = entry.bf0.next_hop1;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			flow_entry->dnat_nexthop = entry.bf3.next_hop2;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			flow_entry->route_nexthop = entry.bf2.next_hop3;
+			flow_entry->port_valid = entry.bf2.port_vp_valid1;
+			flow_entry->route_port = entry.bf2.port_vp1;
+			if (entry.bf2.port_vp1 >= 64)
+				flow_entry->route_port |= 0x1000000;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			flow_entry->bridge_port = entry.bf1.port_vp2;
+			if (entry.bf1.port_vp2 >= 64)
+				flow_entry->bridge_port |= 0x1000000;
+		}
+		flow_entry->deacclr_en = entry.bf0.de_acce;
+		flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en;
+		flow_entry->syn_toggle = entry.bf0.syn_toggle;
+		flow_entry->pri_profile = entry.bf0.pri_profile_0 |\
+								entry.bf0.pri_profile_1 << 1;
+		flow_entry->sevice_code = entry.bf0.service_code;
+		flow_entry->flow_ip.ipv4 = entry.bf0.ip_addr_0 |\
+					   entry.bf0.ip_addr_1 << 20;
+		flow_entry->ip_type = entry.bf0.ip_protocol;
+	} else if ((type & FAL_FLOW_IP6_3TUPLE_ADDR) == FAL_FLOW_IP6_3TUPLE_ADDR) {
+		union in_flow_ipv6_3tuple_tbl_u entry;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3];
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[2] << 12;
+		entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[1] << 12;
+		entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[0] << 12;
+		entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20;
+		entry.bf0.ip_protocol = flow_entry->ip_type;
+		rv = hppe_flow_ipv6_3tuple_get(dev_id, get_mode, &flow_entry->entry_id, &entry);
+		if (entry.bf0.entry_type != FLOW_ENTRY_TYPE_IPV6 ||
+				entry.bf0.protocol_type != FLOW_TUPLE_TYPE_3) {
+			return SW_BAD_VALUE;
+		}
+		flow_entry->host_addr_type = entry.bf0.host_addr_index_type;
+		flow_entry->host_addr_index = entry.bf0.host_addr_index;
+		flow_entry->protocol = entry.bf0.protocol_type;
+		flow_entry->age = entry.bf0.age;
+		flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid;
+		flow_entry->src_intf_index = entry.bf0.src_l3_if;
+		flow_entry->fwd_type = entry.bf0.fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			flow_entry->snat_nexthop = entry.bf1.next_hop1;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			flow_entry->dnat_nexthop = entry.bf3.next_hop2;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			flow_entry->route_nexthop = entry.bf2.next_hop3;
+			flow_entry->port_valid = entry.bf2.port_vp_valid1;
+			flow_entry->route_port = entry.bf2.port_vp1;
+			if (entry.bf2.port_vp1 >= 64)
+				flow_entry->route_port |= 0x1000000;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			flow_entry->bridge_port = entry.bf0.port_vp2;
+			if (entry.bf0.port_vp2 >= 64)
+				flow_entry->bridge_port |= 0x1000000;
+		}
+		flow_entry->deacclr_en = entry.bf0.de_acce;
+		flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en;
+		flow_entry->syn_toggle = entry.bf0.syn_toggle;
+		flow_entry->pri_profile = entry.bf0.pri_profile_0 |\
+								entry.bf0.pri_profile_1 << 1;
+		flow_entry->sevice_code = entry.bf0.service_code;
+		flow_entry->flow_ip.ipv6.ul[3] = entry.bf0.ip_addr_0 |\
+					   entry.bf0.ip_addr_1 << 20;
+		flow_entry->flow_ip.ipv6.ul[2] = entry.bf0.ip_addr_1 >> 12 |\
+					   entry.bf0.ip_addr_2 << 20;
+		flow_entry->flow_ip.ipv6.ul[1] = entry.bf0.ip_addr_2 >> 12 |\
+					   entry.bf0.ip_addr_3 << 20;
+		flow_entry->flow_ip.ipv6.ul[0] = entry.bf0.ip_addr_3 >> 12 |\
+					   entry.bf0.ip_addr_4 << 20;
+		flow_entry->ip_type = entry.bf0.ip_protocol;
+	} else
+		return SW_FAIL;
+
+	if (rv == SW_OK) {
+		union eg_flow_tree_map_tbl_u eg_treemap;
+		union in_flow_cnt_tbl_u cnt;
+		rv = hppe_eg_flow_tree_map_tbl_get(dev_id, flow_entry->entry_id, &eg_treemap);
+		flow_entry->tree_id = eg_treemap.bf.tree_id;
+		rv = hppe_in_flow_cnt_tbl_get(dev_id, flow_entry->entry_id, &cnt);
+		flow_entry->pkt_counter = cnt.bf.hit_pkt_counter;
+		flow_entry->byte_counter = cnt.bf.hit_byte_counter_0 | \
+					((a_uint64_t)cnt.bf.hit_byte_counter_1 << 32);
+	}
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_flow_entry_next(
+		a_uint32_t dev_id,
+		a_uint32_t next_mode,
+		fal_flow_entry_t *flow_entry)
+{
+	a_uint32_t i = 0, step = 0;
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(flow_entry);
+
+	if (FAL_NEXT_ENTRY_FIRST_ID == flow_entry->entry_id)
+		i = 0;
+
+	if (next_mode == FAL_FLOW_IP4_3TUPLE_ADDR ||
+		next_mode == FAL_FLOW_IP4_5TUPLE_ADDR) {
+		if (FAL_NEXT_ENTRY_FIRST_ID != flow_entry->entry_id)
+			i = flow_entry->entry_id + 1;
+		step = 1;
+	} else if (next_mode == FAL_FLOW_IP6_5TUPLE_ADDR ||
+		 next_mode == FAL_FLOW_IP6_3TUPLE_ADDR) {
+		if (FAL_NEXT_ENTRY_FIRST_ID != flow_entry->entry_id)
+			i = (flow_entry->entry_id & ~1) + 2;
+		step = 2;
+	}
+	for (; i < IN_FLOW_TBL_MAX_ENTRY;) {
+		flow_entry->entry_type = next_mode;
+		flow_entry->entry_id = i;
+		rv = adpt_hppe_flow_entry_get(dev_id, 1, flow_entry);
+		if (!rv) {
+			return rv;
+		}
+		i += step;
+	}
+
+	return SW_FAIL;
+
+}
+
+sw_error_t
+adpt_hppe_flow_entry_del(
+		a_uint32_t dev_id,
+		a_uint32_t del_mode,
+		fal_flow_entry_t *flow_entry)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t type = 0;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(flow_entry);
+
+	if (del_mode == FAL_FLOW_OP_MODE_FLUSH)
+		return hppe_flow_flush_common(dev_id);
+
+	type = flow_entry->entry_type;
+	if ((type & FAL_FLOW_IP4_5TUPLE_ADDR) == FAL_FLOW_IP4_5TUPLE_ADDR) {
+		union in_flow_tbl_u entry;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf0.next_hop1 = flow_entry->snat_nexthop;
+			entry.bf0.l4_port1 = flow_entry->snat_srcport;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+			entry.bf3.l4_port2 = flow_entry->dnat_dstport;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf1.port_vp2 = flow_entry->bridge_port & 0xffffff;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4;
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20;
+		entry.bf0.l4_sport = flow_entry->src_port;
+		entry.bf0.l4_dport_0 = flow_entry->dst_port;
+		entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4;
+		rv = hppe_flow_ipv4_5tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry);
+	} else if ((type & FAL_FLOW_IP6_5TUPLE_ADDR) == FAL_FLOW_IP6_5TUPLE_ADDR) {
+		union in_flow_ipv6_5tuple_tbl_u entry;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf0.next_hop1 = flow_entry->snat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf1.port_vp2 = flow_entry->bridge_port & 0xffffff;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3];
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[2] << 12;
+		entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[1] << 12;
+		entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[0] << 12;
+		entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20;
+		entry.bf0.l4_sport = flow_entry->src_port;
+		entry.bf0.l4_dport_0 = flow_entry->dst_port;
+		entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4;
+		rv = hppe_flow_ipv6_5tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry);
+	} else if ((type & FAL_FLOW_IP4_3TUPLE_ADDR) == FAL_FLOW_IP4_3TUPLE_ADDR) {
+		union in_flow_3tuple_tbl_u entry;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf0.next_hop1 = flow_entry->snat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf1.port_vp2 = flow_entry->bridge_port & 0xffffff;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4;
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20;
+		entry.bf0.ip_protocol = flow_entry->ip_type;
+		rv = hppe_flow_ipv4_3tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry);
+	} else if ((type & FAL_FLOW_IP6_3TUPLE_ADDR) == FAL_FLOW_IP6_3TUPLE_ADDR) {
+		union in_flow_ipv6_3tuple_tbl_u entry;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf1.next_hop1 = flow_entry->snat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf0.port_vp2 = flow_entry->bridge_port & 0xffffff;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3];
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[2] << 12;
+		entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[1] << 12;
+		entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[0] << 12;
+		entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20;
+		entry.bf0.ip_protocol = flow_entry->ip_type;
+		rv = hppe_flow_ipv6_3tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry);
+	} else
+		return SW_FAIL;
+	return rv;
+}
+sw_error_t
+adpt_hppe_flow_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	union flow_ctrl0_u flow_ctrl0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	memset(&flow_ctrl0, 0, sizeof(flow_ctrl0));
+
+	rv = hppe_flow_ctrl0_get(dev_id, &flow_ctrl0);
+	if( rv != SW_OK )
+		return rv;
+
+	*enable = flow_ctrl0.bf.flow_en;
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+adpt_hppe_flow_ctrl_set(
+		a_uint32_t dev_id,
+		fal_flow_pkt_type_t type,
+		fal_flow_direction_t dir,
+		fal_flow_mgmt_t *ctrl)
+{
+	sw_error_t rv = SW_OK;
+	union flow_ctrl1_u flow_ctrl1;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	memset(&flow_ctrl1, 0, sizeof(flow_ctrl1));
+	rv = hppe_flow_ctrl1_get(dev_id, type, &flow_ctrl1);
+	if( rv != SW_OK )
+		return rv;
+
+	if (dir == FAL_FLOW_LAN_TO_LAN_DIR) {
+		flow_ctrl1.bf.flow_ctl0_miss_action = ctrl->miss_action;
+		flow_ctrl1.bf.flow_ctl0_frag_bypass = ctrl->frag_bypass_en;
+		flow_ctrl1.bf.flow_ctl0_tcp_special = ctrl->tcp_spec_bypass_en;
+		flow_ctrl1.bf.flow_ctl0_bypass = ctrl->all_bypass_en;
+		flow_ctrl1.bf.flow_ctl0_key_sel = ctrl->key_sel;
+	} else if (dir == FAL_FLOW_LAN_TO_WAN_DIR) {
+		flow_ctrl1.bf.flow_ctl1_miss_action = ctrl->miss_action;
+		flow_ctrl1.bf.flow_ctl1_frag_bypass = ctrl->frag_bypass_en;
+		flow_ctrl1.bf.flow_ctl1_tcp_special = ctrl->tcp_spec_bypass_en;
+		flow_ctrl1.bf.flow_ctl1_bypass = ctrl->all_bypass_en;
+		flow_ctrl1.bf.flow_ctl1_key_sel = ctrl->key_sel;
+	} else if (dir == FAL_FLOW_WAN_TO_LAN_DIR) {
+		flow_ctrl1.bf.flow_ctl2_miss_action = ctrl->miss_action;
+		flow_ctrl1.bf.flow_ctl2_frag_bypass = ctrl->frag_bypass_en;
+		flow_ctrl1.bf.flow_ctl2_tcp_special = ctrl->tcp_spec_bypass_en;
+		flow_ctrl1.bf.flow_ctl2_bypass = ctrl->all_bypass_en;
+		flow_ctrl1.bf.flow_ctl2_key_sel = ctrl->key_sel;
+	} else if (dir == FAL_FLOW_WAN_TO_WAN_DIR) {
+		flow_ctrl1.bf.flow_ctl3_miss_action = ctrl->miss_action;
+		flow_ctrl1.bf.flow_ctl3_frag_bypass = ctrl->frag_bypass_en;
+		flow_ctrl1.bf.flow_ctl3_tcp_special = ctrl->tcp_spec_bypass_en;
+		flow_ctrl1.bf.flow_ctl3_bypass = ctrl->all_bypass_en;
+		flow_ctrl1.bf.flow_ctl3_key_sel = ctrl->key_sel;
+	} else if (dir == FAL_FLOW_UNKOWN_DIR_DIR) {
+		flow_ctrl1.bf.flow_ctl4_miss_action = ctrl->miss_action;
+		flow_ctrl1.bf.flow_ctl4_frag_bypass = ctrl->frag_bypass_en;
+		flow_ctrl1.bf.flow_ctl4_tcp_special = ctrl->tcp_spec_bypass_en;
+		flow_ctrl1.bf.flow_ctl4_bypass = ctrl->all_bypass_en;
+		flow_ctrl1.bf.flow_ctl4_key_sel = ctrl->key_sel;
+	} else
+		return SW_FAIL;
+
+	return hppe_flow_ctrl1_set(dev_id, type, &flow_ctrl1);;
+}
+
+#ifndef IN_FLOW_MINI
+sw_error_t
+adpt_hppe_flow_age_timer_get(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer)
+{
+	sw_error_t rv = SW_OK;
+	union flow_ctrl0_u flow_ctrl0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(age_timer);
+
+	memset(&flow_ctrl0, 0, sizeof(flow_ctrl0));
+
+	rv = hppe_flow_ctrl0_get(dev_id, &flow_ctrl0);
+	if( rv != SW_OK )
+		return rv;
+
+	age_timer->age_time = flow_ctrl0.bf.flow_age_timer;
+	age_timer->unit = flow_ctrl0.bf.flow_age_timer_unit;
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_flow_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union flow_ctrl0_u flow_ctrl0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	memset(&flow_ctrl0, 0, sizeof(flow_ctrl0));
+
+	rv = hppe_flow_ctrl0_get(dev_id, &flow_ctrl0);
+	if( rv != SW_OK )
+		return rv;
+
+	flow_ctrl0.bf.flow_en = enable;
+	return hppe_flow_ctrl0_set(dev_id, &flow_ctrl0);
+}
+#endif
+
+sw_error_t
+adpt_hppe_flow_ctrl_get(
+		a_uint32_t dev_id,
+		fal_flow_pkt_type_t type,
+		fal_flow_direction_t dir,
+		fal_flow_mgmt_t *ctrl)
+{
+	sw_error_t rv = SW_OK;
+	union flow_ctrl1_u flow_ctrl1;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	memset(&flow_ctrl1, 0, sizeof(flow_ctrl1));
+	rv = hppe_flow_ctrl1_get(dev_id, type, &flow_ctrl1);
+	if( rv != SW_OK )
+		return rv;
+
+	if (dir == FAL_FLOW_LAN_TO_LAN_DIR) {
+		ctrl->miss_action = flow_ctrl1.bf.flow_ctl0_miss_action;
+		ctrl->frag_bypass_en = flow_ctrl1.bf.flow_ctl0_frag_bypass;
+		ctrl->tcp_spec_bypass_en = flow_ctrl1.bf.flow_ctl0_tcp_special;
+		ctrl->all_bypass_en = flow_ctrl1.bf.flow_ctl0_bypass;
+		ctrl->key_sel = flow_ctrl1.bf.flow_ctl0_key_sel;
+	} else if (dir == FAL_FLOW_LAN_TO_WAN_DIR) {
+		ctrl->miss_action = flow_ctrl1.bf.flow_ctl1_miss_action;
+		ctrl->frag_bypass_en = flow_ctrl1.bf.flow_ctl1_frag_bypass;
+		ctrl->tcp_spec_bypass_en = flow_ctrl1.bf.flow_ctl1_tcp_special;
+		ctrl->all_bypass_en = flow_ctrl1.bf.flow_ctl1_bypass;
+		ctrl->key_sel = flow_ctrl1.bf.flow_ctl1_key_sel;
+	} else if (dir == FAL_FLOW_WAN_TO_LAN_DIR) {
+		ctrl->miss_action = flow_ctrl1.bf.flow_ctl2_miss_action;
+		ctrl->frag_bypass_en = flow_ctrl1.bf.flow_ctl2_frag_bypass;
+		ctrl->tcp_spec_bypass_en = flow_ctrl1.bf.flow_ctl2_tcp_special;
+		ctrl->all_bypass_en = flow_ctrl1.bf.flow_ctl2_bypass;
+		ctrl->key_sel = flow_ctrl1.bf.flow_ctl2_key_sel;
+	} else if (dir == FAL_FLOW_WAN_TO_WAN_DIR) {
+		ctrl->miss_action = flow_ctrl1.bf.flow_ctl3_miss_action;
+		ctrl->frag_bypass_en = flow_ctrl1.bf.flow_ctl3_frag_bypass;
+		ctrl->tcp_spec_bypass_en = flow_ctrl1.bf.flow_ctl3_tcp_special;
+		ctrl->all_bypass_en = flow_ctrl1.bf.flow_ctl3_bypass;
+		ctrl->key_sel = flow_ctrl1.bf.flow_ctl3_key_sel;
+	} else if (dir == FAL_FLOW_UNKOWN_DIR_DIR) {
+		ctrl->miss_action = flow_ctrl1.bf.flow_ctl4_miss_action;
+		ctrl->frag_bypass_en = flow_ctrl1.bf.flow_ctl4_frag_bypass;
+		ctrl->tcp_spec_bypass_en = flow_ctrl1.bf.flow_ctl4_tcp_special;
+		ctrl->all_bypass_en = flow_ctrl1.bf.flow_ctl4_bypass;
+		ctrl->key_sel = flow_ctrl1.bf.flow_ctl4_key_sel;
+	} else
+		return SW_FAIL;
+
+	return SW_OK;
+}
+
+#ifndef IN_FLOW_MINI
+sw_error_t
+adpt_hppe_flow_age_timer_set(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer)
+{
+	sw_error_t rv = SW_OK;
+	union flow_ctrl0_u flow_ctrl0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(age_timer);
+
+	memset(&flow_ctrl0, 0, sizeof(flow_ctrl0));
+
+	rv = hppe_flow_ctrl0_get(dev_id, &flow_ctrl0);
+	if( rv != SW_OK )
+		return rv;
+
+	flow_ctrl0.bf.flow_age_timer = age_timer->age_time;
+	flow_ctrl0.bf.flow_age_timer_unit = age_timer->unit;
+	return hppe_flow_ctrl0_set(dev_id, &flow_ctrl0);
+}
+
+sw_error_t
+adpt_hppe_flow_entry_add(
+		a_uint32_t dev_id,
+		a_uint32_t add_mode, /*index or hash*/
+		fal_flow_entry_t *flow_entry)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t type = 0;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(flow_entry);
+
+	type = flow_entry->entry_type;
+	if ((type & FAL_FLOW_IP4_5TUPLE_ADDR) == FAL_FLOW_IP4_5TUPLE_ADDR) {
+		union in_flow_tbl_u entry;
+		entry.bf0.valid= 1;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf0.next_hop1 = flow_entry->snat_nexthop;
+			entry.bf0.l4_port1 = flow_entry->snat_srcport;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+			entry.bf3.l4_port2 = flow_entry->dnat_dstport;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf1.port_vp2 = flow_entry->bridge_port & 0xffffff;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4;
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20;
+		entry.bf0.l4_sport = flow_entry->src_port;
+		entry.bf0.l4_dport_0 = flow_entry->dst_port;
+		entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4;
+		rv = hppe_flow_ipv4_5tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry);
+	} else if ((type & FAL_FLOW_IP6_5TUPLE_ADDR) == FAL_FLOW_IP6_5TUPLE_ADDR) {
+		union in_flow_ipv6_5tuple_tbl_u entry;
+		entry.bf0.valid= 1;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf0.next_hop1 = flow_entry->snat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf1.port_vp2 = flow_entry->bridge_port & 0xffffff;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3];
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[2] << 12;
+		entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[1] << 12;
+		entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[0] << 12;
+		entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20;
+		entry.bf0.l4_sport = flow_entry->src_port;
+		entry.bf0.l4_dport_0 = flow_entry->dst_port;
+		entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4;
+		rv = hppe_flow_ipv6_5tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry);
+	} else if ((type & FAL_FLOW_IP4_3TUPLE_ADDR) == FAL_FLOW_IP4_3TUPLE_ADDR) {
+		union in_flow_3tuple_tbl_u entry;
+		entry.bf0.valid= 1;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf0.next_hop1 = flow_entry->snat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf1.port_vp2 = flow_entry->bridge_port & 0xffffff;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4;
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20;
+		entry.bf0.ip_protocol = flow_entry->ip_type;
+		rv = hppe_flow_ipv4_3tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry);
+	} else if ((type & FAL_FLOW_IP6_3TUPLE_ADDR) == FAL_FLOW_IP6_3TUPLE_ADDR) {
+		union in_flow_ipv6_3tuple_tbl_u entry;
+		entry.bf0.valid= 1;
+		entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6;
+		entry.bf0.host_addr_index_type = flow_entry->host_addr_type;
+		entry.bf0.host_addr_index = flow_entry->host_addr_index;
+		entry.bf0.protocol_type = flow_entry->protocol;
+		entry.bf0.age = flow_entry->age;
+		entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid;
+		entry.bf0.src_l3_if = flow_entry->src_intf_index;
+		entry.bf0.fwd_type = flow_entry->fwd_type;
+		if (flow_entry->fwd_type == FAL_FLOW_SNAT) {
+			entry.bf1.next_hop1 = flow_entry->snat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_DNAT) {
+			entry.bf3.next_hop2 = flow_entry->dnat_nexthop;
+		} else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) {
+			entry.bf2.next_hop3 = flow_entry->route_nexthop;
+			entry.bf2.port_vp_valid1= flow_entry->port_valid;
+			entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff;
+		} else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) {
+			entry.bf0.port_vp2 = flow_entry->bridge_port & 0xffffff;
+		}
+		entry.bf0.de_acce = flow_entry->deacclr_en;
+		entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en;
+		entry.bf0.syn_toggle = flow_entry->syn_toggle;
+		entry.bf0.pri_profile_0 = flow_entry->pri_profile;
+		entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1;
+		entry.bf0.service_code = flow_entry->sevice_code;
+		entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3];
+		entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[2] << 12;
+		entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[1] << 12;
+		entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\
+							flow_entry->flow_ip.ipv6.ul[0] << 12;
+		entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20;
+		entry.bf0.ip_protocol = flow_entry->ip_type;
+		rv = hppe_flow_ipv6_3tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry);
+	} else
+		return SW_FAIL;
+	if (rv == SW_OK) {
+		union eg_flow_tree_map_tbl_u eg_treemap;
+		eg_treemap.bf.tree_id = flow_entry->tree_id;
+		rv = hppe_eg_flow_tree_map_tbl_set(dev_id, flow_entry->entry_id, &eg_treemap);
+	}
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_flow_global_cfg_get(
+		a_uint32_t dev_id,
+		fal_flow_global_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+#if defined(CPPE)
+	a_uint32_t chip_ver = 0;
+	a_bool_t flow_cpy_escape = A_FALSE;
+#endif
+	union flow_ctrl0_u flow_ctrl0;
+	union l3_route_ctrl_u route_ctrl;
+	union l3_route_ctrl_ext_u route_ctrl_ext;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+	
+	memset(&flow_ctrl0, 0, sizeof(flow_ctrl0));
+	memset(&route_ctrl, 0, sizeof(route_ctrl));
+	memset(&route_ctrl_ext, 0, sizeof(route_ctrl_ext));
+
+	rv = hppe_flow_ctrl0_get(dev_id, &flow_ctrl0);
+	if( rv != SW_OK )
+		return rv;
+	rv = hppe_l3_route_ctrl_get(dev_id, &route_ctrl);
+	if( rv != SW_OK )
+		return rv;
+	rv = hppe_l3_route_ctrl_ext_get(dev_id, &route_ctrl_ext);
+	if( rv != SW_OK )
+		return rv;
+
+#if defined(CPPE)
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+		rv = adpt_cppe_flow_copy_escape_get(dev_id, &flow_cpy_escape);
+		SW_RTN_ON_ERROR(rv);
+		cfg->flow_mismatch_copy_escape_en = flow_cpy_escape;
+	}
+#endif
+
+	cfg->src_if_check_action= route_ctrl.bf.flow_src_if_check_cmd;
+	cfg->src_if_check_deacclr_en= route_ctrl.bf.flow_src_if_check_de_acce;
+	cfg->service_loop_en = route_ctrl_ext.bf.flow_service_code_loop_en;
+	cfg->service_loop_action = route_ctrl.bf.flow_service_code_loop;
+	cfg->service_loop_deacclr_en = route_ctrl.bf.flow_service_code_loop_de_acce;
+	cfg->flow_deacclr_action = route_ctrl.bf.flow_de_acce_cmd;
+	cfg->sync_mismatch_action = route_ctrl.bf.flow_sync_mismatch_cmd;
+	cfg->sync_mismatch_deacclr_en = route_ctrl.bf.flow_sync_mismatch_de_acce;
+	cfg->hash_mode_0 = flow_ctrl0.bf.flow_hash_mode_0;
+	cfg->hash_mode_1 = flow_ctrl0.bf.flow_hash_mode_1;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_flow_global_cfg_set(
+		a_uint32_t dev_id,
+		fal_flow_global_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+#if defined(CPPE)
+	a_uint32_t chip_ver = 0;
+#endif
+	union flow_ctrl0_u flow_ctrl0;
+	union l3_route_ctrl_u route_ctrl;
+	union l3_route_ctrl_ext_u route_ctrl_ext;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+	
+	memset(&flow_ctrl0, 0, sizeof(flow_ctrl0));
+	memset(&route_ctrl, 0, sizeof(route_ctrl));
+	memset(&route_ctrl_ext, 0, sizeof(route_ctrl_ext));
+
+	rv = hppe_flow_ctrl0_get(dev_id, &flow_ctrl0);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = hppe_l3_route_ctrl_get(dev_id, &route_ctrl);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = hppe_l3_route_ctrl_ext_get(dev_id, &route_ctrl_ext);
+	SW_RTN_ON_ERROR(rv);
+
+	route_ctrl.bf.flow_src_if_check_cmd = cfg->src_if_check_action;
+	route_ctrl.bf.flow_src_if_check_de_acce = cfg->src_if_check_deacclr_en;
+	route_ctrl_ext.bf.flow_service_code_loop_en = cfg->service_loop_en;
+	route_ctrl.bf.flow_service_code_loop = cfg->service_loop_action;
+	route_ctrl.bf.flow_service_code_loop_de_acce = cfg->service_loop_deacclr_en;
+	route_ctrl.bf.flow_de_acce_cmd = cfg->flow_deacclr_action;
+	route_ctrl.bf.flow_sync_mismatch_cmd = cfg->sync_mismatch_action;
+	route_ctrl.bf.flow_sync_mismatch_de_acce = cfg->sync_mismatch_deacclr_en;
+	flow_ctrl0.bf.flow_hash_mode_0 = cfg->hash_mode_0;
+	flow_ctrl0.bf.flow_hash_mode_1 = cfg->hash_mode_1;
+
+	rv = hppe_flow_ctrl0_set(dev_id, &flow_ctrl0);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = hppe_l3_route_ctrl_set(dev_id, &route_ctrl);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = hppe_l3_route_ctrl_ext_set(dev_id, &route_ctrl_ext);
+	SW_RTN_ON_ERROR(rv);
+
+#if defined(CPPE)
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+		rv = adpt_cppe_flow_copy_escape_set(dev_id,
+				cfg->flow_mismatch_copy_escape_en);
+		SW_RTN_ON_ERROR(rv);
+	}
+#endif
+
+	return SW_OK;
+}
+#endif
+
+void adpt_hppe_flow_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_flow_func_bitmap = 0;
+	return;
+}
+
+static void adpt_hppe_flow_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_flow_host_add = NULL;
+	p_adpt_api->adpt_flow_entry_get = NULL;
+	p_adpt_api->adpt_flow_entry_del = NULL;
+	p_adpt_api->adpt_flow_status_get = NULL;
+	p_adpt_api->adpt_flow_ctrl_set = NULL;
+	p_adpt_api->adpt_flow_age_timer_get = NULL;
+	p_adpt_api->adpt_flow_status_set = NULL;
+	p_adpt_api->adpt_flow_host_get = NULL;
+	p_adpt_api->adpt_flow_host_del = NULL;
+	p_adpt_api->adpt_flow_ctrl_get = NULL;
+	p_adpt_api->adpt_flow_age_timer_set = NULL;
+	p_adpt_api->adpt_flow_entry_add = NULL;
+	p_adpt_api->adpt_flow_global_cfg_get = NULL;
+	p_adpt_api->adpt_flow_global_cfg_set = NULL;
+	p_adpt_api->adpt_flow_entry_next = NULL;
+
+	return;
+}
+
+sw_error_t adpt_hppe_flow_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_flow_func_unregister(dev_id, p_adpt_api);
+
+#ifndef IN_FLOW_MINI
+	if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_HOST_ADD))
+		p_adpt_api->adpt_flow_host_add = adpt_hppe_flow_host_add;
+	if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_ENTRY_GET))
+		p_adpt_api->adpt_flow_entry_get = adpt_hppe_flow_entry_get;
+	if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_ENTRY_DEL))
+		p_adpt_api->adpt_flow_entry_del = adpt_hppe_flow_entry_del;
+	if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_STATUS_GET))
+		p_adpt_api->adpt_flow_status_get = adpt_hppe_flow_status_get;
+	if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_AGE_TIMER_GET))
+		p_adpt_api->adpt_flow_age_timer_get = adpt_hppe_flow_age_timer_get;
+	if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_STATUS_SET))
+		p_adpt_api->adpt_flow_status_set = adpt_hppe_flow_status_set;
+	if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_HOST_GET))
+		p_adpt_api->adpt_flow_host_get = adpt_hppe_flow_host_get;
+	if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_HOST_DEL))
+		p_adpt_api->adpt_flow_host_del = adpt_hppe_flow_host_del;
+	if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_AGE_TIMER_SET))
+		p_adpt_api->adpt_flow_age_timer_set = adpt_hppe_flow_age_timer_set;
+	if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_ENTRY_ADD))
+		p_adpt_api->adpt_flow_entry_add = adpt_hppe_flow_entry_add;
+	if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_GLOBAL_CFG_GET))
+		p_adpt_api->adpt_flow_global_cfg_get = adpt_hppe_flow_global_cfg_get;
+	if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_GLOBAL_CFG_SET))
+		p_adpt_api->adpt_flow_global_cfg_set = adpt_hppe_flow_global_cfg_set;
+	if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_ENTRY_NEXT))
+		p_adpt_api->adpt_flow_entry_next = adpt_hppe_flow_entry_next;
+#endif
+	if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_CTRL_GET))
+		p_adpt_api->adpt_flow_ctrl_get = adpt_hppe_flow_ctrl_get;
+	if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_CTRL_SET))
+		p_adpt_api->adpt_flow_ctrl_set = adpt_hppe_flow_ctrl_set;
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_ip.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_ip.c
new file mode 100755
index 0000000..f4a40dd
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_ip.c
@@ -0,0 +1,1355 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "fal_ip.h"
+#include "hppe_ip_reg.h"
+#include "hppe_ip.h"
+#include "adpt.h"
+
+#ifndef IN_IP_MINI
+sw_error_t
+adpt_hppe_ip_network_route_get(a_uint32_t dev_id,
+			a_uint32_t index, a_uint8_t type,
+			fal_network_route_entry_t *entry)
+{
+	sw_error_t rv = SW_OK;
+	union network_route_ip_u network_route_ip;
+	union network_route_ip_ext_u network_route_ip_ext;
+	union network_route_action_u network_route_action;
+	fal_ip6_addr_t ipv6, ipv6_mask;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+	memset(&network_route_ip, 0, sizeof(network_route_ip));
+	memset(&network_route_ip_ext, 0, sizeof(network_route_ip_ext));
+	memset(&network_route_action, 0, sizeof(network_route_action));
+
+	if (type > 1 || (type == 0 && index > 31) || (type == 1 && index > 7))
+		return SW_BAD_VALUE;
+
+	if (type == 0) {
+		rv = hppe_network_route_ip_get(dev_id, index,
+							&network_route_ip);
+		if( rv != SW_OK )
+			return rv;
+		rv = hppe_network_route_ip_ext_get(dev_id, index,
+							&network_route_ip_ext);
+		if( rv != SW_OK )
+			return rv;
+		rv = hppe_network_route_action_get(dev_id, index,
+							&network_route_action);
+		if( rv != SW_OK )
+			return rv;
+	} else {
+		rv = hppe_network_route_ip_get(dev_id, index * 4, &network_route_ip);
+		if( rv != SW_OK )
+			return rv;
+		ipv6.ul[3] = network_route_ip.val[0];
+		ipv6.ul[2] = network_route_ip.val[1];
+		rv = hppe_network_route_ip_get(dev_id, index * 4 + 1, &network_route_ip);
+		if( rv != SW_OK )
+			return rv;
+		ipv6.ul[1] = network_route_ip.val[0];
+		ipv6.ul[0] = network_route_ip.val[1];
+		rv = hppe_network_route_ip_get(dev_id, index * 4 + 2, &network_route_ip);
+		if( rv != SW_OK )
+			return rv;
+		ipv6_mask.ul[3] = network_route_ip.val[0];
+		ipv6_mask.ul[2] = network_route_ip.val[1];
+		rv = hppe_network_route_ip_get(dev_id, index * 4 + 3, &network_route_ip);
+		if( rv != SW_OK )
+			return rv;
+		ipv6_mask.ul[1] = network_route_ip.val[0];
+		ipv6_mask.ul[0] = network_route_ip.val[1];
+		rv = hppe_network_route_ip_ext_get(dev_id, index * 4,
+							&network_route_ip_ext);
+		if( rv != SW_OK )
+			return rv;
+		rv = hppe_network_route_action_get(dev_id, index * 4,
+							&network_route_action);
+		if( rv != SW_OK )
+			return rv;
+	}
+
+	if (!network_route_ip_ext.bf.valid)
+		return SW_FAIL;
+	entry->action = (fal_fwd_cmd_t)network_route_action.bf.fwd_cmd;
+	entry->lan_wan = network_route_action.bf.lan_wan;
+	entry->dst_info = network_route_action.bf.dst_info;
+	entry->type = network_route_ip_ext.bf.entry_type;
+	if (type == 0) {
+		entry->route_addr.ip4_addr = network_route_ip.bf.ip_addr;
+		entry->route_addr_mask.ip4_addr_mask = network_route_ip.bf.ip_addr_mask;
+	} else {
+		memcpy(&entry->route_addr.ip6_addr , &ipv6, sizeof(ipv6));
+		memcpy(&entry->route_addr_mask.ip6_addr_mask,
+							&ipv6_mask, sizeof(ipv6_mask));
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry)
+{
+	a_uint8_t mode = 0, type = 0;
+	sw_error_t rv = SW_OK;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(host_entry);
+
+	mode = host_entry->flags >> 24;
+	type = host_entry->flags & 0xff;
+
+	if ((type & FAL_IP_IP4_ADDR) == FAL_IP_IP4_ADDR) {
+		union host_tbl_u entry;
+		entry.bf.valid= host_entry->status;
+		entry.bf.key_type = 0;
+		entry.bf.fwd_cmd = host_entry->action;
+		entry.bf.syn_toggle = host_entry->syn_toggle;
+		entry.bf.dst_info = host_entry->dst_info;
+		entry.bf.lan_wan = host_entry->lan_wan;
+		entry.bf.ip_addr = host_entry->ip4_addr;
+		rv = hppe_host_ipv4_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+	} else if ((type & FAL_IP_IP6_ADDR) == FAL_IP_IP6_ADDR) {
+		union host_ipv6_tbl_u entry;
+		entry.bf.valid= host_entry->status;
+		entry.bf.key_type = 2;
+		entry.bf.fwd_cmd = host_entry->action;
+		entry.bf.syn_toggle = host_entry->syn_toggle;
+		entry.bf.dst_info = host_entry->dst_info;
+		entry.bf.lan_wan = host_entry->lan_wan;
+		entry.bf.ipv6_addr_0 = host_entry->ip6_addr.ul[3];
+		entry.bf.ipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 10 | \
+							host_entry->ip6_addr.ul[2] << 22;
+		entry.bf.ipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 10 | \
+							host_entry->ip6_addr.ul[1] << 22;
+		entry.bf.ipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 10 | \
+							host_entry->ip6_addr.ul[0] << 22;
+		entry.bf.ipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 10;
+		rv = hppe_host_ipv6_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+	} else if ((type & FAL_IP_IP4_ADDR_MCAST) == FAL_IP_IP4_ADDR_MCAST) {
+		union host_ipv4_mcast_tbl_u entry;
+		entry.bf.valid= host_entry->status;
+		entry.bf.key_type = 1;
+		entry.bf.fwd_cmd = host_entry->action;
+		entry.bf.syn_toggle = host_entry->syn_toggle;
+		entry.bf.dst_info = host_entry->dst_info;
+		entry.bf.lan_wan = host_entry->lan_wan;
+		entry.bf.gip_addr_0 = host_entry->ip4_addr;
+		entry.bf.gip_addr_1 = host_entry->ip4_addr >> 11;
+		entry.bf.vsi = host_entry->mcast_info.vsi;
+		entry.bf.sip_addr_0 = host_entry->mcast_info.sip4_addr;
+		entry.bf.sip_addr_1 = host_entry->mcast_info.sip4_addr >> 11;
+		rv = hppe_host_ipv4_mcast_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+	} else if ((type & FAL_IP_IP6_ADDR_MCAST) == FAL_IP_IP6_ADDR_MCAST) {
+		union host_ipv6_mcast_tbl_u entry;
+		entry.bf.valid= host_entry->status;
+		entry.bf.key_type = 3;
+		entry.bf.fwd_cmd = host_entry->action;
+		entry.bf.syn_toggle = host_entry->syn_toggle;
+		entry.bf.dst_info = host_entry->dst_info;
+		entry.bf.lan_wan = host_entry->lan_wan;
+		entry.bf.gipv6_addr_0 = host_entry->ip6_addr.ul[3];
+		entry.bf.gipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 20 | \
+							host_entry->ip6_addr.ul[2] << 12;
+		entry.bf.gipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 20 | \
+							host_entry->ip6_addr.ul[1] << 12;
+		entry.bf.gipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 20 | \
+							host_entry->ip6_addr.ul[0] << 12;
+		entry.bf.gipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 20;
+		entry.bf.vsi = host_entry->mcast_info.vsi;
+		entry.bf.sipv6_addr_0 = host_entry->mcast_info.sip6_addr.ul[3];
+		entry.bf.sipv6_addr_1 = host_entry->mcast_info.sip6_addr.ul[3] >> 20 | \
+							host_entry->mcast_info.sip6_addr.ul[2] << 12;
+		entry.bf.sipv6_addr_2 = host_entry->mcast_info.sip6_addr.ul[2] >> 20 | \
+							host_entry->mcast_info.sip6_addr.ul[1] << 12;
+		entry.bf.sipv6_addr_3 = host_entry->mcast_info.sip6_addr.ul[1] >> 20 | \
+							host_entry->mcast_info.sip6_addr.ul[0] << 12;
+		entry.bf.sipv6_addr_4 = host_entry->mcast_info.sip6_addr.ul[0] >> 20;
+		rv = hppe_host_ipv6_mcast_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+	}
+	return rv;
+}
+sw_error_t
+adpt_hppe_ip_vsi_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_sg_cfg_t *sg_cfg)
+{
+	sw_error_t rv = SW_OK;
+	union l3_vsi_ext_u l3_vsi_ext;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(sg_cfg);
+	memset(&l3_vsi_ext, 0, sizeof(l3_vsi_ext));
+
+	rv = hppe_l3_vsi_ext_get(dev_id, vsi, &l3_vsi_ext);
+	if( rv != SW_OK )
+		return rv;
+
+	sg_cfg->ipv4_sg_en = l3_vsi_ext.bf.ipv4_sg_en;
+	sg_cfg->ipv4_sg_vio_action = l3_vsi_ext.bf.ipv4_sg_vio_cmd;
+	sg_cfg->ipv4_sg_port_en = l3_vsi_ext.bf.ipv4_sg_port_en;
+	sg_cfg->ipv4_sg_svlan_en = l3_vsi_ext.bf.ipv4_sg_svlan_en;
+	sg_cfg->ipv4_sg_cvlan_en = l3_vsi_ext.bf.ipv4_sg_cvlan_en;
+	sg_cfg->ipv4_src_unk_action = l3_vsi_ext.bf.ipv4_src_unk_cmd;
+	sg_cfg->ipv6_sg_en = l3_vsi_ext.bf.ipv6_sg_en;
+	sg_cfg->ipv6_sg_vio_action = l3_vsi_ext.bf.ipv6_sg_vio_cmd;
+	sg_cfg->ipv6_sg_port_en = l3_vsi_ext.bf.ipv6_sg_port_en;
+	sg_cfg->ipv6_sg_svlan_en = l3_vsi_ext.bf.ipv6_sg_svlan_en;
+	sg_cfg->ipv6_sg_cvlan_en = l3_vsi_ext.bf.ipv6_sg_cvlan_en;
+	sg_cfg->ipv6_src_unk_action = l3_vsi_ext.bf.ipv6_src_unk_cmd;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_port_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_sg_cfg_t *sg_cfg)
+{
+	union l3_vp_port_tbl_u l3_vp_port_tbl;
+
+	memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl);
+
+	l3_vp_port_tbl.bf.ipv4_sg_en = sg_cfg->ipv4_sg_en;
+	l3_vp_port_tbl.bf.ipv4_sg_vio_cmd = sg_cfg->ipv4_sg_vio_action;
+	l3_vp_port_tbl.bf.ipv4_sg_port_en = sg_cfg->ipv4_sg_port_en;
+	l3_vp_port_tbl.bf.ipv4_sg_svlan_en = sg_cfg->ipv4_sg_svlan_en;
+	l3_vp_port_tbl.bf.ipv4_sg_cvlan_en = sg_cfg->ipv4_sg_cvlan_en;
+	l3_vp_port_tbl.bf.ipv4_src_unk_cmd = sg_cfg->ipv4_src_unk_action;
+	l3_vp_port_tbl.bf.ipv6_sg_en = sg_cfg->ipv6_sg_en;
+	l3_vp_port_tbl.bf.ipv6_sg_vio_cmd = sg_cfg->ipv6_sg_vio_action;
+	l3_vp_port_tbl.bf.ipv6_sg_port_en = sg_cfg->ipv6_sg_port_en;
+	l3_vp_port_tbl.bf.ipv6_sg_svlan_en = sg_cfg->ipv6_sg_svlan_en;
+	l3_vp_port_tbl.bf.ipv6_sg_cvlan_en = sg_cfg->ipv6_sg_cvlan_en;
+	l3_vp_port_tbl.bf.ipv6_src_unk_cmd = sg_cfg->ipv6_src_unk_action;
+	
+	return hppe_l3_vp_port_tbl_set(dev_id, port_id, &l3_vp_port_tbl);
+}
+sw_error_t
+adpt_hppe_ip_port_intf_get(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id)
+{
+	sw_error_t rv = SW_OK;
+	union l3_vp_port_tbl_u l3_vp_port_tbl;
+
+	memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(id);
+
+	rv = hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	id->l3_if_valid = l3_vp_port_tbl.bf.l3_if_valid;
+	id->l3_if_index = l3_vp_port_tbl.bf.l3_if_index;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_vsi_arp_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_arp_sg_cfg_t *arp_sg_cfg)
+{
+	union l3_vsi_ext_u l3_vsi_ext;
+
+	memset(&l3_vsi_ext, 0, sizeof(l3_vsi_ext));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_l3_vsi_ext_get(dev_id, vsi, &l3_vsi_ext);
+
+	l3_vsi_ext.bf.ip_arp_sg_en = arp_sg_cfg->ipv4_arp_sg_en;
+	l3_vsi_ext.bf.ip_arp_sg_vio_cmd = arp_sg_cfg->ipv4_arp_sg_vio_action;
+	l3_vsi_ext.bf.ip_arp_sg_port_en = arp_sg_cfg->ipv4_arp_sg_port_en;
+	l3_vsi_ext.bf.ip_arp_sg_svlan_en = arp_sg_cfg->ipv4_arp_sg_svlan_en;
+	l3_vsi_ext.bf.ip_arp_sg_cvlan_en = arp_sg_cfg->ipv4_arp_sg_cvlan_en;
+	l3_vsi_ext.bf.ip_arp_src_unk_cmd = arp_sg_cfg->ipv4_arp_src_unk_action;
+	l3_vsi_ext.bf.ip_nd_sg_en = arp_sg_cfg->ip_nd_sg_en;
+	l3_vsi_ext.bf.ip_nd_sg_vio_cmd = arp_sg_cfg->ip_nd_sg_vio_action;
+	l3_vsi_ext.bf.ip_nd_sg_port_en = arp_sg_cfg->ip_nd_sg_port_en;
+	l3_vsi_ext.bf.ip_nd_sg_svlan_en = arp_sg_cfg->ip_nd_sg_svlan_en;
+	l3_vsi_ext.bf.ip_nd_sg_cvlan_en = arp_sg_cfg->ip_nd_sg_cvlan_en;
+	l3_vsi_ext.bf.ip_nd_src_unk_cmd = arp_sg_cfg->ip_nd_src_unk_action;
+	
+	return hppe_l3_vsi_ext_set(dev_id, vsi, &l3_vsi_ext);
+}
+sw_error_t
+adpt_hppe_ip_pub_addr_get(a_uint32_t dev_id,
+		a_uint32_t index, fal_ip_pub_addr_t *entry)
+{
+	sw_error_t rv = SW_OK;
+	union in_pub_ip_addr_tbl_u in_pub_ip_addr_tbl;
+
+	memset(&in_pub_ip_addr_tbl, 0, sizeof(in_pub_ip_addr_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	rv = hppe_in_pub_ip_addr_tbl_get(dev_id, index, &in_pub_ip_addr_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	entry->pub_ip_addr = in_pub_ip_addr_tbl.bf.ip_addr;
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_port_intf_set(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id)
+{
+	union l3_vp_port_tbl_u l3_vp_port_tbl;
+
+	memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl);
+
+	l3_vp_port_tbl.bf.l3_if_valid = id->l3_if_valid;
+	l3_vp_port_tbl.bf.l3_if_index = id->l3_if_index;
+	
+	return hppe_l3_vp_port_tbl_set(dev_id, port_id, &l3_vp_port_tbl);
+}
+
+sw_error_t
+adpt_hppe_ip_vsi_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_sg_cfg_t *sg_cfg)
+{
+	union l3_vsi_ext_u l3_vsi_ext;
+
+	memset(&l3_vsi_ext, 0, sizeof(l3_vsi_ext));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_l3_vsi_ext_get(dev_id, vsi, &l3_vsi_ext);
+
+	l3_vsi_ext.bf.ipv4_sg_en = sg_cfg->ipv4_sg_en;
+	l3_vsi_ext.bf.ipv4_sg_vio_cmd = sg_cfg->ipv4_sg_vio_action;
+	l3_vsi_ext.bf.ipv4_sg_port_en = sg_cfg->ipv4_sg_port_en;
+	l3_vsi_ext.bf.ipv4_sg_svlan_en = sg_cfg->ipv4_sg_svlan_en;
+	l3_vsi_ext.bf.ipv4_sg_cvlan_en = sg_cfg->ipv4_sg_cvlan_en;
+	l3_vsi_ext.bf.ipv4_src_unk_cmd = sg_cfg->ipv4_src_unk_action;
+	l3_vsi_ext.bf.ipv6_sg_en = sg_cfg->ipv6_sg_en;
+	l3_vsi_ext.bf.ipv6_sg_vio_cmd = sg_cfg->ipv6_sg_vio_action;
+	l3_vsi_ext.bf.ipv6_sg_port_en = sg_cfg->ipv6_sg_port_en;
+	l3_vsi_ext.bf.ipv6_sg_svlan_en = sg_cfg->ipv6_sg_svlan_en;
+	l3_vsi_ext.bf.ipv6_sg_cvlan_en = sg_cfg->ipv6_sg_cvlan_en;
+	l3_vsi_ext.bf.ipv6_src_unk_cmd = sg_cfg->ipv6_src_unk_action;
+	
+	return hppe_l3_vsi_ext_set(dev_id, vsi, &l3_vsi_ext);
+}
+sw_error_t
+adpt_hppe_ip_port_macaddr_set(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_macaddr_entry_t *macaddr)
+{
+	union l3_vp_port_tbl_u l3_vp_port_tbl;
+
+	memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl);
+
+	l3_vp_port_tbl.bf.mac_valid = macaddr->valid;
+	l3_vp_port_tbl.bf.mac_da_0 =  macaddr->mac_addr.uc[4] << 8 | \
+							macaddr->mac_addr.uc[5];
+	l3_vp_port_tbl.bf.mac_da_1 =  macaddr->mac_addr.uc[0] << 24 | \
+							macaddr->mac_addr.uc[1] << 16 | \
+							macaddr->mac_addr.uc[2] << 8 | \
+							macaddr->mac_addr.uc[3];
+	
+	return hppe_l3_vp_port_tbl_set(dev_id, port_id, &l3_vp_port_tbl);
+}
+sw_error_t
+adpt_hppe_ip_vsi_intf_get(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id)
+{
+	sw_error_t rv = SW_OK;
+	union l3_vsi_u l3_vsi;
+
+	memset(&l3_vsi, 0, sizeof(l3_vsi));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(id);
+
+
+	rv = hppe_l3_vsi_get(dev_id, vsi, &l3_vsi);
+
+	if( rv != SW_OK )
+		return rv;
+
+	id->l3_if_valid = l3_vsi.bf.l3_if_valid;
+	id->l3_if_index = l3_vsi.bf.l3_if_index;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_network_route_add(a_uint32_t dev_id,
+			a_uint32_t index,
+			fal_network_route_entry_t *entry)
+{
+	union network_route_ip_u network_route_ip;
+	union network_route_ip_ext_u network_route_ip_ext;
+	union network_route_action_u network_route_action;
+
+	memset(&network_route_ip, 0, sizeof(network_route_ip));
+	memset(&network_route_ip_ext, 0, sizeof(network_route_ip_ext));
+	memset(&network_route_action, 0, sizeof(network_route_action));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	if (entry->type > 1 || (entry->type == 0 && index > 31) || (entry->type == 1 && index > 7))
+		return SW_BAD_VALUE;
+
+	if (entry->type == 0) {
+		network_route_ip.bf.ip_addr = entry->route_addr.ip4_addr;
+		network_route_ip.bf.ip_addr_mask = entry->route_addr_mask.ip4_addr_mask;
+		network_route_ip_ext.bf.valid = 1;
+		network_route_ip_ext.bf.entry_type = entry->type;
+		network_route_action.bf.dst_info = entry->dst_info;
+		network_route_action.bf.fwd_cmd = entry->action;
+		network_route_action.bf.lan_wan = entry->lan_wan;
+		hppe_network_route_ip_set(dev_id, index, &network_route_ip);
+		hppe_network_route_ip_ext_set(dev_id, index, &network_route_ip_ext);
+		hppe_network_route_action_set(dev_id, index, &network_route_action);
+	} else {
+		network_route_ip_ext.bf.valid = 1;
+		network_route_ip_ext.bf.entry_type = entry->type;
+		network_route_action.bf.dst_info = entry->dst_info;
+		network_route_action.bf.fwd_cmd = entry->action;
+		network_route_action.bf.lan_wan = entry->lan_wan;
+		hppe_network_route_ip_ext_set(dev_id, index * 4, &network_route_ip_ext);
+		hppe_network_route_action_set(dev_id, index * 4, &network_route_action);
+		network_route_ip.bf.ip_addr = entry->route_addr.ip6_addr.ul[3];
+		network_route_ip.bf.ip_addr_mask = entry->route_addr.ip6_addr.ul[2];
+		hppe_network_route_ip_set(dev_id, index * 4, &network_route_ip);
+		network_route_ip.bf.ip_addr = entry->route_addr.ip6_addr.ul[1];
+		network_route_ip.bf.ip_addr_mask = entry->route_addr.ip6_addr.ul[0];
+		hppe_network_route_ip_set(dev_id, index * 4 + 1, &network_route_ip);
+		network_route_ip.bf.ip_addr = entry->route_addr_mask.ip6_addr_mask.ul[3];
+		network_route_ip.bf.ip_addr_mask = entry->route_addr_mask.ip6_addr_mask.ul[2];
+		hppe_network_route_ip_set(dev_id, index * 4 + 2, &network_route_ip);
+		network_route_ip.bf.ip_addr = entry->route_addr_mask.ip6_addr_mask.ul[1];
+		network_route_ip.bf.ip_addr_mask = entry->route_addr_mask.ip6_addr_mask.ul[0];
+		hppe_network_route_ip_set(dev_id, index * 4 + 3, &network_route_ip);
+	}
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_network_route_del(a_uint32_t dev_id,
+			a_uint32_t index, a_uint8_t type)
+{
+	union network_route_ip_u network_route_ip;
+	union network_route_ip_ext_u network_route_ip_ext;
+	union network_route_action_u network_route_action;
+
+	memset(&network_route_ip, 0, sizeof(network_route_ip));
+	memset(&network_route_ip_ext, 0, sizeof(network_route_ip_ext));
+	memset(&network_route_action, 0, sizeof(network_route_action));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (type > 1 || (type == 0 && index > 31) || (type == 1 && index > 7))
+		return SW_BAD_VALUE;
+
+	network_route_ip_ext.bf.valid = 0;
+	if (type == 0) {
+		hppe_network_route_ip_ext_set(dev_id, index, &network_route_ip_ext);
+	} else {
+		hppe_network_route_ip_ext_set(dev_id, index * 4, &network_route_ip_ext);
+	}
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_port_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_sg_cfg_t *sg_cfg)
+{
+	sw_error_t rv = SW_OK;
+	union l3_vp_port_tbl_u l3_vp_port_tbl;
+
+	memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(sg_cfg);
+
+	rv = hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	sg_cfg->ipv4_sg_en = l3_vp_port_tbl.bf.ipv4_sg_en;
+	sg_cfg->ipv4_sg_vio_action= l3_vp_port_tbl.bf.ipv4_sg_vio_cmd;
+	sg_cfg->ipv4_sg_port_en = l3_vp_port_tbl.bf.ipv4_sg_port_en;
+	sg_cfg->ipv4_sg_svlan_en = l3_vp_port_tbl.bf.ipv4_sg_svlan_en;
+	sg_cfg->ipv4_sg_cvlan_en = l3_vp_port_tbl.bf.ipv4_sg_cvlan_en;
+	sg_cfg->ipv4_src_unk_action = l3_vp_port_tbl.bf.ipv4_src_unk_cmd;
+	sg_cfg->ipv6_sg_en = l3_vp_port_tbl.bf.ipv6_sg_en;
+	sg_cfg->ipv6_sg_vio_action = l3_vp_port_tbl.bf.ipv6_sg_vio_cmd;
+	sg_cfg->ipv6_sg_port_en = l3_vp_port_tbl.bf.ipv6_sg_port_en;
+	sg_cfg->ipv6_sg_svlan_en = l3_vp_port_tbl.bf.ipv6_sg_svlan_en;
+	sg_cfg->ipv6_sg_cvlan_en = l3_vp_port_tbl.bf.ipv6_sg_cvlan_en;
+	sg_cfg->ipv6_src_unk_action = l3_vp_port_tbl.bf.ipv6_src_unk_cmd;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_intf_get(
+    			a_uint32_t dev_id,
+    			a_uint32_t index,
+    			fal_intf_entry_t *entry)
+{
+	sw_error_t rv = SW_OK;
+	union in_l3_if_tbl_u in_l3_if_tbl;
+	union eg_l3_if_tbl_u eg_l3_if_tbl;
+
+	memset(&in_l3_if_tbl, 0, sizeof(in_l3_if_tbl));
+	memset(&eg_l3_if_tbl, 0, sizeof(eg_l3_if_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	rv = hppe_in_l3_if_tbl_get(dev_id, index, &in_l3_if_tbl);
+	if( rv != SW_OK )
+		return rv;
+	rv = hppe_eg_l3_if_tbl_get(dev_id, index, &eg_l3_if_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	entry->mru = in_l3_if_tbl.bf.mru;
+	entry->mtu = in_l3_if_tbl.bf.mtu;
+	entry->ttl_dec_bypass_en = in_l3_if_tbl.bf.ttl_dec_bypass;
+	entry->ipv4_uc_route_en = in_l3_if_tbl.bf.ipv4_uc_route_en;
+	entry->ipv6_uc_route_en = in_l3_if_tbl.bf.ipv6_uc_route_en;
+	entry->icmp_trigger_en = in_l3_if_tbl.bf.icmp_trigger_en;
+	entry->ttl_exceed_action = in_l3_if_tbl.bf.ttl_exceed_cmd;
+	entry->ttl_exceed_deacclr_en = in_l3_if_tbl.bf.ttl_exceed_de_acce;
+	entry->mac_addr_bitmap = in_l3_if_tbl.bf.mac_bitmap;
+	entry->mac_addr.uc[5] = eg_l3_if_tbl.bf.mac_addr_0;
+	entry->mac_addr.uc[4] = eg_l3_if_tbl.bf.mac_addr_0 >> 8;
+	entry->mac_addr.uc[3] = eg_l3_if_tbl.bf.mac_addr_0 >> 16;
+	entry->mac_addr.uc[2] = eg_l3_if_tbl.bf.mac_addr_0 >> 24;
+	entry->mac_addr.uc[1] = eg_l3_if_tbl.bf.mac_addr_1;
+	entry->mac_addr.uc[0] = eg_l3_if_tbl.bf.mac_addr_1 >> 8;
+
+	if (rv == SW_OK) {
+		union rt_interface_cnt_tbl_u cnt_ingress, cnt_egress;
+		hppe_rt_interface_cnt_tbl_get(dev_id, index, &cnt_ingress);
+		hppe_rt_interface_cnt_tbl_get(dev_id, index + 256, &cnt_egress);
+		entry->counter.rx_pkt_counter = cnt_ingress.bf.pkt_cnt;
+		entry->counter.rx_byte_counter = cnt_ingress.bf.byte_cnt_0 | ((a_uint64_t)cnt_ingress.bf.byte_cnt_1 << 32);
+		entry->counter.rx_drop_pkt_counter = cnt_ingress.bf.drop_pkt_cnt_0 | (cnt_ingress.bf.drop_pkt_cnt_1 << 24);
+		entry->counter.rx_drop_byte_counter = cnt_ingress.bf.drop_byte_cnt_0 | \
+								((a_uint64_t)cnt_ingress.bf.drop_byte_cnt_1 << 24);
+
+		entry->counter.tx_pkt_counter = cnt_egress.bf.pkt_cnt;
+		entry->counter.tx_byte_counter = cnt_egress.bf.byte_cnt_0 | ((a_uint64_t)cnt_egress.bf.byte_cnt_1 << 32);
+		entry->counter.tx_drop_pkt_counter = cnt_egress.bf.drop_pkt_cnt_0 | (cnt_egress.bf.drop_pkt_cnt_1 << 24);
+		entry->counter.tx_drop_byte_counter = cnt_egress.bf.drop_byte_cnt_0 | \
+								((a_uint64_t)cnt_egress.bf.drop_byte_cnt_1 << 24);
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_pub_addr_set(a_uint32_t dev_id,
+		a_uint32_t index, fal_ip_pub_addr_t *entry)
+{
+	union in_pub_ip_addr_tbl_u in_pub_ip_addr_tbl;
+
+	memset(&in_pub_ip_addr_tbl, 0, sizeof(in_pub_ip_addr_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	in_pub_ip_addr_tbl.bf.ip_addr = entry->pub_ip_addr;
+	return hppe_in_pub_ip_addr_tbl_set(dev_id, index, &in_pub_ip_addr_tbl);
+}
+
+sw_error_t
+adpt_hppe_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                    fal_host_entry_t * host_entry)
+{
+	a_uint8_t mode = 0, type = 0;
+	sw_error_t rv = SW_OK;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(host_entry);
+
+	mode = host_entry->flags >> 24;
+	type = host_entry->flags & 0xff;
+
+	if (del_mode & FAL_IP_ENTRY_ID_EN)
+		mode = 1;
+	else if (del_mode & FAL_IP_ENTRY_IPADDR_EN)
+		mode  = 0;
+	else if (del_mode & FAL_IP_ENTRY_ALL_EN) {
+		return hppe_host_flush_common(dev_id);
+	}
+
+	if ((type & FAL_IP_IP4_ADDR) == FAL_IP_IP4_ADDR) {
+		union host_tbl_u entry;
+		entry.bf.valid= 1;
+		entry.bf.key_type = 0;
+		entry.bf.fwd_cmd = host_entry->action;
+		entry.bf.syn_toggle = host_entry->syn_toggle;
+		entry.bf.dst_info = host_entry->dst_info;
+		entry.bf.lan_wan = host_entry->lan_wan;
+		entry.bf.ip_addr = host_entry->ip4_addr;
+		rv = hppe_host_ipv4_del(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+	} else if ((type & FAL_IP_IP6_ADDR) == FAL_IP_IP6_ADDR) {
+		union host_ipv6_tbl_u entry;
+		entry.bf.valid= 1;
+		entry.bf.key_type = 2;
+		entry.bf.fwd_cmd = host_entry->action;
+		entry.bf.syn_toggle = host_entry->syn_toggle;
+		entry.bf.dst_info = host_entry->dst_info;
+		entry.bf.lan_wan = host_entry->lan_wan;
+		entry.bf.ipv6_addr_0 = host_entry->ip6_addr.ul[3];
+		entry.bf.ipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 10 | \
+							host_entry->ip6_addr.ul[2] << 22;
+		entry.bf.ipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 10 | \
+							host_entry->ip6_addr.ul[1] << 22;
+		entry.bf.ipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 10 | \
+							host_entry->ip6_addr.ul[0] << 22;
+		entry.bf.ipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 10;
+		rv = hppe_host_ipv6_del(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+	} else if ((type & FAL_IP_IP4_ADDR_MCAST) == FAL_IP_IP4_ADDR_MCAST) {
+		union host_ipv4_mcast_tbl_u entry;
+		entry.bf.valid= 1;
+		entry.bf.key_type = 1;
+		entry.bf.fwd_cmd = host_entry->action;
+		entry.bf.syn_toggle = host_entry->syn_toggle;
+		entry.bf.dst_info = host_entry->dst_info;
+		entry.bf.lan_wan = host_entry->lan_wan;
+		entry.bf.gip_addr_0 = host_entry->ip4_addr;
+		entry.bf.gip_addr_1 = host_entry->ip4_addr >> 11;
+		entry.bf.vsi = host_entry->mcast_info.vsi;
+		entry.bf.sip_addr_0 = host_entry->mcast_info.sip4_addr;
+		entry.bf.sip_addr_1 = host_entry->mcast_info.sip4_addr >> 11;
+		rv = hppe_host_ipv4_mcast_del(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+	} else if ((type & FAL_IP_IP6_ADDR_MCAST) == FAL_IP_IP6_ADDR_MCAST) {
+		union host_ipv6_mcast_tbl_u entry;
+		entry.bf.valid= 1;
+		entry.bf.key_type = 3;
+		entry.bf.fwd_cmd = host_entry->action;
+		entry.bf.syn_toggle = host_entry->syn_toggle;
+		entry.bf.dst_info = host_entry->dst_info;
+		entry.bf.lan_wan = host_entry->lan_wan;
+		entry.bf.gipv6_addr_0 = host_entry->ip6_addr.ul[3];
+		entry.bf.gipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 20 | \
+							host_entry->ip6_addr.ul[2] << 12;
+		entry.bf.gipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 20 | \
+							host_entry->ip6_addr.ul[1] << 12;
+		entry.bf.gipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 20 | \
+							host_entry->ip6_addr.ul[0] << 12;
+		entry.bf.gipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 20;
+		entry.bf.vsi = host_entry->mcast_info.vsi;
+		entry.bf.sipv6_addr_0 = host_entry->mcast_info.sip6_addr.ul[3];
+		entry.bf.sipv6_addr_1 = host_entry->mcast_info.sip6_addr.ul[3] >> 20 | \
+							host_entry->mcast_info.sip6_addr.ul[2] << 12;
+		entry.bf.sipv6_addr_2 = host_entry->mcast_info.sip6_addr.ul[2] >> 20 | \
+							host_entry->mcast_info.sip6_addr.ul[1] << 12;
+		entry.bf.sipv6_addr_3 = host_entry->mcast_info.sip6_addr.ul[1] >> 20 | \
+							host_entry->mcast_info.sip6_addr.ul[0] << 12;
+		entry.bf.sipv6_addr_4 = host_entry->mcast_info.sip6_addr.ul[0] >> 20;
+		rv = hppe_host_ipv6_mcast_del(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+	}
+	return rv;
+}
+sw_error_t
+adpt_hppe_ip_route_mismatch_get(a_uint32_t dev_id, fal_fwd_cmd_t *cmd)
+{
+	sw_error_t rv = SW_OK;
+	union l3_route_ctrl_ext_u l3_route_ctrl_ext;
+
+	memset(&l3_route_ctrl_ext, 0, sizeof(l3_route_ctrl_ext));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cmd);
+
+	rv = hppe_l3_route_ctrl_ext_get(dev_id, &l3_route_ctrl_ext);
+	if( rv != SW_OK )
+		return rv;
+
+	*cmd = (fal_fwd_cmd_t)l3_route_ctrl_ext.bf.ip_route_mismatch;
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ip_vsi_arp_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_arp_sg_cfg_t *arp_sg_cfg)
+{
+	sw_error_t rv = SW_OK;
+	union l3_vsi_ext_u l3_vsi_ext;
+
+	memset(&l3_vsi_ext, 0, sizeof(l3_vsi_ext));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(arp_sg_cfg);
+
+	rv = hppe_l3_vsi_ext_get(dev_id, vsi, &l3_vsi_ext);
+	if( rv != SW_OK )
+		return rv;
+
+	arp_sg_cfg->ipv4_arp_sg_en = l3_vsi_ext.bf.ip_arp_sg_en;
+	arp_sg_cfg->ipv4_arp_sg_vio_action = l3_vsi_ext.bf.ip_arp_sg_vio_cmd;
+	arp_sg_cfg->ipv4_arp_sg_port_en = l3_vsi_ext.bf.ip_arp_sg_port_en;
+	arp_sg_cfg->ipv4_arp_sg_svlan_en = l3_vsi_ext.bf.ip_arp_sg_svlan_en;
+	arp_sg_cfg->ipv4_arp_sg_cvlan_en = l3_vsi_ext.bf.ip_arp_sg_cvlan_en;
+	arp_sg_cfg->ipv4_arp_src_unk_action = l3_vsi_ext.bf.ip_arp_src_unk_cmd;
+	arp_sg_cfg->ip_nd_sg_en = l3_vsi_ext.bf.ip_nd_sg_en;
+	arp_sg_cfg->ip_nd_sg_vio_action = l3_vsi_ext.bf.ip_nd_sg_vio_cmd;
+	arp_sg_cfg->ip_nd_sg_port_en = l3_vsi_ext.bf.ip_nd_sg_port_en;
+	arp_sg_cfg->ip_nd_sg_svlan_en = l3_vsi_ext.bf.ip_nd_sg_svlan_en;
+	arp_sg_cfg->ip_nd_sg_cvlan_en = l3_vsi_ext.bf.ip_nd_sg_cvlan_en;
+	arp_sg_cfg->ip_nd_src_unk_action = l3_vsi_ext.bf.ip_nd_src_unk_cmd;
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ip_port_arp_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_arp_sg_cfg_t *arp_sg_cfg)
+{
+	union l3_vp_port_tbl_u l3_vp_port_tbl;
+
+	memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl);
+
+	l3_vp_port_tbl.bf.ip_arp_sg_en = arp_sg_cfg->ipv4_arp_sg_en;
+	l3_vp_port_tbl.bf.ip_arp_sg_vio_cmd = arp_sg_cfg->ipv4_arp_sg_vio_action;
+	l3_vp_port_tbl.bf.ip_arp_sg_port_en = arp_sg_cfg->ipv4_arp_sg_port_en;
+	l3_vp_port_tbl.bf.ip_arp_sg_svlan_en = arp_sg_cfg->ipv4_arp_sg_svlan_en;
+	l3_vp_port_tbl.bf.ip_arp_sg_cvlan_en = arp_sg_cfg->ipv4_arp_sg_cvlan_en;
+	l3_vp_port_tbl.bf.ip_arp_src_unk_cmd = arp_sg_cfg->ipv4_arp_src_unk_action;
+	l3_vp_port_tbl.bf.ip_nd_sg_en = arp_sg_cfg->ip_nd_sg_en;
+	l3_vp_port_tbl.bf.ip_nd_sg_vio_cmd = arp_sg_cfg->ip_nd_sg_vio_action;
+	l3_vp_port_tbl.bf.ip_nd_sg_port_en = arp_sg_cfg->ip_nd_sg_port_en;
+	l3_vp_port_tbl.bf.ip_nd_sg_svlan_en = arp_sg_cfg->ip_nd_sg_svlan_en;
+	l3_vp_port_tbl.bf.ip_nd_sg_cvlan_en = arp_sg_cfg->ip_nd_sg_cvlan_en;
+	l3_vp_port_tbl.bf.ip_nd_src_unk_cmd = arp_sg_cfg->ip_nd_src_unk_action;
+	
+	return hppe_l3_vp_port_tbl_set(dev_id, port_id, &l3_vp_port_tbl);
+}
+sw_error_t
+adpt_hppe_ip_vsi_mc_mode_set(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_mc_mode_cfg_t *cfg)
+{
+	union l3_vsi_u l3_vsi;
+
+	memset(&l3_vsi, 0, sizeof(l3_vsi));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_l3_vsi_get(dev_id, vsi, &l3_vsi);
+
+	l3_vsi.bf.l2_ipv4_mc_en = cfg->l2_ipv4_mc_en;
+	l3_vsi.bf.l2_ipv4_mc_mode = cfg->l2_ipv4_mc_mode;
+	l3_vsi.bf.l2_ipv6_mc_en = cfg->l2_ipv6_mc_en;
+	l3_vsi.bf.l2_ipv6_mc_mode = cfg->l2_ipv6_mc_mode;
+	
+	return hppe_l3_vsi_set(dev_id, vsi, &l3_vsi);
+}
+
+sw_error_t
+adpt_hppe_ip_vsi_intf_set(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id)
+{
+	union l3_vsi_u l3_vsi;
+
+	memset(&l3_vsi, 0, sizeof(l3_vsi));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_l3_vsi_get(dev_id, vsi, &l3_vsi);
+
+	l3_vsi.bf.l3_if_valid = id->l3_if_valid;
+	l3_vsi.bf.l3_if_index = id->l3_if_index;
+	
+	return hppe_l3_vsi_set(dev_id, vsi, &l3_vsi);
+}
+
+sw_error_t
+adpt_hppe_ip_nexthop_get(a_uint32_t dev_id,
+		a_uint32_t index, fal_ip_nexthop_t *entry)
+{
+	sw_error_t rv = SW_OK;
+	union in_nexthop_tbl_u in_nexthop_tbl;
+
+	memset(&in_nexthop_tbl, 0, sizeof(in_nexthop_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	rv = hppe_in_nexthop_tbl_get(dev_id, index, &in_nexthop_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	entry->type = in_nexthop_tbl.bf0.type;
+	entry->vsi = in_nexthop_tbl.bf1.vsi;
+	entry->port = in_nexthop_tbl.bf0.port;
+	entry->if_index = in_nexthop_tbl.bf0.post_l3_if;
+	entry->ip_to_me_en = in_nexthop_tbl.bf0.ip_to_me;
+	entry->pub_ip_index = in_nexthop_tbl.bf1.ip_pub_addr_index;
+	entry->stag_fmt = in_nexthop_tbl.bf0.stag_fmt;
+	entry->svid = in_nexthop_tbl.bf0.svid;
+	entry->ctag_fmt = in_nexthop_tbl.bf0.ctag_fmt;
+	entry->cvid = in_nexthop_tbl.bf0.cvid;
+	entry->mac_addr.uc[5] = in_nexthop_tbl.bf1.mac_addr_0;
+	entry->mac_addr.uc[4] = in_nexthop_tbl.bf1.mac_addr_0 >> 8;
+	entry->mac_addr.uc[3] = in_nexthop_tbl.bf1.mac_addr_1;
+	entry->mac_addr.uc[2] = in_nexthop_tbl.bf1.mac_addr_1 >> 8;
+	entry->mac_addr.uc[1] = in_nexthop_tbl.bf1.mac_addr_1 >> 16;
+	entry->mac_addr.uc[0] = in_nexthop_tbl.bf1.mac_addr_1 >> 24;
+	entry->dnat_ip = in_nexthop_tbl.bf0.ip_addr_dnat;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_route_mismatch_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+	union l3_route_ctrl_ext_u l3_route_ctrl_ext;
+
+	memset(&l3_route_ctrl_ext, 0, sizeof(l3_route_ctrl_ext));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_l3_route_ctrl_ext_get(dev_id, &l3_route_ctrl_ext);
+	l3_route_ctrl_ext.bf.ip_route_mismatch = cmd;
+	
+	return hppe_l3_route_ctrl_ext_set(dev_id, &l3_route_ctrl_ext);
+}
+sw_error_t
+adpt_hppe_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                    fal_host_entry_t *host_entry)
+{
+	a_uint8_t mode = 0, type = 0;
+	sw_error_t rv = SW_OK;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(host_entry);
+
+	mode = host_entry->flags >> 24;
+	type = host_entry->flags & 0xff;
+
+	if (get_mode & FAL_IP_ENTRY_ID_EN)
+		mode = 1;
+	else if (get_mode & FAL_IP_ENTRY_IPADDR_EN)
+		mode  = 0;
+
+	if ((type & FAL_IP_IP4_ADDR) == FAL_IP_IP4_ADDR) {
+		union host_tbl_u entry;
+		entry.bf.key_type = 0;
+		entry.bf.ip_addr = host_entry->ip4_addr;
+		rv = hppe_host_ipv4_get(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+		if (!rv && (entry.bf.key_type != 0))
+			rv = SW_FAIL;
+		host_entry->ip4_addr = entry.bf.ip_addr;
+		host_entry->lan_wan = entry.bf.lan_wan;
+		host_entry->dst_info = entry.bf.dst_info;
+		host_entry->syn_toggle = entry.bf.syn_toggle;
+		host_entry->action = entry.bf.fwd_cmd;
+		host_entry->status = entry.bf.valid;
+	} else if ((type & FAL_IP_IP6_ADDR) == FAL_IP_IP6_ADDR) {
+		union host_ipv6_tbl_u entry;
+		entry.bf.key_type = 2;
+		entry.bf.ipv6_addr_0 = host_entry->ip6_addr.ul[3];
+		entry.bf.ipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 10 | \
+							host_entry->ip6_addr.ul[2] << 22;
+		entry.bf.ipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 10 | \
+							host_entry->ip6_addr.ul[1] << 22;
+		entry.bf.ipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 10 | \
+							host_entry->ip6_addr.ul[0] << 22;
+		entry.bf.ipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 10;
+		rv = hppe_host_ipv6_get(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+		if (!rv && (entry.bf.key_type != 2))
+			rv = SW_FAIL;
+		host_entry->ip6_addr.ul[3] = entry.bf.ipv6_addr_0 | entry.bf.ipv6_addr_1 << 10;
+		host_entry->ip6_addr.ul[2] = entry.bf.ipv6_addr_1 >> 22 | entry.bf.ipv6_addr_2 << 10;
+		host_entry->ip6_addr.ul[1] = entry.bf.ipv6_addr_2 >> 22 | entry.bf.ipv6_addr_3 << 10;
+		host_entry->ip6_addr.ul[0] = entry.bf.ipv6_addr_3 >> 22 | entry.bf.ipv6_addr_4 << 10;
+		host_entry->lan_wan = entry.bf.lan_wan;
+		host_entry->dst_info = entry.bf.dst_info;
+		host_entry->syn_toggle = entry.bf.syn_toggle;
+		host_entry->action = entry.bf.fwd_cmd;
+		host_entry->status = entry.bf.valid;
+	} else if ((type & FAL_IP_IP4_ADDR_MCAST) == FAL_IP_IP4_ADDR_MCAST) {
+		union host_ipv4_mcast_tbl_u entry;
+		entry.bf.key_type = 1;
+		entry.bf.gip_addr_0 = host_entry->ip4_addr;
+		entry.bf.gip_addr_1 = host_entry->ip4_addr >> 11;
+		entry.bf.vsi = host_entry->mcast_info.vsi;
+		entry.bf.sip_addr_0 = host_entry->mcast_info.sip4_addr;
+		entry.bf.sip_addr_1 = host_entry->mcast_info.sip4_addr >> 11;
+		rv = hppe_host_ipv4_mcast_get(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+		if (!rv && (entry.bf.key_type != 1))
+			rv = SW_FAIL;
+		host_entry->lan_wan = entry.bf.lan_wan;
+		host_entry->dst_info = entry.bf.dst_info;
+		host_entry->syn_toggle = entry.bf.syn_toggle;
+		host_entry->action = entry.bf.fwd_cmd;
+		host_entry->status = entry.bf.valid;
+		host_entry->ip4_addr = entry.bf.gip_addr_0 | entry.bf.gip_addr_1 << 11;
+		host_entry->mcast_info.vsi = entry.bf.vsi;
+		host_entry->mcast_info.sip4_addr = entry.bf.sip_addr_0 | entry.bf.sip_addr_1 << 11;
+	} else if ((type & FAL_IP_IP6_ADDR_MCAST) == FAL_IP_IP6_ADDR_MCAST) {
+		union host_ipv6_mcast_tbl_u entry;
+		entry.bf.key_type = 3;
+		entry.bf.vsi = host_entry->mcast_info.vsi;
+		entry.bf.gipv6_addr_0 = host_entry->ip6_addr.ul[3];
+		entry.bf.gipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 20 | \
+							host_entry->ip6_addr.ul[2] << 12;
+		entry.bf.gipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 20 | \
+							host_entry->ip6_addr.ul[1] << 12;
+		entry.bf.gipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 20 | \
+							host_entry->ip6_addr.ul[0] << 12;
+		entry.bf.gipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 20;
+		entry.bf.sipv6_addr_0 = host_entry->mcast_info.sip6_addr.ul[3];
+		entry.bf.sipv6_addr_1 = host_entry->mcast_info.sip6_addr.ul[3] >> 20 | \
+							host_entry->mcast_info.sip6_addr.ul[2] << 12;
+		entry.bf.sipv6_addr_2 = host_entry->mcast_info.sip6_addr.ul[2] >> 20 | \
+							host_entry->mcast_info.sip6_addr.ul[1] << 12;
+		entry.bf.sipv6_addr_3 = host_entry->mcast_info.sip6_addr.ul[1] >> 20 | \
+							host_entry->mcast_info.sip6_addr.ul[0] << 12;
+		entry.bf.sipv6_addr_4 = host_entry->mcast_info.sip6_addr.ul[0] >> 20;
+		rv = hppe_host_ipv6_mcast_get(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry);
+		if (!rv && (entry.bf.key_type != 3))
+			rv = SW_FAIL;
+		host_entry->lan_wan = entry.bf.lan_wan;
+		host_entry->dst_info = entry.bf.dst_info;
+		host_entry->syn_toggle = entry.bf.syn_toggle;
+		host_entry->action = entry.bf.fwd_cmd;
+		host_entry->status = entry.bf.valid;
+		host_entry->ip6_addr.ul[3] = entry.bf.gipv6_addr_0 | entry.bf.gipv6_addr_1 << 20;
+		host_entry->ip6_addr.ul[2] = entry.bf.gipv6_addr_1 >> 12 | entry.bf.gipv6_addr_2 << 20;
+		host_entry->ip6_addr.ul[1] = entry.bf.gipv6_addr_2 >> 12 | entry.bf.gipv6_addr_3 << 20;
+		host_entry->ip6_addr.ul[0] = entry.bf.gipv6_addr_3 >> 12 | entry.bf.gipv6_addr_4 << 20;
+		host_entry->mcast_info.vsi = entry.bf.vsi;
+		host_entry->mcast_info.sip6_addr.ul[3] = entry.bf.sipv6_addr_0 | entry.bf.sipv6_addr_1 << 20;
+		host_entry->mcast_info.sip6_addr.ul[2] = entry.bf.sipv6_addr_1 >> 12 | entry.bf.sipv6_addr_2 << 20;
+		host_entry->mcast_info.sip6_addr.ul[1] = entry.bf.sipv6_addr_2 >> 12 | entry.bf.sipv6_addr_3 << 20;
+		host_entry->mcast_info.sip6_addr.ul[0] = entry.bf.sipv6_addr_3 >> 12 | entry.bf.sipv6_addr_4 << 20;
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                     fal_host_entry_t * host_entry)
+{
+	a_uint32_t i = 0, step = 0;
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(host_entry);
+
+	if (FAL_NEXT_ENTRY_FIRST_ID == host_entry->entry_id)
+		i = 0;
+
+	if (next_mode == FAL_IP_IP6_ADDR_MCAST) {
+		if (FAL_NEXT_ENTRY_FIRST_ID != host_entry->entry_id)
+			i = (host_entry->entry_id & ~3) + 4;
+		step = 4;
+	} else if (next_mode == FAL_IP_IP4_ADDR_MCAST) {
+		if (FAL_NEXT_ENTRY_FIRST_ID != host_entry->entry_id)
+			i = (host_entry->entry_id & ~1) + 2;
+		step = 2;
+	} else if (next_mode == FAL_IP_IP4_ADDR) {
+		if (FAL_NEXT_ENTRY_FIRST_ID != host_entry->entry_id)
+			i = host_entry->entry_id + 1;
+		step = 1;
+	} else if (next_mode == FAL_IP_IP6_ADDR) {
+		if (FAL_NEXT_ENTRY_FIRST_ID != host_entry->entry_id)
+			i = (host_entry->entry_id & ~1) + 2;
+		step = 2;
+	}
+	for (; i < HOST_TBL_MAX_ENTRY;) {
+		host_entry->flags = next_mode;
+		host_entry->entry_id = i;
+		rv = adpt_hppe_ip_host_get(dev_id, FAL_IP_ENTRY_ID_EN, host_entry);
+		if (!rv) {
+			return rv;
+		}
+		i += step;
+	}
+
+	return SW_FAIL;
+
+}
+sw_error_t
+adpt_hppe_ip_intf_set(
+    			a_uint32_t dev_id,
+    			a_uint32_t index,
+    			fal_intf_entry_t *entry)
+{
+	union in_l3_if_tbl_u in_l3_if_tbl;
+	union eg_l3_if_tbl_u eg_l3_if_tbl;
+	a_uint8_t i = 0;
+
+	memset(&in_l3_if_tbl, 0, sizeof(in_l3_if_tbl));
+	memset(&eg_l3_if_tbl, 0, sizeof(eg_l3_if_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	in_l3_if_tbl.bf.mru = entry->mru;
+	in_l3_if_tbl.bf.mtu = entry->mtu;
+	in_l3_if_tbl.bf.ttl_dec_bypass = entry->ttl_dec_bypass_en;
+	in_l3_if_tbl.bf.ipv4_uc_route_en = entry->ipv4_uc_route_en;
+	in_l3_if_tbl.bf.ipv6_uc_route_en = entry->ipv6_uc_route_en;
+	in_l3_if_tbl.bf.icmp_trigger_en = entry->icmp_trigger_en;
+	in_l3_if_tbl.bf.ttl_exceed_cmd = entry->ttl_exceed_action;
+	in_l3_if_tbl.bf.ttl_exceed_de_acce = entry->ttl_exceed_deacclr_en;
+	in_l3_if_tbl.bf.mac_bitmap = entry->mac_addr_bitmap;
+	eg_l3_if_tbl.bf.mac_addr_0 = entry->mac_addr.uc[5] | \
+							entry->mac_addr.uc[4] << 8 | \
+							entry->mac_addr.uc[3] << 16 | \
+							entry->mac_addr.uc[2] << 24;
+	eg_l3_if_tbl.bf.mac_addr_1 = entry->mac_addr.uc[1] | \
+							entry->mac_addr.uc[0] << 8;
+
+	for (i = 0; i < 8; i++) {
+		if ((entry->mac_addr_bitmap >> i) & 0x1) {
+			union my_mac_tbl_u mymac;
+			mymac.bf.valid = 1;
+			mymac.bf.mac_da_0 = eg_l3_if_tbl.bf.mac_addr_0;
+			mymac.bf.mac_da_1 = eg_l3_if_tbl.bf.mac_addr_1;
+			hppe_my_mac_tbl_set(dev_id, i, &mymac);
+			break;
+		}
+	}
+	
+	hppe_in_l3_if_tbl_set(dev_id, index, &in_l3_if_tbl);
+	hppe_eg_l3_if_tbl_set(dev_id, index, &eg_l3_if_tbl);
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_vsi_mc_mode_get(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_mc_mode_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+	union l3_vsi_u l3_vsi;
+
+	memset(&l3_vsi, 0, sizeof(l3_vsi));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+
+	rv = hppe_l3_vsi_get(dev_id, vsi, &l3_vsi);
+	if( rv != SW_OK )
+		return rv;
+
+	cfg->l2_ipv4_mc_en = l3_vsi.bf.l2_ipv4_mc_en;
+	cfg->l2_ipv4_mc_mode = l3_vsi.bf.l2_ipv4_mc_mode;
+	cfg->l2_ipv6_mc_en = l3_vsi.bf.l2_ipv6_mc_en;
+	cfg->l2_ipv6_mc_mode = l3_vsi.bf.l2_ipv6_mc_mode;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_port_macaddr_get(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_macaddr_entry_t *macaddr)
+{
+	sw_error_t rv = SW_OK;
+	union l3_vp_port_tbl_u l3_vp_port_tbl;
+
+	memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(macaddr);
+
+	rv = hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	macaddr->valid = l3_vp_port_tbl.bf.mac_valid;
+	macaddr->mac_addr.uc[5] = l3_vp_port_tbl.bf.mac_da_0;
+	macaddr->mac_addr.uc[4] = l3_vp_port_tbl.bf.mac_da_0 >> 8;
+	macaddr->mac_addr.uc[3] = l3_vp_port_tbl.bf.mac_da_1;
+	macaddr->mac_addr.uc[2] = l3_vp_port_tbl.bf.mac_da_1 >> 8;
+	macaddr->mac_addr.uc[1] = l3_vp_port_tbl.bf.mac_da_1 >> 16;
+	macaddr->mac_addr.uc[0] = l3_vp_port_tbl.bf.mac_da_1 >> 24;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_port_arp_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_arp_sg_cfg_t *arp_sg_cfg)
+{
+	sw_error_t rv = SW_OK;
+	union l3_vp_port_tbl_u l3_vp_port_tbl;
+
+	memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(arp_sg_cfg);
+
+	rv = hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	arp_sg_cfg->ipv4_arp_sg_en = l3_vp_port_tbl.bf.ip_arp_sg_en;
+	arp_sg_cfg->ipv4_arp_sg_vio_action = l3_vp_port_tbl.bf.ip_arp_sg_vio_cmd;
+	arp_sg_cfg->ipv4_arp_sg_port_en = l3_vp_port_tbl.bf.ip_arp_sg_port_en;
+	arp_sg_cfg->ipv4_arp_sg_svlan_en = l3_vp_port_tbl.bf.ip_arp_sg_svlan_en;
+	arp_sg_cfg->ipv4_arp_sg_cvlan_en = l3_vp_port_tbl.bf.ip_arp_sg_cvlan_en;
+	arp_sg_cfg->ipv4_arp_src_unk_action = l3_vp_port_tbl.bf.ip_arp_src_unk_cmd;
+	arp_sg_cfg->ip_nd_sg_en = l3_vp_port_tbl.bf.ip_nd_sg_en;
+	arp_sg_cfg->ip_nd_sg_vio_action = l3_vp_port_tbl.bf.ip_nd_sg_vio_cmd;
+	arp_sg_cfg->ip_nd_sg_port_en = l3_vp_port_tbl.bf.ip_nd_sg_port_en;
+	arp_sg_cfg->ip_nd_sg_svlan_en = l3_vp_port_tbl.bf.ip_nd_sg_svlan_en;
+	arp_sg_cfg->ip_nd_sg_cvlan_en = l3_vp_port_tbl.bf.ip_nd_sg_cvlan_en;
+	arp_sg_cfg->ip_nd_src_unk_action = l3_vp_port_tbl.bf.ip_nd_src_unk_cmd;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_global_ctrl_get(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+	union l3_route_ctrl_u l3_route_ctrl;
+	union l3_route_ctrl_ext_u l3_route_ctrl_ext;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+	memset(&l3_route_ctrl, 0, sizeof(l3_route_ctrl));
+	memset(&l3_route_ctrl, 0, sizeof(l3_route_ctrl_ext));
+
+	rv = hppe_l3_route_ctrl_get(dev_id, &l3_route_ctrl);
+	if( rv != SW_OK )
+		return rv;
+
+	rv = hppe_l3_route_ctrl_ext_get(dev_id, &l3_route_ctrl_ext);
+	if( rv != SW_OK )
+		return rv;
+
+	cfg->mru_fail_action = l3_route_ctrl.bf.ip_mru_check_fail;
+	cfg->mru_deacclr_en = l3_route_ctrl.bf.ip_mru_check_fail_de_acce;
+	cfg->mtu_fail_action = l3_route_ctrl.bf.ip_mtu_fail;
+	cfg->mtu_deacclr_en = l3_route_ctrl.bf.ip_mtu_fail_de_acce;
+	cfg->mtu_nonfrag_fail_action = l3_route_ctrl.bf.ip_mtu_df_fail;
+	cfg->mtu_df_deacclr_en = l3_route_ctrl.bf.ip_mtu_df_fail_de_acce;
+	cfg->prefix_bc_action = l3_route_ctrl.bf.ip_prefix_bc_cmd;
+	cfg->prefix_deacclr_en = l3_route_ctrl.bf.ip_prefix_bc_de_acce;
+	cfg->icmp_rdt_action = l3_route_ctrl.bf.icmp_rdt_cmd;
+	cfg->icmp_rdt_deacclr_en = l3_route_ctrl.bf.icmp_rdt_de_acce;
+	cfg->hash_mode_0 = l3_route_ctrl_ext.bf.host_hash_mode_0;
+	cfg->hash_mode_1 = l3_route_ctrl_ext.bf.host_hash_mode_1;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_global_ctrl_set(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+	union l3_route_ctrl_u l3_route_ctrl;
+	union l3_route_ctrl_ext_u l3_route_ctrl_ext;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+	memset(&l3_route_ctrl, 0, sizeof(l3_route_ctrl));
+	memset(&l3_route_ctrl, 0, sizeof(l3_route_ctrl_ext));
+
+	rv = hppe_l3_route_ctrl_get(dev_id, &l3_route_ctrl);
+	if( rv != SW_OK )
+		return rv;
+
+	rv = hppe_l3_route_ctrl_ext_get(dev_id, &l3_route_ctrl_ext);
+	if( rv != SW_OK )
+		return rv;
+
+	l3_route_ctrl.bf.ip_mru_check_fail = cfg->mru_fail_action;
+	l3_route_ctrl.bf.ip_mru_check_fail_de_acce = cfg->mru_deacclr_en;
+	l3_route_ctrl.bf.ip_mtu_fail = cfg->mtu_fail_action;
+	l3_route_ctrl.bf.ip_mtu_fail_de_acce = cfg->mtu_deacclr_en;
+	l3_route_ctrl.bf.ip_mtu_df_fail = cfg->mtu_nonfrag_fail_action;
+	l3_route_ctrl.bf.ip_mtu_df_fail_de_acce = cfg->mtu_df_deacclr_en;
+	l3_route_ctrl.bf.ip_prefix_bc_cmd =cfg->prefix_bc_action;
+	l3_route_ctrl.bf.ip_prefix_bc_de_acce = cfg->prefix_deacclr_en;
+	l3_route_ctrl.bf.icmp_rdt_cmd = cfg->icmp_rdt_action;
+	l3_route_ctrl.bf.icmp_rdt_de_acce = cfg->icmp_rdt_deacclr_en;
+	l3_route_ctrl_ext.bf.host_hash_mode_0 = cfg->hash_mode_0;
+	l3_route_ctrl_ext.bf.host_hash_mode_1 = cfg->hash_mode_1;
+
+	hppe_l3_route_ctrl_set(dev_id, &l3_route_ctrl);
+	hppe_l3_route_ctrl_ext_set(dev_id, &l3_route_ctrl_ext);
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ip_nexthop_set(a_uint32_t dev_id,
+			a_uint32_t index, fal_ip_nexthop_t *entry)
+{
+	union in_nexthop_tbl_u in_nexthop_tbl;
+
+	memset(&in_nexthop_tbl, 0, sizeof(in_nexthop_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	in_nexthop_tbl.bf0.type = entry->type;
+	if (entry->type == 0)
+		in_nexthop_tbl.bf1.vsi = entry->vsi;
+	else
+		in_nexthop_tbl.bf0.port = entry->port;
+	in_nexthop_tbl.bf0.post_l3_if = entry->if_index;
+	in_nexthop_tbl.bf0.ip_to_me = entry->ip_to_me_en;
+	in_nexthop_tbl.bf0.ip_pub_addr_index = entry->pub_ip_index;
+	in_nexthop_tbl.bf0.stag_fmt = entry->stag_fmt;
+	in_nexthop_tbl.bf0.svid = entry->svid;
+	in_nexthop_tbl.bf0.ctag_fmt = entry->ctag_fmt;
+	in_nexthop_tbl.bf0.cvid = entry->cvid;
+	in_nexthop_tbl.bf0.mac_addr_0 = entry->mac_addr.uc[5] |
+					entry->mac_addr.uc[4] << 8;
+	in_nexthop_tbl.bf0.mac_addr_1 = entry->mac_addr.uc[3] |
+					entry->mac_addr.uc[2] << 8 |
+					entry->mac_addr.uc[1] << 16 |
+					entry->mac_addr.uc[0] << 24;
+	in_nexthop_tbl.bf0.ip_addr_dnat = entry->dnat_ip;
+
+	return hppe_in_nexthop_tbl_set(dev_id, index, &in_nexthop_tbl);
+}
+#endif
+void adpt_hppe_ip_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_ip_func_bitmap[0] = 0;
+	p_adpt_api->adpt_ip_func_bitmap[1] = 0;
+	return;
+}
+
+static void adpt_hppe_ip_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_ip_network_route_get = NULL;
+	p_adpt_api->adpt_ip_host_add = NULL;
+	p_adpt_api->adpt_ip_vsi_sg_cfg_get = NULL;
+	p_adpt_api->adpt_ip_pub_addr_set = NULL;
+	p_adpt_api->adpt_ip_port_sg_cfg_set = NULL;
+	p_adpt_api->adpt_ip_port_intf_get = NULL;
+	p_adpt_api->adpt_ip_vsi_arp_sg_cfg_set = NULL;
+	p_adpt_api->adpt_ip_pub_addr_get = NULL;
+	p_adpt_api->adpt_ip_port_intf_set = NULL;
+	p_adpt_api->adpt_ip_vsi_sg_cfg_set = NULL;
+	p_adpt_api->adpt_ip_host_next = NULL;
+	p_adpt_api->adpt_ip_port_macaddr_set = NULL;
+	p_adpt_api->adpt_ip_vsi_intf_get = NULL;
+	p_adpt_api->adpt_ip_network_route_add = NULL;
+	p_adpt_api->adpt_ip_port_sg_cfg_get = NULL;
+	p_adpt_api->adpt_ip_intf_get = NULL;
+	p_adpt_api->adpt_ip_network_route_del = NULL;
+	p_adpt_api->adpt_ip_host_del = NULL;
+	p_adpt_api->adpt_ip_route_mismatch_get = NULL;
+	p_adpt_api->adpt_ip_vsi_arp_sg_cfg_get = NULL;
+	p_adpt_api->adpt_ip_port_arp_sg_cfg_set = NULL;
+	p_adpt_api->adpt_ip_vsi_mc_mode_set = NULL;
+	p_adpt_api->adpt_ip_vsi_intf_set = NULL;
+	p_adpt_api->adpt_ip_nexthop_get = NULL;
+	p_adpt_api->adpt_ip_route_mismatch_set = NULL;
+	p_adpt_api->adpt_ip_host_get = NULL;
+	p_adpt_api->adpt_ip_intf_set = NULL;
+	p_adpt_api->adpt_ip_vsi_mc_mode_get = NULL;
+	p_adpt_api->adpt_ip_port_macaddr_get = NULL;
+	p_adpt_api->adpt_ip_port_arp_sg_cfg_get = NULL;
+	p_adpt_api->adpt_ip_nexthop_set = NULL;
+	p_adpt_api->adpt_ip_global_ctrl_get = NULL;
+	p_adpt_api->adpt_ip_global_ctrl_set = NULL;
+
+	return;
+}
+sw_error_t adpt_hppe_ip_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_ip_func_unregister(dev_id, p_adpt_api);
+#ifndef IN_IP_MINI
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_NETWORK_ROUTE_GET))
+		p_adpt_api->adpt_ip_network_route_get = adpt_hppe_ip_network_route_get;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_HOST_ADD))
+		p_adpt_api->adpt_ip_host_add = adpt_hppe_ip_host_add;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_SG_CFG_GET))
+		p_adpt_api->adpt_ip_vsi_sg_cfg_get = adpt_hppe_ip_vsi_sg_cfg_get;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PUB_ADDR_SET))
+		p_adpt_api->adpt_ip_pub_addr_set = adpt_hppe_ip_pub_addr_set;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_SG_CFG_SET))
+		p_adpt_api->adpt_ip_port_sg_cfg_set = adpt_hppe_ip_port_sg_cfg_set;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_INTF_GET))
+		p_adpt_api->adpt_ip_port_intf_get = adpt_hppe_ip_port_intf_get;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_ARP_SG_CFG_SET))
+		p_adpt_api->adpt_ip_vsi_arp_sg_cfg_set = adpt_hppe_ip_vsi_arp_sg_cfg_set;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PUB_ADDR_GET))
+		p_adpt_api->adpt_ip_pub_addr_get = adpt_hppe_ip_pub_addr_get;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_INTF_SET))
+		p_adpt_api->adpt_ip_port_intf_set = adpt_hppe_ip_port_intf_set;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_SG_CFG_SET))
+		p_adpt_api->adpt_ip_vsi_sg_cfg_set = adpt_hppe_ip_vsi_sg_cfg_set;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_HOST_NEXT))
+		p_adpt_api->adpt_ip_host_next = adpt_hppe_ip_host_next;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_MACADDR_SET))
+		p_adpt_api->adpt_ip_port_macaddr_set = adpt_hppe_ip_port_macaddr_set;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_INTF_GET))
+		p_adpt_api->adpt_ip_vsi_intf_get = adpt_hppe_ip_vsi_intf_get;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_NETWORK_ROUTE_ADD))
+		p_adpt_api->adpt_ip_network_route_add = adpt_hppe_ip_network_route_add;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_SG_CFG_GET))
+		p_adpt_api->adpt_ip_port_sg_cfg_get = adpt_hppe_ip_port_sg_cfg_get;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_INTF_GET))
+		p_adpt_api->adpt_ip_intf_get = adpt_hppe_ip_intf_get;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_NETWORK_ROUTE_DEL))
+		p_adpt_api->adpt_ip_network_route_del = adpt_hppe_ip_network_route_del;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_HOST_DEL))
+		p_adpt_api->adpt_ip_host_del = adpt_hppe_ip_host_del;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_ROUTE_MISMATCH_GET))
+		p_adpt_api->adpt_ip_route_mismatch_get = adpt_hppe_ip_route_mismatch_get;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_ARP_SG_CFG_GET))
+		p_adpt_api->adpt_ip_vsi_arp_sg_cfg_get = adpt_hppe_ip_vsi_arp_sg_cfg_get;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_ARP_SG_CFG_SET))
+		p_adpt_api->adpt_ip_port_arp_sg_cfg_set = adpt_hppe_ip_port_arp_sg_cfg_set;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_MC_MODE_SET))
+		p_adpt_api->adpt_ip_vsi_mc_mode_set = adpt_hppe_ip_vsi_mc_mode_set;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_INTF_SET))
+		p_adpt_api->adpt_ip_vsi_intf_set = adpt_hppe_ip_vsi_intf_set;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_NEXTHOP_GET))
+		p_adpt_api->adpt_ip_nexthop_get = adpt_hppe_ip_nexthop_get;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_ROUTE_MISMATCH_SET))
+		p_adpt_api->adpt_ip_route_mismatch_set = adpt_hppe_ip_route_mismatch_set;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_HOST_GET))
+		p_adpt_api->adpt_ip_host_get = adpt_hppe_ip_host_get;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_INTF_SET))
+		p_adpt_api->adpt_ip_intf_set = adpt_hppe_ip_intf_set;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_MC_MODE_GET))
+		p_adpt_api->adpt_ip_vsi_mc_mode_get = adpt_hppe_ip_vsi_mc_mode_get;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_MACADDR_GET))
+		p_adpt_api->adpt_ip_port_macaddr_get = adpt_hppe_ip_port_macaddr_get;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_ARP_SG_CFG_GET))
+		p_adpt_api->adpt_ip_port_arp_sg_cfg_get = adpt_hppe_ip_port_arp_sg_cfg_get;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_NEXTHOP_SET))
+		p_adpt_api->adpt_ip_nexthop_set = adpt_hppe_ip_nexthop_set;
+	if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_GLOBAL_CTRL_GET))
+		p_adpt_api->adpt_ip_global_ctrl_get = adpt_hppe_ip_global_ctrl_get;
+	if (p_adpt_api->adpt_ip_func_bitmap[1] & (1 << (FUNC_IP_GLOBAL_CTRL_SET % 32)))
+		p_adpt_api->adpt_ip_global_ctrl_set = adpt_hppe_ip_global_ctrl_set;
+#endif
+	return SW_OK;
+}
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_mib.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_mib.c
new file mode 100755
index 0000000..5237072
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_mib.c
@@ -0,0 +1,1019 @@
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_mib_reg.h"
+#include "hppe_mib.h"
+#include "adpt.h"
+#include "hppe_xgmacmib_reg.h"
+#include "hppe_xgmacmib.h"
+
+#include "hppe_init.h"
+#include "adpt_hppe.h"
+#ifdef CPPE
+#include "adpt_cppe_mib.h"
+#endif
+
+sw_error_t
+adpt_hppe_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_id = 0, status = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	rv = hppe_mac_mib_ctrl_mib_rd_clr_get(dev_id, port_id, &status);
+
+	if (status == A_TRUE)
+	{
+		*enable = A_FALSE;
+	}
+	else
+	{
+		*enable = A_TRUE;
+	}
+
+	if( rv != SW_OK )
+	{
+		return rv;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_ppe_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable)
+{
+	a_uint32_t port_id = 0, g_port_id = 0;
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	for (port_id = SSDK_PHYSICAL_PORT1; port_id <= SSDK_PHYSICAL_PORT6; port_id++)
+	{
+#ifdef CPPE
+		if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION &&
+			port_id == SSDK_PHYSICAL_PORT6)
+		{
+			rv = adpt_cppe_lpbk_mib_cpukeep_set(dev_id, port_id, enable);
+			SW_RTN_ON_ERROR(rv);
+			continue;
+		}
+#endif
+		g_port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+		hppe_mac_mib_ctrl_mib_rd_clr_set(dev_id, g_port_id, (a_uint32_t)(!enable));
+	}
+
+	return rv;
+}
+
+static sw_error_t
+adpt_hppe_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_mib_info_t * mib_info )
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mib_info);
+	memset(mib_info, 0, sizeof(fal_mib_info_t));
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	hppe_rxbroad_get(dev_id, (a_uint32_t)port_id, (union rxbroad_u *)&mib_info->RxBroad);
+	hppe_rxpause_get(dev_id, (a_uint32_t)port_id, (union rxpause_u *)&mib_info->RxPause);
+	hppe_rxmulti_get(dev_id, (a_uint32_t)port_id, (union rxmulti_u *)&mib_info->RxMulti);
+	hppe_rxfcserr_get(dev_id, (a_uint32_t)port_id, (union rxfcserr_u *)&mib_info->RxFcsErr);
+	hppe_rxalignerr_get(dev_id, (a_uint32_t)port_id,
+		(union rxalignerr_u *)&mib_info->RxAllignErr);
+	hppe_rxrunt_get(dev_id, (a_uint32_t)port_id, (union rxrunt_u *)&mib_info->RxRunt);
+	hppe_rxfrag_get(dev_id, (a_uint32_t)port_id, (union rxfrag_u *)&mib_info->RxFragment);
+	hppe_rxjumbofcserr_get(dev_id, (a_uint32_t)port_id,
+		(union rxjumbofcserr_u *)&mib_info->RxJumboFcsErr);
+	hppe_rxjumboalignerr_get(dev_id, (a_uint32_t)port_id,
+		(union rxjumboalignerr_u *)&mib_info->RxJumboAligenErr);
+	hppe_rxpkt64_get(dev_id, (a_uint32_t)port_id, (union rxpkt64_u *)&mib_info->Rx64Byte);
+	hppe_rxpkt65to127_get(dev_id, (a_uint32_t)port_id,
+		(union rxpkt65to127_u *)&mib_info->Rx128Byte);
+	hppe_rxpkt128to255_get(dev_id, (a_uint32_t)port_id,
+		(union rxpkt128to255_u *)&mib_info->Rx256Byte);
+	hppe_rxpkt256to511_get(dev_id, (a_uint32_t)port_id,
+		(union rxpkt256to511_u *)&mib_info->Rx512Byte);
+	hppe_rxpkt512to1023_get(dev_id, (a_uint32_t)port_id,
+		(union rxpkt512to1023_u *)&mib_info->Rx1024Byte);
+	hppe_rxpkt1024to1518_get(dev_id, (a_uint32_t)port_id,
+		(union rxpkt1024to1518_u *)&mib_info->Rx1518Byte);
+	hppe_rxpkt1519tox_get(dev_id, (a_uint32_t)port_id,
+		(union rxpkt1519tox_u *)&mib_info->RxMaxByte);
+	hppe_rxtoolong_get(dev_id, (a_uint32_t)port_id,
+		(union rxtoolong_u *)&mib_info->RxTooLong);
+	hppe_rxgoodbyte_l_get(dev_id, (a_uint32_t)port_id,
+		(union rxgoodbyte_l_u *)&mib_info->RxGoodByte_lo);
+	hppe_rxgoodbyte_h_get(dev_id, (a_uint32_t)port_id,
+		(union rxgoodbyte_h_u *)&mib_info->RxGoodByte_hi);
+	hppe_rxbadbyte_l_get(dev_id, (a_uint32_t)port_id,
+		(union rxbadbyte_l_u *)&mib_info->RxBadByte_lo);
+	hppe_rxbadbyte_h_get(dev_id, (a_uint32_t)port_id,
+		(union rxbadbyte_h_u *)&mib_info->RxBadByte_hi);
+	hppe_rxuni_get(dev_id, (a_uint32_t)port_id, (union rxuni_u *)&mib_info->RxUniCast);
+	hppe_txbroad_get(dev_id, (a_uint32_t)port_id, (union txbroad_u *)&mib_info->TxBroad);
+	hppe_txpause_get(dev_id, (a_uint32_t)port_id, (union txpause_u *)&mib_info->TxPause);
+	hppe_txmulti_get(dev_id, (a_uint32_t)port_id, (union txmulti_u *)&mib_info->TxMulti);
+	hppe_txunderrun_get(dev_id, (a_uint32_t)port_id,
+		(union txunderrun_u *)&mib_info->TxUnderRun);
+	hppe_txpkt64_get(dev_id, (a_uint32_t)port_id, (union txpkt64_u *)&mib_info->Tx64Byte);
+	hppe_txpkt65to127_get(dev_id, (a_uint32_t)port_id,
+		(union txpkt65to127_u *)&mib_info->Tx128Byte);
+	hppe_txpkt128to255_get(dev_id, (a_uint32_t)port_id,
+		(union txpkt128to255_u *)&mib_info->Tx256Byte);
+	hppe_txpkt256to511_get(dev_id, (a_uint32_t)port_id,
+		(union txpkt256to511_u *)&mib_info->Tx512Byte);
+	hppe_txpkt512to1023_get(dev_id, (a_uint32_t)port_id,
+		(union txpkt512to1023_u *)&mib_info->Tx1024Byte);
+	hppe_txpkt1024to1518_get(dev_id, (a_uint32_t)port_id,
+		(union txpkt1024to1518_u *)&mib_info->Tx1518Byte);
+	hppe_txpkt1519tox_get(dev_id, (a_uint32_t)port_id,
+		(union txpkt1519tox_u *)&mib_info->TxMaxByte);
+	hppe_txbyte_l_get(dev_id, (a_uint32_t)port_id,
+		(union txbyte_l_u *)&mib_info->TxByte_lo);
+	hppe_txbyte_h_get(dev_id, (a_uint32_t)port_id,
+		(union txbyte_h_u *)&mib_info->TxByte_hi);
+	hppe_txcollisions_get(dev_id, (a_uint32_t)port_id,
+		(union txcollisions_u *)&mib_info->TxCollision);
+	hppe_txabortcol_get(dev_id, (a_uint32_t)port_id,
+		(union txabortcol_u *)&mib_info->TxAbortCol);
+	hppe_txmulticol_get(dev_id, (a_uint32_t)port_id,
+		(union txmulticol_u *)&mib_info->TxMultiCol);
+	hppe_txsinglecol_get(dev_id, (a_uint32_t)port_id,
+		(union txsinglecol_u *)&mib_info->TxSingalCol);
+	hppe_txexcessivedefer_get(dev_id, (a_uint32_t)port_id,
+		(union txexcessivedefer_u *)&mib_info->TxExcDefer);
+	hppe_txdefer_get(dev_id, (a_uint32_t)port_id, (union txdefer_u *)&mib_info->TxDefer);
+	hppe_txlatecol_get(dev_id, (a_uint32_t)port_id, (union txlatecol_u *)&mib_info->TxLateCol);
+	hppe_txuni_get(dev_id, (a_uint32_t)port_id, (union txuni_u *)&mib_info->TxUniCast);
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_ppe_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_mib_info_t * mib_info)
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mib_info);
+#ifdef CPPE
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION &&
+		port_id == SSDK_PHYSICAL_PORT6)
+	{
+		return adpt_cppe_lpbk_get_mib_info(dev_id, port_id, mib_info);
+	}
+#endif
+	return adpt_hppe_get_mib_info(dev_id, port_id, mib_info);
+}
+
+sw_error_t
+adpt_hppe_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_mib_info_t * mib_info )
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mib_info);
+	memset(mib_info, 0, sizeof(fal_mib_info_t));
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	hppe_txbroad_get(dev_id, (a_uint32_t)port_id, (union txbroad_u *)&mib_info->TxBroad);
+	hppe_txpause_get(dev_id, (a_uint32_t)port_id, (union txpause_u *)&mib_info->TxPause);
+	hppe_txmulti_get(dev_id, (a_uint32_t)port_id, (union txmulti_u *)&mib_info->TxMulti);
+	hppe_txunderrun_get(dev_id, (a_uint32_t)port_id,
+		(union txunderrun_u *)&mib_info->TxUnderRun);
+	hppe_txpkt64_get(dev_id, (a_uint32_t)port_id, (union txpkt64_u *)&mib_info->Tx64Byte);
+	hppe_txpkt65to127_get(dev_id, (a_uint32_t)port_id,
+		(union txpkt65to127_u *)&mib_info->Tx128Byte);
+	hppe_txpkt128to255_get(dev_id, (a_uint32_t)port_id,
+		(union txpkt128to255_u *)&mib_info->Tx256Byte);
+	hppe_txpkt256to511_get(dev_id, (a_uint32_t)port_id,
+		(union txpkt256to511_u *)&mib_info->Tx512Byte);
+	hppe_txpkt512to1023_get(dev_id, (a_uint32_t)port_id,
+		(union txpkt512to1023_u *)&mib_info->Tx1024Byte);
+	hppe_txpkt1024to1518_get(dev_id, (a_uint32_t)port_id,
+		(union txpkt1024to1518_u *)&mib_info->Tx1518Byte);
+	hppe_txpkt1519tox_get(dev_id, (a_uint32_t)port_id,
+		(union txpkt1519tox_u *)&mib_info->TxMaxByte);
+	hppe_txbyte_l_get(dev_id, (a_uint32_t)port_id, (union txbyte_l_u *)&mib_info->TxByte_lo);
+	hppe_txbyte_h_get(dev_id, (a_uint32_t)port_id, (union txbyte_h_u *)&mib_info->TxByte_hi);
+	hppe_txcollisions_get(dev_id, (a_uint32_t)port_id,
+		(union txcollisions_u *)&mib_info->TxCollision);
+	hppe_txabortcol_get(dev_id, (a_uint32_t)port_id,
+		(union txabortcol_u *)&mib_info->TxAbortCol);
+	hppe_txmulticol_get(dev_id, (a_uint32_t)port_id,
+		(union txmulticol_u *)&mib_info->TxMultiCol);
+	hppe_txsinglecol_get(dev_id, (a_uint32_t)port_id,
+		(union txsinglecol_u *)&mib_info->TxSingalCol);
+	hppe_txexcessivedefer_get(dev_id, (a_uint32_t)port_id,
+		(union txexcessivedefer_u *)&mib_info->TxExcDefer);
+	hppe_txdefer_get(dev_id, (a_uint32_t)port_id, (union txdefer_u *)&mib_info->TxDefer);
+	hppe_txlatecol_get(dev_id, (a_uint32_t)port_id,
+		(union txlatecol_u *)&mib_info->TxLateCol);
+	hppe_txuni_get(dev_id, (a_uint32_t)port_id, (union txuni_u *)&mib_info->TxUniCast);
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_ppe_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+	a_uint32_t port_id = 0, xg_port_id = 0, g_port_id = 0;
+	a_uint32_t port_num = SSDK_PHYSICAL_PORT6;
+	union mmc_control_u mmc_control;
+	sw_error_t rv = SW_OK;
+
+	memset(&mmc_control, 0, sizeof(mmc_control));
+	ADPT_DEV_ID_CHECK(dev_id);
+#ifdef CPPE
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
+	{
+		port_num = SSDK_PHYSICAL_PORT5;
+		rv = adpt_cppe_lpbk_mib_status_set(dev_id, SSDK_PHYSICAL_PORT6, enable);
+		SW_RTN_ON_ERROR(rv);
+	}
+#endif
+	for (port_id = SSDK_PHYSICAL_PORT1; port_id <= port_num; port_id++) {
+		g_port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+		hppe_mac_mib_ctrl_mib_en_set(dev_id, g_port_id, (a_uint32_t)enable);
+	}
+
+	for (port_id = SSDK_PHYSICAL_PORT5; port_id <= port_num; port_id++) {
+		xg_port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+		hppe_mmc_control_get(dev_id, xg_port_id, &mmc_control);
+
+		if(A_TRUE == enable)
+			mmc_control.bf.mcf = 0;
+		else
+			mmc_control.bf.mcf = 1;
+
+		hppe_mmc_control_set(dev_id, xg_port_id, &mmc_control);
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id)
+{
+	union mmc_control_u mmc_control;
+
+	memset(&mmc_control, 0, sizeof(mmc_control));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if(port_id < SSDK_PHYSICAL_PORT1 || port_id > SSDK_PHYSICAL_PORT6)
+		return SW_BAD_PARAM;
+	/*GMAC*/
+	if(!hppe_xgmac_port_check(port_id))
+	{
+		port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+		hppe_mac_mib_ctrl_mib_reset_set(dev_id, port_id, A_TRUE);
+		hppe_mac_mib_ctrl_mib_reset_set(dev_id, port_id, A_FALSE);
+	}
+	/*XGMAC*/
+	else
+	{
+		port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+		hppe_mmc_control_get(dev_id, port_id, &mmc_control);
+		mmc_control.bf.cntrst = 1;
+		hppe_mmc_control_set(dev_id, port_id, &mmc_control);
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_ppe_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id)
+{
+#ifdef CPPE
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION &&
+		port_id == SSDK_PHYSICAL_PORT6)
+	{
+		return adpt_cppe_lpbk_mib_flush_counters(dev_id, port_id);
+	}
+#endif
+	return adpt_hppe_mib_port_flush_counters(dev_id, port_id);
+}
+
+sw_error_t
+adpt_hppe_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_id = 0, status = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	rv = hppe_mac_mib_ctrl_mib_en_get(dev_id, port_id, &status);
+	*enable = status;
+
+	if( rv != SW_OK )
+		return rv;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_mib_info_t * mib_info )
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mib_info);
+	memset(mib_info, 0, sizeof(fal_mib_info_t));
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	hppe_rxbroad_get(dev_id, (a_uint32_t)port_id, (union rxbroad_u *)&mib_info->RxBroad);
+	hppe_rxpause_get(dev_id, (a_uint32_t)port_id, (union rxpause_u *)&mib_info->RxPause);
+	hppe_rxmulti_get(dev_id, (a_uint32_t)port_id, (union rxmulti_u *)&mib_info->RxMulti);
+	hppe_rxfcserr_get(dev_id, (a_uint32_t)port_id, (union rxfcserr_u *)&mib_info->RxFcsErr);
+	hppe_rxalignerr_get(dev_id, (a_uint32_t)port_id,
+		(union rxalignerr_u *)&mib_info->RxAllignErr);
+	hppe_rxrunt_get(dev_id, (a_uint32_t)port_id, (union rxrunt_u *)&mib_info->RxRunt);
+	hppe_rxfrag_get(dev_id, (a_uint32_t)port_id, (union rxfrag_u *)&mib_info->RxFragment);
+	hppe_rxjumbofcserr_get(dev_id, (a_uint32_t)port_id,
+		(union rxjumbofcserr_u *)&mib_info->RxJumboFcsErr);
+	hppe_rxjumboalignerr_get(dev_id, (a_uint32_t)port_id,
+		(union rxjumboalignerr_u *)&mib_info->RxJumboAligenErr);
+	hppe_rxpkt64_get(dev_id, (a_uint32_t)port_id, (union rxpkt64_u *)&mib_info->Rx64Byte);
+	hppe_rxpkt65to127_get(dev_id, (a_uint32_t)port_id,
+		(union rxpkt65to127_u *)&mib_info->Rx128Byte);
+	hppe_rxpkt128to255_get(dev_id, (a_uint32_t)port_id,
+		(union rxpkt128to255_u *)&mib_info->Rx256Byte);
+	hppe_rxpkt256to511_get(dev_id, (a_uint32_t)port_id,
+		(union rxpkt256to511_u *)&mib_info->Rx512Byte);
+	hppe_rxpkt512to1023_get(dev_id, (a_uint32_t)port_id,
+		(union rxpkt512to1023_u *)&mib_info->Rx1024Byte);
+	hppe_rxpkt1024to1518_get(dev_id, (a_uint32_t)port_id,
+		(union rxpkt1024to1518_u *)&mib_info->Rx1518Byte);
+	hppe_rxpkt1519tox_get(dev_id, (a_uint32_t)port_id,
+		(union rxpkt1519tox_u *)&mib_info->RxMaxByte);
+	hppe_rxtoolong_get(dev_id, (a_uint32_t)port_id,
+		(union rxtoolong_u *)&mib_info->RxTooLong);
+	hppe_rxgoodbyte_l_get(dev_id, (a_uint32_t)port_id,
+		(union rxgoodbyte_l_u *)&mib_info->RxGoodByte_lo);
+	hppe_rxgoodbyte_h_get(dev_id, (a_uint32_t)port_id,
+		(union rxgoodbyte_h_u *)&mib_info->RxGoodByte_hi);
+	hppe_rxbadbyte_l_get(dev_id, (a_uint32_t)port_id,
+		(union rxbadbyte_l_u *)&mib_info->RxBadByte_lo);
+	hppe_rxbadbyte_h_get(dev_id, (a_uint32_t)port_id,
+		(union rxbadbyte_h_u *)&mib_info->RxBadByte_hi);
+	hppe_rxuni_get(dev_id, (a_uint32_t)port_id, (union rxuni_u *)&mib_info->RxUniCast);
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_ppe_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_mib_info_t * mib_info)
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mib_info);
+#ifdef CPPE
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION &&
+		port_id == SSDK_PHYSICAL_PORT6)
+	{
+		return adpt_cppe_lpbk_get_mib_info(dev_id, port_id, mib_info);
+	}
+#endif
+	return adpt_hppe_get_rx_mib_info(dev_id, port_id, mib_info);
+}
+
+void adpt_hppe_mib_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_mib_func_bitmap = ((1<<FUNC_GET_MIB_INFO)|
+						(1<<FUNC_GET_RX_MIB_INFO)|
+						(1<<FUNC_GET_TX_MIB_INFO)|
+						(1<<FUNC_GET_XGMIB_INFO)|
+						(1<<FUNC_GET_TX_XGMIB_INFO)|
+						(1<<FUNC_GET_RX_XGMIB_INFO)|
+						(1<<FUNC_MIB_STATUS_SET)|
+						(1<<FUNC_MIB_STATUS_GET)|
+						(1<<FUNC_MIB_PORT_FLUSH_COUNTERS)|
+						(1<<FUNC_MIB_CPUKEEP_SET)|
+						(1<<FUNC_MIB_CPUKEEP_GET)
+						);
+	return;
+}
+
+static void adpt_hppe_mib_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_get_mib_info = NULL;
+	p_adpt_api->adpt_get_rx_mib_info = NULL;
+	p_adpt_api->adpt_get_tx_mib_info = NULL;
+	p_adpt_api->adpt_mib_status_set = NULL;
+	p_adpt_api->adpt_mib_status_get = NULL;
+	p_adpt_api->adpt_mib_port_flush_counters = NULL;
+	p_adpt_api->adpt_mib_cpukeep_set = NULL;
+	p_adpt_api->adpt_mib_cpukeep_get = NULL;
+	p_adpt_api->adpt_get_xgmib_info = NULL;
+	p_adpt_api->adpt_get_tx_xgmib_info = NULL;
+	p_adpt_api->adpt_get_rx_xgmib_info = NULL;
+
+	return;
+}
+
+sw_error_t
+adpt_hppe_get_xgmib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_xgmib_info_t * mib_info )
+{
+	a_uint64_t data_low , data_high ;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mib_info);
+	memset(mib_info, 0, sizeof( * mib_info ));
+
+	if(!(hppe_xgmac_port_check(port_id)))
+	{
+		printk("this port is not xg port!\n");
+		return SW_FAIL;
+	}
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+
+	/*get tx xgmib information*/
+	data_low = 0; data_high = 0;
+	hppe_tx_octet_count_good_bad_low_get(dev_id, port_id, (union tx_octet_count_good_bad_low_u*)&data_low);
+	hppe_tx_octet_count_good_bad_high_get(dev_id, port_id, (union tx_octet_count_good_bad_high_u *)&data_high);
+	mib_info->TxByte = (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_frame_count_good_bad_low_get(dev_id, port_id, (union tx_frame_count_good_bad_low_u *)&data_low);
+	hppe_tx_frame_count_good_bad_high_get(dev_id, port_id, (union tx_frame_count_good_bad_high_u *)&data_high);
+	mib_info->TxFrame =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_broadcast_frames_good_low_get(dev_id, port_id, (union tx_broadcast_frames_good_low_u *)&data_low);
+	hppe_tx_broadcast_frames_good_high_get(dev_id, port_id, (union tx_broadcast_frames_good_high_u*)&data_high);
+	mib_info->TxBroadGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_multicast_frames_good_low_get(dev_id, port_id, (union tx_multicast_frames_good_low_u*)&data_low);
+	hppe_tx_multicast_frames_good_high_get(dev_id, port_id, (union tx_multicast_frames_good_high_u*)&data_high);
+	mib_info->TxMultiGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_64octets_frames_good_bad_low_get(dev_id, port_id, (union tx_64octets_frames_good_bad_low_u*)&data_low);
+	hppe_tx_64octets_frames_good_bad_high_get(dev_id, port_id, (union tx_64octets_frames_good_bad_high_u*)&data_high);
+	mib_info->Tx64Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_65to127octets_frames_good_bad_low_get(dev_id, port_id, (union tx_65to127octets_frames_good_bad_low_u *)&data_low);
+	hppe_tx_65to127octets_frames_good_bad_high_get(dev_id, port_id, (union tx_65to127octets_frames_good_bad_high_u *)&data_high);
+	mib_info->Tx128Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_128to255octets_frames_good_bad_low_get(dev_id, port_id, (union tx_128to255octets_frames_good_bad_low_u  *)&data_low);
+	hppe_tx_128to255octets_frames_good_bad_high_get(dev_id, port_id, (union tx_128to255octets_frames_good_bad_high_u  *)&data_high);
+	mib_info->Tx256Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_256to511octets_frames_good_bad_low_get(dev_id, port_id, (union tx_256to511octets_frames_good_bad_low_u  *)&data_low);
+	hppe_tx_256to511octets_frames_good_bad_high_get(dev_id, port_id, (union tx_256to511octets_frames_good_bad_high_u  *)&data_high);
+	mib_info->Tx512Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_512to1023octets_frames_good_bad_low_get(dev_id, port_id, (union tx_512to1023octets_frames_good_bad_low_u*)&data_low);
+	hppe_tx_512to1023octets_frames_good_bad_high_get(dev_id, port_id, (union tx_512to1023octets_frames_good_bad_high_u*)&data_high);
+	mib_info->Tx1024Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_1024tomaxoctets_frames_good_bad_low_get(dev_id, port_id, (union tx_1024tomaxoctets_frames_good_bad_low_u*)&data_low);
+	hppe_tx_1024tomaxoctets_frames_good_bad_high_get(dev_id, port_id, (union tx_1024tomaxoctets_frames_good_bad_high_u*)&data_high);
+	mib_info->TxMaxByte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_unicast_frames_good_bad_low_get(dev_id, port_id, (union tx_unicast_frames_good_bad_low_u*)&data_low);
+	hppe_tx_unicast_frames_good_bad_high_get(dev_id, port_id, (union tx_unicast_frames_good_bad_high_u*)&data_high);
+	mib_info->TxUnicast =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_multicast_frames_good_bad_low_get(dev_id, port_id, (union tx_multicast_frames_good_bad_low_u *)&data_low);
+	hppe_tx_multicast_frames_good_bad_high_get(dev_id, port_id, (union tx_multicast_frames_good_bad_high_u *)&data_high);
+	mib_info->TxMulti =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_broadcast_frames_good_bad_low_get(dev_id, port_id, (union tx_broadcast_frames_good_bad_low_u*)&data_low);
+	hppe_tx_broadcast_frames_good_bad_high_get(dev_id, port_id, (union tx_broadcast_frames_good_bad_high_u*)&data_high);
+	mib_info->TxBroad =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_underflow_error_frames_low_get(dev_id, port_id, (union tx_underflow_error_frames_low_u*)&data_low);
+	hppe_tx_underflow_error_frames_high_get(dev_id, port_id, (union tx_underflow_error_frames_high_u*)&data_high);
+	mib_info->TxUnderFlowError =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_octet_count_good_low_get(dev_id, port_id, (union tx_octet_count_good_low_u*)&data_low);
+	hppe_tx_octet_count_good_high_get(dev_id, port_id, (union tx_octet_count_good_high_u*)&data_high);
+	mib_info->TxByteGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_frame_count_good_low_get(dev_id, port_id, (union tx_frame_count_good_low_u*)&data_low);
+	hppe_tx_frame_count_good_high_get(dev_id, port_id, (union tx_frame_count_good_high_u*)&data_high);
+	mib_info->TxFrameGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_pause_frames_low_get(dev_id, port_id, (union tx_pause_frames_low_u *)&data_low);
+	hppe_tx_pause_frames_high_get(dev_id, port_id, (union tx_pause_frames_high_u *)&data_high);
+	mib_info->TxPause =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_vlan_frames_good_low_get(dev_id, port_id, (union tx_vlan_frames_good_low_u *)&data_low);
+	hppe_tx_vlan_frames_good_high_get(dev_id, port_id, (union tx_vlan_frames_good_high_u *)&data_high);
+	mib_info->TxVLANFrameGood =  (data_high<<32) |data_low;
+
+	data_low = 0;
+	hppe_tx_lpi_usec_cntr_get(dev_id, port_id, (union tx_lpi_usec_cntr_u  *)&data_low);
+	mib_info->TxLPIUsec =  data_low;
+
+	data_low = 0;
+	hppe_tx_lpi_tran_cntr_get(dev_id, port_id, (union tx_lpi_tran_cntr_u  *)&data_low);
+	mib_info->TxLPITran =  data_low;
+
+	/*get rx xgmib information*/
+	data_low = 0; data_high = 0;
+	hppe_rx_frame_count_good_bad_low_get(dev_id, port_id, (union rx_frame_count_good_bad_low_u *)&data_low);
+	hppe_rx_frame_count_good_bad_high_get(dev_id, port_id, (union rx_frame_count_good_bad_high_u *)&data_high);
+	mib_info->RxFrame =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_octet_count_good_bad_low_get(dev_id, port_id, (union rx_octet_count_good_bad_low_u*)&data_low);
+	hppe_rx_octet_count_good_bad_high_get(dev_id, port_id, (union rx_octet_count_good_bad_high_u*)&data_high);
+	mib_info->RxByte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_octet_count_good_low_get(dev_id, port_id, (union rx_octet_count_good_low_u *)&data_low);
+	hppe_rx_octet_count_good_high_get(dev_id, port_id, (union rx_octet_count_good_high_u *)&data_high);
+	mib_info->RxByteGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_broadcast_frames_good_low_get(dev_id, port_id, (union rx_broadcast_frames_good_low_u *)&data_low);
+	hppe_rx_broadcast_frames_good_high_get(dev_id, port_id, (union rx_broadcast_frames_good_high_u*)&data_high);
+	mib_info->RxBroadGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_multicast_frames_good_low_get(dev_id, port_id, (union rx_multicast_frames_good_low_u*)&data_low);
+	hppe_rx_multicast_frames_good_high_get(dev_id, port_id, (union rx_multicast_frames_good_high_u*)&data_high);
+	mib_info->RxMultiGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_crc_error_frames_low_get(dev_id, port_id, (union rx_crc_error_frames_low_u *)&data_low);
+	hppe_rx_crc_error_frames_high_get(dev_id, port_id, (union rx_crc_error_frames_high_u *)&data_high);
+	mib_info->RxFcsErr =  (data_high<<32) |data_low;
+
+	data_low = 0;
+	hppe_rx_runt_error_frames_get(dev_id, port_id, (union rx_runt_error_frames_u  *)&data_low);
+	mib_info->RxRuntErr  =   data_low;
+
+	data_low = 0;
+	hppe_rx_jabber_error_frames_get(dev_id, port_id, (union rx_jabber_error_frames_u  *)&data_low);
+	mib_info->RxJabberError = data_low;
+
+	data_low = 0;
+	hppe_rx_undersize_frames_good_get(dev_id, port_id, (union rx_undersize_frames_good_u  *)&data_low);
+	mib_info->RxUndersizeGood =  data_low;
+
+	data_low = 0;
+	hppe_rx_oversize_frames_good_get(dev_id, port_id, (union rx_oversize_frames_good_u  *)&data_low);
+	mib_info->RxOversizeGood = data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_64octets_frames_good_bad_low_get(dev_id, port_id, (union rx_64octets_frames_good_bad_low_u  *)&data_low);
+	hppe_rx_64octets_frames_good_bad_high_get(dev_id, port_id, (union rx_64octets_frames_good_bad_high_u  *)&data_high);
+	mib_info->Rx64Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_65to127octets_frames_good_bad_low_get(dev_id, port_id, (union rx_65to127octets_frames_good_bad_low_u  *)&data_low);
+	hppe_rx_65to127octets_frames_good_bad_high_get(dev_id, port_id, (union rx_65to127octets_frames_good_bad_high_u  *)&data_high);
+	mib_info->Rx128Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_128to255octets_frames_good_bad_low_get(dev_id, port_id, (union rx_128to255octets_frames_good_bad_low_u  *)&data_low);
+	hppe_rx_128to255octets_frames_good_bad_high_get(dev_id, port_id, (union rx_128to255octets_frames_good_bad_high_u  *)&data_high);
+	mib_info->Rx256Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_256to511octets_frames_good_bad_low_get	(dev_id, port_id, (union rx_256to511octets_frames_good_bad_low_u  *)&data_low);
+	hppe_rx_256to511octets_frames_good_bad_high_get(dev_id, port_id, (union rx_256to511octets_frames_good_bad_high_u  *)&data_high);
+	mib_info->Rx512Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_512to1023octets_frames_good_bad_low_get(dev_id, port_id, (union rx_512to1023octets_frames_good_bad_low_u *)&data_low);
+	hppe_rx_512to1023octets_frames_good_bad_high_get(dev_id, port_id, (union rx_512to1023octets_frames_good_bad_high_u *)&data_high);
+	mib_info->Rx1024Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_1024tomaxoctets_frames_good_bad_low_get(dev_id, port_id, (union rx_1024tomaxoctets_frames_good_bad_low_u *)&data_low);
+	hppe_rx_1024tomaxoctets_frames_good_bad_high_get(dev_id, port_id, (union rx_1024tomaxoctets_frames_good_bad_high_u *)&data_high);
+	mib_info->RxMaxByte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_unicast_frames_good_low_get(dev_id, port_id, (union rx_unicast_frames_good_low_u  *)&data_low);
+	hppe_rx_unicast_frames_good_high_get(dev_id, port_id, (union rx_unicast_frames_good_high_u  *)&data_high);
+	mib_info->RxUnicastGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_length_error_frames_low_get(dev_id, port_id, (union rx_length_error_frames_low_u  *)&data_low);
+	hppe_rx_length_error_frames_high_get(dev_id, port_id, (union rx_length_error_frames_high_u  *)&data_high);
+	mib_info->RxLengthError =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_outofrange_frames_low_get(dev_id, port_id, (union rx_outofrange_frames_low_u*)&data_low);
+	hppe_rx_outofrange_frames_high_get(dev_id, port_id, (union rx_outofrange_frames_high_u*)&data_high);
+	mib_info->RxOutOfRangeError =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_pause_frames_low_get(dev_id, port_id, (union rx_pause_frames_low_u *)&data_low);
+	hppe_rx_pause_frames_high_get(dev_id, port_id, (union rx_pause_frames_high_u *)&data_high);
+	mib_info->RxPause =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_fifooverflow_frames_low_get(dev_id, port_id, (union rx_fifooverflow_frames_low_u *)&data_low);
+	hppe_rx_fifooverflow_frames_high_get(dev_id, port_id, (union rx_fifooverflow_frames_high_u *)&data_high);
+	mib_info->RxOverFlow =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_vlan_frames_good_bad_low_get(dev_id, port_id, (union rx_vlan_frames_good_bad_low_u *)&data_low);
+	hppe_rx_vlan_frames_good_bad_high_get(dev_id, port_id, (union rx_vlan_frames_good_bad_high_u*)&data_high);
+	mib_info->RxVLANFrameGoodBad =  (data_high<<32) |data_low;
+
+	data_low = 0;
+	hppe_rx_watchdog_error_frames_get(dev_id, port_id, (union rx_watchdog_error_frames_u*)&data_low);
+	mib_info->RxWatchDogError = data_low;
+
+	data_low = 0;
+	hppe_rx_lpi_usec_cntr_get(dev_id, port_id, (union rx_lpi_usec_cntr_u *)&data_low);
+	mib_info->RxLPIUsec = data_low;
+
+	data_low = 0;
+	hppe_rx_lpi_tran_cntr_get(dev_id, port_id, (union rx_lpi_tran_cntr_u *)&data_low);
+	mib_info->RxLPITran = data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_discard_frame_count_good_bad_low_get(dev_id, port_id, (union rx_discard_frame_count_good_bad_low_u *)&data_low);
+	hppe_rx_discard_frame_count_good_bad_high_get(dev_id, port_id, (union rx_discard_frame_count_good_bad_high_u *)&data_high);
+	mib_info->RxDropFrameGoodBad =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_discard_octet_count_good_bad_low_get(dev_id, port_id, (union rx_discard_octet_count_good_bad_low_u *)&data_low);
+	hppe_rx_discard_octet_count_good_bad_high_get(dev_id, port_id, (union rx_discard_octet_count_good_bad_high_u *)&data_high);
+	mib_info->RxDropByteGoodBad =  (data_high<<32) |data_low;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_get_tx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_xgmib_info_t * mib_info )
+{
+
+	a_uint64_t data_low , data_high ;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mib_info);
+	memset(mib_info, 0, sizeof(* mib_info));
+
+	if(!(hppe_xgmac_port_check(port_id)))
+	{
+		printk("this port is not xg port!\n");
+		return SW_FAIL;
+	}
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+
+	/*get tx xgmib information*/
+	data_low = 0; data_high = 0;
+	hppe_tx_octet_count_good_bad_low_get(dev_id, port_id, (union tx_octet_count_good_bad_low_u*)&data_low);
+	hppe_tx_octet_count_good_bad_high_get(dev_id, port_id, (union tx_octet_count_good_bad_high_u *)&data_high);
+	mib_info->TxByte = (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_frame_count_good_bad_low_get(dev_id, port_id, (union tx_frame_count_good_bad_low_u *)&data_low);
+	hppe_tx_frame_count_good_bad_high_get(dev_id, port_id, (union tx_frame_count_good_bad_high_u *)&data_high);
+	mib_info->TxFrame =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_broadcast_frames_good_low_get(dev_id, port_id, (union tx_broadcast_frames_good_low_u *)&data_low);
+	hppe_tx_broadcast_frames_good_high_get(dev_id, port_id, (union tx_broadcast_frames_good_high_u*)&data_high);
+	mib_info->TxBroadGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_multicast_frames_good_low_get(dev_id, port_id, (union tx_multicast_frames_good_low_u*)&data_low);
+	hppe_tx_multicast_frames_good_high_get(dev_id, port_id, (union tx_multicast_frames_good_high_u*)&data_high);
+	mib_info->TxMultiGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_64octets_frames_good_bad_low_get(dev_id, port_id, (union tx_64octets_frames_good_bad_low_u*)&data_low);
+	hppe_tx_64octets_frames_good_bad_high_get(dev_id, port_id, (union tx_64octets_frames_good_bad_high_u*)&data_high);
+	mib_info->Tx64Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_65to127octets_frames_good_bad_low_get(dev_id, port_id, (union tx_65to127octets_frames_good_bad_low_u *)&data_low);
+	hppe_tx_65to127octets_frames_good_bad_high_get(dev_id, port_id, (union tx_65to127octets_frames_good_bad_high_u *)&data_high);
+	mib_info->Tx128Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_128to255octets_frames_good_bad_low_get(dev_id, port_id, (union tx_128to255octets_frames_good_bad_low_u  *)&data_low);
+	hppe_tx_128to255octets_frames_good_bad_high_get(dev_id, port_id, (union tx_128to255octets_frames_good_bad_high_u  *)&data_high);
+	mib_info->Tx256Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_256to511octets_frames_good_bad_low_get(dev_id, port_id, (union tx_256to511octets_frames_good_bad_low_u  *)&data_low);
+	hppe_tx_256to511octets_frames_good_bad_high_get(dev_id, port_id, (union tx_256to511octets_frames_good_bad_high_u  *)&data_high);
+	mib_info->Tx512Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_512to1023octets_frames_good_bad_low_get(dev_id, port_id, (union tx_512to1023octets_frames_good_bad_low_u*)&data_low);
+	hppe_tx_512to1023octets_frames_good_bad_high_get(dev_id, port_id, (union tx_512to1023octets_frames_good_bad_high_u*)&data_high);
+	mib_info->Tx1024Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_1024tomaxoctets_frames_good_bad_low_get(dev_id, port_id, (union tx_1024tomaxoctets_frames_good_bad_low_u*)&data_low);
+	hppe_tx_1024tomaxoctets_frames_good_bad_high_get(dev_id, port_id, (union tx_1024tomaxoctets_frames_good_bad_high_u*)&data_high);
+	mib_info->TxMaxByte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_unicast_frames_good_bad_low_get(dev_id, port_id, (union tx_unicast_frames_good_bad_low_u*)&data_low);
+	hppe_tx_unicast_frames_good_bad_high_get(dev_id, port_id, (union tx_unicast_frames_good_bad_high_u*)&data_high);
+	mib_info->TxUnicast =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_multicast_frames_good_bad_low_get(dev_id, port_id, (union tx_multicast_frames_good_bad_low_u *)&data_low);
+	hppe_tx_multicast_frames_good_bad_high_get(dev_id, port_id, (union tx_multicast_frames_good_bad_high_u *)&data_high);
+	mib_info->TxMulti =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_broadcast_frames_good_bad_low_get(dev_id, port_id, (union tx_broadcast_frames_good_bad_low_u*)&data_low);
+	hppe_tx_broadcast_frames_good_bad_high_get(dev_id, port_id, (union tx_broadcast_frames_good_bad_high_u*)&data_high);
+	mib_info->TxBroad =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_underflow_error_frames_low_get(dev_id, port_id, (union tx_underflow_error_frames_low_u*)&data_low);
+	hppe_tx_underflow_error_frames_high_get(dev_id, port_id, (union tx_underflow_error_frames_high_u*)&data_high);
+	mib_info->TxUnderFlowError =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_octet_count_good_low_get(dev_id, port_id, (union tx_octet_count_good_low_u*)&data_low);
+	hppe_tx_octet_count_good_high_get(dev_id, port_id, (union tx_octet_count_good_high_u*)&data_high);
+	mib_info->TxByteGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_frame_count_good_low_get(dev_id, port_id, (union tx_frame_count_good_low_u*)&data_low);
+	hppe_tx_frame_count_good_high_get(dev_id, port_id, (union tx_frame_count_good_high_u*)&data_high);
+	mib_info->TxFrameGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_pause_frames_low_get(dev_id, port_id, (union tx_pause_frames_low_u *)&data_low);
+	hppe_tx_pause_frames_high_get(dev_id, port_id, (union tx_pause_frames_high_u *)&data_high);
+	mib_info->TxPause =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_tx_vlan_frames_good_low_get(dev_id, port_id, (union tx_vlan_frames_good_low_u *)&data_low);
+	hppe_tx_vlan_frames_good_high_get(dev_id, port_id, (union tx_vlan_frames_good_high_u *)&data_high);
+	mib_info->TxVLANFrameGood =  (data_high<<32) |data_low;
+
+	data_low = 0;
+	hppe_tx_lpi_usec_cntr_get(dev_id, port_id, (union tx_lpi_usec_cntr_u  *)&data_low);
+	mib_info->TxLPIUsec = data_low;
+
+	data_low = 0;
+	hppe_tx_lpi_tran_cntr_get(dev_id, port_id, (union tx_lpi_tran_cntr_u  *)&data_low);
+	mib_info->TxLPITran = data_low;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_get_rx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_xgmib_info_t * mib_info )
+{
+	a_uint64_t data_low , data_high ;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mib_info);
+	memset(mib_info, 0, sizeof(* mib_info));
+
+	if(!(hppe_xgmac_port_check(port_id)))
+	{
+		printk("this port is not xg port!\n");
+		return SW_FAIL;
+	}
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+
+	/*get tx xgmib information*/
+	data_low = 0; data_high = 0;
+	hppe_rx_frame_count_good_bad_low_get(dev_id, port_id, (union rx_frame_count_good_bad_low_u *)&data_low);
+	hppe_rx_frame_count_good_bad_high_get(dev_id, port_id, (union rx_frame_count_good_bad_high_u *)&data_high);
+	mib_info->RxFrame =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_octet_count_good_bad_low_get(dev_id, port_id, (union rx_octet_count_good_bad_low_u*)&data_low);
+	hppe_rx_octet_count_good_bad_high_get(dev_id, port_id, (union rx_octet_count_good_bad_high_u*)&data_high);
+	mib_info->RxByte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_octet_count_good_low_get(dev_id, port_id, (union rx_octet_count_good_low_u *)&data_low);
+	hppe_rx_octet_count_good_high_get(dev_id, port_id, (union rx_octet_count_good_high_u *)&data_high);
+	mib_info->RxByteGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_broadcast_frames_good_low_get(dev_id, port_id, (union rx_broadcast_frames_good_low_u *)&data_low);
+	hppe_rx_broadcast_frames_good_high_get(dev_id, port_id, (union rx_broadcast_frames_good_high_u*)&data_high);
+	mib_info->RxBroadGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_multicast_frames_good_low_get(dev_id, port_id, (union rx_multicast_frames_good_low_u*)&data_low);
+	hppe_rx_multicast_frames_good_high_get(dev_id, port_id, (union rx_multicast_frames_good_high_u*)&data_high);
+	mib_info->RxMultiGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_crc_error_frames_low_get(dev_id, port_id, (union rx_crc_error_frames_low_u *)&data_low);
+	hppe_rx_crc_error_frames_high_get(dev_id, port_id, (union rx_crc_error_frames_high_u *)&data_high);
+	mib_info->RxFcsErr =  (data_high<<32) |data_low;
+
+	data_low = 0;
+	hppe_rx_runt_error_frames_get(dev_id, port_id, (union rx_runt_error_frames_u  *)&data_low);
+	mib_info->RxRuntErr = data_low;
+
+	data_low = 0;
+	hppe_rx_jabber_error_frames_get(dev_id, port_id, (union rx_jabber_error_frames_u  *)&data_low);
+	mib_info->RxJabberError = data_low;
+
+	data_low = 0;
+	hppe_rx_undersize_frames_good_get(dev_id, port_id, (union rx_undersize_frames_good_u  *)&data_low);
+	mib_info->RxUndersizeGood = data_low;
+
+	data_low = 0;
+	hppe_rx_oversize_frames_good_get(dev_id, port_id, (union rx_oversize_frames_good_u  *)&data_low);
+	mib_info->RxOversizeGood = data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_64octets_frames_good_bad_low_get(dev_id, port_id, (union rx_64octets_frames_good_bad_low_u  *)&data_low);
+	hppe_rx_64octets_frames_good_bad_high_get(dev_id, port_id, (union rx_64octets_frames_good_bad_high_u  *)&data_high);
+	mib_info->Rx64Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_65to127octets_frames_good_bad_low_get(dev_id, port_id, (union rx_65to127octets_frames_good_bad_low_u  *)&data_low);
+	hppe_rx_65to127octets_frames_good_bad_high_get(dev_id, port_id, (union rx_65to127octets_frames_good_bad_high_u  *)&data_high);
+	mib_info->Rx128Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_128to255octets_frames_good_bad_low_get(dev_id, port_id, (union rx_128to255octets_frames_good_bad_low_u  *)&data_low);
+	hppe_rx_128to255octets_frames_good_bad_high_get(dev_id, port_id, (union rx_128to255octets_frames_good_bad_high_u  *)&data_high);
+	mib_info->Rx256Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_256to511octets_frames_good_bad_low_get	(dev_id, port_id, (union rx_256to511octets_frames_good_bad_low_u  *)&data_low);
+	hppe_rx_256to511octets_frames_good_bad_high_get(dev_id, port_id, (union rx_256to511octets_frames_good_bad_high_u  *)&data_high);
+	mib_info->Rx512Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_512to1023octets_frames_good_bad_low_get(dev_id, port_id, (union rx_512to1023octets_frames_good_bad_low_u *)&data_low);
+	hppe_rx_512to1023octets_frames_good_bad_high_get(dev_id, port_id, (union rx_512to1023octets_frames_good_bad_high_u *)&data_high);
+	mib_info->Rx1024Byte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_1024tomaxoctets_frames_good_bad_low_get(dev_id, port_id, (union rx_1024tomaxoctets_frames_good_bad_low_u *)&data_low);
+	hppe_rx_1024tomaxoctets_frames_good_bad_high_get(dev_id, port_id, (union rx_1024tomaxoctets_frames_good_bad_high_u *)&data_high);
+	mib_info->RxMaxByte =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_unicast_frames_good_low_get(dev_id, port_id, (union rx_unicast_frames_good_low_u  *)&data_low);
+	hppe_rx_unicast_frames_good_high_get(dev_id, port_id, (union rx_unicast_frames_good_high_u  *)&data_high);
+	mib_info->RxUnicastGood =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_length_error_frames_low_get(dev_id, port_id, (union rx_length_error_frames_low_u  *)&data_low);
+	hppe_rx_length_error_frames_high_get(dev_id, port_id, (union rx_length_error_frames_high_u  *)&data_high);
+	mib_info->RxLengthError =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_outofrange_frames_low_get(dev_id, port_id, (union rx_outofrange_frames_low_u*)&data_low);
+	hppe_rx_outofrange_frames_high_get(dev_id, port_id, (union rx_outofrange_frames_high_u*)&data_high);
+	mib_info->RxOutOfRangeError =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_pause_frames_low_get(dev_id, port_id, (union rx_pause_frames_low_u *)&data_low);
+	hppe_rx_pause_frames_high_get(dev_id, port_id, (union rx_pause_frames_high_u *)&data_high);
+	mib_info->RxPause =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_fifooverflow_frames_low_get(dev_id, port_id, (union rx_fifooverflow_frames_low_u *)&data_low);
+	hppe_rx_fifooverflow_frames_high_get(dev_id, port_id, (union rx_fifooverflow_frames_high_u *)&data_high);
+	mib_info->RxOverFlow =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_vlan_frames_good_bad_low_get(dev_id, port_id, (union rx_vlan_frames_good_bad_low_u *)&data_low);
+	hppe_rx_vlan_frames_good_bad_high_get(dev_id, port_id, (union rx_vlan_frames_good_bad_high_u*)&data_high);
+	mib_info->RxVLANFrameGoodBad =  (data_high<<32) |data_low;
+
+	data_low = 0;
+	hppe_rx_watchdog_error_frames_get(dev_id, port_id, (union rx_watchdog_error_frames_u*)&data_low);
+	mib_info->RxWatchDogError = data_low;
+
+	data_low = 0;
+	hppe_rx_lpi_usec_cntr_get(dev_id, port_id, (union rx_lpi_usec_cntr_u *)&data_low);
+	mib_info->RxLPIUsec = data_low;
+
+	data_low = 0;
+	hppe_rx_lpi_tran_cntr_get(dev_id, port_id, (union rx_lpi_tran_cntr_u *)&data_low);
+	mib_info->RxLPITran =   (data_high<<32) & data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_discard_frame_count_good_bad_low_get(dev_id, port_id, (union rx_discard_frame_count_good_bad_low_u *)&data_low);
+	hppe_rx_discard_frame_count_good_bad_high_get(dev_id, port_id, (union rx_discard_frame_count_good_bad_high_u *)&data_high);
+	mib_info->RxDropFrameGoodBad =  (data_high<<32) |data_low;
+
+	data_low = 0; data_high = 0;
+	hppe_rx_discard_octet_count_good_bad_low_get(dev_id, port_id, (union rx_discard_octet_count_good_bad_low_u *)&data_low);
+	hppe_rx_discard_octet_count_good_bad_high_get(dev_id, port_id, (union rx_discard_octet_count_good_bad_high_u *)&data_high);
+	mib_info->RxDropByteGoodBad =  (data_high<<32) |data_low;
+
+	return SW_OK;
+}
+
+sw_error_t adpt_hppe_mib_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_mib_func_unregister(dev_id, p_adpt_api);
+
+	if(p_adpt_api->adpt_mib_func_bitmap & (1<<FUNC_GET_MIB_INFO))
+	{
+		p_adpt_api->adpt_get_mib_info = adpt_ppe_get_mib_info;
+	}
+	if(p_adpt_api->adpt_mib_func_bitmap & (1<<FUNC_GET_RX_MIB_INFO))
+	{
+		p_adpt_api->adpt_get_rx_mib_info = adpt_ppe_get_rx_mib_info;
+	}
+	if(p_adpt_api->adpt_mib_func_bitmap & (1<<FUNC_GET_TX_MIB_INFO))
+	{
+		p_adpt_api->adpt_get_tx_mib_info = adpt_hppe_get_tx_mib_info;
+	}
+	if(p_adpt_api->adpt_mib_func_bitmap & (1<<FUNC_MIB_STATUS_SET))
+	{
+		p_adpt_api->adpt_mib_status_set = adpt_ppe_mib_status_set;
+	}
+	if(p_adpt_api->adpt_mib_func_bitmap & (1<<FUNC_MIB_STATUS_GET))
+	{
+		p_adpt_api->adpt_mib_status_get = adpt_hppe_mib_status_get;
+	}
+	if(p_adpt_api->adpt_mib_func_bitmap & (1<<FUNC_MIB_PORT_FLUSH_COUNTERS))
+	{
+		p_adpt_api->adpt_mib_port_flush_counters = adpt_ppe_mib_port_flush_counters;
+	}
+	if(p_adpt_api->adpt_mib_func_bitmap & (1<<FUNC_MIB_CPUKEEP_SET))
+	{
+		p_adpt_api->adpt_mib_cpukeep_set = adpt_ppe_mib_cpukeep_set;
+	}
+	if(p_adpt_api->adpt_mib_func_bitmap & (1<<FUNC_MIB_CPUKEEP_GET))
+	{
+		p_adpt_api->adpt_mib_cpukeep_get = adpt_hppe_mib_cpukeep_get;
+	}
+	if(p_adpt_api->adpt_mib_func_bitmap & (1<<FUNC_GET_XGMIB_INFO))
+	{
+		p_adpt_api->adpt_get_xgmib_info= adpt_hppe_get_xgmib_info;
+	}
+	if(p_adpt_api->adpt_mib_func_bitmap & (1<<FUNC_GET_TX_XGMIB_INFO))
+	{
+		p_adpt_api->adpt_get_tx_xgmib_info = adpt_hppe_get_tx_xgmib_info;
+	}
+	if(p_adpt_api->adpt_mib_func_bitmap & (1<<FUNC_GET_RX_XGMIB_INFO))
+	{
+		p_adpt_api->adpt_get_rx_xgmib_info = adpt_hppe_get_rx_xgmib_info;
+	}
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_mirror.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_mirror.c
new file mode 100755
index 0000000..346e95e
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_mirror.c
@@ -0,0 +1,345 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_mirror_reg.h"
+#include "hppe_mirror.h"
+#include "hppe_qm_reg.h"
+#include "hppe_qm.h"
+#include "adpt.h"
+
+sw_error_t
+adpt_hppe_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+	union port_mirror_u port_mirror;
+
+	memset(&port_mirror, 0, sizeof(port_mirror));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	/* mirror port just support physical port, not support trunk and virtual port */
+	if (FAL_PORT_ID_TYPE(port_id) != 0)
+		return SW_BAD_PARAM;
+
+	rv = hppe_port_mirror_get(dev_id, port_id, &port_mirror);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*enable = port_mirror.bf.in_mirr_en;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+	union port_mirror_u port_mirror;
+
+	memset(&port_mirror, 0, sizeof(port_mirror));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	/* mirror port just support physical port, not support trunk and virtual port */
+	if (FAL_PORT_ID_TYPE(port_id) != 0)
+		return SW_BAD_PARAM;
+
+	rv = hppe_port_mirror_get(dev_id, port_id, &port_mirror);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*enable = port_mirror.bf.eg_mirr_en;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+	sw_error_t rv = SW_OK;
+	union mirror_analyzer_u mirror_analyzer;
+
+	memset(&mirror_analyzer, 0, sizeof(mirror_analyzer));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(port_id);
+
+	/* analysis port just support physical port and trunk port, not support virtual port */
+	if (FAL_PORT_ID_TYPE(*port_id) != 0 && FAL_PORT_ID_TYPE(*port_id) != 1)
+		return SW_BAD_PARAM;
+
+	rv = hppe_mirror_analyzer_get(dev_id, &mirror_analyzer);
+
+	if( rv != SW_OK )
+		return rv;
+
+	if (mirror_analyzer.bf.in_analyzer_port != mirror_analyzer.bf.eg_analyzer_port)
+		return SW_FAIL;
+
+	*port_id = mirror_analyzer.bf.eg_analyzer_port;
+
+	if (*port_id == 32 || *port_id == 33)
+		*port_id = FAL_PORT_ID(FAL_PORT_TYPE_TRUNK, *port_id);
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+	union port_mirror_u port_mirror;
+
+	memset(&port_mirror, 0, sizeof(port_mirror));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	/* mirror port just support physical port, not support trunk and virtual port */
+	if (FAL_PORT_ID_TYPE(port_id) != 0)
+		return SW_BAD_PARAM;
+
+	hppe_port_mirror_get(dev_id, port_id, &port_mirror);
+	port_mirror.bf.in_mirr_en = enable;
+
+	hppe_port_mirror_set(dev_id, port_id, &port_mirror);
+
+	return SW_OK;
+}
+sw_error_t
+adpt_hppe_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+	union port_mirror_u port_mirror;
+
+	memset(&port_mirror, 0, sizeof(port_mirror));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	/* mirror port just support physical port, not support trunk and virtual port */
+	if (FAL_PORT_ID_TYPE(port_id) != 0)
+		return SW_BAD_PARAM;
+
+	hppe_port_mirror_get(dev_id, port_id, &port_mirror);
+	port_mirror.bf.eg_mirr_en = enable;
+
+	hppe_port_mirror_set(dev_id, port_id, &port_mirror);
+
+	return SW_OK;
+}
+sw_error_t
+adpt_hppe_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+	union mirror_analyzer_u mirror_analyzer;
+
+	memset(&mirror_analyzer, 0, sizeof(mirror_analyzer));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	/* analysis port just support physical port and trunk port, not support port */
+	if (FAL_PORT_ID_TYPE(port_id) != 0 && FAL_PORT_ID_TYPE(port_id) != 1)
+		return SW_BAD_PARAM;
+
+	port_id = FAL_PORT_ID_VALUE(port_id);
+
+	hppe_mirror_analyzer_get(dev_id, &mirror_analyzer);
+
+	mirror_analyzer.bf.in_analyzer_port = port_id;
+	mirror_analyzer.bf.eg_analyzer_port = port_id;
+
+	hppe_mirror_analyzer_set(dev_id, &mirror_analyzer);
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_mirr_analysis_config_set(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config)
+{
+	union mirror_analyzer_u mirror_analyzer;
+	union in_mirror_priority_ctrl_u in_mirror_priority_ctrl;
+	union eg_mirror_priority_ctrl_u eg_mirror_priority_ctrl;
+
+	memset(&mirror_analyzer, 0, sizeof(mirror_analyzer));
+	memset(&in_mirror_priority_ctrl, 0, sizeof(in_mirror_priority_ctrl));
+	memset(&eg_mirror_priority_ctrl, 0, sizeof(eg_mirror_priority_ctrl));
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	/* analysis port just support physical port and trunk port, not support port */
+	if (FAL_PORT_ID_TYPE(config->port_id) != 0 && FAL_PORT_ID_TYPE(config->port_id) != 1)
+		return SW_BAD_PARAM;
+
+	config->port_id = FAL_PORT_ID_VALUE(config->port_id);
+
+	hppe_mirror_analyzer_get(dev_id, &mirror_analyzer);
+
+	if (direction == FAL_MIRR_BOTH)
+	{
+		mirror_analyzer.bf.in_analyzer_port = config->port_id;
+		mirror_analyzer.bf.eg_analyzer_port = config->port_id;
+		in_mirror_priority_ctrl.bf.priority = config->priority;
+		eg_mirror_priority_ctrl.bf.priority = config->priority;
+		hppe_mirror_analyzer_set(dev_id, &mirror_analyzer);
+		hppe_in_mirror_priority_ctrl_set(dev_id, &in_mirror_priority_ctrl);
+		hppe_eg_mirror_priority_ctrl_set(dev_id, &eg_mirror_priority_ctrl);
+	}
+	else if (direction == FAL_MIRR_INGRESS)
+	{
+		mirror_analyzer.bf.in_analyzer_port = config->port_id;
+		in_mirror_priority_ctrl.bf.priority = config->priority;
+		hppe_mirror_analyzer_set(dev_id, &mirror_analyzer);
+		hppe_in_mirror_priority_ctrl_set(dev_id, &in_mirror_priority_ctrl);
+	}
+	else if (direction == FAL_MIRR_EGRESS)
+	{
+		mirror_analyzer.bf.eg_analyzer_port = config->port_id;
+		eg_mirror_priority_ctrl.bf.priority = config->priority;
+		hppe_mirror_analyzer_set(dev_id, &mirror_analyzer);
+		hppe_eg_mirror_priority_ctrl_set(dev_id, &eg_mirror_priority_ctrl);
+	}
+	else
+		return SW_NOT_SUPPORTED;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_mirr_analysis_config_get(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config)
+{
+	union mirror_analyzer_u mirror_analyzer;
+	union in_mirror_priority_ctrl_u in_mirror_priority_ctrl;
+	union eg_mirror_priority_ctrl_u eg_mirror_priority_ctrl;
+
+	memset(&mirror_analyzer, 0, sizeof(mirror_analyzer));
+	memset(&in_mirror_priority_ctrl, 0, sizeof(in_mirror_priority_ctrl));
+	memset(&eg_mirror_priority_ctrl, 0, sizeof(eg_mirror_priority_ctrl));
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(config);
+	/* analysis port just support physical port and trunk port, not support virtual port */
+	if (FAL_PORT_ID_TYPE(config->port_id) != 0 && FAL_PORT_ID_TYPE(config->port_id) != 1)
+		return SW_BAD_PARAM;
+
+	hppe_mirror_analyzer_get(dev_id, &mirror_analyzer);
+	hppe_in_mirror_priority_ctrl_get(dev_id, &in_mirror_priority_ctrl);
+	hppe_eg_mirror_priority_ctrl_get(dev_id, &eg_mirror_priority_ctrl);
+
+	if (direction == FAL_MIRR_BOTH)
+	{
+		if ((mirror_analyzer.bf.in_analyzer_port != mirror_analyzer.bf.eg_analyzer_port) ||
+			(in_mirror_priority_ctrl.bf.priority != eg_mirror_priority_ctrl.bf.priority))
+			return SW_FAIL;
+
+		config->port_id = mirror_analyzer.bf.in_analyzer_port;
+		config->priority = in_mirror_priority_ctrl.bf.priority;
+	}
+	else if (direction == FAL_MIRR_INGRESS)
+	{
+		config->port_id = mirror_analyzer.bf.in_analyzer_port;
+		config->priority = in_mirror_priority_ctrl.bf.priority;
+	}
+	else if (direction == FAL_MIRR_EGRESS)
+	{
+		config->port_id = mirror_analyzer.bf.eg_analyzer_port;
+		config->priority = eg_mirror_priority_ctrl.bf.priority;
+	}
+	else
+		return SW_NOT_SUPPORTED;
+
+	if (config->port_id == 32 || config->port_id == 33)
+		config->port_id = FAL_PORT_ID(FAL_PORT_TYPE_TRUNK, config->port_id);
+
+	return SW_OK;
+}
+
+void adpt_hppe_mirror_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_mirror_func_bitmap = ((1 << FUNC_MIRR_ANALYSIS_PORT_SET) |
+						(1 << FUNC_MIRR_ANALYSIS_PORT_GET) |
+						(1 << FUNC_MIRR_PORT_IN_SET) |
+						(1 << FUNC_MIRR_PORT_IN_GET) |
+						(1 << FUNC_MIRR_PORT_EG_SET) |
+						(1 << FUNC_MIRR_PORT_EG_GET) |
+						(1 << FUNC_MIRR_ANALYSIS_CONFIG_SET) |
+						(1 << FUNC_MIRR_ANALYSIS_CONFIG_GET));
+
+	return;
+}
+
+static void adpt_hppe_mirror_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_mirr_port_in_set = NULL;
+	p_adpt_api->adpt_mirr_port_in_get = NULL;
+	p_adpt_api->adpt_mirr_port_eg_set = NULL;
+	p_adpt_api->adpt_mirr_port_eg_get = NULL;
+	p_adpt_api->adpt_mirr_analysis_port_set = NULL;
+	p_adpt_api->adpt_mirr_analysis_port_get = NULL;
+	p_adpt_api->adpt_mirr_analysis_config_set = NULL;
+	p_adpt_api->adpt_mirr_analysis_config_get = NULL;
+
+	return;
+}
+
+
+
+
+sw_error_t adpt_hppe_mirror_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_mirror_func_unregister(dev_id, p_adpt_api);
+
+	if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_PORT_IN_SET))
+		p_adpt_api->adpt_mirr_port_in_set = adpt_hppe_mirr_port_in_set;
+	if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_PORT_IN_GET))
+		p_adpt_api->adpt_mirr_port_in_get = adpt_hppe_mirr_port_in_get;
+	if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_PORT_EG_SET))
+		p_adpt_api->adpt_mirr_port_eg_set = adpt_hppe_mirr_port_eg_set;
+	if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_PORT_EG_GET))
+		p_adpt_api->adpt_mirr_port_eg_get = adpt_hppe_mirr_port_eg_get;
+	if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_ANALYSIS_PORT_SET))
+		p_adpt_api->adpt_mirr_analysis_port_set = adpt_hppe_mirr_analysis_port_set;
+	if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_ANALYSIS_PORT_GET))
+		p_adpt_api->adpt_mirr_analysis_port_get = adpt_hppe_mirr_analysis_port_get;
+	if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_ANALYSIS_CONFIG_SET))
+		p_adpt_api->adpt_mirr_analysis_config_set = adpt_hppe_mirr_analysis_config_set;
+	if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_ANALYSIS_CONFIG_GET))
+		p_adpt_api->adpt_mirr_analysis_config_get = adpt_hppe_mirr_analysis_config_get;
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_misc.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_misc.c
new file mode 100755
index 0000000..e3dbd31
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_misc.c
@@ -0,0 +1,1011 @@
+/*
+ * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_portctrl_reg.h"
+#include "hppe_portctrl.h"
+#include "hppe_portvlan_reg.h"
+#include "hppe_portvlan.h"
+#include "hppe_vsi_reg.h"
+#include "hppe_vsi.h"
+#include "hppe_policer_reg.h"
+#include "hppe_policer.h"
+#include "hppe_qm_reg.h"
+#include "hppe_qm.h"
+#include "adpt_hppe.h"
+#include "adpt.h"
+#if defined(CPPE)
+#include "adpt_cppe_misc.h"
+#endif
+
+
+#ifndef IN_MISC_MINI
+char cpucode[][85] = {
+"Forwarding to CPU",
+"Unkown L2 protocol exception redirect/copy to CPU",
+"PPPoE wrong version or wrong type exception redirect/copy to CPU",
+"PPPoE wrong code exception redirect/copy to CPU",
+"PPPoE unsupported PPP protocol exception redirect/copy to CPU",
+"IPv4 wrong version exception redirect/copy to CPU",
+"IPv4 small IHL exception redirect/copy to CPU",
+"IPv4 with option exception redirect/copy to CPU",
+"IPv4 header incomplete exception redirect/copy to CPU",
+"IPv4 bad total length exception redirect/copy to CPU",
+"IPv4 data incomplete exception redirect/copy to CPU",
+"IPv4 fragment exception redirect/copy to CPU",
+"IPv4 ping of death exception redirect/copy to CPU",
+"IPv4 small TTL exception redirect/copy to CPU",
+"IPv4 unknown IP protocol exception redirect/copy to CPU",
+"IPv4 checksum error exception redirect/copy to CPU",
+"IPv4 invalid SIP exception redirect/copy to CPU",
+"IPv4 invalid DIP exception redirect/copy to CPU",
+"IPv4 LAND attack exception redirect/copy to CPU",
+"IPv4 AH header incomplete exception redirect/copy to CPU",
+"IPv4 AH header cross 128-byte exception redirect/copy to CPU",
+"IPv4 ESP header incomplete exception redirect/copy to CPU",
+"IPv6 wrong version exception redirect/copy to CPU",
+"IPv6 header incomplete exception redirect/copy to CPU",
+"IPv6 bad total length exception redirect/copy to CPU",
+"IPv6 data incomplete exception redirect/copy to CPU",
+"IPv6 with extension header exception redirect/copy to CPU",
+"IPv6 small hop limit exception redirect/copy to CPU",
+"IPv6 invalid SIP exception redirect/copy to CPU",
+"IPv6 invalid DIP exception redirect/copy to CPU",
+"IPv6 LAND attack exception redirect/copy to CPU",
+"IPv6 fragment exception redirect/copy to CPU",
+"IPv6 ping of death exception redirect/copy to CPU",
+"IPv6 with more than 2 extension headers exception redirect/copy to CPU",
+"IPv6 unknown last next header exception redirect/copy to CPU",
+"IPv6 mobility header incomplete exception redirect/copy to CPU",
+"IPv6 mobility header cross 128-byte exception redirect/copy to CPU",
+"IPv6 AH header incomplete exception redirect/copy to CPU",
+"IPv6 AH header cross 128-byte exception redirect/copy to CPU",
+"IPv6 ESP header incomplete exception redirect/copy to CPU",
+"IPv6 ESP header cross 128-byte exception redirect/copy to CPU",
+"IPv6 other extension header incomplete exception redirect/copy to CPU",
+"IPv6 other extension header cross 128-byte exception redirect/copy to CPU",
+"TCP header incomplete exception redirect/copy to CPU",
+"TCP header cross 128-byte exception redirect/copy to CPU",
+"TCP same SP and DP exception redirect/copy to CPU",
+"TCP small data offset redirect/copy to CPU",
+"TCP flags VALUE/MASK group 0 exception redirect/copy to CPU",
+"TCP flags VALUE/MASK group 1 exception redirect/copy to CPU",
+"TCP flags VALUE/MASK group 2 exception redirect/copy to CPU",
+"TCP flags VALUE/MASK group 3 exception redirect/copy to CPU",
+"TCP flags VALUE/MASK group 4 exception redirect/copy to CPU",
+"TCP flags VALUE/MASK group 5 exception redirect/copy to CPU",
+"TCP flags VALUE/MASK group 6 exception redirect/copy to CPU",
+"TCP flags VALUE/MASK group 7 exception redirect/copy to CPU",
+"TCP checksum error exception redirect/copy to CPU",
+"UDP header incomplete exception redirect/copy to CPU",
+"UDP header cross 128-byte exception redirect/copy to CPU",
+"UDP same SP and DP exception redirect/copy to CPU",
+"UDP bad length exception redirect/copy to CPU",
+"UDP data incomplete exception redirect/copy to CPU",
+"UDP checksum error exception redirect/copy to CPU",
+"UDP-Lite header incomplete exception redirect/copy to CPU",
+"UDP-Lite header cross 128-byte exception redirect/copy to CPU",
+"UDP-Lite same SP and DP exception redirect/copy to CPU",
+"UDP-Lite checksum coverage value 0-7 exception redirect/copy to CPU",
+"UDP-Lite checksum coverage value too big exception redirect/copy to CPU",
+"UDP-Lite checksum coverage value cross 128-byte exception redirect/copy to CPU",
+"UDP-Lite checksum error exception redirect/copy to CPU",
+"Fake L2 protocol packet redirect/copy to CPU",
+"Fake MAC header packet redirect/copy to CPU",
+"L2 MRU checking fail redirect/copy to CPU",
+"L2 MTU checking fail redirect/copy to CPU",
+"IP prefix broadcast redirect/copy to CPU",
+"L3 MTU checking fail redirect/copy to CPU",
+"L3 MRU checking fail redirect/copy to CPU",
+"ICMP redirect/copy to CPU",
+"IP to me routing TTL 1 redirect/copy to CPU",
+"IP to me routing TTL 0 redirect/copy to CPU",
+"Flow service code loop redirect/copy to CPU",
+"Flow de-accelearate redirect/copy to CPU",
+"Flow source interface check fail redirect/copy to CPU",
+"Flow sync toggle mismatch redirect/copy to CPU",
+"MTU check fail if DF set redirect/copy to CPU",
+"PPPoE multicast redirect/copy to CPU",
+"EAPoL packet redirect/copy to CPU",
+"PPPoE discovery packet redirect/copy to CPU",
+"IGMP packet redirect/copy to CPU",
+"ARP request packet redirect/copy to CPU",
+"ARP reply packet redirect/copy to CPU",
+"DHCPv4 packet redirect/copy to CPU",
+"MLD packet redirect/copy to CPU",
+"NS packet redirect/copy to CPU",
+"NA packet redirect/copy to CPU",
+"DHCPv6 packet redirect/copy to CPU",
+"PTP sync packet redirect/copy to CPU",
+"PTP follow up packet redirect/copy to CPU",
+"PTP delay request packet redirect/copy to CPU",
+"PTP delay response packet redirect/copy to CPU",
+"PTP pdelay request packet redirect/copy to CPU",
+"PTP pdelay response packet redirect/copy to CPU",
+"PTP pdelay response follow up packet redirect/copy to CPU",
+"PTP announce packet redirect/copy to CPU",
+"PTP management packet redirect/copy to CPU",
+"PTP signaling packet redirect/copy to CPU",
+"PTP message reserved type 0 packet redirect/copy to CPU",
+"PTP message reserved type 1 packet redirect/copy to CPU",
+"PTP message reserved type 2 packet redirect/copy to CPU",
+"PTP message reserved type 3 packet redirect/copy to CPU",
+"PTP message reserved type packet redirect/copy to CPU",
+"IPv4 source guard unknown packet redirect/copy to CPU",
+"IPv6 source guard unknown packet redirect/copy to CPU",
+"ARP source guard unknown packet redirect/copy to CPU",
+"ND source guard unknown packet redirect/copy to CPU",
+"IPv4 source guard violation packet redirect/copy to CPU",
+"IPv6 source guard violation packet redirect/copy to CPU",
+"ARP source guard violation packet redirect/copy to CPU",
+"ND source guard violation packet redirect/copy to CPU",
+"L3 route host mismatch action redirect/copy to CPU",
+"L3 flow SNAT action redirect/copy to CPU",
+"L3 flow DNAT action redirect/copy to CPU",
+"L3 flow routing action redirect/copy to CPU",
+"L3 flow bridging action redirect/copy to CPU",
+"L3 multicast bridging action redirect/copy to CPU",
+"L3 route Preheader routing action redirect/copy to CPU",
+"L3 route Preheader SNAPT action redirect/copy to CPU",
+"L3 route Preheader DNAPT action redirect/copy to CPU",
+"L3 route Preheader SNAT action redirect/copy to CPU",
+"L3 route Preheader DNAT action redirect/copy to CPU",
+"L3 no route preheader NAT action redirect/copy to CPU",
+"L3 no route preheader NAT error redirect/copy to CPU",
+"L3 route action redirect/copy to CPU",
+"L3 no route action redirect/copy to CPU",
+"L3 no route next hop invalid action redirect/copy to CPU",
+"L3 no route preheader action redirect/copy to CPU",
+"L3 bridge action redirect/copy to CPU",
+"L3 flow action redirect/copy to CPU",
+"L3 flow miss action redirect/copy to CPU",
+"L2 new MAC address redirect/copy to CPU",
+"L2 hash violation redirect/copy to CPU",
+"L2 station move redirect/copy to CPU",
+"L2 learn limit redirect/copy to CPU",
+"L2 SA lookup action redirect/copy to CPU",
+"L2 DA lookup action redirect/copy to CPU",
+"APP_CTRL action redirect/copy to CPU",
+"Pre-IPO action",
+"Post-IPO action",
+"Service code action",
+"Egress mirror to CPU",
+"Ingress mirror to CPU",
+};
+
+char dropcode[][75] = {
+"None",
+"Unkown L2 protocol exception drop",
+"PPPoE wrong version or wrong type exception drop",
+"PPPoE wrong code exception drop",
+"PPPoE unsupported PPP protocol exception drop",
+"IPv4 wrong version exception drop",
+"IPv4 small IHL exception drop",
+"IPv4 with option exception drop",
+"IPv4 header incomplete exception drop",
+"IPv4 bad total length exception drop",
+"IPv4 data incomplete exception drop",
+"IPv4 fragment exception drop",
+"IPv4 ping of death exception drop",
+"IPv4 small TTL exception drop",
+"IPv4 unknown IP protocol exception drop",
+"IPv4 checksum error exception drop",
+"IPv4 invalid SIP exception drop",
+"IPv4 invalid DIP exception drop",
+"IPv4 LAND attack exception drop",
+"IPv4 AH header incomplete exception drop",
+"IPv4 AH header cross 128-byte exception drop",
+"IPv4 ESP header incomplete exception drop",
+"IPv6 wrong version exception drop",
+"IPv6 header incomplete exception drop",
+"IPv6 bad total length exception drop",
+"IPv6 data incomplete exception drop",
+"IPv6 with extension header exception drop",
+"IPv6 small hop limit exception drop",
+"IPv6 invalid SIP exception drop",
+"IPv6 invalid DIP exception drop",
+"IPv6 LAND attack exception drop",
+"IPv6 fragment exception drop",
+"IPv6 ping of death exception drop",
+"IPv6 with more than 2 extension headers exception drop",
+"IPv6 unknown last next header exception drop",
+"IPv6 mobility header incomplete exception drop",
+"IPv6 mobility header cross 128-byte exception drop",
+"IPv6 AH header incomplete exception drop",
+"IPv6 AH header cross 128-byte exception drop",
+"IPv6 ESP header incomplete exception drop",
+"IPv6 ESP header cross 128-byte exception drop",
+"IPv6 other extension header incomplete exception drop",
+"IPv6 other extension header cross 128-byte exception drop",
+"TCP header incomplete exception drop",
+"TCP header cross 128-byte exception drop",
+"TCP same SP and DP exception drop",
+"TCP small data offset drop",
+"TCP flags VALUE/MASK group 0 exception drop",
+"TCP flags VALUE/MASK group 1 exception drop",
+"TCP flags VALUE/MASK group 2 exception drop",
+"TCP flags VALUE/MASK group 3 exception drop",
+"TCP flags VALUE/MASK group 4 exception drop",
+"TCP flags VALUE/MASK group 5 exception drop",
+"TCP flags VALUE/MASK group 6 exception drop",
+"TCP flags VALUE/MASK group 7 exception drop",
+"TCP checksum error exception drop",
+"UDP header incomplete exception drop",
+"UDP header cross 128-byte exception drop",
+"UDP same SP and DP exception drop",
+"UDP bad length exception drop",
+"UDP data incomplete exception drop",
+"UDP checksum error exception drop",
+"UDP-Lite header incomplete exception drop",
+"UDP-Lite header cross 128-byte exception drop",
+"UDP-Lite same SP and DP exception drop",
+"UDP-Lite checksum coverage value 0-7 exception drop",
+"UDP-Lite checksum coverage value too big exception drop",
+"UDP-Lite checksum coverage value cross 128-byte exception drop",
+"UDP-Lite checksum error exception drop",
+"L3 multicast bridging action",
+"L3 no route with Preheader NAT action",
+"L3 no route with Preheader NAT action error configuration",
+"L3 route action drop",
+"L3 no route action drop",
+"L3 no route next hop invalid action drop",
+"L3 no route preheader action drop",
+"L3 bridge action drop",
+"L3 flow action drop",
+"L3 flow miss action drop",
+"L2 MRU checking fail drop",
+"L2 MTU checking fail drop",
+"L3 IP prefix broadcast drop",
+"L3 MTU checking fail drop",
+"L3 MRU checking fail drop",
+"L3 ICMP redirect drop",
+"Fake MAC header indicated packet not routing or bypass L3 edit drop",
+"L3 IP route TTL zero drop",
+"L3 flow service code loop drop",
+"L3 flow de-accelerate drop",
+"L3 flow source interface check fail drop",
+"Flow toggle mismatch exception drop",
+"MTU check exception if DF set drop",
+"PPPoE multicast packet with IP routing enabled drop",
+"IPv4 SG unkown drop",
+"IPv6 SG unkown drop",
+"ARP SG unkown drop",
+"ND SG unkown drop",
+"IPv4 SG violation drop",
+"IPv6 SG violation drop",
+"ARP SG violation drop",
+"ND SG violation drop",
+"L2 new MAC address drop",
+"L2 hash violation drop",
+"L2 station move drop",
+"L2 learn limit drop",
+"L2 SA lookup action drop",
+"L2 DA lookup action drop",
+"APP_CTRL action drop",
+"Ingress VLAN filtering action drop",
+"Ingress VLAN translation miss drop",
+"Egress VLAN filtering drop",
+"Pre-IPO entry hit action drop",
+"Post-IPO entry hit action drop",
+"Multicast SA or broadcast SA drop",
+"No destination drop",
+"STG ingress filtering drop",
+"STG egress filtering drop",
+"Source port filter drop",
+"Trunk select fail drop",
+"TX MAC disable drop",
+"Ingress VLAN tag format drop",
+"CRC error drop",
+"PAUSE frame drop",
+"Promisc drop",
+"Isolation drop",
+"Magagement packet APP_CTRL drop",
+"Fake L2 protocol indicated packet not routing or bypass L3 edit drop",
+"Policing drop"
+};
+
+sw_error_t
+adpt_hppe_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id,
+		fal_counter_en_t *cnt_en)
+{
+	union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;
+	union mc_mtu_ctrl_tbl_u mc_mtu_ctrl_tbl;
+	union port_eg_vlan_u port_eg_vlan;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cnt_en);
+
+	port_id = FAL_PORT_ID_VALUE(port_id);
+
+	if (port_id < SSDK_MAX_PORT_NUM) {
+		SW_RTN_ON_ERROR(hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl));
+		SW_RTN_ON_ERROR(hppe_mc_mtu_ctrl_tbl_get(dev_id, port_id, &mc_mtu_ctrl_tbl));
+		SW_RTN_ON_ERROR(hppe_port_eg_vlan_get(dev_id, port_id, &port_eg_vlan));
+		mru_mtu_ctrl_tbl.bf.rx_cnt_en = cnt_en->rx_counter_en;
+		mru_mtu_ctrl_tbl.bf.tx_cnt_en = cnt_en->vp_uni_tx_counter_en;
+		mc_mtu_ctrl_tbl.bf.tx_cnt_en = cnt_en->port_mc_tx_counter_en;
+		port_eg_vlan.bf.tx_counting_en = cnt_en->port_tx_counter_en;
+		SW_RTN_ON_ERROR(hppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &mru_mtu_ctrl_tbl));
+		SW_RTN_ON_ERROR(hppe_mc_mtu_ctrl_tbl_set(dev_id, port_id, &mc_mtu_ctrl_tbl));
+		SW_RTN_ON_ERROR(hppe_port_eg_vlan_set(dev_id, port_id, &port_eg_vlan));
+	}
+	else if (port_id >= SSDK_MAX_PORT_NUM &&
+			port_id < SSDK_MAX_VIRTUAL_PORT_NUM) {
+		SW_RTN_ON_ERROR(hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl));
+		mru_mtu_ctrl_tbl.bf.rx_cnt_en = cnt_en->rx_counter_en;
+		mru_mtu_ctrl_tbl.bf.tx_cnt_en = cnt_en->vp_uni_tx_counter_en;
+		SW_RTN_ON_ERROR(hppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &mru_mtu_ctrl_tbl));
+	} else {
+		return SW_OUT_OF_RANGE;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_ppe_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id,
+		fal_counter_en_t *cnt_en)
+{
+	a_uint32_t chip_ver = 0;
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+#if defined(CPPE)
+	if (chip_ver == CPPE_REVISION) {
+		return adpt_cppe_debug_port_counter_enable(dev_id, port_id, cnt_en);
+	} else
+#endif
+	{
+		return adpt_hppe_debug_port_counter_enable(dev_id, port_id, cnt_en);
+	}
+}
+
+sw_error_t
+adpt_hppe_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_counter_en_t *cnt_en)
+{
+	union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;
+	union mc_mtu_ctrl_tbl_u mc_mtu_ctrl_tbl;
+	union port_eg_vlan_u port_eg_vlan;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cnt_en);
+
+	port_id = FAL_PORT_ID_VALUE(port_id);
+
+	if (port_id < SSDK_MAX_PORT_NUM) {
+		SW_RTN_ON_ERROR(hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl));
+		SW_RTN_ON_ERROR(hppe_mc_mtu_ctrl_tbl_get(dev_id, port_id, &mc_mtu_ctrl_tbl));
+		SW_RTN_ON_ERROR(hppe_port_eg_vlan_get(dev_id, port_id, &port_eg_vlan));
+		cnt_en->rx_counter_en = mru_mtu_ctrl_tbl.bf.rx_cnt_en;
+		cnt_en->vp_uni_tx_counter_en = mru_mtu_ctrl_tbl.bf.tx_cnt_en;
+		cnt_en->port_mc_tx_counter_en = mc_mtu_ctrl_tbl.bf.tx_cnt_en;
+		cnt_en->port_tx_counter_en = port_eg_vlan.bf.tx_counting_en;
+	} else if (port_id >= SSDK_MAX_PORT_NUM &&
+			port_id < SSDK_MAX_VIRTUAL_PORT_NUM) {
+		SW_RTN_ON_ERROR(hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl));
+		cnt_en->rx_counter_en = mru_mtu_ctrl_tbl.bf.rx_cnt_en;
+		cnt_en->vp_uni_tx_counter_en = mru_mtu_ctrl_tbl.bf.tx_cnt_en;
+	} else {
+		return SW_OUT_OF_RANGE;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_ppe_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_counter_en_t *cnt_en)
+{
+	a_uint32_t chip_ver = 0;
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+#if defined(CPPE)
+	if (chip_ver == CPPE_REVISION) {
+		return adpt_cppe_debug_port_counter_status_get(dev_id, port_id, cnt_en);
+	} else
+#endif
+	{
+		return adpt_hppe_debug_port_counter_status_get(dev_id, port_id, cnt_en);
+	}
+}
+
+sw_error_t
+adpt_hppe_debug_counter_set(void)
+{
+	union vlan_cnt_tbl_u vlan_cnt_tbl = {0};
+	union pre_l2_cnt_tbl_u pre_l2_cnt_tbl = {0};
+	union port_tx_drop_cnt_tbl_u port_tx_drop_cnt_tbl = {0};
+	union eg_vsi_counter_tbl_u eg_vsi_counter_tbl = {0};
+	union port_tx_counter_tbl_reg_u port_tx_counter_tbl = {0};
+	union vp_tx_counter_tbl_reg_u vp_tx_counter_tbl = {0};
+	union queue_tx_counter_tbl_u queue_tx_counter_tbl = {0};
+	union epe_dbg_in_cnt_reg_u epe_dbg_in_cnt = {0};
+	union epe_dbg_out_cnt_reg_u epe_dbg_out_cnt = {0};
+	union vp_tx_drop_cnt_tbl_u vp_tx_drop_cnt_tbl = {0};
+	union drop_cpu_cnt_tbl_u drop_cpu_cnt_tbl = {0};
+
+	a_uint32_t i;
+
+	/* clear PRX DROP_CNT */
+	for (i = 0; i < DROP_CNT_MAX_ENTRY; i++)
+		hppe_drop_cnt_drop_cnt_set(0, i, 0);
+
+	/* clear PRX DROP_PKT_STAT */
+	for (i = 0; i < DROP_PKT_STAT_MAX_ENTRY; i++) {
+		hppe_drop_stat_pkts_set(0, i, 0);
+		hppe_drop_stat_bytes_set(0, i, 0);
+	}
+
+	/* clear IPR_PKT_NUM */
+	for (i = 0; i < IPR_PKT_NUM_TBL_REG_MAX_ENTRY; i++) {
+		hppe_ipr_pkt_num_tbl_reg_packets_set(0, i, 0);
+		hppe_ipr_byte_low_reg_reg_bytes_set(0, i, 0);
+		hppe_ipr_byte_high_reg_bytes_set(0, i, 0);
+	}
+
+	/* clear VLAN_CNT_TBL */
+	for (i = 0; i < VLAN_CNT_TBL_MAX_ENTRY; i++)
+		hppe_vlan_cnt_tbl_set(0, i, &vlan_cnt_tbl);
+
+	/* clear PRE_L2_CNT_TBL */
+	for (i = 0; i < PRE_L2_CNT_TBL_MAX_ENTRY; i++)
+		hppe_pre_l2_cnt_tbl_set(0, i, &pre_l2_cnt_tbl);
+
+	/* clear PORT_TX_DROP_CNT_TBL */
+	for (i = 0; i < PORT_TX_DROP_CNT_TBL_MAX_ENTRY; i++)
+		hppe_port_tx_drop_cnt_tbl_set(0, i, &port_tx_drop_cnt_tbl);
+
+	/* clear EG_VSI_COUNTER_TBL */
+	for (i = 0; i < EG_VSI_COUNTER_TBL_MAX_ENTRY; i++)
+		hppe_eg_vsi_counter_tbl_set(0, i, &eg_vsi_counter_tbl);
+
+	/* clear PORT_TX_COUNTER_TBL */
+	for (i = 0; i < PORT_TX_COUNTER_TBL_REG_MAX_ENTRY; i++)
+		hppe_port_tx_counter_tbl_reg_set(0, i, &port_tx_counter_tbl);
+
+	/* clear VP_TX_COUNTER_TBL */
+	for (i = 0; i < VP_TX_COUNTER_TBL_REG_MAX_ENTRY; i++)
+		hppe_vp_tx_counter_tbl_reg_set(0, i, &vp_tx_counter_tbl);
+
+	/* clear QUEUE_TX_COUNTER_TBL */
+	for (i = 0; i < QUEUE_TX_COUNTER_TBL_MAX_ENTRY; i++)
+		hppe_queue_tx_counter_tbl_set(0, i, &queue_tx_counter_tbl);
+
+	/* clear EPE_DBG_IN_CNT & EPE_DBG_OUT_CNT */
+	hppe_epe_dbg_in_cnt_reg_set(0, &epe_dbg_in_cnt);
+	hppe_epe_dbg_out_cnt_reg_set(0, &epe_dbg_out_cnt);
+
+	/* clear VP_TX_DROP_CNT_TBL */
+	for (i = 0; i < VP_TX_DROP_CNT_TBL_MAX_ENTRY; i++)
+		hppe_vp_tx_drop_cnt_tbl_set(0, i, &vp_tx_drop_cnt_tbl);
+
+	/* clear DROP_CPU_CNT_TBL */
+	for (i = 0; i < DROP_CPU_CNT_TBL_MAX_ENTRY; i++)
+		hppe_drop_cpu_cnt_tbl_set(0, i, &drop_cpu_cnt_tbl);
+
+	return SW_OK;
+}
+
+void
+adpt_hppe_debug_prx_drop_cnt_get(void)
+{
+	a_uint32_t value;
+	int i, tags, sign;
+
+	sign = tags = 0;
+	printk("%-35s", "PRX_DROP_CNT RX:");
+	for (i = 0; i < DROP_CNT_MAX_ENTRY; i++)
+	{
+		hppe_drop_cnt_drop_cnt_get(0, i, &value);
+		if (value > 0)
+		{
+			if (sign) {
+				printk(KERN_CONT "\n");
+				printk(KERN_CONT "%-35s", "");
+			}
+			sign = 0;
+			printk(KERN_CONT "%15u(port=%04d)", value, i);
+			if (++tags % 3 == 0)
+				sign = 1;
+		}
+	}
+	printk(KERN_CONT "\n");
+}
+
+void
+adpt_hppe_debug_prx_drop_pkt_stat_get(a_bool_t show_type)
+{
+	a_uint32_t value32;
+	a_uint64_t value;
+	int i, tags, sign;
+
+	sign = tags = 0;
+	printk("%-35s", "PRX_DROP_PKT_STAT RX:");
+	for (i = 0; i < DROP_PKT_STAT_MAX_ENTRY; i++)
+	{
+		if (show_type == A_FALSE)
+		{
+			hppe_drop_stat_pkts_get(0, i, &value32);
+			value = (a_uint64_t)value32;
+		}
+		else
+			hppe_drop_stat_bytes_get(0, i, &value);
+		if (value > 0)
+		{
+			if (sign) {
+				printk(KERN_CONT "\n");
+				printk(KERN_CONT "%-35s", "");
+			}
+			sign = 0;
+			printk(KERN_CONT "%15llu(port=%04d)", value, i);
+			if (++tags % 3 == 0)
+				sign = 1;
+		}
+	}
+	printk(KERN_CONT "\n");
+}
+
+void
+adpt_hppe_debug_ipx_pkt_num_get(a_bool_t show_type)
+{
+	union ipr_pkt_num_tbl_reg_u ipr_pkt_num_tbl_reg;
+	union ipr_byte_low_reg_reg_u ipr_byte_low_reg;
+	union ipr_byte_high_reg_u ipr_byte_high_reg;
+	a_uint64_t value;
+	int i, tags, sign;
+
+	sign = tags = 0;
+	printk("%-35s", "IPR_PKT_NUM RX:");
+	for (i = 0; i < IPR_PKT_NUM_TBL_REG_MAX_ENTRY; i++)
+	{
+		hppe_ipr_pkt_num_tbl_reg_get(0, i, &ipr_pkt_num_tbl_reg);
+		hppe_ipr_byte_low_reg_reg_get(0, i, &ipr_byte_low_reg);
+		hppe_ipr_byte_high_reg_get(0, i, &ipr_byte_high_reg);
+		if (show_type == A_FALSE)
+			value = (a_uint64_t)ipr_pkt_num_tbl_reg.bf.packets;
+		else
+			value = ipr_byte_low_reg.bf.bytes | ((a_uint64_t)ipr_byte_high_reg.bf.bytes << 32);
+
+		if (value > 0)
+		{
+			if (sign) {
+				printk(KERN_CONT "\n");
+				printk(KERN_CONT "%-35s", "");
+			}
+			sign = 0;
+			printk(KERN_CONT "%15llu(port=%04d)", value, i);
+			if (++tags % 3 == 0)
+				sign = 1;
+		}
+	}
+	printk(KERN_CONT "\n");
+}
+
+void
+adpt_hppe_debug_vlan_counter_get(a_bool_t show_type)
+{
+	union vlan_cnt_tbl_u vlan_cnt_tbl;
+	a_uint64_t value;
+	int i, tags, sign;
+
+	sign = tags = 0;
+	printk("%-35s", "VLAN_CNT_TBL RX:");
+	for (i = 0; i < VLAN_CNT_TBL_MAX_ENTRY; i++)
+	{
+		hppe_vlan_cnt_tbl_get(0, i, &vlan_cnt_tbl);
+		if (show_type == A_FALSE)
+			value = (a_uint64_t)vlan_cnt_tbl.bf.rx_pkt_cnt;
+		else
+			value = vlan_cnt_tbl.bf.rx_byte_cnt_0 | ((a_uint64_t)vlan_cnt_tbl.bf.rx_byte_cnt_1 << 32);
+		if (value > 0)
+		{
+			if (sign) {
+				printk(KERN_CONT "\n");
+				printk(KERN_CONT "%-35s", "");
+			}
+			sign = 0;
+			printk(KERN_CONT "%15llu(vsi=%04d)", value, i);
+			if (++tags % 3 == 0)
+				sign = 1;
+		}
+	}
+	printk(KERN_CONT "\n");
+}
+
+void
+adpt_hppe_debug_pre_l2_counter_get(a_bool_t show_type)
+{
+	union pre_l2_cnt_tbl_u pre_l2_cnt_tbl;
+	a_uint64_t value;
+	int i, tags, sign;
+
+	sign = tags = 0;
+	printk("%-35s", "PRE_L2_CNT_TBL RX:");
+	for (i = 0; i < PRE_L2_CNT_TBL_MAX_ENTRY; i++)
+	{
+		hppe_pre_l2_cnt_tbl_get(0, i, &pre_l2_cnt_tbl);
+		if (show_type == A_FALSE)
+			value = (a_uint64_t)pre_l2_cnt_tbl.bf.rx_pkt_cnt;
+		else
+			value = pre_l2_cnt_tbl.bf.rx_byte_cnt_0 | ((a_uint64_t)pre_l2_cnt_tbl.bf.rx_byte_cnt_1 << 32);
+		if (value > 0)
+		{
+			if (sign) {
+				printk(KERN_CONT "\n");
+				printk(KERN_CONT "%-35s", "");
+			}
+			sign = 0;
+			printk(KERN_CONT "%15llu(vsi=%04d)", value, i);
+			if (++tags % 3 == 0)
+				sign = 1;
+		}
+	}
+	printk(KERN_CONT "\n");
+
+	sign = tags = 0;
+	printk("%-35s", "PRE_L2_CNT_TBL RX_DROP:");
+	for (i = 0; i < PRE_L2_CNT_TBL_MAX_ENTRY; i++)
+	{
+		hppe_pre_l2_cnt_tbl_get(0, i, &pre_l2_cnt_tbl);
+		if (show_type == A_FALSE)
+			value = pre_l2_cnt_tbl.bf.rx_drop_pkt_cnt_0 | ((a_uint64_t)pre_l2_cnt_tbl.bf.rx_drop_pkt_cnt_1 << 24);
+		else
+			value = pre_l2_cnt_tbl.bf.rx_drop_byte_cnt_0 | ((a_uint64_t)pre_l2_cnt_tbl.bf.rx_drop_byte_cnt_1 << 24);
+		if (value > 0)
+		{
+			if (sign) {
+				printk(KERN_CONT "\n");
+				printk(KERN_CONT "%-35s", "");
+			}
+			sign = 0;
+			printk(KERN_CONT "%15llu(vsi=%04d)", value, i);
+			if (++tags % 3 == 0)
+				sign = 1;
+		}
+	}
+	printk(KERN_CONT "\n");
+}
+
+void adpt_hppe_debug_port_tx_drop_counter_get(a_bool_t show_type)
+{
+	union port_tx_drop_cnt_tbl_u port_tx_drop_cnt_tbl;
+	a_uint64_t value;
+	int i, tags, sign;
+
+	sign = tags = 0;
+	printk("%-35s", "PORT_TX_DROP_CNT_TBL TX_DROP:");
+	for (i = 0; i < PORT_TX_DROP_CNT_TBL_MAX_ENTRY; i++)
+	{
+		hppe_port_tx_drop_cnt_tbl_get(0, i, &port_tx_drop_cnt_tbl);
+		if (show_type == A_FALSE)
+			value = (a_uint64_t)port_tx_drop_cnt_tbl.bf.tx_drop_pkt_cnt;
+		else
+			value = port_tx_drop_cnt_tbl.bf.tx_drop_byte_cnt_0 | ((a_uint64_t)port_tx_drop_cnt_tbl.bf.tx_drop_byte_cnt_1 << 32);
+		if (value > 0)
+		{
+			if (sign) {
+				printk(KERN_CONT "\n");
+				printk(KERN_CONT "%-35s", "");
+			}
+			sign = 0;
+			printk(KERN_CONT "%15llu(port=%04d)", value, i);
+			if (++tags % 3 == 0)
+				sign = 1;
+		}
+	}
+	printk(KERN_CONT "\n");
+}
+
+void
+adpt_hppe_debug_eg_vsi_counter_get(a_bool_t show_type)
+{
+	union eg_vsi_counter_tbl_u eg_vsi_counter_tbl;
+	a_uint64_t value;
+	int i, tags, sign;
+
+	sign = tags = 0;
+	printk("%-35s", "EG_VSI_COUNTER_TBL TX:");
+	for (i = 0; i < EG_VSI_COUNTER_TBL_MAX_ENTRY; i++)
+	{
+		hppe_eg_vsi_counter_tbl_get(0, i, &eg_vsi_counter_tbl);
+		if (show_type == A_FALSE)
+			value = (a_uint64_t)eg_vsi_counter_tbl.bf.tx_packets;
+		else
+			value = eg_vsi_counter_tbl.bf.tx_bytes_0 | ((a_uint64_t)eg_vsi_counter_tbl.bf.tx_bytes_1 << 32);
+		if (value > 0)
+		{
+			if (sign) {
+				printk(KERN_CONT "\n");
+				printk(KERN_CONT "%-35s", "");
+			}
+			sign = 0;
+			printk(KERN_CONT "%15llu(vsi=%04d)", value, i);
+			if (++tags % 3 == 0)
+				sign = 1;
+		}
+	}
+	printk(KERN_CONT "\n");
+}
+
+void
+adpt_hppe_debug_port_tx_counter_get(a_bool_t show_type)
+{
+	union port_tx_counter_tbl_reg_u port_tx_counter_tbl;
+	a_uint64_t value;
+	int i, tags, sign;
+
+	sign = tags = 0;
+	printk("%-35s", "PORT_TX_COUNTER_TBL TX:");
+	for (i = 0; i < PORT_TX_COUNTER_TBL_REG_MAX_ENTRY; i++)
+	{
+		hppe_port_tx_counter_tbl_reg_get(0, i, &port_tx_counter_tbl);
+		if (show_type == A_FALSE)
+			value = (a_uint64_t)port_tx_counter_tbl.bf.tx_packets;
+		else
+			value = port_tx_counter_tbl.bf.tx_bytes_0 | ((a_uint64_t)port_tx_counter_tbl.bf.tx_bytes_1 << 32);
+		if (value > 0)
+		{
+			if (sign) {
+				printk(KERN_CONT "\n");
+				printk(KERN_CONT "%-35s", "");
+			}
+			sign = 0;
+			printk(KERN_CONT "%15llu(port=%04d)", value, i);
+			if (++tags % 3 == 0)
+				sign = 1;
+		}
+	}
+	printk(KERN_CONT "\n");
+}
+
+void
+adpt_hppe_debug_vp_tx_counter_get(a_bool_t show_type)
+{
+	union vp_tx_counter_tbl_reg_u vp_tx_counter_tbl;
+	a_uint64_t value;
+	int i, tags, sign;
+
+	sign = tags = 0;
+	printk("%-35s", "VP_TX_COUNTER_TBL TX:");
+	for (i = 0; i < VP_TX_COUNTER_TBL_REG_MAX_ENTRY; i++)
+	{
+		hppe_vp_tx_counter_tbl_reg_get(0, i, &vp_tx_counter_tbl);
+		if (show_type == A_FALSE)
+			value = (a_uint64_t)vp_tx_counter_tbl.bf.tx_packets;
+		else
+			value = vp_tx_counter_tbl.bf.tx_bytes_0 | ((a_uint64_t)vp_tx_counter_tbl.bf.tx_bytes_1 << 32);
+		if (value > 0)
+		{
+			if (sign) {
+				printk(KERN_CONT "\n");
+				printk(KERN_CONT "%-35s", "");
+			}
+			sign = 0;
+			printk(KERN_CONT "%15llu(port=%04d)", value, i);
+			if (++tags % 3 == 0)
+				sign = 1;
+		}
+	}
+	printk(KERN_CONT "\n");
+}
+
+void
+adpt_hppe_debug_queue_tx_counter_get(a_bool_t show_type)
+{
+	union queue_tx_counter_tbl_u queue_tx_counter_tbl;
+	a_uint64_t value;
+	int i, tags, sign;
+
+	sign = tags = 0;
+	printk("%-35s", "QUEUE_TX_COUNTER_TBL TX:");
+	for (i = 0; i < QUEUE_TX_COUNTER_TBL_MAX_ENTRY; i++)
+	{
+		hppe_queue_tx_counter_tbl_get(0, i, &queue_tx_counter_tbl);
+		if (show_type == A_FALSE)
+			value = (a_uint64_t)queue_tx_counter_tbl.bf.tx_packets;
+		else
+			value = queue_tx_counter_tbl.bf.tx_bytes_0 | ((a_uint64_t)queue_tx_counter_tbl.bf.tx_bytes_1 << 32);
+		if (value > 0)
+		{
+			if (sign) {
+				printk(KERN_CONT "\n");
+				printk(KERN_CONT "%-35s", "");
+			}
+			sign = 0;
+			printk(KERN_CONT "%15llu(queue=%04d)", value, i);
+			if (++tags % 3 == 0)
+				sign = 1;
+		}
+	}
+	printk(KERN_CONT "\n");
+}
+
+void
+adpt_hppe_debug_vp_tx_drop_counter_get(a_bool_t show_type)
+{
+	union vp_tx_drop_cnt_tbl_u vp_tx_drop_cnt_tbl;
+	a_uint64_t value;
+	int i, tags, sign;
+
+	sign = tags = 0;
+	printk("%-35s", "VP_TX_DROP_CNT_TBL TX_DROP:");
+	for (i = 0; i < VP_TX_DROP_CNT_TBL_MAX_ENTRY; i++)
+	{
+		hppe_vp_tx_drop_cnt_tbl_get(0, i, &vp_tx_drop_cnt_tbl);
+		if (show_type == A_FALSE)
+			value = (a_uint64_t)vp_tx_drop_cnt_tbl.bf.tx_drop_pkt_cnt;
+		else
+			value = vp_tx_drop_cnt_tbl.bf.tx_drop_byte_cnt_0 | ((a_uint64_t)vp_tx_drop_cnt_tbl.bf.tx_drop_byte_cnt_1 << 32);
+		if (value > 0)
+		{
+			if (sign) {
+				printk(KERN_CONT "\n");
+				printk(KERN_CONT "%-35s", "");
+			}
+			sign = 0;
+			printk(KERN_CONT "%15llu(port=%04d)", value, i);
+			if (++tags % 3 == 0)
+				sign = 1;
+		}
+	}
+	printk(KERN_CONT "\n");
+}
+
+void
+adpt_hppe_debug_cpu_code_counter_get(a_bool_t show_type)
+{
+	union drop_cpu_cnt_tbl_u drop_cpu_cnt_tbl;
+	a_uint64_t value;
+	int i, tags, sign;
+
+	sign = tags = 0;
+	printk("%-35s", "CPU_CODE_CNT_TBL:");
+	for (i = 0; i < CPU_CODE_CNT_TBL_MAX_ENTRY; i++)
+	{
+		hppe_drop_cpu_cnt_tbl_get(0, i, &drop_cpu_cnt_tbl);
+		if (show_type == A_FALSE)
+			value = (a_uint64_t)drop_cpu_cnt_tbl.bf.pkt_cnt;
+		else
+			value = drop_cpu_cnt_tbl.bf.byte_cnt_0 | ((a_uint64_t)drop_cpu_cnt_tbl.bf.byte_cnt_1 << 32);
+		if (value > 0)
+		{
+			printk(KERN_CONT "\n");
+			printk(KERN_CONT "%-35s", "");
+			if (i >=0 && i <= 70)
+				printk(KERN_CONT "%15llu(%s)", value, cpucode[i]);
+			else if (i >= 79 && i <= 92)
+				printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 8]);
+			else if (i >= 97 && i <= 102)
+				printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 12]);
+			else if (i >= 107 && i <= 110)
+				printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 16]);
+			else if (i >= 113 && i <= 127)
+				printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 18]);
+			else if (i >= 136 && i <= 143)
+				printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 26]);
+			else if (i >= 148 && i <= 174)
+				printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 30]);
+			else if (i >= 178 && i <= 180)
+				printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 33]);
+			else if (i >= 254 && i <= 255)
+				printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 106]);
+			else
+				printk(KERN_CONT "%15llu(Reserved)", value);
+		}
+	}
+	printk(KERN_CONT "\n");
+}
+
+void
+adpt_hppe_debug_drop_cpu_counter_get(a_bool_t show_type)
+{
+	union drop_cpu_cnt_tbl_u drop_cpu_cnt_tbl;
+	a_uint64_t value;
+	int i, tags, sign;
+
+	sign = tags = 0;
+	printk("%-35s", "DROP_CPU_CNT_TBL:");
+	for (i = CPU_CODE_CNT_TBL_MAX_ENTRY; i < DROP_CPU_CNT_TBL_MAX_ENTRY; i++)
+	{
+		hppe_drop_cpu_cnt_tbl_get(0, i, &drop_cpu_cnt_tbl);
+		if (show_type == A_FALSE)
+			value = (a_uint64_t)drop_cpu_cnt_tbl.bf.pkt_cnt;
+		else
+			value = drop_cpu_cnt_tbl.bf.byte_cnt_0 | ((a_uint64_t)drop_cpu_cnt_tbl.bf.byte_cnt_1 << 32);
+		if (value > 0)
+		{
+			printk(KERN_CONT "\n");
+			printk(KERN_CONT "%-35s", "");
+			printk(KERN_CONT "%15llu(port=%d:%s)", value, (i - 256) % 8, dropcode[(i - 256) / 8]);
+		}
+	}
+	printk(KERN_CONT "\n");
+}
+
+/* if show_type = A_FALSE, show packets.
+ * if show_type = A_TRUE, show bytes.
+ */
+sw_error_t
+adpt_hppe_debug_counter_get(a_bool_t show_type)
+{
+	/* show PRX DROP_CNT */
+	adpt_hppe_debug_prx_drop_cnt_get();
+
+	/* show PRX DROP_PKT_STAT */
+	adpt_hppe_debug_prx_drop_pkt_stat_get(show_type);
+
+	/* show IPR_PKT_NUM */
+	adpt_hppe_debug_ipx_pkt_num_get(show_type);
+
+	/* show VLAN_CNT_TBL */
+	adpt_hppe_debug_vlan_counter_get(show_type);
+
+	/* show PRE_L2_CNT_TBL */
+	adpt_hppe_debug_pre_l2_counter_get(show_type);
+
+	/* show PORT_TX_DROP_CNT_TBL */
+	adpt_hppe_debug_port_tx_drop_counter_get(show_type);
+
+	/* show EG_VSI_COUNTER_TBL */
+	adpt_hppe_debug_eg_vsi_counter_get(show_type);
+
+	/* show PORT_TX_COUNTER_TBL */
+	adpt_hppe_debug_port_tx_counter_get(show_type);
+
+	/* show VP_TX_COUNTER_TBL */
+	adpt_hppe_debug_vp_tx_counter_get(show_type);
+
+	/* show QUEUE_TX_COUNTER_TBL */
+	adpt_hppe_debug_queue_tx_counter_get(show_type);
+
+	/* show VP_TX_DROP_CNT_TBL */
+	adpt_hppe_debug_vp_tx_drop_counter_get(show_type);
+
+	/* show CPU_CODE_CNT */
+	adpt_hppe_debug_cpu_code_counter_get(show_type);
+
+	/* show DROP_CPU_CNT_TBL */
+	adpt_hppe_debug_drop_cpu_counter_get(show_type);
+
+	return SW_OK;
+}
+#endif
+sw_error_t adpt_hppe_misc_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL) {
+		return SW_FAIL;
+	}
+
+#ifndef IN_MISC_MINI
+	p_adpt_api->adpt_debug_port_counter_enable = adpt_ppe_debug_port_counter_enable;
+	p_adpt_api->adpt_debug_port_counter_status_get = adpt_ppe_debug_port_counter_status_get;
+
+	p_adpt_api->adpt_debug_counter_set = adpt_hppe_debug_counter_set;
+	p_adpt_api->adpt_debug_counter_get = adpt_hppe_debug_counter_get;
+#endif
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_policer.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_policer.c
new file mode 100755
index 0000000..cf6191a
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_policer.c
@@ -0,0 +1,1138 @@
+/*
+ * Copyright (c) 2016-2017, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_policer_reg.h"
+#include "hppe_policer.h"
+#include "adpt.h"
+
+#define NR_ADPT_HPPE_POLICER_METER_UNIT         2
+#define NR_ADPT_HPPE_POLICER_METER_TOKEN_UNIT         8
+#define ADPT_HPPE_POLICER_METER_UNIT_BYTE       0
+#define ADPT_HPPE_POLICER_METER_UNIT_FRAME      1
+#define ADPT_HPPE_FREQUENCY      300  /*MHZ*/
+#define ADPT_HPPE_POLICER_BURST_SIZE_UNIT      65536
+#define ADPT_HPPE_POLICER_REFRESH_BITS  18
+#define ADPT_HPPE_POLICER_BUCKET_SIZE_BITS  16
+#define ADPT_HPPE_POLICER_REFRESH_MAX  ((1 << ADPT_HPPE_POLICER_REFRESH_BITS) - 1)
+#define ADPT_HPPE_POLICER_BUCKET_SIZE_MAX  ((1 << ADPT_HPPE_POLICER_BUCKET_SIZE_BITS) - 1)
+#define BYTE_POLICER_MAX_RATE 10000000
+#define BYTE_POLICER_MIN_RATE 64
+#define FRAME_POLICER_MAX_RATE 14881000
+#define FRAME_POLICER_MIN_RATE 6
+
+
+static a_uint32_t hppe_policer_token_unit[NR_ADPT_HPPE_POLICER_METER_UNIT]
+	[NR_ADPT_HPPE_POLICER_METER_TOKEN_UNIT] = {{2048 * 8,
+	512 * 8,128 * 8,32 * 8,8 * 8,2 * 8, 4, 1},
+	{2097152,524288,131072,32768,8192,2048,512,128}};
+
+typedef struct
+{
+    a_uint64_t rate_1bit;
+    a_uint64_t rate_max;
+} adpt_hppe_policer_rate_t;
+
+typedef struct
+{
+    a_uint64_t burst_size_1bit;
+    a_uint64_t burst_size_max;
+} adpt_hppe_policer_burst_size_t;
+
+static adpt_hppe_policer_rate_t
+hppe_policer_rate[NR_ADPT_HPPE_POLICER_METER_UNIT][NR_ADPT_HPPE_POLICER_METER_TOKEN_UNIT] =
+{
+	/* byte based*/
+	{
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+	},
+
+	/*frame based */
+	{
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+	},
+};
+
+static adpt_hppe_policer_burst_size_t
+hppe_policer_burst_size[NR_ADPT_HPPE_POLICER_METER_UNIT][NR_ADPT_HPPE_POLICER_METER_TOKEN_UNIT] =
+{
+	{	{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+	},
+	{	{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+	},
+};
+
+#ifndef IN_POLICER_MINI
+sw_error_t
+adpt_hppe_acl_policer_counter_get(a_uint32_t dev_id, a_uint32_t index,
+		fal_policer_counter_t *counter)
+{
+	union in_acl_meter_cnt_tbl_u in_acl_meter_cnt_tbl;
+
+	memset(&in_acl_meter_cnt_tbl, 0, sizeof(in_acl_meter_cnt_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(counter);
+
+	if (index < 0 || index > 511)
+		return SW_BAD_PARAM;
+
+	hppe_in_acl_meter_cnt_tbl_get(dev_id, index * 3, &in_acl_meter_cnt_tbl);
+	counter->green_packet_counter = in_acl_meter_cnt_tbl.bf.pkt_cnt;
+	counter->green_byte_counter = in_acl_meter_cnt_tbl.bf.byte_cnt_1;
+	counter->green_byte_counter = (counter->green_byte_counter << 32) | in_acl_meter_cnt_tbl.bf.byte_cnt_0;
+
+	hppe_in_acl_meter_cnt_tbl_get(dev_id, index * 3 + 1, &in_acl_meter_cnt_tbl);
+	counter->yellow_packet_counter = in_acl_meter_cnt_tbl.bf.pkt_cnt;
+	counter->yellow_byte_counter = in_acl_meter_cnt_tbl.bf.byte_cnt_1;
+	counter->yellow_byte_counter = (counter->yellow_byte_counter << 32) | in_acl_meter_cnt_tbl.bf.byte_cnt_0;
+
+	hppe_in_acl_meter_cnt_tbl_get(dev_id, index * 3 + 2, &in_acl_meter_cnt_tbl);
+	counter->red_packet_counter = in_acl_meter_cnt_tbl.bf.pkt_cnt;
+	counter->red_byte_counter = in_acl_meter_cnt_tbl.bf.byte_cnt_1;
+	counter->red_byte_counter = (counter->red_byte_counter << 32) | in_acl_meter_cnt_tbl.bf.byte_cnt_0;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_policer_counter_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_policer_counter_t *counter)
+{
+	union in_port_meter_cnt_tbl_u in_port_meter_cnt_tbl;
+
+	memset(&in_port_meter_cnt_tbl, 0, sizeof(in_port_meter_cnt_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(counter);
+
+	if (port_id < 0 || port_id > 7)
+		return SW_BAD_PARAM;
+
+	hppe_in_port_meter_cnt_tbl_get(dev_id, port_id * 3, &in_port_meter_cnt_tbl);
+	counter->green_packet_counter = in_port_meter_cnt_tbl.bf.pkt_cnt;
+	counter->green_byte_counter = in_port_meter_cnt_tbl.bf.byte_cnt_1;
+	counter->green_byte_counter = (counter->green_byte_counter << 32) | in_port_meter_cnt_tbl.bf.byte_cnt_0;
+
+	hppe_in_port_meter_cnt_tbl_get(dev_id, port_id * 3 + 1, &in_port_meter_cnt_tbl);
+	counter->yellow_packet_counter = in_port_meter_cnt_tbl.bf.pkt_cnt;
+	counter->yellow_byte_counter = in_port_meter_cnt_tbl.bf.byte_cnt_1;
+	counter->yellow_byte_counter = (counter->yellow_byte_counter << 32) | in_port_meter_cnt_tbl.bf.byte_cnt_0;
+
+	hppe_in_port_meter_cnt_tbl_get(dev_id, port_id * 3 + 2, &in_port_meter_cnt_tbl);
+	counter->red_packet_counter = in_port_meter_cnt_tbl.bf.pkt_cnt;
+	counter->red_byte_counter = in_port_meter_cnt_tbl.bf.byte_cnt_1;
+	counter->red_byte_counter = (counter->red_byte_counter << 32) | in_port_meter_cnt_tbl.bf.byte_cnt_0;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_compensation_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t  *length)
+{
+	sw_error_t rv = SW_OK;
+	union meter_cmpst_length_reg_u meter_cmpst_length_reg;
+
+	memset(&meter_cmpst_length_reg, 0, sizeof(meter_cmpst_length_reg));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(length);
+
+	if (port_id < 0 || port_id > 7)
+		return SW_BAD_PARAM;
+
+	rv = hppe_meter_cmpst_length_reg_get(dev_id, port_id, &meter_cmpst_length_reg);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*length = meter_cmpst_length_reg.bf.cmpst_length;
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_hppe_policer_rate_to_refresh(a_uint32_t rate,
+							a_uint32_t *refresh,
+							a_bool_t meter_unit,
+							a_uint32_t  token_unit)
+{
+	a_uint32_t temp_refresh;
+	a_uint64_t temp_rate;
+
+	if(hppe_policer_rate[meter_unit][token_unit].rate_1bit > 0)
+	{
+		temp_rate = ((a_uint64_t)rate) * 1000;
+		do_div(temp_rate, hppe_policer_rate[meter_unit][token_unit].rate_1bit);
+		temp_refresh = temp_rate;
+	}
+	else
+	{
+		return SW_BAD_PARAM;;
+	}
+
+	if (temp_refresh > ADPT_HPPE_POLICER_REFRESH_MAX)
+	{
+		temp_refresh = ADPT_HPPE_POLICER_REFRESH_MAX;
+	}
+
+	*refresh = temp_refresh;
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_hppe_policer_burst_size_to_bucket_size(a_uint32_t burst_size,
+							a_uint32_t *bucket_size,
+							a_bool_t meter_unit,
+							a_uint32_t  token_unit)
+{
+	a_uint32_t temp_bucket_size;
+	a_uint64_t temp_burst_size;
+
+	if(hppe_policer_burst_size[meter_unit][token_unit].burst_size_1bit > 0)
+	{
+		temp_burst_size = ((a_uint64_t)burst_size) * 1000;
+		do_div(temp_burst_size, hppe_policer_burst_size[meter_unit][token_unit].burst_size_1bit);
+		temp_bucket_size = temp_burst_size;
+	}
+	else
+	{
+		return SW_BAD_PARAM;
+	}
+
+	if(temp_bucket_size > ADPT_HPPE_POLICER_BUCKET_SIZE_MAX)
+	{
+		temp_bucket_size = ADPT_HPPE_POLICER_BUCKET_SIZE_MAX;
+	}
+
+	*bucket_size = temp_bucket_size;
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_hppe_policer_refresh_to_rate(a_uint32_t refresh,
+							a_uint32_t *rate,
+							a_bool_t meter_unit,
+							a_uint32_t  token_unit)
+{
+	a_uint32_t temp_rate;
+	a_uint64_t temp_refresh;
+
+	if(hppe_policer_rate[meter_unit][token_unit].rate_1bit > 0)
+	{
+		temp_refresh = ((a_uint64_t)refresh) * hppe_policer_rate[meter_unit][token_unit].rate_1bit;
+		do_div(temp_refresh, 1000);
+		temp_rate = temp_refresh;
+	}
+	else
+	{
+		return SW_BAD_PARAM;;
+	}
+
+	*rate = temp_rate;
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_hppe_policer_bucket_size_to_burst_size(a_uint32_t bucket_size,
+							a_uint32_t *burst_size,
+							a_bool_t meter_unit,
+							a_uint32_t  token_unit)
+{
+	a_uint32_t temp_burst_size;
+	a_uint64_t temp_bucket_size;
+
+	if(hppe_policer_burst_size[meter_unit][token_unit].burst_size_1bit > 0)
+	{
+		temp_bucket_size = ((a_uint64_t)bucket_size) * hppe_policer_burst_size[meter_unit][token_unit].burst_size_1bit;
+		do_div(temp_bucket_size, 1000);
+		temp_burst_size = temp_bucket_size;
+	}
+	else
+	{
+		return SW_BAD_PARAM;
+	}
+
+	*burst_size = temp_burst_size;
+
+	return SW_OK;
+}
+#endif
+
+static sw_error_t
+__adpt_hppe_policer_max_rate(a_uint32_t time_slot)
+{
+	a_uint32_t i = 0, j = 0;
+	a_uint32_t time_cycle = 0;
+	a_uint64_t temp = 0, temp1 = 0, temp2 = 0;
+
+
+	/* time_cycle is ns*/
+	time_cycle = ( time_slot * 8)/ ADPT_HPPE_FREQUENCY;
+
+	for (j = 0; j < 8; j++)
+	{
+		/*max rate is bps*/
+		temp1 = (a_uint64_t)(ADPT_HPPE_POLICER_REFRESH_MAX  * 1000 * 8) * 1000;
+		temp2 =  hppe_policer_token_unit[i][j] * time_cycle;
+
+		do_div(temp1, temp2);
+		hppe_policer_rate[i][j].rate_max= temp1;
+
+		temp = temp1;
+		do_div(temp, ADPT_HPPE_POLICER_REFRESH_MAX);
+		hppe_policer_rate[i][j].rate_1bit = temp;
+
+	//	printk("hppe policer byte max_rate generating =%llu\n", hppe_policer_rate[i][j].rate_max);
+	//	printk("hppe policer byte based step =%llu\n", hppe_policer_rate[i][j].rate_1bit);
+	}
+
+	i = i + 1;
+	for (j = 0; j < 8; j++)
+	{
+		/* max rate unit  is 1/1000 pps*/
+		temp1 = (a_uint64_t)(ADPT_HPPE_POLICER_REFRESH_MAX * 1000) * 1000 * 1000;
+		temp2 = (a_uint64_t)hppe_policer_token_unit[i][j] * time_cycle;
+
+		do_div(temp1, temp2);
+		hppe_policer_rate[i][j].rate_max = temp1;
+
+		temp = temp1;
+		do_div(temp, ADPT_HPPE_POLICER_REFRESH_MAX);
+		hppe_policer_rate[i][j].rate_1bit = temp;
+
+	//	printk("policer frame hppe_max_rate generating =%llu\n", hppe_policer_rate[i][j].rate_max);
+	//	printk("policer frame step rate =%llu\n", hppe_policer_rate[i][j].rate_1bit);
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_hppe_policer_max_burst_size(void)
+{
+	a_uint32_t i = 0, j = 0;
+	a_uint64_t temp = 0, temp1 = 0;
+
+
+	for (j = 0; j < 8; j++)
+	{
+		/*max size unit is 1/1000 byte based*/
+		temp = ((a_uint64_t)(ADPT_HPPE_POLICER_BURST_SIZE_UNIT)) *
+			ADPT_HPPE_POLICER_BUCKET_SIZE_MAX;
+		do_div(temp, hppe_policer_token_unit[i][j]);
+		hppe_policer_burst_size[i][j].burst_size_max = (a_uint64_t)(temp * 1000);
+
+		temp1 = hppe_policer_burst_size[i][j].burst_size_max;
+		do_div(temp1, ADPT_HPPE_POLICER_BUCKET_SIZE_MAX);
+		hppe_policer_burst_size[i][j].burst_size_1bit = temp1;
+
+		/*
+		printk("policer byte hppe_max_burst_size generating =%llu\n",
+				hppe_policer_burst_size[i][j].burst_size_max);
+		printk("policer byte hppe_max_burst_size step  =%llu\n",
+				hppe_policer_burst_size[i][j].burst_size_1bit);
+		*/
+
+	}
+
+	i = i + 1;
+	for (j = 0; j < 8; j++)
+	{
+		/* max size unit is 1/1000 frame based */
+		temp = ((a_uint64_t)(ADPT_HPPE_POLICER_BURST_SIZE_UNIT)) *
+			ADPT_HPPE_POLICER_BUCKET_SIZE_MAX;
+		do_div(temp, hppe_policer_token_unit[i][j]);
+		hppe_policer_burst_size[i][j].burst_size_max = (a_uint64_t)(temp * 1000);
+
+		temp1 = hppe_policer_burst_size[i][j].burst_size_max;
+		do_div(temp1, ADPT_HPPE_POLICER_BUCKET_SIZE_MAX);
+		hppe_policer_burst_size[i][j].burst_size_1bit = temp1;
+
+		/*
+		printk("policer frame hppe_max_burst_size generating =%llu\n",
+				hppe_policer_burst_size[i][j].burst_size_max);
+		printk("policer frame hppe_max_burst_size step  =%llu\n",
+				hppe_policer_burst_size[i][j].burst_size_1bit);
+		*/
+
+	}
+
+	return SW_OK;
+}
+
+#ifndef IN_POLICER_MINI
+static sw_error_t
+__adpt_hppe_policer_two_bucket_parameter_select(a_uint64_t c_rate,
+						a_uint64_t c_burst_size,
+						a_uint64_t e_rate,
+						a_uint64_t e_burst_size,
+						a_uint32_t meter_unit,
+						a_uint32_t *token_unit)
+{
+	a_uint32_t  temp_token_unit;
+	a_uint32_t match = A_FALSE;
+	a_uint64_t temp_rate = 0, temp_burst_size = 0;
+
+	if(c_rate > e_rate)
+		temp_rate = c_rate;
+	else
+		temp_rate = e_rate;
+
+	if(c_burst_size > e_burst_size)
+		temp_burst_size = c_burst_size;
+	else
+		temp_burst_size = e_burst_size;
+
+	for (temp_token_unit = 0; temp_token_unit < 8; temp_token_unit++)
+	{
+		 if (temp_rate > hppe_policer_rate[meter_unit][temp_token_unit].rate_max)
+		 {
+		 	continue;
+		 }
+		 else if(temp_burst_size <= hppe_policer_burst_size[meter_unit][temp_token_unit].burst_size_max)
+		{
+			*token_unit = temp_token_unit;
+			match = A_TRUE;
+			break;
+		}
+	}
+
+	if (match == A_FALSE)
+	{
+		printk("Not match C and E token bucket parameter rate configuration \n");
+		return SW_BAD_PARAM;
+	}
+
+	return SW_OK;
+}
+
+#if 0
+static sw_error_t
+__adpt_hppe_policer_one_bucket_parameter_select(a_uint64_t c_rate,
+						a_uint64_t c_burst_size,
+						a_uint32_t meter_unit,
+						a_uint32_t *token_unit)
+{
+	a_uint32_t  temp_token_unit;
+	a_uint32_t match = A_FALSE;
+
+	for (temp_token_unit = 0; temp_token_unit < 8; temp_token_unit++)
+	{
+		if (c_rate > hppe_policer_rate[meter_unit][temp_token_unit].rate_max)
+		{
+			continue;
+		}
+		else if (c_burst_size <= hppe_policer_burst_size[meter_unit][temp_token_unit].burst_size_max)
+		{
+			*token_unit = temp_token_unit;
+			match = A_TRUE;
+			break;
+		}
+	}
+
+	if (match == A_FALSE)
+	{
+		printk("Not match policer C token bucket parameter rate configuration \n");
+		return SW_BAD_PARAM;
+	}
+
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+adpt_hppe_port_policer_entry_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_policer_config_t *policer, fal_policer_action_t *action)
+{
+	union in_port_meter_cfg_tbl_u in_port_meter_cfg_tbl;
+	a_uint32_t hppe_cir =0, hppe_cbs = 0, hppe_eir = 0,hppe_ebs = 0;
+
+	memset(&in_port_meter_cfg_tbl, 0, sizeof(in_port_meter_cfg_tbl));
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(policer);
+	ADPT_NULL_POINT_CHECK(action);
+
+	if (port_id < 0 || port_id > 7)
+		return SW_BAD_PARAM;
+
+	hppe_in_port_meter_cfg_tbl_get(dev_id, port_id, &in_port_meter_cfg_tbl);
+
+	hppe_cir = (in_port_meter_cfg_tbl.bf.cir_1 << 3) | in_port_meter_cfg_tbl.bf.cir_0;
+	hppe_cbs = in_port_meter_cfg_tbl.bf.cbs;
+	hppe_eir = (in_port_meter_cfg_tbl.bf.eir_1 << 1) | in_port_meter_cfg_tbl.bf.eir_0;
+	hppe_ebs = in_port_meter_cfg_tbl.bf.ebs;
+
+
+	__adpt_hppe_policer_refresh_to_rate(hppe_cir,
+								&policer->cir,
+								in_port_meter_cfg_tbl.bf.meter_unit,
+								in_port_meter_cfg_tbl.bf.token_unit);
+
+	__adpt_hppe_policer_refresh_to_rate(hppe_eir,
+								&policer->eir,
+								in_port_meter_cfg_tbl.bf.meter_unit,
+								in_port_meter_cfg_tbl.bf.token_unit);
+
+	__adpt_hppe_policer_bucket_size_to_burst_size(hppe_cbs,
+								&policer->cbs,
+								in_port_meter_cfg_tbl.bf.meter_unit,
+								in_port_meter_cfg_tbl.bf.token_unit);
+
+	__adpt_hppe_policer_bucket_size_to_burst_size(hppe_ebs,
+								&policer->ebs,
+								in_port_meter_cfg_tbl.bf.meter_unit,
+								in_port_meter_cfg_tbl.bf.token_unit);
+
+	policer->meter_en = in_port_meter_cfg_tbl.bf.meter_en;
+	policer->color_mode = in_port_meter_cfg_tbl.bf.color_mode;
+	policer->frame_type = in_port_meter_cfg_tbl.bf.meter_flag;
+	policer->couple_en = in_port_meter_cfg_tbl.bf.coupling_flag;
+	policer->meter_mode = in_port_meter_cfg_tbl.bf.meter_mode;
+	policer->meter_unit = in_port_meter_cfg_tbl.bf.meter_unit;
+	action->yellow_priority_en = in_port_meter_cfg_tbl.bf.exceed_chg_pri_cmd;
+	action->yellow_drop_priority_en = in_port_meter_cfg_tbl.bf.exceed_chg_dp_cmd;
+	action->yellow_pcp_en = in_port_meter_cfg_tbl.bf.exceed_chg_pcp_cmd;
+	action->yellow_dei_en = in_port_meter_cfg_tbl.bf.exceed_chg_dei_cmd;
+	action->yellow_priority = in_port_meter_cfg_tbl.bf.exceed_pri;
+	action->yellow_drop_priority = in_port_meter_cfg_tbl.bf.exceed_dp;
+	action->yellow_pcp = in_port_meter_cfg_tbl.bf.exceed_pcp;
+	action->yellow_dei = in_port_meter_cfg_tbl.bf.exceed_dei;
+	if (in_port_meter_cfg_tbl.bf.violate_cmd == 0)
+		action->red_action = FAL_MAC_DROP;
+	else
+		action->red_action = FAL_MAC_FRWRD;
+	action->red_priority_en = in_port_meter_cfg_tbl.bf.violate_chg_pri_cmd;
+	action->red_drop_priority_en = in_port_meter_cfg_tbl.bf.violate_chg_dp_cmd;
+	action->red_pcp_en = in_port_meter_cfg_tbl.bf.violate_chg_pcp_cmd;
+	action->red_dei_en = in_port_meter_cfg_tbl.bf.violate_chg_dei_cmd;
+	action->red_priority = in_port_meter_cfg_tbl.bf.violate_pri;
+	action->red_drop_priority = in_port_meter_cfg_tbl.bf.violate_dp;
+	action->red_pcp = in_port_meter_cfg_tbl.bf.violate_pcp;
+	action->red_dei = in_port_meter_cfg_tbl.bf.violate_dei;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_policer_entry_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_policer_config_t *policer, fal_policer_action_t *action)
+{
+	union in_port_meter_cfg_tbl_u in_port_meter_cfg_tbl;
+	a_uint32_t hppe_cir = 0, hppe_cbs = 0, hppe_eir = 0,hppe_ebs = 0;
+	a_uint64_t temp_cir = 0, temp_eir =0, temp_cbs =0, temp_ebs = 0;
+	a_uint32_t token_unit = 0;
+	sw_error_t rv = SW_OK;
+
+	memset(&in_port_meter_cfg_tbl, 0, sizeof(in_port_meter_cfg_tbl));
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(policer);
+	ADPT_NULL_POINT_CHECK(action);
+
+	if (port_id < 0 || port_id > 7)
+		return SW_BAD_PARAM;
+
+	if(ADPT_HPPE_POLICER_METER_UNIT_BYTE == policer->meter_unit)
+	{
+		if ((policer->cir > BYTE_POLICER_MAX_RATE) || (policer->eir > BYTE_POLICER_MAX_RATE))
+			return SW_BAD_PARAM;
+		if ((policer->cir < BYTE_POLICER_MIN_RATE) && (policer->cir != 0))
+			return SW_BAD_PARAM;
+		if ((policer->eir < BYTE_POLICER_MIN_RATE) && (policer->eir != 0))
+			return SW_BAD_PARAM;
+	}
+
+	if(ADPT_HPPE_POLICER_METER_UNIT_FRAME == policer->meter_unit)
+	{
+		if ((policer->cir > FRAME_POLICER_MAX_RATE) || (policer->eir > FRAME_POLICER_MAX_RATE))
+			return SW_BAD_PARAM;
+		if ((policer->cir < FRAME_POLICER_MIN_RATE) && (policer->cir != 0))
+			return SW_BAD_PARAM;
+		if ((policer->eir < FRAME_POLICER_MIN_RATE) && (policer->eir != 0))
+			return SW_BAD_PARAM;
+	}
+
+	if((0 == policer->meter_mode) && (policer->cir > policer->eir))
+		return SW_BAD_PARAM;
+
+	temp_cir = ((a_uint64_t)policer->cir) * 1000;
+	temp_cbs = ((a_uint64_t)policer->cbs) * 1000;
+	temp_eir = ((a_uint64_t)policer->eir) * 1000;
+	temp_ebs = ((a_uint64_t)policer->ebs) * 1000;
+
+	rv = __adpt_hppe_policer_two_bucket_parameter_select(temp_cir,
+								temp_cbs,
+								temp_eir,
+								temp_ebs,
+								policer->meter_unit,
+								&token_unit);
+	if( rv != SW_OK )
+		return rv;
+
+//	printk("current meter unit is = %d\n", policer->meter_unit);
+//	printk("current token unit is = %d\n", token_unit);
+
+	__adpt_hppe_policer_rate_to_refresh(policer->cir,
+								&hppe_cir,
+								policer->meter_unit,
+								token_unit);
+
+	__adpt_hppe_policer_rate_to_refresh(policer->eir,
+								&hppe_eir,
+								policer->meter_unit,
+								token_unit);
+
+	__adpt_hppe_policer_burst_size_to_bucket_size(policer->cbs,
+								&hppe_cbs,
+								policer->meter_unit,
+								token_unit);
+
+	__adpt_hppe_policer_burst_size_to_bucket_size(policer->ebs,
+								&hppe_ebs,
+								policer->meter_unit,
+								token_unit);
+
+	in_port_meter_cfg_tbl.bf.meter_en = policer->meter_en;
+	in_port_meter_cfg_tbl.bf.color_mode = policer->color_mode;
+	in_port_meter_cfg_tbl.bf.meter_flag = policer->frame_type;
+	in_port_meter_cfg_tbl.bf.coupling_flag = policer->couple_en;
+	in_port_meter_cfg_tbl.bf.meter_mode = policer->meter_mode;
+	in_port_meter_cfg_tbl.bf.token_unit = token_unit;
+	in_port_meter_cfg_tbl.bf.meter_unit = (a_uint32_t)policer->meter_unit;
+	in_port_meter_cfg_tbl.bf.cbs = hppe_cbs;
+	in_port_meter_cfg_tbl.bf.cir_0 = hppe_cir & 0x7;
+	in_port_meter_cfg_tbl.bf.cir_1 = hppe_cir >> 3;
+	in_port_meter_cfg_tbl.bf.ebs = hppe_ebs;
+	in_port_meter_cfg_tbl.bf.eir_0 = hppe_eir & 0x1;
+	in_port_meter_cfg_tbl.bf.eir_1 = hppe_eir >> 1;
+	in_port_meter_cfg_tbl.bf.exceed_chg_pri_cmd = action->yellow_priority_en;
+	in_port_meter_cfg_tbl.bf.exceed_chg_dp_cmd = action->yellow_drop_priority_en;
+	in_port_meter_cfg_tbl.bf.exceed_chg_pcp_cmd = action->yellow_pcp_en;
+	in_port_meter_cfg_tbl.bf.exceed_chg_dei_cmd = action->yellow_dei_en;
+	in_port_meter_cfg_tbl.bf.exceed_pri = action->yellow_priority;
+	in_port_meter_cfg_tbl.bf.exceed_dp = action->yellow_drop_priority;
+	in_port_meter_cfg_tbl.bf.exceed_pcp = action->yellow_pcp;
+	in_port_meter_cfg_tbl.bf.exceed_dei = action->yellow_dei;
+	if (action->red_action == FAL_MAC_DROP)
+		in_port_meter_cfg_tbl.bf.violate_cmd = 0;
+	else
+		in_port_meter_cfg_tbl.bf.violate_cmd = 1;
+	in_port_meter_cfg_tbl.bf.violate_chg_pri_cmd = action->red_priority_en;
+	in_port_meter_cfg_tbl.bf.violate_chg_dp_cmd = action->red_drop_priority_en;
+	in_port_meter_cfg_tbl.bf.violate_chg_pcp_cmd = action->red_pcp_en;
+	in_port_meter_cfg_tbl.bf.violate_chg_dei_cmd = action->red_dei_en;
+	in_port_meter_cfg_tbl.bf.violate_pri = action->red_priority;
+	in_port_meter_cfg_tbl.bf.violate_dp = action->red_drop_priority;
+	in_port_meter_cfg_tbl.bf.violate_pcp = action->red_pcp;
+	in_port_meter_cfg_tbl.bf.violate_dei = action->red_dei;
+
+	hppe_in_port_meter_cfg_tbl_set(dev_id, port_id, &in_port_meter_cfg_tbl);
+
+	return SW_OK;
+
+}
+sw_error_t
+adpt_hppe_acl_policer_entry_get(a_uint32_t dev_id, a_uint32_t index,
+		fal_policer_config_t *policer, fal_policer_action_t *action)
+{
+	union in_acl_meter_cfg_tbl_u in_acl_meter_cfg_tbl;
+	a_uint32_t hppe_cir =0, hppe_cbs = 0, hppe_eir = 0,hppe_ebs = 0;
+
+	memset(&in_acl_meter_cfg_tbl, 0, sizeof(in_acl_meter_cfg_tbl));
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(policer);
+	ADPT_NULL_POINT_CHECK(action);
+
+	if (index < 0 || index > 511)
+		return SW_BAD_PARAM;
+
+	hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &in_acl_meter_cfg_tbl);
+
+	hppe_cir = (in_acl_meter_cfg_tbl.bf.cir_1 << 8) | in_acl_meter_cfg_tbl.bf.cir_0;
+	hppe_cbs = in_acl_meter_cfg_tbl.bf.cbs;
+	hppe_eir = (in_acl_meter_cfg_tbl.bf.eir_1 << 6) | in_acl_meter_cfg_tbl.bf.eir_0;
+	hppe_ebs = in_acl_meter_cfg_tbl.bf.ebs;
+
+	__adpt_hppe_policer_refresh_to_rate(hppe_cir,
+								&policer->cir,
+								in_acl_meter_cfg_tbl.bf.meter_unit,
+								in_acl_meter_cfg_tbl.bf.token_unit);
+
+	__adpt_hppe_policer_refresh_to_rate(hppe_eir,
+								&policer->eir,
+								in_acl_meter_cfg_tbl.bf.meter_unit,
+								in_acl_meter_cfg_tbl.bf.token_unit);
+
+	__adpt_hppe_policer_bucket_size_to_burst_size(hppe_cbs,
+								&policer->cbs,
+								in_acl_meter_cfg_tbl.bf.meter_unit,
+								in_acl_meter_cfg_tbl.bf.token_unit);
+
+	__adpt_hppe_policer_bucket_size_to_burst_size(hppe_ebs,
+								&policer->ebs,
+								in_acl_meter_cfg_tbl.bf.meter_unit,
+								in_acl_meter_cfg_tbl.bf.token_unit);
+
+	policer->meter_en = in_acl_meter_cfg_tbl.bf.meter_en;
+	policer->color_mode = in_acl_meter_cfg_tbl.bf.color_mode;
+	policer->couple_en= in_acl_meter_cfg_tbl.bf.coupling_flag;
+	policer->meter_mode = in_acl_meter_cfg_tbl.bf.meter_mode;
+	policer->meter_unit = in_acl_meter_cfg_tbl.bf.meter_unit;
+	action->yellow_priority_en = in_acl_meter_cfg_tbl.bf.exceed_chg_pri_cmd;
+	action->yellow_drop_priority_en = in_acl_meter_cfg_tbl.bf.exceed_chg_dp_cmd;
+	action->yellow_pcp_en = in_acl_meter_cfg_tbl.bf.exceed_chg_pcp_cmd;
+	action->yellow_dei_en = in_acl_meter_cfg_tbl.bf.exceed_chg_dei_cmd;
+	action->yellow_priority = in_acl_meter_cfg_tbl.bf.exceed_pri;
+	action->yellow_drop_priority = in_acl_meter_cfg_tbl.bf.exceed_dp;
+	action->yellow_pcp = in_acl_meter_cfg_tbl.bf.exceed_pcp;
+	action->yellow_dei = in_acl_meter_cfg_tbl.bf.exceed_dei;
+	if (in_acl_meter_cfg_tbl.bf.violate_cmd == 0)
+		action->red_action = FAL_MAC_DROP;
+	else
+		action->red_action = FAL_MAC_FRWRD;
+	action->red_priority_en = in_acl_meter_cfg_tbl.bf.violate_chg_pri_cmd;
+	action->red_drop_priority_en = in_acl_meter_cfg_tbl.bf.violate_chg_dp_cmd;
+	action->red_pcp_en = in_acl_meter_cfg_tbl.bf.violate_chg_pcp_cmd;
+	action->red_dei_en = in_acl_meter_cfg_tbl.bf.violate_chg_dei_cmd;
+	action->red_priority = (in_acl_meter_cfg_tbl.bf.violate_pri_1 << 1) |in_acl_meter_cfg_tbl.bf.violate_pri_0;
+	action->red_drop_priority = in_acl_meter_cfg_tbl.bf.violate_dp;
+	action->red_pcp = in_acl_meter_cfg_tbl.bf.violate_pcp;
+	action->red_dei = in_acl_meter_cfg_tbl.bf.violate_dei;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_acl_policer_entry_set(a_uint32_t dev_id, a_uint32_t index,
+		fal_policer_config_t *policer, fal_policer_action_t *action)
+{
+	union in_acl_meter_cfg_tbl_u in_acl_meter_cfg_tbl;
+	a_uint32_t hppe_cir =0, hppe_cbs = 0, hppe_eir = 0,hppe_ebs = 0;
+	a_uint64_t temp_cir = 0, temp_eir =0, temp_cbs =0, temp_ebs = 0;
+	a_uint32_t token_unit = 0;
+	sw_error_t rv = SW_OK;
+
+	memset(&in_acl_meter_cfg_tbl, 0, sizeof(in_acl_meter_cfg_tbl));
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(policer);
+	ADPT_NULL_POINT_CHECK(action);
+
+	if (index < 0 || index > 511)
+		return SW_BAD_PARAM;
+
+	if(ADPT_HPPE_POLICER_METER_UNIT_BYTE == policer->meter_unit)
+	{
+		if ((policer->cir > BYTE_POLICER_MAX_RATE) || (policer->eir > BYTE_POLICER_MAX_RATE))
+			return SW_BAD_PARAM;
+		if ((policer->cir < BYTE_POLICER_MIN_RATE) && (policer->cir != 0))
+			return SW_BAD_PARAM;
+		if ((policer->eir < BYTE_POLICER_MIN_RATE) && (policer->eir != 0))
+			return SW_BAD_PARAM;
+	}
+
+	if(ADPT_HPPE_POLICER_METER_UNIT_FRAME == policer->meter_unit)
+	{
+		if ((policer->cir > FRAME_POLICER_MAX_RATE) || (policer->eir > FRAME_POLICER_MAX_RATE))
+			return SW_BAD_PARAM;
+		if ((policer->cir < FRAME_POLICER_MIN_RATE) && (policer->cir != 0))
+			return SW_BAD_PARAM;
+		if ((policer->eir < FRAME_POLICER_MIN_RATE) && (policer->eir != 0))
+			return SW_BAD_PARAM;
+	}
+
+	if((0 == policer->meter_mode) && (policer->cir > policer->eir))
+		return SW_BAD_PARAM;
+
+	temp_cir = ((a_uint64_t)policer->cir) * 1000;
+	temp_cbs = ((a_uint64_t)policer->cbs) * 1000;
+	temp_eir = ((a_uint64_t)policer->eir) * 1000;
+	temp_ebs = ((a_uint64_t)policer->ebs) * 1000;
+
+	rv = __adpt_hppe_policer_two_bucket_parameter_select(temp_cir,
+								temp_cbs,
+								temp_eir,
+								temp_ebs,
+								policer->meter_unit,
+								&token_unit);
+	if( rv != SW_OK )
+		return rv;
+
+//	printk("current meter unit is = %d\n", policer->meter_unit);
+//	printk("current token unit is = %d\n", token_unit);
+
+	__adpt_hppe_policer_rate_to_refresh(policer->cir,
+								&hppe_cir,
+								policer->meter_unit,
+								token_unit);
+
+	__adpt_hppe_policer_rate_to_refresh(policer->eir,
+								&hppe_eir,
+								policer->meter_unit,
+								token_unit);
+
+	__adpt_hppe_policer_burst_size_to_bucket_size(policer->cbs,
+								&hppe_cbs,
+								policer->meter_unit,
+								token_unit);
+
+	__adpt_hppe_policer_burst_size_to_bucket_size(policer->ebs,
+								&hppe_ebs,
+								policer->meter_unit,
+								token_unit);
+
+	in_acl_meter_cfg_tbl.bf.meter_en = policer->meter_en;
+	in_acl_meter_cfg_tbl.bf.color_mode = policer->color_mode;
+	in_acl_meter_cfg_tbl.bf.coupling_flag = policer->couple_en;
+	in_acl_meter_cfg_tbl.bf.meter_mode = policer->meter_mode;
+	in_acl_meter_cfg_tbl.bf.token_unit = token_unit;
+	in_acl_meter_cfg_tbl.bf.meter_unit = policer->meter_unit;
+	in_acl_meter_cfg_tbl.bf.cbs = hppe_cbs;
+	in_acl_meter_cfg_tbl.bf.cir_0 = hppe_cir & 0xff;
+	in_acl_meter_cfg_tbl.bf.cir_1 = hppe_cir >> 8;
+	in_acl_meter_cfg_tbl.bf.ebs = hppe_ebs;
+	in_acl_meter_cfg_tbl.bf.eir_0 = hppe_eir & 0x3f;
+	in_acl_meter_cfg_tbl.bf.eir_1 = hppe_eir >> 6;
+	in_acl_meter_cfg_tbl.bf.exceed_chg_pri_cmd = action->yellow_priority_en;
+	in_acl_meter_cfg_tbl.bf.exceed_chg_dp_cmd = action->yellow_drop_priority_en;
+	in_acl_meter_cfg_tbl.bf.exceed_chg_pcp_cmd = action->yellow_pcp_en;
+	in_acl_meter_cfg_tbl.bf.exceed_chg_dei_cmd = action->yellow_dei_en;
+	in_acl_meter_cfg_tbl.bf.exceed_pri = action->yellow_priority;
+	in_acl_meter_cfg_tbl.bf.exceed_dp = action->yellow_drop_priority;
+	in_acl_meter_cfg_tbl.bf.exceed_pcp = action->yellow_pcp;
+	in_acl_meter_cfg_tbl.bf.exceed_dei = action->yellow_dei;
+	if (action->red_action == FAL_MAC_DROP)
+		in_acl_meter_cfg_tbl.bf.violate_cmd = 0;
+	else
+		in_acl_meter_cfg_tbl.bf.violate_cmd = 1;
+	in_acl_meter_cfg_tbl.bf.violate_chg_pri_cmd = action->red_priority_en;
+	in_acl_meter_cfg_tbl.bf.violate_chg_dp_cmd = action->red_drop_priority_en;
+	in_acl_meter_cfg_tbl.bf.violate_chg_pcp_cmd = action->red_pcp_en;
+	in_acl_meter_cfg_tbl.bf.violate_chg_dei_cmd = action->red_dei_en;
+	in_acl_meter_cfg_tbl.bf.violate_pri_0 = action->red_priority & 0x1;
+	in_acl_meter_cfg_tbl.bf.violate_pri_1 = action->red_priority >>1;
+	in_acl_meter_cfg_tbl.bf.violate_dp = action->red_drop_priority;
+	in_acl_meter_cfg_tbl.bf.violate_pcp = action->red_pcp;
+	in_acl_meter_cfg_tbl.bf.violate_dei = action->red_dei;
+
+	hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &in_acl_meter_cfg_tbl);
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_policer_time_slot_get(a_uint32_t dev_id, a_uint32_t *time_slot)
+{
+	sw_error_t rv = SW_OK;
+	union time_slot_reg_u time_slot_reg;
+
+	memset(&time_slot_reg, 0, sizeof(time_slot_reg));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time_slot);
+
+
+	rv = hppe_time_slot_reg_get(dev_id, &time_slot_reg);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*time_slot = time_slot_reg.bf.time_slot;
+
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+adpt_hppe_port_compensation_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t  length)
+{
+	union meter_cmpst_length_reg_u meter_cmpst_length_reg;
+
+	memset(&meter_cmpst_length_reg, 0, sizeof(meter_cmpst_length_reg));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (port_id < 0 || port_id > 7)
+		return SW_BAD_PARAM;
+
+	if (length > 0x1f)
+		return SW_BAD_PARAM;
+
+	hppe_meter_cmpst_length_reg_get(dev_id, port_id, &meter_cmpst_length_reg);
+	meter_cmpst_length_reg.bf.cmpst_length = length;
+
+	hppe_meter_cmpst_length_reg_set(dev_id, port_id, &meter_cmpst_length_reg);
+
+	return SW_OK;
+}
+sw_error_t
+adpt_hppe_policer_time_slot_set(a_uint32_t dev_id, a_uint32_t time_slot)
+{
+	union time_slot_reg_u time_slot_reg;
+
+	memset(&time_slot_reg, 0, sizeof(time_slot_reg));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if ((time_slot > 1024) || (time_slot < 512))
+		return SW_BAD_PARAM;
+
+	time_slot_reg.bf.time_slot = time_slot;
+	hppe_time_slot_reg_set(dev_id, &time_slot_reg);
+
+	__adpt_hppe_policer_max_rate(time_slot);
+
+	__adpt_hppe_policer_max_burst_size();
+
+	return SW_OK;
+}
+#ifndef IN_POLICER_MINI
+sw_error_t
+adpt_hppe_policer_global_counter_get(a_uint32_t dev_id,
+		fal_policer_global_counter_t *counter)
+{
+	union pc_global_cnt_tbl_u pc_global_cnt_tbl;
+	a_uint32_t index = 0;
+
+	memset(&pc_global_cnt_tbl, 0, sizeof(pc_global_cnt_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(counter);
+
+	hppe_pc_global_cnt_tbl_get(dev_id, index, &pc_global_cnt_tbl);
+	counter->policer_drop_packet_counter = pc_global_cnt_tbl.bf.pkt_cnt;
+	counter->policer_drop_byte_counter = pc_global_cnt_tbl.bf.byte_cnt_1;
+	counter->policer_drop_byte_counter = (counter->policer_drop_byte_counter << 32) |
+		pc_global_cnt_tbl.bf.byte_cnt_0;
+
+	hppe_pc_global_cnt_tbl_get(dev_id, index + 1, &pc_global_cnt_tbl);
+	counter->policer_forward_packet_counter = pc_global_cnt_tbl.bf.pkt_cnt;
+	counter->policer_forward_byte_counter = pc_global_cnt_tbl.bf.byte_cnt_1;
+	counter->policer_forward_byte_counter = (counter->policer_forward_byte_counter << 32) |
+		pc_global_cnt_tbl.bf.byte_cnt_0;
+
+	hppe_pc_global_cnt_tbl_get(dev_id, index + 2, &pc_global_cnt_tbl);
+	counter->policer_bypass_packet_counter = pc_global_cnt_tbl.bf.pkt_cnt;
+	counter->policer_bypass_byte_counter = pc_global_cnt_tbl.bf.byte_cnt_1;
+	counter->policer_bypass_byte_counter = (counter->policer_bypass_byte_counter << 32) |
+		pc_global_cnt_tbl.bf.byte_cnt_0;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_policer_bypass_en_get(a_uint32_t dev_id, fal_policer_frame_type_t frame_type,
+	a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	union pc_drop_bypass_reg_u drop_bypass_reg;
+
+	memset(&drop_bypass_reg, 0, sizeof(drop_bypass_reg));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	rv = hppe_pc_drop_bypass_reg_get(dev_id, &drop_bypass_reg);
+	SW_RTN_ON_ERROR (rv);
+
+	if (frame_type == FAL_FRAME_DROPPED) {
+		*enable = drop_bypass_reg.bf.drop_bypass_en;
+	} else {
+		return SW_BAD_PARAM;
+	}
+
+	return SW_OK;
+}
+
+#endif
+
+sw_error_t
+adpt_hppe_policer_bypass_en_set(a_uint32_t dev_id, fal_policer_frame_type_t frame_type,
+	a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union pc_drop_bypass_reg_u drop_bypass_reg;
+
+	memset(&drop_bypass_reg, 0, sizeof(drop_bypass_reg));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (frame_type == FAL_FRAME_DROPPED) {
+		drop_bypass_reg.bf.drop_bypass_en = enable;
+	} else {
+		return SW_BAD_PARAM;
+	}
+
+	rv = hppe_pc_drop_bypass_reg_set(dev_id, &drop_bypass_reg);
+	SW_RTN_ON_ERROR (rv);
+
+	return SW_OK;
+}
+
+void adpt_hppe_policer_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_policer_func_bitmap = ((1 << FUNC_ADPT_ACL_POLICER_COUNTER_GET)|
+						(1 << FUNC_ADPT_PORT_POLICER_COUNTER_GET)|
+						(1 << FUNC_ADPT_PORT_COMPENSATION_BYTE_GET)|
+						(1 << FUNC_ADPT_PORT_POLICER_ENTRY_GET)|
+						(1 << FUNC_ADPT_PORT_POLICER_ENTRY_SET)|
+						(1 << FUNC_ADPT_ACL_POLICER_ENTRY_GET)|
+						(1 << FUNC_ADPT_ACL_POLICER_ENTRY_SET)|
+						(1 << FUNC_ADPT_POLICER_TIME_SLOT_GET)|
+						(1 << FUNC_ADPT_PORT_COMPENSATION_BYTE_SET)|
+						(1 << FUNC_ADPT_POLICER_TIME_SLOT_SET) |
+						(1 << FUNC_ADPT_POLICER_GLOBAL_COUNTER_GET)|
+						(1 << FUNC_ADPT_POLICER_BYPASS_EN_SET)|
+						(1 << FUNC_ADPT_POLICER_BYPASS_EN_GET));
+
+	return;
+
+}
+
+static void adpt_hppe_policer_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_acl_policer_counter_get = NULL;
+	p_adpt_api->adpt_port_policer_counter_get = NULL;
+	p_adpt_api->adpt_port_compensation_byte_get = NULL;
+	p_adpt_api->adpt_port_policer_entry_get = NULL;
+	p_adpt_api->adpt_port_policer_entry_set = NULL;
+	p_adpt_api->adpt_acl_policer_entry_get = NULL;
+	p_adpt_api->adpt_acl_policer_entry_set = NULL;
+	p_adpt_api->adpt_policer_time_slot_get = NULL;
+	p_adpt_api->adpt_port_compensation_byte_set = NULL;
+	p_adpt_api->adpt_policer_time_slot_set = NULL;
+	p_adpt_api->adpt_policer_global_counter_get = NULL;
+	p_adpt_api->adpt_policer_bypass_en_set = NULL;
+	p_adpt_api->adpt_policer_bypass_en_get = NULL;
+
+	return;
+
+}
+
+
+sw_error_t adpt_hppe_policer_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_policer_func_unregister(dev_id, p_adpt_api);
+
+#ifndef IN_POLICER_MINI
+	if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_ACL_POLICER_COUNTER_GET))
+	{
+		p_adpt_api->adpt_acl_policer_counter_get = adpt_hppe_acl_policer_counter_get;
+	}
+	if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_PORT_POLICER_COUNTER_GET))
+	{
+		p_adpt_api->adpt_port_policer_counter_get = adpt_hppe_port_policer_counter_get;
+	}
+	if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_PORT_COMPENSATION_BYTE_GET))
+	{
+		p_adpt_api->adpt_port_compensation_byte_get = adpt_hppe_port_compensation_byte_get;
+	}
+	if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_PORT_POLICER_ENTRY_GET))
+	{
+		p_adpt_api->adpt_port_policer_entry_get = adpt_hppe_port_policer_entry_get;
+	}
+	if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_PORT_POLICER_ENTRY_SET))
+	{
+		p_adpt_api->adpt_port_policer_entry_set = adpt_hppe_port_policer_entry_set;
+	}
+	if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_ACL_POLICER_ENTRY_GET))
+	{
+		p_adpt_api->adpt_acl_policer_entry_get = adpt_hppe_acl_policer_entry_get;
+	}
+	if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_ACL_POLICER_ENTRY_SET))
+	{
+		p_adpt_api->adpt_acl_policer_entry_set = adpt_hppe_acl_policer_entry_set;
+	}
+	if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_POLICER_TIME_SLOT_GET))
+	{
+		p_adpt_api->adpt_policer_time_slot_get = adpt_hppe_policer_time_slot_get;
+	}
+	if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_POLICER_GLOBAL_COUNTER_GET))
+	{
+		p_adpt_api->adpt_policer_global_counter_get = adpt_hppe_policer_global_counter_get;
+	}
+	if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_POLICER_BYPASS_EN_GET))
+	{
+		p_adpt_api->adpt_policer_bypass_en_get = adpt_hppe_policer_bypass_en_get;
+	}
+#endif
+	if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_PORT_COMPENSATION_BYTE_SET))
+	{
+		p_adpt_api->adpt_port_compensation_byte_set = adpt_hppe_port_compensation_byte_set;
+	}
+	if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_POLICER_TIME_SLOT_SET))
+	{
+		p_adpt_api->adpt_policer_time_slot_set = adpt_hppe_policer_time_slot_set;
+	}
+	if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_POLICER_BYPASS_EN_SET))
+	{
+		p_adpt_api->adpt_policer_bypass_en_set = adpt_hppe_policer_bypass_en_set;
+	}
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_portctrl.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_portctrl.c
new file mode 100755
index 0000000..97f0828
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_portctrl.c
@@ -0,0 +1,5611 @@
+/*
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_portctrl_reg.h"
+#include "hppe_portctrl.h"
+#include "hppe_xgportctrl_reg.h"
+#include "hppe_xgportctrl.h"
+#include "hppe_uniphy_reg.h"
+#include "hppe_uniphy.h"
+#include "hppe_fdb_reg.h"
+#include "hppe_fdb.h"
+#include "hppe_global_reg.h"
+#include "hppe_global.h"
+#include "adpt.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "hsl_phy.h"
+#include "hppe_init.h"
+#include "ssdk_init.h"
+#include "ssdk_dts.h"
+#include "ssdk_clk.h"
+#include "adpt_hppe.h"
+#if defined(CPPE)
+#include "adpt_cppe_portctrl.h"
+#include "cppe_portctrl.h"
+#endif
+#include "sfp_phy.h"
+
+#define PORT4_PCS_SEL_GMII_FROM_PCS0 1
+#define PORT4_PCS_SEL_RGMII 0
+
+#define PORT5_PCS_SEL_RGMII 0
+#define PORT5_PCS_SEL_GMII_FROM_PCS0 1
+#define PORT5_PCS_SEL_GMII_FROM_PCS1 2
+#define PORT5_GMAC_SEL_GMAC 1
+#define PORT5_GMAC_SEL_XGMAC 0
+
+#define PORT6_PCS_SEL_RGMII 0
+#define PORT6_PCS_SEL_GMII_FROM_PCS2 1
+#define PORT6_GMAC_SEL_GMAC 1
+#define PORT6_GMAC_SEL_XGMAC 0
+
+#define MAC_SPEED_10M 0
+#define MAC_SPEED_100M 1
+#define MAC_SPEED_1000M 2
+#define MAC_SPEED_10000M 3
+#define MAC_SPEED_2500M 4
+
+#define XGMAC_USXGMII_ENABLE 1
+#define XGMAC_USXGMII_CLEAR 0
+
+#define XGMAC_SPEED_SELECT_10000M 0
+#define XGMAC_SPEED_SELECT_5000M 1
+#define XGMAC_SPEED_SELECT_2500M 2
+#define XGMAC_SPEED_SELECT_1000M 3
+#define LPI_WAKEUP_TIMER	0x20
+#define LPI_SLEEP_TIMER	0x100
+#define PROMISCUOUS_MODE 0x1
+#define PASS_CONTROL_PACKET 0x2
+#define XGMAC_PAUSE_TIME	0xffff
+#define CARRIER_SENSE_SIGNAL_FROM_MAC        0x0
+
+#define PHY_PORT_TO_BM_PORT(port)	(port + 7)
+#define GMAC_IPG_CHECK 0xc
+#define LPI_EEE_TIMER_FREQUENCY 300  /* 300MHZ*/
+#define LPI_EEE_TIMER_UNIT 256
+
+/* This register is used to adjust the write timing for reserving
+ * some bandwidth of the memory to read operation.
+ */
+#define GMAC_TX_THD    0x1
+
+static a_uint32_t port_interface_mode[SW_MAX_NR_DEV][SW_MAX_NR_PORT] = {0};
+
+static a_bool_t
+_adpt_hppe_port_phy_connected (a_uint32_t dev_id, fal_port_t port_id)
+{
+	a_bool_t force_port = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	/* force port which connect s17c or other device chip*/
+	force_port = ssdk_port_feature_get(dev_id, port_id, PHY_F_FORCE);
+	if (force_port == A_TRUE) {
+		SSDK_DEBUG("port_id %d is a force port!\n", port_id);
+		return A_FALSE;
+	}
+	/* sfp port which connect a sfp module*/
+	if (A_TRUE == hsl_port_is_sfp(dev_id, port_id)) {
+		SSDK_DEBUG("port_id %d is a SFP port!\n", port_id);
+		return A_FALSE;
+	}
+	/* cpu port and other ethernet port */
+	if ((SSDK_PHYSICAL_PORT0 == port_id) || (SSDK_PHYSICAL_PORT7 == port_id)) {
+		return A_FALSE;
+	} else {
+		return hppe_mac_port_valid_check (dev_id, port_id);
+	}
+}
+
+static sw_error_t
+_adpt_phy_status_get_from_ppe(a_uint32_t dev_id, a_uint32_t port_id,
+		struct port_phy_status *phy_status)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t reg_field = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (port_id == SSDK_PHYSICAL_PORT5)
+	{
+
+		if (adpt_hppe_chip_revision_get(dev_id)
+			== HPPE_REVISION)
+		{
+			rv = hppe_port_phy_status_1_port5_1_phy_status_get(dev_id,
+							&reg_field);
+			SW_RTN_ON_ERROR (rv);
+		}
+#ifdef CPPE
+		else
+		{
+			rv = cppe_port5_pcs1_phy_status_get(dev_id,
+					&reg_field);
+			SW_RTN_ON_ERROR (rv);
+		}
+#endif
+	} else if (port_id == SSDK_PHYSICAL_PORT1) {
+		/*mac0 port1 as 1G sfp mode*/
+		rv = hppe_port_phy_status_0_port1_phy_status_get(dev_id,
+				&reg_field);
+		SW_RTN_ON_ERROR (rv);
+	} else if (port_id == SSDK_PHYSICAL_PORT2) {
+		/*mac1 port2 as 1G sfp mode*/
+		rv = hppe_port_phy_status_0_port2_phy_status_get(dev_id,
+				&reg_field);
+		SW_RTN_ON_ERROR (rv);
+	} else if (port_id == SSDK_PHYSICAL_PORT6) {
+		rv = hppe_port_phy_status_1_port6_phy_status_get(dev_id,
+						&reg_field);
+		SW_RTN_ON_ERROR (rv);
+	} else {
+		return SW_NOT_SUPPORTED;
+	}
+
+	phy_status->tx_flowctrl = A_TRUE;
+	phy_status->rx_flowctrl = A_TRUE;
+
+	if ((reg_field >> 7) & 0x1)
+	{
+		phy_status->link_status = PORT_LINK_UP;
+		switch (reg_field & 0x7)
+		{
+			case MAC_SPEED_10M:
+				phy_status->speed = FAL_SPEED_10;
+				break;
+			case MAC_SPEED_100M:
+				phy_status->speed = FAL_SPEED_100;
+				break;
+			case MAC_SPEED_1000M:
+				phy_status->speed = FAL_SPEED_1000;
+				break;
+			case MAC_SPEED_10000M:
+				phy_status->speed = FAL_SPEED_10000;
+				break;
+			case MAC_SPEED_2500M:
+				phy_status->speed = FAL_SPEED_2500;
+				break;
+			default:
+				phy_status->speed = FAL_SPEED_BUTT;
+				break;
+		}
+		phy_status->duplex = FAL_FULL_DUPLEX;
+	}
+	else
+	{
+		phy_status->link_status = PORT_LINK_DOWN;
+		phy_status->speed = FAL_SPEED_BUTT;
+		phy_status->duplex = FAL_DUPLEX_BUTT;
+	}
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_adpt_hppe_port_xgmac_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv = hppe_mac_rx_configuration_lm_get(dev_id, port_id, (a_uint32_t*)enable);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_hppe_port_gmac_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = hppe_mac_ctrl2_mac_loop_back_get(dev_id, port_id, (a_uint32_t*)enable);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_hppe_port_xgmac_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv = hppe_mac_rx_configuration_lm_set(dev_id, port_id, (a_uint32_t)enable);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_hppe_port_gmac_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = hppe_mac_ctrl2_mac_loop_back_set(dev_id, port_id, (a_uint32_t)enable);
+
+	return rv;
+}
+#endif
+static sw_error_t
+_adpt_hppe_port_jumbo_size_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t jumbo_size)
+{
+	sw_error_t rv = SW_OK;
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = hppe_mac_jumbo_size_mac_jumbo_size_set(dev_id, port_id, jumbo_size);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_xgmac_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t *max_frame)
+{
+	sw_error_t rv = SW_OK;
+
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv = hppe_mac_rx_configuration_gpsl_get(dev_id,port_id, max_frame);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_gmac_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t *max_frame)
+{
+	sw_error_t rv = SW_OK;
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = hppe_mac_jumbo_size_mac_jumbo_size_get(dev_id, port_id, max_frame);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_xgmac_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t max_frame)
+{
+	sw_error_t rv = SW_OK;
+
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv |= hppe_mac_tx_configuration_jd_set(dev_id, port_id, (a_uint32_t)A_TRUE);
+	rv |= hppe_mac_rx_configuration_gpsl_set(dev_id, port_id, max_frame);
+	rv |= hppe_mac_rx_configuration_wd_set(dev_id, port_id, 1);
+	rv |= hppe_mac_rx_configuration_gmpslce_set(dev_id, port_id, 1);
+	rv |= hppe_mac_packet_filter_pr_set(dev_id, port_id, PROMISCUOUS_MODE);
+	rv |= hppe_mac_packet_filter_pcf_set(dev_id, port_id, PASS_CONTROL_PACKET);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_gmac_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t max_frame)
+{
+	sw_error_t rv = SW_OK;
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv |= hppe_mac_ctrl2_maxfr_set(dev_id, port_id, max_frame);
+	rv |= hppe_mac_ctrl2_crs_sel_set(dev_id, port_id, CARRIER_SENSE_SIGNAL_FROM_MAC);
+	rv |= hppe_mac_dbg_ctrl_hihg_ipg_set(dev_id, port_id, GMAC_IPG_CHECK);
+	rv |= hppe_mac_ctrl2_mac_tx_thd_set(dev_id, port_id, GMAC_TX_THD);
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_adpt_xgmac_port_rx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* port_rxmac_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_rx_configuration_u xgmac_rx_enable;
+
+	memset(&xgmac_rx_enable, 0, sizeof(xgmac_rx_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv = hppe_mac_rx_configuration_get(dev_id, port_id,  &xgmac_rx_enable);
+	if( rv != SW_OK )
+		return rv;
+	*port_rxmac_status = xgmac_rx_enable.bf.re;
+
+	return rv;
+}
+static sw_error_t
+_adpt_gmac_port_rx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* port_rxmac_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_rx_enable;
+
+	memset(&gmac_rx_enable, 0, sizeof(gmac_rx_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = hppe_mac_enable_get(dev_id, port_id, &gmac_rx_enable);
+	if( rv != SW_OK )
+		return rv;
+	* port_rxmac_status = gmac_rx_enable.bf.rxmac_en;
+
+	return rv;
+}
+#endif
+static sw_error_t
+_adpt_xgmac_port_rx_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_rx_configuration_u xgmac_rx_enable;
+
+	memset(&xgmac_rx_enable, 0, sizeof(xgmac_rx_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv |=  hppe_mac_rx_configuration_get(dev_id, port_id,  &xgmac_rx_enable);
+
+	xgmac_rx_enable.bf.acs = 1;
+	xgmac_rx_enable.bf.cst = 1;
+	if (A_TRUE == enable)
+	{
+		xgmac_rx_enable.bf.re = 1;
+	}
+	else {
+		xgmac_rx_enable.bf.re = 0;
+	}
+	rv |= hppe_mac_rx_configuration_set(dev_id, port_id, &xgmac_rx_enable);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_gmac_port_rx_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_rx_enable;
+
+	memset(&gmac_rx_enable, 0, sizeof(gmac_rx_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_rx_enable);
+	if (A_TRUE == enable)
+		gmac_rx_enable.bf.rxmac_en = 1;
+	if (A_FALSE == enable)
+		gmac_rx_enable.bf.rxmac_en = 0;
+	rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_rx_enable);
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_adpt_xgmac_port_tx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *port_txmac_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_tx_configuration_u xgmac_tx_enable;
+
+	memset(&xgmac_tx_enable, 0, sizeof(xgmac_tx_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv = hppe_mac_tx_configuration_get(dev_id, port_id,  &xgmac_tx_enable);
+	if( rv != SW_OK )
+		return  rv;
+	*port_txmac_status = xgmac_tx_enable.bf.te;
+
+	return SW_OK;
+}
+
+static sw_error_t
+_adpt_gmac_port_tx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *port_txmac_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_tx_enable;
+
+	memset(&gmac_tx_enable, 0, sizeof(gmac_tx_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = hppe_mac_enable_get(dev_id, port_id, &gmac_tx_enable);
+	if( rv != SW_OK )
+		return  rv;
+	*port_txmac_status = gmac_tx_enable.bf.txmac_en;
+
+	return SW_OK;
+}
+#endif
+static sw_error_t
+_adpt_xgmac_port_tx_status_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_tx_configuration_u xgmac_tx_enable;
+
+	memset(&xgmac_tx_enable, 0, sizeof(xgmac_tx_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	 rv |=hppe_mac_tx_configuration_get(dev_id, port_id,  &xgmac_tx_enable);
+	 if (A_TRUE == enable)
+		 xgmac_tx_enable.bf.te = 1;
+	 if (A_FALSE == enable)
+		 xgmac_tx_enable.bf.te = 0;
+	 rv |= hppe_mac_tx_configuration_set(dev_id, port_id, &xgmac_tx_enable);
+
+	 return SW_OK;
+}
+
+static sw_error_t
+_adpt_gmac_port_tx_status_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_tx_enable;
+
+	memset(&gmac_tx_enable, 0, sizeof(gmac_tx_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_tx_enable);
+	if (A_TRUE == enable)
+		gmac_tx_enable.bf.txmac_en = 1;
+	if (A_FALSE == enable)
+		gmac_tx_enable.bf.txmac_en = 0;
+	rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_tx_enable);
+
+	return SW_OK;
+}
+
+static sw_error_t
+_adpt_xgmac_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* txfc_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_q0_tx_flow_ctrl_u xgmac_txfc_enable;
+
+	memset(&xgmac_txfc_enable, 0, sizeof(xgmac_txfc_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv = hppe_mac_q0_tx_flow_ctrl_get(dev_id, port_id, &xgmac_txfc_enable);
+	if( rv != SW_OK )
+		return rv;
+	*txfc_status = xgmac_txfc_enable.bf.tfe;
+
+	return  SW_OK;
+}
+
+static sw_error_t
+_adpt_gmac_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* txfc_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_txfc_enable;
+
+	memset(&gmac_txfc_enable, 0, sizeof(gmac_txfc_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = hppe_mac_enable_get(dev_id, port_id, &gmac_txfc_enable);
+	if( rv != SW_OK )
+		return rv;
+	*txfc_status = gmac_txfc_enable.bf.tx_flow_en;
+
+	return  SW_OK;
+}
+
+static sw_error_t
+_adpt_xgmac_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id,  a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_q0_tx_flow_ctrl_u xgmac_txfc_enable;
+
+	memset(&xgmac_txfc_enable, 0, sizeof(xgmac_txfc_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv |= hppe_mac_q0_tx_flow_ctrl_get(dev_id, port_id,  &xgmac_txfc_enable);
+	if (A_TRUE == enable)
+	{
+		xgmac_txfc_enable.bf.tfe = 1;
+		xgmac_txfc_enable.bf.pt = XGMAC_PAUSE_TIME;
+	}
+	if (A_FALSE == enable)
+		xgmac_txfc_enable.bf.tfe = 0;
+	 rv |= hppe_mac_q0_tx_flow_ctrl_set(dev_id, port_id,  &xgmac_txfc_enable);
+
+	 return SW_OK;
+}
+
+static sw_error_t
+_adpt_gmac_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id,  a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_txfc_enable;
+
+	memset(&gmac_txfc_enable, 0, sizeof(gmac_txfc_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_txfc_enable);
+	if (A_TRUE == enable)
+		gmac_txfc_enable.bf.tx_flow_en = 1;
+	if (A_FALSE == enable)
+		gmac_txfc_enable.bf.tx_flow_en = 0;
+	rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_txfc_enable);
+
+	return SW_OK;
+}
+
+static sw_error_t
+_adpt_xgmac_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id,  a_uint32_t* rxfc_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_rx_flow_ctrl_u xgmac_rxfc_enable;
+
+	memset(&xgmac_rxfc_enable, 0, sizeof(xgmac_rxfc_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv = hppe_mac_rx_flow_ctrl_get(dev_id, port_id, &xgmac_rxfc_enable);
+	if(rv != SW_OK)
+		return rv;
+	*rxfc_status = xgmac_rxfc_enable.bf.rfe;
+
+	return  SW_OK;
+}
+
+static sw_error_t
+_adpt_gmac_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* rxfc_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_rxfc_enable;
+
+	memset(&gmac_rxfc_enable, 0, sizeof(gmac_rxfc_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = hppe_mac_enable_get(dev_id, port_id, &gmac_rxfc_enable);
+	if( rv != SW_OK)
+		return rv;
+	*rxfc_status = gmac_rxfc_enable.bf.rx_flow_en;
+
+	return SW_OK;
+}
+
+static sw_error_t
+_adpt_xgmac_port_rxfc_status_set(a_uint32_t dev_id,fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_rx_flow_ctrl_u xgmac_rxfc_enable;
+
+	memset(&xgmac_rxfc_enable, 0, sizeof(xgmac_rxfc_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv |= hppe_mac_rx_flow_ctrl_get(dev_id, port_id, &xgmac_rxfc_enable);
+	if (A_TRUE == enable)
+		xgmac_rxfc_enable.bf.rfe= 1;
+	if (A_FALSE == enable)
+		xgmac_rxfc_enable.bf.rfe = 0;
+	rv |= hppe_mac_rx_flow_ctrl_set(dev_id, port_id, &xgmac_rxfc_enable);
+
+	return SW_OK;
+}
+
+static sw_error_t
+_adpt_gmac_port_rxfc_status_set(a_uint32_t dev_id,fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_rxfc_enable;
+
+	memset(&gmac_rxfc_enable, 0, sizeof(gmac_rxfc_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_rxfc_enable);
+	if (A_TRUE == enable)
+		gmac_rxfc_enable.bf.rx_flow_en = 1;
+	if (A_FALSE == enable)
+		gmac_rxfc_enable.bf.rx_flow_en = 0;
+	rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_rxfc_enable);
+
+	return SW_OK;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_hppe_port_local_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
+					a_bool_t * enable)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_local_loopback_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_local_loopback_get (dev_id, phy_id, enable);
+
+	return rv;
+
+}
+#endif
+sw_error_t
+adpt_hppe_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_restart_autoneg)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_restart_autoneg (dev_id, phy_id);
+	return rv;
+
+}
+sw_error_t
+adpt_hppe_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_duplex_t duplex)
+{
+	union mac_enable_u mac_enable;
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	memset(&mac_enable, 0, sizeof(mac_enable));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_duplex_set)
+		return SW_NOT_SUPPORTED;
+
+	if (FAL_DUPLEX_BUTT <= duplex)
+	{
+		return SW_BAD_PARAM;
+	}
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex);
+	SW_RTN_ON_ERROR (rv);
+
+#if 0
+	port_id = port_id - 1;
+	hppe_mac_enable_get(dev_id, port_id, &mac_enable);
+
+	if (FAL_HALF_DUPLEX == duplex)
+		mac_enable.bf.duplex = 0;
+	if (FAL_FULL_DUPLEX == duplex)
+		mac_enable.bf.duplex = 1;
+
+	hppe_mac_enable_set(dev_id, port_id, &mac_enable);
+
+#endif
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_hppe_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id,
+				      a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_rxmac_status = 0, port_mac_type;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == PORT_XGMAC_TYPE)
+		_adpt_xgmac_port_rx_status_get( dev_id, port_id, &port_rxmac_status);
+	else if (port_mac_type == PORT_GMAC_TYPE)
+		 _adpt_gmac_port_rx_status_get( dev_id, port_id, &port_rxmac_status);
+	else
+		return SW_BAD_VALUE;
+
+	if (port_rxmac_status)
+		*enable = A_TRUE;
+	else
+		*enable = A_FALSE;
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_port_cdt(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t mdi_pair, fal_cable_status_t * cable_status,
+		a_uint32_t * cable_len)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cable_status);
+	ADPT_NULL_POINT_CHECK(cable_len);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_cdt)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_cdt (dev_id, phy_id, mdi_pair, cable_status, cable_len);
+
+	return rv;
+
+}
+#endif
+sw_error_t
+adpt_hppe_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id,
+				      a_bool_t enable)
+{
+	a_uint32_t port_mac_type;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == PORT_XGMAC_TYPE)
+		_adpt_xgmac_port_tx_status_set( dev_id, port_id, enable);
+	else if (port_mac_type == PORT_GMAC_TYPE)
+		_adpt_gmac_port_tx_status_set( dev_id, port_id, enable);
+	else
+		return SW_BAD_VALUE;
+
+	return SW_OK;
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_hppe_port_combo_fiber_mode_set(a_uint32_t dev_id,
+						  a_uint32_t port_id,
+						  fal_port_fiber_mode_t mode)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_combo_fiber_mode_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_combo_fiber_mode_set (dev_id, phy_id, mode);
+
+	return rv;
+
+}
+sw_error_t
+adpt_hppe_port_combo_medium_status_get(a_uint32_t dev_id,
+						     a_uint32_t port_id,
+						     fal_port_medium_t *
+						     medium)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(medium);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_combo_medium_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_combo_medium_status_get (dev_id, phy_id, medium);
+
+	return rv;
+
+}
+
+sw_error_t
+adpt_hppe_port_magic_frame_mac_set(a_uint32_t dev_id, fal_port_t port_id,
+				   fal_mac_addr_t * mac)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mac);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_magic_frame_mac_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_magic_frame_mac_set (dev_id, phy_id,mac);
+
+	return rv;
+
+}
+sw_error_t
+adpt_hppe_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_powersave_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_powersave_set (dev_id, phy_id, enable);
+
+	return rv;
+
+}
+sw_error_t
+adpt_hppe_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_hibernation_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_hibernation_set (dev_id, phy_id, enable);
+
+	return rv;
+
+}
+
+sw_error_t
+adpt_hppe_port_mru_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl)
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	hppe_mru_mtu_ctrl_tbl_mru_set(dev_id, port_id, ctrl->mru_size);
+	hppe_mru_mtu_ctrl_tbl_mru_cmd_set(dev_id, port_id, (a_uint32_t)ctrl->action);
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_ppe_port_mru_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl)
+{
+	a_uint32_t chip_ver = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_port_mru_set(dev_id, port_id, ctrl);
+#endif
+	} else {
+		return adpt_hppe_port_mru_set(dev_id, port_id, ctrl);
+	}
+
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+adpt_hppe_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl)
+{
+	union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;
+
+	memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl);
+	mru_mtu_ctrl_tbl.bf.mtu = ctrl->mtu_size;
+	mru_mtu_ctrl_tbl.bf.mtu_cmd = (a_uint32_t)ctrl->action;
+	hppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &mru_mtu_ctrl_tbl);
+
+	if ((port_id >= SSDK_PHYSICAL_PORT0) && (port_id <= SSDK_PHYSICAL_PORT7))
+	{
+		hppe_mc_mtu_ctrl_tbl_mtu_set(dev_id, port_id, ctrl->mtu_size);
+		hppe_mc_mtu_ctrl_tbl_mtu_cmd_set(dev_id, port_id, (a_uint32_t)ctrl->action);
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_ppe_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl)
+{
+	a_uint32_t chip_ver = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_port_mtu_set(dev_id, port_id, ctrl);
+#endif
+	} else {
+		return adpt_hppe_port_mtu_set(dev_id, port_id, ctrl);
+	}
+
+	return SW_NOT_SUPPORTED;
+}
+#endif
+
+sw_error_t
+adpt_hppe_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t max_frame)
+{
+	a_uint32_t port_mac_type = 0;
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (max_frame > SSDK_MAX_FRAME_SIZE) {
+		return SW_BAD_VALUE;
+	}
+
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == PORT_XGMAC_TYPE)
+		rv |= _adpt_xgmac_port_max_frame_size_set( dev_id, port_id, max_frame);
+	else if (port_mac_type == PORT_GMAC_TYPE)
+	{
+		/*for gmac, rxtoolong have counters when package length is longer than jumbo size and shorter than max frame size,
+		   when package length is longer than max frame size, the rxbadbyte have counters.*/
+		rv |= _adpt_hppe_port_jumbo_size_set(dev_id, port_id, max_frame);
+		rv |= _adpt_gmac_port_max_frame_size_set( dev_id, port_id, max_frame);
+	}
+	else
+		return SW_BAD_VALUE;
+
+	return rv;
+}
+
+sw_error_t
+adpt_ppe_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t max_frame)
+{
+#ifdef CPPE
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION &&
+		port_id == SSDK_PHYSICAL_PORT6)
+	{
+		return adpt_cppe_lpbk_max_frame_size_set(dev_id, port_id, max_frame);
+	}
+#endif
+	return adpt_hppe_port_max_frame_size_set(dev_id, port_id, max_frame);
+}
+
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_hppe_port_8023az_get(a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t * enable)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_8023az_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_8023az_get (dev_id, phy_id, enable);
+
+	return rv;
+
+}
+#endif
+sw_error_t
+adpt_hppe_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t rxfc_status = 0, port_mac_type;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == PORT_XGMAC_TYPE)
+		_adpt_xgmac_port_rxfc_status_get( dev_id, port_id, &rxfc_status);
+	else if (port_mac_type == PORT_GMAC_TYPE)
+		_adpt_gmac_port_rxfc_status_get( dev_id, port_id, &rxfc_status);
+	else
+		return SW_BAD_VALUE;
+
+	if (rxfc_status)
+		*enable = A_TRUE;
+	else
+		*enable = A_FALSE;
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t * enable)
+{
+	a_uint32_t txfc_status = 0, port_mac_type;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == PORT_XGMAC_TYPE)
+		_adpt_xgmac_port_txfc_status_get( dev_id, port_id, &txfc_status);
+	else if (port_mac_type == PORT_GMAC_TYPE)
+		_adpt_gmac_port_txfc_status_get( dev_id, port_id, &txfc_status);
+	else
+		return SW_BAD_VALUE;
+
+	if (txfc_status)
+		*enable = A_TRUE;
+	else
+		*enable = A_FALSE;
+
+	return SW_OK;
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_hppe_port_remote_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
+					 a_bool_t enable)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_remote_loopback_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_remote_loopback_set (dev_id, phy_id, enable);
+
+	return rv;
+
+}
+#endif
+sw_error_t
+adpt_hppe_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+					a_bool_t * status)
+{
+
+	a_uint32_t phy_id = 0;
+	sw_error_t rv = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(status);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_autoneg_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	*status = phy_drv->phy_autoneg_status_get (dev_id, phy_id);
+
+	return SW_OK;
+
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_hppe_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id,
+				      a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_txmac_status = 0, port_mac_type;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == PORT_XGMAC_TYPE)
+		_adpt_xgmac_port_tx_status_get( dev_id, port_id, &port_txmac_status);
+	else if (port_mac_type == PORT_GMAC_TYPE)
+		_adpt_gmac_port_tx_status_get( dev_id, port_id, &port_txmac_status);
+	else
+		return SW_BAD_VALUE;
+
+	if (port_txmac_status)
+		*enable = A_TRUE;
+	else
+		*enable = A_FALSE;
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_port_mdix_get(a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_mdix_mode_t * mode)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mode);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_mdix_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_mdix_get (dev_id, phy_id, mode);
+
+	return rv;
+
+}
+
+sw_error_t
+adpt_hppe_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t port_id;
+	a_uint32_t phy_id;
+	hsl_dev_t *pdev = NULL;
+	hsl_phy_ops_t *phy_drv;
+	struct port_phy_status phy_status = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(status);
+
+	pdev = hsl_dev_ptr_get(dev_id);
+	if (pdev == NULL)
+		return SW_NOT_INITIALIZED;
+
+	*status = 0x0;
+	for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id++)
+	{
+		/* for those ports without PHY device should be sfp port */
+		if (A_FALSE == _adpt_hppe_port_phy_connected(dev_id, port_id))
+		{
+			if (hsl_port_prop_check(dev_id, port_id, HSL_PP_CPU) ||
+				hsl_port_prop_check(dev_id, port_id, HSL_PP_INNER))
+			{
+				*status |= (0x1 << port_id);
+			}
+			else
+			{
+				if(!hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+				{
+					continue;
+				}
+				rv = _adpt_phy_status_get_from_ppe(dev_id,
+					port_id, &phy_status);
+				SW_RTN_ON_ERROR (rv);
+
+				if (phy_status.link_status == PORT_LINK_UP)
+				{
+					*status |= (0x1 << port_id);
+				}
+				else
+				{
+					*status &= ~(0x1 << port_id);
+				}
+			}
+		}
+		else
+		{
+			SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+			if (NULL == phy_drv->phy_link_status_get)
+			{
+				return SW_NOT_SUPPORTED;
+			}
+			rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+			SW_RTN_ON_ERROR(rv);
+
+			if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id))
+			{
+				*status |= (0x1 << port_id);
+			}
+			else
+			{
+				*status &= ~(0x1 << port_id);
+			}
+		}
+	}
+	return SW_OK;
+
+}
+
+sw_error_t
+adpt_hppe_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_mac_type = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == PORT_XGMAC_TYPE)
+		rv = _adpt_hppe_port_xgmac_loopback_set( dev_id, port_id, enable);
+	else if(port_mac_type == PORT_GMAC_TYPE)
+		rv =  _adpt_hppe_port_gmac_loopback_set( dev_id, port_id, enable);
+	else
+		return SW_BAD_VALUE;
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_port_phy_id_get(a_uint32_t dev_id, fal_port_t port_id,
+		      a_uint16_t * org_id, a_uint16_t * rev_id)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+	a_uint32_t phy_data;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(org_id);
+	ADPT_NULL_POINT_CHECK(rev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_id_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_id_get (dev_id, phy_id, &phy_data);
+	SW_RTN_ON_ERROR (rv);
+
+	*org_id = (phy_data >> 16) & 0xffff;
+	*rev_id = phy_data & 0xffff;
+
+	return rv;
+
+}
+sw_error_t
+adpt_hppe_port_mru_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl)
+{
+	sw_error_t rv = SW_OK;
+	union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;
+
+	memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	rv = hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	ctrl->mru_size = mru_mtu_ctrl_tbl.bf.mru;
+	ctrl->action = (fal_fwd_cmd_t)mru_mtu_ctrl_tbl.bf.mru_cmd;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_ppe_port_mru_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl)
+{
+	a_uint32_t chip_ver = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_port_mru_get(dev_id, port_id, ctrl);
+#endif
+	} else {
+		return adpt_hppe_port_mru_get(dev_id, port_id, ctrl);
+	}
+
+	return SW_NOT_SUPPORTED;
+}
+#endif
+
+sw_error_t
+adpt_hppe_port_power_on(a_uint32_t dev_id, fal_port_t port_id)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_power_on)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_power_on(dev_id, phy_id);
+
+	return rv;
+
+}
+sw_error_t
+adpt_hppe_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+			       fal_port_speed_t speed)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_speed_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_speed_set (dev_id, phy_id, speed);
+	SW_RTN_ON_ERROR (rv);
+
+	return rv;
+}
+sw_error_t
+adpt_hppe_port_interface_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t * mode)
+{
+	sw_error_t rv = 0;
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU))
+	{
+		return SW_BAD_PARAM;
+	}
+	*mode = port_interface_mode[dev_id][port_id];
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_duplex_t * pduplex)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+	struct port_phy_status phy_status = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(pduplex);
+
+	if (port_id == SSDK_PHYSICAL_PORT0 || port_id == SSDK_PHYSICAL_PORT7)
+	{
+		*pduplex = FAL_FULL_DUPLEX;
+		return SW_OK;
+	}
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	/* for those ports without PHY device should be sfp port */
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+	{
+
+		rv = _adpt_phy_status_get_from_ppe(dev_id,
+			port_id, &phy_status);
+		SW_RTN_ON_ERROR (rv);
+		*pduplex = phy_status.duplex;
+
+	}
+	else
+	{
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+		if (NULL == phy_drv->phy_duplex_get)
+			return SW_NOT_SUPPORTED;
+
+		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR (rv);
+		rv = phy_drv->phy_duplex_get (dev_id, phy_id, pduplex);
+		SW_RTN_ON_ERROR (rv);
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+				     a_uint32_t * autoadv)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(autoadv);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_autoneg_adv_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	*autoadv = 0;
+	rv = phy_drv->phy_autoneg_adv_get (dev_id, phy_id, autoadv);
+	SW_RTN_ON_ERROR (rv);
+
+	return SW_OK;
+
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_hppe_port_mdix_status_get(a_uint32_t dev_id, fal_port_t port_id,
+				     fal_port_mdix_status_t * mode)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mode);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_mdix_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_mdix_status_get (dev_id, phy_id, mode);
+
+	return rv;
+
+}
+#endif
+sw_error_t
+adpt_hppe_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t * status)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+	struct port_phy_status phy_status = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(status);
+
+	if (port_id == SSDK_PHYSICAL_PORT0 || port_id == SSDK_PHYSICAL_PORT7)
+	{
+		*status = A_TRUE;
+		return SW_OK;
+	}
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	/* for those ports without PHY device should be sfp port */
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+	{
+		rv = _adpt_phy_status_get_from_ppe(dev_id,
+			port_id, &phy_status);
+		SW_RTN_ON_ERROR (rv);
+		*status = (a_bool_t) phy_status.link_status;
+	}
+	else
+	{
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+		if (NULL == phy_drv->phy_link_status_get)
+			return SW_NOT_SUPPORTED;
+
+		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR (rv);
+
+		if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id))
+		{
+			*status = A_TRUE;
+		}
+		else
+		{
+			*status = A_FALSE;
+		}
+	}
+
+	return SW_OK;
+
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_hppe_port_8023az_set(a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t enable)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_8023az_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_8023az_set (dev_id, phy_id, enable);
+
+	return rv;
+
+}
+sw_error_t
+adpt_hppe_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_powersave_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_powersave_get (dev_id, phy_id, enable);
+
+	return rv;
+
+}
+
+sw_error_t
+adpt_hppe_port_combo_prefer_medium_get(a_uint32_t dev_id,
+						     a_uint32_t port_id,
+						     fal_port_medium_t *
+						     medium)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(medium);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_combo_prefer_medium_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_combo_prefer_medium_get (dev_id, phy_id, medium);
+
+	return rv;
+
+}
+#endif
+sw_error_t
+adpt_hppe_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t *max_frame)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_mac_type = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(max_frame);
+
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == PORT_XGMAC_TYPE)
+	{
+		rv = _adpt_xgmac_port_max_frame_size_get( dev_id, port_id, max_frame);
+	}
+	else if (port_mac_type == PORT_GMAC_TYPE)
+	{
+		rv = _adpt_gmac_port_max_frame_size_get( dev_id, port_id, max_frame);
+	}
+	else
+	{
+		return SW_BAD_VALUE;
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_ppe_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t *max_frame)
+{
+#ifdef CPPE
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION &&
+		port_id == SSDK_PHYSICAL_PORT6)
+	{
+		return adpt_cppe_lpbk_max_frame_size_get(dev_id, port_id, max_frame);
+	}
+#endif
+	return adpt_hppe_port_max_frame_size_get(dev_id, port_id, max_frame);
+
+}
+
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_hppe_port_combo_prefer_medium_set(a_uint32_t dev_id,
+					     a_uint32_t port_id,
+					     fal_port_medium_t medium)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_combo_prefer_medium_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_combo_prefer_medium_set (dev_id, phy_id, medium);
+
+	return rv;
+
+}
+#endif
+sw_error_t
+adpt_hppe_port_power_off(a_uint32_t dev_id, fal_port_t port_id)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_power_off)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_power_off(dev_id, phy_id);
+
+	return rv;
+
+}
+sw_error_t
+adpt_hppe_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_mac_type;
+	struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id);
+	adpt_api_t *p_adpt_api;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (!priv)
+		return SW_FAIL;
+
+	if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6))
+		return SW_BAD_VALUE;
+
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == PORT_XGMAC_TYPE)
+		rv = _adpt_xgmac_port_txfc_status_set( dev_id, port_id, enable);
+	else if (port_mac_type == PORT_GMAC_TYPE)
+		rv = _adpt_gmac_port_txfc_status_set( dev_id, port_id, enable);
+	else
+		return SW_BAD_VALUE;
+
+	if (rv != SW_OK)
+		return rv;
+
+	priv->port_old_tx_flowctrl[port_id - 1] = enable;
+
+	/*keep bm status same with port*/
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+	if (p_adpt_api && p_adpt_api->adpt_port_bm_ctrl_set)
+		rv = p_adpt_api->adpt_port_bm_ctrl_set(dev_id,
+					PHY_PORT_TO_BM_PORT(port_id),
+					enable);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id,
+				     a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_mac_type;
+	struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id);
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (!priv)
+		return SW_FAIL;
+
+	if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6))
+		return SW_BAD_VALUE;
+
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if(port_mac_type == PORT_XGMAC_TYPE)
+		rv = _adpt_xgmac_port_rxfc_status_set( dev_id, port_id, enable);
+	else if (port_mac_type == PORT_GMAC_TYPE)
+		rv = _adpt_gmac_port_rxfc_status_set( dev_id, port_id, enable);
+	else
+		return SW_BAD_VALUE;
+
+	if (rv != SW_OK)
+		return rv;
+
+	priv->port_old_rx_flowctrl[port_id - 1] = enable;
+
+	return SW_OK;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_hppe_port_counter_set(a_uint32_t dev_id, fal_port_t port_id,
+		   a_bool_t enable)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_counter_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_counter_set (dev_id, phy_id, enable);
+
+	return rv;
+}
+sw_error_t
+adpt_hppe_port_combo_fiber_mode_get(a_uint32_t dev_id,
+						  a_uint32_t port_id,
+						  fal_port_fiber_mode_t * mode)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mode);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+	  	return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_combo_fiber_mode_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_combo_fiber_mode_get (dev_id, phy_id, mode);
+
+	return rv;
+
+}
+
+sw_error_t
+adpt_hppe_port_local_loopback_set(a_uint32_t dev_id,
+						fal_port_t port_id,
+						a_bool_t enable)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_local_loopback_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_local_loopback_set (dev_id, phy_id, enable);
+
+	return rv;
+
+}
+sw_error_t
+adpt_hppe_port_wol_status_set(a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t enable)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_wol_status_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_wol_status_set (dev_id, phy_id, enable);
+
+	return rv;
+
+
+}
+sw_error_t
+adpt_hppe_port_magic_frame_mac_get(a_uint32_t dev_id, fal_port_t port_id,
+				   fal_mac_addr_t * mac)
+{
+
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mac);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_magic_frame_mac_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_magic_frame_mac_get (dev_id, phy_id,mac);
+
+	return rv;
+
+}
+
+sw_error_t
+adpt_hppe_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+	a_bool_t txfc_enable, rxfc_enable;
+
+#if defined(CPPE)
+	if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) &&
+		(port_id == SSDK_PHYSICAL_PORT6)) {
+		return adpt_cppe_switch_port_loopback_flowctrl_get(dev_id,
+				port_id, enable);
+	}
+#endif
+	rv = adpt_hppe_port_txfc_status_get(dev_id, port_id,  &txfc_enable);
+	rv |= adpt_hppe_port_rxfc_status_get(dev_id, port_id,  &rxfc_enable);
+	if(rv != SW_OK)
+		return rv;
+	*enable = txfc_enable & rxfc_enable;
+
+	return SW_OK;
+}
+#endif
+sw_error_t
+adpt_hppe_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id,
+				      a_bool_t enable)
+{
+	a_uint32_t port_mac_type;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == PORT_XGMAC_TYPE)
+		_adpt_xgmac_port_rx_status_set(dev_id, port_id, enable);
+	else if (port_mac_type == PORT_GMAC_TYPE)
+		_adpt_gmac_port_rx_status_set(dev_id, port_id, enable);
+	else
+		return SW_BAD_VALUE;
+
+	return SW_OK;
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_hppe_port_counter_get(a_uint32_t dev_id, fal_port_t port_id,
+		   a_bool_t * enable)
+{
+
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	   {
+		return SW_BAD_PARAM;
+	   }
+	 if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		 return SW_NOT_SUPPORTED;
+
+	 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	 if (NULL == phy_drv->phy_counter_get)
+		return SW_NOT_SUPPORTED;
+
+	 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	 SW_RTN_ON_ERROR (rv);
+
+	 rv = phy_drv->phy_counter_get (dev_id, phy_id, enable);
+
+	 return rv;
+
+}
+#endif
+
+static sw_error_t
+_adpt_hppe_port_interface_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t mode)
+{
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU) &&
+		mode != PORT_INTERFACE_MODE_MAX)
+	{
+		return SW_BAD_PARAM;
+	}
+
+	port_interface_mode[dev_id][port_id] = mode;
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_port_interface_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t mode)
+{
+	sw_error_t rv = SW_OK;
+	struct qca_phy_priv *priv;
+
+	priv = ssdk_phy_priv_data_get(dev_id);
+	SW_RTN_ON_NULL(priv);
+	qca_mac_sw_sync_work_stop(priv);
+
+	rv = _adpt_hppe_port_interface_mode_set(dev_id, port_id, mode);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_hppe_gmac_speed_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_speed_t speed)
+{
+	sw_error_t rv = SW_OK;
+	union mac_speed_u mac_speed;
+
+	memset(&mac_speed, 0, sizeof(mac_speed));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	hppe_mac_speed_get(dev_id, port_id, &mac_speed);
+
+	if(FAL_SPEED_10 == speed)
+		mac_speed.bf.mac_speed = MAC_SPEED_10M;
+	else if(FAL_SPEED_100 == speed)
+		mac_speed.bf.mac_speed = MAC_SPEED_100M;
+	else if(FAL_SPEED_1000 == speed || FAL_SPEED_2500 == speed)
+		mac_speed.bf.mac_speed = MAC_SPEED_1000M;
+
+	rv = hppe_mac_speed_set(dev_id, port_id, &mac_speed);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_hppe_xgmac_speed_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_speed_t speed)
+{
+	sw_error_t rv = SW_OK;
+	union mac_tx_configuration_u mac_tx_configuration;
+	a_uint32_t mode = 0;
+
+	memset(&mac_tx_configuration, 0, sizeof(mac_tx_configuration));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	hppe_mac_tx_configuration_get(dev_id, port_id, &mac_tx_configuration);
+
+	if(FAL_SPEED_1000 == speed)
+	{
+		mac_tx_configuration.bf.uss= XGMAC_USXGMII_CLEAR;
+		mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_1000M;
+	}
+	else if(FAL_SPEED_10000 == speed)
+	{
+		if (port_id == SSDK_PHYSICAL_PORT0)
+		{
+			mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1);
+		}
+		else
+		{
+			mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE2);
+		}
+		if (mode == PORT_WRAPPER_USXGMII)
+		{
+			mac_tx_configuration.bf.uss= XGMAC_USXGMII_ENABLE;
+			mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_10000M;
+		}
+		else
+		{
+			mac_tx_configuration.bf.uss= XGMAC_USXGMII_CLEAR;
+			mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_10000M;
+		}
+	}
+	else if(FAL_SPEED_5000 == speed)
+	{
+		mac_tx_configuration.bf.uss= XGMAC_USXGMII_ENABLE;
+		mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_5000M;
+	}
+	else if(FAL_SPEED_2500 == speed)
+	{
+		if (port_id == SSDK_PHYSICAL_PORT0)
+		{
+			mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1);
+		}
+		else
+		{
+			mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE2);
+		}
+		if (mode == PORT_WRAPPER_USXGMII)
+		{
+			mac_tx_configuration.bf.uss= XGMAC_USXGMII_ENABLE;
+			mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_2500M;
+		}
+		else
+		{
+			mac_tx_configuration.bf.uss= XGMAC_USXGMII_CLEAR;
+			mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_2500M;
+		}
+	}
+	else if(FAL_SPEED_100 == speed)
+	{
+		mac_tx_configuration.bf.uss= XGMAC_USXGMII_CLEAR;
+		mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_1000M;
+	}
+	else if(FAL_SPEED_10 == speed)
+	{
+		mac_tx_configuration.bf.uss= XGMAC_USXGMII_CLEAR;
+		mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_1000M;
+	}
+
+	rv = hppe_mac_tx_configuration_set(dev_id, port_id, &mac_tx_configuration);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_hppe_gmac_duplex_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_duplex_t duplex)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u mac_enable;
+
+	memset(&mac_enable, 0, sizeof(mac_enable));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	hppe_mac_enable_get(dev_id, port_id, &mac_enable);
+
+	if (FAL_FULL_DUPLEX == duplex)
+		mac_enable.bf.duplex = 1;
+	else
+		mac_enable.bf.duplex = 0;
+
+	rv = hppe_mac_enable_set(dev_id, port_id, &mac_enable);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_port_mac_duplex_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_duplex_t duplex)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_mac_type;
+
+	port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == PORT_XGMAC_TYPE)
+	{
+		return rv;
+	}
+	else if (port_mac_type == PORT_GMAC_TYPE)
+	{
+		rv = _adpt_hppe_gmac_duplex_set(dev_id, port_id, duplex);
+	}
+	else
+	{
+		return SW_BAD_VALUE;
+	}
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_hppe_port_mux_mac_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t port_type)
+{
+	sw_error_t rv = SW_OK;
+	union port_mux_ctrl_u port_mux_ctrl;
+	a_uint32_t mode0, mode1;
+
+	memset(&port_mux_ctrl, 0, sizeof(port_mux_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_port_mux_ctrl_get(dev_id, &port_mux_ctrl);
+	port_mux_ctrl.bf.port4_pcs_sel = PORT4_PCS_SEL_GMII_FROM_PCS0;
+
+	if (port_id == HPPE_MUX_PORT1)
+	{
+		if (port_type == PORT_GMAC_TYPE)
+		{
+			mode0 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0);
+			mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1);
+			if ((mode0 == PORT_WRAPPER_PSGMII) ||
+				(mode0 == PORT_WRAPPER_PSGMII_FIBER) ||
+				(mode0 == PORT_WRAPPER_SGMII4_RGMII4) ||
+				(mode0 == PORT_WRAPPER_SGMII_CHANNEL4))
+			{
+				port_mux_ctrl.bf.port5_pcs_sel = PORT5_PCS_SEL_GMII_FROM_PCS0;
+				port_mux_ctrl.bf.port5_gmac_sel = PORT5_GMAC_SEL_GMAC;
+			}
+			if (mode1 == PORT_WRAPPER_SGMII0_RGMII4 ||
+					mode1 == PORT_WRAPPER_SGMII_CHANNEL0 ||
+					mode1 == PORT_WRAPPER_SGMII_PLUS ||
+					mode1 == PORT_WRAPPER_SGMII_FIBER)
+			{
+				port_mux_ctrl.bf.port5_pcs_sel = PORT5_PCS_SEL_GMII_FROM_PCS1;
+				port_mux_ctrl.bf.port5_gmac_sel = PORT5_GMAC_SEL_GMAC;
+			}
+		}
+		else if (port_type == PORT_XGMAC_TYPE)
+		{
+			port_mux_ctrl.bf.port5_pcs_sel = PORT5_PCS_SEL_GMII_FROM_PCS1;
+			port_mux_ctrl.bf.port5_gmac_sel = PORT5_GMAC_SEL_XGMAC;
+		}
+		else
+			return SW_NOT_SUPPORTED;
+	}
+	else if (port_id == HPPE_MUX_PORT2)
+	{
+		if (port_type == PORT_GMAC_TYPE)
+		{
+			port_mux_ctrl.bf.port6_pcs_sel = PORT6_PCS_SEL_GMII_FROM_PCS2;
+			port_mux_ctrl.bf.port6_gmac_sel = PORT6_GMAC_SEL_GMAC;
+		}
+		else if (port_type == PORT_XGMAC_TYPE)
+		{
+			port_mux_ctrl.bf.port6_pcs_sel = PORT6_PCS_SEL_GMII_FROM_PCS2;
+			port_mux_ctrl.bf.port6_gmac_sel = PORT6_GMAC_SEL_XGMAC;
+		}
+		else
+			return SW_NOT_SUPPORTED;
+	}
+	else
+		return SW_OK;
+
+	rv = hppe_port_mux_ctrl_set(dev_id, &port_mux_ctrl);
+
+	return rv;
+}
+
+static sw_error_t
+adpt_hppe_port_xgmac_promiscuous_mode_set(a_uint32_t dev_id,
+	a_uint32_t port_id)
+{
+	sw_error_t rv = 0;
+
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+
+	rv = hppe_mac_packet_filter_pr_set(dev_id, port_id, PROMISCUOUS_MODE);
+
+	SW_RTN_ON_ERROR (rv);
+
+	rv = hppe_mac_packet_filter_pcf_set(dev_id, port_id, PASS_CONTROL_PACKET);
+
+	return rv;
+}
+static sw_error_t
+adpt_hppe_port_speed_change_mac_reset(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	a_uint32_t uniphy_index = 0, mode = 0;
+	a_uint32_t rxfc_status = 0, txfc_status = 0;
+	sw_error_t rv = 0;
+
+	if (port_id == HPPE_MUX_PORT1) {
+		uniphy_index = SSDK_UNIPHY_INSTANCE1;
+	} else if (port_id == HPPE_MUX_PORT2) {
+		uniphy_index = SSDK_UNIPHY_INSTANCE2;
+	} else {
+		return SW_OK;
+	}
+	mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index);
+	if (mode == PORT_WRAPPER_USXGMII) {
+		ssdk_port_mac_clock_reset(dev_id, port_id);
+		/*restore xgmac's pr and pcf setting after reset operation*/
+		rv = adpt_hppe_port_xgmac_promiscuous_mode_set(dev_id,
+			port_id);
+		SW_RTN_ON_ERROR(rv);
+		/*flowctrl need to be configured when reset XGMAC*/
+		rv = _adpt_xgmac_port_rxfc_status_get(dev_id, port_id,
+			&rxfc_status);
+		SW_RTN_ON_ERROR(rv);
+		rv = _adpt_xgmac_port_rxfc_status_set(dev_id, port_id,
+			rxfc_status);
+		SW_RTN_ON_ERROR(rv);
+
+		rv = _adpt_xgmac_port_txfc_status_get(dev_id, port_id,
+			&txfc_status);
+		SW_RTN_ON_ERROR(rv);
+		rv = _adpt_xgmac_port_txfc_status_set(dev_id, port_id,
+			txfc_status);
+	}
+	return rv;
+}
+static sw_error_t
+adpt_hppe_port_interface_mode_switch_mac_reset(a_uint32_t dev_id,
+	a_uint32_t port_id)
+{
+	a_uint32_t uniphy_index = 0, mode = 0;
+	sw_error_t rv = 0;
+	phy_type_t phy_type;
+	a_uint32_t port_mac_type;
+
+	phy_type = hsl_phy_type_get(dev_id, port_id);
+	if (phy_type != AQUANTIA_PHY_CHIP && phy_type != SFP_PHY_CHIP) {
+		return SW_OK;
+	}
+
+	if (port_id == HPPE_MUX_PORT1) {
+		uniphy_index = SSDK_UNIPHY_INSTANCE1;
+	} else if (port_id == HPPE_MUX_PORT2) {
+		uniphy_index = SSDK_UNIPHY_INSTANCE2;
+	} else {
+		return SW_OK;
+	}
+
+	mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index);
+	if ((mode == PORT_WRAPPER_USXGMII) ||
+		(mode == PORT_WRAPPER_SGMII_CHANNEL0) ||
+		(mode == PORT_WRAPPER_SGMII0_RGMII4) ||
+		(mode == PORT_WRAPPER_SGMII_FIBER) ||
+		(mode == PORT_WRAPPER_10GBASE_R) ||
+		(mode == PORT_WRAPPER_SGMII_PLUS)) {
+		ssdk_port_mac_clock_reset(dev_id, port_id);
+		port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id);
+		if (port_mac_type == PORT_XGMAC_TYPE) {
+			/*restore xgmac's pr and pcf setting after reset operation*/
+			rv = adpt_hppe_port_xgmac_promiscuous_mode_set(dev_id,
+			port_id);
+		}
+	}
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_port_mac_speed_set(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_port_speed_t speed)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_mac_type;
+
+	port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == PORT_XGMAC_TYPE)
+	{
+		rv = _adpt_hppe_xgmac_speed_set(dev_id, port_id, speed);
+
+	}
+	else if (port_mac_type == PORT_GMAC_TYPE)
+	{
+		rv = _adpt_hppe_gmac_speed_set(dev_id, port_id, speed);
+	}
+	else
+	{
+		return SW_BAD_VALUE;
+	}
+	return rv;
+}
+static sw_error_t
+_adpt_hppe_port_mux_set(a_uint32_t dev_id, fal_port_t port_id,
+	a_uint32_t mode1, a_uint32_t mode2)
+{
+	a_uint32_t  mode = 0, port_type;
+	sw_error_t rv = SW_OK;
+
+	port_type = qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_type == PORT_GMAC_TYPE)
+	{
+		rv = adpt_hppe_port_mac_speed_set(dev_id, port_id, FAL_SPEED_1000);
+		rv = adpt_hppe_port_mac_duplex_set(dev_id, port_id, FAL_FULL_DUPLEX);
+	}
+	else if (port_type == PORT_XGMAC_TYPE)
+	{
+		if (port_id == HPPE_MUX_PORT1)
+			mode = mode1;
+		else if (port_id == HPPE_MUX_PORT2)
+			mode = mode2;
+		else
+			return SW_NOT_SUPPORTED;
+		if (mode == PORT_WRAPPER_SGMII_PLUS)
+		{
+			rv = adpt_hppe_port_mac_speed_set(dev_id, port_id, FAL_SPEED_2500);
+			rv = adpt_hppe_port_mac_duplex_set(dev_id, port_id, FAL_FULL_DUPLEX);
+		}
+		else
+		{
+			rv = adpt_hppe_port_mac_speed_set(dev_id, port_id, FAL_SPEED_10000);
+			rv = adpt_hppe_port_mac_duplex_set(dev_id, port_id, FAL_FULL_DUPLEX);
+		}
+	}
+	if ((port_type == PORT_GMAC_TYPE) ||(port_type == PORT_XGMAC_TYPE)) {
+		if (adpt_hppe_chip_revision_get(dev_id) == HPPE_REVISION) {
+		 	rv = _adpt_hppe_port_mux_mac_set(dev_id, port_id, port_type);
+		} else if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+#if defined(CPPE)
+			rv = _adpt_cppe_port_mux_mac_set(dev_id, port_id, port_type);
+#endif
+		}
+	}
+
+	if (port_id >= HPPE_MUX_PORT1) {
+		if (port_type == PORT_GMAC_TYPE) {
+			rv = _adpt_xgmac_port_txfc_status_set( dev_id, port_id, A_FALSE);
+			SW_RTN_ON_ERROR(rv);
+			rv = _adpt_xgmac_port_rxfc_status_set( dev_id, port_id, A_FALSE);
+			SW_RTN_ON_ERROR(rv);
+		} else if (port_type == PORT_XGMAC_TYPE) {
+			rv = _adpt_gmac_port_txfc_status_set( dev_id, port_id, A_FALSE);
+			SW_RTN_ON_ERROR(rv);
+			rv = _adpt_gmac_port_rxfc_status_set( dev_id, port_id, A_FALSE);
+			SW_RTN_ON_ERROR(rv);
+		} else {
+			return SW_NOT_SUPPORTED;
+		}
+		rv = adpt_hppe_port_interface_mode_switch_mac_reset(dev_id, port_id);
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_port_mux_mac_type_set(a_uint32_t dev_id, fal_port_t port_id,
+	a_uint32_t mode0, a_uint32_t mode1, a_uint32_t mode2)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t mode_tmp;
+
+	/*init the port interface mode before set it according to three mac modes*/
+	rv = _adpt_hppe_port_interface_mode_set(dev_id, port_id, PORT_INTERFACE_MODE_MAX);
+	SW_RTN_ON_ERROR(rv);
+
+	switch (mode0) {
+		case PORT_WRAPPER_PSGMII_FIBER:
+			if(port_id >= SSDK_PHYSICAL_PORT1  && port_id <= SSDK_PHYSICAL_PORT5)
+			{
+				qca_hppe_port_mac_type_set(dev_id, port_id, PORT_GMAC_TYPE);
+				if (port_id == SSDK_PHYSICAL_PORT5) {
+					_adpt_hppe_port_interface_mode_set(dev_id,
+							SSDK_PHYSICAL_PORT5, PHY_PSGMII_FIBER);
+				} else {
+					_adpt_hppe_port_interface_mode_set(dev_id,
+							port_id, PHY_PSGMII_BASET);
+				}
+			}
+			break;
+		case PORT_WRAPPER_PSGMII:
+			if((port_id >= SSDK_PHYSICAL_PORT1 && port_id <= SSDK_PHYSICAL_PORT4) ||
+					(port_id == SSDK_PHYSICAL_PORT5 &&
+					 mode1 == PORT_WRAPPER_MAX))
+			{
+				qca_hppe_port_mac_type_set(dev_id, port_id, PORT_GMAC_TYPE);
+				_adpt_hppe_port_interface_mode_set(dev_id, port_id, PHY_PSGMII_BASET);
+			}
+			break;
+		case PORT_WRAPPER_QSGMII:
+			if(port_id >= SSDK_PHYSICAL_PORT1 && port_id <= SSDK_PHYSICAL_PORT4)
+			{
+				qca_hppe_port_mac_type_set(dev_id, port_id, PORT_GMAC_TYPE);
+				_adpt_hppe_port_interface_mode_set(dev_id, port_id, PORT_QSGMII);
+			}
+			break;
+		case PORT_WRAPPER_SGMII0_RGMII4:
+		case PORT_WRAPPER_SGMII_CHANNEL0:
+		case PORT_WRAPPER_SGMII_FIBER:
+#ifdef CPPE
+		case PORT_WRAPPER_SGMII_PLUS:
+			if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION
+				&& port_id == SSDK_PHYSICAL_PORT4)
+			{
+				qca_hppe_port_mac_type_set(dev_id, port_id,
+					PORT_GMAC_TYPE);
+				if((mode0 == PORT_WRAPPER_SGMII0_RGMII4 ||
+					mode0 == PORT_WRAPPER_SGMII_CHANNEL0))
+				{
+					if(hsl_port_prop_check (dev_id, port_id,
+						HSL_PP_EXCL_CPU))
+					{
+						_adpt_hppe_port_interface_mode_set(dev_id, port_id,
+							PHY_SGMII_BASET);
+					}
+					else
+					{
+						SSDK_ERROR("Port bitmap is incorrect when port 4"
+							"support sgmii for CPPE\n");
+						return SW_NOT_SUPPORTED;
+					}
+				}
+				else if(mode0 == PORT_WRAPPER_SGMII_PLUS)
+				{
+					_adpt_hppe_port_interface_mode_set(dev_id, port_id,
+						PORT_SGMII_PLUS);
+				}
+				else
+				{
+					SSDK_ERROR("CPPE doesn't support mode0 : %x\n",
+						mode0);
+					return SW_NOT_SUPPORTED;
+				}
+				break;
+			}
+#endif
+			if(port_id == SSDK_PHYSICAL_PORT1)
+			{
+				qca_hppe_port_mac_type_set(dev_id, SSDK_PHYSICAL_PORT1,
+						PORT_GMAC_TYPE);
+				if(mode0 == PORT_WRAPPER_SGMII_FIBER)
+				{
+					_adpt_hppe_port_interface_mode_set(dev_id,
+							SSDK_PHYSICAL_PORT1, PORT_SGMII_FIBER);
+				}
+				else
+				{
+					_adpt_hppe_port_interface_mode_set(dev_id,
+							SSDK_PHYSICAL_PORT1, PHY_SGMII_BASET);
+				}
+			}
+			break;
+		case PORT_WRAPPER_SGMII1_RGMII4:
+		case PORT_WRAPPER_SGMII_CHANNEL1:
+			if(port_id == SSDK_PHYSICAL_PORT2)
+			{
+				qca_hppe_port_mac_type_set(dev_id, SSDK_PHYSICAL_PORT2,
+						PORT_GMAC_TYPE);
+				_adpt_hppe_port_interface_mode_set(dev_id,
+						SSDK_PHYSICAL_PORT2, PHY_SGMII_BASET);
+			}
+			break;
+		case PORT_WRAPPER_SGMII4_RGMII4:
+		case PORT_WRAPPER_SGMII_CHANNEL4:
+			if(port_id == SSDK_PHYSICAL_PORT5)
+			{
+				qca_hppe_port_mac_type_set(dev_id, SSDK_PHYSICAL_PORT5,
+						PORT_GMAC_TYPE);
+				_adpt_hppe_port_interface_mode_set(dev_id,
+						SSDK_PHYSICAL_PORT5, PHY_SGMII_BASET);
+			}
+			break;
+		default:
+			break;
+	}
+	if(port_id == SSDK_PHYSICAL_PORT5 ||port_id == SSDK_PHYSICAL_PORT6)
+	{
+		if(port_id == SSDK_PHYSICAL_PORT5)
+			mode_tmp = mode1;
+		else
+			mode_tmp = mode2;
+
+		switch(mode_tmp)
+		{
+			case PORT_WRAPPER_SGMII_CHANNEL0:
+			case PORT_WRAPPER_SGMII0_RGMII4:
+			case PORT_WRAPPER_SGMII_FIBER:
+				qca_hppe_port_mac_type_set(dev_id, port_id, PORT_GMAC_TYPE);
+				if(mode_tmp == PORT_WRAPPER_SGMII_FIBER)
+				{
+					_adpt_hppe_port_interface_mode_set(dev_id, port_id,
+						PORT_SGMII_FIBER);
+				}
+				else
+				{
+					_adpt_hppe_port_interface_mode_set(dev_id, port_id,
+						PHY_SGMII_BASET);
+				}
+				break;
+			case PORT_WRAPPER_SGMII_PLUS:
+				if (ssdk_port_feature_get(dev_id, port_id, PHY_F_QGMAC)) {
+					qca_hppe_port_mac_type_set(dev_id, port_id,
+							PORT_GMAC_TYPE);
+				} else {
+					qca_hppe_port_mac_type_set(dev_id, port_id,
+							PORT_XGMAC_TYPE);
+				}
+				_adpt_hppe_port_interface_mode_set(dev_id, port_id, PORT_SGMII_PLUS);
+				break;
+			case PORT_WRAPPER_USXGMII:
+				qca_hppe_port_mac_type_set(dev_id, port_id, PORT_XGMAC_TYPE);
+				_adpt_hppe_port_interface_mode_set(dev_id, port_id, PORT_USXGMII);
+				break;
+			case PORT_WRAPPER_10GBASE_R:
+				qca_hppe_port_mac_type_set(dev_id, port_id, PORT_XGMAC_TYPE);
+				_adpt_hppe_port_interface_mode_set(dev_id, port_id, PORT_10GBASE_R);
+				break;
+			default:
+				break;
+		}
+	}
+
+	rv = _adpt_hppe_port_mux_set(dev_id, port_id,mode1, mode2);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_hppe_instance0_mode_get(a_uint32_t dev_id, a_uint32_t *mode0)
+{
+	a_uint32_t port_id = 0;
+
+	for(port_id = SSDK_PHYSICAL_PORT1; port_id <= SSDK_PHYSICAL_PORT5; port_id++)
+	{
+		if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU))
+		{
+			continue;
+		}
+		SSDK_DEBUG("port_id:%d, port_interface_mode:%d\n", port_id,
+			port_interface_mode[dev_id][port_id]);
+		if(port_interface_mode[dev_id][port_id] == PHY_PSGMII_BASET)
+		{
+			if(*mode0 != PORT_WRAPPER_MAX && *mode0 != PORT_WRAPPER_PSGMII)
+			{
+				SSDK_ERROR("when the port_interface_mode of port %d is %d, "
+					"mode0:%d cannot be supported\n",
+					port_id, port_interface_mode[dev_id][port_id], *mode0);
+				return SW_NOT_SUPPORTED;
+			}
+			*mode0 = PORT_WRAPPER_PSGMII;
+		}
+
+		if(port_interface_mode[dev_id][port_id] == PHY_PSGMII_FIBER &&
+			port_id == SSDK_PHYSICAL_PORT5)
+		{
+			*mode0 = PORT_WRAPPER_PSGMII_FIBER;
+		}
+
+		if(port_interface_mode[dev_id][port_id] == PORT_QSGMII)
+		{
+			if((*mode0 != PORT_WRAPPER_MAX && *mode0 != PORT_WRAPPER_QSGMII) ||
+				port_id == SSDK_PHYSICAL_PORT5)
+			{
+				SSDK_ERROR("when the port_interface_mode of port %d is %d, "
+					"mode0:%d cannot be supported\n",
+					port_id, port_interface_mode[dev_id][port_id], *mode0);
+				return SW_NOT_SUPPORTED;
+			}
+			*mode0 = PORT_WRAPPER_QSGMII;
+		}
+
+		if(port_interface_mode[dev_id][port_id] == PHY_SGMII_BASET ||
+			port_interface_mode[dev_id][port_id] == PORT_SGMII_FIBER)
+		{
+			if(*mode0 !=PORT_WRAPPER_MAX)
+			{
+				if(port_id != SSDK_PHYSICAL_PORT5)
+				{
+					SSDK_ERROR("when the port_interface_mode of port %d is %d, "
+						"mode0:%d cannot be supported\n",
+						port_id, port_interface_mode[dev_id][port_id],
+						*mode0);
+					return SW_NOT_SUPPORTED;
+				}
+				else
+				{
+					return SW_OK;
+				}
+			}
+			switch(port_id)
+			{
+				case SSDK_PHYSICAL_PORT1:
+					if(port_interface_mode[dev_id][port_id] == PORT_SGMII_FIBER)
+					{
+						*mode0 = PORT_WRAPPER_SGMII_FIBER;
+					}
+					else
+					{
+						*mode0 = PORT_WRAPPER_SGMII_CHANNEL0;
+					}
+					break;
+				case SSDK_PHYSICAL_PORT2:
+					*mode0 = PORT_WRAPPER_SGMII_CHANNEL1;
+					break;
+#ifdef CPPE
+				case SSDK_PHYSICAL_PORT4:
+					if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
+					{
+						*mode0 = PORT_WRAPPER_SGMII_CHANNEL0;
+					}
+					break;
+#endif
+				case SSDK_PHYSICAL_PORT5:
+					if(ssdk_dt_global_get_mac_mode(dev_id,
+						SSDK_UNIPHY_INSTANCE1) == PORT_WRAPPER_MAX)
+					{
+						*mode0 = PORT_WRAPPER_SGMII_CHANNEL4;
+					}
+					break;
+				default:
+					SSDK_ERROR("port %d doesn't support "
+						"port_interface_mode %d\n",
+						port_id, port_interface_mode[dev_id][port_id]);
+					return SW_NOT_SUPPORTED;
+			}
+		}
+		if(port_id != SSDK_PHYSICAL_PORT5 &&
+				(port_interface_mode[dev_id][port_id] == PORT_SGMII_PLUS ||
+				 port_interface_mode[dev_id][port_id] ==PORT_USXGMII ||
+				 port_interface_mode[dev_id][port_id] == PORT_10GBASE_R))
+		{
+#ifdef CPPE
+			if(port_interface_mode[dev_id][port_id] == PORT_SGMII_PLUS
+				&& adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION
+				&& port_id == SSDK_PHYSICAL_PORT4)
+			{
+				*mode0 = PORT_WRAPPER_SGMII_PLUS;
+				continue;
+			}
+#endif
+			SSDK_ERROR("port %d doesn't support port_interface_mode %d\n",
+				port_id, port_interface_mode[dev_id][port_id]);
+			return SW_NOT_SUPPORTED;
+		}
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+_adpt_hppe_instance1_mode_get(a_uint32_t dev_id, a_uint32_t port_id,  a_uint32_t *mode)
+{
+	if ((A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) ||
+		A_TRUE == hsl_port_prop_check (dev_id, port_id, HSL_PP_INNER))
+	{
+		return SW_OK;
+	}
+	SSDK_DEBUG("port_id:%x: %x\n", port_id, port_interface_mode[dev_id][port_id]);
+	switch(port_interface_mode[dev_id][port_id])
+	{
+		case PHY_SGMII_BASET:
+			*mode = PORT_WRAPPER_SGMII_CHANNEL0;
+			break;
+		case PORT_SGMII_PLUS:
+			*mode = PORT_WRAPPER_SGMII_PLUS;
+			break;
+		case PORT_USXGMII:
+			*mode = PORT_WRAPPER_USXGMII;
+			break;
+		case PORT_10GBASE_R:
+			*mode = PORT_WRAPPER_10GBASE_R;
+			break;
+		case PORT_SGMII_FIBER:
+			*mode = PORT_WRAPPER_SGMII_FIBER;
+			break;
+		case PHY_PSGMII_BASET:
+		case PHY_PSGMII_FIBER:
+			if(port_id == SSDK_PHYSICAL_PORT6)
+			{
+				SSDK_ERROR("port %d doesn't support port_interface_mode %d\n",
+					port_id, port_interface_mode[dev_id][port_id]);
+				return SW_NOT_SUPPORTED;
+			}
+			*mode = PORT_INTERFACE_MODE_MAX;
+			break;
+		case PORT_INTERFACE_MODE_MAX:
+			break;
+		default:
+			SSDK_ERROR("port %d doesn't support port_interface_mode %d\n",
+				port_id, port_interface_mode[dev_id][port_id]);
+			return SW_NOT_SUPPORTED;
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+_adpt_hppe_instance_mode_get(a_uint32_t dev_id, a_uint32_t uniphy_index,
+	a_uint32_t *interface_mode)
+{
+	sw_error_t rv = SW_OK;
+
+	switch(uniphy_index)
+	{
+		case SSDK_UNIPHY_INSTANCE0:
+			rv = _adpt_hppe_instance0_mode_get(dev_id, interface_mode);
+			SW_RTN_ON_ERROR(rv);
+			break;
+		case SSDK_UNIPHY_INSTANCE1:
+			rv =_adpt_hppe_instance1_mode_get(dev_id, SSDK_PHYSICAL_PORT5,
+				interface_mode);
+			SW_RTN_ON_ERROR(rv);
+			break;
+		case SSDK_UNIPHY_INSTANCE2:
+			rv =_adpt_hppe_instance1_mode_get(dev_id, SSDK_PHYSICAL_PORT6,
+				interface_mode);
+			SW_RTN_ON_ERROR(rv);
+			break;
+		default:
+			return SW_NOT_SUPPORTED;
+	}
+
+	return rv;
+}
+
+extern sw_error_t
+adpt_hppe_uniphy_mode_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode);
+
+static sw_error_t
+_adpt_hppe_port_interface_mode_phy_config(a_uint32_t dev_id, a_uint32_t port_id,
+	fal_port_interface_mode_t mode)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		SSDK_ERROR("port %d is not in bitmap\n", port_id);
+		return SW_BAD_PARAM;
+	}
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_interface_mode_set)
+	{
+		SSDK_ERROR("the phy_interface_mode_set api is null for port %d\n",
+			port_id);
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+	SSDK_DEBUG("port_id:%d, phy_id:%d, mode:%d\n", port_id, phy_id, mode);
+	rv = phy_drv->phy_interface_mode_set (dev_id, phy_id,mode);
+
+	return rv;
+}
+
+static sw_error_t _adpt_hppe_port_mac_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+
+	rv = adpt_hppe_port_txmac_status_set(dev_id, port_id, enable);
+	SW_RTN_ON_ERROR(rv);
+	rv = adpt_hppe_port_rxmac_status_set(dev_id, port_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_hppe_port_phyaddr_update(a_uint32_t dev_id, a_uint32_t port_id,
+	a_uint32_t mode)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t phy_addr = 0, mode0 = PORT_WRAPPER_MAX;
+	ssdk_port_phyinfo *port_phyinfo = NULL;
+
+	if(port_id != SSDK_PHYSICAL_PORT5)
+	{
+		return rv;
+	}
+	if(mode == PORT_WRAPPER_10GBASE_R)
+	{
+		port_phyinfo = ssdk_port_phyinfo_get(dev_id, port_id);
+		if (!port_phyinfo)
+		{
+			SSDK_ERROR("port_phyinfo of port%d is null\n", port_id);
+			return SW_FAIL;
+		}
+		phy_addr = port_phyinfo->phy_addr;
+		qca_ssdk_phy_address_set(dev_id, port_id, phy_addr);
+		hsl_port_phy_access_type_set(dev_id, port_id, PHY_I2C_ACCESS);
+		SSDK_DEBUG("port %x phy_addr is %x\n", port_id, phy_addr);
+	}
+	else
+	{
+		mode0 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0);
+		if((mode0 == PORT_WRAPPER_PSGMII || mode0 == PORT_WRAPPER_PSGMII_FIBER) &&
+			mode == PORT_WRAPPER_MAX)
+		{
+			rv = hsl_port_prop_get_phyid (dev_id, SSDK_PHYSICAL_PORT4, &phy_addr);
+			SW_RTN_ON_ERROR (rv);
+			phy_addr++;
+			qca_ssdk_phy_address_set(dev_id, port_id, phy_addr);
+			hsl_port_phy_access_type_set(dev_id, port_id, PHY_MDIO_ACCESS);
+			SSDK_DEBUG("port %x phy_addr is %x\n", port_id, phy_addr);
+		}
+	}
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_hppe_sfp_copper_phydriver_switch(a_uint32_t dev_id, a_uint32_t port_id,
+	a_uint32_t mode)
+{
+	sw_error_t rv = SW_OK;
+
+	rv = _adpt_hppe_port_phyaddr_update(dev_id, port_id, mode);
+	SW_RTN_ON_ERROR(rv);
+	rv = hsl_phydriver_update(dev_id, port_id, mode);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_hppe_port_phy_config(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode)
+{
+	sw_error_t rv = SW_OK;
+
+	switch(mode)
+	{
+		case PORT_WRAPPER_PSGMII:
+			/*interface mode changed form psgmii+usxgmii to psgmii+10gbase-r+usxgmii, cannot
+			use port 5 to configure malibu*/
+			rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
+				SSDK_PHYSICAL_PORT4, PHY_PSGMII_BASET);
+			break;
+		case PORT_WRAPPER_PSGMII_FIBER:
+			rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
+				SSDK_PHYSICAL_PORT4, PHY_PSGMII_FIBER);
+			break;
+		case PORT_WRAPPER_SGMII_CHANNEL4:
+			rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
+				SSDK_PHYSICAL_PORT5, PHY_SGMII_BASET);
+			break;
+		case PORT_WRAPPER_QSGMII:
+			rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
+				SSDK_PHYSICAL_PORT4, PORT_QSGMII);
+			break;
+		case PORT_WRAPPER_SGMII_CHANNEL0:
+#ifdef CPPE
+			if(index == SSDK_UNIPHY_INSTANCE0 &&
+				adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION &&
+				(hsl_port_prop_check (dev_id, SSDK_PHYSICAL_PORT4,
+					HSL_PP_EXCL_CPU)))
+			{
+					rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
+						SSDK_PHYSICAL_PORT4, PHY_SGMII_BASET);
+			}
+#endif
+			if(index == SSDK_UNIPHY_INSTANCE1)
+			{
+				rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
+					SSDK_PHYSICAL_PORT5, PHY_SGMII_BASET);
+			}
+			if(index == SSDK_UNIPHY_INSTANCE2)
+			{
+				rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
+					SSDK_PHYSICAL_PORT6, PHY_SGMII_BASET);
+			}
+			break;
+		case PORT_WRAPPER_USXGMII:
+			if(index == SSDK_UNIPHY_INSTANCE1)
+			{
+				rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
+					SSDK_PHYSICAL_PORT5, PORT_USXGMII);
+			}
+			if(index == SSDK_UNIPHY_INSTANCE2)
+			{
+				rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
+					SSDK_PHYSICAL_PORT6, PORT_USXGMII);
+			}
+			break;
+		case PORT_WRAPPER_SGMII_PLUS:
+#ifdef CPPE
+			if(index == SSDK_UNIPHY_INSTANCE0 &&
+				adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
+			{
+				rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
+					SSDK_PHYSICAL_PORT4, PORT_SGMII_PLUS);
+			}
+#endif
+			if(index == SSDK_UNIPHY_INSTANCE1)
+			{
+				rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
+					SSDK_PHYSICAL_PORT5, PORT_SGMII_PLUS);
+			}
+			if(index == SSDK_UNIPHY_INSTANCE2)
+			{
+				rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
+					SSDK_PHYSICAL_PORT6, PORT_SGMII_PLUS);
+			}
+			break;
+		default:
+			break;
+	}
+
+	return rv;
+}
+
+static sw_error_t
+adpt_hppe_port_mac_uniphy_phy_config(a_uint32_t dev_id, a_uint32_t mode_index,
+	a_uint32_t mode[], a_bool_t force_switch)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_id = 0, port_id_from = 0, port_id_end = 0;
+
+	if(mode_index == SSDK_UNIPHY_INSTANCE0)
+	{
+		switch (mode[SSDK_UNIPHY_INSTANCE0])
+		{
+			case PORT_WRAPPER_PSGMII:
+			case PORT_WRAPPER_PSGMII_FIBER:
+				port_id_from = SSDK_PHYSICAL_PORT1;
+				/*qsgmii+10gbase-r+usxgmii --> psgmii+10gbase-r+usxgmii*/
+				if(mode[SSDK_UNIPHY_INSTANCE1] != PORT_WRAPPER_MAX)
+				{
+					port_id_end = SSDK_PHYSICAL_PORT4;
+				}
+				else
+				{
+					port_id_end = SSDK_PHYSICAL_PORT5;
+				}
+				break;
+			case PORT_WRAPPER_QSGMII:
+				port_id_from = SSDK_PHYSICAL_PORT1;
+				port_id_end = SSDK_PHYSICAL_PORT4;
+				break;
+			case PORT_WRAPPER_SGMII0_RGMII4:
+			case PORT_WRAPPER_SGMII_CHANNEL0:
+			case PORT_WRAPPER_SGMII_FIBER:
+#ifdef CPPE
+			case PORT_WRAPPER_SGMII_PLUS:
+				if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
+				{
+					a_uint32_t mode_tmp = 0;
+					mode_tmp = mode[SSDK_UNIPHY_INSTANCE0];
+					if (mode_tmp == PORT_WRAPPER_SGMII_PLUS ||
+						((mode_tmp == PORT_WRAPPER_SGMII0_RGMII4 ||
+						mode_tmp == PORT_WRAPPER_SGMII_CHANNEL0) &&
+						(hsl_port_prop_check (dev_id, SSDK_PHYSICAL_PORT4,
+							HSL_PP_EXCL_CPU))))
+					{
+						port_id_from = SSDK_PHYSICAL_PORT4;
+						port_id_end = SSDK_PHYSICAL_PORT4;
+						break;
+					}
+				}
+#endif
+				port_id_from = SSDK_PHYSICAL_PORT1;
+				port_id_end = SSDK_PHYSICAL_PORT1;
+				break;
+			case PORT_WRAPPER_SGMII1_RGMII4:
+			case PORT_WRAPPER_SGMII_CHANNEL1:
+				port_id_from = SSDK_PHYSICAL_PORT2;
+				port_id_end = SSDK_PHYSICAL_PORT2;
+				break;
+			case PORT_WRAPPER_SGMII4_RGMII4:
+			case PORT_WRAPPER_SGMII_CHANNEL4:
+				port_id_from = SSDK_PHYSICAL_PORT5;
+				port_id_end = SSDK_PHYSICAL_PORT5;
+				break;
+			default:
+				SSDK_INFO ("uniphy %d interface mode is 0x%x\n",
+					mode_index, mode[SSDK_UNIPHY_INSTANCE0]);
+				return SW_OK;
+		}
+	}
+	else if(mode_index == SSDK_UNIPHY_INSTANCE1)
+	{
+		port_id_from = SSDK_PHYSICAL_PORT5;
+		port_id_end = SSDK_PHYSICAL_PORT5;
+	}
+	else if(mode_index == SSDK_UNIPHY_INSTANCE2)
+	{
+		port_id_from = SSDK_PHYSICAL_PORT6;
+		port_id_end = SSDK_PHYSICAL_PORT6;
+	}
+	else
+	{
+		return SW_NOT_SUPPORTED;
+	}
+	/*disable mac tx and rx for special ports*/
+	for(port_id = port_id_from; port_id <= port_id_end; port_id++)
+	{
+		rv = _adpt_hppe_port_mac_set(dev_id, port_id, A_FALSE);
+	}
+
+	/*configure the uniphy*/
+	rv = adpt_hppe_uniphy_mode_set(dev_id, mode_index, mode[mode_index]);
+	SSDK_DEBUG("configure uniphy mode_index:%x, mode:%x, rv:%x\n",
+		mode_index, mode[mode_index], rv);
+	SW_RTN_ON_ERROR(rv);
+
+	/*configure the mac*/
+	for(port_id = port_id_from; port_id <= port_id_end; port_id++)
+	{
+		rv = adpt_hppe_port_mux_mac_type_set(dev_id, port_id, mode[SSDK_UNIPHY_INSTANCE0],
+			mode[SSDK_UNIPHY_INSTANCE1], mode[SSDK_UNIPHY_INSTANCE2]);
+		SSDK_DEBUG("configure mac, port_id is %x,mode0:%x,mode1:%x,mode2:%x, rv:%x\n",
+			port_id, mode[SSDK_UNIPHY_INSTANCE0], mode[SSDK_UNIPHY_INSTANCE1],
+			mode[SSDK_UNIPHY_INSTANCE2], rv);
+		SW_RTN_ON_ERROR(rv);
+	}
+
+	/*configure the phy*/
+	if(SSDK_PHYSICAL_PORT5 >= port_id_from && SSDK_PHYSICAL_PORT5 <= port_id_end)
+	{
+		rv = _adpt_hppe_sfp_copper_phydriver_switch(dev_id, SSDK_PHYSICAL_PORT5,
+			mode[SSDK_UNIPHY_INSTANCE1]);
+	}
+	SW_RTN_ON_ERROR(rv);
+	if (force_switch != A_FALSE) {
+		rv = _adpt_hppe_port_phy_config(dev_id, mode_index, mode[mode_index]);
+		SSDK_DEBUG("configure phy, mode_index:%x,interface_mode:%x, rv:%x\n",
+			mode_index, mode[mode_index], rv);
+	}
+
+	/*init port status for special ports to triger polling*/
+	for(port_id = port_id_from; port_id <= port_id_end; port_id++)
+	{
+		adpt_hppe_port_txfc_status_set(dev_id, port_id, A_FALSE);
+		adpt_hppe_port_rxfc_status_set(dev_id, port_id, A_FALSE);
+		qca_mac_port_status_init(dev_id, port_id);
+	}
+
+	return rv;
+}
+
+sw_error_t
+_adpt_hppe_port_interface_mode_apply(a_uint32_t dev_id, a_bool_t force_switch)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t mode_index = 0, mode_old[3] = {0};
+	a_uint32_t mode_new[3] = {PORT_WRAPPER_MAX,PORT_WRAPPER_MAX,PORT_WRAPPER_MAX};
+
+	/*get three intances mode, include old mode and new mode*/
+	for(mode_index = SSDK_UNIPHY_INSTANCE0; mode_index <= SSDK_UNIPHY_INSTANCE2; mode_index++)
+	{
+		mode_old[mode_index] = ssdk_dt_global_get_mac_mode(dev_id, mode_index);
+		if(mode_index == SSDK_UNIPHY_INSTANCE1 &&
+			mode_new[SSDK_UNIPHY_INSTANCE0] == PORT_WRAPPER_SGMII_CHANNEL4)
+		{
+			mode_new[SSDK_UNIPHY_INSTANCE1] = PORT_WRAPPER_MAX;
+		}
+		else
+		{
+			rv = _adpt_hppe_instance_mode_get(dev_id, mode_index, &mode_new[mode_index]);
+			SW_RTN_ON_ERROR(rv);
+		}
+	}
+	SSDK_DEBUG("mode0_old: %x, mode1_old:%x, mode2_old:%x\n",
+			mode_old[0], mode_old[1], mode_old[2]);
+	SSDK_DEBUG("mode0_new: %x, mode1_new:%x, mode2_new:%x\n",
+			mode_new[0], mode_new[1], mode_new[2]);
+	/*set three new intances mode*/
+	for(mode_index = SSDK_UNIPHY_INSTANCE0; mode_index <= SSDK_UNIPHY_INSTANCE2; mode_index++)
+	{
+		ssdk_dt_global_set_mac_mode(dev_id, mode_index, mode_new[mode_index]);
+	}
+
+	for (mode_index = SSDK_UNIPHY_INSTANCE0; mode_index <= SSDK_UNIPHY_INSTANCE2; mode_index++)
+	{
+		ssdk_gcc_uniphy_sys_set(dev_id, mode_index, A_TRUE);
+	}
+	ssdk_uniphy_port5_clock_source_set();
+
+	/*configure the mode according to mode_new*/
+	for(mode_index = SSDK_UNIPHY_INSTANCE0; mode_index <= SSDK_UNIPHY_INSTANCE2; mode_index++)
+	{
+		if(mode_new[mode_index] != mode_old[mode_index])
+		{
+			SSDK_DEBUG("need to configure instance%x\n", mode_index);
+			rv = adpt_hppe_port_mac_uniphy_phy_config(dev_id,
+				mode_index, mode_new, force_switch);
+			if(rv)
+			{
+				SSDK_ERROR("config instance%x, rv:%x faild\n", mode_index,rv);
+				return rv;
+			}
+		}
+		if (mode_new[mode_index] == PORT_WRAPPER_MAX) {
+			ssdk_gcc_uniphy_sys_set(dev_id, mode_index, A_FALSE);
+		}
+	}
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_hppe_port_interface_mode_apply(a_uint32_t dev_id)
+{
+	struct qca_phy_priv *priv;
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	priv = ssdk_phy_priv_data_get(dev_id);
+	if (!priv)
+	{
+		return SW_FAIL;
+	}
+
+	mutex_lock(&priv->mac_sw_sync_lock);
+	rv = _adpt_hppe_port_interface_mode_apply(dev_id, A_TRUE);
+	mutex_unlock(&priv->mac_sw_sync_lock);
+
+	qca_mac_sw_sync_work_resume(priv);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_mac_type = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == PORT_XGMAC_TYPE)
+		rv = _adpt_hppe_port_xgmac_loopback_get( dev_id, port_id, enable);
+	else if (port_mac_type == PORT_GMAC_TYPE)
+		rv = _adpt_hppe_port_gmac_loopback_get( dev_id, port_id, enable);
+	else
+		return SW_BAD_VALUE;
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_hibernation_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_hibernation_get (dev_id, phy_id, enable);
+
+	return rv;
+
+}
+#endif
+sw_error_t
+adpt_hppe_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+				     a_uint32_t autoadv)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_autoneg_adv_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_autoneg_adv_set (dev_id, phy_id, autoadv);
+	SW_RTN_ON_ERROR (rv);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0))
+	rv = hsl_port_phydev_adv_update (dev_id, port_id, autoadv);
+	SW_RTN_ON_ERROR (rv);
+#endif
+
+	return SW_OK;
+
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_hppe_port_remote_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
+					 a_bool_t * enable)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_remote_loopback_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_remote_loopback_get (dev_id, phy_id, enable);
+
+	return rv;
+
+}
+
+sw_error_t
+adpt_hppe_port_counter_show(a_uint32_t dev_id, fal_port_t port_id,
+				 fal_port_counter_info_t * counter_info)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(counter_info);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_counter_show)
+	  return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_counter_show (dev_id, phy_id,counter_info);
+
+	return rv;
+
+}
+sw_error_t
+adpt_hppe_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl)
+{
+	sw_error_t rv = SW_OK;
+	union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;
+
+	memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	rv = hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	ctrl->mtu_size = mru_mtu_ctrl_tbl.bf.mtu;
+	ctrl->action = (fal_fwd_cmd_t)mru_mtu_ctrl_tbl.bf.mtu_cmd;
+
+	return SW_OK;
+}
+
+#endif
+sw_error_t
+adpt_hppe_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_autoneg_enable_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_autoneg_enable_set (dev_id, phy_id);
+	return rv;
+
+}
+
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_ppe_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl)
+{
+	a_uint32_t chip_ver = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_port_mtu_get(dev_id, port_id, ctrl);
+#endif
+	} else {
+		return adpt_hppe_port_mtu_get(dev_id, port_id, ctrl);
+	}
+
+	return SW_NOT_SUPPORTED;
+}
+#endif
+
+sw_error_t
+adpt_hppe_port_interface_mode_status_get(a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t * mode)
+{
+
+	sw_error_t rv = SW_OK;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mode);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+
+	/* for those ports without PHY device should be sfp port */
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) {
+		rv = sfp_phy_interface_get_mode_status(dev_id, port_id, mode);
+		SW_RTN_ON_ERROR (rv);
+	} else {
+		SW_RTN_ON_NULL(phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+		if (NULL == phy_drv->phy_interface_mode_status_get)
+			return SW_NOT_SUPPORTED;
+
+		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR (rv);
+
+		rv = phy_drv->phy_interface_mode_status_get (dev_id, phy_id,mode);
+	}
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_hppe_port_reset(a_uint32_t dev_id, fal_port_t port_id)
+{
+
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_reset)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_reset(dev_id, phy_id);
+
+	return rv;
+
+}
+#endif
+
+sw_error_t
+adpt_hppe_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id);
+
+	if (!priv)
+		return SW_FAIL;
+
+	if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6))
+		return SW_BAD_VALUE;
+#if defined(CPPE)
+	if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) &&
+		(port_id == SSDK_PHYSICAL_PORT6)) {
+		return adpt_cppe_switch_port_loopback_flowctrl_set(dev_id,
+				port_id, enable);
+	}
+#endif
+	rv = adpt_hppe_port_txfc_status_set(dev_id, port_id, enable);
+	rv |= adpt_hppe_port_rxfc_status_set(dev_id, port_id, enable);
+
+	if(rv != SW_OK)
+		return rv;
+
+	priv->port_old_tx_flowctrl[port_id - 1] = enable;
+	priv->port_old_rx_flowctrl[port_id - 1] = enable;
+
+	return SW_OK;
+}
+sw_error_t
+adpt_hppe_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+			       fal_port_speed_t * pspeed)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+	struct port_phy_status phy_status = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(pspeed);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	/* for those ports without PHY device should be sfp port */
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+	{
+		if (port_id == SSDK_PHYSICAL_PORT0)
+			*pspeed = FAL_SPEED_10000;
+		else {
+			rv = _adpt_phy_status_get_from_ppe(dev_id,
+				port_id, &phy_status);
+			SW_RTN_ON_ERROR (rv);
+			*pspeed= phy_status.speed;
+		}
+	}
+	else
+	{
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+		if (NULL == phy_drv->phy_speed_get)
+			return SW_NOT_SUPPORTED;
+
+		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR (rv);
+		rv = phy_drv->phy_speed_get (dev_id, phy_id, pspeed);
+		SW_RTN_ON_ERROR (rv);
+	}
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+adpt_hppe_port_mdix_set(a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_mdix_mode_t mode)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	  {
+		return SW_BAD_PARAM;
+	  }
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_mdix_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_mdix_set (dev_id, phy_id, mode);
+
+	return rv;
+
+}
+sw_error_t
+adpt_hppe_port_wol_status_get(a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * enable)
+{
+
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_wol_status_get)
+	  return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_wol_status_get (dev_id, phy_id, enable);
+
+	return rv;
+
+}
+
+sw_error_t
+adpt_hppe_port_source_filter_get(a_uint32_t dev_id,
+				fal_port_t port_id, a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+	union port_in_forward_u port_in_forward = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_port_in_forward_get(dev_id, port_id, &port_in_forward);
+
+	if (rv != SW_OK)
+		return rv;
+
+	if (port_in_forward.bf.source_filtering_bypass == A_TRUE)
+		*enable = A_FALSE;
+	else
+		*enable = A_TRUE;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_source_filter_set(a_uint32_t dev_id,
+				fal_port_t port_id, a_bool_t enable)
+{
+	union port_in_forward_u port_in_forward = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (enable == A_TRUE)
+		port_in_forward.bf.source_filtering_bypass = A_FALSE;
+	else
+		port_in_forward.bf.source_filtering_bypass = A_TRUE;
+
+	return hppe_port_in_forward_set(dev_id, port_id, &port_in_forward);
+}
+
+sw_error_t
+adpt_ppe_port_source_filter_get(a_uint32_t dev_id,
+				fal_port_t port_id, a_bool_t * enable)
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+#ifdef CPPE
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+		return adpt_cppe_port_source_filter_get(dev_id, port_id, enable);
+	}
+#endif
+	return adpt_hppe_port_source_filter_get(dev_id, port_id, enable);
+}
+
+sw_error_t
+adpt_ppe_port_source_filter_set(a_uint32_t dev_id,
+				fal_port_t port_id, a_bool_t enable)
+
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+#ifdef CPPE
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+		return adpt_cppe_port_source_filter_set(dev_id, port_id, enable);
+	}
+#endif
+	return adpt_hppe_port_source_filter_set(dev_id, port_id, enable);
+}
+
+sw_error_t
+adpt_ppe_port_source_filter_config_get(a_uint32_t dev_id,
+				fal_port_t port_id, fal_src_filter_config_t* src_filter_config)
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+#ifdef CPPE
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+		return adpt_cppe_port_source_filter_config_get(dev_id, port_id,
+				src_filter_config);
+	}
+#endif
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+adpt_ppe_port_source_filter_config_set(a_uint32_t dev_id,
+				fal_port_t port_id, fal_src_filter_config_t *src_filter_config)
+
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+#ifdef CPPE
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+		return adpt_cppe_port_source_filter_config_set(dev_id, port_id, src_filter_config);
+	}
+#endif
+	return SW_NOT_SUPPORTED;
+}
+
+static sw_error_t
+adpt_hppe_port_interface_3az_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = 0;
+	union lpi_enable_u lpi_enable = {0};
+	union lpi_port_timer_u lpi_port_timer = {0};
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL(phy_drv = hsl_phy_api_ops_get(dev_id, port_id));
+	if (NULL == phy_drv->phy_8023az_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_8023az_set(dev_id, phy_id, enable);
+	SW_RTN_ON_ERROR (rv);
+
+	hppe_lpi_enable_get(dev_id, port_id, &lpi_enable);
+
+	lpi_enable.val &= ~(0x1 << (port_id - 1));
+	lpi_enable.val |= (((a_uint32_t)enable) << (port_id - 1));
+	hppe_lpi_enable_set(dev_id, port_id, &lpi_enable);
+
+	lpi_port_timer.bf.lpi_port_wakeup_timer = LPI_WAKEUP_TIMER;
+	lpi_port_timer.bf.lpi_port_sleep_timer = LPI_SLEEP_TIMER;
+	hppe_lpi_timer_set(dev_id, port_id, &lpi_port_timer);
+
+	return SW_OK;
+}
+static sw_error_t
+adpt_hppe_port_interface_3az_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+	sw_error_t rv = 0;
+	union lpi_enable_u lpi_enable = {0};
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+	a_bool_t phy_status = 0, mac_status = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
+		return SW_NOT_SUPPORTED;
+
+	SW_RTN_ON_NULL (phy_drv =hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_8023az_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_8023az_get(dev_id, phy_id, &phy_status);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = hppe_lpi_enable_get(dev_id, port_id, &lpi_enable);
+
+	if(((lpi_enable.val >> (port_id - 1)) & 0x1) == A_TRUE)
+		mac_status = A_TRUE;
+	else
+		mac_status = A_FALSE;
+
+	*enable = (phy_status & mac_status);
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_promisc_mode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	union port_bridge_ctrl_u port_bridge_ctrl = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*enable = port_bridge_ctrl.bf.promisc_en;
+
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+adpt_hppe_port_promisc_mode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union port_bridge_ctrl_u port_bridge_ctrl = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	port_bridge_ctrl.bf.promisc_en = enable;
+
+	return hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl);
+}
+
+static sw_error_t
+adpt_hppe_port_bridge_txmac_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union port_bridge_ctrl_u port_bridge_ctrl = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	if(enable == A_TRUE)
+		port_bridge_ctrl.bf.txmac_en= 1;
+	else
+		port_bridge_ctrl.bf.txmac_en= 0;
+
+	return hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl);
+}
+
+sw_error_t
+adpt_hppe_port_mux_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t port_type)
+{
+	sw_error_t rv = SW_OK;
+	union port_mux_ctrl_u port_mux_ctrl;
+	a_uint32_t mode, mode1;
+
+	memset(&port_mux_ctrl, 0, sizeof(port_mux_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_port_mux_ctrl_get(dev_id, &port_mux_ctrl);
+	port_mux_ctrl.bf.port4_pcs_sel = 1;
+
+	if (port_id == HPPE_MUX_PORT1)
+	{
+		if (port_type == PORT_GMAC_TYPE)
+		{
+			mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0);
+			mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1);
+			if ((((mode == PORT_WRAPPER_PSGMII) ||
+			      (mode == PORT_WRAPPER_PSGMII_FIBER)) &&
+			     (mode1 == PORT_WRAPPER_MAX)) ||
+			    ((mode == PORT_WRAPPER_SGMII4_RGMII4) && (mode1 == PORT_WRAPPER_MAX)))
+			{
+				port_mux_ctrl.bf.port5_pcs_sel = 1;
+				port_mux_ctrl.bf.port5_gmac_sel = 1;
+			}
+			else if (mode1 == PORT_WRAPPER_SGMII0_RGMII4 ||
+					mode1 == PORT_WRAPPER_SGMII_CHANNEL0 ||
+					mode1 == PORT_WRAPPER_SGMII_FIBER)
+			{
+				port_mux_ctrl.bf.port5_pcs_sel = 2;
+				port_mux_ctrl.bf.port5_gmac_sel = 1;
+			}
+		}
+		else if (port_type == PORT_XGMAC_TYPE)
+		{
+			port_mux_ctrl.bf.port5_pcs_sel = 2;
+			port_mux_ctrl.bf.port5_gmac_sel = 0;
+		}
+	}
+	else if (port_id == HPPE_MUX_PORT2)
+	{
+		if (port_type == PORT_GMAC_TYPE)
+		{
+			port_mux_ctrl.bf.port6_pcs_sel = 1;
+			port_mux_ctrl.bf.port6_gmac_sel = 1;
+		}
+		else if (port_type == PORT_XGMAC_TYPE)
+		{
+			port_mux_ctrl.bf.port6_pcs_sel = 1;
+			port_mux_ctrl.bf.port6_gmac_sel = 0;
+		}
+	}
+	else
+	{
+		return SW_OK;
+	}
+	rv = hppe_port_mux_ctrl_set(dev_id, &port_mux_ctrl);
+
+	return rv;
+}
+
+static sw_error_t
+adpt_hppe_port_flowctrl_forcemode_set(a_uint32_t dev_id,
+		fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id);
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (!priv)
+		return SW_FAIL;
+
+	if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6))
+		return SW_BAD_VALUE;
+
+	priv->port_tx_flowctrl_forcemode[port_id - 1] = enable;
+	priv->port_rx_flowctrl_forcemode[port_id - 1] = enable;
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+adpt_hppe_port_flowctrl_forcemode_get(a_uint32_t dev_id,
+		fal_port_t port_id, a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id);
+
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6))
+		return SW_BAD_VALUE;
+
+	if (!priv)
+		return SW_FAIL;
+
+	*enable = (priv->port_tx_flowctrl_forcemode[port_id - 1] &
+		priv->port_rx_flowctrl_forcemode[port_id - 1]);
+
+	return rv;
+}
+#endif
+static a_uint32_t port_lpi_sleep_timer[SW_MAX_NR_DEV][SSDK_PHYSICAL_PORT6] = {
+	{218, 218, 218, 218, 218, 218},
+	{218, 218, 218, 218, 218, 218},
+	{218, 218, 218, 218, 218, 218},
+}; /* unit is us*/
+static a_uint32_t port_lpi_wakeup_timer[SW_MAX_NR_DEV][SSDK_PHYSICAL_PORT6] = {
+	{27, 27, 27, 27, 27, 27},
+	{27, 27, 27, 27, 27, 27},
+	{27, 27, 27, 27, 27, 27},
+}; /* unit is us*/
+static sw_error_t
+adpt_hppe_port_interface_eee_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
+	fal_port_eee_cfg_t *port_eee_cfg)
+{
+	sw_error_t rv = 0;
+	union lpi_enable_u lpi_enable = {0};
+	union lpi_port_timer_u lpi_port_timer = {0};
+	a_uint32_t phy_id = 0;
+	a_uint32_t adv, enable;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6)) {
+		return SW_BAD_PARAM;
+	}
+	if (port_eee_cfg->enable) {
+		adv = port_eee_cfg->advertisement;
+	} else {
+		adv = 0;
+	}
+	if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) {
+		return SW_BAD_PARAM;
+	}
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) {
+		return SW_NOT_SUPPORTED;
+	}
+
+	SW_RTN_ON_NULL(phy_drv = hsl_phy_api_ops_get(dev_id, port_id));
+	if (NULL == phy_drv->phy_eee_adv_set) {
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_eee_adv_set(dev_id, phy_id, adv);
+	SW_RTN_ON_ERROR (rv);
+
+	hppe_lpi_enable_get(dev_id, port_id, &lpi_enable);
+
+	enable = port_eee_cfg->lpi_tx_enable;
+	lpi_enable.val &= ~(0x1 << (port_id - 1));
+	lpi_enable.val |= (enable << (port_id - 1));
+	hppe_lpi_enable_set(dev_id, port_id, &lpi_enable);
+
+	lpi_port_timer.bf.lpi_port_wakeup_timer =
+		(port_eee_cfg->lpi_wakeup_timer * LPI_EEE_TIMER_FREQUENCY) /LPI_EEE_TIMER_UNIT;
+	lpi_port_timer.bf.lpi_port_sleep_timer =
+		(port_eee_cfg->lpi_sleep_timer * LPI_EEE_TIMER_FREQUENCY) /LPI_EEE_TIMER_UNIT;
+	rv = hppe_lpi_timer_set(dev_id, port_id, &lpi_port_timer);
+	SW_RTN_ON_ERROR (rv);
+	port_lpi_wakeup_timer[dev_id][port_id - 1] = port_eee_cfg->lpi_wakeup_timer;
+	port_lpi_sleep_timer[dev_id][port_id - 1] = port_eee_cfg->lpi_sleep_timer;
+
+	return rv;
+}
+static sw_error_t
+adpt_hppe_port_interface_eee_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
+	fal_port_eee_cfg_t *port_eee_cfg)
+{
+	sw_error_t rv = 0;
+	union lpi_enable_u lpi_enable = {0};
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+	a_uint32_t adv, lp_adv, cap, status;
+
+	if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6)) {
+		return SW_BAD_PARAM;
+	}
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(port_eee_cfg);
+	memset(port_eee_cfg, 0, sizeof(*port_eee_cfg));
+
+	if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) {
+		return SW_BAD_PARAM;
+	}
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) {
+		return SW_NOT_SUPPORTED;
+	}
+
+	SW_RTN_ON_NULL (phy_drv =hsl_phy_api_ops_get (dev_id, port_id));
+	if ((NULL == phy_drv->phy_eee_adv_get) || (NULL == phy_drv->phy_eee_partner_adv_get) ||
+		(NULL == phy_drv->phy_eee_cap_get) || (NULL == phy_drv->phy_eee_status_get)) {
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_eee_adv_get(dev_id, phy_id, &adv);
+	SW_RTN_ON_ERROR (rv);
+	port_eee_cfg->advertisement = adv;
+	rv = phy_drv->phy_eee_partner_adv_get(dev_id, phy_id, &lp_adv);
+	SW_RTN_ON_ERROR (rv);
+	port_eee_cfg->link_partner_advertisement = lp_adv;
+	rv = phy_drv->phy_eee_cap_get(dev_id, phy_id, &cap);
+	SW_RTN_ON_ERROR (rv);
+	port_eee_cfg->capability = cap;
+	rv = phy_drv->phy_eee_status_get(dev_id, phy_id, &status);
+	SW_RTN_ON_ERROR (rv);
+	port_eee_cfg->eee_status = status;
+
+	if (port_eee_cfg->advertisement) {
+		port_eee_cfg->enable = A_TRUE;
+	} else {
+		port_eee_cfg->enable = A_FALSE;
+	}
+	rv = hppe_lpi_enable_get(dev_id, port_id, &lpi_enable);
+	SW_RTN_ON_ERROR (rv);
+
+	if(((lpi_enable.val >> (port_id - 1)) & 0x1) == A_TRUE) {
+		port_eee_cfg->lpi_tx_enable = A_TRUE;
+	} else {
+		port_eee_cfg->lpi_tx_enable = A_FALSE;
+	}
+	port_eee_cfg->lpi_wakeup_timer =  port_lpi_wakeup_timer[dev_id][port_id - 1];
+	port_eee_cfg->lpi_sleep_timer = port_lpi_sleep_timer[dev_id][port_id - 1];
+
+	return rv;
+}
+
+static sw_error_t
+adpt_hppe_port_phy_status_get(a_uint32_t dev_id, a_uint32_t port_id,
+				struct port_phy_status *phy_status)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(phy_status);
+
+	/* for those ports without PHY device should be sfp port or a internal port*/
+	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) {
+		if (port_id != SSDK_PHYSICAL_PORT0) {
+			rv = _adpt_phy_status_get_from_ppe(dev_id,
+				port_id, phy_status);
+			SW_RTN_ON_ERROR (rv);
+		} else {
+			return SW_NOT_SUPPORTED;
+		}
+	} else {
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+		if (NULL == phy_drv->phy_get_status)
+			return SW_NOT_SUPPORTED;
+
+		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR (rv);
+		rv = phy_drv->phy_get_status (dev_id, phy_id, phy_status);
+		SW_RTN_ON_ERROR (rv);
+	}
+
+	return rv;
+
+}
+static void
+adpt_hppe_uniphy_psgmii_port_reset(a_uint32_t dev_id, a_uint32_t uniphy_index,
+			a_uint32_t port_id)
+{
+	union uniphy_channel0_input_output_4_u uniphy_channel0_input_output_4;
+	union uniphy_channel1_input_output_4_u uniphy_channel1_input_output_4;
+	union uniphy_channel2_input_output_4_u uniphy_channel2_input_output_4;
+	union uniphy_channel3_input_output_4_u uniphy_channel3_input_output_4;
+	union uniphy_channel4_input_output_4_u uniphy_channel4_input_output_4;
+
+	memset(&uniphy_channel0_input_output_4, 0, sizeof(uniphy_channel0_input_output_4));
+	memset(&uniphy_channel1_input_output_4, 0, sizeof(uniphy_channel1_input_output_4));
+	memset(&uniphy_channel2_input_output_4, 0, sizeof(uniphy_channel2_input_output_4));
+	memset(&uniphy_channel3_input_output_4, 0, sizeof(uniphy_channel3_input_output_4));
+	memset(&uniphy_channel4_input_output_4, 0, sizeof(uniphy_channel4_input_output_4));
+
+	if (port_id == SSDK_PHYSICAL_PORT1)
+	{
+		hppe_uniphy_channel0_input_output_4_get(dev_id, uniphy_index,
+			&uniphy_channel0_input_output_4);
+		uniphy_channel0_input_output_4.bf.newaddedfromhere_ch0_adp_sw_rstn = 0;
+		hppe_uniphy_channel0_input_output_4_set(dev_id, uniphy_index,
+			&uniphy_channel0_input_output_4);
+		uniphy_channel0_input_output_4.bf.newaddedfromhere_ch0_adp_sw_rstn = 1;
+		hppe_uniphy_channel0_input_output_4_set(dev_id, uniphy_index,
+			&uniphy_channel0_input_output_4);
+	}
+	else if (port_id == SSDK_PHYSICAL_PORT2)
+	{
+		hppe_uniphy_channel1_input_output_4_get(dev_id, uniphy_index,
+			&uniphy_channel1_input_output_4);
+		uniphy_channel1_input_output_4.bf.newaddedfromhere_ch1_adp_sw_rstn = 0;
+		hppe_uniphy_channel1_input_output_4_set(dev_id, uniphy_index,
+			&uniphy_channel1_input_output_4);
+		uniphy_channel1_input_output_4.bf.newaddedfromhere_ch1_adp_sw_rstn = 1;
+		hppe_uniphy_channel1_input_output_4_set(dev_id, uniphy_index,
+			&uniphy_channel1_input_output_4);
+	}
+	else if (port_id == SSDK_PHYSICAL_PORT3)
+	{
+		hppe_uniphy_channel2_input_output_4_get(dev_id, uniphy_index,
+			&uniphy_channel2_input_output_4);
+		uniphy_channel2_input_output_4.bf.newaddedfromhere_ch2_adp_sw_rstn = 0;
+		hppe_uniphy_channel2_input_output_4_set(dev_id, uniphy_index,
+			&uniphy_channel2_input_output_4);
+		uniphy_channel2_input_output_4.bf.newaddedfromhere_ch2_adp_sw_rstn = 1;
+		hppe_uniphy_channel2_input_output_4_set(dev_id, uniphy_index,
+			&uniphy_channel2_input_output_4);
+	}
+	else if (port_id == SSDK_PHYSICAL_PORT4)
+	{
+		hppe_uniphy_channel3_input_output_4_get(dev_id, uniphy_index,
+			&uniphy_channel3_input_output_4);
+		uniphy_channel3_input_output_4.bf.newaddedfromhere_ch3_adp_sw_rstn = 0;
+		hppe_uniphy_channel3_input_output_4_set(dev_id, uniphy_index,
+			&uniphy_channel3_input_output_4);
+		uniphy_channel3_input_output_4.bf.newaddedfromhere_ch3_adp_sw_rstn = 1;
+		hppe_uniphy_channel3_input_output_4_set(dev_id, uniphy_index,
+			&uniphy_channel3_input_output_4);
+	}
+	else if (port_id == SSDK_PHYSICAL_PORT5)
+	{
+		hppe_uniphy_channel4_input_output_4_get(dev_id, uniphy_index,
+			&uniphy_channel4_input_output_4);
+		uniphy_channel4_input_output_4.bf.newaddedfromhere_ch4_adp_sw_rstn = 0;
+		hppe_uniphy_channel4_input_output_4_set(dev_id, uniphy_index,
+			&uniphy_channel4_input_output_4);
+		uniphy_channel4_input_output_4.bf.newaddedfromhere_ch4_adp_sw_rstn = 1;
+		hppe_uniphy_channel4_input_output_4_set(dev_id, uniphy_index,
+			&uniphy_channel4_input_output_4);
+	}
+
+	return;
+}
+static void
+adpt_hppe_uniphy_usxgmii_port_reset(a_uint32_t dev_id, a_uint32_t uniphy_index,
+			a_uint32_t port_id)
+{
+	union vr_xs_pcs_dig_ctrl1_u vr_xs_pcs_dig_ctrl1;
+
+	memset(&vr_xs_pcs_dig_ctrl1, 0, sizeof(vr_xs_pcs_dig_ctrl1));
+
+	hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, uniphy_index, &vr_xs_pcs_dig_ctrl1);
+	vr_xs_pcs_dig_ctrl1.bf.usra_rst = 1;
+	hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, uniphy_index, &vr_xs_pcs_dig_ctrl1);
+
+	return;
+}
+
+static void
+adpt_hppe_uniphy_port_adapter_reset(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	a_uint32_t uniphy_index, mode, mode1;
+#if defined(CPPE)
+	a_uint32_t channel_id = 0;
+#endif
+
+	if (port_id < HPPE_MUX_PORT1)
+	{
+		uniphy_index = SSDK_UNIPHY_INSTANCE0;
+#if defined(CPPE)
+		adpt_cppe_port_to_channel_convert(dev_id, port_id,
+				&channel_id);
+		port_id = channel_id;
+#endif
+		adpt_hppe_uniphy_psgmii_port_reset(dev_id, uniphy_index,
+						port_id);
+	}
+	else
+	{
+		if (port_id == HPPE_MUX_PORT1)
+		{
+			mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0);
+			mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1);
+			if ((((mode == PORT_WRAPPER_PSGMII) ||
+			      (mode == PORT_WRAPPER_PSGMII_FIBER)) &&
+			     (mode1 == PORT_WRAPPER_MAX)) ||
+			    ((mode == PORT_WRAPPER_SGMII4_RGMII4) && (mode1 == PORT_WRAPPER_MAX)))
+			{
+				uniphy_index = SSDK_UNIPHY_INSTANCE0;
+				adpt_hppe_uniphy_psgmii_port_reset(dev_id, uniphy_index,
+						port_id);
+				return;
+			}
+			else
+				uniphy_index = SSDK_UNIPHY_INSTANCE1;
+		}
+		else
+			uniphy_index = SSDK_UNIPHY_INSTANCE2;
+
+		mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index);
+
+		if ((mode == PORT_WRAPPER_SGMII_PLUS) || (mode == PORT_WRAPPER_SGMII0_RGMII4)
+				|| (mode == PORT_WRAPPER_SGMII_CHANNEL0)
+				|| (mode == PORT_WRAPPER_SGMII_FIBER))
+		{
+			/* only reset channel 0 */
+			adpt_hppe_uniphy_psgmii_port_reset(dev_id, uniphy_index, 1);
+		}
+		else if (mode == PORT_WRAPPER_USXGMII)
+		{
+			adpt_hppe_uniphy_usxgmii_port_reset(dev_id, uniphy_index,
+						port_id);
+		}
+	}
+
+	return;
+}
+static void
+adpt_hppe_uniphy_usxgmii_speed_set(a_uint32_t dev_id, a_uint32_t uniphy_index,
+				fal_port_speed_t speed)
+{
+	union sr_mii_ctrl_u sr_mii_ctrl;
+	memset(&sr_mii_ctrl, 0, sizeof(sr_mii_ctrl));
+
+	hppe_sr_mii_ctrl_get(0, uniphy_index, &sr_mii_ctrl);
+	sr_mii_ctrl.bf.duplex_mode = 1;
+	if (speed == FAL_SPEED_10)
+	{
+		sr_mii_ctrl.bf.ss5 = 0;
+		sr_mii_ctrl.bf.ss6 = 0;
+		sr_mii_ctrl.bf.ss13 = 0;
+	}
+	else if (speed == FAL_SPEED_100)
+	{
+		sr_mii_ctrl.bf.ss5 = 0;
+		sr_mii_ctrl.bf.ss6 = 0;
+		sr_mii_ctrl.bf.ss13 = 1;
+	}
+	else if (speed == FAL_SPEED_1000)
+	{
+		sr_mii_ctrl.bf.ss5 = 0;
+		sr_mii_ctrl.bf.ss6 = 1;
+		sr_mii_ctrl.bf.ss13 = 0;
+	}
+	else if (speed == FAL_SPEED_10000)
+	{
+		sr_mii_ctrl.bf.ss5 = 0;
+		sr_mii_ctrl.bf.ss6 = 1;
+		sr_mii_ctrl.bf.ss13 = 1;
+	}
+	else if (speed == FAL_SPEED_2500)
+	{
+		sr_mii_ctrl.bf.ss5 = 1;
+		sr_mii_ctrl.bf.ss6 = 0;
+		sr_mii_ctrl.bf.ss13 = 0;
+	}
+	else if (speed == FAL_SPEED_5000)
+	{
+		sr_mii_ctrl.bf.ss5 = 1;
+		sr_mii_ctrl.bf.ss6 = 0;
+		sr_mii_ctrl.bf.ss13 = 1;
+	}
+	hppe_sr_mii_ctrl_set(0, uniphy_index, &sr_mii_ctrl);
+
+	return;
+}
+static void
+adpt_hppe_uniphy_usxgmii_duplex_set(a_uint32_t dev_id, a_uint32_t uniphy_index,
+				fal_port_duplex_t duplex)
+{
+	union sr_mii_ctrl_u sr_mii_ctrl;
+	memset(&sr_mii_ctrl, 0, sizeof(sr_mii_ctrl));
+
+	hppe_sr_mii_ctrl_get(dev_id, uniphy_index, &sr_mii_ctrl);
+
+	if (duplex == FAL_FULL_DUPLEX)
+		sr_mii_ctrl.bf.duplex_mode = 1;
+	else
+		sr_mii_ctrl.bf.duplex_mode = 0;
+
+	hppe_sr_mii_ctrl_set(dev_id, uniphy_index, &sr_mii_ctrl);
+
+	return;
+}
+sw_error_t
+adpt_hppe_uniphy_usxgmii_autoneg_completed(a_uint32_t dev_id,
+				a_uint32_t uniphy_index)
+{
+	a_uint32_t autoneg_complete = 0, retries = 100;
+	union vr_mii_an_intr_sts_u vr_mii_an_intr_sts;
+
+	memset(&vr_mii_an_intr_sts, 0, sizeof(vr_mii_an_intr_sts));
+
+	// swith uniphy xpcs auto-neg complete and clear interrupt
+	while (autoneg_complete != 0x1) {
+		mdelay(1);
+		if (retries-- == 0)
+		{
+			printk("uniphy autoneg time out!\n");
+			return SW_TIMEOUT;
+		}
+		hppe_vr_mii_an_intr_sts_get(dev_id, uniphy_index, &vr_mii_an_intr_sts);
+		autoneg_complete = vr_mii_an_intr_sts.bf.cl37_ancmplt_intr;
+	}
+
+	vr_mii_an_intr_sts.bf.cl37_ancmplt_intr = 0;
+	hppe_vr_mii_an_intr_sts_set(dev_id, uniphy_index, &vr_mii_an_intr_sts);
+
+	return SW_OK;
+}
+static void
+adpt_hppe_uniphy_speed_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_speed_t speed)
+{
+	a_uint32_t uniphy_index = 0, mode = 0;
+
+	if (port_id == HPPE_MUX_PORT1)
+		uniphy_index = SSDK_UNIPHY_INSTANCE1;
+	else if (port_id == HPPE_MUX_PORT2)
+		uniphy_index = SSDK_UNIPHY_INSTANCE2;
+
+	mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index);
+	if (mode == PORT_WRAPPER_USXGMII)
+	{
+		/* adpt_hppe_uniphy_usxgmii_autoneg_completed(dev_id,uniphy_index); */
+		/* configure xpcs speed at usxgmii mode */
+		adpt_hppe_uniphy_usxgmii_speed_set(dev_id, uniphy_index, speed);
+	}
+
+	return;
+}
+static void
+adpt_hppe_uniphy_duplex_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_duplex_t duplex)
+{
+	a_uint32_t uniphy_index = 0, mode = 0;
+
+	if (port_id == HPPE_MUX_PORT1)
+		uniphy_index = SSDK_UNIPHY_INSTANCE1;
+	else if (port_id == HPPE_MUX_PORT2)
+		uniphy_index = SSDK_UNIPHY_INSTANCE2;
+
+	mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index);
+	if (mode == PORT_WRAPPER_USXGMII)
+	{
+		/* adpt_hppe_uniphy_usxgmii_autoneg_completed(0,uniphy_index); */
+		/* configure xpcs duplex at usxgmii mode */
+		adpt_hppe_uniphy_usxgmii_duplex_set(dev_id, uniphy_index, duplex);
+	}
+
+	return;
+}
+static void
+adpt_hppe_uniphy_autoneg_status_check(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	a_uint32_t uniphy_index = 0, mode = 0;
+
+	if (port_id == HPPE_MUX_PORT1)
+		uniphy_index = SSDK_UNIPHY_INSTANCE1;
+	else if (port_id == HPPE_MUX_PORT2)
+		uniphy_index = SSDK_UNIPHY_INSTANCE2;
+
+	mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index);
+	if (mode == PORT_WRAPPER_USXGMII)
+	{
+		adpt_hppe_uniphy_usxgmii_autoneg_completed(dev_id,uniphy_index);;
+	}
+	return;
+}
+
+static void
+adpt_hppe_sgmii_speed_clock_set(
+	a_uint32_t dev_id,
+	a_uint32_t port_id,
+	fal_port_speed_t phy_speed)
+{
+	switch (phy_speed) {
+		case FAL_SPEED_10:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, SGMII_SPEED_10M_CLK);
+			break;
+		case FAL_SPEED_100:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, SGMII_SPEED_100M_CLK);
+			break;
+		case FAL_SPEED_1000:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, SGMII_SPEED_1000M_CLK);
+			break;
+		default:
+			break;
+               }
+}
+static void
+adpt_hppe_pqsgmii_speed_clock_set(
+	a_uint32_t dev_id,
+	a_uint32_t port_id,
+	fal_port_speed_t phy_speed)
+{
+	switch (phy_speed) {
+		case FAL_SPEED_10:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, PQSGMII_SPEED_10M_CLK);
+			break;
+		case FAL_SPEED_100:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, PQSGMII_SPEED_100M_CLK);
+			break;
+		case FAL_SPEED_1000:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, PQSGMII_SPEED_1000M_CLK);
+			break;
+		default:
+			break;
+	}
+}
+
+static void
+adpt_hppe_usxgmii_speed_clock_set(
+	a_uint32_t dev_id,
+	a_uint32_t port_id,
+	fal_port_speed_t phy_speed)
+{
+	switch (phy_speed) {
+		case FAL_SPEED_10:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, USXGMII_SPEED_10M_CLK);
+			break;
+		case FAL_SPEED_100:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, USXGMII_SPEED_100M_CLK);
+			break;
+		case FAL_SPEED_1000:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, USXGMII_SPEED_1000M_CLK);
+			break;
+		case FAL_SPEED_2500:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, USXGMII_SPEED_2500M_CLK);
+			break;
+		case FAL_SPEED_5000:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, USXGMII_SPEED_5000M_CLK);
+			break;
+		case FAL_SPEED_10000:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, USXGMII_SPEED_10000M_CLK);
+			break;
+		default:
+			break;
+               }
+
+}
+
+static void
+adpt_hppe_sgmiiplus_speed_clock_set(
+	a_uint32_t dev_id,
+	a_uint32_t port_id,
+	fal_port_speed_t phy_speed)
+{
+               ssdk_port_speed_clock_set(dev_id, port_id, SGMII_PLUS_SPEED_2500M_CLK);
+}
+
+
+void
+adpt_hppe_gcc_port_speed_clock_set(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_port_speed_t phy_speed)
+{
+	a_uint32_t  mode = 0, uniphy_index = 0, mode1 = 0;
+
+	if (port_id < HPPE_MUX_PORT1)
+	{
+#if defined(CPPE)
+		if (port_id == SSDK_PHYSICAL_PORT4) {
+			mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0);
+			if (mode == PORT_WRAPPER_SGMII_PLUS) {
+				adpt_hppe_sgmiiplus_speed_clock_set(dev_id, port_id, phy_speed);
+				return;
+			}
+		}
+#endif
+		adpt_hppe_pqsgmii_speed_clock_set(dev_id, port_id, phy_speed);
+	}
+	else
+	{
+		if (port_id == HPPE_MUX_PORT1)
+		{
+			uniphy_index = SSDK_UNIPHY_INSTANCE0;
+			mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index);
+			mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1);
+			if ((((mode == PORT_WRAPPER_PSGMII) ||
+			      (mode == PORT_WRAPPER_PSGMII_FIBER)) &&
+			     (mode1 == PORT_WRAPPER_MAX)) ||
+			    ((mode == PORT_WRAPPER_SGMII4_RGMII4 ||
+			        mode == PORT_WRAPPER_SGMII_CHANNEL4)
+			        && (mode1 == PORT_WRAPPER_MAX)))
+			{
+				adpt_hppe_pqsgmii_speed_clock_set(dev_id, port_id, phy_speed);
+				return;
+			}
+		}
+		if (port_id == HPPE_MUX_PORT1)
+			uniphy_index = SSDK_UNIPHY_INSTANCE1;
+		else
+			uniphy_index = SSDK_UNIPHY_INSTANCE2;
+
+		mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index);
+		if (mode == PORT_WRAPPER_SGMII0_RGMII4 || mode == PORT_WRAPPER_SGMII_CHANNEL0
+			|| mode == PORT_WRAPPER_SGMII_FIBER)
+			adpt_hppe_sgmii_speed_clock_set(dev_id, port_id, phy_speed);
+		else if (mode == PORT_WRAPPER_SGMII_PLUS)
+			adpt_hppe_sgmiiplus_speed_clock_set(dev_id, port_id, phy_speed);
+		else if ((mode == PORT_WRAPPER_USXGMII) || (mode == PORT_WRAPPER_10GBASE_R))
+			adpt_hppe_usxgmii_speed_clock_set(dev_id,port_id, phy_speed);
+	}
+	return;
+}
+
+void
+adpt_hppe_gcc_uniphy_clock_status_set(a_uint32_t dev_id, a_uint32_t port_id,
+				a_bool_t enable)
+{
+	a_uint32_t mode = 0, uniphy_index = 0, mode1 = 0;
+#if defined(CPPE)
+	a_uint32_t channel_id = 0;
+#endif
+
+	if (port_id < HPPE_MUX_PORT1)
+	{
+		uniphy_index = SSDK_UNIPHY_INSTANCE0;
+#if defined(CPPE)
+		adpt_cppe_port_to_channel_convert(dev_id, port_id,
+				&channel_id);
+		port_id = channel_id;
+#endif
+		qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+				port_id, enable);
+	}
+	else
+	{
+		if (port_id == HPPE_MUX_PORT1)
+		{
+			uniphy_index = SSDK_UNIPHY_INSTANCE0;
+			mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index);
+			mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1);
+			if ((((mode == PORT_WRAPPER_PSGMII) ||
+			      (mode == PORT_WRAPPER_PSGMII_FIBER)) &&
+			     (mode1 == PORT_WRAPPER_MAX)) ||
+			    ((mode == PORT_WRAPPER_SGMII4_RGMII4 ||
+			        mode == PORT_WRAPPER_SGMII_CHANNEL4)
+			        && (mode1 == PORT_WRAPPER_MAX)))
+			{
+				qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+				port_id, enable);
+				return;
+			}
+		}
+		if (port_id == HPPE_MUX_PORT1)
+			uniphy_index = SSDK_UNIPHY_INSTANCE1;
+		else
+			uniphy_index = SSDK_UNIPHY_INSTANCE2;
+
+		qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+				1, enable);
+	}
+	return;
+}
+
+static sw_error_t
+adpt_hppe_port_interface_mode_switch(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	sw_error_t rv = SW_OK;
+	fal_port_interface_mode_t port_mode_old = PORT_INTERFACE_MODE_MAX;
+	fal_port_interface_mode_t port_mode_new = PORT_INTERFACE_MODE_MAX;
+
+	rv = adpt_hppe_port_interface_mode_get(dev_id, port_id,
+				&port_mode_old);
+	SW_RTN_ON_ERROR(rv);
+
+	port_mode_new = port_mode_old;
+	rv = adpt_hppe_port_interface_mode_status_get(dev_id, port_id,
+				&port_mode_new);
+	SW_RTN_ON_ERROR(rv);
+
+	if (port_mode_new != port_mode_old) {
+		SSDK_DEBUG("Port %d change interface mode to %d from %d\n", port_id,
+				port_mode_new, port_mode_old);
+		rv = _adpt_hppe_port_interface_mode_set(dev_id, port_id,
+				port_mode_new);
+		SW_RTN_ON_ERROR(rv);
+		rv = _adpt_hppe_port_interface_mode_apply(dev_id, A_FALSE);
+		SW_RTN_ON_ERROR(rv);
+	}
+
+	return rv;
+}
+
+static sw_error_t
+adpt_hppe_sfp_interface_mode_switch(a_uint32_t dev_id,
+	a_uint32_t port_id)
+{
+	sw_error_t rv = SW_OK;
+
+	if (A_TRUE == hsl_port_is_sfp(dev_id, port_id)) {
+		SSDK_DEBUG("sfp port %d change interface mode!\n", port_id);
+		rv = adpt_hppe_port_interface_mode_switch(dev_id, port_id);
+		SW_RTN_ON_ERROR(rv);
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+adpt_hppe_phy_interface_mode_switch(a_uint32_t dev_id,
+	a_uint32_t port_id)
+{
+	sw_error_t rv = SW_OK;
+
+	if (A_TRUE == _adpt_hppe_port_phy_connected(dev_id, port_id)) {
+		SSDK_DEBUG("phy port %d change interface mode!\n", port_id);
+		rv = adpt_hppe_port_interface_mode_switch(dev_id, port_id);
+		SW_RTN_ON_ERROR(rv);
+	}
+
+	return SW_OK;
+}
+
+void
+adpt_hppe_gcc_mac_clock_status_set(a_uint32_t dev_id, a_uint32_t port_id,
+				a_bool_t enable)
+{
+
+	qca_gcc_mac_port_clock_set(dev_id, port_id, enable);
+
+	return;
+}
+a_bool_t
+adpt_hppe_port_phy_status_change(struct qca_phy_priv *priv, a_uint32_t port_id,
+				struct port_phy_status phy_status)
+{
+	if ((a_uint32_t)phy_status.speed != priv->port_old_speed[port_id - 1])
+		return A_TRUE;
+	if ((a_uint32_t)phy_status.duplex != priv->port_old_duplex[port_id - 1])
+		return A_TRUE;
+	if (phy_status.tx_flowctrl != priv->port_old_tx_flowctrl[port_id - 1])
+		return A_TRUE;
+	if (phy_status.rx_flowctrl != priv->port_old_rx_flowctrl[port_id - 1])
+		return A_TRUE;
+	return A_FALSE;
+}
+sw_error_t
+qca_hppe_mac_sw_sync_task(struct qca_phy_priv *priv)
+{
+	a_uint32_t port_id;
+	struct port_phy_status phy_status = {0};
+	a_bool_t status;
+	a_uint32_t portbmp[SW_MAX_NR_DEV] = {0};
+	sw_error_t rv = SW_OK;
+
+	portbmp[priv->device_id] = qca_ssdk_port_bmp_get(priv->device_id);
+
+	for (port_id = 1; port_id < SW_MAX_NR_PORT; port_id ++) {
+
+		if(!(portbmp[priv->device_id] & (0x1 << port_id)))
+			continue;
+
+		rv = adpt_hppe_sfp_interface_mode_switch(priv->device_id, port_id);
+		if(rv) {
+			SSDK_DEBUG("port %d sfp interface mode change failed\n", port_id);
+		}
+		rv = adpt_hppe_port_phy_status_get(priv->device_id,
+				port_id, &phy_status);
+		if (rv != SW_OK) {
+			SSDK_DEBUG("failed to get port %d status return value is %d\n",
+					port_id, rv);
+			continue;
+		}
+		SSDK_DEBUG("polling task external phy %d link status is %d and speed is %d\n",
+				port_id, phy_status.link_status, phy_status.speed);
+		/* link status from up to down */
+		if ((phy_status.link_status == PORT_LINK_DOWN) &&
+			(priv->port_old_link[port_id - 1] == PORT_LINK_UP))
+		{
+			SSDK_DEBUG("Port %d change to link down status\n", port_id);
+			/* disable ppe port bridge txmac */
+			adpt_hppe_port_bridge_txmac_set(priv->device_id, port_id, A_FALSE);
+			/* disable rx mac */
+			adpt_hppe_port_rxmac_status_set(priv->device_id, port_id, A_FALSE);
+			priv->port_old_link[port_id - 1] = phy_status.link_status;
+			/* switch interface mode if necessary */
+			if (adpt_hppe_phy_interface_mode_switch(priv->device_id,
+					port_id) == SW_OK) {
+				SSDK_DEBUG("Port %d the interface mode switched\n",
+						port_id);
+			}
+#ifdef IN_FDB
+			adpt_hppe_fdb_del_by_port(priv->device_id, port_id, !(FAL_FDB_DEL_STATIC));
+#endif
+			continue;
+		}
+		/* link status from down to up*/
+		if ((phy_status.link_status == PORT_LINK_UP) &&
+			(priv->port_old_link[port_id - 1] == PORT_LINK_DOWN))
+		{
+			SSDK_DEBUG("Port %d change to link up status\n", port_id);
+			status = adpt_hppe_port_phy_status_change(priv, port_id, phy_status);
+			/*disable tx mac*/
+			adpt_hppe_port_txmac_status_set(priv->device_id, port_id, A_FALSE);
+			/* switch interface mode if necessary */
+			if (adpt_hppe_phy_interface_mode_switch(priv->device_id,
+					port_id) == SW_OK) {
+				SSDK_DEBUG("Port %d the interface mode switched\n",
+						port_id);
+			}
+			/* first check uniphy auto-neg complete interrupt to usxgmii */
+			adpt_hppe_uniphy_autoneg_status_check(priv->device_id, port_id);
+			if (status == A_TRUE)
+			{
+				adpt_hppe_gcc_uniphy_clock_status_set(priv->device_id,
+						port_id, A_FALSE);
+				if ((a_uint32_t)phy_status.speed !=
+						priv->port_old_speed[port_id - 1])
+				{
+					/* configure gcc speed clock according to current speed */
+					adpt_hppe_gcc_port_speed_clock_set(priv->device_id, port_id,
+							phy_status.speed);
+
+					/* config uniphy speed to usxgmii mode */
+					adpt_hppe_uniphy_speed_set(priv->device_id, port_id,
+							phy_status.speed);
+
+					/* reset port mac when speed change under usxgmii mode */
+					adpt_hppe_port_speed_change_mac_reset(priv->device_id, port_id);
+
+					/* config mac speed */
+					adpt_hppe_port_mac_speed_set(priv->device_id, port_id,
+							phy_status.speed);
+					priv->port_old_speed[port_id - 1] =
+						(a_uint32_t)phy_status.speed;
+
+					SSDK_DEBUG("Port %d is link up and speed change to %d\n",
+							port_id, priv->port_old_speed[port_id - 1]);
+				}
+				if ((a_uint32_t)phy_status.duplex !=
+						priv->port_old_duplex[port_id - 1])
+				{
+					adpt_hppe_uniphy_duplex_set(priv->device_id, port_id,
+							phy_status.duplex);
+					adpt_hppe_port_mac_duplex_set(priv->device_id, port_id,
+							phy_status.duplex);
+					priv->port_old_duplex[port_id - 1] =
+						(a_uint32_t)phy_status.duplex;
+
+					SSDK_DEBUG("Port %d is link up and duplex change to %d\n",
+							port_id,
+							priv->port_old_duplex[port_id - 1]);
+				}
+				if (priv->port_tx_flowctrl_forcemode[port_id - 1] != A_TRUE)
+				{
+					if (phy_status.duplex == FAL_HALF_DUPLEX)
+					{
+						phy_status.tx_flowctrl = A_TRUE;
+					}
+					if (phy_status.tx_flowctrl !=
+							priv->port_old_tx_flowctrl[port_id - 1])
+					{
+						adpt_hppe_port_txfc_status_set(priv->device_id,
+								port_id, phy_status.tx_flowctrl);
+						priv->port_old_tx_flowctrl[port_id - 1] =
+							phy_status.tx_flowctrl;
+
+						SSDK_DEBUG("Port %d is link up and tx flowctrl"
+							" change to %d\n", port_id,
+							priv->port_old_tx_flowctrl[port_id - 1]);
+					}
+				}
+				if (priv->port_rx_flowctrl_forcemode[port_id - 1] != A_TRUE)
+				{
+					if (phy_status.duplex == FAL_HALF_DUPLEX)
+					{
+						phy_status.rx_flowctrl = A_TRUE;
+					}
+					if (phy_status.rx_flowctrl !=
+							priv->port_old_rx_flowctrl[port_id - 1])
+					{
+						adpt_hppe_port_rxfc_status_set(priv->device_id,
+								port_id, phy_status.rx_flowctrl);
+						priv->port_old_rx_flowctrl[port_id - 1] =
+							phy_status.rx_flowctrl;
+
+						SSDK_DEBUG("Port %d is link up and rx flowctrl"
+							" change to %d\n", port_id,
+							priv->port_old_rx_flowctrl[port_id-1]);
+					}
+				}
+				adpt_hppe_gcc_uniphy_clock_status_set(priv->device_id,
+						port_id, A_TRUE);
+				adpt_hppe_uniphy_port_adapter_reset(priv->device_id, port_id);
+			}
+			/* enable mac and ppe txmac*/
+			adpt_hppe_port_txmac_status_set(priv->device_id, port_id, A_TRUE);
+			adpt_hppe_port_rxmac_status_set(priv->device_id, port_id, A_TRUE);
+			adpt_hppe_port_bridge_txmac_set(priv->device_id, port_id, A_TRUE);
+			priv->port_old_link[port_id - 1] = phy_status.link_status;
+		}
+		SSDK_DEBUG("polling task PPE port %d link status is %d and speed is %d\n",
+				port_id, priv->port_old_link[port_id - 1],
+				priv->port_old_speed[port_id - 1]);
+	}
+	return 0;
+}
+
+void adpt_hppe_port_ctrl_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_port_ctrl_func_bitmap[0] = \
+		((1 << FUNC_ADPT_PORT_LOCAL_LOOPBACK_GET)|
+		(1 << FUNC_ADPT_PORT_AUTONEG_RESTART)|
+		(1 << FUNC_ADPT_PORT_DUPLEX_SET)|
+		(1 << FUNC_ADPT_PORT_RXMAC_STATUS_GET)|
+		(1 << FUNC_ADPT_PORT_CDT)|
+		(1 << FUNC_ADPT_PORT_TXMAC_STATUS_SET)|
+		(1 << FUNC_ADPT_PORT_COMBO_FIBER_MODE_SET)|
+		(1 << FUNC_ADPT_PORT_COMBO_MEDIUM_STATUS_GET)|
+		(1 << FUNC_ADPT_PORT_MAGIC_FRAME_MAC_SET)|
+		(1 << FUNC_ADPT_PORT_POWERSAVE_SET)|
+		(1 << FUNC_ADPT_PORT_HIBERNATE_SET)|
+		(1 << FUNC_ADPT_PORT_8023AZ_GET)|
+		(1 << FUNC_ADPT_PORT_RXFC_STATUS_GET)|
+		(1 << FUNC_ADPT_PORT_TXFC_STATUS_GET)|
+		(1 << FUNC_ADPT_PORT_REMOTE_LOOPBACK_SET)|
+		(1 << FUNC_ADPT_PORT_FLOWCTRL_SET)|
+		(1 << FUNC_ADPT_PORT_MRU_SET)|
+		(1 << FUNC_ADPT_PORT_AUTONEG_STATUS_GET)|
+		(1 << FUNC_ADPT_PORT_TXMAC_STATUS_GET)|
+		(1 << FUNC_ADPT_PORT_MDIX_GET)|
+		(1 << FUNC_ADPT_PORTS_LINK_STATUS_GET)|
+		(1 << FUNC_ADPT_PORT_MAC_LOOPBACK_SET)|
+		(1 << FUNC_ADPT_PORT_PHY_ID_GET)|
+		(1 << FUNC_ADPT_PORT_MRU_GET)|
+		(1 << FUNC_ADPT_PORT_POWER_ON)|
+		(1 << FUNC_ADPT_PORT_SPEED_SET)|
+		(1 << FUNC_ADPT_PORT_INTERFACE_MODE_GET)|
+		(1 << FUNC_ADPT_PORT_DUPLEX_GET)|
+		(1 << FUNC_ADPT_PORT_AUTONEG_ADV_GET)|
+		(1 << FUNC_ADPT_PORT_MDIX_STATUS_GET)|
+		(1 << FUNC_ADPT_PORT_MTU_SET)|
+		(1 << FUNC_ADPT_PORT_LINK_STATUS_GET));
+
+	p_adpt_api->adpt_port_ctrl_func_bitmap[1] = \
+		((1 << (FUNC_ADPT_PORT_8023AZ_SET % 32))|
+		(1 << (FUNC_ADPT_PORT_POWERSAVE_GET % 32))|
+		(1 << (FUNC_ADPT_PORT_COMBO_PREFER_MEDIUM_GET % 32))|
+		(1 << (FUNC_ADPT_PORT_COMBO_PREFER_MEDIUM_SET % 32))|
+		(1 << (FUNC_ADPT_PORT_POWER_OFF % 32))|
+		(1 << (FUNC_ADPT_PORT_TXFC_STATUS_SET % 32))|
+		(1 << (FUNC_ADPT_PORT_COUNTER_SET % 32))|
+		(1 << (FUNC_ADPT_PORT_COMBO_FIBER_MODE_GET % 32))|
+		(1 << (FUNC_ADPT_PORT_LOCAL_LOOPBACK_SET % 32))|
+		(1 << (FUNC_ADPT_PORT_WOL_STATUS_SET % 32))|
+		(1 << (FUNC_ADPT_PORT_MAGIC_FRAME_MAC_GET % 32))|
+		(1 << (FUNC_ADPT_PORT_FLOWCTRL_GET % 32))|
+		(1 << (FUNC_ADPT_PORT_RXMAC_STATUS_SET % 32))|
+		(1 << (FUNC_ADPT_PORT_COUNTER_GET % 32))|
+		(1 << (FUNC_ADPT_PORT_INTERFACE_MODE_SET % 32))|
+		(1 << (FUNC_ADPT_PORT_MAC_LOOPBACK_GET % 32))|
+		(1 << (FUNC_ADPT_PORT_HIBERNATE_GET % 32))|
+		(1 << (FUNC_ADPT_PORT_AUTONEG_ADV_SET % 32))|
+		(1 << (FUNC_ADPT_PORT_REMOTE_LOOPBACK_GET % 32))|
+		(1 << (FUNC_ADPT_PORT_COUNTER_SHOW % 32))|
+		(1 << (FUNC_ADPT_PORT_AUTONEG_ENABLE % 32))|
+		(1 << (FUNC_ADPT_PORT_MTU_GET % 32))|
+		(1 << (FUNC_ADPT_PORT_INTERFACE_MODE_STATUS_GET % 32))|
+		(1 << (FUNC_ADPT_PORT_RESET % 32))|
+		(1 << (FUNC_ADPT_PORT_RXFC_STATUS_SET % 32))|
+		(1 << (FUNC_ADPT_PORT_SPEED_GET % 32))|
+		(1 << (FUNC_ADPT_PORT_MDIX_SET % 32))|
+		(1 << (FUNC_ADPT_PORT_WOL_STATUS_GET % 32))|
+		(1 << (FUNC_ADPT_PORT_MAX_FRAME_SIZE_SET % 32))|
+		(1 << (FUNC_ADPT_PORT_MAX_FRAME_SIZE_GET % 32))|
+		(1 << (FUNC_ADPT_PORT_SOURCE_FILTER_GET % 32))|
+		(1 << (FUNC_ADPT_PORT_SOURCE_FILTER_SET % 32)));
+
+	p_adpt_api->adpt_port_ctrl_func_bitmap[2] = \
+		((1 << (FUNC_ADPT_PORT_INTERFACE_MODE_APPLY% 32))|
+		(1 << (FUNC_ADPT_PORT_INTERFACE_3AZ_STATUS_SET% 32))|
+		(1 << (FUNC_ADPT_PORT_INTERFACE_3AZ_STATUS_GET% 32))|
+		(1 << (FUNC_ADPT_PORT_PROMISC_MODE_SET% 32))|
+		(1 << (FUNC_ADPT_PORT_PROMISC_MODE_GET% 32))|
+		(1 << (FUNC_ADPT_PORT_FLOWCTRL_FORCEMODE_SET% 32))|
+		(1 << (FUNC_ADPT_PORT_FLOWCTRL_FORCEMODE_GET% 32)));
+
+	return;
+
+}
+
+static void adpt_hppe_port_ctrl_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_port_local_loopback_get = NULL;
+	p_adpt_api->adpt_port_autoneg_restart = NULL;
+	p_adpt_api->adpt_port_duplex_set = NULL;
+	p_adpt_api->adpt_port_rxmac_status_get = NULL;
+	p_adpt_api->adpt_port_cdt = NULL;
+	p_adpt_api->adpt_port_txmac_status_set = NULL;
+	p_adpt_api->adpt_port_combo_fiber_mode_set = NULL;
+	p_adpt_api->adpt_port_combo_medium_status_get = NULL;
+	p_adpt_api->adpt_port_magic_frame_mac_set = NULL;
+	p_adpt_api->adpt_port_powersave_set = NULL;
+	p_adpt_api->adpt_port_hibernate_set = NULL;
+	p_adpt_api->adpt_port_8023az_get = NULL;
+	p_adpt_api->adpt_port_rxfc_status_get = NULL;
+	p_adpt_api->adpt_port_txfc_status_get = NULL;
+	p_adpt_api->adpt_port_remote_loopback_set = NULL;
+	p_adpt_api->adpt_port_flowctrl_set = NULL;
+	p_adpt_api->adpt_port_mru_set = NULL;
+	p_adpt_api->adpt_port_autoneg_status_get = NULL;
+	p_adpt_api->adpt_port_txmac_status_get = NULL;
+	p_adpt_api->adpt_port_mdix_get = NULL;
+	p_adpt_api->adpt_ports_link_status_get = NULL;
+	p_adpt_api->adpt_port_mac_loopback_set = NULL;
+	p_adpt_api->adpt_port_phy_id_get = NULL;
+	p_adpt_api->adpt_port_mru_get = NULL;
+	p_adpt_api->adpt_port_power_on = NULL;
+	p_adpt_api->adpt_port_speed_set = NULL;
+	p_adpt_api->adpt_port_interface_mode_get = NULL;
+	p_adpt_api->adpt_port_duplex_get = NULL;
+	p_adpt_api->adpt_port_autoneg_adv_get = NULL;
+	p_adpt_api->adpt_port_mdix_status_get = NULL;
+	p_adpt_api->adpt_port_mtu_set = NULL;
+	p_adpt_api->adpt_port_link_status_get = NULL;
+	p_adpt_api->adpt_port_8023az_set = NULL;
+	p_adpt_api->adpt_port_powersave_get = NULL;
+	p_adpt_api->adpt_port_combo_prefer_medium_get = NULL;
+	p_adpt_api->adpt_port_combo_prefer_medium_set = NULL;
+	p_adpt_api->adpt_port_power_off = NULL;
+	p_adpt_api->adpt_port_txfc_status_set = NULL;
+	p_adpt_api->adpt_port_counter_set = NULL;
+	p_adpt_api->adpt_port_combo_fiber_mode_get = NULL;
+	p_adpt_api->adpt_port_local_loopback_set = NULL;
+	p_adpt_api->adpt_port_wol_status_set = NULL;
+	p_adpt_api->adpt_port_magic_frame_mac_get = NULL;
+	p_adpt_api->adpt_port_flowctrl_get = NULL;
+	p_adpt_api->adpt_port_rxmac_status_set = NULL;
+	p_adpt_api->adpt_port_counter_get = NULL;
+	p_adpt_api->adpt_port_interface_mode_set = NULL;
+	p_adpt_api->adpt_port_interface_mode_apply = NULL;
+	p_adpt_api->adpt_port_mac_loopback_get = NULL;
+	p_adpt_api->adpt_port_hibernate_get = NULL;
+	p_adpt_api->adpt_port_autoneg_adv_set = NULL;
+	p_adpt_api->adpt_port_remote_loopback_get = NULL;
+	p_adpt_api->adpt_port_counter_show = NULL;
+	p_adpt_api->adpt_port_autoneg_enable = NULL;
+	p_adpt_api->adpt_port_mtu_get = NULL;
+	p_adpt_api->adpt_port_interface_mode_status_get = NULL;
+	p_adpt_api->adpt_port_reset = NULL;
+	p_adpt_api->adpt_port_rxfc_status_set = NULL;
+	p_adpt_api->adpt_port_speed_get = NULL;
+	p_adpt_api->adpt_port_mdix_set = NULL;
+	p_adpt_api->adpt_port_wol_status_get = NULL;
+	p_adpt_api->adpt_port_max_frame_size_set = NULL;
+	p_adpt_api->adpt_port_max_frame_size_get = NULL;
+	p_adpt_api->adpt_port_source_filter_get = NULL;
+	p_adpt_api->adpt_port_source_filter_set = NULL;
+	p_adpt_api->adpt_port_interface_3az_status_set = NULL;
+	p_adpt_api->adpt_port_interface_3az_status_get = NULL;
+	p_adpt_api->adpt_port_promisc_mode_set = NULL;
+	p_adpt_api->adpt_port_promisc_mode_get = NULL;
+	p_adpt_api->adpt_port_flowctrl_forcemode_set = NULL;
+	p_adpt_api->adpt_port_flowctrl_forcemode_get = NULL;
+
+	return;
+
+}
+
+sw_error_t adpt_hppe_port_ctrl_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_port_ctrl_func_unregister(dev_id, p_adpt_api);
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_LOCAL_LOOPBACK_GET))
+	{
+		p_adpt_api->adpt_port_local_loopback_get = adpt_hppe_port_local_loopback_get;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_AUTONEG_RESTART))
+	{
+		p_adpt_api->adpt_port_autoneg_restart = adpt_hppe_port_autoneg_restart;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_DUPLEX_SET))
+	{
+		p_adpt_api->adpt_port_duplex_set = adpt_hppe_port_duplex_set;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_RXMAC_STATUS_GET))
+	{
+		p_adpt_api->adpt_port_rxmac_status_get = adpt_hppe_port_rxmac_status_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_CDT))
+	{
+		p_adpt_api->adpt_port_cdt = adpt_hppe_port_cdt;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_TXMAC_STATUS_SET))
+	{
+		p_adpt_api->adpt_port_txmac_status_set = adpt_hppe_port_txmac_status_set;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_COMBO_FIBER_MODE_SET))
+	{
+		p_adpt_api->adpt_port_combo_fiber_mode_set = adpt_hppe_port_combo_fiber_mode_set;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] &
+		(1 << FUNC_ADPT_PORT_COMBO_MEDIUM_STATUS_GET))
+	{
+		p_adpt_api->adpt_port_combo_medium_status_get =
+			adpt_hppe_port_combo_medium_status_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_MAGIC_FRAME_MAC_SET))
+	{
+		p_adpt_api->adpt_port_magic_frame_mac_set = adpt_hppe_port_magic_frame_mac_set;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_POWERSAVE_SET))
+	{
+		p_adpt_api->adpt_port_powersave_set = adpt_hppe_port_powersave_set;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_HIBERNATE_SET))
+	{
+		p_adpt_api->adpt_port_hibernate_set = adpt_hppe_port_hibernate_set;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_8023AZ_GET))
+	{
+		p_adpt_api->adpt_port_8023az_get = adpt_hppe_port_8023az_get;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_RXFC_STATUS_GET))
+	{
+		p_adpt_api->adpt_port_rxfc_status_get = adpt_hppe_port_rxfc_status_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_TXFC_STATUS_GET))
+	{
+		p_adpt_api->adpt_port_txfc_status_get = adpt_hppe_port_txfc_status_get;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_REMOTE_LOOPBACK_SET))
+	{
+		p_adpt_api->adpt_port_remote_loopback_set = adpt_hppe_port_remote_loopback_set;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_FLOWCTRL_SET))
+	{
+		p_adpt_api->adpt_port_flowctrl_set = adpt_hppe_port_flowctrl_set;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_MRU_SET))
+	{
+		p_adpt_api->adpt_port_mru_set = adpt_ppe_port_mru_set;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_AUTONEG_STATUS_GET))
+	{
+		p_adpt_api->adpt_port_autoneg_status_get = adpt_hppe_port_autoneg_status_get;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_TXMAC_STATUS_GET))
+	{
+		p_adpt_api->adpt_port_txmac_status_get = adpt_hppe_port_txmac_status_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_MDIX_GET))
+	{
+		p_adpt_api->adpt_port_mdix_get = adpt_hppe_port_mdix_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORTS_LINK_STATUS_GET))
+	{
+		p_adpt_api->adpt_ports_link_status_get = adpt_hppe_ports_link_status_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_MAC_LOOPBACK_SET))
+	{
+		p_adpt_api->adpt_port_mac_loopback_set = adpt_hppe_port_mac_loopback_set;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_PHY_ID_GET))
+	{
+		p_adpt_api->adpt_port_phy_id_get = adpt_hppe_port_phy_id_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_MRU_GET))
+	{
+		p_adpt_api->adpt_port_mru_get = adpt_ppe_port_mru_get;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_POWER_ON))
+	{
+		p_adpt_api->adpt_port_power_on = adpt_hppe_port_power_on;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_SPEED_SET))
+	{
+		p_adpt_api->adpt_port_speed_set = adpt_hppe_port_speed_set;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_INTERFACE_MODE_GET))
+	{
+		p_adpt_api->adpt_port_interface_mode_get = adpt_hppe_port_interface_mode_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_DUPLEX_GET))
+	{
+		p_adpt_api->adpt_port_duplex_get = adpt_hppe_port_duplex_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_AUTONEG_ADV_GET))
+	{
+		p_adpt_api->adpt_port_autoneg_adv_get = adpt_hppe_port_autoneg_adv_get;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_MDIX_STATUS_GET))
+	{
+		p_adpt_api->adpt_port_mdix_status_get = adpt_hppe_port_mdix_status_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_MTU_SET))
+	{
+		p_adpt_api->adpt_port_mtu_set = adpt_ppe_port_mtu_set;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_LINK_STATUS_GET))
+	{
+		p_adpt_api->adpt_port_link_status_get = adpt_hppe_port_link_status_get;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 <<  (FUNC_ADPT_PORT_8023AZ_SET % 32)))
+	{
+		p_adpt_api->adpt_port_8023az_set = adpt_hppe_port_8023az_set;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 <<  (FUNC_ADPT_PORT_POWERSAVE_GET % 32)))
+	{
+		p_adpt_api->adpt_port_powersave_get = adpt_hppe_port_powersave_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_COMBO_PREFER_MEDIUM_GET % 32)))
+	{
+		p_adpt_api->adpt_port_combo_prefer_medium_get =
+			adpt_hppe_port_combo_prefer_medium_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_COMBO_PREFER_MEDIUM_SET % 32)))
+	{
+		p_adpt_api->adpt_port_combo_prefer_medium_set =
+			adpt_hppe_port_combo_prefer_medium_set;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 <<  (FUNC_ADPT_PORT_POWER_OFF % 32)))
+	{
+		p_adpt_api->adpt_port_power_off = adpt_hppe_port_power_off;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_TXFC_STATUS_SET  % 32)))
+	{
+		p_adpt_api->adpt_port_txfc_status_set = adpt_hppe_port_txfc_status_set;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 <<  (FUNC_ADPT_PORT_COUNTER_SET % 32)))
+	{
+		p_adpt_api->adpt_port_counter_set = adpt_hppe_port_counter_set;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_COMBO_FIBER_MODE_GET % 32)))
+	{
+		p_adpt_api->adpt_port_combo_fiber_mode_get = adpt_hppe_port_combo_fiber_mode_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_LOCAL_LOOPBACK_SET % 32)))
+	{
+		p_adpt_api->adpt_port_local_loopback_set = adpt_hppe_port_local_loopback_set;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 <<  (FUNC_ADPT_PORT_WOL_STATUS_SET % 32)))
+	{
+		p_adpt_api->adpt_port_wol_status_set = adpt_hppe_port_wol_status_set;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_MAGIC_FRAME_MAC_GET % 32)))
+	{
+		p_adpt_api->adpt_port_magic_frame_mac_get = adpt_hppe_port_magic_frame_mac_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 <<  (FUNC_ADPT_PORT_FLOWCTRL_GET % 32)))
+	{
+		p_adpt_api->adpt_port_flowctrl_get = adpt_hppe_port_flowctrl_get;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_RXMAC_STATUS_SET % 32)))
+	{
+		p_adpt_api->adpt_port_rxmac_status_set = adpt_hppe_port_rxmac_status_set;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 <<  (FUNC_ADPT_PORT_COUNTER_GET % 32)))
+	{
+		p_adpt_api->adpt_port_counter_get = adpt_hppe_port_counter_get;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_INTERFACE_MODE_SET % 32)))
+	{
+		p_adpt_api->adpt_port_interface_mode_set = adpt_hppe_port_interface_mode_set;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_MAC_LOOPBACK_GET % 32)))
+	{
+		p_adpt_api->adpt_port_mac_loopback_get = adpt_hppe_port_mac_loopback_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 <<  (FUNC_ADPT_PORT_HIBERNATE_GET % 32)))
+	{
+		p_adpt_api->adpt_port_hibernate_get = adpt_hppe_port_hibernate_get;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_AUTONEG_ADV_SET % 32)))
+	{
+		p_adpt_api->adpt_port_autoneg_adv_set = adpt_hppe_port_autoneg_adv_set;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_REMOTE_LOOPBACK_GET % 32)))
+	{
+		p_adpt_api->adpt_port_remote_loopback_get = adpt_hppe_port_remote_loopback_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 <<  (FUNC_ADPT_PORT_COUNTER_SHOW % 32)))
+	{
+		p_adpt_api->adpt_port_counter_show = adpt_hppe_port_counter_show;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 <<  (FUNC_ADPT_PORT_AUTONEG_ENABLE % 32)))
+	{
+		p_adpt_api->adpt_port_autoneg_enable = adpt_hppe_port_autoneg_enable;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 <<  (FUNC_ADPT_PORT_MTU_GET % 32)))
+	{
+		p_adpt_api->adpt_port_mtu_get = adpt_ppe_port_mtu_get;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_INTERFACE_MODE_STATUS_GET % 32)))
+	{
+		p_adpt_api->adpt_port_interface_mode_status_get =
+			adpt_hppe_port_interface_mode_status_get;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 <<  (FUNC_ADPT_PORT_RESET % 32)))
+	{
+		p_adpt_api->adpt_port_reset = adpt_hppe_port_reset;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_RXFC_STATUS_SET % 32)))
+	{
+		p_adpt_api->adpt_port_rxfc_status_set = adpt_hppe_port_rxfc_status_set;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 <<  (FUNC_ADPT_PORT_SPEED_GET % 32)))
+	{
+		p_adpt_api->adpt_port_speed_get = adpt_hppe_port_speed_get;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 <<  (FUNC_ADPT_PORT_MDIX_SET % 32)))
+	{
+		p_adpt_api->adpt_port_mdix_set = adpt_hppe_port_mdix_set;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 <<  (FUNC_ADPT_PORT_WOL_STATUS_GET % 32)))
+	{
+		p_adpt_api->adpt_port_wol_status_get = adpt_hppe_port_wol_status_get;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_MAX_FRAME_SIZE_SET % 32)))
+	{
+		p_adpt_api->adpt_port_max_frame_size_set = adpt_ppe_port_max_frame_size_set;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_MAX_FRAME_SIZE_GET % 32)))
+	{
+		p_adpt_api->adpt_port_max_frame_size_get = adpt_ppe_port_max_frame_size_get;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_SOURCE_FILTER_GET % 32)))
+	{
+		p_adpt_api->adpt_port_source_filter_get = adpt_ppe_port_source_filter_get;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] &
+		(1 <<  (FUNC_ADPT_PORT_SOURCE_FILTER_SET % 32)))
+	{
+		p_adpt_api->adpt_port_source_filter_set = adpt_ppe_port_source_filter_set;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[2] &
+		(1 <<  (FUNC_ADPT_PORT_INTERFACE_MODE_APPLY% 32)))
+	{
+		p_adpt_api->adpt_port_interface_mode_apply = adpt_hppe_port_interface_mode_apply;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[2] &
+		(1 <<  (FUNC_ADPT_PORT_INTERFACE_3AZ_STATUS_SET% 32)))
+	{
+		p_adpt_api->adpt_port_interface_3az_status_set = adpt_hppe_port_interface_3az_set;
+	}
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[2] &
+		(1 <<  (FUNC_ADPT_PORT_INTERFACE_3AZ_STATUS_GET% 32)))
+	{
+		p_adpt_api->adpt_port_interface_3az_status_get = adpt_hppe_port_interface_3az_get;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[2] &
+		(1 <<  (FUNC_ADPT_PORT_PROMISC_MODE_SET% 32)))
+	{
+		p_adpt_api->adpt_port_promisc_mode_set = adpt_hppe_port_promisc_mode_set;
+	}
+#ifndef IN_PORTCONTROL_MINI
+
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[2] &
+		(1 <<  (FUNC_ADPT_PORT_PROMISC_MODE_GET% 32)))
+	{
+		p_adpt_api->adpt_port_promisc_mode_get = adpt_hppe_port_promisc_mode_get;
+	}
+#endif
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[2] &
+		(1 <<  (FUNC_ADPT_PORT_FLOWCTRL_FORCEMODE_SET% 32)))
+	{
+		p_adpt_api->adpt_port_flowctrl_forcemode_set =
+			adpt_hppe_port_flowctrl_forcemode_set;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	if(p_adpt_api->adpt_port_ctrl_func_bitmap[2] &
+		(1 <<  (FUNC_ADPT_PORT_FLOWCTRL_FORCEMODE_GET% 32)))
+	{
+		p_adpt_api->adpt_port_flowctrl_forcemode_get =
+			adpt_hppe_port_flowctrl_forcemode_get;
+	}
+	p_adpt_api->adpt_port_source_filter_config_get = adpt_ppe_port_source_filter_config_get;
+	p_adpt_api->adpt_port_source_filter_config_set = adpt_ppe_port_source_filter_config_set;
+#endif
+	p_adpt_api->adpt_port_mux_mac_type_set = adpt_hppe_port_mux_mac_type_set;
+	p_adpt_api->adpt_port_mac_speed_set = adpt_hppe_port_mac_speed_set;
+	p_adpt_api->adpt_port_mac_duplex_set = adpt_hppe_port_mac_duplex_set;
+	p_adpt_api->adpt_port_polling_sw_sync_set = qca_hppe_mac_sw_sync_task;
+	p_adpt_api->adpt_port_bridge_txmac_set = adpt_hppe_port_bridge_txmac_set;
+	p_adpt_api->adpt_port_interface_eee_cfg_set = adpt_hppe_port_interface_eee_cfg_set;
+	p_adpt_api->adpt_port_interface_eee_cfg_get = adpt_hppe_port_interface_eee_cfg_get;
+	p_adpt_api->adpt_port_phy_status_get = adpt_hppe_port_phy_status_get;
+#if defined(CPPE)
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+		p_adpt_api->adpt_switch_port_loopback_set = adpt_cppe_switch_port_loopback_set;
+		p_adpt_api->adpt_switch_port_loopback_get = adpt_cppe_switch_port_loopback_get;
+	}
+#endif
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_portvlan.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_portvlan.c
new file mode 100755
index 0000000..aebb885
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_portvlan.c
@@ -0,0 +1,2235 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_portvlan_reg.h"
+#include "hppe_portvlan.h"
+#include "hppe_portctrl_reg.h"
+#include "hppe_portctrl.h"
+#include "hppe_policer_reg.h"
+#include "hppe_policer.h"
+#include "hppe_fdb_reg.h"
+#include "hppe_fdb.h"
+#include "adpt.h"
+
+#ifndef IN_PORTVLAN_MINI
+a_uint32_t
+_get_port_vlan_ingress_trans_by_index(a_uint32_t dev_id,
+		a_uint32_t index, fal_vlan_trans_entry_t *entry)
+{
+	union xlt_rule_tbl_u in_vlan_xlt_rule;
+	union xlt_action_tbl_u in_vlan_xlt_action;
+
+	/*rule part*/
+	SW_RTN_ON_ERROR(hppe_xlt_rule_tbl_get(dev_id, index, &in_vlan_xlt_rule));
+	if (!in_vlan_xlt_rule.bf.valid) {
+		memset(&in_vlan_xlt_rule, 0, sizeof(struct xlt_rule_tbl));
+	}
+
+	entry->trans_direction = 0;
+	entry->frmtype_enable = in_vlan_xlt_rule.bf.frm_type_incl;
+	entry->frmtype = in_vlan_xlt_rule.bf.frm_type;
+	entry->protocol_enable = in_vlan_xlt_rule.bf.prot_incl;
+	entry->protocol = ((in_vlan_xlt_rule.bf.prot_value_1 << 7) |
+			(in_vlan_xlt_rule.bf.prot_value_0));
+
+	entry->port_bitmap = in_vlan_xlt_rule.bf.port_bitmap;
+	entry->c_tagged = in_vlan_xlt_rule.bf.ckey_fmt_0 | (in_vlan_xlt_rule.bf.ckey_fmt_1 << 1);
+	entry->s_tagged = in_vlan_xlt_rule.bf.skey_fmt;
+
+	entry->c_vid_enable = in_vlan_xlt_rule.bf.ckey_vid_incl;
+	entry->c_vid = in_vlan_xlt_rule.bf.ckey_vid;
+	entry->c_pcp_enable = in_vlan_xlt_rule.bf.ckey_pcp_incl;
+	entry->c_pcp = in_vlan_xlt_rule.bf.ckey_pcp;
+	entry->c_dei_enable = in_vlan_xlt_rule.bf.ckey_dei_incl;
+	entry->c_dei = in_vlan_xlt_rule.bf.ckey_dei;
+
+	entry->s_vid_enable = in_vlan_xlt_rule.bf.skey_vid_incl;
+	entry->s_vid = in_vlan_xlt_rule.bf.skey_vid;
+	entry->s_pcp_enable = in_vlan_xlt_rule.bf.skey_pcp_incl;
+	entry->s_pcp = in_vlan_xlt_rule.bf.skey_pcp;
+	entry->s_dei_enable = in_vlan_xlt_rule.bf.skey_dei_incl;
+	entry->s_dei = in_vlan_xlt_rule.bf.skey_dei;
+
+	/*action part*/
+	SW_RTN_ON_ERROR(hppe_xlt_action_tbl_get(dev_id, index, &in_vlan_xlt_action));
+	if (!in_vlan_xlt_rule.bf.valid) {
+		memset(&in_vlan_xlt_action, 0, sizeof(struct xlt_action_tbl));
+	}
+
+	entry->counter_enable = in_vlan_xlt_action.bf.counter_en;
+	entry->counter_id = in_vlan_xlt_action.bf.counter_id;
+	entry->vsi_action_enable = in_vlan_xlt_action.bf.vsi_cmd;
+	entry->vsi_action = in_vlan_xlt_action.bf.vsi;
+
+	entry->cdei_xlt_enable = in_vlan_xlt_action.bf.xlt_cdei_cmd;
+	entry->cdei_xlt = in_vlan_xlt_action.bf.xlt_cdei;
+	entry->sdei_xlt_enable = in_vlan_xlt_action.bf.xlt_sdei_cmd;
+	entry->sdei_xlt = in_vlan_xlt_action.bf.xlt_sdei;
+	entry->swap_sdei_cdei = in_vlan_xlt_action.bf.dei_swap_cmd;
+
+	entry->cpcp_xlt_enable = in_vlan_xlt_action.bf.xlt_cpcp_cmd;
+	entry->cpcp_xlt = in_vlan_xlt_action.bf.xlt_cpcp;
+	entry->spcp_xlt_enable = in_vlan_xlt_action.bf.xlt_spcp_cmd;
+	entry->spcp_xlt = (in_vlan_xlt_action.bf.xlt_spcp_0 |
+			(in_vlan_xlt_action.bf.xlt_spcp_1 << 1));
+	entry->swap_spcp_cpcp = in_vlan_xlt_action.bf.pcp_swap_cmd;
+
+	entry->cvid_xlt_cmd = in_vlan_xlt_action.bf.xlt_cvid_cmd;
+	entry->cvid_xlt = in_vlan_xlt_action.bf.xlt_cvid;
+	entry->svid_xlt_cmd = in_vlan_xlt_action.bf.xlt_svid_cmd;
+	entry->svid_xlt = in_vlan_xlt_action.bf.xlt_svid;
+	entry->swap_svid_cvid = in_vlan_xlt_action.bf.vid_swap_cmd;
+
+	return in_vlan_xlt_rule.bf.valid;
+}
+
+a_uint32_t
+_get_port_vlan_egress_trans_by_index(a_uint32_t dev_id,
+		a_uint32_t index, fal_vlan_trans_entry_t *entry)
+{
+	union eg_vlan_xlt_rule_u eg_vlan_xlt_rule;
+	union eg_vlan_xlt_action_u eg_vlan_xlt_action;
+
+	/*rule part*/
+	SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_rule_get(dev_id, index, &eg_vlan_xlt_rule));
+	if (!eg_vlan_xlt_rule.bf.valid) {
+		memset(&eg_vlan_xlt_rule, 0, sizeof(struct eg_vlan_xlt_rule));
+	}
+
+	entry->trans_direction = 1;
+
+	entry->port_bitmap = eg_vlan_xlt_rule.bf.port_bitmap;
+
+	entry->vsi_enable = eg_vlan_xlt_rule.bf.vsi_incl;
+	entry->vsi = eg_vlan_xlt_rule.bf.vsi;
+	entry->vsi_valid = eg_vlan_xlt_rule.bf.vsi_valid;
+
+	entry->c_tagged = eg_vlan_xlt_rule.bf.ckey_fmt;
+	entry->s_tagged = eg_vlan_xlt_rule.bf.skey_fmt;
+
+	entry->c_vid_enable = eg_vlan_xlt_rule.bf.ckey_vid_incl;
+	entry->c_vid = eg_vlan_xlt_rule.bf.ckey_vid;
+	entry->c_pcp_enable = eg_vlan_xlt_rule.bf.ckey_pcp_incl;
+	entry->c_pcp = eg_vlan_xlt_rule.bf.ckey_pcp;
+	entry->c_dei_enable = eg_vlan_xlt_rule.bf.ckey_dei_incl;
+	entry->c_dei = eg_vlan_xlt_rule.bf.ckey_dei;
+
+	entry->s_vid_enable = eg_vlan_xlt_rule.bf.skey_vid_incl;
+	entry->s_vid = eg_vlan_xlt_rule.bf.skey_vid;
+	entry->s_pcp_enable = eg_vlan_xlt_rule.bf.skey_pcp_incl;
+	entry->s_pcp = eg_vlan_xlt_rule.bf.skey_pcp;
+	entry->s_dei_enable = eg_vlan_xlt_rule.bf.skey_dei_incl;
+	entry->s_dei = eg_vlan_xlt_rule.bf.skey_dei;
+
+	/*action part*/
+	SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_action_get(dev_id, index, &eg_vlan_xlt_action));
+	if (!eg_vlan_xlt_rule.bf.valid) {
+		memset(&eg_vlan_xlt_action, 0, sizeof(struct eg_vlan_xlt_action));
+	}
+
+	entry->counter_enable = eg_vlan_xlt_action.bf.counter_en;
+	entry->counter_id = eg_vlan_xlt_action.bf.counter_id;
+
+	entry->cdei_xlt_enable = eg_vlan_xlt_action.bf.xlt_cdei_cmd;
+	entry->cdei_xlt = eg_vlan_xlt_action.bf.xlt_cdei;
+	entry->sdei_xlt_enable = eg_vlan_xlt_action.bf.xlt_sdei_cmd;
+	entry->sdei_xlt = eg_vlan_xlt_action.bf.xlt_sdei;
+	entry->swap_sdei_cdei = eg_vlan_xlt_action.bf.dei_swap_cmd;
+
+	entry->cpcp_xlt_enable = eg_vlan_xlt_action.bf.xlt_cpcp_cmd;
+	entry->cpcp_xlt = eg_vlan_xlt_action.bf.xlt_cpcp;
+	entry->spcp_xlt_enable = eg_vlan_xlt_action.bf.xlt_spcp_cmd;
+	entry->spcp_xlt = (eg_vlan_xlt_action.bf.xlt_spcp_0 |
+			(eg_vlan_xlt_action.bf.xlt_spcp_1 << 1));
+	entry->swap_spcp_cpcp = eg_vlan_xlt_action.bf.pcp_swap_cmd;
+
+	entry->cvid_xlt_cmd = eg_vlan_xlt_action.bf.xlt_cvid_cmd;
+	entry->cvid_xlt = eg_vlan_xlt_action.bf.xlt_cvid;
+	entry->svid_xlt_cmd = eg_vlan_xlt_action.bf.xlt_svid_cmd;
+	entry->svid_xlt = eg_vlan_xlt_action.bf.xlt_svid;
+	entry->swap_svid_cvid = eg_vlan_xlt_action.bf.vid_swap_cmd;
+
+	return eg_vlan_xlt_rule.bf.valid;
+}
+#endif
+
+a_uint32_t
+_get_port_vlan_trans_adv_rule_by_index(a_uint32_t dev_id,
+		a_uint32_t index, fal_port_vlan_direction_t direction,
+		fal_vlan_trans_adv_rule_t *rule, fal_vlan_trans_adv_action_t * action)
+{
+	union xlt_rule_tbl_u in_vlan_xlt_rule;
+	union xlt_action_tbl_u in_vlan_xlt_action;
+	union eg_vlan_xlt_rule_u eg_vlan_xlt_rule;
+	union eg_vlan_xlt_action_u eg_vlan_xlt_action;
+
+	if (direction == FAL_PORT_VLAN_INGRESS) {
+		/*rule part*/
+		SW_RTN_ON_ERROR(hppe_xlt_rule_tbl_get(dev_id, index, &in_vlan_xlt_rule));
+		if (!in_vlan_xlt_rule.bf.valid) {
+			memset(&in_vlan_xlt_rule, 0, sizeof(struct xlt_rule_tbl));
+		}
+
+		rule->port_bitmap = in_vlan_xlt_rule.bf.port_bitmap;
+
+		rule->s_tagged = in_vlan_xlt_rule.bf.skey_fmt;
+		rule->s_vid_enable = in_vlan_xlt_rule.bf.skey_vid_incl;
+		rule->s_vid = in_vlan_xlt_rule.bf.skey_vid;
+		rule->s_pcp_enable = in_vlan_xlt_rule.bf.skey_pcp_incl;
+		rule->s_pcp = in_vlan_xlt_rule.bf.skey_pcp;
+		rule->s_dei_enable = in_vlan_xlt_rule.bf.skey_dei_incl;
+		rule->s_dei = in_vlan_xlt_rule.bf.skey_dei;
+
+		rule->c_tagged = in_vlan_xlt_rule.bf.ckey_fmt_0 |
+			(in_vlan_xlt_rule.bf.ckey_fmt_1 << 1);
+		rule->c_vid_enable = in_vlan_xlt_rule.bf.ckey_vid_incl;
+		rule->c_vid = in_vlan_xlt_rule.bf.ckey_vid;
+		rule->c_pcp_enable = in_vlan_xlt_rule.bf.ckey_pcp_incl;
+		rule->c_pcp = in_vlan_xlt_rule.bf.ckey_pcp;
+		rule->c_dei_enable = in_vlan_xlt_rule.bf.ckey_dei_incl;
+		rule->c_dei = in_vlan_xlt_rule.bf.ckey_dei;
+
+		rule->frmtype_enable = in_vlan_xlt_rule.bf.frm_type_incl;
+		rule->frmtype = in_vlan_xlt_rule.bf.frm_type;
+		rule->protocol_enable = in_vlan_xlt_rule.bf.prot_incl;
+		rule->protocol = ((in_vlan_xlt_rule.bf.prot_value_1 << 7) |
+				(in_vlan_xlt_rule.bf.prot_value_0));
+
+		/*action part*/
+		SW_RTN_ON_ERROR(hppe_xlt_action_tbl_get(dev_id, index, &in_vlan_xlt_action));
+		if (!in_vlan_xlt_rule.bf.valid) {
+			memset(&in_vlan_xlt_action, 0, sizeof(struct xlt_action_tbl));
+		}
+
+		action->swap_svid_cvid = in_vlan_xlt_action.bf.vid_swap_cmd;
+		action->svid_xlt_cmd = in_vlan_xlt_action.bf.xlt_svid_cmd;
+		action->svid_xlt = in_vlan_xlt_action.bf.xlt_svid;
+		action->cvid_xlt_cmd = in_vlan_xlt_action.bf.xlt_cvid_cmd;
+		action->cvid_xlt = in_vlan_xlt_action.bf.xlt_cvid;
+
+		action->swap_spcp_cpcp = in_vlan_xlt_action.bf.pcp_swap_cmd;
+		action->spcp_xlt_enable = in_vlan_xlt_action.bf.xlt_spcp_cmd;
+		action->spcp_xlt = (in_vlan_xlt_action.bf.xlt_spcp_0 |
+				(in_vlan_xlt_action.bf.xlt_spcp_1 << 1));
+		action->cpcp_xlt_enable = in_vlan_xlt_action.bf.xlt_cpcp_cmd;
+		action->cpcp_xlt = in_vlan_xlt_action.bf.xlt_cpcp;
+
+		action->swap_sdei_cdei = in_vlan_xlt_action.bf.dei_swap_cmd;
+		action->sdei_xlt_enable = in_vlan_xlt_action.bf.xlt_sdei_cmd;
+		action->sdei_xlt = in_vlan_xlt_action.bf.xlt_sdei;
+		action->cdei_xlt_enable = in_vlan_xlt_action.bf.xlt_cdei_cmd;
+		action->cdei_xlt = in_vlan_xlt_action.bf.xlt_cdei;
+
+		action->counter_enable = in_vlan_xlt_action.bf.counter_en;
+		action->counter_id = in_vlan_xlt_action.bf.counter_id;
+		action->vsi_xlt_enable = in_vlan_xlt_action.bf.vsi_cmd;
+		action->vsi_xlt = in_vlan_xlt_action.bf.vsi;
+
+		return in_vlan_xlt_rule.bf.valid;
+	}
+	else
+	{
+		/*rule part*/
+		SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_rule_get(dev_id, index, &eg_vlan_xlt_rule));
+		if (!eg_vlan_xlt_rule.bf.valid) {
+			memset(&eg_vlan_xlt_rule, 0, sizeof(struct eg_vlan_xlt_rule));
+		}
+
+		rule->port_bitmap = eg_vlan_xlt_rule.bf.port_bitmap;
+
+		rule->s_tagged = eg_vlan_xlt_rule.bf.skey_fmt;
+		rule->s_vid_enable = eg_vlan_xlt_rule.bf.skey_vid_incl;
+		rule->s_vid = eg_vlan_xlt_rule.bf.skey_vid;
+		rule->s_pcp_enable = eg_vlan_xlt_rule.bf.skey_pcp_incl;
+		rule->s_pcp = eg_vlan_xlt_rule.bf.skey_pcp;
+		rule->s_dei_enable = eg_vlan_xlt_rule.bf.skey_dei_incl;
+		rule->s_dei = eg_vlan_xlt_rule.bf.skey_dei;
+
+		rule->c_tagged = eg_vlan_xlt_rule.bf.ckey_fmt;
+		rule->c_vid_enable = eg_vlan_xlt_rule.bf.ckey_vid_incl;
+		rule->c_vid = eg_vlan_xlt_rule.bf.ckey_vid;
+		rule->c_pcp_enable = eg_vlan_xlt_rule.bf.ckey_pcp_incl;
+		rule->c_pcp = eg_vlan_xlt_rule.bf.ckey_pcp;
+		rule->c_dei_enable = eg_vlan_xlt_rule.bf.ckey_dei_incl;
+		rule->c_dei = eg_vlan_xlt_rule.bf.ckey_dei;
+
+		rule->vsi_valid = eg_vlan_xlt_rule.bf.vsi_valid;
+		rule->vsi_enable = eg_vlan_xlt_rule.bf.vsi_incl;
+		rule->vsi = eg_vlan_xlt_rule.bf.vsi;
+
+		/*action part*/
+		SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_action_get(dev_id, index, &eg_vlan_xlt_action));
+		if (!eg_vlan_xlt_rule.bf.valid) {
+			memset(&eg_vlan_xlt_action, 0, sizeof(struct eg_vlan_xlt_action));
+		}
+
+		action->swap_svid_cvid = eg_vlan_xlt_action.bf.vid_swap_cmd;
+		action->svid_xlt_cmd = eg_vlan_xlt_action.bf.xlt_svid_cmd;
+		action->svid_xlt = eg_vlan_xlt_action.bf.xlt_svid;
+		action->cvid_xlt_cmd = eg_vlan_xlt_action.bf.xlt_cvid_cmd;
+		action->cvid_xlt = eg_vlan_xlt_action.bf.xlt_cvid;
+
+		action->swap_spcp_cpcp = eg_vlan_xlt_action.bf.pcp_swap_cmd;
+		action->spcp_xlt_enable = eg_vlan_xlt_action.bf.xlt_spcp_cmd;
+		action->spcp_xlt = (eg_vlan_xlt_action.bf.xlt_spcp_0 |
+				(eg_vlan_xlt_action.bf.xlt_spcp_1 << 1));
+		action->cpcp_xlt_enable = eg_vlan_xlt_action.bf.xlt_cpcp_cmd;
+		action->cpcp_xlt = eg_vlan_xlt_action.bf.xlt_cpcp;
+
+		action->swap_sdei_cdei = eg_vlan_xlt_action.bf.dei_swap_cmd;
+		action->sdei_xlt_enable = eg_vlan_xlt_action.bf.xlt_sdei_cmd;
+		action->sdei_xlt = eg_vlan_xlt_action.bf.xlt_sdei;
+		action->cdei_xlt_enable = eg_vlan_xlt_action.bf.xlt_cdei_cmd;
+		action->cdei_xlt = eg_vlan_xlt_action.bf.xlt_cdei;
+
+		action->counter_enable = eg_vlan_xlt_action.bf.counter_en;
+		action->counter_id = eg_vlan_xlt_action.bf.counter_id;
+
+		return eg_vlan_xlt_rule.bf.valid;
+	}
+}
+
+a_uint32_t
+_check_if_rule_equal(fal_port_vlan_direction_t direction, fal_vlan_trans_adv_rule_t * rule1,
+		fal_vlan_trans_adv_rule_t * rule2)
+{
+	if (!(rule1->s_tagged == rule2->s_tagged &&
+		rule1->s_vid_enable == rule2->s_vid_enable && rule1->s_vid == rule2->s_vid &&
+		rule1->s_pcp_enable == rule2->s_pcp_enable && rule1->s_pcp == rule2->s_pcp &&
+		rule1->s_dei_enable == rule2->s_dei_enable && rule1->s_dei == rule2->s_dei &&
+		rule1->c_tagged == rule2->c_tagged &&
+		rule1->c_vid_enable == rule2->c_vid_enable && rule1->c_vid == rule2->c_vid &&
+		rule1->c_pcp_enable == rule2->c_pcp_enable && rule1->c_pcp == rule2->c_pcp &&
+		rule1->c_dei_enable == rule2->c_dei_enable && rule1->c_dei == rule2->c_dei))
+		return 1;
+
+	if (direction == FAL_PORT_VLAN_INGRESS)
+	{
+		if (!(rule1->frmtype_enable == rule2->frmtype_enable &&
+					rule1->frmtype == rule2->frmtype &&
+					rule1->protocol_enable == rule2->protocol_enable &&
+					rule1->protocol == rule2->protocol))
+			return 1;
+	}
+	else
+	{
+		if (!(rule1->vsi_valid == rule2->vsi_valid &&
+					rule1->vsi_enable == rule2->vsi_enable &&
+					rule1->vsi == rule2->vsi))
+			return 1;
+	}
+
+	return 0;
+}
+
+a_uint32_t
+_check_if_action_equal(fal_port_vlan_direction_t direction, fal_vlan_trans_adv_action_t * action1,
+		fal_vlan_trans_adv_action_t * action2)
+{
+	if (!(action1->swap_svid_cvid == action2->swap_svid_cvid &&
+		action1->svid_xlt_cmd == action2->svid_xlt_cmd &&
+		action1->svid_xlt == action2->svid_xlt &&
+		action1->cvid_xlt_cmd == action2->cvid_xlt_cmd &&
+		action1->cvid_xlt == action2->cvid_xlt &&
+		action1->swap_sdei_cdei == action2->swap_sdei_cdei &&
+		action1->sdei_xlt_enable == action2->sdei_xlt_enable &&
+		action1->sdei_xlt == action2->sdei_xlt &&
+		action1->cdei_xlt_enable == action2->cdei_xlt_enable &&
+		action1->cdei_xlt == action2->cdei_xlt &&
+		action1->swap_spcp_cpcp == action2->swap_spcp_cpcp &&
+		action1->spcp_xlt_enable == action2->spcp_xlt_enable &&
+		action1->spcp_xlt == action2->spcp_xlt &&
+		action1->cpcp_xlt_enable == action2->cpcp_xlt_enable &&
+		action1->cpcp_xlt == action2->cpcp_xlt &&
+		action1->counter_enable == action2->counter_enable &&
+		action1->counter_id == action2->counter_id))
+		return 1;
+
+	if (direction == FAL_PORT_VLAN_INGRESS)
+	{
+		if (!(action1->vsi_xlt_enable == action2->vsi_xlt_enable &&
+					action1->vsi_xlt == action2->vsi_xlt))
+			return 1;
+	}
+
+	return 0;
+}
+
+a_uint32_t
+_insert_vlan_trans_adv_rule_action(a_uint32_t dev_id, a_uint32_t index,
+		fal_port_vlan_direction_t direction,
+		fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action)
+{
+	a_uint32_t rtn = SW_OK;
+	union xlt_rule_tbl_u in_vlan_xlt_rule;
+	union eg_vlan_xlt_rule_u eg_vlan_xlt_rule;
+	union xlt_action_tbl_u in_vlan_xlt_action;
+	union eg_vlan_xlt_action_u eg_vlan_xlt_action;
+
+	if (direction == FAL_PORT_VLAN_INGRESS)
+	{
+		in_vlan_xlt_rule.bf.valid = A_TRUE;
+		in_vlan_xlt_rule.bf.port_bitmap = rule->port_bitmap;
+
+		in_vlan_xlt_rule.bf.skey_fmt = rule->s_tagged;
+		in_vlan_xlt_rule.bf.skey_vid_incl = rule->s_vid_enable;
+		in_vlan_xlt_rule.bf.skey_vid = rule->s_vid;
+		in_vlan_xlt_rule.bf.skey_pcp_incl = rule->s_pcp_enable;
+		in_vlan_xlt_rule.bf.skey_pcp = rule->s_pcp;
+		in_vlan_xlt_rule.bf.skey_dei_incl = rule->s_dei_enable;
+		in_vlan_xlt_rule.bf.skey_dei = rule->s_dei;
+
+		in_vlan_xlt_rule.bf.ckey_fmt_0 = (rule->c_tagged & 0x1);
+		in_vlan_xlt_rule.bf.ckey_fmt_1 = (rule->c_tagged >> 1);
+		in_vlan_xlt_rule.bf.ckey_vid_incl = rule->c_vid_enable;
+		in_vlan_xlt_rule.bf.ckey_vid = rule->c_vid;
+		in_vlan_xlt_rule.bf.ckey_pcp_incl = rule->c_pcp_enable;
+		in_vlan_xlt_rule.bf.ckey_pcp = rule->c_pcp;
+		in_vlan_xlt_rule.bf.ckey_dei_incl = rule->c_dei_enable;
+		in_vlan_xlt_rule.bf.ckey_dei = rule->c_dei;
+
+		in_vlan_xlt_rule.bf.prot_incl = rule->protocol_enable;
+		in_vlan_xlt_rule.bf.prot_value_0 = (rule->protocol  & 0x7f);
+		in_vlan_xlt_rule.bf.prot_value_1 = (rule->protocol >> 7);
+		in_vlan_xlt_rule.bf.frm_type_incl = rule->frmtype_enable;
+		in_vlan_xlt_rule.bf.frm_type = rule->frmtype;
+
+		SW_RTN_ON_ERROR(hppe_xlt_rule_tbl_set(dev_id, index, &in_vlan_xlt_rule));
+
+		/*action part*/
+		in_vlan_xlt_action.bf.vid_swap_cmd = action->swap_svid_cvid;
+		in_vlan_xlt_action.bf.xlt_svid_cmd = action->svid_xlt_cmd;
+		in_vlan_xlt_action.bf.xlt_svid = action->svid_xlt;
+		in_vlan_xlt_action.bf.xlt_cvid_cmd = action->cvid_xlt_cmd;
+		in_vlan_xlt_action.bf.xlt_cvid = action->cvid_xlt;
+
+		in_vlan_xlt_action.bf.pcp_swap_cmd = action->swap_spcp_cpcp;
+		in_vlan_xlt_action.bf.xlt_spcp_cmd = action->spcp_xlt_enable;
+		in_vlan_xlt_action.bf.xlt_spcp_0 = (action->spcp_xlt & 0x1);
+		in_vlan_xlt_action.bf.xlt_spcp_1 = (action->spcp_xlt >> 1);
+		in_vlan_xlt_action.bf.xlt_cpcp_cmd = action->cpcp_xlt_enable;
+		in_vlan_xlt_action.bf.xlt_cpcp = action->cpcp_xlt;
+
+		in_vlan_xlt_action.bf.dei_swap_cmd = action->swap_sdei_cdei;
+		in_vlan_xlt_action.bf.xlt_cdei_cmd = action->cdei_xlt_enable;
+		in_vlan_xlt_action.bf.xlt_cdei = action->cdei_xlt;
+		in_vlan_xlt_action.bf.xlt_sdei_cmd = action->sdei_xlt_enable;
+		in_vlan_xlt_action.bf.xlt_sdei = action->sdei_xlt;
+
+		in_vlan_xlt_action.bf.counter_en = action->counter_enable;
+		in_vlan_xlt_action.bf.counter_id = action->counter_id;
+		in_vlan_xlt_action.bf.vsi_cmd = action->vsi_xlt_enable;
+		in_vlan_xlt_action.bf.vsi = action->vsi_xlt;
+
+		SW_RTN_ON_ERROR(hppe_xlt_action_tbl_set(dev_id, index, &in_vlan_xlt_action));
+	}
+	else
+	{
+		eg_vlan_xlt_rule.bf.valid = A_TRUE;
+		eg_vlan_xlt_rule.bf.port_bitmap = rule->port_bitmap;
+
+		eg_vlan_xlt_rule.bf.skey_fmt = rule->s_tagged;
+		eg_vlan_xlt_rule.bf.skey_vid_incl = rule->s_vid_enable;
+		eg_vlan_xlt_rule.bf.skey_vid = rule->s_vid;
+		eg_vlan_xlt_rule.bf.skey_pcp_incl = rule->s_pcp_enable;
+		eg_vlan_xlt_rule.bf.skey_pcp = rule->s_pcp;
+		eg_vlan_xlt_rule.bf.skey_dei_incl = rule->s_dei_enable;
+		eg_vlan_xlt_rule.bf.skey_dei = rule->s_dei;
+
+		eg_vlan_xlt_rule.bf.ckey_fmt = rule->c_tagged;
+		eg_vlan_xlt_rule.bf.ckey_vid_incl = rule->c_vid_enable;
+		eg_vlan_xlt_rule.bf.ckey_vid = rule->c_vid;
+		eg_vlan_xlt_rule.bf.ckey_pcp_incl = rule->c_pcp_enable;
+		eg_vlan_xlt_rule.bf.ckey_pcp = rule->c_pcp;
+		eg_vlan_xlt_rule.bf.ckey_dei_incl = rule->c_dei_enable;
+		eg_vlan_xlt_rule.bf.ckey_dei = rule->c_dei;
+
+		eg_vlan_xlt_rule.bf.vsi_valid = rule->vsi_valid;
+		eg_vlan_xlt_rule.bf.vsi_incl = rule->vsi_enable;
+		eg_vlan_xlt_rule.bf.vsi = rule->vsi;
+
+		SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_rule_set(dev_id, index, &eg_vlan_xlt_rule));
+
+		/*action part*/
+		eg_vlan_xlt_action.bf.vid_swap_cmd = action->swap_svid_cvid;
+		eg_vlan_xlt_action.bf.xlt_svid_cmd = action->svid_xlt_cmd;
+		eg_vlan_xlt_action.bf.xlt_svid = action->svid_xlt;
+		eg_vlan_xlt_action.bf.xlt_cvid_cmd = action->cvid_xlt_cmd;
+		eg_vlan_xlt_action.bf.xlt_cvid = action->cvid_xlt;
+
+		eg_vlan_xlt_action.bf.pcp_swap_cmd = action->swap_spcp_cpcp;
+		eg_vlan_xlt_action.bf.xlt_spcp_cmd = action->spcp_xlt_enable;
+		eg_vlan_xlt_action.bf.xlt_spcp_0 = (action->spcp_xlt & 0x1);
+		eg_vlan_xlt_action.bf.xlt_spcp_1 = (action->spcp_xlt >> 1);
+		eg_vlan_xlt_action.bf.xlt_cpcp_cmd = action->cpcp_xlt_enable;
+		eg_vlan_xlt_action.bf.xlt_cpcp = action->cpcp_xlt;
+
+		eg_vlan_xlt_action.bf.dei_swap_cmd = action->swap_sdei_cdei;
+		eg_vlan_xlt_action.bf.xlt_sdei_cmd = action->sdei_xlt_enable;
+		eg_vlan_xlt_action.bf.xlt_sdei = action->sdei_xlt;
+		eg_vlan_xlt_action.bf.xlt_cdei_cmd = action->cdei_xlt_enable;
+		eg_vlan_xlt_action.bf.xlt_cdei = action->cdei_xlt;
+
+		eg_vlan_xlt_action.bf.counter_en = action->counter_enable;
+		eg_vlan_xlt_action.bf.counter_id = action->counter_id;
+
+		SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_action_set(dev_id, index, &eg_vlan_xlt_action));
+	}
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_global_qinq_mode_set(a_uint32_t dev_id, fal_global_qinq_mode_t *mode)
+{
+	sw_error_t rtn = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (FAL_FLG_TST(mode->mask, FAL_GLOBAL_QINQ_MODE_INGRESS_EN)) {
+		SW_RTN_ON_ERROR(hppe_bridge_config_bridge_type_set(dev_id,
+					(a_uint32_t)mode->ingress_mode));
+	}
+
+	if (FAL_FLG_TST(mode->mask, FAL_GLOBAL_QINQ_MODE_EGRESS_EN)) {
+		SW_RTN_ON_ERROR(hppe_eg_bridge_config_bridge_type_set(dev_id,
+					(a_uint32_t)mode->egress_mode));
+	}
+
+	if (FAL_FLG_TST(mode->mask, FAL_GLOBAL_QINQ_MODE_EGRESS_UNTOUCHED_FOR_CPU_CODE)) {
+		SW_RTN_ON_ERROR(hppe_eg_bridge_config_pkt_l2_edit_en_set(dev_id,
+					(a_uint32_t)!mode->untouched_for_cpucode));
+	}
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_global_qinq_mode_get(a_uint32_t dev_id, fal_global_qinq_mode_t *mode)
+{
+	sw_error_t rtn = SW_OK;
+	a_uint32_t l2_edit_en = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mode);
+
+	SW_RTN_ON_ERROR(hppe_bridge_config_bridge_type_get(dev_id,
+					(a_uint32_t *)&mode->ingress_mode));
+
+	SW_RTN_ON_ERROR(hppe_eg_bridge_config_bridge_type_get(dev_id,
+					(a_uint32_t *)&mode->egress_mode));
+
+	SW_RTN_ON_ERROR(hppe_eg_bridge_config_pkt_l2_edit_en_get(dev_id, &l2_edit_en));
+
+	mode->untouched_for_cpucode = !l2_edit_en;
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_qinq_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode)
+{
+	sw_error_t rtn = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (FAL_FLG_TST(mode->mask, FAL_PORT_QINQ_ROLE_INGRESS_EN)) {
+		SW_RTN_ON_ERROR(hppe_port_parsing_reg_port_role_set(dev_id, port_id,
+					(a_uint32_t)mode->ingress_port_role));
+	}
+
+	if (FAL_FLG_TST(mode->mask, FAL_PORT_QINQ_ROLE_EGRESS_EN)) {
+		SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_vlan_type_set(dev_id, port_id,
+					(a_uint32_t)mode->egress_port_role));
+	}
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_qinq_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode)
+{
+	sw_error_t rtn = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mode);
+
+	SW_RTN_ON_ERROR(hppe_port_parsing_reg_port_role_get(dev_id, port_id,
+				(a_uint32_t *)&mode->ingress_port_role));
+
+	SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_vlan_type_get(dev_id, port_id,
+				(a_uint32_t *)&mode->egress_port_role));
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid)
+{
+	sw_error_t rtn = SW_OK;
+	union edma_vlan_tpid_reg_u edma_tpid;
+	union vlan_tpid_reg_u ppe_tpid;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rtn = hppe_edma_vlan_tpid_reg_get(dev_id, &edma_tpid);
+	SW_RTN_ON_ERROR(rtn);
+
+	rtn = hppe_vlan_tpid_reg_get(dev_id, &ppe_tpid);
+	SW_RTN_ON_ERROR(rtn);
+
+	if (FAL_FLG_TST(tpid->mask, FAL_TPID_CTAG_EN)) {
+		edma_tpid.bf.ctag_tpid = tpid->ctpid;
+		ppe_tpid.bf.ctag_tpid = tpid->ctpid;
+	}
+
+	if (FAL_FLG_TST(tpid->mask, FAL_TPID_STAG_EN)) {
+		edma_tpid.bf.stag_tpid = tpid->stpid;
+		ppe_tpid.bf.stag_tpid = tpid->stpid;
+	}
+
+	rtn = hppe_edma_vlan_tpid_reg_set(dev_id, &edma_tpid);
+	SW_RTN_ON_ERROR(rtn);
+
+	rtn = hppe_vlan_tpid_reg_set(dev_id, &ppe_tpid);
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_tpid_get(a_uint32_t dev_id, fal_tpid_t *tpid)
+{
+	sw_error_t rtn = SW_OK;
+	union vlan_tpid_reg_u ppe_tpid;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(tpid);
+
+	rtn = hppe_vlan_tpid_reg_get(dev_id, &ppe_tpid);
+	SW_RTN_ON_ERROR(rtn);
+
+	tpid->ctpid = ppe_tpid.bf.ctag_tpid;
+	tpid->stpid = ppe_tpid.bf.stag_tpid;
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_egress_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid)
+{
+	sw_error_t rtn = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (FAL_FLG_TST(tpid->mask, FAL_TPID_CTAG_EN)) {
+		SW_RTN_ON_ERROR(hppe_eg_vlan_tpid_ctpid_set(dev_id,
+						(a_uint32_t)tpid->ctpid));
+	}
+
+	if (FAL_FLG_TST(tpid->mask, FAL_TPID_STAG_EN)) {
+		SW_RTN_ON_ERROR(hppe_eg_vlan_tpid_stpid_set(dev_id,
+						(a_uint32_t)tpid->stpid));
+	}
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_egress_tpid_get(a_uint32_t dev_id, fal_tpid_t *tpid)
+{
+	sw_error_t rtn = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(tpid);
+
+	SW_RTN_ON_ERROR(hppe_eg_vlan_tpid_ctpid_get(dev_id,
+					(a_uint32_t *)&tpid->ctpid));
+
+	SW_RTN_ON_ERROR(hppe_eg_vlan_tpid_stpid_get(dev_id,
+					(a_uint32_t *)&tpid->stpid));
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_ingress_vlan_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_ingress_vlan_filter_t *filter)
+{
+	sw_error_t rtn = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	SW_RTN_ON_ERROR(hppe_port_vlan_config_port_in_vlan_fltr_cmd_set(dev_id,
+				port_id, (a_uint32_t)filter->membership_filter));
+	SW_RTN_ON_ERROR(hppe_port_vlan_config_port_untag_fltr_cmd_set(dev_id,
+				port_id, (a_uint32_t)filter->untagged_filter));
+	SW_RTN_ON_ERROR(hppe_port_vlan_config_port_tag_fltr_cmd_set(dev_id,
+				port_id, (a_uint32_t)filter->tagged_filter));
+	SW_RTN_ON_ERROR(hppe_port_vlan_config_port_pri_tag_fltr_cmd_set(dev_id,
+				port_id, (a_uint32_t)filter->priority_filter));
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_ingress_vlan_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_ingress_vlan_filter_t *filter)
+{
+	sw_error_t rtn = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(filter);
+
+	SW_RTN_ON_ERROR(hppe_port_vlan_config_port_in_vlan_fltr_cmd_get(dev_id,
+				port_id, (a_uint32_t *)&filter->membership_filter));
+	SW_RTN_ON_ERROR(hppe_port_vlan_config_port_untag_fltr_cmd_get(dev_id,
+				port_id, (a_uint32_t *)&filter->untagged_filter));
+	SW_RTN_ON_ERROR(hppe_port_vlan_config_port_tag_fltr_cmd_get(dev_id,
+				port_id, (a_uint32_t *)&filter->tagged_filter));
+	SW_RTN_ON_ERROR(hppe_port_vlan_config_port_pri_tag_fltr_cmd_get(dev_id,
+				port_id, (a_uint32_t *)&filter->priority_filter));
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_default_vlantag_set(a_uint32_t dev_id,
+		fal_port_t port_id, fal_port_vlan_direction_t direction,
+		fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag)
+{
+	sw_error_t rtn = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (direction == FAL_PORT_VLAN_EGRESS)
+	{
+		if (!FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_CVID_EN) && 
+			!FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_SVID_EN))
+			return SW_NOT_SUPPORTED;
+	}
+
+	if (direction == FAL_PORT_VLAN_ALL || direction == FAL_PORT_VLAN_INGRESS)
+	{
+		SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_cvid_en_set(dev_id, port_id,
+					(a_uint32_t)default_vid_en->default_cvid_en));
+		SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_svid_en_set(dev_id, port_id,
+					(a_uint32_t)default_vid_en->default_svid_en));
+
+		if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_CVID_EN)) {
+			SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_cvid_set(dev_id, port_id,
+						(a_uint32_t)default_tag->cvid));
+		}
+
+		if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_SVID_EN)) {
+			SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_svid_set(dev_id, port_id,
+						(a_uint32_t)default_tag->svid));
+		}
+
+		if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_CPCP_EN)) {
+			SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_cpcp_set(dev_id, port_id,
+						(a_uint32_t)default_tag->cpri));
+		}
+
+		if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_SPCP_EN)) {
+			SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_spcp_set(dev_id, port_id,
+						(a_uint32_t)default_tag->spri));
+		}
+
+		if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_CDEI_EN)) {
+			SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_cdei_set(dev_id, port_id,
+						(a_uint32_t)default_tag->cdei));
+		}
+
+		if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_SDEI_EN)) {
+			SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_sdei_set(dev_id, port_id,
+						(a_uint32_t)default_tag->sdei));
+		}
+	}
+
+	if (direction == FAL_PORT_VLAN_ALL || direction == FAL_PORT_VLAN_EGRESS)
+	{
+		SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_cvid_en_set(dev_id,
+					port_id, (a_uint32_t)default_vid_en->default_cvid_en));
+		SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_svid_en_set(dev_id,
+					port_id, (a_uint32_t)default_vid_en->default_svid_en));
+
+		if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_CVID_EN)) {
+			SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_cvid_set(dev_id, port_id,
+						(a_uint32_t)default_tag->cvid));
+		}
+
+		if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_SVID_EN)) {
+			SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_svid_set(dev_id, port_id,
+						(a_uint32_t)default_tag->svid));
+		}
+	}
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_default_vlantag_get(a_uint32_t dev_id,
+		fal_port_t port_id, fal_port_vlan_direction_t direction,
+		fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag)
+{
+	sw_error_t rtn = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(default_vid_en);
+	ADPT_NULL_POINT_CHECK(default_tag);
+
+	if (direction == FAL_PORT_VLAN_ALL)
+		return SW_NOT_SUPPORTED;
+
+	if (direction == FAL_PORT_VLAN_INGRESS) {
+		SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_cvid_en_get(dev_id, port_id,
+					(a_uint32_t *)&default_vid_en->default_cvid_en));
+
+		SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_svid_en_get(dev_id, port_id,
+					(a_uint32_t *)&default_vid_en->default_svid_en));
+
+		SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_cvid_get(dev_id, port_id,
+					(a_uint32_t *)&default_tag->cvid));
+
+		SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_svid_get(dev_id, port_id,
+					(a_uint32_t *)&default_tag->svid));
+
+		SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_cpcp_get(dev_id, port_id,
+					(a_uint32_t *)&default_tag->cpri));
+
+		SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_spcp_get(dev_id, port_id,
+					(a_uint32_t *)&default_tag->spri));
+
+		SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_cdei_get(dev_id, port_id,
+					(a_uint32_t *)&default_tag->cdei));
+
+		SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_sdei_get(dev_id, port_id,
+					(a_uint32_t *)&default_tag->sdei));
+	}
+	else if (direction == FAL_PORT_VLAN_EGRESS) {
+		SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_cvid_en_get(dev_id, port_id,
+					(a_uint32_t *)&default_vid_en->default_cvid_en));
+
+		SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_svid_en_get(dev_id, port_id,
+					(a_uint32_t *)&default_vid_en->default_svid_en));
+
+		SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_cvid_get(dev_id, port_id,
+					(a_uint32_t *)&default_tag->cvid));
+
+		SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_svid_get(dev_id, port_id,
+					(a_uint32_t *)&default_tag->svid));
+
+	}
+	else
+		return SW_NOT_SUPPORTED;
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_tag_propagation_set(a_uint32_t dev_id,
+		fal_port_t port_id, fal_port_vlan_direction_t direction,
+		fal_vlantag_propagation_t *prop)
+{
+	sw_error_t rtn = SW_OK;
+	a_uint32_t value_pcp, value_dei = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (prop->pri_propagation == FAL_VLAN_PROPAGATION_DISABLE)
+		value_pcp = 0;
+	else if (prop->pri_propagation == FAL_VLAN_PROPAGATION_CLONE)
+		value_pcp = 1;
+	else
+		return SW_NOT_SUPPORTED;
+
+	if (prop->dei_propagation == FAL_VLAN_PROPAGATION_DISABLE)
+		value_dei = 0;
+	else if (prop->dei_propagation == FAL_VLAN_PROPAGATION_CLONE)
+		value_dei = 1;
+	else
+		return SW_NOT_SUPPORTED;
+
+	if (direction == FAL_PORT_VLAN_ALL || direction == FAL_PORT_VLAN_INGRESS)
+	{
+		if (FAL_FLG_TST(prop->mask, FAL_PORT_PROPAGATION_PCP_EN)) {
+			SW_RTN_ON_ERROR(hppe_port_vlan_config_port_in_pcp_prop_cmd_set(dev_id,
+					port_id, value_pcp));
+		}
+		if (FAL_FLG_TST(prop->mask, FAL_PORT_PROPAGATION_DEI_EN)) {
+			SW_RTN_ON_ERROR(hppe_port_vlan_config_port_in_dei_prop_cmd_set(dev_id,
+					port_id, value_dei));
+		}
+	}
+
+	if (direction == FAL_PORT_VLAN_ALL || direction == FAL_PORT_VLAN_EGRESS)
+	{
+		if (FAL_FLG_TST(prop->mask, FAL_PORT_PROPAGATION_PCP_EN)) {
+			SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_pcp_prop_cmd_set(dev_id,
+					port_id, value_pcp));
+		}
+		if (FAL_FLG_TST(prop->mask, FAL_PORT_PROPAGATION_DEI_EN)) {
+			SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_dei_prop_cmd_set(dev_id,
+					port_id, value_dei));
+		}
+	}
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_tag_propagation_get(a_uint32_t dev_id,
+		fal_port_t port_id, fal_port_vlan_direction_t direction,
+		fal_vlantag_propagation_t *prop)
+{
+	sw_error_t rtn = SW_OK;
+	a_uint32_t value_pcp = 0, value_dei = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(prop);
+
+	if (direction == FAL_PORT_VLAN_ALL)
+		return SW_NOT_SUPPORTED;
+
+	if (direction == FAL_PORT_VLAN_INGRESS) {
+		SW_RTN_ON_ERROR(hppe_port_vlan_config_port_in_pcp_prop_cmd_get(dev_id,
+					port_id, &value_pcp));
+
+		SW_RTN_ON_ERROR(hppe_port_vlan_config_port_in_dei_prop_cmd_get(dev_id,
+					port_id, &value_dei));
+	}
+	else if (direction == FAL_PORT_VLAN_EGRESS) {
+		SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_pcp_prop_cmd_get(dev_id,
+					port_id, &value_pcp));
+
+		SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_dei_prop_cmd_get(dev_id,
+					port_id, &value_dei));
+	}
+	else
+		return SW_NOT_SUPPORTED;
+
+	if (value_pcp == 0)
+		prop->pri_propagation = FAL_VLAN_PROPAGATION_DISABLE;
+	else if (value_pcp == 1)
+		prop->pri_propagation = FAL_VLAN_PROPAGATION_CLONE;
+	else
+		return SW_FAIL;
+
+	if (value_dei == 0)
+		prop->dei_propagation = FAL_VLAN_PROPAGATION_DISABLE;
+	else if (value_dei == 1)
+		prop->dei_propagation = FAL_VLAN_PROPAGATION_CLONE;
+	else
+		return SW_FAIL;
+
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_vlantag_egmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_vlantag_egress_mode_t *port_egvlanmode)
+{
+	sw_error_t rtn = SW_OK;
+	a_uint32_t value = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (FAL_FLG_TST(port_egvlanmode->mask, FAL_EGRESSMODE_CTAG_EN)) {
+		if (port_egvlanmode->ctag_mode == FAL_EG_UNMODIFIED) {
+			value = 2;
+		} else if (port_egvlanmode->ctag_mode == FAL_EG_UNTOUCHED) {
+			value = 3;
+		} else if (port_egvlanmode->ctag_mode == FAL_EG_UNTAGGED) {
+			value = 0;
+		} else if (port_egvlanmode->ctag_mode == FAL_EG_TAGGED) {
+			value = 1;
+		} else {
+			return SW_FAIL;
+		}
+
+		SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_vlan_ctag_mode_set(dev_id,
+					port_id, value));
+	}
+
+	if (FAL_FLG_TST(port_egvlanmode->mask, FAL_EGRESSMODE_STAG_EN)) {
+		if (port_egvlanmode->stag_mode == FAL_EG_UNMODIFIED) {
+			value = 2;
+		} else if (port_egvlanmode->stag_mode == FAL_EG_UNTOUCHED) {
+			value = 3;
+		} else if (port_egvlanmode->stag_mode == FAL_EG_UNTAGGED) {
+			value = 0;
+		} else if (port_egvlanmode->stag_mode == FAL_EG_TAGGED) {
+			value = 1;
+		} else {
+			return SW_FAIL;
+		}
+
+		SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_vlan_stag_mode_set(dev_id,
+					port_id, value));
+	}
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_vlantag_egmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_vlantag_egress_mode_t *port_egvlanmode)
+{
+	sw_error_t rtn = SW_OK;
+	a_uint32_t value = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(port_egvlanmode);
+
+
+	SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_vlan_ctag_mode_get(dev_id,
+				port_id, &value));
+
+	if (value == 2) {
+		port_egvlanmode->ctag_mode = FAL_EG_UNMODIFIED;
+	} else if (value == 3) {
+		port_egvlanmode->ctag_mode = FAL_EG_UNTOUCHED;
+	} else if (value == 0) {
+		port_egvlanmode->ctag_mode = FAL_EG_UNTAGGED;
+	} else if (value == 1) {
+		port_egvlanmode->ctag_mode = FAL_EG_TAGGED;
+	} else {
+		return SW_FAIL;
+	}
+
+	SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_vlan_stag_mode_get(dev_id,
+				port_id, &value));
+
+	if (value == 2) {
+		port_egvlanmode->stag_mode = FAL_EG_UNMODIFIED;
+	} else if (value == 3) {
+		port_egvlanmode->stag_mode = FAL_EG_UNTOUCHED;
+	} else if (value == 0) {
+		port_egvlanmode->stag_mode = FAL_EG_UNTAGGED;
+	} else if (value == 1) {
+		port_egvlanmode->stag_mode = FAL_EG_TAGGED;
+	} else {
+		return SW_FAIL;
+	}
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_vlan_xlt_miss_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_fwd_cmd_t cmd)
+{
+	sw_error_t rtn = SW_OK;
+	a_uint32_t value = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (cmd == FAL_MAC_FRWRD) {
+		value = 0;
+	} else if (cmd == FAL_MAC_DROP) {
+		value = 1;
+	} else if (cmd == FAL_MAC_CPY_TO_CPU) {
+		value = 2;
+	} else if (cmd == FAL_MAC_RDT_TO_CPU) {
+		value = 3;
+	} else {
+		return SW_FAIL;
+	}
+
+	SW_RTN_ON_ERROR(hppe_port_vlan_config_port_vlan_xlt_miss_fwd_cmd_set(dev_id,
+					port_id, value));
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_vlan_xlt_miss_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_fwd_cmd_t *cmd)
+{
+	sw_error_t rtn = SW_OK;
+	a_uint32_t value = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cmd);
+
+	SW_RTN_ON_ERROR(hppe_port_vlan_config_port_vlan_xlt_miss_fwd_cmd_get(dev_id,
+					port_id, &value));
+
+	if (value == 0) {
+		*cmd = FAL_MAC_FRWRD;
+	} else if (value == 1) {
+		*cmd = FAL_MAC_DROP;
+	} else if (value == 2) {
+		*cmd = FAL_MAC_CPY_TO_CPU;
+	} else if (value == 3) {
+		*cmd = FAL_MAC_RDT_TO_CPU;
+	} else {
+		return SW_FAIL;
+	}
+
+	return rtn;
+}
+
+#ifndef IN_PORTVLAN_MINI
+sw_error_t
+adpt_hppe_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * iterator, fal_vlan_trans_entry_t *entry)
+{
+	a_uint32_t idx, eg_tbl_num, rule_valid;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(iterator);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	eg_tbl_num = XLT_RULE_TBL_NUM * 2;
+
+	if (*iterator < XLT_RULE_TBL_NUM) {
+		for (idx = *iterator; idx < XLT_RULE_TBL_NUM; idx++) {
+			aos_mem_zero(entry, sizeof (fal_vlan_trans_entry_t));
+			rule_valid = _get_port_vlan_ingress_trans_by_index(dev_id, idx, entry);
+			if (rule_valid == 1) {
+				if (SW_IS_PBMP_MEMBER(entry->port_bitmap, port_id))
+					break;
+			}
+		}
+
+		if (idx == XLT_RULE_TBL_NUM)
+			return SW_NO_MORE;
+	}
+	else if (*iterator < eg_tbl_num) {
+		for (idx = *iterator; idx < eg_tbl_num; idx++) {
+			aos_mem_zero(entry, sizeof (fal_vlan_trans_entry_t));
+			rule_valid = _get_port_vlan_egress_trans_by_index(dev_id,
+					idx - XLT_RULE_TBL_NUM, entry);
+			if (rule_valid == 1) {
+				if (SW_IS_PBMP_MEMBER(entry->port_bitmap, port_id))
+					break;
+			}
+		}
+
+		if (idx == eg_tbl_num)
+			return SW_NO_MORE;
+	}
+	else {
+		return SW_OUT_OF_RANGE;
+	}
+
+	*iterator = idx + 1;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+	sw_error_t rtn = SW_OK;
+	union xlt_rule_tbl_u in_vlan_xlt_rule;
+	union eg_vlan_xlt_rule_u eg_vlan_xlt_rule;
+	union xlt_action_tbl_u in_vlan_xlt_action;
+	union eg_vlan_xlt_action_u eg_vlan_xlt_action;
+	a_uint32_t idx, entry_idx, entry_sign, rule_valid;
+	fal_vlan_trans_entry_t temp;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	entry_idx = 0;
+
+	if (entry->trans_direction == 0) {
+		/*rule part*/
+		entry_sign = 0;
+		for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) {
+			aos_mem_zero(&temp, sizeof (fal_vlan_trans_entry_t));
+			rule_valid = _get_port_vlan_ingress_trans_by_index(dev_id, idx, &temp);
+			if (rule_valid == 1) {
+				if (!aos_mem_cmp(entry, &temp, sizeof (fal_vlan_trans_entry_t))) {
+					if (SW_IS_PBMP_MEMBER(temp.port_bitmap, port_id))
+						return SW_ALREADY_EXIST;
+					entry_idx = idx;
+					entry_sign = 1;
+					break;
+				}
+			}
+			else {
+				if (entry_sign == 0) {
+					entry_idx = idx;
+					entry_sign = 1;
+				}
+			}
+		}
+
+		if (entry_sign == 0)
+			return SW_NO_RESOURCE;
+
+		in_vlan_xlt_rule.bf.valid = A_TRUE;
+		in_vlan_xlt_rule.bf.port_bitmap = entry->port_bitmap | (0x1 << port_id);
+
+		in_vlan_xlt_rule.bf.prot_incl = entry->protocol_enable;
+		in_vlan_xlt_rule.bf.prot_value_0 = (entry->protocol  & 0x7f);
+		in_vlan_xlt_rule.bf.prot_value_1 = (entry->protocol >> 7);
+		in_vlan_xlt_rule.bf.frm_type_incl = entry->frmtype_enable;
+		in_vlan_xlt_rule.bf.frm_type = entry->frmtype;
+
+		in_vlan_xlt_rule.bf.ckey_fmt_0 = (entry->c_tagged & 0x1);
+		in_vlan_xlt_rule.bf.ckey_fmt_1 = (entry->c_tagged >> 1);
+		in_vlan_xlt_rule.bf.skey_fmt = entry->s_tagged;
+
+		in_vlan_xlt_rule.bf.ckey_vid_incl = entry->c_vid_enable;
+		in_vlan_xlt_rule.bf.ckey_vid = entry->c_vid;
+		in_vlan_xlt_rule.bf.ckey_pcp_incl = entry->c_pcp_enable;
+		in_vlan_xlt_rule.bf.ckey_pcp = entry->c_pcp;
+		in_vlan_xlt_rule.bf.ckey_dei_incl = entry->c_dei_enable;
+		in_vlan_xlt_rule.bf.ckey_dei = entry->c_dei;
+
+		in_vlan_xlt_rule.bf.skey_vid_incl = entry->s_vid_enable;
+		in_vlan_xlt_rule.bf.skey_vid = entry->s_vid;
+		in_vlan_xlt_rule.bf.skey_pcp_incl = entry->s_pcp_enable;
+		in_vlan_xlt_rule.bf.skey_pcp = entry->s_pcp;
+		in_vlan_xlt_rule.bf.skey_dei_incl = entry->s_dei_enable;
+		in_vlan_xlt_rule.bf.skey_dei = entry->s_dei;
+
+		SW_RTN_ON_ERROR(hppe_xlt_rule_tbl_set(dev_id, entry_idx, &in_vlan_xlt_rule));
+
+		/*action part*/
+		in_vlan_xlt_action.bf.counter_en = entry->counter_enable;
+		in_vlan_xlt_action.bf.counter_id = entry->counter_id;
+		in_vlan_xlt_action.bf.vsi_cmd = entry->vsi_action_enable;
+		in_vlan_xlt_action.bf.vsi = entry->vsi_action;
+
+		in_vlan_xlt_action.bf.xlt_cdei_cmd = entry->cdei_xlt_enable;
+		in_vlan_xlt_action.bf.xlt_cdei = entry->cdei_xlt;
+		in_vlan_xlt_action.bf.xlt_sdei_cmd = entry->sdei_xlt_enable;
+		in_vlan_xlt_action.bf.xlt_sdei = entry->sdei_xlt;
+		in_vlan_xlt_action.bf.dei_swap_cmd = entry->swap_sdei_cdei;
+
+		in_vlan_xlt_action.bf.xlt_cpcp_cmd = entry->cpcp_xlt_enable;
+		in_vlan_xlt_action.bf.xlt_cpcp = entry->cpcp_xlt;
+		in_vlan_xlt_action.bf.xlt_spcp_cmd = entry->spcp_xlt_enable;
+		in_vlan_xlt_action.bf.xlt_spcp_0 = (entry->spcp_xlt & 0x1);
+		in_vlan_xlt_action.bf.xlt_spcp_1 = (entry->spcp_xlt >> 1);
+		in_vlan_xlt_action.bf.pcp_swap_cmd = entry->swap_spcp_cpcp;
+
+		in_vlan_xlt_action.bf.xlt_cvid_cmd = entry->cvid_xlt_cmd;
+		in_vlan_xlt_action.bf.xlt_cvid = entry->cvid_xlt;
+		in_vlan_xlt_action.bf.xlt_svid_cmd = entry->svid_xlt_cmd;
+		in_vlan_xlt_action.bf.xlt_svid = entry->svid_xlt;
+		in_vlan_xlt_action.bf.vid_swap_cmd = entry->swap_svid_cvid;
+
+		SW_RTN_ON_ERROR(hppe_xlt_action_tbl_set(dev_id, entry_idx, &in_vlan_xlt_action));
+	}
+	else {
+		/*rule part*/
+		entry_sign = 0;
+		for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) {
+			aos_mem_zero(&temp, sizeof (fal_vlan_trans_entry_t));
+			rule_valid = _get_port_vlan_egress_trans_by_index(dev_id, idx, &temp);
+			if (rule_valid == 1) {
+				if (!aos_mem_cmp(entry, &temp, sizeof (fal_vlan_trans_entry_t))) {
+					if (SW_IS_PBMP_MEMBER(temp.port_bitmap, port_id))
+						return SW_ALREADY_EXIST;
+					entry_idx = idx;
+					entry_sign = 1;
+					break;
+				}
+			}
+			else {
+				if (entry_sign == 0) {
+					entry_idx = idx;
+					entry_sign = 1;
+				}
+			}
+		}
+
+		if (entry_sign == 0)
+			return SW_NO_RESOURCE;
+
+		eg_vlan_xlt_rule.bf.valid = A_TRUE;
+		eg_vlan_xlt_rule.bf.port_bitmap = entry->port_bitmap | (0x1 << port_id);
+
+		eg_vlan_xlt_rule.bf.vsi_incl = entry->vsi_enable;
+		eg_vlan_xlt_rule.bf.vsi = entry->vsi;
+		eg_vlan_xlt_rule.bf.vsi_valid = entry->vsi_valid;
+
+		eg_vlan_xlt_rule.bf.ckey_fmt = entry->c_tagged;
+		eg_vlan_xlt_rule.bf.skey_fmt = entry->s_tagged;
+
+		eg_vlan_xlt_rule.bf.ckey_vid_incl = entry->c_vid_enable;
+		eg_vlan_xlt_rule.bf.ckey_vid = entry->c_vid;
+		eg_vlan_xlt_rule.bf.ckey_pcp_incl = entry->c_pcp_enable;
+		eg_vlan_xlt_rule.bf.ckey_pcp = entry->c_pcp;
+		eg_vlan_xlt_rule.bf.ckey_dei_incl = entry->c_dei_enable;
+		eg_vlan_xlt_rule.bf.ckey_dei = entry->c_dei;
+
+		eg_vlan_xlt_rule.bf.skey_vid_incl = entry->s_vid_enable;
+		eg_vlan_xlt_rule.bf.skey_vid = entry->s_vid;
+		eg_vlan_xlt_rule.bf.skey_pcp_incl = entry->s_pcp_enable;
+		eg_vlan_xlt_rule.bf.skey_pcp = entry->s_pcp;
+		eg_vlan_xlt_rule.bf.skey_dei_incl = entry->s_dei_enable;
+		eg_vlan_xlt_rule.bf.skey_dei = entry->s_dei;
+
+		SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_rule_set(dev_id, entry_idx, &eg_vlan_xlt_rule));
+
+		/*action part*/
+		eg_vlan_xlt_action.bf.counter_en = entry->counter_enable;
+		eg_vlan_xlt_action.bf.counter_id = entry->counter_id;
+
+		eg_vlan_xlt_action.bf.xlt_cdei_cmd = entry->cdei_xlt_enable;
+		eg_vlan_xlt_action.bf.xlt_cdei = entry->cdei_xlt;
+		eg_vlan_xlt_action.bf.xlt_sdei_cmd = entry->sdei_xlt_enable;
+		eg_vlan_xlt_action.bf.xlt_sdei = entry->sdei_xlt;
+		eg_vlan_xlt_action.bf.dei_swap_cmd = entry->swap_sdei_cdei;
+
+		eg_vlan_xlt_action.bf.xlt_cpcp_cmd = entry->cpcp_xlt_enable;
+		eg_vlan_xlt_action.bf.xlt_cpcp = entry->cpcp_xlt;
+		eg_vlan_xlt_action.bf.xlt_spcp_cmd = entry->spcp_xlt_enable;
+		eg_vlan_xlt_action.bf.xlt_spcp_0 = (entry->spcp_xlt & 0x1);
+		eg_vlan_xlt_action.bf.xlt_spcp_1 = (entry->spcp_xlt >> 1);
+		eg_vlan_xlt_action.bf.pcp_swap_cmd = entry->swap_spcp_cpcp;
+
+		eg_vlan_xlt_action.bf.xlt_cvid_cmd = entry->cvid_xlt_cmd;
+		eg_vlan_xlt_action.bf.xlt_cvid = entry->cvid_xlt;
+		eg_vlan_xlt_action.bf.xlt_svid_cmd = entry->svid_xlt_cmd;
+		eg_vlan_xlt_action.bf.xlt_svid = entry->svid_xlt;
+		eg_vlan_xlt_action.bf.vid_swap_cmd = entry->swap_svid_cvid;
+
+		SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_action_set(dev_id,
+					entry_idx, &eg_vlan_xlt_action));
+	}
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+	a_uint32_t idx, rule_valid;
+	fal_vlan_trans_entry_t temp;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	if (entry->trans_direction == 0) {
+		for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) {
+			aos_mem_zero(&temp, sizeof (fal_vlan_trans_entry_t));
+			rule_valid = _get_port_vlan_ingress_trans_by_index(dev_id, idx, &temp);
+			if (rule_valid == 1) {
+				if (!aos_mem_cmp(entry, &temp, sizeof(fal_vlan_trans_entry_t))) {
+					if (SW_IS_PBMP_MEMBER(temp.port_bitmap, port_id)) {
+						aos_mem_copy(entry, &temp,
+								sizeof(fal_vlan_trans_entry_t));
+						return SW_OK;
+					}
+				}
+			}
+		}
+	}
+	else {
+		for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) {
+			aos_mem_zero(&temp, sizeof (fal_vlan_trans_entry_t));
+			rule_valid = _get_port_vlan_egress_trans_by_index(dev_id, idx, &temp);
+			if (rule_valid == 1) {
+				if (!aos_mem_cmp(entry, &temp, sizeof(fal_vlan_trans_entry_t))) {
+					if (SW_IS_PBMP_MEMBER(temp.port_bitmap, port_id)) {
+						aos_mem_copy(entry, &temp,
+								sizeof(fal_vlan_trans_entry_t));
+						return SW_OK;
+					}
+				}
+			}
+		}
+	}
+
+	return SW_NOT_FOUND;
+}
+
+sw_error_t
+adpt_hppe_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+	a_uint32_t idx, rule_valid;
+	fal_vlan_trans_entry_t temp;
+
+	union xlt_rule_tbl_u in_vlan_xlt_rule;
+	union eg_vlan_xlt_rule_u eg_vlan_xlt_rule;
+	union xlt_action_tbl_u in_vlan_xlt_action;
+	union eg_vlan_xlt_action_u eg_vlan_xlt_action;
+
+	memset(&in_vlan_xlt_rule, 0, sizeof(struct xlt_rule_tbl));
+	memset(&eg_vlan_xlt_rule, 0, sizeof(struct eg_vlan_xlt_rule));
+	memset(&in_vlan_xlt_action, 0, sizeof(struct xlt_action_tbl));
+	memset(&eg_vlan_xlt_action, 0, sizeof(struct eg_vlan_xlt_action));
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	if (entry->trans_direction == 0) {
+		for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) {
+			aos_mem_zero(&temp, sizeof (fal_vlan_trans_entry_t));
+			rule_valid = _get_port_vlan_ingress_trans_by_index(dev_id, idx, &temp);
+			if (rule_valid == 1) {
+				if (!aos_mem_cmp(entry, &temp, sizeof (fal_vlan_trans_entry_t))) {
+					if (SW_IS_PBMP_MEMBER(temp.port_bitmap, port_id)) {
+						SW_RTN_ON_ERROR(hppe_xlt_rule_tbl_set(dev_id,
+									idx, &in_vlan_xlt_rule));
+						SW_RTN_ON_ERROR(hppe_xlt_action_tbl_set(dev_id,
+									idx, &in_vlan_xlt_action));
+						return SW_OK;
+					}
+				}
+			}
+		}
+	}
+	else {
+		for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) {
+			aos_mem_zero(&temp, sizeof (fal_vlan_trans_entry_t));
+			rule_valid = _get_port_vlan_egress_trans_by_index(dev_id, idx, &temp);
+			if (rule_valid == 1) {
+				if (!aos_mem_cmp(entry, &temp, sizeof (fal_vlan_trans_entry_t))) {
+					if (SW_IS_PBMP_MEMBER(temp.port_bitmap, port_id)) {
+						SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_rule_set(dev_id,
+									idx, &eg_vlan_xlt_rule));
+						SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_action_set(dev_id,
+									idx, &eg_vlan_xlt_action));
+						return SW_OK;
+					}
+				}
+			}
+		}
+	}
+
+	return SW_NOT_FOUND;
+}
+#endif
+
+sw_error_t
+adpt_hppe_port_vsi_egmode_set(a_uint32_t dev_id,
+		a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t egmode)
+{
+	sw_error_t rtn = SW_OK;
+	a_uint32_t value, tag_value;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+
+	if (egmode == FAL_EG_UNMODIFIED) {
+		value = 2;
+	} else if (egmode == FAL_EG_UNTOUCHED) {
+		value = 3;
+	} else if (egmode == FAL_EG_UNTAGGED) {
+		value = 0;
+	} else if (egmode == FAL_EG_TAGGED) {
+		value = 1;
+	} else {
+		return SW_FAIL;
+	}
+
+	SW_RTN_ON_ERROR(hppe_eg_vsi_tag_tagged_mode_port_bitmap_get(dev_id, vsi, &tag_value));
+
+	tag_value &= ~(0x3 << (port_id * 2));
+	tag_value |= (value << (port_id * 2));
+
+	SW_RTN_ON_ERROR(hppe_eg_vsi_tag_tagged_mode_port_bitmap_set(dev_id, vsi, tag_value));
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_vsi_egmode_get(a_uint32_t dev_id,
+		a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t * egmode)
+{
+	sw_error_t rtn = SW_OK;
+	a_uint32_t value, tag_value;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(egmode);
+
+	SW_RTN_ON_ERROR(hppe_eg_vsi_tag_tagged_mode_port_bitmap_get(dev_id, vsi, &tag_value));
+
+	value = (tag_value >> (port_id * 2)) & 0x3;
+
+	if (value == 0)
+		*egmode = FAL_EG_UNTAGGED;
+	else if (value == 1)
+		*egmode = FAL_EG_TAGGED;
+	else if (value == 2)
+		*egmode = FAL_EG_UNMODIFIED;
+	else if (value == 3)
+		*egmode = FAL_EG_UNTOUCHED;
+	else
+		return SW_FAIL;
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_vlantag_vsi_egmode_enable_set(a_uint32_t dev_id,
+		fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rtn = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	SW_RTN_ON_ERROR(hppe_port_eg_vlan_vsi_tag_mode_en_set(dev_id, port_id, enable));
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_vlantag_vsi_egmode_enable_get(a_uint32_t dev_id,
+		fal_port_t port_id, a_bool_t * enable)
+{
+	sw_error_t rtn = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	SW_RTN_ON_ERROR(hppe_port_eg_vlan_vsi_tag_mode_en_get(dev_id, port_id, enable));
+
+	return rtn;
+}
+
+#ifndef IN_PORTVLAN_MINI
+sw_error_t
+adpt_hppe_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+	sw_error_t rtn = SW_OK;
+	fal_global_qinq_mode_t global_mode;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	global_mode.mask = 0x3;
+	global_mode.ingress_mode = mode;
+	global_mode.egress_mode = mode;
+	adpt_hppe_global_qinq_mode_set(dev_id, &global_mode);
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+	sw_error_t rtn = SW_OK;
+	fal_global_qinq_mode_t global_mode;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	adpt_hppe_global_qinq_mode_get(dev_id, &global_mode);
+
+	if (global_mode.ingress_mode == global_mode.egress_mode)
+		*mode = global_mode.ingress_mode;
+	else
+		return SW_FAIL;
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role)
+{
+	sw_error_t rtn = SW_OK;
+	fal_port_qinq_role_t port_role;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	port_role.mask = 0x3;
+	port_role.ingress_port_role = role;
+	port_role.egress_port_role = role;
+	adpt_hppe_port_qinq_mode_set(dev_id, port_id, &port_role);
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role)
+{
+	sw_error_t rtn = SW_OK;
+	fal_port_qinq_role_t port_role;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	adpt_hppe_port_qinq_mode_get(dev_id, port_id, &port_role);
+
+	if (port_role.ingress_port_role == port_role.egress_port_role)
+		*role = port_role.ingress_port_role;
+	else
+		return SW_FAIL;
+
+	return rtn;
+}
+#endif
+
+sw_error_t
+adpt_hppe_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_pt_invlan_mode_t mode)
+{
+	sw_error_t rtn = SW_OK;
+	fal_ingress_vlan_filter_t filter;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (mode == FAL_INVLAN_ADMIT_ALL)
+	{
+		filter.tagged_filter = A_FALSE;
+		filter.untagged_filter = A_FALSE;
+		filter.priority_filter = A_FALSE;
+	}
+	else if (mode == FAL_INVLAN_ADMIT_TAGGED)
+	{
+		filter.tagged_filter = A_FALSE;
+		filter.untagged_filter = A_TRUE;
+		filter.priority_filter = A_TRUE;
+	}
+	else if (mode == FAL_INVLAN_ADMIT_UNTAGGED)
+	{
+		filter.tagged_filter = A_TRUE;
+		filter.untagged_filter = A_FALSE;
+		filter.priority_filter = A_FALSE;
+	}
+	else
+		return SW_FAIL;
+
+	adpt_hppe_port_ingress_vlan_filter_set(dev_id, port_id, &filter);
+
+	return rtn;
+}
+
+#ifndef IN_PORTVLAN_MINI
+sw_error_t
+adpt_hppe_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_pt_invlan_mode_t * mode)
+{
+	sw_error_t rtn = SW_OK;
+	fal_ingress_vlan_filter_t filter;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	adpt_hppe_port_ingress_vlan_filter_get(dev_id, port_id, &filter);
+
+	if (filter.tagged_filter == A_FALSE && filter.untagged_filter == A_FALSE && 
+		filter.priority_filter  == A_FALSE)
+		*mode = FAL_INVLAN_ADMIT_ALL;
+	else if (filter.tagged_filter == A_FALSE && filter.untagged_filter == A_TRUE &&
+		filter.priority_filter  == A_TRUE)
+		*mode = FAL_INVLAN_ADMIT_TAGGED;
+	else if (filter.tagged_filter == A_TRUE && filter.untagged_filter == A_FALSE &&
+		filter.priority_filter  == A_FALSE)
+		*mode = FAL_INVLAN_ADMIT_UNTAGGED;
+	else
+		return SW_FAIL;
+
+	return rtn;
+}
+#endif
+
+sw_error_t
+adpt_hppe_port_vlan_trans_adv_add(a_uint32_t dev_id,
+		fal_port_t port_id, fal_port_vlan_direction_t direction,
+		fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action)
+{
+	sw_error_t rtn = SW_OK;
+	a_uint32_t entry_idx, entry_sign, rule_valid;
+	a_int32_t idx;
+	fal_vlan_trans_adv_rule_t temp_rule;
+	fal_vlan_trans_adv_action_t temp_action;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (direction == FAL_PORT_VLAN_ALL)
+		return SW_FAIL;
+
+	entry_sign = 0;
+	for (idx = XLT_RULE_TBL_NUM - 1; idx >= 0; idx--) {
+		aos_mem_zero(&temp_rule, sizeof (fal_vlan_trans_adv_rule_t));
+		aos_mem_zero(&temp_action, sizeof (fal_vlan_trans_adv_action_t));
+		rule_valid = _get_port_vlan_trans_adv_rule_by_index(dev_id,
+				idx, direction, &temp_rule, &temp_action);
+		if (rule_valid == 1)
+		{ /* existing rule */
+			if (!_check_if_rule_equal(direction, &temp_rule, rule))
+			{ /* rule equal */
+				if (!_check_if_action_equal(direction, &temp_action, action))
+				{ /* action equal */
+					if (SW_IS_PBMP_MEMBER(temp_rule.port_bitmap, port_id))
+					{ /* current port_bitmap includes this port_id,
+					     nothing need to do */
+						return SW_ALREADY_EXIST;
+					}
+					else
+					{ /* current port_bitmap doesn't include this port_id,
+					     add this port_id */
+						temp_rule.port_bitmap |= (0x1 << port_id);
+						_insert_vlan_trans_adv_rule_action(dev_id,
+								idx, direction, &temp_rule,
+								&temp_action);
+						return SW_OK;
+					}
+				}
+				else
+				{ /* action not equal */
+					if (temp_rule.port_bitmap == (0x1 << port_id))
+					{ /* port equal, need update action */
+						_insert_vlan_trans_adv_rule_action(dev_id,
+								idx, direction, &temp_rule,
+								action);
+						return SW_OK;
+					}
+					else
+					{ /* port not equal, need remove port from existing rule
+					     bitmap, insert new rule and action later */
+						temp_rule.port_bitmap &= ~(0x1 << port_id);
+						_insert_vlan_trans_adv_rule_action(dev_id, idx,
+								direction, &temp_rule,
+								&temp_action);
+					}
+				}
+			}
+			else
+			{ /* rule not equal, nothing need to do */
+				;
+			}
+		}
+		else
+		{ /* nonexist rule */
+			if (entry_sign == 0) {
+				entry_idx = idx;
+				entry_sign = 1;
+			}
+		}
+	}
+
+	if (entry_sign == 0)
+		return SW_NO_RESOURCE;
+
+	/* insert new rule and action */
+	rule->port_bitmap |= (0x1 << port_id);
+	_insert_vlan_trans_adv_rule_action(dev_id, entry_idx, direction, rule, action);
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_vlan_trans_adv_del(a_uint32_t dev_id,
+		fal_port_t port_id, fal_port_vlan_direction_t direction,
+		fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action)
+{
+	sw_error_t rtn = SW_OK;
+	a_uint32_t idx, rule_valid;
+	fal_vlan_trans_adv_rule_t temp_rule;
+	fal_vlan_trans_adv_action_t temp_action;
+	union xlt_rule_tbl_u in_vlan_xlt_rule;
+	union eg_vlan_xlt_rule_u eg_vlan_xlt_rule;
+	union xlt_action_tbl_u in_vlan_xlt_action;
+	union eg_vlan_xlt_action_u eg_vlan_xlt_action;
+
+	memset(&in_vlan_xlt_rule, 0, sizeof(struct xlt_rule_tbl));
+	memset(&eg_vlan_xlt_rule, 0, sizeof(struct eg_vlan_xlt_rule));
+	memset(&in_vlan_xlt_action, 0, sizeof(struct xlt_action_tbl));
+	memset(&eg_vlan_xlt_action, 0, sizeof(struct eg_vlan_xlt_action));
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (direction == FAL_PORT_VLAN_ALL)
+		return SW_FAIL;
+
+	for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) {
+		aos_mem_zero(&temp_rule, sizeof (fal_vlan_trans_adv_rule_t));
+		aos_mem_zero(&temp_action, sizeof (fal_vlan_trans_adv_action_t));
+		rule_valid = _get_port_vlan_trans_adv_rule_by_index(dev_id,
+				idx, direction, &temp_rule, &temp_action);
+		if (rule_valid == 1)
+		{ /* existing rule */
+			if (!_check_if_rule_equal(direction, &temp_rule, rule))
+			{ /* rule equal */
+				if (!_check_if_action_equal(direction, &temp_action, action))
+				{ /* action equal */
+					if (temp_rule.port_bitmap == (0x1 << port_id))
+					{ /* port equal, need delete existing rule and action */
+						if (direction == FAL_PORT_VLAN_INGRESS)
+						{
+							rtn = hppe_xlt_rule_tbl_set(dev_id,
+									idx, &in_vlan_xlt_rule);
+							SW_RTN_ON_ERROR(rtn);
+							rtn = hppe_xlt_action_tbl_set(dev_id,
+									idx, &in_vlan_xlt_action);
+							SW_RTN_ON_ERROR(rtn);
+						}
+						else
+						{
+							rtn = hppe_eg_vlan_xlt_rule_set(dev_id,
+									idx, &eg_vlan_xlt_rule);
+							SW_RTN_ON_ERROR(rtn);
+							rtn = hppe_eg_vlan_xlt_action_set(dev_id,
+									idx, &eg_vlan_xlt_action);
+							SW_RTN_ON_ERROR(rtn);
+						}
+					}
+					else if (SW_IS_PBMP_MEMBER(temp_rule.port_bitmap, port_id))
+					{ /* current port_bitmap includes this port_id,
+					     remove port from port_bitmap and update rule
+					     and action */
+						temp_rule.port_bitmap &= ~(0x1 << port_id);
+						_insert_vlan_trans_adv_rule_action(dev_id,
+								idx, direction, &temp_rule,
+								&temp_action);
+					}
+					else
+					{ /* current port_bitmap doesn't include port_id,
+					     return SW_NOT_FOUND */
+						return SW_NOT_FOUND;
+					}
+					break;
+				}
+			}
+		}
+	}
+
+	if (idx == XLT_RULE_TBL_NUM)
+		return SW_NOT_FOUND;
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_vlan_trans_adv_getfirst(a_uint32_t dev_id,
+		fal_port_t port_id, fal_port_vlan_direction_t direction,
+		fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action)
+{
+	sw_error_t rtn = SW_OK;
+	a_uint32_t idx, rule_valid;
+	fal_vlan_trans_adv_rule_t temp_rule;
+	fal_vlan_trans_adv_action_t temp_action;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(rule);
+	ADPT_NULL_POINT_CHECK(action);
+
+	if (direction == FAL_PORT_VLAN_ALL)
+		return SW_FAIL;
+
+	for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) {
+		aos_mem_zero(&temp_rule, sizeof (fal_vlan_trans_adv_rule_t));
+		aos_mem_zero(&temp_action, sizeof (fal_vlan_trans_adv_action_t));
+		rule_valid = _get_port_vlan_trans_adv_rule_by_index(dev_id,
+				idx, direction, &temp_rule, &temp_action);
+		if (rule_valid == 1 && SW_IS_PBMP_MEMBER(temp_rule.port_bitmap, port_id))
+		{
+			aos_mem_copy(rule, &temp_rule, sizeof (fal_vlan_trans_adv_rule_t));
+			aos_mem_copy(action, &temp_action, sizeof (fal_vlan_trans_adv_action_t));
+			break;
+		}
+	}
+
+	if (idx == XLT_RULE_TBL_NUM)
+		return SW_NOT_FOUND;
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_vlan_trans_adv_getnext(a_uint32_t dev_id,
+		fal_port_t port_id, fal_port_vlan_direction_t direction,
+		fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action)
+{
+	sw_error_t rtn = SW_OK, sign_tag = 0;
+	a_uint32_t idx, rule_valid;
+	fal_vlan_trans_adv_rule_t temp_rule;
+	fal_vlan_trans_adv_action_t temp_action;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(rule);
+	ADPT_NULL_POINT_CHECK(action);
+
+	if (direction == FAL_PORT_VLAN_ALL)
+		return SW_FAIL;
+
+	for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) {
+		aos_mem_zero(&temp_rule, sizeof (fal_vlan_trans_adv_rule_t));
+		aos_mem_zero(&temp_action, sizeof (fal_vlan_trans_adv_action_t));
+		rule_valid = _get_port_vlan_trans_adv_rule_by_index(dev_id, idx,
+				direction, &temp_rule, &temp_action);
+		if (rule_valid == 1)
+		{ /* existing rule */
+			if (sign_tag == 1 && SW_IS_PBMP_MEMBER(temp_rule.port_bitmap, port_id))
+			{
+				aos_mem_copy(rule, &temp_rule,
+						sizeof (fal_vlan_trans_adv_rule_t));
+				aos_mem_copy(action, &temp_action,
+						sizeof (fal_vlan_trans_adv_action_t));
+				break;
+			}
+			if (!_check_if_rule_equal(direction, &temp_rule, rule))
+			{ /* rule equal */
+				if (!_check_if_action_equal(direction, &temp_action, action))
+				{ /* action equal */
+					if (SW_IS_PBMP_MEMBER(temp_rule.port_bitmap, port_id))
+						sign_tag = 1;
+				}
+			}
+		}
+	}
+
+	if (idx == XLT_RULE_TBL_NUM)
+		return SW_NOT_FOUND;
+
+	return rtn;
+}
+
+sw_error_t
+adpt_hppe_port_vlan_counter_get(a_uint32_t dev_id,
+		a_uint32_t cnt_index, fal_port_vlan_counter_t * counter)
+{
+	union vlan_dev_cnt_tbl_u vlan_dev_cnt_tbl;
+	union vlan_dev_tx_counter_tbl_u vlan_dev_tx_counter_tbl;
+
+	SW_RTN_ON_ERROR(hppe_vlan_dev_cnt_tbl_get(dev_id, cnt_index, &vlan_dev_cnt_tbl));
+	SW_RTN_ON_ERROR(hppe_vlan_dev_tx_counter_tbl_get(dev_id,
+				cnt_index, &vlan_dev_tx_counter_tbl));
+
+	counter->rx_packet_counter = vlan_dev_cnt_tbl.bf.rx_pkt_cnt;
+	counter->rx_byte_counter = ((a_uint64_t)vlan_dev_cnt_tbl.bf.rx_byte_cnt_1 << 32) |
+		vlan_dev_cnt_tbl.bf.rx_byte_cnt_0;
+	counter->tx_packet_counter = vlan_dev_tx_counter_tbl.bf.tx_pkt_cnt;
+	counter->tx_byte_counter = ((a_uint64_t)vlan_dev_tx_counter_tbl.bf.tx_byte_cnt_1 << 32) |
+		vlan_dev_tx_counter_tbl.bf.tx_byte_cnt_0;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_vlan_counter_cleanup(a_uint32_t dev_id, a_uint32_t cnt_index)
+{
+	union vlan_dev_cnt_tbl_u vlan_dev_cnt_tbl;
+	union vlan_dev_tx_counter_tbl_u vlan_dev_tx_counter_tbl;
+
+	memset(&vlan_dev_cnt_tbl, 0, sizeof(union vlan_dev_cnt_tbl_u));
+	memset(&vlan_dev_tx_counter_tbl, 0, sizeof(union vlan_dev_tx_counter_tbl_u));
+
+	SW_RTN_ON_ERROR(hppe_vlan_dev_cnt_tbl_set(dev_id, cnt_index, &vlan_dev_cnt_tbl));
+	SW_RTN_ON_ERROR(hppe_vlan_dev_tx_counter_tbl_set(dev_id,
+				cnt_index, &vlan_dev_tx_counter_tbl));
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, fal_port_t mem_port_id)
+{
+	union port_bridge_ctrl_u port_bridge_ctrl;
+
+	port_id = FAL_PORT_ID_VALUE(port_id);
+	mem_port_id = FAL_PORT_ID_VALUE(mem_port_id);
+
+	memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl);
+
+	port_bridge_ctrl.bf.port_isolation_bitmap |= (0x1 << mem_port_id);
+
+	SW_RTN_ON_ERROR(hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl));
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, fal_port_t mem_port_id)
+{
+	union port_bridge_ctrl_u port_bridge_ctrl;
+
+	port_id = FAL_PORT_ID_VALUE(port_id);
+	mem_port_id = FAL_PORT_ID_VALUE(mem_port_id);
+
+	memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl);
+
+	port_bridge_ctrl.bf.port_isolation_bitmap &= ~(0x1 << mem_port_id);
+
+	SW_RTN_ON_ERROR(hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl));
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, fal_pbmp_t mem_port_map)
+{
+	union port_bridge_ctrl_u port_bridge_ctrl;
+
+	port_id = FAL_PORT_ID_VALUE(port_id);
+
+	memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl);
+
+	port_bridge_ctrl.bf.port_isolation_bitmap = mem_port_map;
+
+	SW_RTN_ON_ERROR(hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl));
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, fal_pbmp_t * mem_port_map)
+{
+	union port_bridge_ctrl_u port_bridge_ctrl;
+
+	port_id = FAL_PORT_ID_VALUE(port_id);
+
+	memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl);
+
+	*mem_port_map = port_bridge_ctrl.bf.port_isolation_bitmap;
+
+	return SW_OK;
+}
+
+void adpt_hppe_portvlan_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_portvlan_func_bitmap[0] = ((1 << FUNC_PORT_INVLAN_MODE_SET) |
+						(1 << FUNC_PORT_INVLAN_MODE_GET) |
+						(1 << FUNC_PORT_VLAN_TRANS_ADD) |
+						(1 << FUNC_PORT_VLAN_TRANS_DEL) |
+						(1 << FUNC_PORT_VLAN_TRANS_GET) |
+						(1 << FUNC_QINQ_MODE_SET) |
+						(1 << FUNC_QINQ_MODE_GET) |
+						(1 << FUNC_PORT_QINQ_ROLE_SET) |
+						(1 << FUNC_PORT_QINQ_ROLE_GET) |
+						(1 << FUNC_PORT_VLAN_TRANS_ITERATE) |
+						(1 << FUNC_GLOBAL_QINQ_MODE_SET) |
+						(1 << FUNC_GLOBAL_QINQ_MODE_GET) |
+						(1 << FUNC_PORT_QINQ_MODE_SET) |
+						(1 << FUNC_PORT_QINQ_MODE_GET) |
+						(1 << FUNC_INGRESS_TPID_SET) |
+						(1 << FUNC_INGRESS_TPID_GET) |
+						(1 << FUNC_EGRESS_TPID_SET) |
+						(1 << FUNC_EGRESS_TPID_GET) |
+						(1 << FUNC_PORT_INGRESS_VLAN_FILTER_SET) |
+						(1 << FUNC_PORT_INGRESS_VLAN_FILTER_GET) |
+						(1 << FUNC_PORT_DEFAULT_VLANTAG_SET) |
+						(1 << FUNC_PORT_DEFAULT_VLANTAG_GET) |
+						(1 << FUNC_PORT_TAG_PROPAGATION_SET) |
+						(1 << FUNC_PORT_TAG_PROPAGATION_GET) |
+						(1 << FUNC_PORT_VLANTAG_EGMODE_SET) |
+						(1 << FUNC_PORT_VLANTAG_EGMODE_GET) |
+						(1 << FUNC_PORT_VLAN_XLT_MISS_CMD_SET) |
+						(1 << FUNC_PORT_VLAN_XLT_MISS_CMD_GET) |
+						(1 << FUNC_PORT_VSI_EGMODE_SET) |
+						(1 << FUNC_PORT_VSI_EGMODE_GET) |
+						(1 << FUNC_PORT_VLANTAG_VSI_EGMODE_ENABLE_SET) |
+						(1 << FUNC_PORT_VLANTAG_VSI_EGMODE_ENABLE_GET));
+
+	p_adpt_api->adpt_portvlan_func_bitmap[1] = ((1 << (FUNC_PORT_VLAN_TRANS_ADV_ADD % 32)) |
+						(1 << (FUNC_PORT_VLAN_TRANS_ADV_DEL % 32)) |
+						(1 << (FUNC_PORT_VLAN_TRANS_ADV_GETFIRST % 32)) |
+						(1 << (FUNC_PORT_VLAN_TRANS_ADV_GETNEXT % 32)) |
+						(1 << (FUNC_PORT_VLAN_COUNTER_GET % 32)) |
+						(1 << (FUNC_PORT_VLAN_COUNTER_CLEANUP % 32)) |
+						(1 << (FUNC_PORT_VLAN_MEMBER_ADD % 32)) |
+						(1 << (FUNC_PORT_VLAN_MEMBER_DEL % 32)) |
+						(1 << (FUNC_PORT_VLAN_MEMBER_UPDATE % 32)) |
+						(1 << (FUNC_PORT_VLAN_MEMBER_GET % 32)));
+
+	return;
+}
+
+static void adpt_hppe_portvlan_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_global_qinq_mode_set = NULL;
+	p_adpt_api->adpt_global_qinq_mode_get = NULL;
+	p_adpt_api->adpt_port_qinq_mode_set = NULL;
+	p_adpt_api->adpt_port_qinq_mode_get = NULL;
+	p_adpt_api->adpt_tpid_set = NULL;
+	p_adpt_api->adpt_tpid_get = NULL;
+	p_adpt_api->adpt_egress_tpid_set = NULL;
+	p_adpt_api->adpt_egress_tpid_get = NULL;
+	p_adpt_api->adpt_port_ingress_vlan_filter_set = NULL;
+	p_adpt_api->adpt_port_ingress_vlan_filter_get = NULL;
+	p_adpt_api->adpt_port_default_vlantag_set = NULL;
+	p_adpt_api->adpt_port_default_vlantag_get = NULL;
+	p_adpt_api->adpt_port_tag_propagation_set = NULL;
+	p_adpt_api->adpt_port_tag_propagation_get = NULL;
+	p_adpt_api->adpt_port_vlantag_egmode_set = NULL;
+	p_adpt_api->adpt_port_vlantag_egmode_get = NULL;
+	p_adpt_api->adpt_port_vlan_xlt_miss_cmd_set = NULL;
+	p_adpt_api->adpt_port_vlan_xlt_miss_cmd_get = NULL;
+	p_adpt_api->adpt_port_vlan_trans_iterate = NULL;
+	p_adpt_api->adpt_port_vlan_trans_add = NULL;
+	p_adpt_api->adpt_port_vlan_trans_get = NULL;
+	p_adpt_api->adpt_port_vlan_trans_del = NULL;
+
+	p_adpt_api->adpt_port_vsi_egmode_set = NULL;
+	p_adpt_api->adpt_port_vsi_egmode_get = NULL;
+	p_adpt_api->adpt_port_vlantag_vsi_egmode_enable_set = NULL;
+	p_adpt_api->adpt_port_vlantag_vsi_egmode_enable_get = NULL;
+
+	p_adpt_api->adpt_qinq_mode_set = NULL;
+	p_adpt_api->adpt_qinq_mode_get = NULL;
+	p_adpt_api->adpt_port_qinq_role_set = NULL;
+	p_adpt_api->adpt_port_qinq_role_get = NULL;
+	p_adpt_api->adpt_port_invlan_mode_set = NULL;
+	p_adpt_api->adpt_port_invlan_mode_get = NULL;
+
+	p_adpt_api->adpt_port_vlan_trans_adv_add = NULL;
+	p_adpt_api->adpt_port_vlan_trans_adv_del = NULL;
+	p_adpt_api->adpt_port_vlan_trans_adv_getfirst = NULL;
+	p_adpt_api->adpt_port_vlan_trans_adv_getnext = NULL;
+
+	p_adpt_api->adpt_port_vlan_counter_get = NULL;
+	p_adpt_api->adpt_port_vlan_counter_cleanup = NULL;
+
+	p_adpt_api->adpt_portvlan_member_add = NULL;
+	p_adpt_api->adpt_portvlan_member_del = NULL;
+	p_adpt_api->adpt_portvlan_member_update = NULL;
+	p_adpt_api->adpt_portvlan_member_get = NULL;
+
+	return;
+}
+
+sw_error_t adpt_hppe_portvlan_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_portvlan_func_unregister(dev_id, p_adpt_api);
+
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_GLOBAL_QINQ_MODE_SET))
+		p_adpt_api->adpt_global_qinq_mode_set = adpt_hppe_global_qinq_mode_set;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_GLOBAL_QINQ_MODE_GET))
+		p_adpt_api->adpt_global_qinq_mode_get = adpt_hppe_global_qinq_mode_get;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_QINQ_MODE_SET))
+		p_adpt_api->adpt_port_qinq_mode_set = adpt_hppe_port_qinq_mode_set;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_QINQ_MODE_GET))
+		p_adpt_api->adpt_port_qinq_mode_get = adpt_hppe_port_qinq_mode_get;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_INGRESS_TPID_SET))
+		p_adpt_api->adpt_tpid_set = adpt_hppe_tpid_set;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_INGRESS_TPID_GET))
+		p_adpt_api->adpt_tpid_get = adpt_hppe_tpid_get;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_EGRESS_TPID_SET))
+		p_adpt_api->adpt_egress_tpid_set = adpt_hppe_egress_tpid_set;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_EGRESS_TPID_GET))
+		p_adpt_api->adpt_egress_tpid_get = adpt_hppe_egress_tpid_get;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_INGRESS_VLAN_FILTER_SET))
+		p_adpt_api->adpt_port_ingress_vlan_filter_set =
+			adpt_hppe_port_ingress_vlan_filter_set;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_INGRESS_VLAN_FILTER_GET))
+		p_adpt_api->adpt_port_ingress_vlan_filter_get =
+			adpt_hppe_port_ingress_vlan_filter_get;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_DEFAULT_VLANTAG_SET))
+		p_adpt_api->adpt_port_default_vlantag_set = adpt_hppe_port_default_vlantag_set;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_DEFAULT_VLANTAG_GET))
+		p_adpt_api->adpt_port_default_vlantag_get = adpt_hppe_port_default_vlantag_get;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_TAG_PROPAGATION_SET))
+		p_adpt_api->adpt_port_tag_propagation_set = adpt_hppe_port_tag_propagation_set;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_TAG_PROPAGATION_GET))
+		p_adpt_api->adpt_port_tag_propagation_get = adpt_hppe_port_tag_propagation_get;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLANTAG_EGMODE_SET))
+		p_adpt_api->adpt_port_vlantag_egmode_set = adpt_hppe_port_vlantag_egmode_set;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLANTAG_EGMODE_GET))
+		p_adpt_api->adpt_port_vlantag_egmode_get = adpt_hppe_port_vlantag_egmode_get;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLAN_XLT_MISS_CMD_SET))
+		p_adpt_api->adpt_port_vlan_xlt_miss_cmd_set = adpt_hppe_port_vlan_xlt_miss_cmd_set;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLAN_XLT_MISS_CMD_GET))
+		p_adpt_api->adpt_port_vlan_xlt_miss_cmd_get = adpt_hppe_port_vlan_xlt_miss_cmd_get;
+#ifndef IN_PORTVLAN_MINI
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLAN_TRANS_ITERATE))
+		p_adpt_api->adpt_port_vlan_trans_iterate = adpt_hppe_port_vlan_trans_iterate;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLAN_TRANS_ADD))
+		p_adpt_api->adpt_port_vlan_trans_add = adpt_hppe_port_vlan_trans_add;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLAN_TRANS_GET))
+		p_adpt_api->adpt_port_vlan_trans_get = adpt_hppe_port_vlan_trans_get;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLAN_TRANS_DEL))
+		p_adpt_api->adpt_port_vlan_trans_del = adpt_hppe_port_vlan_trans_del;
+#endif
+
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VSI_EGMODE_SET))
+		p_adpt_api->adpt_port_vsi_egmode_set = adpt_hppe_port_vsi_egmode_set;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VSI_EGMODE_GET))
+		p_adpt_api->adpt_port_vsi_egmode_get = adpt_hppe_port_vsi_egmode_get;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] &
+			(1 << FUNC_PORT_VLANTAG_VSI_EGMODE_ENABLE_SET))
+		p_adpt_api->adpt_port_vlantag_vsi_egmode_enable_set =
+			adpt_hppe_port_vlantag_vsi_egmode_enable_set;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] &
+			(1 << FUNC_PORT_VLANTAG_VSI_EGMODE_ENABLE_GET))
+		p_adpt_api->adpt_port_vlantag_vsi_egmode_enable_get =
+			adpt_hppe_port_vlantag_vsi_egmode_enable_get;
+#ifndef IN_PORTVLAN_MINI
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_QINQ_MODE_SET))
+		p_adpt_api->adpt_qinq_mode_set = adpt_hppe_qinq_mode_set;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_QINQ_MODE_GET))
+		p_adpt_api->adpt_qinq_mode_get = adpt_hppe_qinq_mode_get;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_QINQ_ROLE_SET))
+		p_adpt_api->adpt_port_qinq_role_set = adpt_hppe_port_qinq_role_set;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_QINQ_ROLE_GET))
+		p_adpt_api->adpt_port_qinq_role_get = adpt_hppe_port_qinq_role_get;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_INVLAN_MODE_GET))
+		p_adpt_api->adpt_port_invlan_mode_get = adpt_hppe_port_invlan_mode_get;
+#endif
+	if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_INVLAN_MODE_SET))
+		p_adpt_api->adpt_port_invlan_mode_set = adpt_hppe_port_invlan_mode_set;
+
+	if (p_adpt_api->adpt_portvlan_func_bitmap[1] & (1 << (FUNC_PORT_VLAN_TRANS_ADV_ADD % 32)))
+		p_adpt_api->adpt_port_vlan_trans_adv_add = adpt_hppe_port_vlan_trans_adv_add;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[1] & (1 << (FUNC_PORT_VLAN_TRANS_ADV_DEL % 32)))
+		p_adpt_api->adpt_port_vlan_trans_adv_del = adpt_hppe_port_vlan_trans_adv_del;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[1] &
+			(1 << (FUNC_PORT_VLAN_TRANS_ADV_GETFIRST % 32)))
+		p_adpt_api->adpt_port_vlan_trans_adv_getfirst =
+			adpt_hppe_port_vlan_trans_adv_getfirst;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[1] &
+			(1 << (FUNC_PORT_VLAN_TRANS_ADV_GETNEXT % 32)))
+		p_adpt_api->adpt_port_vlan_trans_adv_getnext =
+			adpt_hppe_port_vlan_trans_adv_getnext;
+
+	if (p_adpt_api->adpt_portvlan_func_bitmap[1] & (1 << (FUNC_PORT_VLAN_COUNTER_GET % 32)))
+		p_adpt_api->adpt_port_vlan_counter_get = adpt_hppe_port_vlan_counter_get;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[1] &
+			(1 << (FUNC_PORT_VLAN_COUNTER_CLEANUP % 32)))
+		p_adpt_api->adpt_port_vlan_counter_cleanup = adpt_hppe_port_vlan_counter_cleanup;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[1] & (1 << (FUNC_PORT_VLAN_MEMBER_ADD % 32)))
+		p_adpt_api->adpt_portvlan_member_add = adpt_hppe_portvlan_member_add;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[1] & (1 << (FUNC_PORT_VLAN_MEMBER_DEL % 32)))
+		p_adpt_api->adpt_portvlan_member_del = adpt_hppe_portvlan_member_del;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[1] & (1 << (FUNC_PORT_VLAN_MEMBER_UPDATE % 32)))
+		p_adpt_api->adpt_portvlan_member_update = adpt_hppe_portvlan_member_update;
+	if (p_adpt_api->adpt_portvlan_func_bitmap[1] & (1 << (FUNC_PORT_VLAN_MEMBER_GET % 32)))
+		p_adpt_api->adpt_portvlan_member_get = adpt_hppe_portvlan_member_get;
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_pppoe.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_pppoe.c
new file mode 100755
index 0000000..059cae6
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_pppoe.c
@@ -0,0 +1,330 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_pppoe_reg.h"
+#include "hppe_pppoe.h"
+#include "hppe_ip_reg.h"
+#include "hppe_ip.h"
+#include "adpt.h"
+
+#define MAX_SESSION_ID 0xffff
+
+sw_error_t
+adpt_hppe_pppoe_session_table_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+	sw_error_t rv = SW_OK;
+	union pppoe_session_u pppoe_session = {0};
+	union pppoe_session_ext_u pppoe_session_ext = {0};
+	union pppoe_session_ext1_u pppoe_session_ext1 = {0};
+	union eg_l3_if_tbl_u eg_l3_if_tbl = {0};
+	a_uint32_t num, index, entry_idx = PPPOE_SESSION_MAX_ENTRY;
+	a_uint16_t smac_ext = 0;
+	a_uint32_t smac_ext1 = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(session_tbl);
+
+	if (session_tbl->session_id > MAX_SESSION_ID)
+		return SW_BAD_PARAM;
+	if (session_tbl->multi_session == A_FALSE && session_tbl->uni_session == A_FALSE)
+		return SW_BAD_PARAM;
+	if (session_tbl->l3_if_index >= IN_L3_IF_TBL_MAX_ENTRY)
+		return SW_BAD_PARAM;
+	for (num = 0; num < PPPOE_SESSION_MAX_ENTRY; num++)
+	{
+		hppe_pppoe_session_get(dev_id, num, &pppoe_session);
+		hppe_pppoe_session_ext_get(dev_id, num, &pppoe_session_ext);
+		hppe_pppoe_session_ext1_get(dev_id, num, &pppoe_session_ext1);
+
+		for (index = 0; index <= 3; index++) {
+			smac_ext1 = (smac_ext1 << 8) + session_tbl->smac_addr.uc[index];
+
+		}
+		for (index = 4; index <= 5; index++) {
+			smac_ext = (smac_ext << 8) + session_tbl->smac_addr.uc[index];
+		}
+
+		if (pppoe_session_ext.bf.mc_valid == A_FALSE &&
+				pppoe_session_ext.bf.uc_valid == A_FALSE)
+		{
+			if (entry_idx == PPPOE_SESSION_MAX_ENTRY)
+				entry_idx = num;
+		}
+		else if (pppoe_session.bf.session_id == session_tbl->session_id &&
+				pppoe_session_ext.bf.smac_valid == session_tbl->smac_valid) {
+			if (session_tbl->smac_valid == A_FALSE ||
+					(session_tbl->smac_valid == A_TRUE &&
+					 smac_ext == pppoe_session_ext.bf.smac &&
+					 smac_ext1 == pppoe_session_ext1.bf.smac)) {
+				return SW_ALREADY_EXIST;
+			}
+		}
+	}
+	if (entry_idx == PPPOE_SESSION_MAX_ENTRY)
+		return SW_NO_RESOURCE;
+
+	pppoe_session.bf.session_id = session_tbl->session_id;
+	pppoe_session.bf.port_bitmap = session_tbl->port_bitmap;
+	pppoe_session.bf.l3_if_index = session_tbl->l3_if_index;
+
+	pppoe_session_ext.bf.l3_if_valid = session_tbl->l3_if_valid;
+	pppoe_session_ext.bf.mc_valid = session_tbl->multi_session;
+	pppoe_session_ext.bf.uc_valid = session_tbl->uni_session;
+	pppoe_session_ext.bf.smac_valid = session_tbl->smac_valid;
+
+	pppoe_session_ext.bf.smac = smac_ext;
+	pppoe_session_ext1.bf.smac = smac_ext1;
+
+	hppe_pppoe_session_set(dev_id, entry_idx, &pppoe_session);
+	hppe_pppoe_session_ext_set(dev_id, entry_idx, &pppoe_session_ext);
+	hppe_pppoe_session_ext1_set(dev_id, entry_idx, &pppoe_session_ext1);
+
+	rv = hppe_eg_l3_if_tbl_get(dev_id, session_tbl->l3_if_index, &eg_l3_if_tbl);
+	SW_RTN_ON_ERROR(rv);
+
+	eg_l3_if_tbl.bf.session_id = session_tbl->session_id;
+	rv = hppe_eg_l3_if_tbl_set(dev_id, session_tbl->l3_if_index, &eg_l3_if_tbl);
+	SW_RTN_ON_ERROR(rv);
+
+	session_tbl->entry_id = entry_idx;
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_pppoe_session_table_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+	sw_error_t rv = SW_OK;
+	union pppoe_session_u pppoe_session = {0};
+	union pppoe_session_ext_u pppoe_session_ext = {0};
+	union pppoe_session_ext1_u pppoe_session_ext1 = {0};
+	union pppoe_session_u pppoe_session_zero = {0};
+	union pppoe_session_ext_u pppoe_session_ext_zero = {0};
+	union pppoe_session_ext1_u pppoe_session_ext1_zero = {0};
+	union eg_l3_if_tbl_u eg_l3_if_tbl = {0};
+	a_uint16_t smac_ext = 0;
+	a_uint32_t smac_ext1 = 0;
+	a_uint32_t num, index;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(session_tbl);
+
+	if (session_tbl->session_id > MAX_SESSION_ID)
+		return SW_BAD_PARAM;
+
+	for (num = 0; num < PPPOE_SESSION_MAX_ENTRY; num++)
+	{
+		hppe_pppoe_session_get(dev_id, num, &pppoe_session);
+		hppe_pppoe_session_ext_get(dev_id, num, &pppoe_session_ext);
+		hppe_pppoe_session_ext1_get(dev_id, num, &pppoe_session_ext1);
+
+		for (index = 0; index <= 3; index++) {
+			smac_ext1 = (smac_ext1 << 8) + session_tbl->smac_addr.uc[index];
+		}
+		for (index = 4; index <= 5; index++) {
+			smac_ext = (smac_ext << 8) + session_tbl->smac_addr.uc[index];
+		}
+
+		if ((pppoe_session_ext.bf.mc_valid == A_TRUE ||
+					pppoe_session_ext.bf.uc_valid == A_TRUE) &&
+				(pppoe_session.bf.session_id == session_tbl->session_id &&
+				 pppoe_session_ext.bf.smac_valid == session_tbl->smac_valid &&
+				 (session_tbl->smac_valid == A_FALSE ||
+				  (session_tbl->smac_valid == A_TRUE &&
+				   smac_ext == pppoe_session_ext.bf.smac &&
+				   smac_ext1 == pppoe_session_ext1.bf.smac))))
+		{
+			hppe_pppoe_session_set(dev_id, num, &pppoe_session_zero);
+			hppe_pppoe_session_ext_set(dev_id, num, &pppoe_session_ext_zero);
+			hppe_pppoe_session_ext1_set(dev_id, num, &pppoe_session_ext1_zero);
+
+			rv = hppe_eg_l3_if_tbl_get(dev_id,
+					pppoe_session.bf.l3_if_index, &eg_l3_if_tbl);
+			SW_RTN_ON_ERROR(rv);
+
+			eg_l3_if_tbl.bf.session_id = 0;
+			rv = hppe_eg_l3_if_tbl_set(dev_id,
+					pppoe_session.bf.l3_if_index, &eg_l3_if_tbl);
+
+			return rv;
+		}
+	}
+
+	return SW_NOT_FOUND;
+}
+
+sw_error_t
+adpt_hppe_pppoe_session_table_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+	union pppoe_session_u pppoe_session = {0};
+	union pppoe_session_ext_u pppoe_session_ext = {0};
+	union pppoe_session_ext1_u pppoe_session_ext1 = {0};
+	a_uint16_t smac_ext = 0;
+	a_uint32_t smac_ext1 = 0;
+	a_uint32_t num, index;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(session_tbl);
+
+	if (session_tbl->session_id > MAX_SESSION_ID)
+		return SW_BAD_PARAM;
+
+	for (num = 0; num < PPPOE_SESSION_MAX_ENTRY; num++)
+	{
+		hppe_pppoe_session_get(dev_id, num, &pppoe_session);
+		hppe_pppoe_session_ext_get(dev_id, num, &pppoe_session_ext);
+		hppe_pppoe_session_ext1_get(dev_id, num, &pppoe_session_ext1);
+
+		for (index = 0; index <= 3; index++) {
+			smac_ext1 = (smac_ext1 << 8) + session_tbl->smac_addr.uc[index];
+		}
+		for (index = 4; index <= 5; index++) {
+			smac_ext = (smac_ext << 8) + session_tbl->smac_addr.uc[index];
+		}
+		if ((pppoe_session_ext.bf.mc_valid == A_TRUE ||
+					pppoe_session_ext.bf.uc_valid == A_TRUE) &&
+				(pppoe_session.bf.session_id == session_tbl->session_id &&
+				 pppoe_session_ext.bf.smac_valid == session_tbl->smac_valid &&
+				 (session_tbl->smac_valid == A_FALSE ||
+				  (session_tbl->smac_valid == A_TRUE &&
+				   smac_ext == pppoe_session_ext.bf.smac &&
+				   smac_ext1 == pppoe_session_ext1.bf.smac))))
+		{
+			session_tbl->entry_id = num;
+			session_tbl->session_id = pppoe_session.bf.session_id;
+			session_tbl->port_bitmap = pppoe_session.bf.port_bitmap;
+			session_tbl->l3_if_index = pppoe_session.bf.l3_if_index;
+			session_tbl->l3_if_valid = pppoe_session_ext.bf.l3_if_valid;
+			session_tbl->multi_session = pppoe_session_ext.bf.mc_valid;
+			session_tbl->uni_session = pppoe_session_ext.bf.uc_valid;
+			session_tbl->smac_valid = pppoe_session_ext.bf.smac_valid;
+			session_tbl->smac_addr.uc[0] = (pppoe_session_ext1.bf.smac >> 24) & 0xff;
+			session_tbl->smac_addr.uc[1] = (pppoe_session_ext1.bf.smac >> 16) & 0xff;
+			session_tbl->smac_addr.uc[2] = (pppoe_session_ext1.bf.smac >> 8) & 0xff;
+			session_tbl->smac_addr.uc[3] = pppoe_session_ext1.bf.smac & 0xff;
+			session_tbl->smac_addr.uc[4] = (pppoe_session_ext.bf.smac >> 8) & 0xff;
+			session_tbl->smac_addr.uc[5] = pppoe_session_ext.bf.smac & 0xff;
+			return SW_OK;
+		}
+	}
+
+	return SW_NOT_FOUND;
+}
+
+sw_error_t
+adpt_hppe_pppoe_en_set(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union in_l3_if_tbl_u in_l3_if_tbl = {0};
+	union eg_l3_if_tbl_u eg_l3_if_tbl = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_in_l3_if_tbl_get(dev_id, l3_if, &in_l3_if_tbl);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = hppe_eg_l3_if_tbl_get(dev_id, l3_if, &eg_l3_if_tbl);
+	SW_RTN_ON_ERROR(rv);
+
+	in_l3_if_tbl.bf.pppoe_en = enable;
+	eg_l3_if_tbl.bf.pppoe_en = enable;
+
+	rv = hppe_in_l3_if_tbl_set(dev_id, l3_if, &in_l3_if_tbl);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = hppe_eg_l3_if_tbl_set(dev_id, l3_if, &eg_l3_if_tbl);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_pppoe_en_get(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	union in_l3_if_tbl_u in_l3_if_tbl = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	rv = hppe_in_l3_if_tbl_get(dev_id, l3_if, &in_l3_if_tbl);
+	SW_RTN_ON_ERROR(rv);
+
+	*enable = in_l3_if_tbl.bf.pppoe_en;
+
+	return rv;
+}
+
+void adpt_hppe_pppoe_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_pppoe_func_bitmap = 0x0;
+
+	return;
+}
+
+static void adpt_hppe_pppoe_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_pppoe_session_table_add = NULL;
+	p_adpt_api->adpt_pppoe_session_table_del = NULL;
+	p_adpt_api->adpt_pppoe_session_table_get = NULL;
+	p_adpt_api->adpt_pppoe_en_set = NULL;
+	p_adpt_api->adpt_pppoe_en_get = NULL;
+
+	return;
+}
+
+sw_error_t adpt_hppe_pppoe_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_pppoe_func_unregister(dev_id, p_adpt_api);
+
+	if (p_adpt_api->adpt_pppoe_func_bitmap & (1 << FUNC_PPPOE_SESSION_TABLE_ADD))
+		p_adpt_api->adpt_pppoe_session_table_add = adpt_hppe_pppoe_session_table_add;
+	if (p_adpt_api->adpt_pppoe_func_bitmap & (1 << FUNC_PPPOE_SESSION_TABLE_DEL))
+		p_adpt_api->adpt_pppoe_session_table_del = adpt_hppe_pppoe_session_table_del;
+	if (p_adpt_api->adpt_pppoe_func_bitmap & (1 << FUNC_PPPOE_SESSION_TABLE_GET))
+		p_adpt_api->adpt_pppoe_session_table_get = adpt_hppe_pppoe_session_table_get;
+	if (p_adpt_api->adpt_pppoe_func_bitmap & (1 << FUNC_PPPOE_EN_SET))
+		p_adpt_api->adpt_pppoe_en_set = adpt_hppe_pppoe_en_set;
+	if (p_adpt_api->adpt_pppoe_func_bitmap & (1 << FUNC_PPPOE_EN_GET))
+		p_adpt_api->adpt_pppoe_en_get = adpt_hppe_pppoe_en_get;
+
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_ptp.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_ptp.c
new file mode 100755
index 0000000..6e86261
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_ptp.c
@@ -0,0 +1,1382 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "adpt.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "hsl_phy.h"
+
+sw_error_t
+adpt_hppe_ptp_config_set(a_uint32_t dev_id, a_uint32_t port_id, fal_ptp_config_t *config)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(config);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_config_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_config_set(dev_id, phy_id, config);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_config_get(a_uint32_t dev_id, a_uint32_t port_id, fal_ptp_config_t *config)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(config);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_config_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_config_get(dev_id, phy_id, config);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_reference_clock_set(a_uint32_t dev_id, a_uint32_t port_id, fal_ptp_reference_clock_t ref_clock)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_reference_clock_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_reference_clock_set(dev_id, phy_id, ref_clock);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_reference_clock_get(a_uint32_t dev_id, a_uint32_t port_id, fal_ptp_reference_clock_t *ref_clock)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ref_clock);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_reference_clock_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_reference_clock_get(dev_id, phy_id, ref_clock);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_rx_timestamp_mode_set(a_uint32_t dev_id,
+			a_uint32_t port_id,
+			fal_ptp_rx_timestamp_mode_t ts_mode)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rx_timestamp_mode_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_rx_timestamp_mode_set(dev_id, phy_id, ts_mode);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_rx_timestamp_mode_get(a_uint32_t dev_id,
+			a_uint32_t port_id,
+			fal_ptp_rx_timestamp_mode_t *ts_mode)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ts_mode);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rx_timestamp_mode_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_rx_timestamp_mode_get(dev_id, phy_id, ts_mode);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_direction_t direction,
+			fal_ptp_pkt_info_t *pkt_info,
+			fal_ptp_time_t *time)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_timestamp_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_timestamp_get(dev_id, phy_id, direction, pkt_info, time);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_pkt_timestamp_set(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_time_t *time)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_pkt_timestamp_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_pkt_timestamp_set(dev_id, phy_id, time);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_pkt_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_time_t *time)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_pkt_timestamp_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_pkt_timestamp_get(dev_id, phy_id, time);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_grandmaster_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_grandmaster_mode_t *gm_mode)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(gm_mode);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_grandmaster_mode_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_grandmaster_mode_set(dev_id, phy_id, gm_mode);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_grandmaster_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_grandmaster_mode_t *gm_mode)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(gm_mode);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_grandmaster_mode_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_grandmaster_mode_get(dev_id, phy_id, gm_mode);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_rtc_time_get(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_time_t *time)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_time_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_time_get(dev_id, phy_id, time);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_rtc_time_set(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_time_t *time)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_time_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_time_set(dev_id, phy_id, time);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_rtc_time_clear(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_time_clear)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_time_clear(dev_id, phy_id);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_rtc_adjtime_set(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_time_t *time)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_adjtime_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_adjtime_set(dev_id, phy_id, time);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_rtc_adjfreq_set(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_time_t *time)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_adjfreq_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_adjfreq_set(dev_id, phy_id, time);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_rtc_adjfreq_get(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_time_t *time)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_adjfreq_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_adjfreq_get(dev_id, phy_id, time);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_link_delay_set(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_time_t *time)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_link_delay_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_link_delay_set(dev_id, phy_id, time);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_link_delay_get(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_time_t *time)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_link_delay_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_link_delay_get(dev_id, phy_id, time);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_security_set(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_security_t *sec)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(sec);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_security_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_security_set(dev_id, phy_id, sec);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_security_get(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_security_t *sec)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(sec);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_security_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_security_get(dev_id, phy_id, sec);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_pps_signal_control_set(a_uint32_t dev_id,
+			a_uint32_t port_id,
+			fal_ptp_pps_signal_control_t *sig_control)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(sig_control);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_pps_signal_control_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_pps_signal_control_set(dev_id, phy_id, sig_control);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_pps_signal_control_get(a_uint32_t dev_id,
+			a_uint32_t port_id,
+			fal_ptp_pps_signal_control_t *sig_control)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(sig_control);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_pps_signal_control_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_pps_signal_control_get(dev_id, phy_id, sig_control);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_rx_crc_recalc_enable(a_uint32_t dev_id, a_uint32_t port_id,
+			a_bool_t status)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rx_crc_recalc_enable)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_rx_crc_recalc_enable(dev_id, phy_id, status);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_rx_crc_recalc_status_get(a_uint32_t dev_id,
+			a_uint32_t port_id, a_bool_t *status)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(status);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rx_crc_recalc_status_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_rx_crc_recalc_status_get(dev_id, phy_id, status);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_asym_correction_set(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_asym_correction_t *asym_cf)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(asym_cf);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_asym_correction_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_asym_correction_set(dev_id, phy_id, asym_cf);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_asym_correction_get(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_asym_correction_t* asym_cf)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(asym_cf);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_asym_correction_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_asym_correction_get(dev_id, phy_id, asym_cf);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_output_waveform_set(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_output_waveform_t *waveform)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(waveform);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_output_waveform_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_output_waveform_set(dev_id, phy_id, waveform);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_output_waveform_get(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_output_waveform_t *waveform)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(waveform);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_output_waveform_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_output_waveform_get(dev_id, phy_id, waveform);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_rtc_time_snapshot_enable(a_uint32_t dev_id,
+			a_uint32_t port_id, a_bool_t status)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_time_snapshot_enable)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_time_snapshot_enable(dev_id, phy_id, status);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_rtc_time_snapshot_status_get(a_uint32_t dev_id,
+			a_uint32_t port_id, a_bool_t *status)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(status);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_time_snapshot_status_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_time_snapshot_status_get(dev_id, phy_id, status);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_increment_sync_from_clock_enable(a_uint32_t dev_id,
+			a_uint32_t port_id, a_bool_t status)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_increment_sync_from_clock_enable)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_increment_sync_from_clock_enable(dev_id, phy_id, status);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_increment_sync_from_clock_status_get(a_uint32_t dev_id,
+			a_uint32_t port_id, a_bool_t *status)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(status);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_increment_sync_from_clock_status_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_increment_sync_from_clock_status_get(dev_id,
+			phy_id, status);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_tod_uart_set(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_tod_uart_t *tod_uart)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(tod_uart);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_tod_uart_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_tod_uart_set(dev_id, phy_id, tod_uart);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_tod_uart_get(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_tod_uart_t *tod_uart)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(tod_uart);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_tod_uart_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_tod_uart_get(dev_id, phy_id, tod_uart);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_enhanced_timestamp_engine_set(a_uint32_t dev_id,
+			a_uint32_t port_id, fal_ptp_direction_t direction,
+			fal_ptp_enhanced_ts_engine_t *ts_engine)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ts_engine);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_enhanced_timestamp_engine_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_enhanced_timestamp_engine_set(dev_id,
+			phy_id, direction, ts_engine);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_enhanced_timestamp_engine_get(a_uint32_t dev_id,
+			a_uint32_t port_id, fal_ptp_direction_t direction,
+			fal_ptp_enhanced_ts_engine_t *ts_engine)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ts_engine);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_enhanced_timestamp_engine_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_enhanced_timestamp_engine_get(dev_id,
+			phy_id, direction, ts_engine);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_trigger_set(a_uint32_t dev_id, a_uint32_t port_id,
+			a_uint32_t trigger_id, fal_ptp_trigger_t *triger)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(triger);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_trigger_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_trigger_set(dev_id, phy_id, trigger_id, triger);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_trigger_get(a_uint32_t dev_id, a_uint32_t port_id,
+			a_uint32_t trigger_id, fal_ptp_trigger_t *triger)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(triger);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_trigger_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_trigger_get(dev_id, phy_id, trigger_id, triger);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_capture_set(a_uint32_t dev_id, a_uint32_t port_id,
+			a_uint32_t capture_id, fal_ptp_capture_t *capture)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(capture);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_capture_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_capture_set(dev_id, phy_id, capture_id, capture);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_capture_get(a_uint32_t dev_id, a_uint32_t port_id,
+			a_uint32_t capture_id, fal_ptp_capture_t *capture)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(capture);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_capture_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_capture_get(dev_id, phy_id, capture_id, capture);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_interrupt_set(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_interrupt_t *interrupt)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(interrupt);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_interrupt_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_interrupt_set(dev_id, phy_id, interrupt);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ptp_interrupt_get(a_uint32_t dev_id, a_uint32_t port_id,
+			fal_ptp_interrupt_t *interrupt)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(interrupt);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_ptp_ops.phy_ptp_interrupt_get)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_ptp_ops.phy_ptp_interrupt_get(dev_id, phy_id, interrupt);
+
+	return rv;
+}
+
+sw_error_t adpt_hppe_ptp_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+	{
+		return SW_FAIL;
+	}
+
+	p_adpt_api->adpt_ptp_config_set = adpt_hppe_ptp_config_set;
+	p_adpt_api->adpt_ptp_config_get = adpt_hppe_ptp_config_get;
+	p_adpt_api->adpt_ptp_reference_clock_set = adpt_hppe_ptp_reference_clock_set;
+	p_adpt_api->adpt_ptp_reference_clock_get = adpt_hppe_ptp_reference_clock_get;
+	p_adpt_api->adpt_ptp_rx_timestamp_mode_set = adpt_hppe_ptp_rx_timestamp_mode_set;
+	p_adpt_api->adpt_ptp_rx_timestamp_mode_get = adpt_hppe_ptp_rx_timestamp_mode_get;
+	p_adpt_api->adpt_ptp_timestamp_get = adpt_hppe_ptp_timestamp_get;
+	p_adpt_api->adpt_ptp_pkt_timestamp_set = adpt_hppe_ptp_pkt_timestamp_set;
+	p_adpt_api->adpt_ptp_pkt_timestamp_get = adpt_hppe_ptp_pkt_timestamp_get;
+	p_adpt_api->adpt_ptp_grandmaster_mode_set = adpt_hppe_ptp_grandmaster_mode_set;
+	p_adpt_api->adpt_ptp_grandmaster_mode_get = adpt_hppe_ptp_grandmaster_mode_get;
+	p_adpt_api->adpt_ptp_rtc_time_set = adpt_hppe_ptp_rtc_time_set;
+	p_adpt_api->adpt_ptp_rtc_time_get = adpt_hppe_ptp_rtc_time_get;
+	p_adpt_api->adpt_ptp_rtc_time_clear = adpt_hppe_ptp_rtc_time_clear;
+	p_adpt_api->adpt_ptp_rtc_adjtime_set = adpt_hppe_ptp_rtc_adjtime_set;
+	p_adpt_api->adpt_ptp_rtc_adjfreq_set = adpt_hppe_ptp_rtc_adjfreq_set;
+	p_adpt_api->adpt_ptp_rtc_adjfreq_get = adpt_hppe_ptp_rtc_adjfreq_get;
+	p_adpt_api->adpt_ptp_link_delay_set = adpt_hppe_ptp_link_delay_set;
+	p_adpt_api->adpt_ptp_link_delay_get = adpt_hppe_ptp_link_delay_get;
+	p_adpt_api->adpt_ptp_security_set = adpt_hppe_ptp_security_set;
+	p_adpt_api->adpt_ptp_security_get = adpt_hppe_ptp_security_get;
+	p_adpt_api->adpt_ptp_pps_signal_control_set = adpt_hppe_ptp_pps_signal_control_set;
+	p_adpt_api->adpt_ptp_pps_signal_control_get = adpt_hppe_ptp_pps_signal_control_get;
+	p_adpt_api->adpt_ptp_rx_crc_recalc_enable = adpt_hppe_ptp_rx_crc_recalc_enable;
+	p_adpt_api->adpt_ptp_rx_crc_recalc_status_get = adpt_hppe_ptp_rx_crc_recalc_status_get;
+	p_adpt_api->adpt_ptp_asym_correction_set = adpt_hppe_ptp_asym_correction_set;
+	p_adpt_api->adpt_ptp_asym_correction_get = adpt_hppe_ptp_asym_correction_get;
+	p_adpt_api->adpt_ptp_output_waveform_set = adpt_hppe_ptp_output_waveform_set;
+	p_adpt_api->adpt_ptp_output_waveform_get = adpt_hppe_ptp_output_waveform_get;
+	p_adpt_api->adpt_ptp_rtc_time_snapshot_enable = adpt_hppe_ptp_rtc_time_snapshot_enable;
+	p_adpt_api->adpt_ptp_tod_uart_set = adpt_hppe_ptp_tod_uart_set;
+	p_adpt_api->adpt_ptp_tod_uart_get = adpt_hppe_ptp_tod_uart_get;
+	p_adpt_api->adpt_ptp_trigger_set = adpt_hppe_ptp_trigger_set;
+	p_adpt_api->adpt_ptp_trigger_get = adpt_hppe_ptp_trigger_get;
+	p_adpt_api->adpt_ptp_capture_set = adpt_hppe_ptp_capture_set;
+	p_adpt_api->adpt_ptp_capture_get = adpt_hppe_ptp_capture_get;
+	p_adpt_api->adpt_ptp_interrupt_set = adpt_hppe_ptp_interrupt_set;
+	p_adpt_api->adpt_ptp_interrupt_get = adpt_hppe_ptp_interrupt_get;
+	p_adpt_api->adpt_ptp_rtc_time_snapshot_status_get =
+		adpt_hppe_ptp_rtc_time_snapshot_status_get;
+	p_adpt_api->adpt_ptp_increment_sync_from_clock_enable =
+		adpt_hppe_ptp_increment_sync_from_clock_enable;
+	p_adpt_api->adpt_ptp_increment_sync_from_clock_status_get =
+		adpt_hppe_ptp_increment_sync_from_clock_status_get;
+	p_adpt_api->adpt_ptp_enhanced_timestamp_engine_set =
+		adpt_hppe_ptp_enhanced_timestamp_engine_set;
+	p_adpt_api->adpt_ptp_enhanced_timestamp_engine_get =
+		adpt_hppe_ptp_enhanced_timestamp_engine_get;
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_qm.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_qm.c
new file mode 100755
index 0000000..9c33c19
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_qm.c
@@ -0,0 +1,1413 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "fal_qm.h"
+#include "hppe_reg_access.h"
+#include "hppe_qm_reg.h"
+#include "hppe_qm.h"
+#include "hppe_qos_reg.h"
+#include "hppe_qos.h"
+#include "hppe_portvlan_reg.h"
+#include "hppe_portvlan.h"
+#include "hppe_portctrl_reg.h"
+#include "hppe_portctrl.h"
+#include "adpt.h"
+#include "adpt_hppe.h"
+#if defined(CPPE)
+#include "adpt_cppe_qm.h"
+#endif
+
+#define SERVICE_CODE_QUEUE_OFFSET   2048
+#define CPU_CODE_QUEUE_OFFSET         1024
+#define VP_PORT_QUEUE_OFFSET            0
+
+#define UCAST_QUEUE_ID_MAX	256
+#define ALL_QUEUE_ID_MAX	300
+#define MCAST_QUEUE_PORT7_START	296
+#define MCAST_QUEUE_PORT6_START	292
+#define MCAST_QUEUE_PORT5_START	288
+#define MCAST_QUEUE_PORT4_START	284
+#define MCAST_QUEUE_PORT3_START	280
+#define MCAST_QUEUE_PORT2_START	276
+#define MCAST_QUEUE_PORT1_START	272
+#define MCAST_QUEUE_PORT0_START	256
+#define MCAST_QUEUE_OFFSET	(3*0x10)
+#define UCAST_QUEUE_ITEMS	6
+#define MCAST_QUEUE_ITEMS	3
+#define DROP_INC	0x10
+
+#ifndef IN_QM_MINI
+sw_error_t
+adpt_hppe_ucast_hash_map_set(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t rss_hash,
+		a_int8_t queue_hash)
+{
+	union ucast_hash_map_tbl_u ucast_hash_map_tbl;
+	a_uint32_t index = 0;
+
+	memset(&ucast_hash_map_tbl, 0, sizeof(ucast_hash_map_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	index = profile << 8 | rss_hash;
+	ucast_hash_map_tbl.bf.hash = queue_hash;
+	
+	return hppe_ucast_hash_map_tbl_set(dev_id, index, &ucast_hash_map_tbl);
+}
+
+sw_error_t
+adpt_hppe_ac_dynamic_threshold_get(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		fal_ac_dynamic_threshold_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+	union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl;
+
+	memset(&ac_uni_queue_cfg_tbl, 0, sizeof(ac_uni_queue_cfg_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+
+	rv = hppe_ac_uni_queue_cfg_tbl_get(dev_id, queue_id, &ac_uni_queue_cfg_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	cfg->wred_enable = ac_uni_queue_cfg_tbl.bf.ac_cfg_wred_en;
+	cfg->color_enable = ac_uni_queue_cfg_tbl.bf.ac_cfg_color_aware;
+	cfg->shared_weight = ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_weight;
+	cfg->green_min_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_grn_min;
+	cfg->yel_max_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_max;
+	cfg->yel_min_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_0 | \
+					ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_1 << 10;
+	cfg->red_max_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_max;
+	cfg->red_min_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_min;
+	cfg->green_resume_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_grn_resume_offset;
+	cfg->yel_resume_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset;
+	cfg->red_resume_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_0 | \
+					ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_1 << 9;
+	cfg->ceiling = ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_ceiling;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ucast_queue_base_profile_get(
+		a_uint32_t dev_id,
+		fal_ucast_queue_dest_t *queue_dest,
+		a_uint32_t *queue_base, a_uint8_t *profile)
+{
+	sw_error_t rv = SW_OK;
+	union ucast_queue_map_tbl_u ucast_queue_map_tbl;
+	a_uint32_t index = 0;
+
+	memset(&ucast_queue_map_tbl, 0, sizeof(ucast_queue_map_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(queue_dest);
+	ADPT_NULL_POINT_CHECK(queue_base);
+	ADPT_NULL_POINT_CHECK(profile);
+
+	if (queue_dest ->service_code_en) {
+		index = SERVICE_CODE_QUEUE_OFFSET + (queue_dest->src_profile << 8) \
+				+ queue_dest->service_code;
+	} else if (queue_dest ->cpu_code_en) {
+		index = CPU_CODE_QUEUE_OFFSET + (queue_dest->src_profile << 8) \
+				+ queue_dest->cpu_code;
+	} else {
+		index = VP_PORT_QUEUE_OFFSET + (queue_dest->src_profile << 8) \
+				+ queue_dest->dst_port;
+	}
+
+	rv = hppe_ucast_queue_map_tbl_get(dev_id, index, &ucast_queue_map_tbl);
+	if (rv)
+		return rv;
+	*queue_base = ucast_queue_map_tbl.bf.queue_id;
+	*profile = ucast_queue_map_tbl.bf.profile_id;
+	
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_mcast_priority_class_get(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint8_t priority,
+		a_uint8_t *queue_class)
+{
+	sw_error_t rv = SW_OK;
+	union mcast_priority_map0_u mcast_priority_map0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(queue_class);
+
+
+	if (port == 0){
+		rv = hppe_mcast_priority_map0_get(dev_id, priority, &mcast_priority_map0);
+	} else if (port == 1) {
+		rv = hppe_mcast_priority_map1_get(dev_id, priority,
+					(union mcast_priority_map1_u *)&mcast_priority_map0);
+	} else if (port == 2) {
+		rv = hppe_mcast_priority_map2_get(dev_id, priority,
+					(union mcast_priority_map2_u *)&mcast_priority_map0);
+	} else if (port == 3) {
+		rv = hppe_mcast_priority_map3_get(dev_id, priority,
+					(union mcast_priority_map3_u *)&mcast_priority_map0);
+	} else if (port == 4) {
+		rv = hppe_mcast_priority_map4_get(dev_id, priority,
+					(union mcast_priority_map4_u *)&mcast_priority_map0);
+	} else if (port == 5) {
+		rv = hppe_mcast_priority_map5_get(dev_id, priority,
+					(union mcast_priority_map5_u *)&mcast_priority_map0);
+	} else if (port == 6) {
+		rv = hppe_mcast_priority_map6_get(dev_id, priority,
+					(union mcast_priority_map6_u *)&mcast_priority_map0);
+	} else if (port == 7) {
+		rv = hppe_mcast_priority_map7_get(dev_id, priority,
+					(union mcast_priority_map7_u *)&mcast_priority_map0);
+	}
+
+	if( rv != SW_OK )
+		return rv;
+
+	*queue_class = mcast_priority_map0.bf.class;
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+adpt_hppe_ac_dynamic_threshold_set(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		fal_ac_dynamic_threshold_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+	union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl;
+
+	memset(&ac_uni_queue_cfg_tbl, 0, sizeof(ac_uni_queue_cfg_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+
+	rv = hppe_ac_uni_queue_cfg_tbl_get(dev_id, queue_id, &ac_uni_queue_cfg_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	ac_uni_queue_cfg_tbl.bf.ac_cfg_wred_en = cfg->wred_enable;
+	ac_uni_queue_cfg_tbl.bf.ac_cfg_color_aware = cfg->color_enable;
+	ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_dynamic = 1;
+	ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_grn_min = cfg->green_min_off;
+	ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_max = cfg->yel_max_off;
+	ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_0 = cfg->yel_min_off;
+	ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_1 = cfg->yel_min_off >> 20;
+	ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_max = cfg->red_max_off;
+	ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_min = cfg->red_min_off;
+	ac_uni_queue_cfg_tbl.bf.ac_cfg_grn_resume_offset = cfg->green_resume_off;
+	ac_uni_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset = cfg->yel_resume_off;
+	ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_0 = cfg->red_resume_off;
+	ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_1 = cfg->red_resume_off >> 9;
+	ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_weight = cfg->shared_weight;
+	ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_ceiling = cfg->ceiling;
+
+	return hppe_ac_uni_queue_cfg_tbl_set(dev_id, queue_id, &ac_uni_queue_cfg_tbl);
+}
+
+sw_error_t
+adpt_hppe_ac_prealloc_buffer_set(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		a_uint16_t num)
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (obj->type == FAL_AC_GROUP) {
+		union ac_grp_cfg_tbl_u ac_grp_cfg_tbl;
+
+		memset(&ac_grp_cfg_tbl, 0, sizeof(ac_grp_cfg_tbl));
+		hppe_ac_grp_cfg_tbl_get(dev_id, obj->obj_id, &ac_grp_cfg_tbl);
+
+		ac_grp_cfg_tbl.bf.ac_grp_palloc_limit = num;
+
+		return hppe_ac_grp_cfg_tbl_set(dev_id, obj->obj_id, &ac_grp_cfg_tbl);
+		
+	} else if (obj->type == FAL_AC_QUEUE) {
+		if (obj->obj_id < UCAST_QUEUE_ID_MAX) {
+			union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl;
+			hppe_ac_uni_queue_cfg_tbl_get(dev_id,
+					obj->obj_id,
+					&ac_uni_queue_cfg_tbl);
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_pre_alloc_limit = num;
+			return hppe_ac_uni_queue_cfg_tbl_set(dev_id,
+					obj->obj_id,
+					&ac_uni_queue_cfg_tbl);;
+			
+		} else {
+			union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl;
+			hppe_ac_mul_queue_cfg_tbl_get(dev_id,
+					obj->obj_id - UCAST_QUEUE_ID_MAX,
+					&ac_mul_queue_cfg_tbl);
+			ac_mul_queue_cfg_tbl.bf.ac_cfg_pre_alloc_limit = num;
+			return hppe_ac_mul_queue_cfg_tbl_set(dev_id,
+					obj->obj_id -UCAST_QUEUE_ID_MAX,
+					&ac_mul_queue_cfg_tbl);
+		}
+	} else
+		return SW_FAIL;
+}
+#ifndef IN_QM_MINI
+sw_error_t
+adpt_hppe_ucast_default_hash_get(
+		a_uint32_t dev_id,
+		a_uint8_t *hash_value)
+{
+	sw_error_t rv = SW_OK;
+	union ucast_default_hash_u ucast_default_hash;
+
+	memset(&ucast_default_hash, 0, sizeof(ucast_default_hash));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(hash_value);
+
+	rv = hppe_ucast_default_hash_get(dev_id, &ucast_default_hash);
+	if( rv != SW_OK )
+		return rv;
+	
+	*hash_value = ucast_default_hash.bf.hash;
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_ucast_default_hash_set(
+		a_uint32_t dev_id,
+		a_uint8_t hash_value)
+{
+	sw_error_t rv = SW_OK;
+	union ucast_default_hash_u ucast_default_hash;
+
+	memset(&ucast_default_hash, 0, sizeof(ucast_default_hash));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	ucast_default_hash.bf.hash = hash_value;
+	rv = hppe_ucast_default_hash_set(dev_id, &ucast_default_hash);
+	
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ac_queue_group_get(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_uint8_t *group_id)
+{
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(group_id);
+
+
+	if (queue_id < UCAST_QUEUE_ID_MAX) {
+		union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl;
+		rv = hppe_ac_uni_queue_cfg_tbl_get(dev_id,
+				queue_id,
+				&ac_uni_queue_cfg_tbl);
+		*group_id = ac_uni_queue_cfg_tbl.bf.ac_cfg_grp_id;
+		
+	} else {
+		union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl;
+		rv = hppe_ac_mul_queue_cfg_tbl_get(dev_id,
+				queue_id - UCAST_QUEUE_ID_MAX,
+				&ac_mul_queue_cfg_tbl);
+		*group_id = ac_mul_queue_cfg_tbl.bf.ac_cfg_grp_id;
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ac_ctrl_get(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_ctrl_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+
+	if (obj->type == FAL_AC_GROUP) {
+		union ac_grp_cfg_tbl_u ac_grp_cfg_tbl;
+
+		memset(&ac_grp_cfg_tbl, 0, sizeof(ac_grp_cfg_tbl));
+		rv = hppe_ac_grp_cfg_tbl_get(dev_id, obj->obj_id, &ac_grp_cfg_tbl);
+
+		cfg->ac_en = ac_grp_cfg_tbl.bf.ac_cfg_ac_en;
+		cfg->ac_fc_en = ac_grp_cfg_tbl.bf.ac_cfg_force_ac_en;
+	} else if (obj->type == FAL_AC_QUEUE) {
+		if (obj->obj_id < UCAST_QUEUE_ID_MAX) {
+			union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl;
+			rv = hppe_ac_uni_queue_cfg_tbl_get(dev_id,
+					obj->obj_id,
+					&ac_uni_queue_cfg_tbl);
+			cfg->ac_en = ac_uni_queue_cfg_tbl.bf.ac_cfg_ac_en;
+			cfg->ac_fc_en = ac_uni_queue_cfg_tbl.bf.ac_cfg_force_ac_en;
+			
+		} else {
+			union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl;
+			rv = hppe_ac_mul_queue_cfg_tbl_get(dev_id,
+					obj->obj_id - UCAST_QUEUE_ID_MAX,
+					&ac_mul_queue_cfg_tbl);
+			cfg->ac_en = ac_mul_queue_cfg_tbl.bf.ac_cfg_ac_en;
+			cfg->ac_fc_en = ac_mul_queue_cfg_tbl.bf.ac_cfg_force_ac_en;
+		}
+	} else
+		return SW_FAIL;
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ac_prealloc_buffer_get(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		a_uint16_t *num)
+{
+	sw_error_t rv = SW_OK;
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(num);
+
+	if (obj->type == FAL_AC_GROUP) {
+		union ac_grp_cfg_tbl_u ac_grp_cfg_tbl;
+
+		rv = hppe_ac_grp_cfg_tbl_get(dev_id, obj->obj_id, &ac_grp_cfg_tbl);
+
+		*num = ac_grp_cfg_tbl.bf.ac_grp_palloc_limit;
+
+		return rv;
+		
+	} else if (obj->type == FAL_AC_QUEUE) {
+		if (obj->obj_id < UCAST_QUEUE_ID_MAX) {
+			union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl;
+			rv = hppe_ac_uni_queue_cfg_tbl_get(dev_id,
+					obj->obj_id,
+					&ac_uni_queue_cfg_tbl);
+			*num = ac_uni_queue_cfg_tbl.bf.ac_cfg_pre_alloc_limit;
+		} else {
+			union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl;
+			rv = hppe_ac_mul_queue_cfg_tbl_get(dev_id,
+					obj->obj_id - UCAST_QUEUE_ID_MAX,
+					&ac_mul_queue_cfg_tbl);
+			*num = ac_mul_queue_cfg_tbl.bf.ac_cfg_pre_alloc_limit;
+		}
+		return rv;
+	} else
+		return SW_FAIL;
+}
+
+sw_error_t
+adpt_hppe_port_mcast_priority_class_set(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint8_t priority,
+		a_uint8_t queue_class)
+{
+	sw_error_t rv = SW_OK;
+	union mcast_priority_map0_u mcast_priority_map0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	mcast_priority_map0.bf.class = queue_class;
+	
+	if (port == 0){
+		rv = hppe_mcast_priority_map0_set(dev_id, priority, &mcast_priority_map0);
+	} else if (port == 1) {
+		rv = hppe_mcast_priority_map1_set(dev_id, priority,
+					(union mcast_priority_map1_u *)&mcast_priority_map0);
+	} else if (port == 2) {
+		rv = hppe_mcast_priority_map2_set(dev_id, priority,
+					(union mcast_priority_map2_u *)&mcast_priority_map0);
+	} else if (port == 3) {
+		rv = hppe_mcast_priority_map3_set(dev_id, priority,
+					(union mcast_priority_map3_u *)&mcast_priority_map0);
+	} else if (port == 4) {
+		rv = hppe_mcast_priority_map4_set(dev_id, priority,
+					(union mcast_priority_map4_u *)&mcast_priority_map0);
+	} else if (port == 5) {
+		rv = hppe_mcast_priority_map5_set(dev_id, priority,
+					(union mcast_priority_map5_u *)&mcast_priority_map0);
+	} else if (port == 6) {
+		rv = hppe_mcast_priority_map6_set(dev_id, priority,
+					(union mcast_priority_map6_u *)&mcast_priority_map0);
+	} else if (port == 7) {
+		rv = hppe_mcast_priority_map7_set(dev_id, priority,
+					(union mcast_priority_map7_u *)&mcast_priority_map0);
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_ucast_hash_map_get(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t rss_hash,
+		a_int8_t *queue_hash)
+{
+	union ucast_hash_map_tbl_u ucast_hash_map_tbl;
+	sw_error_t rv = SW_OK;
+	a_uint32_t index = 0;
+
+	memset(&ucast_hash_map_tbl, 0, sizeof(ucast_hash_map_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	index = profile << 8 | rss_hash;
+	
+	rv = hppe_ucast_hash_map_tbl_get(dev_id, index, &ucast_hash_map_tbl);
+	if (rv)
+		return rv;
+
+	*queue_hash = ucast_hash_map_tbl.bf.hash;
+	return rv;
+}
+#endif
+
+sw_error_t
+adpt_hppe_ac_static_threshold_set(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_static_threshold_t *cfg)
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (obj->type == FAL_AC_GROUP) {
+		union ac_grp_cfg_tbl_u ac_grp_cfg_tbl;
+
+		hppe_ac_grp_cfg_tbl_get(dev_id, obj->obj_id, &ac_grp_cfg_tbl);
+
+		ac_grp_cfg_tbl.bf.ac_cfg_color_aware = cfg->color_enable;
+		ac_grp_cfg_tbl.bf.ac_grp_dp_thrd_0 = cfg->green_max;
+		ac_grp_cfg_tbl.bf.ac_grp_dp_thrd_1 = cfg->green_max >> 7;
+		ac_grp_cfg_tbl.bf.ac_grp_gap_grn_yel = cfg->yel_max_off;
+		ac_grp_cfg_tbl.bf.ac_grp_gap_grn_red = cfg->red_max_off;
+		ac_grp_cfg_tbl.bf.ac_grp_grn_resume_offset = cfg->green_resume_off;
+		ac_grp_cfg_tbl.bf.ac_grp_yel_resume_offset_0 = cfg->yel_resume_off;
+		ac_grp_cfg_tbl.bf.ac_grp_yel_resume_offset_1 = cfg->yel_resume_off >> 6;
+		ac_grp_cfg_tbl.bf.ac_grp_red_resume_offset = cfg->red_resume_off;
+
+		return hppe_ac_grp_cfg_tbl_set(dev_id, obj->obj_id, &ac_grp_cfg_tbl);
+		
+	} else if (obj->type == FAL_AC_QUEUE) {
+		if (obj->obj_id < UCAST_QUEUE_ID_MAX) {
+			union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl;
+			hppe_ac_uni_queue_cfg_tbl_get(dev_id,
+					obj->obj_id,
+					&ac_uni_queue_cfg_tbl);
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_wred_en = cfg->wred_enable;
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_color_aware = cfg->color_enable;
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_dynamic = 0;
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_grn_min = cfg->green_min_off;
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_max = cfg->yel_max_off;
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_0 = cfg->yel_min_off;
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_1 = cfg->yel_min_off >> 10;
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_max = cfg->red_max_off;
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_min = cfg->red_min_off;
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_grn_resume_offset = cfg->green_resume_off;
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset = cfg->yel_resume_off;
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_0 = cfg->red_resume_off;
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_1 = cfg->red_resume_off >> 9;
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_ceiling = cfg->green_max;
+			return hppe_ac_uni_queue_cfg_tbl_set(dev_id,
+					obj->obj_id,
+					&ac_uni_queue_cfg_tbl);;
+			
+		} else {
+			union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl;
+			hppe_ac_mul_queue_cfg_tbl_get(dev_id,
+					obj->obj_id - UCAST_QUEUE_ID_MAX,
+					&ac_mul_queue_cfg_tbl);
+			ac_mul_queue_cfg_tbl.bf.ac_cfg_color_aware = cfg->color_enable;
+			ac_mul_queue_cfg_tbl.bf.ac_cfg_grn_resume_offset = cfg->green_resume_off;
+			ac_mul_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset_0 = cfg->yel_resume_off;
+			ac_mul_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset_1 = cfg->yel_resume_off >> 4;
+			ac_mul_queue_cfg_tbl.bf.ac_cfg_red_resume_offset = cfg->red_resume_off;
+			ac_mul_queue_cfg_tbl.bf.ac_cfg_gap_grn_red = cfg->red_max_off;
+			ac_mul_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_0 = cfg->yel_max_off;
+			ac_mul_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_1 = cfg->yel_max_off >> 5;
+			ac_mul_queue_cfg_tbl.bf.ac_cfg_shared_ceiling = cfg->green_max;
+			return hppe_ac_mul_queue_cfg_tbl_set(dev_id,
+					obj->obj_id -UCAST_QUEUE_ID_MAX,
+					&ac_mul_queue_cfg_tbl);
+		}
+	} else
+		return SW_FAIL;
+}
+
+sw_error_t
+adpt_hppe_ac_queue_group_set(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_uint8_t group_id)
+{
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+
+	if (queue_id < UCAST_QUEUE_ID_MAX) {
+		union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl;
+		hppe_ac_uni_queue_cfg_tbl_get(dev_id,
+				queue_id,
+				&ac_uni_queue_cfg_tbl);
+		ac_uni_queue_cfg_tbl.bf.ac_cfg_grp_id = group_id;
+		return hppe_ac_uni_queue_cfg_tbl_set(dev_id,
+				queue_id,
+				&ac_uni_queue_cfg_tbl);
+		
+	} else {
+		union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl;
+		hppe_ac_mul_queue_cfg_tbl_get(dev_id,
+				queue_id - UCAST_QUEUE_ID_MAX,
+				&ac_mul_queue_cfg_tbl);
+		ac_mul_queue_cfg_tbl.bf.ac_cfg_grp_id = group_id;
+		return hppe_ac_mul_queue_cfg_tbl_set(dev_id,
+				queue_id - UCAST_QUEUE_ID_MAX,
+				&ac_mul_queue_cfg_tbl);
+	}
+
+	return rv;
+}
+
+#ifndef IN_QM_MINI
+sw_error_t
+adpt_hppe_ac_group_buffer_get(
+		a_uint32_t dev_id,
+		a_uint8_t group_id,
+		fal_ac_group_buffer_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+	union ac_grp_cfg_tbl_u ac_grp_cfg_tbl;
+
+	memset(&ac_grp_cfg_tbl, 0, sizeof(ac_grp_cfg_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+
+	rv = hppe_ac_grp_cfg_tbl_get(dev_id, group_id, &ac_grp_cfg_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	cfg->prealloc_buffer = ac_grp_cfg_tbl.bf.ac_grp_palloc_limit;
+	cfg->total_buffer = ac_grp_cfg_tbl.bf.ac_grp_limit;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_mcast_cpu_code_class_get(
+		a_uint32_t dev_id,
+		a_uint8_t cpu_code,
+		a_uint8_t *queue_class)
+{
+	sw_error_t rv = SW_OK;
+	union mcast_queue_map_tbl_u mcast_queue_map_tbl;
+
+	memset(&mcast_queue_map_tbl, 0, sizeof(mcast_queue_map_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(queue_class);
+
+	rv = hppe_mcast_queue_map_tbl_get(dev_id, cpu_code, &mcast_queue_map_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	*queue_class = mcast_queue_map_tbl.bf.class;
+
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+adpt_hppe_ac_ctrl_set(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_ctrl_t *cfg)
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+
+	if (obj->type == FAL_AC_GROUP) {
+		union ac_grp_cfg_tbl_u ac_grp_cfg_tbl;
+
+		memset(&ac_grp_cfg_tbl, 0, sizeof(ac_grp_cfg_tbl));
+		hppe_ac_grp_cfg_tbl_get(dev_id, obj->obj_id, &ac_grp_cfg_tbl);
+
+		ac_grp_cfg_tbl.bf.ac_cfg_ac_en = cfg->ac_en;
+		ac_grp_cfg_tbl.bf.ac_cfg_force_ac_en = cfg->ac_fc_en;
+		return hppe_ac_grp_cfg_tbl_set(dev_id, obj->obj_id, &ac_grp_cfg_tbl);
+	} else if (obj->type == FAL_AC_QUEUE) {
+		if (obj->obj_id < UCAST_QUEUE_ID_MAX) {
+			union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl;
+			hppe_ac_uni_queue_cfg_tbl_get(dev_id,
+					obj->obj_id,
+					&ac_uni_queue_cfg_tbl);
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_ac_en = cfg->ac_en;
+			ac_uni_queue_cfg_tbl.bf.ac_cfg_force_ac_en = cfg->ac_fc_en;
+			return hppe_ac_uni_queue_cfg_tbl_set(dev_id,
+					obj->obj_id,
+					&ac_uni_queue_cfg_tbl);
+			
+		} else {
+			union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl;
+			hppe_ac_mul_queue_cfg_tbl_get(dev_id,
+					obj->obj_id - UCAST_QUEUE_ID_MAX,
+					&ac_mul_queue_cfg_tbl);
+			ac_mul_queue_cfg_tbl.bf.ac_cfg_ac_en = cfg->ac_en;
+			ac_mul_queue_cfg_tbl.bf.ac_cfg_force_ac_en = cfg->ac_fc_en;
+			return hppe_ac_mul_queue_cfg_tbl_set(dev_id,
+					obj->obj_id - UCAST_QUEUE_ID_MAX,
+					&ac_mul_queue_cfg_tbl);
+		}
+	} else
+		return SW_FAIL;
+
+}
+
+#ifndef IN_QM_MINI
+sw_error_t
+adpt_hppe_ucast_priority_class_get(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t priority,
+		a_uint8_t *class)
+{
+	sw_error_t rv = SW_OK;
+	union ucast_priority_map_tbl_u ucast_priority_map_tbl;
+	a_uint32_t index = 0;
+
+	memset(&ucast_priority_map_tbl, 0, sizeof(ucast_priority_map_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(class);
+
+	index = profile << 4 | priority;
+	rv = hppe_ucast_priority_map_tbl_get(dev_id, index, &ucast_priority_map_tbl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*class = ucast_priority_map_tbl.bf.class;
+	return rv;
+}
+#endif
+
+sw_error_t
+adpt_hppe_queue_flush(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint16_t queue_id)
+{
+	union flush_cfg_u flush_cfg;
+	a_uint32_t i = 0x100;
+	sw_error_t rv;
+
+	memset(&flush_cfg, 0, sizeof(flush_cfg));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	#if 0
+	/* disable queue firstly */
+	if (queue_id == 0xffff) {
+		/* all queue in this port */
+		a_uint32_t i, j, k, tmp;
+		enq.bf.enq_disable = 1;
+		deq.bf.deq_dis = 1;
+		p_api = adpt_api_ptr_get(0);
+		if (!p_api || !p_api->adpt_port_queues_get)
+			return SW_FAIL;
+		p_api->adpt_port_queues_get(dev_id, port, &queue_bmp);
+		for (i = 0; i < ALL_QUEUE_ID_MAX; i++) {
+			j = i / 32;
+			k = i % 32;
+			tmp = queue_bmp.bmp[j];
+			if ((tmp & (1 << k)) == 0)
+				continue;
+			hppe_oq_enq_opr_tbl_set(dev_id, i, &enq);
+			hppe_deq_dis_tbl_set(dev_id, i, &deq);
+		}
+	} else {
+		/* single queue in this port */
+		enq.bf.enq_disable = 1;
+		deq.bf.deq_dis = 1;
+		if (queue_id >= ALL_QUEUE_ID_MAX)
+			return SW_BAD_VALUE;
+		hppe_oq_enq_opr_tbl_set(dev_id, queue_id, &enq);
+		hppe_deq_dis_tbl_set(dev_id, queue_id, &deq);
+	}
+	#endif
+
+	hppe_flush_cfg_get(dev_id, &flush_cfg);
+
+	if (queue_id == 0xffff) {
+		flush_cfg.bf.flush_all_queues = 1;
+		flush_cfg.bf.flush_qid = 0;
+		i = 0x1000;
+	}
+	else {
+		flush_cfg.bf.flush_all_queues = 0;
+		flush_cfg.bf.flush_qid = queue_id;
+	}
+	flush_cfg.bf.flush_dst_port = port;
+	flush_cfg.bf.flush_busy = 1;
+	
+	hppe_flush_cfg_set(dev_id, &flush_cfg);
+	rv = hppe_flush_cfg_get(dev_id, &flush_cfg);
+	if (SW_OK != rv)
+		return rv;
+	while (flush_cfg.bf.flush_busy && --i) {
+		hppe_flush_cfg_get(dev_id, &flush_cfg);
+	}
+	if (i == 0)
+		return SW_BUSY;
+	if (!flush_cfg.bf.flush_status)
+		return SW_FAIL;
+
+	#if 0
+	/* enable queue again */
+	if (queue_id == 0xffff) {
+		/* all queue in this port */
+		a_uint32_t i, j, k, tmp;
+		enq.bf.enq_disable = 0;
+		deq.bf.deq_dis = 0;
+		for (i = 0; i < ALL_QUEUE_ID_MAX; i++) {
+			j = i / 32;
+			k = i % 32;
+			tmp = queue_bmp.bmp[j];
+			if ((tmp & (1 << k)) == 0)
+				continue;
+			hppe_oq_enq_opr_tbl_set(dev_id, i, &enq);
+			hppe_deq_dis_tbl_set(dev_id, i, &deq);
+		}
+	} else {
+		/* single queue in this port */
+		enq.bf.enq_disable = 0;
+		deq.bf.deq_dis = 0;
+		hppe_oq_enq_opr_tbl_set(dev_id, queue_id, &enq);
+		hppe_deq_dis_tbl_set(dev_id, queue_id, &deq);
+	}
+	#endif
+	return SW_OK;
+}
+
+#ifndef IN_QM_MINI
+sw_error_t
+adpt_hppe_mcast_cpu_code_class_set(
+		a_uint32_t dev_id,
+		a_uint8_t cpu_code,
+		a_uint8_t queue_class)
+{
+	union mcast_queue_map_tbl_u mcast_queue_map_tbl;
+
+	memset(&mcast_queue_map_tbl, 0, sizeof(mcast_queue_map_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	mcast_queue_map_tbl.bf.class = queue_class;
+	return hppe_mcast_queue_map_tbl_set(dev_id, cpu_code, &mcast_queue_map_tbl);
+}
+
+sw_error_t
+adpt_hppe_ucast_priority_class_set(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t priority,
+		a_uint8_t class)
+{
+	union ucast_priority_map_tbl_u ucast_priority_map_tbl;
+	a_int32_t index = 0;
+
+	memset(&ucast_priority_map_tbl, 0, sizeof(ucast_priority_map_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	index = profile << 4 | priority;
+	ucast_priority_map_tbl.bf.class = class;
+	
+	return hppe_ucast_priority_map_tbl_set(dev_id, index, &ucast_priority_map_tbl);
+}
+
+sw_error_t
+adpt_hppe_ac_static_threshold_get(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_static_threshold_t *cfg)
+{
+	sw_error_t rv;
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (obj->type == FAL_AC_GROUP) {
+		union ac_grp_cfg_tbl_u ac_grp_cfg_tbl;
+
+		rv = hppe_ac_grp_cfg_tbl_get(dev_id, obj->obj_id, &ac_grp_cfg_tbl);
+
+		cfg->color_enable = ac_grp_cfg_tbl.bf.ac_cfg_color_aware;
+		cfg->green_max = ac_grp_cfg_tbl.bf.ac_grp_dp_thrd_0 |
+					ac_grp_cfg_tbl.bf.ac_grp_dp_thrd_1 << 7;
+		cfg->yel_max_off = ac_grp_cfg_tbl.bf.ac_grp_gap_grn_yel;
+		cfg->red_max_off = ac_grp_cfg_tbl.bf.ac_grp_gap_grn_red;
+		cfg->green_resume_off = ac_grp_cfg_tbl.bf.ac_grp_grn_resume_offset;
+		cfg->yel_resume_off = ac_grp_cfg_tbl.bf.ac_grp_yel_resume_offset_0 |
+					ac_grp_cfg_tbl.bf.ac_grp_yel_resume_offset_1 << 6;
+		cfg->red_resume_off = ac_grp_cfg_tbl.bf.ac_grp_red_resume_offset;
+
+		return rv;
+		
+	} else if (obj->type == FAL_AC_QUEUE) {
+		if (obj->obj_id < UCAST_QUEUE_ID_MAX) {
+			union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl;
+			rv = hppe_ac_uni_queue_cfg_tbl_get(dev_id,
+					obj->obj_id,
+					&ac_uni_queue_cfg_tbl);
+			cfg->wred_enable = ac_uni_queue_cfg_tbl.bf.ac_cfg_wred_en;
+			cfg->color_enable = ac_uni_queue_cfg_tbl.bf.ac_cfg_color_aware;
+			cfg->green_min_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_grn_min;
+			cfg->yel_max_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_max;
+			cfg->yel_min_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_0 |
+					ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_1 << 10;
+			cfg->red_max_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_max;
+			cfg->red_min_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_min;
+			cfg->green_resume_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_grn_resume_offset;
+			cfg->yel_resume_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset;
+			cfg->red_resume_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_0 |
+					ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_1 << 9;
+			cfg->green_max = ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_ceiling;
+			return rv;
+			
+		} else {
+			union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl;
+			rv = hppe_ac_mul_queue_cfg_tbl_get(dev_id,
+					obj->obj_id - UCAST_QUEUE_ID_MAX,
+					&ac_mul_queue_cfg_tbl);
+			cfg->color_enable = ac_mul_queue_cfg_tbl.bf.ac_cfg_color_aware;
+			cfg->green_max = ac_mul_queue_cfg_tbl.bf.ac_cfg_shared_ceiling;
+			cfg->red_max_off = ac_mul_queue_cfg_tbl.bf.ac_cfg_gap_grn_red;
+			cfg->yel_max_off= ac_mul_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_0 |
+						ac_mul_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_1 << 5;
+			cfg->green_resume_off = ac_mul_queue_cfg_tbl.bf.ac_cfg_grn_resume_offset;
+			cfg->yel_resume_off = ac_mul_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset_0 |
+					ac_mul_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset_1 << 4;
+			cfg->red_resume_off = ac_mul_queue_cfg_tbl.bf.ac_cfg_red_resume_offset;
+
+			return rv;
+		}
+	} else
+		return SW_FAIL;
+}
+#endif
+
+sw_error_t
+adpt_hppe_ucast_queue_base_profile_set(
+		a_uint32_t dev_id,
+		fal_ucast_queue_dest_t *queue_dest,
+		a_uint32_t queue_base, a_uint8_t profile)
+{
+	union ucast_queue_map_tbl_u ucast_queue_map_tbl;
+	a_uint32_t index = 0;
+
+	memset(&ucast_queue_map_tbl, 0, sizeof(ucast_queue_map_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(queue_dest);
+
+	if (queue_dest ->service_code_en) {
+		index = SERVICE_CODE_QUEUE_OFFSET + (queue_dest->src_profile << 8) \
+				+ queue_dest->service_code;
+	} else if (queue_dest ->cpu_code_en) {
+		index = CPU_CODE_QUEUE_OFFSET + (queue_dest->src_profile << 8) \
+				+ queue_dest->cpu_code;
+	} else {
+		index = VP_PORT_QUEUE_OFFSET + (queue_dest->src_profile << 8) \
+				+ queue_dest->dst_port;
+	}
+
+	ucast_queue_map_tbl.bf.queue_id = queue_base;
+	ucast_queue_map_tbl.bf.profile_id = profile;
+	
+	return hppe_ucast_queue_map_tbl_set(dev_id, index, &ucast_queue_map_tbl);
+}
+
+sw_error_t
+adpt_hppe_ac_group_buffer_set(
+		a_uint32_t dev_id,
+		a_uint8_t group_id,
+		fal_ac_group_buffer_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+	union ac_grp_cfg_tbl_u ac_grp_cfg_tbl;
+
+	memset(&ac_grp_cfg_tbl, 0, sizeof(ac_grp_cfg_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+
+	rv = hppe_ac_grp_cfg_tbl_get(dev_id, group_id, &ac_grp_cfg_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	ac_grp_cfg_tbl.bf.ac_grp_palloc_limit = cfg->prealloc_buffer;
+	ac_grp_cfg_tbl.bf.ac_grp_limit = cfg->total_buffer;
+
+	return hppe_ac_grp_cfg_tbl_set(dev_id, group_id, &ac_grp_cfg_tbl);;
+}
+
+#ifndef IN_QM_MINI
+static a_uint32_t
+adpt_hppe_mcast_queue_dropcnt_start_addr_get(a_uint32_t queue_id)
+{
+	a_uint32_t start_addr = QUEUE_MANAGER_BASE_ADDR;
+
+	if (queue_id >= MCAST_QUEUE_PORT7_START) {
+		start_addr += MUL_P7_DROP_CNT_TBL_ADDRESS;
+		start_addr += (queue_id - MCAST_QUEUE_PORT7_START)*MCAST_QUEUE_OFFSET;
+	} else if (queue_id >= MCAST_QUEUE_PORT6_START) {
+		start_addr += MUL_P6_DROP_CNT_TBL_ADDRESS;
+		start_addr += (queue_id - MCAST_QUEUE_PORT6_START)*MCAST_QUEUE_OFFSET;
+	} else if (queue_id >= MCAST_QUEUE_PORT5_START) {
+		start_addr += MUL_P5_DROP_CNT_TBL_ADDRESS;
+		start_addr += (queue_id - MCAST_QUEUE_PORT5_START)*MCAST_QUEUE_OFFSET;
+	} else if (queue_id >= MCAST_QUEUE_PORT4_START) {
+		start_addr += MUL_P4_DROP_CNT_TBL_ADDRESS;
+		start_addr += (queue_id - MCAST_QUEUE_PORT4_START)*MCAST_QUEUE_OFFSET;
+	} else if (queue_id >= MCAST_QUEUE_PORT3_START) {
+		start_addr += MUL_P3_DROP_CNT_TBL_ADDRESS;
+		start_addr += (queue_id - MCAST_QUEUE_PORT3_START)*MCAST_QUEUE_OFFSET;
+	} else if (queue_id >= MCAST_QUEUE_PORT2_START) {
+		start_addr += MUL_P2_DROP_CNT_TBL_ADDRESS;
+		start_addr += (queue_id - MCAST_QUEUE_PORT2_START)*MCAST_QUEUE_OFFSET;
+	} else if (queue_id >= MCAST_QUEUE_PORT1_START) {
+		start_addr += MUL_P1_DROP_CNT_TBL_ADDRESS;
+		start_addr += (queue_id - MCAST_QUEUE_PORT1_START)*MCAST_QUEUE_OFFSET;
+	}  else if (queue_id >= MCAST_QUEUE_PORT0_START) {
+		start_addr += MUL_P0_DROP_CNT_TBL_ADDRESS;
+		start_addr += (queue_id - MCAST_QUEUE_PORT0_START)*MCAST_QUEUE_OFFSET;
+	}
+
+	return start_addr;
+}
+
+sw_error_t
+adpt_hppe_queue_counter_cleanup(a_uint32_t dev_id, a_uint32_t queue_id)
+{
+	union queue_tx_counter_tbl_u tx_cnt;
+	a_uint32_t i = 0;
+	a_uint32_t val[3] = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (queue_id >= ALL_QUEUE_ID_MAX)
+		return SW_BAD_VALUE;
+
+	tx_cnt.bf.tx_packets = 0;
+	tx_cnt.bf.tx_bytes_0 = 0;
+	tx_cnt.bf.tx_bytes_1 = 0;
+
+	hppe_queue_tx_counter_tbl_set(dev_id, queue_id, &tx_cnt);
+
+	if (queue_id >= UCAST_QUEUE_ID_MAX) {
+		a_uint32_t start_addr = 0;
+
+		start_addr = adpt_hppe_mcast_queue_dropcnt_start_addr_get(queue_id);
+		for (i = 0; i < MCAST_QUEUE_ITEMS; i++) {
+			hppe_reg_tbl_set(dev_id, start_addr + i*DROP_INC, val, 3);
+		}
+	} else {
+		union uni_drop_cnt_tbl_u uni_drop_cnt;
+
+		memset(&uni_drop_cnt, 0, sizeof(uni_drop_cnt));
+		for (i = 0; i < UCAST_QUEUE_ITEMS; i++) {
+			hppe_uni_drop_cnt_tbl_set(dev_id, queue_id*UCAST_QUEUE_ITEMS+i, &uni_drop_cnt);
+		}
+	}
+
+	return SW_OK;
+}
+sw_error_t
+adpt_hppe_queue_counter_get(a_uint32_t dev_id, a_uint32_t queue_id, fal_queue_stats_t *info)
+{
+	sw_error_t rv = SW_OK;
+	union queue_tx_counter_tbl_u tx_cnt;
+	union ac_mul_queue_cnt_tbl_u mul_cnt;
+	union ac_uni_queue_cnt_tbl_u uni_cnt;
+	a_uint32_t i = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(info);
+
+	if (queue_id >= ALL_QUEUE_ID_MAX)
+		return SW_BAD_VALUE;
+
+	rv = hppe_queue_tx_counter_tbl_get(dev_id, queue_id, &tx_cnt);
+	if( rv != SW_OK )
+		return rv;
+	if (queue_id >= UCAST_QUEUE_ID_MAX) {
+		a_uint32_t start_addr = 0;
+		union mul_p7_drop_cnt_tbl_u drop_cnt;
+
+		rv = hppe_ac_mul_queue_cnt_tbl_get(dev_id,
+				queue_id - UCAST_QUEUE_ID_MAX, &mul_cnt);
+		if( rv != SW_OK )
+			return rv;
+		info->pending_buff_num = mul_cnt.bf.ac_mul_queue_cnt;
+		start_addr = adpt_hppe_mcast_queue_dropcnt_start_addr_get(queue_id);
+		for (i = 0; i < MCAST_QUEUE_ITEMS; i++) {
+			hppe_reg_tbl_get(dev_id, start_addr + i*DROP_INC, drop_cnt.val, 3);
+			info->drop_packets[i+3] = drop_cnt.bf.mul_p7_drop_pkt;
+			info->drop_bytes[i+3] = (a_uint64_t)drop_cnt.bf.mul_p7_drop_byte_0 |
+					(a_uint64_t)drop_cnt.bf.mul_p7_drop_byte_1 <<32;
+		}
+	} else {
+		union uni_drop_cnt_tbl_u uni_drop_cnt;
+
+		rv = hppe_ac_uni_queue_cnt_tbl_get(dev_id, queue_id, &uni_cnt);
+		if( rv != SW_OK )
+			return rv;
+		info->pending_buff_num = uni_cnt.bf.ac_uni_queue_cnt;
+		for (i = 0; i < UCAST_QUEUE_ITEMS; i++) {
+			hppe_uni_drop_cnt_tbl_get(dev_id, queue_id*UCAST_QUEUE_ITEMS+i, &uni_drop_cnt);
+			info->drop_packets[i] = uni_drop_cnt.bf.uni_drop_pkt;
+			info->drop_bytes[i] = (a_uint64_t)uni_drop_cnt.bf.uni_drop_byte_0 |
+					(a_uint64_t)uni_drop_cnt.bf.uni_drop_byte_1 <<32;
+		}
+	}
+	info->tx_packets = tx_cnt.bf.tx_packets;
+	info->tx_bytes = (a_uint64_t)tx_cnt.bf.tx_bytes_0 | (a_uint64_t)tx_cnt.bf.tx_bytes_1 << 32;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_queue_counter_ctrl_get(a_uint32_t dev_id, a_bool_t *cnt_en)
+{
+	sw_error_t rv = SW_OK;
+	union eg_bridge_config_u eg_bridge_config;
+
+	memset(&eg_bridge_config, 0, sizeof(eg_bridge_config));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cnt_en);
+
+	rv = hppe_eg_bridge_config_get(dev_id, &eg_bridge_config);
+	if( rv != SW_OK )
+		return rv;
+
+	*cnt_en = eg_bridge_config.bf.queue_cnt_en;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_queue_counter_ctrl_set(a_uint32_t dev_id, a_bool_t cnt_en)
+{
+	sw_error_t rv = SW_OK;
+	union eg_bridge_config_u eg_bridge_config;
+
+	memset(&eg_bridge_config, 0, sizeof(eg_bridge_config));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+
+	rv = hppe_eg_bridge_config_get(dev_id, &eg_bridge_config);
+	if( rv != SW_OK )
+		return rv;
+
+	eg_bridge_config.bf.queue_cnt_en = cnt_en;
+	return hppe_eg_bridge_config_set(dev_id, &eg_bridge_config);
+}
+#endif
+
+sw_error_t
+adpt_hppe_qm_enqueue_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_bool_t enable)
+{
+	union oq_enq_opr_tbl_u enq;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	memset(&enq, 0, sizeof(enq));
+
+	enq.bf.enq_disable = !enable;
+	return hppe_oq_enq_opr_tbl_set(dev_id, queue_id, &enq);
+}
+
+#ifndef IN_QM_MINI
+sw_error_t
+adpt_hppe_qm_enqueue_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	union oq_enq_opr_tbl_u enq;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	memset(&enq, 0, sizeof(enq));
+
+	rv = hppe_oq_enq_opr_tbl_get(dev_id, queue_id, &enq);
+	if( rv != SW_OK )
+		return rv;
+
+	*enable = !(enq.bf.enq_disable);
+
+	return SW_OK;
+}
+
+static sw_error_t
+adpt_hppe_qm_port_source_profile_set(
+		a_uint32_t dev_id, fal_port_t port, a_uint32_t src_profile)
+{
+	union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;
+	a_uint32_t index = FAL_PORT_ID_VALUE(port);
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl));
+
+
+	return hppe_mru_mtu_ctrl_tbl_src_profile_set(dev_id, index,
+				src_profile);
+}
+
+sw_error_t
+adpt_ppe_qm_port_source_profile_set(
+		a_uint32_t dev_id, fal_port_t port, a_uint32_t src_profile)
+{
+	a_uint32_t chip_ver = 0;
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_qm_port_source_profile_set(dev_id, port,
+				src_profile);
+#endif
+	} else {
+		return adpt_hppe_qm_port_source_profile_set(dev_id, port,
+				src_profile);
+	}
+
+	return SW_NOT_SUPPORTED;
+}
+
+static sw_error_t
+adpt_hppe_qm_port_source_profile_get(
+		a_uint32_t dev_id, fal_port_t port, a_uint32_t *src_profile)
+{
+	union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;
+	a_uint32_t index = FAL_PORT_ID_VALUE(port);
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(src_profile);
+	memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl));
+
+	return hppe_mru_mtu_ctrl_tbl_src_profile_get(dev_id, index,
+				src_profile);
+}
+
+sw_error_t
+adpt_ppe_qm_port_source_profile_get(
+		a_uint32_t dev_id, fal_port_t port, a_uint32_t *src_profile)
+{
+	a_uint32_t chip_ver = 0;
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_qm_port_source_profile_get(dev_id, port,
+				src_profile);
+#endif
+	} else {
+		return adpt_hppe_qm_port_source_profile_get(dev_id, port,
+				src_profile);
+	}
+
+	return SW_NOT_SUPPORTED;
+}
+#endif
+
+void adpt_hppe_qm_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_qm_func_bitmap[0] = ((1 << FUNC_UCAST_HASH_MAP_SET) |
+						(1 << FUNC_AC_DYNAMIC_THRESHOLD_GET) |
+						(1 << FUNC_UCAST_QUEUE_BASE_PROFILE_GET) |
+						(1 << FUNC_PORT_MCAST_PRIORITY_CLASS_GET) |
+						(1 << FUNC_AC_DYNAMIC_THRESHOLD_SET) |
+						(1 << FUNC_AC_PREALLOC_BUFFER_SET) |
+						(1 << FUNC_UCAST_DEFAULT_HASH_GET) |
+						(1 << FUNC_UCAST_DEFAULT_HASH_SET) |
+						(1 << FUNC_AC_QUEUE_GROUP_GET) |
+						(1 << FUNC_AC_CTRL_GET) |
+						(1 << FUNC_AC_PREALLOC_BUFFER_GET) |
+						(1 << FUNC_PORT_MCAST_PRIORITY_CLASS_SET) |
+						(1 << FUNC_UCAST_HASH_MAP_GET) |
+						(1 << FUNC_AC_STATIC_THRESHOLD_SET) |
+						(1 << FUNC_AC_QUEUE_GROUP_SET) |
+						(1 << FUNC_AC_GROUP_BUFFER_GET) |
+						(1 << FUNC_MCAST_CPU_CODE_CLASS_GET) |
+						(1 << FUNC_AC_CTRL_SET) |
+						(1 << FUNC_UCAST_PRIORITY_CLASS_GET) |
+						(1 << FUNC_QUEUE_FLUSH) |
+						(1 << FUNC_MCAST_CPU_CODE_CLASS_SET) |
+						(1 << FUNC_UCAST_PRIORITY_CLASS_SET) |
+						(1 << FUNC_AC_STATIC_THRESHOLD_GET) |
+						(1 << FUNC_UCAST_QUEUE_BASE_PROFILE_SET) |
+						(1 << FUNC_AC_GROUP_BUFFER_SET) |
+						(1 << FUNC_QUEUE_COUNTER_CLEANUP) |
+						(1 << FUNC_QUEUE_COUNTER_GET) |
+						(1 << FUNC_QUEUE_COUNTER_CTRL_GET) |
+						(1 << FUNC_QUEUE_COUNTER_CTRL_SET) |
+						(1 << FUNC_QM_ENQUEUE_CTRL_GET) |
+						(1 << FUNC_QM_ENQUEUE_CTRL_SET) |
+						(1 << FUNC_QM_PORT_SRCPROFILE_GET));
+	p_adpt_api->adpt_qm_func_bitmap[1] = 1 << (FUNC_QM_PORT_SRCPROFILE_SET % 32);
+	return;
+}
+
+static void adpt_hppe_qm_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_ucast_hash_map_set = NULL;
+	p_adpt_api->adpt_ac_dynamic_threshold_get = NULL;
+	p_adpt_api->adpt_ucast_queue_base_profile_get = NULL;
+	p_adpt_api->adpt_port_mcast_priority_class_get = NULL;
+	p_adpt_api->adpt_ac_dynamic_threshold_set = NULL;
+	p_adpt_api->adpt_ac_prealloc_buffer_set = NULL;
+	p_adpt_api->adpt_ucast_default_hash_get = NULL;
+	p_adpt_api->adpt_ucast_default_hash_set = NULL;
+	p_adpt_api->adpt_ac_queue_group_get = NULL;
+	p_adpt_api->adpt_ac_ctrl_get = NULL;
+	p_adpt_api->adpt_ac_prealloc_buffer_get = NULL;
+	p_adpt_api->adpt_port_mcast_priority_class_set = NULL;
+	p_adpt_api->adpt_ucast_hash_map_get = NULL;
+	p_adpt_api->adpt_ac_static_threshold_set = NULL;
+	p_adpt_api->adpt_ac_queue_group_set = NULL;
+	p_adpt_api->adpt_ac_group_buffer_get = NULL;
+	p_adpt_api->adpt_mcast_cpu_code_class_get = NULL;
+	p_adpt_api->adpt_ac_ctrl_set = NULL;
+	p_adpt_api->adpt_ucast_priority_class_get = NULL;
+	p_adpt_api->adpt_queue_flush = NULL;
+	p_adpt_api->adpt_mcast_cpu_code_class_set = NULL;
+	p_adpt_api->adpt_ucast_priority_class_set = NULL;
+	p_adpt_api->adpt_ac_static_threshold_get = NULL;
+	p_adpt_api->adpt_ucast_queue_base_profile_set = NULL;
+	p_adpt_api->adpt_ac_group_buffer_set = NULL;
+	p_adpt_api->adpt_queue_counter_cleanup = NULL;
+	p_adpt_api->adpt_queue_counter_get = NULL;
+	p_adpt_api->adpt_queue_counter_ctrl_get = NULL;
+	p_adpt_api->adpt_queue_counter_ctrl_set = NULL;
+	p_adpt_api->adpt_qm_enqueue_ctrl_set = NULL;
+	p_adpt_api->adpt_qm_enqueue_ctrl_get = NULL;
+	p_adpt_api->adpt_qm_port_source_profile_get = NULL;
+	p_adpt_api->adpt_qm_port_source_profile_set = NULL;
+
+	return;
+}
+
+sw_error_t adpt_hppe_qm_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_qm_func_unregister(dev_id, p_adpt_api);
+
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_CTRL_SET))
+		p_adpt_api->adpt_ac_ctrl_set = adpt_hppe_ac_ctrl_set;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_PREALLOC_BUFFER_SET))
+		p_adpt_api->adpt_ac_prealloc_buffer_set = adpt_hppe_ac_prealloc_buffer_set;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_QUEUE_GROUP_SET))
+		p_adpt_api->adpt_ac_queue_group_set = adpt_hppe_ac_queue_group_set;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_STATIC_THRESHOLD_SET))
+		p_adpt_api->adpt_ac_static_threshold_set = adpt_hppe_ac_static_threshold_set;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_DYNAMIC_THRESHOLD_SET))
+		p_adpt_api->adpt_ac_dynamic_threshold_set = adpt_hppe_ac_dynamic_threshold_set;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_GROUP_BUFFER_SET))
+		p_adpt_api->adpt_ac_group_buffer_set = adpt_hppe_ac_group_buffer_set;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_QUEUE_BASE_PROFILE_SET))
+		p_adpt_api->adpt_ucast_queue_base_profile_set =
+			adpt_hppe_ucast_queue_base_profile_set;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QUEUE_FLUSH))
+		p_adpt_api->adpt_queue_flush = adpt_hppe_queue_flush;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QM_ENQUEUE_CTRL_SET))
+		p_adpt_api->adpt_qm_enqueue_ctrl_set = adpt_hppe_qm_enqueue_ctrl_set;
+#ifndef IN_QM_MINI
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_HASH_MAP_SET))
+		p_adpt_api->adpt_ucast_hash_map_set = adpt_hppe_ucast_hash_map_set;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_DYNAMIC_THRESHOLD_GET))
+		p_adpt_api->adpt_ac_dynamic_threshold_get = adpt_hppe_ac_dynamic_threshold_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_QUEUE_BASE_PROFILE_GET))
+		p_adpt_api->adpt_ucast_queue_base_profile_get =
+			adpt_hppe_ucast_queue_base_profile_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_PORT_MCAST_PRIORITY_CLASS_GET))
+		p_adpt_api->adpt_port_mcast_priority_class_get =
+			adpt_hppe_port_mcast_priority_class_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_DEFAULT_HASH_GET))
+		p_adpt_api->adpt_ucast_default_hash_get = adpt_hppe_ucast_default_hash_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_DEFAULT_HASH_SET))
+		p_adpt_api->adpt_ucast_default_hash_set = adpt_hppe_ucast_default_hash_set;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_QUEUE_GROUP_GET))
+		p_adpt_api->adpt_ac_queue_group_get = adpt_hppe_ac_queue_group_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_CTRL_GET))
+		p_adpt_api->adpt_ac_ctrl_get = adpt_hppe_ac_ctrl_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_PREALLOC_BUFFER_GET))
+		p_adpt_api->adpt_ac_prealloc_buffer_get = adpt_hppe_ac_prealloc_buffer_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_PORT_MCAST_PRIORITY_CLASS_SET))
+		p_adpt_api->adpt_port_mcast_priority_class_set =
+			adpt_hppe_port_mcast_priority_class_set;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_HASH_MAP_GET))
+		p_adpt_api->adpt_ucast_hash_map_get = adpt_hppe_ucast_hash_map_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_GROUP_BUFFER_GET))
+		p_adpt_api->adpt_ac_group_buffer_get = adpt_hppe_ac_group_buffer_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_MCAST_CPU_CODE_CLASS_GET))
+		p_adpt_api->adpt_mcast_cpu_code_class_get = adpt_hppe_mcast_cpu_code_class_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_PRIORITY_CLASS_GET))
+		p_adpt_api->adpt_ucast_priority_class_get = adpt_hppe_ucast_priority_class_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_MCAST_CPU_CODE_CLASS_SET))
+		p_adpt_api->adpt_mcast_cpu_code_class_set = adpt_hppe_mcast_cpu_code_class_set;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_PRIORITY_CLASS_SET))
+		p_adpt_api->adpt_ucast_priority_class_set = adpt_hppe_ucast_priority_class_set;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_STATIC_THRESHOLD_GET))
+		p_adpt_api->adpt_ac_static_threshold_get = adpt_hppe_ac_static_threshold_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QUEUE_COUNTER_CLEANUP))
+		p_adpt_api->adpt_queue_counter_cleanup = adpt_hppe_queue_counter_cleanup;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QUEUE_COUNTER_GET))
+		p_adpt_api->adpt_queue_counter_get = adpt_hppe_queue_counter_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QUEUE_COUNTER_CTRL_GET))
+		p_adpt_api->adpt_queue_counter_ctrl_get = adpt_hppe_queue_counter_ctrl_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QUEUE_COUNTER_CTRL_SET))
+		p_adpt_api->adpt_queue_counter_ctrl_set = adpt_hppe_queue_counter_ctrl_set;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QM_ENQUEUE_CTRL_GET))
+		p_adpt_api->adpt_qm_enqueue_ctrl_get = adpt_hppe_qm_enqueue_ctrl_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QM_PORT_SRCPROFILE_GET))
+		p_adpt_api->adpt_qm_port_source_profile_get = adpt_ppe_qm_port_source_profile_get;
+	if (p_adpt_api->adpt_qm_func_bitmap[1] & (1 << (FUNC_QM_PORT_SRCPROFILE_SET % 32)))
+		p_adpt_api->adpt_qm_port_source_profile_set = adpt_ppe_qm_port_source_profile_set;
+#endif
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_qos.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_qos.c
new file mode 100644
index 0000000..ca48de6
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_qos.c
@@ -0,0 +1,1235 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "ssdk_dts.h"
+#include "fal_qos.h"
+#include "hppe_qos_reg.h"
+#include "hppe_qos.h"
+#include "hppe_shaper_reg.h"
+#include "hppe_shaper.h"
+#include "adpt.h"
+#include "adpt_hppe.h"
+#if defined(CPPE)
+#include "adpt_cppe_qos.h"
+#endif
+
+static fal_queue_bmp_t port_queue_map[8] = {0};
+
+sw_error_t
+adpt_hppe_l1_flow_map_get(a_uint32_t dev_id,
+					a_uint32_t node_id,
+					fal_port_t *port_id,
+					fal_qos_scheduler_cfg_t *scheduler_cfg)
+{
+	union l1_flow_map_tbl_u l1_flow_map_tbl;
+	union l1_c_sp_cfg_tbl_u l1_c_sp_cfg_tbl;
+	union l1_e_sp_cfg_tbl_u l1_e_sp_cfg_tbl;
+	union l1_flow_port_map_tbl_u port_map;
+	union l1_comp_cfg_tbl_u l1_comp_cfg_tbl;
+	a_uint32_t c_sp_id, e_sp_id;
+
+	memset(&l1_flow_map_tbl, 0, sizeof(l1_flow_map_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(scheduler_cfg);
+	if (node_id >= L1_FLOW_MAP_TBL_MAX_ENTRY)
+		return SW_BAD_PARAM;
+
+	hppe_l1_flow_map_tbl_get(dev_id, node_id, &l1_flow_map_tbl);
+	scheduler_cfg->e_drr_wt = l1_flow_map_tbl.bf.e_drr_wt;
+	scheduler_cfg->c_drr_wt = l1_flow_map_tbl.bf.c_drr_wt;
+	scheduler_cfg->e_pri = l1_flow_map_tbl.bf.e_pri;
+	scheduler_cfg->c_pri = l1_flow_map_tbl.bf.c_pri;
+	scheduler_cfg->sp_id = l1_flow_map_tbl.bf.sp_id;
+	
+	c_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->c_pri;
+	hppe_l1_c_sp_cfg_tbl_get(dev_id, c_sp_id, &l1_c_sp_cfg_tbl);
+	scheduler_cfg->c_drr_unit = l1_c_sp_cfg_tbl.bf.drr_credit_unit;
+	scheduler_cfg->c_drr_id = l1_c_sp_cfg_tbl.bf.drr_id;
+
+	e_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->e_pri;
+	hppe_l1_e_sp_cfg_tbl_get(dev_id, e_sp_id, &l1_e_sp_cfg_tbl);
+	scheduler_cfg->e_drr_unit = l1_e_sp_cfg_tbl.bf.drr_credit_unit;
+	scheduler_cfg->e_drr_id = l1_e_sp_cfg_tbl.bf.drr_id;
+
+	hppe_l1_flow_port_map_tbl_get(dev_id, node_id, &port_map);
+	*port_id = port_map.bf.port_num;
+
+	hppe_l1_comp_cfg_tbl_get(dev_id, node_id, &l1_comp_cfg_tbl);
+	scheduler_cfg->drr_frame_mode = l1_comp_cfg_tbl.bf.drr_meter_len;
+
+	return SW_OK;
+}
+#ifndef IN_QOS_MINI
+sw_error_t
+adpt_hppe_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+				fal_qos_mode_t mode, a_uint32_t pri)
+{
+	union port_qos_ctrl_u port_qos_ctrl;
+
+	memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl);
+
+	if (mode == FAL_QOS_UP_MODE)
+		port_qos_ctrl.bf.port_pcp_qos_pri = pri;
+	else if (mode == FAL_QOS_DSCP_MODE)
+		port_qos_ctrl.bf.port_dscp_qos_pri = pri;
+	else if (mode == FAL_QOS_FLOW_MODE)
+		port_qos_ctrl.bf.port_flow_qos_pri = pri;
+	else
+		return SW_NOT_SUPPORTED;
+	
+	return hppe_port_qos_ctrl_set(dev_id, port_id, &port_qos_ctrl);
+}
+
+sw_error_t
+adpt_hppe_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+				fal_qos_mode_t mode, a_uint32_t *pri)
+{
+	union port_qos_ctrl_u port_qos_ctrl;
+
+	memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl);
+
+	if (mode == FAL_QOS_UP_MODE)
+		*pri = port_qos_ctrl.bf.port_pcp_qos_pri;
+	else if (mode == FAL_QOS_DSCP_MODE)
+		*pri = port_qos_ctrl.bf.port_dscp_qos_pri;
+	else if (mode == FAL_QOS_FLOW_MODE)
+		*pri = port_qos_ctrl.bf.port_flow_qos_pri;
+	else
+		return SW_NOT_SUPPORTED;
+	
+	return SW_OK;
+}
+#endif
+
+static sw_error_t
+adpt_hppe_qos_port_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_pri_precedence_t *pri)
+{
+	union port_qos_ctrl_u port_qos_ctrl;
+
+	memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(pri);
+
+	hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl);
+
+	port_qos_ctrl.bf.port_pcp_qos_pri = pri->pcp_pri;
+	port_qos_ctrl.bf.port_dscp_qos_pri = pri->dscp_pri;
+	port_qos_ctrl.bf.port_preheader_qos_pri = pri->preheader_pri;
+	port_qos_ctrl.bf.port_flow_qos_pri = pri->flow_pri;
+	port_qos_ctrl.bf.port_acl_qos_pri = pri->acl_pri;
+	
+	return hppe_port_qos_ctrl_set(dev_id, port_id, &port_qos_ctrl);
+}
+
+sw_error_t
+adpt_ppe_qos_port_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_pri_precedence_t *pri)
+{
+	a_uint32_t chip_ver = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(pri);
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_qos_port_pri_set(dev_id, port_id, pri);
+#endif
+	} else {
+		return adpt_hppe_qos_port_pri_set(dev_id, port_id, pri);
+	}
+
+	return SW_NOT_SUPPORTED;
+}
+
+static sw_error_t
+adpt_hppe_qos_port_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_pri_precedence_t *pri)
+{
+	sw_error_t rv = SW_OK;
+	union port_qos_ctrl_u port_qos_ctrl;
+
+	memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(pri);
+
+	rv = hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl);
+	if( rv != SW_OK )
+		return rv;
+
+	pri->pcp_pri = port_qos_ctrl.bf.port_pcp_qos_pri;
+	pri->dscp_pri = port_qos_ctrl.bf.port_dscp_qos_pri;
+	pri->preheader_pri = port_qos_ctrl.bf.port_preheader_qos_pri;
+	pri->flow_pri = port_qos_ctrl.bf.port_flow_qos_pri;
+	pri->acl_pri = port_qos_ctrl.bf.port_acl_qos_pri;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_ppe_qos_port_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_pri_precedence_t *pri)
+{
+	a_uint32_t chip_ver = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+        ADPT_NULL_POINT_CHECK(pri);
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_qos_port_pri_get(dev_id, port_id, pri);
+#endif
+	} else {
+		return adpt_hppe_qos_port_pri_get(dev_id, port_id, pri);
+	}
+
+	return SW_NOT_SUPPORTED;
+}
+
+static sw_error_t
+adpt_hppe_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t pcp, fal_qos_cosmap_t *cosmap)
+{
+	sw_error_t rv = SW_OK;
+	union pcp_qos_group_0_u pcp_qos_group_0;
+	union pcp_qos_group_1_u pcp_qos_group_1;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cosmap);
+
+	if (pcp >= PCP_QOS_GROUP_0_MAX_ENTRY)
+		return SW_BAD_PARAM;
+
+	if (group_id == 0) {
+		rv = hppe_pcp_qos_group_0_get(dev_id, pcp, &pcp_qos_group_0);
+		if( rv != SW_OK )
+			return rv;
+		cosmap->internal_pcp = pcp_qos_group_0.bf.qos_info & 7;
+		cosmap->internal_dei = (pcp_qos_group_0.bf.qos_info >> 3) & 1;
+		cosmap->internal_pri = (pcp_qos_group_0.bf.qos_info >> 4) & 0xf;
+		cosmap->internal_dscp = (pcp_qos_group_0.bf.qos_info >> 8) & 0x3f;
+		cosmap->internal_dp = (pcp_qos_group_0.bf.qos_info >> 14) & 0x3;
+	} else if (group_id == 1) {
+		rv = hppe_pcp_qos_group_1_get(dev_id, pcp, &pcp_qos_group_1);
+		if( rv != SW_OK )
+			return rv;
+		cosmap->internal_pcp = pcp_qos_group_1.bf.qos_info & 7;
+		cosmap->internal_dei = (pcp_qos_group_1.bf.qos_info >> 3) & 1;
+		cosmap->internal_pri = (pcp_qos_group_1.bf.qos_info >> 4) & 0xf;
+		cosmap->internal_dscp = (pcp_qos_group_1.bf.qos_info >> 8) & 0x3f;
+		cosmap->internal_dp = (pcp_qos_group_1.bf.qos_info >> 14) & 0x3;
+	} else
+		return SW_BAD_PARAM;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_ppe_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t pcp, fal_qos_cosmap_t *cosmap)
+{
+	a_uint32_t chip_ver = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+        ADPT_NULL_POINT_CHECK(cosmap);
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_qos_cosmap_pcp_get(dev_id, group_id,
+				pcp, cosmap);
+#endif
+	} else {
+		return adpt_hppe_qos_cosmap_pcp_get(dev_id, group_id,
+				pcp, cosmap);
+	}
+
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+adpt_hppe_l0_queue_map_set(a_uint32_t dev_id,
+					a_uint32_t node_id,
+					fal_port_t port_id,
+					fal_qos_scheduler_cfg_t *scheduler_cfg)
+{
+	union l0_flow_map_tbl_u l0_flow_map_tbl;
+	union l0_c_sp_cfg_tbl_u l0_c_sp_cfg_tbl;
+	union l0_e_sp_cfg_tbl_u l0_e_sp_cfg_tbl;
+	union l0_flow_port_map_tbl_u l0_flow_port_map_tbl;
+	union l0_comp_cfg_tbl_u l0_comp_cfg_tbl;
+	a_uint32_t c_sp_id, e_sp_id;
+	a_uint32_t i, j, k;
+
+	memset(&l0_flow_map_tbl, 0, sizeof(l0_flow_map_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(scheduler_cfg);
+	if (node_id >= L0_FLOW_MAP_TBL_MAX_ENTRY)
+		return SW_BAD_PARAM;
+
+	l0_flow_map_tbl.bf.e_drr_wt= scheduler_cfg->e_drr_wt;
+	l0_flow_map_tbl.bf.c_drr_wt = scheduler_cfg->c_drr_wt;
+	l0_flow_map_tbl.bf.e_pri = scheduler_cfg->e_pri;
+	l0_flow_map_tbl.bf.c_pri = scheduler_cfg->c_pri;
+	l0_flow_map_tbl.bf.sp_id = scheduler_cfg->sp_id;
+	hppe_l0_flow_map_tbl_set(dev_id, node_id, &l0_flow_map_tbl);
+
+	c_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->c_pri;
+	l0_c_sp_cfg_tbl.bf.drr_credit_unit = scheduler_cfg->c_drr_unit;
+	l0_c_sp_cfg_tbl.bf.drr_id = scheduler_cfg->c_drr_id;
+	hppe_l0_c_sp_cfg_tbl_set(dev_id, c_sp_id, &l0_c_sp_cfg_tbl);
+
+	e_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->e_pri;
+	l0_e_sp_cfg_tbl.bf.drr_credit_unit = scheduler_cfg->e_drr_unit;
+	l0_e_sp_cfg_tbl.bf.drr_id = scheduler_cfg->e_drr_id;
+	hppe_l0_e_sp_cfg_tbl_set(dev_id, e_sp_id, &l0_e_sp_cfg_tbl);
+
+	l0_flow_port_map_tbl.bf.port_num = port_id;
+	hppe_l0_flow_port_map_tbl_set(dev_id, node_id, &l0_flow_port_map_tbl);
+
+	hppe_l0_comp_cfg_tbl_get(dev_id, node_id, &l0_comp_cfg_tbl);
+	l0_comp_cfg_tbl.bf.drr_meter_len = scheduler_cfg->drr_frame_mode;
+	hppe_l0_comp_cfg_tbl_set(dev_id, node_id, &l0_comp_cfg_tbl);
+
+	i = node_id / 32;
+	j = node_id % 32;
+	port_queue_map[port_id].bmp[i] |= 1 << j;
+	for (k = 0; k < 8; k++) {
+		if (k != port_id) {
+			port_queue_map[k].bmp[i] &= ~(1 << j);
+		}
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_l0_queue_map_get(a_uint32_t dev_id,
+					a_uint32_t node_id,
+					fal_port_t *port_id,
+					fal_qos_scheduler_cfg_t *scheduler_cfg)
+{
+	union l0_flow_map_tbl_u l0_flow_map_tbl;
+	union l0_c_sp_cfg_tbl_u l0_c_sp_cfg_tbl;
+	union l0_e_sp_cfg_tbl_u l0_e_sp_cfg_tbl;
+	union l0_flow_port_map_tbl_u l0_flow_port_map_tbl;
+	union l0_comp_cfg_tbl_u l0_comp_cfg_tbl;
+	a_uint32_t c_sp_id, e_sp_id;
+
+	memset(&l0_flow_map_tbl, 0, sizeof(l0_flow_map_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(scheduler_cfg);
+	if (node_id >= L0_FLOW_MAP_TBL_MAX_ENTRY)
+		return SW_BAD_PARAM;
+
+	hppe_l0_flow_map_tbl_get(dev_id, node_id, &l0_flow_map_tbl);
+	scheduler_cfg->e_drr_wt = l0_flow_map_tbl.bf.e_drr_wt;
+	scheduler_cfg->c_drr_wt = l0_flow_map_tbl.bf.c_drr_wt;
+	scheduler_cfg->e_pri = l0_flow_map_tbl.bf.e_pri;
+	scheduler_cfg->c_pri = l0_flow_map_tbl.bf.c_pri;
+	scheduler_cfg->sp_id = l0_flow_map_tbl.bf.sp_id;
+	
+	c_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->c_pri;
+	hppe_l0_c_sp_cfg_tbl_get(dev_id, c_sp_id, &l0_c_sp_cfg_tbl);
+	scheduler_cfg->c_drr_unit = l0_c_sp_cfg_tbl.bf.drr_credit_unit;
+	scheduler_cfg->c_drr_id = l0_c_sp_cfg_tbl.bf.drr_id;
+
+	e_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->e_pri;
+	hppe_l0_e_sp_cfg_tbl_get(dev_id, e_sp_id, &l0_e_sp_cfg_tbl);
+	scheduler_cfg->e_drr_unit = l0_e_sp_cfg_tbl.bf.drr_credit_unit;
+	scheduler_cfg->e_drr_id = l0_e_sp_cfg_tbl.bf.drr_id;
+
+	hppe_l0_flow_port_map_tbl_get(dev_id, node_id, &l0_flow_port_map_tbl);
+	*port_id = l0_flow_port_map_tbl.bf.port_num;
+
+	hppe_l0_comp_cfg_tbl_get(dev_id, node_id, &l0_comp_cfg_tbl);
+	scheduler_cfg->drr_frame_mode = l0_comp_cfg_tbl.bf.drr_meter_len;
+
+	return SW_OK;
+}
+
+static sw_error_t
+adpt_hppe_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t pcp, fal_qos_cosmap_t *cosmap)
+{
+	sw_error_t rv = SW_OK;
+	union pcp_qos_group_0_u pcp_qos_group_0;
+	union pcp_qos_group_1_u pcp_qos_group_1;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cosmap);
+
+	if (pcp >= PCP_QOS_GROUP_0_MAX_ENTRY)
+		return SW_BAD_PARAM;
+
+	if (group_id == 0) {
+		pcp_qos_group_0.bf.qos_info = cosmap->internal_pcp | \
+								(cosmap->internal_dei << 3) | \
+								(cosmap->internal_pri << 4) | \
+								(cosmap->internal_dscp << 8) | \
+								(cosmap->internal_dp << 14);
+		rv = hppe_pcp_qos_group_0_set(dev_id, pcp, &pcp_qos_group_0);
+	} else if (group_id == 1) {
+		pcp_qos_group_1.bf.qos_info = cosmap->internal_pcp | \
+								(cosmap->internal_dei << 3) | \
+								(cosmap->internal_pri << 4) | \
+								(cosmap->internal_dscp << 8) | \
+								(cosmap->internal_dp << 14);
+		rv = hppe_pcp_qos_group_1_set(dev_id, pcp, &pcp_qos_group_1);
+	} else
+		return SW_BAD_PARAM;
+
+	return rv;
+}
+
+sw_error_t
+adpt_ppe_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t pcp, fal_qos_cosmap_t *cosmap)
+{
+	a_uint32_t chip_ver = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+        ADPT_NULL_POINT_CHECK(cosmap);
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_qos_cosmap_pcp_set(dev_id, group_id,
+				pcp, cosmap);
+#endif
+	} else {
+		return adpt_hppe_qos_cosmap_pcp_set(dev_id, group_id,
+				pcp, cosmap);
+	}
+
+	return SW_NOT_SUPPORTED;;
+}
+sw_error_t
+adpt_hppe_qos_port_remark_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_remark_enable_t *remark)
+{
+	sw_error_t rv = SW_OK;
+	union port_qos_ctrl_u port_qos_ctrl;
+
+	memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(remark);
+
+	rv = hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	remark->pcp_change_en = port_qos_ctrl.bf.port_pcp_change_en;
+	remark->dei_chage_en = port_qos_ctrl.bf.port_dei_change_en;
+	remark->dscp_change_en = port_qos_ctrl.bf.port_dscp_change_en;
+
+	return SW_OK;
+}
+
+static sw_error_t
+adpt_hppe_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t dscp, fal_qos_cosmap_t *cosmap)
+{
+	sw_error_t rv = SW_OK;
+	union dscp_qos_group_0_u dscp_qos_group_0;
+	union dscp_qos_group_1_u dscp_qos_group_1;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cosmap);
+
+	if (dscp >= DSCP_QOS_GROUP_0_MAX_ENTRY)
+		return SW_BAD_PARAM;
+
+	if (group_id == 0) {
+		rv = hppe_dscp_qos_group_0_get(dev_id, dscp, &dscp_qos_group_0);
+		if( rv != SW_OK )
+			return rv;
+		cosmap->internal_pcp = dscp_qos_group_0.bf.qos_info & 7;
+		cosmap->internal_dei = (dscp_qos_group_0.bf.qos_info >> 3) & 1;
+		cosmap->internal_pri = (dscp_qos_group_0.bf.qos_info >> 4) & 0xf;
+		cosmap->internal_dscp = (dscp_qos_group_0.bf.qos_info >> 8) & 0x3f;
+		cosmap->internal_dp = (dscp_qos_group_0.bf.qos_info >> 14) & 0x3;
+	} else if (group_id == 1) {
+		rv = hppe_dscp_qos_group_1_get(dev_id, dscp, &dscp_qos_group_1);
+		if( rv != SW_OK )
+			return rv;
+		cosmap->internal_pcp = dscp_qos_group_1.bf.qos_info & 7;
+		cosmap->internal_dei = (dscp_qos_group_1.bf.qos_info >> 3) & 1;
+		cosmap->internal_pri = (dscp_qos_group_1.bf.qos_info >> 4) & 0xf;
+		cosmap->internal_dscp = (dscp_qos_group_1.bf.qos_info >> 8) & 0x3f;
+		cosmap->internal_dp = (dscp_qos_group_1.bf.qos_info >> 14) & 0x3;
+	} else
+		return SW_BAD_PARAM;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_ppe_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t dscp, fal_qos_cosmap_t *cosmap)
+{
+	a_uint32_t chip_ver = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+        ADPT_NULL_POINT_CHECK(cosmap);
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_qos_cosmap_dscp_get(dev_id, group_id,
+				dscp, cosmap);
+#endif
+	} else {
+		return adpt_hppe_qos_cosmap_dscp_get(dev_id, group_id,
+				dscp, cosmap);
+	}
+
+	return SW_NOT_SUPPORTED;
+}
+
+static sw_error_t
+adpt_hppe_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint16_t flow, fal_qos_cosmap_t *cosmap)
+{
+	sw_error_t rv = SW_OK;
+	union flow_qos_group_0_u flow_qos_group_0;
+	union flow_qos_group_1_u flow_qos_group_1;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cosmap);
+
+	if (flow >= FLOW_QOS_GROUP_0_MAX_ENTRY)
+		return SW_BAD_PARAM;
+
+	if (group_id == 0) {
+		flow_qos_group_0.bf.qos_info = cosmap->internal_pcp | \
+								(cosmap->internal_dei << 3) | \
+								(cosmap->internal_pri << 4) | \
+								(cosmap->internal_dscp << 8) | \
+								(cosmap->internal_dp << 14);
+		rv = hppe_flow_qos_group_0_set(dev_id, flow, &flow_qos_group_0);
+	} else if (group_id == 1) {
+		flow_qos_group_1.bf.qos_info = cosmap->internal_pcp | \
+								(cosmap->internal_dei << 3) | \
+								(cosmap->internal_pri << 4) | \
+								(cosmap->internal_dscp << 8) | \
+								(cosmap->internal_dp << 14);
+		rv = hppe_flow_qos_group_1_set(dev_id, flow, &flow_qos_group_1);
+	} else
+		return SW_BAD_PARAM;
+
+	return rv;
+}
+
+sw_error_t
+adpt_ppe_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint16_t flow, fal_qos_cosmap_t *cosmap)
+{
+	a_uint32_t chip_ver = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+        ADPT_NULL_POINT_CHECK(cosmap);
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_qos_cosmap_flow_set(dev_id, group_id,
+				flow, cosmap);
+#endif
+	} else {
+		return adpt_hppe_qos_cosmap_flow_set(dev_id, group_id,
+				flow, cosmap);
+	}
+
+	return SW_NOT_SUPPORTED;
+}
+
+static sw_error_t
+adpt_hppe_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_group_t *group)
+{
+	union port_qos_ctrl_u port_qos_ctrl;
+
+	memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(group);
+
+	hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl);
+
+	port_qos_ctrl.bf.pcp_qos_group_id = group->pcp_group;
+	port_qos_ctrl.bf.dscp_qos_group_id = group->dscp_group;
+	port_qos_ctrl.bf.flow_qos_group_id = group->flow_group;
+	
+	return hppe_port_qos_ctrl_set(dev_id, port_id, &port_qos_ctrl);
+}
+
+sw_error_t
+adpt_ppe_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_group_t *group)
+{
+	a_uint32_t chip_ver = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+        ADPT_NULL_POINT_CHECK(group);
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_qos_port_group_set(dev_id, port_id, group);
+#endif
+	} else {
+		return adpt_hppe_qos_port_group_set(dev_id, port_id, group);
+	}
+
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+adpt_hppe_ring_queue_map_set(a_uint32_t dev_id, 
+					a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp)
+{
+	union ring_q_map_tbl_u ring_q_map_tbl;
+
+	memset(&ring_q_map_tbl, 0, sizeof(ring_q_map_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(queue_bmp);
+	if (ring_id >= RING_Q_MAP_TBL_MAX_ENTRY)
+		return SW_BAD_PARAM;
+
+	memcpy(ring_q_map_tbl.val, queue_bmp->bmp, sizeof(ring_q_map_tbl.val));
+	return hppe_ring_q_map_tbl_set(dev_id, ring_id, &ring_q_map_tbl);
+}
+
+static sw_error_t
+adpt_hppe_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t dscp, fal_qos_cosmap_t *cosmap)
+{
+	sw_error_t rv = SW_OK;
+	union dscp_qos_group_0_u dscp_qos_group_0;
+	union dscp_qos_group_1_u dscp_qos_group_1;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cosmap);
+
+	if (dscp >= DSCP_QOS_GROUP_0_MAX_ENTRY)
+		return SW_BAD_PARAM;
+
+	if (group_id == 0) {
+		dscp_qos_group_0.bf.qos_info = cosmap->internal_pcp | \
+								(cosmap->internal_dei << 3) | \
+								(cosmap->internal_pri << 4) | \
+								(cosmap->internal_dscp << 8) | \
+								(cosmap->internal_dp << 14);
+		rv = hppe_dscp_qos_group_0_set(dev_id, dscp, &dscp_qos_group_0);
+	} else if (group_id == 1) {
+		dscp_qos_group_1.bf.qos_info = cosmap->internal_pcp | \
+								(cosmap->internal_dei << 3) | \
+								(cosmap->internal_pri << 4) | \
+								(cosmap->internal_dscp << 8) | \
+								(cosmap->internal_dp << 14);
+		rv = hppe_dscp_qos_group_1_set(dev_id, dscp, &dscp_qos_group_1);
+	} else
+		return SW_BAD_PARAM;
+
+	return rv;
+}
+
+sw_error_t
+adpt_ppe_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id,
+				a_uint8_t dscp, fal_qos_cosmap_t *cosmap)
+{
+	a_uint32_t chip_ver = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+        ADPT_NULL_POINT_CHECK(cosmap);
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_qos_cosmap_dscp_set(dev_id, group_id,
+				dscp, cosmap);
+#endif
+	} else {
+		return adpt_hppe_qos_cosmap_dscp_set(dev_id, group_id,
+				dscp, cosmap);
+	}
+
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+adpt_hppe_qos_port_remark_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_remark_enable_t *remark)
+{
+	union port_qos_ctrl_u port_qos_ctrl;
+
+	memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(remark);
+
+	hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl);
+
+	port_qos_ctrl.bf.port_pcp_change_en = remark->pcp_change_en;
+	port_qos_ctrl.bf.port_dei_change_en = remark->dei_chage_en;
+	port_qos_ctrl.bf.port_dscp_change_en = remark->dscp_change_en;
+	
+	return hppe_port_qos_ctrl_set(dev_id, port_id, &port_qos_ctrl);
+}
+sw_error_t
+adpt_hppe_l1_flow_map_set(a_uint32_t dev_id,
+					a_uint32_t node_id,
+					fal_port_t port_id,
+					fal_qos_scheduler_cfg_t *scheduler_cfg)
+{
+	union l1_flow_map_tbl_u l1_flow_map_tbl;
+	union l1_c_sp_cfg_tbl_u l1_c_sp_cfg_tbl;
+	union l1_e_sp_cfg_tbl_u l1_e_sp_cfg_tbl;
+	union l1_flow_port_map_tbl_u l1_flow_port_map_tbl;
+	union l1_comp_cfg_tbl_u l1_comp_cfg_tbl;
+	a_uint32_t c_sp_id, e_sp_id;
+
+	memset(&l1_flow_map_tbl, 0, sizeof(l1_flow_map_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(scheduler_cfg);
+	if (node_id >= L1_FLOW_MAP_TBL_MAX_ENTRY)
+		return SW_BAD_PARAM;
+
+	l1_flow_map_tbl.bf.e_drr_wt= scheduler_cfg->e_drr_wt;
+	l1_flow_map_tbl.bf.c_drr_wt = scheduler_cfg->c_drr_wt;
+	l1_flow_map_tbl.bf.e_pri = scheduler_cfg->e_pri;
+	l1_flow_map_tbl.bf.c_pri = scheduler_cfg->c_pri;
+	l1_flow_map_tbl.bf.sp_id = scheduler_cfg->sp_id;
+	hppe_l1_flow_map_tbl_set(dev_id, node_id, &l1_flow_map_tbl);
+
+	c_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->c_pri;
+	l1_c_sp_cfg_tbl.bf.drr_credit_unit = scheduler_cfg->c_drr_unit;
+	l1_c_sp_cfg_tbl.bf.drr_id = scheduler_cfg->c_drr_id;
+	hppe_l1_c_sp_cfg_tbl_set(dev_id, c_sp_id, &l1_c_sp_cfg_tbl);
+
+	e_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->e_pri;
+	l1_e_sp_cfg_tbl.bf.drr_credit_unit = scheduler_cfg->e_drr_unit;
+	l1_e_sp_cfg_tbl.bf.drr_id = scheduler_cfg->e_drr_id;
+	hppe_l1_e_sp_cfg_tbl_set(dev_id, e_sp_id, &l1_e_sp_cfg_tbl);
+
+	l1_flow_port_map_tbl.bf.port_num = port_id;
+	hppe_l1_flow_port_map_tbl_set(dev_id, node_id, &l1_flow_port_map_tbl);
+
+	hppe_l1_comp_cfg_tbl_get(dev_id, node_id, &l1_comp_cfg_tbl);
+	l1_comp_cfg_tbl.bf.drr_meter_len = scheduler_cfg->drr_frame_mode;
+	hppe_l1_comp_cfg_tbl_set(dev_id, node_id, &l1_comp_cfg_tbl);
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_queue_scheduler_set(a_uint32_t dev_id, a_uint32_t node_id,
+					fal_queue_scheduler_level_t level,
+					fal_port_t port_id,
+					fal_qos_scheduler_cfg_t *scheduler_cfg)
+{
+	if (level == FAL_QUEUE_SCHEDULER_LEVEL0)
+		return adpt_hppe_l0_queue_map_set(dev_id, node_id, port_id, scheduler_cfg);
+	else if ((level == FAL_QUEUE_SCHEDULER_LEVEL1))
+		return adpt_hppe_l1_flow_map_set(dev_id, node_id, port_id, scheduler_cfg);
+	else
+		return SW_FAIL;
+}
+
+sw_error_t
+adpt_hppe_queue_scheduler_get(a_uint32_t dev_id, a_uint32_t node_id,
+					fal_queue_scheduler_level_t level,
+					fal_port_t *port_id,
+					fal_qos_scheduler_cfg_t *scheduler_cfg)
+{
+	if (level == FAL_QUEUE_SCHEDULER_LEVEL0)
+		return adpt_hppe_l0_queue_map_get(dev_id, node_id, port_id, scheduler_cfg);
+	else if ((level == FAL_QUEUE_SCHEDULER_LEVEL1))
+		return adpt_hppe_l1_flow_map_get(dev_id, node_id, port_id, scheduler_cfg);
+	else
+		return SW_FAIL;
+}
+
+static sw_error_t
+adpt_hppe_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint16_t flow, fal_qos_cosmap_t *cosmap)
+{
+	sw_error_t rv = SW_OK;
+	union flow_qos_group_0_u flow_qos_group_0;
+	union flow_qos_group_1_u flow_qos_group_1;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cosmap);
+
+	if (flow >= FLOW_QOS_GROUP_0_MAX_ENTRY)
+		return SW_BAD_PARAM;
+
+	if (group_id == 0) {
+		rv = hppe_flow_qos_group_0_get(dev_id, flow, &flow_qos_group_0);
+		if( rv != SW_OK )
+			return rv;
+		cosmap->internal_pcp = flow_qos_group_0.bf.qos_info & 7;
+		cosmap->internal_dei = (flow_qos_group_0.bf.qos_info >> 3) & 1;
+		cosmap->internal_pri = (flow_qos_group_0.bf.qos_info >> 4) & 0xf;
+		cosmap->internal_dscp = (flow_qos_group_0.bf.qos_info >> 8) & 0x3f;
+		cosmap->internal_dp = (flow_qos_group_0.bf.qos_info >> 14) & 0x3;
+	} else if (group_id == 1) {
+		rv = hppe_flow_qos_group_1_get(dev_id, flow, &flow_qos_group_1);
+		if( rv != SW_OK )
+			return rv;
+		cosmap->internal_pcp = flow_qos_group_1.bf.qos_info & 7;
+		cosmap->internal_dei = (flow_qos_group_1.bf.qos_info >> 3) & 1;
+		cosmap->internal_pri = (flow_qos_group_1.bf.qos_info >> 4) & 0xf;
+		cosmap->internal_dscp = (flow_qos_group_1.bf.qos_info >> 8) & 0x3f;
+		cosmap->internal_dp = (flow_qos_group_1.bf.qos_info >> 14) & 0x3;
+	} else
+		return SW_BAD_PARAM;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_ppe_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint16_t flow, fal_qos_cosmap_t *cosmap)
+{
+	a_uint32_t chip_ver = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+        ADPT_NULL_POINT_CHECK(cosmap);
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_qos_cosmap_flow_get(dev_id, group_id,
+				flow, cosmap);
+#endif
+	} else {
+		return adpt_hppe_qos_cosmap_flow_get(dev_id, group_id,
+				flow, cosmap);
+	}
+
+	return SW_NOT_SUPPORTED;
+}
+
+static sw_error_t
+adpt_hppe_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_group_t *group)
+{
+	sw_error_t rv = SW_OK;
+	union port_qos_ctrl_u port_qos_ctrl;
+
+	memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(group);
+
+	rv = hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl);
+	if( rv != SW_OK )
+		return rv;
+
+	group->pcp_group = port_qos_ctrl.bf.pcp_qos_group_id;
+	group->dscp_group = port_qos_ctrl.bf.dscp_qos_group_id;
+	group->flow_group = port_qos_ctrl.bf.flow_qos_group_id;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_ppe_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_group_t *group)
+{
+	a_uint32_t chip_ver = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+        ADPT_NULL_POINT_CHECK(group);
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+	if (chip_ver == CPPE_REVISION) {
+#if defined(CPPE)
+		return adpt_cppe_qos_port_group_get(dev_id, port_id, group);
+#endif
+	} else {
+		return adpt_hppe_qos_port_group_get(dev_id, port_id, group);
+	}
+
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+adpt_hppe_ring_queue_map_get(a_uint32_t dev_id, 
+					a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp)
+{
+	union ring_q_map_tbl_u ring_q_map_tbl;
+
+	memset(&ring_q_map_tbl, 0, sizeof(ring_q_map_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(queue_bmp);
+	if (ring_id >= RING_Q_MAP_TBL_MAX_ENTRY)
+		return SW_BAD_PARAM;
+
+	hppe_ring_q_map_tbl_get(dev_id, ring_id, &ring_q_map_tbl);
+	memcpy(queue_bmp->bmp, ring_q_map_tbl.val, sizeof(ring_q_map_tbl.val));
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_queues_get(a_uint32_t dev_id, 
+				fal_port_t port_id, fal_queue_bmp_t *queue_bmp)
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(queue_bmp);
+
+	*queue_bmp = port_queue_map[port_id];
+	
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_tdm_tick_num_set(a_uint32_t dev_id, a_uint32_t tick_num)
+{
+	union tdm_depth_cfg_u tdm_depth_cfg;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	tdm_depth_cfg.bf.tdm_depth = tick_num;
+	return hppe_tdm_depth_cfg_set(dev_id, &tdm_depth_cfg);
+}
+#ifndef IN_QOS_MINI
+sw_error_t
+adpt_hppe_tdm_tick_num_get(a_uint32_t dev_id, a_uint32_t *tick_num)
+{
+	union tdm_depth_cfg_u tdm_depth_cfg;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(tick_num);
+
+	hppe_tdm_depth_cfg_get(dev_id, &tdm_depth_cfg);
+	*tick_num = tdm_depth_cfg.bf.tdm_depth;
+
+	return SW_OK;
+}
+#endif
+sw_error_t
+adpt_hppe_port_scheduler_cfg_reset(a_uint32_t dev_id,
+				fal_port_t port_id)
+{
+	ssdk_dt_scheduler_cfg *dt_cfg;
+	fal_qos_scheduler_cfg_t cfg;
+	a_uint32_t i;
+
+	dt_cfg = ssdk_bootup_shceduler_cfg_get(dev_id);
+	if (!dt_cfg)
+		return SW_FAIL;
+
+	/* L1 shceduler */
+	for (i = 0; i < SSDK_L1SCHEDULER_CFG_MAX; i++) {
+		if (dt_cfg->l1cfg[i].valid && dt_cfg->l1cfg[i].port_id == port_id) {
+			cfg.sp_id = dt_cfg->l1cfg[i].port_id;
+			cfg.c_pri = dt_cfg->l1cfg[i].cpri;
+			cfg.e_pri = dt_cfg->l1cfg[i].epri;
+			cfg.c_drr_id = dt_cfg->l1cfg[i].cdrr_id;
+			cfg.e_drr_id = dt_cfg->l1cfg[i].edrr_id;
+			cfg.c_drr_wt = 1;
+			cfg.e_drr_wt = 1;
+			adpt_hppe_queue_scheduler_set(dev_id, i, 1,
+					dt_cfg->l1cfg[i].port_id, &cfg);
+		}
+	}
+
+	/* L0 shceduler */
+	for (i = 0; i < SSDK_L0SCHEDULER_CFG_MAX; i++) {
+		if (dt_cfg->l0cfg[i].valid && dt_cfg->l0cfg[i].port_id == port_id) {
+			cfg.sp_id = dt_cfg->l0cfg[i].sp_id;
+			cfg.c_pri = dt_cfg->l0cfg[i].cpri;
+			cfg.e_pri = dt_cfg->l0cfg[i].epri;
+			cfg.c_drr_id = dt_cfg->l0cfg[i].cdrr_id;
+			cfg.e_drr_id = dt_cfg->l0cfg[i].edrr_id;
+			cfg.c_drr_wt = 1;
+			cfg.e_drr_wt = 1;
+			adpt_hppe_queue_scheduler_set(dev_id, i,
+					0, dt_cfg->l0cfg[i].port_id, &cfg);
+		}
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_scheduler_cfg_set(a_uint32_t dev_id,
+				a_uint32_t tick_index,
+				fal_port_scheduler_cfg_t *cfg)
+{
+	union psch_tdm_cfg_tbl_u psch_tdm_cfg;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+
+	psch_tdm_cfg.bf.ens_port_bitmap = cfg->en_scheduler_port_bmp;
+	psch_tdm_cfg.bf.ens_port = cfg->en_scheduler_port;
+	psch_tdm_cfg.bf.des_port = cfg->de_scheduler_port;
+	return hppe_psch_tdm_cfg_tbl_set(dev_id, tick_index, &psch_tdm_cfg);
+}
+#ifndef IN_QOS_MINI
+sw_error_t
+adpt_hppe_port_scheduler_cfg_get(a_uint32_t dev_id,
+				a_uint32_t tick_index,
+				fal_port_scheduler_cfg_t *cfg)
+{
+	union psch_tdm_cfg_tbl_u psch_tdm_cfg;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+
+	hppe_psch_tdm_cfg_tbl_get(dev_id, tick_index, &psch_tdm_cfg);
+	cfg->en_scheduler_port_bmp = psch_tdm_cfg.bf.ens_port_bitmap;
+	cfg->en_scheduler_port = psch_tdm_cfg.bf.ens_port;
+	cfg->de_scheduler_port = psch_tdm_cfg.bf.des_port;
+
+	return SW_OK;
+}
+#endif
+sw_error_t
+adpt_hppe_scheduler_dequeue_ctrl_get(a_uint32_t dev_id,
+				a_uint32_t queue_id,
+				a_bool_t *enable)
+{
+	union deq_dis_tbl_u deq;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	hppe_deq_dis_tbl_get(dev_id, queue_id, &deq);
+	*enable = !(deq.bf.deq_dis);
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_scheduler_dequeue_ctrl_set(a_uint32_t dev_id,
+				a_uint32_t queue_id,
+				a_bool_t enable)
+{
+	union deq_dis_tbl_u deq;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	deq.bf.deq_dis = !enable;
+	return hppe_deq_dis_tbl_set(dev_id, queue_id, &deq);
+}
+
+sw_error_t
+adpt_hppe_port_scheduler_resource_get(a_uint32_t dev_id,
+				fal_port_t port_id,
+				fal_portscheduler_resource_t *cfg)
+{
+	ssdk_dt_scheduler_cfg *dt_cfg;
+	ssdk_dt_portscheduler_cfg *port_resource;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(cfg);
+
+	if (port_id >= SSDK_MAX_PORT_NUM)
+		return SW_BAD_PARAM;
+
+	dt_cfg = ssdk_bootup_shceduler_cfg_get(dev_id);
+	if (!dt_cfg)
+		return SW_NOT_SUPPORTED;
+
+	port_resource = &dt_cfg->pool[port_id];
+	cfg->ucastq_start = port_resource->ucastq_start;
+	cfg->ucastq_num = port_resource->ucastq_end - port_resource->ucastq_start + 1;
+	cfg->mcastq_start = port_resource->mcastq_start;
+	cfg->mcastq_num = port_resource->mcastq_end - port_resource->mcastq_start + 1;
+	cfg->l0sp_start = port_resource->l0sp_start;
+	cfg->l0sp_num = port_resource->l0sp_end - port_resource->l0sp_start + 1;
+	cfg->l0cdrr_start = port_resource->l0cdrr_start;
+	cfg->l0cdrr_num = port_resource->l0cdrr_end - port_resource->l0cdrr_start + 1;
+	cfg->l0edrr_start = port_resource->l0edrr_start;
+	cfg->l0edrr_num = port_resource->l0edrr_end - port_resource->l0edrr_start + 1;
+	cfg->l1sp_start = port_id;
+	cfg->l1sp_num = 1;
+	cfg->l1cdrr_start = port_resource->l1cdrr_start;
+	cfg->l1cdrr_num = port_resource->l1cdrr_end - port_resource->l1cdrr_start + 1;
+	cfg->l1edrr_start = port_resource->l1edrr_start;
+	cfg->l1edrr_num = port_resource->l1edrr_end - port_resource->l1edrr_start + 1;
+
+	return SW_OK;
+}
+
+void adpt_hppe_qos_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_qos_func_bitmap = ((1 << FUNC_QOS_PORT_PRI_SET) |
+						(1 << FUNC_QOS_PORT_PRI_GET) |
+						(1 << FUNC_QOS_COSMAP_PCP_GET) |
+						(1 << FUNC_QUEUE_SCHEDULER_SET) |
+						(1 << FUNC_QUEUE_SCHEDULER_GET) |
+						(1 << FUNC_PORT_QUEUES_GET) |
+						(1 << FUNC_QOS_COSMAP_PCP_SET) |
+						(1 << FUNC_QOS_PORT_REMARK_GET) |
+						(1 << FUNC_QOS_COSMAP_DSCP_GET) |
+						(1 << FUNC_QOS_COSMAP_FLOW_SET) |
+						(1 << FUNC_QOS_PORT_GROUP_SET) |
+						(1 << FUNC_RING_QUEUE_MAP_SET) |
+						(1 << FUNC_QOS_COSMAP_DSCP_SET) |
+						(1 << FUNC_QOS_PORT_REMARK_SET) |
+						(1 << FUNC_QOS_COSMAP_FLOW_GET) |
+						(1 << FUNC_QOS_PORT_GROUP_GET) |
+						(1 << FUNC_RING_QUEUE_MAP_GET) |
+						(1 << FUNC_TDM_TICK_NUM_SET) |
+						(1 << FUNC_TDM_TICK_NUM_GET) |
+						(1 << FUNC_PORT_SCHEDULER_CFG_SET) |
+						(1 << FUNC_PORT_SCHEDULER_CFG_GET) |
+						(1 << FUNC_SCHEDULER_DEQUEUE_CTRL_GET) |
+						(1 << FUNC_SCHEDULER_DEQUEUE_CTRL_SET) |
+						(1 << FUNC_QOS_PORT_MODE_PRI_GET) |
+						(1 << FUNC_QOS_PORT_MODE_PRI_SET) |
+						(1 << FUNC_QOS_PORT_SCHEDULER_CFG_RESET) |
+						(1 << FUNC_QOS_PORT_SCHEDULER_RESOURCE_GET));
+	return;
+}
+
+static void adpt_hppe_qos_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_qos_port_pri_set = NULL;
+	p_adpt_api->adpt_qos_port_pri_get = NULL;
+	p_adpt_api->adpt_qos_cosmap_pcp_get = NULL;
+	p_adpt_api->adpt_queue_scheduler_set = NULL;
+	p_adpt_api->adpt_queue_scheduler_get = NULL;
+	p_adpt_api->adpt_port_queues_get = NULL;
+	p_adpt_api->adpt_qos_cosmap_pcp_set = NULL;
+	p_adpt_api->adpt_qos_port_remark_get = NULL;
+	p_adpt_api->adpt_qos_cosmap_dscp_get = NULL;
+	p_adpt_api->adpt_qos_cosmap_flow_set = NULL;
+	p_adpt_api->adpt_qos_port_group_set = NULL;
+	p_adpt_api->adpt_ring_queue_map_set = NULL;
+	p_adpt_api->adpt_qos_cosmap_dscp_set = NULL;
+	p_adpt_api->adpt_qos_port_remark_set = NULL;
+	p_adpt_api->adpt_qos_cosmap_flow_get = NULL;
+	p_adpt_api->adpt_qos_port_group_get = NULL;
+	p_adpt_api->adpt_ring_queue_map_get = NULL;
+	p_adpt_api->adpt_tdm_tick_num_set = NULL;
+	p_adpt_api->adpt_tdm_tick_num_get = NULL;
+	p_adpt_api->adpt_port_scheduler_cfg_set = NULL;
+	p_adpt_api->adpt_port_scheduler_cfg_get = NULL;
+	p_adpt_api->adpt_scheduler_dequeue_ctrl_get = NULL;
+	p_adpt_api->adpt_scheduler_dequeue_ctrl_set = NULL;
+	p_adpt_api->adpt_qos_port_mode_pri_get = NULL;
+	p_adpt_api->adpt_qos_port_mode_pri_set = NULL;
+	p_adpt_api->adpt_port_scheduler_cfg_reset = NULL;
+	p_adpt_api->adpt_port_scheduler_resource_get = NULL;
+
+	return;
+}
+
+sw_error_t adpt_hppe_qos_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_qos_func_unregister(dev_id, p_adpt_api);
+
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_PRI_SET))
+		p_adpt_api->adpt_qos_port_pri_set = adpt_ppe_qos_port_pri_set;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_PRI_GET))
+		p_adpt_api->adpt_qos_port_pri_get = adpt_ppe_qos_port_pri_get;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_COSMAP_PCP_GET))
+		p_adpt_api->adpt_qos_cosmap_pcp_get = adpt_ppe_qos_cosmap_pcp_get;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QUEUE_SCHEDULER_SET))
+		p_adpt_api->adpt_queue_scheduler_set = adpt_hppe_queue_scheduler_set;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QUEUE_SCHEDULER_GET))
+		p_adpt_api->adpt_queue_scheduler_get = adpt_hppe_queue_scheduler_get;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_PORT_QUEUES_GET))
+		p_adpt_api->adpt_port_queues_get = adpt_hppe_port_queues_get;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_COSMAP_PCP_SET))
+		p_adpt_api->adpt_qos_cosmap_pcp_set = adpt_ppe_qos_cosmap_pcp_set;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_REMARK_GET))
+		p_adpt_api->adpt_qos_port_remark_get = adpt_hppe_qos_port_remark_get;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_COSMAP_DSCP_GET))
+		p_adpt_api->adpt_qos_cosmap_dscp_get = adpt_ppe_qos_cosmap_dscp_get;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_COSMAP_FLOW_SET))
+		p_adpt_api->adpt_qos_cosmap_flow_set = adpt_ppe_qos_cosmap_flow_set;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_GROUP_SET))
+		p_adpt_api->adpt_qos_port_group_set = adpt_ppe_qos_port_group_set;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_RING_QUEUE_MAP_SET))
+		p_adpt_api->adpt_ring_queue_map_set = adpt_hppe_ring_queue_map_set;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_COSMAP_DSCP_SET))
+		p_adpt_api->adpt_qos_cosmap_dscp_set = adpt_ppe_qos_cosmap_dscp_set;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_REMARK_SET))
+		p_adpt_api->adpt_qos_port_remark_set = adpt_hppe_qos_port_remark_set;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_COSMAP_FLOW_GET))
+		p_adpt_api->adpt_qos_cosmap_flow_get = adpt_ppe_qos_cosmap_flow_get;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_GROUP_GET))
+		p_adpt_api->adpt_qos_port_group_get = adpt_ppe_qos_port_group_get;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_RING_QUEUE_MAP_GET))
+		p_adpt_api->adpt_ring_queue_map_get = adpt_hppe_ring_queue_map_get;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_TDM_TICK_NUM_SET))
+		p_adpt_api->adpt_tdm_tick_num_set = adpt_hppe_tdm_tick_num_set;
+#ifndef IN_QOS_MINI
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_TDM_TICK_NUM_GET))
+		p_adpt_api->adpt_tdm_tick_num_get = adpt_hppe_tdm_tick_num_get;
+#endif
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_PORT_SCHEDULER_CFG_SET))
+		p_adpt_api->adpt_port_scheduler_cfg_set = adpt_hppe_port_scheduler_cfg_set;
+#ifndef IN_QOS_MINI
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_PORT_SCHEDULER_CFG_GET))
+		p_adpt_api->adpt_port_scheduler_cfg_get = adpt_hppe_port_scheduler_cfg_get;
+#endif
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_SCHEDULER_DEQUEUE_CTRL_GET))
+		p_adpt_api->adpt_scheduler_dequeue_ctrl_get = adpt_hppe_scheduler_dequeue_ctrl_get;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_SCHEDULER_DEQUEUE_CTRL_SET))
+		p_adpt_api->adpt_scheduler_dequeue_ctrl_set = adpt_hppe_scheduler_dequeue_ctrl_set;
+#ifndef IN_QOS_MINI
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_MODE_PRI_GET))
+		p_adpt_api->adpt_qos_port_mode_pri_get = adpt_hppe_qos_port_mode_pri_get;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_MODE_PRI_SET))
+		p_adpt_api->adpt_qos_port_mode_pri_set = adpt_hppe_qos_port_mode_pri_set;
+#endif
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_SCHEDULER_CFG_RESET))
+		p_adpt_api->adpt_port_scheduler_cfg_reset = adpt_hppe_port_scheduler_cfg_reset;
+	if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_SCHEDULER_RESOURCE_GET))
+		p_adpt_api->adpt_port_scheduler_resource_get = adpt_hppe_port_scheduler_resource_get;
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_rss_hash.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_rss_hash.c
new file mode 100755
index 0000000..1834b39
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_rss_hash.c
@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_rss_reg.h"
+#include "hppe_rss.h"
+#include "adpt.h"
+
+sw_error_t
+adpt_hppe_rss_hash_config_set(a_uint32_t dev_id, fal_rss_hash_mode_t mode,
+			fal_rss_hash_config_t * config)
+{
+	a_uint32_t index;
+	union rss_hash_mask_reg_u rss_hash_mask_ipv6 = {0};
+	union rss_hash_seed_reg_u rss_hash_seed_ipv6 = {0};
+	union rss_hash_mix_reg_u rss_hash_mix_ipv6[11] = {0};
+	union rss_hash_fin_reg_u rss_hash_fin_ipv6[5] = {0};
+	union rss_hash_mask_ipv4_reg_u rss_hash_mask_ipv4 = {0};
+	union rss_hash_seed_ipv4_reg_u rss_hash_seed_ipv4 = {0};
+	union rss_hash_mix_ipv4_reg_u rss_hash_mix_ipv4[5] = {0};
+	union rss_hash_fin_ipv4_reg_u rss_hash_fin_ipv4[5] = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (mode == FAL_RSS_HASH_IPV4V6 || mode == FAL_RSS_HASH_IPV4ONLY)
+	{
+		rss_hash_mask_ipv4.bf.mask = config->hash_mask & 0x1fffff;
+		rss_hash_mask_ipv4.bf.fragment = config->hash_fragment_mode;
+
+		rss_hash_seed_ipv4.bf.seed = config->hash_seed;
+
+		rss_hash_mix_ipv4[0].bf.hash_mix = config->hash_sip_mix & 0x1f;
+		rss_hash_mix_ipv4[1].bf.hash_mix = config->hash_dip_mix & 0x1f;
+		rss_hash_mix_ipv4[2].bf.hash_mix = config->hash_protocol_mix & 0x1f;
+		rss_hash_mix_ipv4[3].bf.hash_mix = config->hash_dport_mix & 0x1f;
+		rss_hash_mix_ipv4[4].bf.hash_mix = config->hash_sport_mix & 0x1f;
+
+		rss_hash_fin_ipv4[0].bf.fin_inner = config->hash_fin_inner & 0x1f;
+		rss_hash_fin_ipv4[0].bf.fin_outer = config->hash_fin_outer & 0x1f;
+		rss_hash_fin_ipv4[1].bf.fin_inner = (config->hash_fin_inner >> 0x5) & 0x1f;
+		rss_hash_fin_ipv4[1].bf.fin_outer = (config->hash_fin_outer >> 0x5) & 0x1f;
+		rss_hash_fin_ipv4[2].bf.fin_inner = (config->hash_fin_inner >> 0xa) & 0x1f;
+		rss_hash_fin_ipv4[2].bf.fin_outer = (config->hash_fin_outer >> 0xa) & 0x1f;
+		rss_hash_fin_ipv4[3].bf.fin_inner = (config->hash_fin_inner >> 0xf) & 0x1f;
+		rss_hash_fin_ipv4[3].bf.fin_outer = (config->hash_fin_outer >> 0xf) & 0x1f;
+		rss_hash_fin_ipv4[4].bf.fin_inner = (config->hash_fin_inner >> 0x14) & 0x1f;
+		rss_hash_fin_ipv4[4].bf.fin_outer = (config->hash_fin_outer >> 0x14) & 0x1f;
+
+		SW_RTN_ON_ERROR(hppe_rss_hash_mask_ipv4_reg_set(dev_id, &rss_hash_mask_ipv4));
+		SW_RTN_ON_ERROR(hppe_rss_hash_seed_ipv4_reg_set(dev_id, &rss_hash_seed_ipv4));
+		for (index = 0; index < 5; index++)
+			SW_RTN_ON_ERROR(hppe_rss_hash_mix_ipv4_reg_set(dev_id, index, &rss_hash_mix_ipv4[index]));
+		for (index = 0; index < 5; index++)
+			SW_RTN_ON_ERROR(hppe_rss_hash_fin_ipv4_reg_set(dev_id, index, &rss_hash_fin_ipv4[index]));
+	}
+
+	if (mode == FAL_RSS_HASH_IPV4V6 || mode == FAL_RSS_HASH_IPV6ONLY)
+	{
+		rss_hash_mask_ipv6.bf.mask = config->hash_mask & 0x1fffff;
+		rss_hash_mask_ipv6.bf.fragment = config->hash_fragment_mode;
+
+		rss_hash_seed_ipv6.bf.seed = config->hash_seed;
+
+		rss_hash_mix_ipv6[0].bf.hash_mix = config->hash_sip_mix & 0x1f;
+		rss_hash_mix_ipv6[1].bf.hash_mix = (config->hash_sip_mix >> 0x5) & 0x1f;
+		rss_hash_mix_ipv6[2].bf.hash_mix = (config->hash_sip_mix >> 0xa) & 0x1f;
+		rss_hash_mix_ipv6[3].bf.hash_mix = (config->hash_sip_mix >> 0xf) & 0x1f;
+
+		rss_hash_mix_ipv6[4].bf.hash_mix = config->hash_dip_mix & 0x1f;
+		rss_hash_mix_ipv6[5].bf.hash_mix = (config->hash_dip_mix >> 0x5) & 0x1f;
+		rss_hash_mix_ipv6[6].bf.hash_mix = (config->hash_dip_mix >> 0xa) & 0x1f;
+		rss_hash_mix_ipv6[7].bf.hash_mix = (config->hash_dip_mix >> 0xf) & 0x1f;
+
+		rss_hash_mix_ipv6[8].bf.hash_mix = config->hash_protocol_mix & 0x1f;
+		rss_hash_mix_ipv6[9].bf.hash_mix = config->hash_dport_mix & 0x1f;
+		rss_hash_mix_ipv6[10].bf.hash_mix = config->hash_sport_mix & 0x1f;
+
+		rss_hash_fin_ipv6[0].bf.fin_inner = config->hash_fin_inner & 0x1f;
+		rss_hash_fin_ipv6[0].bf.fin_outer = config->hash_fin_outer & 0x1f;
+		rss_hash_fin_ipv6[1].bf.fin_inner = (config->hash_fin_inner >> 0x5) & 0x1f;
+		rss_hash_fin_ipv6[1].bf.fin_outer = (config->hash_fin_outer >> 0x5) & 0x1f;
+		rss_hash_fin_ipv6[2].bf.fin_inner = (config->hash_fin_inner >> 0xa) & 0x1f;
+		rss_hash_fin_ipv6[2].bf.fin_outer = (config->hash_fin_outer >> 0xa) & 0x1f;
+		rss_hash_fin_ipv6[3].bf.fin_inner = (config->hash_fin_inner >> 0xf) & 0x1f;
+		rss_hash_fin_ipv6[3].bf.fin_outer = (config->hash_fin_outer >> 0xf) & 0x1f;
+		rss_hash_fin_ipv6[4].bf.fin_inner = (config->hash_fin_inner >> 0x14) & 0x1f;
+		rss_hash_fin_ipv6[4].bf.fin_outer = (config->hash_fin_outer >> 0x14) & 0x1f;
+
+		SW_RTN_ON_ERROR(hppe_rss_hash_mask_reg_set(dev_id, &rss_hash_mask_ipv6));
+		SW_RTN_ON_ERROR(hppe_rss_hash_seed_reg_set(dev_id, &rss_hash_seed_ipv6));
+		for (index = 0; index < 11; index++)
+			SW_RTN_ON_ERROR(hppe_rss_hash_mix_reg_set(dev_id, index, &rss_hash_mix_ipv6[index]));
+		for (index = 0; index < 5; index++)
+			SW_RTN_ON_ERROR(hppe_rss_hash_fin_reg_set(dev_id, index, &rss_hash_fin_ipv6[index]));
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_rss_hash_config_get(a_uint32_t dev_id, fal_rss_hash_mode_t mode,
+			fal_rss_hash_config_t * config)
+{
+	a_uint32_t index;
+	union rss_hash_mask_reg_u rss_hash_mask_ipv6 = {0};
+	union rss_hash_seed_reg_u rss_hash_seed_ipv6 = {0};
+	union rss_hash_mix_reg_u rss_hash_mix_ipv6[11] = {0};
+	union rss_hash_fin_reg_u rss_hash_fin_ipv6[5] = {0};
+	union rss_hash_mask_ipv4_reg_u rss_hash_mask_ipv4 = {0};
+	union rss_hash_seed_ipv4_reg_u rss_hash_seed_ipv4 = {0};
+	union rss_hash_mix_ipv4_reg_u rss_hash_mix_ipv4[5] = {0};
+	union rss_hash_fin_ipv4_reg_u rss_hash_fin_ipv4[5] = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	SW_RTN_ON_ERROR(hppe_rss_hash_mask_ipv4_reg_get(dev_id, &rss_hash_mask_ipv4));
+	SW_RTN_ON_ERROR(hppe_rss_hash_seed_ipv4_reg_get(dev_id, &rss_hash_seed_ipv4));
+	for (index = 0; index < 5; index++)
+		SW_RTN_ON_ERROR(hppe_rss_hash_mix_ipv4_reg_get(dev_id, index, &rss_hash_mix_ipv4[index]));
+	for (index = 0; index < 5; index++)
+		SW_RTN_ON_ERROR(hppe_rss_hash_fin_ipv4_reg_get(dev_id, index, &rss_hash_fin_ipv4[index]));
+
+	SW_RTN_ON_ERROR(hppe_rss_hash_mask_reg_get(dev_id, &rss_hash_mask_ipv6));
+	SW_RTN_ON_ERROR(hppe_rss_hash_seed_reg_get(dev_id, &rss_hash_seed_ipv6));
+	for (index = 0; index < 11; index++)
+		SW_RTN_ON_ERROR(hppe_rss_hash_mix_reg_get(dev_id, index, &rss_hash_mix_ipv6[index]));
+	for (index = 0; index < 5; index++)
+		SW_RTN_ON_ERROR(hppe_rss_hash_fin_reg_get(dev_id, index, &rss_hash_fin_ipv6[index]));
+
+	if (mode == FAL_RSS_HASH_IPV4ONLY)
+	{
+		config->hash_mask = rss_hash_mask_ipv4.bf.mask;
+		config->hash_fragment_mode = rss_hash_mask_ipv4.bf.fragment;
+		config->hash_seed = rss_hash_seed_ipv4.bf.seed;
+		config->hash_sip_mix = rss_hash_mix_ipv4[0].bf.hash_mix;
+		config->hash_dip_mix = rss_hash_mix_ipv4[1].bf.hash_mix;
+		config->hash_protocol_mix = rss_hash_mix_ipv4[2].bf.hash_mix;
+		config->hash_dport_mix = rss_hash_mix_ipv4[3].bf.hash_mix;
+		config->hash_sport_mix = rss_hash_mix_ipv4[4].bf.hash_mix;
+		config->hash_fin_inner = rss_hash_fin_ipv4[0].bf.fin_inner +
+				(rss_hash_fin_ipv4[1].bf.fin_inner << 0x5) +
+				(rss_hash_fin_ipv4[2].bf.fin_inner << 0xa) +
+				(rss_hash_fin_ipv4[3].bf.fin_inner << 0xf) +
+				(rss_hash_fin_ipv4[4].bf.fin_inner << 0x14);
+		config->hash_fin_outer = rss_hash_fin_ipv4[0].bf.fin_outer +
+				(rss_hash_fin_ipv4[1].bf.fin_outer << 0x5) +
+				(rss_hash_fin_ipv4[2].bf.fin_outer << 0xa) +
+				(rss_hash_fin_ipv4[3].bf.fin_outer << 0xf) +
+				(rss_hash_fin_ipv4[4].bf.fin_outer << 0x14);
+	}
+	else if (mode == FAL_RSS_HASH_IPV6ONLY)
+	{
+		config->hash_mask = rss_hash_mask_ipv6.bf.mask;
+		config->hash_fragment_mode = rss_hash_mask_ipv6.bf.fragment;
+		config->hash_seed = rss_hash_seed_ipv6.bf.seed;
+		config->hash_sip_mix = rss_hash_mix_ipv6[0].bf.hash_mix +
+				(rss_hash_mix_ipv6[1].bf.hash_mix << 0x5) +
+				(rss_hash_mix_ipv6[2].bf.hash_mix << 0xa) +
+				(rss_hash_mix_ipv6[3].bf.hash_mix << 0xf);
+		config->hash_dip_mix = rss_hash_mix_ipv6[4].bf.hash_mix +
+				(rss_hash_mix_ipv6[5].bf.hash_mix << 0x5) +
+				(rss_hash_mix_ipv6[6].bf.hash_mix << 0xa) +
+				(rss_hash_mix_ipv6[7].bf.hash_mix << 0xf);
+		config->hash_protocol_mix = rss_hash_mix_ipv6[8].bf.hash_mix;
+		config->hash_dport_mix = rss_hash_mix_ipv6[9].bf.hash_mix;
+		config->hash_sport_mix = rss_hash_mix_ipv6[10].bf.hash_mix;
+		config->hash_fin_inner = rss_hash_fin_ipv6[0].bf.fin_inner +
+				(rss_hash_fin_ipv6[1].bf.fin_inner << 0x5) +
+				(rss_hash_fin_ipv6[2].bf.fin_inner << 0xa) +
+				(rss_hash_fin_ipv6[3].bf.fin_inner << 0xf) +
+				(rss_hash_fin_ipv6[4].bf.fin_inner << 0x14);
+		config->hash_fin_outer = rss_hash_fin_ipv6[0].bf.fin_outer +
+				(rss_hash_fin_ipv6[1].bf.fin_outer << 0x5) +
+				(rss_hash_fin_ipv6[2].bf.fin_outer << 0xa) +
+				(rss_hash_fin_ipv6[3].bf.fin_outer << 0xf) +
+				(rss_hash_fin_ipv6[4].bf.fin_outer << 0x14);
+	}
+	else
+	{
+		if ((rss_hash_mask_ipv4.bf.mask == rss_hash_mask_ipv6.bf.mask) &&
+			(rss_hash_mask_ipv4.bf.fragment == rss_hash_mask_ipv6.bf.fragment) &&
+			(rss_hash_seed_ipv4.bf.seed == rss_hash_seed_ipv6.bf.seed) &&
+			(rss_hash_mix_ipv4[0].bf.hash_mix == rss_hash_mix_ipv6[0].bf.hash_mix) &&
+			(rss_hash_mix_ipv4[1].bf.hash_mix == rss_hash_mix_ipv6[4].bf.hash_mix) &&
+			(rss_hash_mix_ipv4[2].bf.hash_mix == rss_hash_mix_ipv6[8].bf.hash_mix) &&
+			(rss_hash_mix_ipv4[3].bf.hash_mix == rss_hash_mix_ipv6[9].bf.hash_mix) &&
+			(rss_hash_mix_ipv4[4].bf.hash_mix == rss_hash_mix_ipv6[10].bf.hash_mix) &&
+			(rss_hash_fin_ipv4[0].bf.fin_inner == rss_hash_fin_ipv6[0].bf.fin_inner) &&
+			(rss_hash_fin_ipv4[1].bf.fin_inner == rss_hash_fin_ipv6[1].bf.fin_inner) &&
+			(rss_hash_fin_ipv4[2].bf.fin_inner == rss_hash_fin_ipv6[2].bf.fin_inner) &&
+			(rss_hash_fin_ipv4[3].bf.fin_inner == rss_hash_fin_ipv6[3].bf.fin_inner) &&
+			(rss_hash_fin_ipv4[4].bf.fin_inner == rss_hash_fin_ipv6[4].bf.fin_inner) &&
+			(rss_hash_fin_ipv4[0].bf.fin_outer == rss_hash_fin_ipv6[0].bf.fin_outer) &&
+			(rss_hash_fin_ipv4[1].bf.fin_outer == rss_hash_fin_ipv6[1].bf.fin_outer) &&
+			(rss_hash_fin_ipv4[2].bf.fin_outer == rss_hash_fin_ipv6[2].bf.fin_outer) &&
+			(rss_hash_fin_ipv4[3].bf.fin_outer == rss_hash_fin_ipv6[3].bf.fin_outer) &&
+			(rss_hash_fin_ipv4[4].bf.fin_outer == rss_hash_fin_ipv6[4].bf.fin_outer))
+		{
+			config->hash_mask = rss_hash_mask_ipv6.bf.mask;
+			config->hash_fragment_mode = rss_hash_mask_ipv6.bf.fragment;
+			config->hash_seed = rss_hash_seed_ipv6.bf.seed;
+			config->hash_sip_mix = rss_hash_mix_ipv6[0].bf.hash_mix +
+					(rss_hash_mix_ipv6[1].bf.hash_mix << 0x5) +
+					(rss_hash_mix_ipv6[2].bf.hash_mix << 0xa) +
+					(rss_hash_mix_ipv6[3].bf.hash_mix << 0xf);
+			config->hash_dip_mix = rss_hash_mix_ipv6[4].bf.hash_mix +
+					(rss_hash_mix_ipv6[5].bf.hash_mix << 0x5) +
+					(rss_hash_mix_ipv6[6].bf.hash_mix << 0xa) +
+					(rss_hash_mix_ipv6[7].bf.hash_mix << 0xf);
+			config->hash_protocol_mix = rss_hash_mix_ipv6[8].bf.hash_mix;
+			config->hash_dport_mix = rss_hash_mix_ipv6[9].bf.hash_mix;
+			config->hash_sport_mix = rss_hash_mix_ipv6[10].bf.hash_mix;
+			config->hash_fin_inner = rss_hash_fin_ipv6[0].bf.fin_inner +
+					(rss_hash_fin_ipv6[1].bf.fin_inner << 0x5) +
+					(rss_hash_fin_ipv6[2].bf.fin_inner << 0xa) +
+					(rss_hash_fin_ipv6[3].bf.fin_inner << 0xf) +
+					(rss_hash_fin_ipv6[4].bf.fin_inner << 0x14);
+			config->hash_fin_outer = rss_hash_fin_ipv6[0].bf.fin_outer +
+					(rss_hash_fin_ipv6[1].bf.fin_outer << 0x5) +
+					(rss_hash_fin_ipv6[2].bf.fin_outer << 0xa) +
+					(rss_hash_fin_ipv6[3].bf.fin_outer << 0xf) +
+					(rss_hash_fin_ipv6[4].bf.fin_outer << 0x14);
+		}
+		else
+			return SW_FAIL;
+	}
+
+	return SW_OK;
+}
+
+void adpt_hppe_rss_hash_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_rss_hash_func_bitmap = ((1 << FUNC_RSS_HASH_CONFIG_SET) |
+						(1 << FUNC_RSS_HASH_CONFIG_GET));
+
+	return;
+}
+
+static void adpt_hppe_rss_hash_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_rss_hash_config_set = NULL;
+	p_adpt_api->adpt_rss_hash_config_get = NULL;
+
+	return;
+}
+
+sw_error_t adpt_hppe_rss_hash_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_rss_hash_func_unregister(dev_id, p_adpt_api);
+
+	if(p_adpt_api->adpt_rss_hash_func_bitmap & (1<<FUNC_RSS_HASH_CONFIG_SET))
+		p_adpt_api->adpt_rss_hash_config_set = adpt_hppe_rss_hash_config_set;
+	if(p_adpt_api->adpt_rss_hash_func_bitmap & (1<<FUNC_RSS_HASH_CONFIG_GET))
+		p_adpt_api->adpt_rss_hash_config_get = adpt_hppe_rss_hash_config_get;
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
+
+
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_sec.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_sec.c
new file mode 100755
index 0000000..e8f5991
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_sec.c
@@ -0,0 +1,261 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "fal_sec.h"
+#include "hppe_sec_reg.h"
+#include "hppe_sec.h"
+#include "adpt.h"
+
+sw_error_t
+adpt_hppe_sec_l3_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl)
+{
+	union l3_exception_parsing_ctrl_reg_u l3_exception_parsing_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	memset(&l3_exception_parsing_ctrl, 0, sizeof(l3_exception_parsing_ctrl));
+
+	l3_exception_parsing_ctrl.bf.small_ttl = ctrl->small_ip4ttl;
+	l3_exception_parsing_ctrl.bf.small_hop_limit = ctrl->small_ip6hoplimit;
+	
+	return hppe_l3_exception_parsing_ctrl_reg_set(dev_id, &l3_exception_parsing_ctrl);
+}
+sw_error_t
+adpt_hppe_sec_l3_excep_ctrl_get(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl)
+{
+	union l3_exception_cmd_u l3_exception_cmd;
+	union l3_exp_l3_only_ctrl_u l3_only_ctrl;
+	union l3_exp_l2_only_ctrl_u l2_only_ctrl;
+	union l3_exp_l2_flow_ctrl_u l2_flow_ctrl;
+	union l3_exp_l3_flow_ctrl_u l3_flow_ctrl;
+	union l3_exp_multicast_ctrl_u multicast_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+	if (excep_type >= L3_EXCEPTION_CMD_MAX_ENTRY)
+		return SW_BAD_VALUE;
+
+	hppe_l3_exception_cmd_get(dev_id, excep_type, &l3_exception_cmd);
+	hppe_l3_exp_l3_only_ctrl_get(dev_id, excep_type, &l3_only_ctrl);
+	hppe_l3_exp_l2_only_ctrl_get(dev_id, excep_type, &l2_only_ctrl);
+	hppe_l3_exp_l3_flow_ctrl_get(dev_id, excep_type, &l3_flow_ctrl);
+	hppe_l3_exp_l2_flow_ctrl_get(dev_id, excep_type, &l2_flow_ctrl);
+	hppe_l3_exp_multicast_ctrl_get(dev_id, excep_type, &multicast_ctrl);
+
+	ctrl->cmd = l3_exception_cmd.bf.l3_excep_cmd;
+	ctrl->deacclr_en = l3_exception_cmd.bf.de_acce;
+	ctrl->l3route_only_en = l3_only_ctrl.bf.excep_en;
+	ctrl->l2fwd_only_en = l2_only_ctrl.bf.excep_en;
+	ctrl->l3flow_en = l3_flow_ctrl.bf.excep_en;
+	ctrl->l2flow_en = l2_flow_ctrl.bf.excep_en;
+	ctrl->multicast_en = multicast_ctrl.bf.excep_en;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_sec_l3_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl)
+{
+	sw_error_t rv = SW_OK;
+	union l3_exception_parsing_ctrl_reg_u l3_exception_parsing_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	rv = hppe_l3_exception_parsing_ctrl_reg_get(dev_id, &l3_exception_parsing_ctrl);
+	if( rv != SW_OK )
+		return rv;
+
+	ctrl->small_ip4ttl = l3_exception_parsing_ctrl.bf.small_ttl;
+	ctrl->small_ip6hoplimit = l3_exception_parsing_ctrl.bf.small_hop_limit;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_sec_l4_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl)
+{
+	union l4_exception_parsing_ctrl_0_reg_u l4_exception_parsing_ctrl_0;
+	union l4_exception_parsing_ctrl_1_reg_u l4_exception_parsing_ctrl_1;
+	union l4_exception_parsing_ctrl_2_reg_u l4_exception_parsing_ctrl_2;
+	union l4_exception_parsing_ctrl_3_reg_u l4_exception_parsing_ctrl_3;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+
+	l4_exception_parsing_ctrl_0.bf.tcp_flags0 = ctrl->tcp_flags[0];
+	l4_exception_parsing_ctrl_0.bf.tcp_flags0_mask = ctrl->tcp_flags_mask[0];
+	l4_exception_parsing_ctrl_0.bf.tcp_flags1 = ctrl->tcp_flags[1];
+	l4_exception_parsing_ctrl_0.bf.tcp_flags1_mask = ctrl->tcp_flags_mask[1];
+	l4_exception_parsing_ctrl_1.bf.tcp_flags2 = ctrl->tcp_flags[2];
+	l4_exception_parsing_ctrl_1.bf.tcp_flags2_mask = ctrl->tcp_flags_mask[2];
+	l4_exception_parsing_ctrl_1.bf.tcp_flags3 = ctrl->tcp_flags[3];
+	l4_exception_parsing_ctrl_1.bf.tcp_flags3_mask = ctrl->tcp_flags_mask[3];
+	l4_exception_parsing_ctrl_2.bf.tcp_flags4 = ctrl->tcp_flags[4];
+	l4_exception_parsing_ctrl_2.bf.tcp_flags4_mask = ctrl->tcp_flags_mask[4];
+	l4_exception_parsing_ctrl_2.bf.tcp_flags5 = ctrl->tcp_flags[5];
+	l4_exception_parsing_ctrl_2.bf.tcp_flags5_mask = ctrl->tcp_flags_mask[5];
+	l4_exception_parsing_ctrl_3.bf.tcp_flags6 = ctrl->tcp_flags[6];
+	l4_exception_parsing_ctrl_3.bf.tcp_flags6_mask = ctrl->tcp_flags_mask[6];
+	l4_exception_parsing_ctrl_3.bf.tcp_flags7 = ctrl->tcp_flags[7];
+	l4_exception_parsing_ctrl_3.bf.tcp_flags7_mask = ctrl->tcp_flags_mask[7];
+	
+	hppe_l4_exception_parsing_ctrl_0_reg_set(dev_id, &l4_exception_parsing_ctrl_0);
+	hppe_l4_exception_parsing_ctrl_1_reg_set(dev_id, &l4_exception_parsing_ctrl_1);
+	hppe_l4_exception_parsing_ctrl_2_reg_set(dev_id, &l4_exception_parsing_ctrl_2);
+	hppe_l4_exception_parsing_ctrl_3_reg_set(dev_id, &l4_exception_parsing_ctrl_3);
+	return SW_OK;
+}
+sw_error_t
+adpt_hppe_sec_l3_excep_ctrl_set(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl)
+{
+	union l3_exception_cmd_u l3_exception_cmd;
+	union l3_exp_l3_only_ctrl_u l3_only_ctrl;
+	union l3_exp_l2_only_ctrl_u l2_only_ctrl;
+	union l3_exp_l2_flow_ctrl_u l2_flow_ctrl;
+	union l3_exp_l3_flow_ctrl_u l3_flow_ctrl;
+	union l3_exp_multicast_ctrl_u multicast_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+	if (excep_type >= L3_EXCEPTION_CMD_MAX_ENTRY)
+		return SW_BAD_VALUE;
+
+	l3_exception_cmd.bf.l3_excep_cmd= ctrl->cmd;
+	l3_exception_cmd.bf.de_acce= ctrl->deacclr_en;
+	l3_only_ctrl.bf.excep_en = ctrl->l3route_only_en;
+	l2_only_ctrl.bf.excep_en = ctrl->l2fwd_only_en;
+	l3_flow_ctrl.bf.excep_en = ctrl->l3flow_en;
+	l2_flow_ctrl.bf.excep_en = ctrl->l2flow_en;
+	multicast_ctrl.bf.excep_en = ctrl->multicast_en;
+
+	hppe_l3_exception_cmd_set(dev_id, excep_type, &l3_exception_cmd);
+	hppe_l3_exp_l3_only_ctrl_set(dev_id, excep_type, &l3_only_ctrl);
+	hppe_l3_exp_l2_only_ctrl_set(dev_id, excep_type, &l2_only_ctrl);
+	hppe_l3_exp_l3_flow_ctrl_set(dev_id, excep_type, &l3_flow_ctrl);
+	hppe_l3_exp_l2_flow_ctrl_set(dev_id, excep_type, &l2_flow_ctrl);
+	hppe_l3_exp_multicast_ctrl_set(dev_id, excep_type, &multicast_ctrl);
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_sec_l4_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl)
+{
+	union l4_exception_parsing_ctrl_0_reg_u l4_exception_parsing_ctrl_0;
+	union l4_exception_parsing_ctrl_1_reg_u l4_exception_parsing_ctrl_1;
+	union l4_exception_parsing_ctrl_2_reg_u l4_exception_parsing_ctrl_2;
+	union l4_exception_parsing_ctrl_3_reg_u l4_exception_parsing_ctrl_3;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ctrl);
+
+	hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, &l4_exception_parsing_ctrl_0);
+	hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, &l4_exception_parsing_ctrl_1);
+	hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, &l4_exception_parsing_ctrl_2);
+	hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, &l4_exception_parsing_ctrl_3);
+
+	ctrl->tcp_flags[0] = l4_exception_parsing_ctrl_0.bf.tcp_flags0;
+	ctrl->tcp_flags_mask[0] = l4_exception_parsing_ctrl_0.bf.tcp_flags0_mask;
+	ctrl->tcp_flags[1] = l4_exception_parsing_ctrl_0.bf.tcp_flags1;
+	ctrl->tcp_flags_mask[1] = l4_exception_parsing_ctrl_0.bf.tcp_flags1_mask;
+	ctrl->tcp_flags[2] = l4_exception_parsing_ctrl_1.bf.tcp_flags2;
+	ctrl->tcp_flags_mask[2] = l4_exception_parsing_ctrl_1.bf.tcp_flags2_mask;
+	ctrl->tcp_flags[3] = l4_exception_parsing_ctrl_1.bf.tcp_flags3;
+	ctrl->tcp_flags_mask[3] = l4_exception_parsing_ctrl_1.bf.tcp_flags3_mask;
+	ctrl->tcp_flags[4] = l4_exception_parsing_ctrl_2.bf.tcp_flags4;
+	ctrl->tcp_flags_mask[4] = l4_exception_parsing_ctrl_2.bf.tcp_flags4_mask;
+	ctrl->tcp_flags[5] = l4_exception_parsing_ctrl_2.bf.tcp_flags5;
+	ctrl->tcp_flags_mask[5] = l4_exception_parsing_ctrl_2.bf.tcp_flags5_mask;
+	ctrl->tcp_flags[6] = l4_exception_parsing_ctrl_3.bf.tcp_flags6;
+	ctrl->tcp_flags_mask[6] = l4_exception_parsing_ctrl_3.bf.tcp_flags6_mask;
+	ctrl->tcp_flags[7] = l4_exception_parsing_ctrl_3.bf.tcp_flags7;
+	ctrl->tcp_flags_mask[7] = l4_exception_parsing_ctrl_3.bf.tcp_flags7_mask;
+
+	return SW_OK;
+}
+
+void adpt_hppe_sec_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_sec_func_bitmap = ((1 << FUNC_SEC_L3_EXCEP_CTRL_SET) |
+						(1 << FUNC_SEC_L3_EXCEP_CTRL_GET) |
+						(1 << FUNC_SEC_L3_EXCEP_PARSER_CTRL_SET) |
+						(1 << FUNC_SEC_L3_EXCEP_PARSER_CTRL_GET) |
+						(1 << FUNC_SEC_L4_EXCEP_PARSER_CTRL_SET) |
+						(1 << FUNC_SEC_L4_EXCEP_PARSER_CTRL_GET));
+
+	return;
+}
+
+static void adpt_hppe_sec_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_sec_l3_excep_parser_ctrl_set = NULL;
+	p_adpt_api->adpt_sec_l3_excep_ctrl_get = NULL;
+	p_adpt_api->adpt_sec_l3_excep_parser_ctrl_get = NULL;
+	p_adpt_api->adpt_sec_l4_excep_parser_ctrl_set = NULL;
+	p_adpt_api->adpt_sec_l3_excep_ctrl_set = NULL;
+	p_adpt_api->adpt_sec_l4_excep_parser_ctrl_get = NULL;
+
+	return;
+}
+
+sw_error_t adpt_hppe_sec_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_sec_func_unregister(dev_id, p_adpt_api);
+
+	if (p_adpt_api->adpt_sec_func_bitmap & (1 << FUNC_SEC_L3_EXCEP_PARSER_CTRL_SET))
+	p_adpt_api->adpt_sec_l3_excep_parser_ctrl_set = adpt_hppe_sec_l3_excep_parser_ctrl_set;
+	if (p_adpt_api->adpt_sec_func_bitmap & (1 << FUNC_SEC_L3_EXCEP_CTRL_GET))
+	p_adpt_api->adpt_sec_l3_excep_ctrl_get = adpt_hppe_sec_l3_excep_ctrl_get;
+	if (p_adpt_api->adpt_sec_func_bitmap & (1 << FUNC_SEC_L3_EXCEP_PARSER_CTRL_GET))
+	p_adpt_api->adpt_sec_l3_excep_parser_ctrl_get = adpt_hppe_sec_l3_excep_parser_ctrl_get;
+	if (p_adpt_api->adpt_sec_func_bitmap & (1 << FUNC_SEC_L4_EXCEP_PARSER_CTRL_SET))
+	p_adpt_api->adpt_sec_l4_excep_parser_ctrl_set = adpt_hppe_sec_l4_excep_parser_ctrl_set;
+	if (p_adpt_api->adpt_sec_func_bitmap & (1 << FUNC_SEC_L3_EXCEP_CTRL_SET))
+	p_adpt_api->adpt_sec_l3_excep_ctrl_set = adpt_hppe_sec_l3_excep_ctrl_set;
+	if (p_adpt_api->adpt_sec_func_bitmap & (1 << FUNC_SEC_L4_EXCEP_PARSER_CTRL_GET))
+	p_adpt_api->adpt_sec_l4_excep_parser_ctrl_get = adpt_hppe_sec_l4_excep_parser_ctrl_get;
+
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_servcode.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_servcode.c
new file mode 100755
index 0000000..2696356
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_servcode.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_servcode_reg.h"
+#include "hppe_servcode.h"
+#include "hppe_fdb_reg.h"
+#include "hppe_fdb.h"
+#include "adpt.h"
+
+#define MAX_PHYSICAL_PORT 8
+
+sw_error_t adpt_hppe_servcode_config_set(a_uint32_t dev_id, a_uint32_t servcode_index,
+					fal_servcode_config_t *entry)
+{
+	union in_l2_service_tbl_u in_l2_service_tbl;
+	union service_tbl_u service_tbl;
+	union eg_service_tbl_u eg_service_tbl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	if (servcode_index >= IN_L2_SERVICE_TBL_MAX_ENTRY || entry->dest_port_id >= MAX_PHYSICAL_PORT)
+		return SW_OUT_OF_RANGE;
+
+	in_l2_service_tbl.bf.dst_port_id_valid = entry->dest_port_valid;
+	in_l2_service_tbl.bf.dst_port_id = entry->dest_port_id;
+	in_l2_service_tbl.bf.direction = entry->direction;
+	in_l2_service_tbl.bf.bypass_bitmap = entry->bypass_bitmap[1];
+	in_l2_service_tbl.bf.rx_cnt_en = (entry->bypass_bitmap[2] >> 1) & 0x1;
+	in_l2_service_tbl.bf.tx_cnt_en = (entry->bypass_bitmap[2] >> 3) & 0x1;
+	SW_RTN_ON_ERROR(hppe_in_l2_service_tbl_set(dev_id, servcode_index, &in_l2_service_tbl));
+
+	service_tbl.bf.bypass_bitmap = entry->bypass_bitmap[0];
+	service_tbl.bf.rx_counting_en = entry->bypass_bitmap[2] & 0x1;
+	SW_RTN_ON_ERROR(hppe_service_tbl_set(dev_id, servcode_index, &service_tbl));
+
+	eg_service_tbl.bf.field_update_action = entry->field_update_bitmap;
+	eg_service_tbl.bf.next_service_code = entry->next_service_code;
+	eg_service_tbl.bf.hw_services = entry->hw_services;
+	eg_service_tbl.bf.offset_sel = entry->offset_sel;
+	eg_service_tbl.bf.tx_counting_en = (entry->bypass_bitmap[2] >> 2) & 0x1;
+	SW_RTN_ON_ERROR(hppe_eg_service_tbl_set(dev_id, servcode_index, &eg_service_tbl));
+
+	return SW_OK;
+}
+
+sw_error_t adpt_hppe_servcode_config_get(a_uint32_t dev_id, a_uint32_t servcode_index,
+					fal_servcode_config_t *entry)
+{
+	union in_l2_service_tbl_u in_l2_service_tbl;
+	union service_tbl_u service_tbl;
+	union eg_service_tbl_u eg_service_tbl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	if (servcode_index >= IN_L2_SERVICE_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+
+	SW_RTN_ON_ERROR(hppe_in_l2_service_tbl_get(dev_id, servcode_index, &in_l2_service_tbl));
+	entry->dest_port_valid = in_l2_service_tbl.bf.dst_port_id_valid;
+	entry->dest_port_id = in_l2_service_tbl.bf.dst_port_id;
+	entry->direction = in_l2_service_tbl.bf.direction;
+	entry->bypass_bitmap[1] = in_l2_service_tbl.bf.bypass_bitmap;
+	entry->bypass_bitmap[2] |= in_l2_service_tbl.bf.rx_cnt_en << 1;
+	entry->bypass_bitmap[2] |= in_l2_service_tbl.bf.tx_cnt_en << 3;
+
+	SW_RTN_ON_ERROR(hppe_service_tbl_get(dev_id, servcode_index, &service_tbl));
+	entry->bypass_bitmap[0] = service_tbl.bf.bypass_bitmap;
+	entry->bypass_bitmap[2] |= service_tbl.bf.rx_counting_en;
+
+	SW_RTN_ON_ERROR(hppe_eg_service_tbl_get(dev_id, servcode_index, &eg_service_tbl));
+	entry->field_update_bitmap = eg_service_tbl.bf.field_update_action;
+	entry->next_service_code = eg_service_tbl.bf.next_service_code;
+	entry->hw_services = eg_service_tbl.bf.hw_services;
+	entry->offset_sel = eg_service_tbl.bf.offset_sel;
+	entry->bypass_bitmap[2] |= eg_service_tbl.bf.tx_counting_en << 2;
+
+	return SW_OK;
+}
+
+sw_error_t adpt_hppe_servcode_loopcheck_en(a_uint32_t dev_id, a_bool_t enable)
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+#ifndef IN_FDB_MINI
+	SW_RTN_ON_ERROR(hppe_l2_global_conf_service_code_loop_set(dev_id, enable));
+#endif
+	return SW_OK;
+}
+
+sw_error_t adpt_hppe_servcode_loopcheck_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+#ifndef IN_FDB_MINI
+	SW_RTN_ON_ERROR(hppe_l2_global_conf_service_code_loop_get(dev_id, enable));
+#endif
+	return SW_OK;
+}
+
+void adpt_hppe_servcode_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_servcode_func_bitmap = 0x0;
+
+	return;
+}
+
+static void adpt_hppe_servcode_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_servcode_config_set = NULL;
+	p_adpt_api->adpt_servcode_config_get = NULL;
+	p_adpt_api->adpt_servcode_loopcheck_en = NULL;
+	p_adpt_api->adpt_servcode_loopcheck_status_get = NULL;
+
+	return;
+}
+
+sw_error_t adpt_hppe_servcode_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_servcode_func_unregister(dev_id, p_adpt_api);
+
+	if(p_adpt_api->adpt_servcode_func_bitmap & (1<<FUNC_SERVCODE_CONFIG_SET))
+		p_adpt_api->adpt_servcode_config_set = adpt_hppe_servcode_config_set;
+	if(p_adpt_api->adpt_servcode_func_bitmap & (1<<FUNC_SERVCODE_CONFIG_GET))
+		p_adpt_api->adpt_servcode_config_get = adpt_hppe_servcode_config_get;
+	if(p_adpt_api->adpt_servcode_func_bitmap & (1<<FUNC_SERVCODE_LOOPCHECK_EN))
+		p_adpt_api->adpt_servcode_loopcheck_en = adpt_hppe_servcode_loopcheck_en;
+	if(p_adpt_api->adpt_servcode_func_bitmap & (1<<FUNC_SERVCODE_LOOPCHECK_STATUS_GET))
+		p_adpt_api->adpt_servcode_loopcheck_status_get = adpt_hppe_servcode_loopcheck_status_get;
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
+
+
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_shaper.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_shaper.c
new file mode 100755
index 0000000..af88d16
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_shaper.c
@@ -0,0 +1,1591 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_shaper_reg.h"
+#include "hppe_shaper.h"
+#include "adpt.h"
+
+#define NR_ADPT_HPPE_SHAPER_METER_UNIT         2
+#define NR_ADPT_HPPE_SHAPER_METER_TOKEN_UNIT         8
+#define ADPT_HPPE_SHAPER_METER_UNIT_BYTE       0
+#define ADPT_HPPE_SHAPER_METER_UNIT_FRAME      1
+#define ADPT_HPPE_FREQUENCY      300  /*MHZ*/
+#define ADPT_HPPE_SHAPER_BURST_SIZE_UNIT      65536
+#define ADPT_HPPE_SHAPER_REFRESH_BITS  18
+#define ADPT_HPPE_SHAPER_BUCKET_SIZE_BITS  14
+#define ADPT_HPPE_SHAPER_REFRESH_MAX  ((1 << ADPT_HPPE_SHAPER_REFRESH_BITS) - 1)
+#define ADPT_HPPE_SHAPER_BUCKET_SIZE_MAX  ((1 << ADPT_HPPE_SHAPER_BUCKET_SIZE_BITS) - 1)
+#define ADPT_HPPE_PORT_SHAPER         0
+#define ADPT_HPPE_FLOW_SHAPER         1
+#define ADPT_HPPE_QUEUE_SHAPER       2
+#define BYTE_SHAPER_MAX_RATE 10000000
+#define BYTE_SHAPER_MIN_RATE 64
+#define FRAME_SHAPER_MAX_RATE 14881000
+#define FRAME_SHAPER_MIN_RATE 6
+
+
+
+static a_uint32_t hppe_shaper_token_unit[NR_ADPT_HPPE_SHAPER_METER_UNIT]
+	[NR_ADPT_HPPE_SHAPER_METER_TOKEN_UNIT] = {{2048 * 8,
+	512 * 8,128 * 8,32 * 8,8 * 8,2 * 8, 4, 1},
+	{2097152,524288,131072,32768,8192,2048,512,128}};
+
+typedef struct
+{
+    a_uint64_t rate_1bit;
+    a_uint64_t rate_max;
+} adpt_hppe_shaper_rate_t;
+
+typedef struct
+{
+    a_uint64_t burst_size_1bit;
+    a_uint64_t burst_size_max;
+} adpt_hppe_shaper_burst_size_t;
+
+static adpt_hppe_shaper_rate_t
+hppe_port_shaper_rate[NR_ADPT_HPPE_SHAPER_METER_UNIT][NR_ADPT_HPPE_SHAPER_METER_TOKEN_UNIT] =
+{
+	/* byte based*/
+	{
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+	},
+
+	/*frame based */
+	{
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+	},
+};
+
+static adpt_hppe_shaper_rate_t
+hppe_flow_shaper_rate[NR_ADPT_HPPE_SHAPER_METER_UNIT][NR_ADPT_HPPE_SHAPER_METER_TOKEN_UNIT] =
+{
+	/* byte based*/
+	{
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+	},
+
+	/*frame based */
+	{
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+	},
+};
+
+static adpt_hppe_shaper_rate_t
+hppe_queue_shaper_rate[NR_ADPT_HPPE_SHAPER_METER_UNIT][NR_ADPT_HPPE_SHAPER_METER_TOKEN_UNIT] =
+{
+	/* byte based*/
+	{
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+	},
+
+	/*frame based */
+	{
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+	},
+};
+
+static adpt_hppe_shaper_burst_size_t
+hppe_shaper_burst_size[NR_ADPT_HPPE_SHAPER_METER_UNIT][NR_ADPT_HPPE_SHAPER_METER_TOKEN_UNIT] =
+{
+	{	{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+	},
+	{	{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+		{0,0},
+	},
+};
+
+static sw_error_t
+__adpt_hppe_port_shaper_max_rate(a_uint32_t time_slot)
+{
+	a_uint32_t i = 0, j = 0;
+	a_uint32_t time_cycle;
+	a_uint64_t temp, temp1,temp2;
+
+	/* time_cycle is ns*/
+	time_cycle = ( time_slot * 8);
+
+	for (j = 0; j < 8; j++)
+	{
+		/*max rate unit is bps*/
+		temp1 = (a_uint64_t)(ADPT_HPPE_SHAPER_REFRESH_MAX  * 1000 * 8) * (a_uint64_t)(ADPT_HPPE_FREQUENCY * 1000);
+		temp2 =  hppe_shaper_token_unit[i][j] * time_cycle;
+
+		do_div(temp1, temp2);
+		hppe_port_shaper_rate[i][j].rate_max = temp1;
+
+		temp = temp1;
+		do_div(temp, ADPT_HPPE_SHAPER_REFRESH_MAX);
+		hppe_port_shaper_rate[i][j].rate_1bit = temp;
+
+		//printk("port shaper hppe_max_rate generating =%llu\n", hppe_port_shaper_rate[i][j].rate_max);
+		//printk("port shaper byte step rate =%llu\n", hppe_port_shaper_rate[i][j].rate_1bit);
+	}
+
+	i = i + 1;
+	for (j = 0; j < 8; j++)
+	{
+		/* max rate unit  is 1/1000 pps*/
+		temp1 = (a_uint64_t)(ADPT_HPPE_SHAPER_REFRESH_MAX * 1000) * 1000 * (a_uint64_t)(ADPT_HPPE_FREQUENCY * 1000);
+		temp2 = (a_uint64_t)hppe_shaper_token_unit[i][j] * time_cycle;
+
+		do_div(temp1, temp2);
+		hppe_port_shaper_rate[i][j].rate_max = temp1;
+
+		temp = temp1;
+		do_div(temp, ADPT_HPPE_SHAPER_REFRESH_MAX);
+		hppe_port_shaper_rate[i][j].rate_1bit = temp;
+
+		//printk("port shaper hppe_max_rate generating =%llu\n", hppe_port_shaper_rate[i][j].rate_max);
+		//printk("port shaper frame step rate =%llu\n", hppe_port_shaper_rate[i][j].rate_1bit);
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_hppe_flow_shaper_max_rate(a_uint32_t time_slot)
+{
+	a_uint32_t i = 0, j = 0;
+	a_uint32_t time_cycle;
+	a_uint64_t temp, temp1,temp2;
+
+	/* time_cycle is ns*/
+	time_cycle = ( time_slot * 8);
+
+	for (j = 0; j < 8; j++)
+	{
+		/*max rate unit is bps*/
+		temp1 = (a_uint64_t)(ADPT_HPPE_SHAPER_REFRESH_MAX  * 1000 * 8) * (a_uint64_t)(ADPT_HPPE_FREQUENCY * 1000);
+		temp2 =  hppe_shaper_token_unit[i][j] * time_cycle;
+
+		do_div(temp1, temp2);
+		hppe_flow_shaper_rate[i][j].rate_max = temp1;
+
+		temp = temp1;
+		do_div(temp, ADPT_HPPE_SHAPER_REFRESH_MAX);
+		hppe_flow_shaper_rate[i][j].rate_1bit = temp;
+
+		//printk("flow shaper hppe_max_rate generating =%llu\n", hppe_flow_shaper_rate[i][j].rate_max);
+		//printk("flow shaper byte step rate =%llu\n", hppe_flow_shaper_rate[i][j].rate_1bit);
+	}
+
+	i = i + 1;
+	for (j = 0; j < 8; j++)
+	{
+		/* max rate unit  is 1/1000 pps*/
+		temp1 = (a_uint64_t)(ADPT_HPPE_SHAPER_REFRESH_MAX * 1000) * 1000 * (a_uint64_t)(ADPT_HPPE_FREQUENCY * 1000);
+		temp2 = (a_uint64_t)hppe_shaper_token_unit[i][j] * time_cycle;
+
+		do_div(temp1, temp2);
+		hppe_flow_shaper_rate[i][j].rate_max = temp1;
+
+		temp = temp1;
+		do_div(temp, ADPT_HPPE_SHAPER_REFRESH_MAX);
+		hppe_flow_shaper_rate[i][j].rate_1bit = temp;
+
+		//printk("flow shaper hppe_max_rate generating =%llu\n", hppe_flow_shaper_rate[i][j].rate_max);
+		//printk("flow shaper frame step rate =%llu\n", hppe_flow_shaper_rate[i][j].rate_1bit);
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_hppe_queue_shaper_max_rate(a_uint32_t time_slot)
+{
+	a_uint32_t i = 0, j = 0;
+	a_uint32_t time_cycle;
+	a_uint64_t temp, temp1,temp2;
+
+
+	/* time_cycle is ns*/
+	time_cycle = ( time_slot * 8) /ADPT_HPPE_FREQUENCY;
+
+	for (j = 0; j < 8; j++)
+	{
+		/*max rate unit is bps*/
+		temp1 = (a_uint64_t)(ADPT_HPPE_SHAPER_REFRESH_MAX  * 1000 * 8) * 1000;
+		temp2 =  hppe_shaper_token_unit[i][j] * time_cycle;
+
+		do_div(temp1, temp2);
+		hppe_queue_shaper_rate[i][j].rate_max = temp1;
+
+		temp = temp1;
+		do_div(temp, ADPT_HPPE_SHAPER_REFRESH_MAX);
+		hppe_queue_shaper_rate[i][j].rate_1bit = temp;
+
+		//printk("queue shaper hppe_max_rate generating =%llu\n", hppe_queue_shaper_rate[i][j].rate_max);
+		//printk("queue shaper byte step rate =%llu\n", hppe_queue_shaper_rate[i][j].rate_1bit);
+	}
+
+	i = i + 1;
+	for (j = 0; j < 8; j++)
+	{
+		/* max rate unit  is 1/1000 pps*/
+		temp1 = (a_uint64_t)(ADPT_HPPE_SHAPER_REFRESH_MAX * 1000) * 1000 * 1000;
+		temp2 = (a_uint64_t)hppe_shaper_token_unit[i][j] * time_cycle;
+
+		do_div(temp1, temp2);
+		hppe_queue_shaper_rate[i][j].rate_max = temp1;
+
+		temp = temp1;
+		do_div(temp, ADPT_HPPE_SHAPER_REFRESH_MAX);
+		hppe_queue_shaper_rate[i][j].rate_1bit = temp;
+
+		//printk("queue shaper hppe_max_rate generating =%llu\n", hppe_queue_shaper_rate[i][j].rate_max);
+		//printk("queue shaper frame step rate =%llu\n", hppe_queue_shaper_rate[i][j].rate_1bit);
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_hppe_shaper_max_burst_size(void)
+{
+	a_uint32_t i = 0, j = 0;
+	a_uint64_t temp = 0, temp1 = 0;
+
+	for (j = 0; j < 8; j++)
+	{
+		/*max size unit is 1/1000 byte based*/
+		temp = (a_uint64_t)(ADPT_HPPE_SHAPER_BURST_SIZE_UNIT * ADPT_HPPE_SHAPER_BUCKET_SIZE_MAX);
+		do_div(temp, hppe_shaper_token_unit[i][j]);
+		hppe_shaper_burst_size[i][j].burst_size_max = (a_uint64_t)(temp * 1000);
+
+		temp1 = hppe_shaper_burst_size[i][j].burst_size_max;
+		do_div(temp1, ADPT_HPPE_SHAPER_BUCKET_SIZE_MAX);
+		hppe_shaper_burst_size[i][j].burst_size_1bit = temp1;
+
+		//printk("shpaer byte hppe_max_burst_size generating =%llu\n", hppe_shaper_burst_size[i][j].burst_size_max);
+		//printk("shpaer byte hppe_max_burst_size step  =%llu\n", hppe_shaper_burst_size[i][j].burst_size_1bit);
+	}
+
+	i = i + 1;
+	for (j = 0; j < 8; j++)
+	{
+		/* max size unit is 1/1000 frame based */
+		temp = (a_uint64_t)(ADPT_HPPE_SHAPER_BURST_SIZE_UNIT * ADPT_HPPE_SHAPER_BUCKET_SIZE_MAX);
+		do_div(temp, hppe_shaper_token_unit[i][j]);
+		hppe_shaper_burst_size[i][j].burst_size_max = (a_uint64_t)(temp * 1000);
+
+		temp1 = hppe_shaper_burst_size[i][j].burst_size_max;
+		do_div(temp1, ADPT_HPPE_SHAPER_BUCKET_SIZE_MAX);
+		hppe_shaper_burst_size[i][j].burst_size_1bit = temp1;
+
+		//printk("shaper frame hppe_max_burst_size generating =%llu\n", hppe_shaper_burst_size[i][j].burst_size_max);
+		//printk("shpaer frame hppe_max_burst_size step  =%llu\n", hppe_shaper_burst_size[i][j].burst_size_1bit);
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_hppe_shaper_one_bucket_parameter_select(a_uint32_t shaper_type,
+						a_uint64_t c_rate,
+						a_uint64_t c_burst_size,
+						a_uint32_t meter_unit,
+						a_uint32_t *token_unit)
+{
+	a_uint32_t  temp_token_unit = 0;
+	a_uint32_t  match = A_FALSE;
+	a_uint64_t  max_rate =0;
+
+	for (temp_token_unit = 0; temp_token_unit < 8; temp_token_unit++)
+	{
+		if (ADPT_HPPE_PORT_SHAPER == shaper_type)
+			max_rate = hppe_port_shaper_rate[meter_unit][temp_token_unit].rate_max;
+
+		if (ADPT_HPPE_FLOW_SHAPER == shaper_type)
+			max_rate = hppe_flow_shaper_rate[meter_unit][temp_token_unit].rate_max;
+
+		if (ADPT_HPPE_QUEUE_SHAPER == shaper_type)
+			max_rate = hppe_queue_shaper_rate[meter_unit][temp_token_unit].rate_max;
+
+		if (c_rate > max_rate)
+		{
+			continue;
+		}
+		else if (c_burst_size <= hppe_shaper_burst_size[meter_unit][temp_token_unit].burst_size_max)
+		{
+			*token_unit = temp_token_unit;
+			match = A_TRUE;
+			break;
+		}
+	}
+
+	if (match == A_FALSE)
+	{
+		printk("Not match  shaper C token bucket parameter rate configuration\n");
+		return SW_BAD_PARAM;
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_hppe_shaper_two_bucket_parameter_select(a_uint32_t shaper_type,
+						a_uint64_t c_rate,
+						a_uint64_t c_burst_size,
+						a_uint64_t e_rate,
+						a_uint64_t e_burst_size,
+						a_uint32_t meter_unit,
+						a_uint32_t *token_unit)
+{
+	a_uint32_t  temp_token_unit;
+	a_uint32_t  match = A_FALSE;
+	a_uint64_t  max_rate = 0, temp_rate = 0, temp_burst_size = 0;
+
+	if(c_rate > e_rate)
+		temp_rate = c_rate;
+	else
+		temp_rate = e_rate;
+
+	if(c_burst_size > e_burst_size)
+		temp_burst_size = c_burst_size;
+	else
+		temp_burst_size = e_burst_size;
+
+	for (temp_token_unit = 0; temp_token_unit < 8; temp_token_unit++)
+	{
+		if (ADPT_HPPE_PORT_SHAPER == shaper_type)
+			max_rate = hppe_port_shaper_rate[meter_unit][temp_token_unit].rate_max;
+
+		if (ADPT_HPPE_FLOW_SHAPER == shaper_type)
+			max_rate = hppe_flow_shaper_rate[meter_unit][temp_token_unit].rate_max;
+
+		if (ADPT_HPPE_QUEUE_SHAPER == shaper_type)
+			max_rate = hppe_queue_shaper_rate[meter_unit][temp_token_unit].rate_max;
+
+		 if (temp_rate > max_rate)
+		 {
+		 	continue;
+		 }
+		 else if(temp_burst_size <= hppe_shaper_burst_size[meter_unit][temp_token_unit].burst_size_max)
+		{
+			*token_unit = temp_token_unit;
+			match = A_TRUE;
+			break;
+		}
+	}
+
+	if (match == A_FALSE)
+	{
+		printk("Not match shaper  C and E token bucket parameter rate configuration \n");
+		return SW_BAD_PARAM;
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_hppe_shaper_rate_to_refresh(a_uint32_t shaper_type,
+							a_uint32_t rate,
+							a_uint32_t *refresh,
+							a_bool_t meter_unit,
+							a_uint32_t  token_unit)
+{
+	a_uint32_t temp_refresh;
+	a_uint64_t temp_rate, temp_rate_1bit;
+
+	temp_rate_1bit = 0;
+
+	if (ADPT_HPPE_PORT_SHAPER == shaper_type)
+	{
+		temp_rate_1bit = hppe_port_shaper_rate[meter_unit][token_unit].rate_1bit;
+	}
+
+	if (ADPT_HPPE_FLOW_SHAPER == shaper_type)
+	{
+		temp_rate_1bit = hppe_flow_shaper_rate[meter_unit][token_unit].rate_1bit;
+	}
+
+	if (ADPT_HPPE_QUEUE_SHAPER == shaper_type)
+	{
+		temp_rate_1bit = hppe_queue_shaper_rate[meter_unit][token_unit].rate_1bit;
+	}
+
+	if(temp_rate_1bit > 0)
+	{
+		temp_rate = ((a_uint64_t)rate) * 1000;
+		do_div(temp_rate, temp_rate_1bit);
+		temp_refresh = temp_rate;
+	}
+	else
+	{
+		return SW_BAD_PARAM;
+	}
+
+	if (temp_refresh > ADPT_HPPE_SHAPER_REFRESH_MAX)
+	{
+		temp_refresh = ADPT_HPPE_SHAPER_REFRESH_MAX;
+	}
+
+	*refresh = temp_refresh;
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_hppe_shaper_burst_size_to_bucket_size(a_uint32_t burst_size,
+							a_uint32_t *bucket_size,
+							a_bool_t meter_unit,
+							a_uint32_t  token_unit)
+{
+	a_uint32_t temp_bucket_size;
+	a_uint64_t temp_burst_size;
+
+	if(hppe_shaper_burst_size[meter_unit][token_unit].burst_size_1bit > 0)
+	{
+		temp_burst_size = ((a_uint64_t)burst_size) * 1000;
+		do_div(temp_burst_size, hppe_shaper_burst_size[meter_unit][token_unit].burst_size_1bit);
+		temp_bucket_size = temp_burst_size;
+	}
+	else
+	{
+		return SW_BAD_PARAM;
+	}
+
+	if(temp_bucket_size > ADPT_HPPE_SHAPER_BUCKET_SIZE_MAX)
+	{
+		temp_bucket_size = ADPT_HPPE_SHAPER_BUCKET_SIZE_MAX;
+	}
+
+	*bucket_size = temp_bucket_size;
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_hppe_shaper_refresh_to_rate(a_uint32_t shaper_type,
+							a_uint32_t refresh,
+							a_uint32_t *rate,
+							a_bool_t meter_unit,
+							a_uint32_t  token_unit)
+{
+	a_uint32_t temp_rate;
+	a_uint64_t temp_refresh, temp_rate_1bit;
+
+	temp_rate_1bit = 0;
+
+	if (ADPT_HPPE_PORT_SHAPER == shaper_type)
+	{
+		temp_rate_1bit = hppe_port_shaper_rate[meter_unit][token_unit].rate_1bit;
+	}
+
+	if (ADPT_HPPE_FLOW_SHAPER == shaper_type)
+	{
+		temp_rate_1bit = hppe_flow_shaper_rate[meter_unit][token_unit].rate_1bit;
+	}
+
+	if (ADPT_HPPE_QUEUE_SHAPER == shaper_type)
+	{
+		temp_rate_1bit = hppe_queue_shaper_rate[meter_unit][token_unit].rate_1bit;
+	}
+
+	if(temp_rate_1bit > 0)
+	{
+		temp_refresh = ((a_uint64_t)refresh) * temp_rate_1bit;
+		do_div(temp_refresh, 1000);
+		temp_rate = temp_refresh;
+	}
+	else
+	{
+		return SW_BAD_PARAM;
+	}
+
+	*rate = temp_rate;
+
+	return SW_OK;
+}
+static sw_error_t
+__adpt_hppe_shaper_bucket_size_to_burst_size(a_uint32_t bucket_size,
+							a_uint32_t *burst_size,
+							a_bool_t meter_unit,
+							a_uint32_t  token_unit)
+{
+	a_uint32_t temp_burst_size;
+	a_uint64_t temp_bucket_size;
+
+	if(hppe_shaper_burst_size[meter_unit][token_unit].burst_size_1bit > 0)
+	{
+		temp_bucket_size = ((a_uint64_t)bucket_size) * hppe_shaper_burst_size[meter_unit][token_unit].burst_size_1bit;
+		do_div(temp_bucket_size, 1000);
+		temp_burst_size = temp_bucket_size;
+	}
+	else
+	{
+		return SW_BAD_PARAM;
+	}
+
+	*burst_size = temp_burst_size;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_queue_shaper_get(a_uint32_t dev_id, a_uint32_t queue_id,
+		fal_shaper_config_t * shaper)
+{
+	sw_error_t rv = SW_OK;
+	union l0_shp_cfg_tbl_u l0_shp_cfg_tbl;
+	union l0_comp_cfg_tbl_u l0_comp_cfg_tbl;
+	a_uint32_t hppe_cir =0, hppe_cbs = 0, hppe_eir = 0, hppe_ebs = 0;
+
+	memset(&l0_shp_cfg_tbl, 0, sizeof(l0_shp_cfg_tbl));
+	memset(&l0_comp_cfg_tbl, 0, sizeof(l0_comp_cfg_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(shaper);
+
+	if ((queue_id < 0) || (queue_id > 299))
+		return SW_BAD_PARAM;
+
+	hppe_l0_comp_cfg_tbl_get(dev_id, queue_id, &l0_comp_cfg_tbl);
+
+
+	rv = hppe_l0_shp_cfg_tbl_get(dev_id, queue_id, &l0_shp_cfg_tbl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	hppe_cir = l0_shp_cfg_tbl.bf.cir;
+	hppe_cbs = l0_shp_cfg_tbl.bf.cbs;
+	hppe_eir = l0_shp_cfg_tbl.bf.eir;
+	hppe_ebs = l0_shp_cfg_tbl.bf.ebs;
+
+	__adpt_hppe_shaper_refresh_to_rate(ADPT_HPPE_QUEUE_SHAPER,
+								hppe_cir,
+								&shaper->cir,
+								l0_shp_cfg_tbl.bf.meter_unit,
+								l0_shp_cfg_tbl.bf.token_unit);
+
+	__adpt_hppe_shaper_refresh_to_rate(ADPT_HPPE_QUEUE_SHAPER,
+								hppe_eir,
+								&shaper->eir,
+								l0_shp_cfg_tbl.bf.meter_unit,
+								l0_shp_cfg_tbl.bf.token_unit);
+
+
+	__adpt_hppe_shaper_bucket_size_to_burst_size(hppe_cbs,
+								&shaper->cbs,
+								l0_shp_cfg_tbl.bf.meter_unit,
+								l0_shp_cfg_tbl.bf.token_unit);
+
+	__adpt_hppe_shaper_bucket_size_to_burst_size(hppe_ebs,
+								&shaper->ebs,
+								l0_shp_cfg_tbl.bf.meter_unit,
+								l0_shp_cfg_tbl.bf.token_unit);
+
+
+	shaper->couple_en = l0_shp_cfg_tbl.bf.cf;
+	shaper->meter_unit = l0_shp_cfg_tbl.bf.meter_unit;
+	shaper->c_shaper_en = l0_shp_cfg_tbl.bf.c_shaper_enable;
+	shaper->e_shaper_en = l0_shp_cfg_tbl.bf.e_shaper_enable;
+	shaper->shaper_frame_mode = l0_comp_cfg_tbl.bf.shaper_meter_len;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_queue_shaper_token_number_set(a_uint32_t dev_id,a_uint32_t queue_id,
+		fal_shaper_token_number_t *token_number)
+{
+	union l0_shp_credit_tbl_u l0_shp_credit_tbl;
+
+	memset(&l0_shp_credit_tbl, 0, sizeof(l0_shp_credit_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(token_number);
+
+	if ((queue_id < 0) || (queue_id > 299))
+		return SW_BAD_PARAM;
+
+	hppe_l0_shp_credit_tbl_get(dev_id, queue_id, &l0_shp_credit_tbl);
+
+
+	l0_shp_credit_tbl.bf.c_shaper_credit_neg = token_number->c_token_number_negative_en;
+	l0_shp_credit_tbl.bf.c_shaper_credit = token_number->c_token_number;
+	l0_shp_credit_tbl.bf.e_shaper_credit_neg = token_number->e_token_number_negative_en;
+	l0_shp_credit_tbl.bf.e_shaper_credit_0 = token_number->e_token_number & 0x1;
+	l0_shp_credit_tbl.bf.e_shaper_credit_1 = token_number->e_token_number >> 1;
+
+	hppe_l0_shp_credit_tbl_set(dev_id, queue_id, &l0_shp_credit_tbl);
+
+	return SW_OK;
+}
+#ifndef IN_SHAPER_MINI
+sw_error_t
+adpt_hppe_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_config_t * shaper)
+{
+	union psch_shp_cfg_tbl_u psch_shp_cfg_tbl;
+	union psch_comp_cfg_tbl_u psch_comp_cfg_tbl;
+	a_uint32_t hppe_cir =0, hppe_cbs = 0;
+
+	memset(&psch_shp_cfg_tbl, 0, sizeof(psch_shp_cfg_tbl));
+	memset(&psch_comp_cfg_tbl, 0, sizeof(psch_comp_cfg_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(shaper);
+
+	if (port_id < 0 || port_id > 7)
+		return SW_BAD_PARAM;
+
+	hppe_psch_shp_cfg_tbl_get(dev_id, port_id, &psch_shp_cfg_tbl);
+
+	hppe_cir = psch_shp_cfg_tbl.bf.cir;
+	hppe_cbs = psch_shp_cfg_tbl.bf.cbs;
+
+	hppe_psch_comp_cfg_tbl_get(dev_id, port_id, &psch_comp_cfg_tbl);
+
+
+	__adpt_hppe_shaper_refresh_to_rate(ADPT_HPPE_PORT_SHAPER,
+								hppe_cir,
+								&shaper->cir,
+								psch_shp_cfg_tbl.bf.meter_unit,
+								psch_shp_cfg_tbl.bf.token_unit);
+
+
+	__adpt_hppe_shaper_bucket_size_to_burst_size(hppe_cbs,
+								&shaper->cbs,
+								psch_shp_cfg_tbl.bf.meter_unit,
+								psch_shp_cfg_tbl.bf.token_unit);
+
+	shaper->meter_unit = psch_shp_cfg_tbl.bf.meter_unit;
+	shaper->c_shaper_en = psch_shp_cfg_tbl.bf.shaper_enable;
+
+	shaper->shaper_frame_mode = psch_comp_cfg_tbl.bf.shaper_meter_len;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_flow_shaper_time_slot_get(a_uint32_t dev_id, a_uint32_t *time_slot)
+{
+	sw_error_t rv = SW_OK;
+	union shp_slot_cfg_l1_u shp_slot_cfg_l1;
+
+	memset(&shp_slot_cfg_l1, 0, sizeof(shp_slot_cfg_l1));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time_slot);
+
+
+	rv = hppe_shp_slot_cfg_l1_get(dev_id, &shp_slot_cfg_l1);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*time_slot = shp_slot_cfg_l1.bf.l1_shp_slot_time;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_shaper_time_slot_get(a_uint32_t dev_id, a_uint32_t *time_slot)
+{
+	sw_error_t rv = SW_OK;
+	union shp_slot_cfg_port_u shp_slot_cfg_port;
+
+	memset(&shp_slot_cfg_port, 0, sizeof(shp_slot_cfg_port));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time_slot);
+
+	rv = hppe_shp_slot_cfg_port_get(dev_id, &shp_slot_cfg_port);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*time_slot = shp_slot_cfg_port.bf.port_shp_slot_time;
+
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+adpt_hppe_flow_shaper_time_slot_set(a_uint32_t dev_id, a_uint32_t time_slot)
+{
+	union shp_slot_cfg_l1_u shp_slot_cfg_l1;
+	sw_error_t rv = SW_OK;
+
+	memset(&shp_slot_cfg_l1, 0, sizeof(shp_slot_cfg_l1));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if ((time_slot < 0x40) || (time_slot > 0xfff))
+		return SW_BAD_PARAM;
+
+	rv = hppe_shp_slot_cfg_l1_get(dev_id, &shp_slot_cfg_l1);
+
+	if( rv != SW_OK )
+		return rv;
+
+	shp_slot_cfg_l1.bf.l1_shp_slot_time = time_slot;
+	hppe_shp_slot_cfg_l1_set(dev_id, &shp_slot_cfg_l1);
+
+	__adpt_hppe_flow_shaper_max_rate(time_slot);
+
+	return SW_OK;
+
+}
+sw_error_t
+adpt_hppe_port_shaper_token_number_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_token_number_t *token_number)
+{
+	union psch_shp_credit_tbl_u psch_shp_credit_tbl;
+	union psch_shp_sign_tbl_u psch_shp_sign_tbl;
+
+	memset(&psch_shp_credit_tbl, 0, sizeof(psch_shp_credit_tbl));
+	memset(&psch_shp_sign_tbl, 0, sizeof(psch_shp_sign_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(token_number);
+
+	if (port_id < 0 || port_id > 7)
+		return SW_BAD_PARAM;
+
+	hppe_psch_shp_credit_tbl_get(dev_id, port_id, &psch_shp_credit_tbl);
+	hppe_psch_shp_sign_tbl_get(dev_id, port_id, &psch_shp_sign_tbl);
+
+
+	psch_shp_sign_tbl.bf.shaper_credit_neg = token_number->c_token_number_negative_en;
+
+	psch_shp_credit_tbl.bf.shaper_credit = token_number->c_token_number;
+
+	hppe_psch_shp_credit_tbl_set(dev_id, port_id, &psch_shp_credit_tbl);
+
+	hppe_psch_shp_sign_tbl_set(dev_id, port_id, &psch_shp_sign_tbl);
+
+	return SW_OK;
+}
+#ifndef IN_SHAPER_MINI
+sw_error_t
+adpt_hppe_queue_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t queue_id,
+		fal_shaper_token_number_t *token_number)
+{
+	sw_error_t rv = SW_OK;
+	union l0_shp_credit_tbl_u l0_shp_credit_tbl;
+
+	memset(&l0_shp_credit_tbl, 0, sizeof(l0_shp_credit_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(token_number);
+
+	if ((queue_id < 0) || (queue_id > 299))
+		return SW_BAD_PARAM;
+
+	rv = hppe_l0_shp_credit_tbl_get(dev_id, queue_id, &l0_shp_credit_tbl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	token_number->c_token_number_negative_en = l0_shp_credit_tbl.bf.c_shaper_credit_neg;
+	token_number->c_token_number = l0_shp_credit_tbl.bf.c_shaper_credit;
+	token_number->e_token_number_negative_en = l0_shp_credit_tbl.bf.e_shaper_credit_neg;
+	token_number->e_token_number = l0_shp_credit_tbl.bf.e_shaper_credit_0 | (l0_shp_credit_tbl.bf.e_shaper_credit_1 << 1);
+
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_queue_shaper_time_slot_get(a_uint32_t dev_id, a_uint32_t *time_slot)
+{
+	sw_error_t rv = SW_OK;
+	union shp_slot_cfg_l0_u shp_slot_cfg_l0;
+
+	memset(&shp_slot_cfg_l0, 0, sizeof(shp_slot_cfg_l0));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(time_slot);
+
+
+	rv = hppe_shp_slot_cfg_l0_get(dev_id, &shp_slot_cfg_l0);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*time_slot = shp_slot_cfg_l0.bf.l0_shp_slot_time;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_port_shaper_token_number_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_token_number_t *token_number)
+{
+	union psch_shp_credit_tbl_u psch_shp_credit_tbl;
+	union psch_shp_sign_tbl_u psch_shp_sign_tbl;
+
+	memset(&psch_shp_credit_tbl, 0, sizeof(psch_shp_credit_tbl));
+	memset(&psch_shp_sign_tbl, 0, sizeof(psch_shp_sign_tbl));
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(token_number);
+
+	if (port_id < 0 || port_id > 7)
+		return SW_BAD_PARAM;
+
+	hppe_psch_shp_credit_tbl_get(dev_id, port_id, &psch_shp_credit_tbl);
+
+	hppe_psch_shp_sign_tbl_get(dev_id, port_id, &psch_shp_sign_tbl);
+
+
+	token_number->c_token_number_negative_en = psch_shp_sign_tbl.bf.shaper_credit_neg;
+	token_number->c_token_number = psch_shp_credit_tbl.bf.shaper_credit;
+
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+adpt_hppe_flow_shaper_token_number_set(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_token_number_t *token_number)
+{
+	union l1_shp_credit_tbl_u l1_shp_credit_tbl;
+
+	memset(&l1_shp_credit_tbl, 0, sizeof(l1_shp_credit_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(token_number);
+
+	if ((flow_id < 0) || (flow_id > 63))
+		return SW_BAD_PARAM;
+
+
+	l1_shp_credit_tbl.bf.c_shaper_credit_neg = token_number->c_token_number_negative_en;
+	l1_shp_credit_tbl.bf.c_shaper_credit = token_number->c_token_number;
+	l1_shp_credit_tbl.bf.e_shaper_credit_neg = token_number->e_token_number_negative_en;
+	l1_shp_credit_tbl.bf.e_shaper_credit_0 = token_number->e_token_number & 0x1;
+	l1_shp_credit_tbl.bf.e_shaper_credit_1 = token_number->e_token_number >> 1;
+
+	hppe_l1_shp_credit_tbl_set(dev_id, flow_id, &l1_shp_credit_tbl);
+
+	return SW_OK;
+}
+#ifndef IN_SHAPER_MINI
+sw_error_t
+adpt_hppe_flow_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_token_number_t *token_number)
+{
+	sw_error_t rv = SW_OK;
+	union l1_shp_credit_tbl_u l1_shp_credit_tbl;
+
+	memset(&l1_shp_credit_tbl, 0, sizeof(l1_shp_credit_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(token_number);
+
+	if ((flow_id < 0) || (flow_id > 63))
+		return SW_BAD_PARAM;
+
+	rv = hppe_l1_shp_credit_tbl_get(dev_id, flow_id, &l1_shp_credit_tbl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	token_number->c_token_number_negative_en = l1_shp_credit_tbl.bf.c_shaper_credit_neg;
+	token_number->c_token_number = l1_shp_credit_tbl.bf.c_shaper_credit;
+	token_number->e_token_number_negative_en = l1_shp_credit_tbl.bf.e_shaper_credit_neg;
+	token_number->e_token_number = l1_shp_credit_tbl.bf.e_shaper_credit_0 |
+		(l1_shp_credit_tbl.bf.e_shaper_credit_1 << 1);
+
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+adpt_hppe_flow_shaper_set(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_config_t * shaper)
+{
+	sw_error_t rv = SW_OK;
+	union l1_shp_cfg_tbl_u l1_shp_cfg_tbl;
+	union l1_comp_cfg_tbl_u l1_comp_cfg_tbl;
+	a_uint32_t hppe_cir = 0, hppe_cbs = 0, hppe_eir= 0, hppe_ebs = 0;
+	a_uint64_t temp_cir = 0, temp_eir =0, temp_cbs =0, temp_ebs = 0;
+	a_uint32_t token_unit = 0;
+	fal_shaper_token_number_t token_number;
+
+	memset(&l1_shp_cfg_tbl, 0, sizeof(l1_shp_cfg_tbl));
+	memset(&l1_comp_cfg_tbl, 0, sizeof(l1_comp_cfg_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(shaper);
+
+	if ((flow_id < 0) || (flow_id > 63))
+		return SW_BAD_PARAM;
+
+	if(ADPT_HPPE_SHAPER_METER_UNIT_BYTE == shaper->meter_unit)
+	{
+		if ((shaper->cir > BYTE_SHAPER_MAX_RATE) || (shaper->eir > BYTE_SHAPER_MAX_RATE))
+			return SW_BAD_PARAM;
+		if ((shaper->cir < BYTE_SHAPER_MIN_RATE) && (shaper->cir != 0))
+			return SW_BAD_PARAM;
+		if ((shaper->eir < BYTE_SHAPER_MIN_RATE) && (shaper->eir != 0))
+			return SW_BAD_PARAM;
+	}
+	if(ADPT_HPPE_SHAPER_METER_UNIT_FRAME == shaper->meter_unit)
+	{
+		if ((shaper->cir > FRAME_SHAPER_MAX_RATE) || (shaper->eir > FRAME_SHAPER_MAX_RATE))
+			return SW_BAD_PARAM;
+		if ((shaper->cir < FRAME_SHAPER_MIN_RATE) && (shaper->cir != 0))
+			return SW_BAD_PARAM;
+		if ((shaper->eir < FRAME_SHAPER_MIN_RATE) && (shaper->eir != 0))
+			return SW_BAD_PARAM;
+	}
+
+	hppe_l1_comp_cfg_tbl_get(dev_id, flow_id, &l1_comp_cfg_tbl);
+
+	temp_cir = ((a_uint64_t)shaper->cir) * 1000;
+	temp_cbs = ((a_uint64_t)shaper->cbs) * 1000;
+	temp_eir = ((a_uint64_t)shaper->eir) * 1000;
+	temp_ebs = ((a_uint64_t)shaper->ebs) * 1000;
+
+	rv = __adpt_hppe_shaper_two_bucket_parameter_select(ADPT_HPPE_FLOW_SHAPER,
+								temp_cir,
+								temp_cbs,
+								temp_eir,
+								temp_ebs,
+								shaper->meter_unit,
+								&token_unit);
+	if( rv != SW_OK )
+		return rv;
+	//printk("flow shaper meter unit is = %d\n", shaper->meter_unit);
+	//printk("flow shaper token unit is = %d\n", token_unit);
+
+		__adpt_hppe_shaper_rate_to_refresh(ADPT_HPPE_FLOW_SHAPER,
+									shaper->cir,
+									&hppe_cir,
+									shaper->meter_unit,
+									token_unit);
+
+		__adpt_hppe_shaper_rate_to_refresh(ADPT_HPPE_FLOW_SHAPER,
+									shaper->eir,
+									&hppe_eir,
+									shaper->meter_unit,
+									token_unit);
+
+		__adpt_hppe_shaper_burst_size_to_bucket_size(shaper->cbs,
+									&hppe_cbs,
+									shaper->meter_unit,
+									token_unit);
+
+		__adpt_hppe_shaper_burst_size_to_bucket_size(shaper->ebs,
+									&hppe_ebs,
+									shaper->meter_unit,
+									token_unit);
+
+	l1_shp_cfg_tbl.bf.cf = shaper->couple_en;
+	l1_shp_cfg_tbl.bf.meter_unit = shaper->meter_unit;
+	l1_shp_cfg_tbl.bf.c_shaper_enable = shaper->c_shaper_en;
+	l1_shp_cfg_tbl.bf.cbs = hppe_cbs;
+	l1_shp_cfg_tbl.bf.cir = hppe_cir;
+	l1_shp_cfg_tbl.bf.e_shaper_enable = shaper->e_shaper_en;
+	l1_shp_cfg_tbl.bf.ebs = hppe_ebs;
+	l1_shp_cfg_tbl.bf.eir = hppe_eir;
+	l1_shp_cfg_tbl.bf.token_unit = token_unit;
+	l1_comp_cfg_tbl.bf.shaper_meter_len = shaper->shaper_frame_mode;
+
+	hppe_l1_shp_cfg_tbl_set(dev_id, flow_id, &l1_shp_cfg_tbl);
+
+	hppe_l1_comp_cfg_tbl_set(dev_id, flow_id, &l1_comp_cfg_tbl);
+
+	if( A_FALSE == shaper->c_shaper_en)
+	{
+		token_number.c_token_number_negative_en = 0;
+		token_number.c_token_number = 0;
+		adpt_hppe_flow_shaper_token_number_set(dev_id, flow_id, &token_number);
+	}
+	if( A_FALSE == shaper->e_shaper_en)
+	{
+		token_number.e_token_number_negative_en = 0;
+		token_number.e_token_number = 0;
+		adpt_hppe_flow_shaper_token_number_set(dev_id, flow_id, &token_number);
+	}
+
+	return SW_OK;
+}
+sw_error_t
+adpt_hppe_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_config_t * shaper)
+{
+	sw_error_t rv = SW_OK;
+	union psch_shp_cfg_tbl_u psch_shp_cfg_tbl;
+	union psch_comp_cfg_tbl_u psch_comp_cfg_tbl;
+	a_uint64_t temp_cir = 0,temp_cbs;
+	a_uint32_t hppe_cir = 0, hppe_cbs = 0;
+	a_uint32_t token_unit = 0;
+	fal_shaper_token_number_t token_number;
+
+	memset(&psch_shp_cfg_tbl, 0, sizeof(psch_shp_cfg_tbl));
+	memset(&psch_comp_cfg_tbl, 0, sizeof(psch_comp_cfg_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(shaper);
+
+	if (port_id < 0 || port_id > 7)
+		return SW_BAD_PARAM;
+
+	if(ADPT_HPPE_SHAPER_METER_UNIT_BYTE == shaper->meter_unit)
+	{
+		if (shaper->cir > BYTE_SHAPER_MAX_RATE)
+			return SW_BAD_PARAM;
+		if ((shaper->cir < BYTE_SHAPER_MIN_RATE) && (shaper->cir != 0))
+			return SW_BAD_PARAM;
+	}
+	if(ADPT_HPPE_SHAPER_METER_UNIT_FRAME == shaper->meter_unit)
+	{
+		if (shaper->cir > FRAME_SHAPER_MAX_RATE)
+			return SW_BAD_PARAM;
+		if ((shaper->cir < FRAME_SHAPER_MIN_RATE) && (shaper->cir != 0))
+			return SW_BAD_PARAM;
+	}
+
+	temp_cir = ((a_uint64_t)shaper->cir) * 1000;
+	temp_cbs = ((a_uint64_t)shaper->cbs) * 1000;
+
+	rv = __adpt_hppe_shaper_one_bucket_parameter_select(ADPT_HPPE_PORT_SHAPER,
+								temp_cir,
+								temp_cbs,
+								shaper->meter_unit,
+								&token_unit);
+	if( rv != SW_OK )
+		return rv;
+
+	// printk("current shaper meter unit is = %d\n", shaper->meter_unit);
+	// printk("current shaper token unit is = %d\n", token_unit);
+
+	__adpt_hppe_shaper_rate_to_refresh(ADPT_HPPE_PORT_SHAPER,
+								shaper->cir,
+								&hppe_cir,
+								shaper->meter_unit,
+								token_unit);
+
+	__adpt_hppe_shaper_burst_size_to_bucket_size(shaper->cbs,
+								&hppe_cbs,
+								shaper->meter_unit,
+								token_unit);
+
+	psch_shp_cfg_tbl.bf.meter_unit = shaper->meter_unit;
+	psch_shp_cfg_tbl.bf.shaper_enable = shaper->c_shaper_en;
+	psch_shp_cfg_tbl.bf.cbs = hppe_cbs;
+	psch_shp_cfg_tbl.bf.cir = hppe_cir;
+	psch_shp_cfg_tbl.bf.token_unit = token_unit;
+
+	psch_comp_cfg_tbl.bf.shaper_meter_len = shaper->shaper_frame_mode;
+
+	hppe_psch_shp_cfg_tbl_set(dev_id, port_id, &psch_shp_cfg_tbl);
+
+	hppe_psch_comp_cfg_tbl_set(dev_id, port_id, &psch_comp_cfg_tbl);
+
+	if( A_FALSE == shaper->c_shaper_en)
+	{
+		token_number.c_token_number_negative_en = 0;
+		token_number.c_token_number = 0;
+		adpt_hppe_port_shaper_token_number_set(dev_id, port_id, &token_number);
+	}
+
+	return SW_OK;
+}
+sw_error_t
+adpt_hppe_port_shaper_time_slot_set(a_uint32_t dev_id, a_uint32_t time_slot)
+{
+	sw_error_t rv = SW_OK;
+	union shp_slot_cfg_port_u shp_slot_cfg_port;
+
+	memset(&shp_slot_cfg_port, 0, sizeof(shp_slot_cfg_port));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if ((time_slot < 0x8) || (time_slot > 0xfff))
+		return SW_BAD_PARAM;
+
+	rv = hppe_shp_slot_cfg_port_get(dev_id, &shp_slot_cfg_port);
+
+	if( rv != SW_OK )
+		return rv;
+
+	shp_slot_cfg_port.bf.port_shp_slot_time = time_slot;
+	hppe_shp_slot_cfg_port_set(dev_id, &shp_slot_cfg_port);
+
+	__adpt_hppe_port_shaper_max_rate(time_slot);
+
+	__adpt_hppe_shaper_max_burst_size();
+
+	return SW_OK;
+
+}
+#ifndef IN_SHAPER_MINI
+sw_error_t
+adpt_hppe_flow_shaper_get(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_config_t * shaper)
+{
+	sw_error_t rv = SW_OK;
+	union l1_shp_cfg_tbl_u l1_shp_cfg_tbl;
+	union l1_comp_cfg_tbl_u l1_comp_cfg_tbl;
+	a_uint32_t hppe_cir =0, hppe_cbs = 0, hppe_eir = 0, hppe_ebs = 0;
+
+	memset(&l1_shp_cfg_tbl, 0, sizeof(l1_shp_cfg_tbl));
+	memset(&l1_comp_cfg_tbl, 0, sizeof(l1_comp_cfg_tbl));
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(shaper);
+
+	if (flow_id < 0 || flow_id > 63)
+		return SW_BAD_PARAM;
+
+	hppe_l1_comp_cfg_tbl_get(dev_id, flow_id, &l1_comp_cfg_tbl);
+
+	rv = hppe_l1_shp_cfg_tbl_get(dev_id, flow_id, &l1_shp_cfg_tbl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	hppe_cir = l1_shp_cfg_tbl.bf.cir;
+	hppe_cbs = l1_shp_cfg_tbl.bf.cbs;
+	hppe_eir = l1_shp_cfg_tbl.bf.eir;
+	hppe_ebs= l1_shp_cfg_tbl.bf.ebs;
+
+	__adpt_hppe_shaper_refresh_to_rate(ADPT_HPPE_FLOW_SHAPER,
+								hppe_cir,
+								&shaper->cir,
+								l1_shp_cfg_tbl.bf.meter_unit,
+								l1_shp_cfg_tbl.bf.token_unit);
+
+	__adpt_hppe_shaper_refresh_to_rate(ADPT_HPPE_FLOW_SHAPER,
+								hppe_eir,
+								&shaper->eir,
+								l1_shp_cfg_tbl.bf.meter_unit,
+								l1_shp_cfg_tbl.bf.token_unit);
+
+
+	__adpt_hppe_shaper_bucket_size_to_burst_size(hppe_cbs,
+								&shaper->cbs,
+								l1_shp_cfg_tbl.bf.meter_unit,
+								l1_shp_cfg_tbl.bf.token_unit);
+
+	__adpt_hppe_shaper_bucket_size_to_burst_size(hppe_ebs,
+								&shaper->ebs,
+								l1_shp_cfg_tbl.bf.meter_unit,
+								l1_shp_cfg_tbl.bf.token_unit);
+
+	shaper->couple_en = l1_shp_cfg_tbl.bf.cf;
+	shaper->meter_unit = l1_shp_cfg_tbl.bf.meter_unit;
+	shaper->c_shaper_en = l1_shp_cfg_tbl.bf.c_shaper_enable;
+	shaper->e_shaper_en = l1_shp_cfg_tbl.bf.e_shaper_enable;
+
+	shaper->shaper_frame_mode = l1_comp_cfg_tbl.bf.shaper_meter_len;
+
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+adpt_hppe_queue_shaper_set(a_uint32_t dev_id,a_uint32_t queue_id,
+		fal_shaper_config_t * shaper)
+{
+	sw_error_t rv = SW_OK;
+	union l0_shp_cfg_tbl_u l0_shp_cfg_tbl;
+	union l0_comp_cfg_tbl_u l0_comp_cfg_tbl;
+	a_uint32_t hppe_cir = 0, hppe_cbs = 0, hppe_eir= 0, hppe_ebs = 0;
+	a_uint32_t token_unit = 0;
+	a_uint64_t temp_cir = 0, temp_eir =0, temp_cbs =0, temp_ebs = 0;
+	fal_shaper_token_number_t token_number;
+
+	memset(&l0_shp_cfg_tbl, 0, sizeof(l0_shp_cfg_tbl));
+	memset(&l0_comp_cfg_tbl, 0, sizeof(l0_comp_cfg_tbl));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(shaper);
+
+	if (queue_id < 0 || queue_id > 299)
+		return SW_BAD_PARAM;
+
+	if(ADPT_HPPE_SHAPER_METER_UNIT_BYTE == shaper->meter_unit)
+	{
+		if ((shaper->cir > BYTE_SHAPER_MAX_RATE) || (shaper->eir > BYTE_SHAPER_MAX_RATE))
+			return SW_BAD_PARAM;
+		if ((shaper->cir < BYTE_SHAPER_MIN_RATE) && (shaper->cir != 0))
+			return SW_BAD_PARAM;
+		if ((shaper->eir < BYTE_SHAPER_MIN_RATE) && (shaper->eir != 0))
+			return SW_BAD_PARAM;
+	}
+	if(ADPT_HPPE_SHAPER_METER_UNIT_FRAME == shaper->meter_unit)
+	{
+		if ((shaper->cir > FRAME_SHAPER_MAX_RATE) || (shaper->eir > FRAME_SHAPER_MAX_RATE))
+			return SW_BAD_PARAM;
+		if ((shaper->cir < FRAME_SHAPER_MIN_RATE) && (shaper->cir != 0))
+			return SW_BAD_PARAM;
+		if ((shaper->eir < FRAME_SHAPER_MIN_RATE) && (shaper->eir != 0))
+			return SW_BAD_PARAM;
+	}
+
+	hppe_l0_comp_cfg_tbl_get(dev_id, queue_id, &l0_comp_cfg_tbl);
+
+	temp_cir = ((a_uint64_t)shaper->cir) * 1000;
+	temp_cbs = ((a_uint64_t)shaper->cbs) * 1000;
+	temp_eir = ((a_uint64_t)shaper->eir) * 1000;
+	temp_ebs = ((a_uint64_t)shaper->ebs) * 1000;
+
+	rv = __adpt_hppe_shaper_two_bucket_parameter_select(ADPT_HPPE_QUEUE_SHAPER,
+								temp_cir,
+								temp_cbs,
+								temp_eir,
+								temp_ebs,
+								shaper->meter_unit,
+								&token_unit);
+	if( rv != SW_OK )
+		return rv;
+	//printk("queue shaper meter unit is = %d\n", shaper->meter_unit);
+	//printk("queue shaper token unit is = %d\n", token_unit);
+
+		__adpt_hppe_shaper_rate_to_refresh(ADPT_HPPE_QUEUE_SHAPER,
+									shaper->cir,
+									&hppe_cir,
+									shaper->meter_unit,
+									token_unit);
+
+		__adpt_hppe_shaper_rate_to_refresh(ADPT_HPPE_QUEUE_SHAPER,
+									shaper->eir,
+									&hppe_eir,
+									shaper->meter_unit,
+									token_unit);
+
+		__adpt_hppe_shaper_burst_size_to_bucket_size(shaper->cbs,
+									&hppe_cbs,
+									shaper->meter_unit,
+									token_unit);
+
+		__adpt_hppe_shaper_burst_size_to_bucket_size(shaper->ebs,
+									&hppe_ebs,
+									shaper->meter_unit,
+									token_unit);
+
+	l0_shp_cfg_tbl.bf.cf = shaper->couple_en;
+	l0_shp_cfg_tbl.bf.meter_unit = shaper->meter_unit;
+	l0_shp_cfg_tbl.bf.c_shaper_enable = shaper->c_shaper_en;
+	l0_shp_cfg_tbl.bf.cbs = hppe_cbs;
+	l0_shp_cfg_tbl.bf.cir = hppe_cir;
+	l0_shp_cfg_tbl.bf.e_shaper_enable = shaper->e_shaper_en;
+	l0_shp_cfg_tbl.bf.ebs = hppe_ebs;
+	l0_shp_cfg_tbl.bf.eir = hppe_eir;
+	l0_shp_cfg_tbl.bf.token_unit = token_unit;
+	l0_comp_cfg_tbl.bf.shaper_meter_len = shaper->shaper_frame_mode;
+
+	hppe_l0_shp_cfg_tbl_set(dev_id, queue_id, &l0_shp_cfg_tbl);
+
+	hppe_l0_comp_cfg_tbl_set(dev_id, queue_id, &l0_comp_cfg_tbl);
+
+	if( A_FALSE == shaper->c_shaper_en)
+	{
+		token_number.c_token_number_negative_en = 0;
+		token_number.c_token_number = 0;
+		adpt_hppe_queue_shaper_token_number_set(dev_id, queue_id, &token_number);
+	}
+	if( A_FALSE == shaper->e_shaper_en)
+	{
+		token_number.e_token_number_negative_en = 0;
+		token_number.e_token_number = 0;
+		adpt_hppe_queue_shaper_token_number_set(dev_id, queue_id, &token_number);
+	}
+
+	return SW_OK;
+
+}
+sw_error_t
+adpt_hppe_queue_shaper_time_slot_set(a_uint32_t dev_id, a_uint32_t time_slot)
+{
+	union shp_slot_cfg_l0_u shp_slot_cfg_l0;
+	sw_error_t rv = SW_OK;
+
+	memset(&shp_slot_cfg_l0, 0, sizeof(shp_slot_cfg_l0));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if ((time_slot < 0x12c) || (time_slot > 0xfff))
+		return SW_BAD_PARAM;
+
+	rv = hppe_shp_slot_cfg_l0_get(dev_id, &shp_slot_cfg_l0);
+
+	if( rv != SW_OK )
+		return rv;
+
+	shp_slot_cfg_l0.bf.l0_shp_slot_time = time_slot;
+	hppe_shp_slot_cfg_l0_set(dev_id, &shp_slot_cfg_l0);
+
+	__adpt_hppe_queue_shaper_max_rate(time_slot);
+
+	return SW_OK;
+
+}
+
+sw_error_t
+adpt_hppe_shaper_ipg_preamble_length_set(a_uint32_t dev_id, a_uint32_t ipg_pre_length)
+{
+	union ipg_pre_len_cfg_u ipg_pre_len_cfg;
+
+	memset(&ipg_pre_len_cfg, 0, sizeof(ipg_pre_len_cfg));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (ipg_pre_length > 0x1f)
+		return SW_BAD_PARAM;
+
+	hppe_ipg_pre_len_cfg_get(dev_id, &ipg_pre_len_cfg);
+	ipg_pre_len_cfg.bf.ipg_pre_len = ipg_pre_length;
+
+	hppe_ipg_pre_len_cfg_set(dev_id, &ipg_pre_len_cfg);
+
+	return SW_OK;
+}
+
+#ifndef IN_SHAPER_MINI
+sw_error_t
+adpt_hppe_shaper_ipg_preamble_length_get(a_uint32_t dev_id, a_uint32_t *ipg_pre_length)
+{
+	sw_error_t rv = SW_OK;
+	union ipg_pre_len_cfg_u ipg_pre_len_cfg;
+
+	memset(&ipg_pre_len_cfg, 0, sizeof(ipg_pre_len_cfg));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(ipg_pre_length);
+
+	rv = hppe_ipg_pre_len_cfg_get(dev_id, &ipg_pre_len_cfg);
+
+	if( rv != SW_OK )
+		return rv;
+
+	*ipg_pre_length = ipg_pre_len_cfg.bf.ipg_pre_len;
+
+	return SW_OK;
+}
+#endif
+
+void adpt_hppe_shaper_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_shaper_func_bitmap = ((1 << FUNC_ADPT_FLOW_SHAPER_SET)|
+						(1 << FUNC_ADPT_QUEUE_SHAPER_GET)|
+						(1 << FUNC_ADPT_QUEUE_SHAPER_TOKEN_NUMBER_SET)|
+						(1 << FUNC_ADPT_PORT_SHAPER_GET)|
+						(1 << FUNC_ADPT_FLOW_SHAPER_TIME_SLOT_GET)|
+						(1 << FUNC_ADPT_PORT_SHAPER_TIME_SLOT_GET)|
+						(1 << FUNC_ADPT_FLOW_SHAPER_TIME_SLOT_SET)|
+						(1 << FUNC_ADPT_PORT_SHAPER_TOKEN_NUMBER_SET)|
+						(1 << FUNC_ADPT_QUEUE_SHAPER_TOKEN_NUMBER_GET)|
+						(1 << FUNC_ADPT_QUEUE_SHAPER_TIME_SLOT_GET)|
+						(1 << FUNC_ADPT_PORT_SHAPER_TOKEN_NUMBER_GET)|
+						(1 << FUNC_ADPT_FLOW_SHAPER_TOKEN_NUMBER_SET)|
+						(1 << FUNC_ADPT_FLOW_SHAPER_TOKEN_NUMBER_GET)|
+						(1 << FUNC_ADPT_PORT_SHAPER_SET)|
+						(1 << FUNC_ADPT_PORT_SHAPER_TIME_SLOT_SET)|
+						(1 << FUNC_ADPT_FLOW_SHAPER_GET)|
+						(1 << FUNC_ADPT_QUEUE_SHAPER_SET)|
+						(1 << FUNC_ADPT_QUEUE_SHAPER_TIME_SLOT_SET)|
+						(1 << FUNC_ADPT_SHAPER_IPG_PREAMBLE_LENGTH_SET)|
+						(1 << FUNC_ADPT_SHAPER_IPG_PREAMBLE_LENGTH_GET));
+
+	return;
+
+}
+
+static void adpt_hppe_shaper_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_flow_shaper_set = NULL;
+	p_adpt_api->adpt_queue_shaper_get = NULL;
+	p_adpt_api->adpt_queue_shaper_token_number_set = NULL;
+	p_adpt_api->adpt_port_shaper_get = NULL;
+	p_adpt_api->adpt_flow_shaper_time_slot_get = NULL;
+	p_adpt_api->adpt_port_shaper_time_slot_get = NULL;
+	p_adpt_api->adpt_flow_shaper_time_slot_set = NULL;
+	p_adpt_api->adpt_port_shaper_token_number_set = NULL;
+	p_adpt_api->adpt_queue_shaper_token_number_get = NULL;
+	p_adpt_api->adpt_queue_shaper_time_slot_get = NULL;
+	p_adpt_api->adpt_port_shaper_token_number_get = NULL;
+	p_adpt_api->adpt_flow_shaper_token_number_set = NULL;
+	p_adpt_api->adpt_flow_shaper_token_number_get = NULL;
+	p_adpt_api->adpt_port_shaper_set = NULL;
+	p_adpt_api->adpt_port_shaper_time_slot_set = NULL;
+	p_adpt_api->adpt_flow_shaper_get = NULL;
+	p_adpt_api->adpt_queue_shaper_set = NULL;
+	p_adpt_api->adpt_queue_shaper_time_slot_set = NULL;
+	p_adpt_api->adpt_shaper_ipg_preamble_length_set = NULL;
+	p_adpt_api->adpt_shaper_ipg_preamble_length_get = NULL;
+
+	return;
+
+}
+
+sw_error_t adpt_hppe_shaper_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_shaper_func_unregister(dev_id, p_adpt_api);
+
+#ifndef IN_SHAPER_MINI
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_PORT_SHAPER_GET))
+	{
+		p_adpt_api->adpt_port_shaper_get = adpt_hppe_port_shaper_get;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_FLOW_SHAPER_TIME_SLOT_GET))
+	{
+		p_adpt_api->adpt_flow_shaper_time_slot_get = adpt_hppe_flow_shaper_time_slot_get;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_PORT_SHAPER_TIME_SLOT_GET))
+	{
+		p_adpt_api->adpt_port_shaper_time_slot_get = adpt_hppe_port_shaper_time_slot_get;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_QUEUE_SHAPER_TOKEN_NUMBER_GET))
+	{
+		p_adpt_api->adpt_queue_shaper_token_number_get =
+			adpt_hppe_queue_shaper_token_number_get;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_QUEUE_SHAPER_TIME_SLOT_GET))
+	{
+		p_adpt_api->adpt_queue_shaper_time_slot_get = adpt_hppe_queue_shaper_time_slot_get;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_PORT_SHAPER_TOKEN_NUMBER_GET))
+	{
+		p_adpt_api->adpt_port_shaper_token_number_get =
+			adpt_hppe_port_shaper_token_number_get;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_FLOW_SHAPER_TOKEN_NUMBER_GET))
+	{
+		p_adpt_api->adpt_flow_shaper_token_number_get =
+			adpt_hppe_flow_shaper_token_number_get;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_FLOW_SHAPER_GET))
+	{
+		p_adpt_api->adpt_flow_shaper_get = adpt_hppe_flow_shaper_get;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_SHAPER_IPG_PREAMBLE_LENGTH_GET))
+	{
+		p_adpt_api->adpt_shaper_ipg_preamble_length_get =
+			adpt_hppe_shaper_ipg_preamble_length_get;
+	}
+#endif
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_FLOW_SHAPER_SET))
+	{
+		p_adpt_api->adpt_flow_shaper_set = adpt_hppe_flow_shaper_set;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_QUEUE_SHAPER_SET))
+	{
+		p_adpt_api->adpt_queue_shaper_set = adpt_hppe_queue_shaper_set;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_QUEUE_SHAPER_GET))
+	{
+		p_adpt_api->adpt_queue_shaper_get = adpt_hppe_queue_shaper_get;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_PORT_SHAPER_SET))
+	{
+		p_adpt_api->adpt_port_shaper_set = adpt_hppe_port_shaper_set;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_SHAPER_IPG_PREAMBLE_LENGTH_SET))
+	{
+		p_adpt_api->adpt_shaper_ipg_preamble_length_set =
+			adpt_hppe_shaper_ipg_preamble_length_set;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_QUEUE_SHAPER_TOKEN_NUMBER_SET))
+	{
+		p_adpt_api->adpt_queue_shaper_token_number_set =
+			adpt_hppe_queue_shaper_token_number_set;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_PORT_SHAPER_TOKEN_NUMBER_SET))
+	{
+		p_adpt_api->adpt_port_shaper_token_number_set =
+			adpt_hppe_port_shaper_token_number_set;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_FLOW_SHAPER_TOKEN_NUMBER_SET))
+	{
+		p_adpt_api->adpt_flow_shaper_token_number_set =
+			adpt_hppe_flow_shaper_token_number_set;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_PORT_SHAPER_TIME_SLOT_SET))
+	{
+		p_adpt_api->adpt_port_shaper_time_slot_set = adpt_hppe_port_shaper_time_slot_set;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_FLOW_SHAPER_TIME_SLOT_SET))
+	{
+		p_adpt_api->adpt_flow_shaper_time_slot_set = adpt_hppe_flow_shaper_time_slot_set;
+	}
+	if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_QUEUE_SHAPER_TIME_SLOT_SET))
+	{
+		p_adpt_api->adpt_queue_shaper_time_slot_set = adpt_hppe_queue_shaper_time_slot_set;
+	}
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_stp.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_stp.c
new file mode 100755
index 0000000..634c3c4
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_stp.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_stp_reg.h"
+#include "hppe_stp.h"
+#include "adpt.h"
+
+sw_error_t
+adpt_hppe_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                       fal_port_t port_id, fal_stp_state_t * state)
+{
+	union cst_state_u cst_state;
+
+	memset(&cst_state, 0, sizeof(cst_state));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(state);
+	if (FAL_SINGLE_STP_ID != st_id)
+		return SW_BAD_PARAM;
+
+	SW_RTN_ON_ERROR(hppe_cst_state_get(dev_id, port_id, &cst_state));
+
+	if (cst_state.bf.port_state == 0)
+		*state = FAL_STP_DISABLED;
+	else if (cst_state.bf.port_state == 1)
+		*state = FAL_STP_BLOKING;
+	else if (cst_state.bf.port_state == 2)
+		*state = FAL_STP_LEARNING;
+	else if (cst_state.bf.port_state == 3)
+		*state = FAL_STP_FARWARDING;
+	else
+		*state = FAL_STP_STATE_BUTT;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                       fal_port_t port_id, fal_stp_state_t state)
+{
+	union cst_state_u cst_state;
+
+	memset(&cst_state, 0, sizeof(cst_state));
+
+	/* stp port_id just support physical port, not support trunk and virtual port */
+	if (FAL_PORT_ID_TYPE(port_id) != 0)
+		return SW_BAD_PARAM;
+
+	if (port_id >= CST_STATE_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	if (FAL_SINGLE_STP_ID != st_id)
+		return SW_BAD_PARAM;
+
+	if (state == FAL_STP_DISABLED)
+		cst_state.bf.port_state = 0;
+	else if (state == FAL_STP_BLOKING || state == FAL_STP_LISTENING)
+		cst_state.bf.port_state = 1;
+	else if (state == FAL_STP_LEARNING)
+		cst_state.bf.port_state = 2;
+	else if (state == FAL_STP_FARWARDING)
+		cst_state.bf.port_state = 3;
+
+	SW_RTN_ON_ERROR(hppe_cst_state_set(dev_id, port_id, &cst_state));
+
+	return SW_OK;
+}
+
+void adpt_hppe_stp_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_stp_func_bitmap = ((1 << FUNC_STP_PORT_STATE_SET) |
+						(1 << FUNC_STP_PORT_STATE_GET));
+
+	return;
+}
+
+static void adpt_hppe_stp_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_stp_port_state_get = NULL;
+	p_adpt_api->adpt_stp_port_state_set = NULL;
+
+	return;
+}
+
+sw_error_t
+adpt_hppe_stp_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_stp_func_unregister(dev_id, p_adpt_api);
+
+	if (p_adpt_api->adpt_stp_func_bitmap & (1 << FUNC_STP_PORT_STATE_GET))
+		p_adpt_api->adpt_stp_port_state_get = adpt_hppe_stp_port_state_get;
+	if (p_adpt_api->adpt_stp_func_bitmap & (1 << FUNC_STP_PORT_STATE_SET))
+		p_adpt_api->adpt_stp_port_state_set = adpt_hppe_stp_port_state_set;
+
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_trunk.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_trunk.c
new file mode 100644
index 0000000..9766255
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_trunk.c
@@ -0,0 +1,345 @@
+/*
+ * Copyright (c) 2016-2017, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+
+#include "hppe_trunk_reg.h"
+#include "hppe_trunk.h"
+#include "adpt.h"
+#include "hppe_fdb_reg.h"
+#include "hppe_fdb.h"
+
+sw_error_t
+adpt_hppe_trunk_fail_over_en_get(a_uint32_t dev_id, a_bool_t * fail_over)
+{
+	union l2_global_conf_u l2_global_conf;
+
+	memset(&l2_global_conf, 0, sizeof(l2_global_conf));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(fail_over);
+
+	SW_RTN_ON_ERROR(hppe_l2_global_conf_get(dev_id, &l2_global_conf));
+
+	*fail_over = l2_global_conf.bf.failover_en;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+	union trunk_hash_field_reg_u trunk_hash_field;
+
+	memset(&trunk_hash_field, 0, sizeof(trunk_hash_field));
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(hash_mode);
+
+	SW_RTN_ON_ERROR(hppe_trunk_hash_field_reg_get(dev_id, &trunk_hash_field));
+
+	*hash_mode = 0;
+
+	if (trunk_hash_field.bf.mac_da_incl)
+		*hash_mode |= FAL_TRUNK_HASH_KEY_DA;
+
+	if (trunk_hash_field.bf.mac_sa_incl)
+		*hash_mode |= FAL_TRUNK_HASH_KEY_SA;
+
+	if (trunk_hash_field.bf.src_ip_incl)
+		*hash_mode |= FAL_TRUNK_HASH_KEY_SIP;
+
+	if (trunk_hash_field.bf.dst_ip_incl)
+		*hash_mode |= FAL_TRUNK_HASH_KEY_DIP;
+
+	if (trunk_hash_field.bf.src_port_incl)
+		*hash_mode |= FAL_TRUNK_HASH_KEY_SRC_PORT;
+
+	if (trunk_hash_field.bf.l4_src_port_incl)
+		*hash_mode |= FAL_TRUNK_HASH_KEY_L4_SRC_PORT;
+
+	if (trunk_hash_field.bf.l4_dst_port_incl)
+		*hash_mode |= FAL_TRUNK_HASH_KEY_L4_DST_PORT;
+
+	if (trunk_hash_field.bf.udf0_incl)
+		*hash_mode |= FAL_TRUNK_HASH_KEY_UDF0;
+
+	if (trunk_hash_field.bf.udf1_incl)
+		*hash_mode |= FAL_TRUNK_HASH_KEY_UDF1;
+
+	if (trunk_hash_field.bf.udf2_incl)
+		*hash_mode |= FAL_TRUNK_HASH_KEY_UDF2;
+
+	if (trunk_hash_field.bf.udf3_incl)
+		*hash_mode |= FAL_TRUNK_HASH_KEY_UDF3;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+                        a_bool_t * enable, fal_pbmp_t * member)
+{
+	union trunk_filter_u trunk_filter;
+	union port_trunk_id_u port_trunk_id;
+	a_uint32_t port_id;
+
+	memset(&trunk_filter, 0, sizeof(trunk_filter));
+	memset(&port_trunk_id, 0, sizeof(port_trunk_id));
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+	ADPT_NULL_POINT_CHECK(member);
+
+	*enable = A_FALSE;
+	for (port_id = 0; port_id < FAL_MAX_PORT_NUMBER; port_id ++)
+	{
+		SW_RTN_ON_ERROR(hppe_port_trunk_id_get(dev_id, port_id, &port_trunk_id));
+		if ((trunk_id == port_trunk_id.bf.trunk_id) && (A_TRUE == port_trunk_id.bf.trunk_en))
+		{
+			*enable = A_TRUE;
+			break;
+		}
+	}
+
+	SW_RTN_ON_ERROR(hppe_trunk_filter_get(dev_id, trunk_id, &trunk_filter));
+
+	*member = trunk_filter.bf.mem_bitmap;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+                        a_bool_t enable, fal_pbmp_t member)
+{
+	union trunk_filter_u trunk_filter;
+	union port_trunk_id_u port_trunk_id;
+	union trunk_member_u trunk_member;
+	a_uint32_t i, j, cnt = 0, data[FAL_MAX_PORT_NUMBER] = {0};
+
+	memset(&trunk_filter, 0, sizeof(trunk_filter));
+	memset(&port_trunk_id, 0, sizeof(port_trunk_id));
+	memset(&trunk_member, 0, sizeof(trunk_member));
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (trunk_id >= TRUNK_FILTER_MAX_ENTRY)
+	{
+		return SW_OUT_OF_RANGE;
+	}
+
+	if(enable == A_TRUE && member == 0)
+	{
+		SSDK_ERROR("trunk member cannot be 0 when trunk group was enabled\n");
+		return SW_BAD_PARAM;
+	}
+
+	if (A_TRUE == enable)
+	{
+		for (i = 0; i < FAL_MAX_PORT_NUMBER; i++)
+		{
+			if (member & (0x1 << i))
+			{
+				if (FAL_TRUNK_GROUP_MAX_MEMEBER <= cnt)
+				{
+					return SW_BAD_PARAM;
+				}
+				data[cnt] = i;
+				cnt++;
+			}
+		}
+	}
+
+	for (i = 0; i < FAL_MAX_PORT_NUMBER; i++)
+	{
+		SW_RTN_ON_ERROR(hppe_port_trunk_id_get(dev_id, i, &port_trunk_id));
+		if (port_trunk_id.bf.trunk_id == trunk_id) {
+			port_trunk_id.bf.trunk_en = A_FALSE;
+			SW_RTN_ON_ERROR(hppe_port_trunk_id_set(dev_id, i, &port_trunk_id));
+		}
+	}
+
+	for (j = 0; j < FAL_MAX_PORT_NUMBER; j++)
+	{
+		if (member & (0x1 << j))
+		{
+			port_trunk_id.bf.trunk_en = enable;
+			port_trunk_id.bf.trunk_id = trunk_id;
+			SW_RTN_ON_ERROR(hppe_port_trunk_id_set(dev_id, j, &port_trunk_id));
+		}
+	}
+
+	if (A_TRUE == enable)
+		trunk_filter.bf.mem_bitmap = member;
+	else
+		trunk_filter.bf.mem_bitmap = 0;
+
+	SW_RTN_ON_ERROR(hppe_trunk_filter_set(dev_id, trunk_id, &trunk_filter));
+
+	if (A_TRUE == enable)
+	{
+		for(i = SSDK_PHYSICAL_PORT0; i <= SSDK_PHYSICAL_PORT7; i+=cnt)
+		{
+			for(j = 0; j < cnt; j++)
+			{
+				if((i+j) < FAL_MAX_PORT_NUMBER)
+				{
+					data[i+j] = data[j];
+				}
+			}
+		}
+	}
+	trunk_member.bf.member_0_port_id = data[0];
+	trunk_member.bf.member_1_port_id = data[1];
+	trunk_member.bf.member_2_port_id = data[2];
+	trunk_member.bf.member_3_port_id = data[3];
+	trunk_member.bf.member_4_port_id = data[4];
+	trunk_member.bf.member_5_port_id = data[5];
+	trunk_member.bf.member_6_port_id = data[6];
+	trunk_member.bf.member_7_port_id = data[7];
+
+	SW_RTN_ON_ERROR(hppe_trunk_member_set(dev_id, trunk_id, &trunk_member));
+
+	return SW_OK;
+}
+sw_error_t
+adpt_hppe_trunk_fail_over_en_set(a_uint32_t dev_id, a_bool_t fail_over)
+{
+	union l2_global_conf_u l2_global_conf;
+
+	memset(&l2_global_conf, 0, sizeof(l2_global_conf));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	SW_RTN_ON_ERROR(hppe_l2_global_conf_get(dev_id, &l2_global_conf));
+
+	l2_global_conf.bf.failover_en = fail_over;
+
+	SW_RTN_ON_ERROR(hppe_l2_global_conf_set(dev_id, &l2_global_conf));
+
+	return SW_OK;
+}
+sw_error_t
+adpt_hppe_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+	union trunk_hash_field_reg_u trunk_hash_field;
+
+	memset(&trunk_hash_field, 0, sizeof(trunk_hash_field));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (FAL_TRUNK_HASH_KEY_DA & hash_mode)
+		trunk_hash_field.bf.mac_da_incl = 1;
+
+	if (FAL_TRUNK_HASH_KEY_SA & hash_mode)
+		trunk_hash_field.bf.mac_sa_incl = 1;
+
+	if (FAL_TRUNK_HASH_KEY_DIP & hash_mode)
+		trunk_hash_field.bf.dst_ip_incl = 1;
+
+	if (FAL_TRUNK_HASH_KEY_SIP & hash_mode)
+		trunk_hash_field.bf.src_ip_incl = 1;
+
+	if (FAL_TRUNK_HASH_KEY_SRC_PORT & hash_mode)
+		trunk_hash_field.bf.src_port_incl = 1;
+
+	if (FAL_TRUNK_HASH_KEY_L4_SRC_PORT & hash_mode)
+		trunk_hash_field.bf.l4_src_port_incl = 1;
+
+	if (FAL_TRUNK_HASH_KEY_L4_DST_PORT & hash_mode)
+		trunk_hash_field.bf.l4_dst_port_incl = 1;
+
+	if (FAL_TRUNK_HASH_KEY_UDF0 & hash_mode)
+		trunk_hash_field.bf.udf0_incl = 1;
+
+	if (FAL_TRUNK_HASH_KEY_UDF1 & hash_mode)
+		trunk_hash_field.bf.udf1_incl = 1;
+
+	if (FAL_TRUNK_HASH_KEY_UDF2 & hash_mode)
+		trunk_hash_field.bf.udf2_incl = 1;
+
+	if (FAL_TRUNK_HASH_KEY_UDF3 & hash_mode)
+		trunk_hash_field.bf.udf3_incl = 1;
+
+	SW_RTN_ON_ERROR(hppe_trunk_hash_field_reg_set(dev_id, &trunk_hash_field));
+
+	return SW_OK;
+}
+
+void adpt_hppe_trunk_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_trunk_func_bitmap = ((1 << FUNC_TRUNK_GROUP_SET) |
+						(1 << FUNC_TRUNK_GROUP_GET) |
+						(1 << FUNC_TRUNK_HASH_MODE_SET) |
+						(1 << FUNC_TRUNK_HASH_MODE_GET) |
+						(1 << FUNC_TRUNK_FAILOVER_ENABLE) |
+						(1 << FUNC_TRUNK_FAILOVER_STATUS_GET));
+
+	return;
+}
+
+static void adpt_hppe_trunk_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_trunk_fail_over_en_get = NULL;
+	p_adpt_api->adpt_trunk_hash_mode_get = NULL;
+	p_adpt_api->adpt_trunk_group_get = NULL;
+	p_adpt_api->adpt_trunk_group_set = NULL;
+	p_adpt_api->adpt_trunk_fail_over_en_set = NULL;
+	p_adpt_api->adpt_trunk_hash_mode_set = NULL;
+
+	return;
+}
+
+sw_error_t adpt_hppe_trunk_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_trunk_func_unregister(dev_id, p_adpt_api);
+
+	if (p_adpt_api->adpt_trunk_func_bitmap & (1 << FUNC_TRUNK_FAILOVER_STATUS_GET))
+		p_adpt_api->adpt_trunk_fail_over_en_get = adpt_hppe_trunk_fail_over_en_get;
+	if (p_adpt_api->adpt_trunk_func_bitmap & (1 << FUNC_TRUNK_HASH_MODE_GET))
+		p_adpt_api->adpt_trunk_hash_mode_get = adpt_hppe_trunk_hash_mode_get;
+	if (p_adpt_api->adpt_trunk_func_bitmap & (1 << FUNC_TRUNK_GROUP_GET))
+		p_adpt_api->adpt_trunk_group_get = adpt_hppe_trunk_group_get;
+	if (p_adpt_api->adpt_trunk_func_bitmap & (1 << FUNC_TRUNK_GROUP_SET))
+		p_adpt_api->adpt_trunk_group_set = adpt_hppe_trunk_group_set;
+	if (p_adpt_api->adpt_trunk_func_bitmap & (1 << FUNC_TRUNK_FAILOVER_ENABLE))
+		p_adpt_api->adpt_trunk_fail_over_en_set = adpt_hppe_trunk_fail_over_en_set;
+	if (p_adpt_api->adpt_trunk_func_bitmap & (1 << FUNC_TRUNK_HASH_MODE_SET))
+		p_adpt_api->adpt_trunk_hash_mode_set = adpt_hppe_trunk_hash_mode_set;
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_uniphy.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_uniphy.c
new file mode 100755
index 0000000..a1149e0
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_uniphy.c
@@ -0,0 +1,801 @@
+/*
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_uniphy_reg.h"
+#include "hppe_uniphy.h"
+#include "hppe_init.h"
+#include "ssdk_init.h"
+#include "ssdk_clk.h"
+#include "ssdk_dts.h"
+#include "adpt.h"
+#include "hppe_reg_access.h"
+#include "hsl_phy.h"
+#include "hsl_port_prop.h"
+#include "adpt_hppe.h"
+#if defined(CPPE)
+#include "adpt_cppe_uniphy.h"
+#include "adpt_cppe_portctrl.h"
+#endif
+
+extern void adpt_hppe_gcc_port_speed_clock_set(a_uint32_t dev_id,
+				a_uint32_t port_id, fal_port_speed_t phy_speed);
+
+static a_uint32_t
+adpt_hppe_port_get_by_uniphy(a_uint32_t dev_id, a_uint32_t uniphy_index,
+		a_uint32_t channel)
+{
+	a_uint32_t ssdk_port = 0;
+
+	if (uniphy_index == SSDK_UNIPHY_INSTANCE0) {
+		if (channel == SSDK_UNIPHY_CHANNEL0) {
+			ssdk_port = SSDK_PHYSICAL_PORT1;
+		} else if (channel == SSDK_UNIPHY_CHANNEL1) {
+			ssdk_port = SSDK_PHYSICAL_PORT2;
+		} else if (channel == SSDK_UNIPHY_CHANNEL4) {
+			ssdk_port = SSDK_PHYSICAL_PORT5;
+		} else if (channel == SSDK_UNIPHY_CHANNEL3) {
+			ssdk_port = SSDK_PHYSICAL_PORT4;
+		}
+	} else if (uniphy_index == SSDK_UNIPHY_INSTANCE1) {
+		ssdk_port = SSDK_PHYSICAL_PORT5;
+	} else if (uniphy_index == SSDK_UNIPHY_INSTANCE2) {
+		ssdk_port = SSDK_PHYSICAL_PORT6;
+	}
+
+	return ssdk_port;
+}
+
+static sw_error_t
+__adpt_hppe_uniphy_10g_r_linkup(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+	a_uint32_t reg_value = 0;
+	a_uint32_t retries = 100, linkup = 0;
+
+	union sr_xs_pcs_kr_sts1_u sr_xs_pcs_kr_sts1;
+
+	memset(&sr_xs_pcs_kr_sts1, 0, sizeof(sr_xs_pcs_kr_sts1));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	/* wait 10G_R link up  to uniphy */
+	while (linkup != UNIPHY_10GR_LINKUP) {
+		mdelay(1);
+		if (retries-- == 0)
+			return SW_TIMEOUT;
+		reg_value = 0;
+		hppe_sr_xs_pcs_kr_sts1_get(dev_id, uniphy_index, &sr_xs_pcs_kr_sts1);
+		reg_value = sr_xs_pcs_kr_sts1.bf.plu;
+		linkup = (reg_value & UNIPHY_10GR_LINKUP);
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+__adpt_hppe_uniphy_calibrate(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+	a_uint32_t reg_value = 0;
+	a_uint32_t retries = 100, calibration_done = 0;
+
+	union uniphy_offset_calib_4_u uniphy_offset_calib_4;
+
+	memset(&uniphy_offset_calib_4, 0, sizeof(uniphy_offset_calib_4));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	/* wait calibration done to uniphy */
+	while (calibration_done != UNIPHY_CALIBRATION_DONE) {
+		mdelay(1);
+		if (retries-- == 0)
+		{
+			SSDK_ERROR("uniphy callibration time out!\n");
+			return SW_TIMEOUT;
+		}
+		reg_value = 0;
+		hppe_uniphy_offset_calib_4_get(dev_id, uniphy_index, &uniphy_offset_calib_4);
+		reg_value = uniphy_offset_calib_4.bf.mmd1_reg_calibration_done_reg;
+
+		calibration_done = (reg_value & UNIPHY_CALIBRATION_DONE);
+	}
+
+	return SW_OK;
+}
+
+void
+__adpt_hppe_gcc_uniphy_xpcs_reset(a_uint32_t dev_id, a_uint32_t uniphy_index, a_bool_t enable)
+{
+	enum unphy_rst_type rst_type;
+	enum ssdk_rst_action rst_action;
+
+	if (uniphy_index == SSDK_UNIPHY_INSTANCE0)
+		rst_type = UNIPHY0_XPCS_RESET_E;
+	else if (uniphy_index == SSDK_UNIPHY_INSTANCE1)
+		rst_type = UNIPHY1_XPCS_RESET_E;
+	else
+		rst_type = UNIPHY2_XPCS_RESET_E;
+
+	if (enable == A_TRUE)
+		rst_action = SSDK_RESET_ASSERT;
+	else
+		rst_action = SSDK_RESET_DEASSERT;
+	
+	ssdk_uniphy_reset(dev_id, rst_type, rst_action);
+
+	return;
+}
+
+void
+__adpt_hppe_gcc_uniphy_software_reset(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+
+	enum unphy_rst_type rst_type;
+
+	if (uniphy_index == SSDK_UNIPHY_INSTANCE0)
+		rst_type = UNIPHY0_SOFT_RESET_E;
+	else if (uniphy_index == SSDK_UNIPHY_INSTANCE1)
+		rst_type = UNIPHY1_SOFT_RESET_E;
+	else
+		rst_type = UNIPHY2_SOFT_RESET_E;
+
+	ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_ASSERT);
+
+	msleep(100);
+
+	ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_DEASSERT);
+
+	return;
+}
+
+static sw_error_t
+__adpt_hppe_uniphy_usxgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+	sw_error_t rv = SW_OK;
+
+	union uniphy_mode_ctrl_u uniphy_mode_ctrl;
+	union vr_xs_pcs_dig_ctrl1_u vr_xs_pcs_dig_ctrl1;
+	union vr_mii_an_ctrl_u vr_mii_an_ctrl;
+	union sr_mii_ctrl_u sr_mii_ctrl;
+
+	memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
+	memset(&vr_xs_pcs_dig_ctrl1, 0, sizeof(vr_xs_pcs_dig_ctrl1));
+	memset(&vr_mii_an_ctrl, 0, sizeof(vr_mii_an_ctrl));
+	memset(&sr_mii_ctrl, 0, sizeof(sr_mii_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	hppe_uniphy_reg_set(dev_id, UNIPHY_MISC2_REG_OFFSET,
+		uniphy_index, UNIPHY_MISC2_REG_VALUE);
+	/*reset uniphy*/
+	hppe_uniphy_reg_set(dev_id, UNIPHY_PLL_RESET_REG_OFFSET,
+		uniphy_index, UNIPHY_PLL_RESET_REG_VALUE);
+	msleep(500);
+	hppe_uniphy_reg_set(dev_id, UNIPHY_PLL_RESET_REG_OFFSET,
+		uniphy_index, UNIPHY_PLL_RESET_REG_DEFAULT_VALUE);
+	msleep(500);
+
+	/* disable instance clock */
+	qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+			1, A_FALSE);
+
+	/* keep xpcs to reset status */
+	__adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE);
+
+	/* configure uniphy to usxgmii mode */
+	hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+		UNIPHY_CH0_QSGMII_SGMII_MODE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+		UNIPHY_CH0_SGMII_MODE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+		UNIPHY_SGMII_MODE_DISABLE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+		UNIPHY_SGMIIPLUS_MODE_DISABLE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+		UNIPHY_XPCS_MODE_ENABLE;
+	hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
+
+	/* configure uniphy usxgmii gcc software reset */
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+#if defined(CPPE)
+		__adpt_cppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
+#endif
+	} else {
+		__adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
+	}
+
+	msleep(100);
+
+	/* wait calibration done to uniphy */
+	__adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
+
+	/* enable instance clock */
+	qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+			1, A_TRUE);
+
+	/* release xpcs reset status */
+	__adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_FALSE);
+
+	/* wait 10g base_r link up */
+	__adpt_hppe_uniphy_10g_r_linkup(dev_id, uniphy_index);
+
+	/* enable uniphy usxgmii */
+	hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, uniphy_index, &vr_xs_pcs_dig_ctrl1);
+	vr_xs_pcs_dig_ctrl1.bf.usxg_en = 1;
+	hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, uniphy_index, &vr_xs_pcs_dig_ctrl1);
+
+	/* enable uniphy autoneg complete interrupt and 10M/100M 8-bits MII width */
+	hppe_vr_mii_an_ctrl_get(dev_id, uniphy_index, &vr_mii_an_ctrl);
+	vr_mii_an_ctrl.bf.mii_an_intr_en = 1;
+	vr_mii_an_ctrl.bf.mii_ctrl = 1;
+	hppe_vr_mii_an_ctrl_set(dev_id, uniphy_index, &vr_mii_an_ctrl);
+
+	/* enable uniphy autoneg ability and usxgmii 10g speed and full duplex */
+	hppe_sr_mii_ctrl_get(dev_id, uniphy_index, &sr_mii_ctrl);
+	sr_mii_ctrl.bf.an_enable = 1;
+	sr_mii_ctrl.bf.ss5 = 0;
+	sr_mii_ctrl.bf.ss6 = 1;
+	sr_mii_ctrl.bf.ss13 = 1;
+	sr_mii_ctrl.bf.duplex_mode = 1;
+	hppe_sr_mii_ctrl_set(dev_id, uniphy_index, &sr_mii_ctrl);
+
+	return rv;
+}
+
+static sw_error_t
+__adpt_hppe_uniphy_10g_r_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+	a_uint32_t port_id = 0;
+	sw_error_t rv = SW_OK;
+
+	union uniphy_mode_ctrl_u uniphy_mode_ctrl;
+	union uniphy_instance_link_detect_u uniphy_instance_link_detect;
+
+	memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
+	memset(&uniphy_instance_link_detect, 0, sizeof(uniphy_instance_link_detect));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	/* keep xpcs to reset status */
+	__adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE);
+
+	/* disable instance clock */
+	qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+				1, A_FALSE);
+
+	/* configure uniphy to 10g_r mode */
+	hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
+
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+		UNIPHY_CH0_QSGMII_SGMII_MODE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+		UNIPHY_CH0_SGMII_MODE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+		UNIPHY_SGMII_MODE_DISABLE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+		UNIPHY_SGMIIPLUS_MODE_DISABLE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+		UNIPHY_XPCS_MODE_ENABLE;
+
+	hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
+
+	hppe_uniphy_instance_link_detect_get(dev_id, uniphy_index, &uniphy_instance_link_detect);
+	uniphy_instance_link_detect.bf.detect_los_from_sfp = UNIPHY_10GR_LINK_LOSS;
+	hppe_uniphy_instance_link_detect_set(dev_id, uniphy_index, &uniphy_instance_link_detect);
+
+	/* configure uniphy gcc software reset */
+	__adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
+
+	/* wait uniphy calibration done */
+	rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
+
+	/* configure gcc speed clock to 10g r mode*/
+	if (uniphy_index == SSDK_UNIPHY_INSTANCE1)
+		port_id = HPPE_MUX_PORT1;
+	else if (uniphy_index == SSDK_UNIPHY_INSTANCE2)
+		port_id = HPPE_MUX_PORT2;
+	adpt_hppe_gcc_port_speed_clock_set(dev_id, port_id, FAL_SPEED_10000);
+
+	/* enable instance clock */
+	qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+			1, A_TRUE);
+
+	/* release xpcs reset status */
+	__adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_FALSE);
+
+	return rv;
+}
+
+static sw_error_t
+__adpt_hppe_uniphy_sgmiiplus_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t ssdk_port = 0;
+
+	union uniphy_mode_ctrl_u uniphy_mode_ctrl;
+
+	memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	SSDK_DEBUG("uniphy %d is sgmiiplus mode\n", uniphy_index);
+#if defined(CPPE)
+	if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
+		&& (uniphy_index == SSDK_UNIPHY_INSTANCE0)) {
+		SSDK_DEBUG("cypress uniphy %d is sgmiiplus mode\n", uniphy_index);
+		rv = __adpt_cppe_uniphy_mode_set(dev_id, uniphy_index,
+			PORT_WRAPPER_SGMII_PLUS);
+		return rv;
+	}
+#endif
+
+	hppe_uniphy_reg_set(dev_id, UNIPHY_MISC2_REG_OFFSET,
+		uniphy_index, UNIPHY_MISC2_REG_SGMII_PLUS_MODE);
+	/*reset uniphy*/
+	hppe_uniphy_reg_set(dev_id, UNIPHY_PLL_RESET_REG_OFFSET,
+		uniphy_index, UNIPHY_PLL_RESET_REG_VALUE);
+	msleep(500);
+	hppe_uniphy_reg_set(dev_id, UNIPHY_PLL_RESET_REG_OFFSET,
+		uniphy_index, UNIPHY_PLL_RESET_REG_DEFAULT_VALUE);
+	msleep(500);
+
+	/* keep xpcs to reset status */
+	__adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE);
+
+	/* disable instance clock */
+	qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+				1, A_FALSE);
+
+	/* configure uniphy to Athr mode and sgmiiplus mode */
+	hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
+
+	ssdk_port = adpt_hppe_port_get_by_uniphy(dev_id, uniphy_index,
+		SSDK_UNIPHY_CHANNEL0);
+	if (A_TRUE == hsl_port_is_sfp(dev_id, ssdk_port)) {
+		uniphy_mode_ctrl.bf.newaddedfromhere_ch0_mode_ctrl_25m = 2;
+		SSDK_DEBUG("uniphy %d is a sgmiiplus fiber port!\n", uniphy_index);
+	}
+
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode =
+		UNIPHY_ATHEROS_NEGOTIATION;
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+		UNIPHY_CH0_QSGMII_SGMII_MODE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+		UNIPHY_CH0_SGMII_MODE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+		UNIPHY_SGMII_MODE_DISABLE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+		UNIPHY_SGMIIPLUS_MODE_ENABLE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+		UNIPHY_XPCS_MODE_DISABLE;
+
+	hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
+
+	/* configure uniphy gcc software reset */
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+#if defined(CPPE)
+		__adpt_cppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
+#endif
+	} else {
+		__adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
+	}
+
+	/* wait uniphy calibration done */
+	rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
+
+	/* enable instance clock */
+	qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+				1, A_TRUE);
+	return rv;
+}
+
+static sw_error_t
+__adpt_hppe_uniphy_sgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index, a_uint32_t channel)
+{
+	a_uint32_t i, max_port, mode, ssdk_port;
+	sw_error_t rv = SW_OK;
+	a_bool_t force_port = 0;
+
+	union uniphy_mode_ctrl_u uniphy_mode_ctrl;
+
+	memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	SSDK_DEBUG("uniphy %d is sgmii mode\n", uniphy_index);
+#if defined(CPPE)
+	if ((uniphy_index == SSDK_UNIPHY_INSTANCE0) &&
+		(channel == SSDK_UNIPHY_CHANNEL0)) {
+		if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+			if (hsl_port_prop_check(dev_id, SSDK_PHYSICAL_PORT4,
+					HSL_PP_EXCL_CPU) == A_TRUE) {
+				SSDK_DEBUG("cypress uniphy %d is sgmii mode\n", uniphy_index);
+				rv = __adpt_cppe_uniphy_mode_set(dev_id,
+					uniphy_index, PORT_WRAPPER_SGMII_CHANNEL0);
+				return rv;
+			}
+		}
+	}
+#endif
+
+	/*set the PHY mode to SGMII*/
+	hppe_uniphy_reg_set(dev_id, UNIPHY_MISC2_REG_OFFSET,
+		uniphy_index, UNIPHY_MISC2_REG_SGMII_MODE);
+	/*reset uniphy*/
+	hppe_uniphy_reg_set(dev_id, UNIPHY_PLL_RESET_REG_OFFSET,
+		uniphy_index, UNIPHY_PLL_RESET_REG_VALUE);
+	msleep(500);
+	hppe_uniphy_reg_set(dev_id, UNIPHY_PLL_RESET_REG_OFFSET,
+		uniphy_index, UNIPHY_PLL_RESET_REG_DEFAULT_VALUE);
+	msleep(500);
+
+	/* keep xpcs to reset status */
+	__adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE);
+
+	/* disable instance clock */
+	if (uniphy_index == SSDK_UNIPHY_INSTANCE0)
+		max_port = SSDK_PHYSICAL_PORT5;
+	else
+		max_port = SSDK_PHYSICAL_PORT1;
+
+	for (i = SSDK_PHYSICAL_PORT1; i <= max_port; i++)
+	{
+		qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+			i, A_FALSE);
+	}
+
+#if defined(CPPE)
+	if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) &&
+		(uniphy_index == SSDK_UNIPHY_INSTANCE0)) {
+		SSDK_DEBUG("uniphy %d sgmii channel selection\n", uniphy_index);
+		rv = __adpt_cppe_uniphy_channel_selection_set(dev_id,
+			CPPE_PCS0_CHANNEL0_SEL_PSGMII,
+			CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK);
+		SW_RTN_ON_ERROR (rv);
+	}
+#endif
+
+	/* configure uniphy to Athr mode and sgmii mode */
+	hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
+	mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index);
+
+	ssdk_port = adpt_hppe_port_get_by_uniphy(dev_id, uniphy_index,channel);
+	if (A_TRUE == hsl_port_is_sfp(dev_id, ssdk_port)) {
+		uniphy_mode_ctrl.bf.newaddedfromhere_ch0_mode_ctrl_25m = 0;
+		SSDK_DEBUG("port_id %d is a fiber port!\n", ssdk_port);
+	}
+
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode =
+		UNIPHY_ATHEROS_NEGOTIATION;
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+		UNIPHY_CH0_QSGMII_SGMII_MODE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+		UNIPHY_CH0_SGMII_MODE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+		UNIPHY_SGMIIPLUS_MODE_DISABLE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+		UNIPHY_XPCS_MODE_DISABLE;
+	if (uniphy_index == SSDK_UNIPHY_INSTANCE0) {
+		uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+			UNIPHY_SGMII_MODE_DISABLE;
+		/* select channel as a sgmii interface */
+		if (channel == SSDK_UNIPHY_CHANNEL0)
+		{
+			uniphy_mode_ctrl.bf.newaddedfromhere_ch1_ch0_sgmii =
+				UNIPHY_SGMII_CHANNEL1_DISABLE;
+			uniphy_mode_ctrl.bf.newaddedfromhere_ch4_ch1_0_sgmii =
+				UNIPHY_SGMII_CHANNEL4_DISABLE;
+		}
+		else if (channel == SSDK_UNIPHY_CHANNEL1)
+		{
+			uniphy_mode_ctrl.bf.newaddedfromhere_ch1_ch0_sgmii =
+				UNIPHY_SGMII_CHANNEL1_ENABLE;
+			uniphy_mode_ctrl.bf.newaddedfromhere_ch4_ch1_0_sgmii =
+				UNIPHY_SGMII_CHANNEL4_DISABLE;
+		}
+		else if (channel == SSDK_UNIPHY_CHANNEL4)
+		{
+			uniphy_mode_ctrl.bf.newaddedfromhere_ch1_ch0_sgmii =
+				UNIPHY_SGMII_CHANNEL1_DISABLE;
+			uniphy_mode_ctrl.bf.newaddedfromhere_ch4_ch1_0_sgmii =
+				UNIPHY_SGMII_CHANNEL4_ENABLE;
+		}
+	}
+	else
+	{
+		uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+			UNIPHY_SGMII_MODE_ENABLE;
+	}
+	hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
+
+	if (uniphy_index != SSDK_UNIPHY_INSTANCE0) {
+		if (uniphy_index == SSDK_UNIPHY_INSTANCE1) {
+			ssdk_port = SSDK_PHYSICAL_PORT5;
+		} else {
+			ssdk_port = SSDK_PHYSICAL_PORT6;
+		}
+		force_port = ssdk_port_feature_get(dev_id,
+			ssdk_port, PHY_F_FORCE);
+		if (force_port == A_TRUE) {
+			rv = hppe_uniphy_channel0_force_speed_mode_set(dev_id,
+				uniphy_index, UNIPHY_FORCE_SPEED_MODE_ENABLE);
+			SW_RTN_ON_ERROR (rv);
+			SSDK_INFO("ssdk uniphy %d connects force port\n",
+					uniphy_index);
+		}
+	}
+	/* configure uniphy gcc software reset */
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+#if defined(CPPE)
+		__adpt_cppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
+#endif
+	} else {
+		__adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
+	}
+
+	/* wait uniphy calibration done */
+	rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
+
+	/* enable instance clock */
+	if (uniphy_index == SSDK_UNIPHY_INSTANCE0)
+		max_port = SSDK_PHYSICAL_PORT5;
+	else
+		max_port = SSDK_PHYSICAL_PORT1;
+
+	for (i = SSDK_PHYSICAL_PORT1; i <= max_port; i++)
+	{
+		qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+			i, A_TRUE);
+	}
+
+	return rv;
+}
+
+static sw_error_t
+__adpt_hppe_uniphy_qsgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+	a_uint32_t i;
+	sw_error_t rv = SW_OK;
+
+	union uniphy_mode_ctrl_u uniphy_mode_ctrl;
+
+	memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	/* configure malibu phy to qsgmii mode*/
+	rv = hsl_port_phy_mode_set(dev_id, PORT_QSGMII);
+	SW_RTN_ON_ERROR (rv);
+
+	/* keep xpcs to reset status */
+	__adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE);
+
+	/* disable instance0 clock */
+	for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT6; i++)
+	{
+		qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+			i, A_FALSE);
+	}
+
+	/* configure uniphy to Athr mode and qsgmii mode */
+	hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode =
+		UNIPHY_ATHEROS_NEGOTIATION;
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+		UNIPHY_CH0_QSGMII_SGMII_MODE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+		UNIPHY_CH0_QSGMII_MODE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+		UNIPHY_SGMII_MODE_DISABLE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+		UNIPHY_SGMII_MODE_DISABLE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+		UNIPHY_XPCS_MODE_DISABLE;
+	hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
+
+	/* configure uniphy gcc software reset */
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+#if defined(CPPE)
+		__adpt_cppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
+#endif
+	} else {
+		__adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
+	}
+
+	/* wait uniphy calibration done */
+	rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
+
+	rv = hsl_port_phy_serdes_reset(dev_id);
+	SW_RTN_ON_ERROR (rv);
+
+	/* enable instance0 clock */
+	for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT6; i++)
+	{
+		qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+			i, A_TRUE);
+	}
+
+	return rv;
+}
+
+static sw_error_t
+__adpt_hppe_uniphy_psgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+	a_uint32_t i;
+	sw_error_t rv = SW_OK;
+#if defined(CPPE)
+	a_uint32_t phy_type = 0;
+#endif
+
+	union uniphy_mode_ctrl_u uniphy_mode_ctrl;
+
+	memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	SSDK_DEBUG("uniphy %d is psgmii mode\n", uniphy_index);
+#if defined(CPPE)
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+		phy_type = hsl_port_phyid_get(dev_id,
+				SSDK_PHYSICAL_PORT3);
+		if (phy_type == MALIBU2PORT_PHY) {
+			SSDK_INFO("cypress uniphy %d is qca8072 psgmii mode\n", uniphy_index);
+			rv = __adpt_cppe_uniphy_mode_set(dev_id, uniphy_index,
+				PORT_WRAPPER_PSGMII);
+			return rv;
+		}
+	}
+#endif
+
+	/* keep xpcs to reset status */
+	__adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE);
+
+	/* disable instance0 clock */
+	for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT6; i++)
+	{
+		qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+			i, A_FALSE);
+	}
+
+#if defined(CPPE)
+	if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) &&
+		(uniphy_index == SSDK_UNIPHY_INSTANCE0)) {
+		SSDK_INFO("uniphy %d psgmii channel selection\n", uniphy_index);
+		rv = __adpt_cppe_uniphy_channel_selection_set(dev_id,
+			CPPE_PCS0_CHANNEL0_SEL_PSGMII,
+			CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK);
+		SW_RTN_ON_ERROR (rv);
+	}
+#endif
+
+	/* configure uniphy to Athr mode and psgmii mode */
+	hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode =
+		UNIPHY_ATHEROS_NEGOTIATION;
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+		UNIPHY_CH0_PSGMII_MODE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+		UNIPHY_CH0_SGMII_MODE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+		UNIPHY_SGMII_MODE_DISABLE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+		UNIPHY_SGMIIPLUS_MODE_DISABLE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+		UNIPHY_XPCS_MODE_DISABLE;
+	hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
+
+	/* configure uniphy gcc software reset */
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+#if defined(CPPE)
+		__adpt_cppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
+#endif
+	} else {
+
+		__adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
+	}
+
+	/* wait uniphy calibration done */
+	rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
+
+	rv = hsl_port_phy_serdes_reset(dev_id);
+	SW_RTN_ON_ERROR (rv);
+
+	/* enable instance0 clock */
+	for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT6; i++)
+	{
+		qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+			i, A_TRUE);
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_uniphy_mode_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t clock = UNIPHY_CLK_RATE_125M;
+
+	if (mode == PORT_WRAPPER_MAX) {
+		ssdk_uniphy_raw_clock_reset(index);
+		return SW_OK;
+	}
+
+	switch(mode) {
+		case PORT_WRAPPER_PSGMII:
+		case PORT_WRAPPER_PSGMII_FIBER:
+			rv = __adpt_hppe_uniphy_psgmii_mode_set(dev_id, index);
+			break;
+
+		case PORT_WRAPPER_QSGMII:
+			rv = __adpt_hppe_uniphy_qsgmii_mode_set(dev_id, index);
+			break;
+
+		case PORT_WRAPPER_SGMII0_RGMII4:
+		case PORT_WRAPPER_SGMII_CHANNEL0:
+		case PORT_WRAPPER_SGMII_FIBER:
+			rv = __adpt_hppe_uniphy_sgmii_mode_set(dev_id, index,
+				SSDK_UNIPHY_CHANNEL0);
+			break;
+
+		case PORT_WRAPPER_SGMII1_RGMII4:
+		case PORT_WRAPPER_SGMII_CHANNEL1:
+			rv = __adpt_hppe_uniphy_sgmii_mode_set(dev_id, index,
+				SSDK_UNIPHY_CHANNEL1);
+			break;
+
+		case PORT_WRAPPER_SGMII4_RGMII4:
+		case PORT_WRAPPER_SGMII_CHANNEL4:
+			rv = __adpt_hppe_uniphy_sgmii_mode_set(dev_id, index,
+				SSDK_UNIPHY_CHANNEL4);
+			break;
+
+		case PORT_WRAPPER_SGMII_PLUS:
+			rv = __adpt_hppe_uniphy_sgmiiplus_mode_set(dev_id, index);
+			clock = UNIPHY_CLK_RATE_312M;
+			break;
+
+		case PORT_WRAPPER_10GBASE_R:
+			rv = __adpt_hppe_uniphy_10g_r_mode_set(dev_id, index);
+			clock = UNIPHY_CLK_RATE_312M;
+			break;
+
+		case PORT_WRAPPER_USXGMII:
+			rv = __adpt_hppe_uniphy_usxgmii_mode_set(dev_id, index);
+			clock = UNIPHY_CLK_RATE_312M;
+			break;
+
+		default:
+			rv = SW_FAIL;
+	}
+	if (SW_OK == rv) {
+		ssdk_uniphy_raw_clock_set(index, UNIPHY_RX, clock);
+		ssdk_uniphy_raw_clock_set(index, UNIPHY_TX, clock);
+	}
+	return rv;
+}
+sw_error_t adpt_hppe_uniphy_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	p_adpt_api->adpt_uniphy_mode_set = adpt_hppe_uniphy_mode_set;
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/hppe/adpt_hppe_vsi.c b/qca-ssdk/src/adpt/hppe/adpt_hppe_vsi.c
new file mode 100755
index 0000000..a81f326
--- /dev/null
+++ b/qca-ssdk/src/adpt/hppe/adpt_hppe_vsi.c
@@ -0,0 +1,637 @@
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "fal_type.h"
+#include "adpt.h"
+#include "hppe_vsi_reg.h"
+#include "hppe_vsi.h"
+#include "hppe_portvlan_reg.h"
+#include "hppe_portvlan.h"
+#include "hppe_ip_reg.h"
+#include "hppe_ip.h"
+
+#define ADPT_VSI_MAX FAL_VSI_MAX
+#define ADPT_VSI_STRIP_VLAN_TAG 2
+
+enum{
+	ADPT_VSI_ADD,
+	ADPT_VSI_DEL
+};
+
+static a_bool_t _adpt_hppe_vsi_xlt_match(a_uint32_t dev_id, fal_port_t port_id,
+				a_uint32_t stag_vid, a_uint32_t ctag_vid, union xlt_rule_tbl_u *xlt_rule)
+{
+	if(stag_vid != FAL_VLAN_INVALID)
+	{
+		if((xlt_rule->bf.skey_vid_incl) &&
+			(xlt_rule->bf.skey_vid == stag_vid))
+		{
+			if(ctag_vid != FAL_VLAN_INVALID)
+			{
+				if((xlt_rule->bf.ckey_vid_incl) &&
+					(xlt_rule->bf.ckey_vid == ctag_vid))
+				{
+					return A_TRUE;
+				}
+			}
+			else
+			{
+				if(!(xlt_rule->bf.ckey_vid_incl))
+				{
+					return A_TRUE;
+				}
+			}
+		}
+	}
+	else
+	{
+		if(!(xlt_rule->bf.skey_vid_incl))
+		{
+			if(ctag_vid != FAL_VLAN_INVALID)
+			{
+				if((xlt_rule->bf.ckey_vid_incl) &&
+					(xlt_rule->bf.ckey_vid == ctag_vid))
+				{
+					return A_TRUE;
+				}
+			}
+			else
+			{
+				if(!(xlt_rule->bf.ckey_vid_incl))
+				{
+					return A_TRUE;
+				}
+			}
+		}
+	}
+	return A_FALSE;
+}
+
+static sw_error_t _adpt_hppe_vsi_xlt_update(a_uint32_t dev_id,
+				a_uint32_t vsi_id, a_uint32_t port_id,
+				a_uint32_t stag_vid, a_uint32_t ctag_vid,
+				a_uint32_t op)
+{
+	a_int32_t index = 0;
+	a_uint32_t new_entry = 0;
+	sw_error_t rv;
+	union xlt_rule_tbl_u xlt_rule;
+	union xlt_action_tbl_u xlt_action;
+
+	/*printk("%s,%d: port_id 0x%x svlan %d cvlan %d vsi %d op %d\n",
+			__FUNCTION__, __LINE__, port_id, stag_vid, ctag_vid, vsi_id, op);*/
+
+	for(index = XLT_RULE_TBL_NUM - 1; index >= 0; index--)
+	{
+		rv = hppe_xlt_rule_tbl_get(dev_id, index, &xlt_rule);
+		if( rv != SW_OK )
+			return rv;
+		rv = hppe_xlt_action_tbl_get(dev_id, index, &xlt_action);
+		if( rv != SW_OK )
+			return rv;
+		if(xlt_rule.bf.valid == A_FALSE && index >= new_entry)
+		{
+			new_entry = index;
+		}
+		if(xlt_rule.bf.valid == A_TRUE)
+		{
+			if(_adpt_hppe_vsi_xlt_match(dev_id, port_id,
+				stag_vid, ctag_vid, &xlt_rule))
+			{
+				if((xlt_action.bf.vsi_cmd == A_TRUE) &&
+					(xlt_action.bf.vsi == vsi_id))
+					break;
+			}
+		}
+	}
+
+	if(index >= 0) /*found*/
+	{
+		if(op == ADPT_VSI_DEL)/*Delete*/
+		{
+			/*printk("%s,%d: port_id 0x%x svlan %d cvlan %d vsi %d op %d\n",
+				__FUNCTION__, __LINE__, port_id, stag_vid, ctag_vid, vsi_id, op);*/
+			if(!(xlt_rule.bf.port_bitmap & (1<<port_id)))
+				return SW_OK;
+			xlt_rule.bf.port_bitmap &= (~(1<<port_id));
+			if(xlt_rule.bf.port_bitmap == 0)
+			{
+				rv= hppe_xlt_rule_tbl_valid_set(dev_id, index, A_FALSE);
+				return rv;
+			}
+		}
+		else/*add*/
+		{
+			/*printk("%s,%d: port_id 0x%x svlan %d cvlan %d vsi %d op %d\n",
+				__FUNCTION__, __LINE__, port_id, stag_vid, ctag_vid, vsi_id, op);*/
+			xlt_rule.bf.port_bitmap |= (1<<port_id);
+		}
+		/*printk("%s,%d: port_map 0x%x svlan %d cvlan %d vsi %d xlt table update index %d\n",
+				__FUNCTION__, __LINE__, xlt_rule.bf.port_bitmap, stag_vid, ctag_vid, vsi_id, index);*/
+		rv = hppe_xlt_rule_tbl_port_bitmap_set(dev_id, index, xlt_rule.bf.port_bitmap);
+		return rv;
+	}
+	else/*not found*/
+	{
+		if(op == ADPT_VSI_DEL)
+			return SW_OK;
+		if(new_entry >= XLT_RULE_TBL_NUM)
+		{
+			printk("%s,%d: port_id 0x%x svlan %d cvlan %d vsi %d xlt table is full\n",
+					__FUNCTION__, __LINE__, port_id, stag_vid, ctag_vid, vsi_id);
+			return SW_NO_RESOURCE;
+		}
+		else/*new entry exist*/
+		{
+			aos_mem_zero(&xlt_rule, sizeof(union xlt_rule_tbl_u));
+			/*printk("%s,%d: port_id 0x%x svlan %d cvlan %d vsi %d xlt table add index %d\n",
+					__FUNCTION__, __LINE__, port_id, stag_vid, ctag_vid, vsi_id, new_entry);*/
+			xlt_rule.bf.valid = A_TRUE;
+			if(ctag_vid != FAL_VLAN_INVALID)
+			{
+				xlt_rule.bf.ckey_vid_incl = A_TRUE;
+				xlt_rule.bf.ckey_vid = ctag_vid;
+				if(ctag_vid == 0)
+					xlt_rule.bf.ckey_fmt_1 = 0x1;
+				else
+					xlt_rule.bf.ckey_fmt_1 = 0x2;
+			}
+			else
+					xlt_rule.bf.ckey_fmt_0 = 0x1;
+			if(stag_vid != FAL_VLAN_INVALID)
+			{
+				xlt_rule.bf.skey_vid_incl = A_TRUE;
+				xlt_rule.bf.skey_vid = stag_vid;
+				if(stag_vid == 0)
+					xlt_rule.bf.skey_fmt = 0x2;
+				else
+					xlt_rule.bf.skey_fmt = 0x4;
+			}
+			else
+					xlt_rule.bf.skey_fmt = 0x1;
+			xlt_rule.bf.port_bitmap = (1<<port_id);
+			rv = hppe_xlt_rule_tbl_set(dev_id, new_entry, &xlt_rule);
+			if( rv != SW_OK )
+				return rv;
+			aos_mem_zero(&xlt_action, sizeof(union xlt_action_tbl_u));
+			xlt_action.bf.vsi_cmd = A_TRUE;
+			xlt_action.bf.vsi = vsi_id;
+			if(ctag_vid != FAL_VLAN_INVALID)
+			{
+				xlt_action.bf.xlt_cvid_cmd = ADPT_VSI_STRIP_VLAN_TAG;
+			}
+			if(stag_vid != FAL_VLAN_INVALID)
+			{
+				xlt_action.bf.xlt_svid_cmd = ADPT_VSI_STRIP_VLAN_TAG;
+			}
+			rv = hppe_xlt_action_tbl_set(dev_id, new_entry, &xlt_action);
+			return rv;
+		}
+	}
+}
+
+sw_error_t
+adpt_hppe_port_vlan_vsi_get(a_uint32_t dev_id, fal_port_t port_id,
+				a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t *vsi_id)
+{
+	a_uint32_t index = 0;
+	sw_error_t rv;
+	union xlt_rule_tbl_u xlt_rule;
+	union xlt_action_tbl_u xlt_action;
+	for(index = 0; index < XLT_RULE_TBL_NUM; index++)
+	{
+		rv = hppe_xlt_rule_tbl_get(dev_id, index, &xlt_rule);
+		if( rv != SW_OK )
+			return rv;
+		rv = hppe_xlt_action_tbl_get(dev_id, index, &xlt_action);
+		if( rv != SW_OK )
+			return rv;
+		if(xlt_rule.bf.valid == A_TRUE)
+		{
+			if(_adpt_hppe_vsi_xlt_match(dev_id, port_id,
+					stag_vid, ctag_vid, &xlt_rule))
+			{
+				if((xlt_rule.bf.port_bitmap&(1<<port_id))&&
+					(xlt_action.bf.vsi_cmd == A_TRUE))
+				{
+					*vsi_id = xlt_action.bf.vsi;
+					return SW_OK;
+				}
+			}
+		}
+	}
+
+	/*not found*/
+	*vsi_id = FAL_VSI_INVALID;
+	return SW_NOT_FOUND;
+}
+
+sw_error_t
+adpt_hppe_port_vlan_vsi_set(a_uint32_t dev_id, fal_port_t port_id,
+				a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id)
+{
+	sw_error_t rv;
+	a_uint32_t org_vsi;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if((stag_vid != FAL_VLAN_INVALID && stag_vid > FAL_VLAN_MAX)||
+	    (ctag_vid != FAL_VLAN_INVALID && ctag_vid > FAL_VLAN_MAX))
+	    return SW_OUT_OF_RANGE;
+
+	adpt_hppe_port_vlan_vsi_get(dev_id, port_id, stag_vid, ctag_vid, &org_vsi);
+
+	if(org_vsi == vsi_id)
+		return SW_OK;
+
+	if(FAL_VSI_INVALID == vsi_id || org_vsi != FAL_VSI_INVALID)
+	{
+		rv = _adpt_hppe_vsi_xlt_update(dev_id, org_vsi, port_id,
+				stag_vid, ctag_vid, ADPT_VSI_DEL);
+		if(rv != SW_OK)
+			return rv;
+	}
+	if(vsi_id != FAL_VSI_INVALID)
+	{
+		rv = _adpt_hppe_vsi_xlt_update(dev_id, vsi_id, port_id,
+				stag_vid, ctag_vid, ADPT_VSI_ADD);
+	}
+
+	return rv;
+}
+
+
+#ifndef IN_VSI_MINI
+sw_error_t
+adpt_hppe_port_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vsi_id)
+{
+	union l3_vp_port_tbl_u l3_vp_port_tbl;
+	sw_error_t rv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	//printk("%s, %d: port %d, vsi %d\n", __FUNCTION__, __LINE__, port_id, vsi_id);
+	if(!(FAL_IS_PPORT(port_id)) && !(FAL_IS_VPORT(port_id)))
+		return SW_BAD_VALUE;
+
+	rv = hppe_l3_vp_port_tbl_get(dev_id, FAL_PORT_ID_VALUE(port_id), &l3_vp_port_tbl);
+	if (SW_OK != rv)
+		return rv;
+	if(l3_vp_port_tbl.bf.vsi_valid)
+		*vsi_id = l3_vp_port_tbl.bf.vsi;
+	else
+		*vsi_id = FAL_VSI_INVALID;
+
+	return rv;
+}
+#endif
+
+sw_error_t
+adpt_hppe_port_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vsi_id)
+{
+	union l3_vp_port_tbl_u l3_vp_port_tbl;
+	sw_error_t rv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	//printk("%s, %d: port %d, vsi %d\n", __FUNCTION__, __LINE__, port_id, vsi_id);
+	if(!(FAL_IS_PPORT(port_id)) && !(FAL_IS_VPORT(port_id)))
+		return SW_BAD_VALUE;
+
+	rv = hppe_l3_vp_port_tbl_get(dev_id, FAL_PORT_ID_VALUE(port_id), &l3_vp_port_tbl);
+	if (SW_OK != rv)
+		return rv;
+	if(FAL_VSI_INVALID == vsi_id)
+	{
+		l3_vp_port_tbl.bf.vsi_valid = A_FALSE;
+		l3_vp_port_tbl.bf.vsi = 0;
+	}
+	else
+	{
+		l3_vp_port_tbl.bf.vsi_valid = A_TRUE;
+		l3_vp_port_tbl.bf.vsi = vsi_id;
+	}
+	rv = hppe_l3_vp_port_tbl_set(dev_id, FAL_PORT_ID_VALUE(port_id), &l3_vp_port_tbl);
+	if( rv != SW_OK )
+		return rv;
+	//printk("%s, %d: port %d, vsi %d\n", __FUNCTION__, __LINE__, port_id, vsi_id);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_vsi_stamove_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove)
+{
+	sw_error_t rv;
+	union vsi_tbl_u vsi_tbl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(stamove);
+
+	rv = hppe_vsi_tbl_get( dev_id, vsi_id, &vsi_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	vsi_tbl.bf.station_move_lrn_en = stamove->stamove_en;
+	vsi_tbl.bf.station_move_fwd_cmd = stamove->action;
+
+	rv = hppe_vsi_tbl_set( dev_id, vsi_id, &vsi_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	return SW_OK;
+}
+#ifndef IN_VSI_MINI
+sw_error_t
+adpt_hppe_vsi_stamove_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove)
+{
+	sw_error_t rv;
+	union vsi_tbl_u vsi_tbl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(stamove);
+
+	rv = hppe_vsi_tbl_get( dev_id, vsi_id, &vsi_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	stamove->stamove_en = vsi_tbl.bf.station_move_lrn_en;
+	stamove->action = vsi_tbl.bf.station_move_fwd_cmd;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_vsi_newaddr_lrn_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn)
+{
+	sw_error_t rv;
+	union vsi_tbl_u vsi_tbl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(newaddr_lrn);
+
+	rv = hppe_vsi_tbl_get( dev_id, vsi_id, &vsi_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	newaddr_lrn->lrn_en = vsi_tbl.bf.new_addr_lrn_en;
+	newaddr_lrn->action = vsi_tbl.bf.new_addr_fwd_cmd;
+
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+adpt_hppe_vsi_newaddr_lrn_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn)
+{
+	sw_error_t rv;
+	union vsi_tbl_u vsi_tbl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(newaddr_lrn);
+
+	rv = hppe_vsi_tbl_get( dev_id, vsi_id, &vsi_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	vsi_tbl.bf.new_addr_lrn_en = newaddr_lrn->lrn_en;
+	vsi_tbl.bf.new_addr_fwd_cmd = newaddr_lrn->action;
+
+	rv = hppe_vsi_tbl_set( dev_id, vsi_id, &vsi_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_vsi_member_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member)
+{
+	sw_error_t rv;
+	union vsi_tbl_u vsi_tbl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(vsi_member);
+
+	rv = hppe_vsi_tbl_get( dev_id, vsi_id, &vsi_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	vsi_tbl.bf.bc_bitmap = vsi_member->bc_ports & 0xff;
+	vsi_tbl.bf.member_port_bitmap = vsi_member->member_ports & 0xff;
+	vsi_tbl.bf.umc_bitmap = vsi_member->umc_ports & 0xff;
+	vsi_tbl.bf.uuc_bitmap = vsi_member->uuc_ports & 0xff;
+
+	rv = hppe_vsi_tbl_set(dev_id, vsi_id, &vsi_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	return SW_OK;
+
+}
+
+sw_error_t
+adpt_hppe_vsi_member_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member)
+{
+	sw_error_t rv;
+	union vsi_tbl_u vsi_tbl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(vsi_member);
+
+	rv = hppe_vsi_tbl_get( dev_id, vsi_id, &vsi_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	vsi_member->bc_ports = vsi_tbl.bf.bc_bitmap;
+	vsi_member->member_ports = vsi_tbl.bf.member_port_bitmap;
+	vsi_member->umc_ports = vsi_tbl.bf.umc_bitmap;
+	vsi_member->uuc_ports = vsi_tbl.bf.uuc_bitmap;
+
+	rv = hppe_vsi_tbl_set(dev_id, vsi_id, &vsi_tbl);
+	if( rv != SW_OK )
+		return rv;
+
+	return SW_OK;
+
+}
+
+#ifndef IN_VSI_MINI
+sw_error_t
+adpt_hppe_vsi_counter_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_counter_t *counter)
+{
+	sw_error_t rv;
+	union vlan_cnt_tbl_u in_cnt;
+	union eg_vsi_counter_tbl_u eg_cnt;
+	union pre_l2_cnt_tbl_u pre_l2_cnt;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(counter);
+
+	rv = hppe_vlan_cnt_tbl_get(dev_id, vsi_id, &in_cnt);
+	if( rv != SW_OK )
+		return rv;
+
+    counter->rx_packet_counter = in_cnt.bf.rx_pkt_cnt;
+    counter->rx_byte_counter = in_cnt.bf.rx_byte_cnt_1;
+    counter->rx_byte_counter = (counter->rx_byte_counter<<32)|in_cnt.bf.rx_byte_cnt_0;
+
+	rv = hppe_eg_vsi_counter_tbl_get(dev_id, vsi_id, &eg_cnt);
+	if( rv != SW_OK )
+		return rv;
+
+    counter->tx_packet_counter = eg_cnt.bf.tx_packets;
+    counter->tx_byte_counter = eg_cnt.bf.tx_bytes_1;
+    counter->tx_byte_counter = (counter->tx_byte_counter<<32)|eg_cnt.bf.tx_bytes_0;
+
+    rv = hppe_pre_l2_cnt_tbl_get(dev_id, vsi_id, &pre_l2_cnt);
+	if( rv != SW_OK )
+		return rv;
+
+	counter->fwd_packet_counter = pre_l2_cnt.bf.rx_pkt_cnt;
+	counter->fwd_byte_counter = pre_l2_cnt.bf.rx_byte_cnt_1;
+	counter->fwd_byte_counter = (counter->fwd_byte_counter<<32)|pre_l2_cnt.bf.rx_byte_cnt_0;
+	counter->drop_packet_counter = pre_l2_cnt.bf.rx_drop_pkt_cnt_1<<24|pre_l2_cnt.bf.rx_drop_pkt_cnt_0;
+	counter->drop_byte_counter = pre_l2_cnt.bf.rx_drop_byte_cnt_1;
+	counter->drop_byte_counter = (counter->drop_byte_counter<<24)|pre_l2_cnt.bf.rx_drop_byte_cnt_0;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_hppe_vsi_counter_cleanup(a_uint32_t dev_id, a_uint32_t vsi_id)
+{
+	sw_error_t rv;
+	union vlan_cnt_tbl_u in_cnt;
+	union eg_vsi_counter_tbl_u eg_cnt;
+	union pre_l2_cnt_tbl_u pre_l2_cnt;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	memset(&in_cnt, 0, sizeof(in_cnt));
+	rv = hppe_vlan_cnt_tbl_set(dev_id, vsi_id, &in_cnt);
+	if( rv != SW_OK )
+		return rv;
+
+	memset(&eg_cnt, 0, sizeof(eg_cnt));
+	rv = hppe_eg_vsi_counter_tbl_set(dev_id, vsi_id, &eg_cnt);
+	if( rv != SW_OK )
+		return rv;
+
+	memset(&pre_l2_cnt, 0, sizeof(pre_l2_cnt));
+	rv = hppe_pre_l2_cnt_tbl_set(dev_id, vsi_id, &pre_l2_cnt);
+	if( rv != SW_OK )
+		return rv;
+
+	return SW_OK;
+}
+#endif
+
+
+void adpt_hppe_vsi_func_bitmap_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return;
+
+
+	p_adpt_api->adpt_vsi_func_bitmap = ((1<<FUNC_PORT_VLAN_VSI_SET)|
+						(1<<FUNC_PORT_VLAN_VSI_GET)|
+						(1<<FUNC_PORT_VSI_SET)|
+						(1<<FUNC_PORT_VSI_GET)|
+						(1<<FUNC_VSI_STAMOVE_SET)|
+						(1<<FUNC_VSI_STAMOVE_GET)|
+						(1<<FUNC_VSI_NEWADDR_LRN_SET)|
+						(1<<FUNC_VSI_NEWADDR_LRN_GET)|
+						(1<<FUNC_VSI_MEMBER_SET)|
+						(1<<FUNC_VSI_MEMBER_GET)|
+						(1<<FUNC_VSI_COUNTER_GET)|
+						(1<<FUNC_VSI_COUNTER_CLEANUP));
+
+	return;
+}
+
+static void adpt_hppe_vsi_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api)
+{
+	if(p_adpt_api == NULL)
+		return;
+
+	p_adpt_api->adpt_port_vlan_vsi_set = NULL;
+	p_adpt_api->adpt_port_vlan_vsi_get = NULL;
+	p_adpt_api->adpt_port_vsi_set = NULL;
+	p_adpt_api->adpt_port_vsi_get = NULL;
+	p_adpt_api->adpt_vsi_stamove_set = NULL;
+	p_adpt_api->adpt_vsi_stamove_get = NULL;
+	p_adpt_api->adpt_vsi_newaddr_lrn_get = NULL;
+	p_adpt_api->adpt_vsi_newaddr_lrn_set = NULL;
+	p_adpt_api->adpt_vsi_member_set = NULL;
+	p_adpt_api->adpt_vsi_member_get = NULL;
+	p_adpt_api->adpt_vsi_counter_get = NULL;
+	p_adpt_api->adpt_vsi_counter_cleanup = NULL;
+
+	return;
+}
+
+
+sw_error_t adpt_hppe_vsi_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	adpt_hppe_vsi_func_unregister(dev_id, p_adpt_api);
+
+#ifndef IN_VSI_MINI
+	if(p_adpt_api->adpt_vsi_func_bitmap & (1<<FUNC_PORT_VSI_GET))
+		p_adpt_api->adpt_port_vsi_get = adpt_hppe_port_vsi_get;
+	if(p_adpt_api->adpt_vsi_func_bitmap & (1<<FUNC_VSI_STAMOVE_GET))
+		p_adpt_api->adpt_vsi_stamove_get = adpt_hppe_vsi_stamove_get;
+	if(p_adpt_api->adpt_vsi_func_bitmap & (1<<FUNC_VSI_NEWADDR_LRN_GET))
+		p_adpt_api->adpt_vsi_newaddr_lrn_get = adpt_hppe_vsi_newaddr_lrn_get;
+	if(p_adpt_api->adpt_vsi_func_bitmap & (1<<FUNC_VSI_COUNTER_GET))
+		p_adpt_api->adpt_vsi_counter_get = adpt_hppe_vsi_counter_get;
+	if(p_adpt_api->adpt_vsi_func_bitmap & (1<<FUNC_VSI_COUNTER_CLEANUP))
+		p_adpt_api->adpt_vsi_counter_cleanup = adpt_hppe_vsi_counter_cleanup;
+#endif
+	if(p_adpt_api->adpt_vsi_func_bitmap & (1<<FUNC_PORT_VLAN_VSI_SET))
+		p_adpt_api->adpt_port_vlan_vsi_set = adpt_hppe_port_vlan_vsi_set;
+	if(p_adpt_api->adpt_vsi_func_bitmap & (1<<FUNC_PORT_VLAN_VSI_GET))
+		p_adpt_api->adpt_port_vlan_vsi_get = adpt_hppe_port_vlan_vsi_get;
+	if(p_adpt_api->adpt_vsi_func_bitmap & (1<<FUNC_PORT_VSI_SET))
+		p_adpt_api->adpt_port_vsi_set = adpt_hppe_port_vsi_set;
+	if(p_adpt_api->adpt_vsi_func_bitmap & (1<<FUNC_VSI_STAMOVE_SET))
+		p_adpt_api->adpt_vsi_stamove_set = adpt_hppe_vsi_stamove_set;
+	if(p_adpt_api->adpt_vsi_func_bitmap & (1<<FUNC_VSI_NEWADDR_LRN_SET))
+		p_adpt_api->adpt_vsi_newaddr_lrn_set = adpt_hppe_vsi_newaddr_lrn_set;
+	if(p_adpt_api->adpt_vsi_func_bitmap & (1<<FUNC_VSI_MEMBER_SET))
+		p_adpt_api->adpt_vsi_member_set = adpt_hppe_vsi_member_set;
+	if(p_adpt_api->adpt_vsi_func_bitmap & (1<<FUNC_VSI_MEMBER_GET))
+		p_adpt_api->adpt_vsi_member_get = adpt_hppe_vsi_member_get;
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/mp/Makefile b/qca-ssdk/src/adpt/mp/Makefile
new file mode 100644
index 0000000..df13503
--- /dev/null
+++ b/qca-ssdk/src/adpt/mp/Makefile
@@ -0,0 +1,32 @@
+LOC_DIR=src/adpt/mp
+LIB=ADPT
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=adpt_mp_interrupt.c
+
+ifeq (TRUE, $(IN_MIB))
+  SRC_LIST += adpt_mp_mib.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+  SRC_LIST += adpt_mp_portctrl.c
+endif
+
+ifeq (TRUE, $(IN_UNIPHY))
+  SRC_LIST += adpt_mp_uniphy.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+  SRC_LIST += adpt_mp_led.c
+endif
+
+ifeq (, $(filter MP, $(SUPPORT_CHIP)))
+  SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/adpt/mp/adpt_mp_interrupt.c b/qca-ssdk/src/adpt/mp/adpt_mp_interrupt.c
new file mode 100755
index 0000000..3e8ca50
--- /dev/null
+++ b/qca-ssdk/src/adpt/mp/adpt_mp_interrupt.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "adpt.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_phy.h"
+#include "hsl_port_prop.h"
+#include "adpt_mp.h"
+
+static sw_error_t
+adpt_mp_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id,
+	a_uint32_t intr_mask_flag)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	SW_RTN_ON_NULL (phy_drv->phy_intr_mask_set);
+
+	rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = phy_drv->phy_intr_mask_set(dev_id, phy_id, intr_mask_flag);
+
+	return rv;
+}
+
+static sw_error_t
+adpt_mp_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id,
+	a_uint32_t * intr_mask_flag)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	SW_RTN_ON_NULL (phy_drv->phy_intr_mask_get);
+
+	rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = phy_drv->phy_intr_mask_get(dev_id, phy_id, intr_mask_flag);
+
+	return rv;
+}
+
+static sw_error_t
+adpt_mp_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id,
+	a_uint32_t * intr_status)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	SW_RTN_ON_NULL (phy_drv->phy_intr_status_get);
+
+	rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = phy_drv->phy_intr_status_get(dev_id, phy_id, intr_status);
+
+	return rv;
+}
+
+sw_error_t adpt_mp_intr_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	SW_RTN_ON_NULL (p_adpt_api);
+
+	p_adpt_api->adpt_intr_port_link_mask_set = adpt_mp_intr_port_link_mask_set;
+	p_adpt_api->adpt_intr_port_link_mask_get = adpt_mp_intr_port_link_mask_get;
+	p_adpt_api->adpt_intr_port_link_status_get = adpt_mp_intr_port_link_status_get;
+
+	return SW_OK;
+}
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/mp/adpt_mp_led.c b/qca-ssdk/src/adpt/mp/adpt_mp_led.c
new file mode 100644
index 0000000..335d2ce
--- /dev/null
+++ b/qca-ssdk/src/adpt/mp/adpt_mp_led.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "adpt.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_phy.h"
+#include "hsl_port_prop.h"
+#include "adpt_mp.h"
+
+static sw_error_t
+adpt_mp_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+	led_pattern_id_t led_pattern_id, led_ctrl_pattern_t * pattern)
+{
+	sw_error_t rv;
+	a_uint32_t phy_addr, port_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK(dev_id);
+
+	if(group != LED_LAN_PORT_GROUP && group != LED_WAN_PORT_GROUP)
+	{
+		SSDK_ERROR("group %x is not supported\n", group);
+		return SW_NOT_SUPPORTED;
+	}
+	port_id = led_pattern_id;
+	if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	SW_RTN_ON_NULL (phy_drv->phy_led_ctrl_pattern_set);
+
+	rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_addr);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = phy_drv->phy_led_ctrl_pattern_set(dev_id, phy_addr, pattern);
+
+	return rv;
+}
+
+static sw_error_t
+adpt_mp_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+	led_pattern_id_t led_pattern_id, led_ctrl_pattern_t * pattern)
+{
+	sw_error_t rv;
+	a_uint32_t phy_addr, port_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK(dev_id);
+
+	if(group != LED_LAN_PORT_GROUP && group != LED_WAN_PORT_GROUP)
+	{
+		SSDK_ERROR("group %x is not supported\n", group);
+		return SW_NOT_SUPPORTED;
+	}
+
+	port_id = led_pattern_id;
+
+	if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	SW_RTN_ON_NULL (phy_drv->phy_led_ctrl_pattern_get);
+
+	rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_addr);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = phy_drv->phy_led_ctrl_pattern_get(dev_id, phy_addr, pattern);
+
+	return rv;
+}
+
+static sw_error_t
+adpt_mp_led_ctrl_source_set(a_uint32_t dev_id, a_uint32_t source_id,
+	led_ctrl_pattern_t *pattern)
+{
+	sw_error_t rv;
+	a_uint32_t phy_addr, port_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK(dev_id);
+
+	/*one port can support max three led source*/
+	port_id = source_id/PORT_LED_SOURCE_MAX+1;
+	source_id = source_id%PORT_LED_SOURCE_MAX;
+
+	if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	SW_RTN_ON_NULL (phy_drv->phy_led_ctrl_source_set);
+
+	rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_addr);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = phy_drv->phy_led_ctrl_source_set(dev_id, phy_addr, source_id,
+		pattern);
+
+	return rv;
+}
+
+sw_error_t adpt_mp_led_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	SW_RTN_ON_NULL (p_adpt_api);
+
+	p_adpt_api->adpt_led_ctrl_pattern_set = adpt_mp_led_ctrl_pattern_set;
+	p_adpt_api->adpt_led_ctrl_pattern_get = adpt_mp_led_ctrl_pattern_get;
+	p_adpt_api->adpt_led_ctrl_source_set = adpt_mp_led_ctrl_source_set;
+
+	return SW_OK;
+}
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/mp/adpt_mp_mib.c b/qca-ssdk/src/adpt/mp/adpt_mp_mib.c
new file mode 100755
index 0000000..8aa84d0
--- /dev/null
+++ b/qca-ssdk/src/adpt/mp/adpt_mp_mib.c
@@ -0,0 +1,360 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "mp_mib_reg.h"
+#include "mp_mib.h"
+#include "adpt.h"
+#include "adpt_mp.h"
+
+sw_error_t
+adpt_mp_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	union mmc_control_u mmc_control;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	rv = mp_mmc_control_get(dev_id, MP_GMAC0, &mmc_control);
+	SW_RTN_ON_ERROR(rv);
+	if(mmc_control.bf.rstonrd)
+	{
+		*enable = A_FALSE;
+	}
+	else
+	{
+		*enable = A_TRUE;
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_mp_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0, status = 0;
+	union mmc_control_u mmc_control;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (enable == A_TRUE)
+	{
+		status = A_FALSE;
+	}
+	else
+	{
+		status = A_TRUE;
+	}
+	for(gmac_id = MP_GMAC0; gmac_id <= MP_GMAC1; gmac_id++)
+	{
+		rv = mp_mmc_control_get(dev_id, gmac_id, &mmc_control);
+		SW_RTN_ON_ERROR(rv);
+		mmc_control.bf.rstonrd = status;
+		rv = mp_mmc_control_set(dev_id, gmac_id, &mmc_control);
+		SW_RTN_ON_ERROR(rv);
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_mp_mib_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	union mmc_control_u mmc_control;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	rv = mp_mmc_control_get(dev_id, MP_GMAC0, &mmc_control);
+	SW_RTN_ON_ERROR(rv);
+	if(mmc_control.bf.cntfreez)
+	{
+		*enable = A_FALSE;
+	}
+	else
+	{
+		*enable = A_TRUE;
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_mp_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0, status = 0;
+	union mmc_control_u mmc_control;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (enable == A_TRUE)
+	{
+		status = A_FALSE;
+	}
+	else
+	{
+		status = A_TRUE;
+	}
+	for(gmac_id = MP_GMAC0; gmac_id <= MP_GMAC1; gmac_id++)
+	{
+		rv = mp_mmc_control_get(dev_id, gmac_id, &mmc_control);
+		SW_RTN_ON_ERROR(rv);
+		mmc_control.bf.cntfreez = status;
+		rv = mp_mmc_control_set(dev_id, gmac_id, &mmc_control);
+		SW_RTN_ON_ERROR(rv);
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_mp_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mmc_control_u mmc_control;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+	rv = mp_mmc_control_get(dev_id, gmac_id, &mmc_control);
+	SW_RTN_ON_ERROR(rv);
+	mmc_control.bf.cntrst = A_TRUE;
+	rv = mp_mmc_control_set(dev_id, gmac_id, &mmc_control);
+
+	return rv;
+}
+
+static sw_error_t
+adpt_mp_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+	fal_mib_info_t * mib_info)
+{
+	a_uint32_t gmac_id = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mib_info);
+	MP_PORT_ID_CHECK(port_id);
+	memset(mib_info, 0, sizeof(fal_mib_info_t));
+
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+	mp_tx_broadcast_frames_good_get(dev_id, gmac_id,
+		(union tx_broadcast_frames_good_u *)&mib_info->TxBroad);
+	mp_tx_multicast_frames_good_get(dev_id, gmac_id,
+		(union tx_multicast_frames_good_u *)&mib_info->TxMulti);
+	mp_tx_64octets_frames_good_bad_get(dev_id, gmac_id,
+		(union tx_64octets_frames_good_bad_u *)&mib_info->Tx64Byte);
+	mp_tx_65to127octets_frames_good_bad_get(dev_id, gmac_id,
+		(union tx_65to127octets_frames_good_bad_u *)&mib_info->Tx128Byte);
+	mp_tx_128to255octets_frames_good_bad_get(dev_id, gmac_id,
+		(union tx_128to255octets_frames_good_bad_u *)&mib_info->Tx256Byte);
+	mp_tx_256to511octets_frames_good_bad_get(dev_id, gmac_id,
+		(union tx_256to511octets_frames_good_bad_u *)&mib_info->Tx512Byte);
+	mp_tx_512to1023octets_frames_good_bad_get(dev_id, gmac_id,
+		(union tx_512to1023octets_frames_good_bad_u *)&mib_info->Tx1024Byte);
+	mp_tx_1024tomaxoctets_frames_good_bad_get(dev_id, gmac_id,
+		(union tx_1024tomaxoctets_frames_good_bad_u *)&mib_info->TxMaxByte);
+	mp_tx_unicast_frames_good_bad_get(dev_id, gmac_id,
+		(union tx_unicast_frames_good_bad_u *)&mib_info->TxUniCast);
+	mp_tx_underflow_error_frames_get(dev_id, gmac_id,
+		(union tx_underflow_error_frames_u *)&mib_info->TxUnderRun);
+	mp_tx_single_col_good_frames_get(dev_id, gmac_id,
+		(union tx_single_collision_good_frames_u *)&mib_info->TxSingalCol);
+	mp_t_multi_col_good_frames_get(dev_id, gmac_id,
+		(union tx_multiple_collision_good_frames_u *)&mib_info->TxMultiCol);
+	mp_tx_defer_frames_get(dev_id, gmac_id,
+		(union tx_deferred_frames_u *)&mib_info->TxDefer);
+	mp_tx_late_col_frames_get(dev_id, gmac_id,
+		(union tx_late_collision_frames_u *)&mib_info->TxLateCol);
+	mp_tx_excessive_col_frames_get(dev_id, gmac_id,
+		(union tx_excessive_collision_frames_u *)&mib_info->TxExcDefer);
+	mp_tx_octet_count_good_get(dev_id, gmac_id,
+		(union tx_octet_count_good_u *) &mib_info->TxByte_lo);
+	mp_tx_pause_frames_get(dev_id, gmac_id,
+		(union tx_pause_frames_u *)&mib_info->TxPause);
+	mp_tx_osize_frames_good_get(dev_id, gmac_id,
+		(union tx_osize_frames_good_u *)&mib_info->TxOverSize);
+
+	mp_rx_octet_count_good_get(dev_id, gmac_id,
+		(union rx_octet_count_good_u *)&mib_info->RxGoodByte_lo);
+	mp_rx_broadcast_frames_good_get(dev_id, gmac_id,
+		(union rx_broadcast_frames_good_u *)&mib_info->RxBroad);
+	mp_rx_multicast_frames_good_get(dev_id, gmac_id,
+		(union rx_multicast_frames_good_u *)&mib_info->RxMulti);
+	mp_rx_crc_error_frames_get(dev_id, gmac_id,
+		(union rx_crc_error_frames_u *)&mib_info->RxFcsErr);
+	mp_rx_alignment_error_frames_get(dev_id, gmac_id,
+		(union rx_crc_error_frames_u *)&mib_info->RxAllignErr);
+	mp_rx_runt_error_frames_get(dev_id, gmac_id,
+		(union rx_runt_error_frames_u *)&mib_info->RxFragment);
+	mp_rx_jabber_error_frames_get(dev_id, gmac_id,
+		(union rx_jabber_error_frames_u *)&mib_info->RxJumboFcsErr);
+	mp_rx_undersize_frames_good_get(dev_id, gmac_id,
+		(union rx_undersize_frames_good_u *)&mib_info->RxRunt);
+	mp_rx_oversize_frames_good_get(dev_id, gmac_id,
+		(union rx_oversize_frames_good_u *)&mib_info->RxTooLong);
+	mp_rx_64octets_frames_good_bad_get(dev_id, gmac_id,
+		(union rx_64octets_frames_good_bad_u *)&mib_info->Rx64Byte);
+	mp_rx_65to127octets_frames_good_bad_get(dev_id,gmac_id,
+		(union rx_65to127octets_frames_good_bad_u *)&mib_info->Rx128Byte);
+	mp_rx_128to255octets_frames_good_bad_get(dev_id, gmac_id,
+		(union rx_128to255octets_frames_good_bad_u *)&mib_info->Rx256Byte);
+	mp_rx_256to511octets_frames_good_bad_get(dev_id, gmac_id,
+		(union rx_256to511octets_frames_good_bad_u *)&mib_info->Rx512Byte);
+	mp_rx_512to1023octets_frames_good_bad_get(dev_id, gmac_id,
+		(union rx_512to1023octets_frames_good_bad_u *)&mib_info->Rx1024Byte);
+	mp_rx_1024tomaxoctets_frames_good_bad_get(dev_id, gmac_id,
+		(union rx_1024tomaxoctets_frames_good_bad_u *)&mib_info->RxMaxByte);
+	mp_rx_unicast_frames_good_get(dev_id, gmac_id,
+		(union rx_unicast_frames_good_u *)&mib_info->RxUniCast);
+	mp_rx_pause_frames_get(dev_id, gmac_id,
+		(union rx_pause_frames_u *)&mib_info->RxPause);
+	mp_rx_fifo_over_flow_frames_get(dev_id, gmac_id,
+		(union rx_fifo_over_flow_frames_u *)&mib_info->RxOverFlow);
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_mp_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+	fal_mib_info_t * mib_info)
+{
+	a_uint32_t gmac_id = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mib_info);
+	MP_PORT_ID_CHECK(port_id);
+	memset(mib_info, 0, sizeof(fal_mib_info_t));
+
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+	mp_tx_broadcast_frames_good_get(dev_id, gmac_id,
+		(union tx_broadcast_frames_good_u *)&mib_info->TxBroad);
+	mp_tx_multicast_frames_good_get(dev_id, gmac_id,
+		(union tx_multicast_frames_good_u *)&mib_info->TxMulti);
+	mp_tx_64octets_frames_good_bad_get(dev_id, gmac_id,
+		(union tx_64octets_frames_good_bad_u *)&mib_info->Tx64Byte);
+	mp_tx_65to127octets_frames_good_bad_get(dev_id, gmac_id,
+		(union tx_65to127octets_frames_good_bad_u *)&mib_info->Tx128Byte);
+	mp_tx_128to255octets_frames_good_bad_get(dev_id, gmac_id,
+		(union tx_128to255octets_frames_good_bad_u *)&mib_info->Tx256Byte);
+	mp_tx_256to511octets_frames_good_bad_get(dev_id, gmac_id,
+		(union tx_256to511octets_frames_good_bad_u *)&mib_info->Tx512Byte);
+	mp_tx_512to1023octets_frames_good_bad_get(dev_id, gmac_id,
+		(union tx_512to1023octets_frames_good_bad_u *)&mib_info->Tx1024Byte);
+	mp_tx_1024tomaxoctets_frames_good_bad_get(dev_id, gmac_id,
+		(union tx_1024tomaxoctets_frames_good_bad_u *)&mib_info->TxMaxByte);
+	mp_tx_unicast_frames_good_bad_get(dev_id, gmac_id,
+		(union tx_unicast_frames_good_bad_u *)&mib_info->TxUniCast);
+	mp_tx_underflow_error_frames_get(dev_id, gmac_id,
+		(union tx_underflow_error_frames_u *)&mib_info->TxUnderRun);
+	mp_tx_single_col_good_frames_get(dev_id, gmac_id,
+		(union tx_single_collision_good_frames_u *)&mib_info->TxSingalCol);
+	mp_t_multi_col_good_frames_get(dev_id, gmac_id,
+		(union tx_multiple_collision_good_frames_u *)&mib_info->TxMultiCol);
+	mp_tx_defer_frames_get(dev_id, gmac_id,
+		(union tx_deferred_frames_u *)&mib_info->TxDefer);
+	mp_tx_late_col_frames_get(dev_id, gmac_id,
+		(union tx_late_collision_frames_u *)&mib_info->TxLateCol);
+	mp_tx_excessive_col_frames_get(dev_id, gmac_id,
+		(union tx_excessive_collision_frames_u *)&mib_info->TxExcDefer);
+	mp_tx_octet_count_good_get(dev_id, gmac_id,
+		(union tx_octet_count_good_u *) &mib_info->TxByte_lo);
+	mp_tx_pause_frames_get(dev_id, gmac_id,
+		(union tx_pause_frames_u *)&mib_info->TxPause);
+	mp_tx_osize_frames_good_get(dev_id, gmac_id,
+		(union tx_osize_frames_good_u *)&mib_info->TxOverSize);
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_mp_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_mib_info_t * mib_info )
+{
+	a_uint32_t gmac_id = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mib_info);
+	MP_PORT_ID_CHECK(port_id);
+	memset(mib_info, 0, sizeof(fal_mib_info_t));
+
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+	mp_rx_octet_count_good_get(dev_id, gmac_id,
+		(union rx_octet_count_good_u *)&mib_info->RxGoodByte_lo);
+	mp_rx_broadcast_frames_good_get(dev_id, gmac_id,
+		(union rx_broadcast_frames_good_u *)&mib_info->RxBroad);
+	mp_rx_multicast_frames_good_get(dev_id, gmac_id,
+		(union rx_multicast_frames_good_u *)&mib_info->RxMulti);
+	mp_rx_crc_error_frames_get(dev_id, gmac_id,
+		(union rx_crc_error_frames_u *)&mib_info->RxFcsErr);
+	mp_rx_alignment_error_frames_get(dev_id, gmac_id,
+		(union rx_crc_error_frames_u *)&mib_info->RxAllignErr);
+	mp_rx_runt_error_frames_get(dev_id, gmac_id,
+		(union rx_runt_error_frames_u *)&mib_info->RxFragment);
+	mp_rx_jabber_error_frames_get(dev_id, gmac_id,
+		(union rx_jabber_error_frames_u *)&mib_info->RxJumboFcsErr);
+	mp_rx_undersize_frames_good_get(dev_id, gmac_id,
+		(union rx_undersize_frames_good_u *)&mib_info->RxRunt);
+	mp_rx_oversize_frames_good_get(dev_id, gmac_id,
+		(union rx_oversize_frames_good_u *)&mib_info->RxTooLong);
+	mp_rx_64octets_frames_good_bad_get(dev_id, gmac_id,
+		(union rx_64octets_frames_good_bad_u *)&mib_info->Rx64Byte);
+	mp_rx_65to127octets_frames_good_bad_get(dev_id,gmac_id,
+		(union rx_65to127octets_frames_good_bad_u *)&mib_info->Rx128Byte);
+	mp_rx_128to255octets_frames_good_bad_get(dev_id, gmac_id,
+		(union rx_128to255octets_frames_good_bad_u *)&mib_info->Rx256Byte);
+	mp_rx_256to511octets_frames_good_bad_get(dev_id, gmac_id,
+		(union rx_256to511octets_frames_good_bad_u *)&mib_info->Rx512Byte);
+	mp_rx_512to1023octets_frames_good_bad_get(dev_id, gmac_id,
+		(union rx_512to1023octets_frames_good_bad_u *)&mib_info->Rx1024Byte);
+	mp_rx_1024tomaxoctets_frames_good_bad_get(dev_id, gmac_id,
+		(union rx_1024tomaxoctets_frames_good_bad_u *)&mib_info->RxMaxByte);
+	mp_rx_unicast_frames_good_get(dev_id, gmac_id,
+		(union rx_unicast_frames_good_u *)&mib_info->RxUniCast);
+	mp_rx_pause_frames_get(dev_id, gmac_id,
+		(union rx_pause_frames_u *)&mib_info->RxPause);
+	mp_rx_fifo_over_flow_frames_get(dev_id, gmac_id,
+		(union rx_fifo_over_flow_frames_u *)&mib_info->RxOverFlow);
+
+	return SW_OK;
+}
+
+sw_error_t adpt_mp_mib_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	SW_RTN_ON_NULL(p_adpt_api);
+
+	p_adpt_api->adpt_mib_cpukeep_get = adpt_mp_mib_cpukeep_get;
+	p_adpt_api->adpt_mib_cpukeep_set = adpt_mp_mib_cpukeep_set;
+	p_adpt_api->adpt_mib_status_get = adpt_mp_mib_status_get;
+	p_adpt_api->adpt_mib_status_set = adpt_mp_mib_status_set;
+	p_adpt_api->adpt_mib_port_flush_counters = adpt_mp_mib_port_flush_counters;
+	p_adpt_api->adpt_get_mib_info = adpt_mp_get_mib_info;
+	p_adpt_api->adpt_get_tx_mib_info = adpt_mp_get_tx_mib_info;
+	p_adpt_api->adpt_get_rx_mib_info = adpt_mp_get_rx_mib_info;
+
+	return SW_OK;
+}
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/mp/adpt_mp_portctrl.c b/qca-ssdk/src/adpt/mp/adpt_mp_portctrl.c
new file mode 100755
index 0000000..a7fd452
--- /dev/null
+++ b/qca-ssdk/src/adpt/mp/adpt_mp_portctrl.c
@@ -0,0 +1,1348 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "mp_portctrl_reg.h"
+#include "mp_portctrl.h"
+#include "adpt.h"
+#include "adpt_mp.h"
+#include "adpt_mp_portctrl.h"
+#include "adpt_mp_uniphy.h"
+#include "hsl_port_prop.h"
+#include "hsl_phy.h"
+#include "ssdk_dts.h"
+#include "ssdk_clk.h"
+
+static a_uint32_t port_lpi_status[SW_MAX_NR_DEV] = {0};
+
+static sw_error_t
+_adpt_mp_gcc_mac_clock_set(a_uint32_t dev_id,
+	a_uint32_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = 0;
+
+	qca_gcc_mac_port_clock_set(dev_id, port_id, enable);
+
+	return rv;
+}
+
+static a_bool_t
+_adpt_mp_port_phy_connected (a_uint32_t dev_id, fal_port_t port_id)
+{
+	a_bool_t force_port = 0;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	/* force port which connect s17c or other device chip*/
+	force_port = ssdk_port_feature_get(dev_id, port_id, PHY_F_FORCE);
+	if (force_port == A_TRUE) {
+		SSDK_DEBUG("port_id %d is a force port!\n", port_id);
+		return A_FALSE;
+	} else {
+		return A_TRUE;
+	}
+}
+
+static sw_error_t
+_adpt_mp_port_gcc_speed_clock_set(
+	a_uint32_t dev_id,
+	a_uint32_t port_id,
+	fal_port_speed_t phy_speed)
+{
+	sw_error_t rv = 0;
+
+	switch (phy_speed) {
+		case FAL_SPEED_10:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, SGMII_SPEED_10M_CLK);
+			break;
+		case FAL_SPEED_100:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, SGMII_SPEED_100M_CLK);
+			break;
+		case FAL_SPEED_1000:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, SGMII_SPEED_1000M_CLK);
+			break;
+		case FAL_SPEED_2500:
+			ssdk_port_speed_clock_set(dev_id,
+					port_id, SGMII_PLUS_SPEED_2500M_CLK);
+			break;
+		default:
+			break;
+               }
+
+	return rv;
+}
+
+static sw_error_t
+adpt_mp_port_reset_set(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_addr;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (port_id == SSDK_PHYSICAL_PORT1) {
+		/*internal gephy reset*/
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get(dev_id,
+				port_id));
+		if (NULL == phy_drv->phy_function_reset)
+			return SW_NOT_SUPPORTED;
+		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_addr);
+		SW_RTN_ON_ERROR (rv);
+		rv = phy_drv->phy_function_reset(dev_id, phy_addr, PHY_FIFO_RESET);
+		SW_RTN_ON_ERROR (rv);
+	} else if (port_id == SSDK_PHYSICAL_PORT2) {
+		rv = adpt_mp_uniphy_adapter_port_reset(dev_id, port_id);
+	} else {
+		return SW_NOT_SUPPORTED;
+	}
+
+	return rv;
+}
+
+static sw_error_t
+adpt_mp_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mac_configuration_u configuration;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+
+	memset(&configuration, 0, sizeof(configuration));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration);
+	SW_RTN_ON_ERROR(rv);
+
+	configuration.bf.tx_enable = enable;
+	rv = mp_mac_configuration_set(dev_id, gmac_id, &configuration);
+
+	return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+adpt_mp_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mac_configuration_u configuration;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	memset(&configuration, 0, sizeof(configuration));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration);
+	SW_RTN_ON_ERROR(rv);
+
+	*enable = configuration.bf.tx_enable;
+
+	return rv;
+}
+#endif
+
+static sw_error_t
+adpt_mp_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mac_configuration_u configuration;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+
+	memset(&configuration, 0, sizeof(configuration));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration);
+	SW_RTN_ON_ERROR(rv);
+
+	configuration.bf.rx_enable = enable;
+	rv = mp_mac_configuration_set(dev_id, gmac_id, &configuration);
+
+	return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+adpt_mp_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mac_configuration_u configuration;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	memset(&configuration, 0, sizeof(configuration));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration);
+	SW_RTN_ON_ERROR(rv);
+
+	*enable = configuration.bf.rx_enable;
+
+	return rv;
+}
+#endif
+
+static sw_error_t
+adpt_mp_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id,
+	a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mac_flow_ctrl_u mac_flow_ctrl;
+	struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id);
+	union mac_operation_mode_ctrl_u mac_operation_mode_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+	ADPT_NULL_POINT_CHECK(priv);
+
+	memset(&mac_flow_ctrl, 0, sizeof(mac_flow_ctrl));
+	memset(&mac_operation_mode_ctrl, 0, sizeof(mac_operation_mode_ctrl));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_flowctrl_get(dev_id, gmac_id, &mac_flow_ctrl);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = mp_mac_operation_mode_ctrl_get(dev_id, gmac_id,
+			&mac_operation_mode_ctrl);
+	SW_RTN_ON_ERROR(rv);
+
+	if (A_TRUE == enable) {
+		mac_flow_ctrl.bf.flowctrl_tx_enable = 1;
+		mac_flow_ctrl.bf.pause_time = GMAC_PAUSE_TIME;
+		mac_flow_ctrl.bf.disable_zero_quanta_pause =
+			GMAC_PAUSE_ZERO_QUANTA_ENABLE;
+		mac_operation_mode_ctrl.bf.enable_hw_flowctrl =
+			GMAC_HW_FLOWCTRL_ENABLE;
+		mac_operation_mode_ctrl.bf.disable_flushing_receiving_frame =
+			GMAC_FLUSH_RECEIVED_FRAMES_DISABLE;
+		/*activate flowctrl when 6KB FIFO is available*/
+		mac_operation_mode_ctrl.val &= ~(GMAC_ACTIVATE_FLOWCTRL_MASK);
+		mac_operation_mode_ctrl.val |= GMAC_ACTIVATE_FLOWCTRL_WITH_6KB;
+		/*dactivate flowctrl when 7KB FIFO is available*/
+		mac_operation_mode_ctrl.val &= ~(GMAC_DACTIVATE_FLOWCTRL_MASK);
+		mac_operation_mode_ctrl.val |= GMAC_DACTIVATE_FLOWCTRL_WITH_7KB;
+	} else {
+		mac_flow_ctrl.bf.flowctrl_tx_enable = 0;
+		mac_operation_mode_ctrl.bf.enable_hw_flowctrl =
+			GMAC_HW_FLOWCTRL_DISABLE;
+	}
+
+	rv = mp_mac_operation_mode_ctrl_set(dev_id, gmac_id,
+			&mac_operation_mode_ctrl);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = mp_mac_flowctrl_set(dev_id, gmac_id, &mac_flow_ctrl);
+	SW_RTN_ON_ERROR(rv);
+
+	priv->port_old_tx_flowctrl[port_id - 1] = enable;
+
+	return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+adpt_mp_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id,
+	a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mac_flow_ctrl_u mac_flow_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	memset(&mac_flow_ctrl, 0, sizeof(mac_flow_ctrl));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_flowctrl_get(dev_id, gmac_id, &mac_flow_ctrl);
+	SW_RTN_ON_ERROR(rv);
+
+	if (mac_flow_ctrl.bf.flowctrl_tx_enable) {
+		*enable = A_TRUE;
+	} else {
+		*enable = A_FALSE;
+	}
+
+	return rv;
+}
+#endif
+
+static sw_error_t
+adpt_mp_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id,
+	a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mac_flow_ctrl_u mac_flow_ctrl;
+	struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id);
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+	ADPT_NULL_POINT_CHECK(priv);
+
+	memset(&mac_flow_ctrl, 0, sizeof(mac_flow_ctrl));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_flowctrl_get(dev_id, gmac_id, &mac_flow_ctrl);
+	SW_RTN_ON_ERROR(rv);
+
+	if (A_TRUE == enable) {
+		mac_flow_ctrl.bf.flowctrl_rx_enable = 1;
+	} else {
+		mac_flow_ctrl.bf.flowctrl_rx_enable = 0;
+	}
+
+	rv = mp_mac_flowctrl_set(dev_id, gmac_id, &mac_flow_ctrl);
+
+	priv->port_old_rx_flowctrl[port_id - 1] = enable;
+
+	return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+adpt_mp_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id,
+	a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mac_flow_ctrl_u mac_flow_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	memset(&mac_flow_ctrl, 0, sizeof(mac_flow_ctrl));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_flowctrl_get(dev_id, gmac_id, &mac_flow_ctrl);
+	SW_RTN_ON_ERROR(rv);
+
+	if (mac_flow_ctrl.bf.flowctrl_rx_enable) {
+		*enable = A_TRUE;
+	} else {
+		*enable = A_FALSE;
+	}
+
+	return rv;
+}
+#endif
+
+static sw_error_t
+adpt_mp_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id,
+	a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id);
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+	ADPT_NULL_POINT_CHECK(priv);
+
+	rv = adpt_mp_port_txfc_status_set(dev_id, port_id, enable);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = adpt_mp_port_rxfc_status_set(dev_id, port_id, enable);
+	SW_RTN_ON_ERROR(rv);
+
+	priv->port_old_tx_flowctrl[port_id - 1] = enable;
+	priv->port_old_rx_flowctrl[port_id - 1] = enable;
+
+	return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+adpt_mp_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+	a_bool_t * enable)
+{
+	sw_error_t rv = SW_OK;
+	a_bool_t txfc_enable, rxfc_enable;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	rv = adpt_mp_port_txfc_status_get(dev_id, port_id,  &txfc_enable);
+	SW_RTN_ON_ERROR(rv);
+	rv = adpt_mp_port_rxfc_status_get(dev_id, port_id,  &rxfc_enable);
+	SW_RTN_ON_ERROR(rv);
+
+	*enable = txfc_enable & rxfc_enable;
+
+	return rv;
+}
+#endif
+
+static sw_error_t
+adpt_mp_port_flowctrl_forcemode_set(a_uint32_t dev_id,
+	fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id);
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+	ADPT_NULL_POINT_CHECK(priv);
+
+	priv->port_tx_flowctrl_forcemode[port_id - 1] = enable;
+	priv->port_rx_flowctrl_forcemode[port_id - 1] = enable;
+
+	return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+adpt_mp_port_flowctrl_forcemode_get(a_uint32_t dev_id,
+	fal_port_t port_id, a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id);
+
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+	ADPT_NULL_POINT_CHECK(enable);
+	ADPT_NULL_POINT_CHECK(priv);
+
+	*enable = (priv->port_tx_flowctrl_forcemode[port_id - 1] &
+		priv->port_rx_flowctrl_forcemode[port_id - 1]);
+
+	return rv;
+}
+#endif
+
+static sw_error_t
+adpt_mp_port_mac_status_get(a_uint32_t dev_id, a_uint32_t port_id,
+	struct port_phy_status *port_mac_status)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mac_configuration_u configuration;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+	ADPT_NULL_POINT_CHECK(port_mac_status);
+
+	memset(&configuration, 0, sizeof(configuration));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration);
+	SW_RTN_ON_ERROR(rv);
+
+	if (configuration.bf.port_select == GMAC_SPEED_1000M) {
+		port_mac_status->speed = FAL_SPEED_1000;
+	} else {
+		if (configuration.bf.mii_speed == GMAC_SPEED_100M) {
+			port_mac_status->speed = FAL_SPEED_100;
+		} else {
+			port_mac_status->speed = FAL_SPEED_10;
+		}
+	}
+
+	if (configuration.bf.duplex == GMAC_FULL_DUPLEX) {
+		port_mac_status->duplex = FAL_FULL_DUPLEX;
+	} else {
+		port_mac_status->duplex = FAL_HALF_DUPLEX;
+	}
+
+	return rv;
+
+}
+
+static sw_error_t
+adpt_mp_port_mac_speed_set(a_uint32_t dev_id, a_uint32_t port_id,
+	fal_port_speed_t speed)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mac_configuration_u configuration;
+	a_bool_t force_port;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+
+	memset(&configuration, 0, sizeof(configuration));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration);
+	SW_RTN_ON_ERROR(rv);
+
+	if ((FAL_SPEED_1000 == speed) || (FAL_SPEED_2500 == speed)) {
+		 configuration.bf.port_select = GMAC_SPEED_1000M;
+	} else if (FAL_SPEED_100 == speed) {
+		configuration.bf.port_select = (~GMAC_SPEED_1000M) & 0x1;
+		configuration.bf.mii_speed = GMAC_SPEED_100M;
+	} else if (FAL_SPEED_10== speed) {
+		configuration.bf.port_select = (~GMAC_SPEED_1000M) & 0x1;
+		configuration.bf.mii_speed = GMAC_SPEED_10M;
+	}
+
+	rv = mp_mac_configuration_set(dev_id, gmac_id, &configuration);
+	SW_RTN_ON_ERROR(rv);
+
+	force_port = ssdk_port_feature_get(dev_id, port_id, PHY_F_FORCE);
+	/* enable force port configuration */
+	if (force_port == A_TRUE) {
+		rv = _adpt_mp_port_gcc_speed_clock_set(dev_id,
+			port_id, speed);
+		SW_RTN_ON_ERROR(rv);
+		rv = adpt_mp_gcc_uniphy_port_clock_set(dev_id,
+			port_id, A_TRUE);
+		SW_RTN_ON_ERROR(rv);
+		rv = _adpt_mp_gcc_mac_clock_set(dev_id,
+			port_id, A_TRUE);
+		SW_RTN_ON_ERROR(rv);
+		rv = adpt_mp_port_reset_set(dev_id, port_id);
+		SW_RTN_ON_ERROR(rv);
+	}
+	return rv;
+
+}
+
+static sw_error_t
+adpt_mp_port_mac_duplex_set(a_uint32_t dev_id, a_uint32_t port_id,
+	fal_port_duplex_t duplex)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mac_configuration_u configuration;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+
+	memset(&configuration, 0, sizeof(configuration));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration);
+	SW_RTN_ON_ERROR(rv);
+
+	if (FAL_FULL_DUPLEX == duplex) {
+		configuration.bf.duplex = GMAC_FULL_DUPLEX;
+	} else {
+		configuration.bf.duplex = GMAC_HALF_DUPLEX;
+	}
+
+	rv = mp_mac_configuration_set(dev_id, gmac_id, &configuration);
+
+	return rv;
+}
+
+static sw_error_t
+adpt_mp_port_promisc_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+	a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mac_frame_filter_u mac_frame_filter;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+
+	memset(&mac_frame_filter, 0, sizeof(mac_frame_filter));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_frame_filter_get(dev_id, gmac_id, &mac_frame_filter);
+	SW_RTN_ON_ERROR(rv);
+
+	mac_frame_filter.bf.promiscuous_mode = enable;
+
+	rv = mp_mac_frame_filter_set(dev_id, gmac_id, &mac_frame_filter);
+
+	return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+adpt_mp_port_promisc_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+	a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mac_frame_filter_u mac_frame_filter;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	memset(&mac_frame_filter, 0, sizeof(mac_frame_filter));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_frame_filter_get(dev_id, gmac_id, &mac_frame_filter);
+	SW_RTN_ON_ERROR(rv);
+
+	*enable = mac_frame_filter.bf.promiscuous_mode;
+
+	return rv;
+}
+#endif
+
+static sw_error_t
+adpt_mp_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
+	a_uint32_t max_frame)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mac_max_frame_ctrl_u mac_max_frame_ctrl;
+	union mac_configuration_u configuration;
+	union mac_operation_mode_ctrl_u mac_operation_mode_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+
+	if (max_frame > PORT_MAX_FRAME_SIZE - 8) {
+		return SW_OUT_OF_RANGE;
+	}
+
+	memset(&configuration, 0, sizeof(configuration));
+	memset(&mac_max_frame_ctrl, 0, sizeof(mac_max_frame_ctrl));
+	memset(&mac_operation_mode_ctrl, 0, sizeof(mac_operation_mode_ctrl));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_max_frame_ctrl_get(dev_id, gmac_id, &mac_max_frame_ctrl);
+	SW_RTN_ON_ERROR(rv);
+	rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration);
+	SW_RTN_ON_ERROR(rv);
+
+	configuration.bf.jabber_disable = GMAC_JD_ENABLE;
+	configuration.bf.watchdog_disable = GMAC_WD_DISABLE;
+	configuration.bf.jumbo_frame_enable = GMAC_JUMBO_FRAME_ENABLE;
+	configuration.bf.frame_burst_enable = GMAC_FRAME_BURST_ENABLE;
+	rv = mp_mac_configuration_set(dev_id, gmac_id, &configuration);
+	SW_RTN_ON_ERROR(rv);
+
+	mac_max_frame_ctrl.bf.max_frame_ctrl_enable = GMAC_MAX_FRAME_CTRL_ENABLE;
+	/* default max_frame 1518 byte doesn't include vlan tag */
+	mac_max_frame_ctrl.bf.max_frame_ctrl = max_frame + 8;
+	rv = mp_mac_max_frame_ctrl_set(dev_id, gmac_id, &mac_max_frame_ctrl);
+
+	rv = mp_mac_operation_mode_ctrl_get(dev_id, gmac_id,
+			&mac_operation_mode_ctrl);
+	mac_operation_mode_ctrl.bf.receive_store_and_foward =
+		GMAC_RX_STORE_FORWAD_ENABLE;
+	mac_operation_mode_ctrl.bf.transmit_store_and_foward =
+		GMAC_TX_STORE_FORWAD_ENABLE;
+	mac_operation_mode_ctrl.bf.forward_error_frame =
+		GMAC_FORWARD_ERROR_FRAME_DISABLE;
+	mac_operation_mode_ctrl.bf.drop_gaint_frame =
+		GMAC_DROP_GAINT_FRAME_DISABLE;
+	rv = mp_mac_operation_mode_ctrl_set(dev_id, gmac_id,
+			&mac_operation_mode_ctrl);
+
+	return rv;
+}
+
+static sw_error_t
+adpt_mp_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
+	a_uint32_t *max_frame)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t gmac_id = 0;
+	union mac_max_frame_ctrl_u mac_max_frame_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+	ADPT_NULL_POINT_CHECK(max_frame);
+
+	memset(&mac_max_frame_ctrl, 0, sizeof(mac_max_frame_ctrl));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_max_frame_ctrl_get(dev_id, gmac_id, &mac_max_frame_ctrl);
+	SW_RTN_ON_ERROR(rv);
+
+	*max_frame = mac_max_frame_ctrl.bf.max_frame_ctrl;
+
+	return rv;
+}
+
+static sw_error_t
+adpt_mp_port_mac_eee_enable_set(a_uint32_t dev_id, fal_port_t port_id,
+	a_bool_t enable)
+{
+	sw_error_t rv = 0;
+	a_uint32_t gmac_id = 0;
+	union mac_lpi_ctrl_status_u mac_lpi_ctrl_status;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+
+	memset(&mac_lpi_ctrl_status, 0, sizeof(mac_lpi_ctrl_status));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_lpi_ctrl_status_get(dev_id, gmac_id, &mac_lpi_ctrl_status);
+	SW_RTN_ON_ERROR(rv);
+	mac_lpi_ctrl_status.bf.lpi_enable = enable;
+
+	rv = mp_mac_lpi_ctrl_status_set(dev_id, gmac_id, &mac_lpi_ctrl_status);
+
+	return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+adpt_mp_port_mac_eee_enable_get(a_uint32_t dev_id, fal_port_t port_id,
+	a_bool_t *enable)
+{
+	sw_error_t rv = 0;
+	a_uint32_t gmac_id = 0;
+	union mac_lpi_ctrl_status_u mac_lpi_ctrl_status;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+	ADPT_NULL_POINT_CHECK(enable);
+
+	memset(&mac_lpi_ctrl_status, 0, sizeof(mac_lpi_ctrl_status));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	rv = mp_mac_lpi_ctrl_status_get(dev_id, gmac_id, &mac_lpi_ctrl_status);
+	SW_RTN_ON_ERROR(rv);
+
+	*enable = mac_lpi_ctrl_status.bf.lpi_enable;
+
+	return rv;
+
+}
+#endif
+
+static sw_error_t
+adpt_mp_port_interface_eee_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
+	fal_port_eee_cfg_t *port_eee_cfg)
+{
+	sw_error_t rv = 0;
+	union mac_lpi_timer_ctrl_u mac_lpi_timer_ctrl;
+	union mac_lpi_ctrl_status_u mac_lpi_ctrl_status;
+
+	a_uint32_t phy_addr = 0, gmac_id = 0;
+	a_uint32_t adv;
+	hsl_phy_ops_t *phy_drv;
+	struct qca_phy_priv *priv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+
+	memset(&mac_lpi_timer_ctrl, 0, sizeof(mac_lpi_timer_ctrl));
+	memset(&mac_lpi_ctrl_status, 0, sizeof(mac_lpi_ctrl_status));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	priv = ssdk_phy_priv_data_get(dev_id);
+	SW_RTN_ON_NULL(priv);
+
+	if (port_eee_cfg->enable) {
+		adv = port_eee_cfg->advertisement;
+	} else {
+		adv = 0;
+	}
+
+	if (port_eee_cfg->lpi_tx_enable) {
+		port_lpi_status[dev_id] |= BIT(port_id-1);
+	} else {
+		port_lpi_status[dev_id] &= ~BIT(port_id-1);
+	}
+
+	SW_RTN_ON_NULL(phy_drv = hsl_phy_api_ops_get(dev_id, port_id));
+	if (NULL == phy_drv->phy_eee_adv_set) {
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_addr);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_eee_adv_set(dev_id, phy_addr, adv);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = mp_mac_lpi_timer_ctrl_get(dev_id, gmac_id, &mac_lpi_timer_ctrl);
+	SW_RTN_ON_ERROR (rv);
+	mac_lpi_timer_ctrl.bf.lpi_tw_timer = port_eee_cfg->lpi_wakeup_timer;
+	rv = mp_mac_lpi_timer_ctrl_set(dev_id, gmac_id, &mac_lpi_timer_ctrl);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = mp_mac_lpi_ctrl_status_get(dev_id, gmac_id, &mac_lpi_ctrl_status);
+	SW_RTN_ON_ERROR (rv);
+	mac_lpi_ctrl_status.bf.lpi_tx_auto_enable = GMAC_LPI_AUTO_MODE;
+	mac_lpi_ctrl_status.bf.link_status = GMAC_LPI_LINK_UP;
+	mac_lpi_ctrl_status.bf.lpi_enable = port_eee_cfg->lpi_tx_enable;
+	rv = mp_mac_lpi_ctrl_status_set(dev_id, gmac_id, &mac_lpi_ctrl_status);
+	SW_RTN_ON_ERROR (rv);
+
+	if (port_lpi_status[dev_id] & PORT_LPI_ENABLE_STATUS) {
+		if (!(port_lpi_status[dev_id] & PORT_LPI_TASK_RUNNING)) {
+			if (!(port_lpi_status[dev_id] & PORT_LPI_TASK_START)) {
+				qca_mac_sw_sync_work_start(priv);
+				port_lpi_status[dev_id] |= PORT_LPI_TASK_START;
+			} else {
+				qca_mac_sw_sync_work_resume(priv);
+			}
+			port_lpi_status[dev_id] |= PORT_LPI_TASK_RUNNING;
+		}
+	} else {
+		qca_mac_sw_sync_work_stop(priv);
+		port_lpi_status[dev_id] &= ~PORT_LPI_TASK_RUNNING;
+	}
+
+	return rv;
+}
+static sw_error_t
+adpt_mp_port_interface_eee_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
+	fal_port_eee_cfg_t *port_eee_cfg)
+{
+	sw_error_t rv = 0;
+	union mac_lpi_timer_ctrl_u mac_lpi_timer_ctrl;
+	union mac_lpi_ctrl_status_u mac_lpi_ctrl_status;
+	a_uint32_t phy_addr = 0, gmac_id = 0;
+	a_uint32_t adv, lp_adv, cap, status;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	MP_PORT_ID_CHECK(port_id);
+	ADPT_NULL_POINT_CHECK(port_eee_cfg);
+
+	memset(&mac_lpi_timer_ctrl, 0, sizeof(mac_lpi_timer_ctrl));
+	memset(&mac_lpi_ctrl_status, 0, sizeof(mac_lpi_ctrl_status));
+	memset(port_eee_cfg, 0, sizeof(*port_eee_cfg));
+	gmac_id = MP_PORT_TO_GMAC_ID(port_id);
+
+	SW_RTN_ON_NULL(phy_drv =hsl_phy_api_ops_get (dev_id, port_id));
+	if ((NULL == phy_drv->phy_eee_adv_get) ||
+		(NULL == phy_drv->phy_eee_partner_adv_get) ||
+		(NULL == phy_drv->phy_eee_cap_get) ||
+		(NULL == phy_drv->phy_eee_status_get)) {
+		return SW_NOT_SUPPORTED;
+	}
+	rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_addr);
+	SW_RTN_ON_ERROR (rv);
+	rv = phy_drv->phy_eee_adv_get(dev_id, phy_addr, &adv);
+	SW_RTN_ON_ERROR (rv);
+	port_eee_cfg->advertisement = adv;
+	rv = phy_drv->phy_eee_partner_adv_get(dev_id, phy_addr, &lp_adv);
+	SW_RTN_ON_ERROR (rv);
+	port_eee_cfg->link_partner_advertisement = lp_adv;
+	rv = phy_drv->phy_eee_cap_get(dev_id, phy_addr, &cap);
+	SW_RTN_ON_ERROR (rv);
+	port_eee_cfg->capability = cap;
+	rv = phy_drv->phy_eee_status_get(dev_id, phy_addr, &status);
+	SW_RTN_ON_ERROR (rv);
+	port_eee_cfg->eee_status = status;
+
+	if (port_eee_cfg->advertisement) {
+		port_eee_cfg->enable = A_TRUE;
+	} else {
+		port_eee_cfg->enable = A_FALSE;
+	}
+	rv = mp_mac_lpi_ctrl_status_get(dev_id, gmac_id, &mac_lpi_ctrl_status);
+	SW_RTN_ON_ERROR (rv);
+	port_eee_cfg->lpi_tx_enable = mac_lpi_ctrl_status.bf.lpi_enable;
+
+	rv = mp_mac_lpi_timer_ctrl_get(dev_id, gmac_id, &mac_lpi_timer_ctrl);
+	SW_RTN_ON_ERROR (rv);
+	port_eee_cfg->lpi_wakeup_timer = mac_lpi_timer_ctrl.bf.lpi_tw_timer;
+
+	return rv;
+}
+
+static sw_error_t
+adpt_mp_port_interface_mode_status_get(a_uint32_t dev_id,
+	a_uint32_t port_id, fal_port_interface_mode_t * mode)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(mode);
+
+	SW_RTN_ON_NULL(phy_drv = hsl_phy_api_ops_get(dev_id, port_id));
+	SW_RTN_ON_NULL(phy_drv->phy_interface_mode_status_get);
+
+	rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_interface_mode_status_get(dev_id, phy_id,mode);
+
+	return rv;
+}
+
+static sw_error_t
+adpt_mp_port_interface_mode_switch(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	sw_error_t rv = SW_OK;
+	fal_port_interface_mode_t port_mode_new = PORT_INTERFACE_MODE_MAX;
+	a_uint32_t uniphy_mode_old = PORT_WRAPPER_MAX;
+	a_uint32_t uniphy_mode_new = PORT_WRAPPER_MAX;
+	a_bool_t force_port;
+
+	force_port = ssdk_port_feature_get(dev_id, port_id, PHY_F_FORCE);
+	if ((port_id == SSDK_PHYSICAL_PORT1) || (force_port == A_TRUE)) {
+		return SW_OK;
+	}
+	rv = adpt_mp_port_interface_mode_status_get(dev_id,
+		port_id, &port_mode_new);
+	SW_RTN_ON_ERROR(rv);
+
+	if (port_mode_new == PHY_SGMII_BASET) {
+		uniphy_mode_new = PORT_WRAPPER_SGMII_CHANNEL0;
+	} else if (port_mode_new == PORT_SGMII_PLUS) {
+		uniphy_mode_new = PORT_WRAPPER_SGMII_PLUS;
+	} else {
+		return SW_NOT_SUPPORTED;
+	}
+	uniphy_mode_old = ssdk_dt_global_get_mac_mode(dev_id,
+		SSDK_UNIPHY_INSTANCE0);
+	if (uniphy_mode_new != uniphy_mode_old) {
+		rv = adpt_mp_uniphy_mode_configure(dev_id,
+			SSDK_UNIPHY_INSTANCE0, uniphy_mode_new);
+		SW_RTN_ON_ERROR(rv);
+		ssdk_dt_global_set_mac_mode(dev_id,
+			SSDK_UNIPHY_INSTANCE0, uniphy_mode_new);
+	}
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_mp_port_phy_status_get(a_uint32_t dev_id, a_uint32_t port_id,
+	struct port_phy_status *phy_status)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_addr;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(phy_status);
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	SW_RTN_ON_NULL (phy_drv->phy_get_status);
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_addr);
+	SW_RTN_ON_ERROR (rv);
+	rv = phy_drv->phy_get_status (dev_id, phy_addr, phy_status);
+	SW_RTN_ON_ERROR (rv);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_mp_port_link_down_update(struct qca_phy_priv *priv,
+	a_uint32_t port_id)
+{
+	sw_error_t rv = 0;
+
+	/* disable rx mac, gcc uniphy port and gcc mac port status */
+	rv = adpt_mp_port_rxmac_status_set(priv->device_id, port_id, A_FALSE);
+	SW_RTN_ON_ERROR (rv);
+	rv = adpt_mp_gcc_uniphy_port_clock_set(priv->device_id, port_id, A_FALSE);
+	SW_RTN_ON_ERROR (rv);
+	_adpt_mp_gcc_mac_clock_set(priv->device_id, port_id, A_FALSE);
+	SW_RTN_ON_ERROR (rv);
+
+	/* switch interface mode if necessary under link down*/
+	rv = adpt_mp_port_interface_mode_switch(priv->device_id, port_id);
+	SW_RTN_ON_ERROR (rv);
+	SSDK_DEBUG("MP port %d interface mode switch under link down!\n",
+			port_id);
+	return rv;
+}
+
+static a_bool_t
+_adpt_mp_port_status_change(struct qca_phy_priv *priv, a_uint32_t port_id,
+	struct port_phy_status phy_status)
+{
+	if ((a_uint32_t)phy_status.speed != priv->port_old_speed[port_id - 1])
+		return A_TRUE;
+	if ((a_uint32_t)phy_status.duplex != priv->port_old_duplex[port_id - 1])
+		return A_TRUE;
+	if (phy_status.tx_flowctrl != priv->port_old_tx_flowctrl[port_id - 1])
+		return A_TRUE;
+	if (phy_status.rx_flowctrl != priv->port_old_rx_flowctrl[port_id - 1])
+		return A_TRUE;
+	return A_FALSE;
+}
+
+sw_error_t
+adpt_mp_port_link_up_change_update(struct qca_phy_priv *priv,
+	a_uint32_t port_id, struct port_phy_status phy_status)
+{
+	sw_error_t rv = 0;
+
+	if ((a_uint32_t)phy_status.speed !=
+		priv->port_old_speed[port_id - 1]) {
+
+		/* configure gcc speed clock frequency */
+		rv = _adpt_mp_port_gcc_speed_clock_set(priv->device_id,
+			port_id, phy_status.speed);
+		SW_RTN_ON_ERROR (rv);
+
+		/* config mac speed */
+		rv = adpt_mp_port_mac_speed_set(priv->device_id,
+			port_id, phy_status.speed);
+		SW_RTN_ON_ERROR (rv);
+
+		priv->port_old_speed[port_id - 1] =
+			(a_uint32_t)phy_status.speed;
+
+		SSDK_DEBUG("Port %d up and speed is %d\n", port_id,
+			priv->port_old_speed[port_id - 1]);
+	}
+	/* link up duplex change configuration */
+	if ((a_uint32_t)phy_status.duplex !=
+		priv->port_old_duplex[port_id - 1]) {
+
+		rv = adpt_mp_port_mac_duplex_set(priv->device_id,
+			port_id, phy_status.duplex);
+
+		priv->port_old_duplex[port_id - 1] =
+			(a_uint32_t)phy_status.duplex;
+		SW_RTN_ON_ERROR (rv);
+
+		SSDK_DEBUG("Port %d up and duplex is %d\n", port_id,
+			priv->port_old_duplex[port_id - 1]);
+	}
+	/* tx flowctrl configuration*/
+	if (priv->port_tx_flowctrl_forcemode[port_id - 1] != A_TRUE) {
+		if (phy_status.duplex == FAL_HALF_DUPLEX) {
+			phy_status.tx_flowctrl = A_TRUE;
+		}
+		if (phy_status.tx_flowctrl !=
+			priv->port_old_tx_flowctrl[port_id - 1]) {
+			rv = adpt_mp_port_txfc_status_set(priv->device_id,
+				port_id, phy_status.tx_flowctrl);
+			SW_RTN_ON_ERROR (rv);
+			priv->port_old_tx_flowctrl[port_id - 1] =
+				phy_status.tx_flowctrl;
+
+			SSDK_DEBUG("Port %d up and tx flowctrl is %d\n",
+				port_id,
+				priv->port_old_tx_flowctrl[port_id - 1]);
+		}
+	}
+	/*rx flowctrl configuration*/
+	if (priv->port_rx_flowctrl_forcemode[port_id - 1] != A_TRUE) {
+		if (phy_status.duplex == FAL_HALF_DUPLEX) {
+			phy_status.rx_flowctrl = A_TRUE;
+		}
+		if (phy_status.rx_flowctrl !=
+			priv->port_old_rx_flowctrl[port_id - 1]) {
+			rv = adpt_mp_port_rxfc_status_set(priv->device_id,
+				port_id, phy_status.rx_flowctrl);
+			SW_RTN_ON_ERROR (rv);
+			priv->port_old_rx_flowctrl[port_id - 1] =
+				phy_status.rx_flowctrl;
+
+			SSDK_DEBUG("Port %d up and rx flowctrl is %d\n",
+				port_id,
+				priv->port_old_rx_flowctrl[port_id-1]);
+		}
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_mp_port_link_up_update(struct qca_phy_priv *priv,
+	a_uint32_t port_id, struct port_phy_status phy_status)
+{
+	sw_error_t rv = 0;
+	a_bool_t change;
+
+	/* port phy status change check*/
+	change = _adpt_mp_port_status_change(priv, port_id,
+			phy_status);
+
+	rv = adpt_mp_port_txmac_status_set(priv->device_id, port_id,
+				A_FALSE);
+	SW_RTN_ON_ERROR (rv);
+
+	/* switch interface mode if necessary under link up */
+	rv = adpt_mp_port_interface_mode_switch(priv->device_id, port_id);
+	SW_RTN_ON_ERROR (rv);
+	SSDK_DEBUG("MP port %d interface mode switch under link up!\n",
+			port_id);
+	/* link up status change*/
+	if (change == A_TRUE) {
+		rv = adpt_mp_port_link_up_change_update(priv,
+			port_id, phy_status);
+		SW_RTN_ON_ERROR (rv);
+	}
+
+	rv = adpt_mp_gcc_uniphy_port_clock_set(priv->device_id,
+			port_id, A_TRUE);
+	SW_RTN_ON_ERROR (rv);
+	rv =_adpt_mp_gcc_mac_clock_set(priv->device_id,
+			port_id, A_TRUE);
+	SW_RTN_ON_ERROR (rv);
+
+	msleep(50);
+
+	rv = adpt_mp_port_reset_set(priv->device_id, port_id);
+	SW_RTN_ON_ERROR (rv);
+	rv = adpt_mp_port_txmac_status_set(priv->device_id,
+			port_id, A_TRUE);
+	SW_RTN_ON_ERROR (rv);
+	rv = adpt_mp_port_rxmac_status_set(priv->device_id,
+		port_id, A_TRUE);
+	SW_RTN_ON_ERROR (rv);
+
+	return rv;
+}
+
+sw_error_t
+adpt_mp_port_netdev_change_notify(struct qca_phy_priv *priv,
+	a_uint32_t port_id)
+{
+	sw_error_t rv = 0;
+	struct port_phy_status phy_status = {0};
+	a_uint32_t portbmp[SW_MAX_NR_DEV] = {0};
+
+	portbmp[priv->device_id] = qca_ssdk_port_bmp_get(priv->device_id);
+
+	if(!(portbmp[priv->device_id] & (0x1 << port_id))) {
+		SSDK_ERROR("netdev change notify with incorrect port %d\n",
+			port_id);
+		return SW_BAD_VALUE;
+	}
+
+	rv = _adpt_mp_port_phy_status_get(priv->device_id, port_id,
+		&phy_status);
+	if (rv != SW_OK) {
+		SSDK_ERROR("failed to get port %d status return value is %d\n",
+			port_id, rv);
+		return rv;
+	}
+	/* link status from up to down*/
+	if ((phy_status.link_status == PORT_LINK_DOWN) &&
+		(priv->port_old_link[port_id - 1] == PORT_LINK_UP)) {
+		SSDK_DEBUG("MP port %d change to link down status\n", port_id);
+		/* link down configuration*/
+		rv = _adpt_mp_port_link_down_update(priv, port_id);
+		SW_RTN_ON_ERROR (rv);
+		priv->port_old_link[port_id - 1] = phy_status.link_status ;
+	}
+	/* link status from down to up */
+	if ((phy_status.link_status == PORT_LINK_UP) &&
+		(priv->port_old_link[port_id - 1] == PORT_LINK_DOWN)) {
+		SSDK_DEBUG("Port %d change to link up status\n", port_id);
+		rv = adpt_mp_port_link_up_update(priv, port_id, phy_status);
+		SW_RTN_ON_ERROR (rv);
+		priv->port_old_link[port_id - 1] = phy_status.link_status;
+	}
+	SSDK_DEBUG("MP port %d link is %d speed is %d duplex is %d"
+		" tx_flowctrl is %d rx_flowctrl is %d\n",
+	port_id, priv->port_old_link[port_id - 1],
+	priv->port_old_speed[port_id - 1],
+	priv->port_old_duplex[port_id - 1],
+	priv->port_old_tx_flowctrl[port_id - 1],
+	priv->port_old_rx_flowctrl[port_id - 1]);
+
+	return rv;
+}
+
+static sw_error_t
+adpt_mp_port_lpi_polling_task(struct qca_phy_priv *priv)
+{
+	a_uint32_t port_id;
+	a_uint32_t portbmp[SW_MAX_NR_DEV] = {0};
+	sw_error_t rv = SW_OK;
+
+	portbmp[priv->device_id] = qca_ssdk_port_bmp_get(priv->device_id);
+
+	for (port_id = SSDK_PHYSICAL_PORT1; port_id < SW_MAX_NR_PORT; port_id ++) {
+
+		if(!(portbmp[priv->device_id] & BIT(port_id)))
+			continue;
+		if (port_lpi_status[priv->device_id] & BIT(port_id-1)) {
+			rv = adpt_mp_port_mac_eee_enable_set(priv->device_id,
+				port_id, A_TRUE);
+			SW_RTN_ON_ERROR(rv);
+		}
+	}
+	return SW_OK;
+}
+
+static sw_error_t
+adpt_mp_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+	fal_port_speed_t * pspeed)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+	struct port_phy_status port_mac_status = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(pspeed);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) {
+		return SW_BAD_PARAM;
+	}
+
+	/* for those ports without PHY device should be s17c port */
+	if (A_FALSE == _adpt_mp_port_phy_connected (dev_id, port_id)) {
+		rv = adpt_mp_port_mac_status_get(dev_id, port_id, &port_mac_status);
+		SW_RTN_ON_ERROR (rv);
+		*pspeed= port_mac_status.speed;
+	} else {
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id,
+				port_id));
+		if (NULL == phy_drv->phy_speed_get) {
+			return SW_NOT_SUPPORTED;
+		}
+
+		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR (rv);
+		rv = phy_drv->phy_speed_get (dev_id, phy_id, pspeed);
+		SW_RTN_ON_ERROR (rv);
+	}
+
+	return rv;
+}
+
+static sw_error_t
+adpt_mp_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+	fal_port_duplex_t * pduplex)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+	struct port_phy_status port_mac_status = {0};
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(pduplex);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) {
+		return SW_BAD_PARAM;
+	}
+
+	/* for those ports without PHY device should be s17c port */
+	if (A_FALSE == _adpt_mp_port_phy_connected (dev_id, port_id)) {
+		rv = adpt_mp_port_mac_status_get(dev_id, port_id, &port_mac_status);
+		SW_RTN_ON_ERROR (rv);
+		*pduplex = port_mac_status.duplex;
+	} else {
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id,
+				port_id));
+		if (NULL == phy_drv->phy_duplex_get) {
+			return SW_NOT_SUPPORTED;
+		}
+
+		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR (rv);
+		rv = phy_drv->phy_duplex_get (dev_id, phy_id, pduplex);
+		SW_RTN_ON_ERROR (rv);
+	}
+
+	return rv;
+}
+
+static sw_error_t
+adpt_mp_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id,
+	a_bool_t * status)
+{
+	sw_error_t rv = 0;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_NULL_POINT_CHECK(status);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) {
+		return SW_BAD_PARAM;
+	}
+
+	/* for those ports without PHY device should be s17c port */
+	if (A_FALSE == _adpt_mp_port_phy_connected (dev_id, port_id)) {
+		*status = A_TRUE;
+	} else {
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id,
+				port_id));
+		if (NULL == phy_drv->phy_link_status_get) {
+			return SW_NOT_SUPPORTED;
+		}
+
+		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR (rv);
+
+		*status = phy_drv->phy_link_status_get (dev_id, phy_id);
+	}
+
+	return SW_OK;
+
+}
+
+sw_error_t 
+adpt_mp_portctrl_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+	{
+		return SW_FAIL;
+	}
+#ifndef IN_PORTCONTROL_MINI
+	p_adpt_api->adpt_port_txmac_status_get = adpt_mp_port_txmac_status_get;
+	p_adpt_api->adpt_port_rxmac_status_get = adpt_mp_port_rxmac_status_get;
+	p_adpt_api->adpt_port_rxfc_status_get = adpt_mp_port_rxfc_status_get;
+	p_adpt_api->adpt_port_txfc_status_get = adpt_mp_port_txfc_status_get;
+	p_adpt_api->adpt_port_flowctrl_get = adpt_mp_port_flowctrl_get;
+	p_adpt_api->adpt_port_flowctrl_forcemode_get =
+		adpt_mp_port_flowctrl_forcemode_get;
+	p_adpt_api->adpt_port_promisc_mode_get = adpt_mp_port_promisc_mode_get;
+	p_adpt_api->adpt_port_interface_3az_status_get = adpt_mp_port_mac_eee_enable_get;
+#endif
+	p_adpt_api->adpt_port_txmac_status_set = adpt_mp_port_txmac_status_set;
+	p_adpt_api->adpt_port_rxmac_status_set = adpt_mp_port_rxmac_status_set;
+	p_adpt_api->adpt_port_rxfc_status_set = adpt_mp_port_rxfc_status_set;
+	p_adpt_api->adpt_port_txfc_status_set = adpt_mp_port_txfc_status_set;
+	p_adpt_api->adpt_port_flowctrl_set = adpt_mp_port_flowctrl_set;
+	p_adpt_api->adpt_port_flowctrl_forcemode_set =
+		adpt_mp_port_flowctrl_forcemode_set;
+	p_adpt_api->adpt_port_max_frame_size_set = adpt_mp_port_max_frame_size_set;
+	p_adpt_api->adpt_port_max_frame_size_get = adpt_mp_port_max_frame_size_get;
+	p_adpt_api->adpt_port_promisc_mode_set = adpt_mp_port_promisc_mode_set;
+	p_adpt_api->adpt_port_mac_speed_set = adpt_mp_port_mac_speed_set;
+	p_adpt_api->adpt_port_speed_get = adpt_mp_port_speed_get;
+	p_adpt_api->adpt_port_mac_duplex_set = adpt_mp_port_mac_duplex_set;
+	p_adpt_api->adpt_port_duplex_get = adpt_mp_port_duplex_get;
+	p_adpt_api->adpt_port_link_status_get = adpt_mp_port_link_status_get;
+	p_adpt_api->adpt_port_interface_3az_status_set = adpt_mp_port_mac_eee_enable_set;
+	p_adpt_api->adpt_port_interface_eee_cfg_set = adpt_mp_port_interface_eee_cfg_set;
+	p_adpt_api->adpt_port_interface_eee_cfg_get = adpt_mp_port_interface_eee_cfg_get;
+	p_adpt_api->adpt_port_netdev_notify_set = adpt_mp_port_netdev_change_notify;
+	p_adpt_api->adpt_port_polling_sw_sync_set = adpt_mp_port_lpi_polling_task;
+
+	return SW_OK;
+}
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/mp/adpt_mp_uniphy.c b/qca-ssdk/src/adpt/mp/adpt_mp_uniphy.c
new file mode 100644
index 0000000..77acad0
--- /dev/null
+++ b/qca-ssdk/src/adpt/mp/adpt_mp_uniphy.c
@@ -0,0 +1,398 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_uniphy_reg.h"
+#include "hppe_uniphy.h"
+#include "hppe_init.h"
+#include "ssdk_init.h"
+#include "ssdk_clk.h"
+#include "ssdk_dts.h"
+#include "adpt.h"
+#include "mp_uniphy_reg.h"
+#include "mp_uniphy.h"
+#include "hsl_phy.h"
+
+static sw_error_t
+_adpt_mp_uniphy_calibrate(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+	a_uint32_t reg_value = 0;
+	a_uint32_t retries = 100, calibration_done = 0;
+	union uniphy_offset_calib_4_u uniphy_offset_calib_4;
+
+	memset(&uniphy_offset_calib_4, 0, sizeof(uniphy_offset_calib_4));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if(ssdk_is_emulation(dev_id)){
+		SSDK_INFO("uniphy_index %d on emulation platform\n", uniphy_index);
+		return SW_OK;
+	}
+	/*wait calibration done to uniphy*/
+	while (calibration_done != UNIPHY_CALIBRATION_DONE) {
+		mdelay(1);
+		if (retries-- == 0)
+		{
+			SSDK_ERROR("uniphy callibration time out!\n");
+			return SW_TIMEOUT;
+		}
+		reg_value = 0;
+		hppe_uniphy_offset_calib_4_get(dev_id, uniphy_index, &uniphy_offset_calib_4);
+		reg_value = uniphy_offset_calib_4.bf.mmd1_reg_calibration_done_reg;
+
+		calibration_done = (reg_value & UNIPHY_CALIBRATION_DONE);
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_mp_uniphy_adapter_port_reset(a_uint32_t dev_id,
+	a_uint32_t port_id)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t uniphy_index = 0;
+	union uniphy_channel0_input_output_4_u uniphy_channel0_input_output_4;
+
+	memset(&uniphy_channel0_input_output_4, 0, sizeof(uniphy_channel0_input_output_4));
+
+	if (port_id == SSDK_PHYSICAL_PORT2) {
+		uniphy_index = SSDK_UNIPHY_INSTANCE0;
+	} else {
+		SSDK_ERROR("uniphy adapter reset port_id is %d\n", port_id);
+		return SW_BAD_VALUE;
+	}
+
+	rv = hppe_uniphy_channel0_input_output_4_get(dev_id, uniphy_index,
+		&uniphy_channel0_input_output_4);
+	SW_RTN_ON_ERROR (rv);
+	uniphy_channel0_input_output_4.bf.newaddedfromhere_ch0_adp_sw_rstn = 0;
+	rv = hppe_uniphy_channel0_input_output_4_set(dev_id, uniphy_index,
+		&uniphy_channel0_input_output_4);
+	SW_RTN_ON_ERROR (rv);
+	uniphy_channel0_input_output_4.bf.newaddedfromhere_ch0_adp_sw_rstn = 1;
+	rv = hppe_uniphy_channel0_input_output_4_set(dev_id, uniphy_index,
+		&uniphy_channel0_input_output_4);
+	SW_RTN_ON_ERROR (rv);
+
+	return rv;
+}
+
+sw_error_t
+adpt_mp_gcc_uniphy_port_clock_set(a_uint32_t dev_id, a_uint32_t port_id,
+	a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+
+	if (port_id == SSDK_PHYSICAL_PORT1) {
+		qca_gcc_uniphy_port_clock_set(dev_id, SSDK_UNIPHY_INSTANCE0,
+				port_id, enable);
+	} else if (port_id == SSDK_PHYSICAL_PORT2) {
+		qca_gcc_uniphy_port_clock_set(dev_id, SSDK_UNIPHY_INSTANCE1,
+				port_id, enable);
+	} else {
+		return SW_BAD_VALUE;
+	}
+
+	return rv;
+}
+
+void
+adpt_mp_gcc_uniphy_port_set(a_uint32_t dev_id, a_uint32_t port_id,
+	a_bool_t enable)
+{
+	enum unphy_rst_type rst_type;
+
+	if (port_id == SSDK_PHYSICAL_PORT2) {
+		rst_type = UNIPHY1_SOFT_RESET_E;
+	} else {
+		return;
+	}
+
+	if (enable == A_TRUE) {
+		ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_DEASSERT);
+	} else {
+		ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_ASSERT);
+	}
+
+	return;
+}
+
+void
+adpt_mp_gcc_uniphy_port_reset(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	adpt_mp_gcc_uniphy_port_set(dev_id, port_id, A_FALSE);
+
+	msleep(100);
+
+	adpt_mp_gcc_uniphy_port_set(dev_id, port_id, A_TRUE);
+
+	return;
+}
+
+static sw_error_t
+adpt_mp_uniphy_reset(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+	sw_error_t rv = SW_OK;
+	union pll_power_on_and_reset_u pll_software_reset;
+
+	memset(&pll_software_reset, 0, sizeof(pll_software_reset));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_uniphy_pll_reset_ctrl_get(dev_id, uniphy_index,
+		&pll_software_reset);
+	SW_RTN_ON_ERROR (rv);
+	pll_software_reset.bf.software_reset_analog_reset = 0;
+	rv = hppe_uniphy_pll_reset_ctrl_set(dev_id, uniphy_index,
+		&pll_software_reset);
+	SW_RTN_ON_ERROR (rv);
+	msleep(500);
+	pll_software_reset.bf.software_reset_analog_reset = 1;
+	rv = hppe_uniphy_pll_reset_ctrl_set(dev_id, uniphy_index,
+		&pll_software_reset);
+	SW_RTN_ON_ERROR (rv);
+	msleep(500);
+
+	return SW_OK;
+}
+
+static sw_error_t
+adpt_mp_uniphy_mode_ctrl_set(a_uint32_t dev_id,
+	a_uint32_t uniphy_index, a_uint32_t mode)
+{
+	sw_error_t rv = SW_OK;
+	union uniphy_mode_ctrl_u uniphy_mode_ctrl;
+	union uniphy_channel0_input_output_4_u uniphy_force_ctrl;
+	a_bool_t force_port = 0;
+
+	memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
+	memset(&uniphy_force_ctrl, 0, sizeof(uniphy_force_ctrl));
+
+	force_port = ssdk_port_feature_get(dev_id, SSDK_PHYSICAL_PORT2,
+				PHY_F_FORCE);
+	/* configure uniphy mode ctrl to sgmii/sgmiiplus */
+	rv = hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
+	SW_RTN_ON_ERROR (rv);
+	if (mode == PORT_WRAPPER_SGMII_CHANNEL0) {
+		uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+			UNIPHY_SGMII_MODE_ENABLE;
+		uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+			UNIPHY_SGMIIPLUS_MODE_DISABLE;
+		if (force_port == A_TRUE) {
+			rv = hppe_uniphy_channel0_input_output_4_get(dev_id,
+				uniphy_index, &uniphy_force_ctrl);
+			SW_RTN_ON_ERROR (rv);
+			uniphy_force_ctrl.bf.newaddedfromhere_ch0_force_speed_25m =
+				UNIPHY_FORCE_SPEED_ENABLE;
+			rv = hppe_uniphy_channel0_input_output_4_set(dev_id,
+				uniphy_index, &uniphy_force_ctrl);
+			SW_RTN_ON_ERROR (rv);
+		}
+	} else {
+		uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+			UNIPHY_SGMII_MODE_DISABLE;
+		uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+			UNIPHY_SGMIIPLUS_MODE_ENABLE;
+	}
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode =
+		UNIPHY_ATHEROS_NEGOTIATION;
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+		UNIPHY_CH0_QSGMII_SGMII_MODE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+		UNIPHY_CH0_SGMII_MODE;
+	uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+		UNIPHY_XPCS_MODE_DISABLE;
+	rv = hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
+
+	return rv;
+}
+
+static sw_error_t
+_adpt_mp_uniphy_clk_output_ctrl_set(a_uint32_t dev_id, a_uint32_t index,
+	a_uint32_t clk_rate)
+{
+	sw_error_t rv = SW_OK;
+	union uniphy_clock_output_control_u clock_output;
+
+	memset(&clock_output, 0, sizeof(union uniphy_clock_output_control_u));
+	clock_output.bf.ref_clk_output_drv = UNIPHY_CLK_DRV_1;
+	clock_output.bf.ref_clk_output_en = A_TRUE;
+	SSDK_INFO("uniphy will output clock as %dHz\n", clk_rate);
+	if(clk_rate == UNIPHY_CLK_RATE_25M)
+	{
+		clock_output.bf.ref_clk_output_div = UNIPHY_CLK_DIV_25M;
+	}
+	else if(clk_rate == UNIPHY_CLK_RATE_50M)
+	{
+		clock_output.bf.ref_clk_output_div = UNIPHY_CLK_DIV_50M;
+	}
+	else
+	{
+		return SW_NOT_SUPPORTED;
+	}
+	rv = mp_uniphy_clock_output_control_set(dev_id, index,
+			&clock_output);
+
+	return rv;
+}
+
+static void
+_adpt_mp_uniphy_clk_output_set(a_uint32_t dev_id, a_uint32_t index)
+{
+	a_uint32_t phy_id =0;
+	a_bool_t force_port = A_FALSE;
+	a_uint32_t force_speed = 0;
+
+	/*when MP connect s17c or qca803x, need to reconfigure reference clock
+	as 25M for port 2*/
+	force_port = ssdk_port_feature_get(dev_id, SSDK_PHYSICAL_PORT2, PHY_F_FORCE);
+	force_speed = ssdk_port_force_speed_get(dev_id, SSDK_PHYSICAL_PORT2);
+
+	if ((force_port) && (force_speed == FAL_SPEED_1000))
+	{
+		_adpt_mp_uniphy_clk_output_ctrl_set(dev_id, index, UNIPHY_CLK_RATE_25M);
+	}
+	phy_id = hsl_port_phyid_get(dev_id, SSDK_PHYSICAL_PORT2);
+	if (phy_id == QCA8030_PHY || phy_id == QCA8033_PHY || phy_id == QCA8035_PHY)
+	{
+		_adpt_mp_uniphy_clk_output_ctrl_set(dev_id, index, UNIPHY_CLK_RATE_25M);
+	}
+
+	return;
+}
+
+sw_error_t
+adpt_mp_uniphy_mode_configure(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t clock = UNIPHY_CLK_RATE_125M;
+
+	union uniphy_misc2_phy_mode_u uniphy_misc2_phy_mode;
+
+	memset(&uniphy_misc2_phy_mode, 0, sizeof(uniphy_misc2_phy_mode));
+
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	if (index != SSDK_UNIPHY_INSTANCE0) {
+		SSDK_ERROR("uniphy index is %d\n", index);
+		return SW_BAD_VALUE;
+	}
+
+	if (mode == PORT_WRAPPER_MAX) {
+		adpt_mp_gcc_uniphy_port_set(dev_id, SSDK_PHYSICAL_PORT2,
+			A_FALSE);
+		return SW_OK;
+	} else if ((mode == PORT_WRAPPER_SGMII_CHANNEL0) ||
+		(mode == PORT_WRAPPER_SGMII_PLUS)) {
+		adpt_mp_gcc_uniphy_port_set(dev_id, SSDK_PHYSICAL_PORT2,
+			A_TRUE);
+	} else {
+		return SW_NOT_SUPPORTED;
+	}
+
+	/*set the PHY mode to SGMII or SGMIIPLUS*/
+	rv = hppe_uniphy_phy_mode_ctrl_get(dev_id, index,
+		&uniphy_misc2_phy_mode);
+	SW_RTN_ON_ERROR (rv);
+	if (mode == PORT_WRAPPER_SGMII_CHANNEL0) {
+		uniphy_misc2_phy_mode.bf.phy_mode =
+			UNIPHY_PHY_SGMII_MODE;
+		clock = UNIPHY_CLK_RATE_125M;
+	} else {
+		uniphy_misc2_phy_mode.bf.phy_mode =
+			UNIPHY_PHY_SGMIIPLUS_MODE;
+		clock = UNIPHY_CLK_RATE_312M;
+	}
+	rv = hppe_uniphy_phy_mode_ctrl_set(dev_id, index,
+		&uniphy_misc2_phy_mode);
+	SW_RTN_ON_ERROR (rv);
+
+	/* reset uniphy */
+	rv = adpt_mp_uniphy_reset(dev_id, index);
+	SW_RTN_ON_ERROR (rv);
+
+	/* disable uniphy port clock */
+	rv = adpt_mp_gcc_uniphy_port_clock_set(dev_id, SSDK_PHYSICAL_PORT2,
+		A_FALSE);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = adpt_mp_uniphy_mode_ctrl_set(dev_id, index, mode);
+	SW_RTN_ON_ERROR (rv);
+
+	adpt_mp_gcc_uniphy_port_reset(dev_id, SSDK_PHYSICAL_PORT2);
+
+	/* wait uniphy calibration done */
+	rv = _adpt_mp_uniphy_calibrate(dev_id, index);
+	SW_RTN_ON_ERROR (rv);
+
+	/* enable instance clock */
+	rv = adpt_mp_gcc_uniphy_port_clock_set(dev_id, SSDK_PHYSICAL_PORT2,
+		A_TRUE);
+	SW_RTN_ON_ERROR (rv);
+
+	if (SW_OK == rv) {
+		/* index + 1 point to mp uniphy clock */
+		ssdk_mp_raw_clock_set(index + 1, UNIPHY_RX, clock);
+		ssdk_mp_raw_clock_set(index + 1, UNIPHY_TX, clock);
+	}
+
+	if (mode == PORT_WRAPPER_SGMII_CHANNEL0) {
+		SSDK_DEBUG("mp uniphy %d sgmii configuration is done!\n", index);
+	} else {
+		SSDK_DEBUG("mp uniphy %d sgmiiplus configuration is done!\n", index);
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_mp_uniphy_mode_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode)
+{
+	sw_error_t rv = SW_OK;
+
+	rv = adpt_mp_uniphy_mode_configure(dev_id, index, mode);
+	SW_RTN_ON_ERROR(rv);
+	_adpt_mp_uniphy_clk_output_set(dev_id, index);
+
+	/*port2 is connected with PHY, need gpio reset*/
+	if(!ssdk_port_feature_get(dev_id, SSDK_PHYSICAL_PORT2, PHY_F_FORCE))
+	{
+		hsl_port_phy_gpio_reset(dev_id, SSDK_PHYSICAL_PORT2);
+		msleep(100);
+		hsl_port_phy_hw_init(dev_id, SSDK_PHYSICAL_PORT2);
+	}
+
+	return rv;
+}
+
+sw_error_t adpt_mp_uniphy_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	SW_RTN_ON_NULL(p_adpt_api = adpt_api_ptr_get(dev_id));
+
+	p_adpt_api->adpt_uniphy_mode_set = adpt_mp_uniphy_mode_set;
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/adpt/sfp/Makefile b/qca-ssdk/src/adpt/sfp/Makefile
new file mode 100755
index 0000000..fdf2ab6
--- /dev/null
+++ b/qca-ssdk/src/adpt/sfp/Makefile
@@ -0,0 +1,16 @@
+LOC_DIR=src/adpt/sfp
+LIB=ADPT
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=
+
+ifeq (TRUE, $(IN_SFP))
+	SRC_LIST += adpt_sfp.c
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/adpt/sfp/adpt_sfp.c b/qca-ssdk/src/adpt/sfp/adpt_sfp.c
new file mode 100755
index 0000000..f555127
--- /dev/null
+++ b/qca-ssdk/src/adpt/sfp/adpt_sfp.c
@@ -0,0 +1,668 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "adpt.h"
+#include "sfp_reg.h"
+#include "sfp.h"
+#include "hsl_phy.h"
+
+
+#define ADPT_RTN_ON_INVALID_DATA_OFFSET(offset) \
+    do { if (offset > 0xff) return(SW_BAD_PARAM); } while(0);
+
+#define ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id) \
+	do { if (PHY_I2C_ACCESS != hsl_port_phy_access_type_get(dev_id, port_id)) \
+		return(SW_NOT_SUPPORTED); } while(0);
+
+sw_error_t
+adpt_sfp_diag_ctrl_status_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_ctrl_status_t *ctrl_status)
+{
+	sw_error_t rv = SW_OK;
+	union sfp_diag_optional_ctrl_status_u sfp_diag_optional_ctrl_status;
+	union sfp_diag_extended_ctrl_status_u sfp_diag_extended_ctrl_status;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(ctrl_status);
+
+	memset(&sfp_diag_optional_ctrl_status, 0, sizeof(sfp_diag_optional_ctrl_status));
+	memset(&sfp_diag_extended_ctrl_status, 0, sizeof(sfp_diag_extended_ctrl_status));
+
+	rv = sfp_diag_optional_ctrl_status_get(dev_id,
+			port_id, &sfp_diag_optional_ctrl_status);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = sfp_diag_extended_ctrl_status_get(dev_id,
+			port_id, &sfp_diag_extended_ctrl_status);
+	SW_RTN_ON_ERROR(rv);
+
+	ctrl_status->data_ready = sfp_diag_optional_ctrl_status.bf.data_ready;
+	ctrl_status->rx_los = sfp_diag_optional_ctrl_status.bf.rx_los;
+	ctrl_status->tx_fault = sfp_diag_optional_ctrl_status.bf.tx_fault;
+	ctrl_status->soft_rate_sel = sfp_diag_optional_ctrl_status.bf.soft_rate_sel;
+	ctrl_status->rate_sel = sfp_diag_optional_ctrl_status.bf.rate_sel;
+	ctrl_status->rs_state = sfp_diag_optional_ctrl_status.bf.rs;
+	ctrl_status->soft_tx_disable = sfp_diag_optional_ctrl_status.bf.soft_tx_disable_sel;
+	ctrl_status->tx_disable = sfp_diag_optional_ctrl_status.bf.tx_disable;
+
+	ctrl_status->pwr_level_sel = sfp_diag_extended_ctrl_status.bf.pwr_level_sel;
+	ctrl_status->pwr_level_op_state = sfp_diag_extended_ctrl_status.bf.pwr_level_op_state;
+	ctrl_status->soft_rs_sel = sfp_diag_extended_ctrl_status.bf.soft_rs_sel;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_diag_extenal_calibration_const_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_cal_const_t *cal_const)
+{
+	sw_error_t rv = SW_OK;
+	union sfp_diag_cal_const_u sfp_diag_cal_const;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(cal_const);
+
+	memset(&sfp_diag_cal_const, 0, sizeof(sfp_diag_cal_const));
+
+	rv = sfp_diag_cal_const_get(dev_id, port_id, &sfp_diag_cal_const);
+	SW_RTN_ON_ERROR(rv);
+
+	cal_const->rx_power4 = sfp_diag_cal_const.bf.rx_pwr_4_0 << 24
+		| sfp_diag_cal_const.bf.rx_pwr_4_1 << 16
+		| sfp_diag_cal_const.bf.rx_pwr_4_2 << 8
+		| sfp_diag_cal_const.bf.rx_pwr_4_3;
+	cal_const->rx_power3 = sfp_diag_cal_const.bf.rx_pwr_3_0 << 24
+		| sfp_diag_cal_const.bf.rx_pwr_3_1 << 16
+		| sfp_diag_cal_const.bf.rx_pwr_3_2 << 8
+		| sfp_diag_cal_const.bf.rx_pwr_3_3;
+	cal_const->rx_power2 = sfp_diag_cal_const.bf.rx_pwr_2_0 << 24
+		| sfp_diag_cal_const.bf.rx_pwr_2_1 << 16
+		| sfp_diag_cal_const.bf.rx_pwr_2_2 << 8
+		| sfp_diag_cal_const.bf.rx_pwr_2_3;
+	cal_const->rx_power1 = sfp_diag_cal_const.bf.rx_pwr_1_0 << 24
+		| sfp_diag_cal_const.bf.rx_pwr_1_1 << 16
+		| sfp_diag_cal_const.bf.rx_pwr_1_2 << 8
+		| sfp_diag_cal_const.bf.rx_pwr_1_3;
+	cal_const->rx_power0 = sfp_diag_cal_const.bf.rx_pwr_0_0 << 24
+		| sfp_diag_cal_const.bf.rx_pwr_0_1 << 16
+		| sfp_diag_cal_const.bf.rx_pwr_0_2 << 8
+		| sfp_diag_cal_const.bf.rx_pwr_0_3;
+
+	cal_const->tx_bias_slope = sfp_diag_cal_const.bf.tx_i_slope_0 << 8
+		| sfp_diag_cal_const.bf.tx_i_slope_1;
+	cal_const->tx_bias_offset = sfp_diag_cal_const.bf.tx_i_offset_0 << 8
+		| sfp_diag_cal_const.bf.tx_i_offset_1;
+
+	cal_const->tx_power_slope = sfp_diag_cal_const.bf.tx_pwr_slope_0 << 8
+		| sfp_diag_cal_const.bf.tx_pwr_slope_1;
+	cal_const->tx_power_offset = sfp_diag_cal_const.bf.tx_pwr_offset_0 << 8
+		| sfp_diag_cal_const.bf.tx_pwr_offset_1;
+
+	cal_const->temp_slope = sfp_diag_cal_const.bf.t_slope_0 << 8
+		| sfp_diag_cal_const.bf.t_slope_1;
+	cal_const->temp_offset = sfp_diag_cal_const.bf.t_offset_0 << 8
+		| sfp_diag_cal_const.bf.t_offset_1;
+
+	cal_const->vol_slope = sfp_diag_cal_const.bf.v_slope_0 << 8
+		| sfp_diag_cal_const.bf.v_slope_1;
+	cal_const->vol_offset = sfp_diag_cal_const.bf.v_offset_0 << 8
+		| sfp_diag_cal_const.bf.v_offset_1;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_link_length_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_link_length_t *link_len)
+{
+	sw_error_t rv = SW_OK;
+	union sfp_link_len_u sfp_link_len;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(link_len);
+
+	memset(&sfp_link_len, 0, sizeof(sfp_link_len));
+
+	rv = sfp_link_len_get(dev_id, port_id, &sfp_link_len);
+	SW_RTN_ON_ERROR(rv);
+
+	link_len->single_mode_length_km = sfp_link_len.bf.single_mode_km;
+	link_len->single_mode_length_100m = sfp_link_len.bf.single_mode_100m;
+	link_len->om2_mode_length_10m = sfp_link_len.bf.om2_mode_10m;
+	link_len->om1_mode_length_10m = sfp_link_len.bf.om1_mode_10m;
+	link_len->copper_mode_length_1m = sfp_link_len.bf.copper_mode_1m;
+	link_len->om3_mode_length_1m = sfp_link_len.bf.om3_mode_1m;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_diag_internal_threshold_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_internal_threshold_t *threshold)
+{
+	sw_error_t rv = SW_OK;
+	union sfp_diag_threshold_u sfp_diag_threshold;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(threshold);
+
+	memset(&sfp_diag_threshold, 0, sizeof(sfp_diag_threshold));
+
+	rv = sfp_diag_threshold_get(dev_id, port_id, &sfp_diag_threshold);
+	SW_RTN_ON_ERROR(rv);
+
+	threshold->temp_high_alarm = sfp_diag_threshold.bf.temp_high_alarm_0 << 8
+		| sfp_diag_threshold.bf.temp_high_alarm_1;
+	threshold->temp_low_alarm = sfp_diag_threshold.bf.temp_low_alarm_0 << 8
+		| sfp_diag_threshold.bf.temp_low_alarm_1;
+	threshold->temp_high_warning = sfp_diag_threshold.bf.temp_high_warning_0 << 8
+		| sfp_diag_threshold.bf.temp_high_warning_1;
+	threshold->temp_low_warning = sfp_diag_threshold.bf.temp_low_warning_0 << 8
+		| sfp_diag_threshold.bf.temp_low_warning_1;
+	threshold->vol_high_alarm = sfp_diag_threshold.bf.vol_high_alarm_0 << 8
+		| sfp_diag_threshold.bf.vol_high_alarm_1;
+	threshold->vol_low_alarm = sfp_diag_threshold.bf.vol_low_alarm_0 << 8
+		| sfp_diag_threshold.bf.vol_low_alarm_1;
+	threshold->vol_high_warning = sfp_diag_threshold.bf.vol_high_warning_0 << 8
+		| sfp_diag_threshold.bf.vol_high_warning_1;
+	threshold->vol_low_warning = sfp_diag_threshold.bf.vol_low_warning_0 << 8
+		| sfp_diag_threshold.bf.vol_low_warning_1;
+	threshold->bias_high_alarm = sfp_diag_threshold.bf.bias_high_alarm_0 << 8
+		| sfp_diag_threshold.bf.bias_high_alarm_1;
+	threshold->bias_low_alarm = sfp_diag_threshold.bf.bias_low_alarm_0 << 8
+		| sfp_diag_threshold.bf.bias_low_alarm_1;
+	threshold->bias_high_warning = sfp_diag_threshold.bf.bias_high_warning_0 << 8
+		| sfp_diag_threshold.bf.bias_high_warning_1;
+	threshold->bias_low_warning = sfp_diag_threshold.bf.bias_low_warning_0 << 8
+		| sfp_diag_threshold.bf.bias_low_warning_1;
+	threshold->tx_power_high_alarm = sfp_diag_threshold.bf.tx_pwr_high_alarm_0 << 8
+		| sfp_diag_threshold.bf.tx_pwr_high_alarm_1;
+	threshold->tx_power_low_alarm = sfp_diag_threshold.bf.tx_pwr_low_alarm_0 << 8
+		| sfp_diag_threshold.bf.tx_pwr_low_alarm_1;
+	threshold->tx_power_high_warning = sfp_diag_threshold.bf.tx_pwr_high_warning_0 << 8
+		| sfp_diag_threshold.bf.tx_pwr_high_warning_1;
+	threshold->tx_power_low_warning = sfp_diag_threshold.bf.tx_pwr_low_warning_0 << 8
+		| sfp_diag_threshold.bf.tx_pwr_low_warning_1;
+	threshold->rx_power_high_alarm = sfp_diag_threshold.bf.rx_pwr_high_alarm_0 << 8
+		| sfp_diag_threshold.bf.rx_pwr_high_alarm_1;
+	threshold->rx_power_low_alarm = sfp_diag_threshold.bf.rx_pwr_low_alarm_0 << 8
+		| sfp_diag_threshold.bf.rx_pwr_low_alarm_1;
+	threshold->rx_power_high_warning = sfp_diag_threshold.bf.rx_pwr_high_warning_0 << 8
+		| sfp_diag_threshold.bf.rx_pwr_high_warning_1;
+	threshold->rx_power_low_warning = sfp_diag_threshold.bf.rx_pwr_low_warning_0 << 8
+		| sfp_diag_threshold.bf.rx_pwr_low_warning_1;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_diag_realtime_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_realtime_diag_t *real_diag)
+{
+	sw_error_t rv = SW_OK;
+	union sfp_diag_realtime_u sfp_diag_realtime;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(real_diag);
+
+	memset(&sfp_diag_realtime, 0, sizeof(sfp_diag_realtime));
+
+	rv = sfp_diag_realtime_get(dev_id, port_id, &sfp_diag_realtime);
+	SW_RTN_ON_ERROR(rv);
+
+	real_diag->cur_temp = sfp_diag_realtime.bf.tmp_0 << 8
+		| sfp_diag_realtime.bf.tmp_1;
+	real_diag->cur_vol = sfp_diag_realtime.bf.vcc_0 << 8
+		| sfp_diag_realtime.bf.vcc_1;
+	real_diag->tx_cur_bias = sfp_diag_realtime.bf.tx_bias_0 << 8
+		| sfp_diag_realtime.bf.tx_bias_1;
+	real_diag->tx_cur_power = sfp_diag_realtime.bf.tx_pwr_0 << 8
+		| sfp_diag_realtime.bf.tx_pwr_1;
+	real_diag->rx_cur_power = sfp_diag_realtime.bf.rx_pwr_0 << 8
+		| sfp_diag_realtime.bf.rx_pwr_1;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_laser_wavelength_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_laser_wavelength_t *laser_wavelen)
+{
+	sw_error_t rv = SW_OK;
+	union sfp_laser_u sfp_laser;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(laser_wavelen);
+
+	memset(&sfp_laser, 0, sizeof(sfp_laser));
+
+	rv = sfp_laser_get(dev_id, port_id, &sfp_laser);
+	SW_RTN_ON_ERROR(rv);
+
+	laser_wavelen->laser_wavelength = sfp_laser.bf.wavelength_0 << 8
+		| sfp_laser.bf.wavelength_1;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_option_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_option_t *option)
+{
+	sw_error_t rv = SW_OK;
+	union sfp_option_u sfp_option;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(option);
+
+	memset(&sfp_option, 0, sizeof(sfp_option));
+
+	rv = sfp_option_get(dev_id, port_id, &sfp_option);
+	SW_RTN_ON_ERROR(rv);
+
+	option->linear_recv_output = sfp_option.bf.linear_recv_output;
+	option->pwr_level_declar = sfp_option.bf.pwr_level_declar;
+	option->cool_transc_declar = sfp_option.bf.cool_transc_declar;
+	option->loss_signal = sfp_option.bf.loss_signal;
+	option->loss_invert_signal = sfp_option.bf.loss_invert_signal;
+	option->tx_fault_signal = sfp_option.bf.tx_fault_signal;
+	option->tx_disable = sfp_option.bf.tx_disable;
+	option->rate_sel = sfp_option.bf.rate_sel;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_checkcode_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_cc_type_t cc_type, a_uint8_t *ccode)
+{
+	sw_error_t rv = SW_OK;
+	union sfp_base_u sfp_base;
+	union sfp_ext_u sfp_ext;
+	union sfp_diag_dmi_u sfp_dmi;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(ccode);
+
+	memset(&sfp_base, 0, sizeof(sfp_base));
+	memset(&sfp_ext, 0, sizeof(sfp_ext));
+	memset(&sfp_dmi, 0, sizeof(sfp_dmi));
+
+	switch (cc_type) {
+		case FAL_SFP_CC_BASE:
+			rv = sfp_base_get(dev_id, port_id, &sfp_base);
+			SW_RTN_ON_ERROR(rv);
+			*ccode = sfp_base.bf.check_code;
+			break;
+		case FAL_SFP_CC_EXT:
+			rv = sfp_ext_get(dev_id, port_id, &sfp_ext);
+			SW_RTN_ON_ERROR(rv);
+			*ccode = sfp_ext.bf.check_code;
+			break;
+		case FAL_SFP_CC_DMI:
+			rv = sfp_diag_dmi_get(dev_id,
+					port_id, &sfp_dmi);
+			SW_RTN_ON_ERROR(rv);
+			*ccode = sfp_dmi.bf.check_code;
+			break;
+		default:
+			return SW_BAD_PARAM;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_diag_alarm_warning_flag_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_alarm_warn_flag_t *alarm_warn_flag)
+{
+	sw_error_t rv = SW_OK;
+	union sfp_diag_flag_u sfp_diag_flag;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(alarm_warn_flag);
+
+	memset(&sfp_diag_flag, 0, sizeof(sfp_diag_flag));
+
+	rv = sfp_diag_flag_get(dev_id, port_id, &sfp_diag_flag);
+	SW_RTN_ON_ERROR(rv);
+
+	alarm_warn_flag->tx_pwr_low_alarm = sfp_diag_flag.bf.tx_pwr_low_alarm;
+	alarm_warn_flag->tx_pwr_high_alarm = sfp_diag_flag.bf.tx_pwr_high_alarm;
+	alarm_warn_flag->tx_bias_low_alarm = sfp_diag_flag.bf.tx_bias_low_alarm;
+	alarm_warn_flag->tx_bias_high_alarm = sfp_diag_flag.bf.tx_bias_high_alarm;
+	alarm_warn_flag->vcc_low_alarm = sfp_diag_flag.bf.vcc_low_alarm;
+	alarm_warn_flag->vcc_high_alarm = sfp_diag_flag.bf.vcc_high_alarm;
+	alarm_warn_flag->tmp_low_alarm = sfp_diag_flag.bf.tmp_low_alarm;
+	alarm_warn_flag->tmp_high_alarm = sfp_diag_flag.bf.tmp_high_alarm;
+	alarm_warn_flag->rx_pwr_low_alarm = sfp_diag_flag.bf.rx_pwr_low_alarm;
+	alarm_warn_flag->rx_pwr_high_alarm = sfp_diag_flag.bf.rx_pwr_high_alarm;
+
+	alarm_warn_flag->tx_pwr_low_warning = sfp_diag_flag.bf.tx_pwr_low_warning;
+	alarm_warn_flag->tx_pwr_high_warning = sfp_diag_flag.bf.tx_pwr_high_warning;
+	alarm_warn_flag->tx_bias_low_warning = sfp_diag_flag.bf.tx_bias_low_warning;
+	alarm_warn_flag->tx_bias_high_warning = sfp_diag_flag.bf.tx_bias_high_warning;
+	alarm_warn_flag->vcc_low_warning = sfp_diag_flag.bf.vcc_low_warning;
+	alarm_warn_flag->vcc_high_warning = sfp_diag_flag.bf.vcc_high_warning;
+	alarm_warn_flag->tmp_low_warning = sfp_diag_flag.bf.tmp_low_warning;
+	alarm_warn_flag->tmp_high_warning = sfp_diag_flag.bf.tmp_high_warning;
+	alarm_warn_flag->rx_pwr_low_warning = sfp_diag_flag.bf.rx_pwr_low_warning;
+	alarm_warn_flag->rx_pwr_high_warning = sfp_diag_flag.bf.rx_pwr_high_warning;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_device_type_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_dev_type_t *sfp_id)
+{
+	sw_error_t rv = SW_OK;
+	union sfp_dev_type_u sfp_dev_type;
+	union sfp_dev_type_ext_u sfp_dev_type_ext;
+	union sfp_dev_connector_type_u sfp_dev_connector_type;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(sfp_id);
+
+	memset(&sfp_dev_type, 0, sizeof(sfp_dev_type));
+	memset(&sfp_dev_type_ext, 0, sizeof(sfp_dev_type_ext));
+	memset(&sfp_dev_connector_type, 0, sizeof(sfp_dev_connector_type));
+
+	rv = sfp_dev_type_get(dev_id, port_id, &sfp_dev_type);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = sfp_dev_type_ext_get(dev_id, port_id, &sfp_dev_type_ext);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = sfp_dev_connector_type_get(dev_id, port_id, &sfp_dev_connector_type);
+	SW_RTN_ON_ERROR(rv);
+
+	sfp_id->identifier = sfp_dev_type.bf.id;
+	sfp_id->ext_indentifier = sfp_dev_type_ext.bf.id;
+	sfp_id->connector_type = sfp_dev_connector_type.bf.code;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_vendor_info_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_vendor_info_t *vender_info)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t index, i;
+	union sfp_vendor_u sfp_vendor;
+	union sfp_vendor_ext_u sfp_vendor_ext;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(vender_info);
+
+	memset(&sfp_vendor, 0, sizeof(sfp_vendor));
+	memset(&sfp_vendor_ext, 0, sizeof(sfp_vendor_ext));
+
+	rv = sfp_vendor_get(dev_id, port_id, &sfp_vendor);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = sfp_vendor_ext_get(dev_id, port_id, &sfp_vendor_ext);
+	SW_RTN_ON_ERROR(rv);
+
+	/* vendor basic info */
+	for (index = 0, i = 0; i < sizeof(vender_info->vendor_name); index++) {
+		vender_info->vendor_name[i++] = *(sfp_vendor.val + index);
+	}
+
+	/* skip Transceiver Code for electronic or optical compatibility */
+	index++;
+
+	for (i = 0; i < sizeof(vender_info->vendor_oui); index++) {
+		vender_info->vendor_oui[i++] = *(sfp_vendor.val + index);
+	}
+
+	for (i = 0; i < sizeof(vender_info->vendor_pn); index++) {
+		vender_info->vendor_pn[i++] = *(sfp_vendor.val + index);
+	}
+
+	for (i = 0; i < sizeof(vender_info->vendor_rev); index++) {
+		vender_info->vendor_rev[i++] = *(sfp_vendor.val + index);
+	}
+
+	/* vendor extended info */
+	for (index = 0, i = 0; i < sizeof(vender_info->vendor_sn); index++) {
+		vender_info->vendor_sn[i++] = *(sfp_vendor_ext.val + index);
+	}
+
+	for (i = 0; i < sizeof(vender_info->vendor_date_code); index++) {
+		vender_info->vendor_date_code[i++] = *(sfp_vendor_ext.val + index);
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_transceiver_code_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_transc_code_t *transc_code)
+{
+	sw_error_t rv = SW_OK;
+	union sfp_transc_u sfp_transc;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(transc_code);
+
+	memset(&sfp_transc, 0, sizeof(sfp_transc));
+
+	rv = sfp_transc_get(dev_id, port_id, &sfp_transc);
+	SW_RTN_ON_ERROR(rv);
+
+	transc_code->eth_10g_ccode = sfp_transc.bf.eth_10g_ccode;
+	transc_code->infiniband_ccode = sfp_transc.bf.infiniband_ccode;
+	transc_code->escon_ccode = sfp_transc.bf.escon_ccode;
+	transc_code->sonet_ccode = sfp_transc.bf.sonet_ccode_1 << 8
+		| sfp_transc.bf.sonet_ccode_2;
+	transc_code->eth_ccode = sfp_transc.bf.eth_ccode;
+	transc_code->fibre_chan_link_length = sfp_transc.bf.fiber_ch_link_len;
+	transc_code->fibre_chan_tech = sfp_transc.bf.fiber_ch_tech_1 << 4
+		| sfp_transc.bf.fiber_ch_tech_2;
+	transc_code->sfp_cable_tech = sfp_transc.bf.cable_tech;
+	transc_code->fibre_chan_trans_md = sfp_transc.bf.fiber_chan_tm_media;
+	transc_code->fibre_chan_speed = sfp_transc.bf.fiber_ch_speed;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_ctrl_rate_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_rate_t *rate_limit)
+{
+	sw_error_t rv = SW_OK;
+	union sfp_rate_ctrl_u sfp_rate_ctrl;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(rate_limit);
+
+	memset(&sfp_rate_ctrl, 0, sizeof(sfp_rate_ctrl));
+
+	rv = sfp_rate_ctrl_get(dev_id, port_id, &sfp_rate_ctrl);
+	SW_RTN_ON_ERROR(rv);
+
+	rate_limit->upper_rate_limit = sfp_rate_ctrl.bf.upper;
+	rate_limit->lower_rate_limit = sfp_rate_ctrl.bf.lower;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_enhanced_cfg_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_enhanced_cfg_t *enhanced_feature)
+{
+	sw_error_t rv = SW_OK;
+	union sfp_enhanced_u sfp_enhanced;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(enhanced_feature);
+
+	memset(&sfp_enhanced, 0, sizeof(sfp_enhanced));
+
+	rv = sfp_enhanced_get(dev_id, port_id, &sfp_enhanced);
+	SW_RTN_ON_ERROR(rv);
+
+	enhanced_feature->addr_mode = sfp_enhanced.bf.addr_mode;
+	enhanced_feature->rec_pwr_type = sfp_enhanced.bf.re_pwr_type;
+	enhanced_feature->external_cal = sfp_enhanced.bf.external_cal;
+	enhanced_feature->internal_cal = sfp_enhanced.bf.internal_cal;
+	enhanced_feature->diag_mon_flag = sfp_enhanced.bf.diag_mon_flag;
+	enhanced_feature->legacy_type = sfp_enhanced.bf.legacy_type;
+
+	enhanced_feature->soft_rate_sel_op = sfp_enhanced.bf.soft_rate_sel_op;
+	enhanced_feature->app_sel_op = sfp_enhanced.bf.app_sel_op;
+	enhanced_feature->soft_rate_ctrl_op = sfp_enhanced.bf.soft_rate_ctrl_op;
+	enhanced_feature->rx_los_op = sfp_enhanced.bf.rx_los_op;
+	enhanced_feature->tx_fault_op = sfp_enhanced.bf.tx_fault_op;
+	enhanced_feature-> tx_disable_ctrl_op = sfp_enhanced.bf.tx_disable_ctrl_op;
+	enhanced_feature->alarm_warning_flag_op = sfp_enhanced.bf.alarm_warning_flag_op;
+
+	enhanced_feature->compliance_feature = sfp_enhanced.bf.cmpl_feature;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_rate_encode_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_sfp_rate_encode_t *encode)
+{
+	sw_error_t rv = SW_OK;
+	union sfp_encoding_u sfp_encoding;
+	union sfp_br_u sfp_br;
+	union sfp_rate_u sfp_rate;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(encode);
+
+	memset(&sfp_encoding, 0, sizeof(sfp_encoding));
+	memset(&sfp_br, 0, sizeof(sfp_br));
+	memset(&sfp_rate, 0, sizeof(sfp_rate));
+
+	rv = sfp_encoding_get(dev_id, port_id, &sfp_encoding);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = sfp_br_get(dev_id, port_id, &sfp_br);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = sfp_rate_get(dev_id, port_id, &sfp_rate);
+	SW_RTN_ON_ERROR(rv);
+
+	encode->encode = sfp_encoding.bf.code;
+	encode->nominal_bit_rate = sfp_br.bf.bit;
+	encode->rate_id = sfp_rate.bf.id;
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_eeprom_data_get(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry)
+{
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	ADPT_RTN_ON_INVALID_DATA_OFFSET(entry->offset + entry->count);
+
+	rv = sfp_eeprom_data_get(dev_id, port_id, entry->addr,
+			entry->offset, entry->data, entry->count);
+	SW_RTN_ON_ERROR(rv);
+
+	return SW_OK;
+}
+
+sw_error_t
+adpt_sfp_eeprom_data_set(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry)
+{
+	sw_error_t rv = SW_OK;
+
+	ADPT_DEV_ID_CHECK(dev_id);
+	ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id);
+	ADPT_NULL_POINT_CHECK(entry);
+
+	ADPT_RTN_ON_INVALID_DATA_OFFSET(entry->offset + entry->count);
+
+	rv = sfp_eeprom_data_set(dev_id, port_id, entry->addr,
+			entry->offset, entry->data, entry->count);
+	SW_RTN_ON_ERROR(rv);
+
+	/* retrieve the data */
+	rv = sfp_eeprom_data_get(dev_id, port_id, entry->addr,
+			entry->offset, entry->data, entry->count);
+	SW_RTN_ON_ERROR(rv);
+
+	return SW_OK;
+}
+
+sw_error_t adpt_sfp_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	p_adpt_api->adpt_sfp_diag_ctrl_status_get = adpt_sfp_diag_ctrl_status_get;
+	p_adpt_api->adpt_sfp_diag_extenal_calibration_const_get =
+		adpt_sfp_diag_extenal_calibration_const_get;
+	p_adpt_api->adpt_sfp_link_length_get = adpt_sfp_link_length_get;
+	p_adpt_api->adpt_sfp_diag_internal_threshold_get =
+		adpt_sfp_diag_internal_threshold_get;
+	p_adpt_api->adpt_sfp_diag_realtime_get = adpt_sfp_diag_realtime_get;
+	p_adpt_api->adpt_sfp_laser_wavelength_get = adpt_sfp_laser_wavelength_get;
+	p_adpt_api->adpt_sfp_option_get = adpt_sfp_option_get;
+	p_adpt_api->adpt_sfp_checkcode_get = adpt_sfp_checkcode_get;
+	p_adpt_api->adpt_sfp_diag_alarm_warning_flag_get =
+		adpt_sfp_diag_alarm_warning_flag_get;
+	p_adpt_api->adpt_sfp_device_type_get = adpt_sfp_device_type_get;
+	p_adpt_api->adpt_sfp_vendor_info_get = adpt_sfp_vendor_info_get;
+	p_adpt_api->adpt_sfp_transceiver_code_get = adpt_sfp_transceiver_code_get;
+	p_adpt_api->adpt_sfp_ctrl_rate_get = adpt_sfp_ctrl_rate_get;
+	p_adpt_api->adpt_sfp_enhanced_cfg_get = adpt_sfp_enhanced_cfg_get;
+	p_adpt_api->adpt_sfp_rate_encode_get = adpt_sfp_rate_encode_get;
+	p_adpt_api->adpt_sfp_eeprom_data_get = adpt_sfp_eeprom_data_get;
+	p_adpt_api->adpt_sfp_eeprom_data_set = adpt_sfp_eeprom_data_set;
+
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/api/Makefile b/qca-ssdk/src/api/Makefile
new file mode 100755
index 0000000..25c788a
--- /dev/null
+++ b/qca-ssdk/src/api/Makefile
@@ -0,0 +1,12 @@
+LOC_DIR=src/sal
+LIB=API
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=$(wildcard *.c)
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/qca-ssdk/src/api/api_access.c b/qca-ssdk/src/api/api_access.c
new file mode 100755
index 0000000..3fd2fc2
--- /dev/null
+++ b/qca-ssdk/src/api/api_access.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2012, 2017-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+/*qca808x_start*/
+#include "sw.h"
+#include "fal.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+
+#include "sw_api.h"
+#include "api_desc.h"
+/*qca808x_end*/
+#if (((!defined(USER_MODE)) && defined(KERNEL_MODULE)) || (defined(USER_MODE) && (!defined(KERNEL_MODULE))))
+#ifdef HSL_STANDALONG
+#if defined ATHENA
+#include "athena_api.h"
+#elif defined GARUDA
+#include "garuda_api.h"
+#elif defined SHIVA
+#include "shiva_api.h"
+#elif defined HORUS
+#include "horus_api.h"
+#elif defined ISIS
+#include "isis_api.h"
+#elif defined ISISC
+#include "isisc_api.h"
+#endif
+#else
+#include "ref_api.h"
+#include "fal_api.h"
+#endif
+#elif (defined(USER_MODE))
+#if defined ATHENA
+#include "athena_api.h"
+#elif defined GARUDA
+#include "garuda_api.h"
+#elif defined SHIVA
+#include "shiva_api.h"
+#elif defined HORUS
+#include "horus_api.h"
+#elif defined ISIS
+#include "isis_api.h"
+#elif defined ISISC
+#include "isisc_api.h"
+#endif
+#else
+#include "ref_api.h"
+/*qca808x_start*/
+#include "fal_api.h"
+/*qca808x_end*/
+#endif
+#include "ref_vsi.h"
+#include "ref_vlan.h"
+
+/*qca808x_start*/
+static sw_api_func_t sw_api_func[] = {
+/*qca808x_end*/
+	SSDK_REF_API
+/*qca808x_start*/
+	SSDK_API };
+static sw_api_param_t sw_api_param[] = {
+/*qca808x_end*/
+	SSDK_REF_PARAM
+/*qca808x_start*/
+	SSDK_PARAM };
+
+sw_api_func_t *
+sw_api_func_find(a_uint32_t api_id)
+{
+    a_uint32_t i = 0;
+    static a_uint32_t save = 0;
+
+    if(api_id == sw_api_func[save].api_id)
+        return &sw_api_func[save];
+
+    do
+    {
+        if (api_id == sw_api_func[i].api_id)
+        {
+            save = i;
+            return &sw_api_func[i];
+        }
+
+    }
+    while (++i < (sizeof(sw_api_func)/sizeof(sw_api_func[0])));
+
+    return NULL;
+}
+
+sw_api_param_t *
+sw_api_param_find(a_uint32_t api_id)
+{
+    a_uint32_t i = 0;
+    static a_uint32_t save = 0;
+
+    if(api_id == sw_api_param[save].api_id)
+        return &sw_api_param[save];
+
+    do
+    {
+        if (api_id == sw_api_param[i].api_id)
+        {
+            save = i;
+            return &sw_api_param[i];
+        }
+    }
+    while (++i < (sizeof(sw_api_param)/sizeof(sw_api_param[0])));
+
+    return NULL;
+}
+
+a_uint32_t
+sw_api_param_nums(a_uint32_t api_id)
+{
+    a_uint32_t i = 0;
+    sw_api_param_t *p = NULL;
+    static sw_api_param_t *savep = NULL;
+    static a_uint32_t save = 0;
+
+    p = sw_api_param_find(api_id);
+    if (!p)
+    {
+        return 0;
+    }
+
+    if (p == savep)
+    {
+        return save;
+    }
+
+    savep = p;
+    while (api_id == p->api_id)
+    {
+        p++;
+        i++;
+    }
+
+    /*error*/
+    if(i >= sizeof(sw_api_param)/sizeof(sw_api_param[0]))
+    {
+        savep = NULL;
+        save = 0;
+        return 0;
+    }
+    save = i;
+
+    return i;
+}
+
+sw_error_t
+sw_api_get(sw_api_t *sw_api)
+{
+    if(!sw_api)
+        return SW_FAIL;
+
+    if ((sw_api->api_fp = sw_api_func_find(sw_api->api_id)) == NULL)
+        return SW_NOT_SUPPORTED;
+
+    if ((sw_api->api_pp = sw_api_param_find(sw_api->api_id)) == NULL)
+        return SW_NOT_SUPPORTED;
+
+    if((sw_api->api_nr = sw_api_param_nums(sw_api->api_id)) == 0)
+        return SW_NOT_SUPPORTED;
+
+    return SW_OK;
+}
+/*qca808x_end*/
diff --git a/qca-ssdk/src/fal/Makefile b/qca-ssdk/src/fal/Makefile
new file mode 100755
index 0000000..9e711e6
--- /dev/null
+++ b/qca-ssdk/src/fal/Makefile
@@ -0,0 +1,140 @@
+LOC_DIR=src/fal
+LIB=FAL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=fal_init.c fal_reg_access.c
+
+ifeq (TRUE, $(IN_ACL))
+  SRC_LIST += fal_acl.c
+endif
+
+ifeq (TRUE, $(IN_FDB))
+  SRC_LIST += fal_fdb.c
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+  SRC_LIST += fal_igmp.c
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+  SRC_LIST += fal_leaky.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+  SRC_LIST += fal_led.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+  SRC_LIST += fal_mib.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+  SRC_LIST += fal_mirror.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+  SRC_LIST += fal_misc.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+  SRC_LIST += fal_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+  SRC_LIST += fal_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+  SRC_LIST += fal_qos.c
+endif
+
+ifeq (TRUE, $(IN_RATE))
+  SRC_LIST += fal_rate.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+  SRC_LIST += fal_stp.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+  SRC_LIST += fal_vlan.c
+endif
+
+ifeq (TRUE, $(IN_COSMAP))
+  SRC_LIST += fal_cosmap.c
+endif
+
+ifeq (TRUE, $(IN_IP))
+  SRC_LIST += fal_ip.c
+endif
+
+ifeq (TRUE, $(IN_NAT))
+  SRC_LIST += fal_nat.c
+endif
+
+ifeq (TRUE, $(IN_FLOW))
+  SRC_LIST += fal_flow.c
+endif
+
+ifeq (TRUE, $(IN_SEC))
+  SRC_LIST += fal_sec.c
+endif
+
+ifeq (TRUE, $(IN_TRUNK))
+  SRC_LIST += fal_trunk.c
+endif
+
+ifeq (TRUE, $(IN_VSI))
+  SRC_LIST += fal_vsi.c
+endif
+
+ifeq (TRUE, $(IN_INTERFACECONTROL))
+  SRC_LIST += fal_interface_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_QM))
+  SRC_LIST += fal_qm.c
+endif
+
+ifeq (TRUE, $(IN_BM))
+  SRC_LIST += fal_bm.c
+endif
+
+ifeq (TRUE, $(IN_CTRLPKT))
+  SRC_LIST += fal_ctrlpkt.c
+endif
+
+ifeq (TRUE, $(IN_SERVCODE))
+  SRC_LIST += fal_servcode.c
+endif
+
+ifeq (TRUE, $(IN_RSS_HASH))
+  SRC_LIST += fal_rss_hash.c
+endif
+
+ifeq (TRUE, $(IN_PPPOE))
+  SRC_LIST += fal_pppoe.c
+endif
+
+ifeq (TRUE, $(IN_SHAPER))
+  SRC_LIST += fal_shaper.c
+endif
+
+ifeq (TRUE, $(IN_POLICER))
+  SRC_LIST += fal_policer.c
+endif
+
+ifeq (TRUE, $(IN_PTP))
+  SRC_LIST += fal_ptp.c
+endif
+
+ifeq (TRUE, $(IN_SFP))
+  SRC_LIST += fal_sfp.c
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/fal/fal_acl.c b/qca-ssdk/src/fal/fal_acl.c
new file mode 100755
index 0000000..22fbeb1
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_acl.c
@@ -0,0 +1,741 @@
+/*
+ * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_acl FAL_ACL
+ * @{
+ */
+#include "sw.h"
+#include "fal_acl.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+static sw_error_t
+_fal_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t prio)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_acl_list_creat)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_acl_list_creat(dev_id, list_id, prio);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_list_creat)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_list_creat(dev_id, list_id, prio);
+    return rv;
+}
+
+static sw_error_t
+_fal_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_acl_list_destroy)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_acl_list_destroy(dev_id, list_id);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_list_destroy)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_list_destroy(dev_id, list_id);
+    return rv;
+}
+
+static sw_error_t
+_fal_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+                  a_uint32_t rule_nr, fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_acl_rule_add)
+            return SW_NOT_SUPPORTED;
+        rv = p_adpt_api->adpt_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_rule_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule);
+    return rv;
+}
+
+static sw_error_t
+_fal_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+                     a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_acl_rule_delete)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_acl_rule_delete(dev_id, list_id, rule_id, rule_nr);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_rule_delete)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_rule_delete(dev_id, list_id, rule_id, rule_nr);
+    return rv;
+}
+
+static sw_error_t
+_fal_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+                    fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_acl_rule_query)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_acl_rule_query(dev_id, list_id, rule_id, rule);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_rule_query)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_rule_query(dev_id, list_id, rule_id, rule);
+    return rv;
+}
+
+static sw_error_t
+_fal_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                   fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                   a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_acl_list_bind)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_list_bind)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx);
+    return rv;
+}
+
+static sw_error_t
+_fal_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                     fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                     a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_acl_list_unbind)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_list_unbind)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx);
+    return rv;
+}
+
+static sw_error_t
+_fal_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_status_set(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_status_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_acl_udf_type_t udf_type, a_uint32_t offset,
+                              a_uint32_t length)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_port_udf_profile_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_port_udf_profile_set(dev_id, port_id, udf_type, offset, length);
+    return rv;
+}
+
+static sw_error_t
+_fal_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_acl_udf_type_t udf_type, a_uint32_t * offset,
+                              a_uint32_t * length)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_port_udf_profile_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_port_udf_profile_get(dev_id, port_id, udf_type, offset, length);
+    return rv;
+}
+
+static sw_error_t
+_fal_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+                     a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_rule_active)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_rule_active(dev_id, list_id, rule_id, rule_nr);
+    return rv;
+}
+
+static sw_error_t
+_fal_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+                       a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_rule_deactive)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_rule_deactive(dev_id, list_id, rule_id, rule_nr);
+    return rv;
+}
+
+static sw_error_t
+_fal_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+                                 a_uint32_t rule_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_rule_src_filter_sts_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_rule_src_filter_sts_set(dev_id, rule_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
+                                 a_uint32_t rule_id, a_bool_t* enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_rule_src_filter_sts_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_rule_src_filter_sts_get(dev_id, rule_id, enable);
+    return rv;
+}
+
+sw_error_t
+_fal_acl_udf_profile_set(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t udf_type, a_uint32_t offset)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_acl_udf_profile_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_acl_udf_profile_set(dev_id, pkt_type, udf_idx, udf_type, offset);
+    return rv;
+}
+sw_error_t
+_fal_acl_udf_profile_get(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t *udf_type, a_uint32_t *offset)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_acl_udf_profile_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_acl_udf_profile_get(dev_id, pkt_type, udf_idx, udf_type, offset);
+    return rv;
+}
+/*insert flag for inner fal, don't remove it*/
+
+sw_error_t
+fal_acl_list_dump(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_list_dump)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_list_dump(dev_id);
+    return rv;
+}
+
+sw_error_t
+fal_acl_rule_dump(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_acl_rule_dump)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_acl_rule_dump(dev_id);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->acl_rule_dump)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_rule_dump(dev_id);
+    return rv;
+}
+
+/**
+ * @brief Creat an acl list
+ * @details  Comments:
+  *     If the priority of a list is more small then the priority is more high,
+ *     that means the list could be first matched.
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] list_pri acl list priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t prio)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_list_creat(dev_id, list_id, prio);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Destroy an acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_list_destroy(dev_id, list_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one rule or more rules to an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this adding operation in list
+ * @param[in] rule_nr rule number of this adding operation
+ * @param[in] rule rules content of this adding operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+                 a_uint32_t rule_nr, fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one rule or more rules from an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[in] rule_nr rule number of this deleteing operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+                    a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_rule_delete(dev_id, list_id, rule_id, rule_nr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Query one particular rule in a particular acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[out] rule rule content of this operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+                   fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_rule_query(dev_id, list_id, rule_id, rule);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind an acl list to a particular object
+ * @details  Comments:
+ *    If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this binding operation
+ * @param[in] obj_t object type of this binding operation
+ * @param[in] obj_idx object index of this binding operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                  fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                  a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Unbind an acl list from a particular object
+ * @details  Comments:
+  *    If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this unbinding operation
+ * @param[in] obj_t object type of this unbinding operation
+ * @param[in] obj_idx object index of this unbinding operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                    fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                    a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_status_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_status_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set user define fields profile on a particular port
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] udf_type udf type
+ * @param[in] offset udf offset
+ * @param[in] length udf length
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_acl_udf_type_t udf_type, a_uint32_t offset,
+                             a_uint32_t length)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_port_udf_profile_set(dev_id, port_id, udf_type, offset,
+                                       length);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get user define fields profile on a particular port
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] udf_type udf type
+ * @param[out] offset udf offset
+ * @param[out] length udf length
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_acl_udf_type_t udf_type, a_uint32_t * offset,
+                             a_uint32_t * length)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_port_udf_profile_get(dev_id, port_id, udf_type, offset,
+                                       length);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Active one or more rules in an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] rule_nr rule number of this deactive operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+                    a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_rule_active(dev_id, list_id, rule_id, rule_nr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Deactive one or more rules in an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] rule_nr rule number of this deactive operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+                      a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_rule_deactive(dev_id, list_id, rule_id, rule_nr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief set status of one rule source filter
+ * @param[in] dev_id device id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+                                a_uint32_t rule_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_rule_src_filter_sts_set(dev_id, rule_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief get status of one rule source filter
+ * @param[in] dev_id device id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
+                                a_uint32_t rule_id, a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_rule_src_filter_sts_get(dev_id, rule_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_acl_udf_profile_set(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t udf_type, a_uint32_t offset)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_udf_profile_set(dev_id, pkt_type, udf_idx, udf_type, offset);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_acl_udf_profile_get(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t *udf_type, a_uint32_t *offset)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_udf_profile_get(dev_id, pkt_type, udf_idx, udf_type, offset);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/*insert flag for outter fal, don't remove it*/
+
+EXPORT_SYMBOL(fal_acl_list_creat);
+EXPORT_SYMBOL(fal_acl_list_destroy);
+EXPORT_SYMBOL(fal_acl_rule_add);
+EXPORT_SYMBOL(fal_acl_rule_delete);
+EXPORT_SYMBOL(fal_acl_rule_query);
+EXPORT_SYMBOL(fal_acl_list_bind);
+EXPORT_SYMBOL(fal_acl_list_unbind);
+EXPORT_SYMBOL(fal_acl_status_set);
+EXPORT_SYMBOL(fal_acl_status_get);
+EXPORT_SYMBOL(fal_acl_port_udf_profile_set);
+EXPORT_SYMBOL(fal_acl_port_udf_profile_get);
+EXPORT_SYMBOL(fal_acl_rule_active);
+EXPORT_SYMBOL(fal_acl_rule_deactive);
+EXPORT_SYMBOL(fal_acl_rule_src_filter_sts_set);
+EXPORT_SYMBOL(fal_acl_rule_src_filter_sts_get);
+EXPORT_SYMBOL(fal_acl_udf_profile_set);
+EXPORT_SYMBOL(fal_acl_udf_profile_get);
+
diff --git a/qca-ssdk/src/fal/fal_bm.c b/qca-ssdk/src/fal/fal_bm.c
new file mode 100755
index 0000000..dc23734
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_bm.c
@@ -0,0 +1,422 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_qm FAL_BM
+ * @{
+ */
+#include "sw.h"
+#include "fal_bm.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#ifndef IN_BM_MINI
+sw_error_t
+_fal_port_bufgroup_map_get(a_uint32_t dev_id, fal_port_t port,
+			a_uint8_t *group)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_bufgroup_map_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_bufgroup_map_get(dev_id, port, group);
+	return rv;
+}
+sw_error_t
+_fal_bm_port_reserved_buffer_get(a_uint32_t dev_id, fal_port_t port,
+			a_uint16_t *prealloc_buff, a_uint16_t *react_buff)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_bm_port_reserved_buffer_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_bm_port_reserved_buffer_get(dev_id, port, prealloc_buff, react_buff);
+	return rv;
+}
+sw_error_t
+_fal_bm_bufgroup_buffer_get(a_uint32_t dev_id, a_uint8_t group,
+			a_uint16_t *buff_num)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_bm_bufgroup_buffer_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_bm_bufgroup_buffer_get(dev_id, group, buff_num);
+	return rv;
+}
+sw_error_t
+_fal_bm_port_dynamic_thresh_get(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_dynamic_cfg_t *cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_bm_port_dynamic_thresh_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_bm_port_dynamic_thresh_get(dev_id, port, cfg);
+	return rv;
+}
+sw_error_t
+_fal_port_bm_ctrl_get(a_uint32_t dev_id, fal_port_t port, a_bool_t *enable)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_bm_ctrl_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_bm_ctrl_get(dev_id, port, enable);
+	return rv;
+}
+#endif
+sw_error_t
+_fal_bm_bufgroup_buffer_set(a_uint32_t dev_id, a_uint8_t group,
+			a_uint16_t buff_num)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_bm_bufgroup_buffer_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_bm_bufgroup_buffer_set(dev_id, group, buff_num);
+	return rv;
+}
+sw_error_t
+_fal_port_bufgroup_map_set(a_uint32_t dev_id, fal_port_t port,
+			a_uint8_t group)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_bufgroup_map_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_bufgroup_map_set(dev_id, port, group);
+	return rv;
+}
+#ifndef IN_BM_MINI
+sw_error_t
+_fal_bm_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_static_cfg_t *cfg)
+{
+	adpt_api_t *p_api;
+	hsl_api_t *p_hsl_api;
+	sw_error_t rv = SW_OK;
+
+	if((p_api = adpt_api_ptr_get(dev_id)) != NULL) {
+		if (NULL == p_api->adpt_bm_port_static_thresh_get)
+			return SW_NOT_SUPPORTED;
+
+		rv = p_api->adpt_bm_port_static_thresh_get(dev_id, port, cfg);
+		return rv;
+	}
+
+	SW_RTN_ON_NULL(p_hsl_api = hsl_api_ptr_get(dev_id));
+
+	if (NULL == p_hsl_api->port_static_thresh_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_hsl_api->port_static_thresh_get(dev_id, port, cfg);
+	return rv;
+}
+#endif
+sw_error_t
+_fal_bm_port_reserved_buffer_set(a_uint32_t dev_id, fal_port_t port,
+			a_uint16_t prealloc_buff, a_uint16_t react_buff)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_bm_port_reserved_buffer_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_bm_port_reserved_buffer_set(dev_id, port, prealloc_buff, react_buff);
+	return rv;
+}
+sw_error_t
+_fal_bm_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_static_cfg_t *cfg)
+{
+	adpt_api_t *p_api;
+	hsl_api_t *p_hsl_api;
+	sw_error_t rv = SW_OK;
+
+	if((p_api = adpt_api_ptr_get(dev_id)) != NULL) {
+		if (NULL == p_api->adpt_bm_port_static_thresh_set)
+			return SW_NOT_SUPPORTED;
+
+		rv = p_api->adpt_bm_port_static_thresh_set(dev_id, port, cfg);
+		return rv;
+	}
+
+	SW_RTN_ON_NULL(p_hsl_api = hsl_api_ptr_get(dev_id));
+
+	if (NULL == p_hsl_api->port_static_thresh_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_hsl_api->port_static_thresh_set(dev_id, port, cfg);
+	return rv;
+}
+sw_error_t
+_fal_bm_port_dynamic_thresh_set(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_dynamic_cfg_t *cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_bm_port_dynamic_thresh_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_bm_port_dynamic_thresh_set(dev_id, port, cfg);
+	return rv;
+}
+sw_error_t
+_fal_port_bm_ctrl_set(a_uint32_t dev_id, fal_port_t port, a_bool_t enable)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_bm_ctrl_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_bm_ctrl_set(dev_id, port, enable);
+	return rv;
+}
+
+#ifndef IN_BM_MINI
+sw_error_t
+_fal_bm_port_counter_get(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_port_counter_t *counter)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_bm_port_counter_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_bm_port_counter_get(dev_id, port, counter);
+	return rv;
+}
+/*insert flag for inner fal, don't remove it*/
+
+sw_error_t
+fal_port_bufgroup_map_get(a_uint32_t dev_id, fal_port_t port,
+			a_uint8_t *group)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_port_bufgroup_map_get(dev_id, port, group);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_bm_port_reserved_buffer_get(a_uint32_t dev_id, fal_port_t port,
+			a_uint16_t *prealloc_buff, a_uint16_t *react_buff)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_bm_port_reserved_buffer_get(dev_id, port, prealloc_buff, react_buff);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_bm_bufgroup_buffer_get(a_uint32_t dev_id, a_uint8_t group,
+			a_uint16_t *buff_num)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_bm_bufgroup_buffer_get(dev_id, group, buff_num);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_bm_port_dynamic_thresh_get(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_dynamic_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_bm_port_dynamic_thresh_get(dev_id, port, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_port_bm_ctrl_get(a_uint32_t dev_id, fal_port_t port, a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_port_bm_ctrl_get(dev_id, port, enable);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#endif
+
+sw_error_t
+fal_bm_bufgroup_buffer_set(a_uint32_t dev_id, a_uint8_t group,
+			a_uint16_t buff_num)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_bm_bufgroup_buffer_set(dev_id, group, buff_num);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_port_bufgroup_map_set(a_uint32_t dev_id, fal_port_t port,
+			a_uint8_t group)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_port_bufgroup_map_set(dev_id, port, group);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#ifndef IN_BM_MINI
+sw_error_t
+fal_bm_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_static_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_bm_port_static_thresh_get(dev_id, port, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#endif
+sw_error_t
+fal_bm_port_reserved_buffer_set(a_uint32_t dev_id, fal_port_t port,
+			a_uint16_t prealloc_buff, a_uint16_t react_buff)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_bm_port_reserved_buffer_set(dev_id, port, prealloc_buff, react_buff);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_bm_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_static_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_bm_port_static_thresh_set(dev_id, port, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_bm_port_dynamic_thresh_set(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_dynamic_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_bm_port_dynamic_thresh_set(dev_id, port, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_port_bm_ctrl_set(a_uint32_t dev_id, fal_port_t port, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_port_bm_ctrl_set(dev_id, port, enable);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+#ifndef IN_BM_MINI
+sw_error_t
+fal_bm_port_counter_get(a_uint32_t dev_id, fal_port_t port,
+			fal_bm_port_counter_t *counter)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_bm_port_counter_get(dev_id, port, counter);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#endif
+
+EXPORT_SYMBOL(fal_port_bm_ctrl_set);
+
+EXPORT_SYMBOL(fal_port_bufgroup_map_set);
+
+EXPORT_SYMBOL(fal_bm_bufgroup_buffer_set);
+
+EXPORT_SYMBOL(fal_bm_port_reserved_buffer_set);
+
+EXPORT_SYMBOL(fal_bm_port_dynamic_thresh_set);
+
+#ifndef IN_BM_MINI
+EXPORT_SYMBOL(fal_port_bm_ctrl_get);
+
+EXPORT_SYMBOL(fal_port_bufgroup_map_get);
+
+EXPORT_SYMBOL(fal_bm_bufgroup_buffer_get);
+
+EXPORT_SYMBOL(fal_bm_port_reserved_buffer_get);
+
+EXPORT_SYMBOL(fal_bm_port_static_thresh_set);
+
+EXPORT_SYMBOL(fal_bm_port_static_thresh_get);
+
+EXPORT_SYMBOL(fal_bm_port_dynamic_thresh_get);
+
+EXPORT_SYMBOL(fal_bm_port_counter_get);
+#endif
+
+/*insert flag for outter fal, don't remove it*/
diff --git a/qca-ssdk/src/fal/fal_cosmap.c b/qca-ssdk/src/fal/fal_cosmap.c
new file mode 100755
index 0000000..4d7d84f
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_cosmap.c
@@ -0,0 +1,783 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_cosmap FAL_COSMAP
+ * @{
+ */
+#include "sw.h"
+#include "fal_cosmap.h"
+#include "hsl_api.h"
+
+#ifndef IN_COSMAP_MINI
+static sw_error_t
+_fal_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_dscp_to_pri_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_dscp_to_pri_set(dev_id, dscp, pri);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+                            a_uint32_t * pri)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_dscp_to_pri_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_dscp_to_pri_get(dev_id, dscp, pri);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_dscp_to_dp_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_dscp_to_dp_set(dev_id, dscp, dp);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_dscp_to_dp_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_dscp_to_dp_get(dev_id, dscp, dp);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_up_to_pri_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_up_to_pri_set(dev_id, up, pri);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_up_to_pri_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_up_to_pri_get(dev_id, up, pri);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_up_to_dp_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_up_to_dp_set(dev_id, up, dp);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_up_to_dp_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_up_to_dp_get(dev_id, up, dp);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_dscp_to_ehpri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_dscp_to_ehpri_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_dscp_to_ehpri_set(dev_id, dscp, pri);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_dscp_to_ehpri_get(a_uint32_t dev_id, a_uint32_t dscp,
+                            a_uint32_t * pri)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_dscp_to_ehpri_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_dscp_to_ehpri_get(dev_id, dscp, pri);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_dscp_to_ehdp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_dscp_to_ehdp_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_dscp_to_ehdp_set(dev_id, dscp, dp);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_dscp_to_ehdp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_dscp_to_ehdp_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_dscp_to_ehdp_get(dev_id, dscp, dp);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_up_to_ehpri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_up_to_ehpri_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_up_to_ehpri_set(dev_id, up, pri);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_up_to_ehpri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_up_to_ehpri_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_up_to_ehpri_get(dev_id, up, pri);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_up_to_ehdp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_up_to_ehdp_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_up_to_ehdp_set(dev_id, up, dp);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_up_to_ehdp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_up_to_ehdp_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_up_to_ehdp_get(dev_id, up, dp);
+    return rv;
+}
+#endif
+
+static sw_error_t
+_fal_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+                             a_uint32_t queue)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_pri_to_queue_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_pri_to_queue_set(dev_id, pri, queue);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+                               a_uint32_t queue)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_pri_to_ehqueue_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_pri_to_ehqueue_set(dev_id, pri, queue);
+    return rv;
+}
+
+#ifndef IN_COSMAP_MINI
+static sw_error_t
+_fal_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+                             a_uint32_t * queue)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_pri_to_queue_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_pri_to_queue_get(dev_id, pri, queue);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+                               a_uint32_t * queue)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_pri_to_ehqueue_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_pri_to_ehqueue_get(dev_id, pri, queue);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+                              fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_egress_remark_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_egress_remark_set(dev_id, tbl_id, tbl);
+    return rv;
+}
+
+static sw_error_t
+_fal_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+                              fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_egress_remark_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_egress_remark_get(dev_id, tbl_id, tbl);
+    return rv;
+}
+
+/**
+ * @brief Set dscp to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_dscp_to_pri_set(dev_id, dscp, pri);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dscp to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+                           a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_dscp_to_pri_get(dev_id, dscp, pri);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dscp to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_dscp_to_dp_set(dev_id, dscp, dp);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dscp to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_dscp_to_dp_get(dev_id, dscp, dp);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dot1p to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_up_to_pri_set(dev_id, up, pri);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dot1p to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_up_to_pri_get(dev_id, up, pri);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dot1p to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_up_to_dp_set(dev_id, up, dp);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dot1p to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_up_to_dp_get(dev_id, up, dp);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dscp to internal priority mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_to_ehpri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_dscp_to_ehpri_set(dev_id, dscp, pri);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dscp to internal priority mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_to_ehpri_get(a_uint32_t dev_id, a_uint32_t dscp,
+                           a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_dscp_to_ehpri_get(dev_id, dscp, pri);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dscp to internal drop precedence mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_to_ehdp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_dscp_to_ehdp_set(dev_id, dscp, dp);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dscp to internal drop precedence mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_to_ehdp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_dscp_to_ehdp_get(dev_id, dscp, dp);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dot1p to internal priority mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_to_ehpri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_up_to_ehpri_set(dev_id, up, pri);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dot1p to internal priority mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_to_ehpri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_up_to_ehpri_get(dev_id, up, pri);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dot1p to internal drop precedence mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_to_ehdp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_up_to_ehdp_set(dev_id, up, dp);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dot1p to internal drop precedence mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_to_ehdp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_up_to_ehdp_get(dev_id, up, dp);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 1/2/3/4 which have four egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+                            a_uint32_t queue)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_pri_to_queue_set(dev_id, pri, queue);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 0/5/6 which have six egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+                              a_uint32_t queue)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_pri_to_ehqueue_set(dev_id, pri, queue);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_COSMAP_MINI
+/**
+ * @brief Get internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 1/2/3/4 which have four egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+                            a_uint32_t * queue)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_pri_to_queue_get(dev_id, pri, queue);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 0/5/6 which have six egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+                              a_uint32_t * queue)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_pri_to_ehqueue_get(dev_id, pri, queue);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress queue based CoS remap table on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] tbl_id CoS remap table id
+ * @param[in] tbl CoS remap table
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+                             fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_egress_remark_set(dev_id, tbl_id, tbl);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress queue based CoS remap table on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] tbl_id CoS remap table id
+ * @param[out] tbl CoS remap table
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+                             fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_egress_remark_get(dev_id, tbl_id, tbl);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/fal/fal_ctrlpkt.c b/qca-ssdk/src/fal/fal_ctrlpkt.c
new file mode 100755
index 0000000..cfcf5a2
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_ctrlpkt.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_ctrlpkt FAL_CTRLPKT
+ * @{
+ */
+#include "sw.h"
+#include "fal_ctrlpkt.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+
+/**
+ * @}
+ */
+sw_error_t
+_fal_mgmtctrl_ethtype_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t ethtype)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_mgmtctrl_ethtype_profile_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_mgmtctrl_ethtype_profile_set(dev_id, profile_id, ethtype);
+    return rv;
+}
+
+sw_error_t
+_fal_mgmtctrl_ethtype_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t * ethtype)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_mgmtctrl_ethtype_profile_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_mgmtctrl_ethtype_profile_get(dev_id, profile_id, ethtype);
+    return rv;
+}
+
+sw_error_t
+_fal_mgmtctrl_rfdb_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_mgmtctrl_rfdb_profile_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_mgmtctrl_rfdb_profile_set(dev_id, profile_id, addr);
+    return rv;
+}
+
+sw_error_t
+_fal_mgmtctrl_rfdb_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_mgmtctrl_rfdb_profile_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_mgmtctrl_rfdb_profile_get(dev_id, profile_id, addr);
+    return rv;
+}
+
+sw_error_t
+_fal_mgmtctrl_ctrlpkt_profile_add(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_mgmtctrl_ctrlpkt_profile_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_mgmtctrl_ctrlpkt_profile_add(dev_id, ctrlpkt);
+    return rv;
+}
+
+sw_error_t
+_fal_mgmtctrl_ctrlpkt_profile_del(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_mgmtctrl_ctrlpkt_profile_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_mgmtctrl_ctrlpkt_profile_del(dev_id, ctrlpkt);
+    return rv;
+}
+
+sw_error_t
+_fal_mgmtctrl_ctrlpkt_profile_getfirst(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_mgmtctrl_ctrlpkt_profile_getfirst)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_mgmtctrl_ctrlpkt_profile_getfirst(dev_id, ctrlpkt);
+    return rv;
+}
+
+sw_error_t
+_fal_mgmtctrl_ctrlpkt_profile_getnext(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_mgmtctrl_ctrlpkt_profile_getnext)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_mgmtctrl_ctrlpkt_profile_getnext(dev_id, ctrlpkt);
+    return rv;
+}
+
+sw_error_t
+fal_mgmtctrl_ethtype_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t ethtype)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_CTRLPKT_API_LOCK;
+    rv = _fal_mgmtctrl_ethtype_profile_set(dev_id, profile_id, ethtype);
+    FAL_CTRLPKT_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_mgmtctrl_ethtype_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t * ethtype)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_CTRLPKT_API_LOCK;
+    rv = _fal_mgmtctrl_ethtype_profile_get(dev_id, profile_id, ethtype);
+    FAL_CTRLPKT_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_mgmtctrl_rfdb_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_CTRLPKT_API_LOCK;
+    rv = _fal_mgmtctrl_rfdb_profile_set(dev_id, profile_id, addr);
+    FAL_CTRLPKT_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_mgmtctrl_rfdb_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_CTRLPKT_API_LOCK;
+    rv = _fal_mgmtctrl_rfdb_profile_get(dev_id, profile_id, addr);
+    FAL_CTRLPKT_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_mgmtctrl_ctrlpkt_profile_add(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_CTRLPKT_API_LOCK;
+    rv = _fal_mgmtctrl_ctrlpkt_profile_add(dev_id, ctrlpkt);
+    FAL_CTRLPKT_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_mgmtctrl_ctrlpkt_profile_del(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_CTRLPKT_API_LOCK;
+    rv = _fal_mgmtctrl_ctrlpkt_profile_del(dev_id, ctrlpkt);
+    FAL_CTRLPKT_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_mgmtctrl_ctrlpkt_profile_getfirst(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_CTRLPKT_API_LOCK;
+    rv = _fal_mgmtctrl_ctrlpkt_profile_getfirst(dev_id, ctrlpkt);
+    FAL_CTRLPKT_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_mgmtctrl_ctrlpkt_profile_getnext(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_CTRLPKT_API_LOCK;
+    rv = _fal_mgmtctrl_ctrlpkt_profile_getnext(dev_id, ctrlpkt);
+    FAL_CTRLPKT_API_UNLOCK;
+    return rv;
+}
+
+EXPORT_SYMBOL(fal_mgmtctrl_ethtype_profile_set);
+EXPORT_SYMBOL(fal_mgmtctrl_ethtype_profile_get);
+EXPORT_SYMBOL(fal_mgmtctrl_rfdb_profile_set);
+EXPORT_SYMBOL(fal_mgmtctrl_rfdb_profile_get);
+EXPORT_SYMBOL(fal_mgmtctrl_ctrlpkt_profile_add);
+EXPORT_SYMBOL(fal_mgmtctrl_ctrlpkt_profile_del);
+EXPORT_SYMBOL(fal_mgmtctrl_ctrlpkt_profile_getfirst);
+EXPORT_SYMBOL(fal_mgmtctrl_ctrlpkt_profile_getnext);
+
diff --git a/qca-ssdk/src/fal/fal_fdb.c b/qca-ssdk/src/fal/fal_fdb.c
new file mode 100755
index 0000000..02dc74a
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_fdb.c
@@ -0,0 +1,1942 @@
+/*
+ * Copyright (c) 2012, 2015-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_fdb FAL_FDB
+ * @{
+ */
+#include "sw.h"
+#include "fal_fdb.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+
+#ifndef IN_FDB_MINI
+static sw_error_t
+_fal_fdb_entry_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_add)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_add(dev_id, entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_add(dev_id, entry);
+    return rv;
+}
+#endif
+
+static sw_error_t
+_fal_fdb_entry_flush(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_del_all)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_del_all(dev_id, flag);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_del_all)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_del_all(dev_id, flag);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_entry_del_byport(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_del_by_port)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_del_by_port(dev_id, port_id, flag);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_del_by_port)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_del_by_port(dev_id, port_id, flag);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_fdb_entry_del_bymac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_del_by_mac)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_del_by_mac(dev_id, entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_del_by_mac)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_del_by_mac(dev_id, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_entry_getfirst(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_first)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_first(dev_id, entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_first)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_first(dev_id, entry);
+    return rv;
+}
+
+#ifndef IN_FDB_MINI
+static sw_error_t
+_fal_fdb_entry_getnext(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_next)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_next(dev_id, entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_next)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_next(dev_id, entry);
+    return rv;
+}
+#endif
+
+static sw_error_t
+_fal_fdb_entry_search(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_find)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_find(dev_id, entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_find)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_find(dev_id, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_port_learn_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_port_learn_set(dev_id, port_id, enable);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_learn_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_learn_set(dev_id, port_id, enable);
+    return rv;
+}
+
+#ifndef IN_FDB_MINI
+static sw_error_t
+_fal_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_port_learn_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_port_learn_get(dev_id, port_id, enable);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_learn_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_learn_get(dev_id, port_id, enable);
+    return rv;
+}
+#endif
+
+static sw_error_t
+_fal_fdb_port_learning_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_fdb_port_newaddr_lrn_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_fdb_port_newaddr_lrn_set(dev_id, port_id, enable, cmd);
+    return rv;
+}
+
+#ifndef IN_FDB_MINI
+static sw_error_t
+_fal_fdb_port_learning_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_fdb_port_newaddr_lrn_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_fdb_port_newaddr_lrn_get(dev_id, port_id, enable, cmd);
+    return rv;
+}
+#endif
+
+static sw_error_t
+_fal_fdb_port_stamove_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_fdb_port_stamove_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_fdb_port_stamove_set(dev_id, port_id, enable, cmd);
+    return rv;
+}
+
+#ifndef IN_FDB_MINI
+static sw_error_t
+_fal_fdb_port_stamove_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_fdb_port_stamove_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_fdb_port_stamove_get(dev_id, port_id, enable, cmd);
+    return rv;
+}
+#endif
+
+static sw_error_t
+_fal_fdb_aging_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_age_ctrl_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_age_ctrl_set(dev_id, enable);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->age_ctrl_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->age_ctrl_set(dev_id, enable);
+    return rv;
+}
+
+#ifndef IN_FDB_MINI
+static sw_error_t
+_fal_fdb_aging_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_age_ctrl_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_age_ctrl_get(dev_id, enable);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->age_ctrl_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->age_ctrl_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->vlan_ivl_svl_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->vlan_ivl_svl_set(dev_id, smode);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->vlan_ivl_svl_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->vlan_ivl_svl_get(dev_id, smode);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_aging_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_age_time_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_age_time_set(dev_id, time);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->age_time_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->age_time_set(dev_id, time);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_fdb_aging_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_age_time_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_age_time_get(dev_id, time);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->age_time_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->age_time_get(dev_id, time);
+    return rv;
+}
+#endif
+
+static sw_error_t
+_fal_fdb_entry_getnext_byindex(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_iterate)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_iterate(dev_id, iterator, entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_iterate)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_iterate(dev_id, iterator, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_entry_extend_getnext(a_uint32_t dev_id, fal_fdb_op_t * option,
+                     fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_extend_next)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_extend_next(dev_id, option, entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_extend_next)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_extend_next(dev_id, option, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_entry_extend_getfirst(a_uint32_t dev_id, fal_fdb_op_t * option,
+                      fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_extend_first)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_extend_first(dev_id, option, entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_extend_first)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_extend_first(dev_id, option, entry);
+    return rv;
+}
+
+#ifndef IN_FDB_MINI
+static sw_error_t
+_fal_fdb_entry_update_byport(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+                  a_uint32_t fid, fal_fdb_op_t * option)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_transfer)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_transfer(dev_id, old_port, new_port, fid, option);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_transfer)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_transfer(dev_id, old_port, new_port, fid, option);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_fdb_learn_limit_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_fdb_learn_limit_set(dev_id, port_id, enable, cnt);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_fdb_learn_limit_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_fdb_learn_limit_set(dev_id, port_id, enable, cnt);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_fdb_learn_limit_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_fdb_learn_limit_get(dev_id, port_id, enable, cnt);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_fdb_learn_limit_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_fdb_learn_limit_get(dev_id, port_id, enable, cnt);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_fdb_learn_exceed_cmd_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_fdb_learn_exceed_cmd_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_fdb_learn_exceed_cmd_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_fdb_learn_exceed_cmd_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_learn_limit_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_learn_limit_set(dev_id, enable, cnt);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_learn_limit_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_learn_limit_get(dev_id, enable, cnt);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_learn_exceed_cmd_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_learn_exceed_cmd_set(dev_id, cmd);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_learn_exceed_cmd_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_learn_exceed_cmd_get(dev_id, cmd);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_resv_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_resv_add(dev_id, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_resv_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_resv_del(dev_id, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_resv_find)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_resv_find(dev_id, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+                      fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_resv_iterate)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_resv_iterate(dev_id, iterator, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_port_learn_static_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_port_learn_static_set(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_port_learn_static_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_port_learn_static_get(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_port_add)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_port_add(dev_id, fid, addr, port_id);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_port_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_port_add(dev_id, fid, addr, port_id);
+    return rv;
+}
+
+static sw_error_t
+_fal_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_fdb_port_del)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_fdb_port_del(dev_id, fid, addr, port_id);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->fdb_port_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->fdb_port_del(dev_id, fid, addr, port_id);
+    return rv;
+}
+
+sw_error_t
+_fal_fdb_rfs_set(a_uint32_t dev_id, const fal_fdb_rfs_t * entry)
+{
+	sw_error_t rv;
+	hsl_api_t *p_api;
+
+	SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+	if (NULL == p_api->fdb_rfs_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->fdb_rfs_set(dev_id, entry);
+	return rv;
+}
+
+sw_error_t
+_fal_fdb_rfs_del(a_uint32_t dev_id, const fal_fdb_rfs_t * entry)
+{
+	sw_error_t rv;
+	hsl_api_t *p_api;
+
+	SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+	if (NULL == p_api->fdb_rfs_del)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->fdb_rfs_del(dev_id, entry);
+	return rv;
+}
+#endif
+
+sw_error_t
+_fal_fdb_learning_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_fdb_learn_ctrl_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_fdb_learn_ctrl_set(dev_id, enable);
+    return rv;
+}
+
+#ifndef IN_FDB_MINI
+sw_error_t
+_fal_fdb_learning_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_fdb_learn_ctrl_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_fdb_learn_ctrl_get(dev_id, enable);
+    return rv;
+}
+sw_error_t
+_fal_fdb_port_learned_mac_counter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t * cnt)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_fdb_learn_counter_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_fdb_learn_counter_get(dev_id, port_id, cnt);
+    return rv;
+}
+sw_error_t
+_fal_fdb_port_maclimit_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_fdb_port_maclimit_ctrl_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_fdb_port_maclimit_ctrl_set(dev_id, port_id, maclimit_ctrl);
+    return rv;
+}
+sw_error_t
+_fal_fdb_port_maclimit_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_fdb_port_maclimit_ctrl_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_fdb_port_maclimit_ctrl_get(dev_id, port_id, maclimit_ctrl);
+    return rv;
+}
+#endif
+sw_error_t
+_fal_fdb_entry_del_byfid(a_uint32_t dev_id, a_uint16_t fid, a_uint32_t flag)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_fdb_del_by_fid)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_fdb_del_by_fid(dev_id, fid, flag);
+    return rv;
+}
+#ifndef IN_FDB_MINI
+/*insert flag for inner fal, don't remove it*/
+
+/**
+ * @brief Add a Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_entry_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_entry_add(dev_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Delete all Fdb entries
+ *   @details   Comments:
+ *         If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ *       entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_entry_flush(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_entry_flush(dev_id, flag);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete Fdb entries on a particular port
+ *   @details   Comments:
+ *       If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ *       entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_entry_del_byport(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_entry_del_byport(dev_id, port_id, flag);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a particular Fdb entry through mac address
+ *   @details   Comments:
+ *       Only addr field in entry is meaning. For IVL learning vid or fid field
+ *       also is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_entry_del_bymac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_entry_del_bymac(dev_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from particular device
+ * @param[in] dev_id device id
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_entry_getfirst(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_entry_getfirst(dev_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_FDB_MINI
+/**
+ * @brief Get next Fdb entry from particular device
+ *   @details   Comments:
+    For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_entry_getnext(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_entry_getnext(dev_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Find a particular Fdb entry from device through mac address.
+ *    @details  Comments:
+    For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_entry_search(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_entry_search(dev_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address and station move learning status on a particular port.
+ *    @details  Comments:
+ *       This operation will enable or disable dynamic address and
+ *       station move learning feature on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_port_learn_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_FDB_MINI
+/**
+ * @brief Get dynamic address and station move learning status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_port_learn_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set dynamic address learning and forward command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] learning status
+ * @param[in] forward command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_port_learning_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_port_learning_ctrl_set(dev_id, port_id, enable, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_FDB_MINI
+/**
+ * @brief Get dynamic address learning and forward command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] learning status
+ * @param[out] forward command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_port_learning_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_port_learning_ctrl_get(dev_id, port_id, enable, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set station move learning and forward command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] learning status
+ * @param[in] forward command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_port_stamove_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_port_stamove_ctrl_set(dev_id, port_id, enable, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_FDB_MINI
+/**
+ * @brief Get station move learning and forward command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] learning status
+ * @param[out] forward command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_port_stamove_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_port_stamove_ctrl_get(dev_id, port_id, enable, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set dynamic address aging status on particular device.
+ *   @details  Comments:
+ *       This operation will enable or disable dynamic address aging
+ *       feature on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_aging_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_aging_ctrl_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_FDB_MINI
+/**
+ * @brief Get dynamic address aging status on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_aging_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_aging_ctrl_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief set arl search mode as ivl or svl when vlan invalid.
+ * @param[in] dev_id device id
+ * @param[in] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_vlan_ivl_svl_set(dev_id, smode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief get arl search mode when vlan invalid.
+ * @param[in] dev_id device id
+ * @param[out] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_vlan_ivl_svl_get(dev_id, smode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+
+
+/**
+ * @brief Set dynamic address aging time on a particular device.
+ * @details   Comments:
+ *       This operation will set dynamic address aging time on a particular device.
+ *       The unit of time is second. Because different device has differnet
+ *       hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param time aging time
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_aging_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_aging_time_set(dev_id, time);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address aging time on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_aging_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_aging_time_get(dev_id, time);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Iterate all fdb entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] iterator fdb entry index if it's zero means get the first entry
+ * @param[out] iterator next valid fdb entry index
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_entry_getnext_byindex(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_entry_getnext_byindex(dev_id, iterator, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get next Fdb entry from a particular device
+ * @param[in] dev_id device id
+ * @param[in] option next operation options
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_entry_extend_getnext(a_uint32_t dev_id, fal_fdb_op_t * option,
+                    fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_entry_extend_getnext(dev_id, option, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from a particular device
+ * @param[in] dev_id device id
+ * @param[in] option first operation options
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_entry_extend_getfirst(a_uint32_t dev_id, fal_fdb_op_t * option,
+                     fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_entry_extend_getfirst(dev_id, option, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_FDB_MINI
+/**
+ * @brief Transfer fdb entries port information on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] old_port source port id
+ * @param[in] new_port destination port id
+ * @param[in] fid filter database id
+ * @param[in] option transfer operation options
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_entry_update_byport(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+                 a_uint32_t fid, fal_fdb_op_t * option)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_entry_update_byport(dev_id, old_port, new_port, fid, option);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_fdb_learn_limit_set(dev_id, port_id, enable, cnt);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] cnt limit count
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_fdb_learn_limit_get(dev_id, port_id, enable, cnt);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count limit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_learn_limit_set(dev_id, enable, cnt);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count limit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_learn_limit_get(dev_id, enable, cnt);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count exceed command on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_learn_exceed_cmd_set(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count exceed command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_learn_exceed_cmd_get(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a particular reserve Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_resv_add(dev_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a particular reserve Fdb entry through mac address
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_resv_del(dev_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a particular reserve Fdb entry through mac address
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @param[out] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_resv_find(dev_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Iterate all reserve fdb entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] iterator reserve fdb entry index if it's zero means get the first entry
+ * @param[out] iterator next valid fdb entry index
+ * @param[out] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+                     fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_resv_iterate(dev_id, iterator, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_port_learn_static_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_port_learn_static_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a port to an exsiting entry
+ * @param[in] dev_id device id
+ * @param[in] fid filtering database id
+ * @param[in] addr MAC address
+ * @param[in] port_id port id
+ * @return SW_OK or error code, If entry not exist will return error.
+ */
+sw_error_t
+fal_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_port_add(dev_id, fid, addr, port_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a port from an exsiting entry
+ * @param[in] dev_id device id
+ * @param[in] fid filtering database id
+ * @param[in] addr MAC address
+ * @param[in] port_id port id
+ * @return SW_OK or error code, If entry not exist will return error.
+ */
+sw_error_t
+fal_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_port_del(dev_id, fid, addr, port_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a Fdb rfs entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_rfs_set(a_uint32_t dev_id, const fal_fdb_rfs_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_rfs_set(dev_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Del a Fdb rfs entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_rfs_del(a_uint32_t dev_id, const fal_fdb_rfs_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_rfs_del(dev_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+int ssdk_rfs_mac_rule_set(u16 vid, u8* mac, u8 ldb, int is_set)
+{
+	fal_fdb_rfs_t entry;
+	memcpy(&entry.addr, mac, 6);
+	entry.fid = vid;
+	entry.load_balance = ldb;
+	if(is_set)
+		return fal_fdb_rfs_set(0, &entry);
+	else
+		return fal_fdb_rfs_del(0, &entry);
+}
+#endif
+
+#if 0
+int ssdk_rfs_mac_rule_set(ssdk_fdb_rfs_t *rfs)
+{
+	fal_fdb_rfs_t entry;
+	memcpy(&entry.addr, rfs->addr, 6);
+	entry.fid = rfs->fid;
+	entry.load_balance = rfs->load_balance;
+	return fal_fdb_rfs_set(0, &entry);
+}
+
+int ssdk_rfs_mac_rule_del(ssdk_fdb_rfs_t *rfs)
+{
+	fal_fdb_rfs_t entry;
+	memcpy(&entry.addr, rfs->addr, 6);
+	entry.fid = rfs->fid;
+	entry.load_balance = rfs->load_balance;
+	return fal_fdb_rfs_del(0, &entry);
+}
+
+
+EXPORT_SYMBOL(ssdk_rfs_mac_rule_set);
+EXPORT_SYMBOL(ssdk_rfs_mac_rule_del);
+#endif
+
+sw_error_t
+fal_fdb_learning_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_learning_ctrl_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_FDB_MINI
+sw_error_t
+fal_fdb_learning_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_learning_ctrl_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_fdb_port_learned_mac_counter_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t * cnt)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_port_learned_mac_counter_get(dev_id, port_id, cnt);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_fdb_port_maclimit_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_port_maclimit_ctrl_set(dev_id, port_id, maclimit_ctrl);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_fdb_port_maclimit_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_port_maclimit_ctrl_get(dev_id, port_id, maclimit_ctrl);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+sw_error_t
+fal_fdb_entry_del_byfid(a_uint32_t dev_id, a_uint16_t fid, a_uint32_t flag)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_fdb_entry_del_byfid(dev_id, fid, flag);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_FDB_MINI
+
+    EXPORT_SYMBOL(fal_fdb_entry_add);
+
+#endif
+
+    EXPORT_SYMBOL(fal_fdb_entry_del_byport);
+
+
+    EXPORT_SYMBOL(fal_fdb_entry_del_bymac);
+
+
+    EXPORT_SYMBOL(fal_fdb_entry_search);
+
+#ifndef IN_FDB_MINI
+
+    EXPORT_SYMBOL(fal_fdb_port_learn_get);
+
+#endif
+
+    EXPORT_SYMBOL(fal_fdb_port_learning_ctrl_set);
+
+    EXPORT_SYMBOL(fal_fdb_entry_flush);
+
+    EXPORT_SYMBOL(fal_fdb_entry_getfirst);
+
+#ifndef IN_FDB_MINI
+
+    EXPORT_SYMBOL(fal_fdb_entry_getnext);
+
+#endif
+
+    EXPORT_SYMBOL(fal_fdb_port_learn_set);
+
+    EXPORT_SYMBOL(fal_fdb_learning_ctrl_set);
+
+#ifndef IN_FDB_MINI
+
+    EXPORT_SYMBOL(fal_fdb_learning_ctrl_get);
+
+#endif
+
+    EXPORT_SYMBOL(fal_fdb_entry_getnext_byindex);
+
+    EXPORT_SYMBOL(fal_fdb_entry_extend_getnext);
+
+    EXPORT_SYMBOL(fal_fdb_entry_extend_getfirst);
+
+#ifndef IN_FDB_MINI
+
+    EXPORT_SYMBOL(fal_fdb_port_learning_ctrl_get);
+
+#endif
+
+    EXPORT_SYMBOL(fal_fdb_port_stamove_ctrl_set);
+
+#ifndef IN_FDB_MINI
+
+    EXPORT_SYMBOL(fal_fdb_port_stamove_ctrl_get);
+
+#endif
+
+    EXPORT_SYMBOL(fal_fdb_aging_ctrl_set);
+
+#ifndef IN_FDB_MINI
+
+    EXPORT_SYMBOL(fal_fdb_aging_ctrl_get);
+
+    EXPORT_SYMBOL(fal_fdb_aging_time_set);
+
+    EXPORT_SYMBOL(fal_fdb_aging_time_get);
+
+    EXPORT_SYMBOL(fal_fdb_entry_update_byport);
+
+    EXPORT_SYMBOL(fal_port_fdb_learn_limit_set);
+
+    EXPORT_SYMBOL(fal_port_fdb_learn_limit_get);
+
+    EXPORT_SYMBOL(fal_port_fdb_learn_exceed_cmd_set);
+
+    EXPORT_SYMBOL(fal_port_fdb_learn_exceed_cmd_get);
+
+    EXPORT_SYMBOL(fal_fdb_port_add);
+
+    EXPORT_SYMBOL(fal_fdb_port_del);
+
+    EXPORT_SYMBOL(fal_fdb_port_maclimit_ctrl_set);
+
+    EXPORT_SYMBOL(fal_fdb_port_maclimit_ctrl_get);
+
+#endif
+
+    EXPORT_SYMBOL(fal_fdb_entry_del_byfid);
+
+#ifndef IN_FDB_MINI
+
+    EXPORT_SYMBOL(fal_fdb_port_learned_mac_counter_get);
+
+#endif
+
+/*insert flag for outter fal, don't remove it*/
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/fal/fal_flow.c b/qca-ssdk/src/fal/fal_flow.c
new file mode 100755
index 0000000..4178e7d
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_flow.c
@@ -0,0 +1,467 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_flow FAL_FLOW
+ * @{
+ */
+#include "sw.h"
+#include "fal_flow.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#ifndef IN_FLOW_MINI
+sw_error_t
+_fal_flow_host_add(
+		a_uint32_t dev_id,
+		a_uint32_t add_mode,
+		fal_flow_host_entry_t *flow_host_entry)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_flow_host_add)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_flow_host_add(dev_id, add_mode, flow_host_entry);
+	return rv;
+}
+sw_error_t
+_fal_flow_entry_get(
+		a_uint32_t dev_id,
+		a_uint32_t get_mode,
+		fal_flow_entry_t *flow_entry)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_flow_entry_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_flow_entry_get(dev_id, get_mode, flow_entry);
+	return rv;
+}
+sw_error_t
+_fal_flow_entry_del(
+		a_uint32_t dev_id,
+		a_uint32_t del_mode,
+		fal_flow_entry_t *flow_entry)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_flow_entry_del)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_flow_entry_del(dev_id, del_mode, flow_entry);
+	return rv;
+}
+sw_error_t
+_fal_flow_entry_next(
+		a_uint32_t dev_id,
+		a_uint32_t next_mode,
+		fal_flow_entry_t *flow_entry)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_flow_entry_next)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_flow_entry_next(dev_id, next_mode, flow_entry);
+	return rv;
+}
+sw_error_t
+_fal_flow_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_flow_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_flow_status_get(dev_id, enable);
+	return rv;
+}
+#endif
+sw_error_t
+_fal_flow_mgmt_set(
+		a_uint32_t dev_id,
+		fal_flow_pkt_type_t type,
+		fal_flow_direction_t dir,
+		fal_flow_mgmt_t *mgmt)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_flow_ctrl_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_flow_ctrl_set(dev_id, type, dir, mgmt);
+	return rv;
+}
+#ifndef IN_FLOW_MINI
+sw_error_t
+_fal_flow_age_timer_get(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_flow_age_timer_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_flow_age_timer_get(dev_id, age_timer);
+	return rv;
+}
+sw_error_t
+_fal_flow_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_flow_status_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_flow_status_set(dev_id, enable);
+	return rv;
+}
+sw_error_t
+_fal_flow_host_get(
+		a_uint32_t dev_id,
+		a_uint32_t get_mode,
+		fal_flow_host_entry_t *flow_host_entry)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_flow_host_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_flow_host_get(dev_id, get_mode, flow_host_entry);
+	return rv;
+}
+sw_error_t
+_fal_flow_host_del(
+		a_uint32_t dev_id,
+		a_uint32_t del_mode,
+		fal_flow_host_entry_t *flow_host_entry)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_flow_host_del)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_flow_host_del(dev_id, del_mode, flow_host_entry);
+	return rv;
+}
+#endif
+sw_error_t
+_fal_flow_mgmt_get(
+		a_uint32_t dev_id,
+		fal_flow_pkt_type_t type,
+		fal_flow_direction_t dir,
+		fal_flow_mgmt_t *mgmt)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_flow_ctrl_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_flow_ctrl_get(dev_id, type, dir, mgmt);
+	return rv;
+}
+#ifndef IN_FLOW_MINI
+sw_error_t
+_fal_flow_age_timer_set(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_flow_age_timer_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_flow_age_timer_set(dev_id, age_timer);
+	return rv;
+}
+sw_error_t
+_fal_flow_entry_add(
+		a_uint32_t dev_id,
+		a_uint32_t add_mode, /*index or hash*/
+		fal_flow_entry_t *flow_entry)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_flow_entry_add)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_flow_entry_add(dev_id, add_mode, flow_entry);
+	return rv;
+}
+
+sw_error_t
+_fal_flow_global_cfg_get(
+		a_uint32_t dev_id,
+		fal_flow_global_cfg_t *cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_flow_global_cfg_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_flow_global_cfg_get(dev_id, cfg);
+	return rv;
+}
+
+sw_error_t
+_fal_flow_global_cfg_set(
+		a_uint32_t dev_id,
+		fal_flow_global_cfg_t *cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_flow_global_cfg_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_flow_global_cfg_set(dev_id, cfg);
+	return rv;
+}
+/*insert flag for inner fal, don't remove it*/
+
+sw_error_t
+fal_flow_host_add(
+		a_uint32_t dev_id,
+		a_uint32_t add_mode,
+		fal_flow_host_entry_t *flow_host_entry)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_flow_host_add(dev_id, add_mode, flow_host_entry);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_flow_entry_get(
+		a_uint32_t dev_id,
+		a_uint32_t get_mode,
+		fal_flow_entry_t *flow_entry)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_flow_entry_get(dev_id, get_mode, flow_entry);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_flow_entry_del(
+		a_uint32_t dev_id,
+		a_uint32_t del_mode,
+		fal_flow_entry_t *flow_entry)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_flow_entry_del(dev_id, del_mode, flow_entry);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_flow_entry_next(
+		a_uint32_t dev_id,
+		a_uint32_t next_mode,
+		fal_flow_entry_t *flow_entry)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_flow_entry_next(dev_id, next_mode, flow_entry);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_flow_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_flow_status_get(dev_id, enable);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#endif
+sw_error_t
+fal_flow_mgmt_set(
+		a_uint32_t dev_id,
+		fal_flow_pkt_type_t type,
+		fal_flow_direction_t dir,
+		fal_flow_mgmt_t *mgmt)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_flow_mgmt_set(dev_id, type, dir, mgmt);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#ifndef IN_FLOW_MINI
+sw_error_t
+fal_flow_age_timer_get(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_flow_age_timer_get(dev_id, age_timer);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_flow_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_flow_status_set(dev_id, enable);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_flow_host_get(
+		a_uint32_t dev_id,
+		a_uint32_t get_mode,
+		fal_flow_host_entry_t *flow_host_entry)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_flow_host_get(dev_id, get_mode, flow_host_entry);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_flow_host_del(
+		a_uint32_t dev_id,
+		a_uint32_t del_mode,
+		fal_flow_host_entry_t *flow_host_entry)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_flow_host_del(dev_id, del_mode, flow_host_entry);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#endif
+sw_error_t
+fal_flow_mgmt_get(
+		a_uint32_t dev_id,
+		fal_flow_pkt_type_t type,
+		fal_flow_direction_t dir,
+		fal_flow_mgmt_t *mgmt)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_flow_mgmt_get(dev_id, type, dir, mgmt);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#ifndef IN_FLOW_MINI
+sw_error_t
+fal_flow_age_timer_set(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_flow_age_timer_set(dev_id, age_timer);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_flow_entry_add(
+		a_uint32_t dev_id,
+		a_uint32_t add_mode, /*index or hash*/
+		fal_flow_entry_t *flow_entry)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_flow_entry_add(dev_id, add_mode, flow_entry);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_flow_global_cfg_get(
+		a_uint32_t dev_id,
+		fal_flow_global_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_flow_global_cfg_get(dev_id, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_flow_global_cfg_set(
+		a_uint32_t dev_id,
+		fal_flow_global_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_flow_global_cfg_set(dev_id, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#endif
+/*insert flag for outter fal, don't remove it*/
diff --git a/qca-ssdk/src/fal/fal_igmp.c b/qca-ssdk/src/fal/fal_igmp.c
new file mode 100755
index 0000000..c861fc8
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_igmp.c
@@ -0,0 +1,961 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+* @defgroup fal_igmp FAL_IGMP
+* @{
+*/
+#include "sw.h"
+#include "fal_igmp.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_igmps_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_igmps_status_set(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_igmps_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_igmps_status_get(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_mld_cmd_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_mld_cmd_set(dev_id, cmd);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_mld_cmd_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_mld_cmd_get(dev_id, cmd);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_igmp_join_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_igmp_join_set(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_igmp_join_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_igmp_join_get(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_igmp_leave_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_igmp_leave_set(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_igmp_leave_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_igmp_leave_get(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_rp_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_rp_set(dev_id, pts);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_rp_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_rp_get(dev_id, pts);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_entry_creat_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_entry_creat_set(dev_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_entry_creat_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_entry_creat_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_entry_static_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_entry_static_set(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_entry_static_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_entry_static_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_entry_leaky_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_entry_leaky_set(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_entry_leaky_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_entry_leaky_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_entry_v3_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_entry_v3_set(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_entry_v3_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_entry_v3_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_entry_queue_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_entry_queue_set(dev_id, enable, queue);
+    return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_entry_queue_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_entry_queue_get(dev_id, enable, queue);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_igmp_mld_learn_limit_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_igmp_mld_learn_limit_set(dev_id, port_id, enable, cnt);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_igmp_mld_learn_limit_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_igmp_mld_learn_limit_get(dev_id, port_id, enable, cnt);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                        fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_igmp_mld_learn_exceed_cmd_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_igmp_mld_learn_exceed_cmd_set(dev_id, port_id, cmd);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                        fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_igmp_mld_learn_exceed_cmd_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_igmp_mld_learn_exceed_cmd_get(dev_id, port_id, cmd);
+    return rv;
+}
+
+static sw_error_t
+_fal_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_sg_entry_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_sg_entry_set(dev_id, entry);
+    return rv;
+}
+static sw_error_t
+_fal_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_sg_entry_clear)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_sg_entry_clear(dev_id, entry);
+    return rv;
+}
+static sw_error_t
+_fal_igmp_sg_entry_show(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_sg_entry_show)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_sg_entry_show(dev_id);
+    return rv;
+}
+static sw_error_t
+_fal_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t * info)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->igmp_sg_entry_query)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->igmp_sg_entry_query(dev_id, info);
+    return rv;
+}
+/**
+ * @brief Set igmp/mld packets snooping status on a particular port.
+ * @details    Comments:
+ *   After enabling igmp/mld snooping feature on a particular port all kinds
+ *   igmp/mld packets received on this port would be acknowledged by hardware.
+ *   Particular forwarding decision could be setted by fal_igmp_mld_cmd_set.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_igmps_status_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets snooping status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_igmps_status_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld packets forwarding command on a particular device.
+ * @details    Comments:
+ *    Particular device may only support parts of forwarding commands.
+ *    This operation will take effect only after enabling igmp/mld snooping
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_mld_cmd_set(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_mld_cmd_get(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld join packets hardware acknowledgement status on particular port.
+ * @details    Comments:
+ *    After enabling igmp/mld join feature on a particular port hardware will
+ *    dynamic learning or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_igmp_mld_join_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_igmp_mld_join_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @details    Comments:
+ *    After enabling igmp join feature on a particular port hardware will dynamic
+ *    deleting or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_igmp_mld_leave_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_igmp_mld_leave_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld router ports on a particular device.
+ * @details     Comments:
+ *    After enabling igmp/mld join/leave feature on a particular port igmp/mld
+ *    join/leave packets received on this port will be forwarded to router ports.
+ * @param[in] dev_id device id
+ * @param[in] pts dedicates ports
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_mld_rp_set(dev_id, pts);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld router ports on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] pts dedicates ports
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_mld_rp_get(dev_id, pts);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   entry creat hardware will dynamic creat and delete multicast entry,
+ *   otherwise hardware only can change destination ports of existing muticast entry.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_mld_entry_creat_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_mld_entry_creat_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the static status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   static status hardware will not age out multicast entry which leardned by hardware,
+ *   otherwise hardware will age out multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_mld_entry_static_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the static status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_mld_entry_static_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the leaky status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   leaky status hardware will set leaky flag of multicast entry which leardned by hardware,
+ *   otherwise hardware will not set leaky flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_mld_entry_leaky_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the leaky status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_mld_entry_leaky_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @details    Comments:
+ *    After enabling igmp join/leave feature on a particular port hardware will dynamic
+ *    creating or changing multicast entry after receiving igmpv3/mldv2 packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_mld_entry_v3_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_mld_entry_v3_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the queue status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   leaky status hardware will set queue flag of multicast entry which leardned by hardware,
+ *   otherwise hardware will not set queue flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_mld_entry_queue_set(dev_id, enable, queue);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the queue status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_mld_entry_queue_get(dev_id, enable, queue);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IGMP hardware learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_igmp_mld_learn_limit_set(dev_id, port_id, enable, cnt);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IGMP hardware learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] cnt limit count
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_igmp_mld_learn_limit_get(dev_id, port_id, enable, cnt);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IGMP hardware learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                       fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_igmp_mld_learn_exceed_cmd_set(dev_id, port_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IGMP hardware learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                       fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_igmp_mld_learn_exceed_cmd_get(dev_id, port_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_sg_entry_set(dev_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_sg_entry_clear(dev_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_igmp_sg_entry_show(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_sg_entry_show(dev_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t * info)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_igmp_sg_entry_query(dev_id, info);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/fal/fal_init.c b/qca-ssdk/src/fal/fal_init.c
new file mode 100755
index 0000000..d5348e0
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_init.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*qca808x_start*/
+/**
+ * @defgroup fal_init FAL_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_api.h"
+/*qca808x_end*/
+#include "fal_vlan.h"
+#include "adpt.h"
+/*qca808x_start*/
+/**
+ * @brief Init fal layer.
+ * @details Comments:
+ *   This operation will init fal layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    sw_error_t rv;
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = hsl_api_init(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = hsl_dev_init(dev_id, cfg);
+    SW_RTN_ON_ERROR(rv);
+/*qca808x_end*/
+#ifdef IN_VLAN
+    rv = fal_vlan_init(dev_id);
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+    rv = adpt_init(dev_id, cfg);
+    SW_RTN_ON_ERROR(rv);
+/*qca808x_start*/
+
+    return rv;
+}
+/*qca808x_end*/
+
+static sw_error_t
+_fal_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->dev_reset)
+        return SW_NOT_SUPPORTED;
+
+#ifdef IN_VLAN
+    rv = fal_vlan_reset(dev_id);
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+    rv = p_api->dev_reset(dev_id);
+    return rv;
+}
+
+static sw_error_t
+_fal_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg)
+{
+    sw_error_t rv;
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = hsl_ssdk_cfg(dev_id, ssdk_cfg);
+
+    return rv;
+}
+
+static sw_error_t
+_fal_module_func_ctrl_set(a_uint32_t dev_id, a_uint32_t module, fal_func_ctrl_t *func_ctrl)
+{
+    return adpt_module_func_ctrl_set(dev_id, module, func_ctrl);
+}
+
+static sw_error_t
+_fal_module_func_ctrl_get(a_uint32_t dev_id, a_uint32_t module, fal_func_ctrl_t *func_ctrl)
+{
+    return adpt_module_func_ctrl_get(dev_id, module, func_ctrl);
+}
+/*qca808x_start*/
+sw_error_t
+fal_cleanup(void)
+{
+    sw_error_t rv;
+
+    rv = hsl_dev_cleanup();
+    SW_RTN_ON_ERROR(rv);
+/*qca808x_end*/
+#ifdef IN_VLAN
+    rv = fal_vlan_cleanup();
+    SW_RTN_ON_ERROR(rv);
+#endif
+/*qca808x_start*/
+    return SW_OK;
+}
+/*qca808x_end*/
+/**
+ * @brief Reset fal layer.
+ * @details Comments:
+ *   This operation will reset fal layer and hsl layer
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_reset(dev_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get SSDK config infomation.
+ * @param[in] dev_id device id
+ * @param[out] ssdk_cfg SSDK config infomation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ssdk_cfg(dev_id, ssdk_cfg);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_switch_devid_get(ssdk_chip_type chip_type, a_uint32_t *pdev_id)
+{
+	sw_error_t rv = SW_OK;
+	ssdk_cfg_t cfg = {{0}};
+	a_uint32_t dev_id = 0;
+
+	for(dev_id = 0; dev_id < SW_MAX_NR_DEV; dev_id++) {
+		rv = _fal_ssdk_cfg(dev_id, &cfg);
+		if(rv == SW_OK && cfg.init_cfg.chip_type == chip_type) {
+			*pdev_id = dev_id;
+			return rv;
+		}
+	}
+	return SW_FAIL;
+}
+
+sw_error_t
+fal_module_func_ctrl_set(a_uint32_t dev_id, a_uint32_t module, fal_func_ctrl_t *func_ctrl)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_module_func_ctrl_set(dev_id, module, func_ctrl);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_module_func_ctrl_get(a_uint32_t dev_id, a_uint32_t module, fal_func_ctrl_t *func_ctrl)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_module_func_ctrl_get(dev_id, module, func_ctrl);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_module_func_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    sw_error_t rv;
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = adpt_module_func_init(dev_id, cfg);
+    SW_RTN_ON_ERROR(rv);
+
+    return rv;
+}
+
+EXPORT_SYMBOL(fal_switch_devid_get);
+EXPORT_SYMBOL(fal_module_func_ctrl_set);
+EXPORT_SYMBOL(fal_module_func_ctrl_get);
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/fal/fal_interface_ctrl.c b/qca-ssdk/src/fal/fal_interface_ctrl.c
new file mode 100755
index 0000000..85cc100
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_interface_ctrl.c
@@ -0,0 +1,386 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_interface_ctrl FAL_INTERFACE_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "fal_interface_ctrl.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_3az_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_3az_status_set(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_3az_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_3az_status_get(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->interface_mac_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->interface_mac_mode_set(dev_id, port_id, config);
+    return rv;
+}
+
+static sw_error_t
+_fal_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->interface_mac_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->interface_mac_mode_get(dev_id, port_id, config);
+    return rv;
+}
+
+static sw_error_t
+_fal_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->interface_phy_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->interface_phy_mode_set(dev_id, phy_id, config);
+    return rv;
+}
+
+static sw_error_t
+_fal_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->interface_phy_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->interface_phy_mode_get(dev_id, phy_id, config);
+    return rv;
+}
+
+static sw_error_t
+_fal_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->interface_fx100_ctrl_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->interface_fx100_ctrl_set(dev_id, config);
+    return rv;
+}
+
+static sw_error_t
+_fal_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->interface_fx100_ctrl_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->interface_fx100_ctrl_get(dev_id, config);
+    return rv;
+}
+
+static sw_error_t
+_fal_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->interface_fx100_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->interface_fx100_status_get(dev_id, status);
+    return rv;
+}
+
+static sw_error_t
+_fal_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->interface_mac06_exch_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->interface_mac06_exch_set(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->interface_mac06_exch_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->interface_mac06_exch_get(dev_id, enable);
+    return rv;
+}
+
+/**
+  * @brief Set 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_3az_status_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Get 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_3az_status_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Set interface mode on a particular MAC device.
+ * @param[in] dev_id device id
+ * @param[in] mca_id MAC device ID
+ * @param[in] config interface configuration
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_interface_mac_mode_set(dev_id, port_id, config);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Get interface mode on a particular MAC device.
+ * @param[in] dev_id device id
+ * @param[in] mca_id MAC device ID
+ * @param[out] config interface configuration
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_interface_mac_mode_get(dev_id, port_id, config);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Set interface phy mode on a particular PHY device.
+ * @param[in] dev_id device id
+ * @param[in] phy_id PHY device ID
+ * @param[in] config interface configuration
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_interface_phy_mode_set(dev_id, phy_id, config);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Get interface phy mode on a particular PHY device.
+ * @param[in] dev_id device id
+ * @param[in] phy_id PHY device ID
+ * @param[out] config interface configuration
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_interface_phy_mode_get(dev_id, phy_id, config);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Set fx100 control configuration.
+ * @param[in] dev_id device id
+ * @param[in] config fx100 control configuration
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_fx100_ctrl_set(a_uint32_t dev_id,  fal_fx100_ctrl_config_t * config)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_interface_fx100_ctrl_set(dev_id, config);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+/**
+  * @brief Get fx100 control configuration.
+ * @param[in] dev_id device id
+ * @param[out] config fx100 control configuration
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_fx100_ctrl_get(a_uint32_t dev_id,  fal_fx100_ctrl_config_t * config)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_interface_fx100_ctrl_get(dev_id, config);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Get fx100 control configuration.
+ * @param[in] dev_id device id
+ * @param[out] fx100 status
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_fx100_status_get(a_uint32_t dev_id,  a_uint32_t* status)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_interface_fx100_status_get(dev_id, status);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+/**
+  * @brief Set mac0 and mac6 exchange status.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_mac06_exch_set(a_uint32_t dev_id,  a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_interface_mac06_exch_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Get mac0 and mac6 exchange status.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_mac06_exch_get(a_uint32_t dev_id,  a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_interface_mac06_exch_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/fal/fal_ip.c b/qca-ssdk/src/fal/fal_ip.c
new file mode 100755
index 0000000..917d312
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_ip.c
@@ -0,0 +1,2370 @@
+/*
+ * Copyright (c) 2012, 2015, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_ip FAL_IP
+ * @{
+ */
+#include "sw.h"
+#include "fal_ip.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#ifndef IN_IP_MINI
+static sw_error_t
+_fal_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_ip_host_add)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_ip_host_add(dev_id, host_entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_host_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_host_add(dev_id, host_entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                 fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_ip_host_del)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_ip_host_del(dev_id, del_mode, host_entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_host_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_host_del(dev_id, del_mode, host_entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                 fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_ip_host_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_ip_host_get(dev_id, get_mode, host_entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_host_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_host_get(dev_id, get_mode, host_entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                  fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_ip_host_next)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_ip_host_next(dev_id, next_mode, host_entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_host_next)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_host_next(dev_id, next_mode, host_entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                          a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_host_counter_bind)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_host_counter_bind(dev_id, entry_id, cnt_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                        a_uint32_t pppoe_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_host_pppoe_bind)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_host_pppoe_bind(dev_id, entry_id, pppoe_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flags)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_pt_arp_learn_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_pt_arp_learn_set(dev_id, port_id, flags);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t * flags)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_pt_arp_learn_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_pt_arp_learn_get(dev_id, port_id, flags);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_arp_learn_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_arp_learn_set(dev_id, mode);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_arp_learn_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_arp_learn_get(dev_id, mode);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_source_guard_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_source_guard_set(dev_id, port_id, mode);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_source_guard_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_source_guard_get(dev_id, port_id, mode);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_unk_source_cmd_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_unk_source_cmd_set(dev_id, cmd);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_unk_source_cmd_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_unk_source_cmd_get(dev_id, cmd);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_arp_guard_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_arp_guard_set(dev_id, port_id, mode);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_arp_guard_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_arp_guard_get(dev_id, port_id, mode);
+    return rv;
+}
+
+static sw_error_t
+_fal_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->arp_unk_source_cmd_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->arp_unk_source_cmd_set(dev_id, cmd);
+    return rv;
+}
+
+static sw_error_t
+_fal_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->arp_unk_source_cmd_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->arp_unk_source_cmd_get(dev_id, cmd);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_route_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_route_status_set(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_route_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_route_status_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_intf_entry_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_intf_entry_add(dev_id, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                       fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_intf_entry_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_intf_entry_del(dev_id, del_mode, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                        fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_intf_entry_next)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_intf_entry_next(dev_id, next_mode, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_age_time_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_age_time_set(dev_id, time);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_age_time_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_age_time_get(dev_id, time);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_wcmp_hash_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_wcmp_hash_mode_set(dev_id, hash_mode);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_wcmp_hash_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_wcmp_hash_mode_get(dev_id, hash_mode);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_vrf_base_addr_set(a_uint32_t dev_id,
+					a_uint32_t vrf_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_vrf_base_addr_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_vrf_base_addr_set(dev_id, vrf_id, addr);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_vrf_base_addr_get(a_uint32_t dev_id,
+					a_uint32_t vrf_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_vrf_base_addr_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_vrf_base_addr_get(dev_id, vrf_id, addr);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_vrf_base_mask_set(a_uint32_t dev_id,
+					a_uint32_t vrf_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_vrf_base_mask_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_vrf_base_mask_set(dev_id, vrf_id, addr);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_vrf_base_mask_get(a_uint32_t dev_id,
+					a_uint32_t vrf_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_vrf_base_mask_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_vrf_base_mask_get(dev_id, vrf_id, addr);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_default_route_set(a_uint32_t dev_id,
+					a_uint32_t droute_id, fal_default_route_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_default_route_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_default_route_set(dev_id, droute_id, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_default_route_get(a_uint32_t dev_id,
+					a_uint32_t droute_id, fal_default_route_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_default_route_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_default_route_get(dev_id, droute_id, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_host_route_set(a_uint32_t dev_id,
+					a_uint32_t hroute_id, fal_host_route_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_host_route_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_host_route_set(dev_id, hroute_id, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_host_route_get(a_uint32_t dev_id,
+					a_uint32_t hroute_id, fal_host_route_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_host_route_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_host_route_get(dev_id, hroute_id, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_wcmp_entry_set(a_uint32_t dev_id,
+					a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_wcmp_entry_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_wcmp_entry_set(dev_id, wcmp_id, wcmp);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_wcmp_entry_get(a_uint32_t dev_id,
+					a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_wcmp_entry_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_wcmp_entry_get(dev_id, wcmp_id, wcmp);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_rfs_ip4_rule_set(a_uint32_t dev_id, fal_ip4_rfs_t * rfs)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_rfs_ip4_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_rfs_ip4_set(dev_id, rfs);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_rfs_ip6_rule_set(a_uint32_t dev_id, fal_ip6_rfs_t * rfs)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_rfs_ip6_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_rfs_ip6_set(dev_id, rfs);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_rfs_ip4_rule_del(a_uint32_t dev_id, fal_ip4_rfs_t * rfs)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_rfs_ip4_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_rfs_ip4_del(dev_id, rfs);
+    return rv;
+}
+
+static sw_error_t
+_fal_ip_rfs_ip6_rule_del(a_uint32_t dev_id, fal_ip6_rfs_t * rfs)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_rfs_ip6_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_rfs_ip6_del(dev_id, rfs);
+    return rv;
+}
+
+static sw_error_t
+_fal_default_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id,
+			fal_flow_type_t type, fal_default_flow_cmd_t cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_default_flow_cmd_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_default_flow_cmd_set(dev_id, vrf_id, type, cmd);
+    return rv;
+}
+
+sw_error_t
+_fal_default_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id,
+			fal_flow_type_t type, fal_default_flow_cmd_t * cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_default_flow_cmd_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_default_flow_cmd_get(dev_id, vrf_id, type, cmd);
+    return rv;
+}
+
+sw_error_t
+_fal_default_rt_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id,
+			fal_flow_type_t type, fal_default_flow_cmd_t cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_default_rt_flow_cmd_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_default_rt_flow_cmd_set(dev_id, vrf_id, type, cmd);
+    return rv;
+}
+
+sw_error_t
+_fal_default_rt_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id,
+			fal_flow_type_t type, fal_default_flow_cmd_t * cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ip_default_rt_flow_cmd_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ip_default_rt_flow_cmd_get(dev_id, vrf_id, type, cmd);
+    return rv;
+}
+
+sw_error_t
+_fal_ip_network_route_get(a_uint32_t dev_id,
+			a_uint32_t index, a_uint8_t type,
+			fal_network_route_entry_t *entry)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_network_route_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_network_route_get(dev_id, index, type, entry);
+    return rv;
+}
+sw_error_t
+_fal_ip_vsi_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_sg_cfg_t *sg_cfg)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_vsi_sg_cfg_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_vsi_sg_cfg_get(dev_id, vsi, sg_cfg);
+    return rv;
+}
+
+sw_error_t
+_fal_ip_network_route_del(a_uint32_t dev_id,
+			a_uint32_t index, a_uint8_t type)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_network_route_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_network_route_del(dev_id, index, type);
+    return rv;
+}
+sw_error_t
+_fal_ip_port_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_sg_cfg_t *sg_cfg)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_port_sg_cfg_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_port_sg_cfg_set(dev_id, port_id, sg_cfg);
+    return rv;
+}
+sw_error_t
+_fal_ip_port_intf_get(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_port_intf_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_port_intf_get(dev_id, port_id, id);
+    return rv;
+}
+sw_error_t
+_fal_ip_vsi_arp_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_arp_sg_cfg_t *arp_sg_cfg)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_vsi_arp_sg_cfg_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_vsi_arp_sg_cfg_set(dev_id, vsi, arp_sg_cfg);
+    return rv;
+}
+sw_error_t
+_fal_ip_pub_addr_get(a_uint32_t dev_id,
+		a_uint32_t index, fal_ip_pub_addr_t *entry)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_pub_addr_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_pub_addr_get(dev_id, index, entry);
+    return rv;
+}
+sw_error_t
+_fal_ip_port_intf_set(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_port_intf_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_port_intf_set(dev_id, port_id, id);
+    return rv;
+}
+sw_error_t
+_fal_ip_vsi_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_sg_cfg_t *sg_cfg)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_vsi_sg_cfg_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_vsi_sg_cfg_set(dev_id, vsi, sg_cfg);
+    return rv;
+}
+sw_error_t
+_fal_ip_port_macaddr_set(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_macaddr_entry_t *macaddr)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_port_macaddr_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_port_macaddr_set(dev_id, port_id, macaddr);
+    return rv;
+}
+sw_error_t
+_fal_ip_vsi_intf_get(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_vsi_intf_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_vsi_intf_get(dev_id, vsi, id);
+    return rv;
+}
+
+sw_error_t
+_fal_ip_network_route_add(a_uint32_t dev_id,
+			a_uint32_t index,
+			fal_network_route_entry_t *entry)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_network_route_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_network_route_add(dev_id, index, entry);
+    return rv;
+}
+sw_error_t
+_fal_ip_port_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_sg_cfg_t *sg_cfg)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_port_sg_cfg_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_port_sg_cfg_get(dev_id, port_id, sg_cfg);
+    return rv;
+}
+sw_error_t
+_fal_ip_intf_get(
+    			a_uint32_t dev_id,
+    			a_uint32_t index,
+    			fal_intf_entry_t *entry)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_intf_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_intf_get(dev_id, index, entry);
+    return rv;
+}
+sw_error_t
+_fal_ip_pub_addr_set(a_uint32_t dev_id,
+		a_uint32_t index, fal_ip_pub_addr_t *entry)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_pub_addr_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_pub_addr_set(dev_id, index, entry);
+    return rv;
+}
+sw_error_t
+_fal_ip_route_mismatch_get(a_uint32_t dev_id, fal_fwd_cmd_t *cmd)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_route_mismatch_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_route_mismatch_get(dev_id, cmd);
+    return rv;
+}
+sw_error_t
+_fal_ip_vsi_arp_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_arp_sg_cfg_t *arp_sg_cfg)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_vsi_arp_sg_cfg_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_vsi_arp_sg_cfg_get(dev_id, vsi, arp_sg_cfg);
+    return rv;
+}
+sw_error_t
+_fal_ip_port_arp_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_arp_sg_cfg_t *arp_sg_cfg)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_port_arp_sg_cfg_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_port_arp_sg_cfg_set(dev_id, port_id, arp_sg_cfg);
+    return rv;
+}
+sw_error_t
+_fal_ip_vsi_mc_mode_set(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_mc_mode_cfg_t *cfg)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_vsi_mc_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_vsi_mc_mode_set(dev_id, vsi, cfg);
+    return rv;
+}
+sw_error_t
+_fal_ip_vsi_intf_set(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_vsi_intf_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_vsi_intf_set(dev_id, vsi, id);
+    return rv;
+}
+sw_error_t
+_fal_ip_nexthop_get(a_uint32_t dev_id, a_uint32_t index, fal_ip_nexthop_t *entry)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_nexthop_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_nexthop_get(dev_id, index, entry);
+    return rv;
+}
+sw_error_t
+_fal_ip_route_mismatch_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_route_mismatch_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_route_mismatch_set(dev_id, cmd);
+    return rv;
+}
+sw_error_t
+_fal_ip_intf_set(
+    			a_uint32_t dev_id,
+    			a_uint32_t index,
+    			fal_intf_entry_t *entry)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_intf_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_intf_set(dev_id, index, entry);
+    return rv;
+}
+sw_error_t
+_fal_ip_vsi_mc_mode_get(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_mc_mode_cfg_t *cfg)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_vsi_mc_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_vsi_mc_mode_get(dev_id, vsi, cfg);
+    return rv;
+}
+sw_error_t
+_fal_ip_port_macaddr_get(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_macaddr_entry_t *macaddr)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_port_macaddr_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_port_macaddr_get(dev_id, port_id, macaddr);
+    return rv;
+}
+sw_error_t
+_fal_ip_port_arp_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_arp_sg_cfg_t *arp_sg_cfg)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_port_arp_sg_cfg_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_port_arp_sg_cfg_get(dev_id, port_id, arp_sg_cfg);
+    return rv;
+}
+sw_error_t
+_fal_ip_nexthop_set(a_uint32_t dev_id,
+			a_uint32_t index, fal_ip_nexthop_t *entry)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_ip_nexthop_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_ip_nexthop_set(dev_id, index, entry);
+    return rv;
+}
+
+sw_error_t
+_fal_ip_global_ctrl_set(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ip_global_ctrl_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ip_global_ctrl_set(dev_id, cfg);
+	return rv;
+}
+
+sw_error_t
+_fal_ip_global_ctrl_get(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ip_global_ctrl_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ip_global_ctrl_get(dev_id, cfg);
+	return rv;
+}
+
+/*insert flag for inner fal, don't remove it*/
+
+/**
+ * @brief Add one host entry to one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry added related interface entry and ip6 base address
+       must be set at first.
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_host_add(dev_id, host_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one host entry from one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry deleted related interface entry and ip6 base address
+       must be set atfirst.
+       For del_mode please refer IP entry operation flags.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operation mode
+ * @param[in] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_host_del(dev_id, del_mode, host_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get one host entry from one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry deleted related interface entry and ip6 base address
+       must be set atfirst.
+       For get_mode please refer IP entry operation flags.
+ * @param[in] dev_id device id
+ * @param[in] get_mode get operation mode
+ * @param[out] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_host_get(dev_id, get_mode, host_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next one host entry from one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry deleted related interface entry and ip6 base address
+       must be set atfirst.
+       For next_mode please refer IP entry operation flags.
+       For get the first entry please set entry id as FAL_NEXT_ENTRY_FIRST_ID
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operation mode
+ * @param[out] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                 fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_host_next(dev_id, next_mode, host_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one host entry on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id host entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE means bind, A_FALSE means unbind
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                         a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_host_counter_bind(dev_id, entry_id, cnt_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one pppoe session entry to one host entry on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id host entry id
+ * @param[in] pppoe_id pppoe session entry id
+ * @param[in] enable A_TRUE means bind, A_FALSE means unbind
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                       a_uint32_t pppoe_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_host_pppoe_bind(dev_id, entry_id, pppoe_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets type to learn on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flags)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_pt_arp_learn_set(dev_id, port_id, flags);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets type to learn on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_uint32_t * flags)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_pt_arp_learn_get(dev_id, port_id, flags);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets type to learn on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode learning mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_arp_learn_set(dev_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets type to learn on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode learning mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_arp_learn_get(dev_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ip packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode source guarding mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_source_guard_set(dev_id, port_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ip packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode source guarding mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_source_guard_get(dev_id, port_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set unkonw source ip packets forwarding command on one particular device.
+ *   @details Comments:
+ *     This settin is no meaning when ip source guard not enable
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_unk_source_cmd_set(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unkonw source ip packets forwarding command on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_unk_source_cmd_get(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode source guarding mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_arp_guard_set(dev_id, port_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode source guarding mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_arp_guard_get(dev_id, port_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set unkonw source arp packets forwarding command on one particular device.
+ *   @details Comments:
+ *     This settin is no meaning when arp source guard not enable
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_arp_unk_source_cmd_set(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unkonw source arp packets forwarding command on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_arp_unk_source_cmd_get(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP unicast routing status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_route_status_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP unicast routing status on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_route_status_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one interface entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry interface entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_intf_entry_add(dev_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one interface entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operation mode
+ * @param[in] entry interface entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                      fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_intf_entry_del(dev_id, del_mode, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next one interface entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operation mode
+ * @param[out] entry interface entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                       fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_intf_entry_next(dev_id, next_mode, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP host entry aging time on one particular device.
+ * @details   Comments:
+ *       This operation will set dynamic entry aging time on a particular device.
+ *       The unit of time is second. Because different device has differnet
+ *       hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param[in] time aging time
+ * @param[out] time actual aging time
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_age_time_set(dev_id, time);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP host entry aging time on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_age_time_get(dev_id, time);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP WCMP hash key mode.
+ * @param[in] dev_id device id
+ * @param[in] hash_mode hash mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_wcmp_hash_mode_set(dev_id, hash_mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP WCMP hash key mode.
+ * @param[in] dev_id device id
+ * @param[out] hash_mode hash mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_wcmp_hash_mode_get(dev_id, hash_mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_vrf_base_addr_set(a_uint32_t dev_id,
+                             a_uint32_t vrf_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_vrf_base_addr_set(dev_id, vrf_id, addr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_vrf_base_addr_get(a_uint32_t dev_id,
+                             a_uint32_t vrf_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_vrf_base_addr_get(dev_id, vrf_id, addr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_vrf_base_mask_set(a_uint32_t dev_id,
+                             a_uint32_t vrf_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_vrf_base_mask_set(dev_id, vrf_id, addr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_vrf_base_mask_get(a_uint32_t dev_id,
+                             a_uint32_t vrf_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_vrf_base_mask_get(dev_id, vrf_id, addr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_default_route_set(a_uint32_t dev_id,
+			a_uint32_t droute_id, fal_default_route_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_default_route_set(dev_id, droute_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_default_route_get(a_uint32_t dev_id,
+                             a_uint32_t droute_id, fal_default_route_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_default_route_get(dev_id, droute_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_host_route_set(a_uint32_t dev_id,
+                             a_uint32_t hroute_id, fal_host_route_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_host_route_set(dev_id, hroute_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_host_route_get(a_uint32_t dev_id,
+                             a_uint32_t hroute_id, fal_host_route_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_host_route_get(dev_id, hroute_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id,
+    							fal_ip_wcmp_t * wcmp)
+{
+	sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_wcmp_entry_set(dev_id, wcmp_id, wcmp);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id,
+    							fal_ip_wcmp_t * wcmp)
+{
+	sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_wcmp_entry_get(dev_id, wcmp_id, wcmp);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_rfs_ip4_rule_set(a_uint32_t dev_id, fal_ip4_rfs_t * rfs)
+{
+	sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_rfs_ip4_rule_set(dev_id, rfs);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_rfs_ip6_rule_set(a_uint32_t dev_id, fal_ip6_rfs_t * rfs)
+{
+	sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_rfs_ip6_rule_set(dev_id, rfs);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_rfs_ip4_rule_del(a_uint32_t dev_id, fal_ip4_rfs_t * rfs)
+{
+	sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_rfs_ip4_rule_del(dev_id, rfs);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_rfs_ip6_rule_del(a_uint32_t dev_id, fal_ip6_rfs_t * rfs)
+{
+	sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_rfs_ip6_rule_del(dev_id, rfs);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+int ssdk_rfs_ip4_rule_set(u16 vid, u32 ip, u8* mac, u8 ldb, int is_set)
+{
+	fal_ip4_rfs_t entry;
+	memcpy(&entry.mac_addr, mac, 6);
+	entry.ip4_addr = ip;
+	entry.load_balance = ldb;
+	entry.vid = vid;
+	if(is_set)
+		return fal_ip_rfs_ip4_rule_set(0, &entry);
+	else
+		return fal_ip_rfs_ip4_rule_del(0, &entry);
+}
+
+int ssdk_rfs_ip6_rule_set(u16 vid, u8* ip, u8* mac, u8 ldb, int is_set)
+{
+	fal_ip6_rfs_t entry;
+	memcpy(&entry.mac_addr, mac, 6);
+	memcpy(&entry.ip6_addr, ip, sizeof(entry.ip6_addr));
+	entry.load_balance = ldb;
+	entry.vid = vid;
+	if(is_set)
+		return fal_ip_rfs_ip6_rule_set(0, &entry);
+	else
+		return fal_ip_rfs_ip6_rule_del(0, &entry);
+}
+
+
+#if 0
+int
+ssdk_ip_rfs_ip4_rule_set(ssdk_ip4_rfs_t * rfs)
+{
+	fal_ip4_rfs_t entry;
+	memcpy(&entry.mac_addr, rfs->mac_addr, 6);
+	entry.ip4_addr = rfs->ip4_addr;
+	entry.load_balance = rfs->load_balance;
+	entry.vid = rfs->vid;
+	return fal_ip_rfs_ip4_rule_set(0, &entry);
+}
+
+int
+ssdk_ip_rfs_ip4_rule_del(ssdk_ip4_rfs_t * rfs)
+{
+	fal_ip4_rfs_t entry;
+	memcpy(&entry.mac_addr, rfs->mac_addr, 6);
+	entry.ip4_addr = rfs->ip4_addr;
+	entry.load_balance = rfs->load_balance;
+	entry.vid = rfs->vid;
+	return fal_ip_rfs_ip4_rule_del(0, &entry);
+}
+
+int
+ssdk_ip_rfs_ip6_rule_set(ssdk_ip6_rfs_t * rfs)
+{
+	fal_ip6_rfs_t entry;
+	memcpy(&entry.mac_addr, rfs->mac_addr, 6);
+	memcpy(&entry.ip6_addr, rfs->ip6_addr, sizeof(rfs->ip6_addr));
+	entry.load_balance = rfs->load_balance;
+	entry.vid = rfs->vid;
+	return fal_ip_rfs_ip6_rule_set(0, &entry);
+}
+
+int
+ssdk_ip_rfs_ip6_rule_del(ssdk_ip6_rfs_t * rfs)
+{
+	fal_ip6_rfs_t entry;
+	memcpy(&entry.mac_addr, rfs->mac_addr, 6);
+	memcpy(&entry.ip6_addr, rfs->ip6_addr, sizeof(rfs->ip6_addr));
+	entry.load_balance = rfs->load_balance;
+	entry.vid = rfs->vid;
+	return fal_ip_rfs_ip6_rule_del(0, &entry);
+}
+
+
+
+EXPORT_SYMBOL(ssdk_ip_rfs_ip4_rule_set);
+EXPORT_SYMBOL(ssdk_ip_rfs_ip4_rule_del);
+EXPORT_SYMBOL(ssdk_ip_rfs_ip6_rule_set);
+EXPORT_SYMBOL(ssdk_ip_rfs_ip6_rule_del);
+#endif
+/**
+ * @brief Set default flow forward command
+ * @param[in] dev_id device id
+ * @param[in] vrf_id VRF route index, from 0~7
+ * @param[in] type traffic flow type pass through switch core
+ * @param[in] fal_default_flow_cmd_t default flow forward command when flow table mismatch
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_default_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id,
+			fal_flow_type_t type, fal_default_flow_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_default_flow_cmd_set(dev_id, vrf_id, type, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flow type traffic default forward command.
+ * @param[in] dev_id device id
+ * @param[in] vrf_id VRF route index, from 0~7
+ * @param[in] type traffic flow type pass through switch core
+ * @param[out] fal_default_flow_cmd_t default flow forward command when flow table mismatch
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_default_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id,
+			fal_flow_type_t type, fal_default_flow_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_default_flow_cmd_get(dev_id, vrf_id, type, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default route flow forward command
+ * @param[in] dev_id device id
+ * @param[in] vrf_id VRF route index, from 0~7
+ * @param[in] type traffic flow type pass through switch core
+ * @param[in] fal_default_flow_cmd_t default route flow forward command when flow table mismatch
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_default_rt_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id,
+			fal_flow_type_t type, fal_default_flow_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_default_rt_flow_cmd_set(dev_id, vrf_id, type, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flow type traffic default forward command.
+ * @param[in] dev_id device id
+ * @param[in] vrf_id VRF route index, from 0~7
+ * @param[in] type traffic flow type pass through switch core
+ * @param[out] fal_default_flow_cmd_t default route flow forward command when flow table mismatch
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_default_rt_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id,
+			fal_flow_type_t type, fal_default_flow_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_default_rt_flow_cmd_get(dev_id, vrf_id, type, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_network_route_get(a_uint32_t dev_id,
+			a_uint32_t index, a_uint8_t type,
+			fal_network_route_entry_t *entry)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_network_route_get(dev_id, index, type, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_vsi_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_sg_cfg_t *sg_cfg)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_vsi_sg_cfg_get(dev_id, vsi, sg_cfg);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_network_route_del(a_uint32_t dev_id,
+			a_uint32_t index, a_uint8_t type)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_network_route_del(dev_id, index, type);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_port_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_sg_cfg_t *sg_cfg)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_port_sg_cfg_set(dev_id, port_id, sg_cfg);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_port_intf_get(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_port_intf_get(dev_id, port_id, id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_vsi_arp_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_arp_sg_cfg_t *arp_sg_cfg)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_vsi_arp_sg_cfg_set(dev_id, vsi, arp_sg_cfg);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_pub_addr_get(a_uint32_t dev_id,
+			a_uint32_t index, fal_ip_pub_addr_t *entry)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_pub_addr_get(dev_id, index, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_port_intf_set(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_port_intf_set(dev_id, port_id, id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_vsi_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_sg_cfg_t *sg_cfg)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_vsi_sg_cfg_set(dev_id, vsi, sg_cfg);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_port_macaddr_set(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_macaddr_entry_t *macaddr)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_port_macaddr_set(dev_id, port_id, macaddr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_vsi_intf_get(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_vsi_intf_get(dev_id, vsi, id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_network_route_add(a_uint32_t dev_id,
+			a_uint32_t index,
+			fal_network_route_entry_t *entry)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_network_route_add(dev_id, index, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_port_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_sg_cfg_t *sg_cfg)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_port_sg_cfg_get(dev_id, port_id, sg_cfg);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_intf_get(
+    			a_uint32_t dev_id,
+    			a_uint32_t index,
+    			fal_intf_entry_t *entry)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_intf_get(dev_id, index, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_pub_addr_set(a_uint32_t dev_id,
+			a_uint32_t index, fal_ip_pub_addr_t *entry)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_pub_addr_set(dev_id, index, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_route_mismatch_action_get(a_uint32_t dev_id, fal_fwd_cmd_t *action)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_route_mismatch_get(dev_id, action);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_vsi_arp_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_arp_sg_cfg_t *arp_sg_cfg)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_vsi_arp_sg_cfg_get(dev_id, vsi, arp_sg_cfg);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_port_arp_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_arp_sg_cfg_t *arp_sg_cfg)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_port_arp_sg_cfg_set(dev_id, port_id, arp_sg_cfg);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_vsi_mc_mode_set(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_mc_mode_cfg_t *cfg)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_vsi_mc_mode_set(dev_id, vsi, cfg);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_vsi_intf_set(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_vsi_intf_set(dev_id, vsi, id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_nexthop_get(a_uint32_t dev_id,
+			a_uint32_t index, fal_ip_nexthop_t *entry)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_nexthop_get(dev_id, index, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_route_mismatch_action_set(a_uint32_t dev_id, fal_fwd_cmd_t action)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_route_mismatch_set(dev_id, action);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_intf_set(
+    			a_uint32_t dev_id,
+    			a_uint32_t index,
+    			fal_intf_entry_t *entry)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_intf_set(dev_id, index, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_vsi_mc_mode_get(a_uint32_t dev_id, a_uint32_t vsi,
+    			fal_mc_mode_cfg_t *cfg)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_vsi_mc_mode_get(dev_id, vsi, cfg);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_port_macaddr_get(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_macaddr_entry_t *macaddr)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_port_macaddr_get(dev_id, port_id, macaddr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_port_arp_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
+    			fal_arp_sg_cfg_t *arp_sg_cfg)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_port_arp_sg_cfg_get(dev_id, port_id, arp_sg_cfg);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_ip_nexthop_set(a_uint32_t dev_id,
+			a_uint32_t index, fal_ip_nexthop_t *entry)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_ip_nexthop_set(dev_id, index, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ip_global_ctrl_set(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ip_global_ctrl_set(dev_id, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_ip_global_ctrl_get(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ip_global_ctrl_get(dev_id, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#endif
+/*insert flag for outter fal, don't remove it*/
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/fal/fal_leaky.c b/qca-ssdk/src/fal/fal_leaky.c
new file mode 100755
index 0000000..db43212
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_leaky.c
@@ -0,0 +1,353 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_leaky FAL_LEAKY
+ * @{
+ */
+#include "sw.h"
+#include "fal_leaky.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_uc_leaky_mode_set(a_uint32_t dev_id, fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->uc_leaky_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->uc_leaky_mode_set(dev_id, ctrl_mode);
+    return rv;
+}
+
+static sw_error_t
+_fal_uc_leaky_mode_get(a_uint32_t dev_id, fal_leaky_ctrl_mode_t * ctrl_mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->uc_leaky_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->uc_leaky_mode_get(dev_id, ctrl_mode);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_mc_leaky_mode_set(a_uint32_t dev_id, fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->mc_leaky_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->mc_leaky_mode_set(dev_id, ctrl_mode);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_mc_leaky_mode_get(a_uint32_t dev_id, fal_leaky_ctrl_mode_t * ctrl_mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->mc_leaky_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->mc_leaky_mode_get(dev_id, ctrl_mode);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_arp_leaky_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_arp_leaky_set(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_arp_leaky_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_arp_leaky_get(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_uc_leaky_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_uc_leaky_set(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_uc_leaky_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_uc_leaky_get(dev_id, port_id, enable);
+    return rv;
+}
+
+
+
+static sw_error_t
+_fal_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_mc_leaky_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_mc_leaky_set(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_mc_leaky_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_mc_leaky_get(dev_id, port_id, enable);
+    return rv;
+}
+/**
+* @brief Set unicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+sw_error_t
+fal_uc_leaky_mode_set(a_uint32_t dev_id, fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_uc_leaky_mode_set(dev_id, ctrl_mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_uc_leaky_mode_get(a_uint32_t dev_id, fal_leaky_ctrl_mode_t * ctrl_mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_uc_leaky_mode_get(dev_id, ctrl_mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Set multicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+sw_error_t
+fal_mc_leaky_mode_set(a_uint32_t dev_id, fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_mc_leaky_mode_set(dev_id, ctrl_mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mc_leaky_mode_get(a_uint32_t dev_id, fal_leaky_ctrl_mode_t * ctrl_mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_mc_leaky_mode_get(dev_id, ctrl_mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_arp_leaky_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_arp_leaky_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_uc_leaky_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_uc_leaky_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_mc_leaky_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_mc_leaky_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/fal/fal_led.c b/qca-ssdk/src/fal/fal_led.c
new file mode 100644
index 0000000..c115875
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_led.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2012, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_led FAL_LED
+ * @{
+ */
+
+#include "sw.h"
+#include "fal_led.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+static sw_error_t
+_fal_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                          led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_led_ctrl_pattern_set != NULL) {
+        rv = p_adpt_api->adpt_led_ctrl_pattern_set(dev_id, group, id, pattern);
+        return rv;
+    }
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->led_ctrl_pattern_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->led_ctrl_pattern_set(dev_id, group, id, pattern);
+    return rv;
+}
+
+
+
+static sw_error_t
+_fal_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                          led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_led_ctrl_pattern_get != NULL) {
+        rv = p_adpt_api->adpt_led_ctrl_pattern_get(dev_id, group, id, pattern);
+        return rv;
+    }
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->led_ctrl_pattern_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->led_ctrl_pattern_get(dev_id, group, id, pattern);
+    return rv;
+}
+
+static sw_error_t
+_fal_led_source_pattern_set(a_uint32_t dev_id, a_uint32_t source_id,
+                          led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_led_ctrl_source_set != NULL) {
+        rv = p_adpt_api->adpt_led_ctrl_source_set(dev_id, source_id, pattern);
+        return rv;
+    }
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->led_ctrl_source_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->led_ctrl_source_set(dev_id, source_id, pattern);
+    return rv;
+}
+
+
+/**
+* @brief Set led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group  pattern group, lan or wan
+* @param[in] id pattern id
+* @param[in] pattern led control pattern
+* @return SW_OK or error code
+*/
+sw_error_t
+fal_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                         led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_led_ctrl_pattern_set(dev_id, group, id, pattern);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Get led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group  pattern group, lan or wan
+* @param[in] id pattern id
+* @param[out] pattern led control pattern
+* @return SW_OK or error code
+*/
+sw_error_t
+fal_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                         led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_led_ctrl_pattern_get(dev_id, group, id, pattern);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Set led control source on a particular device.
+* @param[in] dev_id device id
+* @param[in] source id
+* @param[in] id pattern id
+* @param[in] pattern led control pattern
+* @return SW_OK or error code
+*/
+sw_error_t
+fal_led_source_pattern_set(a_uint32_t dev_id, a_uint32_t source_id,
+                        led_ctrl_pattern_t * pattern)
+{
+	sw_error_t rv;
+
+	FAL_API_LOCK;
+	rv = _fal_led_source_pattern_set(dev_id, source_id, pattern);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/fal/fal_mib.c b/qca-ssdk/src/fal/fal_mib.c
new file mode 100755
index 0000000..0e8b39e
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_mib.c
@@ -0,0 +1,688 @@
+/*
+ * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_mib FAL_MIB
+ * @{
+ */
+
+#include "sw.h"
+#include "fal_mib.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+
+static sw_error_t
+_fal_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                  fal_mib_info_t * mib_Info)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_get_mib_info)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_get_mib_info(dev_id, port_id, mib_Info);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->get_mib_info)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->get_mib_info(dev_id, port_id, mib_Info);
+    return rv;
+}
+
+static sw_error_t
+_fal_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                  fal_mib_info_t * mib_Info)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_get_rx_mib_info)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_get_rx_mib_info(dev_id, port_id, mib_Info);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->get_rx_mib_info)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->get_rx_mib_info(dev_id, port_id, mib_Info);
+    return rv;
+}
+
+static sw_error_t
+_fal_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                  fal_mib_info_t * mib_Info)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_get_tx_mib_info)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_get_tx_mib_info(dev_id, port_id, mib_Info);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->get_tx_mib_info)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->get_tx_mib_info(dev_id, port_id, mib_Info);
+    return rv;
+}
+
+static sw_error_t
+_fal_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_mib_status_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_mib_status_set(dev_id, enable);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->mib_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->mib_status_set(dev_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_mib_status_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_mib_status_get(dev_id, enable);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->mib_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->mib_status_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_mib_port_flush_counters)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_mib_port_flush_counters(dev_id, port_id);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->mib_port_flush_counters)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->mib_port_flush_counters(dev_id, port_id);
+    return rv;
+}
+
+static sw_error_t
+_fal_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_mib_cpukeep_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_mib_cpukeep_set(dev_id, enable);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->mib_cpukeep_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->mib_cpukeep_set(dev_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_mib_cpukeep_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_mib_cpukeep_get(dev_id, enable);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->mib_cpukeep_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->mib_cpukeep_get(dev_id, enable);
+    return rv;
+}
+static sw_error_t
+_fal_get_xgmib_info(a_uint32_t dev_id, fal_port_t port_id,
+                  fal_xgmib_info_t * mib_Info)
+{
+	sw_error_t rv = SW_OK;
+	adpt_api_t *p_api;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_get_xgmib_info)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_get_xgmib_info(dev_id, port_id, mib_Info);
+	return rv;
+}
+
+static sw_error_t
+_fal_get_rx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id,
+                  fal_xgmib_info_t * mib_Info)
+{
+	sw_error_t rv = SW_OK;
+	adpt_api_t *p_api;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+        if (NULL == p_api->adpt_get_rx_xgmib_info)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_api->adpt_get_rx_xgmib_info(dev_id, port_id, mib_Info);
+        return rv;
+}
+
+static sw_error_t
+_fal_get_tx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id,
+                  fal_xgmib_info_t * mib_Info)
+{
+	sw_error_t rv = SW_OK;
+	adpt_api_t *p_api;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+        if (NULL == p_api->adpt_get_tx_xgmib_info)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_api->adpt_get_tx_xgmib_info(dev_id, port_id, mib_Info);
+        return rv;
+}
+
+static fal_mib_counter_t *g_mibcounter[SW_MAX_NR_DEV];
+
+sw_error_t
+fal_mib_counter_alloc(a_uint32_t dev_id, a_uint64_t **p_mibcounter)
+{
+	*p_mibcounter = kzalloc(SW_MAX_NR_PORT * sizeof(fal_mib_counter_t),
+			GFP_KERNEL);
+
+	if(NULL == *p_mibcounter)
+		return SW_OUT_OF_MEM;
+
+	g_mibcounter[dev_id] = (fal_mib_counter_t*)*p_mibcounter;
+
+	return SW_OK;
+}
+
+static void _fal_rx_mib_update(a_uint32_t dev_id, fal_port_t port_id,
+                 fal_mib_info_t * mib_Info)
+{
+	if(NULL == g_mibcounter[dev_id])
+		return;
+
+	g_mibcounter[dev_id][port_id].RxBroad += mib_Info->RxBroad;
+	g_mibcounter[dev_id][port_id].RxPause += mib_Info->RxPause;
+	g_mibcounter[dev_id][port_id].RxMulti += mib_Info->RxMulti;
+	g_mibcounter[dev_id][port_id].RxFcsErr += mib_Info->RxFcsErr;
+	g_mibcounter[dev_id][port_id].RxAllignErr += mib_Info->RxAllignErr;
+	g_mibcounter[dev_id][port_id].RxRunt += mib_Info->RxRunt;
+	g_mibcounter[dev_id][port_id].RxFragment += mib_Info->RxFragment;
+	g_mibcounter[dev_id][port_id].Rx64Byte += mib_Info->Rx64Byte;
+	g_mibcounter[dev_id][port_id].Rx128Byte += mib_Info->Rx128Byte;
+	g_mibcounter[dev_id][port_id].Rx256Byte += mib_Info->Rx256Byte;
+	g_mibcounter[dev_id][port_id].Rx512Byte += mib_Info->Rx512Byte;
+	g_mibcounter[dev_id][port_id].Rx1024Byte += mib_Info->Rx1024Byte;
+	g_mibcounter[dev_id][port_id].Rx1518Byte += mib_Info->Rx1518Byte;
+	g_mibcounter[dev_id][port_id].RxMaxByte += mib_Info->RxMaxByte;
+	g_mibcounter[dev_id][port_id].RxTooLong += mib_Info->RxTooLong;
+	g_mibcounter[dev_id][port_id].RxGoodByte +=
+		(((u64)mib_Info->RxGoodByte_hi) << 32) | mib_Info->RxGoodByte_lo;
+	g_mibcounter[dev_id][port_id].RxBadByte +=
+		(((u64)mib_Info->RxBadByte_hi) << 32) | mib_Info->RxBadByte_lo;
+	g_mibcounter[dev_id][port_id].RxOverFlow += mib_Info->RxOverFlow;
+	g_mibcounter[dev_id][port_id].Filtered += mib_Info->Filtered;
+	g_mibcounter[dev_id][port_id].RxUniCast += mib_Info->RxUniCast;
+	g_mibcounter[dev_id][port_id].RxTooLongByte +=
+		(((u64)mib_Info->RxTooLongByte_hi) << 32) | mib_Info->RxTooLongByte_lo;
+	g_mibcounter[dev_id][port_id].RxRuntByte +=
+		(((u64)mib_Info->RxRuntByte_hi) << 32) | mib_Info->RxRuntByte_lo;
+	g_mibcounter[dev_id][port_id].Rx14To63 += mib_Info->Rx14To63;
+
+	return;
+}
+
+static void _fal_tx_mib_update(a_uint32_t dev_id, fal_port_t port_id,
+                 fal_mib_info_t * mib_Info)
+{
+	if(NULL == g_mibcounter[dev_id])
+		return;
+
+	g_mibcounter[dev_id][port_id].TxBroad += mib_Info->TxBroad;
+	g_mibcounter[dev_id][port_id].TxPause += mib_Info->TxPause;
+	g_mibcounter[dev_id][port_id].TxMulti += mib_Info->TxMulti;
+	g_mibcounter[dev_id][port_id].TxUnderRun += mib_Info->TxUnderRun;
+	g_mibcounter[dev_id][port_id].Tx64Byte += mib_Info->Tx64Byte;
+	g_mibcounter[dev_id][port_id].Tx128Byte += mib_Info->Tx128Byte;
+	g_mibcounter[dev_id][port_id].Tx256Byte += mib_Info->Tx256Byte;
+	g_mibcounter[dev_id][port_id].Tx512Byte += mib_Info->Tx512Byte;
+	g_mibcounter[dev_id][port_id].Tx1024Byte += mib_Info->Tx1024Byte;
+	g_mibcounter[dev_id][port_id].Tx1518Byte += mib_Info->Tx1518Byte;
+	g_mibcounter[dev_id][port_id].TxMaxByte += mib_Info->TxMaxByte;
+	g_mibcounter[dev_id][port_id].TxOverSize += mib_Info->TxOverSize;
+	g_mibcounter[dev_id][port_id].TxByte +=
+		(((u64)mib_Info->TxByte_hi) << 32) | mib_Info->TxByte_lo;
+	g_mibcounter[dev_id][port_id].TxCollision += mib_Info->TxCollision;
+	g_mibcounter[dev_id][port_id].TxAbortCol += mib_Info->TxAbortCol;
+	g_mibcounter[dev_id][port_id].TxMultiCol += mib_Info->TxMultiCol;
+	g_mibcounter[dev_id][port_id].TxSingalCol += mib_Info->TxSingalCol;
+	g_mibcounter[dev_id][port_id].TxExcDefer += mib_Info->TxExcDefer;
+	g_mibcounter[dev_id][port_id].TxDefer += mib_Info->TxDefer;
+	g_mibcounter[dev_id][port_id].TxLateCol += mib_Info->TxLateCol;
+	g_mibcounter[dev_id][port_id].TxUniCast += mib_Info->TxUniCast;
+
+	return;
+}
+
+/*insert flag for inner fal, don't remove it*/
+/**
+ * @brief Get mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                 fal_mib_info_t * mib_Info)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_get_mib_info(dev_id, port_id, mib_Info);
+    _fal_rx_mib_update(dev_id, port_id, mib_Info);
+    _fal_tx_mib_update(dev_id, port_id, mib_Info);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_mib_counter_get(a_uint32_t dev_id, fal_port_t port_id,
+				fal_mib_counter_t *mib_counter)
+{
+	sw_error_t rv;
+	fal_mib_info_t mib_info = {0};
+
+	if(NULL == g_mibcounter[dev_id])
+		return SW_BAD_PTR;
+
+	rv = fal_get_mib_info(dev_id, port_id, &mib_info);
+
+	if(rv != SW_OK)
+		return rv;
+
+	mib_counter->RxBroad        = g_mibcounter[dev_id][port_id].RxBroad;
+	mib_counter->RxPause        = g_mibcounter[dev_id][port_id].RxPause;
+	mib_counter->RxMulti        = g_mibcounter[dev_id][port_id].RxMulti;
+	mib_counter->RxFcsErr       = g_mibcounter[dev_id][port_id].RxFcsErr;
+	mib_counter->RxAllignErr    = g_mibcounter[dev_id][port_id].RxAllignErr;
+	mib_counter->RxRunt         = g_mibcounter[dev_id][port_id].RxRunt;
+	mib_counter->RxFragment     = g_mibcounter[dev_id][port_id].RxFragment ;
+	mib_counter->Rx64Byte       = g_mibcounter[dev_id][port_id].Rx64Byte ;
+	mib_counter->Rx128Byte      = g_mibcounter[dev_id][port_id].Rx128Byte;
+	mib_counter->Rx256Byte      = g_mibcounter[dev_id][port_id].Rx256Byte;
+	mib_counter->Rx512Byte      = g_mibcounter[dev_id][port_id].Rx512Byte;
+	mib_counter->Rx1024Byte     = g_mibcounter[dev_id][port_id].Rx1024Byte;
+	mib_counter->Rx1518Byte     = g_mibcounter[dev_id][port_id].Rx1518Byte;
+	mib_counter->RxMaxByte      = g_mibcounter[dev_id][port_id].RxMaxByte;
+	mib_counter->RxTooLong      = g_mibcounter[dev_id][port_id].RxTooLong;
+	mib_counter->RxGoodByte     = g_mibcounter[dev_id][port_id].RxGoodByte;
+	mib_counter->RxBadByte      = g_mibcounter[dev_id][port_id].RxBadByte;
+	mib_counter->RxOverFlow     = g_mibcounter[dev_id][port_id].RxOverFlow;
+	mib_counter->Filtered       = g_mibcounter[dev_id][port_id].Filtered;
+	mib_counter->TxBroad        = g_mibcounter[dev_id][port_id].TxBroad;
+	mib_counter->TxPause        = g_mibcounter[dev_id][port_id].TxPause;
+	mib_counter->TxMulti        = g_mibcounter[dev_id][port_id].TxMulti;
+	mib_counter->TxUnderRun     = g_mibcounter[dev_id][port_id].TxUnderRun;
+	mib_counter->Tx64Byte       = g_mibcounter[dev_id][port_id].Tx64Byte;
+	mib_counter->Tx128Byte      = g_mibcounter[dev_id][port_id].Tx128Byte;
+	mib_counter->Tx256Byte      = g_mibcounter[dev_id][port_id].Tx256Byte;
+	mib_counter->Tx512Byte      = g_mibcounter[dev_id][port_id].Tx512Byte;
+	mib_counter->Tx1024Byte     = g_mibcounter[dev_id][port_id].Tx1024Byte;
+	mib_counter->Tx1518Byte     = g_mibcounter[dev_id][port_id].Tx1518Byte;
+	mib_counter->TxMaxByte      = g_mibcounter[dev_id][port_id].TxMaxByte;
+	mib_counter->TxOverSize     = g_mibcounter[dev_id][port_id].TxOverSize;
+	mib_counter->TxByte         = g_mibcounter[dev_id][port_id].TxByte;
+	mib_counter->TxCollision    = g_mibcounter[dev_id][port_id].TxCollision;
+	mib_counter->TxAbortCol     = g_mibcounter[dev_id][port_id].TxAbortCol;
+	mib_counter->TxMultiCol     = g_mibcounter[dev_id][port_id].TxMultiCol;
+	mib_counter->TxSingalCol    = g_mibcounter[dev_id][port_id].TxSingalCol;
+	mib_counter->TxExcDefer     = g_mibcounter[dev_id][port_id].TxExcDefer;
+	mib_counter->TxDefer        = g_mibcounter[dev_id][port_id].TxDefer;
+	mib_counter->TxLateCol      = g_mibcounter[dev_id][port_id].TxLateCol;
+	mib_counter->RxUniCast      = g_mibcounter[dev_id][port_id].RxUniCast;
+	mib_counter->TxUniCast      = g_mibcounter[dev_id][port_id].TxUniCast;
+	mib_counter->Rx14To63       = g_mibcounter[dev_id][port_id].Rx14To63;
+	mib_counter->RxTooLongByte  = g_mibcounter[dev_id][port_id].RxTooLongByte;
+	mib_counter->RxRuntByte     = g_mibcounter[dev_id][port_id].RxRuntByte;
+
+	return SW_OK;
+}
+
+/**
+ * @brief Get RX mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                 fal_mib_info_t * mib_Info)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_get_rx_mib_info(dev_id, port_id, mib_Info);
+    _fal_rx_mib_update(dev_id, port_id, mib_Info);
+    FAL_API_UNLOCK;
+
+    return rv;
+}
+
+/**
+ * @brief Get TX mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                 fal_mib_info_t * mib_Info)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_get_tx_mib_info(dev_id, port_id, mib_Info);
+    _fal_tx_mib_update(dev_id, port_id, mib_Info);
+    FAL_API_UNLOCK;
+
+    return rv;
+}
+
+/**
+ * @brief Set mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_mib_status_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_mib_status_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Flush mib counters on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id )
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_mib_port_flush_counters(dev_id, port_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_mib_cpukeep_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_mib_cpukeep_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get xgmacmib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_get_xgmib_info(a_uint32_t dev_id, fal_port_t port_id,
+                 fal_xgmib_info_t * mib_Info)
+{
+    sw_error_t rv;
+    fal_mib_counter_t gmac_mib = { 0 };
+
+    FAL_API_LOCK;
+    rv = _fal_get_xgmib_info(dev_id, port_id, mib_Info);
+    FAL_API_UNLOCK;
+    SW_RTN_ON_ERROR(rv);
+
+    rv = fal_mib_counter_get(dev_id, port_id, &gmac_mib);
+    SW_RTN_ON_ERROR(rv);
+
+    mib_Info->RxFrame += (gmac_mib.RxBroad +
+				gmac_mib.RxMulti + gmac_mib.RxUniCast);
+    mib_Info->RxByte += (gmac_mib.RxGoodByte+gmac_mib.RxBadByte);
+    mib_Info->RxByteGood += gmac_mib.RxGoodByte;
+    mib_Info->RxBroadGood += gmac_mib.RxBroad;
+    mib_Info->RxMultiGood += gmac_mib.RxMulti;
+    mib_Info->RxFcsErr += gmac_mib.RxFcsErr;
+    mib_Info->RxRuntErr += gmac_mib.RxRunt;
+    mib_Info->Rx64Byte += gmac_mib.Rx64Byte;
+    mib_Info->Rx128Byte += gmac_mib.Rx128Byte;
+    mib_Info->Rx256Byte += gmac_mib.Rx256Byte;
+    mib_Info->Rx512Byte += gmac_mib.Rx512Byte;
+    mib_Info->Rx1024Byte += gmac_mib.Rx1024Byte;
+    mib_Info->RxMaxByte += (gmac_mib.Rx1518Byte + gmac_mib.RxMaxByte);
+    mib_Info->RxUnicastGood += gmac_mib.RxUniCast;
+    mib_Info->RxLengthError += gmac_mib.RxTooLong;
+    mib_Info->RxPause += gmac_mib.RxPause;
+    mib_Info->RxOverFlow += gmac_mib.RxOverFlow;
+
+    mib_Info->TxByte += gmac_mib.TxByte;
+    mib_Info->TxFrame += (gmac_mib.TxBroad +
+				gmac_mib.TxMulti + gmac_mib.TxUniCast);
+    mib_Info->TxBroadGood += gmac_mib.TxBroad;
+    mib_Info->TxMultiGood += gmac_mib.TxMulti;
+    mib_Info->Tx64Byte += gmac_mib.Tx64Byte;
+    mib_Info->Tx128Byte += gmac_mib.Tx128Byte;
+    mib_Info->Tx256Byte += gmac_mib.Tx256Byte;
+    mib_Info->Tx512Byte += gmac_mib.Tx512Byte;
+    mib_Info->Tx1024Byte += gmac_mib.Tx1024Byte;
+    mib_Info->TxMaxByte += (gmac_mib.Tx1518Byte + gmac_mib.TxMaxByte);
+    mib_Info->TxUnicast += gmac_mib.TxUniCast;
+    mib_Info->TxMulti += gmac_mib.TxMulti;
+    mib_Info->TxBroad += gmac_mib.TxBroad;
+    mib_Info->TxByteGood += gmac_mib.TxByte;
+    mib_Info->TxFrameGood += (gmac_mib.TxBroad +
+				gmac_mib.TxMulti + gmac_mib.TxUniCast);
+    mib_Info->TxPause += gmac_mib.TxPause;
+
+    return rv;
+}
+
+/**
+ * @brief Get RX xgmacmib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_get_rx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id,
+                 fal_xgmib_info_t * mib_Info)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_get_rx_xgmib_info(dev_id, port_id, mib_Info);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get TX xgmacmib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_get_tx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id,
+                 fal_xgmib_info_t * mib_Info)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_get_tx_xgmib_info(dev_id, port_id, mib_Info);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+EXPORT_SYMBOL(fal_get_mib_info);
+EXPORT_SYMBOL(fal_get_rx_mib_info);
+EXPORT_SYMBOL(fal_get_tx_mib_info);
+EXPORT_SYMBOL(fal_get_xgmib_info);
+EXPORT_SYMBOL(fal_get_rx_xgmib_info);
+EXPORT_SYMBOL(fal_get_tx_xgmib_info);
+EXPORT_SYMBOL(fal_mib_status_set);
+EXPORT_SYMBOL(fal_mib_status_get);
+EXPORT_SYMBOL(fal_mib_port_flush_counters);
+EXPORT_SYMBOL(fal_mib_cpukeep_set);
+EXPORT_SYMBOL(fal_mib_cpukeep_get);
+EXPORT_SYMBOL(fal_mib_counter_get);
+
+/*insert flag for outter fal, don't remove it*/
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/fal/fal_mirror.c b/qca-ssdk/src/fal/fal_mirror.c
new file mode 100755
index 0000000..21856a3
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_mirror.c
@@ -0,0 +1,344 @@
+/*
+ * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_mirror FAL_MIRROR
+ * @{
+ */
+#include "sw.h"
+#include "fal_mirror.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+
+
+static sw_error_t
+_fal_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_mirr_analysis_port_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_mirr_analysis_port_set(dev_id, port_id);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->mirr_analysis_port_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->mirr_analysis_port_set(dev_id, port_id);
+    return rv;
+}
+
+static sw_error_t
+_fal_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_mirr_analysis_port_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_mirr_analysis_port_get(dev_id, port_id);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->mirr_analysis_port_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->mirr_analysis_port_get(dev_id, port_id);
+    return rv;
+}
+
+static sw_error_t
+_fal_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_mirr_port_in_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_mirr_port_in_set(dev_id, port_id, enable);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->mirr_port_in_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->mirr_port_in_set(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_mirr_port_in_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_mirr_port_in_get(dev_id, port_id, enable);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->mirr_port_in_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->mirr_port_in_get(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_mirr_port_eg_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_mirr_port_eg_set(dev_id, port_id, enable);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->mirr_port_eg_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->mirr_port_eg_set(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_mirr_port_eg_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_mirr_port_eg_get(dev_id, port_id, enable);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->mirr_port_eg_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->mirr_port_eg_get(dev_id, port_id, enable);
+    return rv;
+}
+sw_error_t
+_fal_mirr_analysis_config_set(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_mirr_analysis_config_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_mirr_analysis_config_set(dev_id, direction, config);
+    return rv;
+}
+sw_error_t
+_fal_mirr_analysis_config_get(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_mirr_analysis_config_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_mirr_analysis_config_get(dev_id, direction, config);
+    return rv;
+}
+/*insert flag for inner fal, don't remove it*/
+/**
+ *   @details  Comments:
+ *   The analysis port works for both ingress and egress mirror.
+ * @brief Set mirror analyzer port on particular a device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_mirr_analysis_port_set(dev_id, port_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mirror analysis port on particular a device.
+ * @param[in] dev_id device id
+ * @param[out] port_id port id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_mirr_analysis_port_get(dev_id, port_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_mirr_port_in_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_mirr_port_in_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_mirr_port_eg_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_mirr_port_eg_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_mirr_analysis_config_set(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_mirr_analysis_config_set(dev_id, direction, config);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_mirr_analysis_config_get(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_mirr_analysis_config_get(dev_id, direction, config);
+    FAL_API_UNLOCK;
+    return rv;
+}
+/*insert flag for outter fal, don't remove it*/
+
+EXPORT_SYMBOL(fal_mirr_analysis_port_set);
+EXPORT_SYMBOL(fal_mirr_analysis_port_get);
+EXPORT_SYMBOL(fal_mirr_port_in_set);
+EXPORT_SYMBOL(fal_mirr_port_in_get);
+EXPORT_SYMBOL(fal_mirr_port_eg_set);
+EXPORT_SYMBOL(fal_mirr_port_eg_get);
+EXPORT_SYMBOL(fal_mirr_analysis_config_set);
+EXPORT_SYMBOL(fal_mirr_analysis_config_get);
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/fal/fal_misc.c b/qca-ssdk/src/fal/fal_misc.c
new file mode 100755
index 0000000..66623a8
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_misc.c
@@ -0,0 +1,1772 @@
+/*
+ * Copyright (c) 2012, 2017, 2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+* @defgroup fal_gen FAL_MISC
+* @{
+*/
+#include "sw.h"
+#include "fal_misc.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#ifndef IN_MISC_MINI
+static sw_error_t
+_fal_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->arp_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->arp_status_set(dev_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_arp_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->arp_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->arp_status_get(dev_id, enable);
+    return rv;
+}
+#endif
+
+static sw_error_t
+_fal_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->frame_max_size_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->frame_max_size_set(dev_id, size);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->frame_max_size_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->frame_max_size_get(dev_id, size);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_unk_sa_cmd_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_unk_sa_cmd_set(dev_id, port_id, cmd);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_unk_uc_filter_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_unk_uc_filter_set(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_unk_mc_filter_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_unk_mc_filter_set(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_bc_filter_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_bc_filter_set(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cpu_port_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cpu_port_status_set(dev_id, enable);
+    return rv;
+}
+
+#ifndef IN_MISC_MINI
+static sw_error_t
+_fal_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_unk_sa_cmd_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_unk_sa_cmd_get(dev_id, port_id, cmd);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_unk_uc_filter_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_unk_uc_filter_get(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_unk_mc_filter_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_unk_mc_filter_get(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_bc_filter_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_bc_filter_get(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cpu_port_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cpu_port_status_get(dev_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->bc_to_cpu_port_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->bc_to_cpu_port_set(dev_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->bc_to_cpu_port_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->bc_to_cpu_port_get(dev_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_dhcp_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_dhcp_set(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_dhcp_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_dhcp_get(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->arp_cmd_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->arp_cmd_set(dev_id, cmd);
+    return rv;
+}
+
+static sw_error_t
+_fal_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->arp_cmd_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->arp_cmd_get(dev_id, cmd);
+    return rv;
+}
+#endif
+
+static sw_error_t
+_fal_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->eapol_cmd_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->eapol_cmd_set(dev_id, cmd);
+    return rv;
+}
+
+#ifndef IN_MISC_MINI
+static sw_error_t
+_fal_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->eapol_cmd_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->eapol_cmd_get(dev_id, cmd);
+    return rv;
+}
+#endif
+
+static sw_error_t
+_fal_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->eapol_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->eapol_status_set(dev_id, port_id, enable);
+    return rv;
+}
+
+#ifndef IN_MISC_MINI
+static sw_error_t
+_fal_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->eapol_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->eapol_status_get(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ripv1_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ripv1_status_set(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->ripv1_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->ripv1_status_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_arp_req_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_arp_req_status_set(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_arp_req_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_arp_req_status_get(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_arp_ack_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_arp_ack_status_set(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_arp_ack_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_arp_ack_status_get(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->intr_mask_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->intr_mask_set(dev_id, intr_mask);
+    return rv;
+}
+
+static sw_error_t
+_fal_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->intr_mask_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->intr_mask_get(dev_id, intr_mask);
+    return rv;
+}
+
+static sw_error_t
+_fal_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->intr_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->intr_status_get(dev_id, intr_status);
+    return rv;
+}
+
+static sw_error_t
+_fal_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->intr_status_clear)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->intr_status_clear(dev_id, intr_status);
+    return rv;
+}
+
+static sw_error_t
+_fal_intr_port_link_mask_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t intr_mask)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_intr_port_link_mask_set != NULL) {
+        rv = p_adpt_api->adpt_intr_port_link_mask_set(dev_id, port_id, intr_mask);
+        return rv;
+   }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->intr_port_link_mask_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->intr_port_link_mask_set(dev_id, port_id, intr_mask);
+    return rv;
+}
+
+static sw_error_t
+_fal_intr_port_link_mask_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t * intr_mask)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_intr_port_link_mask_get != NULL) {
+        rv = p_adpt_api->adpt_intr_port_link_mask_get(dev_id, port_id, intr_mask);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->intr_port_link_mask_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->intr_port_link_mask_get(dev_id, port_id, intr_mask);
+    return rv;
+}
+
+static sw_error_t
+_fal_intr_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t * intr_mask)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_intr_port_link_status_get != NULL) {
+        rv = p_adpt_api->adpt_intr_port_link_status_get(dev_id, port_id, intr_mask);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->intr_port_link_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->intr_port_link_status_get(dev_id, port_id, intr_mask);
+    return rv;
+}
+
+
+
+static sw_error_t
+_fal_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->intr_mask_mac_linkchg_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->intr_mask_mac_linkchg_set(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->intr_mask_mac_linkchg_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->intr_mask_mac_linkchg_get(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->intr_status_mac_linkchg_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->intr_status_mac_linkchg_get(dev_id, port_bitmap);
+    return rv;
+}
+
+static sw_error_t
+_fal_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cpu_vid_en_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cpu_vid_en_set(dev_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cpu_vid_en_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cpu_vid_en_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_intr_status_mac_linkchg_clear(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->intr_status_mac_linkchg_clear)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->intr_status_mac_linkchg_clear(dev_id);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_global_macaddr_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->global_macaddr_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->global_macaddr_set(dev_id, addr);
+    return rv;
+}
+
+static sw_error_t
+_fal_global_macaddr_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->global_macaddr_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->global_macaddr_get(dev_id, addr);
+    return rv;
+}
+
+static sw_error_t
+_fal_lldp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->lldp_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->lldp_status_set(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_lldp_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->lldp_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->lldp_status_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_frame_crc_reserve_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->frame_crc_reserve_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->frame_crc_reserve_set(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_frame_crc_reserve_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->frame_crc_reserve_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->frame_crc_reserve_get(dev_id, enable);
+    return rv;
+}
+
+sw_error_t
+_fal_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id, fal_counter_en_t * cnt_en)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_debug_port_counter_enable)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_debug_port_counter_enable(dev_id, port_id, cnt_en);
+    return rv;
+}
+
+sw_error_t
+_fal_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id, fal_counter_en_t * cnt_en)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_debug_port_counter_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_debug_port_counter_status_get(dev_id, port_id, cnt_en);
+    return rv;
+}
+
+/**
+ * @brief Set arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_arp_status_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_arp_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_arp_status_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set max frame size which device can received on a particular device.
+ * @details    Comments:
+ * The granularity of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[in] size packet size
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_frame_max_size_set(dev_id, size);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max frame size which device can received on a particular device.
+ * @details   Comments:
+ *    The unit of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[out] size packet size
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_frame_max_size_get(dev_id, size);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set forwarding command for packets which source address is unknown on a particular port.
+ * @details Comments:
+ *    Particular device may only support parts of forwarding commands.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_unk_sa_cmd_set(dev_id, port_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown unicast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown unicast packets filter on one port then unknown
+ *   unicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_unk_uc_filter_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown multicast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown multicast packets filter on one port then unknown
+ *   multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_unk_mc_filter_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of broadcast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown multicast packets filter on one port then unknown
+ *   multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_bc_filter_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cpu_port_status_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_MISC_MINI
+/**
+ * @brief Get forwarding command for packets which source address is unknown on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_unk_sa_cmd_get(dev_id, port_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flooding status of unknown unicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_unk_uc_filter_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+
+/**
+ * @brief Get flooding status of unknown multicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_unk_mc_filter_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+
+/**
+ * @brief Get flooding status of broadcast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_bc_filter_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cpu_port_status_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of braodcast packets broadcasting to cpu on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_bc_to_cpu_port_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get status of braodcast packets broadcasting to cpu on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_bc_to_cpu_port_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dhcp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_dhcp_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dhcp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_dhcp_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets forwarding command on a particular device.
+ * @details    Comments:
+ *    Particular device may only support parts of forwarding commands.
+ *    This operation will take effect only after enabling arp
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_arp_cmd_set(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_arp_cmd_get(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set eapol packets forwarding command on a particular device.
+ * @details    Comments:
+ *    Particular device may only support parts of forwarding commands.
+ *    This operation will take effect only after enabling eapol
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_eapol_cmd_set(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_MISC_MINI
+/**
+ * @brief Get eapol packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_eapol_cmd_get(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set eapol packets hardware acknowledgement on a particular port.
+ * @details    Comments:
+ *    Particular device may only support parts of forwarding commands.
+ *    This operation will take effect only after enabling eapol
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_eapol_status_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_MISC_MINI
+/**
+ * @brief Get eapol packets hardware acknowledgement on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_eapol_status_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ripv1 packets hardware acknowledgement on a particular port.
+ * @details    Comments:
+ *    Particular device may only support parts of forwarding commands.
+ *    This operation will take effect only after enabling eapol
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ripv1_status_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ripv1 packets hardware acknowledgement on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_ripv1_status_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp req packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_arp_req_status_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp req packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_arp_req_status_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp ack packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_arp_ack_status_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp ack packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_arp_ack_status_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set switch interrupt mask on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_mask mask
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_intr_mask_set(dev_id, intr_mask);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get switch interrupt mask on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_mask mask
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_intr_mask_get(dev_id, intr_mask);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get switch interrupt status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_status status
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_intr_status_get(dev_id, intr_status);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Clear switch interrupt status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_status status
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_intr_status_clear(dev_id, intr_status);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set link interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag)
+{
+    sw_error_t rv;
+    FAL_API_LOCK;
+    rv = _fal_intr_port_link_mask_set(dev_id, port_id, intr_mask_flag);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get link interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_intr_port_link_mask_get(dev_id, port_id, intr_mask_flag);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get link interrupt status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_intr_port_link_status_get(dev_id, port_id, intr_mask_flag);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set mac link change interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable ports intr mask enabled
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    FAL_API_LOCK;
+    rv = _fal_intr_mask_mac_linkchg_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mac link change interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port interrupt mask or not
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_intr_mask_mac_linkchg_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get link change interrupt status for all ports.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] ports bitmap which generates interrupt
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_intr_status_mac_linkchg_get(dev_id, port_bitmap);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set to cpu vid enable status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cpu_vid_en_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get to cpu vid enable status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cpu_vid_en_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mac link change interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_status_mac_linkchg_clear(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_intr_status_mac_linkchg_clear(dev_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set global macaddr on particular device.
+ * @param[in] dev_id device id
+ * @param[in] addr   addr
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_global_macaddr_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_global_macaddr_set(dev_id, addr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get global macaddr on particular device.
+ * @param[in]  dev_id device id
+ * @param[out] addr   addr
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_global_macaddr_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_global_macaddr_get(dev_id, addr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set lldp packets hardware acknowledgement status on particular device.
+ * @details     comments:
+ *   Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_lldp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_lldp_status_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get lldp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_lldp_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_lldp_status_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set frame crc reserve enable on particular device.
+ * @details     comments:
+ *   CRC reseve enable.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_frame_crc_reserve_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_frame_crc_reserve_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get frame crc reserve enable on particular device.
+ * @details     comments:
+ *   CRC reseve enable.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_frame_crc_reserve_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_frame_crc_reserve_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id, fal_counter_en_t * cnt_en)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_debug_port_counter_enable(dev_id, port_id, cnt_en);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id, fal_counter_en_t * cnt_en)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_debug_port_counter_status_get(dev_id, port_id, cnt_en);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/fal/fal_nat.c b/qca-ssdk/src/fal/fal_nat.c
new file mode 100755
index 0000000..6110628
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_nat.c
@@ -0,0 +1,1341 @@
+/*
+ * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_nat FAL_NAT
+ * @{
+ */
+
+#include "sw.h"
+#include "fal_nat.h"
+#include "hsl_api.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+int nf_athrs17_hnat_sync_counter_en = 0;
+
+static sw_error_t
+_fal_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_add(dev_id, nat_entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_del(a_uint32_t dev_id, a_uint32_t del_mode,
+             fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_del(dev_id, del_mode, nat_entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_get(a_uint32_t dev_id, a_uint32_t get_mode,
+             fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_get(dev_id, get_mode, nat_entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+              fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_next)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_next(dev_id, next_mode, nat_entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id,
+                      a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_counter_bind)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_counter_bind(dev_id, entry_id, cnt_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->napt_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->napt_add(dev_id, napt_entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_napt_del(a_uint32_t dev_id, a_uint32_t del_mode,
+              fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->napt_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->napt_del(dev_id, del_mode, napt_entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_napt_get(a_uint32_t dev_id, a_uint32_t get_mode,
+              fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->napt_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->napt_get(dev_id, get_mode, napt_entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+               fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->napt_next)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->napt_next(dev_id, next_mode, napt_entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                       a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->napt_counter_bind)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->napt_counter_bind(dev_id, entry_id, cnt_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_flow_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->flow_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->flow_add(dev_id, napt_entry);
+    return rv;
+}
+
+static sw_error_t
+
+_fal_flow_cookie_set(a_uint32_t dev_id, fal_flow_cookie_t * flow_cookie)
+{
+	sw_error_t rv;
+	hsl_api_t *p_api;
+
+	SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+	if (NULL == p_api->flow_cookie_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->flow_cookie_set(dev_id, flow_cookie);
+	return rv;
+}
+
+static sw_error_t
+
+_fal_flow_rfs_set(a_uint32_t dev_id, a_uint8_t action, fal_flow_rfs_t * rfs)
+{
+	sw_error_t rv;
+	hsl_api_t *p_api;
+
+	SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+	if (NULL == p_api->flow_rfs_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->flow_rfs_set(dev_id, action, rfs);
+	return rv;
+}
+
+
+
+static sw_error_t
+_fal_flow_del(a_uint32_t dev_id, a_uint32_t del_mode,
+              fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->flow_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->flow_del(dev_id, del_mode, napt_entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_flow_get(a_uint32_t dev_id, a_uint32_t get_mode,
+              fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->flow_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->flow_get(dev_id, get_mode, napt_entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_flow_next(a_uint32_t dev_id, a_uint32_t next_mode,
+               fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->flow_next)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->flow_next(dev_id, next_mode, napt_entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_flow_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                       a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->flow_counter_bind)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->flow_counter_bind(dev_id, entry_id, cnt_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_status_set(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_status_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_hash_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_hash_mode_set(dev_id, mode);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_hash_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_hash_mode_get(dev_id, mode);
+    return rv;
+}
+
+static sw_error_t
+_fal_napt_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->napt_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->napt_status_set(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_napt_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->napt_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->napt_status_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->napt_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->napt_mode_set(dev_id, mode);
+    return rv;
+}
+
+static sw_error_t
+_fal_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->napt_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->napt_mode_get(dev_id, mode);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_prv_base_addr_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_prv_base_addr_set(dev_id, addr);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_prv_base_addr_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_prv_base_addr_get(dev_id, addr);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_prv_base_mask_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_prv_base_mask_set(dev_id, addr);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_prv_base_mask_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_prv_base_mask_get(dev_id, addr);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_prv_addr_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_prv_addr_mode_set(dev_id, map_en);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_prv_addr_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_prv_addr_mode_get(dev_id, map_en);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_pub_addr_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_pub_addr_add(dev_id, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                      fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_pub_addr_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_pub_addr_del(dev_id, del_mode, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                       fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_pub_addr_next)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_pub_addr_next(dev_id, next_mode, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_unk_session_cmd_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_unk_session_cmd_set(dev_id, cmd);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_unk_session_cmd_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_unk_session_cmd_get(dev_id, cmd);
+    return rv;
+}
+
+static sw_error_t
+_fal_nat_global_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t portbmp)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nat_global_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nat_global_set(dev_id, enable, portbmp);
+    return rv;
+}
+
+/**
+ * @brief Add one NAT entry to one particular device.
+ *   @details Comments:
+       Before NAT entry added ip4 private base address must be set
+       at first.
+       In parameter nat_entry entry flags must be set
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_add(dev_id, nat_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Del NAT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode NAT entry delete operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_del(a_uint32_t dev_id, a_uint32_t del_mode,
+            fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_del(dev_id, del_mode, nat_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get one NAT entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode NAT entry get operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @param[out] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_get(a_uint32_t dev_id, a_uint32_t get_mode,
+            fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_get(dev_id, get_mode, nat_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next NAT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode NAT entry next operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @param[out] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+             fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_next(dev_id, next_mode, nat_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one NAT entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id NAT entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id,
+                     a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_counter_bind(dev_id, entry_id, cnt_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one NAPT entry to one particular device.
+ *   @details Comments:
+       Before NAPT entry added related ip4 private base address must be set
+       at first.
+       In parameter napt_entry related entry flags must be set
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_napt_add(dev_id, napt_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Del NAPT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode NAPT entry delete operation mode
+ * @param[in] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_del(a_uint32_t dev_id, a_uint32_t del_mode,
+             fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_napt_del(dev_id, del_mode, napt_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get one NAPT entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode NAPT entry get operation mode
+ * @param[in] nat_entry NAPT entry parameter
+ * @param[out] nat_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_get(a_uint32_t dev_id, a_uint32_t get_mode,
+             fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_napt_get(dev_id, get_mode, napt_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next NAPT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode NAPT entry next operation mode
+ * @param[in] napt_entry NAPT entry parameter
+ * @param[out] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+              fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_napt_next(dev_id, next_mode, napt_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one NAPT entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id NAPT entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                      a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_napt_counter_bind(dev_id, entry_id, cnt_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one FLOW entry to one particular device.
+ *   @details Comments:
+       Before FLOW entry added related ip4 private base address must be set
+       at first.
+       In parameter napt_entry related entry flags must be set
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] napt_entry FLOW entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_flow_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_flow_add(dev_id, napt_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Del FLOW entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode NAPT entry delete operation mode
+ * @param[in] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_flow_del(a_uint32_t dev_id, a_uint32_t del_mode,
+             fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_flow_del(dev_id, del_mode, napt_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get one FLOW entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode FLOW entry get operation mode
+ * @param[in] nat_entry FLOW entry parameter
+ * @param[out] nat_entry FLOW entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_flow_get(a_uint32_t dev_id, a_uint32_t get_mode,
+             fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_flow_get(dev_id, get_mode, napt_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next FLOW entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode FLOW entry next operation mode
+ * @param[in] napt_entry FLOW entry parameter
+ * @param[out] napt_entry FLOW entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_flow_next(a_uint32_t dev_id, a_uint32_t next_mode,
+              fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_flow_next(dev_id, next_mode, napt_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one FLOW entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id FLOW entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_flow_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                      a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_flow_counter_bind(dev_id, entry_id, cnt_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_status_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_status_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set NAT hash mode on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mode NAT hash mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_hash_mode_set(dev_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get NAT hash mode on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mode NAT hash mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_hash_mode_get(dev_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_napt_status_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working status of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_napt_status_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working mode of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mode NAPT mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_napt_mode_set(dev_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working mode of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mode NAPT mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_napt_mode_get(dev_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP4 private base address on a particular device
+ *   @details Comments:
+        Only 20bits is meaning which 20bits is determined by private address mode.
+ * @param[in] dev_id device id
+ * @param[in] addr private base address
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_prv_base_addr_set(dev_id, addr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[out] addr private base address
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_prv_base_addr_get(dev_id, addr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_prv_base_mask_set(dev_id, addr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_prv_base_mask_get(dev_id, addr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP4 private base address mode on a particular device
+ *   @details Comments:
+        If map_en equal true means bits31-20 bits15-8 are base address
+        else bits31-12 are base address.
+ * @param[in] dev_id device id
+ * @param[in] map_en private base mapping mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_prv_addr_mode_set(dev_id, map_en);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP4 private base address mode on a particular device
+ * @param[in] dev_id device id
+ * @param[out] map_en private base mapping mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_prv_addr_mode_get(dev_id, map_en);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one public address entry to one particular device.
+ *   @details Comments:
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_pub_addr_add(dev_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one public address entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operaton mode
+ * @param[in] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                     fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_pub_addr_del(dev_id, del_mode, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next public address entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operaton mode
+ * @param[out] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                      fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_pub_addr_next(dev_id, next_mode, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set forwarding command for those packets miss NAT entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_unk_session_cmd_set(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get forwarding command for those packets miss NAT entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nat_unk_session_cmd_get(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] sync_cnt_enable A_TRUE or A_FALSE
+ * @param[in] portbmp port bitmap
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_global_set(a_uint32_t dev_id, a_bool_t enable,
+		a_bool_t sync_cnt_enable, a_uint32_t portbmp)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+	nf_athrs17_hnat_sync_counter_en = (int)sync_cnt_enable;
+    rv = _fal_nat_global_set(dev_id, enable, portbmp);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add/del one FLOW cookie entry to one particular device.
+ *   @details Comments:
+       Before FLOW entry added related ip4 private base address must be set
+       at first.
+       In parameter napt_entry related entry flags must be set
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] napt_entry FLOW entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_flow_cookie_set(a_uint32_t dev_id, fal_flow_cookie_t * flow_cookie)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_flow_cookie_set(dev_id, flow_cookie);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add/del one FLOW rfs entry to one particular device.
+ *   @details Comments:
+       Before FLOW entry added related ip4 private base address must be set
+       at first.
+       In parameter napt_entry related entry flags must be set
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] napt_entry FLOW entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_flow_rfs_set(a_uint32_t dev_id, a_uint8_t action, fal_flow_rfs_t * rfs)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_flow_rfs_set(dev_id, action, rfs);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+int ssdk_flow_cookie_set(
+		u32 protocol, __be32 src_ip,
+		__be16 src_port, __be32 dst_ip,
+		__be16 dst_port, u16 flowcookie)
+{
+	fal_flow_cookie_t flow_cookie;
+	if(protocol == 17) {
+		flow_cookie.proto = 0x2;
+	} else {
+		flow_cookie.proto = 0x1;
+	}
+	flow_cookie.src_addr = ntohl(src_ip);
+	flow_cookie.dst_addr = ntohl(dst_ip);
+	flow_cookie.src_port = ntohs(src_port);
+	flow_cookie.dst_port = ntohs(dst_port);
+	flow_cookie.flow_cookie = flowcookie;
+	return fal_flow_cookie_set(0, &flow_cookie);
+}
+
+int ssdk_rfs_ipct_rule_set(
+	__be32 ip_src, __be32 ip_dst,
+	__be16 sport, __be16 dport, uint8_t proto,
+	u16 loadbalance, bool action)
+{
+	fal_flow_rfs_t rfs;
+	if(proto == 17) {
+		rfs.proto = 0x2;
+	} else {
+		rfs.proto = 0x1;
+	}
+	rfs.src_addr = ntohl(ip_src);
+	rfs.dst_addr = ntohl(ip_dst);
+	rfs.src_port = ntohs(sport);
+	rfs.dst_port = ntohs(dport);
+	rfs.load_balance = loadbalance;
+	if(fal_flow_rfs_set(0, action, &rfs))
+		return -1;
+	return 0;
+}
+
+#if 0
+EXPORT_SYMBOL(ssdk_flow_cookie_set);
+EXPORT_SYMBOL(ssdk_rfs_ipct_rule_set);
+#endif
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/fal/fal_policer.c b/qca-ssdk/src/fal/fal_policer.c
new file mode 100755
index 0000000..6e9e68f
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_policer.c
@@ -0,0 +1,402 @@
+/*
+ * Copyright (c) 2016-2017, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_policer FAL_POLICER
+ * @{
+ */
+#include "sw.h"
+#include "fal_policer.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+
+#ifndef IN_POLICER_MINI
+sw_error_t
+_fal_acl_policer_counter_get(a_uint32_t dev_id, a_uint32_t index,
+		fal_policer_counter_t *counter)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_acl_policer_counter_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_acl_policer_counter_get(dev_id, index, counter);
+    return rv;
+}
+sw_error_t
+_fal_port_policer_counter_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_policer_counter_t *counter)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_policer_counter_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_policer_counter_get(dev_id, port_id, counter);
+    return rv;
+}
+sw_error_t
+_fal_port_policer_entry_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_policer_config_t *policer, fal_policer_action_t *action)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_policer_entry_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_policer_entry_get(dev_id, port_id, policer, action);
+    return rv;
+}
+sw_error_t
+_fal_port_policer_entry_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_policer_config_t *policer, fal_policer_action_t *action)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_policer_entry_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_policer_entry_set(dev_id, port_id, policer, action);
+    return rv;
+}
+sw_error_t
+_fal_acl_policer_entry_get(a_uint32_t dev_id, a_uint32_t index,
+		fal_policer_config_t *policer, fal_policer_action_t *action)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_acl_policer_entry_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_acl_policer_entry_get(dev_id, index, policer, action);
+    return rv;
+}
+sw_error_t
+_fal_acl_policer_entry_set(a_uint32_t dev_id, a_uint32_t index,
+		fal_policer_config_t *policer, fal_policer_action_t *action)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_acl_policer_entry_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_acl_policer_entry_set(dev_id, index, policer, action);
+    return rv;
+}
+sw_error_t
+_fal_policer_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_policer_time_slot_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_policer_time_slot_get(dev_id, timeslot);
+    return rv;
+}
+
+sw_error_t
+_fal_policer_bypass_en_get(a_uint32_t dev_id, fal_policer_frame_type_t frame_type,
+	a_bool_t *enable)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_policer_bypass_en_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_policer_bypass_en_get(dev_id, frame_type, enable);
+	return rv;
+}
+
+#endif
+sw_error_t
+_fal_policer_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_policer_time_slot_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_policer_time_slot_set(dev_id, timeslot);
+    return rv;
+}
+
+sw_error_t
+_fal_policer_bypass_en_set(a_uint32_t dev_id, fal_policer_frame_type_t frame_type,
+	a_bool_t enable)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_policer_bypass_en_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_policer_bypass_en_set(dev_id, frame_type, enable);
+	return rv;
+}
+
+#ifndef IN_POLICER_MINI
+sw_error_t
+_fal_port_policer_compensation_byte_get(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t *length)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_compensation_byte_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_compensation_byte_get(dev_id, port_id, length);
+    return rv;
+}
+#endif
+sw_error_t
+_fal_port_policer_compensation_byte_set(a_uint32_t dev_id, a_uint32_t port_id,
+			a_uint32_t length)
+
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_compensation_byte_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_compensation_byte_set(dev_id, port_id, length);
+    return rv;
+}
+
+#ifndef IN_POLICER_MINI
+sw_error_t
+_fal_policer_global_counter_get(a_uint32_t dev_id,
+		fal_policer_global_counter_t *counter)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_policer_global_counter_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_policer_global_counter_get(dev_id, counter);
+	return rv;
+}
+
+/*insert flag for inner fal, don't remove it*/
+
+sw_error_t
+fal_acl_policer_counter_get(a_uint32_t dev_id, a_uint32_t index,
+		fal_policer_counter_t *counter)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_policer_counter_get(dev_id, index, counter);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_policer_counter_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_policer_counter_t *counter)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_policer_counter_get(dev_id, port_id, counter);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_policer_entry_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_policer_config_t *policer, fal_policer_action_t *action)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_policer_entry_get(dev_id, port_id, policer, action);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_policer_entry_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_policer_config_t *policer, fal_policer_action_t *action)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_policer_entry_set(dev_id, port_id, policer, action);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_acl_policer_entry_get(a_uint32_t dev_id, a_uint32_t index,
+		fal_policer_config_t *policer, fal_policer_action_t *action)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_policer_entry_get(dev_id, index, policer, action);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_acl_policer_entry_set(a_uint32_t dev_id, a_uint32_t index,
+		fal_policer_config_t *policer, fal_policer_action_t *action)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_acl_policer_entry_set(dev_id, index, policer, action);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_policer_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_policer_timeslot_get(dev_id, timeslot);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_policer_bypass_en_get(a_uint32_t dev_id, fal_policer_frame_type_t frame_type,
+	a_bool_t *enable)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_policer_bypass_en_get(dev_id, frame_type, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+sw_error_t
+fal_policer_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_policer_timeslot_set(dev_id, timeslot);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_policer_bypass_en_set(a_uint32_t dev_id, fal_policer_frame_type_t frame_type,
+	a_bool_t enable)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_policer_bypass_en_set(dev_id, frame_type, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_POLICER_MINI
+sw_error_t
+fal_port_policer_compensation_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+				a_uint32_t *length)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_policer_compensation_byte_get(dev_id, port_id, length);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+sw_error_t
+fal_port_policer_compensation_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+			a_uint32_t length)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_policer_compensation_byte_set(dev_id, port_id, length);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_POLICER_MINI
+sw_error_t
+fal_policer_global_counter_get(a_uint32_t dev_id,
+		fal_policer_global_counter_t *counter)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_policer_global_counter_get(dev_id, counter);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+#ifndef IN_POLICER_MINI
+EXPORT_SYMBOL(fal_acl_policer_counter_get);
+EXPORT_SYMBOL(fal_port_policer_counter_get);
+EXPORT_SYMBOL(fal_port_policer_entry_get);
+EXPORT_SYMBOL(fal_port_policer_entry_set);
+EXPORT_SYMBOL(fal_acl_policer_entry_get);
+EXPORT_SYMBOL(fal_acl_policer_entry_set);
+EXPORT_SYMBOL(fal_policer_timeslot_get);
+EXPORT_SYMBOL(fal_port_policer_compensation_byte_get);
+EXPORT_SYMBOL(fal_policer_global_counter_get);
+EXPORT_SYMBOL(fal_policer_bypass_en_get);
+#endif
+EXPORT_SYMBOL(fal_policer_timeslot_set);
+EXPORT_SYMBOL(fal_port_policer_compensation_byte_set);
+EXPORT_SYMBOL(fal_policer_bypass_en_set);
+
+/*insert flag for outter fal, don't remove it*/
diff --git a/qca-ssdk/src/fal/fal_port_ctrl.c b/qca-ssdk/src/fal/fal_port_ctrl.c
new file mode 100644
index 0000000..8f3d92a
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_port_ctrl.c
@@ -0,0 +1,3728 @@
+/*
+ * Copyright (c) 2012, 2015-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*qca808x_start*/
+/**
+ * @defgroup fal_port_ctrl FAL_PORT_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "fal_port_ctrl.h"
+#include "hsl_api.h"
+/*qca808x_end*/
+#include "adpt.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+/*qca808x_start*/
+static sw_error_t
+_fal_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id,
+		      fal_port_duplex_t duplex)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_duplex_set != NULL) {
+        rv = p_adpt_api->adpt_port_duplex_set(dev_id, port_id, duplex);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_duplex_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_duplex_set (dev_id, port_id, duplex);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_speed_set (a_uint32_t dev_id, fal_port_t port_id,
+		     fal_port_speed_t speed)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_speed_set != NULL) {
+        rv = p_adpt_api->adpt_port_speed_set(dev_id, port_id, speed);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_speed_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_speed_set (dev_id, port_id, speed);
+  return rv;
+}
+/*qca808x_end*/
+static sw_error_t
+_fal_port_flowctrl_set (a_uint32_t dev_id, fal_port_t port_id,
+			a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_flowctrl_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_flowctrl_set(dev_id, port_id, enable);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_flowctrl_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_flowctrl_set (dev_id, port_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_flowctrl_forcemode_set (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+  adpt_api_t *p_adpt_api;
+
+  if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+    if (NULL == p_adpt_api->adpt_port_flowctrl_forcemode_set)
+      return SW_NOT_SUPPORTED;
+
+  rv = p_adpt_api->adpt_port_flowctrl_forcemode_set(dev_id, port_id, enable);
+  return rv;
+  }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_flowctrl_forcemode_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_flowctrl_forcemode_set (dev_id, port_id, enable);
+  return rv;
+}
+/*qca808x_start*/
+static sw_error_t
+_fal_port_speed_get (a_uint32_t dev_id, fal_port_t port_id,
+		     fal_port_speed_t * pspeed)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_speed_get != NULL) {
+        rv = p_adpt_api->adpt_port_speed_get(dev_id, port_id, pspeed);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_speed_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_speed_get (dev_id, port_id, pspeed);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id,
+		      fal_port_duplex_t * pduplex)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_duplex_get != NULL) {
+        rv = p_adpt_api->adpt_port_duplex_get(dev_id, port_id, pduplex);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_duplex_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_duplex_get (dev_id, port_id, pduplex);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_autoneg_enable != NULL) {
+        rv = p_adpt_api->adpt_port_autoneg_enable(dev_id, port_id);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_autoneg_enable)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_autoneg_enable (dev_id, port_id);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_autoneg_restart != NULL) {
+        rv = p_adpt_api->adpt_port_autoneg_restart(dev_id, port_id);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_autoneg_restart)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_autoneg_restart (dev_id, port_id);
+  return rv;
+}
+
+
+static sw_error_t
+_fal_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id,
+			   a_uint32_t autoadv)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_autoneg_adv_set != NULL) {
+        rv = p_adpt_api->adpt_port_autoneg_adv_set(dev_id, port_id, autoadv);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_autoneg_adv_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_autoneg_adv_set (dev_id, port_id, autoadv);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * status)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_autoneg_status_get != NULL) {
+        rv = p_adpt_api->adpt_port_autoneg_status_get(dev_id, port_id, status);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_autoneg_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_autoneg_status_get (dev_id, port_id, status);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id,
+			   a_uint32_t * autoadv)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_autoneg_adv_get != NULL) {
+        rv = p_adpt_api->adpt_port_autoneg_adv_get(dev_id, port_id, autoadv);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_autoneg_adv_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_autoneg_adv_get (dev_id, port_id, autoadv);
+  return rv;
+}
+/*qca808x_end*/
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_fal_port_hdr_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_hdr_status_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_hdr_status_set (dev_id, port_id, enable);
+  return rv;
+}
+
+
+static sw_error_t
+_fal_port_hdr_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_hdr_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_hdr_status_get (dev_id, port_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_flowctrl_get (a_uint32_t dev_id, fal_port_t port_id,
+			a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_flowctrl_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_flowctrl_get(dev_id, port_id, enable);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_flowctrl_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_flowctrl_get (dev_id, port_id, enable);
+  return rv;
+}
+
+
+
+static sw_error_t
+_fal_port_flowctrl_forcemode_get (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+  adpt_api_t *p_adpt_api;
+
+  if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+    if (NULL == p_adpt_api->adpt_port_flowctrl_forcemode_get)
+      return SW_NOT_SUPPORTED;
+
+  rv = p_adpt_api->adpt_port_flowctrl_forcemode_get(dev_id, port_id, enable);
+  return rv;
+  }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_flowctrl_forcemode_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_flowctrl_forcemode_get (dev_id, port_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_powersave_set != NULL) {
+        rv = p_adpt_api->adpt_port_powersave_set(dev_id, port_id, enable);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_powersave_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_powersave_set (dev_id, port_id, enable);
+  return rv;
+}
+
+
+static sw_error_t
+_fal_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_powersave_get != NULL) {
+        rv = p_adpt_api->adpt_port_powersave_get(dev_id, port_id, enable);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_powersave_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_powersave_get (dev_id, port_id, enable);
+  return rv;
+}
+/*qca808x_start*/
+static sw_error_t
+_fal_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_hibernate_set != NULL) {
+        rv = p_adpt_api->adpt_port_hibernate_set(dev_id, port_id, enable);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_hibernate_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_hibernate_set (dev_id, port_id, enable);
+  return rv;
+}
+
+
+static sw_error_t
+_fal_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_hibernate_get != NULL) {
+        rv = p_adpt_api->adpt_port_hibernate_get(dev_id, port_id, enable);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_hibernate_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_hibernate_get (dev_id, port_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+	       a_uint32_t * cable_status, a_uint32_t * cable_len)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_cdt != NULL) {
+        rv = p_adpt_api->adpt_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_cdt)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_cdt (dev_id, port_id, mdi_pair, cable_status, cable_len);
+  return rv;
+}
+/*qca808x_end*/
+static sw_error_t
+_fal_port_rxhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+			  fal_port_header_mode_t * mode)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_rxhdr_mode_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_rxhdr_mode_get (dev_id, port_id, mode);
+  return rv;
+}
+static sw_error_t
+_fal_port_txhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+			  fal_port_header_mode_t * mode)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_txhdr_mode_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_txhdr_mode_get (dev_id, port_id, mode);
+  return rv;
+}
+static sw_error_t
+_fal_header_type_get (a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->header_type_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->header_type_get (dev_id, enable, type);
+  return rv;
+}
+#endif
+static sw_error_t
+_fal_port_rxhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+			  fal_port_header_mode_t mode)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_rxhdr_mode_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_rxhdr_mode_set (dev_id, port_id, mode);
+  return rv;
+}
+
+
+
+static sw_error_t
+_fal_port_txhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+			  fal_port_header_mode_t mode)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_txhdr_mode_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_txhdr_mode_set (dev_id, port_id, mode);
+  return rv;
+}
+
+
+
+static sw_error_t
+_fal_header_type_set (a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->header_type_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->header_type_set (dev_id, enable, type);
+  return rv;
+}
+
+
+
+static sw_error_t
+_fal_port_txmac_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_txmac_status_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_txmac_status_set(dev_id, port_id, enable);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_txmac_status_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_txmac_status_set (dev_id, port_id, enable);
+  return rv;
+}
+
+
+
+static sw_error_t
+_fal_port_rxmac_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_rxmac_status_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_rxmac_status_set(dev_id, port_id, enable);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_rxmac_status_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_rxmac_status_set (dev_id, port_id, enable);
+  return rv;
+}
+
+
+
+static sw_error_t
+_fal_port_txfc_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_txfc_status_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_txfc_status_set(dev_id, port_id, enable);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_txfc_status_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_txfc_status_set (dev_id, port_id, enable);
+  return rv;
+}
+
+
+
+static sw_error_t
+_fal_port_rxfc_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_rxfc_status_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_rxfc_status_set(dev_id, port_id, enable);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_rxfc_status_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_rxfc_status_set (dev_id, port_id, enable);
+  return rv;
+}
+static sw_error_t
+_fal_port_txfc_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_txfc_status_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_txfc_status_get(dev_id, port_id, enable);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_txfc_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_txfc_status_get (dev_id, port_id, enable);
+  return rv;
+}
+static sw_error_t
+_fal_port_rxfc_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_rxfc_status_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_rxfc_status_get(dev_id, port_id, enable);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_rxfc_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_rxfc_status_get (dev_id, port_id, enable);
+  return rv;
+}
+/*qca808x_start*/
+static sw_error_t
+_fal_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t * status)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_link_status_get != NULL) {
+        rv = p_adpt_api->adpt_port_link_status_get(dev_id, port_id, status);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_link_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_link_status_get (dev_id, port_id, status);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_power_off (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_power_off != NULL) {
+        rv = p_adpt_api->adpt_port_power_off(dev_id, port_id);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_power_off)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_power_off (dev_id, port_id);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_power_on (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_power_on != NULL) {
+        rv = p_adpt_api->adpt_port_power_on(dev_id, port_id);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_power_on)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_power_on (dev_id, port_id);
+  return rv;
+}
+/*qca808x_end*/
+static sw_error_t
+_fal_port_link_forcemode_set (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_link_forcemode_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_link_forcemode_set (dev_id, port_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_link_forcemode_get (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_link_forcemode_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_link_forcemode_get (dev_id, port_id, enable);
+  return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_fal_port_txmac_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_txmac_status_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_txmac_status_get(dev_id, port_id, enable);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_txmac_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_txmac_status_get (dev_id, port_id, enable);
+  return rv;
+}
+static sw_error_t
+_fal_port_rxmac_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_rxmac_status_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_rxmac_status_get(dev_id, port_id, enable);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_rxmac_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_rxmac_status_get (dev_id, port_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_bp_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_bp_status_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_bp_status_set (dev_id, port_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_bp_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_bp_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_bp_status_get (dev_id, port_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_ports_link_status_get (a_uint32_t dev_id, a_uint32_t * status)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_ports_link_status_get != NULL) {
+        rv = p_adpt_api->adpt_ports_link_status_get(dev_id, status);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->ports_link_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->ports_link_status_get (dev_id, status);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_mac_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_mac_loopback_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_mac_loopback_set(dev_id, port_id, enable);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_mac_loopback_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_mac_loopback_set (dev_id, port_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_mac_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_mac_loopback_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_mac_loopback_get(dev_id, port_id, enable);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_mac_loopback_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_mac_loopback_get (dev_id, port_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_congestion_drop_set (a_uint32_t dev_id, fal_port_t port_id,
+			       a_uint32_t queue_id, a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_congestion_drop_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_congestion_drop_set (dev_id, port_id, queue_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_congestion_drop_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_uint32_t queue_id, a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_congestion_drop_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_congestion_drop_get (dev_id, port_id, queue_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_ring_flow_ctrl_thres_set (a_uint32_t dev_id, a_uint32_t ring_id,
+			       a_uint8_t on_thres, a_uint8_t off_thres)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->ring_flow_ctrl_thres_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->ring_flow_ctrl_thres_set (dev_id, ring_id, on_thres, off_thres);
+  return rv;
+}
+
+static sw_error_t
+_fal_ring_flow_ctrl_thres_get (a_uint32_t dev_id, a_uint32_t ring_id,
+			       a_uint8_t * on_thres, a_uint8_t * off_thres)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->ring_flow_ctrl_thres_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->ring_flow_ctrl_thres_get (dev_id, ring_id, on_thres, off_thres);
+  return rv;
+}
+/*qca808x_start*/
+static sw_error_t
+_fal_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_8023az_set != NULL) {
+        rv = p_adpt_api->adpt_port_8023az_set(dev_id, port_id, enable);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_8023az_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_8023az_set (dev_id, port_id, enable);
+  return rv;
+}
+
+
+static sw_error_t
+_fal_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id,
+		      a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_8023az_get != NULL) {
+        rv = p_adpt_api->adpt_port_8023az_get(dev_id, port_id, enable);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_8023az_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_8023az_get (dev_id, port_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_mdix_set (a_uint32_t dev_id, fal_port_t port_id,
+		    fal_port_mdix_mode_t mode)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_mdix_set != NULL) {
+        rv = p_adpt_api->adpt_port_mdix_set(dev_id, port_id, mode);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_mdix_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_mdix_set (dev_id, port_id, mode);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id,
+		    fal_port_mdix_mode_t * mode)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_mdix_get != NULL) {
+        rv = p_adpt_api->adpt_port_mdix_get(dev_id, port_id, mode);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_mdix_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_mdix_get (dev_id, port_id, mode);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			   fal_port_mdix_status_t * mode)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_mdix_status_get != NULL) {
+        rv = p_adpt_api->adpt_port_mdix_status_get(dev_id, port_id, mode);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_mdix_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_mdix_status_get (dev_id, port_id, mode);
+  return rv;
+}
+/*qca808x_end*/
+static sw_error_t
+_fal_port_combo_prefer_medium_set (a_uint32_t dev_id, fal_port_t port_id,
+				   fal_port_medium_t medium)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_combo_prefer_medium_set != NULL) {
+        rv = p_adpt_api->adpt_port_combo_prefer_medium_set(dev_id, port_id, medium);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_combo_prefer_medium_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_combo_prefer_medium_set (dev_id, port_id, medium);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_combo_prefer_medium_get (a_uint32_t dev_id, fal_port_t port_id,
+				   fal_port_medium_t * medium)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_combo_prefer_medium_get != NULL) {
+        rv = p_adpt_api->adpt_port_combo_prefer_medium_get(dev_id, port_id, medium);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_combo_prefer_medium_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_combo_prefer_medium_get (dev_id, port_id, medium);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_combo_medium_status_get (a_uint32_t dev_id, fal_port_t port_id,
+				   fal_port_medium_t * medium)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_combo_medium_status_get != NULL) {
+        rv = p_adpt_api->adpt_port_combo_medium_status_get(dev_id, port_id, medium);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_combo_medium_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_combo_medium_status_get (dev_id, port_id, medium);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_combo_fiber_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_fiber_mode_t mode)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_combo_fiber_mode_set != NULL) {
+        rv = p_adpt_api->adpt_port_combo_fiber_mode_set(dev_id, port_id, mode);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_combo_fiber_mode_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_combo_fiber_mode_set (dev_id, port_id, mode);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_combo_fiber_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_fiber_mode_t * mode)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_combo_fiber_mode_get != NULL) {
+        rv = p_adpt_api->adpt_port_combo_fiber_mode_get(dev_id, port_id, mode);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_combo_fiber_mode_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_combo_fiber_mode_get (dev_id, port_id, mode);
+  return rv;
+}
+/*qca808x_start*/
+static sw_error_t
+_fal_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_local_loopback_set != NULL) {
+        rv = p_adpt_api->adpt_port_local_loopback_set(dev_id, port_id, enable);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_local_loopback_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_local_loopback_set (dev_id, port_id, enable);
+  return rv;
+}
+
+
+static sw_error_t
+_fal_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_local_loopback_get != NULL) {
+        rv = p_adpt_api->adpt_port_local_loopback_get(dev_id, port_id, enable);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_local_loopback_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_local_loopback_get (dev_id, port_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_remote_loopback_set != NULL) {
+        rv = p_adpt_api->adpt_port_remote_loopback_set(dev_id, port_id, enable);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_remote_loopback_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_remote_loopback_set (dev_id, port_id, enable);
+  return rv;
+}
+
+
+static sw_error_t
+_fal_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_remote_loopback_get!= NULL) {
+        rv = p_adpt_api->adpt_port_remote_loopback_get(dev_id, port_id, enable);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_remote_loopback_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_remote_loopback_get (dev_id, port_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_reset (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_reset != NULL) {
+        rv = p_adpt_api->adpt_port_reset(dev_id, port_id);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_reset)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_reset (dev_id, port_id);
+  return rv;
+}
+
+
+static sw_error_t
+_fal_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id,a_uint16_t * org_id, a_uint16_t * rev_id)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_phy_id_get != NULL) {
+        rv = p_adpt_api->adpt_port_phy_id_get(dev_id, port_id, org_id, rev_id);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_phy_id_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_phy_id_get (dev_id, port_id,org_id,rev_id);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_wol_status_set != NULL) {
+        rv = p_adpt_api->adpt_port_wol_status_set(dev_id, port_id, enable);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_wol_status_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_wol_status_set (dev_id, port_id,enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_wol_status_get != NULL) {
+        rv = p_adpt_api->adpt_port_wol_status_get(dev_id, port_id, enable);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_wol_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_wol_status_get (dev_id, port_id,enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id, fal_mac_addr_t * mac)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_magic_frame_mac_set != NULL) {
+        rv = p_adpt_api->adpt_port_magic_frame_mac_set(dev_id, port_id, mac);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_magic_frame_mac_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_magic_frame_mac_set (dev_id, port_id, mac);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id, fal_mac_addr_t * mac)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_magic_frame_mac_get != NULL) {
+        rv = p_adpt_api->adpt_port_magic_frame_mac_get(dev_id, port_id, mac);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_magic_frame_mac_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_magic_frame_mac_get (dev_id, port_id, mac);
+  return rv;
+}
+/*qca808x_end*/
+static sw_error_t
+_fal_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id, fal_port_interface_mode_t  mode)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_interface_mode_set != NULL) {
+        rv = p_adpt_api->adpt_port_interface_mode_set(dev_id, port_id, mode);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_interface_mode_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_interface_mode_set (dev_id, port_id, mode);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id, fal_port_interface_mode_t * mode)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_interface_mode_get != NULL) {
+        rv = p_adpt_api->adpt_port_interface_mode_get(dev_id, port_id, mode);
+        return rv;
+    }
+
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_interface_mode_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_interface_mode_get (dev_id, port_id, mode);
+  return rv;
+}
+/*qca808x_start*/
+static sw_error_t
+_fal_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id, fal_port_interface_mode_t * mode)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_interface_mode_status_get != NULL) {
+        rv = p_adpt_api->adpt_port_interface_mode_status_get(dev_id, port_id, mode);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_interface_mode_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_interface_mode_status_get (dev_id, port_id, mode);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_counter_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_counter_set != NULL) {
+        rv = p_adpt_api->adpt_port_counter_set(dev_id, port_id, enable);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_counter_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_counter_set (dev_id, port_id, enable);
+  return rv;
+}
+
+
+static sw_error_t
+_fal_port_counter_get (a_uint32_t dev_id, fal_port_t port_id,
+		      a_bool_t * enable)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_counter_get != NULL) {
+        rv = p_adpt_api->adpt_port_counter_get(dev_id, port_id, enable);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_counter_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_counter_get (dev_id, port_id, enable);
+  return rv;
+}
+
+static sw_error_t
+_fal_port_counter_show (a_uint32_t dev_id, fal_port_t port_id, fal_port_counter_info_t * counter_info)
+{
+  sw_error_t rv;
+  hsl_api_t *p_api;
+/*qca808x_end*/
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL &&
+        p_adpt_api->adpt_port_counter_show != NULL) {
+        rv = p_adpt_api->adpt_port_counter_show(dev_id, port_id, counter_info);
+        return rv;
+    }
+/*qca808x_start*/
+  SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+  if (NULL == p_api->port_counter_show)
+    return SW_NOT_SUPPORTED;
+
+  rv = p_api->port_counter_show (dev_id, port_id, counter_info);
+  return rv;
+}
+/*qca808x_end*/
+#endif
+
+sw_error_t
+_fal_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t max_frame)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_max_frame_size_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_max_frame_size_set(dev_id, port_id, max_frame);
+    return rv;
+}
+
+sw_error_t
+_fal_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t *max_frame)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_max_frame_size_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_max_frame_size_get(dev_id, port_id, max_frame);
+	return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+_fal_port_mru_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_mru_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_mru_set(dev_id, port_id, ctrl);
+    return rv;
+}
+sw_error_t
+_fal_port_mru_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_mru_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_mru_get(dev_id, port_id, ctrl);
+    return rv;
+}
+sw_error_t
+_fal_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_mtu_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_mtu_set(dev_id, port_id, ctrl);
+    return rv;
+}
+
+sw_error_t
+_fal_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_mtu_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_mtu_get(dev_id, port_id, ctrl);
+    return rv;
+}
+
+sw_error_t
+_fal_port_source_filter_get(a_uint32_t dev_id,
+		fal_port_t port_id, a_bool_t * enable)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_source_filter_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_source_filter_get(dev_id, port_id, enable);
+    return rv;
+}
+
+sw_error_t
+_fal_port_source_filter_set(a_uint32_t dev_id,
+		fal_port_t port_id, a_bool_t enable)
+{
+    adpt_api_t *p_api;
+    sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_source_filter_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_source_filter_set(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_source_filter_config_set(a_uint32_t dev_id,
+	fal_port_t port_id, fal_src_filter_config_t *src_filter_config)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_source_filter_config_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_source_filter_config_set(dev_id, port_id,
+			src_filter_config);
+	return rv;
+}
+
+static sw_error_t
+_fal_port_source_filter_config_get(a_uint32_t dev_id,
+	fal_port_t port_id, fal_src_filter_config_t *src_filter_config)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_source_filter_config_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_source_filter_config_get(dev_id, port_id,
+			src_filter_config);
+	return rv;
+}
+
+static sw_error_t
+_fal_port_interface_3az_status_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t enable)
+{
+
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_interface_3az_status_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_interface_3az_status_set(dev_id, port_id, enable);
+	return rv;
+
+}
+
+static sw_error_t
+_fal_port_interface_3az_status_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t * enable)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_interface_3az_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_interface_3az_status_get(dev_id, port_id, enable);
+	return rv;
+
+}
+
+static sw_error_t
+_fal_port_promisc_mode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+	adpt_api_t *p_adpt_api;
+
+	if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+		if (NULL == p_adpt_api->adpt_port_promisc_mode_get) {
+			return SW_NOT_SUPPORTED;
+		}
+
+		rv = p_adpt_api->adpt_port_promisc_mode_get(dev_id, port_id, enable);
+		return rv;
+	}
+
+	return rv;
+}
+#endif
+
+static sw_error_t
+_fal_port_promisc_mode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	adpt_api_t *p_adpt_api;
+
+	if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+		if (NULL == p_adpt_api->adpt_port_promisc_mode_set) {
+			return SW_NOT_SUPPORTED;
+		}
+
+		rv = p_adpt_api->adpt_port_promisc_mode_set(dev_id, port_id, enable);
+		return rv;
+	}
+
+	return rv;
+}
+
+static sw_error_t
+_fal_port_interface_eee_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
+	fal_port_eee_cfg_t *port_eee_cfg)
+{
+
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_interface_eee_cfg_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_interface_eee_cfg_set(dev_id, port_id, port_eee_cfg);
+	return rv;
+
+}
+
+static sw_error_t
+_fal_port_interface_eee_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
+	fal_port_eee_cfg_t *port_eee_cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_interface_eee_cfg_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_interface_eee_cfg_get(dev_id, port_id, port_eee_cfg);
+	return rv;
+
+}
+static sw_error_t
+_fal_switch_port_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
+	fal_loopback_config_t *loopback_cfg)
+{
+
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_switch_port_loopback_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_switch_port_loopback_set(dev_id, port_id, loopback_cfg);
+	return rv;
+
+}
+
+static sw_error_t
+_fal_switch_port_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
+	fal_loopback_config_t *loopback_cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+	if (NULL == p_api->adpt_switch_port_loopback_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_switch_port_loopback_get(dev_id, port_id, loopback_cfg);
+	return rv;
+
+}
+
+/*qca808x_start*/
+/*insert flag for inner fal, don't remove it*/
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id,
+		     fal_port_duplex_t duplex)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_duplex_set (dev_id, port_id, duplex);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_speed_set (a_uint32_t dev_id, fal_port_t port_id,
+		    fal_port_speed_t speed)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_speed_set (dev_id, port_id, speed);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id,
+		     fal_port_duplex_t * pduplex)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_duplex_get (dev_id, port_id, pduplex);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_speed_get (a_uint32_t dev_id, fal_port_t port_id,
+		    fal_port_speed_t * pspeed)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_speed_get (dev_id, port_id, pspeed);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_autoneg_enable (dev_id, port_id);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_autoneg_restart (dev_id, port_id);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ *   @details  Comments:
+ *   auto negotiation advtisement ability is defined by macro such as
+ *   FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id,
+			  a_uint32_t autoadv)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_autoneg_adv_set (dev_id, port_id, autoadv);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t * status)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_autoneg_status_get (dev_id, port_id, status);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id,
+			  a_uint32_t * autoadv)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_autoneg_adv_get (dev_id, port_id, autoadv);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/*qca808x_end*/
+#ifndef IN_PORTCONTROL_MINI
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_hdr_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_hdr_status_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_hdr_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_hdr_status_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+
+/**
+ * @brief Get flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_flowctrl_get (a_uint32_t dev_id, fal_port_t port_id,
+		       a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_flowctrl_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+
+
+/**
+ * @brief Get flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_flowctrl_forcemode_get (a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_flowctrl_forcemode_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id,
+			a_bool_t enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_powersave_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id,
+			a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_powersave_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/*qca808x_start*/
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id,
+			a_bool_t enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_hibernate_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id,
+			a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_hibernate_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief cable diagnostic test.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mdi_pair mdi pair id
+ * @param[out] cable_status cable status
+ * @param[out] cable_len cable len
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+	      a_uint32_t * cable_status, a_uint32_t * cable_len)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_cdt (dev_id, port_id, mdi_pair, cable_status, cable_len);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/*qca808x_end*/
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_rxhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+			 fal_port_header_mode_t * mode)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_rxhdr_mode_get (dev_id, port_id, mode);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_txhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+			 fal_port_header_mode_t * mode)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_txhdr_mode_get (dev_id, port_id, mode);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/**
+ * @brief Get status of Atheros header type value on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] type header type value
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_header_type_get (a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_header_type_get (dev_id, enable, type);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/**
+ * @brief Get status of txmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_txmac_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_txmac_status_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/**
+ * @brief Get status of rxmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_rxmac_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_rxmac_status_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+#endif
+/**
+ * @brief Set flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_flowctrl_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_flowctrl_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_flowctrl_forcemode_set (a_uint32_t dev_id, fal_port_t port_id,
+				 a_bool_t enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_flowctrl_forcemode_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_rxhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+			 fal_port_header_mode_t mode)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_rxhdr_mode_set (dev_id, port_id, mode);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_txhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+			 fal_port_header_mode_t mode)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_txhdr_mode_set (dev_id, port_id, mode);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+
+
+/**
+ * @brief Set status of Atheros header type value on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] type header type value
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_header_type_set (a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
+{
+  sw_error_t rv;
+  FAL_API_LOCK;
+  rv = _fal_header_type_set (dev_id, enable, type);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+
+
+/**
+ * @brief Set status of txmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_txmac_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t enable)
+{
+  sw_error_t rv;
+  FAL_API_LOCK;
+  rv = _fal_port_txmac_status_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+
+
+/**
+ * @brief Set status of rxmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_rxmac_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t enable)
+{
+  sw_error_t rv;
+  FAL_API_LOCK;
+  rv = _fal_port_rxmac_status_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+
+
+/**
+ * @brief Set status of tx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_txfc_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable)
+{
+  sw_error_t rv;
+  FAL_API_LOCK;
+  rv = _fal_port_txfc_status_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+
+
+/**
+ * @brief Set status of rx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_rxfc_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_rxfc_status_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/**
+ * @brief Set status of rx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_rxfc_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_rxfc_status_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/**
+ * @brief Get status of tx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_txfc_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_txfc_status_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/*qca808x_start*/
+/**
+ * @brief Get link status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status link status up (A_TRUE) or down (A_FALSE)
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * status)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_link_status_get (dev_id, port_id, status);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief power off on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_power_off (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_power_off (dev_id, port_id);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief power on on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_power_on (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_power_on (dev_id, port_id);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/*qca808x_end*/
+/**
+ * @brief Set link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_link_forcemode_set (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_link_forcemode_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_link_forcemode_get (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_link_forcemode_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+/**
+ * @brief Set status of back pressure on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_bp_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			a_bool_t enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_bp_status_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set status of back pressure on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_bp_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_bp_status_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get link status on all ports.
+ * @param[in] dev_id device id
+ * @param[out] status link status bitmap and bit 0 for port 0, bit 1 for port 1, ...etc.
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ports_link_status_get (a_uint32_t dev_id, a_uint32_t * status)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_ports_link_status_get (dev_id, status);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+
+/**
+ * @brief Set loopback on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_mac_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_mac_loopback_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_mac_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_mac_loopback_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set congestion drop on a particular port queue.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_congestion_drop_set (a_uint32_t dev_id, fal_port_t port_id,
+			      a_uint32_t queue_id, a_bool_t enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_congestion_drop_set (dev_id, port_id, queue_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get congestion drop on a particular port queue.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue_id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_congestion_drop_get (a_uint32_t dev_id, fal_port_t port_id,
+			      a_uint32_t queue_id, a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_congestion_drop_get (dev_id, port_id, queue_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set flow control threshold on a DMA ring.
+ * @param[in] dev_id device id
+ * @param[in] ring_id ring_id
+ * @param[in] on_thres on_thres
+ * @param[in] off_thres on_thres
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ring_flow_ctrl_thres_set (a_uint32_t dev_id, a_uint32_t ring_id,
+			      a_uint8_t on_thres, a_uint8_t off_thres)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_ring_flow_ctrl_thres_set (dev_id, ring_id, on_thres, off_thres);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get flow control threshold on a DMA ring.
+ * @param[in] dev_id device id
+ * @param[in] ring_id ring_id
+ * @param[out] on_thres on_thres
+ * @param[out] off_thres on_thres
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ring_flow_ctrl_thres_get (a_uint32_t dev_id, a_uint32_t ring_id,
+			      a_uint8_t * on_thres, a_uint8_t * off_thres)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_ring_flow_ctrl_thres_get (dev_id, ring_id, on_thres, off_thres);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/*qca808x_start*/
+/**
+ * @brief Set 8023az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_8023az_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get 8023az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_8023az_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set mdix mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] set mdix mode [mdx , mdix or auto]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_mdix_set (a_uint32_t dev_id, fal_port_t port_id,
+		   fal_port_mdix_mode_t mode)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_mdix_set (dev_id, port_id, mode);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get mdix on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] set mdx ,mdix or auto 
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id,
+		   fal_port_mdix_mode_t * mode)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_mdix_get (dev_id, port_id, mode);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get mdix status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] set mdx ,mdix 
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			  fal_port_mdix_status_t * mode)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_mdix_status_get (dev_id, port_id, mode);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/*qca808x_end*/
+/**
+ * @brief Set combo prefer medium  on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] set combo prefer medium [fiber for copper]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_combo_prefer_medium_set (a_uint32_t dev_id, a_uint32_t port_id,
+				  fal_port_medium_t medium)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_combo_prefer_medium_set (dev_id, port_id, medium);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get combo prefer medium  on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] set combo prefer medium [fiber for copper]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_combo_prefer_medium_get (a_uint32_t dev_id, a_uint32_t port_id,
+				  fal_port_medium_t * medium)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_combo_prefer_medium_get (dev_id, port_id, medium);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get combo  medium  status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] get combo [fiber for copper]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_combo_medium_status_get (a_uint32_t dev_id, a_uint32_t port_id,
+				  fal_port_medium_t * medium)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_combo_medium_status_get (dev_id, port_id, medium);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set combo fiber mode  on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] get combo fiber mode [1000bx or 100fx]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_combo_fiber_mode_set (a_uint32_t dev_id, a_uint32_t port_id,
+			       fal_port_fiber_mode_t mode)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_combo_fiber_mode_set (dev_id, port_id, mode);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get combo fiber mode  on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] get combo fiber mode [1000bx or 100fx]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_combo_fiber_mode_get (a_uint32_t dev_id, a_uint32_t port_id,
+			       fal_port_fiber_mode_t * mode)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_combo_fiber_mode_get (dev_id, port_id, mode);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/*qca808x_start*/
+/**
+ * @brief Set local loopback  on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_local_loopback_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get local loopback status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_local_loopback_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set remote loopback  on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_remote_loopback_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get remote loopback status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_remote_loopback_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief software reset on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_reset (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_reset (dev_id, port_id);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief phy id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id, a_uint16_t * org_id, a_uint16_t * rev_id)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_phy_id_get (dev_id, port_id,org_id,rev_id);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief wol status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_wol_status_set (dev_id, port_id,enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief wol status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_wol_status_get (dev_id, port_id,enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief magic frame mac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id, fal_mac_addr_t * mac)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_magic_frame_mac_set (dev_id, port_id,mac);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief magic frame mac  on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id, fal_mac_addr_t * mac)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_magic_frame_mac_get (dev_id, port_id,mac);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/*qca808x_end*/
+/**
+ * @brief interface mode  on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id, fal_port_interface_mode_t  mode)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_interface_mode_set (dev_id, port_id,mode);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief interface mode  on a particular port.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+ static sw_error_t
+_fal_port_interface_mode_apply (a_uint32_t dev_id)
+{
+  sw_error_t rv = SW_OK;
+  adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_interface_mode_apply)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_interface_mode_apply(dev_id);
+        return rv;
+    }
+
+  return rv;
+}
+
+sw_error_t
+fal_port_interface_mode_apply (a_uint32_t dev_id)
+{
+  sw_error_t rv = SW_OK;
+
+  FAL_API_LOCK;
+  rv = _fal_port_interface_mode_apply (dev_id);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief interface mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id, fal_port_interface_mode_t * mode)
+{
+  sw_error_t rv = SW_OK;
+
+  FAL_API_LOCK;
+  rv = _fal_port_interface_mode_get (dev_id, port_id,mode);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/*qca808x_start*/
+/**
+ * @brief interface mode status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out]
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id, fal_port_interface_mode_t * mode)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_interface_mode_status_get (dev_id, port_id,mode);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set counter status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_debug_phycounter_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_counter_set (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get counter status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_debug_phycounter_get (a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_counter_get (dev_id, port_id, enable);
+  FAL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get counter statistics on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] counter frame number
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_debug_phycounter_show (a_uint32_t dev_id, fal_port_t port_id, fal_port_counter_info_t* port_counter_info)
+{
+  sw_error_t rv;
+
+  FAL_API_LOCK;
+  rv = _fal_port_counter_show (dev_id, port_id, port_counter_info);
+  FAL_API_UNLOCK;
+  return rv;
+}
+/*qca808x_end*/
+#endif
+
+sw_error_t
+fal_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t max_frame)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_max_frame_size_set(dev_id, port_id, max_frame);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t *max_frame)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_max_frame_size_get(dev_id, port_id, max_frame);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+fal_port_mru_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_mru_set(dev_id, port_id, ctrl);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_mru_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mru_ctrl_t *ctrl)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_mru_get(dev_id, port_id, ctrl);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_mtu_set(dev_id, port_id, ctrl);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_mtu_ctrl_t *ctrl)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_mtu_get(dev_id, port_id, ctrl);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_source_filter_status_get(a_uint32_t dev_id,
+		fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_source_filter_get(dev_id,
+                    port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_source_filter_enable(a_uint32_t dev_id,
+		fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_source_filter_set(dev_id,
+                    port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_source_filter_config_set(a_uint32_t dev_id,
+		fal_port_t port_id, fal_src_filter_config_t *src_filter_config)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_source_filter_config_set(dev_id, port_id, src_filter_config);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_source_filter_config_get(a_uint32_t dev_id,
+		fal_port_t port_id, fal_src_filter_config_t *src_filter_config)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_source_filter_config_get(dev_id, port_id, src_filter_config);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_interface_3az_status_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_interface_3az_status_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_interface_3az_status_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_interface_3az_status_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_promisc_mode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_promisc_mode_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+sw_error_t
+fal_port_promisc_mode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_promisc_mode_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_interface_eee_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
+	fal_port_eee_cfg_t *port_eee_cfg)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_interface_eee_cfg_set(dev_id, port_id, port_eee_cfg);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_interface_eee_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
+	fal_port_eee_cfg_t *port_eee_cfg)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_interface_eee_cfg_get(dev_id, port_id, port_eee_cfg);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_switch_port_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_loopback_config_t *loopback_cfg)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_switch_port_loopback_set(dev_id, port_id, loopback_cfg);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_switch_port_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
+	fal_loopback_config_t *loopback_cfg)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_switch_port_loopback_get(dev_id, port_id, loopback_cfg);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/*insert flag for outter fal, don't remove it*/
+/**
+ * @}
+ */
+ #ifndef IN_PORTCONTROL_MINI
+EXPORT_SYMBOL(fal_port_mtu_set);
+EXPORT_SYMBOL(fal_port_mtu_get);
+EXPORT_SYMBOL(fal_port_mru_set);
+EXPORT_SYMBOL(fal_port_mru_get);
+#endif
+EXPORT_SYMBOL(fal_port_duplex_set);
+EXPORT_SYMBOL(fal_port_duplex_get);
+EXPORT_SYMBOL(fal_port_speed_set);
+EXPORT_SYMBOL(fal_port_speed_get);
+EXPORT_SYMBOL(fal_port_autoneg_status_get);
+EXPORT_SYMBOL(fal_port_autoneg_enable);
+EXPORT_SYMBOL(fal_port_autoneg_restart);
+EXPORT_SYMBOL(fal_port_autoneg_adv_set);
+EXPORT_SYMBOL(fal_port_autoneg_adv_get);
+EXPORT_SYMBOL(fal_port_flowctrl_set);
+#ifndef IN_PORTCONTROL_MINI
+EXPORT_SYMBOL(fal_port_flowctrl_get);
+EXPORT_SYMBOL(fal_port_powersave_set);
+EXPORT_SYMBOL(fal_port_powersave_get);
+EXPORT_SYMBOL(fal_port_hibernate_set);
+EXPORT_SYMBOL(fal_port_hibernate_get);
+EXPORT_SYMBOL(fal_port_cdt);
+EXPORT_SYMBOL(fal_port_txmac_status_get);
+#endif
+EXPORT_SYMBOL(fal_port_txmac_status_set);
+EXPORT_SYMBOL(fal_port_rxmac_status_set);
+#ifndef IN_PORTCONTROL_MINI
+EXPORT_SYMBOL(fal_port_rxmac_status_get);
+#endif
+EXPORT_SYMBOL(fal_port_txfc_status_set);
+EXPORT_SYMBOL(fal_port_txfc_status_get);
+EXPORT_SYMBOL(fal_port_rxfc_status_set);
+EXPORT_SYMBOL(fal_port_rxfc_status_get);
+#ifndef IN_PORTCONTROL_MINI
+EXPORT_SYMBOL(fal_port_bp_status_set);
+EXPORT_SYMBOL(fal_port_bp_status_get);
+#endif
+EXPORT_SYMBOL(fal_port_link_status_get);
+#ifndef IN_PORTCONTROL_MINI
+EXPORT_SYMBOL(fal_ports_link_status_get);
+EXPORT_SYMBOL(fal_port_mac_loopback_set);
+EXPORT_SYMBOL(fal_port_mac_loopback_get);
+EXPORT_SYMBOL(fal_port_8023az_set);
+EXPORT_SYMBOL(fal_port_8023az_get);
+EXPORT_SYMBOL(fal_port_mdix_set);
+EXPORT_SYMBOL(fal_port_mdix_get);
+EXPORT_SYMBOL(fal_port_mdix_status_get);
+EXPORT_SYMBOL(fal_port_combo_prefer_medium_set);
+EXPORT_SYMBOL(fal_port_combo_prefer_medium_get);
+EXPORT_SYMBOL(fal_port_combo_medium_status_get);
+EXPORT_SYMBOL(fal_port_combo_fiber_mode_set);
+EXPORT_SYMBOL(fal_port_combo_fiber_mode_get);
+EXPORT_SYMBOL(fal_port_local_loopback_set);
+EXPORT_SYMBOL(fal_port_local_loopback_get);
+EXPORT_SYMBOL(fal_port_remote_loopback_set);
+EXPORT_SYMBOL(fal_port_remote_loopback_get);
+EXPORT_SYMBOL(fal_port_reset);
+#endif
+EXPORT_SYMBOL(fal_port_power_off);
+EXPORT_SYMBOL(fal_port_power_on);
+#ifndef IN_PORTCONTROL_MINI
+EXPORT_SYMBOL(fal_port_magic_frame_mac_set );
+EXPORT_SYMBOL(fal_port_magic_frame_mac_get );
+EXPORT_SYMBOL(fal_port_phy_id_get );
+EXPORT_SYMBOL(fal_port_wol_status_set );
+EXPORT_SYMBOL(fal_port_wol_status_get );
+EXPORT_SYMBOL(fal_port_interface_mode_set);
+EXPORT_SYMBOL(fal_port_interface_mode_apply);
+
+EXPORT_SYMBOL(fal_port_interface_mode_get );
+EXPORT_SYMBOL(fal_port_interface_mode_status_get );
+EXPORT_SYMBOL(fal_port_source_filter_enable);
+EXPORT_SYMBOL(fal_port_source_filter_status_get);
+EXPORT_SYMBOL(fal_port_source_filter_config_get);
+EXPORT_SYMBOL(fal_port_source_filter_config_set);
+#endif
+EXPORT_SYMBOL(fal_port_max_frame_size_set);
+EXPORT_SYMBOL(fal_port_max_frame_size_get);
+#ifndef IN_PORTCONTROL_MINI
+EXPORT_SYMBOL(fal_port_interface_3az_status_set);
+EXPORT_SYMBOL(fal_port_interface_3az_status_get);
+#endif
+EXPORT_SYMBOL(fal_port_flowctrl_forcemode_set);
+#ifndef IN_PORTCONTROL_MINI
+EXPORT_SYMBOL(fal_port_flowctrl_forcemode_get);
+EXPORT_SYMBOL(fal_port_promisc_mode_set);
+EXPORT_SYMBOL(fal_port_promisc_mode_get);
+#endif
+EXPORT_SYMBOL(fal_port_interface_eee_cfg_set);
+EXPORT_SYMBOL(fal_port_interface_eee_cfg_get);
+EXPORT_SYMBOL(fal_switch_port_loopback_set);
+EXPORT_SYMBOL(fal_switch_port_loopback_get);
+
diff --git a/qca-ssdk/src/fal/fal_portvlan.c b/qca-ssdk/src/fal/fal_portvlan.c
new file mode 100755
index 0000000..0b82acc
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_portvlan.c
@@ -0,0 +1,2550 @@
+/*
+ * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_port_vlan FAL_PORT_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "fal_portvlan.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+static sw_error_t
+_fal_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_1qmode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_1qmode_set(dev_id, port_id, port_1qmode);
+    return rv;
+}
+
+
+
+
+
+static sw_error_t
+_fal_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_egvlanmode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+    return rv;
+}
+
+
+
+static sw_error_t
+_fal_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_portvlan_member_add)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_portvlan_member_add(dev_id, port_id, mem_port_id);
+        return rv;
+    }
+
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->portvlan_member_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->portvlan_member_add(dev_id, port_id, mem_port_id);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_portvlan_member_del)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_portvlan_member_del(dev_id, port_id, mem_port_id);
+        return rv;
+    }
+
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->portvlan_member_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->portvlan_member_del(dev_id, port_id, mem_port_id);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_portvlan_member_update)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_portvlan_member_update(dev_id, port_id, mem_port_map);
+        return rv;
+    }
+
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->portvlan_member_update)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->portvlan_member_update(dev_id, port_id, mem_port_map);
+    return rv;
+}
+
+
+
+static sw_error_t
+_fal_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_default_vid_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_default_vid_set(dev_id, port_id, vid);
+    return rv;
+}
+
+
+
+static sw_error_t
+_fal_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_force_default_vid_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_force_default_vid_set(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_force_portvlan_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_force_portvlan_set(dev_id, port_id, enable);
+    return rv;
+}
+
+
+
+
+static sw_error_t
+_fal_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_nestvlan_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_nestvlan_set(dev_id, port_id, enable);
+    return rv;
+}
+
+
+
+
+
+static sw_error_t
+_fal_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nestvlan_tpid_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nestvlan_tpid_set(dev_id, tpid);
+    return rv;
+}
+
+
+
+static sw_error_t
+_fal_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_invlan_mode_t mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_invlan_mode_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_invlan_mode_set(dev_id, port_id, mode);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_invlan_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_invlan_mode_set(dev_id, port_id, mode);
+    return rv;
+}
+static sw_error_t
+_fal_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+                  a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_tls_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_tls_set(dev_id, port_id, enable);
+    return rv;
+}
+
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_fal_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_invlan_mode_t * mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_invlan_mode_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_invlan_mode_get(dev_id, port_id, mode);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_invlan_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_invlan_mode_get(dev_id, port_id, mode);
+    return rv;
+}
+static sw_error_t
+_fal_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->nestvlan_tpid_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->nestvlan_tpid_get(dev_id, tpid);
+    return rv;
+}
+static sw_error_t
+_fal_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_nestvlan_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_nestvlan_get(dev_id, port_id, enable);
+    return rv;
+}
+static sw_error_t
+_fal_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_force_portvlan_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_force_portvlan_get(dev_id, port_id, enable);
+    return rv;
+}
+static sw_error_t
+_fal_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_force_default_vid_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_force_default_vid_get(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * vid)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_default_vid_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_default_vid_get(dev_id, port_id, vid);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_1qmode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_1qmode_get(dev_id, port_id, pport_1qmode);
+    return rv;
+}
+static sw_error_t
+_fal_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_egvlanmode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+    return rv;
+}
+
+static sw_error_t
+_fal_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_portvlan_member_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_portvlan_member_get(dev_id, port_id, mem_port_map);
+        return rv;
+    }
+
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->portvlan_member_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->portvlan_member_get(dev_id, port_id, mem_port_map);
+    return rv;
+}
+
+
+
+static sw_error_t
+_fal_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+                  a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_tls_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_tls_get(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_pri_propagation_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_pri_propagation_set(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_pri_propagation_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_pri_propagation_get(dev_id, port_id, enable);
+    return rv;
+}
+#endif
+static sw_error_t
+_fal_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t vid)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_default_svid_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_default_svid_set(dev_id, port_id, vid);
+    return rv;
+}
+
+
+
+static sw_error_t
+_fal_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t vid)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_default_cvid_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_default_cvid_set(dev_id, port_id, vid);
+    return rv;
+}
+
+
+
+static sw_error_t
+_fal_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_vlan_propagation_mode_t mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_vlan_propagation_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_vlan_propagation_set(dev_id, port_id, mode);
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_fal_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * vid)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_default_cvid_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_default_cvid_get(dev_id, port_id, vid);
+    return rv;
+}
+static sw_error_t
+_fal_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * vid)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_default_svid_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_default_svid_get(dev_id, port_id, vid);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_vlan_propagation_mode_t * mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_vlan_propagation_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_vlan_propagation_get(dev_id, port_id, mode);
+    return rv;
+}
+#endif
+
+static sw_error_t
+_fal_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_vlan_trans_add)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_vlan_trans_add(dev_id, port_id, entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_vlan_trans_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_vlan_trans_add(dev_id, port_id, entry);
+    return rv;
+}
+
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_fal_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_vlan_trans_del)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_vlan_trans_del(dev_id, port_id, entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_vlan_trans_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_vlan_trans_del(dev_id, port_id, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_vlan_trans_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_vlan_trans_get(dev_id, port_id, entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_vlan_trans_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_vlan_trans_get(dev_id, port_id, entry);
+    return rv;
+}
+#endif
+
+static sw_error_t
+_fal_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_qinq_mode_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_qinq_mode_set(dev_id, mode);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qinq_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qinq_mode_set(dev_id, mode);
+    return rv;
+}
+
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_fal_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_qinq_mode_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_qinq_mode_get(dev_id, mode);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qinq_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qinq_mode_get(dev_id, mode);
+    return rv;
+}
+#endif
+
+static sw_error_t
+_fal_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_qinq_role_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_qinq_role_set(dev_id, port_id, role);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_qinq_role_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_qinq_role_set(dev_id, port_id, role);
+    return rv;
+}
+
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_fal_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_qinq_role_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_qinq_role_get(dev_id, port_id, role);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_qinq_role_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_qinq_role_get(dev_id, port_id, role);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * iterator, fal_vlan_trans_entry_t *entry)
+{
+    sw_error_t rv;
+    adpt_api_t *p_adpt_api;
+    hsl_api_t *p_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_port_vlan_trans_iterate)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_port_vlan_trans_iterate(dev_id, port_id, iterator, entry);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_vlan_trans_iterate)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_vlan_trans_iterate(dev_id, port_id, iterator, entry);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_mac_vlan_xlt_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_mac_vlan_xlt_set(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_mac_vlan_xlt_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_mac_vlan_xlt_get(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_netisolate_set(a_uint32_t dev_id, a_uint32_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->netisolate_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->netisolate_set(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_netisolate_get(a_uint32_t dev_id, a_uint32_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->netisolate_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->netisolate_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_uint32_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->eg_trans_filter_bypass_en_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->eg_trans_filter_bypass_en_set(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_uint32_t* enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->eg_trans_filter_bypass_en_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->eg_trans_filter_bypass_en_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_vrf_id_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t vrf_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_vrf_id_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_vrf_id_set(dev_id, port_id, vrf_id);
+    return rv;
+}
+
+static sw_error_t
+_fal_port_vrf_id_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * vrf_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->port_vrf_id_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->port_vrf_id_get(dev_id, port_id, vrf_id);
+    return rv;
+}
+#endif
+/**
+ * @brief Set 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                    fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_1qmode_set(dev_id, port_id, port_1qmode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                    fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_1qmode_get(dev_id, port_id, pport_1qmode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Add member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                        a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_portvlan_member_add(dev_id, port_id, mem_port_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                        a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_portvlan_member_del(dev_id, port_id, mem_port_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Update member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_map port members
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_portvlan_member_update(dev_id, port_id, mem_port_map);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mem_port_map port members
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_portvlan_member_get(dev_id, port_id, mem_port_map);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set default vlan id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid default vlan id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_default_vid_set(dev_id, port_id, vid);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get default vlan id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid default vlan id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t * vid)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_default_vid_get(dev_id, port_id, vid);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_force_default_vid_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_force_default_vid_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_force_portvlan_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_force_portvlan_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set nest vlan feature status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_nestvlan_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get nest vlan feature status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_nestvlan_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nestvlan_tpid_set(dev_id, tpid);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_nestvlan_tpid_get(dev_id, tpid);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_invlan_mode_t mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_invlan_mode_set(dev_id, port_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_invlan_mode_t * mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_invlan_mode_get(dev_id, port_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+                 a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_tls_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+
+
+/**
+ * @brief Get tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+                 a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_tls_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_pri_propagation_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_pri_propagation_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid s-vid
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t vid)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_default_svid_set(dev_id, port_id, vid);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid s-vid
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * vid)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_default_svid_get(dev_id, port_id, vid);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid c-vid
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t vid)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_default_cvid_set(dev_id, port_id, vid);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid c-vid
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * vid)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_default_cvid_get(dev_id, port_id, vid);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_vlan_propagation_mode_t mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_vlan_propagation_set(dev_id, port_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+
+
+/**
+ * @brief Get vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_vlan_propagation_mode_t * mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_vlan_propagation_get(dev_id, port_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Add a vlan translation entry to a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_vlan_trans_add(dev_id, port_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Delete a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_vlan_trans_del(dev_id, port_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_vlan_trans_get(dev_id, port_id, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode qinq work mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qinq_mode_set(dev_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode qinq work mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qinq_mode_get(dev_id, mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_qinq_role_set(dev_id, port_id, role);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_qinq_role_get(dev_id, port_id, role);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Iterate all vlan translation entries from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] iterator translation entry index if it's zero means get the first entry
+ * @param[out] iterator next valid translation entry index
+ * @param[out] entry vlan translation entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * iterator, fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_vlan_trans_iterate(dev_id, port_id, iterator, entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set MAC_VLAN_XLT status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_mac_vlan_xlt_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get MAC_VLAN_XLT status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_mac_vlan_xlt_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set net isolate function.
+ * @param[in] dev_id device id
+ * @param[in] enable tag protocol identification
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_netisolate_set(a_uint32_t dev_id, a_uint32_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_netisolate_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get net isolate status.
+ * @param[in] dev_id device id
+ * @param[out] enable tag protocol identification
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_netisolate_get(a_uint32_t dev_id, a_uint32_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_netisolate_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+/**
+ * @brief Set egress translation filter bypass enable
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_eg_trans_filter_bypass_en_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress translation filter bypass enable
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_eg_trans_filter_bypass_en_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set VRF id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vrf_id VRF id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_vrf_id_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t vrf_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_vrf_id_set(dev_id, port_id, vrf_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get VRF id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vrf_id VRF id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_vrf_id_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * vrf_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_port_vrf_id_get(dev_id, port_id, vrf_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @}
+ */
+sw_error_t
+_fal_global_qinq_mode_set(a_uint32_t dev_id, fal_global_qinq_mode_t *mode)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_global_qinq_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_global_qinq_mode_set(dev_id, mode);
+    return rv;
+}
+
+sw_error_t
+_fal_global_qinq_mode_get(a_uint32_t dev_id, fal_global_qinq_mode_t *mode)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_global_qinq_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_global_qinq_mode_get(dev_id, mode);
+    return rv;
+}
+
+sw_error_t
+_fal_port_qinq_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_qinq_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_qinq_mode_set(dev_id, port_id, mode);
+    return rv;
+}
+
+sw_error_t
+_fal_port_qinq_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_qinq_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_qinq_mode_get(dev_id, port_id, mode);
+    return rv;
+}
+
+sw_error_t
+_fal_ingress_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_tpid_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_tpid_set(dev_id, tpid);
+    return rv;
+}
+
+sw_error_t
+_fal_ingress_tpid_get(a_uint32_t dev_id, fal_tpid_t * tpid)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_tpid_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_tpid_get(dev_id, tpid);
+    return rv;
+}
+
+sw_error_t
+_fal_egress_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_egress_tpid_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_egress_tpid_set(dev_id, tpid);
+    return rv;
+}
+
+sw_error_t
+_fal_egress_tpid_get(a_uint32_t dev_id, fal_tpid_t * tpid)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_egress_tpid_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_egress_tpid_get(dev_id, tpid);
+    return rv;
+}
+
+sw_error_t
+_fal_port_ingress_vlan_filter_set(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t *filter)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_ingress_vlan_filter_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_ingress_vlan_filter_set(dev_id, port_id, filter);
+    return rv;
+}
+
+sw_error_t
+_fal_port_ingress_vlan_filter_get(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t * filter)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_ingress_vlan_filter_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_ingress_vlan_filter_get(dev_id, port_id, filter);
+    return rv;
+}
+
+sw_error_t
+_fal_port_default_vlantag_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_default_vlantag_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_default_vlantag_set(dev_id, port_id, direction, default_vid_en, default_tag);
+    return rv;
+}
+
+sw_error_t
+_fal_port_default_vlantag_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_default_vlantag_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_default_vlantag_get(dev_id, port_id, direction, default_vid_en, default_tag);
+    return rv;
+}
+
+sw_error_t
+_fal_port_tag_propagation_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlantag_propagation_t *prop)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_tag_propagation_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_tag_propagation_set(dev_id, port_id, direction, prop);
+    return rv;
+}
+
+sw_error_t
+_fal_port_tag_propagation_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlantag_propagation_t *prop)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_tag_propagation_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_tag_propagation_get(dev_id, port_id, direction, prop);
+    return rv;
+}
+
+sw_error_t
+_fal_port_vlantag_egmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_vlantag_egress_mode_t *port_egvlanmode)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vlantag_egmode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vlantag_egmode_set(dev_id, port_id, port_egvlanmode);
+    return rv;
+}
+
+sw_error_t
+_fal_port_vlantag_egmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_vlantag_egress_mode_t *port_egvlanmode)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vlantag_egmode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vlantag_egmode_get(dev_id, port_id, port_egvlanmode);
+    return rv;
+}
+
+sw_error_t
+_fal_port_vlan_xlt_miss_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vlan_xlt_miss_cmd_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vlan_xlt_miss_cmd_set(dev_id, port_id, cmd);
+    return rv;
+}
+
+sw_error_t
+_fal_port_vlan_xlt_miss_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_fwd_cmd_t *cmd)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vlan_xlt_miss_cmd_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vlan_xlt_miss_cmd_get(dev_id, port_id, cmd);
+    return rv;
+}
+
+sw_error_t
+_fal_port_vsi_egmode_set(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t egmode)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vsi_egmode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vsi_egmode_set(dev_id, vsi, port_id, egmode);
+    return rv;
+}
+sw_error_t
+_fal_port_vsi_egmode_get(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t * egmode)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vsi_egmode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vsi_egmode_get(dev_id, vsi, port_id, egmode);
+    return rv;
+}
+sw_error_t
+_fal_port_vlantag_vsi_egmode_enable(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vlantag_vsi_egmode_enable_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vlantag_vsi_egmode_enable_set(dev_id, port_id, enable);
+    return rv;
+}
+sw_error_t
+_fal_port_vlantag_vsi_egmode_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vlantag_vsi_egmode_enable_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vlantag_vsi_egmode_enable_get(dev_id, port_id, enable);
+    return rv;
+}
+sw_error_t
+_fal_port_vlan_trans_adv_add(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vlan_trans_adv_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vlan_trans_adv_add(dev_id, port_id, direction, rule, action);
+    return rv;
+}
+sw_error_t
+_fal_port_vlan_trans_adv_del(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vlan_trans_adv_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vlan_trans_adv_del(dev_id, port_id, direction, rule, action);
+    return rv;
+}
+sw_error_t
+_fal_port_vlan_trans_adv_getfirst(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vlan_trans_adv_getfirst)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vlan_trans_adv_getfirst(dev_id, port_id, direction, rule, action);
+    return rv;
+}
+sw_error_t
+_fal_port_vlan_trans_adv_getnext(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vlan_trans_adv_getnext)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vlan_trans_adv_getnext(dev_id, port_id, direction, rule, action);
+    return rv;
+}
+sw_error_t
+_fal_port_vlan_counter_get(a_uint32_t dev_id, a_uint32_t cnt_index, fal_port_vlan_counter_t * counter)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vlan_counter_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vlan_counter_get(dev_id, cnt_index, counter);
+    return rv;
+}
+sw_error_t
+_fal_port_vlan_counter_cleanup(a_uint32_t dev_id, a_uint32_t cnt_index)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vlan_counter_cleanup)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vlan_counter_cleanup(dev_id, cnt_index);
+    return rv;
+}
+
+sw_error_t
+fal_global_qinq_mode_set(a_uint32_t dev_id, fal_global_qinq_mode_t *mode)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_global_qinq_mode_set(dev_id, mode);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_global_qinq_mode_get(a_uint32_t dev_id, fal_global_qinq_mode_t *mode)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_global_qinq_mode_get(dev_id, mode);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_qinq_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_qinq_mode_set(dev_id, port_id, mode);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_qinq_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_qinq_mode_get(dev_id, port_id, mode);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ingress_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_ingress_tpid_set(dev_id, tpid);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_ingress_tpid_get(a_uint32_t dev_id, fal_tpid_t * tpid)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_ingress_tpid_get(dev_id, tpid);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_egress_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_egress_tpid_set(dev_id, tpid);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_egress_tpid_get(a_uint32_t dev_id, fal_tpid_t * tpid)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_egress_tpid_get(dev_id, tpid);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_ingress_vlan_filter_set(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t *filter)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_ingress_vlan_filter_set(dev_id, port_id, filter);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_ingress_vlan_filter_get(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t * filter)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_ingress_vlan_filter_get(dev_id, port_id, filter);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_default_vlantag_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_default_vlantag_set(dev_id, port_id, direction, default_vid_en, default_tag);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_default_vlantag_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_default_vlantag_get(dev_id, port_id, direction, default_vid_en, default_tag);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_tag_propagation_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlantag_propagation_t *prop)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_tag_propagation_set(dev_id, port_id, direction, prop);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_tag_propagation_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlantag_propagation_t *prop)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_tag_propagation_get(dev_id, port_id, direction, prop);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_vlantag_egmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_vlantag_egress_mode_t *port_egvlanmode)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_vlantag_egmode_set(dev_id, port_id, port_egvlanmode);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_vlantag_egmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_vlantag_egress_mode_t *port_egvlanmode)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_vlantag_egmode_get(dev_id, port_id, port_egvlanmode);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_vlan_xlt_miss_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_vlan_xlt_miss_cmd_set(dev_id, port_id, cmd);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_vlan_xlt_miss_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_fwd_cmd_t *cmd)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_vlan_xlt_miss_cmd_get(dev_id, port_id, cmd);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_port_vsi_egmode_set(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t egmode)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_vsi_egmode_set(dev_id, vsi, port_id, egmode);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_vsi_egmode_get(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t * egmode)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_vsi_egmode_get(dev_id, vsi, port_id, egmode);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_vlantag_vsi_egmode_enable(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_vlantag_vsi_egmode_enable(dev_id, port_id, enable);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_vlantag_vsi_egmode_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_vlantag_vsi_egmode_status_get(dev_id, port_id, enable);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_vlan_trans_adv_add(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_vlan_trans_adv_add(dev_id, port_id, direction, rule, action);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_vlan_trans_adv_del(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_vlan_trans_adv_del(dev_id, port_id, direction, rule, action);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_vlan_trans_adv_getfirst(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_vlan_trans_adv_getfirst(dev_id, port_id, direction, rule, action);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_vlan_trans_adv_getnext(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
+                                 fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_vlan_trans_adv_getnext(dev_id, port_id, direction, rule, action);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_vlan_counter_get(a_uint32_t dev_id, a_uint32_t cnt_index, fal_port_vlan_counter_t * counter)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_vlan_counter_get(dev_id, cnt_index, counter);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_vlan_counter_cleanup(a_uint32_t dev_id, a_uint32_t cnt_index)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_PORTVLAN_API_LOCK;
+    rv = _fal_port_vlan_counter_cleanup(dev_id, cnt_index);
+    FAL_PORTVLAN_API_UNLOCK;
+    return rv;
+}
+
+EXPORT_SYMBOL(fal_port_invlan_mode_set);
+EXPORT_SYMBOL(fal_global_qinq_mode_set);
+EXPORT_SYMBOL(fal_global_qinq_mode_get);
+EXPORT_SYMBOL(fal_port_qinq_mode_set);
+EXPORT_SYMBOL(fal_port_qinq_mode_get);
+EXPORT_SYMBOL(fal_ingress_tpid_set);
+EXPORT_SYMBOL(fal_ingress_tpid_get);
+EXPORT_SYMBOL(fal_egress_tpid_set);
+EXPORT_SYMBOL(fal_egress_tpid_get);
+EXPORT_SYMBOL(fal_port_ingress_vlan_filter_set);
+EXPORT_SYMBOL(fal_port_ingress_vlan_filter_get);
+EXPORT_SYMBOL(fal_port_default_vlantag_set);
+EXPORT_SYMBOL(fal_port_default_vlantag_get);
+EXPORT_SYMBOL(fal_port_tag_propagation_set);
+EXPORT_SYMBOL(fal_port_tag_propagation_get);
+EXPORT_SYMBOL(fal_port_vlantag_egmode_set);
+EXPORT_SYMBOL(fal_port_vlantag_egmode_get);
+EXPORT_SYMBOL(fal_port_vlan_xlt_miss_cmd_set);
+EXPORT_SYMBOL(fal_port_vlan_xlt_miss_cmd_get);
+EXPORT_SYMBOL(fal_port_vsi_egmode_set);
+EXPORT_SYMBOL(fal_port_vsi_egmode_get);
+EXPORT_SYMBOL(fal_port_vlantag_vsi_egmode_enable);
+EXPORT_SYMBOL(fal_port_vlantag_vsi_egmode_status_get);
+EXPORT_SYMBOL(fal_port_vlan_trans_adv_add);
+EXPORT_SYMBOL(fal_port_vlan_trans_adv_del);
+EXPORT_SYMBOL(fal_port_vlan_trans_adv_getfirst);
+EXPORT_SYMBOL(fal_port_vlan_trans_adv_getnext);
+EXPORT_SYMBOL(fal_port_vlan_counter_get);
+EXPORT_SYMBOL(fal_port_vlan_counter_cleanup);
+EXPORT_SYMBOL(fal_portvlan_member_add);
+EXPORT_SYMBOL(fal_portvlan_member_del);
+EXPORT_SYMBOL(fal_portvlan_member_update);
+EXPORT_SYMBOL(fal_qinq_mode_set);
+EXPORT_SYMBOL(fal_port_qinq_role_set);
+EXPORT_SYMBOL(fal_port_vlan_trans_add);
+#ifndef IN_PORTVLAN_MINI
+EXPORT_SYMBOL(fal_qinq_mode_get);
+EXPORT_SYMBOL(fal_port_qinq_role_get);
+EXPORT_SYMBOL(fal_port_vlan_trans_iterate);
+EXPORT_SYMBOL(fal_port_vlan_trans_del);
+EXPORT_SYMBOL(fal_port_vlan_trans_get);
+EXPORT_SYMBOL(fal_portvlan_member_get);
+EXPORT_SYMBOL(fal_port_invlan_mode_get);
+#endif
diff --git a/qca-ssdk/src/fal/fal_pppoe.c b/qca-ssdk/src/fal/fal_pppoe.c
new file mode 100755
index 0000000..1552b8c
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_pppoe.c
@@ -0,0 +1,609 @@
+/*
+ * Copyright (c) 2012, 2015-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_pppoe FAL_PPPOE
+ * @{
+ */
+#include "sw.h"
+#include "fal_pppoe.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+
+static sw_error_t
+_fal_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->pppoe_cmd_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->pppoe_cmd_set(dev_id, cmd);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->pppoe_cmd_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->pppoe_cmd_get(dev_id, cmd);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->pppoe_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->pppoe_status_set(dev_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->pppoe_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->pppoe_status_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->pppoe_session_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->pppoe_session_add(dev_id, session_id, strip_hdr);
+    return rv;
+}
+
+static sw_error_t
+_fal_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->pppoe_session_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->pppoe_session_del(dev_id, session_id);
+    return rv;
+}
+
+static sw_error_t
+_fal_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->pppoe_session_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->pppoe_session_get(dev_id, session_id, strip_hdr);
+    return rv;
+}
+
+static sw_error_t
+_fal_pppoe_session_table_add(a_uint32_t dev_id,
+                             fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_pppoe_session_table_add)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_pppoe_session_table_add(dev_id, session_tbl);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->pppoe_session_table_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->pppoe_session_table_add(dev_id, session_tbl);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_pppoe_session_table_del(a_uint32_t dev_id,
+                             fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_pppoe_session_table_del)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_pppoe_session_table_del(dev_id, session_tbl);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->pppoe_session_table_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->pppoe_session_table_del(dev_id, session_tbl);
+    return rv;
+}
+
+static sw_error_t
+_fal_pppoe_session_table_get(a_uint32_t dev_id,
+                             fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_pppoe_session_table_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_pppoe_session_table_get(dev_id, session_tbl);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->pppoe_session_table_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->pppoe_session_table_get(dev_id, session_tbl);
+    return rv;
+}
+
+static sw_error_t
+_fal_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+                          a_uint32_t id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->pppoe_session_id_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->pppoe_session_id_set(dev_id, index, id);
+    return rv;
+}
+
+static sw_error_t
+_fal_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+                          a_uint32_t * id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->pppoe_session_id_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->pppoe_session_id_get(dev_id, index, id);
+    return rv;
+}
+
+static sw_error_t
+_fal_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rtd_pppoe_en_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rtd_pppoe_en_set(dev_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rtd_pppoe_en_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rtd_pppoe_en_get(dev_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_pppoe_l3intf_status_get(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t *enable)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_pppoe_en_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_pppoe_en_get(dev_id, l3_if, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_pppoe_l3intf_enable(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t enable)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_pppoe_en_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_pppoe_en_set(dev_id, l3_if, enable);
+    return rv;
+}
+/*insert flag for inner fal, don't remove it*/
+
+/**
+ * @brief Set pppoe packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling pppoe packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_pppoe_cmd_set(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get pppoe packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_pppoe_cmd_get(dev_id, cmd);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set pppoe packets hardware acknowledgement status on particular device.
+ * @details     comments:
+ *   Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_pppoe_status_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get pppoe packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_pppoe_status_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a pppoe session entry to a particular device.
+ * @param[in] dev_id device id
+ * @param[in] session_id pppoe session id
+ * @param[in] strip_hdr strip or not strip pppoe header
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_pppoe_session_add(dev_id, session_id, strip_hdr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a pppoe session entry from a particular device.
+ * @param[in] dev_id device id
+ * @param[in] session_id pppoe session id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_pppoe_session_del(dev_id, session_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a pppoe session entry from a particular device.
+ * @param[in] dev_id device id
+ * @param[in] session_id pppoe session id
+ * @param[out] strip_hdr strip or not strip pppoe header
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_pppoe_session_get(dev_id, session_id, strip_hdr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a pppoe session entry to a particular device.
+ *        The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_table_add(a_uint32_t dev_id,
+                            fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_pppoe_session_table_add(dev_id, session_tbl);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a pppoe session entry from a particular device.
+ *        The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_table_del(a_uint32_t dev_id,
+                            fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_pppoe_session_table_del(dev_id, session_tbl);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a pppoe session entry from a particular device.
+ *        The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[out] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_table_get(a_uint32_t dev_id,
+                            fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_pppoe_session_table_get(dev_id, session_tbl);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set a pppoe session id entry to a particular device.
+ *        The entry only for pppoe/ppp header add.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+                         a_uint32_t id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_pppoe_session_id_set(dev_id, index, id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a pppoe session id entry to a particular device.
+ *        The entry only for pppoe/ppp header add.
+ * @param[in] dev_id device id
+ * @param[out] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+                         a_uint32_t * id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_pppoe_session_id_get(dev_id, index, id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set RM_RTD_PPPOE_EN status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rtd_pppoe_en_set(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get RM_RTD_PPPOE_EN status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rtd_pppoe_en_get(dev_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set a l3 interface pppoe status
+ * @param[in] dev_id device id
+ * @param[in] l3 interface name
+ * @param[in] pppoe status enable or disable
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_l3intf_status_get(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t *enable)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_pppoe_l3intf_status_get(dev_id, l3_if, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a l3 interface pppoe status
+ * @param[in] dev_id device id
+ * @param[in] l3 interface name
+ * @param[out] pppoe status enable or disable
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_l3intf_enable(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t enable)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_pppoe_l3intf_enable(dev_id, l3_if, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+/*insert flag for outter fal, don't remove it*/
+
+EXPORT_SYMBOL(fal_pppoe_session_table_add);
+EXPORT_SYMBOL(fal_pppoe_session_table_del);
+EXPORT_SYMBOL(fal_pppoe_session_table_get);
+EXPORT_SYMBOL(fal_pppoe_l3intf_status_get);
+EXPORT_SYMBOL(fal_pppoe_l3intf_enable);
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/fal/fal_ptp.c b/qca-ssdk/src/fal/fal_ptp.c
new file mode 100755
index 0000000..c00df9a
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_ptp.c
@@ -0,0 +1,1208 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_ptp FAL_PTP
+ * @{
+ */
+#include "sw.h"
+#include "fal_ptp.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+sw_error_t
+_fal_ptp_security_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_security_t *sec)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_security_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_security_set(dev_id, port_id, sec);
+	return rv;
+}
+sw_error_t
+_fal_ptp_link_delay_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_link_delay_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_link_delay_set(dev_id, port_id, time);
+	return rv;
+}
+sw_error_t
+_fal_ptp_rx_crc_recalc_status_get(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t *status)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_rx_crc_recalc_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_rx_crc_recalc_status_get(dev_id, port_id, status);
+	return rv;
+}
+sw_error_t
+_fal_ptp_tod_uart_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_tod_uart_t *tod_uart)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_tod_uart_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_tod_uart_set(dev_id, port_id, tod_uart);
+	return rv;
+}
+sw_error_t
+_fal_ptp_enhanced_timestamp_engine_get(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_direction_t direction,
+		fal_ptp_enhanced_ts_engine_t *ts_engine)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_enhanced_timestamp_engine_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_enhanced_timestamp_engine_get(dev_id, port_id, direction, ts_engine);
+	return rv;
+}
+sw_error_t
+_fal_ptp_pps_signal_control_set(a_uint32_t dev_id,
+		a_uint32_t port_id,
+		fal_ptp_pps_signal_control_t *sig_control)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_pps_signal_control_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_pps_signal_control_set(dev_id, port_id, sig_control);
+	return rv;
+}
+sw_error_t
+_fal_ptp_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_direction_t direction,
+		fal_ptp_pkt_info_t *pkt_info,
+		fal_ptp_time_t *time)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_timestamp_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_timestamp_get(dev_id, port_id, direction, pkt_info, time);
+	return rv;
+}
+sw_error_t
+_fal_ptp_asym_correction_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_asym_correction_t* asym_cf)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_asym_correction_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_asym_correction_get(dev_id, port_id, asym_cf);
+	return rv;
+}
+sw_error_t
+_fal_ptp_rtc_time_snapshot_status_get(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t *status)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_rtc_time_snapshot_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_rtc_time_snapshot_status_get(dev_id, port_id, status);
+	return rv;
+}
+sw_error_t
+_fal_ptp_capture_set(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t capture_id, fal_ptp_capture_t *capture)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_capture_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_capture_set(dev_id, port_id, capture_id, capture);
+	return rv;
+}
+sw_error_t
+_fal_ptp_rtc_adjfreq_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_rtc_adjfreq_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_rtc_adjfreq_set(dev_id, port_id, time);
+	return rv;
+}
+sw_error_t
+_fal_ptp_asym_correction_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_asym_correction_t *asym_cf)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_asym_correction_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_asym_correction_set(dev_id, port_id, asym_cf);
+	return rv;
+}
+sw_error_t
+_fal_ptp_pkt_timestamp_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_pkt_timestamp_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_pkt_timestamp_set(dev_id, port_id, time);
+	return rv;
+}
+sw_error_t
+_fal_ptp_rtc_time_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_rtc_time_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_rtc_time_get(dev_id, port_id, time);
+	return rv;
+}
+sw_error_t
+_fal_ptp_rtc_time_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_rtc_time_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_rtc_time_set(dev_id, port_id, time);
+	return rv;
+}
+sw_error_t
+_fal_ptp_pkt_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_pkt_timestamp_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_pkt_timestamp_get(dev_id, port_id, time);
+	return rv;
+}
+sw_error_t
+_fal_ptp_interrupt_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_interrupt_t *interrupt)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_interrupt_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_interrupt_set(dev_id, port_id, interrupt);
+	return rv;
+}
+sw_error_t
+_fal_ptp_trigger_set(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t trigger_id, fal_ptp_trigger_t *triger)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_trigger_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_trigger_set(dev_id, port_id, trigger_id, triger);
+	return rv;
+}
+sw_error_t
+_fal_ptp_pps_signal_control_get(a_uint32_t dev_id,
+		a_uint32_t port_id,
+		fal_ptp_pps_signal_control_t *sig_control)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_pps_signal_control_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_pps_signal_control_get(dev_id, port_id, sig_control);
+	return rv;
+}
+sw_error_t
+_fal_ptp_capture_get(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t capture_id, fal_ptp_capture_t *capture)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_capture_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_capture_get(dev_id, port_id, capture_id, capture);
+	return rv;
+}
+sw_error_t
+_fal_ptp_rx_crc_recalc_enable(a_uint32_t dev_id, a_uint32_t port_id,
+		a_bool_t status)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_rx_crc_recalc_enable)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_rx_crc_recalc_enable(dev_id, port_id, status);
+	return rv;
+}
+sw_error_t
+_fal_ptp_security_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_security_t *sec)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_security_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_security_get(dev_id, port_id, sec);
+	return rv;
+}
+sw_error_t
+_fal_ptp_increment_sync_from_clock_status_get(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t *status)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_increment_sync_from_clock_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_increment_sync_from_clock_status_get(dev_id, port_id, status);
+	return rv;
+}
+sw_error_t
+_fal_ptp_tod_uart_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_tod_uart_t *tod_uart)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_tod_uart_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_tod_uart_get(dev_id, port_id, tod_uart);
+	return rv;
+}
+sw_error_t
+_fal_ptp_enhanced_timestamp_engine_set(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_direction_t direction,
+		fal_ptp_enhanced_ts_engine_t *ts_engine)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_enhanced_timestamp_engine_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_enhanced_timestamp_engine_set(dev_id, port_id, direction, ts_engine);
+	return rv;
+}
+sw_error_t
+_fal_ptp_rtc_time_clear(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_rtc_time_clear)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_rtc_time_clear(dev_id, port_id);
+	return rv;
+}
+sw_error_t
+_fal_ptp_reference_clock_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_reference_clock_t ref_clock)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_reference_clock_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_reference_clock_set(dev_id, port_id, ref_clock);
+	return rv;
+}
+sw_error_t
+_fal_ptp_output_waveform_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_output_waveform_t *waveform)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_output_waveform_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_output_waveform_set(dev_id, port_id, waveform);
+	return rv;
+}
+sw_error_t
+_fal_ptp_rx_timestamp_mode_set(a_uint32_t dev_id,
+		a_uint32_t port_id,
+		fal_ptp_rx_timestamp_mode_t ts_mode)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_rx_timestamp_mode_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_rx_timestamp_mode_set(dev_id, port_id, ts_mode);
+	return rv;
+}
+sw_error_t
+_fal_ptp_grandmaster_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_grandmaster_mode_t *gm_mode)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_grandmaster_mode_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_grandmaster_mode_set(dev_id, port_id, gm_mode);
+	return rv;
+}
+sw_error_t
+_fal_ptp_config_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_config_t *config)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_config_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_config_set(dev_id, port_id, config);
+	return rv;
+}
+sw_error_t
+_fal_ptp_trigger_get(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t trigger_id, fal_ptp_trigger_t *triger)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_trigger_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_trigger_get(dev_id, port_id, trigger_id, triger);
+	return rv;
+}
+sw_error_t
+_fal_ptp_rtc_adjfreq_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_rtc_adjfreq_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_rtc_adjfreq_get(dev_id, port_id, time);
+	return rv;
+}
+sw_error_t
+_fal_ptp_grandmaster_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_grandmaster_mode_t *gm_mode)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_grandmaster_mode_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_grandmaster_mode_get(dev_id, port_id, gm_mode);
+	return rv;
+}
+sw_error_t
+_fal_ptp_rx_timestamp_mode_get(a_uint32_t dev_id,
+		a_uint32_t port_id,
+		fal_ptp_rx_timestamp_mode_t *ts_mode)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_rx_timestamp_mode_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_rx_timestamp_mode_get(dev_id, port_id, ts_mode);
+	return rv;
+}
+sw_error_t
+_fal_ptp_rtc_adjtime_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_rtc_adjtime_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_rtc_adjtime_set(dev_id, port_id, time);
+	return rv;
+}
+sw_error_t
+_fal_ptp_link_delay_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_link_delay_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_link_delay_get(dev_id, port_id, time);
+	return rv;
+}
+sw_error_t
+_fal_ptp_increment_sync_from_clock_enable(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t status)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_increment_sync_from_clock_enable)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_increment_sync_from_clock_enable(dev_id, port_id, status);
+	return rv;
+}
+sw_error_t
+_fal_ptp_config_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_config_t *config)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_config_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_config_get(dev_id, port_id, config);
+	return rv;
+}
+sw_error_t
+_fal_ptp_output_waveform_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_output_waveform_t *waveform)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_output_waveform_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_output_waveform_get(dev_id, port_id, waveform);
+	return rv;
+}
+sw_error_t
+_fal_ptp_interrupt_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_interrupt_t *interrupt)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_interrupt_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_interrupt_get(dev_id, port_id, interrupt);
+	return rv;
+}
+sw_error_t
+_fal_ptp_rtc_time_snapshot_enable(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t status)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_rtc_time_snapshot_enable)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_rtc_time_snapshot_enable(dev_id, port_id, status);
+	return rv;
+}
+sw_error_t
+_fal_ptp_reference_clock_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_reference_clock_t *ref_clock)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ptp_reference_clock_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ptp_reference_clock_get(dev_id, port_id, ref_clock);
+	return rv;
+}
+
+sw_error_t
+fal_ptp_security_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_security_t *sec)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_security_set(dev_id, port_id, sec);
+	FAL_API_UNLOCK;
+	return rv;
+}
+	sw_error_t
+fal_ptp_link_delay_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_link_delay_set(dev_id, port_id, time);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_rx_crc_recalc_status_get(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t *status)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_rx_crc_recalc_status_get(dev_id, port_id, status);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_tod_uart_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_tod_uart_t *tod_uart)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_tod_uart_set(dev_id, port_id, tod_uart);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_enhanced_timestamp_engine_get(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_direction_t direction,
+		fal_ptp_enhanced_ts_engine_t *ts_engine)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_enhanced_timestamp_engine_get(dev_id, port_id, direction, ts_engine);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_pps_signal_control_set(a_uint32_t dev_id,
+		a_uint32_t port_id,
+		fal_ptp_pps_signal_control_t *sig_control)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_pps_signal_control_set(dev_id, port_id, sig_control);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_direction_t direction,
+		fal_ptp_pkt_info_t *pkt_info,
+		fal_ptp_time_t *time)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_timestamp_get(dev_id, port_id, direction, pkt_info, time);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_asym_correction_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_asym_correction_t* asym_cf)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_asym_correction_get(dev_id, port_id, asym_cf);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_rtc_time_snapshot_status_get(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t *status)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_rtc_time_snapshot_status_get(dev_id, port_id, status);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_capture_set(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t capture_id, fal_ptp_capture_t *capture)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_capture_set(dev_id, port_id, capture_id, capture);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_rtc_adjfreq_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_rtc_adjfreq_set(dev_id, port_id, time);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_asym_correction_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_asym_correction_t *asym_cf)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_asym_correction_set(dev_id, port_id, asym_cf);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_pkt_timestamp_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_pkt_timestamp_set(dev_id, port_id, time);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_rtc_time_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_rtc_time_get(dev_id, port_id, time);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_rtc_time_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_rtc_time_set(dev_id, port_id, time);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_pkt_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_pkt_timestamp_get(dev_id, port_id, time);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_interrupt_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_interrupt_t *interrupt)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_interrupt_set(dev_id, port_id, interrupt);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_trigger_set(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t trigger_id, fal_ptp_trigger_t *triger)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_trigger_set(dev_id, port_id, trigger_id, triger);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_pps_signal_control_get(a_uint32_t dev_id,
+		a_uint32_t port_id,
+		fal_ptp_pps_signal_control_t *sig_control)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_pps_signal_control_get(dev_id, port_id, sig_control);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_capture_get(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t capture_id, fal_ptp_capture_t *capture)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_capture_get(dev_id, port_id, capture_id, capture);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_rx_crc_recalc_enable(a_uint32_t dev_id, a_uint32_t port_id,
+		a_bool_t status)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_rx_crc_recalc_enable(dev_id, port_id, status);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_security_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_security_t *sec)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_security_get(dev_id, port_id, sec);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_increment_sync_from_clock_status_get(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t *status)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_increment_sync_from_clock_status_get(dev_id, port_id, status);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_tod_uart_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_tod_uart_t *tod_uart)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_tod_uart_get(dev_id, port_id, tod_uart);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_enhanced_timestamp_engine_set(a_uint32_t dev_id,
+		a_uint32_t port_id, fal_ptp_direction_t direction,
+		fal_ptp_enhanced_ts_engine_t *ts_engine)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_enhanced_timestamp_engine_set(dev_id, port_id, direction, ts_engine);
+	FAL_API_UNLOCK;
+	return rv;
+}
+	sw_error_t
+fal_ptp_rtc_time_clear(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_rtc_time_clear(dev_id, port_id);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_reference_clock_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_reference_clock_t ref_clock)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_reference_clock_set(dev_id, port_id, ref_clock);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_output_waveform_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_output_waveform_t *waveform)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_output_waveform_set(dev_id, port_id, waveform);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_rx_timestamp_mode_set(a_uint32_t dev_id,
+		a_uint32_t port_id,
+		fal_ptp_rx_timestamp_mode_t ts_mode)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_rx_timestamp_mode_set(dev_id, port_id, ts_mode);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_grandmaster_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_grandmaster_mode_t *gm_mode)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_grandmaster_mode_set(dev_id, port_id, gm_mode);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_config_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_config_t *config)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_config_set(dev_id, port_id, config);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_trigger_get(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint32_t trigger_id, fal_ptp_trigger_t *triger)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_trigger_get(dev_id, port_id, trigger_id, triger);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_rtc_adjfreq_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_rtc_adjfreq_get(dev_id, port_id, time);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_grandmaster_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_grandmaster_mode_t *gm_mode)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_grandmaster_mode_get(dev_id, port_id, gm_mode);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_rx_timestamp_mode_get(a_uint32_t dev_id,
+		a_uint32_t port_id,
+		fal_ptp_rx_timestamp_mode_t *ts_mode)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_rx_timestamp_mode_get(dev_id, port_id, ts_mode);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_rtc_adjtime_set(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_rtc_adjtime_set(dev_id, port_id, time);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_link_delay_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_time_t *time)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_link_delay_get(dev_id, port_id, time);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_increment_sync_from_clock_enable(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t status)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_increment_sync_from_clock_enable(dev_id, port_id, status);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_config_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_config_t *config)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_config_get(dev_id, port_id, config);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_output_waveform_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_output_waveform_t *waveform)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_output_waveform_get(dev_id, port_id, waveform);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_interrupt_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_interrupt_t *interrupt)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_interrupt_get(dev_id, port_id, interrupt);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_rtc_time_snapshot_enable(a_uint32_t dev_id,
+		a_uint32_t port_id, a_bool_t status)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_rtc_time_snapshot_enable(dev_id, port_id, status);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ptp_reference_clock_get(a_uint32_t dev_id, a_uint32_t port_id,
+		fal_ptp_reference_clock_t *ref_clock)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ptp_reference_clock_get(dev_id, port_id, ref_clock);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+EXPORT_SYMBOL(fal_ptp_config_set);
+EXPORT_SYMBOL(fal_ptp_config_get);
+EXPORT_SYMBOL(fal_ptp_reference_clock_set);
+EXPORT_SYMBOL(fal_ptp_reference_clock_get);
+EXPORT_SYMBOL(fal_ptp_rx_timestamp_mode_set);
+EXPORT_SYMBOL(fal_ptp_rx_timestamp_mode_get);
+EXPORT_SYMBOL(fal_ptp_timestamp_get);
+EXPORT_SYMBOL(fal_ptp_pkt_timestamp_set);
+EXPORT_SYMBOL(fal_ptp_pkt_timestamp_get);
+EXPORT_SYMBOL(fal_ptp_grandmaster_mode_set);
+EXPORT_SYMBOL(fal_ptp_grandmaster_mode_get);
+EXPORT_SYMBOL(fal_ptp_rtc_time_get);
+EXPORT_SYMBOL(fal_ptp_rtc_time_set);
+EXPORT_SYMBOL(fal_ptp_rtc_time_clear);
+EXPORT_SYMBOL(fal_ptp_rtc_adjtime_set);
+EXPORT_SYMBOL(fal_ptp_rtc_adjfreq_set);
+EXPORT_SYMBOL(fal_ptp_rtc_adjfreq_get);
+EXPORT_SYMBOL(fal_ptp_link_delay_set);
+EXPORT_SYMBOL(fal_ptp_link_delay_get);
+EXPORT_SYMBOL(fal_ptp_security_set);
+EXPORT_SYMBOL(fal_ptp_security_get);
+EXPORT_SYMBOL(fal_ptp_pps_signal_control_set);
+EXPORT_SYMBOL(fal_ptp_pps_signal_control_get);
+EXPORT_SYMBOL(fal_ptp_rx_crc_recalc_enable);
+EXPORT_SYMBOL(fal_ptp_rx_crc_recalc_status_get);
+EXPORT_SYMBOL(fal_ptp_asym_correction_set);
+EXPORT_SYMBOL(fal_ptp_asym_correction_get);
+EXPORT_SYMBOL(fal_ptp_output_waveform_set);
+EXPORT_SYMBOL(fal_ptp_output_waveform_get);
+EXPORT_SYMBOL(fal_ptp_rtc_time_snapshot_enable);
+EXPORT_SYMBOL(fal_ptp_rtc_time_snapshot_status_get);
+EXPORT_SYMBOL(fal_ptp_increment_sync_from_clock_enable);
+EXPORT_SYMBOL(fal_ptp_increment_sync_from_clock_status_get);
+EXPORT_SYMBOL(fal_ptp_tod_uart_set);
+EXPORT_SYMBOL(fal_ptp_tod_uart_get);
+EXPORT_SYMBOL(fal_ptp_enhanced_timestamp_engine_set);
+EXPORT_SYMBOL(fal_ptp_enhanced_timestamp_engine_get);
+EXPORT_SYMBOL(fal_ptp_trigger_set);
+EXPORT_SYMBOL(fal_ptp_trigger_get);
+EXPORT_SYMBOL(fal_ptp_capture_set);
+EXPORT_SYMBOL(fal_ptp_capture_get);
+EXPORT_SYMBOL(fal_ptp_interrupt_set);
+EXPORT_SYMBOL(fal_ptp_interrupt_get);
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/fal/fal_qm.c b/qca-ssdk/src/fal/fal_qm.c
new file mode 100755
index 0000000..e2f1dc7
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_qm.c
@@ -0,0 +1,1089 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_qm FAL_QM
+ * @{
+ */
+#include "sw.h"
+#include "fal_qm.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#ifndef IN_QM_MINI
+sw_error_t
+_fal_ucast_hash_map_set(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t rss_hash,
+		a_int8_t queue_hash)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ucast_hash_map_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ucast_hash_map_set(dev_id, profile, rss_hash, queue_hash);
+	return rv;
+}
+sw_error_t
+_fal_ac_dynamic_threshold_get(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		fal_ac_dynamic_threshold_t *cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ac_dynamic_threshold_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ac_dynamic_threshold_get(dev_id, queue_id, cfg);
+	return rv;
+}
+sw_error_t
+_fal_ucast_queue_base_profile_get(
+		a_uint32_t dev_id,
+		fal_ucast_queue_dest_t *queue_dest,
+		a_uint32_t *queue_base, a_uint8_t *profile)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ucast_queue_base_profile_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ucast_queue_base_profile_get(dev_id, queue_dest, queue_base, profile);
+	return rv;
+}
+sw_error_t
+_fal_port_mcast_priority_class_get(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint8_t priority,
+		a_uint8_t *queue_class)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_mcast_priority_class_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_mcast_priority_class_get(dev_id, port, priority, queue_class);
+	return rv;
+}
+#endif
+sw_error_t
+_fal_ac_dynamic_threshold_set(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		fal_ac_dynamic_threshold_t *cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ac_dynamic_threshold_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ac_dynamic_threshold_set(dev_id, queue_id, cfg);
+	return rv;
+}
+sw_error_t
+_fal_ac_prealloc_buffer_set(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		a_uint16_t num)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ac_prealloc_buffer_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ac_prealloc_buffer_set(dev_id, obj, num);
+	return rv;
+}
+#ifndef IN_QM_MINI
+sw_error_t
+_fal_ucast_default_hash_get(
+		a_uint32_t dev_id,
+		a_uint8_t *hash_value)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ucast_default_hash_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ucast_default_hash_get(dev_id, hash_value);
+	return rv;
+}
+sw_error_t
+_fal_ucast_default_hash_set(
+		a_uint32_t dev_id,
+		a_uint8_t hash_value)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ucast_default_hash_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ucast_default_hash_set(dev_id, hash_value);
+	return rv;
+}
+sw_error_t
+_fal_ac_queue_group_get(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_uint8_t *group_id)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ac_queue_group_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ac_queue_group_get(dev_id, queue_id, group_id);
+	return rv;
+}
+sw_error_t
+_fal_ac_ctrl_get(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_ctrl_t *cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ac_ctrl_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ac_ctrl_get(dev_id, obj, cfg);
+	return rv;
+}
+sw_error_t
+_fal_ac_prealloc_buffer_get(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		a_uint16_t *num)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ac_prealloc_buffer_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ac_prealloc_buffer_get(dev_id, obj, num);
+	return rv;
+}
+sw_error_t
+_fal_port_mcast_priority_class_set(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint8_t priority,
+		a_uint8_t queue_class)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_mcast_priority_class_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_mcast_priority_class_set(dev_id, port, priority, queue_class);
+	return rv;
+}
+sw_error_t
+_fal_ucast_hash_map_get(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t rss_hash,
+		a_int8_t *queue_hash)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ucast_hash_map_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ucast_hash_map_get(dev_id, profile, rss_hash, queue_hash);
+	return rv;
+}
+#endif
+sw_error_t
+_fal_ac_static_threshold_set(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_static_threshold_t *cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ac_static_threshold_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ac_static_threshold_set(dev_id, obj, cfg);
+	return rv;
+}
+sw_error_t
+_fal_ac_queue_group_set(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_uint8_t group_id)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ac_queue_group_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ac_queue_group_set(dev_id, queue_id, group_id);
+	return rv;
+}
+#ifndef IN_QM_MINI
+sw_error_t
+_fal_ac_group_buffer_get(
+		a_uint32_t dev_id,
+		a_uint8_t group_id,
+		fal_ac_group_buffer_t *cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ac_group_buffer_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ac_group_buffer_get(dev_id, group_id, cfg);
+	return rv;
+}
+sw_error_t
+_fal_mcast_cpu_code_class_get(
+		a_uint32_t dev_id,
+		a_uint8_t cpu_code,
+		a_uint8_t *queue_class)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_mcast_cpu_code_class_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_mcast_cpu_code_class_get(dev_id, cpu_code, queue_class);
+	return rv;
+}
+#endif
+sw_error_t
+_fal_ac_ctrl_set(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_ctrl_t *cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ac_ctrl_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ac_ctrl_set(dev_id, obj, cfg);
+	return rv;
+}
+#ifndef IN_QM_MINI
+sw_error_t
+_fal_ucast_priority_class_get(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t priority,
+		a_uint8_t *class)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ucast_priority_class_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ucast_priority_class_get(dev_id, profile, priority, class);
+	return rv;
+}
+#endif
+sw_error_t
+_fal_queue_flush(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint16_t queue_id)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_queue_flush)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_queue_flush(dev_id, port, queue_id);
+	return rv;
+}
+#ifndef IN_QM_MINI
+sw_error_t
+_fal_mcast_cpu_code_class_set(
+		a_uint32_t dev_id,
+		a_uint8_t cpu_code,
+		a_uint8_t queue_class)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_mcast_cpu_code_class_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_mcast_cpu_code_class_set(dev_id, cpu_code, queue_class);
+	return rv;
+}
+sw_error_t
+_fal_ucast_priority_class_set(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t priority,
+		a_uint8_t class)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ucast_priority_class_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ucast_priority_class_set(dev_id, profile, priority, class);
+	return rv;
+}
+sw_error_t
+_fal_ac_static_threshold_get(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_static_threshold_t *cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ac_static_threshold_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ac_static_threshold_get(dev_id, obj, cfg);
+	return rv;
+}
+#endif
+sw_error_t
+_fal_ucast_queue_base_profile_set(
+		a_uint32_t dev_id,
+		fal_ucast_queue_dest_t *queue_dest,
+		a_uint32_t queue_base, a_uint8_t profile)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ucast_queue_base_profile_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ucast_queue_base_profile_set(dev_id, queue_dest, queue_base, profile);
+	return rv;
+}
+sw_error_t
+_fal_ac_group_buffer_set(
+		a_uint32_t dev_id,
+		a_uint8_t group_id,
+		fal_ac_group_buffer_t *cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ac_group_buffer_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ac_group_buffer_set(dev_id, group_id, cfg);
+	return rv;
+}
+
+#ifndef IN_QM_MINI
+sw_error_t
+_fal_queue_counter_ctrl_set(a_uint32_t dev_id, a_bool_t cnt_en)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_queue_counter_ctrl_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_queue_counter_ctrl_set(dev_id, cnt_en);
+	return rv;
+}
+
+sw_error_t
+_fal_queue_counter_ctrl_get(a_uint32_t dev_id, a_bool_t *cnt_en)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_queue_counter_ctrl_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_queue_counter_ctrl_get(dev_id, cnt_en);
+	return rv;
+}
+
+sw_error_t
+_fal_queue_counter_get(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		fal_queue_stats_t *info)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_queue_counter_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_queue_counter_get(dev_id, queue_id, info);
+	return rv;
+}
+
+sw_error_t
+_fal_queue_counter_cleanup(a_uint32_t dev_id, a_uint32_t queue_id)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_queue_counter_cleanup)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_queue_counter_cleanup(dev_id, queue_id);
+	return rv;
+}
+#endif
+
+sw_error_t
+_fal_qm_enqueue_ctrl_set(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t enable)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qm_enqueue_ctrl_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qm_enqueue_ctrl_set(dev_id, queue_id, enable);
+	return rv;
+}
+
+#ifndef IN_QM_MINI
+sw_error_t
+_fal_qm_enqueue_ctrl_get(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t *enable)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qm_enqueue_ctrl_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qm_enqueue_ctrl_get(dev_id, queue_id, enable);
+	return rv;
+}
+
+sw_error_t
+_fal_qm_port_source_profile_set(a_uint32_t dev_id, fal_port_t port, a_uint32_t src_profile)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qm_port_source_profile_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qm_port_source_profile_set(dev_id, port, src_profile);
+	return rv;
+}
+sw_error_t
+_fal_qm_port_source_profile_get(a_uint32_t dev_id, fal_port_t port, a_uint32_t *src_profile)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qm_port_source_profile_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qm_port_source_profile_get(dev_id, port, src_profile);
+	return rv;
+}
+
+/*insert flag for inner fal, don't remove it*/
+
+sw_error_t
+fal_ucast_hash_map_set(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t rss_hash,
+		a_int8_t queue_hash)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ucast_hash_map_set(dev_id, profile, rss_hash, queue_hash);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ac_dynamic_threshold_get(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		fal_ac_dynamic_threshold_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ac_dynamic_threshold_get(dev_id, queue_id, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ucast_queue_base_profile_get(
+		a_uint32_t dev_id,
+		fal_ucast_queue_dest_t *queue_dest,
+		a_uint32_t *queue_base, a_uint8_t *profile)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ucast_queue_base_profile_get(dev_id, queue_dest, queue_base, profile);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_port_mcast_priority_class_get(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint8_t priority,
+		a_uint8_t *queue_class)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_port_mcast_priority_class_get(dev_id, port, priority, queue_class);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#endif
+sw_error_t
+fal_ac_dynamic_threshold_set(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		fal_ac_dynamic_threshold_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ac_dynamic_threshold_set(dev_id, queue_id, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ac_prealloc_buffer_set(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		a_uint16_t num)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ac_prealloc_buffer_set(dev_id, obj, num);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#ifndef IN_QM_MINI
+sw_error_t
+fal_ucast_default_hash_get(
+		a_uint32_t dev_id,
+		a_uint8_t *hash_value)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ucast_default_hash_get(dev_id, hash_value);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ucast_default_hash_set(
+		a_uint32_t dev_id,
+		a_uint8_t hash_value)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ucast_default_hash_set(dev_id, hash_value);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ac_queue_group_get(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_uint8_t *group_id)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ac_queue_group_get(dev_id, queue_id, group_id);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ac_ctrl_get(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_ctrl_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ac_ctrl_get(dev_id, obj, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ac_prealloc_buffer_get(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		a_uint16_t *num)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ac_prealloc_buffer_get(dev_id, obj, num);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_port_mcast_priority_class_set(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint8_t priority,
+		a_uint8_t queue_class)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_port_mcast_priority_class_set(dev_id, port, priority, queue_class);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ucast_hash_map_get(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t rss_hash,
+		a_int8_t *queue_hash)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ucast_hash_map_get(dev_id, profile, rss_hash, queue_hash);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#endif
+sw_error_t
+fal_ac_static_threshold_set(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_static_threshold_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ac_static_threshold_set(dev_id, obj, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ac_queue_group_set(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_uint8_t group_id)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ac_queue_group_set(dev_id, queue_id, group_id);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#ifndef IN_QM_MINI
+sw_error_t
+fal_ac_group_buffer_get(
+		a_uint32_t dev_id,
+		a_uint8_t group_id,
+		fal_ac_group_buffer_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ac_group_buffer_get(dev_id, group_id, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_mcast_cpu_code_class_get(
+		a_uint32_t dev_id,
+		a_uint8_t cpu_code,
+		a_uint8_t *queue_class)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_mcast_cpu_code_class_get(dev_id, cpu_code, queue_class);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#endif
+sw_error_t
+fal_ac_ctrl_set(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_ctrl_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ac_ctrl_set(dev_id, obj, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#ifndef IN_QM_MINI
+sw_error_t
+fal_ucast_priority_class_get(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t priority,
+		a_uint8_t *class)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ucast_priority_class_get(dev_id, profile, priority, class);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#endif
+sw_error_t
+fal_queue_flush(
+		a_uint32_t dev_id,
+		fal_port_t port,
+		a_uint16_t queue_id)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_queue_flush(dev_id, port, queue_id);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#ifndef IN_QM_MINI
+sw_error_t
+fal_mcast_cpu_code_class_set(
+		a_uint32_t dev_id,
+		a_uint8_t cpu_code,
+		a_uint8_t queue_class)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_mcast_cpu_code_class_set(dev_id, cpu_code, queue_class);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ucast_priority_class_set(
+		a_uint32_t dev_id,
+		a_uint8_t profile,
+		a_uint8_t priority,
+		a_uint8_t class)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ucast_priority_class_set(dev_id, profile, priority, class);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ac_static_threshold_get(
+		a_uint32_t dev_id,
+		fal_ac_obj_t *obj,
+		fal_ac_static_threshold_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ac_static_threshold_get(dev_id, obj, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#endif
+sw_error_t
+fal_ucast_queue_base_profile_set(
+		a_uint32_t dev_id,
+		fal_ucast_queue_dest_t *queue_dest,
+		a_uint32_t queue_base, a_uint8_t profile)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ucast_queue_base_profile_set(dev_id, queue_dest, queue_base, profile);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_ac_group_buffer_set(
+		a_uint32_t dev_id,
+		a_uint8_t group_id,
+		fal_ac_group_buffer_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_ac_group_buffer_set(dev_id, group_id, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+#ifndef IN_QM_MINI
+sw_error_t
+fal_queue_counter_ctrl_set(a_uint32_t dev_id, a_bool_t cnt_en)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_queue_counter_ctrl_set(dev_id, cnt_en);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_queue_counter_ctrl_get(a_uint32_t dev_id, a_bool_t *cnt_en)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_queue_counter_ctrl_get(dev_id, cnt_en);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_queue_counter_get(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		fal_queue_stats_t *info)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_queue_counter_get(dev_id, queue_id, info);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_queue_counter_cleanup(a_uint32_t dev_id, a_uint32_t queue_id)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_queue_counter_cleanup(dev_id, queue_id);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#endif
+
+sw_error_t
+fal_qm_enqueue_ctrl_set(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qm_enqueue_ctrl_set(dev_id, queue_id, enable);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+#ifndef IN_QM_MINI
+sw_error_t
+fal_qm_enqueue_ctrl_get(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qm_enqueue_ctrl_get(dev_id, queue_id, enable);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_qm_port_source_profile_set(a_uint32_t dev_id, fal_port_t port, a_uint32_t src_profile)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qm_port_source_profile_set(dev_id, port, src_profile);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_qm_port_source_profile_get(a_uint32_t dev_id, fal_port_t port, a_uint32_t *src_profile)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qm_port_source_profile_get(dev_id, port, src_profile);
+	FAL_API_UNLOCK;
+	return rv;
+}
+#endif
+
+EXPORT_SYMBOL(fal_ac_ctrl_set);
+
+EXPORT_SYMBOL(fal_ac_prealloc_buffer_set);
+
+EXPORT_SYMBOL(fal_ac_queue_group_set);
+
+EXPORT_SYMBOL(fal_ac_static_threshold_set);
+
+EXPORT_SYMBOL(fal_ac_dynamic_threshold_set);
+
+EXPORT_SYMBOL(fal_ac_group_buffer_set);
+
+EXPORT_SYMBOL(fal_ucast_queue_base_profile_set);
+
+EXPORT_SYMBOL(fal_queue_flush);
+
+EXPORT_SYMBOL(fal_qm_enqueue_ctrl_set);
+
+#ifndef IN_QM_MINI
+EXPORT_SYMBOL(fal_qm_port_source_profile_set);
+
+EXPORT_SYMBOL(fal_qm_port_source_profile_get);
+
+EXPORT_SYMBOL(fal_qm_enqueue_ctrl_get);
+
+EXPORT_SYMBOL(fal_ac_ctrl_get);
+
+EXPORT_SYMBOL(fal_ac_prealloc_buffer_get);
+
+EXPORT_SYMBOL(fal_ac_queue_group_get);
+
+EXPORT_SYMBOL(fal_ac_static_threshold_get);
+
+EXPORT_SYMBOL(fal_ac_dynamic_threshold_get);
+
+EXPORT_SYMBOL(fal_ac_group_buffer_get);
+
+EXPORT_SYMBOL(fal_ucast_queue_base_profile_get);
+
+EXPORT_SYMBOL(fal_ucast_priority_class_set);
+
+EXPORT_SYMBOL(fal_ucast_priority_class_get);
+
+EXPORT_SYMBOL(fal_ucast_hash_map_set);
+
+EXPORT_SYMBOL(fal_ucast_hash_map_get);
+
+EXPORT_SYMBOL(fal_mcast_cpu_code_class_set);
+
+EXPORT_SYMBOL(fal_mcast_cpu_code_class_get);
+
+EXPORT_SYMBOL(fal_port_mcast_priority_class_set);
+
+EXPORT_SYMBOL(fal_port_mcast_priority_class_get);
+
+EXPORT_SYMBOL(fal_queue_counter_ctrl_set);
+
+EXPORT_SYMBOL(fal_queue_counter_ctrl_get);
+
+EXPORT_SYMBOL(fal_queue_counter_get);
+
+EXPORT_SYMBOL(fal_queue_counter_cleanup);
+#endif
+
+/*insert flag for outter fal, don't remove it*/
diff --git a/qca-ssdk/src/fal/fal_qos.c b/qca-ssdk/src/fal/fal_qos.c
new file mode 100644
index 0000000..fcb8dc7
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_qos.c
@@ -0,0 +1,2000 @@
+/*
+ * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_qos FAL_QOS
+ * @{
+ */
+#include "sw.h"
+#include "fal_qos.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#ifndef IN_QOS_MINI
+static sw_error_t
+_fal_qos_sch_mode_set(a_uint32_t dev_id,
+                      fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_sch_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_sch_mode_set(dev_id, mode, weight);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_qos_sch_mode_get(a_uint32_t dev_id,
+                      fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_sch_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_sch_mode_get(dev_id, mode, weight);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_queue_tx_buf_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_queue_tx_buf_status_set(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_queue_tx_buf_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_queue_tx_buf_status_get(dev_id, port_id, enable);
+    return rv;
+}
+
+
+
+
+static sw_error_t
+_fal_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_queue_tx_buf_nr_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_tx_buf_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_tx_buf_status_set(dev_id, port_id, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_tx_buf_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_tx_buf_status_get(dev_id, port_id, enable);
+    return rv;
+}
+
+
+
+
+
+static sw_error_t
+_fal_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t* enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_red_en_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_red_en_get(dev_id, port_id, enable);
+    return rv;
+}
+
+
+
+
+static sw_error_t
+_fal_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_tx_buf_nr_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_tx_buf_nr_get(dev_id, port_id, number);
+    return rv;
+}
+
+
+
+
+static sw_error_t
+_fal_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_rx_buf_nr_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_rx_buf_nr_get(dev_id, port_id, number);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, fal_queue_t queue)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_up_queue_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_up_queue_set(dev_id, up, queue);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+                         fal_queue_t * queue)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_up_queue_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_up_queue_get(dev_id, up, queue);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, fal_queue_t queue)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_dscp_queue_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_dscp_queue_set(dev_id, dscp, queue);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+                           fal_queue_t * queue)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->cosmap_dscp_queue_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->cosmap_dscp_queue_get(dev_id, dscp, queue);
+    return rv;
+}
+#endif
+static sw_error_t
+_fal_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_red_en_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_red_en_set(dev_id, port_id, enable);
+    return rv;
+}
+static sw_error_t
+_fal_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_queue_tx_buf_nr_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number);
+    return rv;
+}
+static sw_error_t
+_fal_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_rx_buf_nr_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_rx_buf_nr_set(dev_id, port_id, number);
+    return rv;
+}
+static sw_error_t
+_fal_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_tx_buf_nr_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_tx_buf_nr_set(dev_id, port_id, number);
+    return rv;
+}
+
+static sw_error_t
+_fal_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_qos_mode_t mode, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_mode_set(dev_id, port_id, mode, enable);
+    return rv;
+}
+
+
+
+
+#ifndef IN_QOS_MINI
+static sw_error_t
+_fal_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_qos_mode_t mode, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_mode_get(dev_id, port_id, mode, enable);
+    return rv;
+}
+static sw_error_t
+_fal_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_qos_mode_t mode, a_uint32_t pri)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_qos_port_mode_pri_set)
+            return SW_NOT_SUPPORTED;
+        rv = p_adpt_api->adpt_qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_mode_pri_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_qos_mode_t mode, a_uint32_t * pri)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_qos_port_mode_pri_get)
+            return SW_NOT_SUPPORTED;
+        rv = p_adpt_api->adpt_qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_mode_pri_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t up)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_default_up_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_default_up_set(dev_id, port_id, up);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * up)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_default_up_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_default_up_get(dev_id, port_id, up);
+    return rv;
+}
+
+static sw_error_t
+_fal_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                           fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_sch_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_sch_mode_set(dev_id, port_id, mode, weight);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                           fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_sch_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_sch_mode_get(dev_id, port_id, mode, weight);
+    return rv;
+}
+
+static sw_error_t
+_fal_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t spri)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_default_spri_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_default_spri_set(dev_id, port_id, spri);
+    return rv;
+}
+
+static sw_error_t
+_fal_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * spri)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_default_spri_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_default_spri_get(dev_id, port_id, spri);
+    return rv;
+}
+
+static sw_error_t
+_fal_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t cpri)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_default_cpri_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_default_cpri_set(dev_id, port_id, cpri);
+    return rv;
+}
+
+static sw_error_t
+_fal_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * cpri)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_default_cpri_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_default_cpri_get(dev_id, port_id, cpri);
+    return rv;
+}
+
+static sw_error_t
+_fal_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_force_spri_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_force_spri_status_set(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t* enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_force_spri_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_force_spri_status_get(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_force_cpri_status_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_force_cpri_status_set(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t* enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_port_force_cpri_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_port_force_cpri_status_get(dev_id, port_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_queue_remark_table_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_queue_remark_table_set(dev_id, port_id, queue_id, tbl_id, enable);
+    return rv;
+}
+
+static sw_error_t
+_fal_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->qos_queue_remark_table_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->qos_queue_remark_table_get(dev_id, port_id, queue_id, tbl_id, enable);
+    return rv;
+}
+#endif
+
+sw_error_t
+_fal_qos_port_pri_precedence_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_pri_precedence_t *pri)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qos_port_pri_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qos_port_pri_set(dev_id, port_id, pri);
+	return rv;
+}
+sw_error_t
+_fal_qos_port_pri_precedence_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_pri_precedence_t *pri)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qos_port_pri_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qos_port_pri_get(dev_id, port_id, pri);
+	return rv;
+}
+sw_error_t
+_fal_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t pcp, fal_qos_cosmap_t *cosmap)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qos_cosmap_pcp_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qos_cosmap_pcp_get(dev_id, group_id, pcp, cosmap);
+	return rv;
+}
+sw_error_t 
+_fal_queue_scheduler_set(a_uint32_t dev_id,
+					a_uint32_t node_id, fal_queue_scheduler_level_t level,
+					fal_port_t port_id,
+					fal_qos_scheduler_cfg_t *scheduler_cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_queue_scheduler_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_queue_scheduler_set(dev_id, node_id,
+					level, port_id, scheduler_cfg);
+	return rv;
+}
+sw_error_t 
+_fal_queue_scheduler_get(a_uint32_t dev_id,
+					a_uint32_t node_id, fal_queue_scheduler_level_t level,
+					fal_port_t *port_id,
+					fal_qos_scheduler_cfg_t *scheduler_cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_queue_scheduler_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_queue_scheduler_get(dev_id, node_id,
+					level, port_id, scheduler_cfg);
+	return rv;
+}
+sw_error_t
+_fal_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t pcp, fal_qos_cosmap_t *cosmap)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qos_cosmap_pcp_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qos_cosmap_pcp_set(dev_id, group_id, pcp, cosmap);
+	return rv;
+}
+sw_error_t
+_fal_qos_port_remark_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_remark_enable_t *remark)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qos_port_remark_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qos_port_remark_get(dev_id, port_id, remark);
+	return rv;
+}
+sw_error_t
+_fal_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t dscp, fal_qos_cosmap_t *cosmap)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qos_cosmap_dscp_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qos_cosmap_dscp_get(dev_id, group_id, dscp, cosmap);
+	return rv;
+}
+sw_error_t
+_fal_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint16_t flow, fal_qos_cosmap_t *cosmap)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qos_cosmap_flow_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qos_cosmap_flow_set(dev_id, group_id, flow, cosmap);
+	return rv;
+}
+sw_error_t
+_fal_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_group_t *group)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qos_port_group_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qos_port_group_set(dev_id, port_id, group);
+	return rv;
+}
+sw_error_t
+_fal_edma_ring_queue_map_set(a_uint32_t dev_id, 
+					a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ring_queue_map_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ring_queue_map_set(dev_id, ring_id, queue_bmp);
+	return rv;
+}
+sw_error_t
+_fal_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t dscp, fal_qos_cosmap_t *cosmap)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qos_cosmap_dscp_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qos_cosmap_dscp_set(dev_id, group_id, dscp, cosmap);
+	return rv;
+}
+sw_error_t
+_fal_qos_port_remark_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_remark_enable_t *remark)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qos_port_remark_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qos_port_remark_set(dev_id, port_id, remark);
+	return rv;
+}
+
+sw_error_t
+_fal_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint16_t flow, fal_qos_cosmap_t *cosmap)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qos_cosmap_flow_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qos_cosmap_flow_get(dev_id, group_id, flow, cosmap);
+	return rv;
+}
+sw_error_t
+_fal_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_group_t *group)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_qos_port_group_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_qos_port_group_get(dev_id, port_id, group);
+	return rv;
+}
+sw_error_t
+_fal_edma_ring_queue_map_get(a_uint32_t dev_id, 
+					a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_ring_queue_map_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_ring_queue_map_get(dev_id, ring_id, queue_bmp);
+	return rv;
+}
+
+sw_error_t
+_fal_port_queues_get(a_uint32_t dev_id, 
+				fal_port_t port_id, fal_queue_bmp_t *queue_bmp)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_queues_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_queues_get(dev_id, port_id, queue_bmp);
+	return rv;
+}
+
+sw_error_t
+_fal_scheduler_dequeue_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_bool_t enable)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_scheduler_dequeue_ctrl_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_scheduler_dequeue_ctrl_set(dev_id, queue_id, enable);
+	return rv;
+}
+
+sw_error_t
+_fal_scheduler_dequeue_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_bool_t *enable)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_scheduler_dequeue_ctrl_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_scheduler_dequeue_ctrl_get(dev_id, queue_id, enable);
+	return rv;
+}
+
+sw_error_t
+_fal_port_scheduler_cfg_reset(
+		a_uint32_t dev_id,
+		fal_port_t port_id)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_scheduler_cfg_reset)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_scheduler_cfg_reset(dev_id, port_id);
+	return rv;
+}
+
+sw_error_t
+_fal_port_scheduler_resource_get(
+		a_uint32_t dev_id,
+		fal_port_t port_id,
+		fal_portscheduler_resource_t *cfg)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_port_scheduler_resource_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_port_scheduler_resource_get(dev_id, port_id, cfg);
+	return rv;
+}
+#ifndef IN_QOS_MINI
+/*insert flag for inner fal, don't remove it*/
+
+/**
+ * @brief Set traffic scheduling mode on particular one device.
+ *   @details   Comments:
+ *   Particular device may only support parts of input options. Such as
+ *    GARUDA doesn't support variable weight in wrr mode.
+ *    When scheduling mode is sp the weight is meaningless usually it's zero
+ * @param[in] dev_id device id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[in] weight[] weight value for each queue when in wrr mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_sch_mode_set(a_uint32_t dev_id,
+                     fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_sch_mode_set(dev_id, mode, weight);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get traffic scheduling mode on particular device.
+ * @param[in] dev_id device id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[out] weight weight value for wrr mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_sch_mode_get(a_uint32_t dev_id,
+                     fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_sch_mode_get(dev_id, mode, weight);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting queue on one particular port.
+ *   @details  Comments:
+ *    If enable queue tx buffer on one port that means each queue of this port
+ *    will have fixed number buffers when transmitting packets. Otherwise they
+ *    share the whole buffers with other queues in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_queue_tx_buf_status_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting queue on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_queue_tx_buf_status_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+
+/**
+ * @brief Get max occupied buffer number of transmitting queue on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting port on one particular port.
+ *   @details   Comments:
+ *     If enable tx buffer on one port that means this port will have fixed
+ *    number buffers when transmitting packets. Otherwise they will
+ *    share the whole buffers with other ports in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_tx_buf_status_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_tx_buf_status_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+
+/**
+ * @brief Set status of port red on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_red_en_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+
+
+/**
+ * @brief Get max occupied buffer number of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_tx_buf_nr_get(dev_id, port_id, number);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+
+/**
+ * @brief Get max reserved buffer number of receiving port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_rx_buf_nr_get(dev_id, port_id, number);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set user priority to queue mapping.
+ * @param[in] dev_id device id
+ * @param[in] up 802.1p
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, fal_queue_t queue)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_up_queue_set(dev_id, up, queue);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get user priority to queue mapping.
+ * @param[in] dev_id device id
+ * @param[in] dot1p 802.1p
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+                        fal_queue_t * queue)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_up_queue_get(dev_id, up, queue);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, fal_queue_t queue)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_dscp_queue_set(dev_id, dscp, queue);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+                          fal_queue_t * queue)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_cosmap_dscp_queue_get(dev_id, dscp, queue);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set max occupied buffer number of transmitting queue on one particular port.
+ *   @details  Comments:
+ *    Because different device has differnet hardware granularity
+ *    function will return actual buffer numbers in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number);
+    FAL_API_UNLOCK;
+    return rv;
+}
+/**
+ * @brief Set status of port red on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_red_en_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+/**
+ * @brief Set max occupied buffer number of transmitting port on one particular port.
+ *   @details   Comments:
+ *    Because different device has differnet hardware granularity
+ *    function will return actual buffer number in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_tx_buf_nr_set(dev_id, port_id, number);
+    FAL_API_UNLOCK;
+    return rv;
+}
+/**
+ * @brief Set max reserved buffer number of receiving port on one particular port.
+ *   @details   Comments:
+ *    Because different device has differnet hardware granularity
+ *    function will return actual buffer number in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_rx_buf_nr_set(dev_id, port_id, number);
+    FAL_API_UNLOCK;
+    return rv;
+}
+/**
+ * @brief Set port qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_qos_mode_t mode, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_mode_set(dev_id, port_id, mode, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+#ifndef IN_QOS_MINI
+/**
+ * @brief Get port qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_qos_mode_t mode, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_mode_get(dev_id, port_id, mode, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+/**
+ * @brief Set priority of one particular qos mode on one particular port.
+ *   @details   Comments:
+ *    If the priority of a mode is more small then the priority is more high.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_qos_mode_t mode, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get priority of one particular qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_qos_mode_t mode, a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] up 802.1p
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t up)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_default_up_set(dev_id, port_id, up);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] up 802.1p
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * up)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_default_up_get(dev_id, port_id, up);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set traffic scheduling mode on particular one port.
+ *   @details   Comments:
+ *   Particular device may only support parts of input options. Such as
+ *    GARUDA doesn't support variable weight in wrr mode.
+ *    When scheduling mode is sp the weight is meaningless usually it's zero
+ * @param[in] dev_id device id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[in] weight[] weight value for each queue when in wrr mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                          fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_sch_mode_set(dev_id, port_id, mode, weight);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get traffic scheduling mode on particular port.
+ * @param[in] dev_id device id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[out] weight weight value for wrr mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                          fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_sch_mode_get(dev_id, port_id, mode, weight);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default stag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] spri vlan priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t spri)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_default_spri_set(dev_id, port_id, spri);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default stag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] spri vlan priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * spri)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_default_spri_get(dev_id, port_id, spri);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default ctag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cpri vlan priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t cpri)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_default_cpri_set(dev_id, port_id, cpri);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default ctag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cpri vlan priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * cpri)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_default_cpri_get(dev_id, port_id, cpri);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set force stag priority flag on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_force_spri_status_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+/**
+ * @brief Get force stag priority flag on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_force_spri_status_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set force ctag priority flag on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_force_cpri_status_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get force ctag priority flag on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_port_force_cpri_status_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress queue based CoS remark on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[in] tbl_id CoS remark table id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_queue_remark_table_set(dev_id, port_id, queue_id, tbl_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress queue based CoS remark on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] tbl_id CoS remark table id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+
+sw_error_t
+fal_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_qos_queue_remark_table_get(dev_id, port_id, queue_id, tbl_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+sw_error_t
+fal_qos_port_pri_precedence_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_pri_precedence_t *pri)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qos_port_pri_precedence_set(dev_id, port_id, pri);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_qos_port_pri_precedence_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_pri_precedence_t *pri)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qos_port_pri_precedence_get(dev_id, port_id, pri);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t pcp, fal_qos_cosmap_t *cosmap)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qos_cosmap_pcp_get(dev_id, group_id, pcp, cosmap);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_queue_scheduler_set(a_uint32_t dev_id,
+					a_uint32_t node_id, fal_queue_scheduler_level_t level,
+					fal_port_t port_id,
+					fal_qos_scheduler_cfg_t *scheduler_cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_queue_scheduler_set(dev_id, node_id, level, port_id, scheduler_cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_queue_scheduler_get(a_uint32_t dev_id,
+					a_uint32_t node_id, fal_queue_scheduler_level_t level,
+					fal_port_t *port_id,
+					fal_qos_scheduler_cfg_t *scheduler_cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_queue_scheduler_get(dev_id, node_id, level, port_id, scheduler_cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t pcp, fal_qos_cosmap_t *cosmap)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qos_cosmap_pcp_set(dev_id, group_id, pcp, cosmap);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_qos_port_remark_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_remark_enable_t *remark)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qos_port_remark_get(dev_id, port_id, remark);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t dscp, fal_qos_cosmap_t *cosmap)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qos_cosmap_dscp_get(dev_id, group_id, dscp, cosmap);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint16_t flow, fal_qos_cosmap_t *cosmap)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qos_cosmap_flow_set(dev_id, group_id, flow, cosmap);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_group_t *group)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qos_port_group_set(dev_id, port_id, group);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_edma_ring_queue_map_set(a_uint32_t dev_id, 
+					a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_edma_ring_queue_map_set(dev_id, ring_id, queue_bmp);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint8_t dscp, fal_qos_cosmap_t *cosmap)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qos_cosmap_dscp_set(dev_id, group_id, dscp, cosmap);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_qos_port_remark_set(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_remark_enable_t *remark)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qos_port_remark_set(dev_id, port_id, remark);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id,
+					a_uint16_t flow, fal_qos_cosmap_t *cosmap)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qos_cosmap_flow_get(dev_id, group_id, flow, cosmap);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id,
+					fal_qos_group_t *group)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_qos_port_group_get(dev_id, port_id, group);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_edma_ring_queue_map_get(a_uint32_t dev_id, 
+					a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_edma_ring_queue_map_get(dev_id, ring_id, queue_bmp);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_port_queues_get(a_uint32_t dev_id, 
+				fal_port_t port_id, fal_queue_bmp_t *queue_bmp)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_port_queues_get(dev_id, port_id, queue_bmp);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_scheduler_dequeue_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_scheduler_dequeue_ctrl_set(dev_id, queue_id, enable);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_scheduler_dequeue_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t queue_id,
+		a_bool_t *enable)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_scheduler_dequeue_ctrl_get(dev_id, queue_id, enable);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_port_scheduler_cfg_reset(
+		a_uint32_t dev_id,
+		fal_port_t port_id)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_port_scheduler_cfg_reset(dev_id, port_id);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_port_scheduler_resource_get(
+		a_uint32_t dev_id,
+		fal_port_t port_id,
+		fal_portscheduler_resource_t *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_port_scheduler_resource_get(dev_id, port_id, cfg);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+EXPORT_SYMBOL(fal_scheduler_dequeue_ctrl_get);
+
+EXPORT_SYMBOL(fal_scheduler_dequeue_ctrl_set);
+
+EXPORT_SYMBOL(fal_queue_scheduler_set);
+
+EXPORT_SYMBOL(fal_queue_scheduler_get);
+
+EXPORT_SYMBOL(fal_port_queues_get);
+
+EXPORT_SYMBOL(fal_qos_port_pri_precedence_set);
+
+EXPORT_SYMBOL(fal_qos_port_pri_precedence_get);
+
+EXPORT_SYMBOL(fal_qos_port_group_set);
+
+EXPORT_SYMBOL(fal_qos_port_group_get);
+
+EXPORT_SYMBOL(fal_qos_cosmap_pcp_set);
+
+EXPORT_SYMBOL(fal_qos_cosmap_pcp_get);
+
+EXPORT_SYMBOL(fal_qos_cosmap_dscp_set);
+
+EXPORT_SYMBOL(fal_qos_cosmap_dscp_get);
+
+EXPORT_SYMBOL(fal_qos_cosmap_flow_set);
+
+EXPORT_SYMBOL(fal_qos_port_remark_set);
+
+EXPORT_SYMBOL(fal_qos_port_remark_get);
+
+EXPORT_SYMBOL(fal_edma_ring_queue_map_set);
+
+EXPORT_SYMBOL(fal_edma_ring_queue_map_get);
+
+EXPORT_SYMBOL(fal_port_scheduler_cfg_reset);
+
+EXPORT_SYMBOL(fal_port_scheduler_resource_get);
+
+/*insert flag for outter fal, don't remove it*/
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/fal/fal_rate.c b/qca-ssdk/src/fal/fal_rate.c
new file mode 100755
index 0000000..1298837
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_rate.c
@@ -0,0 +1,840 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_rate FAL_RATE
+ * @{
+ */
+#include "sw.h"
+#include "fal_rate.h"
+#include "hsl_api.h"
+
+
+static sw_error_t
+_fal_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_queue_t queue_id, a_uint32_t * speed,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_queue_egrl_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_queue_egrl_set(dev_id, port_id, queue_id, speed, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_queue_t queue_id, a_uint32_t * speed,
+                         a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_queue_egrl_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_queue_egrl_get(dev_id, port_id, queue_id, speed, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_port_egrl_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_port_egrl_set(dev_id, port_id, speed, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_port_egrl_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_port_egrl_get(dev_id, port_id, speed, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_port_inrl_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_port_inrl_set(dev_id, port_id, speed, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_port_inrl_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_port_inrl_get(dev_id, port_id, speed, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_storm_type_t frame_type, a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->storm_ctrl_frame_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->storm_ctrl_frame_set(dev_id, port_id, frame_type, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_storm_type_t frame_type, a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->storm_ctrl_frame_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->storm_ctrl_frame_get(dev_id, port_id, frame_type, enable);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t * rate)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->storm_ctrl_rate_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->storm_ctrl_rate_set(dev_id, port_id, rate);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t * rate)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->storm_ctrl_rate_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->storm_ctrl_rate_get(dev_id, port_id, rate);
+    return rv;
+}
+
+static sw_error_t
+_fal_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_port_policer_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_port_policer_set(dev_id, port_id, policer);
+    return rv;
+}
+
+static sw_error_t
+_fal_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_port_policer_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_port_policer_get(dev_id, port_id, policer);
+    return rv;
+}
+
+static sw_error_t
+_fal_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_port_shaper_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_port_shaper_set(dev_id, port_id, enable, shaper);
+    return rv;
+}
+
+static sw_error_t
+_fal_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_port_shaper_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_port_shaper_get(dev_id, port_id, enable, shaper);
+    return rv;
+}
+
+static sw_error_t
+_fal_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_queue_t queue_id, a_bool_t enable,
+                           fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_queue_shaper_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_queue_shaper_set(dev_id, port_id, queue_id, enable, shaper);
+    return rv;
+}
+
+static sw_error_t
+_fal_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_queue_t queue_id, a_bool_t * enable,
+                           fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_queue_shaper_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_queue_shaper_get(dev_id, port_id, queue_id, enable, shaper);
+    return rv;
+}
+
+static sw_error_t
+_fal_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+                          fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_acl_policer_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_acl_policer_set(dev_id, policer_id, policer);
+    return rv;
+}
+
+static sw_error_t
+_fal_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+                          fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_acl_policer_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_acl_policer_get(dev_id, policer_id, policer);
+    return rv;
+}
+
+sw_error_t
+_fal_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t  number)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_port_add_rate_byte_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_port_add_rate_byte_set(dev_id, port_id, number);
+    return rv;
+}
+
+sw_error_t
+_fal_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t  *number)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_port_add_rate_byte_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_port_add_rate_byte_get(dev_id, port_id, number);
+    return rv;
+}
+
+sw_error_t
+_fal_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t  enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_port_gol_flow_en_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_port_gol_flow_en_set(dev_id, port_id, enable);
+    return rv;
+}
+
+sw_error_t
+_fal_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t  *enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->rate_port_gol_flow_en_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->rate_port_gol_flow_en_get(dev_id, port_id, enable);
+    return rv;
+}
+
+
+
+/**
+ * @brief Set queue egress rate limit status on one particular port and queue.
+ *   @details   Comments:
+ *    The granularity of speed is bps.
+ *    Because different device has differnet hardware granularity function
+ *    will return actual speed in hardware.
+ *    When disable queue egress rate limit input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_queue_t queue_id, a_uint32_t * speed,
+                        a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_queue_egrl_set(dev_id, port_id, queue_id, speed, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get queue egress rate limit status on one particular port and queue.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_queue_t queue_id, a_uint32_t * speed,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_queue_egrl_get(dev_id, port_id, queue_id, speed, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port egress rate limit status on one particular port.
+ *   @details   Comments:
+ *    The granularity of speed is bps.
+ *    Because different device has differnet hardware granularity function
+ *    will return actual speed in hardware.
+ *    When disable port egress rate limit input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                       a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_port_egrl_set(dev_id, port_id, speed, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port egress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                       a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_port_egrl_get(dev_id, port_id, speed, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port ingress rate limit status on one particular port.
+ *   @details   Comments:
+ *   The granularity of speed is bps.
+ *    Because different device has differnet hardware granularity function
+ *    will return actual speed in hardware.
+ *    When disable port ingress rate limit input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                       a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_port_inrl_set(dev_id, port_id, speed, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port ingress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                       a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_port_inrl_get(dev_id, port_id, speed, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set particular type storm control status on one particular port.
+ *   @details   Comments:
+ *    When enable one particular packets type storm control this type packets
+ *    speed will be calculated in storm control.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_storm_type_t frame_type, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_storm_ctrl_frame_set(dev_id, port_id, frame_type, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get particular type storm control status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_storm_type_t frame_type, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_storm_ctrl_frame_get(dev_id, port_id, frame_type, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set storm control speed on one particular port.
+ *   @details   Comments:
+ *   The granularity of speed is packets per second.
+ *    Because different device has differnet hardware granularity function
+ *    will return actual speed in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed storm control speed
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_uint32_t * rate)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_storm_ctrl_rate_set(dev_id, port_id, rate);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get storm control speed on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed storm control speed
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_uint32_t * rate)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_storm_ctrl_rate_get(dev_id, port_id, rate);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port ingress policer parameters on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] policer port ingress policer parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_port_policer_set(dev_id, port_id, policer);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port ingress policer parameters on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] policer port ingress policer parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_port_policer_get(dev_id, port_id, policer);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port egress shaper parameters on one particular port.
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_port_shaper_set(dev_id, port_id, enable, shaper);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port egress shaper parameters on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_port_shaper_get(dev_id, port_id, enable, shaper);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set queue egress shaper parameters on one particular port.
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_queue_t queue_id, a_bool_t enable,
+                          fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_queue_shaper_set(dev_id, port_id, queue_id, enable, shaper);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get queue egress shaper parameters on one particular port.
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_queue_t queue_id, a_bool_t * enable,
+                          fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_queue_shaper_get(dev_id, port_id, queue_id, enable, shaper);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ACL ingress policer parameters.
+ * @param[in] dev_id device id
+ * @param[in] policer_id ACL policer id
+ * @param[in] policer ACL ingress policer parameters
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+                         fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_acl_policer_set(dev_id, policer_id, policer);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ACL ingress policer parameters.
+ * @param[in] dev_id device id
+ * @param[in] policer_id ACL policer id
+ * @param[in] policer ACL ingress policer parameters
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+                         fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_acl_policer_get(dev_id, policer_id, policer);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+sw_error_t
+fal_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t  number)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_port_add_rate_byte_set(dev_id, port_id, number);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t  *number)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_port_add_rate_byte_get(dev_id, port_id, number);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of port global flow control when global threshold is reached.
+  * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_port_gol_flow_en_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief get status of port global flow control when global threshold is reached.
+  * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_rate_port_gol_flow_en_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/fal/fal_reg_access.c b/qca-ssdk/src/fal/fal_reg_access.c
new file mode 100755
index 0000000..c578def
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_reg_access.c
@@ -0,0 +1,570 @@
+/*
+ * Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*qca808x_start*/
+/**
+ * @defgroup fal_reg_access FAL_REG_ACCESS
+ * @{
+ */
+#include "sw.h"
+#include "fal_reg_access.h"
+#include "hsl_api.h"
+#include "hsl_phy.h"
+
+static sw_error_t
+_fal_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+             a_uint32_t reg, a_uint16_t * value)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    a_uint8_t phy_addr_type;
+    hsl_phy_get phy_get_func;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    /* the MSB first byte of phy_addr marks the type of
+     * phy address, such as the i2c address, the value of
+     * MSB first byte should be 1 */
+    phy_addr_type = (phy_addr & 0xff000000) >> 24;
+    phy_addr = phy_addr & 0xff;
+    switch (phy_addr_type) {
+	    case PHY_I2C_ACCESS:
+		    phy_get_func = p_api->phy_i2c_get;
+		    break;
+	    default:
+		    phy_get_func = p_api->phy_get;
+		    break;
+    }
+
+    if (NULL == phy_get_func) {
+	    return SW_NOT_SUPPORTED;
+    }
+
+    rv = phy_get_func(dev_id, phy_addr, reg, value);
+    return rv;
+}
+
+static sw_error_t
+_fal_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+             a_uint32_t reg, a_uint16_t value)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    a_uint8_t phy_addr_type;
+    hsl_phy_set phy_set_func;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    /* the MSB first byte of phy_addr marks the type of
+     * phy address, such as the i2c address, the value of
+     * MSB first byte should be 1 */
+    phy_addr_type = (phy_addr & 0xff000000) >> 24;
+    phy_addr = phy_addr & 0xff;
+    switch (phy_addr_type) {
+	    case PHY_I2C_ACCESS:
+		    phy_set_func = p_api->phy_i2c_set;
+		    break;
+	    default:
+		    phy_set_func = p_api->phy_set;
+		    break;
+    }
+
+    if (NULL == phy_set_func) {
+	    return SW_NOT_SUPPORTED;
+    }
+
+    rv = phy_set_func(dev_id, phy_addr, reg, value);
+    return rv;
+}
+/*qca808x_end*/
+static sw_error_t
+_fal_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+             a_uint32_t value_len)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->reg_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->reg_get(dev_id, reg_addr, value, value_len);
+    return rv;
+}
+
+static sw_error_t
+_fal_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+             a_uint32_t value_len)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->reg_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->reg_set(dev_id, reg_addr, value, value_len);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_psgmii_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+             a_uint32_t value_len)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->psgmii_reg_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->psgmii_reg_get(dev_id, reg_addr, value, value_len);
+    return rv;
+}
+
+static sw_error_t
+_fal_psgmii_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+             a_uint32_t value_len)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->psgmii_reg_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->psgmii_reg_set(dev_id, reg_addr, value, value_len);
+    return rv;
+}
+
+static sw_error_t
+_fal_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint32_t bit_offset, a_uint32_t field_len,
+                   a_uint8_t value[], a_uint32_t value_len)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->reg_field_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->reg_field_get(dev_id, reg_addr, bit_offset, field_len, value, value_len);
+    return rv;
+}
+
+static sw_error_t
+_fal_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint32_t bit_offset, a_uint32_t field_len,
+                   const a_uint8_t value[], a_uint32_t value_len)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->reg_field_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->reg_field_set(dev_id, reg_addr, bit_offset, field_len, value, value_len);
+    return rv;
+}
+
+static sw_error_t
+_fal_reg_dump(a_uint32_t dev_id, a_uint32_t reg_idx,fal_reg_dump_t *reg_dump)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->register_dump)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->register_dump(dev_id, reg_idx,reg_dump);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_debug_reg_dump(a_uint32_t dev_id, fal_debug_reg_dump_t *reg_dump)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->debug_register_dump)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->debug_register_dump(dev_id, reg_dump);
+    return rv;
+}
+
+static sw_error_t
+_fal_debug_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable,
+            a_uint32_t times, a_uint32_t *result)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->debug_psgmii_self_test)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->debug_psgmii_self_test(dev_id, enable, times, result);
+    return rv;
+}
+
+static sw_error_t
+_fal_phy_dump(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t idx,fal_phy_dump_t *phy_dump)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->phy_dump)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->phy_dump(dev_id, phy_addr,idx,phy_dump);
+    return rv;
+}
+static sw_error_t
+_fal_uniphy_reg_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr,
+		a_uint8_t value[], a_uint32_t value_len)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->uniphy_reg_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->uniphy_reg_get(dev_id, index, reg_addr, value, value_len);
+    return rv;
+}
+
+static sw_error_t
+_fal_uniphy_reg_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr,
+		a_uint8_t value[], a_uint32_t value_len)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->uniphy_reg_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->uniphy_reg_set(dev_id, index, reg_addr, value, value_len);
+    return rv;
+}
+/*qca808x_start*/
+/**
+  * fal_phy_get - get value of specific phy device
+  * @phy_addr: id of the phy device
+  * @reg: register id of phy device
+  * @value: pointer to the memory storing the value.
+  * @return SW_OK or error code
+  */
+sw_error_t
+fal_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+            a_uint32_t reg, a_uint16_t * value)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_phy_get(dev_id, phy_addr, reg, value);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * fal_phy_set - set value of specific phy device
+  * @phy_addr: id of the phy device
+  * @reg: register id of phy device
+  * @value: register value.
+  * @return SW_OK or error code
+  */
+sw_error_t
+fal_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+            a_uint32_t reg, a_uint16_t value)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_phy_set(dev_id, phy_addr, reg, value);
+    FAL_API_UNLOCK;
+    return rv;
+}
+/*qca808x_end*/
+/**
+  * fal_reg_get - get value of specific register
+  * @reg_addr: address of the register
+  * @value: pointer to the memory storing the value.
+  * @value_len: length of the value.
+  *
+  * Get the value of a specific register field with related parameter
+  */
+sw_error_t
+fal_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+            a_uint32_t value_len)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_reg_get(dev_id, reg_addr, value, value_len);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * fal_reg_set - set value of specific register
+  * @reg_addr: address of the register
+  * @value: pointer to the memory storing the value.
+  * @value_len: length of the value.
+  *
+  * Get the value of a specific register field with related parameter
+  */
+sw_error_t
+fal_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+            a_uint32_t value_len)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_reg_set(dev_id, reg_addr, value, value_len);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * fal_psgmii_reg_get - get value of specific register in psgmii module
+  * @reg_addr: address of the register
+  * @value: pointer to the memory storing the value.
+  * @value_len: length of the value.
+  *
+  * Get the value of a specific register field with related parameter
+  */
+sw_error_t
+fal_psgmii_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+            a_uint32_t value_len)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_psgmii_reg_get(dev_id, reg_addr, value, value_len);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * fal_psgmii_reg_set - set value of specific register in psgmii module
+  * @reg_addr: address of the register
+  * @value: pointer to the memory storing the value.
+  * @value_len: length of the value.
+  *
+  * Get the value of a specific register field with related parameter
+  */
+sw_error_t
+fal_psgmii_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+            a_uint32_t value_len)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_psgmii_reg_set(dev_id, reg_addr, value, value_len);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * fal_reg_field_get - get value of specific register field
+  * @reg_addr: address of the register
+  * @bit_offset: position of the field in bit
+  * @field_len: length of the field in bit
+  * @value: pointer to the memory storing the value.
+  * @value_len: length of the value.
+  *
+  * Get the value of a specific register field with related parameter
+  */
+sw_error_t
+fal_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                  a_uint32_t bit_offset, a_uint32_t field_len,
+                  a_uint8_t value[], a_uint32_t value_len)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_reg_field_get(dev_id, reg_addr, bit_offset, field_len, value, value_len);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * fal_reg_field_set - set value of specific register field
+  * @reg_addr: address of the register
+  * @bit_offset: position of the field in bit
+  * @field_len: length of the field in bit
+  * @value: pointer to the memory storing the value.
+  * @value_len: length of the value.
+  *
+  * Set the value of a specific register field with related parameter
+  */
+sw_error_t
+fal_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                  a_uint32_t bit_offset, a_uint32_t field_len,
+                  const a_uint8_t value[], a_uint32_t value_len)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_reg_field_set(dev_id, reg_addr, bit_offset, field_len, value, value_len);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief dump device register group
+ * @details   Comments:
+ *    The unit of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[out] reg_dump dump out register group
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_reg_dump(a_uint32_t dev_id, a_uint32_t reg_idx,fal_reg_dump_t *reg_dump)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_reg_dump(dev_id, reg_idx,reg_dump);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief dump device debug register
+ * @details   Comments:
+ *    The unit of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[out] reg_dump dump out debub register
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_debug_reg_dump(a_uint32_t dev_id, fal_debug_reg_dump_t *reg_dump)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_debug_reg_dump(dev_id,reg_dump);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief psgmii self test
+ * @details   Comments:
+ *    The unit of packets size is byte.
+ * @param[in] dev_id device id, enable, times
+ * @param[out] status
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_debug_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable,
+            a_uint32_t times, a_uint32_t *result)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_debug_psgmii_self_test(dev_id, enable, times, result);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief phy dump
+ * @details   Comments:
+ *    The unit of packets size is byte.
+ * @param[in] dev_id device id, phy addr, phy reg group
+ * @param[out] reg value
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_phy_dump(a_uint32_t dev_id, a_uint32_t phy_addr,
+		a_uint32_t idx, fal_phy_dump_t * phy_dump)
+
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_phy_dump(dev_id, phy_addr, idx, phy_dump);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * fal_uniphy_reg_get - get value of specific register in uniphy module
+  * @reg_addr: address of the register
+  * @uniphy_index: index of uniphy
+  * @value: pointer to the memory storing the value.
+  * @value_len: length of the value.
+  *
+  * Get the value of a specific register field with related parameter
+  */
+sw_error_t
+fal_uniphy_reg_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr,
+		a_uint8_t value[], a_uint32_t value_len)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_uniphy_reg_get(dev_id, index, reg_addr, value, value_len);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * fal_uniphy_reg_set - set value of specific register in uniphy module
+  * @reg_addr: address of the register
+  * @uniphy_index: index of uniphy
+  * @value: pointer to the memory storing the value.
+  * @value_len: length of the value.
+  *
+  * Get the value of a specific register field with related parameter
+  */
+sw_error_t
+fal_uniphy_reg_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr,
+		a_uint8_t value[], a_uint32_t value_len)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_uniphy_reg_set(dev_id, index, reg_addr, value, value_len);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/fal/fal_rss_hash.c b/qca-ssdk/src/fal/fal_rss_hash.c
new file mode 100755
index 0000000..8b2eca8
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_rss_hash.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_rss_hash FAL_RSS_HASH
+ * @{
+ */
+#include "sw.h"
+#include "fal_rss_hash.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+
+/**
+ * @}
+ */
+sw_error_t
+_fal_rss_hash_config_set(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_rss_hash_config_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_rss_hash_config_set(dev_id, mode, config);
+    return rv;
+}
+
+sw_error_t
+_fal_rss_hash_config_get(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_rss_hash_config_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_rss_hash_config_get(dev_id, mode, config);
+    return rv;
+}
+
+sw_error_t
+fal_rss_hash_config_set(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_RSS_HASH_API_LOCK;
+    rv = _fal_rss_hash_config_set(dev_id, mode, config);
+    FAL_RSS_HASH_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_rss_hash_config_get(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_RSS_HASH_API_LOCK;
+    rv = _fal_rss_hash_config_get(dev_id, mode, config);
+    FAL_RSS_HASH_API_UNLOCK;
+    return rv;
+}
+
+EXPORT_SYMBOL(fal_rss_hash_config_set);
+EXPORT_SYMBOL(fal_rss_hash_config_get);
diff --git a/qca-ssdk/src/fal/fal_sec.c b/qca-ssdk/src/fal/fal_sec.c
new file mode 100755
index 0000000..32071e4
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_sec.c
@@ -0,0 +1,247 @@
+/*
+ * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_sec FAL_SEC
+ * @{
+ */
+#include "sw.h"
+#include "fal_sec.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+static sw_error_t
+_fal_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->sec_norm_item_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->sec_norm_item_set(dev_id, item, value);
+    return rv;
+}
+
+static sw_error_t
+_fal_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->sec_norm_item_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->sec_norm_item_get(dev_id, item, value);
+    return rv;
+}
+
+sw_error_t
+_fal_sec_l3_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sec_l3_excep_parser_ctrl_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sec_l3_excep_parser_ctrl_set(dev_id, ctrl);
+	return rv;
+}
+sw_error_t
+_fal_sec_l3_excep_ctrl_get(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sec_l3_excep_ctrl_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sec_l3_excep_ctrl_get(dev_id, excep_type, ctrl);
+	return rv;
+}
+sw_error_t
+_fal_sec_l3_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sec_l3_excep_parser_ctrl_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sec_l3_excep_parser_ctrl_get(dev_id, ctrl);
+	return rv;
+}
+sw_error_t
+_fal_sec_l4_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sec_l4_excep_parser_ctrl_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sec_l4_excep_parser_ctrl_set(dev_id, ctrl);
+	return rv;
+}
+sw_error_t
+_fal_sec_l3_excep_ctrl_set(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sec_l3_excep_ctrl_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sec_l3_excep_ctrl_set(dev_id, excep_type, ctrl);
+	return rv;
+}
+sw_error_t
+_fal_sec_l4_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sec_l4_excep_parser_ctrl_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sec_l4_excep_parser_ctrl_get(dev_id, ctrl);
+	return rv;
+}
+/*insert flag for inner fal, don't remove it*/
+
+/**
+ * @brief Set normalization particular item types value.
+ * @details   Comments:
+ *       This operation will set normalization item values on a particular device.
+ *       The prototye of value based on the item type.
+ * @param[in] dev_id device id
+ * @param[in] item normalizaton item type
+ * @param[in] value normalizaton item value
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_sec_norm_item_set(dev_id, item, value);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get normalization particular item types value.
+ * @details   Comments:
+ *       This operation will set normalization item values on a particular device.
+ *       The prototye of value based on the item type.
+ * @param[in] dev_id device id
+ * @param[in] item normalizaton item type
+ * @param[out] value normalizaton item value
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_sec_norm_item_get(dev_id, item, value);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_sec_l3_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sec_l3_excep_parser_ctrl_set(dev_id, ctrl);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_sec_l3_excep_ctrl_get(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sec_l3_excep_ctrl_get(dev_id, excep_type, ctrl);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_sec_l3_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sec_l3_excep_parser_ctrl_get(dev_id, ctrl);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_sec_l4_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sec_l4_excep_parser_ctrl_set(dev_id, ctrl);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_sec_l3_excep_ctrl_set(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sec_l3_excep_ctrl_set(dev_id, excep_type, ctrl);
+	FAL_API_UNLOCK;
+	return rv;
+}
+sw_error_t
+fal_sec_l4_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sec_l4_excep_parser_ctrl_get(dev_id, ctrl);
+	FAL_API_UNLOCK;
+	return rv;
+}
+/*insert flag for outter fal, don't remove it*/
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/fal/fal_servcode.c b/qca-ssdk/src/fal/fal_servcode.c
new file mode 100755
index 0000000..dda3deb
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_servcode.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_ctrlpkt FAL_SERVCODE
+ * @{
+ */
+#include "sw.h"
+#include "fal_servcode.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+
+/**
+ * @}
+ */
+sw_error_t
+_fal_servcode_config_set(a_uint32_t dev_id, a_uint32_t servcode_index,
+			fal_servcode_config_t *entry)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_servcode_config_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_servcode_config_set(dev_id, servcode_index, entry);
+    return rv;
+}
+
+sw_error_t
+_fal_servcode_config_get(a_uint32_t dev_id, a_uint32_t servcode_index,
+			fal_servcode_config_t *entry)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_servcode_config_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_servcode_config_get(dev_id, servcode_index, entry);
+    return rv;
+}
+
+sw_error_t
+_fal_servcode_loopcheck_en(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_servcode_loopcheck_en)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_servcode_loopcheck_en(dev_id, enable);
+    return rv;
+}
+
+sw_error_t
+_fal_servcode_loopcheck_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+    adpt_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_servcode_loopcheck_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_servcode_loopcheck_status_get(dev_id, enable);
+    return rv;
+}
+
+sw_error_t
+fal_servcode_config_set(a_uint32_t dev_id, a_uint32_t servcode_index,
+			fal_servcode_config_t *entry)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_SERVCODE_API_LOCK;
+    rv = _fal_servcode_config_set(dev_id, servcode_index, entry);
+    FAL_SERVCODE_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_servcode_config_get(a_uint32_t dev_id, a_uint32_t servcode_index,
+			fal_servcode_config_t *entry)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_SERVCODE_API_LOCK;
+    rv = _fal_servcode_config_get(dev_id, servcode_index, entry);
+    FAL_SERVCODE_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_servcode_loopcheck_en(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_SERVCODE_API_LOCK;
+    rv = _fal_servcode_loopcheck_en(dev_id, enable);
+    FAL_SERVCODE_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_servcode_loopcheck_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_SERVCODE_API_LOCK;
+    rv = _fal_servcode_loopcheck_status_get(dev_id, enable);
+    FAL_SERVCODE_API_UNLOCK;
+    return rv;
+}
+
+EXPORT_SYMBOL(fal_servcode_config_set);
+EXPORT_SYMBOL(fal_servcode_config_get);
+EXPORT_SYMBOL(fal_servcode_loopcheck_en);
+EXPORT_SYMBOL(fal_servcode_loopcheck_status_get);
diff --git a/qca-ssdk/src/fal/fal_sfp.c b/qca-ssdk/src/fal/fal_sfp.c
new file mode 100755
index 0000000..c3fe063
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_sfp.c
@@ -0,0 +1,508 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "fal_sfp.h"
+#include "adpt.h"
+#include "hsl_api.h"
+
+sw_error_t
+_fal_sfp_diag_ctrl_status_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_ctrl_status_t *ctrl_status)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_diag_ctrl_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_diag_ctrl_status_get(dev_id, port_id, ctrl_status);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_diag_extenal_calibration_const_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_cal_const_t *cal_const)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_diag_extenal_calibration_const_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_diag_extenal_calibration_const_get(dev_id, port_id, cal_const);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_link_length_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_link_length_t *link_len)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_link_length_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_link_length_get(dev_id, port_id, link_len);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_diag_internal_threshold_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_internal_threshold_t *threshold)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_diag_internal_threshold_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_diag_internal_threshold_get(dev_id, port_id, threshold);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_diag_realtime_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_realtime_diag_t *real_diag)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_diag_realtime_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_diag_realtime_get(dev_id, port_id, real_diag);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_laser_wavelength_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_laser_wavelength_t *laser_wavelen)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_laser_wavelength_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_laser_wavelength_get(dev_id, port_id, laser_wavelen);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_option_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_option_t *option)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_option_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_option_get(dev_id, port_id, option);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_checkcode_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_cc_type_t cc_type, a_uint8_t *ccode)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_checkcode_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_checkcode_get(dev_id, port_id, cc_type, ccode);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_diag_alarm_warning_flag_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_alarm_warn_flag_t *alarm_warn_flag)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_diag_alarm_warning_flag_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_diag_alarm_warning_flag_get(dev_id, port_id, alarm_warn_flag);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_device_type_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_dev_type_t *sfp_id)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_device_type_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_device_type_get(dev_id, port_id, sfp_id);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_vendor_info_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_vendor_info_t *vender_info)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_vendor_info_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_vendor_info_get(dev_id, port_id, vender_info);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_transceiver_code_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_transc_code_t *transc_code)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_transceiver_code_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_transceiver_code_get(dev_id, port_id, transc_code);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_ctrl_rate_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_rate_t *rate_limit)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_ctrl_rate_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_ctrl_rate_get(dev_id, port_id, rate_limit);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_enhanced_cfg_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_enhanced_cfg_t *enhanced_feature)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_enhanced_cfg_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_enhanced_cfg_get(dev_id, port_id, enhanced_feature);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_rate_encode_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_rate_encode_t *encode)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_rate_encode_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_rate_encode_get(dev_id, port_id, encode);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_eeprom_data_get(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_eeprom_data_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_eeprom_data_get(dev_id, port_id, entry);
+	return rv;
+}
+
+sw_error_t
+_fal_sfp_eeprom_data_set(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry)
+{
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+	if (NULL == p_api->adpt_sfp_eeprom_data_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_sfp_eeprom_data_set(dev_id, port_id, entry);
+	return rv;
+}
+
+sw_error_t
+fal_sfp_diag_ctrl_status_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_ctrl_status_t *ctrl_status)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_diag_ctrl_status_get(dev_id, port_id, ctrl_status);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_diag_extenal_calibration_const_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_cal_const_t *cal_const)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_diag_extenal_calibration_const_get(dev_id, port_id, cal_const);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_link_length_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_link_length_t *link_len)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_link_length_get(dev_id, port_id, link_len);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_diag_internal_threshold_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_internal_threshold_t *threshold)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_diag_internal_threshold_get(dev_id, port_id, threshold);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_diag_realtime_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_realtime_diag_t *real_diag)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_diag_realtime_get(dev_id, port_id, real_diag);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_laser_wavelength_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_laser_wavelength_t *laser_wavelen)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_laser_wavelength_get(dev_id, port_id, laser_wavelen);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_option_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_option_t *option)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_option_get(dev_id, port_id, option);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_checkcode_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_cc_type_t cc_type, a_uint8_t *ccode)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_checkcode_get(dev_id, port_id, cc_type, ccode);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_diag_alarm_warning_flag_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_alarm_warn_flag_t *alarm_warn_flag)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_diag_alarm_warning_flag_get(dev_id, port_id, alarm_warn_flag);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_device_type_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_dev_type_t *sfp_id)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_device_type_get(dev_id, port_id, sfp_id);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_vendor_info_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_vendor_info_t *vender_info)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_vendor_info_get(dev_id, port_id, vender_info);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_transceiver_code_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_transc_code_t *transc_code)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_transceiver_code_get(dev_id, port_id, transc_code);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_ctrl_rate_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_rate_t *rate_limit)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_ctrl_rate_get(dev_id, port_id, rate_limit);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_enhanced_cfg_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_enhanced_cfg_t *enhanced_feature)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_enhanced_cfg_get(dev_id, port_id, enhanced_feature);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_rate_encode_get(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_sfp_rate_encode_t *encode)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_rate_encode_get(dev_id, port_id, encode);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_eeprom_data_get(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_eeprom_data_get(dev_id, port_id, entry);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+fal_sfp_eeprom_data_set(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry)
+{
+	sw_error_t rv = SW_OK;
+
+	FAL_API_LOCK;
+	rv = _fal_sfp_eeprom_data_set(dev_id, port_id, entry);
+	FAL_API_UNLOCK;
+	return rv;
+}
+
+EXPORT_SYMBOL(fal_sfp_diag_ctrl_status_get);
+EXPORT_SYMBOL(fal_sfp_diag_extenal_calibration_const_get);
+EXPORT_SYMBOL(fal_sfp_link_length_get);
+EXPORT_SYMBOL(fal_sfp_diag_internal_threshold_get);
+EXPORT_SYMBOL(fal_sfp_diag_realtime_get);
+EXPORT_SYMBOL(fal_sfp_laser_wavelength_get);
+EXPORT_SYMBOL(fal_sfp_option_get);
+EXPORT_SYMBOL(fal_sfp_checkcode_get);
+EXPORT_SYMBOL(fal_sfp_diag_alarm_warning_flag_get);
+EXPORT_SYMBOL(fal_sfp_device_type_get);
+EXPORT_SYMBOL(fal_sfp_vendor_info_get);
+EXPORT_SYMBOL(fal_sfp_transceiver_code_get);
+EXPORT_SYMBOL(fal_sfp_ctrl_rate_get);
+EXPORT_SYMBOL(fal_sfp_enhanced_cfg_get);
+EXPORT_SYMBOL(fal_sfp_rate_encode_get);
+EXPORT_SYMBOL(fal_sfp_eeprom_data_get);
+EXPORT_SYMBOL(fal_sfp_eeprom_data_set);
diff --git a/qca-ssdk/src/fal/fal_shaper.c b/qca-ssdk/src/fal/fal_shaper.c
new file mode 100755
index 0000000..addb0f3
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_shaper.c
@@ -0,0 +1,601 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_shaper FAL_SHAPER
+ * @{
+ */
+#include "sw.h"
+#include "fal_shaper.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+sw_error_t
+_fal_flow_shaper_set(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_config_t * shaper)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_flow_shaper_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_flow_shaper_set(dev_id, flow_id, shaper);
+    return rv;
+}
+sw_error_t
+_fal_queue_shaper_get(a_uint32_t dev_id, a_uint32_t queue_id,
+		fal_shaper_config_t * shaper)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_queue_shaper_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_queue_shaper_get(dev_id, queue_id, shaper);
+    return rv;
+}
+sw_error_t
+_fal_queue_shaper_token_number_set(a_uint32_t dev_id,a_uint32_t queue_id,
+		fal_shaper_token_number_t *token_number)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_queue_shaper_token_number_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_queue_shaper_token_number_set(dev_id, queue_id, token_number);
+    return rv;
+}
+#ifndef IN_SHAPER_MINI
+sw_error_t
+_fal_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_config_t * shaper)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_shaper_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_shaper_get(dev_id, port_id, shaper);
+    return rv;
+}
+sw_error_t
+_fal_flow_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_flow_shaper_time_slot_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_flow_shaper_time_slot_get(dev_id, timeslot);
+    return rv;
+}
+sw_error_t
+_fal_port_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_shaper_time_slot_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_shaper_time_slot_get(dev_id, timeslot);
+    return rv;
+}
+#endif
+sw_error_t
+_fal_flow_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_flow_shaper_time_slot_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_flow_shaper_time_slot_set(dev_id, timeslot);
+    return rv;
+}
+sw_error_t
+_fal_port_shaper_token_number_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_token_number_t *token_number)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_shaper_token_number_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_shaper_token_number_set(dev_id, port_id, token_number);
+    return rv;
+}
+#ifndef IN_SHAPER_MINI
+sw_error_t
+_fal_queue_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t queue_id,
+		fal_shaper_token_number_t *token_number)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_queue_shaper_token_number_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_queue_shaper_token_number_get(dev_id, queue_id, token_number);
+    return rv;
+}
+sw_error_t
+_fal_queue_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_queue_shaper_time_slot_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_queue_shaper_time_slot_get(dev_id, timeslot);
+    return rv;
+}
+sw_error_t
+_fal_port_shaper_token_number_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_token_number_t *token_number)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_shaper_token_number_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_shaper_token_number_get(dev_id, port_id, token_number);
+    return rv;
+}
+#endif
+sw_error_t
+_fal_flow_shaper_token_number_set(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_token_number_t *token_number)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_flow_shaper_token_number_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_flow_shaper_token_number_set(dev_id, flow_id, token_number);
+    return rv;
+}
+#ifndef IN_SHAPER_MINI
+sw_error_t
+_fal_flow_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_token_number_t *token_number)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_flow_shaper_token_number_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_flow_shaper_token_number_get(dev_id, flow_id, token_number);
+    return rv;
+}
+#endif
+sw_error_t
+_fal_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_config_t * shaper)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_shaper_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_shaper_set(dev_id, port_id, shaper);
+    return rv;
+}
+sw_error_t
+_fal_port_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_shaper_time_slot_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_shaper_time_slot_set(dev_id, timeslot);
+    return rv;
+}
+#ifndef IN_SHAPER_MINI
+sw_error_t
+_fal_flow_shaper_get(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_config_t * shaper)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_flow_shaper_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_flow_shaper_get(dev_id, flow_id, shaper);
+    return rv;
+}
+#endif
+sw_error_t
+_fal_queue_shaper_set(a_uint32_t dev_id,a_uint32_t queue_id,
+		fal_shaper_config_t * shaper)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_queue_shaper_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_queue_shaper_set(dev_id, queue_id, shaper);
+    return rv;
+}
+sw_error_t
+_fal_queue_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_queue_shaper_time_slot_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_queue_shaper_time_slot_set(dev_id, timeslot);
+    return rv;
+}
+
+sw_error_t
+_fal_shaper_ipg_preamble_length_set(a_uint32_t dev_id, a_uint32_t ipg_pre_length)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_shaper_ipg_preamble_length_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_shaper_ipg_preamble_length_set(dev_id, ipg_pre_length);
+    return rv;
+}
+
+#ifndef IN_SHAPER_MINI
+sw_error_t
+_fal_shaper_ipg_preamble_length_get(a_uint32_t dev_id, a_uint32_t *ipg_pre_length)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_shaper_ipg_preamble_length_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_shaper_ipg_preamble_length_get(dev_id, ipg_pre_length);
+    return rv;
+}
+#endif
+
+/*insert flag for inner fal, don't remove it*/
+
+sw_error_t
+fal_flow_shaper_set(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_config_t * shaper)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_flow_shaper_set(dev_id, flow_id, shaper);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_queue_shaper_get(a_uint32_t dev_id, a_uint32_t queue_id,
+		fal_shaper_config_t * shaper)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_queue_shaper_get(dev_id, queue_id, shaper);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_queue_shaper_token_number_set(a_uint32_t dev_id,a_uint32_t queue_id,
+		fal_shaper_token_number_t *token_number)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_queue_shaper_token_number_set(dev_id, queue_id, token_number);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_SHAPER_MINI
+sw_error_t
+fal_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_config_t * shaper)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_shaper_get(dev_id, port_id, shaper);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_flow_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_flow_shaper_timeslot_get(dev_id, timeslot);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_shaper_timeslot_get(dev_id, timeslot);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+sw_error_t
+fal_flow_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_flow_shaper_timeslot_set(dev_id, timeslot);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_shaper_token_number_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_token_number_t *token_number)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_shaper_token_number_set(dev_id, port_id, token_number);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_SHAPER_MINI
+sw_error_t
+fal_queue_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t queue_id,
+		fal_shaper_token_number_t *token_number)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_queue_shaper_token_number_get(dev_id, queue_id, token_number);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_queue_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_queue_shaper_timeslot_get(dev_id, timeslot);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_shaper_token_number_get(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_token_number_t *token_number)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_shaper_token_number_get(dev_id, port_id, token_number);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+sw_error_t
+fal_flow_shaper_token_number_set(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_token_number_t *token_number)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_flow_shaper_token_number_set(dev_id, flow_id, token_number);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_SHAPER_MINI
+sw_error_t
+fal_flow_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_token_number_t *token_number)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_flow_shaper_token_number_get(dev_id, flow_id, token_number);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+sw_error_t
+fal_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+		fal_shaper_config_t * shaper)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_shaper_set(dev_id, port_id, shaper);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_shaper_timeslot_set(dev_id, timeslot);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_SHAPER_MINI
+sw_error_t
+fal_flow_shaper_get(a_uint32_t dev_id, a_uint32_t flow_id,
+		fal_shaper_config_t * shaper)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_flow_shaper_get(dev_id, flow_id, shaper);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+sw_error_t
+fal_queue_shaper_set(a_uint32_t dev_id,a_uint32_t queue_id,
+		fal_shaper_config_t * shaper)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_queue_shaper_set(dev_id, queue_id, shaper);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_queue_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_queue_shaper_timeslot_set(dev_id, timeslot);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_shaper_ipg_preamble_length_set(a_uint32_t dev_id, a_uint32_t ipg_pre_length)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_shaper_ipg_preamble_length_set(dev_id, ipg_pre_length);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_SHAPER_MINI
+sw_error_t
+fal_shaper_ipg_preamble_length_get(a_uint32_t dev_id, a_uint32_t *ipg_pre_length)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_shaper_ipg_preamble_length_get(dev_id, ipg_pre_length);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+EXPORT_SYMBOL(fal_flow_shaper_token_number_set);
+
+EXPORT_SYMBOL(fal_queue_shaper_token_number_set);
+
+EXPORT_SYMBOL(fal_port_shaper_token_number_set);
+
+EXPORT_SYMBOL(fal_port_shaper_timeslot_set);
+
+EXPORT_SYMBOL(fal_flow_shaper_timeslot_set);
+
+EXPORT_SYMBOL(fal_queue_shaper_timeslot_set);
+
+EXPORT_SYMBOL(fal_shaper_ipg_preamble_length_set);
+
+EXPORT_SYMBOL(fal_port_shaper_set);
+
+EXPORT_SYMBOL(fal_queue_shaper_get);
+
+EXPORT_SYMBOL(fal_queue_shaper_set);
+
+EXPORT_SYMBOL(fal_flow_shaper_set);
+
+#ifndef IN_SHAPER_MINI
+
+EXPORT_SYMBOL(fal_port_shaper_get);
+
+EXPORT_SYMBOL(fal_flow_shaper_get);
+
+EXPORT_SYMBOL(fal_queue_shaper_token_number_get);
+
+EXPORT_SYMBOL(fal_flow_shaper_token_number_get);
+
+EXPORT_SYMBOL(fal_port_shaper_token_number_get);
+
+EXPORT_SYMBOL(fal_port_shaper_timeslot_get);
+
+EXPORT_SYMBOL(fal_queue_shaper_timeslot_get);
+
+EXPORT_SYMBOL(fal_flow_shaper_timeslot_get);
+
+EXPORT_SYMBOL(fal_shaper_ipg_preamble_length_get);
+#endif
+
+/*insert flag for outter fal, don't remove it*/
diff --git a/qca-ssdk/src/fal/fal_stp.c b/qca-ssdk/src/fal/fal_stp.c
new file mode 100755
index 0000000..8821120
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_stp.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_stp FAL_STP
+ * @{
+ */
+#include "sw.h"
+#include "fal_stp.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+static sw_error_t
+_fal_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                        fal_port_t port_id, fal_stp_state_t state)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_stp_port_state_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_stp_port_state_set(dev_id, st_id, port_id, state);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->stp_port_state_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->stp_port_state_set(dev_id, st_id, port_id, state);
+    return rv;
+}
+
+static sw_error_t
+_fal_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                        fal_port_t port_id, fal_stp_state_t * state)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_stp_port_state_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_stp_port_state_get(dev_id, st_id, port_id, state);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->stp_port_state_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->stp_port_state_get(dev_id, st_id, port_id, state);
+    return rv;
+}
+
+/*insert flag for inner fal, don't remove it*/
+
+/**
+ * @brief Set port stp state on a particular spanning tree and port.
+ *   @details   Comments:
+ *    For those devices which only support single spanning tree st_id should
+ *    be FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[in] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                       fal_port_t port_id, fal_stp_state_t state)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_stp_port_state_set(dev_id, st_id, port_id, state);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port stp state on a particular spanning tree and port.
+ *   @details  Comments:
+ *    For those devices which only support single spanning tree st_id should
+ *    be FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[out] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                       fal_port_t port_id, fal_stp_state_t * state)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_stp_port_state_get(dev_id, st_id, port_id, state);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/*insert flag for outter fal, don't remove it*/
+
+EXPORT_SYMBOL(fal_stp_port_state_set);
+EXPORT_SYMBOL(fal_stp_port_state_get);
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/fal/fal_trunk.c b/qca-ssdk/src/fal/fal_trunk.c
new file mode 100755
index 0000000..b669096
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_trunk.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup fal_trunk FAL_TRUNK
+ * @{
+ */
+#include "sw.h"
+#include "fal_trunk.h"
+#include "hsl_api.h"
+#include "adpt.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+
+static sw_error_t
+_fal_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+                     a_bool_t enable, fal_pbmp_t member)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_trunk_group_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_trunk_group_set(dev_id, trunk_id, enable, member);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->trunk_group_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->trunk_group_set(dev_id, trunk_id, enable, member);
+    return rv;
+}
+
+static sw_error_t
+_fal_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+                     a_bool_t * enable, fal_pbmp_t * member)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_trunk_group_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_trunk_group_get(dev_id, trunk_id, enable, member);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->trunk_group_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->trunk_group_get(dev_id, trunk_id, enable, member);
+    return rv;
+}
+
+static sw_error_t
+_fal_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_trunk_hash_mode_set)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_trunk_hash_mode_set(dev_id, hash_mode);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->trunk_hash_mode_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->trunk_hash_mode_set(dev_id, hash_mode);
+    return rv;
+}
+
+static sw_error_t
+_fal_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+    adpt_api_t *p_adpt_api;
+
+    if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) {
+        if (NULL == p_adpt_api->adpt_trunk_hash_mode_get)
+            return SW_NOT_SUPPORTED;
+
+        rv = p_adpt_api->adpt_trunk_hash_mode_get(dev_id, hash_mode);
+        return rv;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->trunk_hash_mode_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->trunk_hash_mode_get(dev_id, hash_mode);
+    return rv;
+}
+
+static sw_error_t
+_fal_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->trunk_manipulate_sa_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->trunk_manipulate_sa_set(dev_id, addr);
+    return rv;
+}
+
+static sw_error_t
+_fal_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->trunk_manipulate_sa_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->trunk_manipulate_sa_get(dev_id, addr);
+    return rv;
+}
+sw_error_t
+_fal_trunk_failover_status_get(a_uint32_t dev_id, a_bool_t * failover)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_trunk_fail_over_en_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_trunk_fail_over_en_get(dev_id, failover);
+    return rv;
+}
+sw_error_t
+_fal_trunk_failover_enable(a_uint32_t dev_id, a_bool_t failover)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_trunk_fail_over_en_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_trunk_fail_over_en_set(dev_id, failover);
+    return rv;
+}
+
+/*insert flag for inner fal, don't remove it*/
+/**
+ * @brief Set particular trunk group information on particular device.
+ * @param[in] dev_id device id
+ * @param[in] trunk_id trunk group id
+ * @param[in] enable trunk group status, enable or disable
+ * @param[in] member port member information
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+                    a_bool_t enable, fal_pbmp_t member)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_trunk_group_set(dev_id, trunk_id, enable, member);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get particular trunk group information on particular device.
+ * @param[in] dev_id device id
+ * @param[in] trunk_id trunk group id
+ * @param[out] enable trunk group status, enable or disable
+ * @param[out] member port member information
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+                    a_bool_t * enable, fal_pbmp_t * member)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_trunk_group_get(dev_id, trunk_id, enable, member);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set trunk hash mode on particular device.
+ * @param[in] dev_id device id
+ * @param[in] hash_mode trunk hash mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_trunk_hash_mode_set(dev_id, hash_mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get trunk hash mode on particular device.
+ * @param[in] dev_id device id
+ * @param[out] hash_mode trunk hash mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_trunk_hash_mode_get(dev_id, hash_mode);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set trunk manipulate SA on particular device.
+ * @param[in] dev_id device id
+ * @param[in] addr   manipulate SA
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_trunk_manipulate_sa_set(dev_id, addr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get trunk manipulate SA on particular device.
+ * @param[in]  dev_id device id
+ * @param[out] addr   manipulate SA
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_trunk_manipulate_sa_get(dev_id, addr);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_trunk_failover_status_get(a_uint32_t dev_id, a_bool_t * failover)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_trunk_failover_status_get(dev_id, failover);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_trunk_failover_enable(a_uint32_t dev_id, a_bool_t failover)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_trunk_failover_enable(dev_id, failover);
+    FAL_API_UNLOCK;
+    return rv;
+}
+/*insert flag for outter fal, don't remove it*/
+
+EXPORT_SYMBOL(fal_trunk_group_set);
+EXPORT_SYMBOL(fal_trunk_group_get);
+EXPORT_SYMBOL(fal_trunk_hash_mode_set);
+EXPORT_SYMBOL(fal_trunk_hash_mode_get);
+EXPORT_SYMBOL(fal_trunk_failover_status_get);
+EXPORT_SYMBOL(fal_trunk_failover_enable);
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/fal/fal_vlan.c b/qca-ssdk/src/fal/fal_vlan.c
new file mode 100755
index 0000000..b5c37fb
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_vlan.c
@@ -0,0 +1,933 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+ * @defgroup fal_vlan FAL_VLAN
+ * @{
+ */
+
+#include "sw.h"
+#include "util.h"
+#include "fal_vlan.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_api.h"
+
+typedef struct
+{
+    a_uint32_t   idx;
+    fal_vlan_t   entry;
+} v_array_t;
+
+static v_array_t  * vlan_db[SW_MAX_NR_DEV] = { 0 };
+static sid_pool_t * vlan_pool[SW_MAX_NR_DEV]  = { 0 };
+static sll_head_t * vlan_list[SW_MAX_NR_DEV] = { 0 };
+
+
+static sw_error_t
+_fal_vlan_search(a_uint32_t dev_id, fal_vlan_t * vlan_entry)
+{
+    a_ulong_t iterator;
+    v_array_t   v_tbl;
+    v_array_t * p_tbl;
+    hsl_dev_t * p_dev = NULL;
+
+    p_dev = hsl_dev_ptr_get(dev_id);
+    SW_RTN_ON_NULL(p_dev);
+
+    if (A_TRUE == p_dev->hw_vlan_query)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    v_tbl.entry = * vlan_entry;
+    p_tbl = sll_nd_find(vlan_list[dev_id], &v_tbl, &iterator);
+
+    if (NULL == p_tbl)
+    {
+        return SW_NOT_FOUND;
+    }
+    else
+    {
+        * vlan_entry = p_tbl->entry;
+        return SW_OK;
+    }
+}
+
+static sw_error_t
+_fal_vlan_following(a_uint32_t dev_id, fal_vlan_t * vlan_entry)
+{
+    a_ulong_t iterator = 0;
+    v_array_t   v_tbl;
+    v_array_t * p_tbl;
+    hsl_dev_t * p_dev = NULL;
+
+    p_dev = hsl_dev_ptr_get(dev_id);
+    SW_RTN_ON_NULL(p_dev);
+
+    if (A_TRUE == p_dev->hw_vlan_query)
+    {
+        return SW_OK;
+    }
+
+    sll_lock(vlan_list[dev_id]);
+
+    v_tbl.entry = *vlan_entry;
+
+    if (0 == v_tbl.entry.vid)
+    {
+        p_tbl = sll_nd_next(vlan_list[dev_id], &iterator);
+    }
+    else
+    {
+        p_tbl = sll_nd_find(vlan_list[dev_id], &v_tbl, &iterator);
+        if (NULL == p_tbl)
+        {
+            sll_unlock(vlan_list[dev_id]);
+            return SW_NO_MORE;
+        }
+
+        p_tbl = sll_nd_next(vlan_list[dev_id], &iterator);
+    }
+
+    if (NULL == p_tbl)
+    {
+        sll_unlock(vlan_list[dev_id]);
+        return SW_NO_MORE;
+    }
+
+    * vlan_entry = p_tbl->entry;
+    sll_unlock(vlan_list[dev_id]);
+    return SW_OK;
+}
+
+static sw_error_t
+_fal_vlan_del(a_uint32_t dev_id, a_uint16_t vlan_id)
+{
+    v_array_t * p_tbl;
+    v_array_t   ent;
+    sw_error_t  rv;
+    a_ulong_t iterator;
+    a_uint32_t  id;
+    hsl_dev_t * p_dev = NULL;
+
+    p_dev = hsl_dev_ptr_get(dev_id);
+    SW_RTN_ON_NULL(p_dev);
+
+    if (A_TRUE == p_dev->hw_vlan_query)
+    {
+        return SW_OK;
+    }
+
+    ent.entry.vid = vlan_id;
+    p_tbl = sll_nd_find(vlan_list[dev_id], &ent, &iterator);
+    if (NULL == p_tbl)
+    {
+        return SW_NOT_FOUND;
+    }
+    id = p_tbl->idx;
+
+    rv = sll_nd_delete(vlan_list[dev_id], p_tbl);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = sid_pool_id_free(vlan_pool[dev_id], id);
+    return rv;
+}
+
+static sw_error_t
+_fal_vlan_creat(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    v_array_t * v_tbl;
+    sw_error_t  rv;
+    a_uint32_t  id;
+    hsl_dev_t * p_dev = NULL;
+
+    p_dev = hsl_dev_ptr_get(dev_id);
+    SW_RTN_ON_NULL(p_dev);
+
+    if (A_TRUE == p_dev->hw_vlan_query)
+    {
+        return SW_OK;
+    }
+
+    rv = sid_pool_id_alloc(vlan_pool[dev_id], &id);
+    SW_RTN_ON_ERROR(rv);
+
+    v_tbl = &vlan_db[dev_id][id];
+    v_tbl->idx   = id;
+    v_tbl->entry = *vlan_entry;
+    rv = sll_nd_insert(vlan_list[dev_id], v_tbl);
+    return rv;
+}
+
+static sw_error_t
+_fal_vlan_update(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    a_ulong_t iterator;
+    v_array_t   v_tbl;
+    v_array_t * p_tbl;
+    hsl_dev_t * p_dev = NULL;
+
+    p_dev = hsl_dev_ptr_get(dev_id);
+    SW_RTN_ON_NULL(p_dev);
+
+    if (A_TRUE == p_dev->hw_vlan_query)
+    {
+        return SW_OK;
+    }
+
+    sll_lock(vlan_list[dev_id]);
+    v_tbl.entry = *vlan_entry;
+    p_tbl = sll_nd_find(vlan_list[dev_id], &v_tbl, &iterator);
+
+    if (NULL == p_tbl)
+    {
+        sll_unlock(vlan_list[dev_id]);
+        return SW_NOT_FOUND;
+    }
+
+    p_tbl->entry = * vlan_entry;
+    sll_unlock(vlan_list[dev_id]);
+    return SW_OK;
+}
+
+static ll_cmp_rslt_t
+_fal_vlan_entry_cmp(void * src, void * dest)
+{
+    v_array_t * src_nd, * dest_nd;
+
+    src_nd  = (v_array_t*)src;
+    dest_nd = (v_array_t*)dest;
+
+    if (src_nd->entry.vid == dest_nd->entry.vid)
+    {
+        return LL_CMP_EQUAL;
+    }
+    else if (src_nd->entry.vid > dest_nd->entry.vid)
+    {
+        return LL_CMP_GREATER;
+    }
+    else
+    {
+        return LL_CMP_SMALLER;
+    }
+}
+
+static void
+_fal_vlan_entry_dump(void * data)
+{
+    v_array_t * nd;
+
+    nd  = (v_array_t*)data;
+    aos_printk("vid = %d  member = 0x%x\n", nd->entry.vid, nd->entry.mem_ports);
+}
+
+
+static sw_error_t
+_fal_vlan_entry_append(a_uint32_t dev_id, fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    rv = _fal_vlan_search(dev_id, vlan_entry);
+    if (SW_OK == rv)
+    {
+        return SW_ALREADY_EXIST;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+    if (NULL == p_api->vlan_entry_append)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->vlan_entry_append(dev_id, vlan_entry);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _fal_vlan_creat(dev_id, vlan_entry);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+    fal_vlan_t entry;
+    hsl_api_t *p_api;
+
+    aos_mem_zero(&(entry), sizeof(fal_vlan_t));
+    entry.vid = vlan_id;
+    rv = _fal_vlan_search(dev_id, &entry);
+    if (SW_OK == rv)
+    {
+        return SW_ALREADY_EXIST;
+    }
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+    if (NULL == p_api->vlan_creat)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->vlan_creat(dev_id, vlan_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _fal_vlan_creat(dev_id, &entry);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->vlan_next)
+    {
+        p_vlan->vid = vlan_id;
+        rv = _fal_vlan_following(dev_id, p_vlan);
+    }
+    else
+    {
+        rv = p_api->vlan_next(dev_id, vlan_id, p_vlan);
+    }
+    return rv;
+}
+
+
+static sw_error_t
+_fal_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->vlan_find)
+    {
+        p_vlan->vid = vlan_id;
+        rv = _fal_vlan_search(dev_id, p_vlan);
+    }
+    else
+    {
+        rv = p_api->vlan_find(dev_id, vlan_id, p_vlan);
+    }
+    return rv;
+}
+
+
+static sw_error_t
+_fal_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                        fal_pbmp_t member, fal_pbmp_t u_member)
+{
+    sw_error_t rv;
+    fal_vlan_t vlan_entry = {0};
+    hsl_api_t *p_api;
+    hsl_dev_t *p_dev = NULL;
+
+    p_dev = hsl_dev_ptr_get(dev_id);
+    SW_RTN_ON_NULL(p_dev);
+
+    if (A_FALSE == p_dev->hw_vlan_query)
+    {
+        vlan_entry.vid = vlan_id;
+        rv = _fal_vlan_search(dev_id, &vlan_entry);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    vlan_entry.mem_ports = member;
+    vlan_entry.u_ports   = u_member;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+    if (NULL == p_api->vlan_member_update)
+    {
+        if ((NULL == p_api->vlan_entry_append)
+                || (NULL == p_api->vlan_delete))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        p_api->vlan_delete(dev_id, vlan_id);
+
+	vlan_entry.vid = vlan_id;
+	vlan_entry.fid = vlan_id;
+
+	vlan_entry.untagged_ports = u_member;
+	vlan_entry.tagged_ports = member & ~u_member;
+
+        rv = p_api->vlan_entry_append(dev_id, &vlan_entry);
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+
+        rv = p_api->vlan_member_update(dev_id, vlan_id, member, u_member);
+        SW_RTN_ON_ERROR(rv);
+    }
+    rv = _fal_vlan_update(dev_id, &vlan_entry);
+    return rv;
+}
+
+
+static sw_error_t
+_fal_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->vlan_delete)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->vlan_delete(dev_id, vlan_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _fal_vlan_del(dev_id, vlan_id);
+    return rv;
+}
+
+static sw_error_t
+_fal_vlan_flush(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->vlan_flush)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->vlan_flush(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = fal_vlan_reset(dev_id);
+    return rv;
+}
+
+/**
+ * @brief Set FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] fid FDB id
+ * @return SW_OK or error code
+ */
+static sw_error_t
+_fal_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->vlan_fid_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->vlan_fid_set(dev_id, vlan_id, fid);
+    return rv;
+}
+
+/**
+ * @brief Get FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] fid FDB id
+ * @return SW_OK or error code
+ */
+static sw_error_t
+_fal_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->vlan_fid_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->vlan_fid_get(dev_id, vlan_id, fid);
+    return rv;
+}
+
+/**
+ * @brief Add a port member to a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @param[in] port_info port tag information
+ * @return SW_OK or error code
+ */
+static sw_error_t
+_fal_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+                     fal_port_t port_id, fal_pt_1q_egmode_t port_info)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->vlan_member_add)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->vlan_member_add(dev_id, vlan_id, port_id, port_info);
+    return rv;
+}
+
+/**
+ * @brief Del a port member from a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+static sw_error_t
+_fal_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->vlan_member_del)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->vlan_member_del(dev_id, vlan_id, port_id);
+    return rv;
+}
+
+/**
+ * @brief Set FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+static sw_error_t
+_fal_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->vlan_learning_state_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->vlan_learning_state_set(dev_id, vlan_id, enable);
+    return rv;
+}
+
+/**
+ * @brief Get FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+static sw_error_t
+_fal_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    if (NULL == p_api->vlan_learning_state_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->vlan_learning_state_get(dev_id, vlan_id, enable);
+    return rv;
+}
+
+/**
+ * @brief Reset fal vlan module on a paticular device.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_reset(a_uint32_t dev_id)
+{
+    a_uint32_t entry_nr;
+    hsl_dev_t *p_dev = NULL;
+
+    p_dev = hsl_dev_ptr_get(dev_id);
+    SW_RTN_ON_NULL(p_dev);
+
+    if (A_TRUE == p_dev->hw_vlan_query)
+    {
+        return SW_OK;
+    }
+
+    entry_nr = p_dev->nr_vlans;
+    if ((0 == entry_nr) || (4096 < entry_nr))
+    {
+        return SW_FAIL;
+    }
+
+    if (NULL != vlan_pool[dev_id])
+    {
+        sid_pool_destroy(vlan_pool[dev_id]);
+        vlan_pool[dev_id] = NULL;
+    }
+
+    if (NULL != vlan_list[dev_id])
+    {
+        sll_destroy(vlan_list[dev_id]);
+        vlan_list[dev_id] = NULL;
+    }
+
+    aos_mem_zero(vlan_db[dev_id], entry_nr * (sizeof (v_array_t)));
+
+    vlan_pool[dev_id] = sid_pool_creat(entry_nr, 0);
+    if (NULL == vlan_pool[dev_id])
+    {
+        return SW_FAIL;
+    }
+
+    vlan_list[dev_id] = sll_creat(_fal_vlan_entry_cmp, _fal_vlan_entry_dump,
+                                  LL_FIX_NDNR | LL_IN_ORDER, entry_nr);
+    if (NULL == vlan_list[dev_id])
+    {
+        return SW_FAIL;
+    }
+
+    return SW_OK;
+}
+
+
+/**
+ * @brief Init fal vlan module on a paticular device.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_init(a_uint32_t dev_id)
+{
+    a_uint32_t entry_nr;
+    hsl_dev_t *p_dev = NULL;
+
+    p_dev = hsl_dev_ptr_get(dev_id);
+    SW_RTN_ON_NULL(p_dev);
+
+    if (A_TRUE == p_dev->hw_vlan_query)
+    {
+        return SW_OK;
+    }
+
+    entry_nr = p_dev->nr_vlans;
+    if ((0 == entry_nr) || (4096 < entry_nr))
+    {
+        return SW_FAIL;
+    }
+
+    vlan_pool[dev_id] = sid_pool_creat(entry_nr, 0);
+    if (NULL == vlan_pool[dev_id])
+    {
+        return SW_FAIL;
+    }
+
+    /* allocate memory for vlan entry */
+    vlan_db[dev_id] = aos_mem_alloc(entry_nr * (sizeof (v_array_t)));
+    if (NULL == vlan_db[dev_id])
+    {
+        return SW_OUT_OF_MEM;
+    }
+    aos_mem_zero(vlan_db[dev_id], entry_nr * (sizeof (v_array_t)));
+
+    vlan_list[dev_id] = sll_creat(_fal_vlan_entry_cmp, _fal_vlan_entry_dump,
+                                  LL_FIX_NDNR | LL_IN_ORDER, entry_nr);
+
+    if (NULL == vlan_list[dev_id])
+    {
+        return SW_FAIL;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+fal_vlan_cleanup(void)
+{
+    a_uint32_t dev_id;
+
+    for (dev_id = 0; dev_id < SW_MAX_NR_DEV; dev_id++)
+    {
+        if (vlan_db[dev_id])
+        {
+            aos_mem_free(vlan_db[dev_id]);
+            vlan_db[dev_id] = NULL;
+        }
+
+        if (vlan_pool[dev_id])
+        {
+            sid_pool_destroy(vlan_pool[dev_id]);
+            vlan_pool[dev_id] = NULL;
+        }
+
+        if (vlan_list[dev_id])
+        {
+            sll_destroy(vlan_list[dev_id]);
+            vlan_list[dev_id] = NULL;
+        }
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Append a vlan entry on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_entry vlan entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_entry_append(a_uint32_t dev_id, fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_vlan_entry_append(dev_id, vlan_entry);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Creat a vlan entry through vlan id on a paticular device.
+ *   @details   Comments:
+ *    After this operation the member ports of the created vlan entry are null.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_vlan_create(dev_id, vlan_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next a vlan entry through vlan id on a paticular device.
+ *   @details   Comments:
+ *    If the value of vid is zero this operation will get the first entry.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_vlan_next(dev_id, vlan_id, p_vlan);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a vlan entry through vlan id on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_vlan_find(dev_id, vlan_id, p_vlan);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Update a vlan entry member port through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] member member ports
+ * @param[in] u_member tagged or untagged infomation for member ports
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                       fal_pbmp_t member, fal_pbmp_t u_member)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_vlan_member_update(dev_id, vlan_id, member, u_member);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a vlan entry through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_vlan_delete(dev_id, vlan_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Flush all vlan entries on a paticular device.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_flush(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_vlan_flush(dev_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] fid FDB id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_vlan_fid_set(dev_id, vlan_id, fid);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] fid FDB id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_vlan_fid_get(dev_id, vlan_id, fid);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a port member to a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @param[in] port_info port tag information
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+                    fal_port_t port_id, fal_pt_1q_egmode_t port_info)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_vlan_member_add(dev_id, vlan_id, port_id, port_info);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Del a port member from a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_vlan_member_del(dev_id, vlan_id, port_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_vlan_learning_state_set(dev_id, vlan_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _fal_vlan_learning_state_get(dev_id, vlan_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/fal/fal_vsi.c b/qca-ssdk/src/fal/fal_vsi.c
new file mode 100755
index 0000000..a40acd5
--- /dev/null
+++ b/qca-ssdk/src/fal/fal_vsi.c
@@ -0,0 +1,343 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "fal_vsi.h"
+#include "adpt.h"
+#include "hsl_api.h"
+
+sw_error_t
+_fal_port_vlan_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vlan_vsi_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vlan_vsi_set(dev_id, port_id, stag_vid, ctag_vid, vsi_id);
+    return rv;
+}
+sw_error_t
+_fal_port_vlan_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t *vsi_id)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vlan_vsi_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vlan_vsi_get(dev_id, port_id, stag_vid, ctag_vid, vsi_id);
+    return rv;
+}
+
+sw_error_t
+_fal_port_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vsi_id)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vsi_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vsi_set(dev_id, port_id, vsi_id);
+    return rv;
+}
+#ifndef IN_VSI_MINI
+sw_error_t
+_fal_port_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vsi_id)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_port_vsi_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_port_vsi_get(dev_id, port_id, vsi_id);
+    return rv;
+}
+#endif
+sw_error_t
+_fal_vsi_stamove_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_vsi_stamove_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_vsi_stamove_set(dev_id, vsi_id, stamove);
+    return rv;
+}
+#ifndef IN_VSI_MINI
+sw_error_t
+_fal_vsi_stamove_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_vsi_stamove_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_vsi_stamove_get(dev_id, vsi_id, stamove);
+    return rv;
+}
+sw_error_t
+_fal_vsi_newaddr_lrn_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_vsi_newaddr_lrn_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_vsi_newaddr_lrn_get(dev_id, vsi_id, newaddr_lrn);
+    return rv;
+}
+#endif
+sw_error_t
+_fal_vsi_newaddr_lrn_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_vsi_newaddr_lrn_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_vsi_newaddr_lrn_set(dev_id, vsi_id, newaddr_lrn);
+    return rv;
+}
+sw_error_t
+_fal_vsi_member_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_vsi_member_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_vsi_member_set(dev_id, vsi_id, vsi_member);
+    return rv;
+}
+sw_error_t
+_fal_vsi_member_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_vsi_member_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_vsi_member_get(dev_id, vsi_id, vsi_member);
+    return rv;
+}
+
+#ifndef IN_VSI_MINI
+sw_error_t
+_fal_vsi_counter_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_counter_t *counter)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_vsi_counter_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_vsi_counter_get(dev_id, vsi_id, counter);
+    return rv;
+}
+
+sw_error_t
+_fal_vsi_counter_cleanup(a_uint32_t dev_id, a_uint32_t vsi_id)
+{
+    adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+    SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+
+    if (NULL == p_api->adpt_vsi_counter_cleanup)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->adpt_vsi_counter_cleanup(dev_id, vsi_id);
+    return rv;
+}
+#endif
+
+/*insert flag for inner fal, don't remove it*/
+
+sw_error_t
+fal_port_vlan_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_vlan_vsi_set(dev_id, port_id, stag_vid, ctag_vid, vsi_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_vlan_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t *vsi_id)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_vlan_vsi_get(dev_id, port_id, stag_vid, ctag_vid, vsi_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_port_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vsi_id)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_vsi_set(dev_id, port_id, vsi_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_VSI_MINI
+sw_error_t
+fal_port_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vsi_id)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_port_vsi_get(dev_id, port_id, vsi_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+sw_error_t
+fal_vsi_stamove_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_vsi_stamove_set(dev_id, vsi_id, stamove);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_VSI_MINI
+sw_error_t
+fal_vsi_stamove_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_vsi_stamove_get(dev_id, vsi_id, stamove);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_vsi_newaddr_lrn_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_vsi_newaddr_lrn_get(dev_id, vsi_id, newaddr_lrn);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+sw_error_t
+fal_vsi_newaddr_lrn_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_vsi_newaddr_lrn_set(dev_id, vsi_id, newaddr_lrn);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+fal_vsi_member_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_vsi_member_set(dev_id, vsi_id, vsi_member);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_vsi_member_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_vsi_member_get(dev_id, vsi_id, vsi_member);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_VSI_MINI
+sw_error_t
+fal_vsi_counter_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_counter_t *counter)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_vsi_counter_get(dev_id, vsi_id, counter);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+fal_vsi_counter_cleanup(a_uint32_t dev_id, a_uint32_t vsi_id)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _fal_vsi_counter_cleanup(dev_id, vsi_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+/*insert flag for outter fal, don't remove it*/
+
+#ifndef IN_VSI_MINI
+EXPORT_SYMBOL(fal_port_vsi_get);
+EXPORT_SYMBOL(fal_vsi_stamove_get);
+EXPORT_SYMBOL(fal_vsi_newaddr_lrn_get);
+EXPORT_SYMBOL(fal_vsi_counter_get);
+EXPORT_SYMBOL(fal_vsi_counter_cleanup);
+#endif
+EXPORT_SYMBOL(fal_port_vlan_vsi_set);
+EXPORT_SYMBOL(fal_port_vlan_vsi_get);
+EXPORT_SYMBOL(fal_port_vsi_set);
+EXPORT_SYMBOL(fal_vsi_stamove_set);
+EXPORT_SYMBOL(fal_vsi_newaddr_lrn_set);
+EXPORT_SYMBOL(fal_vsi_member_set);
+EXPORT_SYMBOL(fal_vsi_member_get);
diff --git a/qca-ssdk/src/hsl/Makefile b/qca-ssdk/src/hsl/Makefile
new file mode 100755
index 0000000..8fabf4c
--- /dev/null
+++ b/qca-ssdk/src/hsl/Makefile
@@ -0,0 +1,39 @@
+LOC_DIR=/src/hsl
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=hsl_dev.c hsl_port_prop.c hsl_api.c
+
+ifeq (TRUE, $(IN_ACL))
+	ifeq (SHIVA, $(CHIP_TYPE))
+		SRC_LIST += hsl_acl.c
+	endif
+	ifeq (GARUDA, $(CHIP_TYPE))
+		SRC_LIST += hsl_acl.c
+	endif
+	ifeq (ALL_CHIP, $(CHIP_TYPE))
+		SRC_LIST += hsl_acl.c
+	endif
+	ifeq (NONHK_CHIP, $(CHIP_TYPE))
+                SRC_LIST += hsl_acl.c
+        endif
+endif
+
+ifeq (linux, $(OS))
+	ifeq (KSLIB, $(MODULE_TYPE))
+    ifneq (TRUE, $(KERNEL_MODE))
+      SRC_LIST=hsl_dev.c hsl_api.c
+	  endif
+	endif
+endif
+
+ifeq (TRUE, $(API_LOCK))
+  SRC_LIST += hsl_lock.c
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/hsl/athena/Makefile b/qca-ssdk/src/hsl/athena/Makefile
new file mode 100755
index 0000000..7cce5d2
--- /dev/null
+++ b/qca-ssdk/src/hsl/athena/Makefile
@@ -0,0 +1,44 @@
+LOC_DIR=src/hsl/athena
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=athena_reg_access.c athena_init.c
+
+ifeq (TRUE, $(IN_FDB))
+  SRC_LIST += athena_fdb.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+  SRC_LIST += athena_mib.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+  SRC_LIST += athena_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+  SRC_LIST += athena_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+  SRC_LIST += athena_vlan.c
+endif
+
+ifeq (linux, $(OS))
+	ifeq (KSLIB, $(MODULE_TYPE))
+    ifneq (TRUE, $(KERNEL_MODE))
+      SRC_LIST=athena_reg_access.c athena_init.c
+	  endif
+	endif
+endif
+
+ifeq (, $(findstring ATHENA, $(SUPPORT_CHIP)))
+  SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/qca-ssdk/src/hsl/athena/athena_fdb.c b/qca-ssdk/src/hsl/athena/athena_fdb.c
new file mode 100755
index 0000000..5b0fc52
--- /dev/null
+++ b/qca-ssdk/src/hsl/athena/athena_fdb.c
@@ -0,0 +1,639 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup athena_fdb ATHENA_FDB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "athena_fdb.h"
+#include "athena_reg.h"
+
+#define ARL_FLUSH_ALL             1
+#define ARL_LOAD_ENTRY            2
+#define ARL_PURGE_ENTRY           3
+#define ARL_FLUSH_ALL_UNLOCK      4
+#define ARL_FLUSH_PORT_UNICAST    5
+#define ARL_NEXT_ENTRY            6
+
+#define ARL_FIRST_ENTRY           1001
+
+static a_bool_t
+athena_fdb_is_zeroaddr(fal_mac_addr_t addr)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 6; i++)
+    {
+        if (addr.uc[i])
+        {
+            return A_FALSE;
+        }
+    }
+
+    return A_TRUE;
+}
+
+static void
+athena_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1)
+{
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE2, addr.uc[2], *reg1);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE3, addr.uc[3], *reg1);
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0);
+
+    return;
+}
+
+static sw_error_t
+athena_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry,
+                    a_uint32_t reg[])
+{
+    a_uint32_t port;
+
+    if (A_FALSE == entry->portmap_en)
+    {
+        if (A_TRUE !=
+                hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+
+        port = 0x1UL << entry->port.id;
+    }
+    else
+    {
+        if (A_FALSE ==
+                hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+
+        port = entry->port.map;
+    }
+
+    if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]);
+    }
+    else if (FAL_MAC_FRWRD != entry->dacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_MAC_DROP == entry->sacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, SA_DROP_EN, 1, reg[2]);
+    }
+    else if (FAL_MAC_FRWRD != entry->sacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->leaky_en)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->static_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 1, reg[2]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 2, reg[2]);
+    }
+
+    if (A_TRUE == entry->mirror_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, MIRROR_EN, 1, reg[2]);
+    }
+
+    if (A_TRUE == entry->da_pri_en)
+    {
+        hsl_dev_t *p_dev;
+
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI_EN, 1, reg[2]);
+
+        SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+
+        if (entry->da_queue > (p_dev->nr_queue - 1))
+            return SW_BAD_PARAM;
+
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI, entry->da_queue, reg[2]);
+    }
+
+    if (A_TRUE == entry->cross_pt_state)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, DES_PORT, port, reg[2]);
+    athena_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+
+    return SW_OK;
+}
+
+static void
+athena_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+    a_uint32_t i, data;
+
+    aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+    entry->dacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_CPY_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    entry->sacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, SA_DROP_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->sacmd = FAL_MAC_DROP;
+    }
+
+    entry->static_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]);
+    if (1 == data)
+    {
+        entry->static_en = A_TRUE;
+    }
+
+    entry->mirror_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, MIRROR_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+
+    entry->da_pri_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI_EN, data, reg[2]);
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI, data, reg[2]);
+        entry->da_pri_en = A_TRUE;
+        entry->da_queue = data & 0x3;
+    }
+
+    entry->cross_pt_state = A_FALSE;
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, DES_PORT, data, reg[2]);
+
+    entry->portmap_en = A_TRUE;
+    entry->port.map = data;
+
+    for (i = 0; i < 4; i++)
+    {
+        entry->addr.uc[i] = (reg[1] >> ((3 - i) << 3)) & 0xff;
+    }
+
+    for (i = 4; i < 6; i++)
+    {
+        entry->addr.uc[i] = (reg[0] >> ((7 - i) << 3)) & 0xff;
+    }
+
+    return;
+}
+
+static sw_error_t
+athena_fdb_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    sw_error_t rv;
+    a_uint32_t busy = 1;
+    a_uint32_t full_vio;
+    a_uint32_t i = 1000;
+    a_uint32_t entry;
+
+    while (busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+                          (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_BUSY;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_BUSY, 1, entry);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_FUNC, op, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    busy = 1;
+    i = 1000;
+    while (busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+                          (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_FAIL;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_FULL_VIO,
+                      (a_uint8_t *) (&full_vio), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (full_vio)
+    {
+        if (ARL_LOAD_ENTRY == op)
+        {
+            return SW_FULL;
+        }
+        else if ((ARL_PURGE_ENTRY == op)
+                 || (ARL_FLUSH_PORT_UNICAST == op))
+        {
+            return SW_NOT_FOUND;
+        }
+        else
+        {
+            return SW_FAIL;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+athena_atu_get(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op)
+{
+    sw_error_t rv;
+    a_uint32_t reg[3] = { 0 };
+    a_uint32_t destport = 0;
+    a_uint32_t hwop = op;
+
+    if (ARL_NEXT_ENTRY == op)
+    {
+        athena_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* set destport not zero */
+    if (ARL_NEXT_ENTRY == op)
+    {
+        reg[2] = 0xf;
+    }
+
+    if (ARL_FIRST_ENTRY == op)
+    {
+        hwop = ARL_NEXT_ENTRY;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = athena_fdb_commit(dev_id, hwop);
+    SW_RTN_ON_ERROR(rv);
+
+    /* get hardware enrety */
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, DES_PORT, destport, reg[2]);
+
+    athena_atu_hw_to_sw(reg, entry);
+
+    /* If hardware return back with address and status all zero,
+       that means no other next valid entry in fdb table */
+    if ((A_TRUE == athena_fdb_is_zeroaddr(entry->addr))
+            && (0 == destport)
+            && (ARL_NEXT_ENTRY == hwop))
+    {
+        return SW_NO_MORE;
+    }
+    else
+    {
+        return SW_OK;
+    }
+}
+
+static sw_error_t
+_athena_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[3] = { 0, 0, 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((A_TRUE == athena_fdb_is_zeroaddr(entry->addr))
+            && (0 == entry->port.map)
+            && (0 == entry->port.id))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = athena_atu_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (&reg[1]),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&reg[0]),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = athena_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_athena_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        rv = athena_fdb_commit(dev_id, ARL_FLUSH_ALL);
+    }
+    else
+    {
+        rv = athena_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_athena_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_PORT_NUM, port_id, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        rv = athena_fdb_commit(dev_id, ARL_FLUSH_PORT_UNICAST);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_athena_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg0 = 0, reg1 = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    athena_fdb_fill_addr(entry->addr, &reg0, &reg1);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (&reg1),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&reg0),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = athena_fdb_commit(dev_id, ARL_PURGE_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_athena_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = athena_atu_get(dev_id, entry, ARL_FIRST_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_athena_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = athena_atu_get(dev_id, entry, ARL_NEXT_ENTRY);
+    return rv;
+}
+
+/**
+ * @brief Add a Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_fdb_add(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete all Fdb entries
+ * @details Comments:
+ *     If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ *     entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_fdb_del_all(dev_id, flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete Fdb entries on a particular port
+ * @details Comments:
+ *    Athena doesn't support flag option, flag should be setted as zero.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_fdb_del_by_port(dev_id, port_id, flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a particular Fdb entry through mac address
+ * @details Comments:
+ *    Only addr field in entry is meaning. For IVL learning vid or fid field
+ *    also is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_fdb_del_by_mac(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from particular device
+ * @param[in] dev_id device id
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_fdb_first(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get next Fdb entry from particular device
+ * @details Comments:
+ *    For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_fdb_next(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+athena_fdb_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->fdb_add = athena_fdb_add;
+    p_api->fdb_del_all = athena_fdb_del_all;
+    p_api->fdb_del_by_port = athena_fdb_del_by_port;
+    p_api->fdb_del_by_mac = athena_fdb_del_by_mac;
+    p_api->fdb_first = athena_fdb_first;
+    p_api->fdb_next = athena_fdb_next;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/athena/athena_init.c b/qca-ssdk/src/hsl/athena/athena_init.c
new file mode 100755
index 0000000..9e7c84d
--- /dev/null
+++ b/qca-ssdk/src/hsl/athena/athena_init.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup athena_init ATHENA_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "athena_mib.h"
+#include "athena_port_ctrl.h"
+#include "athena_portvlan.h"
+#include "athena_vlan.h"
+#include "athena_fdb.h"
+#include "athena_reg_access.h"
+#include "athena_reg.h"
+#include "athena_init.h"
+
+static ssdk_init_cfg * athena_cfg[SW_MAX_NR_DEV] = { 0 };
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+static sw_error_t
+athena_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
+{
+    hsl_port_prop_t p_type;
+    hsl_dev_t *pdev = NULL;
+    fal_port_t port_id;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return SW_NOT_INITIALIZED;
+
+    for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+    {
+        hsl_port_prop_portmap_set(dev_id, port_id);
+
+        for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
+        {
+            if (HSL_NO_CPU == mode)
+            {
+                SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                continue;
+            }
+
+            switch (p_type)
+            {
+                case HSL_PP_PHY:
+                    if (HSL_CPU_1_PLUS == mode)
+                    {
+                        if ((port_id != pdev->cpu_port_nr)
+                                && (port_id != (pdev->nr_ports -1)))
+                        {
+                            SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                        }
+                    }
+                    else
+                    {
+                        if (port_id != pdev->cpu_port_nr)
+                        {
+                            SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                        }
+                    }
+                    break;
+
+                case HSL_PP_INCL_CPU:
+                    /* include cpu port but exclude wan port in some cases */
+                    if (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1))))
+                        SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+
+                    break;
+
+                case HSL_PP_EXCL_CPU:
+                    /* exclude cpu port and wan port in some cases */
+                    if ((port_id != pdev->cpu_port_nr)
+                            && (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1)))))
+                        SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                    break;
+
+                default:
+                    break;
+            }
+        }
+
+        if (HSL_NO_CPU == mode)
+        {
+            SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+                            (dev_id, port_id, port_id + 1));
+        }
+        else
+        {
+            if (port_id != pdev->cpu_port_nr)
+            {
+                SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+                                (dev_id, port_id, port_id - 1));
+            }
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+athena_hw_init(a_uint32_t dev_id)
+{
+    hsl_dev_t  *pdev = NULL;
+    a_uint32_t port_id, data;
+    sw_error_t rv;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (NULL == pdev)
+    {
+        return SW_NOT_INITIALIZED;
+    }
+
+    for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+    {
+        if (port_id == pdev->cpu_port_nr)
+        {
+            continue;
+        }
+
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data);
+
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+
+#endif
+
+static sw_error_t
+athena_dev_init(a_uint32_t dev_id)
+{
+    hsl_dev_t *pdev = NULL;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return SW_NOT_INITIALIZED;
+
+    pdev->nr_ports = 6;
+    pdev->nr_phy = 5;
+    pdev->cpu_port_nr = 0;
+    pdev->nr_vlans = 16;
+    pdev->hw_vlan_query = A_FALSE;
+    pdev->nr_queue = 4;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_athena_reset(a_uint32_t dev_id)
+{
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+    a_uint32_t val;
+    sw_error_t rv;
+
+    val = 0x1;
+    HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    ATHENA_VLAN_RESET(rv, dev_id);
+
+    rv = athena_hw_init(dev_id);
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+    return SW_OK;
+}
+
+sw_error_t
+athena_cleanup(a_uint32_t dev_id)
+{
+    if (athena_cfg[dev_id])
+    {
+        aos_mem_free(athena_cfg[dev_id]);
+        athena_cfg[dev_id] = NULL;
+    }
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+    {
+        sw_error_t rv;
+        ATHENA_VLAN_CLEANUP(rv, dev_id);
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @brief Reset Athena module.
+ * @details Comments:
+ *    This operation will reset athena.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_reset(dev_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Init Athena module.
+ * @details Comments:
+ *    This operation will init athena.
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+athena_init(a_uint32_t dev_id, ssdk_init_cfg * cfg)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (NULL == athena_cfg[dev_id])
+    {
+        athena_cfg[dev_id] = (ssdk_init_cfg *)aos_mem_alloc(sizeof (ssdk_init_cfg));
+    }
+
+    if (NULL == athena_cfg[dev_id])
+    {
+        return SW_OUT_OF_MEM;
+    }
+
+    aos_mem_copy(athena_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+
+    SW_RTN_ON_ERROR(athena_reg_access_init(dev_id, cfg->reg_mode));
+
+    SW_RTN_ON_ERROR(athena_dev_init(dev_id));
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+    {
+        sw_error_t rv;
+        SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id));
+        SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
+        SW_RTN_ON_ERROR(athena_portproperty_init(dev_id, cfg->cpu_mode));
+
+        ATHENA_MIB_INIT(rv, dev_id);
+        ATHENA_PORT_CTRL_INIT(rv, dev_id);
+        ATHENA_PORTVLAN_INIT(rv, dev_id);
+        ATHENA_VLAN_INIT(rv, dev_id);
+        ATHENA_FDB_INIT(rv, dev_id);
+
+        {
+            hsl_api_t *p_api;
+
+            SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+            p_api->dev_reset   = athena_reset;
+            p_api->dev_clean   = athena_cleanup;
+        }
+
+        SW_RTN_ON_ERROR(athena_hw_init(dev_id));
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/athena/athena_mib.c b/qca-ssdk/src/hsl/athena/athena_mib.c
new file mode 100755
index 0000000..c71cbc3
--- /dev/null
+++ b/qca-ssdk/src/hsl/athena/athena_mib.c
@@ -0,0 +1,406 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup athena_mib ATHENA_MIB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "athena_mib.h"
+#include "athena_reg.h"
+
+static sw_error_t
+_athena_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_mib_info_t * mib_info)
+{
+    a_uint32_t val0 = 0, val1 = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBroad = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxPause = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMulti = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFcsErr = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxAllignErr = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val0),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxRunt = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFragment = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx64Byte = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx128Byte = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx256Byte = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx512Byte = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1024Byte = val0 + val1;
+
+    mib_info->Rx1518Byte = 0;    //reserved for s16
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMaxByte = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxTooLong = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_lo = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_hi = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_lo = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_hi = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxOverFlow = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Filtered = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val0),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxBroad = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val0),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxPause = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val0),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMulti = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxUnderRun = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx64Byte = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx128Byte = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx256Byte = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx512Byte = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1024Byte = val0 + val1;
+
+    mib_info->Tx1518Byte = 0;    //reserved for s16
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMaxByte = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxOverSize = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_lo = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_hi = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxCollision = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxAbortCol = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMultiCol = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxSingalCol = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxExcDefer = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val0),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxDefer = val0 + val1;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+                      (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL_2, port_id,
+                      (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxLateCol = val0 + val1;
+
+    return SW_OK;
+}
+
+/**
+ * @brief Get mib infomation on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                    fal_mib_info_t * mib_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_get_mib_info(dev_id, port_id, mib_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+athena_mib_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->get_mib_info = athena_get_mib_info;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/athena/athena_port_ctrl.c b/qca-ssdk/src/hsl/athena/athena_port_ctrl.c
new file mode 100755
index 0000000..1361684
--- /dev/null
+++ b/qca-ssdk/src/hsl/athena/athena_port_ctrl.c
@@ -0,0 +1,811 @@
+/*
+ * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup athena_port_ctrl ATHENA_PORT_CTRL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "athena_port_ctrl.h"
+#include "athena_reg.h"
+#include "hsl_phy.h"
+
+
+
+static sw_error_t
+_athena_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_port_duplex_t duplex)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    a_uint32_t reg_save = 0;
+    a_uint32_t reg_val = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_duplex_set)
+         return SW_NOT_SUPPORTED;
+
+
+    if (FAL_DUPLEX_BUTT <= duplex)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    //save reg value
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+    reg_save = reg_val;
+
+    SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+    //set mac be config by sw   and turn off RX TX MAC_EN
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+    rv = phy_drv->phy_duplex_set(dev_id, phy_id, duplex);
+
+    //retore reg value
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_save), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+
+static sw_error_t
+_athena_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_port_duplex_t * pduplex)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_duplex_get)
+         return SW_NOT_SUPPORTED;
+
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_duplex_get(dev_id, phy_id, pduplex);
+    return rv;
+}
+
+
+static sw_error_t
+_athena_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_port_speed_t speed)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_speed_set)
+         return SW_NOT_SUPPORTED;
+
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_SPEED_100 < speed)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = phy_drv->phy_speed_set(dev_id, phy_id, speed);
+
+    return rv;
+}
+
+
+static sw_error_t
+_athena_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_port_speed_t * pspeed)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_speed_get)
+         return SW_NOT_SUPPORTED;
+
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_speed_get(dev_id, phy_id, pspeed);
+
+    return rv;
+}
+
+
+static sw_error_t
+_athena_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * status)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_autoneg_status_get)
+         return SW_NOT_SUPPORTED;
+
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *status = phy_drv->phy_autoneg_status_get(dev_id, phy_id);
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_athena_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_autoneg_enable_set)
+	  return SW_NOT_SUPPORTED;
+
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_autoneg_enable_set(dev_id, phy_id);
+    return rv;
+}
+
+
+static sw_error_t
+_athena_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_restart_autoneg)
+         return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_restart_autoneg(dev_id, phy_id);
+    return rv;
+}
+
+
+static sw_error_t
+_athena_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t autoadv)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_autoneg_adv_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_autoneg_adv_set(dev_id, phy_id, autoadv);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_athena_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * autoadv)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_autoneg_adv_get)
+        return SW_NOT_SUPPORTED;
+
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *autoadv = 0;
+    rv = phy_drv->phy_autoneg_adv_get(dev_id, phy_id, autoadv);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_athena_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+
+static sw_error_t
+_athena_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_athena_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+     SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+     if (NULL == phy_drv->phy_powersave_set)
+	   return SW_NOT_SUPPORTED;
+
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_powersave_set(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_athena_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_powersave_get)
+	  return SW_NOT_SUPPORTED;
+
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_powersave_get(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_athena_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_hibernation_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_hibernation_set(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_athena_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_hibernation_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_hibernation_get(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_port_duplex_t duplex)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_duplex_set(dev_id, port_id, duplex);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_port_duplex_t * pduplex)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_duplex_get(dev_id, port_id, pduplex);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_speed_t speed)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_speed_set(dev_id, port_id, speed);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_speed_t * pspeed)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_speed_get(dev_id, port_id, pspeed);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_autoneg_status_get(dev_id, port_id, status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_autoneg_enable(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_autoneg_restart(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ * @details Comments:
+ *    Auto negotiation advtisement ability is defined by macro such as
+ *    FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t autoadv)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_autoneg_adv_set(dev_id, port_id, autoadv);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * autoadv)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_autoneg_adv_get(dev_id, port_id, autoadv);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld packets snooping status on a particular port.
+ * @details Comments:
+ *    After enabling igmp snooping feature on a particular port all kinds
+ *    igmp packets received on this port would be acknowledged by hardware.
+ *    Athena only supports igmp packets, it doesn't support mld packets.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_igmps_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp packets snooping status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_igmps_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_powersave_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_powersave_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_hibernate_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_hibernate_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+athena_port_ctrl_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->port_duplex_get = athena_port_duplex_get;
+    p_api->port_duplex_set = athena_port_duplex_set;
+    p_api->port_speed_get = athena_port_speed_get;
+    p_api->port_speed_set = athena_port_speed_set;
+    p_api->port_autoneg_status_get = athena_port_autoneg_status_get;
+    p_api->port_autoneg_enable = athena_port_autoneg_enable;
+    p_api->port_autoneg_restart = athena_port_autoneg_restart;
+    p_api->port_autoneg_adv_get = athena_port_autoneg_adv_get;
+    p_api->port_autoneg_adv_set = athena_port_autoneg_adv_set;
+    p_api->port_igmps_status_set = athena_port_igmps_status_set;
+    p_api->port_igmps_status_get = athena_port_igmps_status_get;
+    p_api->port_powersave_set = athena_port_powersave_set;
+    p_api->port_powersave_get = athena_port_powersave_get;
+    p_api->port_hibernate_set = athena_port_hibernate_set;
+    p_api->port_hibernate_get = athena_port_hibernate_get;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/athena/athena_portvlan.c b/qca-ssdk/src/hsl/athena/athena_portvlan.c
new file mode 100755
index 0000000..74fdc3e
--- /dev/null
+++ b/qca-ssdk/src/hsl/athena/athena_portvlan.c
@@ -0,0 +1,451 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup athena_port_vlan ATHENA_PORT_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "athena_portvlan.h"
+#include "athena_reg.h"
+
+
+static sw_error_t
+_athena_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_1Q_MODE_BUTT <= port_1qmode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+                      (a_uint8_t *) (&regval[port_1qmode]),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+
+static sw_error_t
+_athena_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK,
+                                  FAL_1Q_CHECK, FAL_1Q_SECURE
+                                };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(pport_1qmode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    *pport_1qmode = retval[regval & 0x3];
+
+    return SW_OK;
+
+}
+
+
+static sw_error_t
+_athena_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3};
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_EG_MODE_BUTT <= port_egvlanmode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((FAL_EG_TAGGED == port_egvlanmode) || (FAL_EG_HYBRID == port_egvlanmode))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+                      (a_uint8_t *) (&regval[port_egvlanmode]),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+
+static sw_error_t
+_athena_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_1q_egmode_t retval[3] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED,
+                                     FAL_EG_TAGGED
+                                   };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(pport_egvlanmode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    *pport_egvlanmode = retval[regval & 0x3];
+
+    return SW_OK;
+
+}
+
+
+static sw_error_t
+_athena_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    regval |= (0x1UL << mem_port_id);
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+
+static sw_error_t
+_athena_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    regval &= (~(0x1UL << mem_port_id));
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+
+static sw_error_t
+_athena_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE ==
+            hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&mem_port_map),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+
+static sw_error_t
+_athena_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    *mem_port_map = 0;
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) mem_port_map,
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_1qmode_set(dev_id, port_id, port_1qmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_1qmode_get(dev_id, port_id, pport_1qmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_portvlan_member_add(dev_id, port_id, mem_port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_portvlan_member_del(dev_id, port_id, mem_port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Update member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_portvlan_member_update(dev_id, port_id, mem_port_map);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_portvlan_member_get(dev_id, port_id, mem_port_map);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+athena_portvlan_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->port_1qmode_get = athena_port_1qmode_get;
+    p_api->port_1qmode_set = athena_port_1qmode_set;
+    p_api->port_egvlanmode_get = athena_port_egvlanmode_get;
+    p_api->port_egvlanmode_set = athena_port_egvlanmode_set;
+    p_api->portvlan_member_add = athena_portvlan_member_add;
+    p_api->portvlan_member_del = athena_portvlan_member_del;
+    p_api->portvlan_member_update = athena_portvlan_member_update;
+    p_api->portvlan_member_get = athena_portvlan_member_get;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/athena/athena_reg_access.c b/qca-ssdk/src/hsl/athena/athena_reg_access.c
new file mode 100755
index 0000000..be4ae46
--- /dev/null
+++ b/qca-ssdk/src/hsl/athena/athena_reg_access.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "sd.h"
+#include "athena_reg_access.h"
+
+static hsl_access_mode reg_mode;
+
+#if defined(API_LOCK)
+static aos_lock_t mdio_lock;
+#define MDIO_LOCKER_INIT    aos_lock_init(&mdio_lock)
+#define MDIO_LOCKER_LOCK    aos_lock(&mdio_lock)
+#define MDIO_LOCKER_UNLOCK  aos_unlock(&mdio_lock)
+#else
+#define MDIO_LOCKER_INIT
+#define MDIO_LOCKER_LOCK
+#define MDIO_LOCKER_UNLOCK
+#endif
+
+static sw_error_t
+_athena_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                     a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_word_addr;
+    a_uint32_t phy_addr, reg_val;
+    a_uint16_t phy_val, tmp_val;
+    a_uint8_t phy_reg;
+    sw_error_t rv;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    /* change reg_addr to 16-bit word address, 32-bit aligned */
+    reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+    /* configure register high address */
+    phy_addr = 0x18;
+    phy_reg = 0x0;
+    phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    /* For some registers such as MIBs, since it is read/clear, we should */
+    /* read the lower 16-bit register then the higher one */
+
+    /* read register in lower address */
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+    SW_RTN_ON_ERROR(rv);
+    reg_val = tmp_val;
+
+    /* read register in higher address */
+    reg_word_addr++;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+    SW_RTN_ON_ERROR(rv);
+    reg_val |= (((a_uint32_t)tmp_val) << 16);
+
+    aos_mem_copy(value, &reg_val, sizeof (a_uint32_t));
+
+    return SW_OK;
+}
+
+static sw_error_t
+_athena_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                     a_uint32_t value_len)
+{
+    a_uint32_t reg_word_addr;
+    a_uint32_t phy_addr, reg_val;
+    a_uint16_t phy_val;
+    a_uint8_t phy_reg;
+    sw_error_t rv;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    aos_mem_copy(&reg_val, value, sizeof (a_uint32_t));
+
+    /* change reg_addr to 16-bit word address, 32-bit aligned */
+    reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+    /* configure register high address */
+    phy_addr = 0x18;
+    phy_reg = 0x0;
+    phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    /* For some registers such as ARL and VLAN, since they include BUSY bit */
+    /* in lower address, we should write the higher 16-bit register then the */
+    /* lower one */
+
+    /* write register in higher address */
+    reg_word_addr++;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff);
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    /* write register in lower address */
+    reg_word_addr--;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (a_uint16_t) (reg_val & 0xffff);
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+sw_error_t
+athena_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+               a_uint32_t reg, a_uint16_t * value)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value);
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+athena_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+               a_uint32_t reg, a_uint16_t value)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value);
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+athena_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+               a_uint32_t value_len)
+{
+    sw_error_t rv;
+    a_uint32_t flags;
+
+    MDIO_LOCKER_LOCK;
+    if (HSL_MDIO == reg_mode)
+    {
+        aos_irq_save(flags);
+        rv = _athena_mdio_reg_get(dev_id, reg_addr, value, value_len);
+        aos_irq_restore(flags);
+    }
+    else
+    {
+        rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len);
+    }
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+athena_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+               a_uint32_t value_len)
+{
+    sw_error_t rv;
+    a_uint32_t flags;
+
+    MDIO_LOCKER_LOCK;
+    if (HSL_MDIO == reg_mode)
+    {
+        aos_irq_save(flags);
+        rv = _athena_mdio_reg_set(dev_id, reg_addr, value, value_len);
+        aos_irq_restore(flags);
+    }
+    else
+    {
+        rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len);
+    }
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+athena_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                     a_uint32_t bit_offset, a_uint32_t field_len,
+                     a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val = 0;
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(athena_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len);
+    return SW_OK;
+}
+
+sw_error_t
+athena_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                     a_uint32_t bit_offset, a_uint32_t field_len,
+                     const a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val;
+    a_uint32_t field_val = *((a_uint32_t *) value);
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(athena_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len);
+
+    SW_RTN_ON_ERROR(athena_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    return SW_OK;
+}
+
+sw_error_t
+athena_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode)
+{
+    hsl_api_t *p_api;
+
+    MDIO_LOCKER_INIT;
+    reg_mode = mode;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+    p_api->phy_get = athena_phy_get;
+    p_api->phy_set = athena_phy_set;
+    p_api->reg_get = athena_reg_get;
+    p_api->reg_set = athena_reg_set;
+    p_api->reg_field_get = athena_reg_field_get;
+    p_api->reg_field_set = athena_reg_field_set;
+    p_api->dev_access_set= athena_access_mode_set;
+
+    return SW_OK;
+}
+
+sw_error_t
+athena_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode)
+{
+    reg_mode = mode;
+    return SW_OK;
+
+}
+
diff --git a/qca-ssdk/src/hsl/athena/athena_vlan.c b/qca-ssdk/src/hsl/athena/athena_vlan.c
new file mode 100755
index 0000000..a4f48f5
--- /dev/null
+++ b/qca-ssdk/src/hsl/athena/athena_vlan.c
@@ -0,0 +1,622 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup athena_vlan ATHENA_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "athena_vlan.h"
+#include "athena_reg.h"
+
+#define MAX_VLAN_ENTRY      16
+#define MAX_VLAN_ID         4094
+
+#define VLAN_FLUSH          1
+#define VLAN_LOAD_ENTRY     2
+#define VLAN_PURGE_ENTRY    3
+#define VLAN_REMOVE_PORT    4
+
+typedef struct
+{
+    fal_vlan_t vlan_entry;
+    a_bool_t active;
+} v_array_t;
+
+static v_array_t *p_vlan_table[SW_MAX_NR_DEV] = { 0 };
+
+static sw_error_t
+athena_vlan_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val;
+    sw_error_t rv;
+
+    while (vt_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
+                          (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_BUSY;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_FUNC, op, val);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_BUSY, 1, val);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_FULL_VIO,
+                      (a_uint8_t *) (&vt_full), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (vt_full)
+    {
+        val = 0x10;
+        HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        if (VLAN_LOAD_ENTRY == op)
+        {
+            return SW_FULL;
+        }
+        else if (VLAN_PURGE_ENTRY == op)
+        {
+            return SW_NOT_FOUND;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+athena_vlan_table_location(a_uint32_t dev_id, a_uint16_t vlan_id,
+                           a_int16_t * loc)
+{
+    a_int16_t i = 0;
+    v_array_t *p_v_array;
+
+    if (p_vlan_table[dev_id] == NULL)
+        return SW_NOT_INITIALIZED;
+
+    p_v_array = p_vlan_table[dev_id];
+
+    for (i = 0; i < MAX_VLAN_ENTRY; i++)
+    {
+        if ((p_v_array[i].active == A_TRUE)
+                && (p_v_array[i].vlan_entry.vid == vlan_id))
+            break;
+    }
+
+    if (i == MAX_VLAN_ENTRY)
+        return SW_NOT_FOUND;
+
+    *loc = i;
+
+    return SW_OK;
+}
+
+static sw_error_t
+athena_vlan_sw_to_hw(const fal_vlan_t * vlan_entry, a_uint32_t reg[])
+{
+    if (A_TRUE == vlan_entry->vid_pri_en)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]);
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri, reg[0]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]);
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_entry->vid, reg[0]);
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, reg[1]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VID_MEM, vlan_entry->mem_ports, reg[1]);
+
+    if (0 != vlan_entry->u_ports)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_athena_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+#ifdef HSL_STANDALONG
+    a_int16_t i, loc = MAX_VLAN_ENTRY;
+    v_array_t *p_v_array;
+#endif
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_entry->vid == 0) || (vlan_entry->vid > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    if (A_FALSE == hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU))
+        return SW_BAD_PARAM;
+
+#ifdef HSL_STANDALONG
+    if ((p_v_array = p_vlan_table[dev_id]) == NULL)
+        return SW_NOT_INITIALIZED;
+
+    for (i = 0; i < MAX_VLAN_ENTRY; i++)
+    {
+        if (p_v_array[i].active == A_FALSE)
+        {
+            loc = i;
+        }
+        else if (p_v_array[i].vlan_entry.vid == vlan_entry->vid)
+        {
+            return SW_ALREADY_EXIST;
+        }
+    }
+
+    if (loc == MAX_VLAN_ENTRY)
+        return SW_FULL;
+#endif
+
+    rv = athena_vlan_sw_to_hw(vlan_entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = athena_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+#ifdef HSL_STANDALONG
+    p_v_array[loc].vlan_entry = *vlan_entry;
+    p_v_array[loc].active     = A_TRUE;
+#endif
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_athena_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+    a_uint32_t vtable_entry = 0;
+#ifdef HSL_STANDALONG
+    a_int16_t i, loc = MAX_VLAN_ENTRY;
+    v_array_t *p_v_array;
+#endif
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+#ifdef HSL_STANDALONG
+    if ((p_v_array = p_vlan_table[dev_id]) == NULL)
+        return SW_NOT_INITIALIZED;
+
+    for (i = 0; i < MAX_VLAN_ENTRY; i++)
+    {
+        if (p_v_array[i].active == A_FALSE)
+        {
+            loc = i;
+        }
+        else if (p_v_array[i].vlan_entry.vid == vlan_id)
+        {
+            return SW_ALREADY_EXIST;
+        }
+    }
+
+    if (loc == MAX_VLAN_ENTRY)
+        return SW_FULL;
+#endif
+
+    /* set default value for VLAN_TABLE_FUNC0, all 0 except vid */
+    vtable_entry = 0;
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, vtable_entry);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&vtable_entry), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    /* set default value for VLAN_TABLE_FUNC1, all 0 */
+    vtable_entry = 0;
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, vtable_entry);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&vtable_entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = athena_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+#ifdef HSL_STANDALONG
+    p_v_array[loc].vlan_entry.vid = vlan_id;
+    p_v_array[loc].vlan_entry.mem_ports = 0;
+    p_v_array[loc].vlan_entry.u_ports = 0;
+    p_v_array[loc].vlan_entry.vid_pri_en = A_FALSE;
+    p_v_array[loc].vlan_entry.vid_pri = 0;
+    p_v_array[loc].active = A_TRUE;
+#endif
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_athena_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+#ifdef HSL_STANDALONG
+    a_uint16_t i = 0, loc = MAX_VLAN_ENTRY;
+    a_uint16_t tmp_vid = MAX_VLAN_ID + 1;
+    v_array_t *p_v_array;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (vlan_id > MAX_VLAN_ID)
+        return SW_OUT_OF_RANGE;
+
+    if ((p_v_array = p_vlan_table[dev_id]) == NULL)
+        return SW_NOT_INITIALIZED;
+
+    for (i = 0; i < MAX_VLAN_ENTRY; i++)
+    {
+        if ((p_v_array[i].active == A_TRUE)
+                && (p_v_array[i].vlan_entry.vid > vlan_id))
+        {
+            if (tmp_vid > p_v_array[i].vlan_entry.vid)
+            {
+                loc = i;
+                tmp_vid = p_v_array[i].vlan_entry.vid;
+            }
+        }
+    }
+
+    if (loc == MAX_VLAN_ENTRY)
+        return SW_NO_MORE;
+
+    *p_vlan = p_v_array[loc].vlan_entry;
+
+    return SW_OK;
+#else
+    return SW_NOT_SUPPORTED;
+#endif
+}
+
+
+static sw_error_t
+_athena_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+#ifdef HSL_STANDALONG
+    a_int16_t loc;
+    v_array_t *p_v_array;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    if ((p_v_array = p_vlan_table[dev_id]) == NULL)
+        return SW_NOT_INITIALIZED;
+
+    rv = athena_vlan_table_location(dev_id, vlan_id, &loc);
+    SW_RTN_ON_ERROR(rv);
+    *p_vlan = p_v_array[loc].vlan_entry;
+
+    return SW_OK;
+#else
+    return SW_NOT_SUPPORTED;
+#endif
+}
+
+
+static sw_error_t
+_athena_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                           fal_pbmp_t member, fal_pbmp_t u_member)
+{
+#ifdef HSL_STANDALONG
+    sw_error_t rv;
+    a_int16_t loc;
+    a_uint32_t reg_tmp;
+    v_array_t *p_v_array;
+    fal_vlan_t *p_sw_vlan;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU))
+        return SW_BAD_PARAM;
+
+    if (u_member != 0)
+        return SW_BAD_PARAM;
+
+    if ((p_v_array = p_vlan_table[dev_id]) == NULL)
+        return SW_NOT_INITIALIZED;
+
+    rv = athena_vlan_table_location(dev_id, vlan_id, &loc);
+    SW_RTN_ON_ERROR(rv);
+    p_sw_vlan = &p_v_array[loc].vlan_entry;
+
+    /* set  value for VLAN_TABLE_FUNC0, all 0 except vid */
+    reg_tmp = 0;
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg_tmp);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN,
+                        (a_int32_t)p_sw_vlan->vid_pri_en, reg_tmp);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, p_sw_vlan->vid_pri, reg_tmp);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg_tmp), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* set  vlan member for VLAN_TABLE_FUNC1 */
+    HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VID_MEM,
+                      (a_uint8_t *) (&member), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = athena_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    p_v_array[loc].vlan_entry.mem_ports = member;
+
+    return SW_OK;
+#else
+    return SW_NOT_SUPPORTED;
+#endif
+}
+
+
+static sw_error_t
+_athena_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+    a_int16_t loc;
+    a_uint32_t reg_tmp;
+#ifdef HSL_STANDALONG
+    v_array_t *p_v_array;
+#endif
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+#ifdef HSL_STANDALONG
+    if ((p_v_array = p_vlan_table[dev_id]) == NULL)
+        return SW_NOT_INITIALIZED;
+
+    rv = athena_vlan_table_location(dev_id, vlan_id, &loc);
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+    reg_tmp = (a_int32_t) vlan_id;
+    HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VLAN_ID,
+                      (a_uint8_t *) (&reg_tmp), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = athena_vlan_commit(dev_id, VLAN_PURGE_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+#ifdef HSL_STANDALONG
+    p_v_array[loc].active = A_FALSE;
+#endif
+
+    return SW_OK;
+}
+
+sw_error_t
+athena_vlan_reset(a_uint32_t dev_id)
+{
+#ifdef HSL_STANDALONG
+    a_int16_t i;
+    v_array_t *p_v_array;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    aos_mem_zero(p_vlan_table[dev_id], MAX_VLAN_ENTRY * (sizeof (v_array_t)));
+
+    p_v_array = p_vlan_table[dev_id];
+    for (i = 0; i < MAX_VLAN_ENTRY; i++)
+    {
+        p_v_array[i].active = A_FALSE;
+    }
+#endif
+
+    return SW_OK;
+}
+
+sw_error_t
+athena_vlan_cleanup(a_uint32_t dev_id)
+{
+    if (p_vlan_table[dev_id])
+    {
+        aos_mem_free(p_vlan_table[dev_id]);
+        p_vlan_table[dev_id] = NULL;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Append a vlan entry on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_entry vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_vlan_entry_append(dev_id, vlan_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Creat a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ *    After this operation the member ports of the created vlan entry are null.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_vlan_create(dev_id, vlan_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ *    If the value of vid is zero this operation will get the first entry.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_vlan_next(dev_id, vlan_id, p_vlan);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a vlan entry through vlan id on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_vlan_find(dev_id, vlan_id, p_vlan);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Update a vlan entry member port through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] member member ports
+ * @param[in] u_member tagged or untagged infomation for member ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                          fal_pbmp_t member, fal_pbmp_t u_member)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_vlan_member_update(dev_id, vlan_id, member, u_member);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a vlan entry through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _athena_vlan_delete(dev_id, vlan_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+athena_vlan_init(a_uint32_t dev_id)
+{
+#ifdef HSL_STANDALONG
+    a_int16_t i;
+    v_array_t *p_v_array;
+    v_array_t *p_mem;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    /* allocate memory for vlan info */
+    p_mem = aos_mem_alloc(MAX_VLAN_ENTRY * (sizeof (v_array_t)));
+    if (p_mem == NULL)
+        return SW_OUT_OF_MEM;
+
+    aos_mem_zero(p_mem, MAX_VLAN_ENTRY * (sizeof (v_array_t)));
+
+    /* start address for vlan info */
+    p_vlan_table[dev_id] = p_v_array = p_mem;
+
+    for (i = 0; i < MAX_VLAN_ENTRY; i++)
+    {
+        p_v_array[i].active = A_FALSE;
+    }
+#endif
+
+#ifndef HSL_STANDALONG
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->vlan_entry_append = athena_vlan_entry_append;
+    p_api->vlan_creat = athena_vlan_create;
+    p_api->vlan_delete = athena_vlan_delete;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/cppe/Makefile b/qca-ssdk/src/hsl/cppe/Makefile
new file mode 100755
index 0000000..73c4dd6
--- /dev/null
+++ b/qca-ssdk/src/hsl/cppe/Makefile
@@ -0,0 +1,23 @@
+LOC_DIR=src/hsl/cppe
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+  SRC_LIST+=cppe_portctrl.c
+  SRC_LIST+=cppe_loopback.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+  SRC_LIST+=cppe_qos.c
+endif
+
+ifeq (, $(findstring CPPE, $(SUPPORT_CHIP)))
+  SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/hsl/cppe/cppe_loopback.c b/qca-ssdk/src/hsl/cppe/cppe_loopback.c
new file mode 100755
index 0000000..49795ae
--- /dev/null
+++ b/qca-ssdk/src/hsl/cppe/cppe_loopback.c
@@ -0,0 +1,440 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "cppe_loopback_reg.h"
+#include "cppe_loopback.h"
+
+sw_error_t
+cppe_lpbk_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_enable_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBK_ENABLE_ADDRESS + \
+				index * LPBK_ENABLEL_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_enable_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBK_ENABLE_ADDRESS + \
+				index * LPBK_ENABLEL_INC,
+				value->val);
+}
+
+sw_error_t
+cppe_lpbk_fifo_1_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_fifo_1_ctrl_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBK_FIFO_1_CTRL_ADDRESS + \
+				index * LPBK_FIFO_1_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_fifo_1_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_fifo_1_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBK_FIFO_1_CTRL_ADDRESS + \
+				index * LPBK_FIFO_1_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+cppe_lpbk_fifo_2_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_fifo_2_ctrl_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBK_FIFO_2_CTRL_ADDRESS + \
+				index * LPBK_FIFO_2_CTRL_INC,
+				&value->val);
+}
+
+
+sw_error_t
+cppe_lpbk_fifo_2_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_fifo_2_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBK_FIFO_2_CTRL_ADDRESS + \
+				index * LPBK_FIFO_2_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+cppe_lpbk_pps_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_pps_ctrl_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBK_PPS_CTRL_ADDRESS + \
+				index * LPBK_PPS_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_pps_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_pps_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBK_PPS_CTRL_ADDRESS + \
+				index * LPBK_PPS_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+cppe_lpbk_mac_junmo_size_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_mac_junmo_size_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBK_MAC_JUNMO_SIZE_ADDRESS + \
+				index * LPBK_MAC_JUNMO_SIZE_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mac_junmo_size_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_mac_junmo_size_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBK_MAC_JUNMO_SIZE_ADDRESS + \
+				index * LPBK_MAC_JUNMO_SIZE_INC,
+				value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_mib_ctrl_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBK_MIB_CTRL_ADDRESS + \
+				index * LPBK_MIB_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbk_mib_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBK_MIB_CTRL_ADDRESS + \
+				index * LPBK_MIB_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_uni_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkuni_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKUNI_ADDRESS + \
+				index * LPBKUNI_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_multi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkmulti_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKMULTI_ADDRESS + \
+				index * LPBKMULTI_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_broad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkbroad_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKBROAD_ADDRESS + \
+				index * LPBKBROAD_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_pkt64_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt64_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKPKT64_ADDRESS + \
+				index * LPBKPKT64_INC,
+				&value->val);
+
+}
+
+sw_error_t
+cppe_lpbk_mib_pkt65to127_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt65to127_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKPKT65TO127_ADDRESS + \
+				index * LPBKPKT65TO127_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_pkt128to255_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt128to255_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKPKT128TO255_ADDRESS + \
+				index * LPBKPKT128TO255_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_pkt256to511_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt256to511_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKPKT256TO511_ADDRESS + \
+				index * LPBKPKT256TO511_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_pkt512to1023_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt512to1023_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKPKT512TO1023_ADDRESS + \
+				index * LPBKPKT512TO1023_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_pkt1024to1518_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt1024to1518_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKPKT1024TO1518_ADDRESS + \
+				index * LPBKPKT1024TO1518_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_pkt1519tox_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt1519tox_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKPKT1519TOX_ADDRESS + \
+				index * LPBKPKT1519TOX_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_toolong_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkttoolong_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKPKTTOOLONG_ADDRESS + \
+				index * LPBKPKTTOOLONG_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_byte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkbyte_l_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKBYTE_L_ADDRESS + \
+				index * LPBKBYTE_L_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_byte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkbyte_h_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKBYTE_H_ADDRESS + \
+				index * LPBKBYTE_H_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_drop_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkdropcounter_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKDROPCOUNTER_ADDRESS + \
+				index * LPBKDROPCOUNTER_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_tooshort_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkttooshort_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKPKTTOOSHORT_ADDRESS + \
+				index * LPBKPKTTOOSHORT_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_pkt14to63_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbkpkt14to63_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKPKT14TO63_ADDRESS + \
+				index * LPBKPKT14TO63_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_toolongbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbktoolongbyte_l_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKTOOLONGBYTE_L_ADDRESS + \
+				index * LPBKTOOLONGBYTE_L_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_toolongbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbktoolongbyte_h_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKTOOLONGBYTE_H_ADDRESS + \
+				index * LPBKTOOLONGBYTE_H_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_tooshortbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbktooshortbyte_l_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKTOOSHORTBYTE_L_ADDRESS + \
+				index * LPBKTOOSHORTBYTE_L_INC,
+				&value->val);
+}
+
+sw_error_t
+cppe_lpbk_mib_tooshortbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpbktooshortbyte_h_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + LPBKTOOSHORTBYTE_H_ADDRESS + \
+				index * LPBKTOOSHORTBYTE_H_INC,
+				&value->val);
+}
diff --git a/qca-ssdk/src/hsl/cppe/cppe_portctrl.c b/qca-ssdk/src/hsl/cppe/cppe_portctrl.c
new file mode 100755
index 0000000..31ffb24
--- /dev/null
+++ b/qca-ssdk/src/hsl/cppe/cppe_portctrl.c
@@ -0,0 +1,488 @@
+/*
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_global_reg.h"
+#include "cppe_portctrl_reg.h"
+#include "cppe_portctrl.h"
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union cppe_mru_mtu_ctrl_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+			dev_id,
+			IPE_L2_BASE_ADDR + CPPE_MRU_MTU_CTRL_TBL_ADDRESS + \
+			index * CPPE_MRU_MTU_CTRL_TBL_INC,
+			value->val,
+			2);
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union cppe_mru_mtu_ctrl_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+			dev_id,
+			IPE_L2_BASE_ADDR + CPPE_MRU_MTU_CTRL_TBL_ADDRESS + \
+			index * CPPE_MRU_MTU_CTRL_TBL_INC,
+			value->val,
+			2);
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_dscp_res_prec_force_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dscp_res_prec_force;
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_dscp_res_prec_force_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dscp_res_prec_force = value;
+	ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pcp_res_prec_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pcp_res_prec;
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pcp_res_prec_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pcp_res_prec = value;
+	ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pcp_qos_group_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pcp_qos_group_id;
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pcp_qos_group_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pcp_qos_group_id = value;
+	ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pcp_res_prec_force_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pcp_res_prec_force;
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pcp_res_prec_force_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pcp_res_prec_force = value;
+	ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_post_acl_res_prec_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.post_acl_res_prec;
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_post_acl_res_prec_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.post_acl_res_prec = value;
+	ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_preheader_res_prec_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.preheader_res_prec;
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_preheader_res_prec_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.preheader_res_prec = value;
+	ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_dscp_res_prec_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dscp_res_prec;
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_dscp_res_prec_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dscp_res_prec = value;
+	ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pre_acl_res_prec_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pre_acl_res_prec;
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_pre_acl_res_prec_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pre_acl_res_prec = value;
+	ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_flow_res_prec_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_res_prec;
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_flow_res_prec_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_res_prec = value;
+	ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_dscp_qos_group_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dscp_qos_group_id;
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_dscp_qos_group_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dscp_qos_group_id = value;
+	ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_src_profile_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.src_profile;
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_src_profile_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.src_profile = value;
+	ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_source_filter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+	{
+		return ret;
+	}
+	reg_val.bf.source_filtering_bypass = value;
+	ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_source_filter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.source_filtering_bypass;
+
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_source_filter_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+	{
+		return ret;
+	}
+	reg_val.bf.source_filtering_mode = value;
+	ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+
+	return ret;
+}
+
+sw_error_t
+cppe_mru_mtu_ctrl_tbl_source_filter_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union cppe_mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.source_filtering_mode;
+
+	return ret;
+}
+
+sw_error_t
+cppe_port_phy_status_1_get(
+		a_uint32_t dev_id,
+		union cppe_port_phy_status_1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT_PHY_STATUS_1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+cppe_port5_pcs1_phy_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union cppe_port_phy_status_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_port_phy_status_1_get(dev_id, &reg_val);
+	*value = reg_val.bf.port5_pcs1_phy_status;
+	return ret;
+}
diff --git a/qca-ssdk/src/hsl/cppe/cppe_qos.c b/qca-ssdk/src/hsl/cppe/cppe_qos.c
new file mode 100755
index 0000000..a919192
--- /dev/null
+++ b/qca-ssdk/src/hsl/cppe/cppe_qos.c
@@ -0,0 +1,428 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_qos_reg.h"
+#include "hppe_qos.h"
+#include "cppe_qos_reg.h"
+
+
+sw_error_t
+cppe_qos_mapping_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union qos_mapping_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + QOS_MAPPING_TBL_ADDRESS + \
+				index * QOS_MAPPING_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union qos_mapping_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + QOS_MAPPING_TBL_ADDRESS + \
+				index * QOS_MAPPING_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.int_pcp;
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.int_pcp = value;
+	ret = cppe_qos_mapping_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.int_dei;
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.int_dei = value;
+	ret = cppe_qos_mapping_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dei_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.int_dei_en;
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dei_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.int_dei_en = value;
+	ret = cppe_qos_mapping_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_dscp_tc_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dscp_tc_mask;
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_dscp_tc_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dscp_tc_mask = value;
+	ret = cppe_qos_mapping_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dscp_tc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.int_dscp_tc;
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dscp_tc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.int_dscp_tc = value;
+	ret = cppe_qos_mapping_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dp_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.int_dp_en;
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dp_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.int_dp_en = value;
+	ret = cppe_qos_mapping_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.int_dp;
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.int_dp = value;
+	ret = cppe_qos_mapping_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pri_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.int_pri_en;
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pri_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.int_pri_en = value;
+	ret = cppe_qos_mapping_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_qos_res_prec_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.qos_res_prec_1 << 1 | \
+		reg_val.bf.qos_res_prec_0;
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_qos_res_prec_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.qos_res_prec_1 = value >> 1;
+	reg_val.bf.qos_res_prec_0 = value & (((a_uint64_t)1<<1)-1);
+	ret = cppe_qos_mapping_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pcp_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.int_pcp_en;
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pcp_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.int_pcp_en = value;
+	ret = cppe_qos_mapping_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.int_pri;
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.int_pri = value;
+	ret = cppe_qos_mapping_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dscp_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.int_dscp_en;
+	return ret;
+}
+
+sw_error_t
+cppe_qos_mapping_tbl_int_dscp_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union qos_mapping_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = cppe_qos_mapping_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.int_dscp_en = value;
+	ret = cppe_qos_mapping_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
\ No newline at end of file
diff --git a/qca-ssdk/src/hsl/dess/Makefile b/qca-ssdk/src/hsl/dess/Makefile
new file mode 100755
index 0000000..c79a503
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/Makefile
@@ -0,0 +1,114 @@
+LOC_DIR=src/hsl/dess
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=dess_reg_access.c dess_init.c
+
+ifeq (TRUE, $(IN_ACL))
+  SRC_LIST += dess_acl.c dess_acl_parse.c dess_multicast_acl.c
+endif
+
+ifeq (TRUE, $(IN_FDB))
+  SRC_LIST += dess_fdb.c
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+  SRC_LIST += dess_igmp.c
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+  SRC_LIST += dess_leaky.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+  SRC_LIST += dess_led.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+  SRC_LIST += dess_mib.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+  SRC_LIST += dess_mirror.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+  SRC_LIST += dess_misc.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+  SRC_LIST += dess_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+  SRC_LIST += dess_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+  SRC_LIST += dess_qos.c
+endif
+
+ifeq (TRUE, $(IN_RATE))
+  SRC_LIST += dess_rate.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+  SRC_LIST += dess_stp.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+  SRC_LIST += dess_vlan.c
+endif
+
+ifeq (TRUE, $(IN_COSMAP))
+  SRC_LIST += dess_cosmap.c
+endif
+
+ifeq (TRUE, $(IN_IP))
+  SRC_LIST += dess_ip.c
+endif
+
+ifeq (TRUE, $(IN_NAT))
+  SRC_LIST += dess_nat.c
+endif
+
+ifeq (TRUE, $(IN_NAT_HELPER))
+  SRC_LIST += nat_helper_dt.c
+  SRC_LIST += nat_helper_hsl.c
+  SRC_LIST += nat_ipt_helper.c
+  SRC_LIST += napt_helper.c
+  SRC_LIST += host_helper.c
+  SRC_LIST += nat_helper.c
+  SRC_LIST += napt_acl.c
+endif
+
+ifeq (TRUE, $(IN_TRUNK))
+  SRC_LIST += dess_trunk.c
+endif
+
+ifeq (TRUE, $(IN_SEC))
+  SRC_LIST += dess_sec.c
+endif
+
+ifeq (TRUE, $(IN_INTERFACECONTROL))
+  SRC_LIST += dess_interface_ctrl.c dess_psgmii.c
+endif
+
+ifeq (linux, $(OS))
+	ifeq (KSLIB, $(MODULE_TYPE))
+    ifneq (TRUE, $(KERNEL_MODE))
+      SRC_LIST=dess_reg_access.c dess_init.c
+	  endif
+	endif
+endif
+
+ifeq (, $(findstring DESS, $(SUPPORT_CHIP)))
+  SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/hsl/dess/dess_acl.c b/qca-ssdk/src/hsl/dess/dess_acl.c
new file mode 100755
index 0000000..9783ac4
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_acl.c
@@ -0,0 +1,2039 @@
+/*
+ * Copyright (c) 2014, 2016, 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_acl DESS_ACL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+#include "dess_acl.h"
+#include "dess_reg.h"
+#include "dess_acl_prv.h"
+
+//#define DESS_ACL_DEBUG
+//#define DESS_SW_ENTRY
+#define DESS_HW_ENTRY
+
+static dess_acl_list_t *sw_list_ent[SW_MAX_NR_DEV];
+static dess_acl_rule_t *sw_rule_ent[SW_MAX_NR_DEV];
+
+static dess_acl_rule_t *sw_rule_tmp[SW_MAX_NR_DEV];
+static dess_acl_rule_t *hw_rule_tmp[SW_MAX_NR_DEV];
+#ifdef DESS_SW_ENTRY
+static a_uint8_t *sw_filter_mem = NULL;
+#endif
+
+static sw_error_t
+_dess_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag);
+
+#ifndef DESS_SW_ENTRY
+#ifndef DESS_HW_ENTRY
+static sw_error_t
+_dess_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx,
+                        a_uint32_t ports);
+
+static sw_error_t
+_dess_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+                   a_uint32_t op);
+#endif
+#endif
+
+//static sw_error_t
+//_dess_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+//                  a_uint32_t op);
+
+static sw_error_t
+_dess_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter,
+                        a_uint32_t flt_idx);
+
+static sw_error_t
+_dess_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter,
+                      a_uint32_t flt_idx);
+
+static sw_error_t
+_dess_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+                                  a_uint32_t rule_id, a_bool_t enable);
+
+static void
+_dess_acl_list_dump(a_uint32_t dev_id)
+{
+    a_uint32_t i;
+    dess_acl_list_t *sw_list;
+
+    aos_printk("\ndev_id=%d  list control infomation:", dev_id);
+    for (i = 0; i < DESS_MAX_FILTER; i++)
+    {
+        sw_list = &(sw_list_ent[dev_id][i]);
+        if (ENT_USED & sw_list->status)
+        {
+            aos_printk
+            ("\nlist_id=%02d  list_pri=%02d  rule_nr=%02d  [pts_map]:0x%02x  idx=%02d ",
+             sw_list->list_id, sw_list->list_pri, sw_list->rule_nr,
+             sw_list->bind_pts, i);
+        }
+    }
+    aos_printk("\n");
+}
+
+static void
+_dess_acl_sw_rule_dump(char *info, dess_acl_rule_t * sw_rule)
+{
+#ifdef DESS_ACL_DEBUG
+    a_uint32_t flt_idx, i;
+
+    aos_printk("\n%s", info);
+    for (flt_idx = 0; flt_idx < DESS_MAX_FILTER; flt_idx++)
+    {
+        aos_printk("\n%d software filter:", flt_idx);
+        aos_printk("\nact:");
+        for (i = 0; i < 3; i++)
+        {
+            aos_printk("%08x  ", sw_rule[flt_idx].filter.act[i]);
+        }
+
+        aos_printk("\nvlu:");
+        for (i = 0; i < 5; i++)
+        {
+            aos_printk("%08x  ", sw_rule[flt_idx].filter.vlu[i]);
+        }
+
+        aos_printk("\nmsk:");
+        for (i = 0; i < 5; i++)
+        {
+            aos_printk("%08x  ", sw_rule[flt_idx].filter.msk[i]);
+        }
+
+        aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d]",
+                   sw_rule[flt_idx].status,
+                   sw_rule[flt_idx].list_id, sw_rule[flt_idx].rule_id);
+
+        aos_printk("\n\n");
+    }
+#else
+    return;
+#endif
+}
+
+static dess_acl_list_t *
+_dess_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < DESS_MAX_FILTER; i++)
+    {
+        if ((ENT_USED & sw_list_ent[dev_id][i].status)
+                && (list_id == sw_list_ent[dev_id][i].list_id))
+        {
+            return &(sw_list_ent[dev_id][i]);
+        }
+    }
+    return NULL;
+}
+
+static sw_error_t
+_dess_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag)
+{
+#ifdef DESS_SW_ENTRY
+    hw_filter_t filter;
+
+    _dess_filter_up_to_sw(dev_id, &filter, flt_idx);
+
+    filter.msk[4] &= 0xfffffff8;
+    filter.msk[4] |= (flag & 0x7);
+
+    _dess_filter_down_to_hw(dev_id, &filter, flt_idx);
+
+    return SW_OK;
+#else
+#ifdef DESS_HW_ENTRY
+    hw_filter_t filter;
+
+    filter = sw_rule_ent[dev_id][flt_idx].filter;
+
+    filter.msk[4] &= 0xfffffff8;
+    filter.msk[4] |= (flag & 0x7);
+
+    _dess_filter_down_to_hw(dev_id, &filter, flt_idx);
+    return SW_OK;
+#else
+    sw_error_t rv;
+    a_uint32_t addr, data = 0;
+
+    /* read filter mask at first */
+    addr = DESS_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 10) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* get filter mask and modify it */
+    addr = DESS_RULE_FUNC_ADDR + 20;
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= 0xfffffff8;
+    data |= (flag & 0x7);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* write back filter mask */
+    addr = DESS_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+#endif
+#endif
+}
+
+static sw_error_t
+_dess_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t ports)
+{
+#ifdef DESS_SW_ENTRY
+    hw_filter_t filter;
+
+    _dess_filter_up_to_sw(dev_id, &filter, flt_idx);
+
+    filter.vlu[4] &= 0xffffff80;
+    filter.vlu[4] |= (ports & 0x7f);
+
+    _dess_filter_down_to_hw(dev_id, &filter, flt_idx);
+
+    return SW_OK;
+#else
+#ifdef DESS_HW_ENTRY
+    hw_filter_t filter;
+
+    filter = sw_rule_ent[dev_id][flt_idx].filter;
+
+    filter.vlu[4] &= 0xffffff80;
+    filter.vlu[4] |= (ports & 0x7f);
+
+    _dess_filter_down_to_hw(dev_id, &filter, flt_idx);
+
+    return SW_OK;
+#else
+    sw_error_t rv;
+    a_uint32_t addr, data;
+
+    /* read filter value at first */
+    addr = DESS_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (0x1 << 10) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* get filter value and modify it */
+    addr = DESS_RULE_FUNC_ADDR + 20;
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= 0xffffff80;
+    data |= (ports & 0x7f);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* write back filter value */
+    addr = DESS_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+#endif
+#endif
+}
+
+#ifndef DESS_SW_ENTRY
+#ifndef DESS_HW_ENTRY
+static sw_error_t
+_dess_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+                   a_uint32_t op)
+{
+    a_uint32_t i, addr, data, idx = 6;
+    sw_error_t rv;
+
+    if (DESS_FILTER_ACT_OP == op)
+    {
+        idx = 4;
+    }
+
+    for (i = 1; i < idx; i++)
+    {
+        addr = DESS_RULE_FUNC_ADDR + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(reg[i - 1])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    addr = DESS_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_dess_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+                  a_uint32_t op)
+{
+    a_uint32_t i, addr, data, idx = 6;
+    sw_error_t rv;
+
+    addr = DESS_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 10) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (DESS_FILTER_ACT_OP == op)
+    {
+        idx = 4;
+    }
+
+    for (i = 1; i < idx; i++)
+    {
+        addr = DESS_RULE_FUNC_ADDR + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(reg[i - 1])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+#endif
+#endif
+
+static sw_error_t
+_dess_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter,
+                        a_uint32_t flt_idx)
+{
+#ifdef DESS_SW_ENTRY
+    a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx;
+
+    aos_mem_copy(tbl, filter, sizeof (hw_filter_t));
+#else
+#ifdef DESS_HW_ENTRY
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    base = DESS_FILTER_ACT_ADDR + (flt_idx << 4);
+    for (i = 0; i < 3; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->act[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    base = DESS_FILTER_VLU_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->vlu[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    base = DESS_FILTER_MSK_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->msk[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+#else
+    sw_error_t rv;
+
+    rv = _dess_filter_write(dev_id, &(filter->act[0]), flt_idx,
+                            DESS_FILTER_ACT_OP);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_filter_write(dev_id, &(filter->vlu[0]), flt_idx,
+                            DESS_FILTER_VLU_OP);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_filter_write(dev_id, &(filter->msk[0]), flt_idx,
+                            DESS_FILTER_MSK_OP);
+    SW_RTN_ON_ERROR(rv);
+#endif
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter,
+                      a_uint32_t flt_idx)
+{
+#ifdef DESS_SW_ENTRY
+    a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx;
+
+    aos_mem_copy(filter, tbl, sizeof (hw_filter_t));
+#else
+#ifdef DESS_HW_ENTRY
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    base = DESS_FILTER_VLU_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->vlu[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    base = DESS_FILTER_MSK_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->msk[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    base = DESS_FILTER_ACT_ADDR + (flt_idx << 4);
+    for (i = 0; i < 3; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->act[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+#else
+    sw_error_t rv;
+
+    rv = _dess_filter_read(dev_id, &(filter->vlu[0]), flt_idx,
+                           DESS_FILTER_VLU_OP);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_filter_read(dev_id, &(filter->msk[0]), flt_idx,
+                           DESS_FILTER_MSK_OP);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_filter_read(dev_id, &(filter->act[0]), flt_idx,
+                           DESS_FILTER_ACT_OP);
+    SW_RTN_ON_ERROR(rv);
+#endif
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_list_insert(a_uint32_t dev_id, a_uint32_t * src_idx,
+                      a_uint32_t * dst_idx, dess_acl_rule_t * src_rule,
+                      dess_acl_rule_t * dst_rule)
+{
+    a_uint32_t i, data, rule_id, list_id, list_pri;
+
+    rule_id = 0;
+    list_id = src_rule[*src_idx].list_id;
+    list_pri = src_rule[*src_idx].list_pri;
+
+    for (i = *src_idx; i < DESS_MAX_FILTER; i++)
+    {
+        if (!(ENT_USED & src_rule[i].status))
+        {
+            continue; // was: break;
+        }
+
+        if (src_rule[i].list_id != list_id)
+        {
+            break;
+        }
+
+        SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data,
+                            src_rule[i].filter.msk[4]);
+        if (!data)
+        {
+            continue;
+        }
+
+        if (DESS_MAX_FILTER <= *dst_idx)
+        {
+            return SW_NO_RESOURCE;
+        }
+
+        if (ENT_USED & dst_rule[*dst_idx].status)
+        {
+            return SW_NO_RESOURCE;
+        }
+
+        SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_VALID, data,
+                            src_rule[i].filter.msk[4]);
+        if ((FLT_START == data) && (*dst_idx % 2))
+        {
+            if (*src_idx != i)
+            {
+                dst_rule[*dst_idx].src_flt_dis = src_rule[i].src_flt_dis;
+                dst_rule[*dst_idx].list_id = list_id;
+                dst_rule[*dst_idx].list_pri = list_pri;
+                dst_rule[*dst_idx].rule_id = rule_id - 1;
+                dst_rule[*dst_idx].status |= ENT_USED;
+            }
+
+            (*dst_idx)++;
+            if (DESS_MAX_FILTER <= *dst_idx)
+            {
+                return SW_NO_RESOURCE;
+            }
+
+            if (ENT_USED & dst_rule[*dst_idx].status)
+            {
+                return SW_NO_RESOURCE;
+            }
+        }
+
+        aos_mem_copy(&(dst_rule[*dst_idx].filter), &(src_rule[i].filter),
+                     sizeof (hw_filter_t));
+        dst_rule[*dst_idx].src_flt_dis = src_rule[i].src_flt_dis;
+        dst_rule[*dst_idx].list_id = list_id;
+        dst_rule[*dst_idx].list_pri = list_pri;
+        dst_rule[*dst_idx].rule_id = rule_id;
+        dst_rule[*dst_idx].status |= ENT_USED;
+        if (ENT_DEACTIVE & src_rule[i].status)
+        {
+            dst_rule[*dst_idx].status |= ENT_DEACTIVE;
+        }
+        (*dst_idx)++;
+
+        if ((FLT_END == data) && (*dst_idx % 2))
+        {
+            if (DESS_MAX_FILTER > *dst_idx)
+            {
+                dst_rule[*dst_idx].src_flt_dis = src_rule[i].src_flt_dis;
+                dst_rule[*dst_idx].list_id = list_id;
+                dst_rule[*dst_idx].list_pri = list_pri;
+                dst_rule[*dst_idx].rule_id = rule_id;
+                dst_rule[*dst_idx].status |= ENT_USED;
+                (*dst_idx)++;
+            }
+        }
+
+        if ((FLT_END == data) || (FLT_STARTEND == data))
+        {
+            rule_id++;
+        }
+    }
+
+    *src_idx = i;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_alloc(a_uint32_t dev_id, dess_acl_list_t * sw_list,
+                     a_uint32_t filter_nr)
+{
+    a_uint32_t free_flt_nr, load_idx, begin_idx, start_idx, end_idx, i;
+    a_uint32_t largest_nr, largest_idx;
+    sw_error_t rv;
+
+    /* calculate the proper location, [start_idx, end_idx) */
+    start_idx = 0;
+    end_idx = DESS_MAX_FILTER;
+    for (i = 0; i < DESS_MAX_FILTER; i++)
+    {
+        if (ENT_USED & sw_rule_ent[dev_id][i].status)
+        {
+            if (sw_rule_ent[dev_id][i].list_pri < sw_list->list_pri)
+            {
+                start_idx = i + 1;
+            }
+            else if (sw_rule_ent[dev_id][i].list_pri > sw_list->list_pri)
+            {
+                end_idx = i;
+                break;
+            }
+        }
+    }
+
+    /* find the larget free filters block */
+    largest_nr = 0;
+    largest_idx = 0;
+    free_flt_nr = 0;
+    begin_idx = start_idx;
+    for (i = start_idx; i < end_idx; i++)
+    {
+        if (!(ENT_USED & sw_rule_ent[dev_id][i].status))
+        {
+            free_flt_nr++;
+        }
+        else
+        {
+            if (free_flt_nr > largest_nr)
+            {
+                largest_nr = free_flt_nr;
+                largest_idx = begin_idx;
+            }
+            free_flt_nr = 0;
+            begin_idx = i + 1;
+        }
+    }
+
+    if (free_flt_nr > largest_nr)
+    {
+        largest_nr = free_flt_nr;
+        largest_idx = begin_idx;
+    }
+
+    if ((!largest_nr) || ((largest_nr + 1) < filter_nr))
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    for (i = 0; i < DESS_MAX_FILTER; i++)
+    {
+        if (ENT_USED & sw_rule_ent[dev_id][i].status)
+        {
+            aos_mem_copy(&(sw_rule_tmp[dev_id][i]), &(sw_rule_ent[dev_id][i]),
+                         sizeof (dess_acl_rule_t));
+        }
+    }
+
+    begin_idx = 0;
+    load_idx = largest_idx;
+    rv = _dess_acl_list_insert(dev_id, &begin_idx, &load_idx,
+                               hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]);
+    return rv;
+}
+
+static sw_error_t
+_dess_acl_rule_reorder(a_uint32_t dev_id, dess_acl_list_t * sw_list)
+{
+    a_uint32_t i, src_idx, dst_idx;
+    sw_error_t rv;
+
+    dst_idx = 0;
+    for (i = 0; i < DESS_MAX_FILTER;)
+    {
+        if (ENT_USED & sw_rule_ent[dev_id][i].status)
+        {
+            if (sw_rule_ent[dev_id][i].list_pri <= sw_list->list_pri)
+            {
+                rv = _dess_acl_list_insert(dev_id, &i, &dst_idx,
+                                           sw_rule_ent[dev_id],
+                                           sw_rule_tmp[dev_id]);
+                SW_RTN_ON_ERROR(rv);
+            }
+            else
+            {
+                break;
+            }
+        }
+        else
+        {
+            i++;
+        }
+    }
+
+    src_idx = 0;
+    rv = _dess_acl_list_insert(dev_id, &src_idx, &dst_idx, hw_rule_tmp[dev_id],
+                               sw_rule_tmp[dev_id]);
+    SW_RTN_ON_ERROR(rv);
+
+    for (; i < DESS_MAX_FILTER;)
+    {
+        if (ENT_USED & sw_rule_ent[dev_id][i].status)
+        {
+            rv = _dess_acl_list_insert(dev_id, &i, &dst_idx,
+                                       sw_rule_ent[dev_id],
+                                       sw_rule_tmp[dev_id]);
+            SW_RTN_ON_ERROR(rv);
+        }
+        else
+        {
+            i++;
+        }
+    }
+
+    return SW_OK;
+}
+
+static void
+_dess_acl_rule_sync(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flt_nr)
+{
+    a_uint32_t i, data;
+
+    for (i = flt_idx; i < (flt_idx + flt_nr); i++)
+    {
+        if (aos_mem_cmp
+                (&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]),
+                 sizeof (dess_acl_rule_t)))
+        {
+            SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data,
+                                sw_rule_tmp[dev_id][i].filter.msk[4]);
+            if (data)
+            {
+                _dess_filter_down_to_hw(dev_id,
+                                        &(sw_rule_tmp[dev_id][i].filter), i);
+            }
+            else
+            {
+                _dess_filter_valid_set(dev_id, i, 0);
+            }
+
+            aos_mem_copy(&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]),
+                         sizeof (dess_acl_rule_t));
+            _dess_acl_rule_src_filter_sts_set(dev_id, i,
+                                              !sw_rule_tmp[dev_id][i].src_flt_dis);
+        }
+    }
+}
+
+static sw_error_t
+_dess_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri)
+{
+    a_uint32_t i, loc = DESS_MAX_FILTER;
+    dess_acl_list_t *sw_list;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((DESS_MAX_LIST_ID < list_id) || (DESS_MAX_LIST_PRI < list_pri))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    for (i = 0; i < DESS_MAX_FILTER; i++)
+    {
+        sw_list = &(sw_list_ent[dev_id][i]);
+        if (ENT_USED & sw_list->status)
+        {
+            if (list_id == sw_list->list_id)
+            {
+                return SW_ALREADY_EXIST;
+            }
+        }
+        else
+        {
+            loc = i;
+        }
+    }
+
+    if (DESS_MAX_FILTER == loc)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    sw_list = &(sw_list_ent[dev_id][loc]);
+    aos_mem_zero(sw_list, sizeof (dess_acl_list_t));
+    sw_list->list_id = list_id;
+    sw_list->list_pri = list_pri;
+    sw_list->status |= ENT_USED;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    dess_acl_list_t *sw_list;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (DESS_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    sw_list = _dess_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (0 != sw_list->bind_pts)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (0 != sw_list->rule_nr)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    aos_mem_zero(sw_list, sizeof (dess_acl_list_t));
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+                   a_uint32_t rule_id, a_uint32_t rule_nr,
+                   fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+    dess_acl_list_t *sw_list;
+    dess_acl_rule_t *sw_rule;
+    a_uint32_t i, free_flt_nr, old_flt_nr, old_flt_idx, new_flt_nr, bind_pts;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (DESS_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if ((0 == rule_nr) || (NULL == rule))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    sw_list = _dess_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (rule_id != sw_list->rule_nr)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    old_flt_idx = 0;
+    old_flt_nr = 0;
+    free_flt_nr = 0;
+    aos_mem_zero(hw_rule_tmp[dev_id],
+                 DESS_HW_RULE_TMP_CNT * sizeof (dess_acl_rule_t));
+    aos_mem_zero(sw_rule_tmp[dev_id],
+                 DESS_MAX_FILTER * sizeof (dess_acl_rule_t));
+    for (i = 0; i < DESS_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i]);
+        if (ENT_USED & sw_rule->status)
+        {
+            if (sw_rule->list_id == sw_list->list_id)
+            {
+                aos_mem_copy(&(hw_rule_tmp[dev_id][old_flt_nr]), sw_rule,
+                             sizeof (dess_acl_rule_t));
+                if (!old_flt_nr)
+                {
+                    old_flt_idx = i;
+                }
+                old_flt_nr++;
+            }
+        }
+        else
+        {
+            free_flt_nr++;
+        }
+    }
+
+    if (!free_flt_nr)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    /* parse rule entry and alloc rule resource */
+    new_flt_nr = old_flt_nr;
+    for (i = 0; i < rule_nr; i++)
+    {
+        rv = _dess_acl_rule_sw_to_hw(dev_id, &rule[i], hw_rule_tmp[dev_id],
+                                     &new_flt_nr);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    if (free_flt_nr < (new_flt_nr - old_flt_nr))
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    for (i = old_flt_nr; i < new_flt_nr; i++)
+    {
+        hw_rule_tmp[dev_id][i].status |= ENT_USED;
+        hw_rule_tmp[dev_id][i].list_id = sw_list->list_id;
+        hw_rule_tmp[dev_id][i].list_pri = sw_list->list_pri;
+        bind_pts = sw_list->bind_pts;
+        SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, bind_pts,
+                            (hw_rule_tmp[dev_id][i].filter.vlu[4]));
+    }
+
+    for (i = 0; i < old_flt_nr; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][old_flt_idx + i]);
+        sw_rule->status &= (~ENT_USED);
+        sw_rule->status |= (ENT_TMP);
+    }
+
+    rv = _dess_acl_rule_alloc(dev_id, sw_list, new_flt_nr);
+    if (SW_OK != rv)
+    {
+        aos_mem_zero(sw_rule_tmp[dev_id],
+                     DESS_MAX_FILTER * sizeof (dess_acl_rule_t));
+        rv = _dess_acl_rule_reorder(dev_id, sw_list);
+    }
+
+    for (i = 0; i < old_flt_nr; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i + old_flt_idx]);
+        sw_rule->status |= (ENT_USED);
+        sw_rule->status &= (~ENT_TMP);
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    _dess_acl_rule_sync(dev_id, 0, DESS_MAX_FILTER);
+    sw_list->rule_nr += rule_nr;
+
+    _dess_acl_sw_rule_dump("sw rule after add", sw_rule_ent[dev_id]);
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+                      a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    dess_acl_rule_t *sw_rule;
+    dess_acl_list_t *sw_list;
+    a_uint32_t i, flt_idx = 0, src_idx, dst_idx, del_nr = 0, flt_nr = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (DESS_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    sw_list = _dess_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (sw_list->rule_nr < (rule_id + rule_nr))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(hw_rule_tmp[dev_id],
+                 DESS_HW_RULE_TMP_CNT * sizeof (dess_acl_rule_t));
+    aos_mem_zero(sw_rule_tmp[dev_id],
+                 DESS_MAX_FILTER * sizeof (dess_acl_rule_t));
+
+    for (i = 0; i < DESS_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i]);
+        if ((ENT_USED & sw_rule->status) && (sw_rule->list_id == list_id))
+        {
+            if (!flt_nr)
+            {
+                flt_idx = i;
+            }
+
+            if ((sw_rule->rule_id >= rule_id)
+                    && (sw_rule->rule_id < (rule_id + rule_nr)))
+            {
+                del_nr++;
+            }
+            else
+            {
+                aos_mem_copy(&(hw_rule_tmp[dev_id][flt_idx + flt_nr]), sw_rule,
+                             sizeof (dess_acl_rule_t));
+            }
+            flt_nr++;
+        }
+    }
+
+    if (!del_nr)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    _dess_acl_sw_rule_dump("hw rule before del", hw_rule_tmp[dev_id]);
+
+    for (i = 0; i < flt_nr; i++)
+    {
+        sw_rule = &(hw_rule_tmp[dev_id][flt_idx + i]);
+        if (ENT_USED & sw_rule->status)
+        {
+            break;
+        }
+    }
+
+    if (i != flt_nr)
+    {
+        src_idx = flt_idx + i;
+        dst_idx = flt_idx;
+        rv = _dess_acl_list_insert(dev_id, &src_idx, &dst_idx,
+                                   hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    _dess_acl_rule_sync(dev_id, flt_idx, flt_nr);
+    sw_list->rule_nr -= rule_nr;
+
+    _dess_acl_sw_rule_dump("sw rule after del", sw_rule_ent[dev_id]);
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+                     a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+    dess_acl_rule_t *sw_rule;
+    a_uint32_t flt_nr = 0, i;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (DESS_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    aos_mem_zero(hw_rule_tmp[dev_id],
+                 DESS_HW_RULE_TMP_CNT * sizeof (dess_acl_rule_t));
+    for (i = 0; i < DESS_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i]);
+        if (ENT_USED & sw_rule->status)
+        {
+            if ((sw_rule->list_id == list_id) && (sw_rule->rule_id == rule_id))
+            {
+                aos_mem_copy(&(hw_rule_tmp[dev_id][flt_nr]), sw_rule,
+                             sizeof (dess_acl_rule_t));
+                flt_nr++;
+            }
+        }
+    }
+
+    if (!flt_nr)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    aos_mem_zero(rule, sizeof (fal_acl_rule_t));
+    rv = _dess_acl_rule_hw_to_sw(dev_id, rule, hw_rule_tmp[dev_id], 0, flt_nr);
+    return rv;
+}
+
+static sw_error_t
+_dess_acl_rule_bind(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t ports)
+{
+    sw_error_t rv;
+    a_uint32_t i;
+    dess_acl_rule_t *sw_rule;
+
+    for (i = 0; i < DESS_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i]);
+
+        if ((ENT_USED & sw_rule->status)
+                && (list_id == sw_rule->list_id)
+                && (!(ENT_DEACTIVE & sw_rule->status)))
+        {
+            rv = _dess_filter_ports_bind(dev_id, i, ports);
+            SW_RTN_ON_ERROR(rv);
+
+            SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports,
+                                (sw_rule->filter.vlu[4]));
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                    fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                    a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+    a_uint32_t ports;
+    dess_acl_list_t *sw_list;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (DESS_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACL_DIREC_IN != direc)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    sw_list = _dess_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (FAL_ACL_BIND_PORT == obj_t)
+    {
+        ports = (sw_list->bind_pts) | (0x1 << obj_idx);
+    }
+    else if (FAL_ACL_BIND_PORTBITMAP == obj_t)
+    {
+        ports = (sw_list->bind_pts) | obj_idx;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    rv = _dess_acl_rule_bind(dev_id, list_id, ports);
+    SW_RTN_ON_ERROR(rv);
+
+    sw_list->bind_pts = ports;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                      fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                      a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+    a_uint32_t ports;
+    dess_acl_list_t *sw_list;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (DESS_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACL_DIREC_IN != direc)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    sw_list = _dess_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (FAL_ACL_BIND_PORT == obj_t)
+    {
+        ports = (sw_list->bind_pts) & (~(0x1UL << obj_idx));
+    }
+    else if (FAL_ACL_BIND_PORTBITMAP == obj_t)
+    {
+        ports = (sw_list->bind_pts) & (~obj_idx);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    rv = _dess_acl_rule_bind(dev_id, list_id, ports);
+    SW_RTN_ON_ERROR(rv);
+
+    sw_list->bind_pts = ports;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_acl_udf_type_t udf_type, a_uint32_t offset,
+                               a_uint32_t length)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (DESS_UDF_MAX_OFFSET < offset)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (DESS_UDF_MAX_OFFSET < length)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
+            || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type))
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    switch (udf_type)
+    {
+        case FAL_ACL_UDF_TYPE_L2:
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_OFFSET, offset, reg);
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_LENGTH, length, reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L3:
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_OFFSET, offset, reg);
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_LENGTH, length, reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L4:
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_OFFSET, offset, reg);
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_LENGTH, length, reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L2_SNAP:
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_OFFSET, offset, reg);
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_LENGTH, length, reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L3_PLUS:
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_OFFSET, offset, reg);
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_LENGTH, length, reg);
+            break;
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
+            || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type))
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL1, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL0, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_dess_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_acl_udf_type_t udf_type, a_uint32_t * offset,
+                               a_uint32_t * length)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
+            || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type))
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    switch (udf_type)
+    {
+        case FAL_ACL_UDF_TYPE_L2:
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_OFFSET, (*offset), reg);
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_LENGTH, (*length), reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L3:
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_OFFSET, (*offset), reg);
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_LENGTH, (*length), reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L4:
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_OFFSET, (*offset), reg);
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_LENGTH, (*length), reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L2_SNAP:
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_OFFSET, (*offset), reg);
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_LENGTH, (*length), reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L3_PLUS:
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_OFFSET, (*offset), reg);
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_LENGTH, (*length), reg);
+            break;
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+                      a_uint32_t rule_id, a_uint32_t rule_nr, a_bool_t active)
+{
+    sw_error_t rv;
+    a_uint32_t i, ports;
+    dess_acl_list_t *sw_list;
+    dess_acl_rule_t *sw_rule;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    sw_list = _dess_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (sw_list->rule_nr < (rule_id + rule_nr))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == active)
+    {
+        ports = (sw_list->bind_pts);
+    }
+    else
+    {
+        ports = 0;
+    }
+
+    for (i = 0; i < DESS_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i]);
+
+        if ((ENT_USED & sw_rule->status)
+                && (list_id == sw_rule->list_id)
+                && (rule_id <= sw_rule->rule_id)
+                && ((rule_id + rule_nr) > sw_rule->rule_id))
+        {
+            rv = _dess_filter_ports_bind(dev_id, i, ports);
+            SW_RTN_ON_ERROR(rv);
+
+            SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports,
+                                (sw_rule->filter.vlu[4]));
+
+            if (A_TRUE == active)
+            {
+                sw_rule->status &= (~ENT_DEACTIVE);
+            }
+            else
+            {
+                sw_rule->status |= (ENT_DEACTIVE);
+            }
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+                                  a_uint32_t rule_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, regIdx;
+    dess_acl_rule_t *sw_rule;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    sw_rule = &sw_rule_ent[dev_id][rule_id];
+    if (!(ENT_USED & sw_rule->status))
+    {
+        return SW_NOT_FOUND;
+    }
+
+    regIdx = rule_id >> 5;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ACL_FWD_SRC_FILTER_CTL0, regIdx,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        reg |= (0x1 << (rule_id & 0x1F));
+        sw_rule->src_flt_dis = 0;
+    }
+    else if (A_FALSE == enable)
+    {
+        reg &= ~(0x1 << (rule_id & 0x1F));
+        sw_rule->src_flt_dis = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ACL_FWD_SRC_FILTER_CTL0, regIdx,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_dess_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
+                                  a_uint32_t rule_id, a_bool_t* enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, regIdx;
+    dess_acl_rule_t *sw_rule;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    sw_rule = &sw_rule_ent[dev_id][rule_id];
+    if (!(ENT_USED & sw_rule->status))
+    {
+        return SW_NOT_FOUND;
+    }
+
+    regIdx = rule_id >> 5;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ACL_FWD_SRC_FILTER_CTL0, regIdx,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (reg & (0x1 << (rule_id & 0x1F)))
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+
+HSL_LOCAL sw_error_t
+dess_acl_list_dump(a_uint32_t dev_id)
+{
+    _dess_acl_list_dump(dev_id);
+    return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+dess_acl_rule_dump(a_uint32_t dev_id)
+{
+    a_uint32_t flt_idx, i;
+    sw_error_t rv;
+    hw_filter_t filter;
+
+    aos_printk("\ndess_acl_rule_dump:\n");
+
+    for (flt_idx = 0; flt_idx < DESS_MAX_FILTER; flt_idx++)
+    {
+        aos_mem_zero(&filter, sizeof (hw_filter_t));
+
+        rv = _dess_filter_up_to_sw(dev_id, &filter, flt_idx);
+        if (SW_OK != rv)
+        {
+            continue;
+        }
+
+        aos_printk("\n%d filter dump:", flt_idx);
+
+        aos_printk("\nhardware content:");
+        aos_printk("\nact:");
+        for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", filter.act[i]);
+        }
+
+        aos_printk("\nvlu:");
+        for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", filter.vlu[i]);
+        }
+
+        aos_printk("\nmsk:");
+        for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", filter.msk[i]);
+        }
+
+        aos_printk("\nsoftware content:");
+        aos_printk("\nact:");
+        for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", sw_rule_ent[dev_id][flt_idx].filter.act[i]);
+        }
+
+        aos_printk("\nvlu:");
+        for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", sw_rule_ent[dev_id][flt_idx].filter.vlu[i]);
+        }
+
+        aos_printk("\nmsk:");
+        for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", sw_rule_ent[dev_id][flt_idx].filter.msk[i]);
+        }
+
+        aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d] src_flt_dis[%02d]",
+                   sw_rule_ent[dev_id][flt_idx].status,
+                   sw_rule_ent[dev_id][flt_idx].list_id,
+                   sw_rule_ent[dev_id][flt_idx].rule_id,
+                   sw_rule_ent[dev_id][flt_idx].src_flt_dis);
+
+        aos_printk("\n\n");
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+dess_acl_reset(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    aos_mem_zero(sw_list_ent[dev_id],
+                 DESS_MAX_FILTER * sizeof (dess_acl_list_t));
+
+    aos_mem_zero(sw_rule_ent[dev_id],
+                 DESS_MAX_FILTER * sizeof (dess_acl_rule_t));
+
+    return SW_OK;
+}
+
+/**
+ * @brief Creat an acl list
+ * @details  Comments:
+  *     If the value of list_pri is more small then the priority is more high,
+ *     that means the list could be first matched.
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] list_pri acl list priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+dess_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_acl_list_creat(dev_id, list_id, list_pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Destroy an acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_acl_list_destroy(dev_id, list_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one rule or more rules to an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this adding operation in list
+ * @param[in] rule_nr rule number of this adding operation
+ * @param[in] rule rules content of this adding operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+dess_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+                  a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one rule or more rules from an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[in] rule_nr rule number of this deleteing operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+dess_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+                     a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_acl_rule_delete(dev_id, list_id, rule_id, rule_nr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Query one particular rule in a particular acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[out] rule rule content of this operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+dess_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+                    a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_acl_rule_query(dev_id, list_id, rule_id, rule);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+a_uint32_t
+dess_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id)
+{
+    a_uint32_t i, pos=0;
+    dess_acl_rule_t *sw_rule;
+
+    for (i = 0; i < DESS_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[0][i]);
+
+        if ((ENT_USED & sw_rule->status)
+                && (list_id == sw_rule->list_id) && (sw_rule->rule_id == rule_id)
+                && (!(ENT_DEACTIVE & sw_rule->status)))
+        {
+            pos = i;
+            break;
+
+        }
+    }
+
+    return pos;
+}
+
+
+sw_error_t
+dess_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act)
+{
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (DESS_MAX_LIST_ID < pos)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    sw_rule_ent[dev_id][pos].filter.act[1] = act[1];
+    sw_rule_ent[dev_id][pos].filter.act[2] = act[2];
+
+    sw_rule_tmp[dev_id][pos].filter.act[1] = act[1];
+    sw_rule_tmp[dev_id][pos].filter.act[2] = act[2];
+
+    hw_rule_tmp[dev_id][pos].filter.act[1] = act[1];
+    hw_rule_tmp[dev_id][pos].filter.act[2] = act[2];
+
+
+    return SW_OK;
+}
+
+/**
+ * @brief Bind an acl list to a particular object
+ * @details  Comments:
+ *    If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this binding operation
+ * @param[in] obj_t object type of this binding operation
+ * @param[in] obj_idx object index of this binding operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+dess_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                   fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                   a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Unbind an acl list from a particular object
+ * @details  Comments:
+  *    If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this unbinding operation
+ * @param[in] obj_t object type of this unbinding operation
+ * @param[in] obj_idx object index of this unbinding operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+dess_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                     fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                     a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+dess_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_acl_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_acl_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set user define fields profile on a particular port
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] udf_type udf type
+ * @param[in] offset udf offset
+ * @param[in] length udf length
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_acl_udf_type_t udf_type, a_uint32_t offset,
+                              a_uint32_t length)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_acl_port_udf_profile_set(dev_id, port_id, udf_type, offset,
+                                        length);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get user define fields profile on a particular port
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] udf_type udf type
+ * @param[out] offset udf offset
+ * @param[out] length udf length
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_acl_udf_type_t udf_type, a_uint32_t * offset,
+                              a_uint32_t * length)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_acl_port_udf_profile_get(dev_id, port_id, udf_type, offset,
+                                        length);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Active one or more rules in an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] rule_nr rule number of this deactive operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+                     a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_TRUE);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Deactive one or more rules in an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] rule_nr rule number of this deactive operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+                       a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_FALSE);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief enable acl forward source filter of one rule.
+ * @param[in] dev_id device id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+                                 a_uint32_t rule_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_acl_rule_src_filter_sts_set(dev_id, rule_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief get the status of acl forward source filter of one rule.
+ * @param[in] dev_id device id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
+                                 a_uint32_t rule_id, a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_acl_rule_src_filter_sts_get(dev_id, rule_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+
+sw_error_t
+dess_acl_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    sw_list_ent[dev_id] =
+        (dess_acl_list_t *) aos_mem_alloc(DESS_MAX_FILTER *
+                                          sizeof (dess_acl_list_t));
+    if (NULL == sw_list_ent[dev_id])
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(sw_list_ent[dev_id],
+                 DESS_MAX_FILTER * sizeof (dess_acl_list_t));
+
+    sw_rule_ent[dev_id] =
+        (dess_acl_rule_t *) aos_mem_alloc(DESS_MAX_FILTER *
+                                          sizeof (dess_acl_rule_t));
+    if (NULL == sw_rule_ent[dev_id])
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(sw_rule_ent[dev_id],
+                 DESS_MAX_FILTER * sizeof (dess_acl_rule_t));
+
+    hw_rule_tmp[dev_id] =
+        (dess_acl_rule_t *) aos_mem_alloc(DESS_HW_RULE_TMP_CNT *
+                                          sizeof (dess_acl_rule_t));
+    if (NULL == hw_rule_tmp[dev_id])
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    sw_rule_tmp[dev_id] =
+        (dess_acl_rule_t *) aos_mem_alloc(DESS_MAX_FILTER *
+                                          sizeof (dess_acl_rule_t));
+    if (NULL == sw_rule_tmp[dev_id])
+    {
+        return SW_NO_RESOURCE;
+    }
+#ifdef DESS_SW_ENTRY
+    sw_filter_mem = aos_mem_alloc(DESS_MAX_FILTER * sizeof (hw_filter_t));
+    if (NULL == sw_filter_mem)
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(sw_filter_mem, DESS_MAX_FILTER * sizeof (hw_filter_t));
+#endif
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->acl_list_creat = dess_acl_list_creat;
+        p_api->acl_list_destroy = dess_acl_list_destroy;
+        p_api->acl_list_bind = dess_acl_list_bind;
+        p_api->acl_list_unbind = dess_acl_list_unbind;
+        p_api->acl_rule_add = dess_acl_rule_add;
+        p_api->acl_rule_delete = dess_acl_rule_delete;
+        p_api->acl_rule_query = dess_acl_rule_query;
+        p_api->acl_status_set = dess_acl_status_set;
+        p_api->acl_status_get = dess_acl_status_get;
+        p_api->acl_list_dump = dess_acl_list_dump;
+        p_api->acl_rule_dump = dess_acl_rule_dump;
+        p_api->acl_port_udf_profile_set = dess_acl_port_udf_profile_set;
+        p_api->acl_port_udf_profile_get = dess_acl_port_udf_profile_get;
+        p_api->acl_rule_active = dess_acl_rule_active;
+        p_api->acl_rule_deactive = dess_acl_rule_deactive;
+        p_api->acl_rule_src_filter_sts_set = dess_acl_rule_src_filter_sts_set;
+        p_api->acl_rule_src_filter_sts_get = dess_acl_rule_src_filter_sts_get;
+        p_api->acl_rule_get_offset = dess_acl_rule_get_offset;
+        p_api->acl_rule_sync_multi_portmap = dess_acl_rule_sync_multi_portmap;
+    }
+#endif
+
+    return SW_OK;
+}
+
+sw_error_t
+dess_acl_cleanup(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (NULL != sw_list_ent[dev_id])
+    {
+        aos_mem_free(sw_list_ent[dev_id]);
+    }
+
+    if (NULL != sw_rule_ent[dev_id])
+    {
+        aos_mem_free(sw_rule_ent[dev_id]);
+    }
+
+    if (NULL != hw_rule_tmp[dev_id])
+    {
+        aos_mem_free(hw_rule_tmp[dev_id]);
+    }
+
+    if (NULL != sw_rule_tmp[dev_id])
+    {
+        aos_mem_free(sw_rule_tmp[dev_id]);
+    }
+#ifdef DESS_SW_ENTRY
+    if (NULL != sw_filter_mem)
+    {
+        aos_mem_free(sw_filter_mem);
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/dess/dess_acl_parse.c b/qca-ssdk/src/hsl/dess/dess_acl_parse.c
new file mode 100755
index 0000000..f38219b
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_acl_parse.c
@@ -0,0 +1,2452 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+#include "dess_acl.h"
+#include "dess_reg.h"
+#include "dess_acl_prv.h"
+
+#define DAH  0x1
+#define SAH  0x2
+#define TAG  0x4
+#define STAG 0x8
+#define CTAG 0x10
+
+typedef sw_error_t(*parse_func_t) (fal_acl_rule_t * sw,
+                                   hw_filter_t * hw_filter_snap,
+                                   a_bool_t * b_care);
+
+static a_bool_t
+_dess_acl_zero_addr(const fal_mac_addr_t addr)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 6; i++)
+    {
+        if (addr.uc[i])
+        {
+            return A_FALSE;
+        }
+    }
+    return A_TRUE;
+}
+
+static a_bool_t
+_dess_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask,
+                     a_uint32_t chkvlu)
+{
+    if (FAL_ACL_FIELD_MASK == op)
+    {
+        if (0 == mask)
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_RANGE == op)
+    {
+        if ((0 == val) && (chkvlu == mask))
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_LE == op)
+    {
+        if (chkvlu == val)
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_GE == op)
+    {
+        if (0 == val)
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_NE == op)
+    {
+        return A_TRUE;
+    }
+
+    return A_TRUE;
+}
+
+static sw_error_t
+_dess_acl_rule_bmac_parse(fal_acl_rule_t * sw,
+                          hw_filter_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, DESS_MAC_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+    {
+        if (A_TRUE != _dess_acl_zero_addr(sw->dest_mac_mask))
+        {
+            *b_care = A_TRUE;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+        }
+
+        FIELD_SET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]);
+        FIELD_SET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]);
+        FIELD_SET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]);
+        FIELD_SET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]);
+        FIELD_SET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]);
+        FIELD_SET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]);
+
+        FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]);
+        FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]);
+        FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]);
+        FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]);
+        FIELD_SET_MASK(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]);
+        FIELD_SET_MASK(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+    {
+        if (A_TRUE != _dess_acl_zero_addr(sw->src_mac_mask))
+        {
+            *b_care = A_TRUE;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+        }
+
+        FIELD_SET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+        FIELD_SET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+        FIELD_SET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]);
+        FIELD_SET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]);
+        FIELD_SET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]);
+        FIELD_SET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+
+        FIELD_SET_MASK(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+        FIELD_SET_MASK(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+        FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]);
+        FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]);
+        FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]);
+        FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+    {
+        if (0x0 != sw->ethtype_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ethtype_val &= sw->ethtype_mask;
+        FIELD_SET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+        FIELD_SET_MASK(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED))
+    {
+        if (0x0 != sw->tagged_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->tagged_val &= sw->tagged_mask;
+        FIELD_SET_MASK(MAC_RUL_M4, TAGGEDV, sw->tagged_val);
+        FIELD_SET_MASK(MAC_RUL_M4, TAGGEDM, sw->tagged_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP))
+    {
+        if (0x0 != sw->up_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->up_val &= sw->up_mask;
+        FIELD_SET(MAC_RUL_V3, VLANPRIV, sw->up_val);
+        FIELD_SET_MASK(MAC_RUL_M3, VLANPRIM, sw->up_mask);
+    }
+
+    FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->vid_op)
+                && (FAL_ACL_FIELD_RANGE != sw->vid_op)
+                && (FAL_ACL_FIELD_LE != sw->vid_op)
+                && (FAL_ACL_FIELD_GE != sw->vid_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_TRUE ==
+                _dess_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask,
+                                     0xfff))
+        {
+            *b_care = A_TRUE;
+        }
+
+        FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 0);
+        if (FAL_ACL_FIELD_MASK == sw->vid_op)
+        {
+            sw->vid_val &= sw->vid_mask;
+            FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+            FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask);
+            FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 1);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->vid_op)
+        {
+            FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+            FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->vid_op)
+        {
+            FIELD_SET(MAC_RUL_V3, VLANIDV, 0);
+            FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_val);
+        }
+        else
+        {
+            FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+            FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, 0xfff);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI))
+    {
+        if (0x0 != sw->cfi_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->cfi_val &= sw->cfi_mask;
+        FIELD_SET(MAC_RUL_V3, VLANCFIV, sw->cfi_val);
+        FIELD_SET_MASK(MAC_RUL_M3, VLANCFIM, sw->cfi_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_ehmac_parse(fal_acl_rule_t * sw,
+                           hw_filter_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i;
+    a_bool_t da_h = A_FALSE, sa_h = A_FALSE;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, DESS_EHMAC_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+    {
+        for (i = 0; i < 3; i++)
+        {
+            if (sw->dest_mac_mask.uc[i])
+            {
+                da_h = A_TRUE;
+                break;
+            }
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+    {
+        for (i = 0; i < 3; i++)
+        {
+            if (sw->src_mac_mask.uc[i])
+            {
+                sa_h = A_TRUE;
+                break;
+            }
+        }
+    }
+
+    /* if sa_h and da_h both are true need't process mac address fileds */
+    if ((A_TRUE == da_h) && ((A_TRUE == sa_h)))
+    {
+        da_h = A_FALSE;
+        sa_h = A_FALSE;
+    }
+
+    if (A_TRUE == da_h)
+    {
+        FIELD_SET(EHMAC_RUL_V3, DA_EN, 1);
+
+        if (A_TRUE != _dess_acl_zero_addr(sw->dest_mac_mask))
+        {
+            *b_care = A_TRUE;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+        }
+
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]);
+        FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]);
+        FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]);
+
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]);
+        FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]);
+        FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]);
+
+        if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+        {
+            if (A_TRUE != _dess_acl_zero_addr(sw->src_mac_mask))
+            {
+                *b_care = A_TRUE;
+            }
+
+            for (i = 0; i < 6; i++)
+            {
+                sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+            }
+
+            FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+            FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+            FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+
+            FIELD_SET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+            FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+            FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+        }
+    }
+
+    if (A_TRUE == sa_h)
+    {
+        if (A_TRUE != _dess_acl_zero_addr(sw->src_mac_mask))
+        {
+            *b_care = A_TRUE;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+        }
+
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->src_mac_val.uc[2]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->src_mac_val.uc[3]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->src_mac_val.uc[4]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->src_mac_val.uc[5]);
+        FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->src_mac_val.uc[0]);
+        FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->src_mac_val.uc[1]);
+
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE2, sw->src_mac_mask.uc[2]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE3, sw->src_mac_mask.uc[3]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE4, sw->src_mac_mask.uc[4]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE5, sw->src_mac_mask.uc[5]);
+        FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE0, sw->src_mac_mask.uc[0]);
+        FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE1, sw->src_mac_mask.uc[1]);
+
+        if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+        {
+            if (A_TRUE != _dess_acl_zero_addr(sw->dest_mac_mask))
+            {
+                *b_care = A_TRUE;
+            }
+
+            for (i = 0; i < 6; i++)
+            {
+                sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+            }
+
+            FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]);
+            FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]);
+            FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]);
+
+            FIELD_SET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]);
+            FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]);
+            FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+    {
+        if (0x0 != sw->ethtype_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ethtype_val &= sw->ethtype_mask;
+        FIELD_SET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+        FIELD_SET_MASK(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+    }
+
+    /* Process Stag Fields */
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED))
+    {
+        if (0x0 != sw->stagged_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->stagged_val &= sw->stagged_mask;
+        FIELD_SET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val);
+        FIELD_SET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask);
+    }
+
+    FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->stag_vid_op)
+                && (FAL_ACL_FIELD_RANGE != sw->stag_vid_op)
+                && (FAL_ACL_FIELD_LE != sw->stag_vid_op)
+                && (FAL_ACL_FIELD_GE != sw->stag_vid_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_TRUE ==
+                _dess_acl_field_care(sw->stag_vid_op, sw->stag_vid_val,
+                                     sw->stag_vid_mask, 0xfff))
+        {
+            *b_care = A_TRUE;
+        }
+
+        FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 0);
+        if (FAL_ACL_FIELD_MASK == sw->stag_vid_op)
+        {
+            sw->stag_vid_val &= sw->stag_vid_mask;
+            FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+            FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask);
+            FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1);
+
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->stag_vid_op)
+        {
+            FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+            FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask);
+
+        }
+        else if (FAL_ACL_FIELD_LE == sw->stag_vid_op)
+        {
+            FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, 0);
+            FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_val);
+
+        }
+        else
+        {
+            FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+            FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, 0xfff);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI))
+    {
+        if (0x0 != sw->stag_pri_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->stag_pri_val &= sw->stag_pri_mask;
+        FIELD_SET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val);
+        FIELD_SET_MASK(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI))
+    {
+        if (0x0 != sw->stag_dei_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->stag_dei_val &= sw->stag_dei_mask;
+        FIELD_SET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val);
+        FIELD_SET_MASK(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask);
+    }
+
+    /* Process Ctag Fields */
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED))
+    {
+        if (0x0 != sw->ctagged_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ctagged_val &= sw->ctagged_mask;
+        FIELD_SET_MASK(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val);
+        FIELD_SET_MASK(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask);
+    }
+
+    FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->ctag_vid_op)
+                && (FAL_ACL_FIELD_RANGE != sw->ctag_vid_op)
+                && (FAL_ACL_FIELD_LE != sw->ctag_vid_op)
+                && (FAL_ACL_FIELD_GE != sw->ctag_vid_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_TRUE ==
+                _dess_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val,
+                                     sw->ctag_vid_mask, 0xfff))
+        {
+            *b_care = A_TRUE;
+        }
+
+        FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 0);
+        if (FAL_ACL_FIELD_MASK == sw->ctag_vid_op)
+        {
+            sw->ctag_vid_val &= sw->ctag_vid_mask;
+            FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+            FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8));
+            FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask);
+            FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8));
+            FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 1);
+
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->ctag_vid_op)
+        {
+            FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+            FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8));
+            FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask);
+            FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8));
+
+        }
+        else if (FAL_ACL_FIELD_LE == sw->ctag_vid_op)
+        {
+            FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, 0);
+            FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, 0);
+            FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_val);
+            FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_val >> 8));
+
+        }
+        else
+        {
+            FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+            FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8));
+            FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, 0xff);
+            FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, 0xf);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI))
+    {
+        if (0x0 != sw->ctag_pri_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ctag_pri_val &= sw->ctag_pri_mask;
+        FIELD_SET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val);
+        FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI))
+    {
+        if (0x0 != sw->ctag_cfi_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ctag_cfi_val &= sw->ctag_cfi_mask;
+        FIELD_SET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val);
+        FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static void
+_dess_acl_rule_mac_preparse(fal_acl_rule_t * sw, a_bool_t * b_mac,
+                            a_bool_t * eh_mac)
+{
+    a_uint32_t bm = 0, i, tmp;
+
+    *b_mac = A_FALSE;
+    *eh_mac = A_FALSE;
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+    {
+        for (i = 0; i < 3; i++)
+        {
+            if (sw->dest_mac_mask.uc[i])
+            {
+                bm |= DAH;
+                break;
+            }
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+    {
+        for (i = 0; i < 3; i++)
+        {
+            if (sw->src_mac_mask.uc[i])
+            {
+                bm |= SAH;
+                break;
+            }
+        }
+    }
+
+    tmp = 0;
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED))
+    {
+        tmp |= ((sw->tagged_mask & 0x1) << 16);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP))
+    {
+        tmp |= ((sw->up_mask & 0x7) << 13);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI))
+    {
+        tmp |= ((sw->cfi_mask & 0x1) << 12);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID))
+    {
+        if (A_TRUE ==
+                _dess_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask,
+                                     0xfff))
+        {
+            tmp |= 0xfff;
+        }
+    }
+    if (tmp)
+    {
+        bm |= TAG;
+    }
+
+    tmp = 0;
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED))
+    {
+        tmp |= ((sw->stagged_mask & 0x1) << 16);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI))
+    {
+        tmp |= ((sw->stag_pri_mask & 0x7) << 13);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI))
+    {
+        tmp |= ((sw->stag_dei_mask & 0x1) << 12);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID))
+    {
+        if (A_TRUE ==
+                _dess_acl_field_care(sw->stag_vid_op, sw->stag_vid_val,
+                                     sw->stag_vid_mask, 0xfff))
+        {
+            tmp |= 0xfff;
+        }
+    }
+    if (tmp)
+    {
+        bm |= STAG;
+    }
+
+    tmp = 0;
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED))
+    {
+        tmp |= ((sw->ctagged_mask & 0x1) << 16);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI))
+    {
+        tmp |= ((sw->ctag_pri_mask & 0x7) << 13);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI))
+    {
+        tmp |= ((sw->ctag_cfi_mask & 0x1) << 12);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID))
+    {
+        if (A_TRUE ==
+                _dess_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val,
+                                     sw->ctag_vid_mask, 0xfff))
+        {
+            tmp |= 0xfff;
+        }
+    }
+    if (tmp)
+    {
+        bm |= CTAG;
+    }
+
+    if ((bm & CTAG) || (bm & STAG))
+    {
+        *eh_mac = A_TRUE;
+    }
+
+    if ((bm & TAG) || ((bm & DAH) && (bm & SAH)))
+    {
+        *b_mac = A_TRUE;
+    }
+}
+
+static sw_error_t
+_dess_acl_rule_ip4_parse(fal_acl_rule_t * sw,
+                         hw_filter_t * hw, a_bool_t * b_care)
+{
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, DESS_IP4_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+    {
+        if (0x0 != sw->ip_dscp_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_dscp_val &= sw->ip_dscp_mask;
+        FIELD_SET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val);
+        FIELD_SET_MASK(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+    {
+        if (0x0 != sw->ip_proto_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_proto_val &= sw->ip_proto_mask;
+        FIELD_SET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val);
+        FIELD_SET_MASK(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_SIP))
+    {
+        if (0x0 != sw->src_ip4_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        sw->src_ip4_val &= sw->src_ip4_mask;
+        hw->vlu[1] = sw->src_ip4_val;
+        hw->msk[1] = sw->src_ip4_mask;
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_DIP))
+    {
+        if (0x0 != sw->dest_ip4_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        sw->dest_ip4_val &= sw->dest_ip4_mask;
+        hw->vlu[0] = sw->dest_ip4_val;
+        hw->msk[0] = sw->dest_ip4_mask;
+    }
+
+    if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+            && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+                || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _dess_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+                                     sw->src_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+            {
+                sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+                sw->src_l4port_val = 0;
+                sw->src_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+
+        FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 0);
+        if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+        {
+            sw->src_l4port_val &= sw->src_l4port_mask;
+            FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 1);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+        {
+            FIELD_SET(IP4_RUL_V3, IP4SPORTV, 0);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_val);
+        }
+        else
+        {
+            FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, 0xffff);
+        }
+    }
+
+    FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _dess_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+                                     sw->dest_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+            {
+                sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+                sw->dest_l4port_val = 0;
+                sw->dest_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+
+        FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 0);
+        if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+        {
+            sw->dest_l4port_val &= sw->dest_l4port_mask;
+            FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 1);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+        {
+            FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+        {
+            FIELD_SET(IP4_RUL_V2, IP4DPORTV, 0);
+            FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_val);
+        }
+        else
+        {
+            FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, 0xffff);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+    {
+        if (0x0 != sw->icmp_type_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        FIELD_SET(IP4_RUL_V3, ICMP_EN, 1);
+
+        sw->icmp_type_val &= sw->icmp_type_mask;
+        FIELD_SET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val);
+        FIELD_SET_MASK(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))
+    {
+        if (0x0 != sw->icmp_code_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        FIELD_SET(IP4_RUL_V3, ICMP_EN, 1);
+
+        sw->icmp_code_val &= sw->icmp_code_mask;
+        FIELD_SET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val);
+        FIELD_SET_MASK(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG))
+    {
+        if (0x0 != sw->tcp_flag_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->tcp_flag_val &= sw->tcp_flag_mask;
+        FIELD_SET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val);
+        FIELD_SET_MASK(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_RIPV1))
+    {
+        if (0x0 != sw->ripv1_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ripv1_val &= sw->ripv1_mask;
+        FIELD_SET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val);
+        FIELD_SET_MASK(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV4))
+    {
+        if (0x0 != sw->dhcpv4_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->dhcpv4_val &= sw->dhcpv4_mask;
+        FIELD_SET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val);
+        FIELD_SET_MASK(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_ip6r1_parse(fal_acl_rule_t * sw,
+                           hw_filter_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, DESS_IP6R1_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_DIP))
+    {
+        for (i = 0; i < 4; i++)
+        {
+            if (0x0 != sw->dest_ip6_mask.ul[i])
+            {
+                *b_care = A_TRUE;
+            }
+
+            sw->dest_ip6_val.ul[3 - i] &= sw->dest_ip6_mask.ul[3 - i];
+            hw->vlu[i] = sw->dest_ip6_val.ul[3 - i];
+            hw->msk[i] = sw->dest_ip6_mask.ul[3 - i];
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_ip6r2_parse(fal_acl_rule_t * sw,
+                           hw_filter_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, DESS_IP6R2_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_SIP))
+    {
+        for (i = 0; i < 4; i++)
+        {
+            if (0x0 != sw->src_ip6_mask.ul[i])
+            {
+                *b_care = A_TRUE;
+            }
+
+            sw->src_ip6_val.ul[3 - i] &= sw->src_ip6_mask.ul[3 - i];
+            hw->vlu[i] = sw->src_ip6_val.ul[3 - i];
+            hw->msk[i] = sw->src_ip6_mask.ul[3 - i];
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_ip6r3_parse(fal_acl_rule_t * sw,
+                           hw_filter_t * hw, a_bool_t * b_care)
+{
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, DESS_IP6R3_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL))
+    {
+        if (0x0 != sw->ip6_lable_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip6_lable_val &= sw->ip6_lable_mask;
+        FIELD_SET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val);
+        FIELD_SET_MASK(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask);
+
+        FIELD_SET(IP6_RUL3_V2, IP6LABEL2V, (sw->ip6_lable_val >> 16));
+        FIELD_SET_MASK(IP6_RUL3_M2, IP6LABEL2M, (sw->ip6_lable_mask >> 16));
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+    {
+        if (0x0 != sw->ip_proto_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_proto_val &= sw->ip_proto_mask;
+        FIELD_SET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val);
+        FIELD_SET_MASK(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+    {
+        if (0x0 != sw->ip_dscp_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_dscp_val &= sw->ip_dscp_mask;
+        FIELD_SET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val);
+        FIELD_SET_MASK(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask);
+    }
+
+    if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+            && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+                || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _dess_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+                                     sw->src_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+            {
+                sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+                sw->src_l4port_val = 0;
+                sw->src_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 0);
+        if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+        {
+            sw->src_l4port_val &= sw->src_l4port_mask;
+            FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 1);
+
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask);
+
+        }
+        else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+        {
+            FIELD_SET(IP6_RUL3_V3, IP6SPORTV, 0);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_val);
+
+        }
+        else
+        {
+            FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, 0xffff);
+        }
+    }
+
+    FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _dess_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+                                     sw->dest_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+            {
+                sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+                sw->dest_l4port_val = 0;
+                sw->dest_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 0);
+        if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+        {
+            sw->dest_l4port_val &= sw->dest_l4port_mask;
+            FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 1);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+        {
+            FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+        {
+            FIELD_SET(IP6_RUL3_V2, IP6DPORTV, 0);
+            FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_val);
+        }
+        else
+        {
+            FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, 0xffff);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+    {
+        if (0x0 != sw->icmp_type_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1);
+
+        sw->icmp_type_val &= sw->icmp_type_mask;
+        FIELD_SET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val);
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))
+    {
+        if (0x0 != sw->icmp_code_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1);
+
+        sw->icmp_code_val &= sw->icmp_code_mask;
+        FIELD_SET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val);
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG))
+    {
+        if (0x0 != sw->tcp_flag_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->tcp_flag_val &= sw->tcp_flag_mask;
+        FIELD_SET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val);
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV6))
+    {
+        if (0x0 != sw->dhcpv6_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->dhcpv6_val &= sw->dhcpv6_mask;
+        FIELD_SET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val);
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_udf_parse(fal_acl_rule_t * sw,
+                         hw_filter_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, DESS_UDF_FILTER);
+
+    if (!FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_UDF))
+    {
+        if (FAL_ACL_RULE_UDF == sw->rule_type)
+        {
+            if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+            {
+                FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+            }
+            *b_care = A_TRUE;
+        }
+        return SW_OK;
+    }
+
+    if (DESS_MAX_UDF_LENGTH < sw->udf_len)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    *b_care = A_TRUE;
+    for (i = 0; i < sw->udf_len; i++)
+    {
+        hw->vlu[3 - i / 4] |=
+            ((sw->udf_mask[i] & sw->udf_val[i]) << (24 - 8 * (i % 4)));
+        hw->msk[3 - i / 4] |= ((sw->udf_mask[i]) << (24 - 8 * (i % 4)));
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw,
+                       hw_filter_t * hw)
+{
+    fal_pbmp_t des_pts;
+
+    aos_mem_zero(&(hw->act[0]), sizeof (hw->act));
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, TRIGGER_INTR, 1);
+    }
+
+    /* FAL_ACL_ACTION_PERMIT need't process */
+
+    if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU))
+            && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU)))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x3);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_DENY))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x7);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MIRROR))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, MIRR_EN, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, DES_PORT_EN, 1);
+
+        des_pts = (sw->ports >> 3) & 0xf;
+        FIELD_SET_ACTION(ACL_RSLT2, DES_PORT1, des_pts);
+
+        des_pts = sw->ports & 0x7;
+        FIELD_SET_ACTION(ACL_RSLT1, DES_PORT0, des_pts);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_UP))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, PRI_QU_EN, 1);
+        FIELD_SET_ACTION(ACL_RSLT1, PRI_QU, sw->queue);
+    }
+
+    if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+            || (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN)))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, DSCPV, sw->dscp);
+        FIELD_SET_ACTION(ACL_RSLT1, DSCP_REMAP, 1);
+    }
+
+    FIELD_SET_ACTION(ACL_RSLT0, STAGVID, sw->stag_vid);
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, TRANS_SVID_CHG, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI))
+    {
+        FIELD_SET_ACTION(ACL_RSLT0, STAGPRI, sw->stag_pri);
+        FIELD_SET_ACTION(ACL_RSLT1, STAG_PRI_REMAP, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI))
+    {
+        FIELD_SET_ACTION(ACL_RSLT0, STAGDEI, sw->stag_dei);
+        FIELD_SET_ACTION(ACL_RSLT1, STAG_DEI_CHG, 1);
+    }
+
+    FIELD_SET_ACTION(ACL_RSLT0, CTAGVID, sw->ctag_vid);
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, TRANS_CVID_CHG, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI))
+    {
+        FIELD_SET_ACTION(ACL_RSLT0, CTAGPRI, sw->ctag_pri);
+        FIELD_SET_ACTION(ACL_RSLT1, CTAG_PRI_REMAP, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI))
+    {
+        FIELD_SET_ACTION(ACL_RSLT0, CTAGCFI, sw->ctag_cfi);
+        FIELD_SET_ACTION(ACL_RSLT1, CTAG_CFI_CHG, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, LOOK_VID_CHG, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICER_EN))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, POLICER_PTR, sw->policer_ptr);
+        FIELD_SET_ACTION(ACL_RSLT2, POLICER_EN, 1);
+    }
+
+    if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN))
+            && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN)))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR, sw->arp_ptr);
+        FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR_EN, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr);
+        FIELD_SET_ACTION(ACL_RSLT1, WCMP_EN, 1);
+        FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR_EN, 1);
+    }
+
+    FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x0);
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN))
+    {
+        if (FAL_ACL_POLICY_ROUTE == sw->policy_fwd)
+        {
+            return SW_NOT_SUPPORTED;
+        }
+        else if (FAL_ACL_POLICY_SNAT == sw->policy_fwd)
+        {
+            FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x1);
+        }
+        else if (FAL_ACL_POLICY_DNAT == sw->policy_fwd)
+        {
+            FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x2);
+        }
+        else if (FAL_ACL_POLICY_RESERVE == sw->policy_fwd)
+        {
+            FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x3);
+        }
+        else
+        {
+            return SW_BAD_PARAM;
+        }
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, EG_BYPASS, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, TRIGGER_INTR, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_bmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t mask_en;
+
+    /* destnation mac address */
+    FIELD_GET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]);
+    FIELD_GET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]);
+    FIELD_GET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]);
+    FIELD_GET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]);
+    FIELD_GET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]);
+    FIELD_GET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]);
+
+    FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]);
+    FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]);
+    FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]);
+    FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]);
+    FIELD_GET_MASK(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]);
+    FIELD_GET_MASK(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]);
+    if (A_FALSE == _dess_acl_zero_addr(sw->dest_mac_mask))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+    }
+
+    /* source mac address */
+    FIELD_GET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]);
+    FIELD_GET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]);
+    FIELD_GET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]);
+    FIELD_GET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+    FIELD_GET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+    FIELD_GET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+
+    FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]);
+    FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]);
+    FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]);
+    FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+    FIELD_GET_MASK(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+    FIELD_GET_MASK(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+    if (A_FALSE == _dess_acl_zero_addr(sw->src_mac_mask))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+    }
+
+    /* ethernet type */
+    FIELD_GET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+    FIELD_GET_MASK(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+    if (0x0 != sw->ethtype_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+    }
+
+    /* packet tagged */
+    FIELD_GET_MASK(MAC_RUL_M4, TAGGEDV, sw->tagged_val);
+    FIELD_GET_MASK(MAC_RUL_M4, TAGGEDM, sw->tagged_mask);
+    if (0x0 != sw->tagged_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED);
+    }
+
+    /* vlan priority */
+    FIELD_GET(MAC_RUL_V3, VLANPRIV, sw->up_val);
+    FIELD_GET_MASK(MAC_RUL_M3, VLANPRIM, sw->up_mask);
+    if (0x0 != sw->up_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_UP);
+    }
+
+    /* vlanid */
+    FIELD_GET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+    FIELD_GET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask);
+    FIELD_GET_MASK(MAC_RUL_M4, VIDMSK, mask_en);
+    if (mask_en)
+    {
+        sw->vid_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->vid_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _dess_acl_field_care(sw->vid_op, (a_uint32_t) sw->vid_val,
+                                 (a_uint32_t) sw->vid_mask, 0xfff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_VID);
+    }
+
+    /* vlan cfi */
+    FIELD_GET(MAC_RUL_V3, VLANCFIV, sw->cfi_val);
+    FIELD_GET_MASK(MAC_RUL_M3, VLANCFIM, sw->cfi_mask);
+    if (0x0 != sw->cfi_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CFI);
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+    if (mask_en)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_ehmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t i, mask_en, data;
+
+    FIELD_GET(EHMAC_RUL_V3, DA_EN, data);
+    if (data)
+    {
+        for (i = 2; i < 6; i++)
+        {
+            sw->dest_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff;
+            sw->dest_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff;
+        }
+
+        for (i = 0; i < 2; i++)
+        {
+            sw->dest_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff;
+            sw->dest_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff;
+        }
+
+        if (A_FALSE == _dess_acl_zero_addr(sw->dest_mac_mask))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+        }
+
+        FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+        FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+        FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+
+        FIELD_GET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+        FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+        FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+
+        if (A_FALSE == _dess_acl_zero_addr(sw->src_mac_mask))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+        }
+    }
+    else
+    {
+        for (i = 2; i < 6; i++)
+        {
+            sw->src_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff;
+            sw->src_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff;
+        }
+
+        for (i = 0; i < 2; i++)
+        {
+            sw->src_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff;
+            sw->src_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff;
+        }
+
+        if (A_FALSE == _dess_acl_zero_addr(sw->src_mac_mask))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+        }
+
+        FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]);
+        FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]);
+        FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]);
+
+        FIELD_GET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]);
+        FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]);
+        FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]);
+        if (A_FALSE == _dess_acl_zero_addr(sw->dest_mac_mask))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+        }
+    }
+
+    /* ethernet type */
+    FIELD_GET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+    FIELD_GET_MASK(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+    if (0x0 != sw->ethtype_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+    }
+
+    /* packet stagged */
+    FIELD_GET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val);
+    FIELD_GET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask);
+    if (0x0 != sw->stagged_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED);
+    }
+
+    /* stag vid */
+    FIELD_GET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+    FIELD_GET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask);
+    FIELD_GET(EHMAC_RUL_V3, SVIDMSK, mask_en);
+    if (mask_en)
+    {
+        sw->stag_vid_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->stag_vid_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _dess_acl_field_care(sw->stag_vid_op, (a_uint32_t) sw->stag_vid_val,
+                                 (a_uint32_t) sw->stag_vid_mask, 0xfff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID);
+    }
+
+    /* stag priority */
+    FIELD_GET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val);
+    FIELD_GET_MASK(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask);
+    if (0x0 != sw->stag_pri_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI);
+    }
+
+    /* stag dei */
+    FIELD_GET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val);
+    FIELD_GET_MASK(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask);
+    if (0x0 != sw->stag_dei_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI);
+    }
+
+    /* packet ctagged */
+    FIELD_GET_MASK(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val);
+    FIELD_GET_MASK(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask);
+    if (0x0 != sw->ctagged_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED);
+    }
+
+    /* ctag vid */
+    FIELD_GET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+    FIELD_GET(EHMAC_RUL_V3, CTAG_VIDHV, data);
+    sw->ctag_vid_val |= (data << 8);
+    FIELD_GET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask);
+    FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, data);
+    sw->ctag_vid_mask |= (data << 8);
+
+    FIELD_GET_MASK(EHMAC_RUL_M4, CVIDMSK, mask_en);
+    if (mask_en)
+    {
+        sw->ctag_vid_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->ctag_vid_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _dess_acl_field_care(sw->ctag_vid_op, (a_uint32_t) sw->ctag_vid_val,
+                                 (a_uint32_t) sw->ctag_vid_mask, 0xfff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID);
+    }
+
+    /* ctag priority */
+    FIELD_GET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val);
+    FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask);
+    if (0x0 != sw->ctag_pri_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI);
+    }
+
+    /* ctag dei */
+    FIELD_GET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val);
+    FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask);
+    if (0x0 != sw->ctag_cfi_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI);
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+    if (mask_en)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_ip4_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t mask_en, icmp_en;
+
+    sw->dest_ip4_val = hw->vlu[0];
+    sw->dest_ip4_mask = hw->msk[0];
+    if (0x0 != sw->dest_ip4_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_DIP);
+    }
+
+    sw->src_ip4_val = hw->vlu[1];
+    sw->src_ip4_mask = hw->msk[1];
+    if (0x0 != sw->src_ip4_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_SIP);
+    }
+
+    FIELD_GET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val);
+    FIELD_GET_MASK(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask);
+    if (0x0 != sw->ip_proto_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+    }
+
+    FIELD_GET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val);
+    FIELD_GET_MASK(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask);
+    if (0x0 != sw->ip_dscp_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+    }
+
+    FIELD_GET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+    FIELD_GET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask);
+    FIELD_GET_MASK(IP4_RUL_M3, IP4DPORTM_EN, mask_en);
+    if (mask_en)
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _dess_acl_field_care(sw->dest_l4port_op,
+                                 (a_uint32_t) sw->dest_l4port_val,
+                                 (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+    else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+
+    FIELD_GET(IP4_RUL_V3, ICMP_EN, icmp_en);
+    if (icmp_en)
+    {
+        FIELD_GET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val);
+        FIELD_GET_MASK(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask);
+        if (0x0 != sw->icmp_type_mask)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE);
+        }
+
+        FIELD_GET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val);
+        FIELD_GET_MASK(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask);
+        if (0x0 != sw->icmp_code_mask)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE);
+        }
+    }
+    else
+    {
+        FIELD_GET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+        FIELD_GET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask);
+        FIELD_GET_MASK(IP4_RUL_M3, IP4SPORTM_EN, mask_en);
+        if (mask_en)
+        {
+            sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+        }
+        else
+        {
+            sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+        }
+
+        if (A_TRUE ==
+                _dess_acl_field_care(sw->src_l4port_op,
+                                     (a_uint32_t) sw->src_l4port_val,
+                                     (a_uint32_t) sw->src_l4port_mask, 0xffff))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+        }
+    }
+
+    FIELD_GET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val);
+    FIELD_GET_MASK(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask);
+    if (0x0 != sw->tcp_flag_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG);
+    }
+
+    FIELD_GET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val);
+    FIELD_GET_MASK(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask);
+    if (0x0 != sw->ripv1_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_RIPV1);
+    }
+
+    FIELD_GET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val);
+    FIELD_GET_MASK(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask);
+    if (0x0 != sw->dhcpv4_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV4);
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+    if (mask_en)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 4; i++)
+    {
+        sw->dest_ip6_val.ul[i] = hw->vlu[3 - i];
+        sw->dest_ip6_mask.ul[i] = hw->msk[3 - i];
+        if (0x0 != sw->dest_ip6_mask.ul[i])
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_DIP);
+        }
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, i);
+    if (i)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 4; i++)
+    {
+        sw->src_ip6_val.ul[i] = hw->vlu[3 - i];
+        sw->src_ip6_mask.ul[i] = hw->msk[3 - i];
+        if (0x0 != sw->src_ip6_mask.ul[i])
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_SIP);
+        }
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, i);
+    if (i)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t mask_en, icmp6_en, tmp;
+
+    FIELD_GET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val);
+    FIELD_GET_MASK(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask);
+    if (0x0 != sw->ip_proto_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+    }
+
+    FIELD_GET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val);
+    FIELD_GET_MASK(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask);
+    if (0x0 != sw->ip_dscp_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+    }
+
+    FIELD_GET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+    FIELD_GET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask);
+    FIELD_GET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, mask_en);
+    if (mask_en)
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _dess_acl_field_care(sw->dest_l4port_op,
+                                 (a_uint32_t) sw->dest_l4port_val,
+                                 (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+    else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+
+    FIELD_GET(IP6_RUL3_V3, ICMP6_EN, icmp6_en);
+    if (icmp6_en)
+    {
+        FIELD_GET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val);
+        FIELD_GET_MASK(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask);
+        if (0x0 != sw->icmp_type_mask)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE);
+        }
+
+        FIELD_GET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val);
+        FIELD_GET_MASK(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask);
+        if (0x0 != sw->icmp_code_mask)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE);
+        }
+    }
+    else
+    {
+        FIELD_GET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+        FIELD_GET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask);
+        FIELD_GET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, mask_en);
+        if (mask_en)
+        {
+            sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+        }
+        else
+        {
+            sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+        }
+
+        if (A_TRUE ==
+                _dess_acl_field_care(sw->src_l4port_op,
+                                     (a_uint32_t) sw->src_l4port_val,
+                                     (a_uint32_t) sw->src_l4port_mask, 0xffff))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+        }
+    }
+
+    FIELD_GET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val);
+    FIELD_GET_MASK(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask);
+
+    FIELD_GET(IP6_RUL3_V2, IP6LABEL2V, tmp);
+    sw->ip6_lable_val |= (tmp << 16);
+    FIELD_GET_MASK(IP6_RUL3_M2, IP6LABEL2M, tmp);
+    sw->ip6_lable_mask |= (tmp << 16);
+
+    if (0x0 != sw->ip6_lable_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL);
+    }
+
+    FIELD_GET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val);
+    FIELD_GET_MASK(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask);
+    if (0x0 != sw->tcp_flag_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG);
+    }
+
+    FIELD_GET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val);
+    FIELD_GET_MASK(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask);
+    if (0x0 != sw->dhcpv6_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV6);
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+    if (mask_en)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_udf_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t i;
+
+    FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_UDF);
+
+    /* for ISIS UDF type, length and offset no meanging in rules, just set default value */
+    sw->udf_type = FAL_ACL_UDF_TYPE_L2;
+    sw->udf_len = 16;
+    sw->udf_offset = 0;
+
+    for (i = 0; i < DESS_MAX_UDF_LENGTH; i++)
+    {
+        sw->udf_val[i] = ((hw->vlu[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff;
+        sw->udf_mask[i] = ((hw->msk[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff;
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, i);
+    if (i)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_acl_rule_action_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t data;
+
+    sw->action_flg = 0;
+
+    FIELD_GET_ACTION(ACL_RSLT2, DES_PORT_EN, data);
+    if (1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REDPT);
+        FIELD_GET_ACTION(ACL_RSLT1, DES_PORT0, sw->ports);
+        FIELD_GET_ACTION(ACL_RSLT2, DES_PORT1, data);
+        sw->ports |= (data << 3);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT2, FWD_CMD, data);
+    if (0x7 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_DENY);
+    }
+    else if (0x3 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_RDTCPU);
+    }
+    else if (0x1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_CPYCPU);
+    }
+    else
+    {
+        /* need't set permit action */
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT2, MIRR_EN, data);
+    if (1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MIRROR);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, PRI_QU_EN, data);
+    if (1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE);
+        FIELD_GET_ACTION(ACL_RSLT1, PRI_QU, sw->queue);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, DSCP_REMAP, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP);
+        FIELD_GET_ACTION(ACL_RSLT1, DSCPV, sw->dscp);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT0, STAGVID, sw->stag_vid);
+
+    FIELD_GET_ACTION(ACL_RSLT1, TRANS_SVID_CHG, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, STAG_PRI_REMAP, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI);
+        FIELD_GET_ACTION(ACL_RSLT0, STAGPRI, sw->stag_pri);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, STAG_DEI_CHG, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI);
+        FIELD_GET_ACTION(ACL_RSLT0, STAGDEI, sw->stag_dei);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT0, CTAGVID, sw->ctag_vid);
+
+    FIELD_GET_ACTION(ACL_RSLT1, TRANS_CVID_CHG, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, CTAG_PRI_REMAP, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI);
+        FIELD_GET_ACTION(ACL_RSLT0, CTAGPRI, sw->ctag_pri);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, CTAG_CFI_CHG, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI);
+        FIELD_GET_ACTION(ACL_RSLT0, CTAGCFI, sw->ctag_cfi);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, LOOK_VID_CHG, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT2, POLICER_EN, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICER_EN);
+        FIELD_GET_ACTION(ACL_RSLT2, POLICER_PTR, sw->policer_ptr);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR_EN, data);
+    if (data)
+    {
+        FIELD_GET_ACTION(ACL_RSLT1, WCMP_EN, data);
+        if (data)
+        {
+            FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_WCMP_EN);
+            FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr);
+        }
+        else
+        {
+            FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_ARP_EN);
+            FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR, sw->arp_ptr);
+        }
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, FORCE_L3_MODE, data);
+    if ((0 != data) && (3 != data))
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN);
+        if (0x1 == data)
+        {
+            sw->policy_fwd = FAL_ACL_POLICY_SNAT;
+        }
+        else
+        {
+            sw->policy_fwd = FAL_ACL_POLICY_DNAT;
+        }
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT2, EG_BYPASS, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT2, TRIGGER_INTR, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR);
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+_dess_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+                        dess_acl_rule_t * hw_rule_snap, a_uint32_t * idx)
+{
+    sw_error_t rv;
+    a_uint32_t tmp_idx, i, b_rule[7] = { 0 };
+    parse_func_t ptr[7] = { NULL };
+    a_bool_t b_care, b_mac, eh_mac;
+
+    rv = _dess_acl_action_parse(dev_id, sw, &(hw_rule_snap[*idx].filter));
+    SW_RTN_ON_ERROR(rv);
+
+    ptr[0] = _dess_acl_rule_udf_parse;
+    _dess_acl_rule_mac_preparse(sw, &b_mac, &eh_mac);
+
+    /* ehmac rule must be parsed bofore mac rule.
+       it's important for reparse process */
+    if (A_TRUE == eh_mac)
+    {
+        ptr[1] = _dess_acl_rule_ehmac_parse;
+    }
+
+    if (A_TRUE == b_mac)
+    {
+        ptr[2] = _dess_acl_rule_bmac_parse;
+    }
+
+    if ((A_FALSE == b_mac) && (A_FALSE == eh_mac))
+    {
+        ptr[2] = _dess_acl_rule_bmac_parse;
+    }
+
+    if (FAL_ACL_RULE_MAC == sw->rule_type)
+    {
+    }
+    else if (FAL_ACL_RULE_IP4 == sw->rule_type)
+    {
+        ptr[3] = _dess_acl_rule_ip4_parse;
+    }
+    else if (FAL_ACL_RULE_IP6 == sw->rule_type)
+    {
+        ptr[4] = _dess_acl_rule_ip6r1_parse;
+        ptr[5] = _dess_acl_rule_ip6r2_parse;
+        ptr[6] = _dess_acl_rule_ip6r3_parse;
+    }
+    else if (FAL_ACL_RULE_UDF == sw->rule_type)
+    {
+        ptr[1] = NULL;
+        ptr[2] = NULL;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    tmp_idx = *idx;
+    for (i = 0; i < 7; i++)
+    {
+        if (ptr[i])
+        {
+            if (DESS_HW_RULE_TMP_CNT <= tmp_idx)
+            {
+                return SW_NO_RESOURCE;
+            }
+
+            rv = ptr[i] (sw, &(hw_rule_snap[tmp_idx].filter), &b_care);
+            SW_RTN_ON_ERROR(rv);
+            if (A_TRUE == b_care)
+            {
+                tmp_idx++;
+                b_rule[i] = 1;
+            }
+        }
+    }
+
+    if (FAL_ACL_RULE_IP6 == sw->rule_type)
+    {
+        if ((!b_rule[4]) && (!b_rule[5]) && (!b_rule[6]))
+        {
+            tmp_idx++;
+        }
+    }
+
+    if (FAL_ACL_RULE_IP4 == sw->rule_type)
+    {
+        if (!b_rule[3])
+        {
+            tmp_idx++;
+        }
+    }
+
+    if (tmp_idx == *idx)
+    {
+        /* set type start & end */
+        SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND,
+                            (hw_rule_snap[*idx].filter.msk[4]));
+        (*idx)++;
+    }
+    else
+    {
+        if (1 == (tmp_idx - *idx))
+        {
+            if (FAL_ACL_COMBINED_START == sw->combined)
+            {
+                SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START,
+                                    (hw_rule_snap[*idx].filter.msk[4]));
+            }
+            else if (FAL_ACL_COMBINED_CONTINUE == sw->combined)
+            {
+                SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE,
+                                    (hw_rule_snap[*idx].filter.msk[4]));
+            }
+            else if (FAL_ACL_COMBINED_END == sw->combined)
+            {
+                SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END,
+                                    (hw_rule_snap[*idx].filter.msk[4]));
+            }
+            else
+            {
+                SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND,
+                                (hw_rule_snap[*idx].filter.msk[4]));
+            }
+        }
+        else
+        {
+            for (i = *idx; i < tmp_idx; i++)
+            {
+                if (i == *idx)
+                {
+                    SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START,
+                                        (hw_rule_snap[i].filter.msk[4]));
+                }
+                else if (i == (tmp_idx - 1))
+                {
+                    SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END,
+                                        (hw_rule_snap[i].filter.msk[4]));
+                }
+                else
+                {
+                    SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE,
+                                        (hw_rule_snap[i].filter.msk[4]));
+                }
+                aos_mem_copy(&(hw_rule_snap[i].filter.act[0]),
+                             &(hw_rule_snap[*idx].filter.act[0]),
+                             sizeof (hw_rule_snap[*idx].filter.act));
+            }
+        }
+        *idx = tmp_idx;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+_dess_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+                        dess_acl_rule_t * hw_rule_snap, a_uint32_t idx,
+                        a_uint32_t ent_nr)
+{
+    a_bool_t b_mac = A_FALSE, b_ip4 = A_FALSE, b_ip6 = A_FALSE;
+    sw_error_t rv;
+    a_uint32_t i, flt_typ;
+    hw_filter_t *hw;
+
+    rv = _dess_acl_rule_action_reparse(sw, &(hw_rule_snap[idx].filter));
+    SW_RTN_ON_ERROR(rv);
+
+    sw->rule_type = FAL_ACL_RULE_UDF;
+    for (i = 0; i < ent_nr; i++)
+    {
+        hw = &(hw_rule_snap[idx + i].filter);
+        FIELD_GET_MASK(MAC_RUL_M4, RULE_TYP, flt_typ);
+
+        if (DESS_UDF_FILTER == flt_typ)
+        {
+            rv = _dess_acl_rule_udf_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+        }
+        else if (DESS_MAC_FILTER == flt_typ)
+        {
+            rv = _dess_acl_rule_bmac_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_mac = A_TRUE;
+        }
+        else if (DESS_EHMAC_FILTER == flt_typ)
+        {
+            rv = _dess_acl_rule_ehmac_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_mac = A_TRUE;
+        }
+        else if (DESS_IP4_FILTER == flt_typ)
+        {
+            rv = _dess_acl_rule_ip4_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_ip4 = A_TRUE;
+        }
+        else if (DESS_IP6R1_FILTER == flt_typ)
+        {
+            rv = _dess_acl_rule_ip6r1_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_ip6 = A_TRUE;
+        }
+        else if (DESS_IP6R2_FILTER == flt_typ)
+        {
+            rv = _dess_acl_rule_ip6r2_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_ip6 = A_TRUE;
+        }
+        else if (DESS_IP6R3_FILTER == flt_typ)
+        {
+            rv = _dess_acl_rule_ip6r3_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_ip6 = A_TRUE;
+        }
+        else
+        {
+            /* ignore fill gap filters */
+        }
+    }
+
+    if (A_TRUE == b_mac)
+    {
+        sw->rule_type = FAL_ACL_RULE_MAC;
+    }
+
+    if (A_TRUE == b_ip4)
+    {
+        sw->rule_type = FAL_ACL_RULE_IP4;
+    }
+
+    if (A_TRUE == b_ip6)
+    {
+        sw->rule_type = FAL_ACL_RULE_IP6;
+    }
+
+    return SW_OK;
+}
diff --git a/qca-ssdk/src/hsl/dess/dess_acl_prv.h b/qca-ssdk/src/hsl/dess/dess_acl_prv.h
new file mode 100755
index 0000000..83a7d40
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_acl_prv.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+typedef struct
+{
+    a_uint8_t  status;
+    a_uint8_t  list_id;
+    a_uint8_t  list_pri;
+    a_uint8_t  rule_nr;
+    fal_pbmp_t bind_pts;
+} dess_acl_list_t;
+
+
+typedef struct
+{
+    a_uint32_t  vlu[5];
+    a_uint32_t  msk[5];
+    a_uint32_t  act[3];
+} hw_filter_t;
+
+
+typedef struct
+{
+    a_uint8_t   status;
+    a_uint8_t   list_id;
+    a_uint8_t   list_pri;
+    a_uint8_t   rule_id;
+    hw_filter_t filter;
+    a_uint32_t  src_flt_dis; /* src filter disabled */
+} dess_acl_rule_t;
+
+
+#define ENT_USED                0x1
+#define ENT_TMP                 0x2
+#define ENT_DEACTIVE            0x4
+
+#define FLT_START               0x0
+#define FLT_CONTINUE            0x1
+#define FLT_END                 0x2
+#define FLT_STARTEND            0x3
+
+
+#define DESS_MAC_FILTER         1
+#define DESS_IP4_FILTER         2
+#define DESS_IP6R1_FILTER       3
+#define DESS_IP6R2_FILTER       4
+#define DESS_IP6R3_FILTER       5
+#define DESS_UDF_FILTER         6
+#define DESS_EHMAC_FILTER       7
+
+
+#define DESS_MAX_UDF_OFFSET     31
+#define DESS_MAX_UDF_LENGTH     16
+
+
+#define DESS_FILTER_VLU_OP      0x0
+#define DESS_FILTER_MSK_OP      0x1
+#define DESS_FILTER_ACT_OP      0x2
+
+
+
+//#define DESS_MAX_FILTER         8
+#define DESS_MAX_FILTER         96
+#define DESS_RULE_FUNC_ADDR     0x0400
+#define DESS_HW_RULE_TMP_CNT    (DESS_MAX_FILTER + 4)
+
+#define DESS_MAX_LIST_ID        255
+#define DESS_MAX_LIST_PRI       255
+
+#define DESS_UDF_MAX_LENGTH     15
+#define DESS_UDF_MAX_OFFSET     31
+
+#define WIN_RULE_CTL0_ADDR      0x218
+#define WIN_RULE_CTL1_ADDR      0x234
+
+
+#define DESS_FILTER_VLU_ADDR    0x58000
+#define DESS_FILTER_MSK_ADDR    0x59000
+#define DESS_FILTER_ACT_ADDR    0x5a000
+
+
+#define FIELD_SET(reg, field, val) \
+    SW_REG_SET_BY_FIELD_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define FIELD_GET(reg, field, val) \
+    SW_FIELD_GET_BY_REG_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define FIELD_SET_MASK(reg, field, val) \
+    SW_REG_SET_BY_FIELD_U32(hw->msk[reg-5], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define FIELD_GET_MASK(reg, field, val) \
+    SW_FIELD_GET_BY_REG_U32(hw->msk[reg-5], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define FIELD_SET_ACTION(reg, field, val) \
+    SW_REG_SET_BY_FIELD_U32(hw->act[reg-10], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define FIELD_GET_ACTION(reg, field, val) \
+    SW_FIELD_GET_BY_REG_U32(hw->act[reg-10], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+sw_error_t
+_dess_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw, dess_acl_rule_t * hw_filter_snap, a_uint32_t * idx);
+
+
+sw_error_t
+_dess_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw, dess_acl_rule_t * hw_filter_snap, a_uint32_t idx, a_uint32_t ent_nr);
+
+
diff --git a/qca-ssdk/src/hsl/dess/dess_cosmap.c b/qca-ssdk/src/hsl/dess/dess_cosmap.c
new file mode 100755
index 0000000..593c573
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_cosmap.c
@@ -0,0 +1,945 @@
+/*
+ * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_cosmap DESS_COSMAP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_cosmap.h"
+#include "dess_reg.h"
+
+#define DESS_MAX_DSCP                63
+#define DESS_MAX_UP                  7
+#define DESS_MAX_PRI                 7
+#define DESS_MAX_DP                  1
+#define DESS_MAX_QUEUE               3
+#define DESS_MAX_EH_QUEUE            5
+
+#define DESS_DSCP_TO_PRI             0
+#define DESS_DSCP_TO_DP              1
+#define DESS_UP_TO_PRI               2
+#define DESS_UP_TO_DP                3
+
+#define DESS_EGRESS_REAMRK_ADDR      0x5ae00
+#define DESS_EGRESS_REAMRK_NUM       16
+
+static sw_error_t
+_dess_cosmap_dscp_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode,
+                                a_uint32_t dscp, a_uint32_t val)
+{
+    sw_error_t rv;
+    a_uint32_t index, data = 0;
+
+    if (DESS_MAX_DSCP < dscp)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    index = dscp >> 3;
+    HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (DESS_DSCP_TO_PRI == mode)
+    {
+        if (DESS_MAX_PRI < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x7 << ((dscp & 0x7) << 2)));
+        data |= (val << ((dscp & 0x7) << 2));
+    }
+    else
+    {
+        if (DESS_MAX_DP < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x1 << (((dscp & 0x7) << 2) + 3)));
+        data |= (val << (((dscp & 0x7) << 2) + 3));
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_cosmap_dscp_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode,
+                                a_uint32_t dscp, a_uint32_t * val)
+{
+    sw_error_t rv;
+    a_uint32_t index, data = 0;
+
+    if (DESS_MAX_DSCP < dscp)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    index = dscp >> 3;
+    HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (data >> ((dscp & 0x7) << 2)) & 0xf;
+    if (DESS_DSCP_TO_PRI == mode)
+    {
+        *val = data & 0x7;
+    }
+    else
+    {
+        *val = (data & 0x8) >> 3;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_cosmap_up_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up,
+                              a_uint32_t val)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (DESS_MAX_UP < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (DESS_UP_TO_PRI == mode)
+    {
+        if (DESS_MAX_PRI < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x7 << (up << 2)));
+        data |= (val << (up << 2));
+    }
+    else
+    {
+        if (DESS_MAX_DP < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x1 << ((up << 2) + 3)));
+        data |= (val << ((up << 2) + 3));
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_cosmap_up_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up,
+                              a_uint32_t * val)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (DESS_MAX_UP < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (data >> (up << 2)) & 0xf;
+
+    if (DESS_UP_TO_PRI == mode)
+    {
+        *val = (data & 0x7);
+    }
+    else
+    {
+        *val = (data & 0x8) >> 3;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_cosmap_dscp_to_ehpri_dp_set(a_uint32_t dev_id, a_uint32_t mode,
+                                a_uint32_t dscp, a_uint32_t val)
+{
+    sw_error_t rv;
+    a_uint32_t index, data = 0;
+
+    if (DESS_MAX_DSCP < dscp)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    index = dscp >> 3;
+    HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_EHPRI, index, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (DESS_DSCP_TO_PRI == mode)
+    {
+        if (DESS_MAX_PRI < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x7 << ((dscp & 0x7) << 2)));
+        data |= (val << ((dscp & 0x7) << 2));
+    }
+    else
+    {
+        if (DESS_MAX_DP < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x1 << (((dscp & 0x7) << 2) + 3)));
+        data |= (val << (((dscp & 0x7) << 2) + 3));
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, DSCP_TO_EHPRI, index, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_cosmap_dscp_to_ehpri_dp_get(a_uint32_t dev_id, a_uint32_t mode,
+                                a_uint32_t dscp, a_uint32_t * val)
+{
+    sw_error_t rv;
+    a_uint32_t index, data = 0;
+
+    if (DESS_MAX_DSCP < dscp)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    index = dscp >> 3;
+    HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_EHPRI, index, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (data >> ((dscp & 0x7) << 2)) & 0xf;
+    if (DESS_DSCP_TO_PRI == mode)
+    {
+        *val = data & 0x7;
+    }
+    else
+    {
+        *val = (data & 0x8) >> 3;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_cosmap_up_to_ehpri_dp_set(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up,
+                              a_uint32_t val)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (DESS_MAX_UP < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_EHPRI, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (DESS_UP_TO_PRI == mode)
+    {
+        if (DESS_MAX_PRI < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x7 << (up << 2)));
+        data |= (val << (up << 2));
+    }
+    else
+    {
+        if (DESS_MAX_DP < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x1 << ((up << 2) + 3)));
+        data |= (val << ((up << 2) + 3));
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, UP_TO_EHPRI, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_cosmap_up_to_ehpri_dp_get(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up,
+                              a_uint32_t * val)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (DESS_MAX_UP < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_EHPRI, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (data >> (up << 2)) & 0xf;
+
+    if (DESS_UP_TO_PRI == mode)
+    {
+        *val = (data & 0x7);
+    }
+    else
+    {
+        *val = (data & 0x8) >> 3;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+                              a_uint32_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if ((DESS_MAX_PRI < pri) || (DESS_MAX_QUEUE < queue))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0x3 << (pri << 2)));
+    data |= (queue << (pri << 2));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+                              a_uint32_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (DESS_MAX_PRI < pri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *queue = (data >> (pri << 2)) & 0x3;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+                                a_uint32_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if ((DESS_MAX_PRI < pri) || (DESS_MAX_EH_QUEUE < queue))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0x7 << (pri << 2)));
+    data |= (queue << (pri << 2));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+                                a_uint32_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (DESS_MAX_PRI < pri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *queue = (data >> (pri << 2)) & 0x7;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+                               fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+    a_uint32_t data, addr;
+
+    if (DESS_EGRESS_REAMRK_NUM <= tbl_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = (tbl->y_up & 0x7)
+           | ((tbl->y_dei & 0x1) << 3)
+           | ((tbl->g_up & 0x7) << 4)
+           | ((tbl->y_dscp & 0x3f) << 8)
+           | ((tbl->g_dei & 0x1) << 14)
+           | ((tbl->g_dscp & 0x3f) << 16)
+           | ((tbl->remark_dscp & 0x1) << 23)
+           | ((tbl->remark_up & 0x1) << 22)
+           | ((tbl->remark_dei & 0x1) << 7);
+
+    addr = DESS_EGRESS_REAMRK_ADDR + (tbl_id << 4);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+                               fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, addr;
+
+    if (DESS_EGRESS_REAMRK_NUM <= tbl_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(tbl, sizeof (fal_egress_remark_table_t));
+
+    addr = DESS_EGRESS_REAMRK_ADDR + (tbl_id << 4);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data & (0x1 << 23))
+    {
+        tbl->remark_dscp = A_TRUE;
+        tbl->y_dscp = (data >> 8) & 0x3f;
+        tbl->g_dscp = (data >> 16) & 0x3f;
+    }
+
+    if (data & (0x1 << 22))
+    {
+        tbl->remark_up = A_TRUE;
+        tbl->y_up = data & 0x7;
+        tbl->g_up = (data >> 4) & 0x7;
+    }
+
+    if (data & (0x1 << 7))
+    {
+        tbl->remark_dei = A_TRUE;
+        tbl->y_dei = (data >> 3) & 0x1;
+        tbl->g_dei = (data >> 14) & 0x1;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set dscp to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_dscp_to_pri_dp_set(dev_id, DESS_DSCP_TO_PRI, dscp, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dscp to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+                            a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_dscp_to_pri_dp_get(dev_id, DESS_DSCP_TO_PRI, dscp, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dscp to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_dscp_to_pri_dp_set(dev_id, DESS_DSCP_TO_DP, dscp, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dscp to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_dscp_to_pri_dp_get(dev_id, DESS_DSCP_TO_DP, dscp, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dot1p to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_up_to_pri_dp_set(dev_id, DESS_UP_TO_PRI, up, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dot1p to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_up_to_pri_dp_get(dev_id, DESS_UP_TO_PRI, up, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dot1p to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_up_to_pri_dp_set(dev_id, DESS_UP_TO_DP, up, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dot1p to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_up_to_pri_dp_get(dev_id, DESS_UP_TO_DP, up, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dscp to internal priority mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_dscp_to_ehpri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_dscp_to_ehpri_dp_set(dev_id, DESS_DSCP_TO_PRI, dscp, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dscp to internal priority mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_dscp_to_ehpri_get(a_uint32_t dev_id, a_uint32_t dscp,
+                            a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_dscp_to_ehpri_dp_get(dev_id, DESS_DSCP_TO_PRI, dscp, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dscp to internal drop precedence mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_dscp_to_ehdp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_dscp_to_ehpri_dp_set(dev_id, DESS_DSCP_TO_DP, dscp, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dscp to internal drop precedence mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_dscp_to_ehdp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_dscp_to_ehpri_dp_get(dev_id, DESS_DSCP_TO_DP, dscp, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dot1p to internal priority mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_up_to_ehpri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_up_to_ehpri_dp_set(dev_id, DESS_UP_TO_PRI, up, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dot1p to internal priority mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_up_to_ehpri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_up_to_ehpri_dp_get(dev_id, DESS_UP_TO_PRI, up, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dot1p to internal drop precedence mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_up_to_ehdp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_up_to_ehpri_dp_set(dev_id, DESS_UP_TO_DP, up, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dot1p to internal drop precedence mapping on one particular device for WAN port.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_up_to_ehdp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_up_to_ehpri_dp_get(dev_id, DESS_UP_TO_DP, up, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 1/2/3/4 which have four egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+                             a_uint32_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_pri_to_queue_set(dev_id, pri, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 1/2/3/4 which have four egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+                             a_uint32_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_pri_to_queue_get(dev_id, pri, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 0/5/6 which have six egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+                               a_uint32_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_pri_to_ehqueue_set(dev_id, pri, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 0/5/6 which have six egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+                               a_uint32_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_pri_to_ehqueue_get(dev_id, pri, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress queue based CoS remap table on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] tbl_id CoS remap table id
+ * @param[in] tbl CoS remap table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+                              fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_egress_remark_set(dev_id, tbl_id, tbl);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress queue based CoS remap table on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] tbl_id CoS remap table id
+ * @param[out] tbl CoS remap table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+                              fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cosmap_egress_remark_get(dev_id, tbl_id, tbl);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+dess_cosmap_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->cosmap_dscp_to_pri_set = dess_cosmap_dscp_to_pri_set;
+        p_api->cosmap_dscp_to_pri_get = dess_cosmap_dscp_to_pri_get;
+        p_api->cosmap_dscp_to_dp_set = dess_cosmap_dscp_to_dp_set;
+        p_api->cosmap_dscp_to_dp_get = dess_cosmap_dscp_to_dp_get;
+        p_api->cosmap_up_to_pri_set = dess_cosmap_up_to_pri_set;
+        p_api->cosmap_up_to_pri_get = dess_cosmap_up_to_pri_get;
+        p_api->cosmap_up_to_dp_set = dess_cosmap_up_to_dp_set;
+        p_api->cosmap_up_to_dp_get = dess_cosmap_up_to_dp_get;
+        p_api->cosmap_dscp_to_ehpri_set = dess_cosmap_dscp_to_ehpri_set;
+        p_api->cosmap_dscp_to_ehpri_get = dess_cosmap_dscp_to_ehpri_get;
+        p_api->cosmap_dscp_to_ehdp_set = dess_cosmap_dscp_to_ehdp_set;
+        p_api->cosmap_dscp_to_ehdp_get = dess_cosmap_dscp_to_ehdp_get;
+        p_api->cosmap_up_to_ehpri_set = dess_cosmap_up_to_ehpri_set;
+        p_api->cosmap_up_to_ehpri_get = dess_cosmap_up_to_ehpri_get;
+        p_api->cosmap_up_to_ehdp_set = dess_cosmap_up_to_ehdp_set;
+        p_api->cosmap_up_to_ehdp_get = dess_cosmap_up_to_ehdp_get;
+        p_api->cosmap_pri_to_queue_set = dess_cosmap_pri_to_queue_set;
+        p_api->cosmap_pri_to_queue_get = dess_cosmap_pri_to_queue_get;
+        p_api->cosmap_pri_to_ehqueue_set = dess_cosmap_pri_to_ehqueue_set;
+        p_api->cosmap_pri_to_ehqueue_get = dess_cosmap_pri_to_ehqueue_get;
+        p_api->cosmap_egress_remark_set = dess_cosmap_egress_remark_set;
+        p_api->cosmap_egress_remark_get = dess_cosmap_egress_remark_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/dess/dess_fdb.c b/qca-ssdk/src/hsl/dess/dess_fdb.c
new file mode 100755
index 0000000..c92899e
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_fdb.c
@@ -0,0 +1,2431 @@
+/*
+ * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_fdb DESS_FDB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_fdb.h"
+#include "dess_reg.h"
+#include "dess_fdb_prv.h"
+
+static aos_lock_t dess_fdb_lock;
+static sw_error_t
+_dess_wl_feature_check(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (DESS_DEVICE_ID == entry)
+    {
+        return SW_OK;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+}
+
+static a_bool_t
+_dess_fdb_is_zeroaddr(fal_mac_addr_t addr)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 6; i++)
+    {
+        if (addr.uc[i])
+        {
+            return A_FALSE;
+        }
+    }
+
+    return A_TRUE;
+}
+
+static void
+_dess_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1)
+{
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1);
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE2, addr.uc[2], *reg0);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE3, addr.uc[3], *reg0);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0);
+
+    return;
+}
+
+static sw_error_t
+_dess_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry,
+                   a_uint32_t reg[])
+{
+    a_uint32_t port;
+    sw_error_t rv;
+
+    if (A_TRUE == entry->white_list_en)
+    {
+        rv = _dess_wl_feature_check(dev_id);
+        SW_RTN_ON_ERROR(rv);
+
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, WL_EN, 1, reg[2]);
+    }
+
+    if (FAL_SVL_FID == entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]);
+    }
+    else if (DESS_MAX_FID >= entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == entry->portmap_en)
+    {
+        if (A_TRUE !=
+                hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+
+        port = 0x1UL << entry->port.id;
+    }
+    else
+    {
+        if (A_FALSE ==
+                hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+
+        port = entry->port.map;
+    }
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg[1]);
+
+    if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]);
+    }
+    else if (FAL_MAC_FRWRD != entry->dacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->leaky_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]);
+    }
+
+    if (A_TRUE == entry->static_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]);
+    }
+
+    if (FAL_MAC_DROP == entry->sacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, SA_DROP_EN, 1, reg[1]);
+    }
+    else if (FAL_MAC_FRWRD != entry->sacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->mirror_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, MIRROR_EN, 1, reg[1]);
+    }
+
+    if (A_TRUE == entry->cross_pt_state)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 1, reg[1]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 0, reg[1]);
+    }
+
+    if (A_TRUE == entry->da_pri_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 1, reg[1]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI, (entry->da_queue & 0x7),
+                            reg[1]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 0, reg[1]);
+    }
+
+    if (A_TRUE == entry->load_balance_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LOAD_BALANCE_EN, 1, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LOAD_BALANCE,
+        			(entry->load_balance & 0x3), reg[2]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LOAD_BALANCE_EN, 0, reg[2]);
+    }
+
+    _dess_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+    return SW_OK;
+}
+
+static void
+_dess_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+    a_uint32_t i, data;
+
+    aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_SVL_EN, data, reg[1]);
+    if (data)
+    {
+        entry->fid = FAL_SVL_FID;
+    }
+    else
+    {
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_VID, data, reg[2]);
+        entry->fid = data;
+    }
+
+    entry->dacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_CPY_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    entry->sacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, SA_DROP_EN, data, reg[1]);
+    if (1 == data)
+    {
+        entry->sacmd = FAL_MAC_DROP;
+    }
+
+    entry->leaky_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->leaky_en = A_TRUE;
+    }
+
+    entry->static_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]);
+    if (0xf == data)
+    {
+        entry->static_en = A_TRUE;
+    }
+
+    entry->mirror_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, MIRROR_EN, data, reg[1]);
+    if (1 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+
+    entry->da_pri_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI_EN, data, reg[1]);
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI, data, reg[1]);
+        entry->da_pri_en = A_TRUE;
+        entry->da_queue = data & 0x7;
+    }
+
+    entry->cross_pt_state = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, CROSS_PT, data, reg[1]);
+    if (1 == data)
+    {
+        entry->cross_pt_state = A_TRUE;
+    }
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, data, reg[1]);
+    entry->portmap_en = A_TRUE;
+    entry->port.map = data;
+
+    for (i = 2; i < 6; i++)
+    {
+        entry->addr.uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff;
+    }
+
+    for (i = 0; i < 2; i++)
+    {
+        entry->addr.uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff;
+    }
+
+    entry->white_list_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, WL_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->white_list_en = A_TRUE;
+    }
+
+    entry->load_balance_en = A_FALSE;
+    entry->load_balance    = 0;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LOAD_BALANCE_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->load_balance_en = A_TRUE;
+	SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LOAD_BALANCE, data, reg[2]);
+	entry->load_balance = data;
+    }
+
+    return;
+}
+
+static sw_error_t
+_dess_atu_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                      (a_uint8_t *) (&reg[3]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_atu_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                      (a_uint8_t *) (&reg[3]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    sw_error_t rv;
+    a_uint32_t busy = 1;
+    a_uint32_t full_vio;
+    a_uint32_t i = 2000;
+    a_uint32_t entry = 0;
+    a_uint32_t hwop = op;
+
+    while (busy && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry);
+    }
+
+    if (0 == i)
+    {
+        return SW_BUSY;
+    }
+
+    if (ARL_FIRST_ENTRY == op)
+    {
+        hwop = ARL_NEXT_ENTRY;
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_BUSY, 1, entry);
+
+    if (ARL_FLUSH_PORT_AND_STATIC == hwop)
+    {
+        hwop = ARL_FLUSH_PORT_UNICAST;
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 1, entry);
+    }
+
+    if (ARL_FLUSH_PORT_NO_STATIC == hwop)
+    {
+        hwop = ARL_FLUSH_PORT_UNICAST;
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 0, entry);
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_FUNC, hwop, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    busy = 1;
+    i = 2000;
+    while (busy && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry);
+    }
+
+    if (0 == i)
+    {
+        return SW_FAIL;
+    }
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_FULL_VIO, full_vio, entry);
+
+    if (full_vio)
+    {
+        /* must clear AT_FULL_VOI bit */
+        entry = 0x1000;
+        HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        if (ARL_LOAD_ENTRY == hwop)
+        {
+            return SW_FULL;
+        }
+        else if ((ARL_PURGE_ENTRY == hwop)
+                 || (ARL_FLUSH_PORT_UNICAST == hwop))
+        {
+            return SW_NOT_FOUND;
+        }
+        else
+        {
+            return SW_FAIL;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_fdb_get(a_uint32_t dev_id, fal_fdb_op_t * option, fal_fdb_entry_t * entry,
+              a_uint32_t hwop)
+{
+    sw_error_t rv;
+    a_uint32_t i, port = 0, status, reg[4] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == option->port_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_EN, 1, reg[3]);
+        if (A_FALSE == entry->portmap_en)
+        {
+            if (A_TRUE !=
+                    hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+            {
+                return SW_BAD_PARAM;
+            }
+            port = entry->port.id;
+        }
+        else
+        {
+            if (A_FALSE ==
+                    hsl_mports_prop_check(dev_id, entry->port.map,
+                                          HSL_PP_INCL_CPU))
+            {
+                return SW_BAD_PARAM;
+            }
+
+            status = 0;
+            for (i = 0; i < SW_MAX_NR_PORT; i++)
+            {
+                if ((entry->port.map) & (0x1UL << i))
+                {
+                    if (status)
+                    {
+                        return SW_BAD_PARAM;
+                    }
+                    port = i;
+                    status = 1;
+                }
+            }
+        }
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port, reg[3]);
+    }
+
+    if (A_TRUE == option->fid_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]);
+    }
+
+    if (A_TRUE == option->multicast_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]);
+    }
+
+    if (FAL_SVL_FID == entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]);
+    }
+    else if (DESS_MAX_FID >= entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, entry->fid, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ARL_FIRST_ENTRY != hwop)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 0xf, reg[2]);
+    }
+
+    _dess_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+
+    rv = _dess_atu_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_fdb_commit(dev_id, hwop);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_atu_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    _dess_atu_hw_to_sw(reg, entry);
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]);
+    if ((A_TRUE == _dess_fdb_is_zeroaddr(entry->addr))
+            && (0 == status))
+    {
+        if (ARL_NEXT_ENTRY == hwop)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            return SW_NOT_FOUND;
+        }
+    }
+    else
+    {
+        return SW_OK;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[4] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_atu_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_atu_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        rv = _dess_fdb_commit(dev_id, ARL_FLUSH_ALL);
+    }
+    else
+    {
+        rv = _dess_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port_id, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        rv = _dess_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC);
+    }
+    else
+    {
+        rv = _dess_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC);
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg0 = 0, reg1 = 0, reg2 = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    _dess_fdb_fill_addr(entry->addr, &reg0, &reg1);
+
+    if (FAL_SVL_FID == entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg2);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg1);
+    }
+    else if (DESS_MAX_FID >= entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg2);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg1);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, (a_uint8_t *) (&reg2),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (&reg1),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&reg0),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_fdb_commit(dev_id, ARL_PURGE_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    fal_fdb_op_t option;
+
+    aos_mem_zero(&option, sizeof (fal_fdb_op_t));
+    rv = _dess_fdb_get(dev_id, &option, entry, ARL_FIND_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option,
+                      fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    rv = _dess_fdb_get(dev_id, option, entry, ARL_NEXT_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+                       fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    rv = _dess_fdb_get(dev_id, option, entry, ARL_FIRST_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+                   a_uint32_t fid, fal_fdb_op_t * option)
+{
+    sw_error_t rv;
+    a_uint32_t reg[4] = { 0 };
+
+    if (A_TRUE == option->port_en)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == option->fid_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]);
+    }
+
+    if (A_TRUE == option->multicast_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]);
+    }
+
+    if (FAL_SVL_FID == fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]);
+    }
+    else if (DESS_MAX_FID >= fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, fid, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, old_port, reg[3]);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, NEW_PORT_NUM, new_port, reg[3]);
+
+    rv = _dess_atu_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_fdb_commit(dev_id, ARL_TRANSFER_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    data = smode;
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, ARL_INI_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, ARL_INI_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+    *smode = data;
+
+    return rv;
+}
+
+
+
+static sw_error_t
+_dess_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((65535 * 7 < *time) || (7 > *time))
+    {
+        return SW_BAD_PARAM;
+    }
+    data = *time / 7;
+    *time = data * 7;
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *time = data * 7;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        if (DESS_MAX_PORT_LEARN_LIMIT_CNT < cnt)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, cnt, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, 0, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, data, reg);
+    if (data)
+    {
+        SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, data, reg);
+        *enable = A_TRUE;
+        *cnt = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *cnt = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        if (DESS_MAX_LEARN_LIMIT_CNT < cnt)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 1,
+                            reg);
+        SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, cnt, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 0,
+                            reg);
+        SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, 0, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable,
+                          a_uint32_t * cnt)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, data,
+                        reg);
+    if (data)
+    {
+        SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, data,
+                            reg);
+        *enable = A_TRUE;
+        *cnt = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *cnt = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+                      GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+                      GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+#define DESS_RESV_ADDR_NUM  32
+#define RESV_ADDR_TBL0_ADDR 0x3c000
+#define RESV_ADDR_TBL1_ADDR 0x3c004
+#define RESV_ADDR_TBL2_ADDR 0x3c008
+
+static void
+_dess_resv_addr_parse(const a_uint32_t reg[], fal_mac_addr_t * addr)
+{
+    a_uint32_t i;
+
+    for (i = 2; i < 6; i++)
+    {
+        addr->uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff;
+    }
+
+    for (i = 0; i < 2; i++)
+    {
+        addr->uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff;
+    }
+}
+
+static sw_error_t
+_dess_resv_atu_sw_to_hw(a_uint32_t dev_id, fal_fdb_entry_t * entry,
+                        a_uint32_t reg[])
+{
+    a_uint32_t port;
+
+    if (A_FALSE == entry->portmap_en)
+    {
+        if (A_TRUE !=
+                hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+        port = 0x1UL << entry->port.id;
+    }
+    else
+    {
+        if (A_FALSE ==
+                hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+        port = entry->port.map;
+    }
+    SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_DES_PORT, port, reg[1]);
+
+    if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, 1, reg[1]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, 1, reg[1]);
+    }
+    else if (FAL_MAC_FRWRD != entry->dacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_MAC_FRWRD != entry->sacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->leaky_en)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 1, reg[1]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 0, reg[1]);
+    }
+
+    if (A_TRUE != entry->static_en)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+    SW_SET_REG_BY_FIELD(RESV_ADDR_TBL2, RESV_STATUS, 1, reg[2]);
+
+    if (A_TRUE == entry->mirror_en)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_MIRROR_EN, 1, reg[1]);
+    }
+
+    if (A_TRUE == entry->cross_pt_state)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_CROSS_PT, 1, reg[1]);
+    }
+
+    if (A_TRUE == entry->da_pri_en)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI_EN, 1, reg[1]);
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI, (entry->da_queue & 0x7),
+                            reg[1]);
+    }
+
+    _dess_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+    return SW_OK;
+}
+
+static void
+_dess_resv_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+    a_uint32_t data;
+
+    aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+    entry->fid = FAL_SVL_FID;
+
+    entry->dacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, data, reg[1]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_CPY_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, data, reg[1]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    entry->sacmd = FAL_MAC_FRWRD;
+
+    entry->leaky_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_LEAKY_EN, data, reg[1]);
+    if (1 == data)
+    {
+        entry->leaky_en = A_TRUE;
+    }
+
+    entry->static_en = A_TRUE;
+
+    entry->mirror_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_MIRROR_EN, data, reg[1]);
+    if (1 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+
+    entry->da_pri_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI_EN, data, reg[1]);
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI, data, reg[1]);
+        entry->da_pri_en = A_TRUE;
+        entry->da_queue = data & 0x7;
+    }
+
+    entry->cross_pt_state = A_FALSE;
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_CROSS_PT, data, reg[1]);
+    if (1 == data)
+    {
+        entry->cross_pt_state = A_TRUE;
+    }
+
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_DES_PORT, data, reg[1]);
+    entry->portmap_en = A_TRUE;
+    entry->port.map = data;
+
+    _dess_resv_addr_parse(reg, &(entry->addr));
+    return;
+}
+
+static sw_error_t
+_dess_fdb_resv_commit(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op,
+                      a_uint32_t * empty)
+{
+    a_uint32_t index, addr, data, tbl[3] = { 0 };
+    sw_error_t rv;
+    fal_mac_addr_t mac_tmp;
+
+    *empty = DESS_RESV_ADDR_NUM;
+    for (index = 0; index < DESS_RESV_ADDR_NUM; index++)
+    {
+        addr = RESV_ADDR_TBL2_ADDR + (index << 4);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]);
+        if (data)
+        {
+            addr = RESV_ADDR_TBL0_ADDR + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[0])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            addr = RESV_ADDR_TBL1_ADDR + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[1])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            _dess_resv_addr_parse(tbl, &mac_tmp);
+            if (!aos_mem_cmp
+                    ((void *) &(entry->addr), (void *) &mac_tmp,
+                     sizeof (fal_mac_addr_t)))
+            {
+                if (ARL_PURGE_ENTRY == op)
+                {
+                    addr = RESV_ADDR_TBL2_ADDR + (index << 4);
+                    tbl[2] = 0;
+                    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                          (a_uint8_t *) (&(tbl[2])),
+                                          sizeof (a_uint32_t));
+                    return rv;
+                }
+                else if (ARL_LOAD_ENTRY == op)
+                {
+                    return SW_ALREADY_EXIST;
+                }
+                else if (ARL_FIND_ENTRY == op)
+                {
+                    _dess_resv_atu_hw_to_sw(tbl, entry);
+                    return SW_OK;
+                }
+            }
+        }
+        else
+        {
+            *empty = index;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_dess_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, empty, addr, tbl[3] = { 0 };
+
+    rv = _dess_resv_atu_sw_to_hw(dev_id, entry, tbl);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_fdb_resv_commit(dev_id, entry, ARL_LOAD_ENTRY, &empty);
+    if (SW_ALREADY_EXIST == rv)
+    {
+        return rv;
+    }
+
+    if (DESS_RESV_ADDR_NUM == empty)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    for (i = 0; i < 3; i++)
+    {
+        addr = RESV_ADDR_TBL0_ADDR + (empty << 4) + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t empty;
+
+    rv = _dess_fdb_resv_commit(dev_id, entry, ARL_PURGE_ENTRY, &empty);
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t empty;
+
+    rv = _dess_fdb_resv_commit(dev_id, entry, ARL_FIND_ENTRY, &empty);
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+                       fal_fdb_entry_t * entry)
+{
+    a_uint32_t index, addr, data, tbl[3] = { 0 };
+    sw_error_t rv;
+
+    if ((NULL == iterator) || (NULL == entry))
+    {
+        return SW_BAD_PTR;
+    }
+
+    if (DESS_RESV_ADDR_NUM < *iterator)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (index = *iterator; index < DESS_RESV_ADDR_NUM; index++)
+    {
+        addr = RESV_ADDR_TBL2_ADDR + (index << 4);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]);
+        if (data)
+        {
+            addr = RESV_ADDR_TBL0_ADDR + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[0])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            addr = RESV_ADDR_TBL1_ADDR + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[1])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            _dess_resv_atu_hw_to_sw(tbl, entry);
+            break;
+        }
+    }
+
+    if (DESS_RESV_ADDR_NUM == index)
+    {
+        return SW_NO_MORE;
+    }
+
+    *iterator = index + 1;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 0xf;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0x7;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      SA_LEARN_STATUS, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      SA_LEARN_STATUS, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0xf == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_fdb_port_update(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id, a_uint32_t op)
+{
+    sw_error_t      rv;
+    fal_fdb_entry_t entry;
+    fal_fdb_op_t    option;
+    a_uint32_t      reg, port;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SVL_FID < fid)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(&option, sizeof(fal_fdb_op_t));
+    aos_mem_copy(&(entry.addr), addr, sizeof(fal_mac_addr_t));
+    entry.fid = fid & 0xffff;
+    rv = _dess_fdb_get(dev_id, &option, &entry, ARL_FIND_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, port, reg);
+    if (op)
+    {
+        port |= (0x1 << port_id);
+    }
+    else
+    {
+        port &= (~(0x1 << port_id));
+    }
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    rv = _dess_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+    return rv;
+}
+#define FDB_RFS_ADD  1
+#define FDB_RFS_DEL  2
+static sw_error_t
+_dess_fdb_rfs_update(const fal_fdb_rfs_t *rfs, fal_fdb_entry_t *entry, char op)
+{
+	_dess_fdb_del_by_mac(0, entry);
+	if(FDB_RFS_ADD == op) {
+		entry->static_en = 1;
+		entry->load_balance_en = 1;
+		entry->load_balance = rfs->load_balance;
+		entry->port.map = 1;
+		entry->portmap_en = 1;
+	} else {
+		entry->static_en = 0;
+		entry->load_balance_en = 0;
+	}
+	return _dess_fdb_add(0, entry);
+}
+
+
+static sw_error_t
+_dess_fdb_rfs_set(a_uint32_t dev_id, const fal_fdb_rfs_t *rfs)
+{
+
+	fal_fdb_entry_t entry;
+	sw_error_t ret;
+
+	memset(&entry, 0, sizeof(entry));
+
+	entry.addr = rfs->addr;
+	entry.fid = rfs->fid;
+	ret = _dess_fdb_find(0, &entry);
+	if(!ret) {
+		return _dess_fdb_rfs_update(rfs, &entry, FDB_RFS_ADD);
+	} else {
+		entry.addr = rfs->addr;
+		entry.fid = rfs->fid;
+		entry.load_balance_en = 1;
+		entry.load_balance = rfs->load_balance;
+		entry.static_en = 1;
+		entry.port.map = 1;
+		entry.portmap_en = 1;
+		return _dess_fdb_add(0, &entry);
+	}
+}
+
+static sw_error_t
+_dess_fdb_rfs_del(a_uint32_t dev_id, const fal_fdb_rfs_t *rfs)
+{
+
+	fal_fdb_entry_t entry;
+	sw_error_t ret;
+
+	memset(&entry, 0, sizeof(entry));
+	entry.addr = rfs->addr;
+	entry.fid = rfs->fid;
+	ret = _dess_fdb_find(0, &entry);
+	if(!ret) {
+		return _dess_fdb_rfs_update(rfs, &entry, FDB_RFS_DEL);
+	} else {
+		return ret;
+	}
+}
+
+
+
+sw_error_t
+inter_dess_fdb_flush(a_uint32_t dev_id, a_uint32_t flag)
+{
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        return _dess_fdb_commit(dev_id, ARL_FLUSH_ALL);
+    }
+    else
+    {
+        return _dess_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+    }
+}
+
+/**
+ * @brief Add a Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    aos_lock_bh(&dess_fdb_lock);
+    rv = _dess_fdb_add(dev_id, entry);
+    aos_unlock_bh(&dess_fdb_lock);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete all Fdb entries
+ *   @details   Comments:
+ *         If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ *       entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    aos_lock_bh(&dess_fdb_lock);
+    rv = _dess_fdb_del_all(dev_id, flag);
+    aos_unlock_bh(&dess_fdb_lock);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete Fdb entries on a particular port
+ *   @details   Comments:
+ *       If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ *       entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    aos_lock_bh(&dess_fdb_lock);
+    rv = _dess_fdb_del_by_port(dev_id, port_id, flag);
+    aos_unlock_bh(&dess_fdb_lock);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a particular Fdb entry through mac address
+ *   @details   Comments:
+ *       Only addr field in entry is meaning. For IVL learning vid or fid field
+ *       also is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    aos_lock_bh(&dess_fdb_lock);
+    rv = _dess_fdb_del_by_mac(dev_id, entry);
+    aos_unlock_bh(&dess_fdb_lock);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a particular Fdb entry from device through mac address.
+ *    @details  Comments:
+    For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    aos_lock_bh(&dess_fdb_lock);
+    rv = _dess_fdb_find(dev_id, entry);
+    aos_unlock_bh(&dess_fdb_lock);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get next Fdb entry from a particular device
+ * @param[in] dev_id device id
+ * @param[in] option next operation options
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option,
+                     fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    aos_lock_bh(&dess_fdb_lock);
+    rv = _dess_fdb_extend_next(dev_id, option, entry);
+    aos_unlock_bh(&dess_fdb_lock);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from a particular device
+ * @param[in] dev_id device id
+ * @param[in] option first operation options
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+                      fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    aos_lock_bh(&dess_fdb_lock);
+    rv = _dess_fdb_extend_first(dev_id, option, entry);
+    aos_unlock_bh(&dess_fdb_lock);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Transfer fdb entries port information on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] old_port source port id
+ * @param[in] new_port destination port id
+ * @param[in] fid filter database id
+ * @param[in] option transfer operation options
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+                  a_uint32_t fid, fal_fdb_op_t * option)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    aos_lock_bh(&dess_fdb_lock);
+    rv = _dess_fdb_transfer(dev_id, old_port, new_port, fid, option);
+    aos_unlock_bh(&dess_fdb_lock);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning status on a particular port.
+ *    @details  Comments:
+ *       This operation will enable or disable dynamic address learning
+ *       feature on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_port_learn_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_port_learn_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address aging status on particular device.
+ *   @details  Comments:
+ *       This operation will enable or disable dynamic address aging
+ *       feature on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_age_ctrl_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address aging status on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_age_ctrl_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief set arl search mode as ivl or svl when vlan invalid.
+ * @param[in] dev_id device id
+ * @param[in] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_vlan_ivl_svl_set(dev_id, smode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief get arl search mode when vlan invalid.
+ * @param[in] dev_id device id
+ * @param[out] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_vlan_ivl_svl_get(dev_id, smode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+
+/**
+ * @brief Set dynamic address aging time on a particular device.
+ * @details   Comments:
+ *       This operation will set dynamic address aging time on a particular device.
+ *       The unit of time is second. Because different device has differnet
+ *       hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_age_time_set(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address aging time on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_age_time_get(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_fdb_learn_limit_set(dev_id, port_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_fdb_learn_limit_get(dev_id, port_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count limit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_learn_limit_set(dev_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count limit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_learn_limit_get(dev_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count exceed command on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_learn_exceed_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count exceed command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_learn_exceed_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a particular reserve Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_resv_add(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a particular reserve Fdb entry through mac address
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_resv_del(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a particular reserve Fdb entry through mac address
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @param[out] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_resv_find(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Iterate all reserve fdb entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] iterator reserve fdb entry index if it's zero means get the first entry
+ * @param[out] iterator next valid fdb entry index
+ * @param[out] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+                      fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_resv_iterate(dev_id, iterator, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the static status of fdb entries which learned by hardware on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_port_learn_static_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the static status of fdb entries which learned by hardware on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_fdb_port_learn_static_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a port to an exsiting entry
+ * @param[in] dev_id device id
+ * @param[in] fid filtering database id
+ * @param[in] addr MAC address
+ * @param[in] port_id port id
+ * @return SW_OK or error code, If entry not exist will return error.
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    aos_lock_bh(&dess_fdb_lock);
+    rv = _dess_fdb_port_update(dev_id, fid, addr, port_id, 1);
+    aos_unlock_bh(&dess_fdb_lock);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a port from an exsiting entry
+ * @param[in] dev_id device id
+ * @param[in] fid filtering database id
+ * @param[in] addr MAC address
+ * @param[in] port_id port id
+ * @return SW_OK or error code, If entry not exist will return error.
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    aos_lock_bh(&dess_fdb_lock);
+    rv = _dess_fdb_port_update(dev_id, fid, addr, port_id, 0);
+    aos_unlock_bh(&dess_fdb_lock);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief set a fdb rfs entry
+ * @param[in] dev_id device id
+ * @param[in] rfs entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_rfs_set(a_uint32_t dev_id, const fal_fdb_rfs_t *rfs)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    aos_lock_bh(&dess_fdb_lock);
+    rv = _dess_fdb_rfs_set(dev_id, rfs);
+    aos_unlock_bh(&dess_fdb_lock);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief del a fdb rfs entry
+ * @param[in] dev_id device id
+ * @param[in] rfs entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_fdb_rfs_del(a_uint32_t dev_id, const fal_fdb_rfs_t *rfs)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    aos_lock_bh(&dess_fdb_lock);
+    rv = _dess_fdb_rfs_del(dev_id, rfs);
+    aos_unlock_bh(&dess_fdb_lock);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+sw_error_t
+dess_fdb_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->fdb_add = dess_fdb_add;
+        p_api->fdb_del_all = dess_fdb_del_all;
+        p_api->fdb_del_by_port = dess_fdb_del_by_port;
+        p_api->fdb_del_by_mac = dess_fdb_del_by_mac;
+        p_api->fdb_find = dess_fdb_find;
+        p_api->port_learn_set = dess_fdb_port_learn_set;
+        p_api->port_learn_get = dess_fdb_port_learn_get;
+        p_api->age_ctrl_set = dess_fdb_age_ctrl_set;
+        p_api->age_ctrl_get = dess_fdb_age_ctrl_get;
+        p_api->vlan_ivl_svl_set = dess_fdb_vlan_ivl_svl_set;
+        p_api->vlan_ivl_svl_get = dess_fdb_vlan_ivl_svl_get;
+        p_api->age_time_set = dess_fdb_age_time_set;
+        p_api->age_time_get = dess_fdb_age_time_get;
+        p_api->fdb_extend_next  = dess_fdb_extend_next;
+        p_api->fdb_extend_first = dess_fdb_extend_first;
+        p_api->fdb_transfer     = dess_fdb_transfer;
+        p_api->port_fdb_learn_limit_set = dess_port_fdb_learn_limit_set;
+        p_api->port_fdb_learn_limit_get = dess_port_fdb_learn_limit_get;
+        p_api->port_fdb_learn_exceed_cmd_set = dess_port_fdb_learn_exceed_cmd_set;
+        p_api->port_fdb_learn_exceed_cmd_get = dess_port_fdb_learn_exceed_cmd_get;
+        p_api->fdb_learn_limit_set = dess_fdb_learn_limit_set;
+        p_api->fdb_learn_limit_get = dess_fdb_learn_limit_get;
+        p_api->fdb_learn_exceed_cmd_set = dess_fdb_learn_exceed_cmd_set;
+        p_api->fdb_learn_exceed_cmd_get = dess_fdb_learn_exceed_cmd_get;
+        p_api->fdb_resv_add     = dess_fdb_resv_add;
+        p_api->fdb_resv_del     = dess_fdb_resv_del;
+        p_api->fdb_resv_find    = dess_fdb_resv_find;
+        p_api->fdb_resv_iterate = dess_fdb_resv_iterate;
+        p_api->fdb_port_learn_static_set = dess_fdb_port_learn_static_set;
+        p_api->fdb_port_learn_static_get = dess_fdb_port_learn_static_get;
+        p_api->fdb_port_add = dess_fdb_port_add;
+        p_api->fdb_port_del = dess_fdb_port_del;
+		p_api->fdb_rfs_set = dess_fdb_rfs_set;
+		p_api->fdb_rfs_del = dess_fdb_rfs_del;
+    }
+#endif
+
+    aos_lock_init(&dess_fdb_lock);
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/dess/dess_igmp.c b/qca-ssdk/src/hsl/dess/dess_igmp.c
new file mode 100755
index 0000000..5ca8a6f
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_igmp.c
@@ -0,0 +1,1147 @@
+/*
+ * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_igmp DESS_IGMP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_igmp.h"
+#include "dess_reg.h"
+
+#define LEAVE_EN_OFFSET     2
+#define JOIN_EN_OFFSET      1
+#define IGMP_MLD_EN_OFFSET  0
+
+#define DESS_MAX_PORT_LEARN_LIMIT_CNT 1024
+
+extern sw_error_t
+dess_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+extern sw_error_t
+dess_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+extern sw_error_t
+dess_igmp_sg_entry_show(a_uint32_t dev_id);
+
+extern sw_error_t
+dess_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t * info);
+
+static sw_error_t
+_dess_port_igmp_property_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable, a_uint32_t item)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (3 >= port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        reg &= ~(0x1UL << ((port_id << 3) + item));
+        reg |= (val << ((port_id << 3) + item));
+
+        HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        reg &= ~(0x1UL << (((port_id - 4) << 3) + item));
+        reg |= (val << (((port_id - 4) << 3) + item));
+
+        HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    return rv;
+}
+
+static sw_error_t
+_dess_port_igmp_property_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable, a_uint32_t item)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (3 >= port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        val = (reg >> ((port_id << 3) + item)) & 0x1UL;
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL;
+    }
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_mports_validity_check(dev_id, pts))
+    {
+        return SW_BAD_PARAM;
+    }
+    val = pts;
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *pts = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 0xf;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0xe;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0xf == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable,
+                               a_uint32_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 1, entry);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, queue, entry);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 0, entry);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, 0, entry);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_CTL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable,
+                               a_uint32_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI_EN, data, entry);
+    if (data)
+    {
+        *enable = A_TRUE;
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI, data, entry);
+        *queue = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *queue = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        if (DESS_MAX_PORT_LEARN_LIMIT_CNT < cnt)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, cnt, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, 0, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, data, reg);
+    if (data)
+    {
+        SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, data, reg);
+        *enable = A_TRUE;
+        *cnt = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *cnt = data;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+        fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+        fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set igmp/mld packets snooping status on a particular port.
+ * @details    Comments:
+ *   After enabling igmp/mld snooping feature on a particular port all kinds
+ *   igmp/mld packets received on this port would be acknowledged by hardware.
+ *   Particular forwarding decision could be setted by fal_igmp_mld_cmd_set.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_igmp_property_set(dev_id, port_id, enable,
+                                      IGMP_MLD_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets snooping status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_igmp_property_get(dev_id, port_id, enable,
+                                      IGMP_MLD_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld packets forwarding command on a particular device.
+ * @details    Comments:
+ *    Particular device may only support parts of forwarding commands.
+ *    This operation will take effect only after enabling igmp/mld snooping
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_igmp_mld_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_igmp_mld_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld join packets hardware acknowledgement status on particular port.
+ * @details    Comments:
+ *    After enabling igmp/mld join feature on a particular port hardware will
+ *    dynamic learning or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_igmp_property_set(dev_id, port_id, enable, JOIN_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_igmp_property_get(dev_id, port_id, enable, JOIN_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @details    Comments:
+ *    After enabling igmp leave feature on a particular port hardware will dynamic
+ *    deleting or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_igmp_property_set(dev_id, port_id, enable, LEAVE_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_igmp_property_get(dev_id, port_id, enable, LEAVE_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld router ports on a particular device.
+ * @details     Comments:
+ *    After enabling igmp/mld join/leave feature on a particular port igmp/mld
+ *    join/leave packets received on this port will be forwarded to router ports.
+ * @param[in] dev_id device id
+ * @param[in] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_igmp_mld_rp_set(dev_id, pts);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld router ports on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_igmp_mld_rp_get(dev_id, pts);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   entry creat hardware will dynamic creat and delete multicast entry,
+ *   otherwise hardware only can change destination ports of existing muticast entry.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_igmp_mld_entry_creat_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_igmp_mld_entry_creat_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the static status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   static status hardware will not age out multicast entry which leardned by hardware,
+ *   otherwise hardware will age out multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_igmp_mld_entry_static_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the static status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_igmp_mld_entry_static_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the leaky status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   leaky status hardware will set leaky flag of multicast entry which leardned by hardware,
+ *   otherwise hardware will not set leaky flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_igmp_mld_entry_leaky_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the leaky status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_igmp_mld_entry_leaky_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @details    Comments:
+ *    After enabling igmp join/leave feature on a particular port hardware will dynamic
+ *    creating or changing multicast entry after receiving igmpv3/mldv2 packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_igmp_mld_entry_v3_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_igmp_mld_entry_v3_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the queue status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   leaky status hardware will set queue flag of multicast entry which leardned by hardware,
+ *   otherwise hardware will not set queue flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable,
+                              a_uint32_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_igmp_mld_entry_queue_set(dev_id, enable, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the queue status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable,
+                              a_uint32_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_igmp_mld_entry_queue_get(dev_id, enable, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IGMP hardware learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_igmp_mld_learn_limit_set(dev_id, port_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IGMP hardware learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_igmp_mld_learn_limit_get(dev_id, port_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IGMP hardware learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                        fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_igmp_mld_learn_exceed_cmd_set(dev_id, port_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IGMP hardware learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                        fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_igmp_mld_learn_exceed_cmd_get(dev_id, port_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+dess_igmp_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->port_igmps_status_set = dess_port_igmps_status_set;
+        p_api->port_igmps_status_get = dess_port_igmps_status_get;
+        p_api->igmp_mld_cmd_set = dess_igmp_mld_cmd_set;
+        p_api->igmp_mld_cmd_get = dess_igmp_mld_cmd_get;
+        p_api->port_igmp_join_set = dess_port_igmp_mld_join_set;
+        p_api->port_igmp_join_get = dess_port_igmp_mld_join_get;
+        p_api->port_igmp_leave_set = dess_port_igmp_mld_leave_set;
+        p_api->port_igmp_leave_get = dess_port_igmp_mld_leave_get;
+        p_api->igmp_rp_set = dess_igmp_mld_rp_set;
+        p_api->igmp_rp_get = dess_igmp_mld_rp_get;
+        p_api->igmp_entry_creat_set = dess_igmp_mld_entry_creat_set;
+        p_api->igmp_entry_creat_get = dess_igmp_mld_entry_creat_get;
+        p_api->igmp_entry_static_set = dess_igmp_mld_entry_static_set;
+        p_api->igmp_entry_static_get = dess_igmp_mld_entry_static_get;
+        p_api->igmp_entry_leaky_set = dess_igmp_mld_entry_leaky_set;
+        p_api->igmp_entry_leaky_get = dess_igmp_mld_entry_leaky_get;
+        p_api->igmp_entry_v3_set = dess_igmp_mld_entry_v3_set;
+        p_api->igmp_entry_v3_get = dess_igmp_mld_entry_v3_get;
+        p_api->igmp_entry_queue_set = dess_igmp_mld_entry_queue_set;
+        p_api->igmp_entry_queue_get = dess_igmp_mld_entry_queue_get;
+        p_api->port_igmp_mld_learn_limit_set = dess_port_igmp_mld_learn_limit_set;
+        p_api->port_igmp_mld_learn_limit_get = dess_port_igmp_mld_learn_limit_get;
+        p_api->port_igmp_mld_learn_exceed_cmd_set = dess_port_igmp_mld_learn_exceed_cmd_set;
+        p_api->port_igmp_mld_learn_exceed_cmd_get = dess_port_igmp_mld_learn_exceed_cmd_get;
+        p_api->igmp_sg_entry_set = dess_igmp_sg_entry_set;
+        p_api->igmp_sg_entry_clear = dess_igmp_sg_entry_clear;
+        p_api->igmp_sg_entry_show = dess_igmp_sg_entry_show;
+        p_api->igmp_sg_entry_query = dess_igmp_sg_entry_query;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/dess/dess_init.c b/qca-ssdk/src/hsl/dess/dess_init.c
new file mode 100644
index 0000000..53eae17
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_init.c
@@ -0,0 +1,343 @@
+/*
+ * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_init DESS_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_mib.h"
+#include "dess_port_ctrl.h"
+#include "dess_portvlan.h"
+#include "dess_vlan.h"
+#include "dess_fdb.h"
+#include "dess_qos.h"
+#include "dess_mirror.h"
+#include "dess_stp.h"
+#include "dess_rate.h"
+#include "dess_misc.h"
+#include "dess_leaky.h"
+#include "dess_igmp.h"
+#include "dess_acl.h"
+#include "dess_led.h"
+#include "dess_cosmap.h"
+#include "dess_ip.h"
+#include "dess_nat.h"
+#if defined(IN_NAT_HELPER)
+#include "dess_nat_helper.h"
+#endif
+#include "dess_sec.h"
+#include "dess_trunk.h"
+#include "dess_interface_ctrl.h"
+#include "dess_reg_access.h"
+#include "dess_reg.h"
+#include "dess_init.h"
+#include <malibu_phy.h>
+
+
+static ssdk_init_cfg * dess_cfg[SW_MAX_NR_DEV] = { 0 };
+a_uint32_t dess_nat_global_status = 0;
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+/* For isis there are five internal PHY devices and seven MAC devices.
+   PORT0 always connect to external DMA device.
+   MAC1..MAC4 connect to internal PHY0..PHY3.
+*/
+
+
+a_uint32_t dess_pbmp_5[PORT_WRAPPER_MAX] = {
+	((1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5)), /*PORT_WRAPPER_PSGMII*/
+	((1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5)), /*PORT_WRAPPER_PSGMII_RGMII5*/
+	((1<<1) | (1<<5)),                            /*PORT_WRAPPER_SGMII0_RGMII5*/
+	((1<<2) | (1<<5)),                            /*PORT_WRAPPER_SGMII1_RGMII5*/
+	((1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5)), /*PORT_WRAPPER_PSGMII_RMII0*/
+	((1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5)), /*PORT_WRAPPER_PSGMII_RMII1*/
+	((1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5)), /*PORT_WRAPPER_PSGMII_RMII0_RMII1*/
+	((1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5)), /*PORT_WRAPPER_SGMII_RGMII4*/
+	((1<<1) | (1<<4)),                            /*PORT_WRAPPER_SGMII0_RGMII4*/
+	((1<<2) | (1<<4)),                            /*PORT_WRAPPER_SGMII1_RGMII4*/
+	((1<<5) | (1<<4)),                            /*PORT_WRAPPER_SGMII4_RGMII4*/
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	((1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5)), /*PORT_WRAPPER_PSGMII_FIBER*/
+	};
+
+a_uint32_t dess_pbmp_2[PORT_WRAPPER_MAX] = {
+	((1<<4) | (1<<5)), 				/*PORT_WRAPPER_PSGMII*/
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	((1<<4) | (1<<5)), 				/*PORT_WRAPPER_PSGMII_FIBER*/
+	};
+
+a_uint32_t dess_get_port_phy_id(void)
+{
+	return dess_cfg[0]->phy_id;
+}
+
+enum ssdk_port_wrapper_cfg dess_get_port_config(void)
+{
+	return dess_cfg[0]->mac_mode;
+}
+
+a_bool_t dess_mac_port_valid_check(fal_port_t port_id)
+{
+	a_uint32_t bitmap = 0;
+	enum ssdk_port_wrapper_cfg cfg;
+	a_uint32_t phy_id;
+
+	cfg = dess_get_port_config();
+	phy_id = dess_get_port_phy_id();
+
+	if (phy_id == MALIBU_1_1_2PORT)
+		bitmap = dess_pbmp_2[cfg];
+	else {
+		bitmap = dess_pbmp_5[cfg];
+	}
+	return SW_IS_PBMP_MEMBER(bitmap, port_id);
+
+}
+
+static sw_error_t
+dess_portproperty_init(a_uint32_t dev_id)
+{
+    hsl_port_prop_t p_type;
+    hsl_dev_t *pdev = NULL;
+    fal_port_t port_id;
+    enum ssdk_port_wrapper_cfg cfg;
+    a_uint32_t bitmap = 0;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return SW_NOT_INITIALIZED;
+
+    cfg = dess_get_port_config();
+    bitmap = dess_pbmp_5[cfg];
+
+    /* for port property set, SSDK should not generate some limitations */
+    for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id++)
+    {
+        if((!SW_IS_PBMP_MEMBER(bitmap, port_id)) && (port_id != pdev->cpu_port_nr))
+            continue;
+
+        hsl_port_prop_portmap_set(dev_id, port_id);
+
+        for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
+        {
+
+            switch (p_type)
+            {
+                case HSL_PP_PHY:
+                    /* Only port0 without PHY device */
+                    if (port_id != pdev->cpu_port_nr)
+                    {
+						if(SW_IS_PBMP_MEMBER(bitmap, port_id))
+                        	SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                    }
+                    break;
+
+                case HSL_PP_INCL_CPU:
+                    /* include cpu port but exclude wan port in some cases */
+                    /* but which port is wan port, we are no meaning */
+					if (port_id == pdev->cpu_port_nr)
+						SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+					if(SW_IS_PBMP_MEMBER(bitmap, port_id))
+                    	SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                    break;
+
+                case HSL_PP_EXCL_CPU:
+                    /* exclude cpu port and wan port in some cases */
+                    /* which port is wan port, we are no meaning but port0 is
+                       always CPU port */
+                    if (port_id != pdev->cpu_port_nr)
+                    {
+						if(SW_IS_PBMP_MEMBER(bitmap, port_id))
+                        	SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                    }
+                    break;
+
+                default:
+                    break;
+            }
+        }
+
+	if (port_id != pdev->cpu_port_nr)
+	{
+		SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+			(dev_id, port_id, port_id - 1));
+	}
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+dess_dev_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    a_uint32_t entry = 0;
+    sw_error_t rv;
+    hsl_dev_t *pdev = NULL;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return SW_NOT_INITIALIZED;
+
+    HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (DESS_DEVICE_ID == entry)
+    {
+	a_uint32_t i = 0, port_nr = 0, tmp = 0;
+	tmp = cfg->port_cfg.lan_bmp | cfg->port_cfg.wan_bmp;
+	for(i = 0; i < SW_MAX_NR_PORT; i++) {
+		if(tmp & (1 << i)) {
+			port_nr++;
+		}
+	}
+	pdev->nr_phy = port_nr;
+	for(i = 0; i < SW_MAX_NR_PORT; i++) {
+		if(cfg->port_cfg.cpu_bmp & (1 << i)) {
+			port_nr++;
+			pdev->cpu_port_nr = i;
+			break;
+		}
+	}
+	if(i >= SW_MAX_NR_PORT)
+		return SW_BAD_VALUE;
+	pdev->nr_ports = port_nr;
+	pdev->nr_vlans = 4096;
+	pdev->hw_vlan_query = A_TRUE;
+	pdev->nr_queue = port_nr;
+	pdev->cpu_mode = cfg->cpu_mode;
+	pdev->wan_bmp = cfg->port_cfg.wan_bmp;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+dess_cleanup(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    if (dess_cfg[dev_id])
+    {
+#if defined(IN_NAT_HELPER)
+        if(dess_nat_global_status)
+            DESS_NAT_HELPER_CLEANUP(rv, dev_id);
+#endif
+
+        DESS_ACL_CLEANUP(rv, dev_id);
+
+        SW_RTN_ON_ERROR(hsl_port_prop_cleanup_by_dev(dev_id));
+
+        aos_mem_free(dess_cfg[dev_id]);
+        dess_cfg[dev_id] = NULL;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Init hsl layer.
+ * @details Comments:
+ *   This operation will init hsl layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+dess_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (NULL == dess_cfg[dev_id])
+    {
+        dess_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg));
+    }
+
+    if (NULL == dess_cfg[dev_id])
+    {
+        return SW_OUT_OF_MEM;
+    }
+
+    aos_mem_copy(dess_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+
+    SW_RTN_ON_ERROR(dess_reg_access_init(dev_id, cfg->reg_mode));
+
+    SW_RTN_ON_ERROR(dess_dev_init(dev_id, cfg));
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+    {
+        sw_error_t rv;
+
+        SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id));
+        SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
+        SW_RTN_ON_ERROR(dess_portproperty_init(dev_id));
+
+        DESS_MIB_INIT(rv, dev_id);
+        DESS_PORT_CTRL_INIT(rv, dev_id);
+        DESS_PORTVLAN_INIT(rv, dev_id);
+        DESS_VLAN_INIT(rv, dev_id);
+        DESS_FDB_INIT(rv, dev_id);
+        DESS_QOS_INIT(rv, dev_id);
+        DESS_STP_INIT(rv, dev_id);
+        DESS_MIRR_INIT(rv, dev_id);
+        DESS_RATE_INIT(rv, dev_id);
+        DESS_MISC_INIT(rv, dev_id);
+        DESS_LEAKY_INIT(rv, dev_id);
+        DESS_IGMP_INIT(rv, dev_id);
+        DESS_ACL_INIT(rv, dev_id);
+        DESS_LED_INIT(rv, dev_id);
+        DESS_COSMAP_INIT(rv, dev_id);
+        DESS_IP_INIT(rv, dev_id);
+        DESS_NAT_INIT(rv, dev_id);
+        DESS_TRUNK_INIT(rv, dev_id);
+        DESS_SEC_INIT(rv, dev_id);
+        DESS_INTERFACE_CTRL_INIT(rv, dev_id);
+
+        {
+            hsl_api_t *p_api;
+
+            SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+            p_api->dev_clean   = dess_cleanup;
+        }
+#if 0
+#if defined(IN_NAT_HELPER)
+		if(!dess_nat_global_status) {
+        	DESS_NAT_HELPER_INIT(rv, dev_id);
+			dess_nat_global_status = 1;
+		}
+#endif
+#endif
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/dess/dess_interface_ctrl.c b/qca-ssdk/src/hsl/dess/dess_interface_ctrl.c
new file mode 100755
index 0000000..f6396f9
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_interface_ctrl.c
@@ -0,0 +1,299 @@
+/*
+ * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_interface_ctrl DESS_INTERFACE_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_interface_ctrl.h"
+#include "dess_reg.h"
+
+
+#define DESS_PHY_MODE_PHY_ID  4
+#define DESS_LPI_PORT1_OFFSET 4
+#define DESS_LPI_BIT_STEP     2
+#define DESS_LPI_ENABLE     3
+
+#define DESS_MAC4  4
+#define DESS_MAC5  5
+
+static sw_error_t
+_dess_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv = SW_OK;
+    a_uint32_t reg = 0, field, offset, device_id;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg);
+    if (DESS_DEVICE_ID != device_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        field  = DESS_LPI_ENABLE;
+    }
+    else if (A_FALSE == enable)
+    {
+        field  = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    offset = (port_id - 1) * DESS_LPI_BIT_STEP + DESS_LPI_PORT1_OFFSET;
+    reg &= (~(DESS_LPI_ENABLE << offset));
+    reg |= (field << offset);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, EEE_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv = SW_OK;
+    a_uint32_t reg = 0, field, offset, device_id;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg);
+    if (DESS_DEVICE_ID != device_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    offset = (port_id - 1) * DESS_LPI_BIT_STEP + DESS_LPI_PORT1_OFFSET;
+    field = (reg >> offset) & 0x3;
+
+    if (field == DESS_LPI_ENABLE)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t reg = 0, field;
+
+	HSL_DEV_ID_CHECK(dev_id);
+
+
+	if (FAL_MAC_MODE_RMII == config->mac_mode)
+	{
+		HSL_REG_ENTRY_GET(rv, dev_id, RGMII_CTRL, 0,
+						  (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+		if (port_id == DESS_MAC4) {
+			SW_GET_FIELD_BY_REG(RGMII_CTRL, RMII1_MASTER_EN, field, reg);
+			if(field == config->config.rmii.master_mode)
+				return rv;
+			SW_SET_REG_BY_FIELD(RGMII_CTRL, RMII1_MASTER_EN, config->config.rmii.master_mode, reg);
+		}
+		else if (port_id == DESS_MAC5) {
+			SW_GET_FIELD_BY_REG(RGMII_CTRL, RMII0_MASTER_EN, field, reg);
+			if(field == config->config.rmii.master_mode)
+				return rv;
+			SW_SET_REG_BY_FIELD(RGMII_CTRL, RMII1_MASTER_EN, config->config.rmii.master_mode, reg);
+		}
+		else
+		{
+			return SW_BAD_PARAM;
+		}
+		HSL_REG_ENTRY_SET(rv, dev_id, RGMII_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+	}
+	else
+	{
+		return SW_BAD_PARAM;
+	}
+
+	return rv;
+}
+
+static sw_error_t
+_dess_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t reg = 0, field;
+
+	HSL_DEV_ID_CHECK(dev_id);
+
+
+	if (FAL_MAC_MODE_RMII == config->mac_mode)
+	{
+		HSL_REG_ENTRY_GET(rv, dev_id, RGMII_CTRL, 0,
+						  (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+		if (port_id == DESS_MAC4) {
+			SW_GET_FIELD_BY_REG(RGMII_CTRL, RMII1_MASTER_EN, field, reg);
+			config->config.rmii.master_mode = field;
+		}
+		else if (port_id == DESS_MAC5) {
+			SW_GET_FIELD_BY_REG(RGMII_CTRL, RMII0_MASTER_EN, field, reg);
+			config->config.rmii.master_mode = field;
+		}
+		else
+		{
+			return SW_BAD_PARAM;
+		}
+	}
+	else
+	{
+		return SW_BAD_PARAM;
+	}
+
+	return rv;
+}
+
+
+/**
+  * @brief Set 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_3az_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Get 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_3az_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+/**
+  * @brief Set interface mode on RGMII/RMII.
+ * @param[in] dev_id device id
+ * @param[in] delay
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _dess_interface_mac_mode_set(dev_id, port_id, config);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+
+/**
+  * @brief Get interface mode on RGMII/RMII.
+ * @param[in] dev_id device id
+ * @param[in] mca_id MAC device ID
+ * @param[out] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_interface_mac_mode_get(dev_id, port_id, config);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+
+
+sw_error_t
+dess_interface_ctrl_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->port_3az_status_set = dess_port_3az_status_set;
+        p_api->port_3az_status_get = dess_port_3az_status_get;
+		p_api->interface_mac_mode_set = dess_interface_mac_mode_set;
+        p_api->interface_mac_mode_get = dess_interface_mac_mode_get;
+
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/dess/dess_ip.c b/qca-ssdk/src/hsl/dess/dess_ip.c
new file mode 100755
index 0000000..5e636a3
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_ip.c
@@ -0,0 +1,3668 @@
+/*
+ * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_ip DESS_IP
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_ip.h"
+#include "dess_reg.h"
+
+#define DESS_HOST_ENTRY_DATA0_ADDR              0x0e80
+#define DESS_HOST_ENTRY_DATA1_ADDR              0x0e84
+#define DESS_HOST_ENTRY_DATA2_ADDR              0x0e88
+#define DESS_HOST_ENTRY_DATA3_ADDR              0x0e8c
+#define DESS_HOST_ENTRY_DATA4_ADDR              0x0e90
+#define DESS_HOST_ENTRY_DATA5_ADDR              0x0e94
+#define DESS_HOST_ENTRY_DATA6_ADDR              0x0e98
+#define DESS_HOST_ENTRY_DATA7_ADDR              0x0e58
+
+#define DESS_HOST_ENTRY_REG_NUM                 8
+
+#define DESS_HOST_ENTRY_FLUSH                   1
+#define DESS_HOST_ENTRY_ADD                     2
+#define DESS_HOST_ENTRY_DEL                     3
+#define DESS_HOST_ENTRY_NEXT                    4
+#define DESS_HOST_ENTRY_SEARCH                  5
+
+#define DESS_ENTRY_ARP                          3
+
+#define DESS_INTF_MAC_ADDR_NUM                  8
+#define DESS_INTF_MAC_TBL0_ADDR                 0x5a900
+#define DESS_INTF_MAC_TBL1_ADDR                 0x5a904
+#define DESS_INTF_MAC_TBL2_ADDR                 0x5a908
+#define DESS_INTF_MAC_EDIT0_ADDR                0x02000
+#define DESS_INTF_MAC_EDIT1_ADDR                0x02004
+#define DESS_INTF_MAC_EDIT2_ADDR                0x02008
+
+#define DESS_IP6_BASE_ADDR                      0x0470
+
+#define DESS_HOST_ENTRY_NUM                     128
+
+#define DESS_IP_COUTER_ADDR                     0x2b000
+
+#define DESS_DEFAULT_ROUTE_NUM                  8
+#define DESS_IP4_DEFAULT_ROUTE_TBL_ADDR                 0x004c4
+#define DESS_IP6_DEFAULT_ROUTE_TBL_ADDR                 0x004e4
+#define DESS_HOST_ROUTE_NUM                  16
+#define DESS_IP4_HOST_ROUTE_TBL0_ADDR                 0x5b000
+#define DESS_IP4_HOST_ROUTE_TBL1_ADDR                 0x5b004
+#define DESS_IP6_HOST_ROUTE_TBL0_ADDR                 0x5b100
+#define DESS_IP6_HOST_ROUTE_TBL1_ADDR                 0x5b104
+#define DESS_IP6_HOST_ROUTE_TBL2_ADDR                 0x5b108
+#define DESS_IP6_HOST_ROUTE_TBL3_ADDR                 0x5b10c
+#define DESS_IP6_HOST_ROUTE_TBL4_ADDR                 0x5b110
+
+
+static a_uint32_t dess_mac_snap[SW_MAX_NR_DEV] = { 0 };
+static fal_intf_mac_entry_t dess_intf_snap[SW_MAX_NR_DEV][DESS_INTF_MAC_ADDR_NUM];
+
+extern aos_lock_t dess_nat_lock;
+
+
+static void
+_dess_ip_pt_learn_save(a_uint32_t dev_id, a_uint32_t * status)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    if (SW_OK != rv)
+    {
+        return;
+    }
+
+    *status = (data & 0x7f7f);
+
+    data &= 0xffff8080;
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return;
+}
+
+static void
+_dess_ip_pt_learn_restore(a_uint32_t dev_id, a_uint32_t status)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    if (SW_OK != rv)
+    {
+        return;
+    }
+
+    data &= 0xffff8080;
+    data |= (status & 0x7f7f);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return;
+}
+
+static sw_error_t
+_dess_ip_feature_check(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (DESS_DEVICE_ID == entry)
+    {
+        return SW_OK;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+}
+
+static sw_error_t
+_dess_ip_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id,
+                     a_uint32_t counter[2])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    addr = DESS_IP_COUTER_ADDR + (cnt_id << 3);
+    for (i = 0; i < 2; i++)
+    {
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(counter[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        addr += 4;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_host_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op)
+{
+    a_uint32_t busy = 1, i = 0x9000000, entry = 0, j, try_num;
+    a_uint32_t learn_status = 0, data = 0;
+    sw_error_t rv;
+
+    while (busy && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+                          sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        //printk("IP first entry is 0x%x\r\n", entry);
+        SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry);
+    }
+
+    if (i == 0)
+    {
+	printk("host entry busy!\n");
+        return SW_BUSY;
+    }
+
+
+    /* hardware requirements, we should disable ARP learn at first */
+    /* and maybe we should try several times... */
+    _dess_ip_pt_learn_save(dev_id, &learn_status);
+
+    //printk("data0=0x%x\n", data);
+    if(learn_status) {
+        aos_mdelay(800);
+        HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+        //printk("data1=0x%x\n", data);
+
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_BUSY, 1, entry);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_SEL, entry_type, entry);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, ENTRY_FUNC, op, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+			sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (learn_status)
+    {
+        try_num = 300;
+    }
+    else
+    {
+        try_num = 1;
+    }
+
+    for (j = 0; j < try_num; j++)
+    {
+        busy = 1;
+	i = 0x9000000;
+        while (busy && --i)
+        {
+            HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+                              sizeof (a_uint32_t));
+	    //printk("IP second entry is 0x%x\r\n", entry);
+            if (SW_OK != rv)
+            {
+                _dess_ip_pt_learn_restore(dev_id, learn_status);
+                return rv;
+            }
+            SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry);
+        }
+
+        if (i == 0)
+        {
+            _dess_ip_pt_learn_restore(dev_id, learn_status);
+            return SW_BUSY;
+        }
+
+        /* hardware requirement, we should read again... */
+        HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+                          sizeof (a_uint32_t));
+        if (SW_OK != rv)
+        {
+            _dess_ip_pt_learn_restore(dev_id, learn_status);
+            return rv;
+        }
+
+        /* operation success...... */
+        SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, busy, entry);
+        if (busy)
+        {
+            _dess_ip_pt_learn_restore(dev_id, learn_status);
+            return SW_OK;
+        }
+    }
+
+    _dess_ip_pt_learn_restore(dev_id, learn_status);
+    if (DESS_HOST_ENTRY_NEXT == op)
+    {
+        return SW_NO_MORE;
+    }
+    else if (DESS_HOST_ENTRY_SEARCH == op)
+    {
+        return SW_NOT_FOUND;
+    }
+    else if (DESS_HOST_ENTRY_DEL == op)
+    {
+        return SW_NOT_FOUND;
+    }
+    else
+    {
+        return SW_FAIL;
+    }
+}
+
+static sw_error_t
+_dess_ip_intf_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry,
+                       a_uint32_t * hw_intf)
+{
+    sw_error_t rv;
+    a_uint32_t addr, lvid, hvid, tbl[3] = {0}, i;
+    a_uint32_t sw_intf = entry->intf_id;
+    a_uint32_t vid_offset;
+
+    for (i = 0; i < DESS_INTF_MAC_ADDR_NUM; i++)
+    {
+        if (dess_mac_snap[dev_id] & (0x1 << i))
+        {
+            addr = DESS_INTF_MAC_TBL0_ADDR + (i << 4) + 4;
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[1])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            addr = DESS_INTF_MAC_TBL0_ADDR + (i << 4) + 8;
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[2])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, hvid, tbl[1]);
+            SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, lvid, tbl[2]);
+            hvid |= ((lvid & 0xff) << 4);
+
+            SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl[1]);
+
+            if ((lvid <= sw_intf) && (hvid >= sw_intf))
+            {
+                vid_offset = entry->expect_vid ? (entry->expect_vid - lvid) : (sw_intf - lvid);
+                *hw_intf = (vid_offset << 3) | i;
+                return SW_OK;
+            }
+        }
+    }
+
+    return SW_BAD_PARAM;
+}
+
+static sw_error_t
+_dess_ip_intf_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_intf,
+                       a_uint32_t * sw_intf)
+{
+    sw_error_t rv;
+    a_uint32_t addr, lvid, tbl = 0, i;
+
+    i = hw_intf & 0x7;
+
+    addr = DESS_INTF_MAC_TBL0_ADDR + (i << 4) + 4;
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&tbl), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl);
+    *sw_intf = lvid + (hw_intf >> 3);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    if (255 < ((*time + 5) / 6))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = ((*time + 5) / 6);
+    *time = data * 6;
+
+    HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *time = data * 6;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_host_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry,
+                    a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    if (FAL_IP_IP4_ADDR & entry->flags)
+    {
+        reg[0] = entry->ip4_addr;
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 0, reg[6]);
+    }
+
+    if (FAL_IP_IP6_ADDR & entry->flags)
+    {
+        reg[0] = entry->ip6_addr.ul[3];
+        reg[1] = entry->ip6_addr.ul[2];
+        reg[2] = entry->ip6_addr.ul[1];
+        reg[3] = entry->ip6_addr.ul[0];
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 1, reg[6]);
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR2, entry->mac_addr.uc[2], reg[4]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR3, entry->mac_addr.uc[3], reg[4]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR4, entry->mac_addr.uc[4], reg[4]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR5, entry->mac_addr.uc[5], reg[4]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY5, MAC_ADDR0, entry->mac_addr.uc[0], reg[5]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY5, MAC_ADDR1, entry->mac_addr.uc[1], reg[5]);
+
+    rv = _dess_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data);
+
+    SW_RTN_ON_ERROR(rv);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY5, INTF_ID, data, reg[5]);
+
+#if 0
+    if (A_TRUE != hsl_port_prop_check(dev_id, entry->port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+#endif
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]);
+
+    if (FAL_IP_CPU_ADDR & entry->flags)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY5, CPU_ADDR, 1, reg[5]);
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY6, VRF_ID, entry->vrf_id, reg[6]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY6, LB_BIT, entry->lb_num, reg[6]);
+
+    if ((A_TRUE == entry->mirror_en) && (FAL_MAC_FRWRD != entry->action))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->counter_en)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_EN, 1, reg[6]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_IDX, entry->counter_id, reg[6]);
+    }
+
+    if (FAL_MAC_DROP == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, 7, reg[5]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 3, reg[6]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 1, reg[6]);
+    }
+    else if (FAL_MAC_CPY_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 2, reg[6]);
+    }
+    else
+    {
+        if (A_TRUE == entry->mirror_en)
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 0, reg[6]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 3, reg[6]);
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_host_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[],
+                    fal_host_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, cnt[2] = {0};
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY6, IP_VER, data, reg[6]);
+    if (data)
+    {
+        entry->ip6_addr.ul[0] = reg[3];
+        entry->ip6_addr.ul[1] = reg[2];
+        entry->ip6_addr.ul[2] = reg[1];
+        entry->ip6_addr.ul[3] = reg[0];
+        entry->flags |= FAL_IP_IP6_ADDR;
+    }
+    else
+    {
+        entry->ip4_addr = reg[0];
+        entry->flags |= FAL_IP_IP4_ADDR;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR2, entry->mac_addr.uc[2], reg[4]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR3, entry->mac_addr.uc[3], reg[4]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR4, entry->mac_addr.uc[4], reg[4]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR5, entry->mac_addr.uc[5], reg[4]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY5, MAC_ADDR0, entry->mac_addr.uc[0], reg[5]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY5, MAC_ADDR1, entry->mac_addr.uc[1], reg[5]);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY5, INTF_ID, data, reg[5]);
+    rv = _dess_ip_intf_hw_to_sw(dev_id, data, &(entry->intf_id));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY5, CPU_ADDR, data, reg[5]);
+    if (data)
+    {
+        entry->flags |= FAL_IP_CPU_ADDR;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY6, VRF_ID, entry->vrf_id, reg[6]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY6, LB_BIT, entry->lb_num, reg[6]);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY6, CNT_EN, data, reg[6]);
+    if (data)
+    {
+        entry->counter_en = A_TRUE;
+        SW_GET_FIELD_BY_REG(HOST_ENTRY6, CNT_IDX, entry->counter_id, reg[6]);
+
+        rv = _dess_ip_counter_get(dev_id, entry->counter_id, cnt);
+        SW_RTN_ON_ERROR(rv);
+
+        entry->packet = cnt[0];
+        entry->byte = cnt[1];
+    }
+    else
+    {
+        entry->counter_en = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY6, PPPOE_EN, data, reg[6]);
+    if (data)
+    {
+        entry->pppoe_en = A_TRUE;
+        SW_GET_FIELD_BY_REG(HOST_ENTRY6, PPPOE_IDX, data, reg[6]);
+        entry->pppoe_id = data;
+    }
+    else
+    {
+        entry->pppoe_en = A_FALSE;
+    }
+
+    if (7 == entry->port_id)
+    {
+        entry->port_id = 0;
+        entry->action = FAL_MAC_DROP;
+    }
+    else
+    {
+        SW_GET_FIELD_BY_REG(HOST_ENTRY6, ACTION, data, reg[6]);
+        entry->action = FAL_MAC_FRWRD;
+        if (0 == data)
+        {
+            entry->mirror_en = A_TRUE;
+        }
+        else if (1 == data)
+        {
+            entry->action = FAL_MAC_RDT_TO_CPU;
+        }
+        else if (2 == data)
+        {
+            entry->action = FAL_MAC_CPY_TO_CPU;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_host_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    for (i = 0; i < DESS_HOST_ENTRY_REG_NUM; i++)
+    {
+        if((DESS_HOST_ENTRY_REG_NUM - 1) == i)
+        {
+            addr = DESS_HOST_ENTRY_DATA7_ADDR;
+        }
+        else
+        {
+            addr = DESS_HOST_ENTRY_DATA0_ADDR + (i << 2);
+        }
+
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&reg[i]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_host_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    for (i = 0; i < DESS_HOST_ENTRY_REG_NUM; i++)
+    {
+        if((DESS_HOST_ENTRY_REG_NUM - 1) == i)
+        {
+            addr = DESS_HOST_ENTRY_DATA7_ADDR;
+        }
+        else
+        {
+            addr = DESS_HOST_ENTRY_DATA0_ADDR + (i << 2);
+        }
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&reg[i]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_host_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+	aos_lock_bh(&dess_nat_lock);
+    rv = _dess_host_down_to_hw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_ADD);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&reg[7]),
+                      sizeof (a_uint32_t));
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+	aos_unlock_bh(&dess_nat_lock);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                  fal_host_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }, op = DESS_HOST_ENTRY_FLUSH;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_IP_ENTRY_ID_EN & del_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_IP_ENTRY_IPADDR_EN & del_mode)
+    {
+        op = DESS_HOST_ENTRY_DEL;
+        if (FAL_IP_IP4_ADDR & entry->flags)
+        {
+            reg[0] = entry->ip4_addr;
+        }
+
+        if (FAL_IP_IP6_ADDR & entry->flags)
+        {
+            reg[0] = entry->ip6_addr.ul[3];
+            reg[1] = entry->ip6_addr.ul[2];
+            reg[2] = entry->ip6_addr.ul[1];
+            reg[3] = entry->ip6_addr.ul[0];
+            SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 1, reg[6]);
+        }
+    }
+
+    if (FAL_IP_ENTRY_INTF_EN & del_mode)
+    {
+        rv = _dess_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data);
+        SW_RTN_ON_ERROR(rv);
+
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_VID, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY5, INTF_ID, data, reg[5]);
+    }
+
+    if (FAL_IP_ENTRY_PORT_EN & del_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SP, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]);
+    }
+
+    if (FAL_IP_ENTRY_STATUS_EN & del_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]);
+    }
+	aos_lock_bh(&dess_nat_lock);
+    rv = _dess_host_down_to_hw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, op);
+	aos_unlock_bh(&dess_nat_lock);
+
+    return rv;
+}
+
+static sw_error_t
+_dess_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                  fal_host_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_IP_ENTRY_IPADDR_EN != get_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_IP_IP4_ADDR & entry->flags)
+    {
+        reg[0] = entry->ip4_addr;
+    }
+    else
+    {
+        reg[0] = entry->ip6_addr.ul[3];
+        reg[1] = entry->ip6_addr.ul[2];
+        reg[2] = entry->ip6_addr.ul[1];
+        reg[3] = entry->ip6_addr.ul[0];
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 1, reg[6]);
+    }
+	aos_lock_bh(&dess_nat_lock);
+    rv = _dess_host_down_to_hw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP,
+                                 DESS_HOST_ENTRY_SEARCH);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_host_up_to_sw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    aos_mem_zero(entry, sizeof (fal_host_entry_t));
+
+    rv = _dess_host_hw_to_sw(dev_id, reg, entry);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    if (!(entry->status))
+    {
+		aos_unlock_bh(&dess_nat_lock);
+        return SW_NOT_FOUND;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&reg[7]),
+                      sizeof (a_uint32_t));
+	aos_unlock_bh(&dess_nat_lock);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                   fal_host_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t idx, data, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id)
+    {
+        idx = DESS_HOST_ENTRY_NUM - 1;
+    }
+    else
+    {
+        if ((DESS_HOST_ENTRY_NUM - 1) == entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = entry->entry_id;
+        }
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, idx, reg[7]);
+
+    if (FAL_IP_ENTRY_INTF_EN & next_mode)
+    {
+        rv = _dess_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data);
+        SW_RTN_ON_ERROR(rv);
+
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_VID, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY5, INTF_ID, data, reg[5]);
+    }
+
+    if (FAL_IP_ENTRY_PORT_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SP, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]);
+    }
+
+    if (FAL_IP_ENTRY_STATUS_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]);
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY6, VRF_ID, entry->vrf_id, reg[6]);
+	aos_lock_bh(&dess_nat_lock);
+    rv = _dess_host_down_to_hw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_NEXT);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_host_up_to_sw(dev_id, reg);
+	aos_unlock_bh(&dess_nat_lock);
+    SW_RTN_ON_ERROR(rv);
+
+    aos_mem_zero(entry, sizeof (fal_host_entry_t));
+
+    rv = _dess_host_hw_to_sw(dev_id, reg, entry);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!(entry->status))
+    {
+        return SW_NO_MORE;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                           a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }, tbl[DESS_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    tbl_idx = (entry_id - 1) & 0x7f;
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+
+    rv = _dess_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_NEXT);
+    if (SW_OK != rv)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    rv = _dess_host_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+    if (entry_id != tbl_idx)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    tbl[0] = reg[0];
+    tbl[1] = reg[1];
+    tbl[2] = reg[2];
+    tbl[3] = reg[3];
+    tbl[6] = (reg[6] >> 15) << 15;
+    rv = _dess_host_down_to_hw(dev_id, tbl);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_DEL);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_EN, 0, reg[6]);
+    }
+    else if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_EN, 1, reg[6]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_IDX, cnt_id, reg[6]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    reg[7] = 0x0;
+    rv = _dess_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_ADD);
+    return rv;
+}
+
+static sw_error_t
+_dess_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                         a_uint32_t pppoe_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }, tbl[DESS_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    tbl_idx = (entry_id - 1) & 0x7f;
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+	aos_lock_bh(&dess_nat_lock);
+    rv = _dess_host_down_to_hw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_NEXT);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_host_up_to_sw(dev_id, reg);
+	aos_unlock_bh(&dess_nat_lock);
+    if (SW_OK != rv)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+    if (entry_id != tbl_idx)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, PPPOE_EN, 0, reg[6]);
+    }
+    else if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, PPPOE_EN, 1, reg[6]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, PPPOE_IDX, pppoe_id, reg[6]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    tbl[0] = reg[0];
+    tbl[1] = reg[1];
+    tbl[2] = reg[2];
+    tbl[3] = reg[3];
+    tbl[6] = (reg[6] >> 15) << 15;
+	aos_lock_bh(&dess_nat_lock);
+    rv = _dess_host_down_to_hw(dev_id, tbl);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_DEL);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    reg[7] = 0x0;
+    rv = _dess_host_down_to_hw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_ADD);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_host_up_to_sw(dev_id, reg);
+	aos_unlock_bh(&dess_nat_lock);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t flags)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_ARP_LEARN_REQ & flags)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        data &= (~(0x1 << port_id));
+    }
+
+    if (FAL_ARP_LEARN_ACK & flags)
+    {
+        data |= (0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id));
+    }
+    else
+    {
+        data &= (~(0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id)));
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * flags)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *flags = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data & (0x1 << port_id))
+    {
+        *flags |= FAL_ARP_LEARN_REQ;
+    }
+
+    if (data & (0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id)))
+    {
+        *flags |= FAL_ARP_LEARN_ACK;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_ARP_LEARN_ALL == mode)
+    {
+        data = 1;
+    }
+    else if (FAL_ARP_LEARN_LOCAL == mode)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *mode = FAL_ARP_LEARN_ALL;
+    }
+    else
+    {
+        *mode = FAL_ARP_LEARN_LOCAL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NO_SOURCE_GUARD < mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = 0;
+    if (FAL_MAC_IP_GUARD == mode)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_IP_PORT_GUARD == mode)
+    {
+        data = 2;
+    }
+    else if (FAL_MAC_IP_VLAN_GUARD == mode)
+    {
+        data = 3;
+    }
+    else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode)
+    {
+        data = 4;
+    }
+    reg &= (~(0x7 << (port_id * 3)));
+    reg |= ((data & 0x7) << (port_id * 3));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL1, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = 1;
+    if (FAL_NO_SOURCE_GUARD == mode)
+    {
+        data = 0;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, SP_CHECK_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (reg >> (port_id * 3)) & 0x7;
+
+    *mode = FAL_NO_SOURCE_GUARD;
+    if (1 == data)
+    {
+        *mode = FAL_MAC_IP_GUARD;
+    }
+    else if (2 == data)
+    {
+        *mode = FAL_MAC_IP_PORT_GUARD;
+    }
+    else if (3 == data)
+    {
+        *mode = FAL_MAC_IP_VLAN_GUARD;
+    }
+    else if (4 == data)
+    {
+        *mode = FAL_MAC_IP_PORT_VLAN_GUARD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        data = 0;
+    }
+    else if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 2;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        *cmd = FAL_MAC_FRWRD;
+    }
+    else if (1 == data)
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NO_SOURCE_GUARD < mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = 0;
+    if (FAL_MAC_IP_GUARD == mode)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_IP_PORT_GUARD == mode)
+    {
+        data = 2;
+    }
+    else if (FAL_MAC_IP_VLAN_GUARD == mode)
+    {
+        data = 3;
+    }
+    else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode)
+    {
+        data = 4;
+    }
+    reg &= (~(0x7 << (port_id * 3)));
+    reg |= ((data & 0x7) << (port_id * 3));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (reg >> (port_id * 3)) & 0x7;
+
+    *mode = FAL_NO_SOURCE_GUARD;
+    if (1 == data)
+    {
+        *mode = FAL_MAC_IP_GUARD;
+    }
+    else if (2 == data)
+    {
+        *mode = FAL_MAC_IP_PORT_GUARD;
+    }
+    else if (3 == data)
+    {
+        *mode = FAL_MAC_IP_VLAN_GUARD;
+    }
+    else if (4 == data)
+    {
+        *mode = FAL_MAC_IP_PORT_VLAN_GUARD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        data = 0;
+    }
+    else if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 2;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        *cmd = FAL_MAC_FRWRD;
+    }
+    else if (1 == data)
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, L3_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t route_en = 0, l3_en = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN,
+                      (a_uint8_t *) (&route_en), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, L3_EN,
+                      (a_uint8_t *) (&l3_en), sizeof (a_uint32_t))
+    SW_RTN_ON_ERROR(rv);
+
+    if (route_en && l3_en)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_dess_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, j, found = 0, addr, tbl[3] = { 0 };
+    fal_intf_mac_entry_t * intf_entry = NULL;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < DESS_INTF_MAC_ADDR_NUM; i++)
+    {
+        if (dess_mac_snap[dev_id] & (0x1 << i))
+        {
+            intf_entry = &(dess_intf_snap[dev_id][i]);
+            if ((entry->vid_low == intf_entry->vid_low)
+                    && (entry->vid_high == intf_entry->vid_high))
+            {
+                /* all same, return OK directly */
+                if (!aos_mem_cmp(intf_entry, entry, sizeof(fal_intf_mac_entry_t)))
+                {
+                    return SW_OK;
+                }
+                else
+                {
+                    /* update entry */
+                    found = 1;
+                    break;
+                }
+            }
+            else
+            {
+                /* entry VID cross border, not support */
+                if ((entry->vid_low >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high))
+                {
+                    return SW_BAD_PARAM;
+                }
+
+                /* entry VID cross border, not support */
+                if ((entry->vid_high >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high))
+                {
+                    return SW_BAD_PARAM;
+                }
+            }
+        }
+    }
+
+    if (!found)
+    {
+        for (i = 0; i < DESS_INTF_MAC_ADDR_NUM; i++)
+        {
+            if (!(dess_mac_snap[dev_id] & (0x1 << i)))
+            {
+                intf_entry = &(dess_intf_snap[dev_id][i]);
+                break;
+            }
+        }
+    }
+
+    if (DESS_INTF_MAC_ADDR_NUM == i)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    if ((A_FALSE == entry->ip4_route) && (A_FALSE == entry->ip6_route))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (512 <= (entry->vid_high - entry->vid_low))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2],
+                        tbl[0]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3],
+                        tbl[0]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4],
+                        tbl[0]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5],
+                        tbl[0]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0],
+                        tbl[1]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1],
+                        tbl[1]);
+
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_HIGH0, (entry->vid_high & 0xf),
+                        tbl[1]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, VID_HIGH1, (entry->vid_high >> 4),
+                        tbl[2]);
+
+    if (A_TRUE == entry->ip4_route)
+    {
+        SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP4_ROUTE, 1, tbl[2]);
+    }
+
+    if (A_TRUE == entry->ip6_route)
+    {
+        SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP6_ROUTE, 1, tbl[2]);
+    }
+
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, VRF_ID, entry->vrf_id, tbl[2]);
+
+    for (j = 0; j < 2; j++)
+    {
+        addr = DESS_INTF_MAC_EDIT0_ADDR + (i << 4) + (j << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    for (j = 0; j < 3; j++)
+    {
+        addr = DESS_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    dess_mac_snap[dev_id] |= (0x1 << i);
+    *intf_entry = *entry;
+    entry->entry_id = i;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                        fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t addr, tbl[3] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!(FAL_IP_ENTRY_ID_EN & del_mode))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (DESS_INTF_MAC_ADDR_NUM <= entry->entry_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    /* clear valid bits */
+    addr = DESS_INTF_MAC_TBL2_ADDR + (entry->entry_id << 4);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    dess_mac_snap[dev_id] &= (~(0x1 << entry->entry_id));
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                         fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, j, idx, addr, tbl[3] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id)
+    {
+        idx = 0;
+    }
+    else
+    {
+        if ((DESS_INTF_MAC_ADDR_NUM - 1) == entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = entry->entry_id + 1;
+        }
+    }
+
+    for (i = idx; i < DESS_INTF_MAC_ADDR_NUM; i++)
+    {
+        if (dess_mac_snap[dev_id] & (0x1 << i))
+        {
+            break;
+        }
+    }
+
+    if (DESS_INTF_MAC_ADDR_NUM == i)
+    {
+        return SW_NO_MORE;
+    }
+
+    for (j = 0; j < 3; j++)
+    {
+        addr = DESS_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    aos_mem_zero(entry, sizeof (fal_intf_mac_entry_t));
+
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2],
+                        tbl[0]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3],
+                        tbl[0]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4],
+                        tbl[0]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5],
+                        tbl[0]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0],
+                        tbl[1]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1],
+                        tbl[1]);
+
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, j, tbl[1]);
+    entry->vid_high = j & 0xf;
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, j, tbl[2]);
+    entry->vid_high |= ((j & 0xff) << 4);
+
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP4_ROUTE, j, tbl[2]);
+    if (j)
+    {
+        entry->ip4_route = A_TRUE;
+    }
+
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP6_ROUTE, j, tbl[2]);
+    if (j)
+    {
+        entry->ip6_route = A_TRUE;
+    }
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VRF_ID, entry->vrf_id, tbl[2]);
+
+    entry->entry_id = i;
+    return SW_OK;
+}
+
+#define DESS_WCMP_ENTRY_MAX_ID    3
+#define DESS_WCMP_HASH_MAX_NUM    16
+#define DESS_IP_ENTRY_MAX_ID      127
+
+#define DESS_WCMP_HASH_TBL_ADDR   0x0e10
+#define DESS_WCMP_NHOP_TBL_ADDR   0x0e20
+
+static sw_error_t
+_dess_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+    sw_error_t rv;
+    a_uint32_t i, j, addr, data;
+    a_uint8_t  idx, ptr[4] = { 0 }, pos[16] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (DESS_WCMP_ENTRY_MAX_ID < wcmp_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (DESS_WCMP_HASH_MAX_NUM < wcmp->nh_nr)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = 0; i < wcmp->nh_nr; i++)
+    {
+        if (DESS_IP_ENTRY_MAX_ID < wcmp->nh_id[i])
+        {
+            return SW_BAD_PARAM;
+        }
+
+        idx = 4;
+        for (j = 0; j < 4; j++)
+        {
+            if (ptr[j] & 0x80)
+            {
+                if ((ptr[j] & 0x7f) == wcmp->nh_id[i])
+                {
+                    idx = j;
+                    break;
+                }
+            }
+            else
+            {
+                idx = j;
+            }
+        }
+
+        if (4 == idx)
+        {
+            return SW_BAD_PARAM;
+        }
+        else
+        {
+            ptr[idx] = (wcmp->nh_id[i] & 0x7f) | 0x80;
+            pos[i]   = idx;
+        }
+    }
+
+    data = 0;
+    for (j = 0; j < 4; j++)
+    {
+        data |= (ptr[j] << (j << 3));
+    }
+
+    addr = DESS_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = 0;
+    for (j = 0; j < 16; j++)
+    {
+        data |= (pos[j] << (j << 1));
+    }
+
+    addr = DESS_WCMP_HASH_TBL_ADDR + (wcmp_id << 2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+    sw_error_t rv;
+    a_uint32_t i, addr, data = 0;
+    a_uint8_t  ptr[4] = { 0 }, pos[16] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (DESS_WCMP_ENTRY_MAX_ID < wcmp_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    wcmp->nh_nr = DESS_WCMP_HASH_MAX_NUM;
+
+    addr = DESS_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < 4; i++)
+    {
+        ptr[i] = (data >> (i << 3)) & 0x7f;
+    }
+
+    addr = DESS_WCMP_HASH_TBL_ADDR + (wcmp_id << 2);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < 16; i++)
+    {
+        pos[i] = (data >> (i << 1)) & 0x3;
+    }
+
+    for (i = 0; i < 16; i++)
+    {
+        wcmp->nh_id[i] = ptr[pos[i]];
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_WCMP_HASH_KEY_SIP & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 0, data);
+    }
+
+    if (FAL_WCMP_HASH_KEY_DIP & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 0, data);
+    }
+
+    if (FAL_WCMP_HASH_KEY_SPORT & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 0, data);
+    }
+
+    if (FAL_WCMP_HASH_KEY_DPORT & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 0, data);
+    }
+
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_CTRL, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, field;
+
+    *hash_mode = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SIP, field, data);
+    if (field)
+    {
+        *hash_mode |= FAL_WCMP_HASH_KEY_SIP;
+    }
+
+    SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DIP, field, data);
+    if (field)
+    {
+        *hash_mode |= FAL_WCMP_HASH_KEY_DIP;
+    }
+
+    SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SP, field, data);
+    if (field)
+    {
+        *hash_mode |= FAL_WCMP_HASH_KEY_SPORT;
+    }
+
+    SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DP, field, data);
+    if (field)
+    {
+        *hash_mode |= FAL_WCMP_HASH_KEY_DPORT;
+    }
+
+    return SW_OK;
+}
+
+#define DESS_VRF_ENTRY_MAX_ID    7
+
+#define DESS_VRF_ENTRY_TBL_ADDR   0x0484
+#define DESS_VRF_ENTRY_MASK_ADDR   0x0488
+
+static sw_error_t
+_dess_ip_vrf_base_addr_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+    a_uint32_t reg_addr;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (DESS_VRF_ENTRY_MAX_ID < vrf_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    reg_addr = DESS_VRF_ENTRY_TBL_ADDR + (vrf_id << 3);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, reg_addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&addr), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return rv;
+}
+
+static sw_error_t
+_dess_ip_vrf_base_addr_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+    a_uint32_t reg_addr;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (DESS_VRF_ENTRY_MAX_ID < vrf_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    reg_addr = DESS_VRF_ENTRY_TBL_ADDR + (vrf_id << 3);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, reg_addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (addr), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_vrf_base_mask_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+    a_uint32_t reg_addr;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (DESS_VRF_ENTRY_MAX_ID < vrf_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    reg_addr = DESS_VRF_ENTRY_MASK_ADDR + (vrf_id << 3);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, reg_addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&addr), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return rv;
+}
+
+static sw_error_t
+_dess_ip_vrf_base_mask_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+    a_uint32_t reg_addr;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (DESS_VRF_ENTRY_MAX_ID < vrf_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    reg_addr = DESS_VRF_ENTRY_MASK_ADDR + (vrf_id << 3);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, reg_addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (addr), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_default_route_set(a_uint32_t dev_id, a_uint32_t droute_id, fal_default_route_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+    a_uint32_t addr;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (entry->ip_version == FAL_ADDR_IPV4)
+    {
+    	SW_SET_REG_BY_FIELD(IP4_DEFAULT_ROUTE_ENTRY, VALID, entry->valid, data);
+    	SW_SET_REG_BY_FIELD(IP4_DEFAULT_ROUTE_ENTRY, VRF, entry->vrf_id, data);
+    	SW_SET_REG_BY_FIELD(IP4_DEFAULT_ROUTE_ENTRY, ARP_WCMP_TYPE, entry->droute_type, data);
+    	SW_SET_REG_BY_FIELD(IP4_DEFAULT_ROUTE_ENTRY, ARP_WCMP_INDEX, entry->index, data);
+
+    	addr = DESS_IP4_DEFAULT_ROUTE_TBL_ADDR + (droute_id << 2);
+    	HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else
+    {
+    	SW_SET_REG_BY_FIELD(IP6_DEFAULT_ROUTE_ENTRY, VALID, entry->valid, data);
+    	SW_SET_REG_BY_FIELD(IP6_DEFAULT_ROUTE_ENTRY, VRF, entry->vrf_id, data);
+    	SW_SET_REG_BY_FIELD(IP6_DEFAULT_ROUTE_ENTRY, ARP_WCMP_TYPE, entry->droute_type, data);
+    	SW_SET_REG_BY_FIELD(IP6_DEFAULT_ROUTE_ENTRY, ARP_WCMP_INDEX, entry->index, data);
+
+    	addr = DESS_IP6_DEFAULT_ROUTE_TBL_ADDR + (droute_id << 2);
+    	HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_dess_ip_default_route_get(a_uint32_t dev_id, a_uint32_t droute_id, fal_default_route_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+    a_uint32_t addr;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (entry->ip_version == FAL_ADDR_IPV4)
+    {
+    	addr = DESS_IP4_DEFAULT_ROUTE_TBL_ADDR + (droute_id << 2);
+    	HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+    	SW_GET_FIELD_BY_REG(IP4_DEFAULT_ROUTE_ENTRY, VALID, entry->valid, data);
+    	SW_GET_FIELD_BY_REG(IP4_DEFAULT_ROUTE_ENTRY, VRF, entry->vrf_id, data);
+    	SW_GET_FIELD_BY_REG(IP4_DEFAULT_ROUTE_ENTRY, ARP_WCMP_TYPE, entry->droute_type, data);
+    	SW_GET_FIELD_BY_REG(IP4_DEFAULT_ROUTE_ENTRY, ARP_WCMP_INDEX, entry->index, data);
+    }
+    else
+    {
+    	addr = DESS_IP6_DEFAULT_ROUTE_TBL_ADDR + (droute_id << 2);
+    	HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+    	SW_GET_FIELD_BY_REG(IP6_DEFAULT_ROUTE_ENTRY, VALID, entry->valid, data);
+    	SW_GET_FIELD_BY_REG(IP6_DEFAULT_ROUTE_ENTRY, VRF, entry->vrf_id, data);
+    	SW_GET_FIELD_BY_REG(IP6_DEFAULT_ROUTE_ENTRY, ARP_WCMP_TYPE, entry->droute_type, data);
+    	SW_GET_FIELD_BY_REG(IP6_DEFAULT_ROUTE_ENTRY, ARP_WCMP_INDEX, entry->index, data);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_host_route_set(a_uint32_t dev_id, a_uint32_t hroute_id, fal_host_route_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t j, addr, tbl[5] = { 0 };
+    a_uint32_t addr0_low, addr0_high, addr1_low, addr1_high,
+		     addr2_low, addr2_high, addr3_low, addr3_high;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (entry->ip_version == FAL_ADDR_IPV4)
+    {
+	addr0_low = entry->route_addr.ip4_addr & 0x7ffffff;
+	addr0_high = entry->route_addr.ip4_addr >> 27;
+	SW_SET_REG_BY_FIELD(IP4_HOST_ROUTE_ENTRY0, PREFIX_LENGTH, entry->prefix_length,
+				tbl[0]);
+	SW_SET_REG_BY_FIELD(IP4_HOST_ROUTE_ENTRY0, IP4_ADDRL, addr0_low, tbl[0]);
+	SW_SET_REG_BY_FIELD(IP4_HOST_ROUTE_ENTRY1, IP4_ADDRH, addr0_high, tbl[1]);
+	SW_SET_REG_BY_FIELD(IP4_HOST_ROUTE_ENTRY1, VALID, entry->valid,
+				tbl[1]);
+	SW_SET_REG_BY_FIELD(IP4_HOST_ROUTE_ENTRY1, VRF, entry->vrf_id,
+				tbl[1]);
+    	for (j = 0; j < 2; j++)
+    	{
+        	    addr = DESS_IP4_HOST_ROUTE_TBL0_ADDR + (hroute_id << 4) + (j << 2);
+        	    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+        	    SW_RTN_ON_ERROR(rv);
+    	}
+    }
+    else
+    {
+        addr0_low = entry->route_addr.ip6_addr.ul[3] & 0x1ffffff;
+        addr0_high = (entry->route_addr.ip6_addr.ul[3] >> 25) & 0x7f;
+        addr1_low = entry->route_addr.ip6_addr.ul[2] & 0x1ffffff;
+        addr1_high = (entry->route_addr.ip6_addr.ul[2] >> 25) & 0x7f;
+        addr2_low = entry->route_addr.ip6_addr.ul[1] & 0x1ffffff;
+        addr2_high = (entry->route_addr.ip6_addr.ul[1] >> 25) & 0x7f;
+        addr3_low = entry->route_addr.ip6_addr.ul[0] & 0x1ffffff;
+        addr3_high = (entry->route_addr.ip6_addr.ul[0] >> 25) & 0x7f;
+
+        SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY0, IP6_ADDR0L, addr0_low, tbl[0]);
+        SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY0, PREFIX_LENGTH, entry->prefix_length, tbl[0]);
+
+        SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY1, IP6_ADDR1L, addr1_low, tbl[1]);
+        SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY1, IP6_ADDR0H, addr0_high, tbl[1]);
+
+        SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY2, IP6_ADDR2L, addr2_low, tbl[2]);
+        SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY2, IP6_ADDR1H, addr1_high, tbl[2]);
+
+        SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY3, IP6_ADDR3L, addr3_low, tbl[3]);
+        SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY3, IP6_ADDR2H, addr2_high, tbl[3]);
+
+        SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY4, VALID, entry->valid, tbl[4]);
+        SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY4, VRF, entry->vrf_id, tbl[4]);
+        SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY4, IP6_ADDR3H, addr3_high, tbl[4]);
+
+    	for (j = 0; j < 5; j++)
+    	{
+        	    addr = DESS_IP6_HOST_ROUTE_TBL0_ADDR + (hroute_id << 5) + (j << 2);
+        	    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+        	    SW_RTN_ON_ERROR(rv);
+    	}    
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_host_route_get(a_uint32_t dev_id, a_uint32_t hroute_id, fal_host_route_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t j, addr, tbl[5] = { 0 };
+    a_uint32_t addr0_low, addr0_high, addr1_low, addr1_high,
+		     addr2_low, addr2_high, addr3_low, addr3_high;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (entry->ip_version == FAL_ADDR_IPV4)
+    {
+    	for (j = 0; j < 2; j++)
+    	{
+        	    addr = DESS_IP4_HOST_ROUTE_TBL0_ADDR + (hroute_id << 4) + (j << 2);
+        	    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+        	    SW_RTN_ON_ERROR(rv);
+    	}
+	SW_GET_FIELD_BY_REG(IP4_HOST_ROUTE_ENTRY0, PREFIX_LENGTH, entry->prefix_length,
+				tbl[0]);
+	SW_GET_FIELD_BY_REG(IP4_HOST_ROUTE_ENTRY0, IP4_ADDRL, addr0_low,
+				tbl[0]);
+	SW_GET_FIELD_BY_REG(IP4_HOST_ROUTE_ENTRY1, IP4_ADDRH, addr0_high,
+				tbl[1]);
+	SW_GET_FIELD_BY_REG(IP4_HOST_ROUTE_ENTRY1, VALID, entry->valid,
+				tbl[1]);
+	SW_GET_FIELD_BY_REG(IP4_HOST_ROUTE_ENTRY1, VRF, entry->vrf_id,
+				tbl[1]);
+	entry->route_addr.ip4_addr = addr0_low | (addr0_high << 27);
+    }
+    else
+    {
+    	for (j = 0; j < 5; j++)
+    	{
+        	    addr = DESS_IP6_HOST_ROUTE_TBL0_ADDR + (hroute_id << 5) + (j << 2);
+        	    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+        	    SW_RTN_ON_ERROR(rv);
+    	}
+
+        SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY0, IP6_ADDR0L, addr0_low, tbl[0]);
+        SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY0, PREFIX_LENGTH, entry->prefix_length, tbl[0]);
+        SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY1, IP6_ADDR1L, addr1_low, tbl[1]);
+        SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY1, IP6_ADDR0H, addr0_high, tbl[1]);
+        SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY2, IP6_ADDR2L, addr2_low, tbl[2]);
+        SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY2, IP6_ADDR1H, addr1_high, tbl[2]);
+        SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY3, IP6_ADDR3L, addr3_low, tbl[3]);
+        SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY3, IP6_ADDR2H, addr2_high, tbl[3]);
+        SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY4, VRF, entry->vrf_id, tbl[4]);
+        SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY4, IP6_ADDR3H, addr3_high, tbl[4]);
+        SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY4, VALID, entry->valid, tbl[4]);
+        entry->route_addr.ip6_addr.ul[3] = (addr0_high << 25) | addr0_low;
+        entry->route_addr.ip6_addr.ul[2] = (addr1_high << 25) | addr1_low;
+        entry->route_addr.ip6_addr.ul[1] = (addr2_high << 25) | addr2_low;
+        entry->route_addr.ip6_addr.ul[0] = (addr3_high << 25) | addr3_low;
+    }
+
+    return SW_OK;
+}
+
+#define RFS_ADD_OP  1
+#define RFS_DEL_OP  2
+static sw_error_t
+_dess_ip_rfs_ip4_update(
+		a_uint32_t dev_id,
+		fal_host_entry_t *entry,
+		fal_ip4_rfs_t * rfs,
+		char op)
+{
+	fal_host_entry_t tmp = *entry;
+
+	_dess_ip_host_del(dev_id, FAL_IP_ENTRY_IPADDR_EN, entry);
+	if(RFS_ADD_OP == op) {
+		tmp.lb_num = rfs->load_balance | 0x4;
+		tmp.status = 0x7;
+	}
+	else {
+		tmp.lb_num = 0;
+		tmp.status = 0x6;
+	}
+	return _dess_ip_host_add(dev_id, &tmp);
+}
+
+static sw_error_t
+_dess_ip_rfs_ip6_update(
+		a_uint32_t dev_id,
+		fal_host_entry_t *entry,
+		fal_ip6_rfs_t * rfs,
+		char op)
+{
+	fal_host_entry_t tmp = *entry;
+
+	_dess_ip_host_del(dev_id, FAL_IP_ENTRY_IPADDR_EN, entry);
+	if(RFS_ADD_OP == op) {
+		tmp.lb_num = rfs->load_balance | 0x4;
+		tmp.status = 0x7;
+	}
+	else {
+		tmp.lb_num = 0;
+		tmp.status = 0x6;
+	}
+	return _dess_ip_host_add(dev_id, &tmp);
+}
+
+static sw_error_t
+_dess_ip_rfs_ip4_set(a_uint32_t dev_id, fal_ip4_rfs_t * rfs)
+{
+	fal_host_entry_t entry;
+
+	memset(&entry, 0, sizeof(entry));
+	entry.flags = FAL_IP_IP4_ADDR;
+	entry.ip4_addr = rfs->ip4_addr;
+	if(SW_OK == _dess_ip_host_get(dev_id, 0x10, &entry)) {
+		return _dess_ip_rfs_ip4_update(dev_id, &entry, rfs, RFS_ADD_OP);
+	}
+	/*add a new one*/
+	entry.status = 0x7;
+	entry.flags = FAL_IP_IP4_ADDR;
+	entry.ip4_addr = rfs->ip4_addr;
+	memcpy(&entry.mac_addr, &rfs->mac_addr, 6);
+	entry.intf_id = rfs->vid;
+	entry.port_id = 0;
+	entry.lb_num = rfs->load_balance | 0x4;
+	entry.action = FAL_MAC_RDT_TO_CPU;
+	return _dess_ip_host_add(dev_id, &entry);
+}
+
+static sw_error_t
+_dess_ip_rfs_ip6_set(a_uint32_t dev_id, fal_ip6_rfs_t * rfs)
+{
+	fal_host_entry_t entry;
+
+	memset(&entry, 0, sizeof(entry));
+	entry.flags = FAL_IP_IP6_ADDR;
+	entry.ip6_addr = rfs->ip6_addr;
+	if(SW_OK == _dess_ip_host_get(dev_id, 0x10, &entry)) {
+		return _dess_ip_rfs_ip6_update(dev_id, &entry, rfs, RFS_ADD_OP);
+	}
+	/*add a new one*/
+	entry.status = 0x7;
+	entry.flags = FAL_IP_IP6_ADDR;
+	entry.ip6_addr = rfs->ip6_addr;
+	memcpy(&entry.mac_addr, &rfs->mac_addr, 6);
+	entry.intf_id = rfs->vid;
+	entry.port_id = 0;
+	entry.lb_num = rfs->load_balance | 0x4;
+	entry.action = FAL_MAC_RDT_TO_CPU;
+	return _dess_ip_host_add(dev_id, &entry);
+}
+
+static sw_error_t
+_dess_ip_rfs_ip4_del(a_uint32_t dev_id, fal_ip4_rfs_t * rfs)
+{
+	fal_host_entry_t entry;
+	sw_error_t ret;
+
+	memset(&entry, 0, sizeof(entry));
+	entry.flags = FAL_IP_IP4_ADDR;
+	entry.ip4_addr = rfs->ip4_addr;
+	if(SW_OK == (ret = _dess_ip_host_get(dev_id, 0x10, &entry))) {
+		return _dess_ip_rfs_ip4_update(dev_id, &entry, rfs, RFS_DEL_OP);
+	}
+	return ret;
+}
+
+static sw_error_t
+_dess_ip_rfs_ip6_del(a_uint32_t dev_id, fal_ip6_rfs_t * rfs)
+{
+	fal_host_entry_t entry;
+	sw_error_t ret;
+
+	memset(&entry, 0, sizeof(entry));
+	entry.flags = FAL_IP_IP6_ADDR;
+	entry.ip6_addr = rfs->ip6_addr;
+	if(SW_OK == (ret = _dess_ip_host_get(dev_id, 0x10, &entry))) {
+		return _dess_ip_rfs_ip6_update(dev_id, &entry, rfs, RFS_DEL_OP);
+	}
+	return ret;
+}
+
+static sw_error_t
+_dess_default_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_DEFAULT_FLOW_FORWARD == cmd)
+    {
+        data = 0;
+    }
+    else if (FAL_DEFAULT_FLOW_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_DEFAULT_FLOW_RDT_TO_CPU == cmd)
+    {
+        data = 2;
+    }
+    else if (FAL_DEFAULT_FLOW_ADMIT_ALL == cmd)
+    {
+        data = 3;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_FLOW_LAN_TO_LAN == type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, FlOW_CMD_CTL, vrf_id, LAN_2_LAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_FLOW_WAN_TO_LAN == type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, FlOW_CMD_CTL, vrf_id, WAN_2_LAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_FLOW_LAN_TO_WAN == type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, FlOW_CMD_CTL, vrf_id, LAN_2_WAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_FLOW_WAN_TO_WAN == type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, FlOW_CMD_CTL, vrf_id, WAN_2_WAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_dess_default_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_FLOW_LAN_TO_LAN == type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, FlOW_CMD_CTL, vrf_id, LAN_2_LAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_FLOW_WAN_TO_LAN == type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, FlOW_CMD_CTL, vrf_id, WAN_2_LAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_FLOW_LAN_TO_WAN == type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, FlOW_CMD_CTL, vrf_id, LAN_2_WAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_FLOW_WAN_TO_WAN == type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, FlOW_CMD_CTL, vrf_id, WAN_2_WAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        *cmd = FAL_DEFAULT_FLOW_FORWARD;
+    }
+    else if (1 == data)
+    {
+        *cmd = FAL_DEFAULT_FLOW_DROP;
+    }
+    else if (2 == data)
+    {
+        *cmd = FAL_DEFAULT_FLOW_RDT_TO_CPU;
+    }
+    else if (3 == data)
+    {
+        *cmd = FAL_DEFAULT_FLOW_ADMIT_ALL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_default_rt_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_DEFAULT_FLOW_FORWARD == cmd)
+    {
+        data = 0;
+    }
+    else if (FAL_DEFAULT_FLOW_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_DEFAULT_FLOW_RDT_TO_CPU == cmd)
+    {
+        data = 2;
+    }
+    else if (FAL_DEFAULT_FLOW_ADMIT_ALL == cmd)
+    {
+        data = 3;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_FLOW_LAN_TO_LAN == type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, LAN_2_LAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_FLOW_WAN_TO_LAN == type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, WAN_2_LAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_FLOW_LAN_TO_WAN == type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, LAN_2_WAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_FLOW_WAN_TO_WAN == type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, WAN_2_WAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_dess_default_rt_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_FLOW_LAN_TO_LAN == type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, LAN_2_LAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_FLOW_WAN_TO_LAN == type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, WAN_2_LAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_FLOW_LAN_TO_WAN == type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, LAN_2_WAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_FLOW_WAN_TO_WAN == type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, WAN_2_WAN_DEFAULT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        *cmd = FAL_DEFAULT_FLOW_FORWARD;
+    }
+    else if (1 == data)
+    {
+        *cmd = FAL_DEFAULT_FLOW_DROP;
+    }
+    else if (2 == data)
+    {
+        *cmd = FAL_DEFAULT_FLOW_RDT_TO_CPU;
+    }
+    else if (3 == data)
+    {
+        *cmd = FAL_DEFAULT_FLOW_ADMIT_ALL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_glb_lock_time_set(a_uint32_t dev_id, fal_glb_lock_time_t lock_time)
+{
+	sw_error_t rv;
+	a_uint32_t data = lock_time;
+
+	HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, GLB_LOCKTIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+	return rv;
+}
+
+sw_error_t
+dess_ip_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t i, addr, data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_FLUSH);
+    SW_RTN_ON_ERROR(rv);
+
+    dess_mac_snap[dev_id] = 0;
+    for (i = 0; i < DESS_INTF_MAC_ADDR_NUM; i++)
+    {
+        addr = DESS_INTF_MAC_TBL2_ADDR + (i << 4);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Add one host entry to one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry added related interface entry and ip6 base address
+       must be set at first.
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_host_add(dev_id, host_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one host entry from one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry deleted related interface entry and ip6 base address
+       must be set atfirst.
+       For del_mode please refer IP entry operation flags.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operation mode
+ * @param[in] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                 fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_host_del(dev_id, del_mode, host_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get one host entry from one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry deleted related interface entry and ip6 base address
+       must be set atfirst.
+       For get_mode please refer IP entry operation flags.
+ * @param[in] dev_id device id
+ * @param[in] get_mode get operation mode
+ * @param[out] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                 fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_host_get(dev_id, get_mode, host_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next one host entry from one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry deleted related interface entry and ip6 base address
+       must be set atfirst.
+       For next_mode please refer IP entry operation flags.
+       For get the first entry please set entry id as FAL_NEXT_ENTRY_FIRST_ID
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operation mode
+ * @param[out] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                  fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_host_next(dev_id, next_mode, host_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one host entry on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id host entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE means bind, A_FALSE means unbind
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                          a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_host_counter_bind(dev_id, entry_id, cnt_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one pppoe session entry to one host entry on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id host entry id
+ * @param[in] pppoe_id pppoe session entry id
+ * @param[in] enable A_TRUE means bind, A_FALSE means unbind
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                        a_uint32_t pppoe_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_host_pppoe_bind(dev_id, entry_id, pppoe_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets type to learn on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t flags)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_pt_arp_learn_set(dev_id, port_id, flags);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets type to learn on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t * flags)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_pt_arp_learn_get(dev_id, port_id, flags);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets type to learn on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode learning mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_arp_learn_set(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets type to learn on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode learning mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_arp_learn_get(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ip packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_source_guard_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ip packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_source_guard_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set unkonw source ip packets forwarding command on one particular device.
+ *   @details Comments:
+ *     This settin is no meaning when ip source guard not enable
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_unk_source_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unkonw source ip packets forwarding command on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_unk_source_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_arp_guard_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_arp_guard_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set unkonw source arp packets forwarding command on one particular device.
+ *   @details Comments:
+ *     This settin is no meaning when arp source guard not enable
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_arp_unk_source_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unkonw source arp packets forwarding command on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_arp_unk_source_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP unicast routing status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_route_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP unicast routing status on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_route_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one interface entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry interface entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_intf_entry_add(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one interface entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operation mode
+ * @param[in] entry interface entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                       fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_intf_entry_del(dev_id, del_mode, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next one interface entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operation mode
+ * @param[out] entry interface entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                        fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_intf_entry_next(dev_id, next_mode, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP host entry aging time on one particular device.
+ * @details   Comments:
+ *       This operation will set dynamic entry aging time on a particular device.
+ *       The unit of time is second. Because different device has differnet
+ *       hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param[in] time aging time
+ * @param[out] time actual aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_age_time_set(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP host entry aging time on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_age_time_get(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP WCMP table one particular device.
+ *   @details Comments:
+ *     Hardware only support 0 - 15 hash values and 4 different host tables.
+ * @param[in] dev_id device id
+ * @param[in] wcmp_id wcmp entry id
+ * @param[in] wcmp wcmp entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_wcmp_entry_set(dev_id, wcmp_id, wcmp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP WCMP table one particular device.
+ *   @details Comments:
+ *     Hardware only support 0 - 15 hash values and 4 different host tables.
+ * @param[in] dev_id device id
+ * @param[in] wcmp_id wcmp entry id
+ * @param[out] wcmp wcmp entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_wcmp_entry_get(dev_id, wcmp_id, wcmp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP WCMP hash key mode.
+ * @param[in] dev_id device id
+ * @param[in] hash_mode hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_wcmp_hash_mode_set(dev_id, hash_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP WCMP hash key mode.
+ * @param[in] dev_id device id
+ * @param[out] hash_mode hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_wcmp_hash_mode_get(dev_id, hash_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP VRF base IP address.
+ * @param[in] dev_id device id
+ * @param[in] vrf_id VRF route index, from 0~7
+ * @param[in] fal_ip4_addr_t IPv4 address for this VRF route
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_vrf_base_addr_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_vrf_base_addr_set(dev_id, vrf_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP VRF base IP address.
+ * @param[in] dev_id device id
+ * @param[in] vrf_id VRF route index, from 0~7
+ * @param[out] fal_ip4_addr_t IPv4 address for this VRF route
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_vrf_base_addr_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_vrf_base_addr_get(dev_id, vrf_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP VRF base IP address mask.
+ * @param[in] dev_id device id
+ * @param[in] vrf_id VRF route index, from 0~7
+ * @param[in] fal_ip4_addr_t IPv4 address mask for this VRF route
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_vrf_base_mask_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_vrf_base_mask_set(dev_id, vrf_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP VRF base IP address mask.
+ * @param[in] dev_id device id
+ * @param[in] vrf_id VRF route index, from 0~7
+ * @param[out] fal_ip4_addr_t IPv4 address mask for this VRF route
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_vrf_base_mask_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_vrf_base_mask_get(dev_id, vrf_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP default route entry with special default route id.
+ * @param[in] dev_id device id
+ * @param[in] droute_id default route index, from 0~7
+ * @param[in] fal_default_route_t default route entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_default_route_set(a_uint32_t dev_id, a_uint32_t droute_id, fal_default_route_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_default_route_set(dev_id, droute_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP default route entry with special default route id.
+ * @param[in] dev_id device id
+ * @param[in] droute_id default route index, from 0~7
+ * @param[in] fal_default_route_t default route entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_default_route_get(a_uint32_t dev_id, a_uint32_t droute_id, fal_default_route_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_default_route_get(dev_id, droute_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP host route entry with special default route id.
+ * @param[in] dev_id device id
+ * @param[in] hroute_id default route index, from 0~15
+ * @param[in] fal_host_route_t host route entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_host_route_set(a_uint32_t dev_id, a_uint32_t hroute_id, fal_host_route_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_host_route_set(dev_id, hroute_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP host route entry with special default route id.
+ * @param[in] dev_id device id
+ * @param[in] hroute_id default route index, from 0~15
+ * @param[in] fal_host_route_t host route entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_host_route_get(a_uint32_t dev_id, a_uint32_t hroute_id, fal_host_route_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_host_route_get(dev_id, hroute_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP host route load balance.
+ * @param[in] dev_id device id
+ * @param[in] fal_ip4_rfs_t host route entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_rfs_ip4_set(a_uint32_t dev_id, fal_ip4_rfs_t * rfs)
+{
+	sw_error_t rv;
+	fal_intf_mac_entry_t mac_entry;
+
+	HSL_API_LOCK;
+	memset(&mac_entry, 0, sizeof(mac_entry));
+	mac_entry.ip4_route = A_TRUE;
+	mac_entry.ip6_route = A_TRUE;
+	mac_entry.vid_low = rfs->vid;
+	mac_entry.vid_high = rfs->vid;
+	mac_entry.mac_addr = rfs->mac_addr;
+	rv = _dess_ip_intf_entry_add(dev_id, &mac_entry);
+	if(!rv)
+    		rv = _dess_ip_rfs_ip4_set(dev_id, rfs);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Set IP6 host route load balance.
+ * @param[in] dev_id device id
+ * @param[in] fal_ip6_rfs_t host route entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_rfs_ip6_set(a_uint32_t dev_id, fal_ip6_rfs_t * rfs)
+{
+	sw_error_t rv;
+	fal_intf_mac_entry_t mac_entry;
+
+	HSL_API_LOCK;
+	memset(&mac_entry, 0, sizeof(mac_entry));
+	mac_entry.ip4_route = A_TRUE;
+	mac_entry.ip6_route = A_TRUE;
+	mac_entry.vid_low = rfs->vid;
+	mac_entry.vid_high = rfs->vid;
+	mac_entry.mac_addr = rfs->mac_addr;
+	rv = _dess_ip_intf_entry_add(dev_id, &mac_entry);
+	if(!rv)
+		rv = _dess_ip_rfs_ip6_set(dev_id, rfs);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief del IP host route load balance.
+ * @param[in] dev_id device id
+ * @param[in] fal_ip4_rfs_t host route entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_rfs_ip4_del(a_uint32_t dev_id, fal_ip4_rfs_t * rfs)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_rfs_ip4_del(dev_id, rfs);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief del IP6 host route load balance.
+ * @param[in] dev_id device id
+ * @param[in] fal_ip6_rfs_t host route entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_rfs_ip6_del(a_uint32_t dev_id, fal_ip6_rfs_t * rfs)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ip_rfs_ip6_del(dev_id, rfs);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flow type traffic default forward command.
+ * @param[in] dev_id device id
+ * @param[in] vrf_id VRF route index, from 0~7
+ * @param[in] type traffic flow type pass through switch core
+ * @param[in] fal_default_flow_cmd_mode_t default flow forward command when flow table mismatch
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_default_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_default_flow_cmd_set(dev_id, vrf_id, type, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flow type traffic default forward command.
+ * @param[in] dev_id device id
+ * @param[in] vrf_id VRF route index, from 0~7
+ * @param[in] type traffic flow type pass through switch core
+ * @param[out] fal_default_flow_cmd_mode_t default flow forward command when flow table mismatch
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_default_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_default_flow_cmd_get(dev_id, vrf_id, type, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flow&route type traffic default forward command.
+ * @param[in] dev_id device id
+ * @param[in] vrf_id VRF route index, from 0~7
+ * @param[in] type traffic flow type pass through switch core
+ * @param[in] fal_default_flow_cmd_mode_t default flow&route forward command when route mac match but flow table mismatch
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_default_rt_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_default_rt_flow_cmd_set(dev_id, vrf_id, type, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flow&route type traffic default forward command.
+ * @param[in] dev_id device id
+ * @param[in] vrf_id VRF route index, from 0~7
+ * @param[in] type traffic flow type pass through switch core
+ * @param[in] fal_default_flow_cmd_mode_t default flow&route forward command when route mac match but flow table mismatch
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_default_rt_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_default_rt_flow_cmd_get(dev_id, vrf_id, type, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set blobal lock time.
+ * @param[in] dev_id device id
+ * @param[in] fal_glb_lock_time_t lock time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ip_glb_lock_time_set(a_uint32_t dev_id, fal_glb_lock_time_t lock_time)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _dess_ip_glb_lock_time_set(dev_id, lock_time);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+dess_ip_init(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = dess_ip_reset(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->ip_host_add = dess_ip_host_add;
+        p_api->ip_host_del = dess_ip_host_del;
+        p_api->ip_host_get = dess_ip_host_get;
+        p_api->ip_host_next = dess_ip_host_next;
+        p_api->ip_host_counter_bind = dess_ip_host_counter_bind;
+        p_api->ip_host_pppoe_bind = dess_ip_host_pppoe_bind;
+        p_api->ip_pt_arp_learn_set = dess_ip_pt_arp_learn_set;
+        p_api->ip_pt_arp_learn_get = dess_ip_pt_arp_learn_get;
+        p_api->ip_arp_learn_set = dess_ip_arp_learn_set;
+        p_api->ip_arp_learn_get = dess_ip_arp_learn_get;
+        p_api->ip_source_guard_set = dess_ip_source_guard_set;
+        p_api->ip_source_guard_get = dess_ip_source_guard_get;
+        p_api->ip_unk_source_cmd_set = dess_ip_unk_source_cmd_set;
+        p_api->ip_unk_source_cmd_get = dess_ip_unk_source_cmd_get;
+        p_api->ip_arp_guard_set = dess_ip_arp_guard_set;
+        p_api->ip_arp_guard_get = dess_ip_arp_guard_get;
+        p_api->arp_unk_source_cmd_set = dess_arp_unk_source_cmd_set;
+        p_api->arp_unk_source_cmd_get = dess_arp_unk_source_cmd_get;
+        p_api->ip_route_status_set = dess_ip_route_status_set;
+        p_api->ip_route_status_get = dess_ip_route_status_get;
+        p_api->ip_intf_entry_add = dess_ip_intf_entry_add;
+        p_api->ip_intf_entry_del = dess_ip_intf_entry_del;
+        p_api->ip_intf_entry_next = dess_ip_intf_entry_next;
+        p_api->ip_age_time_set = dess_ip_age_time_set;
+        p_api->ip_age_time_get = dess_ip_age_time_get;
+        p_api->ip_wcmp_hash_mode_set = dess_ip_wcmp_hash_mode_set;
+        p_api->ip_wcmp_hash_mode_get = dess_ip_wcmp_hash_mode_get;
+        p_api->ip_vrf_base_addr_set = dess_ip_vrf_base_addr_set;
+        p_api->ip_vrf_base_addr_get = dess_ip_vrf_base_addr_get;
+        p_api->ip_vrf_base_mask_set = dess_ip_vrf_base_mask_set;
+        p_api->ip_vrf_base_mask_get = dess_ip_vrf_base_mask_get;
+        p_api->ip_default_route_set = dess_ip_default_route_set;
+        p_api->ip_default_route_get = dess_ip_default_route_get;
+        p_api->ip_host_route_set = dess_ip_host_route_set;
+        p_api->ip_host_route_get = dess_ip_host_route_get;
+		p_api->ip_wcmp_entry_set = dess_ip_wcmp_entry_set;
+        p_api->ip_wcmp_entry_get = dess_ip_wcmp_entry_get;
+		p_api->ip_rfs_ip4_set = dess_ip_rfs_ip4_set;
+		p_api->ip_rfs_ip6_set = dess_ip_rfs_ip6_set;
+		p_api->ip_rfs_ip4_del = dess_ip_rfs_ip4_del;
+		p_api->ip_rfs_ip6_del = dess_ip_rfs_ip6_del;
+        p_api->ip_default_flow_cmd_set = dess_default_flow_cmd_set;
+        p_api->ip_default_flow_cmd_get = dess_default_flow_cmd_get;
+        p_api->ip_default_rt_flow_cmd_set = dess_default_rt_flow_cmd_set;
+        p_api->ip_default_rt_flow_cmd_get = dess_default_rt_flow_cmd_get;
+	p_api->ip_glb_lock_time_set = dess_ip_glb_lock_time_set;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/dess/dess_leaky.c b/qca-ssdk/src/hsl/dess/dess_leaky.c
new file mode 100755
index 0000000..6aef5d5
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_leaky.c
@@ -0,0 +1,526 @@
+/*
+ * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_leaky DESS_LEAKY
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_leaky.h"
+#include "dess_reg.h"
+
+static sw_error_t
+_dess_uc_leaky_mode_set(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+    {
+        data = 0;
+    }
+    else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_uc_leaky_mode_get(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+    }
+    else
+    {
+        *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_mc_leaky_mode_set(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+    {
+        data = 0;
+    }
+    else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_mc_leaky_mode_get(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+    }
+    else
+    {
+        *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+* @brief Set unicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+dess_uc_leaky_mode_set(a_uint32_t dev_id,
+                       fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_uc_leaky_mode_set(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_uc_leaky_mode_get(a_uint32_t dev_id,
+                       fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_uc_leaky_mode_get(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Set multicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+dess_mc_leaky_mode_set(a_uint32_t dev_id,
+                       fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_mc_leaky_mode_set(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_mc_leaky_mode_get(a_uint32_t dev_id,
+                       fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_mc_leaky_mode_get(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_arp_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_arp_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_uc_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_uc_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_mc_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_mc_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+dess_leaky_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->uc_leaky_mode_set = dess_uc_leaky_mode_set;
+        p_api->uc_leaky_mode_get = dess_uc_leaky_mode_get;
+        p_api->mc_leaky_mode_set = dess_mc_leaky_mode_set;
+        p_api->mc_leaky_mode_get = dess_mc_leaky_mode_get;
+        p_api->port_arp_leaky_set = dess_port_arp_leaky_set;
+        p_api->port_arp_leaky_get = dess_port_arp_leaky_get;
+        p_api->port_uc_leaky_set = dess_port_uc_leaky_set;
+        p_api->port_uc_leaky_get = dess_port_uc_leaky_get;
+        p_api->port_mc_leaky_set = dess_port_mc_leaky_set;
+        p_api->port_mc_leaky_get = dess_port_mc_leaky_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/dess/dess_led.c b/qca-ssdk/src/hsl/dess/dess_led.c
new file mode 100755
index 0000000..6f2b2ac
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_led.c
@@ -0,0 +1,670 @@
+/*
+ * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_led DESS_LED
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "dess_led.h"
+#include "dess_reg.h"
+
+#define MAX_LED_PATTERN_ID   2
+#define LED_PATTERN_ADDR     0x50
+
+static sw_error_t
+_dess_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                           led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    a_uint32_t data = 0, reg = 0, mode;
+    a_uint32_t addr;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (id > MAX_LED_PATTERN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    addr = LED_PATTERN_ADDR + (id << 2);
+
+    if (LED_ALWAYS_OFF == pattern->mode)
+    {
+        mode = 0;
+    }
+    else if (LED_ALWAYS_BLINK == pattern->mode)
+    {
+        mode = 1;
+    }
+    else if (LED_ALWAYS_ON == pattern->mode)
+    {
+        mode = 2;
+    }
+    else if (LED_PATTERN_MAP_EN == pattern->mode)
+    {
+        mode = 3;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data);
+
+    if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << POWER_ON_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_1000M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_100M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_10M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << COLLISION_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINKUP_OVERRIDE_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data);
+    }
+
+    if (LED_BLINK_2HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data);
+    }
+    else if (LED_BLINK_4HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data);
+    }
+    else if (LED_BLINK_8HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data);
+    }
+    else if (LED_BLINK_TXRX == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_WAN_PORT_GROUP == group)
+    {
+        reg &= 0xffff;
+        reg |= (data << 16);
+    }
+    else
+    {
+        reg &= 0xffff0000;
+        reg |= data;
+    }
+
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_WAN_PORT_GROUP == group)
+    {
+        return SW_OK;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_LAN_PORT_GROUP == group)
+    {
+        if (0 == id)
+        {
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data);
+        }
+        else if (1 == id)
+        {
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P3L2_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P2L2_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P1L2_MODE, mode, data);
+        }
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                           led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    a_uint32_t data = 0, reg = 0, tmp;
+    a_uint32_t addr;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (id > MAX_LED_PATTERN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t));
+
+    addr = LED_PATTERN_ADDR + (id << 2);
+
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_WAN_PORT_GROUP == group)
+    {
+        data = (reg >> 16) & 0xffff;
+    }
+    else
+    {
+        data = reg & 0xffff;
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data);
+    if (0 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_OFF;
+    }
+    else if (1 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_BLINK;
+    }
+    else if (2 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_ON;
+    }
+    else
+    {
+        pattern->mode = LED_PATTERN_MAP_EN;
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << POWER_ON_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_1000M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_100M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_10M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << COLLISION_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << RX_TRAFFIC_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << TX_TRAFFIC_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINKUP_OVERRIDE_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data);
+    if (0 == tmp)
+    {
+        pattern->freq = LED_BLINK_2HZ;
+    }
+    else if (1 == tmp)
+    {
+        pattern->freq = LED_BLINK_4HZ;
+    }
+    else if (2 == tmp)
+    {
+        pattern->freq = LED_BLINK_8HZ;
+    }
+    else
+    {
+        pattern->freq = LED_BLINK_TXRX;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_led_source_pattern_set(a_uint32_t dev_id, a_uint32_t source_id, led_ctrl_pattern_t * pattern)
+{
+	a_uint32_t data = 0, data1 = 0, reg = 0, mode;
+	sw_error_t rv;
+	a_uint32_t addr;
+
+	HSL_DEV_ID_CHECK(dev_id);
+
+	if (LED_ALWAYS_OFF == pattern->mode)
+	{
+		mode = 0;
+	}
+	else if (LED_ALWAYS_BLINK == pattern->mode)
+	{
+		mode = 1;
+	}
+	else if (LED_ALWAYS_ON == pattern->mode)
+	{
+		mode = 2;
+	}
+	else if (LED_PATTERN_MAP_EN == pattern->mode)
+	{
+		mode = 3;
+	}
+	else
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data);
+
+	if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN))
+	{
+	    SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data);
+	}
+
+	if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN))
+	{
+	    SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data);
+	}
+
+	if (pattern->map & (1 << POWER_ON_LIGHT_EN))
+	{
+	    SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data);
+	}
+
+	if (pattern->map & (1 << LINK_1000M_LIGHT_EN))
+	{
+	    SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data);
+	}
+
+	if (pattern->map & (1 << LINK_100M_LIGHT_EN))
+	{
+	    SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data);
+	}
+
+	if (pattern->map & (1 << LINK_10M_LIGHT_EN))
+	{
+	    SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data);
+	}
+
+	if (pattern->map & (1 << COLLISION_BLINK_EN))
+	{
+	    SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data);
+	}
+
+	if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN))
+	{
+	    SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data);
+	}
+
+	if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN))
+	{
+	    SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data);
+	}
+
+	if (pattern->map & (1 << LINKUP_OVERRIDE_EN))
+	{
+	    SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data);
+	}
+	else
+	{
+	    SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data);
+	}
+
+	if (LED_BLINK_2HZ == pattern->freq)
+	{
+	    SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data);
+	}
+	else if (LED_BLINK_4HZ == pattern->freq)
+	{
+	    SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data);
+	}
+	else if (LED_BLINK_8HZ == pattern->freq)
+	{
+	    SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data);
+	}
+	else if (LED_BLINK_TXRX == pattern->freq)
+	{
+	    SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data);
+	}
+	else
+	{
+	    return SW_BAD_PARAM;
+	}
+
+	if (source_id == 1)
+	{
+
+		addr = LED_PATTERN_ADDR;
+		HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+				(a_uint8_t *) (&reg),
+				sizeof (a_uint32_t));
+		reg &= 0xffff0000;
+		reg |= data;
+		HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+				(a_uint8_t *) (&reg),
+				sizeof (a_uint32_t));
+		SW_RTN_ON_ERROR(rv);
+
+	}
+	else if (source_id == 2)
+	{
+		addr = LED_PATTERN_ADDR + (1 << 2);
+		HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+				(a_uint8_t *) (&reg),
+				 sizeof (a_uint32_t));
+		reg &= 0xffff0000;
+		reg |= data;
+		HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+				(a_uint8_t *) (&reg),
+				sizeof (a_uint32_t));
+		SW_RTN_ON_ERROR(rv);
+
+	}
+	else if (source_id == 3)
+	{
+		addr = LED_PATTERN_ADDR + (2 << 2);
+		HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+				(a_uint8_t *) (&reg),
+				sizeof (a_uint32_t));
+		reg &= 0xffff0000;
+		reg |= data;
+		HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+				 (a_uint8_t *) (&reg),
+				sizeof (a_uint32_t));
+		SW_RTN_ON_ERROR(rv);
+
+	}
+	if (source_id == 13)
+	{
+		addr = LED_PATTERN_ADDR;
+		HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+				(a_uint8_t *) (&reg),
+				 sizeof (a_uint32_t));
+		reg &= 0xffff;
+		reg |= (data << 16);
+		HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+				 (a_uint8_t *) (&reg),
+				 sizeof (a_uint32_t));
+		SW_RTN_ON_ERROR(rv);
+
+	}
+	else if (source_id == 14)
+	{
+		addr = LED_PATTERN_ADDR + (1 << 2);
+		HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+				(a_uint8_t *) (&reg),
+				sizeof (a_uint32_t));
+		reg &= 0xffff;
+		reg |= (data << 16);
+		HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+				(a_uint8_t *) (&reg),
+				sizeof (a_uint32_t));
+		SW_RTN_ON_ERROR(rv);
+
+	}
+	else if (source_id == 15)
+	{
+		addr = LED_PATTERN_ADDR + (2 << 2);
+		HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+				(a_uint8_t *) (&reg),
+				sizeof (a_uint32_t));
+		reg &= 0xffff;
+		reg |= (data << 16);
+		HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+				(a_uint8_t *) (&reg),
+				sizeof (a_uint32_t));
+		SW_RTN_ON_ERROR(rv);
+
+	}
+	else if ((source_id) >= 4 && (source_id <= 12))
+	{
+		HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0,
+                      (a_uint8_t *) (&data1), sizeof (a_uint32_t));
+		SW_RTN_ON_ERROR(rv);
+
+		if (source_id == 4)
+		{
+			SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data1);
+		}
+		if (source_id == 5)
+		{
+			SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data1);
+		}
+		if (source_id == 6)
+		{
+			SW_SET_REG_BY_FIELD(LED_PATTERN, P1L2_MODE, mode, data1);
+		}
+		if (source_id == 7)
+		{
+			SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data1);
+		}
+		if (source_id == 8)
+		{
+			SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data1);
+		}
+		if (source_id == 9)
+		{
+			SW_SET_REG_BY_FIELD(LED_PATTERN, P2L2_MODE, mode, data1);
+		}
+		if (source_id == 10)
+		{
+			SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data1);
+		}
+		if (source_id == 11)
+		{
+			SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data1);
+		}
+		if (source_id == 12)
+		{
+			SW_SET_REG_BY_FIELD(LED_PATTERN, P3L2_MODE, mode, data1);
+		}
+
+		HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0,
+                      (a_uint8_t *) (&data1), sizeof (a_uint32_t));
+		SW_RTN_ON_ERROR(rv);
+
+	}
+
+	return SW_OK;
+
+}
+
+/**
+* @brief Set led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group  pattern group, lan or wan
+* @param[in] id pattern id
+* @param[in] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+dess_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                          led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_led_ctrl_pattern_set(dev_id, group, id, pattern);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Get led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group  pattern group, lan or wan
+* @param[in] id pattern id
+* @param[out] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+dess_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                          led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_led_ctrl_pattern_get(dev_id, group, id, pattern);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Set led source pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] source id
+* @param[in] id pattern id
+* @param[in] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+dess_led_source_pattern_set(a_uint32_t dev_id, a_uint32_t source_id, led_ctrl_pattern_t * pattern)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _dess_led_source_pattern_set(dev_id, source_id, pattern);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+dess_led_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->led_ctrl_pattern_set = dess_led_ctrl_pattern_set;
+        p_api->led_ctrl_pattern_get = dess_led_ctrl_pattern_get;
+	p_api->led_ctrl_source_set = dess_led_source_pattern_set;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/dess/dess_mib.c b/qca-ssdk/src/hsl/dess/dess_mib.c
new file mode 100755
index 0000000..4cc6ed7
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_mib.c
@@ -0,0 +1,861 @@
+/*
+ * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_mib DESS_MIB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_mib.h"
+#include "dess_reg.h"
+
+
+#define MIB_FLUSH_ALL_PORTS          0x1
+#define MIB_FLUSH_ONE_PORT           0x2
+#define MIB_AUTOCAST_ALL_PORTS   0x3
+
+static sw_error_t
+_dess_mib_op_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    a_uint32_t mib_busy = 1, i = 0x1000, val;
+    sw_error_t rv;
+
+    while (mib_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY,
+                          (a_uint8_t *) (&mib_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_BUSY;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_FUNC, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_FUN, op, val);
+    SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_BUSY, 1, val);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, MIB_FUNC, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    mib_busy = 1;
+    i = 0x1000;
+    while (mib_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY,
+                          (a_uint8_t *) (&mib_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_FAIL;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                   fal_mib_info_t * mib_info)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFcsErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxAllignErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxRunt = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFragment = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxTooLong = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxOverFlow = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Filtered = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxUnderRun = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxOverSize = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxCollision = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxAbortCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMultiCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxSingalCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxExcDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxLateCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXUNICAST, port_id,
+                      (a_uint8_t *) (&val), sizeof
+                      (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxUniCast = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNICAST, port_id,
+                      (a_uint8_t *) (&val), sizeof
+                      (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxUniCast = val;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                   fal_mib_info_t * mib_info)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFcsErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxAllignErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxRunt = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFragment = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxTooLong = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxOverFlow = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Filtered = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXUNICAST, port_id,
+                      (a_uint8_t *) (&val), sizeof
+                      (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxUniCast = val;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                   fal_mib_info_t * mib_info)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxUnderRun = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxOverSize = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxCollision = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxAbortCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMultiCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxSingalCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxExcDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxLateCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNICAST, port_id,
+                      (a_uint8_t *) (&val), sizeof
+                      (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxUniCast = val;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, MIB_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, MIB_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_CPU_KEEP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return rv;
+}
+
+static sw_error_t
+_dess_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_CPU_KEEP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id)
+{
+    a_uint32_t val;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    if (port_id>7)
+        return SW_BAD_PARAM;
+
+    val =  port_id;
+    HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_FLUSH_PORT,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    rv = _dess_mib_op_commit( dev_id,  MIB_FLUSH_ONE_PORT);
+
+    return rv;
+}
+
+/**
+ * @brief Get mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                  fal_mib_info_t * mib_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_get_mib_info(dev_id, port_id, mib_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get RX mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                  fal_mib_info_t * mib_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_get_rx_mib_info(dev_id, port_id, mib_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get TX mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                  fal_mib_info_t * mib_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_get_tx_mib_info(dev_id, port_id, mib_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_mib_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_mib_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+dess_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_mib_port_flush_counters(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set mib cpu keep bit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_mib_cpukeep_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mib keep bit on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_mib_cpukeep_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+dess_mib_init(a_uint32_t dev_id)
+{
+
+#ifndef HSL_STANDALONG
+	hsl_api_t *p_api;
+#endif
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->get_mib_info   = dess_get_mib_info;
+    p_api->get_rx_mib_info   = dess_get_rx_mib_info;
+    p_api->get_tx_mib_info   = dess_get_tx_mib_info;
+    p_api->mib_status_set = dess_mib_status_set;
+    p_api->mib_status_get = dess_mib_status_get;
+    p_api->mib_port_flush_counters = dess_mib_port_flush_counters;
+    p_api->mib_cpukeep_set = dess_mib_cpukeep_set;
+    p_api->mib_cpukeep_get = dess_mib_cpukeep_get;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/dess/dess_mirror.c b/qca-ssdk/src/hsl/dess/dess_mirror.c
new file mode 100755
index 0000000..9edb85f
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_mirror.c
@@ -0,0 +1,316 @@
+/*
+ * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_mirror DESS_MIRROR
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_mirror.h"
+#include "dess_reg.h"
+
+static sw_error_t
+_dess_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv;
+	a_uint32_t val;
+
+	HSL_DEV_ID_CHECK(dev_id);
+
+	if (port_id != MIRROR_ANALYZER_NONE) {
+		if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) {
+			return SW_BAD_PARAM;
+		}
+	}
+	val = port_id;
+	HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+	return rv;
+}
+
+static sw_error_t
+_dess_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *port_id = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+ *   @details  Comments:
+ *   The analysis port works for both ingress and egress mirror.
+ * @brief Set mirror analyzer port on particular a device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_mirr_analysis_port_set(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mirror analysis port on particular a device.
+ * @param[in] dev_id device id
+ * @param[out] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_mirr_analysis_port_get(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_mirr_port_in_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_mirr_port_in_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_mirr_port_eg_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_mirr_port_eg_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+dess_mirr_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->mirr_analysis_port_set = dess_mirr_analysis_port_set;
+        p_api->mirr_analysis_port_get = dess_mirr_analysis_port_get;
+        p_api->mirr_port_in_set = dess_mirr_port_in_set;
+        p_api->mirr_port_in_get = dess_mirr_port_in_get;
+        p_api->mirr_port_eg_set = dess_mirr_port_eg_set;
+        p_api->mirr_port_eg_get = dess_mirr_port_eg_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/dess/dess_misc.c b/qca-ssdk/src/hsl/dess/dess_misc.c
new file mode 100755
index 0000000..9db084d
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_misc.c
@@ -0,0 +1,2450 @@
+/*
+ * Copyright (c) 2014, 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_misc DESS_MISC
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_misc.h"
+#include "dess_reg.h"
+#include "hsl_phy.h"
+
+#define DESS_MAX_FRMAE_SIZE      9216
+
+#define ARP_REQ_EN_OFFSET    6
+#define ARP_ACK_EN_OFFSET    5
+#define DHCP_EN_OFFSET       4
+#define EAPOL_EN_OFFSET      3
+
+#define DESS_SWITCH_INT_PHY_INT   0x8000
+
+
+static sw_error_t
+_dess_port_misc_property_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable, a_uint32_t item)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (3 >= port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        reg &= ~(0x1UL << ((port_id << 3) + item));
+        reg |= (val << ((port_id << 3) + item));
+
+        HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        reg &= ~(0x1UL << (((port_id - 4) << 3) + item));
+        reg |= (val << (((port_id - 4) << 3) + item));
+
+        HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    return rv;
+}
+
+static sw_error_t
+_dess_port_misc_property_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable, a_uint32_t item)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (3 >= port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        val = (reg >> ((port_id << 3) + item)) & 0x1UL;
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL;
+    }
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (DESS_MAX_FRMAE_SIZE < size)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = size;
+    HSL_REG_FIELD_SET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *size = data;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t) 0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t) 0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t) 0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PKT_CTRL, 0, CPU_VID_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PKT_CTRL, 0, CPU_VID_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PKT_CTRL, 0, RTD_PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PKT_CTRL, 0, RTD_PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_dess_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_FRWRD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_FRWRD == cmd)
+    {
+        val = 2;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else if (0 == val)
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_FRWRD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+#define DESS_MAX_PPPOE_SESSION  16
+#define DESS_MAX_SESSION_ID     0xffff
+
+static sw_error_t
+_dess_pppoe_session_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, i, valid, id, entry_idx = DESS_MAX_PPPOE_SESSION;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (session_tbl->session_id > DESS_MAX_SESSION_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((A_FALSE == session_tbl->multi_session)
+            && (A_TRUE == session_tbl->uni_session))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((A_FALSE == session_tbl->multi_session)
+            && (A_FALSE == session_tbl->uni_session))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if(session_tbl->vrf_id > FAL_MAX_VRF_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = 0; i < DESS_MAX_PPPOE_SESSION; i++)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+        if (!valid)
+        {
+            entry_idx = i;
+        }
+        else if (id == session_tbl->session_id)
+        {
+            return SW_ALREADY_EXIST;
+        }
+    }
+
+    if (DESS_MAX_PPPOE_SESSION == entry_idx)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    if (A_TRUE == session_tbl->uni_session)
+    {
+        SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 2, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 1, reg);
+    }
+
+    SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, session_tbl->session_id,
+                        reg);
+    SW_SET_REG_BY_FIELD(PPPOE_SESSION, VRF_ID, session_tbl->vrf_id,
+                        reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, entry_idx,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    session_tbl->entry_id = entry_idx;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_pppoe_session_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, i, valid, id;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (session_tbl->session_id > DESS_MAX_SESSION_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = 0; i < DESS_MAX_PPPOE_SESSION; i++)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+        if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id))
+        {
+            SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 0, reg);
+            SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, 0, reg);
+            SW_SET_REG_BY_FIELD(PPPOE_SESSION, VRF_ID, 0, reg);
+            HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, i,
+                              (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+            return rv;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_dess_pppoe_session_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, i, valid, id, vrf_id;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (session_tbl->session_id > DESS_MAX_SESSION_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = 0; i < DESS_MAX_PPPOE_SESSION; i++)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, VRF_ID, vrf_id, reg);
+
+        if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id))
+        {
+            if (1 == valid)
+            {
+                session_tbl->multi_session = A_TRUE;
+                session_tbl->uni_session = A_FALSE;
+            }
+            else
+            {
+                session_tbl->multi_session = A_TRUE;
+                session_tbl->uni_session = A_TRUE;
+            }
+
+            session_tbl->entry_id = i;
+            session_tbl->vrf_id = vrf_id;
+            return SW_OK;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_dess_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+                           a_uint32_t id)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    if (DESS_MAX_PPPOE_SESSION <= index)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (DESS_MAX_SESSION_ID < id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    reg = 0;
+    SW_SET_REG_BY_FIELD(PPPOE_EDIT, EDIT_ID, id, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_dess_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+                           a_uint32_t * id)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, tmp;
+
+    if (DESS_MAX_PPPOE_SESSION <= index)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    tmp = 0;
+    SW_GET_FIELD_BY_REG(PPPOE_EDIT, EDIT_ID, tmp, reg);
+    *id = tmp;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (intr_mask & FAL_SWITCH_INTR_LINK_STATUS)
+    {
+        reg |= DESS_SWITCH_INT_PHY_INT;
+    }
+    else
+    {
+        reg &= (~DESS_SWITCH_INT_PHY_INT);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    *intr_mask = 0;
+    HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (reg & DESS_SWITCH_INT_PHY_INT)
+    {
+        *intr_mask |= FAL_SWITCH_INTR_LINK_STATUS;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    *intr_status = 0;
+    HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (reg & DESS_SWITCH_INT_PHY_INT)
+    {
+        *intr_status |= FAL_SWITCH_INTR_LINK_STATUS;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    reg = 0;
+    if (intr_status & FAL_SWITCH_INTR_LINK_STATUS)
+    {
+        reg |= DESS_SWITCH_INT_PHY_INT;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_link_intr_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+
+    if (NULL == phy_drv->phy_intr_mask_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_intr_mask_set(dev_id, phy_id, intr_mask_flag);
+    return rv;
+}
+
+static sw_error_t
+_dess_port_link_intr_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+
+    if (NULL == phy_drv->phy_intr_mask_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+     rv = phy_drv->phy_intr_mask_get(dev_id, phy_id, intr_mask_flag);
+
+    return rv;
+}
+
+static sw_error_t
+_dess_port_link_intr_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+
+    if (NULL == phy_drv->phy_intr_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_intr_status_get(dev_id, phy_id, intr_mask_flag);
+    return rv;
+}
+
+static sw_error_t
+_dess_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_MASK1, 0, LINK_CHG_INT_M,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_FALSE == enable)
+    {
+        data &= (~((a_uint32_t) 0x1 << port_id));
+    }
+    else if (A_TRUE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, GBL_INT_MASK1, 0, LINK_CHG_INT_M,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+
+static sw_error_t
+_dess_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_MASK1, 0, LINK_CHG_INT_M,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_dess_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_STATUS1, 0, LINK_CHG_INT_S,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    *port_bitmap = reg;
+
+    return rv;
+
+}
+
+static sw_error_t
+_dess_intr_status_mac_linkchg_clear(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_STATUS1, 0, LINK_CHG_INT_S,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    HSL_REG_FIELD_SET(rv, dev_id, GBL_INT_STATUS1, 0, LINK_CHG_INT_S,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+static sw_error_t
+_dess_global_macaddr_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+	sw_error_t rv;
+    a_uint32_t reg = 0;
+
+
+	HSL_DEV_ID_CHECK(dev_id);
+
+	reg = (addr->uc[4] << 8) | addr->uc[5];
+	HSL_REG_ENTRY_SET(rv, dev_id, GLOBAL_MAC_ADDR0, 0, (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+	reg = (addr->uc[0] << 24) | (addr->uc[1] << 16) | (addr->uc[2] << 8) | addr->uc[3];
+	HSL_REG_ENTRY_SET(rv, dev_id, GLOBAL_MAC_ADDR1, 0, (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+	return rv;
+}
+
+static sw_error_t
+_dess_global_macaddr_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+	sw_error_t rv;
+    a_uint32_t reg = 0;
+
+
+	HSL_DEV_ID_CHECK(dev_id);
+	HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_MAC_ADDR0, 0, (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+	addr->uc[4] = (reg >> 8) & 0xff;
+	addr->uc[5] = reg & 0xff;
+	HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_MAC_ADDR1, 0, (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+	addr->uc[0] = (reg >> 24) & 0xff;
+	addr->uc[1] = (reg >> 16) & 0xff;
+	addr->uc[2] = (reg >> 8) & 0xff;
+	addr->uc[3] = reg;
+
+	return rv;
+}
+
+static sw_error_t
+_dess_lldp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, LLDP_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_lldp_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, LLDP_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_frame_crc_reserve_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, MAX_SIZE, 0, CRC_RESERVE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_frame_crc_reserve_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MAX_SIZE, 0, CRC_RESERVE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+/**
+ * @brief Set max frame size which device can received on a particular device.
+ * @details    Comments:
+ * The granularity of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[in] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_frame_max_size_set(dev_id, size);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max frame size which device can received on a particular device.
+ * @details   Comments:
+ *    The unit of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[out] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_frame_max_size_get(dev_id, size);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown unicast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown unicast packets filter on one port then unknown
+ *   unicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_unk_uc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flooding status of unknown unicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_unk_uc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown multicast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown multicast packets filter on one port then unknown
+ *   multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_unk_mc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/** @brief Get flooding status of unknown multicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_unk_mc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of broadcast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown multicast packets filter on one port then unknown
+ *   multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_bc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/** @brief Get flooding status of broadcast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_bc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cpu_port_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cpu_port_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set pppoe packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling pppoe packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_pppoe_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get pppoe packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_pppoe_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set pppoe packets hardware acknowledgement status on particular device.
+ * @details     comments:
+ *   Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_pppoe_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get pppoe packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_pppoe_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dhcp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_misc_property_set(dev_id, port_id, enable, DHCP_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dhcp packets hardware acknowledgement status on particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_misc_property_get(dev_id, port_id, enable, DHCP_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling arp packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_arp_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_arp_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set eapol packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling eapol packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_eapol_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get eapol packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_eapol_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a pppoe session entry to a particular device.
+ *        The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_pppoe_session_table_add(a_uint32_t dev_id,
+                             fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_pppoe_session_add(dev_id, session_tbl);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a pppoe session entry from a particular device.
+ *        The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_pppoe_session_table_del(a_uint32_t dev_id,
+                             fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_pppoe_session_del(dev_id, session_tbl);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a pppoe session entry from a particular device.
+ *        The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[out] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_pppoe_session_table_get(a_uint32_t dev_id,
+                             fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_pppoe_session_get(dev_id, session_tbl);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set a pppoe session id entry to a particular device.
+ *        The entry only for pppoe/ppp header add.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+                          a_uint32_t id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_pppoe_session_id_set(dev_id, index, id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a pppoe session id entry from a particular device.
+ *        The entry only for pppoe/ppp header add.
+ * @param[in] dev_id device id
+ * @param[out] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+                          a_uint32_t * id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_pppoe_session_id_get(dev_id, index, id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_misc_property_set(dev_id, port_id, enable, EAPOL_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_misc_property_get(dev_id, port_id, enable, EAPOL_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ripv1_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ripv1_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp req packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_misc_property_set(dev_id, port_id, enable,
+                                      ARP_REQ_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp req packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_misc_property_get(dev_id, port_id, enable,
+                                      ARP_REQ_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp ack packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_misc_property_set(dev_id, port_id, enable,
+                                      ARP_ACK_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp ack packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_misc_property_get(dev_id, port_id, enable,
+                                      ARP_ACK_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set switch interrupt mask on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_mask mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_intr_mask_set(dev_id, intr_mask);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get switch interrupt mask on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_mask mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_intr_mask_get(dev_id, intr_mask);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get switch interrupt status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_status status
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_intr_status_get(dev_id, intr_status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Clear switch interrupt status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_status status
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_intr_status_clear(dev_id, intr_status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set link interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _dess_port_link_intr_mask_set(dev_id, port_id, intr_mask_flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get link interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_link_intr_mask_get(dev_id, port_id, intr_mask_flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get link interrupt status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_link_intr_status_get(dev_id, port_id, intr_mask_flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set mac link change interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable ports intr mask enabled
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    FAL_API_LOCK;
+    rv = _dess_intr_mask_mac_linkchg_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mac link change interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port interrupt mask or not
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _dess_intr_mask_mac_linkchg_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get link change interrupt status for all ports.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] ports bitmap which generates interrupt
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _dess_intr_status_mac_linkchg_get(dev_id, port_bitmap);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set cpu vid enable status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cpu_vid_en_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get cpu vid enable status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_cpu_vid_en_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set RM_RTD_PPPOE_EN status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_rtd_pppoe_en_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get RM_RTD_PPPOE_EN status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_rtd_pppoe_en_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Clear link change interrupt status for all ports.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_intr_status_mac_linkchg_clear(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _dess_intr_status_mac_linkchg_clear(dev_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set global macaddr on particular device.
+ * @param[in] dev_id device id
+ * @param[in] addr   addr
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_global_macaddr_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_global_macaddr_set(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get global macaddr on particular device.
+ * @param[in]  dev_id device id
+ * @param[out] addr   addr
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_global_macaddr_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_global_macaddr_get(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set lldp packets hardware acknowledgement status on particular device.
+ * @details     comments:
+ *   Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_lldp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_lldp_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get lldp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_lldp_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_lldp_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set frame crc reserve enable on particular device.
+ * @details     comments:
+ *   Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_frame_crc_reserve_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_frame_crc_reserve_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get frame crc reserve enable on particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_frame_crc_reserve_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_frame_crc_reserve_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+sw_error_t
+dess_misc_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->frame_max_size_set = dess_frame_max_size_set;
+        p_api->frame_max_size_get = dess_frame_max_size_get;
+        p_api->port_unk_uc_filter_set = dess_port_unk_uc_filter_set;
+        p_api->port_unk_uc_filter_get = dess_port_unk_uc_filter_get;
+        p_api->port_unk_mc_filter_set = dess_port_unk_mc_filter_set;
+        p_api->port_unk_mc_filter_get = dess_port_unk_mc_filter_get;
+        p_api->port_bc_filter_set = dess_port_bc_filter_set;
+        p_api->port_bc_filter_get = dess_port_bc_filter_get;
+        p_api->cpu_port_status_set = dess_cpu_port_status_set;
+        p_api->cpu_port_status_get = dess_cpu_port_status_get;
+        p_api->pppoe_cmd_set = dess_pppoe_cmd_set;
+        p_api->pppoe_cmd_get = dess_pppoe_cmd_get;
+        p_api->pppoe_status_set = dess_pppoe_status_set;
+        p_api->pppoe_status_get = dess_pppoe_status_get;
+        p_api->port_dhcp_set = dess_port_dhcp_set;
+        p_api->port_dhcp_get = dess_port_dhcp_get;
+        p_api->arp_cmd_set = dess_arp_cmd_set;
+        p_api->arp_cmd_get = dess_arp_cmd_get;
+        p_api->eapol_cmd_set = dess_eapol_cmd_set;
+        p_api->eapol_cmd_get = dess_eapol_cmd_get;
+        p_api->pppoe_session_table_add = dess_pppoe_session_table_add;
+        p_api->pppoe_session_table_del = dess_pppoe_session_table_del;
+        p_api->pppoe_session_table_get = dess_pppoe_session_table_get;
+        p_api->pppoe_session_id_set = dess_pppoe_session_id_set;
+        p_api->pppoe_session_id_get = dess_pppoe_session_id_get;
+        p_api->eapol_status_set = dess_eapol_status_set;
+        p_api->eapol_status_get = dess_eapol_status_get;
+        p_api->ripv1_status_set = dess_ripv1_status_set;
+        p_api->ripv1_status_get = dess_ripv1_status_get;
+        p_api->port_arp_req_status_set = dess_port_arp_req_status_set;
+        p_api->port_arp_req_status_get = dess_port_arp_req_status_get;
+        p_api->port_arp_ack_status_set = dess_port_arp_ack_status_set;
+        p_api->port_arp_ack_status_get = dess_port_arp_ack_status_get;
+        p_api->intr_mask_set = dess_intr_mask_set;
+        p_api->intr_mask_get = dess_intr_mask_get;
+        p_api->intr_status_get = dess_intr_status_get;
+        p_api->intr_status_clear = dess_intr_status_clear;
+        p_api->intr_port_link_mask_set = dess_intr_port_link_mask_set;
+        p_api->intr_port_link_mask_get = dess_intr_port_link_mask_get;
+        p_api->intr_port_link_status_get = dess_intr_port_link_status_get;
+        p_api->intr_mask_mac_linkchg_set = dess_intr_mask_mac_linkchg_set;
+        p_api->intr_mask_mac_linkchg_get = dess_intr_mask_mac_linkchg_get;
+        p_api->intr_status_mac_linkchg_get = dess_intr_status_mac_linkchg_get;
+        p_api->cpu_vid_en_set = dess_cpu_vid_en_set;
+        p_api->cpu_vid_en_get = dess_cpu_vid_en_get;
+        p_api->rtd_pppoe_en_set = dess_rtd_pppoe_en_set;
+        p_api->rtd_pppoe_en_get = dess_rtd_pppoe_en_get;
+        p_api->intr_status_mac_linkchg_clear = dess_intr_status_mac_linkchg_clear;
+		p_api->global_macaddr_set = dess_global_macaddr_set;
+		p_api->global_macaddr_get = dess_global_macaddr_get;
+		p_api->lldp_status_set = dess_lldp_status_set;
+        p_api->lldp_status_get = dess_lldp_status_get;
+		p_api->frame_crc_reserve_set = dess_frame_crc_reserve_set;
+        p_api->frame_crc_reserve_get = dess_frame_crc_reserve_get;
+
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/dess/dess_multicast_acl.c b/qca-ssdk/src/hsl/dess/dess_multicast_acl.c
new file mode 100755
index 0000000..7995737
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_multicast_acl.c
@@ -0,0 +1,1030 @@
+/*
+ * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#include "fal_nat.h"
+#include "fal_ip.h"
+#include "hsl_api.h"
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_igmp.h"
+#include "dess_reg.h"
+#include "dess_acl.h"
+#include "fal_multi.h"
+#include "sal/os/aos_lock.h"
+
+#if 0
+/**
+ * I/F prototype for complete igmpv3 & mldv2 support
+ */
+
+/*supports 32 entries*/
+#define FAL_IGMP_SG_ENTRY_MAX 32
+
+typedef enum
+{
+    FAL_ADDR_IPV4 = 0,
+    FAL_ADDR_IPV6
+} fal_addr_type_t;
+
+typedef struct
+{
+    fal_addr_type_t type;
+    union
+    {
+        fal_ip4_addr_t ip4_addr;
+        fal_ip6_addr_t ip6_addr;
+    } u;
+} fal_igmp_sg_addr_t;
+
+typedef struct
+{
+    fal_igmp_sg_addr_t source;
+    fal_igmp_sg_addr_t group;
+    fal_pbmp_t port_map;
+} fal_igmp_sg_entry_t;
+
+/**
+ * @brief set PortMap of IGMP sg entry.
+ *        search entry according to source/group address,
+ *        update PortMap if SG entry is found, otherwise create a new sg entry.
+ * @param[in] dev_id device id
+ * @param[in-out] entry SG entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+/**
+ * @brief clear PortMap of IGMP sg entry.
+ *        search entry according to source/group address,
+ *        update PortMap if SG entry is found, delete the entry in case PortMap was 0.
+ *        SW_NOT_FOUND will be returned in case search failed.
+ * @param[in] dev_id device id
+ * @param[in-out] entry SG entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+#define MULTI_DEBUG_
+#ifdef MULTI_DEBUG_
+#define MULTI_DEBUG(x...) aos_printk(x)
+#else
+#define MULTI_DEBUG(x...)
+#endif
+
+#define FAL_ACL_LIST_MULTICAST 55
+#define FAL_MULTICAST_PRI   5
+
+#define MULT_ACTION_SET      1
+#define MULT_ACTION_CLEAR    1
+
+static a_uint32_t rule_nr=1;
+
+typedef struct
+{
+    a_uint8_t index; //MAX is 32
+    fal_igmp_sg_entry_t entry; //Stores the specific ACL rule info
+} multi_acl_info_t;
+#endif
+
+static a_uint32_t mul_rule_nr=1;
+
+void
+dess_multicast_init(a_uint32_t dev_id);
+
+HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t pos, fal_igmp_sg_entry_t * entry);
+
+static multi_acl_info_t multi_acl_info[FAL_IGMP_SG_ENTRY_MAX];
+static multi_acl_info_t multi_acl_group[FAL_IGMP_SG_ENTRY_MAX];
+
+static int ip6_addr_is_null(fal_ip6_addr_t *ip6)
+{
+    if (NULL == ip6)
+    {
+        aos_printk("Invalid ip6 address\n");
+        return -1;
+    }
+    if(0 == ip6->ul[0] && 0 == ip6->ul[1] && 0 == ip6->ul[2] && 0 == ip6->ul[3])
+        return 1;
+    else
+        return 0;
+}
+static int multi_source_is_null(fal_igmp_sg_addr_t *s)
+{
+    if (NULL == s)
+    {
+        aos_printk("Invalid source address\n");
+        return -1;
+    }
+    if(0 == s->type && 0==s->u.ip4_addr)
+        return 1;
+    if(1 == s->type && 1 == ip6_addr_is_null(&(s->u.ip6_addr)))
+        return 1;
+
+    return 0;
+}
+
+HSL_LOCAL int iterate_multicast_acl_rule(int list_id, int start_n)
+{
+    a_uint32_t dev_id=0;
+    a_uint32_t rule_id;
+    sw_error_t ret;
+    fal_acl_rule_t  rule= {0};
+
+    if(start_n>=FAL_IGMP_SG_ENTRY_MAX || start_n < 0)
+    {
+        return -1;
+    }
+
+    for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+    {
+        ret = dess_acl_rule_query(dev_id, list_id, rule_id, &rule);
+
+        if (ret==SW_NOT_FOUND )
+            break;//NOT found in ACL rule
+        if((rule_id+start_n)>=FAL_IGMP_SG_ENTRY_MAX)
+        {
+            return -1;
+        }
+
+        multi_acl_info[rule_id+start_n].index = rule_id; // consider here... index is NOT related start_n
+        //MULTI_DEBUG("normal query1: rule dest_ip4_val=%x, src ip4=%x, dst_ip6=%x, ports=%x\n",
+        //rule.dest_ip4_val, rule.src_ip4_val, rule.dest_ip6_val.ul[0], rule.ports);
+
+        if(rule.dest_ip4_val !=0 && ip6_addr_is_null(&rule.dest_ip6_val))  //only ip4
+        {
+            multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV4;
+            multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV4;
+            multi_acl_info[rule_id+start_n].entry.group.u.ip4_addr = rule.dest_ip4_val;
+            multi_acl_info[rule_id+start_n].entry.source.u.ip4_addr = rule.src_ip4_val;
+            multi_acl_info[rule_id+start_n].entry.port_map= rule.ports;
+        }
+        else if(rule.dest_ip4_val ==0 && !ip6_addr_is_null(&rule.dest_ip6_val))  //only ip6
+        {
+            multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV6;
+            multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV6;
+            memcpy(&(multi_acl_info[rule_id+start_n].entry.group.u.ip6_addr), &(rule.dest_ip6_val), sizeof(rule.dest_ip6_val));
+            memcpy(&(multi_acl_info[rule_id+start_n].entry.source.u.ip6_addr), &(rule.src_ip6_val), sizeof(rule.src_ip6_val));
+            multi_acl_info[rule_id+start_n].entry.port_map= rule.ports;
+        }
+        if (FAL_FIELD_FLG_TST(rule.field_flg, FAL_ACL_FIELD_MAC_VID))
+        {
+            multi_acl_info[rule_id+start_n].entry.vlan_id = rule.vid_val;
+        }
+        else
+        {
+            multi_acl_info[rule_id+start_n].entry.vlan_id = 0xffff;
+        }
+    }
+
+    return rule_id+start_n;
+}
+/*
+** Iterate the total 32 multicast ACL entries.
+    After the function completes:
+         1. Stores all multicast related ACL rules in multi_acl_info[32]
+         2. return the number of multicast related ACL rules
+*/
+HSL_LOCAL a_uint32_t dess_multicast_acl_query(void)
+{
+    int start_n;
+    int total_n;
+    //a_uint32_t i;
+
+    start_n = iterate_multicast_acl_rule(FAL_ACL_LIST_MULTICAST, 0);
+    if(-1 == start_n)
+        aos_printk("ACL rule1 is FULL\n");
+    total_n = iterate_multicast_acl_rule(FAL_ACL_LIST_MULTICAST+1, start_n);
+    if(-1 == total_n)
+        aos_printk("ACL rule2 is FULL\n");
+
+    MULTI_DEBUG("KKK, the total ACL rule number is %d, (G,S) number=%d\n", total_n, start_n);
+    /*
+    for(i=0;i<total_n;i++)
+    MULTI_DEBUG("KKK, indx=%d, multi_acl_info[%d].entry=[%d][%x]\n", multi_acl_info[i].index,i,
+        multi_acl_info[i].entry.group.type, multi_acl_info[i].entry.group.u.ip4_addr );
+        */
+
+    return total_n;
+}
+
+HSL_LOCAL a_uint32_t dess_multicast_acl_total_n(a_uint32_t list_id)
+{
+    a_uint32_t dev_id=0;
+    a_uint32_t ret;
+    a_uint32_t rule_id;
+    fal_acl_rule_t  rule= {0};
+
+    for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+    {
+        ret = dess_acl_rule_query(dev_id, list_id,
+                                   rule_id, &rule);
+        if(ret==SW_NOT_FOUND)
+            return rule_id;
+
+    }
+    return 0;
+}
+
+#define DESS_FILTER_ACT_ADDR    0x5a000
+#define DESS_FILTER_MSK_ADDR    0x59000
+HSL_LOCAL sw_error_t multi_portmap_aclreg_set_all(a_uint32_t pos, fal_igmp_sg_entry_t * entry)
+{
+    a_uint32_t i, base, addr;
+    a_uint32_t dev_id=0;
+    a_uint32_t msk_valid=0;
+    sw_error_t rv = SW_OK;
+
+    /*  2'b00:start; 2'b01:continue; 2'b10:end; 2'b11:start&end*/
+    for(i=pos; i<pos+4; i++)
+    {
+        base = DESS_FILTER_MSK_ADDR +(i<<5);
+        addr = base+(4<<2); //fifth byte
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&msk_valid),
+                              sizeof (a_uint32_t));
+
+        SW_RTN_ON_ERROR(rv);
+        if ((((msk_valid>>6)&0x3) == 0x3) || (((msk_valid>>6)&0x3) == 0x2))
+        {
+            rv = multi_portmap_aclreg_set(i, entry);
+            break;
+        }
+        else if ((((msk_valid>>6)&0x3)) == 0x0 || (((msk_valid>>6)&0x3) == 0x1))
+        {
+            rv = multi_portmap_aclreg_set(i, entry);
+            continue;
+        }
+        else
+        {
+            aos_printk("The rule valid bit:6 7 is wrong!!!");
+            break;
+        }
+    }
+    return rv;
+}
+HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t pos, fal_igmp_sg_entry_t * entry)
+{
+    a_uint32_t i, base, addr;
+    a_uint32_t dev_id=0;
+    sw_error_t rv;
+    a_uint32_t act[3]= {0};
+    fal_pbmp_t pm;
+
+    pm = entry->port_map;
+
+    base = DESS_FILTER_ACT_ADDR + (pos << 4);
+    for (i = 0; i < 3; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&act[i]),
+                              sizeof (a_uint32_t));
+        //MULTI_DEBUG("2:Get register value  0x%x =%x\n", addr, act[i]);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    act[1] &= ~(0x7<<29); // clear the high 3 bits
+    act[1] |= (pm&0x7)<<29;  //the low 3 bits of pm means redirect port 0,1,2
+
+    /* New modification: update acl ACTION register from DENY to redirect */
+    if (((act[2]>>6)&0x7) == 0x7) //DENY mode
+    {
+        if(pm)
+        {
+            act[2] &= ~(0x7<<6);//clear DENY bits
+            act[2] |= (0x1<<4); //DES_PORT_EN set 1, enable
+        }
+    }
+    else if (((act[2]>>4)&0x1) == 0x1) //redirect mode
+    {
+        if(pm==0)
+        {
+            act[2] &= ~(0x1<<4);//clear redirect bits
+            act[2] |= (0x7<<6); //set to DENY
+        }
+    }
+
+    act[2] &= ~0xf; //clear the low 4 bits of port 3,4,5,6
+    act[2] |= (pm>>3)&0xf;
+
+    addr = base + (1<<2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&act[1]), sizeof (a_uint32_t));
+    addr = base + (2<<2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&act[2]), sizeof (a_uint32_t));
+    MULTI_DEBUG("pos=%d, before sync portmap, the new act=%x %x\n", pos, act[1],act[2]);
+    if((rv = dess_acl_rule_sync_multi_portmap(dev_id, pos, act)) < 0)
+        aos_printk("Sync multicast portmap error\n");
+    return rv;
+}
+
+HSL_LOCAL int multi_get_dp(void)
+{
+    a_uint32_t addr;
+    a_uint32_t dev_id=0;
+    sw_error_t rv;
+    int val=0;
+
+    addr = 0x624;//GLOBAL_FW_CTRL1
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&val),
+                          sizeof (a_uint32_t));
+    if (rv != SW_OK)
+        aos_printk("Get entry value error\n");
+
+    val = (val>>24)&0x7f; //30:24, IGMP_JOIN_LEAVE_DP
+
+    return val;
+}
+static int old_bind_p=-1;
+HSL_LOCAL int multi_acl_bind(void)
+{
+    int bind_p;
+    int i;
+
+    bind_p = multi_get_dp();
+    if(bind_p == old_bind_p)
+        return 0;
+    old_bind_p = bind_p;
+
+    for(i=0; i<7; i++)
+    {
+        dess_acl_list_unbind(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+        dess_acl_list_unbind(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+    }
+
+    if(bind_p==0)
+    {
+        for(i=0; i<7; i++)
+        {
+            dess_acl_list_bind(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+            dess_acl_list_bind(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+        }
+    }
+    else
+    {
+        for(i=0; i<7; i++)
+            if((bind_p>>i) &0x1)
+            {
+                dess_acl_list_bind(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+                dess_acl_list_bind(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+            }
+            else
+                continue;
+    }
+	return 0;
+}
+/*
+** Only update the related portmap from the privious input.
+*/
+HSL_LOCAL sw_error_t dess_multicast_acl_update( int list_id, int acl_index, fal_igmp_sg_entry_t * entry, int action)
+{
+    a_uint32_t dev_id=0;
+    a_uint32_t rule_pos;
+    sw_error_t rv = SW_OK;
+
+    if(acl_index<0)
+    {
+        aos_printk("Something is wrong...\n");
+        return SW_FAIL;
+    }
+
+    rule_pos = dess_acl_rule_get_offset(dev_id, list_id, multi_acl_group[acl_index].index);
+    if(MULT_ACTION_SET == action)
+    {
+        multi_acl_group[acl_index].entry.port_map |= entry->port_map;
+        if(entry->port_map == 0)
+        {
+            multi_acl_group[acl_index].entry.port_map = 0;
+        }
+    }
+    else if(MULT_ACTION_CLEAR == action)
+        multi_acl_group[acl_index].entry.port_map &= ~(entry->port_map);
+
+    rv = multi_portmap_aclreg_set_all(rule_pos, &multi_acl_group[acl_index].entry);
+
+    multi_acl_bind(); //Here need extra bind since IGMP join/leave would happen
+    return rv;
+}
+
+HSL_LOCAL sw_error_t dess_multicast_acl_del(int list_id, int index)
+{
+    sw_error_t rv;
+    int rule_id;
+
+    rule_id = multi_acl_group[index].index;
+
+    rv = dess_acl_rule_delete(0, list_id, rule_id, 1);
+    multi_acl_bind(); //Here need extra bind since IGMP join/leave would happen
+	return rv;
+}
+
+/*
+** Add new acl rule with parameters: DIP, SIP, redirect port.
+*/
+HSL_LOCAL sw_error_t dess_multicast_acl_add(int list_id, fal_igmp_sg_entry_t * entry)
+{
+    sw_error_t val;
+    a_uint32_t pos;
+    fal_acl_rule_t acl= {0};
+
+    /* IPv4 multicast */
+    if( entry->group.type == FAL_ADDR_IPV4 )
+    {
+        MULTI_DEBUG("KKK1, group[%d][%x], source[%d][%x]\n",entry->group.type,
+                    entry->group.u.ip4_addr, entry->source.type, entry->source.u.ip4_addr);
+
+        acl.rule_type = FAL_ACL_RULE_IP4;
+
+        if(entry->group.u.ip4_addr!= 0)
+        {
+            acl.dest_ip4_val = entry->group.u.ip4_addr;
+            acl.dest_ip4_mask = 0xffffffff;//e->ip.dmsk.s_addr;
+            FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_DIP);
+        }
+        if(entry->source.u.ip4_addr!= 0)
+        {
+            acl.src_ip4_val = entry->source.u.ip4_addr;
+            acl.src_ip4_mask = 0xffffffff;//e->ip.smsk.s_addr;
+            FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_SIP);
+        }
+        if( entry->port_map==0 )
+            FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY);
+        else
+            //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+            FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT );
+
+        /* Be careful, _dess_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */
+        if( entry->port_map )
+        {
+            FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT);
+            acl.ports = entry->port_map;
+        }
+    }
+    else if( entry->group.type == FAL_ADDR_IPV6 )
+    {
+        MULTI_DEBUG("KKK2, group[%d][%x], source[%d][%x], pm=%x\n",entry->group.type,
+                    entry->group.u.ip6_addr.ul[0], entry->source.type, entry->source.u.ip6_addr.ul[0], entry->port_map);
+
+        acl.rule_type = FAL_ACL_RULE_IP6;
+
+        if(!ip6_addr_is_null(&(entry->group.u.ip6_addr)))
+        {
+            memcpy(&acl.dest_ip6_val, &(entry->group.u.ip6_addr), sizeof(entry->group.u.ip6_addr));
+            acl.dest_ip6_mask.ul[0] = 0xffffffff;
+            acl.dest_ip6_mask.ul[1] = 0xffffffff;
+            acl.dest_ip6_mask.ul[2] = 0xffffffff;
+            acl.dest_ip6_mask.ul[3] = 0xffffffff;
+            FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_DIP);
+        }
+        if(!ip6_addr_is_null(&(entry->source.u.ip6_addr)))
+        {
+            memcpy(&acl.src_ip6_val, &(entry->source.u.ip6_addr), sizeof(entry->source.u.ip6_addr));
+            acl.src_ip6_mask.ul[0] = 0xffffffff;
+            acl.src_ip6_mask.ul[1] = 0xffffffff;
+            acl.src_ip6_mask.ul[2] = 0xffffffff;
+            acl.src_ip6_mask.ul[3] = 0xffffffff;
+            FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_SIP);
+        }
+
+        if( entry->port_map==0 )
+            FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY);
+        else
+            //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+            FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT );
+
+        /* Be careful, _dess_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */
+        if( entry->port_map )
+        {
+            FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT);
+            acl.ports = entry->port_map;
+        }
+    }
+
+    if (entry->vlan_id < 4096)
+    {
+        FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_MAC_VID);
+        acl.vid_val = entry->vlan_id;
+        acl.vid_op = FAL_ACL_FIELD_MASK;
+        acl.vid_mask = 0xfff;
+    }
+
+    pos = dess_multicast_acl_total_n(list_id);
+
+    MULTI_DEBUG("In dess_multicast_acl_add, list_id=%d, rule_id=%d\n", list_id, pos);
+    val = dess_acl_rule_add(0, list_id, pos, mul_rule_nr, &acl);
+
+    multi_acl_bind();
+
+    return val;
+}
+
+
+HSL_LOCAL int iterate_multicast_acl_group(a_uint32_t number, fal_igmp_sg_entry_t * entry)
+{
+    int count=0;
+    int i;
+
+    if (number == 0)
+        return 0; //no any ACL rules based the query
+
+    for(i=0; i<number; i++)
+    {
+
+        /*MULTI_DEBUG("2:iterate_multicast_acl_group, index=%d, multi_acl_info[%d].entry=type[%d]-addr[%x], pm=%x, new entry=type[%d]-addr[%x], pm=%x\n",
+            multi_acl_info[i].index,i, multi_acl_info[i].entry.group.type, multi_acl_info[i].entry.group.u.ip6_addr.ul[0], multi_acl_info[i].entry.port_map,
+            entry->group.type, entry->group.u.ip6_addr.ul[0], entry->port_map);*/
+
+        if(0 == memcmp(&(multi_acl_info[i].entry.group), &(entry->group), sizeof(entry->group)))
+        {
+            memcpy(&multi_acl_group[count], &multi_acl_info[i], sizeof(multi_acl_info[i]));
+            count++;//return the real number of multi_acl_group[]
+            MULTI_DEBUG("in iterate_multicast_acl_group, count=%d, i=%d\n", count, i);
+        }
+    }
+
+    return count;
+}
+
+HSL_LOCAL int mult_acl_has_entry(fal_igmp_sg_addr_t * group, fal_igmp_sg_addr_t *source)
+{
+    int rule_id;
+    int ret = 0;
+#if 0
+    if(source != NULL)
+    {
+        MULTI_DEBUG("new group[%d]= %x %x %x %x, new source[%d]=%x %x %x %x\n",
+                    group->type, group->u.ip6_addr.ul[0], group->u.ip6_addr.ul[1], group->u.ip6_addr.ul[2], group->u.ip6_addr.ul[3],
+                    source->type, source->u.ip6_addr.ul[0], source->u.ip6_addr.ul[1], source->u.ip6_addr.ul[2], source->u.ip6_addr.ul[3]);
+
+        MULTI_DEBUG("old group[%d]= %x %x %x %x, old source[%d]=%x %x %x %x\n",
+                    multi_acl_group[0].entry.group.type, multi_acl_group[0].entry.group.u.ip6_addr.ul[0],
+                    multi_acl_group[0].entry.group.u.ip6_addr.ul[1], multi_acl_group[0].entry.group.u.ip6_addr.ul[2], multi_acl_group[0].entry.group.u.ip6_addr.ul[3],
+                    multi_acl_group[0].entry.source.type, multi_acl_group[0].entry.source.u.ip6_addr.ul[0],
+                    multi_acl_group[0].entry.source.u.ip6_addr.ul[1], multi_acl_group[0].entry.source.u.ip6_addr.ul[2], multi_acl_group[0].entry.source.u.ip6_addr.ul[3]);
+    }
+#endif
+    if(source == NULL)
+    {
+        for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+        {
+            if( (0==memcmp(&multi_acl_group[rule_id].entry.group, group, sizeof(fal_igmp_sg_addr_t))) &&
+                    (multi_source_is_null(&multi_acl_group[rule_id].entry.source)))
+            {
+                MULTI_DEBUG("Source=0:Orignal ACL rule have this entry! rule id= %d\n", rule_id);
+                ret = rule_id+1; // ensure the return value is the actually number of entry
+                break;
+            }
+        }
+    }
+    else
+    {
+        for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+        {
+            if( (0==memcmp(&multi_acl_group[rule_id].entry.group, group, sizeof(fal_igmp_sg_addr_t))) &&
+                    (0==memcmp(&multi_acl_group[rule_id].entry.source, source, sizeof(fal_igmp_sg_addr_t))))
+            {
+                MULTI_DEBUG("Orignal ACL rule have this entry! rule id= %d\n", rule_id);
+                ret = rule_id+1; // ensure the return value is the actually number of entry
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+HSL_LOCAL int portmap_null(int index, fal_pbmp_t portmap)
+{
+    int val;
+    if (index<0)
+    {
+        aos_printk("portmap_null, index error\n");
+        return SW_FAIL;
+    }
+    val = multi_acl_group[index].entry.port_map&(~portmap);
+
+    if( 0 == (val&0xff) )
+        return 1;
+    else
+        return 0;
+}
+
+HSL_LOCAL int portmap_valid(fal_igmp_sg_entry_t *g_source, fal_igmp_sg_entry_t *g_star)
+{
+    /* return 0 means the portmap is Not valid
+        return 1 means the protmap is valid
+    */
+    /* MULTI_DEBUG("portmap_valid:g_source portmap=%x,  source=%x,group=%x, g_star portmap=%x, source=%x, group=%x\n",
+          g_source->port_map, g_source->source.u.ip4_addr, g_source->group.u.ip4_addr,
+          g_star->port_map, g_star->source.u.ip4_addr,g_star->group.u.ip4_addr);*/
+
+    if(multi_source_is_null(&(g_star->source)))
+    {
+        if((g_source->port_map|g_star->port_map) == g_star->port_map)
+        {
+            return 0;
+        }
+    }
+
+    return 1;
+}
+
+
+HSL_LOCAL int portmap_clear_type(int count, int index, fal_pbmp_t portmap)
+{
+    if(count>=0 && index<count) //new_index must >0; this means there're (G,*) and (G,S)
+    {
+        //if the new clear portmap will cause (G,S)=(G,*), Delete the (G,S)
+        if((multi_acl_group[index].entry.port_map & (~portmap)) == multi_acl_group[count].entry.port_map)
+            return 1; //delete
+
+
+        //The following means there must be at least one bit clear wrong. Clear the (G,*) portmap.
+        if( ((multi_acl_group[index].entry.port_map & (~portmap)) & (multi_acl_group[count].entry.port_map))
+                != (multi_acl_group[count].entry.port_map))
+            return 0;
+
+        return 2; //Normal update
+    }
+    return 0;
+}
+sw_error_t dess_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+    int number, count;
+    int new_index=0;
+    sw_error_t rv;
+    int action = MULT_ACTION_SET;
+    int i=0;
+
+    HSL_API_LOCK;
+    (void)dess_multicast_init(0);
+    aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    MULTI_DEBUG("Before query: group=%x, source=%x, portmap=%x\n", entry->group.u.ip4_addr, entry->source.u.ip4_addr, entry->port_map);
+    //number is the total multicast ACL rules amount, stores in multi_acl_info[];
+    number = dess_multicast_acl_query();
+
+    if(number > FAL_IGMP_SG_ENTRY_MAX)
+		return SW_FAIL;
+    //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number
+    count = iterate_multicast_acl_group(number, entry);
+    //new_index-1 is the found entry index in multi_acl_group[], the real index is [new_index-1], 0 means no entry
+    new_index = mult_acl_has_entry(&entry->group, &entry->source);
+
+    MULTI_DEBUG("Start entry set: number=%d, count=%d, new_index=%d, pm=%x\n", number, count, new_index, entry->port_map);
+    if( 0==multi_source_is_null(&entry->source) )  // new entry is (G, S)
+    {
+        MULTI_DEBUG("the new entry is (G,S)\n");
+        if(count>0 && 0 == portmap_valid(entry, &(multi_acl_group[count-1].entry))) //specfic group entry exist,(G,S) or (G,*)
+        {
+            //return SW_NO_CHANGE; // The new portmap is Not valid
+            MULTI_DEBUG("KKK, modified 1 !!!\n");
+        }
+
+        if(0 == new_index) //new entry, need add
+        {
+#if 0
+            /*The method:
+                1. predict if the portmap should be modified.
+                2. add new acl rule with new portmap value.
+            */
+            if((tmp_index = mult_acl_has_entry(&entry->group, NULL))>0) // (G, *) entry exist
+            {
+                /*Here the update should new (G, S) OR orignal (G,*) portmap,
+                be careful, entry's portmap value will be modified, so I use tmp_entry.
+                */
+                memcpy(tmp_entry, entry, sizeof(fal_igmp_sg_entry_t));
+                MULTI_DEBUG("Here, (G,*) exist! tmp_index=%d\n", tmp_index);
+                sw_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, tmp_index-1, tmp_entry, action);
+
+                dess_multicast_acl_add(FAL_ACL_LIST_MULTICAST, tmp_entry);
+                return SW_OK;
+            }
+#endif
+            dess_multicast_acl_add(FAL_ACL_LIST_MULTICAST, entry);
+            MULTI_DEBUG("Here, need add (G, S), portmap=%x\n", entry->port_map);
+            return SW_OK;
+        }
+        else
+        {
+            //Here update Just: the old exist entry portmap OR the new entry portmap
+            dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action);
+            return SW_OK;
+        }
+    } //end of memcmp
+    else  // new entry is (G, *)
+    {
+        if(0 == new_index) //new entry, need add
+        {
+            dess_multicast_acl_add(FAL_ACL_LIST_MULTICAST+1, entry);
+            rv = SW_OK;
+        }
+        else if(new_index > 0) // (G, *) entry exist?
+        {
+            //Update exist (G, *) portmap with new portmap
+            MULTI_DEBUG("(G,*) exist, before update, new_index=%d\n", new_index );
+            dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action);
+            rv = SW_OK;
+        }
+
+        if(new_index>0&&count>1) //(G,S*) and (G,*) exist, new entry is (G,*)
+        {
+            for(i=count-2; i>=0&&i<FAL_IGMP_SG_ENTRY_MAX; i--)
+            {
+                if(multi_acl_group[i].entry.port_map==0) //This ACL rule should be done nothing, DENY rule
+                    continue;
+
+                if(0 == portmap_valid(&(multi_acl_group[i].entry), &(multi_acl_group[count-1].entry)))
+                {
+                    MULTI_DEBUG("1:portmap is not valid, should delete, i=%d, source portmap=%x, gstar pm=%x\n",
+                                i, multi_acl_group[i].entry.port_map, multi_acl_group[count-1].entry.port_map);
+                    dess_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+                    rv = SW_NO_MORE;
+                }
+                else
+                {
+                    MULTI_DEBUG("1:Start update all (G,S),i=%d, gstar portmap=%x\n", i, multi_acl_group[count-1].entry.port_map);
+                    //Update all (G,S) entry portmap with new(G, *) portmap
+                    dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+                    rv = SW_OK;
+                }
+            }
+        }
+        else if(new_index==0&&count>0) //only exist (G,S*) orignally
+        {
+            for(i=count-1; i>=0&&i<FAL_IGMP_SG_ENTRY_MAX; i--)
+            {
+                if(multi_acl_group[i].entry.port_map==0) //This ACL rule should be done nothing, DENY rule
+                    continue;
+
+                if(0 == portmap_valid(&(multi_acl_group[i].entry), entry))
+                {
+                    MULTI_DEBUG("2:portmap is not valid, should delete, i=%d, source portmap=%x, gstar pm=%x\n",
+                                i, multi_acl_group[i].entry.port_map, entry->port_map);
+                    dess_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+                    rv = SW_NO_MORE;
+                }
+                else
+                {
+                    MULTI_DEBUG("2:Start update all (G,S),i=%d, portmap=%x\n", i, entry->port_map);
+                    //Update all (G,S) entry portmap with new(G, *) portmap
+                    dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+                    rv = SW_OK;
+                }
+            }
+        }
+    }
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t dess_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+    a_uint32_t number, count;
+    int new_index=0;
+    sw_error_t rv = SW_OK;
+    int action= MULT_ACTION_CLEAR;
+    int i=0;
+    int pm_type;
+
+    HSL_API_LOCK;
+    (void)dess_multicast_init(0);
+    aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    //number is the total multicast ACL rules amount, stores in multi_acl_info[];
+    number = dess_multicast_acl_query();
+    if(number > FAL_IGMP_SG_ENTRY_MAX)
+		return SW_FAIL;
+    //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number
+    count = iterate_multicast_acl_group(number, entry);
+	if(count == 0)
+		return SW_OK;
+    //new_index-1 is the found entry index in multi_acl_group[]
+    new_index = mult_acl_has_entry(&entry->group, &entry->source);
+
+    MULTI_DEBUG("Start entry clear: number=%d, count=%d, new_index=%d\n", number, count, new_index);
+    if(0 == new_index || new_index > FAL_IGMP_SG_ENTRY_MAX || count > FAL_IGMP_SG_ENTRY_MAX) //new entry, the user command is wrong
+    {
+        return SW_NO_SUCH;
+    }
+
+    if( 0==multi_source_is_null(&entry->source) )  // new entry is (G, S)
+    {
+        if (portmap_null(new_index-1, entry->port_map))
+        {
+            MULTI_DEBUG("KKK entry clear, new(G,S), with null portmap. \n");
+            dess_multicast_acl_del(FAL_ACL_LIST_MULTICAST, new_index-1);
+            return SW_OK;
+        }
+        else
+        {
+            MULTI_DEBUG("KKK entry clear, new(G,S), with NOT null portmap. \n");
+            /* If (G,*) doesn't exist, [count-1] is the last specfic group, maybe(G,*) */
+            if(0 == multi_source_is_null(&(multi_acl_group[count-1].entry.source)))
+            {
+                dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action);
+            }
+            else //(G,*) exist
+            {
+                pm_type = portmap_clear_type(count-1, new_index-1, entry->port_map);
+                if(pm_type == 0)
+                    return SW_NO_CHANGE;
+                else if(pm_type == 1)
+                {
+                    dess_multicast_acl_del(FAL_ACL_LIST_MULTICAST, new_index-1);
+                    return SW_OK;
+                }
+                else
+                {
+                    //normal update; consider here...wangson
+                    dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action);
+                }
+            }
+        }
+        return SW_OK;
+    }
+    else  //clear entry is (G,*)
+    {
+        MULTI_DEBUG("Here, new_index[%d]>=0, new portmap to clear is %x\n", new_index, entry->port_map);
+        if (portmap_null(new_index-1, entry->port_map))
+        {
+            dess_multicast_acl_del(FAL_ACL_LIST_MULTICAST+1, new_index-1);
+            rv = SW_OK;
+        }
+        else
+        {
+            MULTI_DEBUG("Update (G,*)!, new_index=%d, pm=%x\n", new_index, entry->port_map);
+            dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action);
+        }
+        MULTI_DEBUG("KKK, ready clear (G, S*), count=%d\n", count);
+#if 0
+        if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry
+        {
+            //count must >=2
+            for(i=count-2; i>=0; i--)
+            {
+                if(portmap_null(i, entry->port_map))
+                {
+                    MULTI_DEBUG("portmap_null, i=%d\n", i);
+                    dess_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+                    rv = SW_NO_MORE;
+                }
+                else
+                {
+                    //Update all (G,S) entry portmap with new(G, *) portmap
+                    dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+                    rv = SW_OK;
+                }
+            }
+        }
+#else
+        if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry
+        {
+            //count must >=2
+            for(i=count-2; i>=0&&i<FAL_IGMP_SG_ENTRY_MAX; i--)
+            {
+                //PortMap of entry (S,G) == (*,G) portmap after clear?
+                if((multi_acl_group[new_index-1].entry.port_map&(~(entry->port_map))) ==
+                        multi_acl_group[i].entry.port_map)
+                    dess_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+                else
+                    //Update all (G,S) entry portmap with new(G, *) portmap
+                    dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+                rv = SW_OK;
+            }
+        }
+#endif
+    }
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+static void
+print_ip4addr(char * param_name, a_uint32_t * buf,
+              a_uint32_t size)
+{
+    a_uint32_t i;
+    fal_ip4_addr_t ip4;
+
+    ip4 = *((fal_ip4_addr_t *) buf);
+    aos_printk("%s", param_name);
+    for (i = 0; i < 3; i++)
+    {
+        aos_printk("%d.", (ip4 >> (24 - i * 8)) & 0xff);
+    }
+    aos_printk("%d", (ip4 & 0xff));
+}
+static void
+print_ip6addr(char * param_name, a_uint32_t * buf,
+              a_uint32_t size)
+{
+    a_uint32_t i;
+    fal_ip6_addr_t ip6;
+
+    ip6 = *(fal_ip6_addr_t *) buf;
+    aos_printk("%s", param_name);
+    for (i = 0; i < 3; i++)
+    {
+        aos_printk("%x:%x:", (ip6.ul[i] >> 16) & 0xffff, ip6.ul[i] & 0xffff);
+    }
+    aos_printk("%x:%x", (ip6.ul[3] >> 16) & 0xffff, ip6.ul[3] & 0xffff);
+}
+sw_error_t dess_igmp_sg_entry_show(a_uint32_t dev_id)
+{
+    a_uint32_t number;
+    int i;
+
+    HSL_API_LOCK;
+    (void)dess_multicast_init(0);
+    aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    //number is the total multicast ACL rules amount, stores in multi_acl_info[];
+    number = dess_multicast_acl_query();
+
+    for(i=0; i<number; i++)
+    {
+        if(0 == multi_acl_info[i].entry.group.type)  //ipv4
+        {
+            aos_printk("\n[%d]:", i);
+            print_ip4addr(" [Group IPv4 addr]:", (a_uint32_t *)&(multi_acl_info[i].entry.group.u.ip4_addr), sizeof (fal_ip4_addr_t));
+            print_ip4addr(" [Source IPv4 addr]:", (a_uint32_t *)&(multi_acl_info[i].entry.source.u.ip4_addr), sizeof (fal_ip4_addr_t));
+            aos_printk("\n     [Portmap]: 0x%x ", multi_acl_info[i].entry.port_map);
+            aos_printk(" [Vlanid]: %d ", multi_acl_info[i].entry.vlan_id);
+        }
+        else if(1 == multi_acl_info[i].entry.group.type)  //ipv6
+        {
+            aos_printk("\n[%d]:", i);
+            print_ip6addr(" [Group IPv6 addr]: ", (a_uint32_t *)&(multi_acl_info[i].entry.group.u.ip6_addr), sizeof (fal_ip6_addr_t));
+            print_ip6addr(" [Source IPv6 addr]: ", (a_uint32_t *)&(multi_acl_info[i].entry.source.u.ip6_addr), sizeof (fal_ip6_addr_t));
+            aos_printk("\n     [Portmap]: 0x%x ", multi_acl_info[i].entry.port_map);
+            aos_printk(" [Vlanid]: %d ", multi_acl_info[i].entry.vlan_id);
+        }
+
+    }
+    aos_printk("\n\nTotal %d multicast ACL rules.\n", number);
+    HSL_API_UNLOCK;
+
+    return SW_OK;
+}
+
+void
+dess_multicast_init(a_uint32_t dev_id)
+{
+    sw_error_t val;
+
+    dess_acl_status_set(0, 1);
+
+    val = dess_acl_list_creat(0, FAL_ACL_LIST_MULTICAST, FAL_MULTICAST_PRI);
+    if(val !=SW_OK && val != SW_ALREADY_EXIST)
+        aos_printk("Multicast 1 acl list create error, val=%d\n", val);
+
+    val = dess_acl_list_creat(0, FAL_ACL_LIST_MULTICAST+1, FAL_MULTICAST_PRI+1);
+    if(val !=SW_OK && val != SW_ALREADY_EXIST)
+        aos_printk("Multicast 2 acl list create error, val=%d\n", val);
+
+}
+
+sw_error_t dess_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t *info)
+{
+    a_uint32_t number;
+    int i;
+
+    HSL_API_LOCK;
+    dess_multicast_init(0);
+    aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    /*number is the total multicast ACL rules amount, stores in multi_acl_info[];*/
+    number = dess_multicast_acl_query();
+    if(number > FAL_IGMP_SG_ENTRY_MAX)
+    {
+	    HSL_API_UNLOCK;
+	    return SW_FAIL;
+    }
+    info->cnt = number;
+
+    for(i=0; i<number; i++)
+    {
+        aos_mem_copy(&(info->acl_info[i]), &(multi_acl_info[i]), sizeof(multi_acl_info_t));
+    }
+    HSL_API_UNLOCK;
+
+    return SW_OK;
+}
+
diff --git a/qca-ssdk/src/hsl/dess/dess_nat.c b/qca-ssdk/src/hsl/dess/dess_nat.c
new file mode 100755
index 0000000..cbe9d57
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_nat.c
@@ -0,0 +1,3213 @@
+/*
+ * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_ip DESS_NAT
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_nat.h"
+#include "dess_reg.h"
+#if defined(IN_NAT_HELPER)
+#include "dess_nat_helper.h"
+#endif
+
+#define DESS_HOST_ENTRY_DATA0_ADDR              0x0e80
+#define DESS_HOST_ENTRY_DATA1_ADDR              0x0e84
+#define DESS_HOST_ENTRY_DATA2_ADDR              0x0e88
+#define DESS_HOST_ENTRY_DATA3_ADDR              0x0e8c
+#define DESS_HOST_ENTRY_DATA4_ADDR              0x0e90
+#define DESS_HOST_ENTRY_DATA5_ADDR              0x0e94
+#define DESS_HOST_ENTRY_DATA6_ADDR              0x0e98
+#define DESS_HOST_ENTRY_DATA7_ADDR              0x0e58
+
+#define DESS_HOST_ENTRY_REG_NUM                 8
+
+#define DESS_NAT_ENTRY_FLUSH                    1
+#define DESS_NAT_ENTRY_ADD                      2
+#define DESS_NAT_ENTRY_DEL                      3
+#define DESS_NAT_ENTRY_NEXT                     4
+#define DESS_NAT_ENTRY_SEARCH                   5
+
+#define DESS_ENTRY_NAPT                         0
+#define DESS_ENTRY_FLOW                         1
+#define DESS_ENTRY_NAT                          2
+#define DESS_ENTRY_ARP                          3
+
+#define DESS_PUB_ADDR_NUM                       16
+#define DESS_PUB_ADDR_TBL0_ADDR                 0x5aa00
+#define DESS_PUB_ADDR_TBL1_ADDR                 0x5aa04
+#define DESS_PUB_ADDR_EDIT0_ADDR                0x02100
+#define DESS_PUB_ADDR_EDIT1_ADDR                0x02104
+#define DESS_PUB_ADDR_OFFLOAD_ADDR              0x2f000
+#define DESS_PUB_ADDR_VALID_ADDR                0x2f040
+
+#define DESS_NAT_ENTRY_NUM                      32
+#define DESS_NAPT_ENTRY_NUM                     1024
+
+#define DESS_NAT_COUTER_ADDR                    0x2b000
+
+#define DESS_NAT_PORT_NUM                       255
+
+aos_lock_t dess_nat_lock;
+static a_uint32_t dess_nat_snap[SW_MAX_NR_DEV] = { 0 };
+extern a_uint32_t dess_nat_global_status;
+
+#if defined(IN_NAT_HELPER)
+extern void nat_helper_cookie_del(a_uint32_t hw_index);
+#endif
+
+static sw_error_t
+_dess_nat_feature_check(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (DESS_DEVICE_ID == entry)
+    {
+        return SW_OK;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+}
+
+static sw_error_t
+_dess_ip_prvaddr_sw_to_hw(a_uint32_t dev_id, fal_ip4_addr_t sw_addr,
+                          a_uint32_t * hw_addr)
+{
+    /*
+        sw_error_t rv;
+        a_uint32_t data;
+
+        HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        if (data) {
+            *hw_addr = (sw_addr & 0xff) | (((sw_addr >> 16) & 0xf) << 8);
+        } else {
+            *hw_addr = sw_addr & 0xfff;
+        }
+    */
+    *hw_addr = sw_addr;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_ip_prvaddr_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_addr,
+                          fal_ip4_addr_t * sw_addr)
+{
+    /*
+        sw_error_t rv;
+        a_uint32_t data, addr;
+
+        HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+                          (a_uint8_t *) (&addr), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        if (data) {
+            *sw_addr = ((addr & 0xff) << 8) | (((addr >> 8) & 0xfff) << 8)
+                | (hw_addr & 0xff) | (((hw_addr >> 8) & 0xf) << 16);
+        } else {
+            *sw_addr = (addr << 12) | (hw_addr & 0xfff);
+        }
+        */
+    *sw_addr = hw_addr;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id,
+                      a_uint32_t counter[4])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    addr = DESS_NAT_COUTER_ADDR + (cnt_id << 4);
+    for (i = 0; i < 4; i++)
+    {
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(counter[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        addr += 4;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op)
+{
+    a_uint32_t busy = 1, i = 0x9000000, entry = 0;
+    sw_error_t rv;
+
+
+    while (busy && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+                          sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry);
+    }
+
+    if (i == 0)
+    {
+	printk("busy 1\n");
+        return SW_BUSY;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_BUSY, 1, entry);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_SEL, entry_type, entry);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, ENTRY_FUNC, op, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    busy = 1;
+    i = 0x90000000;
+    while (busy && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+                          sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry);
+#if 1
+        if(DESS_NAT_ENTRY_SEARCH == op &&  busy) break;
+#endif
+    }
+
+    if (i == 0)
+    {
+	printk("busy 2\n");
+        return SW_BUSY;
+    }
+
+    /* hardware requirement, we should delay... */
+    if ((DESS_NAT_ENTRY_FLUSH == op) && ((DESS_ENTRY_NAPT == entry_type) ||
+		(DESS_ENTRY_FLOW == entry_type)))
+    {
+        aos_mdelay(10);
+    }
+
+    /* hardware requirement, we should read again... */
+    HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, busy, entry);
+    if (!busy)
+    {
+        if (DESS_NAT_ENTRY_NEXT == op)
+        {
+            return SW_NO_MORE;
+        }
+        else if (DESS_NAT_ENTRY_SEARCH == op)
+        {
+            return SW_NOT_FOUND;
+        }
+        else
+        {
+            return SW_FAIL;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_sw_to_hw(a_uint32_t dev_id, fal_nat_entry_t * entry, a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    if (FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & entry->flags)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    reg[0] = entry->trans_addr;
+
+    if (FAL_NAT_ENTRY_PORT_CHECK & entry->flags)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY3, PORT_EN, 1, reg[3]);
+        SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_RANGE, entry->port_range, reg[1]);
+        if (DESS_NAT_PORT_NUM < entry->port_range)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_NUM, entry->port_num, reg[1]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY3, PORT_EN, 0, reg[3]);
+    }
+
+    rv = _dess_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]);
+    SW_SET_REG_BY_FIELD(NAT_ENTRY2, PRV_IPADDR1, (data >> 8), reg[2]);
+
+    if (FAL_MAC_FRWRD == entry->action)
+    {
+        if (A_TRUE == entry->mirror_en)
+        {
+            SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 0, reg[2]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 3, reg[2]);
+        }
+    }
+    else if (FAL_MAC_CPY_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 2, reg[2]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 1, reg[2]);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->counter_en)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]);
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]);
+    }
+
+    if (FAL_NAT_ENTRY_PROTOCOL_ANY & entry->flags)
+    {
+        data = 3;
+    }
+    else if ((FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags)
+             && (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags))
+    {
+        data = 2;
+    }
+    else if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags)
+    {
+        data = 0;
+    }
+    else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(NAT_ENTRY3, PRO_TYP, data, reg[3]);
+	SW_SET_REG_BY_FIELD(NAT_ENTRY3, VRF_ID, entry->vrf_id, reg[3]);
+
+    SW_SET_REG_BY_FIELD(NAT_ENTRY2, HASH_KEY, entry->slct_idx, reg[2]);
+
+    SW_SET_REG_BY_FIELD(NAT_ENTRY3, ENTRY_VALID, 1, reg[3]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[], fal_nat_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, cnt[4] = {0};
+
+    entry->trans_addr = reg[0];
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY3, PORT_EN, data, reg[3]);
+    if (data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PORT_CHECK;
+        SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_RANGE, data, reg[1]);
+        entry->port_range = data;
+        SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_NUM, data, reg[1]);
+        entry->port_num = data;
+    }
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]);
+    entry->src_addr = data;
+    SW_GET_FIELD_BY_REG(NAT_ENTRY2, PRV_IPADDR1, data, reg[2]);
+    data = (entry->src_addr & 0xff) | (data << 8);
+
+    rv = _dess_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY2, ACTION, data, reg[2]);
+    entry->action = FAL_MAC_FRWRD;
+    if (0 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+    else if (2 == data)
+    {
+        entry->action = FAL_MAC_CPY_TO_CPU;
+    }
+    else if (1 == data)
+    {
+        entry->action = FAL_MAC_RDT_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_EN, data, reg[2]);
+    if (data)
+    {
+        entry->counter_en = A_TRUE;
+        SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]);
+
+        rv = _dess_nat_counter_get(dev_id, entry->counter_id, cnt);
+        SW_RTN_ON_ERROR(rv);
+
+        entry->ingress_packet = cnt[0];
+        entry->ingress_byte = cnt[1];
+        entry->egress_packet = cnt[2];
+        entry->egress_byte = cnt[3];
+    }
+    else
+    {
+        entry->counter_en = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY3, PRO_TYP, data, reg[3]);
+
+    if (3 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_ANY;
+    }
+    else if (2 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP;
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP;
+    }
+    else if (1 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP;
+    }
+    else if (0 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP;
+    }
+
+	SW_GET_FIELD_BY_REG(NAT_ENTRY3, VRF_ID, data, reg[3]);
+	entry->vrf_id = data;
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY2, HASH_KEY, data, reg[2]);
+    entry->slct_idx = data;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_napt_sw_to_hw(a_uint32_t dev_id, fal_napt_entry_t * entry,
+                    a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    reg[0] = entry->dst_addr;
+
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]);
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]);
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]);
+
+    rv = _dess_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]);
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]);
+
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+
+    if (FAL_MAC_FRWRD == entry->action)
+    {
+        if (A_TRUE == entry->mirror_en)
+        {
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 0, reg[3]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 3, reg[3]);
+        }
+    }
+    else if (FAL_MAC_CPY_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 2, reg[3]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 1, reg[3]);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->counter_en)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]);
+    }
+
+	if (A_TRUE == entry->priority_en)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, PRIORITY_EN, 1, reg[3]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, PRIORITY_VAL, entry->priority_val, reg[3]);
+    }
+
+    data = 2;
+    if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags)
+    {
+        data = 0;
+    }
+    else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags)
+    {
+        data = 1;
+    }
+    else if (FAL_NAT_ENTRY_PROTOCOL_PPTP & entry->flags)
+    {
+        data = 3;
+    }
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY3, PROT_TYP, data, reg[3]);
+
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]);
+	SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_SYNC, entry->aging_sync, reg[4]);
+	SW_SET_REG_BY_FIELD(NAPT_ENTRY4, VRF_ID, entry->vrf_id, reg[4]);
+	SW_SET_REG_BY_FIELD(NAPT_ENTRY4, FLOW_COOKIE, entry->flow_cookie, reg[4]);
+	SW_SET_REG_BY_FIELD(NAPT_ENTRY4, LOAD_BALANCE, entry->load_balance, reg[4]);
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_napt_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[],
+                    fal_napt_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, cnt[4] = {0};
+
+    entry->dst_addr = reg[0];
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]);
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]);
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]);
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY2, SRC_IPADDR0, data, reg[2]);
+    entry->src_addr = data;
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY3, SRC_IPADDR1, data, reg[3]);
+    data =  (entry->src_addr & 0xfff) | (data << 12);
+    rv = _dess_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr));
+    SW_RTN_ON_ERROR(rv);
+
+    entry->flags |= FAL_NAT_ENTRY_TRANS_IPADDR_INDEX;
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY3, ACTION, data, reg[3]);
+    entry->action = FAL_MAC_FRWRD;
+    if (0 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+    else if (2 == data)
+    {
+        entry->action = FAL_MAC_CPY_TO_CPU;
+    }
+    else if (1 == data)
+    {
+        entry->action = FAL_MAC_RDT_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_EN, data, reg[3]);
+    if (data)
+    {
+        entry->counter_en = A_TRUE;
+        SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]);
+
+        rv = _dess_nat_counter_get(dev_id, entry->counter_id, cnt);
+        SW_RTN_ON_ERROR(rv);
+
+        entry->ingress_packet = cnt[0];
+        entry->ingress_byte = cnt[1];
+        entry->egress_packet = cnt[2];
+        entry->egress_byte = cnt[3];
+    }
+    else
+    {
+        entry->counter_en = A_FALSE;
+    }
+
+	SW_GET_FIELD_BY_REG(NAPT_ENTRY3, PRIORITY_EN, data, reg[3]);
+	if (data)
+	{
+		entry->priority_en = A_TRUE;
+		SW_GET_FIELD_BY_REG(NAPT_ENTRY3, PRIORITY_VAL, entry->priority_val, reg[3]);
+	}
+	else
+	{
+		entry->priority_en = A_FALSE;
+	}
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY3, PROT_TYP, data, reg[3]);
+    if (0 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP;
+    }
+    else if (1 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP;
+    }
+    else if (3 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_PPTP;
+    }
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]);
+	SW_GET_FIELD_BY_REG(NAPT_ENTRY4, AGE_SYNC, entry->aging_sync, reg[4]);
+	SW_GET_FIELD_BY_REG(NAPT_ENTRY4, VRF_ID, entry->vrf_id, reg[4]);
+	SW_GET_FIELD_BY_REG(NAPT_ENTRY4, FLOW_COOKIE, entry->flow_cookie, reg[4]);
+	SW_GET_FIELD_BY_REG(NAPT_ENTRY4, LOAD_BALANCE, entry->load_balance, reg[4]);
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    for (i = 0; i < DESS_HOST_ENTRY_REG_NUM; i++)
+    {
+        if((DESS_HOST_ENTRY_REG_NUM - 1) == i)
+        {
+            addr = DESS_HOST_ENTRY_DATA7_ADDR;
+        }
+        else
+        {
+            addr = DESS_HOST_ENTRY_DATA0_ADDR + (i << 2);
+        }
+
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&reg[i]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    for (i = 0; i < DESS_HOST_ENTRY_REG_NUM; i++)
+    {
+        if((DESS_HOST_ENTRY_REG_NUM -1) == i)
+        {
+            addr = DESS_HOST_ENTRY_DATA7_ADDR;
+        }
+        else
+        {
+            addr = DESS_HOST_ENTRY_DATA0_ADDR + (i << 2);
+        }
+
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&reg[i]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_add(a_uint32_t dev_id, fal_nat_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < DESS_NAT_ENTRY_NUM; i++)
+    {
+        if (!(dess_nat_snap[dev_id] & (0x1 << i)))
+        {
+            break;
+        }
+    }
+
+    if (DESS_NAT_ENTRY_NUM == i)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    entry->entry_id = i;
+
+    rv = _dess_nat_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_ADD);
+    SW_RTN_ON_ERROR(rv);
+
+    dess_nat_snap[dev_id] |= (0x1 << i);
+    entry->entry_id = i;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NAT_ENTRY_ID_EN & del_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, ENTRY_FUNC, DESS_NAT_ENTRY_DEL, reg[7]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+
+        rv = _dess_nat_down_to_hw(dev_id, reg);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_DEL);
+        SW_RTN_ON_ERROR(rv);
+
+        dess_nat_snap[dev_id] &= (~(0x1 << entry->entry_id));
+    }
+    else
+    {
+        rv = _dess_nat_down_to_hw(dev_id, reg);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_FLUSH);
+        SW_RTN_ON_ERROR(rv);
+
+        dess_nat_snap[dev_id] = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NAT_ENTRY_ID_EN != get_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (!(dess_nat_snap[dev_id] & (0x1 << entry->entry_id)))
+    {
+        return SW_NOT_FOUND;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+
+    rv = _dess_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_SEARCH);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_hw_to_sw(dev_id, reg, entry);
+    return rv;
+}
+
+static sw_error_t
+_dess_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+               fal_nat_entry_t * nat_entry)
+{
+    a_uint32_t i, idx, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == nat_entry->entry_id)
+    {
+        idx = 0;
+    }
+    else
+    {
+        if ((DESS_NAT_ENTRY_NUM - 1) == nat_entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = nat_entry->entry_id + 1;
+        }
+    }
+
+    for (i = idx; i < DESS_NAT_ENTRY_NUM; i++)
+    {
+        if (dess_nat_snap[dev_id] & (0x1 << i))
+        {
+            break;
+        }
+    }
+
+    if (DESS_NAT_ENTRY_NUM == i)
+    {
+        return SW_NO_MORE;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, i, reg[7]);
+
+    rv = _dess_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_SEARCH);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    aos_mem_zero(nat_entry, sizeof (fal_nat_entry_t));
+
+    rv = _dess_nat_hw_to_sw(dev_id, reg, nat_entry);
+    SW_RTN_ON_ERROR(rv);
+
+    nat_entry->entry_id = i;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                       a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!(dess_nat_snap[dev_id] & (0x1 << entry_id)))
+    {
+        return SW_NOT_FOUND;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry_id, reg[7]);
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_SEARCH);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 0, reg[2]);
+    }
+    else if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]);
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, cnt_id, reg[2]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    /* needn't set TBL_IDX, keep hardware register value */
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_DEL);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    /* needn't set TBL_IDX, keep hardware register value */
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_ADD);
+    return rv;
+}
+
+static sw_error_t
+_dess_napt_add(a_uint32_t dev_id, fal_napt_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_napt_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+	aos_lock_bh(&dess_nat_lock);
+    rv = _dess_nat_down_to_hw(dev_id, reg);
+    	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+    	}
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_ADD);
+    	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+    	}
+
+    rv = _dess_nat_up_to_sw(dev_id, reg);
+    	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+    	}
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+	aos_unlock_bh(&dess_nat_lock);
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NAT_ENTRY_ID_EN & del_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_NAT_ENTRY_KEY_EN & del_mode)
+    {
+        rv = _dess_napt_sw_to_hw(dev_id, entry, reg);
+        SW_RTN_ON_ERROR(rv);
+
+	aos_lock_bh(&dess_nat_lock);
+        rv = _dess_nat_down_to_hw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+        rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_DEL);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+        rv = _dess_nat_up_to_sw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+        SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+	aos_unlock_bh(&dess_nat_lock);
+        return SW_OK;
+    }
+    else
+    {
+        if (FAL_NAT_ENTRY_PUBLIC_IP_EN & del_mode)
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_PIP, 1, reg[7]);
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+        }
+
+        if (FAL_NAT_ENTRY_SOURCE_IP_EN & del_mode)
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SIP, 1, reg[7]);
+            rv = _dess_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+            SW_RTN_ON_ERROR(rv);
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]);
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]);
+        }
+
+        if (FAL_NAT_ENTRY_AGE_EN & del_mode)
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]);
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]);
+        }
+
+	aos_lock_bh(&dess_nat_lock);
+        rv = _dess_nat_down_to_hw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+        rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_FLUSH);
+	aos_unlock_bh(&dess_nat_lock);
+        return rv;
+    }
+}
+
+static sw_error_t
+_dess_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t found, age, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+#if 0
+    if (FAL_NAT_ENTRY_ID_EN != get_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+#else
+    rv = _dess_napt_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+	aos_lock_bh(&dess_nat_lock);
+    rv = _dess_nat_down_to_hw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_SEARCH);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_nat_up_to_sw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+	aos_unlock_bh(&dess_nat_lock);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, found, reg[7]);
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY4, AGE_FLAG,  age, reg[4]);
+    if (found && age)
+    {
+        found = 1;
+    }
+    else
+    {
+        found = 0;
+    }
+
+    rv = _dess_napt_hw_to_sw(dev_id, reg, entry);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!found)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX,   entry->entry_id, reg[7]);
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                fal_napt_entry_t * napt_entry)
+{
+    a_uint32_t data, idx, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == napt_entry->entry_id)
+    {
+        idx = DESS_NAPT_ENTRY_NUM - 1;
+    }
+    else
+    {
+        if ((DESS_NAPT_ENTRY_NUM - 1) == napt_entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = napt_entry->entry_id;
+        }
+    }
+
+    if (FAL_NAT_ENTRY_PUBLIC_IP_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_PIP, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, napt_entry->trans_addr, reg[2]);
+    }
+
+    if (FAL_NAT_ENTRY_SOURCE_IP_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SIP, 1, reg[7]);
+        rv = _dess_ip_prvaddr_sw_to_hw(dev_id, napt_entry->src_addr, &data);
+        SW_RTN_ON_ERROR(rv);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]);
+    }
+
+    if (FAL_NAT_ENTRY_AGE_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, napt_entry->status, reg[4]);
+    }
+
+	if (FAL_NAT_ENTRY_SYNC_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SYNC, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_SYNC, napt_entry->aging_sync, reg[4]);
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, idx, reg[7]);
+
+	aos_lock_bh(&dess_nat_lock);
+    rv = _dess_nat_down_to_hw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_NEXT);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_nat_up_to_sw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+	aos_unlock_bh(&dess_nat_lock);
+
+    aos_mem_zero(napt_entry, sizeof (fal_nat_entry_t));
+
+    rv = _dess_napt_hw_to_sw(dev_id, reg, napt_entry);
+    SW_RTN_ON_ERROR(rv);
+
+#if 0
+    a_uint32_t temp=0, complete=0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&temp),
+                      sizeof (a_uint32_t));
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, complete, temp);
+
+    if (!complete)
+    {
+        return SW_NO_MORE;
+    }
+#endif
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, napt_entry->entry_id, reg[7]);
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                        a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    tbl_idx = (entry_id - 1) & 0x3ff;
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+
+    rv = _dess_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_NEXT);
+    if (SW_OK != rv)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    rv = _dess_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+    if (entry_id != tbl_idx)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 0, reg[3]);
+    }
+    else if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, cnt_id, reg[3]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_DEL);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_ADD);
+    return rv;
+}
+
+static sw_error_t
+_dess_flow_add(a_uint32_t dev_id, fal_napt_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_napt_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+	aos_lock_bh(&dess_nat_lock);
+    rv = _dess_nat_down_to_hw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_ADD);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_nat_up_to_sw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+	aos_unlock_bh(&dess_nat_lock);
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_flow_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NAT_ENTRY_ID_EN & del_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_NAT_ENTRY_KEY_EN & del_mode)
+    {
+        rv = _dess_napt_sw_to_hw(dev_id, entry, reg);
+        SW_RTN_ON_ERROR(rv);
+
+	aos_lock_bh(&dess_nat_lock);
+        rv = _dess_nat_down_to_hw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+        rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_DEL);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+        rv = _dess_nat_up_to_sw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+        SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+	aos_unlock_bh(&dess_nat_lock);
+        return SW_OK;
+    }
+    else
+    {
+        if (FAL_NAT_ENTRY_PUBLIC_IP_EN & del_mode)
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_PIP, 1, reg[7]);
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+        }
+
+        if (FAL_NAT_ENTRY_SOURCE_IP_EN & del_mode)
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SIP, 1, reg[7]);
+            rv = _dess_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+            SW_RTN_ON_ERROR(rv);
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]);
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]);
+        }
+
+        if (FAL_NAT_ENTRY_AGE_EN & del_mode)
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]);
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]);
+        }
+
+	aos_lock_bh(&dess_nat_lock);
+        rv = _dess_nat_down_to_hw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+        rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_FLUSH);
+	aos_unlock_bh(&dess_nat_lock);
+        return rv;
+    }
+}
+
+static sw_error_t
+_dess_flow_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t found, age, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+#if 0
+    if (FAL_NAT_ENTRY_ID_EN != get_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+#else
+    rv = _dess_napt_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+	aos_lock_bh(&dess_nat_lock);
+    rv = _dess_nat_down_to_hw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_SEARCH);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_nat_up_to_sw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+	aos_unlock_bh(&dess_nat_lock);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, found, reg[7]);
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY4, AGE_FLAG,  age, reg[4]);
+    if (found && age)
+    {
+        found = 1;
+    }
+    else
+    {
+        found = 0;
+    }
+
+    rv = _dess_napt_hw_to_sw(dev_id, reg, entry);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!found)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX,   entry->entry_id, reg[7]);
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_flow_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                fal_napt_entry_t * napt_entry)
+{
+    a_uint32_t data, idx, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 };
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == napt_entry->entry_id)
+    {
+        idx = DESS_NAPT_ENTRY_NUM - 1;
+    }
+    else
+    {
+        if ((DESS_NAPT_ENTRY_NUM - 1) == napt_entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = napt_entry->entry_id;
+        }
+    }
+
+    if (FAL_NAT_ENTRY_PUBLIC_IP_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_PIP, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, napt_entry->trans_addr, reg[2]);
+    }
+
+    if (FAL_NAT_ENTRY_SOURCE_IP_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SIP, 1, reg[7]);
+        rv = _dess_ip_prvaddr_sw_to_hw(dev_id, napt_entry->src_addr, &data);
+        SW_RTN_ON_ERROR(rv);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]);
+    }
+
+    if (FAL_NAT_ENTRY_AGE_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, napt_entry->status, reg[4]);
+    }
+
+	if (FAL_NAT_ENTRY_SYNC_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SYNC, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_SYNC, napt_entry->status, reg[4]);
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, idx, reg[7]);
+
+	aos_lock_bh(&dess_nat_lock);
+    rv = _dess_nat_down_to_hw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_NEXT);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+
+    rv = _dess_nat_up_to_sw(dev_id, reg);
+	if (rv != SW_OK) {
+		aos_unlock_bh(&dess_nat_lock);
+		return rv;
+	}
+	aos_unlock_bh(&dess_nat_lock);
+
+    aos_mem_zero(napt_entry, sizeof (fal_nat_entry_t));
+
+    rv = _dess_napt_hw_to_sw(dev_id, reg, napt_entry);
+    SW_RTN_ON_ERROR(rv);
+
+#if 0
+    a_uint32_t temp=0, complete=0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&temp),
+                      sizeof (a_uint32_t));
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, complete, temp);
+
+    if (!complete)
+    {
+        return SW_NO_MORE;
+    }
+#endif
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, napt_entry->entry_id, reg[7]);
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_flow_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                        a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    tbl_idx = (entry_id - 1) & 0x3ff;
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+
+    rv = _dess_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_NEXT);
+    if (SW_OK != rv)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    rv = _dess_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+    if (entry_id != tbl_idx)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 0, reg[3]);
+    }
+    else if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, cnt_id, reg[3]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_DEL);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_ADD);
+    return rv;
+}
+
+static sw_error_t
+_dess_nat_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_nat_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_dess_napt_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_napt_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_dess_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NAPT_FULL_CONE == mode)
+    {
+        data = 0;
+    }
+    else if (FAL_NAPT_STRICT_CONE == mode)
+    {
+        data = 1;
+    }
+    else if ((FAL_NAPT_PORT_STRICT == mode)
+             || (FAL_NAPT_SYNMETRIC == mode))
+    {
+        data = 2;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        *mode = FAL_NAPT_FULL_CONE;
+    }
+    else if (1 == data)
+    {
+        *mode = FAL_NAPT_STRICT_CONE;
+    }
+    else
+    {
+        *mode = FAL_NAPT_PORT_STRICT;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if ((FAL_NAT_HASH_KEY_PORT & mode)
+            && (FAL_NAT_HASH_KEY_IPADDR & mode))
+    {
+        data = 2;
+    }
+    else if (FAL_NAT_HASH_KEY_PORT & mode)
+    {
+        data = 0;
+    }
+    else if (FAL_NAT_HASH_KEY_IPADDR & mode)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *mode = 0;
+    if (0 == data)
+    {
+        *mode = FAL_NAT_HASH_KEY_PORT;
+    }
+    else if (1 == data)
+    {
+        *mode = FAL_NAT_HASH_KEY_IPADDR;
+    }
+    else if (2 == data)
+    {
+        *mode = FAL_NAT_HASH_KEY_PORT;
+        *mode |= FAL_NAT_HASH_KEY_IPADDR;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    data = addr;
+    HSL_REG_FIELD_SET(rv, dev_id, PRVIP_ADDR, 0, IP4_BASEADDR,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_ADDR, 0, IP4_BASEADDR,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    *addr = data;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t mask)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    data = mask;
+    HSL_REG_FIELD_SET(rv, dev_id, PRVIP_MASK, 0, IP4_BASEMASK,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * mask)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_MASK, 0, IP4_BASEMASK,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *mask = data;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_pub_addr_commit(a_uint32_t dev_id, fal_nat_pub_addr_t * entry,
+                          a_uint32_t op, a_uint32_t * empty)
+{
+    a_uint32_t index, addr, data, tbl[2] = { 0 };
+    sw_error_t rv;
+
+    *empty = DESS_PUB_ADDR_NUM;
+    for (index = 0; index < DESS_PUB_ADDR_NUM; index++)
+    {
+        addr = DESS_PUB_ADDR_TBL1_ADDR + (index << 4);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]);
+        if (data)
+        {
+            addr = DESS_PUB_ADDR_TBL0_ADDR + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[0])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            if (!aos_mem_cmp
+                    ((void *) &(entry->pub_addr), (void *) &(tbl[0]),
+                     sizeof (fal_ip4_addr_t)))
+            {
+                if (DESS_NAT_ENTRY_DEL == op)
+                {
+                    addr = DESS_PUB_ADDR_TBL1_ADDR + (index << 4);
+                    tbl[1] = 0;
+                    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                          (a_uint8_t *) (&(tbl[1])),
+                                          sizeof (a_uint32_t));
+                    *empty = index;
+                    return rv;
+                }
+                else if (DESS_NAT_ENTRY_ADD == op)
+                {
+                    entry->entry_id = index;
+                    return SW_ALREADY_EXIST;
+                }
+            }
+        }
+        else
+        {
+            *empty = index;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_dess_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, empty, addr, data = 0, tbl[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    tbl[0] = entry->pub_addr;
+    tbl[1] = 1;
+
+    rv = _dess_nat_pub_addr_commit(dev_id, entry, DESS_NAT_ENTRY_ADD, &empty);
+    if (SW_ALREADY_EXIST == rv)
+    {
+        return rv;
+    }
+
+    if (DESS_PUB_ADDR_NUM == empty)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    for (i = 0; i < 1; i++)
+    {
+        addr = DESS_PUB_ADDR_EDIT0_ADDR + (empty << 4) + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    addr = DESS_PUB_ADDR_OFFLOAD_ADDR + (empty << 2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    addr = DESS_PUB_ADDR_VALID_ADDR;
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data |= (0x1 << empty);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < 2; i++)
+    {
+        addr = DESS_PUB_ADDR_TBL0_ADDR + (empty << 4) + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    entry->entry_id = empty;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                       fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t empty, addr, data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_pub_addr_commit(dev_id, entry, DESS_NAT_ENTRY_DEL, &empty);
+    SW_RTN_ON_ERROR(rv);
+
+    addr = DESS_PUB_ADDR_VALID_ADDR;
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0x1 << empty));
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_dess_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                        fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, addr, idx, index, tbl[2] = {0};
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id)
+    {
+        idx = 0;
+    }
+    else
+    {
+        if ((DESS_PUB_ADDR_NUM - 1) == entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = entry->entry_id + 1;
+        }
+    }
+
+    for (index = idx; index < DESS_PUB_ADDR_NUM; index++)
+    {
+        addr = DESS_PUB_ADDR_TBL1_ADDR + (index << 4);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]);
+        if (data)
+        {
+            break;
+        }
+    }
+
+    if (DESS_PUB_ADDR_NUM == index)
+    {
+        return SW_NO_MORE;
+    }
+
+    addr = DESS_PUB_ADDR_TBL0_ADDR + (index << 4);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    entry->entry_id = index;
+    entry->pub_addr = tbl[0];
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+
+    return SW_OK;
+}
+
+#define DESS_NAT_VRF_ENTRY_TBL_ADDR   0x0484
+#define DESS_NAT_VRF_ENTRY_MASK_ADDR   0x0488
+
+a_uint8_t _dess_snat_matched(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+	a_bool_t nat_enable = 0, napt_enable = 0;
+	fal_ip4_addr_t mask = 0, base = 0;
+	a_uint32_t reg_addr;
+	sw_error_t rv;
+
+	_dess_nat_status_get(dev_id, &nat_enable);
+	_dess_napt_status_get(dev_id, &napt_enable);
+	if(!(nat_enable & napt_enable))
+		return 0;
+
+	/*check for private base ip*/
+	reg_addr = DESS_NAT_VRF_ENTRY_MASK_ADDR;
+	HSL_REG_ENTRY_GEN_GET(rv, dev_id, reg_addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&mask), sizeof (a_uint32_t));
+
+	reg_addr = DESS_NAT_VRF_ENTRY_TBL_ADDR;
+	HSL_REG_ENTRY_GEN_GET(rv, dev_id, reg_addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&base), sizeof (a_uint32_t));
+	if (rv)
+		return 0;
+	if((mask&addr) == (mask&base)) {
+		return 1;
+	}
+
+	return 0;
+}
+
+a_uint8_t _dess_dnat_matched(
+		a_uint32_t dev_id,
+		fal_ip4_addr_t addr,
+		a_uint8_t *index)
+{
+	a_bool_t nat_enable = 0, napt_enable = 0;
+	fal_nat_pub_addr_t entry;
+	sw_error_t ret;
+
+	_dess_nat_status_get(dev_id, &nat_enable);
+	_dess_napt_status_get(dev_id, &napt_enable);
+	if(!(nat_enable & napt_enable))
+		return 0;
+
+	/*check for public ip*/
+	memset(&entry, 0, sizeof(entry));
+	entry.entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+	while(1) {
+		ret = _dess_nat_pub_addr_next(dev_id, 0, &entry);
+		if(ret) {
+			break;
+		}
+		if(entry.pub_addr == addr) {
+			*index = entry.entry_id;
+			return 1;
+		}
+	}
+	return 0;
+}
+
+
+
+static sw_error_t
+_dess_flow_cookie_snat_set(a_uint32_t dev_id, fal_flow_cookie_t * flow_cookie)
+{
+	fal_napt_entry_t entry;
+	sw_error_t ret;
+
+	memset(&entry, 0, sizeof(entry));
+	entry.flags = FAL_NAT_ENTRY_TRANS_IPADDR_INDEX | flow_cookie->proto;
+	entry.status = 0xf;
+	entry.src_addr = flow_cookie->src_addr;
+	entry.dst_addr = flow_cookie->dst_addr;
+	entry.src_port = flow_cookie->src_port;
+	entry.dst_port = flow_cookie->dst_port;
+	entry.trans_port = flow_cookie->src_port;
+	entry.action = FAL_MAC_RDT_TO_CPU;
+	ret = _dess_napt_get(dev_id, 0, &entry);
+	if(ret) {
+		if(flow_cookie->flow_cookie == 0)
+			return SW_OK;
+	}
+	if(flow_cookie->flow_cookie == 0) {
+		if(entry.flow_cookie == 0) {
+			ret = _dess_napt_del(dev_id, FAL_NAT_ENTRY_KEY_EN, &entry);
+			#if defined(IN_NAT_HELPER)
+			#if 0
+			napt_cookie[entry.entry_id*2+1] = 0;
+			#endif
+			if (dess_nat_global_status)
+				nat_helper_cookie_del(entry.entry_id);
+			#endif
+			return ret;
+		}
+		ret = _dess_napt_del(dev_id, FAL_NAT_ENTRY_KEY_EN, &entry);
+	} else {
+		entry.flow_cookie = flow_cookie->flow_cookie;
+		ret = _dess_napt_add(dev_id, &entry);
+	}
+
+	return ret;
+}
+
+static sw_error_t
+_dess_flow_cookie_dnat_set(
+		a_uint32_t dev_id,
+		fal_flow_cookie_t * flow_cookie,
+		a_uint8_t index)
+{
+	fal_napt_entry_t entry;
+	sw_error_t ret = 0;
+
+	memset(&entry, 0, sizeof(entry));
+	entry.flags = FAL_NAT_ENTRY_TRANS_IPADDR_INDEX | flow_cookie->proto;
+	entry.status = 0xf;
+	entry.trans_addr = index;
+	entry.trans_port = flow_cookie->dst_port;
+	entry.dst_addr = flow_cookie->src_addr;
+	entry.dst_port = flow_cookie->src_port;
+	entry.src_port = flow_cookie->dst_port;
+	entry.action = FAL_MAC_RDT_TO_CPU;
+	ret = _dess_napt_get(dev_id, 0, &entry);
+	if(ret) {
+		if(flow_cookie->flow_cookie == 0) {
+			return SW_OK;
+		} else {
+			/*add a fresh flowcookie*/
+			entry.flow_cookie = flow_cookie->flow_cookie;
+			ret = _dess_napt_add(dev_id, &entry);
+			return ret;
+		}
+	}
+	if(flow_cookie->flow_cookie == 0) {
+		/*del flow cookie*/
+		if(entry.flow_cookie == 0) {
+			ret = _dess_napt_del(dev_id, FAL_NAT_ENTRY_KEY_EN, &entry);
+			#if defined(IN_NAT_HELPER)
+			#if 0
+			napt_cookie[entry.entry_id*2] = 0;
+			#endif
+			if (dess_nat_global_status)
+				nat_helper_cookie_del(entry.entry_id);
+			#endif
+			return ret;
+		}
+		ret = _dess_napt_del(dev_id, FAL_NAT_ENTRY_KEY_EN, &entry);
+		if(entry.load_balance & 4) {
+			/*keep rfs*/
+			entry.flow_cookie = 0;
+			ret = _dess_napt_add(dev_id, &entry);
+			return ret;
+		}
+	} else {
+		/*add flow cookie*/
+		ret = _dess_napt_del(dev_id, FAL_NAT_ENTRY_KEY_EN, &entry);
+		entry.flow_cookie = flow_cookie->flow_cookie;
+		ret = _dess_napt_add(dev_id, &entry);
+		return ret;
+	}
+	return ret;
+
+}
+
+static sw_error_t
+_dess_flow_rfs_dnat_set(
+		a_uint32_t dev_id,
+		a_uint8_t action,
+		fal_flow_rfs_t * rfs,
+		a_uint8_t index)
+{
+	fal_napt_entry_t entry;
+	sw_error_t ret = 0;
+
+	memset(&entry, 0, sizeof(entry));
+	entry.flags = FAL_NAT_ENTRY_TRANS_IPADDR_INDEX | rfs->proto;
+	entry.status = 0xf;
+	entry.trans_addr = index;
+	entry.trans_port = rfs->dst_port;
+	entry.dst_addr = rfs->src_addr;
+	entry.dst_port = rfs->src_port;
+	entry.src_port = rfs->dst_port;
+	entry.action = FAL_MAC_RDT_TO_CPU;
+	ret = _dess_napt_get(dev_id, 0, &entry);
+	if(ret) {
+		if(action == 0) {
+			return SW_FAIL;
+		} else {
+			/*add a fresh rfs*/
+			entry.load_balance = rfs->load_balance | 4;
+			ret = _dess_napt_add(dev_id, &entry);
+			return ret;
+		}
+	}
+	if(action == 0) {
+		/*del flow rfs*/
+		ret = _dess_napt_del(dev_id, FAL_NAT_ENTRY_KEY_EN, &entry);
+		if(entry.flow_cookie != 0) {
+			/*keep cookie*/
+			entry.load_balance = 0;
+			ret = _dess_napt_add(dev_id, &entry);
+			return ret;
+		}
+	} else {
+		/*add flow rfs*/
+		ret = _dess_napt_del(dev_id, FAL_NAT_ENTRY_KEY_EN, &entry);
+		entry.load_balance = rfs->load_balance | 4;
+		ret = _dess_napt_add(dev_id, &entry);
+		return ret;
+	}
+	return ret;
+
+}
+
+
+static sw_error_t
+_dess_flow_cookie_set(a_uint32_t dev_id, fal_flow_cookie_t * flow_cookie)
+{
+	fal_napt_entry_t entry;
+	sw_error_t ret;
+	a_uint8_t index;
+
+	if(_dess_dnat_matched(dev_id, flow_cookie->dst_addr, &index))
+		return _dess_flow_cookie_dnat_set(dev_id, flow_cookie, index);
+	if(_dess_snat_matched(dev_id, flow_cookie->src_addr))
+		return _dess_flow_cookie_snat_set(dev_id, flow_cookie);
+
+	/*normal flow*/
+	memset(&entry, 0, sizeof(entry));
+	entry.flags = flow_cookie->proto;
+	entry.src_addr = flow_cookie->src_addr;
+	entry.dst_addr = flow_cookie->dst_addr;
+	entry.src_port = flow_cookie->src_port;
+	entry.dst_port = flow_cookie->dst_port;
+    ret = _dess_flow_get(0, 0, &entry);
+	if(SW_OK != ret && flow_cookie->flow_cookie == 0)
+		return ret;
+	if(flow_cookie->flow_cookie == 0) {
+		/*del*/
+		_dess_flow_del(0, FAL_NAT_ENTRY_KEY_EN, &entry);
+		if(entry.load_balance & 4) {
+			entry.status = 0xf;
+			entry.flow_cookie = 0;
+			return _dess_flow_add(0, &entry);
+		}
+	} else {
+		/*add*/
+		if(ret == SW_OK)
+			_dess_flow_del(0, FAL_NAT_ENTRY_KEY_EN, &entry);
+		entry.status = 0xf;
+		entry.flow_cookie = flow_cookie->flow_cookie;
+		return _dess_flow_add(0, &entry);
+	}
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_flow_rfs_set(a_uint32_t dev_id, a_uint8_t action, fal_flow_rfs_t * rfs)
+{
+	fal_napt_entry_t entry;
+	sw_error_t ret;
+	a_uint8_t index;
+
+	if(_dess_dnat_matched(dev_id, rfs->dst_addr, &index))
+		return _dess_flow_rfs_dnat_set(dev_id, action, rfs, index);
+
+	memset(&entry, 0, sizeof(entry));
+	entry.flags = rfs->proto;
+	entry.src_addr = rfs->src_addr;
+	entry.dst_addr = rfs->dst_addr;
+	entry.src_port = rfs->src_port;
+	entry.dst_port = rfs->dst_port;
+	ret = _dess_flow_get(0, 0, &entry);
+	if(SW_OK != ret && action == 0)
+		return ret;
+	if(action == 0) {
+		/*del*/
+		_dess_flow_del(0, FAL_NAT_ENTRY_KEY_EN, &entry);
+		if(entry.flow_cookie != 0) {
+			entry.load_balance = 0;
+			return _dess_flow_add(0, &entry);
+		}
+	} else {
+		/*add*/
+		if(ret == SW_OK)
+			_dess_flow_del(0, FAL_NAT_ENTRY_KEY_EN, &entry);
+		entry.status = 0xf;
+		entry.load_balance = rfs->load_balance | 0x4;
+		return _dess_flow_add(0, &entry);
+	}
+	return SW_OK;
+}
+
+
+
+sw_error_t
+dess_nat_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t index, addr, data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    dess_nat_snap[dev_id] = 0;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_FLUSH);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_FLUSH);
+    SW_RTN_ON_ERROR(rv);
+
+	rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_FLUSH);
+    SW_RTN_ON_ERROR(rv);
+
+    for (index = 0; index < DESS_PUB_ADDR_NUM; index++)
+    {
+        addr = DESS_PUB_ADDR_TBL1_ADDR + (index << 4);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Add one NAT entry to one particular device.
+ *   @details Comments:
+       Before NAT entry added ip4 private base address must be set
+       at first.
+       In parameter nat_entry entry flags must be set
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_add(dev_id, nat_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Del NAT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode NAT entry delete operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_del(a_uint32_t dev_id, a_uint32_t del_mode,
+             fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_del(dev_id, del_mode, nat_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get one NAT entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode NAT entry get operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @param[out] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_get(a_uint32_t dev_id, a_uint32_t get_mode,
+             fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_get(dev_id, get_mode, nat_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next NAT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode NAT entry next operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @param[out] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+              fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_next(dev_id, next_mode, nat_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one NAT entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id NAT entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id,
+                      a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_counter_bind(dev_id, entry_id, cnt_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one NAPT entry to one particular device.
+ *   @details Comments:
+       Before NAPT entry added related ip4 private base address must be set
+       at first.
+       In parameter napt_entry related entry flags must be set
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_napt_add(dev_id, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Del NAPT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode NAPT entry delete operation mode
+ * @param[in] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_napt_del(a_uint32_t dev_id, a_uint32_t del_mode,
+              fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_napt_del(dev_id, del_mode, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get one NAPT entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode NAPT entry get operation mode
+ * @param[in] nat_entry NAPT entry parameter
+ * @param[out] nat_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_napt_get(a_uint32_t dev_id, a_uint32_t get_mode,
+              fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_napt_get(dev_id, get_mode, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next NAPT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode NAPT entry next operation mode
+ * @param[in] napt_entry NAPT entry parameter
+ * @param[out] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+               fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_napt_next(dev_id, next_mode, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one NAPT entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id NAPT entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                       a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_napt_counter_bind(dev_id, entry_id, cnt_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one FLOW entry to one particular device.
+ *   @details Comments:
+       Before FLOW entry added related ip4 private base address must be set
+       at first.
+       In parameter napt_entry related entry flags must be set
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] napt_entry FLOW entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_flow_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_flow_add(dev_id, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Del FLOW entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode FLOW entry delete operation mode
+ * @param[in] napt_entry FLOW entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_flow_del(a_uint32_t dev_id, a_uint32_t del_mode,
+              fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_flow_del(dev_id, del_mode, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get one FLOW entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode FLOW entry get operation mode
+ * @param[in] nat_entry FLOW entry parameter
+ * @param[out] nat_entry FLOW entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_flow_get(a_uint32_t dev_id, a_uint32_t get_mode,
+              fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_flow_get(dev_id, get_mode, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next FLOW entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode FLOW entry next operation mode
+ * @param[in] napt_entry FLOW entry parameter
+ * @param[out] napt_entry FLOW entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_flow_next(a_uint32_t dev_id, a_uint32_t next_mode,
+               fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_flow_next(dev_id, next_mode, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one FLOW entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id FLOW entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_flow_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                       a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_flow_counter_bind(dev_id, entry_id, cnt_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set NAT hash mode on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mode NAT hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_hash_mode_set(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get NAT hash mode on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mode NAT hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_hash_mode_get(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_napt_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_napt_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working status of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_napt_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_napt_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working mode of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mode NAPT mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_napt_mode_set(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working mode of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mode NAPT mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_napt_mode_get(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP4 private base address on a particular device
+ *   @details Comments:
+        Only 20bits is meaning which 20bits is determined by private address mode.
+ * @param[in] dev_id device id
+ * @param[in] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_prv_base_addr_set(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[out] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_prv_base_addr_get(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mask private base mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t mask)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_prv_base_mask_set(dev_id, mask);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mask private base mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * mask)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_prv_base_mask_get(dev_id, mask);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one public address entry to one particular device.
+ *   @details Comments:
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_pub_addr_add(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one public address entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operaton mode
+ * @param[in] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                      fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_pub_addr_del(dev_id, del_mode, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next public address entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operaton mode
+ * @param[out] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                       fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_pub_addr_next(dev_id, next_mode, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set forwarding command for those packets miss NAT entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_unk_session_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get forwarding command for those packets miss NAT entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nat_unk_session_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] portbmp port bitmap
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nat_global_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t portbmp)
+{
+    sw_error_t rv = SW_OK;
+
+    HSL_API_LOCK;
+    printk("enable:%d\n", enable);
+    if(enable) {
+        if(dess_nat_global_status == 0) {
+            dess_nat_global_status = 1;
+#if defined(IN_NAT_HELPER)
+            DESS_NAT_HELPER_INIT(rv, dev_id, portbmp);
+#endif
+        }
+    } else {
+        if(dess_nat_global_status == 1) {
+            dess_nat_global_status = 0;
+#if defined(IN_NAT_HELPER)
+            DESS_NAT_HELPER_CLEANUP(rv, dev_id);
+#endif
+        }
+    }
+    //rv = SW_OK;
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add/del one FLOW cookie entry to one particular device.
+ *   @details Comments:
+       Before FLOW entry added related ip4 private base address must be set
+       at first.
+       In parameter napt_entry related entry flags must be set
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in]  FLOW cookie entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_flow_cookie_set(a_uint32_t dev_id, fal_flow_cookie_t * flow_cookie)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_flow_cookie_set(dev_id, flow_cookie);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add/del one FLOW rfs entry to one particular device.
+ *   @details Comments:
+       Before FLOW entry added related ip4 private base address must be set
+       at first.
+       In parameter napt_entry related entry flags must be set
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in]  FLOW cookie entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_flow_rfs_set(a_uint32_t dev_id, a_uint8_t action, fal_flow_rfs_t * rfs)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_flow_rfs_set(dev_id, action, rfs);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+
+sw_error_t
+dess_nat_init(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+	aos_lock_init(&dess_nat_lock);
+
+    rv = dess_nat_reset(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->nat_add = dess_nat_add;
+        p_api->nat_del = dess_nat_del;
+        p_api->nat_get = dess_nat_get;
+        p_api->nat_next = dess_nat_next;
+        p_api->nat_counter_bind = dess_nat_counter_bind;
+        p_api->napt_add = dess_napt_add;
+        p_api->napt_del = dess_napt_del;
+        p_api->napt_get = dess_napt_get;
+        p_api->napt_next = dess_napt_next;
+        p_api->napt_counter_bind = dess_napt_counter_bind;
+		p_api->flow_add = dess_flow_add;
+        p_api->flow_del = dess_flow_del;
+        p_api->flow_get = dess_flow_get;
+        p_api->flow_next = dess_flow_next;
+        p_api->flow_counter_bind = dess_flow_counter_bind;
+        p_api->nat_status_set = dess_nat_status_set;
+        p_api->nat_status_get = dess_nat_status_get;
+        p_api->nat_hash_mode_set = dess_nat_hash_mode_set;
+        p_api->nat_hash_mode_get = dess_nat_hash_mode_get;
+        p_api->napt_status_set = dess_napt_status_set;
+        p_api->napt_status_get = dess_napt_status_get;
+        p_api->napt_mode_set = dess_napt_mode_set;
+        p_api->napt_mode_get = dess_napt_mode_get;
+        p_api->nat_pub_addr_add = dess_nat_pub_addr_add;
+        p_api->nat_pub_addr_del = dess_nat_pub_addr_del;
+        p_api->nat_pub_addr_next = dess_nat_pub_addr_next;
+        p_api->nat_unk_session_cmd_set = dess_nat_unk_session_cmd_set;
+        p_api->nat_unk_session_cmd_get = dess_nat_unk_session_cmd_get;
+        p_api->nat_prv_base_addr_set = dess_nat_prv_base_addr_set;
+        p_api->nat_prv_base_addr_get = dess_nat_prv_base_addr_get;
+        p_api->nat_prv_base_mask_set = dess_nat_prv_base_mask_set;
+        p_api->nat_prv_base_mask_get = dess_nat_prv_base_mask_get;
+        p_api->nat_global_set = dess_nat_global_set;
+		p_api->flow_cookie_set = dess_flow_cookie_set;
+		p_api->flow_rfs_set = dess_flow_rfs_set;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/dess/dess_port_ctrl.c b/qca-ssdk/src/hsl/dess/dess_port_ctrl.c
new file mode 100755
index 0000000..f038ee9
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_port_ctrl.c
@@ -0,0 +1,3983 @@
+/*
+ * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_port_ctrl DESS_PORT_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_port_ctrl.h"
+#include "dess_reg.h"
+#include "hsl_phy.h"
+
+#define DMA_MAX_VIRT_RING 8
+extern a_bool_t dess_mac_port_valid_check (fal_port_t port_id);
+
+/*
+PORT0 egress 6 queues
+PORT1~4 egress 4 queues
+PORT5 egress 6 queues
+*/
+static a_uint32_t port_queue[6] = { 6, 4, 4, 4, 4, 6 };
+
+
+static a_bool_t
+_dess_port_phy_connected (a_uint32_t dev_id, fal_port_t port_id)
+{
+  if (0 == port_id)
+    {
+      return A_FALSE;
+    }
+  else
+    {
+
+      return dess_mac_port_valid_check (port_id);
+    }
+}
+
+static sw_error_t
+_dess_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id,
+		       fal_port_duplex_t duplex)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_duplex_set)
+    return SW_NOT_SUPPORTED;
+
+  if (FAL_DUPLEX_BUTT <= duplex)
+    {
+      return SW_BAD_PARAM;
+    }
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+      SW_RTN_ON_ERROR (rv);
+
+      rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex);
+      SW_RTN_ON_ERROR (rv);
+#if 0
+  HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+  /* for those ports without PHY device we set MAC register */
+  if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
+    {
+      SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg_val);
+      if (FAL_HALF_DUPLEX == duplex)
+	{
+	  SW_SET_REG_BY_FIELD (PORT_STATUS, DUPLEX_MODE, 0, reg_val);
+	}
+      else
+	{
+	  SW_SET_REG_BY_FIELD (PORT_STATUS, DUPLEX_MODE, 1, reg_val);
+	}
+      reg_save = reg_val;
+    }
+  else
+    {
+      /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
+      reg_save = reg_val;
+      SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg_val);
+      SW_SET_REG_BY_FIELD (PORT_STATUS, RXMAC_EN, 0, reg_val);
+      SW_SET_REG_BY_FIELD (PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+      HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
+			 (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+      rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+      SW_RTN_ON_ERROR (rv);
+
+      rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex);
+      SW_RTN_ON_ERROR (rv);
+
+      /* If MAC not in sync with PHY mode, the behavior is undefine.
+         You must be careful... */
+      SW_GET_FIELD_BY_REG (PORT_STATUS, LINK_EN, force, reg_save);
+      if (!force)
+	{
+	  if (FAL_HALF_DUPLEX == duplex)
+	    {
+	      SW_SET_REG_BY_FIELD (PORT_STATUS, DUPLEX_MODE, 0, reg_save);
+	    }
+	  else
+	    {
+	      SW_SET_REG_BY_FIELD (PORT_STATUS, DUPLEX_MODE, 1, reg_save);
+	    }
+	}
+    }
+
+  HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg_save), sizeof (a_uint32_t));
+  #endif
+  return rv;
+}
+
+static sw_error_t
+_dess_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id,
+		       fal_port_duplex_t * pduplex)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	/* for those ports without PHY device supposed always full duplex */
+	if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
+	{
+		*pduplex = FAL_FULL_DUPLEX;
+	}
+	else
+	{
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+		if (NULL == phy_drv->phy_duplex_get)
+			return SW_NOT_SUPPORTED;
+
+		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR (rv);
+
+		rv = phy_drv->phy_duplex_get (dev_id, phy_id, pduplex);
+		SW_RTN_ON_ERROR (rv);
+	}
+#if 0
+  HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  SW_GET_FIELD_BY_REG (PORT_STATUS, DUPLEX_MODE, field, reg);
+  if (field)
+    {
+      *pduplex = FAL_FULL_DUPLEX;
+    }
+  else
+    {
+      *pduplex = FAL_HALF_DUPLEX;
+    }
+
+#endif
+
+	return rv;
+}
+
+static sw_error_t
+_dess_port_speed_set (a_uint32_t dev_id, fal_port_t port_id,
+		      fal_port_speed_t speed)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_speed_set)
+    return SW_NOT_SUPPORTED;
+
+  if (FAL_SPEED_1000 < speed)
+    {
+      return SW_BAD_PARAM;
+    }
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+      SW_RTN_ON_ERROR (rv);
+
+      rv = phy_drv->phy_speed_set (dev_id, phy_id, speed);
+      SW_RTN_ON_ERROR (rv);
+#if 0
+  HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+  /* for those ports without PHY device we set MAC register */
+  if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
+    {
+      SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg_val);
+      if (FAL_SPEED_10 == speed)
+	{
+	  SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 0, reg_val);
+	}
+      else if (FAL_SPEED_100 == speed)
+	{
+	  SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 1, reg_val);
+	}
+      else
+	{
+	  SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 2, reg_val);
+	}
+      reg_save = reg_val;
+
+    }
+  else
+    {
+      /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
+      reg_save = reg_val;
+      SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg_val);
+      SW_SET_REG_BY_FIELD (PORT_STATUS, RXMAC_EN, 0, reg_val);
+      SW_SET_REG_BY_FIELD (PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+      HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
+			 (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+      rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+      SW_RTN_ON_ERROR (rv);
+
+      rv = phy_drv->phy_speed_set (dev_id, phy_id, speed);
+      SW_RTN_ON_ERROR (rv);
+
+      /* If MAC not in sync with PHY mode, the behavior is undefine.
+         You must be careful... */
+      SW_GET_FIELD_BY_REG (PORT_STATUS, LINK_EN, force, reg_save);
+      if (!force)
+	{
+	  if (FAL_SPEED_10 == speed)
+	    {
+	      SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 0, reg_save);
+	    }
+	  else if (FAL_SPEED_100 == speed)
+	    {
+	      SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 1, reg_save);
+	    }
+	  else
+	    {
+	      SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 2, reg_save);
+	    }
+	}
+    }
+
+  HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg_save), sizeof (a_uint32_t));
+  #endif
+  return rv;
+}
+
+static sw_error_t
+_dess_port_speed_get (a_uint32_t dev_id, fal_port_t port_id,
+		      fal_port_speed_t * pspeed)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	/* for those ports without PHY device supposed always 1000Mbps */
+	if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
+	{
+		*pspeed = FAL_SPEED_1000;
+	}
+	else
+	{
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+		if (NULL == phy_drv->phy_speed_get)
+			return SW_NOT_SUPPORTED;
+
+		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR (rv);
+		rv = phy_drv->phy_speed_get (dev_id, phy_id, pspeed);
+		SW_RTN_ON_ERROR (rv);
+	}
+#if 0
+  HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  SW_GET_FIELD_BY_REG (PORT_STATUS, SPEED_MODE, field, reg);
+  if (0 == field)
+    {
+      *pspeed = FAL_SPEED_10;
+    }
+  else if (1 == field)
+    {
+      *pspeed = FAL_SPEED_100;
+    }
+  else if (2 == field)
+    {
+      *pspeed = FAL_SPEED_1000;
+    }
+  else
+    {
+      *pspeed = FAL_SPEED_BUTT;
+      rv = SW_READ_ERROR;
+    }
+#endif
+
+	return rv;
+}
+
+static sw_error_t
+_dess_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * status)
+{
+  a_uint32_t phy_id;
+  sw_error_t rv;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_autoneg_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  *status = phy_drv->phy_autoneg_status_get (dev_id, phy_id);
+
+  return SW_OK;
+}
+
+static sw_error_t
+_dess_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_autoneg_enable_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_autoneg_enable_set (dev_id, phy_id);
+  return rv;
+}
+
+static sw_error_t
+_dess_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_restart_autoneg)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_restart_autoneg (dev_id, phy_id);
+  return rv;
+}
+
+static sw_error_t
+_dess_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id,
+			    a_uint32_t autoadv)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_autoneg_adv_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_autoneg_adv_set (dev_id, phy_id, autoadv);
+  SW_RTN_ON_ERROR (rv);
+
+  return SW_OK;
+}
+
+static sw_error_t
+_dess_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id,
+			    a_uint32_t * autoadv)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_autoneg_adv_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  *autoadv = 0;
+  rv = phy_drv->phy_autoneg_adv_get (dev_id, phy_id, autoadv);
+  SW_RTN_ON_ERROR (rv);
+
+  return SW_OK;
+}
+
+static sw_error_t
+_dess_port_flowctrl_set (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t enable)
+{
+  sw_error_t rv;
+  a_uint32_t val, force, reg = 0, tmp;
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  if (A_TRUE == enable)
+    {
+      val = 1;
+    }
+  else if (A_FALSE == enable)
+    {
+      val = 0;
+    }
+  else
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  SW_GET_FIELD_BY_REG (PORT_STATUS, FLOW_LINK_EN, force, reg);
+  if (force)
+    {
+      /* flow control isn't in force mode so can't set */
+      return SW_DISABLE;
+    }
+	tmp = reg;
+
+  SW_SET_REG_BY_FIELD (PORT_STATUS, RX_FLOW_EN, val, reg);
+  SW_SET_REG_BY_FIELD (PORT_STATUS, TX_FLOW_EN, val, reg);
+  SW_SET_REG_BY_FIELD (PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
+	if (reg == tmp)
+		return SW_OK;
+
+  HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  return rv;
+}
+
+static sw_error_t
+_dess_port_flowctrl_thresh_set (a_uint32_t dev_id, fal_port_t port_id,
+			 a_uint8_t on, a_uint8_t off)
+{
+	sw_error_t rv;
+	a_uint32_t reg = 0;
+
+	reg = (on << 16) | off;
+	HSL_REG_ENTRY_SET (rv, dev_id, PORT_FLOC_CTRL_THRESH, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+	return rv;
+}
+
+static sw_error_t
+_dess_port_flowctrl_get (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t rx, reg = 0;
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  SW_GET_FIELD_BY_REG (PORT_STATUS, RX_FLOW_EN, rx, reg);
+
+  if (1 == rx)
+    {
+      *enable = A_TRUE;
+    }
+  else
+    {
+      *enable = A_FALSE;
+    }
+
+  return SW_OK;
+}
+
+static sw_error_t
+_dess_port_flowctrl_forcemode_set (a_uint32_t dev_id, fal_port_t port_id,
+				   a_bool_t enable)
+{
+  sw_error_t rv;
+  a_uint32_t reg = 0, tmp;
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+	SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, tmp, reg);
+
+  if (A_TRUE == enable)
+    {
+		if (tmp== 0)
+			return SW_OK;
+      SW_SET_REG_BY_FIELD (PORT_STATUS, FLOW_LINK_EN, 0, reg);
+    }
+  else if (A_FALSE == enable)
+    {
+      /* for those ports without PHY, it can't sync flow control status */
+      if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
+	{
+	  return SW_DISABLE;
+	}
+	  if (tmp == 1)
+	  	return SW_OK;
+      SW_SET_REG_BY_FIELD (PORT_STATUS, FLOW_LINK_EN, 1, reg);
+    }
+  else
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  return rv;
+}
+
+static sw_error_t
+_dess_port_flowctrl_forcemode_get (a_uint32_t dev_id, fal_port_t port_id,
+				   a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t force, reg;
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  SW_GET_FIELD_BY_REG (PORT_STATUS, FLOW_LINK_EN, force, reg);
+  if (0 == force)
+    {
+      *enable = A_TRUE;
+    }
+  else
+    {
+      *enable = A_FALSE;
+    }
+
+  return SW_OK;
+}
+
+static sw_error_t
+_dess_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_powersave_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_powersave_set (dev_id, phy_id, enable);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_powersave_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_powersave_get (dev_id, phy_id, enable);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_hibernation_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_hibernation_set (dev_id, phy_id, enable);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_hibernation_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_hibernation_get (dev_id, phy_id, enable);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+		fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_cdt)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_cdt (dev_id, phy_id, mdi_pair, cable_status, cable_len);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_rxhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+			   fal_port_header_mode_t mode)
+{
+  sw_error_t rv;
+  a_uint32_t val = 0;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  if (FAL_NO_HEADER_EN == mode)
+    {
+      val = 0;
+    }
+  else if (FAL_ONLY_MANAGE_FRAME_EN == mode && port_id != 0)
+    {
+      val = 1;
+    }
+  else if (FAL_ALL_TYPE_FRAME_EN == mode)
+    {
+      val = 2;
+    }
+  else
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_FIELD_SET (rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  return rv;
+}
+
+static sw_error_t
+_dess_port_rxhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+			   fal_port_header_mode_t * mode)
+{
+  sw_error_t rv;
+  a_uint32_t val;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_FIELD_GET (rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  if (1 == val)
+    {
+      *mode = FAL_ONLY_MANAGE_FRAME_EN;
+    }
+  else if (2 == val)
+    {
+      *mode = FAL_ALL_TYPE_FRAME_EN;
+    }
+  else
+    {
+      *mode = FAL_NO_HEADER_EN;
+    }
+
+  return SW_OK;
+}
+
+static sw_error_t
+_dess_port_txhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+			   fal_port_header_mode_t mode)
+{
+  sw_error_t rv;
+  a_uint32_t val = 0;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  if (FAL_NO_HEADER_EN == mode)
+    {
+      val = 0;
+    }
+  else if (FAL_ONLY_MANAGE_FRAME_EN == mode)
+    {
+      val = 1;
+    }
+  else if (FAL_ALL_TYPE_FRAME_EN == mode)
+    {
+      val = 2;
+    }
+  else
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_FIELD_SET (rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  return rv;
+}
+
+static sw_error_t
+_dess_port_txhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+			   fal_port_header_mode_t * mode)
+{
+  sw_error_t rv;
+  a_uint32_t val = 0;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_FIELD_GET (rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  if (1 == val)
+    {
+      *mode = FAL_ONLY_MANAGE_FRAME_EN;
+    }
+  else if (2 == val)
+    {
+      *mode = FAL_ALL_TYPE_FRAME_EN;
+    }
+  else
+    {
+      *mode = FAL_NO_HEADER_EN;
+    }
+
+  return SW_OK;
+}
+
+static sw_error_t
+_dess_header_type_set (a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
+{
+  a_uint32_t reg = 0;
+  sw_error_t rv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  HSL_REG_ENTRY_GET (rv, dev_id, HEADER_CTL, 0,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  if (A_TRUE == enable)
+    {
+      if (0xffff < type)
+	{
+	  return SW_BAD_PARAM;
+	}
+      SW_SET_REG_BY_FIELD (HEADER_CTL, TYPE_LEN, 1, reg);
+      SW_SET_REG_BY_FIELD (HEADER_CTL, TYPE_VAL, type, reg);
+    }
+  else if (A_FALSE == enable)
+    {
+      SW_SET_REG_BY_FIELD (HEADER_CTL, TYPE_LEN, 0, reg);
+      SW_SET_REG_BY_FIELD (HEADER_CTL, TYPE_VAL, 0, reg);
+    }
+  else
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_ENTRY_SET (rv, dev_id, HEADER_CTL, 0,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  return rv;
+}
+
+static sw_error_t
+_dess_header_type_get (a_uint32_t dev_id, a_bool_t * enable,
+		       a_uint32_t * type)
+{
+  a_uint32_t data, reg = 0;
+  sw_error_t rv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  HSL_REG_ENTRY_GET (rv, dev_id, HEADER_CTL, 0,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  SW_GET_FIELD_BY_REG (HEADER_CTL, TYPE_LEN, data, reg);
+  if (data)
+    {
+      SW_GET_FIELD_BY_REG (HEADER_CTL, TYPE_VAL, data, reg);
+      *enable = A_TRUE;
+      *type = data;
+    }
+  else
+    {
+      *enable = A_FALSE;
+      *type = 0;
+    }
+
+  return SW_OK;
+}
+
+static sw_error_t
+_dess_port_txmac_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t enable)
+{
+  sw_error_t rv;
+  a_uint32_t reg, force, val = 0, tmp;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  if (A_TRUE == enable)
+    {
+      val = 1;
+    }
+  else if (A_FALSE == enable)
+    {
+      val = 0;
+    }
+  else
+    {
+      return SW_BAD_PARAM;
+    }
+	tmp = reg;
+
+  /* for those ports without PHY device we set MAC register */
+  if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
+    {
+      SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg);
+      SW_SET_REG_BY_FIELD (PORT_STATUS, TXMAC_EN, val, reg);
+    }
+  else
+    {
+      SW_GET_FIELD_BY_REG (PORT_STATUS, LINK_EN, force, reg);
+      if (force)
+	{
+	  /* link isn't in force mode so can't set */
+	  return SW_DISABLE;
+	}
+      else
+	{
+	  SW_SET_REG_BY_FIELD (PORT_STATUS, TXMAC_EN, val, reg);
+	}
+    }
+	if (tmp == reg)
+		return SW_OK;
+  HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  return rv;
+}
+
+static sw_error_t
+_dess_port_txmac_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t val = 0;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, TXMAC_EN,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  if (val)
+    {
+      *enable = A_TRUE;
+    }
+  else
+    {
+      *enable = A_FALSE;
+    }
+
+  return SW_OK;
+}
+
+static sw_error_t
+_dess_port_rxmac_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t enable)
+{
+  sw_error_t rv;
+  a_uint32_t reg = 0, force, val = 0, tmp = 0;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  if (A_TRUE == enable)
+    {
+      val = 1;
+    }
+  else if (A_FALSE == enable)
+    {
+      val = 0;
+    }
+  else
+    {
+      return SW_BAD_PARAM;
+    }
+	tmp = reg;
+
+  /* for those ports without PHY device we set MAC register */
+  if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
+    {
+      SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg);
+      SW_SET_REG_BY_FIELD (PORT_STATUS, RXMAC_EN, val, reg);
+    }
+  else
+    {
+      SW_GET_FIELD_BY_REG (PORT_STATUS, LINK_EN, force, reg);
+      if (force)
+	{
+	  /* link isn't in force mode so can't set */
+	  return SW_DISABLE;
+	}
+      else
+	{
+	  SW_SET_REG_BY_FIELD (PORT_STATUS, RXMAC_EN, val, reg);
+	}
+    }
+	if (tmp == reg)
+		return SW_OK;
+  HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  return rv;
+}
+
+static sw_error_t
+_dess_port_rxmac_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t val = 0;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, RXMAC_EN,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  if (val)
+    {
+      *enable = A_TRUE;
+    }
+  else
+    {
+      *enable = A_FALSE;
+    }
+
+  return SW_OK;
+}
+
+static sw_error_t
+_dess_port_txfc_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t enable)
+{
+  sw_error_t rv;
+  a_uint32_t val = 0, reg = 0, force, tmp;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  if (A_TRUE == enable)
+    {
+      val = 1;
+    }
+  else if (A_FALSE == enable)
+    {
+      val = 0;
+    }
+  else
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+	tmp = reg;
+
+  /* for those ports without PHY device we set MAC register */
+  if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
+    {
+      SW_SET_REG_BY_FIELD (PORT_STATUS, FLOW_LINK_EN, 0, reg);
+      SW_SET_REG_BY_FIELD (PORT_STATUS, TX_FLOW_EN, val, reg);
+    }
+  else
+    {
+      SW_GET_FIELD_BY_REG (PORT_STATUS, FLOW_LINK_EN, force, reg);
+      if (force)
+	{
+	  /* flow control isn't in force mode so can't set */
+	  return SW_DISABLE;
+	}
+      else
+	{
+	  SW_SET_REG_BY_FIELD (PORT_STATUS, TX_FLOW_EN, val, reg);
+	}
+    }
+	if (tmp == reg)
+		return SW_OK;
+  HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  return rv;
+}
+
+static sw_error_t
+_dess_port_txfc_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t val;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, TX_FLOW_EN,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  if (val)
+    {
+      *enable = A_TRUE;
+    }
+  else
+    {
+      *enable = A_FALSE;
+    }
+
+  return SW_OK;
+}
+
+static sw_error_t
+_dess_port_rxfc_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t enable)
+{
+  sw_error_t rv;
+  a_uint32_t val = 0, reg, force, tmp;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  if (A_TRUE == enable)
+    {
+      val = 1;
+    }
+  else if (A_FALSE == enable)
+    {
+      val = 0;
+    }
+  else
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+	tmp = reg;
+
+  /* for those ports without PHY device we set MAC register */
+  if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
+    {
+      SW_SET_REG_BY_FIELD (PORT_STATUS, FLOW_LINK_EN, 0, reg);
+      SW_SET_REG_BY_FIELD (PORT_STATUS, RX_FLOW_EN, val, reg);
+    }
+  else
+    {
+      SW_GET_FIELD_BY_REG (PORT_STATUS, FLOW_LINK_EN, force, reg);
+      if (force)
+	{
+	  /* flow control isn't in force mode so can't set */
+	  return SW_DISABLE;
+	}
+      else
+	{
+	  SW_SET_REG_BY_FIELD (PORT_STATUS, RX_FLOW_EN, val, reg);
+	}
+    }
+	if (tmp == reg)
+		return SW_OK;
+  HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  return rv;
+}
+
+static sw_error_t
+_dess_port_rxfc_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t val;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, RX_FLOW_EN,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  if (val)
+    {
+      *enable = A_TRUE;
+    }
+  else
+    {
+      *enable = A_FALSE;
+    }
+
+  return SW_OK;
+}
+
+static sw_error_t
+_dess_port_bp_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable)
+{
+  sw_error_t rv;
+  a_uint32_t val = 0, tmp = 0;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  if (A_TRUE == enable)
+    {
+      val = 1;
+    }
+  else if (A_FALSE == enable)
+    {
+      val = 0;
+    }
+  else
+    {
+      return SW_BAD_PARAM;
+    }
+	HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+		     (a_uint8_t *) (&tmp), sizeof (a_uint32_t));
+	if (tmp == val)
+		return SW_OK;
+
+  HSL_REG_FIELD_SET (rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  return rv;
+}
+
+static sw_error_t
+_dess_port_bp_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t val = 0;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  if (val)
+    {
+      *enable = A_TRUE;
+    }
+  else
+    {
+      *enable = A_FALSE;
+    }
+
+  return SW_OK;
+}
+
+static sw_error_t
+_dess_port_link_forcemode_set (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable)
+{
+  sw_error_t rv;
+  a_uint32_t reg = 0, tmp = 0;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+	SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, tmp, reg);
+
+  if (A_TRUE == enable)
+    {
+		if(tmp == 0)
+			return SW_OK;
+      SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg);
+    }
+  else if (A_FALSE == enable)
+    {
+		if(tmp == 1)
+			return SW_OK;
+      /* for those ports without PHY, it can't sync link status */
+      if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
+	{
+	  return SW_DISABLE;
+	}
+      SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 1, reg);
+    }
+  else
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
+		     (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+  return rv;
+}
+
+static sw_error_t
+_dess_port_link_forcemode_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t val = 0;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, LINK_EN,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  if (0 == val)
+    {
+      *enable = A_TRUE;
+    }
+  else
+    {
+      *enable = A_FALSE;
+    }
+
+  return SW_OK;
+}
+
+static sw_error_t
+_dess_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t * status)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+	{
+		return SW_BAD_PARAM;
+	}
+
+		/* for those ports without PHY device supposed always link up */
+	if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
+	{
+		*status = A_TRUE;
+	}
+	else
+	{
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+		if (NULL == phy_drv->phy_link_status_get)
+			return SW_NOT_SUPPORTED;
+
+		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR (rv);
+
+		if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id))
+		{
+			*status = A_TRUE;
+		}
+		else
+		{
+			*status = A_FALSE;
+		}
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+_dess_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status)
+{
+	sw_error_t rv;
+	a_uint32_t port_id;
+	a_uint32_t phy_id;
+	hsl_dev_t *pdev = NULL;
+	hsl_phy_ops_t *phy_drv;
+	a_uint32_t port_bmp[SW_MAX_NR_DEV] = {0};
+
+	HSL_DEV_ID_CHECK(dev_id);
+
+	pdev = hsl_dev_ptr_get(dev_id);
+	if (pdev == NULL)
+		return SW_NOT_INITIALIZED;
+
+	port_bmp[dev_id] = qca_ssdk_phy_type_port_bmp_get(dev_id, MALIBU_PHY_CHIP);
+
+	*status = 0x0;
+	for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+	{
+		if (port_id >= SW_MAX_NR_PORT)
+			break;
+		/* for those ports without PHY device supposed always link up */
+		if (A_FALSE == _dess_port_phy_connected(dev_id, port_id))
+		{
+			*status |= (0x1 << port_id);
+		}
+		else
+		{
+			if(port_bmp[dev_id] & (0x1 << port_id))
+			{
+				SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+				if (NULL == phy_drv->phy_link_status_get)
+					return SW_NOT_SUPPORTED;
+				rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+				SW_RTN_ON_ERROR(rv);
+
+				if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id))
+				{
+					*status |= (0x1 << port_id);
+				}
+				else
+				{
+					*status &= ~(0x1 << port_id);
+				}
+			}
+		}
+	}
+	return SW_OK;
+}
+
+static sw_error_t
+_dess_port_mac_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t enable)
+{
+  sw_error_t rv = SW_OK;
+  a_uint32_t val = 0;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  if (A_TRUE == enable)
+    {
+      val = 1;
+    }
+  else if (A_FALSE == enable)
+    {
+      val = 0;
+    }
+  else
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_FIELD_SET (rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  return rv;
+}
+
+static sw_error_t
+_dess_port_mac_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+			     a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t val = 0;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_FIELD_GET (rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  SW_RTN_ON_ERROR (rv);
+
+  if (0 == val)
+    {
+      *enable = A_FALSE;
+    }
+  else
+    {
+      *enable = A_TRUE;
+    }
+
+  return SW_OK;
+}
+
+
+static sw_error_t
+_dess_port_congestion_drop_set (a_uint32_t dev_id, fal_port_t port_id,
+				a_uint32_t queue_id, a_bool_t enable)
+{
+  sw_error_t rv = SW_OK;
+  a_uint32_t val = 0, offset = 0, field = 0;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  if (queue_id >= port_queue[port_id])
+    {
+      return SW_BAD_PARAM;
+    }
+
+  if (port_id != 0)
+    offset = port_id * 4 + 2;
+  offset += queue_id;
+
+  if (A_TRUE == enable)
+    {
+      field = 1 << offset;
+    }
+  else if (A_FALSE == enable)
+    {
+      field = ~(1 << offset);
+    }
+  else
+    {
+      return SW_BAD_PARAM;
+    }
+
+
+
+  HSL_REG_ENTRY_GET (rv, dev_id, FLOW_CONGE_DROP_CTRL0, 0,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  if (A_TRUE == enable)
+    {
+      val = val | field;
+    }
+  else
+    {
+      val = val & field;
+    }
+
+  HSL_REG_ENTRY_SET (rv, dev_id, FLOW_CONGE_DROP_CTRL0, 0,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  return rv;
+}
+
+
+static sw_error_t
+_dess_port_congestion_drop_get (a_uint32_t dev_id, fal_port_t port_id,
+				a_uint32_t queue_id, a_bool_t * enable)
+{
+  sw_error_t rv = SW_OK;
+  a_uint32_t val, offset = 0;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  if (queue_id >= port_queue[port_id])
+    {
+      return SW_BAD_PARAM;
+    }
+
+  if (port_id != 0)
+    offset = port_id * 4 + 2;
+  offset += queue_id;
+
+  HSL_REG_ENTRY_GET (rv, dev_id, FLOW_CONGE_DROP_CTRL0, 0,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+  val = (val >> offset) & 0x1;
+  if (val == 0)
+    {
+      *enable = A_FALSE;
+    }
+  else if (val == 1)
+    {
+      *enable = A_TRUE;
+    }
+  return rv;
+}
+
+static sw_error_t
+_dess_ring_flow_ctrl_thres_set (a_uint32_t dev_id, a_uint32_t ring_id,
+				a_uint8_t on_thres, a_uint8_t off_thres)
+{
+  sw_error_t rv;
+  a_uint32_t val = 0;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (ring_id >= DMA_MAX_VIRT_RING)
+    {
+      return SW_BAD_PARAM;
+    }
+
+  if (on_thres > off_thres || on_thres == 0)
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_SET_REG_BY_FIELD (RING_FLOW_CTRL_THRES, XON, on_thres, val);
+  SW_SET_REG_BY_FIELD (RING_FLOW_CTRL_THRES, XOFF, off_thres, val);
+  HSL_REG_ENTRY_SET (rv, dev_id, RING_FLOW_CTRL_THRES, ring_id,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+
+  return rv;
+}
+
+
+static sw_error_t
+_dess_ring_flow_ctrl_thres_get (a_uint32_t dev_id, a_uint32_t ring_id,
+				a_uint8_t * on_thres, a_uint8_t * off_thres)
+{
+
+  sw_error_t rv;
+  a_uint32_t val = 0;
+  a_uint8_t hthres, lthres;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (ring_id >= DMA_MAX_VIRT_RING)
+    {
+      return SW_BAD_PARAM;
+    }
+
+  HSL_REG_ENTRY_GET (rv, dev_id, RING_FLOW_CTRL_THRES, ring_id,
+		     (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+  SW_GET_FIELD_BY_REG (RING_FLOW_CTRL_THRES, XON, hthres, val);
+  SW_GET_FIELD_BY_REG (RING_FLOW_CTRL_THRES, XOFF, lthres, val);
+
+  *on_thres = hthres;
+  *off_thres = lthres;
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_8023az_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_8023az_set (dev_id, phy_id, enable);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id,
+		       a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_8023az_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_8023az_get (dev_id, phy_id, enable);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_mdix_set (a_uint32_t dev_id, fal_port_t port_id,
+		     fal_port_mdix_mode_t mode)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_mdix_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_mdix_set (dev_id, phy_id, mode);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id,
+		     fal_port_mdix_mode_t * mode)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_mdix_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_mdix_get (dev_id, phy_id, mode);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			    fal_port_mdix_status_t * mode)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_mdix_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_mdix_status_get (dev_id, phy_id, mode);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_combo_prefer_medium_set (a_uint32_t dev_id, fal_port_t port_id,
+				    fal_port_medium_t phy_medium)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_combo_prefer_medium_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_combo_prefer_medium_set (dev_id, phy_id, phy_medium);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_combo_prefer_medium_get (a_uint32_t dev_id, fal_port_t port_id,
+				    fal_port_medium_t * phy_medium)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_combo_prefer_medium_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_combo_prefer_medium_get (dev_id, phy_id, phy_medium);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_combo_medium_status_get (a_uint32_t dev_id, fal_port_t port_id,
+				    fal_port_medium_t * phy_medium)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_combo_medium_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_combo_medium_status_get (dev_id, phy_id, phy_medium);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_combo_fiber_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+				 fal_port_fiber_mode_t fiber_mode)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_combo_fiber_mode_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_combo_fiber_mode_set (dev_id, phy_id, fiber_mode);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_combo_fiber_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+				 fal_port_fiber_mode_t * fiber_mode)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_combo_fiber_mode_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_combo_fiber_mode_get (dev_id, phy_id, fiber_mode);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_local_loopback_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_local_loopback_set (dev_id, phy_id, enable);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_local_loopback_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_local_loopback_get (dev_id, phy_id, enable);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t enable)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_remote_loopback_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_remote_loopback_set (dev_id, phy_id, enable);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_remote_loopback_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_remote_loopback_get (dev_id, phy_id, enable);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_reset (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_reset)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_reset(dev_id, phy_id);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_power_off (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_power_off)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_power_off(dev_id, phy_id);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_power_on (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_power_on)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_power_on(dev_id, phy_id);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t enable)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_wol_status_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_wol_status_set (dev_id, phy_id, enable);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_wol_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_wol_status_get (dev_id, phy_id, enable);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id,
+				a_uint16_t * org_id, a_uint16_t * rev_id)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+  a_uint32_t phy_data;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_id_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_id_get (dev_id, phy_id, &phy_data);
+  SW_RTN_ON_ERROR (rv);
+
+  *org_id = (phy_data >> 16) & 0xffff;
+  *rev_id = phy_data & 0xffff;
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id,
+				fal_mac_addr_t * mac)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_magic_frame_mac_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_magic_frame_mac_set (dev_id, phy_id,mac);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id,
+				fal_mac_addr_t * mac)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_magic_frame_mac_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_magic_frame_mac_get (dev_id, phy_id,mac);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_interface_mode_t  mode)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_interface_mode_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_interface_mode_set (dev_id, phy_id,mode);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_interface_mode_t * mode)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_interface_mode_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_interface_mode_get (dev_id, phy_id,mode);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_interface_mode_t * mode)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_interface_mode_status_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_interface_mode_status_get (dev_id, phy_id,mode);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_counter_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_counter_set)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_counter_set (dev_id, phy_id, enable);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_counter_get (a_uint32_t dev_id, fal_port_t port_id,
+		       a_bool_t * enable)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_counter_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_counter_get (dev_id, phy_id, enable);
+
+  return rv;
+}
+
+static sw_error_t
+_dess_port_counter_show (a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_counter_info_t * counter_info)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_counter_show)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_counter_show (dev_id, phy_id,counter_info);
+
+  return rv;
+}
+
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id,
+		      fal_port_duplex_t duplex)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_duplex_set (dev_id, port_id, duplex);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id,
+		      fal_port_duplex_t * pduplex)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_duplex_get (dev_id, port_id, pduplex);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_speed_set (a_uint32_t dev_id, fal_port_t port_id,
+		     fal_port_speed_t speed)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_speed_set (dev_id, port_id, speed);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_speed_get (a_uint32_t dev_id, fal_port_t port_id,
+		     fal_port_speed_t * pspeed)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_speed_get (dev_id, port_id, pspeed);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * status)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_autoneg_status_get (dev_id, port_id, status);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_autoneg_enable (dev_id, port_id);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_autoneg_restart (dev_id, port_id);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ *   @details  Comments:
+ *   auto negotiation advtisement ability is defined by macro such as
+ *   FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id,
+			   a_uint32_t autoadv)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_autoneg_adv_set (dev_id, port_id, autoadv);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id,
+			   a_uint32_t * autoadv)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_autoneg_adv_get (dev_id, port_id, autoadv);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set flow control(rx/tx/bp) status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_flowctrl_set (a_uint32_t dev_id, fal_port_t port_id,
+			a_bool_t enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_flowctrl_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set flow control(rx/tx/bp) threshold on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] on on threshold
+ * @param[in] off off threshold
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_flowctrl_thresh_set (a_uint32_t dev_id, fal_port_t port_id,
+			a_uint8_t on, a_uint8_t off)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _dess_port_flowctrl_thresh_set (dev_id, port_id, on, off);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_flowctrl_get (a_uint32_t dev_id, fal_port_t port_id,
+			a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_flowctrl_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_flowctrl_forcemode_set (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_flowctrl_forcemode_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_flowctrl_forcemode_get (a_uint32_t dev_id, fal_port_t port_id,
+				  a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_flowctrl_forcemode_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_powersave_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_powersave_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_hibernate_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_hibernate_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Run cable diagnostic test on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mdi_pair mdi pair id
+ * @param[out] cable_status cable status
+ * @param[out] cable_len cable len
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+	       fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_cdt (dev_id, port_id, mdi_pair, cable_status, cable_len);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_rxhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+			  fal_port_header_mode_t mode)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_rxhdr_mode_set (dev_id, port_id, mode);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_rxhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+			  fal_port_header_mode_t * mode)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_rxhdr_mode_get (dev_id, port_id, mode);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_txhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+			  fal_port_header_mode_t mode)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_txhdr_mode_set (dev_id, port_id, mode);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_txhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+			  fal_port_header_mode_t * mode)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_txhdr_mode_get (dev_id, port_id, mode);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set status of Atheros header type value on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] type header type value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_header_type_set (a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_header_type_set (dev_id, enable, type);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get status of Atheros header type value on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] type header type value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_header_type_get (a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_header_type_get (dev_id, enable, type);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set status of txmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_txmac_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t enable)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_txmac_status_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get status of txmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_txmac_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_txmac_status_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set status of rxmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_rxmac_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t enable)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_rxmac_status_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get status of rxmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_rxmac_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_rxmac_status_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set status of tx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_txfc_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t enable)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_txfc_status_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get status of tx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_txfc_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_txfc_status_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set status of rx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_rxfc_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t enable)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_rxfc_status_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set status of rx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_rxfc_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_rxfc_status_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set status of back pressure on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_bp_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t enable)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_bp_status_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set status of back pressure on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_bp_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_bp_status_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_link_forcemode_set (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t enable)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_link_forcemode_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_link_forcemode_get (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_link_forcemode_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get link status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status link status up (A_TRUE) or down (A_FALSE)
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t * status)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_link_status_get (dev_id, port_id, status);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get link status on all ports.
+ * @param[in] dev_id device id
+ * @param[out] status link status bitmap and bit 0 for port 0, bi 1 for port 1, ..., etc.
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_ports_link_status_get(dev_id, status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set mac loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_mac_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t enable)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_mac_loopback_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get mac loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_mac_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_mac_loopback_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set flow congestion drop on a particular port queue.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_congestion_drop_set (a_uint32_t dev_id, fal_port_t port_id,
+			       a_uint32_t queue_id, a_bool_t enable)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_congestion_drop_set (dev_id, port_id, queue_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set flow congestion drop on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_congestion_drop_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_uint32_t queue_id, a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_congestion_drop_get (dev_id, port_id, queue_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set flow ctrl thres on a particular DMA ring.
+ * @param[in] dev_id device id
+ * @param[in] ring_id ring id
+ * @param[in] on_thres on_thres
+ * @param[in] off_thres off_thres
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ring_flow_ctrl_thres_set (a_uint32_t dev_id, a_uint32_t ring_id,
+			       a_uint8_t on_thres, a_uint8_t off_thres)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_ring_flow_ctrl_thres_set (dev_id, ring_id, on_thres, off_thres);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set flow ctrl thres on a particular DMA ring.
+ * @param[in] dev_id device id
+ * @param[in] ring_id ring id
+ * @param[out] on_thres on_thres
+ * @param[out] off_thres off_thres
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_ring_flow_ctrl_thres_get (a_uint32_t dev_id, a_uint32_t ring_id,
+			       a_uint8_t * on_thres, a_uint8_t * off_thres)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_ring_flow_ctrl_thres_get (dev_id, ring_id, on_thres, off_thres);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_8023az_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get 8023az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id,
+		      a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_8023az_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set mdix on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_mdix_set (a_uint32_t dev_id, a_uint32_t phy_id,
+		    fal_port_mdix_mode_t mode)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_mdix_set (dev_id, phy_id, mode);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get mdix configuration on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode 
+ * @return SW_OK or error code
+ */
+
+HSL_LOCAL sw_error_t
+dess_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id,
+		    fal_port_mdix_mode_t * mode)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_mdix_get (dev_id, port_id, mode);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get mdix status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode 
+ * @return SW_OK or error code
+ */
+
+HSL_LOCAL sw_error_t
+dess_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			   fal_port_mdix_status_t * mode)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_mdix_status_get (dev_id, port_id, mode);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set combo prefer medium on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] phy_medium [fiber or copper]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_combo_prefer_medium_set (a_uint32_t dev_id, a_uint32_t phy_id,
+				   fal_port_medium_t phy_medium)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_combo_prefer_medium_set (dev_id, phy_id, phy_medium);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get combo prefer medium on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] phy_medium [fiber or copper]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_combo_prefer_medium_get (a_uint32_t dev_id, a_uint32_t phy_id,
+				   fal_port_medium_t * phy_medium)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_combo_prefer_medium_get (dev_id, phy_id, phy_medium);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get current combo medium status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] phy_medium [fiber or copper]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_combo_medium_status_get (a_uint32_t dev_id, a_uint32_t phy_id,
+				   fal_port_medium_t * phy_medium)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_combo_medium_status_get (dev_id, phy_id, phy_medium);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set fiber mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] fiber mode [1000bx or 100fx]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_combo_fiber_mode_set (a_uint32_t dev_id, a_uint32_t phy_id,
+				fal_port_fiber_mode_t fiber_mode)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_combo_fiber_mode_set (dev_id, phy_id, fiber_mode);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get fiber mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] fiber mode [1000bx or 100fx]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_combo_fiber_mode_get (a_uint32_t dev_id, a_uint32_t phy_id,
+				fal_port_fiber_mode_t * fiber_mode)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_combo_fiber_mode_get (dev_id, phy_id, fiber_mode);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set phy local loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t enable)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_local_loopback_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get phy local loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_local_loopback_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set phy remote loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_remote_loopback_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get phy remote loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_remote_loopback_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief software reset on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_reset (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_reset (dev_id, port_id);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief phy power off on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_power_off (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_power_off (dev_id, port_id);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief phy power on on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_power_on (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_power_on (dev_id, port_id);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set phy wol enable on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_wol_status_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get phy wol status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_wol_status_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get phy id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] org_id and rev_id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_uint16_t * org_id, a_uint16_t * rev_id)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_phy_id_get (dev_id, port_id, org_id,rev_id);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set phy magic frame mac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mac address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_mac_addr_t * mac)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_magic_frame_mac_set (dev_id, port_id, mac);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get phy magic frame mac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mac address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_mac_addr_t * mac)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_magic_frame_mac_get (dev_id, port_id, mac);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+
+/**
+ * @brief Set phy interface mode.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] interface mode..
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t  mode)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_interface_mode_set (dev_id, port_id, mode);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set phy interface mode.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] interface mode..
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t  * mode)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_interface_mode_get (dev_id, port_id, mode);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set phy interface mode status.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] interface mode..
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t  * mode)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _dess_port_interface_mode_status_get (dev_id, port_id, mode);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set counter status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_counter_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_counter_set (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get counter status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_counter_get (a_uint32_t dev_id, fal_port_t port_id,
+		      a_bool_t * enable)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_counter_get (dev_id, port_id, enable);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get counter statistics  on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] frame counter statistics
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_counter_show(a_uint32_t dev_id, fal_port_t port_id,
+		      fal_port_counter_info_t * counter_info)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _dess_port_counter_show (dev_id, port_id, counter_info);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+sw_error_t
+dess_port_ctrl_init (a_uint32_t dev_id)
+{
+  HSL_DEV_ID_CHECK (dev_id);
+
+#ifndef HSL_STANDALONG
+  {
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id));
+
+    p_api->port_duplex_get = dess_port_duplex_get;
+    p_api->port_duplex_set = dess_port_duplex_set;
+    p_api->port_speed_get = dess_port_speed_get;
+    p_api->port_speed_set = dess_port_speed_set;
+    p_api->port_autoneg_status_get = dess_port_autoneg_status_get;
+    p_api->port_autoneg_enable = dess_port_autoneg_enable;
+    p_api->port_autoneg_restart = dess_port_autoneg_restart;
+    p_api->port_autoneg_adv_get = dess_port_autoneg_adv_get;
+    p_api->port_autoneg_adv_set = dess_port_autoneg_adv_set;
+    p_api->port_flowctrl_set = dess_port_flowctrl_set;
+    p_api->port_flowctrl_get = dess_port_flowctrl_get;
+	p_api->port_flowctrl_thresh_set = dess_port_flowctrl_thresh_set;
+    p_api->port_flowctrl_forcemode_set = dess_port_flowctrl_forcemode_set;
+    p_api->port_flowctrl_forcemode_get = dess_port_flowctrl_forcemode_get;
+    p_api->port_powersave_set = dess_port_powersave_set;
+    p_api->port_powersave_get = dess_port_powersave_get;
+    p_api->port_hibernate_set = dess_port_hibernate_set;
+    p_api->port_hibernate_get = dess_port_hibernate_get;
+    p_api->port_cdt = dess_port_cdt;
+    p_api->port_rxhdr_mode_set = dess_port_rxhdr_mode_set;
+    p_api->port_rxhdr_mode_get = dess_port_rxhdr_mode_get;
+    p_api->port_txhdr_mode_set = dess_port_txhdr_mode_set;
+    p_api->port_txhdr_mode_get = dess_port_txhdr_mode_get;
+    p_api->header_type_set = dess_header_type_set;
+    p_api->header_type_get = dess_header_type_get;
+    p_api->port_txmac_status_set = dess_port_txmac_status_set;
+    p_api->port_txmac_status_get = dess_port_txmac_status_get;
+    p_api->port_rxmac_status_set = dess_port_rxmac_status_set;
+    p_api->port_rxmac_status_get = dess_port_rxmac_status_get;
+    p_api->port_txfc_status_set = dess_port_txfc_status_set;
+    p_api->port_txfc_status_get = dess_port_txfc_status_get;
+    p_api->port_rxfc_status_set = dess_port_rxfc_status_set;
+    p_api->port_rxfc_status_get = dess_port_rxfc_status_get;
+    p_api->port_bp_status_set = dess_port_bp_status_set;
+    p_api->port_bp_status_get = dess_port_bp_status_get;
+    p_api->port_link_forcemode_set = dess_port_link_forcemode_set;
+    p_api->port_link_forcemode_get = dess_port_link_forcemode_get;
+    p_api->port_link_status_get = dess_port_link_status_get;
+    p_api->ports_link_status_get = dess_ports_link_status_get;
+    p_api->port_mac_loopback_set = dess_port_mac_loopback_set;
+    p_api->port_mac_loopback_get = dess_port_mac_loopback_get;
+    p_api->port_congestion_drop_set = dess_port_congestion_drop_set;
+    p_api->port_congestion_drop_get = dess_port_congestion_drop_get;
+    p_api->ring_flow_ctrl_thres_set = dess_ring_flow_ctrl_thres_set;
+    p_api->ring_flow_ctrl_thres_get = dess_ring_flow_ctrl_thres_get;
+    p_api->port_8023az_set = dess_port_8023az_set;
+    p_api->port_8023az_get = dess_port_8023az_get;
+    p_api->port_mdix_set = dess_port_mdix_set;
+    p_api->port_mdix_get = dess_port_mdix_get;
+    p_api->port_mdix_status_get = dess_port_mdix_status_get;
+    p_api->port_combo_prefer_medium_set = dess_port_combo_prefer_medium_set;
+    p_api->port_combo_prefer_medium_get = dess_port_combo_prefer_medium_get;
+    p_api->port_combo_medium_status_get = dess_port_combo_medium_status_get;
+    p_api->port_combo_fiber_mode_set = dess_port_combo_fiber_mode_set;
+    p_api->port_combo_fiber_mode_get = dess_port_combo_fiber_mode_get;
+    p_api->port_local_loopback_set = dess_port_local_loopback_set;
+    p_api->port_local_loopback_get = dess_port_local_loopback_get;
+    p_api->port_remote_loopback_set = dess_port_remote_loopback_set;
+    p_api->port_remote_loopback_get = dess_port_remote_loopback_get;
+    p_api->port_reset = dess_port_reset;
+    p_api->port_power_off = dess_port_power_off;
+    p_api->port_power_on = dess_port_power_on;
+    p_api->port_phy_id_get = dess_port_phy_id_get;
+    p_api->port_wol_status_set = dess_port_wol_status_set;
+    p_api->port_wol_status_get = dess_port_wol_status_get;
+    p_api->port_magic_frame_mac_set = dess_port_magic_frame_mac_set;
+    p_api->port_magic_frame_mac_get = dess_port_magic_frame_mac_get;
+    p_api->port_interface_mode_set = dess_port_interface_mode_set;
+    p_api->port_interface_mode_get = dess_port_interface_mode_get;
+    p_api->port_interface_mode_status_get = dess_port_interface_mode_status_get;
+    p_api->port_counter_set = dess_port_counter_set;
+    p_api->port_counter_get = dess_port_counter_get;
+    p_api->port_counter_show = dess_port_counter_show;
+  }
+#endif
+
+  return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/dess/dess_portvlan.c b/qca-ssdk/src/hsl/dess/dess_portvlan.c
new file mode 100755
index 0000000..bab6228
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_portvlan.c
@@ -0,0 +1,2336 @@
+/*
+ * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_port_vlan DESS_PORT_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_portvlan.h"
+#include "dess_reg.h"
+
+#define MAX_VLAN_ID          4095
+#define DESS_MAX_VLAN_TRANS  64
+#define DESS_VLAN_TRANS_ADDR 0x5ac00
+
+
+static sw_error_t
+_dess_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, reg = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      COREP_EN, (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                          DEF_SVID, (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                          DEF_CVID, (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_DEFV, (port_id / 2),
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (port_id % 2)
+    {
+        reg &= 0xffff;
+        reg |= ((data & 0xfff) << 16);
+    }
+    else
+    {
+        reg &= 0xffff0000;
+        reg |= (data & 0xfff);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_DEFV, (port_id / 2),
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+    a_uint32_t data, regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_1Q_MODE_BUTT <= port_1qmode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE,
+                      (a_uint8_t *) (&regval[port_1qmode]),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_1Q_DISABLE == port_1qmode)
+    {
+        data = 1;
+    }
+    else
+    {
+        data = 0;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, VLAN_DIS,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK,
+                                  FAL_1Q_CHECK, FAL_1Q_SECURE
+                                };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(pport_1qmode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    *pport_1qmode = retval[regval & 0x3];
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3, 3 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((FAL_EG_MODE_BUTT <= port_egvlanmode)
+            || (FAL_EG_HYBRID == port_egvlanmode))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE,
+                      (a_uint8_t *) (&regval[port_egvlanmode]),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    return rv;
+}
+
+static sw_error_t
+_dess_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_1q_egmode_t retval[4] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED,
+                                     FAL_EG_TAGGED, FAL_EG_UNTOUCHED
+                                   };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(pport_egvlanmode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    *pport_egvlanmode = retval[regval & 0x3];
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    regval |= (0x1UL << mem_port_id);
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_dess_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    regval &= (~(0x1UL << mem_port_id));
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_dess_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&mem_port_map),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_dess_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    *mem_port_map = 0;
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) mem_port_map,
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    val = tpid;
+    HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+                      TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+                      TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *tpid = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_invlan_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t regval[FAL_INVLAN_MODE_BUTT] = { 0, 1, 2 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_INVLAN_MODE_BUTT <= mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE,
+                      (a_uint8_t *) (&regval[mode]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_invlan_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_invlan_mode_t retval[FAL_INVLAN_MODE_BUTT] = { FAL_INVLAN_ADMIT_ALL,
+            FAL_INVLAN_ADMIT_TAGGED, FAL_INVLAN_ADMIT_UNTAGGED
+                                                        };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(mode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (regval >= 3)
+    {
+        return SW_FAIL;
+    }
+    *mode = retval[regval & 0x3];
+
+    return rv;
+}
+
+static sw_error_t
+_dess_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      PRI_PROPAGATION, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      PRI_PROPAGATION, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t vid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (vid > MAX_VLAN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = vid;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_port_route_defv_set(dev_id, port_id);
+    return rv;
+}
+
+static sw_error_t
+_dess_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * vid)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    *vid = val & 0xfff;
+    return rv;
+}
+
+static sw_error_t
+_dess_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t vid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (vid > MAX_VLAN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = vid;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_port_route_defv_set(dev_id, port_id);
+    return rv;
+}
+
+static sw_error_t
+_dess_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * vid)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    *vid = val & 0xfff;
+    return rv;
+}
+
+static sw_error_t
+_dess_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_vlan_propagation_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, p, c;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_VLAN_PROPAGATION_DISABLE == mode)
+    {
+        p = 0;
+        c = 0;
+    }
+    else if (FAL_VLAN_PROPAGATION_CLONE == mode)
+    {
+        p = 1;
+        c = 1;
+    }
+    else if (FAL_VLAN_PROPAGATION_REPLACE == mode)
+    {
+        p = 1;
+        c = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT_VLAN1, PROPAGATION_EN, p, reg);
+    SW_SET_REG_BY_FIELD(PORT_VLAN1, CLONE, c, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_vlan_propagation_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, p, c;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_VLAN1, PROPAGATION_EN, p, reg);
+    SW_GET_FIELD_BY_REG(PORT_VLAN1, CLONE, c, reg);
+
+    if (p)
+    {
+        if (c)
+        {
+            *mode = FAL_VLAN_PROPAGATION_CLONE;
+        }
+        else
+        {
+            *mode = FAL_VLAN_PROPAGATION_REPLACE;
+        }
+    }
+    else
+    {
+        *mode = FAL_VLAN_PROPAGATION_DISABLE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_vlan_trans_read(a_uint32_t dev_id, a_uint32_t entry_idx,
+                      fal_pbmp_t * pbmp, fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, addr, dir, table[2] = {0};
+
+    *pbmp = 0;
+    aos_mem_zero(entry, sizeof (fal_vlan_trans_entry_t));
+
+    addr = DESS_VLAN_TRANS_ADDR + (entry_idx << 3);
+    /* get vlan trans table */
+    for (i = 0; i < 2; i++)
+    {
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    dir = 0x3 & (table[1] >> 4);
+    if (!dir)
+    {
+        return SW_EMPTY;
+    }
+
+    entry->o_vid = table[0] & 0xfff;
+    *pbmp = (table[1] >> 6) & 0x7f;
+
+    if (3 == dir)
+    {
+        entry->bi_dir = A_TRUE;
+        entry->forward_dir = A_TRUE;
+        entry->reverse_dir = A_TRUE;
+    }
+    else if (1 == dir)
+    {
+        entry->bi_dir = A_FALSE;
+        entry->forward_dir = A_TRUE;
+        entry->reverse_dir = A_FALSE;
+    }
+    else
+    {
+        entry->bi_dir = A_FALSE;
+        entry->forward_dir = A_FALSE;
+        entry->reverse_dir = A_TRUE;
+    }
+
+    entry->o_vid_is_cvid = (table[1] >> 13) & 0x1UL;
+    entry->one_2_one_vlan = (table[1] >> 16) & 0x1UL;
+    entry->s_vid_enable = (table[1] >> 14) & 0x1UL;
+    entry->c_vid_enable = (table[1] >> 15) & 0x1UL;
+
+    if (A_TRUE == entry->s_vid_enable)
+    {
+        entry->s_vid = (table[0] >> 12) & 0xfff;
+    }
+
+    if (A_TRUE == entry->c_vid_enable)
+    {
+        entry->c_vid = ((table[0] >> 24) & 0xff) | ((table[1] & 0xf) << 8);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_vlan_trans_write(a_uint32_t dev_id, a_uint32_t entry_idx, fal_pbmp_t pbmp,
+                       fal_vlan_trans_entry_t entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, addr, table[2] = { 0 };
+
+    addr = DESS_VLAN_TRANS_ADDR + (entry_idx << 3);
+
+    if (0 != pbmp)
+    {
+        table[0] = entry.o_vid & 0xfff;
+        table[0] |= ((entry.s_vid & 0xfff) << 12);
+        table[0] |= ((entry.c_vid & 0xff) << 24);
+        table[1] = (entry.c_vid >> 8) & 0xf;
+
+        if (A_TRUE == entry.bi_dir)
+        {
+            table[1] |= (0x3 << 4);
+        }
+
+        if (A_TRUE == entry.forward_dir)
+        {
+            table[1] |= (0x1 << 4);
+        }
+
+        if (A_TRUE == entry.reverse_dir)
+        {
+            table[1] |= (0x1 << 5);
+        }
+
+        table[1] |= (pbmp << 6);
+        table[1] |= ((0x1UL & entry.o_vid_is_cvid) << 13);
+        table[1] |= ((0x1UL & entry.s_vid_enable) << 14);
+        table[1] |= ((0x1UL & entry.c_vid_enable) << 15);
+        table[1] |= ((0x1UL & entry.one_2_one_vlan) << 16);
+    }
+
+    /* set vlan trans table */
+    for (i = 0; i < 2; i++)
+    {
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_vlan_trans_convert(fal_vlan_trans_entry_t * entry,
+                              fal_vlan_trans_entry_t * local)
+{
+    aos_mem_copy(local, entry, sizeof (fal_vlan_trans_entry_t));
+
+    if ((A_TRUE == local->bi_dir)
+            || ((A_TRUE == local->forward_dir)
+                && (A_TRUE == local->reverse_dir)))
+    {
+        local->bi_dir = A_TRUE;
+        local->forward_dir = A_TRUE;
+        local->reverse_dir = A_TRUE;
+    }
+
+    if (A_FALSE == local->s_vid_enable)
+    {
+        local->s_vid = 0;
+    }
+
+    if (A_FALSE == local->c_vid_enable)
+    {
+        local->c_vid = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+    fal_pbmp_t t_pbmp;
+    a_uint32_t idx, entry_idx = DESS_MAX_VLAN_TRANS;
+    fal_vlan_trans_entry_t temp, local;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (NULL == entry)
+    {
+        return SW_BAD_PTR;
+    }
+    aos_mem_zero(&local, sizeof (fal_vlan_trans_entry_t));
+    rv = _dess_port_vlan_trans_convert(entry, &local);
+    SW_RTN_ON_ERROR(rv);
+
+    for (idx = 0; idx < DESS_MAX_VLAN_TRANS; idx++)
+    {
+        rv = _dess_vlan_trans_read(dev_id, idx, &t_pbmp, &temp);
+        if (SW_EMPTY == rv)
+        {
+            entry_idx = idx;
+            continue;
+        }
+        SW_RTN_ON_ERROR(rv);
+
+        if (!aos_mem_cmp(&local, &temp, sizeof (fal_vlan_trans_entry_t)))
+        {
+            if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+            {
+                return SW_ALREADY_EXIST;
+            }
+            entry_idx = idx;
+            break;
+        }
+        else
+        {
+            t_pbmp = 0;
+        }
+    }
+
+    if (DESS_MAX_VLAN_TRANS != entry_idx)
+    {
+        t_pbmp |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    return _dess_vlan_trans_write(dev_id, entry_idx, t_pbmp, local);
+}
+
+static sw_error_t
+_dess_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+    fal_pbmp_t t_pbmp;
+    a_uint32_t idx, entry_idx = DESS_MAX_VLAN_TRANS;
+    fal_vlan_trans_entry_t temp, local;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (NULL == entry)
+    {
+        return SW_BAD_PTR;
+    }
+    aos_mem_zero(&local, sizeof (fal_vlan_trans_entry_t));
+    rv = _dess_port_vlan_trans_convert(entry, &local);
+    SW_RTN_ON_ERROR(rv);
+
+    for (idx = 0; idx < DESS_MAX_VLAN_TRANS; idx++)
+    {
+        rv = _dess_vlan_trans_read(dev_id, idx, &t_pbmp, &temp);
+        if (SW_EMPTY == rv)
+        {
+            continue;
+        }
+        SW_RTN_ON_ERROR(rv);
+
+        if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t)))
+        {
+            if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+            {
+                entry_idx = idx;
+                break;
+            }
+        }
+    }
+
+    if (DESS_MAX_VLAN_TRANS != entry_idx)
+    {
+        t_pbmp &= (~(0x1 << port_id));
+    }
+    else
+    {
+        return SW_NOT_FOUND;
+    }
+
+    return _dess_vlan_trans_write(dev_id, entry_idx, t_pbmp, local);
+}
+
+static sw_error_t
+_dess_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+    fal_pbmp_t t_pbmp;
+    a_uint32_t idx;
+    fal_vlan_trans_entry_t temp, local;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (NULL == entry)
+    {
+        return SW_BAD_PTR;
+    }
+    aos_mem_zero(&local, sizeof (fal_vlan_trans_entry_t));
+    rv = _dess_port_vlan_trans_convert(entry, &local);
+    SW_RTN_ON_ERROR(rv);
+
+    for (idx = 0; idx < DESS_MAX_VLAN_TRANS; idx++)
+    {
+        rv = _dess_vlan_trans_read(dev_id, idx, &t_pbmp, &temp);
+        if (SW_EMPTY == rv)
+        {
+            continue;
+        }
+        SW_RTN_ON_ERROR(rv);
+
+        if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t)))
+        {
+            if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+            {
+                return SW_OK;
+            }
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_dess_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * iterator,
+                              fal_vlan_trans_entry_t * entry)
+{
+    a_uint32_t index;
+    sw_error_t rv;
+    fal_vlan_trans_entry_t entry_t;
+    fal_pbmp_t pbmp_t;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((NULL == iterator) || (NULL == entry))
+    {
+        return SW_BAD_PTR;
+    }
+
+    if (DESS_MAX_VLAN_TRANS < *iterator)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (index = *iterator; index < DESS_MAX_VLAN_TRANS; index++)
+    {
+        rv = _dess_vlan_trans_read(dev_id, index, &pbmp_t, &entry_t);
+        if (SW_EMPTY == rv)
+        {
+            continue;
+        }
+
+        if (SW_IS_PBMP_MEMBER(pbmp_t, port_id))
+        {
+            aos_mem_copy(entry, &entry_t, sizeof (fal_vlan_trans_entry_t));
+            break;
+        }
+    }
+
+    if (DESS_MAX_VLAN_TRANS == index)
+    {
+        return SW_NO_MORE;
+    }
+
+    *iterator = index + 1;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t stag = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_QINQ_MODE_BUTT <= mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QINQ_STAG_MODE == mode)
+    {
+        stag = 1;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+                      STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_dess_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t stag = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+                      STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (stag)
+    {
+        *mode = FAL_QINQ_STAG_MODE;
+    }
+    else
+    {
+        *mode = FAL_QINQ_CTAG_MODE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_qinq_port_role_t role)
+{
+    sw_error_t rv;
+    a_uint32_t core = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QINQ_PORT_ROLE_BUTT <= role)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QINQ_CORE_PORT == role)
+    {
+        core = 1;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_port_route_defv_set(dev_id, port_id);
+    return rv;
+}
+
+static sw_error_t
+_dess_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_qinq_port_role_t * role)
+{
+    sw_error_t rv;
+    a_uint32_t core = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (core)
+    {
+        *role = FAL_QINQ_CORE_PORT;
+    }
+    else
+    {
+        *role = FAL_QINQ_EDGE_PORT;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id,
+                      EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+
+}
+
+static sw_error_t
+_dess_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id,
+                      EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_netisolate_set(a_uint32_t dev_id, a_uint32_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    val = enable;
+    HSL_REG_FIELD_SET(rv, dev_id, VLAN_TRANS, 0,
+                      NET_ISO, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_netisolate_get(a_uint32_t dev_id, a_uint32_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TRANS, 0,
+                      NET_ISO, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *enable = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_uint32_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    val = enable;
+    HSL_REG_FIELD_SET(rv, dev_id, VLAN_TRANS, 0,
+                      EG_FLTR_BYPASS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_uint32_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TRANS, 0,
+                      EG_FLTR_BYPASS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *enable = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_port_vrf_id_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t vrf_id)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      VRF_ID, (a_uint8_t *) (&vrf_id),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    return rv;
+}
+
+static sw_error_t
+_dess_port_vrf_id_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * vrf_id)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      VRF_ID, (a_uint8_t *) (vrf_id),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    return rv;
+}
+
+
+/**
+ * @brief Set 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_1qmode_set(dev_id, port_id, port_1qmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_1qmode_get(dev_id, port_id, pport_1qmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_portvlan_member_add(dev_id, port_id, mem_port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_portvlan_member_del(dev_id, port_id, mem_port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Update member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_portvlan_member_update(dev_id, port_id, mem_port_map);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_portvlan_member_get(dev_id, port_id, mem_port_map);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_force_default_vid_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_force_default_vid_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_force_portvlan_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_force_portvlan_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nestvlan_tpid_set(dev_id, tpid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_nestvlan_tpid_get(dev_id, tpid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_invlan_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_invlan_mode_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_invlan_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_invlan_mode_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_tls_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_tls_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_pri_propagation_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_pri_propagation_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid s-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_default_svid_set(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid s-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_default_svid_get(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid c-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_default_cvid_set(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid c-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_default_cvid_get(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_vlan_propagation_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_vlan_propagation_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_vlan_propagation_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_vlan_propagation_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a vlan translation entry to a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_vlan_trans_add(dev_id, port_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_vlan_trans_del(dev_id, port_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_vlan_trans_get(dev_id, port_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Iterate all vlan translation entries from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] iterator translation entry index if it's zero means get the first entry
+ * @param[out] iterator next valid translation entry index
+ * @param[out] entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * iterator,
+                             fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_vlan_trans_iterate(dev_id, port_id, iterator, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qinq_mode_set(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qinq_mode_get(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qinq_port_role_t role)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_qinq_role_set(dev_id, port_id, role);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qinq_port_role_t * role)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_qinq_role_get(dev_id, port_id, role);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set MAC_VLAN_XLT status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_mac_vlan_xlt_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get MAC_VLAN_XLT status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_mac_vlan_xlt_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#if 0
+HSL_LOCAL sw_error_t
+dess_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv =_dess_port_route_defv_set(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set NET_ISOLATE_EN
+ * @param[in] dev_id device id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_netisolate_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_netisolate_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get NET_ISOLATE_EN status
+ * @param[in] dev_id device id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_netisolate_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_netisolate_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress translation filter bypass enable
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_eg_trans_filter_bypass_en_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress translation filter bypass enable
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_eg_trans_filter_bypass_en_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set VRF id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vrf_id VRF id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_vrf_id_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t vrf_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_vrf_id_set(dev_id, port_id, vrf_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get VRF id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vrf_id VRF id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_port_vrf_id_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * vrf_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_port_vrf_id_get(dev_id, port_id, vrf_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+dess_portvlan_init(a_uint32_t dev_id)
+{
+    a_uint32_t i;
+    sw_error_t rv;
+    fal_vlan_trans_entry_t entry_init;
+    hsl_api_t *p_api;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    aos_mem_set(&entry_init, 0, sizeof (fal_vlan_trans_entry_t));
+
+    for (i = 0; i < DESS_MAX_VLAN_TRANS; i++)
+    {
+        rv = _dess_vlan_trans_write(dev_id, i, 0, entry_init);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+#ifndef HSL_STANDALONG
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->port_1qmode_get = dess_port_1qmode_get;
+    p_api->port_1qmode_set = dess_port_1qmode_set;
+    p_api->port_egvlanmode_get = dess_port_egvlanmode_get;
+    p_api->port_egvlanmode_set = dess_port_egvlanmode_set;
+    p_api->portvlan_member_add = dess_portvlan_member_add;
+    p_api->portvlan_member_del = dess_portvlan_member_del;
+    p_api->portvlan_member_update = dess_portvlan_member_update;
+    p_api->portvlan_member_get = dess_portvlan_member_get;
+    p_api->port_force_default_vid_set = dess_port_force_default_vid_set;
+    p_api->port_force_default_vid_get = dess_port_force_default_vid_get;
+    p_api->port_force_portvlan_set = dess_port_force_portvlan_set;
+    p_api->port_force_portvlan_get = dess_port_force_portvlan_get;
+    p_api->nestvlan_tpid_set = dess_nestvlan_tpid_set;
+    p_api->nestvlan_tpid_get = dess_nestvlan_tpid_get;
+    p_api->port_invlan_mode_set = dess_port_invlan_mode_set;
+    p_api->port_invlan_mode_get = dess_port_invlan_mode_get;
+    p_api->port_tls_set = dess_port_tls_set;
+    p_api->port_tls_get = dess_port_tls_get;
+    p_api->port_pri_propagation_set = dess_port_pri_propagation_set;
+    p_api->port_pri_propagation_get = dess_port_pri_propagation_get;
+    p_api->port_default_svid_set = dess_port_default_svid_set;
+    p_api->port_default_svid_get = dess_port_default_svid_get;
+    p_api->port_default_cvid_set = dess_port_default_cvid_set;
+    p_api->port_default_cvid_get = dess_port_default_cvid_get;
+    p_api->port_vlan_propagation_set = dess_port_vlan_propagation_set;
+    p_api->port_vlan_propagation_get = dess_port_vlan_propagation_get;
+    p_api->port_vlan_trans_add = dess_port_vlan_trans_add;
+    p_api->port_vlan_trans_del = dess_port_vlan_trans_del;
+    p_api->port_vlan_trans_get = dess_port_vlan_trans_get;
+    p_api->qinq_mode_set = dess_qinq_mode_set;
+    p_api->qinq_mode_get = dess_qinq_mode_get;
+    p_api->port_qinq_role_set = dess_port_qinq_role_set;
+    p_api->port_qinq_role_get = dess_port_qinq_role_get;
+    p_api->port_vlan_trans_iterate = dess_port_vlan_trans_iterate;
+    p_api->port_mac_vlan_xlt_set = dess_port_mac_vlan_xlt_set;
+    p_api->port_mac_vlan_xlt_get = dess_port_mac_vlan_xlt_get;
+    p_api->netisolate_set = dess_netisolate_set;
+    p_api->netisolate_get = dess_netisolate_get;
+    p_api->eg_trans_filter_bypass_en_set = dess_eg_trans_filter_bypass_en_set;
+    p_api->eg_trans_filter_bypass_en_get = dess_eg_trans_filter_bypass_en_get;
+    p_api->port_vrf_id_set = dess_port_vrf_id_set;
+    p_api->port_vrf_id_get = dess_port_vrf_id_get;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/dess/dess_psgmii.c b/qca-ssdk/src/hsl/dess/dess_psgmii.c
new file mode 100755
index 0000000..aab36d2
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_psgmii.c
@@ -0,0 +1,722 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#include "sw.h"
+#include "fal_port_ctrl.h"
+#include "hsl_api.h"
+#include "hsl.h"
+#include "sd.h"
+#include "dess_psgmii.h"
+#include "aos_timer.h"
+
+static psgmii_interface_mac_mode_t psgmii_mac_mode = {0};
+static a_uint32_t sgmii_ch_id = 0;
+
+sw_error_t
+dess_psgmii_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+             a_uint32_t value_len)
+{
+    sw_error_t rv;
+
+    rv = sd_reg_psgmii_get(dev_id, reg_addr, value, value_len);
+    return rv;
+}
+
+sw_error_t
+dess_psgmii_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+             a_uint32_t value_len)
+{
+    sw_error_t rv;
+
+    rv = sd_reg_psgmii_set(dev_id, reg_addr, value, value_len);
+    return rv;
+}
+
+sw_error_t
+dess_psgmii_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint32_t bit_offset, a_uint32_t field_len,
+                   a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val = 0;
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(dess_psgmii_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+
+    if(32 == field_len)
+    {
+        *((a_uint32_t *) value) = reg_val;
+    }
+    else
+    {
+        *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len);
+    }
+    return SW_OK;
+}
+
+sw_error_t
+dess_psgmii_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint32_t bit_offset, a_uint32_t field_len,
+                   const a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val = 0;
+    a_uint32_t field_val = *((a_uint32_t *) value);
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(dess_psgmii_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    if(32 == field_len)
+    {
+        reg_val = field_val;
+    }
+    else
+    {
+        SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len);
+    }
+
+    SW_RTN_ON_ERROR(dess_psgmii_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    return SW_OK;
+}
+
+
+/******************************************************************************
+*
+* psgmii_set_powersave - set power saving status
+*
+* set power saving status
+*/
+sw_error_t
+dess_psgmii_set_lpi(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (phy_id == 0)
+    {
+        rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_EEE_CH0_5,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_EEE_CH1_1 + phy_id * 0xc,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    if (enable)
+    {
+		data &= ~(PSGMIIPHY_EEE_DIS_LPI);
+		data |= PSGMIIPHY_EEE_EN_LPI;
+    }
+    else
+    {
+		data |= PSGMIIPHY_EEE_DIS_LPI;
+		data &= ~(PSGMIIPHY_EEE_EN_LPI);
+    }
+
+    if (phy_id == 0)
+    {
+        rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_EEE_CH0_5,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_EEE_CH1_1 + phy_id * 0xc,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+*psgmii_get_powersave - get power saving status
+*
+* set power saving status
+*/
+sw_error_t
+dess_psgmii_get_lpi(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (phy_id == 0)
+    {
+        rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_EEE_CH0_5,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_EEE_CH1_1 + phy_id * 0xc,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    if (!(data & PSGMIIPHY_EEE_DIS_LPI) && (data & PSGMIIPHY_EEE_EN_LPI))
+    {
+		*enable = A_TRUE;
+    }
+    else
+    {
+		*enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+*psgmii_set_hibernate - set hibernate status
+*
+* set hibernate status
+*/
+sw_error_t
+dess_psgmii_set_interface_type(a_uint32_t dev_id, a_uint32_t phy_id,
+								psgmii_interface_mac_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_MODE_CONTROL,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    switch(mode)
+    {
+		case PSGMII_MAC_MODE_PSGMII:
+		{
+			data |= PSGMIIPHY_MODE_CH0_PSGMII_QSGMII;
+			data &= (~PSGMIIPHY_MODE_CH0_QSGMII_SGMII);
+			data &= (~PSGMIIPHY_MODE_CH4_CH1_0_SGMII);
+			data &= (~PSGMIIPHY_MODE_CH1_CH0_SGMII);
+			break;
+		}
+		case PSGMII_MAC_MODE_QSGMII:
+		{
+			data &= (~PSGMIIPHY_MODE_CH0_PSGMII_QSGMII);
+			data |= PSGMIIPHY_MODE_CH0_QSGMII_SGMII;
+			if (phy_id == 0)
+			{
+				data &= (~PSGMIIPHY_MODE_CH4_CH1_0_SGMII);
+				data &= (~PSGMIIPHY_MODE_CH1_CH0_SGMII);
+			}
+			else if (phy_id == 1)
+			{
+				data &= (~PSGMIIPHY_MODE_CH4_CH1_0_SGMII);
+				data |= PSGMIIPHY_MODE_CH1_CH0_SGMII;
+			}
+			else if (phy_id == 4)
+			{
+				data |= PSGMIIPHY_MODE_CH4_CH1_0_SGMII;
+				data &= (~PSGMIIPHY_MODE_CH1_CH0_SGMII);
+			}
+			else
+			{
+				return SW_NOT_SUPPORTED;
+			}
+
+			break;
+		}
+		case PSGMII_MAC_MODE_SGMII:
+		{
+			data &= (~PSGMIIPHY_MODE_CH0_PSGMII_QSGMII);
+			data &= (~PSGMIIPHY_MODE_CH0_QSGMII_SGMII);
+			if (phy_id == 0)
+			{
+				data &= (~PSGMIIPHY_MODE_CH4_CH1_0_SGMII);
+				data &= (~PSGMIIPHY_MODE_CH1_CH0_SGMII);
+			}
+			else if (phy_id == 1)
+			{
+				data &= (~PSGMIIPHY_MODE_CH4_CH1_0_SGMII);
+				data |= PSGMIIPHY_MODE_CH1_CH0_SGMII;
+			}
+			else if (phy_id == 4)
+			{
+				data |= PSGMIIPHY_MODE_CH4_CH1_0_SGMII;
+				data &= (~PSGMIIPHY_MODE_CH1_CH0_SGMII);
+			}
+			else
+			{
+				return SW_NOT_SUPPORTED;
+			}
+
+			break;
+		}
+		default:
+			break;
+	}
+
+    rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_MODE_CONTROL,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    psgmii_mac_mode = mode;
+    sgmii_ch_id = phy_id;
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* psgmii_get_hibernate - get hibernate status
+*
+* get hibernate status
+*/
+sw_error_t
+dess_psgmii_get_interface_type(a_uint32_t dev_id, a_uint32_t * phy_id,
+								psgmii_interface_mac_mode_t * mode)
+{
+    *phy_id = sgmii_ch_id;
+    *mode = psgmii_mac_mode;
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* psgmii_autoneg_done
+*
+*psgmii_autoneg_done
+*/
+a_bool_t
+dess_psgmii_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_1 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data & PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_1_MR_AN_COMPLETE)
+        return A_TRUE;
+    else
+        return A_FALSE;
+
+    return A_TRUE;
+}
+
+/******************************************************************************
+*
+*psgmii_reset - reset the psgmii
+*
+* reset the psgmii
+*/
+sw_error_t
+dess_psgmii_reset(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MAIN_RESET_25M;
+
+    rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* psgmii_off - power off the psgmii to change its speed
+*
+* Power off the psgmii
+*/
+sw_error_t
+dess_psgmii_poweroff(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_POWER_ON_25M);
+
+    rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* psgmii_on - power on the psgmii after speed changed
+*
+* Power on the psgmii
+*/
+sw_error_t
+dess_psgmii_poweron(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_POWER_ON_25M;
+
+    rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* psgmii_status - test to see if the specified psgmii link is alive
+*
+* RETURNS:
+*    A_TRUE  --> link is alive
+*    A_FALSE --> link is down
+*/
+a_bool_t
+dess_psgmii_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data & PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_LINK_25M)
+        return A_TRUE;
+    else
+        return A_FALSE;
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* psgmii_set_loopback - set the psgmii loopback
+*
+*/
+sw_error_t
+dess_psgmii_set_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+                       a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (enable)
+        data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M;
+    else
+        data &= (~PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M);
+
+    rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* psgmii_get_loopback - get the psgmii loopback
+*
+*/
+sw_error_t
+dess_psgmii_get_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+                       a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data & PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M)
+        *enable = A_TRUE;
+    else
+        *enable = A_FALSE;
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* psgmii_enable_autonego - power off the psgmii to change its speed
+*
+* Power off the phy
+*/
+a_bool_t
+dess_psgmii_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+
+    return A_FALSE;
+}
+
+/******************************************************************************
+*
+* psgmii_restart_autoneg - restart the psgmii autoneg
+*
+*/
+sw_error_t
+dess_psgmii_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_RESTART_AN_25M;
+
+    rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* psgmii_enable_autonego - power off the psgmii to change its speed
+*
+* Power off the phy
+*/
+sw_error_t
+dess_psgmii_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_AN_ENABLE_25M;
+
+    rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+
+/******************************************************************************
+*
+* psgmii_get_speed - Determines the speed of psgmii ports associated with the
+* specified device.
+*/
+
+sw_error_t
+dess_psgmii_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+                 fal_port_speed_t * speed)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /*Force speed mode*/
+    if (data & PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_FORCE_SPEED_25M)
+    {
+	    switch (data & PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_MASK)
+	    {
+	        case PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_1000M:
+	            *speed = FAL_SPEED_1000;
+	            break;
+	        case PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_100M:
+	            *speed = FAL_SPEED_100;
+	            break;
+	        case PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_10M:
+	            *speed = FAL_SPEED_10;
+	            break;
+	        default:
+	            return SW_READ_ERROR;
+	    }
+    }
+    else
+    {
+	    rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5 + phy_id * 0x18,
+							(a_uint8_t *) (&data), sizeof (a_uint32_t));
+	    SW_RTN_ON_ERROR(rv);
+	    switch (data & PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_MODE_25M)
+	    {
+	        case PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_25M_1000M:
+	            *speed = FAL_SPEED_1000;
+	            break;
+	        case PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_25M_100M:
+	            *speed = FAL_SPEED_100;
+	            break;
+	        case PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_25M_10M:
+	            *speed = FAL_SPEED_10;
+	            break;
+	        default:
+	            return SW_READ_ERROR;
+	    }
+    }
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* psgmii_set_speed - Determines the speed of psgmii ports associated with the
+* specified device.
+*/
+sw_error_t
+dess_psgmii_set_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+                 fal_port_speed_t speed)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_FORCE_SPEED_25M;
+    data &= ~(PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_MASK);
+
+    if (FAL_SPEED_1000 == speed)
+    {
+        data |= PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_1000M;
+    }
+    else if (FAL_SPEED_100 == speed)
+    {
+        data |= PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_100M;
+    }
+    else if (FAL_SPEED_10 == speed)
+    {
+        data |= PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_10M;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* psgmii_get_duplex - Determines the speed of psgmii ports associated with the
+* specified device.
+*/
+sw_error_t
+dess_psgmii_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+                  fal_port_duplex_t * duplex)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /*Force speed mode*/
+    if (data & PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_DUPLEX_MODE_25M)
+    {
+	    *duplex = FAL_FULL_DUPLEX;
+    }
+    else
+    {
+	    *duplex = FAL_HALF_DUPLEX;
+    }
+
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+*psgmii_set_duplex - Determines the speed of psgmii ports associated with the
+* specified device.
+*/
+sw_error_t
+dess_psgmii_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+                  fal_port_duplex_t duplex)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_FULL_DUPLEX == duplex)
+    {
+        data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_FULL_DUPLEX_25M;
+        data &= (~PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_HALF_DUPLEX_25M);
+    }
+    else
+    {
+        data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_HALF_DUPLEX_25M;
+        data &= (~PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_FULL_DUPLEX_25M);
+    }
+
+    rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5 + phy_id * 0x18,
+						(a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* psgmii_init -
+*
+*/
+a_bool_t
+dess_psgmii_init(a_uint32_t dev_id, a_uint32_t phy_id,
+            a_uint16_t org_id, a_uint16_t rev_id)
+{
+
+    return SW_OK;
+}
diff --git a/qca-ssdk/src/hsl/dess/dess_qos.c b/qca-ssdk/src/hsl/dess/dess_qos.c
new file mode 100755
index 0000000..80039f5
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_qos.c
@@ -0,0 +1,1562 @@
+/*
+ * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_qos DESS_QOS
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_qos.h"
+#include "dess_reg.h"
+
+#define DESS_QOS_QUEUE_TX_BUFFER_MAX 120
+#define DESS_QOS_PORT_TX_BUFFER_MAX  504
+#define DESS_QOS_PORT_RX_BUFFER_MAX  120
+
+#define DESS_QOS_HOL_STEP       8
+#define DESS_QOS_HOL_MOD        3
+
+//#define DESS_MIN_QOS_MODE_PRI 0
+#define DESS_MAX_QOS_MODE_PRI   3
+#define DESS_MAX_PRI            7
+#define DESS_MAX_QUEUE          3
+#define DESS_MAX_EH_QUEUE       5
+
+static sw_error_t
+_dess_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_RED_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+
+static sw_error_t
+_dess_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_RED_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+
+static sw_error_t
+_dess_qos_port_queue_check(fal_port_t port_id, fal_queue_t queue_id)
+{
+    if ((0 == port_id) || (5 == port_id) || (6 == port_id))
+    {
+        if (DESS_MAX_EH_QUEUE < queue_id)
+        {
+            return SW_BAD_PARAM;
+        }
+    }
+    else
+    {
+        if (DESS_MAX_QUEUE < queue_id)
+        {
+            return SW_BAD_PARAM;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_queue_t queue_id, a_uint32_t * number)
+{
+    a_uint32_t data = 0, val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (DESS_QOS_QUEUE_TX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _dess_qos_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    val = *number / DESS_QOS_HOL_STEP;
+    *number = val << DESS_QOS_HOL_MOD;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0xf << (queue_id << 2)));
+    data |= (val << (queue_id << 2));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return rv;
+}
+
+static sw_error_t
+_dess_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_queue_t queue_id, a_uint32_t * number)
+{
+    a_uint32_t data = 0, val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _dess_qos_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    val = (data >> (queue_id << 2)) & 0xf;
+    *number = val << DESS_QOS_HOL_MOD;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (DESS_QOS_PORT_TX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = *number / DESS_QOS_HOL_STEP;
+    *number = val << DESS_QOS_HOL_MOD;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *number = val << DESS_QOS_HOL_MOD;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (DESS_QOS_PORT_RX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = *number / DESS_QOS_HOL_STEP;
+    *number = val << DESS_QOS_HOL_MOD;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *number = val << DESS_QOS_HOL_MOD;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qos_mode_t mode, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_FLOW_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, FLOW_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_dess_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qos_mode_t mode, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_FLOW_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, FLOW_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_qos_mode_t mode, a_uint32_t pri)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (DESS_MAX_QOS_MODE_PRI < pri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_FLOW_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, FLOW_PRI_SEL, pri, val);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_qos_mode_t mode, a_uint32_t * pri)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0, f_val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_FLOW_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, FLOW_PRI_SEL, f_val, entry);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    *pri = f_val;
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                            fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val, w[6] = { 0 };
+    a_int32_t i, _index;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SCH_SP_MODE == mode)
+    {
+        val = 0;
+        _index = -1;
+    }
+    else if (FAL_SCH_WRR_MODE == mode)
+    {
+        val = 3;
+        _index = 5;
+    }
+    else if (FAL_SCH_MIX_MODE == mode)
+    {
+        val = 1;
+        _index = 4;
+    }
+    else if (FAL_SCH_MIX_PLUS_MODE == mode)
+    {
+        val = 2;
+        _index = 3;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    for (i = _index; i >= 0; i--)
+    {
+        if (weight[i] > 0x1f)
+        {
+            return SW_BAD_PARAM;
+        }
+        w[i] = weight[i];
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(WRR_CTRL, SCH_MODE, val, reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q5_W, w[5], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q4_W, w[4], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q3_W, w[3], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q2_W, w[2], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q1_W, w[1], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q0_W, w[0], reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, WRR_CTRL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                            fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+    a_uint32_t val = 0, sch, w[6], i;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(WRR_CTRL, SCH_MODE, sch, val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q5_W, w[5], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q4_W, w[4], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q3_W, w[3], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q2_W, w[2], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q1_W, w[1], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q0_W, w[0], val);
+
+    if (0 == sch)
+    {
+        *mode = FAL_SCH_SP_MODE;
+    }
+    else if (1 == sch)
+    {
+        *mode = FAL_SCH_MIX_MODE;
+    }
+    else if (2 == sch)
+    {
+        *mode = FAL_SCH_MIX_PLUS_MODE;
+    }
+    else
+    {
+        *mode = FAL_SCH_WRR_MODE;
+    }
+
+    for (i = 0; i < 6; i++)
+    {
+        weight[i] = w[i];
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t spri)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (DESS_MAX_PRI < spri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = spri;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_dess_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * spri)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    *spri = val & 0x7;
+    return rv;
+}
+
+static sw_error_t
+_dess_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t cpri)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (DESS_MAX_PRI < cpri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = cpri;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+_dess_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * cpri)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    *cpri = val & 0x7;
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+_dess_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_FORCE_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+_dess_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_bool_t* enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_FORCE_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+_dess_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = enable ? 1 : 0;
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_FORCE_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+_dess_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_bool_t* enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_FORCE_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_dess_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t addr, data = 0;
+    a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60};
+
+    rv = _dess_qos_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    addr = base[port_id] + ((queue_id / 4) << 2);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0xff << ((queue_id % 4) << 3)));
+    data |= (((enable << 7 ) | (tbl_id & 0xf)) << ((queue_id % 4) << 3));
+
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+_dess_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t addr, data = 0;
+    a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60};
+
+    rv = _dess_qos_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    addr = base[port_id] + ((queue_id / 4) << 2);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *tbl_id = (data >> ((queue_id % 4) << 3)) & 0xf;
+    *enable = ((data >> ((queue_id % 4) << 3)) & 0x80) >> 7;
+    return SW_OK;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting queue on one particular port.
+ *   @details  Comments:
+ *    If enable queue tx buffer on one port that means each queue of this port
+ *    will have fixed number buffers when transmitting packets. Otherwise they
+ *    share the whole buffers with other queues in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_queue_tx_buf_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting queue on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_queue_tx_buf_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting port on one particular port.
+ *   @details  Comments:
+    If enable tx buffer on one port that means this port will have fixed
+    number buffers when transmitting packets. Otherwise they will
+    share the whole buffers with other ports in device.
+ *    function will return actual buffer numbers in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_tx_buf_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_tx_buf_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of port red on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_red_en_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of port red on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_red_en_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+/**
+ * @brief Set max occupied buffer number of transmitting queue on one particular port.
+ *   @details   Comments:
+    The step of buffer number in Garuda is 4, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for queue is 4 to 60.
+ *    share the whole buffers with other ports in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting queue on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting port on one particular port.
+ *   @details   Comments:
+    The step of buffer number in Garuda is four, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for transmitting port is 4 to 124.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_tx_buf_nr_set(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_tx_buf_nr_get(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of receiving port on one particular port.
+ *   @details   Comments:
+    The step of buffer number in Shiva is four, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for receiving port is 4 to 60.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_rx_buf_nr_set(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of receiving port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_rx_buf_nr_get(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_qos_mode_t mode, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_mode_set(dev_id, port_id, mode, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_qos_mode_t mode, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_mode_get(dev_id, port_id, mode, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set priority of one particular qos mode on one particular port.
+ *   @details   Comments:
+    If the priority of a mode is more small then the priority is more high.
+    Differnet mode should have differnet priority.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_qos_mode_t mode, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get priority of one particular qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_qos_mode_t mode, a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set traffic scheduling mode on particular one port.
+ *   @details   Comments:
+ *   When scheduling mode is sp the weight is meaningless usually it's zero
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[in] weight[] weight value for each queue when in wrr mode,
+              the max value supported by ISIS is 0x1f.
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                           fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_sch_mode_set(dev_id, port_id, mode, weight);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get traffic scheduling mode on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] fal_sch_mode_t traffic scheduling mode
+ * @param[out] weight weight value for wrr mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                           fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_sch_mode_get(dev_id, port_id, mode, weight);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default stag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] spri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t spri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_default_spri_set(dev_id, port_id, spri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default stag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] spri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * spri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_default_spri_get(dev_id, port_id, spri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default ctag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cpri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t cpri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_default_cpri_set(dev_id, port_id, cpri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default ctag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cpri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * cpri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_default_cpri_get(dev_id, port_id, cpri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port force stag priority enable flag one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_force_spri_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port force stag priority enable flag one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t* enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _dess_qos_port_force_spri_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port force ctag priority enable flag one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_force_cpri_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port force ctag priority enable flag one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_port_force_cpri_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress queue based CoS remark on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[in] tbl_id CoS remark table id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_queue_remark_table_set(dev_id, port_id, queue_id, tbl_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress queue based CoS remark on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] tbl_id CoS remark table id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_qos_queue_remark_table_get(dev_id, port_id, queue_id, tbl_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+dess_qos_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->qos_queue_tx_buf_status_set = dess_qos_queue_tx_buf_status_set;
+        p_api->qos_queue_tx_buf_status_get = dess_qos_queue_tx_buf_status_get;
+        p_api->qos_port_tx_buf_status_set = dess_qos_port_tx_buf_status_set;
+        p_api->qos_port_tx_buf_status_get = dess_qos_port_tx_buf_status_get;
+        p_api->qos_port_red_en_set = dess_qos_port_red_en_set;
+        p_api->qos_port_red_en_get = dess_qos_port_red_en_get;
+        p_api->qos_queue_tx_buf_nr_set = dess_qos_queue_tx_buf_nr_set;
+        p_api->qos_queue_tx_buf_nr_get = dess_qos_queue_tx_buf_nr_get;
+        p_api->qos_port_tx_buf_nr_set = dess_qos_port_tx_buf_nr_set;
+        p_api->qos_port_tx_buf_nr_get = dess_qos_port_tx_buf_nr_get;
+        p_api->qos_port_rx_buf_nr_set = dess_qos_port_rx_buf_nr_set;
+        p_api->qos_port_rx_buf_nr_get = dess_qos_port_rx_buf_nr_get;
+        p_api->qos_port_mode_set = dess_qos_port_mode_set;
+        p_api->qos_port_mode_get = dess_qos_port_mode_get;
+        p_api->qos_port_mode_pri_set = dess_qos_port_mode_pri_set;
+        p_api->qos_port_mode_pri_get = dess_qos_port_mode_pri_get;
+        p_api->qos_port_sch_mode_set = dess_qos_port_sch_mode_set;
+        p_api->qos_port_sch_mode_get = dess_qos_port_sch_mode_get;
+        p_api->qos_port_default_spri_set = dess_qos_port_default_spri_set;
+        p_api->qos_port_default_spri_get = dess_qos_port_default_spri_get;
+        p_api->qos_port_default_cpri_set = dess_qos_port_default_cpri_set;
+        p_api->qos_port_default_cpri_get = dess_qos_port_default_cpri_get;
+        p_api->qos_port_force_spri_status_set = dess_qos_port_force_spri_status_set;
+        p_api->qos_port_force_spri_status_get = dess_qos_port_force_spri_status_get;
+        p_api->qos_port_force_cpri_status_set = dess_qos_port_force_cpri_status_set;
+        p_api->qos_port_force_cpri_status_get = dess_qos_port_force_cpri_status_get;
+        p_api->qos_queue_remark_table_set = dess_qos_queue_remark_table_set;
+        p_api->qos_queue_remark_table_get = dess_qos_queue_remark_table_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/dess/dess_rate.c b/qca-ssdk/src/hsl/dess/dess_rate.c
new file mode 100755
index 0000000..44cd36a
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_rate.c
@@ -0,0 +1,1672 @@
+/*
+ * Copyright (c) 2014,2016 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_rate DESS_RATE
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_rate.h"
+#include "dess_reg.h"
+
+#define DESS_MAX_POLICER_ID          31
+#define DESS_MAX_QUEUE               3
+#define DESS_MAX_EH_QUEUE            5
+
+#define ACL_POLICER_CNT_SEL_ADDR          0x09f0
+#define ACL_POLICER_CNT_MODE_ADDR         0x09f4
+#define ACL_POLICER_CNT_RST_ADDR          0x09f8
+
+static sw_error_t
+_dess_rate_port_queue_check(fal_port_t port_id, fal_queue_t queue_id)
+{
+    if ((0 == port_id) || (5 == port_id) || (6 == port_id))
+    {
+        if (DESS_MAX_EH_QUEUE < queue_id)
+        {
+            return SW_BAD_PARAM;
+        }
+    }
+    else
+    {
+        if (DESS_MAX_QUEUE < queue_id)
+        {
+            return SW_BAD_PARAM;
+        }
+    }
+
+    return SW_OK;
+}
+
+static void
+_dess_egress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+    a_int32_t i;
+    a_uint32_t data[8] =
+    {
+        0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024,
+        512 * 1024
+    };
+
+    for (i = 7; i >= 0; i--)
+    {
+        if (sw_bs >= data[i])
+        {
+            *hw_bs = i;
+            break;
+        }
+    }
+}
+
+static void
+_dess_egress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+    a_uint32_t data[8] =
+    {
+        0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024,
+        512 * 1024
+    };
+
+    *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_dess_egress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+    a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 };
+    a_int32_t i;
+
+    for (i = 7; i >= 0; i--)
+    {
+        if (sw_bs >= data[i])
+        {
+            *hw_bs = i;
+            break;
+        }
+    }
+}
+
+static void
+_dess_egress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+    a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 };
+
+    *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_dess_ingress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+    a_int32_t i;
+    a_uint32_t data[8] =
+    {
+        0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024,
+        8 * 1024 * 1024, 32 * 1024 * 1024
+    };
+
+    for (i = 7; i >= 0; i--)
+    {
+        if (sw_bs >= data[i])
+        {
+            *hw_bs = i;
+            break;
+        }
+    }
+}
+
+static void
+_dess_ingress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+    a_uint32_t data[8] =
+    {
+        0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024,
+        8 * 1024 * 1024, 32 * 1024 * 1024
+    };
+
+    *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_dess_ingress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+    a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 };
+    a_int32_t i;
+
+    for (i = 7; i >= 0; i--)
+    {
+        if (sw_bs >= data[i])
+        {
+            *hw_bs = i;
+            break;
+        }
+    }
+}
+
+static void
+_dess_ingress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+    a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 };
+
+    *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_dess_rate_flag_parse(a_uint32_t sw_flag, a_uint32_t * hw_flag)
+{
+    *hw_flag = 0;
+
+    if (FAL_INGRESS_POLICING_TCP_CTRL & sw_flag)
+    {
+        *hw_flag |= (0x1 << 1);
+    }
+
+    if (FAL_INGRESS_POLICING_MANAGEMENT & sw_flag)
+    {
+        *hw_flag |= (0x1 << 2);
+    }
+
+    if (FAL_INGRESS_POLICING_BROAD & sw_flag)
+    {
+        *hw_flag |= (0x1 << 3);
+    }
+
+    if (FAL_INGRESS_POLICING_UNK_UNI & sw_flag)
+    {
+        *hw_flag |= (0x1 << 4);
+    }
+
+    if (FAL_INGRESS_POLICING_UNK_MUL & sw_flag)
+    {
+        *hw_flag |= (0x1 << 5);
+    }
+
+    if (FAL_INGRESS_POLICING_UNI & sw_flag)
+    {
+        *hw_flag |= (0x1 << 6);
+    }
+
+    if (FAL_INGRESS_POLICING_MUL & sw_flag)
+    {
+        *hw_flag |= (0x1 << 7);
+    }
+}
+
+static void
+_dess_rate_flag_reparse(a_uint32_t hw_flag, a_uint32_t * sw_flag)
+{
+    *sw_flag = 0;
+
+    if (hw_flag & 0x2)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_TCP_CTRL;
+    }
+
+    if (hw_flag & 0x4)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_MANAGEMENT;
+    }
+
+    if (hw_flag & 0x8)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_BROAD;
+    }
+
+    if (hw_flag & 0x10)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_UNK_UNI;
+    }
+
+    if (hw_flag & 0x20)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_UNK_MUL;
+    }
+
+    if (hw_flag & 0x40)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_UNI;
+    }
+
+    if (hw_flag & 0x80)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_MUL;
+    }
+}
+
+static void
+_dess_rate_ts_parse(fal_rate_mt_t sw, a_uint32_t * hw)
+{
+    if (FAL_RATE_MI_100US == sw)
+    {
+        *hw = 0;
+    }
+    else if (FAL_RATE_MI_1MS == sw)
+    {
+        *hw = 1;
+    }
+    else if (FAL_RATE_MI_10MS == sw)
+    {
+        *hw = 2;
+    }
+    else if (FAL_RATE_MI_100MS)
+    {
+        *hw = 3;
+    }
+    else
+    {
+        *hw = 0;
+    }
+}
+
+static void
+_dess_rate_ts_reparse(a_uint32_t hw, fal_rate_mt_t * sw)
+{
+    if (0 == hw)
+    {
+        *sw = FAL_RATE_MI_100US;
+    }
+    else if (1 == hw)
+    {
+        *sw = FAL_RATE_MI_1MS;
+    }
+    else if (2 == hw)
+    {
+        *sw = FAL_RATE_MI_10MS;
+    }
+    else
+    {
+        *sw = FAL_RATE_MI_100MS;
+    }
+}
+
+static sw_error_t
+_dess_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+    a_uint32_t cir = 0x7fff, eir = 0x7fff, cbs = 0, ebs = 0, tmp, data[3] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data[0] = 0x18000000;
+    if (FAL_BYTE_BASED == policer->meter_unit)
+    {
+        if (A_TRUE == policer->c_enable)
+        {
+            cir = policer->cir >> 5;
+            policer->cir = cir << 5;
+            _dess_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs);
+            _dess_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+        }
+
+        if (A_TRUE == policer->e_enable)
+        {
+            eir = policer->eir >> 5;
+            policer->eir = eir << 5;
+            _dess_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs);
+            _dess_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+        }
+
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 0, data[1]);
+    }
+    else if (FAL_FRAME_BASED == policer->meter_unit)
+    {
+        if (A_TRUE == policer->c_enable)
+        {
+            cir = (policer->cir * 2) / 125;
+            policer->cir = cir / 2 * 125 + cir % 2 * 63;
+            _dess_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs);
+            _dess_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+        }
+
+        if (A_TRUE == policer->e_enable)
+        {
+            eir = (policer->eir * 2) / 125;
+            policer->eir = eir / 2 * 125 + eir % 2 * 63;
+            _dess_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs);
+            _dess_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+        }
+
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 1, data[1]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]);
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]);
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]);
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]);
+
+    if (A_TRUE == policer->combine_mode)
+    {
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER0, RATE_MODE, 1, data[0]);
+    }
+
+    if (A_TRUE == policer->deficit_en)
+    {
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_BORROW, 1, data[1]);
+    }
+
+    if (A_TRUE == policer->color_mode)
+    {
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CM, 1, data[1]);
+    }
+
+    if (A_TRUE == policer->couple_flag)
+    {
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CF, 1, data[1]);
+    }
+
+    _dess_rate_ts_parse(policer->c_meter_interval, &tmp);
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER0, C_ING_TS, tmp, data[0]);
+
+    _dess_rate_ts_parse(policer->e_meter_interval, &tmp);
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER1, E_ING_TS, tmp, data[1]);
+
+    _dess_rate_flag_parse(policer->c_rate_flag, &tmp);
+    data[2] = (tmp << 8) & 0xff00;
+
+    _dess_rate_flag_parse(policer->e_rate_flag, &tmp);
+    data[2] |= (tmp & 0xff);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER0, port_id,
+                      (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER1, port_id,
+                      (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER2, port_id,
+                      (a_uint8_t *) (&data[2]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+    a_uint32_t unit, ts, cir, eir, cbs, ebs, data[3] = {0};
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER0, port_id,
+                      (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER1, port_id,
+                      (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER2, port_id,
+                      (a_uint8_t *) (&data[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_UNIT, unit, data[1]);
+
+    policer->c_enable = A_TRUE;
+    if (0x7fff == cir)
+    {
+        policer->c_enable = A_FALSE;
+        cir = 0;
+    }
+
+    policer->e_enable = A_TRUE;
+    if (0x7fff == eir)
+    {
+        policer->e_enable = A_FALSE;
+        eir = 0;
+    }
+
+    if (unit)
+    {
+        policer->meter_unit = FAL_FRAME_BASED;
+        policer->cir = cir / 2 * 125 + cir % 2 * 63;
+        policer->eir = eir / 2 * 125 + eir % 2 * 63;
+        _dess_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+        _dess_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+    }
+    else
+    {
+        policer->meter_unit = FAL_BYTE_BASED;
+        policer->cir = cir << 5;
+        policer->eir = eir << 5;
+        _dess_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+        _dess_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+    }
+
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER0, RATE_MODE, policer->combine_mode,
+                        data[0]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_BORROW, policer->deficit_en,
+                        data[1]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CF, policer->couple_flag,
+                        data[1]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CM, policer->color_mode,
+                        data[1]);
+
+    ts = (data[2] >> 8) & 0xff;
+    _dess_rate_flag_reparse(ts, &(policer->c_rate_flag));
+
+    ts = data[2] & 0xff;
+    _dess_rate_flag_reparse(ts, &(policer->e_rate_flag));
+
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER0, C_ING_TS, ts, data[0]);
+    _dess_rate_ts_reparse(ts, &(policer->c_meter_interval));
+
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, E_ING_TS, ts, data[1]);
+    _dess_rate_ts_reparse(ts, &(policer->e_meter_interval));
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    a_uint32_t data, cir, eir, cbs = 0, ebs = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == enable)
+    {
+        aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+        cir = 0x7fff;
+        eir = 0x7fff;
+    }
+    else
+    {
+        if (FAL_BYTE_BASED == shaper->meter_unit)
+        {
+            cir = shaper->cir >> 5;
+            shaper->cir = cir << 5;
+
+            eir = shaper->eir >> 5;
+            shaper->eir = eir << 5;
+
+            _dess_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs);
+            _dess_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+
+            _dess_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs);
+            _dess_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+
+            data = 0;
+        }
+        else if (FAL_FRAME_BASED == shaper->meter_unit)
+        {
+            cir = (shaper->cir * 2) / 125;
+            shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+
+            eir = (shaper->eir * 2) / 125;
+            shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+
+            _dess_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs);
+            _dess_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+
+            _dess_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs);
+            _dess_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+
+            data = 1;
+        }
+        else
+        {
+            return SW_BAD_PARAM;
+        }
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        data = 1;
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        data = 0;
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_TS,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+                      (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+                      (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+                      (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+                      (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, cir = 0, eir = 0, cbs = 0, ebs = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (!data)
+    {
+        *enable = A_FALSE;
+        return SW_OK;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+                      (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+                      (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+                      (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+                      (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if ((0x7fff == cir) && (0x7fff == eir))
+    {
+        *enable = A_FALSE;
+        return SW_OK;
+    }
+
+    *enable = A_TRUE;
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        shaper->meter_unit = FAL_FRAME_BASED;
+        shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+        shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+        _dess_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+        _dess_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+    }
+    else
+    {
+        shaper->meter_unit = FAL_BYTE_BASED;
+        shaper->cir = cir << 5;
+        shaper->eir = eir << 5;
+        _dess_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+        _dess_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_queue_t queue_id, a_bool_t enable,
+                            fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    a_uint32_t unit = 0, data, cir, eir, cbs = 0, ebs = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _dess_rate_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_FALSE == enable)
+    {
+        aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+        cir = 0x7fff;
+        eir = 0x7fff;
+    }
+    else
+    {
+        if (FAL_BYTE_BASED == shaper->meter_unit)
+        {
+            cir = shaper->cir >> 5;
+            shaper->cir = cir << 5;
+
+            eir = shaper->eir >> 5;
+            shaper->eir = eir << 5;
+
+            _dess_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs);
+            _dess_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+
+            _dess_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs);
+            _dess_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+
+            unit = 0;
+        }
+        else if (FAL_FRAME_BASED == shaper->meter_unit)
+        {
+            cir = (shaper->cir * 2) / 125;
+            shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+
+            eir = (shaper->eir * 2) / 125;
+            shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+
+            _dess_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs);
+            _dess_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+
+            _dess_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs);
+            _dess_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+
+            unit = 1;
+        }
+
+        data = 0;
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        data = 0;
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_TS,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (4 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_queue_t queue_id, a_bool_t * enable,
+                            fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, cir = 0, eir = 0, cbs = 0, ebs = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _dess_rate_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *enable = A_FALSE;
+        return SW_OK;
+    }
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (4 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    if ((0x7fff == cir) && (0x7fff == eir))
+    {
+        *enable = A_FALSE;
+        return SW_OK;
+    }
+
+    *enable = A_TRUE;
+    if (data)
+    {
+        shaper->meter_unit = FAL_FRAME_BASED;
+        shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+        shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+        _dess_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+        _dess_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+    }
+    else
+    {
+        shaper->meter_unit = FAL_BYTE_BASED;
+        shaper->cir = cir << 5;
+        shaper->eir = eir << 5;
+        _dess_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+        _dess_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+                           fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+    a_uint32_t ts, cir, eir, cbs = 0, ebs = 0, addr, data[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (DESS_MAX_POLICER_ID < policer_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == policer->counter_mode)
+    {
+        addr = ACL_POLICER_CNT_SEL_ADDR;
+        data[0] = 0x1;
+        HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+                              (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        addr = ACL_POLICER_CNT_MODE_ADDR;
+        if (FAL_FRAME_BASED == policer->meter_unit)
+        {
+            data[0] = 0x0;
+        }
+        else
+        {
+            data[0] = 0x1;
+        }
+        HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+                              (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        addr = ACL_POLICER_CNT_RST_ADDR;
+        data[0] = 0x1;
+        HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+                              (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        data[0] = 0x0;
+        HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+                              (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        return rv;
+    }
+
+    addr = ACL_POLICER_CNT_SEL_ADDR;
+    data[0] = 0x0;
+    HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+                          (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_BYTE_BASED == policer->meter_unit)
+    {
+        cir = policer->cir >> 5;
+        policer->cir = cir << 5;
+
+        eir = policer->eir >> 5;
+        policer->eir = eir << 5;
+
+        _dess_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs);
+        _dess_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+
+        _dess_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs);
+        _dess_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+
+        SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 0, data[1]);
+    }
+    else if (FAL_FRAME_BASED == policer->meter_unit)
+    {
+        cir = (policer->cir * 2) / 125;
+        policer->cir = cir / 2 * 125 + cir % 2 * 63;
+
+        eir = (policer->eir * 2) / 125;
+        policer->eir = eir / 2 * 125 + eir % 2 * 63;
+
+        _dess_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs);
+        _dess_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+
+        _dess_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs);
+        _dess_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+
+        SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 1, data[1]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CIR, cir, data[0]);
+    SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CBS, cbs, data[0]);
+    SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EIR, eir, data[1]);
+    SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EBS, ebs, data[1]);
+
+    if (A_TRUE == policer->deficit_en)
+    {
+        SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_BORROW, 1, data[1]);
+    }
+
+    if (A_TRUE == policer->color_mode)
+    {
+        SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CM, 1, data[1]);
+    }
+
+    if (A_TRUE == policer->couple_flag)
+    {
+        SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CF, 1, data[1]);
+    }
+
+    _dess_rate_ts_parse(policer->meter_interval, &ts);
+    SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_TS, ts, data[1]);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER0, policer_id,
+                      (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER1, policer_id,
+                      (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_dess_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+                           fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+    a_uint32_t unit, ts, cir, eir, cbs, ebs, addr, data[2] = {0};
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (DESS_MAX_POLICER_ID < policer_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(policer, sizeof (policer));
+
+    addr = ACL_POLICER_CNT_SEL_ADDR;
+    HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id,
+                          (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data[0])
+    {
+        policer->counter_mode = A_TRUE;
+
+        addr = ACL_POLICER_CNT_MODE_ADDR;
+        HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id,
+                              (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        if (data[0])
+        {
+            policer->meter_unit = FAL_BYTE_BASED;
+        }
+        else
+        {
+            policer->meter_unit = FAL_FRAME_BASED;
+        }
+
+        HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER0, policer_id,
+                          (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER1, policer_id,
+                          (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        policer->counter_low = data[0];
+        policer->counter_high = data[1];
+
+        return SW_OK;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER0, policer_id,
+                      (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER1, policer_id,
+                      (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+
+    SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CIR, cir, data[0]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CBS, cbs, data[0]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EIR, eir, data[1]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EBS, ebs, data[1]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_UNIT, unit, data[1]);
+    if (unit)
+    {
+        policer->meter_unit = FAL_FRAME_BASED;
+        policer->cir = cir / 2 * 125 + cir % 2 * 63;
+        policer->eir = eir / 2 * 125 + eir % 2 * 63;
+        _dess_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+        _dess_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+
+    }
+    else
+    {
+        policer->meter_unit = FAL_BYTE_BASED;
+        policer->cir = cir << 5;
+        policer->eir = eir << 5;
+        _dess_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+        _dess_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_BORROW, policer->deficit_en,
+                        data[1]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CF, policer->couple_flag, data[1]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CM, policer->color_mode, data[1]);
+
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_TS, ts, data[1]);
+    _dess_rate_ts_reparse(ts, &(policer->meter_interval));
+
+    return SW_OK;
+}
+
+sw_error_t
+_dess_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t  number)
+{
+    a_uint32_t val = number;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (val>255)
+        return SW_BAD_PARAM;
+
+    HSL_REG_FIELD_SET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+sw_error_t
+_dess_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t  *number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv = SW_OK;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+
+    HSL_REG_FIELD_GET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    *number = val;
+
+    return rv;
+}
+
+sw_error_t
+_dess_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t  enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, QM_CTRL_REG, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+
+    if (A_TRUE == enable)
+    {
+        val |= (0x1<<(16+port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        val &= ~(0x1<<(16+port_id));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, QM_CTRL_REG, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+sw_error_t
+_dess_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t*  enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, QM_CTRL_REG, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (val&(0x1<<(16+port_id)))
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+
+
+/**
+ * @brief Set port ingress policer parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port ingress policer input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] policer port ingress policer parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_rate_port_policer_set(dev_id, port_id, policer);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port ingress policer parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port ingress policer input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] policer port ingress policer parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_rate_port_policer_get(dev_id, port_id, policer);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port egress shaper parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port egress shaper parameters is meaningless.
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_rate_port_shaper_set(dev_id, port_id, enable, shaper);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port egress shaper parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port egress shaper parameters is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_rate_port_shaper_get(dev_id, port_id, enable, shaper);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set queue egress shaper parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable queue egress shaper parameters is meaningless.
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_queue_t queue_id, a_bool_t enable,
+                           fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_rate_queue_shaper_set(dev_id, port_id, queue_id, enable, shaper);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get queue egress shaper parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable queue egress shaper parameters is meaningless.
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_queue_t queue_id, a_bool_t * enable,
+                           fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_rate_queue_shaper_get(dev_id, port_id, queue_id, enable, shaper);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ACL ingress policer parameters.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+ * @param[in] dev_id device id
+ * @param[in] policer_id ACL policer id
+ * @param[in] policer ACL ingress policer parameters
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+                          fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_rate_acl_policer_set(dev_id, policer_id, policer);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ACL ingress policer parameters.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+ * @param[in] dev_id device id
+ * @param[in] policer_id ACL policer id
+ * @param[in] policer ACL ingress policer parameters
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+                          fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_rate_acl_policer_get(dev_id, policer_id, policer);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+dess_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t  number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_rate_port_add_rate_byte_set(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+dess_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t  *number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_rate_port_add_rate_byte_get(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of port global flow control when global threshold is reached.
+  * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_rate_port_gol_flow_en_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief get status of port global flow control when global threshold is reached.
+  * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_rate_port_gol_flow_en_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+
+sw_error_t
+dess_rate_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->rate_port_policer_set = dess_rate_port_policer_set;
+        p_api->rate_port_policer_get = dess_rate_port_policer_get;
+        p_api->rate_port_shaper_set = dess_rate_port_shaper_set;
+        p_api->rate_port_shaper_get = dess_rate_port_shaper_get;
+        p_api->rate_queue_shaper_set = dess_rate_queue_shaper_set;
+        p_api->rate_queue_shaper_get = dess_rate_queue_shaper_get;
+        p_api->rate_acl_policer_set = dess_rate_acl_policer_set;
+        p_api->rate_acl_policer_get = dess_rate_acl_policer_get;
+        p_api->rate_port_gol_flow_en_set = dess_rate_port_gol_flow_en_set;
+        p_api->rate_port_gol_flow_en_get = dess_rate_port_gol_flow_en_get;
+        p_api->rate_port_add_rate_byte_set=dess_rate_port_add_rate_byte_set;
+        p_api->rate_port_add_rate_byte_get=dess_rate_port_add_rate_byte_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/dess/dess_reg_access.c b/qca-ssdk/src/hsl/dess/dess_reg_access.c
new file mode 100755
index 0000000..734b2e7
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_reg_access.c
@@ -0,0 +1,644 @@
+/*
+ * Copyright (c) 2014, 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "sd.h"
+#include "dess_reg_access.h"
+#include "dess_psgmii.h"
+
+#if 0
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <asm/uaccess.h>
+#include <linux/mm.h>
+#endif
+
+static hsl_access_mode reg_mode;
+
+#if defined(API_LOCK)
+static aos_lock_t mdio_lock;
+#define MDIO_LOCKER_INIT    aos_lock_init(&mdio_lock)
+#define MDIO_LOCKER_LOCK    aos_lock(&mdio_lock)
+#define MDIO_LOCKER_UNLOCK  aos_unlock(&mdio_lock)
+#else
+#define MDIO_LOCKER_INIT
+#define MDIO_LOCKER_LOCK
+#define MDIO_LOCKER_UNLOCK
+#endif
+
+#if defined(REG_ACCESS_SPEEDUP)
+static a_uint32_t mdio_base_addr = 0xffffffff;
+#endif
+
+extern void ssdk_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable, a_uint32_t times, a_uint32_t *result);
+extern void clear_self_test_config(a_uint32_t dev_id);
+
+static sw_error_t
+_dess_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint8_t value[], a_uint32_t value_len)
+{
+#if 0
+	 a_uint32_t reg_word_addr;
+	 a_uint32_t phy_addr, reg_val;
+	 a_uint16_t phy_val, tmp_val;
+	 a_uint8_t phy_reg;
+	 sw_error_t rv;
+#else
+	a_uint32_t reg_val;
+#endif
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+#if 0
+    /* change reg_addr to 16-bit word address, 32-bit aligned */
+    reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+    /* configure register high address */
+    phy_addr = 0x18;
+    phy_reg = 0x0;
+    phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+
+#if defined(REG_ACCESS_SPEEDUP)
+    if (phy_val != mdio_base_addr)
+    {
+        rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+        SW_RTN_ON_ERROR(rv);
+
+        mdio_base_addr = phy_val;
+    }
+#else
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+    /* For some registers such as MIBs, since it is read/clear, we should */
+    /* read the lower 16-bit register then the higher one */
+
+    /* read register in lower address */
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+    SW_RTN_ON_ERROR(rv);
+    reg_val = tmp_val;
+
+    /* read register in higher address */
+    reg_word_addr++;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+    SW_RTN_ON_ERROR(rv);
+    reg_val |= (((a_uint32_t)tmp_val) << 16);
+#else
+    reg_val = sd_reg_mii_get(dev_id, reg_addr);
+#endif
+    aos_mem_copy(value, &reg_val, sizeof (a_uint32_t));
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                   a_uint32_t value_len)
+{
+#if 0
+	 a_uint32_t reg_word_addr;
+	 a_uint32_t phy_addr, reg_val;
+	 a_uint16_t phy_val;
+	 a_uint8_t phy_reg;
+	 sw_error_t rv;
+#else
+	a_uint32_t reg_val = 0;
+#endif
+
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    aos_mem_copy(&reg_val, value, sizeof (a_uint32_t));
+
+#if 0
+    /* change reg_addr to 16-bit word address, 32-bit aligned */
+    reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+    /* configure register high address */
+    phy_addr = 0x18;
+    phy_reg = 0x0;
+    phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+
+#if defined(REG_ACCESS_SPEEDUP)
+    if (phy_val != mdio_base_addr)
+    {
+        rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+        SW_RTN_ON_ERROR(rv);
+
+        mdio_base_addr = phy_val;
+    }
+#else
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+    /* For some registers such as ARL and VLAN, since they include BUSY bit */
+    /* in higher address, we should write the lower 16-bit register then the */
+    /* higher one */
+
+    /* write register in lower address */
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (a_uint16_t) (reg_val & 0xffff);
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    /* write register in higher address */
+    reg_word_addr++;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff);
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+#else
+    sd_reg_mii_set(dev_id, reg_addr, reg_val);
+#endif
+    return SW_OK;
+}
+
+sw_error_t
+dess_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+             a_uint32_t reg, a_uint16_t * value)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value);
+    MDIO_LOCKER_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+dess_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+             a_uint32_t reg, a_uint16_t value)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value);
+    MDIO_LOCKER_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+dess_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+             a_uint32_t value_len)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    if (HSL_MDIO == reg_mode)
+    {
+        rv = _dess_mdio_reg_get(dev_id, reg_addr, value, value_len);
+    }
+    else
+    {
+        rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len);
+    }
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+dess_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+             a_uint32_t value_len)
+{
+    sw_error_t rv;
+#if 0
+    unsigned long flags;
+
+    struct file *filp;
+    // mm_segment_t fs;
+    a_uint32_t rt_value = 0;
+    a_uint32_t write_flag = 0;
+    char s[20]= {0};
+    a_uint32_t tmp_val = *((a_uint32_t *) value);
+#else
+	a_uint32_t rt_value = 0;
+#endif
+
+    /*get MODULE_EN reg rsv */
+    SW_RTN_ON_ERROR(dess_reg_get(dev_id, 0x30,(void *)&rt_value,4));
+//    write_flag = (rt_value>>15) & 0x1;
+
+    MDIO_LOCKER_LOCK;
+    if (HSL_MDIO == reg_mode)
+    {
+        rv = _dess_mdio_reg_set(dev_id, reg_addr, value, value_len);
+    }
+    else
+    {
+        rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len);
+    }
+    MDIO_LOCKER_UNLOCK;
+
+#if 0
+    if(write_flag)
+    {
+        filp = filp_open("/tmp/asic_output", O_RDWR|O_APPEND, 0644);
+        if(IS_ERR(filp))
+        {
+            printk("open error...\n");
+            return;
+        }
+
+        fs=get_fs();
+
+        set_fs(KERNEL_DS);
+        sprintf(s,"%08x %08x\n",reg_addr,tmp_val);
+        filp->f_op->write(filp, s, strlen(s),&filp->f_pos);
+
+        set_fs(fs);
+
+        filp_close(filp,NULL);
+    }
+#endif
+
+    return rv;
+}
+
+sw_error_t
+dess_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint32_t bit_offset, a_uint32_t field_len,
+                   a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val = 0;
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(dess_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+
+    if(32 == field_len)
+    {
+        *((a_uint32_t *) value) = reg_val;
+    }
+    else
+    {
+        *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len);
+    }
+    return SW_OK;
+}
+
+sw_error_t
+dess_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint32_t bit_offset, a_uint32_t field_len,
+                   const a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val = 0;
+    a_uint32_t field_val = *((a_uint32_t *) value);
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(dess_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    if(32 == field_len)
+    {
+        reg_val = field_val;
+    }
+    else
+    {
+        SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len);
+    }
+
+
+    SW_RTN_ON_ERROR(dess_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump)
+{
+    sw_error_t rv = SW_OK;
+	typedef struct {
+		a_uint32_t reg_base;
+		a_uint32_t reg_end;
+		char name[30];
+	} regdump;
+
+	regdump reg_dumps[8] =
+	{
+		{0x0, 0xE4, "0.Global control registers"},
+		{0x100, 0x168, "1.EEE control registers"},
+		{0x200, 0x270, "2.Parser control registers"},
+		{0x400, 0x474, "3.ACL control registers"},
+		{0x600, 0x718, "4.Lookup control registers"},
+		{0x800, 0xb70, "5.QM control registers"},
+		{0xc00, 0xc80, "6.PKT edit control registers"},
+		{0x820, 0x820, "7.QM debug registers"}
+	};
+
+	a_uint32_t dump_addr, reg_count, reg_val = 0;
+	switch (register_idx)
+	{
+		case 0:
+		case 1:
+		case 2:
+		case 3:
+		case 4:
+		case 5:
+		case 6:
+			reg_count = 0;
+			for (dump_addr = reg_dumps[register_idx].reg_base; dump_addr <= reg_dumps[register_idx].reg_end; reg_count++)
+			{
+				rv = dess_reg_get(dev_id, dump_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t));
+				reg_dump->reg_value[reg_count] = reg_val;
+				dump_addr += 4;
+			}
+			reg_dump->reg_count = reg_count;
+			reg_dump->reg_base = reg_dumps[register_idx].reg_base;
+			reg_dump->reg_end = reg_dumps[register_idx].reg_end;
+			snprintf((char *)reg_dump->reg_name,sizeof(reg_dump->reg_name),"%s",reg_dumps[register_idx].name);
+			break;
+		default:
+			return SW_BAD_PARAM;
+	}
+
+    return rv;
+}
+
+static sw_error_t
+_dess_debug_regsiter_dump(a_uint32_t dev_id,fal_debug_reg_dump_t * dbg_reg_dump)
+{
+    sw_error_t rv = SW_OK;
+    a_uint32_t reg;
+	a_uint32_t  reg_count, reg_val = 0;
+
+	reg_count = 0;
+
+	for(reg=0;reg<=0x1F;reg++)
+	{
+		dess_reg_set(dev_id, 0x820, (a_uint8_t *) & reg, sizeof (a_uint32_t));
+		rv = dess_reg_get(dev_id, 0x824, (a_uint8_t *) & reg_val, sizeof (a_uint32_t));
+		dbg_reg_dump->reg_value[reg_count] = reg_val;
+		dbg_reg_dump->reg_addr[reg_count] = reg;
+		reg_count++;
+	}
+	dbg_reg_dump->reg_count = reg_count;
+
+	snprintf((char *)dbg_reg_dump->reg_name,sizeof(dbg_reg_dump->reg_name),"QM debug registers");
+    return rv;
+}
+static sw_error_t
+_dess_debug_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable,
+					a_uint32_t times, a_uint32_t * result)
+{
+	sw_error_t rv = SW_OK;
+	ssdk_psgmii_self_test(dev_id, enable, times, result);
+	clear_self_test_config(dev_id);
+
+	return rv;
+}
+
+static sw_error_t
+_dess_phy_dump(a_uint32_t dev_id, a_uint32_t phy_addr,
+		a_uint32_t idx, fal_phy_dump_t * phy_dump)
+{
+	sw_error_t rv = SW_OK;
+	typedef struct {
+		a_uint32_t phy_base;
+		a_uint32_t phy_end;
+		char name[30];
+	} phydump;
+
+	phydump dump[2] =
+	{
+		{0x0, 0x1f, "0.mii registers"},
+		{0x0, 0x3f, "1.debug registers"},
+	};
+
+	a_uint32_t mmd1[] = {0x0,0x5,0x8,0x1800,0x1801,0x1802,0x1803,0x1804,
+		0x1805,0x1806,0x1807,0x1808,0x9000,0x9001,0x9002,0x9003,
+		0x9004,0x9905,0x9006,0x9007,0x9008,0x9009,0x900a,0x900b};
+	char mmd1name[30] = {"2.mmd1 register"};
+
+	a_uint32_t mmd3[] = {0x0,0x1,0x5,0x8,0x14,0x16,0x8001,0x8002,
+		0x8003,0x8004,0x8005,0x8006,0x8007,0x8008,0x8009,0x800a,
+		0x8045,0x8046,0x8047,0x8048,0x8049,0x804a,0x804b,0x804c,
+		0x804d,0x804e,0x804f};
+	char mmd3name[30] = {"3.mmd3 register"};
+
+	a_uint32_t mmd7[] = {0x0,0x1,0x5,0x16,0x17,0x18,0x19,0x1a,0x1b,
+		0x3c,0x3d,0x8000,0x801a};
+	char mmd7name[30] = {"4.mmd7 register"};
+
+	a_uint32_t reg = 0, phy_count = 0,i = 0;
+	a_uint16_t phy_val = 0;
+	switch (idx)
+	{
+		case 0:
+			for (reg = dump[idx].phy_base; reg <= dump[idx].phy_end; reg++)
+			{
+				rv = dess_phy_get(dev_id, phy_addr, reg, &phy_val);
+				phy_dump->phy_value[phy_count] = phy_val;
+				phy_count ++;
+			}
+			phy_dump->phy_count = phy_count;
+			phy_dump->phy_base = dump[idx].phy_base;
+			phy_dump->phy_end = dump[idx].phy_end;
+			snprintf((char *)phy_dump->phy_name,
+				sizeof(phy_dump->phy_name),"%s",dump[idx].name);
+			break;
+		case 1:
+			for (reg = dump[idx].phy_base; reg <= dump[idx].phy_end; reg++)
+			{
+				rv = dess_phy_set(dev_id, phy_addr, 0x1d, (a_uint16_t)reg);
+				rv = dess_phy_get(dev_id, phy_addr, 0x1e, &phy_val);
+				phy_dump->phy_value[phy_count] = phy_val;
+				phy_count ++;
+			}
+			phy_dump->phy_count = phy_count;
+			phy_dump->phy_base = dump[idx].phy_base;
+			phy_dump->phy_end = dump[idx].phy_end;
+			snprintf((char *)phy_dump->phy_name,
+				sizeof(phy_dump->phy_name),"%s",dump[idx].name);
+			break;
+		case 2:
+			phy_count = sizeof (mmd1)/sizeof(a_uint32_t);
+			for (i = 0; i < phy_count; i++ )
+			{
+				rv = dess_phy_set(dev_id, phy_addr, 0xd, 1);
+				rv = dess_phy_set(dev_id, phy_addr, 0xe, (a_uint16_t)mmd1[i]);
+				rv = dess_phy_set(dev_id, phy_addr, 0xd, 0x4001);
+				rv = dess_phy_get(dev_id, phy_addr, 0xe, &phy_val);
+				phy_dump->phy_value[i] = phy_val;
+			}
+			phy_dump->phy_count = phy_count - 1;
+			phy_dump->phy_base = mmd1[0];
+			phy_dump->phy_end = mmd1[phy_count - 1];
+			snprintf((char *)phy_dump->phy_name,
+				sizeof(phy_dump->phy_name),"%s",mmd1name);
+			break;
+		case 3:
+			phy_count = sizeof (mmd3)/sizeof(a_uint32_t);
+			for (i = 0; i < phy_count; i++ )
+			{
+				rv = dess_phy_set(dev_id, phy_addr, 0xd, 3);
+				rv = dess_phy_set(dev_id, phy_addr, 0xe, (a_uint16_t)mmd3[i]);
+				rv = dess_phy_set(dev_id, phy_addr, 0xd, 0x4003);
+				rv = dess_phy_get(dev_id, phy_addr, 0xe, &phy_val);
+				phy_dump->phy_value[i] = phy_val;
+			}
+			phy_dump->phy_count = phy_count - 1;
+			phy_dump->phy_base = mmd3[0];
+			phy_dump->phy_end = mmd3[phy_count - 1];
+			snprintf((char *)phy_dump->phy_name,
+				sizeof(phy_dump->phy_name),"%s",mmd3name);
+			break;
+		case 4:
+			phy_count = sizeof (mmd7)/sizeof(a_uint32_t);
+			for (i = 0; i < phy_count; i++ )
+			{
+				rv = dess_phy_set(dev_id, phy_addr, 0xd, 7);
+				rv = dess_phy_set(dev_id, phy_addr, 0xe, (a_uint16_t)mmd7[i]);
+				rv = dess_phy_set(dev_id, phy_addr, 0xd, 0x4007);
+				rv = dess_phy_get(dev_id, phy_addr, 0xe, &phy_val);
+				phy_dump->phy_value[i] = phy_val;
+			}
+			phy_dump->phy_count = phy_count - 1;
+			phy_dump->phy_base = mmd7[0];
+			phy_dump->phy_end = mmd7[phy_count - 1];
+			snprintf((char *)phy_dump->phy_name,
+				sizeof(phy_dump->phy_name),"%s",mmd7name);
+			break;
+		default:
+			return SW_BAD_PARAM;
+	}
+
+    return rv;
+}
+
+/**
+ * @brief dump registers.
+ * @param[in] dev_id device id
+ * @param[in] register_idx register group id
+ * @param[out] reg_dump register dump result
+ * @return SW_OK or error code
+ */
+sw_error_t
+dess_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _dess_regsiter_dump(dev_id,register_idx,reg_dump);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief dump registers.
+ * @param[in] dev_id device id
+ * @param[out] reg_dump debug register dump
+ * @return SW_OK or error code
+ */
+sw_error_t
+dess_debug_regsiter_dump(a_uint32_t dev_id, fal_debug_reg_dump_t * dbg_reg_dump)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _dess_debug_regsiter_dump(dev_id,dbg_reg_dump);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+/**
+ * @brief debug psgmii self test.
+ * @param[in] dev_id, enable, times
+ * @param[out] status
+ * @return SW_OK or error code
+ */
+sw_error_t
+dess_debug_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable,
+				a_uint32_t times, a_uint32_t * result)
+
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _dess_debug_psgmii_self_test(dev_id, enable, times, result);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+dess_phy_dump(a_uint32_t dev_id, a_uint32_t phy_addr,
+		a_uint32_t idx, fal_phy_dump_t * phy_dump)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _dess_phy_dump(dev_id, phy_addr, idx, phy_dump);
+    FAL_API_UNLOCK;
+    return rv;
+}
+sw_error_t
+dess_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode)
+{
+    hsl_api_t *p_api;
+
+    MDIO_LOCKER_INIT;
+    reg_mode = mode;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+    p_api->phy_get = dess_phy_get;
+    p_api->phy_set = dess_phy_set;
+    p_api->reg_get = dess_reg_get;
+    p_api->reg_set = dess_reg_set;
+    p_api->reg_field_get = dess_reg_field_get;
+    p_api->reg_field_set = dess_reg_field_set;
+   #ifdef IN_INTERFACECONTROL
+    p_api->psgmii_reg_get = dess_psgmii_reg_get;
+    p_api->psgmii_reg_set = dess_psgmii_reg_set;
+   #endif
+	p_api->register_dump = dess_regsiter_dump;
+	p_api->debug_register_dump = dess_debug_regsiter_dump;
+	p_api->debug_psgmii_self_test = dess_debug_psgmii_self_test;
+	p_api->phy_dump = dess_phy_dump;
+
+
+    return SW_OK;
+}
+
+sw_error_t
+dess_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode)
+{
+    reg_mode = mode;
+    return SW_OK;
+
+}
+
diff --git a/qca-ssdk/src/hsl/dess/dess_sec.c b/qca-ssdk/src/hsl/dess/dess_sec.c
new file mode 100755
index 0000000..61c7588
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_sec.c
@@ -0,0 +1,787 @@
+/*
+ * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_sec DESS_SEC
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_sec.h"
+#include "dess_reg.h"
+
+#define NORM_CTRL0_ADDR 0x0200
+#define NORM_CTRL1_ADDR 0x0204
+#define NORM_CTRL2_ADDR 0x0208
+#define NORM_CTRL3_ADDR 0x0c00
+
+static sw_error_t
+_dess_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+    fal_fwd_cmd_t cmd;
+    a_bool_t enable;
+    a_uint32_t addr, offset, len, reg = 0, val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    cmd = *((fal_fwd_cmd_t *) value);
+    enable = *((a_bool_t *) value);
+    val = *((a_uint32_t *) value);
+
+    len = 1;
+    switch (item)
+    {
+        case FAL_NORM_MAC_RESV_VID_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 0;
+            goto cmd_chk;
+
+        case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 20;
+            goto cmd_chk;
+
+        case FAL_NORM_IP_INVALID_VER_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 1;
+            goto cmd_chk;
+
+        case FAL_NROM_IP_SAME_ADDR_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 2;
+            goto cmd_chk;
+            break;
+
+        case FAL_NROM_IP_TTL_CHANGE_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 11;
+            goto sts_chk;
+
+        case FAL_NROM_IP_TTL_VALUE:
+            addr = NORM_CTRL3_ADDR;
+            offset = 12;
+            len = 8;
+            goto set_reg;
+
+        case FAL_NROM_IP4_INVALID_HL_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 3;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_HDR_OPTIONS_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 4;
+            len = 2;
+            goto s_cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_DF_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 7;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 8;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE:
+            addr = NORM_CTRL1_ADDR;
+            offset = 24;
+            len = 8;
+            goto set_reg;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 9;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 10;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_SIP_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 11;
+            len = 1;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_DIP_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 12;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 13;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_PL_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 19;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_DF_CLEAR_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 9;
+            goto sts_chk;
+
+        case FAL_NROM_IP4_IPID_RANDOM_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 10;
+            goto sts_chk;
+
+        case FAL_NROM_IP6_INVALID_DIP_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 16;
+            goto cmd_chk;
+
+        case FAL_NROM_IP6_INVALID_SIP_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 17;
+            goto cmd_chk;
+
+        case FAL_NROM_IP6_INVALID_PL_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 18;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_BLAT_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 14;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_INVALID_HL_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 15;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_MIN_HDR_SIZE:
+            addr = NORM_CTRL1_ADDR;
+            offset = 12;
+            len = 4;
+            goto set_reg;
+
+        case FAL_NROM_TCP_INVALID_SYN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 16;
+            goto cmd_chk;
+            break;
+
+        case FAL_NROM_TCP_SU_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 17;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SP_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 18;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SAP_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 19;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_XMAS_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 20;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_NULL_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 21;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SR_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 22;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SF_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 23;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SAR_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 24;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_RST_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 25;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SYN_WITH_DATA_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 26;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_RST_WITH_DATA_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 27;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_FA_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 28;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_PA_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 29;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_UA_BLOCK_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 0;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 1;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_INVALID_URGPTR_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 2;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_INVALID_OPTIONS_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 3;
+            goto cmd_chk;
+
+        case FAL_NROM_UDP_BLAT_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 4;
+            goto cmd_chk;
+
+        case FAL_NROM_UDP_INVALID_LEN_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 5;
+            goto cmd_chk;
+
+        case FAL_NROM_UDP_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 6;
+            goto cmd_chk;
+
+        case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 7;
+            goto cmd_chk;
+
+        case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 8;
+            goto cmd_chk;
+
+        case FAL_NROM_ICMP4_PING_FRAG_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 9;
+            goto cmd_chk;
+
+        case FAL_NROM_ICMP6_PING_FRAG_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 10;
+            goto cmd_chk;
+
+        case FAL_NROM_ICMP4_PING_MAX_PL_VALUE:
+            addr = NORM_CTRL2_ADDR;
+            offset = 0;
+            len = 14;
+            goto set_reg;
+
+        case FAL_NROM_ICMP6_PING_MAX_PL_VALUE:
+            addr = NORM_CTRL2_ADDR;
+            offset = 16;
+            len = 14;
+            goto set_reg;
+
+        default:
+            return SW_BAD_PARAM;
+    }
+
+sts_chk:
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    goto set_reg;
+
+s_cmd_chk:
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_DROP == cmd)
+    {
+        val = 3;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 2;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    goto set_reg;
+
+cmd_chk:
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_DROP == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+set_reg:
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_REG_SET_BY_FIELD_U32(reg, val, offset, len);
+
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+    a_uint32_t addr, offset, len, reg = 0, val;
+    a_uint32_t status_chk = 0, val_chk = 0, scmd_chk = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    len = 1;
+    switch (item)
+    {
+        case FAL_NORM_MAC_RESV_VID_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 0;
+            break;
+
+        case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 20;
+            break;
+
+        case FAL_NORM_IP_INVALID_VER_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 1;
+            break;
+
+        case FAL_NROM_IP_SAME_ADDR_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 2;
+            break;
+
+        case FAL_NROM_IP_TTL_CHANGE_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 11;
+            status_chk = 1;
+            break;
+
+        case FAL_NROM_IP_TTL_VALUE:
+            addr = NORM_CTRL3_ADDR;
+            offset = 12;
+            len = 8;
+            val_chk = 1;
+            break;
+
+        case FAL_NROM_IP4_INVALID_HL_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 3;
+            break;
+
+        case FAL_NROM_IP4_HDR_OPTIONS_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 4;
+            len = 2;
+            scmd_chk = 1;
+            break;
+
+        case FAL_NROM_IP4_INVALID_DF_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 7;
+            break;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 8;
+            break;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE:
+            addr = NORM_CTRL1_ADDR;
+            offset = 24;
+            len = 8;
+            val_chk = 1;
+            break;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 9;
+            break;
+
+        case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 10;
+            break;
+
+        case FAL_NROM_IP4_INVALID_SIP_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 11;
+            len = 1;
+            break;
+
+        case FAL_NROM_IP4_INVALID_DIP_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 12;
+            break;
+
+        case FAL_NROM_IP4_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 13;
+            break;
+
+        case FAL_NROM_IP4_INVALID_PL_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 19;
+            break;
+
+        case FAL_NROM_IP4_DF_CLEAR_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 9;
+            status_chk = 1;
+            break;
+
+        case FAL_NROM_IP4_IPID_RANDOM_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 10;
+            status_chk = 1;
+            break;
+
+        case FAL_NROM_IP6_INVALID_DIP_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 16;
+            break;
+
+        case FAL_NROM_IP6_INVALID_SIP_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 17;
+            break;
+
+        case FAL_NROM_IP6_INVALID_PL_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 18;
+            break;
+
+        case FAL_NROM_TCP_BLAT_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 14;
+            break;
+
+        case FAL_NROM_TCP_INVALID_HL_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 15;
+            break;
+
+        case FAL_NROM_TCP_MIN_HDR_SIZE:
+            addr = NORM_CTRL1_ADDR;
+            offset = 12;
+            len = 4;
+            val_chk = 1;
+            break;
+
+        case FAL_NROM_TCP_INVALID_SYN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 16;
+            break;
+
+        case FAL_NROM_TCP_SU_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 17;
+            break;
+
+        case FAL_NROM_TCP_SP_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 18;
+            break;
+
+        case FAL_NROM_TCP_SAP_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 19;
+            break;
+
+        case FAL_NROM_TCP_XMAS_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 20;
+            break;
+
+        case FAL_NROM_TCP_NULL_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 21;
+            break;
+
+        case FAL_NROM_TCP_SR_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 22;
+            break;
+
+        case FAL_NROM_TCP_SF_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 23;
+            break;
+
+        case FAL_NROM_TCP_SAR_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 24;
+            break;
+
+        case FAL_NROM_TCP_RST_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 25;
+            break;
+
+        case FAL_NROM_TCP_SYN_WITH_DATA_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 26;
+            break;
+
+        case FAL_NROM_TCP_RST_WITH_DATA_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 27;
+            break;
+
+        case FAL_NROM_TCP_FA_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 28;
+            break;
+
+        case FAL_NROM_TCP_PA_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 29;
+            break;
+
+        case FAL_NROM_TCP_UA_BLOCK_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 0;
+            break;
+
+        case FAL_NROM_TCP_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 1;
+            break;
+
+        case FAL_NROM_TCP_INVALID_URGPTR_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 2;
+            break;
+
+        case FAL_NROM_TCP_INVALID_OPTIONS_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 3;
+            break;
+
+        case FAL_NROM_UDP_BLAT_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 4;
+            break;
+
+        case FAL_NROM_UDP_INVALID_LEN_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 5;
+            break;
+
+        case FAL_NROM_UDP_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 6;
+            break;
+
+        case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 7;
+            break;
+
+        case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 8;
+            break;
+
+        case FAL_NROM_ICMP4_PING_FRAG_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 9;
+            break;
+
+        case FAL_NROM_ICMP6_PING_FRAG_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 10;
+            break;
+
+        case FAL_NROM_ICMP4_PING_MAX_PL_VALUE:
+            addr = NORM_CTRL2_ADDR;
+            offset = 0;
+            len = 14;
+            val_chk = 1;
+            break;
+
+        case FAL_NROM_ICMP6_PING_MAX_PL_VALUE:
+            addr = NORM_CTRL2_ADDR;
+            offset = 16;
+            len = 14;
+            val_chk = 1;
+            break;
+
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_FIELD_GET_BY_REG_U32(reg, val, offset, len);
+
+    if (val_chk)
+    {
+        *((a_uint32_t *) value) = val;
+    }
+    else if (status_chk)
+    {
+        if (val)
+        {
+            *((a_bool_t *) value) = A_TRUE;
+        }
+        else
+        {
+            *((a_bool_t *) value) = A_FALSE;
+        }
+    }
+    else if (scmd_chk)
+    {
+        if (2 == val)
+        {
+            *((fal_fwd_cmd_t *) value) = FAL_MAC_RDT_TO_CPU;
+        }
+        else if (3 == val)
+        {
+            *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP;
+        }
+        else
+        {
+            *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD;
+        }
+    }
+    else
+    {
+        if (val)
+        {
+            *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP;
+        }
+        else
+        {
+            *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD;
+        }
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set normalization particular item types value.
+ * @details   Comments:
+ *       This operation will set normalization item values on a particular device.
+ *       The prototye of value based on the item type.
+ * @param[in] dev_id device id
+ * @param[in] item normalizaton item type
+ * @param[in] value normalizaton item value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_sec_norm_item_set(dev_id, item, value);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get normalization particular item types value.
+ * @details   Comments:
+ *       This operation will set normalization item values on a particular device.
+ *       The prototye of value based on the item type.
+ * @param[in] dev_id device id
+ * @param[in] item normalizaton item type
+ * @param[out] value normalizaton item value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_sec_norm_item_get(dev_id, item, value);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+dess_sec_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->sec_norm_item_set = dess_sec_norm_item_set;
+        p_api->sec_norm_item_get = dess_sec_norm_item_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/dess/dess_stp.c b/qca-ssdk/src/hsl/dess/dess_stp.c
new file mode 100755
index 0000000..6537241
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_stp.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_stp DESS_STP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_stp.h"
+#include "dess_reg.h"
+
+#define DESS_PORT_DISABLED      0
+#define DESS_STP_BLOCKING       1
+#define DESS_STP_LISTENING      2
+#define DESS_STP_LEARNING       3
+#define DESS_STP_FARWARDING     4
+
+static sw_error_t
+_dess_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                         fal_port_t port_id, fal_stp_state_t state)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SINGLE_STP_ID != st_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    switch (state)
+    {
+        case FAL_STP_BLOKING:
+            val = DESS_STP_BLOCKING;
+            break;
+        case FAL_STP_LISTENING:
+            val = DESS_STP_LISTENING;
+            break;
+        case FAL_STP_LEARNING:
+            val = DESS_STP_LEARNING;
+            break;
+        case FAL_STP_FARWARDING:
+            val = DESS_STP_FARWARDING;
+            break;
+        case FAL_STP_DISABLED:
+            val =  DESS_PORT_DISABLED;
+            break;
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                         fal_port_t port_id, fal_stp_state_t * state)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SINGLE_STP_ID != st_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    switch (val)
+    {
+        case DESS_STP_BLOCKING:
+            *state = FAL_STP_BLOKING;
+            break;
+        case DESS_STP_LISTENING:
+            *state = FAL_STP_LISTENING;
+            break;
+        case DESS_STP_LEARNING:
+            *state = FAL_STP_LEARNING;
+            break;
+        case DESS_STP_FARWARDING:
+            *state = FAL_STP_FARWARDING;
+            break;
+        case DESS_PORT_DISABLED:
+            *state = FAL_STP_DISABLED;
+            break;
+        default:
+            return SW_FAIL;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set port stp state on a particular spanning tree and port.
+ *   @details   Comments:
+    Garuda only support single spanning tree so st_id should be
+    FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[in] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                        fal_port_t port_id, fal_stp_state_t state)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_stp_port_state_set(dev_id, st_id, port_id, state);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port stp state on a particular spanning tree and port.
+ *   @details  Comments:
+    Garuda only support single spanning tree so st_id should be
+    FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[out] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                        fal_port_t port_id, fal_stp_state_t * state)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_stp_port_state_get(dev_id, st_id, port_id, state);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+dess_stp_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->stp_port_state_set = dess_stp_port_state_set;
+        p_api->stp_port_state_get = dess_stp_port_state_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/dess/dess_trunk.c b/qca-ssdk/src/hsl/dess/dess_trunk.c
new file mode 100755
index 0000000..e57eb0d
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_trunk.c
@@ -0,0 +1,327 @@
+/*
+ * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+ * @defgroup dess_trunk DESS_TRUNK
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_trunk.h"
+#include "dess_reg.h"
+
+#define DESS_MAX_TRUNK_ID    3
+
+enum dess_trunk_reg_id
+{
+    DESS_TRUNK_HASH_EN = 0, /*0x270*/
+    DESS_TRUNK_CTRL_0,        /*0x700*/
+    DESS_TRUNK_CTRL_1,        /*0x704*/
+    DESS_TRUNK_CTRL_2,        /*0x708*/
+    DESS_TRUNK_REG_MAX
+};
+
+static a_uint32_t dess_trunk_regs[DESS_TRUNK_REG_MAX] =
+{
+    0xf, 0x0, 0x0, 0x0
+};
+
+static sw_error_t
+_dess_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+                      a_bool_t enable, fal_pbmp_t member)
+{
+    sw_error_t rv;
+    a_uint32_t i, reg = 0, cnt = 0, data0 = 0, data1 = 0;
+
+    if (DESS_MAX_TRUNK_ID < trunk_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data0 = (0x1 << 7) | member;
+
+        for (i = 0; i < 7; i++)
+        {
+            if (member & (0x1 << i))
+            {
+                if (4 <= cnt)
+                {
+                    return SW_BAD_PARAM;
+                }
+
+                data1 |= (i << (cnt << 2));
+                data1 |= (1 << (3 + (cnt << 2)));
+                cnt++;
+            }
+        }
+    }
+    else if (A_FALSE == enable)
+    {
+
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    /* set trunk port member bitmap info */
+    HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    reg &= (~(0xff << (trunk_id << 3)));
+    reg |= (data0 << (trunk_id << 3));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    dess_trunk_regs[DESS_TRUNK_CTRL_0] = reg;
+
+    /* set trunk port member id info */
+    HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1),
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    reg &= (~(0xffff << ((trunk_id % 2) << 4)));
+    reg |= (data1 << ((trunk_id % 2) << 4));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1),
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    dess_trunk_regs[DESS_TRUNK_CTRL_1 + (trunk_id >> 1)] = reg;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+                      a_bool_t * enable, fal_pbmp_t * member)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg = 0;
+
+    if (DESS_MAX_TRUNK_ID < trunk_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (reg >> (trunk_id << 3)) & 0xff;
+    if (0x80 & data)
+    {
+        *enable = A_TRUE;
+        *member = data & 0x7f;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *member = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (FAL_TRUNK_HASH_KEY_DA & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DA_EN, 1, data);
+    }
+
+    if (FAL_TRUNK_HASH_KEY_SA & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SA_EN, 1, data);
+    }
+
+    if (FAL_TRUNK_HASH_KEY_DIP & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DIP_EN, 1, data);
+    }
+
+    if (FAL_TRUNK_HASH_KEY_SIP & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SIP_EN, 1, data);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, TRUNK_HASH_MODE, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    dess_trunk_regs[DESS_TRUNK_HASH_EN] = data;
+
+    return rv;
+}
+
+static sw_error_t
+_dess_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, TRUNK_HASH_MODE, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *hash_mode = 0;
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DA_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_DA;
+    }
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SA_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_SA;
+    }
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DIP_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_DIP;
+    }
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SIP_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_SIP;
+    }
+
+    return SW_OK;
+}
+
+
+/**
+ * @brief Set particular trunk group information on particular device.
+ * @param[in] dev_id device id
+ * @param[in] trunk_id trunk group id
+ * @param[in] enable trunk group status, enable or disable
+ * @param[in] member port member information
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+                     a_bool_t enable, fal_pbmp_t member)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_trunk_group_set(dev_id, trunk_id, enable, member);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get particular trunk group information on particular device.
+ * @param[in] dev_id device id
+ * @param[in] trunk_id trunk group id
+ * @param[out] enable trunk group status, enable or disable
+ * @param[out] member port member information
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+                     a_bool_t * enable, fal_pbmp_t * member)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_trunk_group_get(dev_id, trunk_id, enable, member);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set trunk hash mode on particular device.
+ * @details   Comments:
+    hash mode is listed below
+    FAL_TRUNK_HASH_KEY_DA, FAL_TRUNK_HASH_KEY_SA, FAL_TRUNK_HASH_KEY_DIP and FAL_TRUNK_HASH_KEY_SIP
+ * @param[in] dev_id device id
+ * @param[in] hash_mode trunk hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_trunk_hash_mode_set(dev_id, hash_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get trunk hash mode on particular device.
+ * @param[in] dev_id device id
+ * @param[out] hash_mode trunk hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_trunk_hash_mode_get(dev_id, hash_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+sw_error_t
+dess_trunk_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->trunk_group_set = dess_trunk_group_set;
+        p_api->trunk_group_get = dess_trunk_group_get;
+        p_api->trunk_hash_mode_set = dess_trunk_hash_mode_set;
+        p_api->trunk_hash_mode_get = dess_trunk_hash_mode_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/dess/dess_vlan.c b/qca-ssdk/src/hsl/dess/dess_vlan.c
new file mode 100755
index 0000000..2923cb3
--- /dev/null
+++ b/qca-ssdk/src/hsl/dess/dess_vlan.c
@@ -0,0 +1,906 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_vlan DESS_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "dess_vlan.h"
+#include "dess_reg.h"
+
+#define MAX_VLAN_ID         4095
+
+#define VLAN_FLUSH          1
+#define VLAN_LOAD_ENTRY     2
+#define VLAN_PURGE_ENTRY    3
+#define VLAN_REMOVE_PORT    4
+#define VLAN_NEXT_ENTRY     5
+#define VLAN_FIND_ENTRY     6
+
+static void
+_dess_vlan_hw_to_sw(a_uint32_t reg[], fal_vlan_t * vlan_entry)
+{
+    a_uint32_t i, data, tmp;
+
+    aos_mem_zero(vlan_entry, sizeof (fal_vlan_t));
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VLAN_ID, data, reg[1]);
+    vlan_entry->vid = data & 0xfff;
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]);
+    if (1 == data)
+    {
+        vlan_entry->fid = vlan_entry->vid;
+    }
+    else
+    {
+        vlan_entry->fid = FAL_SVL_FID;
+    }
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]);
+    if (1 == data)
+    {
+        vlan_entry->learn_dis = A_TRUE;
+    }
+    else
+    {
+        vlan_entry->learn_dis = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]);
+    if (1 == data)
+    {
+        vlan_entry->vid_pri_en = A_TRUE;
+
+        SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]);
+        vlan_entry->vid_pri = data & 0xff;
+    }
+    else
+    {
+        vlan_entry->vid_pri_en = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]);
+    for (i = 0; i < 7; i++)
+    {
+        tmp = (data >> (i << 1)) & 0x3UL;
+        if (0 == tmp)
+        {
+            vlan_entry->mem_ports |= (0x1UL << i);
+            vlan_entry->unmodify_ports |= (0x1UL << i);
+        }
+        else if (1 == tmp)
+        {
+            vlan_entry->mem_ports |= (0x1UL << i);
+            vlan_entry->untagged_ports |= (0x1UL << i);
+        }
+        else if (2 == tmp)
+        {
+            vlan_entry->mem_ports |= (0x1UL << i);
+            vlan_entry->tagged_ports |= (0x1UL << i);
+        }
+    }
+
+    return;
+}
+
+static sw_error_t
+_dess_vlan_sw_to_hw(a_uint32_t dev_id, const fal_vlan_t * vlan_entry,
+                    a_uint32_t reg[])
+{
+    a_uint32_t i, tag, untag, unmodify, member = 0;
+
+    if (vlan_entry->vid > MAX_VLAN_ID)
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    if (A_FALSE ==
+            hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]);
+
+    if (FAL_SVL_FID == vlan_entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]);
+    }
+    else if (vlan_entry->vid == vlan_entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]);
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (A_TRUE == vlan_entry->learn_dis)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]);
+    }
+
+    for (i = 0; i < 7; i++)
+    {
+        if ((vlan_entry->mem_ports >> i) & 0x1UL)
+        {
+            tag = (vlan_entry->tagged_ports >> i) & 0x1UL;
+            untag = (vlan_entry->untagged_ports >> i) & 0x1UL;
+            unmodify = (vlan_entry->unmodify_ports >> i) & 0x1UL;
+
+            if ((0 == (tag + untag + unmodify))
+                    || (1 < (tag + untag + unmodify)))
+            {
+                return SW_BAD_VALUE;
+            }
+
+            if (tag)
+            {
+                member |= (2 << (i << 1));
+            }
+            else if (untag)
+            {
+                member |= (1 << (i << 1));
+            }
+        }
+        else
+        {
+            member |= (3 << (i << 1));
+        }
+    }
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, member, reg[0]);
+
+    if (A_TRUE == vlan_entry->vid_pri_en)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]);
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri,
+                            reg[0]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]);
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_entry->vid, reg[1]);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_vlan_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_vlan_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_dess_vlan_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val;
+    sw_error_t rv;
+
+    while (vt_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY,
+                          (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_BUSY;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_FUNC, op, val);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_BUSY, 1, val);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    vt_busy = 1;
+    i = 0x1000;
+    while (vt_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY,
+                          (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_FAIL;
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_FULL_VIO,
+                      (a_uint8_t *) (&vt_full), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (vt_full)
+    {
+        val = 0x10;
+        HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        if (VLAN_LOAD_ENTRY == op)
+        {
+            return SW_FULL;
+        }
+        else if (VLAN_PURGE_ENTRY == op)
+        {
+            return SW_NOT_FOUND;
+        }
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_VALID,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (!val)
+    {
+        if (VLAN_FIND_ENTRY == op)
+            return SW_NOT_FOUND;
+
+        if (VLAN_NEXT_ENTRY == op)
+            return SW_NO_MORE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_vlan_hwentry_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+
+    if (vlan_id > MAX_VLAN_ID)
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_vlan_up_to_sw(dev_id, reg);
+    return rv;
+}
+
+static sw_error_t
+_dess_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_vlan_sw_to_hw(dev_id, vlan_entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_vlan_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_dess_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (vlan_id > MAX_VLAN_ID)
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, 0x3fff, reg[0]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]);
+
+    rv = _dess_vlan_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_dess_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == vlan_id)
+    {
+        rv = _dess_vlan_hwentry_get(dev_id, 0, reg);
+
+        if (SW_OK == rv)
+        {
+            _dess_vlan_hw_to_sw(reg, p_vlan);
+            return SW_OK;
+        }
+        else
+        {
+            vlan_id = 0;
+        }
+    }
+
+    if (vlan_id > MAX_VLAN_ID)
+        return SW_OUT_OF_RANGE;
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_vlan_commit(dev_id, VLAN_NEXT_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_vlan_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    _dess_vlan_hw_to_sw(reg, p_vlan);
+
+    if (0 == p_vlan->vid)
+    {
+        return SW_NO_MORE;
+    }
+    else
+    {
+        return SW_OK;
+    }
+}
+
+static sw_error_t
+_dess_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    _dess_vlan_hw_to_sw(reg, p_vlan);
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (vlan_id > MAX_VLAN_ID)
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    reg = (a_int32_t) vlan_id;
+    HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VLAN_ID,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_vlan_commit(dev_id, VLAN_PURGE_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_dess_vlan_flush(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_vlan_commit(dev_id, VLAN_FLUSH);
+    return rv;
+}
+
+static sw_error_t
+_dess_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((MAX_VLAN_ID < fid) && (FAL_SVL_FID != fid))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((MAX_VLAN_ID >= fid) && (vlan_id != fid))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _dess_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_SVL_FID == fid)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]);
+    }
+
+    rv = _dess_vlan_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    if (SW_FULL == rv)
+    {
+        rv = SW_OK;
+    }
+    return rv;
+}
+
+static sw_error_t
+_dess_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]);
+    if (data)
+    {
+        *fid = vlan_id;
+    }
+    else
+    {
+        *fid = FAL_SVL_FID;
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+_dess_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                         fal_port_t port_id, a_uint32_t port_info)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _dess_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]);
+    data &= (~(0x3 << (port_id << 1)));
+    data |= ((port_info & 0x3) << (port_id << 1));
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]);
+
+    rv = _dess_vlan_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    if (SW_FULL == rv)
+    {
+        rv = SW_OK;
+    }
+    return rv;
+}
+
+static sw_error_t
+_dess_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+                      fal_port_t port_id, fal_pt_1q_egmode_t port_info)
+{
+    sw_error_t rv;
+    a_uint32_t info = 0;
+
+    if (FAL_EG_UNMODIFIED == port_info)
+    {
+        info = 0;
+    }
+    else if (FAL_EG_TAGGED == port_info)
+    {
+        info = 0x2;
+    }
+    else if (FAL_EG_UNTAGGED == port_info)
+    {
+        info = 0x1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _dess_vlan_member_update(dev_id, vlan_id, port_id, info);
+    return rv;
+}
+
+static sw_error_t
+_dess_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t info = 0x3;
+
+    rv = _dess_vlan_member_update(dev_id, vlan_id, port_id, info);
+    return rv;
+}
+
+static sw_error_t
+_dess_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _dess_vlan_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _dess_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    if (SW_FULL == rv)
+    {
+        rv = SW_OK;
+    }
+    return rv;
+}
+
+static sw_error_t
+_dess_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _dess_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]);
+    if (data)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+    return SW_OK;
+}
+
+/**
+ * @brief Append a vlan entry on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_entry vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_vlan_entry_append(dev_id, vlan_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Creat a vlan entry through vlan id on a paticular device.
+ *   @details   Comments:
+ *    After this operation the member ports of the created vlan entry are null.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_vlan_create(dev_id, vlan_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next a vlan entry through vlan id on a paticular device.
+ *   @details   Comments:
+ *    If the value of vid is zero this operation will get the first entry.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_vlan_next(dev_id, vlan_id, p_vlan);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a vlan entry through vlan id on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_vlan_find(dev_id, vlan_id, p_vlan);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a vlan entry through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_vlan_delete(dev_id, vlan_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Flush all vlan entries on a paticular device.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_vlan_flush(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_vlan_flush(dev_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] fid FDB id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_vlan_fid_set(dev_id, vlan_id, fid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] fid FDB id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_vlan_fid_get(dev_id, vlan_id, fid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a port member to a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @param[in] port_info port tag information
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+                     fal_port_t port_id, fal_pt_1q_egmode_t port_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_vlan_member_add(dev_id, vlan_id, port_id, port_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Del a port member from a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_vlan_member_del(dev_id, vlan_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_vlan_learning_state_set(dev_id, vlan_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+dess_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _dess_vlan_learning_state_get(dev_id, vlan_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+dess_vlan_init(a_uint32_t dev_id)
+{
+    hsl_api_t *p_api;
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->vlan_entry_append = dess_vlan_entry_append;
+    p_api->vlan_creat = dess_vlan_create;
+    p_api->vlan_delete = dess_vlan_delete;
+    p_api->vlan_next = dess_vlan_next;
+    p_api->vlan_find = dess_vlan_find;
+    p_api->vlan_flush = dess_vlan_flush;
+    p_api->vlan_fid_set = dess_vlan_fid_set;
+    p_api->vlan_fid_get = dess_vlan_fid_get;
+    p_api->vlan_member_add = dess_vlan_member_add;
+    p_api->vlan_member_del = dess_vlan_member_del;
+    p_api->vlan_learning_state_set = dess_vlan_learning_state_set;
+    p_api->vlan_learning_state_get = dess_vlan_learning_state_get;
+
+
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/garuda/Makefile b/qca-ssdk/src/hsl/garuda/Makefile
new file mode 100755
index 0000000..67ebb12
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/Makefile
@@ -0,0 +1,84 @@
+LOC_DIR=src/hsl/garuda
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=garuda_reg_access.c garuda_init.c
+
+ifeq (TRUE, $(IN_ACL))
+  SRC_LIST += garuda_acl.c
+endif
+
+ifeq (TRUE, $(IN_FDB))
+  SRC_LIST += garuda_fdb.c
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+  SRC_LIST += garuda_igmp.c
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+  SRC_LIST += garuda_leaky.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+  SRC_LIST += garuda_led.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+  SRC_LIST += garuda_mib.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+  SRC_LIST += garuda_mirror.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+  SRC_LIST += garuda_misc.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+  SRC_LIST += garuda_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+  SRC_LIST += garuda_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+  SRC_LIST += garuda_qos.c
+endif
+
+ifeq (TRUE, $(IN_RATE))
+  SRC_LIST += garuda_rate.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+  SRC_LIST += garuda_stp.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+  SRC_LIST += garuda_vlan.c
+endif
+
+ifeq (TRUE, $(IN_REDUCED_ACL))
+  SRC_LIST += garuda_reduced_acl.c
+endif
+
+ifeq (linux, $(OS))
+	ifeq (KSLIB, $(MODULE_TYPE))
+    ifneq (TRUE, $(KERNEL_MODE))
+      SRC_LIST=garuda_reg_access.c garuda_init.c
+	  endif
+	endif
+endif
+
+ifeq (, $(findstring GARUDA, $(SUPPORT_CHIP)))
+  SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/qca-ssdk/src/hsl/garuda/garuda_acl.c b/qca-ssdk/src/hsl/garuda/garuda_acl.c
new file mode 100755
index 0000000..216468f
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_acl.c
@@ -0,0 +1,3034 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+ * @defgroup garuda_acl GARUDA_ACL
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+#include "hsl_port_prop.h"
+#include "garuda_acl.h"
+#include "garuda_reg.h"
+
+//#define GARUDA_ACL_DEBUG
+//#define GARUDA_SW_ENTRY
+//#define GARUDA_ENTRY_DUMP
+
+typedef struct
+{
+    a_uint32_t list_id;
+    a_uint32_t list_pri;
+    a_uint32_t addr;
+    a_uint32_t size;
+    a_uint32_t status;
+    fal_pbmp_t bind_pts;
+} garuda_acl_list_t;
+
+typedef struct
+{
+    a_uint32_t slct[8];
+    a_uint32_t vlu[5];
+    a_uint32_t msk[5];
+    a_uint32_t typ;
+    a_uint32_t act;
+} garuda_acl_hw_rule_t;
+
+static garuda_acl_list_t *list_ent[SW_MAX_NR_DEV];
+static garuda_acl_hw_rule_t *hw_rule_ent;
+
+static a_uint32_t filter[SW_MAX_NR_DEV];
+static a_uint32_t filter_snap[SW_MAX_NR_DEV];
+
+#define GARUDA_MAX_LIST 32
+#define GARUDA_MAX_RULE 32
+
+#define ENT_FREE        0x1
+#define ENT_USED        0x2
+
+#define GARUDA_RULE_VLU_ADDR  0x58400
+#define GARUDA_RULE_MSK_ADDR  0x58c00
+#define GARUDA_RULE_TYP_ADDR  0x5881c
+#define GARUDA_RULE_ACT_ADDR  0x58000
+#define GARUDA_RULE_SLCT_ADDR 0x58800
+
+#define GARUDA_MAC_FILTER       1
+#define GARUDA_IP4_FILTER       2
+#define GARUDA_IP6R1_FILTER     3
+#define GARUDA_IP6R2_FILTER     4
+#define GARUDA_IP6R3_FILTER     5
+
+#ifdef GARUDA_SW_ENTRY
+static char *flt_vlu_mem = NULL;
+static char *flt_msk_mem = NULL;
+static char *flt_typ_mem = NULL;
+static char *act_mem = NULL;
+static char *slct_mem = NULL;
+#endif
+
+static a_bool_t _garuda_acl_zero_addr(const fal_mac_addr_t addr);
+
+static a_bool_t
+_garuda_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask,
+                       a_uint32_t chkvlu);
+
+static sw_error_t
+_garuda_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t * idx);
+
+static sw_error_t
+_garuda_acl_filter_map_get(const garuda_acl_hw_rule_t * rule,
+                           a_uint32_t flt_idx[], a_uint32_t * flt_nr);
+
+static sw_error_t
+_garuda_acl_rule_mac_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+                           garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+                           a_uint32_t * len);
+
+static sw_error_t
+_garuda_acl_rule_ip4_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+                           garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+                           a_uint32_t * len);
+
+static sw_error_t
+_garuda_acl_rule_ip6r1_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+                             garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+                             a_uint32_t * len);
+
+static sw_error_t
+_garuda_acl_rule_ip6r2_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+                             garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+                             a_uint32_t * len);
+
+static sw_error_t
+_garuda_acl_rule_ip6r3_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+                             garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+                             a_uint32_t * len);
+
+static sw_error_t
+_garuda_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw,
+                         garuda_acl_hw_rule_t * hw);
+
+static sw_error_t
+_garuda_acl_rule_mac_reparse(fal_acl_rule_t * sw,
+                             const garuda_acl_hw_rule_t * hw);
+
+static sw_error_t
+_garuda_acl_rule_ip4_reparse(fal_acl_rule_t * sw,
+                             const garuda_acl_hw_rule_t * hw);
+
+static sw_error_t
+_garuda_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw,
+                               const garuda_acl_hw_rule_t * hw);
+
+static sw_error_t
+_garuda_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw,
+                               const garuda_acl_hw_rule_t * hw);
+
+static sw_error_t
+_garuda_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw,
+                               const garuda_acl_hw_rule_t * hw);
+
+static sw_error_t
+_garuda_acl_rule_action_reparse(fal_acl_rule_t * sw,
+                                const garuda_acl_hw_rule_t * hw);
+
+static sw_error_t
+_garuda_acl_filter_alloc(a_uint32_t dev_id, a_uint32_t * idx);
+
+static void
+_garuda_acl_filter_free(a_uint32_t dev_id, a_uint32_t idx);
+
+static void
+_garuda_acl_filter_snap(a_uint32_t dev_id);
+
+static void
+_garuda_acl_filter_commit(a_uint32_t dev_id);
+
+static sw_error_t
+_garuda_acl_slct_update(garuda_acl_hw_rule_t * hw, a_uint32_t offset,
+                        a_uint32_t flt_idx);
+
+static sw_error_t
+_garuda_acl_filter_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule,
+                         a_uint32_t flt_idx);
+
+static sw_error_t
+_garuda_acl_action_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule,
+                         a_uint32_t act_idx);
+
+static sw_error_t
+_garuda_acl_slct_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule,
+                       a_uint32_t slct_idx);
+
+static sw_error_t
+_garuda_acl_filter_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+                        a_uint32_t flt_idx);
+
+static sw_error_t
+_garuda_acl_action_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+                        a_uint32_t act_idx);
+
+static sw_error_t
+_garuda_acl_slct_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+                      a_uint32_t slct_idx);
+
+static sw_error_t
+_garuda_acl_rule_set(a_uint32_t dev_id, a_uint32_t base_addr,
+                     const garuda_acl_hw_rule_t * hw_rule_ent,
+                     a_uint32_t rule_nr);
+
+static sw_error_t
+_garuda_acl_rule_get(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+                     a_uint32_t * ent_idx, a_uint32_t rule_idx);
+
+static sw_error_t
+_garuda_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+                          fal_pbmp_t bind_pts, garuda_acl_hw_rule_t * hw,
+                          a_uint32_t * idx, a_uint32_t * flt_len);
+
+static sw_error_t
+_garuda_acl_rule_hw_to_sw(fal_acl_rule_t * sw, const garuda_acl_hw_rule_t * hw,
+                          a_uint32_t ent_idx, a_uint32_t ent_nr);
+
+static sw_error_t
+_garuda_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_slct_idx,
+                      a_uint32_t dst_slct_idx, a_uint32_t size);
+
+static sw_error_t
+_garuda_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t rule_idx,
+                         a_uint32_t size);
+
+static sw_error_t
+_garuda_acl_rule_valid(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t size,
+                       a_uint32_t flag);
+
+static sw_error_t
+_garuda_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr,
+                        a_uint32_t new_addr, a_uint32_t list_id);
+
+static sw_error_t
+_garuda_acl_rule_bind(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t ports);
+
+#ifdef GARUDA_ACL_DEBUG
+static void
+_garuda_acl_list_dump(a_uint32_t dev_id)
+{
+    a_uint32_t i;
+
+    aos_printk("\ndev_id=%d  list control infomation", dev_id);
+    for (i = 0; i < GARUDA_MAX_LIST; i++)
+    {
+        if (ENT_USED == list_ent[dev_id][i].status)
+        {
+            aos_printk("\nlist_id=%d  list_pri=%d  addr=%d  size=%d  idx=%d ",
+                       list_ent[dev_id][i].list_id,
+                       list_ent[dev_id][i].list_pri,
+                       list_ent[dev_id][i].addr, list_ent[dev_id][i].size, i);
+        }
+    }
+    aos_printk("\n");
+}
+#else
+#define _garuda_acl_list_dump(dev_id)
+#endif
+
+static a_bool_t
+_garuda_acl_zero_addr(const fal_mac_addr_t addr)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 6; i++)
+    {
+        if (addr.uc[i])
+        {
+            return A_FALSE;
+        }
+    }
+    return A_TRUE;
+}
+
+static a_bool_t
+_garuda_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask,
+                       a_uint32_t chkvlu)
+{
+    if (FAL_ACL_FIELD_MASK == op)
+    {
+        if (0 == mask)
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_RANGE == op)
+    {
+        if ((0 == val) && (chkvlu == mask))
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_LE == op)
+    {
+        if (chkvlu == val)
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_GE == op)
+    {
+        if (0 == val)
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_NE == op)
+    {
+        return A_TRUE;
+    }
+
+    return A_TRUE;
+}
+
+static sw_error_t
+_garuda_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t * idx)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < GARUDA_MAX_LIST; i++)
+    {
+        if ((ENT_USED == list_ent[dev_id][i].status)
+                && (list_id == list_ent[dev_id][i].list_id))
+        {
+            *idx = i;
+            return SW_OK;
+        }
+    }
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_garuda_acl_filter_map_get(const garuda_acl_hw_rule_t * rule,
+                           a_uint32_t flt_idx[], a_uint32_t * flt_nr)
+{
+    a_uint32_t flt_en, idx, i = 0;
+
+    SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR0_EN, flt_en, (rule->slct[0]));
+    if (flt_en)
+    {
+        SW_GET_FIELD_BY_REG(RUL_SLCT1, ADDR0, idx, (rule->slct[1]));
+        flt_idx[i] = idx;
+        i++;
+    }
+
+    SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR1_EN, flt_en, (rule->slct[0]));
+    if (flt_en)
+    {
+        SW_GET_FIELD_BY_REG(RUL_SLCT2, ADDR1, idx, (rule->slct[2]));
+        flt_idx[i] = idx;
+        i++;
+    }
+
+    SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR2_EN, flt_en, (rule->slct[0]));
+    if (flt_en)
+    {
+        SW_GET_FIELD_BY_REG(RUL_SLCT3, ADDR2, idx, (rule->slct[3]));
+        flt_idx[i] = idx;
+        i++;
+    }
+
+    SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR3_EN, flt_en, (rule->slct[0]));
+    if (flt_en)
+    {
+        SW_GET_FIELD_BY_REG(RUL_SLCT4, ADDR3, idx, (rule->slct[4]));
+        flt_idx[i] = idx;
+        i++;
+    }
+
+    *flt_nr = i;
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_mac_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+                           garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+                           a_uint32_t * len)
+{
+    a_uint32_t i;
+
+    *b_care = A_FALSE;
+    *len = 0;
+
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+    aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+
+    SW_SET_REG_BY_FIELD(MAC_RUL_V4, MAC_INPT, bind_pts, hw->vlu[4]);
+    SW_SET_REG_BY_FIELD(RUL_TYPE, TYP, GARUDA_MAC_FILTER, hw->typ);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+    {
+        if (A_TRUE != _garuda_acl_zero_addr(sw->dest_mac_mask))
+        {
+            *b_care = A_TRUE;
+            *len = 6;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+        }
+
+        SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2],
+                            hw->vlu[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3],
+                            hw->vlu[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4],
+                            hw->vlu[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5],
+                            hw->vlu[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0],
+                            hw->vlu[1]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1],
+                            hw->vlu[1]);
+
+        SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2],
+                            hw->msk[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3],
+                            hw->msk[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4],
+                            hw->msk[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5],
+                            hw->msk[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0],
+                            hw->msk[1]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1],
+                            hw->msk[1]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+    {
+        if (A_TRUE != _garuda_acl_zero_addr(sw->src_mac_mask))
+        {
+            *b_care = A_TRUE;
+            *len = 12;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+        }
+
+        SW_SET_REG_BY_FIELD(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4],
+                            hw->vlu[1]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5],
+                            hw->vlu[1]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0],
+                            hw->vlu[2]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1],
+                            hw->vlu[2]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2],
+                            hw->vlu[2]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3],
+                            hw->vlu[2]);
+
+        SW_SET_REG_BY_FIELD(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4],
+                            hw->msk[1]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5],
+                            hw->msk[1]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0],
+                            hw->msk[2]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1],
+                            hw->msk[2]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2],
+                            hw->msk[2]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3],
+                            hw->msk[2]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+    {
+        if (0x0 != sw->ethtype_mask)
+        {
+            *b_care = A_TRUE;
+            *len = 14;
+        }
+
+        sw->ethtype_val &= sw->ethtype_mask;
+        SW_SET_REG_BY_FIELD(MAC_RUL_V3, ETHTYPV, sw->ethtype_val, hw->vlu[3]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask, hw->msk[3]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED))
+    {
+        if (0x0 != sw->tagged_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->tagged_val &= sw->tagged_mask;
+        SW_SET_REG_BY_FIELD(MAC_RUL_V4, TAGGEDV, sw->tagged_val, hw->vlu[4]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V4, TAGGEDM, sw->tagged_mask, hw->vlu[4]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP))
+    {
+        if (0x0 != sw->up_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->up_val &= sw->up_mask;
+        SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANPRIV, sw->up_val, hw->vlu[3]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANPRIM, sw->up_mask, hw->msk[3]);
+    }
+
+    SW_SET_REG_BY_FIELD(MAC_RUL_M3, VIDMSK, 1, hw->msk[3]);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->vid_op)
+                && (FAL_ACL_FIELD_RANGE != sw->vid_op)
+                && (FAL_ACL_FIELD_LE != sw->vid_op)
+                && (FAL_ACL_FIELD_GE != sw->vid_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_TRUE ==
+                _garuda_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask,
+                                       0xfff))
+        {
+            *b_care = A_TRUE;
+        }
+
+        SW_SET_REG_BY_FIELD(MAC_RUL_M3, VIDMSK, 0, hw->msk[3]);
+        if (FAL_ACL_FIELD_MASK == sw->vid_op)
+        {
+            sw->vid_val &= sw->vid_mask;
+            SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]);
+            SW_SET_REG_BY_FIELD(MAC_RUL_M3, VIDMSK, 1, hw->msk[3]);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->vid_op)
+        {
+            SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->vid_op)
+        {
+            SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, 0, hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_val, hw->msk[3]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, 0xfff, hw->msk[3]);
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip4_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+                           garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+                           a_uint32_t * len)
+{
+    *b_care = A_FALSE;
+    *len = 0;
+
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+    aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+
+    SW_SET_REG_BY_FIELD(IP4_RUL_V4, IP4_INPT, bind_pts, hw->vlu[4]);
+    SW_SET_REG_BY_FIELD(RUL_TYPE, TYP, GARUDA_IP4_FILTER, hw->typ);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+    {
+        if (0x0 != sw->ip_dscp_mask)
+        {
+            *b_care = A_TRUE;
+            *len = 16;
+        }
+
+        sw->ip_dscp_val &= sw->ip_dscp_mask;
+        SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val, hw->vlu[2]);
+        SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask, hw->msk[2]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+    {
+        if (0x0 != sw->ip_proto_mask)
+        {
+            *b_care = A_TRUE;
+            *len = 24;
+        }
+
+        sw->ip_proto_val &= sw->ip_proto_mask;
+        SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val, hw->vlu[2]);
+        SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask,
+                            hw->msk[2]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_SIP))
+    {
+        if (0x0 != sw->src_ip4_mask)
+        {
+            *b_care = A_TRUE;
+            *len = 30;
+        }
+        sw->src_ip4_val &= sw->src_ip4_mask;
+        hw->vlu[1] = sw->src_ip4_val;
+        hw->msk[1] = sw->src_ip4_mask;
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_DIP))
+    {
+        if (0x0 != sw->dest_ip4_mask)
+        {
+            *b_care = A_TRUE;
+            *len = 34;
+        }
+        sw->dest_ip4_val &= sw->dest_ip4_mask;
+        hw->vlu[0] = sw->dest_ip4_val;
+        hw->msk[0] = sw->dest_ip4_mask;
+    }
+
+    SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 1, hw->msk[3]);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_TRUE ==
+                _garuda_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+                                       sw->src_l4port_mask, 0xffff))
+        {
+            *b_care = A_TRUE;
+            *len = 36;
+        }
+
+        SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 0, hw->msk[3]);
+        if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+        {
+            sw->src_l4port_val &= sw->src_l4port_mask;
+            SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val,
+                                hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask,
+                                hw->msk[3]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 1, hw->msk[3]);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val,
+                                hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask,
+                                hw->msk[3]);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, 0, hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_val,
+                                hw->msk[3]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val,
+                                hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, 0xffff, hw->msk[3]);
+        }
+    }
+
+    SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 1, hw->msk[3]);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_TRUE ==
+                _garuda_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+                                       sw->dest_l4port_mask, 0xffff))
+        {
+            *b_care = A_TRUE;
+            *len = 38;
+        }
+
+        SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 0, hw->msk[3]);
+        if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+        {
+            sw->dest_l4port_val &= sw->dest_l4port_mask;
+            SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val,
+                                hw->vlu[2]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask,
+                                hw->msk[2]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 1, hw->msk[3]);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val,
+                                hw->vlu[2]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask,
+                                hw->msk[2]);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, 0, hw->vlu[2]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_val,
+                                hw->msk[2]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val,
+                                hw->vlu[2]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, 0xffff, hw->msk[2]);
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip6r1_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+                             garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+                             a_uint32_t * len)
+{
+    a_uint32_t i;
+
+    *b_care = A_FALSE;
+    *len = 0;
+
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+    aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+
+    SW_SET_REG_BY_FIELD(IP6_RUL1_V4, IP6_RUL1_INPT, bind_pts, hw->vlu[4]);
+    SW_SET_REG_BY_FIELD(RUL_TYPE, TYP, GARUDA_IP6R1_FILTER, hw->typ);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_DIP))
+    {
+        for (i = 0; i < 4; i++)
+        {
+            if (0x0 != sw->dest_ip6_mask.ul[i])
+            {
+                *b_care = A_TRUE;
+                *len = 54;
+            }
+
+            sw->dest_ip6_val.ul[3 - i] &= sw->dest_ip6_mask.ul[3 - i];
+            hw->vlu[i] = sw->dest_ip6_val.ul[3 - i];
+            hw->msk[i] = sw->dest_ip6_mask.ul[3 - i];
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip6r2_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+                             garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+                             a_uint32_t * len)
+{
+    a_uint32_t i;
+
+    *b_care = A_FALSE;
+    *len = 0;
+
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+    aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+
+    SW_SET_REG_BY_FIELD(IP6_RUL2_V4, IP6_RUL2_INPT, bind_pts, hw->vlu[4]);
+    SW_SET_REG_BY_FIELD(RUL_TYPE, TYP, GARUDA_IP6R2_FILTER, hw->typ);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_SIP))
+    {
+        for (i = 0; i < 4; i++)
+        {
+            if (0x0 != sw->src_ip6_mask.ul[i])
+            {
+                *b_care = A_TRUE;
+                *len = 38;
+            }
+
+            sw->src_ip6_val.ul[3 - i] &= sw->src_ip6_mask.ul[3 - i];
+            hw->vlu[i] = sw->src_ip6_val.ul[3 - i];
+            hw->msk[i] = sw->src_ip6_mask.ul[3 - i];
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip6r3_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+                             garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+                             a_uint32_t * len)
+{
+    *b_care = A_FALSE;
+    *len = 0;
+
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+    aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+
+    SW_SET_REG_BY_FIELD(IP6_RUL3_V4, IP6_RUL3_INPT, bind_pts, hw->vlu[4]);
+    SW_SET_REG_BY_FIELD(RUL_TYPE, TYP, GARUDA_IP6R3_FILTER, hw->typ);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+    {
+        if (0x0 != sw->ip_dscp_mask)
+        {
+            *b_care = A_TRUE;
+            *len = 38;
+        }
+
+        sw->ip_dscp_val &= sw->ip_dscp_mask;
+        SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val, hw->vlu[0]);
+        SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask,
+                            hw->msk[0]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL))
+    {
+        if (0x0 != sw->ip6_lable_mask)
+        {
+            *b_care = A_TRUE;
+            *len = 18;
+        }
+
+        sw->ip6_lable_val &= sw->ip6_lable_mask;
+        SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val,
+                            hw->vlu[1]);
+        SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask,
+                            hw->msk[1]);
+
+        SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6LABEL2V, (sw->ip6_lable_val >> 16),
+                            hw->vlu[2]);
+        SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6LABEL2M, (sw->ip6_lable_mask >> 16),
+                            hw->msk[2]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+    {
+        if (0x0 != sw->ip_proto_mask)
+        {
+            *b_care = A_TRUE;
+            *len = 21;
+        }
+
+        sw->ip_proto_val &= sw->ip_proto_mask;
+        SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val,
+                            hw->vlu[0]);
+        SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask,
+                            hw->msk[0]);
+    }
+
+    SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 1, hw->msk[3]);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_TRUE ==
+                _garuda_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+                                       sw->src_l4port_mask, 0xffff))
+        {
+            *b_care = A_TRUE;
+            *len = 56;
+        }
+
+        SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 0, hw->msk[3]);
+        if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+        {
+            sw->src_l4port_val &= sw->src_l4port_mask;
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6SPORTV, sw->src_l4port_val,
+                                hw->vlu[1]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6SPORTM, sw->src_l4port_mask,
+                                hw->msk[1]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 1, hw->msk[3]);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6SPORTV, sw->src_l4port_val,
+                                hw->vlu[1]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6SPORTM, sw->src_l4port_mask,
+                                hw->msk[1]);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6SPORTV, 0, hw->vlu[1]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6SPORTM, sw->src_l4port_val,
+                                hw->msk[1]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6SPORTV, sw->src_l4port_val,
+                                hw->vlu[1]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6SPORTM, 0xffff, hw->msk[1]);
+        }
+    }
+
+    SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 1, hw->msk[3]);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_TRUE ==
+                _garuda_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+                                       sw->dest_l4port_mask, 0xffff))
+        {
+            *b_care = A_TRUE;
+            *len = 58;
+        }
+
+        SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 0, hw->msk[3]);
+        if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+        {
+            sw->dest_l4port_val &= sw->dest_l4port_mask;
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DPORTV, sw->dest_l4port_val,
+                                hw->vlu[0]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DPORTM, sw->dest_l4port_mask,
+                                hw->msk[0]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 1, hw->msk[3]);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DPORTV, sw->dest_l4port_val,
+                                hw->vlu[0]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DPORTM, sw->dest_l4port_mask,
+                                hw->msk[0]);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DPORTV, 0, hw->vlu[0]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DPORTM, sw->dest_l4port_val,
+                                hw->msk[0]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DPORTV, sw->dest_l4port_val,
+                                hw->vlu[0]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DPORTM, 0xffff, hw->msk[0]);
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw,
+                         garuda_acl_hw_rule_t * hw)
+{
+    hw->act = 0;
+    if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+            && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN)))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    /* FAL_ACL_ACTION_PERMIT need't process */
+
+    /* we should ignore any other action flags when DENY bit is settd. */
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_DENY))
+    {
+        SW_SET_REG_BY_FIELD(ACL_RSLT, DES_PORT_EN, 1, hw->act);
+        SW_SET_REG_BY_FIELD(ACL_RSLT, PORT_MEM, 0, hw->act);
+        return SW_OK;
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU))
+    {
+        SW_SET_REG_BY_FIELD(ACL_RSLT, RDTCPU, 1, hw->act);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU))
+    {
+        SW_SET_REG_BY_FIELD(ACL_RSLT, CPYCPU, 1, hw->act);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MIRROR))
+    {
+        SW_SET_REG_BY_FIELD(ACL_RSLT, MIRR_EN, 1, hw->act);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT))
+    {
+        SW_SET_REG_BY_FIELD(ACL_RSLT, DES_PORT_EN, 1, hw->act);
+        SW_SET_REG_BY_FIELD(ACL_RSLT, PORT_MEM, sw->ports, hw->act);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_UP))
+    {
+        SW_SET_REG_BY_FIELD(ACL_RSLT, REMARK_DOT1P, 1, hw->act);
+        SW_SET_REG_BY_FIELD(ACL_RSLT, DOT1P, sw->up, hw->act);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE))
+    {
+        SW_SET_REG_BY_FIELD(ACL_RSLT, REMARK_PRI_QU, 1, hw->act);
+        SW_SET_REG_BY_FIELD(ACL_RSLT, PRI_QU, sw->queue, hw->act);
+    }
+
+    if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+            || (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN)))
+    {
+
+        SW_SET_REG_BY_FIELD(ACL_RSLT, CHG_VID_EN, 1, hw->act);
+        SW_SET_REG_BY_FIELD(ACL_RSLT, VID, sw->vid, hw->act);
+        SW_SET_REG_BY_FIELD(ACL_RSLT, STAG_CHG_EN, 1, hw->act);
+        if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+        {
+            SW_SET_REG_BY_FIELD(ACL_RSLT, STAG_CHG_EN, 0, hw->act);
+
+            if (!FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT))
+            {
+                SW_SET_REG_BY_FIELD(ACL_RSLT, VID_MEM_EN, 1, hw->act);
+                SW_SET_REG_BY_FIELD(ACL_RSLT, PORT_MEM, sw->ports, hw->act);
+            }
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_mac_reparse(fal_acl_rule_t * sw,
+                             const garuda_acl_hw_rule_t * hw)
+{
+    a_uint32_t mask_en;
+
+    /* destnation mac address */
+    SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2],
+                        hw->vlu[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3],
+                        hw->vlu[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4],
+                        hw->vlu[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5],
+                        hw->vlu[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0],
+                        hw->vlu[1]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1],
+                        hw->vlu[1]);
+
+    SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2],
+                        hw->msk[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3],
+                        hw->msk[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4],
+                        hw->msk[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5],
+                        hw->msk[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0],
+                        hw->msk[1]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1],
+                        hw->msk[1]);
+    if (A_FALSE == _garuda_acl_zero_addr(sw->dest_mac_mask))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+    }
+
+    /* source mac address */
+    SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0],
+                        hw->vlu[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1],
+                        hw->vlu[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2],
+                        hw->vlu[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3],
+                        hw->vlu[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4],
+                        hw->vlu[1]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5],
+                        hw->vlu[1]);
+
+    SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0],
+                        hw->msk[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1],
+                        hw->msk[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2],
+                        hw->msk[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3],
+                        hw->msk[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4],
+                        hw->msk[1]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5],
+                        hw->msk[1]);
+    if (A_FALSE == _garuda_acl_zero_addr(sw->src_mac_mask))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+    }
+
+    /* ethernet type */
+    SW_GET_FIELD_BY_REG(MAC_RUL_V3, ETHTYPV, sw->ethtype_val, hw->vlu[3]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask, hw->msk[3]);
+    if (0x0 != sw->ethtype_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+    }
+
+    /* packet tagged */
+    SW_GET_FIELD_BY_REG(MAC_RUL_V4, TAGGEDV, sw->tagged_val, hw->vlu[4]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V4, TAGGEDM, sw->tagged_mask, hw->vlu[4]);
+    if (0x0 != sw->tagged_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED);
+    }
+
+    /* vlan priority */
+    SW_GET_FIELD_BY_REG(MAC_RUL_V3, VLANPRIV, sw->up_val, hw->vlu[3]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M3, VLANPRIM, sw->up_mask, hw->msk[3]);
+    if (0x0 != sw->up_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_UP);
+    }
+
+    /* vlanid */
+    SW_GET_FIELD_BY_REG(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M3, VIDMSK, mask_en, hw->msk[3]);
+    if (mask_en)
+    {
+        sw->vid_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->vid_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _garuda_acl_field_care(sw->vid_op, (a_uint32_t) sw->vid_val,
+                                   (a_uint32_t) sw->vid_mask, 0xfff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_VID);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip4_reparse(fal_acl_rule_t * sw,
+                             const garuda_acl_hw_rule_t * hw)
+{
+    a_uint32_t mask_en;
+
+    sw->dest_ip4_val = hw->vlu[0];
+    sw->dest_ip4_mask = hw->msk[0];
+    if (0x0 != sw->dest_ip4_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_DIP);
+    }
+
+    sw->src_ip4_val = hw->vlu[1];
+    sw->src_ip4_mask = hw->msk[1];
+    if (0x0 != sw->src_ip4_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_SIP);
+    }
+
+    SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val, hw->vlu[2]);
+    SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask, hw->msk[2]);
+    if (0x0 != sw->ip_proto_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+    }
+
+    SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val, hw->vlu[2]);
+    SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask, hw->msk[2]);
+    if (0x0 != sw->ip_dscp_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+    }
+
+    SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val, hw->vlu[2]);
+    SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask,
+                        hw->msk[2]);
+    SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4DPORTM_EN, mask_en, hw->msk[3]);
+    if (mask_en)
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _garuda_acl_field_care(sw->dest_l4port_op,
+                                   (a_uint32_t) sw->dest_l4port_val,
+                                   (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+
+    SW_GET_FIELD_BY_REG(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val, hw->vlu[3]);
+    SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask, hw->msk[3]);
+    SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4SPORTM_EN, mask_en, hw->msk[3]);
+    if (mask_en)
+    {
+        sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _garuda_acl_field_care(sw->src_l4port_op,
+                                   (a_uint32_t) sw->src_l4port_val,
+                                   (a_uint32_t) sw->src_l4port_mask, 0xffff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw,
+                               const garuda_acl_hw_rule_t * hw)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 4; i++)
+    {
+        sw->dest_ip6_val.ul[i] = hw->vlu[3 - i];
+        sw->dest_ip6_mask.ul[i] = hw->msk[3 - i];
+        if (0x0 != sw->dest_ip6_mask.ul[i])
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_DIP);
+        }
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw,
+                               const garuda_acl_hw_rule_t * hw)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 4; i++)
+    {
+        sw->src_ip6_val.ul[i] = hw->vlu[3 - i];
+        sw->src_ip6_mask.ul[i] = hw->msk[3 - i];
+        if (0x0 != sw->src_ip6_mask.ul[i])
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_SIP);
+        }
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw,
+                               const garuda_acl_hw_rule_t * hw)
+{
+    a_uint32_t mask_en;
+    a_uint32_t tmp;
+
+    SW_GET_FIELD_BY_REG(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val, hw->vlu[0]);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask, hw->msk[0]);
+    if (0x0 != sw->ip_proto_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+    }
+
+    SW_GET_FIELD_BY_REG(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val, hw->vlu[0]);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask, hw->msk[0]);
+    if (0x0 != sw->ip_dscp_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+    }
+
+    SW_GET_FIELD_BY_REG(IP6_RUL3_V0, IP6DPORTV, sw->dest_l4port_val,
+                        hw->vlu[0]);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M0, IP6DPORTM, sw->dest_l4port_mask,
+                        hw->msk[0]);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M3, IP6DPORTM_EN, mask_en, hw->msk[3]);
+    if (mask_en)
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _garuda_acl_field_care(sw->dest_l4port_op,
+                                   (a_uint32_t) sw->dest_l4port_val,
+                                   (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+
+    SW_GET_FIELD_BY_REG(IP6_RUL3_V1, IP6SPORTV, sw->src_l4port_val, hw->vlu[1]);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M1, IP6SPORTM, sw->src_l4port_mask,
+                        hw->msk[1]);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M3, IP6SPORTM_EN, mask_en, hw->msk[3]);
+    if (mask_en)
+    {
+        sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _garuda_acl_field_care(sw->src_l4port_op,
+                                   (a_uint32_t) sw->src_l4port_val,
+                                   (a_uint32_t) sw->src_l4port_mask, 0xffff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+    }
+
+    SW_GET_FIELD_BY_REG(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val, hw->vlu[1]);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask,
+                        hw->msk[1]);
+
+    SW_GET_FIELD_BY_REG(IP6_RUL3_V2, IP6LABEL2V, tmp, hw->vlu[2]);
+    sw->ip6_lable_val |= (tmp << 16);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M2, IP6LABEL2M, tmp, hw->msk[2]);
+    sw->ip6_lable_mask |= (tmp << 16);
+
+    if (0x0 != sw->ip6_lable_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_action_reparse(fal_acl_rule_t * sw,
+                                const garuda_acl_hw_rule_t * hw)
+{
+    a_uint32_t data;
+
+    sw->action_flg = 0;
+    SW_GET_FIELD_BY_REG(ACL_RSLT, DES_PORT_EN, data, (hw->act));
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(ACL_RSLT, PORT_MEM, data, (hw->act));
+        sw->ports = data;
+
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REDPT);
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_RSLT, RDTCPU, data, (hw->act));
+    if (1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_RDTCPU);
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_RSLT, CPYCPU, data, (hw->act));
+    if (1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_CPYCPU);
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_RSLT, MIRR_EN, data, (hw->act));
+    if (1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MIRROR);
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_RSLT, REMARK_DOT1P, data, (hw->act));
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(ACL_RSLT, DOT1P, data, (hw->act));
+        sw->up = data & 0x7;
+
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_UP);
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_RSLT, REMARK_PRI_QU, data, (hw->act));
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(ACL_RSLT, PRI_QU, data, (hw->act));
+        sw->queue = data & 0x3;
+
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE);
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_RSLT, CHG_VID_EN, data, (hw->act));
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(ACL_RSLT, STAG_CHG_EN, data, (hw->act));
+        if (1 == data)
+        {
+            FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN);
+        }
+        else
+        {
+            FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN);
+            SW_GET_FIELD_BY_REG(ACL_RSLT, PORT_MEM, data, (hw->act));
+            sw->ports = data;
+        }
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_RSLT, VID, data, (hw->act));
+    sw->vid = data & 0xfff;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_filter_alloc(a_uint32_t dev_id, a_uint32_t * idx)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < GARUDA_MAX_RULE; i++)
+    {
+        if (0 == (filter_snap[dev_id] & (0x1UL << i)))
+        {
+            filter_snap[dev_id] |= (0x1UL << i);
+            *idx = i;
+            return SW_OK;
+        }
+    }
+    return SW_NO_RESOURCE;
+}
+
+static void
+_garuda_acl_filter_free(a_uint32_t dev_id, a_uint32_t idx)
+{
+    filter_snap[dev_id] &= (~(0x1UL << idx));
+}
+
+static void
+_garuda_acl_filter_snap(a_uint32_t dev_id)
+{
+    filter_snap[dev_id] = filter[dev_id];
+    return;
+}
+
+static void
+_garuda_acl_filter_commit(a_uint32_t dev_id)
+{
+    filter[dev_id] = filter_snap[dev_id];
+    return;
+}
+
+static sw_error_t
+_garuda_acl_slct_update(garuda_acl_hw_rule_t * hw, a_uint32_t offset,
+                        a_uint32_t flt_idx)
+{
+    switch (offset)
+    {
+        case 0:
+            SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR0_EN, 1, hw->slct[0]);
+            SW_SET_REG_BY_FIELD(RUL_SLCT1, ADDR0, flt_idx, hw->slct[1]);
+            break;
+
+        case 1:
+            SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR1_EN, 1, hw->slct[0]);
+            SW_SET_REG_BY_FIELD(RUL_SLCT2, ADDR1, flt_idx, hw->slct[2]);
+            break;
+
+        case 2:
+            SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR2_EN, 1, hw->slct[0]);
+            SW_SET_REG_BY_FIELD(RUL_SLCT3, ADDR2, flt_idx, hw->slct[3]);
+            break;
+
+        case 3:
+            SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR3_EN, 1, hw->slct[0]);
+            SW_SET_REG_BY_FIELD(RUL_SLCT4, ADDR3, flt_idx, hw->slct[4]);
+            break;
+
+        default:
+            return SW_FAIL;
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_filter_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule,
+                         a_uint32_t flt_idx)
+{
+#ifdef GARUDA_SW_ENTRY
+    char *memaddr;
+    a_uint32_t i;
+
+    memaddr = flt_vlu_mem + (flt_idx << 5);
+    aos_mem_copy(memaddr, (char *) &(rule->vlu[0]), 20);
+
+    memaddr = flt_msk_mem + (flt_idx << 5);
+    aos_mem_copy(memaddr, (char *) &(rule->msk[0]), 20);
+
+    memaddr = flt_typ_mem + (flt_idx << 5);
+    aos_mem_copy(memaddr, (char *) &(rule->typ), 4);
+
+#else
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    /* set filter value */
+    base = GARUDA_RULE_VLU_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(rule->vlu[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* set filter mask */
+    base = GARUDA_RULE_MSK_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(rule->msk[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* set filter type */
+    addr = GARUDA_RULE_TYP_ADDR + (flt_idx << 5);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(rule->typ)), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef GARUDA_ENTRY_DUMP
+    aos_printk("\n_garuda_acl_filter_write flt_idx = %d\n", flt_idx);
+    for (i = 0; i < 5; i++)
+    {
+        aos_printk("%08x  ", rule->vlu[i]);
+    }
+    aos_printk("\n");
+    for (i = 0; i < 5; i++)
+    {
+        aos_printk("%08x  ", rule->msk[i]);
+    }
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_action_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule,
+                         a_uint32_t act_idx)
+{
+#ifdef GARUDA_SW_ENTRY
+    char *memaddr;
+
+    memaddr = act_mem + (act_idx << 5);
+    aos_mem_copy(memaddr, (char *) &(rule->act), 4);
+
+#else
+    sw_error_t rv;
+    a_uint32_t addr;
+
+    /* set rule action */
+    addr = GARUDA_RULE_ACT_ADDR + (act_idx << 5);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(rule->act)), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef GARUDA_ENTRY_DUMP
+    aos_printk("\n_garuda_acl_action_write act_idx = %d    ", act_idx);
+    aos_printk("%08x  ", rule->act);
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_slct_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule,
+                       a_uint32_t slct_idx)
+{
+#ifdef GARUDA_SW_ENTRY
+    char *memaddr;
+    a_uint32_t i;
+
+    memaddr = slct_mem + (slct_idx << 5);
+    aos_mem_copy(memaddr, (char *) &(rule->slct[0]), 32);
+
+#else
+    sw_error_t rv;
+    a_uint32_t base, addr;
+    a_uint32_t i;
+
+    base = GARUDA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+    /* set filter length */
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, (base + 24), sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(rule->slct[6])),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* set filter address */
+    for (i = 1; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(rule->slct[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* set filter enable */
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(rule->slct[0])),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef GARUDA_ENTRY_DUMP
+    aos_printk("\n_garuda_acl_slct_write slct_idx = %d\n", slct_idx);
+    for (i = 0; i < 8; i++)
+    {
+        aos_printk("%08x  ", rule->slct[i]);
+    }
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_filter_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+                        a_uint32_t flt_idx)
+{
+#ifdef GARUDA_SW_ENTRY
+    char *memaddr;
+    a_uint32_t i;
+
+    memaddr = flt_vlu_mem + (flt_idx << 5);
+    aos_mem_copy((char *) &(rule->vlu[0]), memaddr, 20);
+
+    memaddr = flt_msk_mem + (flt_idx << 5);
+    aos_mem_copy((char *) &(rule->msk[0]), memaddr, 20);
+
+    memaddr = flt_typ_mem + (flt_idx << 5);
+    aos_mem_copy((char *) &(rule->typ), memaddr, 4);
+
+#else
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    /* get filter value */
+    base = GARUDA_RULE_VLU_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(rule->vlu[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* get filter mask */
+    base = GARUDA_RULE_MSK_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(rule->msk[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* get filter type */
+    addr = GARUDA_RULE_TYP_ADDR + (flt_idx << 5);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(rule->typ)), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef GARUDA_ENTRY_DUMP
+    aos_printk("\n_garuda_acl_filter_read flt_idx = %d\n", flt_idx);
+    for (i = 0; i < 5; i++)
+    {
+        aos_printk("%08x  ", rule->vlu[i]);
+    }
+    aos_printk("\n");
+    for (i = 0; i < 5; i++)
+    {
+        aos_printk("%08x  ", rule->msk[i]);
+    }
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_action_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+                        a_uint32_t act_idx)
+{
+#ifdef GARUDA_SW_ENTRY
+    char *memaddr;
+
+    memaddr = act_mem + (act_idx << 5);
+    aos_mem_copy((char *) &(rule->act), memaddr, 4);
+
+#else
+    sw_error_t rv;
+    a_uint32_t addr;
+
+    /* get rule action */
+    addr = GARUDA_RULE_ACT_ADDR + (act_idx << 5);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(rule->act)), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef GARUDA_ENTRY_DUMP
+    aos_printk("\n_garuda_acl_action_read act_idx = %d    ", act_idx);
+    aos_printk("%08x  ", rule->act);
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_slct_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+                      a_uint32_t slct_idx)
+{
+#ifdef GARUDA_SW_ENTRY
+    char *memaddr;
+    a_uint32_t i;
+
+    memaddr = slct_mem + (slct_idx << 5);
+    aos_mem_copy((char *) &(rule->slct[0]), memaddr, 32);
+
+#else
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    base = GARUDA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+    /* get filter type */
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, (base + 28), sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(rule->slct[7])),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* get filter length */
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, (base + 24), sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(rule->slct[6])),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* get filter address and enable */
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(rule->slct[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+#endif
+
+#ifdef GARUDA_ENTRY_DUMP
+    aos_printk("\n_garuda_acl_slct_read slct_idx = %d\n", slct_idx);
+    for (i = 0; i < 8; i++)
+    {
+        aos_printk("%08x  ", rule->slct[i]);
+    }
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_set(a_uint32_t dev_id, a_uint32_t base_addr,
+                     const garuda_acl_hw_rule_t * rule, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+    a_uint32_t ent_idx, tmp_ent_idx;
+    a_uint32_t i, flt_nr, flt_idx[4];
+    a_uint32_t act_idx, slct_idx;
+
+    act_idx = base_addr;
+    slct_idx = base_addr;
+    ent_idx = 0;
+    for (i = 0; i < rule_nr; i++)
+    {
+        tmp_ent_idx = ent_idx;
+
+        rv = _garuda_acl_filter_map_get(&rule[ent_idx], flt_idx, &flt_nr);
+        SW_RTN_ON_ERROR(rv);
+
+        if (!flt_nr)
+        {
+            return SW_FAIL;
+        }
+
+        for (i = 0; i < flt_nr; i++)
+        {
+            rv = _garuda_acl_filter_write(dev_id, &(rule[ent_idx]), flt_idx[i]);
+            ent_idx++;
+        }
+
+        rv = _garuda_acl_action_write(dev_id, &(rule[tmp_ent_idx]), act_idx);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _garuda_acl_slct_write(dev_id, &(rule[tmp_ent_idx]), slct_idx);
+        SW_RTN_ON_ERROR(rv);
+
+        act_idx++;
+        slct_idx++;
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_get(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+                     a_uint32_t * ent_idx, a_uint32_t rule_idx)
+{
+    sw_error_t rv;
+    a_uint32_t i, tmp_idx, flt_nr, flt_idx[4];
+
+    tmp_idx = *ent_idx;
+
+    rv = _garuda_acl_slct_read(dev_id, &rule[tmp_idx], rule_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _garuda_acl_action_read(dev_id, &rule[tmp_idx], rule_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _garuda_acl_filter_map_get(&rule[tmp_idx], flt_idx, &flt_nr);
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < flt_nr; i++)
+    {
+        rv = _garuda_acl_filter_read(dev_id, &rule[tmp_idx], flt_idx[i]);
+        SW_RTN_ON_ERROR(rv);
+
+        tmp_idx++;
+    }
+
+    *ent_idx = tmp_idx;
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+                          fal_pbmp_t bind_pts, garuda_acl_hw_rule_t * hw,
+                          a_uint32_t * idx, a_uint32_t * flt_len)
+{
+    sw_error_t rv;
+    a_bool_t b_care;
+    a_bool_t b_valid = A_FALSE;
+    a_uint32_t tmp_idx;
+    a_uint32_t len1 = 0, len2 = 0, len3 = 0, maxlen = 0;
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_UDF))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    tmp_idx = *idx;
+    if (FAL_ACL_RULE_MAC == sw->rule_type)
+    {
+        rv = _garuda_acl_rule_mac_parse(sw, bind_pts, &hw[tmp_idx], &b_care,
+                                        &len1);
+        SW_RTN_ON_ERROR(rv);
+        tmp_idx++;
+
+        if (0 == len1)
+        {
+            *flt_len = 14;
+        }
+        else
+        {
+            *flt_len = len1;
+        }
+    }
+    else if (FAL_ACL_RULE_IP4 == sw->rule_type)
+    {
+        rv = _garuda_acl_rule_mac_parse(sw, bind_pts, &hw[tmp_idx], &b_care,
+                                        &len1);
+        SW_RTN_ON_ERROR(rv);
+        if (A_TRUE == b_care)
+        {
+            tmp_idx++;
+        }
+
+        rv = _garuda_acl_rule_ip4_parse(sw, bind_pts, &hw[tmp_idx], &b_care,
+                                        &len1);
+        SW_RTN_ON_ERROR(rv);
+        tmp_idx++;
+
+        if (0 == len1)
+        {
+            *flt_len = 34;
+        }
+        else
+        {
+            *flt_len = len1;
+        }
+    }
+    else if (FAL_ACL_RULE_IP6 == sw->rule_type)
+    {
+        rv = _garuda_acl_rule_mac_parse(sw, bind_pts, &hw[tmp_idx], &b_care,
+                                        &len1);
+        SW_RTN_ON_ERROR(rv);
+        if (A_TRUE == b_care)
+        {
+            tmp_idx++;
+        }
+
+        rv = _garuda_acl_rule_ip6r1_parse(sw, bind_pts, &hw[tmp_idx], &b_care,
+                                          &len1);
+        SW_RTN_ON_ERROR(rv);
+        if (A_TRUE == b_care)
+        {
+            tmp_idx++;
+            b_valid = A_TRUE;
+        }
+
+        rv = _garuda_acl_rule_ip6r2_parse(sw, bind_pts, &hw[tmp_idx], &b_care,
+                                          &len2);
+        SW_RTN_ON_ERROR(rv);
+        if (A_TRUE == b_care)
+        {
+            tmp_idx++;
+            b_valid = A_TRUE;
+        }
+
+        rv = _garuda_acl_rule_ip6r3_parse(sw, bind_pts, &hw[tmp_idx], &b_care,
+                                          &len3);
+        SW_RTN_ON_ERROR(rv);
+        if ((A_TRUE == b_care) || (A_FALSE == b_valid))
+        {
+            tmp_idx++;
+        }
+
+        if (len1 >= len2)
+        {
+            if (len1 >= len3)
+            {
+                maxlen = len1;
+            }
+            else
+            {
+                maxlen = len3;
+            }
+        }
+        else
+        {
+            if (len2 >= len3)
+            {
+                maxlen = len2;
+            }
+            else
+            {
+                maxlen = len3;
+            }
+        }
+
+        if (0 == maxlen)
+        {
+            *flt_len = 54;
+        }
+        else
+        {
+            *flt_len = maxlen;
+        }
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    rv = _garuda_acl_action_parse(dev_id, sw, &(hw_rule_ent[*idx]));
+    SW_RTN_ON_ERROR(rv);
+
+    *idx = tmp_idx;
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_hw_to_sw(fal_acl_rule_t * sw, const garuda_acl_hw_rule_t * hw,
+                          a_uint32_t ent_idx, a_uint32_t ent_nr)
+{
+    sw_error_t rv;
+    a_uint32_t i, flt_typ;
+    a_bool_t b_ip4 = A_FALSE, b_ip6 = A_FALSE;
+
+    rv = _garuda_acl_rule_action_reparse(sw, &hw[ent_idx]);
+    SW_RTN_ON_ERROR(rv);
+
+    sw->rule_type = FAL_ACL_RULE_MAC;
+    for (i = 0; i < ent_nr; i++)
+    {
+        SW_GET_FIELD_BY_REG(RUL_TYPE, TYP, flt_typ, hw[ent_idx + i].typ);
+
+        if (GARUDA_MAC_FILTER == flt_typ)
+        {
+            rv = _garuda_acl_rule_mac_reparse(sw, &hw[ent_idx + i]);
+            SW_RTN_ON_ERROR(rv);
+        }
+        else if (GARUDA_IP4_FILTER == flt_typ)
+        {
+            rv = _garuda_acl_rule_ip4_reparse(sw, &hw[ent_idx + i]);
+            SW_RTN_ON_ERROR(rv);
+            b_ip4 = A_TRUE;
+        }
+        else if (GARUDA_IP6R1_FILTER == flt_typ)
+        {
+            rv = _garuda_acl_rule_ip6r1_reparse(sw, &hw[ent_idx + i]);
+            SW_RTN_ON_ERROR(rv);
+            b_ip6 = A_TRUE;
+        }
+        else if (GARUDA_IP6R2_FILTER == flt_typ)
+        {
+            rv = _garuda_acl_rule_ip6r2_reparse(sw, &hw[ent_idx + i]);
+            SW_RTN_ON_ERROR(rv);
+            b_ip6 = A_TRUE;
+        }
+        else if (GARUDA_IP6R3_FILTER == flt_typ)
+        {
+            rv = _garuda_acl_rule_ip6r3_reparse(sw, &hw[ent_idx + i]);
+            SW_RTN_ON_ERROR(rv);
+            b_ip6 = A_TRUE;
+        }
+        else
+        {
+            return SW_FAIL;
+        }
+    }
+
+    if (A_TRUE == b_ip4)
+    {
+        sw->rule_type = FAL_ACL_RULE_IP4;
+    }
+
+    if (A_TRUE == b_ip6)
+    {
+        sw->rule_type = FAL_ACL_RULE_IP6;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_slct_idx,
+                      a_uint32_t dst_slct_idx, a_uint32_t size)
+{
+    sw_error_t rv;
+    a_uint32_t i;
+    a_int32_t step, src_idx, dst_idx;
+    garuda_acl_hw_rule_t rule;
+
+    if (dst_slct_idx <= src_slct_idx)
+    {
+        src_idx = src_slct_idx & 0x7fffffff;
+        dst_idx = dst_slct_idx & 0x7fffffff;
+        step = 1;
+    }
+    else
+    {
+        src_idx = (src_slct_idx + size - 1) & 0x7fffffff;
+        dst_idx = (dst_slct_idx + size - 1) & 0x7fffffff;
+        step = -1;
+    }
+
+    aos_mem_zero(&rule, sizeof (garuda_acl_hw_rule_t));
+    for (i = 0; i < size; i++)
+    {
+        rv = _garuda_acl_rule_invalid(dev_id, (a_uint32_t) dst_idx, 1);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _garuda_acl_action_read(dev_id, &rule, (a_uint32_t) src_idx);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _garuda_acl_action_write(dev_id, &rule, (a_uint32_t) dst_idx);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _garuda_acl_slct_read(dev_id, &rule, (a_uint32_t) src_idx);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _garuda_acl_slct_write(dev_id, &rule, (a_uint32_t) dst_idx);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _garuda_acl_rule_invalid(dev_id, (a_uint32_t) src_idx, 1);
+        SW_RTN_ON_ERROR(rv);
+
+        src_idx += step;
+        dst_idx += step;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t rule_idx,
+                         a_uint32_t size)
+{
+    sw_error_t rv;
+    a_uint32_t base, flag, i;
+
+    flag = 0;
+    for (i = 0; i < size; i++)
+    {
+        base = GARUDA_RULE_SLCT_ADDR + ((rule_idx + i) << 5);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&flag), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_valid(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t size,
+                       a_uint32_t flag)
+{
+    sw_error_t rv;
+    a_uint32_t base, i;
+
+    for (i = 0; i < size; i++)
+    {
+        base = GARUDA_RULE_SLCT_ADDR + ((rule_idx + i) << 5);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&flag), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr,
+                        a_uint32_t new_addr, a_uint32_t list_id)
+{
+    sw_error_t rv;
+    a_uint32_t idx;
+
+    rv = _garuda_acl_list_loc(dev_id, list_id, &idx);
+    SW_RTN_ON_ERROR(rv);
+
+    if (old_addr != list_ent[dev_id][idx].addr)
+    {
+        return SW_FAIL;
+    }
+
+    list_ent[dev_id][idx].addr = new_addr;
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_bind(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t ports)
+{
+    sw_error_t rv;
+    a_uint32_t flt_idx[4], flt_nr;
+    a_uint32_t bind_pts = 0, addr, i, ret = 0;
+    garuda_acl_hw_rule_t rule;
+
+    aos_mem_zero(&rule, sizeof (garuda_acl_hw_rule_t));
+
+    rv = _garuda_acl_slct_read(dev_id, &rule, rule_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _garuda_acl_filter_map_get(&rule, flt_idx, &flt_nr);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _garuda_acl_rule_invalid(dev_id, rule_idx, 1);
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < flt_nr; i++)
+    {
+        addr = GARUDA_RULE_VLU_ADDR + (flt_idx[i] << 5) + 16;
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&bind_pts), sizeof (a_uint32_t));
+
+        /* source port field in different type rules has the same
+           hardware bit position */
+        SW_SET_REG_BY_FIELD(MAC_RUL_V4, MAC_INPT, ports, bind_pts);
+
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&bind_pts), sizeof (a_uint32_t));
+        ret += rv;
+    }
+
+    rv = _garuda_acl_rule_valid(dev_id, rule_idx, 1, rule.slct[0]);
+    ret += rv;
+    if (0 != ret)
+    {
+        return SW_FAIL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+                       a_uint32_t list_pri)
+{
+    a_uint32_t i, loc = GARUDA_MAX_LIST;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    for (i = 0; i < GARUDA_MAX_LIST; i++)
+    {
+        if ((ENT_USED == list_ent[dev_id][i].status)
+                && (list_id == list_ent[dev_id][i].list_id))
+        {
+            return SW_ALREADY_EXIST;
+        }
+
+        if (ENT_FREE == list_ent[dev_id][i].status)
+        {
+            loc = i;
+        }
+    }
+
+    if (GARUDA_MAX_LIST == loc)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    aos_mem_zero(&(list_ent[dev_id][loc]), sizeof (garuda_acl_list_t));
+    list_ent[dev_id][loc].list_id = list_id;
+    list_ent[dev_id][loc].list_pri = list_pri;
+    list_ent[dev_id][loc].status = ENT_USED;
+    _garuda_acl_list_dump(dev_id);
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    a_uint32_t list_idx;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    for (list_idx = 0; list_idx < GARUDA_MAX_LIST; list_idx++)
+    {
+        if ((ENT_USED == list_ent[dev_id][list_idx].status)
+                && (list_id == list_ent[dev_id][list_idx].list_id))
+        {
+            break;
+        }
+    }
+
+    if (list_idx >= GARUDA_MAX_LIST)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (0 != list_ent[dev_id][list_idx].bind_pts)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (0 != list_ent[dev_id][list_idx].size)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    aos_mem_zero(&(list_ent[dev_id][list_idx]), sizeof (garuda_acl_list_t));
+    list_ent[dev_id][list_idx].status = ENT_FREE;
+    _garuda_acl_list_dump(dev_id);
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+                     a_uint32_t rule_id, a_uint32_t rule_nr,
+                     fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+    a_uint32_t hsl_f_rsc, list_new_size, list_addr;
+    a_uint32_t list_pri, list_idx, load_addr, bind_pts;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((0 == rule_nr) || (NULL == rule))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = hsl_acl_free_rsc_get(dev_id, &hsl_f_rsc);
+    SW_RTN_ON_ERROR(rv);
+    if (hsl_f_rsc < rule_nr)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    rv = _garuda_acl_list_loc(dev_id, list_id, &list_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    if (rule_id != list_ent[dev_id][list_idx].size)
+    {
+        return SW_ALREADY_EXIST;
+    }
+    bind_pts = list_ent[dev_id][list_idx].bind_pts;
+
+    _garuda_acl_filter_snap(dev_id);
+
+    /* parse rule entry and alloc rule resource */
+    {
+        a_uint32_t i, j;
+        a_uint32_t ent_idx, tmp_ent_idx, flt_idx, flt_len;
+
+        aos_mem_zero(hw_rule_ent,
+                     GARUDA_MAX_RULE * sizeof (garuda_acl_hw_rule_t));
+
+        ent_idx = 0;
+        for (i = 0; i < rule_nr; i++)
+        {
+            tmp_ent_idx = ent_idx;
+            rv = _garuda_acl_rule_sw_to_hw(dev_id, &rule[i], bind_pts,
+                                           &hw_rule_ent[ent_idx], &ent_idx,
+                                           &flt_len);
+            SW_RTN_ON_ERROR(rv);
+
+            for (j = tmp_ent_idx; j < ent_idx; j++)
+            {
+                rv = _garuda_acl_filter_alloc(dev_id, &flt_idx);
+                SW_RTN_ON_ERROR(rv);
+
+                rv = _garuda_acl_slct_update(&hw_rule_ent[tmp_ent_idx],
+                                             j - tmp_ent_idx, flt_idx);
+                SW_RTN_ON_ERROR(rv);
+            }
+            SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, flt_len,
+                                hw_rule_ent[tmp_ent_idx].slct[6]);
+        }
+    }
+
+    /* alloc hardware select entry resource */
+    if (0 == list_ent[dev_id][list_idx].size)
+    {
+        list_new_size = rule_nr;
+        list_pri = list_ent[dev_id][list_idx].list_pri;
+
+        rv = hsl_acl_blk_alloc(dev_id, list_pri, list_new_size, list_id,
+                               &list_addr);
+        SW_RTN_ON_ERROR(rv);
+
+        load_addr = list_addr;
+    }
+    else
+    {
+        list_new_size = list_ent[dev_id][list_idx].size + rule_nr;
+        list_addr = list_ent[dev_id][list_idx].addr;
+
+        rv = hsl_acl_blk_resize(dev_id, list_addr, list_new_size);
+        SW_RTN_ON_ERROR(rv);
+
+        /* must be careful resize opration maybe change list base address */
+        list_addr = list_ent[dev_id][list_idx].addr;
+        load_addr = list_ent[dev_id][list_idx].size + list_addr;
+    }
+
+    /* load acl rule to hardware */
+    rv = _garuda_acl_rule_set(dev_id, load_addr, hw_rule_ent, rule_nr);
+    if (SW_OK != rv)
+    {
+        (void) hsl_acl_blk_resize(dev_id, list_addr,
+                                  list_ent[dev_id][list_idx].size);
+        return rv;
+    }
+
+    /* update software list control information */
+    list_ent[dev_id][list_idx].size = list_new_size;
+    list_ent[dev_id][list_idx].addr = list_addr;
+
+    /* update hardware acl rule resource information */
+    _garuda_acl_filter_commit(dev_id);
+    _garuda_acl_list_dump(dev_id);
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+                        a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+    a_uint32_t flt_idx[4];
+    a_uint32_t i, j, flt_nr;
+    a_uint32_t list_idx, addr, size, rule_idx, cnt;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _garuda_acl_list_loc(dev_id, list_id, &list_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == rule_nr)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((rule_id + rule_nr) > list_ent[dev_id][list_idx].size)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    _garuda_acl_filter_snap(dev_id);
+
+    /* free hardware filter resource */
+    addr = list_ent[dev_id][list_idx].addr + rule_id;
+    for (i = 0; i < rule_nr; i++)
+    {
+        rv = _garuda_acl_slct_read(dev_id, &hw_rule_ent[0], i + addr);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _garuda_acl_filter_map_get(&hw_rule_ent[0], flt_idx, &flt_nr);
+        SW_RTN_ON_ERROR(rv);
+
+        for (j = 0; j < flt_nr; j++)
+        {
+            _garuda_acl_filter_free(dev_id, flt_idx[j]);
+        }
+    }
+
+    cnt = list_ent[dev_id][list_idx].size - (rule_id + rule_nr);
+    rule_idx = list_ent[dev_id][list_idx].addr + (rule_id + rule_nr);
+    rv = _garuda_acl_rule_copy(dev_id, rule_idx, rule_idx - rule_nr, cnt);
+    SW_RTN_ON_ERROR(rv);
+
+    addr = list_ent[dev_id][list_idx].addr;
+    size = list_ent[dev_id][list_idx].size;
+    rv = hsl_acl_blk_resize(dev_id, addr, size - rule_nr);
+    SW_RTN_ON_ERROR(rv);
+
+    list_ent[dev_id][list_idx].size -= rule_nr;
+    _garuda_acl_filter_commit(dev_id);
+    _garuda_acl_list_dump(dev_id);
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+                       a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+    a_uint32_t list_idx, ent_idx, tmp_ent_idx, rule_idx;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _garuda_acl_list_loc(dev_id, list_id, &list_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    if (rule_id >= list_ent[dev_id][list_idx].size)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    aos_mem_zero(rule, sizeof (fal_acl_rule_t));
+
+    ent_idx = 0;
+    tmp_ent_idx = 0;
+    rule_idx = list_ent[dev_id][list_idx].addr + rule_id;
+    rv = _garuda_acl_rule_get(dev_id, hw_rule_ent, &tmp_ent_idx, rule_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _garuda_acl_rule_hw_to_sw(rule, hw_rule_ent, ent_idx,
+                                   tmp_ent_idx - ent_idx);
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                      fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                      a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+    a_uint32_t i, list_idx, rule_idx, base, ports;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_ACL_DIREC_IN != direc)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACL_BIND_PORT != obj_t)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    rv = _garuda_acl_list_loc(dev_id, list_id, &list_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    if (list_ent[dev_id][list_idx].bind_pts & (0x1 << obj_idx))
+    {
+        return SW_ALREADY_EXIST;
+    }
+
+    base = list_ent[dev_id][list_idx].addr;
+    ports = list_ent[dev_id][list_idx].bind_pts | (0x1 << obj_idx);
+    for (i = 0; i < list_ent[dev_id][list_idx].size; i++)
+    {
+        rule_idx = base + i;
+        rv = _garuda_acl_rule_bind(dev_id, rule_idx, ports);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    list_ent[dev_id][list_idx].bind_pts = ports;
+    return SW_OK;
+}
+
+
+
+static sw_error_t
+_garuda_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                        fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                        a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+    a_uint32_t i, list_idx, rule_idx, base, ports;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_ACL_DIREC_IN != direc)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACL_BIND_PORT != obj_t)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    rv = _garuda_acl_list_loc(dev_id, list_id, &list_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!(list_ent[dev_id][list_idx].bind_pts & (0x1 << obj_idx)))
+    {
+        return SW_NOT_FOUND;
+    }
+
+    base = list_ent[dev_id][list_idx].addr;
+    ports = list_ent[dev_id][list_idx].bind_pts & (~(0x1UL << obj_idx));
+    for (i = 0; i < list_ent[dev_id][list_idx].size; i++)
+    {
+        rule_idx = base + i;
+        rv = _garuda_acl_rule_bind(dev_id, rule_idx, ports);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    list_ent[dev_id][list_idx].bind_pts = ports;
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ACL_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ACL_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+garuda_acl_list_dump(a_uint32_t dev_id)
+{
+    a_uint32_t idx;
+
+    aos_printk("\ngaruda_acl_list_dump:\n");
+    for (idx = 0; idx < GARUDA_MAX_LIST; idx++)
+    {
+        if (ENT_USED == list_ent[dev_id][idx].status)
+        {
+            aos_printk
+            ("\n[id]:%02d  [pri]:%02d  [size]:%02d  [addr]:%02d  [pts_map]:0x%02x",
+             list_ent[dev_id][idx].list_id, list_ent[dev_id][idx].list_pri,
+             list_ent[dev_id][idx].size, list_ent[dev_id][idx].addr,
+             list_ent[dev_id][idx].bind_pts);
+        }
+    }
+    aos_printk("\n");
+
+    return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+garuda_acl_rule_dump(a_uint32_t dev_id)
+{
+    a_uint32_t slt_idx, flt_nr, i, j;
+    a_uint32_t flt_idx[4];
+    sw_error_t rv;
+    garuda_acl_hw_rule_t rule;
+
+    aos_printk("\ngaruda_acl_rule_dump:\n");
+
+    aos_printk("\nfilter_bitmap:0x%x", filter[dev_id]);
+    for (slt_idx = 0; slt_idx < GARUDA_MAX_RULE; slt_idx++)
+    {
+        aos_mem_zero(&rule, sizeof (garuda_acl_hw_rule_t));
+
+        rv = _garuda_acl_slct_read(dev_id, &rule, slt_idx);
+        if (SW_OK != rv)
+        {
+            continue;
+        }
+
+        rv = _garuda_acl_filter_map_get(&rule, flt_idx, &flt_nr);
+        if (SW_OK != rv)
+        {
+            continue;
+        }
+
+        aos_printk("\nslct_idx=%d  ", slt_idx);
+        for (i = 0; i < flt_nr; i++)
+        {
+            aos_printk("flt%d_idx=%d  ", i, flt_idx[i]);
+        }
+
+        aos_printk("\nslt:");
+        for (i = 0; i < 8; i++)
+        {
+            aos_printk("%08x  ", rule.slct[i]);
+        }
+
+        if (flt_nr)
+        {
+            rv = _garuda_acl_action_read(dev_id, &rule, slt_idx);
+            if (SW_OK != rv)
+            {
+                continue;
+            }
+            aos_printk("\nact:%08x  ", rule.act);
+
+            for (i = 0; i < flt_nr; i++)
+            {
+                rv = _garuda_acl_filter_read(dev_id, &rule, flt_idx[i]);
+                if (SW_OK != rv)
+                {
+                    continue;
+                }
+
+                aos_printk("\ntyp:%08x  ", rule.typ);
+                aos_printk("\nvlu:");
+                for (j = 0; j < 5; j++)
+                {
+                    aos_printk("%08x  ", rule.vlu[j]);
+                }
+
+                aos_printk("\nmsk:");
+                for (j = 0; j < 5; j++)
+                {
+                    aos_printk("%08x  ", rule.msk[j]);
+                }
+                aos_printk("\n");
+            }
+        }
+        aos_printk("\n");
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+garuda_acl_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t i;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    aos_mem_zero(hw_rule_ent,
+                 (GARUDA_MAX_RULE + 3) * sizeof (garuda_acl_hw_rule_t));
+
+    aos_mem_zero(list_ent[dev_id],
+                 GARUDA_MAX_LIST * sizeof (garuda_acl_list_t));
+
+    for (i = 0; i < GARUDA_MAX_LIST; i++)
+    {
+        list_ent[dev_id][i].status = ENT_FREE;
+    }
+
+    filter[dev_id]      = 0;
+    filter_snap[dev_id] = 0;
+
+    rv = hsl_acl_pool_destroy(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = hsl_acl_pool_creat(dev_id, GARUDA_MAX_LIST, GARUDA_MAX_RULE);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+/**
+ * @brief Creat an acl list
+ * @details  Comments:
+  *     If the priority of a list is more small then the priority is more high,
+ *     that means the list could be first matched.
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] list_pri acl list priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+                      a_uint32_t list_pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_acl_list_creat(dev_id, list_id, list_pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Destroy an acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_acl_list_destroy(dev_id, list_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one rule or more rules to an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this adding operation in list
+ * @param[in] rule_nr rule number of this adding operation
+ * @param[in] rule rules content of this adding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+                    a_uint32_t rule_id, a_uint32_t rule_nr,
+                    fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one rule or more rules from an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[in] rule_nr rule number of this deleteing operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+                       a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_acl_rule_delete(dev_id, list_id, rule_id, rule_nr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Query one particular rule in a particular acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[out] rule rule content of this operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+                      a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_acl_rule_query(dev_id, list_id, rule_id, rule);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind an acl list to a particular object
+ * @details  Comments:
+ *    If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this binding operation
+ * @param[in] obj_t object type of this binding operation
+ * @param[in] obj_idx object index of this binding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                     fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                     a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Unbind an acl list from a particular object
+ * @details  Comments:
+  *    If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this unbinding operation
+ * @param[in] obj_t object type of this unbinding operation
+ * @param[in] obj_idx object index of this unbinding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                       fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                       a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_acl_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_acl_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+garuda_acl_init(a_uint32_t dev_id)
+{
+    static a_bool_t b_hw_rule = A_FALSE;
+    hsl_acl_func_t *acl_func;
+    garuda_acl_hw_rule_t rule;
+    sw_error_t rv;
+    a_uint32_t i;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == b_hw_rule)
+    {
+        hw_rule_ent = (garuda_acl_hw_rule_t *)
+                      aos_mem_alloc((GARUDA_MAX_RULE +
+                                     3) * sizeof (garuda_acl_hw_rule_t));
+        if (NULL == hw_rule_ent)
+        {
+            return SW_NO_RESOURCE;
+        }
+        aos_mem_zero(hw_rule_ent,
+                     (GARUDA_MAX_RULE + 3) * sizeof (garuda_acl_hw_rule_t));
+        b_hw_rule = A_TRUE;
+    }
+
+    list_ent[dev_id] = (garuda_acl_list_t *)
+                       aos_mem_alloc(GARUDA_MAX_LIST * sizeof (garuda_acl_list_t));
+    if (NULL == list_ent[dev_id])
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(list_ent[dev_id],
+                 GARUDA_MAX_LIST * sizeof (garuda_acl_list_t));
+
+    for (i = 0; i < GARUDA_MAX_LIST; i++)
+    {
+        list_ent[dev_id][i].status = ENT_FREE;
+    }
+
+    filter[dev_id] = 0;
+    filter_snap[dev_id] = 0;
+
+    rv = hsl_acl_pool_creat(dev_id, GARUDA_MAX_LIST, GARUDA_MAX_RULE);
+    SW_RTN_ON_ERROR(rv);
+
+    acl_func = hsl_acl_ptr_get(dev_id);
+    SW_RTN_ON_NULL(acl_func);
+
+    acl_func->acl_rule_copy = _garuda_acl_rule_copy;
+    acl_func->acl_rule_invalid = _garuda_acl_rule_invalid;
+    acl_func->acl_addr_update = _garuda_acl_addr_update;
+
+    /* zero acl hardware memory */
+    aos_mem_zero(&rule, sizeof (garuda_acl_hw_rule_t));
+    for (i = 0; i < GARUDA_MAX_RULE; i++)
+    {
+        rv = _garuda_acl_slct_write(dev_id, &rule, i);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+#ifdef GARUDA_SW_ENTRY
+    flt_vlu_mem = aos_mem_alloc(GARUDA_MAX_RULE * 32);
+    if (NULL == flt_vlu_mem)
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(flt_vlu_mem, GARUDA_MAX_RULE * 32);
+
+    flt_msk_mem = aos_mem_alloc(GARUDA_MAX_RULE * 32);
+    if (NULL == flt_msk_mem)
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(flt_msk_mem, GARUDA_MAX_RULE * 32);
+
+    flt_typ_mem = aos_mem_alloc(GARUDA_MAX_RULE * 4);
+    if (NULL == flt_typ_mem)
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(flt_typ_mem, GARUDA_MAX_RULE * 4);
+
+    act_mem = aos_mem_alloc(GARUDA_MAX_RULE * 32);
+    if (NULL == act_mem)
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(act_mem, GARUDA_MAX_RULE * 32);
+
+    slct_mem = aos_mem_alloc(GARUDA_MAX_RULE * 32);
+    if (NULL == slct_mem)
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(slct_mem, GARUDA_MAX_RULE * 32);
+#endif
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->acl_list_creat = garuda_acl_list_creat;
+        p_api->acl_list_destroy = garuda_acl_list_destroy;
+        p_api->acl_list_bind = garuda_acl_list_bind;
+        p_api->acl_list_unbind = garuda_acl_list_unbind;
+        p_api->acl_rule_add = garuda_acl_rule_add;
+        p_api->acl_rule_delete = garuda_acl_rule_delete;
+        p_api->acl_rule_query = garuda_acl_rule_query;
+        p_api->acl_status_set = garuda_acl_status_set;
+        p_api->acl_status_get = garuda_acl_status_get;
+        p_api->acl_list_dump = garuda_acl_list_dump;
+        p_api->acl_rule_dump = garuda_acl_rule_dump;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/garuda/garuda_fdb.c b/qca-ssdk/src/hsl/garuda/garuda_fdb.c
new file mode 100755
index 0000000..1904396
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_fdb.c
@@ -0,0 +1,1007 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+ * @defgroup garuda_fdb GARUDA_FDB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_fdb.h"
+#include "garuda_reg.h"
+
+#define ARL_FLUSH_ALL             1
+#define ARL_LOAD_ENTRY            2
+#define ARL_PURGE_ENTRY           3
+#define ARL_FLUSH_ALL_UNLOCK      4
+#define ARL_FLUSH_PORT_UNICAST    5
+#define ARL_NEXT_ENTRY            6
+#define ARL_FIND_ENTRY            7
+
+#define ARL_FIRST_ENTRY           1001
+#define ARL_FLUSH_PORT_NO_STATIC  1002
+#define ARL_FLUSH_PORT_AND_STATIC 1003
+
+static a_bool_t
+garuda_fdb_is_zeroaddr(fal_mac_addr_t addr)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 6; i++)
+    {
+        if (addr.uc[i])
+        {
+            return A_FALSE;
+        }
+    }
+
+    return A_TRUE;
+}
+
+static void
+garuda_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1)
+{
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE2, addr.uc[2], *reg1);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE3, addr.uc[3], *reg1);
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0);
+
+    return;
+}
+
+static sw_error_t
+garuda_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry,
+                    a_uint32_t reg[])
+{
+    a_uint32_t port;
+
+    if (A_FALSE == entry->portmap_en)
+    {
+        if (A_TRUE !=
+                hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+
+        port = 0x1UL << entry->port.id;
+    }
+    else
+    {
+        if (A_FALSE ==
+                hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+
+        port = entry->port.map;
+    }
+
+    if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]);
+    }
+    else if (FAL_MAC_FRWRD != entry->dacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_MAC_DROP == entry->sacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, SA_DROP_EN, 1, reg[2]);
+    }
+    else if (FAL_MAC_FRWRD != entry->sacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->leaky_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]);
+    }
+
+    if (A_TRUE == entry->static_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]);
+    }
+
+    if (A_TRUE == entry->mirror_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, MIRROR_EN, 1, reg[2]);
+    }
+
+    if (A_TRUE == entry->clone_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CLONE_EN, 1, reg[2]);
+    }
+
+    if (A_TRUE == entry->da_pri_en)
+    {
+        hsl_dev_t *p_dev;
+
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI_EN, 1, reg[2]);
+
+        SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+
+        if (entry->da_queue > (p_dev->nr_queue - 1))
+            return SW_BAD_PARAM;
+
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI, entry->da_queue, reg[2]);
+    }
+
+    if (A_TRUE == entry->cross_pt_state)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, DES_PORT, port, reg[2]);
+    garuda_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+
+    return SW_OK;
+}
+
+static void
+garuda_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+    a_uint32_t i, data;
+
+    aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+    entry->dacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_CPY_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    entry->sacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, SA_DROP_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->sacmd = FAL_MAC_DROP;
+    }
+
+    entry->leaky_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->leaky_en = A_TRUE;
+    }
+
+    entry->static_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]);
+    if (0xf == data)
+    {
+        entry->static_en = A_TRUE;
+    }
+
+    entry->mirror_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, MIRROR_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+
+    entry->clone_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, CLONE_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->clone_en = A_TRUE;
+    }
+
+    entry->da_pri_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI_EN, data, reg[2]);
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI, data, reg[2]);
+        entry->da_pri_en = A_TRUE;
+        entry->da_queue = data & 0x3;
+    }
+
+    entry->cross_pt_state = A_FALSE;
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, DES_PORT, data, reg[2]);
+
+    entry->portmap_en = A_TRUE;
+    entry->port.map = data;
+
+    for (i = 0; i < 4; i++)
+    {
+        entry->addr.uc[i] = (reg[1] >> ((3 - i) << 3)) & 0xff;
+    }
+
+    for (i = 4; i < 6; i++)
+    {
+        entry->addr.uc[i] = (reg[0] >> ((7 - i) << 3)) & 0xff;
+    }
+
+    return;
+}
+
+static sw_error_t
+garuda_fdb_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    sw_error_t rv;
+    a_uint32_t busy = 1;
+    a_uint32_t full_vio;
+    a_uint32_t i = 1000;
+    a_uint32_t entry;
+    a_uint32_t hwop = op;
+
+    while (busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+                          (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_BUSY;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_BUSY, 1, entry);
+
+    if (ARL_FLUSH_PORT_AND_STATIC == hwop)
+    {
+        hwop = ARL_FLUSH_PORT_UNICAST;
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 1, entry);
+    }
+
+    if (ARL_FLUSH_PORT_NO_STATIC == hwop)
+    {
+        hwop = ARL_FLUSH_PORT_UNICAST;
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 0, entry);
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_FUNC, hwop, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    busy = 1;
+    i = 1000;
+    while (busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+                          (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_FAIL;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_FULL_VIO,
+                      (a_uint8_t *) (&full_vio), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (full_vio)
+    {
+        /* must clear AT_FULL_VOI bit */
+        entry = 0x1000;
+        HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        if (ARL_LOAD_ENTRY == hwop)
+        {
+            return SW_FULL;
+        }
+        else if ((ARL_PURGE_ENTRY == hwop)
+                 || (ARL_FLUSH_PORT_UNICAST == hwop))
+        {
+            return SW_NOT_FOUND;
+        }
+        else
+        {
+            return SW_FAIL;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+garuda_atu_get(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op)
+{
+    sw_error_t rv;
+    a_uint32_t reg[3] = { 0 };
+    a_uint32_t status = 0;
+    a_uint32_t hwop = op;
+
+    if ((ARL_NEXT_ENTRY == op)
+            || (ARL_FIND_ENTRY == op))
+    {
+        garuda_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* set status not zero */
+    if (ARL_NEXT_ENTRY == op)
+    {
+        reg[2] = 0xf0000;
+    }
+
+    if (ARL_FIRST_ENTRY == op)
+    {
+        hwop = ARL_NEXT_ENTRY;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = garuda_fdb_commit(dev_id, hwop);
+    SW_RTN_ON_ERROR(rv);
+
+    /* get hardware enrety */
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]);
+
+    garuda_atu_hw_to_sw(reg, entry);
+
+    /* If hardware return back with address and status all zero,
+       that means no other next valid entry in fdb table */
+    if ((A_TRUE == garuda_fdb_is_zeroaddr(entry->addr))
+            && (0 == status))
+    {
+        if (ARL_NEXT_ENTRY == op)
+        {
+            return SW_NO_MORE;
+        }
+        else if ((ARL_FIND_ENTRY == op)
+                 || (ARL_FIRST_ENTRY == op))
+        {
+            return SW_NOT_FOUND;
+        }
+        else
+        {
+            return SW_FAIL;
+        }
+    }
+    else
+    {
+        return SW_OK;
+    }
+}
+
+static sw_error_t
+_garuda_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[3] = { 0, 0, 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = garuda_atu_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (&reg[1]),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&reg[0]),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = garuda_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        rv = garuda_fdb_commit(dev_id, ARL_FLUSH_ALL);
+    }
+    else
+    {
+        rv = garuda_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+    }
+
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_PORT_NUM, port_id, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        rv = garuda_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC);
+    }
+    else
+    {
+        rv = garuda_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC);
+    }
+
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg0 = 0, reg1 = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    garuda_fdb_fill_addr(entry->addr, &reg0, &reg1);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (&reg1),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&reg0),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = garuda_fdb_commit(dev_id, ARL_PURGE_ENTRY);
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = garuda_atu_get(dev_id, entry, ARL_NEXT_ENTRY);
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = garuda_atu_get(dev_id, entry, ARL_FIRST_ENTRY);
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = garuda_atu_get(dev_id, entry, ARL_FIND_ENTRY);
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEARN_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t *enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEARN_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((65535 * 7 < *time) || (7 > *time))
+    {
+        return SW_BAD_PARAM;
+    }
+    data = *time / 7;
+    *time = data * 7;
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *time = data * 7;
+    return SW_OK;
+}
+
+/**
+ * @brief Add a Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_fdb_add(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete all Fdb entries
+ *   @details   Comments:
+ *         If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ *       entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_fdb_del_all(dev_id, flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete Fdb entries on a particular port
+ *   @details   Comments:
+ *       If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ *       entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_fdb_del_by_port(dev_id, port_id, flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a particular Fdb entry through mac address
+ *   @details   Comments:
+ *       Only addr field in entry is meaning. For IVL learning vid or fid field
+ *       also is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_fdb_del_by_mac(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get next Fdb entry from particular device
+ *   @details   Comments:
+ *    For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_fdb_next(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from particular device
+ * @param[in] dev_id device id
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_fdb_first(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a particular Fdb entry from device through mac address.
+ *    @details  Comments:
+    For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_fdb_find(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning status on a particular port.
+ *    @details  Comments:
+ *       This operation will enable or disable dynamic address learning
+ *       feature on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_fdb_port_learn_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_fdb_port_learn_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address aging status on particular device.
+ *   @details  Comments:
+ *       This operation will enable or disable dynamic address aging
+ *       feature on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_fdb_age_ctrl_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address aging status on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_fdb_age_ctrl_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address aging time on a particular device.
+ * @details   Comments:
+ *       This operation will set dynamic address aging time on a particular device.
+ *       The unit of time is second. Because different device has differnet
+ *       hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_fdb_age_time_set(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address aging time on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_fdb_age_time_get(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+garuda_fdb_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->fdb_add = garuda_fdb_add;
+        p_api->fdb_del_all = garuda_fdb_del_all;
+        p_api->fdb_del_by_port = garuda_fdb_del_by_port;
+        p_api->fdb_del_by_mac = garuda_fdb_del_by_mac;
+        p_api->fdb_first = garuda_fdb_first;
+        p_api->fdb_next = garuda_fdb_next;
+        p_api->fdb_find = garuda_fdb_find;
+        p_api->port_learn_set = garuda_fdb_port_learn_set;
+        p_api->port_learn_get = garuda_fdb_port_learn_get;
+        p_api->age_ctrl_set = garuda_fdb_age_ctrl_set;
+        p_api->age_ctrl_get = garuda_fdb_age_ctrl_get;
+        p_api->age_time_set = garuda_fdb_age_time_set;
+        p_api->age_time_get = garuda_fdb_age_time_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/garuda/garuda_igmp.c b/qca-ssdk/src/hsl/garuda/garuda_igmp.c
new file mode 100755
index 0000000..5f95f70
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_igmp.c
@@ -0,0 +1,610 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_igmp GARUDA_IGMP
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_igmp.h"
+#include "garuda_reg.h"
+
+static sw_error_t
+_garuda_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, JOIN_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, JOIN_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_mports_validity_check(dev_id, pts))
+    {
+        return SW_BAD_PARAM;
+    }
+    val = pts;
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *pts = val;
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set igmp/mld packets snooping status on a particular port.
+ * @details    Comments:
+ *   After enabling igmp/mld snooping feature on a particular port all kinds
+ *   igmp/mld packets received on this port would be acknowledged by hardware.
+ *   Particular forwarding decision could be setted by fal_igmp_mld_cmd_set.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_igmps_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets snooping status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_igmps_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld packets forwarding command on a particular device.
+ * @details    Comments:
+ *    Particular device may only support parts of forwarding commands.
+ *    This operation will take effect only after enabling igmp/mld snooping
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_igmp_mld_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_igmp_mld_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld join packets hardware acknowledgement status on particular port.
+ * @details    Comments:
+ *    After enabling igmp/mld join feature on a particular port hardware will
+ *    dynamic learning or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_igmp_mld_join_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_igmp_mld_join_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @details    Comments:
+ *    After enabling igmp join feature on a particular port hardware will dynamic
+ *    deleting or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_igmp_mld_leave_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_igmp_mld_leave_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld router ports on a particular device.
+ * @details     Comments:
+ *    After enabling igmp/mld join/leave feature on a particular port igmp/mld
+ *    join/leave packets received on this port will be forwarded to router ports.
+ * @param[in] dev_id device id
+ * @param[in] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_igmp_mld_rp_set(dev_id, pts);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld router ports on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_igmp_mld_rp_get(dev_id, pts);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   entry creat hardware will dynamic creat and delete multicast entry,
+ *   otherwise hardware only can change destination ports of existing muticast entry.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_igmp_mld_entry_creat_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_igmp_mld_entry_creat_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+garuda_igmp_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->port_igmps_status_set = garuda_port_igmps_status_set;
+        p_api->port_igmps_status_get = garuda_port_igmps_status_get;
+        p_api->igmp_mld_cmd_set = garuda_igmp_mld_cmd_set;
+        p_api->igmp_mld_cmd_get = garuda_igmp_mld_cmd_get;
+        p_api->port_igmp_join_set = garuda_port_igmp_mld_join_set;
+        p_api->port_igmp_join_get = garuda_port_igmp_mld_join_get;
+        p_api->port_igmp_leave_set = garuda_port_igmp_mld_leave_set;
+        p_api->port_igmp_leave_get = garuda_port_igmp_mld_leave_get;
+        p_api->igmp_rp_set = garuda_igmp_mld_rp_set;
+        p_api->igmp_rp_get = garuda_igmp_mld_rp_get;
+        p_api->igmp_entry_creat_set = garuda_igmp_mld_entry_creat_set;
+        p_api->igmp_entry_creat_get = garuda_igmp_mld_entry_creat_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/garuda/garuda_init.c b/qca-ssdk/src/hsl/garuda/garuda_init.c
new file mode 100755
index 0000000..eeef514
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_init.c
@@ -0,0 +1,642 @@
+/*
+ * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_init GARUDA_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_mib.h"
+#include "garuda_port_ctrl.h"
+#include "garuda_portvlan.h"
+#include "garuda_vlan.h"
+#include "garuda_fdb.h"
+#include "garuda_qos.h"
+#include "garuda_mirror.h"
+#include "garuda_stp.h"
+#include "garuda_rate.h"
+#include "garuda_misc.h"
+#include "garuda_leaky.h"
+#include "garuda_igmp.h"
+#include "garuda_acl.h"
+#include "garuda_led.h"
+#include "garuda_reg_access.h"
+#include "garuda_reg.h"
+#include "garuda_init.h"
+#include "f1_phy.h"
+
+static ssdk_init_cfg * garuda_cfg[SW_MAX_NR_DEV] = { 0 };
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+static sw_error_t
+garuda_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
+{
+    hsl_port_prop_t p_type;
+    hsl_dev_t *pdev = NULL;
+    fal_port_t port_id;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return SW_NOT_INITIALIZED;
+
+    for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+    {
+        hsl_port_prop_portmap_set(dev_id, port_id);
+
+        for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
+        {
+            if (HSL_NO_CPU == mode)
+            {
+                SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                continue;
+            }
+
+            switch (p_type)
+            {
+                case HSL_PP_PHY:
+                    if (HSL_CPU_1 != mode)
+                    {
+                        if ((port_id != pdev->cpu_port_nr)
+                                && (port_id != (pdev->nr_ports -1)))
+                        {
+                            SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                        }
+                    }
+                    else
+                    {
+                        if (port_id != pdev->cpu_port_nr)
+                        {
+                            SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                        }
+                    }
+                    break;
+
+                case HSL_PP_INCL_CPU:
+                    /* include cpu port but exclude wan port in some cases */
+                    if (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1))))
+                        SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+
+                    break;
+
+                case HSL_PP_EXCL_CPU:
+                    /* exclude cpu port and wan port in some cases */
+                    if ((port_id != pdev->cpu_port_nr)
+                            && (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1)))))
+                        SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                    break;
+
+                default:
+                    break;
+            }
+        }
+
+        if (HSL_NO_CPU == mode)
+        {
+            SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+                            (dev_id, port_id, port_id + 1));
+        }
+        else
+        {
+            if (port_id != pdev->cpu_port_nr)
+            {
+                SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+                                (dev_id, port_id, port_id - 1));
+            }
+        }
+    }
+
+    return SW_OK;
+}
+
+static void
+phy_dport_set(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t dport_addr, a_uint16_t val_mask)
+{
+    a_uint16_t phy_data;
+    sw_error_t rv;
+
+    HSL_PHY_SET(rv, dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, dport_addr);
+    HSL_PHY_GET(rv, dev_id, phy_id, F1_DEBUG_PORT_DATA, &phy_data);
+    phy_data |= val_mask;
+    HSL_PHY_SET(rv, dev_id, phy_id, F1_DEBUG_PORT_DATA, phy_data);
+}
+
+static void
+phy_dport_clear(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t dport_addr, a_uint16_t val_mask)
+{
+    a_uint16_t phy_data;
+    sw_error_t rv;
+
+    HSL_PHY_SET(rv, dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, dport_addr);
+    HSL_PHY_GET(rv, dev_id, phy_id, F1_DEBUG_PORT_DATA, &phy_data);
+    phy_data &= ~val_mask;
+    HSL_PHY_SET(rv, dev_id, phy_id, F1_DEBUG_PORT_DATA, phy_data);
+}
+
+static sw_error_t
+garuda_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    garuda_init_spec_cfg *garuda_init_cfg = NULL;
+    hsl_dev_t    *pdev = NULL;
+    hsl_init_mode cpu_mode;
+    a_uint32_t port_id;
+    a_uint32_t data;
+    sw_error_t rv;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (NULL == pdev)
+    {
+        return SW_NOT_INITIALIZED;
+    }
+    cpu_mode = cfg->cpu_mode;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, POSTRIP, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* phy pll on */
+    SW_SET_REG_BY_FIELD(POSTRIP, PHY_PLL_ON, 1, data);
+
+    garuda_init_cfg = (garuda_init_spec_cfg* )(cfg->chip_spec_cfg);
+    if (!garuda_init_cfg)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    /* delay */
+    if (A_TRUE == garuda_init_cfg->rx_delay_s1)
+    {
+        SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S1, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S1, 0, data);
+    }
+
+    if (A_TRUE == garuda_init_cfg->rx_delay_s0)
+    {
+        SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S0, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S0, 0, data);
+    }
+
+    if (A_TRUE ==  garuda_init_cfg->tx_delay_s1)
+    {
+        SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S1, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S1, 0, data);
+    }
+
+    if (A_TRUE ==  garuda_init_cfg->tx_delay_s0)
+    {
+        SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S0, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S0, 0, data);
+    }
+
+    /* tx/rx delay enable */
+    if (A_TRUE ==  garuda_init_cfg->rgmii_txclk_delay)
+    {
+        SW_SET_REG_BY_FIELD(POSTRIP, RGMII_TXCLK_DELAY_EN, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(POSTRIP, RGMII_TXCLK_DELAY_EN, 0, data);
+    }
+
+    /* tx/rx delay enable */
+    if (A_TRUE ==  garuda_init_cfg->rgmii_rxclk_delay)
+    {
+        SW_SET_REG_BY_FIELD(POSTRIP, RGMII_RXCLK_DELAY_EN, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(POSTRIP, RGMII_RXCLK_DELAY_EN, 0, data);
+    }
+
+    /* mac5 default mode */
+    /*SW_SET_REG_BY_FIELD(POSTRIP, MAC5_PHY_MODE, 0, data);
+    SW_SET_REG_BY_FIELD(POSTRIP, MAC5_MAC_MODE, 0, data);*/
+
+    /* mac0 default phy mode */
+    SW_SET_REG_BY_FIELD(POSTRIP, MAC0_MAC_MODE, 0, data);
+
+    /* mac0 default rgmii mode */
+    SW_SET_REG_BY_FIELD(POSTRIP, MAC0_RGMII_EN, 1, data);
+    SW_SET_REG_BY_FIELD(POSTRIP, MAC0_GMII_EN, 0, data);
+
+    /* mac5 default disable mode */
+    SW_SET_REG_BY_FIELD(POSTRIP, MAC5_PHY_MODE, 0, data);
+    SW_SET_REG_BY_FIELD(POSTRIP, MAC5_MAC_MODE, 0, data);
+
+    /* phy default mode */
+    SW_SET_REG_BY_FIELD(POSTRIP, PHY4_RGMII_EN, 0, data);
+    SW_SET_REG_BY_FIELD(POSTRIP, PHY4_GMII_EN, 0, data);
+
+    /* modify default mode */
+    if (A_FALSE == garuda_init_cfg->mac0_rgmii)
+    {
+        SW_SET_REG_BY_FIELD(POSTRIP, MAC0_RGMII_EN, 0, data);
+        SW_SET_REG_BY_FIELD(POSTRIP, MAC0_GMII_EN,  1, data);
+
+        /*invert clock output for port0 gmii pad.*/
+        a_uint32_t temp;
+        HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0,
+                          (a_uint8_t *) (&temp), sizeof (a_uint32_t));
+        temp |= 1<<MASK_CTL_MII_CLK0_SEL_BOFFSET;
+        HSL_REG_ENTRY_SET(rv, dev_id, MASK_CTL, 0,
+                          (a_uint8_t *) (&temp), sizeof (a_uint32_t));
+    }
+
+    if(HSL_CPU_2 == cpu_mode)
+    {
+        if (A_TRUE == garuda_init_cfg->mac5_rgmii)
+        {
+
+            SW_SET_REG_BY_FIELD(POSTRIP, PHY4_RGMII_EN, 1, data);
+            SW_SET_REG_BY_FIELD(POSTRIP, PHY4_GMII_EN, 0, data);
+
+            a_uint32_t phy_id = 4;
+            /* phy4 rgmii mode enable */
+            phy_dport_set(dev_id, phy_id, F1_DEBUG_PORT_RGMII_MODE, F1_DEBUG_PORT_RGMII_MODE_EN);
+
+            /* Rx delay enable */
+            if (A_TRUE ==  garuda_init_cfg->phy4_rx_delay)
+            {
+                phy_dport_set(dev_id, phy_id, F1_DEBUG_PORT_RX_DELAY, F1_DEBUG_PORT_RX_DELAY_EN);
+            }
+            else
+            {
+                phy_dport_clear(dev_id, phy_id, F1_DEBUG_PORT_RX_DELAY, F1_DEBUG_PORT_RX_DELAY_EN);
+            }
+
+            /* Tx delay enable */
+            if (A_TRUE ==  garuda_init_cfg->phy4_tx_delay)
+            {
+                phy_dport_set(dev_id, phy_id, F1_DEBUG_PORT_TX_DELAY, F1_DEBUG_PORT_TX_DELAY_EN);
+            }
+            else
+            {
+                phy_dport_clear(dev_id, phy_id, F1_DEBUG_PORT_TX_DELAY, F1_DEBUG_PORT_TX_DELAY_EN);
+            }
+
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(POSTRIP, PHY4_RGMII_EN, 0, data);
+            SW_SET_REG_BY_FIELD(POSTRIP, PHY4_GMII_EN, 1, data);
+        }
+    }
+    else if (HSL_CPU_1 == cpu_mode)
+    {
+        //SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S0, 0, data);
+
+    }
+    else if (HSL_CPU_1_PLUS == cpu_mode)
+    {
+        SW_SET_REG_BY_FIELD(POSTRIP, MAC5_MAC_MODE, 1, data);
+
+    }
+    else if (HSL_NO_CPU == cpu_mode)
+    {
+
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, POSTRIP, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+    {
+        if (port_id == pdev->cpu_port_nr)
+        {
+            continue;
+        }
+
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data);
+
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+garuda_bist_test(a_uint32_t dev_id)
+{
+    a_uint32_t entry, data, i;
+    sw_error_t rv;
+
+    data = 1;
+    i = 0x1000;
+    while (data && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_INIT_ERROR;
+    }
+
+    entry = 0;
+    SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = 1;
+    i = 0x1000;
+    while (data && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_INIT_ERROR;
+    }
+
+    SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry);
+    if (data)
+    {
+        SW_GET_FIELD_BY_REG(BIST_CTRL, ONE_ERR, data, entry);
+        if (!data)
+        {
+            return SW_INIT_ERROR;
+        }
+
+        SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_ADDR, data, entry);
+
+        entry = 0;
+        SW_SET_REG_BY_FIELD(BIST_RCV, RCV_EN, 1, entry);
+        SW_SET_REG_BY_FIELD(BIST_RCV, RCV_ADDR, data, entry);
+        HSL_REG_ENTRY_SET(rv, dev_id, BIST_RCV, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        return SW_OK;
+    }
+
+    entry = 0;
+    SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = 1;
+    i = 0x1000;
+    while (data && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_INIT_ERROR;
+    }
+
+    SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry);
+    if (data)
+    {
+        return SW_INIT_ERROR;
+    }
+
+    return SW_OK;
+}
+
+
+#endif
+
+static sw_error_t
+garuda_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode)
+{
+    hsl_dev_t *pdev = NULL;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return SW_NOT_INITIALIZED;
+
+    pdev->nr_ports = 6;
+    pdev->nr_phy = 5;
+    pdev->cpu_port_nr = 0;
+    pdev->nr_vlans = 4096;
+    pdev->hw_vlan_query = A_TRUE;
+    pdev->nr_queue = 4;
+    pdev->cpu_mode = cpu_mode;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_reset(a_uint32_t dev_id)
+{
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    val = 0x1;
+    HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = garuda_hw_init(dev_id, garuda_cfg[dev_id]);
+    SW_RTN_ON_ERROR(rv);
+
+    GARUDA_ACL_RESET(rv, dev_id);
+#endif
+
+    return SW_OK;
+}
+
+sw_error_t
+garuda_cleanup(a_uint32_t dev_id)
+{
+    if (garuda_cfg[dev_id])
+    {
+        aos_mem_free(garuda_cfg[dev_id]);
+        garuda_cfg[dev_id] = NULL;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief reset hsl layer.
+ * @details Comments:
+ *   This operation will reset hsl layer
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_reset(dev_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Init hsl layer.
+ * @details Comments:
+ *   This operation will init hsl layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+garuda_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    a_uint8_t *p_mem;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    p_mem = (a_uint8_t *)garuda_cfg[dev_id];
+    if (NULL == p_mem)
+    {
+        p_mem = aos_mem_alloc(sizeof (ssdk_init_cfg)
+                              + sizeof(garuda_init_spec_cfg));
+        garuda_cfg[dev_id] = (ssdk_init_cfg *)p_mem;
+        garuda_cfg[dev_id]->chip_spec_cfg = (garuda_init_spec_cfg *)
+                                            (p_mem + sizeof (ssdk_init_cfg));
+    }
+
+    if (NULL == p_mem)
+    {
+        return SW_OUT_OF_MEM;
+    }
+
+    aos_mem_copy(garuda_cfg[dev_id]->chip_spec_cfg,
+                 cfg->chip_spec_cfg, sizeof (garuda_init_spec_cfg));
+    aos_mem_copy(garuda_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+    garuda_cfg[dev_id]->chip_spec_cfg = (garuda_init_spec_cfg *)
+                                        (p_mem + sizeof (ssdk_init_cfg));
+
+    SW_RTN_ON_ERROR(garuda_reg_access_init(dev_id, cfg->reg_mode));
+
+    SW_RTN_ON_ERROR(garuda_dev_init(dev_id, cfg->cpu_mode));
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+    {
+        a_uint32_t i, entry;
+        sw_error_t rv;
+
+        if(HSL_MDIO == cfg->reg_mode)
+        {
+            SW_RTN_ON_ERROR(garuda_bist_test(dev_id));
+
+            entry = 0x1;
+            HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+                              (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            i = 0x10;
+            do
+            {
+                HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+                                  (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+                SW_RTN_ON_ERROR(rv);
+
+                aos_mdelay(10);
+            }
+            while (entry && --i);
+
+            if (0 == i)
+            {
+                return SW_INIT_ERROR;
+            }
+        }
+        SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id));
+        SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
+        SW_RTN_ON_ERROR(garuda_portproperty_init(dev_id, cfg->cpu_mode));
+
+        GARUDA_MIB_INIT(rv, dev_id);
+        GARUDA_PORT_CTRL_INIT(rv, dev_id);
+        GARUDA_PORTVLAN_INIT(rv, dev_id);
+        GARUDA_VLAN_INIT(rv, dev_id);
+        GARUDA_FDB_INIT(rv, dev_id);
+        GARUDA_QOS_INIT(rv, dev_id);
+        GARUDA_STP_INIT(rv, dev_id);
+        GARUDA_MIRR_INIT(rv, dev_id);
+        GARUDA_RATE_INIT(rv, dev_id);
+        GARUDA_MISC_INIT(rv, dev_id);
+        GARUDA_LEAKY_INIT(rv, dev_id);
+        GARUDA_IGMP_INIT(rv, dev_id);
+        GARUDA_ACL_INIT(rv, dev_id);
+        GARUDA_LED_INIT(rv, dev_id);
+
+        {
+            hsl_api_t *p_api;
+
+            SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+            p_api->dev_reset   = garuda_reset;
+            p_api->dev_clean   = garuda_cleanup;
+        }
+
+        if(cfg->reg_mode == HSL_MDIO)
+        {
+            SW_RTN_ON_ERROR(garuda_hw_init(dev_id, cfg));
+        }
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/garuda/garuda_leaky.c b/qca-ssdk/src/hsl/garuda/garuda_leaky.c
new file mode 100755
index 0000000..5969fa1
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_leaky.c
@@ -0,0 +1,531 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+ * @defgroup garuda_leaky GARUDA_LEAKY
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_leaky.h"
+#include "garuda_reg.h"
+
+static sw_error_t
+_garuda_uc_leaky_mode_set(a_uint32_t dev_id,
+                          fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+    {
+        data = 0;
+    }
+    else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_uc_leaky_mode_get(a_uint32_t dev_id,
+                          fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+    }
+    else
+    {
+        *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_mc_leaky_mode_set(a_uint32_t dev_id,
+                          fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+    {
+        data = 0;
+    }
+    else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+
+static sw_error_t
+_garuda_mc_leaky_mode_get(a_uint32_t dev_id,
+                          fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+    }
+    else
+    {
+        *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, ARP_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t *enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, ARP_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+* @brief Set unicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+garuda_uc_leaky_mode_set(a_uint32_t dev_id,
+                         fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_uc_leaky_mode_set(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_uc_leaky_mode_get(a_uint32_t dev_id,
+                         fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_uc_leaky_mode_get(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Set multicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+garuda_mc_leaky_mode_set(a_uint32_t dev_id,
+                         fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_mc_leaky_mode_set(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mc_leaky_mode_get(a_uint32_t dev_id,
+                         fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_mc_leaky_mode_get(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_arp_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_arp_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_uc_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_uc_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_mc_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_mc_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+garuda_leaky_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->uc_leaky_mode_set = garuda_uc_leaky_mode_set;
+        p_api->uc_leaky_mode_get = garuda_uc_leaky_mode_get;
+        p_api->mc_leaky_mode_set = garuda_mc_leaky_mode_set;
+        p_api->mc_leaky_mode_get = garuda_mc_leaky_mode_get;
+        p_api->port_arp_leaky_set = garuda_port_arp_leaky_set;
+        p_api->port_arp_leaky_get = garuda_port_arp_leaky_get;
+        p_api->port_uc_leaky_set = garuda_port_uc_leaky_set;
+        p_api->port_uc_leaky_get = garuda_port_uc_leaky_get;
+        p_api->port_mc_leaky_set = garuda_port_mc_leaky_set;
+        p_api->port_mc_leaky_get = garuda_port_mc_leaky_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/garuda/garuda_led.c b/qca-ssdk/src/hsl/garuda/garuda_led.c
new file mode 100755
index 0000000..f69b2a9
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_led.c
@@ -0,0 +1,370 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+ * @defgroup garuda_led GARUDA_LED
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "garuda_led.h"
+#include "garuda_reg.h"
+
+#define MAX_LED_PATTERN_ID   2
+#define LED_PATTERN_ADDR     0xB0
+
+
+static sw_error_t
+_garuda_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                             led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    a_uint32_t data = 0, reg;
+    a_uint32_t addr;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((LED_LAN_PORT_GROUP != group) && (LED_WAN_PORT_GROUP != group))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (id > MAX_LED_PATTERN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    addr = LED_PATTERN_ADDR + (id << 2);
+
+    if (LED_ALWAYS_OFF == pattern->mode)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, 0, data);
+    }
+    else if (LED_ALWAYS_BLINK == pattern->mode)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, 1, data);
+    }
+    else if (LED_ALWAYS_ON == pattern->mode)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, 2, data);
+    }
+    else if (LED_PATTERN_MAP_EN == pattern->mode)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, 3, data);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << POWER_ON_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_1000M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_100M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_10M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << COLLISION_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINKUP_OVERRIDE_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data);
+    }
+
+    if (LED_BLINK_2HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data);
+    }
+    else if (LED_BLINK_4HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data);
+    }
+    else if (LED_BLINK_8HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data);
+    }
+    else if (LED_BLINK_TXRX == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_LAN_PORT_GROUP == group)
+    {
+        reg &= 0xffff0000;
+        reg |= data;
+    }
+    else
+    {
+        reg &= 0xffff;
+        reg |= (data << 16);
+    }
+
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                             led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    a_uint32_t data = 0, reg, tmp;
+    a_uint32_t addr;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (group >= LED_GROUP_BUTT)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (id > MAX_LED_PATTERN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t));
+
+    addr = LED_PATTERN_ADDR + (id << 2);
+
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_LAN_PORT_GROUP == group)
+    {
+        data = reg & 0xffff;
+    }
+    else
+    {
+        data = (reg >> 16) & 0xffff;
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data);
+    if (0 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_OFF;
+    }
+    else if (1 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_BLINK;
+    }
+    else if (2 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_ON;
+    }
+    else
+    {
+        pattern->mode = LED_PATTERN_MAP_EN;
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << POWER_ON_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_1000M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_100M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_10M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << COLLISION_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << RX_TRAFFIC_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << TX_TRAFFIC_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINKUP_OVERRIDE_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data);
+    if (0 == tmp)
+    {
+        pattern->freq = LED_BLINK_2HZ;
+    }
+    else if (1 == tmp)
+    {
+        pattern->freq = LED_BLINK_4HZ;
+    }
+    else if (2 == tmp)
+    {
+        pattern->freq = LED_BLINK_8HZ;
+    }
+    else
+    {
+        pattern->freq = LED_BLINK_TXRX;
+    }
+
+    return SW_OK;
+}
+
+/**
+* @brief Set led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group  pattern group, lan or wan
+* @param[in] id pattern id
+* @param[in] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+garuda_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                            led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_led_ctrl_pattern_set(dev_id, group, id, pattern);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Get led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group  pattern group, lan or wan
+* @param[in] id pattern id
+* @param[out] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+garuda_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                            led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_led_ctrl_pattern_get(dev_id, group, id, pattern);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+garuda_led_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->led_ctrl_pattern_set = garuda_led_ctrl_pattern_set;
+        p_api->led_ctrl_pattern_get = garuda_led_ctrl_pattern_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/garuda/garuda_mib.c b/qca-ssdk/src/hsl/garuda/garuda_mib.c
new file mode 100755
index 0000000..9e1fe74
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_mib.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_mib GARUDA_MIB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_mib.h"
+#include "garuda_reg.h"
+
+static sw_error_t
+_garuda_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_mib_info_t * mib_info)
+{
+    a_uint32_t val;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFcsErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxAllignErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxRunt = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFragment = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxTooLong = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxOverFlow = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Filtered = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxUnderRun = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxOverSize = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxCollision = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxAbortCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMultiCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxSingalCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxExcDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxLateCol = val;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Get mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                    fal_mib_info_t * mib_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_get_mib_info(dev_id, port_id, mib_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_mib_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_mib_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+garuda_mib_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->get_mib_info   = garuda_get_mib_info;
+    p_api->mib_status_set = garuda_mib_status_set;
+    p_api->mib_status_get = garuda_mib_status_get;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/garuda/garuda_mirror.c b/qca-ssdk/src/hsl/garuda/garuda_mirror.c
new file mode 100755
index 0000000..88b78f1
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_mirror.c
@@ -0,0 +1,318 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_mirror GARUDA_MIRROR
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_mirror.h"
+#include "garuda_reg.h"
+
+static sw_error_t
+_garuda_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = port_id;
+    HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *port_id = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+ *   @details  Comments:
+ *   The analysis port works for both ingress and egress mirror.
+ * @brief Set mirror analyzer port on particular a device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_mirr_analysis_port_set(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mirror analysis port on particular a device.
+ * @param[in] dev_id device id
+ * @param[out] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_mirr_analysis_port_get(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_mirr_port_in_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_mirr_port_in_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_mirr_port_eg_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_mirr_port_eg_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+garuda_mirr_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->mirr_analysis_port_set = garuda_mirr_analysis_port_set;
+        p_api->mirr_analysis_port_get = garuda_mirr_analysis_port_get;
+        p_api->mirr_port_in_set = garuda_mirr_port_in_set;
+        p_api->mirr_port_in_get = garuda_mirr_port_in_get;
+        p_api->mirr_port_eg_set = garuda_mirr_port_eg_set;
+        p_api->mirr_port_eg_get = garuda_mirr_port_eg_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/garuda/garuda_misc.c b/qca-ssdk/src/hsl/garuda/garuda_misc.c
new file mode 100755
index 0000000..73ba5ef
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_misc.c
@@ -0,0 +1,1009 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_misc GARUDA_MISC
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_misc.h"
+#include "garuda_reg.h"
+
+#define GARUDA_MAX_FRMAE_SIZE      9216
+
+
+static sw_error_t
+_garuda_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, ARP_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_arp_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, ARP_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (GARUDA_MAX_FRMAE_SIZE < size)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = size;
+    HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *size = data;
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 0, data);
+    }
+    else if (FAL_MAC_DROP == cmd)
+    {
+        SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
+        SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 1, data);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
+        SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 0, data);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_fwd_cmd_t * action)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+    a_uint32_t port_lock_en, port_drop_en;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_CTL, PORT_LOCK_EN, port_lock_en, data);
+    SW_GET_FIELD_BY_REG(PORT_CTL, LOCK_DROP_EN, port_drop_en, data);
+
+    if (1 == port_lock_en)
+    {
+        if (1 == port_drop_en)
+        {
+            *action = FAL_MAC_DROP;
+        }
+        else
+        {
+            *action = FAL_MAC_RDT_TO_CPU;
+        }
+    }
+    else
+    {
+        *action = FAL_MAC_FRWRD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t)0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t)0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, BROAD_TO_CPU,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BROAD_TO_CPU,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_FRWRD;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+
+static sw_error_t
+_garuda_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, DHCP_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, DHCP_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_arp_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_arp_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_arp_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max frame size which device can received on a particular device.
+ * @details    Comments:
+ * The granularity of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[in] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_frame_max_size_set(dev_id, size);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max frame size which device can received on a particular device.
+ * @details   Comments:
+ *    The unit of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[out] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_frame_max_size_get(dev_id, size);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set forwarding command for packets which source address is unknown on a particular port.
+ * @details Comments:
+ *    Particular device may only support parts of forwarding commands.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_unk_sa_cmd_set(dev_id, port_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get forwarding command for packets which source address is unknown on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_fwd_cmd_t * action)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_unk_sa_cmd_get(dev_id, port_id, action);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown unicast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown unicast packets filter on one port then unknown
+ *   unicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_unk_uc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flooding status of unknown unicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_unk_uc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown multicast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown multicast packets filter on one port then unknown
+ *   multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_unk_mc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/** @brief Get flooding status of unknown multicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_unk_mc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_cpu_port_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_cpu_port_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of braodcast packets broadcasting to cpu on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_bc_to_cpu_port_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get status of braodcast packets broadcasting to cpu on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_bc_to_cpu_port_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set pppoe packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling pppoe packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_pppoe_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get pppoe packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_pppoe_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set pppoe packets hardware acknowledgement status on particular device.
+ * @details     comments:
+ *   Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_pppoe_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get pppoe packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_pppoe_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dhcp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_dhcp_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dhcp packets hardware acknowledgement status on particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_dhcp_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+garuda_misc_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->arp_status_set = garuda_arp_status_set;
+        p_api->arp_status_get = garuda_arp_status_get;
+        p_api->frame_max_size_set = garuda_frame_max_size_set;
+        p_api->frame_max_size_get = garuda_frame_max_size_get;
+        p_api->port_unk_sa_cmd_set = garuda_port_unk_sa_cmd_set;
+        p_api->port_unk_sa_cmd_get = garuda_port_unk_sa_cmd_get;
+        p_api->port_unk_uc_filter_set = garuda_port_unk_uc_filter_set;
+        p_api->port_unk_uc_filter_get = garuda_port_unk_uc_filter_get;
+        p_api->port_unk_mc_filter_set = garuda_port_unk_mc_filter_set;
+        p_api->port_unk_mc_filter_get = garuda_port_unk_mc_filter_get;
+        p_api->cpu_port_status_set = garuda_cpu_port_status_set;
+        p_api->cpu_port_status_get = garuda_cpu_port_status_get;
+        p_api->bc_to_cpu_port_set = garuda_bc_to_cpu_port_set;
+        p_api->bc_to_cpu_port_get = garuda_bc_to_cpu_port_get;
+        p_api->pppoe_cmd_set = garuda_pppoe_cmd_set;
+        p_api->pppoe_cmd_get = garuda_pppoe_cmd_get;
+        p_api->pppoe_status_set = garuda_pppoe_status_set;
+        p_api->pppoe_status_get = garuda_pppoe_status_get;
+        p_api->port_dhcp_set = garuda_port_dhcp_set;
+        p_api->port_dhcp_get = garuda_port_dhcp_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/garuda/garuda_port_ctrl.c b/qca-ssdk/src/hsl/garuda/garuda_port_ctrl.c
new file mode 100755
index 0000000..839db8c
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_port_ctrl.c
@@ -0,0 +1,1069 @@
+/*
+ * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_port_ctrl GARUDA_PORT_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_port_ctrl.h"
+#include "garuda_reg.h"
+#include "hsl_phy.h"
+
+static sw_error_t
+_garuda_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_port_duplex_t duplex)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    a_uint32_t reg_save = 0;
+    a_uint32_t reg_val = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_duplex_set)
+    	  return SW_NOT_SUPPORTED;
+
+    if (FAL_DUPLEX_BUTT <= duplex)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    //save reg value
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+    reg_save = reg_val;
+
+    SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+    //set mac be config by sw   and turn off RX TX MAC_EN
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+    rv = phy_drv->phy_duplex_set(dev_id, phy_id, duplex);
+
+    //retore reg value
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_save), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_port_duplex_t * pduplex)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_duplex_get)
+         return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_duplex_get(dev_id, phy_id, pduplex);
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_port_speed_t speed)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+ 
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_speed_set)
+         return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_SPEED_1000 < speed)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = phy_drv->phy_speed_set(dev_id, phy_id, speed);
+
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_port_speed_t * pspeed)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_speed_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_speed_get(dev_id, phy_id, pspeed);
+
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * status)
+{
+    a_uint32_t phy_id;
+    sw_error_t rv;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_autoneg_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *status = phy_drv->phy_autoneg_status_get (dev_id, phy_id);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_autoneg_enable_set)
+ 	  return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_autoneg_enable_set(dev_id, phy_id);
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_restart_autoneg)
+	 return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_restart_autoneg(dev_id, phy_id);
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t autoadv)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_autoneg_adv_set)
+    	 return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_autoneg_adv_set(dev_id, phy_id, autoadv);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * autoadv)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_autoneg_adv_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *autoadv = 0;
+    rv = phy_drv->phy_autoneg_adv_get(dev_id, phy_id, autoadv);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, HEAD_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, HEAD_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val, force, reg;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+    if (force)
+    {
+        /* flow control isn't in force mode so can't set */
+        return SW_DISABLE;
+    }
+
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t tx, rx, reg;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg);
+    SW_GET_FIELD_BY_REG(PORT_STATUS, TX_FLOW_EN, tx, reg);
+
+    if (1 == rx)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t force, reg;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+    if (force != (a_uint32_t) enable)
+    {
+        return SW_OK;
+    }
+
+    if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 0, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, 0, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t force, reg;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+    if (0 == force)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+   SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+   if (NULL == phy_drv->phy_powersave_set)
+	 return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_powersave_set(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_powersave_get)
+         return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_powersave_get(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_hibernation_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_hibernation_set(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_hibernation_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_hibernation_get(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+                 fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_cdt)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_cdt(dev_id, phy_id, mdi_pair, cable_status, cable_len);
+
+    return rv;
+}
+
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_port_duplex_t duplex)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_duplex_set(dev_id, port_id, duplex);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_port_duplex_t * pduplex)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_duplex_get(dev_id, port_id, pduplex);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_speed_t speed)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_speed_set(dev_id, port_id, speed);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_speed_t * pspeed)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_speed_get(dev_id, port_id, pspeed);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_autoneg_status_get(dev_id, port_id, status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_autoneg_enable(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_autoneg_restart(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ *   @details  Comments:
+ *   auto negotiation advtisement ability is defined by macro such as
+ *   FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t autoadv)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_autoneg_adv_set(dev_id, port_id, autoadv);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * autoadv)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_autoneg_adv_get(dev_id, port_id, autoadv);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_hdr_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_hdr_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_flowctrl_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_flowctrl_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_flowctrl_forcemode_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_flowctrl_forcemode_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_powersave_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_powersave_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_hibernate_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_hibernate_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Run cable diagnostic test on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mdi_pair mdi pair id
+ * @param[out] cable_status cable status
+ * @param[out] cable_len cable len
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+                fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+garuda_port_ctrl_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->port_duplex_get = garuda_port_duplex_get;
+        p_api->port_duplex_set = garuda_port_duplex_set;
+        p_api->port_speed_get = garuda_port_speed_get;
+        p_api->port_speed_set = garuda_port_speed_set;
+        p_api->port_autoneg_status_get = garuda_port_autoneg_status_get;
+        p_api->port_autoneg_enable = garuda_port_autoneg_enable;
+        p_api->port_autoneg_restart = garuda_port_autoneg_restart;
+        p_api->port_autoneg_adv_get = garuda_port_autoneg_adv_get;
+        p_api->port_autoneg_adv_set = garuda_port_autoneg_adv_set;
+        p_api->port_hdr_status_set = garuda_port_hdr_status_set;
+        p_api->port_hdr_status_get = garuda_port_hdr_status_get;
+        p_api->port_flowctrl_set = garuda_port_flowctrl_set;
+        p_api->port_flowctrl_get = garuda_port_flowctrl_get;
+        p_api->port_flowctrl_forcemode_set = garuda_port_flowctrl_forcemode_set;
+        p_api->port_flowctrl_forcemode_get = garuda_port_flowctrl_forcemode_get;
+        p_api->port_powersave_set = garuda_port_powersave_set;
+        p_api->port_powersave_get = garuda_port_powersave_get;
+        p_api->port_hibernate_set = garuda_port_hibernate_set;
+        p_api->port_hibernate_get = garuda_port_hibernate_get;
+        p_api->port_cdt           = garuda_port_cdt;
+
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/garuda/garuda_portvlan.c b/qca-ssdk/src/hsl/garuda/garuda_portvlan.c
new file mode 100755
index 0000000..38986bc
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_portvlan.c
@@ -0,0 +1,912 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+ * @defgroup garuda_port_vlan GARUDA_PORT_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_portvlan.h"
+#include "garuda_reg.h"
+
+#define MAX_VLAN_ID         4095
+
+
+static sw_error_t
+_garuda_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_1Q_MODE_BUTT <= port_1qmode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+                      (a_uint8_t *) (&regval[port_1qmode]),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+
+static sw_error_t
+_garuda_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK,
+                                  FAL_1Q_CHECK, FAL_1Q_SECURE
+                                };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(pport_1qmode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    *pport_1qmode = retval[regval & 0x3];
+
+    return SW_OK;
+
+}
+
+
+static sw_error_t
+_garuda_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_EG_MODE_BUTT <= port_egvlanmode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_EG_HYBRID == port_egvlanmode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+                      (a_uint8_t *) (&regval[port_egvlanmode]),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+
+static sw_error_t
+_garuda_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_1q_egmode_t retval[3] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED,
+                                     FAL_EG_TAGGED
+                                   };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(pport_egvlanmode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    *pport_egvlanmode = retval[regval & 0x3];
+
+    return SW_OK;
+
+}
+
+
+static sw_error_t
+_garuda_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    regval |= (0x1UL << mem_port_id);
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+static sw_error_t
+_garuda_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    regval &= (~(0x1UL << mem_port_id));
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+
+static sw_error_t
+_garuda_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE ==
+            hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&mem_port_map),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    *mem_port_map = 0;
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) mem_port_map,
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((0 == vid) || (vid > MAX_VLAN_ID))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = vid;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+
+    *vid = val & 0xfff;
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      FORCE_DEF_VID, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      FORCE_DEF_VID, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      FORCE_PVLAN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      FORCE_PVLAN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id,
+                      DTAG_EN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id,
+                      DTAG_EN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    val = tpid;
+    HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+                      TAG_VALUE, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+                      TAG_VALUE, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *tpid = val;
+    return SW_OK;
+}
+
+/**
+ * @brief Set 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_1qmode_set(dev_id, port_id, port_1qmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_1qmode_get(dev_id, port_id, pport_1qmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_portvlan_member_add(dev_id, port_id, mem_port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_portvlan_member_del(dev_id, port_id, mem_port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Update member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_portvlan_member_update(dev_id, port_id, mem_port_map);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_portvlan_member_get(dev_id, port_id, mem_port_map);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default vlan id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid default vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_default_vid_set(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default vlan id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid default vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_default_vid_get(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_force_default_vid_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_force_default_vid_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_force_portvlan_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_force_portvlan_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set nest vlan feature status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_nestvlan_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get nest vlan feature status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_port_nestvlan_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_nestvlan_tpid_set(dev_id, tpid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_nestvlan_tpid_get(dev_id, tpid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+garuda_portvlan_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->port_1qmode_get = garuda_port_1qmode_get;
+    p_api->port_1qmode_set = garuda_port_1qmode_set;
+    p_api->port_egvlanmode_get = garuda_port_egvlanmode_get;
+    p_api->port_egvlanmode_set = garuda_port_egvlanmode_set;
+    p_api->portvlan_member_add = garuda_portvlan_member_add;
+    p_api->portvlan_member_del = garuda_portvlan_member_del;
+    p_api->portvlan_member_update = garuda_portvlan_member_update;
+    p_api->portvlan_member_get = garuda_portvlan_member_get;
+    p_api->port_default_vid_set = garuda_port_default_vid_set;
+    p_api->port_default_vid_get = garuda_port_default_vid_get;
+    p_api->port_force_default_vid_set = garuda_port_force_default_vid_set;
+    p_api->port_force_default_vid_get = garuda_port_force_default_vid_get;
+    p_api->port_force_portvlan_set = garuda_port_force_portvlan_set;
+    p_api->port_force_portvlan_get = garuda_port_force_portvlan_get;
+    p_api->port_nestvlan_set = garuda_port_nestvlan_set;
+    p_api->port_nestvlan_get = garuda_port_nestvlan_get;
+    p_api->nestvlan_tpid_set = garuda_nestvlan_tpid_set;
+    p_api->nestvlan_tpid_get = garuda_nestvlan_tpid_get;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/garuda/garuda_qos.c b/qca-ssdk/src/hsl/garuda/garuda_qos.c
new file mode 100755
index 0000000..f1c367a
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_qos.c
@@ -0,0 +1,1191 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_qos GARUDA_QOS
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_qos.h"
+#include "garuda_reg.h"
+
+#define GARUDA_QOS_QUEUE_TX_BUFFER_MAX 60
+#define GARUDA_QOS_PORT_TX_BUFFER_MAX  252
+
+//#define GARUDA_MIN_QOS_MODE_PRI 0
+#define GARUDA_MAX_QOS_MODE_PRI 3
+
+static sw_error_t
+_garuda_qos_sch_mode_set(a_uint32_t dev_id,
+                         fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+    a_uint32_t val, wrr, mix;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SCH_SP_MODE == mode)
+    {
+        wrr = 0;
+        mix = 0;
+    }
+    else if (FAL_SCH_WRR_MODE == mode)
+    {
+        wrr = 1;
+        mix = 0;
+    }
+    else if (FAL_SCH_MIX_MODE == mode)
+    {
+        wrr = 1;
+        mix = 1;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_CTL, 0, (a_uint32_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(GLOBAL_CTL, WEIGHT_PRIORITY, wrr, val);
+    SW_SET_REG_BY_FIELD(GLOBAL_CTL, MIX_PRIORITY, mix, val);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GLOBAL_CTL, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_qos_sch_mode_get(a_uint32_t dev_id,
+                         fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+    a_uint32_t idx, val, wrr, mix;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_CTL, 0, (a_uint32_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(GLOBAL_CTL, WEIGHT_PRIORITY, wrr, val);
+    SW_GET_FIELD_BY_REG(GLOBAL_CTL, MIX_PRIORITY, mix, val);
+
+    if (0 == wrr)
+    {
+        *mode = FAL_SCH_SP_MODE;
+        for (idx = 0; idx < 4; idx++)
+        {
+            weight[idx] = 0;
+        }
+    }
+    else
+    {
+        if (0 == mix)
+        {
+            *mode = FAL_SCH_WRR_MODE;
+            weight[0] = 1;
+            for (idx = 1; idx < 4; idx++)
+            {
+                weight[idx] = weight[idx - 1] << 1;
+            }
+        }
+        else
+        {
+            *mode = FAL_SCH_MIX_MODE;
+            weight[3] = 0;
+            weight[2] = 4;
+            weight[1] = 2;
+            weight[0] = 1;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t * enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_queue_t queue_id, a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (GARUDA_QOS_QUEUE_TX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = *number / 4;
+    *number = val << 2;
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_queue_t queue_id, a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    *number = val << 2;
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (GARUDA_QOS_PORT_TX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = *number / 4;
+    *number = val << 2;
+    HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *number = val << 2;
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+                            fal_queue_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+    hsl_dev_t *p_dev = NULL;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_DOT1P_MAX < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+    if (p_dev->nr_queue <= queue)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = queue;
+    HSL_REG_FIELD_GEN_SET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2,
+                          (a_uint16_t) (up << 1), (a_uint8_t *) (&val),
+                          sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+                            fal_queue_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_DOT1P_MAX < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GEN_GET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2,
+                          (a_uint16_t) (up << 1), (a_uint8_t *) (&val),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *queue = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+                              fal_queue_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+    a_uint32_t offsetaddr;
+    a_uint16_t fieldoffset;
+    hsl_dev_t *p_dev = NULL;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_DSCP_MAX < dscp)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+    if (p_dev->nr_queue <= queue)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    offsetaddr = (dscp >> 4) << 2;
+    fieldoffset = (dscp & 0xf) << 1;
+
+    val = queue;
+    HSL_REG_FIELD_GEN_SET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr),
+                          2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+                              fal_queue_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+    a_uint32_t offsetaddr;
+    a_uint16_t fieldoffset;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_DSCP_MAX < dscp)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    offsetaddr = (dscp / 16) << 2;
+    fieldoffset = (dscp & 0xf) << 1;
+
+    HSL_REG_FIELD_GEN_GET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr),
+                          2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *queue = val;
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_qos_mode_t mode, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_PORT_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_qos_mode_t mode, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_PORT_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_qos_mode_t mode, a_uint32_t pri)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (GARUDA_MAX_QOS_MODE_PRI < pri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_PORT_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, PORT_PRI_SEL, pri, val);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_qos_mode_t mode, a_uint32_t * pri)
+{
+    sw_error_t rv;
+    a_uint32_t entry, f_val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_PORT_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, PORT_PRI_SEL, f_val, entry);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    *pri = f_val;
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t up)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_DOT1P_MAX < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = up;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, ING_PRI,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * up)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, ING_PRI,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *up = val;
+    return SW_OK;
+}
+
+/**
+ * @brief Set traffic scheduling mode on particular one device.
+ *   @details   Comments:
+ *   GARUDA doesn't support variable weight in wrr mode, the weight for four queues
+ *   are 8:4:2:1.
+ *   When scheduling mode is sp the weight is meaningless usually it's zero
+ *  When scheduling mode is sp the weight for four queues are 0:4:2:1
+ * @param[in] dev_id device id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[in] weight[] weight value for each queue when in wrr mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_sch_mode_set(a_uint32_t dev_id,
+                        fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_sch_mode_set(dev_id, mode, weight);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get traffic scheduling mode on particular device.
+ * @param[in] dev_id device id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[out] weight weight value for wrr mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_sch_mode_get(a_uint32_t dev_id,
+                        fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_sch_mode_get(dev_id, mode, weight);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting queue on one particular port.
+ *   @details  Comments:
+ *    If enable queue tx buffer on one port that means each queue of this port
+ *    will have fixed number buffers when transmitting packets. Otherwise they
+ *    share the whole buffers with other queues in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_queue_tx_buf_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting queue on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_queue_tx_buf_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting port on one particular port.
+ *   @details  Comments:
+    If enable tx buffer on one port that means this port will have fixed
+    number buffers when transmitting packets. Otherwise they will
+    share the whole buffers with other ports in device.
+ *    function will return actual buffer numbers in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_port_tx_buf_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_port_tx_buf_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting queue on one particular port.
+ *   @details   Comments:
+    The step of buffer number in GARUDA is 4, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for queue is 4 to 60.
+ *    share the whole buffers with other ports in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting queue on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting port on one particular port.
+ *   @details   Comments:
+    The step of buffer number in GARUDA is four, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for transmitting port is 4 to 124.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_port_tx_buf_nr_set(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_port_tx_buf_nr_get(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set user priority to mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dot1p 802.1p
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+                           fal_queue_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_cosmap_up_queue_set(dev_id, up, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get user priority to mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dot1p 802.1p
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+                           fal_queue_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_cosmap_up_queue_get(dev_id, up, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+                             fal_queue_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_cosmap_dscp_queue_set(dev_id, dscp, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+                             fal_queue_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_cosmap_dscp_queue_get(dev_id, dscp, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_qos_mode_t mode, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_port_mode_set(dev_id, port_id, mode, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_qos_mode_t mode, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_port_mode_get(dev_id, port_id, mode, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set priority of one particular qos mode on one particular port.
+ *   @details   Comments:
+    If the priority of a mode is more small then the priority is more high.
+    Differnet mode should have differnet priority.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_qos_mode_t mode, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get priority of one particular qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_qos_mode_t mode, a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] up 802.1p
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t up)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_port_default_up_set(dev_id, port_id, up);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] up 802.1p
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * up)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_qos_port_default_up_get(dev_id, port_id, up);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+garuda_qos_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->qos_sch_mode_set = garuda_qos_sch_mode_set;
+        p_api->qos_sch_mode_get = garuda_qos_sch_mode_get;
+        p_api->qos_queue_tx_buf_status_set = garuda_qos_queue_tx_buf_status_set;
+        p_api->qos_queue_tx_buf_status_get = garuda_qos_queue_tx_buf_status_get;
+        p_api->qos_port_tx_buf_status_set = garuda_qos_port_tx_buf_status_set;
+        p_api->qos_port_tx_buf_status_get = garuda_qos_port_tx_buf_status_get;
+        p_api->qos_queue_tx_buf_nr_set = garuda_qos_queue_tx_buf_nr_set;
+        p_api->qos_queue_tx_buf_nr_get = garuda_qos_queue_tx_buf_nr_get;
+        p_api->qos_port_tx_buf_nr_set = garuda_qos_port_tx_buf_nr_set;
+        p_api->qos_port_tx_buf_nr_get = garuda_qos_port_tx_buf_nr_get;
+        p_api->cosmap_up_queue_set = garuda_cosmap_up_queue_set;
+        p_api->cosmap_up_queue_get = garuda_cosmap_up_queue_get;
+        p_api->cosmap_dscp_queue_set = garuda_cosmap_dscp_queue_set;
+        p_api->cosmap_dscp_queue_get = garuda_cosmap_dscp_queue_get;
+        p_api->qos_port_mode_set = garuda_qos_port_mode_set;
+        p_api->qos_port_mode_get = garuda_qos_port_mode_get;
+        p_api->qos_port_mode_pri_set = garuda_qos_port_mode_pri_set;
+        p_api->qos_port_mode_pri_get = garuda_qos_port_mode_pri_get;
+        p_api->qos_port_default_up_set = garuda_qos_port_default_up_set;
+        p_api->qos_port_default_up_get = garuda_qos_port_default_up_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/garuda/garuda_rate.c b/qca-ssdk/src/hsl/garuda/garuda_rate.c
new file mode 100755
index 0000000..8bd9cac
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_rate.c
@@ -0,0 +1,851 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+ * @defgroup garuda_rate GARUDA_RATE
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_rate.h"
+#include "garuda_reg.h"
+
+#define GARUDA_STORM_MIN_RATE_PPS 1000
+#define GARUDA_STORM_MAX_RATE_PPS (1024 * 1000)
+
+static sw_error_t
+garuda_stormrate_sw_to_hw(a_uint32_t swrate, a_uint32_t * hwrate)
+{
+    a_uint32_t shrnr = 0;
+    a_uint32_t tmp = swrate / 1000;
+
+    if ((GARUDA_STORM_MIN_RATE_PPS > swrate)
+            || (GARUDA_STORM_MAX_RATE_PPS < swrate))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    while ((tmp != 0) && (shrnr < 12))
+    {
+        tmp = tmp >> 1;
+        shrnr++;
+    }
+
+    if (12 == shrnr)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    *hwrate = shrnr;
+    return SW_OK;
+}
+
+static sw_error_t
+garuda_stormrate_hw_to_sw(a_uint32_t hwrate, a_uint32_t * swrate)
+{
+    if (0 == hwrate)
+    {
+        hwrate = 1;
+    }
+
+    if ((1 > hwrate) || (11 < hwrate))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    *swrate = (1 << (hwrate - 1)) * 1000;
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_queue_t queue_id, a_uint32_t * speed,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+    a_uint32_t portrl;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+                      (a_uint8_t *) (&portrl), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        if (1 == portrl)
+        {
+            /* already enable port egress rate limit, queue and port
+               egress rate limit can't coexist */
+            return SW_NOT_SUPPORTED;
+        }
+
+        if ((0x7ffe << 5) < *speed)
+        {
+            return SW_BAD_PARAM;
+        }
+        val = *speed >> 5;
+        *speed = val << 5;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0x7fff;
+        *speed = 0;
+        if (1 == portrl)
+        {
+            /* already enable port egress rate limit */
+            return SW_OK;
+        }
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_garuda_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_queue_t queue_id, a_uint32_t * speed,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        /* already enable port egress rate limit */
+        *speed = 0;
+        *enable = A_FALSE;
+
+        return SW_OK;
+    }
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (0x7fff == val)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+        *speed = val << 5;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+    a_uint32_t portrl;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+                      (a_uint8_t *) (&portrl), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_FALSE == enable)
+    {
+        *speed = 0;
+
+        /* if port egress rate limit current enable then disable */
+        if (1 == portrl)
+        {
+            val = 0;
+            HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+                              (a_uint8_t *) (&val), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            val = 0x7fff;
+            HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+                              (a_uint8_t *) (&val), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+        }
+
+        rv = SW_OK;
+    }
+    else
+    {
+        if ((0x7ffe << 5) < *speed)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        /* not enable egress port rate limit */
+        if (0 == portrl)
+        {
+            HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE,
+                              (a_uint8_t *) (&val), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            if (0x7fff != val)
+            {
+                /* already enable egress queue0 rate limit, queue and port
+                   egress rate limit can't coexist */
+                return SW_NOT_SUPPORTED;
+            }
+
+            HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE,
+                              (a_uint8_t *) (&val), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            if (0x7fff != val)
+            {
+                /* already enable egress queue1 rate limit, queue and port
+                   egress rate limit can't coexist */
+                return SW_NOT_SUPPORTED;
+            }
+
+            HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE,
+                              (a_uint8_t *) (&val), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            if (0x7fff != val)
+            {
+                /* already enable egress queue2 rate limit, queue and port
+                   egress rate limit can't coexist */
+                return SW_NOT_SUPPORTED;
+            }
+
+            HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+                              (a_uint8_t *) (&val), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            if (0x7fff != val)
+            {
+                /* already enable egress queue3 rate limit, queue and port
+                   egress rate limit can't coexist */
+                return SW_NOT_SUPPORTED;
+            }
+
+            val = 1;
+            HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+                              (a_uint8_t *) (&val), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+        }
+
+        val = *speed >> 5;
+        *speed = val << 5;
+        HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_garuda_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == val)
+    {
+        *speed = 0;
+        *enable = A_FALSE;
+        return SW_OK;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    *enable = A_TRUE;
+    *speed = val << 5;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        if ((0x7ffe << 5) < *speed)
+        {
+            return SW_BAD_PARAM;
+        }
+        val = *speed >> 5;
+        *speed = val << 5;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0x7fff;
+        *speed = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0x7fff == val)
+    {
+        *enable = A_FALSE;
+        *speed = 0;
+    }
+    else
+    {
+        *enable = A_TRUE;
+        *speed = val << 5;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_storm_type_t storm_type, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_UNICAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, UNI_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_MULTICAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, MUL_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_BROADCAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, BRO_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        data = 1;
+        HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_storm_type_t storm_type, a_bool_t * enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_UNICAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, UNI_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_MULTICAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, MUL_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_BROADCAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, BRO_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        data = 1;
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * rate_in_pps)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = garuda_stormrate_sw_to_hw(*rate_in_pps, &data);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = garuda_stormrate_hw_to_sw(data, rate_in_pps);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * rate_in_pps)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = garuda_stormrate_hw_to_sw(data, rate_in_pps);
+    return rv;
+}
+
+/**
+ * @brief Set queue egress rate limit status on one particular port and queue.
+ *   @details   Comments:
+    The granularity of speed is bps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable queue egress rate limit input parameter speed is meaningless.
+    Egress queue rate limit can't coexist with port egress rate limit.
+    The step of speed is 32kbps.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_queue_t queue_id, a_uint32_t * speed,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_rate_queue_egrl_set(dev_id, port_id, queue_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get queue egress rate limit status on one particular port and queue.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_queue_t queue_id, a_uint32_t * speed,
+                           a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_rate_queue_egrl_get(dev_id, port_id, queue_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port egress rate limit status on one particular port.
+ *   @details   Comments:
+    The granularity of speed is bps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port egress rate limit input parameter speed is meaningless.
+    Egress port rate limit can't coexist with queue egress rate limit.
+    The step of speed is 32kbps.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_rate_port_egrl_set(dev_id, port_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port egress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_rate_port_egrl_get(dev_id, port_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port ingress rate limit status on one particular port.
+ *   @details   Comments:
+    The granularity of speed is bps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port ingress rate limit input parameter speed is meaningless.
+    The step of speed is 32kbps.
+ *    When disable port ingress rate limit input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_rate_port_inrl_set(dev_id, port_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port ingress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_rate_port_inrl_get(dev_id, port_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set particular type storm control status on one particular port.
+ *   @details   Comments:
+ *    When enable one particular packets type storm control this type packets
+ *    speed will be calculated in storm control.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_storm_type_t storm_type, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_storm_ctrl_frame_set(dev_id, port_id, storm_type, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get particular type storm control status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_storm_type_t storm_type, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_storm_ctrl_frame_get(dev_id, port_id, storm_type, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set storm control speed on one particular port.
+ *   @details   Comments:
+    Because of hardware granularity function will return actual speed in hardware.
+    The step of speed is kpps.
+    The speed range is from 1k to 1M
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed storm control speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * rate_in_pps)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_storm_ctrl_rate_set(dev_id, port_id, rate_in_pps);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get storm control speed on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed storm control speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * rate_in_pps)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_storm_ctrl_rate_get(dev_id, port_id, rate_in_pps);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+garuda_rate_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->rate_queue_egrl_set = garuda_rate_queue_egrl_set;
+        p_api->rate_queue_egrl_get = garuda_rate_queue_egrl_get;
+        p_api->rate_port_egrl_set = garuda_rate_port_egrl_set;
+        p_api->rate_port_egrl_get = garuda_rate_port_egrl_get;
+        p_api->rate_port_inrl_set = garuda_rate_port_inrl_set;
+        p_api->rate_port_inrl_get = garuda_rate_port_inrl_get;
+        p_api->storm_ctrl_frame_set = garuda_storm_ctrl_frame_set;
+        p_api->storm_ctrl_frame_get = garuda_storm_ctrl_frame_get;
+        p_api->storm_ctrl_rate_set = garuda_storm_ctrl_rate_set;
+        p_api->storm_ctrl_rate_get = garuda_storm_ctrl_rate_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/garuda/garuda_reduced_acl.c b/qca-ssdk/src/hsl/garuda/garuda_reduced_acl.c
new file mode 100755
index 0000000..73d2a5a
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_reduced_acl.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "garuda_reduced_acl.h"
+#include "hsl.h"
+
+#define GARUDA_RULE_VLU_ADDR  0x58400
+#define GARUDA_RULE_MSK_ADDR  0x58c00
+#define GARUDA_RULE_ACT_ADDR  0x58000
+#define GARUDA_RULE_SLCT_ADDR 0x58800
+
+sw_error_t
+garuda_acl_rule_write(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+                      a_uint32_t msk[8])
+{
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    /* set rule value */
+    base = GARUDA_RULE_VLU_ADDR + (rule_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(vlu[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* set rule mask */
+    base = GARUDA_RULE_MSK_ADDR + (rule_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(msk[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+garuda_acl_action_write(a_uint32_t dev_id, a_uint32_t act_idx,
+                        a_uint32_t act)
+{
+    sw_error_t rv;
+    a_uint32_t addr;
+
+    /* set rule action */
+    addr = GARUDA_RULE_ACT_ADDR + (act_idx << 5);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&act), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+sw_error_t
+garuda_acl_slct_write(a_uint32_t dev_id, a_uint32_t slct_idx,
+                      a_uint32_t slct[8])
+{
+    sw_error_t rv;
+    a_uint32_t base, addr;
+    a_uint32_t i;
+
+    base = GARUDA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+    /* set rule address */
+    for (i = 1; i < 7; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(slct[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* set rule enable */
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(slct[0])),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+sw_error_t
+garuda_acl_rule_read(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+                     a_uint32_t msk[8])
+{
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    /* get rule value */
+    base = GARUDA_RULE_VLU_ADDR + (rule_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(vlu[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* get rule mask */
+    base = GARUDA_RULE_MSK_ADDR + (rule_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(msk[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+garuda_acl_action_read(a_uint32_t dev_id, a_uint32_t act_idx,
+                       a_uint32_t * act)
+{
+    sw_error_t rv;
+    a_uint32_t addr;
+
+    /* get rule action */
+    addr = GARUDA_RULE_ACT_ADDR + (act_idx << 5);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) act, sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+sw_error_t
+garuda_acl_slct_read(a_uint32_t dev_id, a_uint32_t slct_idx,
+                     a_uint32_t slct[8])
+{
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    base = GARUDA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+    /* get filter address and enable */
+    for (i = 0; i < 7; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(slct[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
diff --git a/qca-ssdk/src/hsl/garuda/garuda_reg_access.c b/qca-ssdk/src/hsl/garuda/garuda_reg_access.c
new file mode 100755
index 0000000..2fb0784
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_reg_access.c
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "sd.h"
+#include "garuda_reg_access.h"
+
+static hsl_access_mode reg_mode;
+
+#if defined(API_LOCK)
+static aos_lock_t mdio_lock;
+#define MDIO_LOCKER_INIT    aos_lock_init(&mdio_lock)
+#define MDIO_LOCKER_LOCK    aos_lock(&mdio_lock)
+#define MDIO_LOCKER_UNLOCK  aos_unlock(&mdio_lock)
+#else
+#define MDIO_LOCKER_INIT
+#define MDIO_LOCKER_LOCK
+#define MDIO_LOCKER_UNLOCK
+#endif
+
+static sw_error_t
+_garuda_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                     a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_word_addr;
+    a_uint32_t phy_addr, reg_val;
+    a_uint16_t phy_val, tmp_val;
+    a_uint8_t phy_reg;
+    sw_error_t rv;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    /* change reg_addr to 16-bit word address, 32-bit aligned */
+    reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+    /* configure register high address */
+    phy_addr = 0x18;
+    phy_reg = 0x0;
+    phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    /* For some registers such as MIBs, since it is read/clear, we should */
+    /* read the lower 16-bit register then the higher one */
+
+    /* read register in lower address */
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+    SW_RTN_ON_ERROR(rv);
+    reg_val = tmp_val;
+
+    /* read register in higher address */
+    reg_word_addr++;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+    SW_RTN_ON_ERROR(rv);
+    reg_val |= (((a_uint32_t)tmp_val) << 16);
+
+    aos_mem_copy(value, &reg_val, sizeof (a_uint32_t));
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                     a_uint32_t value_len)
+{
+    a_uint32_t reg_word_addr;
+    a_uint32_t phy_addr, reg_val;
+    a_uint16_t phy_val;
+    a_uint8_t phy_reg;
+    sw_error_t rv;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    aos_mem_copy(&reg_val, value, sizeof (a_uint32_t));
+
+    /* change reg_addr to 16-bit word address, 32-bit aligned */
+    reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+    /* configure register high address */
+    phy_addr = 0x18;
+    phy_reg = 0x0;
+    phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    /* For some registers such as ARL and VLAN, since they include BUSY bit */
+    /* in lower address, we should write the higher 16-bit register then the */
+    /* lower one */
+
+    /* write register in higher address */
+    reg_word_addr++;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff);
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    /* write register in lower address */
+    reg_word_addr--;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (a_uint16_t) (reg_val & 0xffff);
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+sw_error_t
+garuda_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+               a_uint32_t reg, a_uint16_t * value)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value);
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+garuda_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+               a_uint32_t reg, a_uint16_t value)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value);
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+garuda_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+               a_uint32_t value_len)
+{
+    sw_error_t rv;
+    a_uint32_t flags;
+
+    MDIO_LOCKER_LOCK;
+    if (HSL_MDIO == reg_mode)
+    {
+        aos_irq_save(flags);
+        rv = _garuda_mdio_reg_get(dev_id, reg_addr, value, value_len);
+        aos_irq_restore(flags);
+    }
+    else
+    {
+        rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len);
+    }
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+garuda_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+               a_uint32_t value_len)
+{
+    sw_error_t rv;
+    a_uint32_t flags;
+
+    MDIO_LOCKER_LOCK;
+    if (HSL_MDIO == reg_mode)
+    {
+        aos_irq_save(flags);
+        rv = _garuda_mdio_reg_set(dev_id, reg_addr, value, value_len);
+        aos_irq_restore(flags);
+    }
+    else
+    {
+        rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len);
+    }
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+garuda_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                     a_uint32_t bit_offset, a_uint32_t field_len,
+                     a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val = 0;
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(garuda_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len);
+    return SW_OK;
+}
+
+sw_error_t
+garuda_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                     a_uint32_t bit_offset, a_uint32_t field_len,
+                     const a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val;
+    a_uint32_t field_val = *((a_uint32_t *) value);
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(garuda_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len);
+
+    SW_RTN_ON_ERROR(garuda_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    return SW_OK;
+}
+
+sw_error_t
+garuda_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode)
+{
+    hsl_api_t *p_api;
+
+    MDIO_LOCKER_INIT;
+    reg_mode = mode;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+    p_api->phy_get = garuda_phy_get;
+    p_api->phy_set = garuda_phy_set;
+    p_api->reg_get = garuda_reg_get;
+    p_api->reg_set = garuda_reg_set;
+    p_api->reg_field_get = garuda_reg_field_get;
+    p_api->reg_field_set = garuda_reg_field_set;
+    p_api->dev_access_set= garuda_access_mode_set;
+
+    return SW_OK;
+}
+
+sw_error_t
+garuda_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode)
+{
+    reg_mode = mode;
+    return SW_OK;
+
+}
diff --git a/qca-ssdk/src/hsl/garuda/garuda_stp.c b/qca-ssdk/src/hsl/garuda/garuda_stp.c
new file mode 100755
index 0000000..b05435c
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_stp.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_stp GARUDA_STP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_stp.h"
+#include "garuda_reg.h"
+
+#define GARUDA_PORT_DISABLED      0
+#define GARUDA_STP_BLOCKING       1
+#define GARUDA_STP_LISTENING      2
+#define GARUDA_STP_LEARNING       3
+#define GARUDA_STP_FARWARDING     4
+
+static sw_error_t
+_garuda_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                           fal_port_t port_id, fal_stp_state_t state)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SINGLE_STP_ID != st_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    switch (state)
+    {
+        case FAL_STP_BLOKING:
+            val = GARUDA_STP_BLOCKING;
+            break;
+        case FAL_STP_LISTENING:
+            val = GARUDA_STP_LISTENING;
+            break;
+        case FAL_STP_LEARNING:
+            val = GARUDA_STP_LEARNING;
+            break;
+        case FAL_STP_FARWARDING:
+            val = GARUDA_STP_FARWARDING;
+            break;
+        case FAL_STP_DISABLED:
+            val =  GARUDA_PORT_DISABLED;
+            break;
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, PORT_STATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_garuda_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                           fal_port_t port_id, fal_stp_state_t * state)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SINGLE_STP_ID != st_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, PORT_STATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    switch (val)
+    {
+        case GARUDA_STP_BLOCKING:
+            *state = FAL_STP_BLOKING;
+            break;
+        case GARUDA_STP_LISTENING:
+            *state = FAL_STP_LISTENING;
+            break;
+        case GARUDA_STP_LEARNING:
+            *state = FAL_STP_LEARNING;
+            break;
+        case GARUDA_STP_FARWARDING:
+            *state = FAL_STP_FARWARDING;
+            break;
+        case GARUDA_PORT_DISABLED:
+            *state = FAL_STP_DISABLED;
+            break;
+        default:
+            return SW_FAIL;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set port stp state on a particular spanning tree and port.
+ *   @details   Comments:
+    GARUDA only support single spanning tree so st_id should be
+    FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[in] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                          fal_port_t port_id, fal_stp_state_t state)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_stp_port_state_set(dev_id, st_id, port_id, state);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port stp state on a particular spanning tree and port.
+ *   @details  Comments:
+    GARUDA only support single spanning tree so st_id should be
+    FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[out] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                          fal_port_t port_id, fal_stp_state_t * state)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_stp_port_state_get(dev_id, st_id, port_id, state);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+garuda_stp_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->stp_port_state_set = garuda_stp_port_state_set;
+        p_api->stp_port_state_get = garuda_stp_port_state_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/garuda/garuda_vlan.c b/qca-ssdk/src/hsl/garuda/garuda_vlan.c
new file mode 100755
index 0000000..5f001d5
--- /dev/null
+++ b/qca-ssdk/src/hsl/garuda/garuda_vlan.c
@@ -0,0 +1,498 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup garuda_vlan GARUDA_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_vlan.h"
+#include "garuda_reg.h"
+
+#define MAX_VLAN_ID         4095
+
+#define VLAN_FLUSH          1
+#define VLAN_LOAD_ENTRY     2
+#define VLAN_PURGE_ENTRY    3
+#define VLAN_REMOVE_PORT    4
+#define VLAN_NEXT_ENTRY     5
+#define VLAN_FIND_ENTRY     6
+
+static void
+garuda_vlan_hw_to_sw(const a_uint32_t reg[], fal_vlan_t * vlan_entry)
+{
+    a_uint32_t data;
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]);
+    if (1 == data)
+    {
+        vlan_entry->vid_pri_en = A_TRUE;
+
+        SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]);
+        vlan_entry->vid_pri = data & 0xff;
+    }
+    else
+    {
+        vlan_entry->vid_pri_en = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VLAN_ID, data, reg[0]);
+    vlan_entry->vid = data & 0xffff;
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VID_MEM, data, reg[1]);
+    vlan_entry->mem_ports = data;
+
+    return;
+}
+
+static sw_error_t
+garuda_vlan_sw_to_hw(const fal_vlan_t * vlan_entry, a_uint32_t reg[])
+{
+    if (A_TRUE == vlan_entry->vid_pri_en)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]);
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri, reg[0]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]);
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_entry->vid, reg[0]);
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, reg[1]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VID_MEM, vlan_entry->mem_ports, reg[1]);
+
+    if (0 != vlan_entry->u_ports)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+garuda_vlan_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val;
+    sw_error_t rv;
+
+    while (vt_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
+                          (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_BUSY;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_FUNC, op, val);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_BUSY, 1, val);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    vt_busy = 1;
+    i = 0x1000;
+    while (vt_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
+                          (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_FAIL;
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_FULL_VIO,
+                      (a_uint8_t *) (&vt_full), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (vt_full)
+    {
+        val = 0x10;
+        HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        if (VLAN_LOAD_ENTRY == op)
+        {
+            return SW_FULL;
+        }
+        else if (VLAN_PURGE_ENTRY == op)
+        {
+            return SW_NOT_FOUND;
+        }
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_VALID,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (!val)
+    {
+        if (VLAN_FIND_ENTRY == op)
+            return SW_NOT_FOUND;
+
+        if (VLAN_NEXT_ENTRY == op)
+            return SW_NO_MORE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_entry->vid == 0) || (vlan_entry->vid > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    if (A_FALSE == hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU))
+        return SW_BAD_PARAM;
+
+    rv = garuda_vlan_sw_to_hw(vlan_entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = garuda_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_garuda_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    /* set default value for VLAN_TABLE_FUNC0, all 0 except vid */
+    entry = 0;
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, entry);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    /* set default value for VLAN_TABLE_FUNC1, all 0 */
+    entry = 0;
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, entry);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = garuda_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_garuda_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (vlan_id > MAX_VLAN_ID)
+        return SW_OUT_OF_RANGE;
+
+    aos_mem_zero(p_vlan, sizeof (fal_vlan_t));
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = garuda_vlan_commit(dev_id, VLAN_NEXT_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    garuda_vlan_hw_to_sw(reg, p_vlan);
+
+    if (0 == p_vlan->vid)
+        return SW_NO_MORE;
+    else
+        return SW_OK;
+}
+
+static sw_error_t
+_garuda_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    aos_mem_zero(p_vlan, sizeof (fal_vlan_t));
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = garuda_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    garuda_vlan_hw_to_sw(reg, p_vlan);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_garuda_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                           fal_pbmp_t member, fal_pbmp_t u_member)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU))
+        return SW_BAD_PARAM;
+
+    if (u_member != 0)
+        return SW_BAD_PARAM;
+
+    /* get vlan entry first */
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = garuda_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    /* set vlan member for VLAN_TABLE_FUNC1 */
+    HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VID_MEM,
+                      (a_uint8_t *) (&member), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = garuda_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    /* when update port member through LOAD opration, hardware will
+        return VT_FULL_VIO, we should ignore it */
+    if (SW_FULL == rv)
+        rv = SW_OK;
+
+    return rv;
+}
+
+
+static sw_error_t
+_garuda_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    reg = (a_int32_t) vlan_id;
+    HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VLAN_ID,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = garuda_vlan_commit(dev_id, VLAN_PURGE_ENTRY);
+    return rv;
+}
+
+/**
+ * @brief Append a vlan entry on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_entry vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_vlan_entry_append(dev_id, vlan_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Creat a vlan entry through vlan id on a paticular device.
+ *   @details   Comments:
+ *    After this operation the member ports of the created vlan entry are null.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_vlan_create(dev_id, vlan_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next a vlan entry through vlan id on a paticular device.
+ *   @details   Comments:
+ *    If the value of vid is zero this operation will get the first entry.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_vlan_next(dev_id, vlan_id, p_vlan);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a vlan entry through vlan id on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_vlan_find(dev_id, vlan_id, p_vlan);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Update a vlan entry member port through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] member member ports
+ * @param[in] u_member tagged or untagged infomation for member ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                          fal_pbmp_t member, fal_pbmp_t u_member)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_vlan_member_update(dev_id, vlan_id, member, u_member);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a vlan entry through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _garuda_vlan_delete(dev_id, vlan_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+garuda_vlan_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->vlan_entry_append = garuda_vlan_entry_append;
+    p_api->vlan_creat = garuda_vlan_create;
+    p_api->vlan_member_update = garuda_vlan_member_update;
+    p_api->vlan_delete = garuda_vlan_delete;
+    p_api->vlan_next = garuda_vlan_next;
+    p_api->vlan_find = garuda_vlan_find;
+
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/horus/Makefile b/qca-ssdk/src/hsl/horus/Makefile
new file mode 100755
index 0000000..bdbd6c0
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/Makefile
@@ -0,0 +1,80 @@
+LOC_DIR=src/hsl/horus
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=horus_reg_access.c horus_init.c
+
+ifeq (TRUE, $(IN_FDB))
+  SRC_LIST += horus_fdb.c
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+  SRC_LIST += horus_igmp.c
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+  SRC_LIST += horus_leaky.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+  SRC_LIST += horus_led.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+  SRC_LIST += horus_mib.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+  SRC_LIST += horus_mirror.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+  SRC_LIST += horus_misc.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+  SRC_LIST += horus_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+  SRC_LIST += horus_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+  SRC_LIST += horus_qos.c
+endif
+
+ifeq (TRUE, $(IN_RATE))
+  SRC_LIST += horus_rate.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+  SRC_LIST += horus_stp.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+  SRC_LIST += horus_vlan.c
+endif
+
+ifeq (TRUE, $(IN_REDUCED_ACL))
+  SRC_LIST += horus_reduced_acl.c
+endif
+
+ifeq (linux, $(OS))
+	ifeq (KSLIB, $(MODULE_TYPE))
+    ifneq (TRUE, $(KERNEL_MODE))
+      SRC_LIST=horus_reg_access.c horus_init.c
+	  endif
+	endif
+endif
+
+ifeq (, $(findstring HORUS, $(SUPPORT_CHIP)))
+  SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/qca-ssdk/src/hsl/horus/horus_fdb.c b/qca-ssdk/src/hsl/horus/horus_fdb.c
new file mode 100755
index 0000000..6ca18e0
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/horus_fdb.c
@@ -0,0 +1,999 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_fdb HORUS_FDB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_fdb.h"
+#include "horus_reg.h"
+
+#define ARL_FLUSH_ALL             1
+#define ARL_LOAD_ENTRY            2
+#define ARL_PURGE_ENTRY           3
+#define ARL_FLUSH_ALL_UNLOCK      4
+#define ARL_FLUSH_PORT_UNICAST    5
+#define ARL_NEXT_ENTRY            6
+#define ARL_FIND_ENTRY            7
+
+#define ARL_FIRST_ENTRY           1001
+#define ARL_FLUSH_PORT_NO_STATIC  1002
+#define ARL_FLUSH_PORT_AND_STATIC 1003
+
+static a_bool_t
+horus_fdb_is_zeroaddr(fal_mac_addr_t addr)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 6; i++)
+    {
+        if (addr.uc[i])
+        {
+            return A_FALSE;
+        }
+    }
+
+    return A_TRUE;
+}
+
+static void
+horus_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1)
+{
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE2, addr.uc[2], *reg1);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE3, addr.uc[3], *reg1);
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0);
+
+    return;
+}
+
+static sw_error_t
+horus_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry,
+                   a_uint32_t reg[])
+{
+    a_uint32_t port;
+
+    if (A_FALSE == entry->portmap_en)
+    {
+        if (A_TRUE !=
+                hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+
+        port = 0x1UL << entry->port.id;
+    }
+    else
+    {
+        if (A_FALSE ==
+                hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+
+        port = entry->port.map;
+    }
+
+    if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]);
+    }
+    else if (FAL_MAC_FRWRD != entry->dacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_MAC_DROP == entry->sacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, SA_DROP_EN, 1, reg[2]);
+    }
+    else if (FAL_MAC_FRWRD != entry->sacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->leaky_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]);
+    }
+
+    if (A_TRUE == entry->static_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]);
+    }
+
+    if (A_TRUE == entry->mirror_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, MIRROR_EN, 1, reg[2]);
+    }
+
+    if (A_TRUE == entry->clone_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CLONE_EN, 1, reg[2]);
+    }
+
+    if (A_TRUE == entry->cross_pt_state)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CROSS_PT, 1, reg[2]);
+    }
+
+    if (A_TRUE == entry->da_pri_en)
+    {
+        hsl_dev_t *p_dev;
+
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI_EN, 1, reg[2]);
+
+        SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+
+        if (entry->da_queue > (p_dev->nr_queue - 1))
+            return SW_BAD_PARAM;
+
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI, entry->da_queue, reg[2]);
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, DES_PORT, port, reg[2]);
+    horus_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+
+    return SW_OK;
+}
+
+static void
+horus_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+    a_uint32_t i, data;
+
+    aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+    entry->dacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_CPY_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    entry->sacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, SA_DROP_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->sacmd = FAL_MAC_DROP;
+    }
+
+    entry->leaky_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->leaky_en = A_TRUE;
+    }
+
+    entry->static_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]);
+    if (0xf == data)
+    {
+        entry->static_en = A_TRUE;
+    }
+
+    entry->mirror_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, MIRROR_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+
+    entry->clone_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, CLONE_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->clone_en = A_TRUE;
+    }
+
+    entry->da_pri_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI_EN, data, reg[2]);
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI, data, reg[2]);
+        entry->da_pri_en = A_TRUE;
+        entry->da_queue = data & 0x3;
+    }
+
+    entry->cross_pt_state = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, CROSS_PT, data, reg[2]);
+    if (1 == data)
+    {
+        entry->cross_pt_state = A_TRUE;
+    }
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, DES_PORT, data, reg[2]);
+
+    entry->portmap_en = A_TRUE;
+    entry->port.map = data;
+
+    for (i = 0; i < 4; i++)
+    {
+        entry->addr.uc[i] = (reg[1] >> ((3 - i) << 3)) & 0xff;
+    }
+
+    for (i = 4; i < 6; i++)
+    {
+        entry->addr.uc[i] = (reg[0] >> ((7 - i) << 3)) & 0xff;
+    }
+
+    return;
+}
+
+static sw_error_t
+horus_fdb_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    sw_error_t rv;
+    a_uint32_t busy = 1;
+    a_uint32_t full_vio;
+    a_uint32_t i = 1000;
+    a_uint32_t entry;
+    a_uint32_t hwop = op;
+
+    while (busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+                          (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_BUSY;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_BUSY, 1, entry);
+
+    if (ARL_FLUSH_PORT_AND_STATIC == hwop)
+    {
+        hwop = ARL_FLUSH_PORT_UNICAST;
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 1, entry);
+    }
+
+    if (ARL_FLUSH_PORT_NO_STATIC == hwop)
+    {
+        hwop = ARL_FLUSH_PORT_UNICAST;
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 0, entry);
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_FUNC, hwop, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    busy = 1;
+    i = 1000;
+    while (busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+                          (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_FAIL;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_FULL_VIO,
+                      (a_uint8_t *) (&full_vio), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (full_vio)
+    {
+        /* must clear AT_FULL_VOI bit */
+        entry = 0x1000;
+        HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        if (ARL_LOAD_ENTRY == hwop)
+        {
+            return SW_FULL;
+        }
+        else if ((ARL_PURGE_ENTRY == hwop)
+                 || (ARL_FLUSH_PORT_UNICAST == hwop))
+        {
+            return SW_NOT_FOUND;
+        }
+        else
+        {
+            return SW_FAIL;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+horus_atu_get(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op)
+{
+    sw_error_t rv;
+    a_uint32_t reg[3] = { 0 };
+    a_uint32_t status = 0;
+    a_uint32_t hwop = op;
+
+    if ((ARL_NEXT_ENTRY == op)
+            || (ARL_FIND_ENTRY == op))
+    {
+        horus_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* set status not zero */
+    if (ARL_NEXT_ENTRY == op)
+    {
+        reg[2] = 0xf0000;
+    }
+
+    if (ARL_FIRST_ENTRY == op)
+    {
+        hwop = ARL_NEXT_ENTRY;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = horus_fdb_commit(dev_id, hwop);
+    SW_RTN_ON_ERROR(rv);
+
+    /* get hardware enrety */
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]);
+
+    horus_atu_hw_to_sw(reg, entry);
+
+    /* If hardware return back with address and status all zero,
+       that means no other next valid entry in fdb table */
+    if ((A_TRUE == horus_fdb_is_zeroaddr(entry->addr))
+            && (0 == status))
+    {
+        if (ARL_NEXT_ENTRY == op)
+        {
+            return SW_NO_MORE;
+        }
+        else if ((ARL_FIND_ENTRY == op)
+                 || (ARL_FIRST_ENTRY == op))
+        {
+            return SW_NOT_FOUND;
+        }
+        else
+        {
+            return SW_FAIL;
+        }
+    }
+    else
+    {
+        return SW_OK;
+    }
+}
+
+static sw_error_t
+_horus_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[3] = { 0, 0, 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = horus_atu_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (&reg[1]),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&reg[0]),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = horus_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+
+    return rv;
+}
+
+static sw_error_t
+_horus_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        rv = horus_fdb_commit(dev_id, ARL_FLUSH_ALL);
+    }
+    else
+    {
+        rv = horus_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_horus_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_PORT_NUM, port_id, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        rv = horus_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC);
+    }
+    else
+    {
+        rv = horus_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC);
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_horus_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg0 = 0, reg1 = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    horus_fdb_fill_addr(entry->addr, &reg0, &reg1);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (&reg1),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&reg0),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = horus_fdb_commit(dev_id, ARL_PURGE_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_horus_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = horus_atu_get(dev_id, entry, ARL_NEXT_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_horus_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = horus_atu_get(dev_id, entry, ARL_FIRST_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_horus_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = horus_atu_get(dev_id, entry, ARL_FIND_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_horus_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEARN_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEARN_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((65535 * 7 < *time) || (7 > *time))
+    {
+        return SW_BAD_PARAM;
+    }
+    data = *time / 7;
+    *time = data * 7;
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *time = data * 7;
+    return SW_OK;
+}
+
+/**
+ * @brief Add a Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_fdb_add(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete all Fdb entries
+ *   @details   Comments:
+ *         If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ *       entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_fdb_del_all(dev_id, flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete Fdb entries on a particular port
+ *   @details   Comments:
+ *       If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ *       entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_fdb_del_by_port(dev_id, port_id, flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a particular Fdb entry through mac address
+ *   @details   Comments:
+ *       Only addr field in entry is meaning. For IVL learning vid or fid field
+ *       also is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_fdb_del_by_mac(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get next Fdb entry from particular device
+ *   @details   Comments:
+ *    For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_fdb_next(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from particular device
+ * @param[in] dev_id device id
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_fdb_first(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a particular Fdb entry from device through mac address.
+ *    @details  Comments:
+    For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_fdb_find(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning status on a particular port.
+ *    @details  Comments:
+ *       This operation will enable or disable dynamic address learning
+ *       feature on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_fdb_port_learn_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_fdb_port_learn_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address aging status on particular device.
+ *   @details  Comments:
+ *       This operation will enable or disable dynamic address aging
+ *       feature on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_fdb_age_ctrl_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address aging status on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_fdb_age_ctrl_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address aging time on a particular device.
+ * @details   Comments:
+ *       This operation will set dynamic address aging time on a particular device.
+ *       The unit of time is second. Because different device has differnet
+ *       hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_fdb_age_time_set(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address aging time on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_fdb_age_time_get(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+horus_fdb_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->fdb_add = horus_fdb_add;
+        p_api->fdb_del_all = horus_fdb_del_all;
+        p_api->fdb_del_by_port = horus_fdb_del_by_port;
+        p_api->fdb_del_by_mac = horus_fdb_del_by_mac;
+        p_api->fdb_first = horus_fdb_first;
+        p_api->fdb_next = horus_fdb_next;
+        p_api->fdb_find = horus_fdb_find;
+        p_api->port_learn_set = horus_fdb_port_learn_set;
+        p_api->port_learn_get = horus_fdb_port_learn_get;
+        p_api->age_ctrl_set = horus_fdb_age_ctrl_set;
+        p_api->age_ctrl_get = horus_fdb_age_ctrl_get;
+        p_api->age_time_set = horus_fdb_age_time_set;
+        p_api->age_time_get = horus_fdb_age_time_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/horus/horus_igmp.c b/qca-ssdk/src/hsl/horus/horus_igmp.c
new file mode 100755
index 0000000..4f42ed2
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/horus_igmp.c
@@ -0,0 +1,979 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_igmp HORUS_IGMP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_igmp.h"
+#include "horus_reg.h"
+
+static sw_error_t
+_horus_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, JOIN_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, JOIN_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_mports_validity_check(dev_id, pts))
+    {
+        return SW_BAD_PARAM;
+    }
+    val = pts;
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *pts = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 0xf;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0xe;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_STATIC,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_STATIC,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0xf == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_LEAKY,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_LEAKY,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_V3_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_V3_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t entry;
+    hsl_dev_t *p_dev;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 1, entry);
+        SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+        if (queue >= p_dev->nr_queue)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, queue, entry);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 0, entry);
+        SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, 0, entry);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, QM_CTL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t entry, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI_EN, data, entry);
+    if (data)
+    {
+        *enable = A_TRUE;
+        SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI, data, entry);
+        *queue  = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *queue  = 0;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set igmp/mld packets snooping status on a particular port.
+ * @details    Comments:
+ *   After enabling igmp/mld snooping feature on a particular port all kinds
+ *   igmp/mld packets received on this port would be acknowledged by hardware.
+ *   Particular forwarding decision could be setted by fal_igmp_mld_cmd_set.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_igmps_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets snooping status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_igmps_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld packets forwarding command on a particular device.
+ * @details    Comments:
+ *    Particular device may only support parts of forwarding commands.
+ *    This operation will take effect only after enabling igmp/mld snooping
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_igmp_mld_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_igmp_mld_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld join packets hardware acknowledgement status on particular port.
+ * @details    Comments:
+ *    After enabling igmp/mld join feature on a particular port hardware will
+ *    dynamic learning or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_igmp_mld_join_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_igmp_mld_join_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @details    Comments:
+ *    After enabling igmp leave feature on a particular port hardware will dynamic
+ *    deleting or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_igmp_mld_leave_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_igmp_mld_leave_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld router ports on a particular device.
+ * @details     Comments:
+ *    After enabling igmp/mld join/leave feature on a particular port igmp/mld
+ *    join/leave packets received on this port will be forwarded to router ports.
+ * @param[in] dev_id device id
+ * @param[in] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_igmp_mld_rp_set(dev_id, pts);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld router ports on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_igmp_mld_rp_get(dev_id, pts);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   entry creat hardware will dynamic creat and delete multicast entry,
+ *   otherwise hardware only can change destination ports of existing muticast entry.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_igmp_mld_entry_creat_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_igmp_mld_entry_creat_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the static status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   static status hardware will not age out multicast entry which leardned by hardware,
+ *   otherwise hardware will age out multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_igmp_mld_entry_static_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the static status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_igmp_mld_entry_static_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the leaky status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   leaky status hardware will set leaky flag of multicast entry which leardned by hardware,
+ *   otherwise hardware will not set leaky flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_igmp_mld_entry_leaky_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the leaky status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_igmp_mld_entry_leaky_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @details    Comments:
+ *    After enabling igmp join/leave feature on a particular port hardware will dynamic
+ *    creating or changing multicast entry after receiving igmpv3/mldv2 packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_igmp_mld_entry_v3_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_igmp_mld_entry_v3_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the queue status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   leaky status hardware will set queue flag of multicast entry which leardned by hardware,
+ *   otherwise hardware will not set queue flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_igmp_mld_entry_queue_set(dev_id, enable, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the queue status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_igmp_mld_entry_queue_get(dev_id, enable, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+horus_igmp_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->port_igmps_status_set = horus_port_igmps_status_set;
+        p_api->port_igmps_status_get = horus_port_igmps_status_get;
+        p_api->igmp_mld_cmd_set = horus_igmp_mld_cmd_set;
+        p_api->igmp_mld_cmd_get = horus_igmp_mld_cmd_get;
+        p_api->port_igmp_join_set = horus_port_igmp_mld_join_set;
+        p_api->port_igmp_join_get = horus_port_igmp_mld_join_get;
+        p_api->port_igmp_leave_set = horus_port_igmp_mld_leave_set;
+        p_api->port_igmp_leave_get = horus_port_igmp_mld_leave_get;
+        p_api->igmp_rp_set = horus_igmp_mld_rp_set;
+        p_api->igmp_rp_get = horus_igmp_mld_rp_get;
+        p_api->igmp_entry_creat_set = horus_igmp_mld_entry_creat_set;
+        p_api->igmp_entry_creat_get = horus_igmp_mld_entry_creat_get;
+        p_api->igmp_entry_static_set = horus_igmp_mld_entry_static_set;
+        p_api->igmp_entry_static_get = horus_igmp_mld_entry_static_get;
+        p_api->igmp_entry_leaky_set = horus_igmp_mld_entry_leaky_set;
+        p_api->igmp_entry_leaky_get = horus_igmp_mld_entry_leaky_get;
+        p_api->igmp_entry_v3_set = horus_igmp_mld_entry_v3_set;
+        p_api->igmp_entry_v3_get = horus_igmp_mld_entry_v3_get;
+        p_api->igmp_entry_queue_set = horus_igmp_mld_entry_queue_set;
+        p_api->igmp_entry_queue_get = horus_igmp_mld_entry_queue_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/horus/horus_init.c b/qca-ssdk/src/hsl/horus/horus_init.c
new file mode 100755
index 0000000..d22fe86
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/horus_init.c
@@ -0,0 +1,432 @@
+/*
+ * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_init HORUS_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_mib.h"
+#include "horus_port_ctrl.h"
+#include "horus_portvlan.h"
+#include "horus_vlan.h"
+#include "horus_fdb.h"
+#include "horus_qos.h"
+#include "horus_mirror.h"
+#include "horus_stp.h"
+#include "horus_rate.h"
+#include "horus_misc.h"
+#include "horus_leaky.h"
+#include "horus_igmp.h"
+#include "horus_led.h"
+#include "horus_reg_access.h"
+#include "horus_reg.h"
+#include "f2_phy.h"
+
+static ssdk_init_cfg * horus_cfg[SW_MAX_NR_DEV] = { 0 };
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+static sw_error_t
+horus_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
+{
+    hsl_port_prop_t p_type;
+    hsl_dev_t *pdev = NULL;
+    fal_port_t port_id;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return SW_NOT_INITIALIZED;
+
+    for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+    {
+        hsl_port_prop_portmap_set(dev_id, port_id);
+
+        for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
+        {
+            if (HSL_NO_CPU == mode)
+            {
+                SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                continue;
+            }
+
+            switch (p_type)
+            {
+                case HSL_PP_PHY:
+                    if (HSL_CPU_1 != mode)
+                    {
+                        if ((port_id != pdev->cpu_port_nr)
+                                && (port_id != (pdev->nr_ports -1)))
+                        {
+                            SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                        }
+                    }
+                    else
+                    {
+                        if (port_id != pdev->cpu_port_nr)
+                        {
+                            SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                        }
+                    }
+                    break;
+
+                case HSL_PP_INCL_CPU:
+                    /* include cpu port and wan port in some cases */
+                    if (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1))))
+                        SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+
+                    break;
+
+                case HSL_PP_EXCL_CPU:
+                    /* exclude cpu port and wan port in some cases */
+                    if ((port_id != pdev->cpu_port_nr)
+                            && (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1)))))
+                        SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                    break;
+
+                default:
+                    break;
+            }
+        }
+
+        if (HSL_NO_CPU == mode)
+        {
+            SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+                            (dev_id, port_id, port_id + 1));
+        }
+        else
+        {
+            if (port_id != pdev->cpu_port_nr)
+            {
+                SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+                                (dev_id, port_id, port_id - 1));
+            }
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+horus_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    hsl_dev_t *pdev = NULL;
+    a_uint32_t port_id;
+    a_uint32_t data;
+    sw_error_t rv;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (NULL == pdev)
+    {
+        return SW_NOT_INITIALIZED;
+    }
+
+    for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+    {
+        if (port_id == pdev->cpu_port_nr)
+        {
+            continue;
+        }
+
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data);
+
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+horus_bist_test(a_uint32_t dev_id)
+{
+    a_uint32_t entry, data, i;
+    sw_error_t rv;
+
+    data = 1;
+    i = 0x1000;
+    while (data && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_INIT_ERROR;
+    }
+
+    entry = 0;
+    SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = 1;
+    i = 0x1000;
+    while (data && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_INIT_ERROR;
+    }
+
+    SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry);
+    if (data)
+    {
+        SW_GET_FIELD_BY_REG(BIST_CTRL, ONE_ERR, data, entry);
+        if (!data)
+        {
+            return SW_INIT_ERROR;
+        }
+
+        SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_ADDR, data, entry);
+
+        entry = 0;
+        SW_SET_REG_BY_FIELD(BIST_RCV, RCV_EN, 1, entry);
+        SW_SET_REG_BY_FIELD(BIST_RCV, RCV_ADDR, data, entry);
+        HSL_REG_ENTRY_SET(rv, dev_id, BIST_RCV, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        return SW_OK;
+    }
+
+    entry = 0;
+    SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = 1;
+    i = 0x1000;
+    while (data && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_INIT_ERROR;
+    }
+
+    SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry);
+    if (data)
+    {
+        return SW_INIT_ERROR;
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+horus_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode)
+{
+    hsl_dev_t *pdev = NULL;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return SW_NOT_INITIALIZED;
+
+    pdev->nr_ports = 6;
+    pdev->nr_phy = 5;
+    pdev->cpu_port_nr = 0;
+    pdev->nr_vlans = 16;
+    pdev->hw_vlan_query = A_TRUE;
+    pdev->nr_queue = 4;
+    pdev->cpu_mode = cpu_mode;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_reset(a_uint32_t dev_id)
+{
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    val = 0x1;
+    HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = horus_hw_init(dev_id, horus_cfg[dev_id]);
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+    return SW_OK;
+}
+
+
+sw_error_t
+horus_cleanup(a_uint32_t dev_id)
+{
+
+    if (horus_cfg[dev_id])
+    {
+        aos_mem_free(horus_cfg[dev_id]);
+        horus_cfg[dev_id] = NULL;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief reset hsl layer.
+ * @details Comments:
+ *   This operation will reset hsl layer
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+sw_error_t
+horus_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_reset(dev_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Init hsl layer.
+ * @details Comments:
+ *   This operation will init hsl layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+horus_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (NULL == horus_cfg[dev_id])
+    {
+        horus_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg));
+    }
+
+    if (NULL == horus_cfg[dev_id])
+    {
+        return SW_OUT_OF_MEM;
+    }
+
+    aos_mem_copy(horus_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+
+    SW_RTN_ON_ERROR(horus_reg_access_init(dev_id, cfg->reg_mode));
+
+    SW_RTN_ON_ERROR(horus_dev_init(dev_id, cfg->cpu_mode));
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+    {
+        a_uint32_t i, entry;
+        sw_error_t rv;
+
+        SW_RTN_ON_ERROR(horus_bist_test(dev_id));
+
+        entry = 0x1;
+        HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        i = 0x10;
+        do
+        {
+            HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+                              (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            aos_mdelay(10);
+        }
+        while (entry && --i);
+
+        if (0 == i)
+        {
+            return SW_INIT_ERROR;
+        }
+
+        SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id));
+        SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
+        SW_RTN_ON_ERROR(horus_portproperty_init(dev_id, cfg->cpu_mode));
+
+        HORUS_MIB_INIT(rv, dev_id);
+        HORUS_PORT_CTRL_INIT(rv, dev_id);
+        HORUS_PORTVLAN_INIT(rv, dev_id);
+        HORUS_VLAN_INIT(rv, dev_id);
+        HORUS_FDB_INIT(rv, dev_id);
+        HORUS_QOS_INIT(rv, dev_id);
+        HORUS_STP_INIT(rv, dev_id);
+        HORUS_MIRR_INIT(rv, dev_id);
+        HORUS_RATE_INIT(rv, dev_id);
+        HORUS_MISC_INIT(rv, dev_id);
+        HORUS_LEAKY_INIT(rv, dev_id);
+        HORUS_IGMP_INIT(rv, dev_id);
+        HORUS_LED_INIT(rv, dev_id);
+
+        {
+            hsl_api_t *p_api;
+
+            SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+            p_api->dev_reset = horus_reset;
+            p_api->dev_clean = horus_cleanup;
+        }
+
+        SW_RTN_ON_ERROR(horus_hw_init(dev_id, cfg));
+    }
+#endif
+
+    return SW_OK;
+}
+
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/horus/horus_leaky.c b/qca-ssdk/src/hsl/horus/horus_leaky.c
new file mode 100755
index 0000000..d3973be
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/horus_leaky.c
@@ -0,0 +1,525 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_leaky HORUS_LEAKY
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_leaky.h"
+#include "horus_reg.h"
+
+static sw_error_t
+_horus_uc_leaky_mode_set(a_uint32_t dev_id,
+                         fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+    {
+        data = 0;
+    }
+    else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_uc_leaky_mode_get(a_uint32_t dev_id,
+                         fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+    }
+    else
+    {
+        *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_mc_leaky_mode_set(a_uint32_t dev_id,
+                         fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+    {
+        data = 0;
+    }
+    else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_mc_leaky_mode_get(a_uint32_t dev_id,
+                         fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+    }
+    else
+    {
+        *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, ARP_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, ARP_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+* @brief Set unicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+horus_uc_leaky_mode_set(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_uc_leaky_mode_set(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_uc_leaky_mode_get(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_uc_leaky_mode_get(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Set multicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+horus_mc_leaky_mode_set(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_mc_leaky_mode_set(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mc_leaky_mode_get(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_mc_leaky_mode_get(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_arp_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_arp_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_uc_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_uc_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_mc_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_mc_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+horus_leaky_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->uc_leaky_mode_set = horus_uc_leaky_mode_set;
+        p_api->uc_leaky_mode_get = horus_uc_leaky_mode_get;
+        p_api->mc_leaky_mode_set = horus_mc_leaky_mode_set;
+        p_api->mc_leaky_mode_get = horus_mc_leaky_mode_get;
+        p_api->port_arp_leaky_set = horus_port_arp_leaky_set;
+        p_api->port_arp_leaky_get = horus_port_arp_leaky_get;
+        p_api->port_uc_leaky_set = horus_port_uc_leaky_set;
+        p_api->port_uc_leaky_get = horus_port_uc_leaky_get;
+        p_api->port_mc_leaky_set = horus_port_mc_leaky_set;
+        p_api->port_mc_leaky_get = horus_port_mc_leaky_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/horus/horus_led.c b/qca-ssdk/src/hsl/horus/horus_led.c
new file mode 100755
index 0000000..db2765d
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/horus_led.c
@@ -0,0 +1,427 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_led HORUS_LED
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_led.h"
+#include "horus_reg.h"
+
+#define MAX_LED_PATTERN_ID   1
+#define LED_PATTERN_ADDR     0xB0
+
+static sw_error_t
+_horus_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                            led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    a_uint32_t data = 0, reg, mode;
+    a_uint32_t addr;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (group >= LED_GROUP_BUTT)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (id > MAX_LED_PATTERN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((LED_MAC_PORT_GROUP == group) && (0 != id))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (LED_MAC_PORT_GROUP == group)
+    {
+        addr = LED_PATTERN_ADDR + 8;
+    }
+    else
+    {
+        addr = LED_PATTERN_ADDR + (id << 2);
+    }
+
+    if (LED_ALWAYS_OFF == pattern->mode)
+    {
+        mode = 0;
+    }
+    else if (LED_ALWAYS_BLINK == pattern->mode)
+    {
+        mode = 1;
+    }
+    else if (LED_ALWAYS_ON == pattern->mode)
+    {
+        mode = 2;
+    }
+    else if (LED_PATTERN_MAP_EN == pattern->mode)
+    {
+        mode = 3;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data);
+
+    if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << POWER_ON_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_1000M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_100M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_10M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << COLLISION_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINKUP_OVERRIDE_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data);
+    }
+
+    if (LED_BLINK_2HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data);
+    }
+    else if (LED_BLINK_4HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data);
+    }
+    else if (LED_BLINK_8HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data);
+    }
+    else if (LED_BLINK_TXRX == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_WAN_PORT_GROUP == group)
+    {
+        reg &= 0xffff;
+        reg |= (data << 16);
+    }
+    else
+    {
+        reg &= 0xffff0000;
+        reg |= data;
+    }
+
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_WAN_PORT_GROUP == group)
+    {
+        return SW_OK;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_LAN_PORT_GROUP == group)
+    {
+        if (id)
+        {
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data);
+        }
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(LED_PATTERN, M5_MODE, mode, data);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                            led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    a_uint32_t data = 0, reg, tmp;
+    a_uint32_t addr;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (group >= LED_GROUP_BUTT)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (id > MAX_LED_PATTERN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((LED_MAC_PORT_GROUP == group) && (0 != id))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t));
+
+    if (LED_MAC_PORT_GROUP == group)
+    {
+        addr = LED_PATTERN_ADDR + 8;
+    }
+    else
+    {
+        addr = LED_PATTERN_ADDR + (id << 2);
+    }
+
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_WAN_PORT_GROUP == group)
+    {
+        data = (reg >> 16) & 0xffff;
+    }
+    else
+    {
+        data = reg & 0xffff;
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data);
+    if (0 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_OFF;
+    }
+    else if (1 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_BLINK;
+    }
+    else if (2 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_ON;
+    }
+    else
+    {
+        pattern->mode = LED_PATTERN_MAP_EN;
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << POWER_ON_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_1000M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_100M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_10M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << COLLISION_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << RX_TRAFFIC_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << TX_TRAFFIC_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINKUP_OVERRIDE_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data);
+    if (0 == tmp)
+    {
+        pattern->freq = LED_BLINK_2HZ;
+    }
+    else if (1 == tmp)
+    {
+        pattern->freq = LED_BLINK_4HZ;
+    }
+    else if (2 == tmp)
+    {
+        pattern->freq = LED_BLINK_8HZ;
+    }
+    else
+    {
+        pattern->freq = LED_BLINK_TXRX;
+    }
+
+    return SW_OK;
+}
+
+/**
+* @brief Set led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group  pattern group, lan or wan
+* @param[in] id pattern id
+* @param[in] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+horus_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                           led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_led_ctrl_pattern_set(dev_id, group, id, pattern);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Get led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group  pattern group, lan or wan
+* @param[in] id pattern id
+* @param[out] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+horus_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                           led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_led_ctrl_pattern_get(dev_id, group, id, pattern);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+horus_led_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->led_ctrl_pattern_set = horus_led_ctrl_pattern_set;
+        p_api->led_ctrl_pattern_get = horus_led_ctrl_pattern_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/horus/horus_mib.c b/qca-ssdk/src/hsl/horus/horus_mib.c
new file mode 100755
index 0000000..4c80001
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/horus_mib.c
@@ -0,0 +1,377 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_mib HORUS_MIB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_mib.h"
+#include "horus_reg.h"
+
+static sw_error_t
+_horus_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                    fal_mib_info_t * mib_info)
+{
+    a_uint32_t val;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFcsErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxAllignErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxRunt = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFragment = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxTooLong = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxOverFlow = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Filtered = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxUnderRun = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxOverSize = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxCollision = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxAbortCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMultiCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxSingalCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxExcDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxLateCol = val;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Get mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                   fal_mib_info_t * mib_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_get_mib_info(dev_id, port_id, mib_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_mib_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_mib_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+horus_mib_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->get_mib_info   = horus_get_mib_info;
+    p_api->mib_status_set = horus_mib_status_set;
+    p_api->mib_status_get = horus_mib_status_get;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/horus/horus_mirror.c b/qca-ssdk/src/hsl/horus/horus_mirror.c
new file mode 100755
index 0000000..bc92980
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/horus_mirror.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_mirror HORUS_MIRROR
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_mirror.h"
+#include "horus_reg.h"
+
+static sw_error_t
+_horus_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = port_id;
+    HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *port_id = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+ *   @details  Comments:
+ *   The analysis port works for both ingress and egress mirror.
+ * @brief Set mirror analyzer port on particular a device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_mirr_analysis_port_set(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mirror analysis port on particular a device.
+ * @param[in] dev_id device id
+ * @param[out] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_mirr_analysis_port_get(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_mirr_port_in_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_mirr_port_in_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_mirr_port_eg_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_mirr_port_eg_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+horus_mirr_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->mirr_analysis_port_set = horus_mirr_analysis_port_set;
+        p_api->mirr_analysis_port_get = horus_mirr_analysis_port_get;
+        p_api->mirr_port_in_set = horus_mirr_port_in_set;
+        p_api->mirr_port_in_get = horus_mirr_port_in_get;
+        p_api->mirr_port_eg_set = horus_mirr_port_eg_set;
+        p_api->mirr_port_eg_get = horus_mirr_port_eg_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/horus/horus_misc.c b/qca-ssdk/src/hsl/horus/horus_misc.c
new file mode 100755
index 0000000..1c13ff7
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/horus_misc.c
@@ -0,0 +1,1396 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_misc HORUS_MISC
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_misc.h"
+#include "horus_reg.h"
+
+#define HORUS_MAX_FRMAE_SIZE      9216
+
+static sw_error_t
+_horus_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ARP_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_arp_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ARP_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (HORUS_MAX_FRMAE_SIZE < size)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = size;
+    HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *size = data;
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 0, data);
+    }
+    else if (FAL_MAC_DROP == cmd)
+    {
+        SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
+        SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 1, data);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
+        SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 0, data);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_fwd_cmd_t * action)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+    a_uint32_t port_lock_en, port_drop_en;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_CTL, PORT_LOCK_EN, port_lock_en, data);
+    SW_GET_FIELD_BY_REG(PORT_CTL, LOCK_DROP_EN, port_drop_en, data);
+
+    if (1 == port_lock_en)
+    {
+        if (1 == port_drop_en)
+        {
+            *action = FAL_MAC_DROP;
+        }
+        else
+        {
+            *action = FAL_MAC_RDT_TO_CPU;
+        }
+    }
+    else
+    {
+        *action = FAL_MAC_FRWRD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t)0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t)0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t)0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_FRWRD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, DHCP_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, DHCP_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ARP_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ARP_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, EAPOL_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, EAPOL_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EAPOL_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t *enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EAPOL_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, RIP_CPY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_ripv1_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, RIP_CPY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_arp_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_arp_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_arp_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max frame size which device can received on a particular device.
+ * @details    Comments:
+ * The granularity of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[in] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_frame_max_size_set(dev_id, size);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max frame size which device can received on a particular device.
+ * @details   Comments:
+ *    The unit of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[out] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_frame_max_size_get(dev_id, size);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set forwarding command for packets which source address is unknown on a particular port.
+ * @details Comments:
+ *    Particular device may only support parts of forwarding commands.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_unk_sa_cmd_set(dev_id, port_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get forwarding command for packets which source address is unknown on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_fwd_cmd_t * action)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_unk_sa_cmd_get(dev_id, port_id, action);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown unicast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown unicast packets filter on one port then unknown
+ *   unicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_unk_uc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flooding status of unknown unicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_unk_uc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown multicast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown multicast packets filter on one port then unknown
+ *   multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_unk_mc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/** @brief Get flooding status of unknown multicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_unk_mc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of broadcast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown multicast packets filter on one port then unknown
+ *   multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_bc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/** @brief Get flooding status of broadcast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_bc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_cpu_port_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_cpu_port_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set pppoe packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling pppoe packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_pppoe_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get pppoe packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_pppoe_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set pppoe packets hardware acknowledgement status on particular device.
+ * @details     comments:
+ *   Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_pppoe_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get pppoe packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_pppoe_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dhcp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_dhcp_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dhcp packets hardware acknowledgement status on particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_dhcp_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling arp packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_arp_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_arp_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set eapol packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling eapol packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_eapol_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get eapol packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_eapol_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_eapol_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_eapol_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_ripv1_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_ripv1_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_ripv1_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+horus_misc_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->arp_status_set = horus_arp_status_set;
+        p_api->arp_status_get = horus_arp_status_get;
+        p_api->frame_max_size_set = horus_frame_max_size_set;
+        p_api->frame_max_size_get = horus_frame_max_size_get;
+        p_api->port_unk_sa_cmd_set = horus_port_unk_sa_cmd_set;
+        p_api->port_unk_sa_cmd_get = horus_port_unk_sa_cmd_get;
+        p_api->port_unk_uc_filter_set = horus_port_unk_uc_filter_set;
+        p_api->port_unk_uc_filter_get = horus_port_unk_uc_filter_get;
+        p_api->port_unk_mc_filter_set = horus_port_unk_mc_filter_set;
+        p_api->port_unk_mc_filter_get = horus_port_unk_mc_filter_get;
+        p_api->port_bc_filter_set = horus_port_bc_filter_set;
+        p_api->port_bc_filter_get = horus_port_bc_filter_get;
+        p_api->cpu_port_status_set = horus_cpu_port_status_set;
+        p_api->cpu_port_status_get = horus_cpu_port_status_get;
+        p_api->pppoe_cmd_set = horus_pppoe_cmd_set;
+        p_api->pppoe_cmd_get = horus_pppoe_cmd_get;
+        p_api->pppoe_status_set = horus_pppoe_status_set;
+        p_api->pppoe_status_get = horus_pppoe_status_get;
+        p_api->port_dhcp_set = horus_port_dhcp_set;
+        p_api->port_dhcp_get = horus_port_dhcp_get;
+        p_api->arp_cmd_set = horus_arp_cmd_set;
+        p_api->arp_cmd_get = horus_arp_cmd_get;
+        p_api->eapol_cmd_set = horus_eapol_cmd_set;
+        p_api->eapol_cmd_get = horus_eapol_cmd_get;
+        p_api->eapol_status_set = horus_eapol_status_set;
+        p_api->eapol_status_get = horus_eapol_status_get;
+        p_api->ripv1_status_set = horus_ripv1_status_set;
+        p_api->ripv1_status_get = horus_ripv1_status_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/horus/horus_port_ctrl.c b/qca-ssdk/src/hsl/horus/horus_port_ctrl.c
new file mode 100755
index 0000000..75fcee8
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/horus_port_ctrl.c
@@ -0,0 +1,1061 @@
+/*
+ * Copyright (c) 2012, 2015,The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_port_ctrl HORUS_PORT_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_port_ctrl.h"
+#include "horus_reg.h"
+#include "hsl_phy.h"
+
+static sw_error_t
+_horus_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_port_duplex_t duplex)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    a_uint32_t reg_save = 0;
+    a_uint32_t reg_val = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_duplex_set)
+         return SW_NOT_SUPPORTED;
+
+    if (FAL_DUPLEX_BUTT <= duplex)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    //save reg value
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+    reg_save = reg_val;
+
+    SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+    //set mac be config by sw   and turn off RX TX MAC_EN
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+    rv = phy_drv->phy_duplex_set(dev_id, phy_id, duplex);
+
+    //retore reg value
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_save), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_horus_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_port_duplex_t * pduplex)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_duplex_get)
+         return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_duplex_get(dev_id, phy_id, pduplex);
+    return rv;
+}
+
+static sw_error_t
+_horus_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_speed_t speed)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_speed_set)
+         return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_SPEED_100 < speed)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = phy_drv->phy_speed_set(dev_id, phy_id, speed);
+
+    return rv;
+}
+
+static sw_error_t
+_horus_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_speed_t * pspeed)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_speed_get)
+         return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_speed_get(dev_id, phy_id, pspeed);
+
+    return rv;
+}
+
+static sw_error_t
+_horus_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * status)
+{
+    a_uint32_t phy_id;
+    sw_error_t rv;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_autoneg_status_get)
+         return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *status = phy_drv->phy_autoneg_status_get(dev_id, phy_id);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_autoneg_enable_set)
+	  return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_autoneg_enable_set(dev_id, phy_id);
+    return rv;
+}
+
+static sw_error_t
+_horus_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_restart_autoneg)
+         return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_restart_autoneg(dev_id, phy_id);
+    return rv;
+}
+
+static sw_error_t
+_horus_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t autoadv)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_autoneg_adv_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_autoneg_adv_set(dev_id, phy_id, autoadv);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * autoadv)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_autoneg_adv_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *autoadv = 0;
+    rv = phy_drv->phy_autoneg_adv_get(dev_id, phy_id, autoadv);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, HEAD_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_horus_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, HEAD_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_horus_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val, force, reg;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+    if (force)
+    {
+        /* flow control isn't in force mode so can't set */
+        return SW_DISABLE;
+    }
+
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t tx, rx, reg;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg);
+    SW_GET_FIELD_BY_REG(PORT_STATUS, TX_FLOW_EN, tx, reg);
+
+    if (1 == rx)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t force, reg;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+    if (force != (a_uint32_t) enable)
+    {
+        return SW_OK;
+    }
+
+    if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 0, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, 0, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t force, reg;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+    if (0 == force)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_powersave_set)
+	 return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_powersave_set(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_horus_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_powersave_get)
+	 return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_powersave_get(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_horus_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_hibernation_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_hibernation_set(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_horus_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_hibernation_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_hibernation_get(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_horus_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+                fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
+    if (NULL == phy_drv->phy_cdt)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_cdt(dev_id, phy_id, mdi_pair, cable_status, cable_len);
+
+    return rv;
+}
+
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_duplex_t duplex)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_duplex_set(dev_id, port_id, duplex);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_duplex_t * pduplex)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_duplex_get(dev_id, port_id, pduplex);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_port_speed_t speed)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_speed_set(dev_id, port_id, speed);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_port_speed_t * pspeed)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_speed_get(dev_id, port_id, pspeed);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_autoneg_status_get(dev_id, port_id, status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_autoneg_enable(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_autoneg_restart(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ *   @details  Comments:
+ *   auto negotiation advtisement ability is defined by macro such as
+ *   FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t autoadv)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_autoneg_adv_set(dev_id, port_id, autoadv);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * autoadv)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_autoneg_adv_get(dev_id, port_id, autoadv);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_hdr_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_hdr_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_flowctrl_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_flowctrl_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_flowctrl_forcemode_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_flowctrl_forcemode_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_powersave_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_powersave_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_hibernate_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_hibernate_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Run cable diagnostic test on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mdi_pair mdi pair id
+ * @param[out] cable_status cable status
+ * @param[out] cable_len cable len
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+               fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+horus_port_ctrl_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->port_duplex_get = horus_port_duplex_get;
+        p_api->port_duplex_set = horus_port_duplex_set;
+        p_api->port_speed_get = horus_port_speed_get;
+        p_api->port_speed_set = horus_port_speed_set;
+        p_api->port_autoneg_status_get = horus_port_autoneg_status_get;
+        p_api->port_autoneg_enable = horus_port_autoneg_enable;
+        p_api->port_autoneg_restart = horus_port_autoneg_restart;
+        p_api->port_autoneg_adv_get = horus_port_autoneg_adv_get;
+        p_api->port_autoneg_adv_set = horus_port_autoneg_adv_set;
+        p_api->port_hdr_status_set = horus_port_hdr_status_set;
+        p_api->port_hdr_status_get = horus_port_hdr_status_get;
+        p_api->port_flowctrl_set = horus_port_flowctrl_set;
+        p_api->port_flowctrl_get = horus_port_flowctrl_get;
+        p_api->port_flowctrl_forcemode_set = horus_port_flowctrl_forcemode_set;
+        p_api->port_flowctrl_forcemode_get = horus_port_flowctrl_forcemode_get;
+        p_api->port_powersave_set = horus_port_powersave_set;
+        p_api->port_powersave_get = horus_port_powersave_get;
+        p_api->port_hibernate_set = horus_port_hibernate_set;
+        p_api->port_hibernate_get = horus_port_hibernate_get;
+        p_api->port_cdt           = horus_port_cdt;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/horus/horus_portvlan.c b/qca-ssdk/src/hsl/horus/horus_portvlan.c
new file mode 100755
index 0000000..1bf9f98
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/horus_portvlan.c
@@ -0,0 +1,1184 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_port_vlan HORUS_PORT_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_portvlan.h"
+#include "horus_reg.h"
+
+#define MAX_VLAN_ID           4095
+
+static sw_error_t
+_horus_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_1Q_MODE_BUTT <= port_1qmode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+                      (a_uint8_t *) (&regval[port_1qmode]),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+static sw_error_t
+_horus_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK,
+                                  FAL_1Q_CHECK, FAL_1Q_SECURE
+                                };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(pport_1qmode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    *pport_1qmode = retval[regval & 0x3];
+
+    return SW_OK;
+
+}
+
+static sw_error_t
+_horus_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3};
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_EG_MODE_BUTT <= port_egvlanmode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+                      (a_uint8_t *) (&regval[port_egvlanmode]),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+static sw_error_t
+_horus_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_1q_egmode_t retval[4] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED,
+                                     FAL_EG_TAGGED, FAL_EG_HYBRID
+                                   };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(pport_egvlanmode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    *pport_egvlanmode = retval[regval & 0x3];
+
+    return SW_OK;
+
+}
+
+static sw_error_t
+_horus_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    regval |= (0x1UL << mem_port_id);
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+static sw_error_t
+_horus_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    regval &= (~(0x1UL << mem_port_id));
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+static sw_error_t
+_horus_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE ==
+            hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&mem_port_map),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_horus_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    *mem_port_map = 0;
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) mem_port_map,
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((0 == vid) || (vid > MAX_VLAN_ID))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = vid;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1Q, port_id,
+                      DEF_VID, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+
+static sw_error_t
+_horus_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1Q, port_id,
+                      DEF_VID, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+
+    *vid = val & 0xfff;
+    return rv;
+}
+
+
+static sw_error_t
+_horus_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1Q, port_id,
+                      FORCE_DEF_VID, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1Q, port_id,
+                      FORCE_DEF_VID, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1Q, port_id,
+                      FORCE_PVLAN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1Q, port_id,
+                      FORCE_PVLAN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    val = tpid;
+    HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+                      TAG_VALUE, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+                      TAG_VALUE, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *tpid = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pt_invlan_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t regval[FAL_INVLAN_MODE_BUTT] = { 0, 1, 2};
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_INVLAN_MODE_BUTT <= mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, IN_VLAN_MODE,
+                      (a_uint8_t *) (&regval[mode]),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_horus_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pt_invlan_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_invlan_mode_t retval[FAL_INVLAN_MODE_BUTT] = { FAL_INVLAN_ADMIT_ALL,
+            FAL_INVLAN_ADMIT_TAGGED, FAL_INVLAN_ADMIT_UNTAGGED
+                                                        };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(mode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, IN_VLAN_MODE,
+                      (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (regval >= 3)
+    {
+        return SW_FAIL;
+    }
+    *mode = retval[regval & 0x3];
+
+    return rv;
+}
+
+static sw_error_t
+_horus_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PRI_PROPAGATION, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PRI_PROPAGATION, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t stag = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_QINQ_MODE_BUTT <= mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QINQ_STAG_MODE == mode)
+    {
+        stag = 1;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0,
+                      STAG_MODE, (a_uint8_t *) (&stag),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_horus_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t stag = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0,
+                      STAG_MODE, (a_uint8_t *) (&stag),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (stag)
+    {
+        *mode = FAL_QINQ_STAG_MODE;
+    }
+    else
+    {
+        *mode = FAL_QINQ_CTAG_MODE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role)
+{
+    sw_error_t rv;
+    a_uint32_t core = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QINQ_PORT_ROLE_BUTT <= role)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QINQ_CORE_PORT == role)
+    {
+        core = 1;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      COREP_EN, (a_uint8_t *) (&core),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_horus_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role)
+{
+    sw_error_t rv;
+    a_uint32_t core = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      COREP_EN, (a_uint8_t *) (&core),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (core)
+    {
+        *role = FAL_QINQ_CORE_PORT;
+    }
+    else
+    {
+        *role = FAL_QINQ_EDGE_PORT;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_1qmode_set(dev_id, port_id, port_1qmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_1qmode_get(dev_id, port_id, pport_1qmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_portvlan_member_add(dev_id, port_id, mem_port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_portvlan_member_del(dev_id, port_id, mem_port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Update member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_portvlan_member_update(dev_id, port_id, mem_port_map);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_portvlan_member_get(dev_id, port_id, mem_port_map);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default vlan id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid default vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_default_vid_set(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default vlan id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid default vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_default_vid_get(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_force_default_vid_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_force_default_vid_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_force_portvlan_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_force_portvlan_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_nestvlan_tpid_set(dev_id, tpid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_nestvlan_tpid_get(dev_id, tpid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_invlan_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_invlan_mode_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_invlan_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_invlan_mode_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_pri_propagation_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_pri_propagation_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qinq_mode_set(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qinq_mode_get(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_qinq_role_set(dev_id, port_id, role);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_port_qinq_role_get(dev_id, port_id, role);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+horus_portvlan_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->port_1qmode_get = horus_port_1qmode_get;
+    p_api->port_1qmode_set = horus_port_1qmode_set;
+    p_api->port_egvlanmode_get = horus_port_egvlanmode_get;
+    p_api->port_egvlanmode_set = horus_port_egvlanmode_set;
+    p_api->portvlan_member_add = horus_portvlan_member_add;
+    p_api->portvlan_member_del = horus_portvlan_member_del;
+    p_api->portvlan_member_update = horus_portvlan_member_update;
+    p_api->portvlan_member_get = horus_portvlan_member_get;
+    p_api->port_default_vid_set = horus_port_default_vid_set;
+    p_api->port_default_vid_get = horus_port_default_vid_get;
+    p_api->port_force_default_vid_set = horus_port_force_default_vid_set;
+    p_api->port_force_default_vid_get = horus_port_force_default_vid_get;
+    p_api->port_force_portvlan_set = horus_port_force_portvlan_set;
+    p_api->port_force_portvlan_get = horus_port_force_portvlan_get;
+    p_api->nestvlan_tpid_set = horus_nestvlan_tpid_set;
+    p_api->nestvlan_tpid_get = horus_nestvlan_tpid_get;
+    p_api->port_invlan_mode_set = horus_port_invlan_mode_set;
+    p_api->port_invlan_mode_get = horus_port_invlan_mode_get;
+    p_api->port_pri_propagation_set = horus_port_pri_propagation_set;
+    p_api->port_pri_propagation_get = horus_port_pri_propagation_get;
+    p_api->qinq_mode_set = horus_qinq_mode_set;
+    p_api->qinq_mode_get = horus_qinq_mode_get;
+    p_api->port_qinq_role_set = horus_port_qinq_role_set;
+    p_api->port_qinq_role_get = horus_port_qinq_role_get;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/horus/horus_qos.c b/qca-ssdk/src/hsl/horus/horus_qos.c
new file mode 100755
index 0000000..b2c6398
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/horus_qos.c
@@ -0,0 +1,1260 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_qos HORUS_QOS
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_qos.h"
+#include "horus_reg.h"
+
+#define HORUS_QOS_QUEUE_TX_BUFFER_MAX 60
+#define HORUS_QOS_PORT_TX_BUFFER_MAX  252
+#define HORUS_QOS_PORT_RX_BUFFER_MAX  60
+
+//#define HORUS_MIN_QOS_MODE_PRI 0
+#define HORUS_MAX_QOS_MODE_PRI 3
+
+static sw_error_t
+_horus_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (HORUS_QOS_QUEUE_TX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = *number / 4;
+    *number = val << 2;
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_horus_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    *number = val << 2;
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (HORUS_QOS_PORT_TX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = *number / 4;
+    *number = val << 2;
+    HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *number = val << 2;
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (HORUS_QOS_PORT_RX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = *number / 4;
+    *number = val << 2;
+    HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_IN_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_IN_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *number = val << 2;
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+                           fal_queue_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+    hsl_dev_t *p_dev = NULL;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_DOT1P_MAX < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+    if (p_dev->nr_queue <= queue)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = queue;
+    HSL_REG_FIELD_GEN_SET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2,
+                          (a_uint16_t) (up << 1), (a_uint8_t *) (&val),
+                          sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+                           fal_queue_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_DOT1P_MAX < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GEN_GET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2,
+                          (a_uint16_t) (up << 1), (a_uint8_t *) (&val),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *queue = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+                             fal_queue_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+    a_uint32_t offsetaddr;
+    a_uint16_t fieldoffset;
+    hsl_dev_t *p_dev = NULL;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_DSCP_MAX < dscp)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+    if (p_dev->nr_queue <= queue)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    offsetaddr = (dscp >> 4) << 2;
+    fieldoffset = (dscp & 0xf) << 1;
+
+    val = queue;
+    HSL_REG_FIELD_GEN_SET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr),
+                          2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+                             fal_queue_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+    a_uint32_t offsetaddr;
+    a_uint16_t fieldoffset;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_DSCP_MAX < dscp)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    offsetaddr = (dscp / 16) << 2;
+    fieldoffset = (dscp & 0xf) << 1;
+
+    HSL_REG_FIELD_GEN_GET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr),
+                          2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *queue = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_qos_mode_t mode, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_PORT_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_horus_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_qos_mode_t mode, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_PORT_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_qos_mode_t mode, a_uint32_t pri)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (HORUS_MAX_QOS_MODE_PRI < pri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_PORT_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, PORT_PRI_SEL, pri, val);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_qos_mode_t mode, a_uint32_t * pri)
+{
+    sw_error_t rv;
+    a_uint32_t entry, f_val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_PORT_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, PORT_PRI_SEL, f_val, entry);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    *pri = f_val;
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t up)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_DOT1P_MAX < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = up;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1Q, port_id, ING_PRI,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * up)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1Q, port_id, ING_PRI,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *up = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                             fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SCH_SP_MODE == mode)
+    {
+        val   = 0;
+    }
+    else if (FAL_SCH_WRR_MODE == mode)
+    {
+        val   = 3;
+    }
+    else if (FAL_SCH_MIX_MODE == mode)
+    {
+        val   = 1;
+    }
+    else if (FAL_SCH_MIX_PLUS_MODE == mode)
+    {
+        val   = 2;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, WRR_CTRL, port_id, SCH_MODE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                             fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+    a_uint32_t sch, i;
+    a_uint32_t w[4] = {1, 2, 4, 8};
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, WRR_CTRL, port_id, SCH_MODE,
+                      (a_uint8_t *) (&sch), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == sch)
+    {
+        *mode = FAL_SCH_SP_MODE;
+        for (i = 0; i < 4; i++)
+        {
+            w[i] = 0;
+        }
+    }
+    else if (1 == sch)
+    {
+        *mode = FAL_SCH_MIX_MODE;
+        w[3] = 0;
+    }
+    else if (2 == sch)
+    {
+        *mode = FAL_SCH_MIX_PLUS_MODE;
+        w[3] = 0;
+        w[2] = 0;
+    }
+    else
+    {
+        *mode = FAL_SCH_WRR_MODE;
+    }
+
+    for (i = 0; i < 4; i++)
+    {
+        weight[i] = w[i];
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting queue on one particular port.
+ *   @details  Comments:
+ *    If enable queue tx buffer on one port that means each queue of this port
+ *    will have fixed number buffers when transmitting packets. Otherwise they
+ *    share the whole buffers with other queues in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_queue_tx_buf_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting queue on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_queue_tx_buf_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting port on one particular port.
+ *   @details  Comments:
+    If enable tx buffer on one port that means this port will have fixed
+    number buffers when transmitting packets. Otherwise they will
+    share the whole buffers with other ports in device.
+ *    function will return actual buffer numbers in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_port_tx_buf_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_port_tx_buf_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting queue on one particular port.
+ *   @details   Comments:
+    The step of buffer number in Garuda is 4, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for queue is 4 to 60.
+ *    share the whole buffers with other ports in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting queue on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting port on one particular port.
+ *   @details   Comments:
+    The step of buffer number in Garuda is four, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for transmitting port is 4 to 124.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_port_tx_buf_nr_set(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_port_tx_buf_nr_get(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of receiving port on one particular port.
+ *   @details   Comments:
+    The step of buffer number in Horus is four, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for receiving port is 4 to 60.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_port_rx_buf_nr_set(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of receiving port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_port_rx_buf_nr_get(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set user priority to mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dot1p 802.1p
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+                          fal_queue_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_cosmap_up_queue_set(dev_id, up, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get user priority to mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dot1p 802.1p
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+                          fal_queue_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_cosmap_up_queue_get(dev_id, up, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+                            fal_queue_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_cosmap_dscp_queue_set(dev_id, dscp, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+                            fal_queue_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_cosmap_dscp_queue_get(dev_id, dscp, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qos_mode_t mode, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_port_mode_set(dev_id, port_id, mode, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qos_mode_t mode, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_port_mode_get(dev_id, port_id, mode, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set priority of one particular qos mode on one particular port.
+ *   @details   Comments:
+    If the priority of a mode is more small then the priority is more high.
+    Differnet mode should have differnet priority.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_qos_mode_t mode, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get priority of one particular qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_qos_mode_t mode, a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] up 802.1p
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t up)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_port_default_up_set(dev_id, port_id, up);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] up 802.1p
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * up)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_port_default_up_get(dev_id, port_id, up);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set traffic scheduling mode on particular one port.
+ *   @details   Comments:
+ *   When scheduling mode is sp the weight is meaningless usually it's zero
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[in] weight[] weight value for each queue when in wrr mode,
+              Horus only support fixed weight 1:2:4:8 for four queues.
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                            fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_port_sch_mode_set(dev_id, port_id, mode, weight);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get traffic scheduling mode on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] fal_sch_mode_t traffic scheduling mode
+ * @param[out] weight weight value for wrr mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                            fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_qos_port_sch_mode_get(dev_id, port_id, mode, weight);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+horus_qos_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->qos_queue_tx_buf_status_set = horus_qos_queue_tx_buf_status_set;
+        p_api->qos_queue_tx_buf_status_get = horus_qos_queue_tx_buf_status_get;
+        p_api->qos_port_tx_buf_status_set = horus_qos_port_tx_buf_status_set;
+        p_api->qos_port_tx_buf_status_get = horus_qos_port_tx_buf_status_get;
+        p_api->qos_queue_tx_buf_nr_set = horus_qos_queue_tx_buf_nr_set;
+        p_api->qos_queue_tx_buf_nr_get = horus_qos_queue_tx_buf_nr_get;
+        p_api->qos_port_tx_buf_nr_set = horus_qos_port_tx_buf_nr_set;
+        p_api->qos_port_tx_buf_nr_get = horus_qos_port_tx_buf_nr_get;
+        p_api->qos_port_rx_buf_nr_set = horus_qos_port_rx_buf_nr_set;
+        p_api->qos_port_rx_buf_nr_get = horus_qos_port_rx_buf_nr_get;
+        p_api->cosmap_up_queue_set = horus_cosmap_up_queue_set;
+        p_api->cosmap_up_queue_get = horus_cosmap_up_queue_get;
+        p_api->cosmap_dscp_queue_set = horus_cosmap_dscp_queue_set;
+        p_api->cosmap_dscp_queue_get = horus_cosmap_dscp_queue_get;
+        p_api->qos_port_mode_set = horus_qos_port_mode_set;
+        p_api->qos_port_mode_get = horus_qos_port_mode_get;
+        p_api->qos_port_mode_pri_set = horus_qos_port_mode_pri_set;
+        p_api->qos_port_mode_pri_get = horus_qos_port_mode_pri_get;
+        p_api->qos_port_default_up_set = horus_qos_port_default_up_set;
+        p_api->qos_port_default_up_get = horus_qos_port_default_up_get;
+        p_api->qos_port_sch_mode_set = horus_qos_port_sch_mode_set;
+        p_api->qos_port_sch_mode_get = horus_qos_port_sch_mode_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/horus/horus_rate.c b/qca-ssdk/src/hsl/horus/horus_rate.c
new file mode 100755
index 0000000..acb1fb0
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/horus_rate.c
@@ -0,0 +1,578 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_rate HORUS_RATE
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_rate.h"
+#include "horus_reg.h"
+
+#define HORUS_STORM_MIN_RATE_PPS 1000
+#define HORUS_STORM_MAX_RATE_PPS (1024 * 1000)
+
+static sw_error_t
+horus_stormrate_sw_to_hw(a_uint32_t swrate, a_uint32_t * hwrate)
+{
+    a_uint32_t shrnr = 0;
+    a_uint32_t tmp = swrate / 1000;
+
+    if ((HORUS_STORM_MIN_RATE_PPS > swrate)
+            || (HORUS_STORM_MAX_RATE_PPS < swrate))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    while ((tmp != 0) && (shrnr < 12))
+    {
+        tmp = tmp >> 1;
+        shrnr++;
+    }
+
+    if (12 == shrnr)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    *hwrate = shrnr;
+    return SW_OK;
+}
+
+static sw_error_t
+horus_stormrate_hw_to_sw(a_uint32_t hwrate, a_uint32_t * swrate)
+{
+    if (0 == hwrate)
+    {
+        hwrate = 1;
+    }
+
+    if ((1 > hwrate) || (11 < hwrate))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    *swrate = (1 << (hwrate - 1)) * 1000;
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == enable)
+    {
+        *speed = 0;
+
+        val = 0x1fff;
+        HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        if ((0x1ffe << 5) < *speed)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        val = *speed >> 5;
+        *speed = val << 5;
+        HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_horus_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_RATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0x1fff == val)
+    {
+        *speed = 0;
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+        *speed = val << 5;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        if ((0x7ffe << 5) < *speed)
+        {
+            return SW_BAD_PARAM;
+        }
+        val = *speed >> 5;
+        *speed = val << 5;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0x7fff;
+        *speed = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0x7fff == val)
+    {
+        *enable = A_FALSE;
+        *speed = 0;
+    }
+    else
+    {
+        *enable = A_TRUE;
+        *speed = val << 5;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_storm_type_t storm_type, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_UNICAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, UNI_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_MULTICAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, MUL_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_BROADCAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, BRO_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        data = 1;
+        HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_storm_type_t storm_type, a_bool_t * enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_UNICAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, UNI_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_MULTICAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, MUL_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_BROADCAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, BRO_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        data = 1;
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * rate_in_pps)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = horus_stormrate_sw_to_hw(*rate_in_pps, &data);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = horus_stormrate_hw_to_sw(data, rate_in_pps);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * rate_in_pps)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = horus_stormrate_hw_to_sw(data, rate_in_pps);
+    return rv;
+}
+
+/**
+ * @brief Set port egress rate limit status on one particular port.
+ *   @details   Comments:
+    The granularity of speed is bps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port egress rate limit input parameter speed is meaningless.
+    The step of speed is 32kbps.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_rate_port_egrl_set(dev_id, port_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port egress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_rate_port_egrl_get(dev_id, port_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port ingress rate limit status on one particular port.
+ *   @details   Comments:
+    The granularity of speed is bps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port ingress rate limit input parameter speed is meaningless.
+    The step of speed is 32kbps.
+ *    When disable port ingress rate limit input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_rate_port_inrl_set(dev_id, port_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port ingress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_rate_port_inrl_get(dev_id, port_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set particular type storm control status on one particular port.
+ *   @details   Comments:
+ *    When enable one particular packets type storm control this type packets
+ *    speed will be calculated in storm control.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_storm_type_t storm_type, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_storm_ctrl_frame_set(dev_id, port_id, storm_type, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get particular type storm control status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_storm_type_t storm_type, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_storm_ctrl_frame_get(dev_id, port_id, storm_type, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set storm control speed on one particular port.
+ *   @details   Comments:
+    Because of hardware granularity function will return actual speed in hardware.
+    The step of speed is kpps.
+    The speed range is from 1k to 1M
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed storm control speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * rate_in_pps)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_storm_ctrl_rate_set(dev_id, port_id, rate_in_pps);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get storm control speed on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed storm control speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * rate_in_pps)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_storm_ctrl_rate_get(dev_id, port_id, rate_in_pps);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+horus_rate_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->rate_port_egrl_set = horus_rate_port_egrl_set;
+        p_api->rate_port_egrl_get = horus_rate_port_egrl_get;
+        p_api->rate_port_inrl_set = horus_rate_port_inrl_set;
+        p_api->rate_port_inrl_get = horus_rate_port_inrl_get;
+        p_api->storm_ctrl_frame_set = horus_storm_ctrl_frame_set;
+        p_api->storm_ctrl_frame_get = horus_storm_ctrl_frame_get;
+        p_api->storm_ctrl_rate_set = horus_storm_ctrl_rate_set;
+        p_api->storm_ctrl_rate_get = horus_storm_ctrl_rate_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/horus/horus_reg_access.c b/qca-ssdk/src/hsl/horus/horus_reg_access.c
new file mode 100755
index 0000000..f8d4fae
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/horus_reg_access.c
@@ -0,0 +1,273 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "sd.h"
+#include "horus_reg_access.h"
+
+static hsl_access_mode reg_mode;
+
+#if defined(API_LOCK)
+static aos_lock_t mdio_lock;
+#define MDIO_LOCKER_INIT    aos_lock_init(&mdio_lock)
+#define MDIO_LOCKER_LOCK    aos_lock(&mdio_lock)
+#define MDIO_LOCKER_UNLOCK  aos_unlock(&mdio_lock)
+#else
+#define MDIO_LOCKER_INIT
+#define MDIO_LOCKER_LOCK
+#define MDIO_LOCKER_UNLOCK
+#endif
+
+static sw_error_t
+_horus_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                    a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_word_addr;
+    a_uint32_t phy_addr, reg_val;
+    a_uint16_t phy_val, tmp_val;
+    a_uint8_t phy_reg;
+    sw_error_t rv;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    /* change reg_addr to 16-bit word address, 32-bit aligned */
+    reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+    /* configure register high address */
+    phy_addr = 0x18;
+    phy_reg = 0x0;
+    phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    /* For some registers such as MIBs, since it is read/clear, we should */
+    /* read the lower 16-bit register then the higher one */
+
+    /* read register in lower address */
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+    SW_RTN_ON_ERROR(rv);
+    reg_val = tmp_val;
+
+    /* read register in higher address */
+    reg_word_addr++;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+    SW_RTN_ON_ERROR(rv);
+    reg_val |= (((a_uint32_t)tmp_val) << 16);
+
+    aos_mem_copy(value, &reg_val, sizeof (a_uint32_t));
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                    a_uint32_t value_len)
+{
+    a_uint32_t reg_word_addr;
+    a_uint32_t phy_addr, reg_val;
+    a_uint16_t phy_val;
+    a_uint8_t phy_reg;
+    sw_error_t rv;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    aos_mem_copy(&reg_val, value, sizeof (a_uint32_t));
+
+    /* change reg_addr to 16-bit word address, 32-bit aligned */
+    reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+    /* configure register high address */
+    phy_addr = 0x18;
+    phy_reg = 0x0;
+    phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    /* For some registers such as ARL and VLAN, since they include BUSY bit */
+    /* in lower address, we should write the higher 16-bit register then the */
+    /* lower one */
+
+    /* write register in higher address */
+    reg_word_addr++;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff);
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    /* write register in lower address */
+    reg_word_addr--;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (a_uint16_t) (reg_val & 0xffff);
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+sw_error_t
+horus_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+              a_uint32_t reg, a_uint16_t * value)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value);
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+horus_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+              a_uint32_t reg, a_uint16_t value)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value);
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+horus_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+              a_uint32_t value_len)
+{
+    sw_error_t rv;
+    a_uint32_t flags;
+
+    MDIO_LOCKER_LOCK;
+    if (HSL_MDIO == reg_mode)
+    {
+        aos_irq_save(flags);
+        rv = _horus_mdio_reg_get(dev_id, reg_addr, value, value_len);
+        aos_irq_restore(flags);
+    }
+    else
+    {
+        rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len);
+    }
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+horus_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+              a_uint32_t value_len)
+{
+    sw_error_t rv;
+    a_uint32_t flags;
+
+    MDIO_LOCKER_LOCK;
+    if (HSL_MDIO == reg_mode)
+    {
+        aos_irq_save(flags);
+        rv = _horus_mdio_reg_set(dev_id, reg_addr, value, value_len);
+        aos_irq_restore(flags);
+    }
+    else
+    {
+        rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len);
+    }
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+horus_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                    a_uint32_t bit_offset, a_uint32_t field_len,
+                    a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val = 0;
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(horus_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len);
+    return SW_OK;
+}
+
+sw_error_t
+horus_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                    a_uint32_t bit_offset, a_uint32_t field_len,
+                    const a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val;
+    a_uint32_t field_val = *((a_uint32_t *) value);
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(horus_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len);
+
+    SW_RTN_ON_ERROR(horus_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    return SW_OK;
+}
+
+sw_error_t
+horus_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode)
+{
+    hsl_api_t *p_api;
+
+    MDIO_LOCKER_INIT;
+    reg_mode = mode;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->phy_get = horus_phy_get;
+    p_api->phy_set = horus_phy_set;
+    p_api->reg_get = horus_reg_get;
+    p_api->reg_set = horus_reg_set;
+    p_api->reg_field_get = horus_reg_field_get;
+    p_api->reg_field_set = horus_reg_field_set;
+    p_api->dev_access_set= horus_access_mode_set;
+
+    return SW_OK;
+}
+
+sw_error_t
+horus_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode)
+{
+    reg_mode = mode;
+    return SW_OK;
+
+}
+
diff --git a/qca-ssdk/src/hsl/horus/horus_stp.c b/qca-ssdk/src/hsl/horus/horus_stp.c
new file mode 100755
index 0000000..0f4a973
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/horus_stp.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_stp HORUS_STP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_stp.h"
+#include "horus_reg.h"
+
+#define HORUS_PORT_DISABLED      0
+#define HORUS_STP_BLOCKING       1
+#define HORUS_STP_LISTENING      2
+#define HORUS_STP_LEARNING       3
+#define HORUS_STP_FARWARDING     4
+
+static sw_error_t
+_horus_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                          fal_port_t port_id, fal_stp_state_t state)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SINGLE_STP_ID != st_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    switch (state)
+    {
+        case FAL_STP_BLOKING:
+            val = HORUS_STP_BLOCKING;
+            break;
+        case FAL_STP_LISTENING:
+            val = HORUS_STP_LISTENING;
+            break;
+        case FAL_STP_LEARNING:
+            val = HORUS_STP_LEARNING;
+            break;
+        case FAL_STP_FARWARDING:
+            val = HORUS_STP_FARWARDING;
+            break;
+        case FAL_STP_DISABLED:
+            val =  HORUS_PORT_DISABLED;
+            break;
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, PORT_STATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_horus_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                          fal_port_t port_id, fal_stp_state_t * state)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SINGLE_STP_ID != st_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, PORT_STATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    switch (val)
+    {
+        case HORUS_STP_BLOCKING:
+            *state = FAL_STP_BLOKING;
+            break;
+        case HORUS_STP_LISTENING:
+            *state = FAL_STP_LISTENING;
+            break;
+        case HORUS_STP_LEARNING:
+            *state = FAL_STP_LEARNING;
+            break;
+        case HORUS_STP_FARWARDING:
+            *state = FAL_STP_FARWARDING;
+            break;
+        case HORUS_PORT_DISABLED:
+            *state = FAL_STP_DISABLED;
+            break;
+        default:
+            return SW_FAIL;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set port stp state on a particular spanning tree and port.
+ *   @details   Comments:
+    Garuda only support single spanning tree so st_id should be
+    FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[in] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                         fal_port_t port_id, fal_stp_state_t state)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_stp_port_state_set(dev_id, st_id, port_id, state);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port stp state on a particular spanning tree and port.
+ *   @details  Comments:
+    Garuda only support single spanning tree so st_id should be
+    FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[out] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                         fal_port_t port_id, fal_stp_state_t * state)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_stp_port_state_get(dev_id, st_id, port_id, state);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+horus_stp_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->stp_port_state_set = horus_stp_port_state_set;
+        p_api->stp_port_state_get = horus_stp_port_state_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/horus/horus_vlan.c b/qca-ssdk/src/hsl/horus/horus_vlan.c
new file mode 100755
index 0000000..754194f
--- /dev/null
+++ b/qca-ssdk/src/hsl/horus/horus_vlan.c
@@ -0,0 +1,518 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup horus_vlan HORUS_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_vlan.h"
+#include "horus_reg.h"
+
+#define MAX_VLAN_ID         4095
+
+#define VLAN_FLUSH          1
+#define VLAN_LOAD_ENTRY     2
+#define VLAN_PURGE_ENTRY    3
+#define VLAN_REMOVE_PORT    4
+#define VLAN_NEXT_ENTRY     5
+#define VLAN_FIND_ENTRY     6
+
+static void
+horus_vlan_hw_to_sw(const a_uint32_t reg[], fal_vlan_t * vlan_entry)
+{
+    a_uint32_t data;
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]);
+    if (1 == data)
+    {
+        vlan_entry->vid_pri_en = A_TRUE;
+
+        SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]);
+        vlan_entry->vid_pri = data & 0xff;
+    }
+    else
+    {
+        vlan_entry->vid_pri_en = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VLAN_ID, data, reg[0]);
+    vlan_entry->vid = data & 0xffff;
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VID_MEM, data, reg[1]);
+    vlan_entry->mem_ports = data;
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, LEARN_DIS, data, reg[1]);
+    if (1 == data)
+    {
+        vlan_entry->learn_dis = A_TRUE;
+    }
+    else
+    {
+        vlan_entry->learn_dis = A_FALSE;
+    }
+
+    return;
+}
+
+static sw_error_t
+horus_vlan_sw_to_hw(const fal_vlan_t * vlan_entry, a_uint32_t reg[])
+{
+    if (A_TRUE == vlan_entry->vid_pri_en)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]);
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri, reg[0]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]);
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_entry->vid, reg[0]);
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, reg[1]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VID_MEM, vlan_entry->mem_ports, reg[1]);
+
+    if (A_TRUE == vlan_entry->learn_dis)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, LEARN_DIS, 1, reg[1]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, LEARN_DIS, 0, reg[1]);
+    }
+
+    if (0 != vlan_entry->u_ports)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+horus_vlan_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val;
+    sw_error_t rv;
+
+    while (vt_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
+                          (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_BUSY;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_FUNC, op, val);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_BUSY, 1, val);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    vt_busy = 1;
+    i = 0x1000;
+    while (vt_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
+                          (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_FAIL;
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_FULL_VIO,
+                      (a_uint8_t *) (&vt_full), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (vt_full)
+    {
+        val = 0x10;
+        HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        if (VLAN_LOAD_ENTRY == op)
+        {
+            return SW_FULL;
+        }
+        else if (VLAN_PURGE_ENTRY == op)
+        {
+            return SW_NOT_FOUND;
+        }
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_VALID,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (!val)
+    {
+        if (VLAN_FIND_ENTRY == op)
+            return SW_NOT_FOUND;
+
+        if (VLAN_NEXT_ENTRY == op)
+            return SW_NO_MORE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_entry->vid == 0) || (vlan_entry->vid > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    if (A_FALSE == hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU))
+        return SW_BAD_PARAM;
+
+    rv = horus_vlan_sw_to_hw(vlan_entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = horus_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_horus_vlan_create(a_uint32_t dev_id, a_uint16_t vlan_id)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    /* set default value for VLAN_TABLE_FUNC0, all 0 except vid */
+    entry = 0;
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, entry);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    /* set default value for VLAN_TABLE_FUNC1, all 0 */
+    entry = 0;
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, entry);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = horus_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_horus_vlan_next(a_uint32_t dev_id, a_uint16_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (vlan_id > MAX_VLAN_ID)
+        return SW_OUT_OF_RANGE;
+
+    aos_mem_zero(p_vlan, sizeof (fal_vlan_t));
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = horus_vlan_commit(dev_id, VLAN_NEXT_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    horus_vlan_hw_to_sw(reg, p_vlan);
+
+    if (0 == p_vlan->vid)
+        return SW_NO_MORE;
+    else
+        return SW_OK;
+}
+
+static sw_error_t
+_horus_vlan_find(a_uint32_t dev_id, a_uint16_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    aos_mem_zero(p_vlan, sizeof (fal_vlan_t));
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = horus_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    horus_vlan_hw_to_sw(reg, p_vlan);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_horus_vlan_member_update(a_uint32_t dev_id, a_uint16_t vlan_id,
+                          fal_pbmp_t member, fal_pbmp_t u_member)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU))
+        return SW_BAD_PARAM;
+
+    if (u_member != 0)
+        return SW_BAD_PARAM;
+
+    /* get vlan entry first */
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = horus_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    /* set vlan member for VLAN_TABLE_FUNC1 */
+    HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VID_MEM,
+                      (a_uint8_t *) (&member), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = horus_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    /* when update port member through LOAD opration, hardware will
+        return VT_FULL_VIO, we should ignore it */
+    if (SW_FULL == rv)
+        rv = SW_OK;
+
+    return rv;
+}
+
+static sw_error_t
+_horus_vlan_delete(a_uint32_t dev_id, a_uint16_t vlan_id)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    reg = (a_int32_t) vlan_id;
+    HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VLAN_ID,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = horus_vlan_commit(dev_id, VLAN_PURGE_ENTRY);
+    return rv;
+}
+
+/**
+ * @brief Append a vlan entry on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_entry vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_vlan_entry_append(dev_id, vlan_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Creat a vlan entry through vlan id on a paticular device.
+ *   @details   Comments:
+ *    After this operation the member ports of the created vlan entry are null.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_vlan_create(dev_id, vlan_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next a vlan entry through vlan id on a paticular device.
+ *   @details   Comments:
+ *    If the value of vid is zero this operation will get the first entry.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_vlan_next(dev_id, vlan_id, p_vlan);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a vlan entry through vlan id on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_vlan_find(dev_id, vlan_id, p_vlan);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Update a vlan entry member port through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] member member ports
+ * @param[in] u_member tagged or untagged infomation for member ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                         fal_pbmp_t member, fal_pbmp_t u_member)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_vlan_member_update(dev_id, vlan_id, member, u_member);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a vlan entry through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _horus_vlan_delete(dev_id, vlan_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+horus_vlan_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->vlan_entry_append = horus_vlan_entry_append;
+    p_api->vlan_creat = horus_vlan_create;
+    p_api->vlan_member_update = horus_vlan_member_update;
+    p_api->vlan_delete = horus_vlan_delete;
+    p_api->vlan_next = horus_vlan_next;
+    p_api->vlan_find = horus_vlan_find;
+
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/hppe/Makefile b/qca-ssdk/src/hsl/hppe/Makefile
new file mode 100755
index 0000000..453b55d
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/Makefile
@@ -0,0 +1,110 @@
+LOC_DIR=src/hsl/hppe
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=hppe_init.c hppe_reg_access.c hppe_global.c
+
+ifeq (TRUE, $(IN_FLOW))
+	SRC_LIST+=hppe_flow.c
+endif
+
+ifeq (TRUE, $(IN_IP))
+	SRC_LIST+=hppe_ip.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+	SRC_LIST+=hppe_qos.c
+endif
+
+ifeq (TRUE, $(IN_FDB))
+	SRC_LIST+=hppe_fdb.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+	SRC_LIST+=hppe_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+	SRC_LIST+=hppe_stp.c
+endif
+
+ifeq (TRUE, $(IN_QM))
+	SRC_LIST+=hppe_qm.c
+endif
+
+ifeq (TRUE, $(IN_VSI))
+	SRC_LIST+=hppe_vsi.c
+endif
+
+ifeq (TRUE, $(IN_SEC))
+	SRC_LIST+=hppe_sec.c
+endif
+
+ifeq (TRUE, $(IN_BM))
+	SRC_LIST+=hppe_bm.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+	SRC_LIST+=hppe_mib.c hppe_xgmacmib.c
+endif
+
+ifeq (TRUE, $(IN_SERVCODE))
+	SRC_LIST+=hppe_servcode.c
+endif
+
+ifeq (TRUE, $(IN_CTRLPKT))
+	SRC_LIST+=hppe_ctrlpkt.c
+endif
+
+ifeq (TRUE, $(IN_RSS_HASH))
+	SRC_LIST+=hppe_rss.c
+endif
+
+ifeq (TRUE, $(IN_PPPOE))
+	SRC_LIST+=hppe_pppoe.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+	SRC_LIST+=hppe_portctrl.c hppe_xgportctrl.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+	SRC_LIST+=hppe_mirror.c
+endif
+
+ifeq (TRUE, $(IN_TRUNK))
+	SRC_LIST+=hppe_trunk.c
+endif
+
+ifeq (TRUE, $(IN_ACL))
+	SRC_LIST+=hppe_acl.c
+endif
+
+ifeq (TRUE, $(IN_POLICER))
+	SRC_LIST+=hppe_policer.c
+endif
+
+ifeq (TRUE, $(IN_SHAPER))
+	SRC_LIST+=hppe_shaper.c
+endif
+
+ifeq (TRUE, $(IN_UNIPHY))
+	SRC_LIST+=hppe_uniphy.c
+endif
+
+ifeq (, $(findstring HPPE, $(SUPPORT_CHIP)))
+  SRC_LIST=
+ifneq (, $(filter MP, $(SUPPORT_CHIP)))
+  SRC_LIST=hppe_reg_access.c
+ifeq (TRUE, $(IN_UNIPHY))
+  SRC_LIST+=hppe_uniphy.c
+endif
+endif
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/hsl/hppe/hppe_acl.c b/qca-ssdk/src/hsl/hppe/hppe_acl.c
new file mode 100755
index 0000000..6df9253
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_acl.c
@@ -0,0 +1,3164 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_acl_reg.h"
+#include "hppe_acl.h"
+
+sw_error_t
+hppe_non_ip_udf0_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + NON_IP_UDF0_CTRL_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_non_ip_udf0_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + NON_IP_UDF0_CTRL_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_non_ip_udf1_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + NON_IP_UDF1_CTRL_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_non_ip_udf1_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + NON_IP_UDF1_CTRL_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_non_ip_udf2_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + NON_IP_UDF2_CTRL_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_non_ip_udf2_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + NON_IP_UDF2_CTRL_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_non_ip_udf3_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + NON_IP_UDF3_CTRL_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_non_ip_udf3_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + NON_IP_UDF3_CTRL_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_ipv4_udf0_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV4_UDF0_CTRL_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipv4_udf0_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV4_UDF0_CTRL_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_ipv4_udf1_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV4_UDF1_CTRL_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipv4_udf1_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV4_UDF1_CTRL_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_ipv4_udf2_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV4_UDF2_CTRL_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipv4_udf2_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV4_UDF2_CTRL_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_ipv4_udf3_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV4_UDF3_CTRL_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipv4_udf3_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV4_UDF3_CTRL_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_ipv6_udf0_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV6_UDF0_CTRL_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipv6_udf0_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV6_UDF0_CTRL_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_ipv6_udf1_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV6_UDF1_CTRL_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipv6_udf1_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV6_UDF1_CTRL_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_ipv6_udf2_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV6_UDF2_CTRL_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipv6_udf2_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV6_UDF2_CTRL_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_ipv6_udf3_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV6_UDF3_CTRL_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipv6_udf3_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union udf_ctrl_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPV6_UDF3_CTRL_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_non_ip_udf0_ctrl_reg_udf0_base_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf0_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_base;
+	return ret;
+}
+
+sw_error_t
+hppe_non_ip_udf0_ctrl_reg_udf0_base_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf0_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_base = value;
+	ret = hppe_non_ip_udf0_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_non_ip_udf0_ctrl_reg_udf0_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf0_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_non_ip_udf0_ctrl_reg_udf0_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf0_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_offset = value;
+	ret = hppe_non_ip_udf0_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_non_ip_udf1_ctrl_reg_udf1_base_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf1_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_base;
+	return ret;
+}
+
+sw_error_t
+hppe_non_ip_udf1_ctrl_reg_udf1_base_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf1_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_base = value;
+	ret = hppe_non_ip_udf1_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_non_ip_udf1_ctrl_reg_udf1_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf1_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_non_ip_udf1_ctrl_reg_udf1_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf1_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_offset = value;
+	ret = hppe_non_ip_udf1_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_non_ip_udf2_ctrl_reg_udf2_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf2_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_non_ip_udf2_ctrl_reg_udf2_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf2_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_offset = value;
+	ret = hppe_non_ip_udf2_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_non_ip_udf2_ctrl_reg_udf2_base_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf2_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_base;
+	return ret;
+}
+
+sw_error_t
+hppe_non_ip_udf2_ctrl_reg_udf2_base_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf2_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_base = value;
+	ret = hppe_non_ip_udf2_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_non_ip_udf3_ctrl_reg_udf3_base_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf3_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_base;
+	return ret;
+}
+
+sw_error_t
+hppe_non_ip_udf3_ctrl_reg_udf3_base_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf3_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_base = value;
+	ret = hppe_non_ip_udf3_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_non_ip_udf3_ctrl_reg_udf3_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf3_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_non_ip_udf3_ctrl_reg_udf3_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_non_ip_udf3_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_offset = value;
+	ret = hppe_non_ip_udf3_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf0_ctrl_reg_udf0_base_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf0_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_base;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf0_ctrl_reg_udf0_base_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf0_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_base = value;
+	ret = hppe_ipv4_udf0_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf0_ctrl_reg_udf0_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf0_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf0_ctrl_reg_udf0_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf0_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_offset = value;
+	ret = hppe_ipv4_udf0_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf1_ctrl_reg_udf1_base_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf1_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_base;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf1_ctrl_reg_udf1_base_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf1_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_base = value;
+	ret = hppe_ipv4_udf1_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf1_ctrl_reg_udf1_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf1_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf1_ctrl_reg_udf1_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf1_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_offset = value;
+	ret = hppe_ipv4_udf1_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf2_ctrl_reg_udf2_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf2_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf2_ctrl_reg_udf2_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf2_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_offset = value;
+	ret = hppe_ipv4_udf2_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf2_ctrl_reg_udf2_base_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf2_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_base;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf2_ctrl_reg_udf2_base_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf2_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_base = value;
+	ret = hppe_ipv4_udf2_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf3_ctrl_reg_udf3_base_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf3_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_base;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf3_ctrl_reg_udf3_base_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf3_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_base = value;
+	ret = hppe_ipv4_udf3_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf3_ctrl_reg_udf3_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf3_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv4_udf3_ctrl_reg_udf3_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv4_udf3_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_offset = value;
+	ret = hppe_ipv4_udf3_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf0_ctrl_reg_udf0_base_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf0_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_base;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf0_ctrl_reg_udf0_base_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf0_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_base = value;
+	ret = hppe_ipv6_udf0_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf0_ctrl_reg_udf0_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf0_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf0_ctrl_reg_udf0_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf0_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_offset = value;
+	ret = hppe_ipv6_udf0_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf1_ctrl_reg_udf1_base_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf1_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_base;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf1_ctrl_reg_udf1_base_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf1_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_base = value;
+	ret = hppe_ipv6_udf1_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf1_ctrl_reg_udf1_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf1_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf1_ctrl_reg_udf1_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf1_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_offset = value;
+	ret = hppe_ipv6_udf1_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf2_ctrl_reg_udf2_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf2_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf2_ctrl_reg_udf2_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf2_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_offset = value;
+	ret = hppe_ipv6_udf2_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf2_ctrl_reg_udf2_base_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf2_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_base;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf2_ctrl_reg_udf2_base_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf2_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_base = value;
+	ret = hppe_ipv6_udf2_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf3_ctrl_reg_udf3_base_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf3_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_base;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf3_ctrl_reg_udf3_base_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf3_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_base = value;
+	ret = hppe_ipv6_udf3_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf3_ctrl_reg_udf3_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf3_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_ipv6_udf3_ctrl_reg_udf3_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union udf_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipv6_udf3_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf_offset = value;
+	ret = hppe_ipv6_udf3_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_rule_reg_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + IPO_RULE_REG_ADDRESS + \
+				index * IPO_RULE_REG_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_ipo_rule_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_rule_reg_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPO_CSR_BASE_ADDR + IPO_RULE_REG_ADDRESS + \
+				index * IPO_RULE_REG_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_ipo_mask_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_mask_reg_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + IPO_MASK_REG_ADDRESS + \
+				index * IPO_MASK_REG_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_ipo_mask_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_mask_reg_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPO_CSR_BASE_ADDR + IPO_MASK_REG_ADDRESS + \
+				index * IPO_MASK_REG_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_rule_ext_1_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rule_ext_1_reg_u *value)
+{
+	if (index >= RULE_EXT_1_REG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RULE_EXT_1_REG_ADDRESS + \
+				index * RULE_EXT_1_REG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rule_ext_1_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rule_ext_1_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RULE_EXT_1_REG_ADDRESS + \
+				index * RULE_EXT_1_REG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_rule_ext_2_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rule_ext_2_reg_u *value)
+{
+	if (index >= RULE_EXT_2_REG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RULE_EXT_2_REG_ADDRESS + \
+				index * RULE_EXT_2_REG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rule_ext_2_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rule_ext_2_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RULE_EXT_2_REG_ADDRESS + \
+				index * RULE_EXT_2_REG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_rule_ext_4_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rule_ext_4_reg_u *value)
+{
+	if (index >= RULE_EXT_4_REG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RULE_EXT_4_REG_ADDRESS + \
+				index * RULE_EXT_4_REG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rule_ext_4_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rule_ext_4_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RULE_EXT_4_REG_ADDRESS + \
+				index * RULE_EXT_4_REG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_ipo_dbg_addr_reg_get(
+		a_uint32_t dev_id,
+		union ipo_dbg_addr_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + IPO_DBG_ADDR_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipo_dbg_addr_reg_set(
+		a_uint32_t dev_id,
+		union ipo_dbg_addr_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPO_CSR_BASE_ADDR + IPO_DBG_ADDR_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_ipo_dbg_data_reg_get(
+		a_uint32_t dev_id,
+		union ipo_dbg_data_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + IPO_DBG_DATA_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipo_dbg_data_reg_set(
+		a_uint32_t dev_id,
+		union ipo_dbg_data_reg_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_ipo_spare_reg_reg_get(
+		a_uint32_t dev_id,
+		union ipo_spare_reg_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + IPO_SPARE_REG_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipo_spare_reg_reg_set(
+		a_uint32_t dev_id,
+		union ipo_spare_reg_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPO_CSR_BASE_ADDR + IPO_SPARE_REG_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_ipo_glb_hit_counter_reg_get(
+		a_uint32_t dev_id,
+		union ipo_glb_hit_counter_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + IPO_GLB_HIT_COUNTER_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipo_glb_hit_counter_reg_set(
+		a_uint32_t dev_id,
+		union ipo_glb_hit_counter_reg_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_ipo_glb_miss_counter_reg_get(
+		a_uint32_t dev_id,
+		union ipo_glb_miss_counter_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + IPO_GLB_MISS_COUNTER_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipo_glb_miss_counter_reg_set(
+		a_uint32_t dev_id,
+		union ipo_glb_miss_counter_reg_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_ipo_glb_bypass_counter_reg_get(
+		a_uint32_t dev_id,
+		union ipo_glb_bypass_counter_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + IPO_GLB_BYPASS_COUNTER_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipo_glb_bypass_counter_reg_set(
+		a_uint32_t dev_id,
+		union ipo_glb_bypass_counter_reg_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_src_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.src_1 << 3 | \
+		reg_val.bf.src_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_src_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.src_1 = value >> 3;
+	reg_val.bf.src_0 = value & (((a_uint64_t)1<<3)-1);
+	ret = hppe_ipo_rule_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_inverse_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.inverse_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_inverse_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.inverse_en = value;
+	ret = hppe_ipo_rule_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_rule_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rule_type;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_rule_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rule_type = value;
+	ret = hppe_ipo_rule_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_src_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.src_type;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_src_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.src_type = value;
+	ret = hppe_ipo_rule_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_range_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.range_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_range_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.range_en = value;
+	ret = hppe_ipo_rule_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_post_routing_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.post_routing_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_post_routing_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.post_routing_en = value;
+	ret = hppe_ipo_rule_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_fake_mac_header_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.fake_mac_header;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_fake_mac_header_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fake_mac_header = value;
+	ret = hppe_ipo_rule_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_res_chain_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.res_chain;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_res_chain_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.res_chain = value;
+	ret = hppe_ipo_rule_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pri;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pri = value;
+	ret = hppe_ipo_rule_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_rule_field_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.rule_field_1 << 32 | \
+		reg_val.bf.rule_field_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_rule_reg_rule_field_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union ipo_rule_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_rule_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rule_field_1 = value >> 32;
+	reg_val.bf.rule_field_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_ipo_rule_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_mask_reg_maskfield_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union ipo_mask_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_mask_reg_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.maskfield_1 << 32 | \
+		reg_val.bf.maskfield_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_mask_reg_maskfield_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union ipo_mask_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_mask_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.maskfield_1 = value >> 32;
+	reg_val.bf.maskfield_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_ipo_mask_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rule_ext_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rule_ext_1_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ext2_2;
+	return ret;
+}
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rule_ext_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rule_ext_1_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ext2_2 = value;
+	ret = hppe_rule_ext_1_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rule_ext_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rule_ext_1_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ext2_0;
+	return ret;
+}
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rule_ext_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rule_ext_1_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ext2_0 = value;
+	ret = hppe_rule_ext_1_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_3_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rule_ext_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rule_ext_1_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ext2_3;
+	return ret;
+}
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_3_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rule_ext_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rule_ext_1_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ext2_3 = value;
+	ret = hppe_rule_ext_1_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rule_ext_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rule_ext_1_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ext2_1;
+	return ret;
+}
+
+sw_error_t
+hppe_rule_ext_1_reg_ext2_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rule_ext_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rule_ext_1_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ext2_1 = value;
+	ret = hppe_rule_ext_1_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rule_ext_2_reg_ext4_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rule_ext_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rule_ext_2_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ext4_0;
+	return ret;
+}
+
+sw_error_t
+hppe_rule_ext_2_reg_ext4_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rule_ext_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rule_ext_2_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ext4_0 = value;
+	ret = hppe_rule_ext_2_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rule_ext_2_reg_ext4_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rule_ext_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rule_ext_2_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ext4_1;
+	return ret;
+}
+
+sw_error_t
+hppe_rule_ext_2_reg_ext4_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rule_ext_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rule_ext_2_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ext4_1 = value;
+	ret = hppe_rule_ext_2_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rule_ext_4_reg_ext8_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rule_ext_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rule_ext_4_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ext8;
+	return ret;
+}
+
+sw_error_t
+hppe_rule_ext_4_reg_ext8_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rule_ext_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rule_ext_4_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ext8 = value;
+	ret = hppe_rule_ext_4_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_dbg_addr_reg_ipo_dbg_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union ipo_dbg_addr_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_dbg_addr_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.ipo_dbg_addr;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_dbg_addr_reg_ipo_dbg_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union ipo_dbg_addr_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_dbg_addr_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipo_dbg_addr = value;
+	ret = hppe_ipo_dbg_addr_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_dbg_data_reg_ipo_dbg_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union ipo_dbg_data_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_dbg_data_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.ipo_dbg_data;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_dbg_data_reg_ipo_dbg_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_ipo_spare_reg_reg_spare_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union ipo_spare_reg_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_spare_reg_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.spare_reg;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_spare_reg_reg_spare_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union ipo_spare_reg_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_spare_reg_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.spare_reg = value;
+	ret = hppe_ipo_spare_reg_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_glb_hit_counter_reg_hit_count_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union ipo_glb_hit_counter_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_glb_hit_counter_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.hit_count;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_glb_hit_counter_reg_hit_count_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_ipo_glb_miss_counter_reg_miss_count_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union ipo_glb_miss_counter_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_glb_miss_counter_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.miss_count;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_glb_miss_counter_reg_miss_count_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_ipo_glb_bypass_counter_reg_bypass_count_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union ipo_glb_bypass_counter_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_glb_bypass_counter_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.bypass_count;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_glb_bypass_counter_reg_bypass_count_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+
+sw_error_t
+hppe_ipo_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IPO_CNT_TBL_ADDRESS + \
+				index * IPO_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_ipo_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IPO_CNT_TBL_ADDRESS + \
+				index * IPO_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_ipo_cnt_tbl_hit_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union ipo_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.hit_byte_cnt_1 << 32 | \
+		reg_val.bf.hit_byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_cnt_tbl_hit_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union ipo_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hit_byte_cnt_1 = value >> 32;
+	reg_val.bf.hit_byte_cnt_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_ipo_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_cnt_tbl_hit_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.hit_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_cnt_tbl_hit_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hit_pkt_cnt = value;
+	ret = hppe_ipo_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+
+sw_error_t
+hppe_ipo_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_action_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + IPO_ACTION_ADDRESS + \
+				index * IPO_ACTION_INC,
+				value->val,
+				5);
+}
+
+sw_error_t
+hppe_ipo_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipo_action_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + IPO_ACTION_ADDRESS + \
+				index * IPO_ACTION_INC,
+				value->val,
+				5);
+}
+
+sw_error_t
+hppe_ipo_action_mirror_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mirror_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_mirror_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mirror_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_ctag_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ctag_pcp_1 << 2 | \
+		reg_val.bf.ctag_pcp_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_ctag_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ctag_pcp_1 = value >> 2;
+	reg_val.bf.ctag_pcp_0 = value & (((a_uint64_t)1<<2)-1);
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_int_dp_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.int_dp_change_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_int_dp_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.int_dp_change_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_enqueue_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.enqueue_pri;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_enqueue_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.enqueue_pri = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_stag_pcp_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.stag_pcp_change_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_stag_pcp_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.stag_pcp_change_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_dscp_tc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dscp_tc;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_dscp_tc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dscp_tc = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_cpu_code_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cpu_code_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_cpu_code_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cpu_code_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_stag_dei_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.stag_dei_change_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_stag_dei_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.stag_dei_change_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_ctag_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ctag_fmt;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_ctag_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ctag_fmt = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_dest_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dest_info;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_dest_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dest_info = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_svid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.svid;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_svid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.svid = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_dest_info_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dest_info_change_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_dest_info_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dest_info_change_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_policer_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.policer_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_policer_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.policer_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_int_dp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.int_dp;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_int_dp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.int_dp = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_ctag_pcp_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ctag_pcp_change_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_ctag_pcp_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ctag_pcp_change_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_metadata_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.metadata_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_metadata_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.metadata_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_enqueue_pri_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.enqueue_pri_change_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_enqueue_pri_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.enqueue_pri_change_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_stag_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.stag_dei;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_stag_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.stag_dei = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_fwd_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.fwd_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_fwd_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fwd_cmd = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_bypass_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.bypass_bitmap_1 << 14 | \
+		reg_val.bf.bypass_bitmap_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_bypass_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.bypass_bitmap_1 = value >> 14;
+	reg_val.bf.bypass_bitmap_0 = value & (((a_uint64_t)1<<14)-1);
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_ctag_dei_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ctag_dei_change_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_ctag_dei_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ctag_dei_change_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_policer_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.policer_index;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_policer_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.policer_index = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_ctag_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ctag_dei;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_ctag_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ctag_dei = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_stag_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.stag_pcp;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_stag_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.stag_pcp = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_syn_toggle_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.syn_toggle;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_syn_toggle_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.syn_toggle = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_service_code_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.service_code_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_service_code_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.service_code_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_qid_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.qid_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_qid_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.qid_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_service_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.service_code_1 << 1 | \
+		reg_val.bf.service_code_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_service_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.service_code_1 = value >> 1;
+	reg_val.bf.service_code_0 = value & (((a_uint64_t)1<<1)-1);
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_cvid_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cvid_change_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_cvid_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cvid_change_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_cvid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cvid;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_cvid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cvid = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_svid_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.svid_change_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_svid_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.svid_change_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_cpu_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cpu_code;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_cpu_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cpu_code = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_dscp_tc_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dscp_tc_change_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_dscp_tc_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dscp_tc_change_en = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_qid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.qid;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_qid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.qid = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_stag_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.stag_fmt;
+	return ret;
+}
+
+sw_error_t
+hppe_ipo_action_stag_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipo_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipo_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.stag_fmt = value;
+	ret = hppe_ipo_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_bm.c b/qca-ssdk/src/hsl/hppe/hppe_bm.c
new file mode 100755
index 0000000..989275f
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_bm.c
@@ -0,0 +1,3027 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_bm_reg.h"
+#include "hppe_bm.h"
+
+#ifndef IN_BM_MINI
+sw_error_t
+hppe_fb_fifo_cfg_get(
+		a_uint32_t dev_id,
+		union fb_fifo_cfg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + FB_FIFO_CFG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_fb_fifo_cfg_set(
+		a_uint32_t dev_id,
+		union fb_fifo_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + FB_FIFO_CFG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_fp_fifo_cfg_get(
+		a_uint32_t dev_id,
+		union fp_fifo_cfg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + FP_FIFO_CFG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_fp_fifo_cfg_set(
+		a_uint32_t dev_id,
+		union fp_fifo_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + FP_FIFO_CFG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_deq_fifo_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union deq_fifo_cfg_u *value)
+{
+	if (index >= DEQ_FIFO_CFG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + DEQ_FIFO_CFG_ADDRESS + \
+				index * DEQ_FIFO_CFG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_deq_fifo_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union deq_fifo_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + DEQ_FIFO_CFG_ADDRESS + \
+				index * DEQ_FIFO_CFG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_tick_dly_cfg_get(
+		a_uint32_t dev_id,
+		union tick_dly_cfg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + TICK_DLY_CFG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_tick_dly_cfg_set(
+		a_uint32_t dev_id,
+		union tick_dly_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + TICK_DLY_CFG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_bm_rsv_0_get(
+		a_uint32_t dev_id,
+		union bm_rsv_0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + BM_RSV_0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_bm_rsv_0_set(
+		a_uint32_t dev_id,
+		union bm_rsv_0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + BM_RSV_0_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_bm_rsv_1_get(
+		a_uint32_t dev_id,
+		union bm_rsv_1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + BM_RSV_1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_bm_rsv_1_set(
+		a_uint32_t dev_id,
+		union bm_rsv_1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + BM_RSV_1_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_bm_dbg_addr_get(
+		a_uint32_t dev_id,
+		union bm_dbg_addr_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + BM_DBG_ADDR_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_bm_dbg_addr_set(
+		a_uint32_t dev_id,
+		union bm_dbg_addr_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + BM_DBG_ADDR_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_bm_dbg_data_get(
+		a_uint32_t dev_id,
+		union bm_dbg_data_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + BM_DBG_DATA_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_bm_dbg_data_set(
+		a_uint32_t dev_id,
+		union bm_dbg_data_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port_fc_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_fc_mode_u *value)
+{
+	if (index >= PORT_FC_MODE_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_FC_MODE_ADDRESS + \
+				index * PORT_FC_MODE_INC,
+				&value->val);
+}
+#endif
+
+sw_error_t
+hppe_port_fc_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_fc_mode_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_FC_MODE_ADDRESS + \
+				index * PORT_FC_MODE_INC,
+				value->val);
+}
+
+#ifndef IN_BM_MINI
+sw_error_t
+hppe_port_fc_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_fc_status_u *value)
+{
+	if (index >= PORT_FC_STATUS_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_FC_STATUS_ADDRESS + \
+				index * PORT_FC_STATUS_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_fc_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_fc_status_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port_group_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_group_id_u *value)
+{
+	if (index >= PORT_GROUP_ID_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_GROUP_ID_ADDRESS + \
+				index * PORT_GROUP_ID_INC,
+				&value->val);
+}
+#endif
+
+sw_error_t
+hppe_port_group_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_group_id_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_GROUP_ID_ADDRESS + \
+				index * PORT_GROUP_ID_INC,
+				value->val);
+}
+
+#ifndef IN_BM_MINI
+sw_error_t
+hppe_port_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_cnt_u *value)
+{
+	if (index >= PORT_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_CNT_ADDRESS + \
+				index * PORT_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_cnt_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port_reacted_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_reacted_cnt_u *value)
+{
+	if (index >= PORT_REACTED_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_REACTED_CNT_ADDRESS + \
+				index * PORT_REACTED_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_reacted_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_reacted_cnt_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_shared_group_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union shared_group_cnt_u *value)
+{
+	if (index >= SHARED_GROUP_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + SHARED_GROUP_CNT_ADDRESS + \
+				index * SHARED_GROUP_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_shared_group_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union shared_group_cnt_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_shared_group_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union shared_group_cfg_u *value)
+{
+	if (index >= SHARED_GROUP_CFG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + SHARED_GROUP_CFG_ADDRESS + \
+				index * SHARED_GROUP_CFG_INC,
+				&value->val);
+}
+#endif
+
+sw_error_t
+hppe_shared_group_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union shared_group_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + SHARED_GROUP_CFG_ADDRESS + \
+				index * SHARED_GROUP_CFG_INC,
+				value->val);
+}
+
+#ifndef IN_BM_MINI
+sw_error_t
+hppe_port_profile_cnt_en_get(
+		a_uint32_t dev_id,
+		union port_profile_cnt_en_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_PROFILE_CNT_EN_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_set(
+		a_uint32_t dev_id,
+		union port_profile_cnt_en_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_PROFILE_CNT_EN_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_grp_profile_cnt_en_get(
+		a_uint32_t dev_id,
+		union grp_profile_cnt_en_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + GRP_PROFILE_CNT_EN_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_grp_profile_cnt_en_set(
+		a_uint32_t dev_id,
+		union grp_profile_cnt_en_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + GRP_PROFILE_CNT_EN_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_port_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_profile_th_cfg_u *value)
+{
+	if (index >= PORT_PROFILE_TH_CFG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_PROFILE_TH_CFG_ADDRESS + \
+				index * PORT_PROFILE_TH_CFG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_profile_th_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_PROFILE_TH_CFG_ADDRESS + \
+				index * PORT_PROFILE_TH_CFG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_react_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union react_profile_th_cfg_u *value)
+{
+	if (index >= REACT_PROFILE_TH_CFG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + REACT_PROFILE_TH_CFG_ADDRESS + \
+				index * REACT_PROFILE_TH_CFG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_react_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union react_profile_th_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + REACT_PROFILE_TH_CFG_ADDRESS + \
+				index * REACT_PROFILE_TH_CFG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_grp_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_profile_th_cfg_u *value)
+{
+	if (index >= GRP_PROFILE_TH_CFG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + GRP_PROFILE_TH_CFG_ADDRESS + \
+				index * GRP_PROFILE_TH_CFG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_grp_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_profile_th_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + GRP_PROFILE_TH_CFG_ADDRESS + \
+				index * GRP_PROFILE_TH_CFG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_tot_react_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		union tot_react_profile_th_cfg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + TOT_REACT_PROFILE_TH_CFG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_tot_react_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		union tot_react_profile_th_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + TOT_REACT_PROFILE_TH_CFG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_port_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_out_profile_cnt_u *value)
+{
+	if (index >= PORT_OUT_PROFILE_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_OUT_PROFILE_CNT_ADDRESS + \
+				index * PORT_OUT_PROFILE_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_out_profile_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_OUT_PROFILE_CNT_ADDRESS + \
+				index * PORT_OUT_PROFILE_CNT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_port_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_in_profile_cnt_u *value)
+{
+	if (index >= PORT_IN_PROFILE_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_IN_PROFILE_CNT_ADDRESS + \
+				index * PORT_IN_PROFILE_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_in_profile_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_IN_PROFILE_CNT_ADDRESS + \
+				index * PORT_IN_PROFILE_CNT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_react_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union react_out_profile_cnt_u *value)
+{
+	if (index >= REACT_OUT_PROFILE_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + REACT_OUT_PROFILE_CNT_ADDRESS + \
+				index * REACT_OUT_PROFILE_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_react_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union react_out_profile_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + REACT_OUT_PROFILE_CNT_ADDRESS + \
+				index * REACT_OUT_PROFILE_CNT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_react_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union react_in_profile_cnt_u *value)
+{
+	if (index >= REACT_IN_PROFILE_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + REACT_IN_PROFILE_CNT_ADDRESS + \
+				index * REACT_IN_PROFILE_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_react_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union react_in_profile_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + REACT_IN_PROFILE_CNT_ADDRESS + \
+				index * REACT_IN_PROFILE_CNT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_grp_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_out_profile_cnt_u *value)
+{
+	if (index >= GRP_OUT_PROFILE_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + GRP_OUT_PROFILE_CNT_ADDRESS + \
+				index * GRP_OUT_PROFILE_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_grp_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_out_profile_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + GRP_OUT_PROFILE_CNT_ADDRESS + \
+				index * GRP_OUT_PROFILE_CNT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_grp_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_in_profile_cnt_u *value)
+{
+	if (index >= GRP_IN_PROFILE_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + GRP_IN_PROFILE_CNT_ADDRESS + \
+				index * GRP_IN_PROFILE_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_grp_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_in_profile_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + GRP_IN_PROFILE_CNT_ADDRESS + \
+				index * GRP_IN_PROFILE_CNT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_tot_react_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		union tot_react_out_profile_cnt_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + TOT_REACT_OUT_PROFILE_CNT_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_tot_react_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		union tot_react_out_profile_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + TOT_REACT_OUT_PROFILE_CNT_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_tot_react_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		union tot_react_in_profile_cnt_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + TOT_REACT_IN_PROFILE_CNT_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_tot_react_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		union tot_react_in_profile_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + TOT_REACT_IN_PROFILE_CNT_ADDRESS,
+				value->val);
+}
+#endif
+
+sw_error_t
+hppe_port_fc_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_fc_cfg_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_FC_CFG_ADDRESS + \
+				index * PORT_FC_CFG_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_port_fc_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_fc_cfg_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + PORT_FC_CFG_ADDRESS + \
+				index * PORT_FC_CFG_INC,
+				value->val,
+				2);
+}
+
+#ifndef IN_BM_MINI
+sw_error_t
+hppe_llm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union llm_u *value)
+{
+	if (index >= LLM_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + LLM_ADDRESS + \
+				index * LLM_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_llm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union llm_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + LLM_ADDRESS + \
+				index * LLM_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_rcm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rcm_u *value)
+{
+	if (index >= RCM_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + RCM_ADDRESS + \
+				index * RCM_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rcm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rcm_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + RCM_ADDRESS + \
+				index * RCM_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_dm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union dm_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + DM_ADDRESS + \
+				index * DM_INC,
+				value->val,
+				16);
+}
+
+sw_error_t
+hppe_dm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union dm_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				NSS_BM_CSR_BASE_ADDR + DM_ADDRESS + \
+				index * DM_INC,
+				value->val,
+				16);
+}
+
+sw_error_t
+hppe_fb_fifo_cfg_fb_fifo_thres_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fb_fifo_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fb_fifo_cfg_get(dev_id, &reg_val);
+	*value = reg_val.bf.fb_fifo_thres;
+	return ret;
+}
+
+sw_error_t
+hppe_fb_fifo_cfg_fb_fifo_thres_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fb_fifo_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fb_fifo_cfg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fb_fifo_thres = value;
+	ret = hppe_fb_fifo_cfg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_fp_fifo_cfg_fp_fifo_thres_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fp_fifo_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fp_fifo_cfg_get(dev_id, &reg_val);
+	*value = reg_val.bf.fp_fifo_thres;
+	return ret;
+}
+
+sw_error_t
+hppe_fp_fifo_cfg_fp_fifo_thres_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fp_fifo_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fp_fifo_cfg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fp_fifo_thres = value;
+	ret = hppe_fp_fifo_cfg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_deq_fifo_cfg_deq_fifo_thres_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union deq_fifo_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_deq_fifo_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.deq_fifo_thres;
+	return ret;
+}
+
+sw_error_t
+hppe_deq_fifo_cfg_deq_fifo_thres_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union deq_fifo_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_deq_fifo_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.deq_fifo_thres = value;
+	ret = hppe_deq_fifo_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_tick_dly_cfg_tick_dly_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union tick_dly_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tick_dly_cfg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tick_dly;
+	return ret;
+}
+
+sw_error_t
+hppe_tick_dly_cfg_tick_dly_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union tick_dly_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tick_dly_cfg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tick_dly = value;
+	ret = hppe_tick_dly_cfg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_bm_rsv_0_rsv_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union bm_rsv_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_bm_rsv_0_get(dev_id, &reg_val);
+	*value = reg_val.bf.rsv_0;
+	return ret;
+}
+
+sw_error_t
+hppe_bm_rsv_0_rsv_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union bm_rsv_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_bm_rsv_0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rsv_0 = value;
+	ret = hppe_bm_rsv_0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_bm_rsv_1_rsv_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union bm_rsv_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_bm_rsv_1_get(dev_id, &reg_val);
+	*value = reg_val.bf.rsv_1;
+	return ret;
+}
+
+sw_error_t
+hppe_bm_rsv_1_rsv_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union bm_rsv_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_bm_rsv_1_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rsv_1 = value;
+	ret = hppe_bm_rsv_1_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_bm_dbg_addr_dbg_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union bm_dbg_addr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_bm_dbg_addr_get(dev_id, &reg_val);
+	*value = reg_val.bf.dbg_addr;
+	return ret;
+}
+
+sw_error_t
+hppe_bm_dbg_addr_dbg_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union bm_dbg_addr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_bm_dbg_addr_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dbg_addr = value;
+	ret = hppe_bm_dbg_addr_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_bm_dbg_data_dbg_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union bm_dbg_data_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_bm_dbg_data_get(dev_id, &reg_val);
+	*value = reg_val.bf.dbg_data;
+	return ret;
+}
+
+sw_error_t
+hppe_bm_dbg_data_dbg_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port_fc_mode_fc_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_fc_mode_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_mode_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.fc_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_mode_fc_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_fc_mode_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_mode_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fc_en = value;
+	ret = hppe_port_fc_mode_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_status_port_fc_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_fc_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_fc_status;
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_status_port_fc_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port_fc_status_port_xon_th_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_fc_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_xon_th;
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_status_port_xon_th_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port_group_id_port_shared_group_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_group_id_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_group_id_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_shared_group_id;
+	return ret;
+}
+
+sw_error_t
+hppe_port_group_id_port_shared_group_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_group_id_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_group_id_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_shared_group_id = value;
+	ret = hppe_port_group_id_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_cnt_port_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_port_cnt_port_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port_reacted_cnt_port_reacted_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_reacted_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_reacted_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_reacted_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_port_reacted_cnt_port_reacted_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_shared_group_cnt_shared_group_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union shared_group_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_shared_group_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.shared_group_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_shared_group_cnt_shared_group_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_shared_group_cfg_shared_group_limit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union shared_group_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_shared_group_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.shared_group_limit;
+	return ret;
+}
+
+sw_error_t
+hppe_shared_group_cfg_shared_group_limit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union shared_group_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_shared_group_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.shared_group_limit = value;
+	ret = hppe_shared_group_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_8_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.react_cnt_en_8;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_8_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_cnt_en_8 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_7_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.react_cnt_en_7;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_7_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_cnt_en_7 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_6_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_cnt_en_6;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_6_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_cnt_en_6 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.react_cnt_en_2;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_2_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_cnt_en_2 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_8_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_cnt_en_8;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_8_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_cnt_en_8 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_5_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_cnt_en_5;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_5_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_cnt_en_5 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_12_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_cnt_en_12;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_12_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_cnt_en_12 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.react_cnt_en_4;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_4_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_cnt_en_4 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_3_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_cnt_en_3;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_3_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_cnt_en_3 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_10_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_cnt_en_10;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_10_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_cnt_en_10 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_cnt_en_4;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_4_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_cnt_en_4 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_5_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.react_cnt_en_5;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_5_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_cnt_en_5 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_14_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_cnt_en_14;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_14_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_cnt_en_14 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_14_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.react_cnt_en_14;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_14_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_cnt_en_14 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_3_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.react_cnt_en_3;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_3_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_cnt_en_3 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_cnt_en_1;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_cnt_en_1 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_cnt_en_0;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_cnt_en_0 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_7_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_cnt_en_7;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_7_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_cnt_en_7 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_13_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_cnt_en_13;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_13_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_cnt_en_13 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_6_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.react_cnt_en_6;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_6_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_cnt_en_6 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.react_cnt_en_0;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_cnt_en_0 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_13_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.react_cnt_en_13;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_13_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_cnt_en_13 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_11_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_cnt_en_11;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_11_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_cnt_en_11 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.react_cnt_en_1;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_cnt_en_1 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_12_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.react_cnt_en_12;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_12_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_cnt_en_12 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_11_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.react_cnt_en_11;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_11_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_cnt_en_11 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_10_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.react_cnt_en_10;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_10_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_cnt_en_10 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_9_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_cnt_en_9;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_9_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_cnt_en_9 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_cnt_en_2;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_port_cnt_en_2_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_cnt_en_2 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_9_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.react_cnt_en_9;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_cnt_en_react_cnt_en_9_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_cnt_en_9 = value;
+	ret = hppe_port_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_3_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union grp_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.grp_cnt_en_3;
+	return ret;
+}
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_3_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union grp_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grp_cnt_en_3 = value;
+	ret = hppe_grp_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_grp_profile_cnt_en_tot_rect_cnt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union grp_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.tot_rect_cnt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_grp_profile_cnt_en_tot_rect_cnt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union grp_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tot_rect_cnt_en = value;
+	ret = hppe_grp_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union grp_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.grp_cnt_en_1;
+	return ret;
+}
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union grp_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grp_cnt_en_1 = value;
+	ret = hppe_grp_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union grp_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.grp_cnt_en_0;
+	return ret;
+}
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union grp_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grp_cnt_en_0 = value;
+	ret = hppe_grp_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union grp_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.grp_cnt_en_2;
+	return ret;
+}
+
+sw_error_t
+hppe_grp_profile_cnt_en_grp_cnt_en_2_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union grp_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grp_cnt_en_2 = value;
+	ret = hppe_grp_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_th_cfg_port_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_profile_th_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_th_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_profile_th_cfg;
+	return ret;
+}
+
+sw_error_t
+hppe_port_profile_th_cfg_port_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_profile_th_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_profile_th_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_profile_th_cfg = value;
+	ret = hppe_port_profile_th_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_react_profile_th_cfg_react_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union react_profile_th_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_react_profile_th_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.react_profile_th_cfg;
+	return ret;
+}
+
+sw_error_t
+hppe_react_profile_th_cfg_react_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union react_profile_th_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_react_profile_th_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_profile_th_cfg = value;
+	ret = hppe_react_profile_th_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_grp_profile_th_cfg_grp_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union grp_profile_th_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_profile_th_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.grp_profile_th_cfg;
+	return ret;
+}
+
+sw_error_t
+hppe_grp_profile_th_cfg_grp_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union grp_profile_th_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_profile_th_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grp_profile_th_cfg = value;
+	ret = hppe_grp_profile_th_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_tot_react_profile_th_cfg_tot_react_profile_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union tot_react_profile_th_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tot_react_profile_th_cfg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tot_react_profile_th_cfg;
+	return ret;
+}
+
+sw_error_t
+hppe_tot_react_profile_th_cfg_tot_react_profile_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union tot_react_profile_th_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tot_react_profile_th_cfg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tot_react_profile_th_cfg = value;
+	ret = hppe_tot_react_profile_th_cfg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_out_profile_cnt_port_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_out_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_out_profile_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_out_profile_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_port_out_profile_cnt_port_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_out_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_out_profile_cnt_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_out_profile_cnt = value;
+	ret = hppe_port_out_profile_cnt_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_in_profile_cnt_port_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_in_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_in_profile_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_in_profile_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_port_in_profile_cnt_port_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_in_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_in_profile_cnt_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_in_profile_cnt = value;
+	ret = hppe_port_in_profile_cnt_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_react_out_profile_cnt_react_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union react_out_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_react_out_profile_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.react_out_profile_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_react_out_profile_cnt_react_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union react_out_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_react_out_profile_cnt_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_out_profile_cnt = value;
+	ret = hppe_react_out_profile_cnt_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_react_in_profile_cnt_react_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union react_in_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_react_in_profile_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.react_in_profile_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_react_in_profile_cnt_react_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union react_in_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_react_in_profile_cnt_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.react_in_profile_cnt = value;
+	ret = hppe_react_in_profile_cnt_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_grp_out_profile_cnt_grp_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union grp_out_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_out_profile_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.grp_out_profile_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_grp_out_profile_cnt_grp_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union grp_out_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_out_profile_cnt_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grp_out_profile_cnt = value;
+	ret = hppe_grp_out_profile_cnt_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_grp_in_profile_cnt_grp_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union grp_in_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_in_profile_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.grp_in_profile_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_grp_in_profile_cnt_grp_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union grp_in_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_in_profile_cnt_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grp_in_profile_cnt = value;
+	ret = hppe_grp_in_profile_cnt_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_tot_react_out_profile_cnt_tot_react_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union tot_react_out_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tot_react_out_profile_cnt_get(dev_id, &reg_val);
+	*value = reg_val.bf.tot_react_out_profile_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_tot_react_out_profile_cnt_tot_react_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union tot_react_out_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tot_react_out_profile_cnt_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tot_react_out_profile_cnt = value;
+	ret = hppe_tot_react_out_profile_cnt_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_tot_react_in_profile_cnt_tot_react_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union tot_react_in_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tot_react_in_profile_cnt_get(dev_id, &reg_val);
+	*value = reg_val.bf.tot_react_in_profile_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_tot_react_in_profile_cnt_tot_react_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union tot_react_in_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tot_react_in_profile_cnt_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tot_react_in_profile_cnt = value;
+	ret = hppe_tot_react_in_profile_cnt_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_cfg_port_pre_alloc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_fc_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_pre_alloc;
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_cfg_port_pre_alloc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_fc_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_pre_alloc = value;
+	ret = hppe_port_fc_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_cfg_port_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_fc_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_resume_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_cfg_port_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_fc_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_resume_offset = value;
+	ret = hppe_port_fc_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_cfg_port_shared_dynamic_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_fc_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_shared_dynamic;
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_cfg_port_shared_dynamic_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_fc_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_shared_dynamic = value;
+	ret = hppe_port_fc_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_cfg_port_shared_weight_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_fc_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_shared_weight;
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_cfg_port_shared_weight_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_fc_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_shared_weight = value;
+	ret = hppe_port_fc_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_cfg_port_resume_floor_th_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_fc_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_resume_floor_th;
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_cfg_port_resume_floor_th_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_fc_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_resume_floor_th = value;
+	ret = hppe_port_fc_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_cfg_port_react_limit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_fc_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_react_limit;
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_cfg_port_react_limit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_fc_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_react_limit = value;
+	ret = hppe_port_fc_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_cfg_port_shared_ceiling_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_fc_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_shared_ceiling_1 << 3 | \
+		reg_val.bf.port_shared_ceiling_0;
+	return ret;
+}
+
+sw_error_t
+hppe_port_fc_cfg_port_shared_ceiling_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_fc_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_fc_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_shared_ceiling_1 = value >> 3;
+	reg_val.bf.port_shared_ceiling_0 = value & (((a_uint64_t)1<<3)-1);
+	ret = hppe_port_fc_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_llm_eop_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union llm_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_llm_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.eop;
+	return ret;
+}
+
+sw_error_t
+hppe_llm_eop_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union llm_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_llm_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.eop = value;
+	ret = hppe_llm_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_llm_nxt_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union llm_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_llm_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.nxt_ptr;
+	return ret;
+}
+
+sw_error_t
+hppe_llm_nxt_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union llm_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_llm_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.nxt_ptr = value;
+	ret = hppe_llm_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rcm_ref_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rcm_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rcm_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ref_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_rcm_ref_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rcm_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rcm_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ref_cnt = value;
+	ret = hppe_rcm_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_dm_pkt_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union dm_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_dm_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.pkt_data_1 << 32 | \
+		reg_val.bf.pkt_data_0;
+	return ret;
+}
+
+sw_error_t
+hppe_dm_pkt_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union dm_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_dm_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pkt_data_1 = value >> 32;
+	reg_val.bf.pkt_data_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_dm_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
diff --git a/qca-ssdk/src/hsl/hppe/hppe_ctrlpkt.c b/qca-ssdk/src/hsl/hppe/hppe_ctrlpkt.c
new file mode 100755
index 0000000..a3ff314
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_ctrlpkt.c
@@ -0,0 +1,581 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_ctrlpkt_reg.h"
+#include "hppe_ctrlpkt.h"
+
+sw_error_t
+hppe_ethertype_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ethertype_ctrl_u *value)
+{
+	if (index >= ETHERTYPE_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + ETHERTYPE_CTRL_ADDRESS + \
+				index * ETHERTYPE_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_ethertype_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ethertype_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + ETHERTYPE_CTRL_ADDRESS + \
+				index * ETHERTYPE_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_app_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union app_ctrl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + APP_CTRL_ADDRESS + \
+				index * APP_CTRL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_app_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union app_ctrl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + APP_CTRL_ADDRESS + \
+				index * APP_CTRL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_ethertype_ctrl_ethertype_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ethertype_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ethertype_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ethertype;
+	return ret;
+}
+
+sw_error_t
+hppe_ethertype_ctrl_ethertype_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ethertype_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ethertype_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ethertype = value;
+	ret = hppe_ethertype_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ethertype_ctrl_ethertype_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ethertype_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ethertype_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ethertype_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ethertype_ctrl_ethertype_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ethertype_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ethertype_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ethertype_en = value;
+	ret = hppe_ethertype_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_portbitmap_include_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.portbitmap_include;
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_portbitmap_include_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.portbitmap_include = value;
+	ret = hppe_app_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmd = value;
+	ret = hppe_app_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_portbitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.portbitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_portbitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.portbitmap = value;
+	ret = hppe_app_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_rfdb_index_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rfdb_index_bitmap_1 << 30 | \
+		reg_val.bf.rfdb_index_bitmap_0;
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_rfdb_index_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rfdb_index_bitmap_1 = value >> 30;
+	reg_val.bf.rfdb_index_bitmap_0 = value & (((a_uint64_t)1<<30)-1);
+	ret = hppe_app_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_protocol_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.protocol_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_protocol_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.protocol_bitmap = value;
+	ret = hppe_app_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_in_stg_byp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.in_stg_byp;
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_in_stg_byp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.in_stg_byp = value;
+	ret = hppe_app_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.valid;
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.valid = value;
+	ret = hppe_app_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_l2_sec_byp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.l2_sec_byp;
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_l2_sec_byp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_sec_byp = value;
+	ret = hppe_app_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_protocol_include_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.protocol_include;
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_protocol_include_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.protocol_include = value;
+	ret = hppe_app_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_ethertype_include_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ethertype_include;
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_ethertype_include_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ethertype_include = value;
+	ret = hppe_app_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_sg_byp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.sg_byp;
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_sg_byp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.sg_byp = value;
+	ret = hppe_app_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_rfdb_include_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rfdb_include;
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_rfdb_include_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rfdb_include = value;
+	ret = hppe_app_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_ethertype_index_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ethertype_index_bitmap_1 << 2 | \
+		reg_val.bf.ethertype_index_bitmap_0;
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_ethertype_index_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ethertype_index_bitmap_1 = value >> 2;
+	reg_val.bf.ethertype_index_bitmap_0 = value & (((a_uint64_t)1<<2)-1);
+	ret = hppe_app_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_in_vlan_fltr_byp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.in_vlan_fltr_byp;
+	return ret;
+}
+
+sw_error_t
+hppe_app_ctrl_in_vlan_fltr_byp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union app_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_app_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.in_vlan_fltr_byp = value;
+	ret = hppe_app_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_fdb.c b/qca-ssdk/src/hsl/hppe/hppe_fdb.c
new file mode 100755
index 0000000..43481d0
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_fdb.c
@@ -0,0 +1,2178 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_fdb_reg.h"
+#include "hppe_fdb.h"
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_l2_dbg_addr_get(
+		a_uint32_t dev_id,
+		union l2_dbg_addr_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + L2_DBG_ADDR_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l2_dbg_addr_set(
+		a_uint32_t dev_id,
+		union l2_dbg_addr_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + L2_DBG_ADDR_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_l2_dbg_data_get(
+		a_uint32_t dev_id,
+		union l2_dbg_data_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + L2_DBG_DATA_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l2_dbg_data_set(
+		a_uint32_t dev_id,
+		union l2_dbg_data_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_OP_ADDRESS,
+				&value->val);
+}
+#endif
+sw_error_t
+hppe_fdb_tbl_op_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_OP_ADDRESS,
+				value->val);
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_fdb_tbl_rd_op_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_ADDRESS,
+				&value->val);
+}
+#endif
+sw_error_t
+hppe_fdb_tbl_rd_op_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_rslt_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_OP_RSLT_ADDRESS,
+				&value->val);
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_fdb_tbl_op_rslt_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_rslt_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_RSLT_ADDRESS,
+				&value->val);
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_age_timer_get(
+		a_uint32_t dev_id,
+		union age_timer_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + AGE_TIMER_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_age_timer_set(
+		a_uint32_t dev_id,
+		union age_timer_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + AGE_TIMER_ADDRESS,
+				value->val);
+}
+#endif
+sw_error_t
+hppe_l2_global_conf_get(
+		a_uint32_t dev_id,
+		union l2_global_conf_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + L2_GLOBAL_CONF_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l2_global_conf_set(
+		a_uint32_t dev_id,
+		union l2_global_conf_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + L2_GLOBAL_CONF_ADDRESS,
+				value->val);
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_l2_dbgcnt_cmd_get(
+		a_uint32_t dev_id,
+		union l2_dbgcnt_cmd_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + L2_DBGCNT_CMD_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l2_dbgcnt_cmd_set(
+		a_uint32_t dev_id,
+		union l2_dbgcnt_cmd_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + L2_DBGCNT_CMD_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_l2_dbgcnt_rdata_get(
+		a_uint32_t dev_id,
+		union l2_dbgcnt_rdata_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + L2_DBGCNT_RDATA_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l2_dbgcnt_rdata_set(
+		a_uint32_t dev_id,
+		union l2_dbgcnt_rdata_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l2_dbgcnt_wdata_get(
+		a_uint32_t dev_id,
+		union l2_dbgcnt_wdata_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + L2_DBGCNT_WDATA_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l2_dbgcnt_wdata_set(
+		a_uint32_t dev_id,
+		union l2_dbgcnt_wdata_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + L2_DBGCNT_WDATA_ADDRESS,
+				value->val);
+}
+#endif
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data0_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_data0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_RSLT_DATA0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data0_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_data0_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data1_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_data1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_RSLT_DATA1_ADDRESS,
+				&value->val);
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data1_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_data1_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data2_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_data2_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_RSLT_DATA2_ADDRESS,
+				&value->val);
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data2_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_rslt_data2_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
+sw_error_t
+hppe_fdb_tbl_op_data0_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_data0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_OP_DATA0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_fdb_tbl_op_data0_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_data0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_OP_DATA0_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_fdb_tbl_op_data1_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_data1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_OP_DATA1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_fdb_tbl_op_data1_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_data1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_OP_DATA1_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_fdb_tbl_op_data2_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_data2_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_OP_DATA2_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_fdb_tbl_op_data2_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_op_data2_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_OP_DATA2_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data0_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_data0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_DATA0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data0_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_data0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_DATA0_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data1_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_data1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_DATA1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data1_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_data1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_DATA1_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data2_get(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_data2_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_DATA2_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_data2_set(
+		a_uint32_t dev_id,
+		union fdb_tbl_rd_op_data2_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_DATA2_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_port_bridge_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_bridge_ctrl_u *value)
+{
+	if (index >= PORT_BRIDGE_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + \
+				index * PORT_BRIDGE_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_bridge_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_bridge_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + \
+				index * PORT_BRIDGE_CTRL_INC,
+				value->val);
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_port_lrn_limit_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_lrn_limit_ctrl_u *value)
+{
+	if (index >= PORT_LRN_LIMIT_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + PORT_LRN_LIMIT_CTRL_ADDRESS + \
+				index * PORT_LRN_LIMIT_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_lrn_limit_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_lrn_limit_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + PORT_LRN_LIMIT_CTRL_ADDRESS + \
+				index * PORT_LRN_LIMIT_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_port_lrn_limit_counter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_lrn_limit_counter_u *value)
+{
+	if (index >= PORT_LRN_LIMIT_COUNTER_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + PORT_LRN_LIMIT_COUNTER_ADDRESS + \
+				index * PORT_LRN_LIMIT_COUNTER_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_lrn_limit_counter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_lrn_limit_counter_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
+sw_error_t
+hppe_rfdb_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rfdb_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + RFDB_TBL_ADDRESS + \
+				index * RFDB_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_rfdb_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rfdb_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + RFDB_TBL_ADDRESS + \
+				index * RFDB_TBL_INC,
+				value->val,
+				2);
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_fdb_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union fdb_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_ADDRESS + \
+				index * FDB_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_fdb_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union fdb_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + FDB_TBL_ADDRESS + \
+				index * FDB_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_l2_dbg_addr_l2_dbg_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l2_dbg_addr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_dbg_addr_get(dev_id, &reg_val);
+	*value = reg_val.bf.l2_dbg_addr;
+	return ret;
+}
+
+sw_error_t
+hppe_l2_dbg_addr_l2_dbg_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l2_dbg_addr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_dbg_addr_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_dbg_addr = value;
+	ret = hppe_l2_dbg_addr_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l2_dbg_data_l2_dbg_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l2_dbg_data_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_dbg_data_get(dev_id, &reg_val);
+	*value = reg_val.bf.l2_dbg_data;
+	return ret;
+}
+
+sw_error_t
+hppe_l2_dbg_data_l2_dbg_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_op_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_op_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_mode = value;
+	ret = hppe_fdb_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_op_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_type;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_op_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_type = value;
+	ret = hppe_fdb_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.entry_index = value;
+	ret = hppe_fdb_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_cmd_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.cmd_id;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_cmd_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmd_id = value;
+	ret = hppe_fdb_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.hash_block_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hash_block_bitmap = value;
+	ret = hppe_fdb_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_byp_rslt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.byp_rslt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_byp_rslt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.byp_rslt_en = value;
+	ret = hppe_fdb_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_op_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_op_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_mode = value;
+	ret = hppe_fdb_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_op_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_type;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_op_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_type = value;
+	ret = hppe_fdb_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.entry_index = value;
+	ret = hppe_fdb_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_cmd_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.cmd_id;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_cmd_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmd_id = value;
+	ret = hppe_fdb_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.hash_block_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hash_block_bitmap = value;
+	ret = hppe_fdb_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_byp_rslt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.byp_rslt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_byp_rslt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.byp_rslt_en = value;
+	ret = hppe_fdb_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_op_rslt_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_rslt;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_op_rslt_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_valid_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.valid_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_valid_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_cmd_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.cmd_id;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_rslt_cmd_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_op_rslt_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_rslt;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_op_rslt_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_valid_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.valid_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_valid_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_cmd_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.cmd_id;
+	return ret;
+}
+
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_cmd_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_age_timer_age_val_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union age_timer_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_age_timer_get(dev_id, &reg_val);
+	*value = reg_val.bf.age_val;
+	return ret;
+}
+
+sw_error_t
+hppe_age_timer_age_val_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union age_timer_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_age_timer_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.age_val = value;
+	ret = hppe_age_timer_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_fdb_hash_full_fwd_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	*value = reg_val.bf.fdb_hash_full_fwd_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_fdb_hash_full_fwd_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fdb_hash_full_fwd_cmd = value;
+	ret = hppe_l2_global_conf_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_failover_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	*value = reg_val.bf.failover_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_failover_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.failover_en = value;
+	ret = hppe_l2_global_conf_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_lrn_ctrl_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	*value = reg_val.bf.lrn_ctrl_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_lrn_ctrl_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.lrn_ctrl_mode = value;
+	ret = hppe_l2_global_conf_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_age_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	*value = reg_val.bf.age_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_age_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.age_en = value;
+	ret = hppe_l2_global_conf_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_fdb_hash_mode_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	*value = reg_val.bf.fdb_hash_mode_1;
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_fdb_hash_mode_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fdb_hash_mode_1 = value;
+	ret = hppe_l2_global_conf_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_lrn_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	*value = reg_val.bf.lrn_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_lrn_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.lrn_en = value;
+	ret = hppe_l2_global_conf_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_fdb_hash_mode_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	*value = reg_val.bf.fdb_hash_mode_0;
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_fdb_hash_mode_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fdb_hash_mode_0 = value;
+	ret = hppe_l2_global_conf_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_age_ctrl_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	*value = reg_val.bf.age_ctrl_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_age_ctrl_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.age_ctrl_mode = value;
+	ret = hppe_l2_global_conf_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_service_code_loop_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	*value = reg_val.bf.service_code_loop;
+	return ret;
+}
+
+sw_error_t
+hppe_l2_global_conf_service_code_loop_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l2_global_conf_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_global_conf_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.service_code_loop = value;
+	ret = hppe_l2_global_conf_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l2_dbgcnt_cmd_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l2_dbgcnt_cmd_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_dbgcnt_cmd_get(dev_id, &reg_val);
+	*value = reg_val.bf.type;
+	return ret;
+}
+
+sw_error_t
+hppe_l2_dbgcnt_cmd_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l2_dbgcnt_cmd_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_dbgcnt_cmd_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.type = value;
+	ret = hppe_l2_dbgcnt_cmd_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l2_dbgcnt_cmd_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l2_dbgcnt_cmd_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_dbgcnt_cmd_get(dev_id, &reg_val);
+	*value = reg_val.bf.addr;
+	return ret;
+}
+
+sw_error_t
+hppe_l2_dbgcnt_cmd_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l2_dbgcnt_cmd_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_dbgcnt_cmd_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.addr = value;
+	ret = hppe_l2_dbgcnt_cmd_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l2_dbgcnt_rdata_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l2_dbgcnt_rdata_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_dbgcnt_rdata_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_l2_dbgcnt_rdata_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l2_dbgcnt_wdata_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l2_dbgcnt_wdata_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_dbgcnt_wdata_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_l2_dbgcnt_wdata_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l2_dbgcnt_wdata_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l2_dbgcnt_wdata_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_l2_dbgcnt_wdata_set(dev_id, &reg_val);
+	return ret;
+}
+#endif
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data0_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_rslt_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_rslt_data0_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data0_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data1_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_rslt_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_rslt_data1_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data1_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data2_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_rslt_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_rslt_data2_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_fdb_tbl_rd_op_rslt_data2_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_fdb_tbl_op_data0_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_data0_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_fdb_tbl_op_data0_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_data0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_fdb_tbl_op_data0_set(dev_id, &reg_val);
+	return ret;
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_fdb_tbl_op_data1_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_data1_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_fdb_tbl_op_data1_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_data1_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_fdb_tbl_op_data1_set(dev_id, &reg_val);
+	return ret;
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_fdb_tbl_op_data2_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_data2_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_fdb_tbl_op_data2_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_op_data2_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_fdb_tbl_op_data2_set(dev_id, &reg_val);
+	return ret;
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_fdb_tbl_rd_op_data0_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_data0_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_fdb_tbl_rd_op_data0_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_rd_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_data0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_fdb_tbl_rd_op_data0_set(dev_id, &reg_val);
+	return ret;
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_fdb_tbl_rd_op_data1_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_data1_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_fdb_tbl_rd_op_data1_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_rd_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_data1_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_fdb_tbl_rd_op_data1_set(dev_id, &reg_val);
+	return ret;
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_fdb_tbl_rd_op_data2_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union fdb_tbl_rd_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_data2_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_fdb_tbl_rd_op_data2_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union fdb_tbl_rd_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_fdb_tbl_rd_op_data2_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_fdb_tbl_rd_op_data2_set(dev_id, &reg_val);
+	return ret;
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_port_bridge_ctrl_txmac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_bridge_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_bridge_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txmac_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_bridge_ctrl_txmac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_bridge_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_bridge_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.txmac_en = value;
+	ret = hppe_port_bridge_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_bridge_ctrl_port_isolation_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_bridge_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_bridge_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_isolation_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_port_bridge_ctrl_port_isolation_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_bridge_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_bridge_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_isolation_bitmap = value;
+	ret = hppe_port_bridge_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_bridge_ctrl_station_move_lrn_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_bridge_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_bridge_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.station_move_lrn_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_bridge_ctrl_station_move_lrn_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_bridge_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_bridge_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.station_move_lrn_en = value;
+	ret = hppe_port_bridge_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_bridge_ctrl_new_addr_fwd_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_bridge_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_bridge_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.new_addr_fwd_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_port_bridge_ctrl_new_addr_fwd_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_bridge_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_bridge_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.new_addr_fwd_cmd = value;
+	ret = hppe_port_bridge_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_bridge_ctrl_promisc_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_bridge_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_bridge_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.promisc_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_bridge_ctrl_promisc_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_bridge_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_bridge_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.promisc_en = value;
+	ret = hppe_port_bridge_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_bridge_ctrl_new_addr_lrn_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_bridge_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_bridge_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.new_addr_lrn_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_bridge_ctrl_new_addr_lrn_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_bridge_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_bridge_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.new_addr_lrn_en = value;
+	ret = hppe_port_bridge_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_bridge_ctrl_station_move_fwd_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_bridge_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_bridge_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.station_move_fwd_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_port_bridge_ctrl_station_move_fwd_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_bridge_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_bridge_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.station_move_fwd_cmd = value;
+	ret = hppe_port_bridge_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_lrn_limit_ctrl_lrn_lmt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_lrn_limit_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_lrn_limit_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lrn_lmt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_lrn_limit_ctrl_lrn_lmt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_lrn_limit_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_lrn_limit_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.lrn_lmt_en = value;
+	ret = hppe_port_lrn_limit_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_lrn_limit_ctrl_lrn_lmt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_lrn_limit_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_lrn_limit_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lrn_lmt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_port_lrn_limit_ctrl_lrn_lmt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_lrn_limit_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_lrn_limit_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.lrn_lmt_cnt = value;
+	ret = hppe_port_lrn_limit_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_lrn_limit_ctrl_lrn_lmt_exceed_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_lrn_limit_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_lrn_limit_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lrn_lmt_exceed_fwd;
+	return ret;
+}
+
+sw_error_t
+hppe_port_lrn_limit_ctrl_lrn_lmt_exceed_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_lrn_limit_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_lrn_limit_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.lrn_lmt_exceed_fwd = value;
+	ret = hppe_port_lrn_limit_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_lrn_limit_counter_lrn_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_lrn_limit_counter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_lrn_limit_counter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lrn_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_port_lrn_limit_counter_lrn_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
+sw_error_t
+hppe_rfdb_tbl_mac_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union rfdb_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rfdb_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.mac_addr_1 << 32 | \
+		reg_val.bf.mac_addr_0;
+	return ret;
+}
+
+sw_error_t
+hppe_rfdb_tbl_mac_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union rfdb_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rfdb_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr_1 = value >> 32;
+	reg_val.bf.mac_addr_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_rfdb_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+hppe_rfdb_tbl_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rfdb_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rfdb_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.valid;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_rfdb_tbl_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rfdb_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rfdb_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.valid = value;
+	ret = hppe_rfdb_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_flow.c b/qca-ssdk/src/hsl/hppe/hppe_flow.c
new file mode 100755
index 0000000..f2fabba
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_flow.c
@@ -0,0 +1,5814 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_flow_reg.h"
+#include "hppe_flow.h"
+#include "hppe_ip_reg.h"
+#include "hppe_ip.h"
+
+#ifndef IN_FLOW_MINI
+static a_uint32_t flow_cmd_id = 0;
+static a_uint32_t flow_host_cmd_id = 0;
+
+sw_error_t
+hppe_in_flow_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IN_FLOW_CNT_TBL_ADDRESS + \
+				index * IN_FLOW_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_in_flow_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IN_FLOW_CNT_TBL_ADDRESS + \
+				index * IN_FLOW_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_flow_ctrl0_get(
+		a_uint32_t dev_id,
+		union flow_ctrl0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_CTRL0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_ctrl0_set(
+		a_uint32_t dev_id,
+		union flow_ctrl0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_CTRL0_ADDRESS,
+				value->val);
+}
+#endif
+
+sw_error_t
+hppe_flow_ctrl1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union flow_ctrl1_u *value)
+{
+	if (index >= FLOW_CTRL1_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_CTRL1_ADDRESS + \
+				index * FLOW_CTRL1_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_ctrl1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union flow_ctrl1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_CTRL1_ADDRESS + \
+				index * FLOW_CTRL1_INC,
+				value->val);
+}
+
+#ifndef IN_FLOW_MINI
+sw_error_t
+hppe_in_flow_tbl_op_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_host_tbl_op_get(
+		a_uint32_t dev_id,
+		union in_flow_host_tbl_op_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_HOST_TBL_OP_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_host_tbl_op_set(
+		a_uint32_t dev_id,
+		union in_flow_host_tbl_op_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_HOST_TBL_OP_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data0_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data0_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA0_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data1_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data1_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA1_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data2_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data2_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA2_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data2_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data2_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA2_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data3_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data3_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA3_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data3_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data3_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA3_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data4_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data4_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA4_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data4_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data4_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA4_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data5_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data5_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA5_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data5_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data5_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA5_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data6_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data6_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA6_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data6_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data6_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA6_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data7_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data7_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA7_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data7_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data7_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA7_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data8_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data8_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA8_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data8_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_data8_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA8_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data0_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data0_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA0_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data1_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data1_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA1_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data2_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data2_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA2_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data2_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data2_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA2_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data3_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data3_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA3_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data3_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data3_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA3_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data4_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data4_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA4_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data4_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data4_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA4_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data5_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data5_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA5_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data5_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data5_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA5_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data6_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data6_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA6_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data6_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data6_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA6_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data7_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data7_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA7_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data7_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data7_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA7_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data8_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data8_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA8_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data8_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data8_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA8_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data9_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data9_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA9_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data9_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_data9_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA9_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_rslt_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_RSLT_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_op_rslt_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_rslt_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_rslt_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_RSLT_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_rslt_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_op_rslt_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_host_tbl_rd_op_get(
+		a_uint32_t dev_id,
+		union in_flow_host_tbl_rd_op_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_HOST_TBL_RD_OP_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_host_tbl_rd_op_set(
+		a_uint32_t dev_id,
+		union in_flow_host_tbl_rd_op_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_HOST_TBL_RD_OP_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data0_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data0_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA0_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data1_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data1_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA1_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data2_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data2_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA2_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data2_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data2_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA2_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data3_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data3_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA3_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data3_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data3_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA3_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data4_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data4_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA4_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data4_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data4_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA4_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data5_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data5_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA5_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data5_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data5_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA5_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data6_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data6_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA6_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data6_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data6_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA6_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data7_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data7_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA7_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data7_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data7_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA7_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data8_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data8_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA8_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data8_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_data8_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA8_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data0_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data0_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA0_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data1_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data1_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA1_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data2_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data2_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA2_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data2_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data2_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA2_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data3_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data3_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA3_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data3_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data3_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA3_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data4_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data4_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA4_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data4_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data4_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA4_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data5_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data5_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA5_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data5_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data5_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA5_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data6_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data6_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA6_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data6_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data6_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA6_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data7_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data7_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA7_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data7_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data7_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA7_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data8_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data8_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA8_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data8_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data8_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA8_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data9_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data9_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA9_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data9_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_data9_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA9_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_rslt_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_RSLT_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_op_rslt_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_rslt_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_rslt_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_RSLT_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_rslt_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_op_rslt_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data0_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data0_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data0_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data1_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data1_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data1_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data2_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data2_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA2_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data2_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data2_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data3_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data3_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA3_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data3_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data3_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data4_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data4_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA4_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data4_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data4_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data5_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data5_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA5_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data5_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data5_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data6_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data6_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA6_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data6_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data6_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data7_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data7_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA7_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data7_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data7_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data8_get(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data8_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA8_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data8_set(
+		a_uint32_t dev_id,
+		union in_flow_tbl_rd_rslt_data8_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data0_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data0_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data0_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data1_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data1_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data1_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data2_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data2_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA2_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data2_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data2_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data3_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data3_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA3_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data3_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data3_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data4_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data4_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA4_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data4_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data4_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data5_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data5_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA5_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data5_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data5_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data6_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data6_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA6_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data6_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data6_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data7_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data7_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA7_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data7_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data7_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data8_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data8_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA8_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data8_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data8_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data9_get(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data9_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA9_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data9_set(
+		a_uint32_t dev_id,
+		union flow_host_tbl_rd_rslt_data9_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_3tuple_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_3tuple_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_3TUPLE_TBL_ADDRESS + \
+				index * IN_FLOW_3TUPLE_TBL_INC,
+				value->val,
+				4);
+}
+
+sw_error_t
+hppe_in_flow_3tuple_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_3tuple_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_3TUPLE_TBL_ADDRESS + \
+				index * IN_FLOW_3TUPLE_TBL_INC,
+				value->val,
+				4);
+}
+
+sw_error_t
+hppe_in_flow_ipv6_3tuple_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_ipv6_3tuple_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_IPV6_3TUPLE_TBL_ADDRESS + \
+				index * IN_FLOW_IPV6_3TUPLE_TBL_INC,
+				value->val,
+				9);
+}
+
+sw_error_t
+hppe_in_flow_ipv6_3tuple_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_ipv6_3tuple_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_IPV6_3TUPLE_TBL_ADDRESS + \
+				index * IN_FLOW_IPV6_3TUPLE_TBL_INC,
+				value->val,
+				9);
+}
+
+sw_error_t
+hppe_in_flow_ipv6_5tuple_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_ipv6_5tuple_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_IPV6_5TUPLE_TBL_ADDRESS + \
+				index * IN_FLOW_IPV6_5TUPLE_TBL_INC,
+				value->val,
+				9);
+}
+
+sw_error_t
+hppe_in_flow_ipv6_5tuple_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_ipv6_5tuple_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_IPV6_5TUPLE_TBL_ADDRESS + \
+				index * IN_FLOW_IPV6_5TUPLE_TBL_INC,
+				value->val,
+				9);
+}
+
+sw_error_t
+hppe_in_flow_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_ADDRESS + \
+				index * IN_FLOW_TBL_INC,
+				value->val,
+				5);
+}
+
+sw_error_t
+hppe_in_flow_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_flow_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_ADDRESS + \
+				index * IN_FLOW_TBL_INC,
+				value->val,
+				5);
+}
+
+sw_error_t
+hppe_eg_flow_tree_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_flow_tree_map_tbl_u *value)
+{
+	if (index >= EG_FLOW_TREE_MAP_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_FLOW_TREE_MAP_TBL_ADDRESS + \
+				index * EG_FLOW_TREE_MAP_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_eg_flow_tree_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_flow_tree_map_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_FLOW_TREE_MAP_TBL_ADDRESS + \
+				index * EG_FLOW_TREE_MAP_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_ctrl0_flow_hash_mode_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl0_get(dev_id, &reg_val);
+	*value = reg_val.bf.flow_hash_mode_0;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl0_flow_hash_mode_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_hash_mode_0 = value;
+	ret = hppe_flow_ctrl0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl0_flow_age_timer_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl0_get(dev_id, &reg_val);
+	*value = reg_val.bf.flow_age_timer_unit;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl0_flow_age_timer_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_age_timer_unit = value;
+	ret = hppe_flow_ctrl0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl0_flow_hash_mode_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl0_get(dev_id, &reg_val);
+	*value = reg_val.bf.flow_hash_mode_1;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl0_flow_hash_mode_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_hash_mode_1 = value;
+	ret = hppe_flow_ctrl0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl0_flow_age_timer_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl0_get(dev_id, &reg_val);
+	*value = reg_val.bf.flow_age_timer;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl0_flow_age_timer_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_age_timer = value;
+	ret = hppe_flow_ctrl0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl0_flow_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl0_get(dev_id, &reg_val);
+	*value = reg_val.bf.flow_en;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl0_flow_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_en = value;
+	ret = hppe_flow_ctrl0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_frag_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl1_frag_bypass;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_frag_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl1_frag_bypass = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_key_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl4_key_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_key_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl4_key_sel = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_key_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl1_key_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_key_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl1_key_sel = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_frag_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl0_frag_bypass;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_frag_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl0_frag_bypass = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_miss_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl0_miss_action;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_miss_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl0_miss_action = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_key_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl0_key_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_key_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl0_key_sel = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl1_bypass;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl1_bypass = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl0_bypass;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl0_bypass = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_tcp_special_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl2_tcp_special;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_tcp_special_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl2_tcp_special = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_tcp_special_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl4_tcp_special;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_tcp_special_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl4_tcp_special = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_frag_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl3_frag_bypass;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_frag_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl3_frag_bypass = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl3_bypass;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl3_bypass = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_tcp_special_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl3_tcp_special;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_tcp_special_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl3_tcp_special = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_miss_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl1_miss_action;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_miss_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl1_miss_action = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_frag_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl4_frag_bypass;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_frag_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl4_frag_bypass = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_tcp_special_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl1_tcp_special;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl1_tcp_special_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl1_tcp_special = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_key_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl2_key_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_key_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl2_key_sel = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_miss_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl2_miss_action;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_miss_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl2_miss_action = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl2_bypass;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl2_bypass = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl4_bypass;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl4_bypass = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_key_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl3_key_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_key_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl3_key_sel = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_tcp_special_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl0_tcp_special;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl0_tcp_special_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl0_tcp_special = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_frag_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl2_frag_bypass;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl2_frag_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl2_frag_bypass = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_miss_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl3_miss_action;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl3_miss_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl3_miss_action = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_miss_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_ctl4_miss_action;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_ctrl1_flow_ctl4_miss_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_ctl4_miss_action = value;
+	ret = hppe_flow_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.entry_index = value;
+	ret = hppe_in_flow_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_cmd_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.cmd_id;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_cmd_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmd_id = value;
+	ret = hppe_in_flow_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_byp_rslt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.byp_rslt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_byp_rslt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.byp_rslt_en = value;
+	ret = hppe_in_flow_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_op_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_op_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_mode = value;
+	ret = hppe_in_flow_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_op_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_type;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_op_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_type = value;
+	ret = hppe_in_flow_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_op_host_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_host_en;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_op_host_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_host_en = value;
+	ret = hppe_in_flow_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_op_result_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_result;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_op_result_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_result = value;
+	ret = hppe_in_flow_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_busy_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.busy;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_busy_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.busy = value;
+	ret = hppe_in_flow_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.hash_block_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hash_block_bitmap = value;
+	ret = hppe_in_flow_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_host_tbl_op_host_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_host_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.host_entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_host_tbl_op_host_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_host_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.host_entry_index = value;
+	ret = hppe_in_flow_host_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_host_tbl_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_host_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.hash_block_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_host_tbl_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_host_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hash_block_bitmap = value;
+	ret = hppe_in_flow_host_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data0_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data0_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data0_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_op_data0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data1_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data1_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data1_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data1_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_op_data1_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data2_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data2_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data2_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data2_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_op_data2_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data3_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_data3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data3_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data3_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_data3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data3_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_op_data3_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data4_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_data4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data4_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data4_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_data4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data4_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_op_data4_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data5_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_data5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data5_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data5_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_data5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data5_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_op_data5_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data6_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_data6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data6_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data6_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_data6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data6_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_op_data6_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data7_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_data7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data7_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data7_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_data7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data7_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_op_data7_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data8_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_data8_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data8_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_data8_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_op_data8_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_data8_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_op_data8_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data0_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data0_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data0_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_op_data0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data1_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data1_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data1_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data1_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_op_data1_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data2_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data2_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data2_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data2_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_op_data2_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data3_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_op_data3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data3_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data3_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_op_data3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data3_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_op_data3_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data4_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_op_data4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data4_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data4_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_op_data4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data4_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_op_data4_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data5_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_op_data5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data5_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data5_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_op_data5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data5_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_op_data5_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data6_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_op_data6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data6_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data6_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_op_data6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data6_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_op_data6_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data7_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_op_data7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data7_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data7_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_op_data7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data7_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_op_data7_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data8_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_op_data8_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data8_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data8_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_op_data8_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data8_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_op_data8_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data9_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_op_data9_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data9_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_data9_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_op_data9_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_data9_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_op_data9_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_op_rslt_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_rslt;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_op_rslt_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_valid_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.valid_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_valid_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_flow_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.flow_entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_flow_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_cmd_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.cmd_id;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_op_rslt_cmd_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_rslt_host_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.host_entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_op_rslt_host_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.entry_index = value;
+	ret = hppe_in_flow_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_cmd_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.cmd_id;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_cmd_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmd_id = value;
+	ret = hppe_in_flow_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_byp_rslt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.byp_rslt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_byp_rslt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.byp_rslt_en = value;
+	ret = hppe_in_flow_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_mode = value;
+	ret = hppe_in_flow_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_type;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_type = value;
+	ret = hppe_in_flow_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_host_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_host_en;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_host_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_host_en = value;
+	ret = hppe_in_flow_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_result_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_result;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_op_result_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_result = value;
+	ret = hppe_in_flow_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_busy_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.busy;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_busy_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.busy = value;
+	ret = hppe_in_flow_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.hash_block_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hash_block_bitmap = value;
+	ret = hppe_in_flow_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_host_tbl_rd_op_host_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_host_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.host_entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_host_tbl_rd_op_host_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_host_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.host_entry_index = value;
+	ret = hppe_in_flow_host_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_host_tbl_rd_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_host_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.hash_block_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_host_tbl_rd_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_host_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hash_block_bitmap = value;
+	ret = hppe_in_flow_host_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data0_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data0_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data0_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_rd_op_data0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data1_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data1_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data1_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data1_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_rd_op_data1_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data2_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data2_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data2_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data2_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_rd_op_data2_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data3_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_data3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data3_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data3_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_data3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data3_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_rd_op_data3_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data4_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_data4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data4_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data4_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_data4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data4_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_rd_op_data4_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data5_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_data5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data5_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data5_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_data5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data5_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_rd_op_data5_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data6_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_data6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data6_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data6_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_data6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data6_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_rd_op_data6_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data7_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_data7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data7_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data7_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_data7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data7_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_rd_op_data7_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data8_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_data8_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data8_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_data8_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_flow_tbl_rd_op_data8_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_data8_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_in_flow_tbl_rd_op_data8_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data0_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data0_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data0_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_rd_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_rd_op_data0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data1_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data1_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data1_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_rd_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data1_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_rd_op_data1_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data2_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data2_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data2_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_rd_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data2_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_rd_op_data2_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data3_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_op_data3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data3_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data3_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_rd_op_data3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data3_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_rd_op_data3_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data4_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_op_data4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data4_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data4_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_rd_op_data4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data4_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_rd_op_data4_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data5_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_op_data5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data5_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data5_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_rd_op_data5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data5_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_rd_op_data5_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data6_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_op_data6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data6_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data6_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_rd_op_data6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data6_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_rd_op_data6_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data7_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_op_data7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data7_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data7_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_rd_op_data7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data7_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_rd_op_data7_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data8_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_op_data8_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data8_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data8_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_rd_op_data8_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data8_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_rd_op_data8_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data9_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_op_data9_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data9_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_data9_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flow_host_tbl_rd_op_data9_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_data9_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_flow_host_tbl_rd_op_data9_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_op_rslt_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_rslt;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_op_rslt_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_valid_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.valid_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_valid_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_flow_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.flow_entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_flow_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_cmd_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.cmd_id;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_op_rslt_cmd_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_rslt_host_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.host_entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_op_rslt_host_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data0_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_rslt_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_rslt_data0_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data0_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data1_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_rslt_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_rslt_data1_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data1_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data2_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_rslt_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_rslt_data2_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data2_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data3_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_rslt_data3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_rslt_data3_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data3_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data4_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_rslt_data4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_rslt_data4_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data4_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data5_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_rslt_data5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_rslt_data5_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data5_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data6_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_rslt_data6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_rslt_data6_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data6_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data7_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_rslt_data7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_rslt_data7_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data7_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data8_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_flow_tbl_rd_rslt_data8_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_tbl_rd_rslt_data8_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_tbl_rd_rslt_data8_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data0_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_rslt_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_rslt_data0_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data0_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data1_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_rslt_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_rslt_data1_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data1_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data2_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_rslt_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_rslt_data2_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data2_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data3_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_rslt_data3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_rslt_data3_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data3_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data4_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_rslt_data4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_rslt_data4_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data4_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data5_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_rslt_data5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_rslt_data5_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data5_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data6_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_rslt_data6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_rslt_data6_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data6_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data7_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_rslt_data7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_rslt_data7_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data7_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data8_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_rslt_data8_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_rslt_data8_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data8_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data9_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flow_host_tbl_rd_rslt_data9_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_host_tbl_rd_rslt_data9_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_host_tbl_rd_rslt_data9_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_eg_flow_tree_map_tbl_tree_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_flow_tree_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_flow_tree_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tree_id;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_flow_tree_map_tbl_tree_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_flow_tree_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_flow_tree_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tree_id = value;
+	ret = hppe_eg_flow_tree_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_cnt_tbl_hit_byte_counter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union in_flow_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.hit_byte_counter_1 << 32 | \
+		reg_val.bf.hit_byte_counter_0;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_cnt_tbl_hit_byte_counter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union in_flow_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hit_byte_counter_1 = value >> 32;
+	reg_val.bf.hit_byte_counter_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_in_flow_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_cnt_tbl_hit_pkt_counter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_flow_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.hit_pkt_counter;
+	return ret;
+}
+
+sw_error_t
+hppe_in_flow_cnt_tbl_hit_pkt_counter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_flow_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_flow_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hit_pkt_counter = value;
+	ret = hppe_in_flow_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+
+sw_error_t
+hppe_flow_get_common(
+		a_uint32_t dev_id,
+		a_uint32_t op_mode,
+		a_uint32_t *index,
+		a_uint32_t *data,
+		a_uint32_t num)
+{
+	union in_flow_tbl_rd_op_u op;
+	union in_flow_tbl_rd_op_rslt_u result;
+	a_uint32_t i = 0x100;
+	sw_error_t rv;
+
+	op.bf.cmd_id = flow_cmd_id;
+	flow_cmd_id++;
+	op.bf.byp_rslt_en = 0;
+	op.bf.op_type = 2;
+	op.bf.hash_block_bitmap = 3;
+	op.bf.op_mode = op_mode;
+	op.bf.entry_index = *index;
+	op.bf.op_host_en = 0;
+
+	rv = hppe_in_flow_tbl_rd_op_set(dev_id, &op);
+	if (SW_OK != rv)
+		return rv;
+	rv = hppe_in_flow_tbl_rd_op_rslt_get(dev_id, &result);
+	if (SW_OK != rv)
+		return rv;
+	while (!result.bf.valid_cnt && --i) {
+		hppe_in_flow_tbl_rd_op_rslt_get(dev_id, &result);
+	}
+	if (i == 0)
+		return SW_BUSY;
+	if (result.bf.op_rslt == 0) {
+		hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA0_ADDRESS,
+				data, num);
+		*index = result.bf.flow_entry_index;
+		return SW_OK;
+	}
+	else
+		return SW_FAIL;
+	
+}
+
+
+sw_error_t
+hppe_flow_flush_common(a_uint32_t dev_id)
+{
+	union in_flow_tbl_op_u op;
+	union in_flow_tbl_op_rslt_u result;
+	a_uint32_t i = 0x100 * 50;
+	sw_error_t rv;
+
+	op.bf.cmd_id = flow_cmd_id;
+	flow_cmd_id++;
+	op.bf.byp_rslt_en = 0;
+	op.bf.op_type = 3;
+	op.bf.hash_block_bitmap = 3;
+	op.bf.op_mode = 0;
+	op.bf.op_host_en = 0;
+
+	rv = hppe_in_flow_tbl_op_set(dev_id, &op);
+	if (SW_OK != rv)
+		return rv;
+	rv = hppe_in_flow_tbl_op_rslt_get(dev_id, &result);
+	if (SW_OK != rv)
+		return rv;
+	while (!result.bf.valid_cnt && --i) {
+		hppe_in_flow_tbl_op_rslt_get(dev_id, &result);
+	}
+	if (i == 0)
+		return SW_BUSY;
+	if (result.bf.op_rslt == 0)
+		return SW_OK;
+	else
+		return SW_FAIL;
+	
+	
+}
+
+sw_error_t
+hppe_flow_op_common(
+		a_uint32_t dev_id,
+		a_uint32_t op_type,
+		a_uint32_t op_mode,
+		a_uint32_t *index)
+{
+	union in_flow_tbl_op_u op;
+	union in_flow_tbl_op_rslt_u result;
+	a_uint32_t i = 0x100;
+	sw_error_t rv;
+
+	op.bf.cmd_id = flow_cmd_id;
+	flow_cmd_id++;
+	op.bf.byp_rslt_en = 0;
+	op.bf.op_type = op_type;
+	op.bf.hash_block_bitmap = 3;
+	op.bf.op_mode = op_mode;
+	op.bf.entry_index = *index;
+	op.bf.op_host_en = 0;
+
+	rv = hppe_in_flow_tbl_op_set(dev_id, &op);
+	if (SW_OK != rv)
+		return rv;
+	rv = hppe_in_flow_tbl_op_rslt_get(dev_id, &result);
+	if (SW_OK != rv)
+		return rv;
+	while (!result.bf.valid_cnt && --i) {
+		hppe_in_flow_tbl_op_rslt_get(dev_id, &result);
+	}
+	if (i == 0)
+		return SW_BUSY;
+	if (result.bf.op_rslt == 0) {
+		*index = result.bf.flow_entry_index;
+		return SW_OK;
+	}
+	else
+		return SW_FAIL;
+	
+}
+
+#include "hppe_ip_reg.h"
+
+sw_error_t
+hppe_flow_host_get_common(
+		a_uint32_t dev_id,
+		a_uint32_t op_mode,
+		a_uint32_t *index,
+		a_uint32_t *data,
+		a_uint32_t num)
+{
+	union in_flow_tbl_rd_op_u op;
+	union in_flow_tbl_rd_op_rslt_u result;
+	a_uint32_t i = 0x100;
+	sw_error_t rv;
+
+	op.bf.cmd_id = flow_host_cmd_id;
+	flow_host_cmd_id++;
+	op.bf.byp_rslt_en = 0;
+	op.bf.op_type = 2;
+	op.bf.hash_block_bitmap = 3;
+	op.bf.op_mode = op_mode;
+	op.bf.entry_index = *index;
+	op.bf.op_host_en = 1;
+
+	rv = hppe_in_flow_tbl_rd_op_set(dev_id, &op);
+	if (SW_OK != rv)
+		return rv;
+	rv = hppe_in_flow_tbl_rd_op_rslt_get(dev_id, &result);
+	if (SW_OK != rv)
+		return rv;
+	while (!result.bf.valid_cnt && --i) {
+		hppe_in_flow_tbl_rd_op_rslt_get(dev_id, &result);
+	}
+	if (i == 0)
+		return SW_BUSY;
+
+	if (result.bf.op_rslt == 0) {
+		hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA0_ADDRESS,
+				data, num);
+		*index = result.bf.flow_entry_index;
+		return SW_OK;
+	}
+	else
+		return SW_FAIL;
+}
+
+sw_error_t
+hppe_flow_host_flush_common(a_uint32_t dev_id)
+{
+	union in_flow_tbl_op_u op;
+	union in_flow_tbl_op_rslt_u result;
+	a_uint32_t i = 0x100 * 50;
+	sw_error_t rv;
+
+	op.bf.cmd_id = flow_host_cmd_id;
+	flow_host_cmd_id++;
+	op.bf.byp_rslt_en = 0;
+	op.bf.op_type = 3;
+	op.bf.hash_block_bitmap = 3;
+	op.bf.op_mode = 0;
+	op.bf.op_host_en = 1;
+
+	rv = hppe_in_flow_tbl_op_set(dev_id, &op);
+	if (SW_OK != rv)
+		return rv;
+	rv = hppe_in_flow_tbl_op_rslt_get(dev_id, &result);
+	if (SW_OK != rv)
+		return rv;
+	while (!result.bf.valid_cnt && --i) {
+		hppe_in_flow_tbl_op_rslt_get(dev_id, &result);
+	}
+	if (i == 0)
+		return SW_BUSY;
+	if (result.bf.op_rslt == 0)
+		return SW_OK;
+	else
+		return SW_FAIL;
+}
+
+sw_error_t
+hppe_flow_host_op_both_common(
+		a_uint32_t dev_id,
+		a_uint32_t op_type,
+		a_uint32_t op_mode,
+		a_uint32_t *index)
+{
+	union in_flow_tbl_op_u op;
+	union in_flow_tbl_op_rslt_u result;
+	a_uint32_t i = 0x100;
+	sw_error_t rv;
+
+	op.bf.cmd_id = flow_host_cmd_id;
+	flow_host_cmd_id++;
+	op.bf.byp_rslt_en = 0;
+	op.bf.op_type = op_type;
+	op.bf.hash_block_bitmap = 3;
+	op.bf.op_mode = op_mode;
+	op.bf.entry_index = *index;
+	op.bf.op_host_en = 1;
+
+	rv = hppe_in_flow_tbl_op_set(dev_id, &op);
+	if (SW_OK != rv)
+		return rv;
+	rv = hppe_in_flow_tbl_op_rslt_get(dev_id, &result);
+	if (SW_OK != rv)
+		return rv;
+	while (!result.bf.valid_cnt && --i) {
+		hppe_in_flow_tbl_op_rslt_get(dev_id, &result);
+	}
+	if (i == 0)
+		return SW_BUSY;
+	if (result.bf.op_rslt == 0) {
+		*index = result.bf.flow_entry_index;
+		return SW_OK;
+	}
+	else
+		return SW_FAIL;
+}
+
+sw_error_t
+hppe_flow_entry_host_op_ipv4_5tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_tbl_u *entry)
+{
+	hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+	hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+	hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+	hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+	hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+	return hppe_flow_host_op_both_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_entry_host_op_ipv4_3tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_3tuple_tbl_u *entry)
+{
+	hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+	hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+	hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+	hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+	hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+	return hppe_flow_host_op_both_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_entry_host_op_ipv6_5tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry)
+{
+	hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+	hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+	hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+	hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+	hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+	hppe_in_flow_tbl_op_data5_set(dev_id, (union in_flow_tbl_op_data5_u *)(&entry->val[5]));
+	hppe_in_flow_tbl_op_data6_set(dev_id, (union in_flow_tbl_op_data6_u *)(&entry->val[6]));
+	hppe_in_flow_tbl_op_data7_set(dev_id, (union in_flow_tbl_op_data7_u *)(&entry->val[7]));
+	hppe_in_flow_tbl_op_data8_set(dev_id, (union in_flow_tbl_op_data8_u *)(&entry->val[8]));
+	return hppe_flow_host_op_both_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_entry_host_op_ipv6_3tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry)
+{
+	hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+	hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+	hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+	hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+	hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+	hppe_in_flow_tbl_op_data5_set(dev_id, (union in_flow_tbl_op_data5_u *)(&entry->val[5]));
+	hppe_in_flow_tbl_op_data6_set(dev_id, (union in_flow_tbl_op_data6_u *)(&entry->val[6]));
+	hppe_in_flow_tbl_op_data7_set(dev_id, (union in_flow_tbl_op_data7_u *)(&entry->val[7]));
+	hppe_in_flow_tbl_op_data8_set(dev_id, (union in_flow_tbl_op_data8_u *)(&entry->val[8]));
+	return hppe_flow_host_op_both_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_entry_host_op_ipv4_5tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+	}
+	return hppe_flow_host_op_both_common(dev_id, 1, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_entry_host_op_ipv4_3tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_3tuple_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+	}
+	return hppe_flow_host_op_both_common(dev_id, 1, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_entry_host_op_ipv6_5tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+		hppe_in_flow_tbl_op_data5_set(dev_id, (union in_flow_tbl_op_data5_u *)(&entry->val[5]));
+		hppe_in_flow_tbl_op_data6_set(dev_id, (union in_flow_tbl_op_data6_u *)(&entry->val[6]));
+		hppe_in_flow_tbl_op_data7_set(dev_id, (union in_flow_tbl_op_data7_u *)(&entry->val[7]));
+		hppe_in_flow_tbl_op_data8_set(dev_id, (union in_flow_tbl_op_data8_u *)(&entry->val[8]));
+	}
+	return hppe_flow_host_op_both_common(dev_id, 1, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_entry_host_op_ipv6_3tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+		hppe_in_flow_tbl_op_data5_set(dev_id, (union in_flow_tbl_op_data5_u *)(&entry->val[5]));
+		hppe_in_flow_tbl_op_data6_set(dev_id, (union in_flow_tbl_op_data6_u *)(&entry->val[6]));
+		hppe_in_flow_tbl_op_data7_set(dev_id, (union in_flow_tbl_op_data7_u *)(&entry->val[7]));
+		hppe_in_flow_tbl_op_data8_set(dev_id, (union in_flow_tbl_op_data8_u *)(&entry->val[8]));
+	}
+	return hppe_flow_host_op_both_common(dev_id, 1, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_entry_host_op_ipv4_5tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_rd_op_data0_set(dev_id, (union in_flow_tbl_rd_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_rd_op_data1_set(dev_id, (union in_flow_tbl_rd_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_rd_op_data2_set(dev_id, (union in_flow_tbl_rd_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_rd_op_data3_set(dev_id, (union in_flow_tbl_rd_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_rd_op_data4_set(dev_id, (union in_flow_tbl_rd_op_data4_u *)(&entry->val[4]));
+	}
+	return hppe_flow_host_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 5);
+}
+
+sw_error_t
+hppe_flow_entry_host_op_ipv4_3tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_3tuple_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_rd_op_data0_set(dev_id, (union in_flow_tbl_rd_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_rd_op_data1_set(dev_id, (union in_flow_tbl_rd_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_rd_op_data2_set(dev_id, (union in_flow_tbl_rd_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_rd_op_data3_set(dev_id, (union in_flow_tbl_rd_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_rd_op_data4_set(dev_id, (union in_flow_tbl_rd_op_data4_u *)(&entry->val[4]));
+	}
+	return hppe_flow_host_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 5);
+}
+
+sw_error_t
+hppe_flow_entry_host_op_ipv6_5tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_rd_op_data0_set(dev_id, (union in_flow_tbl_rd_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_rd_op_data1_set(dev_id, (union in_flow_tbl_rd_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_rd_op_data2_set(dev_id, (union in_flow_tbl_rd_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_rd_op_data3_set(dev_id, (union in_flow_tbl_rd_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_rd_op_data4_set(dev_id, (union in_flow_tbl_rd_op_data4_u *)(&entry->val[4]));
+		hppe_in_flow_tbl_rd_op_data5_set(dev_id, (union in_flow_tbl_rd_op_data5_u *)(&entry->val[5]));
+		hppe_in_flow_tbl_rd_op_data6_set(dev_id, (union in_flow_tbl_rd_op_data6_u *)(&entry->val[6]));
+		hppe_in_flow_tbl_rd_op_data7_set(dev_id, (union in_flow_tbl_rd_op_data7_u *)(&entry->val[7]));
+		hppe_in_flow_tbl_rd_op_data8_set(dev_id, (union in_flow_tbl_rd_op_data8_u *)(&entry->val[8]));
+	}
+	return hppe_flow_host_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 9);
+}
+
+sw_error_t
+hppe_flow_entry_host_op_ipv6_3tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_rd_op_data0_set(dev_id, (union in_flow_tbl_rd_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_rd_op_data1_set(dev_id, (union in_flow_tbl_rd_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_rd_op_data2_set(dev_id, (union in_flow_tbl_rd_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_rd_op_data3_set(dev_id, (union in_flow_tbl_rd_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_rd_op_data4_set(dev_id, (union in_flow_tbl_rd_op_data4_u *)(&entry->val[4]));
+		hppe_in_flow_tbl_rd_op_data5_set(dev_id, (union in_flow_tbl_rd_op_data5_u *)(&entry->val[5]));
+		hppe_in_flow_tbl_rd_op_data6_set(dev_id, (union in_flow_tbl_rd_op_data6_u *)(&entry->val[6]));
+		hppe_in_flow_tbl_rd_op_data7_set(dev_id, (union in_flow_tbl_rd_op_data7_u *)(&entry->val[7]));
+		hppe_in_flow_tbl_rd_op_data8_set(dev_id, (union in_flow_tbl_rd_op_data8_u *)(&entry->val[8]));
+	}
+	return hppe_flow_host_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 9);
+}
+
+sw_error_t
+hppe_flow_host_data_op_common(
+		a_uint32_t dev_id,
+		a_uint32_t op_type,
+		a_uint32_t op_mode,
+		a_uint32_t *index)
+{
+	union in_flow_host_tbl_op_u op;
+	sw_error_t rv;
+
+	op.bf.hash_block_bitmap = 3;
+	op.bf.host_entry_index = *index;
+
+	rv = hppe_in_flow_host_tbl_op_set(dev_id, &op);
+	if (SW_OK != rv)
+		return rv;
+
+	return SW_OK;
+}
+
+sw_error_t
+hppe_flow_host_data_rd_op_common(
+		a_uint32_t dev_id,
+		a_uint32_t op_type,
+		a_uint32_t op_mode,
+		a_uint32_t *index)
+{
+	union in_flow_host_tbl_rd_op_u op;
+	sw_error_t rv;
+
+	op.bf.hash_block_bitmap = 3;
+	op.bf.host_entry_index = *index;
+
+	rv = hppe_in_flow_host_tbl_rd_op_set(dev_id, &op);
+	if (SW_OK != rv)
+		return rv;
+
+	return SW_OK;
+}
+sw_error_t
+hppe_flow_host_ipv4_data_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_tbl_u *entry)
+{
+	hppe_flow_host_tbl_op_data0_set(dev_id, (union flow_host_tbl_op_data0_u *)(&entry->val[0]));
+	hppe_flow_host_tbl_op_data1_set(dev_id, (union flow_host_tbl_op_data1_u *)(&entry->val[1]));
+	hppe_flow_host_tbl_op_data2_set(dev_id, (union flow_host_tbl_op_data2_u *)(&entry->val[2]));
+	return hppe_flow_host_data_op_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_host_ipv6_data_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_tbl_u *entry)
+{
+	hppe_flow_host_tbl_op_data0_set(dev_id, (union flow_host_tbl_op_data0_u *)(&entry->val[0]));
+	hppe_flow_host_tbl_op_data1_set(dev_id, (union flow_host_tbl_op_data1_u *)(&entry->val[1]));
+	hppe_flow_host_tbl_op_data2_set(dev_id, (union flow_host_tbl_op_data2_u *)(&entry->val[2]));
+	hppe_flow_host_tbl_op_data3_set(dev_id, (union flow_host_tbl_op_data3_u *)(&entry->val[3]));
+	hppe_flow_host_tbl_op_data4_set(dev_id, (union flow_host_tbl_op_data4_u *)(&entry->val[4]));
+	return hppe_flow_host_data_op_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_host_ipv4_data_rd_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_tbl_u *entry)
+{
+	hppe_flow_host_tbl_rd_op_data0_set(dev_id, (union flow_host_tbl_rd_op_data0_u *)(&entry->val[0]));
+	hppe_flow_host_tbl_rd_op_data1_set(dev_id, (union flow_host_tbl_rd_op_data1_u *)(&entry->val[1]));
+	hppe_flow_host_tbl_rd_op_data2_set(dev_id, (union flow_host_tbl_rd_op_data2_u*)(&entry->val[2]));
+	return hppe_flow_host_data_rd_op_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_host_ipv6_data_rd_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_tbl_u *entry)
+{
+	hppe_flow_host_tbl_rd_op_data0_set(dev_id, (union flow_host_tbl_rd_op_data0_u *)(&entry->val[0]));
+	hppe_flow_host_tbl_rd_op_data1_set(dev_id, (union flow_host_tbl_rd_op_data1_u *)(&entry->val[1]));
+	hppe_flow_host_tbl_rd_op_data2_set(dev_id, (union flow_host_tbl_rd_op_data2_u *)(&entry->val[2]));
+	hppe_flow_host_tbl_rd_op_data3_set(dev_id, (union flow_host_tbl_rd_op_data3_u *)(&entry->val[3]));
+	hppe_flow_host_tbl_rd_op_data4_set(dev_id, (union flow_host_tbl_rd_op_data4_u *)(&entry->val[4]));
+	return hppe_flow_host_data_rd_op_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_host_ipv4_data_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_tbl_u *entry)
+{
+	if (1){//op_mode == 0) {
+		hppe_host_tbl_rd_op_data0_get(dev_id, (union host_tbl_rd_op_data0_u *)(&entry->val[0]));
+		hppe_host_tbl_rd_op_data1_get(dev_id, (union host_tbl_rd_op_data1_u *)(&entry->val[1]));
+		hppe_host_tbl_rd_op_data2_set(dev_id, (union host_tbl_rd_op_data2_u *)(&entry->val[2]));
+	}
+	return SW_OK;
+}
+
+sw_error_t
+hppe_flow_host_ipv6_data_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_tbl_u *entry)
+{
+	if (1){//op_mode == 0) {
+		hppe_host_tbl_rd_op_data0_get(dev_id, (union host_tbl_rd_op_data0_u *)(&entry->val[0]));
+		hppe_host_tbl_rd_op_data1_get(dev_id, (union host_tbl_rd_op_data1_u *)(&entry->val[1]));
+		hppe_host_tbl_rd_op_data2_get(dev_id, (union host_tbl_rd_op_data2_u *)(&entry->val[2]));
+		hppe_host_tbl_rd_op_data3_get(dev_id, (union host_tbl_rd_op_data3_u *)(&entry->val[3]));
+		hppe_host_tbl_rd_op_data4_get(dev_id, (union host_tbl_rd_op_data4_u *)(&entry->val[4]));
+	}
+	return SW_OK;
+}
+
+sw_error_t
+hppe_flow_host_ipv4_data_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0]));
+		hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1]));
+		hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2]));
+	}
+	return hppe_flow_host_data_op_common(dev_id, 1, op_mode, index);
+
+}
+
+sw_error_t
+hppe_flow_host_ipv6_data_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0]));
+		hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1]));
+		hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2]));
+		hppe_host_tbl_op_data3_set(dev_id, (union host_tbl_op_data3_u *)(&entry->val[3]));
+		hppe_host_tbl_op_data4_set(dev_id, (union host_tbl_op_data4_u *)(&entry->val[4]));
+	}
+	return hppe_flow_host_data_op_common(dev_id, 1, op_mode, index);
+}
+
+
+sw_error_t
+hppe_flow_ipv4_5tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_tbl_u *entry)
+{
+	hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+	hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+	hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+	hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+	hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+	return hppe_flow_op_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_ipv4_3tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_3tuple_tbl_u *entry)
+{
+	hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+	hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+	hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+	hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+	hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+	return hppe_flow_op_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_ipv6_5tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry)
+{
+	hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+	hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+	hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+	hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+	hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+	hppe_in_flow_tbl_op_data5_set(dev_id, (union in_flow_tbl_op_data5_u *)(&entry->val[5]));
+	hppe_in_flow_tbl_op_data6_set(dev_id, (union in_flow_tbl_op_data6_u *)(&entry->val[6]));
+	hppe_in_flow_tbl_op_data7_set(dev_id, (union in_flow_tbl_op_data7_u *)(&entry->val[7]));
+	hppe_in_flow_tbl_op_data8_set(dev_id, (union in_flow_tbl_op_data8_u *)(&entry->val[8]));
+	return hppe_flow_op_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_ipv6_3tuple_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry)
+{
+	hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+	hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+	hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+	hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+	hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+	hppe_in_flow_tbl_op_data5_set(dev_id, (union in_flow_tbl_op_data5_u *)(&entry->val[5]));
+	hppe_in_flow_tbl_op_data6_set(dev_id, (union in_flow_tbl_op_data6_u *)(&entry->val[6]));
+	hppe_in_flow_tbl_op_data7_set(dev_id, (union in_flow_tbl_op_data7_u *)(&entry->val[7]));
+	hppe_in_flow_tbl_op_data8_set(dev_id, (union in_flow_tbl_op_data8_u *)(&entry->val[8]));
+	return hppe_flow_op_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_ipv4_5tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_op_data0_set(dev_id,
+				(union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_op_data1_set(dev_id,
+				(union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_op_data2_set(dev_id,
+				(union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_op_data3_set(dev_id,
+				(union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_op_data4_set(dev_id,
+				(union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+	}
+	return hppe_flow_op_common(dev_id, 1, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_ipv4_3tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_3tuple_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_op_data0_set(dev_id,
+				(union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_op_data1_set(dev_id,
+				(union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_op_data2_set(dev_id,
+				(union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_op_data3_set(dev_id,
+				(union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_op_data4_set(dev_id,
+				(union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+	}
+	return hppe_flow_op_common(dev_id, 1, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_ipv6_5tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_op_data0_set(dev_id,
+				(union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_op_data1_set(dev_id,
+				(union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_op_data2_set(dev_id,
+				(union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_op_data3_set(dev_id,
+				(union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_op_data4_set(dev_id,
+				(union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+		hppe_in_flow_tbl_op_data5_set(dev_id,
+				(union in_flow_tbl_op_data5_u *)(&entry->val[5]));
+		hppe_in_flow_tbl_op_data6_set(dev_id,
+				(union in_flow_tbl_op_data6_u *)(&entry->val[6]));
+		hppe_in_flow_tbl_op_data7_set(dev_id,
+				(union in_flow_tbl_op_data7_u *)(&entry->val[7]));
+		hppe_in_flow_tbl_op_data8_set(dev_id,
+				(union in_flow_tbl_op_data8_u *)(&entry->val[8]));
+	}
+	return hppe_flow_op_common(dev_id, 1, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_ipv6_3tuple_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_op_data0_set(dev_id,
+				(union in_flow_tbl_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_op_data1_set(dev_id,
+				(union in_flow_tbl_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_op_data2_set(dev_id,
+				(union in_flow_tbl_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_op_data3_set(dev_id,
+				(union in_flow_tbl_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_op_data4_set(dev_id,
+				(union in_flow_tbl_op_data4_u *)(&entry->val[4]));
+		hppe_in_flow_tbl_op_data5_set(dev_id,
+				(union in_flow_tbl_op_data5_u *)(&entry->val[5]));
+		hppe_in_flow_tbl_op_data6_set(dev_id,
+				(union in_flow_tbl_op_data6_u *)(&entry->val[6]));
+		hppe_in_flow_tbl_op_data7_set(dev_id,
+				(union in_flow_tbl_op_data7_u *)(&entry->val[7]));
+		hppe_in_flow_tbl_op_data8_set(dev_id,
+				(union in_flow_tbl_op_data8_u *)(&entry->val[8]));
+	}
+	return hppe_flow_op_common(dev_id, 1, op_mode, index);
+}
+
+sw_error_t
+hppe_flow_ipv4_5tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_rd_op_data0_set(dev_id,
+				(union in_flow_tbl_rd_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_rd_op_data1_set(dev_id,
+				(union in_flow_tbl_rd_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_rd_op_data2_set(dev_id,
+				(union in_flow_tbl_rd_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_rd_op_data3_set(dev_id,
+				(union in_flow_tbl_rd_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_rd_op_data4_set(dev_id,
+				(union in_flow_tbl_rd_op_data4_u *)(&entry->val[4]));
+	}
+	return hppe_flow_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 5);
+}
+
+sw_error_t
+hppe_flow_ipv4_3tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_3tuple_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_rd_op_data0_set(dev_id,
+				(union in_flow_tbl_rd_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_rd_op_data1_set(dev_id,
+				(union in_flow_tbl_rd_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_rd_op_data2_set(dev_id,
+				(union in_flow_tbl_rd_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_rd_op_data3_set(dev_id,
+				(union in_flow_tbl_rd_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_rd_op_data4_set(dev_id,
+				(union in_flow_tbl_rd_op_data4_u *)(&entry->val[4]));
+	}
+	return hppe_flow_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 5);
+}
+
+sw_error_t
+hppe_flow_ipv6_5tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_rd_op_data0_set(dev_id,
+				(union in_flow_tbl_rd_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_rd_op_data1_set(dev_id,
+				(union in_flow_tbl_rd_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_rd_op_data2_set(dev_id,
+				(union in_flow_tbl_rd_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_rd_op_data3_set(dev_id,
+				(union in_flow_tbl_rd_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_rd_op_data4_set(dev_id,
+				(union in_flow_tbl_rd_op_data4_u *)(&entry->val[4]));
+		hppe_in_flow_tbl_rd_op_data5_set(dev_id,
+				(union in_flow_tbl_rd_op_data5_u *)(&entry->val[5]));
+		hppe_in_flow_tbl_rd_op_data6_set(dev_id,
+				(union in_flow_tbl_rd_op_data6_u *)(&entry->val[6]));
+		hppe_in_flow_tbl_rd_op_data7_set(dev_id,
+				(union in_flow_tbl_rd_op_data7_u *)(&entry->val[7]));
+		hppe_in_flow_tbl_rd_op_data8_set(dev_id,
+				(union in_flow_tbl_rd_op_data8_u *)(&entry->val[8]));
+	}
+	return hppe_flow_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 9);
+}
+
+sw_error_t
+hppe_flow_ipv6_3tuple_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_in_flow_tbl_rd_op_data0_set(dev_id,
+				(union in_flow_tbl_rd_op_data0_u *)(&entry->val[0]));
+		hppe_in_flow_tbl_rd_op_data1_set(dev_id,
+				(union in_flow_tbl_rd_op_data1_u *)(&entry->val[1]));
+		hppe_in_flow_tbl_rd_op_data2_set(dev_id,
+				(union in_flow_tbl_rd_op_data2_u *)(&entry->val[2]));
+		hppe_in_flow_tbl_rd_op_data3_set(dev_id,
+				(union in_flow_tbl_rd_op_data3_u *)(&entry->val[3]));
+		hppe_in_flow_tbl_rd_op_data4_set(dev_id,
+				(union in_flow_tbl_rd_op_data4_u *)(&entry->val[4]));
+		hppe_in_flow_tbl_rd_op_data5_set(dev_id,
+				(union in_flow_tbl_rd_op_data5_u *)(&entry->val[5]));
+		hppe_in_flow_tbl_rd_op_data6_set(dev_id,
+				(union in_flow_tbl_rd_op_data6_u *)(&entry->val[6]));
+		hppe_in_flow_tbl_rd_op_data7_set(dev_id,
+				(union in_flow_tbl_rd_op_data7_u *)(&entry->val[7]));
+		hppe_in_flow_tbl_rd_op_data8_set(dev_id,
+				(union in_flow_tbl_rd_op_data8_u *)(&entry->val[8]));
+	}
+	return hppe_flow_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 9);
+}
+#endif
diff --git a/qca-ssdk/src/hsl/hppe/hppe_global.c b/qca-ssdk/src/hsl/hppe/hppe_global.c
new file mode 100755
index 0000000..85fbaaf
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_global.c
@@ -0,0 +1,3117 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_global_reg.h"
+#include "hppe_global.h"
+
+sw_error_t
+hppe_switch_id_get(
+		a_uint32_t dev_id,
+		union switch_id_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + SWITCH_ID_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_switch_id_set(
+		a_uint32_t dev_id,
+		union switch_id_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + SWITCH_ID_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_rgmii_ctrl_get(
+		a_uint32_t dev_id,
+		union rgmii_ctrl_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + RGMII_CTRL_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_rgmii_ctrl_set(
+		a_uint32_t dev_id,
+		union rgmii_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + RGMII_CTRL_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_clk_gating_ctrl_get(
+		a_uint32_t dev_id,
+		union clk_gating_ctrl_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + CLK_GATING_CTRL_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_clk_gating_ctrl_set(
+		a_uint32_t dev_id,
+		union clk_gating_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + CLK_GATING_CTRL_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_port_mux_ctrl_get(
+		a_uint32_t dev_id,
+		union port_mux_ctrl_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT_MUX_CTRL_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_mux_ctrl_set(
+		a_uint32_t dev_id,
+		union port_mux_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT_MUX_CTRL_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+cppe_port_mux_ctrl_get(
+		a_uint32_t dev_id,
+		union cppe_port_mux_ctrl_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT_MUX_CTRL_ADDRESS,
+				&value->val);
+}
+sw_error_t
+cppe_port_mux_ctrl_set(
+		a_uint32_t dev_id,
+		union cppe_port_mux_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT_MUX_CTRL_ADDRESS,
+				value->val);
+}
+sw_error_t
+hppe_module_ini_done_int_get(
+		a_uint32_t dev_id,
+		union module_ini_done_int_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + MODULE_INI_DONE_INT_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_module_ini_done_int_set(
+		a_uint32_t dev_id,
+		union module_ini_done_int_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + MODULE_INI_DONE_INT_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_module_cpu_done_int_get(
+		a_uint32_t dev_id,
+		union module_cpu_done_int_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + MODULE_CPU_DONE_INT_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_module_cpu_done_int_set(
+		a_uint32_t dev_id,
+		union module_cpu_done_int_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + MODULE_CPU_DONE_INT_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_port_link_int_get(
+		a_uint32_t dev_id,
+		union port_link_int_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT_LINK_INT_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_link_int_set(
+		a_uint32_t dev_id,
+		union port_link_int_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT_LINK_INT_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		union module_ini_done_int_mask_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + MODULE_INI_DONE_INT_MASK_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		union module_ini_done_int_mask_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + MODULE_INI_DONE_INT_MASK_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_get(
+		a_uint32_t dev_id,
+		union module_cpu_done_int_mask_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + MODULE_CPU_DONE_INT_MASK_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_set(
+		a_uint32_t dev_id,
+		union module_cpu_done_int_mask_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + MODULE_CPU_DONE_INT_MASK_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_port_link_int_mask_get(
+		a_uint32_t dev_id,
+		union port_link_int_mask_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT_LINK_INT_MASK_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_link_int_mask_set(
+		a_uint32_t dev_id,
+		union port_link_int_mask_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT_LINK_INT_MASK_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_port_phy_status_0_get(
+		a_uint32_t dev_id,
+		union port_phy_status_0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT_PHY_STATUS_0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_phy_status_0_set(
+		a_uint32_t dev_id,
+		union port_phy_status_0_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port_phy_status_1_get(
+		a_uint32_t dev_id,
+		union port_phy_status_1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT_PHY_STATUS_1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_phy_status_1_set(
+		a_uint32_t dev_id,
+		union port_phy_status_1_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port1_status_get(
+		a_uint32_t dev_id,
+		union port1_status_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT1_STATUS_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_port1_status_set(
+		a_uint32_t dev_id,
+		union port1_status_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port2_status_get(
+		a_uint32_t dev_id,
+		union port2_status_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT2_STATUS_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_port2_status_set(
+		a_uint32_t dev_id,
+		union port2_status_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port3_status_get(
+		a_uint32_t dev_id,
+		union port3_status_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT3_STATUS_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_port3_status_set(
+		a_uint32_t dev_id,
+		union port3_status_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port4_status_get(
+		a_uint32_t dev_id,
+		union port4_status_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT4_STATUS_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_port4_status_set(
+		a_uint32_t dev_id,
+		union port4_status_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port5_status_get(
+		a_uint32_t dev_id,
+		union port5_status_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT5_STATUS_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_port5_status_set(
+		a_uint32_t dev_id,
+		union port5_status_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port6_status_get(
+		a_uint32_t dev_id,
+		union port6_status_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + PORT6_STATUS_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_port6_status_set(
+		a_uint32_t dev_id,
+		union port6_status_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_reserved_regs_0_get(
+		a_uint32_t dev_id,
+		union reserved_regs_0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_reserved_regs_0_set(
+		a_uint32_t dev_id,
+		union reserved_regs_0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_0_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_reserved_regs_1_get(
+		a_uint32_t dev_id,
+		union reserved_regs_1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_reserved_regs_1_set(
+		a_uint32_t dev_id,
+		union reserved_regs_1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_1_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_reserved_regs_2_get(
+		a_uint32_t dev_id,
+		union reserved_regs_2_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_2_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_reserved_regs_2_set(
+		a_uint32_t dev_id,
+		union reserved_regs_2_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_2_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_reserved_regs_3_get(
+		a_uint32_t dev_id,
+		union reserved_regs_3_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_3_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_reserved_regs_3_set(
+		a_uint32_t dev_id,
+		union reserved_regs_3_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_3_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_dbg_data_sel_get(
+		a_uint32_t dev_id,
+		union dbg_data_sel_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + DBG_DATA_SEL_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_dbg_data_sel_set(
+		a_uint32_t dev_id,
+		union dbg_data_sel_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_GLOBAL_BASE_ADDR + DBG_DATA_SEL_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_switch_id_dev_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union switch_id_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_switch_id_get(dev_id, &reg_val);
+	*value = reg_val.bf.dev_id;
+	return ret;
+}
+
+sw_error_t
+hppe_switch_id_dev_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union switch_id_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_switch_id_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dev_id = value;
+	ret = hppe_switch_id_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_switch_id_rev_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union switch_id_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_switch_id_get(dev_id, &reg_val);
+	*value = reg_val.bf.rev_id;
+	return ret;
+}
+
+sw_error_t
+hppe_switch_id_rev_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union switch_id_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_switch_id_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rev_id = value;
+	ret = hppe_switch_id_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rgmii_ctrl_rgmii_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union rgmii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rgmii_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.rgmii_ctrl;
+	return ret;
+}
+
+sw_error_t
+hppe_rgmii_ctrl_rgmii_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union rgmii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rgmii_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rgmii_ctrl = value;
+	ret = hppe_rgmii_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_clk_gating_ctrl_clk_gating_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union clk_gating_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_clk_gating_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.clk_gating_ctrl;
+	return ret;
+}
+
+sw_error_t
+hppe_clk_gating_ctrl_clk_gating_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union clk_gating_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_clk_gating_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.clk_gating_ctrl = value;
+	ret = hppe_clk_gating_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_mux_ctrl_port6_pcs_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_mux_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_mux_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.port6_pcs_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_port_mux_ctrl_port6_pcs_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_mux_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_mux_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port6_pcs_sel = value;
+	ret = hppe_port_mux_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_mux_ctrl_port5_gmac_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_mux_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_mux_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.port5_gmac_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_port_mux_ctrl_port5_gmac_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_mux_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_mux_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port5_gmac_sel = value;
+	ret = hppe_port_mux_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_mux_ctrl_port5_pcs_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_mux_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_mux_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.port5_pcs_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_port_mux_ctrl_port5_pcs_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_mux_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_mux_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port5_pcs_sel = value;
+	ret = hppe_port_mux_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_mux_ctrl_port4_pcs_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_mux_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_mux_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.port4_pcs_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_port_mux_ctrl_port4_pcs_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_mux_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_mux_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port4_pcs_sel = value;
+	ret = hppe_port_mux_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_mux_ctrl_port6_gmac_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_mux_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_mux_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.port6_gmac_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_port_mux_ctrl_port6_gmac_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_mux_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_mux_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port6_gmac_sel = value;
+	ret = hppe_port_mux_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_iv_ini_done_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.iv_ini_done_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_iv_ini_done_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.iv_ini_done_int = value;
+	ret = hppe_module_ini_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_qm_ini_done_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.qm_ini_done_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_qm_ini_done_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.qm_ini_done_int = value;
+	ret = hppe_module_ini_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_l3_ini_done_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_ini_done_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_l3_ini_done_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_ini_done_int = value;
+	ret = hppe_module_ini_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_bm_ini_done_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.bm_ini_done_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_bm_ini_done_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.bm_ini_done_int = value;
+	ret = hppe_module_ini_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_ptx_ini_done_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.ptx_ini_done_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_ptx_ini_done_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptx_ini_done_int = value;
+	ret = hppe_module_ini_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_tm_ini_done_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.tm_ini_done_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_tm_ini_done_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tm_ini_done_int = value;
+	ret = hppe_module_ini_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_l2_ini_done_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.l2_ini_done_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_l2_ini_done_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_ini_done_int = value;
+	ret = hppe_module_ini_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_acl_ini_done_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.acl_ini_done_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_acl_ini_done_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.acl_ini_done_int = value;
+	ret = hppe_module_ini_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_ing_rate_ini_done_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.ing_rate_ini_done_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_ing_rate_ini_done_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ing_rate_ini_done_int = value;
+	ret = hppe_module_ini_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_wr_cmd_overflow_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_flow_wr_cmd_overflow_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_wr_cmd_overflow_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_flow_wr_cmd_overflow_int = value;
+	ret = hppe_module_cpu_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_rd_cmd_overflow_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.l2_fdb_rd_cmd_overflow_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_rd_cmd_overflow_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_fdb_rd_cmd_overflow_int = value;
+	ret = hppe_module_cpu_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_qm_cpu_op_done_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.qm_cpu_op_done_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_qm_cpu_op_done_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.qm_cpu_op_done_int = value;
+	ret = hppe_module_cpu_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_rd_cmd_overflow_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_flow_rd_cmd_overflow_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_rd_cmd_overflow_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_flow_rd_cmd_overflow_int = value;
+	ret = hppe_module_cpu_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_wr_result_vld_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.l2_fdb_wr_result_vld_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_wr_result_vld_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_fdb_wr_result_vld_int = value;
+	ret = hppe_module_cpu_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_rd_result_vld_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.l2_fdb_rd_result_vld_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_rd_result_vld_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_fdb_rd_result_vld_int = value;
+	ret = hppe_module_cpu_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_wr_cmd_overflow_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.l2_fdb_wr_cmd_overflow_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l2_fdb_wr_cmd_overflow_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_fdb_wr_cmd_overflow_int = value;
+	ret = hppe_module_cpu_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_rd_result_vld_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_flow_rd_result_vld_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_rd_result_vld_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_flow_rd_result_vld_int = value;
+	ret = hppe_module_cpu_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_wr_cmd_overflow_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_host_wr_cmd_overflow_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_wr_cmd_overflow_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_host_wr_cmd_overflow_int = value;
+	ret = hppe_module_cpu_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_rd_cmd_overflow_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_host_rd_cmd_overflow_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_rd_cmd_overflow_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_host_rd_cmd_overflow_int = value;
+	ret = hppe_module_cpu_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_rd_result_vld_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_host_rd_result_vld_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_rd_result_vld_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_host_rd_result_vld_int = value;
+	ret = hppe_module_cpu_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_wr_result_vld_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_host_wr_result_vld_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_host_wr_result_vld_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_host_wr_result_vld_int = value;
+	ret = hppe_module_cpu_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_wr_result_vld_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_flow_wr_result_vld_int;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_l3_flow_wr_result_vld_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_flow_wr_result_vld_int = value;
+	ret = hppe_module_cpu_done_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_port6_link_chg_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.port6_link_chg_int;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_port6_link_chg_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port6_link_chg_int = value;
+	ret = hppe_port_link_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_xgmac0_an_done_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.xgmac0_an_done_int;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_xgmac0_an_done_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xgmac0_an_done_int = value;
+	ret = hppe_port_link_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_port5_1_link_chg_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.port5_1_link_chg_int;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_port5_1_link_chg_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port5_1_link_chg_int = value;
+	ret = hppe_port_link_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_port5_0_link_chg_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.port5_0_link_chg_int;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_port5_0_link_chg_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port5_0_link_chg_int = value;
+	ret = hppe_port_link_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_port4_link_chg_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.port4_link_chg_int;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_port4_link_chg_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port4_link_chg_int = value;
+	ret = hppe_port_link_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_port3_link_chg_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.port3_link_chg_int;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_port3_link_chg_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port3_link_chg_int = value;
+	ret = hppe_port_link_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_port2_link_chg_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.port2_link_chg_int;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_port2_link_chg_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port2_link_chg_int = value;
+	ret = hppe_port_link_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_xgmac1_an_done_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.xgmac1_an_done_int;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_xgmac1_an_done_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xgmac1_an_done_int = value;
+	ret = hppe_port_link_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_port1_link_chg_int_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	*value = reg_val.bf.port1_link_chg_int;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_port1_link_chg_int_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port1_link_chg_int = value;
+	ret = hppe_port_link_int_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_tm_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.tm_ini_done_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_tm_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tm_ini_done_int_mask = value;
+	ret = hppe_module_ini_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_bm_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.bm_ini_done_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_bm_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.bm_ini_done_int_mask = value;
+	ret = hppe_module_ini_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_iv_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.iv_ini_done_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_iv_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.iv_ini_done_int_mask = value;
+	ret = hppe_module_ini_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_acl_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.acl_ini_done_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_acl_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.acl_ini_done_int_mask = value;
+	ret = hppe_module_ini_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_qm_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.qm_ini_done_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_qm_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.qm_ini_done_int_mask = value;
+	ret = hppe_module_ini_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_l2_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.l2_ini_done_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_l2_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_ini_done_int_mask = value;
+	ret = hppe_module_ini_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_ptx_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.ptx_ini_done_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_ptx_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptx_ini_done_int_mask = value;
+	ret = hppe_module_ini_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_ing_rate_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.ing_rate_ini_done_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_ing_rate_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ing_rate_ini_done_int_mask = value;
+	ret = hppe_module_ini_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_l3_ini_done_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_ini_done_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_ini_done_int_mask_l3_ini_done_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_ini_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_ini_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_ini_done_int_mask = value;
+	ret = hppe_module_ini_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_wr_result_vld_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_host_wr_result_vld_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_wr_result_vld_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_host_wr_result_vld_int_mask = value;
+	ret = hppe_module_cpu_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_wr_result_vld_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_flow_wr_result_vld_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_wr_result_vld_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_flow_wr_result_vld_int_mask = value;
+	ret = hppe_module_cpu_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_rd_cmd_overflow_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_host_rd_cmd_overflow_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_rd_cmd_overflow_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_host_rd_cmd_overflow_int_mask = value;
+	ret = hppe_module_cpu_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_wr_cmd_overflow_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_flow_wr_cmd_overflow_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_wr_cmd_overflow_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_flow_wr_cmd_overflow_int_mask = value;
+	ret = hppe_module_cpu_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_rd_result_vld_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_host_rd_result_vld_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_rd_result_vld_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_host_rd_result_vld_int_mask = value;
+	ret = hppe_module_cpu_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_rd_cmd_overflow_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.l2_fdb_rd_cmd_overflow_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_rd_cmd_overflow_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_fdb_rd_cmd_overflow_int_mask = value;
+	ret = hppe_module_cpu_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_wr_cmd_overflow_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.l2_fdb_wr_cmd_overflow_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_wr_cmd_overflow_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_fdb_wr_cmd_overflow_int_mask = value;
+	ret = hppe_module_cpu_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_wr_cmd_overflow_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_host_wr_cmd_overflow_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_host_wr_cmd_overflow_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_host_wr_cmd_overflow_int_mask = value;
+	ret = hppe_module_cpu_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_rd_result_vld_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.l2_fdb_rd_result_vld_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_rd_result_vld_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_fdb_rd_result_vld_int_mask = value;
+	ret = hppe_module_cpu_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_wr_result_vld_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.l2_fdb_wr_result_vld_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l2_fdb_wr_result_vld_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_fdb_wr_result_vld_int_mask = value;
+	ret = hppe_module_cpu_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_qm_cpu_op_done_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.qm_cpu_op_done_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_qm_cpu_op_done_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.qm_cpu_op_done_int_mask = value;
+	ret = hppe_module_cpu_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_rd_result_vld_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_flow_rd_result_vld_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_rd_result_vld_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_flow_rd_result_vld_int_mask = value;
+	ret = hppe_module_cpu_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_rd_cmd_overflow_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.l3_flow_rd_cmd_overflow_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_module_cpu_done_int_mask_l3_flow_rd_cmd_overflow_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union module_cpu_done_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_module_cpu_done_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_flow_rd_cmd_overflow_int_mask = value;
+	ret = hppe_module_cpu_done_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_xgmac0_an_done_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.xgmac0_an_done_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_xgmac0_an_done_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xgmac0_an_done_int_mask = value;
+	ret = hppe_port_link_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_port2_link_chg_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.port2_link_chg_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_port2_link_chg_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port2_link_chg_int_mask = value;
+	ret = hppe_port_link_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_port4_link_chg_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.port4_link_chg_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_port4_link_chg_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port4_link_chg_int_mask = value;
+	ret = hppe_port_link_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_port3_link_chg_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.port3_link_chg_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_port3_link_chg_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port3_link_chg_int_mask = value;
+	ret = hppe_port_link_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_port5_1_link_chg_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.port5_1_link_chg_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_port5_1_link_chg_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port5_1_link_chg_int_mask = value;
+	ret = hppe_port_link_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_xgmac1_an_done_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.xgmac1_an_done_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_xgmac1_an_done_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xgmac1_an_done_int_mask = value;
+	ret = hppe_port_link_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_port1_link_chg_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.port1_link_chg_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_port1_link_chg_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port1_link_chg_int_mask = value;
+	ret = hppe_port_link_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_port5_0_link_chg_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.port5_0_link_chg_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_port5_0_link_chg_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port5_0_link_chg_int_mask = value;
+	ret = hppe_port_link_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_port6_link_chg_int_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	*value = reg_val.bf.port6_link_chg_int_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_port_link_int_mask_port6_link_chg_int_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union port_link_int_mask_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_link_int_mask_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port6_link_chg_int_mask = value;
+	ret = hppe_port_link_int_mask_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_phy_status_0_port3_phy_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_phy_status_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_phy_status_0_get(dev_id, &reg_val);
+	*value = reg_val.bf.port3_phy_status;
+	return ret;
+}
+
+sw_error_t
+hppe_port_phy_status_0_port3_phy_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port_phy_status_0_port4_phy_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_phy_status_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_phy_status_0_get(dev_id, &reg_val);
+	*value = reg_val.bf.port4_phy_status;
+	return ret;
+}
+
+sw_error_t
+hppe_port_phy_status_0_port4_phy_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port_phy_status_0_port2_phy_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_phy_status_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_phy_status_0_get(dev_id, &reg_val);
+	*value = reg_val.bf.port2_phy_status;
+	return ret;
+}
+
+sw_error_t
+hppe_port_phy_status_0_port2_phy_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port_phy_status_0_port1_phy_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_phy_status_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_phy_status_0_get(dev_id, &reg_val);
+	*value = reg_val.bf.port1_phy_status;
+	return ret;
+}
+
+sw_error_t
+hppe_port_phy_status_0_port1_phy_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port_phy_status_1_port6_phy_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_phy_status_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_phy_status_1_get(dev_id, &reg_val);
+	*value = reg_val.bf.port6_phy_status;
+	return ret;
+}
+
+sw_error_t
+hppe_port_phy_status_1_port6_phy_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port_phy_status_1_port5_0_phy_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_phy_status_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_phy_status_1_get(dev_id, &reg_val);
+	*value = reg_val.bf.port5_0_phy_status;
+	return ret;
+}
+
+sw_error_t
+hppe_port_phy_status_1_port5_0_phy_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port_phy_status_1_port5_1_phy_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port_phy_status_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_phy_status_1_get(dev_id, &reg_val);
+	*value = reg_val.bf.port5_1_phy_status;
+	return ret;
+}
+
+sw_error_t
+hppe_port_phy_status_1_port5_1_phy_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port1_status_port1_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port1_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port1_status_get(dev_id, &reg_val);
+	*value = reg_val.bf.port1_status;
+	return ret;
+}
+
+sw_error_t
+hppe_port1_status_port1_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port2_status_port2_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port2_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port2_status_get(dev_id, &reg_val);
+	*value = reg_val.bf.port2_status;
+	return ret;
+}
+
+sw_error_t
+hppe_port2_status_port2_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port3_status_port3_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port3_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port3_status_get(dev_id, &reg_val);
+	*value = reg_val.bf.port3_status;
+	return ret;
+}
+
+sw_error_t
+hppe_port3_status_port3_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port4_status_port4_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port4_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port4_status_get(dev_id, &reg_val);
+	*value = reg_val.bf.port4_status;
+	return ret;
+}
+
+sw_error_t
+hppe_port4_status_port4_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port5_status_port3_mac_speed_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port5_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port5_status_get(dev_id, &reg_val);
+	*value = reg_val.bf.port3_mac_speed;
+	return ret;
+}
+
+sw_error_t
+hppe_port5_status_port3_mac_speed_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port5_status_port2_mac_speed_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port5_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port5_status_get(dev_id, &reg_val);
+	*value = reg_val.bf.port2_mac_speed;
+	return ret;
+}
+
+sw_error_t
+hppe_port5_status_port2_mac_speed_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port5_status_port1_mac_speed_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port5_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port5_status_get(dev_id, &reg_val);
+	*value = reg_val.bf.port1_mac_speed;
+	return ret;
+}
+
+sw_error_t
+hppe_port5_status_port1_mac_speed_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port5_status_port5_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port5_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port5_status_get(dev_id, &reg_val);
+	*value = reg_val.bf.port5_status;
+	return ret;
+}
+
+sw_error_t
+hppe_port5_status_port5_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port5_status_port4_mac_speed_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port5_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port5_status_get(dev_id, &reg_val);
+	*value = reg_val.bf.port4_mac_speed;
+	return ret;
+}
+
+sw_error_t
+hppe_port5_status_port4_mac_speed_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_port6_status_port6_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union port6_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port6_status_get(dev_id, &reg_val);
+	*value = reg_val.bf.port6_status;
+	return ret;
+}
+
+sw_error_t
+hppe_port6_status_port6_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_reserved_regs_0_spare_regs_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union reserved_regs_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_reserved_regs_0_get(dev_id, &reg_val);
+	*value = reg_val.bf.spare_regs_0;
+	return ret;
+}
+
+sw_error_t
+hppe_reserved_regs_0_spare_regs_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union reserved_regs_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_reserved_regs_0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.spare_regs_0 = value;
+	ret = hppe_reserved_regs_0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_reserved_regs_1_spare_regs_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union reserved_regs_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_reserved_regs_1_get(dev_id, &reg_val);
+	*value = reg_val.bf.spare_regs_1;
+	return ret;
+}
+
+sw_error_t
+hppe_reserved_regs_1_spare_regs_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union reserved_regs_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_reserved_regs_1_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.spare_regs_1 = value;
+	ret = hppe_reserved_regs_1_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_reserved_regs_2_spare_regs_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union reserved_regs_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_reserved_regs_2_get(dev_id, &reg_val);
+	*value = reg_val.bf.spare_regs_2;
+	return ret;
+}
+
+sw_error_t
+hppe_reserved_regs_2_spare_regs_2_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union reserved_regs_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_reserved_regs_2_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.spare_regs_2 = value;
+	ret = hppe_reserved_regs_2_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_reserved_regs_3_spare_regs_3_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union reserved_regs_3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_reserved_regs_3_get(dev_id, &reg_val);
+	*value = reg_val.bf.spare_regs_3;
+	return ret;
+}
+
+sw_error_t
+hppe_reserved_regs_3_spare_regs_3_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union reserved_regs_3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_reserved_regs_3_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.spare_regs_3 = value;
+	ret = hppe_reserved_regs_3_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_dbg_data_sel_dbg_data_sel_desp_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union dbg_data_sel_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_dbg_data_sel_get(dev_id, &reg_val);
+	*value = reg_val.bf.dbg_data_sel_desp;
+	return ret;
+}
+
+sw_error_t
+hppe_dbg_data_sel_dbg_data_sel_desp_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union dbg_data_sel_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_dbg_data_sel_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dbg_data_sel_desp = value;
+	ret = hppe_dbg_data_sel_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_dbg_data_sel_dbg_data_sel_switch_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union dbg_data_sel_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_dbg_data_sel_get(dev_id, &reg_val);
+	*value = reg_val.bf.dbg_data_sel_switch;
+	return ret;
+}
+
+sw_error_t
+hppe_dbg_data_sel_dbg_data_sel_switch_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union dbg_data_sel_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_dbg_data_sel_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dbg_data_sel_switch = value;
+	ret = hppe_dbg_data_sel_set(dev_id, &reg_val);
+	return ret;
+}
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_init.c b/qca-ssdk/src/hsl/hppe/hppe_init.c
new file mode 100755
index 0000000..1297d9c
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_init.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup dess_init HPPE_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "sd.h"
+#include "hsl_phy.h"
+
+
+static ssdk_init_cfg * hppe_cfg[SW_MAX_NR_DEV] = { 0 };
+
+a_bool_t hppe_xgmac_port_check(fal_port_t port_id)
+{
+	return ((port_id == 5) ||( port_id == 6));
+}
+a_bool_t hppe_mac_port_valid_check(a_uint32_t dev_id, fal_port_t port_id)
+{
+	a_uint32_t bitmap = 0;
+
+	bitmap = qca_ssdk_port_bmp_get(dev_id);
+
+	return SW_IS_PBMP_MEMBER(bitmap, port_id);
+
+}
+
+static sw_error_t
+hppe_portproperty_init(a_uint32_t dev_id)
+{
+	hsl_port_prop_t p_type;
+	hsl_dev_t *pdev = NULL;
+	fal_port_t port_id;
+	a_uint32_t bitmap = 0;
+	a_uint32_t inner_pbmp = 0;
+
+	pdev = hsl_dev_ptr_get(dev_id);
+	if (pdev == NULL)
+		return SW_NOT_INITIALIZED;
+
+	bitmap = qca_ssdk_port_bmp_get(dev_id);
+	inner_pbmp = hsl_dev_inner_ports_get(dev_id);
+
+	/* for port property set, SSDK should not generate some limitations */
+	for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id++)
+	{
+		if ((port_id == pdev->cpu_port_nr) ||
+			(bitmap & (0x1 << port_id)) ||
+			(inner_pbmp & (0x1 << port_id)))
+		{
+			hsl_port_prop_portmap_set(dev_id, port_id);
+
+			for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
+			{
+				switch (p_type)
+				{
+					case HSL_PP_PHY:/*front ports*/
+						if (SW_IS_PBMP_MEMBER(bitmap, port_id))
+						{
+							SW_RTN_ON_ERROR
+							(hsl_port_prop_set(dev_id, port_id,p_type));
+						}
+						break;
+
+					case HSL_PP_INNER:/*inner ports*/
+						if (SW_IS_PBMP_MEMBER(inner_pbmp, port_id))
+						{
+							SW_RTN_ON_ERROR
+							(hsl_port_prop_set(dev_id, port_id,p_type));
+						}
+						break;
+
+					case HSL_PP_INCL_CPU:
+						/*the ports include cpu port*/
+						SW_RTN_ON_ERROR
+						(hsl_port_prop_set(dev_id, port_id, p_type));
+						break;
+
+					case HSL_PP_EXCL_CPU:
+						/*the ports exclude cpu port*/
+						if (port_id != pdev->cpu_port_nr)
+						{
+							SW_RTN_ON_ERROR
+							(hsl_port_prop_set(dev_id, port_id,p_type));
+						}
+						break;
+
+					case HSL_PP_CPU:/*cpu port*/
+						if (port_id == pdev->cpu_port_nr)
+						{
+							SW_RTN_ON_ERROR
+							(hsl_port_prop_set(dev_id, port_id,p_type));
+						}
+						break;
+
+					default:
+						break;
+				}
+			}
+		}
+	}
+	return SW_OK;
+}
+
+static sw_error_t
+hppe_dev_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+	hsl_dev_t *pdev = NULL;
+	a_uint32_t i = 0, port_nr = 0, tmp = 0;
+
+	pdev = hsl_dev_ptr_get(dev_id);
+	if (pdev == NULL)
+		return SW_NOT_INITIALIZED;
+
+	tmp = cfg->port_cfg.lan_bmp | cfg->port_cfg.wan_bmp;
+	for(i = 0; i < SW_MAX_NR_PORT; i++) {
+		if(tmp & (1 << i)) {
+			port_nr++;
+		}
+	}
+	pdev->nr_phy = port_nr;
+
+	for(i = 0; i < SW_MAX_NR_PORT; i++) {
+		if(cfg->port_cfg.inner_bmp & (1 << i)) {
+			port_nr++;
+		}
+	}
+
+	for(i = 0; i < SW_MAX_NR_PORT; i++) {
+		if(cfg->port_cfg.cpu_bmp & (1 << i)) {
+			port_nr++;
+			pdev->cpu_port_nr = i;
+			break;
+		}
+	}
+	if(i >= SW_MAX_NR_PORT)
+		return SW_BAD_VALUE;
+	pdev->nr_ports = port_nr;
+	pdev->nr_vlans = 4096;
+	pdev->hw_vlan_query = A_TRUE;
+	pdev->nr_queue = port_nr;
+	pdev->cpu_mode = cfg->cpu_mode;
+	pdev->wan_bmp = cfg->port_cfg.wan_bmp;
+
+	return SW_OK;
+}
+
+sw_error_t
+hppe_cleanup(a_uint32_t dev_id)
+{
+
+    if (hppe_cfg[dev_id])
+    {
+        SW_RTN_ON_ERROR(hsl_port_prop_cleanup_by_dev(dev_id));
+
+        aos_mem_free(hppe_cfg[dev_id]);
+        hppe_cfg[dev_id] = NULL;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Init hsl layer.
+ * @details Comments:
+ *   This operation will init hsl layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t hppe_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    printk("HPPE initializing...\n");
+    if (NULL == hppe_cfg[dev_id])
+    {
+        hppe_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg));
+    }
+
+    if (NULL == hppe_cfg[dev_id])
+    {
+        return SW_OUT_OF_MEM;
+    }
+
+    aos_mem_copy(hppe_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+
+    SW_RTN_ON_ERROR(hppe_dev_init(dev_id, cfg));
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+	{
+		hsl_api_t *p_api;
+
+		SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id));
+		SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
+		SW_RTN_ON_ERROR(hppe_portproperty_init(dev_id));
+
+		SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+		p_api->dev_clean   = hppe_cleanup;
+		p_api->reg_get = sd_reg_hdr_get;
+		p_api->reg_set = sd_reg_hdr_set;
+		p_api->phy_get = sd_reg_mdio_get;
+		p_api->phy_set = sd_reg_mdio_set;
+		p_api->phy_i2c_get = sd_reg_i2c_get;
+		p_api->phy_i2c_set = sd_reg_i2c_set;
+		p_api->uniphy_reg_get = sd_reg_uniphy_get;
+		p_api->uniphy_reg_set = sd_reg_uniphy_set;
+
+	}
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_ip.c b/qca-ssdk/src/hsl/hppe/hppe_ip.c
new file mode 100755
index 0000000..81af477
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_ip.c
@@ -0,0 +1,6892 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_ip_reg.h"
+#include "hppe_ip.h"
+
+#ifndef IN_IP_MINI
+static a_uint32_t host_cmd_id = 0;
+sw_error_t
+hppe_rt_interface_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rt_interface_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + RT_INTERFACE_CNT_TBL_ADDRESS + \
+				index * RT_INTERFACE_CNT_TBL_INC,
+				value->val,
+				5);
+}
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rt_interface_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + RT_INTERFACE_CNT_TBL_ADDRESS + \
+				index * RT_INTERFACE_CNT_TBL_INC,
+				value->val,
+				5);
+}
+
+sw_error_t
+hppe_my_mac_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union my_mac_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + MY_MAC_TBL_ADDRESS + \
+				index * MY_MAC_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_my_mac_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union my_mac_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + MY_MAC_TBL_ADDRESS + \
+				index * MY_MAC_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_l3_vsi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_vsi_u *value)
+{
+	if (index >= L3_VSI_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_VSI_ADDRESS + \
+				index * L3_VSI_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l3_vsi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_vsi_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_VSI_ADDRESS + \
+				index * L3_VSI_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_l3_vsi_ext_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_vsi_ext_u *value)
+{
+	if (index >= L3_VSI_EXT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_VSI_EXT_ADDRESS + \
+				index * L3_VSI_EXT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l3_vsi_ext_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_vsi_ext_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_VSI_EXT_ADDRESS + \
+				index * L3_VSI_EXT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_network_route_ip_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union network_route_ip_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + NETWORK_ROUTE_IP_ADDRESS + \
+				index * NETWORK_ROUTE_IP_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_in_pub_ip_addr_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_pub_ip_addr_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_PUB_IP_ADDR_TBL_ADDRESS + \
+				index * IN_PUB_IP_ADDR_TBL_INC,
+				value->val);
+}
+
+
+sw_error_t
+hppe_in_pub_ip_addr_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_pub_ip_addr_tbl_u *value)
+{
+	if (index >= IN_PUB_IP_ADDR_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_PUB_IP_ADDR_TBL_ADDRESS + \
+				index * IN_PUB_IP_ADDR_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_network_route_ip_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union network_route_ip_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + NETWORK_ROUTE_IP_ADDRESS + \
+				index * NETWORK_ROUTE_IP_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_network_route_ip_ext_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union network_route_ip_ext_u *value)
+{
+	if (index >= NETWORK_ROUTE_IP_EXT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + NETWORK_ROUTE_IP_EXT_ADDRESS + \
+				index * NETWORK_ROUTE_IP_EXT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_network_route_ip_ext_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union network_route_ip_ext_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + NETWORK_ROUTE_IP_EXT_ADDRESS + \
+				index * NETWORK_ROUTE_IP_EXT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_network_route_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union network_route_action_u *value)
+{
+	if (index >= NETWORK_ROUTE_ACTION_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + NETWORK_ROUTE_ACTION_ADDRESS + \
+				index * NETWORK_ROUTE_ACTION_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_network_route_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union network_route_action_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + NETWORK_ROUTE_ACTION_ADDRESS + \
+				index * NETWORK_ROUTE_ACTION_INC,
+				value->val);
+}
+#endif
+#if ((!defined IN_IP_MINI) || (!defined IN_FLOW_MINI))
+sw_error_t
+hppe_l3_route_ctrl_get(
+		a_uint32_t dev_id,
+		union l3_route_ctrl_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_ROUTE_CTRL_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l3_route_ctrl_set(
+		a_uint32_t dev_id,
+		union l3_route_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_ROUTE_CTRL_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ext_get(
+		a_uint32_t dev_id,
+		union l3_route_ctrl_ext_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_ROUTE_CTRL_EXT_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ext_set(
+		a_uint32_t dev_id,
+		union l3_route_ctrl_ext_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_ROUTE_CTRL_EXT_ADDRESS,
+				value->val);
+}
+#endif
+#ifndef IN_IP_MINI
+sw_error_t
+hppe_host_tbl_op_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_ADDRESS,
+				value->val);
+}
+#endif
+#if ((!defined IN_IP_MINI) || (!defined IN_FLOW_MINI))
+sw_error_t
+hppe_host_tbl_op_data0_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data0_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA0_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data1_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data1_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA1_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data2_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data2_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA2_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data2_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data2_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA2_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data3_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data3_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA3_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data3_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data3_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA3_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data4_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data4_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA4_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data4_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data4_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA4_ADDRESS,
+				value->val);
+}
+#endif
+#ifndef IN_IP_MINI
+sw_error_t
+hppe_host_tbl_op_data5_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data5_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA5_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data5_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data5_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA5_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data6_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data6_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA6_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data6_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data6_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA6_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data7_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data7_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA7_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data7_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data7_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA7_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data8_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data8_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA8_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data8_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data8_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA8_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data9_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_data9_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA9_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_data9_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_data9_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA9_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_rslt_get(
+		a_uint32_t dev_id,
+		union host_tbl_op_rslt_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_OP_RSLT_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_op_rslt_set(
+		a_uint32_t dev_id,
+		union host_tbl_op_rslt_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_ADDRESS,
+				value->val);
+}
+#endif
+#if ((!defined IN_IP_MINI) || (!defined IN_FLOW_MINI))
+sw_error_t
+hppe_host_tbl_rd_op_data0_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data0_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA0_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data1_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data1_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA1_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data2_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data2_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA2_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data2_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data2_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA2_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data3_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data3_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA3_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data3_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data3_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA3_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data4_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data4_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA4_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data4_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data4_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA4_ADDRESS,
+				value->val);
+}
+#endif
+#ifndef IN_IP_MINI
+sw_error_t
+hppe_host_tbl_rd_op_data5_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data5_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA5_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data5_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data5_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA5_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data6_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data6_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA6_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data6_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data6_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA6_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data7_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data7_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA7_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data7_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data7_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA7_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data8_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data8_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA8_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data8_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data8_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA8_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data9_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data9_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA9_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data9_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_data9_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA9_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_rslt_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_RSLT_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_op_rslt_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data0_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data0_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data0_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data1_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data1_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data1_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data2_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data2_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA2_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data2_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data2_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data3_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data3_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA3_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data3_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data3_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data4_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data4_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA4_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data4_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data4_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data5_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data5_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA5_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data5_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data5_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data6_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data6_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA6_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data6_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data6_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data7_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data7_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA7_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data7_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data7_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data8_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data8_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA8_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data8_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data8_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data9_get(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data9_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA9_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data9_set(
+		a_uint32_t dev_id,
+		union host_tbl_rd_rslt_data9_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l3_dbg_cmd_get(
+		a_uint32_t dev_id,
+		union l3_dbg_cmd_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_DBG_CMD_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l3_dbg_cmd_set(
+		a_uint32_t dev_id,
+		union l3_dbg_cmd_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_DBG_CMD_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_l3_dbg_wr_data_get(
+		a_uint32_t dev_id,
+		union l3_dbg_wr_data_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_DBG_WR_DATA_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l3_dbg_wr_data_set(
+		a_uint32_t dev_id,
+		union l3_dbg_wr_data_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_DBG_WR_DATA_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_l3_dbg_rd_data_get(
+		a_uint32_t dev_id,
+		union l3_dbg_rd_data_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_DBG_RD_DATA_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l3_dbg_rd_data_set(
+		a_uint32_t dev_id,
+		union l3_dbg_rd_data_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
+sw_error_t
+hppe_l3_vp_port_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_vp_port_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_VP_PORT_TBL_ADDRESS + \
+				index * L3_VP_PORT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_vp_port_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_VP_PORT_TBL_ADDRESS + \
+				index * L3_VP_PORT_TBL_INC,
+				value->val,
+				3);
+}
+#if ((!defined IN_IP_MINI) || (defined IN_PPPOE))
+sw_error_t
+hppe_in_l3_if_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_l3_if_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_L3_IF_TBL_ADDRESS + \
+				index * IN_L3_IF_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_l3_if_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_L3_IF_TBL_ADDRESS + \
+				index * IN_L3_IF_TBL_INC,
+				value->val,
+				2);
+}
+#endif
+#ifndef IN_IP_MINI
+sw_error_t
+hppe_host_ipv6_mcast_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_ipv6_mcast_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_IPV6_MCAST_TBL_ADDRESS + \
+				index * HOST_IPV6_MCAST_TBL_INC,
+				value->val,
+				10);
+}
+
+sw_error_t
+hppe_host_ipv6_mcast_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_ipv6_mcast_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_IPV6_MCAST_TBL_ADDRESS + \
+				index * HOST_IPV6_MCAST_TBL_INC,
+				value->val,
+				10);
+}
+
+sw_error_t
+hppe_host_ipv4_mcast_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_ipv4_mcast_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_IPV4_MCAST_TBL_ADDRESS + \
+				index * HOST_IPV4_MCAST_TBL_INC,
+				value->val,
+				5);
+}
+
+sw_error_t
+hppe_host_ipv4_mcast_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_ipv4_mcast_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_IPV4_MCAST_TBL_ADDRESS + \
+				index * HOST_IPV4_MCAST_TBL_INC,
+				value->val,
+				5);
+}
+
+sw_error_t
+hppe_host_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_ADDRESS + \
+				index * HOST_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_host_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_ADDRESS + \
+				index * HOST_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_host_ipv6_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_ipv6_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_IPV6_TBL_ADDRESS + \
+				index * HOST_IPV6_TBL_INC,
+				value->val,
+				5);
+}
+
+sw_error_t
+hppe_host_ipv6_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union host_ipv6_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_IPV6_TBL_ADDRESS + \
+				index * HOST_IPV6_TBL_INC,
+				value->val,
+				5);
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_nexthop_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_NEXTHOP_TBL_ADDRESS + \
+				index * IN_NEXTHOP_TBL_INC,
+				value->val,
+				4);
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_nexthop_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + IN_NEXTHOP_TBL_ADDRESS + \
+				index * IN_NEXTHOP_TBL_INC,
+				value->val,
+				4);
+}
+#endif
+#if ((!defined IN_IP_MINI) || (defined IN_PPPOE))
+sw_error_t
+hppe_eg_l3_if_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_l3_if_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_L3_IF_TBL_ADDRESS + \
+				index * EG_L3_IF_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_eg_l3_if_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_l3_if_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_L3_IF_TBL_ADDRESS + \
+				index * EG_L3_IF_TBL_INC,
+				value->val,
+				3);
+}
+#endif
+#ifndef IN_IP_MINI
+sw_error_t
+hppe_my_mac_tbl_mac_da_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union my_mac_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_my_mac_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.mac_da_1 << 32 | \
+		reg_val.bf.mac_da_0;
+	return ret;
+}
+
+sw_error_t
+hppe_my_mac_tbl_mac_da_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union my_mac_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_my_mac_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_da_1 = value >> 32;
+	reg_val.bf.mac_da_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_my_mac_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_my_mac_tbl_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union my_mac_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_my_mac_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.valid;
+	return ret;
+}
+
+sw_error_t
+hppe_my_mac_tbl_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union my_mac_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_my_mac_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.valid = value;
+	ret = hppe_my_mac_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_l3_if_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.l3_if_index;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_l3_if_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_if_index = value;
+	ret = hppe_l3_vsi_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_l2_ipv6_mc_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.l2_ipv6_mc_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_l2_ipv6_mc_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_ipv6_mc_mode = value;
+	ret = hppe_l3_vsi_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_l3_if_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.l3_if_valid;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_l3_if_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_if_valid = value;
+	ret = hppe_l3_vsi_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_l2_ipv6_mc_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.l2_ipv6_mc_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_l2_ipv6_mc_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_ipv6_mc_en = value;
+	ret = hppe_l3_vsi_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_l2_ipv4_mc_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.l2_ipv4_mc_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_l2_ipv4_mc_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_ipv4_mc_en = value;
+	ret = hppe_l3_vsi_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_l2_ipv4_mc_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.l2_ipv4_mc_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_l2_ipv4_mc_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l2_ipv4_mc_mode = value;
+	ret = hppe_l3_vsi_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_arp_sg_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_arp_sg_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv6_sg_svlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_sg_svlan_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_nd_sg_cvlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_nd_sg_cvlan_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_nd_sg_vio_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_nd_sg_vio_cmd = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv4_sg_port_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_sg_port_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_nd_sg_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_nd_sg_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv4_sg_svlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_sg_svlan_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv4_sg_cvlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_sg_cvlan_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_arp_sg_svlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_arp_sg_svlan_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_nd_sg_svlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_nd_sg_svlan_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv6_sg_vio_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_sg_vio_cmd = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_nd_sg_port_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_nd_sg_port_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_arp_src_unk_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_arp_src_unk_cmd = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv6_sg_port_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_sg_port_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv4_src_unk_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_src_unk_cmd = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_arp_sg_vio_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_arp_sg_vio_cmd = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_arp_sg_port_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_arp_sg_port_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv4_sg_vio_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_sg_vio_cmd = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv6_src_unk_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_src_unk_cmd = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv6_sg_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_sg_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_arp_sg_cvlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_arp_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_arp_sg_cvlan_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_nd_src_unk_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ip_nd_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_nd_src_unk_cmd = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv4_sg_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv4_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_sg_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv6_sg_cvlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vsi_ext_ipv6_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vsi_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vsi_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_sg_cvlan_en = value;
+	ret = hppe_l3_vsi_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_network_route_ip_ip_addr_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union network_route_ip_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_network_route_ip_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_addr_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_network_route_ip_ip_addr_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union network_route_ip_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_network_route_ip_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr_mask = value;
+	ret = hppe_network_route_ip_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_network_route_ip_ip_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union network_route_ip_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_network_route_ip_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+hppe_network_route_ip_ip_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union network_route_ip_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_network_route_ip_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = hppe_network_route_ip_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_network_route_ip_ext_entry_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union network_route_ip_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_network_route_ip_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.entry_type;
+	return ret;
+}
+
+sw_error_t
+hppe_network_route_ip_ext_entry_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union network_route_ip_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_network_route_ip_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.entry_type = value;
+	ret = hppe_network_route_ip_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_network_route_ip_ext_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union network_route_ip_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_network_route_ip_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.valid;
+	return ret;
+}
+
+sw_error_t
+hppe_network_route_ip_ext_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union network_route_ip_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_network_route_ip_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.valid = value;
+	ret = hppe_network_route_ip_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_network_route_action_lan_wan_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union network_route_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_network_route_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lan_wan;
+	return ret;
+}
+
+sw_error_t
+hppe_network_route_action_lan_wan_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union network_route_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_network_route_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.lan_wan = value;
+	ret = hppe_network_route_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_network_route_action_fwd_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union network_route_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_network_route_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.fwd_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_network_route_action_fwd_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union network_route_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_network_route_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fwd_cmd = value;
+	ret = hppe_network_route_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_network_route_action_dst_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union network_route_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_network_route_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dst_info;
+	return ret;
+}
+
+sw_error_t
+hppe_network_route_action_dst_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union network_route_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_network_route_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dst_info = value;
+	ret = hppe_network_route_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_flow_src_if_check_de_acce_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.flow_src_if_check_de_acce;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_flow_src_if_check_de_acce_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_src_if_check_de_acce = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_pppoe_multicast_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.pppoe_multicast_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_pppoe_multicast_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pppoe_multicast_cmd = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_fail_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.ip_mtu_fail;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_fail_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_mtu_fail = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_flow_src_if_check_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.flow_src_if_check_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_flow_src_if_check_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_src_if_check_cmd = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_icmp_rdt_de_acce_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.icmp_rdt_de_acce;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_icmp_rdt_de_acce_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.icmp_rdt_de_acce = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_flow_de_acce_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.flow_de_acce_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_flow_de_acce_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_de_acce_cmd = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_fail_de_acce_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.ip_mtu_fail_de_acce;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_fail_de_acce_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_mtu_fail_de_acce = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_flow_sync_mismatch_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.flow_sync_mismatch_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_flow_sync_mismatch_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_sync_mismatch_cmd = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_flow_service_code_loop_de_acce_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.flow_service_code_loop_de_acce;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_flow_service_code_loop_de_acce_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_service_code_loop_de_acce = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_flow_sync_mismatch_de_acce_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.flow_sync_mismatch_de_acce;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_flow_sync_mismatch_de_acce_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_sync_mismatch_de_acce = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_df_fail_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.ip_mtu_df_fail;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_df_fail_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_mtu_df_fail = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_flow_service_code_loop_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.flow_service_code_loop;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_flow_service_code_loop_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_service_code_loop = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mru_check_fail_de_acce_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.ip_mru_check_fail_de_acce;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mru_check_fail_de_acce_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_mru_check_fail_de_acce = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_prefix_bc_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.ip_prefix_bc_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_prefix_bc_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_prefix_bc_cmd = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_df_fail_de_acce_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.ip_mtu_df_fail_de_acce;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mtu_df_fail_de_acce_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_mtu_df_fail_de_acce = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_pppoe_multicast_de_acce_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.pppoe_multicast_de_acce;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_pppoe_multicast_de_acce_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pppoe_multicast_de_acce = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mru_check_fail_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.ip_mru_check_fail;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_mru_check_fail_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_mru_check_fail = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_icmp_rdt_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.icmp_rdt_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_icmp_rdt_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.icmp_rdt_cmd = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_prefix_bc_de_acce_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.ip_prefix_bc_de_acce;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ip_prefix_bc_de_acce_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_prefix_bc_de_acce = value;
+	ret = hppe_l3_route_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ext_flow_service_code_loop_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_ext_get(dev_id, &reg_val);
+	*value = reg_val.bf.flow_service_code_loop_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ext_flow_service_code_loop_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_ext_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_service_code_loop_en = value;
+	ret = hppe_l3_route_ctrl_ext_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ext_host_hash_mode_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_ext_get(dev_id, &reg_val);
+	*value = reg_val.bf.host_hash_mode_0;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ext_host_hash_mode_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_ext_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.host_hash_mode_0 = value;
+	ret = hppe_l3_route_ctrl_ext_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ext_host_hash_mode_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_ext_get(dev_id, &reg_val);
+	*value = reg_val.bf.host_hash_mode_1;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ext_host_hash_mode_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_ext_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.host_hash_mode_1 = value;
+	ret = hppe_l3_route_ctrl_ext_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ext_ip_route_mismatch_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_route_ctrl_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_ext_get(dev_id, &reg_val);
+	*value = reg_val.bf.ip_route_mismatch;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_route_ctrl_ext_ip_route_mismatch_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_route_ctrl_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_route_ctrl_ext_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_route_mismatch = value;
+	ret = hppe_l3_route_ctrl_ext_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.entry_index = value;
+	ret = hppe_host_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_cmd_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.cmd_id;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_cmd_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmd_id = value;
+	ret = hppe_host_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_byp_rslt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.byp_rslt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_byp_rslt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.byp_rslt_en = value;
+	ret = hppe_host_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_op_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_op_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_mode = value;
+	ret = hppe_host_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_op_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_type;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_op_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_type = value;
+	ret = hppe_host_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_op_result_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_result;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_op_result_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_result = value;
+	ret = hppe_host_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_busy_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.busy;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_busy_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.busy = value;
+	ret = hppe_host_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.hash_block_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hash_block_bitmap = value;
+	ret = hppe_host_tbl_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data0_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data0_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data0_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_op_data0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data1_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data1_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data1_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data1_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_op_data1_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data2_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data2_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data2_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data2_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_op_data2_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data3_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_data3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data3_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data3_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_data3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data3_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_op_data3_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data4_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_data4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data4_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data4_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_data4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data4_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_op_data4_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data5_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_data5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data5_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data5_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_data5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data5_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_op_data5_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data6_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_data6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data6_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data6_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_data6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data6_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_op_data6_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data7_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_data7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data7_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data7_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_data7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data7_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_op_data7_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data8_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_data8_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data8_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data8_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_data8_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data8_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_op_data8_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data9_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_data9_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data9_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_data9_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_op_data9_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_data9_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_op_data9_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_rslt_op_rslt_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_rslt;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_rslt_op_rslt_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_op_rslt_valid_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.valid_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_rslt_valid_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_op_rslt_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_rslt_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_op_rslt_cmd_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.cmd_id;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_op_rslt_cmd_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.entry_index = value;
+	ret = hppe_host_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_cmd_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.cmd_id;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_cmd_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmd_id = value;
+	ret = hppe_host_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_byp_rslt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.byp_rslt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_byp_rslt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.byp_rslt_en = value;
+	ret = hppe_host_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_op_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_op_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_mode = value;
+	ret = hppe_host_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_op_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_type;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_op_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_type = value;
+	ret = hppe_host_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_op_result_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_result;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_op_result_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.op_result = value;
+	ret = hppe_host_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_busy_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.busy;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_busy_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.busy = value;
+	ret = hppe_host_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_hash_block_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	*value = reg_val.bf.hash_block_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_hash_block_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hash_block_bitmap = value;
+	ret = hppe_host_tbl_rd_op_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data0_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data0_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data0_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_rd_op_data0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data1_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data1_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data1_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data1_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_rd_op_data1_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data2_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data2_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data2_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data2_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_rd_op_data2_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data3_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_data3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data3_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data3_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_data3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data3_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_rd_op_data3_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data4_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_data4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data4_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data4_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_data4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data4_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_rd_op_data4_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data5_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_data5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data5_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data5_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_data5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data5_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_rd_op_data5_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data6_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_data6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data6_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data6_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_data6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data6_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_rd_op_data6_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data7_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_data7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data7_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data7_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_data7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data7_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_rd_op_data7_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data8_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_data8_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data8_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data8_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_data8_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data8_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_rd_op_data8_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data9_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_data9_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data9_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_data9_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union host_tbl_rd_op_data9_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_data9_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_host_tbl_rd_op_data9_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_op_rslt_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.op_rslt;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_op_rslt_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_valid_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.valid_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_valid_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_entry_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.entry_index;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_entry_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_cmd_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_op_rslt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_op_rslt_get(dev_id, &reg_val);
+	*value = reg_val.bf.cmd_id;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_op_rslt_cmd_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data0_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_rslt_data0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_rslt_data0_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data0_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data1_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_rslt_data1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_rslt_data1_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data1_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data2_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_rslt_data2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_rslt_data2_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data2_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data3_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_rslt_data3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_rslt_data3_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data3_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data4_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_rslt_data4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_rslt_data4_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data4_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data5_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_rslt_data5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_rslt_data5_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data5_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data6_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_rslt_data6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_rslt_data6_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data6_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data7_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_rslt_data7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_rslt_data7_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data7_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data8_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_rslt_data8_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_rslt_data8_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data8_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data9_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union host_tbl_rd_rslt_data9_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_host_tbl_rd_rslt_data9_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_host_tbl_rd_rslt_data9_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l3_dbg_cmd_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_dbg_cmd_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_dbg_cmd_get(dev_id, &reg_val);
+	*value = reg_val.bf.type;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_dbg_cmd_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_dbg_cmd_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_dbg_cmd_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.type = value;
+	ret = hppe_l3_dbg_cmd_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_dbg_cmd_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_dbg_cmd_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_dbg_cmd_get(dev_id, &reg_val);
+	*value = reg_val.bf.addr;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_dbg_cmd_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_dbg_cmd_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_dbg_cmd_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.addr = value;
+	ret = hppe_l3_dbg_cmd_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_dbg_wr_data_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_dbg_wr_data_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_dbg_wr_data_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_dbg_wr_data_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_dbg_wr_data_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_dbg_wr_data_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.data = value;
+	ret = hppe_l3_dbg_wr_data_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_dbg_rd_data_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_dbg_rd_data_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_dbg_rd_data_get(dev_id, &reg_val);
+	*value = reg_val.bf.data;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_dbg_rd_data_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_arp_sg_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_arp_sg_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv6_sg_svlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_sg_svlan_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_nd_sg_cvlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_nd_sg_cvlan_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_l3_if_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.l3_if_valid;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_l3_if_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_if_valid = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_nd_sg_vio_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_nd_sg_vio_cmd = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv4_sg_port_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_sg_port_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_nd_sg_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_nd_sg_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_l3_if_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.l3_if_index;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_l3_if_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_if_index = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv4_sg_svlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_sg_svlan_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv4_sg_cvlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_sg_cvlan_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_arp_sg_svlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_arp_sg_svlan_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_mac_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_valid;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_mac_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_valid = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_svlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_nd_sg_svlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_svlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_nd_sg_svlan_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_vsi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vsi;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_vsi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vsi = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_mac_da_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.mac_da_1 << 16 | \
+		reg_val.bf.mac_da_0;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_mac_da_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_da_1 = value >> 16;
+	reg_val.bf.mac_da_0 = value & (((a_uint64_t)1<<16)-1);
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv6_sg_vio_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_sg_vio_cmd = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_nd_sg_port_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_nd_sg_port_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_arp_src_unk_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_arp_src_unk_cmd = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv6_sg_port_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_sg_port_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv4_src_unk_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_src_unk_cmd = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_port_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_arp_sg_port_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_port_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_arp_sg_port_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_arp_sg_vio_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_arp_sg_vio_cmd = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_vio_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv4_sg_vio_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_vio_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_sg_vio_cmd = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv6_src_unk_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_src_unk_cmd = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_arp_sg_cvlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_arp_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_arp_sg_cvlan_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv6_sg_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_sg_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_vsi_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vsi_valid;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_vsi_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vsi_valid = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_src_unk_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_nd_src_unk_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ip_nd_src_unk_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_nd_src_unk_cmd = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv4_sg_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv4_sg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_sg_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_cvlan_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv6_sg_cvlan_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_vp_port_tbl_ipv6_sg_cvlan_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_vp_port_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_vp_port_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_sg_cvlan_en = value;
+	ret = hppe_l3_vp_port_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_ttl_dec_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ttl_dec_bypass;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_ttl_dec_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ttl_dec_bypass = value;
+	ret = hppe_in_l3_if_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_ttl_exceed_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ttl_exceed_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_ttl_exceed_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ttl_exceed_cmd = value;
+	ret = hppe_in_l3_if_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_mru_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mru;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_mru_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mru = value;
+	ret = hppe_in_l3_if_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_ipv4_uc_route_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv4_uc_route_en;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_ipv4_uc_route_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_uc_route_en = value;
+	ret = hppe_in_l3_if_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_ipv6_uc_route_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipv6_uc_route_en;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_ipv6_uc_route_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_uc_route_en = value;
+	ret = hppe_in_l3_if_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_ttl_exceed_de_acce_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ttl_exceed_de_acce;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_ttl_exceed_de_acce_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ttl_exceed_de_acce = value;
+	ret = hppe_in_l3_if_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_icmp_trigger_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.icmp_trigger_en;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_icmp_trigger_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.icmp_trigger_en = value;
+	ret = hppe_in_l3_if_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_mac_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_mac_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_bitmap = value;
+	ret = hppe_in_l3_if_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_pppoe_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pppoe_en;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_pppoe_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pppoe_en = value;
+	ret = hppe_in_l3_if_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_mtu_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mtu;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l3_if_tbl_mtu_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l3_if_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mtu = value;
+	ret = hppe_in_l3_if_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_ip_pub_addr_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.ip_pub_addr_index;
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_ip_pub_addr_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.ip_pub_addr_index = value;
+	ret = hppe_in_nexthop_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_cvid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.cvid;
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_cvid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.cvid = value;
+	ret = hppe_in_nexthop_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_post_l3_if_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.post_l3_if;
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_post_l3_if_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.post_l3_if = value;
+	ret = hppe_in_nexthop_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_mac_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf1.mac_addr_1 << 16 | \
+		reg_val.bf1.mac_addr_0;
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_mac_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.mac_addr_1 = value >> 16;
+	reg_val.bf1.mac_addr_0 = value & (((a_uint64_t)1<<16)-1);
+	ret = hppe_in_nexthop_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_port_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf0.port;
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_port_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf0.port = value;
+	ret = hppe_in_nexthop_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_ip_to_me_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.ip_to_me;
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_ip_to_me_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.ip_to_me = value;
+	ret = hppe_in_nexthop_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_ip_addr_dnat_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.ip_addr_dnat;
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_ip_addr_dnat_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.ip_addr_dnat = value;
+	ret = hppe_in_nexthop_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.type;
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.type = value;
+	ret = hppe_in_nexthop_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_stag_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.stag_fmt;
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_stag_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.stag_fmt = value;
+	ret = hppe_in_nexthop_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_vsi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.vsi;
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_vsi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.vsi = value;
+	ret = hppe_in_nexthop_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_svid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.svid;
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_svid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.svid = value;
+	ret = hppe_in_nexthop_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_ctag_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.ctag_fmt;
+	return ret;
+}
+
+sw_error_t
+hppe_in_nexthop_tbl_ctag_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_nexthop_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_nexthop_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.ctag_fmt = value;
+	ret = hppe_in_nexthop_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_l3_if_tbl_session_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_l3_if_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.session_id;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_l3_if_tbl_session_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_l3_if_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.session_id = value;
+	ret = hppe_eg_l3_if_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_l3_if_tbl_mac_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union eg_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_l3_if_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.mac_addr_1 << 32 | \
+		reg_val.bf.mac_addr_0;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_l3_if_tbl_mac_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union eg_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_l3_if_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr_1 = value >> 32;
+	reg_val.bf.mac_addr_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_eg_l3_if_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_l3_if_tbl_pppoe_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_l3_if_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pppoe_en;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_l3_if_tbl_pppoe_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_l3_if_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_l3_if_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pppoe_en = value;
+	ret = hppe_eg_l3_if_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_pub_ip_addr_tbl_ip_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_pub_ip_addr_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_pub_ip_addr_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+hppe_in_pub_ip_addr_tbl_ip_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_pub_ip_addr_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_pub_ip_addr_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = hppe_in_pub_ip_addr_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union rt_interface_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.byte_cnt_1 << 32 | \
+		reg_val.bf.byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union rt_interface_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.byte_cnt_1 = value >> 32;
+	reg_val.bf.byte_cnt_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_rt_interface_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rt_interface_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rt_interface_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pkt_cnt = value;
+	ret = hppe_rt_interface_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_drop_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union rt_interface_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.drop_byte_cnt_1 << 24 | \
+		reg_val.bf.drop_byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_drop_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union rt_interface_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.drop_byte_cnt_1 = value >> 24;
+	reg_val.bf.drop_byte_cnt_0 = value & (((a_uint64_t)1<<24)-1);
+	ret = hppe_rt_interface_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_drop_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rt_interface_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.drop_pkt_cnt_1 << 24 | \
+		reg_val.bf.drop_pkt_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_rt_interface_cnt_tbl_drop_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rt_interface_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.drop_pkt_cnt_1 = value >> 24;
+	reg_val.bf.drop_pkt_cnt_0 = value & (((a_uint64_t)1<<24)-1);
+	ret = hppe_rt_interface_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+
+sw_error_t
+hppe_host_op_common(
+		a_uint32_t dev_id,
+		a_uint32_t op_type,
+		a_uint32_t op_mode,
+		a_uint32_t *index)
+{
+	union host_tbl_op_u op;
+	union host_tbl_op_rslt_u result;
+	a_uint32_t i = 0x100;
+	sw_error_t rv;
+
+	op.bf.cmd_id = host_cmd_id;
+	host_cmd_id++;
+	op.bf.byp_rslt_en = 0;
+	op.bf.op_type = op_type;
+	op.bf.hash_block_bitmap = 3;
+	op.bf.op_mode = op_mode;
+	op.bf.entry_index = *index;
+
+	rv = hppe_host_tbl_op_set(dev_id, &op);
+	if (SW_OK != rv)
+		return rv;
+	rv = hppe_host_tbl_op_rslt_get(dev_id, &result);
+	if (SW_OK != rv)
+		return rv;
+	while (!result.bf.valid_cnt && --i) {
+		hppe_host_tbl_op_rslt_get(dev_id, &result);
+	}
+	if (i == 0)
+		return SW_BUSY;
+	if (result.bf.op_rslt == 0) {
+		*index = result.bf.entry_index;
+		return SW_OK;
+	}
+	else
+		return SW_FAIL;
+	
+}
+
+sw_error_t
+hppe_host_ipv4_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_tbl_u *entry)
+{
+	hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0]));
+	hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1]));
+	hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2]));
+	return hppe_host_op_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_host_ipv6_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_tbl_u *entry)
+{
+	hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0]));
+	hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1]));
+	hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2]));
+	hppe_host_tbl_op_data3_set(dev_id, (union host_tbl_op_data3_u *)(&entry->val[3]));
+	hppe_host_tbl_op_data4_set(dev_id, (union host_tbl_op_data4_u *)(&entry->val[4]));
+	return hppe_host_op_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_host_ipv4_mcast_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv4_mcast_tbl_u *entry)
+{
+	hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0]));
+	hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1]));
+	hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2]));
+	hppe_host_tbl_op_data3_set(dev_id, (union host_tbl_op_data3_u *)(&entry->val[3]));
+	hppe_host_tbl_op_data4_set(dev_id, (union host_tbl_op_data4_u *)(&entry->val[4]));
+	return hppe_host_op_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_host_ipv6_mcast_add(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_mcast_tbl_u *entry)
+{
+	hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0]));
+	hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1]));
+	hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2]));
+	hppe_host_tbl_op_data3_set(dev_id, (union host_tbl_op_data3_u *)(&entry->val[3]));
+	hppe_host_tbl_op_data4_set(dev_id, (union host_tbl_op_data4_u *)(&entry->val[4]));
+	hppe_host_tbl_op_data5_set(dev_id, (union host_tbl_op_data5_u *)(&entry->val[5]));
+	hppe_host_tbl_op_data6_set(dev_id, (union host_tbl_op_data6_u *)(&entry->val[6]));
+	hppe_host_tbl_op_data7_set(dev_id, (union host_tbl_op_data7_u *)(&entry->val[7]));
+	hppe_host_tbl_op_data8_set(dev_id, (union host_tbl_op_data8_u *)(&entry->val[8]));
+	hppe_host_tbl_op_data9_set(dev_id, (union host_tbl_op_data9_u *)(&entry->val[9]));
+	return hppe_host_op_common(dev_id, 0, op_mode, index);
+}
+
+sw_error_t
+hppe_host_ipv4_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0]));
+		hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1]));
+		hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2]));
+	}
+	return hppe_host_op_common(dev_id, 1, op_mode, index);
+
+}
+
+sw_error_t
+hppe_host_ipv6_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0]));
+		hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1]));
+		hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2]));
+		hppe_host_tbl_op_data3_set(dev_id, (union host_tbl_op_data3_u *)(&entry->val[3]));
+		hppe_host_tbl_op_data4_set(dev_id, (union host_tbl_op_data4_u *)(&entry->val[4]));
+	}
+	return hppe_host_op_common(dev_id, 1, op_mode, index);
+}
+
+sw_error_t
+hppe_host_ipv4_mcast_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv4_mcast_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0]));
+		hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1]));
+		hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2]));
+		hppe_host_tbl_op_data3_set(dev_id, (union host_tbl_op_data3_u *)(&entry->val[3]));
+		hppe_host_tbl_op_data4_set(dev_id, (union host_tbl_op_data4_u *)(&entry->val[4]));
+	}
+	return hppe_host_op_common(dev_id, 1, op_mode, index);
+}
+
+sw_error_t
+hppe_host_ipv6_mcast_del(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_mcast_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0]));
+		hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1]));
+		hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2]));
+		hppe_host_tbl_op_data3_set(dev_id, (union host_tbl_op_data3_u *)(&entry->val[3]));
+		hppe_host_tbl_op_data4_set(dev_id, (union host_tbl_op_data4_u *)(&entry->val[4]));
+		hppe_host_tbl_op_data5_set(dev_id, (union host_tbl_op_data5_u *)(&entry->val[5]));
+		hppe_host_tbl_op_data6_set(dev_id, (union host_tbl_op_data6_u *)(&entry->val[6]));
+		hppe_host_tbl_op_data7_set(dev_id, (union host_tbl_op_data7_u *)(&entry->val[7]));
+		hppe_host_tbl_op_data8_set(dev_id, (union host_tbl_op_data8_u *)(&entry->val[8]));
+		hppe_host_tbl_op_data9_set(dev_id, (union host_tbl_op_data9_u *)(&entry->val[9]));
+	}
+	return hppe_host_op_common(dev_id, 1, op_mode, index);
+}
+
+sw_error_t
+hppe_host_get_common(
+		a_uint32_t dev_id,
+		a_uint32_t op_mode,
+		a_uint32_t *index,
+		a_uint32_t *data,
+		a_uint32_t num)
+{
+	union host_tbl_rd_op_u op;
+	union host_tbl_rd_op_rslt_u result;
+	a_uint32_t i = 0x100;
+	sw_error_t rv;
+
+	op.bf.cmd_id = host_cmd_id;
+	host_cmd_id++;
+	op.bf.byp_rslt_en = 0;
+	op.bf.op_type = 2;
+	op.bf.hash_block_bitmap = 3;
+	op.bf.op_mode = op_mode;
+	op.bf.entry_index = *index;
+
+	rv = hppe_host_tbl_rd_op_set(dev_id, &op);
+	if (SW_OK != rv)
+		return rv;
+	rv = hppe_host_tbl_rd_op_rslt_get(dev_id, &result);
+	if (SW_OK != rv)
+		return rv;
+	while (!result.bf.valid_cnt && --i) {
+		hppe_host_tbl_rd_op_rslt_get(dev_id, &result);
+	}
+	if (i == 0)
+		return SW_BUSY;
+	if (result.bf.op_rslt == 0) {
+		hppe_reg_tbl_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA0_ADDRESS,
+				data, num);
+		*index = result.bf.entry_index;
+		return SW_OK;
+	}
+	else
+		return SW_FAIL;
+	
+}
+
+
+sw_error_t
+hppe_host_ipv4_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_host_tbl_rd_op_data0_set(dev_id, (union host_tbl_rd_op_data0_u *)(&entry->val[0]));
+		hppe_host_tbl_rd_op_data1_set(dev_id, (union host_tbl_rd_op_data1_u *)(&entry->val[1]));
+		hppe_host_tbl_rd_op_data2_set(dev_id, (union host_tbl_rd_op_data2_u *)(&entry->val[2]));
+	}
+	return hppe_host_get_common(dev_id, op_mode, index,
+					(a_uint32_t *)entry, 3);
+
+}
+
+sw_error_t
+hppe_host_ipv6_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_host_tbl_rd_op_data0_set(dev_id, (union host_tbl_rd_op_data0_u *)(&entry->val[0]));
+		hppe_host_tbl_rd_op_data1_set(dev_id, (union host_tbl_rd_op_data1_u *)(&entry->val[1]));
+		hppe_host_tbl_rd_op_data2_set(dev_id, (union host_tbl_rd_op_data2_u *)(&entry->val[2]));
+		hppe_host_tbl_rd_op_data3_set(dev_id, (union host_tbl_rd_op_data3_u *)(&entry->val[3]));
+		hppe_host_tbl_rd_op_data4_set(dev_id, (union host_tbl_rd_op_data4_u *)(&entry->val[4]));
+	}
+	return hppe_host_get_common(dev_id, op_mode, index,
+					(a_uint32_t *)entry, 5);
+}
+
+sw_error_t
+hppe_host_ipv4_mcast_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv4_mcast_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_host_tbl_rd_op_data0_set(dev_id, (union host_tbl_rd_op_data0_u *)(&entry->val[0]));
+		hppe_host_tbl_rd_op_data1_set(dev_id, (union host_tbl_rd_op_data1_u *)(&entry->val[1]));
+		hppe_host_tbl_rd_op_data2_set(dev_id, (union host_tbl_rd_op_data2_u *)(&entry->val[2]));
+		hppe_host_tbl_rd_op_data3_set(dev_id, (union host_tbl_rd_op_data3_u *)(&entry->val[3]));
+		hppe_host_tbl_rd_op_data4_set(dev_id, (union host_tbl_rd_op_data4_u *)(&entry->val[4]));
+	}
+	return hppe_host_get_common(dev_id, op_mode, index,
+					(a_uint32_t *)entry, 5);
+}
+
+sw_error_t
+hppe_host_ipv6_mcast_get(
+		a_uint32_t dev_id, a_uint32_t op_mode,
+		a_uint32_t *index, union host_ipv6_mcast_tbl_u *entry)
+{
+	if (op_mode == 0) {
+		hppe_host_tbl_rd_op_data0_set(dev_id, (union host_tbl_rd_op_data0_u *)(&entry->val[0]));
+		hppe_host_tbl_rd_op_data1_set(dev_id, (union host_tbl_rd_op_data1_u *)(&entry->val[1]));
+		hppe_host_tbl_rd_op_data2_set(dev_id, (union host_tbl_rd_op_data2_u *)(&entry->val[2]));
+		hppe_host_tbl_rd_op_data3_set(dev_id, (union host_tbl_rd_op_data3_u *)(&entry->val[3]));
+		hppe_host_tbl_rd_op_data4_set(dev_id, (union host_tbl_rd_op_data4_u *)(&entry->val[4]));
+		hppe_host_tbl_rd_op_data5_set(dev_id, (union host_tbl_rd_op_data5_u *)(&entry->val[5]));
+		hppe_host_tbl_rd_op_data6_set(dev_id, (union host_tbl_rd_op_data6_u *)(&entry->val[6]));
+		hppe_host_tbl_rd_op_data7_set(dev_id, (union host_tbl_rd_op_data7_u *)(&entry->val[7]));
+		hppe_host_tbl_rd_op_data8_set(dev_id, (union host_tbl_rd_op_data8_u *)(&entry->val[8]));
+		hppe_host_tbl_rd_op_data9_set(dev_id, (union host_tbl_rd_op_data9_u *)(&entry->val[9]));
+	}
+	return hppe_host_get_common(dev_id, op_mode, index,
+					(a_uint32_t *)entry, 10);
+}
+
+sw_error_t
+hppe_host_flush_common(a_uint32_t dev_id)
+{
+	union host_tbl_op_u op;
+	union host_tbl_op_rslt_u result;
+	a_uint32_t i = 0x100 * 50;
+	sw_error_t rv;
+
+	op.bf.cmd_id = host_cmd_id;
+	host_cmd_id++;
+	op.bf.byp_rslt_en = 0;
+	op.bf.op_type = 3;
+	op.bf.hash_block_bitmap = 3;
+	op.bf.op_mode = 0;
+
+	rv = hppe_host_tbl_op_set(dev_id, &op);
+	if (SW_OK != rv)
+		return rv;
+	rv = hppe_host_tbl_op_rslt_get(dev_id, &result);
+	if (SW_OK != rv)
+		return rv;
+	while (!result.bf.valid_cnt && --i) {
+		hppe_host_tbl_op_rslt_get(dev_id, &result);
+	}
+	if (i == 0)
+		return SW_BUSY;
+	if (result.bf.op_rslt == 0)
+		return SW_OK;
+	else
+		return SW_FAIL;
+	
+	
+}
+#endif
diff --git a/qca-ssdk/src/hsl/hppe/hppe_mib.c b/qca-ssdk/src/hsl/hppe/hppe_mib.c
new file mode 100755
index 0000000..34c66db
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_mib.c
@@ -0,0 +1,2167 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_mib_reg.h"
+#include "hppe_mib.h"
+
+sw_error_t
+hppe_mac_mib_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_mib_ctrl_u *value)
+{
+	if (index >= MAC_MIB_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_MIB_CTRL_ADDRESS + \
+				index * MAC_MIB_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_mib_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_mib_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_MIB_CTRL_ADDRESS + \
+				index * MAC_MIB_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_rxbroad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxbroad_u *value)
+{
+	if (index >= RXBROAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXBROAD_ADDRESS + \
+				index * RXBROAD_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxbroad_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxbroad_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpause_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpause_u *value)
+{
+	if (index >= RXPAUSE_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXPAUSE_ADDRESS + \
+				index * RXPAUSE_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxpause_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpause_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxmulti_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxmulti_u *value)
+{
+	if (index >= RXMULTI_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXMULTI_ADDRESS + \
+				index * RXMULTI_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxmulti_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxmulti_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxfcserr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxfcserr_u *value)
+{
+	if (index >= RXFCSERR_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXFCSERR_ADDRESS + \
+				index * RXFCSERR_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxfcserr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxfcserr_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxalignerr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxalignerr_u *value)
+{
+	if (index >= RXALIGNERR_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXALIGNERR_ADDRESS + \
+				index * RXALIGNERR_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxalignerr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxalignerr_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxrunt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxrunt_u *value)
+{
+	if (index >= RXRUNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXRUNT_ADDRESS + \
+				index * RXRUNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxrunt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxrunt_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxfrag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxfrag_u *value)
+{
+	if (index >= RXFRAG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXFRAG_ADDRESS + \
+				index * RXFRAG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxfrag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxfrag_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxjumbofcserr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxjumbofcserr_u *value)
+{
+	if (index >= RXJUMBOFCSERR_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXJUMBOFCSERR_ADDRESS + \
+				index * RXJUMBOFCSERR_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxjumbofcserr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxjumbofcserr_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxjumboalignerr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxjumboalignerr_u *value)
+{
+	if (index >= RXJUMBOALIGNERR_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXJUMBOALIGNERR_ADDRESS + \
+				index * RXJUMBOALIGNERR_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxjumboalignerr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxjumboalignerr_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpkt64_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt64_u *value)
+{
+	if (index >= RXPKT64_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXPKT64_ADDRESS + \
+				index * RXPKT64_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxpkt64_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt64_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpkt65to127_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt65to127_u *value)
+{
+	if (index >= RXPKT65TO127_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXPKT65TO127_ADDRESS + \
+				index * RXPKT65TO127_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxpkt65to127_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt65to127_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpkt128to255_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt128to255_u *value)
+{
+	if (index >= RXPKT128TO255_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXPKT128TO255_ADDRESS + \
+				index * RXPKT128TO255_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxpkt128to255_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt128to255_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpkt256to511_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt256to511_u *value)
+{
+	if (index >= RXPKT256TO511_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXPKT256TO511_ADDRESS + \
+				index * RXPKT256TO511_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxpkt256to511_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt256to511_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpkt512to1023_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt512to1023_u *value)
+{
+	if (index >= RXPKT512TO1023_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXPKT512TO1023_ADDRESS + \
+				index * RXPKT512TO1023_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxpkt512to1023_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt512to1023_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpkt1024to1518_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt1024to1518_u *value)
+{
+	if (index >= RXPKT1024TO1518_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXPKT1024TO1518_ADDRESS + \
+				index * RXPKT1024TO1518_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxpkt1024to1518_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt1024to1518_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpkt1519tox_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt1519tox_u *value)
+{
+	if (index >= RXPKT1519TOX_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXPKT1519TOX_ADDRESS + \
+				index * RXPKT1519TOX_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxpkt1519tox_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxpkt1519tox_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxtoolong_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxtoolong_u *value)
+{
+	if (index >= RXTOOLONG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXTOOLONG_ADDRESS + \
+				index * RXTOOLONG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxtoolong_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxtoolong_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxgoodbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxgoodbyte_l_u *value)
+{
+	if (index >= RXGOODBYTE_L_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXGOODBYTE_L_ADDRESS + \
+				index * RXGOODBYTE_L_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxgoodbyte_l_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxgoodbyte_l_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxgoodbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxgoodbyte_h_u *value)
+{
+	if (index >= RXGOODBYTE_H_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXGOODBYTE_H_ADDRESS + \
+				index * RXGOODBYTE_H_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxgoodbyte_h_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxgoodbyte_h_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxbadbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxbadbyte_l_u *value)
+{
+	if (index >= RXBADBYTE_L_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXBADBYTE_L_ADDRESS + \
+				index * RXBADBYTE_L_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxbadbyte_l_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxbadbyte_l_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxbadbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxbadbyte_h_u *value)
+{
+	if (index >= RXBADBYTE_H_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXBADBYTE_H_ADDRESS + \
+				index * RXBADBYTE_H_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxbadbyte_h_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxbadbyte_h_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxuni_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxuni_u *value)
+{
+	if (index >= RXUNI_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + RXUNI_ADDRESS + \
+				index * RXUNI_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rxuni_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rxuni_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txbroad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txbroad_u *value)
+{
+	if (index >= TXBROAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXBROAD_ADDRESS + \
+				index * TXBROAD_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txbroad_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txbroad_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpause_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpause_u *value)
+{
+	if (index >= TXPAUSE_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXPAUSE_ADDRESS + \
+				index * TXPAUSE_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txpause_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpause_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txmulti_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txmulti_u *value)
+{
+	if (index >= TXMULTI_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXMULTI_ADDRESS + \
+				index * TXMULTI_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txmulti_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txmulti_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txunderrun_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txunderrun_u *value)
+{
+	if (index >= TXUNDERRUN_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXUNDERRUN_ADDRESS + \
+				index * TXUNDERRUN_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txunderrun_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txunderrun_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpkt64_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt64_u *value)
+{
+	if (index >= TXPKT64_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXPKT64_ADDRESS + \
+				index * TXPKT64_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txpkt64_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt64_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpkt65to127_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt65to127_u *value)
+{
+	if (index >= TXPKT65TO127_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXPKT65TO127_ADDRESS + \
+				index * TXPKT65TO127_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txpkt65to127_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt65to127_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpkt128to255_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt128to255_u *value)
+{
+	if (index >= TXPKT128TO255_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXPKT128TO255_ADDRESS + \
+				index * TXPKT128TO255_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txpkt128to255_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt128to255_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpkt256to511_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt256to511_u *value)
+{
+	if (index >= TXPKT256TO511_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXPKT256TO511_ADDRESS + \
+				index * TXPKT256TO511_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txpkt256to511_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt256to511_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpkt512to1023_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt512to1023_u *value)
+{
+	if (index >= TXPKT512TO1023_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXPKT512TO1023_ADDRESS + \
+				index * TXPKT512TO1023_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txpkt512to1023_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt512to1023_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpkt1024to1518_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt1024to1518_u *value)
+{
+	if (index >= TXPKT1024TO1518_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXPKT1024TO1518_ADDRESS + \
+				index * TXPKT1024TO1518_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txpkt1024to1518_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt1024to1518_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpkt1519tox_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt1519tox_u *value)
+{
+	if (index >= TXPKT1519TOX_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXPKT1519TOX_ADDRESS + \
+				index * TXPKT1519TOX_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txpkt1519tox_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txpkt1519tox_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txbyte_l_u *value)
+{
+	if (index >= TXBYTE_L_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXBYTE_L_ADDRESS + \
+				index * TXBYTE_L_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txbyte_l_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txbyte_l_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txbyte_h_u *value)
+{
+	if (index >= TXBYTE_H_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXBYTE_H_ADDRESS + \
+				index * TXBYTE_H_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txbyte_h_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txbyte_h_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txcollisions_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txcollisions_u *value)
+{
+	if (index >= TXCOLLISIONS_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXCOLLISIONS_ADDRESS + \
+				index * TXCOLLISIONS_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txcollisions_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txcollisions_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txabortcol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txabortcol_u *value)
+{
+	if (index >= TXABORTCOL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXABORTCOL_ADDRESS + \
+				index * TXABORTCOL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txabortcol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txabortcol_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txmulticol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txmulticol_u *value)
+{
+	if (index >= TXMULTICOL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXMULTICOL_ADDRESS + \
+				index * TXMULTICOL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txmulticol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txmulticol_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txsinglecol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txsinglecol_u *value)
+{
+	if (index >= TXSINGLECOL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXSINGLECOL_ADDRESS + \
+				index * TXSINGLECOL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txsinglecol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txsinglecol_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txexcessivedefer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txexcessivedefer_u *value)
+{
+	if (index >= TXEXCESSIVEDEFER_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXEXCESSIVEDEFER_ADDRESS + \
+				index * TXEXCESSIVEDEFER_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txexcessivedefer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txexcessivedefer_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txdefer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txdefer_u *value)
+{
+	if (index >= TXDEFER_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXDEFER_ADDRESS + \
+				index * TXDEFER_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txdefer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txdefer_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txlatecol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txlatecol_u *value)
+{
+	if (index >= TXLATECOL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXLATECOL_ADDRESS + \
+				index * TXLATECOL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txlatecol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txlatecol_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txuni_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txuni_u *value)
+{
+	if (index >= TXUNI_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + TXUNI_ADDRESS + \
+				index * TXUNI_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_txuni_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union txuni_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mac_mib_ctrl_mib_reset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_mib_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_mib_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mib_reset;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_mib_ctrl_mib_reset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_mib_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_mib_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mib_reset = value;
+	ret = hppe_mac_mib_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_mib_ctrl_mib_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_mib_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_mib_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mib_en;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_mib_ctrl_mib_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_mib_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_mib_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mib_en = value;
+	ret = hppe_mac_mib_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_mib_ctrl_mib_rd_clr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_mib_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_mib_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mib_rd_clr;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_mib_ctrl_mib_rd_clr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_mib_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_mib_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mib_rd_clr = value;
+	ret = hppe_mac_mib_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rxbroad_rxbroad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxbroad_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxbroad_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxbroad;
+	return ret;
+}
+
+sw_error_t
+hppe_rxbroad_rxbroad_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpause_rxpause_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxpause_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxpause_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxpause;
+	return ret;
+}
+
+sw_error_t
+hppe_rxpause_rxpause_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxmulti_rxmulti_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxmulti_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxmulti_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxmulti;
+	return ret;
+}
+
+sw_error_t
+hppe_rxmulti_rxmulti_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxfcserr_rxfcserr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxfcserr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxfcserr_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxfcserr;
+	return ret;
+}
+
+sw_error_t
+hppe_rxfcserr_rxfcserr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxalignerr_rxalignerr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxalignerr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxalignerr_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxalignerr;
+	return ret;
+}
+
+sw_error_t
+hppe_rxalignerr_rxalignerr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxrunt_rxrunt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxrunt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxrunt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxrunt;
+	return ret;
+}
+
+sw_error_t
+hppe_rxrunt_rxrunt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxfrag_rxfrag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxfrag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxfrag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxfrag;
+	return ret;
+}
+
+sw_error_t
+hppe_rxfrag_rxfrag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxjumbofcserr_rxjumbofcserr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxjumbofcserr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxjumbofcserr_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxjumbofcserr;
+	return ret;
+}
+
+sw_error_t
+hppe_rxjumbofcserr_rxjumbofcserr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxjumboalignerr_rxjumboalignerr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxjumboalignerr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxjumboalignerr_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxjumboalignerr;
+	return ret;
+}
+
+sw_error_t
+hppe_rxjumboalignerr_rxjumboalignerr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpkt64_rxpkt64_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxpkt64_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxpkt64_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxpkt64;
+	return ret;
+}
+
+sw_error_t
+hppe_rxpkt64_rxpkt64_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpkt65to127_rxpkt65to127_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxpkt65to127_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxpkt65to127_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxpkt65to127;
+	return ret;
+}
+
+sw_error_t
+hppe_rxpkt65to127_rxpkt65to127_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpkt128to255_rxpkt128to255_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxpkt128to255_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxpkt128to255_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxpkt128to255;
+	return ret;
+}
+
+sw_error_t
+hppe_rxpkt128to255_rxpkt128to255_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpkt256to511_rxpkt256to511_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxpkt256to511_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxpkt256to511_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxpkt256to511;
+	return ret;
+}
+
+sw_error_t
+hppe_rxpkt256to511_rxpkt256to511_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpkt512to1023_rxpkt512to1023_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxpkt512to1023_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxpkt512to1023_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxpkt512to1023;
+	return ret;
+}
+
+sw_error_t
+hppe_rxpkt512to1023_rxpkt512to1023_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpkt1024to1518_rxpkt1024to1518_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxpkt1024to1518_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxpkt1024to1518_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxpkt1024to1518;
+	return ret;
+}
+
+sw_error_t
+hppe_rxpkt1024to1518_rxpkt1024to1518_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxpkt1519tox_rxpkt1519tox_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxpkt1519tox_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxpkt1519tox_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxpkt1519tox;
+	return ret;
+}
+
+sw_error_t
+hppe_rxpkt1519tox_rxpkt1519tox_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxtoolong_rxtoolong_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxtoolong_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxtoolong_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxtoolong;
+	return ret;
+}
+
+sw_error_t
+hppe_rxtoolong_rxtoolong_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxgoodbyte_l_rxgoodbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxgoodbyte_l_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxgoodbyte_l_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxgoodbyte_l;
+	return ret;
+}
+
+sw_error_t
+hppe_rxgoodbyte_l_rxgoodbyte_l_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxgoodbyte_h_rxgoodbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxgoodbyte_h_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxgoodbyte_h_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxgoodbyte_h;
+	return ret;
+}
+
+sw_error_t
+hppe_rxgoodbyte_h_rxgoodbyte_h_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxbadbyte_l_rxbadbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxbadbyte_l_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxbadbyte_l_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxbadbyte_l;
+	return ret;
+}
+
+sw_error_t
+hppe_rxbadbyte_l_rxbadbyte_l_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxbadbyte_h_rxbadbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxbadbyte_h_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxbadbyte_h_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxbadbyte_h;
+	return ret;
+}
+
+sw_error_t
+hppe_rxbadbyte_h_rxbadbyte_h_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rxuni_rxuni_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rxuni_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rxuni_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxuni;
+	return ret;
+}
+
+sw_error_t
+hppe_rxuni_rxuni_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txbroad_txbroad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txbroad_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txbroad_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txbroad;
+	return ret;
+}
+
+sw_error_t
+hppe_txbroad_txbroad_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpause_txpause_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txpause_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txpause_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txpause;
+	return ret;
+}
+
+sw_error_t
+hppe_txpause_txpause_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txmulti_txmulti_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txmulti_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txmulti_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txmulti;
+	return ret;
+}
+
+sw_error_t
+hppe_txmulti_txmulti_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txunderrun_txunderrun_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txunderrun_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txunderrun_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txunderrun;
+	return ret;
+}
+
+sw_error_t
+hppe_txunderrun_txunderrun_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpkt64_txpkt64_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txpkt64_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txpkt64_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txpkt64;
+	return ret;
+}
+
+sw_error_t
+hppe_txpkt64_txpkt64_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpkt65to127_txpkt65to127_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txpkt65to127_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txpkt65to127_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txpkt65to127;
+	return ret;
+}
+
+sw_error_t
+hppe_txpkt65to127_txpkt65to127_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpkt128to255_txpkt128to255_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txpkt128to255_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txpkt128to255_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txpkt128to255;
+	return ret;
+}
+
+sw_error_t
+hppe_txpkt128to255_txpkt128to255_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpkt256to511_txpkt256to511_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txpkt256to511_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txpkt256to511_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txpkt256to511;
+	return ret;
+}
+
+sw_error_t
+hppe_txpkt256to511_txpkt256to511_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpkt512to1023_txpkt512to1023_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txpkt512to1023_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txpkt512to1023_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txpkt512to1023;
+	return ret;
+}
+
+sw_error_t
+hppe_txpkt512to1023_txpkt512to1023_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpkt1024to1518_txpkt1024to1518_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txpkt1024to1518_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txpkt1024to1518_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txpkt1024to1518;
+	return ret;
+}
+
+sw_error_t
+hppe_txpkt1024to1518_txpkt1024to1518_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txpkt1519tox_txpkt1519tox_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txpkt1519tox_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txpkt1519tox_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txpkt1519tox;
+	return ret;
+}
+
+sw_error_t
+hppe_txpkt1519tox_txpkt1519tox_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txbyte_l_txbyte_l_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txbyte_l_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txbyte_l_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txbyte_l;
+	return ret;
+}
+
+sw_error_t
+hppe_txbyte_l_txbyte_l_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txbyte_h_txbyte_h_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txbyte_h_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txbyte_h_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txbyte_h;
+	return ret;
+}
+
+sw_error_t
+hppe_txbyte_h_txbyte_h_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txcollisions_txcollisions_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txcollisions_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txcollisions_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txcollisions;
+	return ret;
+}
+
+sw_error_t
+hppe_txcollisions_txcollisions_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txabortcol_txabortcol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txabortcol_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txabortcol_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txabortcol;
+	return ret;
+}
+
+sw_error_t
+hppe_txabortcol_txabortcol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txmulticol_txmulticol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txmulticol_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txmulticol_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txmulticol;
+	return ret;
+}
+
+sw_error_t
+hppe_txmulticol_txmulticol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txsinglecol_txsinglecol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txsinglecol_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txsinglecol_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txsinglecol;
+	return ret;
+}
+
+sw_error_t
+hppe_txsinglecol_txsinglecol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txexcessivedefer_txexcessivedefer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txexcessivedefer_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txexcessivedefer_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txexcessivedefer;
+	return ret;
+}
+
+sw_error_t
+hppe_txexcessivedefer_txexcessivedefer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txdefer_txdefer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txdefer_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txdefer_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txdefer;
+	return ret;
+}
+
+sw_error_t
+hppe_txdefer_txdefer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txlatecol_txlatecol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txlatecol_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txlatecol_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txlatecol;
+	return ret;
+}
+
+sw_error_t
+hppe_txlatecol_txlatecol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_txuni_txuni_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union txuni_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_txuni_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txuni;
+	return ret;
+}
+
+sw_error_t
+hppe_txuni_txuni_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_mirror.c b/qca-ssdk/src/hsl/hppe/hppe_mirror.c
new file mode 100755
index 0000000..531460a
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_mirror.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_mirror_reg.h"
+#include "hppe_mirror.h"
+
+sw_error_t
+hppe_mirror_analyzer_get(
+		a_uint32_t dev_id,
+		union mirror_analyzer_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + MIRROR_ANALYZER_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_mirror_analyzer_set(
+		a_uint32_t dev_id,
+		union mirror_analyzer_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + MIRROR_ANALYZER_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_port_mirror_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_mirror_u *value)
+{
+	if (index >= PORT_MIRROR_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + PORT_MIRROR_ADDRESS + \
+				index * PORT_MIRROR_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_mirror_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_mirror_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + PORT_MIRROR_ADDRESS + \
+				index * PORT_MIRROR_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mirror_analyzer_in_analyzer_port_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union mirror_analyzer_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mirror_analyzer_get(dev_id, &reg_val);
+	*value = reg_val.bf.in_analyzer_port;
+	return ret;
+}
+
+sw_error_t
+hppe_mirror_analyzer_in_analyzer_port_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union mirror_analyzer_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mirror_analyzer_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.in_analyzer_port = value;
+	ret = hppe_mirror_analyzer_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mirror_analyzer_eg_analyzer_port_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union mirror_analyzer_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mirror_analyzer_get(dev_id, &reg_val);
+	*value = reg_val.bf.eg_analyzer_port;
+	return ret;
+}
+
+sw_error_t
+hppe_mirror_analyzer_eg_analyzer_port_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union mirror_analyzer_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mirror_analyzer_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.eg_analyzer_port = value;
+	ret = hppe_mirror_analyzer_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_mirror_in_mirr_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_mirror_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_mirror_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.in_mirr_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_mirror_in_mirr_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_mirror_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_mirror_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.in_mirr_en = value;
+	ret = hppe_port_mirror_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_mirror_eg_mirr_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_mirror_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_mirror_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.eg_mirr_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_mirror_eg_mirr_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_mirror_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_mirror_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.eg_mirr_en = value;
+	ret = hppe_port_mirror_set(dev_id, index, &reg_val);
+	return ret;
+}
diff --git a/qca-ssdk/src/hsl/hppe/hppe_policer.c b/qca-ssdk/src/hsl/hppe/hppe_policer.c
new file mode 100755
index 0000000..45e8f34
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_policer.c
@@ -0,0 +1,2928 @@
+/*
+ * Copyright (c) 2016-2017, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_policer_reg.h"
+#include "hppe_policer.h"
+
+sw_error_t
+hppe_meter_cmpst_length_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union meter_cmpst_length_reg_u *value)
+{
+	if (index >= METER_CMPST_LENGTH_REG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + METER_CMPST_LENGTH_REG_ADDRESS + \
+				index * METER_CMPST_LENGTH_REG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_meter_cmpst_length_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union meter_cmpst_length_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + METER_CMPST_LENGTH_REG_ADDRESS + \
+				index * METER_CMPST_LENGTH_REG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_pc_drop_bypass_reg_set(
+		a_uint32_t dev_id,
+		union pc_drop_bypass_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + PC_DROP_BYPASS_REG_ADDRESS,
+				value->val);
+}
+
+#ifndef IN_POLICER_MINI
+sw_error_t
+hppe_pc_drop_bypass_reg_get(
+		a_uint32_t dev_id,
+		union pc_drop_bypass_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + PC_DROP_BYPASS_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_pc_spare_reg_get(
+		a_uint32_t dev_id,
+		union pc_spare_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + PC_SPARE_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_pc_spare_reg_set(
+		a_uint32_t dev_id,
+		union pc_spare_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + PC_SPARE_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_time_slot_reg_get(
+		a_uint32_t dev_id,
+		union time_slot_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + TIME_SLOT_REG_ADDRESS,
+				&value->val);
+}
+#endif
+
+sw_error_t
+hppe_time_slot_reg_set(
+		a_uint32_t dev_id,
+		union time_slot_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + TIME_SLOT_REG_ADDRESS,
+				value->val);
+}
+
+#ifndef IN_POLICER_MINI
+sw_error_t
+hppe_pc_dbg_addr_reg_get(
+		a_uint32_t dev_id,
+		union pc_dbg_addr_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + PC_DBG_ADDR_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_pc_dbg_addr_reg_set(
+		a_uint32_t dev_id,
+		union pc_dbg_addr_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + PC_DBG_ADDR_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_pc_dbg_data_reg_get(
+		a_uint32_t dev_id,
+		union pc_dbg_data_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + PC_DBG_DATA_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_pc_dbg_data_reg_set(
+		a_uint32_t dev_id,
+		union pc_dbg_data_reg_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_acl_meter_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IN_ACL_METER_CFG_TBL_ADDRESS + \
+				index * IN_ACL_METER_CFG_TBL_INC,
+				value->val,
+				4);
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_acl_meter_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IN_ACL_METER_CFG_TBL_ADDRESS + \
+				index * IN_ACL_METER_CFG_TBL_INC,
+				value->val,
+				4);
+}
+
+sw_error_t
+hppe_in_acl_meter_crdt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_acl_meter_crdt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IN_ACL_METER_CRDT_TBL_ADDRESS + \
+				index * IN_ACL_METER_CRDT_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_in_acl_meter_crdt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_acl_meter_crdt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IN_ACL_METER_CRDT_TBL_ADDRESS + \
+				index * IN_ACL_METER_CRDT_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_port_meter_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IN_PORT_METER_CFG_TBL_ADDRESS + \
+				index * IN_PORT_METER_CFG_TBL_INC,
+				value->val,
+				4);
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_port_meter_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IN_PORT_METER_CFG_TBL_ADDRESS + \
+				index * IN_PORT_METER_CFG_TBL_INC,
+				value->val,
+				4);
+}
+
+sw_error_t
+hppe_in_port_meter_crdt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_port_meter_crdt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IN_PORT_METER_CRDT_TBL_ADDRESS + \
+				index * IN_PORT_METER_CRDT_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_in_port_meter_crdt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_port_meter_crdt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IN_PORT_METER_CRDT_TBL_ADDRESS + \
+				index * IN_PORT_METER_CRDT_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_in_port_meter_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_port_meter_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IN_PORT_METER_CNT_TBL_ADDRESS + \
+				index * IN_PORT_METER_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_in_port_meter_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_port_meter_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IN_PORT_METER_CNT_TBL_ADDRESS + \
+				index * IN_PORT_METER_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_in_acl_meter_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_acl_meter_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IN_ACL_METER_CNT_TBL_ADDRESS + \
+				index * IN_ACL_METER_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_in_acl_meter_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_acl_meter_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + IN_ACL_METER_CNT_TBL_ADDRESS + \
+				index * IN_ACL_METER_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_pc_global_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pc_global_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + PC_GLOBAL_CNT_TBL_ADDRESS + \
+				index * PC_GLOBAL_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_pc_global_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pc_global_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + PC_GLOBAL_CNT_TBL_ADDRESS + \
+				index * PC_GLOBAL_CNT_TBL_INC,
+				value->val,
+				3);
+}
+#endif
+
+sw_error_t
+hppe_drop_cpu_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union drop_cpu_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + DROP_CPU_CNT_TBL_ADDRESS + \
+				index * DROP_CPU_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_drop_cpu_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union drop_cpu_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + DROP_CPU_CNT_TBL_ADDRESS + \
+				index * DROP_CPU_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_port_tx_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_tx_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + PORT_TX_DROP_CNT_TBL_ADDRESS + \
+				index * PORT_TX_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_port_tx_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_tx_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + PORT_TX_DROP_CNT_TBL_ADDRESS + \
+				index * PORT_TX_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_vp_tx_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vp_tx_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + VP_TX_DROP_CNT_TBL_ADDRESS + \
+				index * VP_TX_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_vp_tx_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vp_tx_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + VP_TX_DROP_CNT_TBL_ADDRESS + \
+				index * VP_TX_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_vlan_dev_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vlan_dev_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + VLAN_DEV_CNT_TBL_ADDRESS + \
+				index * VLAN_DEV_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_vlan_dev_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vlan_dev_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + VLAN_DEV_CNT_TBL_ADDRESS + \
+				index * VLAN_DEV_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+#ifndef IN_POLICER_MINI
+sw_error_t
+hppe_meter_cmpst_length_reg_cmpst_length_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union meter_cmpst_length_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_meter_cmpst_length_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmpst_length;
+	return ret;
+}
+
+sw_error_t
+hppe_meter_cmpst_length_reg_cmpst_length_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union meter_cmpst_length_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_meter_cmpst_length_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmpst_length = value;
+	ret = hppe_meter_cmpst_length_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pc_drop_bypass_reg_drop_bypass_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union pc_drop_bypass_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pc_drop_bypass_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.drop_bypass_en;
+	return ret;
+}
+
+sw_error_t
+hppe_pc_drop_bypass_reg_drop_bypass_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union pc_drop_bypass_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pc_drop_bypass_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.drop_bypass_en = value;
+	ret = hppe_pc_drop_bypass_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pc_spare_reg_spare_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union pc_spare_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pc_spare_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.spare_reg;
+	return ret;
+}
+
+sw_error_t
+hppe_pc_spare_reg_spare_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union pc_spare_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pc_spare_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.spare_reg = value;
+	ret = hppe_pc_spare_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_time_slot_reg_time_slot_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union time_slot_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_time_slot_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.time_slot;
+	return ret;
+}
+
+sw_error_t
+hppe_time_slot_reg_time_slot_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union time_slot_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_time_slot_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.time_slot = value;
+	ret = hppe_time_slot_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pc_dbg_addr_reg_dbg_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union pc_dbg_addr_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pc_dbg_addr_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.dbg_addr;
+	return ret;
+}
+
+sw_error_t
+hppe_pc_dbg_addr_reg_dbg_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union pc_dbg_addr_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pc_dbg_addr_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dbg_addr = value;
+	ret = hppe_pc_dbg_addr_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pc_dbg_data_reg_dbg_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union pc_dbg_data_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pc_dbg_data_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.dbg_data;
+	return ret;
+}
+
+sw_error_t
+hppe_pc_dbg_data_reg_dbg_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_meter_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.meter_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_meter_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.meter_mode = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_color_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.color_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_color_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.color_mode = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_pcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_chg_pcp_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_pcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_chg_pcp_cmd = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_pri;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_pri = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_pri_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_chg_pri_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_pri_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_chg_pri_cmd = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_dp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_dp;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_dp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_dp = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_dp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_dp;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_dp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_dp = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_dei;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_dei = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_pri_1 << 1 | \
+		reg_val.bf.violate_pri_0;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_pri_1 = value >> 1;
+	reg_val.bf.violate_pri_0 = value & (((a_uint64_t)1<<1)-1);
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_cbs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cbs;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_cbs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cbs = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_dei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_chg_dei_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_dei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_chg_dei_cmd = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_pcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_chg_pcp_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_pcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_chg_pcp_cmd = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_cir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cir_1 << 8 | \
+		reg_val.bf.cir_0;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_cir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cir_1 = value >> 8;
+	reg_val.bf.cir_0 = value & (((a_uint64_t)1<<8)-1);
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_dei;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_dei = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_pri_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_chg_pri_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_pri_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_chg_pri_cmd = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_meter_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.meter_unit;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_meter_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.meter_unit = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_meter_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.meter_en;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_meter_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.meter_en = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_cmd = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_dp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_chg_dp_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_chg_dp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_chg_dp_cmd = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_eir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.eir_1 << 6 | \
+		reg_val.bf.eir_0;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_eir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.eir_1 = value >> 6;
+	reg_val.bf.eir_0 = value & (((a_uint64_t)1<<6)-1);
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_dp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_chg_dp_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_dp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_chg_dp_cmd = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_dei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_chg_dei_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_chg_dei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_chg_dei_cmd = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_pcp;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_exceed_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_pcp = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_pcp;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_violate_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_pcp = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_token_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.token_unit;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_token_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.token_unit = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_coupling_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.coupling_flag;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_coupling_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.coupling_flag = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_ebs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ebs;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cfg_tbl_ebs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ebs = value;
+	ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_crdt_tbl_c_crdt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_crdt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_crdt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_crdt;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_crdt_tbl_c_crdt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_crdt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_crdt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.c_crdt = value;
+	ret = hppe_in_acl_meter_crdt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_crdt_tbl_e_crdt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_crdt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_crdt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_crdt;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_crdt_tbl_e_crdt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_crdt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_crdt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.e_crdt = value;
+	ret = hppe_in_acl_meter_crdt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.meter_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.meter_mode = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_color_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.color_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_color_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.color_mode = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_pcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_chg_pcp_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_pcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_chg_pcp_cmd = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_pri;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_pri = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_pri_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_chg_pri_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_pri_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_chg_pri_cmd = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_dp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_dp;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_dp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_dp = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_dp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_dp;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_dp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_dp = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_dei;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_dei = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_pri;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_pri = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_cbs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cbs;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_cbs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cbs = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_dei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_chg_dei_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_dei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_chg_dei_cmd = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_pcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_chg_pcp_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_pcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_chg_pcp_cmd = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_cir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cir_1 << 3 | \
+		reg_val.bf.cir_0;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_cir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cir_1 = value >> 3;
+	reg_val.bf.cir_0 = value & (((a_uint64_t)1<<3)-1);
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_dei;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_dei = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_pri_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_chg_pri_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_pri_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_chg_pri_cmd = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.meter_unit;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.meter_unit = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.meter_en;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.meter_en = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_cmd = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_dp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_chg_dp_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_chg_dp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_chg_dp_cmd = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_eir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.eir_1 << 1 | \
+		reg_val.bf.eir_0;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_eir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.eir_1 = value >> 1;
+	reg_val.bf.eir_0 = value & (((a_uint64_t)1<<1)-1);
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_dp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_chg_dp_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_dp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_chg_dp_cmd = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_dei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_chg_dei_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_chg_dei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_chg_dei_cmd = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.exceed_pcp;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_exceed_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.exceed_pcp = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.violate_pcp;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_violate_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.violate_pcp = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_token_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.token_unit;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_token_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.token_unit = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_coupling_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.coupling_flag;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_coupling_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.coupling_flag = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.meter_flag;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_meter_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.meter_flag = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_ebs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ebs;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cfg_tbl_ebs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ebs = value;
+	ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_crdt_tbl_c_crdt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_crdt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_crdt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_crdt;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_crdt_tbl_c_crdt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_crdt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_crdt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.c_crdt = value;
+	ret = hppe_in_port_meter_crdt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_crdt_tbl_e_crdt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_crdt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_crdt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_crdt;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_crdt_tbl_e_crdt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_crdt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_crdt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.e_crdt = value;
+	ret = hppe_in_port_meter_crdt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cnt_tbl_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union in_port_meter_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.byte_cnt_1 << 32 | \
+		reg_val.bf.byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cnt_tbl_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union in_port_meter_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.byte_cnt_1 = value >> 32;
+	reg_val.bf.byte_cnt_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_in_port_meter_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cnt_tbl_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_port_meter_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_in_port_meter_cnt_tbl_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_port_meter_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_port_meter_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pkt_cnt = value;
+	ret = hppe_in_port_meter_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cnt_tbl_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union in_acl_meter_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.byte_cnt_1 << 32 | \
+		reg_val.bf.byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cnt_tbl_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union in_acl_meter_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.byte_cnt_1 = value >> 32;
+	reg_val.bf.byte_cnt_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_in_acl_meter_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cnt_tbl_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_acl_meter_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_in_acl_meter_cnt_tbl_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_acl_meter_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_acl_meter_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pkt_cnt = value;
+	ret = hppe_in_acl_meter_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pc_global_cnt_tbl_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union pc_global_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pc_global_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.byte_cnt_1 << 32 | \
+		reg_val.bf.byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_pc_global_cnt_tbl_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union pc_global_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pc_global_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.byte_cnt_1 = value >> 32;
+	reg_val.bf.byte_cnt_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_pc_global_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pc_global_cnt_tbl_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pc_global_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pc_global_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_pc_global_cnt_tbl_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pc_global_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pc_global_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pkt_cnt = value;
+	ret = hppe_pc_global_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_drop_cpu_cnt_tbl_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union drop_cpu_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_drop_cpu_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.byte_cnt_1 << 32 | \
+		reg_val.bf.byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_drop_cpu_cnt_tbl_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union drop_cpu_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_drop_cpu_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.byte_cnt_1 = value >> 32;
+	reg_val.bf.byte_cnt_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_drop_cpu_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_drop_cpu_cnt_tbl_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union drop_cpu_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_drop_cpu_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_drop_cpu_cnt_tbl_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union drop_cpu_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_drop_cpu_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pkt_cnt = value;
+	ret = hppe_drop_cpu_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_tx_drop_cnt_tbl_tx_drop_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union port_tx_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_tx_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.tx_drop_byte_cnt_1 << 32 | \
+		reg_val.bf.tx_drop_byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_port_tx_drop_cnt_tbl_tx_drop_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union port_tx_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_tx_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_drop_byte_cnt_1 = value >> 32;
+	reg_val.bf.tx_drop_byte_cnt_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_port_tx_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_tx_drop_cnt_tbl_tx_drop_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_tx_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_tx_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_drop_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_port_tx_drop_cnt_tbl_tx_drop_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_tx_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_tx_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_drop_pkt_cnt = value;
+	ret = hppe_port_tx_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vp_tx_drop_cnt_tbl_tx_drop_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union vp_tx_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vp_tx_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.tx_drop_byte_cnt_1 << 32 | \
+		reg_val.bf.tx_drop_byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_vp_tx_drop_cnt_tbl_tx_drop_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union vp_tx_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vp_tx_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_drop_byte_cnt_1 = value >> 32;
+	reg_val.bf.tx_drop_byte_cnt_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_vp_tx_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vp_tx_drop_cnt_tbl_tx_drop_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vp_tx_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vp_tx_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_drop_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_vp_tx_drop_cnt_tbl_tx_drop_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vp_tx_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vp_tx_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_drop_pkt_cnt = value;
+	ret = hppe_vp_tx_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vlan_dev_cnt_tbl_rx_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union vlan_dev_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_dev_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.rx_byte_cnt_1 << 32 | \
+		reg_val.bf.rx_byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_vlan_dev_cnt_tbl_rx_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union vlan_dev_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_dev_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_byte_cnt_1 = value >> 32;
+	reg_val.bf.rx_byte_cnt_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_vlan_dev_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vlan_dev_cnt_tbl_rx_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vlan_dev_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_dev_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_vlan_dev_cnt_tbl_rx_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vlan_dev_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_dev_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_pkt_cnt = value;
+	ret = hppe_vlan_dev_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
diff --git a/qca-ssdk/src/hsl/hppe/hppe_portctrl.c b/qca-ssdk/src/hsl/hppe/hppe_portctrl.c
new file mode 100755
index 0000000..3771da9
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_portctrl.c
@@ -0,0 +1,3441 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_portctrl_reg.h"
+#include "hppe_portctrl.h"
+
+sw_error_t
+hppe_mac_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_enable_u *value)
+{
+	if (index >= MAC_ENABLE_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_ENABLE_ADDRESS + \
+				index * MAC_ENABLE_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_enable_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_ENABLE_ADDRESS + \
+				index * MAC_ENABLE_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_speed_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_speed_u *value)
+{
+	if (index >= MAC_SPEED_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_SPEED_ADDRESS + \
+				index * MAC_SPEED_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_speed_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_speed_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_SPEED_ADDRESS + \
+				index * MAC_SPEED_INC,
+				value->val);
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+hppe_gol_mac_addr0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union gol_mac_addr0_u *value)
+{
+	if (index >= GOL_MAC_ADDR0_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + GOL_MAC_ADDR0_ADDRESS + \
+				index * GOL_MAC_ADDR0_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_gol_mac_addr0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union gol_mac_addr0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + GOL_MAC_ADDR0_ADDRESS + \
+				index * GOL_MAC_ADDR0_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_gol_mac_addr1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union gol_mac_addr1_u *value)
+{
+	if (index >= GOL_MAC_ADDR1_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + GOL_MAC_ADDR1_ADDRESS + \
+				index * GOL_MAC_ADDR1_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_gol_mac_addr1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union gol_mac_addr1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + GOL_MAC_ADDR1_ADDRESS + \
+				index * GOL_MAC_ADDR1_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_ctrl0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_ctrl0_u *value)
+{
+	if (index >= MAC_CTRL0_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_CTRL0_ADDRESS + \
+				index * MAC_CTRL0_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_ctrl0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_ctrl0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_CTRL0_ADDRESS + \
+				index * MAC_CTRL0_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_ctrl1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_ctrl1_u *value)
+{
+	if (index >= MAC_CTRL1_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_CTRL1_ADDRESS + \
+				index * MAC_CTRL1_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_ctrl1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_ctrl1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_CTRL1_ADDRESS + \
+				index * MAC_CTRL1_INC,
+				value->val);
+}
+#endif
+sw_error_t
+hppe_mac_ctrl2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_ctrl2_u *value)
+{
+	if (index >= MAC_CTRL2_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_CTRL2_ADDRESS + \
+				index * MAC_CTRL2_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_ctrl2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_ctrl2_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_CTRL2_ADDRESS + \
+				index * MAC_CTRL2_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_dbg_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_dbg_ctrl_u *value)
+{
+	if (index >= MAC_DBG_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_DBG_CTRL_ADDRESS + \
+				index * MAC_DBG_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_dbg_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_dbg_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_DBG_CTRL_ADDRESS + \
+				index * MAC_DBG_CTRL_INC,
+				value->val);
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+hppe_mac_dbg_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_dbg_addr_u *value)
+{
+	if (index >= MAC_DBG_ADDR_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_DBG_ADDR_ADDRESS + \
+				index * MAC_DBG_ADDR_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_dbg_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_dbg_addr_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_DBG_ADDR_ADDRESS + \
+				index * MAC_DBG_ADDR_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_dbg_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_dbg_data_u *value)
+{
+	if (index >= MAC_DBG_DATA_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_DBG_DATA_ADDRESS + \
+				index * MAC_DBG_DATA_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_dbg_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_dbg_data_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
+
+sw_error_t
+hppe_mac_jumbo_size_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_jumbo_size_u *value)
+{
+	if (index >= MAC_JUMBO_SIZE_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_JUMBO_SIZE_ADDRESS + \
+				index * MAC_JUMBO_SIZE_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_jumbo_size_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_jumbo_size_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_MAC_CSR_BASE_ADDR + MAC_JUMBO_SIZE_ADDRESS + \
+				index * MAC_JUMBO_SIZE_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mru_mtu_ctrl_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + MRU_MTU_CTRL_TBL_ADDRESS + \
+				index * MRU_MTU_CTRL_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mru_mtu_ctrl_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + MRU_MTU_CTRL_TBL_ADDRESS + \
+				index * MRU_MTU_CTRL_TBL_INC,
+				value->val,
+				2);
+}
+
+#if ((!defined(IN_PORTCONTROL_MINI)) || (!defined(IN_MISC_MINI)))
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mc_mtu_ctrl_tbl_u *value)
+{
+	if (index >= MC_MTU_CTRL_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + MC_MTU_CTRL_TBL_ADDRESS + \
+				index * MC_MTU_CTRL_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mc_mtu_ctrl_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + MC_MTU_CTRL_TBL_ADDRESS + \
+				index * MC_MTU_CTRL_TBL_INC,
+				value->val);
+}
+#endif
+
+sw_error_t
+hppe_tdm_ctrl_get(
+		a_uint32_t dev_id,
+		union tdm_ctrl_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_PRX_CSR_BASE_ADDR + TDM_CTRL_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_tdm_ctrl_set(
+		a_uint32_t dev_id,
+		union tdm_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_PRX_CSR_BASE_ADDR + TDM_CTRL_ADDRESS,
+				value->val);
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+hppe_rx_fifo_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_fifo_cfg_u *value)
+{
+	if (index >= RX_FIFO_CFG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_PRX_CSR_BASE_ADDR + RX_FIFO_CFG_ADDRESS + \
+				index * RX_FIFO_CFG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_fifo_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_fifo_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_PRX_CSR_BASE_ADDR + RX_FIFO_CFG_ADDRESS + \
+				index * RX_FIFO_CFG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_tdm_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tdm_cfg_u *value)
+{
+	if (index >= TDM_CFG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_PRX_CSR_BASE_ADDR + TDM_CFG_ADDRESS + \
+				index * TDM_CFG_INC,
+				&value->val);
+}
+#endif
+
+sw_error_t
+hppe_tdm_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tdm_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_PRX_CSR_BASE_ADDR + TDM_CFG_ADDRESS + \
+				index * TDM_CFG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_drop_stat_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union drop_stat_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				NSS_PRX_CSR_BASE_ADDR + DROP_STAT_ADDRESS + \
+				index * DROP_STAT_INC,
+				value->val,
+				3);
+}
+
+#ifndef IN_MISC_MINI
+sw_error_t
+hppe_drop_stat_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union drop_stat_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				NSS_PRX_CSR_BASE_ADDR + DROP_STAT_ADDRESS + \
+				index * DROP_STAT_INC,
+				value->val,
+				3);
+}
+#endif
+
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+hppe_mac_enable_txmac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txmac_en;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_enable_txmac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_enable_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.txmac_en = value;
+	ret = hppe_mac_enable_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_enable_rxmac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxmac_en;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_enable_rxmac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_enable_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rxmac_en = value;
+	ret = hppe_mac_enable_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_enable_tx_flow_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_flow_en;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_enable_tx_flow_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_enable_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_flow_en = value;
+	ret = hppe_mac_enable_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_enable_rx_flow_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_flow_en;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_enable_rx_flow_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_enable_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_flow_en = value;
+	ret = hppe_mac_enable_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_enable_duplex_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.duplex;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_enable_duplex_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_enable_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.duplex = value;
+	ret = hppe_mac_enable_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_speed_mac_speed_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_speed_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_speed_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_speed;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_speed_mac_speed_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_speed_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_speed_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_speed = value;
+	ret = hppe_mac_speed_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_gol_mac_addr0_mac_addr_byte4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union gol_mac_addr0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_gol_mac_addr0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_addr_byte4;
+	return ret;
+}
+
+sw_error_t
+hppe_gol_mac_addr0_mac_addr_byte4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union gol_mac_addr0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_gol_mac_addr0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr_byte4 = value;
+	ret = hppe_gol_mac_addr0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_gol_mac_addr0_mac_addr_byte5_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union gol_mac_addr0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_gol_mac_addr0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_addr_byte5;
+	return ret;
+}
+
+sw_error_t
+hppe_gol_mac_addr0_mac_addr_byte5_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union gol_mac_addr0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_gol_mac_addr0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr_byte5 = value;
+	ret = hppe_gol_mac_addr0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union gol_mac_addr1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_gol_mac_addr1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_addr_byte1;
+	return ret;
+}
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union gol_mac_addr1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_gol_mac_addr1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr_byte1 = value;
+	ret = hppe_gol_mac_addr1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union gol_mac_addr1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_gol_mac_addr1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_addr_byte2;
+	return ret;
+}
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union gol_mac_addr1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_gol_mac_addr1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr_byte2 = value;
+	ret = hppe_gol_mac_addr1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union gol_mac_addr1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_gol_mac_addr1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_addr_byte0;
+	return ret;
+}
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union gol_mac_addr1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_gol_mac_addr1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr_byte0 = value;
+	ret = hppe_gol_mac_addr1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte3_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union gol_mac_addr1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_gol_mac_addr1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_addr_byte3;
+	return ret;
+}
+
+sw_error_t
+hppe_gol_mac_addr1_mac_addr_byte3_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union gol_mac_addr1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_gol_mac_addr1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr_byte3 = value;
+	ret = hppe_gol_mac_addr1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_amaxc_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.amaxc_en;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_amaxc_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.amaxc_en = value;
+	ret = hppe_mac_ctrl0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_ipgt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipgt;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_ipgt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipgt = value;
+	ret = hppe_mac_ctrl0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_nobo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.nobo;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_nobo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.nobo = value;
+	ret = hppe_mac_ctrl0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_half_thdf_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.half_thdf_ctrl;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_half_thdf_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.half_thdf_ctrl = value;
+	ret = hppe_mac_ctrl0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_hugen_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.hugen;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_hugen_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hugen = value;
+	ret = hppe_mac_ctrl0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_bpnb_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.bpnb;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_bpnb_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.bpnb = value;
+	ret = hppe_mac_ctrl0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_flchk_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flchk;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_flchk_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flchk = value;
+	ret = hppe_mac_ctrl0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_ipgr2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipgr2;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_ipgr2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipgr2 = value;
+	ret = hppe_mac_ctrl0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_drbnib_rxok_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.drbnib_rxok_en;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_drbnib_rxok_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.drbnib_rxok_en = value;
+	ret = hppe_mac_ctrl0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_huge_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.huge;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_huge_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.huge = value;
+	ret = hppe_mac_ctrl0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_abebe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.abebe;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl0_abebe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.abebe = value;
+	ret = hppe_mac_ctrl0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_povr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.povr;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_povr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.povr = value;
+	ret = hppe_mac_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_simr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.simr;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_simr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.simr = value;
+	ret = hppe_mac_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_jam_ipg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.jam_ipg;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_jam_ipg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.jam_ipg = value;
+	ret = hppe_mac_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_lcol_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lcol;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_lcol_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.lcol = value;
+	ret = hppe_mac_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_tctl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tctl;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_tctl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tctl = value;
+	ret = hppe_mac_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_retry_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.retry;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_retry_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.retry = value;
+	ret = hppe_mac_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_prlen_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.prlen;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_prlen_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.prlen = value;
+	ret = hppe_mac_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_ppad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ppad;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_ppad_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ppad = value;
+	ret = hppe_mac_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_long_jam_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.long_jam_en;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_long_jam_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.long_jam_en = value;
+	ret = hppe_mac_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_phug_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.phug;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_phug_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.phug = value;
+	ret = hppe_mac_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_sstct_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.sstct;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_sstct_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.sstct = value;
+	ret = hppe_mac_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_mbof_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mbof;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_mbof_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mbof = value;
+	ret = hppe_mac_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_tpause_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tpause;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl1_tpause_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tpause = value;
+	ret = hppe_mac_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl2_ipg_dec_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipg_dec_en;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl2_ipg_dec_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipg_dec_en = value;
+	ret = hppe_mac_ctrl2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl2_mac_rsv_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_rsv;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl2_mac_rsv_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_rsv = value;
+	ret = hppe_mac_ctrl2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl2_mac_tx_thd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_tx_thd;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_mac_ctrl2_mac_tx_thd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_tx_thd = value;
+	ret = hppe_mac_ctrl2_set(dev_id, index, &reg_val);
+	return ret;
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+hppe_mac_ctrl2_crc_rsv_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.crc_rsv_en;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl2_crc_rsv_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.crc_rsv_en = value;
+	ret = hppe_mac_ctrl2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl2_crs_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.crs_sel;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_mac_ctrl2_crs_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.crs_sel = value;
+	ret = hppe_mac_ctrl2_set(dev_id, index, &reg_val);
+	return ret;
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+hppe_mac_ctrl2_ipg_dec_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipg_dec_len;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl2_ipg_dec_len_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipg_dec_len = value;
+	ret = hppe_mac_ctrl2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl2_maxfr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.maxfr;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_mac_ctrl2_maxfr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.maxfr = value;
+	ret = hppe_mac_ctrl2_set(dev_id, index, &reg_val);
+	return ret;
+}
+#ifndef IN_PORTCONTROL_MINI
+
+sw_error_t
+hppe_mac_ctrl2_mac_lpi_tx_idle_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_lpi_tx_idle;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl2_mac_lpi_tx_idle_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_lpi_tx_idle = value;
+	ret = hppe_mac_ctrl2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl2_mac_loop_back_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_loop_back;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl2_mac_loop_back_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_loop_back = value;
+	ret = hppe_mac_ctrl2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl2_test_pause_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.test_pause;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_ctrl2_test_pause_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_ctrl2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_ctrl2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.test_pause = value;
+	ret = hppe_mac_ctrl2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_dbg_ctrl_edxsdfr_transmit_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_dbg_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_dbg_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.edxsdfr_transmit_en;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_dbg_ctrl_edxsdfr_transmit_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_dbg_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_dbg_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.edxsdfr_transmit_en = value;
+	ret = hppe_mac_dbg_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_dbg_ctrl_hihg_ipg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_dbg_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_dbg_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.hihg_ipg;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_mac_dbg_ctrl_hihg_ipg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_dbg_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_dbg_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hihg_ipg = value;
+	ret = hppe_mac_dbg_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+hppe_mac_dbg_ctrl_mac_ipg_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_dbg_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_dbg_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_ipg_ctrl;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_dbg_ctrl_mac_ipg_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_dbg_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_dbg_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_ipg_ctrl = value;
+	ret = hppe_mac_dbg_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_dbg_ctrl_mac_len_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_dbg_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_dbg_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_len_ctrl;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_dbg_ctrl_mac_len_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_dbg_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_dbg_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_len_ctrl = value;
+	ret = hppe_mac_dbg_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_dbg_ctrl_ipgr1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_dbg_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_dbg_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipgr1;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_dbg_ctrl_ipgr1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_dbg_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_dbg_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipgr1 = value;
+	ret = hppe_mac_dbg_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_dbg_addr_mac_debug_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_dbg_addr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_dbg_addr_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_debug_addr;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_dbg_addr_mac_debug_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_dbg_addr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_dbg_addr_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_debug_addr = value;
+	ret = hppe_mac_dbg_addr_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_dbg_data_mac_debug_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_dbg_data_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_dbg_data_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_debug_data;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_dbg_data_mac_debug_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
+sw_error_t
+hppe_mac_jumbo_size_mac_jumbo_size_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_jumbo_size_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_jumbo_size_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mac_jumbo_size;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_jumbo_size_mac_jumbo_size_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_jumbo_size_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_jumbo_size_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_jumbo_size = value;
+	ret = hppe_mac_jumbo_size_set(dev_id, index, &reg_val);
+	return ret;
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_mtu_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mtu_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_mtu_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mtu_cmd = value;
+	ret = hppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_rx_cnt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_cnt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_rx_cnt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_cnt_en = value;
+	ret = hppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_tx_cnt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_cnt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_tx_cnt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_cnt_en = value;
+	ret = hppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_mru_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mru_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_mru_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mru_cmd = value;
+	ret = hppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_mru_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mru;
+	return ret;
+}
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_mru_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mru = value;
+	ret = hppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_src_profile_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.src_profile;
+	return ret;
+}
+
+sw_error_t
+hppe_mru_mtu_ctrl_tbl_src_profile_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mru_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.src_profile = value;
+	ret = hppe_mru_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_mtu_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mc_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mc_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mtu_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_mtu_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mc_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mc_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mtu_cmd = value;
+	ret = hppe_mc_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_tx_cnt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mc_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mc_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_cnt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_tx_cnt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mc_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mc_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_cnt_en = value;
+	ret = hppe_mc_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_mtu_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mc_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mc_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mtu;
+	return ret;
+}
+
+sw_error_t
+hppe_mc_mtu_ctrl_tbl_mtu_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mc_mtu_ctrl_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mc_mtu_ctrl_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mtu = value;
+	ret = hppe_mc_mtu_ctrl_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_tdm_ctrl_tdm_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union tdm_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tdm_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.tdm_en;
+	return ret;
+}
+
+sw_error_t
+hppe_tdm_ctrl_tdm_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union tdm_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tdm_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tdm_en = value;
+	ret = hppe_tdm_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_tdm_ctrl_tdm_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union tdm_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tdm_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.tdm_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_tdm_ctrl_tdm_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union tdm_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tdm_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tdm_offset = value;
+	ret = hppe_tdm_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_tdm_ctrl_tdm_depth_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union tdm_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tdm_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.tdm_depth;
+	return ret;
+}
+
+sw_error_t
+hppe_tdm_ctrl_tdm_depth_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union tdm_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tdm_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tdm_depth = value;
+	ret = hppe_tdm_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rx_fifo_cfg_rx_fifo_thres_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_fifo_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_fifo_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_fifo_thres;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_fifo_cfg_rx_fifo_thres_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rx_fifo_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_fifo_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_fifo_thres = value;
+	ret = hppe_rx_fifo_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_tdm_cfg_port_num_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tdm_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tdm_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_num;
+	return ret;
+}
+
+sw_error_t
+hppe_tdm_cfg_port_num_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union tdm_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tdm_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_num = value;
+	ret = hppe_tdm_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_tdm_cfg_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tdm_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tdm_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.valid;
+	return ret;
+}
+
+sw_error_t
+hppe_tdm_cfg_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union tdm_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tdm_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.valid = value;
+	ret = hppe_tdm_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_tdm_cfg_dir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tdm_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tdm_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dir;
+	return ret;
+}
+
+sw_error_t
+hppe_tdm_cfg_dir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union tdm_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tdm_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dir = value;
+	ret = hppe_tdm_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
+sw_error_t
+hppe_port_in_forward_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_in_forward_u *value)
+{
+	if (index >= PORT_IN_FORWARD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + PORT_IN_FORWARD_ADDRESS + \
+				index * PORT_IN_FORWARD_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_in_forward_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_in_forward_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + PORT_IN_FORWARD_ADDRESS + \
+				index * PORT_IN_FORWARD_INC,
+				value->val);
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+hppe_port_in_forward_source_filtering_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_in_forward_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_in_forward_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.source_filtering_bypass;
+	return ret;
+}
+
+sw_error_t
+hppe_port_in_forward_source_filtering_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_in_forward_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_in_forward_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.source_filtering_bypass = value;
+	ret = hppe_port_in_forward_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
+
+#ifndef IN_MISC_MINI
+sw_error_t
+hppe_drop_stat_bytes_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union drop_stat_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_drop_stat_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.bytes_1 << 32 | \
+		reg_val.bf.bytes_0;
+	return ret;
+}
+
+sw_error_t
+hppe_drop_stat_bytes_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union drop_stat_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_drop_stat_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.bytes_1 = value >> 32;
+	reg_val.bf.bytes_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_drop_stat_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_drop_stat_pkts_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union drop_stat_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_drop_stat_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pkts;
+	return ret;
+}
+
+sw_error_t
+hppe_drop_stat_pkts_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union drop_stat_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_drop_stat_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pkts = value;
+	ret = hppe_drop_stat_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
+
+#if ((!defined(IN_PORTCONTROL_MINI)) || (!defined(IN_MISC_MINI)))
+sw_error_t
+hppe_port_tx_counter_tbl_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_tx_counter_tbl_reg_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + PORT_TX_COUNTER_TBL_REG_ADDRESS + \
+				index * PORT_TX_COUNTER_TBL_REG_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_port_tx_counter_tbl_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_tx_counter_tbl_reg_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + PORT_TX_COUNTER_TBL_REG_ADDRESS + \
+				index * PORT_TX_COUNTER_TBL_REG_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_vp_tx_counter_tbl_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vp_tx_counter_tbl_reg_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + VP_TX_COUNTER_TBL_REG_ADDRESS + \
+				index * VP_TX_COUNTER_TBL_REG_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_vp_tx_counter_tbl_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vp_tx_counter_tbl_reg_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + VP_TX_COUNTER_TBL_REG_ADDRESS + \
+				index * VP_TX_COUNTER_TBL_REG_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_epe_dbg_in_cnt_reg_get(
+		a_uint32_t dev_id,
+		union epe_dbg_in_cnt_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EPE_DBG_IN_CNT_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_epe_dbg_in_cnt_reg_set(
+		a_uint32_t dev_id,
+		union epe_dbg_in_cnt_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EPE_DBG_IN_CNT_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_epe_dbg_out_cnt_reg_set(
+		a_uint32_t dev_id,
+		union epe_dbg_out_cnt_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EPE_DBG_OUT_CNT_REG_ADDRESS,
+				value->val);
+}
+#endif
+
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+hppe_epe_dbg_out_cnt_reg_get(
+		a_uint32_t dev_id,
+		union epe_dbg_out_cnt_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EPE_DBG_OUT_CNT_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_tx_counter_tbl_reg_tx_bytes_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union port_tx_counter_tbl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_tx_counter_tbl_reg_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.tx_bytes_1 << 32 | \
+		reg_val.bf.tx_bytes_0;
+	return ret;
+}
+
+sw_error_t
+hppe_port_tx_counter_tbl_reg_tx_bytes_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union port_tx_counter_tbl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_tx_counter_tbl_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_bytes_1 = value >> 32;
+	reg_val.bf.tx_bytes_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_port_tx_counter_tbl_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_tx_counter_tbl_reg_tx_packets_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_tx_counter_tbl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_tx_counter_tbl_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_packets;
+	return ret;
+}
+
+sw_error_t
+hppe_port_tx_counter_tbl_reg_tx_packets_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_tx_counter_tbl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_tx_counter_tbl_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_packets = value;
+	ret = hppe_port_tx_counter_tbl_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vp_tx_counter_tbl_reg_tx_bytes_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union vp_tx_counter_tbl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vp_tx_counter_tbl_reg_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.tx_bytes_1 << 32 | \
+		reg_val.bf.tx_bytes_0;
+	return ret;
+}
+
+sw_error_t
+hppe_vp_tx_counter_tbl_reg_tx_bytes_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union vp_tx_counter_tbl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vp_tx_counter_tbl_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_bytes_1 = value >> 32;
+	reg_val.bf.tx_bytes_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_vp_tx_counter_tbl_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vp_tx_counter_tbl_reg_tx_packets_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vp_tx_counter_tbl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vp_tx_counter_tbl_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_packets;
+	return ret;
+}
+
+sw_error_t
+hppe_vp_tx_counter_tbl_reg_tx_packets_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vp_tx_counter_tbl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vp_tx_counter_tbl_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_packets = value;
+	ret = hppe_vp_tx_counter_tbl_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_epe_dbg_in_cnt_reg_counter_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union epe_dbg_in_cnt_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_epe_dbg_in_cnt_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.counter;
+	return ret;
+}
+
+sw_error_t
+hppe_epe_dbg_in_cnt_reg_counter_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union epe_dbg_in_cnt_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_epe_dbg_in_cnt_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.counter = value;
+	ret = hppe_epe_dbg_in_cnt_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_epe_dbg_out_cnt_reg_counter_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union epe_dbg_out_cnt_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_epe_dbg_out_cnt_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.counter;
+	return ret;
+}
+
+sw_error_t
+hppe_epe_dbg_out_cnt_reg_counter_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union epe_dbg_out_cnt_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_epe_dbg_out_cnt_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.counter = value;
+	ret = hppe_epe_dbg_out_cnt_reg_set(dev_id, &reg_val);
+	return ret;
+}
+#endif
+
+sw_error_t
+hppe_lpi_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_enable_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_LPI_BASE_ADDR + LPI_ENABLE_ADDRESS + \
+				index * LPI_ENABLE_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_lpi_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_enable_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_LPI_BASE_ADDR + LPI_ENABLE_ADDRESS + \
+				index * LPI_ENABLE_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_lpi_timer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_port_timer_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_LPI_BASE_ADDR + LPI_PORT_TIMER_ADDRESS + \
+				index * LPI_PORT_TIMER_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_lpi_timer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_port_timer_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_LPI_BASE_ADDR + LPI_PORT_TIMER_ADDRESS + \
+				index * LPI_PORT_TIMER_INC,
+				value->val);
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+hppe_lpi_dbg_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_dbg_addr_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_LPI_BASE_ADDR + LPI_DBG_ADDR_ADDRESS + \
+				index * LPI_DBG_ADDR_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_lpi_dbg_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_dbg_addr_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_LPI_BASE_ADDR + LPI_DBG_ADDR_ADDRESS + \
+				index * LPI_DBG_ADDR_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_lpi_dbg_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_dbg_data_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_LPI_BASE_ADDR + LPI_DBG_DATA_ADDRESS + \
+				index * LPI_DBG_DATA_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_lpi_dbg_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_dbg_addr_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_LPI_BASE_ADDR + LPI_DBG_DATA_ADDRESS + \
+				index * LPI_DBG_DATA_INC,
+				value->val);
+}
+sw_error_t
+hppe_lpi_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_cnt_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_LPI_BASE_ADDR + LPI_CNT_ADDRESS + \
+				index * LPI_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_lpi_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union lpi_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_LPI_BASE_ADDR + LPI_CNT_ADDRESS + \
+				index * LPI_CNT_INC,
+				value->val);
+}
+#endif
+
+#ifndef IN_MISC_MINI
+sw_error_t
+hppe_drop_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union drop_cnt_u *value)
+{
+	if (index >= DROP_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_PRX_CSR_BASE_ADDR + DROP_CNT_ADDRESS + \
+				index * DROP_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_drop_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union drop_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_PRX_CSR_BASE_ADDR + DROP_CNT_ADDRESS + \
+				index * DROP_CNT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_drop_cnt_drop_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union drop_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_drop_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.drop_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_drop_cnt_drop_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union drop_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_drop_cnt_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.drop_cnt = value;
+	ret = hppe_drop_cnt_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipr_pkt_num_tbl_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipr_pkt_num_tbl_reg_u *value)
+{
+	if (index >= IPR_PKT_NUM_TBL_REG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPR_PKT_NUM_TBL_REG_ADDRESS + \
+				index * IPR_PKT_NUM_TBL_REG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipr_pkt_num_tbl_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipr_pkt_num_tbl_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPR_PKT_NUM_TBL_REG_ADDRESS + \
+				index * IPR_PKT_NUM_TBL_REG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_ipr_byte_low_reg_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipr_byte_low_reg_reg_u *value)
+{
+	if (index >= IPR_BYTE_LOW_REG_REG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPR_BYTE_LOW_REG_REG_ADDRESS + \
+				index * IPR_BYTE_LOW_REG_REG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipr_byte_low_reg_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipr_byte_low_reg_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPR_BYTE_LOW_REG_REG_ADDRESS + \
+				index * IPR_BYTE_LOW_REG_REG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_ipr_byte_high_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipr_byte_high_reg_u *value)
+{
+	if (index >= IPR_BYTE_HIGH_REG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPR_BYTE_HIGH_REG_ADDRESS + \
+				index * IPR_BYTE_HIGH_REG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipr_byte_high_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ipr_byte_high_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + IPR_BYTE_HIGH_REG_ADDRESS + \
+				index * IPR_BYTE_HIGH_REG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_ipr_pkt_num_tbl_reg_packets_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipr_pkt_num_tbl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipr_pkt_num_tbl_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.packets;
+	return ret;
+}
+
+sw_error_t
+hppe_ipr_pkt_num_tbl_reg_packets_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipr_pkt_num_tbl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipr_pkt_num_tbl_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.packets = value;
+	ret = hppe_ipr_pkt_num_tbl_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipr_byte_low_reg_reg_bytes_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipr_byte_low_reg_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipr_byte_low_reg_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.bytes;
+	return ret;
+}
+
+sw_error_t
+hppe_ipr_byte_low_reg_reg_bytes_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipr_byte_low_reg_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipr_byte_low_reg_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.bytes = value;
+	ret = hppe_ipr_byte_low_reg_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ipr_byte_high_reg_bytes_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ipr_byte_high_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipr_byte_high_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.bytes;
+	return ret;
+}
+
+sw_error_t
+hppe_ipr_byte_high_reg_bytes_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ipr_byte_high_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipr_byte_high_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.bytes = value;
+	ret = hppe_ipr_byte_high_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_portvlan.c b/qca-ssdk/src/hsl/hppe/hppe_portvlan.c
new file mode 100755
index 0000000..d38b782
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_portvlan.c
@@ -0,0 +1,4108 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_portvlan_reg.h"
+#include "hppe_portvlan.h"
+
+sw_error_t
+hppe_port_parsing_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_parsing_reg_u *value)
+{
+	if (index >= PORT_PARSING_REG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + PORT_PARSING_REG_ADDRESS + \
+				index * PORT_PARSING_REG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_parsing_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_parsing_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + PORT_PARSING_REG_ADDRESS + \
+				index * PORT_PARSING_REG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_edma_vlan_tpid_reg_get(
+		a_uint32_t dev_id,
+		union edma_vlan_tpid_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				EDMA_CSR_BASE_ADDR + EDMA_VLAN_TPID_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_edma_vlan_tpid_reg_set(
+		a_uint32_t dev_id,
+		union edma_vlan_tpid_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				EDMA_CSR_BASE_ADDR + EDMA_VLAN_TPID_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_vlan_tpid_reg_get(
+		a_uint32_t dev_id,
+		union vlan_tpid_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + VLAN_TPID_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_vlan_tpid_reg_set(
+		a_uint32_t dev_id,
+		union vlan_tpid_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + VLAN_TPID_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_port_parsing_reg_port_role_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_parsing_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_parsing_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_role;
+	return ret;
+}
+
+sw_error_t
+hppe_port_parsing_reg_port_role_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_parsing_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_parsing_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_role = value;
+	ret = hppe_port_parsing_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vlan_tpid_reg_stag_tpid_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union vlan_tpid_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_tpid_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.stag_tpid;
+	return ret;
+}
+
+sw_error_t
+hppe_vlan_tpid_reg_stag_tpid_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union vlan_tpid_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_tpid_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.stag_tpid = value;
+	ret = hppe_vlan_tpid_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vlan_tpid_reg_ctag_tpid_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union vlan_tpid_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_tpid_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.ctag_tpid;
+	return ret;
+}
+
+sw_error_t
+hppe_vlan_tpid_reg_ctag_tpid_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union vlan_tpid_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_tpid_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ctag_tpid = value;
+	ret = hppe_vlan_tpid_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_bridge_config_get(
+		a_uint32_t dev_id,
+		union bridge_config_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + BRIDGE_CONFIG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_bridge_config_set(
+		a_uint32_t dev_id,
+		union bridge_config_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + BRIDGE_CONFIG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_port_def_vid_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		union port_def_vid_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + PORT_DEF_VID_ADDRESS +
+				port_id * PORT_DEF_VID_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_def_vid_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		union port_def_vid_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + PORT_DEF_VID_ADDRESS +
+				port_id * PORT_DEF_VID_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_port_def_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		union port_def_pcp_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + PORT_DEF_PCP_ADDRESS +
+				port_id * PORT_DEF_PCP_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_def_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		union port_def_pcp_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + PORT_DEF_PCP_ADDRESS +
+				port_id * PORT_DEF_PCP_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_port_vlan_config_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		union port_vlan_config_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + PORT_VLAN_CONFIG_ADDRESS +
+				port_id * PORT_VLAN_CONFIG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_vlan_config_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		union port_vlan_config_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + PORT_VLAN_CONFIG_ADDRESS +
+				port_id * PORT_VLAN_CONFIG_INC,
+				value->val);
+}
+
+#ifndef IN_PORTVLAN_MINI
+sw_error_t
+hppe_iv_dbg_addr_get(
+		a_uint32_t dev_id,
+		union iv_dbg_addr_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + IV_DBG_ADDR_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_iv_dbg_addr_set(
+		a_uint32_t dev_id,
+		union iv_dbg_addr_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + IV_DBG_ADDR_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_iv_dbg_data_get(
+		a_uint32_t dev_id,
+		union iv_dbg_data_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + IV_DBG_DATA_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_iv_dbg_data_set(
+		a_uint32_t dev_id,
+		union iv_dbg_data_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_eco_reserve_get(
+		a_uint32_t dev_id,
+		union eco_reserve_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + ECO_RESERVE_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_eco_reserve_set(
+		a_uint32_t dev_id,
+		union eco_reserve_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + ECO_RESERVE_ADDRESS,
+				value->val);
+}
+#endif
+
+sw_error_t
+hppe_xlt_rule_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union xlt_rule_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + XLT_RULE_TBL_ADDRESS + \
+				index * XLT_RULE_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union xlt_rule_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + XLT_RULE_TBL_ADDRESS + \
+				index * XLT_RULE_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_xlt_action_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union xlt_action_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + XLT_ACTION_TBL_ADDRESS + \
+				index * XLT_ACTION_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_xlt_action_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union xlt_action_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + XLT_ACTION_TBL_ADDRESS + \
+				index * XLT_ACTION_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_bridge_config_bridge_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union bridge_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_bridge_config_get(dev_id, &reg_val);
+	*value = reg_val.bf.bridge_type;
+	return ret;
+}
+
+sw_error_t
+hppe_bridge_config_bridge_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union bridge_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_bridge_config_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.bridge_type = value;
+	ret = hppe_bridge_config_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_vid_port_def_cvid_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t *value)
+{
+	union port_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_vid_get(dev_id, port_id, &reg_val);
+	*value = reg_val.bf.port_def_cvid_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_vid_port_def_cvid_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t value)
+{
+	union port_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_vid_get(dev_id, port_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_def_cvid_en = value;
+	ret = hppe_port_def_vid_set(dev_id, port_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_vid_port_def_svid_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t *value)
+{
+	union port_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_vid_get(dev_id, port_id, &reg_val);
+	*value = reg_val.bf.port_def_svid_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_vid_port_def_svid_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t value)
+{
+	union port_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_vid_get(dev_id, port_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_def_svid_en = value;
+	ret = hppe_port_def_vid_set(dev_id, port_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_vid_port_def_cvid_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t *value)
+{
+	union port_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_vid_get(dev_id, port_id, &reg_val);
+	*value = reg_val.bf.port_def_cvid;
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_vid_port_def_cvid_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t value)
+{
+	union port_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_vid_get(dev_id, port_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_def_cvid = value;
+	ret = hppe_port_def_vid_set(dev_id, port_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_vid_port_def_svid_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t *value)
+{
+	union port_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_vid_get(dev_id, port_id, &reg_val);
+	*value = reg_val.bf.port_def_svid;
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_vid_port_def_svid_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t value)
+{
+	union port_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_vid_get(dev_id, port_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_def_svid = value;
+	ret = hppe_port_def_vid_set(dev_id, port_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_pcp_port_def_sdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t *value)
+{
+	union port_def_pcp_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_pcp_get(dev_id, port_id, &reg_val);
+	*value = reg_val.bf.port_def_sdei;
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_pcp_port_def_sdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t value)
+{
+	union port_def_pcp_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_pcp_get(dev_id, port_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_def_sdei = value;
+	ret = hppe_port_def_pcp_set(dev_id, port_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_pcp_port_def_spcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t *value)
+{
+	union port_def_pcp_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_pcp_get(dev_id, port_id, &reg_val);
+	*value = reg_val.bf.port_def_spcp;
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_pcp_port_def_spcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t value)
+{
+	union port_def_pcp_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_pcp_get(dev_id, port_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_def_spcp = value;
+	ret = hppe_port_def_pcp_set(dev_id, port_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_pcp_port_def_cdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t *value)
+{
+	union port_def_pcp_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_pcp_get(dev_id, port_id, &reg_val);
+	*value = reg_val.bf.port_def_cdei;
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_pcp_port_def_cdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t value)
+{
+	union port_def_pcp_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_pcp_get(dev_id, port_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_def_cdei = value;
+	ret = hppe_port_def_pcp_set(dev_id, port_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_pcp_port_def_cpcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t *value)
+{
+	union port_def_pcp_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_pcp_get(dev_id, port_id, &reg_val);
+	*value = reg_val.bf.port_def_cpcp;
+	return ret;
+}
+
+sw_error_t
+hppe_port_def_pcp_port_def_cpcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t value)
+{
+	union port_def_pcp_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_def_pcp_get(dev_id, port_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_def_cpcp = value;
+	ret = hppe_port_def_pcp_set(dev_id, port_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_vlan_config_port_in_dei_prop_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t *value)
+{
+	union port_vlan_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_vlan_config_get(dev_id, port_id, &reg_val);
+	*value = reg_val.bf.port_in_dei_prop_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_port_vlan_config_port_in_dei_prop_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t value)
+{
+	union port_vlan_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_vlan_config_get(dev_id, port_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_in_dei_prop_cmd = value;
+	ret = hppe_port_vlan_config_set(dev_id, port_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_vlan_config_port_in_pcp_prop_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t *value)
+{
+	union port_vlan_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_vlan_config_get(dev_id, port_id, &reg_val);
+	*value = reg_val.bf.port_in_pcp_prop_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_port_vlan_config_port_in_pcp_prop_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t value)
+{
+	union port_vlan_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_vlan_config_get(dev_id, port_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_in_pcp_prop_cmd = value;
+	ret = hppe_port_vlan_config_set(dev_id, port_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_vlan_config_port_untag_fltr_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t *value)
+{
+	union port_vlan_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_vlan_config_get(dev_id, port_id, &reg_val);
+	*value = reg_val.bf.port_untag_fltr_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_port_vlan_config_port_untag_fltr_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t value)
+{
+	union port_vlan_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_vlan_config_get(dev_id, port_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_untag_fltr_cmd = value;
+	ret = hppe_port_vlan_config_set(dev_id, port_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_vlan_config_port_in_vlan_fltr_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t *value)
+{
+	union port_vlan_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_vlan_config_get(dev_id, port_id, &reg_val);
+	*value = reg_val.bf.port_in_vlan_fltr_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_port_vlan_config_port_in_vlan_fltr_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t value)
+{
+	union port_vlan_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_vlan_config_get(dev_id, port_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_in_vlan_fltr_cmd = value;
+	ret = hppe_port_vlan_config_set(dev_id, port_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_vlan_config_port_pri_tag_fltr_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t *value)
+{
+	union port_vlan_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_vlan_config_get(dev_id, port_id, &reg_val);
+	*value = reg_val.bf.port_pri_tag_fltr_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_port_vlan_config_port_pri_tag_fltr_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t value)
+{
+	union port_vlan_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_vlan_config_get(dev_id, port_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_pri_tag_fltr_cmd = value;
+	ret = hppe_port_vlan_config_set(dev_id, port_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_vlan_config_port_vlan_xlt_miss_fwd_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t *value)
+{
+	union port_vlan_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_vlan_config_get(dev_id, port_id, &reg_val);
+	*value = reg_val.bf.port_vlan_xlt_miss_fwd_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_port_vlan_config_port_vlan_xlt_miss_fwd_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t value)
+{
+	union port_vlan_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_vlan_config_get(dev_id, port_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_vlan_xlt_miss_fwd_cmd = value;
+	ret = hppe_port_vlan_config_set(dev_id, port_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_vlan_config_port_tag_fltr_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t *value)
+{
+	union port_vlan_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_vlan_config_get(dev_id, port_id, &reg_val);
+	*value = reg_val.bf.port_tag_fltr_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_port_vlan_config_port_tag_fltr_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t port_id,
+		a_uint32_t value)
+{
+	union port_vlan_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_vlan_config_get(dev_id, port_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_tag_fltr_cmd = value;
+	ret = hppe_port_vlan_config_set(dev_id, port_id, &reg_val);
+	return ret;
+}
+
+#ifndef IN_PORTVLAN_MINI
+sw_error_t
+hppe_iv_dbg_addr_dbg_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union iv_dbg_addr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_iv_dbg_addr_get(dev_id, &reg_val);
+	*value = reg_val.bf.dbg_addr;
+	return ret;
+}
+
+sw_error_t
+hppe_iv_dbg_addr_dbg_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union iv_dbg_addr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_iv_dbg_addr_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dbg_addr = value;
+	ret = hppe_iv_dbg_addr_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_iv_dbg_data_dbg_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union iv_dbg_data_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_iv_dbg_data_get(dev_id, &reg_val);
+	*value = reg_val.bf.dbg_data;
+	return ret;
+}
+
+sw_error_t
+hppe_iv_dbg_data_dbg_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_eco_reserve_eco_res_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union eco_reserve_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eco_reserve_get(dev_id, &reg_val);
+	*value = reg_val.bf.eco_res;
+	return ret;
+}
+
+sw_error_t
+hppe_eco_reserve_eco_res_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union eco_reserve_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eco_reserve_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.eco_res = value;
+	ret = hppe_eco_reserve_set(dev_id, &reg_val);
+	return ret;
+}
+#endif
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_vid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ckey_vid;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_vid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ckey_vid = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_frm_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.frm_type;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_frm_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.frm_type = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_prot_value_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.prot_value_1 << 7 | \
+		reg_val.bf.prot_value_0;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_prot_value_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.prot_value_1 = value >> 7;
+	reg_val.bf.prot_value_0 = value & (((a_uint64_t)1<<7)-1);
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.valid;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.valid = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_frm_type_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.frm_type_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_frm_type_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.frm_type_incl = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ckey_dei;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ckey_dei = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.skey_dei;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.skey_dei = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.skey_pcp;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.skey_pcp = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ckey_pcp;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ckey_pcp = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_vid_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ckey_vid_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_vid_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ckey_vid_incl = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_dei_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ckey_dei_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_dei_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ckey_dei_incl = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_port_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_port_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_bitmap = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_prot_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.prot_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_prot_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.prot_incl = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_pcp_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.skey_pcp_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_pcp_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.skey_pcp_incl = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ckey_fmt_1 << 1 | \
+		reg_val.bf.ckey_fmt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ckey_fmt_1 = value >> 1;
+	reg_val.bf.ckey_fmt_0 = value & (((a_uint64_t)1<<1)-1);
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_vid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.skey_vid;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_vid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.skey_vid = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.skey_fmt;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.skey_fmt = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_pcp_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ckey_pcp_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_ckey_pcp_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ckey_pcp_incl = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_dei_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.skey_dei_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_dei_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.skey_dei_incl = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_vid_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.skey_vid_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_rule_tbl_skey_vid_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_rule_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_rule_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.skey_vid_incl = value;
+	ret = hppe_xlt_rule_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_dei_swap_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dei_swap_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_dei_swap_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dei_swap_cmd = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cvid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_cvid;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cvid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_cvid = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cpcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_cpcp;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cpcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_cpcp = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_spcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_spcp_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_spcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_spcp_cmd = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_sdei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_sdei_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_sdei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_sdei_cmd = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cvid_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_cvid_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cvid_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_cvid_cmd = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_vsi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vsi;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_vsi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vsi = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_spcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_spcp_1 << 1 | \
+		reg_val.bf.xlt_spcp_0;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_spcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_spcp_1 = value >> 1;
+	reg_val.bf.xlt_spcp_0 = value & (((a_uint64_t)1<<1)-1);
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_counter_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.counter_id;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_counter_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.counter_id = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_vid_swap_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vid_swap_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_vid_swap_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vid_swap_cmd = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_sdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_sdei;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_sdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_sdei = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_counter_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.counter_en;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_counter_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.counter_en = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_svid_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_svid_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_svid_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_svid_cmd = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_svid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_svid;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_svid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_svid = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_vsi_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vsi_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_vsi_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vsi_cmd = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cpcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_cpcp_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cpcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_cpcp_cmd = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cdei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_cdei_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cdei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_cdei_cmd = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_pcp_swap_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pcp_swap_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_pcp_swap_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pcp_swap_cmd = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_cdei;
+	return ret;
+}
+
+sw_error_t
+hppe_xlt_action_tbl_xlt_cdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union xlt_action_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_xlt_action_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_cdei = value;
+	ret = hppe_xlt_action_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vlan_xlt_rule_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_VLAN_XLT_RULE_ADDRESS + \
+				index * EG_VLAN_XLT_RULE_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vlan_xlt_rule_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_VLAN_XLT_RULE_ADDRESS + \
+				index * EG_VLAN_XLT_RULE_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_eg_vsi_tag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vsi_tag_u *value)
+{
+	if (index >= EG_VSI_TAG_NUM)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_VSI_TAG_ADDRESS + \
+				index * EG_VSI_TAG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_eg_vsi_tag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vsi_tag_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_VSI_TAG_ADDRESS + \
+				index * EG_VSI_TAG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_port_eg_def_vid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_eg_def_vid_u *value)
+{
+	if (index >= PORT_EG_DEF_VID_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + PORT_EG_DEF_VID_ADDRESS + \
+				index * PORT_EG_DEF_VID_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_eg_def_vid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_eg_def_vid_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + PORT_EG_DEF_VID_ADDRESS + \
+				index * PORT_EG_DEF_VID_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_port_eg_vlan_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_eg_vlan_u *value)
+{
+	if (index >= PORT_EG_VLAN_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + PORT_EG_VLAN_ADDRESS + \
+				index * PORT_EG_VLAN_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_eg_vlan_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_eg_vlan_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + PORT_EG_VLAN_ADDRESS + \
+				index * PORT_EG_VLAN_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_eg_vlan_tpid_get(
+		a_uint32_t dev_id,
+		union eg_vlan_tpid_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_VLAN_TPID_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_eg_vlan_tpid_set(
+		a_uint32_t dev_id,
+		union eg_vlan_tpid_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_VLAN_TPID_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_eg_bridge_config_get(
+		a_uint32_t dev_id,
+		union eg_bridge_config_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_BRIDGE_CONFIG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_eg_bridge_config_set(
+		a_uint32_t dev_id,
+		union eg_bridge_config_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_BRIDGE_CONFIG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vlan_xlt_action_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_VLAN_XLT_ACTION_ADDRESS + \
+				index * EG_VLAN_XLT_ACTION_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vlan_xlt_action_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_VLAN_XLT_ACTION_ADDRESS + \
+				index * EG_VLAN_XLT_ACTION_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_vid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ckey_vid;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_vid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ckey_vid = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.valid;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.valid = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ckey_dei;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ckey_dei = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_dei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.skey_dei;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_dei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.skey_dei = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.skey_pcp;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.skey_pcp = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_pcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ckey_pcp;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_pcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ckey_pcp = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_vsi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vsi;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_vsi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vsi = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_vid_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ckey_vid_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_vid_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ckey_vid_incl = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_dei_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ckey_dei_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_dei_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ckey_dei_incl = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_vsi_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vsi_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_vsi_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vsi_incl = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_port_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_port_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_bitmap = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_pcp_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.skey_pcp_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_pcp_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.skey_pcp_incl = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ckey_fmt;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ckey_fmt = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_vid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.skey_vid;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_vid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.skey_vid = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.skey_fmt;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.skey_fmt = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_pcp_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ckey_pcp_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_ckey_pcp_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ckey_pcp_incl = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_vid_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.skey_vid_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_vid_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.skey_vid_incl = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_dei_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.skey_dei_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_skey_dei_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.skey_dei_incl = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_vsi_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vsi_valid;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_rule_vsi_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_rule_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vsi_valid = value;
+	ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vsi_tag_tagged_mode_port_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vsi_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vsi_tag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tagged_mode_port_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vsi_tag_tagged_mode_port_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vsi_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vsi_tag_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tagged_mode_port_bitmap = value;
+	ret = hppe_eg_vsi_tag_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_svid_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_eg_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_def_vid_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_def_svid_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_svid_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_eg_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_def_vid_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_def_svid_en = value;
+	ret = hppe_port_eg_def_vid_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_svid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_eg_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_def_vid_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_def_svid;
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_svid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_eg_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_def_vid_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_def_svid = value;
+	ret = hppe_port_eg_def_vid_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_cvid_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_eg_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_def_vid_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_def_cvid_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_cvid_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_eg_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_def_vid_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_def_cvid_en = value;
+	ret = hppe_port_eg_def_vid_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_cvid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_eg_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_def_vid_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_def_cvid;
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_def_vid_port_def_cvid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_eg_def_vid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_def_vid_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_def_cvid = value;
+	ret = hppe_port_eg_def_vid_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_vlan_tx_counting_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_eg_vlan_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_vlan_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_counting_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_vlan_tx_counting_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_eg_vlan_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_vlan_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_counting_en = value;
+	ret = hppe_port_eg_vlan_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_vlan_ctag_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_eg_vlan_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_vlan_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_eg_vlan_ctag_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_vlan_ctag_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_eg_vlan_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_vlan_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_eg_vlan_ctag_mode = value;
+	ret = hppe_port_eg_vlan_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_pcp_prop_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_eg_vlan_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_vlan_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_eg_pcp_prop_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_pcp_prop_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_eg_vlan_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_vlan_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_eg_pcp_prop_cmd = value;
+	ret = hppe_port_eg_vlan_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_vlan_vsi_tag_mode_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_eg_vlan_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_vlan_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vsi_tag_mode_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_vlan_vsi_tag_mode_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_eg_vlan_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_vlan_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vsi_tag_mode_en = value;
+	ret = hppe_port_eg_vlan_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_vlan_stag_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_eg_vlan_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_vlan_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_eg_vlan_stag_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_vlan_stag_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_eg_vlan_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_vlan_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_eg_vlan_stag_mode = value;
+	ret = hppe_port_eg_vlan_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_dei_prop_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_eg_vlan_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_vlan_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_eg_dei_prop_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_vlan_port_eg_dei_prop_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_eg_vlan_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_vlan_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_eg_dei_prop_cmd = value;
+	ret = hppe_port_eg_vlan_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_vlan_port_vlan_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_eg_vlan_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_vlan_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_vlan_type;
+	return ret;
+}
+
+sw_error_t
+hppe_port_eg_vlan_port_vlan_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_eg_vlan_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_eg_vlan_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_vlan_type = value;
+	ret = hppe_port_eg_vlan_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_tpid_ctpid_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union eg_vlan_tpid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_tpid_get(dev_id, &reg_val);
+	*value = reg_val.bf.ctpid;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_tpid_ctpid_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union eg_vlan_tpid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_tpid_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ctpid = value;
+	ret = hppe_eg_vlan_tpid_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_tpid_stpid_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union eg_vlan_tpid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_tpid_get(dev_id, &reg_val);
+	*value = reg_val.bf.stpid;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_tpid_stpid_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union eg_vlan_tpid_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_tpid_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.stpid = value;
+	ret = hppe_eg_vlan_tpid_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_bridge_config_bridge_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union eg_bridge_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_bridge_config_get(dev_id, &reg_val);
+	*value = reg_val.bf.bridge_type;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_bridge_config_bridge_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union eg_bridge_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_bridge_config_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.bridge_type = value;
+	ret = hppe_eg_bridge_config_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_bridge_config_pkt_l2_edit_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union eg_bridge_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_bridge_config_get(dev_id, &reg_val);
+	*value = reg_val.bf.pkt_l2_edit_en;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_bridge_config_pkt_l2_edit_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union eg_bridge_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_bridge_config_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pkt_l2_edit_en = value;
+	ret = hppe_eg_bridge_config_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_bridge_config_queue_cnt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union eg_bridge_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_bridge_config_get(dev_id, &reg_val);
+	*value = reg_val.bf.queue_cnt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_bridge_config_queue_cnt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union eg_bridge_config_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_bridge_config_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.queue_cnt_en = value;
+	ret = hppe_eg_bridge_config_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_dei_swap_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dei_swap_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_dei_swap_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dei_swap_cmd = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cvid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_cvid;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cvid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_cvid = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cpcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_cpcp;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cpcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_cpcp = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_spcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_spcp_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_spcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_spcp_cmd = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_sdei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_sdei_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_sdei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_sdei_cmd = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cvid_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_cvid_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cvid_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_cvid_cmd = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_spcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_spcp_1 << 1 | \
+		reg_val.bf.xlt_spcp_0;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_spcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_spcp_1 = value >> 1;
+	reg_val.bf.xlt_spcp_0 = value & (((a_uint64_t)1<<1)-1);
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_counter_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.counter_id;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_counter_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.counter_id = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_vid_swap_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vid_swap_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_vid_swap_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vid_swap_cmd = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_sdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_sdei;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_sdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_sdei = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_counter_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.counter_en;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_counter_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.counter_en = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_svid_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_svid_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_svid_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_svid_cmd = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_svid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_svid;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_svid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_svid = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cpcp_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_cpcp_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cpcp_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_cpcp_cmd = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cdei_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_cdei_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cdei_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_cdei_cmd = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_pcp_swap_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pcp_swap_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_pcp_swap_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pcp_swap_cmd = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.xlt_cdei;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vlan_xlt_action_xlt_cdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vlan_xlt_action_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vlan_xlt_action_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.xlt_cdei = value;
+	ret = hppe_eg_vlan_xlt_action_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vlan_dev_tx_counter_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vlan_dev_tx_counter_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + VLAN_DEV_TX_COUNTER_TBL_ADDRESS + \
+				index * VLAN_DEV_TX_COUNTER_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_vlan_dev_tx_counter_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vlan_dev_tx_counter_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + VLAN_DEV_TX_COUNTER_TBL_ADDRESS + \
+				index * VLAN_DEV_TX_COUNTER_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_vlan_dev_tx_counter_tbl_tx_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union vlan_dev_tx_counter_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_dev_tx_counter_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.tx_byte_cnt_1 << 32 | \
+		reg_val.bf.tx_byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_vlan_dev_tx_counter_tbl_tx_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union vlan_dev_tx_counter_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_dev_tx_counter_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_byte_cnt_1 = value >> 32;
+	reg_val.bf.tx_byte_cnt_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_vlan_dev_tx_counter_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vlan_dev_tx_counter_tbl_tx_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vlan_dev_tx_counter_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_dev_tx_counter_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_vlan_dev_tx_counter_tbl_tx_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vlan_dev_tx_counter_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_dev_tx_counter_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_pkt_cnt = value;
+	ret = hppe_vlan_dev_tx_counter_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_pppoe.c b/qca-ssdk/src/hsl/hppe/hppe_pppoe.c
new file mode 100755
index 0000000..481de47
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_pppoe.c
@@ -0,0 +1,388 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_pppoe_reg.h"
+#include "hppe_pppoe.h"
+
+sw_error_t
+hppe_pppoe_session_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pppoe_session_u *value)
+{
+	if (index >= PPPOE_SESSION_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + PPPOE_SESSION_ADDRESS + \
+				index * PPPOE_SESSION_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_pppoe_session_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pppoe_session_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + PPPOE_SESSION_ADDRESS + \
+				index * PPPOE_SESSION_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_pppoe_session_ext_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pppoe_session_ext_u *value)
+{
+	if (index >= PPPOE_SESSION_EXT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + PPPOE_SESSION_EXT_ADDRESS + \
+				index * PPPOE_SESSION_EXT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_pppoe_session_ext_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pppoe_session_ext_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + PPPOE_SESSION_EXT_ADDRESS + \
+				index * PPPOE_SESSION_EXT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_pppoe_session_ext1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pppoe_session_ext1_u *value)
+{
+	if (index >= PPPOE_SESSION_EXT1_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + PPPOE_SESSION_EXT1_ADDRESS + \
+				index * PPPOE_SESSION_EXT1_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_pppoe_session_ext1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pppoe_session_ext1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + PPPOE_SESSION_EXT1_ADDRESS + \
+				index * PPPOE_SESSION_EXT1_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_pppoe_session_session_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pppoe_session_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.session_id;
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_session_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pppoe_session_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.session_id = value;
+	ret = hppe_pppoe_session_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_l3_if_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pppoe_session_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.l3_if_index;
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_l3_if_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pppoe_session_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_if_index = value;
+	ret = hppe_pppoe_session_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_port_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pppoe_session_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_port_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pppoe_session_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_bitmap = value;
+	ret = hppe_pppoe_session_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_ext_uc_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pppoe_session_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.uc_valid;
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_ext_uc_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pppoe_session_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.uc_valid = value;
+	ret = hppe_pppoe_session_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_ext_mc_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pppoe_session_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mc_valid;
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_ext_mc_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pppoe_session_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mc_valid = value;
+	ret = hppe_pppoe_session_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_ext_smac_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pppoe_session_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.smac_valid;
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_ext_smac_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pppoe_session_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.smac_valid = value;
+	ret = hppe_pppoe_session_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_ext_l3_if_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pppoe_session_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.l3_if_valid;
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_ext_l3_if_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pppoe_session_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_if_valid = value;
+	ret = hppe_pppoe_session_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_ext_smac_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pppoe_session_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.smac;
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_ext_smac_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pppoe_session_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_ext_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.smac = value;
+	ret = hppe_pppoe_session_ext_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_ext1_smac_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pppoe_session_ext1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_ext1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.smac;
+	return ret;
+}
+
+sw_error_t
+hppe_pppoe_session_ext1_smac_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pppoe_session_ext1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pppoe_session_ext1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.smac = value;
+	ret = hppe_pppoe_session_ext1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_qm.c b/qca-ssdk/src/hsl/hppe/hppe_qm.c
new file mode 100755
index 0000000..16e3ceb
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_qm.c
@@ -0,0 +1,9622 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_qm_reg.h"
+#include "hppe_qm.h"
+
+sw_error_t
+hppe_queue_tx_counter_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union queue_tx_counter_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + QUEUE_TX_COUNTER_TBL_ADDRESS + \
+				index * QUEUE_TX_COUNTER_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_queue_tx_counter_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union queue_tx_counter_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + QUEUE_TX_COUNTER_TBL_ADDRESS + \
+				index * QUEUE_TX_COUNTER_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_flush_cfg_get(
+		a_uint32_t dev_id,
+		union flush_cfg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + FLUSH_CFG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_flush_cfg_set(
+		a_uint32_t dev_id,
+		union flush_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + FLUSH_CFG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_in_mirror_priority_ctrl_get(
+		a_uint32_t dev_id,
+		union in_mirror_priority_ctrl_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + IN_MIRROR_PRIORITY_CTRL_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_mirror_priority_ctrl_set(
+		a_uint32_t dev_id,
+		union in_mirror_priority_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + IN_MIRROR_PRIORITY_CTRL_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_eg_mirror_priority_ctrl_get(
+		a_uint32_t dev_id,
+		union eg_mirror_priority_ctrl_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + EG_MIRROR_PRIORITY_CTRL_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_eg_mirror_priority_ctrl_set(
+		a_uint32_t dev_id,
+		union eg_mirror_priority_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + EG_MIRROR_PRIORITY_CTRL_ADDRESS,
+				value->val);
+}
+
+#ifndef IN_QM_MINI
+sw_error_t
+hppe_ucast_default_hash_get(
+		a_uint32_t dev_id,
+		union ucast_default_hash_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UCAST_DEFAULT_HASH_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ucast_default_hash_set(
+		a_uint32_t dev_id,
+		union ucast_default_hash_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UCAST_DEFAULT_HASH_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_spare_reg0_get(
+		a_uint32_t dev_id,
+		union spare_reg0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + SPARE_REG0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_spare_reg0_set(
+		a_uint32_t dev_id,
+		union spare_reg0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + SPARE_REG0_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_spare_reg1_get(
+		a_uint32_t dev_id,
+		union spare_reg1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + SPARE_REG1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_spare_reg1_set(
+		a_uint32_t dev_id,
+		union spare_reg1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + SPARE_REG1_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_qm_dbg_addr_get(
+		a_uint32_t dev_id,
+		union qm_dbg_addr_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + QM_DBG_ADDR_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_qm_dbg_addr_set(
+		a_uint32_t dev_id,
+		union qm_dbg_addr_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + QM_DBG_ADDR_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_qm_dbg_data_get(
+		a_uint32_t dev_id,
+		union qm_dbg_data_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + QM_DBG_DATA_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_qm_dbg_data_set(
+		a_uint32_t dev_id,
+		union qm_dbg_data_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mcast_priority_map0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map0_u *value)
+{
+	if (index >= MCAST_PRIORITY_MAP0_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP0_ADDRESS + \
+				index * MCAST_PRIORITY_MAP0_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mcast_priority_map0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP0_ADDRESS + \
+				index * MCAST_PRIORITY_MAP0_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mcast_priority_map1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map1_u *value)
+{
+	if (index >= MCAST_PRIORITY_MAP1_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP1_ADDRESS + \
+				index * MCAST_PRIORITY_MAP1_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mcast_priority_map1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP1_ADDRESS + \
+				index * MCAST_PRIORITY_MAP1_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mcast_priority_map2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map2_u *value)
+{
+	if (index >= MCAST_PRIORITY_MAP2_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP2_ADDRESS + \
+				index * MCAST_PRIORITY_MAP2_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mcast_priority_map2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map2_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP2_ADDRESS + \
+				index * MCAST_PRIORITY_MAP2_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mcast_priority_map3_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map3_u *value)
+{
+	if (index >= MCAST_PRIORITY_MAP3_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP3_ADDRESS + \
+				index * MCAST_PRIORITY_MAP3_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mcast_priority_map3_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map3_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP3_ADDRESS + \
+				index * MCAST_PRIORITY_MAP3_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mcast_priority_map4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map4_u *value)
+{
+	if (index >= MCAST_PRIORITY_MAP4_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP4_ADDRESS + \
+				index * MCAST_PRIORITY_MAP4_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mcast_priority_map4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map4_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP4_ADDRESS + \
+				index * MCAST_PRIORITY_MAP4_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mcast_priority_map5_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map5_u *value)
+{
+	if (index >= MCAST_PRIORITY_MAP5_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP5_ADDRESS + \
+				index * MCAST_PRIORITY_MAP5_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mcast_priority_map5_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map5_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP5_ADDRESS + \
+				index * MCAST_PRIORITY_MAP5_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mcast_priority_map6_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map6_u *value)
+{
+	if (index >= MCAST_PRIORITY_MAP6_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP6_ADDRESS + \
+				index * MCAST_PRIORITY_MAP6_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mcast_priority_map6_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map6_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP6_ADDRESS + \
+				index * MCAST_PRIORITY_MAP6_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mcast_priority_map7_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map7_u *value)
+{
+	if (index >= MCAST_PRIORITY_MAP7_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP7_ADDRESS + \
+				index * MCAST_PRIORITY_MAP7_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mcast_priority_map7_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_priority_map7_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP7_ADDRESS + \
+				index * MCAST_PRIORITY_MAP7_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_get(
+		a_uint32_t dev_id,
+		union agg_profile_cnt_en_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AGG_PROFILE_CNT_EN_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_set(
+		a_uint32_t dev_id,
+		union agg_profile_cnt_en_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AGG_PROFILE_CNT_EN_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_uq_agg_profile_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_profile_cfg_u *value)
+{
+	if (index >= UQ_AGG_PROFILE_CFG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UQ_AGG_PROFILE_CFG_ADDRESS + \
+				index * UQ_AGG_PROFILE_CFG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uq_agg_profile_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_profile_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UQ_AGG_PROFILE_CFG_ADDRESS + \
+				index * UQ_AGG_PROFILE_CFG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mq_agg_profile_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mq_agg_profile_cfg_u *value)
+{
+	if (index >= MQ_AGG_PROFILE_CFG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MQ_AGG_PROFILE_CFG_ADDRESS + \
+				index * MQ_AGG_PROFILE_CFG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mq_agg_profile_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mq_agg_profile_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MQ_AGG_PROFILE_CFG_ADDRESS + \
+				index * MQ_AGG_PROFILE_CFG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_grp_agg_profile_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_agg_profile_cfg_u *value)
+{
+	if (index >= GRP_AGG_PROFILE_CFG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + GRP_AGG_PROFILE_CFG_ADDRESS + \
+				index * GRP_AGG_PROFILE_CFG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_grp_agg_profile_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_agg_profile_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + GRP_AGG_PROFILE_CFG_ADDRESS + \
+				index * GRP_AGG_PROFILE_CFG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_uq_agg_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_in_profile_cnt_u *value)
+{
+	if (index >= UQ_AGG_IN_PROFILE_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UQ_AGG_IN_PROFILE_CNT_ADDRESS + \
+				index * UQ_AGG_IN_PROFILE_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uq_agg_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_in_profile_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UQ_AGG_IN_PROFILE_CNT_ADDRESS + \
+				index * UQ_AGG_IN_PROFILE_CNT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_uq_agg_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_out_profile_cnt_u *value)
+{
+	if (index >= UQ_AGG_OUT_PROFILE_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UQ_AGG_OUT_PROFILE_CNT_ADDRESS + \
+				index * UQ_AGG_OUT_PROFILE_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uq_agg_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_out_profile_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UQ_AGG_OUT_PROFILE_CNT_ADDRESS + \
+				index * UQ_AGG_OUT_PROFILE_CNT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mq_agg_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mq_agg_in_profile_cnt_u *value)
+{
+	if (index >= MQ_AGG_IN_PROFILE_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MQ_AGG_IN_PROFILE_CNT_ADDRESS + \
+				index * MQ_AGG_IN_PROFILE_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mq_agg_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mq_agg_in_profile_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MQ_AGG_IN_PROFILE_CNT_ADDRESS + \
+				index * MQ_AGG_IN_PROFILE_CNT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mq_agg_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mq_agg_out_profile_cnt_u *value)
+{
+	if (index >= MQ_AGG_OUT_PROFILE_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MQ_AGG_OUT_PROFILE_CNT_ADDRESS + \
+				index * MQ_AGG_OUT_PROFILE_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mq_agg_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mq_agg_out_profile_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MQ_AGG_OUT_PROFILE_CNT_ADDRESS + \
+				index * MQ_AGG_OUT_PROFILE_CNT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_grp_agg_in_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_agg_in_profile_cnt_u *value)
+{
+	if (index >= GRP_AGG_IN_PROFILE_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + GRP_AGG_IN_PROFILE_CNT_ADDRESS + \
+				index * GRP_AGG_IN_PROFILE_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_grp_agg_in_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_agg_in_profile_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + GRP_AGG_IN_PROFILE_CNT_ADDRESS + \
+				index * GRP_AGG_IN_PROFILE_CNT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_grp_agg_out_profile_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_agg_out_profile_cnt_u *value)
+{
+	if (index >= GRP_AGG_OUT_PROFILE_CNT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + GRP_AGG_OUT_PROFILE_CNT_ADDRESS + \
+				index * GRP_AGG_OUT_PROFILE_CNT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_grp_agg_out_profile_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union grp_agg_out_profile_cnt_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + GRP_AGG_OUT_PROFILE_CNT_ADDRESS + \
+				index * GRP_AGG_OUT_PROFILE_CNT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_ucast_queue_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ucast_queue_map_tbl_u *value)
+{
+	if (index >= UCAST_QUEUE_MAP_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UCAST_QUEUE_MAP_TBL_ADDRESS + \
+				index * UCAST_QUEUE_MAP_TBL_INC,
+				&value->val);
+}
+#endif
+
+sw_error_t
+hppe_ucast_queue_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ucast_queue_map_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UCAST_QUEUE_MAP_TBL_ADDRESS + \
+				index * UCAST_QUEUE_MAP_TBL_INC,
+				value->val);
+}
+
+#ifndef IN_QM_MINI
+sw_error_t
+hppe_ucast_hash_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ucast_hash_map_tbl_u *value)
+{
+	if (index >= UCAST_HASH_MAP_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UCAST_HASH_MAP_TBL_ADDRESS + \
+				index * UCAST_HASH_MAP_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_ucast_hash_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ucast_hash_map_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UCAST_HASH_MAP_TBL_ADDRESS + \
+				index * UCAST_HASH_MAP_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_ucast_priority_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ucast_priority_map_tbl_u *value)
+{
+	if (index >= UCAST_PRIORITY_MAP_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UCAST_PRIORITY_MAP_TBL_ADDRESS + \
+				index * UCAST_PRIORITY_MAP_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_ucast_priority_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ucast_priority_map_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UCAST_PRIORITY_MAP_TBL_ADDRESS + \
+				index * UCAST_PRIORITY_MAP_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mcast_queue_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_queue_map_tbl_u *value)
+{
+	if (index >= MCAST_QUEUE_MAP_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_QUEUE_MAP_TBL_ADDRESS + \
+				index * MCAST_QUEUE_MAP_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mcast_queue_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mcast_queue_map_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MCAST_QUEUE_MAP_TBL_ADDRESS + \
+				index * MCAST_QUEUE_MAP_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_ac_mseq_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mseq_tbl_u *value)
+{
+	if (index >= AC_MSEQ_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_MSEQ_TBL_ADDRESS + \
+				index * AC_MSEQ_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_ac_mseq_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mseq_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_MSEQ_TBL_ADDRESS + \
+				index * AC_MSEQ_TBL_INC,
+				value->val);
+}
+#endif
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_uni_queue_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_CFG_TBL_ADDRESS + \
+				index * AC_UNI_QUEUE_CFG_TBL_INC,
+				value->val,
+				4);
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_uni_queue_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_CFG_TBL_ADDRESS + \
+				index * AC_UNI_QUEUE_CFG_TBL_INC,
+				value->val,
+				4);
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mul_queue_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_CFG_TBL_ADDRESS + \
+				index * AC_MUL_QUEUE_CFG_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mul_queue_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_CFG_TBL_ADDRESS + \
+				index * AC_MUL_QUEUE_CFG_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_grp_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_GRP_CFG_TBL_ADDRESS + \
+				index * AC_GRP_CFG_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_grp_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_GRP_CFG_TBL_ADDRESS + \
+				index * AC_GRP_CFG_TBL_INC,
+				value->val,
+				3);
+}
+
+#ifndef IN_QM_MINI
+sw_error_t
+hppe_ac_uni_queue_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_uni_queue_cnt_tbl_u *value)
+{
+	if (index >= AC_UNI_QUEUE_CNT_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_CNT_TBL_ADDRESS + \
+				index * AC_UNI_QUEUE_CNT_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_ac_uni_queue_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_uni_queue_cnt_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_CNT_TBL_ADDRESS + \
+				index * AC_UNI_QUEUE_CNT_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_ac_mul_queue_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mul_queue_cnt_tbl_u *value)
+{
+	if (index >= AC_MUL_QUEUE_CNT_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_CNT_TBL_ADDRESS + \
+				index * AC_MUL_QUEUE_CNT_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_ac_mul_queue_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mul_queue_cnt_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_CNT_TBL_ADDRESS + \
+				index * AC_MUL_QUEUE_CNT_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_ac_grp_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_grp_cnt_tbl_u *value)
+{
+	if (index >= AC_GRP_CNT_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_GRP_CNT_TBL_ADDRESS + \
+				index * AC_GRP_CNT_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_ac_grp_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_grp_cnt_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_GRP_CNT_TBL_ADDRESS + \
+				index * AC_GRP_CNT_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_uni_queue_drop_state_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_DROP_STATE_TBL_ADDRESS + \
+				index * AC_UNI_QUEUE_DROP_STATE_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_uni_queue_drop_state_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_DROP_STATE_TBL_ADDRESS + \
+				index * AC_UNI_QUEUE_DROP_STATE_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mul_queue_drop_state_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_DROP_STATE_TBL_ADDRESS + \
+				index * AC_MUL_QUEUE_DROP_STATE_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_mul_queue_drop_state_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_DROP_STATE_TBL_ADDRESS + \
+				index * AC_MUL_QUEUE_DROP_STATE_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_grp_drop_state_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_GRP_DROP_STATE_TBL_ADDRESS + \
+				index * AC_GRP_DROP_STATE_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ac_grp_drop_state_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + AC_GRP_DROP_STATE_TBL_ADDRESS + \
+				index * AC_GRP_DROP_STATE_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_oq_enq_opr_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_enq_opr_tbl_u *value)
+{
+	if (index >= OQ_ENQ_OPR_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_ENQ_OPR_TBL_ADDRESS + \
+				index * OQ_ENQ_OPR_TBL_INC,
+				&value->val);
+}
+#endif
+
+sw_error_t
+hppe_oq_enq_opr_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_enq_opr_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_ENQ_OPR_TBL_ADDRESS + \
+				index * OQ_ENQ_OPR_TBL_INC,
+				value->val);
+}
+
+#ifndef IN_QM_MINI
+sw_error_t
+hppe_oq_deq_opr_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_deq_opr_tbl_u *value)
+{
+	if (index >= OQ_DEQ_OPR_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_DEQ_OPR_TBL_ADDRESS + \
+				index * OQ_DEQ_OPR_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_oq_deq_opr_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_deq_opr_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_DEQ_OPR_TBL_ADDRESS + \
+				index * OQ_DEQ_OPR_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_oq_head_uni_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_head_uni_tbl_u *value)
+{
+	if (index >= OQ_HEAD_UNI_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_HEAD_UNI_TBL_ADDRESS + \
+				index * OQ_HEAD_UNI_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_oq_head_uni_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_head_uni_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_HEAD_UNI_TBL_ADDRESS + \
+				index * OQ_HEAD_UNI_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_oq_head_mul_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_head_mul_tbl_u *value)
+{
+	if (index >= OQ_HEAD_MUL_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_HEAD_MUL_TBL_ADDRESS + \
+				index * OQ_HEAD_MUL_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_oq_head_mul_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_head_mul_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_HEAD_MUL_TBL_ADDRESS + \
+				index * OQ_HEAD_MUL_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_oq_ll_uni_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_uni_tbl_u *value)
+{
+	if (index >= OQ_LL_UNI_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_UNI_TBL_ADDRESS + \
+				index * OQ_LL_UNI_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_oq_ll_uni_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_uni_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_UNI_TBL_ADDRESS + \
+				index * OQ_LL_UNI_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p0_tbl_u *value)
+{
+	if (index >= OQ_LL_MUL_P0_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P0_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P0_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p0_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P0_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P0_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p1_tbl_u *value)
+{
+	if (index >= OQ_LL_MUL_P1_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P1_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P1_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p1_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P1_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P1_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p2_tbl_u *value)
+{
+	if (index >= OQ_LL_MUL_P2_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P2_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P2_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p2_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P2_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P2_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p3_tbl_u *value)
+{
+	if (index >= OQ_LL_MUL_P3_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P3_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P3_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p3_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P3_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P3_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p4_tbl_u *value)
+{
+	if (index >= OQ_LL_MUL_P4_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P4_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P4_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p4_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P4_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P4_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p5_tbl_u *value)
+{
+	if (index >= OQ_LL_MUL_P5_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P5_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P5_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p5_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P5_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P5_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p6_tbl_u *value)
+{
+	if (index >= OQ_LL_MUL_P6_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P6_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P6_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p6_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P6_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P6_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p7_tbl_u *value)
+{
+	if (index >= OQ_LL_MUL_P7_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P7_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P7_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union oq_ll_mul_p7_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P7_TBL_ADDRESS + \
+				index * OQ_LL_MUL_P7_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pkt_desp_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + PKT_DESP_TBL_ADDRESS + \
+				index * PKT_DESP_TBL_INC,
+				value->val,
+				13);
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pkt_desp_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + PKT_DESP_TBL_ADDRESS + \
+				index * PKT_DESP_TBL_INC,
+				value->val,
+				13);
+}
+
+sw_error_t
+hppe_uni_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uni_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UNI_DROP_CNT_TBL_ADDRESS + \
+				index * UNI_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_uni_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uni_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UNI_DROP_CNT_TBL_ADDRESS + \
+				index * UNI_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p0_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p0_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P0_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P0_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p0_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p0_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P0_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P0_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p1_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p1_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P1_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P1_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p1_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p1_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P1_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P1_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p2_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p2_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P2_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P2_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p2_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p2_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P2_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P2_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p3_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p3_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P3_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P3_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p3_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p3_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P3_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P3_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p4_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p4_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P4_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P4_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p4_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p4_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P4_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P4_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p5_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p5_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P5_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P5_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p5_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p5_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P5_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P5_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p6_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p6_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P6_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P6_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p6_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p6_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P6_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P6_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p7_drop_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p7_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P7_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P7_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_mul_p7_drop_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mul_p7_drop_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + MUL_P7_DROP_CNT_TBL_ADDRESS + \
+				index * MUL_P7_DROP_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_uq_agg_profile_map_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_profile_map_u *value)
+{
+	if (index >= UQ_AGG_PROFILE_MAP_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UQ_AGG_PROFILE_MAP_ADDRESS + \
+				index * UQ_AGG_PROFILE_MAP_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uq_agg_profile_map_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uq_agg_profile_map_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				QUEUE_MANAGER_BASE_ADDR + UQ_AGG_PROFILE_MAP_ADDRESS + \
+				index * UQ_AGG_PROFILE_MAP_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_flush_cfg_flush_busy_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flush_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flush_cfg_get(dev_id, &reg_val);
+	*value = reg_val.bf.flush_busy;
+	return ret;
+}
+
+sw_error_t
+hppe_flush_cfg_flush_busy_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flush_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flush_cfg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flush_busy = value;
+	ret = hppe_flush_cfg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flush_cfg_flush_qid_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flush_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flush_cfg_get(dev_id, &reg_val);
+	*value = reg_val.bf.flush_qid;
+	return ret;
+}
+
+sw_error_t
+hppe_flush_cfg_flush_qid_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flush_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flush_cfg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flush_qid = value;
+	ret = hppe_flush_cfg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flush_cfg_flush_dst_port_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flush_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flush_cfg_get(dev_id, &reg_val);
+	*value = reg_val.bf.flush_dst_port;
+	return ret;
+}
+
+sw_error_t
+hppe_flush_cfg_flush_dst_port_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flush_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flush_cfg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flush_dst_port = value;
+	ret = hppe_flush_cfg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flush_cfg_flush_all_queues_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flush_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flush_cfg_get(dev_id, &reg_val);
+	*value = reg_val.bf.flush_all_queues;
+	return ret;
+}
+
+sw_error_t
+hppe_flush_cfg_flush_all_queues_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flush_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flush_cfg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flush_all_queues = value;
+	ret = hppe_flush_cfg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flush_cfg_flush_wt_time_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flush_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flush_cfg_get(dev_id, &reg_val);
+	*value = reg_val.bf.flush_wt_time;
+	return ret;
+}
+
+sw_error_t
+hppe_flush_cfg_flush_wt_time_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flush_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flush_cfg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flush_wt_time = value;
+	ret = hppe_flush_cfg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flush_cfg_flush_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union flush_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flush_cfg_get(dev_id, &reg_val);
+	*value = reg_val.bf.flush_status;
+	return ret;
+}
+
+sw_error_t
+hppe_flush_cfg_flush_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union flush_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flush_cfg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flush_status = value;
+	ret = hppe_flush_cfg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_mirror_priority_ctrl_priority_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union in_mirror_priority_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_mirror_priority_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.priority;
+	return ret;
+}
+
+sw_error_t
+hppe_in_mirror_priority_ctrl_priority_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union in_mirror_priority_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_mirror_priority_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.priority = value;
+	ret = hppe_in_mirror_priority_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_mirror_priority_ctrl_priority_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union eg_mirror_priority_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_mirror_priority_ctrl_get(dev_id, &reg_val);
+	*value = reg_val.bf.priority;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_mirror_priority_ctrl_priority_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union eg_mirror_priority_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_mirror_priority_ctrl_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.priority = value;
+	ret = hppe_eg_mirror_priority_ctrl_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ucast_default_hash_hash_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union ucast_default_hash_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ucast_default_hash_get(dev_id, &reg_val);
+	*value = reg_val.bf.hash;
+	return ret;
+}
+
+sw_error_t
+hppe_ucast_default_hash_hash_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union ucast_default_hash_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ucast_default_hash_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hash = value;
+	ret = hppe_ucast_default_hash_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_spare_reg0_spare_reg0_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union spare_reg0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_spare_reg0_get(dev_id, &reg_val);
+	*value = reg_val.bf.spare_reg0;
+	return ret;
+}
+
+sw_error_t
+hppe_spare_reg0_spare_reg0_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union spare_reg0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_spare_reg0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.spare_reg0 = value;
+	ret = hppe_spare_reg0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_spare_reg1_spare_reg1_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union spare_reg1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_spare_reg1_get(dev_id, &reg_val);
+	*value = reg_val.bf.spare_reg1;
+	return ret;
+}
+
+sw_error_t
+hppe_spare_reg1_spare_reg1_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union spare_reg1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_spare_reg1_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.spare_reg1 = value;
+	ret = hppe_spare_reg1_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_qm_dbg_addr_dbg_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union qm_dbg_addr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_qm_dbg_addr_get(dev_id, &reg_val);
+	*value = reg_val.bf.dbg_addr;
+	return ret;
+}
+
+sw_error_t
+hppe_qm_dbg_addr_dbg_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union qm_dbg_addr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_qm_dbg_addr_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dbg_addr = value;
+	ret = hppe_qm_dbg_addr_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_qm_dbg_data_dbg_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union qm_dbg_data_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_qm_dbg_data_get(dev_id, &reg_val);
+	*value = reg_val.bf.dbg_data;
+	return ret;
+}
+
+sw_error_t
+hppe_qm_dbg_data_dbg_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mcast_priority_map0_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mcast_priority_map0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.class;
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_priority_map0_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mcast_priority_map0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.class = value;
+	ret = hppe_mcast_priority_map0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_priority_map1_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mcast_priority_map1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.class;
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_priority_map1_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mcast_priority_map1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.class = value;
+	ret = hppe_mcast_priority_map1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_priority_map2_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mcast_priority_map2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.class;
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_priority_map2_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mcast_priority_map2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.class = value;
+	ret = hppe_mcast_priority_map2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_priority_map3_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mcast_priority_map3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map3_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.class;
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_priority_map3_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mcast_priority_map3_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map3_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.class = value;
+	ret = hppe_mcast_priority_map3_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_priority_map4_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mcast_priority_map4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.class;
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_priority_map4_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mcast_priority_map4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.class = value;
+	ret = hppe_mcast_priority_map4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_priority_map5_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mcast_priority_map5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map5_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.class;
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_priority_map5_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mcast_priority_map5_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map5_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.class = value;
+	ret = hppe_mcast_priority_map5_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_priority_map6_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mcast_priority_map6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map6_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.class;
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_priority_map6_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mcast_priority_map6_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map6_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.class = value;
+	ret = hppe_mcast_priority_map6_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_priority_map7_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mcast_priority_map7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map7_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.class;
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_priority_map7_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mcast_priority_map7_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_priority_map7_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.class = value;
+	ret = hppe_mcast_priority_map7_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p2_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.mq_p2_en;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p2_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mq_p2_en = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.uq_en_1;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.uq_en_1 = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p0_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.mq_p0_en;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p0_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mq_p0_en = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_1_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.grp_1_en;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_1_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grp_1_en = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_0_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.grp_0_en;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_0_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grp_0_en = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p6_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.mq_p6_en;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p6_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mq_p6_en = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_3_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.uq_en_3;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_3_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.uq_en_3 = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p4_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.mq_p4_en;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p4_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mq_p4_en = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.uq_en_2;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_2_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.uq_en_2 = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_5_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.uq_en_5;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_5_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.uq_en_5 = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_6_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.uq_en_6;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_6_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.uq_en_6 = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_3_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.grp_3_en;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_3_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grp_3_en = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_2_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.grp_2_en;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_grp_2_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grp_2_en = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.uq_en_4;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_4_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.uq_en_4 = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p7_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.mq_p7_en;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p7_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mq_p7_en = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_7_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.uq_en_7;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_7_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.uq_en_7 = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_global_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.global_en;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_global_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.global_en = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p5_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.mq_p5_en;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p5_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mq_p5_en = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p1_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.mq_p1_en;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p1_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mq_p1_en = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.uq_en_0;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_uq_en_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.uq_en_0 = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p3_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	*value = reg_val.bf.mq_p3_en;
+	return ret;
+}
+
+sw_error_t
+hppe_agg_profile_cnt_en_mq_p3_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union agg_profile_cnt_en_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_agg_profile_cnt_en_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mq_p3_en = value;
+	ret = hppe_agg_profile_cnt_en_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uq_agg_profile_cfg_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uq_agg_profile_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uq_agg_profile_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.th_cfg;
+	return ret;
+}
+
+sw_error_t
+hppe_uq_agg_profile_cfg_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uq_agg_profile_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uq_agg_profile_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.th_cfg = value;
+	ret = hppe_uq_agg_profile_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mq_agg_profile_cfg_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mq_agg_profile_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mq_agg_profile_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.th_cfg;
+	return ret;
+}
+
+sw_error_t
+hppe_mq_agg_profile_cfg_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mq_agg_profile_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mq_agg_profile_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.th_cfg = value;
+	ret = hppe_mq_agg_profile_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_grp_agg_profile_cfg_th_cfg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union grp_agg_profile_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_agg_profile_cfg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.th_cfg;
+	return ret;
+}
+
+sw_error_t
+hppe_grp_agg_profile_cfg_th_cfg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union grp_agg_profile_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_agg_profile_cfg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.th_cfg = value;
+	ret = hppe_grp_agg_profile_cfg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uq_agg_in_profile_cnt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uq_agg_in_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uq_agg_in_profile_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_uq_agg_in_profile_cnt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uq_agg_in_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uq_agg_in_profile_cnt_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cnt = value;
+	ret = hppe_uq_agg_in_profile_cnt_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uq_agg_out_profile_cnt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uq_agg_out_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uq_agg_out_profile_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_uq_agg_out_profile_cnt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uq_agg_out_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uq_agg_out_profile_cnt_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cnt = value;
+	ret = hppe_uq_agg_out_profile_cnt_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mq_agg_in_profile_cnt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mq_agg_in_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mq_agg_in_profile_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_mq_agg_in_profile_cnt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mq_agg_in_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mq_agg_in_profile_cnt_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cnt = value;
+	ret = hppe_mq_agg_in_profile_cnt_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mq_agg_out_profile_cnt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mq_agg_out_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mq_agg_out_profile_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_mq_agg_out_profile_cnt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mq_agg_out_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mq_agg_out_profile_cnt_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cnt = value;
+	ret = hppe_mq_agg_out_profile_cnt_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_grp_agg_in_profile_cnt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union grp_agg_in_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_agg_in_profile_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_grp_agg_in_profile_cnt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union grp_agg_in_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_agg_in_profile_cnt_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cnt = value;
+	ret = hppe_grp_agg_in_profile_cnt_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_grp_agg_out_profile_cnt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union grp_agg_out_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_agg_out_profile_cnt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_grp_agg_out_profile_cnt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union grp_agg_out_profile_cnt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_grp_agg_out_profile_cnt_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cnt = value;
+	ret = hppe_grp_agg_out_profile_cnt_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ucast_queue_map_tbl_profile_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ucast_queue_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ucast_queue_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.profile_id;
+	return ret;
+}
+
+sw_error_t
+hppe_ucast_queue_map_tbl_profile_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ucast_queue_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ucast_queue_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.profile_id = value;
+	ret = hppe_ucast_queue_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ucast_queue_map_tbl_queue_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ucast_queue_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ucast_queue_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.queue_id;
+	return ret;
+}
+
+sw_error_t
+hppe_ucast_queue_map_tbl_queue_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ucast_queue_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ucast_queue_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.queue_id = value;
+	ret = hppe_ucast_queue_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ucast_hash_map_tbl_hash_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ucast_hash_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ucast_hash_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.hash;
+	return ret;
+}
+
+sw_error_t
+hppe_ucast_hash_map_tbl_hash_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ucast_hash_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ucast_hash_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hash = value;
+	ret = hppe_ucast_hash_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ucast_priority_map_tbl_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ucast_priority_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ucast_priority_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.class;
+	return ret;
+}
+
+sw_error_t
+hppe_ucast_priority_map_tbl_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ucast_priority_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ucast_priority_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.class = value;
+	ret = hppe_ucast_priority_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_queue_map_tbl_class_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mcast_queue_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_queue_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.class;
+	return ret;
+}
+
+sw_error_t
+hppe_mcast_queue_map_tbl_class_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mcast_queue_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mcast_queue_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.class = value;
+	ret = hppe_mcast_queue_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mseq_tbl_ac_mseq_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mseq_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mseq_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_mseq;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mseq_tbl_ac_mseq_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mseq_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mseq_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_mseq = value;
+	ret = hppe_ac_mseq_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_max_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_gap_grn_yel_max;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_max_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_gap_grn_yel_max = value;
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_wred_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_wred_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_wred_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_wred_en = value;
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_ac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_ac_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_ac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_ac_en = value;
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_red_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_red_resume_offset_1 << 9 | \
+		reg_val.bf.ac_cfg_red_resume_offset_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_red_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_red_resume_offset_1 = value >> 9;
+	reg_val.bf.ac_cfg_red_resume_offset_0 = value & (((a_uint64_t)1<<9)-1);
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_grp_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_grp_id;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_grp_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_grp_id = value;
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_color_aware_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_color_aware;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_color_aware_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_color_aware = value;
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_yel_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_yel_resume_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_yel_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_yel_resume_offset = value;
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_min_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_gap_grn_yel_min_1 << 10 | \
+		reg_val.bf.ac_cfg_gap_grn_yel_min_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_min_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_gap_grn_yel_min_1 = value >> 10;
+	reg_val.bf.ac_cfg_gap_grn_yel_min_0 = value & (((a_uint64_t)1<<10)-1);
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_weight_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_shared_weight;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_weight_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_shared_weight = value;
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_dynamic_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_shared_dynamic;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_dynamic_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_shared_dynamic = value;
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_max_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_gap_grn_red_max;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_max_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_gap_grn_red_max = value;
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_pre_alloc_limit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_pre_alloc_limit;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_pre_alloc_limit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_pre_alloc_limit = value;
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_force_ac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_force_ac_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_force_ac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_force_ac_en = value;
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_min_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_gap_grn_red_min;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_min_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_gap_grn_red_min = value;
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_grn_min_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_gap_grn_grn_min;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_grn_min_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_gap_grn_grn_min = value;
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_ceiling_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_shared_ceiling;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_ceiling_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_shared_ceiling = value;
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_grn_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_grn_resume_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cfg_tbl_ac_cfg_grn_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_grn_resume_offset = value;
+	ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_ac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_ac_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_ac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_ac_en = value;
+	ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_red_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_red_resume_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_red_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_red_resume_offset = value;
+	ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_grp_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_grp_id;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_grp_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_grp_id = value;
+	ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_color_aware_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_color_aware;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_color_aware_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_color_aware = value;
+	ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_yel_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_yel_resume_offset_1 << 4 | \
+		reg_val.bf.ac_cfg_yel_resume_offset_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_yel_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_yel_resume_offset_1 = value >> 4;
+	reg_val.bf.ac_cfg_yel_resume_offset_0 = value & (((a_uint64_t)1<<4)-1);
+	ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_pre_alloc_limit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_pre_alloc_limit;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_pre_alloc_limit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_pre_alloc_limit = value;
+	ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_force_ac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_force_ac_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_force_ac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_force_ac_en = value;
+	ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_shared_ceiling_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_shared_ceiling;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_shared_ceiling_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_shared_ceiling = value;
+	ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_grn_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_grn_resume_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_grn_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_grn_resume_offset = value;
+	ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_yel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_gap_grn_yel_1 << 5 | \
+		reg_val.bf.ac_cfg_gap_grn_yel_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_yel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_gap_grn_yel_1 = value >> 5;
+	reg_val.bf.ac_cfg_gap_grn_yel_0 = value & (((a_uint64_t)1<<5)-1);
+	ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_red_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_gap_grn_red;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_red_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_gap_grn_red = value;
+	ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_grn_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_grp_grn_resume_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_grn_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_grp_grn_resume_offset = value;
+	ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_dp_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_grp_dp_thrd_1 << 7 | \
+		reg_val.bf.ac_grp_dp_thrd_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_dp_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_grp_dp_thrd_1 = value >> 7;
+	reg_val.bf.ac_grp_dp_thrd_0 = value & (((a_uint64_t)1<<7)-1);
+	ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_cfg_ac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_ac_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_cfg_ac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_ac_en = value;
+	ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_palloc_limit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_grp_palloc_limit;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_palloc_limit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_grp_palloc_limit = value;
+	ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_cfg_color_aware_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_color_aware;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_cfg_color_aware_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_color_aware = value;
+	ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_red_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_grp_red_resume_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_red_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_grp_red_resume_offset = value;
+	ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_yel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_grp_gap_grn_yel;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_yel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_grp_gap_grn_yel = value;
+	ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_cfg_force_ac_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_cfg_force_ac_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_cfg_force_ac_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_cfg_force_ac_en = value;
+	ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_yel_resume_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_grp_yel_resume_offset_1 << 6 | \
+		reg_val.bf.ac_grp_yel_resume_offset_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_yel_resume_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_grp_yel_resume_offset_1 = value >> 6;
+	reg_val.bf.ac_grp_yel_resume_offset_0 = value & (((a_uint64_t)1<<6)-1);
+	ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_red_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_grp_gap_grn_red;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_red_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_grp_gap_grn_red = value;
+	ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_limit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_grp_limit;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cfg_tbl_ac_grp_limit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_grp_limit = value;
+	ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cnt_tbl_ac_uni_queue_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_uni_queue_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_cnt_tbl_ac_uni_queue_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_uni_queue_cnt = value;
+	ret = hppe_ac_uni_queue_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cnt_tbl_ac_mul_queue_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_mul_queue_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_cnt_tbl_ac_mul_queue_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_mul_queue_cnt = value;
+	ret = hppe_ac_mul_queue_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cnt_tbl_ac_grp_alloc_used_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_grp_alloc_used;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cnt_tbl_ac_grp_alloc_used_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_grp_alloc_used = value;
+	ret = hppe_ac_grp_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cnt_tbl_ac_grp_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ac_grp_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_cnt_tbl_ac_grp_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ac_grp_cnt = value;
+	ret = hppe_ac_grp_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_red_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.red_resume_thrd;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_red_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.red_resume_thrd = value;
+	ret = hppe_ac_uni_queue_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_red_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.red_drop_state;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_red_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.red_drop_state = value;
+	ret = hppe_ac_uni_queue_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_yel_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.yel_resume_thrd;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_yel_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.yel_resume_thrd = value;
+	ret = hppe_ac_uni_queue_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_grn_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.grn_drop_state;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_grn_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grn_drop_state = value;
+	ret = hppe_ac_uni_queue_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_yel_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.yel_drop_state;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_yel_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.yel_drop_state = value;
+	ret = hppe_ac_uni_queue_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_grn_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_uni_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.grn_resume_thrd_1 << 10 | \
+		reg_val.bf.grn_resume_thrd_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_uni_queue_drop_state_tbl_grn_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_uni_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grn_resume_thrd_1 = value >> 10;
+	reg_val.bf.grn_resume_thrd_0 = value & (((a_uint64_t)1<<10)-1);
+	ret = hppe_ac_uni_queue_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_red_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.red_resume_thrd;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_red_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.red_resume_thrd = value;
+	ret = hppe_ac_mul_queue_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_red_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.red_drop_state;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_red_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.red_drop_state = value;
+	ret = hppe_ac_mul_queue_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_yel_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.yel_resume_thrd;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_yel_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.yel_resume_thrd = value;
+	ret = hppe_ac_mul_queue_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_grn_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.grn_drop_state;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_grn_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grn_drop_state = value;
+	ret = hppe_ac_mul_queue_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_yel_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.yel_drop_state;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_yel_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.yel_drop_state = value;
+	ret = hppe_ac_mul_queue_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_grn_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_mul_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.grn_resume_thrd_1 << 10 | \
+		reg_val.bf.grn_resume_thrd_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_mul_queue_drop_state_tbl_grn_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_mul_queue_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grn_resume_thrd_1 = value >> 10;
+	reg_val.bf.grn_resume_thrd_0 = value & (((a_uint64_t)1<<10)-1);
+	ret = hppe_ac_mul_queue_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_red_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.red_resume_thrd;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_red_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.red_resume_thrd = value;
+	ret = hppe_ac_grp_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_red_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.red_drop_state;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_red_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.red_drop_state = value;
+	ret = hppe_ac_grp_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_yel_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.yel_resume_thrd;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_yel_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.yel_resume_thrd = value;
+	ret = hppe_ac_grp_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_grn_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.grn_drop_state;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_grn_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grn_drop_state = value;
+	ret = hppe_ac_grp_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_yel_drop_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.yel_drop_state;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_yel_drop_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.yel_drop_state = value;
+	ret = hppe_ac_grp_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_grn_resume_thrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ac_grp_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.grn_resume_thrd_1 << 10 | \
+		reg_val.bf.grn_resume_thrd_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ac_grp_drop_state_tbl_grn_resume_thrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ac_grp_drop_state_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grn_resume_thrd_1 = value >> 10;
+	reg_val.bf.grn_resume_thrd_0 = value & (((a_uint64_t)1<<10)-1);
+	ret = hppe_ac_grp_drop_state_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_enq_opr_tbl_enq_disable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_enq_opr_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_enq_opr_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.enq_disable;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_enq_opr_tbl_enq_disable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_enq_opr_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_enq_opr_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.enq_disable = value;
+	ret = hppe_oq_enq_opr_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_deq_opr_tbl_deq_drop_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_deq_opr_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_deq_opr_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.deq_drop;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_deq_opr_tbl_deq_drop_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_deq_opr_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_deq_opr_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.deq_drop = value;
+	ret = hppe_oq_deq_opr_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_uni_tbl_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_head_uni_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_uni_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.head;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_uni_tbl_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_head_uni_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_uni_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.head = value;
+	ret = hppe_oq_head_uni_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_uni_tbl_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_head_uni_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_uni_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tail;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_uni_tbl_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_head_uni_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_uni_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tail = value;
+	ret = hppe_oq_head_uni_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_uni_tbl_empty_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_head_uni_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_uni_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.empty;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_uni_tbl_empty_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_head_uni_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_uni_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.empty = value;
+	ret = hppe_oq_head_uni_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_mul_tbl_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_head_mul_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_mul_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.head;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_mul_tbl_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_head_mul_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_mul_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.head = value;
+	ret = hppe_oq_head_mul_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_mul_tbl_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_head_mul_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_mul_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tail;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_mul_tbl_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_head_mul_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_mul_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tail = value;
+	ret = hppe_oq_head_mul_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_mul_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_head_mul_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_mul_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ingress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_mul_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_head_mul_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_mul_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ingress_mirr = value;
+	ret = hppe_oq_head_mul_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_mul_tbl_empty_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_head_mul_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_mul_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.empty;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_mul_tbl_empty_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_head_mul_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_mul_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.empty = value;
+	ret = hppe_oq_head_mul_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_mul_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_head_mul_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_mul_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.egress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_mul_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_head_mul_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_mul_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.egress_mirr = value;
+	ret = hppe_oq_head_mul_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_mul_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_head_mul_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_mul_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.normal_fwd;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_head_mul_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_head_mul_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_head_mul_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.normal_fwd = value;
+	ret = hppe_oq_head_mul_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_uni_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_uni_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_uni_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_pointer;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_uni_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_uni_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_uni_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.next_pointer = value;
+	ret = hppe_oq_ll_uni_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p0_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_pointer;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p0_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.next_pointer = value;
+	ret = hppe_oq_ll_mul_p0_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p0_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ingress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p0_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ingress_mirr = value;
+	ret = hppe_oq_ll_mul_p0_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p0_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.egress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p0_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.egress_mirr = value;
+	ret = hppe_oq_ll_mul_p0_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p0_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.normal_fwd;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p0_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p0_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.normal_fwd = value;
+	ret = hppe_oq_ll_mul_p0_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p1_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_pointer;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p1_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.next_pointer = value;
+	ret = hppe_oq_ll_mul_p1_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p1_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ingress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p1_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ingress_mirr = value;
+	ret = hppe_oq_ll_mul_p1_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p1_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.egress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p1_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.egress_mirr = value;
+	ret = hppe_oq_ll_mul_p1_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p1_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.normal_fwd;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p1_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p1_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.normal_fwd = value;
+	ret = hppe_oq_ll_mul_p1_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p2_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_pointer;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p2_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.next_pointer = value;
+	ret = hppe_oq_ll_mul_p2_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p2_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ingress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p2_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ingress_mirr = value;
+	ret = hppe_oq_ll_mul_p2_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p2_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.egress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p2_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.egress_mirr = value;
+	ret = hppe_oq_ll_mul_p2_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p2_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.normal_fwd;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p2_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p2_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.normal_fwd = value;
+	ret = hppe_oq_ll_mul_p2_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p3_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_pointer;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p3_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.next_pointer = value;
+	ret = hppe_oq_ll_mul_p3_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p3_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ingress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p3_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ingress_mirr = value;
+	ret = hppe_oq_ll_mul_p3_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p3_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.egress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p3_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.egress_mirr = value;
+	ret = hppe_oq_ll_mul_p3_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p3_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.normal_fwd;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p3_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p3_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.normal_fwd = value;
+	ret = hppe_oq_ll_mul_p3_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p4_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_pointer;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p4_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.next_pointer = value;
+	ret = hppe_oq_ll_mul_p4_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p4_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ingress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p4_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ingress_mirr = value;
+	ret = hppe_oq_ll_mul_p4_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p4_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.egress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p4_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.egress_mirr = value;
+	ret = hppe_oq_ll_mul_p4_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p4_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.normal_fwd;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p4_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p4_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.normal_fwd = value;
+	ret = hppe_oq_ll_mul_p4_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p5_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_pointer;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p5_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.next_pointer = value;
+	ret = hppe_oq_ll_mul_p5_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p5_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ingress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p5_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ingress_mirr = value;
+	ret = hppe_oq_ll_mul_p5_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p5_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.egress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p5_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.egress_mirr = value;
+	ret = hppe_oq_ll_mul_p5_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p5_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.normal_fwd;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p5_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p5_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.normal_fwd = value;
+	ret = hppe_oq_ll_mul_p5_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p6_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_pointer;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p6_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.next_pointer = value;
+	ret = hppe_oq_ll_mul_p6_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p6_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ingress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p6_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ingress_mirr = value;
+	ret = hppe_oq_ll_mul_p6_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p6_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.egress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p6_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.egress_mirr = value;
+	ret = hppe_oq_ll_mul_p6_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p6_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.normal_fwd;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p6_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p6_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.normal_fwd = value;
+	ret = hppe_oq_ll_mul_p6_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_next_pointer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p7_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_pointer;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_next_pointer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p7_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.next_pointer = value;
+	ret = hppe_oq_ll_mul_p7_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_ingress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p7_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ingress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_ingress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p7_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ingress_mirr = value;
+	ret = hppe_oq_ll_mul_p7_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_egress_mirr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p7_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.egress_mirr;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_egress_mirr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p7_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.egress_mirr = value;
+	ret = hppe_oq_ll_mul_p7_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_normal_fwd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union oq_ll_mul_p7_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.normal_fwd;
+	return ret;
+}
+
+sw_error_t
+hppe_oq_ll_mul_p7_tbl_normal_fwd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union oq_ll_mul_p7_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.normal_fwd = value;
+	ret = hppe_oq_ll_mul_p7_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.ip_addr_index_valid;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.ip_addr_index_valid = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_route_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.route_flag;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_route_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.route_flag = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_cpcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.int_cpcp;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_cpcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.int_cpcp = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_pkt_l3_edit_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.pkt_l3_edit_bypass;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_pkt_l3_edit_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.pkt_l3_edit_bypass = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_ctag_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.int_ctag_fmt;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_ctag_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.int_ctag_fmt = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_fake_mac_header_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.fake_mac_header;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_fake_mac_header_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.fake_mac_header = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_acl_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.acl_index;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_acl_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.acl_index = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_l4_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.l4_type;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_l4_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.l4_type = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_svid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.int_svid;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_svid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.int_svid = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_sdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.int_sdei;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_sdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.int_sdei = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_fc_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.fc_en;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_fc_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.fc_en = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_packet_length_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.packet_length_1 << 8 | \
+		reg_val.bf1.packet_length_0;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_packet_length_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.packet_length_1 = value >> 8;
+	reg_val.bf1.packet_length_0 = value & (((a_uint64_t)1<<8)-1);
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_rx_ts_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf1.rx_ts_1 << 24 | \
+		reg_val.bf1.rx_ts_0;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_rx_ts_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.rx_ts_1 = value >> 24;
+	reg_val.bf1.rx_ts_0 = value & (((a_uint64_t)1<<24)-1);
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ts_dir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.ts_dir;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ts_dir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.ts_dir = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_chg_port_vp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.chg_port_vp;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_chg_port_vp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.chg_port_vp = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.int_pri;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.int_pri = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_one_enq_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.one_enq_flag;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_one_enq_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.one_enq_flag = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_fc_grp_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.fc_grp_id;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_fc_grp_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.fc_grp_id = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_fake_l2_prot_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.fake_l2_prot;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_fake_l2_prot_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.fake_l2_prot = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_org_src_port_vp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.org_src_port_vp;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_org_src_port_vp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.org_src_port_vp = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_hash_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.hash_flag;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_hash_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.hash_flag = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_stag_fmt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.int_stag_fmt;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_stag_fmt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.int_stag_fmt = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_service_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.service_code_1 << 2 | \
+		reg_val.bf1.service_code_0;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_service_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.service_code_1 = value >> 2;
+	reg_val.bf1.service_code_0 = value & (((a_uint64_t)1<<2)-1);
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_rx_ptp_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.rx_ptp_type;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_rx_ptp_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.rx_ptp_type = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_mac_da_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf1.mac_da_1 << 18 | \
+		reg_val.bf1.mac_da_0;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_mac_da_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.mac_da_1 = value >> 18;
+	reg_val.bf1.mac_da_0 = value & (((a_uint64_t)1<<18)-1);
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_cpu_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.cpu_code;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_cpu_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.cpu_code = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_eg_vlan_tag_fmt_bypass_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.eg_vlan_tag_fmt_bypass_en;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_eg_vlan_tag_fmt_bypass_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.eg_vlan_tag_fmt_bypass_en = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.ip_addr_index_type;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.ip_addr_index_type = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_cvid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.int_cvid_1 << 9 | \
+		reg_val.bf1.int_cvid_0;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_cvid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.int_cvid_1 = value >> 9;
+	reg_val.bf1.int_cvid_0 = value & (((a_uint64_t)1<<9)-1);
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_eg_vlan_xlt_bypass_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.eg_vlan_xlt_bypass_en;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_eg_vlan_xlt_bypass_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.eg_vlan_xlt_bypass_en = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_hash_value_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.hash_value_1 << 5 | \
+		reg_val.bf1.hash_value_0;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_hash_value_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.hash_value_1 = value >> 5;
+	reg_val.bf1.hash_value_0 = value & (((a_uint64_t)1<<5)-1);
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_stag_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.stag_flag;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_stag_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.stag_flag = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_dst_l3_if_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.dst_l3_if;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_dst_l3_if_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.dst_l3_if = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_cdei_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.int_cdei;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_cdei_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.int_cdei = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_edma_vp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.edma_vp;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_edma_vp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.edma_vp = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ac_group_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.ac_group_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ac_group_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.ac_group_bitmap = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_vp_tx_cnt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.vp_tx_cnt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_vp_tx_cnt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.vp_tx_cnt_en = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_src_port_vp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.src_port_vp;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_src_port_vp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.src_port_vp = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_nat_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.nat_action;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_nat_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.nat_action = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_dscp_update_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.dscp_update;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_dscp_update_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.dscp_update = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_pppoe_strip_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.pppoe_strip_flag;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_pppoe_strip_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.pppoe_strip_flag = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_snap_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.snap_flag;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_snap_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.snap_flag = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_vsi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.vsi;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_vsi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.vsi = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_pkt_l2_edit_bypass_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.pkt_l2_edit_bypass;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_pkt_l2_edit_bypass_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.pkt_l2_edit_bypass = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_tx_ptp_tag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf0.tx_ptp_tag;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_tx_ptp_tag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf0.tx_ptp_tag = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.ip_addr_index_1 << 1 | \
+		reg_val.bf1.ip_addr_index_0;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.ip_addr_index_1 = value >> 1;
+	reg_val.bf1.ip_addr_index_0 = value & (((a_uint64_t)1<<1)-1);
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_dp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.int_dp;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_dp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.int_dp = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_src_pn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.src_pn;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_src_pn_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.src_pn = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_tx_ts_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf0.tx_ts_en;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_tx_ts_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf0.tx_ts_en = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_l4_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.l4_offset_1 << 6 | \
+		reg_val.bf1.l4_offset_0;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_l4_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.l4_offset_1 = value >> 6;
+	reg_val.bf1.l4_offset_0 = value & (((a_uint64_t)1<<6)-1);
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ttl_update_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.ttl_update;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ttl_update_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.ttl_update = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_napt_port_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.napt_port;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_napt_port_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.napt_port = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_napt_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.napt_addr_1 << 13 | \
+		reg_val.bf1.napt_addr_0;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_napt_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.napt_addr_1 = value >> 13;
+	reg_val.bf1.napt_addr_0 = value & (((a_uint64_t)1<<13)-1);
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_copy_cpu_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.copy_cpu_flag;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_copy_cpu_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.copy_cpu_flag = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ttl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.ttl_1 << 3 | \
+		reg_val.bf1.ttl_0;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ttl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.ttl_1 = value >> 3;
+	reg_val.bf1.ttl_0 = value & (((a_uint64_t)1<<3)-1);
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_l3_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.l3_offset;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_l3_offset_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.l3_offset = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_rsv0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.rsv0_1 << 3 | \
+		reg_val.bf1.rsv0_0;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_rsv0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.rsv0_1 = value >> 3;
+	reg_val.bf1.rsv0_0 = value & (((a_uint64_t)1<<3)-1);
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_next_header_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.next_header;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_next_header_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.next_header = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_acl_index_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.acl_index_valid;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_acl_index_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.acl_index_valid = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_rx_ts_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.rx_ts_valid;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_rx_ts_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.rx_ts_valid = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_dscp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.dscp;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_dscp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.dscp = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_acl_index_toggle_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.acl_index_toggle;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_acl_index_toggle_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.acl_index_toggle = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ctag_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.ctag_flag;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ctag_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.ctag_flag = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_toggle_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.ip_addr_index_toggle;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_ip_addr_index_toggle_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.ip_addr_index_toggle = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_tx_os_correction_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf0.tx_os_correction_en;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_tx_os_correction_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf0.tx_os_correction_en = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_spcp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.int_spcp;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_int_spcp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.int_spcp = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_pppoe_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.pppoe_flag;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_pppoe_flag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.pppoe_flag = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_l3_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.l3_type;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_l3_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.l3_type = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_vsi_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf1.vsi_valid;
+	return ret;
+}
+
+sw_error_t
+hppe_pkt_desp_tbl_vsi_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pkt_desp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pkt_desp_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf1.vsi_valid = value;
+	ret = hppe_pkt_desp_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uni_drop_cnt_tbl_uni_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union uni_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uni_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.uni_drop_byte_1 << 32 | \
+		reg_val.bf.uni_drop_byte_0;
+	return ret;
+}
+
+sw_error_t
+hppe_uni_drop_cnt_tbl_uni_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union uni_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uni_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.uni_drop_byte_1 = value >> 32;
+	reg_val.bf.uni_drop_byte_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_uni_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uni_drop_cnt_tbl_uni_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uni_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uni_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.uni_drop_pkt;
+	return ret;
+}
+
+sw_error_t
+hppe_uni_drop_cnt_tbl_uni_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uni_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uni_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.uni_drop_pkt = value;
+	ret = hppe_uni_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mul_p0_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p0_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mul_p0_drop_pkt;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mul_p0_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p0_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p0_drop_pkt = value;
+	ret = hppe_mul_p0_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union mul_p0_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p0_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.mul_p0_drop_byte_1 << 32 | \
+		reg_val.bf.mul_p0_drop_byte_0;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union mul_p0_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p0_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p0_drop_byte_1 = value >> 32;
+	reg_val.bf.mul_p0_drop_byte_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_mul_p0_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union mul_p1_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p1_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.mul_p1_drop_byte_1 << 32 | \
+		reg_val.bf.mul_p1_drop_byte_0;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union mul_p1_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p1_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p1_drop_byte_1 = value >> 32;
+	reg_val.bf.mul_p1_drop_byte_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_mul_p1_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mul_p1_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p1_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mul_p1_drop_pkt;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mul_p1_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p1_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p1_drop_pkt = value;
+	ret = hppe_mul_p1_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mul_p2_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p2_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mul_p2_drop_pkt;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mul_p2_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p2_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p2_drop_pkt = value;
+	ret = hppe_mul_p2_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union mul_p2_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p2_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.mul_p2_drop_byte_1 << 32 | \
+		reg_val.bf.mul_p2_drop_byte_0;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union mul_p2_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p2_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p2_drop_byte_1 = value >> 32;
+	reg_val.bf.mul_p2_drop_byte_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_mul_p2_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mul_p3_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p3_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mul_p3_drop_pkt;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mul_p3_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p3_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p3_drop_pkt = value;
+	ret = hppe_mul_p3_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union mul_p3_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p3_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.mul_p3_drop_byte_1 << 32 | \
+		reg_val.bf.mul_p3_drop_byte_0;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union mul_p3_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p3_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p3_drop_byte_1 = value >> 32;
+	reg_val.bf.mul_p3_drop_byte_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_mul_p3_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mul_p4_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p4_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mul_p4_drop_pkt;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mul_p4_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p4_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p4_drop_pkt = value;
+	ret = hppe_mul_p4_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union mul_p4_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p4_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.mul_p4_drop_byte_1 << 32 | \
+		reg_val.bf.mul_p4_drop_byte_0;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union mul_p4_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p4_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p4_drop_byte_1 = value >> 32;
+	reg_val.bf.mul_p4_drop_byte_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_mul_p4_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union mul_p5_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p5_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.mul_p5_drop_byte_1 << 32 | \
+		reg_val.bf.mul_p5_drop_byte_0;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union mul_p5_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p5_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p5_drop_byte_1 = value >> 32;
+	reg_val.bf.mul_p5_drop_byte_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_mul_p5_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mul_p5_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p5_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mul_p5_drop_pkt;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mul_p5_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p5_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p5_drop_pkt = value;
+	ret = hppe_mul_p5_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union mul_p6_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p6_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.mul_p6_drop_byte_1 << 32 | \
+		reg_val.bf.mul_p6_drop_byte_0;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union mul_p6_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p6_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p6_drop_byte_1 = value >> 32;
+	reg_val.bf.mul_p6_drop_byte_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_mul_p6_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mul_p6_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p6_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mul_p6_drop_pkt;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mul_p6_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p6_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p6_drop_pkt = value;
+	ret = hppe_mul_p6_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_pkt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mul_p7_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p7_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mul_p7_drop_pkt;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_pkt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mul_p7_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p7_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p7_drop_pkt = value;
+	ret = hppe_mul_p7_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_byte_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union mul_p7_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p7_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.mul_p7_drop_byte_1 << 32 | \
+		reg_val.bf.mul_p7_drop_byte_0;
+	return ret;
+}
+
+sw_error_t
+hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_byte_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union mul_p7_drop_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mul_p7_drop_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_p7_drop_byte_1 = value >> 32;
+	reg_val.bf.mul_p7_drop_byte_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_mul_p7_drop_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uq_agg_profile_map_qid_2_agg_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uq_agg_profile_map_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uq_agg_profile_map_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.qid_2_agg_id;
+	return ret;
+}
+
+sw_error_t
+hppe_uq_agg_profile_map_qid_2_agg_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uq_agg_profile_map_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uq_agg_profile_map_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.qid_2_agg_id = value;
+	ret = hppe_uq_agg_profile_map_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uq_agg_profile_map_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uq_agg_profile_map_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uq_agg_profile_map_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.enable;
+	return ret;
+}
+
+sw_error_t
+hppe_uq_agg_profile_map_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uq_agg_profile_map_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uq_agg_profile_map_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.enable = value;
+	ret = hppe_uq_agg_profile_map_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_queue_tx_counter_tbl_tx_bytes_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union queue_tx_counter_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_queue_tx_counter_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.tx_bytes_1 << 32 | \
+		reg_val.bf.tx_bytes_0;
+	return ret;
+}
+
+sw_error_t
+hppe_queue_tx_counter_tbl_tx_bytes_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union queue_tx_counter_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_queue_tx_counter_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_bytes_1 = value >> 32;
+	reg_val.bf.tx_bytes_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_queue_tx_counter_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_queue_tx_counter_tbl_tx_packets_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union queue_tx_counter_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_queue_tx_counter_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_packets;
+	return ret;
+}
+
+sw_error_t
+hppe_queue_tx_counter_tbl_tx_packets_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union queue_tx_counter_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_queue_tx_counter_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_packets = value;
+	ret = hppe_queue_tx_counter_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
diff --git a/qca-ssdk/src/hsl/hppe/hppe_qos.c b/qca-ssdk/src/hsl/hppe/hppe_qos.c
new file mode 100755
index 0000000..f617917
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_qos.c
@@ -0,0 +1,4548 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_qos_reg.h"
+#include "hppe_qos.h"
+
+sw_error_t
+hppe_dscp_qos_group_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union dscp_qos_group_0_u *value)
+{
+	if (index >= DSCP_QOS_GROUP_0_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + DSCP_QOS_GROUP_0_ADDRESS + \
+				index * DSCP_QOS_GROUP_0_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_dscp_qos_group_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union dscp_qos_group_0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + DSCP_QOS_GROUP_0_ADDRESS + \
+				index * DSCP_QOS_GROUP_0_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_dscp_qos_group_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union dscp_qos_group_1_u *value)
+{
+	if (index >= DSCP_QOS_GROUP_1_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + DSCP_QOS_GROUP_1_ADDRESS + \
+				index * DSCP_QOS_GROUP_1_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_dscp_qos_group_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union dscp_qos_group_1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + DSCP_QOS_GROUP_1_ADDRESS + \
+				index * DSCP_QOS_GROUP_1_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_pcp_qos_group_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pcp_qos_group_0_u *value)
+{
+	if (index >= PCP_QOS_GROUP_0_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + PCP_QOS_GROUP_0_ADDRESS + \
+				index * PCP_QOS_GROUP_0_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_pcp_qos_group_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pcp_qos_group_0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + PCP_QOS_GROUP_0_ADDRESS + \
+				index * PCP_QOS_GROUP_0_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_pcp_qos_group_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pcp_qos_group_1_u *value)
+{
+	if (index >= PCP_QOS_GROUP_1_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + PCP_QOS_GROUP_1_ADDRESS + \
+				index * PCP_QOS_GROUP_1_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_pcp_qos_group_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pcp_qos_group_1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + PCP_QOS_GROUP_1_ADDRESS + \
+				index * PCP_QOS_GROUP_1_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_qos_group_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union flow_qos_group_0_u *value)
+{
+	if (index >= FLOW_QOS_GROUP_0_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FLOW_QOS_GROUP_0_ADDRESS + \
+				index * FLOW_QOS_GROUP_0_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_qos_group_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union flow_qos_group_0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + FLOW_QOS_GROUP_0_ADDRESS + \
+				index * FLOW_QOS_GROUP_0_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_flow_qos_group_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union flow_qos_group_1_u *value)
+{
+	if (index >= FLOW_QOS_GROUP_1_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + FLOW_QOS_GROUP_1_ADDRESS + \
+				index * FLOW_QOS_GROUP_1_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_flow_qos_group_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union flow_qos_group_1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + FLOW_QOS_GROUP_1_ADDRESS + \
+				index * FLOW_QOS_GROUP_1_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_port_qos_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_qos_ctrl_u *value)
+{
+	if (index >= PORT_QOS_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + PORT_QOS_CTRL_ADDRESS + \
+				index * PORT_QOS_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_qos_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_qos_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + PORT_QOS_CTRL_ADDRESS + \
+				index * PORT_QOS_CTRL_INC,
+				value->val);
+}
+#ifndef IN_QOS_MINI
+sw_error_t
+hppe_tdm_depth_cfg_get(
+		a_uint32_t dev_id,
+		union tdm_depth_cfg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + TDM_DEPTH_CFG_ADDRESS,
+				&value->val);
+}
+#endif
+sw_error_t
+hppe_tdm_depth_cfg_set(
+		a_uint32_t dev_id,
+		union tdm_depth_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + TDM_DEPTH_CFG_ADDRESS,
+				value->val);
+}
+#ifndef IN_QOS_MINI
+sw_error_t
+hppe_min_max_mode_cfg_get(
+		a_uint32_t dev_id,
+		union min_max_mode_cfg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + MIN_MAX_MODE_CFG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_min_max_mode_cfg_set(
+		a_uint32_t dev_id,
+		union min_max_mode_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + MIN_MAX_MODE_CFG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_tm_dbg_addr_get(
+		a_uint32_t dev_id,
+		union tm_dbg_addr_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + TM_DBG_ADDR_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_tm_dbg_addr_set(
+		a_uint32_t dev_id,
+		union tm_dbg_addr_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + TM_DBG_ADDR_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_tm_dbg_data_get(
+		a_uint32_t dev_id,
+		union tm_dbg_data_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + TM_DBG_DATA_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_tm_dbg_data_set(
+		a_uint32_t dev_id,
+		union tm_dbg_data_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_eco_reserve_0_get(
+		a_uint32_t dev_id,
+		union eco_reserve_0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + ECO_RESERVE_0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_eco_reserve_0_set(
+		a_uint32_t dev_id,
+		union eco_reserve_0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + ECO_RESERVE_0_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_eco_reserve_1_get(
+		a_uint32_t dev_id,
+		union eco_reserve_1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + ECO_RESERVE_1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_eco_reserve_1_set(
+		a_uint32_t dev_id,
+		union eco_reserve_1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + ECO_RESERVE_1_ADDRESS,
+				value->val);
+}
+#endif
+sw_error_t
+hppe_l0_flow_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_flow_map_tbl_u *value)
+{
+	if (index >= L0_FLOW_MAP_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_FLOW_MAP_TBL_ADDRESS + \
+				index * L0_FLOW_MAP_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l0_flow_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_flow_map_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_FLOW_MAP_TBL_ADDRESS + \
+				index * L0_FLOW_MAP_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_l0_c_sp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_sp_cfg_tbl_u *value)
+{
+	if (index >= L0_C_SP_CFG_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_C_SP_CFG_TBL_ADDRESS + \
+				index * L0_C_SP_CFG_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l0_c_sp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_sp_cfg_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_C_SP_CFG_TBL_ADDRESS + \
+				index * L0_C_SP_CFG_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_l0_e_sp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_sp_cfg_tbl_u *value)
+{
+	if (index >= L0_E_SP_CFG_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_E_SP_CFG_TBL_ADDRESS + \
+				index * L0_E_SP_CFG_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l0_e_sp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_sp_cfg_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_E_SP_CFG_TBL_ADDRESS + \
+				index * L0_E_SP_CFG_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_l0_flow_port_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_flow_port_map_tbl_u *value)
+{
+	if (index >= L0_FLOW_PORT_MAP_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_FLOW_PORT_MAP_TBL_ADDRESS + \
+				index * L0_FLOW_PORT_MAP_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l0_flow_port_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_flow_port_map_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_FLOW_PORT_MAP_TBL_ADDRESS + \
+				index * L0_FLOW_PORT_MAP_TBL_INC,
+				value->val);
+}
+#ifndef IN_QOS_MINI
+sw_error_t
+hppe_l0_c_drr_head_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_drr_head_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_C_DRR_HEAD_TBL_ADDRESS + \
+				index * L0_C_DRR_HEAD_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_drr_head_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_drr_head_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_E_DRR_HEAD_TBL_ADDRESS + \
+				index * L0_E_DRR_HEAD_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_drr_head_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_drr_credit_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_drr_credit_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_DRR_CREDIT_TBL_ADDRESS + \
+				index * L0_DRR_CREDIT_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_l0_drr_credit_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_drr_credit_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_c_drr_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_drr_ll_tbl_u *value)
+{
+	if (index >= L0_C_DRR_LL_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_C_DRR_LL_TBL_ADDRESS + \
+				index * L0_C_DRR_LL_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l0_c_drr_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_drr_ll_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_c_drr_reverse_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_drr_reverse_ll_tbl_u *value)
+{
+	if (index >= L0_C_DRR_REVERSE_LL_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_C_DRR_REVERSE_LL_TBL_ADDRESS + \
+				index * L0_C_DRR_REVERSE_LL_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l0_c_drr_reverse_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_c_drr_reverse_ll_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_e_drr_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_drr_ll_tbl_u *value)
+{
+	if (index >= L0_E_DRR_LL_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_E_DRR_LL_TBL_ADDRESS + \
+				index * L0_E_DRR_LL_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l0_e_drr_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_drr_ll_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_e_drr_reverse_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_drr_reverse_ll_tbl_u *value)
+{
+	if (index >= L0_E_DRR_REVERSE_LL_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_E_DRR_REVERSE_LL_TBL_ADDRESS + \
+				index * L0_E_DRR_REVERSE_LL_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l0_e_drr_reverse_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_e_drr_reverse_ll_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_sp_entry_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_sp_entry_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_SP_ENTRY_TBL_ADDRESS + \
+				index * L0_SP_ENTRY_TBL_INC,
+				value->val,
+				5);
+}
+
+sw_error_t
+hppe_l0_sp_entry_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_sp_entry_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_ens_q_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_ens_q_ll_tbl_u *value)
+{
+	if (index >= L0_ENS_Q_LL_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_ENS_Q_LL_TBL_ADDRESS + \
+				index * L0_ENS_Q_LL_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l0_ens_q_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_ens_q_ll_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_ens_q_head_tbl_u *value)
+{
+	if (index >= L0_ENS_Q_HEAD_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_ENS_Q_HEAD_TBL_ADDRESS + \
+				index * L0_ENS_Q_HEAD_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_ens_q_head_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_ens_q_entry_tbl_u *value)
+{
+	if (index >= L0_ENS_Q_ENTRY_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_ENS_Q_ENTRY_TBL_ADDRESS + \
+				index * L0_ENS_Q_ENTRY_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_ens_q_entry_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_flow_status_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_flow_status_tbl_u *value)
+{
+	if (index >= L0_FLOW_STATUS_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_FLOW_STATUS_TBL_ADDRESS + \
+				index * L0_FLOW_STATUS_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l0_flow_status_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_flow_status_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
+sw_error_t
+hppe_ring_q_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ring_q_map_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + RING_Q_MAP_TBL_ADDRESS + \
+				index * RING_Q_MAP_TBL_INC,
+				value->val,
+				10);
+}
+
+sw_error_t
+hppe_ring_q_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ring_q_map_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + RING_Q_MAP_TBL_ADDRESS + \
+				index * RING_Q_MAP_TBL_INC,
+				value->val,
+				10);
+}
+#ifndef IN_QOS_MINI
+sw_error_t
+hppe_rfc_block_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rfc_block_tbl_u *value)
+{
+	if (index >= RFC_BLOCK_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + RFC_BLOCK_TBL_ADDRESS + \
+				index * RFC_BLOCK_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rfc_block_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rfc_block_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rfc_status_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rfc_status_tbl_u *value)
+{
+	if (index >= RFC_STATUS_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + RFC_STATUS_TBL_ADDRESS + \
+				index * RFC_STATUS_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rfc_status_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rfc_status_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
+sw_error_t
+hppe_deq_dis_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union deq_dis_tbl_u *value)
+{
+	if (index >= DEQ_DIS_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + DEQ_DIS_TBL_ADDRESS + \
+				index * DEQ_DIS_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_deq_dis_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union deq_dis_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + DEQ_DIS_TBL_ADDRESS + \
+				index * DEQ_DIS_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_l1_flow_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_flow_map_tbl_u *value)
+{
+	if (index >= L1_FLOW_MAP_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_FLOW_MAP_TBL_ADDRESS + \
+				index * L1_FLOW_MAP_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l1_flow_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_flow_map_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_FLOW_MAP_TBL_ADDRESS + \
+				index * L1_FLOW_MAP_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_l1_c_sp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_sp_cfg_tbl_u *value)
+{
+	if (index >= L1_C_SP_CFG_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_C_SP_CFG_TBL_ADDRESS + \
+				index * L1_C_SP_CFG_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l1_c_sp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_sp_cfg_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_C_SP_CFG_TBL_ADDRESS + \
+				index * L1_C_SP_CFG_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_l1_e_sp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_sp_cfg_tbl_u *value)
+{
+	if (index >= L1_E_SP_CFG_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_E_SP_CFG_TBL_ADDRESS + \
+				index * L1_E_SP_CFG_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l1_e_sp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_sp_cfg_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_E_SP_CFG_TBL_ADDRESS + \
+				index * L1_E_SP_CFG_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_l1_flow_port_map_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_flow_port_map_tbl_u *value)
+{
+	if (index >= L1_FLOW_PORT_MAP_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_FLOW_PORT_MAP_TBL_ADDRESS + \
+				index * L1_FLOW_PORT_MAP_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l1_flow_port_map_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_flow_port_map_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_FLOW_PORT_MAP_TBL_ADDRESS + \
+				index * L1_FLOW_PORT_MAP_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_drr_head_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_C_DRR_HEAD_TBL_ADDRESS + \
+				index * L1_C_DRR_HEAD_TBL_INC,
+				value->val,
+				2);
+}
+#ifndef IN_QOS_MINI
+sw_error_t
+hppe_l1_c_drr_head_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_drr_head_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_drr_head_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_E_DRR_HEAD_TBL_ADDRESS + \
+				index * L1_E_DRR_HEAD_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_drr_head_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_drr_credit_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_drr_credit_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_DRR_CREDIT_TBL_ADDRESS + \
+				index * L1_DRR_CREDIT_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_l1_drr_credit_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_drr_credit_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_c_drr_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_drr_ll_tbl_u *value)
+{
+	if (index >= L1_C_DRR_LL_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_C_DRR_LL_TBL_ADDRESS + \
+				index * L1_C_DRR_LL_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l1_c_drr_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_drr_ll_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_c_drr_reverse_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_drr_reverse_ll_tbl_u *value)
+{
+	if (index >= L1_C_DRR_REVERSE_LL_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_C_DRR_REVERSE_LL_TBL_ADDRESS + \
+				index * L1_C_DRR_REVERSE_LL_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l1_c_drr_reverse_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_c_drr_reverse_ll_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_e_drr_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_drr_ll_tbl_u *value)
+{
+	if (index >= L1_E_DRR_LL_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_E_DRR_LL_TBL_ADDRESS + \
+				index * L1_E_DRR_LL_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l1_e_drr_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_drr_ll_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_e_drr_reverse_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_drr_reverse_ll_tbl_u *value)
+{
+	if (index >= L1_E_DRR_REVERSE_LL_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_E_DRR_REVERSE_LL_TBL_ADDRESS + \
+				index * L1_E_DRR_REVERSE_LL_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l1_e_drr_reverse_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_e_drr_reverse_ll_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_a_flow_entry_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_a_flow_entry_tbl_u *value)
+{
+	if (index >= L1_A_FLOW_ENTRY_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_A_FLOW_ENTRY_TBL_ADDRESS + \
+				index * L1_A_FLOW_ENTRY_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l1_a_flow_entry_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_a_flow_entry_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_b_flow_entry_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_b_flow_entry_tbl_u *value)
+{
+	if (index >= L1_B_FLOW_ENTRY_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_B_FLOW_ENTRY_TBL_ADDRESS + \
+				index * L1_B_FLOW_ENTRY_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l1_b_flow_entry_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_b_flow_entry_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_sp_entry_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_sp_entry_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_SP_ENTRY_TBL_ADDRESS + \
+				index * L1_SP_ENTRY_TBL_INC,
+				value->val,
+				9);
+}
+
+sw_error_t
+hppe_l1_sp_entry_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_sp_entry_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_ens_q_ll_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_ens_q_ll_tbl_u *value)
+{
+	if (index >= L1_ENS_Q_LL_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_ENS_Q_LL_TBL_ADDRESS + \
+				index * L1_ENS_Q_LL_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l1_ens_q_ll_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_ens_q_ll_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_ens_q_head_tbl_u *value)
+{
+	if (index >= L1_ENS_Q_HEAD_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_ENS_Q_HEAD_TBL_ADDRESS + \
+				index * L1_ENS_Q_HEAD_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_ens_q_head_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_ens_q_entry_tbl_u *value)
+{
+	if (index >= L1_ENS_Q_ENTRY_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_ENS_Q_ENTRY_TBL_ADDRESS + \
+				index * L1_ENS_Q_ENTRY_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_ens_q_entry_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_flow_status_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_flow_status_tbl_u *value)
+{
+	if (index >= L1_FLOW_STATUS_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_FLOW_STATUS_TBL_ADDRESS + \
+				index * L1_FLOW_STATUS_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l1_flow_status_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_flow_status_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_psch_tdm_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_tdm_cfg_tbl_u *value)
+{
+	if (index >= PSCH_TDM_CFG_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + PSCH_TDM_CFG_TBL_ADDRESS + \
+				index * PSCH_TDM_CFG_TBL_INC,
+				&value->val);
+}
+#endif
+sw_error_t
+hppe_psch_tdm_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_tdm_cfg_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + PSCH_TDM_CFG_TBL_ADDRESS + \
+				index * PSCH_TDM_CFG_TBL_INC,
+				value->val);
+}
+#ifndef IN_QOS_MINI
+sw_error_t
+hppe_tdm_depth_cfg_tdm_depth_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union tdm_depth_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tdm_depth_cfg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tdm_depth;
+	return ret;
+}
+
+sw_error_t
+hppe_tdm_depth_cfg_tdm_depth_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union tdm_depth_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tdm_depth_cfg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tdm_depth = value;
+	ret = hppe_tdm_depth_cfg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_min_max_mode_cfg_min_max_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union min_max_mode_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_min_max_mode_cfg_get(dev_id, &reg_val);
+	*value = reg_val.bf.min_max_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_min_max_mode_cfg_min_max_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union min_max_mode_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_min_max_mode_cfg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.min_max_mode = value;
+	ret = hppe_min_max_mode_cfg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_tm_dbg_addr_dbg_addr_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union tm_dbg_addr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tm_dbg_addr_get(dev_id, &reg_val);
+	*value = reg_val.bf.dbg_addr;
+	return ret;
+}
+
+sw_error_t
+hppe_tm_dbg_addr_dbg_addr_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union tm_dbg_addr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tm_dbg_addr_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dbg_addr = value;
+	ret = hppe_tm_dbg_addr_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_tm_dbg_data_dbg_data_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union tm_dbg_data_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tm_dbg_data_get(dev_id, &reg_val);
+	*value = reg_val.bf.dbg_data;
+	return ret;
+}
+
+sw_error_t
+hppe_tm_dbg_data_dbg_data_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_eco_reserve_0_eco_res_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union eco_reserve_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eco_reserve_0_get(dev_id, &reg_val);
+	*value = reg_val.bf.eco_res_0;
+	return ret;
+}
+
+sw_error_t
+hppe_eco_reserve_0_eco_res_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union eco_reserve_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eco_reserve_0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.eco_res_0 = value;
+	ret = hppe_eco_reserve_0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eco_reserve_1_eco_res_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union eco_reserve_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eco_reserve_1_get(dev_id, &reg_val);
+	*value = reg_val.bf.eco_res_1;
+	return ret;
+}
+
+sw_error_t
+hppe_eco_reserve_1_eco_res_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union eco_reserve_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eco_reserve_1_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.eco_res_1 = value;
+	ret = hppe_eco_reserve_1_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_flow_map_tbl_e_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_flow_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_pri;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_flow_map_tbl_e_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_flow_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.e_pri = value;
+	ret = hppe_l0_flow_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_flow_map_tbl_c_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_flow_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_pri;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_flow_map_tbl_c_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_flow_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.c_pri = value;
+	ret = hppe_l0_flow_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_flow_map_tbl_e_drr_wt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_flow_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_drr_wt;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_flow_map_tbl_e_drr_wt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_flow_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.e_drr_wt = value;
+	ret = hppe_l0_flow_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_flow_map_tbl_c_drr_wt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_flow_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_drr_wt;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_flow_map_tbl_c_drr_wt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_flow_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.c_drr_wt = value;
+	ret = hppe_l0_flow_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_flow_map_tbl_sp_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_flow_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.sp_id;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_flow_map_tbl_sp_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_flow_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.sp_id = value;
+	ret = hppe_l0_flow_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_c_sp_cfg_tbl_drr_credit_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_c_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_c_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.drr_credit_unit;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_c_sp_cfg_tbl_drr_credit_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_c_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_c_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.drr_credit_unit = value;
+	ret = hppe_l0_c_sp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_c_sp_cfg_tbl_drr_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_c_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_c_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.drr_id;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_c_sp_cfg_tbl_drr_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_c_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_c_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.drr_id = value;
+	ret = hppe_l0_c_sp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_e_sp_cfg_tbl_drr_credit_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_e_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_e_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.drr_credit_unit;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_e_sp_cfg_tbl_drr_credit_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_e_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_e_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.drr_credit_unit = value;
+	ret = hppe_l0_e_sp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_e_sp_cfg_tbl_drr_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_e_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_e_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.drr_id;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_e_sp_cfg_tbl_drr_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_e_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_e_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.drr_id = value;
+	ret = hppe_l0_e_sp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_flow_port_map_tbl_port_num_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_flow_port_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_flow_port_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_num;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_flow_port_map_tbl_port_num_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_flow_port_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_flow_port_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_num = value;
+	ret = hppe_l0_flow_port_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_head;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_vld;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_max_n;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_tail_1 << 8 | \
+		reg_val.bf.active_tail_0;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_head;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_vld;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_max_n;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_active_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_tail;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_c_drr_head_tbl_backup_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_head;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_vld;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_max_n;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_tail_1 << 8 | \
+		reg_val.bf.active_tail_0;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_head;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_vld;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_max_n;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_active_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_tail;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_e_drr_head_tbl_backup_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_drr_credit_tbl_e_drr_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_drr_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_drr_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_drr_credit_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_drr_credit_tbl_e_drr_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_drr_credit_tbl_c_drr_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_drr_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_drr_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_drr_credit_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_drr_credit_tbl_c_drr_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_drr_credit_tbl_c_drr_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_drr_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_drr_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_drr_credit;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_drr_credit_tbl_c_drr_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_drr_credit_tbl_e_drr_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_drr_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_drr_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_drr_credit_1 << 7 | \
+		reg_val.bf.e_drr_credit_0;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_drr_credit_tbl_e_drr_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_c_drr_ll_tbl_next_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_c_drr_ll_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_c_drr_ll_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_ptr;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_c_drr_ll_tbl_next_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_c_drr_reverse_ll_tbl_pre_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_c_drr_reverse_ll_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_c_drr_reverse_ll_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pre_ptr;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_c_drr_reverse_ll_tbl_pre_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_e_drr_ll_tbl_next_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_e_drr_ll_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_e_drr_ll_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_ptr;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_e_drr_ll_tbl_next_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_e_drr_reverse_ll_tbl_pre_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_e_drr_reverse_ll_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_e_drr_reverse_ll_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pre_ptr;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_e_drr_reverse_ll_tbl_pre_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_sp_entry_tbl_entry_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_sp_entry_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_sp_entry_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.entry_vld;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_sp_entry_tbl_entry_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_sp_entry_tbl_entry_path_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union l0_sp_entry_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_sp_entry_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.entry_path_id_1 << 32 | \
+		reg_val.bf.entry_path_id_0;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_sp_entry_tbl_entry_path_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_ens_q_ll_tbl_next_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_ens_q_ll_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_ens_q_ll_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_ptr;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_ens_q_ll_tbl_next_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_ens_q_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_ens_q_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vld;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_ens_q_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_ens_q_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.head;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_ens_q_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_ens_q_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tail;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_ens_q_head_tbl_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_entry_ens_in_q_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_ens_q_entry_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_ens_q_entry_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.entry_ens_in_q;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_entry_ens_in_q_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_entry_ens_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_ens_q_entry_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_ens_q_entry_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.entry_ens_vld;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_entry_ens_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_entry_ens_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_ens_q_entry_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_ens_q_entry_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.entry_ens_type;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_ens_q_entry_tbl_entry_ens_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_flow_status_tbl_en_cdrr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_flow_status_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_flow_status_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.en_cdrr;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_flow_status_tbl_en_cdrr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_flow_status_tbl_en_edrr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_flow_status_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_flow_status_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.en_edrr;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_flow_status_tbl_en_edrr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_flow_status_tbl_en_level_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_flow_status_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_flow_status_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.en_level;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_flow_status_tbl_en_level_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_ring_q_map_tbl_queue_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union ring_q_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ring_q_map_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.queue_bitmap_1 << 32 | \
+		reg_val.bf.queue_bitmap_0;
+	return ret;
+}
+
+sw_error_t
+hppe_ring_q_map_tbl_queue_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union ring_q_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ring_q_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.queue_bitmap_1 = value >> 32;
+	reg_val.bf.queue_bitmap_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_ring_q_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rfc_block_tbl_rfc_block_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rfc_block_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rfc_block_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rfc_block;
+	return ret;
+}
+
+sw_error_t
+hppe_rfc_block_tbl_rfc_block_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rfc_status_tbl_rfc_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rfc_status_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rfc_status_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rfc_status;
+	return ret;
+}
+
+sw_error_t
+hppe_rfc_status_tbl_rfc_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_deq_dis_tbl_deq_dis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union deq_dis_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_deq_dis_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.deq_dis;
+	return ret;
+}
+
+sw_error_t
+hppe_deq_dis_tbl_deq_dis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union deq_dis_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_deq_dis_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.deq_dis = value;
+	ret = hppe_deq_dis_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_flow_map_tbl_e_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_flow_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_pri;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_flow_map_tbl_e_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_flow_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.e_pri = value;
+	ret = hppe_l1_flow_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_flow_map_tbl_c_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_flow_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_pri;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_flow_map_tbl_c_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_flow_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.c_pri = value;
+	ret = hppe_l1_flow_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_flow_map_tbl_e_drr_wt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_flow_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_drr_wt;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_flow_map_tbl_e_drr_wt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_flow_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.e_drr_wt = value;
+	ret = hppe_l1_flow_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_flow_map_tbl_c_drr_wt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_flow_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_drr_wt;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_flow_map_tbl_c_drr_wt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_flow_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.c_drr_wt = value;
+	ret = hppe_l1_flow_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_flow_map_tbl_sp_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_flow_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.sp_id;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_flow_map_tbl_sp_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_flow_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_flow_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.sp_id = value;
+	ret = hppe_l1_flow_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_c_sp_cfg_tbl_drr_credit_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_c_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_c_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.drr_credit_unit;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_c_sp_cfg_tbl_drr_credit_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_c_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_c_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.drr_credit_unit = value;
+	ret = hppe_l1_c_sp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_c_sp_cfg_tbl_drr_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_c_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_c_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.drr_id;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_c_sp_cfg_tbl_drr_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_c_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_c_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.drr_id = value;
+	ret = hppe_l1_c_sp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_e_sp_cfg_tbl_drr_credit_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_e_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_e_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.drr_credit_unit;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_e_sp_cfg_tbl_drr_credit_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_e_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_e_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.drr_credit_unit = value;
+	ret = hppe_l1_e_sp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_e_sp_cfg_tbl_drr_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_e_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_e_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.drr_id;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_e_sp_cfg_tbl_drr_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_e_sp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_e_sp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.drr_id = value;
+	ret = hppe_l1_e_sp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_flow_port_map_tbl_port_num_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_flow_port_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_flow_port_map_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_num;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_flow_port_map_tbl_port_num_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_flow_port_map_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_flow_port_map_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_num = value;
+	ret = hppe_l1_flow_port_map_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_head;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_vld;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_max_n;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_tail;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_head;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_vld;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_max_n_1 << 1 | \
+		reg_val.bf.active_max_n_0;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_active_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_c_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_tail;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_c_drr_head_tbl_backup_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_head;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_vld;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_max_n;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_tail;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_head;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_vld;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_max_n_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.active_max_n_1 << 1 | \
+		reg_val.bf.active_max_n_0;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_active_max_n_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_e_drr_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.backup_tail;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_e_drr_head_tbl_backup_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_drr_credit_tbl_e_drr_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_drr_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_drr_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_drr_credit_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_drr_credit_tbl_e_drr_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_drr_credit_tbl_c_drr_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_drr_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_drr_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_drr_credit_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_drr_credit_tbl_c_drr_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_drr_credit_tbl_c_drr_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_drr_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_drr_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_drr_credit;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_drr_credit_tbl_c_drr_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_drr_credit_tbl_e_drr_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_drr_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_drr_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_drr_credit_1 << 7 | \
+		reg_val.bf.e_drr_credit_0;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_drr_credit_tbl_e_drr_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_c_drr_ll_tbl_next_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_c_drr_ll_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_c_drr_ll_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_ptr;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_c_drr_ll_tbl_next_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_c_drr_reverse_ll_tbl_pre_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_c_drr_reverse_ll_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_c_drr_reverse_ll_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pre_ptr;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_c_drr_reverse_ll_tbl_pre_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_e_drr_ll_tbl_next_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_e_drr_ll_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_e_drr_ll_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_ptr;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_e_drr_ll_tbl_next_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_e_drr_reverse_ll_tbl_pre_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_e_drr_reverse_ll_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_e_drr_reverse_ll_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pre_ptr;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_e_drr_reverse_ll_tbl_pre_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_a_flow_entry_tbl_entry_path_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_a_flow_entry_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_a_flow_entry_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.entry_path_id;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_a_flow_entry_tbl_entry_path_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_b_flow_entry_tbl_entry_path_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_b_flow_entry_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_b_flow_entry_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.entry_path_id;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_b_flow_entry_tbl_entry_path_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_sp_entry_tbl_entry_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_sp_entry_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_sp_entry_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.entry_vld;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_sp_entry_tbl_entry_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_sp_entry_tbl_entry_path_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union l1_sp_entry_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_sp_entry_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.entry_path_id_1 << 32 | \
+		reg_val.bf.entry_path_id_0;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_sp_entry_tbl_entry_path_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_ens_q_ll_tbl_next_ptr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_ens_q_ll_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_ens_q_ll_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_ptr;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_ens_q_ll_tbl_next_ptr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_ens_q_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_ens_q_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vld;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_head_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_ens_q_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_ens_q_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.head;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_head_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_tail_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_ens_q_head_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_ens_q_head_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tail;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_ens_q_head_tbl_tail_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_entry_ens_in_q_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_ens_q_entry_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_ens_q_entry_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.entry_ens_in_q;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_entry_ens_in_q_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_entry_ens_vld_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_ens_q_entry_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_ens_q_entry_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.entry_ens_vld;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_entry_ens_vld_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_entry_ens_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_ens_q_entry_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_ens_q_entry_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.entry_ens_type;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_ens_q_entry_tbl_entry_ens_type_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_flow_status_tbl_en_cdrr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_flow_status_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_flow_status_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.en_cdrr;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_flow_status_tbl_en_cdrr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_flow_status_tbl_en_edrr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_flow_status_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_flow_status_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.en_edrr;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_flow_status_tbl_en_edrr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_flow_status_tbl_en_level_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_flow_status_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_flow_status_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.en_level;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_flow_status_tbl_en_level_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_psch_tdm_cfg_tbl_ens_port_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union psch_tdm_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_tdm_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ens_port;
+	return ret;
+}
+
+sw_error_t
+hppe_psch_tdm_cfg_tbl_ens_port_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union psch_tdm_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_tdm_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ens_port = value;
+	ret = hppe_psch_tdm_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_psch_tdm_cfg_tbl_des_port_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union psch_tdm_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_tdm_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.des_port;
+	return ret;
+}
+
+sw_error_t
+hppe_psch_tdm_cfg_tbl_des_port_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union psch_tdm_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_tdm_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.des_port = value;
+	ret = hppe_psch_tdm_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_psch_tdm_cfg_tbl_ens_port_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union psch_tdm_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_tdm_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ens_port_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_psch_tdm_cfg_tbl_ens_port_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union psch_tdm_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_tdm_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ens_port_bitmap = value;
+	ret = hppe_psch_tdm_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_flow_qos_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_flow_qos_pri;
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_flow_qos_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_flow_qos_pri = value;
+	ret = hppe_port_qos_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_dscp_qos_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_dscp_qos_pri;
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_dscp_qos_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_dscp_qos_pri = value;
+	ret = hppe_port_qos_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_dscp_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_dscp_change_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_dscp_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_dscp_change_en = value;
+	ret = hppe_port_qos_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_pcp_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_pcp_change_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_pcp_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_pcp_change_en = value;
+	ret = hppe_port_qos_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_acl_qos_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_acl_qos_pri;
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_acl_qos_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_acl_qos_pri = value;
+	ret = hppe_port_qos_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_flow_qos_group_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.flow_qos_group_id;
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_flow_qos_group_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.flow_qos_group_id = value;
+	ret = hppe_port_qos_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_preheader_qos_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_preheader_qos_pri;
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_preheader_qos_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_preheader_qos_pri = value;
+	ret = hppe_port_qos_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_pcp_qos_group_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pcp_qos_group_id;
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_pcp_qos_group_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pcp_qos_group_id = value;
+	ret = hppe_port_qos_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_dscp_qos_group_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dscp_qos_group_id;
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_dscp_qos_group_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dscp_qos_group_id = value;
+	ret = hppe_port_qos_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_pcp_qos_pri_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_pcp_qos_pri;
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_pcp_qos_pri_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_pcp_qos_pri = value;
+	ret = hppe_port_qos_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_dei_change_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_dei_change_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_qos_ctrl_port_dei_change_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_qos_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_qos_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_dei_change_en = value;
+	ret = hppe_port_qos_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pcp_qos_group_0_qos_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pcp_qos_group_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pcp_qos_group_0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.qos_info;
+	return ret;
+}
+
+sw_error_t
+hppe_pcp_qos_group_0_qos_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pcp_qos_group_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pcp_qos_group_0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.qos_info = value;
+	ret = hppe_pcp_qos_group_0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pcp_qos_group_1_qos_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pcp_qos_group_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pcp_qos_group_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.qos_info;
+	return ret;
+}
+
+sw_error_t
+hppe_pcp_qos_group_1_qos_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pcp_qos_group_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pcp_qos_group_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.qos_info = value;
+	ret = hppe_pcp_qos_group_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_qos_group_0_qos_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_qos_group_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_qos_group_0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.qos_info;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_qos_group_0_qos_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_qos_group_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_qos_group_0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.qos_info = value;
+	ret = hppe_flow_qos_group_0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_flow_qos_group_1_qos_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union flow_qos_group_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_qos_group_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.qos_info;
+	return ret;
+}
+
+sw_error_t
+hppe_flow_qos_group_1_qos_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union flow_qos_group_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_flow_qos_group_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.qos_info = value;
+	ret = hppe_flow_qos_group_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_dscp_qos_group_0_qos_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union dscp_qos_group_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_dscp_qos_group_0_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.qos_info;
+	return ret;
+}
+
+sw_error_t
+hppe_dscp_qos_group_0_qos_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union dscp_qos_group_0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_dscp_qos_group_0_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.qos_info = value;
+	ret = hppe_dscp_qos_group_0_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_dscp_qos_group_1_qos_info_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union dscp_qos_group_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_dscp_qos_group_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.qos_info;
+	return ret;
+}
+
+sw_error_t
+hppe_dscp_qos_group_1_qos_info_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union dscp_qos_group_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_dscp_qos_group_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.qos_info = value;
+	ret = hppe_dscp_qos_group_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
\ No newline at end of file
diff --git a/qca-ssdk/src/hsl/hppe/hppe_reg_access.c b/qca-ssdk/src/hsl/hppe/hppe_reg_access.c
new file mode 100755
index 0000000..a7eeeda
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_reg_access.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "ssdk_init.h"
+#include <linux/kconfig.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <generated/autoconf.h>
+#include <linux/delay.h>
+#include <linux/phy.h>
+#include <linux/netdevice.h>
+#include "ssdk_plat.h"
+#include <linux/string.h>
+
+sw_error_t hppe_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t *val)
+{
+	qca_switch_reg_read(dev_id, reg_addr, (a_uint8_t *)val, 4);
+	return SW_OK;
+}
+
+sw_error_t hppe_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t val) 
+{
+	qca_switch_reg_write(dev_id, reg_addr, (a_uint8_t *)&val, 4);
+	return SW_OK; 
+}
+
+sw_error_t hppe_reg_tbl_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t *val, a_uint32_t num)   
+{
+	a_uint32_t i = 0;
+	for(i = 0; i < num; i++) {
+		hppe_reg_get(dev_id, (reg_addr + i *4), &val[i]);
+	}
+	return SW_OK;
+}
+
+sw_error_t hppe_reg_tbl_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t *val, a_uint32_t num)   
+{
+	a_uint32_t i = 0;
+	for(i = 0; i < num; i++) {
+		hppe_reg_set(dev_id, (reg_addr + i *4), val[i]);
+	}
+	return SW_OK;   
+} 
+
+sw_error_t hppe_uniphy_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t index, a_uint32_t *val)
+{
+	qca_uniphy_reg_read(dev_id, index, reg_addr, (a_uint8_t *)val, 4);
+	return SW_OK;
+}
+
+sw_error_t hppe_uniphy_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t index, a_uint32_t val)
+{
+	qca_uniphy_reg_write(dev_id, index, reg_addr, (a_uint8_t *)&val, 4);
+	return SW_OK;
+}
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_rss.c b/qca-ssdk/src/hsl/hppe/hppe_rss.c
new file mode 100755
index 0000000..d1ec5c3
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_rss.c
@@ -0,0 +1,585 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_rss_reg.h"
+#include "hppe_rss.h"
+
+sw_error_t
+hppe_rss_hash_mask_reg_get(
+		a_uint32_t dev_id,
+		union rss_hash_mask_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_MASK_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_rss_hash_mask_reg_set(
+		a_uint32_t dev_id,
+		union rss_hash_mask_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_MASK_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_rss_hash_seed_reg_get(
+		a_uint32_t dev_id,
+		union rss_hash_seed_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_SEED_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_rss_hash_seed_reg_set(
+		a_uint32_t dev_id,
+		union rss_hash_seed_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_SEED_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_rss_hash_mix_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_mix_reg_u *value)
+{
+	if (index >= RSS_HASH_MIX_REG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_MIX_REG_ADDRESS + \
+				index * RSS_HASH_MIX_REG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rss_hash_mix_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_mix_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_MIX_REG_ADDRESS + \
+				index * RSS_HASH_MIX_REG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_rss_hash_fin_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_fin_reg_u *value)
+{
+	if (index >= RSS_HASH_FIN_REG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_FIN_REG_ADDRESS + \
+				index * RSS_HASH_FIN_REG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rss_hash_fin_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_fin_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_FIN_REG_ADDRESS + \
+				index * RSS_HASH_FIN_REG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_rss_hash_mask_ipv4_reg_get(
+		a_uint32_t dev_id,
+		union rss_hash_mask_ipv4_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_MASK_IPV4_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_rss_hash_mask_ipv4_reg_set(
+		a_uint32_t dev_id,
+		union rss_hash_mask_ipv4_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_MASK_IPV4_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_rss_hash_seed_ipv4_reg_get(
+		a_uint32_t dev_id,
+		union rss_hash_seed_ipv4_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_SEED_IPV4_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_rss_hash_seed_ipv4_reg_set(
+		a_uint32_t dev_id,
+		union rss_hash_seed_ipv4_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_SEED_IPV4_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_rss_hash_mix_ipv4_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_mix_ipv4_reg_u *value)
+{
+	if (index >= RSS_HASH_MIX_IPV4_REG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_MIX_IPV4_REG_ADDRESS + \
+				index * RSS_HASH_MIX_IPV4_REG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rss_hash_mix_ipv4_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_mix_ipv4_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_MIX_IPV4_REG_ADDRESS + \
+				index * RSS_HASH_MIX_IPV4_REG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_rss_hash_fin_ipv4_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_fin_ipv4_reg_u *value)
+{
+	if (index >= RSS_HASH_FIN_IPV4_REG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_FIN_IPV4_REG_ADDRESS + \
+				index * RSS_HASH_FIN_IPV4_REG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rss_hash_fin_ipv4_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rss_hash_fin_ipv4_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPO_CSR_BASE_ADDR + RSS_HASH_FIN_IPV4_REG_ADDRESS + \
+				index * RSS_HASH_FIN_IPV4_REG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_rss_hash_mask_reg_fragment_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union rss_hash_mask_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_mask_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.fragment;
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_mask_reg_fragment_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union rss_hash_mask_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_mask_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fragment = value;
+	ret = hppe_rss_hash_mask_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_mask_reg_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union rss_hash_mask_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_mask_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.mask;
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_mask_reg_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union rss_hash_mask_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_mask_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mask = value;
+	ret = hppe_rss_hash_mask_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_seed_reg_seed_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union rss_hash_seed_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_seed_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.seed;
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_seed_reg_seed_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union rss_hash_seed_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_seed_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.seed = value;
+	ret = hppe_rss_hash_seed_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_mix_reg_hash_mix_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rss_hash_mix_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_mix_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.hash_mix;
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_mix_reg_hash_mix_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rss_hash_mix_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_mix_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hash_mix = value;
+	ret = hppe_rss_hash_mix_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_fin_reg_fin_outer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rss_hash_fin_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_fin_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.fin_outer;
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_fin_reg_fin_outer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rss_hash_fin_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_fin_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fin_outer = value;
+	ret = hppe_rss_hash_fin_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_fin_reg_fin_inner_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rss_hash_fin_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_fin_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.fin_inner;
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_fin_reg_fin_inner_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rss_hash_fin_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_fin_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fin_inner = value;
+	ret = hppe_rss_hash_fin_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_mask_ipv4_reg_fragment_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union rss_hash_mask_ipv4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_mask_ipv4_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.fragment;
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_mask_ipv4_reg_fragment_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union rss_hash_mask_ipv4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_mask_ipv4_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fragment = value;
+	ret = hppe_rss_hash_mask_ipv4_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_mask_ipv4_reg_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union rss_hash_mask_ipv4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_mask_ipv4_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.mask;
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_mask_ipv4_reg_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union rss_hash_mask_ipv4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_mask_ipv4_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mask = value;
+	ret = hppe_rss_hash_mask_ipv4_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_seed_ipv4_reg_seed_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union rss_hash_seed_ipv4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_seed_ipv4_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.seed;
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_seed_ipv4_reg_seed_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union rss_hash_seed_ipv4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_seed_ipv4_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.seed = value;
+	ret = hppe_rss_hash_seed_ipv4_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_mix_ipv4_reg_hash_mix_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rss_hash_mix_ipv4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_mix_ipv4_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.hash_mix;
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_mix_ipv4_reg_hash_mix_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rss_hash_mix_ipv4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_mix_ipv4_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hash_mix = value;
+	ret = hppe_rss_hash_mix_ipv4_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_fin_ipv4_reg_fin_outer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rss_hash_fin_ipv4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_fin_ipv4_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.fin_outer;
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_fin_ipv4_reg_fin_outer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rss_hash_fin_ipv4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_fin_ipv4_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fin_outer = value;
+	ret = hppe_rss_hash_fin_ipv4_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_fin_ipv4_reg_fin_inner_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rss_hash_fin_ipv4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_fin_ipv4_reg_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.fin_inner;
+	return ret;
+}
+
+sw_error_t
+hppe_rss_hash_fin_ipv4_reg_fin_inner_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union rss_hash_fin_ipv4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rss_hash_fin_ipv4_reg_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fin_inner = value;
+	ret = hppe_rss_hash_fin_ipv4_reg_set(dev_id, index, &reg_val);
+	return ret;
+}
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_sec.c b/qca-ssdk/src/hsl/hppe/hppe_sec.c
new file mode 100755
index 0000000..992f47c
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_sec.c
@@ -0,0 +1,1041 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_sec_reg.h"
+#include "hppe_sec.h"
+
+sw_error_t
+hppe_l3_exception_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exception_cmd_u *value)
+{
+	if (index >= L3_EXCEPTION_CMD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_EXCEPTION_CMD_ADDRESS + \
+				index * L3_EXCEPTION_CMD_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l3_exception_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exception_cmd_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_EXCEPTION_CMD_ADDRESS + \
+				index * L3_EXCEPTION_CMD_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_l3_exp_l3_only_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l3_only_ctrl_u *value)
+{
+	if (index >= L3_EXP_L3_ONLY_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_EXP_L3_ONLY_CTRL_ADDRESS + \
+				index * L3_EXP_L3_ONLY_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l3_exp_l3_only_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l3_only_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_EXP_L3_ONLY_CTRL_ADDRESS + \
+				index * L3_EXP_L3_ONLY_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_l3_exp_l2_only_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l2_only_ctrl_u *value)
+{
+	if (index >= L3_EXP_L2_ONLY_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_EXP_L2_ONLY_CTRL_ADDRESS + \
+				index * L3_EXP_L2_ONLY_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l3_exp_l2_only_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l2_only_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_EXP_L2_ONLY_CTRL_ADDRESS + \
+				index * L3_EXP_L2_ONLY_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_l3_exp_l2_flow_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l2_flow_ctrl_u *value)
+{
+	if (index >= L3_EXP_L2_FLOW_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_EXP_L2_FLOW_CTRL_ADDRESS + \
+				index * L3_EXP_L2_FLOW_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l3_exp_l2_flow_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l2_flow_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_EXP_L2_FLOW_CTRL_ADDRESS + \
+				index * L3_EXP_L2_FLOW_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_l3_exp_l3_flow_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l3_flow_ctrl_u *value)
+{
+	if (index >= L3_EXP_L3_FLOW_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_EXP_L3_FLOW_CTRL_ADDRESS + \
+				index * L3_EXP_L3_FLOW_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l3_exp_l3_flow_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_l3_flow_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_EXP_L3_FLOW_CTRL_ADDRESS + \
+				index * L3_EXP_L3_FLOW_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_l3_exp_multicast_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_multicast_ctrl_u *value)
+{
+	if (index >= L3_EXP_MULTICAST_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_EXP_MULTICAST_CTRL_ADDRESS + \
+				index * L3_EXP_MULTICAST_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l3_exp_multicast_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l3_exp_multicast_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L3_BASE_ADDR + L3_EXP_MULTICAST_CTRL_ADDRESS + \
+				index * L3_EXP_MULTICAST_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_l3_exception_cmd_l3_excep_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_exception_cmd_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exception_cmd_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.l3_excep_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exception_cmd_l3_excep_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_exception_cmd_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exception_cmd_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l3_excep_cmd = value;
+	ret = hppe_l3_exception_cmd_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exception_cmd_de_acce_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_exception_cmd_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exception_cmd_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.de_acce;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exception_cmd_de_acce_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_exception_cmd_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exception_cmd_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.de_acce = value;
+	ret = hppe_l3_exception_cmd_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exp_l3_only_ctrl_excep_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_exp_l3_only_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exp_l3_only_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.excep_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exp_l3_only_ctrl_excep_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_exp_l3_only_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exp_l3_only_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.excep_en = value;
+	ret = hppe_l3_exp_l3_only_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exp_l2_only_ctrl_excep_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_exp_l2_only_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exp_l2_only_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.excep_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exp_l2_only_ctrl_excep_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_exp_l2_only_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exp_l2_only_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.excep_en = value;
+	ret = hppe_l3_exp_l2_only_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exp_l2_flow_ctrl_excep_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_exp_l2_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exp_l2_flow_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.excep_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exp_l2_flow_ctrl_excep_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_exp_l2_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exp_l2_flow_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.excep_en = value;
+	ret = hppe_l3_exp_l2_flow_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exp_l3_flow_ctrl_excep_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_exp_l3_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exp_l3_flow_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.excep_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exp_l3_flow_ctrl_excep_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_exp_l3_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exp_l3_flow_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.excep_en = value;
+	ret = hppe_l3_exp_l3_flow_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exp_multicast_ctrl_excep_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l3_exp_multicast_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exp_multicast_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.excep_en;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exp_multicast_ctrl_excep_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l3_exp_multicast_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exp_multicast_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.excep_en = value;
+	ret = hppe_l3_exp_multicast_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exception_parsing_ctrl_reg_get(
+		a_uint32_t dev_id,
+		union l3_exception_parsing_ctrl_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + L3_EXCEPTION_PARSING_CTRL_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l3_exception_parsing_ctrl_reg_set(
+		a_uint32_t dev_id,
+		union l3_exception_parsing_ctrl_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + L3_EXCEPTION_PARSING_CTRL_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_get(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_0_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_0_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_set(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_0_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_0_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_get(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_1_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_1_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_set(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_1_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_1_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_get(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_2_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_2_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_set(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_2_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_2_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_get(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_3_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_3_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_set(
+		a_uint32_t dev_id,
+		union l4_exception_parsing_ctrl_3_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_3_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_l3_exception_parsing_ctrl_reg_small_hop_limit_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_exception_parsing_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exception_parsing_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.small_hop_limit;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exception_parsing_ctrl_reg_small_hop_limit_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_exception_parsing_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exception_parsing_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.small_hop_limit = value;
+	ret = hppe_l3_exception_parsing_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exception_parsing_ctrl_reg_small_ttl_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l3_exception_parsing_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exception_parsing_ctrl_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.small_ttl;
+	return ret;
+}
+
+sw_error_t
+hppe_l3_exception_parsing_ctrl_reg_small_ttl_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l3_exception_parsing_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l3_exception_parsing_ctrl_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.small_ttl = value;
+	ret = hppe_l3_exception_parsing_ctrl_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags0;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags0 = value;
+	ret = hppe_l4_exception_parsing_ctrl_0_reg_set(dev_id, &reg_val);
+	return ret;
+}
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags0_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags0_mask = value;
+	ret = hppe_l4_exception_parsing_ctrl_0_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags1;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags1 = value;
+	ret = hppe_l4_exception_parsing_ctrl_0_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags1_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags1_mask = value;
+	ret = hppe_l4_exception_parsing_ctrl_0_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags2;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags2 = value;
+	ret = hppe_l4_exception_parsing_ctrl_1_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags2_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags2_mask = value;
+	ret = hppe_l4_exception_parsing_ctrl_1_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags3;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags3 = value;
+	ret = hppe_l4_exception_parsing_ctrl_1_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags3_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags3_mask = value;
+	ret = hppe_l4_exception_parsing_ctrl_1_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags4;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags4 = value;
+	ret = hppe_l4_exception_parsing_ctrl_2_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags4_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags4_mask = value;
+	ret = hppe_l4_exception_parsing_ctrl_2_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags5;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags5 = value;
+	ret = hppe_l4_exception_parsing_ctrl_2_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags5_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags5_mask = value;
+	ret = hppe_l4_exception_parsing_ctrl_2_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags6;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags6 = value;
+	ret = hppe_l4_exception_parsing_ctrl_3_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags6_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags6_mask = value;
+	ret = hppe_l4_exception_parsing_ctrl_3_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags7;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags7 = value;
+	ret = hppe_l4_exception_parsing_ctrl_3_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_mask_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union l4_exception_parsing_ctrl_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.tcp_flags7_mask;
+	return ret;
+}
+
+sw_error_t
+hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_mask_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union l4_exception_parsing_ctrl_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tcp_flags7_mask = value;
+	ret = hppe_l4_exception_parsing_ctrl_3_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_servcode.c b/qca-ssdk/src/hsl/hppe/hppe_servcode.c
new file mode 100755
index 0000000..0f5246a
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_servcode.c
@@ -0,0 +1,511 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_servcode_reg.h"
+#include "hppe_servcode.h"
+
+sw_error_t
+hppe_service_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union service_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + SERVICE_TBL_ADDRESS + \
+				index * SERVICE_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_service_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union service_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_VLAN_BASE_ADDR + SERVICE_TBL_ADDRESS + \
+				index * SERVICE_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_service_tbl_rx_counting_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_service_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_counting_en;
+	return ret;
+}
+
+sw_error_t
+hppe_service_tbl_rx_counting_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_service_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_counting_en = value;
+	ret = hppe_service_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_service_tbl_bypass_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_service_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.bypass_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_service_tbl_bypass_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_service_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.bypass_bitmap = value;
+	ret = hppe_service_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l2_service_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_l2_service_tbl_u *value)
+{
+	if (index >= IN_L2_SERVICE_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + IN_L2_SERVICE_TBL_ADDRESS + \
+				index * IN_L2_SERVICE_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_in_l2_service_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union in_l2_service_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + IN_L2_SERVICE_TBL_ADDRESS + \
+				index * IN_L2_SERVICE_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_in_l2_service_tbl_direction_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l2_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l2_service_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.direction;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l2_service_tbl_direction_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l2_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l2_service_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.direction = value;
+	ret = hppe_in_l2_service_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l2_service_tbl_rx_cnt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l2_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l2_service_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_cnt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l2_service_tbl_rx_cnt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l2_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l2_service_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_cnt_en = value;
+	ret = hppe_in_l2_service_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l2_service_tbl_tx_cnt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l2_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l2_service_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_cnt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l2_service_tbl_tx_cnt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l2_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l2_service_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_cnt_en = value;
+	ret = hppe_in_l2_service_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l2_service_tbl_bypass_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l2_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l2_service_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.bypass_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l2_service_tbl_bypass_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l2_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l2_service_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.bypass_bitmap = value;
+	ret = hppe_in_l2_service_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l2_service_tbl_dst_port_id_valid_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l2_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l2_service_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dst_port_id_valid;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l2_service_tbl_dst_port_id_valid_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l2_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l2_service_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dst_port_id_valid = value;
+	ret = hppe_in_l2_service_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_in_l2_service_tbl_dst_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union in_l2_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l2_service_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dst_port_id;
+	return ret;
+}
+
+sw_error_t
+hppe_in_l2_service_tbl_dst_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union in_l2_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_in_l2_service_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dst_port_id = value;
+	ret = hppe_in_l2_service_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_service_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_service_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_SERVICE_TBL_ADDRESS + \
+				index * EG_SERVICE_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_eg_service_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_service_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_SERVICE_TBL_ADDRESS + \
+				index * EG_SERVICE_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_eg_service_tbl_next_service_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_service_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.next_service_code;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_service_tbl_next_service_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_service_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.next_service_code = value;
+	ret = hppe_eg_service_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_service_tbl_tx_counting_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_service_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_counting_en;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_service_tbl_tx_counting_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_service_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_counting_en = value;
+	ret = hppe_eg_service_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_service_tbl_field_update_action_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_service_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.field_update_action;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_service_tbl_field_update_action_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_service_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.field_update_action = value;
+	ret = hppe_eg_service_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_service_tbl_offset_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_service_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.offset_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_service_tbl_offset_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_service_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.offset_sel = value;
+	ret = hppe_eg_service_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_service_tbl_hw_services_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_service_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.hw_services;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_service_tbl_hw_services_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_service_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_service_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hw_services = value;
+	ret = hppe_eg_service_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
\ No newline at end of file
diff --git a/qca-ssdk/src/hsl/hppe/hppe_shaper.c b/qca-ssdk/src/hsl/hppe/hppe_shaper.c
new file mode 100755
index 0000000..339d357
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_shaper.c
@@ -0,0 +1,2396 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_shaper_reg.h"
+#include "hppe_shaper.h"
+
+sw_error_t
+hppe_shp_slot_cfg_l0_get(
+		a_uint32_t dev_id,
+		union shp_slot_cfg_l0_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + SHP_SLOT_CFG_L0_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_shp_slot_cfg_l0_set(
+		a_uint32_t dev_id,
+		union shp_slot_cfg_l0_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + SHP_SLOT_CFG_L0_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_shp_slot_cfg_l1_get(
+		a_uint32_t dev_id,
+		union shp_slot_cfg_l1_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + SHP_SLOT_CFG_L1_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_shp_slot_cfg_l1_set(
+		a_uint32_t dev_id,
+		union shp_slot_cfg_l1_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + SHP_SLOT_CFG_L1_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_shp_slot_cfg_port_get(
+		a_uint32_t dev_id,
+		union shp_slot_cfg_port_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + SHP_SLOT_CFG_PORT_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_shp_slot_cfg_port_set(
+		a_uint32_t dev_id,
+		union shp_slot_cfg_port_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + SHP_SLOT_CFG_PORT_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_l0_shp_credit_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_shp_credit_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_SHP_CREDIT_TBL_ADDRESS + \
+				index * L0_SHP_CREDIT_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_l0_shp_credit_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_shp_credit_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_SHP_CREDIT_TBL_ADDRESS + \
+				index * L0_SHP_CREDIT_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_shp_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_SHP_CFG_TBL_ADDRESS + \
+				index * L0_SHP_CFG_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_shp_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_SHP_CFG_TBL_ADDRESS + \
+				index * L0_SHP_CFG_TBL_INC,
+				value->val,
+				3);
+}
+
+#ifndef IN_SHAPER_MINI
+sw_error_t
+hppe_l0_comp_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_comp_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_COMP_TBL_ADDRESS + \
+				index * L0_COMP_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_l0_comp_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_comp_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
+
+sw_error_t
+hppe_l0_comp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_comp_cfg_tbl_u *value)
+{
+	if (index >= L0_COMP_CFG_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_COMP_CFG_TBL_ADDRESS + \
+				index * L0_COMP_CFG_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l0_comp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l0_comp_cfg_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L0_COMP_CFG_TBL_ADDRESS + \
+				index * L0_COMP_CFG_TBL_INC,
+				value->val);
+}
+
+
+sw_error_t
+hppe_l1_shp_credit_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_shp_credit_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_SHP_CREDIT_TBL_ADDRESS + \
+				index * L1_SHP_CREDIT_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_l1_shp_credit_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_shp_credit_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_SHP_CREDIT_TBL_ADDRESS + \
+				index * L1_SHP_CREDIT_TBL_INC,
+				value->val,
+				2);
+}
+
+#ifndef IN_SHAPER_MINI
+sw_error_t
+hppe_l1_shp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_shp_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_SHP_CFG_TBL_ADDRESS + \
+				index * L1_SHP_CFG_TBL_INC,
+				value->val,
+				3);
+}
+#endif
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_shp_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_SHP_CFG_TBL_ADDRESS + \
+				index * L1_SHP_CFG_TBL_INC,
+				value->val,
+				3);
+}
+
+
+#ifndef IN_SHAPER_MINI
+sw_error_t
+hppe_l1_comp_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_comp_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_COMP_TBL_ADDRESS + \
+				index * L1_COMP_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_l1_comp_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_comp_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
+
+sw_error_t
+hppe_l1_comp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_comp_cfg_tbl_u *value)
+{
+	if (index >= L1_COMP_CFG_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_COMP_CFG_TBL_ADDRESS + \
+				index * L1_COMP_CFG_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_l1_comp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union l1_comp_cfg_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + L1_COMP_CFG_TBL_ADDRESS + \
+				index * L1_COMP_CFG_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_psch_shp_sign_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_shp_sign_tbl_u *value)
+{
+	if (index >= PSCH_SHP_SIGN_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + PSCH_SHP_SIGN_TBL_ADDRESS + \
+				index * PSCH_SHP_SIGN_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_psch_shp_sign_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_shp_sign_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + PSCH_SHP_SIGN_TBL_ADDRESS + \
+				index * PSCH_SHP_SIGN_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_psch_shp_credit_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_shp_credit_tbl_u *value)
+{
+	if (index >= PSCH_SHP_CREDIT_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + PSCH_SHP_CREDIT_TBL_ADDRESS + \
+				index * PSCH_SHP_CREDIT_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_psch_shp_credit_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_shp_credit_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + PSCH_SHP_CREDIT_TBL_ADDRESS + \
+				index * PSCH_SHP_CREDIT_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_shp_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + PSCH_SHP_CFG_TBL_ADDRESS + \
+				index * PSCH_SHP_CFG_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_shp_cfg_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + PSCH_SHP_CFG_TBL_ADDRESS + \
+				index * PSCH_SHP_CFG_TBL_INC,
+				value->val,
+				2);
+}
+
+#ifndef IN_SHAPER_MINI
+sw_error_t
+hppe_psch_comp_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_comp_tbl_u *value)
+{
+	if (index >= PSCH_COMP_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + PSCH_COMP_TBL_ADDRESS + \
+				index * PSCH_COMP_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_psch_comp_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_comp_tbl_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
+
+sw_error_t
+hppe_psch_comp_cfg_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_comp_cfg_tbl_u *value)
+{
+	if (index >= PSCH_COMP_CFG_TBL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + PSCH_COMP_CFG_TBL_ADDRESS + \
+				index * PSCH_COMP_CFG_TBL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_psch_comp_cfg_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union psch_comp_cfg_tbl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + PSCH_COMP_CFG_TBL_ADDRESS + \
+				index * PSCH_COMP_CFG_TBL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_ipg_pre_len_cfg_get(
+		a_uint32_t dev_id,
+		union ipg_pre_len_cfg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + IPG_PRE_LEN_CFG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_ipg_pre_len_cfg_set(
+		a_uint32_t dev_id,
+		union ipg_pre_len_cfg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				TRAFFIC_MANAGER_BASE_ADDR + IPG_PRE_LEN_CFG_ADDRESS,
+				value->val);
+}
+
+#ifndef IN_SHAPER_MINI
+sw_error_t
+hppe_ipg_pre_len_cfg_ipg_pre_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union ipg_pre_len_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipg_pre_len_cfg_get(dev_id, &reg_val);
+	*value = reg_val.bf.ipg_pre_len;
+	return ret;
+}
+
+sw_error_t
+hppe_ipg_pre_len_cfg_ipg_pre_len_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union ipg_pre_len_cfg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ipg_pre_len_cfg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipg_pre_len = value;
+	ret = hppe_ipg_pre_len_cfg_set(dev_id, &reg_val);
+	return ret;
+}
+
+
+sw_error_t
+hppe_shp_slot_cfg_l0_l0_shp_slot_time_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union shp_slot_cfg_l0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_shp_slot_cfg_l0_get(dev_id, &reg_val);
+	*value = reg_val.bf.l0_shp_slot_time;
+	return ret;
+}
+
+sw_error_t
+hppe_shp_slot_cfg_l0_l0_shp_slot_time_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union shp_slot_cfg_l0_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_shp_slot_cfg_l0_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l0_shp_slot_time = value;
+	ret = hppe_shp_slot_cfg_l0_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_shp_slot_cfg_l1_l1_shp_slot_time_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union shp_slot_cfg_l1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_shp_slot_cfg_l1_get(dev_id, &reg_val);
+	*value = reg_val.bf.l1_shp_slot_time;
+	return ret;
+}
+
+sw_error_t
+hppe_shp_slot_cfg_l1_l1_shp_slot_time_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union shp_slot_cfg_l1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_shp_slot_cfg_l1_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l1_shp_slot_time = value;
+	ret = hppe_shp_slot_cfg_l1_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_shp_slot_cfg_port_port_shp_slot_time_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union shp_slot_cfg_port_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_shp_slot_cfg_port_get(dev_id, &reg_val);
+	*value = reg_val.bf.port_shp_slot_time;
+	return ret;
+}
+
+sw_error_t
+hppe_shp_slot_cfg_port_port_shp_slot_time_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union shp_slot_cfg_port_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_shp_slot_cfg_port_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_shp_slot_time = value;
+	ret = hppe_shp_slot_cfg_port_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_credit_tbl_e_shaper_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_shaper_credit_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_credit_tbl_e_shaper_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_credit_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.e_shaper_credit_neg = value;
+	ret = hppe_l0_shp_credit_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_credit_tbl_e_shaper_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_shaper_credit_1 << 1 | \
+		reg_val.bf.e_shaper_credit_0;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_credit_tbl_e_shaper_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_credit_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.e_shaper_credit_1 = value >> 1;
+	reg_val.bf.e_shaper_credit_0 = value & (((a_uint64_t)1<<1)-1);
+	ret = hppe_l0_shp_credit_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_credit_tbl_c_shaper_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_shaper_credit;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_credit_tbl_c_shaper_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_credit_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.c_shaper_credit = value;
+	ret = hppe_l0_shp_credit_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_credit_tbl_c_shaper_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_shaper_credit_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_credit_tbl_c_shaper_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_credit_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.c_shaper_credit_neg = value;
+	ret = hppe_l0_shp_credit_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_cir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cir;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_cir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cir = value;
+	ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_cf_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cf;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_cf_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cf = value;
+	ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_meter_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.meter_unit;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_meter_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.meter_unit = value;
+	ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_e_shaper_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_shaper_enable;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_e_shaper_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.e_shaper_enable = value;
+	ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_c_shaper_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_shaper_enable;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_c_shaper_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.c_shaper_enable = value;
+	ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_eir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.eir;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_eir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.eir = value;
+	ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_token_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.token_unit;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_token_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.token_unit = value;
+	ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_cbs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cbs;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_cbs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cbs = value;
+	ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_ebs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ebs;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_shp_cfg_tbl_ebs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ebs = value;
+	ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_c_drr_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_drr_compensate_byte_cnt_1 << 9 | \
+		reg_val.bf.c_drr_compensate_byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_c_drr_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_e_drr_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_drr_compensate_byte_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_e_drr_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_c_shaper_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_shaper_compensate_byte_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_c_shaper_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_c_shaper_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_shaper_compensate_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_c_shaper_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_c_shaper_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_shaper_compensate_byte_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_c_shaper_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_e_shaper_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_shaper_compensate_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_e_shaper_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_e_drr_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_drr_compensate_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_e_drr_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_e_drr_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_drr_compensate_byte_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_e_drr_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_c_drr_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_drr_compensate_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_c_drr_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_c_drr_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_drr_compensate_byte_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_c_drr_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_e_shaper_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_shaper_compensate_byte_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_e_shaper_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_e_shaper_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_shaper_compensate_byte_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_tbl_e_shaper_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l0_comp_cfg_tbl_drr_meter_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_comp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.drr_meter_len;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_cfg_tbl_drr_meter_len_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_comp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.drr_meter_len = value;
+	ret = hppe_l0_comp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_cfg_tbl_shaper_meter_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l0_comp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.shaper_meter_len;
+	return ret;
+}
+
+sw_error_t
+hppe_l0_comp_cfg_tbl_shaper_meter_len_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l0_comp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l0_comp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.shaper_meter_len = value;
+	ret = hppe_l0_comp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_credit_tbl_e_shaper_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_shaper_credit_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_credit_tbl_e_shaper_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_credit_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.e_shaper_credit_neg = value;
+	ret = hppe_l1_shp_credit_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_credit_tbl_e_shaper_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_shaper_credit_1 << 1 | \
+		reg_val.bf.e_shaper_credit_0;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_credit_tbl_e_shaper_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_credit_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.e_shaper_credit_1 = value >> 1;
+	reg_val.bf.e_shaper_credit_0 = value & (((a_uint64_t)1<<1)-1);
+	ret = hppe_l1_shp_credit_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_credit_tbl_c_shaper_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_shaper_credit;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_credit_tbl_c_shaper_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_credit_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.c_shaper_credit = value;
+	ret = hppe_l1_shp_credit_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_credit_tbl_c_shaper_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_shaper_credit_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_credit_tbl_c_shaper_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_credit_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.c_shaper_credit_neg = value;
+	ret = hppe_l1_shp_credit_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_cir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cir;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_cir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cir = value;
+	ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_cf_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cf;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_cf_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cf = value;
+	ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_meter_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.meter_unit;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_meter_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.meter_unit = value;
+	ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_e_shaper_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_shaper_enable;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_e_shaper_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.e_shaper_enable = value;
+	ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_c_shaper_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_shaper_enable;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_c_shaper_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.c_shaper_enable = value;
+	ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_eir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.eir;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_eir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.eir = value;
+	ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_token_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.token_unit;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_token_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.token_unit = value;
+	ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_cbs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cbs;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_cbs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cbs = value;
+	ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_ebs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ebs;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_shp_cfg_tbl_ebs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ebs = value;
+	ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_c_drr_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_drr_compensate_byte_cnt_1 << 9 | \
+		reg_val.bf.c_drr_compensate_byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_c_drr_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_e_drr_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_drr_compensate_byte_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_e_drr_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_c_shaper_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_shaper_compensate_byte_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_c_shaper_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_c_shaper_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_shaper_compensate_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_c_shaper_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_c_shaper_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_shaper_compensate_byte_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_c_shaper_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_e_shaper_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_shaper_compensate_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_e_shaper_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_e_drr_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_drr_compensate_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_e_drr_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_e_drr_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_drr_compensate_byte_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_e_drr_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_c_drr_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_drr_compensate_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_c_drr_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_c_drr_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.c_drr_compensate_byte_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_c_drr_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_e_shaper_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_shaper_compensate_byte_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_e_shaper_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_e_shaper_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.e_shaper_compensate_byte_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_tbl_e_shaper_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_l1_comp_cfg_tbl_drr_meter_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_comp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.drr_meter_len;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_cfg_tbl_drr_meter_len_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_comp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.drr_meter_len = value;
+	ret = hppe_l1_comp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_cfg_tbl_shaper_meter_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union l1_comp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.shaper_meter_len;
+	return ret;
+}
+
+sw_error_t
+hppe_l1_comp_cfg_tbl_shaper_meter_len_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union l1_comp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_l1_comp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.shaper_meter_len = value;
+	ret = hppe_l1_comp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_psch_shp_sign_tbl_shaper_credit_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union psch_shp_sign_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_shp_sign_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.shaper_credit_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_psch_shp_sign_tbl_shaper_credit_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union psch_shp_sign_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_shp_sign_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.shaper_credit_neg = value;
+	ret = hppe_psch_shp_sign_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_psch_shp_credit_tbl_shaper_credit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union psch_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_shp_credit_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.shaper_credit;
+	return ret;
+}
+
+sw_error_t
+hppe_psch_shp_credit_tbl_shaper_credit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union psch_shp_credit_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_shp_credit_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.shaper_credit = value;
+	ret = hppe_psch_shp_credit_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_cir_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union psch_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cir;
+	return ret;
+}
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_cir_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union psch_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cir = value;
+	ret = hppe_psch_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_meter_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union psch_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.meter_unit;
+	return ret;
+}
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_meter_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union psch_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.meter_unit = value;
+	ret = hppe_psch_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_token_unit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union psch_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.token_unit;
+	return ret;
+}
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_token_unit_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union psch_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.token_unit = value;
+	ret = hppe_psch_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_cbs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union psch_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cbs;
+	return ret;
+}
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_cbs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union psch_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cbs = value;
+	ret = hppe_psch_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_shaper_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union psch_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.shaper_enable;
+	return ret;
+}
+
+sw_error_t
+hppe_psch_shp_cfg_tbl_shaper_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union psch_shp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.shaper_enable = value;
+	ret = hppe_psch_shp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_psch_comp_tbl_shaper_compensate_byte_neg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union psch_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.shaper_compensate_byte_neg;
+	return ret;
+}
+
+sw_error_t
+hppe_psch_comp_tbl_shaper_compensate_byte_neg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_psch_comp_tbl_shaper_compensate_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union psch_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.shaper_compensate_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_psch_comp_tbl_shaper_compensate_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_psch_comp_tbl_shaper_compensate_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union psch_comp_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_comp_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.shaper_compensate_byte_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_psch_comp_tbl_shaper_compensate_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_psch_comp_cfg_tbl_shaper_meter_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union psch_comp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_comp_cfg_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.shaper_meter_len;
+	return ret;
+}
+
+sw_error_t
+hppe_psch_comp_cfg_tbl_shaper_meter_len_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union psch_comp_cfg_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_psch_comp_cfg_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.shaper_meter_len = value;
+	ret = hppe_psch_comp_cfg_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
diff --git a/qca-ssdk/src/hsl/hppe/hppe_stp.c b/qca-ssdk/src/hsl/hppe/hppe_stp.c
new file mode 100755
index 0000000..a6b4b82
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_stp.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_stp_reg.h"
+#include "hppe_stp.h"
+
+sw_error_t
+hppe_cst_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union cst_state_u *value)
+{
+	if (index >= CST_STATE_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + CST_STATE_ADDRESS + \
+				index * CST_STATE_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_cst_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union cst_state_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + CST_STATE_ADDRESS + \
+				index * CST_STATE_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_cst_state_port_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union cst_state_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_cst_state_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.port_state;
+	return ret;
+}
+
+sw_error_t
+hppe_cst_state_port_state_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union cst_state_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_cst_state_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.port_state = value;
+	ret = hppe_cst_state_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_trunk.c b/qca-ssdk/src/hsl/hppe/hppe_trunk.c
new file mode 100755
index 0000000..d9db536
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_trunk.c
@@ -0,0 +1,790 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_trunk_reg.h"
+#include "hppe_trunk.h"
+
+sw_error_t
+hppe_trunk_hash_field_reg_get(
+		a_uint32_t dev_id,
+		union trunk_hash_field_reg_u *value)
+{
+	return hppe_reg_get(
+				dev_id,
+				IPR_CSR_BASE_ADDR + TRUNK_HASH_FIELD_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_set(
+		a_uint32_t dev_id,
+		union trunk_hash_field_reg_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPR_CSR_BASE_ADDR + TRUNK_HASH_FIELD_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+hppe_trunk_filter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union trunk_filter_u *value)
+{
+	if (index >= TRUNK_FILTER_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + TRUNK_FILTER_ADDRESS + \
+				index * TRUNK_FILTER_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_trunk_filter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union trunk_filter_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + TRUNK_FILTER_ADDRESS + \
+				index * TRUNK_FILTER_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_trunk_member_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union trunk_member_u *value)
+{
+	if (index >= TRUNK_MEMBER_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + TRUNK_MEMBER_ADDRESS + \
+				index * TRUNK_MEMBER_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_trunk_member_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union trunk_member_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + TRUNK_MEMBER_ADDRESS + \
+				index * TRUNK_MEMBER_INC,
+				value->val);
+}
+sw_error_t
+hppe_port_trunk_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_trunk_id_u *value)
+{
+	if (index >= PORT_TRUNK_ID_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + PORT_TRUNK_ID_ADDRESS + \
+				index * PORT_TRUNK_ID_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_port_trunk_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union port_trunk_id_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + PORT_TRUNK_ID_ADDRESS + \
+				index * PORT_TRUNK_ID_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf2_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf2_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf2_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf2_incl = value;
+	ret = hppe_trunk_hash_field_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_mac_da_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.mac_da_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_mac_da_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_da_incl = value;
+	ret = hppe_trunk_hash_field_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_src_port_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.src_port_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_src_port_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.src_port_incl = value;
+	ret = hppe_trunk_hash_field_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf3_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf3_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf3_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf3_incl = value;
+	ret = hppe_trunk_hash_field_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_l4_dst_port_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.l4_dst_port_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_l4_dst_port_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l4_dst_port_incl = value;
+	ret = hppe_trunk_hash_field_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf0_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf0_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf0_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf0_incl = value;
+	ret = hppe_trunk_hash_field_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_dst_ip_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.dst_ip_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_dst_ip_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dst_ip_incl = value;
+	ret = hppe_trunk_hash_field_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_l4_src_port_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.l4_src_port_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_l4_src_port_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l4_src_port_incl = value;
+	ret = hppe_trunk_hash_field_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_src_ip_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.src_ip_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_src_ip_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.src_ip_incl = value;
+	ret = hppe_trunk_hash_field_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf1_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.udf1_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_udf1_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udf1_incl = value;
+	ret = hppe_trunk_hash_field_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_mac_sa_incl_get(
+		a_uint32_t dev_id,
+		a_uint32_t *value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	*value = reg_val.bf.mac_sa_incl;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_hash_field_reg_mac_sa_incl_set(
+		a_uint32_t dev_id,
+		a_uint32_t value)
+{
+	union trunk_hash_field_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_hash_field_reg_get(dev_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_sa_incl = value;
+	ret = hppe_trunk_hash_field_reg_set(dev_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_filter_mem_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union trunk_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mem_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_filter_mem_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union trunk_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mem_bitmap = value;
+	ret = hppe_trunk_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_2_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.member_2_port_id;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_2_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.member_2_port_id = value;
+	ret = hppe_trunk_member_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_0_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.member_0_port_id;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_0_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.member_0_port_id = value;
+	ret = hppe_trunk_member_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_1_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.member_1_port_id;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_1_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.member_1_port_id = value;
+	ret = hppe_trunk_member_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_6_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.member_6_port_id;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_6_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.member_6_port_id = value;
+	ret = hppe_trunk_member_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_4_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.member_4_port_id;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_4_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.member_4_port_id = value;
+	ret = hppe_trunk_member_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_3_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.member_3_port_id;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_3_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.member_3_port_id = value;
+	ret = hppe_trunk_member_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_5_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.member_5_port_id;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_5_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.member_5_port_id = value;
+	ret = hppe_trunk_member_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_7_port_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.member_7_port_id;
+	return ret;
+}
+
+sw_error_t
+hppe_trunk_member_member_7_port_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union trunk_member_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_trunk_member_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.member_7_port_id = value;
+	ret = hppe_trunk_member_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_trunk_id_trunk_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_trunk_id_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_trunk_id_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.trunk_id;
+	return ret;
+}
+
+sw_error_t
+hppe_port_trunk_id_trunk_id_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_trunk_id_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_trunk_id_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.trunk_id = value;
+	ret = hppe_port_trunk_id_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_port_trunk_id_trunk_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union port_trunk_id_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_trunk_id_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.trunk_en;
+	return ret;
+}
+
+sw_error_t
+hppe_port_trunk_id_trunk_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union port_trunk_id_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_port_trunk_id_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.trunk_en = value;
+	ret = hppe_port_trunk_id_set(dev_id, index, &reg_val);
+	return ret;
+}
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_uniphy.c b/qca-ssdk/src/hsl/hppe/hppe_uniphy.c
new file mode 100755
index 0000000..9588e67
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_uniphy.c
@@ -0,0 +1,6120 @@
+/*
+ * Copyright (c) 2017, 2019-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_uniphy_reg.h"
+#include "hppe_uniphy.h"
+
+sw_error_t
+hppe_uniphy_offset_calib_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_offset_calib_4_u *value)
+{
+	if (index >= UNIPHY_OFFSET_CALIB_4_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_OFFSET_CALIB_4_ADDRESS,
+				index * UNIPHY_OFFSET_CALIB_4_INC,
+				&value->val);
+}
+#ifndef IN_UNIPHY_MINI
+sw_error_t
+hppe_uniphy_offset_calib_4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_offset_calib_4_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_OFFSET_CALIB_4_ADDRESS,
+				index * UNIPHY_OFFSET_CALIB_4_INC,
+				value->val);
+}
+#endif
+sw_error_t
+hppe_uniphy_mode_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_mode_ctrl_u *value)
+{
+	if (index >= UNIPHY_MODE_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_MODE_CTRL_ADDRESS,
+				index * UNIPHY_MODE_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_mode_ctrl_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_MODE_CTRL_ADDRESS,
+				index * UNIPHY_MODE_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel0_input_output_4_u *value)
+{
+	if (index >= UNIPHY_CHANNEL0_INPUT_OUTPUT_4_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL0_INPUT_OUTPUT_4_ADDRESS,
+				index * UNIPHY_CHANNEL0_INPUT_OUTPUT_4_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel0_input_output_4_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL0_INPUT_OUTPUT_4_ADDRESS,
+				index * UNIPHY_CHANNEL0_INPUT_OUTPUT_4_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel1_input_output_4_u *value)
+{
+	if (index >= UNIPHY_CHANNEL1_INPUT_OUTPUT_4_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL1_INPUT_OUTPUT_4_ADDRESS,
+				index * UNIPHY_CHANNEL1_INPUT_OUTPUT_4_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel1_input_output_4_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL1_INPUT_OUTPUT_4_ADDRESS,
+				index * UNIPHY_CHANNEL1_INPUT_OUTPUT_4_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel2_input_output_4_u *value)
+{
+	if (index >= UNIPHY_CHANNEL2_INPUT_OUTPUT_4_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL2_INPUT_OUTPUT_4_ADDRESS,
+				index * UNIPHY_CHANNEL2_INPUT_OUTPUT_4_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel2_input_output_4_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL2_INPUT_OUTPUT_4_ADDRESS,
+				index * UNIPHY_CHANNEL2_INPUT_OUTPUT_4_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel3_input_output_4_u *value)
+{
+	if (index >= UNIPHY_CHANNEL3_INPUT_OUTPUT_4_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL3_INPUT_OUTPUT_4_ADDRESS,
+				index * UNIPHY_CHANNEL3_INPUT_OUTPUT_4_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel3_input_output_4_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL3_INPUT_OUTPUT_4_ADDRESS,
+				index * UNIPHY_CHANNEL3_INPUT_OUTPUT_4_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel4_input_output_4_u *value)
+{
+	if (index >= UNIPHY_CHANNEL4_INPUT_OUTPUT_4_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL4_INPUT_OUTPUT_4_ADDRESS,
+				index * UNIPHY_CHANNEL4_INPUT_OUTPUT_4_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_channel4_input_output_4_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL4_INPUT_OUTPUT_4_ADDRESS,
+				index * UNIPHY_CHANNEL4_INPUT_OUTPUT_4_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_uniphy_instance_link_detect_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_instance_link_detect_u *value)
+{
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_INSTANCE_LINK_DETECT_ADDRESS,
+				index * UNIPHY_INSTANCE_LINK_DETECT_INC,
+				&value->val);
+}
+
+
+sw_error_t
+hppe_uniphy_instance_link_detect_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_instance_link_detect_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_INSTANCE_LINK_DETECT_ADDRESS,
+				index * UNIPHY_INSTANCE_LINK_DETECT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sr_xs_pcs_kr_sts1_u *value)
+{
+	if (index >= SR_XS_PCS_KR_STS1_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + SR_XS_PCS_KR_STS1_ADDRESS,
+				index * SR_XS_PCS_KR_STS1_INC,
+				&value->val);
+}
+#ifndef IN_UNIPHY_MINI
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sr_xs_pcs_kr_sts1_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + SR_XS_PCS_KR_STS1_ADDRESS,
+				index * SR_XS_PCS_KR_STS1_INC,
+				value->val);
+}
+#endif
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vr_xs_pcs_dig_ctrl1_u *value)
+{
+	if (index >= VR_XS_PCS_DIG_CTRL1_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + VR_XS_PCS_DIG_CTRL1_ADDRESS,
+				index * VR_XS_PCS_DIG_CTRL1_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vr_xs_pcs_dig_ctrl1_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + VR_XS_PCS_DIG_CTRL1_ADDRESS,
+				index * VR_XS_PCS_DIG_CTRL1_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sr_mii_ctrl_u *value)
+{
+	if (index >= SR_MII_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + SR_MII_CTRL_ADDRESS,
+				index * SR_MII_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sr_mii_ctrl_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + SR_MII_CTRL_ADDRESS,
+				index * SR_MII_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_vr_mii_an_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vr_mii_an_ctrl_u *value)
+{
+	if (index >= VR_MII_AN_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + VR_MII_AN_CTRL_ADDRESS,
+				index * VR_MII_AN_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_vr_mii_an_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vr_mii_an_ctrl_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + VR_MII_AN_CTRL_ADDRESS,
+				index * VR_MII_AN_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vr_mii_an_intr_sts_u *value)
+{
+	if (index >= VR_MII_AN_INTR_STS_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + VR_MII_AN_INTR_STS_ADDRESS,
+				index * VR_MII_AN_INTR_STS_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vr_mii_an_intr_sts_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + VR_MII_AN_INTR_STS_ADDRESS,
+				index * VR_MII_AN_INTR_STS_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_cal_rep_time_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_offset_calib_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_offset_calib_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_cal_rep_time;
+	return ret;
+}
+#ifndef IN_UNIPHY_MINI
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_cal_rep_time_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_offset_calib_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_offset_calib_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_cal_rep_time = value;
+	ret = hppe_uniphy_offset_calib_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_pll_locked_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_offset_calib_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_offset_calib_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_pll_locked_reg;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_pll_locked_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_offset_calib_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_offset_calib_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_pll_locked_reg = value;
+	ret = hppe_uniphy_offset_calib_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_clr_sampler_calib_timeout_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_offset_calib_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_offset_calib_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_clr_sampler_calib_timeout;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_clr_sampler_calib_timeout_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_offset_calib_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_offset_calib_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_clr_sampler_calib_timeout = value;
+	ret = hppe_uniphy_offset_calib_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_lockdet_lckdt_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_offset_calib_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_offset_calib_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_lockdet_lckdt_reg;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_lockdet_lckdt_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_offset_calib_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_offset_calib_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_lockdet_lckdt_reg = value;
+	ret = hppe_uniphy_offset_calib_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_cal_detect_time_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_offset_calib_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_offset_calib_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_cal_detect_time;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_cal_detect_time_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_offset_calib_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_offset_calib_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_cal_detect_time = value;
+	ret = hppe_uniphy_offset_calib_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_calibration_done_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_offset_calib_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_offset_calib_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_calibration_done_reg;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_calibration_done_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_offset_calib_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_offset_calib_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_calibration_done_reg = value;
+	ret = hppe_uniphy_offset_calib_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_smpl_cal_ready_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_offset_calib_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_offset_calib_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_smpl_cal_ready;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_offset_calib_4_mmd1_reg_smpl_cal_ready_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_offset_calib_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_offset_calib_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_smpl_cal_ready = value;
+	ret = hppe_uniphy_offset_calib_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch1_ch0_sgmii_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch1_ch0_sgmii;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch1_ch0_sgmii_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch1_ch0_sgmii = value;
+	ret = hppe_uniphy_mode_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_usxg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_usxg_en;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_usxg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_usxg_en = value;
+	ret = hppe_uniphy_mode_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch4_ch1_0_sgmii_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch4_ch1_0_sgmii;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch4_ch1_0_sgmii_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch4_ch1_0_sgmii = value;
+	ret = hppe_uniphy_mode_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sgplus_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_sgplus_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sgplus_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_sgplus_mode = value;
+	ret = hppe_uniphy_mode_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_xpcs_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_xpcs_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_xpcs_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_xpcs_mode = value;
+	ret = hppe_uniphy_mode_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_psgmii_qsgmii_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch0_psgmii_qsgmii;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_psgmii_qsgmii_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch0_psgmii_qsgmii = value;
+	ret = hppe_uniphy_mode_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_autoneg_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch0_autoneg_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_autoneg_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch0_autoneg_mode = value;
+	ret = hppe_uniphy_mode_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sw_v17_v18_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_sw_v17_v18;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sw_v17_v18_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_sw_v17_v18 = value;
+	ret = hppe_uniphy_mode_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_mode_ctrl_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch0_mode_ctrl_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_mode_ctrl_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch0_mode_ctrl_25m = value;
+	ret = hppe_uniphy_mode_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sgmii_even_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_sgmii_even_low;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sgmii_even_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_sgmii_even_low = value;
+	ret = hppe_uniphy_mode_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_qsgmii_sgmii_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch0_qsgmii_sgmii;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_qsgmii_sgmii_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch0_qsgmii_sgmii = value;
+	ret = hppe_uniphy_mode_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sg_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_sg_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_mode_ctrl_newaddedfromhere_sg_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_mode_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_mode_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_sg_mode = value;
+	ret = hppe_uniphy_mode_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_restart_an_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch0_mr_restart_an_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_restart_an_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch0_mr_restart_an_25m = value;
+	ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_rem_phy_lpbk_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch0_rem_phy_lpbk;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_rem_phy_lpbk_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch0_rem_phy_lpbk = value;
+	ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_reg4_ch_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch0_mr_reg4_ch_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_reg4_ch_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch0_mr_reg4_ch_25m = value;
+	ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_power_on_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch0_power_on_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_power_on_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch0_power_on_25m = value;
+	ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_main_reset_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch0_mr_main_reset_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_main_reset_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch0_mr_main_reset_25m = value;
+	ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_force_speed_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch0_force_speed_25m;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_uniphy_channel0_force_speed_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch0_force_speed_25m = value;
+	ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+#ifndef IN_UNIPHY_MINI
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_adp_sw_rstn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch0_adp_sw_rstn;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_adp_sw_rstn_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch0_adp_sw_rstn = value;
+	ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch0_speed_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch0_speed_25m = value;
+	ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_an_enable_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch0_mr_an_enable_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_an_enable_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch0_mr_an_enable_25m = value;
+	ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_np_loaded_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch0_mr_np_loaded_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_np_loaded_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch0_mr_np_loaded_25m = value;
+	ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_loopback_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch0_mr_loopback_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_loopback_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel0_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch0_mr_loopback_25m = value;
+	ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_adp_sw_rstn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch1_adp_sw_rstn;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_adp_sw_rstn_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch1_adp_sw_rstn = value;
+	ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_power_on_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch1_power_on_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_power_on_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch1_power_on_25m = value;
+	ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_main_reset_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch1_mr_main_reset_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_main_reset_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch1_mr_main_reset_25m = value;
+	ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_an_enable_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch1_mr_an_enable_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_an_enable_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch1_mr_an_enable_25m = value;
+	ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch1_speed_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch1_speed_25m = value;
+	ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_rem_phy_lpbk_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch1_rem_phy_lpbk;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_rem_phy_lpbk_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch1_rem_phy_lpbk = value;
+	ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_reg4_ch_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch1_mr_reg4_ch_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_reg4_ch_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch1_mr_reg4_ch_25m = value;
+	ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_np_loaded_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch1_mr_np_loaded_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_np_loaded_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch1_mr_np_loaded_25m = value;
+	ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_force_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch1_force_speed_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_force_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch1_force_speed_25m = value;
+	ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_restart_an_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch1_mr_restart_an_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_restart_an_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch1_mr_restart_an_25m = value;
+	ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_loopback_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch1_mr_loopback_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_loopback_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel1_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch1_mr_loopback_25m = value;
+	ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_rem_phy_lpbk_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch2_rem_phy_lpbk;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_rem_phy_lpbk_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch2_rem_phy_lpbk = value;
+	ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_adp_sw_rstn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch2_adp_sw_rstn;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_adp_sw_rstn_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch2_adp_sw_rstn = value;
+	ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_main_reset_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch2_mr_main_reset_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_main_reset_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch2_mr_main_reset_25m = value;
+	ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_loopback_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch2_mr_loopback_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_loopback_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch2_mr_loopback_25m = value;
+	ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_restart_an_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch2_mr_restart_an_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_restart_an_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch2_mr_restart_an_25m = value;
+	ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch2_speed_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch2_speed_25m = value;
+	ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_np_loaded_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch2_mr_np_loaded_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_np_loaded_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch2_mr_np_loaded_25m = value;
+	ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_force_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch2_force_speed_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_force_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch2_force_speed_25m = value;
+	ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_an_enable_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch2_mr_an_enable_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_an_enable_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch2_mr_an_enable_25m = value;
+	ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_power_on_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch2_power_on_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_power_on_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch2_power_on_25m = value;
+	ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_reg4_ch_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch2_mr_reg4_ch_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_reg4_ch_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel2_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch2_mr_reg4_ch_25m = value;
+	ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_main_reset_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch3_mr_main_reset_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_main_reset_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch3_mr_main_reset_25m = value;
+	ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch3_speed_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch3_speed_25m = value;
+	ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_np_loaded_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch3_mr_np_loaded_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_np_loaded_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch3_mr_np_loaded_25m = value;
+	ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_adp_sw_rstn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch3_adp_sw_rstn;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_adp_sw_rstn_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch3_adp_sw_rstn = value;
+	ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_power_on_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch3_power_on_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_power_on_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch3_power_on_25m = value;
+	ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_an_enable_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch3_mr_an_enable_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_an_enable_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch3_mr_an_enable_25m = value;
+	ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_reg4_ch_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch3_mr_reg4_ch_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_reg4_ch_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch3_mr_reg4_ch_25m = value;
+	ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_restart_an_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch3_mr_restart_an_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_restart_an_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch3_mr_restart_an_25m = value;
+	ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_rem_phy_lpbk_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch3_rem_phy_lpbk;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_rem_phy_lpbk_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch3_rem_phy_lpbk = value;
+	ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_force_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch3_force_speed_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_force_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch3_force_speed_25m = value;
+	ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_loopback_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch3_mr_loopback_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_loopback_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel3_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch3_mr_loopback_25m = value;
+	ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_loopback_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch4_mr_loopback_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_loopback_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch4_mr_loopback_25m = value;
+	ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_reg4_ch_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch4_mr_reg4_ch_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_reg4_ch_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch4_mr_reg4_ch_25m = value;
+	ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_restart_an_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch4_mr_restart_an_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_restart_an_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch4_mr_restart_an_25m = value;
+	ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_an_enable_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch4_mr_an_enable_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_an_enable_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch4_mr_an_enable_25m = value;
+	ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_force_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch4_force_speed_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_force_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch4_force_speed_25m = value;
+	ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_main_reset_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch4_mr_main_reset_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_main_reset_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch4_mr_main_reset_25m = value;
+	ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_power_on_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch4_power_on_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_power_on_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch4_power_on_25m = value;
+	ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_speed_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch4_speed_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_speed_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch4_speed_25m = value;
+	ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_rem_phy_lpbk_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch4_rem_phy_lpbk;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_rem_phy_lpbk_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch4_rem_phy_lpbk = value;
+	ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_np_loaded_25m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch4_mr_np_loaded_25m;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_np_loaded_25m_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch4_mr_np_loaded_25m = value;
+	ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_adp_sw_rstn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.newaddedfromhere_ch4_adp_sw_rstn;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_adp_sw_rstn_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_channel4_input_output_4_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.newaddedfromhere_ch4_adp_sw_rstn = value;
+	ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_plu_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sr_xs_pcs_kr_sts1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.plu;
+	return ret;
+}
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_plu_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union sr_xs_pcs_kr_sts1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.plu = value;
+	ret = hppe_sr_xs_pcs_kr_sts1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_prbs31abl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sr_xs_pcs_kr_sts1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.prbs31abl;
+	return ret;
+}
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_prbs31abl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union sr_xs_pcs_kr_sts1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.prbs31abl = value;
+	ret = hppe_sr_xs_pcs_kr_sts1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_rpcs_bklk_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sr_xs_pcs_kr_sts1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rpcs_bklk;
+	return ret;
+}
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_rpcs_bklk_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union sr_xs_pcs_kr_sts1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rpcs_bklk = value;
+	ret = hppe_sr_xs_pcs_kr_sts1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_prcs_hiber_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sr_xs_pcs_kr_sts1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.prcs_hiber;
+	return ret;
+}
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_prcs_hiber_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union sr_xs_pcs_kr_sts1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.prcs_hiber = value;
+	ret = hppe_sr_xs_pcs_kr_sts1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_prbs9abl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sr_xs_pcs_kr_sts1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.prbs9abl;
+	return ret;
+}
+
+sw_error_t
+hppe_sr_xs_pcs_kr_sts1_prbs9abl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union sr_xs_pcs_kr_sts1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.prbs9abl = value;
+	ret = hppe_sr_xs_pcs_kr_sts1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_vr_rst_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vr_rst;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_vr_rst_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vr_rst = value;
+	ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_usra_rst_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.usra_rst;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_usra_rst_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.usra_rst = value;
+	ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_en_2_5g_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.en_2_5g_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_en_2_5g_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.en_2_5g_mode = value;
+	ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_dskbyp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dskbyp;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_dskbyp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dskbyp = value;
+	ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_en_vsmmd1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.en_vsmmd1;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_en_vsmmd1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.en_vsmmd1 = value;
+	ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_init_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.init;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_init_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.init = value;
+	ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_cl37_bp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cl37_bp;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_cl37_bp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cl37_bp = value;
+	ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_pwrsv_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pwrsv;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_pwrsv_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pwrsv = value;
+	ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_3_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dtxlaned_3_1;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_3_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dtxlaned_3_1 = value;
+	ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_usxg_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.usxg_en;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_usxg_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.usxg_en = value;
+	ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_r2tlbe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.r2tlbe;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_r2tlbe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.r2tlbe = value;
+	ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_cr_cjn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cr_cjn;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_cr_cjn_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cr_cjn = value;
+	ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dtxlaned_0;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dtxlaned_0 = value;
+	ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_byp_pwrup_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.byp_pwrup;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_xs_pcs_dig_ctrl1_byp_pwrup_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_xs_pcs_dig_ctrl1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.byp_pwrup = value;
+	ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_lpm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lpm;
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_lpm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.lpm = value;
+	ret = hppe_sr_mii_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_duplex_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.duplex_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_duplex_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.duplex_mode = value;
+	ret = hppe_sr_mii_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_ss6_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ss6;
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_ss6_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ss6 = value;
+	ret = hppe_sr_mii_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_ss5_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ss5;
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_ss5_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ss5 = value;
+	ret = hppe_sr_mii_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_ss13_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ss13;
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_ss13_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ss13 = value;
+	ret = hppe_sr_mii_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_an_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.an_enable;
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_an_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.an_enable = value;
+	ret = hppe_sr_mii_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_restart_an_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.restart_an;
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_restart_an_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.restart_an = value;
+	ret = hppe_sr_mii_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_rst_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rst;
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_rst_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rst = value;
+	ret = hppe_sr_mii_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_lbe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lbe;
+	return ret;
+}
+
+sw_error_t
+hppe_sr_mii_ctrl_lbe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union sr_mii_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_sr_mii_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.lbe = value;
+	ret = hppe_sr_mii_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_ctrl_pcs_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_mii_an_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pcs_mode;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_ctrl_pcs_mode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_mii_an_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pcs_mode = value;
+	ret = hppe_vr_mii_an_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_ctrl_mii_an_intr_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_mii_an_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mii_an_intr_en;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_ctrl_mii_an_intr_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_mii_an_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mii_an_intr_en = value;
+	ret = hppe_vr_mii_an_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_ctrl_sgmii_link_sts_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_mii_an_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.sgmii_link_sts;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_ctrl_sgmii_link_sts_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_mii_an_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.sgmii_link_sts = value;
+	ret = hppe_vr_mii_an_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_ctrl_tx_config_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_mii_an_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_config;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_ctrl_tx_config_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_mii_an_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_config = value;
+	ret = hppe_vr_mii_an_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_ctrl_mii_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_mii_an_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mii_ctrl;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_ctrl_mii_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_mii_an_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mii_ctrl = value;
+	ret = hppe_vr_mii_an_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_usxg_an_sts_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_mii_an_intr_sts_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_intr_sts_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.usxg_an_sts;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_usxg_an_sts_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_mii_an_intr_sts_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_intr_sts_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.usxg_an_sts = value;
+	ret = hppe_vr_mii_an_intr_sts_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_cl37_ansgm_sts_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_mii_an_intr_sts_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_intr_sts_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cl37_ansgm_sts;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_cl37_ansgm_sts_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_mii_an_intr_sts_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_intr_sts_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cl37_ansgm_sts = value;
+	ret = hppe_vr_mii_an_intr_sts_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_cl37_ancmplt_intr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vr_mii_an_intr_sts_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_intr_sts_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cl37_ancmplt_intr;
+	return ret;
+}
+
+sw_error_t
+hppe_vr_mii_an_intr_sts_cl37_ancmplt_intr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vr_mii_an_intr_sts_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vr_mii_an_intr_sts_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cl37_ancmplt_intr = value;
+	ret = hppe_vr_mii_an_intr_sts_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_pll_control_vco_related_selection_u *value)
+{
+	if (index >= UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_ADDRESS,
+				index * UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_pll_control_vco_related_selection_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_ADDRESS,
+				index * UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_tx_ac_jtag_mux_driver_selection_u *value)
+{
+	if (index >= UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_ADDRESS,
+				index * UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_tx_ac_jtag_mux_driver_selection_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_ADDRESS,
+				index * UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_resistor_calibration_1_u *value)
+{
+	if (index >= UNIPHY_RESISTOR_CALIBRATION_1_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_RESISTOR_CALIBRATION_1_ADDRESS,
+				index * UNIPHY_RESISTOR_CALIBRATION_1_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_resistor_calibration_1_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_RESISTOR_CALIBRATION_1_ADDRESS,
+				index * UNIPHY_RESISTOR_CALIBRATION_1_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_pll_vco_related_control_1_u *value)
+{
+	if (index >= UNIPHY_PLL_VCO_RELATED_CONTROL_1_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_PLL_VCO_RELATED_CONTROL_1_ADDRESS,
+				index * UNIPHY_PLL_VCO_RELATED_CONTROL_1_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_pll_vco_related_control_1_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_PLL_VCO_RELATED_CONTROL_1_ADDRESS,
+				index * UNIPHY_PLL_VCO_RELATED_CONTROL_1_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_uniphy_rx_afe_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_rx_afe_2_u *value)
+{
+	if (index >= UNIPHY_RX_AFE_2_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_RX_AFE_2_ADDRESS,
+				index * UNIPHY_RX_AFE_2_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uniphy_rx_afe_2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_rx_afe_2_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_RX_AFE_2_ADDRESS,
+				index * UNIPHY_RX_AFE_2_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union bandgap_ip_mbias_2_u *value)
+{
+	if (index >= BANDGAP_IP_MBIAS_2_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + BANDGAP_IP_MBIAS_2_ADDRESS,
+				index * BANDGAP_IP_MBIAS_2_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union bandgap_ip_mbias_2_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + BANDGAP_IP_MBIAS_2_ADDRESS,
+				index * BANDGAP_IP_MBIAS_2_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ldo_0p9v_related_1_u *value)
+{
+	if (index >= LDO_0P9V_RELATED_1_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + LDO_0P9V_RELATED_1_ADDRESS,
+				index * LDO_0P9V_RELATED_1_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union ldo_0p9v_related_1_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + LDO_0P9V_RELATED_1_ADDRESS,
+				index * LDO_0P9V_RELATED_1_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union otp_vtt_ldo_related_u *value)
+{
+	if (index >= OTP_VTT_LDO_RELATED_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + OTP_VTT_LDO_RELATED_ADDRESS,
+				index * OTP_VTT_LDO_RELATED_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union otp_vtt_ldo_related_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + OTP_VTT_LDO_RELATED_ADDRESS,
+				index * OTP_VTT_LDO_RELATED_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_otp_temperature_compensate_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union otp_temperature_compensate_1_u *value)
+{
+	if (index >= OTP_TEMPERATURE_COMPENSATE_1_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + OTP_TEMPERATURE_COMPENSATE_1_ADDRESS,
+				index * OTP_TEMPERATURE_COMPENSATE_1_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_otp_temperature_compensate_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union otp_temperature_compensate_1_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + OTP_TEMPERATURE_COMPENSATE_1_ADDRESS,
+				index * OTP_TEMPERATURE_COMPENSATE_1_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_pll_vco_related_control_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pll_vco_related_control_1_u *value)
+{
+	if (index >= PLL_VCO_RELATED_CONTROL_1_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + PLL_VCO_RELATED_CONTROL_1_ADDRESS,
+				index * PLL_VCO_RELATED_CONTROL_1_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_pll_vco_related_control_1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pll_vco_related_control_1_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + PLL_VCO_RELATED_CONTROL_1_ADDRESS,
+				index * PLL_VCO_RELATED_CONTROL_1_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pll_control_vco_related_selection_2_u *value)
+{
+	if (index >= PLL_CONTROL_VCO_RELATED_SELECTION_2_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + PLL_CONTROL_VCO_RELATED_SELECTION_2_ADDRESS,
+				index * PLL_CONTROL_VCO_RELATED_SELECTION_2_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pll_control_vco_related_selection_2_u *value)
+{
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + PLL_CONTROL_VCO_RELATED_SELECTION_2_ADDRESS,
+				index * PLL_CONTROL_VCO_RELATED_SELECTION_2_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_gain_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_pll_control_vco_related_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_src_uphy_pll_vco_gain;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_gain_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_pll_control_vco_related_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_src_uphy_pll_vco_gain = value;
+	ret = hppe_uniphy_pll_control_vco_related_selection_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_temp_cmp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_pll_control_vco_related_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_src_uphy_pll_vco_temp_cmp;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_temp_cmp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_pll_control_vco_related_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_src_uphy_pll_vco_temp_cmp = value;
+	ret = hppe_uniphy_pll_control_vco_related_selection_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_c2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_pll_control_vco_related_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_src_uphy_pll_lpf_c2;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_c2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_pll_control_vco_related_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_src_uphy_pll_lpf_c2 = value;
+	ret = hppe_uniphy_pll_control_vco_related_selection_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_amp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_pll_control_vco_related_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_src_uphy_pll_vco_amp;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_amp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_pll_control_vco_related_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_src_uphy_pll_vco_amp = value;
+	ret = hppe_uniphy_pll_control_vco_related_selection_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_dc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_pll_control_vco_related_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_src_uphy_pll_lpf_dc;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_dc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_pll_control_vco_related_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_src_uphy_pll_lpf_dc = value;
+	ret = hppe_uniphy_pll_control_vco_related_selection_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_cp_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_pll_control_vco_related_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_src_uphy_pll_cp_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_cp_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_pll_control_vco_related_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_src_uphy_pll_cp_sel = value;
+	ret = hppe_uniphy_pll_control_vco_related_selection_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_res_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_pll_control_vco_related_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_src_uphy_pll_lpf_res;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_res_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_pll_control_vco_related_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_src_uphy_pll_lpf_res = value;
+	ret = hppe_uniphy_pll_control_vco_related_selection_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_vcm_delta_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_src_uphy_tx_vcm_delta;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_vcm_delta_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_src_uphy_tx_vcm_delta = value;
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lsb_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_src_uphy_tx_emp_lsb_en;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lsb_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_src_uphy_tx_emp_lsb_en = value;
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lvl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_src_uphy_tx_emp_lvl;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lvl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_src_uphy_tx_emp_lvl = value;
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_acjtag_beacon_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_src_uphy_tx_acjtag_beacon_en;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_acjtag_beacon_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_src_uphy_tx_acjtag_beacon_en = value;
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_src_uphy_tx_en;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_src_uphy_tx_en = value;
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_txd_bit_width_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_src_uphy_txd_bit_width;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_txd_bit_width_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_src_uphy_txd_bit_width = value;
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_rescal_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_src_uphy_tx_rescal_code;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_rescal_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_src_uphy_tx_rescal_code = value;
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_amp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_src_uphy_tx_amp;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_amp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_src_uphy_tx_amp = value;
+	ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_disable_load_res_txrx_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_resistor_calibration_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_disable_load_res_txrx;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_disable_load_res_txrx_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_resistor_calibration_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_disable_load_res_txrx = value;
+	ret = hppe_uniphy_resistor_calibration_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_tx_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_resistor_calibration_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_calib_tx_reg;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_tx_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_resistor_calibration_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_calib_tx_reg = value;
+	ret = hppe_uniphy_resistor_calibration_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_rx_reg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_resistor_calibration_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_calib_rx_reg;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_rx_reg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_resistor_calibration_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_calib_rx_reg = value;
+	ret = hppe_uniphy_resistor_calibration_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_vref_lvl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_resistor_calibration_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmd1_reg_vref_lvl;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_resistor_calibration_1_mmd1_reg_vref_lvl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_resistor_calibration_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmd1_reg_vref_lvl = value;
+	ret = hppe_uniphy_resistor_calibration_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_uphy_pll_lckdt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.miireg_uphy_pll_lckdt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_uphy_pll_lckdt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.miireg_uphy_pll_lckdt_en = value;
+	ret = hppe_uniphy_pll_vco_related_control_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_autoload_sel_pll_vco_calib_ready_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.miireg_autoload_sel_pll_vco_calib_ready;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_autoload_sel_pll_vco_calib_ready_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.miireg_autoload_sel_pll_vco_calib_ready = value;
+	ret = hppe_uniphy_pll_vco_related_control_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_calib_ready_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.miireg_reg_uphy_pll_vco_calib_ready;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_calib_ready_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.miireg_reg_uphy_pll_vco_calib_ready = value;
+	ret = hppe_uniphy_pll_vco_related_control_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_temp_cmp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.miireg_reg_uphy_pll_vco_temp_cmp;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_temp_cmp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.miireg_reg_uphy_pll_vco_temp_cmp = value;
+	ret = hppe_uniphy_pll_vco_related_control_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_amp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.miireg_reg_uphy_pll_vco_amp;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_amp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.miireg_reg_uphy_pll_vco_amp = value;
+	ret = hppe_uniphy_pll_vco_related_control_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_gain_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.miireg_reg_uphy_pll_vco_gain;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_gain_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.miireg_reg_uphy_pll_vco_gain = value;
+	ret = hppe_uniphy_pll_vco_related_control_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_res1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_rx_afe_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_rx_afe_2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.miireg_reg_uphy_rx_afe_res1;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_res1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_rx_afe_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_rx_afe_2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.miireg_reg_uphy_rx_afe_res1 = value;
+	ret = hppe_uniphy_rx_afe_2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_cap1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_rx_afe_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_rx_afe_2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.miireg_reg_uphy_rx_afe_cap1;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_cap1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_rx_afe_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_rx_afe_2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.miireg_reg_uphy_rx_afe_cap1 = value;
+	ret = hppe_uniphy_rx_afe_2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_rescal_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union uniphy_rx_afe_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_rx_afe_2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.miireg_reg_uphy_rx_rescal_code;
+	return ret;
+}
+
+sw_error_t
+hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_rescal_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union uniphy_rx_afe_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_uniphy_rx_afe_2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.miireg_reg_uphy_rx_rescal_code = value;
+	ret = hppe_uniphy_rx_afe_2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_mbias_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union bandgap_ip_mbias_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_bandgap_ip_mbias_2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_mbias_en;
+	return ret;
+}
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_mbias_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union bandgap_ip_mbias_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_bandgap_ip_mbias_2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_mbias_en = value;
+	ret = hppe_bandgap_ip_mbias_2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_icc_rescode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union bandgap_ip_mbias_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_bandgap_ip_mbias_2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_icc_rescode;
+	return ret;
+}
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_icc_rescode_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union bandgap_ip_mbias_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_bandgap_ip_mbias_2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_icc_rescode = value;
+	ret = hppe_bandgap_ip_mbias_2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_bg_rsv_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union bandgap_ip_mbias_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_bandgap_ip_mbias_2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_bg_rsv;
+	return ret;
+}
+
+sw_error_t
+hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_bg_rsv_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union bandgap_ip_mbias_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_bandgap_ip_mbias_2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_bg_rsv = value;
+	ret = hppe_bandgap_ip_mbias_2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_ocp_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_ldo_ocp_en = value;
+	ret = hppe_ldo_0p9v_related_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_load_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_int_load_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_load_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_ldo_int_load_en = value;
+	ret = hppe_ldo_0p9v_related_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_res_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_int_res_ctrl;
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_res_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_ldo_int_res_ctrl = value;
+	ret = hppe_ldo_0p9v_related_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_vout_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_vout_ctrl;
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_vout_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_ldo_vout_ctrl = value;
+	ret = hppe_ldo_0p9v_related_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_current_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_ocp_current_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_current_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_ldo_ocp_current_sel = value;
+	ret = hppe_ldo_0p9v_related_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_vtt_ldo_biasgen_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_biasgen_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_vtt_ldo_biasgen_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_biasgen_sel = value;
+	ret = hppe_ldo_0p9v_related_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_ldo_en = value;
+	ret = hppe_ldo_0p9v_related_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_comp_current_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_comp_current_en;
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_comp_current_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_ldo_comp_current_en = value;
+	ret = hppe_ldo_0p9v_related_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_bias_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_bias_ctrl;
+	return ret;
+}
+
+sw_error_t
+hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_bias_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union ldo_0p9v_related_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_ldo_0p9v_related_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_ldo_bias_ctrl = value;
+	ret = hppe_ldo_0p9v_related_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_ana_isolation_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union otp_vtt_ldo_related_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_vtt_ldo_related_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_ana_isolation;
+	return ret;
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_ana_isolation_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union otp_vtt_ldo_related_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_vtt_ldo_related_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_ana_isolation = value;
+	ret = hppe_otp_vtt_ldo_related_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union otp_vtt_ldo_related_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_vtt_ldo_related_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_ocp_en;
+	return ret;
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union otp_vtt_ldo_related_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_vtt_ldo_related_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_ocp_en = value;
+	ret = hppe_otp_vtt_ldo_related_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union otp_vtt_ldo_related_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_vtt_ldo_related_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_en;
+	return ret;
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union otp_vtt_ldo_related_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_vtt_ldo_related_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_en = value;
+	ret = hppe_otp_vtt_ldo_related_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_bias_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union otp_vtt_ldo_related_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_vtt_ldo_related_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_bias_ctrl;
+	return ret;
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_bias_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union otp_vtt_ldo_related_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_vtt_ldo_related_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_bias_ctrl = value;
+	ret = hppe_otp_vtt_ldo_related_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_rsv_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union otp_vtt_ldo_related_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_vtt_ldo_related_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_rsv;
+	return ret;
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_rsv_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union otp_vtt_ldo_related_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_vtt_ldo_related_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_rsv = value;
+	ret = hppe_otp_vtt_ldo_related_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_current_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union otp_vtt_ldo_related_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_vtt_ldo_related_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_ocp_current_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_current_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union otp_vtt_ldo_related_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_vtt_ldo_related_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_ocp_current_sel = value;
+	ret = hppe_otp_vtt_ldo_related_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_int_load_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union otp_vtt_ldo_related_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_vtt_ldo_related_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_int_load_ctrl;
+	return ret;
+}
+
+sw_error_t
+hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_int_load_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union otp_vtt_ldo_related_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_vtt_ldo_related_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_int_load_ctrl = value;
+	ret = hppe_otp_vtt_ldo_related_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union otp_temperature_compensate_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_temperature_compensate_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_en;
+	return ret;
+}
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union otp_temperature_compensate_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_temperature_compensate_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_en = value;
+	ret = hppe_otp_temperature_compensate_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_cmn_pll_ictat100u_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union otp_temperature_compensate_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_temperature_compensate_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_cmn_pll_ictat100u_en;
+	return ret;
+}
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_cmn_pll_ictat100u_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union otp_temperature_compensate_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_temperature_compensate_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_cmn_pll_ictat100u_en = value;
+	ret = hppe_otp_temperature_compensate_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union otp_temperature_compensate_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_temperature_compensate_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_ctrl1;
+	return ret;
+}
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl1_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union otp_temperature_compensate_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_temperature_compensate_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_ctrl1 = value;
+	ret = hppe_otp_temperature_compensate_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union otp_temperature_compensate_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_temperature_compensate_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_ctrl2;
+	return ret;
+}
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl2_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union otp_temperature_compensate_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_temperature_compensate_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_ctrl2 = value;
+	ret = hppe_otp_temperature_compensate_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union otp_temperature_compensate_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_temperature_compensate_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_ctrl0;
+	return ret;
+}
+
+sw_error_t
+hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl0_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union otp_temperature_compensate_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_otp_temperature_compensate_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_ctrl0 = value;
+	ret = hppe_otp_temperature_compensate_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_calib_ready_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mii_reg_reg_cmn_pll_vco_calib_ready;
+	return ret;
+}
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_calib_ready_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mii_reg_reg_cmn_pll_vco_calib_ready = value;
+	ret = hppe_pll_vco_related_control_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_temp_cmp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mii_reg_reg_cmn_pll_vco_temp_cmp;
+	return ret;
+}
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_temp_cmp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mii_reg_reg_cmn_pll_vco_temp_cmp = value;
+	ret = hppe_pll_vco_related_control_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_cmn_pll_lckdt_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mii_reg_cmn_pll_lckdt_en;
+	return ret;
+}
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_cmn_pll_lckdt_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mii_reg_cmn_pll_lckdt_en = value;
+	ret = hppe_pll_vco_related_control_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_amp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mii_reg_reg_cmn_pll_vco_amp;
+	return ret;
+}
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_amp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mii_reg_reg_cmn_pll_vco_amp = value;
+	ret = hppe_pll_vco_related_control_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_autoload_sel_pll_vco_calib_ready_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mii_reg_autoload_sel_pll_vco_calib_ready;
+	return ret;
+}
+
+sw_error_t
+hppe_pll_vco_related_control_1_cmn_mii_reg_autoload_sel_pll_vco_calib_ready_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pll_vco_related_control_1_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_vco_related_control_1_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mii_reg_autoload_sel_pll_vco_calib_ready = value;
+	ret = hppe_pll_vco_related_control_1_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_ready_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pll_control_vco_related_selection_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_calib_ready;
+	return ret;
+}
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_ready_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pll_control_vco_related_selection_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_calib_ready = value;
+	ret = hppe_pll_control_vco_related_selection_2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_temp_cmp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pll_control_vco_related_selection_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_temp_cmp;
+	return ret;
+}
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_temp_cmp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pll_control_vco_related_selection_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_temp_cmp = value;
+	ret = hppe_pll_control_vco_related_selection_2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_amp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pll_control_vco_related_selection_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_amp;
+	return ret;
+}
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_amp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pll_control_vco_related_selection_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_amp = value;
+	ret = hppe_pll_control_vco_related_selection_2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_start_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pll_control_vco_related_selection_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_calib_start;
+	return ret;
+}
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_start_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pll_control_vco_related_selection_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_calib_start = value;
+	ret = hppe_pll_control_vco_related_selection_2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pll_control_vco_related_selection_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_calib_code;
+	return ret;
+}
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_code_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pll_control_vco_related_selection_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_calib_code = value;
+	ret = hppe_pll_control_vco_related_selection_2_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_fbclk_div_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pll_control_vco_related_selection_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmn_mmd1_reg_src_cmn_pll_fbclk_div;
+	return ret;
+}
+
+sw_error_t
+hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_fbclk_div_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pll_control_vco_related_selection_2_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cmn_mmd1_reg_src_cmn_pll_fbclk_div = value;
+	ret = hppe_pll_control_vco_related_selection_2_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
+
+sw_error_t
+hppe_uniphy_phy_mode_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_misc2_phy_mode_u *value)
+{
+	if (index >= UNIPHY_MISC2_PHY_MODE_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_MISC2_PHY_MODE_ADDRESS,
+				index * UNIPHY_MISC2_PHY_MODE_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uniphy_phy_mode_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_misc2_phy_mode_u *value)
+{
+	if (index >= UNIPHY_MISC2_PHY_MODE_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_MISC2_PHY_MODE_ADDRESS,
+				index * UNIPHY_MISC2_PHY_MODE_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_uniphy_pll_reset_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pll_power_on_and_reset_u *value)
+{
+	if (index >= UNIPHY_PLL_POWER_ON_AND_RESET_INC_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + PLL_POWER_ON_AND_RESET_ADDRESS,
+				index * PLL_POWER_ON_AND_RESET_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_uniphy_pll_reset_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pll_power_on_and_reset_u *value)
+{
+	if (index >= UNIPHY_PLL_POWER_ON_AND_RESET_INC_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + PLL_POWER_ON_AND_RESET_ADDRESS,
+				index * PLL_POWER_ON_AND_RESET_INC,
+				value->val);
+}
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_vsi.c b/qca-ssdk/src/hsl/hppe/hppe_vsi.c
new file mode 100755
index 0000000..25d1d90
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_vsi.c
@@ -0,0 +1,650 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_vsi_reg.h"
+#include "hppe_vsi.h"
+
+sw_error_t
+hppe_vsi_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vsi_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				IPE_L2_BASE_ADDR + VSI_TBL_ADDRESS + \
+				index * VSI_TBL_INC,
+				value->val,
+				2);
+}
+
+sw_error_t
+hppe_vsi_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vsi_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				IPE_L2_BASE_ADDR + VSI_TBL_ADDRESS + \
+				index * VSI_TBL_INC,
+				value->val,
+				2);
+}
+
+#ifndef IN_VSI_MINI
+sw_error_t
+hppe_vsi_tbl_umc_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.umc_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_vsi_tbl_umc_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.umc_bitmap = value;
+	ret = hppe_vsi_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vsi_tbl_station_move_lrn_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.station_move_lrn_en;
+	return ret;
+}
+
+sw_error_t
+hppe_vsi_tbl_station_move_lrn_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.station_move_lrn_en = value;
+	ret = hppe_vsi_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vsi_tbl_new_addr_fwd_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.new_addr_fwd_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_vsi_tbl_new_addr_fwd_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.new_addr_fwd_cmd = value;
+	ret = hppe_vsi_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vsi_tbl_uuc_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.uuc_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_vsi_tbl_uuc_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.uuc_bitmap = value;
+	ret = hppe_vsi_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vsi_tbl_member_port_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.member_port_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_vsi_tbl_member_port_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.member_port_bitmap = value;
+	ret = hppe_vsi_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vsi_tbl_new_addr_lrn_en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.new_addr_lrn_en;
+	return ret;
+}
+
+sw_error_t
+hppe_vsi_tbl_new_addr_lrn_en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.new_addr_lrn_en = value;
+	ret = hppe_vsi_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vsi_tbl_bc_bitmap_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.bc_bitmap;
+	return ret;
+}
+
+sw_error_t
+hppe_vsi_tbl_bc_bitmap_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.bc_bitmap = value;
+	ret = hppe_vsi_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vsi_tbl_station_move_fwd_cmd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.station_move_fwd_cmd;
+	return ret;
+}
+
+sw_error_t
+hppe_vsi_tbl_station_move_fwd_cmd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vsi_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vsi_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.station_move_fwd_cmd = value;
+	ret = hppe_vsi_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
+
+sw_error_t
+hppe_vlan_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vlan_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + VLAN_CNT_TBL_ADDRESS + \
+				index * VLAN_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_vlan_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union vlan_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + VLAN_CNT_TBL_ADDRESS + \
+				index * VLAN_CNT_TBL_INC,
+				value->val,
+				3);
+}
+
+#ifndef IN_VSI_MINI
+sw_error_t
+hppe_vlan_cnt_tbl_rx_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union vlan_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.rx_byte_cnt_1 << 32 | \
+		reg_val.bf.rx_byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_vlan_cnt_tbl_rx_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union vlan_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_byte_cnt_1 = value >> 32;
+	reg_val.bf.rx_byte_cnt_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_vlan_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_vlan_cnt_tbl_rx_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union vlan_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_vlan_cnt_tbl_rx_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union vlan_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_vlan_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_pkt_cnt = value;
+	ret = hppe_vlan_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
+
+
+sw_error_t
+hppe_eg_vsi_counter_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vsi_counter_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_VSI_COUNTER_TBL_ADDRESS + \
+				index * EG_VSI_COUNTER_TBL_INC,
+				value->val,
+				3);
+}
+
+sw_error_t
+hppe_eg_vsi_counter_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union eg_vsi_counter_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				NSS_PTX_CSR_BASE_ADDR + EG_VSI_COUNTER_TBL_ADDRESS + \
+				index * EG_VSI_COUNTER_TBL_INC,
+				value->val,
+				3);
+}
+
+#ifndef IN_VSI_MINI
+sw_error_t
+hppe_eg_vsi_counter_tbl_tx_bytes_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union eg_vsi_counter_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vsi_counter_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.tx_bytes_1 << 32 | \
+		reg_val.bf.tx_bytes_0;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vsi_counter_tbl_tx_bytes_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union eg_vsi_counter_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vsi_counter_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_bytes_1 = value >> 32;
+	reg_val.bf.tx_bytes_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_eg_vsi_counter_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vsi_counter_tbl_tx_packets_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union eg_vsi_counter_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vsi_counter_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_packets;
+	return ret;
+}
+
+sw_error_t
+hppe_eg_vsi_counter_tbl_tx_packets_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union eg_vsi_counter_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_eg_vsi_counter_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_packets = value;
+	ret = hppe_eg_vsi_counter_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pre_l2_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_get(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + PRE_L2_CNT_TBL_ADDRESS + \
+				index * PRE_L2_CNT_TBL_INC,
+				value->val,
+				5);
+}
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union pre_l2_cnt_tbl_u *value)
+{
+	return hppe_reg_tbl_set(
+				dev_id,
+				INGRESS_POLICER_BASE_ADDR + PRE_L2_CNT_TBL_ADDRESS + \
+				index * PRE_L2_CNT_TBL_INC,
+				value->val,
+				5);
+}
+#ifndef IN_VSI_MINI
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_drop_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union pre_l2_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.rx_drop_byte_cnt_1 << 24 | \
+		reg_val.bf.rx_drop_byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_drop_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union pre_l2_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_drop_byte_cnt_1 = value >> 24;
+	reg_val.bf.rx_drop_byte_cnt_0 = value & (((a_uint64_t)1<<24)-1);
+	ret = hppe_pre_l2_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_byte_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t *value)
+{
+	union pre_l2_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = (a_uint64_t)reg_val.bf.rx_byte_cnt_1 << 32 | \
+		reg_val.bf.rx_byte_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_byte_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint64_t value)
+{
+	union pre_l2_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_byte_cnt_1 = value >> 32;
+	reg_val.bf.rx_byte_cnt_0 = value & (((a_uint64_t)1<<32)-1);
+	ret = hppe_pre_l2_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pre_l2_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pkt_cnt;
+	return ret;
+}
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pre_l2_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_pkt_cnt = value;
+	ret = hppe_pre_l2_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_drop_pkt_cnt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union pre_l2_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_drop_pkt_cnt_1 << 24 | \
+		reg_val.bf.rx_drop_pkt_cnt_0;
+	return ret;
+}
+
+sw_error_t
+hppe_pre_l2_cnt_tbl_rx_drop_pkt_cnt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union pre_l2_cnt_tbl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_drop_pkt_cnt_1 = value >> 24;
+	reg_val.bf.rx_drop_pkt_cnt_0 = value & (((a_uint64_t)1<<24)-1);
+	ret = hppe_pre_l2_cnt_tbl_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
diff --git a/qca-ssdk/src/hsl/hppe/hppe_xgmacmib.c b/qca-ssdk/src/hsl/hppe/hppe_xgmacmib.c
new file mode 100755
index 0000000..aee2f49
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_xgmacmib.c
@@ -0,0 +1,4210 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_xgmacmib_reg.h"
+#include "hppe_xgmacmib.h"
+
+
+sw_error_t
+hppe_mmc_control_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_control_u *value)
+{
+	if (index >= MMC_CONTROL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MMC_CONTROL_ADDRESS + \
+				index * MMC_CONTROL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mmc_control_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_control_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MMC_CONTROL_ADDRESS + \
+				index * MMC_CONTROL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_tx_octet_count_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_bad_low_u *value)
+{
+	if (index >= TX_OCTET_COUNT_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_OCTET_COUNT_GOOD_BAD_LOW_ADDRESS + \
+				index * TX_OCTET_COUNT_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_octet_count_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_octet_count_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_bad_high_u *value)
+{
+	if (index >= TX_OCTET_COUNT_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_OCTET_COUNT_GOOD_BAD_HIGH_ADDRESS + \
+				index * TX_OCTET_COUNT_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_octet_count_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_frame_count_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_bad_low_u *value)
+{
+	if (index >= TX_FRAME_COUNT_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_FRAME_COUNT_GOOD_BAD_LOW_ADDRESS + \
+				index * TX_FRAME_COUNT_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_frame_count_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_frame_count_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_bad_high_u *value)
+{
+	if (index >= TX_FRAME_COUNT_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_FRAME_COUNT_GOOD_BAD_HIGH_ADDRESS + \
+				index * TX_FRAME_COUNT_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_frame_count_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_low_u *value)
+{
+	if (index >= TX_BROADCAST_FRAMES_GOOD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_BROADCAST_FRAMES_GOOD_LOW_ADDRESS + \
+				index * TX_BROADCAST_FRAMES_GOOD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_high_u *value)
+{
+	if (index >= TX_BROADCAST_FRAMES_GOOD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_BROADCAST_FRAMES_GOOD_HIGH_ADDRESS + \
+				index * TX_BROADCAST_FRAMES_GOOD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_low_u *value)
+{
+	if (index >= TX_MULTICAST_FRAMES_GOOD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_MULTICAST_FRAMES_GOOD_LOW_ADDRESS + \
+				index * TX_MULTICAST_FRAMES_GOOD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_high_u *value)
+{
+	if (index >= TX_MULTICAST_FRAMES_GOOD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_MULTICAST_FRAMES_GOOD_HIGH_ADDRESS + \
+				index * TX_MULTICAST_FRAMES_GOOD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_64octets_frames_good_bad_low_u *value)
+{
+	if (index >= TX_64OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_64OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * TX_64OCTETS_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_64octets_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_64octets_frames_good_bad_high_u *value)
+{
+	if (index >= TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_64octets_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_65to127octets_frames_good_bad_low_u *value)
+{
+	if (index >= TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_65to127octets_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_65to127octets_frames_good_bad_high_u *value)
+{
+	if (index >= TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_65to127octets_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_128to255octets_frames_good_bad_low_u *value)
+{
+	if (index >= TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_128to255octets_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_128to255octets_frames_good_bad_high_u *value)
+{
+	if (index >= TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_128to255octets_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_256to511octets_frames_good_bad_low_u *value)
+{
+	if (index >= TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_256to511octets_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_256to511octets_frames_good_bad_high_u *value)
+{
+	if (index >= TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_256to511octets_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_512to1023octets_frames_good_bad_low_u *value)
+{
+	if (index >= TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_512to1023octets_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_512to1023octets_frames_good_bad_high_u *value)
+{
+	if (index >= TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_512to1023octets_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_1024tomaxoctets_frames_good_bad_low_u *value)
+{
+	if (index >= TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_1024tomaxoctets_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_1024tomaxoctets_frames_good_bad_high_u *value)
+{
+	if (index >= TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_1024tomaxoctets_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_unicast_frames_good_bad_low_u *value)
+{
+	if (index >= TX_UNICAST_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_UNICAST_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * TX_UNICAST_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_unicast_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_unicast_frames_good_bad_high_u *value)
+{
+	if (index >= TX_UNICAST_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_UNICAST_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * TX_UNICAST_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_unicast_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_bad_low_u *value)
+{
+	if (index >= TX_MULTICAST_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_MULTICAST_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * TX_MULTICAST_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_bad_high_u *value)
+{
+	if (index >= TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_bad_low_u *value)
+{
+	if (index >= TX_BROADCAST_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_BROADCAST_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * TX_BROADCAST_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_bad_high_u *value)
+{
+	if (index >= TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_underflow_error_frames_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_underflow_error_frames_low_u *value)
+{
+	if (index >= TX_UNDERFLOW_ERROR_FRAMES_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_UNDERFLOW_ERROR_FRAMES_LOW_ADDRESS + \
+				index * TX_UNDERFLOW_ERROR_FRAMES_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_underflow_error_frames_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_underflow_error_frames_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_underflow_error_frames_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_underflow_error_frames_high_u *value)
+{
+	if (index >= TX_UNDERFLOW_ERROR_FRAMES_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_UNDERFLOW_ERROR_FRAMES_HIGH_ADDRESS + \
+				index * TX_UNDERFLOW_ERROR_FRAMES_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_underflow_error_frames_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_underflow_error_frames_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_octet_count_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_low_u *value)
+{
+	if (index >= TX_OCTET_COUNT_GOOD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_OCTET_COUNT_GOOD_LOW_ADDRESS + \
+				index * TX_OCTET_COUNT_GOOD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_octet_count_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_octet_count_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_high_u *value)
+{
+	if (index >= TX_OCTET_COUNT_GOOD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_OCTET_COUNT_GOOD_HIGH_ADDRESS + \
+				index * TX_OCTET_COUNT_GOOD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_octet_count_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_frame_count_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_low_u *value)
+{
+	if (index >= TX_FRAME_COUNT_GOOD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_FRAME_COUNT_GOOD_LOW_ADDRESS + \
+				index * TX_FRAME_COUNT_GOOD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_frame_count_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_frame_count_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_high_u *value)
+{
+	if (index >= TX_FRAME_COUNT_GOOD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_FRAME_COUNT_GOOD_HIGH_ADDRESS + \
+				index * TX_FRAME_COUNT_GOOD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_frame_count_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_pause_frames_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_pause_frames_low_u *value)
+{
+	if (index >= TX_PAUSE_FRAMES_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_PAUSE_FRAMES_LOW_ADDRESS + \
+				index * TX_PAUSE_FRAMES_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_pause_frames_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_pause_frames_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_pause_frames_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_pause_frames_high_u *value)
+{
+	if (index >= TX_PAUSE_FRAMES_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_PAUSE_FRAMES_HIGH_ADDRESS + \
+				index * TX_PAUSE_FRAMES_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_pause_frames_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_pause_frames_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_vlan_frames_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_vlan_frames_good_low_u *value)
+{
+	if (index >= TX_VLAN_FRAMES_GOOD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_VLAN_FRAMES_GOOD_LOW_ADDRESS + \
+				index * TX_VLAN_FRAMES_GOOD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_vlan_frames_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_vlan_frames_good_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_vlan_frames_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_vlan_frames_good_high_u *value)
+{
+	if (index >= TX_VLAN_FRAMES_GOOD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_VLAN_FRAMES_GOOD_HIGH_ADDRESS + \
+				index * TX_VLAN_FRAMES_GOOD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_vlan_frames_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_vlan_frames_good_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_lpi_usec_cntr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_lpi_usec_cntr_u *value)
+{
+	if (index >= TX_LPI_USEC_CNTR_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_LPI_USEC_CNTR_ADDRESS + \
+				index * TX_LPI_USEC_CNTR_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_lpi_usec_cntr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_lpi_usec_cntr_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_lpi_tran_cntr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_lpi_tran_cntr_u *value)
+{
+	if (index >= TX_LPI_TRAN_CNTR_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + TX_LPI_TRAN_CNTR_ADDRESS + \
+				index * TX_LPI_TRAN_CNTR_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_tx_lpi_tran_cntr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_lpi_tran_cntr_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_frame_count_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_frame_count_good_bad_low_u *value)
+{
+	if (index >= RX_FRAME_COUNT_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_FRAME_COUNT_GOOD_BAD_LOW_ADDRESS + \
+				index * RX_FRAME_COUNT_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_frame_count_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_frame_count_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_frame_count_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_frame_count_good_bad_high_u *value)
+{
+	if (index >= RX_FRAME_COUNT_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_FRAME_COUNT_GOOD_BAD_HIGH_ADDRESS + \
+				index * RX_FRAME_COUNT_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_frame_count_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_frame_count_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_octet_count_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_bad_low_u *value)
+{
+	if (index >= RX_OCTET_COUNT_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_OCTET_COUNT_GOOD_BAD_LOW_ADDRESS + \
+				index * RX_OCTET_COUNT_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_octet_count_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_octet_count_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_bad_high_u *value)
+{
+	if (index >= RX_OCTET_COUNT_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_OCTET_COUNT_GOOD_BAD_HIGH_ADDRESS + \
+				index * RX_OCTET_COUNT_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_octet_count_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_octet_count_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_low_u *value)
+{
+	if (index >= RX_OCTET_COUNT_GOOD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_OCTET_COUNT_GOOD_LOW_ADDRESS + \
+				index * RX_OCTET_COUNT_GOOD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_octet_count_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_octet_count_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_high_u *value)
+{
+	if (index >= RX_OCTET_COUNT_GOOD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_OCTET_COUNT_GOOD_HIGH_ADDRESS + \
+				index * RX_OCTET_COUNT_GOOD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_octet_count_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_broadcast_frames_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_broadcast_frames_good_low_u *value)
+{
+	if (index >= RX_BROADCAST_FRAMES_GOOD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_BROADCAST_FRAMES_GOOD_LOW_ADDRESS + \
+				index * RX_BROADCAST_FRAMES_GOOD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_broadcast_frames_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_broadcast_frames_good_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_broadcast_frames_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_broadcast_frames_good_high_u *value)
+{
+	if (index >= RX_BROADCAST_FRAMES_GOOD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_BROADCAST_FRAMES_GOOD_HIGH_ADDRESS + \
+				index * RX_BROADCAST_FRAMES_GOOD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_broadcast_frames_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_broadcast_frames_good_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_multicast_frames_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_multicast_frames_good_low_u *value)
+{
+	if (index >= RX_MULTICAST_FRAMES_GOOD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_MULTICAST_FRAMES_GOOD_LOW_ADDRESS + \
+				index * RX_MULTICAST_FRAMES_GOOD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_multicast_frames_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_multicast_frames_good_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_multicast_frames_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_multicast_frames_good_high_u *value)
+{
+	if (index >= RX_MULTICAST_FRAMES_GOOD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_MULTICAST_FRAMES_GOOD_HIGH_ADDRESS + \
+				index * RX_MULTICAST_FRAMES_GOOD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_multicast_frames_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_multicast_frames_good_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_crc_error_frames_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_crc_error_frames_low_u *value)
+{
+	if (index >= RX_CRC_ERROR_FRAMES_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_CRC_ERROR_FRAMES_LOW_ADDRESS + \
+				index * RX_CRC_ERROR_FRAMES_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_crc_error_frames_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_crc_error_frames_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_crc_error_frames_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_crc_error_frames_high_u *value)
+{
+	if (index >= RX_CRC_ERROR_FRAMES_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_CRC_ERROR_FRAMES_HIGH_ADDRESS + \
+				index * RX_CRC_ERROR_FRAMES_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_crc_error_frames_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_crc_error_frames_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_runt_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_runt_error_frames_u *value)
+{
+	if (index >= RX_RUNT_ERROR_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_RUNT_ERROR_FRAMES_ADDRESS + \
+				index * RX_RUNT_ERROR_FRAMES_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_runt_error_frames_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_runt_error_frames_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_jabber_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_jabber_error_frames_u *value)
+{
+	if (index >= RX_JABBER_ERROR_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_JABBER_ERROR_FRAMES_ADDRESS + \
+				index * RX_JABBER_ERROR_FRAMES_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_jabber_error_frames_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_jabber_error_frames_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_undersize_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_undersize_frames_good_u *value)
+{
+	if (index >= RX_UNDERSIZE_FRAMES_GOOD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_UNDERSIZE_FRAMES_GOOD_ADDRESS + \
+				index * RX_UNDERSIZE_FRAMES_GOOD_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_undersize_frames_good_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_undersize_frames_good_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_oversize_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_oversize_frames_good_u *value)
+{
+	if (index >= RX_OVERSIZE_FRAMES_GOOD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_OVERSIZE_FRAMES_GOOD_ADDRESS + \
+				index * RX_OVERSIZE_FRAMES_GOOD_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_oversize_frames_good_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_oversize_frames_good_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_64octets_frames_good_bad_low_u *value)
+{
+	if (index >= RX_64OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_64OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * RX_64OCTETS_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_64octets_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_64octets_frames_good_bad_high_u *value)
+{
+	if (index >= RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_64octets_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_65to127octets_frames_good_bad_low_u *value)
+{
+	if (index >= RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_65to127octets_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_65to127octets_frames_good_bad_high_u *value)
+{
+	if (index >= RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_65to127octets_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_128to255octets_frames_good_bad_low_u *value)
+{
+	if (index >= RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_128to255octets_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_128to255octets_frames_good_bad_high_u *value)
+{
+	if (index >= RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_128to255octets_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_256to511octets_frames_good_bad_low_u *value)
+{
+	if (index >= RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_256to511octets_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_256to511octets_frames_good_bad_high_u *value)
+{
+	if (index >= RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_256to511octets_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_512to1023octets_frames_good_bad_low_u *value)
+{
+	if (index >= RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_512to1023octets_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_512to1023octets_frames_good_bad_high_u *value)
+{
+	if (index >= RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_512to1023octets_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_1024tomaxoctets_frames_good_bad_low_u *value)
+{
+	if (index >= RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_1024tomaxoctets_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_1024tomaxoctets_frames_good_bad_high_u *value)
+{
+	if (index >= RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_1024tomaxoctets_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_unicast_frames_good_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_unicast_frames_good_low_u *value)
+{
+	if (index >= RX_UNICAST_FRAMES_GOOD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_UNICAST_FRAMES_GOOD_LOW_ADDRESS + \
+				index * RX_UNICAST_FRAMES_GOOD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_unicast_frames_good_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_unicast_frames_good_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_unicast_frames_good_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_unicast_frames_good_high_u *value)
+{
+	if (index >= RX_UNICAST_FRAMES_GOOD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_UNICAST_FRAMES_GOOD_HIGH_ADDRESS + \
+				index * RX_UNICAST_FRAMES_GOOD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_unicast_frames_good_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_unicast_frames_good_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_length_error_frames_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_length_error_frames_low_u *value)
+{
+	if (index >= RX_LENGTH_ERROR_FRAMES_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_LENGTH_ERROR_FRAMES_LOW_ADDRESS + \
+				index * RX_LENGTH_ERROR_FRAMES_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_length_error_frames_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_length_error_frames_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_length_error_frames_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_length_error_frames_high_u *value)
+{
+	if (index >= RX_LENGTH_ERROR_FRAMES_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_LENGTH_ERROR_FRAMES_HIGH_ADDRESS + \
+				index * RX_LENGTH_ERROR_FRAMES_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_length_error_frames_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_length_error_frames_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_outofrange_frames_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_outofrange_frames_low_u *value)
+{
+	if (index >= RX_OUTOFRANGE_FRAMES_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_OUTOFRANGE_FRAMES_LOW_ADDRESS + \
+				index * RX_OUTOFRANGE_FRAMES_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_outofrange_frames_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_outofrange_frames_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_outofrange_frames_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_outofrange_frames_high_u *value)
+{
+	if (index >= RX_OUTOFRANGE_FRAMES_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_OUTOFRANGE_FRAMES_HIGH_ADDRESS + \
+				index * RX_OUTOFRANGE_FRAMES_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_outofrange_frames_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_outofrange_frames_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_pause_frames_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_pause_frames_low_u *value)
+{
+	if (index >= RX_PAUSE_FRAMES_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_PAUSE_FRAMES_LOW_ADDRESS + \
+				index * RX_PAUSE_FRAMES_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_pause_frames_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_pause_frames_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_pause_frames_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_pause_frames_high_u *value)
+{
+	if (index >= RX_PAUSE_FRAMES_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_PAUSE_FRAMES_HIGH_ADDRESS + \
+				index * RX_PAUSE_FRAMES_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_pause_frames_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_pause_frames_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_fifooverflow_frames_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_fifooverflow_frames_low_u *value)
+{
+	if (index >= RX_FIFOOVERFLOW_FRAMES_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_FIFOOVERFLOW_FRAMES_LOW_ADDRESS + \
+				index * RX_FIFOOVERFLOW_FRAMES_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_fifooverflow_frames_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_fifooverflow_frames_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_fifooverflow_frames_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_fifooverflow_frames_high_u *value)
+{
+	if (index >= RX_FIFOOVERFLOW_FRAMES_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_FIFOOVERFLOW_FRAMES_HIGH_ADDRESS + \
+				index * RX_FIFOOVERFLOW_FRAMES_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_fifooverflow_frames_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_fifooverflow_frames_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_vlan_frames_good_bad_low_u *value)
+{
+	if (index >= RX_VLAN_FRAMES_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_VLAN_FRAMES_GOOD_BAD_LOW_ADDRESS + \
+				index * RX_VLAN_FRAMES_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_vlan_frames_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_vlan_frames_good_bad_high_u *value)
+{
+	if (index >= RX_VLAN_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_VLAN_FRAMES_GOOD_BAD_HIGH_ADDRESS + \
+				index * RX_VLAN_FRAMES_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_vlan_frames_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_watchdog_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_watchdog_error_frames_u *value)
+{
+	if (index >= RX_WATCHDOG_ERROR_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_WATCHDOG_ERROR_FRAMES_ADDRESS + \
+				index * RX_WATCHDOG_ERROR_FRAMES_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_watchdog_error_frames_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_watchdog_error_frames_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_lpi_usec_cntr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_lpi_usec_cntr_u *value)
+{
+	if (index >= RX_LPI_USEC_CNTR_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_LPI_USEC_CNTR_ADDRESS + \
+				index * RX_LPI_USEC_CNTR_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_lpi_usec_cntr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_lpi_usec_cntr_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_lpi_tran_cntr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_lpi_tran_cntr_u *value)
+{
+	if (index >= RX_LPI_TRAN_CNTR_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_LPI_TRAN_CNTR_ADDRESS + \
+				index * RX_LPI_TRAN_CNTR_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_lpi_tran_cntr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_lpi_tran_cntr_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_frame_count_good_bad_low_u *value)
+{
+	if (index >= RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_ADDRESS + \
+				index * RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_frame_count_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_frame_count_good_bad_high_u *value)
+{
+	if (index >= RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_ADDRESS + \
+				index * RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_frame_count_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_octet_count_good_bad_low_u *value)
+{
+	if (index >= RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_ADDRESS + \
+				index * RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_octet_count_good_bad_low_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_octet_count_good_bad_high_u *value)
+{
+	if (index >= RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_ADDRESS + \
+				index * RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_discard_octet_count_good_bad_high_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_control_cntrst_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_control_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_control_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cntrst;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_control_cntrst_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_control_rstonrd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_control_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_control_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rstonrd;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_control_rstonrd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_control_cntstopro_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_control_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_control_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cntstopro;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_control_cntstopro_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_control_mct_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_control_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_control_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mct;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_control_mct_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_control_pr_mmc_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_control_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_control_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pr_mmc_sel;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_control_pr_mmc_sel_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_control_cntprst_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_control_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_control_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cntprst;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_control_cntprst_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_control_mcf_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_control_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_control_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mcf;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_control_mcf_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_octet_count_good_bad_low_txoctgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_octet_count_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_octet_count_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txoctgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_octet_count_good_bad_low_txoctgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_octet_count_good_bad_high_txoctgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_octet_count_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_octet_count_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txoctgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_octet_count_good_bad_high_txoctgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_frame_count_good_bad_low_txfrmgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_frame_count_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_frame_count_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txfrmgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_frame_count_good_bad_low_txfrmgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_frame_count_good_bad_high_txfrmgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_frame_count_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_frame_count_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txfrmgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_frame_count_good_bad_high_txfrmgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_low_txbcastglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_broadcast_frames_good_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_broadcast_frames_good_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txbcastglo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_low_txbcastglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_high_txbcastghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_broadcast_frames_good_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_broadcast_frames_good_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txbcastghi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_high_txbcastghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_low_txmcastglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_multicast_frames_good_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_multicast_frames_good_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txmcastglo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_low_txmcastglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_high_txmcastghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_multicast_frames_good_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_multicast_frames_good_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txmcastghi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_high_txmcastghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_low_tx64octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_64octets_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_64octets_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx64octgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_low_tx64octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_high_tx64octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_64octets_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_64octets_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx64octgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_64octets_frames_good_bad_high_tx64octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_low_tx65_127octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_65to127octets_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_65to127octets_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx65_127octgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_low_tx65_127octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_high_tx65_127octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_65to127octets_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_65to127octets_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx65_127octgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_65to127octets_frames_good_bad_high_tx65_127octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_low_tx128_255octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_128to255octets_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_128to255octets_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx128_255octgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_low_tx128_255octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_high_tx128_255octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_128to255octets_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_128to255octets_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx128_255octgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_128to255octets_frames_good_bad_high_tx128_255octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_low_tx256_511octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_256to511octets_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_256to511octets_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx256_511octgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_low_tx256_511octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_high_tx256_511octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_256to511octets_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_256to511octets_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx256_511octgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_256to511octets_frames_good_bad_high_tx256_511octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_low_tx512_1023octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_512to1023octets_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_512to1023octets_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx512_1023octgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_low_tx512_1023octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_high_tx512_1023octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_512to1023octets_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_512to1023octets_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx512_1023octgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_512to1023octets_frames_good_bad_high_tx512_1023octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_low_tx1024_maxoctgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_1024tomaxoctets_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_1024tomaxoctets_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx1024_maxoctgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_low_tx1024_maxoctgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_high_tx1024_maxoctgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_1024tomaxoctets_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_1024tomaxoctets_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx1024_maxoctgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_1024tomaxoctets_frames_good_bad_high_tx1024_maxoctgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_low_txucastgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_unicast_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_unicast_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txucastgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_low_txucastgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_high_txucastgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_unicast_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_unicast_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txucastgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_unicast_frames_good_bad_high_txucastgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_low_txmcastgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_multicast_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_multicast_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txmcastgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_low_txmcastgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_high_txmcastgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_multicast_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_multicast_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txmcastgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_multicast_frames_good_bad_high_txmcastgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_low_txbcastgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_broadcast_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_broadcast_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txbcastgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_low_txbcastgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_high_txbcastgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_broadcast_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_broadcast_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txbcastgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_broadcast_frames_good_bad_high_txbcastgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_underflow_error_frames_low_txundrflwlo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_underflow_error_frames_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_underflow_error_frames_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txundrflwlo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_underflow_error_frames_low_txundrflwlo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_underflow_error_frames_high_txundrflwhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_underflow_error_frames_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_underflow_error_frames_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txundrflwhi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_underflow_error_frames_high_txundrflwhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_octet_count_good_low_txoctglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_octet_count_good_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_octet_count_good_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txoctglo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_octet_count_good_low_txoctglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_octet_count_good_high_txoctghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_octet_count_good_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_octet_count_good_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txoctghi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_octet_count_good_high_txoctghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_frame_count_good_low_txfrmglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_frame_count_good_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_frame_count_good_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txfrmglo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_frame_count_good_low_txfrmglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_frame_count_good_high_txfrmghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_frame_count_good_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_frame_count_good_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txfrmghi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_frame_count_good_high_txfrmghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_pause_frames_low_txpauseglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_pause_frames_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_pause_frames_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txpauseglo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_pause_frames_low_txpauseglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_pause_frames_high_txpauseghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_pause_frames_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_pause_frames_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txpauseghi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_pause_frames_high_txpauseghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_vlan_frames_good_low_txvlanglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_vlan_frames_good_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_vlan_frames_good_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txvlanglo;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_vlan_frames_good_low_txvlanglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_vlan_frames_good_high_txvlanghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_vlan_frames_good_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_vlan_frames_good_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txvlanghi;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_vlan_frames_good_high_txvlanghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_lpi_usec_cntr_txlpiusc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_lpi_usec_cntr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_lpi_usec_cntr_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txlpiusc;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_lpi_usec_cntr_txlpiusc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_tx_lpi_tran_cntr_txlpitrc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union tx_lpi_tran_cntr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_tx_lpi_tran_cntr_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txlpitrc;
+	return ret;
+}
+
+sw_error_t
+hppe_tx_lpi_tran_cntr_txlpitrc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_frame_count_good_bad_low_rxfrmgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_frame_count_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_frame_count_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxfrmgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_frame_count_good_bad_low_rxfrmgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_frame_count_good_bad_high_rxfrmgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_frame_count_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_frame_count_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxfrmgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_frame_count_good_bad_high_rxfrmgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_octet_count_good_bad_low_rxoctgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_octet_count_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_octet_count_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxoctgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_octet_count_good_bad_low_rxoctgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_octet_count_good_bad_high_rxoctgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_octet_count_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_octet_count_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxoctgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_octet_count_good_bad_high_rxoctgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_octet_count_good_low_rxoctglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_octet_count_good_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_octet_count_good_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxoctglo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_octet_count_good_low_rxoctglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_octet_count_good_high_rxoctghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_octet_count_good_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_octet_count_good_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxoctghi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_octet_count_good_high_rxoctghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_broadcast_frames_good_low_rxbcastglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_broadcast_frames_good_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_broadcast_frames_good_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxbcastglo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_broadcast_frames_good_low_rxbcastglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_broadcast_frames_good_high_rxbcastghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_broadcast_frames_good_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_broadcast_frames_good_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxbcastghi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_broadcast_frames_good_high_rxbcastghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_multicast_frames_good_low_rxmcastglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_multicast_frames_good_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_multicast_frames_good_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxmcastglo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_multicast_frames_good_low_rxmcastglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_multicast_frames_good_high_rxmcastghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_multicast_frames_good_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_multicast_frames_good_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxmcastghi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_multicast_frames_good_high_rxmcastghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_crc_error_frames_low_rxcrcerlo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_crc_error_frames_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_crc_error_frames_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxcrcerlo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_crc_error_frames_low_rxcrcerlo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_crc_error_frames_high_rxcrcerhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_crc_error_frames_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_crc_error_frames_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxcrcerhi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_crc_error_frames_high_rxcrcerhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_runt_error_frames_rxrunter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_runt_error_frames_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_runt_error_frames_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxrunter;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_runt_error_frames_rxrunter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_jabber_error_frames_rxjaberer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_jabber_error_frames_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_jabber_error_frames_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxjaberer;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_jabber_error_frames_rxjaberer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_undersize_frames_good_rxusizeg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_undersize_frames_good_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_undersize_frames_good_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxusizeg;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_undersize_frames_good_rxusizeg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_oversize_frames_good_rxosizeg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_oversize_frames_good_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_oversize_frames_good_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxosizeg;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_oversize_frames_good_rxosizeg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_low_rx64octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_64octets_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_64octets_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx64octgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_low_rx64octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_high_rx64octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_64octets_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_64octets_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx64octgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_64octets_frames_good_bad_high_rx64octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_low_rx65_127octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_65to127octets_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_65to127octets_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx65_127octgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_low_rx65_127octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_high_rx65_127octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_65to127octets_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_65to127octets_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx65_127octgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_65to127octets_frames_good_bad_high_rx65_127octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_low_rx128_255octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_128to255octets_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_128to255octets_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx128_255octgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_low_rx128_255octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_high_rx128_255octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_128to255octets_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_128to255octets_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx128_255octgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_128to255octets_frames_good_bad_high_rx128_255octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_low_rx256_511octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_256to511octets_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_256to511octets_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx256_511octgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_low_rx256_511octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_high_rx256_511octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_256to511octets_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_256to511octets_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx256_511octgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_256to511octets_frames_good_bad_high_rx256_511octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_low_rx512_1023octgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_512to1023octets_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_512to1023octets_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx512_1023octgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_low_rx512_1023octgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_high_rx512_1023octgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_512to1023octets_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_512to1023octets_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx512_1023octgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_512to1023octets_frames_good_bad_high_rx512_1023octgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_low_rx1024_maxgboctlo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_1024tomaxoctets_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_1024tomaxoctets_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx1024_maxgboctlo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_low_rx1024_maxgboctlo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_high_rx1024_maxgbocthi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_1024tomaxoctets_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_1024tomaxoctets_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx1024_maxgbocthi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_1024tomaxoctets_frames_good_bad_high_rx1024_maxgbocthi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_unicast_frames_good_low_rxucastglo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_unicast_frames_good_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_unicast_frames_good_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxucastglo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_unicast_frames_good_low_rxucastglo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_unicast_frames_good_high_rxucastghi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_unicast_frames_good_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_unicast_frames_good_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxucastghi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_unicast_frames_good_high_rxucastghi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_length_error_frames_low_rxlenerrlo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_length_error_frames_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_length_error_frames_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxlenerrlo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_length_error_frames_low_rxlenerrlo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_length_error_frames_high_rxlenerrhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_length_error_frames_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_length_error_frames_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxlenerrhi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_length_error_frames_high_rxlenerrhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_outofrange_frames_low_rxorangelo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_outofrange_frames_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_outofrange_frames_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxorangelo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_outofrange_frames_low_rxorangelo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_outofrange_frames_high_rxorangehi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_outofrange_frames_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_outofrange_frames_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxorangehi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_outofrange_frames_high_rxorangehi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_pause_frames_low_rxpauselo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_pause_frames_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_pause_frames_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxpauselo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_pause_frames_low_rxpauselo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_pause_frames_high_rxpausehi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_pause_frames_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_pause_frames_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxpausehi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_pause_frames_high_rxpausehi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_fifooverflow_frames_low_rxfovflo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_fifooverflow_frames_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_fifooverflow_frames_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxfovflo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_fifooverflow_frames_low_rxfovflo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_fifooverflow_frames_high_rxfovfhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_fifooverflow_frames_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_fifooverflow_frames_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxfovfhi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_fifooverflow_frames_high_rxfovfhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_low_rxvlangblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_vlan_frames_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_vlan_frames_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxvlangblo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_low_rxvlangblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_high_rxvlangbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_vlan_frames_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_vlan_frames_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxvlangbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_vlan_frames_good_bad_high_rxvlangbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_watchdog_error_frames_rxwdogerr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_watchdog_error_frames_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_watchdog_error_frames_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxwdogerr;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_watchdog_error_frames_rxwdogerr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_lpi_usec_cntr_rxlpiusc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_lpi_usec_cntr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_lpi_usec_cntr_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxlpiusc;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_lpi_usec_cntr_rxlpiusc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_lpi_tran_cntr_rxlpitrc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_lpi_tran_cntr_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_lpi_tran_cntr_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxlpitrc;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_lpi_tran_cntr_rxlpitrc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_low_rxdfcntgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_discard_frame_count_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_discard_frame_count_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxdfcntgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_low_rxdfcntgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_high_rxdfcntgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_discard_frame_count_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_discard_frame_count_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxdfcntgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_discard_frame_count_good_bad_high_rxdfcntgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_low_rxdocntgblo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_discard_octet_count_good_bad_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_discard_octet_count_good_bad_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxdocntgblo;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_low_rxdocntgblo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_high_rxdocntgbhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union rx_discard_octet_count_good_bad_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_rx_discard_octet_count_good_bad_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxdocntgbhi;
+	return ret;
+}
+
+sw_error_t
+hppe_rx_discard_octet_count_good_bad_high_rxdocntgbhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
diff --git a/qca-ssdk/src/hsl/hppe/hppe_xgportctrl.c b/qca-ssdk/src/hsl/hppe/hppe_xgportctrl.c
new file mode 100755
index 0000000..2caddc7
--- /dev/null
+++ b/qca-ssdk/src/hsl/hppe/hppe_xgportctrl.c
@@ -0,0 +1,6074 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hppe_reg_access.h"
+#include "hppe_xgportctrl_reg.h"
+#include "hppe_xgportctrl.h"
+
+sw_error_t
+hppe_mac_tx_configuration_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_tx_configuration_u *value)
+{
+	if (index >= MAC_TX_CONFIGURATION_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_TX_CONFIGURATION_ADDRESS + \
+				index * MAC_TX_CONFIGURATION_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_tx_configuration_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_tx_configuration_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_TX_CONFIGURATION_ADDRESS + \
+				index * MAC_TX_CONFIGURATION_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_rx_configuration_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_configuration_u *value)
+{
+	if (index >= MAC_RX_CONFIGURATION_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_RX_CONFIGURATION_ADDRESS + \
+				index * MAC_RX_CONFIGURATION_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_rx_configuration_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_configuration_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_RX_CONFIGURATION_ADDRESS + \
+				index * MAC_RX_CONFIGURATION_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_packet_filter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_packet_filter_u *value)
+{
+	if (index >= MAC_PACKET_FILTER_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_PACKET_FILTER_ADDRESS + \
+				index * MAC_PACKET_FILTER_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_packet_filter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_packet_filter_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_PACKET_FILTER_ADDRESS + \
+				index * MAC_PACKET_FILTER_INC,
+				value->val);
+}
+#ifndef IN_PORTCONTROL_MINI
+
+sw_error_t
+hppe_mac_watchdog_timeout_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_watchdog_timeout_u *value)
+{
+	if (index >= MAC_WATCHDOG_TIMEOUT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_WATCHDOG_TIMEOUT_ADDRESS + \
+				index * MAC_WATCHDOG_TIMEOUT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_watchdog_timeout_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_watchdog_timeout_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_WATCHDOG_TIMEOUT_ADDRESS + \
+				index * MAC_WATCHDOG_TIMEOUT_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_vlan_tag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_vlan_tag_u *value)
+{
+	if (index >= MAC_VLAN_TAG_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_VLAN_TAG_ADDRESS + \
+				index * MAC_VLAN_TAG_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_vlan_tag_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_vlan_tag_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_VLAN_TAG_ADDRESS + \
+				index * MAC_VLAN_TAG_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_rx_eth_type_match_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_eth_type_match_u *value)
+{
+	if (index >= MAC_RX_ETH_TYPE_MATCH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_RX_ETH_TYPE_MATCH_ADDRESS + \
+				index * MAC_RX_ETH_TYPE_MATCH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_rx_eth_type_match_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_eth_type_match_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_RX_ETH_TYPE_MATCH_ADDRESS + \
+				index * MAC_RX_ETH_TYPE_MATCH_INC,
+				value->val);
+}
+#endif
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_q0_tx_flow_ctrl_u *value)
+{
+	if (index >= MAC_Q0_TX_FLOW_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_Q0_TX_FLOW_CTRL_ADDRESS + \
+				index * MAC_Q0_TX_FLOW_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_q0_tx_flow_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_Q0_TX_FLOW_CTRL_ADDRESS + \
+				index * MAC_Q0_TX_FLOW_CTRL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_flow_ctrl_u *value)
+{
+	if (index >= MAC_RX_FLOW_CTRL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_RX_FLOW_CTRL_ADDRESS + \
+				index * MAC_RX_FLOW_CTRL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_flow_ctrl_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_RX_FLOW_CTRL_ADDRESS + \
+				index * MAC_RX_FLOW_CTRL_INC,
+				value->val);
+}
+#ifndef IN_PORTCONTROL_MINI
+
+sw_error_t
+hppe_mac_interrupt_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_interrupt_status_u *value)
+{
+	if (index >= MAC_INTERRUPT_STATUS_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_INTERRUPT_STATUS_ADDRESS + \
+				index * MAC_INTERRUPT_STATUS_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_interrupt_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_interrupt_status_u *value)
+{
+	return SW_NOT_SUPPORTED;
+
+}
+
+sw_error_t
+hppe_mac_interrupt_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_interrupt_enable_u *value)
+{
+	if (index >= MAC_INTERRUPT_ENABLE_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_INTERRUPT_ENABLE_ADDRESS + \
+				index * MAC_INTERRUPT_ENABLE_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_interrupt_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_interrupt_enable_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_INTERRUPT_ENABLE_ADDRESS + \
+				index * MAC_INTERRUPT_ENABLE_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_rx_tx_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_tx_status_u *value)
+{
+	if (index >= MAC_RX_TX_STATUS_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_RX_TX_STATUS_ADDRESS + \
+				index * MAC_RX_TX_STATUS_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_rx_tx_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_rx_tx_status_u *value)
+{
+	return SW_NOT_SUPPORTED;
+
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_lpi_control_status_u *value)
+{
+	if (index >= MAC_LPI_CONTROL_STATUS_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_LPI_CONTROL_STATUS_ADDRESS + \
+				index * MAC_LPI_CONTROL_STATUS_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_lpi_control_status_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_LPI_CONTROL_STATUS_ADDRESS + \
+				index * MAC_LPI_CONTROL_STATUS_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_lpi_timers_control_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_lpi_timers_control_u *value)
+{
+	if (index >= MAC_LPI_TIMERS_CONTROL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_LPI_TIMERS_CONTROL_ADDRESS + \
+				index * MAC_LPI_TIMERS_CONTROL_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_lpi_timers_control_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_lpi_timers_control_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_LPI_TIMERS_CONTROL_ADDRESS + \
+				index * MAC_LPI_TIMERS_CONTROL_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_lpi_auto_entry_timer_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_lpi_auto_entry_timer_u *value)
+{
+	if (index >= MAC_LPI_AUTO_ENTRY_TIMER_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_LPI_AUTO_ENTRY_TIMER_ADDRESS + \
+				index * MAC_LPI_AUTO_ENTRY_TIMER_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_lpi_auto_entry_timer_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_lpi_auto_entry_timer_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_LPI_AUTO_ENTRY_TIMER_ADDRESS + \
+				index * MAC_LPI_AUTO_ENTRY_TIMER_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_1us_tic_counter_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_1us_tic_counter_u *value)
+{
+	if (index >= MAC_1US_TIC_COUNTER_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_1US_TIC_COUNTER_ADDRESS + \
+				index * MAC_1US_TIC_COUNTER_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_1us_tic_counter_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_1us_tic_counter_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_1US_TIC_COUNTER_ADDRESS + \
+				index * MAC_1US_TIC_COUNTER_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_address0_high_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_address0_high_u *value)
+{
+	if (index >= MAC_ADDRESS0_HIGH_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_ADDRESS0_HIGH_ADDRESS + \
+				index * MAC_ADDRESS0_HIGH_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_address0_high_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_address0_high_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_ADDRESS0_HIGH_ADDRESS + \
+				index * MAC_ADDRESS0_HIGH_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_address0_low_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_address0_low_u *value)
+{
+	if (index >= MAC_ADDRESS0_LOW_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_ADDRESS0_LOW_ADDRESS + \
+				index * MAC_ADDRESS0_LOW_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mac_address0_low_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mac_address0_low_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MAC_ADDRESS0_LOW_ADDRESS + \
+				index * MAC_ADDRESS0_LOW_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_receive_interrupt_u *value)
+{
+	if (index >= MMC_RECEIVE_INTERRUPT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MMC_RECEIVE_INTERRUPT_ADDRESS + \
+				index * MMC_RECEIVE_INTERRUPT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_receive_interrupt_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_transmit_interrupt_u *value)
+{
+	if (index >= MMC_TRANSMIT_INTERRUPT_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MMC_TRANSMIT_INTERRUPT_ADDRESS + \
+				index * MMC_TRANSMIT_INTERRUPT_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_transmit_interrupt_u *value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_receive_interrupt_enable_u *value)
+{
+	if (index >= MMC_RECEIVE_INTERRUPT_ENABLE_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MMC_RECEIVE_INTERRUPT_ENABLE_ADDRESS + \
+				index * MMC_RECEIVE_INTERRUPT_ENABLE_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_receive_interrupt_enable_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MMC_RECEIVE_INTERRUPT_ENABLE_ADDRESS + \
+				index * MMC_RECEIVE_INTERRUPT_ENABLE_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_transmit_interrupt_enable_u *value)
+{
+	if (index >= MMC_TRANSMIT_INTERRUPT_ENABLE_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_reg_get(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MMC_TRANSMIT_INTERRUPT_ENABLE_ADDRESS + \
+				index * MMC_TRANSMIT_INTERRUPT_ENABLE_INC,
+				&value->val);
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_transmit_interrupt_enable_u *value)
+{
+	return hppe_reg_set(
+				dev_id,
+				NSS_XGMAC_CSR_BASE_ADDR + MMC_TRANSMIT_INTERRUPT_ENABLE_ADDRESS + \
+				index * MMC_TRANSMIT_INTERRUPT_ENABLE_INC,
+				value->val);
+}
+
+sw_error_t
+hppe_mac_tx_configuration_vne_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vne;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_vne_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vne = value;
+	ret = hppe_mac_tx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_ddic_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ddic;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_ddic_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ddic = value;
+	ret = hppe_mac_tx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_te_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.te;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_te_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.te = value;
+	ret = hppe_mac_tx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_ipg_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipg;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_ipg_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipg = value;
+	ret = hppe_mac_tx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_ism_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ism;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_ism_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ism = value;
+	ret = hppe_mac_tx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_ifp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ifp;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_ifp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ifp = value;
+	ret = hppe_mac_tx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_sarc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.sarc;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_sarc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.sarc = value;
+	ret = hppe_mac_tx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_isr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.isr;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_isr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.isr = value;
+	ret = hppe_mac_tx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_ss_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ss;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_ss_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ss = value;
+	ret = hppe_mac_tx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_g9991en_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.g9991en;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_g9991en_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.g9991en = value;
+	ret = hppe_mac_tx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_uss_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.uss;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_uss_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.uss = value;
+	ret = hppe_mac_tx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_vnm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vnm;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_vnm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vnm = value;
+	ret = hppe_mac_tx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_tx_configuration_jd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.jd;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_mac_tx_configuration_jd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_tx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_tx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.jd = value;
+	ret = hppe_mac_tx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+#ifndef IN_PORTCONTROL_MINI
+
+sw_error_t
+hppe_mac_rx_configuration_lm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lm;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_lm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.lm = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_je_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.je;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_je_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.je = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_arpen_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.arpen;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_arpen_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.arpen = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_elen_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.elen;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_elen_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.elen = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_gmpslce_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.gmpslce;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_mac_rx_configuration_gmpslce_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.gmpslce = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+#ifndef IN_PORTCONTROL_MINI
+
+sw_error_t
+hppe_mac_rx_configuration_hdsms_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.hdsms;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_hdsms_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hdsms = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_spen_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.spen;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_spen_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.spen = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_usp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.usp;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_usp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.usp = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_ipc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipc;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_ipc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipc = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+#endif
+sw_error_t
+hppe_mac_rx_configuration_gpsl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.gpsl;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_gpsl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.gpsl = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+#ifndef IN_PORTCONTROL_MINI
+
+sw_error_t
+hppe_mac_rx_configuration_re_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.re;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_re_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.re = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_cst_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cst;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_cst_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cst = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_dcrcc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dcrcc;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_dcrcc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dcrcc = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_wd_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.wd;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_mac_rx_configuration_wd_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.wd = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+#ifndef IN_PORTCONTROL_MINI
+
+sw_error_t
+hppe_mac_rx_configuration_acs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.acs;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_acs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.acs = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_s2kp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.s2kp;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_configuration_s2kp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_configuration_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_configuration_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.s2kp = value;
+	ret = hppe_mac_rx_configuration_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_pcf_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pcf;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_mac_packet_filter_pcf_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pcf = value;
+	ret = hppe_mac_packet_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+#ifndef IN_PORTCONTROL_MINI
+
+sw_error_t
+hppe_mac_packet_filter_hmc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.hmc;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_hmc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hmc = value;
+	ret = hppe_mac_packet_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_dntu_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dntu;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_dntu_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dntu = value;
+	ret = hppe_mac_packet_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_saf_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.saf;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_saf_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.saf = value;
+	ret = hppe_mac_packet_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_dbf_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dbf;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_dbf_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dbf = value;
+	ret = hppe_mac_packet_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_huc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.huc;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_huc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.huc = value;
+	ret = hppe_mac_packet_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_vtfe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vtfe;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_vtfe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vtfe = value;
+	ret = hppe_mac_packet_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_daif_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.daif;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_daif_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.daif = value;
+	ret = hppe_mac_packet_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_ra_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ra;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_ra_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ra = value;
+	ret = hppe_mac_packet_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_hpf_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.hpf;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_hpf_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.hpf = value;
+	ret = hppe_mac_packet_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_pm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pm;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_pm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pm = value;
+	ret = hppe_mac_packet_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_vucc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vucc;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_vucc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vucc = value;
+	ret = hppe_mac_packet_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_pr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pr;
+	return ret;
+}
+#endif
+sw_error_t
+hppe_mac_packet_filter_pr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pr = value;
+	ret = hppe_mac_packet_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+#ifndef IN_PORTCONTROL_MINI
+
+sw_error_t
+hppe_mac_packet_filter_ipfe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ipfe;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_ipfe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipfe = value;
+	ret = hppe_mac_packet_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_saif_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.saif;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_packet_filter_saif_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_packet_filter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_packet_filter_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.saif = value;
+	ret = hppe_mac_packet_filter_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_watchdog_timeout_pwe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_watchdog_timeout_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_watchdog_timeout_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pwe;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_watchdog_timeout_pwe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_watchdog_timeout_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_watchdog_timeout_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pwe = value;
+	ret = hppe_mac_watchdog_timeout_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_watchdog_timeout_wto_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_watchdog_timeout_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_watchdog_timeout_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.wto;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_watchdog_timeout_wto_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_watchdog_timeout_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_watchdog_timeout_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.wto = value;
+	ret = hppe_mac_watchdog_timeout_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_eivls_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.eivls;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_eivls_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.eivls = value;
+	ret = hppe_mac_vlan_tag_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_vthm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vthm;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_vthm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vthm = value;
+	ret = hppe_mac_vlan_tag_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_vl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vl;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_vl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vl = value;
+	ret = hppe_mac_vlan_tag_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_dovltc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dovltc;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_dovltc_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dovltc = value;
+	ret = hppe_mac_vlan_tag_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_etv_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.etv;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_etv_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.etv = value;
+	ret = hppe_mac_vlan_tag_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_erivlt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.erivlt;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_erivlt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.erivlt = value;
+	ret = hppe_mac_vlan_tag_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_eivlrxs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.eivlrxs;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_eivlrxs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.eivlrxs = value;
+	ret = hppe_mac_vlan_tag_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_vtim_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vtim;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_vtim_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.vtim = value;
+	ret = hppe_mac_vlan_tag_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_edvlp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.edvlp;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_edvlp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.edvlp = value;
+	ret = hppe_mac_vlan_tag_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_evlrxs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.evlrxs;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_evlrxs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.evlrxs = value;
+	ret = hppe_mac_vlan_tag_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_evls_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.evls;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_evls_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.evls = value;
+	ret = hppe_mac_vlan_tag_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_esvl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.esvl;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_esvl_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.esvl = value;
+	ret = hppe_mac_vlan_tag_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_ersvlm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ersvlm;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_vlan_tag_ersvlm_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_vlan_tag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_vlan_tag_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ersvlm = value;
+	ret = hppe_mac_vlan_tag_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_eth_type_match_et_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_eth_type_match_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_eth_type_match_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.et;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_eth_type_match_et_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_eth_type_match_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_eth_type_match_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.et = value;
+	ret = hppe_mac_rx_eth_type_match_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_pt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_q0_tx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pt;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_pt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_q0_tx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pt = value;
+	ret = hppe_mac_q0_tx_flow_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_plt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_q0_tx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.plt;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_plt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_q0_tx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.plt = value;
+	ret = hppe_mac_q0_tx_flow_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_tfe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_q0_tx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tfe;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_tfe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_q0_tx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tfe = value;
+	ret = hppe_mac_q0_tx_flow_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_fcb_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_q0_tx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.fcb;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_fcb_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_q0_tx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fcb = value;
+	ret = hppe_mac_q0_tx_flow_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_dapq_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_q0_tx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dapq;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_q0_tx_flow_ctrl_dapq_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_q0_tx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dapq = value;
+	ret = hppe_mac_q0_tx_flow_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_pfce_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_flow_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pfce;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_pfce_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_flow_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pfce = value;
+	ret = hppe_mac_rx_flow_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_up_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_flow_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.up;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_up_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_flow_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.up = value;
+	ret = hppe_mac_rx_flow_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_rfe_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_flow_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rfe;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_flow_ctrl_rfe_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_flow_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_flow_ctrl_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rfe = value;
+	ret = hppe_mac_rx_flow_ctrl_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_txesis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txesis;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_txesis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.txesis = value;
+	ret = hppe_mac_interrupt_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_gpiis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.gpiis;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_gpiis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.gpiis = value;
+	ret = hppe_mac_interrupt_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_tsis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tsis;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_tsis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tsis = value;
+	ret = hppe_mac_interrupt_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_mmctxis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmctxis;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_mmctxis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmctxis = value;
+	ret = hppe_mac_interrupt_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_ls_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ls;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_ls_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ls = value;
+	ret = hppe_mac_interrupt_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_mmcrxis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.mmcrxis;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_mmcrxis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mmcrxis = value;
+	ret = hppe_mac_interrupt_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_smi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.smi;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_smi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.smi = value;
+	ret = hppe_mac_interrupt_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_pmtis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pmtis;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_pmtis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pmtis = value;
+	ret = hppe_mac_interrupt_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_rxesis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxesis;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_rxesis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rxesis = value;
+	ret = hppe_mac_interrupt_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_lpiis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lpiis;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_status_lpiis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_interrupt_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.lpiis = value;
+	ret = hppe_mac_interrupt_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_enable_tsie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tsie;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_enable_tsie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mac_interrupt_enable_lpiie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lpiie;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_enable_lpiie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mac_interrupt_enable_txesie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txesie;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_enable_txesie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mac_interrupt_enable_pmtie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pmtie;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_enable_pmtie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mac_interrupt_enable_rxesie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxesie;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_interrupt_enable_rxesie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mac_rx_tx_status_tjt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_tx_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_tx_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tjt;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_tx_status_tjt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_tx_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_tx_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tjt = value;
+	ret = hppe_mac_rx_tx_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_tx_status_rwt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_rx_tx_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_tx_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rwt;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_rx_tx_status_rwt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_rx_tx_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_rx_tx_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rwt = value;
+	ret = hppe_mac_rx_tx_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_tlpien_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tlpien;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_tlpien_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tlpien = value;
+	ret = hppe_mac_lpi_control_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_lpitcse_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lpitcse;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_lpitcse_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.lpitcse = value;
+	ret = hppe_mac_lpi_control_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_rxrstp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxrstp;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_rxrstp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rxrstp = value;
+	ret = hppe_mac_lpi_control_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_lpite_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lpite;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_lpite_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.lpite = value;
+	ret = hppe_mac_lpi_control_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_pls_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pls;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_pls_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pls = value;
+	ret = hppe_mac_lpi_control_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_rlpiex_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rlpiex;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_rlpiex_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rlpiex = value;
+	ret = hppe_mac_lpi_control_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_rlpien_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rlpien;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_rlpien_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rlpien = value;
+	ret = hppe_mac_lpi_control_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_rlpist_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rlpist;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_rlpist_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rlpist = value;
+	ret = hppe_mac_lpi_control_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_tlpist_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tlpist;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_tlpist_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tlpist = value;
+	ret = hppe_mac_lpi_control_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_txrstp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txrstp;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_txrstp_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.txrstp = value;
+	ret = hppe_mac_lpi_control_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_plsdis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.plsdis;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_plsdis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.plsdis = value;
+	ret = hppe_mac_lpi_control_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_lpitxa_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lpitxa;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_lpitxa_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.lpitxa = value;
+	ret = hppe_mac_lpi_control_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_tlpiex_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tlpiex;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_tlpiex_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tlpiex = value;
+	ret = hppe_mac_lpi_control_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_lpitxen_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lpitxen;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_control_status_lpitxen_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	union mac_lpi_control_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_control_status_get(dev_id, index, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.lpitxen = value;
+	ret = hppe_mac_lpi_control_status_set(dev_id, index, &reg_val);
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_timers_control_lst_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_timers_control_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_timers_control_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lst;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_timers_control_lst_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mac_lpi_timers_control_twt_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_timers_control_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_timers_control_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.twt;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_timers_control_twt_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mac_lpi_auto_entry_timer_lpiet_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_lpi_auto_entry_timer_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_lpi_auto_entry_timer_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lpiet;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_lpi_auto_entry_timer_lpiet_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mac_1us_tic_counter_tic_1us_cntr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_1us_tic_counter_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_1us_tic_counter_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tic_1us_cntr;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_1us_tic_counter_tic_1us_cntr_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mac_address0_high_addrhi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_address0_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_address0_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.addrhi;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_address0_high_addrhi_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mac_address0_high_ae_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_address0_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_address0_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.ae;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_address0_high_ae_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mac_address0_high_dcs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_address0_high_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_address0_high_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.dcs;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_address0_high_dcs_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mac_address0_low_addrlo_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mac_address0_low_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mac_address0_low_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.addrlo;
+	return ret;
+}
+
+sw_error_t
+hppe_mac_address0_low_addrlo_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxorangefis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxorangefis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxorangefis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxlenerfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxlenerfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxlenerfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx65t127octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx65t127octgbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx65t127octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxprmmcis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxprmmcis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxprmmcis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx512t1023octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx512t1023octgbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx512t1023octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxgboctis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxgboctis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxgboctis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxlpiuscis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxlpiuscis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxlpiuscis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxjaberfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxjaberfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxjaberfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxvlangbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxvlangbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxvlangbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxpausfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxpausfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxpausfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxcrcerfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxcrcerfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxcrcerfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxdisocgbis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxdisocgbis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxdisocgbis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxwdogfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxwdogfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxwdogfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx128t255octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx128t255octgbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx128t255octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxdisfcgbis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxdisfcgbis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxdisfcgbis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxosizegfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxosizegfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxosizegfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx1024tmaxoctgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx1024tmaxoctgbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx1024tmaxoctgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxruntfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxruntfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxruntfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxmcgfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxmcgfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxmcgfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx256t511octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx256t511octgbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx256t511octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx64octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx64octgbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rx64octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxfovfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxfovfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxfovfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxgoctis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxgoctis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxgoctis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxgbfrmis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxgbfrmis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxgbfrmis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxlpitrcis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxlpitrcis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxlpitrcis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxbcgfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxbcgfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxbcgfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxusizegfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxusizegfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxusizegfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxucgfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxucgfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_rxucgfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgbfrmis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txgbfrmis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgbfrmis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txprmmcis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txprmmcis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txprmmcis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx1024tmaxoctgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx1024tmaxoctgbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx1024tmaxoctgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx256t511octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx256t511octgbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx256t511octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txlpitrcis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txlpitrcis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txlpitrcis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txbcgfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txbcgfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txbcgfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx64octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx64octgbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx64octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txlpiuscis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txlpiuscis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txlpiuscis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txuflowerfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txuflowerfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txuflowerfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txbcgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txbcgbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txbcgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txpausfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txpausfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txpausfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txvlangfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txvlangfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txvlangfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgboctis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txgboctis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgboctis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgfrmis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txgfrmis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgfrmis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx512t1023octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx512t1023octgbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx512t1023octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txmcgfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txmcgfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txmcgfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txucgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txucgbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txucgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx65t127octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx65t127octgbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx65t127octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txmcgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txmcgbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txmcgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx128t255octgbfis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx128t255octgbfis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_tx128t255octgbfis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgoctis_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txgoctis;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_txgoctis_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxprmmcise_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxprmmcise;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxprmmcise_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx65t127octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx65t127octgbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx65t127octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxruntfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxruntfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxruntfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxcrcerfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxcrcerfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxcrcerfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx256t511octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx256t511octgbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx256t511octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxlenerfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxlenerfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxlenerfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxusizegfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxusizegfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxusizegfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxosizegfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxosizegfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxosizegfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxfovfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxfovfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxfovfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxmcgfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxmcgfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxmcgfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxvlangbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxvlangbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxvlangbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxwdogfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxwdogfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxwdogfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxdisocie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxdisocie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxdisocie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxgbfrmie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxgbfrmie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxgbfrmie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxjaberfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxjaberfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxjaberfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxlpiuscie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxlpiuscie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxlpiuscie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxucgfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxucgfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxucgfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx1024tmaxoctgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx1024tmaxoctgbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx1024tmaxoctgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxpausfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxpausfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxpausfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxdisfcie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxdisfcie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxdisfcie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxgoctie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxgoctie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxgoctie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxgboctie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxgboctie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxgboctie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx128t255octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx128t255octgbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx128t255octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxlpitrcie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxlpitrcie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxlpitrcie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxbcgfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxbcgfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxbcgfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx64octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx64octgbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx64octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxorangefie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rxorangefie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rxorangefie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx512t1023octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_receive_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx512t1023octgbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_receive_interrupt_enable_rx512t1023octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txucgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txucgbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txucgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx64octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx64octgbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx64octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txbcgfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txbcgfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txbcgfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgbfrmie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txgbfrmie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgbfrmie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgfrmie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txgfrmie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgfrmie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgoctie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txgoctie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgoctie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txbcgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txbcgbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txbcgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txlpitrcie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txlpitrcie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txlpitrcie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txvlangfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txvlangfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txvlangfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txpausfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txpausfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txpausfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgboctie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txgboctie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txgboctie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txmcgfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txmcgfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txmcgfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txuflowerfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txuflowerfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txuflowerfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txlpiuscie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txlpiuscie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txlpiuscie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx256t511octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx256t511octgbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx256t511octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx65t127octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx65t127octgbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx65t127octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx128t255octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx128t255octgbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx128t255octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx512t1023octgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx512t1023octgbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx512t1023octgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx1024tmaxoctgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx1024tmaxoctgbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_tx1024tmaxoctgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txprmmcise_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txprmmcise;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txprmmcise_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txmcgbfie_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union mmc_transmit_interrupt_enable_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.txmcgbfie;
+	return ret;
+}
+
+sw_error_t
+hppe_mmc_transmit_interrupt_enable_txmcgbfie_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t value)
+{
+	return SW_NOT_SUPPORTED;
+}
+#endif
diff --git a/qca-ssdk/src/hsl/hsl_acl.c b/qca-ssdk/src/hsl/hsl_acl.c
new file mode 100755
index 0000000..2361fae
--- /dev/null
+++ b/qca-ssdk/src/hsl/hsl_acl.c
@@ -0,0 +1,972 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#include "sw_config.h"
+#include "aos_head.h"
+#include "sw_error.h"
+#include "shared_func.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+
+typedef struct
+{
+    a_uint32_t pri;
+    a_uint32_t addr;
+    a_uint32_t size;
+    a_uint32_t status;
+    a_uint32_t info;
+} hsl_acl_blk_t;
+
+typedef struct
+{
+    a_uint32_t used_blk;
+    a_uint32_t total_blk;
+    a_uint32_t free_rsc;
+    hsl_acl_blk_t *blk_ent;
+} hsl_acl_pool_t;
+
+#define MEM_FREE    1
+#define MEM_USED    2
+
+static hsl_acl_pool_t acl_pool[SW_MAX_NR_DEV];
+
+static sw_error_t
+_hsl_acl_blk_loc(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t * idx);
+
+static sw_error_t
+_hsl_acl_blk_comb(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t nr);
+
+static sw_error_t _hsl_acl_free_blk_comb(a_uint32_t dev_id, a_uint32_t idx);
+
+static sw_error_t
+_hsl_acl_blk_ent_left_mv(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t offset);
+
+static sw_error_t
+_hsl_acl_blk_ent_right_mv(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t offset);
+
+static sw_error_t
+_hsl_acl_blk_left_defrag(a_uint32_t dev_id, a_uint32_t p_idx, a_uint32_t t_size,
+                         a_bool_t b_must, a_uint32_t * f_idx, a_uint32_t * f_nr,
+                         a_uint32_t * f_size);
+
+static sw_error_t
+_hsl_acl_blk_right_defrag(a_uint32_t dev_id, a_uint32_t p_idx,
+                          a_uint32_t t_size, a_bool_t b_must,
+                          a_uint32_t * f_idx, a_uint32_t * f_nr,
+                          a_uint32_t * f_size);
+
+static sw_error_t
+_hsl_acl_blk_alloc(a_uint32_t dev_id, a_uint32_t free_idx, a_uint32_t pri,
+                   a_uint32_t size, a_uint32_t info, a_uint32_t * addr);
+
+static sw_error_t
+_hsl_acl_blk_reduce(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t new_size);
+
+static sw_error_t
+_hsl_acl_blk_left_enlarge(a_uint32_t dev_id, a_uint32_t idx,
+                          a_uint32_t new_size);
+
+static sw_error_t
+_hsl_acl_blk_right_enlarge(a_uint32_t dev_id, a_uint32_t idx,
+                           a_uint32_t new_size);
+
+static sw_error_t
+_hsl_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_addr, a_uint32_t dest_addr,
+                   a_uint32_t size);
+
+static sw_error_t
+_hsl_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t size);
+
+static sw_error_t
+_hsl_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr,
+                     a_uint32_t new_addr, a_uint32_t info);
+
+//#define ACL_POOL_DEBUG
+#ifdef ACL_POOL_DEBUG
+static void
+_hsl_acl_blk_dump(a_uint32_t dev_id, const char *info)
+{
+    a_uint32_t i;
+
+    aos_printk("\n%s dev_id=%d  free_rsc=%d  total_blk=%d  used_blk=%d",
+               info, dev_id, acl_pool[dev_id].free_rsc,
+               acl_pool[dev_id].total_blk, acl_pool[dev_id].used_blk);
+
+    for (i = 0; i < acl_pool[dev_id].used_blk; i++)
+    {
+        aos_printk("\naddr=%d  status = %d  size=%d  list_id=%d  list_pri=%d",
+                   acl_pool[dev_id].blk_ent[i].addr,
+                   acl_pool[dev_id].blk_ent[i].status,
+                   acl_pool[dev_id].blk_ent[i].size,
+                   acl_pool[dev_id].blk_ent[i].info,
+                   acl_pool[dev_id].blk_ent[i].pri);
+    }
+    aos_printk("\n");
+}
+#else
+#define _hsl_acl_blk_dump(dev_id, info)
+#endif
+
+static sw_error_t
+_hsl_acl_blk_loc(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t * idx)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < acl_pool[dev_id].used_blk; i++)
+    {
+        if (addr == acl_pool[dev_id].blk_ent[i].addr)
+        {
+            *idx = i;
+            return SW_OK;
+        }
+    }
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_hsl_acl_blk_comb(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t nr)
+{
+    sw_error_t rv;
+    a_uint32_t i, size;
+
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_comb before combine");
+
+    if ((idx + nr) > acl_pool[dev_id].used_blk)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (nr < 2)
+    {
+        _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_comb after combine");
+        return SW_OK;
+    }
+
+    size = 0;
+    for (i = 0; i < nr; i++)
+    {
+        size += acl_pool[dev_id].blk_ent[idx + i].size;
+    }
+    acl_pool[dev_id].blk_ent[idx].size = size;
+
+    rv = _hsl_acl_blk_ent_left_mv(dev_id, idx + nr, nr - 1);
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_comb after combine");
+    return rv;
+}
+
+static sw_error_t
+_hsl_acl_free_blk_comb(a_uint32_t dev_id, a_uint32_t idx)
+{
+    sw_error_t rv;
+    a_uint32_t first, num;
+
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_free_blk_comb before combine");
+
+    first = idx;
+    num = 1;
+    if (0 != idx)
+    {
+        if (MEM_FREE == acl_pool[dev_id].blk_ent[idx - 1].status)
+        {
+            num++;
+            first = idx - 1;
+        }
+    }
+
+    if ((acl_pool[dev_id].used_blk - 1) != idx)
+    {
+        if (MEM_FREE == acl_pool[dev_id].blk_ent[idx + 1].status)
+        {
+            num++;
+        }
+    }
+
+    rv = _hsl_acl_blk_comb(dev_id, first, num);
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_free_blk_comb after combine");
+    return rv;
+}
+
+static sw_error_t
+_hsl_acl_blk_ent_left_mv(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t offset)
+{
+    a_uint32_t i;
+
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_ent_left_mv before move");
+
+    if (offset > idx)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = idx; i < acl_pool[dev_id].used_blk; i++)
+    {
+        acl_pool[dev_id].blk_ent[i - offset] = acl_pool[dev_id].blk_ent[i];
+    }
+
+    acl_pool[dev_id].used_blk -= offset;
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_ent_left_mv after move");
+    return SW_OK;
+}
+
+static sw_error_t
+_hsl_acl_blk_ent_right_mv(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t offset)
+{
+    a_uint32_t i, cnt, tmp;
+
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_ent_right_mv before move");
+
+    if (acl_pool[dev_id].total_blk < (acl_pool[dev_id].used_blk + offset))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    /* we support to increase used block number without block moving */
+    if (idx > acl_pool[dev_id].used_blk)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    cnt = acl_pool[dev_id].used_blk - idx;
+    tmp = acl_pool[dev_id].used_blk - 1;
+    for (i = 0; i < cnt; i++)
+    {
+        acl_pool[dev_id].blk_ent[tmp + offset - i]
+            = acl_pool[dev_id].blk_ent[tmp - i];
+    }
+
+    acl_pool[dev_id].used_blk += offset;
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_ent_right_mv after move");
+    return SW_OK;
+}
+
+static sw_error_t
+_hsl_acl_blk_left_defrag(a_uint32_t dev_id, a_uint32_t p_idx, a_uint32_t t_size,
+                         a_bool_t b_must, a_uint32_t * f_idx, a_uint32_t * f_nr,
+                         a_uint32_t * f_size)
+{
+    sw_error_t rv;
+    a_int32_t idx;
+    a_uint32_t i, f_rsc, f_blk, dest_addr;
+
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_left_defrag before defrag");
+
+    f_rsc = 0;
+    for (idx = p_idx - 1; idx >= 0; idx--)
+    {
+        if (MEM_FREE == acl_pool[dev_id].blk_ent[idx].status)
+        {
+            f_rsc += acl_pool[dev_id].blk_ent[idx].size;
+        }
+
+        if (t_size <= f_rsc)
+        {
+            break;
+        }
+    }
+
+    if ((f_rsc < t_size) && (A_TRUE == b_must))
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    if (0 == f_rsc)
+    {
+        *f_idx  = p_idx;
+        *f_nr   = 0;
+        *f_size = 0;
+        _hsl_acl_blk_dump(dev_id, "_hsl_acl_left_defrag after defrag");
+        return SW_OK;
+    }
+
+    if (idx < 0)
+    {
+        idx = 0;
+    }
+
+    f_blk = 0;
+    f_rsc = 0;
+    dest_addr = acl_pool[dev_id].blk_ent[idx].addr;
+    for (i = idx; i < p_idx; i++)
+    {
+        if (MEM_FREE == acl_pool[dev_id].blk_ent[i].status)
+        {
+            f_blk += 1;
+            f_rsc += acl_pool[dev_id].blk_ent[i].size;
+        }
+
+        if (MEM_USED == acl_pool[dev_id].blk_ent[i].status)
+        {
+            if (dest_addr != acl_pool[dev_id].blk_ent[i].addr)
+            {
+                /* update acl rules hardware position */
+                rv = _hsl_acl_rule_copy(dev_id,
+                                        acl_pool[dev_id].blk_ent[i].addr,
+                                        dest_addr,
+                                        acl_pool[dev_id].blk_ent[i].size);
+                SW_RTN_ON_ERROR(rv);
+
+                rv = _hsl_acl_addr_update(dev_id,
+                                          acl_pool[dev_id].blk_ent[i].addr,
+                                          dest_addr,
+                                          acl_pool[dev_id].blk_ent[i].info);
+                SW_RTN_ON_ERROR(rv);
+
+                /* update acl memory block control infomation */
+                acl_pool[dev_id].blk_ent[i - f_blk] =
+                    acl_pool[dev_id].blk_ent[i];
+                acl_pool[dev_id].blk_ent[i - f_blk].addr -= f_rsc;
+            }
+            dest_addr += acl_pool[dev_id].blk_ent[i].size;
+        }
+    }
+
+    for (i = p_idx - f_blk; i < p_idx; i++)
+    {
+        acl_pool[dev_id].blk_ent[i].status = MEM_FREE;
+        acl_pool[dev_id].blk_ent[i].addr = dest_addr;
+        acl_pool[dev_id].blk_ent[i].size = 0;
+        acl_pool[dev_id].blk_ent[i].info = 0;
+        acl_pool[dev_id].blk_ent[i].pri  = 0;
+    }
+    acl_pool[dev_id].blk_ent[p_idx - f_blk].size = f_rsc;
+
+    *f_idx = p_idx - f_blk;
+    *f_nr = f_blk;
+    *f_size = f_rsc;
+    rv = _hsl_acl_rule_invalid(dev_id, acl_pool[dev_id].blk_ent[*f_idx].addr,
+                               f_rsc);
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_left_defrag after defrag");
+    return rv;
+}
+
+static sw_error_t
+_hsl_acl_blk_right_defrag(a_uint32_t dev_id, a_uint32_t p_idx,
+                          a_uint32_t t_size, a_bool_t b_must,
+                          a_uint32_t * f_idx, a_uint32_t * f_nr,
+                          a_uint32_t * f_size)
+{
+    sw_error_t rv;
+    a_uint32_t i, cnt;
+    a_uint32_t idx, f_rsc, f_blk, dest_addr;
+
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_right_defrag before defrag");
+
+    f_rsc = 0;
+    for (idx = p_idx; idx < acl_pool[dev_id].used_blk; idx++)
+    {
+        if (MEM_FREE == acl_pool[dev_id].blk_ent[idx].status)
+        {
+            f_rsc += acl_pool[dev_id].blk_ent[idx].size;
+        }
+
+        if (t_size <= f_rsc)
+        {
+            break;
+        }
+    }
+
+    if ((f_rsc < t_size) && (A_TRUE == b_must))
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    if (0 == f_rsc)
+    {
+        *f_idx  = p_idx;
+        *f_nr   = 0;
+        *f_size = 0;
+        _hsl_acl_blk_dump(dev_id, "_hsl_acl_right_defrag after defrag");
+        return SW_OK;
+    }
+
+    if (idx >= acl_pool[dev_id].used_blk)
+    {
+        idx = acl_pool[dev_id].used_blk - 1;
+    }
+
+    f_blk = 0;
+    f_rsc = 0;
+    dest_addr = acl_pool[dev_id].blk_ent[idx].addr
+                + acl_pool[dev_id].blk_ent[idx].size;
+    for (cnt = 0; cnt <= (idx -p_idx); cnt++)
+    {
+        i = idx - cnt;
+        if (MEM_FREE == acl_pool[dev_id].blk_ent[i].status)
+        {
+            f_blk += 1;
+            f_rsc += acl_pool[dev_id].blk_ent[i].size;
+        }
+
+        if (MEM_USED == acl_pool[dev_id].blk_ent[i].status)
+        {
+            dest_addr -= acl_pool[dev_id].blk_ent[i].size;
+
+            if (dest_addr != acl_pool[dev_id].blk_ent[i].addr)
+            {
+                /* update acl rules hardware position */
+                rv = _hsl_acl_rule_copy(dev_id,
+                                        acl_pool[dev_id].blk_ent[i].addr,
+                                        dest_addr,
+                                        acl_pool[dev_id].blk_ent[i].size);
+                SW_RTN_ON_ERROR(rv);
+
+                rv = _hsl_acl_addr_update(dev_id,
+                                          acl_pool[dev_id].blk_ent[i].addr,
+                                          dest_addr,
+                                          acl_pool[dev_id].blk_ent[i].info);
+                SW_RTN_ON_ERROR(rv);
+
+                /* update acl memory block control infomation */
+                acl_pool[dev_id].blk_ent[i + f_blk] =
+                    acl_pool[dev_id].blk_ent[i];
+                acl_pool[dev_id].blk_ent[i + f_blk].addr += f_rsc;
+            }
+        }
+    }
+
+    for (i = p_idx; i < (p_idx + f_blk); i++)
+    {
+        acl_pool[dev_id].blk_ent[i].status = MEM_FREE;
+        acl_pool[dev_id].blk_ent[i].size = 0;
+        acl_pool[dev_id].blk_ent[i].addr = dest_addr - f_rsc;
+    }
+    acl_pool[dev_id].blk_ent[p_idx].size = f_rsc;
+
+    *f_idx = p_idx;
+    *f_nr = f_blk;
+    *f_size = f_rsc;
+    rv = _hsl_acl_rule_invalid(dev_id, acl_pool[dev_id].blk_ent[*f_idx].addr,
+                               f_rsc);
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_right_defrag after defrag");
+    return rv;
+}
+
+static sw_error_t
+_hsl_acl_blk_alloc(a_uint32_t dev_id, a_uint32_t free_idx, a_uint32_t pri,
+                   a_uint32_t size, a_uint32_t info, a_uint32_t * addr)
+{
+    sw_error_t rv;
+    a_uint32_t i;
+    a_bool_t   b_comb = A_FALSE;
+
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_alloc before alloc");
+
+    if (MEM_FREE != acl_pool[dev_id].blk_ent[free_idx].status)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (size > acl_pool[dev_id].blk_ent[free_idx].size)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    if (size != acl_pool[dev_id].blk_ent[free_idx].size)
+    {
+        b_comb = A_TRUE;
+        i  = free_idx + 1;
+        rv = _hsl_acl_blk_ent_right_mv(dev_id, i, 1);
+        SW_RTN_ON_ERROR(rv);
+
+        acl_pool[dev_id].blk_ent[i].addr =
+            acl_pool[dev_id].blk_ent[free_idx].addr + size;
+        acl_pool[dev_id].blk_ent[i].size =
+            acl_pool[dev_id].blk_ent[free_idx].size - size;
+        acl_pool[dev_id].blk_ent[i].status = MEM_FREE;
+        acl_pool[dev_id].blk_ent[i].pri    = 0;
+        acl_pool[dev_id].blk_ent[i].info   = 0;
+    }
+
+    acl_pool[dev_id].blk_ent[free_idx].status = MEM_USED;
+    acl_pool[dev_id].blk_ent[free_idx].size = size;
+    acl_pool[dev_id].blk_ent[free_idx].pri  = pri;
+    acl_pool[dev_id].blk_ent[free_idx].info = info;
+    acl_pool[dev_id].free_rsc -= size;
+
+    if (A_TRUE == b_comb)
+    {
+        /* try to combine neighbor free memory blocks */
+        rv = _hsl_acl_free_blk_comb(dev_id, free_idx + 1);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    *addr = acl_pool[dev_id].blk_ent[free_idx].addr;
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_alloc after alloc");
+    return SW_OK;
+}
+
+static sw_error_t
+_hsl_acl_blk_reduce(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t new_size)
+{
+    sw_error_t rv;
+    a_uint32_t addr, old_size;
+
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_reduce before reduce");
+
+    addr = acl_pool[dev_id].blk_ent[idx].addr;
+    old_size = acl_pool[dev_id].blk_ent[idx].size;
+
+    rv = _hsl_acl_blk_ent_right_mv(dev_id, idx + 1, 1);
+    SW_RTN_ON_ERROR(rv);
+
+    acl_pool[dev_id].blk_ent[idx].size = new_size;
+    acl_pool[dev_id].blk_ent[idx + 1].status = MEM_FREE;
+    acl_pool[dev_id].blk_ent[idx + 1].addr = addr + new_size;
+    acl_pool[dev_id].blk_ent[idx + 1].size = old_size - new_size;
+    acl_pool[dev_id].blk_ent[idx + 1].pri  = 0;
+    acl_pool[dev_id].blk_ent[idx + 1].info = 0;
+    acl_pool[dev_id].free_rsc += (old_size - new_size);
+
+    /* try to combine neighbor free blocks */
+    rv = _hsl_acl_free_blk_comb(dev_id, idx + 1);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _hsl_acl_rule_invalid(dev_id, addr + new_size, old_size - new_size);
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_reduce after reduce");
+    return rv;
+}
+
+static sw_error_t
+_hsl_acl_blk_left_enlarge(a_uint32_t dev_id, a_uint32_t idx,
+                          a_uint32_t new_size)
+{
+    sw_error_t rv;
+    a_uint32_t old_size, old_addr, new_addr;
+
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_left_enlarge before enlarge");
+
+    if (0 == idx)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (MEM_FREE != acl_pool[dev_id].blk_ent[idx - 1].status)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    old_size = acl_pool[dev_id].blk_ent[idx].size;
+    if ((new_size - old_size) > acl_pool[dev_id].blk_ent[idx - 1].size)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    old_addr = acl_pool[dev_id].blk_ent[idx].addr;
+    new_addr = old_addr - (new_size - old_size);
+    rv = _hsl_acl_rule_copy(dev_id, old_addr, new_addr, old_size);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _hsl_acl_rule_invalid(dev_id, new_addr + old_size, new_size - old_size);
+    SW_RTN_ON_ERROR(rv);
+
+    acl_pool[dev_id].blk_ent[idx].size = new_size;
+    acl_pool[dev_id].blk_ent[idx].addr = new_addr;
+    acl_pool[dev_id].free_rsc         -= (new_size - old_size);
+    rv = _hsl_acl_addr_update(dev_id, old_addr, new_addr,
+                              acl_pool[dev_id].blk_ent[idx].info);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = SW_OK;
+    if ((new_size - old_size) == acl_pool[dev_id].blk_ent[idx - 1].size)
+    {
+        rv = _hsl_acl_blk_ent_left_mv(dev_id, idx, 1);
+    }
+    else
+    {
+        acl_pool[dev_id].blk_ent[idx - 1].size -= (new_size - old_size);
+    }
+
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_left_enlarge after enlarge");
+    return rv;
+}
+
+static sw_error_t
+_hsl_acl_blk_right_enlarge(a_uint32_t dev_id, a_uint32_t idx,
+                           a_uint32_t new_size)
+{
+    sw_error_t rv;
+    a_uint32_t old_size;
+
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_right_enlarge before enlarge");
+
+    if ((idx + 1) >= acl_pool[dev_id].used_blk)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (MEM_FREE != acl_pool[dev_id].blk_ent[idx + 1].status)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    old_size = acl_pool[dev_id].blk_ent[idx].size;
+    if ((new_size - old_size) > acl_pool[dev_id].blk_ent[idx + 1].size)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    acl_pool[dev_id].blk_ent[idx].size = new_size;
+    acl_pool[dev_id].free_rsc         -= (new_size - old_size);
+    rv = SW_OK;
+    if ((new_size - old_size) < acl_pool[dev_id].blk_ent[idx + 1].size)
+    {
+        acl_pool[dev_id].blk_ent[idx + 1].size -= (new_size - old_size);
+        acl_pool[dev_id].blk_ent[idx + 1].addr += (new_size - old_size);
+    }
+    else
+    {
+        if ((idx + 2) < acl_pool[dev_id].used_blk)
+        {
+            rv = _hsl_acl_blk_ent_left_mv(dev_id, idx + 2, 1);
+        }
+    }
+
+    _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_right_enlarge after enlarge");
+    return rv;
+}
+
+static sw_error_t
+_hsl_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_addr, a_uint32_t dest_addr,
+                   a_uint32_t size)
+{
+    hsl_acl_func_t * p_api;
+    sw_error_t       rv;
+
+    p_api = hsl_acl_ptr_get(dev_id);
+    SW_RTN_ON_NULL(p_api);
+
+    if (NULL == p_api->acl_rule_copy)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_rule_copy(dev_id, src_addr, dest_addr, size);
+    return rv;
+}
+
+static sw_error_t
+_hsl_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t size)
+{
+    hsl_acl_func_t * p_api;
+    sw_error_t       rv;
+
+    p_api = hsl_acl_ptr_get(dev_id);
+    SW_RTN_ON_NULL(p_api);
+
+    if (NULL == p_api->acl_rule_invalid)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_rule_invalid(dev_id, addr, size);
+    return rv;
+}
+
+static sw_error_t
+_hsl_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr,
+                     a_uint32_t new_addr, a_uint32_t info)
+{
+    hsl_acl_func_t * p_api;
+    sw_error_t       rv;
+
+    p_api = hsl_acl_ptr_get(dev_id);
+    SW_RTN_ON_NULL(p_api);
+
+    if (NULL == p_api->acl_addr_update)
+        return SW_NOT_SUPPORTED;
+
+    rv = p_api->acl_addr_update(dev_id, old_addr, new_addr, info);
+    return rv;
+}
+
+sw_error_t
+hsl_acl_pool_creat(a_uint32_t dev_id, a_uint32_t blk_nr, a_uint32_t rsc_nr)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    acl_pool[dev_id].blk_ent = aos_mem_alloc(blk_nr * (sizeof (hsl_acl_blk_t)));
+    if (NULL == acl_pool[dev_id].blk_ent)
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(acl_pool[dev_id].blk_ent, blk_nr * (sizeof (hsl_acl_blk_t)));
+
+    acl_pool[dev_id].used_blk  = 1;
+    acl_pool[dev_id].total_blk = blk_nr;
+    acl_pool[dev_id].free_rsc  = rsc_nr;
+
+    acl_pool[dev_id].blk_ent[0].addr = 0;
+    acl_pool[dev_id].blk_ent[0].size = rsc_nr;
+    acl_pool[dev_id].blk_ent[0].status = MEM_FREE;
+
+    _hsl_acl_blk_dump(dev_id, "hsl_acl_pool_creat after creat");
+    return SW_OK;
+}
+
+sw_error_t
+hsl_acl_pool_destroy(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (NULL == acl_pool[dev_id].blk_ent)
+    {
+        return SW_FAIL;
+    }
+
+    aos_mem_free(acl_pool[dev_id].blk_ent);
+    aos_mem_zero(&acl_pool[dev_id], sizeof(acl_pool[dev_id]));
+    return SW_OK;
+}
+
+sw_error_t
+hsl_acl_blk_alloc(a_uint32_t dev_id, a_uint32_t pri, a_uint32_t size,
+                  a_uint32_t info, a_uint32_t * addr)
+{
+    sw_error_t rv;
+    a_uint32_t i;
+    a_uint32_t blk_nr;
+    a_uint32_t p_idx, largest_idx, prev_f_s, largest_f_s;
+    a_uint32_t l_idx, l_nr, l_size, r_idx, r_nr, r_size;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_alloc before alloc");
+
+    if (0 == size)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (size > acl_pool[dev_id].free_rsc)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    blk_nr = acl_pool[dev_id].used_blk;
+
+    p_idx       = 0;
+    prev_f_s    = 0;
+    largest_f_s = 0;
+    largest_idx = 0;
+
+    for (i = 0; i < blk_nr; i++)
+    {
+        if (MEM_FREE == acl_pool[dev_id].blk_ent[i].status)
+        {
+            prev_f_s += acl_pool[dev_id].blk_ent[i].size;
+            continue;
+        }
+
+        p_idx = i;
+        if (pri <= acl_pool[dev_id].blk_ent[i].pri)
+        {
+            break;
+        }
+    }
+
+    if (i == blk_nr)
+    {
+        p_idx = blk_nr;
+    }
+
+    for (i = p_idx; i < blk_nr; i++)
+    {
+        if (MEM_FREE == acl_pool[dev_id].blk_ent[i].status)
+        {
+            if (largest_f_s < acl_pool[dev_id].blk_ent[i].size)
+            {
+                largest_idx = i;
+                largest_f_s = acl_pool[dev_id].blk_ent[i].size;
+            }
+            continue;
+        }
+
+        if (pri != acl_pool[dev_id].blk_ent[i].pri)
+        {
+            break;
+        }
+    }
+
+    if (largest_f_s >= size)
+    {
+        rv = _hsl_acl_blk_alloc(dev_id, largest_idx, pri, size, info,
+                                addr);
+
+    }
+    else if (prev_f_s >= size)
+    {
+        rv = _hsl_acl_blk_left_defrag(dev_id, p_idx, size, A_TRUE, &l_idx,
+                                      &l_nr, &l_size);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _hsl_acl_blk_comb(dev_id, l_idx, l_nr);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _hsl_acl_blk_alloc(dev_id, l_idx, pri, size, info, addr);
+    }
+    else if ((acl_pool[dev_id].free_rsc - prev_f_s) >= size)
+    {
+        rv = _hsl_acl_blk_right_defrag(dev_id, p_idx, size, A_TRUE, &r_idx,
+                                       &r_nr, &r_size);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _hsl_acl_blk_comb(dev_id, r_idx, r_nr);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _hsl_acl_blk_alloc(dev_id, r_idx, pri, size, info, addr);
+    }
+    else
+    {
+        rv = _hsl_acl_blk_left_defrag(dev_id, p_idx, size, A_FALSE, &l_idx,
+                                      &l_nr, &l_size);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _hsl_acl_blk_right_defrag(dev_id, p_idx, size, A_FALSE, &r_idx,
+                                       &r_nr, &r_size);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _hsl_acl_blk_comb(dev_id, l_idx, (l_nr + r_nr));
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _hsl_acl_blk_alloc(dev_id, l_idx, pri, size, info, addr);
+    }
+
+    _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_alloc after alloc");
+    return rv;
+}
+
+sw_error_t
+hsl_acl_blk_free(a_uint32_t dev_id, a_uint32_t addr)
+{
+    sw_error_t rv;
+    a_uint32_t idx;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_free before free");
+
+    rv = _hsl_acl_blk_loc(dev_id, addr, &idx);
+    SW_RTN_ON_ERROR(rv);
+
+    acl_pool[dev_id].blk_ent[idx].status = MEM_FREE;
+    acl_pool[dev_id].blk_ent[idx].pri  = 0;
+    acl_pool[dev_id].blk_ent[idx].info = 0;
+    acl_pool[dev_id].free_rsc += acl_pool[dev_id].blk_ent[idx].size;
+
+    rv = _hsl_acl_rule_invalid(dev_id, addr, acl_pool[dev_id].blk_ent[idx].size);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _hsl_acl_free_blk_comb(dev_id, idx);
+    SW_RTN_ON_ERROR(rv);
+
+    _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_free after free");
+    return SW_OK;
+}
+
+sw_error_t
+hsl_acl_blk_resize(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t new_size)
+{
+    sw_error_t rv;
+    a_uint32_t idx, l_idx, l_nr, l_size, r_idx, r_nr, r_size, old_size;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_resize before resize");
+
+    rv = _hsl_acl_blk_loc(dev_id, addr, &idx);
+    SW_RTN_ON_ERROR(rv);
+
+    if (MEM_USED != acl_pool[dev_id].blk_ent[idx].status)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    old_size = acl_pool[dev_id].blk_ent[idx].size;
+    if (new_size == old_size)
+    {
+        return SW_OK;
+    }
+
+    if (0 == new_size)
+    {
+        rv = hsl_acl_blk_free(dev_id, addr);
+        return rv;
+    }
+
+    /* reduce acl memory block size */
+    if (new_size < old_size)
+    {
+        rv = _hsl_acl_blk_reduce(dev_id, idx, new_size);
+        _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_resize after resize");
+        return rv;
+    }
+
+    /* enlarge acl memory block size */
+    if (acl_pool[dev_id].free_rsc < (new_size - old_size))
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    rv = _hsl_acl_blk_left_defrag(dev_id, idx, new_size - old_size,
+                                  A_FALSE, &l_idx, &l_nr, &l_size);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _hsl_acl_blk_comb(dev_id, l_idx, l_nr);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _hsl_acl_blk_loc(dev_id, addr, &idx);
+    SW_RTN_ON_ERROR(rv);
+
+    if (l_size >= (new_size - old_size))
+    {
+        rv = _hsl_acl_blk_left_enlarge(dev_id, idx, new_size);
+        _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_resize after resize");
+        return rv;
+    }
+
+    if (idx >= (acl_pool[dev_id].used_blk - 1))
+    {
+        return SW_NO_RESOURCE;
+    }
+    rv = _hsl_acl_blk_right_defrag(dev_id, idx + 1, new_size - old_size,
+                                   A_FALSE, &r_idx, &r_nr, &r_size);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _hsl_acl_blk_comb(dev_id, r_idx, r_nr);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _hsl_acl_blk_loc(dev_id, addr, &idx);
+    SW_RTN_ON_ERROR(rv);
+
+    if (r_size >= (new_size - old_size))
+    {
+        rv = _hsl_acl_blk_right_enlarge(dev_id, idx, new_size);
+        _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_resize after resize");
+        return rv;
+    }
+
+    rv = _hsl_acl_blk_right_enlarge(dev_id, idx, old_size + r_size);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _hsl_acl_blk_left_enlarge(dev_id, idx, new_size);
+    _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_resize after resize");
+    return rv;
+}
+
+sw_error_t
+hsl_acl_free_rsc_get(a_uint32_t dev_id, a_uint32_t * free_rsc)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    * free_rsc = acl_pool[dev_id].free_rsc;
+    return SW_OK;
+}
diff --git a/qca-ssdk/src/hsl/hsl_api.c b/qca-ssdk/src/hsl/hsl_api.c
new file mode 100755
index 0000000..aeb3d36
--- /dev/null
+++ b/qca-ssdk/src/hsl/hsl_api.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#include "sw.h"
+#include "hsl_api.h"
+
+static hsl_api_t hsl_api_table[SW_MAX_NR_DEV];
+
+hsl_api_t *
+hsl_api_ptr_get(a_uint32_t dev_id)
+{
+    if (dev_id >= SW_MAX_NR_DEV)
+        return NULL;
+
+    return &(hsl_api_table[dev_id]);
+}
+
+sw_error_t
+hsl_api_init(a_uint32_t dev_id)
+{
+    if (SW_MAX_NR_DEV <= dev_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_set(&hsl_api_table[dev_id], 0, sizeof (hsl_api_t));
+    return SW_OK;
+}
+
diff --git a/qca-ssdk/src/hsl/hsl_dev.c b/qca-ssdk/src/hsl/hsl_dev.c
new file mode 100755
index 0000000..ae9b98a
--- /dev/null
+++ b/qca-ssdk/src/hsl/hsl_dev.c
@@ -0,0 +1,705 @@
+/*
+ * Copyright (c) 2012, 2017-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/*qca808x_start*/
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_lock.h"
+#include "sd.h"
+/*qca808x_end*/
+#if defined ATHENA
+#include "athena_init.h"
+#endif
+#if defined GARUDA
+#include "garuda_init.h"
+#endif
+#if defined SHIVA
+#include "shiva_init.h"
+#endif
+#if defined HORUS
+#include "horus_init.h"
+#endif
+#if defined ISIS
+#include "isis_init.h"
+#endif
+#if defined ISISC
+#include "isisc_init.h"
+#endif
+#if defined DESS
+#include "dess_init.h"
+#endif
+#if defined HPPE
+#include "hppe_init.h"
+#endif
+#if defined SCOMPHY
+/*qca808x_start*/
+#include "scomphy_init.h"
+/*qca808x_end*/
+#endif
+/*qca808x_start*/
+#include "sw_api.h"
+/*qca808x_end*/
+#ifdef KERNEL_MODULE
+/*qca808x_start*/
+#include "sw_api_ks.h"
+/*qca808x_end*/
+#else
+#include "sw_api_us.h"
+#endif
+#include "ssdk_plat.h"
+#ifdef MP
+#include "hsl_phy.h"
+#endif
+/*qca808x_start*/
+static hsl_dev_t dev_table[SW_MAX_NR_DEV];
+static ssdk_init_cfg *dev_ssdk_cfg[SW_MAX_NR_DEV] = { 0 };
+ssdk_chip_type SSDK_CURRENT_CHIP_TYPE = CHIP_UNSPECIFIED;
+
+static sw_error_t hsl_set_current_chip_type(ssdk_chip_type chip_type)
+{
+    sw_error_t rv = SW_OK;
+
+    SSDK_CURRENT_CHIP_TYPE = chip_type;
+
+    if (SSDK_CURRENT_CHIP_TYPE == CHIP_UNSPECIFIED)
+    {
+/*qca808x_end*/
+#if defined ATHENA
+        SSDK_CURRENT_CHIP_TYPE = CHIP_ATHENA;
+#elif defined GARUDA
+        SSDK_CURRENT_CHIP_TYPE = CHIP_GARUDA;
+#elif defined SHIVA
+        SSDK_CURRENT_CHIP_TYPE = CHIP_SHIVA;
+#elif defined HORUS
+        SSDK_CURRENT_CHIP_TYPE = CHIP_HORUS;
+#elif defined ISIS
+        SSDK_CURRENT_CHIP_TYPE = CHIP_ISIS;
+#elif defined ISISC
+        SSDK_CURRENT_CHIP_TYPE = CHIP_ISISC;
+#elif defined DESS
+        SSDK_CURRENT_CHIP_TYPE = CHIP_DESS;
+#elif defined HPPE
+        SSDK_CURRENT_CHIP_TYPE = CHIP_HPPE;
+#elif defined SCOMPHY
+/*qca808x_start*/
+        SSDK_CURRENT_CHIP_TYPE = CHIP_SCOMPHY;
+/*qca808x_end*/
+#else
+        rv = SW_FAIL;
+#endif
+/*qca808x_start*/
+    }
+    return rv;
+}
+
+hsl_dev_t *
+hsl_dev_ptr_get(a_uint32_t dev_id)
+{
+    if (dev_id >= SW_MAX_NR_DEV)
+        return NULL;
+
+    return &dev_table[dev_id];
+}
+/*qca808x_end*/
+hsl_acl_func_t *
+hsl_acl_ptr_get(a_uint32_t dev_id)
+{
+    if (dev_id >= SW_MAX_NR_DEV)
+        return NULL;
+
+    return &(dev_table[dev_id].acl_func);
+}
+
+a_uint32_t hsl_dev_wan_port_get(a_uint32_t dev_id)
+{
+	if(dev_ssdk_cfg[dev_id]) {
+		return dev_ssdk_cfg[dev_id]->port_cfg.wan_bmp;
+	}
+	return 0;
+}
+
+a_uint32_t hsl_dev_inner_ports_get(a_uint32_t dev_id)
+{
+	if(dev_ssdk_cfg[dev_id]) {
+		return dev_ssdk_cfg[dev_id]->port_cfg.inner_bmp;
+	}
+	return 0;
+}
+
+/*qca808x_start*/
+sw_error_t
+hsl_dev_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    sw_error_t rv = SW_OK;
+    static int dev_init = 0;
+
+    if (SW_MAX_NR_DEV <= dev_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_set(&dev_table[dev_id], 0, sizeof (hsl_dev_t));
+
+    if (!dev_init) {
+        SW_RTN_ON_ERROR(sd_init(dev_id,cfg));
+
+#ifdef UK_IF
+        SW_RTN_ON_ERROR(sw_uk_init(cfg->nl_prot));
+#endif
+
+#if defined API_LOCK
+        SW_RTN_ON_ERROR(hsl_api_lock_init());
+#endif
+        dev_init = 1;
+    }
+    rv = hsl_set_current_chip_type(cfg->chip_type);
+    SW_RTN_ON_ERROR(rv);
+
+    if (NULL == dev_ssdk_cfg[dev_id])
+    {
+        dev_ssdk_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg));
+    }
+
+    if (NULL == dev_ssdk_cfg[dev_id])
+    {
+        return SW_OUT_OF_MEM;
+    }
+
+    aos_mem_copy(dev_ssdk_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+#if defined UK_MINOR_DEV
+    dev_ssdk_cfg[dev_id]->nl_prot = UK_MINOR_DEV;
+#endif
+
+    rv = SW_INIT_ERROR;
+    switch (cfg->chip_type)
+    {
+/*qca808x_end*/
+        case CHIP_ATHENA:
+#if defined ATHENA
+            rv = athena_init(dev_id, cfg);
+#endif
+            break;
+
+        case CHIP_GARUDA:
+#if defined GARUDA
+            rv = garuda_init(dev_id, cfg);
+#endif
+            break;
+
+        case CHIP_SHIVA:
+#if defined SHIVA
+            rv = shiva_init(dev_id, cfg);
+#endif
+            break;
+
+        case CHIP_HORUS:
+#if defined HORUS
+            rv = horus_init(dev_id, cfg);
+#endif
+            break;
+
+        case CHIP_ISIS:
+#if defined ISIS
+            rv = isis_init(dev_id, cfg);
+#endif
+            break;
+        case CHIP_ISISC:
+#if defined ISISC
+            rv = isisc_init(dev_id, cfg);
+#endif
+            break;
+        case CHIP_DESS:
+#if defined DESS
+            rv = dess_init(dev_id, cfg);
+#endif
+            break;
+        case CHIP_HPPE:
+#if defined HPPE
+            rv = hppe_init(dev_id, cfg);
+#endif
+            break;
+/*qca808x_start*/
+	case CHIP_SCOMPHY:
+/*qca808x_end*/
+#if defined SCOMPHY
+/*qca808x_start*/
+	    rv = scomphy_init(dev_id, cfg);
+/*qca808x_end*/
+#endif
+/*qca808x_start*/
+	    break;
+/*qca808x_end*/
+        case CHIP_UNSPECIFIED:
+#if defined ATHENA
+            rv = athena_init(dev_id, cfg);
+#elif defined GARUDA
+            rv = garuda_init(dev_id, cfg);
+#elif defined SHIVA
+            rv = shiva_init(dev_id, cfg);
+#elif defined HORUS
+            rv = horus_init(dev_id, cfg);
+#elif defined ISIS
+            rv = isis_init(dev_id, cfg);
+#elif defined ISISC
+            rv = isisc_init(dev_id, cfg);
+#endif
+            break;
+/*qca808x_start*/
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+/*qca808x_end*/
+sw_error_t
+hsl_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg)
+{
+    if(!dev_ssdk_cfg[dev_id])
+    {
+        SSDK_ERROR("the dev%d wasn't initialized\n", dev_id);
+        return SW_BAD_VALUE;
+    }
+    aos_mem_set(&(ssdk_cfg->init_cfg), 0,  sizeof(ssdk_init_cfg));
+
+    aos_mem_copy(&(ssdk_cfg->init_cfg), dev_ssdk_cfg[dev_id], sizeof(ssdk_init_cfg));
+
+#ifdef VERSION
+    aos_mem_copy(ssdk_cfg->build_ver, VERSION, sizeof(VERSION));
+#endif
+
+#ifdef BUILD_DATE
+    aos_mem_copy(ssdk_cfg->build_date, BUILD_DATE, sizeof(BUILD_DATE));
+#endif
+
+    switch (dev_ssdk_cfg[dev_id]->chip_type)
+    {
+        case CHIP_ATHENA:
+            aos_mem_copy(ssdk_cfg->chip_type, "athena", sizeof("athena"));
+            break;
+
+        case CHIP_GARUDA:
+            aos_mem_copy(ssdk_cfg->chip_type, "garuda", sizeof("garuda"));
+            break;
+
+        case CHIP_SHIVA:
+            aos_mem_copy(ssdk_cfg->chip_type, "shiva", sizeof("shiva"));
+            break;
+
+        case CHIP_HORUS:
+            aos_mem_copy(ssdk_cfg->chip_type, "horus", sizeof("horus"));
+            break;
+
+        case CHIP_ISIS:
+            aos_mem_copy(ssdk_cfg->chip_type, "isis", sizeof("isis"));
+            break;
+
+        case CHIP_ISISC:
+            aos_mem_copy(ssdk_cfg->chip_type, "isisc", sizeof("isisc"));
+            break;
+
+        case CHIP_DESS:
+            aos_mem_copy(ssdk_cfg->chip_type, "dess", sizeof("dess"));
+            break;
+
+        case CHIP_HPPE:
+            aos_mem_copy(ssdk_cfg->chip_type, "hppe", sizeof("hppe"));
+            break;
+
+        case CHIP_SCOMPHY:
+#ifdef MP
+            if(dev_ssdk_cfg[dev_id]->chip_revision == MP_GEPHY)
+            {
+                aos_mem_copy(ssdk_cfg->chip_type, "mp", sizeof("mp"));
+            }
+#endif
+            break;
+
+        case CHIP_UNSPECIFIED:
+#if defined ATHENA
+            aos_mem_copy(ssdk_cfg->chip_type, "athena", sizeof("athena"));
+#elif defined GARUDA
+            aos_mem_copy(ssdk_cfg->chip_type, "garuda", sizeof("garuda"));
+#elif defined SHIVA
+            aos_mem_copy(ssdk_cfg->chip_type, "shiva", sizeof("shiva"));
+#elif defined HORUS
+            aos_mem_copy(ssdk_cfg->chip_type, "horus", sizeof("horus"));
+#elif defined ISIS
+            aos_mem_copy(ssdk_cfg->chip_type, "isis", sizeof("isis"));
+#elif defined ISISC
+            aos_mem_copy(ssdk_cfg->chip_type, "isisc", sizeof("isisc"));
+#endif
+            break;
+
+        default:
+            return SW_BAD_PARAM;
+    }
+
+#ifdef CPU
+    aos_mem_copy(ssdk_cfg->cpu_type, CPU, sizeof(CPU));
+#endif
+
+#ifdef OS
+    aos_mem_copy(ssdk_cfg->os_info, OS, sizeof(OS));
+#if defined KVER26
+    aos_mem_copy(ssdk_cfg->os_info+sizeof(OS)-1, " version 2.6", sizeof(" version 2.6"));
+#elif defined KVER24
+    aos_mem_copy(ssdk_cfg->os_info+sizeof(OS)-1, " version 2.4", sizeof(" version 2.4"));
+#else
+    aos_mem_copy(ssdk_cfg->os_info+sizeof(OS)-1, " unknown", sizeof(" unknown"));
+#endif
+#endif
+
+#ifdef HSL_STANDALONG
+    ssdk_cfg->fal_mod = A_FALSE;
+#else
+    ssdk_cfg->fal_mod = A_TRUE;
+#endif
+
+#ifdef USER_MODE
+    ssdk_cfg->kernel_mode = A_FALSE;
+#else
+    ssdk_cfg->kernel_mode = A_TRUE;
+#endif
+
+#ifdef UK_IF
+    ssdk_cfg->uk_if = A_TRUE;
+#else
+    ssdk_cfg->uk_if = A_FALSE;
+#endif
+
+#ifdef IN_ACL
+    ssdk_cfg->features.in_acl = A_TRUE;
+#endif
+#ifdef IN_FDB
+    ssdk_cfg->features.in_fdb = A_TRUE;
+#endif
+#ifdef IN_IGMP
+    ssdk_cfg->features.in_igmp = A_TRUE;
+#endif
+#ifdef IN_LEAKY
+    ssdk_cfg->features.in_leaky = A_TRUE;
+#endif
+#ifdef IN_LED
+    ssdk_cfg->features.in_led = A_TRUE;
+#endif
+#ifdef IN_MIB
+    ssdk_cfg->features.in_mib = A_TRUE;
+#endif
+#ifdef IN_MIRROR
+    ssdk_cfg->features.in_mirror = A_TRUE;
+#endif
+#ifdef IN_MISC
+    ssdk_cfg->features.in_misc = A_TRUE;
+#endif
+#ifdef IN_PORTCONTROL
+    ssdk_cfg->features.in_portcontrol = A_TRUE;
+#endif
+#ifdef IN_PORTVLAN
+    ssdk_cfg->features.in_portvlan = A_TRUE;
+#endif
+#ifdef IN_QOS
+    ssdk_cfg->features.in_qos = A_TRUE;
+#endif
+#ifdef IN_RATE
+    ssdk_cfg->features.in_rate = A_TRUE;
+#endif
+#ifdef IN_STP
+    ssdk_cfg->features.in_stp = A_TRUE;
+#endif
+#ifdef IN_VLAN
+    ssdk_cfg->features.in_vlan = A_TRUE;
+#endif
+#ifdef IN_REDUCED_ACL
+    ssdk_cfg->features.in_reduced_acl = A_TRUE;
+#endif
+#ifdef IN_IP
+    ssdk_cfg->features.in_ip = A_TRUE;
+#endif
+#ifdef IN_NAT
+    ssdk_cfg->features.in_nat = A_TRUE;
+#endif
+#ifdef IN_COSMAP
+    ssdk_cfg->features.in_cosmap = A_TRUE;
+#endif
+#ifdef IN_SEC
+    ssdk_cfg->features.in_sec = A_TRUE;
+#endif
+#ifdef IN_TRUNK
+    ssdk_cfg->features.in_trunk = A_TRUE;
+#endif
+#ifdef IN_NAT_HELPER
+    ssdk_cfg->features.in_nathelper= A_TRUE;
+#endif
+#ifdef IN_INTERFACECONTROL
+    ssdk_cfg->features.in_interfacectrl= A_TRUE;
+#endif
+
+    return SW_OK;
+}
+/*qca808x_start*/
+sw_error_t
+hsl_dev_cleanup(void)
+{
+    sw_error_t rv = SW_OK;
+    a_uint32_t dev_id;
+
+    for (dev_id = 0; dev_id < SW_MAX_NR_DEV; dev_id++)
+    {
+        if (dev_ssdk_cfg[dev_id])
+        {
+            hsl_api_t *p_api;
+
+            SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+            if (p_api->dev_clean)
+            {
+                rv = p_api->dev_clean(dev_id);
+                SW_RTN_ON_ERROR(rv);
+            }
+
+            aos_mem_free(dev_ssdk_cfg[dev_id]);
+            dev_ssdk_cfg[dev_id] = NULL;
+        }
+    }
+
+#ifdef UK_IF
+    SW_RTN_ON_ERROR(sw_uk_cleanup());
+#endif
+
+    return SW_OK;
+}
+/*qca808x_end*/
+sw_error_t
+hsl_access_mode_set(a_uint32_t dev_id, hsl_access_mode reg_mode)
+{
+    sw_error_t rv;
+    hsl_api_t *p_api;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+    if (p_api->dev_access_set)
+    {
+        rv = p_api->dev_access_set(dev_id, reg_mode);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+sw_error_t reduce_hsl_reg_entry_get(a_uint32_t dev,a_uint32_t reg,a_uint8_t* value,a_uint8_t val_len)
+{
+	sw_error_t rv;
+
+	hsl_api_t *p_api = hsl_api_ptr_get(dev);
+	if (p_api) {
+		rv = p_api->reg_get(dev, reg, (a_uint8_t*)value, (a_uint8_t)val_len);
+	} else {
+		rv = SW_NOT_INITIALIZED;
+	}
+
+	return rv;
+}
+
+sw_error_t reduce_hsl_reg_entry_set(a_uint32_t dev,a_uint32_t reg,a_uint8_t* value,a_uint8_t val_len)
+{
+	sw_error_t rv;
+
+	hsl_api_t *p_api = hsl_api_ptr_get(dev);
+	if (p_api) {
+	    rv = p_api->reg_set (dev, reg,
+	                               (a_uint8_t*)value, (a_uint8_t)val_len);
+	} else {
+	    rv = SW_NOT_INITIALIZED;
+	}
+
+	return rv;
+
+}
+
+sw_error_t reduce_hsl_reg_field_get(a_uint32_t dev,a_uint32_t reg,a_uint32_t reg_offset,
+						a_uint32_t reg_offset_len,a_uint8_t* value,a_uint8_t val_len)
+{
+	sw_error_t rv;
+
+	hsl_api_t *p_api = hsl_api_ptr_get(dev);
+	if (p_api) {
+		rv = p_api->reg_field_get(dev, reg, reg_offset, reg_offset_len, (a_uint8_t*)value, val_len);
+	} else {
+		rv = SW_NOT_INITIALIZED;
+	}
+	return rv;
+}
+
+sw_error_t reduce_hsl_reg_field_set(a_uint32_t dev,a_uint32_t reg,a_uint32_t reg_offset,
+						a_uint32_t reg_offset_len,a_uint8_t* value,a_uint8_t val_len)
+{
+	sw_error_t rv;
+
+	hsl_api_t *p_api = hsl_api_ptr_get(dev);
+	if (p_api) {
+		rv = p_api->reg_field_set(dev, reg,
+								  reg_offset,
+								  reg_offset_len, (a_uint8_t*)value, val_len);
+	} else {
+		rv = SW_NOT_INITIALIZED;
+	}
+	return rv;
+}
+
+sw_error_t reduce_hsl_reg_entry_gen_get(a_uint32_t dev,a_uint32_t addr,a_uint8_t* value,a_uint8_t val_len)
+{
+	sw_error_t rv;
+
+	hsl_api_t *p_api = hsl_api_ptr_get(dev);
+	if (p_api) {
+		rv = p_api->reg_get(dev, addr, (a_uint8_t*)value, val_len);
+	} else {
+		rv = SW_NOT_INITIALIZED;
+	}
+
+	return rv;
+}
+
+
+sw_error_t reduce_hsl_reg_entry_gen_set(a_uint32_t dev,a_uint32_t addr,a_uint8_t* value,a_uint8_t val_len)
+{
+	sw_error_t rv;
+
+	hsl_api_t *p_api = hsl_api_ptr_get(dev);
+	if (p_api) {
+		rv = p_api->reg_set(dev, addr, (a_uint8_t*)value, val_len);
+	} else {
+		rv = SW_NOT_INITIALIZED;
+	}
+
+	return rv;
+}
+
+sw_error_t reduce_hsl_reg_field_gen_get(a_uint32_t dev,a_uint32_t reg_addr,a_uint32_t bitoffset,
+						a_uint32_t field_len,a_uint8_t* value,a_uint8_t val_len)
+{
+	sw_error_t rv;
+
+	hsl_api_t *p_api = hsl_api_ptr_get(dev);
+	if (p_api) {
+		rv = p_api->reg_field_get(dev, reg_addr,
+								  bitoffset,
+								  field_len, (a_uint8_t*)value, val_len);
+	} else {
+		rv = SW_NOT_INITIALIZED;
+	}
+	return rv;
+}
+
+
+sw_error_t reduce_hsl_reg_field_gen_set(a_uint32_t dev,a_uint32_t regaddr,a_uint32_t bitoffset,
+						a_uint32_t bitlength,a_uint8_t* value,a_uint8_t val_len)
+{
+	sw_error_t rv;
+
+	hsl_api_t *p_api = hsl_api_ptr_get(dev);
+	if (p_api) {
+		rv = p_api->reg_field_set(dev, regaddr,
+								  bitoffset,
+								  bitlength, (a_uint8_t*)value, val_len);
+	} else {
+		rv = SW_NOT_INITIALIZED;
+	}
+	return rv;
+}
+
+/*qca808x_start*/
+sw_error_t reduce_hsl_phy_set(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t value)
+{
+	sw_error_t rv;
+
+	hsl_api_t *p_api = hsl_api_ptr_get(dev); 
+	if (p_api) { 
+	    rv = p_api->phy_set(dev, phy_addr, reg, value); 
+	} else { 
+	    rv = SW_NOT_INITIALIZED; 
+	} 
+
+	return rv;
+}
+
+sw_error_t reduce_hsl_phy_get(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t* value)
+{
+	sw_error_t rv;
+
+	hsl_api_t *p_api = hsl_api_ptr_get(dev);
+	if (p_api) {
+	    rv = p_api->phy_get(dev, phy_addr, reg, value);
+	} else {
+	    rv = SW_NOT_INITIALIZED;
+	}
+
+	return rv;
+}
+
+sw_error_t hsl_phy_i2c_set(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t value)
+{
+	sw_error_t rv;
+
+	hsl_api_t *p_api = hsl_api_ptr_get(dev);
+	if (p_api) {
+	    rv = p_api->phy_i2c_set(dev, phy_addr, reg, value);
+	} else {
+	    rv = SW_NOT_INITIALIZED;
+	}
+
+	return rv;
+}
+
+sw_error_t hsl_phy_i2c_get(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t* value)
+{
+	sw_error_t rv;
+
+	hsl_api_t *p_api = hsl_api_ptr_get(dev);
+	if (p_api) {
+	    rv = p_api->phy_i2c_get(dev, phy_addr, reg, value);
+	} else {
+	    rv = SW_NOT_INITIALIZED;
+	}
+
+	return rv;
+}
+
+#if 0
+void reduce_sw_set_reg_by_field_u32(unsigned int reg_value,unsigned int field_value,
+													unsigned int reg_offset,unsigned int reg_len)
+{
+    do {
+        (reg_value) = (((reg_value) & SW_FIELD_MASK_NOT_U32((reg_offset),(reg_offset)))
+              | (((field_value) & SW_BIT_MASK_U32(reg_len)) << (reg_offset)));
+    } while (0);
+
+}
+
+
+void reduce_sw_field_get_by_reg_u32(unsigned int reg_value,unsigned int field_value,
+													unsigned int reg_offset,unsigned int reg_len)
+{
+    do {
+        (field_value) = (((reg_value) >> (reg_offset)) & SW_BIT_MASK_U32(reg_len));
+    } while (0);
+
+}
+#endif
+/*qca808x_end*/
+
diff --git a/qca-ssdk/src/hsl/hsl_lock.c b/qca-ssdk/src/hsl/hsl_lock.c
new file mode 100755
index 0000000..e9d4540
--- /dev/null
+++ b/qca-ssdk/src/hsl/hsl_lock.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#include "sw.h"
+
+#ifdef KVER32
+aos_lock_t sw_hsl_api_lock;
+#else
+aos_lock_t sw_hsl_api_lock = aos_default_unlock;
+#endif
+
+sw_error_t
+hsl_api_lock_init(void)
+{
+    aos_lock_init(&sw_hsl_api_lock);
+    return SW_OK;
+}
diff --git a/qca-ssdk/src/hsl/hsl_port_prop.c b/qca-ssdk/src/hsl/hsl_port_prop.c
new file mode 100755
index 0000000..b450fe4
--- /dev/null
+++ b/qca-ssdk/src/hsl/hsl_port_prop.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#include "sw_config.h"
+#include "aos_head.h"
+#include "sw_error.h"
+#include "shared_func.h"
+#include "fal_type.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "hsl_phy.h"
+
+
+typedef struct
+{
+    a_uint32_t phy_id[SW_MAX_NR_PORT];
+    fal_pbmp_t dev_portmap;
+    fal_pbmp_t property[HSL_PP_BUTT];
+} port_info_t;
+
+static port_info_t *p_port_info[SW_MAX_NR_DEV] = { 0 };
+
+a_bool_t
+hsl_port_prop_check(a_uint32_t dev_id, fal_port_t port_id,
+                    hsl_port_prop_t p_type)
+{
+    fal_pbmp_t pbitmap;
+
+    if (dev_id >= SW_MAX_NR_DEV)
+        return A_FALSE;
+
+    if (HSL_PP_BUTT <= p_type)
+    {
+        return A_FALSE;
+    }
+
+    pbitmap = p_port_info[dev_id]->property[p_type];
+
+    return SW_IS_PBMP_MEMBER(pbitmap, port_id);
+}
+
+a_bool_t
+hsl_mports_prop_check(a_uint32_t dev_id, fal_pbmp_t port_bitmap,
+                      hsl_port_prop_t p_type)
+{
+    fal_pbmp_t pbitmap;
+
+    if (dev_id >= SW_MAX_NR_DEV)
+        return A_FALSE;
+
+    if (HSL_PP_BUTT <= p_type)
+    {
+        return A_FALSE;
+    }
+
+    pbitmap = p_port_info[dev_id]->property[p_type];
+
+    return (SW_IS_PBMP_INCLUDE(pbitmap, port_bitmap));
+}
+
+a_bool_t
+hsl_port_validity_check(a_uint32_t dev_id, fal_port_t port_id)
+{
+    fal_pbmp_t pbitmap;
+
+    if (dev_id >= SW_MAX_NR_DEV)
+        return A_FALSE;
+
+    pbitmap = p_port_info[dev_id]->dev_portmap;
+
+    return SW_IS_PBMP_MEMBER(pbitmap, port_id);
+}
+
+a_bool_t
+hsl_mports_validity_check(a_uint32_t dev_id, fal_pbmp_t port_bitmap)
+{
+    fal_pbmp_t pbitmap;
+
+    if (dev_id >= SW_MAX_NR_DEV)
+        return A_FALSE;
+
+    pbitmap = p_port_info[dev_id]->dev_portmap;
+
+    return (SW_IS_PBMP_INCLUDE(pbitmap, port_bitmap));
+}
+
+sw_error_t
+hsl_port_prop_set(a_uint32_t dev_id, fal_port_t port_id, hsl_port_prop_t p_type)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_validity_check(dev_id, port_id))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    if (HSL_PP_BUTT <= p_type)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_PBMP_ADD_PORT(p_port_info[dev_id]->property[p_type], port_id);
+
+    return SW_OK;
+}
+
+sw_error_t
+hsl_port_prop_clr(a_uint32_t dev_id, fal_port_t port_id, hsl_port_prop_t p_type)
+{
+    HSL_DEV_ID_CHECK(dev_id);;
+
+    if (A_FALSE == hsl_port_validity_check(dev_id, port_id))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    if (HSL_PP_BUTT <= p_type)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_PBMP_DEL_PORT(p_port_info[dev_id]->property[p_type], port_id);
+
+    return SW_OK;
+}
+
+sw_error_t
+hsl_port_prop_get_phyid(a_uint32_t dev_id, fal_port_t port_id,
+                        a_uint32_t * phy_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+	HSL_PORT_ID_CHECK(port_id);
+
+    if (A_FALSE == hsl_port_validity_check(dev_id, port_id))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    *phy_id = qca_ssdk_port_to_phy_addr(dev_id, port_id);
+
+    return SW_OK;
+}
+
+sw_error_t
+hsl_port_prop_set_phyid(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t phy_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+	HSL_PORT_ID_CHECK(port_id);
+
+    if (A_FALSE == hsl_port_validity_check(dev_id, port_id))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    p_port_info[dev_id]->phy_id[port_id] = phy_id;
+    return SW_OK;
+}
+
+sw_error_t
+hsl_port_prop_portmap_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (port_id > SW_MAX_NR_PORT)
+        return SW_OUT_OF_RANGE;
+
+    SW_PBMP_ADD_PORT(p_port_info[dev_id]->dev_portmap, port_id);
+
+    return SW_OK;
+}
+
+sw_error_t
+hsl_port_prop_init_by_dev(a_uint32_t dev_id)
+{
+    port_info_t *p_mem;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    p_mem = aos_mem_alloc(sizeof (port_info_t));
+    if (p_mem == NULL)
+        return SW_OUT_OF_MEM;
+
+    aos_mem_zero(p_mem, sizeof (port_info_t));
+    p_port_info[dev_id] = p_mem;
+
+    return SW_OK;
+}
+
+sw_error_t
+hsl_port_prop_cleanup_by_dev(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (p_port_info[dev_id] != NULL)
+        aos_mem_free((void *)p_port_info[dev_id]);
+
+    p_port_info[dev_id] = NULL;
+
+    return SW_OK;
+}
+
+
+sw_error_t
+hsl_port_prop_init(a_uint32_t dev_id)
+{
+    if (dev_id >= SW_MAX_NR_DEV)
+    	return SW_BAD_VALUE;
+
+    p_port_info[dev_id] = NULL;
+
+    return SW_OK;
+}
diff --git a/qca-ssdk/src/hsl/isis/Makefile b/qca-ssdk/src/hsl/isis/Makefile
new file mode 100755
index 0000000..2fa5d4b
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/Makefile
@@ -0,0 +1,124 @@
+LOC_DIR=src/hsl/isis
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=isis_reg_access.c isis_init.c
+
+ifeq (TRUE, $(IN_ACL))
+  SRC_LIST += isis_acl.c isis_acl_parse.c isis_multicast_acl.c
+endif
+
+ifeq (TRUE, $(IN_FDB))
+  SRC_LIST += isis_fdb.c
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+  SRC_LIST += isis_igmp.c
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+  SRC_LIST += isis_leaky.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+  SRC_LIST += isis_led.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+  SRC_LIST += isis_mib.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+  SRC_LIST += isis_mirror.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+  SRC_LIST += isis_misc.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+  SRC_LIST += isis_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+  SRC_LIST += isis_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+  SRC_LIST += isis_qos.c
+endif
+
+ifeq (TRUE, $(IN_RATE))
+  SRC_LIST += isis_rate.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+  SRC_LIST += isis_stp.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+  SRC_LIST += isis_vlan.c
+endif
+
+ifeq (TRUE, $(IN_REDUCED_ACL))
+  SRC_LIST += isis_reduced_acl.c
+endif
+
+ifeq (TRUE, $(IN_COSMAP))
+  SRC_LIST += isis_cosmap.c
+endif
+
+ifeq (TRUE, $(IN_IP))
+  SRC_LIST += isis_ip.c
+endif
+
+ifeq (TRUE, $(IN_NAT))
+  SRC_LIST += isis_nat.c
+endif
+
+ifeq (TRUE, $(IN_NAT_HELPER))
+  SRC_LIST += nat_helper_dt.c
+  SRC_LIST += nat_helper_hsl.c
+  SRC_LIST += nat_ipt_helper.c
+  SRC_LIST += napt_helper.c
+  SRC_LIST += host_helper.c
+  SRC_LIST += nat_helper.c
+  SRC_LIST += napt_acl.c
+  SRC_LIST += napt_procfs.c
+endif
+
+ifeq (TRUE, $(IN_TRUNK))
+  SRC_LIST += isis_trunk.c
+endif
+
+ifeq (TRUE, $(IN_SEC))
+  SRC_LIST += isis_sec.c
+endif
+
+ifeq (TRUE, $(IN_INTERFACECONTROL))
+  SRC_LIST += isis_interface_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_MACBLOCK))
+  SRC_LIST += isis_mac_block.c
+endif
+
+
+ifeq (linux, $(OS))
+	ifeq (KSLIB, $(MODULE_TYPE))
+    ifneq (TRUE, $(KERNEL_MODE))
+      SRC_LIST=isis_reg_access.c isis_init.c
+	  endif
+	endif
+endif
+
+ifeq (, $(filter ISIS, $(SUPPORT_CHIP)))
+  SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/hsl/isis/isis_acl.c b/qca-ssdk/src/hsl/isis/isis_acl.c
new file mode 100755
index 0000000..edca76a
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_acl.c
@@ -0,0 +1,1904 @@
+/*
+ * Copyright (c) 2012, 2016, 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_acl ISIS_ACL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+#include "isis_acl.h"
+#include "isis_reg.h"
+#include "isis_acl_prv.h"
+
+//#define ISIS_ACL_DEBUG
+//#define ISIS_SW_ENTRY
+#define ISIS_HW_ENTRY
+
+static isis_acl_list_t *sw_list_ent[SW_MAX_NR_DEV];
+static isis_acl_rule_t *sw_rule_ent[SW_MAX_NR_DEV];
+
+static isis_acl_rule_t *sw_rule_tmp[SW_MAX_NR_DEV];
+static isis_acl_rule_t *hw_rule_tmp[SW_MAX_NR_DEV];
+#ifdef ISIS_SW_ENTRY
+static a_uint8_t *sw_filter_mem = NULL;
+#endif
+
+static sw_error_t
+_isis_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag);
+
+static sw_error_t
+_isis_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx,
+                        a_uint32_t ports);
+
+#ifdef ISIS_SW_ENTRY
+static sw_error_t
+_isis_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+                   a_uint32_t op);
+
+static sw_error_t
+_isis_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+                  a_uint32_t op);
+#endif
+
+static sw_error_t
+_isis_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter,
+                        a_uint32_t flt_idx);
+
+static sw_error_t
+_isis_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter,
+                      a_uint32_t flt_idx);
+
+static void
+_isis_acl_list_dump(a_uint32_t dev_id)
+{
+    a_uint32_t i;
+    isis_acl_list_t *sw_list;
+
+    aos_printk("\ndev_id=%d  list control infomation:", dev_id);
+    for (i = 0; i < ISIS_MAX_FILTER; i++)
+    {
+        sw_list = &(sw_list_ent[dev_id][i]);
+        if (ENT_USED & sw_list->status)
+        {
+            aos_printk
+            ("\nlist_id=%02d  list_pri=%02d  rule_nr=%02d  [pts_map]:0x%02x  idx=%02d ",
+             sw_list->list_id, sw_list->list_pri, sw_list->rule_nr,
+             sw_list->bind_pts, i);
+        }
+    }
+    aos_printk("\n");
+}
+
+static void
+_isis_acl_sw_rule_dump(char *info, isis_acl_rule_t * sw_rule)
+{
+#ifdef ISIS_ACL_DEBUG
+    a_uint32_t flt_idx, i;
+
+    aos_printk("\n%s", info);
+    for (flt_idx = 0; flt_idx < ISIS_MAX_FILTER; flt_idx++)
+    {
+        aos_printk("\n%d software filter:", flt_idx);
+        aos_printk("\nact:");
+        for (i = 0; i < 3; i++)
+        {
+            aos_printk("%08x  ", sw_rule[flt_idx].filter.act[i]);
+        }
+
+        aos_printk("\nvlu:");
+        for (i = 0; i < 5; i++)
+        {
+            aos_printk("%08x  ", sw_rule[flt_idx].filter.vlu[i]);
+        }
+
+        aos_printk("\nmsk:");
+        for (i = 0; i < 5; i++)
+        {
+            aos_printk("%08x  ", sw_rule[flt_idx].filter.msk[i]);
+        }
+
+        aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d]",
+                   sw_rule[flt_idx].status,
+                   sw_rule[flt_idx].list_id, sw_rule[flt_idx].rule_id);
+
+        aos_printk("\n\n");
+    }
+#else
+    return;
+#endif
+}
+
+static isis_acl_list_t *
+_isis_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < ISIS_MAX_FILTER; i++)
+    {
+        if ((ENT_USED & sw_list_ent[dev_id][i].status)
+                && (list_id == sw_list_ent[dev_id][i].list_id))
+        {
+            return &(sw_list_ent[dev_id][i]);
+        }
+    }
+    return NULL;
+}
+
+static sw_error_t
+_isis_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag)
+{
+#ifdef ISIS_SW_ENTRY
+    hw_filter_t filter;
+
+    _isis_filter_up_to_sw(dev_id, &filter, flt_idx);
+
+    filter.msk[4] &= 0xfffffff8;
+    filter.msk[4] |= (flag & 0x7);
+
+    _isis_filter_down_to_hw(dev_id, &filter, flt_idx);
+
+    return SW_OK;
+#else
+#ifdef ISIS_HW_ENTRY
+    hw_filter_t filter;
+
+    filter = sw_rule_ent[dev_id][flt_idx].filter;
+
+    filter.msk[4] &= 0xfffffff8;
+    filter.msk[4] |= (flag & 0x7);
+
+    _isis_filter_down_to_hw(dev_id, &filter, flt_idx);
+    return SW_OK;
+#else
+    sw_error_t rv;
+    a_uint32_t addr, data = 0;
+
+    /* read filter mask at first */
+    addr = ISIS_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 10) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* get filter mask and modify it */
+    addr = ISIS_RULE_FUNC_ADDR + 20;
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= 0xfffffff8;
+    data |= (flag & 0x7);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* write back filter mask */
+    addr = ISIS_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+#endif
+#endif
+}
+
+static sw_error_t
+_isis_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t ports)
+{
+#ifdef ISIS_SW_ENTRY
+    hw_filter_t filter;
+
+    _isis_filter_up_to_sw(dev_id, &filter, flt_idx);
+
+    filter.vlu[4] &= 0xffffff80;
+    filter.vlu[4] |= (ports & 0x7f);
+
+    _isis_filter_down_to_hw(dev_id, &filter, flt_idx);
+
+    return SW_OK;
+#else
+#ifdef ISIS_HW_ENTRY
+    hw_filter_t filter;
+
+    filter = sw_rule_ent[dev_id][flt_idx].filter;
+
+    filter.vlu[4] &= 0xffffff80;
+    filter.vlu[4] |= (ports & 0x7f);
+
+    _isis_filter_down_to_hw(dev_id, &filter, flt_idx);
+
+    return SW_OK;
+#else
+    sw_error_t rv;
+    a_uint32_t addr, data;
+
+    /* read filter value at first */
+    addr = ISIS_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (0x1 << 10) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* get filter value and modify it */
+    addr = ISIS_RULE_FUNC_ADDR + 20;
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= 0xffffff80;
+    data |= (ports & 0x7f);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* write back filter value */
+    addr = ISIS_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+#endif
+#endif
+}
+
+#ifdef ISIS_SW_ENTRY
+static sw_error_t
+_isis_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+                   a_uint32_t op)
+{
+    a_uint32_t i, addr, data, idx = 6;
+    sw_error_t rv;
+
+    if (ISIS_FILTER_ACT_OP == op)
+    {
+        idx = 4;
+    }
+
+    for (i = 1; i < idx; i++)
+    {
+        addr = ISIS_RULE_FUNC_ADDR + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(reg[i - 1])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    addr = ISIS_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isis_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+                  a_uint32_t op)
+{
+    a_uint32_t i, addr, data, idx = 6;
+    sw_error_t rv;
+
+    addr = ISIS_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 10) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (ISIS_FILTER_ACT_OP == op)
+    {
+        idx = 4;
+    }
+
+    for (i = 1; i < idx; i++)
+    {
+        addr = ISIS_RULE_FUNC_ADDR + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(reg[i - 1])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isis_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter,
+                        a_uint32_t flt_idx)
+{
+#ifdef ISIS_SW_ENTRY
+    a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx;
+
+    aos_mem_copy(tbl, filter, sizeof (hw_filter_t));
+#else
+#ifdef ISIS_HW_ENTRY
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    base = ISIS_FILTER_ACT_ADDR + (flt_idx << 4);
+    for (i = 0; i < 3; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->act[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    base = ISIS_FILTER_VLU_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->vlu[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    base = ISIS_FILTER_MSK_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->msk[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+#else
+    sw_error_t rv;
+
+    rv = _isis_filter_write(dev_id, &(filter->act[0]), flt_idx,
+                            ISIS_FILTER_ACT_OP);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_filter_write(dev_id, &(filter->vlu[0]), flt_idx,
+                            ISIS_FILTER_VLU_OP);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_filter_write(dev_id, &(filter->msk[0]), flt_idx,
+                            ISIS_FILTER_MSK_OP);
+    SW_RTN_ON_ERROR(rv);
+#endif
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter,
+                      a_uint32_t flt_idx)
+{
+#ifdef ISIS_SW_ENTRY
+    a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx;
+
+    aos_mem_copy(filter, tbl, sizeof (hw_filter_t));
+#else
+#ifdef ISIS_HW_ENTRY
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    base = ISIS_FILTER_VLU_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->vlu[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    base = ISIS_FILTER_MSK_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->msk[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    base = ISIS_FILTER_ACT_ADDR + (flt_idx << 4);
+    for (i = 0; i < 3; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->act[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+#else
+    sw_error_t rv;
+
+    rv = _isis_filter_read(dev_id, &(filter->vlu[0]), flt_idx,
+                           ISIS_FILTER_VLU_OP);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_filter_read(dev_id, &(filter->msk[0]), flt_idx,
+                           ISIS_FILTER_MSK_OP);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_filter_read(dev_id, &(filter->act[0]), flt_idx,
+                           ISIS_FILTER_ACT_OP);
+    SW_RTN_ON_ERROR(rv);
+#endif
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_list_insert(a_uint32_t dev_id, a_uint32_t * src_idx,
+                      a_uint32_t * dst_idx, isis_acl_rule_t * src_rule,
+                      isis_acl_rule_t * dst_rule)
+{
+    a_uint32_t i, data, rule_id, list_id, list_pri;
+
+    rule_id = 0;
+    list_id = src_rule[*src_idx].list_id;
+    list_pri = src_rule[*src_idx].list_pri;
+
+    for (i = *src_idx; i < ISIS_MAX_FILTER; i++)
+    {
+        if (!(ENT_USED & src_rule[i].status))
+        {
+            continue; // was: break;
+        }
+
+        if (src_rule[i].list_id != list_id)
+        {
+            break;
+        }
+
+        SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data,
+                            src_rule[i].filter.msk[4]);
+        if (!data)
+        {
+            continue;
+        }
+
+        if (ISIS_MAX_FILTER <= *dst_idx)
+        {
+            return SW_NO_RESOURCE;
+        }
+
+        if (ENT_USED & dst_rule[*dst_idx].status)
+        {
+            return SW_NO_RESOURCE;
+        }
+
+        SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_VALID, data,
+                            src_rule[i].filter.msk[4]);
+        if ((FLT_START == data) && (*dst_idx % 2))
+        {
+            if (*src_idx != i)
+            {
+                dst_rule[*dst_idx].list_id = list_id;
+                dst_rule[*dst_idx].list_pri = list_pri;
+                dst_rule[*dst_idx].rule_id = rule_id - 1;
+                dst_rule[*dst_idx].status |= ENT_USED;
+            }
+
+            (*dst_idx)++;
+            if (ISIS_MAX_FILTER <= *dst_idx)
+            {
+                return SW_NO_RESOURCE;
+            }
+
+            if (ENT_USED & dst_rule[*dst_idx].status)
+            {
+                return SW_NO_RESOURCE;
+            }
+        }
+
+        aos_mem_copy(&(dst_rule[*dst_idx].filter), &(src_rule[i].filter),
+                     sizeof (hw_filter_t));
+        dst_rule[*dst_idx].list_id = list_id;
+        dst_rule[*dst_idx].list_pri = list_pri;
+        dst_rule[*dst_idx].rule_id = rule_id;
+        dst_rule[*dst_idx].status |= ENT_USED;
+        if (ENT_DEACTIVE & src_rule[i].status)
+        {
+            dst_rule[*dst_idx].status |= ENT_DEACTIVE;
+        }
+        (*dst_idx)++;
+
+        if ((FLT_END == data) && (*dst_idx % 2))
+        {
+            if (ISIS_MAX_FILTER > *dst_idx)
+            {
+                dst_rule[*dst_idx].list_id = list_id;
+                dst_rule[*dst_idx].list_pri = list_pri;
+                dst_rule[*dst_idx].rule_id = rule_id;
+                dst_rule[*dst_idx].status |= ENT_USED;
+                (*dst_idx)++;
+            }
+        }
+
+        if ((FLT_END == data) || (FLT_STARTEND == data))
+        {
+            rule_id++;
+        }
+    }
+
+    *src_idx = i;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_alloc(a_uint32_t dev_id, isis_acl_list_t * sw_list,
+                     a_uint32_t filter_nr)
+{
+    a_uint32_t free_flt_nr, load_idx, begin_idx, start_idx, end_idx, i;
+    a_uint32_t largest_nr, largest_idx;
+    sw_error_t rv;
+
+    /* calculate the proper location, [start_idx, end_idx) */
+    start_idx = 0;
+    end_idx = ISIS_MAX_FILTER;
+    for (i = 0; i < ISIS_MAX_FILTER; i++)
+    {
+        if (ENT_USED & sw_rule_ent[dev_id][i].status)
+        {
+            if (sw_rule_ent[dev_id][i].list_pri < sw_list->list_pri)
+            {
+                start_idx = i + 1;
+            }
+            else if (sw_rule_ent[dev_id][i].list_pri > sw_list->list_pri)
+            {
+                end_idx = i;
+                break;
+            }
+        }
+    }
+
+    /* find the larget free filters block */
+    largest_nr = 0;
+    largest_idx = 0;
+    free_flt_nr = 0;
+    begin_idx = start_idx;
+    for (i = start_idx; i < end_idx; i++)
+    {
+        if (!(ENT_USED & sw_rule_ent[dev_id][i].status))
+        {
+            free_flt_nr++;
+        }
+        else
+        {
+            if (free_flt_nr > largest_nr)
+            {
+                largest_nr = free_flt_nr;
+                largest_idx = begin_idx;
+            }
+            free_flt_nr = 0;
+            begin_idx = i + 1;
+        }
+    }
+
+    if (free_flt_nr > largest_nr)
+    {
+        largest_nr = free_flt_nr;
+        largest_idx = begin_idx;
+    }
+
+    if ((!largest_nr) || ((largest_nr + 1) < filter_nr))
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    for (i = 0; i < ISIS_MAX_FILTER; i++)
+    {
+        if (ENT_USED & sw_rule_ent[dev_id][i].status)
+        {
+            aos_mem_copy(&(sw_rule_tmp[dev_id][i]), &(sw_rule_ent[dev_id][i]),
+                         sizeof (isis_acl_rule_t));
+        }
+    }
+
+    begin_idx = 0;
+    load_idx = largest_idx;
+    rv = _isis_acl_list_insert(dev_id, &begin_idx, &load_idx,
+                               hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]);
+    return rv;
+}
+
+static sw_error_t
+_isis_acl_rule_reorder(a_uint32_t dev_id, isis_acl_list_t * sw_list)
+{
+    a_uint32_t i, src_idx, dst_idx;
+    sw_error_t rv;
+
+    dst_idx = 0;
+    for (i = 0; i < ISIS_MAX_FILTER;)
+    {
+        if (ENT_USED & sw_rule_ent[dev_id][i].status)
+        {
+            if (sw_rule_ent[dev_id][i].list_pri <= sw_list->list_pri)
+            {
+                rv = _isis_acl_list_insert(dev_id, &i, &dst_idx,
+                                           sw_rule_ent[dev_id],
+                                           sw_rule_tmp[dev_id]);
+                SW_RTN_ON_ERROR(rv);
+            }
+            else
+            {
+                break;
+            }
+        }
+        else
+        {
+            i++;
+        }
+    }
+
+    src_idx = 0;
+    rv = _isis_acl_list_insert(dev_id, &src_idx, &dst_idx, hw_rule_tmp[dev_id],
+                               sw_rule_tmp[dev_id]);
+    SW_RTN_ON_ERROR(rv);
+
+    for (; i < ISIS_MAX_FILTER;)
+    {
+        if (ENT_USED & sw_rule_ent[dev_id][i].status)
+        {
+            rv = _isis_acl_list_insert(dev_id, &i, &dst_idx,
+                                       sw_rule_ent[dev_id],
+                                       sw_rule_tmp[dev_id]);
+            SW_RTN_ON_ERROR(rv);
+        }
+        else
+        {
+            i++;
+        }
+    }
+
+    return SW_OK;
+}
+
+static void
+_isis_acl_rule_sync(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flt_nr)
+{
+    a_uint32_t i, data;
+
+    for (i = flt_idx; i < (flt_idx + flt_nr); i++)
+    {
+        if (aos_mem_cmp
+                (&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]),
+                 sizeof (isis_acl_rule_t)))
+        {
+            SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data,
+                                sw_rule_tmp[dev_id][i].filter.msk[4]);
+            if (data)
+            {
+                _isis_filter_down_to_hw(dev_id,
+                                        &(sw_rule_tmp[dev_id][i].filter), i);
+            }
+            else
+            {
+                _isis_filter_valid_set(dev_id, i, 0);
+            }
+
+            aos_mem_copy(&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]),
+                         sizeof (isis_acl_rule_t));
+        }
+    }
+}
+
+static sw_error_t
+_isis_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri)
+{
+    a_uint32_t i, loc = ISIS_MAX_FILTER;
+    isis_acl_list_t *sw_list;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((ISIS_MAX_LIST_ID < list_id) || (ISIS_MAX_LIST_PRI < list_pri))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    for (i = 0; i < ISIS_MAX_FILTER; i++)
+    {
+        sw_list = &(sw_list_ent[dev_id][i]);
+        if (ENT_USED & sw_list->status)
+        {
+            if (list_id == sw_list->list_id)
+            {
+                return SW_ALREADY_EXIST;
+            }
+        }
+        else
+        {
+            loc = i;
+        }
+    }
+
+    if (ISIS_MAX_FILTER == loc)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    sw_list = &(sw_list_ent[dev_id][loc]);
+    aos_mem_zero(sw_list, sizeof (isis_acl_list_t));
+    sw_list->list_id = list_id;
+    sw_list->list_pri = list_pri;
+    sw_list->status |= ENT_USED;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    isis_acl_list_t *sw_list;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISIS_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    sw_list = _isis_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (0 != sw_list->bind_pts)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (0 != sw_list->rule_nr)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    aos_mem_zero(sw_list, sizeof (isis_acl_list_t));
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+                   a_uint32_t rule_id, a_uint32_t rule_nr,
+                   fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+    isis_acl_list_t *sw_list;
+    isis_acl_rule_t *sw_rule;
+    a_uint32_t i, free_flt_nr, old_flt_nr, old_flt_idx, new_flt_nr, bind_pts;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISIS_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if ((0 == rule_nr) || (NULL == rule))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    sw_list = _isis_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (rule_id != sw_list->rule_nr)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    old_flt_idx = 0;
+    old_flt_nr = 0;
+    free_flt_nr = 0;
+    aos_mem_zero(hw_rule_tmp[dev_id],
+                 ISIS_HW_RULE_TMP_CNT * sizeof (isis_acl_rule_t));
+    aos_mem_zero(sw_rule_tmp[dev_id],
+                 ISIS_MAX_FILTER * sizeof (isis_acl_rule_t));
+    for (i = 0; i < ISIS_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i]);
+        if (ENT_USED & sw_rule->status)
+        {
+            if (sw_rule->list_id == sw_list->list_id)
+            {
+                aos_mem_copy(&(hw_rule_tmp[dev_id][old_flt_nr]), sw_rule,
+                             sizeof (isis_acl_rule_t));
+                if (!old_flt_nr)
+                {
+                    old_flt_idx = i;
+                }
+                old_flt_nr++;
+            }
+        }
+        else
+        {
+            free_flt_nr++;
+        }
+    }
+
+    if (!free_flt_nr)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    /* parse rule entry and alloc rule resource */
+    new_flt_nr = old_flt_nr;
+    for (i = 0; i < rule_nr; i++)
+    {
+        rv = _isis_acl_rule_sw_to_hw(dev_id, &rule[i], hw_rule_tmp[dev_id],
+                                     &new_flt_nr);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    if (free_flt_nr < (new_flt_nr - old_flt_nr))
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    for (i = old_flt_nr; i < new_flt_nr; i++)
+    {
+        hw_rule_tmp[dev_id][i].status |= ENT_USED;
+        hw_rule_tmp[dev_id][i].list_id = sw_list->list_id;
+        hw_rule_tmp[dev_id][i].list_pri = sw_list->list_pri;
+        bind_pts = sw_list->bind_pts;
+        SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, bind_pts,
+                            (hw_rule_tmp[dev_id][i].filter.vlu[4]));
+    }
+
+    for (i = 0; i < old_flt_nr; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][old_flt_idx + i]);
+        sw_rule->status &= (~ENT_USED);
+        sw_rule->status |= (ENT_TMP);
+    }
+
+    rv = _isis_acl_rule_alloc(dev_id, sw_list, new_flt_nr);
+    if (SW_OK != rv)
+    {
+        aos_mem_zero(sw_rule_tmp[dev_id],
+                     ISIS_MAX_FILTER * sizeof (isis_acl_rule_t));
+        rv = _isis_acl_rule_reorder(dev_id, sw_list);
+    }
+
+    for (i = 0; i < old_flt_nr; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i + old_flt_idx]);
+        sw_rule->status |= (ENT_USED);
+        sw_rule->status &= (~ENT_TMP);
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    _isis_acl_rule_sync(dev_id, 0, ISIS_MAX_FILTER);
+    sw_list->rule_nr += rule_nr;
+
+    _isis_acl_sw_rule_dump("sw rule after add", sw_rule_ent[dev_id]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+                      a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    isis_acl_rule_t *sw_rule;
+    isis_acl_list_t *sw_list;
+    a_uint32_t i, flt_idx = 0, src_idx, dst_idx, del_nr = 0, flt_nr = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISIS_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    sw_list = _isis_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (sw_list->rule_nr < (rule_id + rule_nr))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(hw_rule_tmp[dev_id],
+                 ISIS_HW_RULE_TMP_CNT * sizeof (isis_acl_rule_t));
+    aos_mem_zero(sw_rule_tmp[dev_id],
+                 ISIS_MAX_FILTER * sizeof (isis_acl_rule_t));
+
+    for (i = 0; i < ISIS_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i]);
+        if ((ENT_USED & sw_rule->status) && (sw_rule->list_id == list_id))
+        {
+            if (!flt_nr)
+            {
+                flt_idx = i;
+            }
+
+            if ((sw_rule->rule_id >= rule_id)
+                    && (sw_rule->rule_id < (rule_id + rule_nr)))
+            {
+                del_nr++;
+            }
+            else
+            {
+                aos_mem_copy(&(hw_rule_tmp[dev_id][flt_idx + flt_nr]), sw_rule,
+                             sizeof (isis_acl_rule_t));
+            }
+            flt_nr++;
+        }
+    }
+
+    if (!del_nr)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    _isis_acl_sw_rule_dump("hw rule before del", hw_rule_tmp[dev_id]);
+
+    for (i = 0; i < flt_nr; i++)
+    {
+        sw_rule = &(hw_rule_tmp[dev_id][flt_idx + i]);
+        if (ENT_USED & sw_rule->status)
+        {
+            break;
+        }
+    }
+
+    if (i != flt_nr)
+    {
+        src_idx = flt_idx + i;
+        dst_idx = flt_idx;
+        rv = _isis_acl_list_insert(dev_id, &src_idx, &dst_idx,
+                                   hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    _isis_acl_rule_sync(dev_id, flt_idx, flt_nr);
+    sw_list->rule_nr -= rule_nr;
+
+    _isis_acl_sw_rule_dump("sw rule after del", sw_rule_ent[dev_id]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+                     a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+    isis_acl_rule_t *sw_rule;
+    a_uint32_t flt_nr = 0, i;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISIS_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    aos_mem_zero(hw_rule_tmp[dev_id],
+                 ISIS_HW_RULE_TMP_CNT * sizeof (isis_acl_rule_t));
+    for (i = 0; i < ISIS_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i]);
+        if (ENT_USED & sw_rule->status)
+        {
+            if ((sw_rule->list_id == list_id) && (sw_rule->rule_id == rule_id))
+            {
+                aos_mem_copy(&(hw_rule_tmp[dev_id][flt_nr]), sw_rule,
+                             sizeof (isis_acl_rule_t));
+                flt_nr++;
+            }
+        }
+    }
+
+    if (!flt_nr)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    aos_mem_zero(rule, sizeof (fal_acl_rule_t));
+    rv = _isis_acl_rule_hw_to_sw(dev_id, rule, hw_rule_tmp[dev_id], 0, flt_nr);
+    return rv;
+}
+
+static sw_error_t
+_isis_acl_rule_bind(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t ports)
+{
+    sw_error_t rv;
+    a_uint32_t i;
+    isis_acl_rule_t *sw_rule;
+
+    for (i = 0; i < ISIS_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i]);
+
+        if ((ENT_USED & sw_rule->status)
+                && (list_id == sw_rule->list_id)
+                && (!(ENT_DEACTIVE & sw_rule->status)))
+        {
+            rv = _isis_filter_ports_bind(dev_id, i, ports);
+            SW_RTN_ON_ERROR(rv);
+
+            SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports,
+                                (sw_rule->filter.vlu[4]));
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                    fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                    a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+    a_uint32_t ports;
+    isis_acl_list_t *sw_list;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISIS_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACL_DIREC_IN != direc)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    sw_list = _isis_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (FAL_ACL_BIND_PORT == obj_t)
+    {
+        ports = (sw_list->bind_pts) | (0x1 << obj_idx);
+    }
+    else if (FAL_ACL_BIND_PORTBITMAP == obj_t)
+    {
+        ports = (sw_list->bind_pts) | obj_idx;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    rv = _isis_acl_rule_bind(dev_id, list_id, ports);
+    SW_RTN_ON_ERROR(rv);
+
+    sw_list->bind_pts = ports;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                      fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                      a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+    a_uint32_t ports;
+    isis_acl_list_t *sw_list;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISIS_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACL_DIREC_IN != direc)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    sw_list = _isis_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (FAL_ACL_BIND_PORT == obj_t)
+    {
+        ports = (sw_list->bind_pts) & (~(0x1UL << obj_idx));
+    }
+    else if (FAL_ACL_BIND_PORTBITMAP == obj_t)
+    {
+        ports = (sw_list->bind_pts) & (~obj_idx);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    rv = _isis_acl_rule_bind(dev_id, list_id, ports);
+    SW_RTN_ON_ERROR(rv);
+
+    sw_list->bind_pts = ports;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_acl_udf_type_t udf_type, a_uint32_t offset,
+                               a_uint32_t length)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISIS_UDF_MAX_OFFSET < offset)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISIS_UDF_MAX_OFFSET < length)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
+            || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type))
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    switch (udf_type)
+    {
+        case FAL_ACL_UDF_TYPE_L2:
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_OFFSET, offset, reg);
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_LENGTH, length, reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L3:
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_OFFSET, offset, reg);
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_LENGTH, length, reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L4:
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_OFFSET, offset, reg);
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_LENGTH, length, reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L2_SNAP:
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_OFFSET, offset, reg);
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_LENGTH, length, reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L3_PLUS:
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_OFFSET, offset, reg);
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_LENGTH, length, reg);
+            break;
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
+            || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type))
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL1, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL0, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isis_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_acl_udf_type_t udf_type, a_uint32_t * offset,
+                               a_uint32_t * length)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
+            || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type))
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    switch (udf_type)
+    {
+        case FAL_ACL_UDF_TYPE_L2:
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_OFFSET, (*offset), reg);
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_LENGTH, (*length), reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L3:
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_OFFSET, (*offset), reg);
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_LENGTH, (*length), reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L4:
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_OFFSET, (*offset), reg);
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_LENGTH, (*length), reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L2_SNAP:
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_OFFSET, (*offset), reg);
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_LENGTH, (*length), reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L3_PLUS:
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_OFFSET, (*offset), reg);
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_LENGTH, (*length), reg);
+            break;
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+                      a_uint32_t rule_id, a_uint32_t rule_nr, a_bool_t active)
+{
+    sw_error_t rv;
+    a_uint32_t i, ports;
+    isis_acl_list_t *sw_list;
+    isis_acl_rule_t *sw_rule;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    sw_list = _isis_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (sw_list->rule_nr < (rule_id + rule_nr))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == active)
+    {
+        ports = (sw_list->bind_pts);
+    }
+    else
+    {
+        ports = 0;
+    }
+
+    for (i = 0; i < ISIS_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i]);
+
+        if ((ENT_USED & sw_rule->status)
+                && (list_id == sw_rule->list_id)
+                && (rule_id <= sw_rule->rule_id)
+                && ((rule_id + rule_nr) > sw_rule->rule_id))
+        {
+            rv = _isis_filter_ports_bind(dev_id, i, ports);
+            SW_RTN_ON_ERROR(rv);
+
+            SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports,
+                                (sw_rule->filter.vlu[4]));
+
+            if (A_TRUE == active)
+            {
+                sw_rule->status &= (~ENT_DEACTIVE);
+            }
+            else
+            {
+                sw_rule->status |= (ENT_DEACTIVE);
+            }
+        }
+    }
+
+    return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+isis_acl_list_dump(a_uint32_t dev_id)
+{
+    _isis_acl_list_dump(dev_id);
+    return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+isis_acl_rule_dump(a_uint32_t dev_id)
+{
+    a_uint32_t flt_idx, i;
+    sw_error_t rv;
+    hw_filter_t filter;
+
+    aos_printk("\nisis_acl_rule_dump:\n");
+
+    for (flt_idx = 0; flt_idx < ISIS_MAX_FILTER; flt_idx++)
+    {
+        aos_mem_zero(&filter, sizeof (hw_filter_t));
+
+        rv = _isis_filter_up_to_sw(dev_id, &filter, flt_idx);
+        if (SW_OK != rv)
+        {
+            continue;
+        }
+
+        aos_printk("\n%d filter dump:", flt_idx);
+
+        aos_printk("\nhardware content:");
+        aos_printk("\nact:");
+        for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", filter.act[i]);
+        }
+
+        aos_printk("\nvlu:");
+        for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", filter.vlu[i]);
+        }
+
+        aos_printk("\nmsk:");
+        for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", filter.msk[i]);
+        }
+
+        aos_printk("\nsoftware content:");
+        aos_printk("\nact:");
+        for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", sw_rule_ent[dev_id][flt_idx].filter.act[i]);
+        }
+
+        aos_printk("\nvlu:");
+        for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", sw_rule_ent[dev_id][flt_idx].filter.vlu[i]);
+        }
+
+        aos_printk("\nmsk:");
+        for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", sw_rule_ent[dev_id][flt_idx].filter.msk[i]);
+        }
+
+        aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d]",
+                   sw_rule_ent[dev_id][flt_idx].status,
+                   sw_rule_ent[dev_id][flt_idx].list_id,
+                   sw_rule_ent[dev_id][flt_idx].rule_id);
+
+        aos_printk("\n\n");
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+isis_acl_reset(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    aos_mem_zero(sw_list_ent[dev_id],
+                 ISIS_MAX_FILTER * sizeof (isis_acl_list_t));
+
+    aos_mem_zero(sw_rule_ent[dev_id],
+                 ISIS_MAX_FILTER * sizeof (isis_acl_rule_t));
+
+    return SW_OK;
+}
+
+/**
+ * @brief Creat an acl list
+ * @details  Comments:
+  *     If the value of list_pri is more small then the priority is more high,
+ *     that means the list could be first matched.
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] list_pri acl list priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+isis_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_acl_list_creat(dev_id, list_id, list_pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Destroy an acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_acl_list_destroy(dev_id, list_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one rule or more rules to an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this adding operation in list
+ * @param[in] rule_nr rule number of this adding operation
+ * @param[in] rule rules content of this adding operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+isis_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+                  a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one rule or more rules from an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[in] rule_nr rule number of this deleteing operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+isis_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+                     a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_acl_rule_delete(dev_id, list_id, rule_id, rule_nr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Query one particular rule in a particular acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[out] rule rule content of this operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+isis_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+                    a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_acl_rule_query(dev_id, list_id, rule_id, rule);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+a_uint32_t
+isis_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id)
+{
+    a_uint32_t i, pos=0;
+    isis_acl_rule_t *sw_rule;
+
+    for (i = 0; i < ISIS_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[0][i]);
+
+        if ((ENT_USED & sw_rule->status)
+                && (list_id == sw_rule->list_id) && (sw_rule->rule_id == rule_id)
+                && (!(ENT_DEACTIVE & sw_rule->status)))
+        {
+            pos = i;
+            break;
+
+        }
+    }
+
+    return pos;
+}
+
+
+sw_error_t
+isis_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act)
+{
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISIS_MAX_LIST_ID < pos)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    sw_rule_ent[dev_id][pos].filter.act[1] = act[1];
+    sw_rule_ent[dev_id][pos].filter.act[2] = act[2];
+
+    sw_rule_tmp[dev_id][pos].filter.act[1] = act[1];
+    sw_rule_tmp[dev_id][pos].filter.act[2] = act[2];
+
+    hw_rule_tmp[dev_id][pos].filter.act[1] = act[1];
+    hw_rule_tmp[dev_id][pos].filter.act[2] = act[2];
+
+
+    return SW_OK;
+}
+
+/**
+ * @brief Bind an acl list to a particular object
+ * @details  Comments:
+ *    If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this binding operation
+ * @param[in] obj_t object type of this binding operation
+ * @param[in] obj_idx object index of this binding operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+isis_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                   fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                   a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Unbind an acl list from a particular object
+ * @details  Comments:
+  *    If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this unbinding operation
+ * @param[in] obj_t object type of this unbinding operation
+ * @param[in] obj_idx object index of this unbinding operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+isis_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                     fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                     a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+isis_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_acl_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_acl_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set user define fields profile on a particular port
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] udf_type udf type
+ * @param[in] offset udf offset
+ * @param[in] length udf length
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_acl_udf_type_t udf_type, a_uint32_t offset,
+                              a_uint32_t length)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_acl_port_udf_profile_set(dev_id, port_id, udf_type, offset,
+                                        length);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get user define fields profile on a particular port
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] udf_type udf type
+ * @param[out] offset udf offset
+ * @param[out] length udf length
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_acl_udf_type_t udf_type, a_uint32_t * offset,
+                              a_uint32_t * length)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_acl_port_udf_profile_get(dev_id, port_id, udf_type, offset,
+                                        length);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Active one or more rules in an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] rule_nr rule number of this deactive operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+                     a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_TRUE);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Deactive one or more rules in an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] rule_nr rule number of this deactive operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+                       a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_FALSE);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_acl_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    sw_list_ent[dev_id] =
+        (isis_acl_list_t *) aos_mem_alloc(ISIS_MAX_FILTER *
+                                          sizeof (isis_acl_list_t));
+    if (NULL == sw_list_ent[dev_id])
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(sw_list_ent[dev_id],
+                 ISIS_MAX_FILTER * sizeof (isis_acl_list_t));
+
+    sw_rule_ent[dev_id] =
+        (isis_acl_rule_t *) aos_mem_alloc(ISIS_MAX_FILTER *
+                                          sizeof (isis_acl_rule_t));
+    if (NULL == sw_rule_ent[dev_id])
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(sw_rule_ent[dev_id],
+                 ISIS_MAX_FILTER * sizeof (isis_acl_rule_t));
+
+    hw_rule_tmp[dev_id] =
+        (isis_acl_rule_t *) aos_mem_alloc(ISIS_HW_RULE_TMP_CNT *
+                                          sizeof (isis_acl_rule_t));
+    if (NULL == hw_rule_tmp[dev_id])
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    sw_rule_tmp[dev_id] =
+        (isis_acl_rule_t *) aos_mem_alloc(ISIS_MAX_FILTER *
+                                          sizeof (isis_acl_rule_t));
+    if (NULL == sw_rule_tmp[dev_id])
+    {
+        return SW_NO_RESOURCE;
+    }
+#ifdef ISIS_SW_ENTRY
+    sw_filter_mem = aos_mem_alloc(ISIS_MAX_FILTER * sizeof (hw_filter_t));
+    if (NULL == sw_filter_mem)
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(sw_filter_mem, ISIS_MAX_FILTER * sizeof (hw_filter_t));
+#endif
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->acl_list_creat = isis_acl_list_creat;
+        p_api->acl_list_destroy = isis_acl_list_destroy;
+        p_api->acl_list_bind = isis_acl_list_bind;
+        p_api->acl_list_unbind = isis_acl_list_unbind;
+        p_api->acl_rule_add = isis_acl_rule_add;
+        p_api->acl_rule_delete = isis_acl_rule_delete;
+        p_api->acl_rule_query = isis_acl_rule_query;
+        p_api->acl_status_set = isis_acl_status_set;
+        p_api->acl_status_get = isis_acl_status_get;
+        p_api->acl_list_dump = isis_acl_list_dump;
+        p_api->acl_rule_dump = isis_acl_rule_dump;
+        p_api->acl_port_udf_profile_set = isis_acl_port_udf_profile_set;
+        p_api->acl_port_udf_profile_get = isis_acl_port_udf_profile_get;
+        p_api->acl_rule_active = isis_acl_rule_active;
+        p_api->acl_rule_deactive = isis_acl_rule_deactive;
+        p_api->acl_rule_get_offset = isis_acl_rule_get_offset;
+        p_api->acl_rule_sync_multi_portmap = isis_acl_rule_sync_multi_portmap;
+    }
+#endif
+
+    return SW_OK;
+}
+
+sw_error_t
+isis_acl_cleanup(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (NULL != sw_list_ent[dev_id])
+    {
+        aos_mem_free(sw_list_ent[dev_id]);
+    }
+
+    if (NULL != sw_rule_ent[dev_id])
+    {
+        aos_mem_free(sw_rule_ent[dev_id]);
+    }
+
+    if (NULL != hw_rule_tmp[dev_id])
+    {
+        aos_mem_free(hw_rule_tmp[dev_id]);
+    }
+
+    if (NULL != sw_rule_tmp[dev_id])
+    {
+        aos_mem_free(sw_rule_tmp[dev_id]);
+    }
+#ifdef DESS_SW_ENTRY
+    if (NULL != sw_filter_mem)
+    {
+        aos_mem_free(sw_filter_mem);
+    }
+#endif
+
+    return SW_OK;
+}
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isis/isis_acl_parse.c b/qca-ssdk/src/hsl/isis/isis_acl_parse.c
new file mode 100755
index 0000000..4c52671
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_acl_parse.c
@@ -0,0 +1,2452 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+#include "isis_acl.h"
+#include "isis_reg.h"
+#include "isis_acl_prv.h"
+
+#define DAH  0x1
+#define SAH  0x2
+#define TAG  0x4
+#define STAG 0x8
+#define CTAG 0x10
+
+typedef sw_error_t(*parse_func_t) (fal_acl_rule_t * sw,
+                                   hw_filter_t * hw_filter_snap,
+                                   a_bool_t * b_care);
+
+static a_bool_t
+_isis_acl_zero_addr(const fal_mac_addr_t addr)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 6; i++)
+    {
+        if (addr.uc[i])
+        {
+            return A_FALSE;
+        }
+    }
+    return A_TRUE;
+}
+
+static a_bool_t
+_isis_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask,
+                     a_uint32_t chkvlu)
+{
+    if (FAL_ACL_FIELD_MASK == op)
+    {
+        if (0 == mask)
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_RANGE == op)
+    {
+        if ((0 == val) && (chkvlu == mask))
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_LE == op)
+    {
+        if (chkvlu == val)
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_GE == op)
+    {
+        if (0 == val)
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_NE == op)
+    {
+        return A_TRUE;
+    }
+
+    return A_TRUE;
+}
+
+static sw_error_t
+_isis_acl_rule_bmac_parse(fal_acl_rule_t * sw,
+                          hw_filter_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISIS_MAC_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+    {
+        if (A_TRUE != _isis_acl_zero_addr(sw->dest_mac_mask))
+        {
+            *b_care = A_TRUE;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+        }
+
+        FIELD_SET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]);
+        FIELD_SET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]);
+        FIELD_SET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]);
+        FIELD_SET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]);
+        FIELD_SET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]);
+        FIELD_SET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]);
+
+        FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]);
+        FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]);
+        FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]);
+        FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]);
+        FIELD_SET_MASK(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]);
+        FIELD_SET_MASK(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+    {
+        if (A_TRUE != _isis_acl_zero_addr(sw->src_mac_mask))
+        {
+            *b_care = A_TRUE;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+        }
+
+        FIELD_SET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+        FIELD_SET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+        FIELD_SET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]);
+        FIELD_SET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]);
+        FIELD_SET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]);
+        FIELD_SET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+
+        FIELD_SET_MASK(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+        FIELD_SET_MASK(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+        FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]);
+        FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]);
+        FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]);
+        FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+    {
+        if (0x0 != sw->ethtype_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ethtype_val &= sw->ethtype_mask;
+        FIELD_SET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+        FIELD_SET_MASK(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED))
+    {
+        if (0x0 != sw->tagged_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->tagged_val &= sw->tagged_mask;
+        FIELD_SET_MASK(MAC_RUL_M4, TAGGEDV, sw->tagged_val);
+        FIELD_SET_MASK(MAC_RUL_M4, TAGGEDM, sw->tagged_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP))
+    {
+        if (0x0 != sw->up_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->up_val &= sw->up_mask;
+        FIELD_SET(MAC_RUL_V3, VLANPRIV, sw->up_val);
+        FIELD_SET_MASK(MAC_RUL_M3, VLANPRIM, sw->up_mask);
+    }
+
+    FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->vid_op)
+                && (FAL_ACL_FIELD_RANGE != sw->vid_op)
+                && (FAL_ACL_FIELD_LE != sw->vid_op)
+                && (FAL_ACL_FIELD_GE != sw->vid_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_TRUE ==
+                _isis_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask,
+                                     0xfff))
+        {
+            *b_care = A_TRUE;
+        }
+
+        FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 0);
+        if (FAL_ACL_FIELD_MASK == sw->vid_op)
+        {
+            sw->vid_val &= sw->vid_mask;
+            FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+            FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask);
+            FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 1);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->vid_op)
+        {
+            FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+            FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->vid_op)
+        {
+            FIELD_SET(MAC_RUL_V3, VLANIDV, 0);
+            FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_val);
+        }
+        else
+        {
+            FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+            FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, 0xfff);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI))
+    {
+        if (0x0 != sw->cfi_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->cfi_val &= sw->cfi_mask;
+        FIELD_SET(MAC_RUL_V3, VLANCFIV, sw->cfi_val);
+        FIELD_SET_MASK(MAC_RUL_M3, VLANCFIM, sw->cfi_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ehmac_parse(fal_acl_rule_t * sw,
+                           hw_filter_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i;
+    a_bool_t da_h = A_FALSE, sa_h = A_FALSE;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISIS_EHMAC_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+    {
+        for (i = 0; i < 3; i++)
+        {
+            if (sw->dest_mac_mask.uc[i])
+            {
+                da_h = A_TRUE;
+                break;
+            }
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+    {
+        for (i = 0; i < 3; i++)
+        {
+            if (sw->src_mac_mask.uc[i])
+            {
+                sa_h = A_TRUE;
+                break;
+            }
+        }
+    }
+
+    /* if sa_h and da_h both are true need't process mac address fileds */
+    if ((A_TRUE == da_h) && ((A_TRUE == sa_h)))
+    {
+        da_h = A_FALSE;
+        sa_h = A_FALSE;
+    }
+
+    if (A_TRUE == da_h)
+    {
+        FIELD_SET(EHMAC_RUL_V3, DA_EN, 1);
+
+        if (A_TRUE != _isis_acl_zero_addr(sw->dest_mac_mask))
+        {
+            *b_care = A_TRUE;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+        }
+
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]);
+        FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]);
+        FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]);
+
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]);
+        FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]);
+        FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]);
+
+        if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+        {
+            if (A_TRUE != _isis_acl_zero_addr(sw->src_mac_mask))
+            {
+                *b_care = A_TRUE;
+            }
+
+            for (i = 0; i < 6; i++)
+            {
+                sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+            }
+
+            FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+            FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+            FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+
+            FIELD_SET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+            FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+            FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+        }
+    }
+
+    if (A_TRUE == sa_h)
+    {
+        if (A_TRUE != _isis_acl_zero_addr(sw->src_mac_mask))
+        {
+            *b_care = A_TRUE;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+        }
+
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->src_mac_val.uc[2]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->src_mac_val.uc[3]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->src_mac_val.uc[4]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->src_mac_val.uc[5]);
+        FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->src_mac_val.uc[0]);
+        FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->src_mac_val.uc[1]);
+
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE2, sw->src_mac_mask.uc[2]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE3, sw->src_mac_mask.uc[3]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE4, sw->src_mac_mask.uc[4]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE5, sw->src_mac_mask.uc[5]);
+        FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE0, sw->src_mac_mask.uc[0]);
+        FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE1, sw->src_mac_mask.uc[1]);
+
+        if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+        {
+            if (A_TRUE != _isis_acl_zero_addr(sw->dest_mac_mask))
+            {
+                *b_care = A_TRUE;
+            }
+
+            for (i = 0; i < 6; i++)
+            {
+                sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+            }
+
+            FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]);
+            FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]);
+            FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]);
+
+            FIELD_SET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]);
+            FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]);
+            FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+    {
+        if (0x0 != sw->ethtype_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ethtype_val &= sw->ethtype_mask;
+        FIELD_SET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+        FIELD_SET_MASK(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+    }
+
+    /* Process Stag Fields */
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED))
+    {
+        if (0x0 != sw->stagged_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->stagged_val &= sw->stagged_mask;
+        FIELD_SET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val);
+        FIELD_SET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask);
+    }
+
+    FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->stag_vid_op)
+                && (FAL_ACL_FIELD_RANGE != sw->stag_vid_op)
+                && (FAL_ACL_FIELD_LE != sw->stag_vid_op)
+                && (FAL_ACL_FIELD_GE != sw->stag_vid_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_TRUE ==
+                _isis_acl_field_care(sw->stag_vid_op, sw->stag_vid_val,
+                                     sw->stag_vid_mask, 0xfff))
+        {
+            *b_care = A_TRUE;
+        }
+
+        FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 0);
+        if (FAL_ACL_FIELD_MASK == sw->stag_vid_op)
+        {
+            sw->stag_vid_val &= sw->stag_vid_mask;
+            FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+            FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask);
+            FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1);
+
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->stag_vid_op)
+        {
+            FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+            FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask);
+
+        }
+        else if (FAL_ACL_FIELD_LE == sw->stag_vid_op)
+        {
+            FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, 0);
+            FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_val);
+
+        }
+        else
+        {
+            FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+            FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, 0xfff);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI))
+    {
+        if (0x0 != sw->stag_pri_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->stag_pri_val &= sw->stag_pri_mask;
+        FIELD_SET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val);
+        FIELD_SET_MASK(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI))
+    {
+        if (0x0 != sw->stag_dei_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->stag_dei_val &= sw->stag_dei_mask;
+        FIELD_SET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val);
+        FIELD_SET_MASK(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask);
+    }
+
+    /* Process Ctag Fields */
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED))
+    {
+        if (0x0 != sw->ctagged_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ctagged_val &= sw->ctagged_mask;
+        FIELD_SET_MASK(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val);
+        FIELD_SET_MASK(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask);
+    }
+
+    FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->ctag_vid_op)
+                && (FAL_ACL_FIELD_RANGE != sw->ctag_vid_op)
+                && (FAL_ACL_FIELD_LE != sw->ctag_vid_op)
+                && (FAL_ACL_FIELD_GE != sw->ctag_vid_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_TRUE ==
+                _isis_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val,
+                                     sw->ctag_vid_mask, 0xfff))
+        {
+            *b_care = A_TRUE;
+        }
+
+        FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 0);
+        if (FAL_ACL_FIELD_MASK == sw->ctag_vid_op)
+        {
+            sw->ctag_vid_val &= sw->ctag_vid_mask;
+            FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+            FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8));
+            FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask);
+            FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8));
+            FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 1);
+
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->ctag_vid_op)
+        {
+            FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+            FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8));
+            FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask);
+            FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8));
+
+        }
+        else if (FAL_ACL_FIELD_LE == sw->ctag_vid_op)
+        {
+            FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, 0);
+            FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, 0);
+            FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_val);
+            FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_val >> 8));
+
+        }
+        else
+        {
+            FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+            FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8));
+            FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, 0xff);
+            FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, 0xf);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI))
+    {
+        if (0x0 != sw->ctag_pri_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ctag_pri_val &= sw->ctag_pri_mask;
+        FIELD_SET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val);
+        FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI))
+    {
+        if (0x0 != sw->ctag_cfi_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ctag_cfi_val &= sw->ctag_cfi_mask;
+        FIELD_SET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val);
+        FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static void
+_isis_acl_rule_mac_preparse(fal_acl_rule_t * sw, a_bool_t * b_mac,
+                            a_bool_t * eh_mac)
+{
+    a_uint32_t bm = 0, i, tmp;
+
+    *b_mac = A_FALSE;
+    *eh_mac = A_FALSE;
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+    {
+        for (i = 0; i < 3; i++)
+        {
+            if (sw->dest_mac_mask.uc[i])
+            {
+                bm |= DAH;
+                break;
+            }
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+    {
+        for (i = 0; i < 3; i++)
+        {
+            if (sw->src_mac_mask.uc[i])
+            {
+                bm |= SAH;
+                break;
+            }
+        }
+    }
+
+    tmp = 0;
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED))
+    {
+        tmp |= ((sw->tagged_mask & 0x1) << 16);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP))
+    {
+        tmp |= ((sw->up_mask & 0x7) << 13);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI))
+    {
+        tmp |= ((sw->cfi_mask & 0x1) << 12);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID))
+    {
+        if (A_TRUE ==
+                _isis_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask,
+                                     0xfff))
+        {
+            tmp |= 0xfff;
+        }
+    }
+    if (tmp)
+    {
+        bm |= TAG;
+    }
+
+    tmp = 0;
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED))
+    {
+        tmp |= ((sw->stagged_mask & 0x1) << 16);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI))
+    {
+        tmp |= ((sw->stag_pri_mask & 0x7) << 13);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI))
+    {
+        tmp |= ((sw->stag_dei_mask & 0x1) << 12);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID))
+    {
+        if (A_TRUE ==
+                _isis_acl_field_care(sw->stag_vid_op, sw->stag_vid_val,
+                                     sw->stag_vid_mask, 0xfff))
+        {
+            tmp |= 0xfff;
+        }
+    }
+    if (tmp)
+    {
+        bm |= STAG;
+    }
+
+    tmp = 0;
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED))
+    {
+        tmp |= ((sw->ctagged_mask & 0x1) << 16);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI))
+    {
+        tmp |= ((sw->ctag_pri_mask & 0x7) << 13);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI))
+    {
+        tmp |= ((sw->ctag_cfi_mask & 0x1) << 12);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID))
+    {
+        if (A_TRUE ==
+                _isis_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val,
+                                     sw->ctag_vid_mask, 0xfff))
+        {
+            tmp |= 0xfff;
+        }
+    }
+    if (tmp)
+    {
+        bm |= CTAG;
+    }
+
+    if ((bm & CTAG) || (bm & STAG))
+    {
+        *eh_mac = A_TRUE;
+    }
+
+    if ((bm & TAG) || ((bm & DAH) && (bm & SAH)))
+    {
+        *b_mac = A_TRUE;
+    }
+}
+
+static sw_error_t
+_isis_acl_rule_ip4_parse(fal_acl_rule_t * sw,
+                         hw_filter_t * hw, a_bool_t * b_care)
+{
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISIS_IP4_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+    {
+        if (0x0 != sw->ip_dscp_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_dscp_val &= sw->ip_dscp_mask;
+        FIELD_SET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val);
+        FIELD_SET_MASK(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+    {
+        if (0x0 != sw->ip_proto_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_proto_val &= sw->ip_proto_mask;
+        FIELD_SET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val);
+        FIELD_SET_MASK(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_SIP))
+    {
+        if (0x0 != sw->src_ip4_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        sw->src_ip4_val &= sw->src_ip4_mask;
+        hw->vlu[1] = sw->src_ip4_val;
+        hw->msk[1] = sw->src_ip4_mask;
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_DIP))
+    {
+        if (0x0 != sw->dest_ip4_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        sw->dest_ip4_val &= sw->dest_ip4_mask;
+        hw->vlu[0] = sw->dest_ip4_val;
+        hw->msk[0] = sw->dest_ip4_mask;
+    }
+
+    if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+            && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+                || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _isis_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+                                     sw->src_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+            {
+                sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+                sw->src_l4port_val = 0;
+                sw->src_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+
+        FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 0);
+        if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+        {
+            sw->src_l4port_val &= sw->src_l4port_mask;
+            FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 1);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+        {
+            FIELD_SET(IP4_RUL_V3, IP4SPORTV, 0);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_val);
+        }
+        else
+        {
+            FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, 0xffff);
+        }
+    }
+
+    FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _isis_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+                                     sw->dest_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+            {
+                sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+                sw->dest_l4port_val = 0;
+                sw->dest_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+
+        FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 0);
+        if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+        {
+            sw->dest_l4port_val &= sw->dest_l4port_mask;
+            FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 1);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+        {
+            FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+        {
+            FIELD_SET(IP4_RUL_V2, IP4DPORTV, 0);
+            FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_val);
+        }
+        else
+        {
+            FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, 0xffff);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+    {
+        if (0x0 != sw->icmp_type_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        FIELD_SET(IP4_RUL_V3, ICMP_EN, 1);
+
+        sw->icmp_type_val &= sw->icmp_type_mask;
+        FIELD_SET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val);
+        FIELD_SET_MASK(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))
+    {
+        if (0x0 != sw->icmp_code_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        FIELD_SET(IP4_RUL_V3, ICMP_EN, 1);
+
+        sw->icmp_code_val &= sw->icmp_code_mask;
+        FIELD_SET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val);
+        FIELD_SET_MASK(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG))
+    {
+        if (0x0 != sw->tcp_flag_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->tcp_flag_val &= sw->tcp_flag_mask;
+        FIELD_SET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val);
+        FIELD_SET_MASK(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_RIPV1))
+    {
+        if (0x0 != sw->ripv1_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ripv1_val &= sw->ripv1_mask;
+        FIELD_SET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val);
+        FIELD_SET_MASK(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV4))
+    {
+        if (0x0 != sw->dhcpv4_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->dhcpv4_val &= sw->dhcpv4_mask;
+        FIELD_SET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val);
+        FIELD_SET_MASK(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ip6r1_parse(fal_acl_rule_t * sw,
+                           hw_filter_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISIS_IP6R1_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_DIP))
+    {
+        for (i = 0; i < 4; i++)
+        {
+            if (0x0 != sw->dest_ip6_mask.ul[i])
+            {
+                *b_care = A_TRUE;
+            }
+
+            sw->dest_ip6_val.ul[3 - i] &= sw->dest_ip6_mask.ul[3 - i];
+            hw->vlu[i] = sw->dest_ip6_val.ul[3 - i];
+            hw->msk[i] = sw->dest_ip6_mask.ul[3 - i];
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ip6r2_parse(fal_acl_rule_t * sw,
+                           hw_filter_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISIS_IP6R2_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_SIP))
+    {
+        for (i = 0; i < 4; i++)
+        {
+            if (0x0 != sw->src_ip6_mask.ul[i])
+            {
+                *b_care = A_TRUE;
+            }
+
+            sw->src_ip6_val.ul[3 - i] &= sw->src_ip6_mask.ul[3 - i];
+            hw->vlu[i] = sw->src_ip6_val.ul[3 - i];
+            hw->msk[i] = sw->src_ip6_mask.ul[3 - i];
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ip6r3_parse(fal_acl_rule_t * sw,
+                           hw_filter_t * hw, a_bool_t * b_care)
+{
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISIS_IP6R3_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL))
+    {
+        if (0x0 != sw->ip6_lable_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip6_lable_val &= sw->ip6_lable_mask;
+        FIELD_SET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val);
+        FIELD_SET_MASK(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask);
+
+        FIELD_SET(IP6_RUL3_V2, IP6LABEL2V, (sw->ip6_lable_val >> 16));
+        FIELD_SET_MASK(IP6_RUL3_M2, IP6LABEL2M, (sw->ip6_lable_mask >> 16));
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+    {
+        if (0x0 != sw->ip_proto_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_proto_val &= sw->ip_proto_mask;
+        FIELD_SET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val);
+        FIELD_SET_MASK(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+    {
+        if (0x0 != sw->ip_dscp_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_dscp_val &= sw->ip_dscp_mask;
+        FIELD_SET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val);
+        FIELD_SET_MASK(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask);
+    }
+
+    if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+            && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+                || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _isis_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+                                     sw->src_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+            {
+                sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+                sw->src_l4port_val = 0;
+                sw->src_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 0);
+        if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+        {
+            sw->src_l4port_val &= sw->src_l4port_mask;
+            FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 1);
+
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask);
+
+        }
+        else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+        {
+            FIELD_SET(IP6_RUL3_V3, IP6SPORTV, 0);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_val);
+
+        }
+        else
+        {
+            FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, 0xffff);
+        }
+    }
+
+    FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _isis_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+                                     sw->dest_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+            {
+                sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+                sw->dest_l4port_val = 0;
+                sw->dest_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 0);
+        if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+        {
+            sw->dest_l4port_val &= sw->dest_l4port_mask;
+            FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 1);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+        {
+            FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+        {
+            FIELD_SET(IP6_RUL3_V2, IP6DPORTV, 0);
+            FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_val);
+        }
+        else
+        {
+            FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, 0xffff);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+    {
+        if (0x0 != sw->icmp_type_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1);
+
+        sw->icmp_type_val &= sw->icmp_type_mask;
+        FIELD_SET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val);
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))
+    {
+        if (0x0 != sw->icmp_code_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1);
+
+        sw->icmp_code_val &= sw->icmp_code_mask;
+        FIELD_SET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val);
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG))
+    {
+        if (0x0 != sw->tcp_flag_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->tcp_flag_val &= sw->tcp_flag_mask;
+        FIELD_SET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val);
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV6))
+    {
+        if (0x0 != sw->dhcpv6_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->dhcpv6_val &= sw->dhcpv6_mask;
+        FIELD_SET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val);
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_udf_parse(fal_acl_rule_t * sw,
+                         hw_filter_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISIS_UDF_FILTER);
+
+    if (!FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_UDF))
+    {
+        if (FAL_ACL_RULE_UDF == sw->rule_type)
+        {
+            if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+            {
+                FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+            }
+            *b_care = A_TRUE;
+        }
+        return SW_OK;
+    }
+
+    if (ISIS_MAX_UDF_LENGTH < sw->udf_len)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    *b_care = A_TRUE;
+    for (i = 0; i < sw->udf_len; i++)
+    {
+        hw->vlu[3 - i / 4] |=
+            ((sw->udf_mask[i] & sw->udf_val[i]) << (24 - 8 * (i % 4)));
+        hw->msk[3 - i / 4] |= ((sw->udf_mask[i]) << (24 - 8 * i));
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw,
+                       hw_filter_t * hw)
+{
+    fal_pbmp_t des_pts;
+
+    aos_mem_zero(&(hw->act[0]), sizeof (hw->act));
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, TRIGGER_INTR, 1);
+    }
+
+    /* FAL_ACL_ACTION_PERMIT need't process */
+
+    if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU))
+            && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU)))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x3);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_DENY))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x7);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MIRROR))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, MIRR_EN, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, DES_PORT_EN, 1);
+
+        des_pts = (sw->ports >> 3) & 0xf;
+        FIELD_SET_ACTION(ACL_RSLT2, DES_PORT1, des_pts);
+
+        des_pts = sw->ports & 0x7;
+        FIELD_SET_ACTION(ACL_RSLT1, DES_PORT0, des_pts);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_UP))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, PRI_QU_EN, 1);
+        FIELD_SET_ACTION(ACL_RSLT1, PRI_QU, sw->queue);
+    }
+
+    if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+            || (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN)))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, DSCPV, sw->dscp);
+        FIELD_SET_ACTION(ACL_RSLT1, DSCP_REMAP, 1);
+    }
+
+    FIELD_SET_ACTION(ACL_RSLT0, STAGVID, sw->stag_vid);
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, TRANS_SVID_CHG, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI))
+    {
+        FIELD_SET_ACTION(ACL_RSLT0, STAGPRI, sw->stag_pri);
+        FIELD_SET_ACTION(ACL_RSLT1, STAG_PRI_REMAP, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI))
+    {
+        FIELD_SET_ACTION(ACL_RSLT0, STAGDEI, sw->stag_dei);
+        FIELD_SET_ACTION(ACL_RSLT1, STAG_DEI_CHG, 1);
+    }
+
+    FIELD_SET_ACTION(ACL_RSLT0, CTAGVID, sw->ctag_vid);
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, TRANS_CVID_CHG, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI))
+    {
+        FIELD_SET_ACTION(ACL_RSLT0, CTAGPRI, sw->ctag_pri);
+        FIELD_SET_ACTION(ACL_RSLT1, CTAG_PRI_REMAP, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI))
+    {
+        FIELD_SET_ACTION(ACL_RSLT0, CTAGCFI, sw->ctag_cfi);
+        FIELD_SET_ACTION(ACL_RSLT1, CTAG_CFI_CHG, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, LOOK_VID_CHG, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICER_EN))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, POLICER_PTR, sw->policer_ptr);
+        FIELD_SET_ACTION(ACL_RSLT2, POLICER_EN, 1);
+    }
+
+    if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN))
+            && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN)))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR, sw->arp_ptr);
+        FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR_EN, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr);
+        FIELD_SET_ACTION(ACL_RSLT1, WCMP_EN, 1);
+        FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR_EN, 1);
+    }
+
+    FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x0);
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN))
+    {
+        if (FAL_ACL_POLICY_ROUTE == sw->policy_fwd)
+        {
+            return SW_NOT_SUPPORTED;
+        }
+        else if (FAL_ACL_POLICY_SNAT == sw->policy_fwd)
+        {
+            FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x1);
+        }
+        else if (FAL_ACL_POLICY_DNAT == sw->policy_fwd)
+        {
+            FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x2);
+        }
+        else if (FAL_ACL_POLICY_RESERVE == sw->policy_fwd)
+        {
+            FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x3);
+        }
+        else
+        {
+            return SW_BAD_PARAM;
+        }
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, EG_BYPASS, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, TRIGGER_INTR, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_bmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t mask_en;
+
+    /* destnation mac address */
+    FIELD_GET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]);
+    FIELD_GET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]);
+    FIELD_GET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]);
+    FIELD_GET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]);
+    FIELD_GET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]);
+    FIELD_GET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]);
+
+    FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]);
+    FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]);
+    FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]);
+    FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]);
+    FIELD_GET_MASK(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]);
+    FIELD_GET_MASK(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]);
+    if (A_FALSE == _isis_acl_zero_addr(sw->dest_mac_mask))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+    }
+
+    /* source mac address */
+    FIELD_GET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]);
+    FIELD_GET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]);
+    FIELD_GET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]);
+    FIELD_GET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+    FIELD_GET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+    FIELD_GET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+
+    FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]);
+    FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]);
+    FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]);
+    FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+    FIELD_GET_MASK(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+    FIELD_GET_MASK(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+    if (A_FALSE == _isis_acl_zero_addr(sw->src_mac_mask))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+    }
+
+    /* ethernet type */
+    FIELD_GET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+    FIELD_GET_MASK(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+    if (0x0 != sw->ethtype_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+    }
+
+    /* packet tagged */
+    FIELD_GET_MASK(MAC_RUL_M4, TAGGEDV, sw->tagged_val);
+    FIELD_GET_MASK(MAC_RUL_M4, TAGGEDM, sw->tagged_mask);
+    if (0x0 != sw->tagged_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED);
+    }
+
+    /* vlan priority */
+    FIELD_GET(MAC_RUL_V3, VLANPRIV, sw->up_val);
+    FIELD_GET_MASK(MAC_RUL_M3, VLANPRIM, sw->up_mask);
+    if (0x0 != sw->up_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_UP);
+    }
+
+    /* vlanid */
+    FIELD_GET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+    FIELD_GET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask);
+    FIELD_GET_MASK(MAC_RUL_M4, VIDMSK, mask_en);
+    if (mask_en)
+    {
+        sw->vid_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->vid_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _isis_acl_field_care(sw->vid_op, (a_uint32_t) sw->vid_val,
+                                 (a_uint32_t) sw->vid_mask, 0xfff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_VID);
+    }
+
+    /* vlan cfi */
+    FIELD_GET(MAC_RUL_V3, VLANCFIV, sw->cfi_val);
+    FIELD_GET_MASK(MAC_RUL_M3, VLANCFIM, sw->cfi_mask);
+    if (0x0 != sw->cfi_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CFI);
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+    if (mask_en)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ehmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t i, mask_en, data;
+
+    FIELD_GET(EHMAC_RUL_V3, DA_EN, data);
+    if (data)
+    {
+        for (i = 2; i < 6; i++)
+        {
+            sw->dest_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff;
+            sw->dest_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff;
+        }
+
+        for (i = 0; i < 2; i++)
+        {
+            sw->dest_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff;
+            sw->dest_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff;
+        }
+
+        if (A_FALSE == _isis_acl_zero_addr(sw->dest_mac_mask))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+        }
+
+        FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+        FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+        FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+
+        FIELD_GET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+        FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+        FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+
+        if (A_FALSE == _isis_acl_zero_addr(sw->src_mac_mask))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+        }
+    }
+    else
+    {
+        for (i = 2; i < 6; i++)
+        {
+            sw->src_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff;
+            sw->src_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff;
+        }
+
+        for (i = 0; i < 2; i++)
+        {
+            sw->src_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff;
+            sw->src_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff;
+        }
+
+        if (A_FALSE == _isis_acl_zero_addr(sw->src_mac_mask))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+        }
+
+        FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]);
+        FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]);
+        FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]);
+
+        FIELD_GET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]);
+        FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]);
+        FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]);
+        if (A_FALSE == _isis_acl_zero_addr(sw->dest_mac_mask))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+        }
+    }
+
+    /* ethernet type */
+    FIELD_GET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+    FIELD_GET_MASK(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+    if (0x0 != sw->ethtype_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+    }
+
+    /* packet stagged */
+    FIELD_GET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val);
+    FIELD_GET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask);
+    if (0x0 != sw->stagged_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED);
+    }
+
+    /* stag vid */
+    FIELD_GET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+    FIELD_GET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask);
+    FIELD_GET(EHMAC_RUL_V3, SVIDMSK, mask_en);
+    if (mask_en)
+    {
+        sw->stag_vid_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->stag_vid_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _isis_acl_field_care(sw->stag_vid_op, (a_uint32_t) sw->stag_vid_val,
+                                 (a_uint32_t) sw->stag_vid_mask, 0xfff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID);
+    }
+
+    /* stag priority */
+    FIELD_GET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val);
+    FIELD_GET_MASK(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask);
+    if (0x0 != sw->stag_pri_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI);
+    }
+
+    /* stag dei */
+    FIELD_GET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val);
+    FIELD_GET_MASK(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask);
+    if (0x0 != sw->stag_dei_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI);
+    }
+
+    /* packet ctagged */
+    FIELD_GET_MASK(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val);
+    FIELD_GET_MASK(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask);
+    if (0x0 != sw->ctagged_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED);
+    }
+
+    /* ctag vid */
+    FIELD_GET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+    FIELD_GET(EHMAC_RUL_V3, CTAG_VIDHV, data);
+    sw->ctag_vid_val |= (data << 8);
+    FIELD_GET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask);
+    FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, data);
+    sw->ctag_vid_mask |= (data << 8);
+
+    FIELD_GET_MASK(EHMAC_RUL_M4, CVIDMSK, mask_en);
+    if (mask_en)
+    {
+        sw->ctag_vid_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->ctag_vid_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _isis_acl_field_care(sw->ctag_vid_op, (a_uint32_t) sw->ctag_vid_val,
+                                 (a_uint32_t) sw->ctag_vid_mask, 0xfff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID);
+    }
+
+    /* ctag priority */
+    FIELD_GET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val);
+    FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask);
+    if (0x0 != sw->ctag_pri_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI);
+    }
+
+    /* ctag dei */
+    FIELD_GET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val);
+    FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask);
+    if (0x0 != sw->ctag_cfi_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI);
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+    if (mask_en)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ip4_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t mask_en, icmp_en;
+
+    sw->dest_ip4_val = hw->vlu[0];
+    sw->dest_ip4_mask = hw->msk[0];
+    if (0x0 != sw->dest_ip4_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_DIP);
+    }
+
+    sw->src_ip4_val = hw->vlu[1];
+    sw->src_ip4_mask = hw->msk[1];
+    if (0x0 != sw->src_ip4_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_SIP);
+    }
+
+    FIELD_GET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val);
+    FIELD_GET_MASK(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask);
+    if (0x0 != sw->ip_proto_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+    }
+
+    FIELD_GET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val);
+    FIELD_GET_MASK(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask);
+    if (0x0 != sw->ip_dscp_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+    }
+
+    FIELD_GET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+    FIELD_GET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask);
+    FIELD_GET_MASK(IP4_RUL_M3, IP4DPORTM_EN, mask_en);
+    if (mask_en)
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _isis_acl_field_care(sw->dest_l4port_op,
+                                 (a_uint32_t) sw->dest_l4port_val,
+                                 (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+    else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+
+    FIELD_GET(IP4_RUL_V3, ICMP_EN, icmp_en);
+    if (icmp_en)
+    {
+        FIELD_GET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val);
+        FIELD_GET_MASK(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask);
+        if (0x0 != sw->icmp_type_mask)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE);
+        }
+
+        FIELD_GET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val);
+        FIELD_GET_MASK(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask);
+        if (0x0 != sw->icmp_code_mask)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE);
+        }
+    }
+    else
+    {
+        FIELD_GET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+        FIELD_GET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask);
+        FIELD_GET_MASK(IP4_RUL_M3, IP4SPORTM_EN, mask_en);
+        if (mask_en)
+        {
+            sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+        }
+        else
+        {
+            sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+        }
+
+        if (A_TRUE ==
+                _isis_acl_field_care(sw->src_l4port_op,
+                                     (a_uint32_t) sw->src_l4port_val,
+                                     (a_uint32_t) sw->src_l4port_mask, 0xffff))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+        }
+    }
+
+    FIELD_GET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val);
+    FIELD_GET_MASK(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask);
+    if (0x0 != sw->tcp_flag_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG);
+    }
+
+    FIELD_GET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val);
+    FIELD_GET_MASK(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask);
+    if (0x0 != sw->ripv1_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_RIPV1);
+    }
+
+    FIELD_GET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val);
+    FIELD_GET_MASK(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask);
+    if (0x0 != sw->dhcpv4_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV4);
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+    if (mask_en)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 4; i++)
+    {
+        sw->dest_ip6_val.ul[i] = hw->vlu[3 - i];
+        sw->dest_ip6_mask.ul[i] = hw->msk[3 - i];
+        if (0x0 != sw->dest_ip6_mask.ul[i])
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_DIP);
+        }
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, i);
+    if (i)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 4; i++)
+    {
+        sw->src_ip6_val.ul[i] = hw->vlu[3 - i];
+        sw->src_ip6_mask.ul[i] = hw->msk[3 - i];
+        if (0x0 != sw->src_ip6_mask.ul[i])
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_SIP);
+        }
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, i);
+    if (i)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t mask_en, icmp6_en, tmp;
+
+    FIELD_GET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val);
+    FIELD_GET_MASK(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask);
+    if (0x0 != sw->ip_proto_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+    }
+
+    FIELD_GET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val);
+    FIELD_GET_MASK(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask);
+    if (0x0 != sw->ip_dscp_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+    }
+
+    FIELD_GET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+    FIELD_GET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask);
+    FIELD_GET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, mask_en);
+    if (mask_en)
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _isis_acl_field_care(sw->dest_l4port_op,
+                                 (a_uint32_t) sw->dest_l4port_val,
+                                 (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+    else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+
+    FIELD_GET(IP6_RUL3_V3, ICMP6_EN, icmp6_en);
+    if (icmp6_en)
+    {
+        FIELD_GET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val);
+        FIELD_GET_MASK(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask);
+        if (0x0 != sw->icmp_type_mask)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE);
+        }
+
+        FIELD_GET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val);
+        FIELD_GET_MASK(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask);
+        if (0x0 != sw->icmp_code_mask)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE);
+        }
+    }
+    else
+    {
+        FIELD_GET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+        FIELD_GET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask);
+        FIELD_GET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, mask_en);
+        if (mask_en)
+        {
+            sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+        }
+        else
+        {
+            sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+        }
+
+        if (A_TRUE ==
+                _isis_acl_field_care(sw->src_l4port_op,
+                                     (a_uint32_t) sw->src_l4port_val,
+                                     (a_uint32_t) sw->src_l4port_mask, 0xffff))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+        }
+    }
+
+    FIELD_GET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val);
+    FIELD_GET_MASK(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask);
+
+    FIELD_GET(IP6_RUL3_V2, IP6LABEL2V, tmp);
+    sw->ip6_lable_val |= (tmp << 16);
+    FIELD_GET_MASK(IP6_RUL3_M2, IP6LABEL2M, tmp);
+    sw->ip6_lable_mask |= (tmp << 16);
+
+    if (0x0 != sw->ip6_lable_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL);
+    }
+
+    FIELD_GET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val);
+    FIELD_GET_MASK(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask);
+    if (0x0 != sw->tcp_flag_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG);
+    }
+
+    FIELD_GET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val);
+    FIELD_GET_MASK(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask);
+    if (0x0 != sw->dhcpv6_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV6);
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+    if (mask_en)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_udf_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t i;
+
+    FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_UDF);
+
+    /* for ISIS UDF type, length and offset no meanging in rules, just set default value */
+    sw->udf_type = FAL_ACL_UDF_TYPE_L2;
+    sw->udf_len = 16;
+    sw->udf_offset = 0;
+
+    for (i = 0; i < ISIS_MAX_UDF_LENGTH; i++)
+    {
+        sw->udf_val[i] = ((hw->vlu[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff;
+        sw->udf_mask[i] = ((hw->msk[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff;
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, i);
+    if (i)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_action_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t data;
+
+    sw->action_flg = 0;
+
+    FIELD_GET_ACTION(ACL_RSLT2, DES_PORT_EN, data);
+    if (1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REDPT);
+        FIELD_GET_ACTION(ACL_RSLT1, DES_PORT0, sw->ports);
+        FIELD_GET_ACTION(ACL_RSLT2, DES_PORT1, data);
+        sw->ports |= (data << 3);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT2, FWD_CMD, data);
+    if (0x7 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_DENY);
+    }
+    else if (0x3 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_RDTCPU);
+    }
+    else if (0x1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_CPYCPU);
+    }
+    else
+    {
+        /* need't set permit action */
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT2, MIRR_EN, data);
+    if (1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MIRROR);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, PRI_QU_EN, data);
+    if (1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE);
+        FIELD_GET_ACTION(ACL_RSLT1, PRI_QU, sw->queue);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, DSCP_REMAP, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP);
+        FIELD_GET_ACTION(ACL_RSLT1, DSCPV, sw->dscp);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT0, STAGVID, sw->stag_vid);
+
+    FIELD_GET_ACTION(ACL_RSLT1, TRANS_SVID_CHG, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, STAG_PRI_REMAP, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI);
+        FIELD_GET_ACTION(ACL_RSLT0, STAGPRI, sw->stag_pri);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, STAG_DEI_CHG, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI);
+        FIELD_GET_ACTION(ACL_RSLT0, STAGDEI, sw->stag_dei);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT0, CTAGVID, sw->ctag_vid);
+
+    FIELD_GET_ACTION(ACL_RSLT1, TRANS_CVID_CHG, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, CTAG_PRI_REMAP, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI);
+        FIELD_GET_ACTION(ACL_RSLT0, CTAGPRI, sw->ctag_pri);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, CTAG_CFI_CHG, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI);
+        FIELD_GET_ACTION(ACL_RSLT0, CTAGCFI, sw->ctag_cfi);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, LOOK_VID_CHG, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT2, POLICER_EN, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICER_EN);
+        FIELD_GET_ACTION(ACL_RSLT2, POLICER_PTR, sw->policer_ptr);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR_EN, data);
+    if (data)
+    {
+        FIELD_GET_ACTION(ACL_RSLT1, WCMP_EN, data);
+        if (data)
+        {
+            FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_WCMP_EN);
+            FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr);
+        }
+        else
+        {
+            FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_ARP_EN);
+            FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR, sw->arp_ptr);
+        }
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, FORCE_L3_MODE, data);
+    if ((0 != data) && (3 != data))
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN);
+        if (0x1 == data)
+        {
+            sw->policy_fwd = FAL_ACL_POLICY_SNAT;
+        }
+        else
+        {
+            sw->policy_fwd = FAL_ACL_POLICY_DNAT;
+        }
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT2, EG_BYPASS, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT2, TRIGGER_INTR, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR);
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+_isis_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+                        isis_acl_rule_t * hw_rule_snap, a_uint32_t * idx)
+{
+    sw_error_t rv;
+    a_uint32_t tmp_idx, i, b_rule[7] = { 0 };
+    parse_func_t ptr[7] = { NULL };
+    a_bool_t b_care, b_mac, eh_mac;
+
+    rv = _isis_acl_action_parse(dev_id, sw, &(hw_rule_snap[*idx].filter));
+    SW_RTN_ON_ERROR(rv);
+
+    ptr[0] = _isis_acl_rule_udf_parse;
+    _isis_acl_rule_mac_preparse(sw, &b_mac, &eh_mac);
+
+    /* ehmac rule must be parsed bofore mac rule.
+       it's important for reparse process */
+    if (A_TRUE == eh_mac)
+    {
+        ptr[1] = _isis_acl_rule_ehmac_parse;
+    }
+
+    if (A_TRUE == b_mac)
+    {
+        ptr[2] = _isis_acl_rule_bmac_parse;
+    }
+
+    if ((A_FALSE == b_mac) && (A_FALSE == eh_mac))
+    {
+        ptr[2] = _isis_acl_rule_bmac_parse;
+    }
+
+    if (FAL_ACL_RULE_MAC == sw->rule_type)
+    {
+    }
+    else if (FAL_ACL_RULE_IP4 == sw->rule_type)
+    {
+        ptr[3] = _isis_acl_rule_ip4_parse;
+    }
+    else if (FAL_ACL_RULE_IP6 == sw->rule_type)
+    {
+        ptr[4] = _isis_acl_rule_ip6r1_parse;
+        ptr[5] = _isis_acl_rule_ip6r2_parse;
+        ptr[6] = _isis_acl_rule_ip6r3_parse;
+    }
+    else if (FAL_ACL_RULE_UDF == sw->rule_type)
+    {
+        ptr[1] = NULL;
+        ptr[2] = NULL;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    tmp_idx = *idx;
+    for (i = 0; i < 7; i++)
+    {
+        if (ptr[i])
+        {
+            if (ISIS_HW_RULE_TMP_CNT <= tmp_idx)
+            {
+                return SW_NO_RESOURCE;
+            }
+
+            rv = ptr[i] (sw, &(hw_rule_snap[tmp_idx].filter), &b_care);
+            SW_RTN_ON_ERROR(rv);
+            if (A_TRUE == b_care)
+            {
+                tmp_idx++;
+                b_rule[i] = 1;
+            }
+        }
+    }
+
+    if (FAL_ACL_RULE_IP6 == sw->rule_type)
+    {
+        if ((!b_rule[4]) && (!b_rule[5]) && (!b_rule[6]))
+        {
+            tmp_idx++;
+        }
+    }
+
+    if (FAL_ACL_RULE_IP4 == sw->rule_type)
+    {
+        if (!b_rule[3])
+        {
+            tmp_idx++;
+        }
+    }
+
+    if (tmp_idx == *idx)
+    {
+        /* set type start & end */
+        SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND,
+                            (hw_rule_snap[*idx].filter.msk[4]));
+        (*idx)++;
+    }
+    else
+    {
+        if (1 == (tmp_idx - *idx))
+        {
+            if (FAL_ACL_COMBINED_START == sw->combined)
+            {
+                SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START,
+                                    (hw_rule_snap[*idx].filter.msk[4]));
+            }
+            else if (FAL_ACL_COMBINED_CONTINUE == sw->combined)
+            {
+                SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE,
+                                    (hw_rule_snap[*idx].filter.msk[4]));
+            }
+            else if (FAL_ACL_COMBINED_END == sw->combined)
+            {
+                SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END,
+                                    (hw_rule_snap[*idx].filter.msk[4]));
+            }
+            else
+            {
+                SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND,
+                                    (hw_rule_snap[*idx].filter.msk[4]));
+            }
+        }
+        else
+        {
+            for (i = *idx; i < tmp_idx; i++)
+            {
+                if (i == *idx)
+                {
+                    SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START,
+                                        (hw_rule_snap[i].filter.msk[4]));
+                }
+                else if (i == (tmp_idx - 1))
+                {
+                    SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END,
+                                        (hw_rule_snap[i].filter.msk[4]));
+                }
+                else
+                {
+                    SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE,
+                                        (hw_rule_snap[i].filter.msk[4]));
+                }
+                aos_mem_copy(&(hw_rule_snap[i].filter.act[0]),
+                             &(hw_rule_snap[*idx].filter.act[0]),
+                             sizeof (hw_rule_snap[*idx].filter.act));
+            }
+        }
+        *idx = tmp_idx;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+_isis_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+                        isis_acl_rule_t * hw_rule_snap, a_uint32_t idx,
+                        a_uint32_t ent_nr)
+{
+    a_bool_t b_mac = A_FALSE, b_ip4 = A_FALSE, b_ip6 = A_FALSE;
+    sw_error_t rv;
+    a_uint32_t i, flt_typ;
+    hw_filter_t *hw;
+
+    rv = _isis_acl_rule_action_reparse(sw, &(hw_rule_snap[idx].filter));
+    SW_RTN_ON_ERROR(rv);
+
+    sw->rule_type = FAL_ACL_RULE_UDF;
+    for (i = 0; i < ent_nr; i++)
+    {
+        hw = &(hw_rule_snap[idx + i].filter);
+        FIELD_GET_MASK(MAC_RUL_M4, RULE_TYP, flt_typ);
+
+        if (ISIS_UDF_FILTER == flt_typ)
+        {
+            rv = _isis_acl_rule_udf_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+        }
+        else if (ISIS_MAC_FILTER == flt_typ)
+        {
+            rv = _isis_acl_rule_bmac_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_mac = A_TRUE;
+        }
+        else if (ISIS_EHMAC_FILTER == flt_typ)
+        {
+            rv = _isis_acl_rule_ehmac_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_mac = A_TRUE;
+        }
+        else if (ISIS_IP4_FILTER == flt_typ)
+        {
+            rv = _isis_acl_rule_ip4_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_ip4 = A_TRUE;
+        }
+        else if (ISIS_IP6R1_FILTER == flt_typ)
+        {
+            rv = _isis_acl_rule_ip6r1_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_ip6 = A_TRUE;
+        }
+        else if (ISIS_IP6R2_FILTER == flt_typ)
+        {
+            rv = _isis_acl_rule_ip6r2_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_ip6 = A_TRUE;
+        }
+        else if (ISIS_IP6R3_FILTER == flt_typ)
+        {
+            rv = _isis_acl_rule_ip6r3_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_ip6 = A_TRUE;
+        }
+        else
+        {
+            /* ignore fill gap filters */
+        }
+    }
+
+    if (A_TRUE == b_mac)
+    {
+        sw->rule_type = FAL_ACL_RULE_MAC;
+    }
+
+    if (A_TRUE == b_ip4)
+    {
+        sw->rule_type = FAL_ACL_RULE_IP4;
+    }
+
+    if (A_TRUE == b_ip6)
+    {
+        sw->rule_type = FAL_ACL_RULE_IP6;
+    }
+
+    return SW_OK;
+}
diff --git a/qca-ssdk/src/hsl/isis/isis_acl_prv.h b/qca-ssdk/src/hsl/isis/isis_acl_prv.h
new file mode 100755
index 0000000..f6b9c7f
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_acl_prv.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+typedef struct
+{
+    a_uint8_t  status;
+    a_uint8_t  list_id;
+    a_uint8_t  list_pri;
+    a_uint8_t  rule_nr;
+    fal_pbmp_t bind_pts;
+} isis_acl_list_t;
+
+
+typedef struct
+{
+    a_uint32_t  vlu[5];
+    a_uint32_t  msk[5];
+    a_uint32_t  act[3];
+} hw_filter_t;
+
+
+typedef struct
+{
+    a_uint8_t   status;
+    a_uint8_t   list_id;
+    a_uint8_t   list_pri;
+    a_uint8_t   rule_id;
+    hw_filter_t filter;
+} isis_acl_rule_t;
+
+
+#define ENT_USED                0x1
+#define ENT_TMP                 0x2
+#define ENT_DEACTIVE            0x4
+
+#define FLT_START               0x0
+#define FLT_CONTINUE            0x1
+#define FLT_END                 0x2
+#define FLT_STARTEND            0x3
+
+
+#define ISIS_MAC_FILTER         1
+#define ISIS_IP4_FILTER         2
+#define ISIS_IP6R1_FILTER       3
+#define ISIS_IP6R2_FILTER       4
+#define ISIS_IP6R3_FILTER       5
+#define ISIS_UDF_FILTER         6
+#define ISIS_EHMAC_FILTER       7
+
+
+#define ISIS_MAX_UDF_OFFSET     31
+#define ISIS_MAX_UDF_LENGTH     16
+
+
+#define ISIS_FILTER_VLU_OP      0x0
+#define ISIS_FILTER_MSK_OP      0x1
+#define ISIS_FILTER_ACT_OP      0x2
+
+
+
+//#define ISIS_MAX_FILTER         8
+#define ISIS_MAX_FILTER         96
+#define ISIS_RULE_FUNC_ADDR     0x0400
+#define ISIS_HW_RULE_TMP_CNT    (ISIS_MAX_FILTER + 4)
+
+#define ISIS_MAX_LIST_ID        255
+#define ISIS_MAX_LIST_PRI       255
+
+#define ISIS_UDF_MAX_LENGTH     15
+#define ISIS_UDF_MAX_OFFSET     31
+
+#define WIN_RULE_CTL0_ADDR      0x218
+#define WIN_RULE_CTL1_ADDR      0x234
+
+
+#define ISIS_FILTER_VLU_ADDR    0x58000
+#define ISIS_FILTER_MSK_ADDR    0x59000
+#define ISIS_FILTER_ACT_ADDR    0x5a000
+
+
+#define FIELD_SET(reg, field, val) \
+    SW_REG_SET_BY_FIELD_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define FIELD_GET(reg, field, val) \
+    SW_FIELD_GET_BY_REG_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define FIELD_SET_MASK(reg, field, val) \
+    SW_REG_SET_BY_FIELD_U32(hw->msk[reg-5], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define FIELD_GET_MASK(reg, field, val) \
+    SW_FIELD_GET_BY_REG_U32(hw->msk[reg-5], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define FIELD_SET_ACTION(reg, field, val) \
+    SW_REG_SET_BY_FIELD_U32(hw->act[reg-10], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define FIELD_GET_ACTION(reg, field, val) \
+    SW_FIELD_GET_BY_REG_U32(hw->act[reg-10], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+sw_error_t
+_isis_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw, isis_acl_rule_t * hw_filter_snap, a_uint32_t * idx);
+
+
+sw_error_t
+_isis_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw, isis_acl_rule_t * hw_filter_snap, a_uint32_t idx, a_uint32_t ent_nr);
+
+
diff --git a/qca-ssdk/src/hsl/isis/isis_cosmap.c b/qca-ssdk/src/hsl/isis/isis_cosmap.c
new file mode 100755
index 0000000..4cecb02
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_cosmap.c
@@ -0,0 +1,637 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_cosmap ISIS_COSMAP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_cosmap.h"
+#include "isis_reg.h"
+
+#define ISIS_MAX_DSCP                63
+#define ISIS_MAX_UP                  7
+#define ISIS_MAX_PRI                 7
+#define ISIS_MAX_DP                  1
+#define ISIS_MAX_QUEUE               3
+#define ISIS_MAX_EH_QUEUE            5
+
+#define ISIS_DSCP_TO_PRI             0
+#define ISIS_DSCP_TO_DP              1
+#define ISIS_UP_TO_PRI               2
+#define ISIS_UP_TO_DP                3
+
+#define ISIS_EGRESS_REAMRK_ADDR      0x5ae00
+#define ISIS_EGRESS_REAMRK_NUM       16
+
+static sw_error_t
+_isis_cosmap_dscp_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode,
+                                a_uint32_t dscp, a_uint32_t val)
+{
+    sw_error_t rv;
+    a_uint32_t index, data = 0;
+
+    if (ISIS_MAX_DSCP < dscp)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    index = dscp >> 3;
+    HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (ISIS_DSCP_TO_PRI == mode)
+    {
+        if (ISIS_MAX_PRI < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x7 << ((dscp & 0x7) << 2)));
+        data |= (val << ((dscp & 0x7) << 2));
+    }
+    else
+    {
+        if (ISIS_MAX_DP < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x1 << (((dscp & 0x7) << 2) + 3)));
+        data |= (val << (((dscp & 0x7) << 2) + 3));
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_cosmap_dscp_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode,
+                                a_uint32_t dscp, a_uint32_t * val)
+{
+    sw_error_t rv;
+    a_uint32_t index, data = 0;
+
+    if (ISIS_MAX_DSCP < dscp)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    index = dscp >> 3;
+    HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (data >> ((dscp & 0x7) << 2)) & 0xf;
+    if (ISIS_DSCP_TO_PRI == mode)
+    {
+        *val = data & 0x7;
+    }
+    else
+    {
+        *val = (data & 0x8) >> 3;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_cosmap_up_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up,
+                              a_uint32_t val)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (ISIS_MAX_UP < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (ISIS_UP_TO_PRI == mode)
+    {
+        if (ISIS_MAX_PRI < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x7 << (up << 2)));
+        data |= (val << (up << 2));
+    }
+    else
+    {
+        if (ISIS_MAX_DP < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x1 << ((up << 2) + 3)));
+        data |= (val << ((up << 2) + 3));
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_cosmap_up_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up,
+                              a_uint32_t * val)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (ISIS_MAX_UP < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (data >> (up << 2)) & 0xf;
+
+    if (ISIS_UP_TO_PRI == mode)
+    {
+        *val = (data & 0x7);
+    }
+    else
+    {
+        *val = (data & 0x8) >> 3;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+                              a_uint32_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if ((ISIS_MAX_PRI < pri) || (ISIS_MAX_QUEUE < queue))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0x3 << (pri << 2)));
+    data |= (queue << (pri << 2));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+                              a_uint32_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (ISIS_MAX_PRI < pri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *queue = (data >> (pri << 2)) & 0x3;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+                                a_uint32_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if ((ISIS_MAX_PRI < pri) || (ISIS_MAX_EH_QUEUE < queue))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0x7 << (pri << 2)));
+    data |= (queue << (pri << 2));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+                                a_uint32_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t data= 0;
+
+    if (ISIS_MAX_PRI < pri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *queue = (data >> (pri << 2)) & 0x7;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+                               fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+    a_uint32_t data, addr;
+
+    if (ISIS_EGRESS_REAMRK_NUM <= tbl_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = (tbl->y_up & 0x7)
+           | ((tbl->g_up & 0x7) << 4)
+           | ((tbl->y_dscp & 0x3f) << 8)
+           | ((tbl->g_dscp & 0x3f) << 16)
+           | ((tbl->remark_dscp & 0x1) << 23)
+           | ((tbl->remark_up & 0x1) << 22);
+
+    addr = ISIS_EGRESS_REAMRK_ADDR + (tbl_id << 2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+                               fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, addr;
+
+    if (ISIS_EGRESS_REAMRK_NUM <= tbl_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(tbl, sizeof (fal_egress_remark_table_t));
+
+    addr = ISIS_EGRESS_REAMRK_ADDR + (tbl_id << 2);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data & (0x1 << 23))
+    {
+        tbl->remark_dscp = A_TRUE;
+        tbl->y_dscp = (data >> 8) & 0x3f;
+        tbl->g_dscp = (data >> 16) & 0x3f;
+    }
+
+    if (data & (0x1 << 22))
+    {
+        tbl->remark_up = A_TRUE;
+        tbl->y_up = data & 0x7;
+        tbl->g_up = (data >> 4) & 0x7;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set dscp to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cosmap_dscp_to_pri_dp_set(dev_id, ISIS_DSCP_TO_PRI, dscp, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dscp to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+                            a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cosmap_dscp_to_pri_dp_get(dev_id, ISIS_DSCP_TO_PRI, dscp, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dscp to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cosmap_dscp_to_pri_dp_set(dev_id, ISIS_DSCP_TO_DP, dscp, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dscp to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cosmap_dscp_to_pri_dp_get(dev_id, ISIS_DSCP_TO_DP, dscp, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dot1p to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cosmap_up_to_pri_dp_set(dev_id, ISIS_UP_TO_PRI, up, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dot1p to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cosmap_up_to_pri_dp_get(dev_id, ISIS_UP_TO_PRI, up, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dot1p to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cosmap_up_to_pri_dp_set(dev_id, ISIS_UP_TO_DP, up, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dot1p to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cosmap_up_to_pri_dp_get(dev_id, ISIS_UP_TO_DP, up, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 1/2/3/4 which have four egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+                             a_uint32_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cosmap_pri_to_queue_set(dev_id, pri, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 1/2/3/4 which have four egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+                             a_uint32_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cosmap_pri_to_queue_get(dev_id, pri, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 0/5/6 which have six egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+                               a_uint32_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cosmap_pri_to_ehqueue_set(dev_id, pri, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 0/5/6 which have six egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+                               a_uint32_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cosmap_pri_to_ehqueue_get(dev_id, pri, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress queue based CoS remap table on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] tbl_id CoS remap table id
+ * @param[in] tbl CoS remap table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+                              fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cosmap_egress_remark_set(dev_id, tbl_id, tbl);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress queue based CoS remap table on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] tbl_id CoS remap table id
+ * @param[out] tbl CoS remap table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+                              fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cosmap_egress_remark_get(dev_id, tbl_id, tbl);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_cosmap_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->cosmap_dscp_to_pri_set = isis_cosmap_dscp_to_pri_set;
+        p_api->cosmap_dscp_to_pri_get = isis_cosmap_dscp_to_pri_get;
+        p_api->cosmap_dscp_to_dp_set = isis_cosmap_dscp_to_dp_set;
+        p_api->cosmap_dscp_to_dp_get = isis_cosmap_dscp_to_dp_get;
+        p_api->cosmap_up_to_pri_set = isis_cosmap_up_to_pri_set;
+        p_api->cosmap_up_to_pri_get = isis_cosmap_up_to_pri_get;
+        p_api->cosmap_up_to_dp_set = isis_cosmap_up_to_dp_set;
+        p_api->cosmap_up_to_dp_get = isis_cosmap_up_to_dp_get;
+        p_api->cosmap_pri_to_queue_set = isis_cosmap_pri_to_queue_set;
+        p_api->cosmap_pri_to_queue_get = isis_cosmap_pri_to_queue_get;
+        p_api->cosmap_pri_to_ehqueue_set = isis_cosmap_pri_to_ehqueue_set;
+        p_api->cosmap_pri_to_ehqueue_get = isis_cosmap_pri_to_ehqueue_get;
+        p_api->cosmap_egress_remark_set = isis_cosmap_egress_remark_set;
+        p_api->cosmap_egress_remark_get = isis_cosmap_egress_remark_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isis/isis_fdb.c b/qca-ssdk/src/hsl/isis/isis_fdb.c
new file mode 100755
index 0000000..da21f22
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_fdb.c
@@ -0,0 +1,2217 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_fdb ISIS_FDB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_fdb.h"
+#include "isis_reg.h"
+
+#define ARL_FLUSH_ALL             1
+#define ARL_LOAD_ENTRY            2
+#define ARL_PURGE_ENTRY           3
+#define ARL_FLUSH_ALL_UNLOCK      4
+#define ARL_FLUSH_PORT_UNICAST    5
+#define ARL_NEXT_ENTRY            6
+#define ARL_FIND_ENTRY            7
+#define ARL_TRANSFER_ENTRY        8
+
+#define ARL_FIRST_ENTRY           1001
+#define ARL_FLUSH_PORT_NO_STATIC  1002
+#define ARL_FLUSH_PORT_AND_STATIC 1003
+
+#define ISIS_MAX_FID                   4095
+#define ISIS_MAX_LEARN_LIMIT_CNT       2047
+#define ISIS_MAX_PORT_LEARN_LIMIT_CNT  1023
+
+static sw_error_t
+_isis_wl_feature_check(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (S17_DEVICE_ID == entry)
+    {
+        return SW_OK;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+}
+
+static a_bool_t
+_isis_fdb_is_zeroaddr(fal_mac_addr_t addr)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 6; i++)
+    {
+        if (addr.uc[i])
+        {
+            return A_FALSE;
+        }
+    }
+
+    return A_TRUE;
+}
+
+static void
+_isis_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1)
+{
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1);
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE2, addr.uc[2], *reg0);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE3, addr.uc[3], *reg0);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0);
+
+    return;
+}
+
+static sw_error_t
+_isis_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry,
+                   a_uint32_t reg[])
+{
+    a_uint32_t port;
+    sw_error_t rv;
+
+    if (A_TRUE == entry->white_list_en)
+    {
+        rv = _isis_wl_feature_check(dev_id);
+        SW_RTN_ON_ERROR(rv);
+
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, WL_EN, 1, reg[2]);
+    }
+
+    if (FAL_SVL_FID == entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]);
+    }
+    else if (ISIS_MAX_FID >= entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == entry->portmap_en)
+    {
+        if (A_TRUE !=
+                hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+
+        port = 0x1UL << entry->port.id;
+    }
+    else
+    {
+        if (A_FALSE ==
+                hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+
+        port = entry->port.map;
+    }
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg[1]);
+
+    if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]);
+    }
+    else if (FAL_MAC_FRWRD != entry->dacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->leaky_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]);
+    }
+
+    if (A_TRUE == entry->static_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]);
+    }
+
+    if (FAL_MAC_DROP == entry->sacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, SA_DROP_EN, 1, reg[1]);
+    }
+    else if (FAL_MAC_FRWRD != entry->sacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->mirror_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, MIRROR_EN, 1, reg[1]);
+    }
+
+    if (A_TRUE == entry->cross_pt_state)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 1, reg[1]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 0, reg[1]);
+    }
+
+    if (A_TRUE == entry->da_pri_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 1, reg[1]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI, (entry->da_queue & 0x7),
+                            reg[1]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 0, reg[1]);
+    }
+
+    _isis_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+    return SW_OK;
+}
+
+static void
+_isis_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+    a_uint32_t i, data;
+
+    aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_SVL_EN, data, reg[1]);
+    if (data)
+    {
+        entry->fid = FAL_SVL_FID;
+    }
+    else
+    {
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_VID, data, reg[2]);
+        entry->fid = data;
+    }
+
+    entry->dacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_CPY_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    entry->sacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, SA_DROP_EN, data, reg[1]);
+    if (1 == data)
+    {
+        entry->sacmd = FAL_MAC_DROP;
+    }
+
+    entry->leaky_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->leaky_en = A_TRUE;
+    }
+
+    entry->static_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]);
+    if (0xf == data)
+    {
+        entry->static_en = A_TRUE;
+    }
+
+    entry->mirror_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, MIRROR_EN, data, reg[1]);
+    if (1 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+
+    entry->da_pri_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI_EN, data, reg[1]);
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI, data, reg[1]);
+        entry->da_pri_en = A_TRUE;
+        entry->da_queue = data & 0x7;
+    }
+
+    entry->cross_pt_state = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, CROSS_PT, data, reg[1]);
+    if (1 == data)
+    {
+        entry->cross_pt_state = A_TRUE;
+    }
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, data, reg[1]);
+    entry->portmap_en = A_TRUE;
+    entry->port.map = data;
+
+    for (i = 2; i < 6; i++)
+    {
+        entry->addr.uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff;
+    }
+
+    for (i = 0; i < 2; i++)
+    {
+        entry->addr.uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff;
+    }
+
+    entry->white_list_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, WL_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->white_list_en = A_TRUE;
+    }
+
+    return;
+}
+
+static sw_error_t
+_isis_atu_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                      (a_uint8_t *) (&reg[3]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_atu_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                      (a_uint8_t *) (&reg[3]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    sw_error_t rv;
+    a_uint32_t busy = 1;
+    a_uint32_t full_vio;
+    a_uint32_t i = 2000;
+    a_uint32_t entry = 0;
+    a_uint32_t hwop = op;
+
+    while (busy && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry);
+	aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        printk("%s BUSY\n", __FUNCTION__);
+        return SW_BUSY;
+    }
+
+    if (ARL_FIRST_ENTRY == op)
+    {
+        hwop = ARL_NEXT_ENTRY;
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_BUSY, 1, entry);
+
+    if (ARL_FLUSH_PORT_AND_STATIC == hwop)
+    {
+        hwop = ARL_FLUSH_PORT_UNICAST;
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 1, entry);
+    }
+
+    if (ARL_FLUSH_PORT_NO_STATIC == hwop)
+    {
+        hwop = ARL_FLUSH_PORT_UNICAST;
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 0, entry);
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_FUNC, hwop, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    busy = 1;
+    i = 2000;
+    while (busy && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry);
+    }
+
+    if (0 == i)
+    {
+        return SW_FAIL;
+    }
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_FULL_VIO, full_vio, entry);
+
+    if (full_vio)
+    {
+        /* must clear AT_FULL_VOI bit */
+        entry = 0x1000;
+        HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        if (ARL_LOAD_ENTRY == hwop)
+        {
+            return SW_FULL;
+        }
+        else if ((ARL_PURGE_ENTRY == hwop)
+                 || (ARL_FLUSH_PORT_UNICAST == hwop))
+        {
+            return SW_NOT_FOUND;
+        }
+        else
+        {
+            return SW_FAIL;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_get(a_uint32_t dev_id, fal_fdb_op_t * option, fal_fdb_entry_t * entry,
+              a_uint32_t hwop)
+{
+    sw_error_t rv;
+    a_uint32_t i, port = 0, status, reg[4] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == option->port_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_EN, 1, reg[3]);
+        if (A_FALSE == entry->portmap_en)
+        {
+            if (A_TRUE !=
+                    hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+            {
+                return SW_BAD_PARAM;
+            }
+            port = entry->port.id;
+        }
+        else
+        {
+            if (A_FALSE ==
+                    hsl_mports_prop_check(dev_id, entry->port.map,
+                                          HSL_PP_INCL_CPU))
+            {
+                return SW_BAD_PARAM;
+            }
+
+            status = 0;
+            for (i = 0; i < SW_MAX_NR_PORT; i++)
+            {
+                if ((entry->port.map) & (0x1UL << i))
+                {
+                    if (status)
+                    {
+                        return SW_BAD_PARAM;
+                    }
+                    port = i;
+                    status = 1;
+                }
+            }
+        }
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port, reg[3]);
+    }
+
+    if (A_TRUE == option->fid_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]);
+    }
+
+    if (A_TRUE == option->multicast_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]);
+    }
+
+    if (FAL_SVL_FID == entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]);
+    }
+    else if (ISIS_MAX_FID >= entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, entry->fid, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ARL_FIRST_ENTRY != hwop)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 0xf, reg[2]);
+    }
+
+    _isis_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+
+    rv = _isis_atu_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_fdb_commit(dev_id, hwop);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_atu_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    _isis_atu_hw_to_sw(reg, entry);
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]);
+    if ((A_TRUE == _isis_fdb_is_zeroaddr(entry->addr))
+            && (0 == status))
+    {
+        if (ARL_NEXT_ENTRY == hwop)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            return SW_NOT_FOUND;
+        }
+    }
+    else
+    {
+        return SW_OK;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[4] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_atu_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_atu_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        rv = _isis_fdb_commit(dev_id, ARL_FLUSH_ALL);
+    }
+    else
+    {
+        rv = _isis_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port_id, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        rv = _isis_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC);
+    }
+    else
+    {
+        rv = _isis_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC);
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg0 = 0, reg1 = 0, reg2 = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    _isis_fdb_fill_addr(entry->addr, &reg0, &reg1);
+
+    if (FAL_SVL_FID == entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg2);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg1);
+    }
+    else if (ISIS_MAX_FID >= entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg2);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg1);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, (a_uint8_t *) (&reg2),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (&reg1),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&reg0),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_fdb_commit(dev_id, ARL_PURGE_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    fal_fdb_op_t option;
+
+    aos_mem_zero(&option, sizeof (fal_fdb_op_t));
+    rv = _isis_fdb_get(dev_id, &option, entry, ARL_FIND_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option,
+                      fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    rv = _isis_fdb_get(dev_id, option, entry, ARL_NEXT_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+                       fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    rv = _isis_fdb_get(dev_id, option, entry, ARL_FIRST_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+                   a_uint32_t fid, fal_fdb_op_t * option)
+{
+    sw_error_t rv;
+    a_uint32_t reg[4] = { 0 };
+
+    if (A_TRUE == option->port_en)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == option->fid_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]);
+    }
+
+    if (A_TRUE == option->multicast_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]);
+    }
+
+    if (FAL_SVL_FID == fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]);
+    }
+    else if (ISIS_MAX_FID >= fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, fid, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, old_port, reg[3]);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, NEW_PORT_NUM, new_port, reg[3]);
+
+    rv = _isis_atu_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_fdb_commit(dev_id, ARL_TRANSFER_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((65535 * 7 < *time) || (7 > *time))
+    {
+        return SW_BAD_PARAM;
+    }
+    data = *time / 7;
+    *time = data * 7;
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *time = data * 7;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        if (ISIS_MAX_PORT_LEARN_LIMIT_CNT < cnt)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, cnt, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, 0, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, data, reg);
+    if (data)
+    {
+        SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, data, reg);
+        *enable = A_TRUE;
+        *cnt = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *cnt = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        if (ISIS_MAX_LEARN_LIMIT_CNT < cnt)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 1,
+                            reg);
+        SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, cnt, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 0,
+                            reg);
+        SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, 0, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable,
+                          a_uint32_t * cnt)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, data,
+                        reg);
+    if (data)
+    {
+        SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, data,
+                            reg);
+        *enable = A_TRUE;
+        *cnt = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *cnt = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+                      GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+                      GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+#define ISIS_RESV_ADDR_NUM  32
+#define RESV_ADDR_TBL0_ADDR 0x3c000
+#define RESV_ADDR_TBL1_ADDR 0x3c004
+#define RESV_ADDR_TBL2_ADDR 0x3c008
+
+static void
+_isis_resv_addr_parse(const a_uint32_t reg[], fal_mac_addr_t * addr)
+{
+    a_uint32_t i;
+
+    for (i = 2; i < 6; i++)
+    {
+        addr->uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff;
+    }
+
+    for (i = 0; i < 2; i++)
+    {
+        addr->uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff;
+    }
+}
+
+static sw_error_t
+_isis_resv_atu_sw_to_hw(a_uint32_t dev_id, fal_fdb_entry_t * entry,
+                        a_uint32_t reg[])
+{
+    a_uint32_t port;
+
+    if (A_FALSE == entry->portmap_en)
+    {
+        if (A_TRUE !=
+                hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+        port = 0x1UL << entry->port.id;
+    }
+    else
+    {
+        if (A_FALSE ==
+                hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+        port = entry->port.map;
+    }
+    SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_DES_PORT, port, reg[1]);
+
+    if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, 1, reg[1]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, 1, reg[1]);
+    }
+    else if (FAL_MAC_FRWRD != entry->dacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_MAC_FRWRD != entry->sacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->leaky_en)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 1, reg[1]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 0, reg[1]);
+    }
+
+    if (A_TRUE != entry->static_en)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+    SW_SET_REG_BY_FIELD(RESV_ADDR_TBL2, RESV_STATUS, 1, reg[2]);
+
+    if (A_TRUE == entry->mirror_en)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_MIRROR_EN, 1, reg[1]);
+    }
+
+    if (A_TRUE == entry->cross_pt_state)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_CROSS_PT, 1, reg[1]);
+    }
+
+    if (A_TRUE == entry->da_pri_en)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI_EN, 1, reg[1]);
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI, (entry->da_queue & 0x7),
+                            reg[1]);
+    }
+
+    _isis_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+    return SW_OK;
+}
+
+static void
+_isis_resv_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+    a_uint32_t data;
+
+    aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+    entry->fid = FAL_SVL_FID;
+
+    entry->dacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, data, reg[1]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_CPY_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, data, reg[1]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    entry->sacmd = FAL_MAC_FRWRD;
+
+    entry->leaky_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_LEAKY_EN, data, reg[1]);
+    if (1 == data)
+    {
+        entry->leaky_en = A_TRUE;
+    }
+
+    entry->static_en = A_TRUE;
+
+    entry->mirror_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_MIRROR_EN, data, reg[1]);
+    if (1 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+
+    entry->da_pri_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI_EN, data, reg[1]);
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI, data, reg[1]);
+        entry->da_pri_en = A_TRUE;
+        entry->da_queue = data & 0x7;
+    }
+
+    entry->cross_pt_state = A_FALSE;
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_CROSS_PT, data, reg[1]);
+    if (1 == data)
+    {
+        entry->cross_pt_state = A_TRUE;
+    }
+
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_DES_PORT, data, reg[1]);
+    entry->portmap_en = A_TRUE;
+    entry->port.map = data;
+
+    _isis_resv_addr_parse(reg, &(entry->addr));
+    return;
+}
+
+static sw_error_t
+_isis_fdb_resv_commit(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op,
+                      a_uint32_t * empty)
+{
+    a_uint32_t index, addr, data, tbl[3] = { 0 };
+    sw_error_t rv;
+    fal_mac_addr_t mac_tmp;
+
+    *empty = ISIS_RESV_ADDR_NUM;
+    for (index = 0; index < ISIS_RESV_ADDR_NUM; index++)
+    {
+        addr = RESV_ADDR_TBL2_ADDR + (index << 4);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]);
+        if (data)
+        {
+            addr = RESV_ADDR_TBL0_ADDR + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[0])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            addr = RESV_ADDR_TBL1_ADDR + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[1])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            _isis_resv_addr_parse(tbl, &mac_tmp);
+            if (!aos_mem_cmp
+                    ((void *) &(entry->addr), (void *) &mac_tmp,
+                     sizeof (fal_mac_addr_t)))
+            {
+                if (ARL_PURGE_ENTRY == op)
+                {
+                    addr = RESV_ADDR_TBL2_ADDR + (index << 4);
+                    tbl[2] = 0;
+                    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                          (a_uint8_t *) (&(tbl[2])),
+                                          sizeof (a_uint32_t));
+                    return rv;
+                }
+                else if (ARL_LOAD_ENTRY == op)
+                {
+                    return SW_ALREADY_EXIST;
+                }
+                else if (ARL_FIND_ENTRY == op)
+                {
+                    _isis_resv_atu_hw_to_sw(tbl, entry);
+                    return SW_OK;
+                }
+            }
+        }
+        else
+        {
+            *empty = index;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isis_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, empty, addr, tbl[3] = { 0 };
+
+    rv = _isis_resv_atu_sw_to_hw(dev_id, entry, tbl);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_fdb_resv_commit(dev_id, entry, ARL_LOAD_ENTRY, &empty);
+    if (SW_ALREADY_EXIST == rv)
+    {
+        return rv;
+    }
+
+    if (ISIS_RESV_ADDR_NUM == empty)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    for (i = 0; i < 3; i++)
+    {
+        addr = RESV_ADDR_TBL0_ADDR + (empty << 4) + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t empty;
+
+    rv = _isis_fdb_resv_commit(dev_id, entry, ARL_PURGE_ENTRY, &empty);
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t empty;
+
+    rv = _isis_fdb_resv_commit(dev_id, entry, ARL_FIND_ENTRY, &empty);
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+                       fal_fdb_entry_t * entry)
+{
+    a_uint32_t index, addr, data, tbl[3] = { 0 };
+    sw_error_t rv;
+
+    if ((NULL == iterator) || (NULL == entry))
+    {
+        return SW_BAD_PTR;
+    }
+
+    if (ISIS_RESV_ADDR_NUM < *iterator)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (index = *iterator; index < ISIS_RESV_ADDR_NUM; index++)
+    {
+        addr = RESV_ADDR_TBL2_ADDR + (index << 4);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]);
+        if (data)
+        {
+            addr = RESV_ADDR_TBL0_ADDR + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[0])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            addr = RESV_ADDR_TBL1_ADDR + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[1])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            _isis_resv_atu_hw_to_sw(tbl, entry);
+            break;
+        }
+    }
+
+    if (ISIS_RESV_ADDR_NUM == index)
+    {
+        return SW_NO_MORE;
+    }
+
+    *iterator = index + 1;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 0xf;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0x7;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      SA_LEARN_STATUS, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      SA_LEARN_STATUS, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0xf == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_port_update(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id, a_uint32_t op)
+{
+    sw_error_t      rv;
+    fal_fdb_entry_t entry;
+    fal_fdb_op_t    option;
+    a_uint32_t      reg, port;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SVL_FID < fid)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(&option, sizeof(fal_fdb_op_t));
+    aos_mem_copy(&(entry.addr), addr, sizeof(fal_mac_addr_t));
+    entry.fid = fid & 0xffff;
+    rv = _isis_fdb_get(dev_id, &option, &entry, ARL_FIND_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, port, reg);
+    if (op)
+    {
+        port |= (0x1 << port_id);
+    }
+    else
+    {
+        port &= (~(0x1 << port_id));
+    }
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    rv = _isis_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+    return rv;
+}
+
+/**
+ * @brief Add a Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_add(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete all Fdb entries
+ *   @details   Comments:
+ *         If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ *       entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_del_all(dev_id, flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete Fdb entries on a particular port
+ *   @details   Comments:
+ *       If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ *       entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_del_by_port(dev_id, port_id, flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a particular Fdb entry through mac address
+ *   @details   Comments:
+ *       Only addr field in entry is meaning. For IVL learning vid or fid field
+ *       also is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_del_by_mac(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a particular Fdb entry from device through mac address.
+ *    @details  Comments:
+    For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_find(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get next Fdb entry from a particular device
+ * @param[in] dev_id device id
+ * @param[in] option next operation options
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option,
+                     fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_extend_next(dev_id, option, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from a particular device
+ * @param[in] dev_id device id
+ * @param[in] option first operation options
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+                      fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_extend_first(dev_id, option, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Transfer fdb entries port information on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] old_port source port id
+ * @param[in] new_port destination port id
+ * @param[in] fid filter database id
+ * @param[in] option transfer operation options
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+                  a_uint32_t fid, fal_fdb_op_t * option)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_transfer(dev_id, old_port, new_port, fid, option);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning status on a particular port.
+ *    @details  Comments:
+ *       This operation will enable or disable dynamic address learning
+ *       feature on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_port_learn_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_port_learn_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address aging status on particular device.
+ *   @details  Comments:
+ *       This operation will enable or disable dynamic address aging
+ *       feature on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_age_ctrl_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address aging status on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_age_ctrl_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address aging time on a particular device.
+ * @details   Comments:
+ *       This operation will set dynamic address aging time on a particular device.
+ *       The unit of time is second. Because different device has differnet
+ *       hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_age_time_set(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address aging time on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_age_time_get(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_fdb_learn_limit_set(dev_id, port_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_fdb_learn_limit_get(dev_id, port_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count limit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_learn_limit_set(dev_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count limit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_learn_limit_get(dev_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count exceed command on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_learn_exceed_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count exceed command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_learn_exceed_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a particular reserve Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_resv_add(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a particular reserve Fdb entry through mac address
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_resv_del(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a particular reserve Fdb entry through mac address
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @param[out] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_resv_find(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Iterate all reserve fdb entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] iterator reserve fdb entry index if it's zero means get the first entry
+ * @param[out] iterator next valid fdb entry index
+ * @param[out] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+                      fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_resv_iterate(dev_id, iterator, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the static status of fdb entries which learned by hardware on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_port_learn_static_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the static status of fdb entries which learned by hardware on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_port_learn_static_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a port to an exsiting entry
+ * @param[in] dev_id device id
+ * @param[in] fid filtering database id
+ * @param[in] addr MAC address
+ * @param[in] port_id port id
+ * @return SW_OK or error code, If entry not exist will return error.
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_port_update(dev_id, fid, addr, port_id, 1);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a port from an exsiting entry
+ * @param[in] dev_id device id
+ * @param[in] fid filtering database id
+ * @param[in] addr MAC address
+ * @param[in] port_id port id
+ * @return SW_OK or error code, If entry not exist will return error.
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_fdb_port_update(dev_id, fid, addr, port_id, 0);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_fdb_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->fdb_add = isis_fdb_add;
+        p_api->fdb_del_all = isis_fdb_del_all;
+        p_api->fdb_del_by_port = isis_fdb_del_by_port;
+        p_api->fdb_del_by_mac = isis_fdb_del_by_mac;
+        p_api->fdb_extend_first = isis_fdb_extend_first;
+        p_api->fdb_extend_next = isis_fdb_extend_next;
+        p_api->fdb_find = isis_fdb_find;
+        p_api->port_learn_set = isis_fdb_port_learn_set;
+        p_api->port_learn_get = isis_fdb_port_learn_get;
+        p_api->age_ctrl_set = isis_fdb_age_ctrl_set;
+        p_api->age_ctrl_get = isis_fdb_age_ctrl_get;
+        p_api->age_time_set = isis_fdb_age_time_set;
+        p_api->age_time_get = isis_fdb_age_time_get;
+        p_api->fdb_extend_next  = isis_fdb_extend_next;
+        p_api->fdb_extend_first = isis_fdb_extend_first;
+        p_api->fdb_transfer     = isis_fdb_transfer;
+        p_api->port_fdb_learn_limit_set = isis_port_fdb_learn_limit_set;
+        p_api->port_fdb_learn_limit_get = isis_port_fdb_learn_limit_get;
+        p_api->port_fdb_learn_exceed_cmd_set = isis_port_fdb_learn_exceed_cmd_set;
+        p_api->port_fdb_learn_exceed_cmd_get = isis_port_fdb_learn_exceed_cmd_get;
+        p_api->fdb_learn_limit_set = isis_fdb_learn_limit_set;
+        p_api->fdb_learn_limit_get = isis_fdb_learn_limit_get;
+        p_api->fdb_learn_exceed_cmd_set = isis_fdb_learn_exceed_cmd_set;
+        p_api->fdb_learn_exceed_cmd_get = isis_fdb_learn_exceed_cmd_get;
+        p_api->fdb_resv_add     = isis_fdb_resv_add;
+        p_api->fdb_resv_del     = isis_fdb_resv_del;
+        p_api->fdb_resv_find    = isis_fdb_resv_find;
+        p_api->fdb_resv_iterate = isis_fdb_resv_iterate;
+        p_api->fdb_port_learn_static_set = isis_fdb_port_learn_static_set;
+        p_api->fdb_port_learn_static_get = isis_fdb_port_learn_static_get;
+        p_api->fdb_port_add = isis_fdb_port_add;
+        p_api->fdb_port_del = isis_fdb_port_del;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isis/isis_igmp.c b/qca-ssdk/src/hsl/isis/isis_igmp.c
new file mode 100755
index 0000000..300dd04
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_igmp.c
@@ -0,0 +1,1143 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_igmp ISIS_IGMP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_igmp.h"
+#include "isis_reg.h"
+
+#define LEAVE_EN_OFFSET     2
+#define JOIN_EN_OFFSET      1
+#define IGMP_MLD_EN_OFFSET  0
+
+#define ISIS_MAX_PORT_LEARN_LIMIT_CNT 1023
+
+extern sw_error_t
+isis_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+extern sw_error_t
+isis_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+extern sw_error_t
+isis_igmp_sg_entry_show(a_uint32_t dev_id);
+
+static sw_error_t
+_isis_port_igmp_property_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable, a_uint32_t item)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (3 >= port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        reg &= ~(0x1UL << ((port_id << 3) + item));
+        reg |= (val << ((port_id << 3) + item));
+
+        HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        reg &= ~(0x1UL << (((port_id - 4) << 3) + item));
+        reg |= (val << (((port_id - 4) << 3) + item));
+
+        HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    return rv;
+}
+
+static sw_error_t
+_isis_port_igmp_property_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable, a_uint32_t item)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (3 >= port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        val = (reg >> ((port_id << 3) + item)) & 0x1UL;
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL;
+    }
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_mports_validity_check(dev_id, pts))
+    {
+        return SW_BAD_PARAM;
+    }
+    val = pts;
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *pts = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 0xf;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0xe;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0xf == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable,
+                               a_uint32_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 1, entry);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, queue, entry);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 0, entry);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, 0, entry);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_CTL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable,
+                               a_uint32_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI_EN, data, entry);
+    if (data)
+    {
+        *enable = A_TRUE;
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI, data, entry);
+        *queue = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *queue = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        if (ISIS_MAX_PORT_LEARN_LIMIT_CNT < cnt)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, cnt, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, 0, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, data, reg);
+    if (data)
+    {
+        SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, data, reg);
+        *enable = A_TRUE;
+        *cnt = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *cnt = data;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+        fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+        fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set igmp/mld packets snooping status on a particular port.
+ * @details    Comments:
+ *   After enabling igmp/mld snooping feature on a particular port all kinds
+ *   igmp/mld packets received on this port would be acknowledged by hardware.
+ *   Particular forwarding decision could be setted by fal_igmp_mld_cmd_set.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_igmp_property_set(dev_id, port_id, enable,
+                                      IGMP_MLD_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets snooping status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_igmp_property_get(dev_id, port_id, enable,
+                                      IGMP_MLD_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld packets forwarding command on a particular device.
+ * @details    Comments:
+ *    Particular device may only support parts of forwarding commands.
+ *    This operation will take effect only after enabling igmp/mld snooping
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_igmp_mld_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_igmp_mld_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld join packets hardware acknowledgement status on particular port.
+ * @details    Comments:
+ *    After enabling igmp/mld join feature on a particular port hardware will
+ *    dynamic learning or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_igmp_property_set(dev_id, port_id, enable, JOIN_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_igmp_property_get(dev_id, port_id, enable, JOIN_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @details    Comments:
+ *    After enabling igmp leave feature on a particular port hardware will dynamic
+ *    deleting or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_igmp_property_set(dev_id, port_id, enable, LEAVE_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_igmp_property_get(dev_id, port_id, enable, LEAVE_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld router ports on a particular device.
+ * @details     Comments:
+ *    After enabling igmp/mld join/leave feature on a particular port igmp/mld
+ *    join/leave packets received on this port will be forwarded to router ports.
+ * @param[in] dev_id device id
+ * @param[in] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_igmp_mld_rp_set(dev_id, pts);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld router ports on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_igmp_mld_rp_get(dev_id, pts);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   entry creat hardware will dynamic creat and delete multicast entry,
+ *   otherwise hardware only can change destination ports of existing muticast entry.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_igmp_mld_entry_creat_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_igmp_mld_entry_creat_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the static status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   static status hardware will not age out multicast entry which leardned by hardware,
+ *   otherwise hardware will age out multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_igmp_mld_entry_static_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the static status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_igmp_mld_entry_static_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the leaky status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   leaky status hardware will set leaky flag of multicast entry which leardned by hardware,
+ *   otherwise hardware will not set leaky flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_igmp_mld_entry_leaky_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the leaky status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_igmp_mld_entry_leaky_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @details    Comments:
+ *    After enabling igmp join/leave feature on a particular port hardware will dynamic
+ *    creating or changing multicast entry after receiving igmpv3/mldv2 packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_igmp_mld_entry_v3_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_igmp_mld_entry_v3_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the queue status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   leaky status hardware will set queue flag of multicast entry which leardned by hardware,
+ *   otherwise hardware will not set queue flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable,
+                              a_uint32_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_igmp_mld_entry_queue_set(dev_id, enable, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the queue status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable,
+                              a_uint32_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_igmp_mld_entry_queue_get(dev_id, enable, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IGMP hardware learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_igmp_mld_learn_limit_set(dev_id, port_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IGMP hardware learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_igmp_mld_learn_limit_get(dev_id, port_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IGMP hardware learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                        fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_igmp_mld_learn_exceed_cmd_set(dev_id, port_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IGMP hardware learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                        fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_igmp_mld_learn_exceed_cmd_get(dev_id, port_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_igmp_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->port_igmps_status_set = isis_port_igmps_status_set;
+        p_api->port_igmps_status_get = isis_port_igmps_status_get;
+        p_api->igmp_mld_cmd_set = isis_igmp_mld_cmd_set;
+        p_api->igmp_mld_cmd_get = isis_igmp_mld_cmd_get;
+        p_api->port_igmp_join_set = isis_port_igmp_mld_join_set;
+        p_api->port_igmp_join_get = isis_port_igmp_mld_join_get;
+        p_api->port_igmp_leave_set = isis_port_igmp_mld_leave_set;
+        p_api->port_igmp_leave_get = isis_port_igmp_mld_leave_get;
+        p_api->igmp_rp_set = isis_igmp_mld_rp_set;
+        p_api->igmp_rp_get = isis_igmp_mld_rp_get;
+        p_api->igmp_entry_creat_set = isis_igmp_mld_entry_creat_set;
+        p_api->igmp_entry_creat_get = isis_igmp_mld_entry_creat_get;
+        p_api->igmp_entry_static_set = isis_igmp_mld_entry_static_set;
+        p_api->igmp_entry_static_get = isis_igmp_mld_entry_static_get;
+        p_api->igmp_entry_leaky_set = isis_igmp_mld_entry_leaky_set;
+        p_api->igmp_entry_leaky_get = isis_igmp_mld_entry_leaky_get;
+        p_api->igmp_entry_v3_set = isis_igmp_mld_entry_v3_set;
+        p_api->igmp_entry_v3_get = isis_igmp_mld_entry_v3_get;
+        p_api->igmp_entry_queue_set = isis_igmp_mld_entry_queue_set;
+        p_api->igmp_entry_queue_get = isis_igmp_mld_entry_queue_get;
+        p_api->port_igmp_mld_learn_limit_set = isis_port_igmp_mld_learn_limit_set;
+        p_api->port_igmp_mld_learn_limit_get = isis_port_igmp_mld_learn_limit_get;
+        p_api->port_igmp_mld_learn_exceed_cmd_set = isis_port_igmp_mld_learn_exceed_cmd_set;
+        p_api->port_igmp_mld_learn_exceed_cmd_get = isis_port_igmp_mld_learn_exceed_cmd_get;
+        p_api->igmp_sg_entry_set = isis_igmp_sg_entry_set;
+        p_api->igmp_sg_entry_clear = isis_igmp_sg_entry_clear;
+        p_api->igmp_sg_entry_show = isis_igmp_sg_entry_show;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isis/isis_init.c b/qca-ssdk/src/hsl/isis/isis_init.c
new file mode 100755
index 0000000..b854c2b
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_init.c
@@ -0,0 +1,340 @@
+/*
+ * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_init ISIS_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_mib.h"
+#include "isis_port_ctrl.h"
+#include "isis_portvlan.h"
+#include "isis_vlan.h"
+#include "isis_fdb.h"
+#include "isis_qos.h"
+#include "isis_mirror.h"
+#include "isis_stp.h"
+#include "isis_rate.h"
+#include "isis_misc.h"
+#include "isis_leaky.h"
+#include "isis_igmp.h"
+#include "isis_acl.h"
+#include "isis_led.h"
+#include "isis_cosmap.h"
+#include "isis_ip.h"
+#include "isis_nat.h"
+#if defined(IN_NAT_HELPER)
+#include "isis_nat_helper.h"
+#endif
+#include "isis_sec.h"
+#include "isis_trunk.h"
+#include "isis_interface_ctrl.h"
+#include "isis_reg_access.h"
+#include "isis_reg.h"
+#include "isis_init.h"
+#include "f1_phy.h"
+
+static ssdk_init_cfg * isis_cfg[SW_MAX_NR_DEV] = { 0 };
+a_uint32_t isis_nat_global_status = 0;
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+/* For isis there are five internal PHY devices and seven MAC devices.
+   MAC0 always connect to external MAC device.
+   PHY4 can connect to MAC5 or external MAC device.
+   MAC6 always connect to external devices.
+   MAC1..MAC4 connect to internal PHY0..PHY3.
+*/
+static sw_error_t
+isis_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
+{
+    hsl_port_prop_t p_type;
+    hsl_dev_t *pdev = NULL;
+    fal_port_t port_id;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return SW_NOT_INITIALIZED;
+
+    /* for port property set, SSDK should not generate some limitations */
+    for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+    {
+        hsl_port_prop_portmap_set(dev_id, port_id);
+
+        for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
+        {
+            if (HSL_NO_CPU == mode)
+            {
+                SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                continue;
+            }
+
+            switch (p_type)
+            {
+                case HSL_PP_PHY:
+                    /* Only port0/port6 without PHY device */
+                    if ((port_id != pdev->cpu_port_nr)
+                            && (port_id != pdev->nr_ports - 1))
+                    {
+                        SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                    }
+                    break;
+
+                case HSL_PP_INCL_CPU:
+                    /* include cpu port but exclude wan port in some cases */
+                    /* but which port is wan port, we are no meaning */
+                    SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                    break;
+
+                case HSL_PP_EXCL_CPU:
+                    /* exclude cpu port and wan port in some cases */
+                    /* which port is wan port, we are no meaning but port0 is
+                       always CPU port */
+                    if (port_id != pdev->cpu_port_nr)
+                    {
+                        SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                    }
+                    break;
+
+                default:
+                    break;
+            }
+        }
+
+        if (HSL_NO_CPU == mode)
+        {
+            SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+                            (dev_id, port_id, port_id + 1));
+        }
+        else
+        {
+            if (port_id != pdev->cpu_port_nr)
+            {
+                SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+                                (dev_id, port_id, port_id - 1));
+            }
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+isis_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    return SW_OK;
+}
+
+#endif
+
+static sw_error_t
+isis_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode)
+{
+    a_uint32_t entry = 0;
+    sw_error_t rv;
+    hsl_dev_t *pdev = NULL;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return SW_NOT_INITIALIZED;
+
+    HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (S17_DEVICE_ID == entry)
+    {
+        pdev->nr_ports = 7;
+        pdev->nr_phy = 5;
+        pdev->cpu_port_nr = 0;
+        pdev->nr_vlans = 4096;
+        pdev->hw_vlan_query = A_TRUE;
+        pdev->nr_queue = 6;
+        pdev->cpu_mode = cpu_mode;
+    }
+    else
+    {
+        pdev->nr_ports = 6;
+        pdev->nr_phy = 5;
+        pdev->cpu_port_nr = 0;
+        pdev->nr_vlans = 4096;
+        pdev->hw_vlan_query = A_TRUE;
+        pdev->nr_queue = 6;
+        pdev->cpu_mode = cpu_mode;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_isis_reset(a_uint32_t dev_id)
+{
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    val = 0x1;
+    HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = isis_hw_init(dev_id, isis_cfg[dev_id]);
+    SW_RTN_ON_ERROR(rv);
+
+    ISIS_ACL_RESET(rv, dev_id);
+    ISIS_IP_RESET(rv, dev_id);
+    ISIS_NAT_RESET(rv, dev_id);
+#endif
+
+    return SW_OK;
+}
+
+sw_error_t
+isis_cleanup(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    if (isis_cfg[dev_id])
+    {
+#if defined(IN_NAT_HELPER)
+		if(isis_nat_global_status) {
+        	ISIS_NAT_HELPER_CLEANUP(rv, dev_id);
+			isis_nat_global_status = 0;
+		}
+#endif
+
+	ISIS_ACL_CLEANUP(rv, dev_id);
+
+        SW_RTN_ON_ERROR(hsl_port_prop_cleanup_by_dev(dev_id));
+
+        aos_mem_free(isis_cfg[dev_id]);
+        isis_cfg[dev_id] = NULL;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief reset hsl layer.
+ * @details Comments:
+ *   This operation will reset hsl layer
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_reset(dev_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Init hsl layer.
+ * @details Comments:
+ *   This operation will init hsl layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+isis_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (NULL == isis_cfg[dev_id])
+    {
+        isis_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg));
+    }
+
+    if (NULL == isis_cfg[dev_id])
+    {
+        return SW_OUT_OF_MEM;
+    }
+
+    aos_mem_copy(isis_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+
+    SW_RTN_ON_ERROR(isis_reg_access_init(dev_id, cfg->reg_mode));
+
+    SW_RTN_ON_ERROR(isis_dev_init(dev_id, cfg->cpu_mode));
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+    {
+        sw_error_t rv;
+
+        SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id));
+        SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
+        SW_RTN_ON_ERROR(isis_portproperty_init(dev_id, cfg->cpu_mode));
+
+        ISIS_MIB_INIT(rv, dev_id);
+        ISIS_PORT_CTRL_INIT(rv, dev_id);
+        ISIS_PORTVLAN_INIT(rv, dev_id);
+        ISIS_VLAN_INIT(rv, dev_id);
+        ISIS_FDB_INIT(rv, dev_id);
+        ISIS_QOS_INIT(rv, dev_id);
+        ISIS_STP_INIT(rv, dev_id);
+        ISIS_MIRR_INIT(rv, dev_id);
+        ISIS_RATE_INIT(rv, dev_id);
+        ISIS_MISC_INIT(rv, dev_id);
+        ISIS_LEAKY_INIT(rv, dev_id);
+        ISIS_IGMP_INIT(rv, dev_id);
+        ISIS_ACL_INIT(rv, dev_id);
+        ISIS_LED_INIT(rv, dev_id);
+        ISIS_COSMAP_INIT(rv, dev_id);
+        ISIS_IP_INIT(rv, dev_id);
+        ISIS_NAT_INIT(rv, dev_id);
+        ISIS_TRUNK_INIT(rv, dev_id);
+        ISIS_SEC_INIT(rv, dev_id);
+        ISIS_INTERFACE_CTRL_INIT(rv, dev_id);
+
+        {
+            hsl_api_t *p_api;
+
+            SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+            p_api->dev_reset   = isis_reset;
+            p_api->dev_clean   = isis_cleanup;
+        }
+
+        SW_RTN_ON_ERROR(isis_hw_init(dev_id, cfg));
+#if 0
+#if defined(IN_NAT_HELPER)
+		if(!isis_nat_global_status) {
+        	ISIS_NAT_HELPER_INIT(rv, dev_id);
+			isis_nat_global_status = 1;
+		}
+#endif
+#endif
+
+#if defined(IN_MACBLOCK)
+        qca_mac_scan_helper_init();
+#endif
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isis/isis_interface_ctrl.c b/qca-ssdk/src/hsl/isis/isis_interface_ctrl.c
new file mode 100755
index 0000000..8874ad1
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_interface_ctrl.c
@@ -0,0 +1,1710 @@
+/*
+ * Copyright (c) 2012, 2015-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_interface_ctrl ISIS_INTERFACE_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_interface_ctrl.h"
+#include "isis_reg.h"
+#include "hsl_phy.h"
+
+#define ISIS_MAC_0     0
+#define ISIS_MAC_5     5
+#define ISIS_MAC_6     6
+
+#define ISIS_PHY_MODE_PHY_ID  4
+#define ISIS_LPI_PORT1_OFFSET 4
+#define ISIS_LPI_BIT_STEP     2
+
+/* we need to do more about MAC5/PHY4 connection... */
+#if 0
+static sw_error_t
+_isis_port_mac5_internal_mode(a_uint32_t dev_id, a_bool_t * inter_mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg, rgmii, gmii_mac, gmii_phy, mii_mac, mii_phy, sgmii;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_EN,    rgmii, reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, gmii_mac, reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, gmii_phy, reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_EN,  mii_mac, reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN,  mii_phy, reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_SGMII_EN,    sgmii, reg);
+
+    if (rgmii || gmii_mac || gmii_phy || mii_mac || mii_phy || sgmii)
+    {
+        *inter_mode = A_FALSE;
+    }
+    else
+    {
+        *inter_mode = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_phy4_internal_mode(a_uint32_t dev_id, a_bool_t * inter_mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg, rgmii, gmii, mii;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_RGMII_EN, rgmii, reg);
+    SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_GMII_EN,  gmii,  reg);
+    SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_MII_EN,   mii,   reg);
+
+    if (rgmii || gmii || mii)
+    {
+        *inter_mode = A_FALSE;
+    }
+    else
+    {
+        *inter_mode = A_TRUE;
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isis_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field, offset, device_id, rev_id, reverse = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg);
+    if (S17_DEVICE_ID != device_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    SW_GET_FIELD_BY_REG(MASK_CTL, REV_ID, rev_id, reg);
+    if (S17_REVISION_A == rev_id)
+    {
+        reverse = 0;
+    }
+    else
+    {
+        reverse = 1;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        field  = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        field  = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (reverse)
+    {
+        field = (~field) & 0x1UL;
+    }
+
+    offset = (port_id - 1) * ISIS_LPI_BIT_STEP + ISIS_LPI_PORT1_OFFSET;
+    reg &= (~(0x1UL << offset));
+    reg |= (field << offset);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, EEE_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field, offset, device_id, rev_id, reverse = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg);
+    if (S17_DEVICE_ID != device_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    SW_GET_FIELD_BY_REG(MASK_CTL, REV_ID, rev_id, reg);
+    if (S17_REVISION_A == rev_id)
+    {
+        reverse = 0;
+    }
+    else
+    {
+        reverse = 1;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    offset = (port_id - 1) * ISIS_LPI_BIT_STEP + ISIS_LPI_PORT1_OFFSET;
+    field = (reg >> offset) & 0x1;
+
+    if (reverse)
+    {
+        field = (~field) & 0x1UL;
+    }
+
+    if (field)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_rgmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rgmii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN,    0, reg);
+
+    /* hardware suggestions: restore to defatult settings */
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL,     0, reg);
+
+    if (A_TRUE == config->txclk_delay_cmd)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, config->txclk_delay_sel, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg);
+    }
+
+    if (A_TRUE == config->rxclk_delay_cmd)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, config->rxclk_delay_sel, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg);
+    }
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    /* Port status register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    /* setting port status default configuration */
+    SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,        0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE,     2, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_rgmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rgmii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, field, reg);
+    if (field)
+    {
+        config->txclk_delay_cmd = A_TRUE;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, field, reg);
+        config->txclk_delay_sel = field;
+    }
+    else
+    {
+        config->txclk_delay_cmd = A_FALSE;
+        config->txclk_delay_sel = 0;
+    }
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, field, reg);
+    if (field)
+    {
+        config->rxclk_delay_cmd = A_TRUE;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, field, reg);
+        config->rxclk_delay_sel = field;
+    }
+    else
+    {
+        config->rxclk_delay_cmd = A_FALSE;
+        config->rxclk_delay_sel = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_gmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_gmii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN,    0, reg);
+
+    /* hardware suggestions: restore to defatult settings */
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL,     0, reg);
+
+    if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, config->txclk_select, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, config->rxclk_select, reg);
+
+    }
+    else if (FAL_INTERFACE_CLOCK_MAC_MODE == config->clock_mode)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, config->txclk_select, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, config->rxclk_select, reg);
+
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    /* Port status register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    /* setting port status default configuration */
+    SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,        0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE,     2, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_gmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_gmii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, field, reg);
+    if (field)
+    {
+        config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, field, reg);
+        config->txclk_select = field;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, field, reg);
+        config->rxclk_select = field;
+
+    }
+    else
+    {
+        config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, field, reg);
+        config->txclk_select = field;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, field, reg);
+        config->rxclk_select = field;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_mii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_mii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN,    0, reg);
+
+    /* hardware suggestions: restore to defatult settings */
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL,     0, reg);
+
+    if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, config->txclk_select, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, config->rxclk_select, reg);
+    }
+    else if (FAL_INTERFACE_CLOCK_MAC_MODE == config->clock_mode)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN,  1, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN,  0, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, config->txclk_select, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, config->rxclk_select, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    /* Port status register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    /* setting port status default configuration */
+    SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,        0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE,     1, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_mii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_mii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, field, reg);
+    if (field)
+    {
+        config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, field, reg);
+        config->txclk_select = field;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, field, reg);
+        config->rxclk_select = field;
+    }
+    else
+    {
+        config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, field, reg);
+        config->txclk_select = field;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, field, reg);
+        config->rxclk_select = field;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_sgmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_sgmii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN,    1, reg);
+
+    /* hardware suggestions: restore to defatult settings */
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL,     0, reg);
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        /* only support one SGMII interface, so we need to disable another SGMII */
+        field = 0;
+        HSL_REG_FIELD_SET(rv, dev_id, PORT6_PAD_CTRL, port_id, MAC6_SGMII_EN,
+                          (a_uint8_t *) (&field), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        /* only support one SGMII interface, so we need to disable another SGMII */
+        field = 0;
+        HSL_REG_FIELD_SET(rv, dev_id, PORT0_PAD_CTRL, port_id, MAC0_SGMII_EN,
+                          (a_uint8_t *) (&field), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* SGMII global settings, for all SGMII interfaces, now we fix all the values */
+    /* TX/RX clock setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_RX_SEL,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_TX_SEL,    0, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* SGMII control register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_FIBER_MODE,  0, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_PLL,      0, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_RX,       0, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_TX,       0, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_SD,       1, reg);
+    if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode)
+    {
+        SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 2, reg);
+    }
+    HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* Port status register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    /* setting port status default configuration */
+    SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE,     2, reg);
+    if (A_TRUE == config->auto_neg)
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,   1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,   0, reg);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_sgmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_sgmii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        /* nothing to do */
+    }
+    else if (ISIS_MAC_6 == port_id)
+    {
+        /* nothing to do */
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, field, reg);
+    if (field)
+    {
+        config->auto_neg = A_TRUE;
+    }
+    else
+    {
+        config->auto_neg = A_FALSE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    SW_GET_FIELD_BY_REG(SGMII_CTRL, MODE_CTRL_25M, field, reg);
+    if (1 == field)
+    {
+        config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE;
+    }
+    else
+    {
+        config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_fiber_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_fiber_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN,    1, reg);
+
+    /* hardware suggestions: restore to defatult settings */
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL,     0, reg);
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        /* only support one SGMII interface, so we need to disable another SGMII */
+        field = 0;
+        HSL_REG_FIELD_SET(rv, dev_id, PORT6_PAD_CTRL, port_id, MAC6_SGMII_EN,
+                          (a_uint8_t *) (&field), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        /* only support one SGMII interface, so we need to disable another SGMII */
+        field = 0;
+        HSL_REG_FIELD_SET(rv, dev_id, PORT0_PAD_CTRL, port_id, MAC0_SGMII_EN,
+                          (a_uint8_t *) (&field), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* SGMII global settings, for all SGMII interfaces, now we fix all the values */
+    /* TX/RX clock setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_RX_SEL,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_TX_SEL,    0, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* SGMII control register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M,     0, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_FIBER_MODE,  3, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_PLL,   0, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_RX,    0, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_TX,    0, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_SD,    1, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* Power on strip register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, POWER_STRIP, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    if (A_TRUE == config->auto_neg)
+    {
+        SW_SET_REG_BY_FIELD(POWER_STRIP, SERDES_AN_EN,   1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(POWER_STRIP, SERDES_AN_EN,   0, reg);
+    }
+    HSL_REG_ENTRY_SET(rv, dev_id, POWER_STRIP, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    /* Port status register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    /* setting port status default configuration */
+    SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,        0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE,     2, reg);
+    if (A_TRUE == config->auto_neg)
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,   1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,   0, reg);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_fiber_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_fiber_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        /* nothing to do */
+    }
+    else if (ISIS_MAC_6 == port_id)
+    {
+        /* nothing to do */
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, POWER_STRIP, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(POWER_STRIP, SERDES_AN_EN, field, reg);
+    if (field)
+    {
+        config->auto_neg = A_TRUE;
+    }
+    else
+    {
+        config->auto_neg = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_default_mode_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN,    0, reg);
+
+    /* hardware suggestions: restore to defatult settings */
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL,     0, reg);
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isis_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_MODE_RGMII == config->mac_mode)
+    {
+        rv = _isis_port_rgmii_mode_set(dev_id, port_id, &(config->config.rgmii));
+    }
+    else if (FAL_MAC_MODE_GMII == config->mac_mode)
+    {
+        rv = _isis_port_gmii_mode_set(dev_id, port_id, &(config->config.gmii));
+    }
+    else if (FAL_MAC_MODE_MII == config->mac_mode)
+    {
+        rv = _isis_port_mii_mode_set(dev_id, port_id, &(config->config.mii));
+    }
+    else if (FAL_MAC_MODE_SGMII == config->mac_mode)
+    {
+        rv = _isis_port_sgmii_mode_set(dev_id, port_id, &(config->config.sgmii));
+    }
+    else if (FAL_MAC_MODE_FIBER == config->mac_mode)
+    {
+        rv = _isis_port_fiber_mode_set(dev_id, port_id, &(config->config.fiber));
+    }
+    else if (FAL_MAC_MODE_DEFAULT == config->mac_mode)
+    {
+        rv = _isis_port_default_mode_set(dev_id, port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isis_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field, field2;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISIS_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISIS_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    aos_mem_zero(config, sizeof(fal_interface_mac_mode_t));
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_EN, field, reg);
+    if (field)
+    {
+        config->mac_mode = FAL_MAC_MODE_RGMII;
+        rv = _isis_port_rgmii_mode_get(dev_id, port_id, &(config->config.rgmii));
+        return rv;
+    }
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, field,  reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, field2, reg);
+    if (field || field2)
+    {
+        config->mac_mode = FAL_MAC_MODE_GMII;
+        rv = _isis_port_gmii_mode_get(dev_id, port_id, &(config->config.gmii));
+        return rv;
+    }
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, field,  reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, field2, reg);
+    if (field || field2)
+    {
+        config->mac_mode = FAL_MAC_MODE_MII;
+        rv = _isis_port_mii_mode_get(dev_id, port_id, &(config->config.mii));
+        return rv;
+    }
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_SGMII_EN, field, reg);
+    if (field)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(SGMII_CTRL, SGMII_FIBER_MODE, field, reg);
+        if (3 == field)
+        {
+            config->mac_mode = FAL_MAC_MODE_FIBER;
+            rv = _isis_port_fiber_mode_get(dev_id, port_id, &(config->config.fiber));
+        }
+        else
+        {
+            config->mac_mode = FAL_MAC_MODE_SGMII;
+            rv = _isis_port_sgmii_mode_get(dev_id, port_id, &(config->config.sgmii));
+        }
+        return rv;
+    }
+
+    config->mac_mode = FAL_MAC_MODE_DEFAULT;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+    sw_error_t rv;
+    a_uint16_t data;
+    a_bool_t tx_delay_cmd, rx_delay_cmd;
+    hsl_phy_ops_t *phy_drv;
+    a_uint32_t reg, rgmii_mode, tx_delay = 2, port_id;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    /* only PHY4 support mode setting */
+    if (ISIS_PHY_MODE_PHY_ID != phy_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+	port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id);
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get(dev_id, port_id));
+    if ((NULL == phy_drv->phy_debug_write) || (NULL == phy_drv->phy_debug_read))
+	  return SW_NOT_SUPPORTED;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_MAC_MODE_RGMII == config->mac_mode)
+    {
+        SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_GMII_EN,  0, reg);
+        SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_MII_EN,   0, reg);
+        rgmii_mode = 1;
+        /* PHY TX delay */
+        if (A_TRUE == config->txclk_delay_cmd)
+        {
+            tx_delay_cmd = A_TRUE;
+            tx_delay     = config->txclk_delay_sel;
+        }
+        else
+        {
+            tx_delay_cmd = A_FALSE;
+        }
+
+        /* PHY RX delay */
+        if (A_TRUE == config->rxclk_delay_cmd)
+        {
+            rx_delay_cmd = A_TRUE;
+        }
+        else
+        {
+            rx_delay_cmd = A_FALSE;
+        }
+    }
+    else if (FAL_MAC_MODE_GMII == config->mac_mode)
+    {
+        SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_GMII_EN,  1, reg);
+        SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_MII_EN,   0, reg);
+        rgmii_mode = 0;
+        tx_delay_cmd = A_FALSE;
+        rx_delay_cmd = A_FALSE;
+    }
+    else if (FAL_MAC_MODE_MII == config->mac_mode)
+    {
+        SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_GMII_EN,  0, reg);
+        SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_MII_EN,   1, reg);
+        rgmii_mode = 0;
+        tx_delay_cmd = A_FALSE;
+        rx_delay_cmd = A_FALSE;
+    }
+    else if (FAL_MAC_MODE_DEFAULT == config->mac_mode)
+    {
+        SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_GMII_EN,  0, reg);
+        SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_MII_EN,   0, reg);
+
+        rgmii_mode = 0;
+        tx_delay_cmd = A_FALSE;
+        rx_delay_cmd = A_FALSE;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* PHY RGMII mode, debug register18 bit3 */
+    data = phy_drv->phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 18);
+    data &= 0xfff7UL;
+    data |= ((rgmii_mode & 0x1) << 3);
+    rv = phy_drv->phy_debug_write(dev_id, ISIS_PHY_MODE_PHY_ID, 18, data);
+    SW_RTN_ON_ERROR(rv);
+
+    /* PHY TX delay command, debug regigster5 bit8 */
+    data = phy_drv->phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 5);
+    if (A_TRUE == tx_delay_cmd)
+    {
+        data |= 0x0100UL;
+    }
+    else
+    {
+        data &= 0xfeffUL;
+    }
+    rv = phy_drv->phy_debug_write(dev_id, ISIS_PHY_MODE_PHY_ID, 5, data);
+    SW_RTN_ON_ERROR(rv);
+
+    /* PHY TX delay select, debug register11 bit-6 */
+    data = phy_drv->phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 11);
+    data &= 0xff9fUL;
+    data |= ((tx_delay & 0x3UL) << 5);
+    if (A_TRUE == tx_delay_cmd)
+    {
+        data |= 0x0100UL;
+    }
+    else
+    {
+        data &= 0xfeffUL;
+    }
+    rv = phy_drv->phy_debug_write(dev_id, ISIS_PHY_MODE_PHY_ID, 11, data);
+    SW_RTN_ON_ERROR(rv);
+
+    /* PHY RX delay command, debug regigster0 bit15 */
+    data = phy_drv->phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 0);
+    if (A_TRUE == rx_delay_cmd)
+    {
+        data |= 0x8000UL;
+    }
+    else
+    {
+        data &= 0x7fffUL;
+    }
+    rv = phy_drv->phy_debug_write(dev_id, ISIS_PHY_MODE_PHY_ID, 0, data);
+    SW_RTN_ON_ERROR(rv);
+
+    /* PHY RX delay select, now hardware not support */
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+    sw_error_t rv;
+    a_uint16_t data;
+    a_uint32_t reg = 0, rgmii, gmii, mii, port_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+	port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id);
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get(dev_id, port_id));
+    if (NULL == phy_drv->phy_debug_read)
+	  return SW_NOT_SUPPORTED;
+
+    /* only one PHY device support this */
+    if (ISIS_PHY_MODE_PHY_ID != phy_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(config, sizeof(fal_phy_config_t));
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_RGMII_EN, rgmii, reg);
+    SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_GMII_EN,  gmii,  reg);
+    SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_MII_EN,   mii,   reg);
+
+    if ((rgmii) && (!gmii) && (!mii))
+    {
+        config->mac_mode = FAL_MAC_MODE_RGMII;
+        data = phy_drv->phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 5);
+        if (data & 0x0100)
+        {
+            config->txclk_delay_cmd = A_TRUE;
+            data = phy_drv->phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 11);
+            config->txclk_delay_sel = (data >> 5) & 0x3UL;
+        }
+        else
+        {
+            config->txclk_delay_cmd = A_FALSE;
+        }
+
+        data = phy_drv->phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 0);
+        if (data & 0x8000)
+        {
+            config->rxclk_delay_cmd = A_TRUE;
+        }
+        else
+        {
+            config->rxclk_delay_cmd = A_FALSE;
+        }
+    }
+    else if ((!rgmii) && (gmii) && (!mii))
+    {
+        config->mac_mode = FAL_MAC_MODE_GMII;
+    }
+    else if ((!rgmii) && (!gmii) && (mii))
+    {
+        config->mac_mode = FAL_MAC_MODE_MII;
+    }
+    else
+    {
+        config->mac_mode = FAL_MAC_MODE_DEFAULT;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_interface_mac_sgmii_set(a_uint32_t dev_id,a_uint32_t value)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    reg = value;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isis_interface_mac_sgmii_get(a_uint32_t dev_id, a_uint32_t *value)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+	*value = reg;
+
+    return rv;
+}
+
+static sw_error_t
+_isis_interface_mac_pad_set(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t value)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    reg = value;
+
+    switch (port_num)
+    {
+	    case ISIS_MAC_0:
+		    HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+				    (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+		    break;
+	    case ISIS_MAC_5:
+		    HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+				    (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+		    break;
+	    case ISIS_MAC_6:
+		    HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+				    (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+		    break;
+	    default:
+		    return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isis_interface_mac_pad_get(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t *value)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    switch (port_num)
+    {
+	    case ISIS_MAC_0:
+		    HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+				    (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+		    break;
+	    case ISIS_MAC_5:
+		    HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+				    (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+		    break;
+	    case ISIS_MAC_6:
+		    HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+				    (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+		    break;
+	    default:
+		    return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    *value = reg;
+
+    return rv;
+}
+
+
+
+/**
+  * @brief Set 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_3az_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Get 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_3az_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Set interface mode on a particular MAC device.
+ * @param[in] dev_id device id
+ * @param[in] mca_id MAC device ID
+ * @param[in] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_interface_mac_mode_set(dev_id, port_id, config);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Get interface mode on a particular MAC device.
+ * @param[in] dev_id device id
+ * @param[in] mca_id MAC device ID
+ * @param[out] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_interface_mac_mode_get(dev_id, port_id, config);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Set interface phy mode on a particular PHY device.
+ * @param[in] dev_id device id
+ * @param[in] phy_id PHY device ID
+ * @param[in] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_interface_phy_mode_set(dev_id, phy_id, config);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Get interface phy mode on a particular PHY device.
+ * @param[in] dev_id device id
+ * @param[in] phy_id PHY device ID
+ * @param[out] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_interface_phy_mode_get(dev_id, phy_id, config);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mac pad configuration.
+ * @param[in] dev_id device id
+ * @param[in] port_num port num
+ * @param[out] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_mac_pad_get(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t* value)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_interface_mac_pad_get(dev_id, port_num, value);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+/**
+ * @brief Set mac pad configuration.
+ * @param[in] dev_id device id
+ * @param[in] port_num port num
+ * @param[in] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_mac_pad_set(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t value)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_interface_mac_pad_set(dev_id,port_num,value);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mac SGMII configuration.
+ * @param[in] dev_id device id
+ * @param[out] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_mac_sgmii_get(a_uint32_t dev_id, a_uint32_t* value)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_interface_mac_sgmii_get(dev_id, value);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+/**
+ * @brief Set mac SGMII configuration.
+ * @param[in] dev_id device id
+ * @param[in] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_mac_sgmii_set(a_uint32_t dev_id, a_uint32_t value)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_interface_mac_sgmii_set(dev_id, value);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+sw_error_t
+isis_interface_ctrl_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->port_3az_status_set = isis_port_3az_status_set;
+        p_api->port_3az_status_get = isis_port_3az_status_get;
+        p_api->interface_mac_mode_set = isis_interface_mac_mode_set;
+        p_api->interface_mac_mode_get = isis_interface_mac_mode_get;
+        p_api->interface_phy_mode_set = isis_interface_phy_mode_set;
+        p_api->interface_phy_mode_get = isis_interface_phy_mode_get;
+	p_api->interface_mac_pad_get = isis_interface_mac_pad_get;
+	p_api->interface_mac_pad_set = isis_interface_mac_pad_set;
+	p_api->interface_mac_sgmii_get = isis_interface_mac_sgmii_get;
+	p_api->interface_mac_sgmii_set = isis_interface_mac_sgmii_set;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isis/isis_ip.c b/qca-ssdk/src/hsl/isis/isis_ip.c
new file mode 100755
index 0000000..f216add
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_ip.c
@@ -0,0 +1,2516 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_ip ISIS_IP
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_ip.h"
+#include "isis_reg.h"
+
+#define ISIS_HOST_ENTRY_DATA0_ADDR              0x0e48
+#define ISIS_HOST_ENTRY_DATA1_ADDR              0x0e4c
+#define ISIS_HOST_ENTRY_DATA2_ADDR              0x0e50
+#define ISIS_HOST_ENTRY_DATA3_ADDR              0x0e54
+#define ISIS_HOST_ENTRY_DATA4_ADDR              0x0e58
+
+#define ISIS_HOST_ENTRY_FLUSH                   1
+#define ISIS_HOST_ENTRY_ADD                     2
+#define ISIS_HOST_ENTRY_DEL                     3
+#define ISIS_HOST_ENTRY_NEXT                    4
+#define ISIS_HOST_ENTRY_SEARCH                  5
+
+#define ISIS_ENTRY_ARP                          3
+
+#define ISIS_INTF_MAC_ADDR_NUM                  8
+#define ISIS_INTF_MAC_TBL0_ADDR                 0x5a900
+#define ISIS_INTF_MAC_TBL1_ADDR                 0x5a904
+#define ISIS_INTF_MAC_TBL2_ADDR                 0x5a908
+#define ISIS_INTF_MAC_EDIT0_ADDR                0x02000
+#define ISIS_INTF_MAC_EDIT1_ADDR                0x02004
+#define ISIS_INTF_MAC_EDIT2_ADDR                0x02008
+
+#define ISIS_IP6_BASE_ADDR                      0x0470
+
+#define ISIS_HOST_ENTRY_NUM                     128
+
+#define ISIS_IP_COUTER_ADDR                     0x2b000
+
+static a_uint32_t isis_mac_snap[SW_MAX_NR_DEV] = { 0 };
+static fal_intf_mac_entry_t isis_intf_snap[SW_MAX_NR_DEV][ISIS_INTF_MAC_ADDR_NUM];
+
+static void
+_isis_ip_pt_learn_save(a_uint32_t dev_id, a_uint32_t * status)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    if (SW_OK != rv)
+    {
+        return;
+    }
+
+    *status = (data & 0x7f7f);
+
+    data &= 0xffff8080;
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return;
+}
+
+static void
+_isis_ip_pt_learn_restore(a_uint32_t dev_id, a_uint32_t status)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    if (SW_OK != rv)
+    {
+        return;
+    }
+
+    data &= 0xffff8080;
+    data |= (status & 0x7f7f);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return;
+}
+
+static sw_error_t
+_isis_ip_feature_check(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (S17_DEVICE_ID == entry)
+    {
+        return SW_OK;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+}
+
+static sw_error_t
+_isis_ip_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id,
+                     a_uint32_t counter[2])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    addr = ISIS_IP_COUTER_ADDR + (cnt_id << 3);
+    for (i = 0; i < 2; i++)
+    {
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(counter[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        addr += 4;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_host_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op)
+{
+    a_uint32_t busy = 1, i = 0x100, entry = 0, j, try_num;
+    a_uint32_t learn_status = 0;
+    sw_error_t rv;
+
+    while (busy && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+                          sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_BUSY, busy, entry);
+        aos_udelay(500);
+    }
+
+    if (i == 0)
+    {
+        printk("%s BUSY\n", __FUNCTION__);
+        return SW_BUSY;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_BUSY, 1, entry);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_SEL, entry_type, entry);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, ENTRY_FUNC, op, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* hardware requirements, we should disable ARP learn at first */
+    /* and maybe we should try several times... */
+    _isis_ip_pt_learn_save(dev_id, &learn_status);
+    if (learn_status)
+    {
+        try_num = 10;
+    }
+    else
+    {
+        try_num = 1;
+    }
+
+    for (j = 0; j < try_num; j++)
+    {
+        busy = 1;
+        i = 0x100;
+        while (busy && --i)
+        {
+            HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+                              sizeof (a_uint32_t));
+            if (SW_OK != rv)
+            {
+                _isis_ip_pt_learn_restore(dev_id, learn_status);
+                return rv;
+            }
+            SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_BUSY, busy, entry);
+            aos_udelay(500);
+        }
+
+        if (i == 0)
+        {
+            _isis_ip_pt_learn_restore(dev_id, learn_status);
+            printk("%s BUSY\n", __FUNCTION__);
+            return SW_BUSY;
+        }
+
+        /* hardware requirement, we should read again... */
+        HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+                          sizeof (a_uint32_t));
+        if (SW_OK != rv)
+        {
+            _isis_ip_pt_learn_restore(dev_id, learn_status);
+            return rv;
+        }
+
+        /* operation success...... */
+        SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_STAUS, busy, entry);
+        if (busy)
+        {
+            _isis_ip_pt_learn_restore(dev_id, learn_status);
+            return SW_OK;
+        }
+    }
+
+    _isis_ip_pt_learn_restore(dev_id, learn_status);
+    if (ISIS_HOST_ENTRY_NEXT == op)
+    {
+        return SW_NO_MORE;
+    }
+    else if (ISIS_HOST_ENTRY_SEARCH == op)
+    {
+        return SW_NOT_FOUND;
+    }
+    else if (ISIS_HOST_ENTRY_DEL == op)
+    {
+        return SW_NOT_FOUND;
+    }
+    else
+    {
+        return SW_FAIL;
+    }
+}
+
+static sw_error_t
+_isis_ip_intf_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry,
+                       a_uint32_t * hw_intf)
+{
+    sw_error_t rv;
+    a_uint32_t addr, lvid, hvid, tbl[3] = {0}, i;
+    a_uint32_t sw_intf = entry->intf_id;
+    a_uint32_t vid_offset;
+
+    for (i = 0; i < ISIS_INTF_MAC_ADDR_NUM; i++)
+    {
+        if (isis_mac_snap[dev_id] & (0x1 << i))
+        {
+            addr = ISIS_INTF_MAC_TBL0_ADDR + (i << 4) + 4;
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[1])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            addr = ISIS_INTF_MAC_TBL0_ADDR + (i << 4) + 8;
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[2])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, hvid, tbl[1]);
+            SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, lvid, tbl[2]);
+            hvid |= ((lvid & 0xff) << 4);
+
+            SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl[1]);
+
+            if ((lvid <= sw_intf) && (hvid >= sw_intf))
+            {
+                vid_offset = entry->expect_vid ? (entry->expect_vid - lvid) : (sw_intf - lvid);
+                *hw_intf = (vid_offset << 3) | i;
+                return SW_OK;
+            }
+        }
+    }
+
+    return SW_BAD_PARAM;
+}
+
+static sw_error_t
+_isis_ip_intf_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_intf,
+                       a_uint32_t * sw_intf)
+{
+    sw_error_t rv;
+    a_uint32_t addr, lvid, tbl = 0, i;
+
+    i = hw_intf & 0x7;
+
+    addr = ISIS_INTF_MAC_TBL0_ADDR + (i << 4) + 4;
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&tbl), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl);
+    *sw_intf = lvid + (hw_intf >> 3);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    if (255 < ((*time + 5) / 6))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = ((*time + 5) / 6);
+    *time = data * 6;
+
+    HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *time = data * 6;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_host_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry,
+                    a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    if (FAL_IP_IP4_ADDR & entry->flags)
+    {
+        reg[0] = entry->ip4_addr;
+    }
+
+    if (FAL_IP_IP6_ADDR & entry->flags)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY1, MAC_ADDR2, entry->mac_addr.uc[2], reg[1]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY1, MAC_ADDR3, entry->mac_addr.uc[3], reg[1]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY1, MAC_ADDR4, entry->mac_addr.uc[4], reg[1]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY1, MAC_ADDR5, entry->mac_addr.uc[5], reg[1]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY2, MAC_ADDR0, entry->mac_addr.uc[0], reg[2]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY2, MAC_ADDR1, entry->mac_addr.uc[1], reg[2]);
+
+    rv = _isis_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data);
+    SW_RTN_ON_ERROR(rv);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY2, INTF_ID, data, reg[2]);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, entry->port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_SET_REG_BY_FIELD(HOST_ENTRY2, SRC_PORT, entry->port_id, reg[2]);
+
+    if (FAL_IP_CPU_ADDR & entry->flags)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY2, CPU_ADDR, 1, reg[2]);
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY3, AGE_FLAG, entry->status, reg[3]);
+
+    if ((A_TRUE == entry->mirror_en) && (FAL_MAC_FRWRD != entry->action))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->counter_en)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY3, CNT_EN, 1, reg[3]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY3, CNT_IDX, entry->counter_id, reg[3]);
+    }
+
+    if (FAL_MAC_DROP == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY2, SRC_PORT, 7, reg[2]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY3, ACTION, 3, reg[3]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY3, ACTION, 1, reg[3]);
+    }
+    else if (FAL_MAC_CPY_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY3, ACTION, 2, reg[3]);
+    }
+    else
+    {
+        if (A_TRUE == entry->mirror_en)
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY3, ACTION, 0, reg[3]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY3, ACTION, 3, reg[3]);
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_host_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[],
+                    fal_host_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, cnt[2] = {0};
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY3, IP_VER, data, reg[3]);
+    if (data)
+    {
+        entry->ip6_addr.ul[0] =  reg[0];
+        entry->flags |= FAL_IP_IP6_ADDR;
+    }
+    else
+    {
+        entry->ip4_addr = reg[0];
+        entry->flags |= FAL_IP_IP4_ADDR;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY1, MAC_ADDR2, entry->mac_addr.uc[2], reg[1]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY1, MAC_ADDR3, entry->mac_addr.uc[3], reg[1]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY1, MAC_ADDR4, entry->mac_addr.uc[4], reg[1]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY1, MAC_ADDR5, entry->mac_addr.uc[5], reg[1]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY2, MAC_ADDR0, entry->mac_addr.uc[0], reg[2]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY2, MAC_ADDR1, entry->mac_addr.uc[1], reg[2]);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY2, INTF_ID, data, reg[2]);
+    rv = _isis_ip_intf_hw_to_sw(dev_id, data, &(entry->intf_id));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY2, SRC_PORT, entry->port_id, reg[2]);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY2, CPU_ADDR, data, reg[2]);
+    if (data)
+    {
+        entry->flags |= FAL_IP_CPU_ADDR;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY3, AGE_FLAG, entry->status, reg[3]);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY3, CNT_EN, data, reg[3]);
+    if (data)
+    {
+        entry->counter_en = A_TRUE;
+        SW_GET_FIELD_BY_REG(HOST_ENTRY3, CNT_IDX, entry->counter_id, reg[3]);
+
+        rv = _isis_ip_counter_get(dev_id, entry->counter_id, cnt);
+        SW_RTN_ON_ERROR(rv);
+
+        entry->packet = cnt[0];
+        entry->byte = cnt[1];
+    }
+    else
+    {
+        entry->counter_en = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY3, PPPOE_EN, data, reg[3]);
+    if (data)
+    {
+        entry->pppoe_en = A_TRUE;
+        SW_GET_FIELD_BY_REG(HOST_ENTRY3, PPPOE_IDX, data, reg[3]);
+        entry->pppoe_id = data;
+    }
+    else
+    {
+        entry->pppoe_en = A_FALSE;
+    }
+
+    if (7 == entry->port_id)
+    {
+        entry->port_id = 0;
+        entry->action = FAL_MAC_DROP;
+    }
+    else
+    {
+        SW_GET_FIELD_BY_REG(HOST_ENTRY3, ACTION, data, reg[3]);
+        entry->action = FAL_MAC_FRWRD;
+        if (0 == data)
+        {
+            entry->mirror_en = A_TRUE;
+        }
+        else if (1 == data)
+        {
+            entry->action = FAL_MAC_RDT_TO_CPU;
+        }
+        else if (2 == data)
+        {
+            entry->action = FAL_MAC_CPY_TO_CPU;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_host_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    for (i = 0; i < 5; i++)
+    {
+        addr = ISIS_HOST_ENTRY_DATA0_ADDR + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&reg[i]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_host_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    for (i = 0; i < 5; i++)
+    {
+        addr = ISIS_HOST_ENTRY_DATA0_ADDR + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&reg[i]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[5] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_ADD);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&reg[4]),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                  fal_host_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[5] = { 0 }, op = ISIS_HOST_ENTRY_FLUSH;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_IP_ENTRY_ID_EN & del_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_IP_ENTRY_IPADDR_EN & del_mode)
+    {
+        op = ISIS_HOST_ENTRY_DEL;
+        if (FAL_IP_IP4_ADDR & entry->flags)
+        {
+            reg[0] = entry->ip4_addr;
+        }
+
+        if (FAL_IP_IP6_ADDR & entry->flags)
+        {
+            return SW_NOT_SUPPORTED;
+        }
+    }
+
+    if (FAL_IP_ENTRY_INTF_EN & del_mode)
+    {
+        rv = _isis_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data);
+        SW_RTN_ON_ERROR(rv);
+
+        SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_VID, 1, reg[4]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY2, INTF_ID, data, reg[2]);
+    }
+
+    if (FAL_IP_ENTRY_PORT_EN & del_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_SP, 1, reg[4]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY2, SRC_PORT, entry->port_id, reg[2]);
+    }
+
+    if (FAL_IP_ENTRY_STATUS_EN & del_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_STATUS, 1, reg[4]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY3, AGE_FLAG, entry->status, reg[3]);
+    }
+
+    rv = _isis_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, op);
+    return rv;
+}
+
+static sw_error_t
+_isis_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                  fal_host_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[5] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_IP_ENTRY_IPADDR_EN != get_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_IP_IP4_ADDR & entry->flags)
+    {
+        reg[0] = entry->ip4_addr;
+    }
+    else if (FAL_IP_IP6_ADDR & entry->flags)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    rv = _isis_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP,
+                                 ISIS_HOST_ENTRY_SEARCH);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    aos_mem_zero(entry, sizeof (fal_host_entry_t));
+
+    rv = _isis_host_hw_to_sw(dev_id, reg, entry);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!(entry->status))
+    {
+        return SW_NOT_FOUND;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&reg[4]),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                   fal_host_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t idx, data, reg[5] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id)
+    {
+        idx = ISIS_HOST_ENTRY_NUM - 1;
+    }
+    else
+    {
+        if ((ISIS_HOST_ENTRY_NUM - 1) == entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = entry->entry_id;
+        }
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, idx, reg[4]);
+
+    if (FAL_IP_ENTRY_INTF_EN & next_mode)
+    {
+        rv = _isis_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data);
+        SW_RTN_ON_ERROR(rv);
+
+        SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_VID, 1, reg[4]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY2, INTF_ID, data, reg[2]);
+    }
+
+    if (FAL_IP_ENTRY_PORT_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_SP, 1, reg[4]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY2, SRC_PORT, entry->port_id, reg[2]);
+    }
+
+    if (FAL_IP_ENTRY_STATUS_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_STATUS, 1, reg[4]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY3, AGE_FLAG, entry->status, reg[3]);
+    }
+
+    rv = _isis_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_NEXT);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    aos_mem_zero(entry, sizeof (fal_host_entry_t));
+
+    rv = _isis_host_hw_to_sw(dev_id, reg, entry);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!(entry->status))
+    {
+        return SW_NO_MORE;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                           a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[5] = { 0 }, tbl[5] = { 0 }, tbl_idx;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    tbl_idx = (entry_id - 1) & 0x7f;
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]);
+
+    rv = _isis_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_NEXT);
+    if (SW_OK != rv)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    rv = _isis_host_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]);
+    if (entry_id != tbl_idx)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    tbl[0] = reg[0];
+    tbl[3] = (reg[3] >> 15) << 15;
+    rv = _isis_host_down_to_hw(dev_id, tbl);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_DEL);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY3, CNT_EN, 0, reg[3]);
+    }
+    else if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY3, CNT_EN, 1, reg[3]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY3, CNT_IDX, cnt_id, reg[3]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    reg[4] = 0x0;
+    rv = _isis_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_ADD);
+    return rv;
+}
+
+static sw_error_t
+_isis_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                         a_uint32_t pppoe_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[5] = { 0 }, tbl[5] = { 0 }, tbl_idx;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    tbl_idx = (entry_id - 1) & 0x7f;
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]);
+
+    rv = _isis_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_NEXT);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_up_to_sw(dev_id, reg);
+    if (SW_OK != rv)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]);
+    if (entry_id != tbl_idx)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY3, PPPOE_EN, 0, reg[3]);
+    }
+    else if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY3, PPPOE_EN, 1, reg[3]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY3, PPPOE_IDX, pppoe_id, reg[3]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    tbl[0] = reg[0];
+    tbl[3] = (reg[3] >> 15) << 15;
+    rv = _isis_host_down_to_hw(dev_id, tbl);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_DEL);
+    SW_RTN_ON_ERROR(rv);
+
+    reg[4] = 0x0;
+    rv = _isis_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_ADD);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t flags)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_ARP_LEARN_REQ & flags)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        data &= (~(0x1 << port_id));
+    }
+
+    if (FAL_ARP_LEARN_ACK & flags)
+    {
+        data |= (0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id));
+    }
+    else
+    {
+        data &= (~(0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id)));
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * flags)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *flags = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data & (0x1 << port_id))
+    {
+        *flags |= FAL_ARP_LEARN_REQ;
+    }
+
+    if (data & (0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id)))
+    {
+        *flags |= FAL_ARP_LEARN_ACK;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_ARP_LEARN_ALL == mode)
+    {
+        data = 1;
+    }
+    else if (FAL_ARP_LEARN_LOCAL == mode)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *mode = FAL_ARP_LEARN_ALL;
+    }
+    else
+    {
+        *mode = FAL_ARP_LEARN_LOCAL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NO_SOURCE_GUARD < mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = 0;
+    if (FAL_MAC_IP_GUARD == mode)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_IP_PORT_GUARD == mode)
+    {
+        data = 2;
+    }
+    else if (FAL_MAC_IP_VLAN_GUARD == mode)
+    {
+        data = 3;
+    }
+    else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode)
+    {
+        data = 4;
+    }
+    reg &= (~(0x7 << (port_id * 3)));
+    reg |= ((data & 0x7) << (port_id * 3));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL1, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = 1;
+    if (FAL_NO_SOURCE_GUARD == mode)
+    {
+        data = 0;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, SP_CHECK_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (reg >> (port_id * 3)) & 0x7;
+
+    *mode = FAL_NO_SOURCE_GUARD;
+    if (1 == data)
+    {
+        *mode = FAL_MAC_IP_GUARD;
+    }
+    else if (2 == data)
+    {
+        *mode = FAL_MAC_IP_PORT_GUARD;
+    }
+    else if (3 == data)
+    {
+        *mode = FAL_MAC_IP_VLAN_GUARD;
+    }
+    else if (4 == data)
+    {
+        *mode = FAL_MAC_IP_PORT_VLAN_GUARD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        data = 0;
+    }
+    else if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 2;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        *cmd = FAL_MAC_FRWRD;
+    }
+    else if (1 == data)
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NO_SOURCE_GUARD < mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = 0;
+    if (FAL_MAC_IP_GUARD == mode)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_IP_PORT_GUARD == mode)
+    {
+        data = 2;
+    }
+    else if (FAL_MAC_IP_VLAN_GUARD == mode)
+    {
+        data = 3;
+    }
+    else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode)
+    {
+        data = 4;
+    }
+    reg &= (~(0x7 << (port_id * 3)));
+    reg |= ((data & 0x7) << (port_id * 3));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (reg >> (port_id * 3)) & 0x7;
+
+    *mode = FAL_NO_SOURCE_GUARD;
+    if (1 == data)
+    {
+        *mode = FAL_MAC_IP_GUARD;
+    }
+    else if (2 == data)
+    {
+        *mode = FAL_MAC_IP_PORT_GUARD;
+    }
+    else if (3 == data)
+    {
+        *mode = FAL_MAC_IP_VLAN_GUARD;
+    }
+    else if (4 == data)
+    {
+        *mode = FAL_MAC_IP_PORT_VLAN_GUARD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        data = 0;
+    }
+    else if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 2;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        *cmd = FAL_MAC_FRWRD;
+    }
+    else if (1 == data)
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, L3_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t route_en = 0, l3_en = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN,
+                      (a_uint8_t *) (&route_en), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, L3_EN,
+                      (a_uint8_t *) (&l3_en), sizeof (a_uint32_t))
+    SW_RTN_ON_ERROR(rv);
+
+    if (route_en && l3_en)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isis_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, j, found = 0, addr, tbl[3] = { 0 };
+    fal_intf_mac_entry_t * intf_entry;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < ISIS_INTF_MAC_ADDR_NUM; i++)
+    {
+        if (isis_mac_snap[dev_id] & (0x1 << i))
+        {
+            intf_entry = &(isis_intf_snap[dev_id][i]);
+            if ((entry->vid_low == intf_entry->vid_low)
+                    && (entry->vid_high == intf_entry->vid_high)
+                    &&(!memcmp(&entry->mac_addr, &intf_entry->mac_addr, 6)))
+            {
+                /* all same, return OK directly */
+                if (!aos_mem_cmp(intf_entry, entry, sizeof(fal_intf_mac_entry_t)))
+                {
+                    return SW_OK;
+                }
+                else
+                {
+                    /* update entry */
+                    found = 1;
+                    break;
+                }
+            }
+            else
+            {
+#if 0 /* Different mac should be ok for VID range? */
+                /* entry VID cross border, not support */
+                if ((entry->vid_low >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high))
+                {
+                    return SW_BAD_PARAM;
+                }
+
+                /* entry VID cross border, not support */
+                if ((entry->vid_high >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high))
+                {
+                    return SW_BAD_PARAM;
+                }
+#endif
+            }
+        }
+    }
+
+    if (!found)
+    {
+        for (i = 0; i < ISIS_INTF_MAC_ADDR_NUM; i++)
+        {
+            if (!(isis_mac_snap[dev_id] & (0x1 << i)))
+            {
+                intf_entry = &(isis_intf_snap[dev_id][i]);
+                break;
+            }
+        }
+    }
+
+    if (ISIS_INTF_MAC_ADDR_NUM == i)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    if ((A_FALSE == entry->ip4_route) && (A_FALSE == entry->ip6_route))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (512 <= (entry->vid_high - entry->vid_low))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2],
+                        tbl[0]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3],
+                        tbl[0]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4],
+                        tbl[0]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5],
+                        tbl[0]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0],
+                        tbl[1]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1],
+                        tbl[1]);
+
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_HIGH0, (entry->vid_high & 0xf),
+                        tbl[1]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, VID_HIGH1, (entry->vid_high >> 4),
+                        tbl[2]);
+
+    if (A_TRUE == entry->ip4_route)
+    {
+        SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP4_ROUTE, 1, tbl[2]);
+    }
+
+    if (A_TRUE == entry->ip6_route)
+    {
+        SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP6_ROUTE, 1, tbl[2]);
+    }
+
+    for (j = 0; j < 2; j++)
+    {
+        addr = ISIS_INTF_MAC_EDIT0_ADDR + (i << 4) + (j << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    for (j = 0; j < 3; j++)
+    {
+        addr = ISIS_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    isis_mac_snap[dev_id] |= (0x1 << i);
+    *intf_entry = *entry;
+    entry->entry_id = i;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                        fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t addr, tbl[3] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!(FAL_IP_ENTRY_ID_EN & del_mode))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (ISIS_INTF_MAC_ADDR_NUM <= entry->entry_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    /* clear valid bits */
+    addr = ISIS_INTF_MAC_TBL2_ADDR + (entry->entry_id << 4);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    isis_mac_snap[dev_id] &= (~(0x1 << entry->entry_id));
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                         fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, j, idx, addr, tbl[3] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id)
+    {
+        idx = 0;
+    }
+    else
+    {
+        if ((ISIS_INTF_MAC_ADDR_NUM - 1) == entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = entry->entry_id + 1;
+        }
+    }
+
+    for (i = idx; i < ISIS_INTF_MAC_ADDR_NUM; i++)
+    {
+        if (isis_mac_snap[dev_id] & (0x1 << i))
+        {
+            break;
+        }
+    }
+
+    if (ISIS_INTF_MAC_ADDR_NUM == i)
+    {
+        return SW_NO_MORE;
+    }
+
+    for (j = 0; j < 3; j++)
+    {
+        addr = ISIS_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    aos_mem_zero(entry, sizeof (fal_intf_mac_entry_t));
+
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2],
+                        tbl[0]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3],
+                        tbl[0]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4],
+                        tbl[0]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5],
+                        tbl[0]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0],
+                        tbl[1]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1],
+                        tbl[1]);
+
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, j, tbl[1]);
+    entry->vid_high = j & 0xf;
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, j, tbl[2]);
+    entry->vid_high |= ((j & 0xff) << 4);
+
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP4_ROUTE, j, tbl[2]);
+    if (j)
+    {
+        entry->ip4_route = A_TRUE;
+    }
+
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP6_ROUTE, j, tbl[2]);
+    if (j)
+    {
+        entry->ip6_route = A_TRUE;
+    }
+
+    entry->entry_id = i;
+    return SW_OK;
+}
+
+#define ISIS_WCMP_ENTRY_MAX_ID    3
+#define ISIS_WCMP_HASH_MAX_NUM    16
+#define ISIS_IP_ENTRY_MAX_ID      127
+
+#define ISIS_WCMP_HASH_TBL_ADDR   0x0e10
+#define ISIS_WCMP_NHOP_TBL_ADDR   0x0e20
+
+#if 0
+static sw_error_t
+_isis_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+    sw_error_t rv;
+    a_uint32_t i, j, addr, data;
+    a_uint8_t  idx, ptr[4] = { 0 }, pos[16] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (ISIS_WCMP_ENTRY_MAX_ID < wcmp_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISIS_WCMP_HASH_MAX_NUM < wcmp->nh_nr)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = 0; i < wcmp->nh_nr; i++)
+    {
+        if (ISIS_IP_ENTRY_MAX_ID < wcmp->nh_id[i])
+        {
+            return SW_BAD_PARAM;
+        }
+
+        idx = 4;
+        for (j = 0; j < 4; j++)
+        {
+            if (ptr[j] & 0x80)
+            {
+                if ((ptr[j] & 0x7f) == wcmp->nh_id[i])
+                {
+                    idx = j;
+                    break;
+                }
+            }
+            else
+            {
+                idx = j;
+            }
+        }
+
+        if (4 == idx)
+        {
+            return SW_BAD_PARAM;
+        }
+        else
+        {
+            ptr[idx] = (wcmp->nh_id[i] & 0x7f) | 0x80;
+            pos[i]   = idx;
+        }
+    }
+
+    data = 0;
+    for (j = 0; j < 4; j++)
+    {
+        data |= (ptr[j] << (j << 3));
+    }
+
+    addr = ISIS_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = 0;
+    for (j = 0; j < 16; j++)
+    {
+        data |= (pos[j] << (j << 1));
+    }
+
+    addr = ISIS_WCMP_HASH_TBL_ADDR + (wcmp_id << 2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+    sw_error_t rv;
+    a_uint32_t i, addr, data= 0;
+    a_uint8_t  ptr[4] = { 0 }, pos[16] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (ISIS_WCMP_ENTRY_MAX_ID < wcmp_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    wcmp->nh_nr = ISIS_WCMP_HASH_MAX_NUM;
+
+    addr = ISIS_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < 4; i++)
+    {
+        ptr[i] = (data >> (i << 3)) & 0x7f;
+    }
+
+    addr = ISIS_WCMP_HASH_TBL_ADDR + (wcmp_id << 2);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < 16; i++)
+    {
+        pos[i] = (data >> (i << 1)) & 0x3;
+    }
+
+    for (i = 0; i < 16; i++)
+    {
+        wcmp->nh_id[i] = ptr[pos[i]];
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isis_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_WCMP_HASH_KEY_SIP & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 0, data);
+    }
+
+    if (FAL_WCMP_HASH_KEY_DIP & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 0, data);
+    }
+
+    if (FAL_WCMP_HASH_KEY_SPORT & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 0, data);
+    }
+
+    if (FAL_WCMP_HASH_KEY_DPORT & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 0, data);
+    }
+
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_CTRL, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, field;
+
+    *hash_mode = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SIP, field, data);
+    if (field)
+    {
+        *hash_mode |= FAL_WCMP_HASH_KEY_SIP;
+    }
+
+    SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DIP, field, data);
+    if (field)
+    {
+        *hash_mode |= FAL_WCMP_HASH_KEY_DIP;
+    }
+
+    SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SP, field, data);
+    if (field)
+    {
+        *hash_mode |= FAL_WCMP_HASH_KEY_SPORT;
+    }
+
+    SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DP, field, data);
+    if (field)
+    {
+        *hash_mode |= FAL_WCMP_HASH_KEY_DPORT;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+isis_ip_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t i, addr, data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_FLUSH);
+    SW_RTN_ON_ERROR(rv);
+
+    isis_mac_snap[dev_id] = 0;
+    for (i = 0; i < ISIS_INTF_MAC_ADDR_NUM; i++)
+    {
+        addr = ISIS_INTF_MAC_TBL2_ADDR + (i << 4);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Add one host entry to one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry added related interface entry and ip6 base address
+       must be set at first.
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_host_add(dev_id, host_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one host entry from one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry deleted related interface entry and ip6 base address
+       must be set atfirst.
+       For del_mode please refer IP entry operation flags.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operation mode
+ * @param[in] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                 fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_host_del(dev_id, del_mode, host_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get one host entry from one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry deleted related interface entry and ip6 base address
+       must be set atfirst.
+       For get_mode please refer IP entry operation flags.
+ * @param[in] dev_id device id
+ * @param[in] get_mode get operation mode
+ * @param[out] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                 fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_host_get(dev_id, get_mode, host_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next one host entry from one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry deleted related interface entry and ip6 base address
+       must be set atfirst.
+       For next_mode please refer IP entry operation flags.
+       For get the first entry please set entry id as FAL_NEXT_ENTRY_FIRST_ID
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operation mode
+ * @param[out] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                  fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_host_next(dev_id, next_mode, host_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one host entry on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id host entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE means bind, A_FALSE means unbind
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                          a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_host_counter_bind(dev_id, entry_id, cnt_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one pppoe session entry to one host entry on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id host entry id
+ * @param[in] pppoe_id pppoe session entry id
+ * @param[in] enable A_TRUE means bind, A_FALSE means unbind
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                        a_uint32_t pppoe_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_host_pppoe_bind(dev_id, entry_id, pppoe_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets type to learn on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t flags)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_pt_arp_learn_set(dev_id, port_id, flags);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets type to learn on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t * flags)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_pt_arp_learn_get(dev_id, port_id, flags);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets type to learn on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode learning mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_arp_learn_set(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets type to learn on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode learning mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_arp_learn_get(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ip packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_source_guard_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ip packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_source_guard_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set unkonw source ip packets forwarding command on one particular device.
+ *   @details Comments:
+ *     This settin is no meaning when ip source guard not enable
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_unk_source_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unkonw source ip packets forwarding command on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_unk_source_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_arp_guard_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_arp_guard_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set unkonw source arp packets forwarding command on one particular device.
+ *   @details Comments:
+ *     This settin is no meaning when arp source guard not enable
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_arp_unk_source_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unkonw source arp packets forwarding command on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_arp_unk_source_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP unicast routing status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_route_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP unicast routing status on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_route_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one interface entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry interface entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_intf_entry_add(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one interface entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operation mode
+ * @param[in] entry interface entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                       fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_intf_entry_del(dev_id, del_mode, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next one interface entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operation mode
+ * @param[out] entry interface entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                        fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_intf_entry_next(dev_id, next_mode, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP host entry aging time on one particular device.
+ * @details   Comments:
+ *       This operation will set dynamic entry aging time on a particular device.
+ *       The unit of time is second. Because different device has differnet
+ *       hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param[in] time aging time
+ * @param[out] time actual aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_age_time_set(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP host entry aging time on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_age_time_get(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#if 0
+/**
+ * @brief Set IP WCMP table one particular device.
+ *   @details Comments:
+ *     Hardware only support 0 - 15 hash values and 4 different host tables.
+ * @param[in] dev_id device id
+ * @param[in] wcmp_id wcmp entry id
+ * @param[in] wcmp wcmp entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_wcmp_entry_set(dev_id, wcmp_id, wcmp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP WCMP table one particular device.
+ *   @details Comments:
+ *     Hardware only support 0 - 15 hash values and 4 different host tables.
+ * @param[in] dev_id device id
+ * @param[in] wcmp_id wcmp entry id
+ * @param[out] wcmp wcmp entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_wcmp_entry_get(dev_id, wcmp_id, wcmp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set IP WCMP hash key mode.
+ * @param[in] dev_id device id
+ * @param[in] hash_mode hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_wcmp_hash_mode_set(dev_id, hash_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP WCMP hash key mode.
+ * @param[in] dev_id device id
+ * @param[out] hash_mode hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ip_wcmp_hash_mode_get(dev_id, hash_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_ip_init(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = isis_ip_reset(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->ip_host_add = isis_ip_host_add;
+        p_api->ip_host_del = isis_ip_host_del;
+        p_api->ip_host_get = isis_ip_host_get;
+        p_api->ip_host_next = isis_ip_host_next;
+        p_api->ip_host_counter_bind = isis_ip_host_counter_bind;
+        p_api->ip_host_pppoe_bind = isis_ip_host_pppoe_bind;
+        p_api->ip_pt_arp_learn_set = isis_ip_pt_arp_learn_set;
+        p_api->ip_pt_arp_learn_get = isis_ip_pt_arp_learn_get;
+        p_api->ip_arp_learn_set = isis_ip_arp_learn_set;
+        p_api->ip_arp_learn_get = isis_ip_arp_learn_get;
+        p_api->ip_source_guard_set = isis_ip_source_guard_set;
+        p_api->ip_source_guard_get = isis_ip_source_guard_get;
+        p_api->ip_unk_source_cmd_set = isis_ip_unk_source_cmd_set;
+        p_api->ip_unk_source_cmd_get = isis_ip_unk_source_cmd_get;
+        p_api->ip_arp_guard_set = isis_ip_arp_guard_set;
+        p_api->ip_arp_guard_get = isis_ip_arp_guard_get;
+        p_api->arp_unk_source_cmd_set = isis_arp_unk_source_cmd_set;
+        p_api->arp_unk_source_cmd_get = isis_arp_unk_source_cmd_get;
+        p_api->ip_route_status_set = isis_ip_route_status_set;
+        p_api->ip_route_status_get = isis_ip_route_status_get;
+        p_api->ip_intf_entry_add = isis_ip_intf_entry_add;
+        p_api->ip_intf_entry_del = isis_ip_intf_entry_del;
+        p_api->ip_intf_entry_next = isis_ip_intf_entry_next;
+        p_api->ip_age_time_set = isis_ip_age_time_set;
+        p_api->ip_age_time_get = isis_ip_age_time_get;
+        p_api->ip_wcmp_hash_mode_set = isis_ip_wcmp_hash_mode_set;
+        p_api->ip_wcmp_hash_mode_get = isis_ip_wcmp_hash_mode_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isis/isis_leaky.c b/qca-ssdk/src/hsl/isis/isis_leaky.c
new file mode 100755
index 0000000..0d720be
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_leaky.c
@@ -0,0 +1,526 @@
+/*
+ * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_leaky ISIS_LEAKY
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_leaky.h"
+#include "isis_reg.h"
+
+static sw_error_t
+_isis_uc_leaky_mode_set(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+    {
+        data = 0;
+    }
+    else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_uc_leaky_mode_get(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+    }
+    else
+    {
+        *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_mc_leaky_mode_set(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+    {
+        data = 0;
+    }
+    else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_mc_leaky_mode_get(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+    }
+    else
+    {
+        *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+* @brief Set unicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isis_uc_leaky_mode_set(a_uint32_t dev_id,
+                       fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_uc_leaky_mode_set(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_uc_leaky_mode_get(a_uint32_t dev_id,
+                       fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_uc_leaky_mode_get(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Set multicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isis_mc_leaky_mode_set(a_uint32_t dev_id,
+                       fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_mc_leaky_mode_set(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mc_leaky_mode_get(a_uint32_t dev_id,
+                       fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_mc_leaky_mode_get(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_arp_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_arp_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_uc_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_uc_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_mc_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_mc_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_leaky_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->uc_leaky_mode_set = isis_uc_leaky_mode_set;
+        p_api->uc_leaky_mode_get = isis_uc_leaky_mode_get;
+        p_api->mc_leaky_mode_set = isis_mc_leaky_mode_set;
+        p_api->mc_leaky_mode_get = isis_mc_leaky_mode_get;
+        p_api->port_arp_leaky_set = isis_port_arp_leaky_set;
+        p_api->port_arp_leaky_get = isis_port_arp_leaky_get;
+        p_api->port_uc_leaky_set = isis_port_uc_leaky_set;
+        p_api->port_uc_leaky_get = isis_port_uc_leaky_get;
+        p_api->port_mc_leaky_set = isis_port_mc_leaky_set;
+        p_api->port_mc_leaky_get = isis_port_mc_leaky_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isis/isis_led.c b/qca-ssdk/src/hsl/isis/isis_led.c
new file mode 100755
index 0000000..1f52c67
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_led.c
@@ -0,0 +1,405 @@
+/*
+ * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_led ISIS_LED
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "isis_led.h"
+#include "isis_reg.h"
+
+#define MAX_LED_PATTERN_ID   2
+#define LED_PATTERN_ADDR     0x50
+
+static sw_error_t
+_isis_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                           led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    a_uint32_t data = 0, reg = 0, mode;
+    a_uint32_t addr;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (id > MAX_LED_PATTERN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    addr = LED_PATTERN_ADDR + (id << 2);
+
+    if (LED_ALWAYS_OFF == pattern->mode)
+    {
+        mode = 0;
+    }
+    else if (LED_ALWAYS_BLINK == pattern->mode)
+    {
+        mode = 1;
+    }
+    else if (LED_ALWAYS_ON == pattern->mode)
+    {
+        mode = 2;
+    }
+    else if (LED_PATTERN_MAP_EN == pattern->mode)
+    {
+        mode = 3;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data);
+
+    if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << POWER_ON_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_1000M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_100M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_10M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << COLLISION_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINKUP_OVERRIDE_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data);
+    }
+
+    if (LED_BLINK_2HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data);
+    }
+    else if (LED_BLINK_4HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data);
+    }
+    else if (LED_BLINK_8HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data);
+    }
+    else if (LED_BLINK_TXRX == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_WAN_PORT_GROUP == group)
+    {
+        reg &= 0xffff;
+        reg |= (data << 16);
+    }
+    else
+    {
+        reg &= 0xffff0000;
+        reg |= data;
+    }
+
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_WAN_PORT_GROUP == group)
+    {
+        return SW_OK;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_LAN_PORT_GROUP == group)
+    {
+        if (0 == id)
+        {
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data);
+        }
+        else if (1 == id)
+        {
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P3L2_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P2L2_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P1L2_MODE, mode, data);
+        }
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                           led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    a_uint32_t data = 0, reg = 0, tmp;
+    a_uint32_t addr;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (id > MAX_LED_PATTERN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t));
+
+    addr = LED_PATTERN_ADDR + (id << 2);
+
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_WAN_PORT_GROUP == group)
+    {
+        data = (reg >> 16) & 0xffff;
+    }
+    else
+    {
+        data = reg & 0xffff;
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data);
+    if (0 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_OFF;
+    }
+    else if (1 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_BLINK;
+    }
+    else if (2 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_ON;
+    }
+    else
+    {
+        pattern->mode = LED_PATTERN_MAP_EN;
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << POWER_ON_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_1000M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_100M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_10M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << COLLISION_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << RX_TRAFFIC_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << TX_TRAFFIC_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINKUP_OVERRIDE_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data);
+    if (0 == tmp)
+    {
+        pattern->freq = LED_BLINK_2HZ;
+    }
+    else if (1 == tmp)
+    {
+        pattern->freq = LED_BLINK_4HZ;
+    }
+    else if (2 == tmp)
+    {
+        pattern->freq = LED_BLINK_8HZ;
+    }
+    else
+    {
+        pattern->freq = LED_BLINK_TXRX;
+    }
+
+    return SW_OK;
+}
+
+/**
+* @brief Set led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group  pattern group, lan or wan
+* @param[in] id pattern id
+* @param[in] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isis_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                          led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_led_ctrl_pattern_set(dev_id, group, id, pattern);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Get led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group  pattern group, lan or wan
+* @param[in] id pattern id
+* @param[out] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isis_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                          led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_led_ctrl_pattern_get(dev_id, group, id, pattern);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_led_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->led_ctrl_pattern_set = isis_led_ctrl_pattern_set;
+        p_api->led_ctrl_pattern_get = isis_led_ctrl_pattern_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isis/isis_mac_block.c b/qca-ssdk/src/hsl/isis/isis_mac_block.c
new file mode 100755
index 0000000..6a33202
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_mac_block.c
@@ -0,0 +1,388 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_port_ctrl.h"
+#include "isis_mib.h"
+#include "isis_misc.h"
+#include "isis_reg.h"
+#include "f1_phy.h"
+
+#include <linux/autoconf.h>
+#include <linux/kthread.h>
+#include <linux/in.h>
+#include <linux/if.h>
+#include <linux/inet.h>
+#include <linux/inetdevice.h>
+#include <linux/netdevice.h>
+#include <linux/if_arp.h>
+#include <linux/skbuff.h>
+#include <linux/ip.h>
+#include <linux/udp.h>
+#include <linux/rculist_nulls.h>
+
+static struct task_struct *mac_scan_task;
+static a_bool_t qca_phy_info[7] = {A_FALSE};
+static a_bool_t qca_portvlan_mem_info[7] = {A_FALSE};
+static struct net_device *master_dev = NULL;
+static fal_port_t uplink_portid =5;
+
+static void qca_cpu_pkt_xmit(struct net_device *dev)
+{
+    if (dev)
+    {
+        arp_send(ARPOP_RREQUEST, ETH_P_RARP, 0, dev, 0, NULL,
+                 dev->dev_addr, dev->dev_addr);
+    }
+}
+
+static a_bool_t
+_isis_port_phy_connected(a_uint32_t dev_id, fal_port_t port_id)
+{
+    if ((0 == port_id) || (6 == port_id))
+    {
+        return A_FALSE;
+    }
+    else
+    {
+        return A_TRUE;
+    }
+}
+
+
+
+static sw_error_t qca_isis_rec_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+        fal_port_speed_t speed)
+{
+    sw_error_t rv;
+    a_uint32_t reg_val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+    if (FAL_SPEED_10 == speed)
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val);
+    }
+    else if (FAL_SPEED_100 == speed)
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+}
+
+
+static sw_error_t qca_isis_nor_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+        fal_port_speed_t speed, fal_port_duplex_t duplex)
+{
+    sw_error_t rv;
+    a_uint32_t reg_val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+    if (FAL_SPEED_10 == speed)
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val);
+    }
+    else if (FAL_SPEED_100 == speed)
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val);
+    }
+
+    if (duplex == FAL_FULL_DUPLEX)
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_val);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+}
+
+
+static void qca_mac_ctrl_init(void)
+{
+    hsl_dev_t *pdev = NULL;
+    fal_port_t port_id;
+    a_uint32_t dev_id = 0, reg_val = 0, reg_save = 0;
+    sw_error_t rv;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return;
+
+    /* for port property set, SSDK should not generate some limitations */
+    for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+    {
+        if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+            continue;
+
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                          (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+
+        reg_save = reg_val;
+
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                          (a_uint8_t *) (&reg_save), sizeof (a_uint32_t));
+
+    }
+
+    isis_mib_status_set(dev_id, A_TRUE);
+}
+
+static void qca_mac_phy_poll(void)
+{
+    hsl_dev_t *pdev = NULL;
+    fal_port_t port_id;
+    a_uint32_t dev_id = 0, phy_id = 0;
+    a_bool_t status, lastStatus;
+    fal_mib_info_t counter;
+    fal_port_speed_t speed;
+    fal_port_duplex_t duplex;
+    a_uint32_t txok = 0;
+    sw_error_t rv;
+    a_uint32_t reg_val;
+    a_uint32_t index;
+    fal_pbmp_t uplink_portvlanmem = 0;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return;
+
+
+    /* for port property set, SSDK should not generate some limitations */
+    for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+    {
+        if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+            continue;
+
+        rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+        if (rv != SW_OK)
+            continue;
+
+        status = f1_phy_get_link_status(dev_id, phy_id);
+
+        lastStatus = qca_phy_info[phy_id];
+
+        if (lastStatus)
+        {
+            /*phy from up to down, disable mac rx/tx*/
+            if (!status)
+            {
+
+                /*make sure UNI port doesn't forward these types of pkts*/
+                isis_port_bc_filter_set(dev_id, port_id, A_TRUE);
+                isis_port_unk_mc_filter_set(dev_id, port_id, A_TRUE);
+                isis_port_unk_uc_filter_set(dev_id, port_id, A_TRUE);
+
+                /*make sure traffic from uplink port doesn't go to UNI port*/
+                isis_portvlan_member_get(0, uplink_portid, &uplink_portvlanmem);
+                if ((0x1UL<<port_id) & uplink_portvlanmem)
+                {
+                    isis_portvlan_member_del(dev_id, uplink_portid, port_id);
+                    qca_portvlan_mem_info[port_id] =  A_TRUE;
+                    printk("%s: del UNI port %d from uplink portID %d\n", __FUNCTION__, port_id, uplink_portid);
+                }
+                isis_port_force_portvlan_set(dev_id, uplink_portid, A_TRUE);
+
+                /*make sure traffic from cpu port doesn't go to UNI port*/
+                isis_port_force_portvlan_set(dev_id, 0, A_TRUE);
+                isis_portvlan_member_del(dev_id, 0, port_id);
+
+                index = 0;
+                /*loop used to make sure that the packets in the buffer are sent out*/
+                do
+                {
+                    index ++;
+                }
+                while (index < 100);
+
+                /*disable UNI port rx/tx*/
+                isis_port_txmac_status_set(dev_id, port_id, A_FALSE);
+                isis_port_rxmac_status_set(dev_id, port_id, A_FALSE);
+                qca_phy_info[phy_id] =  status;
+
+
+                isis_get_mib_info(dev_id, port_id, &counter);
+                txok = counter.Tx64Byte +
+                       counter.Tx128Byte +
+                       counter.Tx256Byte +
+                       counter.Tx512Byte +
+                       counter.Tx1024Byte +
+                       counter.Tx1518Byte +
+                       counter.TxMaxByte;
+                printk("%s: port %d down,  counter %d\n", __FUNCTION__, port_id,
+                       txok);
+            }
+        }
+        else
+        {
+            /*phy from down to up, disable mac rx/tx*/
+            if (status)
+            {
+                HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                                  (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+                if (SW_OK == f1_phy_get_speed(dev_id, phy_id, &speed))
+                    qca_isis_rec_port_speed_set(dev_id, port_id, speed);
+
+                isis_port_txmac_status_set(dev_id, port_id, A_TRUE);
+
+                /*make sure cpu port can send pkts to UNI port*/
+                isis_portvlan_member_add(0, 0, port_id);
+                isis_port_force_portvlan_set(0, 0, A_FALSE);
+
+                /*detct port tx counts*/
+                isis_get_mib_info(dev_id, port_id, &counter);
+                txok = counter.Tx64Byte +
+                       counter.Tx128Byte +
+                       counter.Tx256Byte +
+                       counter.Tx512Byte +
+                       counter.Tx1024Byte +
+                       counter.Tx1518Byte +
+                       counter.TxMaxByte;
+                printk("%s: counter before sending pkts %d for port %d\n", __FUNCTION__,
+                       txok, port_id);
+
+                /*make sure cpu port can send pkts to UNI port*/
+                isis_port_bc_filter_set(dev_id, port_id, A_FALSE);
+                isis_port_unk_mc_filter_set(dev_id, port_id, A_FALSE);
+                isis_port_unk_uc_filter_set(dev_id, port_id, A_FALSE);
+
+                do
+                {
+                    qca_cpu_pkt_xmit(master_dev);
+                    memset(&counter, 0, sizeof(fal_mib_info_t));
+                    isis_get_mib_info(dev_id, port_id, &counter);
+                    txok = counter.Tx64Byte +
+                           counter.Tx128Byte +
+                           counter.Tx256Byte +
+                           counter.Tx512Byte +
+                           counter.Tx1024Byte +
+                           counter.Tx1518Byte +
+                           counter.TxMaxByte;
+                    printk("%s: cpu send pkts for port_id %d\n", __FUNCTION__, port_id);
+                }
+                while(txok == 0);
+
+                f1_phy_get_speed(dev_id, phy_id, &speed);
+                f1_phy_get_duplex(dev_id, phy_id, &duplex);
+                isis_port_txmac_status_set(dev_id, port_id, A_FALSE);
+                isis_port_rxmac_status_set(dev_id, port_id, A_FALSE);
+                qca_isis_nor_port_speed_set(dev_id, port_id, speed, duplex);
+                isis_port_txmac_status_set(dev_id, port_id, A_TRUE);
+                isis_port_rxmac_status_set(dev_id, port_id, A_TRUE);
+
+                /*restore uplink port-base vlan state*/
+                if (qca_portvlan_mem_info[port_id])
+                {
+                    isis_portvlan_member_add(0, uplink_portid, port_id);
+                    qca_portvlan_mem_info[port_id] =  A_FALSE;
+                    printk("%s: add UNI port %d to uplink portID %d\n", __FUNCTION__, port_id, uplink_portid);
+                }
+                isis_port_force_portvlan_set(0, uplink_portid, A_FALSE);
+
+                qca_phy_info[phy_id] =  status;
+
+            }
+
+        }
+
+    }
+}
+
+static a_int32_t
+qca_mac_scan_thread(void *param)
+{
+#define QCA_MAC_SCAN_POLLING_MSEC         500
+
+    qca_mac_ctrl_init();
+
+    while(1)
+    {
+
+        qca_mac_phy_poll();
+
+        msleep_interruptible(QCA_MAC_SCAN_POLLING_MSEC);
+    }
+
+
+    return 0;
+}
+
+void
+qca_mac_scan_helper_init(void)
+{
+    const char mac_thread_name[] = "mac_scan";
+
+    mac_scan_task = kthread_create(qca_mac_scan_thread, NULL, mac_thread_name);
+
+
+    if(IS_ERR(mac_scan_task))
+    {
+        aos_printk("thread: %s create fail\n", mac_thread_name);
+        return;
+    }
+
+    wake_up_process(mac_scan_task);
+
+    printk("thread: %s create success pid:%d\n",
+           mac_thread_name, mac_scan_task->pid);
+}
+
+
+void
+qca_mac_scan_helper_exit(void)
+{
+    if(mac_scan_task)
+    {
+        kthread_stop(mac_scan_task);
+    }
+}
+
+void qca_set_master_dev(struct net_device *dev)
+{
+    master_dev = dev;
+
+}
+
+
+
diff --git a/qca-ssdk/src/hsl/isis/isis_mib.c b/qca-ssdk/src/hsl/isis/isis_mib.c
new file mode 100755
index 0000000..d2f9d3c
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_mib.c
@@ -0,0 +1,663 @@
+/*
+ * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_mib ISIS_MIB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_mib.h"
+#include "isis_reg.h"
+
+static sw_error_t
+_isis_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                   fal_mib_info_t * mib_info)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFcsErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxAllignErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxRunt = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFragment = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxTooLong = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxOverFlow = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Filtered = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxUnderRun = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxOverSize = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxCollision = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxAbortCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMultiCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxSingalCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxExcDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxLateCol = val;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                   fal_mib_info_t * mib_info)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFcsErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxAllignErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxRunt = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFragment = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxTooLong = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxOverFlow = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Filtered = val;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                   fal_mib_info_t * mib_info)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxUnderRun = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxOverSize = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxCollision = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxAbortCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMultiCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxSingalCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxExcDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxLateCol = val;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, MIB_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, MIB_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Get mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                  fal_mib_info_t * mib_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_get_mib_info(dev_id, port_id, mib_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get RX mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                  fal_mib_info_t * mib_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_get_rx_mib_info(dev_id, port_id, mib_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get TX mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                  fal_mib_info_t * mib_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_get_tx_mib_info(dev_id, port_id, mib_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_mib_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_mib_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_mib_init(a_uint32_t dev_id)
+{
+#ifndef HSL_STANDALONG
+    hsl_api_t *p_api;
+#endif
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->get_mib_info   = isis_get_mib_info;
+    p_api->get_rx_mib_info   = isis_get_rx_mib_info;
+    p_api->get_tx_mib_info   = isis_get_tx_mib_info;
+    p_api->mib_status_set = isis_mib_status_set;
+    p_api->mib_status_get = isis_mib_status_get;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isis/isis_mirror.c b/qca-ssdk/src/hsl/isis/isis_mirror.c
new file mode 100755
index 0000000..16a7d21
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_mirror.c
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_mirror ISIS_MIRROR
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_mirror.h"
+#include "isis_reg.h"
+
+static sw_error_t
+_isis_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv;
+	a_uint32_t val;
+
+	HSL_DEV_ID_CHECK(dev_id);
+	if (port_id != MIRROR_ANALYZER_NONE) {
+		if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) {
+			return SW_BAD_PARAM;
+		}
+	}
+	val = port_id;
+	HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+	return rv;
+}
+
+static sw_error_t
+_isis_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *port_id = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+ *   @details  Comments:
+ *   The analysis port works for both ingress and egress mirror.
+ * @brief Set mirror analyzer port on particular a device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_mirr_analysis_port_set(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mirror analysis port on particular a device.
+ * @param[in] dev_id device id
+ * @param[out] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_mirr_analysis_port_get(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_mirr_port_in_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_mirr_port_in_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_mirr_port_eg_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_mirr_port_eg_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_mirr_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->mirr_analysis_port_set = isis_mirr_analysis_port_set;
+        p_api->mirr_analysis_port_get = isis_mirr_analysis_port_get;
+        p_api->mirr_port_in_set = isis_mirr_port_in_set;
+        p_api->mirr_port_in_get = isis_mirr_port_in_get;
+        p_api->mirr_port_eg_set = isis_mirr_port_eg_set;
+        p_api->mirr_port_eg_get = isis_mirr_port_eg_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isis/isis_misc.c b/qca-ssdk/src/hsl/isis/isis_misc.c
new file mode 100755
index 0000000..b2a8d3d
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_misc.c
@@ -0,0 +1,1835 @@
+/*
+ * Copyright (c) 2012, 2015-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_misc ISIS_MISC
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_misc.h"
+#include "isis_reg.h"
+#include "hsl_phy.h"
+
+
+#define ISIS_MAX_FRMAE_SIZE      9216
+
+#define ARP_REQ_EN_OFFSET    6
+#define ARP_ACK_EN_OFFSET    5
+#define DHCP_EN_OFFSET       4
+#define EAPOL_EN_OFFSET      3
+
+#define ISIS_SWITCH_INT_PHY_INT   0x8000
+
+static sw_error_t
+_isis_port_misc_property_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable, a_uint32_t item)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (3 >= port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        reg &= ~(0x1UL << ((port_id << 3) + item));
+        reg |= (val << ((port_id << 3) + item));
+
+        HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        reg &= ~(0x1UL << (((port_id - 4) << 3) + item));
+        reg |= (val << (((port_id - 4) << 3) + item));
+
+        HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    return rv;
+}
+
+static sw_error_t
+_isis_port_misc_property_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable, a_uint32_t item)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (3 >= port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        val = (reg >> ((port_id << 3) + item)) & 0x1UL;
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL;
+    }
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISIS_MAX_FRMAE_SIZE < size)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = size;
+    HSL_REG_FIELD_SET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *size = data;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t) 0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t) 0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t) 0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_FRWRD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_FRWRD == cmd)
+    {
+        val = 2;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else if (0 == val)
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_FRWRD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+#define ISIS_MAX_PPPOE_SESSION  16
+#define ISIS_MAX_SESSION_ID     0xffff
+
+static sw_error_t
+_isis_pppoe_session_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, i, valid, id, entry_idx = ISIS_MAX_PPPOE_SESSION;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (session_tbl->session_id > ISIS_MAX_SESSION_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((A_FALSE == session_tbl->multi_session)
+            && (A_TRUE == session_tbl->uni_session))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((A_FALSE == session_tbl->multi_session)
+            && (A_FALSE == session_tbl->uni_session))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = 0; i < ISIS_MAX_PPPOE_SESSION; i++)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+        if (!valid)
+        {
+            entry_idx = i;
+        }
+        else if (id == session_tbl->session_id)
+        {
+            return SW_ALREADY_EXIST;
+        }
+    }
+
+    if (ISIS_MAX_PPPOE_SESSION == entry_idx)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    if (A_TRUE == session_tbl->uni_session)
+    {
+        SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 2, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 1, reg);
+    }
+    SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, session_tbl->session_id,
+                        reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, entry_idx,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    session_tbl->entry_id = entry_idx;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_pppoe_session_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, i, valid, id;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (session_tbl->session_id > ISIS_MAX_SESSION_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = 0; i < ISIS_MAX_PPPOE_SESSION; i++)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+        if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id))
+        {
+            SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 0, reg);
+            SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, 0, reg);
+            HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, i,
+                              (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+            return rv;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isis_pppoe_session_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, i, valid, id;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (session_tbl->session_id > ISIS_MAX_SESSION_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = 0; i < ISIS_MAX_PPPOE_SESSION; i++)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+        if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id))
+        {
+            if (1 == valid)
+            {
+                session_tbl->multi_session = A_TRUE;
+                session_tbl->uni_session = A_FALSE;
+            }
+            else
+            {
+                session_tbl->multi_session = A_TRUE;
+                session_tbl->uni_session = A_TRUE;
+            }
+
+            session_tbl->entry_id = i;
+            return SW_OK;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isis_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+                           a_uint32_t id)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    if (ISIS_MAX_PPPOE_SESSION <= index)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISIS_MAX_SESSION_ID < id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    reg = 0;
+    SW_SET_REG_BY_FIELD(PPPOE_EDIT, EDIT_ID, id, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isis_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+                           a_uint32_t * id)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, tmp;
+
+    if (ISIS_MAX_PPPOE_SESSION <= index)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    tmp = 0;
+    SW_GET_FIELD_BY_REG(PPPOE_EDIT, EDIT_ID, tmp, reg);
+    *id = tmp;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (intr_mask & FAL_SWITCH_INTR_LINK_STATUS)
+    {
+        reg |= ISIS_SWITCH_INT_PHY_INT;
+    }
+    else
+    {
+        reg &= (~ISIS_SWITCH_INT_PHY_INT);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    *intr_mask = 0;
+    HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (reg & ISIS_SWITCH_INT_PHY_INT)
+    {
+        *intr_mask |= FAL_SWITCH_INTR_LINK_STATUS;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    *intr_status = 0;
+    HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (reg & ISIS_SWITCH_INT_PHY_INT)
+    {
+        *intr_status |= FAL_SWITCH_INTR_LINK_STATUS;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    reg = 0;
+    if (intr_status & FAL_SWITCH_INTR_LINK_STATUS)
+    {
+        reg |= ISIS_SWITCH_INT_PHY_INT;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_link_intr_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_intr_mask_set)
+	  return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_intr_mask_set(dev_id, phy_id, intr_mask_flag);
+    return rv;
+}
+
+static sw_error_t
+_isis_port_link_intr_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_intr_mask_get)
+	  return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_intr_mask_get(dev_id, phy_id, intr_mask_flag);
+    return rv;
+}
+
+static sw_error_t
+_isis_port_link_intr_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_intr_status_get)
+	  return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_intr_status_get(dev_id, phy_id, intr_mask_flag);
+    return rv;
+}
+
+/**
+ * @brief Set max frame size which device can received on a particular device.
+ * @details    Comments:
+ * The granularity of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[in] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_frame_max_size_set(dev_id, size);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max frame size which device can received on a particular device.
+ * @details   Comments:
+ *    The unit of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[out] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_frame_max_size_get(dev_id, size);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown unicast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown unicast packets filter on one port then unknown
+ *   unicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_unk_uc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flooding status of unknown unicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_unk_uc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown multicast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown multicast packets filter on one port then unknown
+ *   multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_unk_mc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/** @brief Get flooding status of unknown multicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_unk_mc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of broadcast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown multicast packets filter on one port then unknown
+ *   multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_bc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/** @brief Get flooding status of broadcast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_bc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cpu_port_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_cpu_port_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set pppoe packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling pppoe packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_pppoe_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get pppoe packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_pppoe_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set pppoe packets hardware acknowledgement status on particular device.
+ * @details     comments:
+ *   Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_pppoe_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get pppoe packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_pppoe_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dhcp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_misc_property_set(dev_id, port_id, enable, DHCP_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dhcp packets hardware acknowledgement status on particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_misc_property_get(dev_id, port_id, enable, DHCP_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling arp packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_arp_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_arp_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set eapol packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling eapol packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_eapol_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get eapol packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_eapol_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a pppoe session entry to a particular device.
+ *        The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_session_table_add(a_uint32_t dev_id,
+                             fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_pppoe_session_add(dev_id, session_tbl);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a pppoe session entry from a particular device.
+ *        The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_session_table_del(a_uint32_t dev_id,
+                             fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_pppoe_session_del(dev_id, session_tbl);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a pppoe session entry from a particular device.
+ *        The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[out] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_session_table_get(a_uint32_t dev_id,
+                             fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_pppoe_session_get(dev_id, session_tbl);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set a pppoe session id entry to a particular device.
+ *        The entry only for pppoe/ppp header add.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+                          a_uint32_t id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_pppoe_session_id_set(dev_id, index, id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a pppoe session id entry from a particular device.
+ *        The entry only for pppoe/ppp header add.
+ * @param[in] dev_id device id
+ * @param[out] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+                          a_uint32_t * id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_pppoe_session_id_get(dev_id, index, id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_misc_property_set(dev_id, port_id, enable, EAPOL_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_misc_property_get(dev_id, port_id, enable, EAPOL_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ripv1_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_ripv1_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp req packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_misc_property_set(dev_id, port_id, enable,
+                                      ARP_REQ_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp req packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_misc_property_get(dev_id, port_id, enable,
+                                      ARP_REQ_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp ack packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_misc_property_set(dev_id, port_id, enable,
+                                      ARP_ACK_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp ack packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_misc_property_get(dev_id, port_id, enable,
+                                      ARP_ACK_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set switch interrupt mask on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_mask mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_intr_mask_set(dev_id, intr_mask);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get switch interrupt mask on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_mask mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_intr_mask_get(dev_id, intr_mask);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get switch interrupt status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_status status
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_intr_status_get(dev_id, intr_status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Clear switch interrupt status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_status status
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_intr_status_clear(dev_id, intr_status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set link interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isis_port_link_intr_mask_set(dev_id, port_id, intr_mask_flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get link interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_link_intr_mask_get(dev_id, port_id, intr_mask_flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get link interrupt status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_link_intr_status_get(dev_id, port_id, intr_mask_flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_misc_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->frame_max_size_set = isis_frame_max_size_set;
+        p_api->frame_max_size_get = isis_frame_max_size_get;
+        p_api->port_unk_uc_filter_set = isis_port_unk_uc_filter_set;
+        p_api->port_unk_uc_filter_get = isis_port_unk_uc_filter_get;
+        p_api->port_unk_mc_filter_set = isis_port_unk_mc_filter_set;
+        p_api->port_unk_mc_filter_get = isis_port_unk_mc_filter_get;
+        p_api->port_bc_filter_set = isis_port_bc_filter_set;
+        p_api->port_bc_filter_get = isis_port_bc_filter_get;
+        p_api->cpu_port_status_set = isis_cpu_port_status_set;
+        p_api->cpu_port_status_get = isis_cpu_port_status_get;
+        p_api->pppoe_cmd_set = isis_pppoe_cmd_set;
+        p_api->pppoe_cmd_get = isis_pppoe_cmd_get;
+        p_api->pppoe_status_set = isis_pppoe_status_set;
+        p_api->pppoe_status_get = isis_pppoe_status_get;
+        p_api->port_dhcp_set = isis_port_dhcp_set;
+        p_api->port_dhcp_get = isis_port_dhcp_get;
+        p_api->arp_cmd_set = isis_arp_cmd_set;
+        p_api->arp_cmd_get = isis_arp_cmd_get;
+        p_api->eapol_cmd_set = isis_eapol_cmd_set;
+        p_api->eapol_cmd_get = isis_eapol_cmd_get;
+        p_api->pppoe_session_table_add = isis_pppoe_session_table_add;
+        p_api->pppoe_session_table_del = isis_pppoe_session_table_del;
+        p_api->pppoe_session_table_get = isis_pppoe_session_table_get;
+        p_api->pppoe_session_id_set = isis_pppoe_session_id_set;
+        p_api->pppoe_session_id_get = isis_pppoe_session_id_get;
+        p_api->eapol_status_set = isis_eapol_status_set;
+        p_api->eapol_status_get = isis_eapol_status_get;
+        p_api->ripv1_status_set = isis_ripv1_status_set;
+        p_api->ripv1_status_get = isis_ripv1_status_get;
+        p_api->port_arp_req_status_set = isis_port_arp_req_status_set;
+        p_api->port_arp_req_status_get = isis_port_arp_req_status_get;
+        p_api->port_arp_ack_status_set = isis_port_arp_ack_status_set;
+        p_api->port_arp_ack_status_get = isis_port_arp_ack_status_get;
+        p_api->intr_mask_set = isis_intr_mask_set;
+        p_api->intr_mask_get = isis_intr_mask_get;
+        p_api->intr_status_get = isis_intr_status_get;
+        p_api->intr_status_clear = isis_intr_status_clear;
+        p_api->intr_port_link_mask_set = isis_intr_port_link_mask_set;
+        p_api->intr_port_link_mask_get = isis_intr_port_link_mask_get;
+        p_api->intr_port_link_status_get = isis_intr_port_link_status_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/isis/isis_multicast_acl.c b/qca-ssdk/src/hsl/isis/isis_multicast_acl.c
new file mode 100755
index 0000000..19ad9c2
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_multicast_acl.c
@@ -0,0 +1,985 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#include "fal_nat.h"
+#include "fal_ip.h"
+#include "hsl_api.h"
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_igmp.h"
+#include "isis_reg.h"
+#include "fal_multi.h"
+#include "isis_acl.h"
+#include "sal/os/aos_lock.h"
+
+#if 0
+/**
+ * I/F prototype for complete igmpv3 & mldv2 support
+ */
+
+/*supports 32 entries*/
+#define FAL_IGMP_SG_ENTRY_MAX 32
+
+typedef enum
+{
+    FAL_ADDR_IPV4 = 0,
+    FAL_ADDR_IPV6
+} fal_addr_type_t;
+
+typedef struct
+{
+    fal_addr_type_t type;
+    union
+    {
+        fal_ip4_addr_t ip4_addr;
+        fal_ip6_addr_t ip6_addr;
+    } u;
+} fal_igmp_sg_addr_t;
+
+typedef struct
+{
+    fal_igmp_sg_addr_t source;
+    fal_igmp_sg_addr_t group;
+    fal_pbmp_t port_map;
+} fal_igmp_sg_entry_t;
+
+/**
+ * @brief set PortMap of IGMP sg entry.
+ *        search entry according to source/group address,
+ *        update PortMap if SG entry is found, otherwise create a new sg entry.
+ * @param[in] dev_id device id
+ * @param[in-out] entry SG entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+/**
+ * @brief clear PortMap of IGMP sg entry.
+ *        search entry according to source/group address,
+ *        update PortMap if SG entry is found, delete the entry in case PortMap was 0.
+ *        SW_NOT_FOUND will be returned in case search failed.
+ * @param[in] dev_id device id
+ * @param[in-out] entry SG entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+#define MULTI_DEBUG_
+#ifdef MULTI_DEBUG_
+#define MULTI_DEBUG(x...) aos_printk(x)
+#else
+#define MULTI_DEBUG(x...)
+#endif
+
+#define FAL_ACL_LIST_MULTICAST 55
+#define FAL_MULTICAST_PRI   5
+
+#define MULT_ACTION_SET      1
+#define MULT_ACTION_CLEAR    1
+
+static a_uint32_t rule_nr=1;
+
+typedef struct
+{
+    a_uint8_t index; //MAX is 32
+    fal_igmp_sg_entry_t entry; //Stores the specific ACL rule info
+} multi_acl_info_t;
+#endif
+
+static a_uint32_t rule_nr=1;
+
+void
+isis_multicast_init(a_uint32_t dev_id);
+
+HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t pos, fal_igmp_sg_entry_t * entry);
+
+static multi_acl_info_t multi_acl_info[FAL_IGMP_SG_ENTRY_MAX];
+static multi_acl_info_t multi_acl_group[FAL_IGMP_SG_ENTRY_MAX];
+
+static int ip6_addr_is_null(fal_ip6_addr_t *ip6)
+{
+    if (NULL == ip6)
+    {
+        aos_printk("Invalid ip6 address\n");
+        return -1;
+    }
+    if(0 == ip6->ul[0] && 0 == ip6->ul[1] && 0 == ip6->ul[2] && 0 == ip6->ul[3])
+        return 1;
+    else
+        return 0;
+}
+static int multi_source_is_null(fal_igmp_sg_addr_t *s)
+{
+    if (NULL == s)
+    {
+        aos_printk("Invalid source address\n");
+        return -1;
+    }
+    if(0 == s->type && 0==s->u.ip4_addr)
+        return 1;
+    if(1 == s->type && 1 == ip6_addr_is_null(&(s->u.ip6_addr)))
+        return 1;
+
+    return 0;
+}
+
+HSL_LOCAL int iterate_multicast_acl_rule(int list_id, int start_n)
+{
+    a_uint32_t dev_id=0;
+    a_uint32_t rule_id;
+    sw_error_t ret;
+    fal_acl_rule_t  rule= {0};
+
+    if(start_n>=FAL_IGMP_SG_ENTRY_MAX || start_n < 0)
+    {
+        return -1;
+    }
+
+    for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+    {
+        ret = isis_acl_rule_query(dev_id, list_id, rule_id, &rule);
+
+        if (ret==SW_NOT_FOUND )
+            break;//NOT found in ACL rule
+        if((rule_id+start_n)>=FAL_IGMP_SG_ENTRY_MAX)
+        {
+            return -1;
+        }
+        multi_acl_info[rule_id+start_n].index = rule_id; // consider here... index is NOT related start_n
+        //MULTI_DEBUG("normal query1: rule dest_ip4_val=%x, src ip4=%x, dst_ip6=%x, ports=%x\n",
+        //rule.dest_ip4_val, rule.src_ip4_val, rule.dest_ip6_val.ul[0], rule.ports);
+
+        if(rule.dest_ip4_val !=0 && ip6_addr_is_null(&rule.dest_ip6_val))  //only ip4
+        {
+            multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV4;
+            multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV4;
+            multi_acl_info[rule_id+start_n].entry.group.u.ip4_addr = rule.dest_ip4_val;
+            multi_acl_info[rule_id+start_n].entry.source.u.ip4_addr = rule.src_ip4_val;
+            multi_acl_info[rule_id+start_n].entry.port_map= rule.ports;
+        }
+        else if(rule.dest_ip4_val ==0 && !ip6_addr_is_null(&rule.dest_ip6_val))  //only ip6
+        {
+            multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV6;
+            multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV6;
+            memcpy(&(multi_acl_info[rule_id+start_n].entry.group.u.ip6_addr), &(rule.dest_ip6_val), sizeof(rule.dest_ip6_val));
+            memcpy(&(multi_acl_info[rule_id+start_n].entry.source.u.ip6_addr), &(rule.src_ip6_val), sizeof(rule.src_ip6_val));
+            multi_acl_info[rule_id+start_n].entry.port_map= rule.ports;
+        }
+    }
+
+    return rule_id+start_n;
+}
+/*
+** Iterate the total 32 multicast ACL entries.
+    After the function completes:
+         1. Stores all multicast related ACL rules in multi_acl_info[32]
+         2. return the number of multicast related ACL rules
+*/
+HSL_LOCAL a_uint32_t isis_multicast_acl_query(void)
+{
+    int start_n;
+    int total_n;
+    //a_uint32_t i;
+
+    start_n = iterate_multicast_acl_rule(FAL_ACL_LIST_MULTICAST, 0);
+    if(-1 == start_n)
+        aos_printk("ACL rule1 is FULL\n");
+    total_n = iterate_multicast_acl_rule(FAL_ACL_LIST_MULTICAST+1, start_n);
+    if(-1 == total_n)
+        aos_printk("ACL rule2 is FULL\n");
+
+    MULTI_DEBUG("KKK, the total ACL rule number is %d, (G,S) number=%d\n", total_n, start_n);
+    /*
+    for(i=0;i<total_n;i++)
+    MULTI_DEBUG("KKK, indx=%d, multi_acl_info[%d].entry=[%d][%x]\n", multi_acl_info[i].index,i,
+        multi_acl_info[i].entry.group.type, multi_acl_info[i].entry.group.u.ip4_addr );
+        */
+
+    return total_n;
+}
+
+HSL_LOCAL a_uint32_t isis_multicast_acl_total_n(a_uint32_t list_id)
+{
+    a_uint32_t dev_id=0;
+    a_uint32_t ret;
+    a_uint32_t rule_id;
+    fal_acl_rule_t  rule= {0};
+
+    for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+    {
+        ret = isis_acl_rule_query(dev_id, list_id,
+                                  rule_id, &rule);
+        if(ret==SW_NOT_FOUND)
+            return rule_id;
+
+    }
+    return 0;
+}
+
+#define ISIS_FILTER_ACT_ADDR    0x5a000
+#define ISIS_FILTER_MSK_ADDR    0x59000
+HSL_LOCAL sw_error_t multi_portmap_aclreg_set_all(a_uint32_t pos, fal_igmp_sg_entry_t * entry)
+{
+    a_uint32_t i, base, addr;
+    a_uint32_t dev_id=0;
+    a_uint32_t msk_valid=0;
+    sw_error_t rv = SW_OK;
+
+    /*  2'b00:start; 2'b01:continue; 2'b10:end; 2'b11:start&end*/
+    for(i=pos; i<pos+4; i++)
+    {
+        base = ISIS_FILTER_MSK_ADDR +(i<<5);
+        addr = base+(4<<2); //fifth byte
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&msk_valid),
+                              sizeof (a_uint32_t));
+
+        SW_RTN_ON_ERROR(rv);
+        if ((((msk_valid>>6)&0x3) == 0x3) || (((msk_valid>>6)&0x3) == 0x2))
+        {
+            rv = multi_portmap_aclreg_set(i, entry);
+            break;
+        }
+        else if ((((msk_valid>>6)&0x3)) == 0x0 || (((msk_valid>>6)&0x3) == 0x1))
+        {
+            rv = multi_portmap_aclreg_set(i, entry);
+            continue;
+        }
+        else
+        {
+            aos_printk("The rule valid bit:6 7 is wrong!!!");
+            break;
+        }
+    }
+    return rv;
+}
+HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t pos, fal_igmp_sg_entry_t * entry)
+{
+    a_uint32_t i, base, addr;
+    a_uint32_t dev_id=0;
+    sw_error_t rv;
+    a_uint32_t act[3]= {0};
+    fal_pbmp_t pm;
+
+    pm = entry->port_map;
+
+    base = ISIS_FILTER_ACT_ADDR + (pos << 4);
+    for (i = 0; i < 3; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&act[i]),
+                              sizeof (a_uint32_t));
+        //MULTI_DEBUG("2:Get register value  0x%x =%x\n", addr, act[i]);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    act[1] &= ~(0x7<<29); // clear the high 3 bits
+    act[1] |= (pm&0x7)<<29;  //the low 3 bits of pm means redirect port 0,1,2
+
+    /* New modification: update acl ACTION register from DENY to redirect */
+    if (((act[2]>>6)&0x7) == 0x7) //DENY mode
+    {
+        if(pm)
+        {
+            act[2] &= ~(0x7<<6);//clear DENY bits
+            act[2] |= (0x1<<4); //DES_PORT_EN set 1, enable
+        }
+    }
+    else if (((act[2]>>4)&0x1) == 0x1) //redirect mode
+    {
+        if(pm==0)
+        {
+            act[2] &= ~(0x1<<4);//clear redirect bits
+            act[2] |= (0x7<<6); //set to DENY
+        }
+    }
+
+    act[2] &= ~0xf; //clear the low 4 bits of port 3,4,5,6
+    act[2] |= (pm>>3)&0xf;
+
+    addr = base + (1<<2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&act[1]), sizeof (a_uint32_t));
+    addr = base + (2<<2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&act[2]), sizeof (a_uint32_t));
+    MULTI_DEBUG("pos=%d, before sync portmap, the new act=%x %x\n", pos, act[1],act[2]);
+    if((rv = isis_acl_rule_sync_multi_portmap(dev_id, pos, act)) < 0)
+        aos_printk("Sync multicast portmap error\n");
+    return rv;
+}
+
+HSL_LOCAL int multi_get_dp(void)
+{
+    a_uint32_t addr;
+    a_uint32_t dev_id=0;
+    sw_error_t rv;
+    int val=0;
+
+    addr = 0x624;//GLOBAL_FW_CTRL1
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&val),
+                          sizeof (a_uint32_t));
+    if (rv != SW_OK)
+        aos_printk("Get entry value error\n");
+
+    val = (val>>24)&0x7f; //30:24, IGMP_JOIN_LEAVE_DP
+
+    return val;
+}
+static int old_bind_p=-1;
+HSL_LOCAL int multi_acl_bind(void)
+{
+    int bind_p;
+    int i;
+
+    bind_p = multi_get_dp();
+    if(bind_p == old_bind_p)
+        return 0;
+    old_bind_p = bind_p;
+
+    for(i=0; i<6; i++)
+    {
+        isis_acl_list_unbind(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+        isis_acl_list_unbind(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+    }
+
+    if(bind_p==0)
+    {
+        for(i=0; i<6; i++)
+        {
+            isis_acl_list_bind(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+            isis_acl_list_bind(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+        }
+    }
+    else
+    {
+        for(i=0; i<6; i++)
+            if((bind_p>>i) &0x1)
+            {
+                isis_acl_list_bind(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+                isis_acl_list_bind(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+            }
+            else
+                continue;
+    }
+	return 0;
+}
+/*
+** Only update the related portmap from the privious input.
+*/
+HSL_LOCAL sw_error_t isis_multicast_acl_update( int list_id, int acl_index, fal_igmp_sg_entry_t * entry, int action)
+{
+    a_uint32_t dev_id=0;
+    a_uint32_t rule_pos;
+    sw_error_t rv = SW_OK;
+
+    if(acl_index<0)
+    {
+        aos_printk("Something is wrong...\n");
+        return SW_FAIL;
+    }
+
+    rule_pos = isis_acl_rule_get_offset(dev_id, list_id, multi_acl_group[acl_index].index);
+    if(MULT_ACTION_SET == action)
+    {
+        multi_acl_group[acl_index].entry.port_map |= entry->port_map;
+        if(entry->port_map == 0)
+        {
+            multi_acl_group[acl_index].entry.port_map = 0;
+        }
+    }
+    else if(MULT_ACTION_CLEAR == action)
+        multi_acl_group[acl_index].entry.port_map &= ~(entry->port_map);
+
+    rv = multi_portmap_aclreg_set_all(rule_pos, &multi_acl_group[acl_index].entry);
+
+    multi_acl_bind(); //Here need extra bind since IGMP join/leave would happen
+    return rv;
+}
+
+HSL_LOCAL sw_error_t isis_multicast_acl_del(int list_id, int index)
+{
+    sw_error_t rv;
+    int rule_id;
+
+    rule_id = multi_acl_group[index].index;
+
+    rv = isis_acl_rule_delete(0, list_id, rule_id, 1);
+    multi_acl_bind(); //Here need extra bind since IGMP join/leave would happen
+    return rv;
+}
+
+/*
+** Add new acl rule with parameters: DIP, SIP, redirect port.
+*/
+HSL_LOCAL sw_error_t isis_multicast_acl_add(int list_id, fal_igmp_sg_entry_t * entry)
+{
+    sw_error_t val;
+    a_uint32_t pos;
+    fal_acl_rule_t acl= {0};
+
+    /* IPv4 multicast */
+    if( entry->group.type == FAL_ADDR_IPV4 )
+    {
+        MULTI_DEBUG("KKK1, group[%d][%x], source[%d][%x]\n",entry->group.type,
+                    entry->group.u.ip4_addr, entry->source.type, entry->source.u.ip4_addr);
+
+        acl.rule_type = FAL_ACL_RULE_IP4;
+
+        if(entry->group.u.ip4_addr!= 0)
+        {
+            acl.dest_ip4_val = entry->group.u.ip4_addr;
+            acl.dest_ip4_mask = 0xffffffff;//e->ip.dmsk.s_addr;
+            FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_DIP);
+        }
+        if(entry->source.u.ip4_addr!= 0)
+        {
+            acl.src_ip4_val = entry->source.u.ip4_addr;
+            acl.src_ip4_mask = 0xffffffff;//e->ip.smsk.s_addr;
+            FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_SIP);
+        }
+        if( entry->port_map==0 )
+            FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY);
+        else
+            //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+            FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT );
+
+        /* Be careful, _isis_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */
+        if( entry->port_map )
+        {
+            FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT);
+            acl.ports = entry->port_map;
+        }
+    }
+    else if( entry->group.type == FAL_ADDR_IPV6 )
+    {
+        MULTI_DEBUG("KKK2, group[%d][%x], source[%d][%x], pm=%x\n",entry->group.type,
+                    entry->group.u.ip6_addr.ul[0], entry->source.type, entry->source.u.ip6_addr.ul[0], entry->port_map);
+
+        acl.rule_type = FAL_ACL_RULE_IP6;
+
+        if(!ip6_addr_is_null(&(entry->group.u.ip6_addr)))
+        {
+            memcpy(&acl.dest_ip6_val, &(entry->group.u.ip6_addr), sizeof(entry->group.u.ip6_addr));
+            acl.dest_ip6_mask.ul[0] = 0xffffffff;
+            acl.dest_ip6_mask.ul[1] = 0xffffffff;
+            acl.dest_ip6_mask.ul[2] = 0xffffffff;
+            acl.dest_ip6_mask.ul[3] = 0xffffffff;
+            FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_DIP);
+        }
+        if(!ip6_addr_is_null(&(entry->source.u.ip6_addr)))
+        {
+            memcpy(&acl.src_ip6_val, &(entry->source.u.ip6_addr), sizeof(entry->source.u.ip6_addr));
+            acl.src_ip6_mask.ul[0] = 0xffffffff;
+            acl.src_ip6_mask.ul[1] = 0xffffffff;
+            acl.src_ip6_mask.ul[2] = 0xffffffff;
+            acl.src_ip6_mask.ul[3] = 0xffffffff;
+            FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_SIP);
+        }
+
+        if( entry->port_map==0 )
+            FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY);
+        else
+            //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+            FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT );
+
+        /* Be careful, _isis_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */
+        if( entry->port_map )
+        {
+            FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT);
+            acl.ports = entry->port_map;
+        }
+    }
+
+    pos = isis_multicast_acl_total_n(list_id);
+
+    MULTI_DEBUG("In isis_multicast_acl_add, list_id=%d, rule_id=%d\n", list_id, pos);
+    val = isis_acl_rule_add(0, list_id, pos, rule_nr, &acl);
+
+    multi_acl_bind();
+
+    return val;
+}
+
+
+HSL_LOCAL int iterate_multicast_acl_group(a_uint32_t number, fal_igmp_sg_entry_t * entry)
+{
+    int count=0;
+    int i;
+
+    if (number == 0)
+        return 0; //no any ACL rules based the query
+
+    for(i=0; i<number; i++)
+    {
+
+        /*MULTI_DEBUG("2:iterate_multicast_acl_group, index=%d, multi_acl_info[%d].entry=type[%d]-addr[%x], pm=%x, new entry=type[%d]-addr[%x], pm=%x\n",
+            multi_acl_info[i].index,i, multi_acl_info[i].entry.group.type, multi_acl_info[i].entry.group.u.ip6_addr.ul[0], multi_acl_info[i].entry.port_map,
+            entry->group.type, entry->group.u.ip6_addr.ul[0], entry->port_map);*/
+
+        if(0 == memcmp(&(multi_acl_info[i].entry.group), &(entry->group), sizeof(entry->group)))
+        {
+            memcpy(&multi_acl_group[count], &multi_acl_info[i], sizeof(multi_acl_info[i]));
+            count++;//return the real number of multi_acl_group[]
+            MULTI_DEBUG("in iterate_multicast_acl_group, count=%d, i=%d\n", count, i);
+        }
+    }
+
+    return count;
+}
+
+HSL_LOCAL int mult_acl_has_entry(fal_igmp_sg_addr_t * group, fal_igmp_sg_addr_t *source)
+{
+    int rule_id;
+    int ret = 0;
+#if 0
+    if(source != NULL)
+    {
+        MULTI_DEBUG("new group[%d]= %x %x %x %x, new source[%d]=%x %x %x %x\n",
+                    group->type, group->u.ip6_addr.ul[0], group->u.ip6_addr.ul[1], group->u.ip6_addr.ul[2], group->u.ip6_addr.ul[3],
+                    source->type, source->u.ip6_addr.ul[0], source->u.ip6_addr.ul[1], source->u.ip6_addr.ul[2], source->u.ip6_addr.ul[3]);
+
+        MULTI_DEBUG("old group[%d]= %x %x %x %x, old source[%d]=%x %x %x %x\n",
+                    multi_acl_group[0].entry.group.type, multi_acl_group[0].entry.group.u.ip6_addr.ul[0],
+                    multi_acl_group[0].entry.group.u.ip6_addr.ul[1], multi_acl_group[0].entry.group.u.ip6_addr.ul[2], multi_acl_group[0].entry.group.u.ip6_addr.ul[3],
+                    multi_acl_group[0].entry.source.type, multi_acl_group[0].entry.source.u.ip6_addr.ul[0],
+                    multi_acl_group[0].entry.source.u.ip6_addr.ul[1], multi_acl_group[0].entry.source.u.ip6_addr.ul[2], multi_acl_group[0].entry.source.u.ip6_addr.ul[3]);
+    }
+#endif
+    if(source == NULL)
+    {
+        for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+        {
+            if( (0==memcmp(&multi_acl_group[rule_id].entry.group, group, sizeof(fal_igmp_sg_addr_t))) &&
+                    (multi_source_is_null(&multi_acl_group[rule_id].entry.source)))
+            {
+                MULTI_DEBUG("Source=0:Orignal ACL rule have this entry! rule id= %d\n", rule_id);
+                ret = rule_id+1; // ensure the return value is the actually number of entry
+                break;
+            }
+        }
+    }
+    else
+    {
+        for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+        {
+            if( (0==memcmp(&multi_acl_group[rule_id].entry.group, group, sizeof(fal_igmp_sg_addr_t))) &&
+                    (0==memcmp(&multi_acl_group[rule_id].entry.source, source, sizeof(fal_igmp_sg_addr_t))))
+            {
+                MULTI_DEBUG("Orignal ACL rule have this entry! rule id= %d\n", rule_id);
+                ret = rule_id+1; // ensure the return value is the actually number of entry
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+HSL_LOCAL int portmap_null(int index, fal_pbmp_t portmap)
+{
+    int val;
+    if (index<0)
+    {
+        aos_printk("portmap_null, index error\n");
+        return SW_FAIL;
+    }
+    val = multi_acl_group[index].entry.port_map&(~portmap);
+
+    if( 0 == (val&0xff) )
+        return 1;
+    else
+        return 0;
+}
+
+HSL_LOCAL int portmap_valid(fal_igmp_sg_entry_t *g_source, fal_igmp_sg_entry_t *g_star)
+{
+    /* return 0 means the portmap is Not valid
+        return 1 means the protmap is valid
+    */
+    /* MULTI_DEBUG("portmap_valid:g_source portmap=%x,  source=%x,group=%x, g_star portmap=%x, source=%x, group=%x\n",
+          g_source->port_map, g_source->source.u.ip4_addr, g_source->group.u.ip4_addr,
+          g_star->port_map, g_star->source.u.ip4_addr,g_star->group.u.ip4_addr);*/
+
+    if(multi_source_is_null(&(g_star->source)))
+    {
+        if((g_source->port_map|g_star->port_map) == g_star->port_map)
+        {
+            return 0;
+        }
+    }
+
+    return 1;
+}
+
+
+HSL_LOCAL int portmap_clear_type(int count, int index, fal_pbmp_t portmap)
+{
+    if(count>=0 && index<count) //new_index must >0; this means there're (G,*) and (G,S)
+    {
+        //if the new clear portmap will cause (G,S)=(G,*), Delete the (G,S)
+        if((multi_acl_group[index].entry.port_map & (~portmap)) == multi_acl_group[count].entry.port_map)
+            return 1; //delete
+
+
+        //The following means there must be at least one bit clear wrong. Clear the (G,*) portmap.
+        if( ((multi_acl_group[index].entry.port_map & (~portmap)) & (multi_acl_group[count].entry.port_map))
+                != (multi_acl_group[count].entry.port_map))
+            return 0;
+
+        return 2; //Normal update
+    }
+	return 0;
+}
+sw_error_t isis_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+    int number, count;
+    int new_index=0;
+    sw_error_t rv;
+    int action = MULT_ACTION_SET;
+    int i=0;
+
+    HSL_API_LOCK;
+    (void)isis_multicast_init(0);
+    aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    MULTI_DEBUG("Before query: group=%x, source=%x, portmap=%x\n", entry->group.u.ip4_addr, entry->source.u.ip4_addr, entry->port_map);
+    //number is the total multicast ACL rules amount, stores in multi_acl_info[];
+    number = isis_multicast_acl_query();
+    if(number > FAL_IGMP_SG_ENTRY_MAX)
+	return SW_FAIL;
+    //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number
+    count = iterate_multicast_acl_group(number, entry);
+    //new_index-1 is the found entry index in multi_acl_group[], the real index is [new_index-1], 0 means no entry
+    new_index = mult_acl_has_entry(&entry->group, &entry->source);
+
+    MULTI_DEBUG("Start entry set: number=%d, count=%d, new_index=%d, pm=%x\n", number, count, new_index, entry->port_map);
+    if( 0==multi_source_is_null(&entry->source) )  // new entry is (G, S)
+    {
+        MULTI_DEBUG("the new entry is (G,S)\n");
+        if(count>0 && 0 == portmap_valid(entry, &(multi_acl_group[count-1].entry))) //specfic group entry exist,(G,S) or (G,*)
+        {
+            //return SW_NO_CHANGE; // The new portmap is Not valid
+            MULTI_DEBUG("KKK, modified 1 !!!\n");
+        }
+
+        if(0 == new_index) //new entry, need add
+        {
+#if 0
+            /*The method:
+                1. predict if the portmap should be modified.
+                2. add new acl rule with new portmap value.
+            */
+            if((tmp_index = mult_acl_has_entry(&entry->group, NULL))>0) // (G, *) entry exist
+            {
+                /*Here the update should new (G, S) OR orignal (G,*) portmap,
+                be careful, entry's portmap value will be modified, so I use tmp_entry.
+                */
+                memcpy(tmp_entry, entry, sizeof(fal_igmp_sg_entry_t));
+                MULTI_DEBUG("Here, (G,*) exist! tmp_index=%d\n", tmp_index);
+                sw_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, tmp_index-1, tmp_entry, action);
+
+                isis_multicast_acl_add(FAL_ACL_LIST_MULTICAST, tmp_entry);
+                return SW_OK;
+            }
+#endif
+            isis_multicast_acl_add(FAL_ACL_LIST_MULTICAST, entry);
+            MULTI_DEBUG("Here, need add (G, S), portmap=%x\n", entry->port_map);
+            return SW_OK;
+        }
+        else
+        {
+            //Here update Just: the old exist entry portmap OR the new entry portmap
+            isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action);
+            return SW_OK;
+        }
+    } //end of memcmp
+    else  // new entry is (G, *)
+    {
+        if(0 == new_index) //new entry, need add
+        {
+            isis_multicast_acl_add(FAL_ACL_LIST_MULTICAST+1, entry);
+            rv = SW_OK;
+        }
+        else if(new_index > 0) // (G, *) entry exist?
+        {
+            //Update exist (G, *) portmap with new portmap
+            MULTI_DEBUG("(G,*) exist, before update, new_index=%d\n", new_index );
+            isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action);
+            rv = SW_OK;
+        }
+
+        if(new_index>0&&count>1) //(G,S*) and (G,*) exist, new entry is (G,*)
+        {
+            for(i=count-2; i>=0&&i<FAL_IGMP_SG_ENTRY_MAX; i--)
+            {
+                if(multi_acl_group[i].entry.port_map==0) //This ACL rule should be done nothing, DENY rule
+                    continue;
+
+                if(0 == portmap_valid(&(multi_acl_group[i].entry), &(multi_acl_group[count-1].entry)))
+                {
+                    MULTI_DEBUG("1:portmap is not valid, should delete, i=%d, source portmap=%x, gstar pm=%x\n",
+                                i, multi_acl_group[i].entry.port_map, multi_acl_group[count-1].entry.port_map);
+                    isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+                    rv = SW_NO_MORE;
+                }
+                else
+                {
+                    MULTI_DEBUG("1:Start update all (G,S),i=%d, gstar portmap=%x\n", i, multi_acl_group[count-1].entry.port_map);
+                    //Update all (G,S) entry portmap with new(G, *) portmap
+                    isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+                    rv = SW_OK;
+                }
+            }
+        }
+        else if(new_index==0&&count>0) //only exist (G,S*) orignally
+        {
+            for(i=count-1; i>=0&&i<FAL_IGMP_SG_ENTRY_MAX; i--)
+            {
+                if(multi_acl_group[i].entry.port_map==0) //This ACL rule should be done nothing, DENY rule
+                    continue;
+
+                if(0 == portmap_valid(&(multi_acl_group[i].entry), entry))
+                {
+                    MULTI_DEBUG("2:portmap is not valid, should delete, i=%d, source portmap=%x, gstar pm=%x\n",
+                                i, multi_acl_group[i].entry.port_map, entry->port_map);
+                    isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+                    rv = SW_NO_MORE;
+                }
+                else
+                {
+                    MULTI_DEBUG("2:Start update all (G,S),i=%d, portmap=%x\n", i, entry->port_map);
+                    //Update all (G,S) entry portmap with new(G, *) portmap
+                    isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+                    rv = SW_OK;
+                }
+            }
+        }
+    }
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t isis_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+    a_uint32_t number, count;
+    int new_index=0;
+    sw_error_t rv = SW_OK;
+    int action= MULT_ACTION_CLEAR;
+    int i=0;
+    int pm_type;
+
+    HSL_API_LOCK;
+    (void)isis_multicast_init(0);
+    aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    //number is the total multicast ACL rules amount, stores in multi_acl_info[];
+    number = isis_multicast_acl_query();
+    if(number > FAL_IGMP_SG_ENTRY_MAX)
+	return SW_FAIL;
+
+    //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number
+    count = iterate_multicast_acl_group(number, entry);
+    if(count == 0)
+        return SW_OK;
+
+    //new_index-1 is the found entry index in multi_acl_group[]
+    new_index = mult_acl_has_entry(&entry->group, &entry->source);
+
+    MULTI_DEBUG("Start entry clear: number=%d, count=%d, new_index=%d\n", number, count, new_index);
+    if(0 == new_index || new_index > FAL_IGMP_SG_ENTRY_MAX ||count > FAL_IGMP_SG_ENTRY_MAX) //new entry, the user command is wrong
+    {
+        return SW_NO_SUCH;
+    }
+
+    if( 0==multi_source_is_null(&entry->source) )  // new entry is (G, S)
+    {
+        if (portmap_null(new_index-1, entry->port_map))
+        {
+            MULTI_DEBUG("KKK entry clear, new(G,S), with null portmap. \n");
+            isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, new_index-1);
+            return SW_OK;
+        }
+        else
+        {
+            MULTI_DEBUG("KKK entry clear, new(G,S), with NOT null portmap. \n");
+            /* If (G,*) doesn't exist, [count-1] is the last specfic group, maybe(G,*) */
+            if(0 == multi_source_is_null(&(multi_acl_group[count-1].entry.source)))
+            {
+                isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action);
+            }
+            else //(G,*) exist
+            {
+                pm_type = portmap_clear_type(count-1, new_index-1, entry->port_map);
+                if(pm_type == 0)
+                    return SW_NO_CHANGE;
+                else if(pm_type == 1)
+                {
+                    isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, new_index-1);
+                    return SW_OK;
+                }
+                else
+                {
+                    //normal update; consider here...wangson
+                    isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action);
+                }
+            }
+        }
+        return SW_OK;
+    }
+    else  //clear entry is (G,*)
+    {
+        MULTI_DEBUG("Here, new_index[%d]>=0, new portmap to clear is %x\n", new_index, entry->port_map);
+        if (portmap_null(new_index-1, entry->port_map))
+        {
+            isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST+1, new_index-1);
+            rv = SW_OK;
+        }
+        else
+        {
+            MULTI_DEBUG("Update (G,*)!, new_index=%d, pm=%x\n", new_index, entry->port_map);
+            isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action);
+        }
+        MULTI_DEBUG("KKK, ready clear (G, S*), count=%d\n", count);
+#if 0
+        if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry
+        {
+            //count must >=2
+            for(i=count-2; i>=0; i--)
+            {
+                if(portmap_null(i, entry->port_map))
+                {
+                    MULTI_DEBUG("portmap_null, i=%d\n", i);
+                    isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+                    rv = SW_NO_MORE;
+                }
+                else
+                {
+                    //Update all (G,S) entry portmap with new(G, *) portmap
+                    isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+                    rv = SW_OK;
+                }
+            }
+        }
+#else
+        if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry
+        {
+            //count must >=2
+            for(i=count-2; i>=0&&i<FAL_IGMP_SG_ENTRY_MAX; i--)
+            {
+                //PortMap of entry (S,G) == (*,G) portmap after clear?
+                if((multi_acl_group[new_index-1].entry.port_map&(~(entry->port_map))) ==
+                        multi_acl_group[i].entry.port_map)
+                    isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+                else
+                    //Update all (G,S) entry portmap with new(G, *) portmap
+                    isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+                rv = SW_OK;
+            }
+        }
+#endif
+    }
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+static void
+print_ip4addr(char * param_name, a_uint32_t * buf,
+              a_uint32_t size)
+{
+    a_uint32_t i;
+    fal_ip4_addr_t ip4;
+
+    ip4 = *((fal_ip4_addr_t *) buf);
+    aos_printk("%s", param_name);
+    for (i = 0; i < 3; i++)
+    {
+        aos_printk("%d.", (ip4 >> (24 - i * 8)) & 0xff);
+    }
+    aos_printk("%d", (ip4 & 0xff));
+}
+static void
+print_ip6addr(char * param_name, a_uint32_t * buf,
+              a_uint32_t size)
+{
+    a_uint32_t i;
+    fal_ip6_addr_t ip6;
+
+    ip6 = *(fal_ip6_addr_t *) buf;
+    aos_printk("%s", param_name);
+    for (i = 0; i < 3; i++)
+    {
+        aos_printk("%x:%x:", (ip6.ul[i] >> 16) & 0xffff, ip6.ul[i] & 0xffff);
+    }
+    aos_printk("%x:%x", (ip6.ul[3] >> 16) & 0xffff, ip6.ul[3] & 0xffff);
+}
+sw_error_t isis_igmp_sg_entry_show(a_uint32_t dev_id)
+{
+    a_uint32_t number;
+    int i;
+
+    HSL_API_LOCK;
+    (void)isis_multicast_init(0);
+    aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    //number is the total multicast ACL rules amount, stores in multi_acl_info[];
+    number = isis_multicast_acl_query();
+
+    for(i=0; i<number; i++)
+    {
+        if(0 == multi_acl_info[i].entry.group.type)  //ipv4
+        {
+            aos_printk("\n[%d]:", i);
+            print_ip4addr(" [Group IPv4 addr]:", (a_uint32_t *)&(multi_acl_info[i].entry.group.u.ip4_addr), sizeof (fal_ip4_addr_t));
+            print_ip4addr(" [Source IPv4 addr]:", (a_uint32_t *)&(multi_acl_info[i].entry.source.u.ip4_addr), sizeof (fal_ip4_addr_t));
+            aos_printk(" [Portmap]: 0x%x ", multi_acl_info[i].entry.port_map);
+        }
+        else if(1 == multi_acl_info[i].entry.group.type)  //ipv6
+        {
+            aos_printk("\n[%d]:", i);
+            print_ip6addr(" [Group IPv6 addr]: ", (a_uint32_t *)&(multi_acl_info[i].entry.group.u.ip6_addr), sizeof (fal_ip6_addr_t));
+            print_ip6addr(" [Source IPv6 addr]: ", (a_uint32_t *)&(multi_acl_info[i].entry.source.u.ip6_addr), sizeof (fal_ip6_addr_t));
+            aos_printk(" [Portmap]: 0x%x ", multi_acl_info[i].entry.port_map);
+        }
+
+    }
+    aos_printk("\n\nTotal %d multicast ACL rules.\n", number);
+    HSL_API_UNLOCK;
+
+    return SW_OK;
+}
+
+void
+isis_multicast_init(a_uint32_t dev_id)
+{
+    sw_error_t val;
+
+    isis_acl_status_set(0, 1);
+
+    val = isis_acl_list_creat(0, FAL_ACL_LIST_MULTICAST, FAL_MULTICAST_PRI);
+    if(val !=SW_OK && val != SW_ALREADY_EXIST)
+        aos_printk("Multicast 1 acl list create error, val=%d\n", val);
+
+    val = isis_acl_list_creat(0, FAL_ACL_LIST_MULTICAST+1, FAL_MULTICAST_PRI+1);
+    if(val !=SW_OK && val != SW_ALREADY_EXIST)
+        aos_printk("Multicast 2 acl list create error, val=%d\n", val);
+
+}
+
diff --git a/qca-ssdk/src/hsl/isis/isis_nat.c b/qca-ssdk/src/hsl/isis/isis_nat.c
new file mode 100755
index 0000000..4795f6d
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_nat.c
@@ -0,0 +1,2457 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_ip ISIS_NAT
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_nat.h"
+#include "isis_reg.h"
+#if defined(IN_NAT_HELPER)
+#include "isis_nat_helper.h"
+#endif
+
+
+#define ISIS_HOST_ENTRY_DATA0_ADDR              0x0e48
+#define ISIS_HOST_ENTRY_DATA1_ADDR              0x0e4c
+#define ISIS_HOST_ENTRY_DATA2_ADDR              0x0e50
+#define ISIS_HOST_ENTRY_DATA3_ADDR              0x0e54
+#define ISIS_HOST_ENTRY_DATA4_ADDR              0x0e58
+
+#define ISIS_NAT_ENTRY_FLUSH                    1
+#define ISIS_NAT_ENTRY_ADD                      2
+#define ISIS_NAT_ENTRY_DEL                      3
+#define ISIS_NAT_ENTRY_NEXT                     4
+#define ISIS_NAT_ENTRY_SEARCH                   5
+
+#define ISIS_ENTRY_NAPT                         0
+#define ISIS_ENTRY_NAT                          2
+#define ISIS_ENTRY_ARP                          3
+
+#define ISIS_PUB_ADDR_NUM                       16
+#define ISIS_PUB_ADDR_TBL0_ADDR                 0x5aa00
+#define ISIS_PUB_ADDR_TBL1_ADDR                 0x5aa04
+#define ISIS_PUB_ADDR_EDIT0_ADDR                0x02100
+#define ISIS_PUB_ADDR_EDIT1_ADDR                0x02104
+#define ISIS_PUB_ADDR_OFFLOAD_ADDR              0x2a000
+#define ISIS_PUB_ADDR_VALID_ADDR                0x2a040
+
+#define ISIS_NAT_ENTRY_NUM                      32
+#define ISIS_NAPT_ENTRY_NUM                     1024
+
+#define ISIS_NAT_COUTER_ADDR                    0x2b000
+
+#define ISIS_NAT_PORT_NUM                       255
+
+static a_uint32_t isis_nat_snap[SW_MAX_NR_DEV] = { 0 };
+extern a_uint32_t isis_nat_global_status;
+
+static sw_error_t
+_isis_nat_feature_check(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (S17_DEVICE_ID == entry)
+    {
+        return SW_OK;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+}
+
+static sw_error_t
+_isis_ip_prvaddr_sw_to_hw(a_uint32_t dev_id, fal_ip4_addr_t sw_addr,
+                          a_uint32_t * hw_addr)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *hw_addr = (sw_addr & 0xff) | (((sw_addr >> 16) & 0xf) << 8);
+    }
+    else
+    {
+        *hw_addr = sw_addr & 0xfff;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_prvaddr_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_addr,
+                          fal_ip4_addr_t * sw_addr)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, addr = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+                      (a_uint8_t *) (&addr), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *sw_addr = ((addr & 0xff) << 8) | (((addr >> 8) & 0xfff) << 8)
+                   | (hw_addr & 0xff) | (((hw_addr >> 8) & 0xf) << 16);
+    }
+    else
+    {
+        *sw_addr = (addr << 12) | (hw_addr & 0xfff);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id,
+                      a_uint32_t counter[4])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    addr = ISIS_NAT_COUTER_ADDR + (cnt_id << 4);
+    for (i = 0; i < 4; i++)
+    {
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(counter[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        addr += 4;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op)
+{
+    a_uint32_t busy = 1, i = 0x100, entry = 0;
+    sw_error_t rv;
+
+    while (busy && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+                          sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_BUSY, busy, entry);
+        aos_udelay(500);
+    }
+
+    if (i == 0)
+    {
+        printk("%s BUSY\n", __FUNCTION__);
+        return SW_BUSY;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_BUSY, 1, entry);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_SEL, entry_type, entry);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, ENTRY_FUNC, op, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    busy = 1;
+    i = 0x100;
+    while (busy && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+                          sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_BUSY, busy, entry);
+        aos_udelay(500);
+#if 1
+        if(ISIS_NAT_ENTRY_SEARCH == op &&  busy) break;
+#endif
+    }
+
+    if (i == 0)
+    {
+        printk("%s BUSY\n", __FUNCTION__);
+        return SW_BUSY;
+    }
+
+    /* hardware requirement, we should delay... */
+    if ((ISIS_NAT_ENTRY_FLUSH == op) && (ISIS_ENTRY_NAPT == entry_type))
+    {
+        aos_mdelay(10);
+    }
+
+    /* hardware requirement, we should read again... */
+    HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_STAUS, busy, entry);
+    if (!busy)
+    {
+        if (ISIS_NAT_ENTRY_NEXT == op)
+        {
+            return SW_NO_MORE;
+        }
+        else if (ISIS_NAT_ENTRY_SEARCH == op)
+        {
+            return SW_NOT_FOUND;
+        }
+        else
+        {
+            return SW_FAIL;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_sw_to_hw(a_uint32_t dev_id, fal_nat_entry_t * entry, a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    if (FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & entry->flags)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    reg[0] = entry->trans_addr;
+
+    if (FAL_NAT_ENTRY_PORT_CHECK & entry->flags)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, PORT_EN, 1, reg[2]);
+        SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_RANGE, entry->port_range, reg[1]);
+        if (ISIS_NAT_PORT_NUM < entry->port_range)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_NUM, entry->port_num, reg[1]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, PORT_EN, 0, reg[2]);
+    }
+
+    rv = _isis_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]);
+    SW_SET_REG_BY_FIELD(NAT_ENTRY2, PRV_IPADDR1, (data >> 8), reg[2]);
+
+    if (FAL_MAC_FRWRD == entry->action)
+    {
+        if (A_TRUE == entry->mirror_en)
+        {
+            SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 0, reg[2]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 3, reg[2]);
+        }
+    }
+    else if (FAL_MAC_CPY_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 2, reg[2]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 1, reg[2]);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->counter_en)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]);
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]);
+    }
+
+    if (FAL_NAT_ENTRY_PROTOCOL_ANY & entry->flags)
+    {
+        data = 3;
+    }
+    else if ((FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags)
+             && (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags))
+    {
+        data = 2;
+    }
+    else if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags)
+    {
+        data = 0;
+    }
+    else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(NAT_ENTRY2, PRO_TYP, data, reg[2]);
+
+    SW_SET_REG_BY_FIELD(NAT_ENTRY2, HASH_KEY, entry->slct_idx, reg[2]);
+
+    SW_SET_REG_BY_FIELD(NAT_ENTRY2, ENTRY_VALID, 1, reg[2]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[], fal_nat_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, cnt[4] = {0};
+
+    entry->trans_addr = reg[0];
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY2, PORT_EN, data, reg[2]);
+    if (data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PORT_CHECK;
+        SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_RANGE, data, reg[1]);
+        entry->port_range = data;
+        SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_NUM, data, reg[1]);
+        entry->port_num = data;
+    }
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]);
+    entry->src_addr = data;
+    SW_GET_FIELD_BY_REG(NAT_ENTRY2, PRV_IPADDR1, data, reg[2]);
+    data = (entry->src_addr & 0xff) | (data << 8);
+
+    rv = _isis_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY2, ACTION, data, reg[2]);
+    entry->action = FAL_MAC_FRWRD;
+    if (0 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+    else if (2 == data)
+    {
+        entry->action = FAL_MAC_CPY_TO_CPU;
+    }
+    else if (1 == data)
+    {
+        entry->action = FAL_MAC_RDT_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_EN, data, reg[2]);
+    if (data)
+    {
+        entry->counter_en = A_TRUE;
+        SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]);
+
+        rv = _isis_nat_counter_get(dev_id, entry->counter_id, cnt);
+        SW_RTN_ON_ERROR(rv);
+
+        entry->ingress_packet = cnt[0];
+        entry->ingress_byte = cnt[1];
+        entry->egress_packet = cnt[2];
+        entry->egress_byte = cnt[3];
+    }
+    else
+    {
+        entry->counter_en = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY2, PRO_TYP, data, reg[2]);
+    if (3 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_ANY;
+    }
+    else if (2 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP;
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP;
+    }
+    else if (1 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP;
+    }
+    else if (0 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP;
+    }
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY2, HASH_KEY, data, reg[2]);
+    entry->slct_idx = data;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_napt_sw_to_hw(a_uint32_t dev_id, fal_napt_entry_t * entry,
+                    a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    reg[0] = entry->dst_addr;
+
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]);
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]);
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]);
+
+    rv = _isis_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+    SW_RTN_ON_ERROR(rv);
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR, data, reg[2]);
+
+    if (!(FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & entry->flags))
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+
+    if (FAL_MAC_FRWRD == entry->action)
+    {
+        if (A_TRUE == entry->mirror_en)
+        {
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 0, reg[3]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 3, reg[3]);
+        }
+    }
+    else if (FAL_MAC_CPY_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 2, reg[3]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 1, reg[3]);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->counter_en)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]);
+    }
+
+    data = 2;
+    if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags)
+    {
+        data = 0;
+    }
+    else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags)
+    {
+        data = 1;
+    }
+    else if (FAL_NAT_ENTRY_PROTOCOL_PPTP & entry->flags)
+    {
+        data = 3;
+    }
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY3, PROT_TYP, data, reg[3]);
+
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY3, AGE_FLAG, entry->status, reg[3]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_napt_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[],
+                    fal_napt_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, cnt[4] = {0};
+
+    entry->dst_addr = reg[0];
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]);
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]);
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]);
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY2, SRC_IPADDR, data, reg[2]);
+    rv = _isis_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr));
+    SW_RTN_ON_ERROR(rv);
+
+    entry->flags |= FAL_NAT_ENTRY_TRANS_IPADDR_INDEX;
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY3, ACTION, data, reg[3]);
+    entry->action = FAL_MAC_FRWRD;
+    if (0 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+    else if (2 == data)
+    {
+        entry->action = FAL_MAC_CPY_TO_CPU;
+    }
+    else if (1 == data)
+    {
+        entry->action = FAL_MAC_RDT_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_EN, data, reg[3]);
+    if (data)
+    {
+        entry->counter_en = A_TRUE;
+        SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]);
+
+        rv = _isis_nat_counter_get(dev_id, entry->counter_id, cnt);
+        SW_RTN_ON_ERROR(rv);
+
+        entry->ingress_packet = cnt[0];
+        entry->ingress_byte = cnt[1];
+        entry->egress_packet = cnt[2];
+        entry->egress_byte = cnt[3];
+    }
+    else
+    {
+        entry->counter_en = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY3, PROT_TYP, data, reg[3]);
+    if (0 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP;
+    }
+    else if (1 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP;
+    }
+    else if (3 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_PPTP;
+    }
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY3, AGE_FLAG, entry->status, reg[3]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    for (i = 0; i < 5; i++)
+    {
+        addr = ISIS_HOST_ENTRY_DATA0_ADDR + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&reg[i]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    for (i = 0; i < 5; i++)
+    {
+        addr = ISIS_HOST_ENTRY_DATA0_ADDR + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&reg[i]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_add(a_uint32_t dev_id, fal_nat_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, reg[5] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < ISIS_NAT_ENTRY_NUM; i++)
+    {
+        if (!(isis_nat_snap[dev_id] & (0x1 << i)))
+        {
+            break;
+        }
+    }
+
+    if (ISIS_NAT_ENTRY_NUM == i)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    entry->entry_id = i;
+
+    rv = _isis_nat_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_ADD);
+    SW_RTN_ON_ERROR(rv);
+
+    isis_nat_snap[dev_id] |= (0x1 << i);
+    entry->entry_id = i;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[5] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NAT_ENTRY_ID_EN & del_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY4, ENTRY_FUNC, ISIS_NAT_ENTRY_DEL, reg[4]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+
+        rv = _isis_nat_down_to_hw(dev_id, reg);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_DEL);
+        SW_RTN_ON_ERROR(rv);
+
+        isis_nat_snap[dev_id] &= (~(0x1 << entry->entry_id));
+    }
+    else
+    {
+        rv = _isis_nat_down_to_hw(dev_id, reg);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_FLUSH);
+        SW_RTN_ON_ERROR(rv);
+
+        isis_nat_snap[dev_id] = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[5] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NAT_ENTRY_ID_EN != get_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (!(isis_nat_snap[dev_id] & (0x1 << entry->entry_id)))
+    {
+        return SW_NOT_FOUND;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+
+    rv = _isis_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_SEARCH);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_hw_to_sw(dev_id, reg, entry);
+    return rv;
+}
+
+static sw_error_t
+_isis_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+               fal_nat_entry_t * nat_entry)
+{
+    a_uint32_t i, idx, reg[5] = { 0 };
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == nat_entry->entry_id)
+    {
+        idx = 0;
+    }
+    else
+    {
+        if ((ISIS_NAT_ENTRY_NUM - 1) == nat_entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = nat_entry->entry_id + 1;
+        }
+    }
+
+    for (i = idx; i < ISIS_NAT_ENTRY_NUM; i++)
+    {
+        if (isis_nat_snap[dev_id] & (0x1 << i))
+        {
+            break;
+        }
+    }
+
+    if (ISIS_NAT_ENTRY_NUM == i)
+    {
+        return SW_NO_MORE;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, i, reg[4]);
+
+    rv = _isis_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_SEARCH);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    aos_mem_zero(nat_entry, sizeof (fal_nat_entry_t));
+
+    rv = _isis_nat_hw_to_sw(dev_id, reg, nat_entry);
+    SW_RTN_ON_ERROR(rv);
+
+    nat_entry->entry_id = i;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                       a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[5] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!(isis_nat_snap[dev_id] & (0x1 << entry_id)))
+    {
+        return SW_NOT_FOUND;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, entry_id, reg[4]);
+
+    rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_SEARCH);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 0, reg[2]);
+    }
+    else if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]);
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, cnt_id, reg[2]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    /* needn't set TBL_IDX, keep hardware register value */
+
+    rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_DEL);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    /* needn't set TBL_IDX, keep hardware register value */
+
+    rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_ADD);
+    return rv;
+}
+
+static sw_error_t
+_isis_napt_add(a_uint32_t dev_id, fal_napt_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[5] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_napt_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_ADD);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[5] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NAT_ENTRY_ID_EN & del_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_NAT_ENTRY_KEY_EN & del_mode)
+    {
+        rv = _isis_napt_sw_to_hw(dev_id, entry, reg);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _isis_nat_down_to_hw(dev_id, reg);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_DEL);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _isis_nat_up_to_sw(dev_id, reg);
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+        return SW_OK;
+    }
+    else
+    {
+        if (FAL_NAT_ENTRY_PUBLIC_IP_EN & del_mode)
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_PIP, 1, reg[4]);
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+        }
+
+        if (FAL_NAT_ENTRY_SOURCE_IP_EN & del_mode)
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_SIP, 1, reg[4]);
+            rv = _isis_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+            SW_RTN_ON_ERROR(rv);
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR, data, reg[2]);
+        }
+
+        if (FAL_NAT_ENTRY_AGE_EN & del_mode)
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_STATUS, 1, reg[4]);
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY3, AGE_FLAG, entry->status, reg[3]);
+        }
+
+        rv = _isis_nat_down_to_hw(dev_id, reg);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_FLUSH);
+        return rv;
+    }
+}
+
+static sw_error_t
+_isis_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t found, age, reg[5] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+#if 0
+    if (FAL_NAT_ENTRY_ID_EN != get_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+#else
+    rv = _isis_napt_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+    rv = _isis_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_SEARCH);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_STAUS, found, reg[4]);
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY3, AGE_FLAG,  age, reg[3]);
+    if (found && age)
+    {
+        found = 1;
+    }
+    else
+    {
+        found = 0;
+    }
+
+    rv = _isis_napt_hw_to_sw(dev_id, reg, entry);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!found)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX,   entry->entry_id, reg[4]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                fal_napt_entry_t * napt_entry)
+{
+    a_uint32_t data, idx, reg[5] = { 0 };
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == napt_entry->entry_id)
+    {
+        idx = ISIS_NAPT_ENTRY_NUM - 1;
+    }
+    else
+    {
+        if ((ISIS_NAPT_ENTRY_NUM - 1) == napt_entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = napt_entry->entry_id;
+        }
+    }
+
+    if (FAL_NAT_ENTRY_PUBLIC_IP_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_PIP, 1, reg[4]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, napt_entry->trans_addr, reg[2]);
+    }
+
+    if (FAL_NAT_ENTRY_SOURCE_IP_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_SIP, 1, reg[4]);
+        rv = _isis_ip_prvaddr_sw_to_hw(dev_id, napt_entry->src_addr, &data);
+        SW_RTN_ON_ERROR(rv);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR, data, reg[2]);
+    }
+
+    if (FAL_NAT_ENTRY_AGE_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_STATUS, 1, reg[4]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, AGE_FLAG, napt_entry->status, reg[3]);
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, idx, reg[4]);
+
+    rv = _isis_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_NEXT);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    aos_mem_zero(napt_entry, sizeof (fal_nat_entry_t));
+
+    rv = _isis_napt_hw_to_sw(dev_id, reg, napt_entry);
+    SW_RTN_ON_ERROR(rv);
+
+#if 0
+    a_uint32_t temp=0, complete=0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&temp),
+                      sizeof (a_uint32_t));
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_STAUS, complete, temp);
+
+    if (!complete)
+    {
+        return SW_NO_MORE;
+    }
+#endif
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, napt_entry->entry_id, reg[4]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                        a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[5] = { 0 }, tbl_idx;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    tbl_idx = (entry_id - 1) & 0x3ff;
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]);
+
+    rv = _isis_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_NEXT);
+    if (SW_OK != rv)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    rv = _isis_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]);
+    if (entry_id != tbl_idx)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 0, reg[3]);
+    }
+    else if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, cnt_id, reg[3]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_DEL);
+    SW_RTN_ON_ERROR(rv);
+
+    reg[4] = 0x0;
+    rv = _isis_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_ADD);
+    return rv;
+}
+
+static sw_error_t
+_isis_nat_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_nat_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isis_napt_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_napt_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isis_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NAPT_FULL_CONE == mode)
+    {
+        data = 0;
+    }
+    else if (FAL_NAPT_STRICT_CONE == mode)
+    {
+        data = 1;
+    }
+    else if ((FAL_NAPT_PORT_STRICT == mode)
+             || (FAL_NAPT_SYNMETRIC == mode))
+    {
+        data = 2;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        *mode = FAL_NAPT_FULL_CONE;
+    }
+    else if (1 == data)
+    {
+        *mode = FAL_NAPT_STRICT_CONE;
+    }
+    else
+    {
+        *mode = FAL_NAPT_PORT_STRICT;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if ((FAL_NAT_HASH_KEY_PORT & mode)
+            && (FAL_NAT_HASH_KEY_IPADDR & mode))
+    {
+        data = 2;
+    }
+    else if (FAL_NAT_HASH_KEY_PORT & mode)
+    {
+        data = 0;
+    }
+    else if (FAL_NAT_HASH_KEY_IPADDR & mode)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *mode = 0;
+    if (0 == data)
+    {
+        *mode = FAL_NAT_HASH_KEY_PORT;
+    }
+    else if (1 == data)
+    {
+        *mode = FAL_NAT_HASH_KEY_IPADDR;
+    }
+    else if (2 == data)
+    {
+        *mode = FAL_NAT_HASH_KEY_PORT;
+        *mode |= FAL_NAT_HASH_KEY_IPADDR;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        data = (((addr >> 20) & 0xfff) << 8) | ((addr >> 8) & 0xff);
+    }
+    else
+    {
+        data = (addr >> 12) & 0xfffff;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, OFFLOAD_PRVIP_CTL, 0, IP4_BASEADDR,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, tmp = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+                      (a_uint8_t *) (&tmp), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (tmp)
+    {
+        *addr = ((data & 0xff) << 8) | (((data >> 8) & 0xfff) << 20);
+    }
+    else
+    {
+        *addr = (data & 0xfffff) << 12;
+    }
+
+    return SW_OK;
+}
+
+#if 0
+static sw_error_t
+_isis_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        data = (((addr >> 20) & 0xfff) << 8) | ((addr >> 8) & 0xff);
+    }
+    else
+    {
+        data = (addr >> 12) & 0xfffff;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+    a_uint32_t data, tmp = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+                      (a_uint8_t *) (&tmp), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (tmp)
+    {
+        *addr = ((data & 0xff) << 8) | (((data >> 8) & 0xfff) << 20);
+    }
+    else
+    {
+        *addr = (data & 0xfffff) << 12;
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isis_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == map_en)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == map_en)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *map_en = A_TRUE;
+    }
+    else
+    {
+        *map_en = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_pub_addr_commit(a_uint32_t dev_id, fal_nat_pub_addr_t * entry,
+                          a_uint32_t op, a_uint32_t * empty)
+{
+    a_uint32_t index, addr, data, tbl[2] = { 0 };
+    sw_error_t rv;
+
+    *empty = ISIS_PUB_ADDR_NUM;
+    for (index = 0; index < ISIS_PUB_ADDR_NUM; index++)
+    {
+        addr = ISIS_PUB_ADDR_TBL1_ADDR + (index << 4);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]);
+        if (data)
+        {
+            addr = ISIS_PUB_ADDR_TBL0_ADDR + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[0])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            if (!aos_mem_cmp
+                    ((void *) &(entry->pub_addr), (void *) &(tbl[0]),
+                     sizeof (fal_ip4_addr_t)))
+            {
+                if (ISIS_NAT_ENTRY_DEL == op)
+                {
+                    addr = ISIS_PUB_ADDR_TBL1_ADDR + (index << 4);
+                    tbl[1] = 0;
+                    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                          (a_uint8_t *) (&(tbl[1])),
+                                          sizeof (a_uint32_t));
+                    *empty = index;
+                    return rv;
+                }
+                else if (ISIS_NAT_ENTRY_ADD == op)
+                {
+                    entry->entry_id = index;
+                    return SW_ALREADY_EXIST;
+                }
+            }
+        }
+        else
+        {
+            *empty = index;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isis_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, empty, addr, data = 0, tbl[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    tbl[0] = entry->pub_addr;
+    tbl[1] = 1;
+
+    rv = _isis_nat_pub_addr_commit(dev_id, entry, ISIS_NAT_ENTRY_ADD, &empty);
+    if (SW_ALREADY_EXIST == rv)
+    {
+        return rv;
+    }
+
+    if (ISIS_PUB_ADDR_NUM == empty)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    for (i = 0; i < 1; i++)
+    {
+        addr = ISIS_PUB_ADDR_EDIT0_ADDR + (empty << 4) + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    addr = ISIS_PUB_ADDR_OFFLOAD_ADDR + (empty << 2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    addr = ISIS_PUB_ADDR_VALID_ADDR;
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data |= (0x1 << empty);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < 2; i++)
+    {
+        addr = ISIS_PUB_ADDR_TBL0_ADDR + (empty << 4) + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    entry->entry_id = empty;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                       fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t empty, addr, data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_pub_addr_commit(dev_id, entry, ISIS_NAT_ENTRY_DEL, &empty);
+    SW_RTN_ON_ERROR(rv);
+
+    addr = ISIS_PUB_ADDR_VALID_ADDR;
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0x1 << empty));
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isis_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                        fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, addr, idx, index, tbl[2] = {0};
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id)
+    {
+        idx = 0;
+    }
+    else
+    {
+        if ((ISIS_PUB_ADDR_NUM - 1) == entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = entry->entry_id + 1;
+        }
+    }
+
+    for (index = idx; index < ISIS_PUB_ADDR_NUM; index++)
+    {
+        addr = ISIS_PUB_ADDR_TBL1_ADDR + (index << 4);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]);
+        if (data)
+        {
+            break;
+        }
+    }
+
+    if (ISIS_PUB_ADDR_NUM == index)
+    {
+        return SW_NO_MORE;
+    }
+
+    addr = ISIS_PUB_ADDR_TBL0_ADDR + (index << 4);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    entry->entry_id = index;
+    entry->pub_addr = tbl[0];
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+isis_nat_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t index, addr, data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    isis_nat_snap[dev_id] = 0;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_FLUSH);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_FLUSH);
+    SW_RTN_ON_ERROR(rv);
+
+    for (index = 0; index < ISIS_PUB_ADDR_NUM; index++)
+    {
+        addr = ISIS_PUB_ADDR_TBL1_ADDR + (index << 4);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Add one NAT entry to one particular device.
+ *   @details Comments:
+       Before NAT entry added ip4 private base address must be set
+       at first.
+       In parameter nat_entry entry flags must be set
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_add(dev_id, nat_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Del NAT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode NAT entry delete operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_del(a_uint32_t dev_id, a_uint32_t del_mode,
+             fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_del(dev_id, del_mode, nat_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get one NAT entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode NAT entry get operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @param[out] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_get(a_uint32_t dev_id, a_uint32_t get_mode,
+             fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_get(dev_id, get_mode, nat_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next NAT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode NAT entry next operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @param[out] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+              fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_next(dev_id, next_mode, nat_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one NAT entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id NAT entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id,
+                      a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_counter_bind(dev_id, entry_id, cnt_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one NAPT entry to one particular device.
+ *   @details Comments:
+       Before NAPT entry added related ip4 private base address must be set
+       at first.
+       In parameter napt_entry related entry flags must be set
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+
+HSL_LOCAL sw_error_t
+isis_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_napt_add(dev_id, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Del NAPT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode NAPT entry delete operation mode
+ * @param[in] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_del(a_uint32_t dev_id, a_uint32_t del_mode,
+              fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_napt_del(dev_id, del_mode, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get one NAPT entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode NAPT entry get operation mode
+ * @param[in] nat_entry NAPT entry parameter
+ * @param[out] nat_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_get(a_uint32_t dev_id, a_uint32_t get_mode,
+              fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_napt_get(dev_id, get_mode, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next NAPT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode NAPT entry next operation mode
+ * @param[in] napt_entry NAPT entry parameter
+ * @param[out] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+               fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_napt_next(dev_id, next_mode, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one NAPT entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id NAPT entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                       a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_napt_counter_bind(dev_id, entry_id, cnt_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set NAT hash mode on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mode NAT hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_hash_mode_set(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get NAT hash mode on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mode NAT hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_hash_mode_get(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_napt_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working status of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_napt_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working mode of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mode NAPT mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_napt_mode_set(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working mode of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mode NAPT mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_napt_mode_get(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP4 private base address on a particular device
+ *   @details Comments:
+        Only 20bits is meaning which 20bits is determined by private address mode.
+ * @param[in] dev_id device id
+ * @param[in] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_prv_base_addr_set(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[out] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_prv_base_addr_get(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#if 0
+/**
+ * @brief Set IP4 private base address on a particular device
+ *   @details Comments:
+        Only 20bits is meaning which 20bits is determined by private address mode.
+ * @param[in] dev_id device id
+ * @param[in] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_psr_prv_base_addr_set(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[out] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_psr_prv_base_addr_get(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set IP4 private base address mode on a particular device
+ *   @details Comments:
+        If map_en equal true means bits31-20 bits15-8 are base address
+        else bits31-12 are base address.
+ * @param[in] dev_id device id
+ * @param[in] map_en private base mapping mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_prv_addr_mode_set(dev_id, map_en);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP4 private base address mode on a particular device
+ * @param[in] dev_id device id
+ * @param[out] map_en private base mapping mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_prv_addr_mode_get(dev_id, map_en);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one public address entry to one particular device.
+ *   @details Comments:
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_pub_addr_add(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one public address entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operaton mode
+ * @param[in] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                      fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_pub_addr_del(dev_id, del_mode, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next public address entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operaton mode
+ * @param[out] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                       fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_pub_addr_next(dev_id, next_mode, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set forwarding command for those packets miss NAT entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_unk_session_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get forwarding command for those packets miss NAT entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nat_unk_session_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_global_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t portbmp)
+{
+    sw_error_t rv = SW_OK;
+
+    HSL_API_LOCK;
+    printk("enable:%d\n", enable);
+    if(enable) {
+        if(isis_nat_global_status == 0) {
+            isis_nat_global_status = 1;
+#if defined(IN_NAT_HELPER)
+            ISIS_NAT_HELPER_INIT(rv, dev_id, portbmp);
+#endif
+        }
+    } else {
+        if(isis_nat_global_status == 1) {
+            isis_nat_global_status = 0;
+#if defined(IN_NAT_HELPER)
+            ISIS_NAT_HELPER_CLEANUP(rv, dev_id);
+#endif
+        }
+    }
+    //rv = SW_OK;
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+sw_error_t
+isis_nat_init(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = isis_nat_reset(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->nat_add = isis_nat_add;
+        p_api->nat_del = isis_nat_del;
+        p_api->nat_get = isis_nat_get;
+        p_api->nat_next = isis_nat_next;
+        p_api->nat_counter_bind = isis_nat_counter_bind;
+        p_api->napt_add = isis_napt_add;
+        p_api->napt_del = isis_napt_del;
+        p_api->napt_get = isis_napt_get;
+        p_api->napt_next = isis_napt_next;
+        p_api->napt_counter_bind = isis_napt_counter_bind;
+        p_api->nat_status_set = isis_nat_status_set;
+        p_api->nat_status_get = isis_nat_status_get;
+        p_api->nat_hash_mode_set = isis_nat_hash_mode_set;
+        p_api->nat_hash_mode_get = isis_nat_hash_mode_get;
+        p_api->napt_status_set = isis_napt_status_set;
+        p_api->napt_status_get = isis_napt_status_get;
+        p_api->napt_mode_set = isis_napt_mode_set;
+        p_api->napt_mode_get = isis_napt_mode_get;
+        p_api->nat_prv_base_addr_set = isis_nat_prv_base_addr_set;
+        p_api->nat_prv_base_addr_get = isis_nat_prv_base_addr_get;
+        p_api->nat_prv_addr_mode_set = isis_nat_prv_addr_mode_set;
+        p_api->nat_prv_addr_mode_get = isis_nat_prv_addr_mode_get;
+        p_api->nat_pub_addr_add = isis_nat_pub_addr_add;
+        p_api->nat_pub_addr_del = isis_nat_pub_addr_del;
+        p_api->nat_pub_addr_next = isis_nat_pub_addr_next;
+        p_api->nat_unk_session_cmd_set = isis_nat_unk_session_cmd_set;
+        p_api->nat_unk_session_cmd_get = isis_nat_unk_session_cmd_get;
+		p_api->nat_global_set = isis_nat_global_set;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/isis/isis_port_ctrl.c b/qca-ssdk/src/hsl/isis/isis_port_ctrl.c
new file mode 100755
index 0000000..00531cc
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_port_ctrl.c
@@ -0,0 +1,2356 @@
+/*
+ * Copyright (c) 2012, 2015-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_port_ctrl ISIS_PORT_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_port_ctrl.h"
+#include "isis_reg.h"
+#include "hsl_phy.h"
+
+static a_bool_t
+_isis_port_phy_connected(a_uint32_t dev_id, fal_port_t port_id)
+{
+    if ((0 == port_id) || (6 == port_id))
+    {
+        return A_FALSE;
+    }
+    else
+    {
+        return A_TRUE;
+    }
+}
+
+static sw_error_t
+_isis_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_duplex_t duplex)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id, reg_save, reg_val = 0, force, tmp;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_DUPLEX_BUTT <= duplex)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+	SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, tmp, reg_val);
+
+    /* for those ports without PHY device we set MAC register */
+    if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+        if (FAL_HALF_DUPLEX == duplex)
+        {
+		if (tmp == 0)
+			return SW_OK;
+            SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_val);
+        }
+        else
+        {
+		if (tmp == 1)
+			return SW_OK;
+            SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val);
+        }
+        reg_save = reg_val;
+    }
+    else
+    {
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+		if (NULL == phy_drv->phy_duplex_set)
+			return SW_NOT_SUPPORTED;
+		/* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
+		rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR(rv);
+		rv = phy_drv->phy_duplex_get (dev_id, phy_id, &tmp);
+		SW_RTN_ON_ERROR(rv);
+		if (tmp == duplex)
+			return SW_OK;
+        reg_save = reg_val;
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                          (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+
+        rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex);
+        SW_RTN_ON_ERROR(rv);
+
+        /* If MAC not in sync with PHY mode, the behavior is undefine.
+           You must be careful... */
+        SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save);
+        if (!force)
+        {
+            if (FAL_HALF_DUPLEX == duplex)
+            {
+                SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_save);
+            }
+            else
+            {
+                SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_save);
+            }
+        }
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_save), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_duplex_t * pduplex)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, field, reg);
+    if (field)
+    {
+        *pduplex = FAL_FULL_DUPLEX;
+    }
+    else
+    {
+        *pduplex = FAL_HALF_DUPLEX;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isis_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_port_speed_t speed)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id, reg_save, reg_val = 0, force, tmp;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_SPEED_1000 < speed)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+	SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, tmp, reg_val);
+
+    /* for those ports without PHY device we set MAC register */
+    if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+        if (FAL_SPEED_10 == speed)
+        {
+		if (tmp == 0)
+			return SW_OK;
+            SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val);
+        }
+        else if (FAL_SPEED_100 == speed)
+        {
+		if (tmp == 1)
+			return SW_OK;
+            SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val);
+        }
+        else
+        {
+		if (tmp == 2)
+			return SW_OK;
+            SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val);
+        }
+        reg_save = reg_val;
+
+    }
+    else
+    {
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+		if (NULL == phy_drv->phy_speed_set)
+			return SW_NOT_SUPPORTED;
+		/* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
+		rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR(rv);
+		rv = phy_drv->phy_speed_get (dev_id, phy_id, &tmp);
+		SW_RTN_ON_ERROR(rv);
+		if (tmp == speed)
+			return SW_OK;
+        reg_save = reg_val;
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,  0, reg_val);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                          (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+        rv = phy_drv->phy_speed_set (dev_id, phy_id, speed);
+        SW_RTN_ON_ERROR(rv);
+
+        /* If MAC not in sync with PHY mode, the behavior is undefine.
+           You must be careful... */
+        SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save);
+        if (!force)
+        {
+            if (FAL_SPEED_10 == speed)
+            {
+                SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_save);
+            }
+            else if (FAL_SPEED_100 == speed)
+            {
+                SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_save);
+            }
+            else
+            {
+                SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_save);
+            }
+        }
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_save), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_port_speed_t * pspeed)
+{
+    sw_error_t rv = SW_OK;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, field, reg);
+    if (0 == field)
+    {
+        *pspeed = FAL_SPEED_10;
+    }
+    else if (1 == field)
+    {
+        *pspeed = FAL_SPEED_100;
+    }
+    else if (2 == field)
+    {
+        *pspeed = FAL_SPEED_1000;
+    }
+    else
+    {
+        *pspeed = FAL_SPEED_BUTT;
+        rv = SW_READ_ERROR;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isis_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * status)
+{
+    a_uint32_t phy_id;
+    sw_error_t rv;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_autoneg_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *status = phy_drv->phy_autoneg_status_get (dev_id, phy_id);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+   SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+   if (NULL == phy_drv->phy_autoneg_enable_set)
+       return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_autoneg_enable_set(dev_id, phy_id);
+    return rv;
+}
+
+static sw_error_t
+_isis_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_restart_autoneg)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_restart_autoneg (dev_id, phy_id);
+    return rv;
+}
+
+static sw_error_t
+_isis_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t autoadv)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_autoneg_adv_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_autoneg_adv_set(dev_id, phy_id, autoadv);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * autoadv)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_autoneg_adv_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *autoadv = 0;
+    rv = phy_drv->phy_autoneg_adv_get (dev_id, phy_id, autoadv);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val, force, reg = 0, tmp;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+    if (force)
+    {
+        /* flow control isn't in force mode so can't set */
+        return SW_DISABLE;
+    }
+	tmp = reg;
+
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
+	if (tmp == reg)
+		return SW_OK;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t rx, reg = 0;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg);
+
+    if (1 == rx)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, tmp;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+	SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, tmp, reg);
+
+    if (A_TRUE == enable)
+    {
+		if (tmp == 0)
+			return SW_OK;
+        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        /* for those ports without PHY, it can't sync flow control status */
+        if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+        {
+            return SW_DISABLE;
+        }
+		if (tmp == 1)
+			return SW_OK;
+        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t force, reg = 0;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+    if (0 == force)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+   SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+   if (NULL == phy_drv->phy_powersave_set)
+       return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_powersave_set(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_isis_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+   SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+   if (NULL == phy_drv->phy_powersave_get)
+       return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_powersave_get(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_isis_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_hibernation_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_hibernation_set (dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_isis_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_hibernation_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_hibernation_get(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_isis_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+               fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_cdt)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_cdt(dev_id, phy_id, mdi_pair, cable_status, cable_len);
+
+    return rv;
+}
+static sw_error_t
+_isis_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK (dev_id);
+    if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_8023az_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR (rv);
+
+    rv = phy_drv->phy_8023az_set (dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_isis_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id,
+		       a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK (dev_id);
+
+    if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_8023az_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR (rv);
+
+    rv = phy_drv->phy_8023az_get (dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_isis_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_header_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_NO_HEADER_EN == mode)
+    {
+        val = 0;
+    }
+    else if (FAL_ONLY_MANAGE_FRAME_EN == mode)
+    {
+        val = 1;
+    }
+    else if (FAL_ALL_TYPE_FRAME_EN == mode)
+    {
+        val = 2;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_header_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *mode = FAL_ONLY_MANAGE_FRAME_EN;
+    }
+    else if (2 == val)
+    {
+        *mode = FAL_ALL_TYPE_FRAME_EN;
+    }
+    else
+    {
+        *mode = FAL_NO_HEADER_EN;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_header_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_NO_HEADER_EN == mode)
+    {
+        val = 0;
+    }
+    else if (FAL_ONLY_MANAGE_FRAME_EN == mode)
+    {
+        val = 1;
+    }
+    else if (FAL_ALL_TYPE_FRAME_EN == mode)
+    {
+        val = 2;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_header_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *mode = FAL_ONLY_MANAGE_FRAME_EN;
+    }
+    else if (2 == val)
+    {
+        *mode = FAL_ALL_TYPE_FRAME_EN;
+    }
+    else
+    {
+        *mode = FAL_NO_HEADER_EN;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
+{
+    a_uint32_t reg = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        if (0xffff < type)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 1, reg);
+        SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, type, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 0, reg);
+        SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, 0, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HEADER_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
+{
+    a_uint32_t data, reg = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_LEN, data, reg);
+    if (data)
+    {
+        SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_VAL, data, reg);
+        *enable = A_TRUE;
+        *type = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *type = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, force, val, tmp;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+	tmp = reg;
+
+    /* for those ports without PHY device we set MAC register */
+    if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,  0, reg);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg);
+    }
+    else
+    {
+        SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN,  force, reg);
+        if (force)
+        {
+            /* link isn't in force mode so can't set */
+            return SW_DISABLE;
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg);
+        }
+    }
+	if (tmp == reg)
+		return SW_OK;
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TXMAC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, force, val, tmp;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+	tmp = reg;
+
+    /* for those ports without PHY device we set MAC register */
+    if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,  0, reg);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg);
+    }
+    else
+    {
+        SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN,  force, reg);
+        if (force)
+        {
+            /* link isn't in force mode so can't set */
+            return SW_DISABLE;
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg);
+        }
+    }
+	if (tmp == reg)
+		return SW_OK;
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RXMAC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val, reg = 0, force, tmp;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+	tmp = reg;
+
+    /* for those ports without PHY device we set MAC register */
+    if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN,   val, reg);
+    }
+    else
+    {
+        SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+        if (force)
+        {
+            /* flow control isn't in force mode so can't set */
+            return SW_DISABLE;
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+        }
+    }
+	if ( tmp == reg)
+		return SW_OK;
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_FLOW_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val, reg = 0, force, tmp;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+	tmp = reg;
+
+    /* for those ports without PHY device we set MAC register */
+    if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN,   val, reg);
+    }
+    else
+    {
+        SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN,  force, reg);
+        if (force)
+        {
+            /* flow control isn't in force mode so can't set */
+            return SW_DISABLE;
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+        }
+    }
+	if ( tmp == reg)
+		return SW_OK;
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RX_FLOW_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val, tmp = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+	HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+                      (a_uint8_t *) (&tmp), sizeof (a_uint32_t));
+	if (tmp == val)
+		return SW_OK;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, tmp;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+	SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, tmp, reg);
+
+    if (A_TRUE == enable)
+    {
+		if(tmp == 0)
+			return SW_OK;
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+		if(tmp == 1)
+			return SW_OK;
+        /* for those ports without PHY, it can't sync link status */
+        if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+        {
+            return SW_DISABLE;
+        }
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, LINK_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+    /* for those ports without PHY device supposed always link up */
+    if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+    {
+        *status = A_TRUE;
+    }
+    else
+    {
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_link_status_get)
+		return SW_NOT_SUPPORTED;
+
+
+        rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+        SW_RTN_ON_ERROR(rv);
+
+        if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id))
+        {
+            *status = A_TRUE;
+        }
+        else
+        {
+            *status = A_FALSE;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv;
+	a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == val)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_port_duplex_t duplex)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_duplex_set(dev_id, port_id, duplex);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_port_duplex_t * pduplex)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_duplex_get(dev_id, port_id, pduplex);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                    fal_port_speed_t speed)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_speed_set(dev_id, port_id, speed);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                    fal_port_speed_t * pspeed)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_speed_get(dev_id, port_id, pspeed);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_autoneg_status_get(dev_id, port_id, status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_autoneg_enable(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_autoneg_restart(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ *   @details  Comments:
+ *   auto negotiation advtisement ability is defined by macro such as
+ *   FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t autoadv)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_autoneg_adv_set(dev_id, port_id, autoadv);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * autoadv)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_autoneg_adv_get(dev_id, port_id, autoadv);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flow control(rx/tx/bp) status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_flowctrl_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_flowctrl_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_flowctrl_forcemode_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_flowctrl_forcemode_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_powersave_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_powersave_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_hibernate_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_hibernate_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Run cable diagnostic test on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mdi_pair mdi pair id
+ * @param[out] cable_status cable status
+ * @param[out] cable_len cable len
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+              fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len);
+    HSL_API_UNLOCK;
+    return rv;
+}
+/**
+ * @brief Set 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_8023az_set (dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get 8023az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id,
+		      a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_8023az_get (dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_header_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_rxhdr_mode_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_header_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_rxhdr_mode_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_header_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_txhdr_mode_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_header_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_txhdr_mode_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of Atheros header type value on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] type header type value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isis_header_type_set(dev_id, enable, type);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get status of Atheros header type value on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] type header type value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_header_type_get(dev_id, enable, type);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of txmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isis_port_txmac_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get status of txmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_txmac_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of rxmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isis_port_rxmac_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get status of rxmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_rxmac_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of tx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isis_port_txfc_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get status of tx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_txfc_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of rx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isis_port_rxfc_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of rx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_rxfc_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of back pressure on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isis_port_bp_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of back pressure on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_bp_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isis_port_link_forcemode_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_link_forcemode_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get link status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status link status up (A_TRUE) or down (A_FALSE)
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_link_status_get(dev_id, port_id, status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set mac loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isis_port_mac_loopback_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mac loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_mac_loopback_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_port_ctrl_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->port_duplex_get = isis_port_duplex_get;
+        p_api->port_duplex_set = isis_port_duplex_set;
+        p_api->port_speed_get = isis_port_speed_get;
+        p_api->port_speed_set = isis_port_speed_set;
+        p_api->port_autoneg_status_get = isis_port_autoneg_status_get;
+        p_api->port_autoneg_enable = isis_port_autoneg_enable;
+        p_api->port_autoneg_restart = isis_port_autoneg_restart;
+        p_api->port_autoneg_adv_get = isis_port_autoneg_adv_get;
+        p_api->port_autoneg_adv_set = isis_port_autoneg_adv_set;
+        p_api->port_flowctrl_set = isis_port_flowctrl_set;
+        p_api->port_flowctrl_get = isis_port_flowctrl_get;
+        p_api->port_flowctrl_forcemode_set = isis_port_flowctrl_forcemode_set;
+        p_api->port_flowctrl_forcemode_get = isis_port_flowctrl_forcemode_get;
+        p_api->port_powersave_set = isis_port_powersave_set;
+        p_api->port_powersave_get = isis_port_powersave_get;
+        p_api->port_hibernate_set = isis_port_hibernate_set;
+        p_api->port_hibernate_get = isis_port_hibernate_get;
+        p_api->port_cdt = isis_port_cdt;
+        p_api->port_rxhdr_mode_set = isis_port_rxhdr_mode_set;
+        p_api->port_rxhdr_mode_get = isis_port_rxhdr_mode_get;
+        p_api->port_txhdr_mode_set = isis_port_txhdr_mode_set;
+        p_api->port_txhdr_mode_get = isis_port_txhdr_mode_get;
+        p_api->header_type_set = isis_header_type_set;
+        p_api->header_type_get = isis_header_type_get;
+        p_api->port_txmac_status_set = isis_port_txmac_status_set;
+        p_api->port_txmac_status_get = isis_port_txmac_status_get;
+        p_api->port_rxmac_status_set = isis_port_rxmac_status_set;
+        p_api->port_rxmac_status_get = isis_port_rxmac_status_get;
+        p_api->port_txfc_status_set = isis_port_txfc_status_set;
+        p_api->port_txfc_status_get = isis_port_txfc_status_get;
+        p_api->port_rxfc_status_set = isis_port_rxfc_status_set;
+        p_api->port_rxfc_status_get = isis_port_rxfc_status_get;
+        p_api->port_bp_status_set = isis_port_bp_status_set;
+        p_api->port_bp_status_get = isis_port_bp_status_get;
+        p_api->port_link_forcemode_set = isis_port_link_forcemode_set;
+        p_api->port_link_forcemode_get = isis_port_link_forcemode_get;
+        p_api->port_link_status_get = isis_port_link_status_get;
+        p_api->port_mac_loopback_set = isis_port_mac_loopback_set;
+        p_api->port_mac_loopback_get = isis_port_mac_loopback_get;
+        p_api->port_8023az_set = isis_port_8023az_set;
+        p_api->port_8023az_get = isis_port_8023az_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isis/isis_portvlan.c b/qca-ssdk/src/hsl/isis/isis_portvlan.c
new file mode 100755
index 0000000..596bc46
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_portvlan.c
@@ -0,0 +1,2130 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_port_vlan ISIS_PORT_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_portvlan.h"
+#include "isis_reg.h"
+
+#define MAX_VLAN_ID          4095
+#define ISIS_MAX_VLAN_TRANS  64
+#define ISIS_VLAN_TRANS_ADDR 0x5ac00
+
+
+static sw_error_t
+_isis_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, reg = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      COREP_EN, (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                          DEF_SVID, (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                          DEF_CVID, (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_DEFV, (port_id / 2),
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (port_id % 2)
+    {
+        reg &= 0xffff;
+        reg |= ((data & 0xfff) << 16);
+    }
+    else
+    {
+        reg &= 0xffff0000;
+        reg |= (data & 0xfff);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_DEFV, (port_id / 2),
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+    a_uint32_t data, regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_1Q_MODE_BUTT <= port_1qmode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE,
+                      (a_uint8_t *) (&regval[port_1qmode]),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_1Q_DISABLE == port_1qmode)
+    {
+        data = 1;
+    }
+    else
+    {
+        data = 0;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, VLAN_DIS,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK,
+                                  FAL_1Q_CHECK, FAL_1Q_SECURE
+                                };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(pport_1qmode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    *pport_1qmode = retval[regval & 0x3];
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3, 3 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((FAL_EG_MODE_BUTT <= port_egvlanmode)
+            || (FAL_EG_HYBRID == port_egvlanmode))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE,
+                      (a_uint8_t *) (&regval[port_egvlanmode]),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_EG, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0x3 << (port_id << 2)));
+    data |= (regval[port_egvlanmode] << (port_id << 2));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_EG, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_1q_egmode_t retval[4] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED,
+                                     FAL_EG_TAGGED, FAL_EG_UNTOUCHED
+                                   };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(pport_egvlanmode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    *pport_egvlanmode = retval[regval & 0x3];
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    regval |= (0x1UL << mem_port_id);
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isis_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    regval &= (~(0x1UL << mem_port_id));
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isis_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&mem_port_map),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isis_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    *mem_port_map = 0;
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) mem_port_map,
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    val = tpid;
+    HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+                      TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+                      TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *tpid = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_invlan_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t regval[FAL_INVLAN_MODE_BUTT] = { 0, 1, 2 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_INVLAN_MODE_BUTT <= mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE,
+                      (a_uint8_t *) (&regval[mode]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_invlan_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_invlan_mode_t retval[FAL_INVLAN_MODE_BUTT] = { FAL_INVLAN_ADMIT_ALL,
+            FAL_INVLAN_ADMIT_TAGGED, FAL_INVLAN_ADMIT_UNTAGGED
+                                                        };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(mode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (regval >= 3)
+    {
+        return SW_FAIL;
+    }
+    *mode = retval[regval & 0x3];
+
+    return rv;
+}
+
+static sw_error_t
+_isis_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      PRI_PROPAGATION, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      PRI_PROPAGATION, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t vid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (vid > MAX_VLAN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = vid;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_port_route_defv_set(dev_id, port_id);
+    return rv;
+}
+
+static sw_error_t
+_isis_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * vid)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    *vid = val & 0xfff;
+    return rv;
+}
+
+static sw_error_t
+_isis_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t vid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (vid > MAX_VLAN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = vid;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_port_route_defv_set(dev_id, port_id);
+    return rv;
+}
+
+static sw_error_t
+_isis_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * vid)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    *vid = val & 0xfff;
+    return rv;
+}
+
+static sw_error_t
+_isis_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_vlan_propagation_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, p, c;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_VLAN_PROPAGATION_DISABLE == mode)
+    {
+        p = 0;
+        c = 0;
+    }
+    else if (FAL_VLAN_PROPAGATION_CLONE == mode)
+    {
+        p = 1;
+        c = 1;
+    }
+    else if (FAL_VLAN_PROPAGATION_REPLACE == mode)
+    {
+        p = 1;
+        c = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT_VLAN1, PROPAGATION_EN, p, reg);
+    SW_SET_REG_BY_FIELD(PORT_VLAN1, CLONE, c, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_vlan_propagation_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, p, c;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_VLAN1, PROPAGATION_EN, p, reg);
+    SW_GET_FIELD_BY_REG(PORT_VLAN1, CLONE, c, reg);
+
+    if (p)
+    {
+        if (c)
+        {
+            *mode = FAL_VLAN_PROPAGATION_CLONE;
+        }
+        else
+        {
+            *mode = FAL_VLAN_PROPAGATION_REPLACE;
+        }
+    }
+    else
+    {
+        *mode = FAL_VLAN_PROPAGATION_DISABLE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_vlan_trans_read(a_uint32_t dev_id, a_uint32_t entry_idx,
+                      fal_pbmp_t * pbmp, fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, addr, dir, table[2] = {0};
+
+    *pbmp = 0;
+    aos_mem_zero(entry, sizeof (fal_vlan_trans_entry_t));
+
+    addr = ISIS_VLAN_TRANS_ADDR + (entry_idx << 3);
+    /* get vlan trans table */
+    for (i = 0; i < 2; i++)
+    {
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    dir = 0x3 & (table[1] >> 4);
+    if (!dir)
+    {
+        return SW_EMPTY;
+    }
+
+    entry->o_vid = table[0] & 0xfff;
+    *pbmp = (table[1] >> 6) & 0x7f;
+
+    if (3 == dir)
+    {
+        entry->bi_dir = A_TRUE;
+        entry->forward_dir = A_TRUE;
+        entry->reverse_dir = A_TRUE;
+    }
+    else if (1 == dir)
+    {
+        entry->bi_dir = A_FALSE;
+        entry->forward_dir = A_TRUE;
+        entry->reverse_dir = A_FALSE;
+    }
+    else
+    {
+        entry->bi_dir = A_FALSE;
+        entry->forward_dir = A_FALSE;
+        entry->reverse_dir = A_TRUE;
+    }
+
+    entry->o_vid_is_cvid = (table[1] >> 13) & 0x1UL;
+    entry->one_2_one_vlan = (table[1] >> 16) & 0x1UL;
+    entry->s_vid_enable = (table[1] >> 14) & 0x1UL;
+    entry->c_vid_enable = (table[1] >> 15) & 0x1UL;
+
+    if (A_TRUE == entry->s_vid_enable)
+    {
+        entry->s_vid = (table[0] >> 12) & 0xfff;
+    }
+
+    if (A_TRUE == entry->c_vid_enable)
+    {
+        entry->c_vid = ((table[0] >> 24) & 0xff) | ((table[1] & 0xf) << 8);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_vlan_trans_write(a_uint32_t dev_id, a_uint32_t entry_idx, fal_pbmp_t pbmp,
+                       fal_vlan_trans_entry_t entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, addr, table[2] = { 0 };
+
+    addr = ISIS_VLAN_TRANS_ADDR + (entry_idx << 3);
+
+    if (0 != pbmp)
+    {
+        table[0] = entry.o_vid & 0xfff;
+        table[0] |= ((entry.s_vid & 0xfff) << 12);
+        table[0] |= ((entry.c_vid & 0xff) << 24);
+        table[1] = (entry.c_vid >> 8) & 0xf;
+
+        if (A_TRUE == entry.bi_dir)
+        {
+            table[1] |= (0x3 << 4);
+        }
+
+        if (A_TRUE == entry.forward_dir)
+        {
+            table[1] |= (0x1 << 4);
+        }
+
+        if (A_TRUE == entry.reverse_dir)
+        {
+            table[1] |= (0x1 << 5);
+        }
+
+        table[1] |= (pbmp << 6);
+        table[1] |= ((0x1UL & entry.o_vid_is_cvid) << 13);
+        table[1] |= ((0x1UL & entry.s_vid_enable) << 14);
+        table[1] |= ((0x1UL & entry.c_vid_enable) << 15);
+        table[1] |= ((0x1UL & entry.one_2_one_vlan) << 16);
+    }
+
+    /* set vlan trans table */
+    for (i = 0; i < 2; i++)
+    {
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_vlan_trans_convert(fal_vlan_trans_entry_t * entry,
+                              fal_vlan_trans_entry_t * local)
+{
+    aos_mem_copy(local, entry, sizeof (fal_vlan_trans_entry_t));
+
+    if ((A_TRUE == local->bi_dir)
+            || ((A_TRUE == local->forward_dir)
+                && (A_TRUE == local->reverse_dir)))
+    {
+        local->bi_dir = A_TRUE;
+        local->forward_dir = A_TRUE;
+        local->reverse_dir = A_TRUE;
+    }
+
+    if (A_FALSE == local->s_vid_enable)
+    {
+        local->s_vid = 0;
+    }
+
+    if (A_FALSE == local->c_vid_enable)
+    {
+        local->c_vid = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+    fal_pbmp_t t_pbmp;
+    a_uint32_t idx, entry_idx = ISIS_MAX_VLAN_TRANS;
+    fal_vlan_trans_entry_t temp, local;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (NULL == entry)
+    {
+        return SW_BAD_PTR;
+    }
+    aos_mem_zero(&local, sizeof(fal_vlan_trans_entry_t));
+    rv = _isis_port_vlan_trans_convert(entry, &local);
+    SW_RTN_ON_ERROR(rv);
+
+    for (idx = 0; idx < ISIS_MAX_VLAN_TRANS; idx++)
+    {
+        rv = _isis_vlan_trans_read(dev_id, idx, &t_pbmp, &temp);
+        if (SW_EMPTY == rv)
+        {
+            entry_idx = idx;
+            continue;
+        }
+        SW_RTN_ON_ERROR(rv);
+
+        if (!aos_mem_cmp(&local, &temp, sizeof (fal_vlan_trans_entry_t)))
+        {
+            if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+            {
+                return SW_ALREADY_EXIST;
+            }
+            entry_idx = idx;
+            break;
+        }
+        else
+        {
+            t_pbmp = 0;
+        }
+    }
+
+    if (ISIS_MAX_VLAN_TRANS != entry_idx)
+    {
+        t_pbmp |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    return _isis_vlan_trans_write(dev_id, entry_idx, t_pbmp, local);
+}
+
+static sw_error_t
+_isis_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+    fal_pbmp_t t_pbmp;
+    a_uint32_t idx, entry_idx = ISIS_MAX_VLAN_TRANS;
+    fal_vlan_trans_entry_t temp, local;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (NULL == entry)
+    {
+        return SW_BAD_PTR;
+    }
+    aos_mem_zero(&local, sizeof(fal_vlan_trans_entry_t));
+    rv = _isis_port_vlan_trans_convert(entry, &local);
+    SW_RTN_ON_ERROR(rv);
+
+    for (idx = 0; idx < ISIS_MAX_VLAN_TRANS; idx++)
+    {
+        rv = _isis_vlan_trans_read(dev_id, idx, &t_pbmp, &temp);
+        if (SW_EMPTY == rv)
+        {
+            continue;
+        }
+        SW_RTN_ON_ERROR(rv);
+
+        if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t)))
+        {
+            if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+            {
+                entry_idx = idx;
+                break;
+            }
+        }
+    }
+
+    if (ISIS_MAX_VLAN_TRANS != entry_idx)
+    {
+        t_pbmp &= (~(0x1 << port_id));
+    }
+    else
+    {
+        return SW_NOT_FOUND;
+    }
+
+    return _isis_vlan_trans_write(dev_id, entry_idx, t_pbmp, local);
+}
+
+static sw_error_t
+_isis_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+    fal_pbmp_t t_pbmp;
+    a_uint32_t idx;
+    fal_vlan_trans_entry_t temp, local;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (NULL == entry)
+    {
+        return SW_BAD_PTR;
+    }
+    aos_mem_zero(&local, sizeof(fal_vlan_trans_entry_t));
+    rv = _isis_port_vlan_trans_convert(entry, &local);
+    SW_RTN_ON_ERROR(rv);
+
+    for (idx = 0; idx < ISIS_MAX_VLAN_TRANS; idx++)
+    {
+        rv = _isis_vlan_trans_read(dev_id, idx, &t_pbmp, &temp);
+        if (SW_EMPTY == rv)
+        {
+            continue;
+        }
+        SW_RTN_ON_ERROR(rv);
+
+        if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t)))
+        {
+            if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+            {
+                return SW_OK;
+            }
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isis_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * iterator,
+                              fal_vlan_trans_entry_t * entry)
+{
+    a_uint32_t index;
+    sw_error_t rv;
+    fal_vlan_trans_entry_t entry_t;
+    fal_pbmp_t pbmp_t;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((NULL == iterator) || (NULL == entry))
+    {
+        return SW_BAD_PTR;
+    }
+
+    if (ISIS_MAX_VLAN_TRANS < *iterator)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (index = *iterator; index < ISIS_MAX_VLAN_TRANS; index++)
+    {
+        rv = _isis_vlan_trans_read(dev_id, index, &pbmp_t, &entry_t);
+        if (SW_EMPTY == rv)
+        {
+            continue;
+        }
+
+        if (SW_IS_PBMP_MEMBER(pbmp_t, port_id))
+        {
+            aos_mem_copy(entry, &entry_t, sizeof (fal_vlan_trans_entry_t));
+            break;
+        }
+    }
+
+    if (ISIS_MAX_VLAN_TRANS == index)
+    {
+        return SW_NO_MORE;
+    }
+
+    *iterator = index + 1;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t stag = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_QINQ_MODE_BUTT <= mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QINQ_STAG_MODE == mode)
+    {
+        stag = 1;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+                      STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isis_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t stag = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+                      STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (stag)
+    {
+        *mode = FAL_QINQ_STAG_MODE;
+    }
+    else
+    {
+        *mode = FAL_QINQ_CTAG_MODE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_qinq_port_role_t role)
+{
+    sw_error_t rv;
+    a_uint32_t core = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QINQ_PORT_ROLE_BUTT <= role)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QINQ_CORE_PORT == role)
+    {
+        core = 1;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_port_route_defv_set(dev_id, port_id);
+    return rv;
+}
+
+static sw_error_t
+_isis_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_qinq_port_role_t * role)
+{
+    sw_error_t rv;
+    a_uint32_t core = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (core)
+    {
+        *role = FAL_QINQ_CORE_PORT;
+    }
+    else
+    {
+        *role = FAL_QINQ_EDGE_PORT;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id,
+                      EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+
+}
+
+static sw_error_t
+_isis_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id,
+                      EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_1qmode_set(dev_id, port_id, port_1qmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_1qmode_get(dev_id, port_id, pport_1qmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_portvlan_member_add(dev_id, port_id, mem_port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_portvlan_member_del(dev_id, port_id, mem_port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Update member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_portvlan_member_update(dev_id, port_id, mem_port_map);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_portvlan_member_get(dev_id, port_id, mem_port_map);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_force_default_vid_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_force_default_vid_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_force_portvlan_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_force_portvlan_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nestvlan_tpid_set(dev_id, tpid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_nestvlan_tpid_get(dev_id, tpid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_invlan_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_invlan_mode_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_invlan_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_invlan_mode_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_tls_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_tls_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_pri_propagation_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_pri_propagation_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid s-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_default_svid_set(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid s-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_default_svid_get(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid c-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_default_cvid_set(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid c-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_default_cvid_get(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_vlan_propagation_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_vlan_propagation_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_vlan_propagation_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_vlan_propagation_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a vlan translation entry to a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_vlan_trans_add(dev_id, port_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_vlan_trans_del(dev_id, port_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_vlan_trans_get(dev_id, port_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Iterate all vlan translation entries from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] iterator translation entry index if it's zero means get the first entry
+ * @param[out] iterator next valid translation entry index
+ * @param[out] entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * iterator,
+                             fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_vlan_trans_iterate(dev_id, port_id, iterator, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qinq_mode_set(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qinq_mode_get(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qinq_port_role_t role)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_qinq_role_set(dev_id, port_id, role);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qinq_port_role_t * role)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_qinq_role_get(dev_id, port_id, role);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set MAC_VLAN_XLT status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_mac_vlan_xlt_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get MAC_VLAN_XLT status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_mac_vlan_xlt_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#ifdef HSL_STANDALONG
+HSL_LOCAL sw_error_t
+isis_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv =_isis_port_route_defv_set(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+sw_error_t
+isis_portvlan_init(a_uint32_t dev_id)
+{
+    a_uint32_t i;
+    sw_error_t rv;
+    fal_vlan_trans_entry_t entry_init;
+    hsl_api_t *p_api;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    aos_mem_set(&entry_init, 0, sizeof (fal_vlan_trans_entry_t));
+
+    for (i = 0; i < ISIS_MAX_VLAN_TRANS; i++)
+    {
+        rv = _isis_vlan_trans_write(dev_id, i, 0, entry_init);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+#ifndef HSL_STANDALONG
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->port_1qmode_get = isis_port_1qmode_get;
+    p_api->port_1qmode_set = isis_port_1qmode_set;
+    p_api->port_egvlanmode_get = isis_port_egvlanmode_get;
+    p_api->port_egvlanmode_set = isis_port_egvlanmode_set;
+    p_api->portvlan_member_add = isis_portvlan_member_add;
+    p_api->portvlan_member_del = isis_portvlan_member_del;
+    p_api->portvlan_member_update = isis_portvlan_member_update;
+    p_api->portvlan_member_get = isis_portvlan_member_get;
+    p_api->port_force_default_vid_set = isis_port_force_default_vid_set;
+    p_api->port_force_default_vid_get = isis_port_force_default_vid_get;
+    p_api->port_force_portvlan_set = isis_port_force_portvlan_set;
+    p_api->port_force_portvlan_get = isis_port_force_portvlan_get;
+    p_api->nestvlan_tpid_set = isis_nestvlan_tpid_set;
+    p_api->nestvlan_tpid_get = isis_nestvlan_tpid_get;
+    p_api->port_invlan_mode_set = isis_port_invlan_mode_set;
+    p_api->port_invlan_mode_get = isis_port_invlan_mode_get;
+    p_api->port_tls_set = isis_port_tls_set;
+    p_api->port_tls_get = isis_port_tls_get;
+    p_api->port_pri_propagation_set = isis_port_pri_propagation_set;
+    p_api->port_pri_propagation_get = isis_port_pri_propagation_get;
+    p_api->port_default_svid_set = isis_port_default_svid_set;
+    p_api->port_default_svid_get = isis_port_default_svid_get;
+    p_api->port_default_cvid_set = isis_port_default_cvid_set;
+    p_api->port_default_cvid_get = isis_port_default_cvid_get;
+    p_api->port_vlan_propagation_set = isis_port_vlan_propagation_set;
+    p_api->port_vlan_propagation_get = isis_port_vlan_propagation_get;
+    p_api->port_vlan_trans_add = isis_port_vlan_trans_add;
+    p_api->port_vlan_trans_del = isis_port_vlan_trans_del;
+    p_api->port_vlan_trans_get = isis_port_vlan_trans_get;
+    p_api->qinq_mode_set = isis_qinq_mode_set;
+    p_api->qinq_mode_get = isis_qinq_mode_get;
+    p_api->port_qinq_role_set = isis_port_qinq_role_set;
+    p_api->port_qinq_role_get = isis_port_qinq_role_get;
+    p_api->port_vlan_trans_iterate = isis_port_vlan_trans_iterate;
+    p_api->port_mac_vlan_xlt_set = isis_port_mac_vlan_xlt_set;
+    p_api->port_mac_vlan_xlt_get = isis_port_mac_vlan_xlt_get;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/isis/isis_qos.c b/qca-ssdk/src/hsl/isis/isis_qos.c
new file mode 100755
index 0000000..0162b3a
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_qos.c
@@ -0,0 +1,1325 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_qos ISIS_QOS
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_qos.h"
+#include "isis_reg.h"
+
+#define ISIS_QOS_QUEUE_TX_BUFFER_MAX 60
+#define ISIS_QOS_PORT_TX_BUFFER_MAX  252
+#define ISIS_QOS_PORT_RX_BUFFER_MAX  60
+
+//#define ISIS_MIN_QOS_MODE_PRI 0
+#define ISIS_MAX_QOS_MODE_PRI   3
+#define ISIS_MAX_PRI            7
+#define ISIS_MAX_QUEUE          3
+#define ISIS_MAX_EH_QUEUE       5
+
+static sw_error_t
+_isis_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_queue_check(fal_port_t port_id, fal_queue_t queue_id)
+{
+    if ((0 == port_id) || (5 == port_id) || (6 == port_id))
+    {
+        if (ISIS_MAX_EH_QUEUE < queue_id)
+        {
+            return SW_BAD_PARAM;
+        }
+    }
+    else
+    {
+        if (ISIS_MAX_QUEUE < queue_id)
+        {
+            return SW_BAD_PARAM;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_queue_t queue_id, a_uint32_t * number)
+{
+    a_uint32_t data = 0, val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISIS_QOS_QUEUE_TX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isis_qos_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    val = *number / 4;
+    *number = val << 2;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0xf << (queue_id << 2)));
+    data |= (val << (queue_id << 2));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return rv;
+}
+
+static sw_error_t
+_isis_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_queue_t queue_id, a_uint32_t * number)
+{
+    a_uint32_t data= 0, val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isis_qos_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    val = (data >> (queue_id << 2)) & 0xf;
+    *number = val << 2;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISIS_QOS_PORT_TX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = *number / 4;
+    *number = val << 2;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *number = val << 2;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISIS_QOS_PORT_RX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = *number / 4;
+    *number = val << 2;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *number = val << 2;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qos_mode_t mode, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isis_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qos_mode_t mode, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_qos_mode_t mode, a_uint32_t pri)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISIS_MAX_QOS_MODE_PRI < pri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_qos_mode_t mode, a_uint32_t * pri)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0, f_val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    *pri = f_val;
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                            fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val, w[6] = { 0 };
+    a_int32_t i, _index;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SCH_SP_MODE == mode)
+    {
+        val = 0;
+        _index = -1;
+    }
+    else if (FAL_SCH_WRR_MODE == mode)
+    {
+        val = 3;
+        _index = 5;
+    }
+    else if (FAL_SCH_MIX_MODE == mode)
+    {
+        val = 1;
+        _index = 4;
+    }
+    else if (FAL_SCH_MIX_PLUS_MODE == mode)
+    {
+        val = 2;
+        _index = 3;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    for (i = _index; i >= 0; i--)
+    {
+        if (weight[i] > 0x1f)
+        {
+            return SW_BAD_PARAM;
+        }
+        w[i] = weight[i];
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(WRR_CTRL, SCH_MODE, val, reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q5_W, w[5], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q4_W, w[4], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q3_W, w[3], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q2_W, w[2], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q1_W, w[1], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q0_W, w[0], reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, WRR_CTRL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                            fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+    a_uint32_t val = 0, sch, w[6], i;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(WRR_CTRL, SCH_MODE, sch, val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q5_W, w[5], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q4_W, w[4], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q3_W, w[3], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q2_W, w[2], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q1_W, w[1], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q0_W, w[0], val);
+
+    if (0 == sch)
+    {
+        *mode = FAL_SCH_SP_MODE;
+    }
+    else if (1 == sch)
+    {
+        *mode = FAL_SCH_MIX_MODE;
+    }
+    else if (2 == sch)
+    {
+        *mode = FAL_SCH_MIX_PLUS_MODE;
+    }
+    else
+    {
+        *mode = FAL_SCH_WRR_MODE;
+    }
+
+    for (i = 0; i < 6; i++)
+    {
+        weight[i] = w[i];
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t spri)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISIS_MAX_PRI < spri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = spri;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isis_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * spri)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    *spri = val & 0x7;
+    return rv;
+}
+
+static sw_error_t
+_isis_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t cpri)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISIS_MAX_PRI < cpri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = cpri;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isis_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * cpri)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    *cpri = val & 0x7;
+    return rv;
+}
+
+static sw_error_t
+_isis_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t addr, data = 0;
+    a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60};
+
+    rv = _isis_qos_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    addr = base[port_id] + ((queue_id / 4) << 2);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0xff << ((queue_id % 4) << 3)));
+    data |= (((enable << 7 ) | (tbl_id & 0xf)) << ((queue_id % 4) << 3));
+
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isis_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t addr, data = 0;
+    a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60};
+
+    rv = _isis_qos_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    addr = base[port_id] + ((queue_id / 4) << 2);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *tbl_id = (data >> ((queue_id % 4) << 3)) & 0xf;
+    *enable = ((data >> ((queue_id % 4) << 3)) & 0x80) >> 7;
+    return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+_isis_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_bm_static_cfg_t *cfg)
+{
+    sw_error_t rv;
+    a_uint32_t reg_value, xon_value, xoff_value;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_FLOW_CTRL_THRESHOLD, port_id,
+                      (a_uint8_t *) (&reg_value), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_FLOW_CTRL_THRESHOLD, XON_THRES, xon_value, reg_value);
+    SW_GET_FIELD_BY_REG(PORT_FLOW_CTRL_THRESHOLD, XOFF_THRES, xoff_value, reg_value);
+    cfg->max_thresh = xoff_value;
+    cfg->resume_off = xoff_value - xon_value;
+
+    return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+_isis_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_bm_static_cfg_t *cfg)
+{
+    sw_error_t rv;
+    a_uint32_t reg_value = 0;
+
+    SW_SET_REG_BY_FIELD(PORT_FLOW_CTRL_THRESHOLD, XON_THRES, cfg->max_thresh - cfg->resume_off, reg_value);
+    SW_SET_REG_BY_FIELD(PORT_FLOW_CTRL_THRESHOLD, XOFF_THRES, cfg->max_thresh, reg_value);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_FLOW_CTRL_THRESHOLD, port_id,
+                      (a_uint8_t *) (&reg_value), sizeof (a_uint32_t));
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting queue on one particular port.
+ *   @details  Comments:
+ *    If enable queue tx buffer on one port that means each queue of this port
+ *    will have fixed number buffers when transmitting packets. Otherwise they
+ *    share the whole buffers with other queues in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_queue_tx_buf_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting queue on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_queue_tx_buf_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting port on one particular port.
+ *   @details  Comments:
+    If enable tx buffer on one port that means this port will have fixed
+    number buffers when transmitting packets. Otherwise they will
+    share the whole buffers with other ports in device.
+ *    function will return actual buffer numbers in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_tx_buf_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_tx_buf_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting queue on one particular port.
+ *   @details   Comments:
+    The step of buffer number in Garuda is 4, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for queue is 4 to 60.
+ *    share the whole buffers with other ports in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting queue on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting port on one particular port.
+ *   @details   Comments:
+    The step of buffer number in Garuda is four, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for transmitting port is 4 to 124.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_tx_buf_nr_set(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_tx_buf_nr_get(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of receiving port on one particular port.
+ *   @details   Comments:
+    The step of buffer number in Shiva is four, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for receiving port is 4 to 60.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_rx_buf_nr_set(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of receiving port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_rx_buf_nr_get(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_qos_mode_t mode, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_mode_set(dev_id, port_id, mode, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_qos_mode_t mode, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_mode_get(dev_id, port_id, mode, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set priority of one particular qos mode on one particular port.
+ *   @details   Comments:
+    If the priority of a mode is more small then the priority is more high.
+    Differnet mode should have differnet priority.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_qos_mode_t mode, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get priority of one particular qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_qos_mode_t mode, a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set traffic scheduling mode on particular one port.
+ *   @details   Comments:
+ *   When scheduling mode is sp the weight is meaningless usually it's zero
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[in] weight[] weight value for each queue when in wrr mode,
+              the max value supported by ISIS is 0x1f.
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                           fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_sch_mode_set(dev_id, port_id, mode, weight);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get traffic scheduling mode on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] fal_sch_mode_t traffic scheduling mode
+ * @param[out] weight weight value for wrr mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                           fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_sch_mode_get(dev_id, port_id, mode, weight);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default stag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] spri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t spri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_default_spri_set(dev_id, port_id, spri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default stag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] spri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * spri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_default_spri_get(dev_id, port_id, spri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default ctag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cpri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t cpri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_default_cpri_set(dev_id, port_id, cpri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default ctag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cpri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * cpri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_port_default_cpri_get(dev_id, port_id, cpri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress queue based CoS remark on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[in] tbl_id CoS remark table id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_queue_remark_table_set(dev_id, port_id, queue_id, tbl_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress queue based CoS remark on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] tbl_id CoS remark table id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_qos_queue_remark_table_get(dev_id, port_id, queue_id, tbl_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get static flow control threshold on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] static maximum threshold and resume offset
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_bm_static_cfg_t *cfg)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_static_thresh_get(dev_id, port_id, cfg);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set static flow control threshold on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] static maximum threshold and resume offset
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_bm_static_cfg_t *cfg)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_port_static_thresh_set(dev_id, port_id, cfg);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_qos_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->qos_queue_tx_buf_status_set = isis_qos_queue_tx_buf_status_set;
+        p_api->qos_queue_tx_buf_status_get = isis_qos_queue_tx_buf_status_get;
+        p_api->qos_port_tx_buf_status_set = isis_qos_port_tx_buf_status_set;
+        p_api->qos_port_tx_buf_status_get = isis_qos_port_tx_buf_status_get;
+        p_api->qos_queue_tx_buf_nr_set = isis_qos_queue_tx_buf_nr_set;
+        p_api->qos_queue_tx_buf_nr_get = isis_qos_queue_tx_buf_nr_get;
+        p_api->qos_port_tx_buf_nr_set = isis_qos_port_tx_buf_nr_set;
+        p_api->qos_port_tx_buf_nr_get = isis_qos_port_tx_buf_nr_get;
+        p_api->qos_port_rx_buf_nr_set = isis_qos_port_rx_buf_nr_set;
+        p_api->qos_port_rx_buf_nr_get = isis_qos_port_rx_buf_nr_get;
+        p_api->qos_port_mode_set = isis_qos_port_mode_set;
+        p_api->qos_port_mode_get = isis_qos_port_mode_get;
+        p_api->qos_port_mode_pri_set = isis_qos_port_mode_pri_set;
+        p_api->qos_port_mode_pri_get = isis_qos_port_mode_pri_get;
+        p_api->qos_port_sch_mode_set = isis_qos_port_sch_mode_set;
+        p_api->qos_port_sch_mode_get = isis_qos_port_sch_mode_get;
+        p_api->qos_port_default_spri_set = isis_qos_port_default_spri_set;
+        p_api->qos_port_default_spri_get = isis_qos_port_default_spri_get;
+        p_api->qos_port_default_cpri_set = isis_qos_port_default_cpri_set;
+        p_api->qos_port_default_cpri_get = isis_qos_port_default_cpri_get;
+        p_api->qos_queue_remark_table_set = isis_qos_queue_remark_table_set;
+        p_api->qos_queue_remark_table_get = isis_qos_queue_remark_table_get;
+
+        p_api->port_static_thresh_get = isis_port_static_thresh_get;
+        p_api->port_static_thresh_set = isis_port_static_thresh_set;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/isis/isis_rate.c b/qca-ssdk/src/hsl/isis/isis_rate.c
new file mode 100755
index 0000000..8e516ed
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_rate.c
@@ -0,0 +1,1549 @@
+/*
+ * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_rate ISIS_RATE
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_rate.h"
+#include "isis_reg.h"
+
+#define ISIS_MAX_POLICER_ID          31
+#define ISIS_MAX_QUEUE               3
+#define ISIS_MAX_EH_QUEUE            5
+
+#define ACL_POLICER_CNT_SEL_ADDR          0x09f0
+#define ACL_POLICER_CNT_MODE_ADDR         0x09f4
+#define ACL_POLICER_CNT_RST_ADDR          0x09f8
+
+static sw_error_t
+_isis_rate_port_queue_check(fal_port_t port_id, fal_queue_t queue_id)
+{
+    if ((0 == port_id) || (5 == port_id) || (6 == port_id))
+    {
+        if (ISIS_MAX_EH_QUEUE < queue_id)
+        {
+            return SW_BAD_PARAM;
+        }
+    }
+    else
+    {
+        if (ISIS_MAX_QUEUE < queue_id)
+        {
+            return SW_BAD_PARAM;
+        }
+    }
+
+    return SW_OK;
+}
+
+static void
+_isis_egress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+    a_int32_t i;
+    a_uint32_t data[8] =
+    {
+        0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024,
+        512 * 1024
+    };
+
+    for (i = 7; i >= 0; i--)
+    {
+        if (sw_bs >= data[i])
+        {
+            *hw_bs = i;
+            break;
+        }
+    }
+}
+
+static void
+_isis_egress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+    a_uint32_t data[8] =
+    {
+        0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024,
+        512 * 1024
+    };
+
+    *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isis_egress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+    a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 };
+    a_int32_t i;
+
+    for (i = 7; i >= 0; i--)
+    {
+        if (sw_bs >= data[i])
+        {
+            *hw_bs = i;
+            break;
+        }
+    }
+}
+
+static void
+_isis_egress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+    a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 };
+
+    *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isis_ingress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+    a_int32_t i;
+    a_uint32_t data[8] =
+    {
+        0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024,
+        8 * 1024 * 1024, 32 * 1024 * 1024
+    };
+
+    for (i = 7; i >= 0; i--)
+    {
+        if (sw_bs >= data[i])
+        {
+            *hw_bs = i;
+            break;
+        }
+    }
+}
+
+static void
+_isis_ingress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+    a_uint32_t data[8] =
+    {
+        0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024,
+        8 * 1024 * 1024, 32 * 1024 * 1024
+    };
+
+    *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isis_ingress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+    a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 };
+    a_int32_t i;
+
+    for (i = 7; i >= 0; i--)
+    {
+        if (sw_bs >= data[i])
+        {
+            *hw_bs = i;
+            break;
+        }
+    }
+}
+
+static void
+_isis_ingress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+    a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 };
+
+    *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isis_rate_flag_parse(a_uint32_t sw_flag, a_uint32_t * hw_flag)
+{
+    *hw_flag = 0;
+
+    if (FAL_INGRESS_POLICING_TCP_CTRL & sw_flag)
+    {
+        *hw_flag |= (0x1 << 1);
+    }
+
+    if (FAL_INGRESS_POLICING_MANAGEMENT & sw_flag)
+    {
+        *hw_flag |= (0x1 << 2);
+    }
+
+    if (FAL_INGRESS_POLICING_BROAD & sw_flag)
+    {
+        *hw_flag |= (0x1 << 3);
+    }
+
+    if (FAL_INGRESS_POLICING_UNK_UNI & sw_flag)
+    {
+        *hw_flag |= (0x1 << 4);
+    }
+
+    if (FAL_INGRESS_POLICING_UNK_MUL & sw_flag)
+    {
+        *hw_flag |= (0x1 << 5);
+    }
+
+    if (FAL_INGRESS_POLICING_UNI & sw_flag)
+    {
+        *hw_flag |= (0x1 << 6);
+    }
+
+    if (FAL_INGRESS_POLICING_MUL & sw_flag)
+    {
+        *hw_flag |= (0x1 << 7);
+    }
+}
+
+static void
+_isis_rate_flag_reparse(a_uint32_t hw_flag, a_uint32_t * sw_flag)
+{
+    *sw_flag = 0;
+
+    if (hw_flag & 0x2)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_TCP_CTRL;
+    }
+
+    if (hw_flag & 0x4)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_MANAGEMENT;
+    }
+
+    if (hw_flag & 0x8)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_BROAD;
+    }
+
+    if (hw_flag & 0x10)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_UNK_UNI;
+    }
+
+    if (hw_flag & 0x20)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_UNK_MUL;
+    }
+
+    if (hw_flag & 0x40)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_UNI;
+    }
+
+    if (hw_flag & 0x80)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_MUL;
+    }
+}
+
+static void
+_isis_rate_ts_parse(fal_rate_mt_t sw, a_uint32_t * hw)
+{
+    if (FAL_RATE_MI_100US == sw)
+    {
+        *hw = 0;
+    }
+    else if (FAL_RATE_MI_1MS == sw)
+    {
+        *hw = 1;
+    }
+    else if (FAL_RATE_MI_10MS == sw)
+    {
+        *hw = 2;
+    }
+    else if (FAL_RATE_MI_100MS)
+    {
+        *hw = 3;
+    }
+    else
+    {
+        *hw = 0;
+    }
+}
+
+static void
+_isis_rate_ts_reparse(a_uint32_t hw, fal_rate_mt_t * sw)
+{
+    if (0 == hw)
+    {
+        *sw = FAL_RATE_MI_100US;
+    }
+    else if (1 == hw)
+    {
+        *sw = FAL_RATE_MI_1MS;
+    }
+    else if (2 == hw)
+    {
+        *sw = FAL_RATE_MI_10MS;
+    }
+    else
+    {
+        *sw = FAL_RATE_MI_100MS;
+    }
+}
+
+static sw_error_t
+_isis_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+    a_uint32_t cir = 0x7fff, eir = 0x7fff, cbs = 0, ebs = 0, tmp, data[3] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data[0] = 0x18000000;
+    if (FAL_BYTE_BASED == policer->meter_unit)
+    {
+        if (A_TRUE == policer->c_enable)
+        {
+            cir = policer->cir >> 5;
+            policer->cir = cir << 5;
+            _isis_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs);
+            _isis_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+        }
+
+        if (A_TRUE == policer->e_enable)
+        {
+            eir = policer->eir >> 5;
+            policer->eir = eir << 5;
+            _isis_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs);
+            _isis_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+        }
+
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 0, data[1]);
+    }
+    else if (FAL_FRAME_BASED == policer->meter_unit)
+    {
+        if (A_TRUE == policer->c_enable)
+        {
+            cir = (policer->cir * 2) / 125;
+            policer->cir = cir / 2 * 125 + cir % 2 * 63;
+            _isis_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs);
+            _isis_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+        }
+
+        if (A_TRUE == policer->e_enable)
+        {
+            eir = (policer->eir * 2) / 125;
+            policer->eir = eir / 2 * 125 + eir % 2 * 63;
+            _isis_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs);
+            _isis_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+        }
+
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 1, data[1]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]);
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]);
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]);
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]);
+
+    if (A_TRUE == policer->combine_mode)
+    {
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER0, RATE_MODE, 1, data[0]);
+    }
+
+    if (A_TRUE == policer->deficit_en)
+    {
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_BORROW, 1, data[1]);
+    }
+
+    if (A_TRUE == policer->color_mode)
+    {
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CM, 1, data[1]);
+    }
+
+    if (A_TRUE == policer->couple_flag)
+    {
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CF, 1, data[1]);
+    }
+
+    _isis_rate_ts_parse(policer->c_meter_interval, &tmp);
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER0, C_ING_TS, tmp, data[0]);
+
+    _isis_rate_ts_parse(policer->e_meter_interval, &tmp);
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER1, E_ING_TS, tmp, data[1]);
+
+    _isis_rate_flag_parse(policer->c_rate_flag, &tmp);
+    data[2] = (tmp << 8) & 0xff00;
+
+    _isis_rate_flag_parse(policer->e_rate_flag, &tmp);
+    data[2] |= (tmp & 0xff);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER0, port_id,
+                      (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER1, port_id,
+                      (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER2, port_id,
+                      (a_uint8_t *) (&data[2]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+    a_uint32_t unit, ts, cir, eir, cbs, ebs, data[3] = {0};
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER0, port_id,
+                      (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER1, port_id,
+                      (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER2, port_id,
+                      (a_uint8_t *) (&data[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_UNIT, unit, data[1]);
+
+    policer->c_enable = A_TRUE;
+    if (0x7fff == cir)
+    {
+        policer->c_enable = A_FALSE;
+        cir = 0;
+    }
+
+    policer->e_enable = A_TRUE;
+    if (0x7fff == eir)
+    {
+        policer->e_enable = A_FALSE;
+        eir = 0;
+    }
+
+    if (unit)
+    {
+        policer->meter_unit = FAL_FRAME_BASED;
+        policer->cir = cir / 2 * 125 + cir % 2 * 63;
+        policer->eir = eir / 2 * 125 + eir % 2 * 63;
+        _isis_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+        _isis_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+    }
+    else
+    {
+        policer->meter_unit = FAL_BYTE_BASED;
+        policer->cir = cir << 5;
+        policer->eir = eir << 5;
+        _isis_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+        _isis_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+    }
+
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER0, RATE_MODE, policer->combine_mode,
+                        data[0]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_BORROW, policer->deficit_en,
+                        data[1]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CF, policer->couple_flag,
+                        data[1]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CM, policer->color_mode,
+                        data[1]);
+
+    ts = (data[2] >> 8) & 0xff;
+    _isis_rate_flag_reparse(ts, &(policer->c_rate_flag));
+
+    ts = data[2] & 0xff;
+    _isis_rate_flag_reparse(ts, &(policer->e_rate_flag));
+
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER0, C_ING_TS, ts, data[0]);
+    _isis_rate_ts_reparse(ts, &(policer->c_meter_interval));
+
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, E_ING_TS, ts, data[1]);
+    _isis_rate_ts_reparse(ts, &(policer->e_meter_interval));
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    a_uint32_t data, cir, eir, cbs = 0, ebs = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == enable)
+    {
+        aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+        cir = 0x7fff;
+        eir = 0x7fff;
+    }
+    else
+    {
+        if (FAL_BYTE_BASED == shaper->meter_unit)
+        {
+            cir = shaper->cir >> 5;
+            shaper->cir = cir << 5;
+
+            eir = shaper->eir >> 5;
+            shaper->eir = eir << 5;
+
+            _isis_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs);
+            _isis_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+
+            _isis_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs);
+            _isis_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+
+            data = 0;
+        }
+        else if (FAL_FRAME_BASED == shaper->meter_unit)
+        {
+            cir = (shaper->cir * 2) / 125;
+            shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+
+            eir = (shaper->eir * 2) / 125;
+            shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+
+            _isis_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs);
+            _isis_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+
+            _isis_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs);
+            _isis_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+
+            data = 1;
+        }
+        else
+        {
+            return SW_BAD_PARAM;
+        }
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        data = 1;
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+                      (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+                      (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+                      (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+                      (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, cir = 0, eir = 0, cbs = 0, ebs = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (!data)
+    {
+        *enable = A_FALSE;
+        return SW_OK;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+                      (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+                      (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+                      (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+                      (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if ((0x7fff == cir) && (0x7fff == eir))
+    {
+        *enable = A_FALSE;
+        return SW_OK;
+    }
+
+    *enable = A_TRUE;
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        shaper->meter_unit = FAL_FRAME_BASED;
+        shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+        shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+        _isis_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+        _isis_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+    }
+    else
+    {
+        shaper->meter_unit = FAL_BYTE_BASED;
+        shaper->cir = cir << 5;
+        shaper->eir = eir << 5;
+        _isis_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+        _isis_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_queue_t queue_id, a_bool_t enable,
+                            fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    a_uint32_t unit = 0, data, cir, eir, cbs = 0, ebs = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isis_rate_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_FALSE == enable)
+    {
+        aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+        cir = 0x7fff;
+        eir = 0x7fff;
+    }
+    else
+    {
+        if (FAL_BYTE_BASED == shaper->meter_unit)
+        {
+            cir = shaper->cir >> 5;
+            shaper->cir = cir << 5;
+
+            eir = shaper->eir >> 5;
+            shaper->eir = eir << 5;
+
+            _isis_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs);
+            _isis_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+
+            _isis_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs);
+            _isis_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+
+            unit = 0;
+        }
+        else if (FAL_FRAME_BASED == shaper->meter_unit)
+        {
+            cir = (shaper->cir * 2) / 125;
+            shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+
+            eir = (shaper->eir * 2) / 125;
+            shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+
+            _isis_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs);
+            _isis_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+
+            _isis_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs);
+            _isis_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+
+            unit = 1;
+        }
+
+        data = 0;
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (4 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_queue_t queue_id, a_bool_t * enable,
+                            fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, cir = 0, eir = 0, cbs = 0, ebs = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isis_rate_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *enable = A_FALSE;
+        return SW_OK;
+    }
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (4 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    if ((0x7fff == cir) && (0x7fff == eir))
+    {
+        *enable = A_FALSE;
+        return SW_OK;
+    }
+
+    *enable = A_TRUE;
+    if (data)
+    {
+        shaper->meter_unit = FAL_FRAME_BASED;
+        shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+        shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+        _isis_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+        _isis_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+    }
+    else
+    {
+        shaper->meter_unit = FAL_BYTE_BASED;
+        shaper->cir = cir << 5;
+        shaper->eir = eir << 5;
+        _isis_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+        _isis_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+                           fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+    a_uint32_t ts, cir, eir, cbs = 0, ebs = 0, addr, data[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISIS_MAX_POLICER_ID < policer_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == policer->counter_mode)
+    {
+        addr = ACL_POLICER_CNT_SEL_ADDR;
+        data[0] = 0x1;
+        HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+                              (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        addr = ACL_POLICER_CNT_MODE_ADDR;
+        if (FAL_FRAME_BASED == policer->meter_unit)
+        {
+            data[0] = 0x0;
+        }
+        else
+        {
+            data[0] = 0x1;
+        }
+        HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+                              (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        addr = ACL_POLICER_CNT_RST_ADDR;
+        data[0] = 0x1;
+        HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+                              (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        data[0] = 0x0;
+        HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+                              (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        return rv;
+    }
+
+    addr = ACL_POLICER_CNT_SEL_ADDR;
+    data[0] = 0x0;
+    HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+                          (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_BYTE_BASED == policer->meter_unit)
+    {
+        cir = policer->cir >> 5;
+        policer->cir = cir << 5;
+
+        eir = policer->eir >> 5;
+        policer->eir = eir << 5;
+
+        _isis_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs);
+        _isis_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+
+        _isis_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs);
+        _isis_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+
+        SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 0, data[1]);
+    }
+    else if (FAL_FRAME_BASED == policer->meter_unit)
+    {
+        cir = (policer->cir * 2) / 125;
+        policer->cir = cir / 2 * 125 + cir % 2 * 63;
+
+        eir = (policer->eir * 2) / 125;
+        policer->eir = eir / 2 * 125 + eir % 2 * 63;
+
+        _isis_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs);
+        _isis_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+
+        _isis_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs);
+        _isis_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+
+        SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 1, data[1]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CIR, cir, data[0]);
+    SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CBS, cbs, data[0]);
+    SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EIR, eir, data[1]);
+    SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EBS, ebs, data[1]);
+
+    if (A_TRUE == policer->deficit_en)
+    {
+        SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_BORROW, 1, data[1]);
+    }
+
+    if (A_TRUE == policer->color_mode)
+    {
+        SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CM, 1, data[1]);
+    }
+
+    if (A_TRUE == policer->couple_flag)
+    {
+        SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CF, 1, data[1]);
+    }
+
+    _isis_rate_ts_parse(policer->meter_interval, &ts);
+    SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_TS, ts, data[1]);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER0, policer_id,
+                      (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER1, policer_id,
+                      (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isis_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+                           fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+    a_uint32_t unit, ts, cir, eir, cbs, ebs, addr, data[2] = {0};
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISIS_MAX_POLICER_ID < policer_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(policer, sizeof (policer));
+
+    addr = ACL_POLICER_CNT_SEL_ADDR;
+    HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id,
+                          (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data[0])
+    {
+        policer->counter_mode = A_TRUE;
+
+        addr = ACL_POLICER_CNT_MODE_ADDR;
+        HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id,
+                              (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        if (data[0])
+        {
+            policer->meter_unit = FAL_BYTE_BASED;
+        }
+        else
+        {
+            policer->meter_unit = FAL_FRAME_BASED;
+        }
+
+        HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER0, policer_id,
+                          (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER1, policer_id,
+                          (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        policer->counter_low = data[0];
+        policer->counter_high = data[1];
+
+        return SW_OK;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER0, policer_id,
+                      (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER1, policer_id,
+                      (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+
+    SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CIR, cir, data[0]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CBS, cbs, data[0]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EIR, eir, data[1]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EBS, ebs, data[1]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_UNIT, unit, data[1]);
+    if (unit)
+    {
+        policer->meter_unit = FAL_FRAME_BASED;
+        policer->cir = cir / 2 * 125 + cir % 2 * 63;
+        policer->eir = eir / 2 * 125 + eir % 2 * 63;
+        _isis_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+        _isis_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+
+    }
+    else
+    {
+        policer->meter_unit = FAL_BYTE_BASED;
+        policer->cir = cir << 5;
+        policer->eir = eir << 5;
+        _isis_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+        _isis_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CF, policer->couple_flag, data[1]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CM, policer->color_mode, data[1]);
+
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_TS, ts, data[1]);
+    _isis_rate_ts_reparse(ts, &(policer->meter_interval));
+
+    return SW_OK;
+}
+
+sw_error_t
+_isis_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t  number)
+{
+    a_uint32_t val = number;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (val>255)
+        return SW_BAD_PARAM;
+
+    HSL_REG_FIELD_SET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+sw_error_t
+_isis_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t  *number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv = SW_OK;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+
+    HSL_REG_FIELD_GET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    *number = val;
+
+    return rv;
+}
+
+/**
+ * @brief Set port ingress policer parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port ingress policer input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] policer port ingress policer parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_rate_port_policer_set(dev_id, port_id, policer);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port ingress policer parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port ingress policer input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] policer port ingress policer parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_rate_port_policer_get(dev_id, port_id, policer);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port egress shaper parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port egress shaper parameters is meaningless.
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_rate_port_shaper_set(dev_id, port_id, enable, shaper);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port egress shaper parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port egress shaper parameters is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_rate_port_shaper_get(dev_id, port_id, enable, shaper);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set queue egress shaper parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable queue egress shaper parameters is meaningless.
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_queue_t queue_id, a_bool_t enable,
+                           fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_rate_queue_shaper_set(dev_id, port_id, queue_id, enable, shaper);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get queue egress shaper parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable queue egress shaper parameters is meaningless.
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_queue_t queue_id, a_bool_t * enable,
+                           fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_rate_queue_shaper_get(dev_id, port_id, queue_id, enable, shaper);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ACL ingress policer parameters.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+ * @param[in] dev_id device id
+ * @param[in] policer_id ACL policer id
+ * @param[in] policer ACL ingress policer parameters
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+                          fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_rate_acl_policer_set(dev_id, policer_id, policer);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+
+/**
+ * @brief Get ACL ingress policer parameters.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+ * @param[in] dev_id device id
+ * @param[in] policer_id ACL policer id
+ * @param[in] policer ACL ingress policer parameters
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+                          fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_rate_acl_policer_get(dev_id, policer_id, policer);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+isis_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t  number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_rate_port_add_rate_byte_set(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+isis_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t  *number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_rate_port_add_rate_byte_get(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_rate_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->rate_port_policer_set = isis_rate_port_policer_set;
+        p_api->rate_port_policer_get = isis_rate_port_policer_get;
+        p_api->rate_port_shaper_set = isis_rate_port_shaper_set;
+        p_api->rate_port_shaper_get = isis_rate_port_shaper_get;
+        p_api->rate_queue_shaper_set = isis_rate_queue_shaper_set;
+        p_api->rate_queue_shaper_get = isis_rate_queue_shaper_get;
+        p_api->rate_acl_policer_set = isis_rate_acl_policer_set;
+        p_api->rate_acl_policer_get = isis_rate_acl_policer_get;
+        p_api->rate_port_add_rate_byte_set = isis_rate_port_add_rate_byte_set;
+        p_api->rate_port_add_rate_byte_get = isis_rate_port_add_rate_byte_get;
+
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isis/isis_reg_access.c b/qca-ssdk/src/hsl/isis/isis_reg_access.c
new file mode 100755
index 0000000..bdcfc9e
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_reg_access.c
@@ -0,0 +1,507 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "sd.h"
+#include "isis_reg_access.h"
+
+static hsl_access_mode reg_mode;
+
+#if defined(API_LOCK)
+static aos_lock_t mdio_lock;
+#define MDIO_LOCKER_INIT    aos_lock_init(&mdio_lock)
+#define MDIO_LOCKER_LOCK    aos_lock(&mdio_lock)
+#define MDIO_LOCKER_UNLOCK  aos_unlock(&mdio_lock)
+#else
+#define MDIO_LOCKER_INIT
+#define MDIO_LOCKER_LOCK
+#define MDIO_LOCKER_UNLOCK
+#endif
+
+#if defined(REG_ACCESS_SPEEDUP)
+static a_uint32_t mdio_base_addr = 0xffffffff;
+#endif
+
+int
+isis_reg_config_header (a_uint8_t *header,  a_uint8_t wr_flag,
+                        a_uint32_t reg_addr, a_uint8_t cmd_len,
+                        a_uint8_t *val, a_uint32_t seq_num)
+{
+    athrs_header_t athrs_header;
+    athrs_header_regcmd_t reg_cmd;
+    a_uint16_t head_offset = ISIS_HEADER_CMD_LEN + ISIS_HEADER_DATA_LEN;
+    a_uint8_t buf[ISIS_HEADER_CMD_LEN+ISIS_HEADER_LEN+ISIS_HEADER_MAX_DATA_LEN] = { 0 };
+    a_uint16_t data2_offset = ISIS_HEADER_CMD_LEN + ISIS_HEADER_DATA_LEN +  ISIS_HEADER_LEN;
+
+    aos_mem_set(&athrs_header, 0, sizeof(athrs_header));
+    aos_mem_set(&reg_cmd, 0, sizeof(reg_cmd));
+    aos_mem_set(buf,    0, sizeof(buf));
+
+    /*fill atheros header*/
+    athrs_header.version =  2;
+    athrs_header.priority =  0;
+    athrs_header.type =      1;/*READ_WRITE_REG*/
+    athrs_header.broadcast = 0;
+    athrs_header.from_cpu =  1;
+    athrs_header.port_num =  0;
+
+    /*fill in 4 byte type atheros header witch specific header type
+    must config reg 0x98*/
+    buf[head_offset] = (ATHRS_HEADER_4BYTE_VAL & 0xff00)>>8;
+    buf[head_offset+1] = ATHRS_HEADER_4BYTE_VAL & 0xff;
+
+    buf[head_offset+2] = athrs_header.type;
+    buf[head_offset+2] |= athrs_header.priority << 3;
+    buf[head_offset+2] |= athrs_header.version << 6;
+    buf[head_offset+3] = athrs_header.port_num;
+    buf[head_offset+3] |= athrs_header.from_cpu << 7;
+
+    /*fill reg cmd*/
+    if(cmd_len > ISIS_HEADER_MAX_DATA_LEN)
+        cmd_len = ISIS_HEADER_MAX_DATA_LEN;//maximum data length is16 bytes
+    reg_cmd.reg_addr = reg_addr&0x7fffc; /*bit 0:18, lower 2 bits must be 0*/
+    reg_cmd.cmd_len = cmd_len;
+    reg_cmd.cmd = wr_flag;
+    reg_cmd.check_code = 5;
+    reg_cmd.seq_num = seq_num;
+
+    /*bit[0:18], reg addr*/
+    buf[0] = reg_cmd.reg_addr & 0xff;
+    buf[1] = (reg_cmd.reg_addr & 0xff00) >> 8;
+    buf[2] = (reg_cmd.reg_addr & 0x70000) >> 16;
+    /*bit[19:23], cmd data length*/
+    buf[2] |= reg_cmd.cmd_len << 3;
+    /*bit[28], cmd type, read/write*/
+    buf[3] = reg_cmd.cmd << 4;
+    /*bit[29:31],  check code, must be 3'b101*/
+    buf[3] |= reg_cmd.check_code << 5;
+    /*bit[32:63], sequence num*/
+    buf[4] = (reg_cmd.seq_num & 0xff);
+    buf[5] = (reg_cmd.seq_num & 0xff00) >> 8;
+    buf[6] = (reg_cmd.seq_num & 0xff0000) >> 16;
+    buf[7] = (reg_cmd.seq_num & 0xff000000) >> 24;
+
+    if(!wr_flag)//write
+    {
+        aos_mem_copy(buf+ ISIS_HEADER_CMD_LEN , val, ISIS_HEADER_DATA_LEN);
+        if (cmd_len >4 )
+            aos_mem_copy(buf+ data2_offset , val + ISIS_HEADER_DATA_LEN, cmd_len - ISIS_HEADER_DATA_LEN);
+    }
+
+    aos_mem_copy(header, buf, sizeof(buf));
+    return 0;
+}
+
+
+sw_error_t isis_reg_parser_header_skb(a_uint8_t *header_buf, athrs_cmd_resp_t *cmd_resp)
+{
+    a_uint16_t data2_offset = ISIS_HEADER_CMD_LEN + ISIS_HEADER_DATA_LEN + ISIS_HEADER_LEN;
+    aos_mem_set(cmd_resp, 0, sizeof(cmd_resp));
+    cmd_resp->len = header_buf[2] >> 3;
+    if (cmd_resp->len > ISIS_HEADER_MAX_DATA_LEN)
+        return SW_BAD_LEN;
+
+    cmd_resp->seq = 0;
+    cmd_resp->seq = header_buf[4];
+    cmd_resp->seq |= header_buf[5] << 8;
+    cmd_resp->seq |= header_buf[6] << 16;
+    cmd_resp->seq |= header_buf[7] << 24;
+
+    aos_mem_copy (cmd_resp->data, (header_buf + ISIS_HEADER_CMD_LEN), ISIS_HEADER_DATA_LEN);
+    if (cmd_resp->len > 4)
+        aos_mem_copy ((cmd_resp->data+ISIS_HEADER_DATA_LEN), (header_buf + data2_offset), cmd_resp->len-4);
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint8_t value[], a_uint32_t value_len)
+{
+#if 0
+    a_uint32_t reg_word_addr;
+    a_uint32_t phy_addr, reg_val;
+    a_uint16_t phy_val, tmp_val;
+    a_uint8_t phy_reg;
+    sw_error_t rv;
+#else
+	a_uint32_t reg_val;
+#endif
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+#if 0
+    /* change reg_addr to 16-bit word address, 32-bit aligned */
+    reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+    /* configure register high address */
+    phy_addr = 0x18;
+    phy_reg = 0x0;
+    phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+
+#if defined(REG_ACCESS_SPEEDUP)
+    if (phy_val != mdio_base_addr)
+    {
+        rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+        SW_RTN_ON_ERROR(rv);
+
+        mdio_base_addr = phy_val;
+    }
+#else
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+    /* For some registers such as MIBs, since it is read/clear, we should */
+    /* read the lower 16-bit register then the higher one */
+
+    /* read register in lower address */
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+    SW_RTN_ON_ERROR(rv);
+    reg_val = tmp_val;
+
+    /* read register in higher address */
+    reg_word_addr++;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+    SW_RTN_ON_ERROR(rv);
+    reg_val |= (((a_uint32_t)tmp_val) << 16);
+
+#else
+    reg_val = sd_reg_mii_get(dev_id, reg_addr);
+#endif
+    aos_mem_copy(value, &reg_val, sizeof (a_uint32_t));
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                   a_uint32_t value_len)
+{
+#if 0
+    a_uint32_t reg_word_addr;
+    a_uint32_t phy_addr, reg_val;
+    a_uint16_t phy_val;
+    a_uint8_t phy_reg;
+    sw_error_t rv;
+#else
+	a_uint32_t reg_val = 0;
+#endif
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    aos_mem_copy(&reg_val, value, sizeof (a_uint32_t));
+
+#if 0
+    /* change reg_addr to 16-bit word address, 32-bit aligned */
+    reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+    /* configure register high address */
+    phy_addr = 0x18;
+    phy_reg = 0x0;
+    phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+
+#if defined(REG_ACCESS_SPEEDUP)
+    if (phy_val != mdio_base_addr)
+    {
+        rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+        SW_RTN_ON_ERROR(rv);
+
+        mdio_base_addr = phy_val;
+    }
+#else
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+    /* For some registers such as ARL and VLAN, since they include BUSY bit */
+    /* in higher address, we should write the lower 16-bit register then the */
+    /* higher one */
+
+    /* write register in lower address */
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (a_uint16_t) (reg_val & 0xffff);
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    /* write register in higher address */
+    reg_word_addr++;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff);
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+#else
+    sd_reg_mii_set(dev_id, reg_addr, reg_val);
+#endif
+    return SW_OK;
+}
+
+sw_error_t
+isis_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+             a_uint32_t reg, a_uint16_t * value)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value);
+    MDIO_LOCKER_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+             a_uint32_t reg, a_uint16_t value)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value);
+    MDIO_LOCKER_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+             a_uint32_t value_len)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    if (HSL_MDIO == reg_mode)
+    {
+        rv = _isis_mdio_reg_get(dev_id, reg_addr, value, value_len);
+    }
+    else
+    {
+        rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len);
+    }
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+isis_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+             a_uint32_t value_len)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    if (HSL_MDIO == reg_mode)
+    {
+        rv = _isis_mdio_reg_set(dev_id, reg_addr, value, value_len);
+    }
+    else
+    {
+        rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len);
+    }
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+isis_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint32_t bit_offset, a_uint32_t field_len,
+                   a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val = 0;
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(isis_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len);
+    return SW_OK;
+}
+
+sw_error_t
+isis_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint32_t bit_offset, a_uint32_t field_len,
+                   const a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val = 0;
+    a_uint32_t field_val = *((a_uint32_t *) value);
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(isis_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len);
+
+    SW_RTN_ON_ERROR(isis_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump)
+{
+    sw_error_t rv = SW_OK;
+	typedef struct {
+		a_uint32_t reg_base;
+		a_uint32_t reg_end;
+		char name[30];
+	} regdump;
+
+	regdump reg_dumps[8] =
+	{
+		{0x0, 0xE4, "0.Global control registers"},
+		{0x100, 0x168, "1.EEE control registers"},
+		{0x200, 0x270, "2.Parser control registers"},
+		{0x400, 0x474, "3.ACL control registers"},
+		{0x600, 0x718, "4.Lookup control registers"},
+		{0x800, 0xb70, "5.QM control registers"},
+		{0xc00, 0xc80, "6.PKT edit control registers"},
+		{0x820, 0x820, "7.QM debug registers"}
+	};
+
+	a_uint32_t dump_addr, reg_count, reg_val = 0;
+	switch (register_idx)
+	{
+		case 0:
+		case 1:
+		case 2:
+		case 3:
+		case 4:
+		case 5:
+		case 6:
+			reg_count = 0;
+			for (dump_addr = reg_dumps[register_idx].reg_base; dump_addr <= reg_dumps[register_idx].reg_end; reg_count++)
+			{
+				rv = isis_reg_get(dev_id, dump_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t));
+				reg_dump->reg_value[reg_count] = reg_val;
+				dump_addr += 4;
+			}
+			reg_dump->reg_count = reg_count;
+			reg_dump->reg_base = reg_dumps[register_idx].reg_base;
+			reg_dump->reg_end = reg_dumps[register_idx].reg_end;
+			snprintf((char *)reg_dump->reg_name,sizeof(reg_dump->reg_name),"%s",reg_dumps[register_idx].name);
+			break;
+		default:
+			return SW_BAD_PARAM;
+	}
+
+    return rv;
+}
+
+static sw_error_t
+_isis_debug_regsiter_dump(a_uint32_t dev_id,fal_debug_reg_dump_t * dbg_reg_dump)
+{
+    sw_error_t rv = SW_OK;
+    a_uint32_t reg;
+	a_uint32_t  reg_count, reg_val = 0;
+
+	reg_count = 0;
+
+	for(reg=0;reg<=0x1F;reg++)
+	{
+		isis_reg_set(dev_id, 0x820, (a_uint8_t *) & reg, sizeof (a_uint32_t));
+		rv = isis_reg_get(dev_id, 0x824, (a_uint8_t *) & reg_val, sizeof (a_uint32_t));
+		dbg_reg_dump->reg_value[reg_count] = reg_val;
+		dbg_reg_dump->reg_addr[reg_count] = reg;
+		reg_count++;
+	}
+	dbg_reg_dump->reg_count = reg_count;
+
+	snprintf((char *)dbg_reg_dump->reg_name,sizeof(dbg_reg_dump->reg_name),"QM debug registers");
+
+    return rv;
+}
+
+
+/**
+ * @brief dump registers.
+ * @param[in] dev_id device id
+ * @param[in] register_idx register group id
+ * @param[out] reg_dump register dump result
+ * @return SW_OK or error code
+ */
+sw_error_t
+isis_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _isis_regsiter_dump(dev_id,register_idx,reg_dump);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief dump registers.
+ * @param[in] dev_id device id
+ * @param[out] reg_dump debug register dump
+ * @return SW_OK or error code
+ */
+sw_error_t
+isis_debug_regsiter_dump(a_uint32_t dev_id, fal_debug_reg_dump_t * dbg_reg_dump)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _isis_debug_regsiter_dump(dev_id,dbg_reg_dump);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+sw_error_t
+isis_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode)
+{
+    hsl_api_t *p_api;
+
+    MDIO_LOCKER_INIT;
+    reg_mode = mode;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+    p_api->phy_get = isis_phy_get;
+    p_api->phy_set = isis_phy_set;
+    p_api->reg_get = isis_reg_get;
+    p_api->reg_set = isis_reg_set;
+    p_api->reg_field_get = isis_reg_field_get;
+    p_api->reg_field_set = isis_reg_field_set;
+	p_api->register_dump = isis_regsiter_dump;
+	p_api->debug_register_dump = isis_debug_regsiter_dump;
+
+    return SW_OK;
+}
+
+sw_error_t
+isis_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode)
+{
+    reg_mode = mode;
+    return SW_OK;
+
+}
+
diff --git a/qca-ssdk/src/hsl/isis/isis_sec.c b/qca-ssdk/src/hsl/isis/isis_sec.c
new file mode 100755
index 0000000..912d09c
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_sec.c
@@ -0,0 +1,787 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_sec ISIS_SEC
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_sec.h"
+#include "isis_reg.h"
+
+#define NORM_CTRL0_ADDR 0x0200
+#define NORM_CTRL1_ADDR 0x0204
+#define NORM_CTRL2_ADDR 0x0208
+#define NORM_CTRL3_ADDR 0x0c00
+
+static sw_error_t
+_isis_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+    fal_fwd_cmd_t cmd;
+    a_bool_t enable;
+    a_uint32_t addr, offset, len, reg = 0, val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    cmd = *((fal_fwd_cmd_t *) value);
+    enable = *((a_bool_t *) value);
+    val = *((a_uint32_t *) value);
+
+    len = 1;
+    switch (item)
+    {
+        case FAL_NORM_MAC_RESV_VID_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 0;
+            goto cmd_chk;
+
+        case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 20;
+            goto cmd_chk;
+
+        case FAL_NORM_IP_INVALID_VER_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 1;
+            goto cmd_chk;
+
+        case FAL_NROM_IP_SAME_ADDR_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 2;
+            goto cmd_chk;
+            break;
+
+        case FAL_NROM_IP_TTL_CHANGE_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 11;
+            goto sts_chk;
+
+        case FAL_NROM_IP_TTL_VALUE:
+            addr = NORM_CTRL3_ADDR;
+            offset = 12;
+            len = 8;
+            goto set_reg;
+
+        case FAL_NROM_IP4_INVALID_HL_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 3;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_HDR_OPTIONS_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 4;
+            len = 2;
+            goto s_cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_DF_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 7;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 8;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE:
+            addr = NORM_CTRL1_ADDR;
+            offset = 24;
+            len = 8;
+            goto set_reg;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 9;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 10;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_SIP_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 11;
+            len = 1;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_DIP_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 12;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 13;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_PL_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 19;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_DF_CLEAR_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 9;
+            goto sts_chk;
+
+        case FAL_NROM_IP4_IPID_RANDOM_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 10;
+            goto sts_chk;
+
+        case FAL_NROM_IP6_INVALID_DIP_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 16;
+            goto cmd_chk;
+
+        case FAL_NROM_IP6_INVALID_SIP_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 17;
+            goto cmd_chk;
+
+        case FAL_NROM_IP6_INVALID_PL_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 18;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_BLAT_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 14;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_INVALID_HL_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 15;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_MIN_HDR_SIZE:
+            addr = NORM_CTRL1_ADDR;
+            offset = 12;
+            len = 4;
+            goto set_reg;
+
+        case FAL_NROM_TCP_INVALID_SYN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 16;
+            goto cmd_chk;
+            break;
+
+        case FAL_NROM_TCP_SU_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 17;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SP_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 18;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SAP_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 19;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_XMAS_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 20;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_NULL_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 21;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SR_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 22;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SF_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 23;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SAR_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 24;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_RST_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 25;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SYN_WITH_DATA_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 26;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_RST_WITH_DATA_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 27;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_FA_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 28;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_PA_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 29;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_UA_BLOCK_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 0;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 1;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_INVALID_URGPTR_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 2;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_INVALID_OPTIONS_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 3;
+            goto cmd_chk;
+
+        case FAL_NROM_UDP_BLAT_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 4;
+            goto cmd_chk;
+
+        case FAL_NROM_UDP_INVALID_LEN_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 5;
+            goto cmd_chk;
+
+        case FAL_NROM_UDP_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 6;
+            goto cmd_chk;
+
+        case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 7;
+            goto cmd_chk;
+
+        case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 8;
+            goto cmd_chk;
+
+        case FAL_NROM_ICMP4_PING_FRAG_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 9;
+            goto cmd_chk;
+
+        case FAL_NROM_ICMP6_PING_FRAG_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 10;
+            goto cmd_chk;
+
+        case FAL_NROM_ICMP4_PING_MAX_PL_VALUE:
+            addr = NORM_CTRL2_ADDR;
+            offset = 0;
+            len = 14;
+            goto set_reg;
+
+        case FAL_NROM_ICMP6_PING_MAX_PL_VALUE:
+            addr = NORM_CTRL2_ADDR;
+            offset = 16;
+            len = 14;
+            goto set_reg;
+
+        default:
+            return SW_BAD_PARAM;
+    }
+
+sts_chk:
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    goto set_reg;
+
+s_cmd_chk:
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_DROP == cmd)
+    {
+        val = 3;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 2;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    goto set_reg;
+
+cmd_chk:
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_DROP == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+set_reg:
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_REG_SET_BY_FIELD_U32(reg, val, offset, len);
+
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+    a_uint32_t addr, offset, len, reg = 0, val;
+    a_uint32_t status_chk = 0, val_chk = 0, scmd_chk = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    len = 1;
+    switch (item)
+    {
+        case FAL_NORM_MAC_RESV_VID_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 0;
+            break;
+
+        case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 20;
+            break;
+
+        case FAL_NORM_IP_INVALID_VER_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 1;
+            break;
+
+        case FAL_NROM_IP_SAME_ADDR_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 2;
+            break;
+
+        case FAL_NROM_IP_TTL_CHANGE_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 11;
+            status_chk = 1;
+            break;
+
+        case FAL_NROM_IP_TTL_VALUE:
+            addr = NORM_CTRL3_ADDR;
+            offset = 12;
+            len = 8;
+            val_chk = 1;
+            break;
+
+        case FAL_NROM_IP4_INVALID_HL_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 3;
+            break;
+
+        case FAL_NROM_IP4_HDR_OPTIONS_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 4;
+            len = 2;
+            scmd_chk = 1;
+            break;
+
+        case FAL_NROM_IP4_INVALID_DF_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 7;
+            break;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 8;
+            break;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE:
+            addr = NORM_CTRL1_ADDR;
+            offset = 24;
+            len = 8;
+            val_chk = 1;
+            break;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 9;
+            break;
+
+        case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 10;
+            break;
+
+        case FAL_NROM_IP4_INVALID_SIP_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 11;
+            len = 1;
+            break;
+
+        case FAL_NROM_IP4_INVALID_DIP_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 12;
+            break;
+
+        case FAL_NROM_IP4_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 13;
+            break;
+
+        case FAL_NROM_IP4_INVALID_PL_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 19;
+            break;
+
+        case FAL_NROM_IP4_DF_CLEAR_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 9;
+            status_chk = 1;
+            break;
+
+        case FAL_NROM_IP4_IPID_RANDOM_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 10;
+            status_chk = 1;
+            break;
+
+        case FAL_NROM_IP6_INVALID_DIP_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 16;
+            break;
+
+        case FAL_NROM_IP6_INVALID_SIP_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 17;
+            break;
+
+        case FAL_NROM_IP6_INVALID_PL_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 18;
+            break;
+
+        case FAL_NROM_TCP_BLAT_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 14;
+            break;
+
+        case FAL_NROM_TCP_INVALID_HL_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 15;
+            break;
+
+        case FAL_NROM_TCP_MIN_HDR_SIZE:
+            addr = NORM_CTRL1_ADDR;
+            offset = 12;
+            len = 4;
+            val_chk = 1;
+            break;
+
+        case FAL_NROM_TCP_INVALID_SYN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 16;
+            break;
+
+        case FAL_NROM_TCP_SU_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 17;
+            break;
+
+        case FAL_NROM_TCP_SP_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 18;
+            break;
+
+        case FAL_NROM_TCP_SAP_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 19;
+            break;
+
+        case FAL_NROM_TCP_XMAS_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 20;
+            break;
+
+        case FAL_NROM_TCP_NULL_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 21;
+            break;
+
+        case FAL_NROM_TCP_SR_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 22;
+            break;
+
+        case FAL_NROM_TCP_SF_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 23;
+            break;
+
+        case FAL_NROM_TCP_SAR_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 24;
+            break;
+
+        case FAL_NROM_TCP_RST_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 25;
+            break;
+
+        case FAL_NROM_TCP_SYN_WITH_DATA_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 26;
+            break;
+
+        case FAL_NROM_TCP_RST_WITH_DATA_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 27;
+            break;
+
+        case FAL_NROM_TCP_FA_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 28;
+            break;
+
+        case FAL_NROM_TCP_PA_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 29;
+            break;
+
+        case FAL_NROM_TCP_UA_BLOCK_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 0;
+            break;
+
+        case FAL_NROM_TCP_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 1;
+            break;
+
+        case FAL_NROM_TCP_INVALID_URGPTR_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 2;
+            break;
+
+        case FAL_NROM_TCP_INVALID_OPTIONS_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 3;
+            break;
+
+        case FAL_NROM_UDP_BLAT_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 4;
+            break;
+
+        case FAL_NROM_UDP_INVALID_LEN_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 5;
+            break;
+
+        case FAL_NROM_UDP_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 6;
+            break;
+
+        case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 7;
+            break;
+
+        case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 8;
+            break;
+
+        case FAL_NROM_ICMP4_PING_FRAG_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 9;
+            break;
+
+        case FAL_NROM_ICMP6_PING_FRAG_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 10;
+            break;
+
+        case FAL_NROM_ICMP4_PING_MAX_PL_VALUE:
+            addr = NORM_CTRL2_ADDR;
+            offset = 0;
+            len = 14;
+            val_chk = 1;
+            break;
+
+        case FAL_NROM_ICMP6_PING_MAX_PL_VALUE:
+            addr = NORM_CTRL2_ADDR;
+            offset = 16;
+            len = 14;
+            val_chk = 1;
+            break;
+
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_FIELD_GET_BY_REG_U32(reg, val, offset, len);
+
+    if (val_chk)
+    {
+        *((a_uint32_t *) value) = val;
+    }
+    else if (status_chk)
+    {
+        if (val)
+        {
+            *((a_bool_t *) value) = A_TRUE;
+        }
+        else
+        {
+            *((a_bool_t *) value) = A_FALSE;
+        }
+    }
+    else if (scmd_chk)
+    {
+        if (2 == val)
+        {
+            *((fal_fwd_cmd_t *) value) = FAL_MAC_RDT_TO_CPU;
+        }
+        else if (3 == val)
+        {
+            *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP;
+        }
+        else
+        {
+            *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD;
+        }
+    }
+    else
+    {
+        if (val)
+        {
+            *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP;
+        }
+        else
+        {
+            *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD;
+        }
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set normalization particular item types value.
+ * @details   Comments:
+ *       This operation will set normalization item values on a particular device.
+ *       The prototye of value based on the item type.
+ * @param[in] dev_id device id
+ * @param[in] item normalizaton item type
+ * @param[in] value normalizaton item value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_sec_norm_item_set(dev_id, item, value);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get normalization particular item types value.
+ * @details   Comments:
+ *       This operation will set normalization item values on a particular device.
+ *       The prototye of value based on the item type.
+ * @param[in] dev_id device id
+ * @param[in] item normalizaton item type
+ * @param[out] value normalizaton item value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_sec_norm_item_get(dev_id, item, value);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_sec_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->sec_norm_item_set = isis_sec_norm_item_set;
+        p_api->sec_norm_item_get = isis_sec_norm_item_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/isis/isis_stp.c b/qca-ssdk/src/hsl/isis/isis_stp.c
new file mode 100755
index 0000000..3d0581b
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_stp.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_stp ISIS_STP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_stp.h"
+#include "isis_reg.h"
+
+#define ISIS_PORT_DISABLED      0
+#define ISIS_STP_BLOCKING       1
+#define ISIS_STP_LISTENING      2
+#define ISIS_STP_LEARNING       3
+#define ISIS_STP_FARWARDING     4
+
+static sw_error_t
+_isis_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                         fal_port_t port_id, fal_stp_state_t state)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SINGLE_STP_ID != st_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    switch (state)
+    {
+        case FAL_STP_BLOKING:
+            val = ISIS_STP_BLOCKING;
+            break;
+        case FAL_STP_LISTENING:
+            val = ISIS_STP_LISTENING;
+            break;
+        case FAL_STP_LEARNING:
+            val = ISIS_STP_LEARNING;
+            break;
+        case FAL_STP_FARWARDING:
+            val = ISIS_STP_FARWARDING;
+            break;
+        case FAL_STP_DISABLED:
+            val =  ISIS_PORT_DISABLED;
+            break;
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                         fal_port_t port_id, fal_stp_state_t * state)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SINGLE_STP_ID != st_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    switch (val)
+    {
+        case ISIS_STP_BLOCKING:
+            *state = FAL_STP_BLOKING;
+            break;
+        case ISIS_STP_LISTENING:
+            *state = FAL_STP_LISTENING;
+            break;
+        case ISIS_STP_LEARNING:
+            *state = FAL_STP_LEARNING;
+            break;
+        case ISIS_STP_FARWARDING:
+            *state = FAL_STP_FARWARDING;
+            break;
+        case ISIS_PORT_DISABLED:
+            *state = FAL_STP_DISABLED;
+            break;
+        default:
+            return SW_FAIL;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set port stp state on a particular spanning tree and port.
+ *   @details   Comments:
+    Garuda only support single spanning tree so st_id should be
+    FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[in] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                        fal_port_t port_id, fal_stp_state_t state)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_stp_port_state_set(dev_id, st_id, port_id, state);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port stp state on a particular spanning tree and port.
+ *   @details  Comments:
+    Garuda only support single spanning tree so st_id should be
+    FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[out] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                        fal_port_t port_id, fal_stp_state_t * state)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_stp_port_state_get(dev_id, st_id, port_id, state);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_stp_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->stp_port_state_set = isis_stp_port_state_set;
+        p_api->stp_port_state_get = isis_stp_port_state_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isis/isis_trunk.c b/qca-ssdk/src/hsl/isis/isis_trunk.c
new file mode 100755
index 0000000..d0767d2
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_trunk.c
@@ -0,0 +1,692 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+ * @defgroup isis_trunk ISIS_TRUNK
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_trunk.h"
+#include "isis_reg.h"
+
+#define ISIS_MAX_TRUNK_ID    3
+
+/*feature on/off for manipulating dp within trunk group*/
+#define ISIS_TRUNK_MANIPULATE_DP_ON       1
+#define ISIS_TRUNK_MANIPULATE_HEADER_LEN 12
+#define MAC_LEN                           6
+#define HASH_SIZE                         4
+
+enum isis_trunk_reg_id
+{
+    ISIS_TRUNK_HASH_EN = 0, /*0x270*/
+    ISIS_TRUNK_CTRL_0,        /*0x700*/
+    ISIS_TRUNK_CTRL_1,        /*0x704*/
+    ISIS_TRUNK_CTRL_2,        /*0x708*/
+    ISIS_TRUNK_REG_MAX
+};
+
+static a_uint32_t isis_trunk_regs[ISIS_TRUNK_REG_MAX] =
+{
+    0xf, 0x0, 0x0, 0x0
+};
+
+static a_uint8_t sa_hash[HASH_SIZE][MAC_LEN] =
+{
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 },
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 },
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x03 }
+};
+
+static sw_error_t
+_isis_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+                      a_bool_t enable, fal_pbmp_t member)
+{
+    sw_error_t rv;
+    a_uint32_t i, reg = 0, cnt = 0, data0 = 0, data1 = 0;
+
+    if (ISIS_MAX_TRUNK_ID < trunk_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data0 = (0x1 << 7) | member;
+
+        for (i = 0; i < 7; i++)
+        {
+            if (member & (0x1 << i))
+            {
+                if (4 <= cnt)
+                {
+                    return SW_BAD_PARAM;
+                }
+
+                data1 |= (i << (cnt << 2));
+                data1 |= (1 << (3 + (cnt << 2)));
+                cnt++;
+            }
+        }
+    }
+    else if (A_FALSE == enable)
+    {
+
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    /* set trunk port member bitmap info */
+    HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    reg &= (~(0xff << (trunk_id << 3)));
+    reg |= (data0 << (trunk_id << 3));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    isis_trunk_regs[ISIS_TRUNK_CTRL_0] = reg;
+
+    /* set trunk port member id info */
+    HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1),
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    reg &= (~(0xffff << ((trunk_id % 2) << 4)));
+    reg |= (data1 << ((trunk_id % 2) << 4));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1),
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    isis_trunk_regs[ISIS_TRUNK_CTRL_1 + (trunk_id >> 1)] = reg;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+                      a_bool_t * enable, fal_pbmp_t * member)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg = 0;
+
+    if (ISIS_MAX_TRUNK_ID < trunk_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (reg >> (trunk_id << 3)) & 0xff;
+    if (0x80 & data)
+    {
+        *enable = A_TRUE;
+        *member = data & 0x7f;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *member = 0;
+    }
+
+    return SW_OK;
+}
+
+#if 0
+static sw_error_t
+_isis_trunk_group_sw_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+                         a_bool_t * enable, fal_pbmp_t * member)
+{
+    a_uint32_t data, reg;
+
+    if (ISIS_MAX_TRUNK_ID < trunk_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    reg = isis_trunk_regs[ISIS_TRUNK_CTRL_0];
+
+    data = (reg >> (trunk_id << 3)) & 0xff;
+    if (0x80 & data)
+    {
+        *enable = A_TRUE;
+        *member = data & 0x7f;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *member = 0;
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isis_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (FAL_TRUNK_HASH_KEY_DA & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DA_EN, 1, data);
+    }
+
+    if (FAL_TRUNK_HASH_KEY_SA & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SA_EN, 1, data);
+    }
+
+    if (FAL_TRUNK_HASH_KEY_DIP & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DIP_EN, 1, data);
+    }
+
+    if (FAL_TRUNK_HASH_KEY_SIP & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SIP_EN, 1, data);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, TRUNK_HASH_MODE, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    isis_trunk_regs[ISIS_TRUNK_HASH_EN] = data;
+
+    return rv;
+}
+
+static sw_error_t
+_isis_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, TRUNK_HASH_MODE, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *hash_mode = 0;
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DA_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_DA;
+    }
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SA_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_SA;
+    }
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DIP_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_DIP;
+    }
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SIP_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_SIP;
+    }
+
+    return SW_OK;
+}
+
+#define BYTE_B2R(x, mask) ((x) ^ (mask))
+#define BYTE_B1C(x) ((((((x&0x55)+((x&0xaa)>>1))&0x33)+((((x&0x55)+((x&0xaa)>>1))&0xcc)>>2))&0x0f)+((((((x&0x55)+((x&0xaa)>>1))&0x33)+((((x&0x55)+((x&0xaa)>>1))&0xcc)>>2))&0xf0)>>4))
+
+static sw_error_t
+_isis_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < HASH_SIZE; i++)
+    {
+        memcpy(sa_hash[i], addr->uc, MAC_LEN);
+        sa_hash[i][MAC_LEN - 1] = BYTE_B2R(sa_hash[i][MAC_LEN - 1], i);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    memcpy(addr->uc, sa_hash[0], MAC_LEN);
+    return SW_OK;
+}
+
+#if 0
+static sw_error_t
+_isis_trunk_hash_mode_sw_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    a_uint32_t reg, data = 0;
+
+    reg = isis_trunk_regs[ISIS_TRUNK_HASH_EN];
+
+    *hash_mode = 0;
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DA_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_DA;
+    }
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SA_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_SA;
+    }
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DIP_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_DIP;
+    }
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SIP_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_SIP;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_trunk_id_member_get(a_uint32_t dev_id, a_uint8_t expect_dp,
+                          a_uint32_t * trunk_id, fal_pbmp_t * member)
+{
+    sw_error_t rv;
+    a_bool_t   enable;
+    a_uint32_t i;
+
+    for (i = 0; i <= ISIS_MAX_TRUNK_ID; i++)
+    {
+        rv = _isis_trunk_group_sw_get(dev_id, i, &enable, member);
+        SW_RTN_ON_ERROR(rv);
+        if (enable && (*member & expect_dp))
+        {
+            *trunk_id = i;
+            return SW_OK;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isis_trunk_hash_dp_get(a_uint32_t dev_id, a_uint8_t * header, a_uint32_t len,
+                        a_uint32_t trunk_id, a_uint32_t mode, a_uint8_t * hash_dp)
+{
+#define BIT2_MASK 0x03
+#define TRUNK_MEM_EN_MASK 0x8
+#define TRUNK_MEM_PT_MASK 0x7
+#define TRUNK_HASH_DP_SEL   4
+    sw_error_t rv;
+    a_uint32_t i, hash_mode, reg, data1 = 0;
+    a_uint32_t da_xor = 0, sa_xor = 0; /*consider da-hash & sa-hash (TBD: dip-hash & sip-hash)*/
+    a_uint8_t  xor_dp = 0;
+
+    rv = _isis_trunk_hash_mode_sw_get(dev_id, &hash_mode);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!hash_mode)
+    {
+        return SW_DISABLE;
+    }
+
+    *hash_dp = 0;
+
+    if ((mode & FAL_TRUNK_HASH_KEY_DA) && (hash_mode & FAL_TRUNK_HASH_KEY_DA))
+    {
+        for (i = 0; i < MAC_LEN; i++)
+        {
+            da_xor ^= (header[i] & BIT2_MASK) ^
+                      ((header[i] >> 2) & BIT2_MASK) ^
+                      ((header[i] >> 4) & BIT2_MASK) ^
+                      ((header[i] >> 6) & BIT2_MASK);
+        }
+        *hash_dp = da_xor;
+    }
+    if ((mode & FAL_TRUNK_HASH_KEY_SA) && (hash_mode & FAL_TRUNK_HASH_KEY_SA))
+    {
+        for (i = 6; i < 2 * MAC_LEN; i++)
+        {
+            sa_xor ^= (header[i] & BIT2_MASK) ^
+                      ((header[i] >> 2) & BIT2_MASK) ^
+                      ((header[i] >> 4) & BIT2_MASK) ^
+                      ((header[i] >> 6) & BIT2_MASK);
+        }
+        *hash_dp = (*hash_dp) ^ sa_xor;
+    }
+
+    /*dp translation*/
+#if 0
+    HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1),
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+#else /*sw*/
+    reg = isis_trunk_regs[ISIS_TRUNK_CTRL_1 + (trunk_id >> 1)];
+#endif
+
+    for (i = 0; i < TRUNK_HASH_DP_SEL; i++)
+    {
+        xor_dp = BYTE_B2R(*hash_dp, i);
+        data1 = (0x0f & (reg >> (((trunk_id % 2) << 4) + (xor_dp << 2))));
+        if (data1 & TRUNK_MEM_EN_MASK)
+        {
+            *hash_dp = data1 & TRUNK_MEM_PT_MASK;
+            *hash_dp = 0x01 << (*hash_dp); /*bmp*/
+            return SW_OK;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isis_trunk_sa_spoofing( a_uint32_t dev_id, a_uint8_t * header, a_uint32_t len,
+                         a_uint8_t expect_dp, a_uint32_t trunk_id, fal_pbmp_t member)
+{
+    sw_error_t rv;
+    a_uint32_t i, hash_mode;
+    a_uint8_t  hash_dp;
+    a_uint8_t  ori_sa[MAC_LEN];
+
+    rv = _isis_trunk_hash_mode_sw_get(dev_id, &hash_mode);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!(hash_mode & FAL_TRUNK_HASH_KEY_SA))
+    {
+        return SW_DISABLE;
+    }
+
+    memcpy(ori_sa, &header[MAC_LEN], MAC_LEN);
+
+    for (i = 0; i < HASH_SIZE/*not HASH_SIZE, for RAD only*/; i++)
+    {
+        memcpy(&header[MAC_LEN], sa_hash[i], MAC_LEN);
+        rv = _isis_trunk_hash_dp_get(dev_id, header, len, trunk_id,
+                                     FAL_TRUNK_HASH_KEY_DA | FAL_TRUNK_HASH_KEY_SA, &hash_dp);
+        SW_RTN_ON_ERROR(rv);
+        if (expect_dp == hash_dp)
+        {
+            // printk("expect_dp = 0x%x, hash_dp(DA+SA) = 0x%x, sa_id = %d\n", expect_dp, hash_dp, i);
+            return SW_OK;
+        }
+    }
+
+    /*should never here*/
+    memcpy(&header[MAC_LEN], ori_sa, MAC_LEN);
+    return SW_FAIL;
+}
+
+static sw_error_t
+_isis_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header,
+                          a_uint32_t len, fal_pbmp_t dp_member)
+{
+    sw_error_t rv;
+    a_uint8_t  expect_dp, hash_dp; /*bitmap*/
+    a_uint32_t i, trunk_id;
+    fal_pbmp_t member;
+
+    if (!ISIS_TRUNK_MANIPULATE_DP_ON)
+    {
+        return SW_OK; /*feature not enabled*/
+    }
+
+    if (!header || len < ISIS_TRUNK_MANIPULATE_HEADER_LEN)
+    {
+        return SW_BAD_VALUE;
+    }
+
+#if 0 /*de-comment this to ignore broadcast packets*/
+    const a_uint8_t  bc_mac[MAC_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+    if (!memcmp(header, bc_mac, MAC_LEN))   /*not for broadcast*/
+    {
+        return SW_OK;
+    }
+#endif
+
+    /*expect_dp within trunk group*/
+    expect_dp = dp_member & 0x7f;
+    for (i = 0; i < 7; i++)
+    {
+        if (expect_dp & (0x01 << i))
+        {
+            rv = _isis_trunk_id_member_get(dev_id, (0x01 << i), &trunk_id, &member);
+            if (rv != SW_OK)
+            {
+                expect_dp &= ~(0x01 << i); /*not the dp doesn't belong to trunk*/
+            }
+        }
+    }
+
+    if (BYTE_B1C(expect_dp) != 1)   /*supports 1 dp only*/
+    {
+        return SW_OK; /*ignore none-dp or multi-dp*/
+    }
+
+    rv = _isis_trunk_id_member_get(dev_id, expect_dp, &trunk_id, &member);
+    SW_RTN_ON_ERROR(rv);
+
+    member &= 0x7f;
+    if (BYTE_B1C(member) == 1)   /*trunk group w/ one port*/
+    {
+        return SW_OK;
+    }
+
+    rv = _isis_trunk_hash_dp_get(dev_id, header, len, trunk_id,
+                                 FAL_TRUNK_HASH_KEY_DA | FAL_TRUNK_HASH_KEY_SA, &hash_dp);
+    SW_RTN_ON_ERROR(rv);
+
+    // printk("expect_dp = 0x%x, hash_dp(DA+SA) = 0x%x, member = 0x%x\n", expect_dp, hash_dp, member);
+    if (expect_dp == hash_dp)
+    {
+        return SW_OK;
+    }
+
+    rv = _isis_trunk_sa_spoofing(dev_id, header, len, expect_dp, trunk_id, member);
+    SW_RTN_ON_ERROR(rv);
+
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set particular trunk group information on particular device.
+ * @param[in] dev_id device id
+ * @param[in] trunk_id trunk group id
+ * @param[in] enable trunk group status, enable or disable
+ * @param[in] member port member information
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+                     a_bool_t enable, fal_pbmp_t member)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_trunk_group_set(dev_id, trunk_id, enable, member);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get particular trunk group information on particular device.
+ * @param[in] dev_id device id
+ * @param[in] trunk_id trunk group id
+ * @param[out] enable trunk group status, enable or disable
+ * @param[out] member port member information
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+                     a_bool_t * enable, fal_pbmp_t * member)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_trunk_group_get(dev_id, trunk_id, enable, member);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set trunk hash mode on particular device.
+ * @details   Comments:
+    hash mode is listed below
+    FAL_TRUNK_HASH_KEY_DA, FAL_TRUNK_HASH_KEY_SA, FAL_TRUNK_HASH_KEY_DIP and FAL_TRUNK_HASH_KEY_SIP
+ * @param[in] dev_id device id
+ * @param[in] hash_mode trunk hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_trunk_hash_mode_set(dev_id, hash_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get trunk hash mode on particular device.
+ * @param[in] dev_id device id
+ * @param[out] hash_mode trunk hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_trunk_hash_mode_get(dev_id, hash_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set trunk manipulate SA on particular device.
+ * @param[in] dev_id device id
+ * @param[in] addr   manipulate SA
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_trunk_manipulate_sa_set(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get trunk manipulate SA on particular device.
+ * @param[in]  dev_id device id
+ * @param[out] addr   manipulate SA
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_trunk_manipulate_sa_get(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#if 0
+/**
+ * @brief manipulate destination port within a trunk group
+ * @details Comments:
+ *  supporting hash mode include: FAL_TRUNK_HASH_KEY_DA & FAL_TRUNK_HASH_KEY_SA;
+ *  FAL_TRUNK_HASH_KEY_DIP & FAL_TRUNK_HASH_KEY_SIP are NOT covered in current design
+ * @param[in]     dev_id    device id
+ * @param[in-out] header    packet header, accept format: [DA:6B][SA:6B]
+ * @param[in]     len       length of packet header, should be 12 in current design (6B DA + 6B SA)
+ * @param[in]     dp_member expect destination port members, bitmap format
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header,
+                         a_uint32_t len, fal_pbmp_t dp_member)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_trunk_manipulate_dp(dev_id, header, len, dp_member);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+sw_error_t
+isis_trunk_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->trunk_group_set = isis_trunk_group_set;
+        p_api->trunk_group_get = isis_trunk_group_get;
+        p_api->trunk_hash_mode_set = isis_trunk_hash_mode_set;
+        p_api->trunk_hash_mode_get = isis_trunk_hash_mode_get;
+        p_api->trunk_manipulate_sa_set = isis_trunk_manipulate_sa_set;
+        p_api->trunk_manipulate_sa_get = isis_trunk_manipulate_sa_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isis/isis_vlan.c b/qca-ssdk/src/hsl/isis/isis_vlan.c
new file mode 100755
index 0000000..248623b
--- /dev/null
+++ b/qca-ssdk/src/hsl/isis/isis_vlan.c
@@ -0,0 +1,909 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isis_vlan ISIS_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_vlan.h"
+#include "isis_reg.h"
+
+#define MAX_VLAN_ID         4095
+
+#define VLAN_FLUSH          1
+#define VLAN_LOAD_ENTRY     2
+#define VLAN_PURGE_ENTRY    3
+#define VLAN_REMOVE_PORT    4
+#define VLAN_NEXT_ENTRY     5
+#define VLAN_FIND_ENTRY     6
+
+static void
+_isis_vlan_hw_to_sw(a_uint32_t reg[], fal_vlan_t * vlan_entry)
+{
+    a_uint32_t i, data, tmp;
+
+    aos_mem_zero(vlan_entry, sizeof (fal_vlan_t));
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VLAN_ID, data, reg[1]);
+    vlan_entry->vid = data & 0xfff;
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]);
+    if (1 == data)
+    {
+        vlan_entry->fid = vlan_entry->vid;
+    }
+    else
+    {
+        vlan_entry->fid = FAL_SVL_FID;
+    }
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]);
+    if (1 == data)
+    {
+        vlan_entry->learn_dis = A_TRUE;
+    }
+    else
+    {
+        vlan_entry->learn_dis = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]);
+    if (1 == data)
+    {
+        vlan_entry->vid_pri_en = A_TRUE;
+
+        SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]);
+        vlan_entry->vid_pri = data & 0xff;
+    }
+    else
+    {
+        vlan_entry->vid_pri_en = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]);
+    for (i = 0; i < 7; i++)
+    {
+        tmp = (data >> (i << 1)) & 0x3UL;
+        if (0 == tmp)
+        {
+            vlan_entry->mem_ports |= (0x1UL << i);
+            vlan_entry->unmodify_ports |= (0x1UL << i);
+        }
+        else if (1 == tmp)
+        {
+            vlan_entry->mem_ports |= (0x1UL << i);
+            vlan_entry->untagged_ports |= (0x1UL << i);
+        }
+        else if (2 == tmp)
+        {
+            vlan_entry->mem_ports |= (0x1UL << i);
+            vlan_entry->tagged_ports |= (0x1UL << i);
+        }
+    }
+
+    return;
+}
+
+static sw_error_t
+_isis_vlan_sw_to_hw(a_uint32_t dev_id, const fal_vlan_t * vlan_entry,
+                    a_uint32_t reg[])
+{
+    a_uint32_t i, tag, untag, unmodify, member = 0;
+
+    if (vlan_entry->vid > MAX_VLAN_ID)
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    if (A_FALSE ==
+            hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]);
+
+    if (FAL_SVL_FID == vlan_entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]);
+    }
+    else if (vlan_entry->vid == vlan_entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]);
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (A_TRUE == vlan_entry->learn_dis)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]);
+    }
+
+    for (i = 0; i < 7; i++)
+    {
+        if ((vlan_entry->mem_ports >> i) & 0x1UL)
+        {
+            tag = (vlan_entry->tagged_ports >> i) & 0x1UL;
+            untag = (vlan_entry->untagged_ports >> i) & 0x1UL;
+            unmodify = (vlan_entry->unmodify_ports >> i) & 0x1UL;
+
+            if ((0 == (tag + untag + unmodify))
+                    || (1 < (tag + untag + unmodify)))
+            {
+                return SW_BAD_VALUE;
+            }
+
+            if (tag)
+            {
+                member |= (2 << (i << 1));
+            }
+            else if (untag)
+            {
+                member |= (1 << (i << 1));
+            }
+        }
+        else
+        {
+            member |= (3 << (i << 1));
+        }
+    }
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, member, reg[0]);
+
+    if (A_TRUE == vlan_entry->vid_pri_en)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]);
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri,
+                            reg[0]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]);
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_entry->vid, reg[1]);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_vlan_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_vlan_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isis_vlan_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val;
+    sw_error_t rv;
+
+    while (vt_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY,
+                          (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+    {
+        printk("%s BUSY\n", __FUNCTION__);
+        return SW_BUSY;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_FUNC, op, val);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_BUSY, 1, val);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    vt_busy = 1;
+    i = 0x1000;
+    while (vt_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY,
+                          (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_FAIL;
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_FULL_VIO,
+                      (a_uint8_t *) (&vt_full), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (vt_full)
+    {
+        val = 0x10;
+        HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        if (VLAN_LOAD_ENTRY == op)
+        {
+            return SW_FULL;
+        }
+        else if (VLAN_PURGE_ENTRY == op)
+        {
+            return SW_NOT_FOUND;
+        }
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_VALID,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (!val)
+    {
+        if (VLAN_FIND_ENTRY == op)
+            return SW_NOT_FOUND;
+
+        if (VLAN_NEXT_ENTRY == op)
+            return SW_NO_MORE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_vlan_hwentry_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+
+    if (vlan_id > MAX_VLAN_ID)
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_vlan_up_to_sw(dev_id, reg);
+    return rv;
+}
+
+static sw_error_t
+_isis_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_vlan_sw_to_hw(dev_id, vlan_entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_vlan_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_isis_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (vlan_id > MAX_VLAN_ID)
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, 0x3fff, reg[0]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]);
+
+    rv = _isis_vlan_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_isis_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == vlan_id)
+    {
+        rv = _isis_vlan_hwentry_get(dev_id, 0, reg);
+
+        if (SW_OK == rv)
+        {
+            _isis_vlan_hw_to_sw(reg, p_vlan);
+            return SW_OK;
+        }
+        else
+        {
+            vlan_id = 0;
+        }
+    }
+
+    if (vlan_id > MAX_VLAN_ID)
+        return SW_OUT_OF_RANGE;
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_vlan_commit(dev_id, VLAN_NEXT_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_vlan_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    _isis_vlan_hw_to_sw(reg, p_vlan);
+
+    if (0 == p_vlan->vid)
+    {
+        return SW_NO_MORE;
+    }
+    else
+    {
+        return SW_OK;
+    }
+}
+
+static sw_error_t
+_isis_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    _isis_vlan_hw_to_sw(reg, p_vlan);
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (vlan_id > MAX_VLAN_ID)
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    reg = (a_int32_t) vlan_id;
+    HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VLAN_ID,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_vlan_commit(dev_id, VLAN_PURGE_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_isis_vlan_flush(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_vlan_commit(dev_id, VLAN_FLUSH);
+    return rv;
+}
+
+static sw_error_t
+_isis_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((MAX_VLAN_ID < fid) && (FAL_SVL_FID != fid))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((MAX_VLAN_ID >= fid) && (vlan_id != fid))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_SVL_FID == fid)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]);
+    }
+
+    rv = _isis_vlan_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    if (SW_FULL == rv)
+    {
+        rv = SW_OK;
+    }
+    return rv;
+}
+
+static sw_error_t
+_isis_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]);
+    if (data)
+    {
+        *fid = vlan_id;
+    }
+    else
+    {
+        *fid = FAL_SVL_FID;
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+_isis_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                         fal_port_t port_id, a_uint32_t port_info)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]);
+    data &= (~(0x3 << (port_id << 1)));
+    data |= ((port_info & 0x3) << (port_id << 1));
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]);
+
+    rv = _isis_vlan_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    if (SW_FULL == rv)
+    {
+        rv = SW_OK;
+    }
+    return rv;
+}
+
+static sw_error_t
+_isis_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+                      fal_port_t port_id, fal_pt_1q_egmode_t port_info)
+{
+    sw_error_t rv;
+    a_uint32_t info = 0;
+
+    if (FAL_EG_UNMODIFIED == port_info)
+    {
+        info = 0;
+    }
+    else if (FAL_EG_TAGGED == port_info)
+    {
+        info = 0x2;
+    }
+    else if (FAL_EG_UNTAGGED == port_info)
+    {
+        info = 0x1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isis_vlan_member_update(dev_id, vlan_id, port_id, info);
+    return rv;
+}
+
+static sw_error_t
+_isis_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t info = 0x3;
+
+    rv = _isis_vlan_member_update(dev_id, vlan_id, port_id, info);
+    return rv;
+}
+
+static sw_error_t
+_isis_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isis_vlan_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isis_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    if (SW_FULL == rv)
+    {
+        rv = SW_OK;
+    }
+    return rv;
+}
+
+static sw_error_t
+_isis_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]);
+    if (data)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+    return SW_OK;
+}
+
+/**
+ * @brief Append a vlan entry on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_entry vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_vlan_entry_append(dev_id, vlan_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Creat a vlan entry through vlan id on a paticular device.
+ *   @details   Comments:
+ *    After this operation the member ports of the created vlan entry are null.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_vlan_create(dev_id, vlan_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next a vlan entry through vlan id on a paticular device.
+ *   @details   Comments:
+ *    If the value of vid is zero this operation will get the first entry.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_vlan_next(dev_id, vlan_id, p_vlan);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a vlan entry through vlan id on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_vlan_find(dev_id, vlan_id, p_vlan);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a vlan entry through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_vlan_delete(dev_id, vlan_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Flush all vlan entries on a paticular device.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_flush(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_vlan_flush(dev_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] fid FDB id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_vlan_fid_set(dev_id, vlan_id, fid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] fid FDB id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_vlan_fid_get(dev_id, vlan_id, fid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a port member to a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @param[in] port_info port tag information
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+                     fal_port_t port_id, fal_pt_1q_egmode_t port_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_vlan_member_add(dev_id, vlan_id, port_id, port_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Del a port member from a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_vlan_member_del(dev_id, vlan_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_vlan_learning_state_set(dev_id, vlan_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isis_vlan_learning_state_get(dev_id, vlan_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isis_vlan_init(a_uint32_t dev_id)
+{
+    hsl_api_t *p_api;
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->vlan_entry_append = isis_vlan_entry_append;
+    p_api->vlan_creat = isis_vlan_create;
+    p_api->vlan_delete = isis_vlan_delete;
+    p_api->vlan_next = isis_vlan_next;
+    p_api->vlan_find = isis_vlan_find;
+    p_api->vlan_flush = isis_vlan_flush;
+    p_api->vlan_fid_set = isis_vlan_fid_set;
+    p_api->vlan_fid_get = isis_vlan_fid_get;
+    p_api->vlan_member_add = isis_vlan_member_add;
+    p_api->vlan_member_del = isis_vlan_member_del;
+    p_api->vlan_learning_state_set = isis_vlan_learning_state_set;
+    p_api->vlan_learning_state_get = isis_vlan_learning_state_get;
+
+
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/Makefile b/qca-ssdk/src/hsl/isisc/Makefile
new file mode 100755
index 0000000..4990ff0
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/Makefile
@@ -0,0 +1,122 @@
+LOC_DIR=src/hsl/isisc
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=isisc_reg_access.c isisc_init.c
+
+ifeq (TRUE, $(IN_ACL))
+  SRC_LIST += isisc_acl.c isisc_acl_parse.c
+endif
+
+ifeq (TRUE, $(IN_FDB))
+  SRC_LIST += isisc_fdb.c
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+  SRC_LIST += isisc_igmp.c
+	ifeq (TRUE, $(IN_ACL))
+		SRC_LIST += isisc_multicast_acl.c
+	endif
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+  SRC_LIST += isisc_leaky.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+  SRC_LIST += isisc_led.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+  SRC_LIST += isisc_mib.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+  SRC_LIST += isisc_mirror.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+  SRC_LIST += isisc_misc.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+  SRC_LIST += isisc_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+  SRC_LIST += isisc_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+  SRC_LIST += isisc_qos.c
+endif
+
+ifeq (TRUE, $(IN_RATE))
+  SRC_LIST += isisc_rate.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+  SRC_LIST += isisc_stp.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+  SRC_LIST += isisc_vlan.c
+endif
+
+ifeq (TRUE, $(IN_REDUCED_ACL))
+  SRC_LIST += isisc_reduced_acl.c
+endif
+
+ifeq (TRUE, $(IN_COSMAP))
+  SRC_LIST += isisc_cosmap.c
+endif
+
+ifeq (TRUE, $(IN_IP))
+  SRC_LIST += isisc_ip.c
+endif
+
+ifeq (TRUE, $(IN_NAT))
+  SRC_LIST += isisc_nat.c
+endif
+
+ifeq (TRUE, $(IN_NAT_HELPER))
+  SRC_LIST += nat_helper_dt.c
+  SRC_LIST += nat_helper_hsl.c
+  SRC_LIST += nat_ipt_helper.c
+  SRC_LIST += napt_helper.c
+  SRC_LIST += host_helper.c
+  SRC_LIST += nat_helper.c
+  SRC_LIST += napt_acl.c
+  SRC_LIST += napt_procfs.c
+endif
+
+ifeq (TRUE, $(IN_TRUNK))
+  SRC_LIST += isisc_trunk.c
+endif
+
+ifeq (TRUE, $(IN_SEC))
+  SRC_LIST += isisc_sec.c
+endif
+
+ifeq (TRUE, $(IN_INTERFACECONTROL))
+  SRC_LIST += isisc_interface_ctrl.c
+endif
+
+ifeq (linux, $(OS))
+	ifeq (KSLIB, $(MODULE_TYPE))
+    ifneq (TRUE, $(KERNEL_MODE))
+      SRC_LIST=isisc_reg_access.c isisc_init.c
+	  endif
+	endif
+endif
+
+ifeq (, $(findstring ISISC, $(SUPPORT_CHIP)))
+  SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/hsl/isisc/isisc_acl.c b/qca-ssdk/src/hsl/isisc/isisc_acl.c
new file mode 100755
index 0000000..a446a2d
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_acl.c
@@ -0,0 +1,2035 @@
+/*
+ * Copyright (c) 2012, 2016, 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_acl ISISC_ACL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+#include "isisc_acl.h"
+#include "isisc_reg.h"
+#include "isisc_acl_prv.h"
+
+//#define ISISC_ACL_DEBUG
+//#define ISISC_SW_ENTRY
+#define ISISC_HW_ENTRY
+
+static isisc_acl_list_t *sw_list_ent[SW_MAX_NR_DEV];
+static isisc_acl_rule_t *sw_rule_ent[SW_MAX_NR_DEV];
+
+static isisc_acl_rule_t *sw_rule_tmp[SW_MAX_NR_DEV];
+static isisc_acl_rule_t *hw_rule_tmp[SW_MAX_NR_DEV];
+#ifdef ISISC_SW_ENTRY
+static a_uint8_t *sw_filter_mem = NULL;
+#endif
+
+static sw_error_t
+_isisc_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag);
+
+static sw_error_t
+_isisc_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx,
+                        a_uint32_t ports);
+
+#ifdef ISISC_SW_ENTRY
+static sw_error_t
+_isisc_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+                   a_uint32_t op);
+
+static sw_error_t
+_isisc_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+                  a_uint32_t op);
+#endif
+
+static sw_error_t
+_isisc_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter,
+                        a_uint32_t flt_idx);
+
+static sw_error_t
+_isisc_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter,
+                      a_uint32_t flt_idx);
+
+static sw_error_t
+_isisc_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+                                  a_uint32_t rule_id, a_bool_t enable);
+
+static void
+_isisc_acl_list_dump(a_uint32_t dev_id)
+{
+    a_uint32_t i;
+    isisc_acl_list_t *sw_list;
+
+    aos_printk("\ndev_id=%d  list control infomation:", dev_id);
+    for (i = 0; i < ISISC_MAX_FILTER; i++)
+    {
+        sw_list = &(sw_list_ent[dev_id][i]);
+        if (ENT_USED & sw_list->status)
+        {
+            aos_printk
+            ("\nlist_id=%02d  list_pri=%02d  rule_nr=%02d  [pts_map]:0x%02x  idx=%02d ",
+             sw_list->list_id, sw_list->list_pri, sw_list->rule_nr,
+             sw_list->bind_pts, i);
+        }
+    }
+    aos_printk("\n");
+}
+
+static void
+_isisc_acl_sw_rule_dump(char *info, isisc_acl_rule_t * sw_rule)
+{
+#ifdef ISISC_ACL_DEBUG
+    a_uint32_t flt_idx, i;
+
+    aos_printk("\n%s", info);
+    for (flt_idx = 0; flt_idx < ISISC_MAX_FILTER; flt_idx++)
+    {
+        aos_printk("\n%d software filter:", flt_idx);
+        aos_printk("\nact:");
+        for (i = 0; i < 3; i++)
+        {
+            aos_printk("%08x  ", sw_rule[flt_idx].filter.act[i]);
+        }
+
+        aos_printk("\nvlu:");
+        for (i = 0; i < 5; i++)
+        {
+            aos_printk("%08x  ", sw_rule[flt_idx].filter.vlu[i]);
+        }
+
+        aos_printk("\nmsk:");
+        for (i = 0; i < 5; i++)
+        {
+            aos_printk("%08x  ", sw_rule[flt_idx].filter.msk[i]);
+        }
+
+        aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d]",
+                   sw_rule[flt_idx].status,
+                   sw_rule[flt_idx].list_id, sw_rule[flt_idx].rule_id);
+
+        aos_printk("\n\n");
+    }
+#else
+    return;
+#endif
+}
+
+static isisc_acl_list_t *
+_isisc_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < ISISC_MAX_FILTER; i++)
+    {
+        if ((ENT_USED & sw_list_ent[dev_id][i].status)
+                && (list_id == sw_list_ent[dev_id][i].list_id))
+        {
+            return &(sw_list_ent[dev_id][i]);
+        }
+    }
+    return NULL;
+}
+
+static sw_error_t
+_isisc_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag)
+{
+#ifdef ISISC_SW_ENTRY
+    hw_filter_t filter;
+
+    _isisc_filter_up_to_sw(dev_id, &filter, flt_idx);
+
+    filter.msk[4] &= 0xfffffff8;
+    filter.msk[4] |= (flag & 0x7);
+
+    _isisc_filter_down_to_hw(dev_id, &filter, flt_idx);
+
+    return SW_OK;
+#else
+#ifdef ISISC_HW_ENTRY
+    hw_filter_t filter;
+
+    filter = sw_rule_ent[dev_id][flt_idx].filter;
+
+    filter.msk[4] &= 0xfffffff8;
+    filter.msk[4] |= (flag & 0x7);
+
+    _isisc_filter_down_to_hw(dev_id, &filter, flt_idx);
+    return SW_OK;
+#else
+    sw_error_t rv;
+    a_uint32_t addr, data = 0;
+
+    /* read filter mask at first */
+    addr = ISISC_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 10) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* get filter mask and modify it */
+    addr = ISISC_RULE_FUNC_ADDR + 20;
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= 0xfffffff8;
+    data |= (flag & 0x7);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* write back filter mask */
+    addr = ISISC_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+#endif
+#endif
+}
+
+static sw_error_t
+_isisc_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t ports)
+{
+#ifdef ISISC_SW_ENTRY
+    hw_filter_t filter;
+
+    _isisc_filter_up_to_sw(dev_id, &filter, flt_idx);
+
+    filter.vlu[4] &= 0xffffff80;
+    filter.vlu[4] |= (ports & 0x7f);
+
+    _isisc_filter_down_to_hw(dev_id, &filter, flt_idx);
+
+    return SW_OK;
+#else
+#ifdef ISISC_HW_ENTRY
+    hw_filter_t filter;
+
+    filter = sw_rule_ent[dev_id][flt_idx].filter;
+
+    filter.vlu[4] &= 0xffffff80;
+    filter.vlu[4] |= (ports & 0x7f);
+
+    _isisc_filter_down_to_hw(dev_id, &filter, flt_idx);
+
+    return SW_OK;
+#else
+    sw_error_t rv;
+    a_uint32_t addr, data;
+
+    /* read filter value at first */
+    addr = ISISC_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (0x1 << 10) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* get filter value and modify it */
+    addr = ISISC_RULE_FUNC_ADDR + 20;
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= 0xffffff80;
+    data |= (ports & 0x7f);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* write back filter value */
+    addr = ISISC_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+#endif
+#endif
+}
+
+#ifdef ISISC_SW_ENTRY
+static sw_error_t
+_isisc_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+                   a_uint32_t op)
+{
+    a_uint32_t i, addr, data, idx = 6;
+    sw_error_t rv;
+
+    if (ISISC_FILTER_ACT_OP == op)
+    {
+        idx = 4;
+    }
+
+    for (i = 1; i < idx; i++)
+    {
+        addr = ISISC_RULE_FUNC_ADDR + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(reg[i - 1])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    addr = ISISC_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+                  a_uint32_t op)
+{
+    a_uint32_t i, addr, data, idx = 6;
+    sw_error_t rv;
+
+    addr = ISISC_RULE_FUNC_ADDR;
+    data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 10) | (0x1 << 31);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (ISISC_FILTER_ACT_OP == op)
+    {
+        idx = 4;
+    }
+
+    for (i = 1; i < idx; i++)
+    {
+        addr = ISISC_RULE_FUNC_ADDR + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(reg[i - 1])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isisc_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter,
+                        a_uint32_t flt_idx)
+{
+#ifdef ISISC_SW_ENTRY
+    a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx;
+
+    aos_mem_copy(tbl, filter, sizeof (hw_filter_t));
+#else
+#ifdef ISISC_HW_ENTRY
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    base = ISISC_FILTER_ACT_ADDR + (flt_idx << 4);
+    for (i = 0; i < 3; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->act[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    base = ISISC_FILTER_VLU_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->vlu[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    base = ISISC_FILTER_MSK_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->msk[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+#else
+    sw_error_t rv;
+
+    rv = _isisc_filter_write(dev_id, &(filter->act[0]), flt_idx,
+                            ISISC_FILTER_ACT_OP);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_filter_write(dev_id, &(filter->vlu[0]), flt_idx,
+                            ISISC_FILTER_VLU_OP);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_filter_write(dev_id, &(filter->msk[0]), flt_idx,
+                            ISISC_FILTER_MSK_OP);
+    SW_RTN_ON_ERROR(rv);
+#endif
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter,
+                      a_uint32_t flt_idx)
+{
+#ifdef ISISC_SW_ENTRY
+    a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx;
+
+    aos_mem_copy(filter, tbl, sizeof (hw_filter_t));
+#else
+#ifdef ISISC_HW_ENTRY
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    base = ISISC_FILTER_VLU_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->vlu[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    base = ISISC_FILTER_MSK_ADDR + (flt_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->msk[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    base = ISISC_FILTER_ACT_ADDR + (flt_idx << 4);
+    for (i = 0; i < 3; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(filter->act[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+#else
+    sw_error_t rv;
+
+    rv = _isisc_filter_read(dev_id, &(filter->vlu[0]), flt_idx,
+                           ISISC_FILTER_VLU_OP);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_filter_read(dev_id, &(filter->msk[0]), flt_idx,
+                           ISISC_FILTER_MSK_OP);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_filter_read(dev_id, &(filter->act[0]), flt_idx,
+                           ISISC_FILTER_ACT_OP);
+    SW_RTN_ON_ERROR(rv);
+#endif
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_list_insert(a_uint32_t dev_id, a_uint32_t * src_idx,
+                      a_uint32_t * dst_idx, isisc_acl_rule_t * src_rule,
+                      isisc_acl_rule_t * dst_rule)
+{
+    a_uint32_t i, data, rule_id, list_id, list_pri;
+
+    rule_id = 0;
+    list_id = src_rule[*src_idx].list_id;
+    list_pri = src_rule[*src_idx].list_pri;
+
+    for (i = *src_idx; i < ISISC_MAX_FILTER; i++)
+    {
+        if (!(ENT_USED & src_rule[i].status))
+        {
+            continue; // was: break;
+        }
+
+        if (src_rule[i].list_id != list_id)
+        {
+            break;
+        }
+
+        SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data,
+                            src_rule[i].filter.msk[4]);
+        if (!data)
+        {
+            continue;
+        }
+
+        if (ISISC_MAX_FILTER <= *dst_idx)
+        {
+            return SW_NO_RESOURCE;
+        }
+
+        if (ENT_USED & dst_rule[*dst_idx].status)
+        {
+            return SW_NO_RESOURCE;
+        }
+
+        SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_VALID, data,
+                            src_rule[i].filter.msk[4]);
+        if ((FLT_START == data) && (*dst_idx % 2))
+        {
+            if (*src_idx != i)
+            {
+                dst_rule[*dst_idx].src_flt_dis = src_rule[i].src_flt_dis;
+                dst_rule[*dst_idx].list_id = list_id;
+                dst_rule[*dst_idx].list_pri = list_pri;
+                dst_rule[*dst_idx].rule_id = rule_id - 1;
+                dst_rule[*dst_idx].status |= ENT_USED;
+            }
+
+            (*dst_idx)++;
+            if (ISISC_MAX_FILTER <= *dst_idx)
+            {
+                return SW_NO_RESOURCE;
+            }
+
+            if (ENT_USED & dst_rule[*dst_idx].status)
+            {
+                return SW_NO_RESOURCE;
+            }
+        }
+
+        aos_mem_copy(&(dst_rule[*dst_idx].filter), &(src_rule[i].filter),
+                     sizeof (hw_filter_t));
+        dst_rule[*dst_idx].src_flt_dis = src_rule[i].src_flt_dis;
+        dst_rule[*dst_idx].list_id = list_id;
+        dst_rule[*dst_idx].list_pri = list_pri;
+        dst_rule[*dst_idx].rule_id = rule_id;
+        dst_rule[*dst_idx].status |= ENT_USED;
+        if (ENT_DEACTIVE & src_rule[i].status)
+        {
+            dst_rule[*dst_idx].status |= ENT_DEACTIVE;
+        }
+        (*dst_idx)++;
+
+        if ((FLT_END == data) && (*dst_idx % 2))
+        {
+            if (ISISC_MAX_FILTER > *dst_idx)
+            {
+                dst_rule[*dst_idx].src_flt_dis = src_rule[i].src_flt_dis;
+                dst_rule[*dst_idx].list_id = list_id;
+                dst_rule[*dst_idx].list_pri = list_pri;
+                dst_rule[*dst_idx].rule_id = rule_id;
+                dst_rule[*dst_idx].status |= ENT_USED;
+                (*dst_idx)++;
+            }
+        }
+
+        if ((FLT_END == data) || (FLT_STARTEND == data))
+        {
+            rule_id++;
+        }
+    }
+
+    *src_idx = i;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_alloc(a_uint32_t dev_id, isisc_acl_list_t * sw_list,
+                     a_uint32_t filter_nr)
+{
+    a_uint32_t free_flt_nr, load_idx, begin_idx, start_idx, end_idx, i;
+    a_uint32_t largest_nr, largest_idx;
+    sw_error_t rv;
+
+    /* calculate the proper location, [start_idx, end_idx) */
+    start_idx = 0;
+    end_idx = ISISC_MAX_FILTER;
+    for (i = 0; i < ISISC_MAX_FILTER; i++)
+    {
+        if (ENT_USED & sw_rule_ent[dev_id][i].status)
+        {
+            if (sw_rule_ent[dev_id][i].list_pri < sw_list->list_pri)
+            {
+                start_idx = i + 1;
+            }
+            else if (sw_rule_ent[dev_id][i].list_pri > sw_list->list_pri)
+            {
+                end_idx = i;
+                break;
+            }
+        }
+    }
+
+    /* find the larget free filters block */
+    largest_nr = 0;
+    largest_idx = 0;
+    free_flt_nr = 0;
+    begin_idx = start_idx;
+    for (i = start_idx; i < end_idx; i++)
+    {
+        if (!(ENT_USED & sw_rule_ent[dev_id][i].status))
+        {
+            free_flt_nr++;
+        }
+        else
+        {
+            if (free_flt_nr > largest_nr)
+            {
+                largest_nr = free_flt_nr;
+                largest_idx = begin_idx;
+            }
+            free_flt_nr = 0;
+            begin_idx = i + 1;
+        }
+    }
+
+    if (free_flt_nr > largest_nr)
+    {
+        largest_nr = free_flt_nr;
+        largest_idx = begin_idx;
+    }
+
+    if ((!largest_nr) || ((largest_nr + 1) < filter_nr))
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    for (i = 0; i < ISISC_MAX_FILTER; i++)
+    {
+        if (ENT_USED & sw_rule_ent[dev_id][i].status)
+        {
+            aos_mem_copy(&(sw_rule_tmp[dev_id][i]), &(sw_rule_ent[dev_id][i]),
+                         sizeof (isisc_acl_rule_t));
+        }
+    }
+
+    begin_idx = 0;
+    load_idx = largest_idx;
+    rv = _isisc_acl_list_insert(dev_id, &begin_idx, &load_idx,
+                               hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]);
+    return rv;
+}
+
+static sw_error_t
+_isisc_acl_rule_reorder(a_uint32_t dev_id, isisc_acl_list_t * sw_list)
+{
+    a_uint32_t i, src_idx, dst_idx;
+    sw_error_t rv;
+
+    dst_idx = 0;
+    for (i = 0; i < ISISC_MAX_FILTER;)
+    {
+        if (ENT_USED & sw_rule_ent[dev_id][i].status)
+        {
+            if (sw_rule_ent[dev_id][i].list_pri <= sw_list->list_pri)
+            {
+                rv = _isisc_acl_list_insert(dev_id, &i, &dst_idx,
+                                           sw_rule_ent[dev_id],
+                                           sw_rule_tmp[dev_id]);
+                SW_RTN_ON_ERROR(rv);
+            }
+            else
+            {
+                break;
+            }
+        }
+        else
+        {
+            i++;
+        }
+    }
+
+    src_idx = 0;
+    rv = _isisc_acl_list_insert(dev_id, &src_idx, &dst_idx, hw_rule_tmp[dev_id],
+                               sw_rule_tmp[dev_id]);
+    SW_RTN_ON_ERROR(rv);
+
+    for (; i < ISISC_MAX_FILTER;)
+    {
+        if (ENT_USED & sw_rule_ent[dev_id][i].status)
+        {
+            rv = _isisc_acl_list_insert(dev_id, &i, &dst_idx,
+                                       sw_rule_ent[dev_id],
+                                       sw_rule_tmp[dev_id]);
+            SW_RTN_ON_ERROR(rv);
+        }
+        else
+        {
+            i++;
+        }
+    }
+
+    return SW_OK;
+}
+
+static void
+_isisc_acl_rule_sync(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flt_nr)
+{
+    a_uint32_t i, data;
+
+    for (i = flt_idx; i < (flt_idx + flt_nr); i++)
+    {
+        if (aos_mem_cmp
+                (&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]),
+                 sizeof (isisc_acl_rule_t)))
+        {
+            SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data,
+                                sw_rule_tmp[dev_id][i].filter.msk[4]);
+            if (data)
+            {
+                _isisc_filter_down_to_hw(dev_id,
+                                        &(sw_rule_tmp[dev_id][i].filter), i);
+            }
+            else
+            {
+                _isisc_filter_valid_set(dev_id, i, 0);
+            }
+
+            aos_mem_copy(&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]),
+                         sizeof (isisc_acl_rule_t));
+            _isisc_acl_rule_src_filter_sts_set(dev_id, i,
+                                              !sw_rule_tmp[dev_id][i].src_flt_dis);
+        }
+    }
+}
+
+static sw_error_t
+_isisc_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri)
+{
+    a_uint32_t i, loc = ISISC_MAX_FILTER;
+    isisc_acl_list_t *sw_list;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((ISISC_MAX_LIST_ID < list_id) || (ISISC_MAX_LIST_PRI < list_pri))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    for (i = 0; i < ISISC_MAX_FILTER; i++)
+    {
+        sw_list = &(sw_list_ent[dev_id][i]);
+        if (ENT_USED & sw_list->status)
+        {
+            if (list_id == sw_list->list_id)
+            {
+                return SW_ALREADY_EXIST;
+            }
+        }
+        else
+        {
+            loc = i;
+        }
+    }
+
+    if (ISISC_MAX_FILTER == loc)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    sw_list = &(sw_list_ent[dev_id][loc]);
+    aos_mem_zero(sw_list, sizeof (isisc_acl_list_t));
+    sw_list->list_id = list_id;
+    sw_list->list_pri = list_pri;
+    sw_list->status |= ENT_USED;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    isisc_acl_list_t *sw_list;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISISC_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    sw_list = _isisc_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (0 != sw_list->bind_pts)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (0 != sw_list->rule_nr)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    aos_mem_zero(sw_list, sizeof (isisc_acl_list_t));
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+                   a_uint32_t rule_id, a_uint32_t rule_nr,
+                   fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+    isisc_acl_list_t *sw_list;
+    isisc_acl_rule_t *sw_rule;
+    a_uint32_t i, free_flt_nr, old_flt_nr, old_flt_idx, new_flt_nr, bind_pts;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISISC_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if ((0 == rule_nr) || (NULL == rule))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    sw_list = _isisc_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (rule_id != sw_list->rule_nr)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    old_flt_idx = 0;
+    old_flt_nr = 0;
+    free_flt_nr = 0;
+    aos_mem_zero(hw_rule_tmp[dev_id],
+                 ISISC_HW_RULE_TMP_CNT * sizeof (isisc_acl_rule_t));
+    aos_mem_zero(sw_rule_tmp[dev_id],
+                 ISISC_MAX_FILTER * sizeof (isisc_acl_rule_t));
+    for (i = 0; i < ISISC_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i]);
+        if (ENT_USED & sw_rule->status)
+        {
+            if (sw_rule->list_id == sw_list->list_id)
+            {
+                aos_mem_copy(&(hw_rule_tmp[dev_id][old_flt_nr]), sw_rule,
+                             sizeof (isisc_acl_rule_t));
+                if (!old_flt_nr)
+                {
+                    old_flt_idx = i;
+                }
+                old_flt_nr++;
+            }
+        }
+        else
+        {
+            free_flt_nr++;
+        }
+    }
+
+    if (!free_flt_nr)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    /* parse rule entry and alloc rule resource */
+    new_flt_nr = old_flt_nr;
+    for (i = 0; i < rule_nr; i++)
+    {
+        rv = _isisc_acl_rule_sw_to_hw(dev_id, &rule[i], hw_rule_tmp[dev_id],
+                                     &new_flt_nr);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    if (free_flt_nr < (new_flt_nr - old_flt_nr))
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    for (i = old_flt_nr; i < new_flt_nr; i++)
+    {
+        hw_rule_tmp[dev_id][i].status |= ENT_USED;
+        hw_rule_tmp[dev_id][i].list_id = sw_list->list_id;
+        hw_rule_tmp[dev_id][i].list_pri = sw_list->list_pri;
+        bind_pts = sw_list->bind_pts;
+        SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, bind_pts,
+                            (hw_rule_tmp[dev_id][i].filter.vlu[4]));
+    }
+
+    for (i = 0; i < old_flt_nr; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][old_flt_idx + i]);
+        sw_rule->status &= (~ENT_USED);
+        sw_rule->status |= (ENT_TMP);
+    }
+
+    rv = _isisc_acl_rule_alloc(dev_id, sw_list, new_flt_nr);
+    if (SW_OK != rv)
+    {
+        aos_mem_zero(sw_rule_tmp[dev_id],
+                     ISISC_MAX_FILTER * sizeof (isisc_acl_rule_t));
+        rv = _isisc_acl_rule_reorder(dev_id, sw_list);
+    }
+
+    for (i = 0; i < old_flt_nr; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i + old_flt_idx]);
+        sw_rule->status |= (ENT_USED);
+        sw_rule->status &= (~ENT_TMP);
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    _isisc_acl_rule_sync(dev_id, 0, ISISC_MAX_FILTER);
+    sw_list->rule_nr += rule_nr;
+
+    _isisc_acl_sw_rule_dump("sw rule after add", sw_rule_ent[dev_id]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+                      a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    isisc_acl_rule_t *sw_rule;
+    isisc_acl_list_t *sw_list;
+    a_uint32_t i, flt_idx = 0, src_idx, dst_idx, del_nr = 0, flt_nr = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISISC_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    sw_list = _isisc_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (sw_list->rule_nr < (rule_id + rule_nr))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(hw_rule_tmp[dev_id],
+                 ISISC_HW_RULE_TMP_CNT * sizeof (isisc_acl_rule_t));
+    aos_mem_zero(sw_rule_tmp[dev_id],
+                 ISISC_MAX_FILTER * sizeof (isisc_acl_rule_t));
+
+    for (i = 0; i < ISISC_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i]);
+        if ((ENT_USED & sw_rule->status) && (sw_rule->list_id == list_id))
+        {
+            if (!flt_nr)
+            {
+                flt_idx = i;
+            }
+
+            if ((sw_rule->rule_id >= rule_id)
+                    && (sw_rule->rule_id < (rule_id + rule_nr)))
+            {
+                del_nr++;
+            }
+            else
+            {
+                aos_mem_copy(&(hw_rule_tmp[dev_id][flt_idx + flt_nr]), sw_rule,
+                             sizeof (isisc_acl_rule_t));
+            }
+            flt_nr++;
+        }
+    }
+
+    if (!del_nr)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    _isisc_acl_sw_rule_dump("hw rule before del", hw_rule_tmp[dev_id]);
+
+    for (i = 0; i < flt_nr; i++)
+    {
+        sw_rule = &(hw_rule_tmp[dev_id][flt_idx + i]);
+        if (ENT_USED & sw_rule->status)
+        {
+            break;
+        }
+    }
+
+    if (i != flt_nr)
+    {
+        src_idx = flt_idx + i;
+        dst_idx = flt_idx;
+        rv = _isisc_acl_list_insert(dev_id, &src_idx, &dst_idx,
+                                   hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    _isisc_acl_rule_sync(dev_id, flt_idx, flt_nr);
+    sw_list->rule_nr -= rule_nr;
+
+    _isisc_acl_sw_rule_dump("sw rule after del", sw_rule_ent[dev_id]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+                     a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+    isisc_acl_rule_t *sw_rule;
+    a_uint32_t flt_nr = 0, i;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISISC_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    aos_mem_zero(hw_rule_tmp[dev_id],
+                 ISISC_HW_RULE_TMP_CNT * sizeof (isisc_acl_rule_t));
+    for (i = 0; i < ISISC_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i]);
+        if (ENT_USED & sw_rule->status)
+        {
+            if ((sw_rule->list_id == list_id) && (sw_rule->rule_id == rule_id))
+            {
+                aos_mem_copy(&(hw_rule_tmp[dev_id][flt_nr]), sw_rule,
+                             sizeof (isisc_acl_rule_t));
+                flt_nr++;
+            }
+        }
+    }
+
+    if (!flt_nr)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    aos_mem_zero(rule, sizeof (fal_acl_rule_t));
+    rv = _isisc_acl_rule_hw_to_sw(dev_id, rule, hw_rule_tmp[dev_id], 0, flt_nr);
+    return rv;
+}
+
+static sw_error_t
+_isisc_acl_rule_bind(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t ports)
+{
+    sw_error_t rv;
+    a_uint32_t i;
+    isisc_acl_rule_t *sw_rule;
+
+    for (i = 0; i < ISISC_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i]);
+
+        if ((ENT_USED & sw_rule->status)
+                && (list_id == sw_rule->list_id)
+                && (!(ENT_DEACTIVE & sw_rule->status)))
+        {
+            rv = _isisc_filter_ports_bind(dev_id, i, ports);
+            SW_RTN_ON_ERROR(rv);
+
+            SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports,
+                                (sw_rule->filter.vlu[4]));
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                    fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                    a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+    a_uint32_t ports;
+    isisc_acl_list_t *sw_list;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISISC_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACL_DIREC_IN != direc)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    sw_list = _isisc_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (FAL_ACL_BIND_PORT == obj_t)
+    {
+        ports = (sw_list->bind_pts) | (0x1 << obj_idx);
+    }
+    else if (FAL_ACL_BIND_PORTBITMAP == obj_t)
+    {
+        ports = (sw_list->bind_pts) | obj_idx;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    rv = _isisc_acl_rule_bind(dev_id, list_id, ports);
+    SW_RTN_ON_ERROR(rv);
+
+    sw_list->bind_pts = ports;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                      fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                      a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+    a_uint32_t ports;
+    isisc_acl_list_t *sw_list;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISISC_MAX_LIST_ID < list_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACL_DIREC_IN != direc)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    sw_list = _isisc_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (FAL_ACL_BIND_PORT == obj_t)
+    {
+        ports = (sw_list->bind_pts) & (~(0x1UL << obj_idx));
+    }
+    else if (FAL_ACL_BIND_PORTBITMAP == obj_t)
+    {
+        ports = (sw_list->bind_pts) & (~obj_idx);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    rv = _isisc_acl_rule_bind(dev_id, list_id, ports);
+    SW_RTN_ON_ERROR(rv);
+
+    sw_list->bind_pts = ports;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_acl_udf_type_t udf_type, a_uint32_t offset,
+                               a_uint32_t length)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISISC_UDF_MAX_OFFSET < offset)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISISC_UDF_MAX_OFFSET < length)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
+            || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type))
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    switch (udf_type)
+    {
+        case FAL_ACL_UDF_TYPE_L2:
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_OFFSET, offset, reg);
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_LENGTH, length, reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L3:
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_OFFSET, offset, reg);
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_LENGTH, length, reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L4:
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_OFFSET, offset, reg);
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_LENGTH, length, reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L2_SNAP:
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_OFFSET, offset, reg);
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_LENGTH, length, reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L3_PLUS:
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_OFFSET, offset, reg);
+            SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_LENGTH, length, reg);
+            break;
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
+            || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type))
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL1, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL0, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_acl_udf_type_t udf_type, a_uint32_t * offset,
+                               a_uint32_t * length)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
+            || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type))
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    switch (udf_type)
+    {
+        case FAL_ACL_UDF_TYPE_L2:
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_OFFSET, (*offset), reg);
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_LENGTH, (*length), reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L3:
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_OFFSET, (*offset), reg);
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_LENGTH, (*length), reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L4:
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_OFFSET, (*offset), reg);
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_LENGTH, (*length), reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L2_SNAP:
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_OFFSET, (*offset), reg);
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_LENGTH, (*length), reg);
+            break;
+        case FAL_ACL_UDF_TYPE_L3_PLUS:
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_OFFSET, (*offset), reg);
+            SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_LENGTH, (*length), reg);
+            break;
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+                      a_uint32_t rule_id, a_uint32_t rule_nr, a_bool_t active)
+{
+    sw_error_t rv;
+    a_uint32_t i, ports;
+    isisc_acl_list_t *sw_list;
+    isisc_acl_rule_t *sw_rule;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    sw_list = _isisc_acl_list_loc(dev_id, list_id);
+    if (NULL == sw_list)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (sw_list->rule_nr < (rule_id + rule_nr))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == active)
+    {
+        ports = (sw_list->bind_pts);
+    }
+    else
+    {
+        ports = 0;
+    }
+
+    for (i = 0; i < ISISC_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[dev_id][i]);
+
+        if ((ENT_USED & sw_rule->status)
+                && (list_id == sw_rule->list_id)
+                && (rule_id <= sw_rule->rule_id)
+                && ((rule_id + rule_nr) > sw_rule->rule_id))
+        {
+            rv = _isisc_filter_ports_bind(dev_id, i, ports);
+            SW_RTN_ON_ERROR(rv);
+
+            SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports,
+                                (sw_rule->filter.vlu[4]));
+
+            if (A_TRUE == active)
+            {
+                sw_rule->status &= (~ENT_DEACTIVE);
+            }
+            else
+            {
+                sw_rule->status |= (ENT_DEACTIVE);
+            }
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+                                  a_uint32_t rule_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, regIdx;
+    isisc_acl_rule_t *sw_rule;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    sw_rule = &sw_rule_ent[dev_id][rule_id];
+    if (!(ENT_USED & sw_rule->status))
+    {
+        return SW_NOT_FOUND;
+    }
+
+    regIdx = rule_id >> 5;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ACL_FWD_SRC_FILTER_CTL0, regIdx,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        reg |= (0x1 << (rule_id & 0x1F));
+        sw_rule->src_flt_dis = 0;
+    }
+    else if (A_FALSE == enable)
+    {
+        reg &= ~(0x1 << (rule_id & 0x1F));
+        sw_rule->src_flt_dis = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ACL_FWD_SRC_FILTER_CTL0, regIdx,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
+                                  a_uint32_t rule_id, a_bool_t* enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, regIdx;
+    isisc_acl_rule_t *sw_rule;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    sw_rule = &sw_rule_ent[dev_id][rule_id];
+    if (!(ENT_USED & sw_rule->status))
+    {
+        return SW_NOT_FOUND;
+    }
+
+    regIdx = rule_id >> 5;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ACL_FWD_SRC_FILTER_CTL0, regIdx,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (reg & (0x1 << (rule_id & 0x1F)))
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+
+HSL_LOCAL sw_error_t
+isisc_acl_list_dump(a_uint32_t dev_id)
+{
+    _isisc_acl_list_dump(dev_id);
+    return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+isisc_acl_rule_dump(a_uint32_t dev_id)
+{
+    a_uint32_t flt_idx, i;
+    sw_error_t rv;
+    hw_filter_t filter;
+
+    aos_printk("\nisisc_acl_rule_dump:\n");
+
+    for (flt_idx = 0; flt_idx < ISISC_MAX_FILTER; flt_idx++)
+    {
+        aos_mem_zero(&filter, sizeof (hw_filter_t));
+
+        rv = _isisc_filter_up_to_sw(dev_id, &filter, flt_idx);
+        if (SW_OK != rv)
+        {
+            continue;
+        }
+
+        aos_printk("\n%d filter dump:", flt_idx);
+
+        aos_printk("\nhardware content:");
+        aos_printk("\nact:");
+        for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", filter.act[i]);
+        }
+
+        aos_printk("\nvlu:");
+        for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", filter.vlu[i]);
+        }
+
+        aos_printk("\nmsk:");
+        for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", filter.msk[i]);
+        }
+
+        aos_printk("\nsoftware content:");
+        aos_printk("\nact:");
+        for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", sw_rule_ent[dev_id][flt_idx].filter.act[i]);
+        }
+
+        aos_printk("\nvlu:");
+        for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", sw_rule_ent[dev_id][flt_idx].filter.vlu[i]);
+        }
+
+        aos_printk("\nmsk:");
+        for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", sw_rule_ent[dev_id][flt_idx].filter.msk[i]);
+        }
+
+        aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d] src_flt_dis[%02d]",
+                   sw_rule_ent[dev_id][flt_idx].status,
+                   sw_rule_ent[dev_id][flt_idx].list_id,
+                   sw_rule_ent[dev_id][flt_idx].rule_id,
+                   sw_rule_ent[dev_id][flt_idx].src_flt_dis);
+
+        aos_printk("\n\n");
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+isisc_acl_reset(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    aos_mem_zero(sw_list_ent[dev_id],
+                 ISISC_MAX_FILTER * sizeof (isisc_acl_list_t));
+
+    aos_mem_zero(sw_rule_ent[dev_id],
+                 ISISC_MAX_FILTER * sizeof (isisc_acl_rule_t));
+
+    return SW_OK;
+}
+
+/**
+ * @brief Creat an acl list
+ * @details  Comments:
+  *     If the value of list_pri is more small then the priority is more high,
+ *     that means the list could be first matched.
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] list_pri acl list priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+isisc_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_acl_list_creat(dev_id, list_id, list_pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Destroy an acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_acl_list_destroy(dev_id, list_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one rule or more rules to an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this adding operation in list
+ * @param[in] rule_nr rule number of this adding operation
+ * @param[in] rule rules content of this adding operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+isisc_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+                  a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one rule or more rules from an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[in] rule_nr rule number of this deleteing operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+isisc_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+                     a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_acl_rule_delete(dev_id, list_id, rule_id, rule_nr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Query one particular rule in a particular acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[out] rule rule content of this operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+isisc_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+                    a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_acl_rule_query(dev_id, list_id, rule_id, rule);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+a_uint32_t
+isisc_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id)
+{
+    a_uint32_t i, pos=0;
+    isisc_acl_rule_t *sw_rule;
+
+    for (i = 0; i < ISISC_MAX_FILTER; i++)
+    {
+        sw_rule = &(sw_rule_ent[0][i]);
+
+        if ((ENT_USED & sw_rule->status)
+                && (list_id == sw_rule->list_id) && (sw_rule->rule_id == rule_id)
+                && (!(ENT_DEACTIVE & sw_rule->status)))
+        {
+            pos = i;
+            break;
+
+        }
+    }
+
+    return pos;
+}
+
+
+sw_error_t
+isisc_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act)
+{
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISISC_MAX_LIST_ID < pos)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    sw_rule_ent[dev_id][pos].filter.act[1] = act[1];
+    sw_rule_ent[dev_id][pos].filter.act[2] = act[2];
+
+    sw_rule_tmp[dev_id][pos].filter.act[1] = act[1];
+    sw_rule_tmp[dev_id][pos].filter.act[2] = act[2];
+
+    hw_rule_tmp[dev_id][pos].filter.act[1] = act[1];
+    hw_rule_tmp[dev_id][pos].filter.act[2] = act[2];
+
+
+    return SW_OK;
+}
+
+/**
+ * @brief Bind an acl list to a particular object
+ * @details  Comments:
+ *    If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this binding operation
+ * @param[in] obj_t object type of this binding operation
+ * @param[in] obj_idx object index of this binding operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+isisc_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                   fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                   a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Unbind an acl list from a particular object
+ * @details  Comments:
+  *    If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this unbinding operation
+ * @param[in] obj_t object type of this unbinding operation
+ * @param[in] obj_idx object index of this unbinding operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+isisc_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                     fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                     a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+isisc_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_acl_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_acl_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set user define fields profile on a particular port
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] udf_type udf type
+ * @param[in] offset udf offset
+ * @param[in] length udf length
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_acl_udf_type_t udf_type, a_uint32_t offset,
+                              a_uint32_t length)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_acl_port_udf_profile_set(dev_id, port_id, udf_type, offset,
+                                        length);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get user define fields profile on a particular port
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] udf_type udf type
+ * @param[out] offset udf offset
+ * @param[out] length udf length
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_acl_udf_type_t udf_type, a_uint32_t * offset,
+                              a_uint32_t * length)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_acl_port_udf_profile_get(dev_id, port_id, udf_type, offset,
+                                        length);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Active one or more rules in an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] rule_nr rule number of this deactive operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+                     a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_TRUE);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Deactive one or more rules in an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] rule_nr rule number of this deactive operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+                       a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_FALSE);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief enable acl forward source filter of one rule.
+ * @param[in] dev_id device id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+                                 a_uint32_t rule_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_acl_rule_src_filter_sts_set(dev_id, rule_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief get the status of acl forward source filter of one rule.
+ * @param[in] dev_id device id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
+                                 a_uint32_t rule_id, a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_acl_rule_src_filter_sts_get(dev_id, rule_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+
+sw_error_t
+isisc_acl_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    sw_list_ent[dev_id] =
+        (isisc_acl_list_t *) aos_mem_alloc(ISISC_MAX_FILTER *
+                                          sizeof (isisc_acl_list_t));
+    if (NULL == sw_list_ent[dev_id])
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(sw_list_ent[dev_id],
+                 ISISC_MAX_FILTER * sizeof (isisc_acl_list_t));
+
+    sw_rule_ent[dev_id] =
+        (isisc_acl_rule_t *) aos_mem_alloc(ISISC_MAX_FILTER *
+                                          sizeof (isisc_acl_rule_t));
+    if (NULL == sw_rule_ent[dev_id])
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(sw_rule_ent[dev_id],
+                 ISISC_MAX_FILTER * sizeof (isisc_acl_rule_t));
+
+    hw_rule_tmp[dev_id] =
+        (isisc_acl_rule_t *) aos_mem_alloc(ISISC_HW_RULE_TMP_CNT *
+                                          sizeof (isisc_acl_rule_t));
+    if (NULL == hw_rule_tmp[dev_id])
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    sw_rule_tmp[dev_id] =
+        (isisc_acl_rule_t *) aos_mem_alloc(ISISC_MAX_FILTER *
+                                          sizeof (isisc_acl_rule_t));
+    if (NULL == sw_rule_tmp[dev_id])
+    {
+        return SW_NO_RESOURCE;
+    }
+#ifdef ISISC_SW_ENTRY
+    sw_filter_mem = aos_mem_alloc(ISISC_MAX_FILTER * sizeof (hw_filter_t));
+    if (NULL == sw_filter_mem)
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(sw_filter_mem, ISISC_MAX_FILTER * sizeof (hw_filter_t));
+#endif
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->acl_list_creat = isisc_acl_list_creat;
+        p_api->acl_list_destroy = isisc_acl_list_destroy;
+        p_api->acl_list_bind = isisc_acl_list_bind;
+        p_api->acl_list_unbind = isisc_acl_list_unbind;
+        p_api->acl_rule_add = isisc_acl_rule_add;
+        p_api->acl_rule_delete = isisc_acl_rule_delete;
+        p_api->acl_rule_query = isisc_acl_rule_query;
+        p_api->acl_status_set = isisc_acl_status_set;
+        p_api->acl_status_get = isisc_acl_status_get;
+        p_api->acl_list_dump = isisc_acl_list_dump;
+        p_api->acl_rule_dump = isisc_acl_rule_dump;
+        p_api->acl_port_udf_profile_set = isisc_acl_port_udf_profile_set;
+        p_api->acl_port_udf_profile_get = isisc_acl_port_udf_profile_get;
+        p_api->acl_rule_active = isisc_acl_rule_active;
+        p_api->acl_rule_deactive = isisc_acl_rule_deactive;
+        p_api->acl_rule_src_filter_sts_set = isisc_acl_rule_src_filter_sts_set;
+        p_api->acl_rule_src_filter_sts_get = isisc_acl_rule_src_filter_sts_get;
+        p_api->acl_rule_get_offset = isisc_acl_rule_get_offset;
+        p_api->acl_rule_sync_multi_portmap = isisc_acl_rule_sync_multi_portmap;
+    }
+#endif
+
+    return SW_OK;
+}
+
+sw_error_t
+isisc_acl_cleanup(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (NULL != sw_list_ent[dev_id])
+    {
+        aos_mem_free(sw_list_ent[dev_id]);
+    }
+
+    if (NULL != sw_rule_ent[dev_id])
+    {
+        aos_mem_free(sw_rule_ent[dev_id]);
+    }
+
+    if (NULL != hw_rule_tmp[dev_id])
+    {
+        aos_mem_free(hw_rule_tmp[dev_id]);
+    }
+
+    if (NULL != sw_rule_tmp[dev_id])
+    {
+        aos_mem_free(sw_rule_tmp[dev_id]);
+    }
+#ifdef DESS_SW_ENTRY
+    if (NULL != sw_filter_mem)
+    {
+        aos_mem_free(sw_filter_mem);
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_acl_parse.c b/qca-ssdk/src/hsl/isisc/isisc_acl_parse.c
new file mode 100755
index 0000000..9fb7b5e
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_acl_parse.c
@@ -0,0 +1,2452 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+#include "isisc_acl.h"
+#include "isisc_reg.h"
+#include "isisc_acl_prv.h"
+
+#define DAH  0x1
+#define SAH  0x2
+#define TAG  0x4
+#define STAG 0x8
+#define CTAG 0x10
+
+typedef sw_error_t(*parse_func_t) (fal_acl_rule_t * sw,
+                                   hw_filter_t * hw_filter_snap,
+                                   a_bool_t * b_care);
+
+static a_bool_t
+_isisc_acl_zero_addr(const fal_mac_addr_t addr)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 6; i++)
+    {
+        if (addr.uc[i])
+        {
+            return A_FALSE;
+        }
+    }
+    return A_TRUE;
+}
+
+static a_bool_t
+_isisc_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask,
+                     a_uint32_t chkvlu)
+{
+    if (FAL_ACL_FIELD_MASK == op)
+    {
+        if (0 == mask)
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_RANGE == op)
+    {
+        if ((0 == val) && (chkvlu == mask))
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_LE == op)
+    {
+        if (chkvlu == val)
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_GE == op)
+    {
+        if (0 == val)
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_NE == op)
+    {
+        return A_TRUE;
+    }
+
+    return A_TRUE;
+}
+
+static sw_error_t
+_isisc_acl_rule_bmac_parse(fal_acl_rule_t * sw,
+                          hw_filter_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISISC_MAC_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+    {
+        if (A_TRUE != _isisc_acl_zero_addr(sw->dest_mac_mask))
+        {
+            *b_care = A_TRUE;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+        }
+
+        FIELD_SET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]);
+        FIELD_SET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]);
+        FIELD_SET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]);
+        FIELD_SET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]);
+        FIELD_SET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]);
+        FIELD_SET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]);
+
+        FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]);
+        FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]);
+        FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]);
+        FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]);
+        FIELD_SET_MASK(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]);
+        FIELD_SET_MASK(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+    {
+        if (A_TRUE != _isisc_acl_zero_addr(sw->src_mac_mask))
+        {
+            *b_care = A_TRUE;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+        }
+
+        FIELD_SET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+        FIELD_SET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+        FIELD_SET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]);
+        FIELD_SET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]);
+        FIELD_SET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]);
+        FIELD_SET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+
+        FIELD_SET_MASK(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+        FIELD_SET_MASK(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+        FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]);
+        FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]);
+        FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]);
+        FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+    {
+        if (0x0 != sw->ethtype_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ethtype_val &= sw->ethtype_mask;
+        FIELD_SET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+        FIELD_SET_MASK(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED))
+    {
+        if (0x0 != sw->tagged_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->tagged_val &= sw->tagged_mask;
+        FIELD_SET_MASK(MAC_RUL_M4, TAGGEDV, sw->tagged_val);
+        FIELD_SET_MASK(MAC_RUL_M4, TAGGEDM, sw->tagged_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP))
+    {
+        if (0x0 != sw->up_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->up_val &= sw->up_mask;
+        FIELD_SET(MAC_RUL_V3, VLANPRIV, sw->up_val);
+        FIELD_SET_MASK(MAC_RUL_M3, VLANPRIM, sw->up_mask);
+    }
+
+    FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->vid_op)
+                && (FAL_ACL_FIELD_RANGE != sw->vid_op)
+                && (FAL_ACL_FIELD_LE != sw->vid_op)
+                && (FAL_ACL_FIELD_GE != sw->vid_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_TRUE ==
+                _isisc_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask,
+                                     0xfff))
+        {
+            *b_care = A_TRUE;
+        }
+
+        FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 0);
+        if (FAL_ACL_FIELD_MASK == sw->vid_op)
+        {
+            sw->vid_val &= sw->vid_mask;
+            FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+            FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask);
+            FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 1);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->vid_op)
+        {
+            FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+            FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->vid_op)
+        {
+            FIELD_SET(MAC_RUL_V3, VLANIDV, 0);
+            FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_val);
+        }
+        else
+        {
+            FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+            FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, 0xfff);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI))
+    {
+        if (0x0 != sw->cfi_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->cfi_val &= sw->cfi_mask;
+        FIELD_SET(MAC_RUL_V3, VLANCFIV, sw->cfi_val);
+        FIELD_SET_MASK(MAC_RUL_M3, VLANCFIM, sw->cfi_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ehmac_parse(fal_acl_rule_t * sw,
+                           hw_filter_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i;
+    a_bool_t da_h = A_FALSE, sa_h = A_FALSE;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISISC_EHMAC_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+    {
+        for (i = 0; i < 3; i++)
+        {
+            if (sw->dest_mac_mask.uc[i])
+            {
+                da_h = A_TRUE;
+                break;
+            }
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+    {
+        for (i = 0; i < 3; i++)
+        {
+            if (sw->src_mac_mask.uc[i])
+            {
+                sa_h = A_TRUE;
+                break;
+            }
+        }
+    }
+
+    /* if sa_h and da_h both are true need't process mac address fileds */
+    if ((A_TRUE == da_h) && ((A_TRUE == sa_h)))
+    {
+        da_h = A_FALSE;
+        sa_h = A_FALSE;
+    }
+
+    if (A_TRUE == da_h)
+    {
+        FIELD_SET(EHMAC_RUL_V3, DA_EN, 1);
+
+        if (A_TRUE != _isisc_acl_zero_addr(sw->dest_mac_mask))
+        {
+            *b_care = A_TRUE;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+        }
+
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]);
+        FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]);
+        FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]);
+
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]);
+        FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]);
+        FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]);
+
+        if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+        {
+            if (A_TRUE != _isisc_acl_zero_addr(sw->src_mac_mask))
+            {
+                *b_care = A_TRUE;
+            }
+
+            for (i = 0; i < 6; i++)
+            {
+                sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+            }
+
+            FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+            FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+            FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+
+            FIELD_SET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+            FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+            FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+        }
+    }
+
+    if (A_TRUE == sa_h)
+    {
+        if (A_TRUE != _isisc_acl_zero_addr(sw->src_mac_mask))
+        {
+            *b_care = A_TRUE;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+        }
+
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->src_mac_val.uc[2]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->src_mac_val.uc[3]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->src_mac_val.uc[4]);
+        FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->src_mac_val.uc[5]);
+        FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->src_mac_val.uc[0]);
+        FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->src_mac_val.uc[1]);
+
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE2, sw->src_mac_mask.uc[2]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE3, sw->src_mac_mask.uc[3]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE4, sw->src_mac_mask.uc[4]);
+        FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE5, sw->src_mac_mask.uc[5]);
+        FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE0, sw->src_mac_mask.uc[0]);
+        FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE1, sw->src_mac_mask.uc[1]);
+
+        if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+        {
+            if (A_TRUE != _isisc_acl_zero_addr(sw->dest_mac_mask))
+            {
+                *b_care = A_TRUE;
+            }
+
+            for (i = 0; i < 6; i++)
+            {
+                sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+            }
+
+            FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]);
+            FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]);
+            FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]);
+
+            FIELD_SET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]);
+            FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]);
+            FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+    {
+        if (0x0 != sw->ethtype_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ethtype_val &= sw->ethtype_mask;
+        FIELD_SET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+        FIELD_SET_MASK(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+    }
+
+    /* Process Stag Fields */
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED))
+    {
+        if (0x0 != sw->stagged_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->stagged_val &= sw->stagged_mask;
+        FIELD_SET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val);
+        FIELD_SET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask);
+    }
+
+    FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->stag_vid_op)
+                && (FAL_ACL_FIELD_RANGE != sw->stag_vid_op)
+                && (FAL_ACL_FIELD_LE != sw->stag_vid_op)
+                && (FAL_ACL_FIELD_GE != sw->stag_vid_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_TRUE ==
+                _isisc_acl_field_care(sw->stag_vid_op, sw->stag_vid_val,
+                                     sw->stag_vid_mask, 0xfff))
+        {
+            *b_care = A_TRUE;
+        }
+
+        FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 0);
+        if (FAL_ACL_FIELD_MASK == sw->stag_vid_op)
+        {
+            sw->stag_vid_val &= sw->stag_vid_mask;
+            FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+            FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask);
+            FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1);
+
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->stag_vid_op)
+        {
+            FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+            FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask);
+
+        }
+        else if (FAL_ACL_FIELD_LE == sw->stag_vid_op)
+        {
+            FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, 0);
+            FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_val);
+
+        }
+        else
+        {
+            FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+            FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, 0xfff);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI))
+    {
+        if (0x0 != sw->stag_pri_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->stag_pri_val &= sw->stag_pri_mask;
+        FIELD_SET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val);
+        FIELD_SET_MASK(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI))
+    {
+        if (0x0 != sw->stag_dei_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->stag_dei_val &= sw->stag_dei_mask;
+        FIELD_SET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val);
+        FIELD_SET_MASK(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask);
+    }
+
+    /* Process Ctag Fields */
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED))
+    {
+        if (0x0 != sw->ctagged_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ctagged_val &= sw->ctagged_mask;
+        FIELD_SET_MASK(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val);
+        FIELD_SET_MASK(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask);
+    }
+
+    FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->ctag_vid_op)
+                && (FAL_ACL_FIELD_RANGE != sw->ctag_vid_op)
+                && (FAL_ACL_FIELD_LE != sw->ctag_vid_op)
+                && (FAL_ACL_FIELD_GE != sw->ctag_vid_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_TRUE ==
+                _isisc_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val,
+                                     sw->ctag_vid_mask, 0xfff))
+        {
+            *b_care = A_TRUE;
+        }
+
+        FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 0);
+        if (FAL_ACL_FIELD_MASK == sw->ctag_vid_op)
+        {
+            sw->ctag_vid_val &= sw->ctag_vid_mask;
+            FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+            FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8));
+            FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask);
+            FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8));
+            FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 1);
+
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->ctag_vid_op)
+        {
+            FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+            FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8));
+            FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask);
+            FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8));
+
+        }
+        else if (FAL_ACL_FIELD_LE == sw->ctag_vid_op)
+        {
+            FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, 0);
+            FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, 0);
+            FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_val);
+            FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_val >> 8));
+
+        }
+        else
+        {
+            FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+            FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8));
+            FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, 0xff);
+            FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, 0xf);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI))
+    {
+        if (0x0 != sw->ctag_pri_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ctag_pri_val &= sw->ctag_pri_mask;
+        FIELD_SET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val);
+        FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI))
+    {
+        if (0x0 != sw->ctag_cfi_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ctag_cfi_val &= sw->ctag_cfi_mask;
+        FIELD_SET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val);
+        FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static void
+_isisc_acl_rule_mac_preparse(fal_acl_rule_t * sw, a_bool_t * b_mac,
+                            a_bool_t * eh_mac)
+{
+    a_uint32_t bm = 0, i, tmp;
+
+    *b_mac = A_FALSE;
+    *eh_mac = A_FALSE;
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+    {
+        for (i = 0; i < 3; i++)
+        {
+            if (sw->dest_mac_mask.uc[i])
+            {
+                bm |= DAH;
+                break;
+            }
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+    {
+        for (i = 0; i < 3; i++)
+        {
+            if (sw->src_mac_mask.uc[i])
+            {
+                bm |= SAH;
+                break;
+            }
+        }
+    }
+
+    tmp = 0;
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED))
+    {
+        tmp |= ((sw->tagged_mask & 0x1) << 16);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP))
+    {
+        tmp |= ((sw->up_mask & 0x7) << 13);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI))
+    {
+        tmp |= ((sw->cfi_mask & 0x1) << 12);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID))
+    {
+        if (A_TRUE ==
+                _isisc_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask,
+                                     0xfff))
+        {
+            tmp |= 0xfff;
+        }
+    }
+    if (tmp)
+    {
+        bm |= TAG;
+    }
+
+    tmp = 0;
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED))
+    {
+        tmp |= ((sw->stagged_mask & 0x1) << 16);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI))
+    {
+        tmp |= ((sw->stag_pri_mask & 0x7) << 13);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI))
+    {
+        tmp |= ((sw->stag_dei_mask & 0x1) << 12);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID))
+    {
+        if (A_TRUE ==
+                _isisc_acl_field_care(sw->stag_vid_op, sw->stag_vid_val,
+                                     sw->stag_vid_mask, 0xfff))
+        {
+            tmp |= 0xfff;
+        }
+    }
+    if (tmp)
+    {
+        bm |= STAG;
+    }
+
+    tmp = 0;
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED))
+    {
+        tmp |= ((sw->ctagged_mask & 0x1) << 16);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI))
+    {
+        tmp |= ((sw->ctag_pri_mask & 0x7) << 13);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI))
+    {
+        tmp |= ((sw->ctag_cfi_mask & 0x1) << 12);
+    }
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID))
+    {
+        if (A_TRUE ==
+                _isisc_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val,
+                                     sw->ctag_vid_mask, 0xfff))
+        {
+            tmp |= 0xfff;
+        }
+    }
+    if (tmp)
+    {
+        bm |= CTAG;
+    }
+
+    if ((bm & CTAG) || (bm & STAG))
+    {
+        *eh_mac = A_TRUE;
+    }
+
+    if ((bm & TAG) || ((bm & DAH) && (bm & SAH)))
+    {
+        *b_mac = A_TRUE;
+    }
+}
+
+static sw_error_t
+_isisc_acl_rule_ip4_parse(fal_acl_rule_t * sw,
+                         hw_filter_t * hw, a_bool_t * b_care)
+{
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISISC_IP4_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+    {
+        if (0x0 != sw->ip_dscp_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_dscp_val &= sw->ip_dscp_mask;
+        FIELD_SET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val);
+        FIELD_SET_MASK(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+    {
+        if (0x0 != sw->ip_proto_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_proto_val &= sw->ip_proto_mask;
+        FIELD_SET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val);
+        FIELD_SET_MASK(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_SIP))
+    {
+        if (0x0 != sw->src_ip4_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        sw->src_ip4_val &= sw->src_ip4_mask;
+        hw->vlu[1] = sw->src_ip4_val;
+        hw->msk[1] = sw->src_ip4_mask;
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_DIP))
+    {
+        if (0x0 != sw->dest_ip4_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        sw->dest_ip4_val &= sw->dest_ip4_mask;
+        hw->vlu[0] = sw->dest_ip4_val;
+        hw->msk[0] = sw->dest_ip4_mask;
+    }
+
+    if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+            && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+                || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _isisc_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+                                     sw->src_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+            {
+                sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+                sw->src_l4port_val = 0;
+                sw->src_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+
+        FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 0);
+        if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+        {
+            sw->src_l4port_val &= sw->src_l4port_mask;
+            FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 1);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+        {
+            FIELD_SET(IP4_RUL_V3, IP4SPORTV, 0);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_val);
+        }
+        else
+        {
+            FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, 0xffff);
+        }
+    }
+
+    FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _isisc_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+                                     sw->dest_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+            {
+                sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+                sw->dest_l4port_val = 0;
+                sw->dest_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+
+        FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 0);
+        if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+        {
+            sw->dest_l4port_val &= sw->dest_l4port_mask;
+            FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask);
+            FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 1);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+        {
+            FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+        {
+            FIELD_SET(IP4_RUL_V2, IP4DPORTV, 0);
+            FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_val);
+        }
+        else
+        {
+            FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, 0xffff);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+    {
+        if (0x0 != sw->icmp_type_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        FIELD_SET(IP4_RUL_V3, ICMP_EN, 1);
+
+        sw->icmp_type_val &= sw->icmp_type_mask;
+        FIELD_SET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val);
+        FIELD_SET_MASK(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))
+    {
+        if (0x0 != sw->icmp_code_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        FIELD_SET(IP4_RUL_V3, ICMP_EN, 1);
+
+        sw->icmp_code_val &= sw->icmp_code_mask;
+        FIELD_SET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val);
+        FIELD_SET_MASK(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG))
+    {
+        if (0x0 != sw->tcp_flag_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->tcp_flag_val &= sw->tcp_flag_mask;
+        FIELD_SET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val);
+        FIELD_SET_MASK(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_RIPV1))
+    {
+        if (0x0 != sw->ripv1_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ripv1_val &= sw->ripv1_mask;
+        FIELD_SET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val);
+        FIELD_SET_MASK(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV4))
+    {
+        if (0x0 != sw->dhcpv4_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->dhcpv4_val &= sw->dhcpv4_mask;
+        FIELD_SET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val);
+        FIELD_SET_MASK(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ip6r1_parse(fal_acl_rule_t * sw,
+                           hw_filter_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISISC_IP6R1_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_DIP))
+    {
+        for (i = 0; i < 4; i++)
+        {
+            if (0x0 != sw->dest_ip6_mask.ul[i])
+            {
+                *b_care = A_TRUE;
+            }
+
+            sw->dest_ip6_val.ul[3 - i] &= sw->dest_ip6_mask.ul[3 - i];
+            hw->vlu[i] = sw->dest_ip6_val.ul[3 - i];
+            hw->msk[i] = sw->dest_ip6_mask.ul[3 - i];
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ip6r2_parse(fal_acl_rule_t * sw,
+                           hw_filter_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISISC_IP6R2_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_SIP))
+    {
+        for (i = 0; i < 4; i++)
+        {
+            if (0x0 != sw->src_ip6_mask.ul[i])
+            {
+                *b_care = A_TRUE;
+            }
+
+            sw->src_ip6_val.ul[3 - i] &= sw->src_ip6_mask.ul[3 - i];
+            hw->vlu[i] = sw->src_ip6_val.ul[3 - i];
+            hw->msk[i] = sw->src_ip6_mask.ul[3 - i];
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ip6r3_parse(fal_acl_rule_t * sw,
+                           hw_filter_t * hw, a_bool_t * b_care)
+{
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISISC_IP6R3_FILTER);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL))
+    {
+        if (0x0 != sw->ip6_lable_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip6_lable_val &= sw->ip6_lable_mask;
+        FIELD_SET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val);
+        FIELD_SET_MASK(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask);
+
+        FIELD_SET(IP6_RUL3_V2, IP6LABEL2V, (sw->ip6_lable_val >> 16));
+        FIELD_SET_MASK(IP6_RUL3_M2, IP6LABEL2M, (sw->ip6_lable_mask >> 16));
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+    {
+        if (0x0 != sw->ip_proto_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_proto_val &= sw->ip_proto_mask;
+        FIELD_SET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val);
+        FIELD_SET_MASK(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+    {
+        if (0x0 != sw->ip_dscp_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_dscp_val &= sw->ip_dscp_mask;
+        FIELD_SET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val);
+        FIELD_SET_MASK(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask);
+    }
+
+    if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+            && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+                || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _isisc_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+                                     sw->src_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+            {
+                sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+                sw->src_l4port_val = 0;
+                sw->src_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 0);
+        if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+        {
+            sw->src_l4port_val &= sw->src_l4port_mask;
+            FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 1);
+
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask);
+
+        }
+        else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+        {
+            FIELD_SET(IP6_RUL3_V3, IP6SPORTV, 0);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_val);
+
+        }
+        else
+        {
+            FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, 0xffff);
+        }
+    }
+
+    FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 1);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _isisc_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+                                     sw->dest_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+            {
+                sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+                sw->dest_l4port_val = 0;
+                sw->dest_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 0);
+        if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+        {
+            sw->dest_l4port_val &= sw->dest_l4port_mask;
+            FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask);
+            FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 1);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+        {
+            FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+        {
+            FIELD_SET(IP6_RUL3_V2, IP6DPORTV, 0);
+            FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_val);
+        }
+        else
+        {
+            FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+            FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, 0xffff);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+    {
+        if (0x0 != sw->icmp_type_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1);
+
+        sw->icmp_type_val &= sw->icmp_type_mask;
+        FIELD_SET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val);
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))
+    {
+        if (0x0 != sw->icmp_code_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1);
+
+        sw->icmp_code_val &= sw->icmp_code_mask;
+        FIELD_SET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val);
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG))
+    {
+        if (0x0 != sw->tcp_flag_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->tcp_flag_val &= sw->tcp_flag_mask;
+        FIELD_SET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val);
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV6))
+    {
+        if (0x0 != sw->dhcpv6_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->dhcpv6_val &= sw->dhcpv6_mask;
+        FIELD_SET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val);
+        FIELD_SET_MASK(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_udf_parse(fal_acl_rule_t * sw,
+                         hw_filter_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+    FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISISC_UDF_FILTER);
+
+    if (!FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_UDF))
+    {
+        if (FAL_ACL_RULE_UDF == sw->rule_type)
+        {
+            if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+            {
+                FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+            }
+            *b_care = A_TRUE;
+        }
+        return SW_OK;
+    }
+
+    if (ISISC_MAX_UDF_LENGTH < sw->udf_len)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    *b_care = A_TRUE;
+    for (i = 0; i < sw->udf_len; i++)
+    {
+        hw->vlu[3 - i / 4] |=
+            ((sw->udf_mask[i] & sw->udf_val[i]) << (24 - 8 * (i % 4)));
+        hw->msk[3 - i / 4] |= ((sw->udf_mask[i]) << (24 - 8 * (i % 4)));
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+    {
+        FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw,
+                       hw_filter_t * hw)
+{
+    fal_pbmp_t des_pts;
+
+    aos_mem_zero(&(hw->act[0]), sizeof (hw->act));
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, TRIGGER_INTR, 1);
+    }
+
+    /* FAL_ACL_ACTION_PERMIT need't process */
+
+    if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU))
+            && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU)))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x3);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_DENY))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x7);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MIRROR))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, MIRR_EN, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, DES_PORT_EN, 1);
+
+        des_pts = (sw->ports >> 3) & 0xf;
+        FIELD_SET_ACTION(ACL_RSLT2, DES_PORT1, des_pts);
+
+        des_pts = sw->ports & 0x7;
+        FIELD_SET_ACTION(ACL_RSLT1, DES_PORT0, des_pts);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_UP))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, PRI_QU_EN, 1);
+        FIELD_SET_ACTION(ACL_RSLT1, PRI_QU, sw->queue);
+    }
+
+    if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+            || (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN)))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, DSCPV, sw->dscp);
+        FIELD_SET_ACTION(ACL_RSLT1, DSCP_REMAP, 1);
+    }
+
+    FIELD_SET_ACTION(ACL_RSLT0, STAGVID, sw->stag_vid);
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, TRANS_SVID_CHG, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI))
+    {
+        FIELD_SET_ACTION(ACL_RSLT0, STAGPRI, sw->stag_pri);
+        FIELD_SET_ACTION(ACL_RSLT1, STAG_PRI_REMAP, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI))
+    {
+        FIELD_SET_ACTION(ACL_RSLT0, STAGDEI, sw->stag_dei);
+        FIELD_SET_ACTION(ACL_RSLT1, STAG_DEI_CHG, 1);
+    }
+
+    FIELD_SET_ACTION(ACL_RSLT0, CTAGVID, sw->ctag_vid);
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, TRANS_CVID_CHG, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI))
+    {
+        FIELD_SET_ACTION(ACL_RSLT0, CTAGPRI, sw->ctag_pri);
+        FIELD_SET_ACTION(ACL_RSLT1, CTAG_PRI_REMAP, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI))
+    {
+        FIELD_SET_ACTION(ACL_RSLT0, CTAGCFI, sw->ctag_cfi);
+        FIELD_SET_ACTION(ACL_RSLT1, CTAG_CFI_CHG, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, LOOK_VID_CHG, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICER_EN))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, POLICER_PTR, sw->policer_ptr);
+        FIELD_SET_ACTION(ACL_RSLT2, POLICER_EN, 1);
+    }
+
+    if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN))
+            && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN)))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR, sw->arp_ptr);
+        FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR_EN, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN))
+    {
+        FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr);
+        FIELD_SET_ACTION(ACL_RSLT1, WCMP_EN, 1);
+        FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR_EN, 1);
+    }
+
+    FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x0);
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN))
+    {
+        if (FAL_ACL_POLICY_ROUTE == sw->policy_fwd)
+        {
+            return SW_NOT_SUPPORTED;
+        }
+        else if (FAL_ACL_POLICY_SNAT == sw->policy_fwd)
+        {
+            FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x1);
+        }
+        else if (FAL_ACL_POLICY_DNAT == sw->policy_fwd)
+        {
+            FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x2);
+        }
+        else if (FAL_ACL_POLICY_RESERVE == sw->policy_fwd)
+        {
+            FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x3);
+        }
+        else
+        {
+            return SW_BAD_PARAM;
+        }
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, EG_BYPASS, 1);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR))
+    {
+        FIELD_SET_ACTION(ACL_RSLT2, TRIGGER_INTR, 1);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_bmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t mask_en;
+
+    /* destnation mac address */
+    FIELD_GET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]);
+    FIELD_GET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]);
+    FIELD_GET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]);
+    FIELD_GET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]);
+    FIELD_GET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]);
+    FIELD_GET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]);
+
+    FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]);
+    FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]);
+    FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]);
+    FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]);
+    FIELD_GET_MASK(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]);
+    FIELD_GET_MASK(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]);
+    if (A_FALSE == _isisc_acl_zero_addr(sw->dest_mac_mask))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+    }
+
+    /* source mac address */
+    FIELD_GET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]);
+    FIELD_GET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]);
+    FIELD_GET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]);
+    FIELD_GET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+    FIELD_GET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+    FIELD_GET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+
+    FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]);
+    FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]);
+    FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]);
+    FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+    FIELD_GET_MASK(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+    FIELD_GET_MASK(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+    if (A_FALSE == _isisc_acl_zero_addr(sw->src_mac_mask))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+    }
+
+    /* ethernet type */
+    FIELD_GET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+    FIELD_GET_MASK(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+    if (0x0 != sw->ethtype_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+    }
+
+    /* packet tagged */
+    FIELD_GET_MASK(MAC_RUL_M4, TAGGEDV, sw->tagged_val);
+    FIELD_GET_MASK(MAC_RUL_M4, TAGGEDM, sw->tagged_mask);
+    if (0x0 != sw->tagged_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED);
+    }
+
+    /* vlan priority */
+    FIELD_GET(MAC_RUL_V3, VLANPRIV, sw->up_val);
+    FIELD_GET_MASK(MAC_RUL_M3, VLANPRIM, sw->up_mask);
+    if (0x0 != sw->up_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_UP);
+    }
+
+    /* vlanid */
+    FIELD_GET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+    FIELD_GET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask);
+    FIELD_GET_MASK(MAC_RUL_M4, VIDMSK, mask_en);
+    if (mask_en)
+    {
+        sw->vid_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->vid_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _isisc_acl_field_care(sw->vid_op, (a_uint32_t) sw->vid_val,
+                                 (a_uint32_t) sw->vid_mask, 0xfff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_VID);
+    }
+
+    /* vlan cfi */
+    FIELD_GET(MAC_RUL_V3, VLANCFIV, sw->cfi_val);
+    FIELD_GET_MASK(MAC_RUL_M3, VLANCFIM, sw->cfi_mask);
+    if (0x0 != sw->cfi_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CFI);
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+    if (mask_en)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ehmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t i, mask_en, data;
+
+    FIELD_GET(EHMAC_RUL_V3, DA_EN, data);
+    if (data)
+    {
+        for (i = 2; i < 6; i++)
+        {
+            sw->dest_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff;
+            sw->dest_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff;
+        }
+
+        for (i = 0; i < 2; i++)
+        {
+            sw->dest_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff;
+            sw->dest_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff;
+        }
+
+        if (A_FALSE == _isisc_acl_zero_addr(sw->dest_mac_mask))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+        }
+
+        FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+        FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+        FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+
+        FIELD_GET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+        FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+        FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+
+        if (A_FALSE == _isisc_acl_zero_addr(sw->src_mac_mask))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+        }
+    }
+    else
+    {
+        for (i = 2; i < 6; i++)
+        {
+            sw->src_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff;
+            sw->src_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff;
+        }
+
+        for (i = 0; i < 2; i++)
+        {
+            sw->src_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff;
+            sw->src_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff;
+        }
+
+        if (A_FALSE == _isisc_acl_zero_addr(sw->src_mac_mask))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+        }
+
+        FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]);
+        FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]);
+        FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]);
+
+        FIELD_GET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]);
+        FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]);
+        FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]);
+        if (A_FALSE == _isisc_acl_zero_addr(sw->dest_mac_mask))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+        }
+    }
+
+    /* ethernet type */
+    FIELD_GET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+    FIELD_GET_MASK(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+    if (0x0 != sw->ethtype_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+    }
+
+    /* packet stagged */
+    FIELD_GET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val);
+    FIELD_GET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask);
+    if (0x0 != sw->stagged_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED);
+    }
+
+    /* stag vid */
+    FIELD_GET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+    FIELD_GET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask);
+    FIELD_GET(EHMAC_RUL_V3, SVIDMSK, mask_en);
+    if (mask_en)
+    {
+        sw->stag_vid_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->stag_vid_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _isisc_acl_field_care(sw->stag_vid_op, (a_uint32_t) sw->stag_vid_val,
+                                 (a_uint32_t) sw->stag_vid_mask, 0xfff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID);
+    }
+
+    /* stag priority */
+    FIELD_GET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val);
+    FIELD_GET_MASK(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask);
+    if (0x0 != sw->stag_pri_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI);
+    }
+
+    /* stag dei */
+    FIELD_GET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val);
+    FIELD_GET_MASK(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask);
+    if (0x0 != sw->stag_dei_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI);
+    }
+
+    /* packet ctagged */
+    FIELD_GET_MASK(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val);
+    FIELD_GET_MASK(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask);
+    if (0x0 != sw->ctagged_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED);
+    }
+
+    /* ctag vid */
+    FIELD_GET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+    FIELD_GET(EHMAC_RUL_V3, CTAG_VIDHV, data);
+    sw->ctag_vid_val |= (data << 8);
+    FIELD_GET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask);
+    FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, data);
+    sw->ctag_vid_mask |= (data << 8);
+
+    FIELD_GET_MASK(EHMAC_RUL_M4, CVIDMSK, mask_en);
+    if (mask_en)
+    {
+        sw->ctag_vid_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->ctag_vid_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _isisc_acl_field_care(sw->ctag_vid_op, (a_uint32_t) sw->ctag_vid_val,
+                                 (a_uint32_t) sw->ctag_vid_mask, 0xfff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID);
+    }
+
+    /* ctag priority */
+    FIELD_GET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val);
+    FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask);
+    if (0x0 != sw->ctag_pri_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI);
+    }
+
+    /* ctag dei */
+    FIELD_GET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val);
+    FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask);
+    if (0x0 != sw->ctag_cfi_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI);
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+    if (mask_en)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ip4_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t mask_en, icmp_en;
+
+    sw->dest_ip4_val = hw->vlu[0];
+    sw->dest_ip4_mask = hw->msk[0];
+    if (0x0 != sw->dest_ip4_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_DIP);
+    }
+
+    sw->src_ip4_val = hw->vlu[1];
+    sw->src_ip4_mask = hw->msk[1];
+    if (0x0 != sw->src_ip4_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_SIP);
+    }
+
+    FIELD_GET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val);
+    FIELD_GET_MASK(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask);
+    if (0x0 != sw->ip_proto_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+    }
+
+    FIELD_GET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val);
+    FIELD_GET_MASK(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask);
+    if (0x0 != sw->ip_dscp_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+    }
+
+    FIELD_GET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+    FIELD_GET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask);
+    FIELD_GET_MASK(IP4_RUL_M3, IP4DPORTM_EN, mask_en);
+    if (mask_en)
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _isisc_acl_field_care(sw->dest_l4port_op,
+                                 (a_uint32_t) sw->dest_l4port_val,
+                                 (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+    else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+
+    FIELD_GET(IP4_RUL_V3, ICMP_EN, icmp_en);
+    if (icmp_en)
+    {
+        FIELD_GET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val);
+        FIELD_GET_MASK(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask);
+        if (0x0 != sw->icmp_type_mask)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE);
+        }
+
+        FIELD_GET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val);
+        FIELD_GET_MASK(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask);
+        if (0x0 != sw->icmp_code_mask)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE);
+        }
+    }
+    else
+    {
+        FIELD_GET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+        FIELD_GET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask);
+        FIELD_GET_MASK(IP4_RUL_M3, IP4SPORTM_EN, mask_en);
+        if (mask_en)
+        {
+            sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+        }
+        else
+        {
+            sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+        }
+
+        if (A_TRUE ==
+                _isisc_acl_field_care(sw->src_l4port_op,
+                                     (a_uint32_t) sw->src_l4port_val,
+                                     (a_uint32_t) sw->src_l4port_mask, 0xffff))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+        }
+    }
+
+    FIELD_GET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val);
+    FIELD_GET_MASK(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask);
+    if (0x0 != sw->tcp_flag_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG);
+    }
+
+    FIELD_GET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val);
+    FIELD_GET_MASK(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask);
+    if (0x0 != sw->ripv1_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_RIPV1);
+    }
+
+    FIELD_GET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val);
+    FIELD_GET_MASK(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask);
+    if (0x0 != sw->dhcpv4_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV4);
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+    if (mask_en)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 4; i++)
+    {
+        sw->dest_ip6_val.ul[i] = hw->vlu[3 - i];
+        sw->dest_ip6_mask.ul[i] = hw->msk[3 - i];
+        if (0x0 != sw->dest_ip6_mask.ul[i])
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_DIP);
+        }
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, i);
+    if (i)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 4; i++)
+    {
+        sw->src_ip6_val.ul[i] = hw->vlu[3 - i];
+        sw->src_ip6_mask.ul[i] = hw->msk[3 - i];
+        if (0x0 != sw->src_ip6_mask.ul[i])
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_SIP);
+        }
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, i);
+    if (i)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t mask_en, icmp6_en, tmp;
+
+    FIELD_GET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val);
+    FIELD_GET_MASK(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask);
+    if (0x0 != sw->ip_proto_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+    }
+
+    FIELD_GET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val);
+    FIELD_GET_MASK(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask);
+    if (0x0 != sw->ip_dscp_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+    }
+
+    FIELD_GET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+    FIELD_GET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask);
+    FIELD_GET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, mask_en);
+    if (mask_en)
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _isisc_acl_field_care(sw->dest_l4port_op,
+                                 (a_uint32_t) sw->dest_l4port_val,
+                                 (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+    else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+
+    FIELD_GET(IP6_RUL3_V3, ICMP6_EN, icmp6_en);
+    if (icmp6_en)
+    {
+        FIELD_GET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val);
+        FIELD_GET_MASK(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask);
+        if (0x0 != sw->icmp_type_mask)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE);
+        }
+
+        FIELD_GET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val);
+        FIELD_GET_MASK(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask);
+        if (0x0 != sw->icmp_code_mask)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE);
+        }
+    }
+    else
+    {
+        FIELD_GET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+        FIELD_GET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask);
+        FIELD_GET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, mask_en);
+        if (mask_en)
+        {
+            sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+        }
+        else
+        {
+            sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+        }
+
+        if (A_TRUE ==
+                _isisc_acl_field_care(sw->src_l4port_op,
+                                     (a_uint32_t) sw->src_l4port_val,
+                                     (a_uint32_t) sw->src_l4port_mask, 0xffff))
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+        }
+    }
+
+    FIELD_GET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val);
+    FIELD_GET_MASK(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask);
+
+    FIELD_GET(IP6_RUL3_V2, IP6LABEL2V, tmp);
+    sw->ip6_lable_val |= (tmp << 16);
+    FIELD_GET_MASK(IP6_RUL3_M2, IP6LABEL2M, tmp);
+    sw->ip6_lable_mask |= (tmp << 16);
+
+    if (0x0 != sw->ip6_lable_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL);
+    }
+
+    FIELD_GET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val);
+    FIELD_GET_MASK(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask);
+    if (0x0 != sw->tcp_flag_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG);
+    }
+
+    FIELD_GET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val);
+    FIELD_GET_MASK(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask);
+    if (0x0 != sw->dhcpv6_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV6);
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+    if (mask_en)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_udf_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t i;
+
+    FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_UDF);
+
+    /* for ISIS UDF type, length and offset no meanging in rules, just set default value */
+    sw->udf_type = FAL_ACL_UDF_TYPE_L2;
+    sw->udf_len = 16;
+    sw->udf_offset = 0;
+
+    for (i = 0; i < ISISC_MAX_UDF_LENGTH; i++)
+    {
+        sw->udf_val[i] = ((hw->vlu[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff;
+        sw->udf_mask[i] = ((hw->msk[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff;
+    }
+
+    FIELD_GET(MAC_RUL_V4, RULE_INV, i);
+    if (i)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_action_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+    a_uint32_t data;
+
+    sw->action_flg = 0;
+
+    FIELD_GET_ACTION(ACL_RSLT2, DES_PORT_EN, data);
+    if (1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REDPT);
+        FIELD_GET_ACTION(ACL_RSLT1, DES_PORT0, sw->ports);
+        FIELD_GET_ACTION(ACL_RSLT2, DES_PORT1, data);
+        sw->ports |= (data << 3);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT2, FWD_CMD, data);
+    if (0x7 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_DENY);
+    }
+    else if (0x3 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_RDTCPU);
+    }
+    else if (0x1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_CPYCPU);
+    }
+    else
+    {
+        /* need't set permit action */
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT2, MIRR_EN, data);
+    if (1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MIRROR);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, PRI_QU_EN, data);
+    if (1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE);
+        FIELD_GET_ACTION(ACL_RSLT1, PRI_QU, sw->queue);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, DSCP_REMAP, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP);
+        FIELD_GET_ACTION(ACL_RSLT1, DSCPV, sw->dscp);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT0, STAGVID, sw->stag_vid);
+
+    FIELD_GET_ACTION(ACL_RSLT1, TRANS_SVID_CHG, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, STAG_PRI_REMAP, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI);
+        FIELD_GET_ACTION(ACL_RSLT0, STAGPRI, sw->stag_pri);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, STAG_DEI_CHG, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI);
+        FIELD_GET_ACTION(ACL_RSLT0, STAGDEI, sw->stag_dei);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT0, CTAGVID, sw->ctag_vid);
+
+    FIELD_GET_ACTION(ACL_RSLT1, TRANS_CVID_CHG, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, CTAG_PRI_REMAP, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI);
+        FIELD_GET_ACTION(ACL_RSLT0, CTAGPRI, sw->ctag_pri);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, CTAG_CFI_CHG, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI);
+        FIELD_GET_ACTION(ACL_RSLT0, CTAGCFI, sw->ctag_cfi);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, LOOK_VID_CHG, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT2, POLICER_EN, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICER_EN);
+        FIELD_GET_ACTION(ACL_RSLT2, POLICER_PTR, sw->policer_ptr);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR_EN, data);
+    if (data)
+    {
+        FIELD_GET_ACTION(ACL_RSLT1, WCMP_EN, data);
+        if (data)
+        {
+            FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_WCMP_EN);
+            FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr);
+        }
+        else
+        {
+            FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_ARP_EN);
+            FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR, sw->arp_ptr);
+        }
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT1, FORCE_L3_MODE, data);
+    if ((0 != data) && (3 != data))
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN);
+        if (0x1 == data)
+        {
+            sw->policy_fwd = FAL_ACL_POLICY_SNAT;
+        }
+        else
+        {
+            sw->policy_fwd = FAL_ACL_POLICY_DNAT;
+        }
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT2, EG_BYPASS, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS);
+    }
+
+    FIELD_GET_ACTION(ACL_RSLT2, TRIGGER_INTR, data);
+    if (data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR);
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+_isisc_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+                        isisc_acl_rule_t * hw_rule_snap, a_uint32_t * idx)
+{
+    sw_error_t rv;
+    a_uint32_t tmp_idx, i, b_rule[7] = { 0 };
+    parse_func_t ptr[7] = { NULL };
+    a_bool_t b_care, b_mac, eh_mac;
+
+    rv = _isisc_acl_action_parse(dev_id, sw, &(hw_rule_snap[*idx].filter));
+    SW_RTN_ON_ERROR(rv);
+
+    ptr[0] = _isisc_acl_rule_udf_parse;
+    _isisc_acl_rule_mac_preparse(sw, &b_mac, &eh_mac);
+
+    /* ehmac rule must be parsed bofore mac rule.
+       it's important for reparse process */
+    if (A_TRUE == eh_mac)
+    {
+        ptr[1] = _isisc_acl_rule_ehmac_parse;
+    }
+
+    if (A_TRUE == b_mac)
+    {
+        ptr[2] = _isisc_acl_rule_bmac_parse;
+    }
+
+    if ((A_FALSE == b_mac) && (A_FALSE == eh_mac))
+    {
+        ptr[2] = _isisc_acl_rule_bmac_parse;
+    }
+
+    if (FAL_ACL_RULE_MAC == sw->rule_type)
+    {
+    }
+    else if (FAL_ACL_RULE_IP4 == sw->rule_type)
+    {
+        ptr[3] = _isisc_acl_rule_ip4_parse;
+    }
+    else if (FAL_ACL_RULE_IP6 == sw->rule_type)
+    {
+        ptr[4] = _isisc_acl_rule_ip6r1_parse;
+        ptr[5] = _isisc_acl_rule_ip6r2_parse;
+        ptr[6] = _isisc_acl_rule_ip6r3_parse;
+    }
+    else if (FAL_ACL_RULE_UDF == sw->rule_type)
+    {
+        ptr[1] = NULL;
+        ptr[2] = NULL;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    tmp_idx = *idx;
+    for (i = 0; i < 7; i++)
+    {
+        if (ptr[i])
+        {
+            if (ISISC_HW_RULE_TMP_CNT <= tmp_idx)
+            {
+                return SW_NO_RESOURCE;
+            }
+
+            rv = ptr[i] (sw, &(hw_rule_snap[tmp_idx].filter), &b_care);
+            SW_RTN_ON_ERROR(rv);
+            if (A_TRUE == b_care)
+            {
+                tmp_idx++;
+                b_rule[i] = 1;
+            }
+        }
+    }
+
+    if (FAL_ACL_RULE_IP6 == sw->rule_type)
+    {
+        if ((!b_rule[4]) && (!b_rule[5]) && (!b_rule[6]))
+        {
+            tmp_idx++;
+        }
+    }
+
+    if (FAL_ACL_RULE_IP4 == sw->rule_type)
+    {
+        if (!b_rule[3])
+        {
+            tmp_idx++;
+        }
+    }
+
+    if (tmp_idx == *idx)
+    {
+        /* set type start & end */
+        SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND,
+                            (hw_rule_snap[*idx].filter.msk[4]));
+        (*idx)++;
+    }
+    else
+    {
+        if (1 == (tmp_idx - *idx))
+        {
+            if (FAL_ACL_COMBINED_START == sw->combined)
+            {
+                SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START,
+                                    (hw_rule_snap[*idx].filter.msk[4]));
+            }
+            else if (FAL_ACL_COMBINED_CONTINUE == sw->combined)
+            {
+                SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE,
+                                    (hw_rule_snap[*idx].filter.msk[4]));
+            }
+            else if (FAL_ACL_COMBINED_END == sw->combined)
+            {
+                SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END,
+                                    (hw_rule_snap[*idx].filter.msk[4]));
+            }
+            else
+            {
+                SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND,
+                                (hw_rule_snap[*idx].filter.msk[4]));
+            }
+        }
+        else
+        {
+            for (i = *idx; i < tmp_idx; i++)
+            {
+                if (i == *idx)
+                {
+                    SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START,
+                                        (hw_rule_snap[i].filter.msk[4]));
+                }
+                else if (i == (tmp_idx - 1))
+                {
+                    SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END,
+                                        (hw_rule_snap[i].filter.msk[4]));
+                }
+                else
+                {
+                    SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE,
+                                        (hw_rule_snap[i].filter.msk[4]));
+                }
+                aos_mem_copy(&(hw_rule_snap[i].filter.act[0]),
+                             &(hw_rule_snap[*idx].filter.act[0]),
+                             sizeof (hw_rule_snap[*idx].filter.act));
+            }
+        }
+        *idx = tmp_idx;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+_isisc_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+                        isisc_acl_rule_t * hw_rule_snap, a_uint32_t idx,
+                        a_uint32_t ent_nr)
+{
+    a_bool_t b_mac = A_FALSE, b_ip4 = A_FALSE, b_ip6 = A_FALSE;
+    sw_error_t rv;
+    a_uint32_t i, flt_typ;
+    hw_filter_t *hw;
+
+    rv = _isisc_acl_rule_action_reparse(sw, &(hw_rule_snap[idx].filter));
+    SW_RTN_ON_ERROR(rv);
+
+    sw->rule_type = FAL_ACL_RULE_UDF;
+    for (i = 0; i < ent_nr; i++)
+    {
+        hw = &(hw_rule_snap[idx + i].filter);
+        FIELD_GET_MASK(MAC_RUL_M4, RULE_TYP, flt_typ);
+
+        if (ISISC_UDF_FILTER == flt_typ)
+        {
+            rv = _isisc_acl_rule_udf_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+        }
+        else if (ISISC_MAC_FILTER == flt_typ)
+        {
+            rv = _isisc_acl_rule_bmac_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_mac = A_TRUE;
+        }
+        else if (ISISC_EHMAC_FILTER == flt_typ)
+        {
+            rv = _isisc_acl_rule_ehmac_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_mac = A_TRUE;
+        }
+        else if (ISISC_IP4_FILTER == flt_typ)
+        {
+            rv = _isisc_acl_rule_ip4_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_ip4 = A_TRUE;
+        }
+        else if (ISISC_IP6R1_FILTER == flt_typ)
+        {
+            rv = _isisc_acl_rule_ip6r1_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_ip6 = A_TRUE;
+        }
+        else if (ISISC_IP6R2_FILTER == flt_typ)
+        {
+            rv = _isisc_acl_rule_ip6r2_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_ip6 = A_TRUE;
+        }
+        else if (ISISC_IP6R3_FILTER == flt_typ)
+        {
+            rv = _isisc_acl_rule_ip6r3_reparse(sw, hw);
+            SW_RTN_ON_ERROR(rv);
+            b_ip6 = A_TRUE;
+        }
+        else
+        {
+            /* ignore fill gap filters */
+        }
+    }
+
+    if (A_TRUE == b_mac)
+    {
+        sw->rule_type = FAL_ACL_RULE_MAC;
+    }
+
+    if (A_TRUE == b_ip4)
+    {
+        sw->rule_type = FAL_ACL_RULE_IP4;
+    }
+
+    if (A_TRUE == b_ip6)
+    {
+        sw->rule_type = FAL_ACL_RULE_IP6;
+    }
+
+    return SW_OK;
+}
diff --git a/qca-ssdk/src/hsl/isisc/isisc_acl_prv.h b/qca-ssdk/src/hsl/isisc/isisc_acl_prv.h
new file mode 100755
index 0000000..cd5540a
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_acl_prv.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+typedef struct
+{
+    a_uint8_t  status;
+    a_uint8_t  list_id;
+    a_uint8_t  list_pri;
+    a_uint8_t  rule_nr;
+    fal_pbmp_t bind_pts;
+} isisc_acl_list_t;
+
+
+typedef struct
+{
+    a_uint32_t  vlu[5];
+    a_uint32_t  msk[5];
+    a_uint32_t  act[3];
+} hw_filter_t;
+
+
+typedef struct
+{
+    a_uint8_t   status;
+    a_uint8_t   list_id;
+    a_uint8_t   list_pri;
+    a_uint8_t   rule_id;
+    hw_filter_t filter;
+    a_uint32_t  src_flt_dis; /* src filter disabled */
+} isisc_acl_rule_t;
+
+
+#define ENT_USED                0x1
+#define ENT_TMP                 0x2
+#define ENT_DEACTIVE            0x4
+
+#define FLT_START               0x0
+#define FLT_CONTINUE            0x1
+#define FLT_END                 0x2
+#define FLT_STARTEND            0x3
+
+
+#define ISISC_MAC_FILTER         1
+#define ISISC_IP4_FILTER         2
+#define ISISC_IP6R1_FILTER       3
+#define ISISC_IP6R2_FILTER       4
+#define ISISC_IP6R3_FILTER       5
+#define ISISC_UDF_FILTER         6
+#define ISISC_EHMAC_FILTER       7
+
+
+#define ISISC_MAX_UDF_OFFSET     31
+#define ISISC_MAX_UDF_LENGTH     16
+
+
+#define ISISC_FILTER_VLU_OP      0x0
+#define ISISC_FILTER_MSK_OP      0x1
+#define ISISC_FILTER_ACT_OP      0x2
+
+
+
+//#define ISISC_MAX_FILTER         8
+#define ISISC_MAX_FILTER         96
+#define ISISC_RULE_FUNC_ADDR     0x0400
+#define ISISC_HW_RULE_TMP_CNT    (ISISC_MAX_FILTER + 4)
+
+#define ISISC_MAX_LIST_ID        255
+#define ISISC_MAX_LIST_PRI       255
+
+#define ISISC_UDF_MAX_LENGTH     15
+#define ISISC_UDF_MAX_OFFSET     31
+
+#define WIN_RULE_CTL0_ADDR      0x218
+#define WIN_RULE_CTL1_ADDR      0x234
+
+
+#define ISISC_FILTER_VLU_ADDR    0x58000
+#define ISISC_FILTER_MSK_ADDR    0x59000
+#define ISISC_FILTER_ACT_ADDR    0x5a000
+
+
+#define FIELD_SET(reg, field, val) \
+    SW_REG_SET_BY_FIELD_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define FIELD_GET(reg, field, val) \
+    SW_FIELD_GET_BY_REG_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define FIELD_SET_MASK(reg, field, val) \
+    SW_REG_SET_BY_FIELD_U32(hw->msk[reg-5], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define FIELD_GET_MASK(reg, field, val) \
+    SW_FIELD_GET_BY_REG_U32(hw->msk[reg-5], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define FIELD_SET_ACTION(reg, field, val) \
+    SW_REG_SET_BY_FIELD_U32(hw->act[reg-10], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+#define FIELD_GET_ACTION(reg, field, val) \
+    SW_FIELD_GET_BY_REG_U32(hw->act[reg-10], val, reg##_##field##_BOFFSET, \
+                            reg##_##field##_BLEN)
+
+sw_error_t
+_isisc_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw, isisc_acl_rule_t * hw_filter_snap, a_uint32_t * idx);
+
+
+sw_error_t
+_isisc_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw, isisc_acl_rule_t * hw_filter_snap, a_uint32_t idx, a_uint32_t ent_nr);
+
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_cosmap.c b/qca-ssdk/src/hsl/isisc/isisc_cosmap.c
new file mode 100755
index 0000000..49473d5
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_cosmap.c
@@ -0,0 +1,647 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_cosmap ISISC_COSMAP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_cosmap.h"
+#include "isisc_reg.h"
+
+#define ISISC_MAX_DSCP                63
+#define ISISC_MAX_UP                  7
+#define ISISC_MAX_PRI                 7
+#define ISISC_MAX_DP                  1
+#define ISISC_MAX_QUEUE               3
+#define ISISC_MAX_EH_QUEUE            5
+
+#define ISISC_DSCP_TO_PRI             0
+#define ISISC_DSCP_TO_DP              1
+#define ISISC_UP_TO_PRI               2
+#define ISISC_UP_TO_DP                3
+
+#define ISISC_EGRESS_REAMRK_ADDR      0x5ae00
+#define ISISC_EGRESS_REAMRK_NUM       16
+
+#ifndef IN_COSMAP_MINI
+static sw_error_t
+_isisc_cosmap_dscp_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode,
+                                a_uint32_t dscp, a_uint32_t val)
+{
+    sw_error_t rv;
+    a_uint32_t index, data = 0;
+
+    if (ISISC_MAX_DSCP < dscp)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    index = dscp >> 3;
+    HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (ISISC_DSCP_TO_PRI == mode)
+    {
+        if (ISISC_MAX_PRI < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x7 << ((dscp & 0x7) << 2)));
+        data |= (val << ((dscp & 0x7) << 2));
+    }
+    else
+    {
+        if (ISISC_MAX_DP < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x1 << (((dscp & 0x7) << 2) + 3)));
+        data |= (val << (((dscp & 0x7) << 2) + 3));
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_cosmap_dscp_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode,
+                                a_uint32_t dscp, a_uint32_t * val)
+{
+    sw_error_t rv;
+    a_uint32_t index, data = 0;
+
+    if (ISISC_MAX_DSCP < dscp)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    index = dscp >> 3;
+    HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (data >> ((dscp & 0x7) << 2)) & 0xf;
+    if (ISISC_DSCP_TO_PRI == mode)
+    {
+        *val = data & 0x7;
+    }
+    else
+    {
+        *val = (data & 0x8) >> 3;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_cosmap_up_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up,
+                              a_uint32_t val)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (ISISC_MAX_UP < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (ISISC_UP_TO_PRI == mode)
+    {
+        if (ISISC_MAX_PRI < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x7 << (up << 2)));
+        data |= (val << (up << 2));
+    }
+    else
+    {
+        if (ISISC_MAX_DP < val)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        data &= (~(0x1 << ((up << 2) + 3)));
+        data |= (val << ((up << 2) + 3));
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_cosmap_up_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up,
+                              a_uint32_t * val)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (ISISC_MAX_UP < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (data >> (up << 2)) & 0xf;
+
+    if (ISISC_UP_TO_PRI == mode)
+    {
+        *val = (data & 0x7);
+    }
+    else
+    {
+        *val = (data & 0x8) >> 3;
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isisc_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+                              a_uint32_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if ((ISISC_MAX_PRI < pri) || (ISISC_MAX_QUEUE < queue))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0x3 << (pri << 2)));
+    data |= (queue << (pri << 2));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+                                a_uint32_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if ((ISISC_MAX_PRI < pri) || (ISISC_MAX_EH_QUEUE < queue))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0x7 << (pri << 2)));
+    data |= (queue << (pri << 2));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+#ifndef IN_COSMAP_MINI
+static sw_error_t
+_isisc_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+                              a_uint32_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (ISISC_MAX_PRI < pri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *queue = (data >> (pri << 2)) & 0x3;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+                                a_uint32_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (ISISC_MAX_PRI < pri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *queue = (data >> (pri << 2)) & 0x7;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+                               fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+    a_uint32_t data, addr;
+
+    if (ISISC_EGRESS_REAMRK_NUM <= tbl_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = (tbl->y_up & 0x7)
+           | ((tbl->g_up & 0x7) << 4)
+           | ((tbl->y_dscp & 0x3f) << 8)
+           | ((tbl->g_dscp & 0x3f) << 16)
+           | ((tbl->remark_dscp & 0x1) << 23)
+           | ((tbl->remark_up & 0x1) << 22);
+
+    addr = ISISC_EGRESS_REAMRK_ADDR + (tbl_id << 4);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+                               fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, addr;
+
+    if (ISISC_EGRESS_REAMRK_NUM <= tbl_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(tbl, sizeof (fal_egress_remark_table_t));
+
+    addr = ISISC_EGRESS_REAMRK_ADDR + (tbl_id << 4);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data & (0x1 << 23))
+    {
+        tbl->remark_dscp = A_TRUE;
+        tbl->y_dscp = (data >> 8) & 0x3f;
+        tbl->g_dscp = (data >> 16) & 0x3f;
+    }
+
+    if (data & (0x1 << 22))
+    {
+        tbl->remark_up = A_TRUE;
+        tbl->y_up = data & 0x7;
+        tbl->g_up = (data >> 4) & 0x7;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set dscp to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cosmap_dscp_to_pri_dp_set(dev_id, ISISC_DSCP_TO_PRI, dscp, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dscp to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+                            a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cosmap_dscp_to_pri_dp_get(dev_id, ISISC_DSCP_TO_PRI, dscp, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dscp to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cosmap_dscp_to_pri_dp_set(dev_id, ISISC_DSCP_TO_DP, dscp, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dscp to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cosmap_dscp_to_pri_dp_get(dev_id, ISISC_DSCP_TO_DP, dscp, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dot1p to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cosmap_up_to_pri_dp_set(dev_id, ISISC_UP_TO_PRI, up, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dot1p to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cosmap_up_to_pri_dp_get(dev_id, ISISC_UP_TO_PRI, up, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dot1p to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cosmap_up_to_pri_dp_set(dev_id, ISISC_UP_TO_DP, up, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dot1p to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cosmap_up_to_pri_dp_get(dev_id, ISISC_UP_TO_DP, up, dp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 1/2/3/4 which have four egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+                             a_uint32_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cosmap_pri_to_queue_set(dev_id, pri, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 0/5/6 which have six egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+                               a_uint32_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cosmap_pri_to_ehqueue_set(dev_id, pri, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_COSMAP_MINI
+/**
+ * @brief Get internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 1/2/3/4 which have four egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+                             a_uint32_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cosmap_pri_to_queue_get(dev_id, pri, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get internal priority to queue mapping on one particular device.
+ * @details  Comments:
+ * This function is for port 0/5/6 which have six egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+                               a_uint32_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cosmap_pri_to_ehqueue_get(dev_id, pri, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress queue based CoS remap table on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] tbl_id CoS remap table id
+ * @param[in] tbl CoS remap table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+                              fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cosmap_egress_remark_set(dev_id, tbl_id, tbl);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress queue based CoS remap table on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] tbl_id CoS remap table id
+ * @param[out] tbl CoS remap table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+                              fal_egress_remark_table_t * tbl)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cosmap_egress_remark_get(dev_id, tbl_id, tbl);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+sw_error_t
+isisc_cosmap_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+#ifndef IN_COSMAP_MINI
+        p_api->cosmap_dscp_to_pri_set = isisc_cosmap_dscp_to_pri_set;
+        p_api->cosmap_dscp_to_pri_get = isisc_cosmap_dscp_to_pri_get;
+        p_api->cosmap_dscp_to_dp_set = isisc_cosmap_dscp_to_dp_set;
+        p_api->cosmap_dscp_to_dp_get = isisc_cosmap_dscp_to_dp_get;
+        p_api->cosmap_up_to_pri_set = isisc_cosmap_up_to_pri_set;
+        p_api->cosmap_up_to_pri_get = isisc_cosmap_up_to_pri_get;
+        p_api->cosmap_up_to_dp_set = isisc_cosmap_up_to_dp_set;
+        p_api->cosmap_up_to_dp_get = isisc_cosmap_up_to_dp_get;
+#endif
+        p_api->cosmap_pri_to_queue_set = isisc_cosmap_pri_to_queue_set;
+	p_api->cosmap_pri_to_ehqueue_set = isisc_cosmap_pri_to_ehqueue_set;
+#ifndef IN_COSMAP_MINI
+        p_api->cosmap_pri_to_queue_get = isisc_cosmap_pri_to_queue_get;
+        p_api->cosmap_pri_to_ehqueue_get = isisc_cosmap_pri_to_ehqueue_get;
+        p_api->cosmap_egress_remark_set = isisc_cosmap_egress_remark_set;
+        p_api->cosmap_egress_remark_get = isisc_cosmap_egress_remark_get;
+#endif
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_fdb.c b/qca-ssdk/src/hsl/isisc/isisc_fdb.c
new file mode 100755
index 0000000..dd5d815
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_fdb.c
@@ -0,0 +1,2296 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_fdb ISISC_FDB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_fdb.h"
+#include "isisc_reg.h"
+#include "isisc_fdb_prv.h"
+
+#ifndef IN_FDB_MINI
+static sw_error_t
+_isisc_wl_feature_check(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (S17C_DEVICE_ID == entry)
+    {
+        return SW_OK;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+}
+#endif
+
+static a_bool_t
+_isisc_fdb_is_zeroaddr(fal_mac_addr_t addr)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 6; i++)
+    {
+        if (addr.uc[i])
+        {
+            return A_FALSE;
+        }
+    }
+
+    return A_TRUE;
+}
+
+static void
+_isisc_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1)
+{
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1);
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE2, addr.uc[2], *reg0);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE3, addr.uc[3], *reg0);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0);
+
+    return;
+}
+
+#ifndef IN_FDB_MINI
+static sw_error_t
+_isisc_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry,
+                   a_uint32_t reg[])
+{
+    a_uint32_t port;
+    sw_error_t rv;
+
+    if (A_TRUE == entry->white_list_en)
+    {
+        rv = _isisc_wl_feature_check(dev_id);
+        SW_RTN_ON_ERROR(rv);
+
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, WL_EN, 1, reg[2]);
+    }
+
+    if (FAL_SVL_FID == entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]);
+    }
+    else if (ISISC_MAX_FID >= entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == entry->portmap_en)
+    {
+        if (A_TRUE !=
+                hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+
+        port = 0x1UL << entry->port.id;
+    }
+    else
+    {
+        if (A_FALSE ==
+                hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+
+        port = entry->port.map;
+    }
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg[1]);
+
+    if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]);
+    }
+    else if (FAL_MAC_FRWRD != entry->dacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->leaky_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]);
+    }
+
+    if (A_TRUE == entry->static_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]);
+    }
+
+    if (FAL_MAC_DROP == entry->sacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, SA_DROP_EN, 1, reg[1]);
+    }
+    else if (FAL_MAC_FRWRD != entry->sacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->mirror_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, MIRROR_EN, 1, reg[1]);
+    }
+
+    if (A_TRUE == entry->cross_pt_state)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 1, reg[1]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 0, reg[1]);
+    }
+
+    if (A_TRUE == entry->da_pri_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 1, reg[1]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI, (entry->da_queue & 0x7),
+                            reg[1]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 0, reg[1]);
+    }
+
+    _isisc_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+    return SW_OK;
+}
+#endif
+
+static void
+_isisc_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+    a_uint32_t i, data;
+
+    aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_SVL_EN, data, reg[1]);
+    if (data)
+    {
+        entry->fid = FAL_SVL_FID;
+    }
+    else
+    {
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_VID, data, reg[2]);
+        entry->fid = data;
+    }
+
+    entry->dacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_CPY_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    entry->sacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, SA_DROP_EN, data, reg[1]);
+    if (1 == data)
+    {
+        entry->sacmd = FAL_MAC_DROP;
+    }
+
+    entry->leaky_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->leaky_en = A_TRUE;
+    }
+
+    entry->static_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]);
+    if (0xf == data)
+    {
+        entry->static_en = A_TRUE;
+    }
+
+    entry->mirror_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, MIRROR_EN, data, reg[1]);
+    if (1 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+
+    entry->da_pri_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI_EN, data, reg[1]);
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI, data, reg[1]);
+        entry->da_pri_en = A_TRUE;
+        entry->da_queue = data & 0x7;
+    }
+
+    entry->cross_pt_state = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, CROSS_PT, data, reg[1]);
+    if (1 == data)
+    {
+        entry->cross_pt_state = A_TRUE;
+    }
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, data, reg[1]);
+    entry->portmap_en = A_TRUE;
+    entry->port.map = data;
+
+    for (i = 2; i < 6; i++)
+    {
+        entry->addr.uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff;
+    }
+
+    for (i = 0; i < 2; i++)
+    {
+        entry->addr.uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff;
+    }
+
+    entry->white_list_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, WL_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->white_list_en = A_TRUE;
+    }
+
+    return;
+}
+
+static sw_error_t
+_isisc_atu_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                      (a_uint8_t *) (&reg[3]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_atu_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                      (a_uint8_t *) (&reg[3]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_fdb_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    sw_error_t rv;
+    a_uint32_t busy = 1;
+    a_uint32_t full_vio;
+    a_uint32_t i = 2000;
+    a_uint32_t entry = 0;
+    a_uint32_t hwop = op;
+
+    while (busy && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry);
+    }
+
+    if (0 == i)
+    {
+        return SW_BUSY;
+    }
+
+    if (ARL_FIRST_ENTRY == op)
+    {
+        hwop = ARL_NEXT_ENTRY;
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_BUSY, 1, entry);
+
+    if (ARL_FLUSH_PORT_AND_STATIC == hwop)
+    {
+        hwop = ARL_FLUSH_PORT_UNICAST;
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 1, entry);
+    }
+
+    if (ARL_FLUSH_PORT_NO_STATIC == hwop)
+    {
+        hwop = ARL_FLUSH_PORT_UNICAST;
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 0, entry);
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_FUNC, hwop, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    busy = 1;
+    i = 2000;
+    while (busy && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry);
+    }
+
+    if (0 == i)
+    {
+        return SW_FAIL;
+    }
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_FULL_VIO, full_vio, entry);
+
+    if (full_vio)
+    {
+        /* must clear AT_FULL_VOI bit */
+        entry = 0x1000;
+        HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        if (ARL_LOAD_ENTRY == hwop)
+        {
+            return SW_FULL;
+        }
+        else if ((ARL_PURGE_ENTRY == hwop)
+                 || (ARL_FLUSH_PORT_UNICAST == hwop))
+        {
+            return SW_NOT_FOUND;
+        }
+        else
+        {
+            return SW_FAIL;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_get(a_uint32_t dev_id, fal_fdb_op_t * option, fal_fdb_entry_t * entry,
+              a_uint32_t hwop)
+{
+    sw_error_t rv;
+    a_uint32_t i, port = 0, status, reg[4] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == option->port_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_EN, 1, reg[3]);
+        if (A_FALSE == entry->portmap_en)
+        {
+            if (A_TRUE !=
+                    hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+            {
+                return SW_BAD_PARAM;
+            }
+            port = entry->port.id;
+        }
+        else
+        {
+            if (A_FALSE ==
+                    hsl_mports_prop_check(dev_id, entry->port.map,
+                                          HSL_PP_INCL_CPU))
+            {
+                return SW_BAD_PARAM;
+            }
+
+            status = 0;
+            for (i = 0; i < SW_MAX_NR_PORT; i++)
+            {
+                if ((entry->port.map) & (0x1UL << i))
+                {
+                    if (status)
+                    {
+                        return SW_BAD_PARAM;
+                    }
+                    port = i;
+                    status = 1;
+                }
+            }
+        }
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port, reg[3]);
+    }
+
+    if (A_TRUE == option->fid_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]);
+    }
+
+    if (A_TRUE == option->multicast_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]);
+    }
+
+    if (FAL_SVL_FID == entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]);
+    }
+    else if (ISISC_MAX_FID >= entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, entry->fid, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ARL_FIRST_ENTRY != hwop)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 0xf, reg[2]);
+    }
+
+    _isisc_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+
+    rv = _isisc_atu_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_fdb_commit(dev_id, hwop);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_atu_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    _isisc_atu_hw_to_sw(reg, entry);
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]);
+    if ((A_TRUE == _isisc_fdb_is_zeroaddr(entry->addr))
+            && (0 == status))
+    {
+        if (ARL_NEXT_ENTRY == hwop)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            return SW_NOT_FOUND;
+        }
+    }
+    else
+    {
+        return SW_OK;
+    }
+
+    return SW_OK;
+}
+
+#ifndef IN_FDB_MINI
+static sw_error_t
+_isisc_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[4] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_atu_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_atu_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+    return rv;
+}
+#endif
+
+static sw_error_t
+_isisc_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        rv = _isisc_fdb_commit(dev_id, ARL_FLUSH_ALL);
+    }
+    else
+    {
+        rv = _isisc_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+    }
+
+    return rv;
+}
+#ifndef IN_FDB_MINI
+static sw_error_t
+_isisc_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port_id, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        rv = _isisc_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC);
+    }
+    else
+    {
+        rv = _isisc_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC);
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg0 = 0, reg1 = 0, reg2 = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    _isisc_fdb_fill_addr(entry->addr, &reg0, &reg1);
+
+    if (FAL_SVL_FID == entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg2);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg1);
+    }
+    else if (ISISC_MAX_FID >= entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg2);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg1);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, (a_uint8_t *) (&reg2),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (&reg1),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&reg0),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_fdb_commit(dev_id, ARL_PURGE_ENTRY);
+    return rv;
+}
+#endif
+
+static sw_error_t
+_isisc_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    fal_fdb_op_t option;
+
+    aos_mem_zero(&option, sizeof (fal_fdb_op_t));
+    rv = _isisc_fdb_get(dev_id, &option, entry, ARL_FIND_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_isisc_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option,
+                      fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    rv = _isisc_fdb_get(dev_id, option, entry, ARL_NEXT_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_isisc_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+                       fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    rv = _isisc_fdb_get(dev_id, option, entry, ARL_FIRST_ENTRY);
+    return rv;
+}
+#ifndef IN_FDB_MINI
+static sw_error_t
+_isisc_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+                   a_uint32_t fid, fal_fdb_op_t * option)
+{
+    sw_error_t rv;
+    a_uint32_t reg[4] = { 0 };
+
+    if (A_TRUE == option->port_en)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == option->fid_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]);
+    }
+
+    if (A_TRUE == option->multicast_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]);
+    }
+
+    if (FAL_SVL_FID == fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]);
+    }
+    else if (ISISC_MAX_FID >= fid)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, fid, reg[2]);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, old_port, reg[3]);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, NEW_PORT_NUM, new_port, reg[3]);
+
+    rv = _isisc_atu_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_fdb_commit(dev_id, ARL_TRANSFER_ENTRY);
+    return rv;
+}
+#endif
+static sw_error_t
+_isisc_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+#ifndef IN_FDB_MINI
+static sw_error_t
+_isisc_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    data = smode;
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, ARL_INI_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, ARL_INI_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+    *smode = data;
+
+    return rv;
+}
+
+
+
+static sw_error_t
+_isisc_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((65535 * 7 < *time) || (7 > *time))
+    {
+        return SW_BAD_PARAM;
+    }
+    data = *time / 7;
+    *time = data * 7;
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *time = data * 7;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        if (ISISC_MAX_PORT_LEARN_LIMIT_CNT < cnt)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, cnt, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, 0, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, data, reg);
+    if (data)
+    {
+        SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, data, reg);
+        *enable = A_TRUE;
+        *cnt = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *cnt = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        if (ISISC_MAX_LEARN_LIMIT_CNT < cnt)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 1,
+                            reg);
+        SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, cnt, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 0,
+                            reg);
+        SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, 0, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable,
+                          a_uint32_t * cnt)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, data,
+                        reg);
+    if (data)
+    {
+        SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, data,
+                            reg);
+        *enable = A_TRUE;
+        *cnt = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *cnt = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+                      GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+                      GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+#define ISISC_RESV_ADDR_NUM  32
+#define RESV_ADDR_TBL0_ADDR 0x3c000
+#define RESV_ADDR_TBL1_ADDR 0x3c004
+#define RESV_ADDR_TBL2_ADDR 0x3c008
+
+static void
+_isisc_resv_addr_parse(const a_uint32_t reg[], fal_mac_addr_t * addr)
+{
+    a_uint32_t i;
+
+    for (i = 2; i < 6; i++)
+    {
+        addr->uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff;
+    }
+
+    for (i = 0; i < 2; i++)
+    {
+        addr->uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff;
+    }
+}
+
+static sw_error_t
+_isisc_resv_atu_sw_to_hw(a_uint32_t dev_id, fal_fdb_entry_t * entry,
+                        a_uint32_t reg[])
+{
+    a_uint32_t port;
+
+    if (A_FALSE == entry->portmap_en)
+    {
+        if (A_TRUE !=
+                hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+        port = 0x1UL << entry->port.id;
+    }
+    else
+    {
+        if (A_FALSE ==
+                hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+        port = entry->port.map;
+    }
+    SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_DES_PORT, port, reg[1]);
+
+    if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, 1, reg[1]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, 1, reg[1]);
+    }
+    else if (FAL_MAC_FRWRD != entry->dacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_MAC_FRWRD != entry->sacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->leaky_en)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 1, reg[1]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 0, reg[1]);
+    }
+
+    if (A_TRUE != entry->static_en)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+    SW_SET_REG_BY_FIELD(RESV_ADDR_TBL2, RESV_STATUS, 1, reg[2]);
+
+    if (A_TRUE == entry->mirror_en)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_MIRROR_EN, 1, reg[1]);
+    }
+
+    if (A_TRUE == entry->cross_pt_state)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_CROSS_PT, 1, reg[1]);
+    }
+
+    if (A_TRUE == entry->da_pri_en)
+    {
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI_EN, 1, reg[1]);
+        SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI, (entry->da_queue & 0x7),
+                            reg[1]);
+    }
+
+    _isisc_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+    return SW_OK;
+}
+
+static void
+_isisc_resv_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+    a_uint32_t data;
+
+    aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+    entry->fid = FAL_SVL_FID;
+
+    entry->dacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, data, reg[1]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_CPY_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, data, reg[1]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    entry->sacmd = FAL_MAC_FRWRD;
+
+    entry->leaky_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_LEAKY_EN, data, reg[1]);
+    if (1 == data)
+    {
+        entry->leaky_en = A_TRUE;
+    }
+
+    entry->static_en = A_TRUE;
+
+    entry->mirror_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_MIRROR_EN, data, reg[1]);
+    if (1 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+
+    entry->da_pri_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI_EN, data, reg[1]);
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI, data, reg[1]);
+        entry->da_pri_en = A_TRUE;
+        entry->da_queue = data & 0x7;
+    }
+
+    entry->cross_pt_state = A_FALSE;
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_CROSS_PT, data, reg[1]);
+    if (1 == data)
+    {
+        entry->cross_pt_state = A_TRUE;
+    }
+
+    SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_DES_PORT, data, reg[1]);
+    entry->portmap_en = A_TRUE;
+    entry->port.map = data;
+
+    _isisc_resv_addr_parse(reg, &(entry->addr));
+    return;
+}
+
+static sw_error_t
+_isisc_fdb_resv_commit(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op,
+                      a_uint32_t * empty)
+{
+    a_uint32_t index, addr, data, tbl[3] = { 0 };
+    sw_error_t rv;
+    fal_mac_addr_t mac_tmp;
+
+    *empty = ISISC_RESV_ADDR_NUM;
+    for (index = 0; index < ISISC_RESV_ADDR_NUM; index++)
+    {
+        addr = RESV_ADDR_TBL2_ADDR + (index << 4);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]);
+        if (data)
+        {
+            addr = RESV_ADDR_TBL0_ADDR + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[0])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            addr = RESV_ADDR_TBL1_ADDR + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[1])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            _isisc_resv_addr_parse(tbl, &mac_tmp);
+            if (!aos_mem_cmp
+                    ((void *) &(entry->addr), (void *) &mac_tmp,
+                     sizeof (fal_mac_addr_t)))
+            {
+                if (ARL_PURGE_ENTRY == op)
+                {
+                    addr = RESV_ADDR_TBL2_ADDR + (index << 4);
+                    tbl[2] = 0;
+                    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                          (a_uint8_t *) (&(tbl[2])),
+                                          sizeof (a_uint32_t));
+                    return rv;
+                }
+                else if (ARL_LOAD_ENTRY == op)
+                {
+                    return SW_ALREADY_EXIST;
+                }
+                else if (ARL_FIND_ENTRY == op)
+                {
+                    _isisc_resv_atu_hw_to_sw(tbl, entry);
+                    return SW_OK;
+                }
+            }
+        }
+        else
+        {
+            *empty = index;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isisc_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, empty, addr, tbl[3] = { 0 };
+
+    rv = _isisc_resv_atu_sw_to_hw(dev_id, entry, tbl);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_fdb_resv_commit(dev_id, entry, ARL_LOAD_ENTRY, &empty);
+    if (SW_ALREADY_EXIST == rv)
+    {
+        return rv;
+    }
+
+    if (ISISC_RESV_ADDR_NUM == empty)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    for (i = 0; i < 3; i++)
+    {
+        addr = RESV_ADDR_TBL0_ADDR + (empty << 4) + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t empty;
+
+    rv = _isisc_fdb_resv_commit(dev_id, entry, ARL_PURGE_ENTRY, &empty);
+    return rv;
+}
+
+static sw_error_t
+_isisc_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t empty;
+
+    rv = _isisc_fdb_resv_commit(dev_id, entry, ARL_FIND_ENTRY, &empty);
+    return rv;
+}
+
+static sw_error_t
+_isisc_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+                       fal_fdb_entry_t * entry)
+{
+    a_uint32_t index, addr, data, tbl[3] = { 0 };
+    sw_error_t rv;
+
+    if ((NULL == iterator) || (NULL == entry))
+    {
+        return SW_BAD_PTR;
+    }
+
+    if (ISISC_RESV_ADDR_NUM < *iterator)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (index = *iterator; index < ISISC_RESV_ADDR_NUM; index++)
+    {
+        addr = RESV_ADDR_TBL2_ADDR + (index << 4);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]);
+        if (data)
+        {
+            addr = RESV_ADDR_TBL0_ADDR + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[0])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            addr = RESV_ADDR_TBL1_ADDR + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[1])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            _isisc_resv_atu_hw_to_sw(tbl, entry);
+            break;
+        }
+    }
+
+    if (ISISC_RESV_ADDR_NUM == index)
+    {
+        return SW_NO_MORE;
+    }
+
+    *iterator = index + 1;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 0xf;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0x7;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      SA_LEARN_STATUS, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      SA_LEARN_STATUS, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0xf == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_port_update(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id, a_uint32_t op)
+{
+    sw_error_t      rv;
+    fal_fdb_entry_t entry;
+    fal_fdb_op_t    option;
+    a_uint32_t      reg, port;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SVL_FID < fid)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(&option, sizeof(fal_fdb_op_t));
+    aos_mem_copy(&(entry.addr), addr, sizeof(fal_mac_addr_t));
+    entry.fid = fid & 0xffff;
+    rv = _isisc_fdb_get(dev_id, &option, &entry, ARL_FIND_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, port, reg);
+    if (op)
+    {
+        port |= (0x1 << port_id);
+    }
+    else
+    {
+        port &= (~(0x1 << port_id));
+    }
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    rv = _isisc_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+    return rv;
+}
+
+sw_error_t
+inter_isisc_fdb_flush(a_uint32_t dev_id, a_uint32_t flag)
+{
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        return _isisc_fdb_commit(dev_id, ARL_FLUSH_ALL);
+    }
+    else
+    {
+        return _isisc_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+    }
+}
+
+/**
+ * @brief Add a Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_add(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Delete all Fdb entries
+ *   @details   Comments:
+ *         If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ *       entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_del_all(dev_id, flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_FDB_MINI
+/**
+ * @brief Delete Fdb entries on a particular port
+ *   @details   Comments:
+ *       If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ *       entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_del_by_port(dev_id, port_id, flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a particular Fdb entry through mac address
+ *   @details   Comments:
+ *       Only addr field in entry is meaning. For IVL learning vid or fid field
+ *       also is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_del_by_mac(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Find a particular Fdb entry from device through mac address.
+ *    @details  Comments:
+    For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_find(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get next Fdb entry from a particular device
+ * @param[in] dev_id device id
+ * @param[in] option next operation options
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option,
+                     fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_extend_next(dev_id, option, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from a particular device
+ * @param[in] dev_id device id
+ * @param[in] option first operation options
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+                      fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_extend_first(dev_id, option, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_FDB_MINI
+/**
+ * @brief Transfer fdb entries port information on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] old_port source port id
+ * @param[in] new_port destination port id
+ * @param[in] fid filter database id
+ * @param[in] option transfer operation options
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+                  a_uint32_t fid, fal_fdb_op_t * option)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_transfer(dev_id, old_port, new_port, fid, option);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set dynamic address learning status on a particular port.
+ *    @details  Comments:
+ *       This operation will enable or disable dynamic address learning
+ *       feature on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_port_learn_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_FDB_MINI
+/**
+ * @brief Get dynamic address learning status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_port_learn_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address aging status on particular device.
+ *   @details  Comments:
+ *       This operation will enable or disable dynamic address aging
+ *       feature on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_age_ctrl_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address aging status on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_age_ctrl_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief set arl search mode as ivl or svl when vlan invalid.
+ * @param[in] dev_id device id
+ * @param[in] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_vlan_ivl_svl_set(dev_id, smode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief get arl search mode when vlan invalid.
+ * @param[in] dev_id device id
+ * @param[out] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_vlan_ivl_svl_get(dev_id, smode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+
+/**
+ * @brief Set dynamic address aging time on a particular device.
+ * @details   Comments:
+ *       This operation will set dynamic address aging time on a particular device.
+ *       The unit of time is second. Because different device has differnet
+ *       hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_age_time_set(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address aging time on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_age_time_get(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_fdb_learn_limit_set(dev_id, port_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_fdb_learn_limit_get(dev_id, port_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count limit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_learn_limit_set(dev_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count limit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_learn_limit_get(dev_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count exceed command on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_learn_exceed_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count exceed command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_learn_exceed_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a particular reserve Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_resv_add(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a particular reserve Fdb entry through mac address
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_resv_del(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a particular reserve Fdb entry through mac address
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @param[out] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_resv_find(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Iterate all reserve fdb entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] iterator reserve fdb entry index if it's zero means get the first entry
+ * @param[out] iterator next valid fdb entry index
+ * @param[out] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+                      fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_resv_iterate(dev_id, iterator, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the static status of fdb entries which learned by hardware on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_port_learn_static_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the static status of fdb entries which learned by hardware on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_port_learn_static_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a port to an exsiting entry
+ * @param[in] dev_id device id
+ * @param[in] fid filtering database id
+ * @param[in] addr MAC address
+ * @param[in] port_id port id
+ * @return SW_OK or error code, If entry not exist will return error.
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_port_update(dev_id, fid, addr, port_id, 1);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a port from an exsiting entry
+ * @param[in] dev_id device id
+ * @param[in] fid filtering database id
+ * @param[in] addr MAC address
+ * @param[in] port_id port id
+ * @return SW_OK or error code, If entry not exist will return error.
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_fdb_port_update(dev_id, fid, addr, port_id, 0);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+sw_error_t
+isisc_fdb_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+#ifndef IN_FDB_MINI
+        p_api->fdb_add = isisc_fdb_add;
+#endif
+        p_api->fdb_del_all = isisc_fdb_del_all;
+#ifndef IN_FDB_MINI
+        p_api->fdb_del_by_port = isisc_fdb_del_by_port;
+        p_api->fdb_del_by_mac = isisc_fdb_del_by_mac;
+#endif
+        p_api->fdb_find = isisc_fdb_find;
+        p_api->port_learn_set = isisc_fdb_port_learn_set;
+#ifndef IN_FDB_MINI
+        p_api->port_learn_get = isisc_fdb_port_learn_get;
+        p_api->age_ctrl_set = isisc_fdb_age_ctrl_set;
+        p_api->age_ctrl_get = isisc_fdb_age_ctrl_get;
+        p_api->vlan_ivl_svl_set = isisc_fdb_vlan_ivl_svl_set;
+        p_api->vlan_ivl_svl_get = isisc_fdb_vlan_ivl_svl_get;
+        p_api->age_time_set = isisc_fdb_age_time_set;
+        p_api->age_time_get = isisc_fdb_age_time_get;
+#endif
+        p_api->fdb_extend_next  = isisc_fdb_extend_next;
+        p_api->fdb_extend_first = isisc_fdb_extend_first;
+#ifndef IN_FDB_MINI
+        p_api->fdb_transfer     = isisc_fdb_transfer;
+        p_api->port_fdb_learn_limit_set = isisc_port_fdb_learn_limit_set;
+        p_api->port_fdb_learn_limit_get = isisc_port_fdb_learn_limit_get;
+        p_api->port_fdb_learn_exceed_cmd_set = isisc_port_fdb_learn_exceed_cmd_set;
+        p_api->port_fdb_learn_exceed_cmd_get = isisc_port_fdb_learn_exceed_cmd_get;
+        p_api->fdb_learn_limit_set = isisc_fdb_learn_limit_set;
+        p_api->fdb_learn_limit_get = isisc_fdb_learn_limit_get;
+        p_api->fdb_learn_exceed_cmd_set = isisc_fdb_learn_exceed_cmd_set;
+        p_api->fdb_learn_exceed_cmd_get = isisc_fdb_learn_exceed_cmd_get;
+        p_api->fdb_resv_add     = isisc_fdb_resv_add;
+        p_api->fdb_resv_del     = isisc_fdb_resv_del;
+        p_api->fdb_resv_find    = isisc_fdb_resv_find;
+        p_api->fdb_resv_iterate = isisc_fdb_resv_iterate;
+        p_api->fdb_port_learn_static_set = isisc_fdb_port_learn_static_set;
+        p_api->fdb_port_learn_static_get = isisc_fdb_port_learn_static_get;
+        p_api->fdb_port_add = isisc_fdb_port_add;
+        p_api->fdb_port_del = isisc_fdb_port_del;
+#endif
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_igmp.c b/qca-ssdk/src/hsl/isisc/isisc_igmp.c
new file mode 100755
index 0000000..83a3df4
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_igmp.c
@@ -0,0 +1,1147 @@
+/*
+ * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_igmp ISISC_IGMP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_igmp.h"
+#include "isisc_reg.h"
+
+#define LEAVE_EN_OFFSET     2
+#define JOIN_EN_OFFSET      1
+#define IGMP_MLD_EN_OFFSET  0
+
+#define ISISC_MAX_PORT_LEARN_LIMIT_CNT 1024
+
+extern sw_error_t
+isisc_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+extern sw_error_t
+isisc_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+extern sw_error_t
+isisc_igmp_sg_entry_show(a_uint32_t dev_id);
+
+extern sw_error_t
+isisc_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t * info);
+
+static sw_error_t
+_isisc_port_igmp_property_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable, a_uint32_t item)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (3 >= port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        reg &= ~(0x1UL << ((port_id << 3) + item));
+        reg |= (val << ((port_id << 3) + item));
+
+        HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        reg &= ~(0x1UL << (((port_id - 4) << 3) + item));
+        reg |= (val << (((port_id - 4) << 3) + item));
+
+        HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_igmp_property_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable, a_uint32_t item)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (3 >= port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        val = (reg >> ((port_id << 3) + item)) & 0x1UL;
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL;
+    }
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_mports_validity_check(dev_id, pts))
+    {
+        return SW_BAD_PARAM;
+    }
+    val = pts;
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *pts = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 0xf;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0xe;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0xf == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable,
+                               a_uint32_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 1, entry);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, queue, entry);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 0, entry);
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, 0, entry);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_CTL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable,
+                               a_uint32_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI_EN, data, entry);
+    if (data)
+    {
+        *enable = A_TRUE;
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI, data, entry);
+        *queue = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *queue = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        if (ISISC_MAX_PORT_LEARN_LIMIT_CNT < cnt)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, cnt, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, 0, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, data, reg);
+    if (data)
+    {
+        SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, data, reg);
+        *enable = A_TRUE;
+        *cnt = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *cnt = data;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+        fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+        fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+                      IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set igmp/mld packets snooping status on a particular port.
+ * @details    Comments:
+ *   After enabling igmp/mld snooping feature on a particular port all kinds
+ *   igmp/mld packets received on this port would be acknowledged by hardware.
+ *   Particular forwarding decision could be setted by fal_igmp_mld_cmd_set.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_igmp_property_set(dev_id, port_id, enable,
+                                      IGMP_MLD_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets snooping status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_igmp_property_get(dev_id, port_id, enable,
+                                      IGMP_MLD_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld packets forwarding command on a particular device.
+ * @details    Comments:
+ *    Particular device may only support parts of forwarding commands.
+ *    This operation will take effect only after enabling igmp/mld snooping
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_igmp_mld_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_igmp_mld_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld join packets hardware acknowledgement status on particular port.
+ * @details    Comments:
+ *    After enabling igmp/mld join feature on a particular port hardware will
+ *    dynamic learning or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_igmp_property_set(dev_id, port_id, enable, JOIN_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_igmp_property_get(dev_id, port_id, enable, JOIN_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @details    Comments:
+ *    After enabling igmp leave feature on a particular port hardware will dynamic
+ *    deleting or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_igmp_property_set(dev_id, port_id, enable, LEAVE_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_igmp_property_get(dev_id, port_id, enable, LEAVE_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld router ports on a particular device.
+ * @details     Comments:
+ *    After enabling igmp/mld join/leave feature on a particular port igmp/mld
+ *    join/leave packets received on this port will be forwarded to router ports.
+ * @param[in] dev_id device id
+ * @param[in] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_igmp_mld_rp_set(dev_id, pts);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld router ports on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_igmp_mld_rp_get(dev_id, pts);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   entry creat hardware will dynamic creat and delete multicast entry,
+ *   otherwise hardware only can change destination ports of existing muticast entry.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_igmp_mld_entry_creat_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_igmp_mld_entry_creat_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the static status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   static status hardware will not age out multicast entry which leardned by hardware,
+ *   otherwise hardware will age out multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_igmp_mld_entry_static_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the static status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_igmp_mld_entry_static_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the leaky status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   leaky status hardware will set leaky flag of multicast entry which leardned by hardware,
+ *   otherwise hardware will not set leaky flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_igmp_mld_entry_leaky_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the leaky status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_igmp_mld_entry_leaky_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @details    Comments:
+ *    After enabling igmp join/leave feature on a particular port hardware will dynamic
+ *    creating or changing multicast entry after receiving igmpv3/mldv2 packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_igmp_mld_entry_v3_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_igmp_mld_entry_v3_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the queue status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   leaky status hardware will set queue flag of multicast entry which leardned by hardware,
+ *   otherwise hardware will not set queue flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable,
+                              a_uint32_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_igmp_mld_entry_queue_set(dev_id, enable, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the queue status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable,
+                              a_uint32_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_igmp_mld_entry_queue_get(dev_id, enable, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IGMP hardware learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable, a_uint32_t cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_igmp_mld_learn_limit_set(dev_id, port_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IGMP hardware learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable, a_uint32_t * cnt)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_igmp_mld_learn_limit_get(dev_id, port_id, enable, cnt);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IGMP hardware learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                                        fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_igmp_mld_learn_exceed_cmd_set(dev_id, port_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IGMP hardware learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                                        fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_igmp_mld_learn_exceed_cmd_get(dev_id, port_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isisc_igmp_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->port_igmps_status_set = isisc_port_igmps_status_set;
+        p_api->port_igmps_status_get = isisc_port_igmps_status_get;
+        p_api->igmp_mld_cmd_set = isisc_igmp_mld_cmd_set;
+        p_api->igmp_mld_cmd_get = isisc_igmp_mld_cmd_get;
+        p_api->port_igmp_join_set = isisc_port_igmp_mld_join_set;
+        p_api->port_igmp_join_get = isisc_port_igmp_mld_join_get;
+        p_api->port_igmp_leave_set = isisc_port_igmp_mld_leave_set;
+        p_api->port_igmp_leave_get = isisc_port_igmp_mld_leave_get;
+        p_api->igmp_rp_set = isisc_igmp_mld_rp_set;
+        p_api->igmp_rp_get = isisc_igmp_mld_rp_get;
+        p_api->igmp_entry_creat_set = isisc_igmp_mld_entry_creat_set;
+        p_api->igmp_entry_creat_get = isisc_igmp_mld_entry_creat_get;
+        p_api->igmp_entry_static_set = isisc_igmp_mld_entry_static_set;
+        p_api->igmp_entry_static_get = isisc_igmp_mld_entry_static_get;
+        p_api->igmp_entry_leaky_set = isisc_igmp_mld_entry_leaky_set;
+        p_api->igmp_entry_leaky_get = isisc_igmp_mld_entry_leaky_get;
+        p_api->igmp_entry_v3_set = isisc_igmp_mld_entry_v3_set;
+        p_api->igmp_entry_v3_get = isisc_igmp_mld_entry_v3_get;
+        p_api->igmp_entry_queue_set = isisc_igmp_mld_entry_queue_set;
+        p_api->igmp_entry_queue_get = isisc_igmp_mld_entry_queue_get;
+        p_api->port_igmp_mld_learn_limit_set = isisc_port_igmp_mld_learn_limit_set;
+        p_api->port_igmp_mld_learn_limit_get = isisc_port_igmp_mld_learn_limit_get;
+        p_api->port_igmp_mld_learn_exceed_cmd_set = isisc_port_igmp_mld_learn_exceed_cmd_set;
+        p_api->port_igmp_mld_learn_exceed_cmd_get = isisc_port_igmp_mld_learn_exceed_cmd_get;
+        p_api->igmp_sg_entry_set = isisc_igmp_sg_entry_set;
+        p_api->igmp_sg_entry_clear = isisc_igmp_sg_entry_clear;
+        p_api->igmp_sg_entry_show = isisc_igmp_sg_entry_show;
+        p_api->igmp_sg_entry_query = isisc_igmp_sg_entry_query;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_init.c b/qca-ssdk/src/hsl/isisc/isisc_init.c
new file mode 100755
index 0000000..e55fa18
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_init.c
@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_init ISISC_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_mib.h"
+#include "isisc_port_ctrl.h"
+#include "isisc_portvlan.h"
+#include "isisc_vlan.h"
+#include "isisc_fdb.h"
+#include "isisc_qos.h"
+#include "isisc_mirror.h"
+#include "isisc_stp.h"
+#include "isisc_rate.h"
+#include "isisc_misc.h"
+#include "isisc_leaky.h"
+#include "isisc_igmp.h"
+#include "isisc_acl.h"
+#include "isisc_led.h"
+#include "isisc_cosmap.h"
+#include "isisc_ip.h"
+#include "isisc_nat.h"
+#if defined(IN_NAT_HELPER)
+#include "isisc_nat_helper.h"
+#endif
+#include "isisc_sec.h"
+#include "isisc_trunk.h"
+#include "isisc_interface_ctrl.h"
+#include "isisc_reg_access.h"
+#include "isisc_reg.h"
+#include "isisc_init.h"
+#include "f1_phy.h"
+
+static ssdk_init_cfg * isisc_cfg[SW_MAX_NR_DEV] = { 0 };
+a_uint32_t isisc_nat_global_status = 0;
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+/* For isis there are five internal PHY devices and seven MAC devices.
+   MAC0 always connect to external MAC device.
+   PHY4 can connect to MAC5 or external MAC device.
+   MAC6 always connect to external devices.
+   MAC1..MAC4 connect to internal PHY0..PHY3.
+*/
+static sw_error_t
+isisc_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
+{
+    hsl_port_prop_t p_type;
+    hsl_dev_t *pdev = NULL;
+    fal_port_t port_id;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return SW_NOT_INITIALIZED;
+
+    /* for port property set, SSDK should not generate some limitations */
+    for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+    {
+        hsl_port_prop_portmap_set(dev_id, port_id);
+
+        for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
+        {
+            if (HSL_NO_CPU == mode)
+            {
+                SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                continue;
+            }
+
+            switch (p_type)
+            {
+                case HSL_PP_PHY:
+                    /* Only port0/port6 without PHY device */
+                    if ((port_id != pdev->cpu_port_nr)
+                            && (port_id != pdev->nr_ports - 1))
+                    {
+                        SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                    }
+                    break;
+
+                case HSL_PP_INCL_CPU:
+                    /* include cpu port but exclude wan port in some cases */
+                    /* but which port is wan port, we are no meaning */
+                    SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                    break;
+
+                case HSL_PP_EXCL_CPU:
+                    /* exclude cpu port and wan port in some cases */
+                    /* which port is wan port, we are no meaning but port0 is
+                       always CPU port */
+                    if (port_id != pdev->cpu_port_nr)
+                    {
+                        SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                    }
+                    break;
+
+                default:
+                    break;
+            }
+        }
+
+        if (HSL_NO_CPU == mode)
+        {
+            SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+                            (dev_id, port_id, port_id + 1));
+        }
+        else
+        {
+            if (port_id != pdev->cpu_port_nr)
+            {
+                SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+                                (dev_id, port_id, port_id - 1));
+            }
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+isisc_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    return SW_OK;
+}
+
+#endif
+
+static sw_error_t
+isisc_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode)
+{
+    a_uint32_t entry = 0;
+    sw_error_t rv;
+    hsl_dev_t *pdev = NULL;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return SW_NOT_INITIALIZED;
+
+    HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (S17C_DEVICE_ID == entry)
+    {
+        pdev->nr_ports = 7;
+        pdev->nr_phy = 5;
+        pdev->cpu_port_nr = 0;
+        pdev->nr_vlans = 4096;
+        pdev->hw_vlan_query = A_TRUE;
+        pdev->nr_queue = 6;
+        pdev->cpu_mode = cpu_mode;
+    }
+    else
+    {
+        pdev->nr_ports = 6;
+        pdev->nr_phy = 5;
+        pdev->cpu_port_nr = 0;
+        pdev->nr_vlans = 4096;
+        pdev->hw_vlan_query = A_TRUE;
+        pdev->nr_queue = 6;
+        pdev->cpu_mode = cpu_mode;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_isisc_reset(a_uint32_t dev_id)
+{
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    val = 0x1;
+    HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = isisc_hw_init(dev_id, isisc_cfg[dev_id]);
+    SW_RTN_ON_ERROR(rv);
+
+    ISISC_ACL_RESET(rv, dev_id);
+    ISISC_IP_RESET(rv, dev_id);
+    ISISC_NAT_RESET(rv, dev_id);
+#endif
+
+    return SW_OK;
+}
+
+sw_error_t
+isisc_cleanup(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    if (isisc_cfg[dev_id])
+    {
+#if defined(IN_NAT_HELPER)
+        if(isisc_nat_global_status) {
+            ISISC_NAT_HELPER_CLEANUP(rv, dev_id);
+			isisc_nat_global_status = 0;
+        }
+#endif
+
+        ISISC_ACL_CLEANUP(rv, dev_id);
+
+        SW_RTN_ON_ERROR(hsl_port_prop_cleanup_by_dev(dev_id));
+
+        aos_mem_free(isisc_cfg[dev_id]);
+        isisc_cfg[dev_id] = NULL;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief reset hsl layer.
+ * @details Comments:
+ *   This operation will reset hsl layer
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_reset(dev_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Init hsl layer.
+ * @details Comments:
+ *   This operation will init hsl layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+isisc_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (NULL == isisc_cfg[dev_id])
+    {
+        isisc_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg));
+    }
+
+    if (NULL == isisc_cfg[dev_id])
+    {
+        return SW_OUT_OF_MEM;
+    }
+
+    aos_mem_copy(isisc_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+
+    SW_RTN_ON_ERROR(isisc_reg_access_init(dev_id, cfg->reg_mode));
+
+    SW_RTN_ON_ERROR(isisc_dev_init(dev_id, cfg->cpu_mode));
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+    {
+        sw_error_t rv;
+
+        SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id));
+        SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
+        SW_RTN_ON_ERROR(isisc_portproperty_init(dev_id, cfg->cpu_mode));
+
+        ISISC_MIB_INIT(rv, dev_id);
+        ISISC_PORT_CTRL_INIT(rv, dev_id);
+        ISISC_PORTVLAN_INIT(rv, dev_id);
+        ISISC_VLAN_INIT(rv, dev_id);
+        ISISC_FDB_INIT(rv, dev_id);
+        ISISC_QOS_INIT(rv, dev_id);
+        ISISC_STP_INIT(rv, dev_id);
+        ISISC_MIRR_INIT(rv, dev_id);
+        ISISC_RATE_INIT(rv, dev_id);
+        ISISC_MISC_INIT(rv, dev_id);
+        ISISC_LEAKY_INIT(rv, dev_id);
+        ISISC_IGMP_INIT(rv, dev_id);
+        ISISC_ACL_INIT(rv, dev_id);
+        ISISC_LED_INIT(rv, dev_id);
+        ISISC_COSMAP_INIT(rv, dev_id);
+        ISISC_IP_INIT(rv, dev_id);
+        ISISC_NAT_INIT(rv, dev_id);
+        ISISC_TRUNK_INIT(rv, dev_id);
+        ISISC_SEC_INIT(rv, dev_id);
+        ISISC_INTERFACE_CTRL_INIT(rv, dev_id);
+
+        {
+            hsl_api_t *p_api;
+
+            SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+            p_api->dev_reset   = isisc_reset;
+            p_api->dev_clean   = isisc_cleanup;
+        }
+
+        SW_RTN_ON_ERROR(isisc_hw_init(dev_id, cfg));
+#if 0
+#if defined(IN_NAT_HELPER)
+		if(!isisc_nat_global_status) {
+        	ISISC_NAT_HELPER_INIT(rv, dev_id);
+			isisc_nat_global_status = 1;
+		}
+
+#endif
+#endif
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_interface_ctrl.c b/qca-ssdk/src/hsl/isisc/isisc_interface_ctrl.c
new file mode 100755
index 0000000..7c45a34
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_interface_ctrl.c
@@ -0,0 +1,2324 @@
+/*
+ * Copyright (c) 2012, 2015-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_interface_ctrl ISISC_INTERFACE_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_interface_ctrl.h"
+#include "isisc_reg.h"
+#include "hsl_phy.h"
+
+#define ISISC_MAC_0     0
+#define ISISC_MAC_5     5
+#define ISISC_MAC_6     6
+
+#define ISISC_PHY_MODE_PHY_ID  4
+#define ISISC_LPI_PORT1_OFFSET 4
+#define ISISC_LPI_BIT_STEP     2
+
+/* we need to do more about MAC5/PHY4 connection... */
+#if 0
+static sw_error_t
+_isisc_port_mac5_internal_mode(a_uint32_t dev_id, a_bool_t * inter_mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg, rgmii, gmii_mac, gmii_phy, mii_mac, mii_phy, sgmii;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_EN,    rgmii, reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, gmii_mac, reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, gmii_phy, reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_EN,  mii_mac, reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN,  mii_phy, reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_SGMII_EN,    sgmii, reg);
+
+    if (rgmii || gmii_mac || gmii_phy || mii_mac || mii_phy || sgmii)
+    {
+        *inter_mode = A_FALSE;
+    }
+    else
+    {
+        *inter_mode = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_phy4_internal_mode(a_uint32_t dev_id, a_bool_t * inter_mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg, rgmii, gmii, mii;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_RGMII_EN, rgmii, reg);
+    SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_GMII_EN,  gmii,  reg);
+    SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_MII_EN,   mii,   reg);
+
+    if (rgmii || gmii || mii)
+    {
+        *inter_mode = A_FALSE;
+    }
+    else
+    {
+        *inter_mode = A_TRUE;
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isisc_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field, offset, device_id, rev_id, reverse = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg);
+    if (S17C_DEVICE_ID != device_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    SW_GET_FIELD_BY_REG(MASK_CTL, REV_ID, rev_id, reg);
+    if (S17_REVISION_A == rev_id)
+    {
+        reverse = 0;
+    }
+    else
+    {
+        reverse = 1;
+    }
+
+    if (rev_id == 0)
+    {
+        reverse = 1;
+    }
+    else
+    {
+        reverse = 0;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        field  = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        field  = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (reverse)
+    {
+        field = (~field) & 0x1UL;
+    }
+
+    offset = (port_id - 1) * ISISC_LPI_BIT_STEP + ISISC_LPI_PORT1_OFFSET;
+    reg &= (~(0x1UL << offset));
+    reg |= (field << offset);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, EEE_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field, offset, device_id, rev_id, reverse = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg);
+    if (S17C_DEVICE_ID != device_id)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    SW_GET_FIELD_BY_REG(MASK_CTL, REV_ID, rev_id, reg);
+    if (S17_REVISION_A == rev_id)
+    {
+        reverse = 0;
+    }
+    else
+    {
+        reverse = 1;
+    }
+
+    if (rev_id == 0)
+    {
+        reverse = 1;
+    }
+    else
+    {
+        reverse = 0;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    offset = (port_id - 1) * ISISC_LPI_BIT_STEP + ISISC_LPI_PORT1_OFFSET;
+    field = (reg >> offset) & 0x1;
+
+    if (reverse)
+    {
+        field = (~field) & 0x1UL;
+    }
+
+    if (field)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_rgmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rgmii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0,  reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg);
+
+    /* hardware suggestions: restore to defatult settings */
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL,     0, reg);
+
+    if (A_TRUE == config->txclk_delay_cmd)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, config->txclk_delay_sel, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg);
+    }
+
+    if (A_TRUE == config->rxclk_delay_cmd)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, config->rxclk_delay_sel, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg);
+    }
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    /* Port status register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    /* setting port status default configuration */
+    SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,        0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE,     2, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_rgmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rgmii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, field, reg);
+    if (field)
+    {
+        config->txclk_delay_cmd = A_TRUE;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, field, reg);
+        config->txclk_delay_sel = field;
+    }
+    else
+    {
+        config->txclk_delay_cmd = A_FALSE;
+        config->txclk_delay_sel = 0;
+    }
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, field, reg);
+    if (field)
+    {
+        config->rxclk_delay_cmd = A_TRUE;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, field, reg);
+        config->rxclk_delay_sel = field;
+    }
+    else
+    {
+        config->rxclk_delay_cmd = A_FALSE;
+        config->rxclk_delay_sel = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MAC06_EXCH_EN, 1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MAC06_EXCH_EN, 0, reg);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0,field;
+
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_MAC06_EXCH_EN, field, reg);
+    if (field)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+
+static sw_error_t
+_isisc_interface_mac_sgmii_set(a_uint32_t dev_id,a_uint32_t value)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+    reg = value;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_interface_mac_sgmii_get(a_uint32_t dev_id, a_uint32_t *value)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+	*value = reg;
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_interface_mac_pad_set(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t value)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    reg = value;
+
+    switch (port_num)
+    {
+	    case ISISC_MAC_0:
+		    HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+				    (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+		    break;
+	    case ISISC_MAC_5:
+		    HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+				    (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+		    break;
+	    case ISISC_MAC_6:
+		    HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+				    (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+		    break;
+	    default:
+		    return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_interface_mac_pad_get(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t *value)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    switch (port_num)
+    {
+	    case ISISC_MAC_0:
+		    HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+				    (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+		    break;
+	    case ISISC_MAC_5:
+		    HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+				    (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+		    break;
+	    case ISISC_MAC_6:
+		    HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+				    (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+		    break;
+	    default:
+		    return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    *value = reg;
+
+    return rv;
+}
+
+
+
+static sw_error_t
+_isisc_port_rmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rmii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (config->master_mode == config->slave_mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_ERROR(rv);
+    if (A_TRUE == config->master_mode)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN,    1, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN,    0, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN,    0, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN,    1, reg);
+    }
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN,    0, reg);
+
+    /* hardware suggestions: restore to defatult settings */
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL,     0, reg);
+
+    if (A_TRUE == config->clock_inverse)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SEL, 1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SEL, 0, reg);
+    }
+
+    if (A_TRUE == config->pipe_rxclk_sel)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_PIPE_RXCLK_SEL, 1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_PIPE_RXCLK_SEL, 0, reg);
+    }
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+
+    SW_RTN_ON_ERROR(rv);
+
+    /* Port status register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    /* setting port status default configuration */
+    SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,        0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE,     2, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_rmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rmii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_MASTER_EN, field, reg);
+    if (field)
+    {
+        config->master_mode = A_TRUE;
+    }
+    else
+    {
+        config->master_mode = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_SLAVE_EN, field, reg);
+    if (field)
+    {
+        config->slave_mode = A_TRUE;
+    }
+    else
+    {
+        config->slave_mode = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_SEL, field, reg);
+    if (field)
+    {
+        config->clock_inverse = A_TRUE;
+    }
+    else
+    {
+        config->clock_inverse = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_PIPE_RXCLK_SEL, field, reg);
+    if (field)
+    {
+        config->pipe_rxclk_sel = A_TRUE;
+    }
+    else
+    {
+        config->pipe_rxclk_sel = A_FALSE;
+    }
+
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_gmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_gmii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0,  reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg);
+
+    /* hardware suggestions: restore to defatult settings */
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL,     0, reg);
+
+    if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, config->txclk_select, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, config->rxclk_select, reg);
+
+    }
+    else if (FAL_INTERFACE_CLOCK_MAC_MODE == config->clock_mode)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, config->txclk_select, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, config->rxclk_select, reg);
+
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    /* Port status register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    /* setting port status default configuration */
+    SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,        0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE,     2, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_gmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_gmii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, field, reg);
+    if (field)
+    {
+        config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, field, reg);
+        config->txclk_select = field;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, field, reg);
+        config->rxclk_select = field;
+
+    }
+    else
+    {
+        config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, field, reg);
+        config->txclk_select = field;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, field, reg);
+        config->rxclk_select = field;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_mii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_mii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0,  reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg);
+
+    /* hardware suggestions: restore to defatult settings */
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL,     0, reg);
+
+    if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 1, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, config->txclk_select, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, config->rxclk_select, reg);
+    }
+    else if (FAL_INTERFACE_CLOCK_MAC_MODE == config->clock_mode)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN,  1, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN,  0, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, config->txclk_select, reg);
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, config->rxclk_select, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    /* Port status register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    /* setting port status default configuration */
+    SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,        0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE,     1, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_mii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_mii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, field, reg);
+    if (field)
+    {
+        config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, field, reg);
+        config->txclk_select = field;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, field, reg);
+        config->rxclk_select = field;
+    }
+    else
+    {
+        config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, field, reg);
+        config->txclk_select = field;
+        SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, field, reg);
+        config->rxclk_select = field;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_sgmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_sgmii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0,  reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg);
+
+    /* hardware suggestions: restore to defatult settings */
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL,     0, reg);
+
+
+    if (A_TRUE == config->force_speed)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_SGMII_FORCE_SPEED,   1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_SGMII_FORCE_SPEED,   0, reg);
+    }
+
+    if (A_TRUE == config->prbs_enable)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_PRBS_BERT_EN,   1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_PRBS_BERT_EN,   0, reg);
+    }
+
+    if (A_TRUE == config->rem_phy_lpbk)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_REM_PHY_LPBK_EN,   1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_REM_PHY_LPBK_EN,   0, reg);
+    }
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        /* only support one SGMII interface, so we need to disable another SGMII */
+        field = 0;
+        HSL_REG_FIELD_SET(rv, dev_id, PORT6_PAD_CTRL, port_id, MAC6_SGMII_EN,
+                          (a_uint8_t *) (&field), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        /* only support one SGMII interface, so we need to disable another SGMII */
+        field = 0;
+        HSL_REG_FIELD_SET(rv, dev_id, PORT0_PAD_CTRL, port_id, MAC0_SGMII_EN,
+                          (a_uint8_t *) (&field), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* SGMII global settings, for all SGMII interfaces, now we fix all the values */
+    /* TX/RX clock setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_RX_SEL,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_TX_SEL,    0, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* SGMII control register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_FIBER_MODE,  0, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_PLL,      1, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_RX,       1, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_TX,       1, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_SD,       1, reg);
+    if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode)
+    {
+        SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 2, reg);
+    }
+    HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* Port status register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    /* setting port status default configuration */
+    SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE,     2, reg);
+    if (A_TRUE == config->auto_neg)
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,   1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,   0, reg);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_sgmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_sgmii_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        /* nothing to do */
+    }
+    else if (ISISC_MAC_6 == port_id)
+    {
+        /* nothing to do */
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, field, reg);
+    if (field)
+    {
+        config->auto_neg = A_TRUE;
+    }
+    else
+    {
+        config->auto_neg = A_FALSE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    SW_GET_FIELD_BY_REG(SGMII_CTRL, MODE_CTRL_25M, field, reg);
+    if (1 == field)
+    {
+        config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE;
+    }
+    else
+    {
+        config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE;
+    }
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, SGMII_PRBS_BERT_EN, field, reg);
+    if (1 == field)
+    {
+        config->prbs_enable = A_TRUE;
+    }
+    else
+    {
+        config->prbs_enable = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, SGMII_REM_PHY_LPBK_EN, field, reg);
+    if (1 == field)
+    {
+        config->rem_phy_lpbk = A_TRUE;
+    }
+    else
+    {
+        config->rem_phy_lpbk = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_fiber_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_fiber_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0,  reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg);
+
+    /* hardware suggestions: restore to defatult settings */
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL,     0, reg);
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        /* only support one SGMII interface, so we need to disable another SGMII */
+        field = 0;
+        HSL_REG_FIELD_SET(rv, dev_id, PORT6_PAD_CTRL, port_id, MAC6_SGMII_EN,
+                          (a_uint8_t *) (&field), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        /* only support one SGMII interface, so we need to disable another SGMII */
+        field = 0;
+        HSL_REG_FIELD_SET(rv, dev_id, PORT0_PAD_CTRL, port_id, MAC0_SGMII_EN,
+                          (a_uint8_t *) (&field), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* SGMII global settings, for all SGMII interfaces, now we fix all the values */
+    /* TX/RX clock setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_RX_SEL,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_TX_SEL,    0, reg);
+
+    if (A_TRUE == config->fx100_enable)
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_FX100_EN,   1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_FX100_EN,   0, reg);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* SGMII control register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M,     0, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_FIBER_MODE,  3, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_PLL,   1, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_RX,    1, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_TX,    1, reg);
+    SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_SD,    1, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* Power on strip register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, POWER_STRIP, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    if (A_TRUE == config->auto_neg)
+    {
+        SW_SET_REG_BY_FIELD(POWER_STRIP, SERDES_AN_EN,   1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(POWER_STRIP, SERDES_AN_EN,   0, reg);
+    }
+    HSL_REG_ENTRY_SET(rv, dev_id, POWER_STRIP, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    /* Port status register setting */
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    /* setting port status default configuration */
+    SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,        0, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN,     1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE,    1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN,       1, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE,     2, reg);
+    if (A_TRUE == config->auto_neg)
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,   1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,   0, reg);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_fiber_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_fiber_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        /* nothing to do */
+    }
+    else if (ISISC_MAC_6 == port_id)
+    {
+        /* nothing to do */
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, POWER_STRIP, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(POWER_STRIP, SERDES_AN_EN, field, reg);
+    if (field)
+    {
+        config->auto_neg = A_TRUE;
+    }
+    else
+    {
+        config->auto_neg = A_FALSE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, SGMII_FX100_EN, field, reg);
+
+    if (field)
+    {
+        config->fx100_enable = A_TRUE;
+    }
+    else
+    {
+        config->fx100_enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_default_mode_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN,  0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0,  reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg);
+
+    /* hardware suggestions: restore to defatult settings */
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL,   0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL,    0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL,     0, reg);
+    SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL,     0, reg);
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_MODE_RGMII == config->mac_mode)
+    {
+        rv = _isisc_port_rgmii_mode_set(dev_id, port_id, &(config->config.rgmii));
+    }
+    else if (FAL_MAC_MODE_GMII == config->mac_mode)
+    {
+        rv = _isisc_port_gmii_mode_set(dev_id, port_id, &(config->config.gmii));
+    }
+    else if (FAL_MAC_MODE_MII == config->mac_mode)
+    {
+        rv = _isisc_port_mii_mode_set(dev_id, port_id, &(config->config.mii));
+    }
+    else if (FAL_MAC_MODE_SGMII == config->mac_mode)
+    {
+        rv = _isisc_port_sgmii_mode_set(dev_id, port_id, &(config->config.sgmii));
+    }
+    else if (FAL_MAC_MODE_FIBER == config->mac_mode)
+    {
+        rv = _isisc_port_fiber_mode_set(dev_id, port_id, &(config->config.fiber));
+    }
+    else if (FAL_MAC_MODE_DEFAULT == config->mac_mode)
+    {
+        rv = _isisc_port_default_mode_set(dev_id, port_id);
+    }
+    else if (FAL_MAC_MODE_RMII == config->mac_mode)
+    {
+        rv = _isisc_port_rmii_mode_set(dev_id, port_id, &(config->config.rmii));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field, field2;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISISC_MAC_0 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_5 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else if (ISISC_MAC_6 == port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    aos_mem_zero(config, sizeof(fal_interface_mac_mode_t));
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_EN, field, reg);
+    if (field)
+    {
+        config->mac_mode = FAL_MAC_MODE_RGMII;
+        rv = _isisc_port_rgmii_mode_get(dev_id, port_id, &(config->config.rgmii));
+        return rv;
+    }
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_MASTER_EN, field,  reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_SLAVE_EN, field2, reg);
+    if (field || field2)
+    {
+        config->mac_mode = FAL_MAC_MODE_RMII;
+        rv = _isisc_port_rmii_mode_get(dev_id, port_id, &(config->config.rmii));
+        return rv;
+    }
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, field,  reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, field2, reg);
+    if (field || field2)
+    {
+        config->mac_mode = FAL_MAC_MODE_GMII;
+        rv = _isisc_port_gmii_mode_get(dev_id, port_id, &(config->config.gmii));
+        return rv;
+    }
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, field,  reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, field2, reg);
+    if (field || field2)
+    {
+        config->mac_mode = FAL_MAC_MODE_MII;
+        rv = _isisc_port_mii_mode_get(dev_id, port_id, &(config->config.mii));
+        return rv;
+    }
+
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_SGMII_EN, field, reg);
+    SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_SGMII_FORCE_SPEED, field2, reg);
+
+    if (field)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(SGMII_CTRL, SGMII_FIBER_MODE, field, reg);
+        if (3 == field)
+        {
+            config->mac_mode = FAL_MAC_MODE_FIBER;
+            rv = _isisc_port_fiber_mode_get(dev_id, port_id, &(config->config.fiber));
+        }
+        else
+        {
+            config->mac_mode = FAL_MAC_MODE_SGMII;
+            rv = _isisc_port_sgmii_mode_get(dev_id, port_id, &(config->config.sgmii));
+            if (field2)
+                config->config.sgmii.force_speed = A_TRUE;
+            else
+                config->config.sgmii.force_speed = A_FALSE;
+        }
+        return rv;
+    }
+
+    config->mac_mode = FAL_MAC_MODE_DEFAULT;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+    sw_error_t rv;
+    a_uint16_t data;
+    a_bool_t tx_delay_cmd, rx_delay_cmd;
+    hsl_phy_ops_t *phy_drv;
+    a_uint32_t reg, rgmii_mode, tx_delay = 2, port_id;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    /* only PHY4 support mode setting */
+    if (ISISC_PHY_MODE_PHY_ID != phy_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+	port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id);
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get(dev_id, port_id));
+    if ((NULL == phy_drv->phy_debug_write) || (NULL == phy_drv->phy_debug_read))
+	  return SW_NOT_SUPPORTED;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_MAC_MODE_RGMII == config->mac_mode)
+    {
+        SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 1, reg);
+        rgmii_mode = 1;
+        /* PHY TX delay */
+        if (A_TRUE == config->txclk_delay_cmd)
+        {
+            tx_delay_cmd = A_TRUE;
+            tx_delay     = config->txclk_delay_sel;
+        }
+        else
+        {
+            tx_delay_cmd = A_FALSE;
+        }
+
+        /* PHY RX delay */
+        if (A_TRUE == config->rxclk_delay_cmd)
+        {
+            rx_delay_cmd = A_TRUE;
+        }
+        else
+        {
+            rx_delay_cmd = A_FALSE;
+        }
+    }
+    else if (FAL_MAC_MODE_DEFAULT == config->mac_mode)
+    {
+        SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 0, reg);
+        rgmii_mode = 0;
+        tx_delay_cmd = A_FALSE;
+        rx_delay_cmd = A_FALSE;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* PHY RGMII mode, debug register18 bit3 */
+    data = phy_drv->phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 18);
+    data &= 0xfff7UL;
+    data |= ((rgmii_mode & 0x1) << 3);
+    rv = phy_drv->phy_debug_write(dev_id, ISISC_PHY_MODE_PHY_ID, 18, data);
+    SW_RTN_ON_ERROR(rv);
+
+    /* PHY TX delay command, debug regigster5 bit8 */
+    data = phy_drv->phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 5);
+    if (A_TRUE == tx_delay_cmd)
+    {
+        data |= 0x0100UL;
+    }
+    else
+    {
+        data &= 0xfeffUL;
+    }
+    rv = phy_drv->phy_debug_write(dev_id, ISISC_PHY_MODE_PHY_ID, 5, data);
+    SW_RTN_ON_ERROR(rv);
+
+    /* PHY TX delay select, debug register11 bit-6 */
+    data = phy_drv->phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 11);
+    data &= 0xff9fUL;
+    data |= ((tx_delay & 0x3UL) << 5);
+    if (A_TRUE == tx_delay_cmd)
+    {
+        data |= 0x0100UL;
+    }
+    else
+    {
+        data &= 0xfeffUL;
+    }
+    rv = phy_drv->phy_debug_write(dev_id, ISISC_PHY_MODE_PHY_ID, 11, data);
+    SW_RTN_ON_ERROR(rv);
+
+    /* PHY RX delay command, debug regigster0 bit15 */
+    data = phy_drv->phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 0);
+    if (A_TRUE == rx_delay_cmd)
+    {
+        data |= 0x8000UL;
+    }
+    else
+    {
+        data &= 0x7fffUL;
+    }
+    rv = phy_drv->phy_debug_write(dev_id, ISISC_PHY_MODE_PHY_ID, 0, data);
+    SW_RTN_ON_ERROR(rv);
+
+    /* PHY RX delay select, now hardware not support */
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+    sw_error_t rv;
+    a_uint16_t data;
+    a_uint32_t reg = 0, rgmii, port_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    /* only one PHY device support this */
+    if (ISISC_PHY_MODE_PHY_ID != phy_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+	port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id);
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get(dev_id, port_id));
+    if (NULL == phy_drv->phy_debug_read)
+	  return SW_NOT_SUPPORTED;
+
+    aos_mem_zero(config, sizeof(fal_phy_config_t));
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_RGMII_EN, rgmii, reg);
+
+    if (rgmii)
+    {
+        config->mac_mode = FAL_MAC_MODE_RGMII;
+        data = phy_drv->phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 5);
+        if (data & 0x0100)
+        {
+            config->txclk_delay_cmd = A_TRUE;
+            data = phy_drv->phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 11);
+            config->txclk_delay_sel = (data >> 5) & 0x3UL;
+        }
+        else
+        {
+            config->txclk_delay_cmd = A_FALSE;
+        }
+
+        data = phy_drv->phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 0);
+        if (data & 0x8000)
+        {
+            config->rxclk_delay_cmd = A_TRUE;
+        }
+        else
+        {
+            config->rxclk_delay_cmd = A_FALSE;
+        }
+    }
+    else
+    {
+        config->mac_mode = FAL_MAC_MODE_DEFAULT;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, FX100_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (Fx100BASE_MODE == config->link_mode)
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, LINK_CTRL, Fx100BASE_MODE, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == config->overshoot)
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, OVERSHOOT_MODE, 1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, OVERSHOOT_MODE, 0, reg);
+    }
+
+    if (A_TRUE == config->loopback)
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, LOOPBACK_MODE, 1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, LOOPBACK_MODE, 0, reg);
+    }
+
+    if (A_TRUE == config->fd_mode)
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, FD_MODE, 1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, FD_MODE, 0, reg);
+    }
+
+    if (A_TRUE == config->col_test)
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, COL_TEST, 1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, COL_TEST, 0, reg);
+    }
+
+    if (FX100_SERDS_MODE == config->sgmii_fiber_mode)
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, SGMII_FIBER, FX100_SERDS_MODE, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == config->crs_ctrl)
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, CRS_CTRL, 1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, CRS_CTRL, 0, reg);
+    }
+
+    if (A_TRUE == config->loopback_ctrl)
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, LOOPBACK_TEST, 1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, LOOPBACK_TEST, 0, reg);
+    }
+
+    if (A_TRUE == config->crs_col_100_ctrl)
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, CRS_COL_100_CTRL, 1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, CRS_COL_100_CTRL, 0, reg);
+    }
+
+    if (A_TRUE == config->loop_en)
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, FX100_LOOP_EN, 1, reg);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(FX100_CTRL, FX100_LOOP_EN, 0, reg);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, FX100_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, FX100_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(FX100_CTRL, LINK_CTRL, field, reg);
+    if (field == Fx100BASE_MODE)
+    {
+        config->link_mode = Fx100BASE_MODE;
+    }
+
+    SW_GET_FIELD_BY_REG(FX100_CTRL, OVERSHOOT_MODE, field, reg);
+    if (A_TRUE == field)
+    {
+        config->overshoot = A_TRUE;
+    }
+    else
+    {
+        config->overshoot = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(FX100_CTRL, LOOPBACK_MODE, field, reg);
+    if (A_TRUE == field)
+    {
+        config->loopback = A_TRUE;
+    }
+    else
+    {
+        config->loopback = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(FX100_CTRL, FD_MODE, field, reg);
+    config->fd_mode =field;
+
+    SW_GET_FIELD_BY_REG(FX100_CTRL, COL_TEST, field, reg);
+    if (A_TRUE == field)
+    {
+        config->col_test = A_TRUE;
+    }
+    else
+    {
+        config->col_test = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(FX100_CTRL, SGMII_FIBER, field, reg);
+    if (FX100_SERDS_MODE == field)
+    {
+        config->sgmii_fiber_mode = FX100_SERDS_MODE;
+    }
+
+    SW_GET_FIELD_BY_REG(FX100_CTRL, CRS_CTRL, field, reg);
+    if (A_TRUE == field)
+    {
+        config->crs_ctrl = A_TRUE;
+    }
+    else
+    {
+        config->crs_ctrl = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(FX100_CTRL, LOOPBACK_TEST, field, reg);
+    if (A_TRUE == field)
+    {
+        config->loopback_ctrl = A_TRUE;
+    }
+    else
+    {
+        config->loopback_ctrl = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(FX100_CTRL, CRS_COL_100_CTRL, field, reg);
+    if (A_TRUE == field)
+    {
+        config->crs_col_100_ctrl = A_TRUE;
+    }
+    else
+    {
+        config->crs_col_100_ctrl = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(FX100_CTRL, FX100_LOOP_EN, field, reg);
+    if (A_TRUE == field)
+    {
+        config->loop_en = A_TRUE;
+    }
+    else
+    {
+        config->loop_en = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, FX100_CTRL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(FX100_CTRL, FX100_STATUS, field, reg);
+
+    *status = field;
+
+    return SW_OK;
+}
+
+/**
+  * @brief Set 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_3az_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Get 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_3az_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Set interface mode on a particular MAC device.
+ * @param[in] dev_id device id
+ * @param[in] mca_id MAC device ID
+ * @param[in] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_interface_mac_mode_set(dev_id, port_id, config);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Get interface mode on a particular MAC device.
+ * @param[in] dev_id device id
+ * @param[in] mca_id MAC device ID
+ * @param[out] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_interface_mac_mode_get(dev_id, port_id, config);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Set interface phy mode on a particular PHY device.
+ * @param[in] dev_id device id
+ * @param[in] phy_id PHY device ID
+ * @param[in] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_interface_phy_mode_set(dev_id, phy_id, config);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Get interface phy mode on a particular PHY device.
+ * @param[in] dev_id device id
+ * @param[in] phy_id PHY device ID
+ * @param[out] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_interface_phy_mode_get(dev_id, phy_id, config);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+/**
+  * @brief Set fx100 control configuration.
+ * @param[in] dev_id device id
+ * @param[in] config fx100 control configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_interface_fx100_ctrl_set(dev_id, config);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Get fx100 control configuration.
+ * @param[in] dev_id device id
+ * @param[out] config fx100 control configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_interface_fx100_ctrl_get(dev_id, config);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Get fx100 status.
+ * @param[in] dev_id device id
+ * @param[out] the value of fx100 status
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_interface_fx100_status_get(dev_id, status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Set mac0 and mac6 exchange status.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_interface_mac06_exch_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+  * @brief Get mac0 and mac6 exchange status.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_interface_mac06_exch_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mac pad configuration.
+ * @param[in] dev_id device id
+ * @param[in] port_num port num
+ * @param[out] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac_pad_get(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t* value)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_interface_mac_pad_get(dev_id, port_num, value);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+/**
+ * @brief Set mac pad configuration.
+ * @param[in] dev_id device id
+ * @param[in] port_num port num
+ * @param[in] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac_pad_set(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t value)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_interface_mac_pad_set(dev_id,port_num,value);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mac SGMII configuration.
+ * @param[in] dev_id device id
+ * @param[out] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac_sgmii_get(a_uint32_t dev_id, a_uint32_t* value)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_interface_mac_sgmii_get(dev_id, value);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+/**
+ * @brief Set mac SGMII configuration.
+ * @param[in] dev_id device id
+ * @param[in] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac_sgmii_set(a_uint32_t dev_id, a_uint32_t value)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_interface_mac_sgmii_set(dev_id, value);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+sw_error_t
+isisc_interface_ctrl_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->port_3az_status_set = isisc_port_3az_status_set;
+        p_api->port_3az_status_get = isisc_port_3az_status_get;
+        p_api->interface_mac_mode_set = isisc_interface_mac_mode_set;
+        p_api->interface_mac_mode_get = isisc_interface_mac_mode_get;
+        p_api->interface_phy_mode_set = isisc_interface_phy_mode_set;
+        p_api->interface_phy_mode_get = isisc_interface_phy_mode_get;
+        p_api->interface_fx100_ctrl_set = isisc_interface_fx100_ctrl_set;
+        p_api->interface_fx100_ctrl_get = isisc_interface_fx100_ctrl_get;
+        p_api->interface_fx100_status_get = isisc_interface_fx100_status_get;
+        p_api->interface_mac06_exch_set = isisc_interface_mac06_exch_set;
+        p_api->interface_mac06_exch_get = isisc_interface_mac06_exch_get;
+	p_api->interface_mac_pad_get = isisc_interface_mac_pad_get;
+	p_api->interface_mac_pad_set = isisc_interface_mac_pad_set;
+	p_api->interface_mac_sgmii_get = isisc_interface_mac_sgmii_get;
+	p_api->interface_mac_sgmii_set = isisc_interface_mac_sgmii_set;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_ip.c b/qca-ssdk/src/hsl/isisc/isisc_ip.c
new file mode 100755
index 0000000..b8851bf
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_ip.c
@@ -0,0 +1,2555 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_ip ISISC_IP
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_ip.h"
+#include "isisc_reg.h"
+
+#define ISISC_HOST_ENTRY_DATA0_ADDR              0x0e80
+#define ISISC_HOST_ENTRY_DATA1_ADDR              0x0e84
+#define ISISC_HOST_ENTRY_DATA2_ADDR              0x0e88
+#define ISISC_HOST_ENTRY_DATA3_ADDR              0x0e8c
+#define ISISC_HOST_ENTRY_DATA4_ADDR              0x0e90
+#define ISISC_HOST_ENTRY_DATA5_ADDR              0x0e94
+#define ISISC_HOST_ENTRY_DATA6_ADDR              0x0e98
+#define ISISC_HOST_ENTRY_DATA7_ADDR              0x0e58
+
+#define ISISC_HOST_ENTRY_REG_NUM                 8
+
+#define ISISC_HOST_ENTRY_FLUSH                   1
+#define ISISC_HOST_ENTRY_ADD                     2
+#define ISISC_HOST_ENTRY_DEL                     3
+#define ISISC_HOST_ENTRY_NEXT                    4
+#define ISISC_HOST_ENTRY_SEARCH                  5
+
+#define ISISC_ENTRY_ARP                          3
+
+#define ISISC_INTF_MAC_ADDR_NUM                  8
+#define ISISC_INTF_MAC_TBL0_ADDR                 0x5a900
+#define ISISC_INTF_MAC_TBL1_ADDR                 0x5a904
+#define ISISC_INTF_MAC_TBL2_ADDR                 0x5a908
+#define ISISC_INTF_MAC_EDIT0_ADDR                0x02000
+#define ISISC_INTF_MAC_EDIT1_ADDR                0x02004
+#define ISISC_INTF_MAC_EDIT2_ADDR                0x02008
+
+#define ISISC_IP6_BASE_ADDR                      0x0470
+
+#define ISISC_HOST_ENTRY_NUM                     128
+
+#define ISISC_IP_COUTER_ADDR                     0x2b000
+
+static a_uint32_t isisc_mac_snap[SW_MAX_NR_DEV] = { 0 };
+static fal_intf_mac_entry_t isisc_intf_snap[SW_MAX_NR_DEV][ISISC_INTF_MAC_ADDR_NUM];
+
+static void
+_isisc_ip_pt_learn_save(a_uint32_t dev_id, a_uint32_t * status)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    if (SW_OK != rv)
+    {
+        return;
+    }
+
+    *status = (data & 0x7f7f);
+
+    data &= 0xffff8080;
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return;
+}
+
+static void
+_isisc_ip_pt_learn_restore(a_uint32_t dev_id, a_uint32_t status)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    if (SW_OK != rv)
+    {
+        return;
+    }
+
+    data &= 0xffff8080;
+    data |= (status & 0x7f7f);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return;
+}
+
+static sw_error_t
+_isisc_ip_feature_check(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (S17C_DEVICE_ID == entry)
+    {
+        return SW_OK;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+}
+
+static sw_error_t
+_isisc_ip_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id,
+                     a_uint32_t counter[2])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    addr = ISISC_IP_COUTER_ADDR + (cnt_id << 3);
+    for (i = 0; i < 2; i++)
+    {
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(counter[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        addr += 4;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_host_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op)
+{
+    a_uint32_t busy = 1, i = 0x100, entry = 0, j, try_num;
+    a_uint32_t learn_status = 0;
+    sw_error_t rv;
+
+    while (busy && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+                          sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry);
+    }
+
+    if (i == 0)
+    {
+        return SW_BUSY;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_BUSY, 1, entry);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_SEL, entry_type, entry);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, ENTRY_FUNC, op, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* hardware requirements, we should disable ARP learn at first */
+    /* and maybe we should try several times... */
+    _isisc_ip_pt_learn_save(dev_id, &learn_status);
+    if (learn_status)
+    {
+        try_num = 10;
+    }
+    else
+    {
+        try_num = 1;
+    }
+
+    for (j = 0; j < try_num; j++)
+    {
+        busy = 1;
+        i = 0x1000;
+        while (busy && --i)
+        {
+            HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+                              sizeof (a_uint32_t));
+            if (SW_OK != rv)
+            {
+                _isisc_ip_pt_learn_restore(dev_id, learn_status);
+                return rv;
+            }
+            SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry);
+        }
+
+        if (i == 0)
+        {
+            _isisc_ip_pt_learn_restore(dev_id, learn_status);
+            return SW_BUSY;
+        }
+
+        /* hardware requirement, we should read again... */
+        HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+                          sizeof (a_uint32_t));
+        if (SW_OK != rv)
+        {
+            _isisc_ip_pt_learn_restore(dev_id, learn_status);
+            return rv;
+        }
+
+        /* operation success...... */
+        SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, busy, entry);
+        if (busy)
+        {
+            _isisc_ip_pt_learn_restore(dev_id, learn_status);
+            return SW_OK;
+        }
+    }
+
+    _isisc_ip_pt_learn_restore(dev_id, learn_status);
+    if (ISISC_HOST_ENTRY_NEXT == op)
+    {
+        return SW_NO_MORE;
+    }
+    else if (ISISC_HOST_ENTRY_SEARCH == op)
+    {
+        return SW_NOT_FOUND;
+    }
+    else if (ISISC_HOST_ENTRY_DEL == op)
+    {
+        return SW_NOT_FOUND;
+    }
+    else
+    {
+        return SW_FAIL;
+    }
+}
+
+static sw_error_t
+_isisc_ip_intf_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry,
+                       a_uint32_t * hw_intf)
+{
+    sw_error_t rv;
+    a_uint32_t addr, lvid, hvid, tbl[3] = {0}, i;
+    a_uint32_t sw_intf = entry->intf_id;
+    a_uint32_t vid_offset;
+
+    for (i = 0; i < ISISC_INTF_MAC_ADDR_NUM; i++)
+    {
+        if (isisc_mac_snap[dev_id] & (0x1 << i))
+        {
+            addr = ISISC_INTF_MAC_TBL0_ADDR + (i << 4) + 4;
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[1])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            addr = ISISC_INTF_MAC_TBL0_ADDR + (i << 4) + 8;
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[2])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, hvid, tbl[1]);
+            SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, lvid, tbl[2]);
+            hvid |= ((lvid & 0xff) << 4);
+
+            SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl[1]);
+
+            if ((lvid <= sw_intf) && (hvid >= sw_intf))
+            {
+                vid_offset = entry->expect_vid ? (entry->expect_vid - lvid) : (sw_intf - lvid);
+                *hw_intf = (vid_offset << 3) | i;
+                return SW_OK;
+            }
+        }
+    }
+
+    return SW_BAD_PARAM;
+}
+
+static sw_error_t
+_isisc_ip_intf_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_intf,
+                       a_uint32_t * sw_intf)
+{
+    sw_error_t rv;
+    a_uint32_t addr, lvid, tbl = 0, i;
+
+    i = hw_intf & 0x7;
+
+    addr = ISISC_INTF_MAC_TBL0_ADDR + (i << 4) + 4;
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&tbl), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl);
+    *sw_intf = lvid + (hw_intf >> 3);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    if (255 < ((*time + 5) / 6))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = ((*time + 5) / 6);
+    *time = data * 6;
+
+    HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *time = data * 6;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_host_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry,
+                    a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    if (FAL_IP_IP4_ADDR & entry->flags)
+    {
+        reg[0] = entry->ip4_addr;
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 0, reg[6]);
+    }
+
+    if (FAL_IP_IP6_ADDR & entry->flags)
+    {
+        reg[0] = entry->ip6_addr.ul[3];
+        reg[1] = entry->ip6_addr.ul[2];
+        reg[2] = entry->ip6_addr.ul[1];
+        reg[3] = entry->ip6_addr.ul[0];
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 1, reg[6]);
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR2, entry->mac_addr.uc[2], reg[4]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR3, entry->mac_addr.uc[3], reg[4]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR4, entry->mac_addr.uc[4], reg[4]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR5, entry->mac_addr.uc[5], reg[4]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY5, MAC_ADDR0, entry->mac_addr.uc[0], reg[5]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY5, MAC_ADDR1, entry->mac_addr.uc[1], reg[5]);
+
+    rv = _isisc_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data);
+
+    SW_RTN_ON_ERROR(rv);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY5, INTF_ID, data, reg[5]);
+
+#if 0
+    if (A_TRUE != hsl_port_prop_check(dev_id, entry->port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+#endif
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]);
+
+    if (FAL_IP_CPU_ADDR & entry->flags)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY5, CPU_ADDR, 1, reg[5]);
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]);
+
+    if ((A_TRUE == entry->mirror_en) && (FAL_MAC_FRWRD != entry->action))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->counter_en)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_EN, 1, reg[6]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_IDX, entry->counter_id, reg[6]);
+    }
+
+    if (FAL_MAC_DROP == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, 7, reg[5]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 3, reg[6]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 1, reg[6]);
+    }
+    else if (FAL_MAC_CPY_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 2, reg[6]);
+    }
+    else
+    {
+        if (A_TRUE == entry->mirror_en)
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 0, reg[6]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 3, reg[6]);
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_host_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[],
+                    fal_host_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, cnt[2] = {0};
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY6, IP_VER, data, reg[6]);
+    if (data)
+    {
+        entry->ip6_addr.ul[0] = reg[3];
+        entry->ip6_addr.ul[1] = reg[2];
+        entry->ip6_addr.ul[2] = reg[1];
+        entry->ip6_addr.ul[3] = reg[0];
+        entry->flags |= FAL_IP_IP6_ADDR;
+    }
+    else
+    {
+        entry->ip4_addr = reg[0];
+        entry->flags |= FAL_IP_IP4_ADDR;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR2, entry->mac_addr.uc[2], reg[4]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR3, entry->mac_addr.uc[3], reg[4]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR4, entry->mac_addr.uc[4], reg[4]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR5, entry->mac_addr.uc[5], reg[4]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY5, MAC_ADDR0, entry->mac_addr.uc[0], reg[5]);
+    SW_GET_FIELD_BY_REG(HOST_ENTRY5, MAC_ADDR1, entry->mac_addr.uc[1], reg[5]);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY5, INTF_ID, data, reg[5]);
+    rv = _isisc_ip_intf_hw_to_sw(dev_id, data, &(entry->intf_id));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY5, CPU_ADDR, data, reg[5]);
+    if (data)
+    {
+        entry->flags |= FAL_IP_CPU_ADDR;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY6, CNT_EN, data, reg[6]);
+    if (data)
+    {
+        entry->counter_en = A_TRUE;
+        SW_GET_FIELD_BY_REG(HOST_ENTRY6, CNT_IDX, entry->counter_id, reg[6]);
+
+        rv = _isisc_ip_counter_get(dev_id, entry->counter_id, cnt);
+        SW_RTN_ON_ERROR(rv);
+
+        entry->packet = cnt[0];
+        entry->byte = cnt[1];
+    }
+    else
+    {
+        entry->counter_en = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY6, PPPOE_EN, data, reg[6]);
+    if (data)
+    {
+        entry->pppoe_en = A_TRUE;
+        SW_GET_FIELD_BY_REG(HOST_ENTRY6, PPPOE_IDX, data, reg[6]);
+        entry->pppoe_id = data;
+    }
+    else
+    {
+        entry->pppoe_en = A_FALSE;
+    }
+
+    if (7 == entry->port_id)
+    {
+        entry->port_id = 0;
+        entry->action = FAL_MAC_DROP;
+    }
+    else
+    {
+        SW_GET_FIELD_BY_REG(HOST_ENTRY6, ACTION, data, reg[6]);
+        entry->action = FAL_MAC_FRWRD;
+        if (0 == data)
+        {
+            entry->mirror_en = A_TRUE;
+        }
+        else if (1 == data)
+        {
+            entry->action = FAL_MAC_RDT_TO_CPU;
+        }
+        else if (2 == data)
+        {
+            entry->action = FAL_MAC_CPY_TO_CPU;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_host_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    for (i = 0; i < ISISC_HOST_ENTRY_REG_NUM; i++)
+    {
+        if((ISISC_HOST_ENTRY_REG_NUM - 1) == i)
+        {
+            addr = ISISC_HOST_ENTRY_DATA7_ADDR;
+        }
+        else
+        {
+            addr = ISISC_HOST_ENTRY_DATA0_ADDR + (i << 2);
+        }
+
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&reg[i]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_host_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    for (i = 0; i < ISISC_HOST_ENTRY_REG_NUM; i++)
+    {
+        if((ISISC_HOST_ENTRY_REG_NUM - 1) == i)
+        {
+            addr = ISISC_HOST_ENTRY_DATA7_ADDR;
+        }
+        else
+        {
+            addr = ISISC_HOST_ENTRY_DATA0_ADDR + (i << 2);
+        }
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&reg[i]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_ADD);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&reg[7]),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                  fal_host_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, op = ISISC_HOST_ENTRY_FLUSH;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_IP_ENTRY_ID_EN & del_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_IP_ENTRY_IPADDR_EN & del_mode)
+    {
+        op = ISISC_HOST_ENTRY_DEL;
+        if (FAL_IP_IP4_ADDR & entry->flags)
+        {
+            reg[0] = entry->ip4_addr;
+        }
+
+        if (FAL_IP_IP6_ADDR & entry->flags)
+        {
+            reg[0] = entry->ip6_addr.ul[3];
+            reg[1] = entry->ip6_addr.ul[2];
+            reg[2] = entry->ip6_addr.ul[1];
+            reg[3] = entry->ip6_addr.ul[0];
+            SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 1, reg[6]);
+        }
+    }
+
+    if (FAL_IP_ENTRY_INTF_EN & del_mode)
+    {
+        rv = _isisc_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data);
+        SW_RTN_ON_ERROR(rv);
+
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_VID, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY5, INTF_ID, data, reg[5]);
+    }
+
+    if (FAL_IP_ENTRY_PORT_EN & del_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SP, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]);
+    }
+
+    if (FAL_IP_ENTRY_STATUS_EN & del_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]);
+    }
+
+    rv = _isisc_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, op);
+    return rv;
+}
+
+static sw_error_t
+_isisc_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                  fal_host_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_IP_ENTRY_IPADDR_EN != get_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_IP_IP4_ADDR & entry->flags)
+    {
+        reg[0] = entry->ip4_addr;
+    }
+    else
+    {
+        reg[0] = entry->ip6_addr.ul[3];
+        reg[1] = entry->ip6_addr.ul[2];
+        reg[2] = entry->ip6_addr.ul[1];
+        reg[3] = entry->ip6_addr.ul[0];
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 1, reg[6]);
+    }
+
+    rv = _isisc_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP,
+                                 ISISC_HOST_ENTRY_SEARCH);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    aos_mem_zero(entry, sizeof (fal_host_entry_t));
+
+    rv = _isisc_host_hw_to_sw(dev_id, reg, entry);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!(entry->status))
+    {
+        return SW_NOT_FOUND;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&reg[7]),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                   fal_host_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t idx, data, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id)
+    {
+        idx = ISISC_HOST_ENTRY_NUM - 1;
+    }
+    else
+    {
+        if ((ISISC_HOST_ENTRY_NUM - 1) == entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = entry->entry_id;
+        }
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, idx, reg[7]);
+
+    if (FAL_IP_ENTRY_INTF_EN & next_mode)
+    {
+        rv = _isisc_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data);
+        SW_RTN_ON_ERROR(rv);
+
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_VID, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY5, INTF_ID, data, reg[5]);
+    }
+
+    if (FAL_IP_ENTRY_PORT_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SP, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]);
+    }
+
+    if (FAL_IP_ENTRY_STATUS_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]);
+    }
+
+    rv = _isisc_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_NEXT);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    aos_mem_zero(entry, sizeof (fal_host_entry_t));
+
+    rv = _isisc_host_hw_to_sw(dev_id, reg, entry);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!(entry->status))
+    {
+        return SW_NO_MORE;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                           a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, tbl[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    tbl_idx = (entry_id - 1) & 0x7f;
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+
+    rv = _isisc_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_NEXT);
+    if (SW_OK != rv)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    rv = _isisc_host_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+    if (entry_id != tbl_idx)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    tbl[0] = reg[0];
+    tbl[1] = reg[1];
+    tbl[2] = reg[2];
+    tbl[3] = reg[3];
+    tbl[6] = (reg[6] >> 15) << 15;
+    rv = _isisc_host_down_to_hw(dev_id, tbl);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_DEL);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_EN, 0, reg[6]);
+    }
+    else if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_EN, 1, reg[6]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_IDX, cnt_id, reg[6]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    reg[7] = 0x0;
+    rv = _isisc_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_ADD);
+    return rv;
+}
+
+static sw_error_t
+_isisc_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                         a_uint32_t pppoe_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, tbl[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    tbl_idx = (entry_id - 1) & 0x7f;
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+
+    rv = _isisc_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_NEXT);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_up_to_sw(dev_id, reg);
+    if (SW_OK != rv)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+    if (entry_id != tbl_idx)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, PPPOE_EN, 0, reg[6]);
+    }
+    else if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, PPPOE_EN, 1, reg[6]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY6, PPPOE_IDX, pppoe_id, reg[6]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    tbl[0] = reg[0];
+    tbl[1] = reg[1];
+    tbl[2] = reg[2];
+    tbl[3] = reg[3];
+    tbl[6] = (reg[6] >> 15) << 15;
+    rv = _isisc_host_down_to_hw(dev_id, tbl);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_DEL);
+    SW_RTN_ON_ERROR(rv);
+
+    reg[7] = 0x0;
+    rv = _isisc_host_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_ADD);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t flags)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_ARP_LEARN_REQ & flags)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        data &= (~(0x1 << port_id));
+    }
+
+    if (FAL_ARP_LEARN_ACK & flags)
+    {
+        data |= (0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id));
+    }
+    else
+    {
+        data &= (~(0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id)));
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * flags)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *flags = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data & (0x1 << port_id))
+    {
+        *flags |= FAL_ARP_LEARN_REQ;
+    }
+
+    if (data & (0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id)))
+    {
+        *flags |= FAL_ARP_LEARN_ACK;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_ARP_LEARN_ALL == mode)
+    {
+        data = 1;
+    }
+    else if (FAL_ARP_LEARN_LOCAL == mode)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *mode = FAL_ARP_LEARN_ALL;
+    }
+    else
+    {
+        *mode = FAL_ARP_LEARN_LOCAL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NO_SOURCE_GUARD < mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = 0;
+    if (FAL_MAC_IP_GUARD == mode)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_IP_PORT_GUARD == mode)
+    {
+        data = 2;
+    }
+    else if (FAL_MAC_IP_VLAN_GUARD == mode)
+    {
+        data = 3;
+    }
+    else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode)
+    {
+        data = 4;
+    }
+    reg &= (~(0x7 << (port_id * 3)));
+    reg |= ((data & 0x7) << (port_id * 3));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL1, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = 1;
+    if (FAL_NO_SOURCE_GUARD == mode)
+    {
+        data = 0;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, SP_CHECK_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (reg >> (port_id * 3)) & 0x7;
+
+    *mode = FAL_NO_SOURCE_GUARD;
+    if (1 == data)
+    {
+        *mode = FAL_MAC_IP_GUARD;
+    }
+    else if (2 == data)
+    {
+        *mode = FAL_MAC_IP_PORT_GUARD;
+    }
+    else if (3 == data)
+    {
+        *mode = FAL_MAC_IP_VLAN_GUARD;
+    }
+    else if (4 == data)
+    {
+        *mode = FAL_MAC_IP_PORT_VLAN_GUARD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        data = 0;
+    }
+    else if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 2;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        *cmd = FAL_MAC_FRWRD;
+    }
+    else if (1 == data)
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NO_SOURCE_GUARD < mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = 0;
+    if (FAL_MAC_IP_GUARD == mode)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_IP_PORT_GUARD == mode)
+    {
+        data = 2;
+    }
+    else if (FAL_MAC_IP_VLAN_GUARD == mode)
+    {
+        data = 3;
+    }
+    else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode)
+    {
+        data = 4;
+    }
+    reg &= (~(0x7 << (port_id * 3)));
+    reg |= ((data & 0x7) << (port_id * 3));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (reg >> (port_id * 3)) & 0x7;
+
+    *mode = FAL_NO_SOURCE_GUARD;
+    if (1 == data)
+    {
+        *mode = FAL_MAC_IP_GUARD;
+    }
+    else if (2 == data)
+    {
+        *mode = FAL_MAC_IP_PORT_GUARD;
+    }
+    else if (3 == data)
+    {
+        *mode = FAL_MAC_IP_VLAN_GUARD;
+    }
+    else if (4 == data)
+    {
+        *mode = FAL_MAC_IP_PORT_VLAN_GUARD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        data = 0;
+    }
+    else if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 2;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        *cmd = FAL_MAC_FRWRD;
+    }
+    else if (1 == data)
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, L3_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t route_en = 0, l3_en = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN,
+                      (a_uint8_t *) (&route_en), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, L3_EN,
+                      (a_uint8_t *) (&l3_en), sizeof (a_uint32_t))
+    SW_RTN_ON_ERROR(rv);
+
+    if (route_en && l3_en)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, j, found = 0, addr, tbl[3] = { 0 };
+    fal_intf_mac_entry_t * intf_entry = NULL;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < ISISC_INTF_MAC_ADDR_NUM; i++)
+    {
+        if (isisc_mac_snap[dev_id] & (0x1 << i))
+        {
+            intf_entry = &(isisc_intf_snap[dev_id][i]);
+            if ((entry->vid_low == intf_entry->vid_low)
+                    && (entry->vid_high == intf_entry->vid_high))
+            {
+                /* all same, return OK directly */
+                if (!aos_mem_cmp(intf_entry, entry, sizeof(fal_intf_mac_entry_t)))
+                {
+                    return SW_OK;
+                }
+                else
+                {
+                    /* update entry */
+                    found = 1;
+                    break;
+                }
+            }
+            else
+            {
+                /* entry VID cross border, not support */
+                if ((entry->vid_low >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high))
+                {
+                    return SW_BAD_PARAM;
+                }
+
+                /* entry VID cross border, not support */
+                if ((entry->vid_high >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high))
+                {
+                    return SW_BAD_PARAM;
+                }
+            }
+        }
+    }
+
+    if (!found)
+    {
+        for (i = 0; i < ISISC_INTF_MAC_ADDR_NUM; i++)
+        {
+            if (!(isisc_mac_snap[dev_id] & (0x1 << i)))
+            {
+                intf_entry = &(isisc_intf_snap[dev_id][i]);
+                break;
+            }
+        }
+    }
+
+    if (ISISC_INTF_MAC_ADDR_NUM == i)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    if ((A_FALSE == entry->ip4_route) && (A_FALSE == entry->ip6_route))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (512 <= (entry->vid_high - entry->vid_low))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2],
+                        tbl[0]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3],
+                        tbl[0]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4],
+                        tbl[0]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5],
+                        tbl[0]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0],
+                        tbl[1]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1],
+                        tbl[1]);
+
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_HIGH0, (entry->vid_high & 0xf),
+                        tbl[1]);
+    SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, VID_HIGH1, (entry->vid_high >> 4),
+                        tbl[2]);
+
+    if (A_TRUE == entry->ip4_route)
+    {
+        SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP4_ROUTE, 1, tbl[2]);
+    }
+
+    if (A_TRUE == entry->ip6_route)
+    {
+        SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP6_ROUTE, 1, tbl[2]);
+    }
+
+    for (j = 0; j < 2; j++)
+    {
+        addr = ISISC_INTF_MAC_EDIT0_ADDR + (i << 4) + (j << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    for (j = 0; j < 3; j++)
+    {
+        addr = ISISC_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    isisc_mac_snap[dev_id] |= (0x1 << i);
+    *intf_entry = *entry;
+    entry->entry_id = i;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                        fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t addr, tbl[3] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!(FAL_IP_ENTRY_ID_EN & del_mode))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (ISISC_INTF_MAC_ADDR_NUM <= entry->entry_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    /* clear valid bits */
+    addr = ISISC_INTF_MAC_TBL2_ADDR + (entry->entry_id << 4);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    isisc_mac_snap[dev_id] &= (~(0x1 << entry->entry_id));
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                         fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, j, idx, addr, tbl[3] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id)
+    {
+        idx = 0;
+    }
+    else
+    {
+        if ((ISISC_INTF_MAC_ADDR_NUM - 1) == entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = entry->entry_id + 1;
+        }
+    }
+
+    for (i = idx; i < ISISC_INTF_MAC_ADDR_NUM; i++)
+    {
+        if (isisc_mac_snap[dev_id] & (0x1 << i))
+        {
+            break;
+        }
+    }
+
+    if (ISISC_INTF_MAC_ADDR_NUM == i)
+    {
+        return SW_NO_MORE;
+    }
+
+    for (j = 0; j < 3; j++)
+    {
+        addr = ISISC_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    aos_mem_zero(entry, sizeof (fal_intf_mac_entry_t));
+
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2],
+                        tbl[0]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3],
+                        tbl[0]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4],
+                        tbl[0]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5],
+                        tbl[0]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0],
+                        tbl[1]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1],
+                        tbl[1]);
+
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]);
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, j, tbl[1]);
+    entry->vid_high = j & 0xf;
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, j, tbl[2]);
+    entry->vid_high |= ((j & 0xff) << 4);
+
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP4_ROUTE, j, tbl[2]);
+    if (j)
+    {
+        entry->ip4_route = A_TRUE;
+    }
+
+    SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP6_ROUTE, j, tbl[2]);
+    if (j)
+    {
+        entry->ip6_route = A_TRUE;
+    }
+
+    entry->entry_id = i;
+    return SW_OK;
+}
+
+#define ISISC_WCMP_ENTRY_MAX_ID    3
+#define ISISC_WCMP_HASH_MAX_NUM    16
+#define ISISC_IP_ENTRY_MAX_ID      127
+
+#define ISISC_WCMP_HASH_TBL_ADDR   0x0e10
+#define ISISC_WCMP_NHOP_TBL_ADDR   0x0e20
+
+#if 0
+static sw_error_t
+_isisc_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+    sw_error_t rv;
+    a_uint32_t i, j, addr, data;
+    a_uint8_t  idx, ptr[4] = { 0 }, pos[16] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (ISISC_WCMP_ENTRY_MAX_ID < wcmp_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISISC_WCMP_HASH_MAX_NUM < wcmp->nh_nr)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = 0; i < wcmp->nh_nr; i++)
+    {
+        if (ISISC_IP_ENTRY_MAX_ID < wcmp->nh_id[i])
+        {
+            return SW_BAD_PARAM;
+        }
+
+        idx = 4;
+        for (j = 0; j < 4; j++)
+        {
+            if (ptr[j] & 0x80)
+            {
+                if ((ptr[j] & 0x7f) == wcmp->nh_id[i])
+                {
+                    idx = j;
+                    break;
+                }
+            }
+            else
+            {
+                idx = j;
+            }
+        }
+
+        if (4 == idx)
+        {
+            return SW_BAD_PARAM;
+        }
+        else
+        {
+            ptr[idx] = (wcmp->nh_id[i] & 0x7f) | 0x80;
+            pos[i]   = idx;
+        }
+    }
+
+    data = 0;
+    for (j = 0; j < 4; j++)
+    {
+        data |= (ptr[j] << (j << 3));
+    }
+
+    addr = ISISC_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = 0;
+    for (j = 0; j < 16; j++)
+    {
+        data |= (pos[j] << (j << 1));
+    }
+
+    addr = ISISC_WCMP_HASH_TBL_ADDR + (wcmp_id << 2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+    sw_error_t rv;
+    a_uint32_t i, addr, data = 0;
+    a_uint8_t  ptr[4] = { 0 }, pos[16] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (ISISC_WCMP_ENTRY_MAX_ID < wcmp_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    wcmp->nh_nr = ISISC_WCMP_HASH_MAX_NUM;
+
+    addr = ISISC_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < 4; i++)
+    {
+        ptr[i] = (data >> (i << 3)) & 0x7f;
+    }
+
+    addr = ISISC_WCMP_HASH_TBL_ADDR + (wcmp_id << 2);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < 16; i++)
+    {
+        pos[i] = (data >> (i << 1)) & 0x3;
+    }
+
+    for (i = 0; i < 16; i++)
+    {
+        wcmp->nh_id[i] = ptr[pos[i]];
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isisc_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_WCMP_HASH_KEY_SIP & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 0, data);
+    }
+
+    if (FAL_WCMP_HASH_KEY_DIP & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 0, data);
+    }
+
+    if (FAL_WCMP_HASH_KEY_SPORT & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 0, data);
+    }
+
+    if (FAL_WCMP_HASH_KEY_DPORT & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 0, data);
+    }
+
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_CTRL, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, field;
+
+    *hash_mode = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SIP, field, data);
+    if (field)
+    {
+        *hash_mode |= FAL_WCMP_HASH_KEY_SIP;
+    }
+
+    SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DIP, field, data);
+    if (field)
+    {
+        *hash_mode |= FAL_WCMP_HASH_KEY_DIP;
+    }
+
+    SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SP, field, data);
+    if (field)
+    {
+        *hash_mode |= FAL_WCMP_HASH_KEY_SPORT;
+    }
+
+    SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DP, field, data);
+    if (field)
+    {
+        *hash_mode |= FAL_WCMP_HASH_KEY_DPORT;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+isisc_ip_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t i, addr, data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_ip_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_FLUSH);
+    SW_RTN_ON_ERROR(rv);
+
+    isisc_mac_snap[dev_id] = 0;
+    for (i = 0; i < ISISC_INTF_MAC_ADDR_NUM; i++)
+    {
+        addr = ISISC_INTF_MAC_TBL2_ADDR + (i << 4);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Add one host entry to one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry added related interface entry and ip6 base address
+       must be set at first.
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_host_add(dev_id, host_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one host entry from one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry deleted related interface entry and ip6 base address
+       must be set atfirst.
+       For del_mode please refer IP entry operation flags.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operation mode
+ * @param[in] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                 fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_host_del(dev_id, del_mode, host_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get one host entry from one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry deleted related interface entry and ip6 base address
+       must be set atfirst.
+       For get_mode please refer IP entry operation flags.
+ * @param[in] dev_id device id
+ * @param[in] get_mode get operation mode
+ * @param[out] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+                 fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_host_get(dev_id, get_mode, host_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next one host entry from one particular device.
+ *   @details Comments:
+ *     For ISIS the intf_id parameter in host_entry means vlan id.
+       Before host entry deleted related interface entry and ip6 base address
+       must be set atfirst.
+       For next_mode please refer IP entry operation flags.
+       For get the first entry please set entry id as FAL_NEXT_ENTRY_FIRST_ID
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operation mode
+ * @param[out] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                  fal_host_entry_t * host_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_host_next(dev_id, next_mode, host_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one host entry on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id host entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE means bind, A_FALSE means unbind
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                          a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_host_counter_bind(dev_id, entry_id, cnt_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one pppoe session entry to one host entry on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id host entry id
+ * @param[in] pppoe_id pppoe session entry id
+ * @param[in] enable A_TRUE means bind, A_FALSE means unbind
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                        a_uint32_t pppoe_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_host_pppoe_bind(dev_id, entry_id, pppoe_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets type to learn on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t flags)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_pt_arp_learn_set(dev_id, port_id, flags);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets type to learn on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t * flags)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_pt_arp_learn_get(dev_id, port_id, flags);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets type to learn on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode learning mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_arp_learn_set(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets type to learn on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode learning mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_arp_learn_get(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ip packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_source_guard_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ip packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_source_guard_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set unkonw source ip packets forwarding command on one particular device.
+ *   @details Comments:
+ *     This settin is no meaning when ip source guard not enable
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_unk_source_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unkonw source ip packets forwarding command on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_unk_source_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_source_guard_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_arp_guard_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_source_guard_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_arp_guard_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set unkonw source arp packets forwarding command on one particular device.
+ *   @details Comments:
+ *     This settin is no meaning when arp source guard not enable
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_arp_unk_source_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unkonw source arp packets forwarding command on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_arp_unk_source_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP unicast routing status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_route_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP unicast routing status on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_route_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one interface entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry interface entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_intf_entry_add(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one interface entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operation mode
+ * @param[in] entry interface entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                       fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_intf_entry_del(dev_id, del_mode, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next one interface entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operation mode
+ * @param[out] entry interface entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                        fal_intf_mac_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_intf_entry_next(dev_id, next_mode, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP host entry aging time on one particular device.
+ * @details   Comments:
+ *       This operation will set dynamic entry aging time on a particular device.
+ *       The unit of time is second. Because different device has differnet
+ *       hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param[in] time aging time
+ * @param[out] time actual aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_age_time_set(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP host entry aging time on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_age_time_get(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#if 0
+/**
+ * @brief Set IP WCMP table one particular device.
+ *   @details Comments:
+ *     Hardware only support 0 - 15 hash values and 4 different host tables.
+ * @param[in] dev_id device id
+ * @param[in] wcmp_id wcmp entry id
+ * @param[in] wcmp wcmp entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_wcmp_entry_set(dev_id, wcmp_id, wcmp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP WCMP table one particular device.
+ *   @details Comments:
+ *     Hardware only support 0 - 15 hash values and 4 different host tables.
+ * @param[in] dev_id device id
+ * @param[in] wcmp_id wcmp entry id
+ * @param[out] wcmp wcmp entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_wcmp_entry_get(dev_id, wcmp_id, wcmp);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set IP WCMP hash key mode.
+ * @param[in] dev_id device id
+ * @param[in] hash_mode hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_wcmp_hash_mode_set(dev_id, hash_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP WCMP hash key mode.
+ * @param[in] dev_id device id
+ * @param[out] hash_mode hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ip_wcmp_hash_mode_get(dev_id, hash_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isisc_ip_init(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = isisc_ip_reset(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->ip_host_add = isisc_ip_host_add;
+        p_api->ip_host_del = isisc_ip_host_del;
+        p_api->ip_host_get = isisc_ip_host_get;
+        p_api->ip_host_next = isisc_ip_host_next;
+        p_api->ip_host_counter_bind = isisc_ip_host_counter_bind;
+        p_api->ip_host_pppoe_bind = isisc_ip_host_pppoe_bind;
+        p_api->ip_pt_arp_learn_set = isisc_ip_pt_arp_learn_set;
+        p_api->ip_pt_arp_learn_get = isisc_ip_pt_arp_learn_get;
+        p_api->ip_arp_learn_set = isisc_ip_arp_learn_set;
+        p_api->ip_arp_learn_get = isisc_ip_arp_learn_get;
+        p_api->ip_source_guard_set = isisc_ip_source_guard_set;
+        p_api->ip_source_guard_get = isisc_ip_source_guard_get;
+        p_api->ip_unk_source_cmd_set = isisc_ip_unk_source_cmd_set;
+        p_api->ip_unk_source_cmd_get = isisc_ip_unk_source_cmd_get;
+        p_api->ip_arp_guard_set = isisc_ip_arp_guard_set;
+        p_api->ip_arp_guard_get = isisc_ip_arp_guard_get;
+        p_api->arp_unk_source_cmd_set = isisc_arp_unk_source_cmd_set;
+        p_api->arp_unk_source_cmd_get = isisc_arp_unk_source_cmd_get;
+        p_api->ip_route_status_set = isisc_ip_route_status_set;
+        p_api->ip_route_status_get = isisc_ip_route_status_get;
+        p_api->ip_intf_entry_add = isisc_ip_intf_entry_add;
+        p_api->ip_intf_entry_del = isisc_ip_intf_entry_del;
+        p_api->ip_intf_entry_next = isisc_ip_intf_entry_next;
+        p_api->ip_age_time_set = isisc_ip_age_time_set;
+        p_api->ip_age_time_get = isisc_ip_age_time_get;
+        p_api->ip_wcmp_hash_mode_set = isisc_ip_wcmp_hash_mode_set;
+        p_api->ip_wcmp_hash_mode_get = isisc_ip_wcmp_hash_mode_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_leaky.c b/qca-ssdk/src/hsl/isisc/isisc_leaky.c
new file mode 100755
index 0000000..14a3dda
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_leaky.c
@@ -0,0 +1,526 @@
+/*
+ * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_leaky ISISC_LEAKY
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_leaky.h"
+#include "isisc_reg.h"
+
+static sw_error_t
+_isisc_uc_leaky_mode_set(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+    {
+        data = 0;
+    }
+    else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_uc_leaky_mode_get(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+    }
+    else
+    {
+        *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_mc_leaky_mode_set(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+    {
+        data = 0;
+    }
+    else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_mc_leaky_mode_get(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+    }
+    else
+    {
+        *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+* @brief Set unicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isisc_uc_leaky_mode_set(a_uint32_t dev_id,
+                       fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_uc_leaky_mode_set(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_uc_leaky_mode_get(a_uint32_t dev_id,
+                       fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_uc_leaky_mode_get(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Set multicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isisc_mc_leaky_mode_set(a_uint32_t dev_id,
+                       fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_mc_leaky_mode_set(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mc_leaky_mode_get(a_uint32_t dev_id,
+                       fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_mc_leaky_mode_get(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_arp_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_arp_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_uc_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_uc_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_mc_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_mc_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isisc_leaky_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->uc_leaky_mode_set = isisc_uc_leaky_mode_set;
+        p_api->uc_leaky_mode_get = isisc_uc_leaky_mode_get;
+        p_api->mc_leaky_mode_set = isisc_mc_leaky_mode_set;
+        p_api->mc_leaky_mode_get = isisc_mc_leaky_mode_get;
+        p_api->port_arp_leaky_set = isisc_port_arp_leaky_set;
+        p_api->port_arp_leaky_get = isisc_port_arp_leaky_get;
+        p_api->port_uc_leaky_set = isisc_port_uc_leaky_set;
+        p_api->port_uc_leaky_get = isisc_port_uc_leaky_get;
+        p_api->port_mc_leaky_set = isisc_port_mc_leaky_set;
+        p_api->port_mc_leaky_get = isisc_port_mc_leaky_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_led.c b/qca-ssdk/src/hsl/isisc/isisc_led.c
new file mode 100755
index 0000000..fd3aebc
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_led.c
@@ -0,0 +1,405 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_led ISISC_LED
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "isisc_led.h"
+#include "isisc_reg.h"
+
+#define MAX_LED_PATTERN_ID   2
+#define LED_PATTERN_ADDR     0x50
+
+static sw_error_t
+_isisc_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                           led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    a_uint32_t data = 0, reg, mode;
+    a_uint32_t addr;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (id > MAX_LED_PATTERN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    addr = LED_PATTERN_ADDR + (id << 2);
+
+    if (LED_ALWAYS_OFF == pattern->mode)
+    {
+        mode = 0;
+    }
+    else if (LED_ALWAYS_BLINK == pattern->mode)
+    {
+        mode = 1;
+    }
+    else if (LED_ALWAYS_ON == pattern->mode)
+    {
+        mode = 2;
+    }
+    else if (LED_PATTERN_MAP_EN == pattern->mode)
+    {
+        mode = 3;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data);
+
+    if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << POWER_ON_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_1000M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_100M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_10M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << COLLISION_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINKUP_OVERRIDE_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data);
+    }
+
+    if (LED_BLINK_2HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data);
+    }
+    else if (LED_BLINK_4HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data);
+    }
+    else if (LED_BLINK_8HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data);
+    }
+    else if (LED_BLINK_TXRX == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_WAN_PORT_GROUP == group)
+    {
+        reg &= 0xffff;
+        reg |= (data << 16);
+    }
+    else
+    {
+        reg &= 0xffff0000;
+        reg |= data;
+    }
+
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_WAN_PORT_GROUP == group)
+    {
+        return SW_OK;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_LAN_PORT_GROUP == group)
+    {
+        if (0 == id)
+        {
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data);
+        }
+        else if (1 == id)
+        {
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P3L2_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P2L2_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P1L2_MODE, mode, data);
+        }
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                           led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    a_uint32_t data = 0, reg = 0, tmp;
+    a_uint32_t addr;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (id > MAX_LED_PATTERN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t));
+
+    addr = LED_PATTERN_ADDR + (id << 2);
+
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_WAN_PORT_GROUP == group)
+    {
+        data = (reg >> 16) & 0xffff;
+    }
+    else
+    {
+        data = reg & 0xffff;
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data);
+    if (0 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_OFF;
+    }
+    else if (1 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_BLINK;
+    }
+    else if (2 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_ON;
+    }
+    else
+    {
+        pattern->mode = LED_PATTERN_MAP_EN;
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << POWER_ON_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_1000M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_100M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_10M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << COLLISION_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << RX_TRAFFIC_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << TX_TRAFFIC_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINKUP_OVERRIDE_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data);
+    if (0 == tmp)
+    {
+        pattern->freq = LED_BLINK_2HZ;
+    }
+    else if (1 == tmp)
+    {
+        pattern->freq = LED_BLINK_4HZ;
+    }
+    else if (2 == tmp)
+    {
+        pattern->freq = LED_BLINK_8HZ;
+    }
+    else
+    {
+        pattern->freq = LED_BLINK_TXRX;
+    }
+
+    return SW_OK;
+}
+
+/**
+* @brief Set led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group  pattern group, lan or wan
+* @param[in] id pattern id
+* @param[in] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isisc_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                          led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_led_ctrl_pattern_set(dev_id, group, id, pattern);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Get led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group  pattern group, lan or wan
+* @param[in] id pattern id
+* @param[out] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isisc_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                          led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_led_ctrl_pattern_get(dev_id, group, id, pattern);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isisc_led_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->led_ctrl_pattern_set = isisc_led_ctrl_pattern_set;
+        p_api->led_ctrl_pattern_get = isisc_led_ctrl_pattern_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_mib.c b/qca-ssdk/src/hsl/isisc/isisc_mib.c
new file mode 100755
index 0000000..5ca5def
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_mib.c
@@ -0,0 +1,860 @@
+/*
+ * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_mib ISISC_MIB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_mib.h"
+#include "isisc_reg.h"
+
+
+#define MIB_FLUSH_ALL_PORTS          0x1
+#define MIB_FLUSH_ONE_PORT           0x2
+#define MIB_AUTOCAST_ALL_PORTS   0x3
+
+static sw_error_t
+_isisc_mib_op_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    a_uint32_t mib_busy = 1, i = 0x1000, val;
+    sw_error_t rv;
+
+    while (mib_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY,
+                          (a_uint8_t *) (&mib_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_BUSY;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_FUNC, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_FUN, op, val);
+    SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_BUSY, 1, val);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, MIB_FUNC, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    mib_busy = 1;
+    i = 0x1000;
+    while (mib_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY,
+                          (a_uint8_t *) (&mib_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_FAIL;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                   fal_mib_info_t * mib_info)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFcsErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxAllignErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxRunt = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFragment = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxTooLong = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxOverFlow = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Filtered = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxUnderRun = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxOverSize = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxCollision = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxAbortCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMultiCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxSingalCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxExcDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxLateCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXUNICAST, port_id,
+                      (a_uint8_t *) (&val), sizeof
+                      (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxUniCast = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNICAST, port_id,
+                      (a_uint8_t *) (&val), sizeof
+                      (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxUniCast = val;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                   fal_mib_info_t * mib_info)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFcsErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxAllignErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxRunt = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFragment = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxTooLong = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxOverFlow = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Filtered = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXUNICAST, port_id,
+                      (a_uint8_t *) (&val), sizeof
+                      (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxUniCast = val;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                   fal_mib_info_t * mib_info)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxUnderRun = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxOverSize = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxCollision = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxAbortCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMultiCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxSingalCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxExcDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxLateCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNICAST, port_id,
+                      (a_uint8_t *) (&val), sizeof
+                      (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxUniCast = val;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, MIB_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, MIB_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_CPU_KEEP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_CPU_KEEP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id)
+{
+    a_uint32_t val;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    if (port_id>7)
+        return SW_BAD_PARAM;
+
+    val =  port_id;
+    HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_FLUSH_PORT,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    rv = _isisc_mib_op_commit( dev_id,  MIB_FLUSH_ONE_PORT);
+
+    return rv;
+}
+
+/**
+ * @brief Get mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                  fal_mib_info_t * mib_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_get_mib_info(dev_id, port_id, mib_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get RX mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                  fal_mib_info_t * mib_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_get_rx_mib_info(dev_id, port_id, mib_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get TX mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                  fal_mib_info_t * mib_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_get_tx_mib_info(dev_id, port_id, mib_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_mib_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_mib_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+isisc_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_mib_port_flush_counters(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set mib cpu keep bit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_mib_cpukeep_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mib keep bit on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_mib_cpukeep_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isisc_mib_init(a_uint32_t dev_id)
+{
+#ifndef HSL_STANDALONG
+    hsl_api_t *p_api;
+#endif
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->get_mib_info   = isisc_get_mib_info;
+    p_api->get_rx_mib_info   = isisc_get_rx_mib_info;
+    p_api->get_tx_mib_info   = isisc_get_tx_mib_info;
+    p_api->mib_status_set = isisc_mib_status_set;
+    p_api->mib_status_get = isisc_mib_status_get;
+    p_api->mib_port_flush_counters = isisc_mib_port_flush_counters;
+    p_api->mib_cpukeep_set = isisc_mib_cpukeep_set;
+    p_api->mib_cpukeep_get = isisc_mib_cpukeep_get;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_mirror.c b/qca-ssdk/src/hsl/isisc/isisc_mirror.c
new file mode 100755
index 0000000..12441dc
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_mirror.c
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_mirror ISISC_MIRROR
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_mirror.h"
+#include "isisc_reg.h"
+
+static sw_error_t
+_isisc_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv;
+	a_uint32_t val;
+
+	HSL_DEV_ID_CHECK(dev_id);
+	if (port_id != MIRROR_ANALYZER_NONE) {
+		if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) {
+			return SW_BAD_PARAM;
+		}
+	}
+	val = port_id;
+	HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+	return rv;
+}
+
+static sw_error_t
+_isisc_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *port_id = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+ *   @details  Comments:
+ *   The analysis port works for both ingress and egress mirror.
+ * @brief Set mirror analyzer port on particular a device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_mirr_analysis_port_set(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mirror analysis port on particular a device.
+ * @param[in] dev_id device id
+ * @param[out] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_mirr_analysis_port_get(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_mirr_port_in_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_mirr_port_in_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_mirr_port_eg_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_mirr_port_eg_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isisc_mirr_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->mirr_analysis_port_set = isisc_mirr_analysis_port_set;
+        p_api->mirr_analysis_port_get = isisc_mirr_analysis_port_get;
+        p_api->mirr_port_in_set = isisc_mirr_port_in_set;
+        p_api->mirr_port_in_get = isisc_mirr_port_in_get;
+        p_api->mirr_port_eg_set = isisc_mirr_port_eg_set;
+        p_api->mirr_port_eg_get = isisc_mirr_port_eg_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_misc.c b/qca-ssdk/src/hsl/isisc/isisc_misc.c
new file mode 100755
index 0000000..bc79d49
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_misc.c
@@ -0,0 +1,2207 @@
+/*
+ * Copyright (c) 2012, 2015-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_misc ISISC_MISC
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_misc.h"
+#include "isisc_reg.h"
+#include "hsl_phy.h"
+
+
+#define ISISC_MAX_FRMAE_SIZE      9216
+
+#define ARP_REQ_EN_OFFSET    6
+#define ARP_ACK_EN_OFFSET    5
+#define DHCP_EN_OFFSET       4
+#define EAPOL_EN_OFFSET      3
+
+#define ISISC_SWITCH_INT_PHY_INT   0x8000
+
+
+static sw_error_t
+_isisc_port_misc_property_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable, a_uint32_t item)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (3 >= port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        reg &= ~(0x1UL << ((port_id << 3) + item));
+        reg |= (val << ((port_id << 3) + item));
+
+        HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        reg &= ~(0x1UL << (((port_id - 4) << 3) + item));
+        reg |= (val << (((port_id - 4) << 3) + item));
+
+        HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    }
+    return rv;
+}
+
+#ifndef IN_MISC_MINI
+static sw_error_t
+_isisc_port_misc_property_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable, a_uint32_t item)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (3 >= port_id)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        val = (reg >> ((port_id << 3) + item)) & 0x1UL;
+    }
+    else
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL;
+    }
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isisc_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISISC_MAX_FRMAE_SIZE < size)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = size;
+    HSL_REG_FIELD_SET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *size = data;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t) 0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_isisc_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t) 0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+
+static sw_error_t
+_isisc_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t) 0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+#ifndef IN_MISC_MINI
+static sw_error_t
+_isisc_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PKT_CTRL, 0, CPU_VID_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PKT_CTRL, 0, CPU_VID_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PKT_CTRL, 0, RTD_PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PKT_CTRL, 0, RTD_PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_isisc_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_FRWRD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_FRWRD == cmd)
+    {
+        val = 2;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else if (0 == val)
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_FRWRD;
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isisc_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+#ifndef IN_MISC_MINI
+static sw_error_t
+_isisc_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+#define ISISC_MAX_PPPOE_SESSION  16
+#define ISISC_MAX_SESSION_ID     0xffff
+
+static sw_error_t
+_isisc_pppoe_session_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, i, valid, id, entry_idx = ISISC_MAX_PPPOE_SESSION;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (session_tbl->session_id > ISISC_MAX_SESSION_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((A_FALSE == session_tbl->multi_session)
+            && (A_TRUE == session_tbl->uni_session))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((A_FALSE == session_tbl->multi_session)
+            && (A_FALSE == session_tbl->uni_session))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = 0; i < ISISC_MAX_PPPOE_SESSION; i++)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+        if (!valid)
+        {
+            entry_idx = i;
+        }
+        else if (id == session_tbl->session_id)
+        {
+            return SW_ALREADY_EXIST;
+        }
+    }
+
+    if (ISISC_MAX_PPPOE_SESSION == entry_idx)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+#if 0
+    if (A_TRUE == session_tbl->uni_session)
+    {
+        SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 2, reg);
+    }
+    else
+#endif
+    {
+        SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 1, reg);
+    }
+    SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, session_tbl->session_id,
+                        reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, entry_idx,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    session_tbl->entry_id = entry_idx;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_pppoe_session_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, i, valid, id;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (session_tbl->session_id > ISISC_MAX_SESSION_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = 0; i < ISISC_MAX_PPPOE_SESSION; i++)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+        if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id))
+        {
+            SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 0, reg);
+            SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, 0, reg);
+            HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, i,
+                              (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+            return rv;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isisc_pppoe_session_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, i, valid, id;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (session_tbl->session_id > ISISC_MAX_SESSION_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = 0; i < ISISC_MAX_PPPOE_SESSION; i++)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+        if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id))
+        {
+            if (1 == valid)
+            {
+                session_tbl->multi_session = A_TRUE;
+                session_tbl->uni_session = A_FALSE;
+            }
+            else
+            {
+                session_tbl->multi_session = A_TRUE;
+                session_tbl->uni_session = A_TRUE;
+            }
+
+            session_tbl->entry_id = i;
+            return SW_OK;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isisc_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+                           a_uint32_t id)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    if (ISISC_MAX_PPPOE_SESSION <= index)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISISC_MAX_SESSION_ID < id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    reg = 0;
+    SW_SET_REG_BY_FIELD(PPPOE_EDIT, EDIT_ID, id, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+                           a_uint32_t * id)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, tmp;
+
+    if (ISISC_MAX_PPPOE_SESSION <= index)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    tmp = 0;
+    SW_GET_FIELD_BY_REG(PPPOE_EDIT, EDIT_ID, tmp, reg);
+    *id = tmp;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (intr_mask & FAL_SWITCH_INTR_LINK_STATUS)
+    {
+        reg |= ISISC_SWITCH_INT_PHY_INT;
+    }
+    else
+    {
+        reg &= (~ISISC_SWITCH_INT_PHY_INT);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    *intr_mask = 0;
+    HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (reg & ISISC_SWITCH_INT_PHY_INT)
+    {
+        *intr_mask |= FAL_SWITCH_INTR_LINK_STATUS;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    *intr_status = 0;
+    HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (reg & ISISC_SWITCH_INT_PHY_INT)
+    {
+        *intr_status |= FAL_SWITCH_INTR_LINK_STATUS;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    reg = 0;
+    if (intr_status & FAL_SWITCH_INTR_LINK_STATUS)
+    {
+        reg |= ISISC_SWITCH_INT_PHY_INT;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_link_intr_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_intr_mask_set)
+	  return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_intr_mask_set(dev_id, phy_id, intr_mask_flag);
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_link_intr_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_intr_mask_get)
+	  return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_intr_mask_get(dev_id, phy_id, intr_mask_flag);
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_link_intr_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_intr_status_get)
+	  return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_intr_status_get(dev_id, phy_id, intr_mask_flag);
+    return rv;
+}
+
+static sw_error_t
+_isisc_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_MASK1, 0, LINK_CHG_INT_M,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_FALSE == enable)
+    {
+        data &= (~((a_uint32_t) 0x1 << port_id));
+    }
+    else if (A_TRUE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, GBL_INT_MASK1, 0, LINK_CHG_INT_M,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+
+static sw_error_t
+_isisc_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_MASK1, 0, LINK_CHG_INT_M,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_isisc_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_STATUS1, 0, LINK_CHG_INT_S,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    *port_bitmap = reg;
+
+    return rv;
+
+}
+
+static sw_error_t
+_isisc_intr_status_mac_linkchg_clear(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_STATUS1, 0, LINK_CHG_INT_S,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    HSL_REG_FIELD_SET(rv, dev_id, GBL_INT_STATUS1, 0, LINK_CHG_INT_S,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    return rv;
+
+}
+#endif
+
+/**
+ * @brief Set max frame size which device can received on a particular device.
+ * @details    Comments:
+ * The granularity of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[in] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_frame_max_size_set(dev_id, size);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max frame size which device can received on a particular device.
+ * @details   Comments:
+ *    The unit of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[out] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_frame_max_size_get(dev_id, size);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown unicast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown unicast packets filter on one port then unknown
+ *   unicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_unk_uc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown multicast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown multicast packets filter on one port then unknown
+ *   multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_unk_mc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of broadcast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown multicast packets filter on one port then unknown
+ *   multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_bc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cpu_port_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_MISC_MINI
+/**
+ * @brief Get flooding status of unknown unicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_unk_uc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/** @brief Get flooding status of unknown multicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_unk_mc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/** @brief Get flooding status of broadcast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_bc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cpu_port_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set pppoe packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling pppoe packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_pppoe_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get pppoe packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_pppoe_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set pppoe packets hardware acknowledgement status on particular device.
+ * @details     comments:
+ *   Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_pppoe_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get pppoe packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_pppoe_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dhcp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_misc_property_set(dev_id, port_id, enable, DHCP_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dhcp packets hardware acknowledgement status on particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_misc_property_get(dev_id, port_id, enable, DHCP_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling arp packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_arp_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_arp_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set eapol packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling eapol packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_eapol_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_MISC_MINI
+/**
+ * @brief Get eapol packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_eapol_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a pppoe session entry to a particular device.
+ *        The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_session_table_add(a_uint32_t dev_id,
+                             fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_pppoe_session_add(dev_id, session_tbl);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a pppoe session entry from a particular device.
+ *        The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_session_table_del(a_uint32_t dev_id,
+                             fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_pppoe_session_del(dev_id, session_tbl);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a pppoe session entry from a particular device.
+ *        The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[out] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_session_table_get(a_uint32_t dev_id,
+                             fal_pppoe_session_t * session_tbl)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_pppoe_session_get(dev_id, session_tbl);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set a pppoe session id entry to a particular device.
+ *        The entry only for pppoe/ppp header add.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+                          a_uint32_t id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_pppoe_session_id_set(dev_id, index, id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a pppoe session id entry from a particular device.
+ *        The entry only for pppoe/ppp header add.
+ * @param[in] dev_id device id
+ * @param[out] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+                          a_uint32_t * id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_pppoe_session_id_get(dev_id, index, id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_misc_property_set(dev_id, port_id, enable, EAPOL_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_MISC_MINI
+/**
+ * @brief Get eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_misc_property_get(dev_id, port_id, enable, EAPOL_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ripv1_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ripv1_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp req packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_misc_property_set(dev_id, port_id, enable,
+                                      ARP_REQ_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp req packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_misc_property_get(dev_id, port_id, enable,
+                                      ARP_REQ_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp ack packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_misc_property_set(dev_id, port_id, enable,
+                                      ARP_ACK_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp ack packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_misc_property_get(dev_id, port_id, enable,
+                                      ARP_ACK_EN_OFFSET);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set switch interrupt mask on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_mask mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_intr_mask_set(dev_id, intr_mask);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get switch interrupt mask on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_mask mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_intr_mask_get(dev_id, intr_mask);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get switch interrupt status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_status status
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_intr_status_get(dev_id, intr_status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Clear switch interrupt status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_status status
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_intr_status_clear(dev_id, intr_status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set link interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isisc_port_link_intr_mask_set(dev_id, port_id, intr_mask_flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get link interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_link_intr_mask_get(dev_id, port_id, intr_mask_flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get link interrupt status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_link_intr_status_get(dev_id, port_id, intr_mask_flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set mac link change interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable ports intr mask enabled
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    FAL_API_LOCK;
+    rv = _isisc_intr_mask_mac_linkchg_set(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mac link change interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port interrupt mask or not
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _isisc_intr_mask_mac_linkchg_get(dev_id, port_id, enable);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get link change interrupt status for all ports.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] ports bitmap which generates interrupt
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _isisc_intr_status_mac_linkchg_get(dev_id, port_bitmap);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set cpu vid enable status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cpu_vid_en_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get cpu vid enable status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_cpu_vid_en_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set RM_RTD_PPPOE_EN status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_rtd_pppoe_en_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get RM_RTD_PPPOE_EN status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_rtd_pppoe_en_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Clear link change interrupt status for all ports.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_status_mac_linkchg_clear(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    FAL_API_LOCK;
+    rv = _isisc_intr_status_mac_linkchg_clear(dev_id);
+    FAL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+sw_error_t
+isisc_misc_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->frame_max_size_set = isisc_frame_max_size_set;
+        p_api->frame_max_size_get = isisc_frame_max_size_get;
+        p_api->port_unk_uc_filter_set = isisc_port_unk_uc_filter_set;
+        p_api->port_unk_mc_filter_set = isisc_port_unk_mc_filter_set;
+        p_api->port_bc_filter_set = isisc_port_bc_filter_set;
+	p_api->cpu_port_status_set = isisc_cpu_port_status_set;
+#ifndef IN_MISC_MINI
+	p_api->port_unk_uc_filter_get = isisc_port_unk_uc_filter_get;
+	p_api->port_unk_mc_filter_get = isisc_port_unk_mc_filter_get;
+        p_api->port_bc_filter_get = isisc_port_bc_filter_get;
+        p_api->cpu_port_status_get = isisc_cpu_port_status_get;
+        p_api->pppoe_cmd_set = isisc_pppoe_cmd_set;
+        p_api->pppoe_cmd_get = isisc_pppoe_cmd_get;
+        p_api->pppoe_status_set = isisc_pppoe_status_set;
+        p_api->pppoe_status_get = isisc_pppoe_status_get;
+        p_api->port_dhcp_set = isisc_port_dhcp_set;
+        p_api->port_dhcp_get = isisc_port_dhcp_get;
+        p_api->arp_cmd_set = isisc_arp_cmd_set;
+        p_api->arp_cmd_get = isisc_arp_cmd_get;
+#endif
+        p_api->eapol_cmd_set = isisc_eapol_cmd_set;
+#ifndef IN_MISC_MINI
+        p_api->eapol_cmd_get = isisc_eapol_cmd_get;
+        p_api->pppoe_session_table_add = isisc_pppoe_session_table_add;
+        p_api->pppoe_session_table_del = isisc_pppoe_session_table_del;
+        p_api->pppoe_session_table_get = isisc_pppoe_session_table_get;
+        p_api->pppoe_session_id_set = isisc_pppoe_session_id_set;
+        p_api->pppoe_session_id_get = isisc_pppoe_session_id_get;
+#endif
+        p_api->eapol_status_set = isisc_eapol_status_set;
+#ifndef IN_MISC_MINI
+        p_api->eapol_status_get = isisc_eapol_status_get;
+        p_api->ripv1_status_set = isisc_ripv1_status_set;
+        p_api->ripv1_status_get = isisc_ripv1_status_get;
+        p_api->port_arp_req_status_set = isisc_port_arp_req_status_set;
+        p_api->port_arp_req_status_get = isisc_port_arp_req_status_get;
+        p_api->port_arp_ack_status_set = isisc_port_arp_ack_status_set;
+        p_api->port_arp_ack_status_get = isisc_port_arp_ack_status_get;
+        p_api->intr_mask_set = isisc_intr_mask_set;
+        p_api->intr_mask_get = isisc_intr_mask_get;
+        p_api->intr_status_get = isisc_intr_status_get;
+        p_api->intr_status_clear = isisc_intr_status_clear;
+        p_api->intr_port_link_mask_set = isisc_intr_port_link_mask_set;
+        p_api->intr_port_link_mask_get = isisc_intr_port_link_mask_get;
+        p_api->intr_port_link_status_get = isisc_intr_port_link_status_get;
+        p_api->intr_mask_mac_linkchg_set = isisc_intr_mask_mac_linkchg_set;
+        p_api->intr_mask_mac_linkchg_get = isisc_intr_mask_mac_linkchg_get;
+        p_api->intr_status_mac_linkchg_get = isisc_intr_status_mac_linkchg_get;
+        p_api->cpu_vid_en_set = isisc_cpu_vid_en_set;
+        p_api->cpu_vid_en_get = isisc_cpu_vid_en_get;
+        p_api->rtd_pppoe_en_set = isisc_rtd_pppoe_en_set;
+        p_api->rtd_pppoe_en_get = isisc_rtd_pppoe_en_get;
+        p_api->intr_status_mac_linkchg_clear = isisc_intr_status_mac_linkchg_clear;
+#endif
+
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/isisc/isisc_multicast_acl.c b/qca-ssdk/src/hsl/isisc/isisc_multicast_acl.c
new file mode 100755
index 0000000..bd2c91c
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_multicast_acl.c
@@ -0,0 +1,1024 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#include "fal_nat.h"
+#include "fal_ip.h"
+#include "hsl_api.h"
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_igmp.h"
+#include "isisc_reg.h"
+#include "isisc_acl.h"
+#include "fal_multi.h"
+#include "sal/os/aos_lock.h"
+
+#if 0
+/**
+ * I/F prototype for complete igmpv3 & mldv2 support
+ */
+
+/*supports 32 entries*/
+#define FAL_IGMP_SG_ENTRY_MAX 32
+
+typedef enum
+{
+    FAL_ADDR_IPV4 = 0,
+    FAL_ADDR_IPV6
+} fal_addr_type_t;
+
+typedef struct
+{
+    fal_addr_type_t type;
+    union
+    {
+        fal_ip4_addr_t ip4_addr;
+        fal_ip6_addr_t ip6_addr;
+    } u;
+} fal_igmp_sg_addr_t;
+
+typedef struct
+{
+    fal_igmp_sg_addr_t source;
+    fal_igmp_sg_addr_t group;
+    fal_pbmp_t port_map;
+} fal_igmp_sg_entry_t;
+
+/**
+ * @brief set PortMap of IGMP sg entry.
+ *        search entry according to source/group address,
+ *        update PortMap if SG entry is found, otherwise create a new sg entry.
+ * @param[in] dev_id device id
+ * @param[in-out] entry SG entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+/**
+ * @brief clear PortMap of IGMP sg entry.
+ *        search entry according to source/group address,
+ *        update PortMap if SG entry is found, delete the entry in case PortMap was 0.
+ *        SW_NOT_FOUND will be returned in case search failed.
+ * @param[in] dev_id device id
+ * @param[in-out] entry SG entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+#define MULTI_DEBUG_
+#ifdef MULTI_DEBUG_
+#define MULTI_DEBUG(x...) aos_printk(x)
+#else
+#define MULTI_DEBUG(x...)
+#endif
+
+#define FAL_ACL_LIST_MULTICAST 55
+#define FAL_MULTICAST_PRI   5
+
+#define MULT_ACTION_SET      1
+#define MULT_ACTION_CLEAR    1
+
+static a_uint32_t rule_nr=1;
+
+typedef struct
+{
+    a_uint8_t index; //MAX is 32
+    fal_igmp_sg_entry_t entry; //Stores the specific ACL rule info
+} multi_acl_info_t;
+#endif
+
+static a_uint32_t mul_rule_nr=1;
+
+void
+isisc_multicast_init(a_uint32_t dev_id);
+
+HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t dev_id, a_uint32_t pos, fal_igmp_sg_entry_t * entry);
+
+static multi_acl_info_t multi_acl_info[FAL_IGMP_SG_ENTRY_MAX];
+static multi_acl_info_t multi_acl_group[FAL_IGMP_SG_ENTRY_MAX];
+
+static int ip6_addr_is_null(fal_ip6_addr_t *ip6)
+{
+    if (NULL == ip6)
+    {
+        aos_printk("Invalid ip6 address\n");
+        return -1;
+    }
+    if(0 == ip6->ul[0] && 0 == ip6->ul[1] && 0 == ip6->ul[2] && 0 == ip6->ul[3])
+        return 1;
+    else
+        return 0;
+}
+static int multi_source_is_null(fal_igmp_sg_addr_t *s)
+{
+    if (NULL == s)
+    {
+        aos_printk("Invalid source address\n");
+        return -1;
+    }
+    if(0 == s->type && 0==s->u.ip4_addr)
+        return 1;
+    if(1 == s->type && 1 == ip6_addr_is_null(&(s->u.ip6_addr)))
+        return 1;
+
+    return 0;
+}
+
+HSL_LOCAL int iterate_multicast_acl_rule(a_uint32_t dev_id, int list_id, int start_n)
+{
+    a_uint32_t rule_id;
+    sw_error_t ret;
+    fal_acl_rule_t  rule= {0};
+
+    if(start_n>=FAL_IGMP_SG_ENTRY_MAX || start_n < 0)
+    {
+        return -1;
+    }
+
+    for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+    {
+        ret = isisc_acl_rule_query(dev_id, list_id, rule_id, &rule);
+
+        if (ret==SW_NOT_FOUND )
+            break;//NOT found in ACL rule
+        if((rule_id+start_n)>=FAL_IGMP_SG_ENTRY_MAX)
+        {
+            return -1;
+        }
+
+        multi_acl_info[rule_id+start_n].index = rule_id; // consider here... index is NOT related start_n
+        //MULTI_DEBUG("normal query1: rule dest_ip4_val=%x, src ip4=%x, dst_ip6=%x, ports=%x\n",
+        //rule.dest_ip4_val, rule.src_ip4_val, rule.dest_ip6_val.ul[0], rule.ports);
+
+        if(rule.dest_ip4_val !=0 && ip6_addr_is_null(&rule.dest_ip6_val))  //only ip4
+        {
+            multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV4;
+            multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV4;
+            multi_acl_info[rule_id+start_n].entry.group.u.ip4_addr = rule.dest_ip4_val;
+            multi_acl_info[rule_id+start_n].entry.source.u.ip4_addr = rule.src_ip4_val;
+            multi_acl_info[rule_id+start_n].entry.port_map= rule.ports;
+        }
+        else if(rule.dest_ip4_val ==0 && !ip6_addr_is_null(&rule.dest_ip6_val))  //only ip6
+        {
+            multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV6;
+            multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV6;
+            memcpy(&(multi_acl_info[rule_id+start_n].entry.group.u.ip6_addr), &(rule.dest_ip6_val), sizeof(rule.dest_ip6_val));
+            memcpy(&(multi_acl_info[rule_id+start_n].entry.source.u.ip6_addr), &(rule.src_ip6_val), sizeof(rule.src_ip6_val));
+            multi_acl_info[rule_id+start_n].entry.port_map= rule.ports;
+        }
+        if (FAL_FIELD_FLG_TST(rule.field_flg, FAL_ACL_FIELD_MAC_VID))
+        {
+            multi_acl_info[rule_id+start_n].entry.vlan_id = rule.vid_val;
+        }
+        else
+        {
+            multi_acl_info[rule_id+start_n].entry.vlan_id = 0xffff;
+        }
+    }
+
+    return rule_id+start_n;
+}
+/*
+** Iterate the total 32 multicast ACL entries.
+    After the function completes:
+         1. Stores all multicast related ACL rules in multi_acl_info[32]
+         2. return the number of multicast related ACL rules
+*/
+HSL_LOCAL a_uint32_t isisc_multicast_acl_query(a_uint32_t dev_id)
+{
+    int start_n;
+    int total_n;
+    //a_uint32_t i;
+
+    start_n = iterate_multicast_acl_rule(dev_id, FAL_ACL_LIST_MULTICAST, 0);
+    if(-1 == start_n)
+        aos_printk("ACL rule1 is FULL\n");
+    total_n = iterate_multicast_acl_rule(dev_id, FAL_ACL_LIST_MULTICAST+1, start_n);
+    if(-1 == total_n)
+        aos_printk("ACL rule2 is FULL\n");
+
+    MULTI_DEBUG("KKK, the total ACL rule number is %d, (G,S) number=%d\n", total_n, start_n);
+    /*
+    for(i=0;i<total_n;i++)
+    MULTI_DEBUG("KKK, indx=%d, multi_acl_info[%d].entry=[%d][%x]\n", multi_acl_info[i].index,i,
+        multi_acl_info[i].entry.group.type, multi_acl_info[i].entry.group.u.ip4_addr );
+        */
+
+    return total_n;
+}
+
+HSL_LOCAL a_uint32_t isisc_multicast_acl_total_n(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    a_uint32_t ret;
+    a_uint32_t rule_id;
+    fal_acl_rule_t  rule= {0};
+
+    for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+    {
+        ret = isisc_acl_rule_query(dev_id, list_id,
+                                   rule_id, &rule);
+        if(ret==SW_NOT_FOUND)
+            return rule_id;
+
+    }
+    return 0;
+}
+
+#define ISISC_FILTER_ACT_ADDR    0x5a000
+#define ISISC_FILTER_MSK_ADDR    0x59000
+HSL_LOCAL sw_error_t multi_portmap_aclreg_set_all(a_uint32_t dev_id, a_uint32_t pos, fal_igmp_sg_entry_t * entry)
+{
+    a_uint32_t i, base, addr;
+    a_uint32_t msk_valid=0;
+    sw_error_t rv = SW_OK;
+
+    /*  2'b00:start; 2'b01:continue; 2'b10:end; 2'b11:start&end*/
+    for(i=pos; i<pos+4; i++)
+    {
+        base = ISISC_FILTER_MSK_ADDR +(i<<5);
+        addr = base+(4<<2); //fifth byte
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&msk_valid),
+                              sizeof (a_uint32_t));
+
+        SW_RTN_ON_ERROR(rv);
+        if ((((msk_valid>>6)&0x3) == 0x3) || (((msk_valid>>6)&0x3) == 0x2))
+        {
+            rv = multi_portmap_aclreg_set(dev_id, i, entry);
+            break;
+        }
+        else if ((((msk_valid>>6)&0x3)) == 0x0 || (((msk_valid>>6)&0x3) == 0x1))
+        {
+            rv = multi_portmap_aclreg_set(dev_id, i, entry);
+            continue;
+        }
+        else
+        {
+            aos_printk("The rule valid bit:6 7 is wrong!!!");
+            break;
+        }
+    }
+    return rv;
+}
+HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t dev_id, a_uint32_t pos, fal_igmp_sg_entry_t * entry)
+{
+    a_uint32_t i, base, addr;
+    sw_error_t rv;
+    a_uint32_t act[3]= {0};
+    fal_pbmp_t pm;
+
+    pm = entry->port_map;
+
+    base = ISISC_FILTER_ACT_ADDR + (pos << 4);
+    for (i = 0; i < 3; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&act[i]),
+                              sizeof (a_uint32_t));
+        //MULTI_DEBUG("2:Get register value  0x%x =%x\n", addr, act[i]);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    act[1] &= ~(0x7<<29); // clear the high 3 bits
+    act[1] |= (pm&0x7)<<29;  //the low 3 bits of pm means redirect port 0,1,2
+
+    /* New modification: update acl ACTION register from DENY to redirect */
+    if (((act[2]>>6)&0x7) == 0x7) //DENY mode
+    {
+        if(pm)
+        {
+            act[2] &= ~(0x7<<6);//clear DENY bits
+            act[2] |= (0x1<<4); //DES_PORT_EN set 1, enable
+        }
+    }
+    else if (((act[2]>>4)&0x1) == 0x1) //redirect mode
+    {
+        if(pm==0)
+        {
+            act[2] &= ~(0x1<<4);//clear redirect bits
+            act[2] |= (0x7<<6); //set to DENY
+        }
+    }
+
+    act[2] &= ~0xf; //clear the low 4 bits of port 3,4,5,6
+    act[2] |= (pm>>3)&0xf;
+
+    addr = base + (1<<2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&act[1]), sizeof (a_uint32_t));
+    addr = base + (2<<2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&act[2]), sizeof (a_uint32_t));
+    MULTI_DEBUG("pos=%d, before sync portmap, the new act=%x %x\n", pos, act[1],act[2]);
+    if((rv = isisc_acl_rule_sync_multi_portmap(dev_id, pos, act)) < 0)
+        aos_printk("Sync multicast portmap error\n");
+    return rv;
+}
+
+HSL_LOCAL int multi_get_dp(a_uint32_t dev_id)
+{
+    a_uint32_t addr;
+    sw_error_t rv;
+    int val=0;
+
+    addr = 0x624;//GLOBAL_FW_CTRL1
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&val),
+                          sizeof (a_uint32_t));
+    if (rv != SW_OK)
+        aos_printk("Get entry value error\n");
+
+    val = (val>>24)&0x7f; //30:24, IGMP_JOIN_LEAVE_DP
+
+    return val;
+}
+static int old_bind_p=-1;
+HSL_LOCAL int multi_acl_bind(a_uint32_t dev_id)
+{
+    int bind_p;
+    int i;
+
+    bind_p = multi_get_dp(dev_id);
+    if(bind_p == old_bind_p)
+        return 0;
+    old_bind_p = bind_p;
+
+    for(i=0; i<7; i++)
+    {
+        isisc_acl_list_unbind(dev_id, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+        isisc_acl_list_unbind(dev_id, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+    }
+
+    if(bind_p==0)
+    {
+        for(i=0; i<7; i++)
+        {
+            isisc_acl_list_bind(dev_id, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+            isisc_acl_list_bind(dev_id, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+        }
+    }
+    else
+    {
+        for(i=0; i<7; i++)
+            if((bind_p>>i) &0x1)
+            {
+                isisc_acl_list_bind(dev_id, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+                isisc_acl_list_bind(dev_id, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+            }
+            else
+                continue;
+    }
+	return 0;
+}
+/*
+** Only update the related portmap from the privious input.
+*/
+HSL_LOCAL sw_error_t isisc_multicast_acl_update(a_uint32_t dev_id, int list_id, int acl_index, fal_igmp_sg_entry_t * entry, int action)
+{
+    a_uint32_t rule_pos;
+    sw_error_t rv;
+
+    if(acl_index<0)
+    {
+        aos_printk("Something is wrong...\n");
+        return SW_FAIL;
+    }
+
+    rule_pos = isisc_acl_rule_get_offset(dev_id, list_id, multi_acl_group[acl_index].index);
+    if(MULT_ACTION_SET == action)
+    {
+        multi_acl_group[acl_index].entry.port_map |= entry->port_map;
+        if(entry->port_map == 0)
+        {
+            multi_acl_group[acl_index].entry.port_map = 0;
+        }
+    }
+    else if(MULT_ACTION_CLEAR == action)
+        multi_acl_group[acl_index].entry.port_map &= ~(entry->port_map);
+
+    rv = multi_portmap_aclreg_set_all(dev_id, rule_pos, &multi_acl_group[acl_index].entry);
+
+    multi_acl_bind(dev_id); //Here need extra bind since IGMP join/leave would happen
+    return rv;
+}
+
+HSL_LOCAL sw_error_t isisc_multicast_acl_del(a_uint32_t dev_id, int list_id, int index)
+{
+    sw_error_t rv;
+    int rule_id;
+
+    rule_id = multi_acl_group[index].index;
+
+    rv = isisc_acl_rule_delete(dev_id, list_id, rule_id, 1);
+    multi_acl_bind(dev_id); //Here need extra bind since IGMP join/leave would happen
+    return rv;
+}
+
+/*
+** Add new acl rule with parameters: DIP, SIP, redirect port.
+*/
+HSL_LOCAL sw_error_t isisc_multicast_acl_add(a_uint32_t dev_id, int list_id, fal_igmp_sg_entry_t * entry)
+{
+    sw_error_t val;
+    a_uint32_t pos;
+    fal_acl_rule_t acl= {0};
+
+    /* IPv4 multicast */
+    if( entry->group.type == FAL_ADDR_IPV4 )
+    {
+        MULTI_DEBUG("KKK1, group[%d][%x], source[%d][%x]\n",entry->group.type,
+                    entry->group.u.ip4_addr, entry->source.type, entry->source.u.ip4_addr);
+
+        acl.rule_type = FAL_ACL_RULE_IP4;
+
+        if(entry->group.u.ip4_addr!= 0)
+        {
+            acl.dest_ip4_val = entry->group.u.ip4_addr;
+            acl.dest_ip4_mask = 0xffffffff;//e->ip.dmsk.s_addr;
+            FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_DIP);
+        }
+        if(entry->source.u.ip4_addr!= 0)
+        {
+            acl.src_ip4_val = entry->source.u.ip4_addr;
+            acl.src_ip4_mask = 0xffffffff;//e->ip.smsk.s_addr;
+            FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_SIP);
+        }
+        if( entry->port_map==0 )
+            FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY);
+        else
+            //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+            FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT );
+
+        /* Be careful, _isisc_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */
+        if( entry->port_map )
+        {
+            FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT);
+            acl.ports = entry->port_map;
+        }
+    }
+    else if( entry->group.type == FAL_ADDR_IPV6 )
+    {
+        MULTI_DEBUG("KKK2, group[%d][%x], source[%d][%x], pm=%x\n",entry->group.type,
+                    entry->group.u.ip6_addr.ul[0], entry->source.type, entry->source.u.ip6_addr.ul[0], entry->port_map);
+
+        acl.rule_type = FAL_ACL_RULE_IP6;
+
+        if(!ip6_addr_is_null(&(entry->group.u.ip6_addr)))
+        {
+            memcpy(&acl.dest_ip6_val, &(entry->group.u.ip6_addr), sizeof(entry->group.u.ip6_addr));
+            acl.dest_ip6_mask.ul[0] = 0xffffffff;
+            acl.dest_ip6_mask.ul[1] = 0xffffffff;
+            acl.dest_ip6_mask.ul[2] = 0xffffffff;
+            acl.dest_ip6_mask.ul[3] = 0xffffffff;
+            FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_DIP);
+        }
+        if(!ip6_addr_is_null(&(entry->source.u.ip6_addr)))
+        {
+            memcpy(&acl.src_ip6_val, &(entry->source.u.ip6_addr), sizeof(entry->source.u.ip6_addr));
+            acl.src_ip6_mask.ul[0] = 0xffffffff;
+            acl.src_ip6_mask.ul[1] = 0xffffffff;
+            acl.src_ip6_mask.ul[2] = 0xffffffff;
+            acl.src_ip6_mask.ul[3] = 0xffffffff;
+            FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_SIP);
+        }
+
+        if( entry->port_map==0 )
+            FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY);
+        else
+            //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+            FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT );
+
+        /* Be careful, _isisc_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */
+        if( entry->port_map )
+        {
+            FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT);
+            acl.ports = entry->port_map;
+        }
+    }
+
+    if (entry->vlan_id < 4096)
+    {
+        FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_MAC_VID);
+        acl.vid_val = entry->vlan_id;
+        acl.vid_op = FAL_ACL_FIELD_MASK;
+        acl.vid_mask = 0xfff;
+    }
+
+    pos = isisc_multicast_acl_total_n(dev_id, list_id);
+
+    MULTI_DEBUG("In isisc_multicast_acl_add, list_id=%d, rule_id=%d\n", list_id, pos);
+    val = isisc_acl_rule_add(dev_id, list_id, pos, mul_rule_nr, &acl);
+
+    multi_acl_bind(dev_id);
+
+    return val;
+}
+
+
+HSL_LOCAL int iterate_multicast_acl_group(a_uint32_t number, fal_igmp_sg_entry_t * entry)
+{
+    int count=0;
+    int i;
+
+    if (number == 0)
+        return 0; //no any ACL rules based the query
+
+    for(i=0; i<number; i++)
+    {
+
+        /*MULTI_DEBUG("2:iterate_multicast_acl_group, index=%d, multi_acl_info[%d].entry=type[%d]-addr[%x], pm=%x, new entry=type[%d]-addr[%x], pm=%x\n",
+            multi_acl_info[i].index,i, multi_acl_info[i].entry.group.type, multi_acl_info[i].entry.group.u.ip6_addr.ul[0], multi_acl_info[i].entry.port_map,
+            entry->group.type, entry->group.u.ip6_addr.ul[0], entry->port_map);*/
+
+        if(0 == memcmp(&(multi_acl_info[i].entry.group), &(entry->group), sizeof(entry->group)))
+        {
+            memcpy(&multi_acl_group[count], &multi_acl_info[i], sizeof(multi_acl_info[i]));
+            count++;//return the real number of multi_acl_group[]
+            MULTI_DEBUG("in iterate_multicast_acl_group, count=%d, i=%d\n", count, i);
+        }
+    }
+
+    return count;
+}
+
+HSL_LOCAL int mult_acl_has_entry(fal_igmp_sg_addr_t * group, fal_igmp_sg_addr_t *source)
+{
+    int rule_id;
+    int ret = 0;
+#if 0
+    if(source != NULL)
+    {
+        MULTI_DEBUG("new group[%d]= %x %x %x %x, new source[%d]=%x %x %x %x\n",
+                    group->type, group->u.ip6_addr.ul[0], group->u.ip6_addr.ul[1], group->u.ip6_addr.ul[2], group->u.ip6_addr.ul[3],
+                    source->type, source->u.ip6_addr.ul[0], source->u.ip6_addr.ul[1], source->u.ip6_addr.ul[2], source->u.ip6_addr.ul[3]);
+
+        MULTI_DEBUG("old group[%d]= %x %x %x %x, old source[%d]=%x %x %x %x\n",
+                    multi_acl_group[0].entry.group.type, multi_acl_group[0].entry.group.u.ip6_addr.ul[0],
+                    multi_acl_group[0].entry.group.u.ip6_addr.ul[1], multi_acl_group[0].entry.group.u.ip6_addr.ul[2], multi_acl_group[0].entry.group.u.ip6_addr.ul[3],
+                    multi_acl_group[0].entry.source.type, multi_acl_group[0].entry.source.u.ip6_addr.ul[0],
+                    multi_acl_group[0].entry.source.u.ip6_addr.ul[1], multi_acl_group[0].entry.source.u.ip6_addr.ul[2], multi_acl_group[0].entry.source.u.ip6_addr.ul[3]);
+    }
+#endif
+    if(source == NULL)
+    {
+        for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+        {
+            if( (0==memcmp(&multi_acl_group[rule_id].entry.group, group, sizeof(fal_igmp_sg_addr_t))) &&
+                    (multi_source_is_null(&multi_acl_group[rule_id].entry.source)))
+            {
+                MULTI_DEBUG("Source=0:Orignal ACL rule have this entry! rule id= %d\n", rule_id);
+                ret = rule_id+1; // ensure the return value is the actually number of entry
+                break;
+            }
+        }
+    }
+    else
+    {
+        for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+        {
+            if( (0==memcmp(&multi_acl_group[rule_id].entry.group, group, sizeof(fal_igmp_sg_addr_t))) &&
+                    (0==memcmp(&multi_acl_group[rule_id].entry.source, source, sizeof(fal_igmp_sg_addr_t))))
+            {
+                MULTI_DEBUG("Orignal ACL rule have this entry! rule id= %d\n", rule_id);
+                ret = rule_id+1; // ensure the return value is the actually number of entry
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+HSL_LOCAL int portmap_null(int index, fal_pbmp_t portmap)
+{
+    int val;
+    if (index<0)
+    {
+        aos_printk("portmap_null, index error\n");
+        return SW_FAIL;
+    }
+    val = multi_acl_group[index].entry.port_map&(~portmap);
+
+    if( 0 == (val&0xff) )
+        return 1;
+    else
+        return 0;
+}
+
+HSL_LOCAL int portmap_valid(fal_igmp_sg_entry_t *g_source, fal_igmp_sg_entry_t *g_star)
+{
+    /* return 0 means the portmap is Not valid
+        return 1 means the protmap is valid
+    */
+    /* MULTI_DEBUG("portmap_valid:g_source portmap=%x,  source=%x,group=%x, g_star portmap=%x, source=%x, group=%x\n",
+          g_source->port_map, g_source->source.u.ip4_addr, g_source->group.u.ip4_addr,
+          g_star->port_map, g_star->source.u.ip4_addr,g_star->group.u.ip4_addr);*/
+
+    if(multi_source_is_null(&(g_star->source)))
+    {
+        if((g_source->port_map|g_star->port_map) == g_star->port_map)
+        {
+            return 0;
+        }
+    }
+
+    return 1;
+}
+
+
+HSL_LOCAL int portmap_clear_type(int count, int index, fal_pbmp_t portmap)
+{
+    if(count>=0 && index<count) //new_index must >0; this means there're (G,*) and (G,S)
+    {
+        //if the new clear portmap will cause (G,S)=(G,*), Delete the (G,S)
+        if((multi_acl_group[index].entry.port_map & (~portmap)) == multi_acl_group[count].entry.port_map)
+            return 1; //delete
+
+
+        //The following means there must be at least one bit clear wrong. Clear the (G,*) portmap.
+        if( ((multi_acl_group[index].entry.port_map & (~portmap)) & (multi_acl_group[count].entry.port_map))
+                != (multi_acl_group[count].entry.port_map))
+            return 0;
+
+        return 2; //Normal update
+    }
+    return 0;
+}
+sw_error_t isisc_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+    int number, count;
+    int new_index=0;
+    sw_error_t rv;
+    int action = MULT_ACTION_SET;
+    int i=0;
+
+    HSL_API_LOCK;
+    isisc_multicast_init(dev_id);
+    aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    MULTI_DEBUG("Before query: group=%x, source=%x, portmap=%x\n", entry->group.u.ip4_addr, entry->source.u.ip4_addr, entry->port_map);
+    //number is the total multicast ACL rules amount, stores in multi_acl_info[];
+    number = isisc_multicast_acl_query(dev_id);
+    if(number > FAL_IGMP_SG_ENTRY_MAX)
+	return SW_FAIL;
+    //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number
+    count = iterate_multicast_acl_group(number, entry);
+    //new_index-1 is the found entry index in multi_acl_group[], the real index is [new_index-1], 0 means no entry
+    new_index = mult_acl_has_entry(&entry->group, &entry->source);
+
+    MULTI_DEBUG("Start entry set: number=%d, count=%d, new_index=%d, pm=%x\n", number, count, new_index, entry->port_map);
+    if( 0==multi_source_is_null(&entry->source) )  // new entry is (G, S)
+    {
+        MULTI_DEBUG("the new entry is (G,S)\n");
+        if(count>0 && 0 == portmap_valid(entry, &(multi_acl_group[count-1].entry))) //specfic group entry exist,(G,S) or (G,*)
+        {
+            //return SW_NO_CHANGE; // The new portmap is Not valid
+            MULTI_DEBUG("KKK, modified 1 !!!\n");
+        }
+
+        if(0 == new_index) //new entry, need add
+        {
+#if 0
+            /*The method:
+                1. predict if the portmap should be modified.
+                2. add new acl rule with new portmap value.
+            */
+            if((tmp_index = mult_acl_has_entry(&entry->group, NULL))>0) // (G, *) entry exist
+            {
+                /*Here the update should new (G, S) OR orignal (G,*) portmap,
+                be careful, entry's portmap value will be modified, so I use tmp_entry.
+                */
+                memcpy(tmp_entry, entry, sizeof(fal_igmp_sg_entry_t));
+                MULTI_DEBUG("Here, (G,*) exist! tmp_index=%d\n", tmp_index);
+                sw_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, tmp_index-1, tmp_entry, action);
+
+                isisc_multicast_acl_add(FAL_ACL_LIST_MULTICAST, tmp_entry);
+                return SW_OK;
+            }
+#endif
+            isisc_multicast_acl_add(dev_id, FAL_ACL_LIST_MULTICAST, entry);
+            MULTI_DEBUG("Here, need add (G, S), portmap=%x\n", entry->port_map);
+            return SW_OK;
+        }
+        else
+        {
+            //Here update Just: the old exist entry portmap OR the new entry portmap
+            isisc_multicast_acl_update(dev_id, FAL_ACL_LIST_MULTICAST, new_index-1, entry, action);
+            return SW_OK;
+        }
+    } //end of memcmp
+    else  // new entry is (G, *)
+    {
+        if(0 == new_index) //new entry, need add
+        {
+            isisc_multicast_acl_add(dev_id, FAL_ACL_LIST_MULTICAST+1, entry);
+            rv = SW_OK;
+        }
+        else if(new_index > 0) // (G, *) entry exist?
+        {
+            //Update exist (G, *) portmap with new portmap
+            MULTI_DEBUG("(G,*) exist, before update, new_index=%d\n", new_index );
+            isisc_multicast_acl_update(dev_id, FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action);
+            rv = SW_OK;
+        }
+
+        if(new_index>0&&count>1) //(G,S*) and (G,*) exist, new entry is (G,*)
+        {
+            for(i=count-2; i>=0&&i<FAL_IGMP_SG_ENTRY_MAX; i--)
+            {
+                if(multi_acl_group[i].entry.port_map==0) //This ACL rule should be done nothing, DENY rule
+                    continue;
+
+                if(0 == portmap_valid(&(multi_acl_group[i].entry), &(multi_acl_group[count-1].entry)))
+                {
+                    MULTI_DEBUG("1:portmap is not valid, should delete, i=%d, source portmap=%x, gstar pm=%x\n",
+                                i, multi_acl_group[i].entry.port_map, multi_acl_group[count-1].entry.port_map);
+                    isisc_multicast_acl_del(dev_id, FAL_ACL_LIST_MULTICAST, i);
+                    rv = SW_NO_MORE;
+                }
+                else
+                {
+                    MULTI_DEBUG("1:Start update all (G,S),i=%d, gstar portmap=%x\n", i, multi_acl_group[count-1].entry.port_map);
+                    //Update all (G,S) entry portmap with new(G, *) portmap
+                    isisc_multicast_acl_update(dev_id, FAL_ACL_LIST_MULTICAST, i, entry, action);
+                    rv = SW_OK;
+                }
+            }
+        }
+        else if(new_index==0&&count>0) //only exist (G,S*) orignally
+        {
+            for(i=count-1; i>=0&&i<FAL_IGMP_SG_ENTRY_MAX; i--)
+            {
+                if(multi_acl_group[i].entry.port_map==0) //This ACL rule should be done nothing, DENY rule
+                    continue;
+
+                if(0 == portmap_valid(&(multi_acl_group[i].entry), entry))
+                {
+                    MULTI_DEBUG("2:portmap is not valid, should delete, i=%d, source portmap=%x, gstar pm=%x\n",
+                                i, multi_acl_group[i].entry.port_map, entry->port_map);
+                    isisc_multicast_acl_del(dev_id, FAL_ACL_LIST_MULTICAST, i);
+                    rv = SW_NO_MORE;
+                }
+                else
+                {
+                    MULTI_DEBUG("2:Start update all (G,S),i=%d, portmap=%x\n", i, entry->port_map);
+                    //Update all (G,S) entry portmap with new(G, *) portmap
+                    isisc_multicast_acl_update(dev_id, FAL_ACL_LIST_MULTICAST, i, entry, action);
+                    rv = SW_OK;
+                }
+            }
+        }
+    }
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t isisc_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+    a_uint32_t number, count;
+    int new_index=0;
+    sw_error_t rv = SW_OK;
+    int action= MULT_ACTION_CLEAR;
+    int i=0;
+    int pm_type;
+
+    HSL_API_LOCK;
+    isisc_multicast_init(dev_id);
+    aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    //number is the total multicast ACL rules amount, stores in multi_acl_info[];
+    number = isisc_multicast_acl_query(dev_id);
+    if(number > FAL_IGMP_SG_ENTRY_MAX)
+	return SW_FAIL;
+    //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number
+    count = iterate_multicast_acl_group(number, entry);
+    if(count == 0)
+        return SW_OK;
+
+    //new_index-1 is the found entry index in multi_acl_group[]
+    new_index = mult_acl_has_entry(&entry->group, &entry->source);
+
+    MULTI_DEBUG("Start entry clear: number=%d, count=%d, new_index=%d\n", number, count, new_index);
+    if(0 == new_index || new_index > FAL_IGMP_SG_ENTRY_MAX || count > FAL_IGMP_SG_ENTRY_MAX) //new entry, the user command is wrong
+    {
+        return SW_NO_SUCH;
+    }
+
+    if( 0==multi_source_is_null(&entry->source) )  // new entry is (G, S)
+    {
+        if (portmap_null(new_index-1, entry->port_map))
+        {
+            MULTI_DEBUG("KKK entry clear, new(G,S), with null portmap. \n");
+            isisc_multicast_acl_del(dev_id, FAL_ACL_LIST_MULTICAST, new_index-1);
+            return SW_OK;
+        }
+        else
+        {
+            MULTI_DEBUG("KKK entry clear, new(G,S), with NOT null portmap. \n");
+            /* If (G,*) doesn't exist, [count-1] is the last specfic group, maybe(G,*) */
+            if(0 == multi_source_is_null(&(multi_acl_group[count-1].entry.source)))
+            {
+                isisc_multicast_acl_update(dev_id, FAL_ACL_LIST_MULTICAST, new_index-1, entry, action);
+            }
+            else //(G,*) exist
+            {
+                pm_type = portmap_clear_type(count-1, new_index-1, entry->port_map);
+                if(pm_type == 0)
+                    return SW_NO_CHANGE;
+                else if(pm_type == 1)
+                {
+                    isisc_multicast_acl_del(dev_id, FAL_ACL_LIST_MULTICAST, new_index-1);
+                    return SW_OK;
+                }
+                else
+                {
+                    //normal update; consider here...wangson
+                    isisc_multicast_acl_update(dev_id, FAL_ACL_LIST_MULTICAST, new_index-1, entry, action);
+                }
+            }
+        }
+        return SW_OK;
+    }
+    else  //clear entry is (G,*)
+    {
+        MULTI_DEBUG("Here, new_index[%d]>=0, new portmap to clear is %x\n", new_index, entry->port_map);
+        if (portmap_null(new_index-1, entry->port_map))
+        {
+            isisc_multicast_acl_del(dev_id, FAL_ACL_LIST_MULTICAST+1, new_index-1);
+            rv = SW_OK;
+        }
+        else
+        {
+            MULTI_DEBUG("Update (G,*)!, new_index=%d, pm=%x\n", new_index, entry->port_map);
+            isisc_multicast_acl_update(dev_id, FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action);
+        }
+        MULTI_DEBUG("KKK, ready clear (G, S*), count=%d\n", count);
+#if 0
+        if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry
+        {
+            //count must >=2
+            for(i=count-2; i>=0; i--)
+            {
+                if(portmap_null(i, entry->port_map))
+                {
+                    MULTI_DEBUG("portmap_null, i=%d\n", i);
+                    isisc_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+                    rv = SW_NO_MORE;
+                }
+                else
+                {
+                    //Update all (G,S) entry portmap with new(G, *) portmap
+                    isisc_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+                    rv = SW_OK;
+                }
+            }
+        }
+#else
+        if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry
+        {
+            //count must >=2
+            for(i=count-2; i>=0&&i<FAL_IGMP_SG_ENTRY_MAX; i--)
+            {
+                //PortMap of entry (S,G) == (*,G) portmap after clear?
+                if((multi_acl_group[new_index-1].entry.port_map&(~(entry->port_map))) ==
+                        multi_acl_group[i].entry.port_map)
+                    isisc_multicast_acl_del(dev_id, FAL_ACL_LIST_MULTICAST, i);
+                else
+                    //Update all (G,S) entry portmap with new(G, *) portmap
+                    isisc_multicast_acl_update(dev_id, FAL_ACL_LIST_MULTICAST, i, entry, action);
+                rv = SW_OK;
+            }
+        }
+#endif
+    }
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+static void
+print_ip4addr(char * param_name, a_uint32_t * buf,
+              a_uint32_t size)
+{
+    a_uint32_t i;
+    fal_ip4_addr_t ip4;
+
+    ip4 = *((fal_ip4_addr_t *) buf);
+    aos_printk("%s", param_name);
+    for (i = 0; i < 3; i++)
+    {
+        aos_printk("%d.", (ip4 >> (24 - i * 8)) & 0xff);
+    }
+    aos_printk("%d", (ip4 & 0xff));
+}
+static void
+print_ip6addr(char * param_name, a_uint32_t * buf,
+              a_uint32_t size)
+{
+    a_uint32_t i;
+    fal_ip6_addr_t ip6;
+
+    ip6 = *(fal_ip6_addr_t *) buf;
+    aos_printk("%s", param_name);
+    for (i = 0; i < 3; i++)
+    {
+        aos_printk("%x:%x:", (ip6.ul[i] >> 16) & 0xffff, ip6.ul[i] & 0xffff);
+    }
+    aos_printk("%x:%x", (ip6.ul[3] >> 16) & 0xffff, ip6.ul[3] & 0xffff);
+}
+sw_error_t isisc_igmp_sg_entry_show(a_uint32_t dev_id)
+{
+    a_uint32_t number;
+    int i;
+
+    HSL_API_LOCK;
+    isisc_multicast_init(dev_id);
+    aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    //number is the total multicast ACL rules amount, stores in multi_acl_info[];
+    number = isisc_multicast_acl_query(dev_id);
+
+    for(i=0; i<number; i++)
+    {
+        if(0 == multi_acl_info[i].entry.group.type)  //ipv4
+        {
+            aos_printk("\n[%d]:", i);
+            print_ip4addr(" [Group IPv4 addr]:", (a_uint32_t *)&(multi_acl_info[i].entry.group.u.ip4_addr), sizeof (fal_ip4_addr_t));
+            print_ip4addr(" [Source IPv4 addr]:", (a_uint32_t *)&(multi_acl_info[i].entry.source.u.ip4_addr), sizeof (fal_ip4_addr_t));
+            aos_printk("\n     [Portmap]: 0x%x ", multi_acl_info[i].entry.port_map);
+            aos_printk(" [Vlanid]: %d ", multi_acl_info[i].entry.vlan_id);
+        }
+        else if(1 == multi_acl_info[i].entry.group.type)  //ipv6
+        {
+            aos_printk("\n[%d]:", i);
+            print_ip6addr(" [Group IPv6 addr]: ", (a_uint32_t *)&(multi_acl_info[i].entry.group.u.ip6_addr), sizeof (fal_ip6_addr_t));
+            print_ip6addr(" [Source IPv6 addr]: ", (a_uint32_t *)&(multi_acl_info[i].entry.source.u.ip6_addr), sizeof (fal_ip6_addr_t));
+            aos_printk("\n     [Portmap]: 0x%x ", multi_acl_info[i].entry.port_map);
+            aos_printk(" [Vlanid]: %d ", multi_acl_info[i].entry.vlan_id);
+        }
+
+    }
+    aos_printk("\n\nTotal %d multicast ACL rules.\n", number);
+    HSL_API_UNLOCK;
+
+    return SW_OK;
+}
+
+void
+isisc_multicast_init(a_uint32_t dev_id)
+{
+    sw_error_t val;
+
+    isisc_acl_status_set(dev_id, 1);
+
+    val = isisc_acl_list_creat(dev_id, FAL_ACL_LIST_MULTICAST, FAL_MULTICAST_PRI);
+    if(val !=SW_OK && val != SW_ALREADY_EXIST)
+        aos_printk("Multicast 1 acl list create error, val=%d\n", val);
+
+    val = isisc_acl_list_creat(dev_id, FAL_ACL_LIST_MULTICAST+1, FAL_MULTICAST_PRI+1);
+    if(val !=SW_OK && val != SW_ALREADY_EXIST)
+        aos_printk("Multicast 2 acl list create error, val=%d\n", val);
+
+}
+
+sw_error_t isisc_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t *info)
+{
+    a_uint32_t number;
+    int i;
+
+    HSL_API_LOCK;
+    isisc_multicast_init(dev_id);
+    aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+    /*number is the total multicast ACL rules amount, stores in multi_acl_info[];*/
+    number = isisc_multicast_acl_query(dev_id);
+    if(number > FAL_IGMP_SG_ENTRY_MAX)
+    {
+	    HSL_API_UNLOCK;
+	    return SW_FAIL;
+    }
+    info->cnt = number;
+
+    for(i=0; i<number; i++)
+    {
+        aos_mem_copy(&(info->acl_info[i]), &(multi_acl_info[i]), sizeof(multi_acl_info_t));
+    }
+    HSL_API_UNLOCK;
+
+    return SW_OK;
+}
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_nat.c b/qca-ssdk/src/hsl/isisc/isisc_nat.c
new file mode 100755
index 0000000..8309761
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_nat.c
@@ -0,0 +1,2468 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_ip ISISC_NAT
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_nat.h"
+#include "isisc_reg.h"
+#if defined(IN_NAT_HELPER)
+#include "isisc_nat_helper.h"
+#endif
+
+#define ISISC_HOST_ENTRY_DATA0_ADDR              0x0e80
+#define ISISC_HOST_ENTRY_DATA1_ADDR              0x0e84
+#define ISISC_HOST_ENTRY_DATA2_ADDR              0x0e88
+#define ISISC_HOST_ENTRY_DATA3_ADDR              0x0e8c
+#define ISISC_HOST_ENTRY_DATA4_ADDR              0x0e90
+#define ISISC_HOST_ENTRY_DATA5_ADDR              0x0e94
+#define ISISC_HOST_ENTRY_DATA6_ADDR              0x0e98
+#define ISISC_HOST_ENTRY_DATA7_ADDR              0x0e58
+
+#define ISISC_HOST_ENTRY_REG_NUM                 8
+
+#define ISISC_NAT_ENTRY_FLUSH                    1
+#define ISISC_NAT_ENTRY_ADD                      2
+#define ISISC_NAT_ENTRY_DEL                      3
+#define ISISC_NAT_ENTRY_NEXT                     4
+#define ISISC_NAT_ENTRY_SEARCH                   5
+
+#define ISISC_ENTRY_NAPT                         0
+#define ISISC_ENTRY_NAT                          2
+#define ISISC_ENTRY_ARP                          3
+
+#define ISISC_PUB_ADDR_NUM                       16
+#define ISISC_PUB_ADDR_TBL0_ADDR                 0x5aa00
+#define ISISC_PUB_ADDR_TBL1_ADDR                 0x5aa04
+#define ISISC_PUB_ADDR_EDIT0_ADDR                0x02100
+#define ISISC_PUB_ADDR_EDIT1_ADDR                0x02104
+#define ISISC_PUB_ADDR_OFFLOAD_ADDR              0x2f000
+#define ISISC_PUB_ADDR_VALID_ADDR                0x2f040
+
+#define ISISC_NAT_ENTRY_NUM                      32
+#define ISISC_NAPT_ENTRY_NUM                     1024
+
+#define ISISC_NAT_COUTER_ADDR                    0x2b000
+
+#define ISISC_NAT_PORT_NUM                       255
+
+static a_uint32_t isisc_nat_snap[SW_MAX_NR_DEV] = { 0 };
+extern a_uint32_t isisc_nat_global_status;
+
+static sw_error_t
+_isisc_nat_feature_check(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (S17C_DEVICE_ID == entry)
+    {
+        return SW_OK;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+}
+
+static sw_error_t
+_isisc_ip_prvaddr_sw_to_hw(a_uint32_t dev_id, fal_ip4_addr_t sw_addr,
+                          a_uint32_t * hw_addr)
+{
+    /*
+        sw_error_t rv;
+        a_uint32_t data;
+
+        HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        if (data) {
+            *hw_addr = (sw_addr & 0xff) | (((sw_addr >> 16) & 0xf) << 8);
+        } else {
+            *hw_addr = sw_addr & 0xfff;
+        }
+    */
+    *hw_addr = sw_addr;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_prvaddr_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_addr,
+                          fal_ip4_addr_t * sw_addr)
+{
+    /*
+        sw_error_t rv;
+        a_uint32_t data, addr;
+
+        HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+                          (a_uint8_t *) (&addr), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        if (data) {
+            *sw_addr = ((addr & 0xff) << 8) | (((addr >> 8) & 0xfff) << 8)
+                | (hw_addr & 0xff) | (((hw_addr >> 8) & 0xf) << 16);
+        } else {
+            *sw_addr = (addr << 12) | (hw_addr & 0xfff);
+        }
+        */
+    *sw_addr = hw_addr;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id,
+                      a_uint32_t counter[4])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    addr = ISISC_NAT_COUTER_ADDR + (cnt_id << 4);
+    for (i = 0; i < 4; i++)
+    {
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(counter[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        addr += 4;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op)
+{
+    a_uint32_t busy = 1, i = 0x100, entry = 0;
+    sw_error_t rv;
+
+    while (busy && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+                          sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry);
+    }
+
+    if (i == 0)
+    {
+        return SW_BUSY;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_BUSY, 1, entry);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_SEL, entry_type, entry);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, ENTRY_FUNC, op, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    busy = 1;
+    i = 0x1000;
+    while (busy && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+                          sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry);
+#if 1
+        if(ISISC_NAT_ENTRY_SEARCH == op &&  busy) break;
+#endif
+    }
+
+    if (i == 0)
+    {
+        return SW_BUSY;
+    }
+
+    /* hardware requirement, we should delay... */
+    if ((ISISC_NAT_ENTRY_FLUSH == op) && (ISISC_ENTRY_NAPT == entry_type))
+    {
+        aos_mdelay(10);
+    }
+
+    /* hardware requirement, we should read again... */
+    HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, busy, entry);
+    if (!busy)
+    {
+        if (ISISC_NAT_ENTRY_NEXT == op)
+        {
+            return SW_NO_MORE;
+        }
+        else if (ISISC_NAT_ENTRY_SEARCH == op)
+        {
+            return SW_NOT_FOUND;
+        }
+        else
+        {
+            return SW_FAIL;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_sw_to_hw(a_uint32_t dev_id, fal_nat_entry_t * entry, a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    if (FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & entry->flags)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    reg[0] = entry->trans_addr;
+
+    if (FAL_NAT_ENTRY_PORT_CHECK & entry->flags)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY3, PORT_EN, 1, reg[3]);
+        SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_RANGE, entry->port_range, reg[1]);
+        if (ISISC_NAT_PORT_NUM < entry->port_range)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_NUM, entry->port_num, reg[1]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY3, PORT_EN, 0, reg[3]);
+    }
+
+    rv = _isisc_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]);
+    SW_SET_REG_BY_FIELD(NAT_ENTRY2, PRV_IPADDR1, (data >> 8), reg[2]);
+
+    if (FAL_MAC_FRWRD == entry->action)
+    {
+        if (A_TRUE == entry->mirror_en)
+        {
+            SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 0, reg[2]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 3, reg[2]);
+        }
+    }
+    else if (FAL_MAC_CPY_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 2, reg[2]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 1, reg[2]);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->counter_en)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]);
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]);
+    }
+
+    if (FAL_NAT_ENTRY_PROTOCOL_ANY & entry->flags)
+    {
+        data = 3;
+    }
+    else if ((FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags)
+             && (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags))
+    {
+        data = 2;
+    }
+    else if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags)
+    {
+        data = 0;
+    }
+    else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(NAT_ENTRY3, PRO_TYP, data, reg[3]);
+
+    SW_SET_REG_BY_FIELD(NAT_ENTRY2, HASH_KEY, entry->slct_idx, reg[2]);
+
+    SW_SET_REG_BY_FIELD(NAT_ENTRY3, ENTRY_VALID, 1, reg[3]);
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[], fal_nat_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, cnt[4] = {0};
+
+    entry->trans_addr = reg[0];
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY3, PORT_EN, data, reg[3]);
+    if (data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PORT_CHECK;
+        SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_RANGE, data, reg[1]);
+        entry->port_range = data;
+        SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_NUM, data, reg[1]);
+        entry->port_num = data;
+    }
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]);
+    entry->src_addr = data;
+    SW_GET_FIELD_BY_REG(NAT_ENTRY2, PRV_IPADDR1, data, reg[2]);
+    data = (entry->src_addr & 0xff) | (data << 8);
+
+    rv = _isisc_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY2, ACTION, data, reg[2]);
+    entry->action = FAL_MAC_FRWRD;
+    if (0 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+    else if (2 == data)
+    {
+        entry->action = FAL_MAC_CPY_TO_CPU;
+    }
+    else if (1 == data)
+    {
+        entry->action = FAL_MAC_RDT_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_EN, data, reg[2]);
+    if (data)
+    {
+        entry->counter_en = A_TRUE;
+        SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]);
+
+        rv = _isisc_nat_counter_get(dev_id, entry->counter_id, cnt);
+        SW_RTN_ON_ERROR(rv);
+
+        entry->ingress_packet = cnt[0];
+        entry->ingress_byte = cnt[1];
+        entry->egress_packet = cnt[2];
+        entry->egress_byte = cnt[3];
+    }
+    else
+    {
+        entry->counter_en = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY3, PRO_TYP, data, reg[3]);
+    if (3 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_ANY;
+    }
+    else if (2 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP;
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP;
+    }
+    else if (1 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP;
+    }
+    else if (0 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP;
+    }
+
+    SW_GET_FIELD_BY_REG(NAT_ENTRY2, HASH_KEY, data, reg[2]);
+    entry->slct_idx = data;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_napt_sw_to_hw(a_uint32_t dev_id, fal_napt_entry_t * entry,
+                    a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    reg[0] = entry->dst_addr;
+
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]);
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]);
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]);
+
+    rv = _isisc_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]);
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]);
+
+    if (!(FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & entry->flags))
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+
+    if (FAL_MAC_FRWRD == entry->action)
+    {
+        if (A_TRUE == entry->mirror_en)
+        {
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 0, reg[3]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 3, reg[3]);
+        }
+    }
+    else if (FAL_MAC_CPY_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 2, reg[3]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->action)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 1, reg[3]);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->counter_en)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]);
+    }
+
+    data = 2;
+    if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags)
+    {
+        data = 0;
+    }
+    else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags)
+    {
+        data = 1;
+    }
+    else if (FAL_NAT_ENTRY_PROTOCOL_PPTP & entry->flags)
+    {
+        data = 3;
+    }
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY3, PROT_TYP, data, reg[3]);
+
+    SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_napt_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[],
+                    fal_napt_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, cnt[4] = {0};
+
+    entry->dst_addr = reg[0];
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]);
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]);
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]);
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY2, SRC_IPADDR0, data, reg[2]);
+    entry->src_addr = data;
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY3, SRC_IPADDR1, data, reg[3]);
+    data =  (entry->src_addr & 0xfff) | (data << 12);
+    rv = _isisc_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr));
+    SW_RTN_ON_ERROR(rv);
+
+    entry->flags |= FAL_NAT_ENTRY_TRANS_IPADDR_INDEX;
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY3, ACTION, data, reg[3]);
+    entry->action = FAL_MAC_FRWRD;
+    if (0 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+    else if (2 == data)
+    {
+        entry->action = FAL_MAC_CPY_TO_CPU;
+    }
+    else if (1 == data)
+    {
+        entry->action = FAL_MAC_RDT_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_EN, data, reg[3]);
+    if (data)
+    {
+        entry->counter_en = A_TRUE;
+        SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]);
+
+        rv = _isisc_nat_counter_get(dev_id, entry->counter_id, cnt);
+        SW_RTN_ON_ERROR(rv);
+
+        entry->ingress_packet = cnt[0];
+        entry->ingress_byte = cnt[1];
+        entry->egress_packet = cnt[2];
+        entry->egress_byte = cnt[3];
+    }
+    else
+    {
+        entry->counter_en = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY3, PROT_TYP, data, reg[3]);
+    if (0 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP;
+    }
+    else if (1 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP;
+    }
+    else if (3 == data)
+    {
+        entry->flags |= FAL_NAT_ENTRY_PROTOCOL_PPTP;
+    }
+
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    for (i = 0; i < ISISC_HOST_ENTRY_REG_NUM; i++)
+    {
+        if((ISISC_HOST_ENTRY_REG_NUM - 1) == i)
+        {
+            addr = ISISC_HOST_ENTRY_DATA7_ADDR;
+        }
+        else
+        {
+            addr = ISISC_HOST_ENTRY_DATA0_ADDR + (i << 2);
+        }
+
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&reg[i]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+    a_uint32_t i, addr;
+
+    for (i = 0; i < ISISC_HOST_ENTRY_REG_NUM; i++)
+    {
+        if((ISISC_HOST_ENTRY_REG_NUM -1) == i)
+        {
+            addr = ISISC_HOST_ENTRY_DATA7_ADDR;
+        }
+        else
+        {
+            addr = ISISC_HOST_ENTRY_DATA0_ADDR + (i << 2);
+        }
+
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&reg[i]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_add(a_uint32_t dev_id, fal_nat_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < ISISC_NAT_ENTRY_NUM; i++)
+    {
+        if (!(isisc_nat_snap[dev_id] & (0x1 << i)))
+        {
+            break;
+        }
+    }
+
+    if (ISISC_NAT_ENTRY_NUM == i)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    entry->entry_id = i;
+
+    rv = _isisc_nat_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_ADD);
+    SW_RTN_ON_ERROR(rv);
+
+    isisc_nat_snap[dev_id] |= (0x1 << i);
+    entry->entry_id = i;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NAT_ENTRY_ID_EN & del_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, ENTRY_FUNC, ISISC_NAT_ENTRY_DEL, reg[7]);
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+
+        rv = _isisc_nat_down_to_hw(dev_id, reg);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_DEL);
+        SW_RTN_ON_ERROR(rv);
+
+        isisc_nat_snap[dev_id] &= (~(0x1 << entry->entry_id));
+    }
+    else
+    {
+        rv = _isisc_nat_down_to_hw(dev_id, reg);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_FLUSH);
+        SW_RTN_ON_ERROR(rv);
+
+        isisc_nat_snap[dev_id] = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NAT_ENTRY_ID_EN != get_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (!(isisc_nat_snap[dev_id] & (0x1 << entry->entry_id)))
+    {
+        return SW_NOT_FOUND;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+
+    rv = _isisc_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_SEARCH);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_hw_to_sw(dev_id, reg, entry);
+    return rv;
+}
+
+static sw_error_t
+_isisc_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+               fal_nat_entry_t * nat_entry)
+{
+    a_uint32_t i, idx, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == nat_entry->entry_id)
+    {
+        idx = 0;
+    }
+    else
+    {
+        if ((ISISC_NAT_ENTRY_NUM - 1) == nat_entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = nat_entry->entry_id + 1;
+        }
+    }
+
+    for (i = idx; i < ISISC_NAT_ENTRY_NUM; i++)
+    {
+        if (isisc_nat_snap[dev_id] & (0x1 << i))
+        {
+            break;
+        }
+    }
+
+    if (ISISC_NAT_ENTRY_NUM == i)
+    {
+        return SW_NO_MORE;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, i, reg[7]);
+
+    rv = _isisc_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_SEARCH);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    aos_mem_zero(nat_entry, sizeof (fal_nat_entry_t));
+
+    rv = _isisc_nat_hw_to_sw(dev_id, reg, nat_entry);
+    SW_RTN_ON_ERROR(rv);
+
+    nat_entry->entry_id = i;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                       a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!(isisc_nat_snap[dev_id] & (0x1 << entry_id)))
+    {
+        return SW_NOT_FOUND;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry_id, reg[7]);
+
+    rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_SEARCH);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 0, reg[2]);
+    }
+    else if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]);
+        SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, cnt_id, reg[2]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    /* needn't set TBL_IDX, keep hardware register value */
+
+    rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_DEL);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    /* needn't set TBL_IDX, keep hardware register value */
+
+    rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_ADD);
+    return rv;
+}
+
+static sw_error_t
+_isisc_napt_add(a_uint32_t dev_id, fal_napt_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_napt_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_ADD);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NAT_ENTRY_ID_EN & del_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_NAT_ENTRY_KEY_EN & del_mode)
+    {
+        rv = _isisc_napt_sw_to_hw(dev_id, entry, reg);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _isisc_nat_down_to_hw(dev_id, reg);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_DEL);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _isisc_nat_up_to_sw(dev_id, reg);
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+        return SW_OK;
+    }
+    else
+    {
+        if (FAL_NAT_ENTRY_PUBLIC_IP_EN & del_mode)
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_PIP, 1, reg[7]);
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+        }
+
+        if (FAL_NAT_ENTRY_SOURCE_IP_EN & del_mode)
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SIP, 1, reg[7]);
+            rv = _isisc_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+            SW_RTN_ON_ERROR(rv);
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]);
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]);
+        }
+
+        if (FAL_NAT_ENTRY_AGE_EN & del_mode)
+        {
+            SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]);
+            SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]);
+        }
+
+        rv = _isisc_nat_down_to_hw(dev_id, reg);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_FLUSH);
+        return rv;
+    }
+}
+
+static sw_error_t
+_isisc_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t found, age, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+#if 0
+    if (FAL_NAT_ENTRY_ID_EN != get_mode)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+#else
+    rv = _isisc_napt_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+    rv = _isisc_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_SEARCH);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, found, reg[7]);
+    SW_GET_FIELD_BY_REG(NAPT_ENTRY4, AGE_FLAG,  age, reg[4]);
+    if (found && age)
+    {
+        found = 1;
+    }
+    else
+    {
+        found = 0;
+    }
+
+    rv = _isisc_napt_hw_to_sw(dev_id, reg, entry);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!found)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX,   entry->entry_id, reg[7]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                fal_napt_entry_t * napt_entry)
+{
+    a_uint32_t data, idx, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == napt_entry->entry_id)
+    {
+        idx = ISISC_NAPT_ENTRY_NUM - 1;
+    }
+    else
+    {
+        if ((ISISC_NAPT_ENTRY_NUM - 1) == napt_entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = napt_entry->entry_id;
+        }
+    }
+
+    if (FAL_NAT_ENTRY_PUBLIC_IP_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_PIP, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, napt_entry->trans_addr, reg[2]);
+    }
+
+    if (FAL_NAT_ENTRY_SOURCE_IP_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SIP, 1, reg[7]);
+        rv = _isisc_ip_prvaddr_sw_to_hw(dev_id, napt_entry->src_addr, &data);
+        SW_RTN_ON_ERROR(rv);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]);
+    }
+
+    if (FAL_NAT_ENTRY_AGE_EN & next_mode)
+    {
+        SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, napt_entry->status, reg[4]);
+    }
+
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, idx, reg[7]);
+
+    rv = _isisc_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_NEXT);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    aos_mem_zero(napt_entry, sizeof (fal_nat_entry_t));
+
+    rv = _isisc_napt_hw_to_sw(dev_id, reg, napt_entry);
+    SW_RTN_ON_ERROR(rv);
+
+#if 0
+    a_uint32_t temp=0, complete=0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&temp),
+                      sizeof (a_uint32_t));
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, complete, temp);
+
+    if (!complete)
+    {
+        return SW_NO_MORE;
+    }
+#endif
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, napt_entry->entry_id, reg[7]);
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                        a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    tbl_idx = (entry_id - 1) & 0x3ff;
+    SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+
+    rv = _isisc_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_NEXT);
+    if (SW_OK != rv)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    rv = _isisc_nat_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+    if (entry_id != tbl_idx)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 0, reg[3]);
+    }
+    else if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]);
+        SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, cnt_id, reg[3]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_DEL);
+    SW_RTN_ON_ERROR(rv);
+
+    reg[4] = 0x0;
+    rv = _isisc_nat_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_ADD);
+    return rv;
+}
+
+static sw_error_t
+_isisc_nat_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_nat_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_napt_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_napt_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NAPT_FULL_CONE == mode)
+    {
+        data = 0;
+    }
+    else if (FAL_NAPT_STRICT_CONE == mode)
+    {
+        data = 1;
+    }
+    else if ((FAL_NAPT_PORT_STRICT == mode)
+             || (FAL_NAPT_SYNMETRIC == mode))
+    {
+        data = 2;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        *mode = FAL_NAPT_FULL_CONE;
+    }
+    else if (1 == data)
+    {
+        *mode = FAL_NAPT_STRICT_CONE;
+    }
+    else
+    {
+        *mode = FAL_NAPT_PORT_STRICT;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if ((FAL_NAT_HASH_KEY_PORT & mode)
+            && (FAL_NAT_HASH_KEY_IPADDR & mode))
+    {
+        data = 2;
+    }
+    else if (FAL_NAT_HASH_KEY_PORT & mode)
+    {
+        data = 0;
+    }
+    else if (FAL_NAT_HASH_KEY_IPADDR & mode)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *mode = 0;
+    if (0 == data)
+    {
+        *mode = FAL_NAT_HASH_KEY_PORT;
+    }
+    else if (1 == data)
+    {
+        *mode = FAL_NAT_HASH_KEY_IPADDR;
+    }
+    else if (2 == data)
+    {
+        *mode = FAL_NAT_HASH_KEY_PORT;
+        *mode |= FAL_NAT_HASH_KEY_IPADDR;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    data = addr;
+    HSL_REG_FIELD_SET(rv, dev_id, PRVIP_ADDR, 0, IP4_BASEADDR,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_ADDR, 0, IP4_BASEADDR,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    *addr = data;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t mask)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    data = mask;
+    HSL_REG_FIELD_SET(rv, dev_id, PRVIP_MASK, 0, IP4_BASEMASK,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+#if 0
+static sw_error_t
+_isisc_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+#if 0
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        data = (((addr >> 20) & 0xfff) << 8) | ((addr >> 8) & 0xff);
+    }
+    else
+    {
+        data = (addr >> 12) & 0xfffff;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+#endif
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+#if 0
+    sw_error_t rv;
+    a_uint32_t data, tmp;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+                      (a_uint8_t *) (&tmp), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (tmp)
+    {
+        *addr = ((data & 0xff) << 8) | (((data >> 8) & 0xfff) << 20);
+    }
+    else
+    {
+        *addr = (data & 0xfffff) << 12;
+    }
+#endif
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isisc_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * mask)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRVIP_MASK, 0, IP4_BASEMASK,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *mask = data;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_pub_addr_commit(a_uint32_t dev_id, fal_nat_pub_addr_t * entry,
+                          a_uint32_t op, a_uint32_t * empty)
+{
+    a_uint32_t index, addr, data, tbl[2] = { 0 };
+    sw_error_t rv;
+
+    *empty = ISISC_PUB_ADDR_NUM;
+    for (index = 0; index < ISISC_PUB_ADDR_NUM; index++)
+    {
+        addr = ISISC_PUB_ADDR_TBL1_ADDR + (index << 4);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]);
+        if (data)
+        {
+            addr = ISISC_PUB_ADDR_TBL0_ADDR + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[0])),
+                                  sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            if (!aos_mem_cmp
+                    ((void *) &(entry->pub_addr), (void *) &(tbl[0]),
+                     sizeof (fal_ip4_addr_t)))
+            {
+                if (ISISC_NAT_ENTRY_DEL == op)
+                {
+                    addr = ISISC_PUB_ADDR_TBL1_ADDR + (index << 4);
+                    tbl[1] = 0;
+                    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                          (a_uint8_t *) (&(tbl[1])),
+                                          sizeof (a_uint32_t));
+                    *empty = index;
+                    return rv;
+                }
+                else if (ISISC_NAT_ENTRY_ADD == op)
+                {
+                    entry->entry_id = index;
+                    return SW_ALREADY_EXIST;
+                }
+            }
+        }
+        else
+        {
+            *empty = index;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isisc_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, empty, addr, data = 0, tbl[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    tbl[0] = entry->pub_addr;
+    tbl[1] = 1;
+
+    rv = _isisc_nat_pub_addr_commit(dev_id, entry, ISISC_NAT_ENTRY_ADD, &empty);
+    if (SW_ALREADY_EXIST == rv)
+    {
+        return rv;
+    }
+
+    if (ISISC_PUB_ADDR_NUM == empty)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    for (i = 0; i < 1; i++)
+    {
+        addr = ISISC_PUB_ADDR_EDIT0_ADDR + (empty << 4) + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    addr = ISISC_PUB_ADDR_OFFLOAD_ADDR + (empty << 2);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    addr = ISISC_PUB_ADDR_VALID_ADDR;
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data |= (0x1 << empty);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < 2; i++)
+    {
+        addr = ISISC_PUB_ADDR_TBL0_ADDR + (empty << 4) + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    entry->entry_id = empty;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                       fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t empty, addr, data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_pub_addr_commit(dev_id, entry, ISISC_NAT_ENTRY_DEL, &empty);
+    SW_RTN_ON_ERROR(rv);
+
+    addr = ISISC_PUB_ADDR_VALID_ADDR;
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0x1 << empty));
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                        fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t data, addr, idx, index, tbl[2] = {0};
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id)
+    {
+        idx = 0;
+    }
+    else
+    {
+        if ((ISISC_PUB_ADDR_NUM - 1) == entry->entry_id)
+        {
+            return SW_NO_MORE;
+        }
+        else
+        {
+            idx = entry->entry_id + 1;
+        }
+    }
+
+    for (index = idx; index < ISISC_PUB_ADDR_NUM; index++)
+    {
+        addr = ISISC_PUB_ADDR_TBL1_ADDR + (index << 4);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]);
+        if (data)
+        {
+            break;
+        }
+    }
+
+    if (ISISC_PUB_ADDR_NUM == index)
+    {
+        return SW_NO_MORE;
+    }
+
+    addr = ISISC_PUB_ADDR_TBL0_ADDR + (index << 4);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    entry->entry_id = index;
+    entry->pub_addr = tbl[0];
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_MAC_DROP == cmd)
+    {
+        data = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_DROP;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+isisc_nat_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t index, addr, data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_nat_feature_check(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    isisc_nat_snap[dev_id] = 0;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_FLUSH);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_FLUSH);
+    SW_RTN_ON_ERROR(rv);
+
+    for (index = 0; index < ISISC_PUB_ADDR_NUM; index++)
+    {
+        addr = ISISC_PUB_ADDR_TBL1_ADDR + (index << 4);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Add one NAT entry to one particular device.
+ *   @details Comments:
+       Before NAT entry added ip4 private base address must be set
+       at first.
+       In parameter nat_entry entry flags must be set
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_add(dev_id, nat_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Del NAT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode NAT entry delete operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_del(a_uint32_t dev_id, a_uint32_t del_mode,
+             fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_del(dev_id, del_mode, nat_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get one NAT entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode NAT entry get operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @param[out] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_get(a_uint32_t dev_id, a_uint32_t get_mode,
+             fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_get(dev_id, get_mode, nat_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next NAT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode NAT entry next operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @param[out] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+              fal_nat_entry_t * nat_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_next(dev_id, next_mode, nat_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one NAT entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id NAT entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id,
+                      a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_counter_bind(dev_id, entry_id, cnt_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one NAPT entry to one particular device.
+ *   @details Comments:
+       Before NAPT entry added related ip4 private base address must be set
+       at first.
+       In parameter napt_entry related entry flags must be set
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_napt_add(dev_id, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Del NAPT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode NAPT entry delete operation mode
+ * @param[in] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_del(a_uint32_t dev_id, a_uint32_t del_mode,
+              fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_napt_del(dev_id, del_mode, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get one NAPT entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode NAPT entry get operation mode
+ * @param[in] nat_entry NAPT entry parameter
+ * @param[out] nat_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_get(a_uint32_t dev_id, a_uint32_t get_mode,
+              fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_napt_get(dev_id, get_mode, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next NAPT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode NAPT entry next operation mode
+ * @param[in] napt_entry NAPT entry parameter
+ * @param[out] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+               fal_napt_entry_t * napt_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_napt_next(dev_id, next_mode, napt_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one NAPT entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id NAPT entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+                       a_uint32_t cnt_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_napt_counter_bind(dev_id, entry_id, cnt_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set NAT hash mode on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mode NAT hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_hash_mode_set(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get NAT hash mode on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mode NAT hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_hash_mode_get(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_napt_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working status of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_napt_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working mode of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mode NAPT mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_napt_mode_set(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working mode of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mode NAPT mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_napt_mode_get(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP4 private base address on a particular device
+ *   @details Comments:
+        Only 20bits is meaning which 20bits is determined by private address mode.
+ * @param[in] dev_id device id
+ * @param[in] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_prv_base_addr_set(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[out] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_prv_base_addr_get(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mask private base mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t mask)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_prv_base_mask_set(dev_id, mask);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mask private base mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * mask)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_prv_base_mask_get(dev_id, mask);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#if 0
+/**
+ * @brief Set IP4 private base address on a particular device
+ *   @details Comments:
+        Only 20bits is meaning which 20bits is determined by private address mode.
+ * @param[in] dev_id device id
+ * @param[in] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_psr_prv_base_addr_set(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[out] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_psr_prv_base_addr_get(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set IP4 private base address mode on a particular device
+ *   @details Comments:
+        If map_en equal true means bits31-20 bits15-8 are base address
+        else bits31-12 are base address.
+ * @param[in] dev_id device id
+ * @param[in] map_en private base mapping mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en)
+{
+    sw_error_t rv = SW_OK;
+
+    HSL_API_LOCK;
+    /*rv = _isisc_nat_prv_addr_mode_set(dev_id, map_en);*/
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Get IP4 private base address mode on a particular device
+ * @param[in] dev_id device id
+ * @param[out] map_en private base mapping mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+isisc_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en)
+{
+    sw_error_t rv = SW_OK;
+
+    HSL_API_LOCK;
+    /*rv = _isisc_nat_prv_addr_mode_get(dev_id, map_en);*/
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one public address entry to one particular device.
+ *   @details Comments:
+       Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_pub_addr_add(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one public address entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operaton mode
+ * @param[in] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+                      fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_pub_addr_del(dev_id, del_mode, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next public address entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operaton mode
+ * @param[out] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+                       fal_nat_pub_addr_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_pub_addr_next(dev_id, next_mode, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set forwarding command for those packets miss NAT entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_unk_session_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get forwarding command for those packets miss NAT entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nat_unk_session_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] portbmp port bitmap
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_global_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t portbmp)
+{
+    sw_error_t rv = SW_OK;
+
+    HSL_API_LOCK;
+    printk("enable:%d\n", enable);
+    if(enable) {
+        if(isisc_nat_global_status == 0) {
+            isisc_nat_global_status = 1;
+#if defined(IN_NAT_HELPER)
+            ISISC_NAT_HELPER_INIT(rv, dev_id, portbmp);
+#endif
+        }
+    } else {
+        if(isisc_nat_global_status == 1) {
+            isisc_nat_global_status = 0;
+#if defined(IN_NAT_HELPER)
+            ISISC_NAT_HELPER_CLEANUP(rv, dev_id);
+#endif
+        }
+    }
+    //rv = SW_OK;
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isisc_nat_init(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = isisc_nat_reset(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->nat_add = isisc_nat_add;
+        p_api->nat_del = isisc_nat_del;
+        p_api->nat_get = isisc_nat_get;
+        p_api->nat_next = isisc_nat_next;
+        p_api->nat_counter_bind = isisc_nat_counter_bind;
+        p_api->napt_add = isisc_napt_add;
+        p_api->napt_del = isisc_napt_del;
+        p_api->napt_get = isisc_napt_get;
+        p_api->napt_next = isisc_napt_next;
+        p_api->napt_counter_bind = isisc_napt_counter_bind;
+        p_api->nat_status_set = isisc_nat_status_set;
+        p_api->nat_status_get = isisc_nat_status_get;
+        p_api->nat_hash_mode_set = isisc_nat_hash_mode_set;
+        p_api->nat_hash_mode_get = isisc_nat_hash_mode_get;
+        p_api->napt_status_set = isisc_napt_status_set;
+        p_api->napt_status_get = isisc_napt_status_get;
+        p_api->napt_mode_set = isisc_napt_mode_set;
+        p_api->napt_mode_get = isisc_napt_mode_get;
+        p_api->nat_pub_addr_add = isisc_nat_pub_addr_add;
+        p_api->nat_pub_addr_del = isisc_nat_pub_addr_del;
+        p_api->nat_pub_addr_next = isisc_nat_pub_addr_next;
+        p_api->nat_unk_session_cmd_set = isisc_nat_unk_session_cmd_set;
+        p_api->nat_unk_session_cmd_get = isisc_nat_unk_session_cmd_get;
+        p_api->nat_prv_base_addr_set = isisc_nat_prv_base_addr_set;
+        p_api->nat_prv_base_addr_get = isisc_nat_prv_base_addr_get;
+        p_api->nat_prv_base_mask_set = isisc_nat_prv_base_mask_set;
+        p_api->nat_prv_base_mask_get = isisc_nat_prv_base_mask_get;
+        p_api->nat_global_set = isisc_nat_global_set;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/isisc/isisc_port_ctrl.c b/qca-ssdk/src/hsl/isisc/isisc_port_ctrl.c
new file mode 100755
index 0000000..2549b0d
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_port_ctrl.c
@@ -0,0 +1,2797 @@
+/*
+ * Copyright (c) 2012, 2015-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_port_ctrl ISISC_PORT_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_port_ctrl.h"
+#include "isisc_reg.h"
+#include "hsl_phy.h"
+
+static a_bool_t
+_isisc_port_phy_connected(a_uint32_t dev_id, fal_port_t port_id)
+{
+    if ((0 == port_id) || (6 == port_id))
+    {
+        return A_FALSE;
+    }
+    else
+    {
+        return A_TRUE;
+    }
+}
+
+static sw_error_t
+_isisc_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_duplex_t duplex)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id, reg_save, reg_val = 0, force, tmp;
+    hsl_phy_ops_t *phy_drv;
+    a_bool_t status;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_DUPLEX_BUTT <= duplex)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+	SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, tmp, reg_val);
+
+    /* for those ports without PHY device we set MAC register */
+    if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+        if (FAL_HALF_DUPLEX == duplex)
+        {
+			if (tmp == 0)
+				return SW_OK;
+            SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_val);
+        }
+        else
+        {
+			if (tmp == 1)
+				return SW_OK;
+            SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val);
+        }
+        reg_save = reg_val;
+    }
+    else
+    {
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+		if (NULL == phy_drv->phy_duplex_set)
+			return SW_NOT_SUPPORTED;
+		/* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
+		rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR(rv);
+		rv = phy_drv->phy_duplex_get (dev_id, phy_id, &tmp);
+		SW_RTN_ON_ERROR(rv);
+		status = phy_drv->phy_autoneg_status_get (dev_id, phy_id);
+		if ((tmp == duplex) && (status == A_FALSE))
+			return SW_OK;
+        reg_save = reg_val;
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                          (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+        rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex);
+        SW_RTN_ON_ERROR(rv);
+
+        /* If MAC not in sync with PHY mode, the behavior is undefine.
+           You must be careful... */
+        SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save);
+        if (!force)
+        {
+            if (FAL_HALF_DUPLEX == duplex)
+            {
+                SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_save);
+            }
+            else
+            {
+                SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_save);
+            }
+        }
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_save), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_port_speed_t speed)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id, reg_save, reg_val = 0, force, tmp;
+    hsl_phy_ops_t *phy_drv;
+    a_bool_t status;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_SPEED_1000 < speed)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+	SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, tmp, reg_val);
+
+    /* for those ports without PHY device we set MAC register */
+    if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+        if (FAL_SPEED_10 == speed)
+        {
+		if (tmp == 0)
+			return SW_OK;
+            SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val);
+        }
+        else if (FAL_SPEED_100 == speed)
+        {
+		if (tmp == 1)
+			return SW_OK;
+            SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val);
+        }
+        else
+        {
+		if (tmp == 2)
+			return SW_OK;
+            SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val);
+        }
+        reg_save = reg_val;
+
+    }
+    else
+    {
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+		if (NULL == phy_drv->phy_speed_set)
+			return SW_NOT_SUPPORTED;
+		/* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
+		rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR(rv);
+		rv = phy_drv->phy_speed_get (dev_id, phy_id, &tmp);
+		SW_RTN_ON_ERROR(rv);
+		status = phy_drv->phy_autoneg_status_get (dev_id, phy_id);
+		if ((tmp == speed) && (status == A_FALSE))
+			return SW_OK;
+        reg_save = reg_val;
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,  0, reg_val);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                          (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+
+        rv = phy_drv->phy_speed_set (dev_id, phy_id, speed);
+        SW_RTN_ON_ERROR(rv);
+
+        /* If MAC not in sync with PHY mode, the behavior is undefine.
+           You must be careful... */
+        SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save);
+        if (!force)
+        {
+            if (FAL_SPEED_10 == speed)
+            {
+                SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_save);
+            }
+            else if (FAL_SPEED_100 == speed)
+            {
+                SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_save);
+            }
+            else
+            {
+                SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_save);
+            }
+        }
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_save), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val, force, reg = 0, tmp;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+    if (force)
+    {
+        /* flow control isn't in force mode so can't set */
+        return SW_DISABLE;
+    }
+	tmp = reg;
+
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
+	if (tmp == reg)
+		return SW_OK;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, tmp;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+	SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, tmp, reg);
+
+    if (A_TRUE == enable)
+    {
+		if (tmp == 0)
+			return SW_OK;
+        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        /* for those ports without PHY, it can't sync flow control status */
+        if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+        {
+            return SW_DISABLE;
+        }
+		if (tmp == 1)
+			return SW_OK;
+        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_port_speed_t * pspeed)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+	{
+		return SW_BAD_PARAM;
+	}
+	/* for those ports without PHY device supposed always 1000Mbps */
+	if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+	{
+		*pspeed = FAL_SPEED_1000;
+	}
+	else
+	{
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+		if (NULL == phy_drv->phy_speed_get)
+			return SW_NOT_SUPPORTED;
+
+		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR (rv);
+
+		rv = phy_drv->phy_speed_get (dev_id, phy_id, pspeed);
+		SW_RTN_ON_ERROR (rv);
+	}
+#if 0
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, field, reg);
+    if (0 == field)
+    {
+        *pspeed = FAL_SPEED_10;
+    }
+    else if (1 == field)
+    {
+        *pspeed = FAL_SPEED_100;
+    }
+    else if (2 == field)
+    {
+        *pspeed = FAL_SPEED_1000;
+    }
+    else
+    {
+        *pspeed = FAL_SPEED_BUTT;
+        rv = SW_READ_ERROR;
+    }
+#endif
+    return rv;
+}
+static sw_error_t
+_isisc_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_duplex_t * pduplex)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK(dev_id);
+
+	if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	/* for those ports without PHY device supposed always full */
+	if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+	{
+		*pduplex = FAL_FULL_DUPLEX;
+	}
+	else
+	{
+		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+		if (NULL == phy_drv->phy_duplex_get)
+		return SW_NOT_SUPPORTED;
+
+		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+		SW_RTN_ON_ERROR (rv);
+
+		rv = phy_drv->phy_duplex_get (dev_id, phy_id, pduplex);
+		SW_RTN_ON_ERROR (rv);
+	}
+#if 0
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, field, reg);
+    if (field)
+    {
+        *pduplex = FAL_FULL_DUPLEX;
+    }
+    else
+    {
+        *pduplex = FAL_HALF_DUPLEX;
+    }
+#endif
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_restart_autoneg)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_restart_autoneg (dev_id, phy_id);
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t autoadv)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_autoneg_adv_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_autoneg_adv_set (dev_id, phy_id, autoadv);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * status)
+{
+    a_uint32_t phy_id;
+    sw_error_t rv;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_autoneg_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *status = phy_drv->phy_autoneg_status_get (dev_id, phy_id);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+   SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+   if (NULL == phy_drv->phy_autoneg_enable_set)
+       return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_autoneg_enable_set (dev_id, phy_id);
+    return rv;
+}
+
+
+static sw_error_t
+_isisc_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * autoadv)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_autoneg_adv_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *autoadv = 0;
+    rv = phy_drv->phy_autoneg_adv_get (dev_id, phy_id, autoadv);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_isisc_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t rx, reg = 0;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg);
+
+    if (1 == rx)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_isisc_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t force, reg;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+    if (0 == force)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+   SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+   if (NULL == phy_drv->phy_powersave_set)
+       return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_powersave_set (dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+   SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+   if (NULL == phy_drv->phy_powersave_get)
+       return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_powersave_get (dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_hibernation_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_hibernation_set (dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_hibernation_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_hibernation_get (dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+               fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_cdt)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_cdt (dev_id, phy_id, mdi_pair, cable_status, cable_len);
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id,
+				a_uint16_t * org_id, a_uint16_t * rev_id)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+  a_uint32_t phy_data;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_id_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_id_get (dev_id, phy_id, &phy_data);
+  SW_RTN_ON_ERROR (rv);
+
+  *org_id = (phy_data >> 16) & 0xffff;
+  *rev_id = phy_data & 0xffff;
+
+  return rv;
+}
+
+static sw_error_t
+_isisc_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK (dev_id);
+    if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_8023az_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR (rv);
+
+    rv = phy_drv->phy_8023az_set (dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id,
+		       a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK (dev_id);
+
+    if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_8023az_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR (rv);
+
+    rv = phy_drv->phy_8023az_get (dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_local_loopback_set(a_uint32_t dev_id, a_uint32_t port_id,
+	a_bool_t enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_local_loopback_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_local_loopback_set (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_isisc_port_local_loopback_get(a_uint32_t dev_id, a_uint32_t port_id,
+	a_bool_t *enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_local_loopback_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_local_loopback_get (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_isisc_port_remote_loopback_set(a_uint32_t dev_id, a_uint32_t port_id,
+	a_bool_t enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_remote_loopback_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_remote_loopback_set (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_isisc_port_remote_loopback_get(a_uint32_t dev_id, a_uint32_t port_id,
+	a_bool_t *enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_remote_loopback_set)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_remote_loopback_get (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+#endif
+static sw_error_t
+_isisc_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_header_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_NO_HEADER_EN == mode)
+    {
+        val = 0;
+    }
+    else if (FAL_ONLY_MANAGE_FRAME_EN == mode)
+    {
+        val = 1;
+    }
+    else if (FAL_ALL_TYPE_FRAME_EN == mode)
+    {
+        val = 2;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_isisc_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_header_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *mode = FAL_ONLY_MANAGE_FRAME_EN;
+    }
+    else if (2 == val)
+    {
+        *mode = FAL_ALL_TYPE_FRAME_EN;
+    }
+    else
+    {
+        *mode = FAL_NO_HEADER_EN;
+    }
+
+    return SW_OK;
+}
+#endif
+static sw_error_t
+_isisc_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_header_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_NO_HEADER_EN == mode)
+    {
+        val = 0;
+    }
+    else if (FAL_ONLY_MANAGE_FRAME_EN == mode)
+    {
+        val = 1;
+    }
+    else if (FAL_ALL_TYPE_FRAME_EN == mode)
+    {
+        val = 2;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_isisc_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_port_header_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *mode = FAL_ONLY_MANAGE_FRAME_EN;
+    }
+    else if (2 == val)
+    {
+        *mode = FAL_ALL_TYPE_FRAME_EN;
+    }
+    else
+    {
+        *mode = FAL_NO_HEADER_EN;
+    }
+
+    return SW_OK;
+}
+#endif
+static sw_error_t
+_isisc_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
+{
+    a_uint32_t reg = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        if (0xffff < type)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 1, reg);
+        SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, type, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 0, reg);
+        SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, 0, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, HEADER_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_isisc_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
+{
+    a_uint32_t data, reg = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_LEN, data, reg);
+    if (data)
+    {
+        SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_VAL, data, reg);
+        *enable = A_TRUE;
+        *type = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *type = 0;
+    }
+
+    return SW_OK;
+}
+#endif
+static sw_error_t
+_isisc_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg, force, val = 0, tmp;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+	tmp = reg;
+
+    /* for those ports without PHY device we set MAC register */
+    if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,  0, reg);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg);
+    }
+    else
+    {
+        SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN,  force, reg);
+        if (force)
+        {
+            /* link isn't in force mode so can't set */
+            return SW_DISABLE;
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg);
+        }
+    }
+	if (tmp == reg)
+		return SW_OK;
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_isisc_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TXMAC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+#endif
+static sw_error_t
+_isisc_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, force, val = 0, tmp;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+	tmp = reg;
+
+    /* for those ports without PHY device we set MAC register */
+    if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,  0, reg);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg);
+    }
+    else
+    {
+        SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN,  force, reg);
+        if (force)
+        {
+            /* link isn't in force mode so can't set */
+            return SW_DISABLE;
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg);
+        }
+    }
+	if (tmp == reg)
+		return SW_OK;
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_isisc_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RXMAC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+#endif
+static sw_error_t
+_isisc_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val, reg = 0, force, tmp;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+	tmp = reg;
+
+    /* for those ports without PHY device we set MAC register */
+    if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN,   val, reg);
+    }
+    else
+    {
+        SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+        if (force)
+        {
+            /* flow control isn't in force mode so can't set */
+            return SW_DISABLE;
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+        }
+    }
+	if (tmp == reg)
+		return SW_OK;
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_FLOW_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0, reg, force, tmp;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+	tmp = reg;
+
+    /* for those ports without PHY device we set MAC register */
+    if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN,   val, reg);
+    }
+    else
+    {
+        SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN,  force, reg);
+        if (force)
+        {
+            /* flow control isn't in force mode so can't set */
+            return SW_DISABLE;
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+        }
+    }
+	if ( tmp == reg)
+		return SW_OK;
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RX_FLOW_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+static sw_error_t
+_isisc_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+   
+   /* for those ports without PHY device supposed always link up */
+   if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+   {
+	   *status = A_TRUE;
+   }
+   else
+   {
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+   	if (NULL == phy_drv->phy_link_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR(rv);
+
+	if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id))
+	{
+            *status = A_TRUE;
+	}
+	else
+	{
+            *status = A_FALSE;
+	}
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_power_off (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_power_off)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_power_off(dev_id, phy_id);
+
+  return rv;
+}
+
+static sw_error_t
+_isisc_port_power_on (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_power_on)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_power_on(dev_id, phy_id);
+
+  return rv;
+}
+
+static sw_error_t
+_isisc_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, tmp = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, tmp, reg);
+
+    if (A_TRUE == enable)
+    {
+        if(tmp == 0)
+          return SW_OK;
+
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        if(tmp == 1)
+          return SW_OK;
+
+        /* for those ports without PHY, it can't sync link status */
+        if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+        {
+            return SW_DISABLE;
+        }
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, LINK_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_isisc_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0, tmp;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+	HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+                      (a_uint8_t *) (&tmp), sizeof (a_uint32_t));
+	if (tmp == val)
+		return SW_OK;
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_isisc_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status)
+{
+	sw_error_t rv;
+	a_uint32_t port_id;
+	a_uint32_t phy_id;
+	hsl_dev_t *pdev = NULL;
+	hsl_phy_ops_t *phy_drv;
+	a_uint32_t port_bmp[SW_MAX_NR_DEV] = {0};
+	HSL_DEV_ID_CHECK(dev_id);
+
+	pdev = hsl_dev_ptr_get(dev_id);
+	if (pdev == NULL)
+	    return SW_NOT_INITIALIZED;
+
+	port_bmp[dev_id] = qca_ssdk_phy_type_port_bmp_get(dev_id, F1_PHY_CHIP);
+
+	*status = 0x0;
+	for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+	{
+		if (port_id >= SW_MAX_NR_PORT)
+			break;
+        	/* for those ports without PHY device supposed always link up */
+        	if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+        	{
+            		*status |= (0x1 << port_id);
+		}
+		else
+		{
+			if(port_bmp[dev_id] & (0x1 << port_id))
+			{
+				SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+				if (NULL == phy_drv->phy_link_status_get)
+					return SW_NOT_SUPPORTED;
+
+				rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+				SW_RTN_ON_ERROR(rv);
+
+				if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id))
+				{
+					*status |= (0x1 << port_id);
+				}
+				else
+				{
+					*status &= ~(0x1 << port_id);
+				}
+			}
+		}
+	}
+	return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == val)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+#endif
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_port_duplex_t duplex)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_duplex_set(dev_id, port_id, duplex);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                    fal_port_speed_t speed)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_speed_set(dev_id, port_id, speed);
+    HSL_API_UNLOCK;
+    return rv;
+}
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_port_duplex_t * pduplex)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_duplex_get(dev_id, port_id, pduplex);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                    fal_port_speed_t * pspeed)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_speed_get(dev_id, port_id, pspeed);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_autoneg_enable(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_autoneg_restart(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ *   @details  Comments:
+ *   auto negotiation advtisement ability is defined by macro such as
+ *   FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t autoadv)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_autoneg_adv_set(dev_id, port_id, autoadv);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_autoneg_status_get(dev_id, port_id, status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * autoadv)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_autoneg_adv_get(dev_id, port_id, autoadv);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+/**
+ * @brief Get flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_flowctrl_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+
+/**
+ * @brief Get flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_flowctrl_forcemode_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_powersave_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_powersave_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_hibernate_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_hibernate_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Run cable diagnostic test on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mdi_pair mdi pair id
+ * @param[out] cable_status cable status
+ * @param[out] cable_len cable len
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+              fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get phy id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] org_id and rev_id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_uint16_t * org_id, a_uint16_t * rev_id)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _isisc_port_phy_id_get (dev_id, port_id, org_id, rev_id);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_8023az_set (dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get 8023az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id,
+		      a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_8023az_get (dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+isisc_port_local_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
+                     a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_local_loopback_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+isisc_port_local_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
+                     a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_local_loopback_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+isisc_port_remote_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
+                     a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_remote_loopback_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+isisc_port_remote_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
+                     a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_remote_loopback_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#endif
+
+/**
+ * @brief Set flow control(rx/tx/bp) status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_flowctrl_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_flowctrl_forcemode_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_header_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_rxhdr_mode_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_header_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_rxhdr_mode_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_header_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_txhdr_mode_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_port_header_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_txhdr_mode_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set status of Atheros header type value on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] type header type value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isisc_header_type_set(dev_id, enable, type);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+/**
+ * @brief Get status of Atheros header type value on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] type header type value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_header_type_get(dev_id, enable, type);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set status of txmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isisc_port_txmac_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+/**
+ * @brief Get status of txmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_txmac_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set status of rxmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isisc_port_rxmac_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+/**
+ * @brief Get status of rxmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_rxmac_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set status of tx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isisc_port_txfc_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get status of tx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_txfc_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of rx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isisc_port_rxfc_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of rx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_rxfc_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+/**
+ * @brief Get link status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status link status up (A_TRUE) or down (A_FALSE)
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_link_status_get(dev_id, port_id, status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief phy power off on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_power_off (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _isisc_port_power_off (dev_id, port_id);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief phy power on on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_power_on (a_uint32_t dev_id, fal_port_t port_id)
+{
+  sw_error_t rv;
+  HSL_API_LOCK;
+  rv = _isisc_port_power_on (dev_id, port_id);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Set link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isisc_port_link_forcemode_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_link_forcemode_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+/**
+ * @brief Set status of back pressure on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isisc_port_bp_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of back pressure on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_bp_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get link status on all ports.
+ * @param[in] dev_id device id
+ * @param[out] status link status bitmap and bit 0 for port 0, bi 1 for port 1, ..., etc.
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_ports_link_status_get(dev_id, status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set mac loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isisc_port_mac_loopback_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mac loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_mac_loopback_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+sw_error_t
+isisc_port_ctrl_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->port_duplex_set = isisc_port_duplex_set;
+        p_api->port_speed_set = isisc_port_speed_set;
+        p_api->port_flowctrl_set = isisc_port_flowctrl_set;
+        p_api->port_flowctrl_forcemode_set = isisc_port_flowctrl_forcemode_set;
+        p_api->port_duplex_get = isisc_port_duplex_get;
+        p_api->port_speed_get = isisc_port_speed_get;
+        p_api->port_autoneg_enable = isisc_port_autoneg_enable;
+        p_api->port_autoneg_restart = isisc_port_autoneg_restart;
+        p_api->port_autoneg_adv_set = isisc_port_autoneg_adv_set;
+        p_api->port_autoneg_status_get = isisc_port_autoneg_status_get;
+        p_api->port_autoneg_adv_get = isisc_port_autoneg_adv_get;
+#ifndef IN_PORTCONTROL_MINI
+        p_api->port_flowctrl_get = isisc_port_flowctrl_get;
+        p_api->port_flowctrl_forcemode_get = isisc_port_flowctrl_forcemode_get;
+        p_api->port_powersave_set = isisc_port_powersave_set;
+        p_api->port_powersave_get = isisc_port_powersave_get;
+        p_api->port_hibernate_set = isisc_port_hibernate_set;
+        p_api->port_hibernate_get = isisc_port_hibernate_get;
+        p_api->port_cdt = isisc_port_cdt;
+	p_api->port_phy_id_get = isisc_port_phy_id_get;
+        p_api->port_rxhdr_mode_get = isisc_port_rxhdr_mode_get;
+        p_api->port_txhdr_mode_get = isisc_port_txhdr_mode_get;
+        p_api->header_type_get = isisc_header_type_get;
+        p_api->port_txmac_status_get = isisc_port_txmac_status_get;
+        p_api->port_rxmac_status_get = isisc_port_rxmac_status_get;
+        p_api->port_8023az_set = isisc_port_8023az_set;
+        p_api->port_8023az_get = isisc_port_8023az_get;
+        p_api->port_local_loopback_set = isisc_port_local_loopback_set;
+        p_api->port_local_loopback_get = isisc_port_local_loopback_get;
+        p_api->port_remote_loopback_set = isisc_port_remote_loopback_set;
+        p_api->port_remote_loopback_get = isisc_port_remote_loopback_get;
+
+#endif
+        p_api->port_txfc_status_get = isisc_port_txfc_status_get;
+        p_api->port_rxhdr_mode_set = isisc_port_rxhdr_mode_set;
+        p_api->port_txhdr_mode_set = isisc_port_txhdr_mode_set;
+        p_api->header_type_set = isisc_header_type_set;
+        p_api->port_txmac_status_set = isisc_port_txmac_status_set;
+        p_api->port_rxmac_status_set = isisc_port_rxmac_status_set;
+        p_api->port_txfc_status_set = isisc_port_txfc_status_set;
+        p_api->port_rxfc_status_set = isisc_port_rxfc_status_set;
+        p_api->port_link_status_get = isisc_port_link_status_get;
+        p_api->port_rxfc_status_get = isisc_port_rxfc_status_get;
+        p_api->port_power_off = isisc_port_power_off;
+        p_api->port_power_on = isisc_port_power_on;
+        p_api->port_link_forcemode_set = isisc_port_link_forcemode_set;
+        p_api->port_link_forcemode_get = isisc_port_link_forcemode_get;
+#ifndef IN_PORTCONTROL_MINI
+        p_api->port_bp_status_set = isisc_port_bp_status_set;
+        p_api->port_bp_status_get = isisc_port_bp_status_get;
+        p_api->ports_link_status_get = isisc_ports_link_status_get;
+        p_api->port_mac_loopback_set=isisc_port_mac_loopback_set;
+        p_api->port_mac_loopback_get=isisc_port_mac_loopback_get;
+#endif
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_portvlan.c b/qca-ssdk/src/hsl/isisc/isisc_portvlan.c
new file mode 100755
index 0000000..bf47d00
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_portvlan.c
@@ -0,0 +1,2291 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_port_vlan ISISC_PORT_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_portvlan.h"
+#include "isisc_reg.h"
+
+#define MAX_VLAN_ID          4095
+#define ISISC_MAX_VLAN_TRANS  64
+#define ISISC_VLAN_TRANS_ADDR 0x5ac00
+
+
+static sw_error_t
+_isisc_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, reg = 0;
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      COREP_EN, (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                          DEF_SVID, (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                          DEF_CVID, (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_DEFV, (port_id / 2),
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (port_id % 2)
+    {
+        reg &= 0xffff;
+        reg |= ((data & 0xfff) << 16);
+    }
+    else
+    {
+        reg &= 0xffff0000;
+        reg |= (data & 0xfff);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_DEFV, (port_id / 2),
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+    a_uint32_t data, regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_1Q_MODE_BUTT <= port_1qmode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE,
+                      (a_uint8_t *) (&regval[port_1qmode]),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_1Q_DISABLE == port_1qmode)
+    {
+        data = 1;
+    }
+    else
+    {
+        data = 0;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, VLAN_DIS,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_isisc_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK,
+                                  FAL_1Q_CHECK, FAL_1Q_SECURE
+                                };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(pport_1qmode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    *pport_1qmode = retval[regval & 0x3];
+
+    return SW_OK;
+}
+#endif
+static sw_error_t
+_isisc_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3, 3 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((FAL_EG_MODE_BUTT <= port_egvlanmode)
+            || (FAL_EG_HYBRID == port_egvlanmode))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE,
+                      (a_uint8_t *) (&regval[port_egvlanmode]),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_EG, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0x3 << (port_id << 2)));
+    data |= (regval[port_egvlanmode] << (port_id << 2));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_EG, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_isisc_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_1q_egmode_t retval[4] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED,
+                                     FAL_EG_TAGGED, FAL_EG_UNTOUCHED
+                                   };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(pport_egvlanmode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    *pport_egvlanmode = retval[regval & 0x3];
+
+    return SW_OK;
+}
+#endif
+static sw_error_t
+_isisc_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    regval |= (0x1UL << mem_port_id);
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    regval &= (~(0x1UL << mem_port_id));
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&mem_port_map),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_isisc_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    *mem_port_map = 0;
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) mem_port_map,
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+#endif
+static sw_error_t
+_isisc_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_isisc_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+#endif
+static sw_error_t
+_isisc_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_isisc_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+                      FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+#endif
+static sw_error_t
+_isisc_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    val = tpid;
+    HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+                      TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_isisc_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+                      TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *tpid = val;
+    return SW_OK;
+}
+#endif
+static sw_error_t
+_isisc_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_invlan_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t regval[FAL_INVLAN_MODE_BUTT] = { 0, 1, 2 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_INVLAN_MODE_BUTT <= mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE,
+                      (a_uint8_t *) (&regval[mode]), sizeof (a_uint32_t));
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_isisc_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_invlan_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_invlan_mode_t retval[FAL_INVLAN_MODE_BUTT] = { FAL_INVLAN_ADMIT_ALL,
+            FAL_INVLAN_ADMIT_TAGGED, FAL_INVLAN_ADMIT_UNTAGGED
+                                                        };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(mode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (regval >= 3)
+    {
+        return SW_FAIL;
+    }
+    *mode = retval[regval & 0x3];
+
+    return rv;
+}
+#endif
+
+static sw_error_t
+_isisc_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_isisc_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      PRI_PROPAGATION, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      PRI_PROPAGATION, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+#endif
+static sw_error_t
+_isisc_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t vid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (vid > MAX_VLAN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = vid;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_port_route_defv_set(dev_id, port_id);
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_isisc_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * vid)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    *vid = val & 0xfff;
+    return rv;
+}
+#endif
+static sw_error_t
+_isisc_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t vid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (vid > MAX_VLAN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = vid;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_port_route_defv_set(dev_id, port_id);
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_isisc_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * vid)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    *vid = val & 0xfff;
+    return rv;
+}
+#endif
+static sw_error_t
+_isisc_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_vlan_propagation_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, p, c;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_VLAN_PROPAGATION_DISABLE == mode)
+    {
+        p = 0;
+        c = 0;
+    }
+    else if (FAL_VLAN_PROPAGATION_CLONE == mode)
+    {
+        p = 1;
+        c = 1;
+    }
+    else if (FAL_VLAN_PROPAGATION_REPLACE == mode)
+    {
+        p = 1;
+        c = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT_VLAN1, PROPAGATION_EN, p, reg);
+    SW_SET_REG_BY_FIELD(PORT_VLAN1, CLONE, c, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+static sw_error_t
+_isisc_vlan_trans_write(a_uint32_t dev_id, a_uint32_t entry_idx, fal_pbmp_t pbmp,
+                       fal_vlan_trans_entry_t entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, addr, table[2] = { 0 };
+
+    addr = ISISC_VLAN_TRANS_ADDR + (entry_idx << 3);
+
+    if (0 != pbmp)
+    {
+        table[0] = entry.o_vid & 0xfff;
+        table[0] |= ((entry.s_vid & 0xfff) << 12);
+        table[0] |= ((entry.c_vid & 0xff) << 24);
+        table[1] = (entry.c_vid >> 8) & 0xf;
+
+        if (A_TRUE == entry.bi_dir)
+        {
+            table[1] |= (0x3 << 4);
+        }
+
+        if (A_TRUE == entry.forward_dir)
+        {
+            table[1] |= (0x1 << 4);
+        }
+
+        if (A_TRUE == entry.reverse_dir)
+        {
+            table[1] |= (0x1 << 5);
+        }
+
+        table[1] |= (pbmp << 6);
+        table[1] |= ((0x1UL & entry.o_vid_is_cvid) << 13);
+        table[1] |= ((0x1UL & entry.s_vid_enable) << 14);
+        table[1] |= ((0x1UL & entry.c_vid_enable) << 15);
+        table[1] |= ((0x1UL & entry.one_2_one_vlan) << 16);
+    }
+
+    /* set vlan trans table */
+    for (i = 0; i < 2; i++)
+    {
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+#ifndef IN_PORTVLAN_MINI
+
+static sw_error_t
+_isisc_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_vlan_propagation_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, p, c;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_VLAN1, PROPAGATION_EN, p, reg);
+    SW_GET_FIELD_BY_REG(PORT_VLAN1, CLONE, c, reg);
+
+    if (p)
+    {
+        if (c)
+        {
+            *mode = FAL_VLAN_PROPAGATION_CLONE;
+        }
+        else
+        {
+            *mode = FAL_VLAN_PROPAGATION_REPLACE;
+        }
+    }
+    else
+    {
+        *mode = FAL_VLAN_PROPAGATION_DISABLE;
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isisc_vlan_trans_read(a_uint32_t dev_id, a_uint32_t entry_idx,
+                      fal_pbmp_t * pbmp, fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, addr, dir, table[2] = {0};
+
+    *pbmp = 0;
+    aos_mem_zero(entry, sizeof (fal_vlan_trans_entry_t));
+
+    addr = ISISC_VLAN_TRANS_ADDR + (entry_idx << 3);
+    /* get vlan trans table */
+    for (i = 0; i < 2; i++)
+    {
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    dir = 0x3 & (table[1] >> 4);
+    if (!dir)
+    {
+        return SW_EMPTY;
+    }
+
+    entry->o_vid = table[0] & 0xfff;
+    *pbmp = (table[1] >> 6) & 0x7f;
+
+    if (3 == dir)
+    {
+        entry->bi_dir = A_TRUE;
+        entry->forward_dir = A_TRUE;
+        entry->reverse_dir = A_TRUE;
+    }
+    else if (1 == dir)
+    {
+        entry->bi_dir = A_FALSE;
+        entry->forward_dir = A_TRUE;
+        entry->reverse_dir = A_FALSE;
+    }
+    else
+    {
+        entry->bi_dir = A_FALSE;
+        entry->forward_dir = A_FALSE;
+        entry->reverse_dir = A_TRUE;
+    }
+
+    entry->o_vid_is_cvid = (table[1] >> 13) & 0x1UL;
+    entry->one_2_one_vlan = (table[1] >> 16) & 0x1UL;
+    entry->s_vid_enable = (table[1] >> 14) & 0x1UL;
+    entry->c_vid_enable = (table[1] >> 15) & 0x1UL;
+
+    if (A_TRUE == entry->s_vid_enable)
+    {
+        entry->s_vid = (table[0] >> 12) & 0xfff;
+    }
+
+    if (A_TRUE == entry->c_vid_enable)
+    {
+        entry->c_vid = ((table[0] >> 24) & 0xff) | ((table[1] & 0xf) << 8);
+    }
+
+    return SW_OK;
+}
+
+
+
+static sw_error_t
+_isisc_port_vlan_trans_convert(fal_vlan_trans_entry_t * entry,
+                              fal_vlan_trans_entry_t * local)
+{
+    aos_mem_copy(local, entry, sizeof (fal_vlan_trans_entry_t));
+
+    if ((A_TRUE == local->bi_dir)
+            || ((A_TRUE == local->forward_dir)
+                && (A_TRUE == local->reverse_dir)))
+    {
+        local->bi_dir = A_TRUE;
+        local->forward_dir = A_TRUE;
+        local->reverse_dir = A_TRUE;
+    }
+
+    if (A_FALSE == local->s_vid_enable)
+    {
+        local->s_vid = 0;
+    }
+
+    if (A_FALSE == local->c_vid_enable)
+    {
+        local->c_vid = 0;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+    fal_pbmp_t t_pbmp;
+    a_uint32_t idx, entry_idx = ISISC_MAX_VLAN_TRANS;
+    fal_vlan_trans_entry_t temp, local;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (NULL == entry)
+    {
+        return SW_BAD_PTR;
+    }
+    aos_mem_zero(&local, sizeof(fal_vlan_trans_entry_t));
+    rv = _isisc_port_vlan_trans_convert(entry, &local);
+    SW_RTN_ON_ERROR(rv);
+
+    for (idx = 0; idx < ISISC_MAX_VLAN_TRANS; idx++)
+    {
+        rv = _isisc_vlan_trans_read(dev_id, idx, &t_pbmp, &temp);
+        if (SW_EMPTY == rv)
+        {
+            entry_idx = idx;
+            continue;
+        }
+        SW_RTN_ON_ERROR(rv);
+
+        if (!aos_mem_cmp(&local, &temp, sizeof (fal_vlan_trans_entry_t)))
+        {
+            if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+            {
+                return SW_ALREADY_EXIST;
+            }
+            entry_idx = idx;
+            break;
+        }
+        else
+        {
+            t_pbmp = 0;
+        }
+    }
+
+    if (ISISC_MAX_VLAN_TRANS != entry_idx)
+    {
+        t_pbmp |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    return _isisc_vlan_trans_write(dev_id, entry_idx, t_pbmp, local);
+}
+
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_isisc_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+    fal_pbmp_t t_pbmp;
+    a_uint32_t idx, entry_idx = ISISC_MAX_VLAN_TRANS;
+    fal_vlan_trans_entry_t temp, local;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (NULL == entry)
+    {
+        return SW_BAD_PTR;
+    }
+    aos_mem_zero(&local, sizeof(fal_vlan_trans_entry_t));
+    rv = _isisc_port_vlan_trans_convert(entry, &local);
+    SW_RTN_ON_ERROR(rv);
+
+    for (idx = 0; idx < ISISC_MAX_VLAN_TRANS; idx++)
+    {
+        rv = _isisc_vlan_trans_read(dev_id, idx, &t_pbmp, &temp);
+        if (SW_EMPTY == rv)
+        {
+            continue;
+        }
+        SW_RTN_ON_ERROR(rv);
+
+        if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t)))
+        {
+            if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+            {
+                entry_idx = idx;
+                break;
+            }
+        }
+    }
+
+    if (ISISC_MAX_VLAN_TRANS != entry_idx)
+    {
+        t_pbmp &= (~(0x1 << port_id));
+    }
+    else
+    {
+        return SW_NOT_FOUND;
+    }
+
+    return _isisc_vlan_trans_write(dev_id, entry_idx, t_pbmp, local);
+}
+
+static sw_error_t
+_isisc_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+    fal_pbmp_t t_pbmp;
+    a_uint32_t idx;
+    fal_vlan_trans_entry_t temp, local;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (NULL == entry)
+    {
+        return SW_BAD_PTR;
+    }
+    aos_mem_zero(&local, sizeof(fal_vlan_trans_entry_t));
+    rv = _isisc_port_vlan_trans_convert(entry, &local);
+    SW_RTN_ON_ERROR(rv);
+
+    for (idx = 0; idx < ISISC_MAX_VLAN_TRANS; idx++)
+    {
+        rv = _isisc_vlan_trans_read(dev_id, idx, &t_pbmp, &temp);
+        if (SW_EMPTY == rv)
+        {
+            continue;
+        }
+        SW_RTN_ON_ERROR(rv);
+
+        if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t)))
+        {
+            if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+            {
+                return SW_OK;
+            }
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isisc_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * iterator,
+                              fal_vlan_trans_entry_t * entry)
+{
+    a_uint32_t index;
+    sw_error_t rv;
+    fal_vlan_trans_entry_t entry_t;
+    fal_pbmp_t pbmp_t;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((NULL == iterator) || (NULL == entry))
+    {
+        return SW_BAD_PTR;
+    }
+
+    if (ISISC_MAX_VLAN_TRANS < *iterator)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (index = *iterator; index < ISISC_MAX_VLAN_TRANS; index++)
+    {
+        rv = _isisc_vlan_trans_read(dev_id, index, &pbmp_t, &entry_t);
+        if (SW_EMPTY == rv)
+        {
+            continue;
+        }
+
+        if (SW_IS_PBMP_MEMBER(pbmp_t, port_id))
+        {
+            aos_mem_copy(entry, &entry_t, sizeof (fal_vlan_trans_entry_t));
+            break;
+        }
+    }
+
+    if (ISISC_MAX_VLAN_TRANS == index)
+    {
+        return SW_NO_MORE;
+    }
+
+    *iterator = index + 1;
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isisc_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t stag = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_QINQ_MODE_BUTT <= mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QINQ_STAG_MODE == mode)
+    {
+        stag = 1;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+                      STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_isisc_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t stag = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+                      STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (stag)
+    {
+        *mode = FAL_QINQ_STAG_MODE;
+    }
+    else
+    {
+        *mode = FAL_QINQ_CTAG_MODE;
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isisc_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_qinq_port_role_t role)
+{
+    sw_error_t rv;
+    a_uint32_t core = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QINQ_PORT_ROLE_BUTT <= role)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QINQ_CORE_PORT == role)
+    {
+        core = 1;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+                      COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_port_route_defv_set(dev_id, port_id);
+    return rv;
+}
+
+#ifndef IN_PORTVLAN_MINI
+static sw_error_t
+_isisc_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_qinq_port_role_t * role)
+{
+    sw_error_t rv;
+    a_uint32_t core = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+                      COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (core)
+    {
+        *role = FAL_QINQ_CORE_PORT;
+    }
+    else
+    {
+        *role = FAL_QINQ_EDGE_PORT;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id,
+                      EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+
+}
+
+static sw_error_t
+_isisc_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id,
+                      EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_netisolate_set(a_uint32_t dev_id, a_uint32_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    val = enable;
+    HSL_REG_FIELD_SET(rv, dev_id, VLAN_TRANS, 0,
+                      NET_ISO, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_netisolate_get(a_uint32_t dev_id, a_uint32_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TRANS, 0,
+                      NET_ISO, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *enable = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_uint32_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    val = enable;
+    HSL_REG_FIELD_SET(rv, dev_id, VLAN_TRANS, 0,
+                      EG_FLTR_BYPASS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_uint32_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TRANS, 0,
+                      EG_FLTR_BYPASS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *enable = val;
+    return SW_OK;
+}
+#endif
+
+
+/**
+ * @brief Set 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_1qmode_set(dev_id, port_id, port_1qmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_1qmode_get(dev_id, port_id, pport_1qmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Add member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_portvlan_member_add(dev_id, port_id, mem_port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_portvlan_member_del(dev_id, port_id, mem_port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Update member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_portvlan_member_update(dev_id, port_id, mem_port_map);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_portvlan_member_get(dev_id, port_id, mem_port_map);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_force_default_vid_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_force_default_vid_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_force_portvlan_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_force_portvlan_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nestvlan_tpid_set(dev_id, tpid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_nestvlan_tpid_get(dev_id, tpid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_invlan_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_invlan_mode_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_invlan_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_invlan_mode_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_tls_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+
+
+/**
+ * @brief Get tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_tls_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_pri_propagation_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_pri_propagation_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid s-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_default_svid_set(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid s-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_default_svid_get(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid c-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_default_cvid_set(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid c-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_default_cvid_get(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_vlan_propagation_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_vlan_propagation_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#ifndef IN_PORTVLAN_MINI
+
+
+/**
+ * @brief Get vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_vlan_propagation_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_vlan_propagation_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Add a vlan translation entry to a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_vlan_trans_add(dev_id, port_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Delete a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_vlan_trans_del(dev_id, port_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_vlan_trans_get(dev_id, port_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Iterate all vlan translation entries from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] iterator translation entry index if it's zero means get the first entry
+ * @param[out] iterator next valid translation entry index
+ * @param[out] entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * iterator,
+                             fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_vlan_trans_iterate(dev_id, port_id, iterator, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qinq_mode_set(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qinq_mode_get(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#endif
+/**
+ * @brief Set qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qinq_port_role_t role)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_qinq_role_set(dev_id, port_id, role);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#ifndef IN_PORTVLAN_MINI
+/**
+ * @brief Get qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qinq_port_role_t * role)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_qinq_role_get(dev_id, port_id, role);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set MAC_VLAN_XLT status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_mac_vlan_xlt_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get MAC_VLAN_XLT status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_mac_vlan_xlt_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#ifdef HSL_STANDALONG
+HSL_LOCAL sw_error_t
+isisc_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv =_isisc_port_route_defv_set(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set NET_ISOLATE_EN
+ * @param[in] dev_id device id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_netisolate_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_netisolate_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get NET_ISOLATE_EN status
+ * @param[in] dev_id device id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_netisolate_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_netisolate_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress translation filter bypass enable
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_eg_trans_filter_bypass_en_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress translation filter bypass enable
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_eg_trans_filter_bypass_en_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+
+sw_error_t
+isisc_portvlan_init(a_uint32_t dev_id)
+{
+    a_uint32_t i;
+    sw_error_t rv;
+    fal_vlan_trans_entry_t entry_init;
+    hsl_api_t *p_api;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    aos_mem_set(&entry_init, 0, sizeof (fal_vlan_trans_entry_t));
+
+    for (i = 0; i < ISISC_MAX_VLAN_TRANS; i++)
+    {
+        rv = _isisc_vlan_trans_write(dev_id, i, 0, entry_init);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+#ifndef HSL_STANDALONG
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+	p_api->port_1qmode_set = isisc_port_1qmode_set;
+	p_api->port_egvlanmode_set = isisc_port_egvlanmode_set;
+	p_api->portvlan_member_add = isisc_portvlan_member_add;
+	p_api->portvlan_member_del = isisc_portvlan_member_del;
+	p_api->portvlan_member_update = isisc_portvlan_member_update;
+	p_api->port_force_default_vid_set = isisc_port_force_default_vid_set;
+	p_api->port_force_portvlan_set = isisc_port_force_portvlan_set;
+	p_api->nestvlan_tpid_set = isisc_nestvlan_tpid_set;
+	p_api->port_invlan_mode_set = isisc_port_invlan_mode_set;
+	p_api->port_tls_set = isisc_port_tls_set;
+	#ifndef IN_PORTVLAN_MINI
+	p_api->port_1qmode_get = isisc_port_1qmode_get;
+	p_api->port_egvlanmode_get = isisc_port_egvlanmode_get;
+	p_api->portvlan_member_get = isisc_portvlan_member_get;
+	p_api->port_force_default_vid_get = isisc_port_force_default_vid_get;
+	p_api->port_force_portvlan_get = isisc_port_force_portvlan_get;
+	p_api->nestvlan_tpid_get = isisc_nestvlan_tpid_get;
+	p_api->port_invlan_mode_get = isisc_port_invlan_mode_get;
+	p_api->port_tls_get = isisc_port_tls_get;
+	p_api->port_pri_propagation_set = isisc_port_pri_propagation_set;
+	p_api->port_pri_propagation_get = isisc_port_pri_propagation_get;
+	#endif
+	p_api->port_default_svid_set = isisc_port_default_svid_set;
+	p_api->port_default_cvid_set = isisc_port_default_cvid_set;
+	p_api->port_vlan_propagation_set = isisc_port_vlan_propagation_set;
+	#ifndef IN_PORTVLAN_MINI
+	p_api->port_default_cvid_get = isisc_port_default_cvid_get;
+	p_api->port_default_svid_get = isisc_port_default_svid_get;
+    p_api->port_vlan_propagation_get = isisc_port_vlan_propagation_get;
+    p_api->port_vlan_trans_del = isisc_port_vlan_trans_del;
+    p_api->port_vlan_trans_get = isisc_port_vlan_trans_get;
+#endif
+    p_api->port_vlan_trans_add = isisc_port_vlan_trans_add;
+    p_api->qinq_mode_set = isisc_qinq_mode_set;
+    p_api->port_qinq_role_set = isisc_port_qinq_role_set;
+#ifndef IN_PORTVLAN_MINI
+    p_api->port_qinq_role_get = isisc_port_qinq_role_get;
+    p_api->qinq_mode_get = isisc_qinq_mode_get;
+    p_api->port_vlan_trans_iterate = isisc_port_vlan_trans_iterate;
+    p_api->port_mac_vlan_xlt_set = isisc_port_mac_vlan_xlt_set;
+    p_api->port_mac_vlan_xlt_get = isisc_port_mac_vlan_xlt_get;
+    p_api->netisolate_set = isisc_netisolate_set;
+    p_api->netisolate_get = isisc_netisolate_get;
+    p_api->eg_trans_filter_bypass_en_set = isisc_eg_trans_filter_bypass_en_set;
+    p_api->eg_trans_filter_bypass_en_get = isisc_eg_trans_filter_bypass_en_get;
+	#endif
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/isisc/isisc_qos.c b/qca-ssdk/src/hsl/isisc/isisc_qos.c
new file mode 100755
index 0000000..e62d75e
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_qos.c
@@ -0,0 +1,1639 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_qos ISISC_QOS
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_qos.h"
+#include "isisc_reg.h"
+
+#define ISISC_QOS_QUEUE_TX_BUFFER_MAX 120
+#define ISISC_QOS_PORT_TX_BUFFER_MAX  504
+#define ISISC_QOS_PORT_RX_BUFFER_MAX  120
+
+#define ISISC_QOS_HOL_STEP       8
+#define ISISC_QOS_HOL_MOD        3
+
+//#define ISISC_MIN_QOS_MODE_PRI 0
+#define ISISC_MAX_QOS_MODE_PRI   3
+#define ISISC_MAX_PRI            7
+#define ISISC_MAX_QUEUE          3
+#define ISISC_MAX_EH_QUEUE       5
+
+static sw_error_t
+_isisc_qos_port_queue_check(fal_port_t port_id, fal_queue_t queue_id)
+{
+    if ((0 == port_id) || (5 == port_id) || (6 == port_id))
+    {
+        if (ISISC_MAX_EH_QUEUE < queue_id)
+        {
+            return SW_BAD_PARAM;
+        }
+    }
+    else
+    {
+        if (ISISC_MAX_QUEUE < queue_id)
+        {
+            return SW_BAD_PARAM;
+        }
+    }
+
+    return SW_OK;
+}
+
+
+#ifndef IN_QOS_MINI
+static sw_error_t
+_isisc_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+
+
+static sw_error_t
+_isisc_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_RED_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+
+
+
+
+static sw_error_t
+_isisc_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_queue_t queue_id, a_uint32_t * number)
+{
+    a_uint32_t data = 0, val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isisc_qos_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    val = (data >> (queue_id << 2)) & 0xf;
+    *number = val << ISISC_QOS_HOL_MOD;
+    return SW_OK;
+}
+
+
+static sw_error_t
+_isisc_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *number = val << ISISC_QOS_HOL_MOD;
+    return SW_OK;
+}
+
+
+static sw_error_t
+_isisc_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *number = val << ISISC_QOS_HOL_MOD;
+    return SW_OK;
+}
+#endif
+static sw_error_t
+_isisc_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_RED_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_queue_t queue_id, a_uint32_t * number)
+{
+    a_uint32_t data = 0, val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISISC_QOS_QUEUE_TX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isisc_qos_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    val = *number / ISISC_QOS_HOL_STEP;
+    *number = val << ISISC_QOS_HOL_MOD;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0xf << (queue_id << 2)));
+    data |= (val << (queue_id << 2));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISISC_QOS_PORT_TX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = *number / ISISC_QOS_HOL_STEP;
+    *number = val << ISISC_QOS_HOL_MOD;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISISC_QOS_PORT_RX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = *number / ISISC_QOS_HOL_STEP;
+    *number = val << ISISC_QOS_HOL_MOD;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qos_mode_t mode, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+#ifndef IN_QOS_MINI
+static sw_error_t
+_isisc_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qos_mode_t mode, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_qos_mode_t mode, a_uint32_t pri)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISISC_MAX_QOS_MODE_PRI < pri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_qos_mode_t mode, a_uint32_t * pri)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0, f_val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    *pri = f_val;
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                            fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val, w[6] = { 0 };
+    a_int32_t i, _index;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SCH_SP_MODE == mode)
+    {
+        val = 0;
+        _index = -1;
+    }
+    else if (FAL_SCH_WRR_MODE == mode)
+    {
+        val = 3;
+        _index = 5;
+    }
+    else if (FAL_SCH_MIX_MODE == mode)
+    {
+        val = 1;
+        _index = 4;
+    }
+    else if (FAL_SCH_MIX_PLUS_MODE == mode)
+    {
+        val = 2;
+        _index = 3;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    for (i = _index; i >= 0; i--)
+    {
+        if (weight[i] > 0x1f)
+        {
+            return SW_BAD_PARAM;
+        }
+        w[i] = weight[i];
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(WRR_CTRL, SCH_MODE, val, reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q5_W, w[5], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q4_W, w[4], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q3_W, w[3], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q2_W, w[2], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q1_W, w[1], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q0_W, w[0], reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, WRR_CTRL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                            fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+    a_uint32_t val = 0, sch, w[6], i;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(WRR_CTRL, SCH_MODE, sch, val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q5_W, w[5], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q4_W, w[4], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q3_W, w[3], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q2_W, w[2], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q1_W, w[1], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q0_W, w[0], val);
+
+    if (0 == sch)
+    {
+        *mode = FAL_SCH_SP_MODE;
+    }
+    else if (1 == sch)
+    {
+        *mode = FAL_SCH_MIX_MODE;
+    }
+    else if (2 == sch)
+    {
+        *mode = FAL_SCH_MIX_PLUS_MODE;
+    }
+    else
+    {
+        *mode = FAL_SCH_WRR_MODE;
+    }
+
+    for (i = 0; i < 6; i++)
+    {
+        weight[i] = w[i];
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t spri)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISISC_MAX_PRI < spri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = spri;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * spri)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    *spri = val & 0x7;
+    return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t cpri)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (ISISC_MAX_PRI < cpri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = cpri;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isisc_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_uint32_t * cpri)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    *cpri = val & 0x7;
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isisc_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_FORCE_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isisc_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_bool_t* enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_FORCE_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isisc_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = enable ? 1 : 0;
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_FORCE_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isisc_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                     a_bool_t* enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+                      ING_FORCE_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t addr, data = 0;
+    a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60};
+
+    rv = _isisc_qos_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    addr = base[port_id] + ((queue_id / 4) << 2);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data &= (~(0xff << ((queue_id % 4) << 3)));
+    data |= (((enable << 7 ) | (tbl_id & 0xf)) << ((queue_id % 4) << 3));
+
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isisc_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t addr, data = 0;
+    a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60};
+
+    rv = _isisc_qos_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    addr = base[port_id] + ((queue_id / 4) << 2);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *tbl_id = (data >> ((queue_id % 4) << 3)) & 0xf;
+    *enable = ((data >> ((queue_id % 4) << 3)) & 0x80) >> 7;
+    return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+_isisc_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_bm_static_cfg_t *cfg)
+{
+    sw_error_t rv;
+    a_uint32_t reg_value, xon_value, xoff_value;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_FLOW_CTRL_THRESHOLD, port_id,
+                      (a_uint8_t *) (&reg_value), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_FLOW_CTRL_THRESHOLD, XON_THRES, xon_value, reg_value);
+    SW_GET_FIELD_BY_REG(PORT_FLOW_CTRL_THRESHOLD, XOFF_THRES, xoff_value, reg_value);
+    cfg->max_thresh = xoff_value;
+    cfg->resume_off = xoff_value - xon_value;
+
+    return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+_isisc_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_bm_static_cfg_t *cfg)
+{
+    sw_error_t rv;
+    a_uint32_t reg_value = 0;
+
+    SW_SET_REG_BY_FIELD(PORT_FLOW_CTRL_THRESHOLD, XON_THRES, cfg->max_thresh - cfg->resume_off, reg_value);
+    SW_SET_REG_BY_FIELD(PORT_FLOW_CTRL_THRESHOLD, XOFF_THRES, cfg->max_thresh, reg_value);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_FLOW_CTRL_THRESHOLD, port_id,
+                      (a_uint8_t *) (&reg_value), sizeof (a_uint32_t));
+
+    return SW_OK;
+}
+#endif
+
+#ifndef IN_QOS_MINI
+/**
+ * @brief Set buffer aggsinment status of transmitting queue on one particular port.
+ *   @details  Comments:
+ *    If enable queue tx buffer on one port that means each queue of this port
+ *    will have fixed number buffers when transmitting packets. Otherwise they
+ *    share the whole buffers with other queues in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_queue_tx_buf_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting queue on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_queue_tx_buf_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting port on one particular port.
+ *   @details  Comments:
+    If enable tx buffer on one port that means this port will have fixed
+    number buffers when transmitting packets. Otherwise they will
+    share the whole buffers with other ports in device.
+ *    function will return actual buffer numbers in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_tx_buf_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_tx_buf_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+
+/**
+ * @brief Set status of port red on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_red_en_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+
+
+/**
+ * @brief Get max occupied buffer number of transmitting queue on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+
+/**
+ * @brief Get max occupied buffer number of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_tx_buf_nr_get(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+
+/**
+ * @brief Get max occupied buffer number of receiving port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_rx_buf_nr_get(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+/**
+ * @brief Set status of port red on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_red_en_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+/**
+ * @brief Set max occupied buffer number of transmitting queue on one particular port.
+ *   @details   Comments:
+    The step of buffer number in Garuda is 4, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for queue is 4 to 60.
+ *    share the whole buffers with other ports in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+/**
+ * @brief Set max occupied buffer number of transmitting port on one particular port.
+ *   @details   Comments:
+    The step of buffer number in Garuda is four, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for transmitting port is 4 to 124.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_tx_buf_nr_set(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+/**
+ * @brief Set max occupied buffer number of receiving port on one particular port.
+ *   @details   Comments:
+    The step of buffer number in Shiva is four, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for receiving port is 4 to 60.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_rx_buf_nr_set(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+/**
+ * @brief Set port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_qos_mode_t mode, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_mode_set(dev_id, port_id, mode, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+#ifndef IN_QOS_MINI
+/**
+ * @brief Get port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_qos_mode_t mode, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_mode_get(dev_id, port_id, mode, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+/**
+ * @brief Set priority of one particular qos mode on one particular port.
+ *   @details   Comments:
+    If the priority of a mode is more small then the priority is more high.
+    Differnet mode should have differnet priority.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_qos_mode_t mode, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get priority of one particular qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_qos_mode_t mode, a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set traffic scheduling mode on particular one port.
+ *   @details   Comments:
+ *   When scheduling mode is sp the weight is meaningless usually it's zero
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[in] weight[] weight value for each queue when in wrr mode,
+              the max value supported by ISIS is 0x1f.
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                           fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_sch_mode_set(dev_id, port_id, mode, weight);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get traffic scheduling mode on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] fal_sch_mode_t traffic scheduling mode
+ * @param[out] weight weight value for wrr mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                           fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_sch_mode_get(dev_id, port_id, mode, weight);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default stag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] spri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t spri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_default_spri_set(dev_id, port_id, spri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default stag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] spri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * spri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_default_spri_get(dev_id, port_id, spri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default ctag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cpri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t cpri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_default_cpri_set(dev_id, port_id, cpri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default ctag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cpri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * cpri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_default_cpri_get(dev_id, port_id, cpri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port force stag priority enable flag one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_force_spri_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port force stag priority enable flag one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t* enable)
+{
+    sw_error_t rv;
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_force_spri_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port force ctag priority enable flag one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_force_cpri_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port force ctag priority enable flag one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                    a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_port_force_cpri_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress queue based CoS remark on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[in] tbl_id CoS remark table id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_queue_remark_table_set(dev_id, port_id, queue_id, tbl_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress queue based CoS remark on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] tbl_id CoS remark table id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_qos_queue_remark_table_get(dev_id, port_id, queue_id, tbl_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get static flow control threshold on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] static maximum threshold and resume offset
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_bm_static_cfg_t *cfg)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_static_thresh_get(dev_id, port_id, cfg);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set static flow control threshold on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] static maximum threshold and resume offset
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_bm_static_cfg_t *cfg)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_port_static_thresh_set(dev_id, port_id, cfg);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+sw_error_t
+isisc_qos_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+		p_api->qos_queue_tx_buf_nr_set = isisc_qos_queue_tx_buf_nr_set;
+		p_api->qos_port_red_en_set = isisc_qos_port_red_en_set;
+		p_api->qos_port_tx_buf_nr_set = isisc_qos_port_tx_buf_nr_set;
+		p_api->qos_port_rx_buf_nr_set = isisc_qos_port_rx_buf_nr_set;
+	#ifndef IN_QOS_MINI
+        p_api->qos_queue_tx_buf_status_set = isisc_qos_queue_tx_buf_status_set;
+        p_api->qos_queue_tx_buf_status_get = isisc_qos_queue_tx_buf_status_get;
+        p_api->qos_port_tx_buf_status_set = isisc_qos_port_tx_buf_status_set;
+        p_api->qos_port_tx_buf_status_get = isisc_qos_port_tx_buf_status_get;
+        p_api->qos_port_red_en_get = isisc_qos_port_red_en_get;
+        p_api->qos_queue_tx_buf_nr_get = isisc_qos_queue_tx_buf_nr_get;
+        p_api->qos_port_tx_buf_nr_get = isisc_qos_port_tx_buf_nr_get;
+        p_api->qos_port_rx_buf_nr_get = isisc_qos_port_rx_buf_nr_get;
+	#endif
+        p_api->qos_port_mode_set = isisc_qos_port_mode_set;
+        
+	#ifndef IN_QOS_MINI
+	p_api->qos_port_mode_get = isisc_qos_port_mode_get;
+        p_api->qos_port_mode_pri_set = isisc_qos_port_mode_pri_set;
+        p_api->qos_port_mode_pri_get = isisc_qos_port_mode_pri_get;
+        p_api->qos_port_sch_mode_set = isisc_qos_port_sch_mode_set;
+        p_api->qos_port_sch_mode_get = isisc_qos_port_sch_mode_get;
+        p_api->qos_port_default_spri_set = isisc_qos_port_default_spri_set;
+        p_api->qos_port_default_spri_get = isisc_qos_port_default_spri_get;
+        p_api->qos_port_default_cpri_set = isisc_qos_port_default_cpri_set;
+        p_api->qos_port_default_cpri_get = isisc_qos_port_default_cpri_get;
+        p_api->qos_port_force_spri_status_set = isisc_qos_port_force_spri_status_set;
+        p_api->qos_port_force_spri_status_get = isisc_qos_port_force_spri_status_get;
+        p_api->qos_port_force_cpri_status_set = isisc_qos_port_force_cpri_status_set;
+        p_api->qos_port_force_cpri_status_get = isisc_qos_port_force_cpri_status_get;
+        p_api->qos_queue_remark_table_set = isisc_qos_queue_remark_table_set;
+        p_api->qos_queue_remark_table_get = isisc_qos_queue_remark_table_get;
+	p_api->port_static_thresh_get = isisc_port_static_thresh_get;
+	p_api->port_static_thresh_set = isisc_port_static_thresh_set;
+	#endif
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/isisc/isisc_rate.c b/qca-ssdk/src/hsl/isisc/isisc_rate.c
new file mode 100755
index 0000000..0cbe6b0
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_rate.c
@@ -0,0 +1,1662 @@
+/*
+ * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_rate ISISC_RATE
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_rate.h"
+#include "isisc_reg.h"
+
+#define ISISC_MAX_POLICER_ID          31
+#define ISISC_MAX_QUEUE               3
+#define ISISC_MAX_EH_QUEUE            5
+
+#define ACL_POLICER_CNT_SEL_ADDR          0x09f0
+#define ACL_POLICER_CNT_MODE_ADDR         0x09f4
+#define ACL_POLICER_CNT_RST_ADDR          0x09f8
+
+static sw_error_t
+_isisc_rate_port_queue_check(fal_port_t port_id, fal_queue_t queue_id)
+{
+    if ((0 == port_id) || (5 == port_id) || (6 == port_id))
+    {
+        if (ISISC_MAX_EH_QUEUE < queue_id)
+        {
+            return SW_BAD_PARAM;
+        }
+    }
+    else
+    {
+        if (ISISC_MAX_QUEUE < queue_id)
+        {
+            return SW_BAD_PARAM;
+        }
+    }
+
+    return SW_OK;
+}
+
+static void
+_isisc_egress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+    a_int32_t i;
+    a_uint32_t data[8] =
+    {
+        0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024,
+        512 * 1024
+    };
+
+    for (i = 7; i >= 0; i--)
+    {
+        if (sw_bs >= data[i])
+        {
+            *hw_bs = i;
+            break;
+        }
+    }
+}
+
+static void
+_isisc_egress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+    a_uint32_t data[8] =
+    {
+        0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024,
+        512 * 1024
+    };
+
+    *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isisc_egress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+    a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 };
+    a_int32_t i;
+
+    for (i = 7; i >= 0; i--)
+    {
+        if (sw_bs >= data[i])
+        {
+            *hw_bs = i;
+            break;
+        }
+    }
+}
+
+static void
+_isisc_egress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+    a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 };
+
+    *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isisc_ingress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+    a_int32_t i;
+    a_uint32_t data[8] =
+    {
+        0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024,
+        8 * 1024 * 1024, 32 * 1024 * 1024
+    };
+
+    for (i = 7; i >= 0; i--)
+    {
+        if (sw_bs >= data[i])
+        {
+            *hw_bs = i;
+            break;
+        }
+    }
+}
+
+static void
+_isisc_ingress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+    a_uint32_t data[8] =
+    {
+        0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024,
+        8 * 1024 * 1024, 32 * 1024 * 1024
+    };
+
+    *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isisc_ingress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+    a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 };
+    a_int32_t i;
+
+    for (i = 7; i >= 0; i--)
+    {
+        if (sw_bs >= data[i])
+        {
+            *hw_bs = i;
+            break;
+        }
+    }
+}
+
+static void
+_isisc_ingress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+    a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 };
+
+    *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isisc_rate_flag_parse(a_uint32_t sw_flag, a_uint32_t * hw_flag)
+{
+    *hw_flag = 0;
+
+    if (FAL_INGRESS_POLICING_TCP_CTRL & sw_flag)
+    {
+        *hw_flag |= (0x1 << 1);
+    }
+
+    if (FAL_INGRESS_POLICING_MANAGEMENT & sw_flag)
+    {
+        *hw_flag |= (0x1 << 2);
+    }
+
+    if (FAL_INGRESS_POLICING_BROAD & sw_flag)
+    {
+        *hw_flag |= (0x1 << 3);
+    }
+
+    if (FAL_INGRESS_POLICING_UNK_UNI & sw_flag)
+    {
+        *hw_flag |= (0x1 << 4);
+    }
+
+    if (FAL_INGRESS_POLICING_UNK_MUL & sw_flag)
+    {
+        *hw_flag |= (0x1 << 5);
+    }
+
+    if (FAL_INGRESS_POLICING_UNI & sw_flag)
+    {
+        *hw_flag |= (0x1 << 6);
+    }
+
+    if (FAL_INGRESS_POLICING_MUL & sw_flag)
+    {
+        *hw_flag |= (0x1 << 7);
+    }
+}
+
+static void
+_isisc_rate_flag_reparse(a_uint32_t hw_flag, a_uint32_t * sw_flag)
+{
+    *sw_flag = 0;
+
+    if (hw_flag & 0x2)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_TCP_CTRL;
+    }
+
+    if (hw_flag & 0x4)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_MANAGEMENT;
+    }
+
+    if (hw_flag & 0x8)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_BROAD;
+    }
+
+    if (hw_flag & 0x10)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_UNK_UNI;
+    }
+
+    if (hw_flag & 0x20)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_UNK_MUL;
+    }
+
+    if (hw_flag & 0x40)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_UNI;
+    }
+
+    if (hw_flag & 0x80)
+    {
+        *sw_flag |= FAL_INGRESS_POLICING_MUL;
+    }
+}
+
+static void
+_isisc_rate_ts_parse(fal_rate_mt_t sw, a_uint32_t * hw)
+{
+    if (FAL_RATE_MI_100US == sw)
+    {
+        *hw = 0;
+    }
+    else if (FAL_RATE_MI_1MS == sw)
+    {
+        *hw = 1;
+    }
+    else if (FAL_RATE_MI_10MS == sw)
+    {
+        *hw = 2;
+    }
+    else if (FAL_RATE_MI_100MS)
+    {
+        *hw = 3;
+    }
+    else
+    {
+        *hw = 0;
+    }
+}
+
+static void
+_isisc_rate_ts_reparse(a_uint32_t hw, fal_rate_mt_t * sw)
+{
+    if (0 == hw)
+    {
+        *sw = FAL_RATE_MI_100US;
+    }
+    else if (1 == hw)
+    {
+        *sw = FAL_RATE_MI_1MS;
+    }
+    else if (2 == hw)
+    {
+        *sw = FAL_RATE_MI_10MS;
+    }
+    else
+    {
+        *sw = FAL_RATE_MI_100MS;
+    }
+}
+
+static sw_error_t
+_isisc_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+    a_uint32_t cir = 0x7fff, eir = 0x7fff, cbs = 0, ebs = 0, tmp, data[3] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data[0] = 0x18000000;
+    if (FAL_BYTE_BASED == policer->meter_unit)
+    {
+        if (A_TRUE == policer->c_enable)
+        {
+            cir = policer->cir >> 5;
+            policer->cir = cir << 5;
+            _isisc_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs);
+            _isisc_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+        }
+
+        if (A_TRUE == policer->e_enable)
+        {
+            eir = policer->eir >> 5;
+            policer->eir = eir << 5;
+            _isisc_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs);
+            _isisc_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+        }
+
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 0, data[1]);
+    }
+    else if (FAL_FRAME_BASED == policer->meter_unit)
+    {
+        if (A_TRUE == policer->c_enable)
+        {
+            cir = (policer->cir * 2) / 125;
+            policer->cir = cir / 2 * 125 + cir % 2 * 63;
+            _isisc_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs);
+            _isisc_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+        }
+
+        if (A_TRUE == policer->e_enable)
+        {
+            eir = (policer->eir * 2) / 125;
+            policer->eir = eir / 2 * 125 + eir % 2 * 63;
+            _isisc_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs);
+            _isisc_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+        }
+
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 1, data[1]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]);
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]);
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]);
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]);
+
+    if (A_TRUE == policer->combine_mode)
+    {
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER0, RATE_MODE, 1, data[0]);
+    }
+
+    if (A_TRUE == policer->deficit_en)
+    {
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_BORROW, 1, data[1]);
+    }
+
+    if (A_TRUE == policer->color_mode)
+    {
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CM, 1, data[1]);
+    }
+
+    if (A_TRUE == policer->couple_flag)
+    {
+        SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CF, 1, data[1]);
+    }
+
+    _isisc_rate_ts_parse(policer->c_meter_interval, &tmp);
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER0, C_ING_TS, tmp, data[0]);
+
+    _isisc_rate_ts_parse(policer->e_meter_interval, &tmp);
+    SW_SET_REG_BY_FIELD(INGRESS_POLICER1, E_ING_TS, tmp, data[1]);
+
+    _isisc_rate_flag_parse(policer->c_rate_flag, &tmp);
+    data[2] = (tmp << 8) & 0xff00;
+
+    _isisc_rate_flag_parse(policer->e_rate_flag, &tmp);
+    data[2] |= (tmp & 0xff);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER0, port_id,
+                      (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER1, port_id,
+                      (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER2, port_id,
+                      (a_uint8_t *) (&data[2]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+    a_uint32_t unit, ts, cir, eir, cbs, ebs, data[3] = {0};
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER0, port_id,
+                      (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER1, port_id,
+                      (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER2, port_id,
+                      (a_uint8_t *) (&data[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_UNIT, unit, data[1]);
+
+    policer->c_enable = A_TRUE;
+    if (0x7fff == cir)
+    {
+        policer->c_enable = A_FALSE;
+        cir = 0;
+    }
+
+    policer->e_enable = A_TRUE;
+    if (0x7fff == eir)
+    {
+        policer->e_enable = A_FALSE;
+        eir = 0;
+    }
+
+    if (unit)
+    {
+        policer->meter_unit = FAL_FRAME_BASED;
+        policer->cir = cir / 2 * 125 + cir % 2 * 63;
+        policer->eir = eir / 2 * 125 + eir % 2 * 63;
+        _isisc_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+        _isisc_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+    }
+    else
+    {
+        policer->meter_unit = FAL_BYTE_BASED;
+        policer->cir = cir << 5;
+        policer->eir = eir << 5;
+        _isisc_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+        _isisc_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+    }
+
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER0, RATE_MODE, policer->combine_mode,
+                        data[0]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_BORROW, policer->deficit_en,
+                        data[1]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CF, policer->couple_flag,
+                        data[1]);
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CM, policer->color_mode,
+                        data[1]);
+
+    ts = (data[2] >> 8) & 0xff;
+    _isisc_rate_flag_reparse(ts, &(policer->c_rate_flag));
+
+    ts = data[2] & 0xff;
+    _isisc_rate_flag_reparse(ts, &(policer->e_rate_flag));
+
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER0, C_ING_TS, ts, data[0]);
+    _isisc_rate_ts_reparse(ts, &(policer->c_meter_interval));
+
+    SW_GET_FIELD_BY_REG(INGRESS_POLICER1, E_ING_TS, ts, data[1]);
+    _isisc_rate_ts_reparse(ts, &(policer->e_meter_interval));
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    a_uint32_t data, cir, eir, cbs = 0, ebs = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == enable)
+    {
+        aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+        cir = 0x7fff;
+        eir = 0x7fff;
+    }
+    else
+    {
+        if (FAL_BYTE_BASED == shaper->meter_unit)
+        {
+            cir = shaper->cir >> 5;
+            shaper->cir = cir << 5;
+
+            eir = shaper->eir >> 5;
+            shaper->eir = eir << 5;
+
+            _isisc_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs);
+            _isisc_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+
+            _isisc_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs);
+            _isisc_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+
+            data = 0;
+        }
+        else if (FAL_FRAME_BASED == shaper->meter_unit)
+        {
+            cir = (shaper->cir * 2) / 125;
+            shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+
+            eir = (shaper->eir * 2) / 125;
+            shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+
+            _isisc_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs);
+            _isisc_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+
+            _isisc_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs);
+            _isisc_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+
+            data = 1;
+        }
+        else
+        {
+            return SW_BAD_PARAM;
+        }
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        data = 1;
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+                      (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+                      (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+                      (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+                      (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, cir = 0, eir = 0, cbs = 0, ebs = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (!data)
+    {
+        *enable = A_FALSE;
+        return SW_OK;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+                      (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+                      (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+                      (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+                      (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if ((0x7fff == cir) && (0x7fff == eir))
+    {
+        *enable = A_FALSE;
+        return SW_OK;
+    }
+
+    *enable = A_TRUE;
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        shaper->meter_unit = FAL_FRAME_BASED;
+        shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+        shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+        _isisc_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+        _isisc_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+    }
+    else
+    {
+        shaper->meter_unit = FAL_BYTE_BASED;
+        shaper->cir = cir << 5;
+        shaper->eir = eir << 5;
+        _isisc_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+        _isisc_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_queue_t queue_id, a_bool_t enable,
+                            fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    a_uint32_t unit = 0, data, cir, eir, cbs = 0, ebs = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isisc_rate_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_FALSE == enable)
+    {
+        aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+        cir = 0x7fff;
+        eir = 0x7fff;
+    }
+    else
+    {
+        if (FAL_BYTE_BASED == shaper->meter_unit)
+        {
+            cir = shaper->cir >> 5;
+            shaper->cir = cir << 5;
+
+            eir = shaper->eir >> 5;
+            shaper->eir = eir << 5;
+
+            _isisc_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs);
+            _isisc_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+
+            _isisc_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs);
+            _isisc_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+
+            unit = 0;
+        }
+        else if (FAL_FRAME_BASED == shaper->meter_unit)
+        {
+            cir = (shaper->cir * 2) / 125;
+            shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+
+            eir = (shaper->eir * 2) / 125;
+            shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+
+            _isisc_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs);
+            _isisc_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+
+            _isisc_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs);
+            _isisc_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+
+            unit = 1;
+        }
+
+        data = 0;
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (4 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT,
+                          (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_queue_t queue_id, a_bool_t * enable,
+                            fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0, cir = 0, eir = 0, cbs = 0, ebs = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isisc_rate_port_queue_check(port_id, queue_id);
+    SW_RTN_ON_ERROR(rv);
+
+    aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+    HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data)
+    {
+        *enable = A_FALSE;
+        return SW_OK;
+    }
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else if (4 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR,
+                          (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR,
+                          (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS,
+                          (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS,
+                          (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    if ((0x7fff == cir) && (0x7fff == eir))
+    {
+        *enable = A_FALSE;
+        return SW_OK;
+    }
+
+    *enable = A_TRUE;
+    if (data)
+    {
+        shaper->meter_unit = FAL_FRAME_BASED;
+        shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+        shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+        _isisc_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+        _isisc_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+    }
+    else
+    {
+        shaper->meter_unit = FAL_BYTE_BASED;
+        shaper->cir = cir << 5;
+        shaper->eir = eir << 5;
+        _isisc_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+        _isisc_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+                           fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+    a_uint32_t ts, cir, eir, cbs = 0, ebs = 0, addr, data[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISISC_MAX_POLICER_ID < policer_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == policer->counter_mode)
+    {
+        addr = ACL_POLICER_CNT_SEL_ADDR;
+        data[0] = 0x1;
+        HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+                              (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        addr = ACL_POLICER_CNT_MODE_ADDR;
+        if (FAL_FRAME_BASED == policer->meter_unit)
+        {
+            data[0] = 0x0;
+        }
+        else
+        {
+            data[0] = 0x1;
+        }
+        HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+                              (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        addr = ACL_POLICER_CNT_RST_ADDR;
+        data[0] = 0x1;
+        HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+                              (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        data[0] = 0x0;
+        HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+                              (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        return rv;
+    }
+
+    addr = ACL_POLICER_CNT_SEL_ADDR;
+    data[0] = 0x0;
+    HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+                          (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_BYTE_BASED == policer->meter_unit)
+    {
+        cir = policer->cir >> 5;
+        policer->cir = cir << 5;
+
+        eir = policer->eir >> 5;
+        policer->eir = eir << 5;
+
+        _isisc_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs);
+        _isisc_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+
+        _isisc_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs);
+        _isisc_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+
+        SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 0, data[1]);
+    }
+    else if (FAL_FRAME_BASED == policer->meter_unit)
+    {
+        cir = (policer->cir * 2) / 125;
+        policer->cir = cir / 2 * 125 + cir % 2 * 63;
+
+        eir = (policer->eir * 2) / 125;
+        policer->eir = eir / 2 * 125 + eir % 2 * 63;
+
+        _isisc_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs);
+        _isisc_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+
+        _isisc_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs);
+        _isisc_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+
+        SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 1, data[1]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CIR, cir, data[0]);
+    SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CBS, cbs, data[0]);
+    SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EIR, eir, data[1]);
+    SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EBS, ebs, data[1]);
+
+    if (A_TRUE == policer->deficit_en)
+    {
+        SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_BORROW, 1, data[1]);
+    }
+
+    if (A_TRUE == policer->color_mode)
+    {
+        SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CM, 1, data[1]);
+    }
+
+    if (A_TRUE == policer->couple_flag)
+    {
+        SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CF, 1, data[1]);
+    }
+
+    _isisc_rate_ts_parse(policer->meter_interval, &ts);
+    SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_TS, ts, data[1]);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER0, policer_id,
+                      (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER1, policer_id,
+                      (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+                           fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+    a_uint32_t unit, ts, cir, eir, cbs, ebs, addr, data[2] = {0};
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (ISISC_MAX_POLICER_ID < policer_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(policer, sizeof (policer));
+
+    addr = ACL_POLICER_CNT_SEL_ADDR;
+    HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id,
+                          (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (data[0])
+    {
+        policer->counter_mode = A_TRUE;
+
+        addr = ACL_POLICER_CNT_MODE_ADDR;
+        HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id,
+                              (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        if (data[0])
+        {
+            policer->meter_unit = FAL_BYTE_BASED;
+        }
+        else
+        {
+            policer->meter_unit = FAL_FRAME_BASED;
+        }
+
+        HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER0, policer_id,
+                          (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER1, policer_id,
+                          (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        policer->counter_low = data[0];
+        policer->counter_high = data[1];
+
+        return SW_OK;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER0, policer_id,
+                      (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER1, policer_id,
+                      (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+
+    SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CIR, cir, data[0]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CBS, cbs, data[0]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EIR, eir, data[1]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EBS, ebs, data[1]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_UNIT, unit, data[1]);
+    if (unit)
+    {
+        policer->meter_unit = FAL_FRAME_BASED;
+        policer->cir = cir / 2 * 125 + cir % 2 * 63;
+        policer->eir = eir / 2 * 125 + eir % 2 * 63;
+        _isisc_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+        _isisc_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+
+    }
+    else
+    {
+        policer->meter_unit = FAL_BYTE_BASED;
+        policer->cir = cir << 5;
+        policer->eir = eir << 5;
+        _isisc_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+        _isisc_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_BORROW, policer->deficit_en,
+                        data[1]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CF, policer->couple_flag, data[1]);
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CM, policer->color_mode, data[1]);
+
+    SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_TS, ts, data[1]);
+    _isisc_rate_ts_reparse(ts, &(policer->meter_interval));
+
+    return SW_OK;
+}
+
+sw_error_t
+_isisc_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t  number)
+{
+    a_uint32_t val = number;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (val>255)
+        return SW_BAD_PARAM;
+
+    HSL_REG_FIELD_SET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+sw_error_t
+_isisc_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_uint32_t  *number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv = SW_OK;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+
+    HSL_REG_FIELD_GET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    *number = val;
+
+    return rv;
+}
+
+sw_error_t
+_isisc_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t  enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, QM_CTRL_REG, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+
+    if (A_TRUE == enable)
+    {
+        val |= (0x1<<(16+port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        val &= ~(0x1<<(16+port_id));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, QM_CTRL_REG, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+sw_error_t
+_isisc_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t*  enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, QM_CTRL_REG, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (val&(0x1<<(16+port_id)))
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+
+
+/**
+ * @brief Set port ingress policer parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port ingress policer input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] policer port ingress policer parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_rate_port_policer_set(dev_id, port_id, policer);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port ingress policer parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port ingress policer input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] policer port ingress policer parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_port_policer_t * policer)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_rate_port_policer_get(dev_id, port_id, policer);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port egress shaper parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port egress shaper parameters is meaningless.
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_rate_port_shaper_set(dev_id, port_id, enable, shaper);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port egress shaper parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port egress shaper parameters is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable, fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_rate_port_shaper_get(dev_id, port_id, enable, shaper);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set queue egress shaper parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable queue egress shaper parameters is meaningless.
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_queue_t queue_id, a_bool_t enable,
+                           fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_rate_queue_shaper_set(dev_id, port_id, queue_id, enable, shaper);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get queue egress shaper parameters on one particular port.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable queue egress shaper parameters is meaningless.
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_queue_t queue_id, a_bool_t * enable,
+                           fal_egress_shaper_t * shaper)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_rate_queue_shaper_get(dev_id, port_id, queue_id, enable, shaper);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ACL ingress policer parameters.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+ * @param[in] dev_id device id
+ * @param[in] policer_id ACL policer id
+ * @param[in] policer ACL ingress policer parameters
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+                          fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_rate_acl_policer_set(dev_id, policer_id, policer);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ACL ingress policer parameters.
+ * @details   Comments:
+    The granularity of speed is 32kbps or 62.5fps.
+    Because of hardware granularity function will return actual speed in hardware.
+ * @param[in] dev_id device id
+ * @param[in] policer_id ACL policer id
+ * @param[in] policer ACL ingress policer parameters
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+                          fal_acl_policer_t * policer)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_rate_acl_policer_get(dev_id, policer_id, policer);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+isisc_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t  number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_rate_port_add_rate_byte_set(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+HSL_LOCAL sw_error_t
+isisc_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_uint32_t  *number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_rate_port_add_rate_byte_get(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of port global flow control when global threshold is reached.
+  * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_rate_port_gol_flow_en_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief get status of port global flow control when global threshold is reached.
+  * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t* enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_rate_port_gol_flow_en_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+
+
+sw_error_t
+isisc_rate_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->rate_port_policer_set = isisc_rate_port_policer_set;
+        p_api->rate_port_policer_get = isisc_rate_port_policer_get;
+        p_api->rate_port_shaper_set = isisc_rate_port_shaper_set;
+        p_api->rate_port_shaper_get = isisc_rate_port_shaper_get;
+        p_api->rate_queue_shaper_set = isisc_rate_queue_shaper_set;
+        p_api->rate_queue_shaper_get = isisc_rate_queue_shaper_get;
+        p_api->rate_acl_policer_set = isisc_rate_acl_policer_set;
+        p_api->rate_acl_policer_get = isisc_rate_acl_policer_get;
+        p_api->rate_port_gol_flow_en_set = isisc_rate_port_gol_flow_en_set;
+        p_api->rate_port_gol_flow_en_get = isisc_rate_port_gol_flow_en_get;
+        p_api->rate_port_add_rate_byte_set=isisc_rate_port_add_rate_byte_set;
+        p_api->rate_port_add_rate_byte_get=isisc_rate_port_add_rate_byte_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_reg_access.c b/qca-ssdk/src/hsl/isisc/isisc_reg_access.c
new file mode 100755
index 0000000..8b90afc
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_reg_access.c
@@ -0,0 +1,459 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "sd.h"
+#include "isisc_reg_access.h"
+
+#if 0
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <asm/uaccess.h>
+#include <linux/mm.h>
+#endif
+
+static hsl_access_mode reg_mode;
+
+#if defined(API_LOCK)
+static aos_lock_t mdio_lock;
+#define MDIO_LOCKER_INIT    aos_lock_init(&mdio_lock)
+#define MDIO_LOCKER_LOCK    aos_lock(&mdio_lock)
+#define MDIO_LOCKER_UNLOCK  aos_unlock(&mdio_lock)
+#else
+#define MDIO_LOCKER_INIT
+#define MDIO_LOCKER_LOCK
+#define MDIO_LOCKER_UNLOCK
+#endif
+
+#if defined(REG_ACCESS_SPEEDUP)
+static a_uint32_t mdio_base_addr = 0xffffffff;
+#endif
+
+static sw_error_t
+_isisc_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+#if 0
+    /* change reg_addr to 16-bit word address, 32-bit aligned */
+    reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+    /* configure register high address */
+    phy_addr = 0x18;
+    phy_reg = 0x0;
+    phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+
+#if defined(REG_ACCESS_SPEEDUP)
+    if (phy_val != mdio_base_addr)
+    {
+        rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+        SW_RTN_ON_ERROR(rv);
+
+        mdio_base_addr = phy_val;
+    }
+#else
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+    /* For some registers such as MIBs, since it is read/clear, we should */
+    /* read the lower 16-bit register then the higher one */
+
+    /* read register in lower address */
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+    SW_RTN_ON_ERROR(rv);
+    reg_val = tmp_val;
+
+    /* read register in higher address */
+    reg_word_addr++;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+    SW_RTN_ON_ERROR(rv);
+    reg_val |= (((a_uint32_t)tmp_val) << 16);
+#else
+    reg_val = sd_reg_mii_get(dev_id, reg_addr);
+#endif
+    aos_mem_copy(value, &reg_val, sizeof (a_uint32_t));
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                   a_uint32_t value_len)
+{
+    a_uint32_t reg_val = 0;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    aos_mem_copy(&reg_val, value, sizeof (a_uint32_t));
+
+#if 0
+    /* change reg_addr to 16-bit word address, 32-bit aligned */
+    reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+    /* configure register high address */
+    phy_addr = 0x18;
+    phy_reg = 0x0;
+    phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+
+#if defined(REG_ACCESS_SPEEDUP)
+    if (phy_val != mdio_base_addr)
+    {
+        rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+        SW_RTN_ON_ERROR(rv);
+
+        mdio_base_addr = phy_val;
+    }
+#else
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+    /* For some registers such as ARL and VLAN, since they include BUSY bit */
+    /* in higher address, we should write the lower 16-bit register then the */
+    /* higher one */
+
+    /* write register in lower address */
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (a_uint16_t) (reg_val & 0xffff);
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    /* write register in higher address */
+    reg_word_addr++;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff);
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+#else
+    sd_reg_mii_set(dev_id, reg_addr, reg_val);
+#endif
+    return SW_OK;
+}
+
+sw_error_t
+isisc_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+             a_uint32_t reg, a_uint16_t * value)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value);
+    MDIO_LOCKER_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isisc_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+             a_uint32_t reg, a_uint16_t value)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value);
+    MDIO_LOCKER_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isisc_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+             a_uint32_t value_len)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    if (HSL_MDIO == reg_mode)
+    {
+        rv = _isisc_mdio_reg_get(dev_id, reg_addr, value, value_len);
+    }
+    else
+    {
+        rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len);
+    }
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+isisc_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+             a_uint32_t value_len)
+{
+    sw_error_t rv;
+#if 0
+    unsigned long flags;
+
+    struct file *filp;
+    // mm_segment_t fs;
+    a_uint32_t rt_value = 0;
+    a_uint32_t write_flag = 0;
+    char s[20]= {0};
+    a_uint32_t tmp_val = *((a_uint32_t *) value);
+
+    /*get MODULE_EN reg rsv */
+    SW_RTN_ON_ERROR(isisc_reg_get(dev_id, 0x30,(void *)&rt_value,4));
+    write_flag = (rt_value>>15) & 0x1;
+#endif
+    MDIO_LOCKER_LOCK;
+    if (HSL_MDIO == reg_mode)
+    {
+        rv = _isisc_mdio_reg_set(dev_id, reg_addr, value, value_len);
+    }
+    else
+    {
+        rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len);
+    }
+    MDIO_LOCKER_UNLOCK;
+
+#if 0
+    if(write_flag)
+    {
+        filp = filp_open("/tmp/asic_output", O_RDWR|O_APPEND, 0644);
+        if(IS_ERR(filp))
+        {
+            printk("open error...\n");
+            return;
+        }
+
+        fs=get_fs();
+
+        set_fs(KERNEL_DS);
+        sprintf(s,"%08x %08x\n",reg_addr,tmp_val);
+        filp->f_op->write(filp, s, strlen(s),&filp->f_pos);
+
+        set_fs(fs);
+
+        filp_close(filp,NULL);
+    }
+#endif
+
+    return rv;
+}
+
+sw_error_t
+isisc_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint32_t bit_offset, a_uint32_t field_len,
+                   a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val = 0;
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(isisc_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+
+    if(32 == field_len)
+    {
+        *((a_uint32_t *) value) = reg_val;
+    }
+    else
+    {
+        *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len);
+    }
+    return SW_OK;
+}
+
+sw_error_t
+isisc_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                   a_uint32_t bit_offset, a_uint32_t field_len,
+                   const a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val = 0;
+    a_uint32_t field_val = *((a_uint32_t *) value);
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(isisc_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    if(32 == field_len)
+    {
+        reg_val = field_val;
+    }
+    else
+    {
+        SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len);
+    }
+
+
+    SW_RTN_ON_ERROR(isisc_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_isisc_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump)
+{
+    sw_error_t rv = SW_OK;
+	typedef struct {
+		a_uint32_t reg_base;
+		a_uint32_t reg_end;
+		char name[30];
+	} regdump;
+
+	regdump reg_dumps[8] =
+	{
+		{0x0, 0xE4, "0.Global control registers"},
+		{0x100, 0x168, "1.EEE control registers"},
+		{0x200, 0x270, "2.Parser control registers"},
+		{0x400, 0x474, "3.ACL control registers"},
+		{0x600, 0x718, "4.Lookup control registers"},
+		{0x800, 0xb70, "5.QM control registers"},
+		{0xc00, 0xc80, "6.PKT edit control registers"},
+		{0x820, 0x820, "7.QM debug registers"}
+	};
+
+	a_uint32_t dump_addr, reg_count, reg_val = 0;
+	switch (register_idx)
+	{
+		case 0:
+		case 1:
+		case 2:
+		case 3:
+		case 4:
+		case 5:
+		case 6:
+			reg_count = 0;
+			for (dump_addr = reg_dumps[register_idx].reg_base; dump_addr <= reg_dumps[register_idx].reg_end; reg_count++)
+			{
+				rv = isisc_reg_get(dev_id, dump_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t));
+				reg_dump->reg_value[reg_count] = reg_val;
+				dump_addr += 4;
+			}
+			reg_dump->reg_count = reg_count;
+			reg_dump->reg_base = reg_dumps[register_idx].reg_base;
+			reg_dump->reg_end = reg_dumps[register_idx].reg_end;
+			snprintf((char *)reg_dump->reg_name,sizeof(reg_dump->reg_name),"%s",reg_dumps[register_idx].name);
+			break;
+		default:
+			return SW_BAD_PARAM;
+	}
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_debug_regsiter_dump(a_uint32_t dev_id,fal_debug_reg_dump_t * dbg_reg_dump)
+{
+    sw_error_t rv = SW_OK;
+    a_uint32_t reg;
+	a_uint32_t  reg_count, reg_val = 0;
+
+	reg_count = 0;
+
+	for(reg=0;reg<=0x1F;reg++)
+	{
+		isisc_reg_set(dev_id, 0x820, (a_uint8_t *) & reg, sizeof (a_uint32_t));
+		rv = isisc_reg_get(dev_id, 0x824, (a_uint8_t *) & reg_val, sizeof (a_uint32_t));
+		dbg_reg_dump->reg_value[reg_count] = reg_val;
+		dbg_reg_dump->reg_addr[reg_count] = reg;
+		reg_count++;
+	}
+	dbg_reg_dump->reg_count = reg_count;
+
+	snprintf((char *)dbg_reg_dump->reg_name,sizeof(dbg_reg_dump->reg_name),"QM debug registers");
+
+    return rv;
+}
+
+
+/**
+ * @brief dump registers.
+ * @param[in] dev_id device id
+ * @param[in] register_idx register group id
+ * @param[out] reg_dump register dump result
+ * @return SW_OK or error code
+ */
+sw_error_t
+isisc_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _isisc_regsiter_dump(dev_id,register_idx,reg_dump);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief dump registers.
+ * @param[in] dev_id device id
+ * @param[out] reg_dump debug register dump
+ * @return SW_OK or error code
+ */
+sw_error_t
+isisc_debug_regsiter_dump(a_uint32_t dev_id, fal_debug_reg_dump_t * dbg_reg_dump)
+{
+    sw_error_t rv = SW_OK;
+
+    FAL_API_LOCK;
+    rv = _isisc_debug_regsiter_dump(dev_id,dbg_reg_dump);
+    FAL_API_UNLOCK;
+    return rv;
+}
+
+
+
+sw_error_t
+isisc_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode)
+{
+    hsl_api_t *p_api;
+
+    MDIO_LOCKER_INIT;
+    reg_mode = mode;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+    p_api->phy_get = isisc_phy_get;
+    p_api->phy_set = isisc_phy_set;
+    p_api->reg_get = isisc_reg_get;
+    p_api->reg_set = isisc_reg_set;
+    p_api->reg_field_get = isisc_reg_field_get;
+    p_api->reg_field_set = isisc_reg_field_set;
+	p_api->register_dump = isisc_regsiter_dump;
+	p_api->debug_register_dump = isisc_debug_regsiter_dump;
+
+    return SW_OK;
+}
+
+sw_error_t
+isisc_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode)
+{
+    reg_mode = mode;
+    return SW_OK;
+
+}
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_sec.c b/qca-ssdk/src/hsl/isisc/isisc_sec.c
new file mode 100755
index 0000000..579868f
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_sec.c
@@ -0,0 +1,787 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_sec ISISC_SEC
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_sec.h"
+#include "isisc_reg.h"
+
+#define NORM_CTRL0_ADDR 0x0200
+#define NORM_CTRL1_ADDR 0x0204
+#define NORM_CTRL2_ADDR 0x0208
+#define NORM_CTRL3_ADDR 0x0c00
+
+static sw_error_t
+_isisc_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+    fal_fwd_cmd_t cmd;
+    a_bool_t enable;
+    a_uint32_t addr, offset, len, reg = 0, val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    cmd = *((fal_fwd_cmd_t *) value);
+    enable = *((a_bool_t *) value);
+    val = *((a_uint32_t *) value);
+
+    len = 1;
+    switch (item)
+    {
+        case FAL_NORM_MAC_RESV_VID_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 0;
+            goto cmd_chk;
+
+        case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 20;
+            goto cmd_chk;
+
+        case FAL_NORM_IP_INVALID_VER_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 1;
+            goto cmd_chk;
+
+        case FAL_NROM_IP_SAME_ADDR_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 2;
+            goto cmd_chk;
+            break;
+
+        case FAL_NROM_IP_TTL_CHANGE_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 11;
+            goto sts_chk;
+
+        case FAL_NROM_IP_TTL_VALUE:
+            addr = NORM_CTRL3_ADDR;
+            offset = 12;
+            len = 8;
+            goto set_reg;
+
+        case FAL_NROM_IP4_INVALID_HL_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 3;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_HDR_OPTIONS_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 4;
+            len = 2;
+            goto s_cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_DF_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 7;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 8;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE:
+            addr = NORM_CTRL1_ADDR;
+            offset = 24;
+            len = 8;
+            goto set_reg;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 9;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 10;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_SIP_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 11;
+            len = 1;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_DIP_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 12;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 13;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_INVALID_PL_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 19;
+            goto cmd_chk;
+
+        case FAL_NROM_IP4_DF_CLEAR_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 9;
+            goto sts_chk;
+
+        case FAL_NROM_IP4_IPID_RANDOM_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 10;
+            goto sts_chk;
+
+        case FAL_NROM_IP6_INVALID_DIP_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 16;
+            goto cmd_chk;
+
+        case FAL_NROM_IP6_INVALID_SIP_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 17;
+            goto cmd_chk;
+
+        case FAL_NROM_IP6_INVALID_PL_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 18;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_BLAT_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 14;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_INVALID_HL_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 15;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_MIN_HDR_SIZE:
+            addr = NORM_CTRL1_ADDR;
+            offset = 12;
+            len = 4;
+            goto set_reg;
+
+        case FAL_NROM_TCP_INVALID_SYN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 16;
+            goto cmd_chk;
+            break;
+
+        case FAL_NROM_TCP_SU_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 17;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SP_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 18;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SAP_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 19;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_XMAS_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 20;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_NULL_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 21;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SR_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 22;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SF_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 23;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SAR_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 24;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_RST_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 25;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_SYN_WITH_DATA_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 26;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_RST_WITH_DATA_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 27;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_FA_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 28;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_PA_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 29;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_UA_BLOCK_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 0;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 1;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_INVALID_URGPTR_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 2;
+            goto cmd_chk;
+
+        case FAL_NROM_TCP_INVALID_OPTIONS_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 3;
+            goto cmd_chk;
+
+        case FAL_NROM_UDP_BLAT_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 4;
+            goto cmd_chk;
+
+        case FAL_NROM_UDP_INVALID_LEN_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 5;
+            goto cmd_chk;
+
+        case FAL_NROM_UDP_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 6;
+            goto cmd_chk;
+
+        case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 7;
+            goto cmd_chk;
+
+        case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 8;
+            goto cmd_chk;
+
+        case FAL_NROM_ICMP4_PING_FRAG_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 9;
+            goto cmd_chk;
+
+        case FAL_NROM_ICMP6_PING_FRAG_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 10;
+            goto cmd_chk;
+
+        case FAL_NROM_ICMP4_PING_MAX_PL_VALUE:
+            addr = NORM_CTRL2_ADDR;
+            offset = 0;
+            len = 14;
+            goto set_reg;
+
+        case FAL_NROM_ICMP6_PING_MAX_PL_VALUE:
+            addr = NORM_CTRL2_ADDR;
+            offset = 16;
+            len = 14;
+            goto set_reg;
+
+        default:
+            return SW_BAD_PARAM;
+    }
+
+sts_chk:
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    goto set_reg;
+
+s_cmd_chk:
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_DROP == cmd)
+    {
+        val = 3;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 2;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    goto set_reg;
+
+cmd_chk:
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_DROP == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+set_reg:
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_REG_SET_BY_FIELD_U32(reg, val, offset, len);
+
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+    a_uint32_t addr, offset, len, reg = 0, val;
+    a_uint32_t status_chk = 0, val_chk = 0, scmd_chk = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    len = 1;
+    switch (item)
+    {
+        case FAL_NORM_MAC_RESV_VID_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 0;
+            break;
+
+        case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 20;
+            break;
+
+        case FAL_NORM_IP_INVALID_VER_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 1;
+            break;
+
+        case FAL_NROM_IP_SAME_ADDR_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 2;
+            break;
+
+        case FAL_NROM_IP_TTL_CHANGE_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 11;
+            status_chk = 1;
+            break;
+
+        case FAL_NROM_IP_TTL_VALUE:
+            addr = NORM_CTRL3_ADDR;
+            offset = 12;
+            len = 8;
+            val_chk = 1;
+            break;
+
+        case FAL_NROM_IP4_INVALID_HL_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 3;
+            break;
+
+        case FAL_NROM_IP4_HDR_OPTIONS_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 4;
+            len = 2;
+            scmd_chk = 1;
+            break;
+
+        case FAL_NROM_IP4_INVALID_DF_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 7;
+            break;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 8;
+            break;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE:
+            addr = NORM_CTRL1_ADDR;
+            offset = 24;
+            len = 8;
+            val_chk = 1;
+            break;
+
+        case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 9;
+            break;
+
+        case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 10;
+            break;
+
+        case FAL_NROM_IP4_INVALID_SIP_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 11;
+            len = 1;
+            break;
+
+        case FAL_NROM_IP4_INVALID_DIP_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 12;
+            break;
+
+        case FAL_NROM_IP4_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 13;
+            break;
+
+        case FAL_NROM_IP4_INVALID_PL_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 19;
+            break;
+
+        case FAL_NROM_IP4_DF_CLEAR_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 9;
+            status_chk = 1;
+            break;
+
+        case FAL_NROM_IP4_IPID_RANDOM_STATUS:
+            addr = NORM_CTRL3_ADDR;
+            offset = 10;
+            status_chk = 1;
+            break;
+
+        case FAL_NROM_IP6_INVALID_DIP_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 16;
+            break;
+
+        case FAL_NROM_IP6_INVALID_SIP_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 17;
+            break;
+
+        case FAL_NROM_IP6_INVALID_PL_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 18;
+            break;
+
+        case FAL_NROM_TCP_BLAT_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 14;
+            break;
+
+        case FAL_NROM_TCP_INVALID_HL_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 15;
+            break;
+
+        case FAL_NROM_TCP_MIN_HDR_SIZE:
+            addr = NORM_CTRL1_ADDR;
+            offset = 12;
+            len = 4;
+            val_chk = 1;
+            break;
+
+        case FAL_NROM_TCP_INVALID_SYN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 16;
+            break;
+
+        case FAL_NROM_TCP_SU_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 17;
+            break;
+
+        case FAL_NROM_TCP_SP_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 18;
+            break;
+
+        case FAL_NROM_TCP_SAP_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 19;
+            break;
+
+        case FAL_NROM_TCP_XMAS_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 20;
+            break;
+
+        case FAL_NROM_TCP_NULL_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 21;
+            break;
+
+        case FAL_NROM_TCP_SR_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 22;
+            break;
+
+        case FAL_NROM_TCP_SF_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 23;
+            break;
+
+        case FAL_NROM_TCP_SAR_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 24;
+            break;
+
+        case FAL_NROM_TCP_RST_SCAN_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 25;
+            break;
+
+        case FAL_NROM_TCP_SYN_WITH_DATA_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 26;
+            break;
+
+        case FAL_NROM_TCP_RST_WITH_DATA_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 27;
+            break;
+
+        case FAL_NROM_TCP_FA_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 28;
+            break;
+
+        case FAL_NROM_TCP_PA_BLOCK_CMD:
+            addr = NORM_CTRL0_ADDR;
+            offset = 29;
+            break;
+
+        case FAL_NROM_TCP_UA_BLOCK_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 0;
+            break;
+
+        case FAL_NROM_TCP_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 1;
+            break;
+
+        case FAL_NROM_TCP_INVALID_URGPTR_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 2;
+            break;
+
+        case FAL_NROM_TCP_INVALID_OPTIONS_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 3;
+            break;
+
+        case FAL_NROM_UDP_BLAT_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 4;
+            break;
+
+        case FAL_NROM_UDP_INVALID_LEN_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 5;
+            break;
+
+        case FAL_NROM_UDP_INVALID_CHKSUM_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 6;
+            break;
+
+        case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 7;
+            break;
+
+        case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 8;
+            break;
+
+        case FAL_NROM_ICMP4_PING_FRAG_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 9;
+            break;
+
+        case FAL_NROM_ICMP6_PING_FRAG_CMD:
+            addr = NORM_CTRL1_ADDR;
+            offset = 10;
+            break;
+
+        case FAL_NROM_ICMP4_PING_MAX_PL_VALUE:
+            addr = NORM_CTRL2_ADDR;
+            offset = 0;
+            len = 14;
+            val_chk = 1;
+            break;
+
+        case FAL_NROM_ICMP6_PING_MAX_PL_VALUE:
+            addr = NORM_CTRL2_ADDR;
+            offset = 16;
+            len = 14;
+            val_chk = 1;
+            break;
+
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_FIELD_GET_BY_REG_U32(reg, val, offset, len);
+
+    if (val_chk)
+    {
+        *((a_uint32_t *) value) = val;
+    }
+    else if (status_chk)
+    {
+        if (val)
+        {
+            *((a_bool_t *) value) = A_TRUE;
+        }
+        else
+        {
+            *((a_bool_t *) value) = A_FALSE;
+        }
+    }
+    else if (scmd_chk)
+    {
+        if (2 == val)
+        {
+            *((fal_fwd_cmd_t *) value) = FAL_MAC_RDT_TO_CPU;
+        }
+        else if (3 == val)
+        {
+            *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP;
+        }
+        else
+        {
+            *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD;
+        }
+    }
+    else
+    {
+        if (val)
+        {
+            *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP;
+        }
+        else
+        {
+            *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD;
+        }
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set normalization particular item types value.
+ * @details   Comments:
+ *       This operation will set normalization item values on a particular device.
+ *       The prototye of value based on the item type.
+ * @param[in] dev_id device id
+ * @param[in] item normalizaton item type
+ * @param[in] value normalizaton item value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_sec_norm_item_set(dev_id, item, value);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get normalization particular item types value.
+ * @details   Comments:
+ *       This operation will set normalization item values on a particular device.
+ *       The prototye of value based on the item type.
+ * @param[in] dev_id device id
+ * @param[in] item normalizaton item type
+ * @param[out] value normalizaton item value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_sec_norm_item_get(dev_id, item, value);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isisc_sec_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->sec_norm_item_set = isisc_sec_norm_item_set;
+        p_api->sec_norm_item_get = isisc_sec_norm_item_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/qca-ssdk/src/hsl/isisc/isisc_stp.c b/qca-ssdk/src/hsl/isisc/isisc_stp.c
new file mode 100755
index 0000000..dc17162
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_stp.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_stp ISISC_STP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_stp.h"
+#include "isisc_reg.h"
+
+#define ISISC_PORT_DISABLED      0
+#define ISISC_STP_BLOCKING       1
+#define ISISC_STP_LISTENING      2
+#define ISISC_STP_LEARNING       3
+#define ISISC_STP_FARWARDING     4
+
+static sw_error_t
+_isisc_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                         fal_port_t port_id, fal_stp_state_t state)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SINGLE_STP_ID != st_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    switch (state)
+    {
+        case FAL_STP_BLOKING:
+            val = ISISC_STP_BLOCKING;
+            break;
+        case FAL_STP_LISTENING:
+            val = ISISC_STP_LISTENING;
+            break;
+        case FAL_STP_LEARNING:
+            val = ISISC_STP_LEARNING;
+            break;
+        case FAL_STP_FARWARDING:
+            val = ISISC_STP_FARWARDING;
+            break;
+        case FAL_STP_DISABLED:
+            val =  ISISC_PORT_DISABLED;
+            break;
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                         fal_port_t port_id, fal_stp_state_t * state)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SINGLE_STP_ID != st_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    switch (val)
+    {
+        case ISISC_STP_BLOCKING:
+            *state = FAL_STP_BLOKING;
+            break;
+        case ISISC_STP_LISTENING:
+            *state = FAL_STP_LISTENING;
+            break;
+        case ISISC_STP_LEARNING:
+            *state = FAL_STP_LEARNING;
+            break;
+        case ISISC_STP_FARWARDING:
+            *state = FAL_STP_FARWARDING;
+            break;
+        case ISISC_PORT_DISABLED:
+            *state = FAL_STP_DISABLED;
+            break;
+        default:
+            return SW_FAIL;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set port stp state on a particular spanning tree and port.
+ *   @details   Comments:
+    Garuda only support single spanning tree so st_id should be
+    FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[in] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                        fal_port_t port_id, fal_stp_state_t state)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_stp_port_state_set(dev_id, st_id, port_id, state);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port stp state on a particular spanning tree and port.
+ *   @details  Comments:
+    Garuda only support single spanning tree so st_id should be
+    FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[out] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                        fal_port_t port_id, fal_stp_state_t * state)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_stp_port_state_get(dev_id, st_id, port_id, state);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isisc_stp_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->stp_port_state_set = isisc_stp_port_state_set;
+        p_api->stp_port_state_get = isisc_stp_port_state_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_trunk.c b/qca-ssdk/src/hsl/isisc/isisc_trunk.c
new file mode 100755
index 0000000..2ed7936
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_trunk.c
@@ -0,0 +1,692 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+/**
+ * @defgroup isisc_trunk ISISC_TRUNK
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_trunk.h"
+#include "isisc_reg.h"
+
+#define ISISC_MAX_TRUNK_ID    3
+
+/*feature on/off for manipulating dp within trunk group*/
+#define ISISC_TRUNK_MANIPULATE_DP_ON       1
+#define ISISC_TRUNK_MANIPULATE_HEADER_LEN 12
+#define MAC_LEN                           6
+#define HASH_SIZE                         4
+
+enum isisc_trunk_reg_id
+{
+    ISISC_TRUNK_HASH_EN = 0, /*0x270*/
+    ISISC_TRUNK_CTRL_0,        /*0x700*/
+    ISISC_TRUNK_CTRL_1,        /*0x704*/
+    ISISC_TRUNK_CTRL_2,        /*0x708*/
+    ISISC_TRUNK_REG_MAX
+};
+
+static a_uint32_t isisc_trunk_regs[ISISC_TRUNK_REG_MAX] =
+{
+    0xf, 0x0, 0x0, 0x0
+};
+
+static a_uint8_t sa_hash[HASH_SIZE][MAC_LEN] =
+{
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 },
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 },
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x03 }
+};
+
+static sw_error_t
+_isisc_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+                      a_bool_t enable, fal_pbmp_t member)
+{
+    sw_error_t rv;
+    a_uint32_t i, reg = 0, cnt = 0, data0 = 0, data1 = 0;
+
+    if (ISISC_MAX_TRUNK_ID < trunk_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data0 = (0x1 << 7) | member;
+
+        for (i = 0; i < 7; i++)
+        {
+            if (member & (0x1 << i))
+            {
+                if (4 <= cnt)
+                {
+                    return SW_BAD_PARAM;
+                }
+
+                data1 |= (i << (cnt << 2));
+                data1 |= (1 << (3 + (cnt << 2)));
+                cnt++;
+            }
+        }
+    }
+    else if (A_FALSE == enable)
+    {
+
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    /* set trunk port member bitmap info */
+    HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    reg &= (~(0xff << (trunk_id << 3)));
+    reg |= (data0 << (trunk_id << 3));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    isisc_trunk_regs[ISISC_TRUNK_CTRL_0] = reg;
+
+    /* set trunk port member id info */
+    HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1),
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    reg &= (~(0xffff << ((trunk_id % 2) << 4)));
+    reg |= (data1 << ((trunk_id % 2) << 4));
+
+    HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1),
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    isisc_trunk_regs[ISISC_TRUNK_CTRL_1 + (trunk_id >> 1)] = reg;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+                      a_bool_t * enable, fal_pbmp_t * member)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg = 0;
+
+    if (ISISC_MAX_TRUNK_ID < trunk_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = (reg >> (trunk_id << 3)) & 0xff;
+    if (0x80 & data)
+    {
+        *enable = A_TRUE;
+        *member = data & 0x7f;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *member = 0;
+    }
+
+    return SW_OK;
+}
+
+#if 0
+static sw_error_t
+_isisc_trunk_group_sw_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+                          a_bool_t * enable, fal_pbmp_t * member)
+{
+    a_uint32_t data, reg;
+
+    if (ISISC_MAX_TRUNK_ID < trunk_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    reg = isisc_trunk_regs[ISISC_TRUNK_CTRL_0];
+
+    data = (reg >> (trunk_id << 3)) & 0xff;
+    if (0x80 & data)
+    {
+        *enable = A_TRUE;
+        *member = data & 0x7f;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *member = 0;
+    }
+
+    return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isisc_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    if (FAL_TRUNK_HASH_KEY_DA & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DA_EN, 1, data);
+    }
+
+    if (FAL_TRUNK_HASH_KEY_SA & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SA_EN, 1, data);
+    }
+
+    if (FAL_TRUNK_HASH_KEY_DIP & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DIP_EN, 1, data);
+    }
+
+    if (FAL_TRUNK_HASH_KEY_SIP & hash_mode)
+    {
+        SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SIP_EN, 1, data);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, TRUNK_HASH_MODE, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    isisc_trunk_regs[ISISC_TRUNK_HASH_EN] = data;
+
+    return rv;
+}
+
+static sw_error_t
+_isisc_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data = 0;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, TRUNK_HASH_MODE, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *hash_mode = 0;
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DA_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_DA;
+    }
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SA_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_SA;
+    }
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DIP_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_DIP;
+    }
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SIP_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_SIP;
+    }
+
+    return SW_OK;
+}
+
+#define BYTE_B2R(x, mask) ((x) ^ (mask))
+#define BYTE_B1C(x) ((((((x&0x55)+((x&0xaa)>>1))&0x33)+((((x&0x55)+((x&0xaa)>>1))&0xcc)>>2))&0x0f)+((((((x&0x55)+((x&0xaa)>>1))&0x33)+((((x&0x55)+((x&0xaa)>>1))&0xcc)>>2))&0xf0)>>4))
+
+static sw_error_t
+_isisc_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < HASH_SIZE; i++)
+    {
+        memcpy(sa_hash[i], addr->uc, MAC_LEN);
+        sa_hash[i][MAC_LEN - 1] = BYTE_B2R(sa_hash[i][MAC_LEN - 1], i);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    memcpy(addr->uc, sa_hash[0], MAC_LEN);
+    return SW_OK;
+}
+
+#if 0
+static sw_error_t
+_isisc_trunk_hash_mode_sw_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    a_uint32_t reg, data = 0;
+
+    reg = isisc_trunk_regs[ISISC_TRUNK_HASH_EN];
+
+    *hash_mode = 0;
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DA_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_DA;
+    }
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SA_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_SA;
+    }
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DIP_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_DIP;
+    }
+
+    SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SIP_EN, data, reg);
+    if (data)
+    {
+        *hash_mode |= FAL_TRUNK_HASH_KEY_SIP;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_trunk_id_member_get(a_uint32_t dev_id, a_uint8_t expect_dp,
+                           a_uint32_t * trunk_id, fal_pbmp_t * member)
+{
+    sw_error_t rv;
+    a_bool_t   enable;
+    a_uint32_t i;
+
+    for (i = 0; i <= ISISC_MAX_TRUNK_ID; i++)
+    {
+        rv = _isisc_trunk_group_sw_get(dev_id, i, &enable, member);
+        SW_RTN_ON_ERROR(rv);
+        if (enable && (*member & expect_dp))
+        {
+            *trunk_id = i;
+            return SW_OK;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isisc_trunk_hash_dp_get(a_uint32_t dev_id, a_uint8_t * header, a_uint32_t len,
+                         a_uint32_t trunk_id, a_uint32_t mode, a_uint8_t * hash_dp)
+{
+#define BIT2_MASK 0x03
+#define TRUNK_MEM_EN_MASK 0x8
+#define TRUNK_MEM_PT_MASK 0x7
+#define TRUNK_HASH_DP_SEL   4
+    sw_error_t rv;
+    a_uint32_t i, hash_mode, reg, data1 = 0;
+    a_uint32_t da_xor = 0, sa_xor = 0; /*consider da-hash & sa-hash (TBD: dip-hash & sip-hash)*/
+    a_uint8_t  xor_dp = 0;
+
+    rv = _isisc_trunk_hash_mode_sw_get(dev_id, &hash_mode);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!hash_mode)
+    {
+        return SW_DISABLE;
+    }
+
+    *hash_dp = 0;
+
+    if ((mode & FAL_TRUNK_HASH_KEY_DA) && (hash_mode & FAL_TRUNK_HASH_KEY_DA))
+    {
+        for (i = 0; i < MAC_LEN; i++)
+        {
+            da_xor ^= (header[i] & BIT2_MASK) ^
+                      ((header[i] >> 2) & BIT2_MASK) ^
+                      ((header[i] >> 4) & BIT2_MASK) ^
+                      ((header[i] >> 6) & BIT2_MASK);
+        }
+        *hash_dp = da_xor;
+    }
+    if ((mode & FAL_TRUNK_HASH_KEY_SA) && (hash_mode & FAL_TRUNK_HASH_KEY_SA))
+    {
+        for (i = 6; i < 2 * MAC_LEN; i++)
+        {
+            sa_xor ^= (header[i] & BIT2_MASK) ^
+                      ((header[i] >> 2) & BIT2_MASK) ^
+                      ((header[i] >> 4) & BIT2_MASK) ^
+                      ((header[i] >> 6) & BIT2_MASK);
+        }
+        *hash_dp = (*hash_dp) ^ sa_xor;
+    }
+
+    /*dp translation*/
+#if 0
+    HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1),
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+#else /*sw*/
+    reg = isisc_trunk_regs[ISISC_TRUNK_CTRL_1 + (trunk_id >> 1)];
+#endif
+
+    for (i = 0; i < TRUNK_HASH_DP_SEL; i++)
+    {
+        xor_dp = BYTE_B2R(*hash_dp, i);
+        data1 = (0x0f & (reg >> (((trunk_id % 2) << 4) + (xor_dp << 2))));
+        if (data1 & TRUNK_MEM_EN_MASK)
+        {
+            *hash_dp = data1 & TRUNK_MEM_PT_MASK;
+            *hash_dp = 0x01 << (*hash_dp); /*bmp*/
+            return SW_OK;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isisc_trunk_sa_spoofing( a_uint32_t dev_id, a_uint8_t * header, a_uint32_t len,
+                          a_uint8_t expect_dp, a_uint32_t trunk_id, fal_pbmp_t member)
+{
+    sw_error_t rv;
+    a_uint32_t i, hash_mode;
+    a_uint8_t  hash_dp;
+    a_uint8_t  ori_sa[MAC_LEN];
+
+    rv = _isisc_trunk_hash_mode_sw_get(dev_id, &hash_mode);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!(hash_mode & FAL_TRUNK_HASH_KEY_SA))
+    {
+        return SW_DISABLE;
+    }
+
+    memcpy(ori_sa, &header[MAC_LEN], MAC_LEN);
+
+    for (i = 0; i < HASH_SIZE/*not HASH_SIZE, for RAD only*/; i++)
+    {
+        memcpy(&header[MAC_LEN], sa_hash[i], MAC_LEN);
+        rv = _isisc_trunk_hash_dp_get(dev_id, header, len, trunk_id,
+                                      FAL_TRUNK_HASH_KEY_DA | FAL_TRUNK_HASH_KEY_SA, &hash_dp);
+        SW_RTN_ON_ERROR(rv);
+        if (expect_dp == hash_dp)
+        {
+            // printk("expect_dp = 0x%x, hash_dp(DA+SA) = 0x%x, sa_id = %d\n", expect_dp, hash_dp, i);
+            return SW_OK;
+        }
+    }
+
+    /*should never here*/
+    memcpy(&header[MAC_LEN], ori_sa, MAC_LEN);
+    return SW_FAIL;
+}
+
+static sw_error_t
+_isisc_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header,
+                           a_uint32_t len, fal_pbmp_t dp_member)
+{
+    sw_error_t rv;
+    a_uint8_t  expect_dp, hash_dp; /*bitmap*/
+    a_uint32_t i, trunk_id;
+    fal_pbmp_t member;
+
+    if (!ISISC_TRUNK_MANIPULATE_DP_ON)
+    {
+        return SW_OK; /*feature not enabled*/
+    }
+
+    if (!header || len < ISISC_TRUNK_MANIPULATE_HEADER_LEN)
+    {
+        return SW_BAD_VALUE;
+    }
+
+#if 0 /*de-comment this to ignore broadcast packets*/
+    const a_uint8_t  bc_mac[MAC_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+    if (!memcmp(header, bc_mac, MAC_LEN))   /*not for broadcast*/
+    {
+        return SW_OK;
+    }
+#endif
+
+    /*expect_dp within trunk group*/
+    expect_dp = dp_member & 0x7f;
+    for (i = 0; i < 7; i++)
+    {
+        if (expect_dp & (0x01 << i))
+        {
+            rv = _isisc_trunk_id_member_get(dev_id, (0x01 << i), &trunk_id, &member);
+            if (rv != SW_OK)
+            {
+                expect_dp &= ~(0x01 << i); /*not the dp doesn't belong to trunk*/
+            }
+        }
+    }
+
+    if (BYTE_B1C(expect_dp) != 1)   /*supports 1 dp only*/
+    {
+        return SW_OK; /*ignore none-dp or multi-dp*/
+    }
+
+    rv = _isisc_trunk_id_member_get(dev_id, expect_dp, &trunk_id, &member);
+    SW_RTN_ON_ERROR(rv);
+
+    member &= 0x7f;
+    if (BYTE_B1C(member) == 1)   /*trunk group w/ one port*/
+    {
+        return SW_OK;
+    }
+
+    rv = _isisc_trunk_hash_dp_get(dev_id, header, len, trunk_id,
+                                  FAL_TRUNK_HASH_KEY_DA | FAL_TRUNK_HASH_KEY_SA, &hash_dp);
+    SW_RTN_ON_ERROR(rv);
+
+    // printk("expect_dp = 0x%x, hash_dp(DA+SA) = 0x%x, member = 0x%x\n", expect_dp, hash_dp, member);
+    if (expect_dp == hash_dp)
+    {
+        return SW_OK;
+    }
+
+    rv = _isisc_trunk_sa_spoofing(dev_id, header, len, expect_dp, trunk_id, member);
+    SW_RTN_ON_ERROR(rv);
+
+    return rv;
+}
+#endif
+
+/**
+ * @brief Set particular trunk group information on particular device.
+ * @param[in] dev_id device id
+ * @param[in] trunk_id trunk group id
+ * @param[in] enable trunk group status, enable or disable
+ * @param[in] member port member information
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+                     a_bool_t enable, fal_pbmp_t member)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_trunk_group_set(dev_id, trunk_id, enable, member);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get particular trunk group information on particular device.
+ * @param[in] dev_id device id
+ * @param[in] trunk_id trunk group id
+ * @param[out] enable trunk group status, enable or disable
+ * @param[out] member port member information
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+                     a_bool_t * enable, fal_pbmp_t * member)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_trunk_group_get(dev_id, trunk_id, enable, member);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set trunk hash mode on particular device.
+ * @details   Comments:
+    hash mode is listed below
+    FAL_TRUNK_HASH_KEY_DA, FAL_TRUNK_HASH_KEY_SA, FAL_TRUNK_HASH_KEY_DIP and FAL_TRUNK_HASH_KEY_SIP
+ * @param[in] dev_id device id
+ * @param[in] hash_mode trunk hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_trunk_hash_mode_set(dev_id, hash_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get trunk hash mode on particular device.
+ * @param[in] dev_id device id
+ * @param[out] hash_mode trunk hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_trunk_hash_mode_get(dev_id, hash_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set trunk manipulate SA on particular device.
+ * @param[in] dev_id device id
+ * @param[in] addr   manipulate SA
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_trunk_manipulate_sa_set(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get trunk manipulate SA on particular device.
+ * @param[in]  dev_id device id
+ * @param[out] addr   manipulate SA
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_trunk_manipulate_sa_get(dev_id, addr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#if 0
+/**
+ * @brief manipulate destination port within a trunk group
+ * @details Comments:
+ *  supporting hash mode include: FAL_TRUNK_HASH_KEY_DA & FAL_TRUNK_HASH_KEY_SA;
+ *  FAL_TRUNK_HASH_KEY_DIP & FAL_TRUNK_HASH_KEY_SIP are NOT covered in current design
+ * @param[in]     dev_id    device id
+ * @param[in-out] header    packet header, accept format: [DA:6B][SA:6B]
+ * @param[in]     len       length of packet header, should be 12 in current design (6B DA + 6B SA)
+ * @param[in]     dp_member expect destination port members, bitmap format
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header,
+                          a_uint32_t len, fal_pbmp_t dp_member)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_trunk_manipulate_dp(dev_id, header, len, dp_member);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+sw_error_t
+isisc_trunk_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->trunk_group_set = isisc_trunk_group_set;
+        p_api->trunk_group_get = isisc_trunk_group_get;
+        p_api->trunk_hash_mode_set = isisc_trunk_hash_mode_set;
+        p_api->trunk_hash_mode_get = isisc_trunk_hash_mode_get;
+        p_api->trunk_manipulate_sa_set = isisc_trunk_manipulate_sa_set;
+        p_api->trunk_manipulate_sa_get = isisc_trunk_manipulate_sa_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/isisc/isisc_vlan.c b/qca-ssdk/src/hsl/isisc/isisc_vlan.c
new file mode 100755
index 0000000..1d61317
--- /dev/null
+++ b/qca-ssdk/src/hsl/isisc/isisc_vlan.c
@@ -0,0 +1,906 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup isisc_vlan ISISC_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_vlan.h"
+#include "isisc_reg.h"
+
+#define MAX_VLAN_ID         4095
+
+#define VLAN_FLUSH          1
+#define VLAN_LOAD_ENTRY     2
+#define VLAN_PURGE_ENTRY    3
+#define VLAN_REMOVE_PORT    4
+#define VLAN_NEXT_ENTRY     5
+#define VLAN_FIND_ENTRY     6
+
+static void
+_isisc_vlan_hw_to_sw(a_uint32_t reg[], fal_vlan_t * vlan_entry)
+{
+    a_uint32_t i, data, tmp;
+
+    aos_mem_zero(vlan_entry, sizeof (fal_vlan_t));
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VLAN_ID, data, reg[1]);
+    vlan_entry->vid = data & 0xfff;
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]);
+    if (1 == data)
+    {
+        vlan_entry->fid = vlan_entry->vid;
+    }
+    else
+    {
+        vlan_entry->fid = FAL_SVL_FID;
+    }
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]);
+    if (1 == data)
+    {
+        vlan_entry->learn_dis = A_TRUE;
+    }
+    else
+    {
+        vlan_entry->learn_dis = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]);
+    if (1 == data)
+    {
+        vlan_entry->vid_pri_en = A_TRUE;
+
+        SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]);
+        vlan_entry->vid_pri = data & 0xff;
+    }
+    else
+    {
+        vlan_entry->vid_pri_en = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]);
+    for (i = 0; i < 7; i++)
+    {
+        tmp = (data >> (i << 1)) & 0x3UL;
+        if (0 == tmp)
+        {
+            vlan_entry->mem_ports |= (0x1UL << i);
+            vlan_entry->unmodify_ports |= (0x1UL << i);
+        }
+        else if (1 == tmp)
+        {
+            vlan_entry->mem_ports |= (0x1UL << i);
+            vlan_entry->untagged_ports |= (0x1UL << i);
+        }
+        else if (2 == tmp)
+        {
+            vlan_entry->mem_ports |= (0x1UL << i);
+            vlan_entry->tagged_ports |= (0x1UL << i);
+        }
+    }
+
+    return;
+}
+
+static sw_error_t
+_isisc_vlan_sw_to_hw(a_uint32_t dev_id, const fal_vlan_t * vlan_entry,
+                    a_uint32_t reg[])
+{
+    a_uint32_t i, tag, untag, unmodify, member = 0;
+
+    if (vlan_entry->vid > MAX_VLAN_ID)
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    if (A_FALSE ==
+            hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]);
+
+    if (FAL_SVL_FID == vlan_entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]);
+    }
+    else if (vlan_entry->vid == vlan_entry->fid)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]);
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (A_TRUE == vlan_entry->learn_dis)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]);
+    }
+
+    for (i = 0; i < 7; i++)
+    {
+        if ((vlan_entry->mem_ports >> i) & 0x1UL)
+        {
+            tag = (vlan_entry->tagged_ports >> i) & 0x1UL;
+            untag = (vlan_entry->untagged_ports >> i) & 0x1UL;
+            unmodify = (vlan_entry->unmodify_ports >> i) & 0x1UL;
+
+            if ((0 == (tag + untag + unmodify))
+                    || (1 < (tag + untag + unmodify)))
+            {
+                return SW_BAD_VALUE;
+            }
+
+            if (tag)
+            {
+                member |= (2 << (i << 1));
+            }
+            else if (untag)
+            {
+                member |= (1 << (i << 1));
+            }
+        }
+        else
+        {
+            member |= (3 << (i << 1));
+        }
+    }
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, member, reg[0]);
+
+    if (A_TRUE == vlan_entry->vid_pri_en)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]);
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri,
+                            reg[0]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]);
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_entry->vid, reg[1]);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_vlan_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_vlan_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_isisc_vlan_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val;
+    sw_error_t rv;
+
+    while (vt_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY,
+                          (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_BUSY;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_FUNC, op, val);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_BUSY, 1, val);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    vt_busy = 1;
+    i = 0x1000;
+    while (vt_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY,
+                          (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_FAIL;
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_FULL_VIO,
+                      (a_uint8_t *) (&vt_full), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (vt_full)
+    {
+        val = 0x10;
+        HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        if (VLAN_LOAD_ENTRY == op)
+        {
+            return SW_FULL;
+        }
+        else if (VLAN_PURGE_ENTRY == op)
+        {
+            return SW_NOT_FOUND;
+        }
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_VALID,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (!val)
+    {
+        if (VLAN_FIND_ENTRY == op)
+            return SW_NOT_FOUND;
+
+        if (VLAN_NEXT_ENTRY == op)
+            return SW_NO_MORE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_vlan_hwentry_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t reg[])
+{
+    sw_error_t rv;
+
+    if (vlan_id > MAX_VLAN_ID)
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_vlan_up_to_sw(dev_id, reg);
+    return rv;
+}
+
+static sw_error_t
+_isisc_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_vlan_sw_to_hw(dev_id, vlan_entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_vlan_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_isisc_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (vlan_id > MAX_VLAN_ID)
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, 0x3fff, reg[0]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]);
+
+    rv = _isisc_vlan_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_isisc_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_NEXT_ENTRY_FIRST_ID == vlan_id)
+    {
+        rv = _isisc_vlan_hwentry_get(dev_id, 0, reg);
+
+        if (SW_OK == rv)
+        {
+            _isisc_vlan_hw_to_sw(reg, p_vlan);
+            return SW_OK;
+        }
+        else
+        {
+            vlan_id = 0;
+        }
+    }
+
+    if (vlan_id > MAX_VLAN_ID)
+        return SW_OUT_OF_RANGE;
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_vlan_commit(dev_id, VLAN_NEXT_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_vlan_up_to_sw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    _isisc_vlan_hw_to_sw(reg, p_vlan);
+
+    if (0 == p_vlan->vid)
+    {
+        return SW_NO_MORE;
+    }
+    else
+    {
+        return SW_OK;
+    }
+}
+
+static sw_error_t
+_isisc_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    _isisc_vlan_hw_to_sw(reg, p_vlan);
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (vlan_id > MAX_VLAN_ID)
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    reg = (a_int32_t) vlan_id;
+    HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VLAN_ID,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_vlan_commit(dev_id, VLAN_PURGE_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_isisc_vlan_flush(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_vlan_commit(dev_id, VLAN_FLUSH);
+    return rv;
+}
+
+static sw_error_t
+_isisc_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((MAX_VLAN_ID < fid) && (FAL_SVL_FID != fid))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((MAX_VLAN_ID >= fid) && (vlan_id != fid))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_SVL_FID == fid)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]);
+    }
+
+    rv = _isisc_vlan_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    if (SW_FULL == rv)
+    {
+        rv = SW_OK;
+    }
+    return rv;
+}
+
+static sw_error_t
+_isisc_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]);
+    if (data)
+    {
+        *fid = vlan_id;
+    }
+    else
+    {
+        *fid = FAL_SVL_FID;
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+_isisc_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                         fal_port_t port_id, a_uint32_t port_info)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]);
+    data &= (~(0x3 << (port_id << 1)));
+    data |= ((port_info & 0x3) << (port_id << 1));
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]);
+
+    rv = _isisc_vlan_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    if (SW_FULL == rv)
+    {
+        rv = SW_OK;
+    }
+    return rv;
+}
+
+static sw_error_t
+_isisc_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+                      fal_port_t port_id, fal_pt_1q_egmode_t port_info)
+{
+    sw_error_t rv;
+    a_uint32_t info = 0;
+
+    if (FAL_EG_UNMODIFIED == port_info)
+    {
+        info = 0;
+    }
+    else if (FAL_EG_TAGGED == port_info)
+    {
+        info = 0x2;
+    }
+    else if (FAL_EG_UNTAGGED == port_info)
+    {
+        info = 0x1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isisc_vlan_member_update(dev_id, vlan_id, port_id, info);
+    return rv;
+}
+
+static sw_error_t
+_isisc_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t info = 0x3;
+
+    rv = _isisc_vlan_member_update(dev_id, vlan_id, port_id, info);
+    return rv;
+}
+
+static sw_error_t
+_isisc_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = _isisc_vlan_down_to_hw(dev_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _isisc_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    if (SW_FULL == rv)
+    {
+        rv = SW_OK;
+    }
+    return rv;
+}
+
+static sw_error_t
+_isisc_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t data, reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]);
+    if (data)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+    return SW_OK;
+}
+
+/**
+ * @brief Append a vlan entry on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_entry vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_vlan_entry_append(dev_id, vlan_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Creat a vlan entry through vlan id on a paticular device.
+ *   @details   Comments:
+ *    After this operation the member ports of the created vlan entry are null.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_vlan_create(dev_id, vlan_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next a vlan entry through vlan id on a paticular device.
+ *   @details   Comments:
+ *    If the value of vid is zero this operation will get the first entry.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_vlan_next(dev_id, vlan_id, p_vlan);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a vlan entry through vlan id on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_vlan_find(dev_id, vlan_id, p_vlan);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a vlan entry through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_vlan_delete(dev_id, vlan_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Flush all vlan entries on a paticular device.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_flush(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_vlan_flush(dev_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] fid FDB id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_vlan_fid_set(dev_id, vlan_id, fid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] fid FDB id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_vlan_fid_get(dev_id, vlan_id, fid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a port member to a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @param[in] port_info port tag information
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+                     fal_port_t port_id, fal_pt_1q_egmode_t port_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_vlan_member_add(dev_id, vlan_id, port_id, port_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Del a port member from a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_vlan_member_del(dev_id, vlan_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_vlan_learning_state_set(dev_id, vlan_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _isisc_vlan_learning_state_get(dev_id, vlan_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+isisc_vlan_init(a_uint32_t dev_id)
+{
+    hsl_api_t *p_api;
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->vlan_entry_append = isisc_vlan_entry_append;
+    p_api->vlan_creat = isisc_vlan_create;
+    p_api->vlan_delete = isisc_vlan_delete;
+    p_api->vlan_next = isisc_vlan_next;
+    p_api->vlan_find = isisc_vlan_find;
+    p_api->vlan_flush = isisc_vlan_flush;
+    p_api->vlan_fid_set = isisc_vlan_fid_set;
+    p_api->vlan_fid_get = isisc_vlan_fid_get;
+    p_api->vlan_member_add = isisc_vlan_member_add;
+    p_api->vlan_member_del = isisc_vlan_member_del;
+    p_api->vlan_learning_state_set = isisc_vlan_learning_state_set;
+    p_api->vlan_learning_state_get = isisc_vlan_learning_state_get;
+
+
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/mp/Makefile b/qca-ssdk/src/hsl/mp/Makefile
new file mode 100755
index 0000000..cfa8234
--- /dev/null
+++ b/qca-ssdk/src/hsl/mp/Makefile
@@ -0,0 +1,26 @@
+LOC_DIR=src/hsl/mp
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+ifeq (TRUE, $(IN_MIB))
+    SRC_LIST+=mp_mib.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+	SRC_LIST+=mp_portctrl.c
+endif
+
+ifeq (TRUE, $(IN_UNIPHY))
+	SRC_LIST+=mp_uniphy.c
+endif
+
+ifeq (, $(filter MP, $(SUPPORT_CHIP)))
+  SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/hsl/mp/mp_mib.c b/qca-ssdk/src/hsl/mp/mp_mib.c
new file mode 100755
index 0000000..e3188a1
--- /dev/null
+++ b/qca-ssdk/src/hsl/mp/mp_mib.c
@@ -0,0 +1,816 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "scomphy_reg_access.h"
+#include "mp_mib_reg.h"
+#include "mp_mib.h"
+
+sw_error_t
+mp_mmc_control_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_control_u *value)
+{
+	if (index >= MMC_CONTROL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				MMC_CONTROL_ADDRESS + \
+				index * MMC_CONTROL_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_mmc_control_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union mmc_control_u *value)
+{
+	if (index >= MMC_CONTROL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_set(
+				dev_id,
+				MMC_CONTROL_ADDRESS + \
+				index * MMC_CONTROL_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_octet_count_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_bad_u *value)
+{
+	if (index >= TX_OCTET_COUNT_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_OCTET_COUNT_GOOD_BAD_ADDRESS + \
+				index * TX_OCTET_COUNT_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_frame_count_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_bad_u *value)
+{
+	if (index >= TX_FRAME_COUNT_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_FRAME_COUNT_GOOD_BAD_ADDRESS + \
+				index * TX_FRAME_COUNT_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_broadcast_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_u *value)
+{
+	if (index >= TX_BROADCAST_FRAMES_GOOD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_BROADCAST_FRAMES_GOOD_ADDRESS + \
+				index * TX_BROADCAST_FRAMES_GOOD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_multicast_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_u *value)
+{
+	if (index >= TX_MULTICAST_FRAMES_GOOD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_MULTICAST_FRAMES_GOOD_ADDRESS + \
+				index * TX_MULTICAST_FRAMES_GOOD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_64octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_64octets_frames_good_bad_u *value)
+{
+	if (index >= TX_64OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_64OCTETS_FRAMES_GOOD_BAD_ADDRESS + \
+				index * TX_64OCTETS_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_65to127octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_65to127octets_frames_good_bad_u *value)
+{
+	if (index >= TX_65TO127OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_65TO127OCTETS_FRAMES_GOOD_BAD_ADDRESS + \
+				index * TX_65TO127OCTETS_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_128to255octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_128to255octets_frames_good_bad_u *value)
+{
+	if (index >= TX_128TO255OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_128TO255OCTETS_FRAMES_GOOD_BAD_ADDRESS + \
+				index * TX_128TO255OCTETS_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_256to511octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_256to511octets_frames_good_bad_u *value)
+{
+	if (index >= TX_256TO511OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_256TO511OCTETS_FRAMES_GOOD_BAD_ADDRESS + \
+				index * TX_256TO511OCTETS_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_512to1023octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_512to1023octets_frames_good_bad_u *value)
+{
+	if (index >= TX_512TO1023OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_512TO1023OCTETS_FRAMES_GOOD_BAD_ADDRESS + \
+				index * TX_512TO1023OCTETS_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_1024tomaxoctets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_1024tomaxoctets_frames_good_bad_u *value)
+{
+	if (index >= TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_ADDRESS + \
+				index * TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_unicast_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_unicast_frames_good_bad_u *value)
+{
+	if (index >= TX_UNICAST_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_UNICAST_FRAMES_GOOD_BAD_ADDRESS + \
+				index * TX_UNICAST_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_multicast_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multicast_frames_good_bad_u *value)
+{
+	if (index >= TX_MULTICAST_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_MULTICAST_FRAMES_GOOD_BAD_ADDRESS + \
+				index * TX_MULTICAST_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_broadcast_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_broadcast_frames_good_bad_u *value)
+{
+	if (index >= TX_BROADCAST_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_BROADCAST_FRAMES_GOOD_BAD_ADDRESS + \
+				index * TX_BROADCAST_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_underflow_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_underflow_error_frames_u *value)
+{
+	if (index >= TX_UNDERFERROR_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_UNDERFLOW_ERROR_FRAMES_ADDRESS + \
+				index * TX_UNDERFLOW_ERROR_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_single_col_good_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_single_collision_good_frames_u *value)
+{
+	if (index >= TX_SINGLE_COLLISION_GOOD_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_SINGLE_COLLISION_GOOD_FRAMES_ADDRESS + \
+				index * TX_SINGLE_COLLISION_GOOD_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_t_multi_col_good_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_multiple_collision_good_frames_u *value)
+{
+	if (index >= TX_MULTIPLE_COLLISION_GOOD_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_MULTIPLE_COLLISION_GOOD_FRAMES_ADDRESS + \
+				index * TX_MULTIPLE_COLLISION_GOOD_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_defer_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_deferred_frames_u *value)
+{
+	if (index >= TX_DEFERRED_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_DEFERRED_FRAMES_ADDRESS + \
+				index * TX_DEFERRED_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_late_col_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_late_collision_frames_u *value)
+{
+	if (index >= TX_LATE_COLLISION_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_LATE_COLLISION_FRAMES_ADDRESS + \
+				index * TX_LATE_COLLISION_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_excessive_col_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_excessive_collision_frames_u *value)
+{
+	if (index >= TX_EXCESSIVE_COLLISION_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_EXCESSIVE_COLLISION_FRAMES_ADDRESS + \
+				index * TX_EXCESSIVE_COLLISION_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_carrier_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_carrier_error_frames_u *value)
+{
+	if (index >= TX_CARRIER_ERROR_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_CARRIER_ERROR_FRAMES_ADDRESS + \
+				index * TX_CARRIER_ERROR_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_octet_count_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_octet_count_good_u *value)
+{
+	if (index >= TX_OCTET_COUNT_GOOD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_OCTET_COUNT_GOOD_ADDRESS + \
+				index * TX_OCTET_COUNT_GOOD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_frame_count_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_frame_count_good_u *value)
+{
+	if (index >= TX_FRAME_COUNT_GOOD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_FRAME_COUNT_GOOD_ADDRESS + \
+				index * TX_FRAME_COUNT_GOOD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_pause_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_pause_frames_u *value)
+{
+	if (index >= TX_PAUSE_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_PAUSE_FRAMES_ADDRESS + \
+				index * TX_PAUSE_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_vlan_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_vlan_frames_good_u *value)
+{
+	if (index >= TX_VLAN_FRAMES_GOOD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_VLAN_FRAMES_GOOD_ADDRESS + \
+				index * TX_VLAN_FRAMES_GOOD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_tx_osize_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union tx_osize_frames_good_u *value)
+{
+	if (index >= TX_OSIZE_FRAMES_GOOD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				TX_OSIZE_FRAMES_GOOD_ADDRESS + \
+				index * TX_OSIZE_FRAMES_GOOD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_frame_count_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_frame_count_good_bad_u *value)
+{
+	if (index >= RX_FRAME_COUNT_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_FRAME_COUNT_GOOD_BAD_ADDRESS + \
+				index * RX_FRAME_COUNT_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_octet_count_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_bad_u *value)
+{
+	if (index >= RX_OCTET_COUNT_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_OCTET_COUNT_GOOD_BAD_ADDRESS + \
+				index * RX_OCTET_COUNT_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_octet_count_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_octet_count_good_u *value)
+{
+	if (index >= RX_OCTET_COUNT_GOOD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_OCTET_COUNT_GOOD_ADDRESS + \
+				index * RX_OCTET_COUNT_GOOD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_broadcast_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_broadcast_frames_good_u *value)
+{
+	if (index >= RX_BROADCAST_FRAMES_GOOD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_BROADCAST_FRAMES_GOOD_ADDRESS + \
+				index * RX_BROADCAST_FRAMES_GOOD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_multicast_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_multicast_frames_good_u *value)
+{
+	if (index >= RX_MULTICAST_FRAMES_GOOD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_MULTICAST_FRAMES_GOOD_ADDRESS + \
+				index * RX_MULTICAST_FRAMES_GOOD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_crc_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_crc_error_frames_u *value)
+{
+	if (index >= RX_CRC_ERROR_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_CRC_ERROR_FRAMES_ADDRESS + \
+				index * RX_CRC_ERROR_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_alignment_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_crc_error_frames_u *value)
+{
+	if (index >= RX_ALIGNMENT_ERROR_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_ALIGNMENT_ERROR_FRAMES_ADDRESS + \
+				index * RX_ALIGNMENT_ERROR_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_runt_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_runt_error_frames_u *value)
+{
+	if (index >= RX_RUNT_ERROR_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_RUNT_ERROR_FRAMES_ADDRESS + \
+				index * RX_RUNT_ERROR_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_jabber_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_jabber_error_frames_u *value)
+{
+	if (index >= RX_JABBER_ERROR_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_JABBER_ERROR_FRAMES_ADDRESS + \
+				index * RX_JABBER_ERROR_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_undersize_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_undersize_frames_good_u *value)
+{
+	if (index >= RX_UNDERSIZE_FRAMES_GOOD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_UNDERSIZE_FRAMES_GOOD_ADDRESS + \
+				index * RX_UNDERSIZE_FRAMES_GOOD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_oversize_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_oversize_frames_good_u *value)
+{
+	if (index >= RX_OVERSIZE_FRAMES_GOOD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_OVERSIZE_FRAMES_GOOD_ADDRESS + \
+				index * RX_OVERSIZE_FRAMES_GOOD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_64octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_64octets_frames_good_bad_u *value)
+{
+	if (index >= RX_64OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_64OCTETS_FRAMES_GOOD_BAD_ADDRESS + \
+				index * RX_64OCTETS_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_65to127octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_65to127octets_frames_good_bad_u *value)
+{
+	if (index >= RX_65TO127OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_65TO127OCTETS_FRAMES_GOOD_BAD_ADDRESS + \
+				index * RX_65TO127OCTETS_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_128to255octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_128to255octets_frames_good_bad_u *value)
+{
+	if (index >= RX_128TO255OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_128TO255OCTETS_FRAMES_GOOD_BAD_ADDRESS + \
+				index * RX_128TO255OCTETS_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_256to511octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_256to511octets_frames_good_bad_u *value)
+{
+	if (index >= RX_256TO511OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_256TO511OCTETS_FRAMES_GOOD_BAD_ADDRESS + \
+				index * RX_256TO511OCTETS_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_512to1023octets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_512to1023octets_frames_good_bad_u *value)
+{
+	if (index >= RX_512TO1023OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_512TO1023OCTETS_FRAMES_GOOD_BAD_ADDRESS + \
+				index * RX_512TO1023OCTETS_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_1024tomaxoctets_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_1024tomaxoctets_frames_good_bad_u *value)
+{
+	if (index >= RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_ADDRESS + \
+				index * RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_unicast_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_unicast_frames_good_u *value)
+{
+	if (index >= RX_UNICAST_FRAMES_GOOD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_UNICAST_FRAMES_GOOD_ADDRESS + \
+				index * RX_UNICAST_FRAMES_GOOD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_length_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_length_error_frames_u *value)
+{
+	if (index >= RX_LENGTH_ERROR_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_LENGTH_ERROR_FRAMES_ADDRESS + \
+				index * RX_LENGTH_ERROR_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_outofrange_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_outofrange_frames_u *value)
+{
+	if (index >= RX_OUTOFRANGE_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_OUTOFRANGE_FRAMES_ADDRESS + \
+				index * RX_OUTOFRANGE_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_pause_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_pause_frames_u *value)
+{
+	if (index >= RX_PAUSE_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_PAUSE_FRAMES_ADDRESS + \
+				index * RX_PAUSE_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_fifo_over_flow_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_fifo_over_flow_frames_u *value)
+{
+	if (index >= RX_FIFO_OVER_FLOW_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_FIFOOVERFW_FRAMES_ADDRESS + \
+				index * RX_FIFOOVERFW_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_vlan_frames_good_bad_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_vlan_frames_good_bad_u *value)
+{
+	if (index >= RX_VLAN_FRAMES_GOOD_BAD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_VLAN_FRAMES_GOOD_BAD_ADDRESS + \
+				index * RX_VLAN_FRAMES_GOOD_BAD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_watchdog_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_watchdog_error_frames_u *value)
+{
+	if (index >= RX_WATCHDOG_ERROR_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_WATCHDOG_ERROR_FRAMES_ADDRESS + \
+				index * RX_WATCHDOG_ERROR_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_receive_error_frames_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_receive_error_frames_u *value)
+{
+	if (index >= RX_RECEIVE_ERROR_FRAMES_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_RECEIVE_ERROR_FRAMES_ADDRESS + \
+				index * RX_RECEIVE_ERROR_FRAMES_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_rx_control_frames_good_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union rx_control_frames_good_u *value)
+{
+	if (index >= RX_CONTROL_FRAMES_GOOD_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return scomphy_reg_get(
+				dev_id,
+				RX_CONTROL_FRAMES_GOOD_ADDRESS + \
+				index * RX_CONTROL_FRAMES_GOOD_INC,
+				(a_uint8_t *)&value->val, 4);
+}
diff --git a/qca-ssdk/src/hsl/mp/mp_portctrl.c b/qca-ssdk/src/hsl/mp/mp_portctrl.c
new file mode 100755
index 0000000..e4931ce
--- /dev/null
+++ b/qca-ssdk/src/hsl/mp/mp_portctrl.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "scomphy_reg_access.h"
+#include "mp_portctrl_reg.h"
+#include "mp_portctrl.h"
+
+sw_error_t
+mp_mac_configuration_get(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_configuration_u *value)
+{
+	 if (index >= MAC_CONFIGURATION_MAX_ENTRY)
+		 return SW_OUT_OF_RANGE;
+	 return scomphy_reg_get(
+				dev_id,
+				MAC_CONFIGURATION_ADDRESS + \
+				index * MAC_CONFIGURATION_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_mac_configuration_set(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_configuration_u *value)
+{
+	 if (index >= MAC_CONFIGURATION_MAX_ENTRY)
+		 return SW_OUT_OF_RANGE;
+	 return scomphy_reg_set(
+				dev_id,
+				MAC_CONFIGURATION_ADDRESS + \
+				index * MAC_CONFIGURATION_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_mac_frame_filter_get(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_frame_filter_u *value)
+{
+	 if (index >= MAC_FRAME_FILTER_MAX_ENTRY)
+		 return SW_OUT_OF_RANGE;
+	 return scomphy_reg_get(
+				dev_id,
+				MAC_FRAME_FILTER_ADDRESS + \
+				index * MAC_FRAME_FILTER_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_mac_frame_filter_set(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_frame_filter_u *value)
+{
+	 if (index >= MAC_FRAME_FILTER_MAX_ENTRY)
+		 return SW_OUT_OF_RANGE;
+	 return scomphy_reg_set(
+				dev_id,
+				MAC_FRAME_FILTER_ADDRESS + \
+				index * MAC_FRAME_FILTER_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_mac_flowctrl_get(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_flow_ctrl_u *value)
+{
+	 if (index >= MAC_FLOW_CTRL_MAX_ENTRY)
+		 return SW_OUT_OF_RANGE;
+	 return scomphy_reg_get(
+				dev_id,
+				MAC_FLOW_CTRL_ADDRESS + \
+				index * MAC_FLOW_CTRL_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_mac_flowctrl_set(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_flow_ctrl_u *value)
+{
+	 if (index >= MAC_FLOW_CTRL_MAX_ENTRY)
+		 return SW_OUT_OF_RANGE;
+	 return scomphy_reg_set(
+				dev_id,
+				MAC_FLOW_CTRL_ADDRESS + \
+				index * MAC_FLOW_CTRL_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_mac_lpi_ctrl_status_get(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_lpi_ctrl_status_u *value)
+{
+	 if (index >= MAC_LPI_CTRL_STATUS_MAX_ENTRY)
+		 return SW_OUT_OF_RANGE;
+	 return scomphy_reg_get(
+				dev_id,
+				MAC_LPI_CTRL_STATUS_ADDRESS + \
+				index * MAC_LPI_CTRL_STATUS_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_mac_lpi_ctrl_status_set(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_lpi_ctrl_status_u *value)
+{
+	 if (index >= MAC_LPI_CTRL_STATUS_MAX_ENTRY)
+		 return SW_OUT_OF_RANGE;
+	 return scomphy_reg_set(
+				dev_id,
+				MAC_LPI_CTRL_STATUS_ADDRESS + \
+				index * MAC_LPI_CTRL_STATUS_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_mac_lpi_timer_ctrl_get(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_lpi_timer_ctrl_u *value)
+{
+	 if (index >= MAC_LPI_TIMER_CTRL_MAX_ENTRY)
+		 return SW_OUT_OF_RANGE;
+	 return scomphy_reg_get(
+				dev_id,
+				MAC_LPI_TIMER_CTRL_ADDRESS + \
+				index * MAC_LPI_TIMER_CTRL_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_mac_lpi_timer_ctrl_set(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_lpi_timer_ctrl_u *value)
+{
+	 if (index >= MAC_LPI_TIMER_CTRL_MAX_ENTRY)
+		 return SW_OUT_OF_RANGE;
+	 return scomphy_reg_set(
+				dev_id,
+				MAC_LPI_TIMER_CTRL_ADDRESS + \
+				index * MAC_LPI_TIMER_CTRL_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_mac_max_frame_ctrl_get(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_max_frame_ctrl_u *value)
+{
+	 if (index >= MAC_MAX_FRAME_CTRL_MAX_ENTRY)
+		 return SW_OUT_OF_RANGE;
+	 return scomphy_reg_get(
+				dev_id,
+				MAC_MAX_FRAME_CTRL_ADDRESS + \
+				index * MAC_MAX_FRAME_CTRL_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_mac_max_frame_ctrl_set(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_max_frame_ctrl_u *value)
+{
+	 if (index >= MAC_MAX_FRAME_CTRL_MAX_ENTRY)
+		 return SW_OUT_OF_RANGE;
+	 return scomphy_reg_set(
+				dev_id,
+				MAC_MAX_FRAME_CTRL_ADDRESS + \
+				index * MAC_MAX_FRAME_CTRL_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_mac_operation_mode_ctrl_get(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_operation_mode_ctrl_u *value)
+{
+	 if (index >= MAC_OPERATION_MODE_CTRL_MAX_ENTRY)
+		 return SW_OUT_OF_RANGE;
+	 return scomphy_reg_get(
+				dev_id,
+				MAC_OPERATION_MODE_CTRL_ADDRESS + \
+				index * MAC_OPERATION_MODE_CTRL_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
+sw_error_t
+mp_mac_operation_mode_ctrl_set(
+		 a_uint32_t dev_id,
+		 a_uint32_t index,
+		 union mac_operation_mode_ctrl_u *value)
+{
+	 if (index >= MAC_OPERATION_MODE_CTRL_MAX_ENTRY)
+		 return SW_OUT_OF_RANGE;
+	 return scomphy_reg_set(
+				dev_id,
+				MAC_OPERATION_MODE_CTRL_ADDRESS + \
+				index * MAC_OPERATION_MODE_CTRL_INC,
+				(a_uint8_t *)&value->val, 4);
+}
+
diff --git a/qca-ssdk/src/hsl/mp/mp_uniphy.c b/qca-ssdk/src/hsl/mp/mp_uniphy.c
new file mode 100755
index 0000000..5d49a7e
--- /dev/null
+++ b/qca-ssdk/src/hsl/mp/mp_uniphy.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/**
+ * @defgroup
+ * @{
+ */
+
+#include "sw.h"
+#include "hppe_reg_access.h"
+#include "mp_uniphy_reg.h"
+#include "mp_uniphy.h"
+
+sw_error_t
+mp_uniphy_clock_output_control_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_clock_output_control_u *value)
+{
+	if (index >= UNIPHY_CLOCK_OUTPUT_CONTROL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_get(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_CLOCK_OUTPUT_CONTROL_ADDRESS,
+				index * UNIPHY_CLOCK_OUTPUT_CONTROL_INC,
+				&value->val);
+}
+
+sw_error_t
+mp_uniphy_clock_output_control_set(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union uniphy_clock_output_control_u *value)
+{
+	if (index >= UNIPHY_CLOCK_OUTPUT_CONTROL_MAX_ENTRY)
+		return SW_OUT_OF_RANGE;
+	return hppe_uniphy_reg_set(
+				dev_id,
+				NSS_UNIPHY_BASE_ADDR + UNIPHY_CLOCK_OUTPUT_CONTROL_ADDRESS,
+				index * UNIPHY_CLOCK_OUTPUT_CONTROL_INC,
+				value->val);
+}
diff --git a/qca-ssdk/src/hsl/phy/Makefile b/qca-ssdk/src/hsl/phy/Makefile
new file mode 100644
index 0000000..51d6d0b
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/Makefile
@@ -0,0 +1,96 @@
+LOC_DIR=src/hsl/phy
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+ifeq (ATHENA, $(CHIP_TYPE))
+  SRC_LIST = f2_phy.c
+endif
+
+ifeq (GARUDA, $(CHIP_TYPE))
+  SRC_LIST = f1_phy.c
+endif
+
+ifeq (SHIVA, $(CHIP_TYPE))
+  SRC_LIST = f2_phy.c
+endif
+
+ifeq (HORUS, $(CHIP_TYPE))
+  SRC_LIST = f2_phy.c
+endif
+
+ifeq (ISIS, $(CHIP_TYPE))
+  SRC_LIST = f1_phy.c
+endif
+
+ifeq (MP, $(CHIP_TYPE))
+  SRC_LIST = mpge_phy.c
+ifeq (TRUE, $(IN_LED))
+  SRC_LIST += mpge_led.c
+endif
+endif
+
+ifneq (,$(filter ISISC, $(SUPPORT_CHIP)))
+  SRC_LIST += f1_phy.c
+endif
+
+ifeq (TRUE, $(IN_MALIBU_PHY))
+  SRC_LIST += malibu_phy.c
+endif
+
+ifeq (ALL_CHIP, $(CHIP_TYPE))
+     SRC_LIST = f1_phy.c f2_phy.c malibu_phy.c
+ifneq (,$(filter MP, $(SUPPORT_CHIP)))
+     SRC_LIST += mpge_phy.c
+ifeq (TRUE, $(IN_LED))
+     SRC_LIST += mpge_led.c
+endif
+endif
+endif
+
+ifeq (NONHK_CHIP, $(CHIP_TYPE))
+     SRC_LIST = f1_phy.c f2_phy.c malibu_phy.c
+endif
+
+ifeq (TRUE, $(IN_AQUANTIA_PHY))
+    SRC_LIST += aquantia_phy.c
+endif
+
+ifeq (TRUE, $(IN_QCA803X_PHY))
+    SRC_LIST += qca803x_phy.c
+endif
+
+ifeq (TRUE, $(IN_QCA808X_PHY))
+    SRC_LIST += qca808x_phy.c
+    SRC_LIST += qca808x.c
+ifeq (TRUE, $(IN_LED))
+    SRC_LIST += qca808x_led.c
+endif
+ifeq (TRUE, $(IN_PTP))
+    SRC_LIST += qca808x_ptp.c
+    SRC_LIST += qca808x_ptp_api.c
+ifeq ($(CONFIG_PTP_1588_CLOCK), y)
+    SRC_LIST += qca808x_phc.c
+endif
+endif
+endif
+
+ifeq (TRUE, $(IN_SFP_PHY))
+    SRC_LIST += sfp_phy.c
+endif
+
+SRC_LIST += hsl_phy.c
+
+ifeq (linux, $(OS))
+	ifeq (KSLIB, $(MODULE_TYPE))
+    ifneq (TRUE, $(KERNEL_MODE))
+      SRC_LIST=
+	  endif
+	endif
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/hsl/phy/aquantia_phy.c b/qca-ssdk/src/hsl/phy/aquantia_phy.c
new file mode 100755
index 0000000..10f0396
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/aquantia_phy.c
@@ -0,0 +1,2205 @@
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "fal_port_ctrl.h"
+#include "hsl_api.h"
+#include "hsl.h"
+#include "aquantia_phy.h"
+#include "hsl_phy.h"
+#include "ssdk_plat.h"
+
+/* #define aquantia_phy_reg_read _phy_reg_read  */
+/* #define aquantia_phy_reg_write _phy_reg_write */
+
+/******************************************************************************
+*
+* aquantia_phy_mii_read - mii register read
+*
+* mii register read
+*/
+static sw_error_t
+aquantia_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_mmd,
+	a_uint32_t reg_id, a_uint16_t *phy_data)
+{
+	sw_error_t rv;
+
+	reg_id = AQUANTIA_REG_ADDRESS(reg_mmd, reg_id);
+	HSL_PHY_GET(rv, dev_id, phy_id, reg_id, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_mii_write - mii register write
+*
+* mii register write
+*/
+static sw_error_t
+aquantia_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_mmd,
+	a_uint32_t reg_id, a_uint16_t reg_val)
+{
+	sw_error_t rv;
+
+	reg_id = AQUANTIA_REG_ADDRESS(reg_mmd, reg_id);
+	HSL_PHY_SET(rv, dev_id,  phy_id, reg_id, reg_val);
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* aquantia_phy_get_phy_id - get the phy id
+*
+*/
+sw_error_t
+aquantia_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *phy_data)
+{
+	sw_error_t rv;
+	a_uint16_t org_id, rev_id;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS,
+		AQUANTIA_PHY_ID1, &org_id);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS,
+		AQUANTIA_PHY_ID2, &rev_id);
+	SW_RTN_ON_ERROR(rv);
+
+	*phy_data = ((org_id & 0xffff) << 16) | (rev_id & 0xffff);
+
+	return rv;
+}
+#endif
+sw_error_t
+aquantia_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+		     fal_port_speed_t * speed)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+	a_bool_t link_status;
+
+	link_status = aquantia_phy_get_link_status(dev_id, phy_id);
+	if (link_status != A_TRUE) {
+		/*the speed register(0x4007c800) is not stable when aquantia phy is down,
+		 but some APIs such as aquantia_phy_set_duplex() aquantia_phy_interface_set_mode()
+		 need to get the speed, so set the speed default value as 100M when link down*/
+		*speed = FAL_SPEED_100;
+		return SW_OK;
+	}
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_REG_AUTONEG_VENDOR_STATUS, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	switch ((phy_data & AQUANTIA_STATUS_SPEED_MASK) >> 1) {
+		case AQUANTIA_STATUS_SPEED_100MBS:
+			*speed = FAL_SPEED_100;
+			break;
+		case AQUANTIA_STATUS_SPEED_1000MBS:
+			*speed = FAL_SPEED_1000;
+			break;
+		case AQUANTIA_STATUS_SPEED_10000MBS:
+			*speed = FAL_SPEED_10000;
+			break;
+		case AQUANTIA_STATUS_SPEED_2500MBS:
+			*speed = FAL_SPEED_2500;
+			break;
+		case AQUANTIA_STATUS_SPEED_5000MBS:
+			*speed = FAL_SPEED_5000;
+			break;
+		default:
+			return SW_READ_ERROR;
+	}
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_get_duplex - Determines the speed of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+aquantia_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+		      fal_port_duplex_t * duplex)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+	a_bool_t link_status;
+
+	link_status = aquantia_phy_get_link_status(dev_id, phy_id);
+	if (link_status != A_TRUE)
+	{
+		return SW_OK;
+	}
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_REG_AUTONEG_VENDOR_STATUS, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	//read duplex
+	if (phy_data & AQUANTIA_STATUS_FULL_DUPLEX)
+	{
+		*duplex = FAL_FULL_DUPLEX;
+	}
+	else
+	{
+		*duplex = FAL_HALF_DUPLEX;
+	}
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* aquantia_phy_reset - reset the phy
+*
+* reset the phy
+*/
+sw_error_t aquantia_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_GLOBAL_STANDARD_CONTROL1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+	AQUANTIA_GLOBAL_STANDARD_CONTROL1, phy_data | AQUANTIA_CTRL_SOFTWARE_RESET);
+	aos_mdelay(100);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_set_powersave - set power saving status
+*
+* set power saving status
+*/
+sw_error_t
+aquantia_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_GLOBAL_RESERVED_PROVISIONING6, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	if (enable == A_TRUE)
+	{
+		phy_data |= AQUANTIA_POWER_SAVE;
+	}
+	else
+	{
+		phy_data &= ~AQUANTIA_POWER_SAVE;
+	}
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_GLOBAL_RESERVED_PROVISIONING6,phy_data);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_restart_autoneg(dev_id, phy_id);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_get_powersave - get power saving status
+*
+* set power saving status
+*/
+sw_error_t
+aquantia_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_GLOBAL_RESERVED_PROVISIONING6, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	if (phy_data& AQUANTIA_POWER_SAVE)
+	{
+		*enable = A_TRUE;
+	}
+	else
+	{
+		*enable = A_FALSE;
+	}
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_set_mdix -
+*
+* set phy mdix configuraiton
+*/
+sw_error_t
+aquantia_phy_set_mdix(a_uint32_t dev_id, a_uint32_t phy_id,
+		    fal_port_mdix_mode_t mode)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_RESERVED_VENDOR_PROVISIONING1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data &= ~(BITS(0,2));
+	switch(mode)
+	{
+		case PHY_MDIX_AUTO:
+			phy_data |= AQUANTIA_PHY_MDIX_AUTO;
+			break;
+		case PHY_MDIX_MDIX:
+			phy_data |= AQUANTIA_PHY_MDIX;
+			break;
+		case PHY_MDIX_MDI:
+			phy_data |= AQUANTIA_PHY_MDI;
+			break;
+		default:
+			return SW_BAD_PARAM;
+	}
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_RESERVED_VENDOR_PROVISIONING1,phy_data);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_restart_autoneg(dev_id, phy_id);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_get_mdix
+*
+* get phy mdix configuration
+*/
+sw_error_t
+aquantia_phy_get_mdix(a_uint32_t dev_id, a_uint32_t phy_id,
+		    fal_port_mdix_mode_t * mode)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_RESERVED_VENDOR_PROVISIONING1,&phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data  &= BITS(0,2);
+	switch(phy_data)
+	{
+		case AQUANTIA_PHY_MDIX_AUTO:
+			*mode = PHY_MDIX_AUTO;
+			break;
+		case AQUANTIA_PHY_MDIX:
+			*mode = PHY_MDIX_MDIX;
+			break;
+		case AQUANTIA_PHY_MDI:
+			*mode = PHY_MDIX_MDI;
+			break;
+		default:
+			return SW_NOT_SUPPORTED;
+	}
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_get_mdix status
+*
+* get phy mdix status
+*/
+sw_error_t
+aquantia_phy_get_mdix_status(a_uint32_t dev_id, a_uint32_t phy_id,
+			   fal_port_mdix_status_t * mode)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_RESERVED_VENDOR_STATUS1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	*mode = (phy_data &  AQUANTIA_PHY_MDIX_STATUS) ? PHY_MDIX_STATUS_MDIX :
+	    PHY_MDIX_STATUS_MDI;
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_set_local_loopback
+*
+* set phy local loopback
+*/
+sw_error_t
+aquantia_phy_set_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	fal_port_speed_t old_speed;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS,
+		AQUANTIA_PHY_XS_TRANAMIT_RESERVED_VENDOR_PROVISION5, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	if (enable == A_TRUE)
+	{
+		phy_data |= AQUANTIA_INTERNAL_LOOPBACK;
+		rv = aquantia_phy_get_speed(dev_id, phy_id, &old_speed);
+		SW_RTN_ON_ERROR(rv);
+		switch(old_speed)
+		{
+			case FAL_SPEED_100:
+				phy_data |= AQUANTIA_100M_LOOPBACK;
+				break;
+			case FAL_SPEED_1000:
+				 phy_data |= AQUANTIA_1000M_LOOPBACK;
+				 break;
+			case FAL_SPEED_10000:
+				phy_data |= AQUANTIA_10000M_LOOPBACK;
+				break;
+			case FAL_SPEED_2500:
+				 phy_data |= AQUANTIA_2500M_LOOPBACK;
+				 break;
+			case FAL_SPEED_5000:
+				phy_data |= AQUANTIA_5000M_LOOPBACK;
+				break;
+			default:
+				return SW_FAIL;
+		}
+	}
+	else
+	{
+		phy_data &= ~(AQUANTIA_INTERNAL_LOOPBACK | AQUANTIA_ALL_SPEED_LOOPBACK);
+	}
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS,
+		AQUANTIA_PHY_XS_TRANAMIT_RESERVED_VENDOR_PROVISION5,phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_get_local_loopback
+*
+* get phy local loopback
+*/
+sw_error_t
+aquantia_phy_get_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS,
+		AQUANTIA_PHY_XS_TRANAMIT_RESERVED_VENDOR_PROVISION5, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	if (phy_data & AQUANTIA_INTERNAL_LOOPBACK)
+	{
+		*enable = A_TRUE;
+	}
+	else
+	{
+		*enable = A_FALSE;
+	}
+
+	return rv;
+}
+
+sw_error_t
+aquantia_phy_set_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+				   a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	fal_port_speed_t speed;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS,
+		AQUANTIA_PHY_XS_TRANAMIT_RESERVED_VENDOR_PROVISION5, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+
+	if (enable == A_TRUE)
+	{
+		rv = aquantia_phy_get_speed(dev_id,  phy_id, &speed);
+		SW_RTN_ON_ERROR(rv);
+		switch(speed)
+		{
+			case FAL_SPEED_100:
+				phy_data |= AQUANTIA_100M_LOOPBACK;
+				break;
+			case FAL_SPEED_1000:
+				phy_data |= AQUANTIA_1000M_LOOPBACK;
+				break;
+			case FAL_SPEED_2500:
+				phy_data |= AQUANTIA_2500M_LOOPBACK;
+				break;
+			case FAL_SPEED_5000:
+				phy_data |= AQUANTIA_5000M_LOOPBACK;
+				break;
+			case FAL_SPEED_10000:
+				phy_data |= AQUANTIA_10000M_LOOPBACK;
+				break;
+			default:
+				break;
+		}
+		phy_data |= AQUANTIA_PHY_REMOTE_LOOPBACK;
+	}
+	else
+	{
+		phy_data &= ~(AQUANTIA_PHY_REMOTE_LOOPBACK |AQUANTIA_ALL_SPEED_LOOPBACK);
+	}
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS,
+		AQUANTIA_PHY_XS_TRANAMIT_RESERVED_VENDOR_PROVISION5, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_get_remote_loopback
+*
+* get phy remote loopback
+*/
+sw_error_t
+aquantia_phy_get_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+				   a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS,
+		AQUANTIA_PHY_XS_TRANAMIT_RESERVED_VENDOR_PROVISION5, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	if (phy_data & AQUANTIA_PHY_REMOTE_LOOPBACK)
+	{
+		*enable = A_TRUE;
+	}
+	else
+	{
+		*enable = A_FALSE;
+	}
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_cdt - cable diagnostic test
+*
+* cable diagnostic test
+*/
+static inline fal_cable_status_t _phy_cdt_status_mapping(a_uint32_t pair_type, a_uint16_t status)
+{
+	fal_cable_status_t status_mapping = FAL_CABLE_STATUS_INVALID;
+
+	switch(status)
+	{
+		case 0:
+			status_mapping = FAL_CABLE_STATUS_NORMAL;
+			break;
+		case 1:
+			if(pair_type == CABLE_PAIR_B)
+				status_mapping = FAL_CABLE_STATUS_CROSSOVERA;
+			else if(pair_type == CABLE_PAIR_C)
+				status_mapping = FAL_CABLE_STATUS_CROSSOVERB;
+			else if(pair_type == CABLE_PAIR_D)
+				status_mapping = FAL_CABLE_STATUS_CROSSOVERC;
+			else
+				status_mapping = FAL_CABLE_STATUS_INVALID;
+			break;
+		case 2:
+			if(pair_type == CABLE_PAIR_C)
+				status_mapping = FAL_CABLE_STATUS_CROSSOVERA;
+			else if(pair_type == CABLE_PAIR_D)
+				status_mapping = FAL_CABLE_STATUS_CROSSOVERB;
+			else
+				status_mapping = FAL_CABLE_STATUS_INVALID;
+			break;
+		case 3:
+			if(pair_type == CABLE_PAIR_D)
+				status_mapping = FAL_CABLE_STATUS_CROSSOVERA;
+			else
+				status_mapping = FAL_CABLE_STATUS_INVALID;
+			break;
+		case 4:
+			status_mapping = FAL_CABLE_STATUS_SHORT;
+			break;
+		case 5:
+			status_mapping = FAL_CABLE_STATUS_LOW_MISMATCH;
+			break;
+		case 6:
+			status_mapping = FAL_CABLE_STATUS_HIGH_MISMATCH;
+			break;
+		case 7:
+			status_mapping = FAL_CABLE_STATUS_OPENED;
+			break;
+		default:
+			status_mapping = FAL_CABLE_STATUS_INVALID;
+			break;
+	}
+
+	return status_mapping;
+}
+
+sw_error_t
+aquantia_phy_cdt_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		   fal_port_cdt_t * port_cdt)
+{
+	a_uint16_t status = 0;
+	sw_error_t rv = SW_OK;
+	a_uint16_t phy_data;
+
+	if (!port_cdt) {
+		return SW_FAIL;
+	}
+	/* Get cable status */
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_CABLE_DIAGNOSTIC_STATUS1, &status);
+	SW_RTN_ON_ERROR(rv);
+	port_cdt->pair_a_status =  (status & AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRA) >> 12
+		& BITS(0, 3);
+	port_cdt->pair_b_status = (status & AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRB) >> 8
+		& BITS(0, 3);
+	port_cdt->pair_c_status = (status & AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRC) >> 4
+		& BITS(0, 3);
+	port_cdt->pair_d_status = (status & AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRD)
+		& BITS(0, 3);
+	SSDK_DEBUG("status:%x, pair_a_status:%x,pair_b_status:%x,pair_c_status:%x, pair_d_status:%x\n",
+		status, port_cdt->pair_a_status,port_cdt->pair_b_status,
+		port_cdt->pair_c_status, port_cdt->pair_d_status);
+	/* Get Cable Length value */
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_CABLE_DIAGNOSTIC_STATUS2, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	port_cdt->pair_a_len = phy_data >> 8 & BITS(0, 8);
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_CABLE_DIAGNOSTIC_STATUS4, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	port_cdt->pair_b_len = phy_data >> 8 & BITS(0, 8);
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_CABLE_DIAGNOSTIC_STATUS6, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	port_cdt->pair_c_len = phy_data >> 8 & BITS(0, 8);
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_CABLE_DIAGNOSTIC_STATUS8, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	port_cdt->pair_d_len = phy_data >> 8 & BITS(0, 8);
+
+	return rv;
+}
+
+sw_error_t aquatia_phy_cdt_start(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t status = 0, phy_data = 0;
+	a_uint32_t aq_phy_id;
+	a_uint16_t ii = 300;
+	sw_error_t rv = SW_OK;
+
+	/*select mode0 if aq107, and select mode2 if aq109*/
+	rv = aquantia_phy_get_phy_id(dev_id, phy_id, &aq_phy_id);
+	SW_RTN_ON_ERROR(rv);
+	rv  = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_GLOBAL_CDT_CONTROL, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	if(aq_phy_id == AQUANTIA_PHY_109)
+	{
+		phy_data |= AQUANTIA_PHY_CDT_MODE2;
+	}
+	else
+	{
+		phy_data |= AQUANTIA_PHY_CDT_MODE0;
+	}
+
+	phy_data |= AQUANTIA_NORMAL_CABLE_DIAGNOSTICS;
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		 AQUANTIA_GLOBAL_CDT_CONTROL, phy_data);
+	SW_RTN_ON_ERROR(rv);
+	do {
+		aos_mdelay(30);
+		rv  = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+			AQUANTIA_GLOBAL_GENERAL_STATUS, &status);
+		SW_RTN_ON_ERROR(rv);
+	}
+	while ((status & AQUANTIA_CABLE_DIAGNOSTICS_STATUS) && (--ii));
+
+	return rv;
+}
+
+sw_error_t
+aquantia_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+	       fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+	fal_port_cdt_t aquantia_port_cdt;
+	sw_error_t rv = SW_OK;
+
+	if (mdi_pair >= 4) {
+		return SW_BAD_PARAM;
+	}
+	rv = aquatia_phy_cdt_start(dev_id, phy_id);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_cdt_get(dev_id, phy_id, &aquantia_port_cdt);
+	SW_RTN_ON_ERROR(rv);
+	switch (mdi_pair)
+	{
+		case 0:
+			*cable_status =
+				 _phy_cdt_status_mapping(CABLE_PAIR_A, aquantia_port_cdt.pair_a_status);
+			/* Get Cable Length value */
+			*cable_len = aquantia_port_cdt.pair_a_len;
+			break;
+		case 1:
+			*cable_status =
+				 _phy_cdt_status_mapping(CABLE_PAIR_B, aquantia_port_cdt.pair_b_status);
+			/* Get Cable Length value */
+			*cable_len = aquantia_port_cdt.pair_b_len;
+			break;
+		case 2:
+			*cable_status =
+				_phy_cdt_status_mapping(CABLE_PAIR_C, aquantia_port_cdt.pair_c_status);
+			/* Get Cable Length value */
+			*cable_len = aquantia_port_cdt.pair_c_len;
+			break;
+		case 3:
+			*cable_status =
+				 _phy_cdt_status_mapping(CABLE_PAIR_D, aquantia_port_cdt.pair_d_status);
+			/* Get Cable Length value */
+			*cable_len = aquantia_port_cdt.pair_d_len;
+			break;
+		default:
+			break;
+	}
+
+	return rv;
+}
+#endif
+/******************************************************************************
+*
+* AQUANTIA_autoneg_done
+*
+* AQUANTIA_autoneg_done
+*/
+a_bool_t aquantia_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	a_uint16_t ii = 200;
+	sw_error_t rv = SW_OK;
+
+	do {
+		rv =  aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+			AQUANTIA_AUTONEG_STANDARD_STATUS1, &phy_data);
+		SW_RTN_ON_ERROR(rv);
+		aos_mdelay(10);
+	}
+	while ((!AQUANTIA_AUTONEG_DONE(phy_data)) && --ii);
+
+	if (ii == 0)
+		return A_FALSE;
+
+	return A_TRUE;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* aquantia_phy_get_ability - get the phy ability
+*
+*
+*/
+sw_error_t
+aquantia_phy_get_partner_ability(a_uint32_t dev_id, a_uint32_t phy_id,
+			       a_uint32_t * ability)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	*ability = 0;
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_LINK_PARTNER_ABILITY, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	if (phy_data & AQUANTIA_LINK_10BASETX_HALF_DUPLEX)
+	{
+		*ability |= FAL_PHY_PART_10T_HD;
+	}
+	if (phy_data & AQUANTIA_LINK_10BASETX_FULL_DUPLEX)
+	{
+		*ability |= FAL_PHY_PART_10T_FD;
+	}
+	if (phy_data & AQUANTIA_LINK_100BASETX_HALF_DUPLEX)
+	{
+		*ability |= FAL_PHY_PART_100TX_HD;
+	}
+	if (phy_data & AQUANTIA_LINK_100BASETX_FULL_DUPLEX)
+	{
+		*ability |= FAL_PHY_PART_100TX_FD;
+	}
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_LINK_PARTNER_5G_ABILITY, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	if (phy_data & AQUANTIA_LINK_1000BASETX_FULL_DUPLEX)
+	{
+		*ability |= FAL_PHY_PART_1000T_FD;
+	}
+	if (phy_data & AQUANTIA_LINK_5000BASETX_FULL_DUPLEX)
+	{
+		*ability |= FAL_PHY_PART_5000T_FD;
+	}
+	if (phy_data & AQUANTIA_LINK_2500BASETX_FULL_DUPLEX)
+	{
+		*ability |= FAL_PHY_PART_2500T_FD;
+	}
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_LINK_PARTNER_10G_ABILITY, &phy_data);
+	if (phy_data & AQUANTIA_LINK_10000BASETX_FULL_DUPLEX)
+	{
+		*ability |= FAL_PHY_PART_10000T_FD;
+	}
+
+	return rv;
+}
+#endif
+/******************************************************************************
+*
+* aquantia_phy_status - test to see if the specified phy link is alive
+*
+* RETURNS:
+*    A_TRUE  --> link is alive
+*    A_FALSE --> link is down
+*/
+a_bool_t aquantia_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	/*in order to get the  link status of real time, need to read the link status two times */
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_STANDARD_STATUS1, &phy_data);
+	if(rv != SW_OK)
+	{
+		return A_FALSE;
+	}
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_STANDARD_STATUS1, &phy_data);
+	if(rv != SW_OK)
+	{
+		return A_FALSE;
+	}
+	if (phy_data & AQUANTIA_STATUS_LINK)
+	{
+		return A_TRUE;
+	}
+
+	return A_FALSE;
+}
+
+/******************************************************************************
+*
+* AQUANTIA_set_autoneg_adv - set the phy autoneg Advertisement
+*
+*/
+sw_error_t
+aquantia_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+			   a_uint32_t autoneg)
+{
+	a_uint16_t phy_data = 0, phy_data1 = 0 ;
+	sw_error_t rv = SW_OK;
+
+	if ((autoneg & FAL_PHY_ADV_10T_FD) ||(autoneg & FAL_PHY_ADV_10T_HD)||
+		(autoneg & FAL_PHY_ADV_100TX_HD))
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data &= ~AQUANTIA_ADVERTISE_MEGA_ALL;
+	phy_data &=
+	    ~(AQUANTIA_ADVERTISE_PAUSE | AQUANTIA_ADVERTISE_ASYM_PAUSE);
+	if (autoneg & FAL_PHY_ADV_100TX_FD)
+	{
+		phy_data |= AQUANTIA_ADVERTISE_100FULL;
+	}
+	if (autoneg & FAL_PHY_ADV_PAUSE)
+	{
+		phy_data |= AQUANTIA_ADVERTISE_PAUSE;
+	}
+	if (autoneg & FAL_PHY_ADV_ASY_PAUSE)
+	{
+		phy_data |= AQUANTIA_ADVERTISE_ASYM_PAUSE;
+	}
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, phy_data);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_VENDOR_PROVISION1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data &= ~AQUANTIA_ADVERTISE_GIGA_ALL;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER, &phy_data1);
+	SW_RTN_ON_ERROR(rv);
+	phy_data1 &= ~AQUANTIA_ADVERTISE_GIGA_PLUS_ALL;
+	if (autoneg & FAL_PHY_ADV_1000T_FD)
+	{
+		phy_data |= AQUANTIA_ADVERTISE_1000FULL;
+	}
+	if (autoneg & FAL_PHY_ADV_2500T_FD)
+	{
+		phy_data |= AQUANTIA_ADVERTISE_2500FULL;
+		phy_data1 |= AQUANTIA_ADVERTISE_8023BZ_2500FULL;
+	}
+	if (autoneg & FAL_PHY_ADV_5000T_FD)
+	{
+		phy_data |= AQUANTIA_ADVERTISE_5000FULL;
+		phy_data1 |= AQUANTIA_ADVERTISE_8023BZ_5000FULL;
+	}
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_VENDOR_PROVISION1, phy_data);
+	SW_RTN_ON_ERROR(rv);
+
+	if (autoneg & FAL_PHY_ADV_10000T_FD)
+		phy_data1 |= AQUANTIA_ADVERTISE_10000FULL;
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER,phy_data1);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* AQUANTIA_get_autoneg_adv - get the phy autoneg Advertisement
+*
+*/
+sw_error_t
+aquantia_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+			   a_uint32_t * autoneg)
+{
+	a_uint16_t phy_data = 0, phy_data1 = 0;
+	sw_error_t rv = SW_OK;
+
+	*autoneg = 0;
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	if (phy_data & AQUANTIA_ADVERTISE_100FULL)
+	{
+		*autoneg |= FAL_PHY_ADV_100TX_FD;
+	}
+	if (phy_data & AQUANTIA_ADVERTISE_PAUSE)
+	{
+		*autoneg |= FAL_PHY_ADV_PAUSE;
+	}
+	if (phy_data & AQUANTIA_ADVERTISE_ASYM_PAUSE)
+	{
+		*autoneg |= FAL_PHY_ADV_ASY_PAUSE;
+	}
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_VENDOR_PROVISION1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER, &phy_data1);
+	SW_RTN_ON_ERROR(rv);
+	if (phy_data & AQUANTIA_ADVERTISE_1000FULL)
+	{
+		*autoneg |= FAL_PHY_ADV_1000T_FD;
+	}
+	if ((phy_data & AQUANTIA_ADVERTISE_2500FULL) &&
+		(phy_data1 & AQUANTIA_ADVERTISE_8023BZ_2500FULL))
+	{
+		*autoneg |= FAL_PHY_ADV_2500T_FD;
+	}
+	if ((phy_data & AQUANTIA_ADVERTISE_5000FULL) &&
+		(phy_data1 & AQUANTIA_ADVERTISE_8023BZ_5000FULL))
+	{
+		*autoneg |= FAL_PHY_ADV_5000T_FD;
+	}
+
+	if (phy_data1 & AQUANTIA_ADVERTISE_10000FULL)
+	{
+		*autoneg |= FAL_PHY_ADV_10000T_FD;
+	}
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_enable_autonego
+*
+*/
+a_bool_t aquantia_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_STANDARD_CONTROL1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	if (phy_data & AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE)
+	{
+		return A_TRUE;
+	}
+
+	return A_FALSE;
+}
+/******************************************************************************
+*
+* AQUANTIA_restart_autoneg - restart the phy autoneg
+*
+*/
+sw_error_t aquantia_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS,
+		AQUANTIA_PHY_XS_USX_TRANSMIT, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	if (!(phy_data & AQUANTIA_PHY_USX_AUTONEG_ENABLE))
+	{
+		rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS,
+			AQUANTIA_PHY_XS_USX_TRANSMIT,
+			phy_data | AQUANTIA_PHY_USX_AUTONEG_ENABLE);
+		SW_RTN_ON_ERROR(rv);
+	}
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_STANDARD_CONTROL1, &phy_data);
+	phy_data |= AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE;
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_STANDARD_CONTROL1,
+		phy_data | AQUANTIA_CTRL_RESTART_AUTONEGOTIATION);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_enable_autonego
+*
+*/
+sw_error_t aquantia_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_STANDARD_CONTROL1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_STANDARD_CONTROL1,
+		phy_data | AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE);
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* aquantia_phy_set_802.3az
+*
+* set 802.3az status
+*/
+sw_error_t
+aquantia_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data = 0, phy_data1 = 0;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_EEE_ADVERTISTMENT_REGISTER, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_EEE_ADVERTISTMENT_REGISTER1, &phy_data1);
+	SW_RTN_ON_ERROR(rv);
+	if(enable == A_TRUE)
+	{
+		phy_data |= (AQUANTIA_EEE_ADV_10000M | AQUANTIA_EEE_ADV_1000M);
+		phy_data1 |= (AQUANTIA_EEE_ADV_2500M | AQUANTIA_EEE_ADV_5000M);
+	}
+	else
+	{
+		phy_data &= ~(AQUANTIA_EEE_ADV_10000M | AQUANTIA_EEE_ADV_1000M);
+		phy_data1 &= ~(AQUANTIA_EEE_ADV_2500M | AQUANTIA_EEE_ADV_5000M);
+	}
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_EEE_ADVERTISTMENT_REGISTER, phy_data);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_EEE_ADVERTISTMENT_REGISTER1, phy_data1);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_restart_autoneg(dev_id, phy_id);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_get_8023az status
+*
+* get 8023az status
+*/
+sw_error_t
+aquantia_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable)
+{
+	a_uint16_t phy_data = 0, phy_data1 = 0;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_EEE_ADVERTISTMENT_REGISTER, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_EEE_ADVERTISTMENT_REGISTER1, &phy_data1);
+	SW_RTN_ON_ERROR(rv);
+
+	if((phy_data & (AQUANTIA_EEE_ADV_1000M | AQUANTIA_EEE_ADV_10000M)) &&
+		(phy_data1 & (AQUANTIA_EEE_ADV_2500M | AQUANTIA_EEE_ADV_5000M)))
+	{
+		*enable = A_TRUE;
+	}
+	else
+	{
+		*enable = A_FALSE;
+	}
+
+	return rv;
+}
+#endif
+/******************************************************************************
+*
+* aquantia_phy_set_speed - Determines the speed of phy ports associated with the
+* specified device.
+*/
+static sw_error_t _aquantia_phy_set_100speed(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_duplex_t duplex)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+	/*set 100M */
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data &= ~(AQUANTIA_ADVERTISE_MEGA_ALL);
+	if(duplex == FAL_FULL_DUPLEX)
+	{
+		phy_data |= AQUANTIA_ADVERTISE_100FULL;
+	}
+	else
+	{
+		phy_data |= AQUANTIA_ADVERTISE_100HALF;
+	}
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, phy_data);
+	SW_RTN_ON_ERROR(rv);
+	/*disable 1000M, 2500M, 5000M speed*/
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_VENDOR_PROVISION1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data &= ~(AQUANTIA_ADVERTISE_GIGA_ALL);
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_VENDOR_PROVISION1, phy_data);
+	SW_RTN_ON_ERROR(rv);
+	/*disable 10000M speed*/
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data &= ~(AQUANTIA_ADVERTISE_GIGA_PLUS_ALL);
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER, phy_data);
+
+	return rv;
+}
+
+static sw_error_t _aquantia_phy_set_giga_speed(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_speed_t speed)
+{
+	a_uint16_t phy_data = 0, phy_data1 = 0;
+	sw_error_t rv = SW_OK;
+	/*set 1000M and disable 2500M, 5000M */
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_VENDOR_PROVISION1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data &= ~(AQUANTIA_ADVERTISE_GIGA_ALL);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER, &phy_data1);
+	SW_RTN_ON_ERROR(rv);
+	phy_data1 &= ~(AQUANTIA_ADVERTISE_GIGA_PLUS_ALL);
+	switch(speed)
+	{
+		case FAL_SPEED_1000:
+			phy_data |= AQUANTIA_ADVERTISE_1000FULL;
+			break;
+		case FAL_SPEED_2500:
+			phy_data |= AQUANTIA_ADVERTISE_2500FULL;
+			phy_data1 |= AQUANTIA_ADVERTISE_8023BZ_2500FULL;
+			break;
+		case FAL_SPEED_5000:
+			phy_data |= AQUANTIA_ADVERTISE_5000FULL;
+			phy_data1 |= AQUANTIA_ADVERTISE_8023BZ_5000FULL;
+			break;
+		default:
+			return SW_NOT_SUPPORTED;
+	}
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_VENDOR_PROVISION1, phy_data);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER, phy_data1);
+	SW_RTN_ON_ERROR(rv);
+
+	/*disable 100M speed*/
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data &= ~(AQUANTIA_ADVERTISE_MEGA_ALL);
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, phy_data);
+
+	return rv;
+}
+
+static sw_error_t _aquantia_phy_set_10g_speed(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+	/*set giga speed */
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER,&phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data &= ~(AQUANTIA_ADVERTISE_GIGA_PLUS_ALL);
+	phy_data |= AQUANTIA_ADVERTISE_10000FULL;
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER, phy_data);
+	SW_RTN_ON_ERROR(rv);
+
+	/*disable 100M speed*/
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data &= ~(AQUANTIA_ADVERTISE_MEGA_ALL);
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, phy_data);
+	SW_RTN_ON_ERROR(rv);
+
+	/*disable 1000M 2500M 5000M speed*/
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_VENDOR_PROVISION1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data &= ~(AQUANTIA_ADVERTISE_GIGA_ALL);
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_VENDOR_PROVISION1, phy_data);
+
+	return rv;
+}
+
+sw_error_t
+aquantia_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+		     fal_port_speed_t speed)
+{
+	fal_port_duplex_t old_duplex;
+	sw_error_t rv;
+
+	rv = aquantia_phy_get_duplex(dev_id, phy_id, &old_duplex);
+	SW_RTN_ON_ERROR(rv);
+	if (old_duplex == FAL_FULL_DUPLEX) {
+		if (FAL_SPEED_100 == speed) {
+			rv = _aquantia_phy_set_100speed(dev_id, phy_id, FAL_FULL_DUPLEX);
+			SW_RTN_ON_ERROR(rv);
+		} else if(FAL_SPEED_2500 == speed ||FAL_SPEED_5000 == speed || FAL_SPEED_1000 == speed){
+			rv = _aquantia_phy_set_giga_speed(dev_id, phy_id, speed);
+			SW_RTN_ON_ERROR(rv);
+		} else if(FAL_SPEED_10000 == speed){
+			rv = _aquantia_phy_set_10g_speed(dev_id, phy_id);
+			SW_RTN_ON_ERROR(rv);
+		} else {
+			return SW_BAD_PARAM;
+		}
+	} else if (old_duplex == FAL_HALF_DUPLEX) {
+		if (FAL_SPEED_100 == speed) {
+			rv = _aquantia_phy_set_100speed(dev_id, phy_id, FAL_HALF_DUPLEX);
+			SW_RTN_ON_ERROR(rv);
+		} else {
+			return SW_BAD_PARAM;
+		}
+	} else {
+		return SW_FAIL;
+	}
+	rv = aquantia_phy_restart_autoneg(dev_id, phy_id);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_set_duplex - Determines the speed of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+aquantia_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+		      fal_port_duplex_t duplex)
+{
+	a_uint16_t phy_data = 0;
+	fal_port_speed_t old_speed;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_get_speed(dev_id, phy_id, &old_speed);
+	SW_RTN_ON_ERROR(rv);
+	if (old_speed == FAL_SPEED_100){
+		rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+			AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, &phy_data);
+		SW_RTN_ON_ERROR(rv);
+		if (duplex == FAL_FULL_DUPLEX) {
+			phy_data &= ~(AQUANTIA_ADVERTISE_MEGA_ALL);
+			phy_data |= AQUANTIA_ADVERTISE_100FULL;
+			 rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+				AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, phy_data);
+			 SW_RTN_ON_ERROR(rv);
+		 } else {
+		 	phy_data &= ~(AQUANTIA_ADVERTISE_MEGA_ALL);
+			phy_data |= AQUANTIA_ADVERTISE_100HALF;
+			rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+				AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, phy_data);
+			SW_RTN_ON_ERROR(rv);
+		 }
+	} else {
+	 	return SW_NOT_SUPPORTED;
+	}
+	rv = aquantia_phy_restart_autoneg(dev_id, phy_id);
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* aquantia_phy_set wol enable or disable
+*
+* set phy wol enable or disable
+*/
+sw_error_t
+aquantia_phy_set_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data0, phy_data1, phy_data2;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_RESERVED_VENDOR_PROVISIONING1, &phy_data0);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS,
+		AQUANTIA_MAGIC_ENGINE_REGISTER1, &phy_data1);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS,
+		AQUANTIA_MAGIC_ENGINE_REGISTER2, &phy_data2);
+
+	if (enable == A_TRUE)
+	{
+		phy_data0 |= AQUANTIA_PHY_WOL_ENABLE;
+		phy_data1 |= AQUANTIA_MAGIC_PACKETS_ENABLE;
+		phy_data2 |= AQUANTIA_MAGIC_PACKETS_ENABLE;
+	}
+	else
+	{
+		phy_data0 &= ~AQUANTIA_PHY_WOL_ENABLE;
+		phy_data1 &= ~AQUANTIA_MAGIC_PACKETS_ENABLE;
+		phy_data2 &= ~AQUANTIA_MAGIC_PACKETS_ENABLE;
+	}
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_RESERVED_VENDOR_PROVISIONING1, phy_data0);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS,
+		AQUANTIA_MAGIC_ENGINE_REGISTER1, phy_data1);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS,
+		AQUANTIA_MAGIC_ENGINE_REGISTER2, phy_data2);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_get_wol status
+*
+* get wol status
+*/
+sw_error_t
+aquantia_phy_get_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	*enable = A_FALSE;
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_RESERVED_VENDOR_PROVISIONING1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	if (phy_data & AQUANTIA_PHY_WOL_ENABLE)
+	{
+		*enable = A_TRUE;
+	}
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_set wol frame mac address
+*
+* set phy wol frame mac address
+*/
+sw_error_t
+aquantia_phy_set_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id,
+			       fal_mac_addr_t * mac)
+{
+	a_uint16_t phy_data1;
+	a_uint16_t phy_data2;
+	a_uint16_t phy_data3;
+	sw_error_t rv = SW_OK;
+
+	phy_data1 = (mac->uc[1] << 8) | mac->uc[0];
+	phy_data2 = (mac->uc[3] << 8) | mac->uc[2];
+	phy_data3 = (mac->uc[5] << 8) | mac->uc[4];
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS,
+		AQUANTIA_MAGIC_FRAME_MAC0, phy_data1);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS,
+		AQUANTIA_MAGIC_FRAME_MAC1, phy_data2);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS,
+		AQUANTIA_MAGIC_FRAME_MAC2, phy_data3);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_get wol frame mac address
+*
+* get phy wol frame mac address
+*/
+sw_error_t
+aquantia_phy_get_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id,
+			       fal_mac_addr_t * mac)
+{
+	a_uint16_t phy_data1;
+	a_uint16_t phy_data2;
+	a_uint16_t phy_data3;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS,
+		AQUANTIA_MAGIC_FRAME_MAC0, &phy_data1);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS,
+		AQUANTIA_MAGIC_FRAME_MAC1, &phy_data2);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS,
+		AQUANTIA_MAGIC_FRAME_MAC2, &phy_data3);
+	SW_RTN_ON_ERROR(rv);
+	mac->uc[0] = (phy_data1 & BITS(0, 8));
+	mac->uc[1] = (phy_data1 >> 8) & BITS(0, 8);
+	mac->uc[2] = (phy_data2 & BITS(0, 8));
+	mac->uc[3] = (phy_data2 >> 8) & BITS(0, 8);
+	mac->uc[4] = (phy_data3 & BITS(0, 8));
+	mac->uc[5] = (phy_data3 >> 8) & BITS(0, 8);
+
+	return rv;
+}
+#endif
+sw_error_t
+aquantia_phy_interface_set_mode(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_interface_mode_t interface_mode)
+{
+	a_uint16_t phy_data;
+	a_uint32_t phy_register;
+	fal_port_speed_t speed;
+	sw_error_t rv =SW_OK;
+
+	rv = aquantia_phy_get_speed(dev_id, phy_id, &speed);
+	SW_RTN_ON_ERROR(rv);
+	switch (speed)
+	{
+		case FAL_SPEED_100:
+			phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_100M;
+			break;
+		case FAL_SPEED_1000:
+			phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_1000M;
+			break;
+		case FAL_SPEED_2500:
+			phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_2500M;
+			break;
+		case FAL_SPEED_5000:
+			phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_5000M;
+			break;
+		case FAL_SPEED_10000:
+			phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_10000M;
+			break;
+		default:
+			return SW_NOT_SUPPORTED;
+	}
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+					phy_register, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data &= ~(BITS(0, 3));
+	switch(interface_mode)
+	{
+		case PHY_SGMII_BASET:
+			if(speed == FAL_SPEED_100 || speed == FAL_SPEED_1000)
+			{
+				phy_data |= AQUANTIA_SERDES_MODE_SGMII;
+			}
+			else
+			{
+				return SW_NOT_SUPPORTED;
+			}
+			break;
+		case PORT_USXGMII:
+			phy_data |= AQUANTIA_SERDES_MODE_XFI;
+			break;
+		case PORT_SGMII_PLUS:
+			if(speed == FAL_SPEED_2500)
+			{
+				phy_data |= AQUANTIA_SERDES_MODE_OCSGMII;
+			}
+			else
+			{
+				return SW_NOT_SUPPORTED;
+			}
+			break;
+		default:
+			return SW_NOT_SUPPORTED;
+	}
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		phy_register, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_interface mode status get
+*
+* get aquantia phy interface mode status
+*/
+sw_error_t
+aquantia_phy_interface_get_mode_status(a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_port_interface_mode_t *interface_mode_status)
+{
+	a_uint16_t phy_data;
+	a_uint32_t phy_register;
+	fal_port_speed_t speed;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_get_speed(dev_id, phy_id, &speed);
+	SW_RTN_ON_ERROR(rv);
+	switch (speed)
+	{
+		case FAL_SPEED_100:
+			phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_100M;
+			break;
+		case FAL_SPEED_1000:
+			phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_1000M;
+			break;
+		case FAL_SPEED_2500:
+			phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_2500M;
+			break;
+		case FAL_SPEED_5000:
+			phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_5000M;
+			break;
+		case FAL_SPEED_10000:
+			phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_10000M;
+			break;
+		default:
+			return SW_NOT_SUPPORTED;
+	}
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		phy_register, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data &= (BITS(0, 3));
+	switch(phy_data)
+	{
+		case AQUANTIA_SERDES_MODE_SGMII:
+			*interface_mode_status = PHY_SGMII_BASET;
+			break;
+		case AQUANTIA_SERDES_MODE_XFI:
+			*interface_mode_status = PORT_USXGMII;
+			break;
+		case AQUANTIA_SERDES_MODE_OCSGMII:
+			*interface_mode_status = PORT_SGMII_PLUS;
+			break;
+		default:
+			return SW_NOT_SUPPORTED;
+	}
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* aquantia_phy_intr_mask_set - Set interrupt mask with the
+* specified device.
+*/
+sw_error_t
+aquantia_phy_intr_mask_set(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_uint32_t intr_mask_flag)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	if ((FAL_PHY_INTR_STATUS_DOWN_CHANGE |FAL_PHY_INTR_STATUS_UP_CHANGE)
+		& intr_mask_flag)
+	{
+		rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+			AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK, &phy_data);
+		SW_RTN_ON_ERROR(rv);
+		phy_data |= AQUANTIA_INTR_LINK_STATUS_CHANGE;
+		rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+			AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK, phy_data);
+		SW_RTN_ON_ERROR(rv);
+
+		rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+			AQUANTIA_GLOBAL_INTR_VENDOR_MASK, &phy_data);
+		SW_RTN_ON_ERROR(rv);
+		phy_data |= AQUANTIA_AUTO_AND_ALARMS_INTR_MASK;
+		rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+			AQUANTIA_GLOBAL_INTR_VENDOR_MASK, phy_data);
+		SW_RTN_ON_ERROR(rv);
+
+		rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+			AQUANTIA_GLOBAL_INTR_STANDARD_MASK, &phy_data);
+		SW_RTN_ON_ERROR(rv);
+		phy_data |= AQUANTIA_ALL_VENDOR_ALARMS_INTR_MASK;
+		rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+			AQUANTIA_GLOBAL_INTR_STANDARD_MASK, phy_data);
+	}
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_intr_mask_get - Get interrupt mask with the
+* specified device.
+*/
+sw_error_t
+aquantia_phy_intr_mask_get(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_uint32_t * intr_mask_flag)
+{
+	a_uint16_t phy_data1 = 0, phy_data2 = 0, phy_data3 = 0;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK, &phy_data1);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_GLOBAL_INTR_VENDOR_MASK, &phy_data2);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_GLOBAL_INTR_STANDARD_MASK, &phy_data3);
+	if ((AQUANTIA_INTR_LINK_STATUS_CHANGE & phy_data1) &&
+		(AQUANTIA_AUTO_AND_ALARMS_INTR_MASK & phy_data2) &&
+		(AQUANTIA_ALL_VENDOR_ALARMS_INTR_MASK & phy_data3))
+	{
+		*intr_mask_flag = FAL_PHY_INTR_STATUS_DOWN_CHANGE |
+			FAL_PHY_INTR_STATUS_UP_CHANGE;
+	}
+
+	return rv;
+}
+#endif
+/******************************************************************************
+*
+* aquantia_phy_off - power off the phy
+*
+* Power off the phy
+*/
+sw_error_t aquantia_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_GLOBAL_STANDARD_CONTROL1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data |= AQUANTIA_POWER_DOWN;
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_GLOBAL_STANDARD_CONTROL1,phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_on - power on the phy
+*
+* Power on the phy
+*/
+sw_error_t aquantia_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_GLOBAL_STANDARD_CONTROL1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	phy_data &= ~AQUANTIA_POWER_DOWN;
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS,
+		AQUANTIA_GLOBAL_STANDARD_CONTROL1,phy_data);
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_aquantia_phy_line_side_counter_get(a_uint32_t dev_id, a_uint32_t phy_id,
+			 fal_port_counter_info_t * counter_infor)
+{
+	a_uint16_t msw_counter;
+	a_uint16_t lsw_counter;
+	sw_error_t rv = SW_OK;
+
+	/*get line side tx good packets*/
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_LINE_SIDE_TRANSMIT_GOOD_FRAME_COUNTER2, &msw_counter);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_LINE_SIDE_TRANSMIT_GOOD_FRAME_COUNTER1, &lsw_counter);
+	SW_RTN_ON_ERROR(rv);
+	counter_infor->TxGoodFrame = (msw_counter << 16) | lsw_counter;
+
+	/*get line side tx bad packets*/
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_LINE_SIDE_TRANSMIT_ERROR_FRAME_COUNTER2, &msw_counter);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_LINE_SIDE_TRANSMIT_ERROR_FRAME_COUNTER1, &lsw_counter);
+	SW_RTN_ON_ERROR(rv);
+	counter_infor->TxBadCRC = (msw_counter << 16) | lsw_counter;
+
+	/*get line side rx good packets*/
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_LINE_SIDE_RECEIVE_GOOD_FRAME_COUNTER2, &msw_counter);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_LINE_SIDE_RECEIVE_GOOD_FRAME_COUNTER1, &lsw_counter);
+	SW_RTN_ON_ERROR(rv);
+	counter_infor->RxGoodFrame = (msw_counter << 16) | lsw_counter;
+
+	/*get line side rx bad packets*/
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_LINE_SIDE_RECEIVE_ERROR_FRAME_COUNTER2, &msw_counter);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_LINE_SIDE_RECEIVE_ERROR_FRAME_COUNTER1, &lsw_counter);
+	SW_RTN_ON_ERROR(rv);
+	counter_infor->RxBadCRC = (msw_counter << 16) | lsw_counter;
+
+	return rv;
+}
+
+static sw_error_t
+_aquantia_phy_system_side_counter_get(a_uint32_t dev_id, a_uint32_t phy_id,
+			 fal_port_counter_info_t * counter_infor)
+{
+	a_uint16_t msw_counter;
+	a_uint16_t lsw_counter;
+	sw_error_t rv = SW_OK;
+
+	/*get system tx good packets*/
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_SYSTEM_SIDE_TRANSMIT_GOOD_FRAME_COUNTER2, &msw_counter);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_SYSTEM_SIDE_TRANSMIT_GOOD_FRAME_COUNTER1, &lsw_counter);
+	SW_RTN_ON_ERROR(rv);
+	counter_infor->SysTxGoodFrame = (msw_counter << 16) | lsw_counter;
+
+	/*get system tx bad packets*/
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_SYSTEM_SIDE_TRANSMIT_ERROR_FRAME_COUNTER2, &msw_counter);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_SYSTEM_SIDE_TRANSMIT_ERROR_FRAME_COUNTER1, &lsw_counter);
+	SW_RTN_ON_ERROR(rv);
+	counter_infor->SysTxBadCRC = (msw_counter << 16) | lsw_counter;
+
+	/*get system rx good packets*/
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_SYSTEM_SIDE_RECEIVE_GOOD_FRAME_COUNTER2, &msw_counter);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_SYSTEM_SIDE_RECEIVE_GOOD_FRAME_COUNTER1, &lsw_counter);
+	SW_RTN_ON_ERROR(rv);
+	counter_infor->SysRxGoodFrame = (msw_counter << 16) | lsw_counter;
+
+	/*get system rx bad packets*/
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_SYSTEM_SIDE_RECEIVE_ERROR_FRAME_COUNTER2, &msw_counter);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_SYSTEM_SIDE_RECEIVE_ERROR_FRAME_COUNTER1, &lsw_counter);
+	SW_RTN_ON_ERROR(rv);
+	counter_infor->SysRxBadCRC = (msw_counter << 16) | lsw_counter;
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_show show counter statistics
+*
+* show counter statistics
+*/
+sw_error_t
+aquantia_phy_show_counter(a_uint32_t dev_id, a_uint32_t phy_id,
+			 fal_port_counter_info_t * counter_infor)
+{
+	sw_error_t rv = SW_OK;
+	fal_port_speed_t speed;
+
+	rv = aquantia_phy_get_speed(dev_id, phy_id, &speed);
+	SW_RTN_ON_ERROR(rv);
+	if(speed == FAL_SPEED_2500 || speed == FAL_SPEED_5000 || speed == FAL_SPEED_10000)
+	{
+		rv = _aquantia_phy_line_side_counter_get(dev_id, phy_id, counter_infor);
+		SW_RTN_ON_ERROR(rv);
+	}
+	rv = _aquantia_phy_system_side_counter_get(dev_id, phy_id, counter_infor);
+
+	return rv;
+}
+#endif
+/******************************************************************************
+*
+* aquantia_phy_get_status
+*
+* get phy status
+*/
+sw_error_t
+aquantia_phy_get_status(a_uint32_t dev_id, a_uint32_t phy_id,
+		struct port_phy_status *phy_status)
+{
+	sw_error_t rv = SW_OK;
+	a_uint16_t phy_data;
+
+	/*get phy link status*/
+	phy_status->link_status = aquantia_phy_get_link_status(dev_id, phy_id);
+	if(phy_status->link_status != A_TRUE)
+	{
+		return SW_OK;
+	}
+	/*get phy speed and duplex*/
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_REG_AUTONEG_VENDOR_STATUS, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	switch ((phy_data & AQUANTIA_STATUS_SPEED_MASK) >>1)
+	{
+		case AQUANTIA_STATUS_SPEED_100MBS:
+			phy_status->speed = FAL_SPEED_100;
+			break;
+		case AQUANTIA_STATUS_SPEED_1000MBS:
+			phy_status->speed = FAL_SPEED_1000;
+			break;
+		case AQUANTIA_STATUS_SPEED_2500MBS:
+			phy_status->speed = FAL_SPEED_2500;
+			break;
+		case AQUANTIA_STATUS_SPEED_5000MBS:
+			phy_status->speed = FAL_SPEED_5000;
+			break;
+		case AQUANTIA_STATUS_SPEED_10000MBS:
+			phy_status->speed = FAL_SPEED_10000;
+			break;
+		default:
+			return SW_READ_ERROR;
+	}
+	if (phy_data & AQUANTIA_STATUS_FULL_DUPLEX)
+	{
+		phy_status->duplex = FAL_FULL_DUPLEX;
+	}
+	else
+	{
+		phy_status->duplex = FAL_HALF_DUPLEX;
+	}
+	/* get phy tx flowctrl and rx flowctrl resolution status */
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_RESERVED_VENDOR_STATUS1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	if(phy_data & AQUANTIA_PHY_TX_FLOWCTRL_STATUS)
+	{
+		phy_status->tx_flowctrl = A_TRUE;
+	}
+	else
+	{
+		phy_status->tx_flowctrl = A_FALSE;
+	}
+	if(phy_data & AQUANTIA_PHY_RX_FLOWCTRL_STATUS)
+	{
+		phy_status->rx_flowctrl = A_TRUE;
+	}
+	else
+	{
+		phy_status->rx_flowctrl = A_FALSE;
+	}
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_set_eee_advertisement
+*
+* set eee advertisement
+*/
+sw_error_t
+aquantia_phy_set_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t adv)
+{
+	a_uint16_t phy_data = 0, phy_data1 = 0;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_EEE_ADVERTISTMENT_REGISTER, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_EEE_ADVERTISTMENT_REGISTER1, &phy_data1);
+	SW_RTN_ON_ERROR(rv);
+
+	phy_data &= ~(AQUANTIA_EEE_ADV_1000M | AQUANTIA_EEE_ADV_10000M);
+	if (adv & FAL_PHY_EEE_1000BASE_T) {
+		phy_data |= AQUANTIA_EEE_ADV_1000M;
+	}
+	if (adv & FAL_PHY_EEE_10000BASE_T) {
+		phy_data |= AQUANTIA_EEE_ADV_10000M;
+	}
+
+	phy_data1 &= ~(AQUANTIA_EEE_ADV_2500M | AQUANTIA_EEE_ADV_5000M);
+	if (adv & FAL_PHY_EEE_2500BASE_T) {
+		phy_data1 |= AQUANTIA_EEE_ADV_2500M;
+	}
+	if (adv & FAL_PHY_EEE_5000BASE_T) {
+		phy_data1 |= AQUANTIA_EEE_ADV_5000M;
+	}
+
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_EEE_ADVERTISTMENT_REGISTER, phy_data);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_EEE_ADVERTISTMENT_REGISTER1, phy_data1);
+	SW_RTN_ON_ERROR(rv);
+	rv = aquantia_phy_restart_autoneg(dev_id, phy_id);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_get_eee_advertisement
+*
+* get eee advertisement
+*/
+sw_error_t
+aquantia_phy_get_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *adv)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	*adv = 0;
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_EEE_ADVERTISTMENT_REGISTER, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+
+	if (phy_data & AQUANTIA_EEE_ADV_1000M) {
+		*adv |= FAL_PHY_EEE_1000BASE_T;
+	}
+	if (phy_data & AQUANTIA_EEE_ADV_10000M){
+		*adv |= FAL_PHY_EEE_10000BASE_T;
+	}
+	phy_data = 0;
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_EEE_ADVERTISTMENT_REGISTER1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+
+	if (phy_data & AQUANTIA_EEE_ADV_2500M) {
+		*adv |= FAL_PHY_EEE_2500BASE_T;
+	}
+	if (phy_data & AQUANTIA_EEE_ADV_5000M) {
+		*adv |= FAL_PHY_EEE_5000BASE_T;
+	}
+
+	return rv;
+}
+/******************************************************************************
+*
+* aquantia_phy_get_eee_partner_advertisement
+*
+* get eee partner advertisement
+*/
+sw_error_t
+aquantia_phy_get_eee_partner_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *adv)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	*adv = 0;
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_EEE_PARTNER_ADVERTISTMENT_REGISTER, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+
+	if (phy_data & AQUANTIA_EEE_PARTNER_ADV_1000M) {
+		*adv |= FAL_PHY_EEE_1000BASE_T;
+	}
+	if (phy_data & AQUANTIA_EEE_PARTNER_ADV_10000M){
+		*adv |= FAL_PHY_EEE_10000BASE_T;
+	}
+	phy_data = 0;
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG,
+		AQUANTIA_EEE_PARTNER_ADVERTISTMENT_REGISTER1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+
+	if (phy_data & AQUANTIA_EEE_PARTNER_ADV_2500M) {
+		*adv |= FAL_PHY_EEE_2500BASE_T;
+	}
+	if (phy_data & AQUANTIA_EEE_PARTNER_ADV_5000M) {
+		*adv |= FAL_PHY_EEE_5000BASE_T;
+	}
+
+	return rv;
+}
+/******************************************************************************
+*
+* aquantia_phy_get_eee_capability
+*
+* get eee capability
+*/
+sw_error_t
+aquantia_phy_get_eee_cap(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *cap)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	*cap = 0;
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_EEE_CAPABILITY_REGISTER, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+
+	if (phy_data & AQUANTIA_EEE_CAPABILITY_1000M) {
+		*cap |= FAL_PHY_EEE_1000BASE_T;
+	}
+	if (phy_data & AQUANTIA_EEE_CAPABILITY_10000M){
+		*cap |= FAL_PHY_EEE_10000BASE_T;
+	}
+	phy_data = 0;
+	rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS,
+		AQUANTIA_EEE_CAPABILITY_REGISTER1, &phy_data);
+	SW_RTN_ON_ERROR(rv);
+
+	if (phy_data & AQUANTIA_EEE_CAPABILITY_2500M) {
+		*cap |= FAL_PHY_EEE_2500BASE_T;
+	}
+	if (phy_data & AQUANTIA_EEE_CAPABILITY_5000M) {
+		*cap |= FAL_PHY_EEE_5000BASE_T;
+	}
+
+	return rv;
+}
+/******************************************************************************
+*
+* aquantia_phy_get_eee_status
+*
+* get eee status
+*/
+sw_error_t
+aquantia_phy_get_eee_status(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *status)
+{
+	a_uint32_t adv = 0, lp_adv = 0;
+	sw_error_t rv = SW_OK;
+
+	rv = aquantia_phy_get_eee_adv(dev_id, phy_id, &adv);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = aquantia_phy_get_eee_partner_adv(dev_id, phy_id, &lp_adv);
+	SW_RTN_ON_ERROR(rv);
+
+	*status = (adv & lp_adv);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_hw_register init to avoid packet loss
+*
+*/
+sw_error_t
+aquantia_phy_hw_init(a_uint32_t dev_id,  a_uint32_t port_bmp)
+{
+	a_uint16_t phy_data = 0;
+	a_uint32_t port_id = 0, phy_addr = 0;
+	sw_error_t rv = SW_OK;
+
+	for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++)
+	{
+		if (port_bmp & (0x1 << port_id))
+		{
+			phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id);
+			/*set auto neg of aq*/
+			rv = aquantia_phy_reg_read(dev_id, phy_addr, AQUANTIA_MMD_PHY_XS_REGISTERS,
+				AQUANTIA_PHY_XS_USX_TRANSMIT, &phy_data);
+			SW_RTN_ON_ERROR(rv);
+			phy_data |= AQUANTIA_PHY_USX_AUTONEG_ENABLE;
+			rv = aquantia_phy_reg_write(dev_id, phy_addr, AQUANTIA_MMD_PHY_XS_REGISTERS,
+				AQUANTIA_PHY_XS_USX_TRANSMIT,phy_data);
+			SW_RTN_ON_ERROR(rv);
+			/*config interrupt of aq*/
+			rv = aquantia_phy_reg_read(dev_id, phy_addr, AQUANTIA_MMD_AUTONEG,
+				AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK, &phy_data);
+			SW_RTN_ON_ERROR(rv);
+			phy_data |= AQUANTIA_INTR_LINK_STATUS_CHANGE;
+			rv = aquantia_phy_reg_write(dev_id, phy_addr, AQUANTIA_MMD_AUTONEG,
+				AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK, phy_data);
+			SW_RTN_ON_ERROR(rv);
+			rv = aquantia_phy_reg_read(dev_id, phy_addr, AQUANTIA_MMD_GLOBAL_REGISTERS,
+				AQUANTIA_GLOBAL_INTR_STANDARD_MASK, &phy_data);
+			SW_RTN_ON_ERROR(rv);
+			phy_data |= AQUANTIA_ALL_VENDOR_ALARMS_INTR_MASK;
+			rv = aquantia_phy_reg_write(dev_id, phy_addr, AQUANTIA_MMD_GLOBAL_REGISTERS,
+				AQUANTIA_GLOBAL_INTR_STANDARD_MASK, phy_data);
+			SW_RTN_ON_ERROR(rv);
+			rv = aquantia_phy_reg_read(dev_id, phy_addr, AQUANTIA_MMD_GLOBAL_REGISTERS,
+				AQUANTIA_GLOBAL_INTR_VENDOR_MASK, &phy_data);
+			SW_RTN_ON_ERROR(rv);
+			phy_data |= AQUANTIA_AUTO_AND_ALARMS_INTR_MASK;
+			rv = aquantia_phy_reg_write(dev_id, phy_addr, AQUANTIA_MMD_GLOBAL_REGISTERS,
+				AQUANTIA_GLOBAL_INTR_VENDOR_MASK, phy_data);
+			SW_RTN_ON_ERROR(rv);
+
+			/* config aq phy ACT and LINK led behavior*/
+			phy_data = AQUANTIA_ACT_LED_VALUE;
+			rv = aquantia_phy_reg_write(dev_id, phy_addr, AQUANTIA_MMD_GLOBAL_REGISTERS,
+				AQUANTIA_ACT_LED_STATUS, phy_data);
+			SW_RTN_ON_ERROR(rv);
+			phy_data = AQUANTIA_LINK_LED_VALUE;
+			rv = aquantia_phy_reg_write(dev_id, phy_addr, AQUANTIA_MMD_GLOBAL_REGISTERS,
+				AQUANTIA_LINK_LED_STATUS, phy_data);
+			SW_RTN_ON_ERROR(rv);
+			/*add all ability of aq phy*/
+			rv = aquantia_phy_set_autoneg_adv(dev_id, phy_addr,
+				FAL_PHY_ADV_XGE_SPEED_ALL | FAL_PHY_ADV_100TX_FD |
+				FAL_PHY_ADV_1000T_FD);
+			SW_RTN_ON_ERROR(rv);
+#if 0
+			rv = aquantia_phy_set_eee_adv(dev_id, phy_addr, FAL_PHY_EEE_1000BASE_T
+				| FAL_PHY_EEE_2500BASE_T | FAL_PHY_EEE_5000BASE_T |
+				FAL_PHY_EEE_10000BASE_T);
+			SW_RTN_ON_ERROR(rv);
+#endif
+		}
+	}
+
+	return rv;
+}
+
+static int aquantia_phy_api_ops_init(void)
+{
+	int ret;
+	hsl_phy_ops_t *aquantia_phy_api_ops = NULL;
+
+	aquantia_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL);
+	if (aquantia_phy_api_ops == NULL) {
+		SSDK_ERROR("aquantia phy ops kzalloc failed!\n");
+		return -ENOMEM;
+	}
+
+	phy_api_ops_init(AQUANTIA_PHY_CHIP);
+
+	aquantia_phy_api_ops->phy_speed_get = aquantia_phy_get_speed;
+	aquantia_phy_api_ops->phy_speed_set = aquantia_phy_set_speed;
+	aquantia_phy_api_ops->phy_duplex_get = aquantia_phy_get_duplex;
+	aquantia_phy_api_ops->phy_duplex_set = aquantia_phy_set_duplex;
+	aquantia_phy_api_ops->phy_autoneg_enable_set = aquantia_phy_enable_autoneg;
+	aquantia_phy_api_ops->phy_restart_autoneg = aquantia_phy_restart_autoneg;
+	aquantia_phy_api_ops->phy_autoneg_status_get = aquantia_phy_autoneg_status;
+	aquantia_phy_api_ops->phy_autoneg_adv_set = aquantia_phy_set_autoneg_adv;
+	aquantia_phy_api_ops->phy_autoneg_adv_get = aquantia_phy_get_autoneg_adv;
+#ifndef IN_PORTCONTROL_MINI
+	aquantia_phy_api_ops->phy_powersave_set = aquantia_phy_set_powersave;
+	aquantia_phy_api_ops->phy_powersave_get = aquantia_phy_get_powersave;
+	aquantia_phy_api_ops->phy_8023az_set = aquantia_phy_set_8023az;
+	aquantia_phy_api_ops->phy_8023az_get = aquantia_phy_get_8023az;
+#endif
+	aquantia_phy_api_ops->phy_power_on = aquantia_phy_poweron;
+	aquantia_phy_api_ops->phy_power_off = aquantia_phy_poweroff;
+#ifndef IN_PORTCONTROL_MINI
+	aquantia_phy_api_ops->phy_cdt = aquantia_phy_cdt;
+#endif
+	aquantia_phy_api_ops->phy_link_status_get = aquantia_phy_get_link_status;
+#ifndef IN_PORTCONTROL_MINI
+	aquantia_phy_api_ops->phy_mdix_set = aquantia_phy_set_mdix;
+	aquantia_phy_api_ops->phy_mdix_get = aquantia_phy_get_mdix;
+	aquantia_phy_api_ops->phy_mdix_status_get = aquantia_phy_get_mdix_status;
+	aquantia_phy_api_ops->phy_local_loopback_set = aquantia_phy_set_local_loopback;
+	aquantia_phy_api_ops->phy_local_loopback_get = aquantia_phy_get_local_loopback;
+	aquantia_phy_api_ops->phy_remote_loopback_set = aquantia_phy_set_remote_loopback;
+	aquantia_phy_api_ops->phy_remote_loopback_get = aquantia_phy_get_remote_loopback;
+	aquantia_phy_api_ops->phy_reset = aquantia_phy_reset;
+	aquantia_phy_api_ops->phy_wol_status_set = aquantia_phy_set_wol_status;
+	aquantia_phy_api_ops->phy_wol_status_get = aquantia_phy_get_wol_status;
+	aquantia_phy_api_ops->phy_magic_frame_mac_get = aquantia_phy_get_magic_frame_mac;
+	aquantia_phy_api_ops->phy_magic_frame_mac_set = aquantia_phy_set_magic_frame_mac;
+	aquantia_phy_api_ops->phy_intr_mask_set = aquantia_phy_intr_mask_set;
+	aquantia_phy_api_ops->phy_intr_mask_get = aquantia_phy_intr_mask_get;
+	aquantia_phy_api_ops->phy_id_get = aquantia_phy_get_phy_id;
+#endif
+	aquantia_phy_api_ops->phy_interface_mode_set = aquantia_phy_interface_set_mode;
+	aquantia_phy_api_ops->phy_interface_mode_status_get=aquantia_phy_interface_get_mode_status;
+	aquantia_phy_api_ops->phy_get_status = aquantia_phy_get_status;
+#ifndef IN_PORTCONTROL_MINI
+	aquantia_phy_api_ops->phy_counter_show = aquantia_phy_show_counter;
+#endif
+	aquantia_phy_api_ops->phy_eee_adv_set = aquantia_phy_set_eee_adv;
+	aquantia_phy_api_ops->phy_eee_adv_get = aquantia_phy_get_eee_adv;
+	aquantia_phy_api_ops->phy_eee_partner_adv_get = aquantia_phy_get_eee_partner_adv;
+	aquantia_phy_api_ops->phy_eee_cap_get = aquantia_phy_get_eee_cap;
+	aquantia_phy_api_ops->phy_eee_status_get = aquantia_phy_get_eee_status;
+	ret = hsl_phy_api_ops_register(AQUANTIA_PHY_CHIP, aquantia_phy_api_ops);
+	if (ret == 0)
+		SSDK_INFO("qca probe aquantia phy driver succeeded!\n");
+	else
+		SSDK_ERROR("qca probe aquantia phy driver failed! (code: %d)\n", ret);
+
+	return ret;
+}
+
+/******************************************************************************
+*
+* aquantia_phy_init -
+*
+*/
+int aquantia_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp)
+{
+	static a_uint32_t phy_ops_flag = 0;
+
+	if(phy_ops_flag == 0) {
+		aquantia_phy_api_ops_init();
+		phy_ops_flag = 1;
+	}
+	aquantia_phy_hw_init(dev_id, port_bmp);
+
+	return 0;
+
+}
+
diff --git a/qca-ssdk/src/hsl/phy/f1_phy.c b/qca-ssdk/src/hsl/phy/f1_phy.c
new file mode 100755
index 0000000..b3017b0
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/f1_phy.c
@@ -0,0 +1,1534 @@
+/*
+ * Copyright (c) 2012, 2015-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "fal_port_ctrl.h"
+#include "hsl_api.h"
+#include "hsl.h"
+#include "f1_phy.h"
+#include "hsl_phy.h"
+#include "ssdk_plat.h"
+
+static a_uint16_t
+_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg)
+{
+    sw_error_t rv;
+    a_uint16_t val = 0;
+
+    HSL_PHY_GET(rv, dev_id, phy_addr, reg, &val);
+    if (SW_OK != rv)
+        return 0xFFFF;
+
+    return val;
+}
+
+static sw_error_t
+_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
+               a_uint16_t val)
+{
+    sw_error_t rv;
+
+    HSL_PHY_SET(rv, dev_id, phy_addr, reg, val);
+
+    return rv;
+}
+
+/* #define f1_phy_reg_read _phy_reg_read */
+/* #define f1_phy_reg_write _phy_reg_write */
+
+/******************************************************************************
+*
+* f1_phy_mii_read - mii register read
+*
+* mil register read
+*/
+a_uint16_t
+f1_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id)
+{
+ 	return _phy_reg_read(dev_id, phy_id, reg_id);
+
+}
+
+/******************************************************************************
+*
+* f1_phy_reg_write - mii register write
+*
+* mii register write
+*/
+sw_error_t
+f1_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id,
+		       a_uint16_t reg_val)
+{
+
+       _phy_reg_write(dev_id,phy_id, reg_id, reg_val);
+
+	return SW_OK;
+}
+
+
+/******************************************************************************
+*
+* f1_phy_debug_write - debug port write
+*
+* debug port write
+*/
+sw_error_t
+f1_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id,
+                   a_uint16_t reg_val)
+{
+    f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, reg_id);
+    f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_DATA, reg_val);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_debug_read - debug port read
+*
+* debug port read
+*/
+a_uint16_t
+f1_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id)
+{
+    f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, reg_id);
+    return f1_phy_reg_read(dev_id, phy_id, F1_DEBUG_PORT_DATA);
+}
+
+/******************************************************************************
+*
+* f1_phy_mmd_write - PHY MMD register write
+*
+* PHY MMD register write
+*/
+sw_error_t
+f1_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id,
+                 a_uint16_t mmd_num,
+                 a_uint16_t reg_id,
+                 a_uint16_t reg_val)
+{
+    f1_phy_reg_write(dev_id, phy_id, F1_MMD_CTRL_REG, mmd_num);
+    f1_phy_reg_write(dev_id, phy_id, F1_MMD_DATA_REG, reg_id);
+    f1_phy_reg_write(dev_id, phy_id, F1_MMD_CTRL_REG, 0x4000|mmd_num);
+    f1_phy_reg_write(dev_id, phy_id, F1_MMD_DATA_REG, reg_val);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_mmd_read -  PHY MMD register read
+*
+* PHY MMD register read
+*/
+a_uint16_t
+f1_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id,
+                  a_uint16_t mmd_num,
+                  a_uint16_t reg_id)
+{
+    f1_phy_reg_write(dev_id, phy_id, F1_MMD_CTRL_REG, mmd_num);
+    f1_phy_reg_write(dev_id, phy_id, F1_MMD_DATA_REG, reg_id);
+    f1_phy_reg_write(dev_id, phy_id, F1_MMD_CTRL_REG, 0x4000|mmd_num);
+
+    return f1_phy_reg_read(dev_id, phy_id, F1_MMD_DATA_REG);
+}
+
+
+/******************************************************************************
+*
+* f1_phy_set_powersave - set power saving status
+*
+* set power saving status
+*/
+sw_error_t
+f1_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+    a_uint16_t phy_data;
+    f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, 0x29);
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_DEBUG_PORT_DATA);
+
+    if(enable == A_TRUE)
+    {
+        phy_data |= 0x8000;
+    }
+    else
+    {
+        phy_data &= ~0x8000;
+    }
+
+    f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_DATA, phy_data);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_get_powersave - get power saving status
+*
+* set power saving status
+*/
+sw_error_t
+f1_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable)
+{
+    a_uint16_t phy_data;
+    *enable = A_FALSE;
+
+    f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, 0x29);
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_DEBUG_PORT_DATA);
+
+    if(phy_data & 0x8000)
+        *enable =  A_TRUE;
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_set_hibernate - set hibernate status
+*
+* set hibernate status
+*/
+sw_error_t
+f1_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+    a_uint16_t phy_data;
+    f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, 0xb);
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_DEBUG_PORT_DATA);
+
+    if(enable == A_TRUE)
+    {
+        phy_data |= 0x8000;
+    }
+    else
+    {
+        phy_data &= ~0x8000;
+    }
+
+    f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_DATA, phy_data);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_get_hibernate - get hibernate status
+*
+* get hibernate status
+*/
+sw_error_t
+f1_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable)
+{
+    a_uint16_t phy_data;
+    *enable = A_FALSE;
+
+    f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, 0xb);
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_DEBUG_PORT_DATA);
+
+    if(phy_data & 0x8000)
+        *enable =  A_TRUE;
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_cdt - cable diagnostic test
+*
+* cable diagnostic test
+*/
+#ifdef ISISC
+#define RUN_CDT 0x8000
+#define CABLE_LENGTH_UNIT 0x0400
+sw_error_t f1_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id);
+a_bool_t f1_phy_reset_done(a_uint32_t dev_id, a_uint32_t phy_id);
+a_bool_t f1_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id);
+
+static inline fal_cable_status_t
+_fal_cdt_status_mapping(a_uint16_t status)
+{
+    fal_cable_status_t status_mapping = FAL_CABLE_STATUS_INVALID;
+
+    if (0 == status)
+        status_mapping = FAL_CABLE_STATUS_INVALID;
+    else if (1 == status)
+        status_mapping = FAL_CABLE_STATUS_NORMAL;
+    else if (2 == status)
+        status_mapping = FAL_CABLE_STATUS_OPENED;
+    else if (3 == status)
+        status_mapping = FAL_CABLE_STATUS_SHORT;
+    
+    return status_mapping;
+}
+
+static sw_error_t
+f1_phy_cdt_start(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t status = 0;
+    a_uint16_t ii = 100;
+
+    /* RUN CDT */
+    f1_phy_reg_write(dev_id, phy_id, F1_PHY_CDT_CONTROL, RUN_CDT|CABLE_LENGTH_UNIT);
+    do
+    {
+        aos_mdelay(30);
+        status = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CDT_CONTROL);
+    }
+    while ((status & RUN_CDT) && (--ii));
+
+    return SW_OK;
+}
+
+sw_error_t
+f1_phy_cdt_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_cdt_t *port_cdt)
+{
+    a_uint16_t status = 0;
+    a_uint16_t cable_delta_time = 0;
+    a_uint16_t org_debug_value = 0;
+    int ii = 100;
+    a_bool_t link_st = A_FALSE;
+    a_uint16_t reg806e = 0;
+    int i;
+
+    if((!port_cdt) || (phy_id > 4))
+    {
+        return SW_FAIL;
+    }
+
+    /*disable clock gating*/
+    org_debug_value = f1_phy_debug_read(dev_id, phy_id, 0x3f);
+    f1_phy_debug_write(dev_id, phy_id, 0x3f, 0);
+
+    f1_phy_cdt_start(dev_id, phy_id);
+
+    /* Get cable status */
+    status = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8064);
+
+    /* Workaround for cable lenth less than 20M  */
+    port_cdt->pair_c_status = (status >> 4) & 0x3;
+    /* Get Cable Length value */
+    cable_delta_time = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8067);
+    /* the actual cable length equals to CableDeltaTime * 0.824*/
+    port_cdt->pair_c_len = (cable_delta_time * 824) /1000;
+    if ((1 == port_cdt->pair_c_status) &&
+        (port_cdt->pair_c_len > 0) && (port_cdt->pair_c_len <= 20))
+    {
+        reg806e = f1_phy_mmd_read(dev_id, phy_id, 3, 0x806e);
+	f1_phy_mmd_write(dev_id, phy_id, 3, 0x806e, reg806e & (~0x8000));
+
+        f1_phy_reset(dev_id, phy_id);
+        f1_phy_reset_done(dev_id, phy_id);
+	do
+        {
+            link_st = f1_phy_get_link_status(dev_id, phy_id);
+	    aos_mdelay(100);
+        } while ((A_FALSE == link_st) && (--ii));
+
+	f1_phy_cdt_start(dev_id, phy_id);
+        /* Get cable status */
+        status = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8064);
+    }
+
+    for (i=0;i<4;i++)
+    {
+        switch(i)
+        {
+            case 0:
+                port_cdt->pair_a_status = (status >> 12) & 0x3;
+                /* Get Cable Length value */
+                cable_delta_time = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8065);
+                /* the actual cable length equals to CableDeltaTime * 0.824*/
+                port_cdt->pair_a_len = (cable_delta_time * 824) /1000;
+
+                break;
+            case 1:
+                port_cdt->pair_b_status = (status >> 8) & 0x3;
+                /* Get Cable Length value */
+                cable_delta_time = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8066);
+                /* the actual cable length equals to CableDeltaTime * 0.824*/
+                port_cdt->pair_b_len = (cable_delta_time * 824) /1000;
+                break;
+            case 2:
+                port_cdt->pair_c_status = (status >> 4) & 0x3;
+                /* Get Cable Length value */
+                cable_delta_time = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8067);
+                /* the actual cable length equals to CableDeltaTime * 0.824*/
+                port_cdt->pair_c_len = (cable_delta_time * 824) /1000;
+                break;
+            case 3:
+                port_cdt->pair_d_status = status & 0x3;
+                /* Get Cable Length value */
+                cable_delta_time = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8068);
+                /* the actual cable length equals to CableDeltaTime * 0.824*/
+                port_cdt->pair_d_len = (cable_delta_time * 824) /1000;
+                break;
+            default:
+                break;
+        }
+    }
+
+    /*restore debug port value*/
+    f1_phy_debug_write(dev_id, phy_id, 0x3f, org_debug_value);
+
+    return SW_OK;
+}
+
+sw_error_t
+f1_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+           fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+    fal_port_cdt_t f1_port_cdt;
+
+    if((mdi_pair >= 4) || (phy_id > 4))
+    {
+        //There are only 4 mdi pairs in 1000BASE-T
+        return SW_BAD_PARAM;
+    }
+
+    f1_phy_cdt_get(dev_id, phy_id, &f1_port_cdt);
+
+    switch(mdi_pair)
+    {
+        case 0:
+            *cable_status = _fal_cdt_status_mapping(f1_port_cdt.pair_a_status);
+            /* Get Cable Length value */
+	    *cable_len = f1_port_cdt.pair_a_len;
+            break;
+        case 1:
+            *cable_status = _fal_cdt_status_mapping(f1_port_cdt.pair_b_status);
+            /* Get Cable Length value */
+	    *cable_len = f1_port_cdt.pair_b_len;
+            break;
+        case 2:
+            *cable_status = _fal_cdt_status_mapping(f1_port_cdt.pair_c_status);
+            /* Get Cable Length value */
+	    *cable_len = f1_port_cdt.pair_c_len;
+            break;
+        case 3:
+            *cable_status = _fal_cdt_status_mapping(f1_port_cdt.pair_d_status);
+            /* Get Cable Length value */
+	    *cable_len = f1_port_cdt.pair_d_len;
+            break;
+        default:
+            break;
+    }
+
+    return SW_OK;
+}
+#else
+sw_error_t
+f1_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+           fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+    a_uint16_t status = 0;
+    a_uint16_t ii = 100;
+    a_uint16_t org_debug_value;
+    a_uint16_t cable_delta_time;
+
+    if(!cable_status || !cable_len)
+    {
+        return SW_FAIL;
+    }
+
+    if(mdi_pair >= 4)
+    {
+        //There are only 4 mdi pairs in 1000BASE-T
+        return SW_BAD_PARAM;
+    }
+
+    org_debug_value = f1_phy_debug_read(dev_id, phy_id, 0x3f);
+
+    /*disable clock gating*/
+    f1_phy_debug_write(dev_id, phy_id, 0x3f, 0);
+    f1_phy_reg_write(dev_id, phy_id, F1_PHY_CDT_CONTROL, (mdi_pair << 8) | 0x0001);
+
+    do
+    {
+        aos_mdelay(30);
+        status = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CDT_CONTROL);
+    }
+    while ((status & 0x0001) && (--ii));
+
+    status = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CDT_STATUS);
+
+    *cable_status = (status&0x300) >> 8;
+    if ( (*cable_status == 1) || (*cable_status == 2))
+    {
+        if ( mdi_pair == 1 || mdi_pair == 3 )
+        {
+            /*Reverse the mdi status for channel 1 and channel 3*/
+            *cable_status = (~(*cable_status)) & 0x3;
+        }
+    }
+
+    /* the actual cable length equals to CableDeltaTime * 0.824*/
+     cable_delta_time = status & 0xff;
+    *cable_len = (cable_delta_time * 824) /1000;
+
+    /*restore debug port value*/
+    f1_phy_debug_write(dev_id, phy_id, 0x3f, org_debug_value);
+    //f1_phy_reg_write(dev_id, phy_id, 0x00, 0x9000);//Reset the PHY if necessary
+
+    return SW_OK;
+}
+#endif
+
+/******************************************************************************
+*
+* f1_phy_reset_done - reset the phy
+*
+* reset the phy
+*/
+a_bool_t
+f1_phy_reset_done(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+    a_uint16_t ii = 200;
+
+    do
+    {
+        phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+        aos_mdelay(10);
+    }
+    while ((!F1_RESET_DONE(phy_data)) && --ii);
+
+    if (ii == 0)
+        return A_FALSE;
+
+    return A_TRUE;
+}
+
+/******************************************************************************
+*
+* f1_autoneg_done
+*
+* f1_autoneg_done
+*/
+a_bool_t
+f1_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+    a_uint16_t ii = 200;
+
+    do
+    {
+        phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_STATUS);
+        aos_mdelay(10);
+    }
+    while ((!F1_AUTONEG_DONE(phy_data)) && --ii);
+
+    if (ii == 0)
+        return A_FALSE;
+
+    return A_TRUE;
+}
+
+/******************************************************************************
+*
+* f1_phy_Speed_Duplex_Resolved
+ - reset the phy
+*
+* reset the phy
+*/
+a_bool_t
+f1_phy_speed_duplex_resolved(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+    a_uint16_t ii = 200;
+
+    do
+    {
+        phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_SPEC_STATUS);
+        aos_mdelay(10);
+    }
+    while ((!F1_SPEED_DUPLEX_RESOVLED(phy_data)) && --ii);
+
+    if (ii == 0)
+        return A_FALSE;
+
+    return A_TRUE;
+}
+
+/******************************************************************************
+*
+* f1_phy_reset - reset the phy
+*
+* reset the phy
+*/
+sw_error_t
+f1_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+    f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL,
+                     phy_data | F1_CTRL_SOFTWARE_RESET);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_off - power off the phy to change its speed
+*
+* Power off the phy
+*/
+sw_error_t
+f1_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+    f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL,
+                     phy_data | F1_CTRL_POWER_DOWN);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_on - power on the phy after speed changed
+*
+* Power on the phy
+*/
+sw_error_t
+f1_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+    f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL,
+                     phy_data & ~F1_CTRL_POWER_DOWN);
+
+    aos_mdelay(200);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_get_ability - get the phy ability
+*
+*
+*/
+sw_error_t
+f1_phy_get_ability(a_uint32_t dev_id, a_uint32_t phy_id,
+                   a_uint32_t * ability)
+{
+    a_uint16_t phy_data;
+
+    *ability = 0;
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_STATUS);
+
+    if (phy_data & F1_STATUS_AUTONEG_CAPS)
+        *ability |= FAL_PHY_AUTONEG_CAPS;
+
+    if (phy_data & F1_STATUS_100T2_HD_CAPS)
+        *ability |= FAL_PHY_100T2_HD_CAPS;
+
+    if (phy_data & F1_STATUS_100T2_FD_CAPS)
+        *ability |= FAL_PHY_100T2_FD_CAPS;
+
+    if (phy_data & F1_STATUS_10T_HD_CAPS)
+        *ability |= FAL_PHY_10T_HD_CAPS;
+
+    if (phy_data & F1_STATUS_10T_FD_CAPS)
+        *ability |= FAL_PHY_10T_FD_CAPS;
+
+    if (phy_data & F1_STATUS_100X_HD_CAPS)
+        *ability |= FAL_PHY_100X_HD_CAPS;
+
+    if (phy_data & F1_STATUS_100X_FD_CAPS)
+        *ability |= FAL_PHY_100X_FD_CAPS;
+
+    if (phy_data & F1_STATUS_100T4_CAPS)
+        *ability |= FAL_PHY_100T4_CAPS;
+
+    if (phy_data & F1_STATUS_EXTENDED_STATUS)
+    {
+        phy_data = f1_phy_reg_read(dev_id, phy_id, F1_EXTENDED_STATUS);
+
+        if (phy_data & F1_STATUS_1000T_FD_CAPS)
+        {
+            *ability |= FAL_PHY_1000T_FD_CAPS;
+        }
+
+        if (phy_data & F1_STATUS_1000X_FD_CAPS)
+        {
+            *ability |= FAL_PHY_1000X_FD_CAPS;
+        }
+    }
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_get_ability - get the phy ability
+*
+*
+*/
+sw_error_t
+f1_phy_get_partner_ability(a_uint32_t dev_id, a_uint32_t phy_id,
+                           a_uint32_t * ability)
+{
+    a_uint16_t phy_data;
+
+    *ability = 0;
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_LINK_PARTNER_ABILITY);
+
+    if (phy_data & F1_LINK_10BASETX_HALF_DUPLEX)
+        *ability |= FAL_PHY_PART_10T_HD;
+
+    if (phy_data & F1_LINK_10BASETX_FULL_DUPLEX)
+        *ability |= FAL_PHY_PART_10T_FD;
+
+    if (phy_data & F1_LINK_100BASETX_HALF_DUPLEX)
+        *ability |= FAL_PHY_PART_100TX_HD;
+
+    if (phy_data & F1_LINK_100BASETX_FULL_DUPLEX)
+        *ability |= FAL_PHY_PART_100TX_FD;
+
+    if (phy_data & F1_LINK_NPAGE)
+    {
+        phy_data = f1_phy_reg_read(dev_id, phy_id, F1_1000BASET_STATUS);
+
+        if (phy_data & F1_LINK_1000BASETX_FULL_DUPLEX)
+            *ability |= FAL_PHY_PART_1000T_FD;
+    }
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_status - test to see if the specified phy link is alive
+*
+* RETURNS:
+*    A_TRUE  --> link is alive
+*    A_FALSE --> link is down
+*/
+a_bool_t
+f1_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_SPEC_STATUS);
+
+    if (phy_data & F1_STATUS_LINK_PASS)
+        return A_TRUE;
+
+    return A_FALSE;
+}
+
+/******************************************************************************
+*
+* f1_set_autoneg_adv - set the phy autoneg Advertisement
+*
+*/
+sw_error_t
+f1_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+                       a_uint32_t autoneg)
+{
+    a_uint16_t phy_data = 0;
+
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_AUTONEG_ADVERT);
+    phy_data &= ~F1_ADVERTISE_MEGA_ALL;
+    phy_data &= ~(F1_ADVERTISE_PAUSE | F1_ADVERTISE_ASYM_PAUSE);
+
+    if (autoneg & FAL_PHY_ADV_100TX_FD)
+        phy_data |= F1_ADVERTISE_100FULL;
+
+    if (autoneg & FAL_PHY_ADV_100TX_HD)
+        phy_data |= F1_ADVERTISE_100HALF;
+
+    if (autoneg & FAL_PHY_ADV_10T_FD)
+        phy_data |= F1_ADVERTISE_10FULL;
+
+    if (autoneg & FAL_PHY_ADV_10T_HD)
+        phy_data |= F1_ADVERTISE_10HALF;
+
+    if (autoneg & FAL_PHY_ADV_PAUSE)
+        phy_data |= F1_ADVERTISE_PAUSE;
+
+    if (autoneg & FAL_PHY_ADV_ASY_PAUSE)
+        phy_data |= F1_ADVERTISE_ASYM_PAUSE;
+
+    f1_phy_reg_write(dev_id, phy_id, F1_AUTONEG_ADVERT, phy_data);
+
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_1000BASET_CONTROL);
+    phy_data &= ~F1_ADVERTISE_1000FULL;
+    phy_data &= ~F1_ADVERTISE_1000HALF;
+
+    if (autoneg & FAL_PHY_ADV_1000T_FD)
+        phy_data |= F1_ADVERTISE_1000FULL;
+
+    f1_phy_reg_write(dev_id, phy_id, F1_1000BASET_CONTROL, phy_data);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_get_autoneg_adv - get the phy autoneg Advertisement
+*
+*/
+sw_error_t
+f1_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+                       a_uint32_t * autoneg)
+{
+    a_uint16_t phy_data = 0;
+
+    *autoneg = 0;
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_AUTONEG_ADVERT);
+
+    if (phy_data & F1_ADVERTISE_100FULL)
+        *autoneg |= FAL_PHY_ADV_100TX_FD;
+
+    if (phy_data & F1_ADVERTISE_100HALF)
+        *autoneg |= FAL_PHY_ADV_100TX_HD;
+
+    if (phy_data & F1_ADVERTISE_10FULL)
+        *autoneg |= FAL_PHY_ADV_10T_FD;
+
+    if (phy_data & F1_ADVERTISE_10HALF)
+        *autoneg |= FAL_PHY_ADV_10T_HD;
+
+    if (phy_data & F1_ADVERTISE_PAUSE)
+        *autoneg |= FAL_PHY_ADV_PAUSE;
+
+    if (phy_data & F1_ADVERTISE_ASYM_PAUSE)
+        *autoneg |= FAL_PHY_ADV_ASY_PAUSE;
+
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_1000BASET_CONTROL);
+
+    if (phy_data & F1_ADVERTISE_1000FULL)
+        *autoneg |= FAL_PHY_ADV_1000T_FD;
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_enable_autonego - power off the phy to change its speed
+*
+* Power off the phy
+*/
+a_bool_t
+f1_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+
+    if (phy_data & F1_CTRL_AUTONEGOTIATION_ENABLE)
+        return A_TRUE;
+
+    return A_FALSE;
+}
+
+/******************************************************************************
+*
+* f1_restart_autoneg - restart the phy autoneg
+*
+*/
+sw_error_t
+f1_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data = 0;
+
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+
+    phy_data |= F1_CTRL_AUTONEGOTIATION_ENABLE;
+    f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL,
+                     phy_data | F1_CTRL_RESTART_AUTONEGOTIATION);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_enable_autonego - power off the phy to change its speed
+*
+* Power off the phy
+*/
+sw_error_t
+f1_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data = 0;
+
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+
+    f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL,
+                     phy_data | F1_CTRL_AUTONEGOTIATION_ENABLE);
+
+    return SW_OK;
+}
+
+
+/******************************************************************************
+*
+* f1_phy_get_speed - Determines the speed of phy ports associated with the
+* specified device.
+*/
+
+sw_error_t
+f1_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+                 fal_port_speed_t * speed)
+{
+	a_uint16_t phy_data;
+	a_bool_t auto_neg;
+
+	auto_neg = f1_phy_autoneg_status(dev_id, phy_id);
+	if (A_TRUE == auto_neg ) {
+		phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_SPEC_STATUS);
+		switch (phy_data & F1_STATUS_SPEED_MASK)
+    		{
+			case F1_STATUS_SPEED_1000MBS:
+				*speed = FAL_SPEED_1000;
+				break;
+			case F1_STATUS_SPEED_100MBS:
+				*speed = FAL_SPEED_100;
+				break;
+			case F1_STATUS_SPEED_10MBS:
+				*speed = FAL_SPEED_10;
+				break;
+			default:
+				return SW_READ_ERROR;
+		}
+	}
+	else
+	{
+		phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+		switch (phy_data & F1_CTRL_SPEED_MASK)
+    		{
+			case F1_CTRL_SPEED_1000:
+				*speed = FAL_SPEED_1000;
+				break;
+			case F1_CTRL_SPEED_100:
+				*speed = FAL_SPEED_100;
+				break;
+			case F1_CTRL_SPEED_10:
+				*speed = FAL_SPEED_10;
+				break;
+			default:
+				return SW_READ_ERROR;
+		}
+	}
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_set_speed - Determines the speed of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+f1_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+                 fal_port_speed_t speed)
+{
+    a_uint16_t phy_data = 0;
+    a_uint16_t phy_status = 0;
+
+    a_uint32_t autoneg, oldneg;
+    fal_port_duplex_t old_duplex;
+
+    if (FAL_SPEED_1000 == speed)
+    {
+        phy_data |= F1_CTRL_SPEED_1000;
+	phy_data |= F1_CTRL_AUTONEGOTIATION_ENABLE;
+    }
+    else if (FAL_SPEED_100 == speed)
+    {
+        phy_data |= F1_CTRL_SPEED_100;
+	phy_data &= ~F1_CTRL_AUTONEGOTIATION_ENABLE;
+    }
+    else if (FAL_SPEED_10 == speed)
+    {
+        phy_data |= F1_CTRL_SPEED_10;
+	phy_data &= ~F1_CTRL_AUTONEGOTIATION_ENABLE;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    (void)f1_phy_get_autoneg_adv(dev_id, phy_id, &autoneg);
+    oldneg = autoneg;
+    autoneg &= ~FAL_PHY_ADV_GE_SPEED_ALL;
+
+    (void)f1_phy_get_duplex(dev_id, phy_id, &old_duplex);
+
+    if (old_duplex == FAL_FULL_DUPLEX)
+    {
+        phy_data |= F1_CTRL_FULL_DUPLEX;
+
+        if (FAL_SPEED_1000 == speed)
+        {
+            autoneg |= FAL_PHY_ADV_1000T_FD;
+        }
+        else if (FAL_SPEED_100 == speed)
+        {
+            autoneg |= FAL_PHY_ADV_100TX_FD;
+        }
+        else
+        {
+            autoneg |= FAL_PHY_ADV_10T_FD;
+        }
+    }
+    else if (old_duplex == FAL_HALF_DUPLEX)
+    {
+        phy_data &= ~F1_CTRL_FULL_DUPLEX;
+
+        if (FAL_SPEED_100 == speed)
+        {
+            autoneg |= FAL_PHY_ADV_100TX_HD;
+        }
+        else
+        {
+            autoneg |= FAL_PHY_ADV_10T_HD;
+        }
+    }
+    else
+    {
+        return SW_FAIL;
+    }
+
+    (void)f1_phy_set_autoneg_adv(dev_id, phy_id, autoneg);
+    (void)f1_phy_restart_autoneg(dev_id, phy_id);
+    if(f1_phy_get_link_status(dev_id, phy_id))
+    {
+        do
+        {
+            phy_status = f1_phy_reg_read(dev_id, phy_id, F1_PHY_STATUS);
+        }
+        while(!F1_AUTONEG_DONE(phy_status));
+    }
+
+    f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL, phy_data);
+    (void)f1_phy_set_autoneg_adv(dev_id, phy_id, oldneg);
+
+    return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* f1_phy_get_duplex - Determines the speed of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+f1_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+                  fal_port_duplex_t * duplex)
+{
+	a_uint16_t phy_data;
+	a_bool_t auto_neg;
+
+	auto_neg = f1_phy_autoneg_status(dev_id, phy_id);
+	if (A_TRUE == auto_neg ) {
+		phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_SPEC_STATUS);
+
+		//read duplex
+		if (phy_data & F1_STATUS_FULL_DUPLEX)
+			*duplex = FAL_FULL_DUPLEX;
+		else
+			*duplex = FAL_HALF_DUPLEX;
+	}
+	else
+	{
+		phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+		//read duplex
+		if (phy_data & F1_CTRL_FULL_DUPLEX)
+			*duplex = FAL_FULL_DUPLEX;
+		else
+			*duplex = FAL_HALF_DUPLEX;
+	}
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_set_duplex - Determines the speed of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+f1_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+                  fal_port_duplex_t duplex)
+{
+    a_uint16_t phy_data = 0;
+    a_uint16_t phy_status = 0;
+
+    fal_port_speed_t old_speed = FAL_SPEED_10;
+    a_uint32_t oldneg, autoneg;
+
+    if (A_TRUE == f1_phy_autoneg_status(dev_id, phy_id))
+        phy_data &= ~F1_CTRL_AUTONEGOTIATION_ENABLE;
+
+    (void)f1_phy_get_autoneg_adv(dev_id, phy_id, &autoneg);
+    oldneg = autoneg;
+    autoneg &= ~FAL_PHY_ADV_GE_SPEED_ALL;
+    (void)f1_phy_get_speed(dev_id, phy_id, &old_speed);
+
+    if (FAL_SPEED_1000 == old_speed)
+    {
+        phy_data |= F1_CTRL_SPEED_1000;
+        phy_data |= F1_CTRL_AUTONEGOTIATION_ENABLE;
+    }
+    else if (FAL_SPEED_100 == old_speed)
+    {
+        phy_data |= F1_CTRL_SPEED_100;
+    }
+    else if (FAL_SPEED_10 == old_speed)
+    {
+        phy_data |= F1_CTRL_SPEED_10;
+    }
+    else
+    {
+        return SW_FAIL;
+    }
+
+    if (duplex == FAL_FULL_DUPLEX)
+    {
+        phy_data |= F1_CTRL_FULL_DUPLEX;
+
+        if (FAL_SPEED_1000 == old_speed)
+        {
+            autoneg = FAL_PHY_ADV_1000T_FD;
+        }
+        else if (FAL_SPEED_100 == old_speed)
+        {
+            autoneg = FAL_PHY_ADV_100TX_FD;
+        }
+        else
+        {
+            autoneg = FAL_PHY_ADV_10T_FD;
+        }
+    }
+    else if (duplex == FAL_HALF_DUPLEX)
+    {
+        phy_data &= ~F1_CTRL_FULL_DUPLEX;
+
+        if (FAL_SPEED_100 == old_speed)
+        {
+            autoneg = FAL_PHY_ADV_100TX_HD;
+        }
+        else
+        {
+            autoneg = FAL_PHY_ADV_10T_HD;
+        }
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    (void)f1_phy_set_autoneg_adv(dev_id, phy_id, autoneg);
+    (void)f1_phy_restart_autoneg(dev_id, phy_id);
+    if(f1_phy_get_link_status(dev_id, phy_id))
+    {
+        do
+        {
+            phy_status = f1_phy_reg_read(dev_id, phy_id, F1_PHY_STATUS);
+        }
+        while(!F1_AUTONEG_DONE(phy_status));
+    }
+
+    f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL, phy_data);
+    (void)f1_phy_set_autoneg_adv(dev_id, phy_id, oldneg);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_get_phy_id - get the phy id
+*
+*/
+static sw_error_t
+f1_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *phy_data)
+{
+    a_uint16_t org_id, rev_id;
+
+    org_id = f1_phy_reg_read(dev_id, phy_id, F1_PHY_ID1);
+    rev_id = f1_phy_reg_read(dev_id, phy_id, F1_PHY_ID2);
+    *phy_data = ((org_id & 0xffff) << 16) | (rev_id & 0xffff);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_intr_mask_set - Set interrupt mask with the
+* specified device.
+*/
+sw_error_t
+f1_phy_intr_mask_set(a_uint32_t dev_id, a_uint32_t phy_id,
+                     a_uint32_t intr_mask_flag)
+{
+    a_uint16_t phy_data = 0;
+
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_INTR_MASK);
+
+    if (FAL_PHY_INTR_STATUS_UP_CHANGE & intr_mask_flag)
+    {
+        phy_data |= F1_INTR_STATUS_UP_CHANGE;
+    }
+    else
+    {
+        phy_data &= (~F1_INTR_STATUS_UP_CHANGE);
+    }
+
+    if (FAL_PHY_INTR_STATUS_DOWN_CHANGE & intr_mask_flag)
+    {
+        phy_data |= F1_INTR_STATUS_DOWN_CHANGE;
+    }
+    else
+    {
+        phy_data &= (~F1_INTR_STATUS_DOWN_CHANGE);
+    }
+
+    if (FAL_PHY_INTR_SPEED_CHANGE & intr_mask_flag)
+    {
+        phy_data |= F1_INTR_SPEED_CHANGE;
+    }
+    else
+    {
+        phy_data &= (~F1_INTR_SPEED_CHANGE);
+    }
+
+    if (FAL_PHY_INTR_DUPLEX_CHANGE & intr_mask_flag)
+    {
+        phy_data |= F1_INTR_DUPLEX_CHANGE;
+    }
+    else
+    {
+        phy_data &= (~F1_INTR_DUPLEX_CHANGE);
+    }
+
+    f1_phy_reg_write(dev_id, phy_id, F1_PHY_INTR_MASK, phy_data);
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_intr_mask_get - Get interrupt mask with the
+* specified device.
+*/
+sw_error_t
+f1_phy_intr_mask_get(a_uint32_t dev_id, a_uint32_t phy_id,
+                     a_uint32_t * intr_mask_flag)
+{
+    a_uint16_t phy_data = 0;
+
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_INTR_MASK);
+
+    *intr_mask_flag = 0;
+    if (F1_INTR_STATUS_UP_CHANGE & phy_data)
+    {
+        *intr_mask_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE;
+    }
+
+    if (F1_INTR_STATUS_DOWN_CHANGE & phy_data)
+    {
+        *intr_mask_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE;
+    }
+
+    if (F1_INTR_SPEED_CHANGE & phy_data)
+    {
+        *intr_mask_flag |= FAL_PHY_INTR_SPEED_CHANGE;
+    }
+
+    if (F1_INTR_DUPLEX_CHANGE & phy_data)
+    {
+        *intr_mask_flag |= FAL_PHY_INTR_DUPLEX_CHANGE;
+    }
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_intr_status_get - Get interrupt status with the
+* specified device.
+*/
+sw_error_t
+f1_phy_intr_status_get(a_uint32_t dev_id, a_uint32_t phy_id,
+                       a_uint32_t * intr_status_flag)
+{
+    a_uint16_t phy_data = 0;
+
+    phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_INTR_STATUS);
+
+    *intr_status_flag = 0;
+    if (F1_INTR_STATUS_UP_CHANGE & phy_data)
+    {
+        *intr_status_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE;
+    }
+
+    if (F1_INTR_STATUS_DOWN_CHANGE & phy_data)
+    {
+        *intr_status_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE;
+    }
+
+    if (F1_INTR_SPEED_CHANGE & phy_data)
+    {
+        *intr_status_flag |= FAL_PHY_INTR_SPEED_CHANGE;
+    }
+
+    if (F1_INTR_DUPLEX_CHANGE & phy_data)
+    {
+        *intr_status_flag |= FAL_PHY_INTR_DUPLEX_CHANGE;
+    }
+
+    return SW_OK;
+}
+/******************************************************************************
+*
+*f1_phy_set_8023az status
+*
+* get 8023az status
+*/
+
+sw_error_t
+f1_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = f1_phy_mmd_read(dev_id, phy_id, F1_PHY_MMD7_NUM,
+				       F1_PHY_8023AZ_EEE_CTRL);
+	if (enable == A_TRUE) {
+		phy_data |= F1_PHY_AZ_ENABLE;
+
+		f1_phy_mmd_write(dev_id, phy_id, F1_PHY_MMD7_NUM,
+			     F1_PHY_8023AZ_EEE_CTRL, phy_data);
+	} else {
+		phy_data &= ~F1_PHY_AZ_ENABLE;
+
+		f1_phy_mmd_write(dev_id, phy_id, F1_PHY_MMD7_NUM,
+			     F1_PHY_8023AZ_EEE_CTRL, phy_data);
+	}
+
+	f1_phy_restart_autoneg(dev_id, phy_id);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+*f1_phy_get_8023az status
+*
+* get 8023az status
+*/
+sw_error_t
+f1_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	*enable = A_FALSE;
+
+	phy_data = f1_phy_mmd_read(dev_id, phy_id, F1_PHY_MMD7_NUM,
+				       F1_PHY_8023AZ_EEE_CTRL);
+
+	if ((phy_data & 0x6) == F1_PHY_AZ_ENABLE)
+		*enable = A_TRUE;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_set_local_loopback
+*
+* set phy local loopback
+*/
+sw_error_t
+f1_phy_set_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	fal_port_speed_t old_speed;
+	sw_error_t rv = SW_OK;
+
+	if (enable == A_TRUE) {
+		rv = f1_phy_get_speed(dev_id, phy_id, &old_speed);
+		SW_RTN_ON_ERROR(rv);
+
+		if (old_speed == FAL_SPEED_1000) {
+			phy_data = F1_1000M_LOOPBACK;
+		} else if (old_speed == FAL_SPEED_100) {
+			phy_data = F1_100M_LOOPBACK;
+		} else if (old_speed == FAL_SPEED_10) {
+			phy_data = F1_10M_LOOPBACK;
+		} else {
+			return SW_FAIL;
+		}
+		phy_data |= F1_CTRL_FULL_DUPLEX;
+	} else {
+		phy_data = F1_COMMON_CTRL;
+	}
+
+	rv = f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* f1_phy_get_local_loopback
+*
+* get phy local loopback
+*/
+sw_error_t
+f1_phy_get_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+
+	if (phy_data & F1_LOCAL_LOOPBACK_ENABLE)
+	{
+		*enable = A_TRUE;
+	}
+	else
+	{
+		*enable = A_FALSE;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_set_remote_loopback
+*
+* set phy remote loopback
+*/
+sw_error_t
+f1_phy_set_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	phy_data = f1_phy_mmd_read(dev_id, phy_id, F1_PHY_MMD3_NUM,
+		F1_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL);
+
+	if (enable == A_TRUE)
+	{
+		phy_data |= F1_PHY_REMOTE_LOOPBACK_ENABLE;
+	}
+	else
+	{
+		phy_data &= ~F1_PHY_REMOTE_LOOPBACK_ENABLE;
+	}
+
+	rv = f1_phy_mmd_write(dev_id, phy_id, F1_PHY_MMD3_NUM,
+		F1_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* f1_phy_get_remote_loopback
+*
+* get phy remote loopback
+*/
+sw_error_t
+f1_phy_get_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = f1_phy_mmd_read(dev_id, phy_id, F1_PHY_MMD3_NUM,
+		F1_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL);
+
+	if (phy_data & F1_PHY_REMOTE_LOOPBACK_ENABLE)
+	{
+		*enable = A_TRUE;
+	}
+	else
+	{
+		*enable = A_FALSE;
+	}
+
+	return SW_OK;
+}
+
+static int f1_phy_api_ops_init(void)
+{
+	int ret;
+	hsl_phy_ops_t *f1_phy_api_ops = NULL;
+
+	f1_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL);
+	if (f1_phy_api_ops == NULL) {
+		SSDK_ERROR("f1 phy ops kzalloc failed!\n");
+		return -ENOMEM;
+	}
+
+	phy_api_ops_init(F1_PHY_CHIP);
+
+	f1_phy_api_ops->phy_hibernation_set = f1_phy_set_hibernate;
+	f1_phy_api_ops->phy_hibernation_get = f1_phy_get_hibernate;
+	f1_phy_api_ops->phy_speed_get = f1_phy_get_speed;
+	f1_phy_api_ops->phy_speed_set = f1_phy_set_speed;
+	f1_phy_api_ops->phy_duplex_get = f1_phy_get_duplex;
+	f1_phy_api_ops->phy_duplex_set = f1_phy_set_duplex;
+	f1_phy_api_ops->phy_autoneg_enable_set = f1_phy_enable_autoneg;
+	f1_phy_api_ops->phy_restart_autoneg = f1_phy_restart_autoneg;
+	f1_phy_api_ops->phy_autoneg_status_get = f1_phy_autoneg_status;
+	f1_phy_api_ops->phy_autoneg_adv_set = f1_phy_set_autoneg_adv;
+	f1_phy_api_ops->phy_autoneg_adv_get = f1_phy_get_autoneg_adv;
+	f1_phy_api_ops->phy_powersave_set = f1_phy_set_powersave;
+	f1_phy_api_ops->phy_powersave_get = f1_phy_get_powersave;
+	f1_phy_api_ops->phy_cdt = f1_phy_cdt;
+	f1_phy_api_ops->phy_link_status_get = f1_phy_get_link_status;
+	f1_phy_api_ops->phy_reset = f1_phy_reset;
+	f1_phy_api_ops->phy_power_off = f1_phy_poweroff;
+	f1_phy_api_ops->phy_power_on = 	f1_phy_poweron;
+	f1_phy_api_ops->phy_id_get = f1_phy_get_phy_id;
+	f1_phy_api_ops->phy_reg_write = f1_phy_reg_write;
+	f1_phy_api_ops->phy_reg_read = f1_phy_reg_read;
+	f1_phy_api_ops->phy_debug_write = f1_phy_debug_write;
+	f1_phy_api_ops->phy_debug_read = f1_phy_debug_read;
+	f1_phy_api_ops->phy_mmd_write = f1_phy_mmd_write;
+	f1_phy_api_ops->phy_mmd_read = f1_phy_mmd_read;
+	f1_phy_api_ops->phy_local_loopback_set = f1_phy_set_local_loopback;
+	f1_phy_api_ops->phy_local_loopback_get = f1_phy_get_local_loopback;
+	f1_phy_api_ops->phy_remote_loopback_set = f1_phy_set_remote_loopback;
+	f1_phy_api_ops->phy_remote_loopback_get = f1_phy_get_remote_loopback;
+	f1_phy_api_ops->phy_intr_mask_set = f1_phy_intr_mask_set;
+	f1_phy_api_ops->phy_intr_mask_get = f1_phy_intr_mask_get;
+	f1_phy_api_ops->phy_intr_status_get = f1_phy_intr_status_get;
+	f1_phy_api_ops->phy_8023az_set = f1_phy_set_8023az;
+	f1_phy_api_ops->phy_8023az_get = f1_phy_get_8023az;
+
+	ret = hsl_phy_api_ops_register(F1_PHY_CHIP, f1_phy_api_ops);
+
+	if (ret == 0)
+		SSDK_INFO("qca probe f1 phy driver succeeded!\n");
+	else
+		SSDK_ERROR("qca probe f1 phy driver failed! (code: %d)\n", ret);
+	return ret;
+}
+
+int f1_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp)
+{
+	static a_uint32_t phy_ops_flag = 0;
+
+	if(phy_ops_flag == 0) {
+		f1_phy_api_ops_init();
+		phy_ops_flag = 1;
+	}
+
+	return 0;
+}
+
diff --git a/qca-ssdk/src/hsl/phy/f2_phy.c b/qca-ssdk/src/hsl/phy/f2_phy.c
new file mode 100755
index 0000000..0742944
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/f2_phy.c
@@ -0,0 +1,918 @@
+/*
+ * Copyright (c) 2012, 2015-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "fal_port_ctrl.h"
+#include "hsl_api.h"
+#include "hsl.h"
+#include "f2_phy.h"
+#include "hsl_phy.h"
+#include "ssdk_plat.h"
+
+static a_uint16_t
+_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint8_t reg)
+{
+    sw_error_t rv;
+    a_uint16_t val = 0;
+
+    HSL_PHY_GET(rv, dev_id, phy_addr, reg, &val);
+    if (SW_OK != rv)
+        return 0xFFFF;
+
+    return val;
+}
+
+
+static sw_error_t
+_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint8_t reg,
+               a_uint16_t val)
+{
+    sw_error_t rv;
+
+    HSL_PHY_SET(rv, dev_id, phy_addr, reg, val);
+
+    return rv;
+}
+
+/* #define f2_phy_reg_read _phy_reg_read */
+/* #define f2_phy_reg_write _phy_reg_write */
+
+/******************************************************************************
+*
+* f2_phy_mii_read - mii register read
+*
+* mil register read
+*/
+a_uint16_t
+f2_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id)
+{
+ 	return _phy_reg_read(dev_id, phy_id, reg_id);
+
+}
+
+/******************************************************************************
+*
+* f2_phy_reg_write - mii register write
+*
+* mii register write
+*/
+sw_error_t
+f2_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id,
+		       a_uint16_t reg_val)
+{
+
+       _phy_reg_write(dev_id,phy_id, reg_id, reg_val);
+
+	return SW_OK;
+}
+
+
+/******************************************************************************
+*
+* f2_phy_debug_write - debug port write
+*
+* debug port write
+*/
+sw_error_t
+f2_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id,
+                   a_uint16_t reg_val)
+{
+    f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, reg_id);
+    f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_DATA, reg_val);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_debug_read - debug port read
+*
+* debug port read
+*/
+a_uint16_t
+f2_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id)
+{
+    f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, reg_id);
+    return f2_phy_reg_read(dev_id, phy_id, F2_DEBUG_PORT_DATA);
+}
+
+/******************************************************************************
+*
+* f2_phy_set_powersave - set power saving status
+*
+* set power saving status
+*/
+sw_error_t
+f2_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+    a_uint16_t phy_data;
+    f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, 0x29);
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_DEBUG_PORT_DATA);
+
+    if(enable == A_TRUE)
+    {
+        phy_data |= 0x8000;
+    }
+    else
+    {
+        phy_data &= ~0x8000;
+    }
+
+    f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_DATA, phy_data);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_get_powersave - get power saving status
+*
+* set power saving status
+*/
+sw_error_t
+f2_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable)
+{
+    a_uint16_t phy_data;
+    *enable = A_FALSE;
+
+    f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, 0x29);
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_DEBUG_PORT_DATA);
+
+    if(phy_data & 0x8000)
+        *enable =  A_TRUE;
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_set_hibernate - set hibernate status
+*
+* set hibernate status
+*/
+sw_error_t
+f2_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+    a_uint16_t phy_data;
+    f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, 0xb);
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_DEBUG_PORT_DATA);
+
+    if(enable == A_TRUE)
+    {
+        phy_data |= 0x8000;
+    }
+    else
+    {
+        phy_data &= ~0x8000;
+    }
+
+    f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_DATA, phy_data);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_get_hibernate - get hibernate status
+*
+* get hibernate status
+*/
+sw_error_t
+f2_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable)
+{
+    a_uint16_t phy_data;
+    *enable = A_FALSE;
+
+    f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, 0xb);
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_DEBUG_PORT_DATA);
+
+    if(phy_data & 0x8000)
+        *enable =  A_TRUE;
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_cdt - cable diagnostic test
+*
+* cable diagnostic test
+*/
+sw_error_t
+f2_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+           fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+    a_uint16_t status = 0;
+    a_uint16_t ii = 100;
+    a_uint16_t cable_delta_time;
+
+    if(!cable_status || !cable_len)
+    {
+        return SW_FAIL;
+    }
+
+    if(mdi_pair >= 2)
+    {
+        //There are only 4 mdi pairs in 1000BASE-T
+        return SW_BAD_PARAM;
+    }
+
+    f2_phy_reg_write(dev_id, phy_id, F2_PHY_CDT_CONTROL, (mdi_pair << 8) | 0x0001);
+
+    do
+    {
+        aos_mdelay(30);
+        status = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CDT_CONTROL);
+    }
+    while ((status & 0x0001) && (--ii));
+
+    status = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CDT_STATUS);
+    *cable_status = (status & 0x300) >> 8;//(00:normal  01:short 10:opened 11:invalid)
+
+    /*the actual cable length equals to CableDeltaTime * 0.824*/
+    cable_delta_time = status & 0xff;
+    *cable_len = (cable_delta_time * 824) /1000;
+
+    /*workaround*/
+    if(*cable_len <= 2 && *cable_status == 1)
+        *cable_status = 2;
+
+    //f2_phy_reg_write(dev_id, phy_id, 0x00, 0x9000);  //Reset the PHY if necessary
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_reset_done - reset the phy
+*
+* reset the phy
+*/
+a_bool_t
+f2_phy_reset_done(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+    a_uint16_t ii = 200;
+
+    do
+    {
+        phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL);
+        aos_mdelay(10);
+    }
+    while ((!F2_RESET_DONE(phy_data)) && --ii);
+
+    if (ii == 0)
+        return A_FALSE;
+
+    return A_TRUE;
+}
+
+/******************************************************************************
+*
+* f2_autoneg_done
+*
+* f2_autoneg_done
+*/
+a_bool_t
+f2_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+    a_uint16_t ii = 200;
+
+    do
+    {
+        phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS);
+        aos_mdelay(10);
+    }
+    while ((!F2_AUTONEG_DONE(phy_data)) && --ii);
+
+    if (ii == 0)
+        return A_FALSE;
+
+    return A_TRUE;
+}
+
+/******************************************************************************
+*
+* f2_phy_Speed_Duplex_Resolved
+ - reset the phy
+*
+* reset the phy
+*/
+a_bool_t
+f2_phy_speed_duplex_resolved(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+    a_uint16_t ii = 200;
+
+    do
+    {
+        phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_SPEC_STATUS);
+        aos_mdelay(10);
+    }
+    while ((!F2_SPEED_DUPLEX_RESOVLED(phy_data)) && --ii);
+
+    if (ii == 0)
+        return A_FALSE;
+
+    return A_TRUE;
+}
+
+/******************************************************************************
+*
+* f2_phy_reset - reset the phy
+*
+* reset the phy
+*/
+sw_error_t
+f2_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL);
+    f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL,
+                     phy_data | F2_CTRL_SOFTWARE_RESET);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_off - power off the phy to change its speed
+*
+* Power off the phy
+*/
+sw_error_t
+f2_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL);
+    f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL,
+                     phy_data | F2_CTRL_POWER_DOWN);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_on - power on the phy after speed changed
+*
+* Power on the phy
+*/
+sw_error_t
+f2_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL);
+    f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL,
+                     phy_data & ~F2_CTRL_POWER_DOWN);
+
+    aos_mdelay(200);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_get_ability - get the phy ability
+*
+*
+*/
+sw_error_t
+f2_phy_get_ability(a_uint32_t dev_id, a_uint32_t phy_id,
+                   a_uint16_t * ability)
+{
+    a_uint16_t phy_data;
+
+    *ability = 0;
+
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS);
+
+    if (phy_data & F2_STATUS_AUTONEG_CAPS)
+        *ability |= FAL_PHY_AUTONEG_CAPS;
+
+    if (phy_data & F2_STATUS_100T2_HD_CAPS)
+        *ability |= FAL_PHY_100T2_HD_CAPS;
+
+    if (phy_data & F2_STATUS_100T2_FD_CAPS)
+        *ability |= FAL_PHY_100T2_FD_CAPS;
+
+    if (phy_data & F2_STATUS_10T_HD_CAPS)
+        *ability |= FAL_PHY_10T_HD_CAPS;
+
+    if (phy_data & F2_STATUS_10T_FD_CAPS)
+        *ability |= FAL_PHY_10T_FD_CAPS;
+
+    if (phy_data & F2_STATUS_100X_HD_CAPS)
+        *ability |= FAL_PHY_100X_HD_CAPS;
+
+    if (phy_data & F2_STATUS_100X_FD_CAPS)
+        *ability |= FAL_PHY_100X_FD_CAPS;
+
+    if (phy_data & F2_STATUS_100T4_CAPS)
+        *ability |= FAL_PHY_100T4_CAPS;
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_get_ability - get the phy ability
+*
+*
+*/
+sw_error_t
+f2_phy_get_partner_ability(a_uint32_t dev_id, a_uint32_t phy_id,
+                           a_uint16_t * ability)
+{
+    a_uint16_t phy_data;
+
+    *ability = 0;
+
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_LINK_PARTNER_ABILITY);
+
+    if (phy_data & F2_LINK_10BASETX_HALF_DUPLEX)
+        *ability |= FAL_PHY_PART_10T_HD;
+
+    if (phy_data & F2_LINK_10BASETX_FULL_DUPLEX)
+        *ability |= FAL_PHY_PART_10T_FD;
+
+    if (phy_data & F2_LINK_100BASETX_HALF_DUPLEX)
+        *ability |= FAL_PHY_PART_100TX_HD;
+
+    if (phy_data & F2_LINK_100BASETX_FULL_DUPLEX)
+        *ability |= FAL_PHY_PART_100TX_FD;
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_status - test to see if the specified phy link is alive
+*
+* RETURNS:
+*    A_TRUE  --> link is alive
+*    A_FALSE --> link is down
+*/
+a_bool_t
+f2_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS);
+
+    if (phy_data & F2_STATUS_LINK_STATUS_UP)
+        return A_TRUE;
+
+    return A_FALSE;
+}
+
+/******************************************************************************
+*
+* f2_set_autoneg_adv - set the phy autoneg Advertisement
+*
+*/
+sw_error_t
+f2_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+                       a_uint32_t autoneg)
+{
+    a_uint16_t phy_data = 0;
+
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_AUTONEG_ADVERT);
+    phy_data &= ~F2_ADVERTISE_ALL;
+    phy_data &= ~(F2_ADVERTISE_PAUSE | F2_ADVERTISE_ASYM_PAUSE);
+
+    if (autoneg & FAL_PHY_ADV_100TX_FD)
+        phy_data |= F2_ADVERTISE_100FULL;
+
+    if (autoneg & FAL_PHY_ADV_100TX_HD)
+        phy_data |= F2_ADVERTISE_100HALF;
+
+    if (autoneg & FAL_PHY_ADV_10T_FD)
+        phy_data |= F2_ADVERTISE_10FULL;
+
+    if (autoneg & FAL_PHY_ADV_10T_HD)
+        phy_data |= F2_ADVERTISE_10HALF;
+
+    if (autoneg & FAL_PHY_ADV_PAUSE)
+        phy_data |= F2_ADVERTISE_PAUSE;
+
+    if (autoneg & FAL_PHY_ADV_ASY_PAUSE)
+        phy_data |= F2_ADVERTISE_ASYM_PAUSE;
+
+    f2_phy_reg_write(dev_id, phy_id, F2_AUTONEG_ADVERT, phy_data);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_get_autoneg_adv - get the phy autoneg Advertisement
+*
+*/
+sw_error_t
+f2_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+                       a_uint32_t * autoneg)
+{
+    a_uint16_t phy_data = 0;
+
+    *autoneg = 0;
+
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_AUTONEG_ADVERT);
+
+    if (phy_data & F2_ADVERTISE_100FULL)
+        *autoneg |= FAL_PHY_ADV_100TX_FD;
+
+    if (phy_data & F2_ADVERTISE_100HALF)
+        *autoneg |= FAL_PHY_ADV_100TX_HD;
+
+    if (phy_data & F2_ADVERTISE_10FULL)
+        *autoneg |= FAL_PHY_ADV_10T_FD;
+
+    if (phy_data & F2_ADVERTISE_10HALF)
+        *autoneg |= FAL_PHY_ADV_10T_HD;
+
+    if (phy_data & F2_ADVERTISE_PAUSE)
+        *autoneg |= FAL_PHY_ADV_PAUSE;
+
+    if (phy_data & F2_ADVERTISE_ASYM_PAUSE)
+        *autoneg |= FAL_PHY_ADV_ASY_PAUSE;
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_enable_autonego - power off the phy to change its speed
+*
+* Power off the phy
+*/
+a_bool_t
+f2_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data;
+
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL);
+
+    if (phy_data & F2_CTRL_AUTONEGOTIATION_ENABLE)
+        return A_TRUE;
+
+    return A_FALSE;
+}
+
+/******************************************************************************
+*
+* f2_restart_autoneg - restart the phy autoneg
+*
+*/
+sw_error_t
+f2_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data = 0;
+
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL);
+
+    phy_data |= F2_CTRL_AUTONEGOTIATION_ENABLE;
+    f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL,
+                     phy_data | F2_CTRL_RESTART_AUTONEGOTIATION);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_enable_autonego - power off the phy to change its speed
+*
+* Power off the phy
+*/
+sw_error_t
+f2_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+    a_uint16_t phy_data = 0;
+
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL);
+
+    f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL,
+                     phy_data | F2_CTRL_AUTONEGOTIATION_ENABLE);
+
+    return SW_OK;
+}
+
+
+/******************************************************************************
+*
+* f2_phy_get_speed - Determines the speed of phy ports associated with the
+* specified device.
+*
+* RETURNS:
+*               AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX;
+*               AG7100_PHY_SPEED_1000T;
+*/
+
+sw_error_t
+f2_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+                 fal_port_speed_t * speed)
+{
+    a_uint16_t phy_data;
+
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_SPEC_STATUS);
+
+    //read speed
+    switch (phy_data & F2_STATUS_SPEED_MASK)
+    {
+        case F2_STATUS_SPEED_1000MBS:
+            *speed = FAL_SPEED_1000;
+            break;
+        case F2_STATUS_SPEED_100MBS:
+            *speed = FAL_SPEED_100;
+            break;
+        case F2_STATUS_SPEED_10MBS:
+            *speed = FAL_SPEED_10;
+            break;
+        default:
+            return SW_READ_ERROR;
+    }
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_set_speed - Determines the speed of phy ports associated with the
+* specified device.
+*
+* RETURNS:
+*               AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX;
+*               AG7100_PHY_SPEED_1000T;
+*/
+sw_error_t
+f2_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+                 fal_port_speed_t speed)
+{
+    a_uint16_t phy_data = 0;
+    a_uint16_t phy_status = 0;
+    a_uint32_t autoneg, oldneg;
+    fal_port_duplex_t old_duplex;
+
+    phy_data &= ~F2_CTRL_AUTONEGOTIATION_ENABLE;
+
+    (void)f2_phy_get_autoneg_adv(dev_id, phy_id, &autoneg);
+    oldneg = autoneg;
+    autoneg &= ~FAL_PHY_ADV_FE_SPEED_ALL;
+
+    (void)f2_phy_get_duplex(dev_id, phy_id, &old_duplex);
+
+    if (old_duplex == FAL_FULL_DUPLEX)
+    {
+        phy_data |= F2_CTRL_FULL_DUPLEX;
+
+        if (speed == FAL_SPEED_100)
+            autoneg |= FAL_PHY_ADV_100TX_FD;
+        else
+            autoneg |= FAL_PHY_ADV_10T_FD;
+    }
+    else if (old_duplex == FAL_HALF_DUPLEX)
+    {
+        phy_data &= ~F2_CTRL_FULL_DUPLEX;
+
+        if (speed == FAL_SPEED_100)
+            autoneg |= FAL_PHY_ADV_100TX_HD;
+        else
+            autoneg |= FAL_PHY_ADV_10T_HD;
+    }
+    else
+        return SW_FAIL;
+
+    (void)f2_phy_set_autoneg_adv(dev_id, phy_id, autoneg);
+    (void)f2_phy_restart_autoneg(dev_id, phy_id);
+
+    if(f2_phy_get_link_status(dev_id, phy_id))
+    {
+        do
+        {
+            phy_status = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS);
+        }
+        while(!F2_AUTONEG_DONE(phy_status));
+    }
+
+    if (speed == FAL_SPEED_100)
+        phy_data |= F2_CTRL_SPEED_100;
+    else if (speed == FAL_SPEED_10)
+        phy_data |= F2_CTRL_SPEED_10;
+    else
+        return SW_BAD_PARAM;
+
+    f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL, phy_data);
+    (void)f2_phy_set_autoneg_adv(dev_id, phy_id, oldneg);
+
+    return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* f2_phy_get_duplex - Determines the speed of phy ports associated with the
+* specified device.
+*
+* RETURNS:
+*               AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX;
+*               AG7100_PHY_SPEED_1000T;
+*/
+sw_error_t
+f2_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+                  fal_port_duplex_t * duplex)
+{
+    a_uint16_t phy_data;
+
+#if 0
+    //a_uint16_t ii = 200;
+    a_uint16_t ii = 2;
+
+    if (phy_id >= F2_PHY_MAX)
+        return SW_BAD_PARAM;
+
+    do
+    {
+        phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_SPEC_STATUS);
+        aos_mdelay(10);
+    }
+    while ((!(phy_data & F2_STATUS_RESOVLED)) && --ii);
+
+    //read time out
+    if (ii == 0)
+        return SW_DISABLE;
+#endif
+
+    phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_SPEC_STATUS);
+
+    //read duplex
+    if (phy_data & F2_STATUS_FULL_DUPLEX)
+        *duplex = FAL_FULL_DUPLEX;
+    else
+        *duplex = FAL_HALF_DUPLEX;
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_set_duplex - Determines the speed of phy ports associated with the
+* specified device.
+*
+* RETURNS:
+*               AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX;
+*               AG7100_PHY_SPEED_1000T;
+*/
+sw_error_t
+f2_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+                  fal_port_duplex_t duplex)
+{
+    a_uint16_t phy_data = 0;
+    a_uint16_t phy_status = 0;
+
+    fal_port_speed_t old_speed = FAL_SPEED_10;
+    a_uint32_t autoneg, oldneg;
+
+    if (f2_phy_autoneg_status(dev_id, phy_id))
+        phy_data &= ~F2_CTRL_AUTONEGOTIATION_ENABLE;
+
+    (void)f2_phy_get_autoneg_adv(dev_id, phy_id, &autoneg);
+    oldneg = autoneg;
+    autoneg &= ~FAL_PHY_ADV_FE_SPEED_ALL;
+
+    (void)f2_phy_get_speed(dev_id, phy_id, &old_speed);
+
+    if (old_speed == FAL_SPEED_100)
+        phy_data |= F2_CTRL_SPEED_100;
+    else if (old_speed == FAL_SPEED_10)
+        phy_data |= F2_CTRL_SPEED_10;
+    else
+        return SW_FAIL;
+
+    if (duplex == FAL_FULL_DUPLEX)
+    {
+        phy_data |= F2_CTRL_FULL_DUPLEX;
+
+        if (old_speed == FAL_SPEED_100)
+            autoneg = FAL_PHY_ADV_100TX_FD;
+        else
+            autoneg = FAL_PHY_ADV_10T_FD;
+    }
+    else if (duplex == FAL_HALF_DUPLEX)
+    {
+        phy_data &= ~F2_CTRL_FULL_DUPLEX;
+
+        if (old_speed == FAL_SPEED_100)
+            autoneg = FAL_PHY_ADV_100TX_HD;
+        else
+            autoneg = FAL_PHY_ADV_10T_HD;
+    }
+    else
+        return SW_BAD_PARAM;
+
+    (void)f2_phy_set_autoneg_adv(dev_id, phy_id, autoneg);
+    (void)f2_phy_restart_autoneg(dev_id, phy_id);
+
+    if(f2_phy_get_link_status(dev_id, phy_id))
+    {
+        do
+        {
+            phy_status = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS);
+        }
+        while(!F2_AUTONEG_DONE(phy_status));
+    }
+
+    f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL, phy_data);
+    (void)f2_phy_set_autoneg_adv(dev_id, phy_id, oldneg);
+
+    return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_get_phy_id - get the phy id
+*
+*/
+static sw_error_t
+f2_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *phy_data)
+{
+    a_uint16_t org_id, rev_id;
+
+    org_id = f2_phy_reg_read(dev_id, phy_id, F2_PHY_ID1);
+    rev_id = f2_phy_reg_read(dev_id, phy_id, F2_PHY_ID2);
+    *phy_data = ((org_id & 0xffff) << 16) | (rev_id & 0xffff);
+
+    return SW_OK;
+}
+static int f2_phy_api_ops_init(void)
+{
+	int ret;
+	hsl_phy_ops_t *f2_phy_api_ops = NULL;
+
+	f2_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL);
+	if (f2_phy_api_ops == NULL) {
+		SSDK_ERROR("f2 phy ops kzalloc failed!\n");
+		return -ENOMEM;
+	}
+
+	phy_api_ops_init(F2_PHY_CHIP);
+
+	f2_phy_api_ops->phy_hibernation_set = f2_phy_set_hibernate;
+	f2_phy_api_ops->phy_hibernation_get = f2_phy_get_hibernate;
+	f2_phy_api_ops->phy_speed_get = f2_phy_get_speed;
+	f2_phy_api_ops->phy_speed_set = f2_phy_set_speed;
+	f2_phy_api_ops->phy_duplex_get = f2_phy_get_duplex;
+	f2_phy_api_ops->phy_duplex_set = f2_phy_set_duplex;
+	f2_phy_api_ops->phy_autoneg_enable_set = f2_phy_enable_autoneg;
+	f2_phy_api_ops->phy_restart_autoneg = f2_phy_restart_autoneg;
+	f2_phy_api_ops->phy_autoneg_status_get = f2_phy_autoneg_status;
+	f2_phy_api_ops->phy_autoneg_adv_set = f2_phy_set_autoneg_adv;
+	f2_phy_api_ops->phy_autoneg_adv_get = f2_phy_get_autoneg_adv;
+	f2_phy_api_ops->phy_powersave_set = f2_phy_set_powersave;
+	f2_phy_api_ops->phy_powersave_get = f2_phy_get_powersave;
+	f2_phy_api_ops->phy_cdt = f2_phy_cdt;
+	f2_phy_api_ops->phy_link_status_get = f2_phy_get_link_status;
+	f2_phy_api_ops->phy_reset = f2_phy_reset;
+	f2_phy_api_ops->phy_power_off = f2_phy_poweroff;
+	f2_phy_api_ops->phy_power_on = f2_phy_poweron;
+	f2_phy_api_ops->phy_id_get = f2_phy_get_phy_id;
+	f2_phy_api_ops->phy_reg_write = f2_phy_reg_write;
+	f2_phy_api_ops->phy_reg_read = f2_phy_reg_read;
+	f2_phy_api_ops->phy_debug_write = f2_phy_debug_write;
+	f2_phy_api_ops->phy_debug_read = f2_phy_debug_read;
+
+	ret = hsl_phy_api_ops_register(F2_PHY_CHIP, f2_phy_api_ops);
+
+	if (ret == 0)
+		SSDK_INFO("qca probe f2 phy driver succeeded!\n");
+	else
+		SSDK_ERROR("qca probe f2 phy driver failed! (code: %d)\n", ret);
+
+	return ret;
+}
+int f2_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp)
+{
+	static a_uint32_t phy_ops_flag = 0;
+
+	if(phy_ops_flag == 0) {
+		f2_phy_api_ops_init();
+		phy_ops_flag = 1;
+	}
+
+	return 0;
+}
+
diff --git a/qca-ssdk/src/hsl/phy/hsl_phy.c b/qca-ssdk/src/hsl/phy/hsl_phy.c
new file mode 100755
index 0000000..03a1023
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/hsl_phy.c
@@ -0,0 +1,847 @@
+/*
+ * Copyright (c) 2015, 2017-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+/*qca808x_start*/
+#include "sw.h"
+#include "hsl_phy.h"
+#include "hsl.h"
+/*qca808x_end*/
+#include "ssdk_dts.h"
+#if defined(ISIS) ||defined(ISISC) ||defined(GARUDA)
+#include <f1_phy.h>
+#endif
+#if defined(ATHENA) ||defined(SHIVA) ||defined(HORUS)
+#include <f2_phy.h>
+#endif
+#ifdef MP
+#include "mpge_phy.h"
+#endif
+#ifdef IN_MALIBU_PHY
+#include <malibu_phy.h>
+#endif
+#ifdef IN_AQUANTIA_PHY
+#include <aquantia_phy.h>
+#endif
+#ifdef IN_QCA803X_PHY
+#include <qca803x_phy.h>
+#endif
+#ifdef IN_SFP_PHY
+#include <sfp_phy.h>
+#endif
+#ifdef IN_QCA808X_PHY
+/*qca808x_start*/
+#include <qca808x_phy.h>
+/*qca808x_end*/
+#endif
+#include <linux/of_gpio.h>
+/*qca808x_start*/
+#include "sw.h"
+#include "ssdk_plat.h"
+#include "hsl_port_prop.h"
+
+phy_info_t *phy_info[SW_MAX_NR_DEV] = {0};
+a_uint32_t port_bmp[SW_MAX_NR_DEV] = {0};
+
+
+phy_driver_instance_t ssdk_phy_driver[] =
+{
+/*qca808x_end*/
+	#if defined(ISIS) ||defined(ISISC) ||defined(GARUDA)
+	{F1_PHY_CHIP, {0}, NULL, f1_phy_init, NULL},
+	#else
+	{F1_PHY_CHIP, {0}, NULL, NULL, NULL},
+	#endif
+	#if defined(ATHENA) ||defined(SHIVA) ||defined(HORUS)
+	{F2_PHY_CHIP, {0}, NULL, f2_phy_init, NULL},
+	#else
+	{F2_PHY_CHIP, {0}, NULL, NULL, NULL},
+	#endif
+	#ifdef IN_MALIBU_PHY
+	{MALIBU_PHY_CHIP, {0}, NULL, malibu_phy_init, NULL},
+	#else
+	{MALIBU_PHY_CHIP, {0}, NULL, NULL, NULL},
+	#endif
+	#ifdef IN_AQUANTIA_PHY
+	{AQUANTIA_PHY_CHIP, {0}, NULL, aquantia_phy_init, NULL},
+	#else
+	{AQUANTIA_PHY_CHIP, {0}, NULL, NULL, NULL},
+	#endif
+	#ifdef IN_QCA803X_PHY
+	{QCA803X_PHY_CHIP, {0}, NULL, qca803x_phy_init, NULL},
+	#else
+	{QCA803X_PHY_CHIP, {0}, NULL, NULL, NULL},
+	#endif
+	#ifdef IN_SFP_PHY
+	{SFP_PHY_CHIP, {0}, NULL, sfp_phy_init, sfp_phy_exit},
+	#else
+	{SFP_PHY_CHIP, {0}, NULL, NULL, NULL},
+	#endif
+	#ifdef MP
+	{MPGE_PHY_CHIP, {0}, NULL, mpge_phy_init, NULL},
+	#else
+	{MPGE_PHY_CHIP, {0}, NULL, NULL, NULL},
+	#endif
+	#ifdef IN_QCA808X_PHY
+/*qca808x_start*/
+	{QCA808X_PHY_CHIP, {0}, NULL, qca808x_phy_init, qca808x_phy_exit},
+/*qca808x_end*/
+	#else
+	{QCA808X_PHY_CHIP, {0}, NULL, NULL, NULL},
+	#endif
+/*qca808x_start*/
+	{MAX_PHY_CHIP, {0}, NULL, NULL, NULL}
+};
+sw_error_t hsl_phy_api_ops_register(phy_type_t phy_type, hsl_phy_ops_t * phy_api_ops)
+{
+
+	ssdk_phy_driver[phy_type].phy_ops = phy_api_ops;
+
+	return SW_OK;
+
+}
+
+sw_error_t hsl_phy_api_ops_unregister(phy_type_t phy_type, hsl_phy_ops_t * phy_api_ops)
+{
+
+	ssdk_phy_driver[phy_type].phy_ops = NULL;
+
+	return SW_OK;
+
+}
+
+hsl_phy_ops_t *hsl_phy_api_ops_get(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	phy_type_t phytype = 0;
+
+	if (dev_id >= SW_MAX_NR_DEV)
+		return NULL;
+
+	phytype = phy_info[dev_id]->phy_type[port_id];
+	if(phytype == MAX_PHY_CHIP)
+	{
+		return NULL;
+	}
+
+	return ssdk_phy_driver[phytype].phy_ops;
+
+}
+
+sw_error_t phy_api_ops_init(phy_type_t phy_type)
+{
+
+	if (MAX_PHY_CHIP <= phy_type)
+		return SW_BAD_PARAM;
+
+	if(ssdk_phy_driver[phy_type].phy_ops != NULL)
+	{
+		kfree(ssdk_phy_driver[phy_type].phy_ops);
+		ssdk_phy_driver[phy_type].phy_ops = NULL;
+	}
+	return SW_OK;
+}
+/*qca808x_end*/
+a_bool_t hsl_port_is_sfp(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	a_bool_t sfp_port = 0;
+	a_uint32_t mode1, mode2;
+
+	sfp_port = ssdk_port_feature_get(dev_id, port_id, PHY_F_SFP);
+	if (sfp_port == A_TRUE) {
+		return A_TRUE;
+	}
+
+	mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1);
+	mode2 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE2);
+
+	if (((SSDK_PHYSICAL_PORT5 == port_id) &&
+			((mode1 == PORT_WRAPPER_10GBASE_R) ||
+			(mode1 == PORT_WRAPPER_SGMII_FIBER))) ||
+	    ((SSDK_PHYSICAL_PORT6 == port_id) &&
+			((mode2 == PORT_WRAPPER_10GBASE_R) ||
+			(mode2 == PORT_WRAPPER_SGMII_FIBER))))
+		return A_TRUE;
+	else
+		return A_FALSE;
+}
+/*qca808x_start*/
+a_uint32_t hsl_phyid_get(a_uint32_t dev_id,
+		a_uint32_t port_id, ssdk_init_cfg *cfg)
+{
+	a_uint16_t org_id = 0, rev_id = 0;
+	a_uint32_t reg_pad = 0, phy_id = 0;
+
+/*qca808x_end*/
+	if(ssdk_is_emulation(dev_id) && ssdk_emu_chip_ver_get(dev_id) == MP_GEPHY){
+		return MP_GEPHY;
+	}
+	if (hsl_port_is_sfp(dev_id, port_id)){
+		return SFP_PHY;
+	}
+/*qca808x_start*/
+	if (phy_info[dev_id]->phy_c45[port_id] == A_TRUE){
+		reg_pad = BIT(30) | BIT(16);
+	}
+
+#if defined(IN_PHY_I2C_MODE)
+	if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS) {
+		cfg->reg_func.i2c_get(dev_id,
+				phy_info[dev_id]->phy_address[port_id], reg_pad | 2, &org_id);
+		cfg->reg_func.i2c_get(dev_id,
+				phy_info[dev_id]->phy_address[port_id], reg_pad | 3, &rev_id);
+		if(((org_id << 16) | rev_id) == INVALID_PHY_ID) {
+			return QCA8081_PHY_V1_1;
+		}
+	}
+	else
+#endif
+	{
+		cfg->reg_func.mdio_get(dev_id,
+				phy_info[dev_id]->phy_address[port_id], reg_pad | 2, &org_id);
+		cfg->reg_func.mdio_get(dev_id,
+				phy_info[dev_id]->phy_address[port_id], reg_pad | 3, &rev_id);
+	}
+
+	phy_id = (org_id<<16) | rev_id;
+
+	return phy_id;
+}
+
+phy_type_t hsl_phytype_get_by_phyid(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	phy_type_t phytype = MAX_PHY_CHIP;
+
+	switch (phy_id)
+	{
+/*qca808x_end*/
+		case F1V1_PHY:
+		case F1V2_PHY:
+		case F1V3_PHY:
+		case F1V4_PHY:
+			phytype = F1_PHY_CHIP;
+			break;
+		case F2V1_PHY:
+			phytype = F2_PHY_CHIP;
+			break;
+		case MALIBU2PORT_PHY:
+		case MALIBU5PORT_PHY:
+			phytype = MALIBU_PHY_CHIP;
+			break;
+		case AQUANTIA_PHY_107:
+		case AQUANTIA_PHY_108:
+		case AQUANTIA_PHY_109:
+		case AQUANTIA_PHY_111:
+		case AQUANTIA_PHY_111B0:
+		case AQUANTIA_PHY_112:
+		case AQUANTIA_PHY_113C_A0:
+		case AQUANTIA_PHY_113C_A1:
+		case AQUANTIA_PHY_112C:
+			phytype = AQUANTIA_PHY_CHIP;
+			break;
+		case QCA8030_PHY:
+		case QCA8033_PHY:
+		case QCA8035_PHY:
+			phytype = QCA803X_PHY_CHIP;
+			break;
+		case SFP_PHY:
+			phytype = SFP_PHY_CHIP;
+			break;
+		case MP_GEPHY:
+			phytype = MPGE_PHY_CHIP;
+			break;
+/*qca808x_start*/
+		case QCA8081_PHY_V1_1:
+			phytype = QCA808X_PHY_CHIP;
+			break;
+		default:
+			phytype = MAX_PHY_CHIP;
+	}
+
+	return phytype;
+}
+/*qca808x_end*/
+sw_error_t hsl_phydriver_update(a_uint32_t dev_id, a_uint32_t port_id,
+	a_uint32_t mode)
+{
+	a_uint32_t phy_id;
+	phy_type_t phytype;
+	ssdk_init_cfg cfg;
+
+	cfg.chip_type = CHIP_HPPE;
+	if(port_id == SSDK_PHYSICAL_PORT5)
+	{
+		cfg.mac_mode1 = mode;
+	}
+	else if(port_id == SSDK_PHYSICAL_PORT6)
+	{
+		cfg.mac_mode2 = mode;
+	}
+	else
+	{
+		return SW_NOT_SUPPORTED;
+	}
+	if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS)
+	{
+		cfg.reg_func.i2c_get = hsl_phy_i2c_get;
+	}
+	else
+	{
+		cfg.reg_func.mdio_get = reduce_hsl_phy_get;
+	}
+	phy_id = hsl_phyid_get(dev_id, port_id, &cfg);
+	phytype = hsl_phytype_get_by_phyid(dev_id, phy_id);
+	SSDK_DEBUG("port_id is %x, phy_id is %x, phy_type is:%x\n",
+		port_id, phy_id, phytype);
+	if (MAX_PHY_CHIP != phytype)
+	{
+		phy_info[dev_id]->phy_type[port_id] = phytype;
+		ssdk_phy_driver[phytype].port_bmp[dev_id] |= (0x1 << port_id);
+	}
+
+	return SW_OK;
+}
+/*qca808x_start*/
+int ssdk_phy_driver_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+
+	int i = 0;
+	a_uint32_t phy_id = 0;
+	phy_type_t phytype = MAX_PHY_CHIP;
+
+	for (i = 0; i < SW_MAX_NR_PORT; i++)
+	{
+		if (port_bmp[dev_id] & (0x1 << i))
+		{
+/*qca808x_end*/
+			if(ssdk_port_feature_get(dev_id, i, PHY_F_FORCE)) {
+				continue;
+			}
+/*qca808x_start*/
+			phy_id = hsl_phyid_get(dev_id, i, cfg);
+			phytype = hsl_phytype_get_by_phyid(dev_id, phy_id);
+			if (MAX_PHY_CHIP != phytype) {
+				phy_info[dev_id]->phy_type[i] = phytype;
+				ssdk_phy_driver[phytype].port_bmp[dev_id] |= (0x1 << i);
+			} else {
+				SSDK_INFO("dev_id = %d, phy_adress = %d, phy_id = 0x%x phy"
+					"type doesn't match\n", dev_id,
+					phy_info[dev_id]->phy_address[i], phy_id);
+			}
+		}
+	}
+
+	for(i = 0; i < MAX_PHY_CHIP;i++) {
+		if(ssdk_phy_driver[i].port_bmp[dev_id] != 0 &&
+			ssdk_phy_driver[i].init != NULL) {
+			ssdk_phy_driver[i].init(dev_id, ssdk_phy_driver[i].port_bmp[dev_id]);
+		}
+	}
+	return 0;
+}
+
+#ifdef QCA808X_PORTS_INFO
+typedef struct {
+	a_uint32_t port_id;
+	a_uint32_t phy_address;
+	a_uint8_t phy_access_type;
+} qca808x_phy_info_t;
+/*5 is port_id, 0x1c is qca808x phy address, PHY_MDIO_ACCESS is mdio
+mode to access qca808x phy, PHY_I2C_ACCESS is I2C mode to access
+qca808x phy*/
+static qca808x_phy_info_t qca808x_phy_info[] = {
+	{5,0x7c,PHY_I2C_ACCESS}
+};
+static int qca_ssdk_qca808x_phy_info_init(a_uint32_t dev_id)
+{
+	a_uint32_t port_bmp = 0, port_id = 0, port_index = 0, port_index_max = 0;
+
+	port_index_max = sizeof(qca808x_phy_info)/(sizeof(qca808x_phy_info_t));
+	for(port_index = 0; port_index < port_index_max; port_index++) {
+		port_id = qca808x_phy_info[port_index].port_id;
+		port_bmp |= (1 << port_id);
+		/*qca808x phy address*/
+		phy_info[dev_id]->phy_address[port_id] =
+			qca808x_phy_info[port_index].phy_address;
+		/*qca808x access mode, 1:i2c, 0:mdio*/
+		phy_info[dev_id]->phy_access_type[port_id] =
+			qca808x_phy_info[port_index].phy_access_type;
+	}
+	qca_ssdk_port_bmp_set(dev_id, port_bmp);
+
+	return 0;
+}
+#endif
+
+int qca_ssdk_phy_info_init(a_uint32_t dev_id)
+{
+	a_uint32_t j = 0;
+	phy_info_t *phy_information;
+
+	phy_information = kzalloc(sizeof(phy_info_t), GFP_KERNEL);
+	if (phy_information == NULL) {
+		SSDK_ERROR("phy_information kzalloc failed!\n");
+		return -ENOMEM;
+	}
+	memset(phy_information, 0, sizeof(*phy_information));
+	phy_info[dev_id] = phy_information;
+
+	for (j = SSDK_PHYSICAL_PORT0; j < SW_MAX_NR_PORT; j ++)
+	{
+		phy_info[dev_id]->phy_type[j] = MAX_PHY_CHIP;
+		if(j == SSDK_PHYSICAL_PORT0)
+		{
+			phy_info[dev_id]->phy_address[j] = INVALID_PHY_ADDR;
+		}
+		else
+		{
+			phy_info[dev_id]->phy_address[j] = j - 1;
+		}
+	}
+#ifdef QCA808X_PORTS_INFO
+	qca_ssdk_qca808x_phy_info_init(dev_id);
+#endif
+
+	return 0;
+}
+void qca_ssdk_port_bmp_init(a_uint32_t dev_id)
+{
+	port_bmp[dev_id] = 0x3e;
+
+	return;
+}
+/*qca808x_end*/
+void hsl_phy_address_init(a_uint32_t dev_id, a_uint32_t i,
+			a_uint32_t value)
+{
+	phy_info[dev_id]->phy_address[i] = value;
+
+	return;
+}
+/*qca808x_start*/
+void qca_ssdk_port_bmp_set(a_uint32_t dev_id, a_uint32_t value)
+{
+	port_bmp[dev_id] = value;
+
+	return;
+}
+
+a_uint32_t qca_ssdk_port_bmp_get(a_uint32_t dev_id)
+{
+
+	return port_bmp[dev_id];
+}
+/*qca808x_end*/
+a_uint32_t qca_ssdk_phy_type_port_bmp_get(a_uint32_t dev_id,
+				phy_type_t phy_type)
+{
+
+	return ssdk_phy_driver[phy_type].port_bmp[dev_id];
+}
+
+void
+qca_ssdk_phy_address_set(a_uint32_t dev_id, a_uint32_t port_id,
+	a_uint32_t phy_addr)
+{
+	 phy_info[dev_id]->phy_address[port_id] = phy_addr;
+
+	 return;
+}
+
+a_uint32_t
+qca_ssdk_port_to_phy_mdio_fake_addr(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	return phy_info[dev_id]->phy_mdio_fake_address[port_id];
+}
+
+void qca_ssdk_phy_mdio_fake_address_set(a_uint32_t dev_id, a_uint32_t i,
+			a_uint32_t value)
+{
+	phy_info[dev_id]->phy_mdio_fake_address[i] = value;
+
+	return;
+}
+
+a_uint32_t
+qca_ssdk_phy_mdio_fake_addr_to_port(a_uint32_t dev_id, a_uint32_t phy_mdio_fake_addr)
+{
+	a_uint32_t i = 0;
+
+	for (i = 0; i < SW_MAX_NR_PORT; i ++)
+	{
+		if (phy_info[dev_id]->phy_mdio_fake_address[i] == phy_mdio_fake_addr)
+			return i;
+	}
+	SSDK_ERROR("doesn't match port_id to specified phy_mdio_fake_addr !\n");
+	return 0;
+}
+/*qca808x_start*/
+a_uint32_t
+qca_ssdk_port_to_phy_addr(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	return phy_info[dev_id]->phy_address[port_id];
+}
+
+a_uint32_t
+qca_ssdk_phy_addr_to_port(a_uint32_t dev_id, a_uint32_t phy_addr)
+{
+	a_uint32_t i = 0;
+
+	for (i = 0; i < SW_MAX_NR_PORT; i ++)
+	{
+		if (phy_info[dev_id]->phy_address[i] == phy_addr)
+			return i;
+	}
+	SSDK_ERROR("doesn't match port_id to specified phy_addr !\n");
+	return 0;
+}
+
+a_bool_t
+hsl_port_phy_combo_capability_get(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	if (dev_id >= SW_MAX_NR_DEV)
+		return A_FALSE;
+
+	return phy_info[dev_id]->phy_combo[port_id];
+}
+
+void
+hsl_port_phy_combo_capability_set(a_uint32_t dev_id, a_uint32_t port_id,
+		a_bool_t enable)
+{
+	if (dev_id >= SW_MAX_NR_DEV)
+		return;
+
+	phy_info[dev_id]->phy_combo[port_id] = enable;
+
+	return;
+}
+
+a_uint8_t
+hsl_port_phy_access_type_get(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	if (dev_id >= SW_MAX_NR_DEV)
+		return 0;
+
+	return phy_info[dev_id]->phy_access_type[port_id];
+}
+
+void
+hsl_port_phy_access_type_set(a_uint32_t dev_id, a_uint32_t port_id,
+		a_uint8_t access_type)
+{
+	if (dev_id >= SW_MAX_NR_DEV)
+		return;
+
+	phy_info[dev_id]->phy_access_type[port_id] = access_type;
+
+	return;
+}
+/*qca808x_end*/
+void
+hsl_port_phy_c45_capability_set(a_uint32_t dev_id, a_uint32_t port_id,
+		a_bool_t enable)
+{
+	phy_info[dev_id]->phy_c45[port_id] = enable;
+
+	return;
+}
+sw_error_t
+hsl_port_phy_serdes_reset(a_uint32_t dev_id)
+{
+	sw_error_t rv;
+	int i = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	for (i = 0; i < SW_MAX_NR_PORT; i++)
+	{
+		if (phy_info[dev_id]->phy_type[i] == MALIBU_PHY_CHIP)
+		{
+			SW_RTN_ON_NULL(phy_drv = hsl_phy_api_ops_get (dev_id, i));
+			if (NULL == phy_drv->phy_serdes_reset)
+				return SW_NOT_SUPPORTED;
+			rv = phy_drv->phy_serdes_reset(dev_id);
+			return rv;
+		}
+	}
+
+	return SW_OK;
+}
+
+sw_error_t hsl_port_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	phy_type_t phytype;
+
+	phytype = hsl_phy_type_get(dev_id, port_id);
+
+	if(ssdk_phy_driver[phytype].port_bmp[dev_id] != 0 &&
+			ssdk_phy_driver[phytype].init != NULL)
+	{
+		ssdk_phy_driver[phytype].init(dev_id,
+			ssdk_phy_driver[phytype].port_bmp[dev_id]);
+	}
+
+	return SW_OK;
+}
+
+a_uint32_t
+hsl_port_phyid_get(a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t phy_addr, phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	phy_drv = hsl_phy_api_ops_get (dev_id, port_id);
+	if (phy_drv == NULL) {
+		return INVALID_PHY_ID;
+	}
+	if (NULL == phy_drv->phy_id_get) {
+		return INVALID_PHY_ID;
+	}
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_addr);
+	if(rv) {
+		return INVALID_PHY_ID;
+	}
+
+	rv = phy_drv->phy_id_get (dev_id, phy_addr, &phy_id);
+	if(rv) {
+		return INVALID_PHY_ID;
+	}
+
+	return phy_id;
+}
+
+sw_error_t
+hsl_port_phy_mode_set(a_uint32_t dev_id, fal_port_interface_mode_t mode)
+{
+	sw_error_t rv;
+	a_uint32_t i = 0, phy_addr = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	for (i = 0; i < SW_MAX_NR_PORT; i++)
+	{
+		if (phy_info[dev_id]->phy_type[i] == MALIBU_PHY_CHIP)
+		{
+			SW_RTN_ON_NULL(phy_drv = hsl_phy_api_ops_get (dev_id, i));
+			if (NULL == phy_drv->phy_interface_mode_set)
+				return SW_NOT_SUPPORTED;
+
+			phy_addr = qca_ssdk_port_to_phy_addr(dev_id, i);
+			rv = phy_drv->phy_interface_mode_set(dev_id, phy_addr, mode);
+			return rv;
+		}
+	}
+
+	return SW_OK;
+}
+phy_type_t hsl_phy_type_get(a_uint32_t dev_id, a_uint32_t port_id)
+{
+
+	if (dev_id >= SW_MAX_NR_DEV)
+		return MAX_PHY_CHIP;
+
+	return phy_info[dev_id]->phy_type[port_id];
+}
+
+a_uint32_t hsl_port_phy_reset_gpio_get(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	return phy_info[dev_id]->phy_reset_gpio[port_id];
+}
+
+void hsl_port_phy_reset_gpio_set(a_uint32_t dev_id, a_uint32_t port_id,
+	a_uint32_t phy_reset_gpio)
+{
+	phy_info[dev_id]->phy_reset_gpio[port_id] = phy_reset_gpio;
+
+	return;
+}
+
+void hsl_port_phy_gpio_reset(a_uint32_t dev_id, a_uint32_t port_id)
+
+{
+	a_uint32_t gpio_num, ret = 0;
+
+	gpio_num = hsl_port_phy_reset_gpio_get(dev_id, port_id);
+
+	if(gpio_num == SSDK_INVALID_GPIO)
+	{
+		return;
+	}
+	ret = gpio_request(gpio_num, "phy_reset_gpio");
+	if(ret)
+	{
+		SSDK_ERROR("gpio request failed, ret:%d\n", ret);
+		return;
+	}
+	ret = gpio_direction_output(gpio_num, SSDK_GPIO_RESET);
+	if(ret)
+	{
+		SSDK_ERROR("when reset, gpio set failed, ret:%d\n",
+			ret);
+		return;
+	}
+	msleep(200);
+	gpio_set_value(gpio_num, SSDK_GPIO_RELEASE);
+	SSDK_INFO("GPIO%d reset PHY done\n", gpio_num);
+
+	gpio_free(gpio_num);
+
+	return;
+}
+
+void
+hsl_port_phy_dac_get(a_uint32_t dev_id, a_uint32_t port_id,
+	phy_dac_t *phy_dac)
+{
+	phy_dac->mdac = phy_info[dev_id]->phy_dac[port_id].mdac;
+	phy_dac->edac = phy_info[dev_id]->phy_dac[port_id].edac;
+
+	return;
+}
+
+void
+hsl_port_phy_dac_set(a_uint32_t dev_id, a_uint32_t port_id,
+	phy_dac_t phy_dac)
+{
+	phy_info[dev_id]->phy_dac[port_id].mdac = phy_dac.mdac;
+	phy_info[dev_id]->phy_dac[port_id].edac = phy_dac.edac;
+
+	return;
+}
+
+sw_error_t
+hsl_port_phydev_get(a_uint32_t dev_id, a_uint32_t port_id,
+	struct phy_device **phydev)
+{
+	struct qca_phy_priv *priv;
+	a_uint32_t phy_addr, pdev_addr;
+	const char *pdev_name;
+
+	priv = ssdk_phy_priv_data_get(dev_id);
+	SW_RTN_ON_NULL(priv);
+
+#if defined(IN_PHY_I2C_MODE)
+	if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS)
+	{
+		phy_addr = qca_ssdk_port_to_phy_mdio_fake_addr(dev_id, port_id);
+	}
+	else
+#endif
+	{
+		phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id);
+	}
+	SW_RTN_ON_NULL(phydev);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION (5, 0, 0))
+	*phydev = priv->miibus->phy_map[phy_addr];
+	SW_RTN_ON_NULL(*phydev);
+	pdev_addr = (*phydev)->addr;
+	pdev_name = dev_name(&((*phydev)->dev));
+#else
+	*phydev = mdiobus_get_phy(priv->miibus, phy_addr);
+	SW_RTN_ON_NULL(*phydev);
+	pdev_addr = (*phydev)->mdio.addr;
+	pdev_name = phydev_name(*phydev);
+#endif
+	if(*phydev == NULL)
+	{
+		SSDK_ERROR("port %d phydev is NULL\n", port_id);
+		return SW_NOT_INITIALIZED;
+	}
+	SSDK_DEBUG("phy[%d]: device %s, driver %s\n",
+		pdev_addr, pdev_name,
+		(*phydev)->drv ? (*phydev)->drv->name : "unknown");
+
+	return SW_OK;
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0))
+static sw_error_t
+hsl_phy_adv_to_linkmode_adv(a_uint32_t autoadv, a_ulong_t *advertising)
+{
+	linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+			advertising, autoadv & FAL_PHY_ADV_PAUSE);
+	linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+			advertising, autoadv & FAL_PHY_ADV_ASY_PAUSE);
+
+	linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
+			advertising, autoadv & FAL_PHY_ADV_10T_HD);
+	linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
+			advertising, autoadv & FAL_PHY_ADV_10T_FD);
+
+	linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
+			advertising, autoadv & FAL_PHY_ADV_100TX_HD);
+	linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
+			advertising, autoadv & FAL_PHY_ADV_100TX_FD);
+
+	linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+			advertising, autoadv & FAL_PHY_ADV_1000T_FD);
+
+	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
+			advertising, autoadv & FAL_PHY_ADV_2500T_FD);
+
+	linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
+			advertising, autoadv & FAL_PHY_ADV_5000T_FD);
+
+	linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
+			advertising, autoadv & FAL_PHY_ADV_10000T_FD);
+
+	SSDK_DEBUG("autoadv:0x%x, advertising::0x%lx\n",
+		autoadv, *advertising);
+
+	return SW_OK;
+}
+
+sw_error_t
+hsl_port_phydev_adv_update(a_uint32_t dev_id, a_uint32_t port_id,
+	a_uint32_t autoadv)
+{
+	sw_error_t rv = SW_OK;
+	struct phy_device *phydev;
+
+	rv = hsl_port_phydev_get(dev_id, port_id, &phydev);
+	SW_RTN_ON_ERROR(rv);
+	rv = hsl_phy_adv_to_linkmode_adv(autoadv, phydev->advertising);
+
+	return rv;
+}
+#endif
+
+/*qca808x_start*/
+sw_error_t ssdk_phy_driver_cleanup(void)
+{
+	a_uint32_t i = 0, j = 0;
+
+	for (i = 0; i < MAX_PHY_CHIP;i++) {
+		for (j = 0; j < SW_MAX_NR_DEV; j++) {
+			if (ssdk_phy_driver[i].port_bmp[j] != 0 &&
+			    ssdk_phy_driver[i].exit != NULL) {
+				ssdk_phy_driver[i].exit(j, ssdk_phy_driver[i].port_bmp[j]);
+			}
+		}
+		if(ssdk_phy_driver[i].phy_ops != NULL)
+		{
+			kfree(ssdk_phy_driver[i].phy_ops);
+			ssdk_phy_driver[i].phy_ops = NULL;
+		}
+	}
+
+	for(i = 0; i < SW_MAX_NR_DEV;i++) {
+
+		if(phy_info[i] != NULL)
+		{
+			kfree(phy_info[i]);
+			phy_info[i] = NULL;
+		}
+	}
+	return SW_OK;
+}
+/*qca808x_end*/
diff --git a/qca-ssdk/src/hsl/phy/malibu_phy.c b/qca-ssdk/src/hsl/phy/malibu_phy.c
new file mode 100644
index 0000000..1f4dba1
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/malibu_phy.c
@@ -0,0 +1,2871 @@
+/*
+ * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "fal_port_ctrl.h"
+#include "hsl_api.h"
+#include "hsl.h"
+#include "malibu_phy.h"
+#include "hsl_phy.h"
+#include "ssdk_plat.h"
+
+static a_uint32_t first_phy_addr = MAX_PHY_ADDR;
+
+static a_uint16_t
+_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg)
+{
+	sw_error_t rv;
+	a_uint16_t phy_data = 0;
+
+	HSL_PHY_GET(rv, dev_id, phy_addr, reg, &phy_data);
+	if (SW_OK != rv)
+		return 0xFFFF;
+
+	return phy_data;
+
+}
+
+static sw_error_t
+_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
+	       a_uint16_t phy_data)
+{
+	sw_error_t rv;
+
+	HSL_PHY_SET(rv, dev_id, phy_addr, reg, phy_data);
+
+	return rv;
+}
+
+/* #define malibu_phy_reg_read _phy_reg_read  */
+/* #define malibu_phy_reg_write _phy_reg_write */
+
+/******************************************************************************
+*
+* malibu_phy_mii_read - mii register read
+*
+* mii register read
+*/
+a_uint16_t
+malibu_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id)
+{
+ 	return _phy_reg_read(dev_id, phy_id, reg_id);
+
+}
+
+/******************************************************************************
+*
+* malibu_phy_mii_write - mii register write
+*
+* mii register write
+*/
+sw_error_t
+malibu_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id,
+		       a_uint16_t reg_val)
+{
+
+       _phy_reg_write(dev_id,phy_id, reg_id, reg_val);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+*  phy4 medium is fiber 100fx
+*
+*  get phy4 medium is 100fx
+*/
+static a_bool_t __medium_is_fiber_100fx(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data = 0;
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SGMII_STATUS);
+
+	if (phy_data & MALIBU_PHY4_AUTO_FX100_SELECT) {
+		return A_TRUE;
+	}
+	/* Link down */
+	if ((!(phy_data & MALIBU_PHY4_AUTO_COPPER_SELECT)) &&
+	    (!(phy_data & MALIBU_PHY4_AUTO_BX1000_SELECT)) &&
+	    (!(phy_data & MALIBU_PHY4_AUTO_SGMII_SELECT))) {
+
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG);
+		if ((phy_data & MALIBU_PHY4_PREFER_FIBER)
+		    && (!(phy_data & MALIBU_PHY4_FIBER_MODE_1000BX))) {
+			return A_TRUE;
+		}
+	}
+
+	return A_FALSE;
+}
+
+/******************************************************************************
+*
+*  phy4 prfer medium
+*
+*  get phy4 prefer medum, fiber or copper;
+*/
+static malibu_phy_medium_t __phy_prefer_medium_get(a_uint32_t dev_id,
+						   a_uint32_t phy_id)
+{
+	a_uint16_t phy_medium = 0;
+
+	phy_medium =
+	    malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG);
+
+	return ((phy_medium & MALIBU_PHY4_PREFER_FIBER) ?
+		MALIBU_PHY_MEDIUM_FIBER : MALIBU_PHY_MEDIUM_COPPER);
+}
+
+/******************************************************************************
+*
+*  phy4 activer medium
+*
+*  get phy4 current active medium, fiber or copper;
+*/
+static malibu_phy_medium_t __phy_active_medium_get(a_uint32_t dev_id,
+						   a_uint32_t phy_id)
+{
+	a_uint16_t phy_data = 0;
+	a_uint16_t phy_mode = 0;
+
+	phy_mode = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG);
+	phy_mode &= 0x000f;
+
+       if (phy_mode == MALIBU_PHY_PSGMII_AMDET)  {
+
+		phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SGMII_STATUS);
+
+		if ((phy_data & MALIBU_PHY4_AUTO_COPPER_SELECT)) {
+			return MALIBU_PHY_MEDIUM_COPPER;
+		} else if ((phy_data & MALIBU_PHY4_AUTO_BX1000_SELECT)) {
+			return MALIBU_PHY_MEDIUM_FIBER;	/*PHY_MEDIUM_FIBER_BX1000 */
+		} else if ((phy_data & MALIBU_PHY4_AUTO_FX100_SELECT)) {
+			return MALIBU_PHY_MEDIUM_FIBER;	/*PHY_MEDIUM_FIBER_FX100 */
+		}
+		/* link down */
+		return __phy_prefer_medium_get(dev_id, phy_id);
+       }  else if ((phy_mode == MALIBU_PHY_PSGMII_BASET) ||(phy_mode == MALIBU_PHY_SGMII_BASET) )  {
+       	return MALIBU_PHY_MEDIUM_COPPER;
+       }  else if ((phy_mode == MALIBU_PHY_PSGMII_BX1000) ||(phy_mode == MALIBU_PHY_PSGMII_FX100)) {
+       	return MALIBU_PHY_MEDIUM_FIBER;
+       } else {
+       	return MALIBU_PHY_MEDIUM_COPPER;
+       }
+}
+
+/******************************************************************************
+*
+*  phy4 copper page or fiber page select
+*
+*  set phy4 copper or fiber page
+*/
+
+static sw_error_t __phy_reg_pages_sel(a_uint32_t dev_id, a_uint32_t phy_id,
+				      malibu_phy_reg_pages_t phy_reg_pages)
+{
+	a_uint16_t reg_pages = 0;
+	reg_pages = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG);
+
+	if (phy_reg_pages == MALIBU_PHY_COPPER_PAGES) {
+		reg_pages |= 0x8000;
+	} else if (phy_reg_pages == MALIBU_PHY_SGBX_PAGES) {
+		reg_pages &= ~0x8000;
+	} else
+		return SW_BAD_PARAM;
+
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG, reg_pages);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+*  phy4 reg pages selection by active medium
+*
+*  phy4 reg pages selection
+*/
+static sw_error_t __phy_reg_pages_sel_by_active_medium(a_uint32_t dev_id,
+						       a_uint32_t phy_id)
+{
+	malibu_phy_medium_t phy_medium;
+	malibu_phy_reg_pages_t reg_pages;
+
+	phy_medium = __phy_active_medium_get(dev_id, phy_id);
+	if (phy_medium == MALIBU_PHY_MEDIUM_FIBER) {
+		reg_pages = MALIBU_PHY_SGBX_PAGES;
+	} else if (phy_medium == MALIBU_PHY_MEDIUM_COPPER) {
+
+		reg_pages = MALIBU_PHY_COPPER_PAGES;
+	} else
+
+		return SW_BAD_VALUE;
+
+	return __phy_reg_pages_sel(dev_id, phy_id, reg_pages);
+}
+
+/******************************************************************************
+*
+* malibu_phy_debug_write - debug port write
+*
+* debug port write
+*/
+sw_error_t
+malibu_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id,
+		       a_uint16_t reg_val)
+{
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_DEBUG_PORT_ADDRESS, reg_id);
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_DEBUG_PORT_DATA, reg_val);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_debug_read - debug port read
+*
+* debug port read
+*/
+a_uint16_t
+malibu_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id)
+{
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_DEBUG_PORT_ADDRESS, reg_id);
+	return malibu_phy_reg_read(dev_id, phy_id, MALIBU_DEBUG_PORT_DATA);
+}
+
+/******************************************************************************
+*
+* malibu_phy_mmd_write - PHY MMD register write
+*
+* PHY MMD register write
+*/
+sw_error_t
+malibu_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id,
+		     a_uint16_t mmd_num, a_uint16_t reg_id, a_uint16_t reg_val)
+{
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_MMD_CTRL_REG, mmd_num);
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_MMD_DATA_REG, reg_id);
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_MMD_CTRL_REG,
+			     0x4000 | mmd_num);
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_MMD_DATA_REG, reg_val);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_mmd_read -  PHY MMD register read
+*
+* PHY MMD register read
+*/
+a_uint16_t
+malibu_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id,
+		    a_uint16_t mmd_num, a_uint16_t reg_id)
+{
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_MMD_CTRL_REG, mmd_num);
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_MMD_DATA_REG, reg_id);
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_MMD_CTRL_REG,
+			     0x4000 | mmd_num);
+
+	return malibu_phy_reg_read(dev_id, phy_id, MALIBU_MMD_DATA_REG);
+}
+
+/******************************************************************************
+*
+* malibu_phy_get_speed - Determines the speed of phy ports associated with the
+* specified device.
+*/
+
+sw_error_t
+malibu_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+		     fal_port_speed_t * speed)
+{
+	a_uint16_t phy_data;
+
+	if (phy_id == COMBO_PHY_ID) {
+		__phy_reg_pages_sel_by_active_medium(dev_id, phy_id);
+	}
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_STATUS);
+
+	switch (phy_data & MALIBU_STATUS_SPEED_MASK) {
+	case MALIBU_STATUS_SPEED_1000MBS:
+		*speed = FAL_SPEED_1000;
+		break;
+	case MALIBU_STATUS_SPEED_100MBS:
+		*speed = FAL_SPEED_100;
+		break;
+	case MALIBU_STATUS_SPEED_10MBS:
+		*speed = FAL_SPEED_10;
+		break;
+	default:
+		return SW_READ_ERROR;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_get_duplex - Determines the speed of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+malibu_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+		      fal_port_duplex_t * duplex)
+{
+	a_uint16_t phy_data;
+
+	if (phy_id == COMBO_PHY_ID) {
+		__phy_reg_pages_sel_by_active_medium(dev_id, phy_id);
+	}
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_STATUS);
+
+	//read duplex
+	if (phy_data & MALIBU_STATUS_FULL_DUPLEX)
+		*duplex = FAL_FULL_DUPLEX;
+	else
+		*duplex = FAL_HALF_DUPLEX;
+
+	return SW_OK;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* malibu_phy_reset - reset the phy
+*
+* reset the phy
+*/
+sw_error_t malibu_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+
+	if (phy_id == COMBO_PHY_ID)
+		__phy_reg_pages_sel_by_active_medium(dev_id, phy_id);
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL);
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL,
+			     phy_data | MALIBU_CTRL_SOFTWARE_RESET);
+
+	return SW_OK;
+}
+#endif
+/******************************************************************************
+*
+* malibu_phy_set_powersave - set power saving status
+*
+* set power saving status
+*/
+sw_error_t
+malibu_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	a_bool_t  status;
+
+	if (phy_id == COMBO_PHY_ID) {
+		if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+	}
+
+	if (enable == A_TRUE) {
+		malibu_phy_get_8023az (dev_id,phy_id,&status);
+		if (status == A_FALSE) {
+			phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+						   MALIBU_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL);
+			phy_data &= ~(1<<14);
+			malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+			     MALIBU_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, phy_data);
+		}
+		phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+						   MALIBU_PHY_MMD3_ADDR_CLD_CTRL5);
+		phy_data &= ~(1<<14);
+		malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+			     MALIBU_PHY_MMD3_ADDR_CLD_CTRL5, phy_data);
+		phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+						   MALIBU_PHY_MMD3_ADDR_CLD_CTRL3);
+		phy_data &= ~(1<<15);
+		malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+			     MALIBU_PHY_MMD3_ADDR_CLD_CTRL3, phy_data);
+
+	} else {
+		phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+						   MALIBU_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL);
+		phy_data|= (1<<14);
+		malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+			     MALIBU_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, phy_data);
+		phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+						   MALIBU_PHY_MMD3_ADDR_CLD_CTRL5);
+		phy_data|= (1<<14);
+		malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+			     MALIBU_PHY_MMD3_ADDR_CLD_CTRL5, phy_data);
+		phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+						   MALIBU_PHY_MMD3_ADDR_CLD_CTRL3);
+		phy_data|= (1<<15);
+		malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+			     MALIBU_PHY_MMD3_ADDR_CLD_CTRL3, phy_data);
+
+	}
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, 0x9040);
+
+	return SW_OK;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* malibu_phy_get_powersave - get power saving status
+*
+* set power saving status
+*/
+sw_error_t
+malibu_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+	a_uint16_t phy_data1;
+
+	if (phy_id == COMBO_PHY_ID) {
+		if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+	}
+
+	phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+					   MALIBU_PHY_MMD3_ADDR_CLD_CTRL5);
+	phy_data1 = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+					   MALIBU_PHY_MMD3_ADDR_CLD_CTRL3);
+	if (!(phy_data& 0x4000) && !(phy_data1 & 0x8000)) {
+		*enable = A_TRUE;
+	}
+	if ((phy_data& 0x4000) && (phy_data1 & 0x8000)) {
+		*enable = A_FALSE;
+	}
+	return SW_OK;
+}
+#endif
+/******************************************************************************
+*
+* malibu_phy_set_802.3az
+*
+* set 802.3az status
+*/
+sw_error_t
+malibu_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+
+	if (phy_id == COMBO_PHY_ID) {
+		if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+	}
+
+	phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+				       MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL);
+	if (enable == A_TRUE) {
+		phy_data |= 0x0006;
+
+		malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+			     MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data);
+	} else {
+		phy_data &= ~0x0006;
+
+		malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+			     MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data);
+	}
+
+	malibu_phy_restart_autoneg(dev_id, phy_id);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_get_8023az status
+*
+* get 8023az status
+*/
+sw_error_t
+malibu_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+	if (phy_id == COMBO_PHY_ID) {
+		if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+	}
+
+	*enable = A_FALSE;
+
+	phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+				       MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL);
+
+	if ((phy_data & 0x0004) && (phy_data & 0x0002))
+		*enable = A_TRUE;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_set_hibernate - set hibernate status
+*
+* set hibernate status
+*/
+sw_error_t
+malibu_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_DEBUG_PORT_ADDRESS,
+			     MALIBU_DEBUG_PHY_HIBERNATION_CTRL);
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_DEBUG_PORT_DATA);
+
+	if (enable == A_TRUE) {
+		phy_data |= 0x8000;
+	} else {
+		phy_data &= ~0x8000;
+	}
+
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_DEBUG_PORT_DATA, phy_data);
+
+	return SW_OK;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* malibu_phy_get_hibernate - get hibernate status
+*
+* get hibernate status
+*/
+sw_error_t
+malibu_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	*enable = A_FALSE;
+
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_DEBUG_PORT_ADDRESS,
+			     MALIBU_DEBUG_PHY_HIBERNATION_CTRL);
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_DEBUG_PORT_DATA);
+
+	if (phy_data & 0x8000)
+		*enable = A_TRUE;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_set combo medium type
+*
+* set combo medium fiber or copper
+*/
+sw_error_t
+malibu_phy_set_combo_prefer_medium(a_uint32_t dev_id, a_uint32_t phy_id,
+				   fal_port_medium_t phy_medium)
+{
+	a_uint16_t phy_data;
+	if (phy_id != COMBO_PHY_ID)
+		return SW_NOT_SUPPORTED;
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG);
+
+	if (phy_medium == PHY_MEDIUM_FIBER) {
+		phy_data |= MALIBU_PHY4_PREFER_FIBER;
+		phy_data &= ~0x8000;
+	} else if (phy_medium == PHY_MEDIUM_COPPER) {
+		phy_data &= ~MALIBU_PHY4_PREFER_FIBER;
+		phy_data |= 0x8000;
+	} else {
+		return SW_BAD_PARAM;
+	}
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG, phy_data);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_get combo medium type
+*
+* get combo medium fiber or copper
+*/
+sw_error_t
+malibu_phy_get_combo_prefer_medium(a_uint32_t dev_id, a_uint32_t phy_id,
+				   fal_port_medium_t * phy_medium)
+{
+	a_uint16_t phy_data;
+	if (phy_id != COMBO_PHY_ID)
+		return SW_NOT_SUPPORTED;
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG);
+
+	*phy_medium =
+	    (phy_data & MALIBU_PHY4_PREFER_FIBER) ? PHY_MEDIUM_FIBER :
+	    PHY_MEDIUM_COPPER;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_get current combo medium type copper or fiber
+*
+* get current combo medium type
+*/
+sw_error_t
+malibu_phy_get_combo_current_medium_type(a_uint32_t dev_id, a_uint32_t phy_id,
+					 fal_port_medium_t * phy_medium)
+{
+
+	if (phy_id != COMBO_PHY_ID)
+		return SW_NOT_SUPPORTED;
+
+	*phy_medium = __phy_active_medium_get(dev_id, phy_id);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_set fiber mode 1000bx or 100fx
+*
+* set combo fbier mode
+*/
+sw_error_t
+malibu_phy_set_combo_fiber_mode(a_uint32_t dev_id, a_uint32_t phy_id,
+				fal_port_fiber_mode_t fiber_mode)
+{
+	a_uint16_t phy_data;
+	if (phy_id != COMBO_PHY_ID)
+		return SW_NOT_SUPPORTED;
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG);
+
+	if (fiber_mode == PHY_FIBER_1000BX) {
+		phy_data |= MALIBU_PHY4_FIBER_MODE_1000BX;
+	} else if (fiber_mode == PHY_FIBER_100FX) {
+		phy_data &= ~MALIBU_PHY4_FIBER_MODE_1000BX;
+	} else {
+		return SW_BAD_PARAM;
+	}
+
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG, phy_data);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_get fiber mode 1000bx or 100fx
+*
+* get combo fbier mode
+*/
+sw_error_t
+malibu_phy_get_combo_fiber_mode(a_uint32_t dev_id, a_uint32_t phy_id,
+				fal_port_fiber_mode_t * fiber_mode)
+{
+	a_uint16_t phy_data;
+	if (phy_id != COMBO_PHY_ID)
+		return SW_NOT_SUPPORTED;
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG);
+
+	*fiber_mode =
+	    (phy_data & MALIBU_PHY4_FIBER_MODE_1000BX) ? PHY_FIBER_1000BX :
+	    PHY_FIBER_100FX;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_set_mdix - 
+*
+* set phy mdix configuraiton
+*/
+sw_error_t
+malibu_phy_set_mdix(a_uint32_t dev_id, a_uint32_t phy_id,
+		    fal_port_mdix_mode_t mode)
+{
+	a_uint16_t phy_data;
+
+	if ((phy_id == COMBO_PHY_ID)
+	    && (MALIBU_PHY_MEDIUM_COPPER !=
+		__phy_active_medium_get(dev_id, phy_id)))
+
+		return SW_NOT_SUPPORTED;
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_CONTROL);
+
+	if (mode == PHY_MDIX_AUTO) {
+		phy_data |= MALIBU_PHY_MDIX_AUTO;
+	} else if (mode == PHY_MDIX_MDIX) {
+		phy_data &= ~MALIBU_PHY_MDIX_AUTO;
+		phy_data |= MALIBU_PHY_MDIX;
+	} else if (mode == PHY_MDIX_MDI) {
+		phy_data &= ~MALIBU_PHY_MDIX_AUTO;
+	} else {
+		return SW_BAD_PARAM;
+	}
+
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_SPEC_CONTROL, phy_data);
+
+	malibu_phy_reset(dev_id, phy_id);
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_get_mdix 
+*
+* get phy mdix configuration
+*/
+sw_error_t
+malibu_phy_get_mdix(a_uint32_t dev_id, a_uint32_t phy_id,
+		    fal_port_mdix_mode_t * mode)
+{
+	a_uint16_t phy_data;
+
+	if ((phy_id == COMBO_PHY_ID)
+	    && (MALIBU_PHY_MEDIUM_COPPER !=
+		__phy_active_medium_get(dev_id, phy_id)))
+
+		return SW_NOT_SUPPORTED;
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_CONTROL);
+
+	if ((phy_data & MALIBU_PHY_MDIX_AUTO) == MALIBU_PHY_MDIX_AUTO) {
+		*mode = PHY_MDIX_AUTO;
+	} else if ((phy_data & MALIBU_PHY_MDIX) == MALIBU_PHY_MDIX) {
+		*mode = PHY_MDIX_MDIX;
+	} else {
+		*mode = PHY_MDIX_MDI;
+	}
+
+	return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* malibu_phy_get_mdix status
+*
+* get phy mdix status
+*/
+sw_error_t
+malibu_phy_get_mdix_status(a_uint32_t dev_id, a_uint32_t phy_id,
+			   fal_port_mdix_status_t * mode)
+{
+	a_uint16_t phy_data;
+
+	if (phy_id == COMBO_PHY_ID) {
+
+		if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+
+		__phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_COPPER_PAGES);
+	}
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_STATUS);
+
+	*mode =
+	    (phy_data & MALIBU_PHY_MDIX_STATUS) ? PHY_MDIX_STATUS_MDIX :
+	    PHY_MDIX_STATUS_MDI;
+
+	return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* malibu_phy_set_local_loopback
+*
+* set phy local loopback
+*/
+sw_error_t
+malibu_phy_set_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	fal_port_speed_t old_speed;
+
+       if (enable == A_TRUE) {
+	     if (phy_id == COMBO_PHY_ID) {
+
+		 if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id)) {
+
+			__phy_reg_pages_sel(dev_id, phy_id,
+					    MALIBU_PHY_SGBX_PAGES);
+
+			if (__medium_is_fiber_100fx(dev_id, phy_id)) {
+
+				phy_data = MALIBU_100M_LOOPBACK;
+
+				} else {
+                                   phy_data = MALIBU_1000M_LOOPBACK;
+					}
+				malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, phy_data);
+				return SW_OK;
+			}
+                 __phy_reg_pages_sel(dev_id, phy_id,
+					    MALIBU_PHY_COPPER_PAGES);
+		}
+
+			  malibu_phy_get_speed(dev_id, phy_id, &old_speed);
+			  if (old_speed == FAL_SPEED_1000) {
+			  	phy_data = MALIBU_1000M_LOOPBACK;
+			  	} else if (old_speed == FAL_SPEED_100) {
+			  	   phy_data = MALIBU_100M_LOOPBACK;
+			  	} else if (old_speed == FAL_SPEED_10) {
+			  	   phy_data = MALIBU_10M_LOOPBACK;
+			  	} else {
+                                return SW_FAIL;
+			  	}
+         } else {
+            if (phy_id == COMBO_PHY_ID) {
+		 if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id)) {
+
+			__phy_reg_pages_sel(dev_id, phy_id,
+					    MALIBU_PHY_SGBX_PAGES);
+			
+			} else {
+	                 __phy_reg_pages_sel(dev_id, phy_id,
+					    MALIBU_PHY_COPPER_PAGES);
+			}
+           	 }
+			  phy_data = MALIBU_COMMON_CTRL;
+		 }
+
+
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, phy_data);
+	return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* malibu_phy_get_local_loopback
+*
+* get phy local loopback
+*/
+sw_error_t
+malibu_phy_get_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	if (phy_id == COMBO_PHY_ID) {
+
+		__phy_reg_pages_sel_by_active_medium(dev_id, phy_id);
+
+	}
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL);
+
+	if (phy_data & MALIBU_LOCAL_LOOPBACK_ENABLE) {
+		*enable = A_TRUE;
+	} else {
+		*enable = A_FALSE;
+	}
+
+	return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* malibu_phy_set_remote_loopback
+*
+* set phy remote loopback
+*/
+sw_error_t
+malibu_phy_set_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+			       a_bool_t enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+					MALIBU_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL);
+
+	if (enable == A_TRUE) {
+		phy_data |= 0x0001;
+	} else {
+		phy_data &= ~0x0001;
+	}
+
+	malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+			     MALIBU_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL,
+			     phy_data);
+	return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* malibu_phy_get_remote_loopback
+*
+* get phy remote loopback
+*/
+sw_error_t
+malibu_phy_get_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+			       a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+					MALIBU_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL);
+
+	if (phy_data & 0x0001) {
+		*enable = A_TRUE;
+	} else {
+		*enable = A_FALSE;
+	}
+
+	return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* malibu_phy_cdt - cable diagnostic test
+*
+* cable diagnostic test
+*/
+
+static inline fal_cable_status_t _phy_cdt_status_mapping(a_uint16_t status)
+{
+	fal_cable_status_t status_mapping = FAL_CABLE_STATUS_INVALID;
+
+	if (0 == status)
+		status_mapping = FAL_CABLE_STATUS_INVALID;
+	else if (1 == status)
+		status_mapping = FAL_CABLE_STATUS_NORMAL;
+	else if (2 == status)
+		status_mapping = FAL_CABLE_STATUS_OPENED;
+	else if (3 == status)
+		status_mapping = FAL_CABLE_STATUS_SHORT;
+
+	return status_mapping;
+}
+
+static sw_error_t malibu_phy_cdt_start(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t status = 0;
+	a_uint16_t ii = 100;
+
+	if (phy_id == COMBO_PHY_ID) {
+
+		if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+
+		__phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_COPPER_PAGES);
+	}
+
+	/* RUN CDT */
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CDT_CONTROL,
+			     RUN_CDT | CABLE_LENGTH_UNIT);
+	do {
+		aos_mdelay(30);
+		status =
+		    malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CDT_CONTROL);
+	}
+	while ((status & RUN_CDT) && (--ii));
+
+	return SW_OK;
+}
+
+sw_error_t
+malibu_phy_cdt_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		   fal_port_cdt_t * port_cdt)
+{
+	a_uint16_t status = 0;
+	a_uint16_t cable_delta_time = 0;
+	int i;
+
+	if ((!port_cdt) || (phy_id > 4)) {
+		return SW_FAIL;
+	}
+
+
+	malibu_phy_cdt_start(dev_id, phy_id);
+
+	/* Get cable status */
+	status = malibu_phy_mmd_read(dev_id, phy_id, 3, 0x8064);
+
+
+
+	for (i = 0; i < 4; i++) {
+		switch (i) {
+		case 0:
+			port_cdt->pair_a_status = (status >> 12) & 0x3;
+			/* Get Cable Length value */
+			cable_delta_time =
+			    malibu_phy_mmd_read(dev_id, phy_id, 3, 0x8065);
+			/* the actual cable length equals to CableDeltaTime * 0.824 */
+			port_cdt->pair_a_len =
+			    ((cable_delta_time & 0xff) * 800) / 1000;
+
+			break;
+		case 1:
+			port_cdt->pair_b_status = (status >> 8) & 0x3;
+			/* Get Cable Length value */
+			cable_delta_time =
+			    malibu_phy_mmd_read(dev_id, phy_id, 3, 0x8066);
+			/* the actual cable length equals to CableDeltaTime * 0.824 */
+			port_cdt->pair_b_len =
+			    ((cable_delta_time & 0xff) * 800) / 1000;
+			break;
+		case 2:
+			port_cdt->pair_c_status = (status >> 4) & 0x3;
+			/* Get Cable Length value */
+			cable_delta_time =
+			    malibu_phy_mmd_read(dev_id, phy_id, 3, 0x8067);
+			/* the actual cable length equals to CableDeltaTime * 0.824 */
+			port_cdt->pair_c_len =
+			    ((cable_delta_time & 0xff) * 800) / 1000;
+			break;
+		case 3:
+			port_cdt->pair_d_status = status & 0x3;
+			/* Get Cable Length value */
+			cable_delta_time =
+			    malibu_phy_mmd_read(dev_id, phy_id, 3, 0x8068);
+			/* the actual cable length equals to CableDeltaTime * 0.824 */
+			port_cdt->pair_d_len =
+			    ((cable_delta_time & 0xff) * 800) / 1000;
+			break;
+		default:
+			break;
+		}
+	}
+
+
+	return SW_OK;
+}
+
+sw_error_t
+malibu_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+	       fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+	fal_port_cdt_t malibu_port_cdt;
+
+	if (phy_id == COMBO_PHY_ID) {
+
+		if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+
+		__phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_COPPER_PAGES);
+	}
+
+	if ((mdi_pair >= 4) || (phy_id > 4)) {
+		//There are only 4 mdi pairs in 1000BASE-T
+		return SW_BAD_PARAM;
+	}
+
+	malibu_phy_cdt_get(dev_id, phy_id, &malibu_port_cdt);
+
+	switch (mdi_pair) {
+	case 0:
+		*cable_status =
+		    _phy_cdt_status_mapping(malibu_port_cdt.pair_a_status);
+		/* Get Cable Length value */
+		*cable_len = malibu_port_cdt.pair_a_len;
+		break;
+	case 1:
+		*cable_status =
+		    _phy_cdt_status_mapping(malibu_port_cdt.pair_b_status);
+		/* Get Cable Length value */
+		*cable_len = malibu_port_cdt.pair_b_len;
+		break;
+	case 2:
+		*cable_status =
+		    _phy_cdt_status_mapping(malibu_port_cdt.pair_c_status);
+		/* Get Cable Length value */
+		*cable_len = malibu_port_cdt.pair_c_len;
+		break;
+	case 3:
+		*cable_status =
+		    _phy_cdt_status_mapping(malibu_port_cdt.pair_d_status);
+		/* Get Cable Length value */
+		*cable_len = malibu_port_cdt.pair_d_len;
+		break;
+	default:
+		break;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_reset_done - reset the phy
+*
+* reset the phy
+*/
+a_bool_t malibu_phy_reset_done(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	a_uint16_t ii = 200;
+
+	if (phy_id == COMBO_PHY_ID)
+		__phy_reg_pages_sel_by_active_medium(dev_id, phy_id);
+
+	do {
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL);
+		aos_mdelay(10);
+	}
+	while ((!MALIBU_RESET_DONE(phy_data)) && --ii);
+
+	if (ii == 0)
+		return A_FALSE;
+
+	return A_TRUE;
+}
+
+/******************************************************************************
+*
+* malibu_autoneg_done
+*
+* malibu_autoneg_done
+*/
+a_bool_t malibu_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	a_uint16_t ii = 200;
+
+	if (phy_id == COMBO_PHY_ID)
+		__phy_reg_pages_sel_by_active_medium(dev_id, phy_id);
+
+	do {
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_STATUS);
+		aos_mdelay(10);
+	}
+	while ((!MALIBU_AUTONEG_DONE(phy_data)) && --ii);
+
+	if (ii == 0)
+		return A_FALSE;
+
+	return A_TRUE;
+}
+
+/******************************************************************************
+*
+* malibu_phy_Speed_Duplex_Resolved
+ - reset the phy
+*
+* reset the phy
+*/
+a_bool_t malibu_phy_speed_duplex_resolved(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	a_uint16_t ii = 200;
+
+	if (phy_id == COMBO_PHY_ID)
+		__phy_reg_pages_sel_by_active_medium(dev_id, phy_id);
+
+	do {
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_STATUS);
+		aos_mdelay(10);
+	}
+	while ((!MALIBU_SPEED_DUPLEX_RESOVLED(phy_data)) && --ii);
+
+	if (ii == 0)
+		return A_FALSE;
+
+	return A_TRUE;
+}
+#endif
+/******************************************************************************
+*
+* malibu_phy_off - power off the phy 
+*
+* Power off the phy
+*/
+sw_error_t malibu_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	if (phy_id == COMBO_PHY_ID) {
+		__phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_SGBX_PAGES);
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL);
+		malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL,
+				     phy_data | MALIBU_CTRL_POWER_DOWN);
+
+		__phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_COPPER_PAGES);
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL);
+		malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL,
+				     phy_data | MALIBU_CTRL_POWER_DOWN);
+	} else {
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL);
+		malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL,
+				     phy_data | MALIBU_CTRL_POWER_DOWN);
+	}
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_on - power on the phy 
+*
+* Power on the phy
+*/
+sw_error_t malibu_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	if (phy_id == COMBO_PHY_ID) {
+		__phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_SGBX_PAGES);
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL);
+		malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL,
+				     phy_data & ~MALIBU_CTRL_POWER_DOWN);
+
+		__phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_COPPER_PAGES);
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL);
+		malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL,
+				     phy_data & ~MALIBU_CTRL_POWER_DOWN);
+
+	} else {
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL);
+		malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL,
+				     phy_data & ~MALIBU_CTRL_POWER_DOWN);
+	}
+
+	aos_mdelay(200);
+
+	return SW_OK;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* malibu_phy_get_ability - get the phy ability
+*
+*
+*/
+sw_error_t
+malibu_phy_get_ability(a_uint32_t dev_id, a_uint32_t phy_id,
+		       a_uint32_t * ability)
+{
+	a_uint16_t phy_data;
+
+	*ability = 0;
+	if (phy_id == COMBO_PHY_ID)
+		__phy_reg_pages_sel_by_active_medium(dev_id, phy_id);
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_STATUS);
+
+	if (phy_data & MALIBU_STATUS_AUTONEG_CAPS)
+		*ability |= FAL_PHY_AUTONEG_CAPS;
+
+	if (phy_data & MALIBU_STATUS_100T2_HD_CAPS)
+		*ability |= FAL_PHY_100T2_HD_CAPS;
+
+	if (phy_data & MALIBU_STATUS_100T2_FD_CAPS)
+		*ability |= FAL_PHY_100T2_FD_CAPS;
+
+	if (phy_data & MALIBU_STATUS_10T_HD_CAPS)
+		*ability |= FAL_PHY_10T_HD_CAPS;
+
+	if (phy_data & MALIBU_STATUS_10T_FD_CAPS)
+		*ability |= FAL_PHY_10T_FD_CAPS;
+
+	if (phy_data & MALIBU_STATUS_100X_HD_CAPS)
+		*ability |= FAL_PHY_100X_HD_CAPS;
+
+	if (phy_data & MALIBU_STATUS_100X_FD_CAPS)
+		*ability |= FAL_PHY_100X_FD_CAPS;
+
+	if (phy_data & MALIBU_STATUS_100T4_CAPS)
+		*ability |= FAL_PHY_100T4_CAPS;
+
+	if (phy_data & MALIBU_STATUS_EXTENDED_STATUS) {
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id, MALIBU_EXTENDED_STATUS);
+
+		if (phy_data & MALIBU_STATUS_1000T_FD_CAPS) {
+			*ability |= FAL_PHY_1000T_FD_CAPS;
+		}
+
+		if (phy_data & MALIBU_STATUS_1000X_FD_CAPS) {
+			*ability |= FAL_PHY_1000X_FD_CAPS;
+		}
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_get_ability - get the phy ability
+*
+*
+*/
+sw_error_t
+malibu_phy_get_partner_ability(a_uint32_t dev_id, a_uint32_t phy_id,
+			       a_uint32_t * ability)
+{
+	a_uint16_t phy_data;
+
+	*ability = 0;
+
+	if (phy_id == COMBO_PHY_ID)
+		__phy_reg_pages_sel_by_active_medium(dev_id, phy_id);
+
+	phy_data =
+	    malibu_phy_reg_read(dev_id, phy_id, MALIBU_LINK_PARTNER_ABILITY);
+
+	if (phy_data & MALIBU_LINK_10BASETX_HALF_DUPLEX)
+		*ability |= FAL_PHY_PART_10T_HD;
+
+	if (phy_data & MALIBU_LINK_10BASETX_FULL_DUPLEX)
+		*ability |= FAL_PHY_PART_10T_FD;
+
+	if (phy_data & MALIBU_LINK_100BASETX_HALF_DUPLEX)
+		*ability |= FAL_PHY_PART_100TX_HD;
+
+	if (phy_data & MALIBU_LINK_100BASETX_FULL_DUPLEX)
+		*ability |= FAL_PHY_PART_100TX_FD;
+
+	if (phy_data & MALIBU_LINK_NPAGE) {
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id,
+					MALIBU_1000BASET_STATUS);
+
+		if (phy_data & MALIBU_LINK_1000BASETX_FULL_DUPLEX)
+			*ability |= FAL_PHY_PART_1000T_FD;
+	}
+
+	return SW_OK;
+}
+#endif
+/******************************************************************************
+*
+* malibu_phy_status - test to see if the specified phy link is alive
+*
+* RETURNS:
+*    A_TRUE  --> link is alive
+*    A_FALSE --> link is down
+*/
+a_bool_t malibu_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	if (phy_id == COMBO_PHY_ID)
+		__phy_reg_pages_sel_by_active_medium(dev_id, phy_id);
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_STATUS);
+
+	if (phy_data & MALIBU_STATUS_LINK_PASS)
+		return A_TRUE;
+
+	return A_FALSE;
+}
+
+/******************************************************************************
+*
+* malibu_set_autoneg_adv - set the phy autoneg Advertisement
+*
+*/
+sw_error_t
+malibu_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+			   a_uint32_t autoneg)
+{
+	a_uint16_t phy_data = 0;
+	if (phy_id == COMBO_PHY_ID) {
+		if (__medium_is_fiber_100fx(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+
+		if (MALIBU_PHY_MEDIUM_COPPER ==
+		    __phy_active_medium_get(dev_id, phy_id)) {
+
+			__phy_reg_pages_sel(dev_id, phy_id,
+					    MALIBU_PHY_COPPER_PAGES);
+			phy_data =
+			    malibu_phy_reg_read(dev_id, phy_id,
+						MALIBU_AUTONEG_ADVERT);
+			phy_data &= ~MALIBU_ADVERTISE_MEGA_ALL;
+			phy_data &=
+			    ~(MALIBU_ADVERTISE_PAUSE |
+			      MALIBU_ADVERTISE_ASYM_PAUSE);
+
+			if (autoneg & FAL_PHY_ADV_100TX_FD) {
+				phy_data |= MALIBU_ADVERTISE_100FULL;
+			}
+			if (autoneg & FAL_PHY_ADV_100TX_HD) {
+				phy_data |= MALIBU_ADVERTISE_100HALF;
+			}
+			if (autoneg & FAL_PHY_ADV_10T_FD) {
+				phy_data |= MALIBU_ADVERTISE_10FULL;
+			}
+			if (autoneg & FAL_PHY_ADV_10T_HD) {
+				phy_data |= MALIBU_ADVERTISE_10HALF;
+			}
+			if (autoneg & FAL_PHY_ADV_PAUSE) {
+				phy_data |= MALIBU_ADVERTISE_PAUSE;
+			}
+			if (autoneg & FAL_PHY_ADV_ASY_PAUSE) {
+				phy_data |= MALIBU_ADVERTISE_ASYM_PAUSE;
+			}
+			__phy_reg_pages_sel(dev_id, phy_id,
+					    MALIBU_PHY_COPPER_PAGES);
+			if (autoneg & FAL_PHY_ADV_1000T_FD) {
+				phy_data |= MALIBU_EXTENDED_NEXT_PAGE_EN;
+			} else {
+				phy_data &= ~MALIBU_EXTENDED_NEXT_PAGE_EN;
+			}
+			malibu_phy_reg_write(dev_id, phy_id,
+					     MALIBU_AUTONEG_ADVERT, phy_data);
+
+			phy_data =
+			    malibu_phy_reg_read(dev_id, phy_id,
+						MALIBU_1000BASET_CONTROL);
+			phy_data &= ~MALIBU_ADVERTISE_1000FULL;
+			phy_data &= ~MALIBU_ADVERTISE_1000HALF;
+
+			if (autoneg & FAL_PHY_ADV_1000T_FD) {
+				phy_data |= MALIBU_ADVERTISE_1000FULL;
+			}
+			malibu_phy_reg_write(dev_id, phy_id,
+					     MALIBU_1000BASET_CONTROL,
+					     phy_data);
+		} else {
+
+			__phy_reg_pages_sel(dev_id, phy_id,
+					    MALIBU_PHY_SGBX_PAGES);
+			phy_data =
+			    malibu_phy_reg_read(dev_id, phy_id,
+						MALIBU_AUTONEG_ADVERT);
+			phy_data &= ~MALIBU_BX_ADVERTISE_ALL;
+
+			if (autoneg & FAL_PHY_ADV_1000BX_FD) {
+				phy_data |= MALIBU_BX_ADVERTISE_1000FULL;
+			}
+			if (autoneg & FAL_PHY_ADV_1000BX_HD) {
+				phy_data |= MALIBU_BX_ADVERTISE_1000HALF;
+			}
+			if (autoneg & FAL_PHY_ADV_PAUSE) {
+				phy_data |= MALIBU_BX_ADVERTISE_PAUSE;
+			}
+			if (autoneg & FAL_PHY_ADV_ASY_PAUSE) {
+				phy_data |= MALIBU_BX_ADVERTISE_ASYM_PAUSE;
+			}
+			__phy_reg_pages_sel(dev_id, phy_id,
+					    MALIBU_PHY_SGBX_PAGES);
+
+			malibu_phy_reg_write(dev_id, phy_id,
+					     MALIBU_AUTONEG_ADVERT, phy_data);
+		}
+	} else {
+
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id, MALIBU_AUTONEG_ADVERT);
+		phy_data &= ~MALIBU_ADVERTISE_MEGA_ALL;
+		phy_data &=
+		    ~(MALIBU_ADVERTISE_PAUSE | MALIBU_ADVERTISE_ASYM_PAUSE);
+
+		if (autoneg & FAL_PHY_ADV_100TX_FD) {
+			phy_data |= MALIBU_ADVERTISE_100FULL;
+		}
+		if (autoneg & FAL_PHY_ADV_100TX_HD) {
+			phy_data |= MALIBU_ADVERTISE_100HALF;
+		}
+		if (autoneg & FAL_PHY_ADV_10T_FD) {
+			phy_data |= MALIBU_ADVERTISE_10FULL;
+		}
+		if (autoneg & FAL_PHY_ADV_10T_HD) {
+			phy_data |= MALIBU_ADVERTISE_10HALF;
+		}
+		if (autoneg & FAL_PHY_ADV_PAUSE) {
+			phy_data |= MALIBU_ADVERTISE_PAUSE;
+		}
+		if (autoneg & FAL_PHY_ADV_ASY_PAUSE) {
+			phy_data |= MALIBU_ADVERTISE_ASYM_PAUSE;
+		}
+		malibu_phy_reg_write(dev_id, phy_id, MALIBU_AUTONEG_ADVERT,
+				     phy_data);
+
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id,
+					MALIBU_1000BASET_CONTROL);
+		phy_data &= ~MALIBU_ADVERTISE_1000FULL;
+		phy_data &= ~MALIBU_ADVERTISE_1000HALF;
+
+		if (autoneg & FAL_PHY_ADV_1000T_FD) {
+			phy_data |= MALIBU_ADVERTISE_1000FULL;
+		}
+		malibu_phy_reg_write(dev_id, phy_id, MALIBU_1000BASET_CONTROL,
+				     phy_data);
+
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_get_autoneg_adv - get the phy autoneg Advertisement
+*
+*/
+sw_error_t
+malibu_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+			   a_uint32_t * autoneg)
+{
+	a_uint16_t phy_data = 0;
+
+	*autoneg = 0;
+
+	if (phy_id == COMBO_PHY_ID) {
+		if (__medium_is_fiber_100fx(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+
+		if (MALIBU_PHY_MEDIUM_COPPER ==
+		    __phy_active_medium_get(dev_id, phy_id)) {
+
+			__phy_reg_pages_sel(dev_id, phy_id,
+					    MALIBU_PHY_COPPER_PAGES);
+
+			phy_data =
+			    malibu_phy_reg_read(dev_id, phy_id,
+						MALIBU_AUTONEG_ADVERT);
+
+			if (phy_data & MALIBU_ADVERTISE_100FULL)
+				*autoneg |= FAL_PHY_ADV_100TX_FD;
+
+			if (phy_data & MALIBU_ADVERTISE_100HALF)
+				*autoneg |= FAL_PHY_ADV_100TX_HD;
+
+			if (phy_data & MALIBU_ADVERTISE_10FULL)
+				*autoneg |= FAL_PHY_ADV_10T_FD;
+
+			if (phy_data & MALIBU_ADVERTISE_10HALF)
+				*autoneg |= FAL_PHY_ADV_10T_HD;
+
+			if (phy_data & MALIBU_ADVERTISE_PAUSE)
+				*autoneg |= FAL_PHY_ADV_PAUSE;
+
+			if (phy_data & MALIBU_ADVERTISE_ASYM_PAUSE)
+				*autoneg |= FAL_PHY_ADV_ASY_PAUSE;
+
+			phy_data =
+			    malibu_phy_reg_read(dev_id, phy_id,
+						MALIBU_1000BASET_CONTROL);
+
+			if (phy_data & MALIBU_ADVERTISE_1000FULL)
+				*autoneg |= FAL_PHY_ADV_1000T_FD;
+
+		} else {
+
+			__phy_reg_pages_sel(dev_id, phy_id,
+					    MALIBU_PHY_SGBX_PAGES);
+			phy_data =
+			    malibu_phy_reg_read(dev_id, phy_id,
+						MALIBU_AUTONEG_ADVERT);
+
+			if (phy_data & MALIBU_BX_ADVERTISE_PAUSE)
+				*autoneg |= FAL_PHY_ADV_PAUSE;
+
+			if (phy_data & MALIBU_BX_ADVERTISE_ASYM_PAUSE)
+				*autoneg |= FAL_PHY_ADV_ASY_PAUSE;
+
+			if (phy_data & MALIBU_BX_ADVERTISE_1000HALF)
+				*autoneg |= FAL_PHY_ADV_1000BX_HD;
+
+			if (phy_data & MALIBU_BX_ADVERTISE_1000FULL)
+				*autoneg |= FAL_PHY_ADV_1000BX_FD;
+		}
+	} else {
+
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id, MALIBU_AUTONEG_ADVERT);
+
+		if (phy_data & MALIBU_ADVERTISE_100FULL)
+			*autoneg |= FAL_PHY_ADV_100TX_FD;
+
+		if (phy_data & MALIBU_ADVERTISE_100HALF)
+			*autoneg |= FAL_PHY_ADV_100TX_HD;
+
+		if (phy_data & MALIBU_ADVERTISE_10FULL)
+			*autoneg |= FAL_PHY_ADV_10T_FD;
+
+		if (phy_data & MALIBU_ADVERTISE_10HALF)
+			*autoneg |= FAL_PHY_ADV_10T_HD;
+
+		if (phy_data & MALIBU_ADVERTISE_PAUSE)
+			*autoneg |= FAL_PHY_ADV_PAUSE;
+
+		if (phy_data & MALIBU_ADVERTISE_ASYM_PAUSE)
+			*autoneg |= FAL_PHY_ADV_ASY_PAUSE;
+
+		phy_data =
+		    malibu_phy_reg_read(dev_id, phy_id,
+					MALIBU_1000BASET_CONTROL);
+		if (phy_data & MALIBU_ADVERTISE_1000FULL)
+			*autoneg |= FAL_PHY_ADV_1000T_FD;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_enable_autonego 
+*
+* Power off the phy
+*/
+a_bool_t malibu_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+
+	if (phy_id == COMBO_PHY_ID) {
+
+		if (__medium_is_fiber_100fx(dev_id, phy_id))
+			return A_FALSE;
+		__phy_reg_pages_sel_by_active_medium(dev_id, phy_id);
+	}
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL);
+
+	if (phy_data & MALIBU_CTRL_AUTONEGOTIATION_ENABLE)
+		return A_TRUE;
+
+	return A_FALSE;
+}
+
+/******************************************************************************
+*
+* malibu_restart_autoneg - restart the phy autoneg
+*
+*/
+sw_error_t malibu_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data = 0;
+
+	if (phy_id == COMBO_PHY_ID) {
+		if (__medium_is_fiber_100fx(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+		__phy_reg_pages_sel_by_active_medium(dev_id, phy_id);
+	}
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL);
+
+	phy_data |= MALIBU_CTRL_AUTONEGOTIATION_ENABLE;
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL,
+			     phy_data | MALIBU_CTRL_RESTART_AUTONEGOTIATION);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_enable_autonego 
+*
+*/
+sw_error_t malibu_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data = 0;
+
+	if (phy_id == COMBO_PHY_ID) {
+		if (__medium_is_fiber_100fx(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+		__phy_reg_pages_sel_by_active_medium(dev_id, phy_id);
+	}
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL);
+
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL,
+			     phy_data | MALIBU_CTRL_AUTONEGOTIATION_ENABLE);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_set_speed - Determines the speed of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+malibu_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+		     fal_port_speed_t speed)
+{
+	a_uint16_t phy_data = 0;
+	fal_port_duplex_t old_duplex;
+
+	if (phy_id == COMBO_PHY_ID) {
+		if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id))
+
+			return SW_NOT_SUPPORTED;
+
+		__phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_COPPER_PAGES);
+	}
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL);
+
+	malibu_phy_get_duplex(dev_id, phy_id, &old_duplex);
+
+	if (old_duplex == FAL_FULL_DUPLEX) {
+		phy_data |= MALIBU_CTRL_FULL_DUPLEX;
+
+		if (FAL_SPEED_1000 == speed) {
+			phy_data |= MALIBU_CTRL_SPEED_1000;
+			phy_data &= ~MALIBU_CTRL_SPEED_100;
+			phy_data |= MALIBU_CTRL_AUTONEGOTIATION_ENABLE;
+		} else if (FAL_SPEED_100 == speed) {
+			phy_data |= MALIBU_CTRL_SPEED_100;
+			phy_data &= ~MALIBU_CTRL_SPEED_1000;
+			phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE;
+		} else if (FAL_SPEED_10 == speed){
+			phy_data &= ~MALIBU_CTRL_SPEED_100;
+			phy_data &= ~MALIBU_CTRL_SPEED_1000;
+			phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE;
+		} else {
+		return SW_BAD_PARAM;
+		}
+	} else if (old_duplex == FAL_HALF_DUPLEX) {
+		phy_data &= ~MALIBU_CTRL_FULL_DUPLEX;
+
+		if (FAL_SPEED_100 == speed) {
+			phy_data |= MALIBU_CTRL_SPEED_100;
+			phy_data &= ~MALIBU_CTRL_SPEED_1000;
+			phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE;
+		} else if (FAL_SPEED_10 == speed) {
+			phy_data &= ~MALIBU_CTRL_SPEED_100;
+			phy_data &= ~MALIBU_CTRL_SPEED_1000;
+			phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE;
+		} else if (FAL_SPEED_1000 == speed){
+            phy_data |= MALIBU_CTRL_FULL_DUPLEX;
+            phy_data |= MALIBU_CTRL_SPEED_1000;
+		    phy_data &= ~MALIBU_CTRL_SPEED_100;
+		    phy_data |= MALIBU_CTRL_AUTONEGOTIATION_ENABLE;
+		} else {
+		return SW_BAD_PARAM;
+	       }
+	} else {
+		return SW_FAIL;
+	}
+
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, phy_data);
+	return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* malibu_phy_set_duplex - Determines the speed of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+malibu_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+		      fal_port_duplex_t duplex)
+{
+	a_uint16_t phy_data = 0;
+	fal_port_speed_t old_speed;
+
+	if (phy_id == COMBO_PHY_ID) {
+
+		if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id)) {
+
+			__phy_reg_pages_sel(dev_id, phy_id,
+					    MALIBU_PHY_SGBX_PAGES);
+
+			phy_data =
+			    malibu_phy_reg_read(dev_id, phy_id,
+						MALIBU_PHY_CONTROL);
+
+			if (__medium_is_fiber_100fx(dev_id, phy_id)) {
+
+				if (duplex == FAL_FULL_DUPLEX) {
+					phy_data |= MALIBU_CTRL_FULL_DUPLEX;
+				} else if (duplex == FAL_HALF_DUPLEX) {
+					phy_data &= ~MALIBU_CTRL_FULL_DUPLEX;
+				} else {
+					return SW_BAD_PARAM;
+				}
+				} else {
+
+					if (duplex == FAL_FULL_DUPLEX) {
+					phy_data |= MALIBU_CTRL_FULL_DUPLEX;
+					phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE;
+				} else if (duplex == FAL_HALF_DUPLEX) {
+					phy_data &= ~MALIBU_CTRL_FULL_DUPLEX;
+					phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE;
+				} else {
+					return SW_BAD_PARAM;
+				}
+					}
+				malibu_phy_reg_write(dev_id, phy_id,
+						     MALIBU_PHY_CONTROL,
+						     phy_data);
+
+				return SW_OK;
+			}
+			__phy_reg_pages_sel(dev_id, phy_id,
+					    MALIBU_PHY_COPPER_PAGES);
+		}
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL);
+
+       malibu_phy_get_speed(dev_id, phy_id, &old_speed);
+
+       if (old_speed == FAL_SPEED_1000) {
+
+	    phy_data |= MALIBU_CTRL_SPEED_1000;
+	    phy_data &= ~MALIBU_CTRL_SPEED_100;
+	    phy_data |= MALIBU_CTRL_AUTONEGOTIATION_ENABLE;
+
+		if (duplex == FAL_FULL_DUPLEX) {
+		phy_data |= MALIBU_CTRL_FULL_DUPLEX;
+
+		} else if (duplex == FAL_HALF_DUPLEX) {
+
+		return SW_NOT_SUPPORTED;
+		} else {
+		return SW_BAD_PARAM;
+		}
+         } else if (old_speed == FAL_SPEED_100) {
+	       phy_data |= MALIBU_CTRL_SPEED_100;
+		phy_data &= ~MALIBU_CTRL_SPEED_1000;
+		phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE;
+
+         if (duplex == FAL_FULL_DUPLEX) {
+		phy_data |= MALIBU_CTRL_FULL_DUPLEX;
+		
+		} else if (duplex == FAL_HALF_DUPLEX) {
+
+		phy_data &= ~MALIBU_CTRL_FULL_DUPLEX;
+
+		} else {
+		return SW_BAD_PARAM;
+		} 
+          } else if (old_speed == FAL_SPEED_10) {
+          	phy_data &= ~MALIBU_CTRL_SPEED_100;
+		phy_data &= ~MALIBU_CTRL_SPEED_1000;
+		phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE;
+
+         if (duplex == FAL_FULL_DUPLEX) {
+		phy_data |= MALIBU_CTRL_FULL_DUPLEX;
+		
+		} else if (duplex == FAL_HALF_DUPLEX) {
+
+		phy_data &= ~MALIBU_CTRL_FULL_DUPLEX;
+
+		} else {
+		return SW_BAD_PARAM;
+		}
+          } else {
+             return SW_FAIL;
+          }
+		malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, phy_data);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_get_phy_id - get the phy id
+*
+*/
+sw_error_t
+malibu_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *phy_data)
+{
+	a_uint16_t org_id, rev_id;
+
+	org_id = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_ID1);
+	rev_id = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_ID2);
+
+	*phy_data = ((org_id & 0xffff) << 16) | (rev_id & 0xffff);
+
+	return SW_OK;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* malibu_phy_set wol frame mac address
+*
+* set phy wol frame mac address
+*/
+sw_error_t
+malibu_phy_set_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id,
+			       fal_mac_addr_t * mac)
+{
+	a_uint16_t phy_data1;
+	a_uint16_t phy_data2;
+	a_uint16_t phy_data3;
+
+	phy_data1 = (mac->uc[0] << 8) | mac->uc[1];
+	phy_data2 = (mac->uc[2] << 8) | mac->uc[3];
+	phy_data3 = (mac->uc[4] << 8) | mac->uc[5];
+
+	malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+			     MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL1, phy_data1);
+
+	malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+			     MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL2, phy_data2);
+
+	malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+			     MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL3, phy_data3);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_get wol frame mac address
+*
+* get phy wol frame mac address
+*/
+sw_error_t
+malibu_phy_get_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id,
+			       fal_mac_addr_t * mac)
+{
+	a_uint16_t phy_data1;
+	a_uint16_t phy_data2;
+	a_uint16_t phy_data3;
+
+	phy_data1 = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+					MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL1);
+
+	phy_data2 = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+					MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL2);
+
+	phy_data3 = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+					MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL3);
+
+	mac->uc[0] = (phy_data1 >> 8);
+	mac->uc[1] = (phy_data1 & 0x00ff);
+	mac->uc[2] = (phy_data2 >> 8);
+	mac->uc[3] = (phy_data2 & 0x00ff);
+	mac->uc[4] = (phy_data3 >> 8);
+	mac->uc[5] = (phy_data3 & 0x00ff);
+	phy_data2 = (mac->uc[2] << 8) | mac->uc[3];
+	phy_data3 = (mac->uc[4] << 8) | mac->uc[5];
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_set wol enable or disable
+*
+* set phy wol enable or disable
+*/
+sw_error_t
+malibu_phy_set_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+				       MALIBU_PHY_MMD3_WOL_CTRL);
+
+	if (enable == A_TRUE) {
+		phy_data |= 0x0020;
+	} else {
+		phy_data &= ~0x0020;
+	}
+
+	malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+			     MALIBU_PHY_MMD3_WOL_CTRL, phy_data);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_get_wol status
+*
+* get wol status
+*/
+sw_error_t
+malibu_phy_get_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	*enable = A_FALSE;
+
+	phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+				       MALIBU_PHY_MMD3_WOL_CTRL);
+
+	if (phy_data & 0x0020)
+		*enable = A_TRUE;
+
+	return SW_OK;
+}
+#endif
+/******************************************************************************
+*
+* malibu_serdes_reset - malibu psgmii serdes reset
+*
+* reset serdes
+*/
+sw_error_t
+malibu_phy_serdes_reset(a_uint32_t dev_id)
+{
+
+	malibu_phy_reg_write(dev_id, first_phy_addr + MALIBU_PHY_PSGMII_ADDR_INC,
+				MALIBU_MODE_RESET_REG, MALIBU_MODE_CHANAGE_RESET);
+	mdelay(100);
+	malibu_phy_reg_write(dev_id, first_phy_addr + MALIBU_PHY_PSGMII_ADDR_INC,
+				MALIBU_MODE_RESET_REG, MALIBU_MODE_RESET_DEFAULT_VALUE);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_interface mode set
+*
+* set malibu phy interface mode
+*/
+sw_error_t
+malibu_phy_interface_set_mode(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_interface_mode_t interface_mode)
+{
+	a_uint16_t phy_data;
+
+	if ((phy_id < first_phy_addr) ||
+				(phy_id > (first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)))
+		return SW_NOT_SUPPORTED;
+
+	phy_data = malibu_phy_reg_read(dev_id,
+		first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG);
+	phy_data &= 0xfff0;
+
+	if (interface_mode == PHY_PSGMII_BASET) {
+		phy_data |= MALIBU_PHY_PSGMII_BASET;
+	} else if (interface_mode == PHY_PSGMII_BX1000) {
+		phy_data |= MALIBU_PHY_PSGMII_BX1000;
+	} else if (interface_mode == PHY_PSGMII_FX100) {
+		phy_data |= MALIBU_PHY_PSGMII_FX100;
+	} else if (interface_mode == PHY_PSGMII_AMDET) {
+	       phy_data |= MALIBU_PHY_PSGMII_AMDET;
+	} else if (interface_mode == PHY_SGMII_BASET ||
+		interface_mode == PORT_QSGMII) {
+	       phy_data |= MALIBU_PHY_SGMII_BASET;
+	} else if (interface_mode == PHY_PSGMII_FIBER) {
+		phy_data |= MALIBU_PHY_PSGMII_AMDET;
+	} else {
+		return SW_BAD_PARAM;
+	}
+
+	malibu_phy_reg_write(dev_id,
+		first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG, phy_data);
+
+	/* reset operation */
+	malibu_phy_serdes_reset(dev_id);
+
+	if (interface_mode == PHY_PSGMII_FIBER) {
+		malibu_phy_reg_write(dev_id, first_phy_addr + MALIBU_PHY_MAX_ADDR_INC,
+			MALIBU_PHY_CHIP_CONFIG, MALIBU_MODECTRL_DFLT);
+		malibu_phy_reg_write(dev_id, first_phy_addr + MALIBU_PHY_MAX_ADDR_INC,
+			MALIBU_PHY_CONTROL, MALIBU_MIICTRL_DFLT);
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_interface mode get
+*
+* get malibu phy interface mode
+*/
+sw_error_t
+malibu_phy_interface_get_mode(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_interface_mode_t *interface_mode)
+{
+	a_uint16_t phy_data;
+	a_uint16_t copper_mode;
+
+	if ((phy_id < first_phy_addr) ||
+				(phy_id > (first_phy_addr + MALIBU_PHY_MAX_ADDR_INC))) {
+		return SW_NOT_SUPPORTED;
+	}
+
+	phy_data = malibu_phy_reg_read(dev_id,
+		first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG);
+	copper_mode = ((phy_data & MALIBU_PHY_COPPER_MODE) >> 0xf);
+	phy_data &= 0x000f;
+
+	switch (phy_data) {
+		case MALIBU_PHY_PSGMII_BASET:
+			*interface_mode = PHY_PSGMII_BASET;
+			break;
+		case  MALIBU_PHY_PSGMII_BX1000:
+			*interface_mode = PHY_PSGMII_BX1000;
+			break;
+		case MALIBU_PHY_PSGMII_FX100:
+			*interface_mode = PHY_PSGMII_FX100;
+			break;
+		case MALIBU_PHY_PSGMII_AMDET:
+			if (copper_mode) {
+				*interface_mode = PHY_PSGMII_AMDET;
+			 } else {
+				if (phy_id == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
+					*interface_mode = PHY_PSGMII_FIBER;
+				else
+					*interface_mode = PHY_PSGMII_AMDET;
+			 }
+			break;
+		case MALIBU_PHY_SGMII_BASET:
+			if (phy_id == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
+				*interface_mode = PHY_SGMII_BASET;
+			else
+				*interface_mode = PORT_QSGMII;
+			break;
+		default:
+			*interface_mode = PORT_INTERFACE_MODE_MAX;
+			break;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_interface mode status get
+*
+* get malibu phy interface mode status
+*/
+sw_error_t
+malibu_phy_interface_get_mode_status(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_interface_mode_t *interface_mode_status)
+{
+	a_uint16_t phy_data;
+	a_uint16_t copper_mode;
+
+	if ((phy_id < first_phy_addr) ||
+			       (phy_id > (first_phy_addr + MALIBU_PHY_MAX_ADDR_INC))) {
+		return SW_NOT_SUPPORTED;
+	}
+
+	phy_data = malibu_phy_reg_read(dev_id,
+		first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG);
+	copper_mode = ((phy_data & MALIBU_PHY_COPPER_MODE) >> 0xf);
+	phy_data &= 0x00f0;
+	phy_data = (phy_data >>4);
+
+	switch (phy_data) {
+		case MALIBU_PHY_PSGMII_BASET:
+			*interface_mode_status = PHY_PSGMII_BASET;
+			break;
+		case  MALIBU_PHY_PSGMII_BX1000:
+			*interface_mode_status = PHY_PSGMII_BX1000;
+			break;
+		case MALIBU_PHY_PSGMII_FX100:
+			*interface_mode_status = PHY_PSGMII_FX100;
+			break;
+		case MALIBU_PHY_PSGMII_AMDET:
+			if (copper_mode) {
+				*interface_mode_status = PHY_PSGMII_BASET;
+			} else {
+				if (phy_id == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
+					*interface_mode_status = PHY_PSGMII_FIBER;
+				else
+					*interface_mode_status = PHY_PSGMII_BASET;
+			}
+			break;
+		case MALIBU_PHY_SGMII_BASET:
+			if (phy_id == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
+				*interface_mode_status = PHY_SGMII_BASET;
+			else
+				*interface_mode_status = PORT_QSGMII;
+			break;
+		default:
+			*interface_mode_status = PORT_INTERFACE_MODE_MAX;
+			break;
+	}
+
+	return SW_OK;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* malibu_phy_intr_mask_set - Set interrupt mask with the
+* specified device.
+*/
+sw_error_t
+malibu_phy_intr_mask_set(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_uint32_t intr_mask_flag)
+{
+	a_uint16_t phy_data = 0;
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_INTR_MASK);
+
+	if (FAL_PHY_INTR_STATUS_UP_CHANGE & intr_mask_flag) {
+		phy_data |= MALIBU_INTR_STATUS_UP_CHANGE;
+	} else {
+		phy_data &= (~MALIBU_INTR_STATUS_UP_CHANGE);
+	}
+
+	if (FAL_PHY_INTR_STATUS_DOWN_CHANGE & intr_mask_flag) {
+		phy_data |= MALIBU_INTR_STATUS_DOWN_CHANGE;
+	} else {
+		phy_data &= (~MALIBU_INTR_STATUS_DOWN_CHANGE);
+	}
+
+	if (FAL_PHY_INTR_SPEED_CHANGE & intr_mask_flag) {
+		phy_data |= MALIBU_INTR_SPEED_CHANGE;
+	} else {
+		phy_data &= (~MALIBU_INTR_SPEED_CHANGE);
+	}
+
+	if (FAL_PHY_INTR_DUPLEX_CHANGE & intr_mask_flag) {
+		phy_data |= MALIBU_INTR_DUPLEX_CHANGE;
+	} else {
+		phy_data &= (~MALIBU_INTR_DUPLEX_CHANGE);
+	}
+
+	if (FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE & intr_mask_flag) {
+		phy_data |= MALIBU_INTR_BX_FX_STATUS_UP_CHANGE;
+	} else {
+		phy_data &= (~MALIBU_INTR_BX_FX_STATUS_UP_CHANGE);
+	}
+
+	if (FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE & intr_mask_flag) {
+		phy_data |= MALIBU_INTR_BX_FX_STATUS_DOWN_CHANGE;
+	} else {
+		phy_data &= (~MALIBU_INTR_BX_FX_STATUS_DOWN_CHANGE);
+	}
+
+	if (FAL_PHY_INTR_MEDIA_STATUS_CHANGE & intr_mask_flag) {
+		phy_data |= MALIBU_INTR_MEDIA_STATUS_CHANGE;
+	} else {
+		phy_data &= (~MALIBU_INTR_MEDIA_STATUS_CHANGE);
+	}
+
+	if (FAL_PHY_INTR_WOL_STATUS & intr_mask_flag) {
+		phy_data |= MALIBU_INTR_WOL;
+	} else {
+		phy_data &= (~MALIBU_INTR_WOL);
+	}
+
+	if (FAL_PHY_INTR_POE_STATUS & intr_mask_flag) {
+		phy_data |= MALIBU_INTR_POE;
+	} else {
+		phy_data &= (~MALIBU_INTR_POE);
+	}
+
+	malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_INTR_MASK, phy_data);
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_intr_mask_get - Get interrupt mask with the
+* specified device.
+*/
+sw_error_t
+malibu_phy_intr_mask_get(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_uint32_t * intr_mask_flag)
+{
+	a_uint16_t phy_data = 0;
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_INTR_MASK);
+
+	*intr_mask_flag = 0;
+	if (MALIBU_INTR_STATUS_UP_CHANGE & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE;
+	}
+
+	if (MALIBU_INTR_STATUS_DOWN_CHANGE & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE;
+	}
+
+	if (MALIBU_INTR_SPEED_CHANGE & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_SPEED_CHANGE;
+	}
+
+	if (MALIBU_INTR_DUPLEX_CHANGE & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_DUPLEX_CHANGE;
+	}
+
+	if (MALIBU_INTR_BX_FX_STATUS_UP_CHANGE & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE;
+	}
+
+	if (MALIBU_INTR_BX_FX_STATUS_DOWN_CHANGE & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE;
+	}
+
+	if (MALIBU_INTR_MEDIA_STATUS_CHANGE  & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_MEDIA_STATUS_CHANGE;
+	}
+
+	if (MALIBU_INTR_WOL  & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_WOL_STATUS;
+	}
+
+	if (MALIBU_INTR_POE  & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_POE_STATUS;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_intr_status_get - Get interrupt status with the
+* specified device.
+*/
+sw_error_t
+malibu_phy_intr_status_get(a_uint32_t dev_id, a_uint32_t phy_id,
+			   a_uint32_t * intr_status_flag)
+{
+	a_uint16_t phy_data = 0;
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_INTR_STATUS);
+
+	*intr_status_flag = 0;
+	if (MALIBU_INTR_STATUS_UP_CHANGE & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE;
+	}
+
+	if (MALIBU_INTR_STATUS_DOWN_CHANGE & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE;
+	}
+
+	if (MALIBU_INTR_SPEED_CHANGE & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_SPEED_CHANGE;
+	}
+
+	if (MALIBU_INTR_DUPLEX_CHANGE & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_DUPLEX_CHANGE;
+	}
+
+	if (MALIBU_INTR_BX_FX_STATUS_UP_CHANGE & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE;
+	}
+
+	if (MALIBU_INTR_BX_FX_STATUS_DOWN_CHANGE & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE;
+	}
+	if (MALIBU_INTR_MEDIA_STATUS_CHANGE  & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_MEDIA_STATUS_CHANGE;
+	}
+
+	if (MALIBU_INTR_WOL  & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_WOL_STATUS;
+	}
+
+	if (MALIBU_INTR_POE  & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_POE_STATUS;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_set_counter - set counter status
+*
+* set counter  status
+*/
+sw_error_t
+malibu_phy_set_counter(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+					MALIBU_PHY_MMD7_COUNTER_CTRL);
+
+	if (enable == A_TRUE) {
+		phy_data |= 0x0003;
+	} else {
+		phy_data &= ~0x0003;
+	}
+
+	malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+			     MALIBU_PHY_MMD7_COUNTER_CTRL, phy_data);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_get_counter_status - get counter status
+*
+* set counter status
+*/
+sw_error_t
+malibu_phy_get_counter(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	*enable = A_FALSE;
+
+	phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+					MALIBU_PHY_MMD7_COUNTER_CTRL);
+
+	if (phy_data & 0x0001)
+		*enable = A_TRUE;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* malibu_phy_show show counter statistics
+*
+* show counter statistics
+*/
+sw_error_t
+malibu_phy_show_counter(a_uint32_t dev_id, a_uint32_t phy_id,
+			 fal_port_counter_info_t * counter_infor)
+{
+	a_uint16_t ingress_high_counter;
+	a_uint16_t ingress_low_counter;
+	a_uint16_t egress_high_counter;
+	a_uint16_t egress_low_counter;
+
+	ingress_high_counter = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+					MALIBU_PHY_MMD7_INGRESS_COUNTER_HIGH);
+	ingress_low_counter = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+					MALIBU_PHY_MMD7_INGRESS_COUNTER_LOW);
+	counter_infor->RxGoodFrame = (ingress_high_counter << 16 ) | ingress_low_counter;
+	counter_infor->RxBadCRC = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+					MALIBU_PHY_MMD7_INGRESS_ERROR_COUNTER);
+
+	egress_high_counter = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+					MALIBU_PHY_MMD7_EGRESS_COUNTER_HIGH);
+	egress_low_counter = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+					MALIBU_PHY_MMD7_EGRESS_COUNTER_LOW);
+	counter_infor->TxGoodFrame = (egress_high_counter << 16 ) | egress_low_counter;
+	counter_infor->TxBadCRC = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+					MALIBU_PHY_MMD7_EGRESS_ERROR_COUNTER);
+
+	return SW_OK;
+}
+#endif
+/******************************************************************************
+*
+* malibu_phy_get status
+*
+* get phy status
+*/
+sw_error_t
+malibu_phy_get_status(a_uint32_t dev_id, a_uint32_t phy_id,
+		struct port_phy_status *phy_status)
+{
+	a_uint16_t phy_data;
+
+	if (phy_id == COMBO_PHY_ID) {
+		__phy_reg_pages_sel_by_active_medium(dev_id, phy_id);
+	}
+
+	phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_STATUS);
+
+	/*get phy link status*/
+	if (phy_data & MALIBU_STATUS_LINK_PASS) {
+		phy_status->link_status = A_TRUE;
+	} else {
+		phy_status->link_status = A_FALSE;
+		return SW_OK;
+	}
+
+	/*get phy speed*/
+	switch (phy_data & MALIBU_STATUS_SPEED_MASK) {
+	case MALIBU_STATUS_SPEED_1000MBS:
+		phy_status->speed = FAL_SPEED_1000;
+		break;
+	case MALIBU_STATUS_SPEED_100MBS:
+		phy_status->speed = FAL_SPEED_100;
+		break;
+	case MALIBU_STATUS_SPEED_10MBS:
+		phy_status->speed = FAL_SPEED_10;
+		break;
+	default:
+		return SW_READ_ERROR;
+	}
+
+	/*get phy duplex*/
+	if (phy_data & MALIBU_STATUS_FULL_DUPLEX) {
+		phy_status->duplex = FAL_FULL_DUPLEX;
+	} else {
+		phy_status->duplex = FAL_HALF_DUPLEX;
+	}
+
+	/* get phy flowctrl resolution status */
+	if (phy_data & MALIBU_PHY_RX_FLOWCTRL_STATUS) {
+		phy_status->rx_flowctrl = A_TRUE;
+	} else {
+		phy_status->rx_flowctrl = A_FALSE;
+	}
+
+	if (phy_data & MALIBU_PHY_TX_FLOWCTRL_STATUS) {
+		phy_status->tx_flowctrl = A_TRUE;
+	} else {
+		phy_status->tx_flowctrl = A_FALSE;
+	}
+
+	return SW_OK;
+}
+/******************************************************************************
+*
+* malibu_phy_set_eee_advertisement
+*
+* set eee advertisement
+*/
+sw_error_t
+malibu_phy_set_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t adv)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	if (phy_id == COMBO_PHY_ID) {
+		if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+	}
+
+	phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+				       MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL);
+	phy_data &= ~(MALIBU_PHY_EEE_ADV_100M | MALIBU_PHY_EEE_ADV_1000M);
+
+	if (adv & FAL_PHY_EEE_100BASE_T) {
+		phy_data |= MALIBU_PHY_EEE_ADV_100M;
+	}
+	if (adv & FAL_PHY_EEE_1000BASE_T) {
+		phy_data |= MALIBU_PHY_EEE_ADV_1000M;
+	}
+
+	rv = malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+		     MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data);
+
+	rv = malibu_phy_restart_autoneg(dev_id, phy_id);
+
+	return rv;
+
+}
+
+/******************************************************************************
+*
+* malibu_phy_get_eee_advertisement
+*
+* get eee advertisement
+*/
+sw_error_t
+malibu_phy_get_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *adv)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	if (phy_id == COMBO_PHY_ID) {
+		if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+	}
+
+	*adv = 0;
+	phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+				       MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL);
+
+	if (phy_data & MALIBU_PHY_EEE_ADV_100M) {
+		*adv |= FAL_PHY_EEE_100BASE_T;
+	}
+	if (phy_data & MALIBU_PHY_EEE_ADV_1000M) {
+		*adv |= FAL_PHY_EEE_1000BASE_T;
+	}
+
+	return rv;
+}
+/******************************************************************************
+*
+* malibu_phy_get_eee_partner_advertisement
+*
+* get eee partner advertisement
+*/
+sw_error_t
+malibu_phy_get_eee_partner_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *adv)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	if (phy_id == COMBO_PHY_ID) {
+		if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+	}
+
+	*adv = 0;
+	phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+				       MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_PARTNER);
+
+	if (phy_data & MALIBU_PHY_EEE_PARTNER_ADV_100M) {
+		*adv |= FAL_PHY_EEE_100BASE_T;
+	}
+	if (phy_data & MALIBU_PHY_EEE_PARTNER_ADV_1000M) {
+		*adv |= FAL_PHY_EEE_1000BASE_T;
+	}
+
+	return rv;
+}
+/******************************************************************************
+*
+* malibu_phy_get_eee_capability
+*
+* get eee capability
+*/
+sw_error_t
+malibu_phy_get_eee_cap(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *cap)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	if (phy_id == COMBO_PHY_ID) {
+		if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+	}
+
+	*cap = 0;
+	phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM,
+				       MALIBU_PHY_MMD3_ADDR_8023AZ_EEE_CAPABILITY);
+
+	if (phy_data & MALIBU_PHY_EEE_CAPABILITY_100M) {
+		*cap |= FAL_PHY_EEE_100BASE_T;
+	}
+	if (phy_data & MALIBU_PHY_EEE_CAPABILITY_1000M) {
+		*cap |= FAL_PHY_EEE_1000BASE_T;
+	}
+
+	return rv;
+}
+/******************************************************************************
+*
+* malibu_phy_get_eee_status
+*
+* get eee status
+*/
+sw_error_t
+malibu_phy_get_eee_status(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *status)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	if (phy_id == COMBO_PHY_ID) {
+		if (MALIBU_PHY_MEDIUM_COPPER !=
+		    __phy_active_medium_get(dev_id, phy_id))
+			return SW_NOT_SUPPORTED;
+	}
+
+	*status = 0;
+	phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM,
+				       MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_STATUS);
+
+	if (phy_data & MALIBU_PHY_EEE_STATUS_100M) {
+		*status |= FAL_PHY_EEE_100BASE_T;
+	}
+	if (phy_data & MALIBU_PHY_EEE_STATUS_1000M) {
+		*status |= FAL_PHY_EEE_1000BASE_T;
+	}
+
+	return rv;
+}
+/******************************************************************************
+*
+* malibu_phy_hw_register init
+*
+*/
+sw_error_t
+malibu_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_bmp)
+{
+	a_uint32_t port_id = 0, phy_addr = 0, phy_cnt = 0;
+	a_uint16_t dac_value,led_status, phy_data;
+	a_uint32_t mode;
+
+	for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++)
+	{
+		if (port_bmp & (0x1 << port_id))
+		{
+			phy_cnt ++;
+			phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id);
+			if (phy_addr < first_phy_addr)
+			{
+				first_phy_addr = phy_addr;
+			}
+			/*enable phy power saving function by default */
+			malibu_phy_set_8023az(dev_id, phy_addr, A_TRUE);
+			malibu_phy_set_powersave(dev_id, phy_addr, A_TRUE);
+			malibu_phy_set_hibernate(dev_id, phy_addr, A_TRUE);
+			/*change malibu control_dac[2:0] of MMD7 0x801A bit[9:7] from 111 to 101*/
+			dac_value = malibu_phy_mmd_read(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM,
+				MALIBU_PHY_MMD7_DAC_CTRL);
+			dac_value &= ~MALIBU_DAC_CTRL_MASK;
+			dac_value |= MALIBU_DAC_CTRL_VALUE;
+			malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM,
+				MALIBU_PHY_MMD7_DAC_CTRL, dac_value);
+
+			/* add 10M and 100M link LED behavior for QFN board*/
+			led_status = malibu_phy_mmd_read(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM,
+				MALIBU_PHY_MMD7_LED_1000_CTRL1);
+			led_status &= ~MALIBU_LED_1000_CTRL1_100_10_MASK;
+			led_status |= MALIBU_LED_1000_CTRL1_100_10_MASK;
+			malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM,
+				MALIBU_PHY_MMD7_LED_1000_CTRL1, led_status);
+			/*disable Extended next page*/
+			phy_data = malibu_phy_reg_read(dev_id, phy_addr, MALIBU_AUTONEG_ADVERT);
+			phy_data &= ~MALIBU_EXTENDED_NEXT_PAGE_EN;
+			malibu_phy_reg_write(dev_id, phy_addr, MALIBU_AUTONEG_ADVERT, phy_data);
+		}
+	}
+	/* qca 8072 two ports phy chip's firstly address to init phy chip */
+	if ((phy_cnt == QCA8072_PHY_NUM) && (first_phy_addr >= 0x3)) {
+		first_phy_addr = first_phy_addr - 0x3;
+	}
+
+	/*workaround to enable AZ transmitting ability*/
+	malibu_phy_mmd_write(dev_id, first_phy_addr + 5, MALIBU_PHY_MMD1_NUM,
+			     MALIBU_PSGMII_MODE_CTRL, MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE);
+
+	/* adjust psgmii serdes tx amp */
+	malibu_phy_reg_write(dev_id, first_phy_addr + 5, MALIBU_PSGMII_TX_DRIVER_1_CTRL,
+		MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP);
+
+	/* to avoid psgmii module goes into hibernation, work with psgmii self test*/
+	phy_data = malibu_phy_mmd_read(dev_id, first_phy_addr + 4, MALIBU_PHY_MMD3_NUM,
+		MALIBU_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL);
+	phy_data &= (~(1<<1));
+	malibu_phy_mmd_write(dev_id, first_phy_addr + 4, MALIBU_PHY_MMD3_NUM,
+		MALIBU_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL, phy_data);
+
+
+	mode = ssdk_dt_global_get_mac_mode(dev_id, 0);
+	if (mode == PORT_WRAPPER_PSGMII_FIBER)
+		malibu_phy_interface_set_mode(dev_id, first_phy_addr, PHY_PSGMII_FIBER);
+	return SW_OK;
+}
+
+static int malibu_phy_api_ops_init(void)
+{
+
+	int ret;
+	hsl_phy_ops_t *malibu_phy_api_ops = NULL;
+
+	malibu_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL);
+	if (malibu_phy_api_ops == NULL) {
+		SSDK_ERROR("malibu phy ops kzalloc failed!\n");
+		return -ENOMEM;
+	}
+
+	phy_api_ops_init(MALIBU_PHY_CHIP);
+#ifndef IN_PORTCONTROL_MINI
+	malibu_phy_api_ops->phy_hibernation_set = malibu_phy_set_hibernate;
+	malibu_phy_api_ops->phy_hibernation_get = malibu_phy_get_hibernate;
+#endif
+	malibu_phy_api_ops->phy_speed_get = malibu_phy_get_speed;
+	malibu_phy_api_ops->phy_speed_set = malibu_phy_set_speed;
+	malibu_phy_api_ops->phy_duplex_get = malibu_phy_get_duplex;
+	malibu_phy_api_ops->phy_duplex_set = malibu_phy_set_duplex;
+	malibu_phy_api_ops->phy_autoneg_enable_set = malibu_phy_enable_autoneg;
+	malibu_phy_api_ops->phy_restart_autoneg = malibu_phy_restart_autoneg;
+	malibu_phy_api_ops->phy_autoneg_status_get = malibu_phy_autoneg_status;
+	malibu_phy_api_ops->phy_autoneg_adv_set = malibu_phy_set_autoneg_adv;
+	malibu_phy_api_ops->phy_autoneg_adv_get = malibu_phy_get_autoneg_adv;
+#ifndef IN_PORTCONTROL_MINI
+	malibu_phy_api_ops->phy_powersave_set = malibu_phy_set_powersave;
+	malibu_phy_api_ops->phy_powersave_get = malibu_phy_get_powersave;
+	malibu_phy_api_ops->phy_cdt = malibu_phy_cdt;
+#endif
+	malibu_phy_api_ops->phy_link_status_get = malibu_phy_get_link_status;
+#ifndef IN_PORTCONTROL_MINI
+	malibu_phy_api_ops->phy_mdix_set = malibu_phy_set_mdix;
+	malibu_phy_api_ops->phy_mdix_get = malibu_phy_get_mdix;
+	malibu_phy_api_ops->phy_mdix_status_get = malibu_phy_get_mdix_status;
+	malibu_phy_api_ops->phy_8023az_set = malibu_phy_set_8023az;
+	malibu_phy_api_ops->phy_8023az_get = malibu_phy_get_8023az;
+	malibu_phy_api_ops->phy_local_loopback_set = malibu_phy_set_local_loopback;
+	malibu_phy_api_ops->phy_local_loopback_get = malibu_phy_get_local_loopback;
+	malibu_phy_api_ops->phy_remote_loopback_set = malibu_phy_set_remote_loopback;
+	malibu_phy_api_ops->phy_remote_loopback_get = malibu_phy_get_remote_loopback;
+	malibu_phy_api_ops->phy_combo_prefer_medium_set = malibu_phy_set_combo_prefer_medium;
+	malibu_phy_api_ops->phy_combo_prefer_medium_get = malibu_phy_get_combo_prefer_medium;
+	malibu_phy_api_ops->phy_combo_medium_status_get = malibu_phy_get_combo_current_medium_type;
+	malibu_phy_api_ops->phy_combo_fiber_mode_set = malibu_phy_set_combo_fiber_mode;
+	malibu_phy_api_ops->phy_combo_fiber_mode_get = malibu_phy_get_combo_fiber_mode;
+	malibu_phy_api_ops->phy_reset = malibu_phy_reset;
+#endif
+	malibu_phy_api_ops->phy_power_off = malibu_phy_poweroff;
+	malibu_phy_api_ops->phy_power_on = 	malibu_phy_poweron;
+	malibu_phy_api_ops->phy_id_get = malibu_phy_get_phy_id;
+	malibu_phy_api_ops->phy_reg_write = malibu_phy_reg_write;
+	malibu_phy_api_ops->phy_reg_read = malibu_phy_reg_read;
+	malibu_phy_api_ops->phy_debug_write = malibu_phy_debug_write;
+	malibu_phy_api_ops->phy_debug_read = malibu_phy_debug_read;
+	malibu_phy_api_ops->phy_mmd_write = malibu_phy_mmd_write;
+	malibu_phy_api_ops->phy_mmd_read = malibu_phy_mmd_read;
+#ifndef IN_PORTCONTROL_MINI
+	malibu_phy_api_ops->phy_magic_frame_mac_set = malibu_phy_set_magic_frame_mac;
+	malibu_phy_api_ops->phy_magic_frame_mac_get = malibu_phy_get_magic_frame_mac;
+	malibu_phy_api_ops->phy_wol_status_set = malibu_phy_set_wol_status;
+	malibu_phy_api_ops->phy_wol_status_get = malibu_phy_get_wol_status;
+#endif
+	malibu_phy_api_ops->phy_interface_mode_set = malibu_phy_interface_set_mode;
+	malibu_phy_api_ops->phy_interface_mode_get = malibu_phy_interface_get_mode;
+	malibu_phy_api_ops->phy_interface_mode_status_get = malibu_phy_interface_get_mode_status;
+#ifndef IN_PORTCONTROL_MINI
+	malibu_phy_api_ops->phy_intr_mask_set = malibu_phy_intr_mask_set;
+	malibu_phy_api_ops->phy_intr_mask_get = malibu_phy_intr_mask_get;
+	malibu_phy_api_ops->phy_intr_status_get = malibu_phy_intr_status_get;
+	malibu_phy_api_ops->phy_counter_set = malibu_phy_set_counter;
+	malibu_phy_api_ops->phy_counter_get = malibu_phy_get_counter;
+	malibu_phy_api_ops->phy_counter_show = malibu_phy_show_counter;
+#endif
+	malibu_phy_api_ops->phy_serdes_reset = malibu_phy_serdes_reset;
+	malibu_phy_api_ops->phy_get_status = malibu_phy_get_status;
+	malibu_phy_api_ops->phy_eee_adv_set = malibu_phy_set_eee_adv;
+	malibu_phy_api_ops->phy_eee_adv_get = malibu_phy_get_eee_adv;
+	malibu_phy_api_ops->phy_eee_partner_adv_get = malibu_phy_get_eee_partner_adv;
+	malibu_phy_api_ops->phy_eee_cap_get = malibu_phy_get_eee_cap;
+	malibu_phy_api_ops->phy_eee_status_get = malibu_phy_get_eee_status;
+
+	ret = hsl_phy_api_ops_register(MALIBU_PHY_CHIP, malibu_phy_api_ops);
+
+	if (ret == 0)
+		SSDK_INFO("qca probe malibu phy driver succeeded!\n");
+	else
+		SSDK_ERROR("qca probe malibu phy driver failed! (code: %d)\n", ret);
+	return ret;
+}
+
+/******************************************************************************
+*
+* malibu_phy_init -
+*
+*/
+int malibu_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp)
+{
+	static a_uint32_t phy_ops_flag = 0;
+
+	if(phy_ops_flag == 0) {
+		malibu_phy_api_ops_init();
+		phy_ops_flag = 1;
+	}
+	malibu_phy_hw_init(dev_id, port_bmp);
+
+	return 0;
+}
+
diff --git a/qca-ssdk/src/hsl/phy/mpge_led.c b/qca-ssdk/src/hsl/phy/mpge_led.c
new file mode 100644
index 0000000..31f47f7
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/mpge_led.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "hsl_phy.h"
+#include "qca808x_led.h"
+
+/******************************************************************************
+*
+* mpge_phy_led_ctrl_pattern_set - set led behavior
+*
+*/
+sw_error_t
+mpge_phy_led_ctrl_pattern_set(a_uint32_t dev_id, a_uint32_t phy_id,
+	led_ctrl_pattern_t *pattern)
+{
+	return qca808x_phy_led_ctrl_pattern_set(dev_id, phy_id, pattern);
+}
+
+/******************************************************************************
+*
+* mpge_phy_led_ctrl_pattern_get - get led behavior
+*
+*/
+sw_error_t
+mpge_phy_led_ctrl_pattern_get(a_uint32_t dev_id, a_uint32_t phy_id,
+	led_ctrl_pattern_t * pattern)
+{
+	return qca808x_phy_led_ctrl_pattern_get(dev_id, phy_id, pattern);
+}
+/******************************************************************************
+*
+* mpge_phy_led_source_pattern_set - set led behavior based on source id
+*
+*/
+sw_error_t
+mpge_phy_led_ctrl_source_set(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t source_id, led_ctrl_pattern_t * pattern)
+{
+	return qca808x_phy_led_ctrl_source_set(dev_id, phy_id, source_id, pattern);
+}
+
+void mpge_phy_led_api_ops_init(hsl_phy_ops_t *mpge_phy_led_api_ops)
+{
+	if (!mpge_phy_led_api_ops) {
+		return;
+	}
+	mpge_phy_led_api_ops->phy_led_ctrl_pattern_get = mpge_phy_led_ctrl_pattern_get;
+	mpge_phy_led_api_ops->phy_led_ctrl_pattern_set = mpge_phy_led_ctrl_pattern_set;
+	mpge_phy_led_api_ops->phy_led_ctrl_source_set = mpge_phy_led_ctrl_source_set;
+
+	return;
+}
diff --git a/qca-ssdk/src/hsl/phy/mpge_phy.c b/qca-ssdk/src/hsl/phy/mpge_phy.c
new file mode 100644
index 0000000..dc4d31e
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/mpge_phy.c
@@ -0,0 +1,1117 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "fal_port_ctrl.h"
+#include "hsl_api.h"
+#include "hsl.h"
+#include "hsl_phy.h"
+#include "ssdk_plat.h"
+#include "qca808x_phy.h"
+#include "mpge_phy.h"
+#ifdef IN_LED
+#include "mpge_led.h"
+#endif
+
+#define PHY_DAC(val) (val<<8)
+
+/******************************************************************************
+*
+* mpge_phy_mii_read - mii register read
+*
+*/
+static a_uint16_t
+mpge_phy_reg_read (a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id)
+{
+	return qca808x_phy_reg_read (dev_id, phy_id, reg_id);
+}
+
+/******************************************************************************
+*
+* mpge_phy_mii_write - mii register write
+*
+*/
+static sw_error_t
+mpge_phy_reg_write (a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id,
+	a_uint16_t reg_val)
+{
+	return qca808x_phy_reg_write (dev_id, phy_id, reg_id, reg_val);
+}
+
+/******************************************************************************
+*
+* mpge_phy_debug_read - debug port read
+*
+*/
+static a_uint16_t
+mpge_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id)
+{
+	return qca808x_phy_debug_read(dev_id, phy_id, reg_id);
+}
+
+/******************************************************************************
+*
+* mpge_phy_debug_write - debug port write
+*
+*/
+static sw_error_t
+mpge_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id,
+	a_uint16_t reg_val)
+{
+	return qca808x_phy_debug_write (dev_id, phy_id, reg_id, reg_val);
+}
+
+/******************************************************************************
+*
+* mpge_phy_mmd_read -  PHY MMD register read
+*
+*/
+static a_uint16_t
+mpge_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint16_t mmd_num, a_uint16_t reg_id)
+{
+	return qca808x_phy_mmd_read(dev_id, phy_id, mmd_num, reg_id);
+}
+
+/******************************************************************************
+*
+* mpge_phy_mmd_write - PHY MMD register write
+*
+*/
+static sw_error_t
+mpge_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint16_t mmd_num, a_uint16_t reg_id, a_uint16_t reg_val)
+{
+	return qca808x_phy_mmd_write (dev_id, phy_id, mmd_num,
+		reg_id, reg_val);
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_status - get the phy status
+*
+*/
+static sw_error_t
+mpge_phy_get_status(a_uint32_t dev_id, a_uint32_t phy_id,
+		struct port_phy_status *phy_status)
+{
+	return qca808x_phy_get_status(dev_id, phy_id, phy_status);
+}
+
+/******************************************************************************
+*
+* mpge_set_autoneg_adv - set the phy autoneg Advertisement
+*
+*/
+static sw_error_t
+mpge_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+			   a_uint32_t autoneg)
+{
+	if (autoneg & (~FAL_PHY_GE_ADV_ALL))
+	{
+		SSDK_ERROR("autoneg adv caps 0x%x is not support for MP\n", autoneg);
+		return SW_BAD_PARAM;
+	}
+	return qca808x_phy_set_autoneg_adv(dev_id, phy_id, autoneg);
+}
+
+/******************************************************************************
+*
+* mpge_get_autoneg_adv - get the phy autoneg Advertisement
+*
+*/
+static sw_error_t
+mpge_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+			   a_uint32_t * autoneg)
+{
+	return qca808x_phy_get_autoneg_adv(dev_id, phy_id, autoneg);
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_speed - Determines the speed of phy ports associated with the
+* specified device.
+*/
+
+static sw_error_t
+mpge_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+		     fal_port_speed_t * speed)
+{
+	return qca808x_phy_get_speed(dev_id, phy_id, speed);
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_duplex - Determines the duplex of phy ports associated with the
+* specified device.
+*/
+static sw_error_t
+mpge_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+		      fal_port_duplex_t * duplex)
+{
+	return qca808x_phy_get_duplex(dev_id, phy_id, duplex);
+}
+
+/******************************************************************************
+*
+* mpge_phy_set_speed - Set the speed of phy ports associated with the
+* specified device.
+*/
+static sw_error_t
+mpge_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+		     fal_port_speed_t speed)
+{
+	a_uint16_t phy_data = 0;
+	a_uint32_t autoneg = 0;
+	fal_port_duplex_t old_duplex = MPGE_CTRL_FULL_DUPLEX;
+	sw_error_t rv = SW_OK;
+
+	phy_data = mpge_phy_reg_read(dev_id, phy_id, MPGE_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	switch(speed)
+	{
+		case FAL_SPEED_1000:
+			rv = mpge_phy_get_autoneg_adv(dev_id, phy_id, &autoneg);
+			PHY_RTN_ON_ERROR(rv);
+			if (!(autoneg & FAL_PHY_ADV_1000T_FD)) {
+				rv = mpge_phy_set_autoneg_adv(dev_id, phy_id,
+						autoneg | FAL_PHY_ADV_1000T_FD);
+				PHY_RTN_ON_ERROR(rv);
+			}
+			phy_data |= MPGE_CTRL_FULL_DUPLEX;
+			phy_data |= MPGE_CTRL_AUTONEGOTIATION_ENABLE;
+			phy_data |= MPGE_CTRL_RESTART_AUTONEGOTIATION;
+			break;
+		case FAL_SPEED_100:
+		case FAL_SPEED_10:
+			phy_data &= ~MPGE_CONTROL_SPEED_MASK;
+			if (speed == FAL_SPEED_100) {
+				phy_data |= MPGE_CONTROL_100M;
+			} else {
+				phy_data |= MPGE_CONTROL_10M;
+			}
+			rv = mpge_phy_get_duplex(dev_id, phy_id, &old_duplex);
+			PHY_RTN_ON_ERROR(rv);
+
+			if (old_duplex == FAL_FULL_DUPLEX) {
+				phy_data |= MPGE_CTRL_FULL_DUPLEX;
+			}
+			else if (old_duplex == FAL_HALF_DUPLEX) {
+				phy_data &= ~MPGE_CTRL_FULL_DUPLEX;
+			}
+			phy_data &= ~MPGE_CTRL_AUTONEGOTIATION_ENABLE;
+			break;
+		default:
+			return SW_BAD_PARAM;
+	}
+	rv = mpge_phy_reg_write(dev_id, phy_id, MPGE_PHY_CONTROL, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* mpge_phy_set_duplex - Set the duplex of phy ports associated with the
+* specified device.
+*/
+static sw_error_t
+mpge_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+		      fal_port_duplex_t duplex)
+{
+
+	a_uint16_t phy_data = 0;
+	a_uint32_t autoneg = 0;
+	fal_port_speed_t old_speed;
+	sw_error_t rv = SW_OK;
+
+	phy_data = mpge_phy_reg_read(dev_id, phy_id, MPGE_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	rv = mpge_phy_get_speed(dev_id, phy_id, &old_speed);
+	PHY_RTN_ON_ERROR(rv);
+
+	switch(old_speed)
+	{
+		case FAL_SPEED_1000:
+			if (duplex == FAL_FULL_DUPLEX) {
+				phy_data |= MPGE_CTRL_FULL_DUPLEX;
+			} else {
+				return SW_NOT_SUPPORTED;
+			}
+			phy_data |= MPGE_CTRL_AUTONEGOTIATION_ENABLE;
+			rv = mpge_phy_get_autoneg_adv(dev_id, phy_id, &autoneg);
+			PHY_RTN_ON_ERROR(rv);
+			if (!(autoneg & FAL_PHY_ADV_1000T_FD)) {
+				rv = mpge_phy_set_autoneg_adv(dev_id, phy_id,
+						autoneg | FAL_PHY_ADV_1000T_FD);
+				PHY_RTN_ON_ERROR(rv);
+			}
+			break;
+		case FAL_SPEED_100:
+		case FAL_SPEED_10:
+			phy_data &= ~MPGE_CONTROL_SPEED_MASK;
+			if (old_speed == FAL_SPEED_100) {
+				phy_data |= MPGE_CONTROL_100M;
+			} else {
+				phy_data |= MPGE_CONTROL_10M;
+			}
+			phy_data &= ~MPGE_CTRL_AUTONEGOTIATION_ENABLE;
+			if (duplex == FAL_FULL_DUPLEX) {
+				phy_data |= MPGE_CTRL_FULL_DUPLEX;
+			} else {
+				phy_data &= ~MPGE_CTRL_FULL_DUPLEX;
+			}
+			break;
+		default:
+			return SW_FAIL;
+	}
+	rv = mpge_phy_reg_write(dev_id, phy_id, MPGE_PHY_CONTROL, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* mpge_phy_enable_autoneg - enable the phy autoneg
+*
+*/
+static sw_error_t
+mpge_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	return qca808x_phy_enable_autoneg(dev_id, phy_id);
+}
+
+/******************************************************************************
+*
+* mpge_restart_autoneg - restart the phy autoneg
+*
+*/
+static sw_error_t
+mpge_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	return qca808x_phy_restart_autoneg(dev_id, phy_id);
+}
+
+/******************************************************************************
+*
+* mpge_phy_autoneg_status - get the phy autoneg status
+*
+*/
+static a_bool_t
+mpge_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	return qca808x_phy_autoneg_status(dev_id, phy_id);
+}
+
+/******************************************************************************
+*
+* mpge_phy_status - get the phy link status
+*
+* RETURNS:
+*    A_TRUE  --> link is alive
+*    A_FALSE --> link is down
+*/
+static a_bool_t
+mpge_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	return qca808x_phy_get_link_status(dev_id, phy_id);
+}
+
+/******************************************************************************
+*
+* mpge_phy_reset - reset the phy
+*
+*/
+static sw_error_t
+mpge_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	return qca808x_phy_reset(dev_id, phy_id);
+}
+
+
+/******************************************************************************
+*
+* mpge_phy_get_phy_id - get the phy id
+*
+*/
+static sw_error_t
+mpge_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *phy_data)
+{
+	return qca808x_phy_get_phy_id (dev_id, phy_id, phy_data);
+}
+
+/******************************************************************************
+*
+* mpge_phy_off - power off the phy
+*
+*/
+static sw_error_t
+mpge_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	return qca808x_phy_poweroff (dev_id, phy_id);
+}
+
+/******************************************************************************
+*
+* mpge_phy_on - power on the phy
+*
+*/
+static sw_error_t
+mpge_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	return qca808x_phy_poweron (dev_id, phy_id);
+}
+
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* mpge_phy_set_hibernate - set hibernate status
+*
+*/
+static sw_error_t
+mpge_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	return qca808x_phy_set_hibernate (dev_id, phy_id, enable);
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_hibernate - get hibernate status
+*
+*/
+static sw_error_t
+mpge_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_bool_t * enable)
+{
+	return qca808x_phy_get_hibernate (dev_id, phy_id, enable);
+}
+
+/******************************************************************************
+*
+* mpge_phy_cdt - cable diagnostic test
+*
+*/
+static sw_error_t
+mpge_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+	fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+	return qca808x_phy_cdt (dev_id, phy_id, mdi_pair,
+		cable_status, cable_len);
+}
+
+/******************************************************************************
+*
+* mpge_phy_set_mdix - set phy mdix configuration
+*
+*/
+static sw_error_t
+mpge_phy_set_mdix(a_uint32_t dev_id, a_uint32_t phy_id,
+		    fal_port_mdix_mode_t mode)
+{
+	return qca808x_phy_set_mdix(dev_id, phy_id, mode);
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_mdix - get phy mdix configuration
+*
+*/
+static sw_error_t
+mpge_phy_get_mdix(a_uint32_t dev_id, a_uint32_t phy_id,
+		    fal_port_mdix_mode_t * mode)
+{
+	return qca808x_phy_get_mdix(dev_id, phy_id, mode);
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_mdix_status - get phy mdix status
+*
+*/
+static sw_error_t
+mpge_phy_get_mdix_status(a_uint32_t dev_id, a_uint32_t phy_id,
+			   fal_port_mdix_status_t * mode)
+{
+	return qca808x_phy_get_mdix_status(dev_id, phy_id, mode);
+}
+
+/******************************************************************************
+*
+* mpge_phy_set_local_loopback
+*
+*/
+static sw_error_t
+mpge_phy_set_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	fal_port_speed_t old_speed;
+	sw_error_t rv = SW_OK;
+
+	if (enable == A_TRUE)
+	{
+		mpge_phy_get_speed(dev_id, phy_id, &old_speed);
+		if (old_speed == FAL_SPEED_1000)
+		{
+			phy_data = MPGE_1000M_LOOPBACK;
+		}
+		else if (old_speed == FAL_SPEED_100)
+		{
+			phy_data = MPGE_100M_LOOPBACK;
+		}
+		else if (old_speed == FAL_SPEED_10)
+		{
+			phy_data = MPGE_10M_LOOPBACK;
+		}
+		else
+		{
+			return SW_FAIL;
+		}
+	}
+	else
+	{
+		phy_data = MPGE_COMMON_CTRL;
+	}
+
+	rv = mpge_phy_reg_write(dev_id, phy_id, MPGE_PHY_CONTROL, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_local_loopback
+*
+*/
+static sw_error_t
+mpge_phy_get_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_bool_t * enable)
+{
+	return qca808x_phy_get_local_loopback (dev_id, phy_id, enable);
+}
+
+/******************************************************************************
+*
+* mpge_phy_set_remote_loopback
+*
+*/
+static sw_error_t
+mpge_phy_set_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_bool_t enable)
+{
+	return qca808x_phy_set_remote_loopback (dev_id, phy_id, enable);
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_remote_loopback
+*
+*/
+static sw_error_t
+mpge_phy_get_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_bool_t * enable)
+{
+	return qca808x_phy_get_remote_loopback (dev_id, phy_id, enable);
+
+}
+
+/******************************************************************************
+*
+* mpge_phy_set_802.3az
+*
+*/
+static sw_error_t
+mpge_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	return qca808x_phy_set_8023az (dev_id, phy_id, enable);
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_8023az status
+*
+*/
+static sw_error_t
+mpge_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable)
+{
+	return qca808x_phy_get_8023az (dev_id, phy_id, enable);
+}
+
+/******************************************************************************
+*
+* mpge_phy_set wol-frame mac address
+*
+*/
+static sw_error_t
+mpge_phy_set_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id,
+	fal_mac_addr_t * mac)
+{
+	return qca808x_phy_set_magic_frame_mac (dev_id, phy_id, mac);
+}
+
+/******************************************************************************
+*
+* mpge_phy_get wol - frame mac address
+*
+*/
+static sw_error_t
+mpge_phy_get_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id,
+	fal_mac_addr_t * mac)
+{
+	return qca808x_phy_get_magic_frame_mac (dev_id, phy_id, mac);
+}
+
+/******************************************************************************
+*
+* mpge_phy_set wol - enable or disable
+*
+*/
+static sw_error_t
+mpge_phy_set_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	return qca808x_phy_set_wol_status (dev_id, phy_id, enable);
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_wol status - get wol status
+*
+*/
+static sw_error_t
+mpge_phy_get_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable)
+{
+	return qca808x_phy_get_wol_status (dev_id, phy_id, enable);
+}
+
+/******************************************************************************
+*
+* mpge_phy_set_counter - set counter status
+*
+*/
+static sw_error_t
+mpge_phy_set_counter(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	return qca808x_phy_set_counter (dev_id, phy_id, enable);
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_counter_status - get counter status
+*
+*/
+static sw_error_t
+mpge_phy_get_counter(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_bool_t * enable)
+{
+	return qca808x_phy_get_counter (dev_id, phy_id, enable);
+}
+
+/******************************************************************************
+*
+* mpge_phy_show show - counter statistics
+*
+*/
+static sw_error_t
+mpge_phy_show_counter(a_uint32_t dev_id, a_uint32_t phy_id,
+	fal_port_counter_info_t * counter_infor)
+{
+	return qca808x_phy_show_counter (dev_id, phy_id, counter_infor);
+}
+
+/******************************************************************************
+*
+* mpge_phy_set_intr_mask - Set interrupt mask with the
+* specified device.
+*/
+sw_error_t
+mpge_phy_set_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t intr_mask_flag)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	phy_data = mpge_phy_reg_read(dev_id, phy_id, MPGE_PHY_INTR_MASK);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (intr_mask_flag & FAL_PHY_INTR_STATUS_UP_CHANGE) {
+		phy_data |= MPGE_INTR_STATUS_LINK_UP;
+	} else {
+		phy_data &= (~MPGE_INTR_STATUS_LINK_UP);
+	}
+
+	if (intr_mask_flag & FAL_PHY_INTR_STATUS_DOWN_CHANGE) {
+		phy_data |= MPGE_INTR_STATUS_LINK_DOWN;
+	} else {
+		phy_data &= (~MPGE_INTR_STATUS_LINK_DOWN);
+	}
+
+	if (intr_mask_flag & FAL_PHY_INTR_SPEED_CHANGE) {
+		phy_data |= MPGE_INTR_SPEED_CHANGE;
+	} else {
+		phy_data &= (~MPGE_INTR_SPEED_CHANGE);
+	}
+
+	if (intr_mask_flag & FAL_PHY_INTR_DUPLEX_CHANGE) {
+		phy_data |= MPGE_INTR_DUPLEX_CHANGE;
+	} else {
+		phy_data &= (~MPGE_INTR_DUPLEX_CHANGE);
+	}
+
+	if (intr_mask_flag & FAL_PHY_INTR_WOL_STATUS) {
+		phy_data |= MPGE_INTR_WOL;
+	} else {
+		phy_data &= (~MPGE_INTR_WOL);
+	}
+
+	rv = mpge_phy_reg_write(dev_id, phy_id, MPGE_PHY_INTR_MASK, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_intr_mask - Get interrupt mask with the
+* specified device.
+*/
+sw_error_t
+mpge_phy_get_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t * intr_mask_flag)
+{
+	a_uint16_t phy_data = 0;
+
+	phy_data = mpge_phy_reg_read(dev_id, phy_id, MPGE_PHY_INTR_MASK);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	*intr_mask_flag = 0;
+	if (phy_data & MPGE_INTR_STATUS_LINK_UP) {
+		*intr_mask_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE;
+	}
+
+	if (phy_data & MPGE_INTR_STATUS_LINK_DOWN) {
+		*intr_mask_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE;
+	}
+
+	if (phy_data & MPGE_INTR_SPEED_CHANGE) {
+		*intr_mask_flag |= FAL_PHY_INTR_SPEED_CHANGE;
+	}
+
+	if (phy_data & MPGE_INTR_DUPLEX_CHANGE) {
+		*intr_mask_flag |= FAL_PHY_INTR_DUPLEX_CHANGE;
+	}
+
+	if (phy_data & MPGE_INTR_WOL) {
+		*intr_mask_flag |= FAL_PHY_INTR_WOL_STATUS;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_intr_status - Get interrupt status with the
+* specified device.
+*/
+sw_error_t
+mpge_phy_get_intr_status(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t * intr_status_flag)
+{
+	a_uint16_t phy_data = 0;
+
+	phy_data = mpge_phy_reg_read(dev_id, phy_id, MPGE_PHY_INTR_STATUS);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	*intr_status_flag = 0;
+	if (phy_data & MPGE_INTR_STATUS_LINK_UP) {
+		*intr_status_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE;
+	}
+
+	if (phy_data & MPGE_INTR_STATUS_LINK_DOWN) {
+		*intr_status_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE;
+	}
+
+	if (phy_data & MPGE_INTR_SPEED_CHANGE) {
+		*intr_status_flag |= FAL_PHY_INTR_SPEED_CHANGE;
+	}
+
+	if (phy_data & MPGE_INTR_DUPLEX_CHANGE) {
+		*intr_status_flag |= FAL_PHY_INTR_DUPLEX_CHANGE;
+	}
+
+	if (phy_data & MPGE_INTR_WOL) {
+		*intr_status_flag |= FAL_PHY_INTR_WOL_STATUS;
+	}
+
+	return SW_OK;
+}
+#endif
+
+/******************************************************************************
+*
+* mpge_phy_set_eee_advertisement
+*
+*/
+static sw_error_t
+mpge_phy_set_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t adv)
+{
+	return qca808x_phy_set_eee_adv (dev_id, phy_id, adv);
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_eee_advertisement
+*
+*/
+static sw_error_t
+mpge_phy_get_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *adv)
+{
+	return qca808x_phy_get_eee_adv (dev_id, phy_id, adv);
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_eee_partner_advertisement
+*
+*/
+static sw_error_t
+mpge_phy_get_eee_partner_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *adv)
+{
+	return qca808x_phy_get_eee_partner_adv (dev_id, phy_id, adv);
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_eee_capability
+*
+*/
+static sw_error_t
+mpge_phy_get_eee_cap(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *cap)
+{
+	return qca808x_phy_get_eee_cap (dev_id, phy_id, cap);
+}
+
+/******************************************************************************
+*
+* mpge_phy_get_eee_status - get eee status
+*
+*/
+static sw_error_t
+mpge_phy_get_eee_status(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *status)
+{
+	return qca808x_phy_get_eee_status (dev_id, phy_id, status);
+}
+/******************************************************************************
+*
+* mpge_phy_cdt_thresh_set - set CDT threshold
+*
+* set CDT threshold
+*/
+static sw_error_t
+mpge_phy_cdt_thresh_init(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	sw_error_t rv = SW_OK;
+
+	rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM,
+		MPGE_PHY_MMD3_CDT_THRESH_CTRL3,
+		MPGE_PHY_MMD3_CDT_THRESH_CTRL3_VAL);
+	SW_RTN_ON_ERROR(rv);
+	rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM,
+		MPGE_PHY_MMD3_CDT_THRESH_CTRL4,
+		MPGE_PHY_MMD3_CDT_THRESH_CTRL4_VAL);
+	SW_RTN_ON_ERROR(rv);
+	rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM,
+		MPGE_PHY_MMD3_CDT_THRESH_CTRL5,
+		MPGE_PHY_MMD3_CDT_THRESH_CTRL5_VAL);
+	SW_RTN_ON_ERROR(rv);
+	rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM,
+		MPGE_PHY_MMD3_CDT_THRESH_CTRL6,
+		MPGE_PHY_MMD3_CDT_THRESH_CTRL6_VAL);
+	SW_RTN_ON_ERROR(rv);
+	rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM,
+		MPGE_PHY_MMD3_CDT_THRESH_CTRL7,
+		MPGE_PHY_MMD3_CDT_THRESH_CTRL7_VAL);
+	SW_RTN_ON_ERROR(rv);
+	rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM,
+		MPGE_PHY_MMD3_CDT_THRESH_CTRL9,
+		MPGE_PHY_MMD3_CDT_THRESH_CTRL9_VAL);
+	SW_RTN_ON_ERROR(rv);
+	rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM,
+		MPGE_PHY_MMD3_CDT_THRESH_CTRL13,
+		MPGE_PHY_MMD3_CDT_THRESH_CTRL13_VAL);
+	SW_RTN_ON_ERROR(rv);
+	rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM,
+		MPGE_PHY_MMD3_CDT_THRESH_CTRL14,
+		MPGE_PHY_MMD3_NEAR_ECHO_THRESH_VAL);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* mpge_phy_function_reset - do function reset
+*
+*/
+static sw_error_t
+mpge_phy_function_reset(a_uint32_t dev_id, a_uint32_t phy_id,
+	hsl_phy_function_reset_t phy_reset_type)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	switch (phy_reset_type)
+	{
+		case PHY_FIFO_RESET:
+			phy_data = mpge_phy_reg_read (dev_id, phy_id, MPGE_PHY_FIFO_CONTROL);
+			PHY_RTN_ON_READ_ERROR(phy_data);
+
+			rv = mpge_phy_reg_write(dev_id, phy_id, MPGE_PHY_FIFO_CONTROL,
+				phy_data & (~MPGE_PHY_FIFO_RESET));
+			SW_RTN_ON_ERROR(rv);
+
+			aos_mdelay(50);
+
+			rv = mpge_phy_reg_write(dev_id, phy_id, MPGE_PHY_FIFO_CONTROL,
+			phy_data | MPGE_PHY_FIFO_RESET);
+			SW_RTN_ON_ERROR(rv);
+			break;
+		default:
+			return SW_NOT_SUPPORTED;
+	}
+
+	return rv;
+}
+
+static void
+mpge_phy_lock_init(void)
+{
+	return qca808x_phy_lock_init();
+}
+
+static sw_error_t
+mpge_phy_dac_set(a_uint32_t dev_id, a_uint32_t phy_id, phy_dac_t phy_dac)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	if(phy_dac.mdac != PHY_INVALID_DAC)
+	{
+		SSDK_INFO("phy mdac is set as 0x%x\n", phy_dac.mdac);
+		/*set mdac value*/
+		phy_data = mpge_phy_mmd_read(dev_id, phy_id, MPGE_PHY_MMD1_NUM,
+			MPGE_PHY_MMD1_DAC);
+		PHY_RTN_ON_READ_ERROR(phy_data);
+		phy_data &= ~(BITS(8,8));
+		rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD1_NUM,
+			MPGE_PHY_MMD1_DAC, phy_data | PHY_DAC(phy_dac.mdac));
+		SW_RTN_ON_ERROR(rv);
+	}
+	if(phy_dac.edac != PHY_INVALID_DAC)
+	{
+		SSDK_INFO("phy edac is set as 0x%x\n", phy_dac.edac);
+		/*set edac value*/
+		phy_data = mpge_phy_debug_read(dev_id, phy_id, MPGE_PHY_DEBUG_EDAC);
+		PHY_RTN_ON_READ_ERROR(phy_data);
+		phy_data &= ~(BITS(8,8));
+		rv = mpge_phy_debug_write(dev_id, phy_id, MPGE_PHY_DEBUG_EDAC,
+			phy_data | PHY_DAC(phy_dac.edac));
+		SW_RTN_ON_ERROR(rv);
+	}
+
+	return rv;
+}
+
+static void
+mpge_phy_dac_init(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t port_id)
+{
+	phy_dac_t  phy_dac;
+
+	hsl_port_phy_dac_get(dev_id, port_id, &phy_dac);
+	mpge_phy_dac_set(dev_id, phy_id, phy_dac);
+
+	return;
+}
+
+static sw_error_t
+mpge_phy_ldo_efuse_set(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t efuse_value)
+{
+	a_uint16_t phy_data = 0, phy_data1 = 0;
+	sw_error_t rv = SW_OK;
+
+	/*when set the register of MPGE_PHY_DEBUG_ANA_LDO_EFUSE, the register of
+	MPGE_PHY_DEBUG_ANA_DAC_FILTER will be changed automatically, so need to
+	save it and restore it*/
+	phy_data1 = mpge_phy_debug_read(dev_id, phy_id, MPGE_PHY_DEBUG_ANA_DAC_FILTER);
+	PHY_RTN_ON_READ_ERROR(phy_data1);
+
+	phy_data = mpge_phy_debug_read(dev_id, phy_id, MPGE_PHY_DEBUG_ANA_LDO_EFUSE);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+	phy_data &= ~(BITS(4,4));
+	rv = mpge_phy_debug_write(dev_id, phy_id, MPGE_PHY_DEBUG_ANA_LDO_EFUSE,
+		phy_data | efuse_value);
+	SW_RTN_ON_ERROR(rv);
+	rv = mpge_phy_debug_write(dev_id, phy_id, MPGE_PHY_DEBUG_ANA_DAC_FILTER,
+		phy_data1);
+
+	return rv;
+}
+
+static sw_error_t
+mpge_phy_hw_init(a_uint32_t dev_id,  a_uint32_t port_bmp)
+{
+	a_uint32_t port_id = 0, phy_addr = 0;
+	sw_error_t rv = SW_OK;
+
+	for (port_id = SSDK_PHYSICAL_PORT0; port_id < SW_MAX_NR_PORT; port_id ++)
+	{
+		if (port_bmp & (0x1 << port_id))
+		{
+			phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id);
+			SW_RTN_ON_ERROR(rv);
+			/*configure the CDT threshold*/
+			rv = mpge_phy_cdt_thresh_init (dev_id, phy_addr);
+			SW_RTN_ON_ERROR(rv);
+			/*set LDO efuse as default and make ICC efuse take effect only*/
+			rv = mpge_phy_ldo_efuse_set(dev_id, phy_addr,
+				MPGE_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT);
+			/*special configuration for AZ*/
+			rv = mpge_phy_mmd_write(dev_id, phy_addr, MPGE_PHY_MMD3_NUM,
+				MPGE_PHY_MMD3_AZ_CTRL1, MPGE_PHY_MMD3_AZ_CTRL1_VAL);
+			SW_RTN_ON_ERROR(rv);
+			rv = mpge_phy_mmd_write(dev_id, phy_addr, MPGE_PHY_MMD3_NUM,
+				MPGE_PHY_MMD3_AZ_CTRL2, MPGE_PHY_MMD3_AZ_CTRL2_VAL);
+			SW_RTN_ON_ERROR(rv);
+			/*configure MSE threshold and over threshold times*/
+			rv = mpge_phy_mmd_write(dev_id, phy_addr, MPGE_PHY_MMD1_NUM,
+				MPGE_PHY_MMD1_MSE_THRESH1, MPGE_PHY_MMD1_MSE_THRESH1_VAL);
+			SW_RTN_ON_ERROR(rv);
+			rv = mpge_phy_mmd_write(dev_id, phy_addr, MPGE_PHY_MMD1_NUM,
+				MPGE_PHY_MMD1_MSE_THRESH2, MPGE_PHY_MMD1_MSE_THRESH2_VAL);
+			SW_RTN_ON_ERROR(rv);
+			mpge_phy_dac_init(dev_id, phy_addr, port_id);
+		}
+	}
+
+	return rv;
+}
+
+static sw_error_t mpge_phy_api_ops_init(void)
+{
+	sw_error_t ret = SW_OK;
+	hsl_phy_ops_t *mpge_phy_api_ops = NULL;
+
+	mpge_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL);
+	if (mpge_phy_api_ops == NULL)
+	{
+		SSDK_ERROR("mpge phy ops kzalloc failed!\n");
+		return -ENOMEM;
+	}
+
+	phy_api_ops_init(MPGE_PHY_CHIP);
+
+	mpge_phy_api_ops->phy_reg_write = mpge_phy_reg_write;
+	mpge_phy_api_ops->phy_reg_read = mpge_phy_reg_read;
+	mpge_phy_api_ops->phy_debug_write = mpge_phy_debug_write;
+	mpge_phy_api_ops->phy_debug_read = mpge_phy_debug_read;
+	mpge_phy_api_ops->phy_mmd_write = mpge_phy_mmd_write;
+	mpge_phy_api_ops->phy_mmd_read = mpge_phy_mmd_read;
+	mpge_phy_api_ops->phy_get_status = mpge_phy_get_status;
+	mpge_phy_api_ops->phy_speed_get = mpge_phy_get_speed;
+	mpge_phy_api_ops->phy_speed_set = mpge_phy_set_speed;
+	mpge_phy_api_ops->phy_duplex_get = mpge_phy_get_duplex;
+	mpge_phy_api_ops->phy_duplex_set = mpge_phy_set_duplex;
+	mpge_phy_api_ops->phy_autoneg_enable_set = mpge_phy_enable_autoneg;
+	mpge_phy_api_ops->phy_restart_autoneg = mpge_phy_restart_autoneg;
+	mpge_phy_api_ops->phy_autoneg_status_get = mpge_phy_autoneg_status;
+	mpge_phy_api_ops->phy_autoneg_adv_set = mpge_phy_set_autoneg_adv;
+	mpge_phy_api_ops->phy_autoneg_adv_get = mpge_phy_get_autoneg_adv;
+	mpge_phy_api_ops->phy_link_status_get = mpge_phy_get_link_status;
+	mpge_phy_api_ops->phy_reset = mpge_phy_reset;
+	mpge_phy_api_ops->phy_id_get = mpge_phy_get_phy_id;
+	mpge_phy_api_ops->phy_power_off = mpge_phy_poweroff;
+	mpge_phy_api_ops->phy_power_on = mpge_phy_poweron;
+#ifndef IN_PORTCONTROL_MINI
+	mpge_phy_api_ops->phy_cdt = mpge_phy_cdt;
+	mpge_phy_api_ops->phy_mdix_set = mpge_phy_set_mdix;
+	mpge_phy_api_ops->phy_mdix_get = mpge_phy_get_mdix;
+	mpge_phy_api_ops->phy_mdix_status_get = mpge_phy_get_mdix_status;
+	mpge_phy_api_ops->phy_local_loopback_set = mpge_phy_set_local_loopback;
+	mpge_phy_api_ops->phy_local_loopback_get = mpge_phy_get_local_loopback;
+	mpge_phy_api_ops->phy_remote_loopback_set = mpge_phy_set_remote_loopback;
+	mpge_phy_api_ops->phy_remote_loopback_get = mpge_phy_get_remote_loopback;
+	mpge_phy_api_ops->phy_8023az_set = mpge_phy_set_8023az;
+	mpge_phy_api_ops->phy_8023az_get = mpge_phy_get_8023az;
+	mpge_phy_api_ops->phy_hibernation_set = mpge_phy_set_hibernate;
+	mpge_phy_api_ops->phy_hibernation_get = mpge_phy_get_hibernate;
+	mpge_phy_api_ops->phy_magic_frame_mac_set = mpge_phy_set_magic_frame_mac;
+	mpge_phy_api_ops->phy_magic_frame_mac_get = mpge_phy_get_magic_frame_mac;
+	mpge_phy_api_ops->phy_counter_set = mpge_phy_set_counter;
+	mpge_phy_api_ops->phy_counter_get = mpge_phy_get_counter;
+	mpge_phy_api_ops->phy_counter_show = mpge_phy_show_counter;
+	mpge_phy_api_ops->phy_wol_status_set = mpge_phy_set_wol_status;
+	mpge_phy_api_ops->phy_wol_status_get = mpge_phy_get_wol_status;
+	mpge_phy_api_ops->phy_intr_mask_set = mpge_phy_set_intr_mask;
+	mpge_phy_api_ops->phy_intr_mask_get = mpge_phy_get_intr_mask;
+	mpge_phy_api_ops->phy_intr_status_get = mpge_phy_get_intr_status;
+#endif
+	mpge_phy_api_ops->phy_eee_adv_set = mpge_phy_set_eee_adv;
+	mpge_phy_api_ops->phy_eee_adv_get = mpge_phy_get_eee_adv;
+	mpge_phy_api_ops->phy_eee_partner_adv_get = mpge_phy_get_eee_partner_adv;
+	mpge_phy_api_ops->phy_eee_cap_get = mpge_phy_get_eee_cap;
+	mpge_phy_api_ops->phy_eee_status_get = mpge_phy_get_eee_status;
+	mpge_phy_api_ops->phy_function_reset = mpge_phy_function_reset;
+#ifdef IN_LED
+	mpge_phy_led_api_ops_init(mpge_phy_api_ops);
+#endif
+	ret = hsl_phy_api_ops_register(MPGE_PHY_CHIP, mpge_phy_api_ops);
+
+	if (ret == SW_OK)
+	{
+		SSDK_INFO("qca probe mpge phy driver succeeded!\n");
+	}
+	else
+	{
+		SSDK_ERROR("qca probe mpge phy driver failed! (code: %d)\n", ret);
+	}
+
+	return ret;
+}
+
+/******************************************************************************
+*
+* mpge_phy_init -
+*
+*/
+int mpge_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp)
+{
+	a_int32_t ret = 0;
+	static a_bool_t phy_ops_flag = A_FALSE;
+
+	if(phy_ops_flag == A_FALSE &&
+			mpge_phy_api_ops_init() == SW_OK) {
+		mpge_phy_lock_init();
+		phy_ops_flag = A_TRUE;
+	}
+	mpge_phy_hw_init(dev_id, port_bmp);
+
+	return ret;
+}
diff --git a/qca-ssdk/src/hsl/phy/qca803x_phy.c b/qca-ssdk/src/hsl/phy/qca803x_phy.c
new file mode 100644
index 0000000..e9ca3bc
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/qca803x_phy.c
@@ -0,0 +1,2341 @@
+/*
+ * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "sw.h"
+#include "fal_port_ctrl.h"
+#include "hsl_api.h"
+#include "hsl.h"
+#include "qca803x_phy.h"
+#include "hsl_phy.h"
+#include "ssdk_plat.h"
+
+#define QCA803X_PHY_DELAYED_INIT_TICKS msecs_to_jiffies(1000)
+
+typedef struct {
+	a_uint32_t dev_id;
+	a_uint32_t combo_phy_bmp;
+	qca803x_phy_medium_t combo_cfg[SW_MAX_NR_PORT];
+	struct delayed_work phy_sync_dwork;
+} qca803x_priv_t;
+
+static qca803x_priv_t g_qca803x_phy;
+static struct mutex qca803x_reg_lock;
+
+#define QCA803X_LOCKER_INIT		mutex_init(&qca803x_reg_lock)
+#define QCA803X_REG_LOCK		mutex_lock(&qca803x_reg_lock)
+#define QCA803X_REG_UNLOCK		mutex_unlock(&qca803x_reg_lock)
+
+
+/******************************************************************************
+*
+* qca803x_phy_mii_read - mii register read
+*
+* mii register read
+*/
+a_uint16_t
+qca803x_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id)
+{
+	sw_error_t rv = SW_OK;
+	a_uint16_t phy_data = 0;
+
+	HSL_PHY_GET(rv, dev_id, phy_id, reg_id, &phy_data);
+	if (SW_OK != rv) {
+		return 0xffff;
+	}
+
+	return phy_data;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_mii_write - mii register write
+*
+* mii register write
+*/
+sw_error_t
+qca803x_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id,
+		       a_uint16_t reg_val)
+{
+	sw_error_t rv;
+
+	HSL_PHY_SET(rv, dev_id, phy_id, reg_id, reg_val);
+
+	return rv;
+
+}
+
+/******************************************************************************
+*
+* qca803x_phy_debug_write - debug port write
+*
+* debug port write
+*/
+sw_error_t
+qca803x_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id,
+		       a_uint16_t reg_val)
+{
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_DEBUG_PORT_ADDRESS, reg_id);
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_DEBUG_PORT_DATA, reg_val);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_debug_read - debug port read
+*
+* debug port read
+*/
+a_uint16_t
+qca803x_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id)
+{
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_DEBUG_PORT_ADDRESS, reg_id);
+	return qca803x_phy_reg_read(dev_id, phy_id, QCA803X_DEBUG_PORT_DATA);
+}
+
+/******************************************************************************
+*
+* qca803x_phy_mmd_write - PHY MMD register write
+*
+* PHY MMD register write
+*/
+sw_error_t
+qca803x_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id,
+		     a_uint16_t mmd_num, a_uint16_t reg_id, a_uint16_t reg_val)
+{
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_MMD_CTRL_REG, mmd_num);
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_MMD_DATA_REG, reg_id);
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_MMD_CTRL_REG,
+			     0x4000 | mmd_num);
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_MMD_DATA_REG, reg_val);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_mmd_read -  PHY MMD register read
+*
+* PHY MMD register read
+*/
+a_uint16_t
+qca803x_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id,
+		    a_uint16_t mmd_num, a_uint16_t reg_id)
+{
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_MMD_CTRL_REG, mmd_num);
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_MMD_DATA_REG, reg_id);
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_MMD_CTRL_REG,
+			     0x4000 | mmd_num);
+
+	return qca803x_phy_reg_read(dev_id, phy_id, QCA803X_MMD_DATA_REG);
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get_speed - Determines the speed of phy ports associated with the
+* specified device.
+*/
+
+sw_error_t
+qca803x_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+		     fal_port_speed_t * speed)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_STATUS);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	switch (phy_data & QCA803X_STATUS_SPEED_MASK)
+	{
+		case QCA803X_STATUS_SPEED_1000MBS:
+			*speed = FAL_SPEED_1000;
+			break;
+		case QCA803X_STATUS_SPEED_100MBS:
+			*speed = FAL_SPEED_100;
+			break;
+		case QCA803X_STATUS_SPEED_10MBS:
+			*speed = FAL_SPEED_10;
+			break;
+		default:
+			return SW_READ_ERROR;
+	}
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_set_speed - Determines the speed of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+qca803x_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+		     fal_port_speed_t speed)
+{
+	a_uint16_t phy_data = 0;
+	fal_port_duplex_t old_duplex;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	rv = qca803x_phy_get_duplex(dev_id, phy_id, &old_duplex);
+	if(rv != SW_OK) {
+		return rv;
+	}
+
+	if (old_duplex == FAL_FULL_DUPLEX) {
+		phy_data |= QCA803X_CTRL_FULL_DUPLEX;
+		switch(speed)
+		{
+			case FAL_SPEED_1000:
+				phy_data |= QCA803X_CTRL_SPEED_1000;
+				phy_data &= ~QCA803X_CTRL_SPEED_100;
+				phy_data |= QCA803X_CTRL_AUTONEGOTIATION_ENABLE;
+				break;
+			case FAL_SPEED_100:
+			case FAL_SPEED_10:
+				phy_data &= ~QCA803X_CTRL_SPEED_1000;
+				phy_data &= ~QCA803X_CTRL_AUTONEGOTIATION_ENABLE;
+				if (FAL_SPEED_100 == speed) {
+					phy_data |= QCA803X_CTRL_SPEED_100;
+				} else {
+					phy_data &= ~QCA803X_CTRL_SPEED_100;
+				}
+				break;
+			default:
+				return SW_BAD_PARAM;
+		}
+	} else if (old_duplex == FAL_HALF_DUPLEX) {
+		phy_data &= ~QCA803X_CTRL_FULL_DUPLEX;
+		switch(speed)
+		{
+			case FAL_SPEED_100:
+			case FAL_SPEED_10:
+				phy_data &= ~QCA803X_CTRL_SPEED_1000;
+				phy_data &= ~QCA803X_CTRL_AUTONEGOTIATION_ENABLE;
+				if (FAL_SPEED_100 == speed) {
+					phy_data |= QCA803X_CTRL_SPEED_100;
+				} else {
+					phy_data &= ~QCA803X_CTRL_SPEED_100;
+				}
+				break;
+			case FAL_SPEED_1000:
+				phy_data |= QCA803X_CTRL_FULL_DUPLEX;
+				phy_data |= QCA803X_CTRL_SPEED_1000;
+				phy_data &= ~QCA803X_CTRL_SPEED_100;
+				phy_data |= QCA803X_CTRL_AUTONEGOTIATION_ENABLE;
+				break;
+			default:
+				return SW_BAD_PARAM;
+		}
+	} else {
+		return SW_FAIL;
+	}
+	rv = qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_set_duplex - Determines the speed of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+qca803x_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+		      fal_port_duplex_t duplex)
+{
+	a_uint16_t phy_data = 0;
+	fal_port_speed_t old_speed;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	qca803x_phy_get_speed(dev_id, phy_id, &old_speed);
+	switch(old_speed)
+	{
+		case FAL_SPEED_1000:
+			phy_data |= QCA803X_CTRL_SPEED_1000;
+			phy_data &= ~QCA803X_CTRL_SPEED_100;
+			phy_data |= QCA803X_CTRL_AUTONEGOTIATION_ENABLE;
+			if (duplex == FAL_FULL_DUPLEX) {
+				phy_data |= QCA803X_CTRL_FULL_DUPLEX;
+			} else {
+				return SW_NOT_SUPPORTED;
+			}
+			break;
+		case FAL_SPEED_100:
+		case FAL_SPEED_10:
+			if(old_speed == FAL_SPEED_100) {
+				phy_data |= QCA803X_CTRL_SPEED_100;
+			} else {
+				phy_data &= ~QCA803X_CTRL_SPEED_100;
+			}
+			phy_data &= ~QCA803X_CTRL_SPEED_1000;
+			phy_data &= ~QCA803X_CTRL_AUTONEGOTIATION_ENABLE;
+			if (duplex == FAL_FULL_DUPLEX) {
+				phy_data |= QCA803X_CTRL_FULL_DUPLEX;
+			} else {
+				phy_data &= ~QCA803X_CTRL_FULL_DUPLEX;
+			}
+			break;
+		default:
+			return SW_FAIL;
+	}
+	rv = qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get_duplex - Determines the speed of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+qca803x_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+		      fal_port_duplex_t * duplex)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_STATUS);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	//read duplex
+	if (phy_data & QCA803X_STATUS_FULL_DUPLEX)
+		*duplex = FAL_FULL_DUPLEX;
+	else
+		*duplex = FAL_HALF_DUPLEX;
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_reset - reset the phy
+*
+* reset the phy
+*/
+sw_error_t qca803x_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	rv = qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL,
+			     phy_data | QCA803X_CTRL_SOFTWARE_RESET);
+
+	return rv;
+}
+/******************************************************************************
+*
+* qca803x_phy_status - test to see if the specified phy link is alive
+*
+* RETURNS:
+*    A_TRUE  --> link is alive
+*    A_FALSE --> link is down
+*/
+a_bool_t qca803x_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	a_bool_t rv = A_TRUE;
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_STATUS);
+
+	if (phy_data & QCA803X_STATUS_LINK_PASS) {
+		rv = A_TRUE;
+	} else {
+		rv = A_FALSE;
+	}
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* qca803x_phy_cdt - cable diagnostic test
+*
+* cable diagnostic test
+*/
+
+static inline fal_cable_status_t _phy_cdt_status_mapping(a_uint16_t status)
+{
+	fal_cable_status_t status_mapping = FAL_CABLE_STATUS_INVALID;
+
+	switch (status) {
+		case 3:
+			status_mapping = FAL_CABLE_STATUS_INVALID;
+			break;
+		case 2:
+			status_mapping = FAL_CABLE_STATUS_OPENED;
+			break;
+		case 1:
+			status_mapping = FAL_CABLE_STATUS_SHORT;
+			break;
+		case 0:
+			status_mapping = FAL_CABLE_STATUS_NORMAL;
+			break;
+	}
+	return status_mapping;
+}
+
+static sw_error_t qca803x_phy_cdt_start(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair)
+{
+	a_uint16_t status = 0;
+	a_uint16_t ii = 100;
+	a_uint16_t MDI_PAIR_S = (mdi_pair << 8) & CDT_PAIR_MASK;
+
+	/* RUN CDT */
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CDT_CONTROL,
+			QCA803X_RUN_CDT | MDI_PAIR_S);
+	do {
+		aos_mdelay(30);
+		status = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CDT_CONTROL);
+	}
+	while ((status & QCA803X_RUN_CDT) && (--ii));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca803x_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+	       fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+	a_uint16_t status = 0;
+
+	if (mdi_pair >= QCA803X_MDI_PAIR_NUM) {
+		//There are only 4 mdi pairs in 1000BASE-T
+		return SW_BAD_PARAM;
+	}
+
+	qca803x_phy_cdt_start(dev_id, phy_id, mdi_pair);
+
+	/* Get cable status */
+	status = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CDT_STATUS);
+	*cable_status = _phy_cdt_status_mapping((status >> 8) & 0x3);
+	/* the actual cable length equals to CableDeltaTime * 0.824 */
+	*cable_len = ((status & 0xff) * 824) / 1000;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_set_mdix -
+*
+* set phy mdix configuraiton
+*/
+sw_error_t
+qca803x_phy_set_mdix(a_uint32_t dev_id, a_uint32_t phy_id,
+		    fal_port_mdix_mode_t mode)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (mode == PHY_MDIX_AUTO) {
+		phy_data |= QCA803X_PHY_MDIX_AUTO;
+	} else if (mode == PHY_MDIX_MDIX) {
+		phy_data &= ~QCA803X_PHY_MDIX_AUTO;
+		phy_data |= QCA803X_PHY_MDIX;
+	} else if (mode == PHY_MDIX_MDI) {
+		phy_data &= ~QCA803X_PHY_MDIX_AUTO;
+	} else {
+		return SW_BAD_PARAM;
+	}
+
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_SPEC_CONTROL, phy_data);
+
+	qca803x_phy_reset(dev_id, phy_id);
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get_mdix
+*
+* get phy mdix configuration
+*/
+sw_error_t
+qca803x_phy_get_mdix(a_uint32_t dev_id, a_uint32_t phy_id,
+		    fal_port_mdix_mode_t * mode)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if ((phy_data & QCA803X_PHY_MDIX_AUTO) == QCA803X_PHY_MDIX_AUTO) {
+		*mode = PHY_MDIX_AUTO;
+	} else if ((phy_data & QCA803X_PHY_MDIX) == QCA803X_PHY_MDIX) {
+		*mode = PHY_MDIX_MDIX;
+	} else {
+		*mode = PHY_MDIX_MDI;
+	}
+
+	return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get_mdix status
+*
+* get phy mdix status
+*/
+sw_error_t
+qca803x_phy_get_mdix_status(a_uint32_t dev_id, a_uint32_t phy_id,
+			   fal_port_mdix_status_t * mode)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_STATUS);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	*mode =
+	    (phy_data & QCA803X_PHY_MDIX_STATUS) ? PHY_MDIX_STATUS_MDIX :
+	    PHY_MDIX_STATUS_MDI;
+
+	return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* qca803x_phy_set_local_loopback
+*
+* set phy local loopback
+*/
+sw_error_t
+qca803x_phy_set_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	fal_port_speed_t old_speed;
+
+	if (enable == A_TRUE) {
+		qca803x_phy_get_speed(dev_id, phy_id, &old_speed);
+		if (old_speed == FAL_SPEED_1000) {
+			phy_data = QCA803X_1000M_LOOPBACK;
+		} else if (old_speed == FAL_SPEED_100) {
+			phy_data = QCA803X_100M_LOOPBACK;
+		} else if (old_speed == FAL_SPEED_10) {
+			phy_data = QCA803X_10M_LOOPBACK;
+		} else {
+			return SW_FAIL;
+		}
+	} else {
+		phy_data = QCA803X_COMMON_CTRL;
+	}
+
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL, phy_data);
+	return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get_local_loopback
+*
+* get phy local loopback
+*/
+sw_error_t
+qca803x_phy_get_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & QCA803X_LOCAL_LOOPBACK_ENABLE) {
+		*enable = A_TRUE;
+	} else {
+		*enable = A_FALSE;
+	}
+
+	return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* qca803x_phy_set_remote_loopback
+*
+* set phy remote loopback
+*/
+sw_error_t
+qca803x_phy_set_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+			       a_bool_t enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM,
+					QCA803X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (enable == A_TRUE) {
+		phy_data |= 0x0001;
+	} else {
+		phy_data &= ~0x0001;
+	}
+
+	qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD3_NUM,
+			     QCA803X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL,
+			     phy_data);
+	return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get_remote_loopback
+*
+* get phy remote loopback
+*/
+sw_error_t
+qca803x_phy_get_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+			       a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM,
+					QCA803X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & 0x0001) {
+		*enable = A_TRUE;
+	} else {
+		*enable = A_FALSE;
+	}
+
+	return SW_OK;
+
+}
+#endif
+/******************************************************************************
+*
+* qca803x_set_autoneg_adv - set the phy autoneg Advertisement
+*
+*/
+sw_error_t
+qca803x_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+			   a_uint32_t autoneg)
+{
+	a_uint16_t phy_data = 0;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id,
+			QCA803X_AUTONEG_ADVERT);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	phy_data &= ~QCA803X_ADVERTISE_MEGA_ALL;
+
+	if (autoneg & FAL_PHY_ADV_100TX_FD) {
+		phy_data |= QCA803X_ADVERTISE_100FULL;
+	}
+	if (autoneg & FAL_PHY_ADV_100TX_HD) {
+		phy_data |= QCA803X_ADVERTISE_100HALF;
+	}
+	if (autoneg & FAL_PHY_ADV_10T_FD) {
+		phy_data |= QCA803X_ADVERTISE_10FULL;
+	}
+	if (autoneg & FAL_PHY_ADV_10T_HD) {
+		phy_data |= QCA803X_ADVERTISE_10HALF;
+	}
+	if (autoneg & FAL_PHY_ADV_PAUSE) {
+		phy_data |= QCA803X_ADVERTISE_PAUSE;
+	}
+	if (autoneg & FAL_PHY_ADV_ASY_PAUSE) {
+		phy_data |= QCA803X_ADVERTISE_ASYM_PAUSE;
+	}
+	if (autoneg & FAL_PHY_ADV_1000T_FD) {
+		phy_data |= QCA803X_EXTENDED_NEXT_PAGE_EN;
+	} else {
+		phy_data &= ~QCA803X_EXTENDED_NEXT_PAGE_EN;
+	}
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_AUTONEG_ADVERT,
+			phy_data);
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id,
+				QCA803X_1000BASET_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	phy_data &= ~QCA803X_ADVERTISE_1000FULL;
+	phy_data &= ~QCA803X_ADVERTISE_1000HALF;
+
+	if (autoneg & FAL_PHY_ADV_1000T_FD) {
+		phy_data |= QCA803X_ADVERTISE_1000FULL;
+	}
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_1000BASET_CONTROL,
+			phy_data);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_get_autoneg_adv - get the phy autoneg Advertisement
+*
+*/
+sw_error_t
+qca803x_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+			   a_uint32_t * autoneg)
+{
+	a_uint16_t phy_data = 0;
+
+	*autoneg = 0;
+	phy_data =
+		qca803x_phy_reg_read(dev_id, phy_id, QCA803X_AUTONEG_ADVERT);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & QCA803X_ADVERTISE_100FULL)
+		*autoneg |= FAL_PHY_ADV_100TX_FD;
+
+	if (phy_data & QCA803X_ADVERTISE_100HALF)
+		*autoneg |= FAL_PHY_ADV_100TX_HD;
+
+	if (phy_data & QCA803X_ADVERTISE_10FULL)
+		*autoneg |= FAL_PHY_ADV_10T_FD;
+
+	if (phy_data & QCA803X_ADVERTISE_10HALF)
+		*autoneg |= FAL_PHY_ADV_10T_HD;
+
+	if (phy_data & QCA803X_ADVERTISE_PAUSE)
+		*autoneg |= FAL_PHY_ADV_PAUSE;
+
+	if (phy_data & QCA803X_ADVERTISE_ASYM_PAUSE)
+		*autoneg |= FAL_PHY_ADV_ASY_PAUSE;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id,
+				QCA803X_1000BASET_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & QCA803X_ADVERTISE_1000FULL)
+		*autoneg |= FAL_PHY_ADV_1000T_FD;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_autoneg_status
+*
+* Power off the phy
+*/
+a_bool_t qca803x_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL);
+
+	if (phy_data & QCA803X_CTRL_AUTONEGOTIATION_ENABLE)
+		return A_TRUE;
+
+	return A_FALSE;
+}
+
+/******************************************************************************
+*
+* qca803x_restart_autoneg - restart the phy autoneg
+*
+*/
+sw_error_t qca803x_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	phy_data |= QCA803X_CTRL_AUTONEGOTIATION_ENABLE;
+	rv = qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL,
+			     phy_data | QCA803X_CTRL_RESTART_AUTONEGOTIATION);
+
+	return rv;
+}
+/******************************************************************************
+*
+* qca803x_phy_enable_autonego
+*
+*/
+sw_error_t qca803x_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	rv = qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL,
+			     phy_data | QCA803X_CTRL_AUTONEGOTIATION_ENABLE);
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* qca803x_phy_get_ability - get the phy ability
+*
+*
+*/
+sw_error_t
+qca803x_phy_get_ability(a_uint32_t dev_id, a_uint32_t phy_id,
+		       a_uint32_t * ability)
+{
+	a_uint16_t phy_data;
+
+	*ability = 0;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_STATUS);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & QCA803X_STATUS_AUTONEG_CAPS)
+		*ability |= FAL_PHY_AUTONEG_CAPS;
+
+	if (phy_data & QCA803X_STATUS_100T2_HD_CAPS)
+		*ability |= FAL_PHY_100T2_HD_CAPS;
+
+	if (phy_data & QCA803X_STATUS_100T2_FD_CAPS)
+		*ability |= FAL_PHY_100T2_FD_CAPS;
+
+	if (phy_data & QCA803X_STATUS_10T_HD_CAPS)
+		*ability |= FAL_PHY_10T_HD_CAPS;
+
+	if (phy_data & QCA803X_STATUS_10T_FD_CAPS)
+		*ability |= FAL_PHY_10T_FD_CAPS;
+
+	if (phy_data & QCA803X_STATUS_100X_HD_CAPS)
+		*ability |= FAL_PHY_100X_HD_CAPS;
+
+	if (phy_data & QCA803X_STATUS_100X_FD_CAPS)
+		*ability |= FAL_PHY_100X_FD_CAPS;
+
+	if (phy_data & QCA803X_STATUS_100T4_CAPS)
+		*ability |= FAL_PHY_100T4_CAPS;
+
+	if (phy_data & QCA803X_STATUS_EXTENDED_STATUS) {
+		phy_data =
+		    qca803x_phy_reg_read(dev_id, phy_id, QCA803X_EXTENDED_STATUS);
+		PHY_RTN_ON_READ_ERROR(phy_data);
+
+		if (phy_data & QCA803X_STATUS_1000T_FD_CAPS) {
+			*ability |= FAL_PHY_1000T_FD_CAPS;
+		}
+
+		if (phy_data & QCA803X_STATUS_1000X_FD_CAPS) {
+			*ability |= FAL_PHY_1000X_FD_CAPS;
+		}
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get_partner_ability - get the phy ability
+*
+*
+*/
+sw_error_t
+qca803x_phy_get_partner_ability(a_uint32_t dev_id, a_uint32_t phy_id,
+			       a_uint32_t * ability)
+{
+	a_uint16_t phy_data;
+
+	*ability = 0;
+
+	phy_data =
+	    qca803x_phy_reg_read(dev_id, phy_id, QCA803X_LINK_PARTNER_ABILITY);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & QCA803X_LINK_10BASETX_HALF_DUPLEX)
+		*ability |= FAL_PHY_PART_10T_HD;
+
+	if (phy_data & QCA803X_LINK_10BASETX_FULL_DUPLEX)
+		*ability |= FAL_PHY_PART_10T_FD;
+
+	if (phy_data & QCA803X_LINK_100BASETX_HALF_DUPLEX)
+		*ability |= FAL_PHY_PART_100TX_HD;
+
+	if (phy_data & QCA803X_LINK_100BASETX_FULL_DUPLEX)
+		*ability |= FAL_PHY_PART_100TX_FD;
+
+	if (phy_data & QCA803X_LINK_NPAGE) {
+		phy_data =
+		    qca803x_phy_reg_read(dev_id, phy_id,
+					QCA803X_1000BASET_STATUS);
+		PHY_RTN_ON_READ_ERROR(phy_data);
+
+		if (phy_data & QCA803X_LINK_1000BASETX_FULL_DUPLEX)
+			*ability |= FAL_PHY_PART_1000T_FD;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_reset_done - reset the phy
+*
+* reset the phy
+*/
+a_bool_t qca803x_phy_reset_done(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	a_uint16_t ii = 200;
+
+	do {
+		phy_data =
+		    qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL);
+		aos_mdelay(10);
+	}
+	while ((!QCA803X_RESET_DONE(phy_data)) && --ii);
+
+	if (ii == 0)
+		return A_FALSE;
+
+	return A_TRUE;
+}
+
+/******************************************************************************
+*
+* qca803x_autoneg_done
+*
+* qca803x_autoneg_done
+*/
+a_bool_t qca803x_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	a_uint16_t ii = 200;
+
+	do {
+		phy_data =
+		    qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_STATUS);
+		aos_mdelay(10);
+	}
+	while ((!QCA803X_AUTONEG_DONE(phy_data)) && --ii);
+
+	if (ii == 0)
+		return A_FALSE;
+
+	return A_TRUE;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_Speed_Duplex_Resolved
+ - reset the phy
+*
+* reset the phy
+*/
+a_bool_t qca803x_phy_speed_duplex_resolved(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	a_uint16_t ii = 200;
+
+	do {
+		phy_data =
+		    qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_STATUS);
+		aos_mdelay(10);
+	}
+	while ((!QCA803X_SPEED_DUPLEX_RESOVLED(phy_data)) && --ii);
+
+	if (ii == 0)
+		return A_FALSE;
+
+	return A_TRUE;
+}
+#endif
+/******************************************************************************
+*
+* qca803x_phy_get_phy_id - get the phy id
+*
+*/
+sw_error_t
+qca803x_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *phy_data)
+{
+	a_uint16_t org_id, rev_id;
+
+	org_id = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_ID1);
+	rev_id = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_ID2);
+
+	*phy_data = ((org_id & 0xffff) << 16) | (rev_id & 0xffff);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_off - power off the phy
+*
+* Power off the phy
+*/
+sw_error_t qca803x_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL,
+				     phy_data | QCA803X_CTRL_POWER_DOWN);
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_on - power on the phy
+*
+* Power on the phy
+*/
+sw_error_t qca803x_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL,
+			phy_data & ~QCA803X_CTRL_POWER_DOWN);
+
+	aos_mdelay(200);
+
+	return SW_OK;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* qca803x_phy_set_802.3az
+*
+* set 802.3az status
+*/
+sw_error_t
+qca803x_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD7_NUM,
+				       QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (enable == A_TRUE) {
+		phy_data |= 0x0006;
+
+		qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD7_NUM,
+			     QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data);
+	} else {
+		phy_data &= ~0x0006;
+
+		qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD7_NUM,
+			     QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data);
+	}
+
+	qca803x_phy_restart_autoneg(dev_id, phy_id);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get_8023az status
+*
+* get 8023az status
+*/
+sw_error_t
+qca803x_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+	*enable = A_FALSE;
+
+	phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD7_NUM,
+				       QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if ((phy_data & 0x0004) && (phy_data & 0x0002))
+		*enable = A_TRUE;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_set_powersave - set power saving status
+*
+* set power saving status
+*/
+sw_error_t
+qca803x_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca803x_phy_debug_read(dev_id, phy_id, QCA803X_PWR_SAVE);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (enable == A_TRUE)
+		phy_data = phy_data | QCA803X_PWR_SAVE_EN;
+	else
+		phy_data = phy_data & ~QCA803X_PWR_SAVE_EN;
+
+	qca803x_phy_debug_write(dev_id, phy_id, QCA803X_PWR_SAVE, phy_data);
+
+	qca803x_phy_restart_autoneg(dev_id, phy_id);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get_powersave - get power saving status
+*
+* set power saving status
+*/
+sw_error_t
+qca803x_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca803x_phy_debug_read(dev_id, phy_id, QCA803X_PWR_SAVE);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & QCA803X_PWR_SAVE_EN)
+		*enable = A_FALSE;
+	else
+		*enable = A_TRUE;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_set wol frame mac address
+*
+* set phy wol frame mac address
+*/
+sw_error_t
+qca803x_phy_set_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id,
+			       fal_mac_addr_t * mac)
+{
+	a_uint16_t phy_data1;
+	a_uint16_t phy_data2;
+	a_uint16_t phy_data3;
+
+	phy_data1 = (mac->uc[0] << 8) | mac->uc[1];
+	phy_data2 = (mac->uc[2] << 8) | mac->uc[3];
+	phy_data3 = (mac->uc[4] << 8) | mac->uc[5];
+
+	qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD3_NUM,
+			     QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL1, phy_data1);
+
+	qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD3_NUM,
+			     QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL2, phy_data2);
+
+	qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD3_NUM,
+			     QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL3, phy_data3);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get wol frame mac address
+*
+* get phy wol frame mac address
+*/
+sw_error_t
+qca803x_phy_get_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id,
+			       fal_mac_addr_t * mac)
+{
+	a_uint16_t phy_data1;
+	a_uint16_t phy_data2;
+	a_uint16_t phy_data3;
+
+	phy_data1 = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM,
+					QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL1);
+
+	phy_data2 = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM,
+					QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL2);
+
+	phy_data3 = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM,
+					QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL3);
+
+	mac->uc[0] = (phy_data1 >> 8);
+	mac->uc[1] = (phy_data1 & 0x00ff);
+	mac->uc[2] = (phy_data2 >> 8);
+	mac->uc[3] = (phy_data2 & 0x00ff);
+	mac->uc[4] = (phy_data3 >> 8);
+	mac->uc[5] = (phy_data3 & 0x00ff);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_set wol enable or disable
+*
+* set phy wol enable or disable
+*/
+sw_error_t
+qca803x_phy_set_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM,
+				       QCA803X_PHY_MMD3_WOL_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (enable == A_TRUE) {
+		phy_data |= 0x0020;
+	} else {
+		phy_data &= ~0x0020;
+	}
+
+	qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD3_NUM,
+			     QCA803X_PHY_MMD3_WOL_CTRL, phy_data);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get_wol status
+*
+* get wol status
+*/
+sw_error_t
+qca803x_phy_get_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	*enable = A_FALSE;
+
+	phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM,
+				       QCA803X_PHY_MMD3_WOL_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & 0x0020)
+		*enable = A_TRUE;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_set_hibernate - set hibernate status
+*
+* set hibernate status
+*/
+sw_error_t
+qca803x_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca803x_phy_debug_read(dev_id, phy_id,
+			QCA803X_DEBUG_PHY_HIBERNATION_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (enable == A_TRUE) {
+		phy_data |= 0x8000;
+	} else {
+		phy_data &= ~0x8000;
+	}
+
+	qca803x_phy_debug_write(dev_id, phy_id,
+			QCA803X_DEBUG_PHY_HIBERNATION_CTRL, phy_data);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get_hibernate - get hibernate status
+*
+* get hibernate status
+*/
+sw_error_t
+qca803x_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	*enable = A_FALSE;
+
+	phy_data = qca803x_phy_debug_read(dev_id, phy_id,
+			QCA803X_DEBUG_PHY_HIBERNATION_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & 0x8000)
+		*enable = A_TRUE;
+
+	return SW_OK;
+}
+#endif
+sw_error_t
+__phy_chip_config_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		qca803x_cfg_type_t cfg_sel, qca803x_cfg_t *cfg_value)
+{
+	a_uint16_t phy_data;
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (cfg_sel == QCA803X_CHIP_CFG_STAT)
+		*cfg_value = (phy_data & QCA803X_PHY_CHIP_MODE_STAT) >> 4;
+	else
+		*cfg_value = phy_data & QCA803X_PHY_CHIP_MODE_CFG;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_interface mode set
+*
+* set qca803x phy interface mode
+*/
+sw_error_t
+qca803x_phy_interface_set_mode(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_interface_mode_t interface_mode)
+{
+	a_uint16_t phy_data;
+
+	QCA803X_REG_LOCK;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG);
+
+	phy_data &= 0xfff0;
+
+	switch (interface_mode) {
+		case PORT_RGMII_BASET:
+			phy_data |= QCA803X_PHY_RGMII_BASET;
+			break;
+		case PHY_SGMII_BASET:
+			phy_data |= QCA803X_PHY_SGMII_BASET;
+			break;
+		case PORT_RGMII_BX1000:
+			phy_data |= QCA803X_PHY_BX1000_RGMII_50;
+			break;
+		case PORT_RGMII_FX100:
+			phy_data |= QCA803X_PHY_FX100_RGMII_50;
+			break;
+		case PORT_RGMII_AMDET:
+			phy_data |= QCA803X_PHY_RGMII_AMDET;
+			break;
+		default:
+			QCA803X_REG_UNLOCK;
+			return SW_BAD_PARAM;
+	}
+
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG, phy_data);
+
+	QCA803X_REG_UNLOCK;
+
+	/* reset operation */
+	qca803x_phy_reset(dev_id, phy_id);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_interface mode get
+*
+* get qca803x phy interface mode
+*/
+sw_error_t
+qca803x_phy_interface_get_mode(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_interface_mode_t *interface_mode)
+{
+	qca803x_cfg_t cfg_value;
+	SW_RTN_ON_ERROR(__phy_chip_config_get(dev_id, phy_id,
+				QCA803X_CHIP_CFG_SET, &cfg_value));
+
+	switch (cfg_value) {
+		case QCA803X_PHY_RGMII_BASET:
+			*interface_mode = PORT_RGMII_BASET;
+			break;
+		case  QCA803X_PHY_SGMII_BASET:
+			*interface_mode = PHY_SGMII_BASET;
+			break;
+		case QCA803X_PHY_BX1000_RGMII_50:
+			*interface_mode = PORT_RGMII_BX1000;
+			break;
+		case QCA803X_PHY_FX100_RGMII_50:
+			*interface_mode = PORT_RGMII_FX100;
+			break;
+		case QCA803X_PHY_RGMII_AMDET:
+			*interface_mode = PORT_RGMII_AMDET;
+			break;
+		default:
+			*interface_mode = PORT_INTERFACE_MODE_MAX;
+			break;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_interface mode status get
+*
+* get qca803x phy interface mode status
+*/
+sw_error_t
+qca803x_phy_interface_get_mode_status(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_interface_mode_t *interface_mode_status)
+{
+	qca803x_cfg_t cfg_value;
+
+	SW_RTN_ON_ERROR(__phy_chip_config_get(dev_id, phy_id,
+				QCA803X_CHIP_CFG_STAT, &cfg_value));
+
+	switch (cfg_value) {
+		case QCA803X_PHY_RGMII_BASET:
+			*interface_mode_status = PORT_RGMII_BASET;
+			break;
+		case QCA803X_PHY_SGMII_BASET:
+			*interface_mode_status = PHY_SGMII_BASET;
+			break;
+		case QCA803X_PHY_BX1000_RGMII_50:
+			*interface_mode_status = PORT_RGMII_BX1000;
+			break;
+		case QCA803X_PHY_FX100_RGMII_50:
+			*interface_mode_status = PORT_RGMII_FX100;
+			break;
+		case QCA803X_PHY_RGMII_AMDET:
+			*interface_mode_status = PORT_RGMII_AMDET;
+			break;
+		default:
+			*interface_mode_status = PORT_INTERFACE_MODE_MAX;
+			break;
+	}
+
+	return SW_OK;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* qca803x_phy_set_intr_mask - Set interrupt mask with the
+* specified device.
+*/
+sw_error_t
+qca803x_phy_set_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_uint32_t intr_mask_flag)
+{
+	a_uint16_t phy_data = 0;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_INTR_MASK);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (FAL_PHY_INTR_STATUS_UP_CHANGE & intr_mask_flag) {
+		phy_data |= QCA803X_INTR_STATUS_UP_CHANGE;
+	} else {
+		phy_data &= (~QCA803X_INTR_STATUS_UP_CHANGE);
+	}
+
+	if (FAL_PHY_INTR_STATUS_DOWN_CHANGE & intr_mask_flag) {
+		phy_data |= QCA803X_INTR_STATUS_DOWN_CHANGE;
+	} else {
+		phy_data &= (~QCA803X_INTR_STATUS_DOWN_CHANGE);
+	}
+
+	if (FAL_PHY_INTR_SPEED_CHANGE & intr_mask_flag) {
+		phy_data |= QCA803X_INTR_SPEED_CHANGE;
+	} else {
+		phy_data &= (~QCA803X_INTR_SPEED_CHANGE);
+	}
+
+	/* DUPLEX INTR bit is reserved for AR803X phy
+	if (FAL_PHY_INTR_DUPLEX_CHANGE & intr_mask_flag) {
+		phy_data |= QCA803X_INTR_DUPLEX_CHANGE;
+	} else {
+		phy_data &= (~QCA803X_INTR_DUPLEX_CHANGE);
+	}
+	*/
+
+	if (FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE & intr_mask_flag) {
+		phy_data |= QCA803X_INTR_BX_FX_STATUS_UP_CHANGE;
+	} else {
+		phy_data &= (~QCA803X_INTR_BX_FX_STATUS_UP_CHANGE);
+	}
+
+	if (FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE & intr_mask_flag) {
+		phy_data |= QCA803X_INTR_BX_FX_STATUS_DOWN_CHANGE;
+	} else {
+		phy_data &= (~QCA803X_INTR_BX_FX_STATUS_DOWN_CHANGE);
+	}
+
+	if (FAL_PHY_INTR_MEDIA_STATUS_CHANGE & intr_mask_flag) {
+		phy_data |= QCA803X_INTR_MEDIA_STATUS_CHANGE;
+	} else {
+		phy_data &= (~QCA803X_INTR_MEDIA_STATUS_CHANGE);
+	}
+
+	if (FAL_PHY_INTR_WOL_STATUS & intr_mask_flag) {
+		phy_data |= QCA803X_INTR_WOL;
+	} else {
+		phy_data &= (~QCA803X_INTR_WOL);
+	}
+
+	if (FAL_PHY_INTR_POE_STATUS & intr_mask_flag) {
+		phy_data |= QCA803X_INTR_POE;
+	} else {
+		phy_data &= (~QCA803X_INTR_POE);
+	}
+
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_INTR_MASK, phy_data);
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get_intr_mask - Get interrupt mask with the
+* specified device.
+*/
+sw_error_t
+qca803x_phy_get_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_uint32_t * intr_mask_flag)
+{
+	a_uint16_t phy_data = 0;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_INTR_MASK);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	*intr_mask_flag = 0;
+	if (QCA803X_INTR_STATUS_UP_CHANGE & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE;
+	}
+
+	if (QCA803X_INTR_STATUS_DOWN_CHANGE & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE;
+	}
+
+	if (QCA803X_INTR_SPEED_CHANGE & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_SPEED_CHANGE;
+	}
+
+	/* DUPLEX INTR bit is reserved for AR803X phy
+	if (QCA803X_INTR_DUPLEX_CHANGE & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_DUPLEX_CHANGE;
+	}
+	*/
+
+	if (QCA803X_INTR_BX_FX_STATUS_UP_CHANGE & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE;
+	}
+
+	if (QCA803X_INTR_BX_FX_STATUS_DOWN_CHANGE & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE;
+	}
+
+	if (QCA803X_INTR_MEDIA_STATUS_CHANGE  & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_MEDIA_STATUS_CHANGE;
+	}
+
+	if (QCA803X_INTR_WOL  & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_WOL_STATUS;
+	}
+
+	if (QCA803X_INTR_POE  & phy_data) {
+		*intr_mask_flag |= FAL_PHY_INTR_POE_STATUS;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get_intr_status - Get interrupt status with the
+* specified device.
+*/
+sw_error_t
+qca803x_phy_get_intr_status(a_uint32_t dev_id, a_uint32_t phy_id,
+			   a_uint32_t * intr_status_flag)
+{
+	a_uint16_t phy_data = 0;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_INTR_STATUS);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	*intr_status_flag = 0;
+	if (QCA803X_INTR_STATUS_UP_CHANGE & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE;
+	}
+
+	if (QCA803X_INTR_STATUS_DOWN_CHANGE & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE;
+	}
+
+	if (QCA803X_INTR_SPEED_CHANGE & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_SPEED_CHANGE;
+	}
+
+	/* DUPLEX INTR bit is reserved for AR803X phy
+	if (QCA803X_INTR_DUPLEX_CHANGE & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_DUPLEX_CHANGE;
+	}
+	*/
+
+	if (QCA803X_INTR_BX_FX_STATUS_UP_CHANGE & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE;
+	}
+
+	if (QCA803X_INTR_BX_FX_STATUS_DOWN_CHANGE & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE;
+	}
+	if (QCA803X_INTR_MEDIA_STATUS_CHANGE  & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_MEDIA_STATUS_CHANGE;
+	}
+
+	if (QCA803X_INTR_WOL  & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_WOL_STATUS;
+	}
+
+	if (QCA803X_INTR_POE  & phy_data) {
+		*intr_status_flag |= FAL_PHY_INTR_POE_STATUS;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_set combo medium type
+*
+* set combo medium fiber or copper
+*/
+sw_error_t
+qca803x_phy_set_combo_prefer_medium(a_uint32_t dev_id, a_uint32_t phy_id,
+				   fal_port_medium_t phy_medium)
+{
+	a_uint16_t phy_data;
+
+	QCA803X_REG_LOCK;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG);
+
+	if (phy_medium == PHY_MEDIUM_FIBER)
+		phy_data |= QCA803X_PHY_PREFER_FIBER;
+	else if (phy_medium == PHY_MEDIUM_COPPER)
+		phy_data &= ~QCA803X_PHY_PREFER_FIBER;
+	else {
+		QCA803X_REG_UNLOCK;
+		return SW_BAD_PARAM;
+	}
+
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG, phy_data);
+
+	QCA803X_REG_UNLOCK;
+
+	/* soft reset after switching combo medium*/
+	qca803x_phy_reset(dev_id, phy_id);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get combo medium type
+*
+* get combo medium fiber or copper
+*/
+sw_error_t
+qca803x_phy_get_combo_prefer_medium(a_uint32_t dev_id, a_uint32_t phy_id,
+				   fal_port_medium_t * phy_medium)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	*phy_medium =
+	    (phy_data & QCA803X_PHY_PREFER_FIBER) ? PHY_MEDIUM_FIBER :
+	    PHY_MEDIUM_COPPER;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+*  qca803x phy activer medium
+*
+*  get qca803x phy current active medium, fiber or copper;
+*/
+static qca803x_phy_medium_t __phy_active_medium_get(a_uint32_t dev_id,
+						   a_uint32_t phy_id)
+{
+	qca803x_cfg_t cfg_value;
+
+	SW_RTN_ON_ERROR(__phy_chip_config_get(dev_id, phy_id,
+				QCA803X_CHIP_CFG_STAT, &cfg_value));
+
+	switch (cfg_value) {
+		case QCA803X_PHY_RGMII_BASET:
+		case QCA803X_PHY_SGMII_BASET:
+			return QCA803X_PHY_MEDIUM_COPPER;
+		case QCA803X_PHY_BX1000_RGMII_50:
+		case QCA803X_PHY_FX100_RGMII_50:
+			return QCA803X_PHY_MEDIUM_FIBER;
+		case QCA803X_PHY_RGMII_AMDET:
+		default:
+			return QCA803X_PHY_MEDIUM_MAX;
+	}
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get current combo medium type copper or fiber
+*
+* get current combo medium type
+*/
+sw_error_t
+qca803x_phy_get_combo_current_medium_type(a_uint32_t dev_id, a_uint32_t phy_id,
+					 fal_port_medium_t * phy_medium)
+{
+	qca803x_phy_medium_t phy_cur_meduim = __phy_active_medium_get(dev_id, phy_id);
+
+	/* auto media select is not done
+	 * or link down, then return prefer medium */
+	if (phy_cur_meduim == QCA803X_PHY_MEDIUM_MAX)
+		qca803x_phy_get_combo_prefer_medium(dev_id, phy_id, phy_medium);
+	else
+		*phy_medium = phy_cur_meduim;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_set fiber mode 1000bx or 100fx
+*
+* set combo fbier mode
+*/
+sw_error_t
+qca803x_phy_set_combo_fiber_mode(a_uint32_t dev_id, a_uint32_t phy_id,
+				fal_port_fiber_mode_t fiber_mode)
+{
+	a_uint16_t phy_data;
+
+	QCA803X_REG_LOCK;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG);
+
+	if (fiber_mode == PHY_FIBER_1000BX) {
+		phy_data |= QCA803X_PHY_FIBER_MODE_1000BX;
+	} else if (fiber_mode == PHY_FIBER_100FX) {
+		phy_data &= ~QCA803X_PHY_FIBER_MODE_1000BX;
+	} else {
+		QCA803X_REG_UNLOCK;
+		return SW_BAD_PARAM;
+	}
+
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG, phy_data);
+
+	QCA803X_REG_UNLOCK;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get fiber mode 1000bx or 100fx
+*
+* get combo fbier mode
+*/
+sw_error_t
+qca803x_phy_get_combo_fiber_mode(a_uint32_t dev_id, a_uint32_t phy_id,
+				fal_port_fiber_mode_t * fiber_mode)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	*fiber_mode =
+	    (phy_data & QCA803X_PHY_FIBER_MODE_1000BX) ? PHY_FIBER_1000BX :
+	    PHY_FIBER_100FX;
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_set_counter_status - set counter status
+*
+*/
+sw_error_t
+qca803x_phy_set_counter_status(a_uint32_t dev_id, a_uint32_t phy_id,
+			a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	a_uint16_t frame_dir = 0;
+
+	phy_data = qca803x_phy_mmd_read(dev_id, phy_id,
+					QCA803X_PHY_MMD7_NUM,
+					QCA803X_PHY_MMD7_FRAME_CTRL);
+	frame_dir = (phy_data & QCA803X_PHY_MMD7_FRAME_DIR) >> 14;
+
+	/*for qca803x phy, tx and rx cannot be all enabled one time,
+	  so we will enable tx or rx based current state, enable rx if
+	  current is tx and enable tx if current is rx*/
+	if (enable == A_TRUE)
+	{
+		phy_data |= QCA803X_PHY_MMD7_FRAME_CHECK;
+		/*enable RX counter*/
+		if(frame_dir)
+		{
+			SSDK_INFO("ENABLE QCA803X RX COUNTER\n");
+			phy_data &= ~QCA803X_PHY_MMD7_FRAME_DIR;
+		}
+		/*enable TX counter*/
+		else
+		{
+			SSDK_INFO("ENABLE QCA803X TX COUNTER\n");
+			phy_data |= QCA803X_PHY_MMD7_FRAME_DIR;
+		}
+	}
+	else
+	{
+		phy_data &= ~QCA803X_PHY_MMD7_FRAME_CHECK;
+	}
+
+	qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD7_NUM,
+			     QCA803X_PHY_MMD7_FRAME_CTRL, phy_data);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get_counter_status - get counter status
+*
+*/
+sw_error_t
+qca803x_phy_get_counter_status(a_uint32_t dev_id, a_uint32_t phy_id,
+			a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+	*enable = A_FALSE;
+
+	phy_data = qca803x_phy_mmd_read(dev_id, phy_id,
+					QCA803X_PHY_MMD7_NUM,
+					QCA803X_PHY_MMD7_FRAME_CTRL);
+
+	if (phy_data & QCA803X_PHY_MMD7_FRAME_CHECK) {
+		*enable = A_TRUE;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_show_counter - show counter statistics
+*
+*/
+sw_error_t
+qca803x_phy_show_counter(a_uint32_t dev_id, a_uint32_t phy_id,
+			 fal_port_counter_info_t * counter_infor)
+{
+	a_uint16_t phy_data, phy_data1;
+	a_uint16_t frame_dir = 0;
+
+	phy_data = qca803x_phy_mmd_read(dev_id, phy_id,
+					QCA803X_PHY_MMD7_NUM,
+					QCA803X_PHY_MMD7_FRAME_CTRL);
+	phy_data1 = qca803x_phy_mmd_read(dev_id, phy_id,
+					QCA803X_PHY_MMD7_NUM,
+					QCA803X_PHY_MMD7_FRAME_DATA);
+	frame_dir = (phy_data & QCA803X_PHY_MMD7_FRAME_DIR) >> 14;
+
+	if(frame_dir)
+	{
+		/*get the counter of tx*/
+		counter_infor->TxGoodFrame = phy_data1 & QCA803X_PHY_FRAME_CNT;
+		counter_infor->TxBadCRC = (phy_data1 & QCA803X_PHY_FRAME_ERROR) >> 8;
+		counter_infor->RxGoodFrame = 0;
+		counter_infor->RxBadCRC = 0;
+	}
+	else
+	{
+		/*get the counter of rx*/
+		counter_infor->TxGoodFrame = 0;
+		counter_infor->TxBadCRC = 0;
+		counter_infor->RxGoodFrame = phy_data1 & QCA803X_PHY_FRAME_CNT;
+		counter_infor->RxBadCRC = (phy_data1 & QCA803X_PHY_FRAME_ERROR) >> 8;
+	}
+
+	return SW_OK;
+}
+
+#endif
+/******************************************************************************
+*
+* qca803x_phy_get status
+*
+* get phy status
+*/
+sw_error_t
+qca803x_phy_get_status(a_uint32_t dev_id, a_uint32_t phy_id,
+		struct port_phy_status *phy_status)
+{
+	a_uint16_t phy_data, phy_data1;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_STATUS);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+	phy_data1 = qca803x_phy_debug_read(dev_id, phy_id,
+		QCA803X_DEBUG_MSE_THRESH);
+	PHY_RTN_ON_READ_ERROR(phy_data1);
+
+	/*get phy link status*/
+	if (phy_data & QCA803X_STATUS_LINK_PASS) {
+		phy_status->link_status = A_TRUE;
+		if((phy_data1 & QCA803X_PHY_MSE_THRESH_MASK) !=
+			QCA803X_PHY_MSE_THRESH_LINK_UP) {
+			phy_data1 &= ~QCA803X_PHY_MSE_THRESH_MASK;
+			SW_RTN_ON_ERROR(qca803x_phy_debug_write(dev_id,
+				phy_id, QCA803X_DEBUG_MSE_THRESH,
+				phy_data1 | QCA803X_PHY_MSE_THRESH_LINK_UP));
+		}
+	}
+	else {
+		phy_status->link_status = A_FALSE;
+		if((phy_data1 & QCA803X_PHY_MSE_THRESH_MASK) !=
+			QCA803X_PHY_MSE_THRESH_LINK_DOWN) {
+			phy_data1 &= ~QCA803X_PHY_MSE_THRESH_MASK;
+			SW_RTN_ON_ERROR(qca803x_phy_debug_write(dev_id,
+				phy_id, QCA803X_DEBUG_MSE_THRESH,
+				phy_data1 | QCA803X_PHY_MSE_THRESH_LINK_DOWN));
+		}
+		return SW_OK;
+	}
+
+	/*get phy speed*/
+	switch (phy_data & QCA803X_STATUS_SPEED_MASK) {
+	case QCA803X_STATUS_SPEED_1000MBS:
+		phy_status->speed = FAL_SPEED_1000;
+		break;
+	case QCA803X_STATUS_SPEED_100MBS:
+		phy_status->speed = FAL_SPEED_100;
+		break;
+	case QCA803X_STATUS_SPEED_10MBS:
+		phy_status->speed = FAL_SPEED_10;
+		break;
+	default:
+		return SW_READ_ERROR;
+	}
+
+	/*get phy duplex*/
+	if (phy_data & QCA803X_STATUS_FULL_DUPLEX)
+		phy_status->duplex = FAL_FULL_DUPLEX;
+	else
+		phy_status->duplex = FAL_HALF_DUPLEX;
+
+	/* get phy flowctrl resolution status */
+	if (phy_data & QCA803X_PHY_RX_FLOWCTRL_STATUS)
+		phy_status->rx_flowctrl = A_TRUE;
+	else
+		phy_status->rx_flowctrl = A_FALSE;
+
+	if (phy_data & QCA803X_PHY_TX_FLOWCTRL_STATUS)
+		phy_status->tx_flowctrl = A_TRUE;
+	else
+		phy_status->tx_flowctrl = A_FALSE;
+
+	return SW_OK;
+}
+/******************************************************************************
+*
+* qca803x_phy_set_eee_advertisement
+*
+* set eee advertisement
+*/
+sw_error_t
+qca803x_phy_set_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t adv)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD7_NUM,
+				       QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL);
+	phy_data &= ~(QCA803X_PHY_EEE_ADV_100M | QCA803X_PHY_EEE_ADV_1000M);
+
+	if (adv & FAL_PHY_EEE_100BASE_T) {
+		phy_data |= QCA803X_PHY_EEE_ADV_100M;
+	}
+	if (adv & FAL_PHY_EEE_1000BASE_T) {
+		phy_data |= QCA803X_PHY_EEE_ADV_1000M;
+	}
+
+	rv = qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD7_NUM,
+		     QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data);
+
+	rv = qca803x_phy_restart_autoneg(dev_id, phy_id);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_get_eee_advertisement
+*
+* get eee advertisement
+*/
+sw_error_t
+qca803x_phy_get_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *adv)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	*adv = 0;
+	phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD7_NUM,
+				       QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL);
+
+	if (phy_data & QCA803X_PHY_EEE_ADV_100M) {
+		*adv |= FAL_PHY_EEE_100BASE_T;
+	}
+	if (phy_data & QCA803X_PHY_EEE_ADV_1000M) {
+		*adv |= FAL_PHY_EEE_1000BASE_T;
+	}
+
+	return rv;
+}
+/******************************************************************************
+*
+* qca803x_phy_get_eee_partner_advertisement
+*
+* get eee partner advertisement
+*/
+sw_error_t
+qca803x_phy_get_eee_partner_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *adv)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	*adv = 0;
+	phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD7_NUM,
+				       QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_PARTNER);
+
+	if (phy_data & QCA803X_PHY_EEE_PARTNER_ADV_100M) {
+		*adv |= FAL_PHY_EEE_100BASE_T;
+	}
+	if (phy_data & QCA803X_PHY_EEE_PARTNER_ADV_1000M) {
+		*adv |= FAL_PHY_EEE_1000BASE_T;
+	}
+
+	return rv;
+}
+/******************************************************************************
+*
+* qca803x_phy_get_eee_capability
+*
+* get eee capability
+*/
+sw_error_t
+qca803x_phy_get_eee_cap(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *cap)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	*cap = 0;
+	phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM,
+				       QCA803X_PHY_MMD3_ADDR_8023AZ_EEE_CAPABILITY);
+
+	if (phy_data & QCA803X_PHY_EEE_CAPABILITY_100M) {
+		*cap |= FAL_PHY_EEE_100BASE_T;
+	}
+	if (phy_data & QCA803X_PHY_EEE_CAPABILITY_1000M) {
+		*cap |= FAL_PHY_EEE_1000BASE_T;
+	}
+
+	return rv;
+}
+/******************************************************************************
+*
+* qca803x_phy_get_eee_status
+*
+* get eee status
+*/
+sw_error_t
+qca803x_phy_get_eee_status(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *status)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	*status = 0;
+	phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD7_NUM,
+				       QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_STATUS);
+
+	if (phy_data & QCA803X_PHY_EEE_STATUS_100M) {
+		*status |= FAL_PHY_EEE_100BASE_T;
+	}
+	if (phy_data & QCA803X_PHY_EEE_STATUS_1000M) {
+		*status |= FAL_PHY_EEE_1000BASE_T;
+	}
+
+	return rv;
+}
+
+static sw_error_t qca803x_phy_api_ops_init(void)
+{
+	sw_error_t  ret = SW_OK;
+	hsl_phy_ops_t *qca803x_phy_api_ops = NULL;
+
+	qca803x_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL);
+	if (qca803x_phy_api_ops == NULL) {
+		SSDK_ERROR("qca803x phy ops kzalloc failed!\n");
+		return -ENOMEM;
+	}
+
+	phy_api_ops_init(QCA803X_PHY_CHIP);
+
+	qca803x_phy_api_ops->phy_speed_get = qca803x_phy_get_speed;
+	qca803x_phy_api_ops->phy_speed_set = qca803x_phy_set_speed;
+	qca803x_phy_api_ops->phy_duplex_get = qca803x_phy_get_duplex;
+	qca803x_phy_api_ops->phy_duplex_set = qca803x_phy_set_duplex;
+	qca803x_phy_api_ops->phy_autoneg_enable_set = qca803x_phy_enable_autoneg;
+	qca803x_phy_api_ops->phy_restart_autoneg = qca803x_phy_restart_autoneg;
+	qca803x_phy_api_ops->phy_autoneg_status_get = qca803x_phy_autoneg_status;
+	qca803x_phy_api_ops->phy_autoneg_adv_set = qca803x_phy_set_autoneg_adv;
+	qca803x_phy_api_ops->phy_autoneg_adv_get = qca803x_phy_get_autoneg_adv;
+	qca803x_phy_api_ops->phy_link_status_get = qca803x_phy_get_link_status;
+	qca803x_phy_api_ops->phy_reset = qca803x_phy_reset;
+#ifndef IN_PORTCONTROL_MINI
+	qca803x_phy_api_ops->phy_powersave_set = qca803x_phy_set_powersave;
+	qca803x_phy_api_ops->phy_powersave_get = qca803x_phy_get_powersave;
+	qca803x_phy_api_ops->phy_cdt = qca803x_phy_cdt;
+	qca803x_phy_api_ops->phy_mdix_set = qca803x_phy_set_mdix;
+	qca803x_phy_api_ops->phy_mdix_get = qca803x_phy_get_mdix;
+	qca803x_phy_api_ops->phy_mdix_status_get = qca803x_phy_get_mdix_status;
+	qca803x_phy_api_ops->phy_local_loopback_set = qca803x_phy_set_local_loopback;
+	qca803x_phy_api_ops->phy_local_loopback_get = qca803x_phy_get_local_loopback;
+	qca803x_phy_api_ops->phy_remote_loopback_set = qca803x_phy_set_remote_loopback;
+	qca803x_phy_api_ops->phy_remote_loopback_get = qca803x_phy_get_remote_loopback;
+#endif
+	qca803x_phy_api_ops->phy_reg_write = qca803x_phy_reg_write;
+	qca803x_phy_api_ops->phy_reg_read = qca803x_phy_reg_read;
+	qca803x_phy_api_ops->phy_debug_write = qca803x_phy_debug_write;
+	qca803x_phy_api_ops->phy_debug_read = qca803x_phy_debug_read;
+	qca803x_phy_api_ops->phy_mmd_write = qca803x_phy_mmd_write;
+	qca803x_phy_api_ops->phy_mmd_read = qca803x_phy_mmd_read;
+	qca803x_phy_api_ops->phy_id_get = qca803x_phy_get_phy_id;
+	qca803x_phy_api_ops->phy_power_off = qca803x_phy_poweroff;
+	qca803x_phy_api_ops->phy_power_on = qca803x_phy_poweron;
+#ifndef IN_PORTCONTROL_MINI
+	qca803x_phy_api_ops->phy_8023az_set = qca803x_phy_set_8023az;
+	qca803x_phy_api_ops->phy_8023az_get = qca803x_phy_get_8023az;
+	qca803x_phy_api_ops->phy_hibernation_set = qca803x_phy_set_hibernate;
+	qca803x_phy_api_ops->phy_hibernation_get = qca803x_phy_get_hibernate;
+	qca803x_phy_api_ops->phy_magic_frame_mac_set = qca803x_phy_set_magic_frame_mac;
+	qca803x_phy_api_ops->phy_magic_frame_mac_get = qca803x_phy_get_magic_frame_mac;
+	qca803x_phy_api_ops->phy_wol_status_set = qca803x_phy_set_wol_status;
+	qca803x_phy_api_ops->phy_wol_status_get = qca803x_phy_get_wol_status;
+#endif
+	qca803x_phy_api_ops->phy_interface_mode_set = qca803x_phy_interface_set_mode;
+	qca803x_phy_api_ops->phy_interface_mode_get = qca803x_phy_interface_get_mode;
+	qca803x_phy_api_ops->phy_interface_mode_status_get = qca803x_phy_interface_get_mode_status;
+#ifndef IN_PORTCONTROL_MINI
+	qca803x_phy_api_ops->phy_intr_mask_set = qca803x_phy_set_intr_mask;
+	qca803x_phy_api_ops->phy_intr_mask_get = qca803x_phy_get_intr_mask;
+	qca803x_phy_api_ops->phy_intr_status_get = qca803x_phy_get_intr_status;
+	qca803x_phy_api_ops->phy_combo_prefer_medium_set = qca803x_phy_set_combo_prefer_medium;
+	qca803x_phy_api_ops->phy_combo_prefer_medium_get = qca803x_phy_get_combo_prefer_medium;
+	qca803x_phy_api_ops->phy_combo_medium_status_get = qca803x_phy_get_combo_current_medium_type;
+	qca803x_phy_api_ops->phy_combo_fiber_mode_set = qca803x_phy_set_combo_fiber_mode;
+	qca803x_phy_api_ops->phy_combo_fiber_mode_get = qca803x_phy_get_combo_fiber_mode;
+	qca803x_phy_api_ops->phy_counter_set = qca803x_phy_set_counter_status;
+	qca803x_phy_api_ops->phy_counter_get = qca803x_phy_get_counter_status;
+	qca803x_phy_api_ops->phy_counter_show = qca803x_phy_show_counter;
+#endif
+	qca803x_phy_api_ops->phy_get_status = qca803x_phy_get_status;
+	qca803x_phy_api_ops->phy_eee_adv_set = qca803x_phy_set_eee_adv;
+	qca803x_phy_api_ops->phy_eee_adv_get = qca803x_phy_get_eee_adv;
+	qca803x_phy_api_ops->phy_eee_partner_adv_get = qca803x_phy_get_eee_partner_adv;
+	qca803x_phy_api_ops->phy_eee_cap_get = qca803x_phy_get_eee_cap;
+	qca803x_phy_api_ops->phy_eee_status_get = qca803x_phy_get_eee_status;
+
+	ret = hsl_phy_api_ops_register(QCA803X_PHY_CHIP, qca803x_phy_api_ops);
+
+	if (ret == SW_OK)
+		SSDK_INFO("qca probe qca803x phy driver succeeded!\n");
+	else
+		SSDK_ERROR("qca probe qca803x phy driver failed! (code: %d)\n", ret);
+
+	return ret;
+}
+
+static sw_error_t
+_qca803x_phy_set_combo_page_regs(a_uint32_t dev_id, a_uint32_t phy_id,
+				   qca803x_phy_medium_t phy_medium)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_medium == QCA803X_PHY_MEDIUM_FIBER) {
+		phy_data &= ~QCA803X_PHY_COPPER_PAGE_SEL;
+	}
+	else if (phy_medium == QCA803X_PHY_MEDIUM_COPPER) {
+		phy_data |= QCA803X_PHY_COPPER_PAGE_SEL;
+	}
+	else {
+		return SW_BAD_PARAM;
+	}
+
+	qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG, phy_data);
+
+	return SW_OK;
+}
+
+void qca803x_combo_phy_polling(qca803x_priv_t *priv)
+{
+
+	qca803x_cfg_t cfg_value;
+	a_uint32_t combo_phy_addr = 0;
+	a_uint32_t combo_bits = priv->combo_phy_bmp;
+	qca803x_phy_medium_t combo_cfg_new = QCA803X_PHY_MEDIUM_COPPER;
+
+	while (combo_bits) {
+		if (combo_bits & 1) {
+			QCA803X_REG_LOCK;
+			__phy_chip_config_get(priv->dev_id, combo_phy_addr,
+					QCA803X_CHIP_CFG_STAT, &cfg_value);
+
+			switch (cfg_value) {
+				case QCA803X_PHY_RGMII_BASET:
+				case QCA803X_PHY_SGMII_BASET:
+					combo_cfg_new = QCA803X_PHY_MEDIUM_COPPER;
+					break;
+				case QCA803X_PHY_BX1000_RGMII_50:
+				case QCA803X_PHY_FX100_RGMII_50:
+					combo_cfg_new = QCA803X_PHY_MEDIUM_FIBER;
+					break;
+				default:
+					combo_cfg_new = QCA803X_PHY_MEDIUM_COPPER;
+			}
+
+			if (priv->combo_cfg[combo_phy_addr] != combo_cfg_new) {
+				priv->combo_cfg[combo_phy_addr] = combo_cfg_new;
+				_qca803x_phy_set_combo_page_regs(priv->dev_id, combo_phy_addr, combo_cfg_new);
+			}
+
+			QCA803X_REG_UNLOCK;
+		}
+		combo_bits >>= 1;
+		combo_phy_addr++;
+	}
+}
+
+void
+qca803x_phy_polling_work(struct work_struct *work)
+{
+	qca803x_priv_t *priv = container_of(work, qca803x_priv_t,
+					phy_sync_dwork.work);
+	qca803x_combo_phy_polling(priv);
+
+	schedule_delayed_work(&priv->phy_sync_dwork,
+					QCA803X_PHY_DELAYED_INIT_TICKS);
+}
+
+sw_error_t
+qca803x_phy_work_start(a_uint32_t dev_id)
+{
+	qca803x_priv_t *priv = &g_qca803x_phy;
+	priv->dev_id = dev_id;
+
+	INIT_DELAYED_WORK(&priv->phy_sync_dwork,
+					qca803x_phy_polling_work);
+	schedule_delayed_work(&priv->phy_sync_dwork,
+					QCA803X_PHY_DELAYED_INIT_TICKS);
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_hw_init
+*
+*/
+sw_error_t
+qca803x_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_bmp)
+{
+	sw_error_t  ret = SW_OK;
+	a_uint32_t port_id = 0, phy_addr = 0, mac_mode = 0;
+	a_uint16_t phy_data= 0;
+
+	for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++)
+	{
+		if (port_bmp & (0x1 << port_id))
+		{
+			/*config phy mode based on the mac mode DT*/
+			switch (port_id) {
+				case SSDK_PHYSICAL_PORT0:
+					mac_mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0);
+					break;
+				case SSDK_PHYSICAL_PORT6:
+					mac_mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE2);
+					break;
+				default:
+					mac_mode = PORT_WRAPPER_MAX;
+			}
+
+			phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id);
+			if (mac_mode == PORT_WRAPPER_SGMII_CHANNEL0)
+				qca803x_phy_interface_set_mode(dev_id, phy_addr, PHY_SGMII_BASET);
+			else if (mac_mode == PORT_WRAPPER_RGMII)
+				qca803x_phy_interface_set_mode(dev_id, phy_addr, PORT_RGMII_BASET);
+
+			if (A_TRUE == hsl_port_phy_combo_capability_get(dev_id, port_id)) {
+				g_qca803x_phy.combo_phy_bmp |= (0x1 << phy_addr);
+				qca803x_phy_interface_set_mode(dev_id, phy_addr, PORT_RGMII_AMDET);
+			}
+			/*config the times that MSE is over threshold as max*/
+			phy_data = qca803x_phy_debug_read(dev_id, phy_addr,
+				QCA803X_DEBUG_MSE_OVER_THRESH_TIMES);
+			PHY_RTN_ON_READ_ERROR(phy_data);
+			ret = qca803x_phy_debug_write(dev_id, phy_addr,
+				QCA803X_DEBUG_MSE_OVER_THRESH_TIMES, phy_data |
+				QCA803X_PHY_MSE_OVER_THRESH_TIMES_MAX);
+			SW_RTN_ON_ERROR(ret);
+		}
+	}
+
+	/* start polling task for the combo port */
+	if (g_qca803x_phy.combo_phy_bmp)
+		qca803x_phy_work_start(dev_id);
+
+	return ret;
+}
+
+/******************************************************************************
+*
+* qca803x_phy_init -
+*
+*/
+int qca803x_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp)
+{
+	static a_uint32_t phy_ops_flag = 0;
+
+	if(phy_ops_flag == 0) {
+		QCA803X_LOCKER_INIT;
+		qca803x_phy_api_ops_init();
+		phy_ops_flag = 1;
+	}
+
+	qca803x_phy_hw_init(dev_id, port_bmp);
+	return 0;
+}
diff --git a/qca-ssdk/src/hsl/phy/qca808x.c b/qca-ssdk/src/hsl/phy/qca808x.c
new file mode 100755
index 0000000..4a6301a
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/qca808x.c
@@ -0,0 +1,658 @@
+/*
+ * Copyright (c) 2018-2019, 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "qca808x.h"
+
+#if defined(IN_PHY_I2C_MODE)
+#include "sfp_phy.h"
+#endif
+
+#define PHY_INVALID_DATA            0xffff
+#define QCA808X_INTR_INIT           0xec00
+
+#define QCA808X_PHY_LINK_UP         1
+#define QCA808X_PHY_LINK_DOWN       0
+
+LIST_HEAD(g_qca808x_phy_list);
+
+struct qca808x_phy_info* qca808x_phy_info_get(a_uint32_t phy_addr)
+{
+	struct qca808x_phy_info *pdata = NULL;
+	list_for_each_entry(pdata, &g_qca808x_phy_list, list) {
+		if (pdata->phydev_addr == phy_addr) {
+			return pdata;
+		}
+	}
+
+	SSDK_ERROR("%s can't get the data for phy addr: %d\n", __func__, phy_addr);
+	return NULL;
+}
+
+static a_bool_t qca808x_sfp_present(struct phy_device *phydev)
+{
+	qca808x_priv *priv = phydev->priv;
+	struct qca808x_phy_info *pdata = priv->phy_info;
+	a_uint32_t phy_id = 0;
+	sw_error_t rv = SW_OK;
+
+	if (!pdata) {
+		SSDK_ERROR("pdata is null\n");
+		return A_FALSE;
+	}
+	rv = qca808x_phy_get_phy_id(pdata->dev_id, pdata->phy_addr, &phy_id);
+	if(rv == SW_READ_ERROR) {
+		return A_FALSE;
+	}
+
+	return A_TRUE;
+}
+
+static sw_error_t qca808x_phy_config_init(struct phy_device *phydev)
+{
+	a_uint16_t phy_data;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+	a_uint32_t features;
+#else
+	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+#endif
+	a_uint32_t dev_id = 0, phy_id = 0;
+	qca808x_priv *priv = phydev->priv;
+	struct qca808x_phy_info *pdata = priv->phy_info;
+
+	if (!pdata) {
+		return SW_NOT_FOUND;
+	}
+
+	dev_id = pdata->dev_id;
+	phy_id = pdata->phy_addr;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+	features = SUPPORTED_TP | SUPPORTED_MII |
+		SUPPORTED_AUI | SUPPORTED_BNC;
+#else
+	linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask);
+	linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask);
+	linkmode_set_bit(ETHTOOL_LINK_MODE_AUI_BIT, mask);
+	linkmode_set_bit(ETHTOOL_LINK_MODE_BNC_BIT, mask);
+#endif
+
+	phy_data = qca808x_phy_reg_read(dev_id,
+			phy_id, QCA808X_PHY_STATUS);
+
+	if (phy_data == PHY_INVALID_DATA) {
+		return SW_READ_ERROR;
+	}
+
+	if (phy_data & QCA808X_STATUS_AUTONEG_CAPS) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+		features |= SUPPORTED_Autoneg;
+#else
+		linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask);
+#endif
+	}
+	if (phy_data & QCA808X_STATUS_100TX_FD_CAPS) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+		features |= SUPPORTED_100baseT_Full;
+#else
+		linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
+#endif
+	}
+	if (phy_data & QCA808X_STATUS_100TX_HD_CAPS) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+		features |= SUPPORTED_100baseT_Half;
+#else
+		linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
+#endif
+	}
+	if (phy_data & QCA808X_STATUS_10T_FD_CAPS) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+		features |= SUPPORTED_10baseT_Full;
+#else
+		linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, mask);
+#endif
+	}
+	if (phy_data & QCA808X_STATUS_10T_HD_CAPS) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+		features |= SUPPORTED_10baseT_Half;
+#else
+		linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, mask);
+#endif
+	}
+
+	if (phy_data & QCA808X_STATUS_EXTENDED_STATUS) {
+		phy_data = qca808x_phy_reg_read(dev_id,
+				phy_id, QCA808X_EXTENDED_STATUS);
+
+		if (phy_data == PHY_INVALID_DATA) {
+			return SW_READ_ERROR;
+		}
+		if (phy_data & QCA808X_STATUS_1000T_FD_CAPS) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+			features |= SUPPORTED_1000baseT_Full;
+#else
+			linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+					mask);
+#endif
+		}
+		if (phy_data & QCA808X_STATUS_1000T_HD_CAPS) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+			features |= SUPPORTED_1000baseT_Half;
+#else
+			linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+					mask);
+#endif
+		}
+	}
+
+#if 0
+	if(qca808x_phy_2500caps(dev_id, phy_id)) {
+		phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+				QCA808X_MMD1_PMA_CAP_REG);
+
+		if (phy_data & QCA808X_STATUS_2500T_FD_CAPS) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+			features |= SUPPORTED_2500baseX_Full;
+#else
+			linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, mask);
+#endif
+		}
+	}
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+	phydev->supported = features;
+	phydev->advertising = features;
+#else
+	linkmode_copy(phydev->supported, mask);
+	linkmode_copy(phydev->advertising, mask);
+#endif
+
+	return SW_OK;
+}
+
+static a_bool_t qca808x_config_init_done = A_FALSE;
+static int _qca808x_config_init(struct phy_device *phydev)
+{
+	int ret = 0;
+#if defined(IN_LINUX_STD_PTP)
+	/* ptp function initialization */
+	ret |= qca808x_ptp_config_init(phydev);
+#endif
+
+	ret |= qca808x_phy_config_init(phydev);
+
+	return ret;
+}
+
+static int qca808x_config_init(struct phy_device *phydev)
+{
+	int ret = 0;
+
+	if(!qca808x_sfp_present(phydev))
+	{
+		return 0;
+	}
+	ret = _qca808x_config_init(phydev);
+	if(!ret)
+	{
+		qca808x_config_init_done = A_TRUE;
+	}
+
+	return ret;
+}
+
+static int qca808x_config_intr(struct phy_device *phydev)
+{
+	int err;
+	a_uint16_t phy_data;
+	a_uint32_t dev_id = 0, phy_id = 0;
+	qca808x_priv *priv = phydev->priv;
+	const struct qca808x_phy_info *pdata = priv->phy_info;
+
+	if (!pdata) {
+		return SW_FAIL;
+	}
+
+	dev_id = pdata->dev_id;
+	phy_id = pdata->phy_addr;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id,
+			QCA808X_PHY_INTR_MASK);
+
+	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+		err = qca808x_phy_reg_write(dev_id, phy_id,
+				QCA808X_PHY_INTR_MASK,
+				phy_data | QCA808X_INTR_INIT);
+	} else {
+		err = qca808x_phy_reg_write(dev_id, phy_id,
+				QCA808X_PHY_INTR_MASK, 0);
+	}
+
+	return err;
+}
+
+static int qca808x_ack_interrupt(struct phy_device *phydev)
+{
+	int err;
+	a_uint32_t dev_id = 0, phy_id = 0;
+	qca808x_priv *priv = phydev->priv;
+	const struct qca808x_phy_info *pdata = priv->phy_info;
+
+	if (!pdata) {
+		return SW_FAIL;
+	}
+
+	dev_id = pdata->dev_id;
+	phy_id = pdata->phy_addr;
+
+	err = qca808x_phy_reg_read(dev_id, phy_id,
+			QCA808X_PHY_INTR_STATUS);
+
+	return (err < 0) ? err : 0;
+}
+
+/* switch linux negtiation capability to fal avariable */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+static a_uint32_t qca808x_negtiation_cap_get(struct phy_device *phydev)
+{
+	a_uint32_t autoneg = 0;
+	a_uint32_t advertise = phydev->advertising & phydev->supported;
+
+	if (advertise & ADVERTISED_Pause) {
+		autoneg |= FAL_PHY_ADV_PAUSE;
+	}
+	if (advertise & ADVERTISED_Asym_Pause) {
+		autoneg |= FAL_PHY_ADV_ASY_PAUSE;
+	}
+	if (advertise & ADVERTISED_10baseT_Half) {
+		autoneg |= FAL_PHY_ADV_10T_HD;
+	}
+	if (advertise & ADVERTISED_10baseT_Full) {
+		autoneg |= FAL_PHY_ADV_10T_FD;
+	}
+	if (advertise & ADVERTISED_100baseT_Half) {
+		autoneg |= FAL_PHY_ADV_100TX_HD;
+	}
+	if (advertise & ADVERTISED_100baseT_Full) {
+		autoneg |= FAL_PHY_ADV_100TX_FD;
+	}
+	if (advertise & ADVERTISED_1000baseT_Full) {
+		autoneg |= FAL_PHY_ADV_1000T_FD;
+	}
+#if 0
+	if (advertise & ADVERTISED_2500baseX_Full) {
+		autoneg |= FAL_PHY_ADV_2500T_FD;
+	}
+#endif
+
+	return autoneg;
+}
+#else
+static a_uint32_t qca808x_negtiation_cap_get(struct phy_device *phydev)
+{
+	a_uint32_t autoneg = 0;
+	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising) = { 0, };
+
+	linkmode_and(advertising, phydev->advertising, phydev->supported);
+
+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertising)) {
+		autoneg |= FAL_PHY_ADV_PAUSE;
+	}
+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertising)) {
+		autoneg |= FAL_PHY_ADV_ASY_PAUSE;
+	}
+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, advertising)) {
+		autoneg |= FAL_PHY_ADV_10T_HD;
+	}
+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, advertising)) {
+		autoneg |= FAL_PHY_ADV_10T_FD;
+	}
+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, advertising)) {
+		autoneg |= FAL_PHY_ADV_100TX_HD;
+	}
+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, advertising)) {
+		autoneg |= FAL_PHY_ADV_100TX_FD;
+	}
+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, advertising)) {
+		autoneg |= FAL_PHY_ADV_1000T_FD;
+	}
+#if 0
+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, advertising)) {
+		autoneg |= FAL_PHY_ADV_2500T_FD;
+	}
+#endif
+
+	return autoneg;
+}
+#endif
+
+static int qca808x_config_aneg(struct phy_device *phydev)
+{
+	a_uint32_t advertise = 0;
+	a_uint16_t phy_data = 0;
+	int err = 0;
+	a_uint32_t dev_id = 0, phy_id = 0;
+	qca808x_priv *priv = phydev->priv;
+	const struct qca808x_phy_info *pdata = priv->phy_info;
+
+	if(!qca808x_sfp_present(phydev))
+	{
+		return 0;
+	}
+
+	if (!pdata) {
+		return SW_FAIL;
+	}
+
+	dev_id = pdata->dev_id;
+	phy_id = pdata->phy_addr;
+	if (phydev->autoneg != AUTONEG_ENABLE)
+	{
+		/* force speed */
+		phydev->pause = 0;
+		phydev->asym_pause = 0;
+
+		phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL);
+		phy_data &= ~QCA808X_CTRL_AUTONEGOTIATION_ENABLE;
+		if (phydev->duplex == FAL_FULL_DUPLEX) {
+			phy_data |= QCA808X_CTRL_FULL_DUPLEX;
+		} else {
+			phy_data &= ~QCA808X_CTRL_FULL_DUPLEX;
+		}
+		qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL, phy_data);
+		err = qca808x_phy_set_force_speed(dev_id, phy_id, phydev->speed);
+	} else {
+		/* autoneg enabled */
+		advertise = qca808x_negtiation_cap_get(phydev);
+		/*link would be down if there is no speed adv except for pause*/
+		if(!(advertise & ~(FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE))) {
+			return SW_BAD_VALUE;
+		}
+		err |= qca808x_phy_set_autoneg_adv(dev_id, phy_id, advertise);
+		err |= qca808x_phy_restart_autoneg(dev_id, phy_id);
+	}
+
+	return err;
+}
+
+static int qca808x_aneg_done(struct phy_device *phydev)
+{
+
+	a_uint16_t phy_data;
+	a_uint32_t dev_id = 0, phy_id = 0;
+	qca808x_priv *priv = phydev->priv;
+	const struct qca808x_phy_info *pdata = priv->phy_info;
+
+	if (!pdata) {
+		return SW_FAIL;
+	}
+
+	dev_id = pdata->dev_id;
+	phy_id = pdata->phy_addr;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id,
+			QCA808X_PHY_STATUS);
+
+	return (phy_data < 0) ? phy_data : (phy_data & QCA808X_STATUS_AUTO_NEG_DONE);
+}
+
+static int qca808x_read_status(struct phy_device *phydev)
+{
+	struct port_phy_status phy_status = {0};
+	a_uint32_t dev_id = 0, phy_id = 0;
+	qca808x_priv *priv = phydev->priv;
+	const struct qca808x_phy_info *pdata = priv->phy_info;
+
+	if(!qca808x_config_init_done)
+	{
+		if(!_qca808x_config_init(phydev))
+		{
+			qca808x_config_init_done = A_TRUE;
+		}
+	}
+
+	if (!pdata) {
+		return SW_FAIL;
+	}
+
+	dev_id = pdata->dev_id;
+	phy_id = pdata->phy_addr;
+
+	qca808x_phy_get_status(dev_id, phy_id, &phy_status);
+
+	if (phy_status.link_status) {
+		phydev->link = QCA808X_PHY_LINK_UP;
+	} else {
+		phydev->link = QCA808X_PHY_LINK_DOWN;
+	}
+
+	switch (phy_status.speed) {
+		case FAL_SPEED_2500:
+			phydev->speed = SPEED_2500;
+			break;
+		case FAL_SPEED_1000:
+			phydev->speed = SPEED_1000;
+			break;
+		case FAL_SPEED_100:
+			phydev->speed = SPEED_100;
+			break;
+		default:
+			phydev->speed = SPEED_10;
+			break;
+	}
+
+	if (phy_status.duplex == FAL_FULL_DUPLEX) {
+		phydev->duplex = DUPLEX_FULL;
+	} else {
+		phydev->duplex = DUPLEX_HALF;
+	}
+
+	return 0;
+}
+
+static int qca808x_suspend(struct phy_device *phydev)
+{
+	a_uint32_t dev_id = 0, phy_id = 0;
+	qca808x_priv *priv = phydev->priv;
+	const struct qca808x_phy_info *pdata = priv->phy_info;
+
+	if (!pdata) {
+		return SW_FAIL;
+	}
+
+	dev_id = pdata->dev_id;
+	phy_id = pdata->phy_addr;
+
+	return qca808x_phy_poweroff(dev_id, phy_id);
+}
+
+static int qca808x_resume(struct phy_device *phydev)
+{
+	a_uint32_t dev_id = 0, phy_id = 0;
+	qca808x_priv *priv = phydev->priv;
+	const struct qca808x_phy_info *pdata = priv->phy_info;
+
+	if (!pdata) {
+		return SW_FAIL;
+	}
+
+	dev_id = pdata->dev_id;
+	phy_id = pdata->phy_addr;
+
+	return qca808x_phy_poweron(dev_id, phy_id);
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+static int qca808x_soft_reset(struct phy_device *phydev)
+{
+	a_uint32_t dev_id = 0, phy_id = 0;
+	qca808x_priv *priv = phydev->priv;
+	const struct qca808x_phy_info *pdata = priv->phy_info;
+
+	if(!qca808x_sfp_present(phydev)) {
+		return 0;
+	}
+
+	if (!pdata) {
+		return SW_FAIL;
+	}
+
+	dev_id = pdata->dev_id;
+	phy_id = pdata->phy_addr;
+
+	return qca808x_phy_reset(dev_id, phy_id);
+}
+
+static void qca808x_link_change_notify(struct phy_device *phydev)
+{
+#if defined(IN_LINUX_STD_PTP)
+	qca808x_ptp_change_notify(phydev);
+#endif
+}
+#endif
+
+static int qca808x_phy_probe(struct phy_device *phydev)
+{
+	qca808x_priv *priv;
+	int err = 0;
+
+	priv = kzalloc(sizeof(qca808x_priv), GFP_KERNEL);
+	if (!priv) {
+		return -ENOMEM;
+	}
+
+	priv->phydev = phydev;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0))
+	priv->phy_info = qca808x_phy_info_get(phydev->addr);
+#else
+	priv->phy_info = qca808x_phy_info_get(phydev->mdio.addr);
+#endif
+	phydev->priv = priv;
+
+#if defined(IN_LINUX_STD_PTP)
+	err = qca808x_ptp_init(priv);
+#endif
+
+	return err;
+}
+
+static void qca808x_phy_remove(struct phy_device *phydev)
+{
+	qca808x_priv *priv = phydev->priv;
+
+#if defined(IN_LINUX_STD_PTP)
+	qca808x_ptp_deinit(priv);
+#endif
+	kfree(priv);
+}
+
+struct phy_driver qca808x_phy_driver = {
+	.phy_id		= QCA8081_PHY_V1_1,
+	.phy_id_mask    = 0xffffffff,
+	.name		= "QCA808X ethernet",
+	.features	= PHY_GBIT_FEATURES,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+	.flags		= PHY_HAS_INTERRUPT,
+#endif
+	.probe		= qca808x_phy_probe,
+	.remove		= qca808x_phy_remove,
+	.config_init	= qca808x_config_init,
+	.config_intr	= qca808x_config_intr,
+	.config_aneg	= qca808x_config_aneg,
+	.aneg_done	= qca808x_aneg_done,
+	.ack_interrupt	= qca808x_ack_interrupt,
+	.read_status	= qca808x_read_status,
+	.suspend	= qca808x_suspend,
+	.resume		= qca808x_resume,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	.soft_reset	= qca808x_soft_reset,
+	.link_change_notify     = qca808x_link_change_notify,
+#endif
+#if defined(IN_LINUX_STD_PTP)
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	.ts_info	= qca808x_ts_info,
+#endif
+	.hwtstamp	= qca808x_hwtstamp,
+	.rxtstamp	= qca808x_rxtstamp,
+	.txtstamp	= qca808x_txtstamp,
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+	.mdiodrv.driver		= { .owner = THIS_MODULE },
+#else
+	.driver		= { .owner = THIS_MODULE },
+#endif
+};
+
+a_int32_t qca808x_phy_driver_register(void)
+{
+	a_int32_t ret;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+	ret = phy_driver_register(&qca808x_phy_driver, THIS_MODULE);
+#else
+	ret = phy_driver_register(&qca808x_phy_driver);
+#endif
+	return ret;
+}
+
+void qca808x_phy_driver_unregister(void)
+{
+	phy_driver_unregister(&qca808x_phy_driver);
+}
+
+void qca808x_phydev_init(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	struct qca808x_phy_info *pdata;
+	pdata = kzalloc(sizeof(struct qca808x_phy_info), GFP_KERNEL);
+
+	if (!pdata) {
+		return;
+	}
+	list_add_tail(&pdata->list, &g_qca808x_phy_list);
+	pdata->dev_id = dev_id;
+	/* the phy address may be the i2c slave addr or mdio addr */
+	pdata->phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id);
+	pdata->phydev_addr = pdata->phy_addr;
+#if defined(IN_PHY_I2C_MODE)
+	/* in i2c mode, need to register a fake phy device
+	 * before the phy driver register */
+	if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS) {
+		a_uint32_t phy_id = QCA8081_PHY_V1_1;
+		qca808x_phy_get_phy_id(dev_id, pdata->phy_addr, &phy_id);
+		if(phy_id != QCA8081_PHY_V1_1 && phy_id != INVALID_PHY_ID) {
+			SSDK_ERROR("phy id 0x%x is not supported\n", phy_id);
+			return;
+		}
+		pdata->phydev_addr = qca_ssdk_port_to_phy_mdio_fake_addr(dev_id, port_id);
+		sfp_phy_device_setup(dev_id, port_id, phy_id);
+	}
+#endif
+}
+
+void qca808x_phydev_deinit(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	struct qca808x_phy_info *pdata, *pnext;
+
+#if defined(IN_PHY_I2C_MODE)
+	/* in i2c mode, need to remove the fake phy device
+	 * after the phy driver unregistered */
+	if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS) {
+		sfp_phy_device_remove(dev_id, port_id);
+	}
+#endif
+	list_for_each_entry_safe(pdata, pnext, &g_qca808x_phy_list, list) {
+		list_del(&pdata->list);
+		kfree(pdata);
+	}
+}
diff --git a/qca-ssdk/src/hsl/phy/qca808x_led.c b/qca-ssdk/src/hsl/phy/qca808x_led.c
new file mode 100644
index 0000000..7abca48
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/qca808x_led.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "hsl_phy.h"
+#include "ssdk_plat.h"
+#include "qca808x_phy.h"
+#include "qca808x_led.h"
+
+static sw_error_t
+_qca808x_phy_led_active_set(a_uint32_t dev_id, a_uint32_t phy_id,
+	led_ctrl_pattern_t *pattern)
+{
+	sw_error_t rv = SW_OK;
+	a_uint16_t phy_data = 0;
+
+	phy_data= qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+			QCA808X_PHY_MMD7_LED_POLARITY_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+	if(pattern->map & BIT(LED_ACTIVE_HIGH))
+	{
+		phy_data |= QCA808X_PHY_MMD7_LED_POLARITY_MASK;
+	}
+	else
+	{
+		phy_data &= ~QCA808X_PHY_MMD7_LED_POLARITY_MASK;
+	}
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+		QCA808X_PHY_MMD7_LED_POLARITY_CTRL, phy_data);
+
+	return rv;
+}
+
+static sw_error_t
+_qca808x_phy_led_active_get(a_uint32_t dev_id, a_uint32_t phy_id,
+	led_ctrl_pattern_t *pattern)
+{
+	a_uint16_t phy_data = 0;
+
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+		QCA808X_PHY_MMD7_LED_POLARITY_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+	if(phy_data & QCA808X_PHY_MMD7_LED_POLARITY_MASK)
+	{
+		pattern->map |= BIT(LED_ACTIVE_HIGH);
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+_qca808x_phy_led_pattern_map_from_phy(a_uint32_t dev_id, a_uint32_t phy_id,
+	led_ctrl_pattern_t *pattern, a_uint16_t *phy_data)
+{
+	if (qca808x_phy_2500caps(dev_id, phy_id) == A_TRUE)
+	{
+		if(*phy_data & QCA808X_PHY_LINK_2500M_LIGHT_EN)
+		{
+			pattern->map |= BIT(LINK_2500M_LIGHT_EN);
+		}
+	}
+	if(*phy_data & QCA808X_PHY_LINK_1000M_LIGHT_EN)
+	{
+		pattern->map |= BIT(LINK_1000M_LIGHT_EN);
+	}
+	if(*phy_data & QCA808X_PHY_LINK_100M_LIGHT_EN)
+	{
+		pattern->map |= BIT(LINK_100M_LIGHT_EN);
+	}
+	if(*phy_data & QCA808X_PHY_LINK_10M_LIGHT_EN)
+	{
+		pattern->map |= BIT(LINK_10M_LIGHT_EN);
+	}
+	if (*phy_data & QCA808X_PHY_RX_TRAFFIC_BLINK_EN)
+	{
+		pattern->map |= BIT(RX_TRAFFIC_BLINK_EN);
+	}
+	if (*phy_data & QCA808X_PHY_TX_TRAFFIC_BLINK_EN)
+	{
+		pattern->map |= BIT(TX_TRAFFIC_BLINK_EN);
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+_qca808x_phy_led_pattern_map_to_phy(a_uint32_t dev_id, a_uint32_t phy_id,
+	led_ctrl_pattern_t *pattern, a_uint32_t *led_map)
+{
+	if (qca808x_phy_2500caps(dev_id, phy_id) == A_TRUE)
+	{
+		if (pattern->map & BIT(LINK_2500M_LIGHT_EN))
+		{
+			*led_map |=  QCA808X_PHY_LINK_2500M_LIGHT_EN;
+		}
+	}
+	if (pattern->map & BIT(LINK_1000M_LIGHT_EN))
+	{
+		*led_map |=  QCA808X_PHY_LINK_1000M_LIGHT_EN;
+	}
+	if (pattern->map & BIT(LINK_100M_LIGHT_EN))
+	{
+		*led_map |=  QCA808X_PHY_LINK_100M_LIGHT_EN;
+	}
+	if (pattern->map & BIT(LINK_10M_LIGHT_EN))
+	{
+		*led_map |=  QCA808X_PHY_LINK_10M_LIGHT_EN;
+	}
+	if (pattern->map & BIT(RX_TRAFFIC_BLINK_EN))
+	{
+		*led_map |=  QCA808X_PHY_RX_TRAFFIC_BLINK_EN;
+	}
+	if (pattern->map & BIT(TX_TRAFFIC_BLINK_EN))
+	{
+		*led_map |=  QCA808X_PHY_TX_TRAFFIC_BLINK_EN;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_led_ctrl_pattern_set
+*
+*/
+sw_error_t
+qca808x_phy_led_ctrl_pattern_set(a_uint32_t dev_id, a_uint32_t phy_id,
+	led_ctrl_pattern_t *pattern)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t source_id = 0;
+
+	if(LED_PATTERN_MAP_EN != pattern->mode)
+	{
+		SSDK_ERROR("led mode %d is not supported\n", pattern->mode);
+		return SW_NOT_SUPPORTED;
+	}
+	for(source_id = QCA808X_PHY_LED_SOURCE0; source_id <= QCA808X_PHY_LED_SOURCE2;
+		source_id++)
+	{
+		/*three source use the same pattern*/
+		rv = qca808x_phy_led_ctrl_source_set (dev_id, phy_id, source_id, pattern);
+		SW_RTN_ON_ERROR(rv);
+	}
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_led_ctrl_pattern_get
+*
+*/
+sw_error_t
+qca808x_phy_led_ctrl_pattern_get(a_uint32_t dev_id, a_uint32_t phy_id,
+	led_ctrl_pattern_t *pattern)
+{
+	sw_error_t rv = SW_OK;
+
+	/*three source use the same pattern*/
+	rv = qca808x_phy_led_ctrl_source_get(dev_id, phy_id, QCA808X_PHY_LED_SOURCE0,
+		pattern);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_led_source_pattern_set
+*
+*/
+sw_error_t
+qca808x_phy_led_ctrl_source_set(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t source_id, led_ctrl_pattern_t *pattern)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t led_map = 0;
+	a_uint16_t led_mmd_addr = 0;
+
+	if(LED_PATTERN_MAP_EN != pattern->mode)
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	rv = _qca808x_phy_led_active_set(dev_id,  phy_id, pattern);
+	SW_RTN_ON_ERROR(rv);
+	rv = _qca808x_phy_led_pattern_map_to_phy(dev_id, phy_id, pattern, &led_map);
+	SW_RTN_ON_ERROR(rv);
+	switch(source_id)
+	{
+		case QCA808X_PHY_LED_SOURCE0:
+			led_mmd_addr = QCA808X_PHY_MMD7_LED0_CTRL;
+			break;
+		case QCA808X_PHY_LED_SOURCE1:
+			led_mmd_addr = QCA808X_PHY_MMD7_LED1_CTRL;
+			break;
+		case QCA808X_PHY_LED_SOURCE2:
+			led_mmd_addr = QCA808X_PHY_MMD7_LED2_CTRL;
+			break;
+		default:
+			SSDK_ERROR("source %d is not support\n", source_id);
+			break;
+	}
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+		led_mmd_addr, led_map);
+
+	return rv;
+}
+/******************************************************************************
+*
+* qca808x_phy_led_source_pattern_get
+*
+*/
+sw_error_t
+qca808x_phy_led_ctrl_source_get(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t source_id, led_ctrl_pattern_t *pattern)
+{
+	sw_error_t rv = SW_OK;
+	a_uint16_t phy_data = 0, led_mmd_addr = 0;
+
+	pattern->map = 0;
+	pattern->mode = LED_PATTERN_MAP_EN;
+	rv = _qca808x_phy_led_active_get(dev_id, phy_id, pattern);
+	SW_RTN_ON_ERROR(rv);
+	switch(source_id)
+	{
+		case QCA808X_PHY_LED_SOURCE0:
+			led_mmd_addr = QCA808X_PHY_MMD7_LED0_CTRL;
+			break;
+		case QCA808X_PHY_LED_SOURCE1:
+			led_mmd_addr = QCA808X_PHY_MMD7_LED1_CTRL;
+			break;
+		case QCA808X_PHY_LED_SOURCE2:
+			led_mmd_addr = QCA808X_PHY_MMD7_LED2_CTRL;
+			break;
+		default:
+			SSDK_ERROR("source %d is not support\n", source_id);
+			break;
+	}
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+		led_mmd_addr);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+	rv = _qca808x_phy_led_pattern_map_from_phy(dev_id, phy_id, pattern,
+		&phy_data);
+
+	return rv;
+}
+
+void qca808x_phy_led_api_ops_init(hsl_phy_ops_t *qca808x_phy_led_api_ops)
+{
+	if (!qca808x_phy_led_api_ops) {
+		return;
+	}
+	qca808x_phy_led_api_ops->phy_led_ctrl_pattern_get = qca808x_phy_led_ctrl_pattern_get;
+	qca808x_phy_led_api_ops->phy_led_ctrl_pattern_set = qca808x_phy_led_ctrl_pattern_set;
+	qca808x_phy_led_api_ops->phy_led_ctrl_source_set = qca808x_phy_led_ctrl_source_set;
+
+	return;
+}
diff --git a/qca-ssdk/src/hsl/phy/qca808x_phc.c b/qca-ssdk/src/hsl/phy/qca808x_phc.c
new file mode 100755
index 0000000..648ffaa
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/qca808x_phc.c
@@ -0,0 +1,1472 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/if_vlan.h>
+#include <linux/net_tstamp.h>
+#include <linux/ptp_classify.h>
+
+#include "qca808x.h"
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+#include <linux/time64.h>
+#else
+#include <linux/time.h>
+#define ns_to_timespec64 ns_to_timespec
+#define timespec64_to_ns timespec_to_ns
+#define timespec64 timespec
+#endif
+
+#include "qca808x_ptp.h"
+#include "qca808x_ptp_reg.h"
+#include "qca808x_ptp_api.h"
+
+#define QCA808X_PTP_EMBEDDED_MODE    0xa
+
+#define QCA808X_PTP_INCVAL_SYNC_MODE 0x8
+#define QCA808X_PTP_TICK_RATE_125M   8
+#define QCA808X_PTP_TICK_RATE_200M   5
+
+#define PTP_HDR_RESERVED0_OFFSET	1
+#define PTP_HDR_RESERVED1_OFFSET	5
+#define PTP_HDR_CORRECTIONFIELD_OFFSET	8
+#define PTP_HDR_RESERVED2_OFFSET	16
+
+#define SKB_TIMESTAMP_TIMEOUT        1 /* jiffies */
+#define GPS_WORK_TIMEOUT             HZ
+
+#define HWTSTAMP_TX_ONESTEP_P2P     (HWTSTAMP_TX_ONESTEP_SYNC + 1)
+
+extern struct list_head g_qca808x_phy_list;
+void qca808x_ptp_gm_gps_seconds_sync_enable(a_uint32_t dev_id,
+		a_uint32_t phy_addr, a_bool_t en)
+{
+	struct qca808x_phy_info *pdata;
+#if defined(IN_PHY_I2C_MODE)
+	a_uint32_t port_id;
+	port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_addr);
+	if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS) {
+		phy_addr = qca_ssdk_port_to_phy_mdio_fake_addr(dev_id, port_id);
+	}
+#endif
+
+	pdata = qca808x_phy_info_get(phy_addr);
+	if (pdata) {
+		pdata->gps_seconds_sync_en = en;
+	}
+
+	if (en == A_TRUE) {
+		schedule_delayed_work(&pdata->ts_schedule_work, GPS_WORK_TIMEOUT);
+	}
+
+	return;
+}
+
+a_bool_t qca808x_ptp_gm_gps_seconds_sync_status_get(a_uint32_t dev_id,
+		a_uint32_t phy_addr)
+{
+	struct qca808x_phy_info *pdata;
+#if defined(IN_PHY_I2C_MODE)
+	a_uint32_t port_id;
+	port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_addr);
+	if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS) {
+		phy_addr = qca_ssdk_port_to_phy_mdio_fake_addr(dev_id, port_id);
+	}
+#endif
+
+	pdata = qca808x_phy_info_get(phy_addr);
+	if (pdata) {
+		return pdata->gps_seconds_sync_en;
+	}
+
+	return A_FALSE;
+}
+
+void qca808x_ptp_clock_mode_config(a_uint32_t dev_id,
+		a_uint32_t phy_addr, a_uint16_t clock_mode, a_uint16_t step_mode)
+{
+	struct qca808x_phy_info *pdata;
+#if defined(IN_PHY_I2C_MODE)
+	a_uint32_t port_id;
+	port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_addr);
+	if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS) {
+		phy_addr = qca_ssdk_port_to_phy_mdio_fake_addr(dev_id, port_id);
+	}
+#endif
+
+	pdata = qca808x_phy_info_get(phy_addr);
+
+	if (pdata) {
+		pdata->clock_mode = clock_mode;
+		pdata->step_mode = step_mode;
+	}
+
+	return;
+}
+
+void qca808x_ptp_stat_update(struct qca808x_phy_info *pdata, fal_ptp_direction_t direction,
+		a_int32_t msg_type, a_int32_t seqid_matched)
+{
+	ptp_packet_stat *pkt_stat = NULL;
+
+	if (((direction != FAL_RX_DIRECTION) && (direction != FAL_TX_DIRECTION)) ||
+			(seqid_matched < PTP_PKT_SEQID_UNMATCHED) ||
+			(seqid_matched >= PTP_PKT_SEQID_MATCH_MAX)) {
+		return;
+	}
+
+	pkt_stat = &pdata->pkt_stat[direction];
+	switch (msg_type) {
+		case QCA808X_PTP_MSG_SYNC:
+			pkt_stat->sync_cnt[seqid_matched]++;
+			break;
+		case QCA808X_PTP_MSG_DREQ:
+			pkt_stat->delay_req_cnt[seqid_matched]++;
+			break;
+		case QCA808X_PTP_MSG_PREQ:
+			pkt_stat->pdelay_req_cnt[seqid_matched]++;
+			break;
+		case QCA808X_PTP_MSG_PRESP:
+			pkt_stat->pdelay_resp_cnt[seqid_matched]++;
+			break;
+		case QCA808X_PTP_MSG_MAX:
+			pkt_stat->event_pkt_cnt++;
+			break;
+		default:
+			SSDK_DEBUG("%s: msg %x is not event frame\n",
+					__func__, msg_type);
+	}
+}
+
+void qca808x_ptp_stat_get(void)
+{
+	int i = 0;
+	struct qca808x_phy_info *pdata = NULL;
+	ptp_packet_stat *pkt_stat;
+
+	list_for_each_entry(pdata, &g_qca808x_phy_list, list) {
+		pkt_stat = pdata->pkt_stat;
+		SSDK_INFO("PHY [%#x] PTP event packet statistics:\n", pdata->phy_addr);
+		for (i=0; i <= FAL_TX_DIRECTION; i++)
+		{
+			if (i == FAL_TX_DIRECTION) {
+				SSDK_INFO("----------TX direction----------\n");
+			} else {
+				SSDK_INFO("----------RX direction----------\n");
+			}
+
+			SSDK_INFO("even sum:    %lld\n",
+					pkt_stat[i].event_pkt_cnt);
+			SSDK_INFO("seq id matched stat:\n");
+			SSDK_INFO("sync:        %lld\n",
+					pkt_stat[i].sync_cnt[PTP_PKT_SEQID_MATCHED]);
+			SSDK_INFO("delay_req:   %lld\n",
+					pkt_stat[i].delay_req_cnt[PTP_PKT_SEQID_MATCHED]);
+			SSDK_INFO("pdelay_req:  %lld\n",
+					pkt_stat[i].pdelay_req_cnt[PTP_PKT_SEQID_MATCHED]);
+			SSDK_INFO("pdelay_resp: %lld\n\n",
+					pkt_stat[i].pdelay_resp_cnt[PTP_PKT_SEQID_MATCHED]);
+
+			SSDK_INFO("seq id unmatched stat:\n");
+			SSDK_INFO("sync:        %lld\n",
+					pkt_stat[i].sync_cnt[PTP_PKT_SEQID_UNMATCHED]);
+			SSDK_INFO("delay_req:   %lld\n",
+					pkt_stat[i].delay_req_cnt[PTP_PKT_SEQID_UNMATCHED]);
+			SSDK_INFO("pdelay_req:  %lld\n",
+					pkt_stat[i].pdelay_req_cnt[PTP_PKT_SEQID_UNMATCHED]);
+			SSDK_INFO("pdelay_resp: %lld\n\n",
+					pkt_stat[i].pdelay_resp_cnt[PTP_PKT_SEQID_UNMATCHED]);
+		}
+	}
+}
+
+void qca808x_ptp_stat_set(void)
+{
+	struct qca808x_phy_info *pdata;
+
+	list_for_each_entry(pdata, &g_qca808x_phy_list, list) {
+		memset(pdata->pkt_stat, 0, sizeof(pdata->pkt_stat));
+	}
+}
+
+static sw_error_t qca808x_ptp_clock_synce_clock_enable(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data, phy_data1;
+	sw_error_t ret = SW_OK;
+
+	phy_data = qca808x_phy_debug_read(dev_id, phy_id,
+			QCA808X_DEBUG_ANA_CLOCK_CTRL_REG);
+
+	phy_data1 = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+			QCA808X_MMD7_CLOCK_CTRL_REG);
+
+	if (enable == A_TRUE) {
+		/* enable analog synce clock output */
+		phy_data |= QCA808X_ANALOG_PHY_SYNCE_CLOCK_EN;
+		/* enable digital synce clock output */
+		phy_data1 |= QCA808X_DIGITAL_PHY_SYNCE_CLOCK_EN;
+	} else {
+		phy_data &= ~QCA808X_ANALOG_PHY_SYNCE_CLOCK_EN;
+		phy_data1 &= ~QCA808X_DIGITAL_PHY_SYNCE_CLOCK_EN;
+	}
+
+	ret = qca808x_phy_debug_write(dev_id, phy_id,
+			QCA808X_DEBUG_ANA_CLOCK_CTRL_REG, phy_data);
+
+	ret |= qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+			QCA808X_MMD7_CLOCK_CTRL_REG, phy_data1);
+	return ret;
+}
+
+static sw_error_t qca808x_ptp_clock_incval_mode_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	sw_error_t ret = SW_OK;
+
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+			PTP_RTC_EXT_CONF_REG_ADDRESS);
+
+	if (enable == A_TRUE) {
+		phy_data |= QCA808X_PTP_INCVAL_SYNC_MODE;
+	} else {
+		phy_data &= ~QCA808X_PTP_INCVAL_SYNC_MODE;
+	}
+
+	ret = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+			PTP_RTC_EXT_CONF_REG_ADDRESS, phy_data);
+
+	return ret;
+}
+
+sw_error_t qca808x_ptp_config_init(struct phy_device *phydev)
+{
+	fal_ptp_config_t ptp_config;
+	fal_ptp_reference_clock_t ptp_ref_clock;
+	fal_ptp_rx_timestamp_mode_t rx_ts_mode;
+	fal_ptp_time_t ptp_time = {0};
+	sw_error_t ret = SW_OK;
+	a_uint32_t dev_id = 0, phy_id = 0;
+	qca808x_priv *priv = phydev->priv;
+	const struct qca808x_phy_info *pdata = priv->phy_info;
+	struct qca808x_ptp_info *ptp_info = &priv->ptp_info;
+
+	if (!pdata) {
+		return SW_FAIL;
+	}
+
+	dev_id = pdata->dev_id;
+	phy_id = pdata->phy_addr;
+
+	/* disable ptp function by default */
+	ptp_info->hwts_tx_type = HWTSTAMP_TX_OFF;
+	ptp_info->hwts_rx_type = PTP_CLASS_NONE;
+
+	ptp_config.ptp_en = A_FALSE;
+	ptp_config.clock_mode = FAL_OC_CLOCK_MODE;
+	ptp_config.step_mode = FAL_TWO_STEP_MODE;
+	ret = qca808x_phy_ptp_config_set(dev_id, phy_id, &ptp_config);
+
+	qca808x_ptp_clock_mode_config(dev_id, phy_id, ptp_config.clock_mode,
+			ptp_config.step_mode);
+
+	/* set rtc clock to asynchronization mode*/
+	ret |= qca808x_ptp_clock_incval_mode_set(dev_id, phy_id, A_FALSE);
+
+	/* adjust frequency to 8ns(125MHz) */
+	ptp_time.nanoseconds = QCA808X_PTP_TICK_RATE_125M;
+	ret |= qca808x_phy_ptp_rtc_adjfreq_set(dev_id, phy_id, &ptp_time);
+
+	/* use SyncE reference clock */
+	ptp_ref_clock = FAL_REF_CLOCK_SYNCE;
+	ret |= qca808x_phy_ptp_reference_clock_set(dev_id, phy_id, ptp_ref_clock);
+
+	/* use Embed mode to get RX timestamp */
+	rx_ts_mode = FAL_RX_TS_EMBED;
+	ret |= qca808x_phy_ptp_rx_timestamp_mode_set(dev_id, phy_id, rx_ts_mode);
+
+	/* disable SYNCE clock output */
+	ret |= qca808x_ptp_clock_synce_clock_enable(dev_id, phy_id, A_FALSE);
+
+	if (ret != SW_OK) {
+		SSDK_ERROR("%s failed\n", __func__);
+	}
+
+	return ret;
+}
+
+static a_uint8_t* skb_ptp_header(struct sk_buff *skb, int type)
+{
+	a_uint8_t *data = skb_mac_header(skb);
+	a_uint32_t offset = 0;
+
+	if (type & PTP_CLASS_VLAN) {
+		offset += VLAN_HLEN;
+	}
+
+	switch (type & PTP_CLASS_PMASK) {
+		case PTP_CLASS_IPV4:
+			offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
+			break;
+		case PTP_CLASS_IPV6:
+			offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
+			break;
+		case PTP_CLASS_L2:
+			offset += ETH_HLEN;
+			break;
+		default:
+			return NULL;
+	}
+
+	if (skb->len + ETH_HLEN < offset +
+			OFF_PTP_SEQUENCE_ID + sizeof(a_uint16_t)) {
+		return NULL;
+	}
+
+	return data + offset;
+}
+
+void qca808x_pkt_info_get(struct sk_buff *skb,
+		unsigned int type, fal_ptp_pkt_info_t *pkt_info)
+{
+	a_uint16_t *seqid, seqid_pkt;
+	a_uint32_t *clockid;
+	a_uint32_t clockid_lo;
+	a_uint64_t clockid_pkt;
+	a_uint16_t *portid, portid_pkt;
+	a_uint8_t msgtype_pkt;
+	a_uint8_t *ptp_header = NULL;
+
+	ptp_header = skb_ptp_header(skb, type);
+	if (!ptp_header) {
+		return;
+	}
+
+#define OFF_PTP_CLOCK_ID 20
+#define OFF_PTP_PORT_ID 28
+
+	seqid = (a_uint16_t *)(ptp_header + OFF_PTP_SEQUENCE_ID);
+	seqid_pkt = ntohs(*seqid);
+	clockid  = (a_uint32_t *)(ptp_header + OFF_PTP_CLOCK_ID);
+	clockid_pkt = ntohl(*clockid);
+
+	clockid  = (a_uint32_t *)(ptp_header + OFF_PTP_CLOCK_ID + 4);
+	clockid_lo = ntohl(*clockid);
+	clockid_pkt =  (clockid_pkt << 32) | clockid_lo;
+	portid = (a_uint16_t *)(ptp_header + OFF_PTP_PORT_ID);
+	portid_pkt = ntohs(*portid);
+	msgtype_pkt = (*ptp_header) & 0xf;
+
+	pkt_info->sequence_id = seqid_pkt;
+	pkt_info->clock_identify = clockid_pkt;
+	pkt_info->port_number = portid_pkt;
+	pkt_info->msg_type = msgtype_pkt;
+	return ;
+}
+
+static void tx_timestamp_work(struct work_struct *work)
+{
+	struct sk_buff *skb;
+	struct skb_shared_hwtstamps shhwtstamps;
+	struct timespec64 ts;
+	a_uint64_t ns;
+	a_uint32_t dev_id, phy_id;
+	qca808x_ptp_cb *ptp_cb;
+	struct qca808x_phy_info *pdata;
+	fal_ptp_pkt_info_t pkt_info;
+	fal_ptp_time_t tx_time = {0};
+	sw_error_t ret = SW_OK;
+	a_uint16_t times = 0;
+	a_uint16_t seqid = 0;
+	struct qca808x_ptp_info *ptp_data =
+		container_of(work, struct qca808x_ptp_info, tx_ts_work.work);
+
+	qca808x_priv *priv =
+		container_of(ptp_data, qca808x_priv, ptp_info);
+
+	pdata = priv->phy_info;
+
+	if (!pdata) {
+		return;
+	}
+
+	dev_id = pdata->dev_id;
+	phy_id = pdata->phy_addr;
+
+	memset(&shhwtstamps, 0, sizeof(shhwtstamps));
+
+	while ((skb = skb_dequeue(&ptp_data->tx_queue))) {
+		ptp_cb = (qca808x_ptp_cb *)skb->cb;
+		qca808x_pkt_info_get(skb, ptp_cb->ptp_type, &pkt_info);
+
+		times = 0;
+		do {
+			/* poll the seqid of the transmitted ptp packet to
+			 * acquire the correspoding tx time stamp.
+			 */
+			seqid = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+					PTP_TX_SEQID_REG_ADDRESS);
+			udelay(1);
+			times++;
+		} while (seqid != pkt_info.sequence_id && times < 100);
+
+		ret = qca808x_phy_ptp_timestamp_get(dev_id, phy_id,
+				FAL_TX_DIRECTION, &pkt_info, &tx_time);
+
+		if (ret == SW_NOT_FOUND) {
+			qca808x_ptp_stat_update(pdata, FAL_TX_DIRECTION,
+					pkt_info.msg_type, PTP_PKT_SEQID_UNMATCHED);
+			SSDK_DEBUG("Fail to get tx_ts: sequence_id:%x, clock_identify:%llx,"
+					" port_number:%x, msg_type:%x\n",
+					pkt_info.sequence_id, pkt_info.clock_identify,
+					pkt_info.port_number, pkt_info.msg_type);
+		} else {
+			qca808x_ptp_stat_update(pdata, FAL_TX_DIRECTION,
+					pkt_info.msg_type, PTP_PKT_SEQID_MATCHED);
+		}
+		ts.tv_sec = tx_time.seconds;
+		ts.tv_nsec = tx_time.nanoseconds;
+
+		ns = timespec64_to_ns(&ts);
+
+		shhwtstamps.hwtstamp = ns_to_ktime(ns);
+		skb_complete_tx_timestamp(skb, &shhwtstamps);
+	}
+
+	if (!skb_queue_empty(&ptp_data->tx_queue))
+		schedule_delayed_work(&ptp_data->tx_ts_work, SKB_TIMESTAMP_TIMEOUT);
+}
+
+static void ptp_ingress_time_sync(a_uint32_t phy_addr, a_uint32_t ingress_time,
+		a_bool_t forward)
+{
+	fal_ptp_time_t ingress_trig_time = {0};
+	struct qca808x_phy_info *pdata = NULL;
+
+	ingress_trig_time.nanoseconds = ingress_time;
+
+	if (forward == A_FALSE) {
+		list_for_each_entry(pdata, &g_qca808x_phy_list, list) {
+			if (pdata->phydev_addr == phy_addr) {
+				qca808x_phy_ptp_pkt_timestamp_set(pdata->dev_id,
+						pdata->phy_addr, &ingress_trig_time);
+				break;
+			}
+		}
+	} else {
+		list_for_each_entry(pdata, &g_qca808x_phy_list, list) {
+			if (pdata->phydev_addr != phy_addr) {
+				qca808x_phy_ptp_pkt_timestamp_set(pdata->dev_id,
+						pdata->phy_addr, &ingress_trig_time);
+			}
+		}
+	}
+}
+
+static void rx_timestamp_work(struct work_struct *work)
+{
+	struct sk_buff *skb;
+	struct skb_shared_hwtstamps *shhwtstamps = NULL;
+	struct timespec64 ts;
+	a_uint64_t ns;
+	a_uint32_t dev_id, phy_id;
+	qca808x_ptp_cb *ptp_cb;
+	struct qca808x_phy_info *pdata;
+	fal_ptp_pkt_info_t pkt_info;
+	fal_ptp_time_t rx_time = {0};
+	sw_error_t ret = SW_OK;
+
+	struct qca808x_ptp_info *ptp_data =
+		container_of(work, struct qca808x_ptp_info, rx_ts_work.work);
+
+	qca808x_priv *priv =
+		container_of(ptp_data, qca808x_priv, ptp_info);
+
+	pdata = priv->phy_info;
+
+	if (!pdata) {
+		return;
+	}
+	dev_id = pdata->dev_id;
+	phy_id = pdata->phy_addr;
+
+	/* Deliver packets */
+	while ((skb = skb_dequeue(&ptp_data->rx_queue))) {
+		ptp_cb = (qca808x_ptp_cb *)skb->cb;
+		qca808x_pkt_info_get(skb, ptp_cb->ptp_type, &pkt_info);
+
+		ret = qca808x_phy_ptp_timestamp_get(dev_id, phy_id,
+				FAL_RX_DIRECTION, &pkt_info, &rx_time);
+		if (ret == SW_NOT_FOUND) {
+			qca808x_ptp_stat_update(pdata, FAL_RX_DIRECTION,
+					pkt_info.msg_type, PTP_PKT_SEQID_UNMATCHED);
+			SSDK_DEBUG("Fail to get rx_ts: sequence_id:%x, clock_identify:%llx, "
+					"port_number:%x, msg_type:%x\n",
+					pkt_info.sequence_id, pkt_info.clock_identify,
+					pkt_info.port_number, pkt_info.msg_type);
+		} else {
+			qca808x_ptp_stat_update(pdata, FAL_RX_DIRECTION,
+					pkt_info.msg_type, PTP_PKT_SEQID_MATCHED);
+		}
+
+		ts.tv_sec = rx_time.seconds;
+		ts.tv_nsec = rx_time.nanoseconds;
+		ns = timespec64_to_ns(&ts);
+		shhwtstamps = skb_hwtstamps(skb);
+		memset(shhwtstamps, 0, sizeof(*shhwtstamps));
+		shhwtstamps->hwtstamp = ns_to_ktime(ns);
+
+		/* OC/BC needs record ingress time stamp on receiving
+		 * peer delay request message under one-step mode.
+		 * TC one step mode should use the embeded mode for offloading
+		 * function.
+		 */
+		if (pdata->step_mode == FAL_ONE_STEP_MODE) {
+			switch (pdata->clock_mode) {
+				case FAL_OC_CLOCK_MODE:
+				case FAL_BC_CLOCK_MODE:
+					if (pkt_info.msg_type == QCA808X_PTP_MSG_PREQ) {
+						ptp_ingress_time_sync(phy_id,
+								ts.tv_nsec, A_FALSE);
+					}
+					break;
+				default:
+					break;
+			}
+		}
+		netif_rx_ni(skb);
+	}
+
+	if (!skb_queue_empty(&ptp_data->rx_queue))
+		schedule_delayed_work(&ptp_data->rx_ts_work, SKB_TIMESTAMP_TIMEOUT);
+}
+
+static void qca808x_gps_second_sync(struct qca808x_phy_info *pdata, a_int32_t *buf)
+{
+	fal_ptp_time_t time, old_time;
+	a_uint32_t dev_id, phy_id;
+
+	if (!pdata) {
+		return;
+	}
+	dev_id = pdata->dev_id;
+	phy_id = pdata->phy_addr;
+	/* 0-3: time of week; 4-5: week number; 6-7: UTC offset
+	 * Time(UTC) = Time(GPS) - UTC offset */
+#define WEEK_TIME  604800
+	time.seconds = ((a_int64_t)buf[0] << 24 | buf[1] << 16 | buf[2] << 8 | buf[3]) +
+		((buf[4] << 8 | buf[5]) * WEEK_TIME) - (buf[6] << 8 | buf[7]);
+
+	time.nanoseconds = 0;
+	time.fracnanoseconds = 0;
+
+	qca808x_phy_ptp_rtc_time_get(dev_id, phy_id, &old_time);
+	time.seconds -= old_time.seconds;
+	qca808x_phy_ptp_rtc_adjtime_set(dev_id, phy_id, &time);
+
+	qca808x_ptp_gm_gps_seconds_sync_enable(dev_id, phy_id, A_FALSE);
+	return;
+}
+
+static void gps_seconds_sync_thread(struct qca808x_phy_info *pdata)
+{
+	struct file *filp;
+	mm_segment_t fs;
+	a_uint32_t nread;
+	char buff[128];
+	char *dev ="/dev/ttyMSM0";
+	a_int32_t data[32];
+	a_uint32_t i = 0, j = 0;
+	a_bool_t is_time_pkt = A_FALSE;
+	a_int32_t try_cycle = 32;
+
+	filp = filp_open(dev, O_RDONLY, 0);
+	if (IS_ERR(filp))
+	{
+		SSDK_ERROR("Open %s error\n", dev);
+		return;
+	}
+
+	fs=get_fs();
+	set_fs(KERNEL_DS);
+	while(1)
+	{
+		memset(data, 0, sizeof(data));
+		memset(buff, 0, sizeof(buff));
+		is_time_pkt = A_FALSE;
+		filp->f_pos = 0;
+		nread = filp->f_op->read(filp, buff, sizeof(buff), &filp->f_pos);
+		if (nread > 0)
+		{
+	/* the packet format: <PKT_DLE><PKT_ID><DATA STRING><PKT_DLE><PKT_ETX> */
+#define PKT_DLE       0x10
+#define PKT_ETX       0x3
+#define PKT_PTIME_ID  0x8f
+#define PKT_PTIME_SID 0xab
+#define PKT_PTIME_LEN 0x10
+			buff[nread+1]='\0';
+			for(i = 0; i < nread; i++)
+			{
+				if (is_time_pkt == A_FALSE)
+				{
+					if (buff[i] == PKT_DLE && i+2 < nread &&
+							buff[i+1] == PKT_PTIME_ID &&
+							buff[i+2] == PKT_PTIME_SID) {
+						is_time_pkt = A_TRUE;
+						i = i + 2;
+						j = 0;
+					}
+				} else {
+					data[j++] = buff[i];
+					if (j >= PKT_PTIME_LEN && data[j-2] == PKT_DLE &&
+							data[j-1] == PKT_ETX)
+					{
+						qca808x_gps_second_sync(pdata, data);
+						goto gps_time_sync_exit;
+					}
+
+					if (j > PKT_PTIME_LEN+2) {
+						is_time_pkt = A_FALSE;
+					}
+				}
+			}
+		}
+
+		if (--try_cycle <= 0) {
+			break;
+		}
+	}
+
+gps_time_sync_exit:
+	set_fs(fs);
+	filp_close(filp, NULL);
+}
+
+static void qca808x_ptp_schedule_work(struct work_struct *work)
+{
+	struct qca808x_phy_info *pdata =
+		container_of(work, struct qca808x_phy_info, ts_schedule_work.work);
+
+	if (!pdata) {
+		return;
+	}
+	gps_seconds_sync_thread(pdata);
+
+	if (pdata->gps_seconds_sync_en == A_TRUE) {
+		schedule_delayed_work(&pdata->ts_schedule_work, GPS_WORK_TIMEOUT);
+	}
+}
+
+static void ingress_trig_time_work(struct work_struct *work)
+{
+	const struct qca808x_phy_info *pdata;
+	struct qca808x_ptp_info *ptp_data =
+		container_of(work, struct qca808x_ptp_info, ingress_trig_work.work);
+
+	qca808x_priv *priv =
+		container_of(ptp_data, qca808x_priv, ptp_info);
+
+	pdata = priv->phy_info;
+
+	if (!pdata) {
+		return;
+	}
+
+	switch (pdata->clock_mode) {
+		case FAL_P2PTC_CLOCK_MODE:
+			/* p2p tc one step just use ingress trig time for pdelay resp,
+			 * the ingress timestamp should be recorded in the local phy.
+			 */
+			ptp_ingress_time_sync(pdata->phy_addr, ptp_data->ingress_time, A_FALSE);
+			break;
+		case FAL_E2ETC_CLOCK_MODE:
+			ptp_ingress_time_sync(pdata->phy_addr, ptp_data->ingress_time, A_TRUE);
+			break;
+		case FAL_OC_CLOCK_MODE:
+		case FAL_BC_CLOCK_MODE:
+			ptp_ingress_time_sync(pdata->phy_addr, ptp_data->ingress_time, A_FALSE);
+			break;
+		default:
+			break;
+	}
+
+	return;
+}
+
+/******************************************************************************
+*
+* qca808x_ptp_settime - reset the rtc timecounter
+*
+* ptp: the ptp clock info structure
+* ts:  the new rtc timecounter
+*
+*/
+static int qca808x_ptp_settime(struct ptp_clock_info *ptp,
+			       const struct timespec64 *ts)
+{
+	const struct qca808x_phy_info *pdata;
+	struct qca808x_ptp_clock *clock =
+		container_of(ptp, struct qca808x_ptp_clock, caps);
+
+	fal_ptp_time_t ptp_time = {0};
+
+	qca808x_priv *priv = clock->priv;
+	pdata = priv->phy_info;
+
+	if (!pdata) {
+		return SW_FAIL;
+	}
+	ptp_time.seconds = ts->tv_sec;
+	ptp_time.nanoseconds = ts->tv_nsec;
+
+	mutex_lock(&clock->tsreg_lock);
+	qca808x_phy_ptp_rtc_time_set(pdata->dev_id, pdata->phy_addr, &ptp_time);
+	mutex_unlock(&clock->tsreg_lock);
+	return 0;
+}
+
+/******************************************************************************
+*
+* qca808x_ptp_gettime - read the rtc timecounter
+*
+* ptp: the ptp clock info structure
+* ts:  the timespace to hold the current rtc time
+*
+*/
+static int qca808x_ptp_gettime(struct ptp_clock_info *ptp,
+			       struct timespec64 *ts)
+{
+	const struct qca808x_phy_info *pdata;
+	struct qca808x_ptp_clock *clock =
+		container_of(ptp, struct qca808x_ptp_clock, caps);
+
+	fal_ptp_time_t ptp_time = {0};
+
+	qca808x_priv *priv = clock->priv;
+	pdata = priv->phy_info;
+
+	if (!pdata) {
+		return SW_FAIL;
+	}
+	mutex_lock(&clock->tsreg_lock);
+	qca808x_phy_ptp_rtc_time_get(pdata->dev_id, pdata->phy_addr, &ptp_time);
+	mutex_unlock(&clock->tsreg_lock);
+
+	ts->tv_sec = ptp_time.seconds;
+	ts->tv_nsec = ptp_time.nanoseconds;
+	return 0;
+}
+
+/******************************************************************************
+*
+* qca808x_ptp_adjtime - adjust the rtc timecounter offset
+*
+* ptp: the ptp clock info structure
+* delta:  offset to be adjusted per cycle counter
+*
+*/
+static int qca808x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
+{
+	struct timespec64 ts;
+	const struct qca808x_phy_info *pdata;
+	struct qca808x_ptp_clock *clock =
+		container_of(ptp, struct qca808x_ptp_clock, caps);
+
+	fal_ptp_time_t ptp_time = {0};
+
+	qca808x_priv *priv = clock->priv;
+	pdata = priv->phy_info;
+
+	if (!pdata) {
+		return SW_FAIL;
+	}
+	ts = ns_to_timespec64(delta);
+	ptp_time.seconds = ts.tv_sec;
+	ptp_time.nanoseconds = ts.tv_nsec;
+
+	mutex_lock(&clock->tsreg_lock);
+	qca808x_phy_ptp_rtc_adjtime_set(pdata->dev_id, pdata->phy_addr, &ptp_time);
+	mutex_unlock(&clock->tsreg_lock);
+	return 0;
+}
+
+static void qca808x_ppb_to_freq (a_int32_t speed, a_int32_t ppb, fal_ptp_time_t *ptp_time)
+{
+	a_uint64_t rate;
+	a_uint16_t ns, ns_tmp;
+	a_int32_t neg_adj = 0, tmp = 0;
+
+	if (ppb < 0) {
+		neg_adj = 1;
+		ppb = -ppb;
+	}
+
+	rate = ppb;
+	rate <<= 20;
+	/* divided by (200Mhz-ppb/8)/64 */
+	if (speed == FAL_SPEED_2500) {
+		tmp = (ppb/5)/64;
+		ns_tmp = QCA808X_PTP_TICK_RATE_200M;
+		rate = div_u64(rate, 3125000 + tmp);
+	} else {
+		tmp = (ppb/8)/64;
+		ns_tmp = QCA808X_PTP_TICK_RATE_125M;
+		rate = div_u64(rate, 1953125 + tmp);
+	}
+
+	if(neg_adj && rate != 0) {
+		ns = ns_tmp - 1;
+		rate = (2<<26)-rate;
+	} else {
+		ns = ns_tmp;
+	}
+
+	/* remove the redundant bits, only 26 bits for fracnanoseconds */
+	while (rate & 0xfc000000) {
+		rate >>= 1;
+	}
+
+	ptp_time->seconds = 0;
+	ptp_time->nanoseconds = ns;
+	ptp_time->fracnanoseconds = rate;
+
+	return;
+}
+
+static void qca808x_ptp_adjfreq_sync(a_uint32_t phy_addr,
+		a_int32_t ppb, fal_ptp_time_t ptp_time_org)
+{
+	fal_ptp_reference_clock_t ref_clock = FAL_REF_CLOCK_LOCAL;
+	fal_ptp_time_t ptp_time = {0};
+	struct qca808x_phy_info *pdata = NULL;
+	sw_error_t ret = SW_OK;
+	a_uint32_t gm_mode = 0;
+
+	/*
+	 * In BC mode, the SYNC clock, PPS and Toduart PINs are connected,
+	 * the adjust frequency should be same among the ports to guaranteeing
+	 * the RTC consistent.
+	 */
+	list_for_each_entry(pdata, &g_qca808x_phy_list, list) {
+		if (pdata->phydev_addr != phy_addr) {
+			ret = qca808x_ptp_gm_conf0_reg_grandmaster_mode_get(pdata->dev_id,
+					pdata->phy_addr, &gm_mode);
+			/* The grandmaster mode should be configured to sync RTC */
+			if (ret == SW_OK && gm_mode == PTP_REG_BIT_TRUE) {
+				ptp_time = ptp_time_org;
+				ret = qca808x_phy_ptp_reference_clock_get(pdata->dev_id,
+						pdata->phy_addr, &ref_clock);
+				/*
+				 * BC ports share the same RTC clock in the external mode
+				 * so the adjust frequency should be also same, otherwise
+				 * the ppb should be converted to the corresponding value
+				 * of the adjust frequency.
+				 */
+				if (ret == SW_OK && ref_clock != FAL_REF_CLOCK_EXTERNAL) {
+					qca808x_ppb_to_freq(pdata->speed, ppb, &ptp_time);
+				}
+				qca808x_phy_ptp_rtc_adjfreq_set(pdata->dev_id,
+						pdata->phy_addr, &ptp_time);
+			}
+		}
+	}
+
+	return;
+}
+
+/******************************************************************************
+*
+* qca808x_ptp_adjfreq - adjust the frequency of cycle counter
+*
+* ptp: the ptp clock info structure
+* ppb:  parts per billion adjustment from master
+*
+*/
+static int qca808x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
+{
+	const struct qca808x_phy_info *pdata;
+	struct qca808x_ptp_clock *clock =
+		container_of(ptp, struct qca808x_ptp_clock, caps);
+
+	fal_ptp_time_t ptp_time = {0};
+
+	qca808x_priv *priv = clock->priv;
+	struct phy_device *phydev = priv->phydev;
+	pdata = priv->phy_info;
+
+	if (!pdata || !phydev) {
+		return SW_FAIL;
+	}
+
+	qca808x_ppb_to_freq(pdata->speed, ppb, &ptp_time);
+
+	mutex_lock(&clock->tsreg_lock);
+	qca808x_phy_ptp_rtc_adjfreq_set(pdata->dev_id, pdata->phy_addr, &ptp_time);
+	if (pdata->clock_mode == FAL_BC_CLOCK_MODE) {
+		/* Keep RTC time consistent among BC ports */
+		qca808x_ptp_adjfreq_sync(pdata->phy_addr, ppb, ptp_time);
+	}
+	mutex_unlock(&clock->tsreg_lock);
+	return 0;
+}
+
+static int qca808x_ptp_enable(struct ptp_clock_info *ptp,
+			      struct ptp_clock_request *rq, int on)
+{
+	return -EOPNOTSUPP;
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+static int qca808x_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
+			      enum ptp_pin_function func, unsigned int chan)
+{
+	return 1;
+}
+#endif
+
+void qca808x_ptp_change_notify(struct phy_device *phydev)
+{
+	fal_ptp_reference_clock_t ptp_ref_clock = FAL_REF_CLOCK_EXTERNAL;
+	fal_ptp_time_t ptp_cycle_time = {0};
+	a_uint32_t nanoseconds = 0;
+	qca808x_priv *priv = phydev->priv;
+	struct qca808x_phy_info *pdata = priv->phy_info;
+
+	if (!pdata) {
+		return;
+	}
+
+	if (pdata->speed != phydev->speed) {
+		if (phydev->speed == SPEED_2500 &&
+				pdata->speed < SPEED_2500) {
+			/* adjust frequency to 5ns(200MHz) */
+			nanoseconds = QCA808X_PTP_TICK_RATE_200M;
+		} else if (pdata->speed == SPEED_2500 &&
+				phydev->speed < SPEED_2500) {
+			/* adjust frequency to 8ns(125MHz) */
+			nanoseconds = QCA808X_PTP_TICK_RATE_125M;
+		}
+
+		if (phydev->speed == SPEED_10) {
+			/* local free running clock for 10M */
+			ptp_ref_clock = FAL_REF_CLOCK_LOCAL;
+		} else if (pdata->speed == SPEED_10) {
+			ptp_ref_clock = FAL_REF_CLOCK_SYNCE;
+		}
+
+		if (ptp_ref_clock != FAL_REF_CLOCK_EXTERNAL) {
+			qca808x_phy_ptp_reference_clock_set(pdata->dev_id,
+					pdata->phy_addr, ptp_ref_clock);
+		}
+
+		pdata->speed = phydev->speed;
+		if (nanoseconds != 0) {
+			ptp_cycle_time.nanoseconds = nanoseconds;
+			qca808x_phy_ptp_rtc_adjfreq_set(pdata->dev_id,
+					pdata->phy_addr, &ptp_cycle_time);
+		}
+	}
+}
+
+int qca808x_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
+{
+	struct hwtstamp_config cfg;
+	a_uint32_t gm_mode = 0;
+	fal_ptp_reference_clock_t ref_clock = FAL_REF_CLOCK_LOCAL;
+	sw_error_t ret = SW_OK;
+	fal_ptp_config_t ptp_config = {0};
+	qca808x_priv *priv = phydev->priv;
+	struct qca808x_phy_info *pdata = priv->phy_info;
+	struct qca808x_ptp_info *ptp_info = &priv->ptp_info;
+	struct qca808x_ptp_clock *clock = ptp_info->clock;
+
+	if (!pdata || !clock) {
+		return -EFAULT;
+	}
+
+	if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
+		return -EFAULT;
+	if (cfg.flags) /* reserved for future extensions */
+		return -EINVAL;
+
+	if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_P2P)
+		return -ERANGE;
+
+	ptp_info->hwts_tx_type = cfg.tx_type;
+
+	switch (cfg.rx_filter) {
+		case HWTSTAMP_FILTER_NONE:
+			ptp_info->hwts_rx_type = PTP_CLASS_NONE;
+			break;
+		case HWTSTAMP_FILTER_PTP_V2_EVENT:
+		case HWTSTAMP_FILTER_PTP_V2_SYNC:
+		case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
+			ptp_info->hwts_rx_type = PTP_CLASS_L4 | PTP_CLASS_L2;
+			break;
+		case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
+		case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
+		case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
+			ptp_info->hwts_rx_type = PTP_CLASS_L4;
+			break;
+		case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
+		case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
+		case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
+			ptp_info->hwts_rx_type = PTP_CLASS_L2;
+			break;
+		default:
+			return -ERANGE;
+	}
+
+	mutex_lock(&clock->tsreg_lock);
+	ptp_config.clock_mode = pdata->clock_mode;
+	switch (ptp_info->hwts_tx_type) {
+		case HWTSTAMP_TX_ON:
+			ptp_config.ptp_en = A_TRUE;
+			ptp_config.step_mode = FAL_TWO_STEP_MODE;
+			break;
+		case HWTSTAMP_TX_ONESTEP_SYNC:
+		case HWTSTAMP_TX_ONESTEP_P2P:
+			ptp_config.ptp_en = A_TRUE;
+			ptp_config.step_mode = FAL_ONE_STEP_MODE;
+			break;
+		case HWTSTAMP_TX_OFF:
+		default:
+			ptp_config.ptp_en = A_FALSE;
+			ptp_config.step_mode = FAL_TWO_STEP_MODE;
+			break;
+	}
+	ret = qca808x_phy_ptp_config_set(pdata->dev_id, pdata->phy_addr, &ptp_config);
+	mutex_unlock(&clock->tsreg_lock);
+	if (ret != SW_OK) {
+		return -EFAULT;
+	}
+
+	/*
+	 * disable SYNCE clock output by default,
+	 * only enabling the clock output under the
+	 * BC mode && not in external reference mode
+	 */
+	qca808x_ptp_clock_synce_clock_enable(pdata->dev_id, pdata->phy_addr, A_FALSE);
+
+	if (pdata->clock_mode == FAL_BC_CLOCK_MODE) {
+		ret = qca808x_ptp_gm_conf0_reg_grandmaster_mode_get(pdata->dev_id,
+				pdata->phy_addr, &gm_mode);
+		/* The grandmaster mode should be configured to sync RTC */
+		if (ret == SW_OK && gm_mode != PTP_REG_BIT_TRUE) {
+			ret = qca808x_phy_ptp_reference_clock_get(pdata->dev_id,
+					pdata->phy_addr, &ref_clock);
+			/*
+			 * The PHC should be with below PINs connected for clock synchronized
+			 * so NAPA1 should be configured as sync or local reference clock,
+			 * and NAPA2 is configured as FAL_REF_CLOCK_EXTERNAL & grandmaster mode.
+			 *
+			 * Napa1 ToD out  --- >  Napa2 ToD in.
+			 * Napa1 PPS out  --- >  Napa2 PPS in.
+			 * Napa1 sync clock out --- > Napa2 reference clock in.
+			 */
+			if (ret == SW_OK && ref_clock != FAL_REF_CLOCK_EXTERNAL) {
+				/* enable SYNCE clock output */
+				qca808x_ptp_clock_synce_clock_enable(pdata->dev_id,
+						pdata->phy_addr, A_TRUE);
+			}
+		}
+	}
+
+	pdata->step_mode = ptp_config.step_mode;
+
+	return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
+}
+
+bool qca808x_rxtstamp(struct phy_device *phydev,
+			     struct sk_buff *nskb, int type)
+{
+	struct skb_shared_hwtstamps *shhwtstamps = NULL;
+	struct timespec64 ts = {0};
+	a_bool_t ingress_trig_flag = A_FALSE;
+	a_uint64_t ns;
+	a_int64_t *correction;
+	a_uint16_t *seqid;
+	a_int32_t ptp_class;
+	a_uint32_t *reserved2;
+	a_uint8_t *reserved0, *reserved1;
+	a_uint32_t *cf1;
+	a_uint8_t *ptp_header;
+	a_uint8_t embed_val, pkt_type;
+	qca808x_ptp_cb *ptp_cb = (qca808x_ptp_cb *)nskb->cb;
+	qca808x_priv *priv = phydev->priv;
+	struct qca808x_phy_info *pdata = priv->phy_info;
+	struct qca808x_ptp_info *ptp_info = &priv->ptp_info;
+
+	if (ptp_info->hwts_rx_type == PTP_CLASS_NONE || !pdata) {
+		return false;
+	}
+
+	/* The PTP_CLASS_NONE is passed, which indicates that the
+	 * PTP class is not determined, calling ptp_classify_raw to
+	 * classfy the packet.
+	 */
+	if (type == PTP_CLASS_NONE) {
+		__skb_push(nskb, ETH_HLEN);
+		/* dissecting the packet content to get ptp class */
+		ptp_class = ptp_classify_raw(nskb);
+		__skb_pull(nskb, ETH_HLEN);
+		if (ptp_class == PTP_CLASS_NONE) {
+			/* this case should not happen, only ptp event packet passed */
+			SSDK_ERROR("%s: No PTP event packet received\n", __func__);
+			return false;
+		}
+		type = ptp_class;
+	}
+
+	if ((ptp_info->hwts_rx_type & type) == PTP_CLASS_NONE) {
+		return false;
+	}
+
+	ptp_header = skb_ptp_header(nskb, type);
+	if (!ptp_header) {
+		return false;
+	}
+	shhwtstamps = skb_hwtstamps(nskb);
+	memset(shhwtstamps, 0, sizeof(*shhwtstamps));
+
+#define PTP_HDR_CORRECTIONFIELD_CPY_SRC 11
+#define PTP_HDR_CORRECTIONFIELD_CPY_DST 9
+#define PTP_HDR_CORRECTIONFIELD_CPY_LEN 5
+
+	reserved0 = ptp_header + PTP_HDR_RESERVED0_OFFSET;
+	reserved1 = ptp_header + PTP_HDR_RESERVED1_OFFSET;
+	cf1 = (a_uint32_t *)(ptp_header + PTP_HDR_CORRECTIONFIELD_OFFSET);
+	correction = (a_uint64_t *)(ptp_header + PTP_HDR_CORRECTIONFIELD_OFFSET);
+	seqid = (a_uint16_t *)(ptp_header + OFF_PTP_SEQUENCE_ID);
+	reserved2 = (a_uint32_t *)(ptp_header + PTP_HDR_RESERVED2_OFFSET);
+
+	embed_val = (*reserved0 & 0xf0) >> 4;
+	pkt_type = *ptp_header & 0xf;
+
+	qca808x_ptp_stat_update(pdata, FAL_RX_DIRECTION,
+			QCA808X_PTP_MSG_MAX, PTP_PKT_SEQID_UNMATCHED);
+
+	if (embed_val == QCA808X_PTP_EMBEDDED_MODE) {
+		ts.tv_sec = ntohl(*reserved2);
+		ts.tv_nsec = ((a_uint32_t)*reserved1 << 24) | (ntohl(*cf1) >> 8);
+
+		if (pdata->step_mode == FAL_ONE_STEP_MODE) {
+			switch (pdata->clock_mode) {
+				case FAL_OC_CLOCK_MODE:
+				case FAL_BC_CLOCK_MODE:
+				case FAL_P2PTC_CLOCK_MODE:
+					/* message sync with the timestamp inserted into the ptp
+					 * header, do not use the ingress_trig_time register, the
+					 * ingress time will be acquired from ptp header.
+					 * the ingress time of pdealy request msg should be
+					 * recorded and will be copied the corresponding pdealy
+					 * response msg.
+					 */
+					if (pkt_type == QCA808X_PTP_MSG_PREQ) {
+						ptp_info->embeded_ts.reserved0 = *reserved0;
+						ptp_info->embeded_ts.reserved1 = *reserved1;
+						ptp_info->embeded_ts.reserved2 = *reserved2;
+						ptp_info->embeded_ts.correction = *correction;
+						ptp_info->embeded_ts.seqid = *seqid;
+						ptp_info->embeded_ts.msg_type = pkt_type;
+					}
+					break;
+				case FAL_E2ETC_CLOCK_MODE:
+					ingress_trig_flag = A_TRUE;
+					break;
+				default:
+					break;
+			}
+			if (ingress_trig_flag == A_TRUE) {
+				ptp_info->ingress_time = ts.tv_nsec;
+				schedule_delayed_work(&ptp_info->ingress_trig_work, 0);
+			}
+		}
+
+		/* restore the original correctionfield value except for
+		 * the TC one-step mode offloading*/
+		if (!(((pdata->clock_mode == FAL_P2PTC_CLOCK_MODE &&
+					pkt_type == QCA808X_PTP_MSG_SYNC) ||
+					pdata->clock_mode == FAL_E2ETC_CLOCK_MODE) &&
+					pdata->step_mode == FAL_ONE_STEP_MODE))
+		{
+			/* in embeded mode for the rx time stamp, the correction field
+			 * is modfied to keep the low 50 bit of nanosecond and the
+			 * fractional nanoseconds should be dropped
+			 */
+			*reserved0 = *reserved0 & 0xf;
+			memmove(ptp_header + PTP_HDR_CORRECTIONFIELD_CPY_DST,
+					ptp_header + PTP_HDR_CORRECTIONFIELD_CPY_SRC,
+					PTP_HDR_CORRECTIONFIELD_CPY_LEN);
+			memset(ptp_header + PTP_HDR_CORRECTIONFIELD_OFFSET, 0, 1);
+			memset(ptp_header + PTP_HDR_RESERVED2_OFFSET - 2, 0, 6);
+		}
+	} else {
+		ptp_cb->ptp_type = type;
+		ptp_cb->pkt_type = pkt_type;
+		skb_queue_tail(&ptp_info->rx_queue, nskb);
+		schedule_delayed_work(&ptp_info->rx_ts_work, 0);
+		return true;
+	}
+	ns = timespec64_to_ns(&ts);
+
+	qca808x_ptp_stat_update(pdata, FAL_RX_DIRECTION,
+			pkt_type, PTP_PKT_SEQID_MATCHED);
+
+	shhwtstamps->hwtstamp = ns_to_ktime(ns);
+	netif_rx_ni(nskb);
+
+	return true;
+}
+
+void qca808x_txtstamp(struct phy_device *phydev,
+			     struct sk_buff *org_skb, int type)
+{
+	a_uint8_t msg_type;
+	struct sk_buff *skb;
+	qca808x_ptp_cb *ptp_cb;
+	a_uint8_t *ptp_header;
+	a_int64_t *correction;
+	a_uint32_t *reserved2;
+	a_uint8_t *reserved0, *reserved1;
+	a_uint16_t *seqid;
+	a_int32_t ptp_class;
+	qca808x_priv *priv = phydev->priv;
+	struct qca808x_ptp_info *ptp_info = &priv->ptp_info;
+
+	/* The PTP_CLASS_NONE is passed, which indicates that the
+	 * PTP class is not determined, calling ptp_classify_raw to
+	 * classfy the packet.
+	 */
+	if (type == PTP_CLASS_NONE) {
+		ptp_class = ptp_classify_raw(org_skb);
+		if (ptp_class == PTP_CLASS_NONE) {
+			return;
+		}
+		skb = skb_clone_sk(org_skb);
+		if (!skb) {
+			SSDK_ERROR("%s: skb_clone_sk failed\n", __func__);
+			return;
+		}
+		type = ptp_class;
+	} else {
+		skb = org_skb;
+	}
+
+	ptp_header = skb_ptp_header(skb, type);
+	if (!ptp_header) {
+		kfree_skb(skb);
+		return;
+	}
+
+	ptp_cb = (qca808x_ptp_cb *)skb->cb;
+	seqid = (a_uint16_t *)(ptp_header + OFF_PTP_SEQUENCE_ID);
+	reserved0 = ptp_header + PTP_HDR_RESERVED0_OFFSET;
+	reserved1 = ptp_header + PTP_HDR_RESERVED1_OFFSET;
+	reserved2 = (a_uint32_t *)(ptp_header + PTP_HDR_RESERVED2_OFFSET);
+	correction = (a_uint64_t *)(ptp_header + PTP_HDR_CORRECTIONFIELD_OFFSET);
+	msg_type = *ptp_header & 0xf;
+	switch (ptp_info->hwts_tx_type) {
+		case HWTSTAMP_TX_ONESTEP_SYNC:
+			if (msg_type == QCA808X_PTP_MSG_SYNC) {
+				skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
+				kfree_skb(skb);
+				return;
+			}
+			break;
+		case HWTSTAMP_TX_ONESTEP_P2P:
+			switch (msg_type) {
+				case QCA808X_PTP_MSG_PRESP:
+					if (ptp_info->embeded_ts.seqid == *seqid &&
+							ptp_info->embeded_ts.msg_type ==
+							QCA808X_PTP_MSG_PREQ) {
+						*reserved0 = ptp_info->embeded_ts.reserved0;
+						*reserved1 = ptp_info->embeded_ts.reserved1;
+						*reserved2 = ptp_info->embeded_ts.reserved2;
+						*correction = ptp_info->embeded_ts.correction;
+					}
+					/* fall down */
+				case QCA808X_PTP_MSG_SYNC:
+					skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
+					kfree_skb(skb);
+					return;
+				default:
+					break;
+			}
+			break;
+		case HWTSTAMP_TX_ON:
+			break;
+			/* enqueue skb to get tx timestamp */
+		case HWTSTAMP_TX_OFF:
+		default:
+			kfree_skb(skb);
+			return;
+	}
+
+	skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
+	skb_queue_tail(&ptp_info->tx_queue, skb);
+	ptp_cb->ptp_type = type;
+	qca808x_ptp_stat_update(priv->phy_info, FAL_TX_DIRECTION,
+			QCA808X_PTP_MSG_MAX, PTP_PKT_SEQID_UNMATCHED);
+	schedule_delayed_work(&ptp_info->tx_ts_work, 0);
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+int qca808x_ts_info(struct phy_device *phydev,
+		struct ethtool_ts_info *info)
+{
+	qca808x_priv *priv = phydev->priv;
+	struct qca808x_ptp_info *ptp_info = &priv->ptp_info;
+	struct qca808x_ptp_clock *clock = ptp_info->clock;
+
+	if (clock) {
+		info->phc_index = ptp_clock_index(clock->ptp_clock);
+	}
+
+	info->so_timestamping =
+		SOF_TIMESTAMPING_TX_HARDWARE |
+		SOF_TIMESTAMPING_RX_HARDWARE |
+		SOF_TIMESTAMPING_RAW_HARDWARE;
+	info->tx_types =
+		(1 << HWTSTAMP_TX_OFF) |
+		(1 << HWTSTAMP_TX_ON) |
+		(1 << HWTSTAMP_TX_ONESTEP_SYNC) |
+		(1 << HWTSTAMP_TX_ONESTEP_P2P);
+
+	info->rx_filters =
+		(1 << HWTSTAMP_FILTER_NONE) |
+		(1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
+		(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
+		(1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
+
+	return 0;
+}
+#endif
+
+static int qca808x_ptp_register(struct phy_device *phydev)
+{
+	int err;
+	struct qca808x_ptp_clock *clock;
+	qca808x_priv *priv = phydev->priv;
+	struct qca808x_ptp_info *ptp_info = &priv->ptp_info;
+
+	clock = kzalloc(sizeof(struct qca808x_ptp_clock), GFP_KERNEL);
+	if (!clock) {
+		return -ENOMEM;
+	}
+
+	mutex_init(&clock->tsreg_lock);
+	clock->caps.owner = THIS_MODULE;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0))
+	snprintf(clock->caps.name, sizeof(clock->caps.name), "qca808x timer %x", phydev->mdio.addr);
+#else
+	snprintf(clock->caps.name, sizeof(clock->caps.name), "qca808x timer %x", phydev->addr);
+#endif
+	clock->caps.max_adj	= 3124999;
+	clock->caps.n_alarm	= 0;
+	clock->caps.n_ext_ts	= 6;
+	clock->caps.n_per_out	= 7;
+	clock->caps.pps		= 0;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	clock->caps.n_pins	= 0;
+	clock->caps.verify	= qca808x_ptp_verify;
+	clock->caps.gettime64	= qca808x_ptp_gettime;
+	clock->caps.settime64	= qca808x_ptp_settime;
+#else
+	clock->caps.gettime	= qca808x_ptp_gettime;
+	clock->caps.settime	= qca808x_ptp_settime;
+#endif
+	clock->caps.adjfreq	= qca808x_ptp_adjfreq;
+	clock->caps.adjtime	= qca808x_ptp_adjtime;
+	clock->caps.enable	= qca808x_ptp_enable;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0))
+	clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->mdio.dev);
+#else
+	clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->dev);
+#endif
+	if (IS_ERR(clock->ptp_clock)) {
+		err = PTR_ERR(clock->ptp_clock);
+		kfree(clock);
+		return err;
+	}
+	ptp_info->clock = clock;
+	clock->priv = priv;
+
+	SSDK_INFO("qca808x ptp clock registered\n");
+	return 0;
+}
+
+static void qca808x_ptp_unregister(struct phy_device *phydev)
+{
+	qca808x_priv *priv = phydev->priv;
+	struct qca808x_ptp_info *ptp_info = &priv->ptp_info;
+	struct qca808x_ptp_clock *clock = ptp_info->clock;
+
+	if (clock) {
+		ptp_clock_unregister(clock->ptp_clock);
+		mutex_destroy(&clock->tsreg_lock);
+		kfree(clock);
+	}
+}
+
+int qca808x_ptp_init(qca808x_priv *priv)
+{
+	int err;
+	struct qca808x_ptp_info *ptp_info;
+	struct qca808x_phy_info *pdata;
+
+	if (!priv) {
+		return -1;
+	}
+
+	ptp_info = &priv->ptp_info;
+	pdata = priv->phy_info;
+	INIT_DELAYED_WORK(&ptp_info->tx_ts_work, tx_timestamp_work);
+	INIT_DELAYED_WORK(&ptp_info->rx_ts_work, rx_timestamp_work);
+	skb_queue_head_init(&ptp_info->tx_queue);
+	skb_queue_head_init(&ptp_info->rx_queue);
+
+	INIT_DELAYED_WORK(&ptp_info->ingress_trig_work, ingress_trig_time_work);
+	INIT_DELAYED_WORK(&pdata->ts_schedule_work, qca808x_ptp_schedule_work);
+
+	err = qca808x_ptp_register(priv->phydev);
+	if (err <0) {
+		SSDK_ERROR("qca808x ptp clock register failed\n");
+		kfree(ptp_info);
+		return err;
+	}
+
+	return err;
+}
+
+void qca808x_ptp_deinit(qca808x_priv *priv)
+{
+	struct qca808x_ptp_info *ptp_info;
+	struct qca808x_phy_info *pdata;
+	if (!priv) {
+		return;
+	}
+
+	ptp_info = &priv->ptp_info;
+	pdata = priv->phy_info;
+	cancel_delayed_work_sync(&ptp_info->tx_ts_work);
+	cancel_delayed_work_sync(&ptp_info->rx_ts_work);
+	cancel_delayed_work_sync(&ptp_info->ingress_trig_work);
+	cancel_delayed_work_sync(&pdata->ts_schedule_work);
+	skb_queue_purge(&ptp_info->tx_queue);
+	skb_queue_purge(&ptp_info->rx_queue);
+
+	qca808x_ptp_unregister(priv->phydev);
+}
diff --git a/qca-ssdk/src/hsl/phy/qca808x_phy.c b/qca-ssdk/src/hsl/phy/qca808x_phy.c
new file mode 100755
index 0000000..43bb27a
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/qca808x_phy.c
@@ -0,0 +1,2284 @@
+/*
+ * Copyright (c) 2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+/*qca808x_start*/
+#include "sw.h"
+#include "fal_port_ctrl.h"
+#include "hsl_api.h"
+#include "hsl.h"
+#include "hsl_phy.h"
+#include "ssdk_plat.h"
+#include "qca808x_phy.h"
+/*qca808x_end*/
+#if defined(IN_PTP)
+#include "qca808x_ptp.h"
+#endif
+#include "qca808x.h"
+#ifdef IN_LED
+#include "qca808x_led.h"
+#endif
+
+static a_bool_t phy_dev_drv_init_flag = A_FALSE;
+/*qca808x_start*/
+static a_bool_t phy_ops_flag = A_FALSE;
+
+static struct mutex qca808x_reg_lock;
+
+#define QCA808X_LOCKER_INIT		mutex_init(&qca808x_reg_lock)
+#define QCA808X_REG_LOCK		mutex_lock(&qca808x_reg_lock)
+#define QCA808X_REG_UNLOCK		mutex_unlock(&qca808x_reg_lock)
+
+/******************************************************************************
+*
+* qca808x_phy_mii_read - mii register read
+*
+* mii register read
+*/
+a_uint16_t
+qca808x_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id)
+{
+	sw_error_t rv = SW_OK;
+	a_uint16_t phy_data = 0;
+#if defined(IN_PHY_I2C_MODE)
+	a_uint32_t port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id);
+	a_uint8_t phy_access_type = hsl_port_phy_access_type_get(dev_id, port_id);
+
+	if (phy_access_type == PHY_I2C_ACCESS) {
+		HSL_PHY_I2C_GET(rv, dev_id, phy_id, reg_id, &phy_data);
+	}
+	else
+#endif
+	{
+		HSL_PHY_GET(rv, dev_id, phy_id, reg_id, &phy_data);
+	}
+
+	if (rv != SW_OK) {
+		return PHY_INVALID_DATA;
+	}
+
+	return phy_data;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_mii_write - mii register write
+*
+* mii register write
+*/
+sw_error_t
+qca808x_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id,
+		       a_uint16_t reg_val)
+{
+	sw_error_t rv;
+#if defined(IN_PHY_I2C_MODE)
+	a_uint32_t port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id);
+	a_uint8_t phy_access_type = hsl_port_phy_access_type_get(dev_id, port_id);
+
+	if (phy_access_type == PHY_I2C_ACCESS) {
+		HSL_PHY_I2C_SET(rv, dev_id, phy_id, reg_id, reg_val);
+	}
+	else
+#endif
+	{
+		HSL_PHY_SET(rv, dev_id, phy_id, reg_id, reg_val);
+	}
+
+	return rv;
+
+}
+
+/******************************************************************************
+*
+* qca808x_phy_debug_write - debug port write
+*
+* debug port write
+*/
+sw_error_t
+qca808x_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id,
+		       a_uint16_t reg_val)
+{
+	sw_error_t rv = SW_OK;
+
+	QCA808X_REG_LOCK;
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_DEBUG_PORT_ADDRESS, reg_id);
+	if (rv != SW_OK)
+	{
+		QCA808X_REG_UNLOCK;
+		SSDK_ERROR("qca808x_phy_reg_write failed\n");
+		return SW_FAIL;
+	}
+
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_DEBUG_PORT_DATA, reg_val);
+	if (rv != SW_OK)
+	{
+		QCA808X_REG_UNLOCK;
+		SSDK_ERROR("qca808x_phy_reg_write failed\n");
+		return SW_FAIL;
+	}
+	QCA808X_REG_UNLOCK;
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_debug_read - debug port read
+*
+* debug port read
+*/
+a_uint16_t
+qca808x_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id)
+{
+	sw_error_t rv = SW_OK;
+	a_uint16_t phy_data = 0;
+
+	QCA808X_REG_LOCK;
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_DEBUG_PORT_ADDRESS, reg_id);
+	if (rv != SW_OK) {
+		QCA808X_REG_UNLOCK;
+		SSDK_DEBUG("qca808x_phy_reg_write failed\n");
+		return PHY_INVALID_DATA;
+	}
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_DEBUG_PORT_DATA);
+	if (phy_data == PHY_INVALID_DATA) {
+		QCA808X_REG_UNLOCK;
+		SSDK_DEBUG("qca808x_phy_reg_read failed\n");
+		return PHY_INVALID_DATA;
+	}
+	QCA808X_REG_UNLOCK;
+
+	return phy_data;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_mmd_write - PHY MMD register write
+*
+* PHY MMD register write
+*/
+sw_error_t
+qca808x_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id,
+		     a_uint16_t mmd_num, a_uint16_t reg_id, a_uint16_t reg_val)
+{
+	sw_error_t rv;
+	a_uint32_t reg_id_c45 = QCA808X_REG_C45_ADDRESS(mmd_num, reg_id);
+#if defined(IN_PHY_I2C_MODE)
+	a_uint32_t port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id);
+	a_uint8_t phy_access_type = hsl_port_phy_access_type_get(dev_id, port_id);
+
+	if (phy_access_type == PHY_I2C_ACCESS) {
+		HSL_PHY_I2C_SET(rv, dev_id, phy_id, reg_id_c45, reg_val);
+	}
+	else
+#endif
+	{
+		HSL_PHY_SET(rv, dev_id, phy_id, reg_id_c45, reg_val);
+	}
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_mmd_read -  PHY MMD register read
+*
+* PHY MMD register read
+*/
+a_uint16_t
+qca808x_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id,
+		    a_uint16_t mmd_num, a_uint16_t reg_id)
+{
+	sw_error_t rv = SW_OK;
+	a_uint16_t phy_data = 0;
+	a_uint32_t reg_id_c45 = QCA808X_REG_C45_ADDRESS(mmd_num, reg_id);
+#if defined(IN_PHY_I2C_MODE)
+	a_uint32_t port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id);
+	a_uint8_t phy_access_type = hsl_port_phy_access_type_get(dev_id, port_id);
+
+	if (phy_access_type == PHY_I2C_ACCESS) {
+		HSL_PHY_I2C_GET(rv, dev_id, phy_id, reg_id_c45, &phy_data);
+	}
+	else
+#endif
+	{
+		HSL_PHY_GET(rv, dev_id, phy_id, reg_id_c45, &phy_data);
+	}
+
+	if (rv != SW_OK) {
+		return PHY_INVALID_DATA;
+	}
+
+	return phy_data;
+}
+
+static sw_error_t
+qca808x_phy_ms_random_seed_set(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_debug_read(dev_id, phy_id,
+		QCA808X_DEBUG_LOCAL_SEED);
+	phy_data &= ~(QCA808X_MASTER_SLAVE_SEED_CFG);
+	phy_data |= (prandom_u32()%QCA808X_MASTER_SLAVE_SEED_RANGE) << 2;
+	SSDK_DEBUG("QCA808X_DEBUG_LOCAL_SEED:%x\n", phy_data);
+	rv = qca808x_phy_debug_write(dev_id, phy_id,
+		QCA808X_DEBUG_LOCAL_SEED, phy_data);
+
+	return rv;
+}
+
+static sw_error_t
+qca808x_phy_ms_seed_enable(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_debug_read(dev_id, phy_id,
+		QCA808X_DEBUG_LOCAL_SEED);
+	if(enable)
+	{
+		phy_data |= QCA808X_MASTER_SLAVE_SEED_ENABLE;
+	}
+	else
+	{
+		phy_data &= ~(QCA808X_MASTER_SLAVE_SEED_ENABLE);
+	}
+	rv = qca808x_phy_debug_write(dev_id, phy_id,
+		QCA808X_DEBUG_LOCAL_SEED, phy_data);
+
+	return rv;
+}
+
+a_bool_t
+qca808x_phy_2500caps(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+							QCA808X_MMD1_PMA_CAP_REG);
+
+	if (phy_data & QCA808X_STATUS_2500T_FD_CAPS) {
+		phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+			QCA808X_PHY_MMD7_CHIP_TYPE);
+		if(!(phy_data & QCA808X_PHY_1G_CHIP_TYPE))
+			return A_TRUE;
+	}
+
+	return A_FALSE;
+
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get status
+*
+* get phy status
+*/
+sw_error_t
+qca808x_phy_get_status(a_uint32_t dev_id, a_uint32_t phy_id,
+		struct port_phy_status *phy_status)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_SPEC_STATUS);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	/*get phy link status*/
+	if (phy_data & QCA808X_STATUS_LINK_PASS) {
+		phy_status->link_status = A_TRUE;
+	}
+	else {
+		phy_status->link_status = A_FALSE;
+		if (qca808x_phy_2500caps(dev_id, phy_id) == A_TRUE) {
+			SW_RTN_ON_ERROR(
+				qca808x_phy_ms_random_seed_set (dev_id, phy_id));
+			/*protect logic, if MASTER_SLAVE_CONFIG_FAULT is 1,
+				then disable this logic*/
+			phy_data = qca808x_phy_reg_read(dev_id, phy_id,
+				QCA808X_1000BASET_STATUS);
+			if ((phy_data & QCA808X_MASTER_SLAVE_CONFIG_FAULT) >> 15)
+			{
+				SW_RTN_ON_ERROR(
+					qca808x_phy_ms_seed_enable (dev_id, phy_id, A_FALSE));
+				SSDK_INFO("master_slave_config_fault was set\n");
+			}
+		}
+
+		return SW_OK;
+	}
+
+	/*get phy speed*/
+	switch (phy_data & QCA808X_STATUS_SPEED_MASK) {
+		case QCA808X_STATUS_SPEED_2500MBS:
+			phy_status->speed = FAL_SPEED_2500;
+			break;
+		case QCA808X_STATUS_SPEED_1000MBS:
+			phy_status->speed = FAL_SPEED_1000;
+			break;
+		case QCA808X_STATUS_SPEED_100MBS:
+			phy_status->speed = FAL_SPEED_100;
+			break;
+		case QCA808X_STATUS_SPEED_10MBS:
+			phy_status->speed = FAL_SPEED_10;
+			break;
+		default:
+			return SW_READ_ERROR;
+	}
+
+	/*get phy duplex*/
+	if (phy_data & QCA808X_STATUS_FULL_DUPLEX) {
+		phy_status->duplex = FAL_FULL_DUPLEX;
+	} else {
+		phy_status->duplex = FAL_HALF_DUPLEX;
+	}
+
+	/* get phy flowctrl resolution status */
+	if (phy_data & QCA808X_PHY_RX_FLOWCTRL_STATUS) {
+		phy_status->rx_flowctrl = A_TRUE;
+	} else {
+		phy_status->rx_flowctrl = A_FALSE;
+	}
+
+	if (phy_data & QCA808X_PHY_TX_FLOWCTRL_STATUS) {
+		phy_status->tx_flowctrl = A_TRUE;
+	} else {
+		phy_status->tx_flowctrl = A_FALSE;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get_speed - Determines the speed of phy ports associated with the
+* specified device.
+*/
+
+sw_error_t
+qca808x_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+		     fal_port_speed_t * speed)
+{
+	sw_error_t rv = SW_OK;
+	struct port_phy_status phy_status = {0};
+
+	rv = qca808x_phy_get_status(dev_id, phy_id, &phy_status);
+	PHY_RTN_ON_ERROR(rv);
+
+	if (phy_status.link_status == A_TRUE) {
+		*speed = phy_status.speed;
+	} else {
+		*speed = FAL_SPEED_10;
+	}
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_set_force_speed - Force the speed of qca808x phy ports associated with the
+* specified device.
+*/
+sw_error_t
+qca808x_phy_set_force_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+		     fal_port_speed_t speed)
+{
+	a_uint16_t phy_data1 = 0;
+	a_uint16_t phy_data2 = 0;
+	sw_error_t rv = SW_OK;
+
+	/* the speed of qca808x controled by MMD1 PMA/PMD control register */
+	phy_data1 = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+			QCA808X_PHY_MMD1_PMA_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data1);
+	phy_data1 &= ~QCA808X_PMA_CONTROL_SPEED_MASK;
+
+	phy_data2 = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+			QCA808X_PHY_MMD1_PMA_TYPE);
+	PHY_RTN_ON_READ_ERROR(phy_data2);
+	phy_data2 &= ~QCA808X_PMA_TYPE_MASK;
+
+	switch(speed)
+	{
+#if 0
+		case FAL_SPEED_2500:
+			if(!qca808x_phy_2500caps(dev_id, phy_id))
+				return SW_NOT_SUPPORTED;
+			phy_data1 |= QCA808X_PMA_CONTROL_2500M;
+			phy_data2 |= QCA808X_PMA_TYPE_2500M;
+			break;
+#endif
+		case FAL_SPEED_1000:
+			phy_data1 |= QCA808X_PMA_CONTROL_1000M;
+			phy_data2 |= QCA808X_PMA_TYPE_1000M;
+			break;
+		case FAL_SPEED_100:
+			phy_data1 |= QCA808X_PMA_CONTROL_100M;
+			phy_data2 |= QCA808X_PMA_TYPE_100M;
+			break;
+		case FAL_SPEED_10:
+			phy_data1 |= QCA808X_PMA_CONTROL_10M;
+			phy_data2 |= QCA808X_PMA_TYPE_10M;
+			break;
+		default:
+			return SW_BAD_PARAM;
+	}
+
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+			QCA808X_PHY_MMD1_PMA_CONTROL, phy_data1);
+	PHY_RTN_ON_ERROR(rv);
+
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+			QCA808X_PHY_MMD1_PMA_TYPE, phy_data2);
+
+	return rv;
+}
+
+sw_error_t
+_qca808x_phy_set_autoneg_adv_ext(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t autoneg)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+			QCA808X_PHY_MMD7_AUTONEGOTIATION_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (autoneg & FAL_PHY_ADV_2500T_FD) {
+		phy_data |= QCA808X_ADVERTISE_2500FULL;
+	} else {
+		phy_data &= ~QCA808X_ADVERTISE_2500FULL;
+	}
+
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+			QCA808X_PHY_MMD7_AUTONEGOTIATION_CONTROL, phy_data);
+
+	return rv;
+
+}
+
+/******************************************************************************
+*
+* qca808x_phy_set_speed - Determines the speed of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+qca808x_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+		     fal_port_speed_t speed)
+{
+	a_uint16_t phy_data = 0;
+	fal_port_duplex_t old_duplex = QCA808X_CTRL_FULL_DUPLEX;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	switch(speed)
+	{
+		case FAL_SPEED_2500:
+		case FAL_SPEED_1000:
+			if (speed == FAL_SPEED_2500) {
+				if(!qca808x_phy_2500caps(dev_id, phy_id))
+					return SW_NOT_SUPPORTED;
+				rv = _qca808x_phy_set_autoneg_adv_ext(dev_id, phy_id,
+						FAL_PHY_ADV_2500T_FD);
+				PHY_RTN_ON_ERROR(rv);
+			} else {
+				rv = _qca808x_phy_set_autoneg_adv_ext(dev_id, phy_id,
+						~FAL_PHY_ADV_2500T_FD);
+				PHY_RTN_ON_ERROR(rv);
+			}
+			phy_data |= QCA808X_CTRL_FULL_DUPLEX;
+			phy_data |= QCA808X_CTRL_AUTONEGOTIATION_ENABLE;
+			phy_data |= QCA808X_CTRL_RESTART_AUTONEGOTIATION;
+			break;
+		case FAL_SPEED_100:
+		case FAL_SPEED_10:
+			/* set qca808x phy speed by pma control registers */
+			rv = qca808x_phy_set_force_speed(dev_id, phy_id, speed);
+			PHY_RTN_ON_ERROR(rv);
+			rv = qca808x_phy_get_duplex(dev_id, phy_id, &old_duplex);
+			PHY_RTN_ON_ERROR(rv);
+
+			if (old_duplex == FAL_FULL_DUPLEX) {
+				phy_data |= QCA808X_CTRL_FULL_DUPLEX;
+			}
+			else if (old_duplex == FAL_HALF_DUPLEX) {
+				phy_data &= ~QCA808X_CTRL_FULL_DUPLEX;
+			}
+			phy_data &= ~QCA808X_CTRL_AUTONEGOTIATION_ENABLE;
+			break;
+		default:
+			return SW_BAD_PARAM;
+	}
+
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_set_duplex - Determines the duplex of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+qca808x_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+		      fal_port_duplex_t duplex)
+{
+	a_uint16_t phy_data = 0;
+	fal_port_speed_t old_speed;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	rv = qca808x_phy_get_speed(dev_id, phy_id, &old_speed);
+	PHY_RTN_ON_ERROR(rv);
+
+	switch(old_speed)
+	{
+		case FAL_SPEED_2500:
+		case FAL_SPEED_1000:
+			if (duplex == FAL_FULL_DUPLEX) {
+				phy_data |= QCA808X_CTRL_FULL_DUPLEX;
+			} else {
+				return SW_NOT_SUPPORTED;
+			}
+			phy_data |= QCA808X_CTRL_AUTONEGOTIATION_ENABLE;
+
+			if (old_speed == FAL_SPEED_2500) {
+				rv = _qca808x_phy_set_autoneg_adv_ext(dev_id, phy_id,
+						FAL_PHY_ADV_2500T_FD);
+				PHY_RTN_ON_ERROR(rv);
+			} else {
+				rv = _qca808x_phy_set_autoneg_adv_ext(dev_id, phy_id,
+						~FAL_PHY_ADV_2500T_FD);
+				PHY_RTN_ON_ERROR(rv);
+			}
+			break;
+		case FAL_SPEED_100:
+		case FAL_SPEED_10:
+			/* force the speed */
+			rv = qca808x_phy_set_force_speed(dev_id, phy_id, old_speed);
+			PHY_RTN_ON_ERROR(rv);
+			phy_data &= ~QCA808X_CTRL_AUTONEGOTIATION_ENABLE;
+			if (duplex == FAL_FULL_DUPLEX) {
+				phy_data |= QCA808X_CTRL_FULL_DUPLEX;
+			} else {
+				phy_data &= ~QCA808X_CTRL_FULL_DUPLEX;
+			}
+			break;
+		default:
+			return SW_FAIL;
+	}
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get_duplex - Determines the duplex of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+qca808x_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+		      fal_port_duplex_t * duplex)
+{
+	sw_error_t rv = SW_OK;
+	struct port_phy_status phy_status = {0};
+
+	rv = qca808x_phy_get_status(dev_id, phy_id, &phy_status);
+	PHY_RTN_ON_ERROR(rv);
+
+	if (phy_status.link_status == A_TRUE) {
+		*duplex = phy_status.duplex;
+	} else {
+		*duplex = FAL_HALF_DUPLEX;
+	}
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_reset - reset the phy
+*
+* reset the phy
+*/
+sw_error_t qca808x_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL,
+			     phy_data | QCA808X_CTRL_SOFTWARE_RESET);
+	SW_RTN_ON_ERROR(rv);
+	/*the configure will lost when reset.*/
+	rv = qca808x_phy_ms_seed_enable(dev_id, phy_id, A_TRUE);
+
+	return rv;
+}
+/******************************************************************************
+*
+* qca808x_phy_status - test to see if the specified phy link is alive
+*
+* RETURNS:
+*    A_TRUE  --> link is alive
+*    A_FALSE --> link is down
+*/
+a_bool_t qca808x_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	struct port_phy_status phy_status = {0};
+	sw_error_t rv = SW_OK;
+
+	rv = qca808x_phy_get_status(dev_id, phy_id, &phy_status);
+	if (rv == SW_OK) {
+		return phy_status.link_status;
+	} else {
+		return A_FALSE;
+	}
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* qca808x_phy_cdt - cable diagnostic test
+*
+* cable diagnostic test
+*/
+
+static inline fal_cable_status_t _phy_cdt_status_mapping(a_uint16_t status)
+{
+	fal_cable_status_t status_mapping = FAL_CABLE_STATUS_INVALID;
+
+	switch (status) {
+		case 0:
+			status_mapping = FAL_CABLE_STATUS_INVALID;
+			break;
+		case 1:
+			status_mapping = FAL_CABLE_STATUS_NORMAL;
+			break;
+		case 2:
+			status_mapping = FAL_CABLE_STATUS_OPENED;
+			break;
+		case 3:
+			status_mapping = FAL_CABLE_STATUS_SHORT;
+			break;
+	}
+
+	return status_mapping;
+}
+
+static sw_error_t qca808x_phy_cdt_start(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t status = 0;
+	a_uint16_t ii = 100;
+	sw_error_t rv = SW_OK;
+
+	/* RUN CDT */
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CDT_CONTROL,
+			     QCA808X_RUN_CDT | QCA808X_CABLE_LENGTH_UNIT);
+	PHY_RTN_ON_ERROR(rv);
+
+	do {
+		aos_mdelay(30);
+		status =
+		    qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CDT_CONTROL);
+		PHY_RTN_ON_READ_ERROR(status);
+	}
+	while ((status & QCA808X_RUN_CDT) && (--ii));
+
+	if (ii == 0) {
+		return SW_TIMEOUT;
+	} else {
+		return SW_OK;
+	}
+}
+
+sw_error_t
+qca808x_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+	       fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+	a_uint16_t cable_delta_time = 0;
+	a_uint16_t status;
+	sw_error_t rv;
+
+	if ((mdi_pair >= QCA808X_MDI_PAIR_NUM)) {
+		return SW_BAD_PARAM;
+	}
+
+	rv = qca808x_phy_cdt_start(dev_id, phy_id);
+
+	if (rv != SW_OK) {
+		*cable_status = FAL_CABLE_STATUS_INVALID;
+		*cable_len = 0;
+		return rv;
+	}
+
+	/* Get cable status */
+	status = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+			QCA808X_PHY_CDT_STATUS);
+	PHY_RTN_ON_READ_ERROR(status);
+
+	switch (mdi_pair) {
+		case 0:
+			*cable_status =
+				_phy_cdt_status_mapping((status >> 12) & 0x3);
+			cable_delta_time =
+				qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+						QCA808X_PHY_CDT_DIAG_PAIR0);
+			PHY_RTN_ON_READ_ERROR(cable_delta_time);
+
+			break;
+		case 1:
+			*cable_status =
+				_phy_cdt_status_mapping((status >> 8) & 0x3);
+			cable_delta_time =
+				qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+						QCA808X_PHY_CDT_DIAG_PAIR1);
+			PHY_RTN_ON_READ_ERROR(cable_delta_time);
+
+			break;
+		case 2:
+			*cable_status =
+				_phy_cdt_status_mapping((status >> 4) & 0x3);
+			cable_delta_time =
+				qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+						QCA808X_PHY_CDT_DIAG_PAIR2);
+			PHY_RTN_ON_READ_ERROR(cable_delta_time);
+
+			break;
+		case 3:
+			*cable_status =
+				_phy_cdt_status_mapping(status & 0x3);
+			cable_delta_time =
+				qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+						QCA808X_PHY_CDT_DIAG_PAIR3);
+			PHY_RTN_ON_READ_ERROR(cable_delta_time);
+
+			break;
+	}
+
+	/* the actual cable length equals to CableDeltaTime * 0.824 */
+	*cable_len = ((cable_delta_time & 0xff) * 824) / 1000;
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_set_mdix -
+*
+* set phy mdix configuraiton
+*/
+sw_error_t
+qca808x_phy_set_mdix(a_uint32_t dev_id, a_uint32_t phy_id,
+		    fal_port_mdix_mode_t mode)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_SPEC_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (mode == PHY_MDIX_AUTO) {
+		phy_data |= QCA808X_PHY_MDIX_AUTO;
+	} else if (mode == PHY_MDIX_MDIX) {
+		phy_data &= ~QCA808X_PHY_MDIX_AUTO;
+		phy_data |= QCA808X_PHY_MDIX;
+	} else if (mode == PHY_MDIX_MDI) {
+		phy_data &= ~QCA808X_PHY_MDIX_AUTO;
+	} else {
+		return SW_BAD_PARAM;
+	}
+
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_SPEC_CONTROL, phy_data);
+	PHY_RTN_ON_ERROR(rv);
+
+	rv = qca808x_phy_reset(dev_id, phy_id);
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get_mdix
+*
+* get phy mdix configuration
+*/
+sw_error_t
+qca808x_phy_get_mdix(a_uint32_t dev_id, a_uint32_t phy_id,
+		    fal_port_mdix_mode_t * mode)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_SPEC_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if ((phy_data & QCA808X_PHY_MDIX_AUTO) == QCA808X_PHY_MDIX_AUTO) {
+		*mode = PHY_MDIX_AUTO;
+	} else if ((phy_data & QCA808X_PHY_MDIX) == QCA808X_PHY_MDIX) {
+		*mode = PHY_MDIX_MDIX;
+	} else {
+		*mode = PHY_MDIX_MDI;
+	}
+
+	return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get_mdix status
+*
+* get phy mdix status
+*/
+sw_error_t
+qca808x_phy_get_mdix_status(a_uint32_t dev_id, a_uint32_t phy_id,
+			   fal_port_mdix_status_t * mode)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_SPEC_STATUS);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	*mode =
+	    (phy_data & QCA808X_PHY_MDIX_STATUS) ? PHY_MDIX_STATUS_MDIX :
+	    PHY_MDIX_STATUS_MDI;
+
+	return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* qca808x_phy_set_local_loopback
+*
+* set phy local loopback
+*/
+sw_error_t
+qca808x_phy_set_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	fal_port_speed_t old_speed;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (enable == A_TRUE) {
+		/* get the link speed first, then force the corresponding
+		 * speed to enable local loopback */
+		rv = qca808x_phy_get_speed(dev_id, phy_id, &old_speed);
+		PHY_RTN_ON_ERROR(rv);
+		rv = qca808x_phy_set_force_speed(dev_id, phy_id, old_speed);
+		PHY_RTN_ON_ERROR(rv);
+
+		phy_data &= ~QCA808X_CTRL_AUTONEGOTIATION_ENABLE;
+		phy_data |= QCA808X_LOCAL_LOOPBACK_ENABLE;
+		phy_data |= QCA808X_CTRL_FULL_DUPLEX;
+	} else {
+		phy_data = QCA808X_COMMON_CTRL;
+	}
+
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL, phy_data);
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get_local_loopback
+*
+* get phy local loopback
+*/
+sw_error_t
+qca808x_phy_get_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+			      a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & QCA808X_LOCAL_LOOPBACK_ENABLE) {
+		*enable = A_TRUE;
+	} else {
+		*enable = A_FALSE;
+	}
+
+	return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* qca808x_phy_set_remote_loopback
+*
+* set phy remote loopback
+*/
+sw_error_t
+qca808x_phy_set_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+			       a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+					QCA808X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (enable == A_TRUE) {
+		phy_data |= QCA808X_PHY_REMOTE_LOOPBACK_EN;
+	} else {
+		phy_data &= ~QCA808X_PHY_REMOTE_LOOPBACK_EN;
+	}
+
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+			     QCA808X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL,
+			     phy_data);
+	return rv;
+
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get_remote_loopback
+*
+* get phy remote loopback
+*/
+sw_error_t
+qca808x_phy_get_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id,
+			       a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+					QCA808X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & QCA808X_PHY_REMOTE_LOOPBACK_EN) {
+		*enable = A_TRUE;
+	} else {
+		*enable = A_FALSE;
+	}
+
+	return SW_OK;
+
+}
+#endif
+/******************************************************************************
+*
+* qca808x_set_autoneg_adv - set the phy autoneg Advertisement
+*
+*/
+sw_error_t
+qca808x_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+			   a_uint32_t autoneg)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id,
+			QCA808X_AUTONEG_ADVERT);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	phy_data &= ~QCA808X_ADVERTISE_MEGA_ALL;
+
+	if (autoneg & FAL_PHY_ADV_100TX_FD) {
+		phy_data |= QCA808X_ADVERTISE_100FULL;
+	}
+
+	if (autoneg & FAL_PHY_ADV_100TX_HD) {
+		phy_data |= QCA808X_ADVERTISE_100HALF;
+	}
+
+	if (autoneg & FAL_PHY_ADV_10T_FD) {
+		phy_data |= QCA808X_ADVERTISE_10FULL;
+	}
+
+	if (autoneg & FAL_PHY_ADV_10T_HD) {
+		phy_data |= QCA808X_ADVERTISE_10HALF;
+	}
+
+	if (autoneg & FAL_PHY_ADV_PAUSE) {
+		phy_data |= QCA808X_ADVERTISE_PAUSE;
+	}
+
+	if (autoneg & FAL_PHY_ADV_ASY_PAUSE) {
+		phy_data |= QCA808X_ADVERTISE_ASYM_PAUSE;
+	}
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_AUTONEG_ADVERT,
+			phy_data);
+	PHY_RTN_ON_ERROR(rv);
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id,
+				QCA808X_1000BASET_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	phy_data &= ~QCA808X_ADVERTISE_1000FULL;
+	phy_data &= ~QCA808X_ADVERTISE_1000HALF;
+
+	if (autoneg & FAL_PHY_ADV_1000T_FD) {
+		phy_data |= QCA808X_ADVERTISE_1000FULL;
+	}
+
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_1000BASET_CONTROL,
+			phy_data);
+	PHY_RTN_ON_ERROR(rv);
+
+	if (qca808x_phy_2500caps(dev_id, phy_id) == A_TRUE) {
+		rv = _qca808x_phy_set_autoneg_adv_ext(dev_id, phy_id, autoneg);
+		PHY_RTN_ON_ERROR(rv);
+	} else {
+		if(autoneg & FAL_PHY_ADV_2500T_FD) {
+			SSDK_ERROR("2.5G auto adv is not supported\n");
+			return SW_NOT_SUPPORTED;
+		}
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+_qca808x_phy_get_autoneg_adv_ext(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t *phy_data)
+{
+	*phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+			QCA808X_PHY_MMD7_AUTONEGOTIATION_CONTROL);
+	PHY_RTN_ON_READ_ERROR(*phy_data);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca808x_get_autoneg_adv - get the phy autoneg Advertisement
+*
+*/
+sw_error_t
+qca808x_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+			   a_uint32_t * autoneg)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	*autoneg = 0;
+	phy_data =
+		qca808x_phy_reg_read(dev_id, phy_id, QCA808X_AUTONEG_ADVERT);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & QCA808X_ADVERTISE_100FULL) {
+		*autoneg |= FAL_PHY_ADV_100TX_FD;
+	}
+
+	if (phy_data & QCA808X_ADVERTISE_100HALF) {
+		*autoneg |= FAL_PHY_ADV_100TX_HD;
+	}
+
+	if (phy_data & QCA808X_ADVERTISE_10FULL) {
+		*autoneg |= FAL_PHY_ADV_10T_FD;
+	}
+
+	if (phy_data & QCA808X_ADVERTISE_10HALF) {
+		*autoneg |= FAL_PHY_ADV_10T_HD;
+	}
+
+	if (phy_data & QCA808X_ADVERTISE_PAUSE) {
+		*autoneg |= FAL_PHY_ADV_PAUSE;
+	}
+
+	if (phy_data & QCA808X_ADVERTISE_ASYM_PAUSE) {
+		*autoneg |= FAL_PHY_ADV_ASY_PAUSE;
+	}
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id,
+				QCA808X_1000BASET_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & QCA808X_ADVERTISE_1000FULL) {
+		*autoneg |= FAL_PHY_ADV_1000T_FD;
+	}
+
+	if (qca808x_phy_2500caps(dev_id, phy_id) == A_TRUE) {
+		rv = _qca808x_phy_get_autoneg_adv_ext(dev_id, phy_id, &phy_data);
+		if ((rv == SW_OK) &&
+				(phy_data & QCA808X_ADVERTISE_2500FULL)) {
+			*autoneg |= FAL_PHY_ADV_2500T_FD;
+		}
+	}
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_autoneg_status - get the phy autoneg status
+*
+*/
+a_bool_t qca808x_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL);
+
+	if (phy_data & QCA808X_CTRL_AUTONEGOTIATION_ENABLE) {
+		return A_TRUE;
+	}
+
+	return A_FALSE;
+}
+
+/******************************************************************************
+*
+* qca808x_restart_autoneg - restart the phy autoneg
+*
+*/
+sw_error_t qca808x_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	phy_data |= QCA808X_CTRL_AUTONEGOTIATION_ENABLE;
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL,
+			     phy_data | QCA808X_CTRL_RESTART_AUTONEGOTIATION);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_enable_autonego
+*
+*/
+sw_error_t qca808x_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL,
+			     phy_data | QCA808X_CTRL_AUTONEGOTIATION_ENABLE);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get_phy_id - get the phy id
+*
+*/
+sw_error_t
+qca808x_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id,
+		      a_uint32_t *phy_data)
+{
+	a_uint16_t org_id, rev_id;
+	org_id = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_ID1);
+	PHY_RTN_ON_READ_ERROR(org_id);
+
+	rev_id = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_ID2);
+	PHY_RTN_ON_READ_ERROR(rev_id);
+
+	*phy_data = ((org_id & 0xffff) << 16) | (rev_id & 0xffff);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_off - power off the phy
+*
+* Power off the phy
+*/
+sw_error_t qca808x_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL,
+				     phy_data | QCA808X_CTRL_POWER_DOWN);
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_on - power on the phy
+*
+* Power on the phy
+*/
+sw_error_t qca808x_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL,
+			phy_data & ~QCA808X_CTRL_POWER_DOWN);
+
+	aos_mdelay(200);
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* qca808x_phy_set_802.3az
+*
+* set 802.3az status
+*/
+sw_error_t
+qca808x_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+				       QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (enable == A_TRUE) {
+		phy_data |= QCA808X_PHY_8023AZ_EEE_1000BT;
+		phy_data |= QCA808X_PHY_8023AZ_EEE_100BT;
+	} else {
+		phy_data &= ~QCA808X_PHY_8023AZ_EEE_1000BT;
+		phy_data &= ~QCA808X_PHY_8023AZ_EEE_100BT;
+	}
+
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+			QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data);
+	PHY_RTN_ON_ERROR(rv);
+
+	rv = qca808x_phy_restart_autoneg(dev_id, phy_id);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get_8023az status
+*
+* get 8023az status
+*/
+sw_error_t
+qca808x_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+	*enable = A_FALSE;
+
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+				       QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if ((phy_data & QCA808X_PHY_8023AZ_EEE_1000BT) &&
+			(phy_data & QCA808X_PHY_8023AZ_EEE_100BT)) {
+		*enable = A_TRUE;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* _qca808x_phy_get_8023az_status status
+*
+* get 8023az status
+*/
+sw_error_t
+_qca808x_phy_get_8023az_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+	*enable = A_FALSE;
+
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+				       QCA808X_PHY_MMD3_ADDR_8023AZ_EEE_DB);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & QCA808X_PHY_8023AZ_EEE_LP_STAT) {
+		*enable = A_TRUE;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_set wol frame mac address
+*
+* set phy wol frame mac address
+*/
+sw_error_t
+qca808x_phy_set_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id,
+			       fal_mac_addr_t * mac)
+{
+	a_uint16_t phy_data1;
+	a_uint16_t phy_data2;
+	a_uint16_t phy_data3;
+	sw_error_t rv = SW_OK;
+
+	phy_data1 = (mac->uc[0] << 8) | mac->uc[1];
+	phy_data2 = (mac->uc[2] << 8) | mac->uc[3];
+	phy_data3 = (mac->uc[4] << 8) | mac->uc[5];
+
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+			     QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL1, phy_data1);
+	PHY_RTN_ON_ERROR(rv);
+
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+			     QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL2, phy_data2);
+	PHY_RTN_ON_ERROR(rv);
+
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+			     QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL3, phy_data3);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get wol frame mac address
+*
+* get phy wol frame mac address
+*/
+sw_error_t
+qca808x_phy_get_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id,
+			       fal_mac_addr_t * mac)
+{
+	a_uint16_t phy_data1;
+	a_uint16_t phy_data2;
+	a_uint16_t phy_data3;
+
+	phy_data1 = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+					QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL1);
+	PHY_RTN_ON_READ_ERROR(phy_data1);
+
+	phy_data2 = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+					QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL2);
+	PHY_RTN_ON_READ_ERROR(phy_data2);
+
+	phy_data3 = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+					QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL3);
+	PHY_RTN_ON_READ_ERROR(phy_data3);
+
+	mac->uc[0] = (phy_data1 >> 8);
+	mac->uc[1] = (phy_data1 & 0x00ff);
+	mac->uc[2] = (phy_data2 >> 8);
+	mac->uc[3] = (phy_data2 & 0x00ff);
+	mac->uc[4] = (phy_data3 >> 8);
+	mac->uc[5] = (phy_data3 & 0x00ff);
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_set wol enable or disable
+*
+* set phy wol enable or disable
+*/
+sw_error_t
+qca808x_phy_set_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+				       QCA808X_PHY_MMD3_WOL_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (enable == A_TRUE) {
+		phy_data |= QCA808X_PHY_WOL_EN;
+	} else {
+		phy_data &= ~QCA808X_PHY_WOL_EN;
+	}
+
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+			     QCA808X_PHY_MMD3_WOL_CTRL, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get_wol status
+*
+* get wol status
+*/
+sw_error_t
+qca808x_phy_get_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	*enable = A_FALSE;
+
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+				       QCA808X_PHY_MMD3_WOL_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & QCA808X_PHY_WOL_EN) {
+		*enable = A_TRUE;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_set_hibernate - set hibernate status
+*
+* set hibernate status
+*/
+sw_error_t
+qca808x_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_debug_read(dev_id, phy_id,
+			QCA808X_DEBUG_PHY_HIBERNATION_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (enable == A_TRUE) {
+		phy_data |= QCA808X_PHY_HIBERNATION_CFG;
+	} else {
+		phy_data &= ~QCA808X_PHY_HIBERNATION_CFG;
+	}
+
+	rv = qca808x_phy_debug_write(dev_id, phy_id,
+			QCA808X_DEBUG_PHY_HIBERNATION_CTRL, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get_hibernate - get hibernate status
+*
+* get hibernate status
+*/
+sw_error_t
+qca808x_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	*enable = A_FALSE;
+
+	phy_data = qca808x_phy_debug_read(dev_id, phy_id,
+			QCA808X_DEBUG_PHY_HIBERNATION_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & QCA808X_PHY_HIBERNATION_CFG) {
+		*enable = A_TRUE;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* _qca808x_phy_get_hibernate_status - get hibernate status
+*
+* get hibernate status
+*/
+sw_error_t
+_qca808x_phy_get_hibernate_status(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	*enable = A_TRUE;
+
+	phy_data = qca808x_phy_debug_read(dev_id, phy_id,
+			QCA808X_DEBUG_PHY_HIBERNATION_STAT);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & QCA808X_PHY_HIBERNATION_STAT_EN) {
+		*enable = A_FALSE;
+	}
+
+	return SW_OK;
+}
+#endif
+/******************************************************************************
+*
+* qca808x_phy_interface mode set
+*
+* set qca808x phy interface mode
+*/
+sw_error_t
+qca808x_phy_interface_set_mode(a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_port_interface_mode_t interface_mode)
+{
+	/* qca808x phy will automatically switch the interface mode according
+	 * to the speed, 2.5G works on SGMII+, other works on SGMII.
+	 */
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_interface mode get
+*
+* get qca808x phy interface mode
+*/
+sw_error_t
+qca808x_phy_interface_get_mode(a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_port_interface_mode_t *interface_mode)
+{
+	a_uint16_t phy_data;
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CHIP_CONFIG);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	phy_data &= QCA808X_PHY_CHIP_MODE_CFG;
+	if (phy_data == QCA808X_PHY_SGMII_BASET) {
+		*interface_mode = PHY_SGMII_BASET;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_interface mode status get
+*
+* get qca808x phy interface mode status
+*/
+sw_error_t
+qca808x_phy_interface_get_mode_status(a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_port_interface_mode_t *interface_mode_status)
+{
+	a_uint16_t phy_data;
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CHIP_CONFIG);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	phy_data &= QCA808X_PHY_MODE_MASK;
+	switch (phy_data) {
+		case QCA808X_PHY_SGMII_PLUS_MODE:
+			*interface_mode_status = PORT_SGMII_PLUS;
+			break;
+		case QCA808X_PHY_SGMII_MODE:
+			*interface_mode_status = PHY_SGMII_BASET;
+			break;
+		default:
+			*interface_mode_status = PORT_INTERFACE_MODE_MAX;
+			break;
+	}
+
+	return SW_OK;
+}
+#ifndef IN_PORTCONTROL_MINI
+/******************************************************************************
+*
+* qca808x_phy_set_intr_mask - Set interrupt mask with the
+* specified device.
+*/
+sw_error_t
+qca808x_phy_set_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_uint32_t intr_mask_flag)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_INTR_MASK);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (intr_mask_flag & FAL_PHY_INTR_STATUS_UP_CHANGE) {
+		phy_data |= QCA808X_INTR_STATUS_UP_CHANGE;
+	} else {
+		phy_data &= (~QCA808X_INTR_STATUS_UP_CHANGE);
+	}
+
+	if (intr_mask_flag & FAL_PHY_INTR_STATUS_DOWN_CHANGE) {
+		phy_data |= QCA808X_INTR_STATUS_DOWN_CHANGE;
+	} else {
+		phy_data &= (~QCA808X_INTR_STATUS_DOWN_CHANGE);
+	}
+
+	if (intr_mask_flag & FAL_PHY_INTR_SPEED_CHANGE) {
+		phy_data |= QCA808X_INTR_SPEED_CHANGE;
+	} else {
+		phy_data &= (~QCA808X_INTR_SPEED_CHANGE);
+	}
+
+	if (intr_mask_flag & FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE) {
+		phy_data |= QCA808X_INTR_LINK_SUCCESS_SG;
+	} else {
+		phy_data &= (~QCA808X_INTR_LINK_SUCCESS_SG);
+	}
+
+	if (intr_mask_flag & FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE) {
+		phy_data |= QCA808X_INTR_LINK_FAIL_SG;
+	} else {
+		phy_data &= (~QCA808X_INTR_LINK_FAIL_SG);
+	}
+
+	if (intr_mask_flag & FAL_PHY_INTR_WOL_STATUS) {
+		phy_data |= QCA808X_INTR_WOL;
+	} else {
+		phy_data &= (~QCA808X_INTR_WOL);
+	}
+
+	if (intr_mask_flag & FAL_PHY_INTR_POE_STATUS) {
+		phy_data |= QCA808X_INTR_POE;
+	} else {
+		phy_data &= (~QCA808X_INTR_POE);
+	}
+
+	rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_INTR_MASK, phy_data);
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get_intr_mask - Get interrupt mask with the
+* specified device.
+*/
+sw_error_t
+qca808x_phy_get_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_uint32_t * intr_mask_flag)
+{
+	a_uint16_t phy_data = 0;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_INTR_MASK);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	*intr_mask_flag = 0;
+	if (phy_data & QCA808X_INTR_STATUS_UP_CHANGE) {
+		*intr_mask_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE;
+	}
+
+	if (phy_data & QCA808X_INTR_STATUS_DOWN_CHANGE) {
+		*intr_mask_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE;
+	}
+
+	if (phy_data & QCA808X_INTR_SPEED_CHANGE) {
+		*intr_mask_flag |= FAL_PHY_INTR_SPEED_CHANGE;
+	}
+
+	if (phy_data & QCA808X_INTR_LINK_SUCCESS_SG) {
+		*intr_mask_flag |= FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE;
+	}
+
+	if (phy_data & QCA808X_INTR_LINK_FAIL_SG) {
+		*intr_mask_flag |= FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE;
+	}
+
+	if (phy_data & QCA808X_INTR_WOL) {
+		*intr_mask_flag |= FAL_PHY_INTR_WOL_STATUS;
+	}
+
+	if (phy_data & QCA808X_INTR_POE) {
+		*intr_mask_flag |= FAL_PHY_INTR_POE_STATUS;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get_intr_status - Get interrupt status with the
+* specified device.
+*/
+sw_error_t
+qca808x_phy_get_intr_status(a_uint32_t dev_id, a_uint32_t phy_id,
+			   a_uint32_t * intr_status_flag)
+{
+	a_uint16_t phy_data = 0;
+
+	phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_INTR_STATUS);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	*intr_status_flag = 0;
+	if (phy_data & QCA808X_INTR_STATUS_UP_CHANGE) {
+		*intr_status_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE;
+	}
+
+	if (phy_data & QCA808X_INTR_STATUS_DOWN_CHANGE) {
+		*intr_status_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE;
+	}
+
+	if (phy_data & QCA808X_INTR_SPEED_CHANGE) {
+		*intr_status_flag |= FAL_PHY_INTR_SPEED_CHANGE;
+	}
+
+	if (phy_data & QCA808X_INTR_LINK_SUCCESS_SG) {
+		*intr_status_flag |= FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE;
+	}
+
+	if (phy_data & QCA808X_INTR_LINK_FAIL_SG) {
+		*intr_status_flag |= FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE;
+	}
+
+	if (phy_data & QCA808X_INTR_WOL) {
+		*intr_status_flag |= FAL_PHY_INTR_WOL_STATUS;
+	}
+
+	if (phy_data & QCA808X_INTR_POE) {
+		*intr_status_flag |= FAL_PHY_INTR_POE_STATUS;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_set_counter - set counter status
+*
+* set counter  status
+*/
+sw_error_t
+qca808x_phy_set_counter(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+	a_uint16_t phy_data;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+					QCA808X_PHY_MMD7_COUNTER_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (enable == A_TRUE) {
+		phy_data |= QCA808X_PHY_FRAME_CHECK_EN;
+		phy_data |= QCA808X_PHY_XMIT_MAC_CNT_SELFCLR;
+	} else {
+		phy_data &= ~QCA808X_PHY_FRAME_CHECK_EN;
+		phy_data &= ~QCA808X_PHY_XMIT_MAC_CNT_SELFCLR;
+	}
+
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+			     QCA808X_PHY_MMD7_COUNTER_CTRL, phy_data);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get_counter_status - get counter status
+*
+* set counter status
+*/
+sw_error_t
+qca808x_phy_get_counter(a_uint32_t dev_id, a_uint32_t phy_id,
+			 a_bool_t * enable)
+{
+	a_uint16_t phy_data;
+
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+					QCA808X_PHY_MMD7_COUNTER_CTRL);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+
+	if (phy_data & QCA808X_PHY_FRAME_CHECK_EN) {
+		*enable = A_TRUE;
+	} else {
+		*enable = A_FALSE;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_show show counter statistics
+*
+* show counter statistics
+*/
+sw_error_t
+qca808x_phy_show_counter(a_uint32_t dev_id, a_uint32_t phy_id,
+			 fal_port_counter_info_t * counter_infor)
+{
+	a_uint16_t ingress_high_counter = 0;
+	a_uint16_t ingress_low_counter = 0;
+	a_uint16_t egress_high_counter = 0;
+	a_uint16_t egress_low_counter = 0;
+
+	ingress_high_counter = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+					QCA808X_PHY_MMD7_INGRESS_COUNTER_HIGH);
+	ingress_low_counter = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+					QCA808X_PHY_MMD7_INGRESS_COUNTER_LOW);
+	counter_infor->RxGoodFrame = (ingress_high_counter << 16 ) | ingress_low_counter;
+	counter_infor->RxBadCRC = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+					QCA808X_PHY_MMD7_INGRESS_ERROR_COUNTER);
+
+	egress_high_counter = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+					QCA808X_PHY_MMD7_EGRESS_COUNTER_HIGH);
+	egress_low_counter = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+					QCA808X_PHY_MMD7_EGRESS_COUNTER_LOW);
+	counter_infor->TxGoodFrame = (egress_high_counter << 16 ) | egress_low_counter;
+	counter_infor->TxBadCRC = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+					QCA808X_PHY_MMD7_EGRESS_ERROR_COUNTER);
+
+	return SW_OK;
+}
+#endif
+/******************************************************************************
+*
+* qca808x_phy_set_eee_advertisement
+*
+* set eee advertisement
+*/
+sw_error_t
+qca808x_phy_set_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t adv)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+				       QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL);
+	phy_data &= ~(QCA808X_PHY_EEE_ADV_100M | QCA808X_PHY_EEE_ADV_1000M);
+
+	if (adv & FAL_PHY_EEE_100BASE_T) {
+		phy_data |= QCA808X_PHY_EEE_ADV_100M;
+	}
+	if (adv & FAL_PHY_EEE_1000BASE_T) {
+		phy_data |= QCA808X_PHY_EEE_ADV_1000M;
+	}
+
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+		     QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data);
+
+	rv = qca808x_phy_restart_autoneg(dev_id, phy_id);
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_get_eee_advertisement
+*
+* get eee advertisement
+*/
+sw_error_t
+qca808x_phy_get_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *adv)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	*adv = 0;
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+				       QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL);
+
+	if (phy_data & QCA808X_PHY_EEE_ADV_100M) {
+		*adv |= FAL_PHY_EEE_100BASE_T;
+	}
+	if (phy_data & QCA808X_PHY_EEE_ADV_1000M) {
+		*adv |= FAL_PHY_EEE_1000BASE_T;
+	}
+
+	return rv;
+}
+/******************************************************************************
+*
+* qca808x_phy_get_eee_partner_advertisement
+*
+* get eee partner advertisement
+*/
+sw_error_t
+qca808x_phy_get_eee_partner_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *adv)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	*adv = 0;
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+				       QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_PARTNER);
+
+	if (phy_data & QCA808X_PHY_EEE_PARTNER_ADV_100M) {
+		*adv |= FAL_PHY_EEE_100BASE_T;
+	}
+	if (phy_data & QCA808X_PHY_EEE_PARTNER_ADV_1000M) {
+		*adv |= FAL_PHY_EEE_1000BASE_T;
+	}
+
+	return rv;
+}
+/******************************************************************************
+*
+* qca808x_phy_get_eee_capability
+*
+* get eee capability
+*/
+sw_error_t
+qca808x_phy_get_eee_cap(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *cap)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	*cap = 0;
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+				       QCA808X_PHY_MMD3_ADDR_8023AZ_EEE_CAPABILITY);
+
+	if (phy_data & QCA808X_PHY_EEE_CAPABILITY_100M) {
+		*cap |= FAL_PHY_EEE_100BASE_T;
+	}
+	if (phy_data & QCA808X_PHY_EEE_CAPABILITY_1000M) {
+		*cap |= FAL_PHY_EEE_1000BASE_T;
+	}
+
+	return rv;
+}
+/******************************************************************************
+*
+* qca808x_phy_get_eee_status
+*
+* get eee status
+*/
+sw_error_t
+qca808x_phy_get_eee_status(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t *status)
+{
+	a_uint16_t phy_data = 0;
+	sw_error_t rv = SW_OK;
+
+	*status = 0;
+	phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+				       QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_STATUS);
+
+	if (phy_data & QCA808X_PHY_EEE_STATUS_100M) {
+		*status |= FAL_PHY_EEE_100BASE_T;
+	}
+	if (phy_data & QCA808X_PHY_EEE_STATUS_1000M) {
+		*status |= FAL_PHY_EEE_1000BASE_T;
+	}
+
+	return rv;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_led_init - set led behavior
+*
+* set led behavior
+*/
+static sw_error_t
+qca808x_phy_led_init(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	sw_error_t rv = SW_OK;
+
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+			QCA808X_PHY_MMD7_LED_POLARITY_CTRL,
+				QCA808X_PHY_MMD7_LED_POLARITY_ACTIVE_HIGH);
+	SW_RTN_ON_ERROR(rv);
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+			QCA808X_PHY_MMD7_LED0_CTRL,
+				QCA808X_PHY_MMD7_LED0_CTRL_ENABLE);
+	SW_RTN_ON_ERROR(rv);
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+			QCA808X_PHY_MMD7_LED1_CTRL,
+				QCA808X_PHY_MMD7_LED1_CTRL_DISABLE);
+	SW_RTN_ON_ERROR(rv);
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+			QCA808X_PHY_MMD7_LED2_CTRL,
+				QCA808X_PHY_MMD7_LED2_CTRL_DISABLE);
+	SW_RTN_ON_ERROR(rv);
+
+	return rv;
+}
+
+static sw_error_t
+qca808x_phy_fast_retrain_cfg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+	sw_error_t rv = SW_OK;
+
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+		QCA808X_PHY_MMD7_AUTONEGOTIATION_CONTROL,
+		QCA808X_ADVERTISE_2500FULL |
+		QCA808X_PHY_FAST_RETRAIN_2500BT |
+		QCA808X_PHY_ADV_LOOP_TIMING);
+	SW_RTN_ON_ERROR(rv);
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+		QCA808X_PHY_MMD1_FAST_RETRAIN_STATUS_CTL,
+		QCA808X_PHY_FAST_RETRAIN_CTRL);
+	SW_RTN_ON_ERROR(rv);
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+		QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
+		QCA808X_PHY_MSE_THRESHOLD_20DB_VALUE);
+	SW_RTN_ON_ERROR(rv);
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+		QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
+		QCA808X_PHY_MSE_THRESHOLD_17DB_VALUE);
+	SW_RTN_ON_ERROR(rv);
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+		QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
+		QCA808X_PHY_MSE_THRESHOLD_27DB_VALUE);
+	SW_RTN_ON_ERROR(rv);
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+		QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
+		QCA808X_PHY_MSE_THRESHOLD_28DB_VALUE);
+	SW_RTN_ON_ERROR(rv);
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+		QCA808X_PHY_MMD7_ADDR_EEE_LP_ADVERTISEMENT,
+		QCA808X_PHY_EEE_ADV_THP);
+	SW_RTN_ON_ERROR(rv);
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+		QCA808X_PHY_MMD7_TOP_OPTION1,
+		QCA808X_PHY_TOP_OPTION1_DATA);
+	SW_RTN_ON_ERROR(rv);
+	/*adjust the threshold for link down*/
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+		0xa100, 0x9203);
+	SW_RTN_ON_ERROR(rv);
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+		0xa105, 0x8001);
+	SW_RTN_ON_ERROR(rv);
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+		0xa106, 0x1111);
+	SW_RTN_ON_ERROR(rv);
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+		0xa103, 0x1698);
+	SW_RTN_ON_ERROR(rv);
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+		0xa011, 0x5f85);
+	SW_RTN_ON_ERROR(rv);
+	rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+		0xa101, 0x48ad);
+
+	return rv;
+}
+
+void qca808x_phy_lock_init(void)
+{
+	static a_bool_t is_init = A_FALSE;
+
+	if(!is_init)
+	{
+		QCA808X_LOCKER_INIT;
+		is_init = A_TRUE;
+	}
+
+	return;
+}
+
+static sw_error_t
+qca808x_phy_adc_threshold_set(a_uint32_t dev_id, a_uint32_t phy_id,
+	a_uint32_t adc_thresold)
+{
+	sw_error_t rv = SW_OK;
+	a_uint16_t phy_data = 0;
+
+	phy_data = qca808x_phy_debug_read(dev_id, phy_id,
+		QCA808X_PHY_ADC_THRESHOLD);
+	PHY_RTN_ON_READ_ERROR(phy_data);
+	phy_data &= ~(BITS(0, 8));
+	rv = qca808x_phy_debug_write (dev_id, phy_id,
+		QCA808X_PHY_ADC_THRESHOLD, phy_data | adc_thresold);
+
+	return rv;
+}
+
+static sw_error_t
+qca808x_phy_hw_init(a_uint32_t dev_id,  a_uint32_t port_bmp)
+{
+	a_uint16_t phy_data = 0;
+	a_uint32_t port_id = 0, phy_addr = 0;
+	sw_error_t rv = SW_OK;
+
+	for (port_id = SSDK_PHYSICAL_PORT0; port_id < SW_MAX_NR_PORT; port_id ++)
+	{
+		if (port_bmp & (0x1 << port_id))
+		{
+			phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id);
+			/*enable vga when init napa to fix 8023az issue*/
+			phy_data = qca808x_phy_mmd_read(dev_id, phy_addr, QCA808X_PHY_MMD3_NUM,
+				QCA808X_PHY_MMD3_ADDR_CLD_CTRL7);
+			phy_data &= (~QCA808X_PHY_8023AZ_AFE_CTRL_MASK);
+			phy_data |= QCA808X_PHY_8023AZ_AFE_EN;
+			rv = qca808x_phy_mmd_write(dev_id, phy_addr, QCA808X_PHY_MMD3_NUM,
+				QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, phy_data);
+			SW_RTN_ON_ERROR(rv);
+			/*set napa led pin behavior on HK board*/
+			rv = qca808x_phy_led_init(dev_id, phy_addr);
+			SW_RTN_ON_ERROR(rv);
+			/*special configuration for AZ under 1G speed mode*/
+			phy_data = QCA808X_PHY_MMD3_AZ_TRAINING_VAL;
+			rv = qca808x_phy_mmd_write(dev_id, phy_addr, QCA808X_PHY_MMD3_NUM,
+				QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, phy_data);
+			SW_RTN_ON_ERROR(rv);
+			if(qca808x_phy_2500caps(dev_id, phy_addr) == A_TRUE)
+			{
+				/*config the fast retrain*/
+				rv = qca808x_phy_fast_retrain_cfg(dev_id, phy_addr);
+				SW_RTN_ON_ERROR(rv);
+				/*enable seed and configure ramdom seed in order that napa can be
+					as slave easier*/
+				rv = qca808x_phy_ms_seed_enable(dev_id, phy_addr, A_TRUE);
+				SW_RTN_ON_ERROR(rv);
+				rv = qca808x_phy_ms_random_seed_set(dev_id, phy_addr);
+				SW_RTN_ON_ERROR(rv);
+			}
+			/*set adc threshold as 100mv for 10M*/
+			rv = qca808x_phy_adc_threshold_set(dev_id, phy_addr,
+				QCA808X_PHY_ADC_THRESHOLD_100MV);
+			SW_RTN_ON_ERROR(rv);
+		}
+	}
+
+	return rv;
+}
+
+static sw_error_t qca808x_phy_api_ops_init(void)
+{
+	sw_error_t  ret = SW_OK;
+	hsl_phy_ops_t *qca808x_phy_api_ops = NULL;
+
+	qca808x_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL);
+	if (qca808x_phy_api_ops == NULL) {
+		SSDK_ERROR("qca808x phy ops kzalloc failed!\n");
+		return -ENOMEM;
+	}
+
+	phy_api_ops_init(QCA808X_PHY_CHIP);
+
+	qca808x_phy_api_ops->phy_reg_write = qca808x_phy_reg_write;
+	qca808x_phy_api_ops->phy_reg_read = qca808x_phy_reg_read;
+	qca808x_phy_api_ops->phy_debug_write = qca808x_phy_debug_write;
+	qca808x_phy_api_ops->phy_debug_read = qca808x_phy_debug_read;
+	qca808x_phy_api_ops->phy_mmd_write = qca808x_phy_mmd_write;
+	qca808x_phy_api_ops->phy_mmd_read = qca808x_phy_mmd_read;
+	qca808x_phy_api_ops->phy_get_status = qca808x_phy_get_status;
+	qca808x_phy_api_ops->phy_speed_get = qca808x_phy_get_speed;
+	qca808x_phy_api_ops->phy_speed_set = qca808x_phy_set_speed;
+	qca808x_phy_api_ops->phy_duplex_get = qca808x_phy_get_duplex;
+	qca808x_phy_api_ops->phy_duplex_set = qca808x_phy_set_duplex;
+	qca808x_phy_api_ops->phy_autoneg_enable_set = qca808x_phy_enable_autoneg;
+	qca808x_phy_api_ops->phy_restart_autoneg = qca808x_phy_restart_autoneg;
+	qca808x_phy_api_ops->phy_autoneg_status_get = qca808x_phy_autoneg_status;
+	qca808x_phy_api_ops->phy_autoneg_adv_set = qca808x_phy_set_autoneg_adv;
+	qca808x_phy_api_ops->phy_autoneg_adv_get = qca808x_phy_get_autoneg_adv;
+	qca808x_phy_api_ops->phy_link_status_get = qca808x_phy_get_link_status;
+	qca808x_phy_api_ops->phy_reset = qca808x_phy_reset;
+#ifndef IN_PORTCONTROL_MINI
+	qca808x_phy_api_ops->phy_cdt = qca808x_phy_cdt;
+	qca808x_phy_api_ops->phy_mdix_set = qca808x_phy_set_mdix;
+	qca808x_phy_api_ops->phy_mdix_get = qca808x_phy_get_mdix;
+	qca808x_phy_api_ops->phy_mdix_status_get = qca808x_phy_get_mdix_status;
+	qca808x_phy_api_ops->phy_local_loopback_set = qca808x_phy_set_local_loopback;
+	qca808x_phy_api_ops->phy_local_loopback_get = qca808x_phy_get_local_loopback;
+	qca808x_phy_api_ops->phy_remote_loopback_set = qca808x_phy_set_remote_loopback;
+	qca808x_phy_api_ops->phy_remote_loopback_get = qca808x_phy_get_remote_loopback;
+#endif
+	qca808x_phy_api_ops->phy_id_get = qca808x_phy_get_phy_id;
+	qca808x_phy_api_ops->phy_power_off = qca808x_phy_poweroff;
+	qca808x_phy_api_ops->phy_power_on = qca808x_phy_poweron;
+#ifndef IN_PORTCONTROL_MINI
+	qca808x_phy_api_ops->phy_8023az_set = qca808x_phy_set_8023az;
+	qca808x_phy_api_ops->phy_8023az_get = qca808x_phy_get_8023az;
+	qca808x_phy_api_ops->phy_hibernation_set = qca808x_phy_set_hibernate;
+	qca808x_phy_api_ops->phy_hibernation_get = qca808x_phy_get_hibernate;
+	qca808x_phy_api_ops->phy_magic_frame_mac_set = qca808x_phy_set_magic_frame_mac;
+	qca808x_phy_api_ops->phy_magic_frame_mac_get = qca808x_phy_get_magic_frame_mac;
+	qca808x_phy_api_ops->phy_wol_status_set = qca808x_phy_set_wol_status;
+	qca808x_phy_api_ops->phy_wol_status_get = qca808x_phy_get_wol_status;
+#endif
+	qca808x_phy_api_ops->phy_interface_mode_set = qca808x_phy_interface_set_mode;
+	qca808x_phy_api_ops->phy_interface_mode_get = qca808x_phy_interface_get_mode;
+	qca808x_phy_api_ops->phy_interface_mode_status_get = qca808x_phy_interface_get_mode_status;
+#ifndef IN_PORTCONTROL_MINI
+	qca808x_phy_api_ops->phy_intr_mask_set = qca808x_phy_set_intr_mask;
+	qca808x_phy_api_ops->phy_intr_mask_get = qca808x_phy_get_intr_mask;
+	qca808x_phy_api_ops->phy_intr_status_get = qca808x_phy_get_intr_status;
+	qca808x_phy_api_ops->phy_counter_set = qca808x_phy_set_counter;
+	qca808x_phy_api_ops->phy_counter_get = qca808x_phy_get_counter;
+	qca808x_phy_api_ops->phy_counter_show = qca808x_phy_show_counter;
+#endif
+	qca808x_phy_api_ops->phy_eee_adv_set = qca808x_phy_set_eee_adv;
+	qca808x_phy_api_ops->phy_eee_adv_get = qca808x_phy_get_eee_adv;
+	qca808x_phy_api_ops->phy_eee_partner_adv_get = qca808x_phy_get_eee_partner_adv;
+	qca808x_phy_api_ops->phy_eee_cap_get = qca808x_phy_get_eee_cap;
+	qca808x_phy_api_ops->phy_eee_status_get = qca808x_phy_get_eee_status;
+#ifdef IN_LED
+	qca808x_phy_led_api_ops_init(qca808x_phy_api_ops);
+#endif
+/*qca808x_end*/
+#if defined(IN_PTP)
+	qca808x_phy_ptp_api_ops_init(&qca808x_phy_api_ops->phy_ptp_ops);
+#endif
+/*qca808x_start*/
+	ret = hsl_phy_api_ops_register(QCA808X_PHY_CHIP, qca808x_phy_api_ops);
+
+	if (ret == SW_OK) {
+		SSDK_INFO("qca probe qca808x phy driver succeeded!\n");
+	} else {
+		SSDK_ERROR("qca probe qca808x phy driver failed! (code: %d)\n", ret);
+	}
+
+	return ret;
+}
+
+/******************************************************************************
+*
+* qca808x_phy_init -
+*
+*/
+int qca808x_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp)
+{
+/*qca808x_end*/
+	a_uint32_t port_id = 0;
+/*qca808x_start*/
+	a_int32_t ret = 0;
+
+	if(phy_ops_flag == A_FALSE &&
+			qca808x_phy_api_ops_init() == SW_OK) {
+		qca808x_phy_lock_init();
+		phy_ops_flag = A_TRUE;
+	}
+	qca808x_phy_hw_init(dev_id, port_bmp);
+
+/*qca808x_end*/
+	if(phy_dev_drv_init_flag == A_FALSE)
+	{
+		for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++)
+		{
+			if (port_bmp & (0x1 << port_id)) {
+				qca808x_phydev_init(dev_id, port_id);
+			}
+		}
+		ret = qca808x_phy_driver_register();
+		phy_dev_drv_init_flag = A_TRUE;
+	}
+/*qca808x_start*/
+	return ret;
+}
+
+void qca808x_phy_exit(a_uint32_t dev_id, a_uint32_t port_bmp)
+{
+/*qca808x_end*/
+	a_uint32_t port_id = 0;
+
+	qca808x_phy_driver_unregister();
+	for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++)
+	{
+		if (port_bmp & (0x1 << port_id)) {
+			qca808x_phydev_deinit(dev_id, port_id);
+		}
+	}
+/*qca808x_start*/
+}
+/*qca808x_end*/
diff --git a/qca-ssdk/src/hsl/phy/qca808x_ptp.c b/qca-ssdk/src/hsl/phy/qca808x_ptp.c
new file mode 100755
index 0000000..c1e3e65
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/qca808x_ptp.c
@@ -0,0 +1,2843 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "sw.h"
+#include "hsl_api.h"
+#include "hsl.h"
+#include "hsl_phy.h"
+#include "ssdk_plat.h"
+#include "qca808x_phy.h"
+#include "qca808x_ptp_reg.h"
+#include "qca808x_ptp_api.h"
+#include "qca808x_ptp.h"
+
+sw_error_t
+qca808x_phy_ptp_config_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_config_t *config)
+{
+	union ptp_main_conf_reg_u ptp_main_conf_reg = {0};
+	union ptp_misc_config_reg_u ptp_misc_config_reg = {0};
+	union ptp_backup_reg_u ptp_backup_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_backup_reg_get(dev_id, phy_id, &ptp_backup_reg));
+	if (config->ptp_en == A_TRUE)
+	{
+		ptp_main_conf_reg.bf.ptp_bypass = PTP_REG_BIT_FALSE;
+		ptp_main_conf_reg.bf.disable_1588_phy = PTP_REG_BIT_FALSE;
+	}
+	else
+	{
+		ptp_main_conf_reg.bf.ptp_bypass = PTP_REG_BIT_TRUE;
+		ptp_main_conf_reg.bf.disable_1588_phy = PTP_REG_BIT_TRUE;
+	}
+	if (config->clock_mode == FAL_OC_CLOCK_MODE || config->clock_mode == FAL_BC_CLOCK_MODE)
+	{
+		if (config->step_mode == FAL_ONE_STEP_MODE)
+		{
+			ptp_main_conf_reg.bf.ptp_clock_mode =
+				PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_OC_ONE_STEP;
+		}
+		else
+		{
+			ptp_main_conf_reg.bf.ptp_clock_mode =
+				PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_OC_TWO_STEP;
+		}
+	}
+	else
+	{
+		if (config->clock_mode == FAL_P2PTC_CLOCK_MODE)
+		{
+			ptp_backup_reg.bf.p2p_tc_en = PTP_REG_BIT_TRUE;
+		}
+		else
+		{
+			ptp_backup_reg.bf.p2p_tc_en = PTP_REG_BIT_FALSE;
+		}
+
+		if (config->step_mode == FAL_ONE_STEP_MODE &&
+		    ptp_misc_config_reg.bf.embed_ingress_time_en == PTP_REG_BIT_TRUE)
+		{
+			ptp_misc_config_reg.bf.tc_offload = PTP_REG_BIT_TRUE;
+		}
+		else
+		{
+			ptp_misc_config_reg.bf.tc_offload = PTP_REG_BIT_FALSE;
+		}
+
+		if (config->step_mode == FAL_ONE_STEP_MODE)
+		{
+			ptp_main_conf_reg.bf.ptp_clock_mode =
+				PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_TC_ONE_STEP;
+		}
+		else
+		{
+			ptp_main_conf_reg.bf.ptp_clock_mode =
+				PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_TC_TWO_STEP;
+		}
+	}
+	if (config->step_mode == FAL_AUTO_MODE)
+	{
+		ptp_misc_config_reg.bf.pkt_one_step_en = PTP_REG_BIT_TRUE;
+	}
+	else
+	{
+		ptp_misc_config_reg.bf.pkt_one_step_en = PTP_REG_BIT_FALSE;
+	}
+#if defined(IN_LINUX_STD_PTP)
+	qca808x_ptp_clock_mode_config(dev_id, phy_id, config->clock_mode, config->step_mode);
+#endif
+	SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &ptp_main_conf_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &ptp_misc_config_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_backup_reg_set(dev_id, phy_id, &ptp_backup_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_config_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_config_t *config)
+{
+	union ptp_main_conf_reg_u ptp_main_conf_reg = {0};
+	union ptp_misc_config_reg_u ptp_misc_config_reg = {0};
+	union ptp_backup_reg_u ptp_backup_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_backup_reg_get(dev_id, phy_id, &ptp_backup_reg));
+	if (ptp_main_conf_reg.bf.ptp_bypass == PTP_REG_BIT_FALSE &&
+			ptp_main_conf_reg.bf.disable_1588_phy == PTP_REG_BIT_FALSE)
+	{
+		config->ptp_en = A_TRUE;
+	}
+	if (ptp_main_conf_reg.bf.ptp_clock_mode ==
+			PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_OC_TWO_STEP)
+	{
+		config->clock_mode = FAL_OC_CLOCK_MODE;
+		config->step_mode = FAL_TWO_STEP_MODE;
+	}
+	else if (ptp_main_conf_reg.bf.ptp_clock_mode ==
+			PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_OC_ONE_STEP)
+	{
+		config->clock_mode = FAL_OC_CLOCK_MODE;
+		config->step_mode = FAL_ONE_STEP_MODE;
+	}
+	else if (ptp_main_conf_reg.bf.ptp_clock_mode ==
+			PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_TC_TWO_STEP)
+	{
+		if (ptp_backup_reg.bf.p2p_tc_en == PTP_REG_BIT_TRUE)
+		{
+			config->clock_mode = FAL_P2PTC_CLOCK_MODE;
+		}
+		else
+		{
+			config->clock_mode = FAL_E2ETC_CLOCK_MODE;
+		}
+
+		config->step_mode = FAL_TWO_STEP_MODE;
+	}
+	else
+	{
+		if (ptp_backup_reg.bf.p2p_tc_en == PTP_REG_BIT_TRUE)
+		{
+			config->clock_mode = FAL_P2PTC_CLOCK_MODE;
+		}
+		else
+		{
+			config->clock_mode = FAL_E2ETC_CLOCK_MODE;
+		}
+
+		config->step_mode = FAL_ONE_STEP_MODE;
+	}
+	if (ptp_misc_config_reg.bf.pkt_one_step_en == PTP_REG_BIT_TRUE)
+	{
+		config->step_mode = FAL_AUTO_MODE;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_reference_clock_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_reference_clock_t ref_clock)
+{
+	union ptp_main_conf_reg_u ptp_main_conf_reg = {0};
+	union ptp_rtc_clk_reg_u ptp_rtc_clk_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_clk_reg_get(dev_id, phy_id, &ptp_rtc_clk_reg));
+	if (ref_clock == FAL_REF_CLOCK_LOCAL)
+	{
+		ptp_main_conf_reg.bf.ptp_clk_sel = PTP_REG_BIT_FALSE;
+		ptp_rtc_clk_reg.bf.rtc_clk_selection = PTP_REG_BIT_FALSE;
+	}
+	else if (ref_clock == FAL_REF_CLOCK_SYNCE)
+	{
+		ptp_main_conf_reg.bf.ptp_clk_sel = PTP_REG_BIT_TRUE;
+		ptp_rtc_clk_reg.bf.rtc_clk_selection = PTP_REG_BIT_FALSE;
+	}
+	else
+	{
+		ptp_main_conf_reg.bf.ptp_clk_sel = PTP_REG_BIT_FALSE;
+		ptp_rtc_clk_reg.bf.rtc_clk_selection = PTP_REG_BIT_TRUE;
+	}
+	SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &ptp_main_conf_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_clk_reg_set(dev_id, phy_id, &ptp_rtc_clk_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_reference_clock_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_reference_clock_t *ref_clock)
+{
+	union ptp_main_conf_reg_u ptp_main_conf_reg = {0};
+	union ptp_rtc_clk_reg_u ptp_rtc_clk_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_clk_reg_get(dev_id, phy_id, &ptp_rtc_clk_reg));
+	if (ptp_main_conf_reg.bf.ptp_clk_sel == PTP_REG_BIT_FALSE &&
+			ptp_rtc_clk_reg.bf.rtc_clk_selection == PTP_REG_BIT_FALSE)
+	{
+		*ref_clock = FAL_REF_CLOCK_LOCAL;
+	}
+	else if (ptp_main_conf_reg.bf.ptp_clk_sel == PTP_REG_BIT_TRUE &&
+			ptp_rtc_clk_reg.bf.rtc_clk_selection == PTP_REG_BIT_FALSE)
+	{
+		*ref_clock = FAL_REF_CLOCK_SYNCE;
+	}
+	else
+	{
+		*ref_clock = FAL_REF_CLOCK_EXTERNAL;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_rx_timestamp_mode_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_rx_timestamp_mode_t ts_mode)
+{
+	union ptp_main_conf_reg_u ptp_main_conf_reg = {0};
+	union ptp_misc_config_reg_u ptp_misc_config_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg));
+	if (ts_mode == FAL_RX_TS_MDIO)
+	{
+		ptp_main_conf_reg.bf.ts_attach_mode = PTP_REG_BIT_FALSE;
+		ptp_main_conf_reg.bf.ipv6_embed_force_checksum_zero = PTP_REG_BIT_FALSE;
+		ptp_misc_config_reg.bf.embed_ingress_time_en = PTP_REG_BIT_FALSE;
+		ptp_misc_config_reg.bf.cf_from_pkt_en = PTP_REG_BIT_TRUE;
+	}
+	else
+	{
+		ptp_main_conf_reg.bf.ts_attach_mode = PTP_REG_BIT_FALSE;
+		ptp_main_conf_reg.bf.ipv6_embed_force_checksum_zero = PTP_REG_BIT_TRUE;
+		ptp_misc_config_reg.bf.embed_ingress_time_en = PTP_REG_BIT_TRUE;
+		ptp_misc_config_reg.bf.cf_from_pkt_en = PTP_REG_BIT_FALSE;
+	}
+	SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &ptp_main_conf_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &ptp_misc_config_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_rx_timestamp_mode_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_rx_timestamp_mode_t *ts_mode)
+{
+	union ptp_main_conf_reg_u ptp_main_conf_reg = {0};
+	union ptp_misc_config_reg_u ptp_misc_config_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg));
+	if (ptp_main_conf_reg.bf.ts_attach_mode == PTP_REG_BIT_FALSE &&
+			ptp_misc_config_reg.bf.embed_ingress_time_en == PTP_REG_BIT_FALSE)
+	{
+		*ts_mode = FAL_RX_TS_MDIO;
+	}
+	else if (ptp_main_conf_reg.bf.ts_attach_mode == PTP_REG_BIT_FALSE &&
+			ptp_misc_config_reg.bf.embed_ingress_time_en == PTP_REG_BIT_TRUE)
+	{
+		*ts_mode = FAL_RX_TS_EMBED;
+	}
+	else
+	{
+		return SW_BAD_VALUE;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_rx_timestamp0_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time)
+{
+	union ptp_rx_seqid0_reg_u ptp_rx_seqid0_reg = {0};
+
+	union ptp_rx_portid0_0_reg_u ptp_rx_portid0_0_reg = {0};
+	union ptp_rx_portid0_1_reg_u ptp_rx_portid0_1_reg = {0};
+	union ptp_rx_portid0_2_reg_u ptp_rx_portid0_2_reg = {0};
+	union ptp_rx_portid0_3_reg_u ptp_rx_portid0_3_reg = {0};
+	union ptp_rx_portid0_4_reg_u ptp_rx_portid0_4_reg = {0};
+	union ptp_rx_ts0_0_reg_u ptp_rx_ts0_0_reg = {0};
+	union ptp_rx_ts0_1_reg_u ptp_rx_ts0_1_reg = {0};
+	union ptp_rx_ts0_2_reg_u ptp_rx_ts0_2_reg = {0};
+	union ptp_rx_ts0_3_reg_u ptp_rx_ts0_3_reg = {0};
+	union ptp_rx_ts0_4_reg_u ptp_rx_ts0_4_reg = {0};
+	union ptp_rx_ts0_5_reg_u ptp_rx_ts0_5_reg = {0};
+	union ptp_rx_ts0_6_reg_u ptp_rx_ts0_6_reg = {0};
+
+	a_uint64_t clock_id;
+	a_uint32_t port_num, msgtype;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_seqid0_reg_get(dev_id, phy_id, &ptp_rx_seqid0_reg));
+	if (pkt_info->sequence_id != ptp_rx_seqid0_reg.bf.rx_seqid)
+	{
+		return SW_NOT_FOUND;
+	}
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid0_0_reg_get(dev_id,
+				phy_id, &ptp_rx_portid0_0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid0_1_reg_get(dev_id,
+				phy_id, &ptp_rx_portid0_1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid0_2_reg_get(dev_id,
+				phy_id, &ptp_rx_portid0_2_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid0_3_reg_get(dev_id,
+				phy_id, &ptp_rx_portid0_3_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid0_4_reg_get(dev_id,
+				phy_id, &ptp_rx_portid0_4_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts0_0_reg_get(dev_id,
+				phy_id, &ptp_rx_ts0_0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts0_1_reg_get(dev_id,
+				phy_id, &ptp_rx_ts0_1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts0_2_reg_get(dev_id,
+				phy_id, &ptp_rx_ts0_2_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts0_3_reg_get(dev_id,
+				phy_id, &ptp_rx_ts0_3_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts0_4_reg_get(dev_id,
+				phy_id, &ptp_rx_ts0_4_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts0_5_reg_get(dev_id,
+				phy_id, &ptp_rx_ts0_5_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts0_6_reg_get(dev_id,
+				phy_id, &ptp_rx_ts0_6_reg));
+
+	clock_id = ((a_uint64_t)ptp_rx_portid0_0_reg.bf.rx_portid << 48) |
+		((a_uint64_t)ptp_rx_portid0_1_reg.bf.rx_portid << 32) |
+		((a_uint64_t)ptp_rx_portid0_2_reg.bf.rx_portid << 16) |
+		ptp_rx_portid0_3_reg.bf.rx_portid;
+	port_num = ptp_rx_portid0_4_reg.bf.rx_portid;
+	msgtype = ptp_rx_ts0_5_reg.bf.rx_msg_type;
+
+	if (pkt_info->clock_identify == clock_id &&
+			pkt_info->port_number == port_num &&
+			pkt_info->msg_type == msgtype)
+	{
+		time->seconds =
+			((a_int64_t)ptp_rx_ts0_0_reg.bf.rx_ts_sec << 32) |
+			((a_int64_t)ptp_rx_ts0_1_reg.bf.rx_ts_sec << 16) |
+			ptp_rx_ts0_2_reg.bf.rx_ts_sec;
+		time->nanoseconds =
+			((a_int32_t)ptp_rx_ts0_3_reg.bf.rx_ts_nsec << 16) |
+			ptp_rx_ts0_4_reg.bf.rx_ts_nsec;
+		time->fracnanoseconds =
+			((a_int32_t)ptp_rx_ts0_5_reg.bf.rx_ts_nfsec << 8) |
+			ptp_rx_ts0_6_reg.bf.rx_ts_nfsec;
+
+		return SW_OK;
+	}
+	return SW_NOT_FOUND;
+}
+
+sw_error_t
+qca808x_phy_ptp_rx_timestamp1_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time)
+{
+	union ptp_rx_seqid1_reg_u ptp_rx_seqid1_reg = {0};
+
+	union ptp_rx_portid1_0_reg_u ptp_rx_portid1_0_reg = {0};
+	union ptp_rx_portid1_1_reg_u ptp_rx_portid1_1_reg = {0};
+	union ptp_rx_portid1_2_reg_u ptp_rx_portid1_2_reg = {0};
+	union ptp_rx_portid1_3_reg_u ptp_rx_portid1_3_reg = {0};
+	union ptp_rx_portid1_4_reg_u ptp_rx_portid1_4_reg = {0};
+	union ptp_rx_ts1_0_reg_u ptp_rx_ts1_0_reg = {0};
+	union ptp_rx_ts1_1_reg_u ptp_rx_ts1_1_reg = {0};
+	union ptp_rx_ts1_2_reg_u ptp_rx_ts1_2_reg = {0};
+	union ptp_rx_ts1_3_reg_u ptp_rx_ts1_3_reg = {0};
+	union ptp_rx_ts1_4_reg_u ptp_rx_ts1_4_reg = {0};
+	union ptp_rx_ts1_5_reg_u ptp_rx_ts1_5_reg = {0};
+	union ptp_rx_ts1_6_reg_u ptp_rx_ts1_6_reg = {0};
+
+	a_uint64_t clock_id;
+	a_uint32_t port_num, msgtype;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_seqid1_reg_get(dev_id, phy_id, &ptp_rx_seqid1_reg));
+	if (pkt_info->sequence_id != ptp_rx_seqid1_reg.bf.rx_seqid)
+	{
+		return SW_NOT_FOUND;
+	}
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid1_0_reg_get(dev_id,
+				phy_id, &ptp_rx_portid1_0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid1_1_reg_get(dev_id,
+				phy_id, &ptp_rx_portid1_1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid1_2_reg_get(dev_id,
+				phy_id, &ptp_rx_portid1_2_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid1_3_reg_get(dev_id,
+				phy_id, &ptp_rx_portid1_3_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid1_4_reg_get(dev_id,
+				phy_id, &ptp_rx_portid1_4_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts1_0_reg_get(dev_id,
+				phy_id, &ptp_rx_ts1_0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts1_1_reg_get(dev_id,
+				phy_id, &ptp_rx_ts1_1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts1_2_reg_get(dev_id,
+				phy_id, &ptp_rx_ts1_2_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts1_3_reg_get(dev_id,
+				phy_id, &ptp_rx_ts1_3_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts1_4_reg_get(dev_id,
+				phy_id, &ptp_rx_ts1_4_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts1_5_reg_get(dev_id,
+				phy_id, &ptp_rx_ts1_5_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts1_6_reg_get(dev_id,
+				phy_id, &ptp_rx_ts1_6_reg));
+
+	clock_id = ((a_uint64_t)ptp_rx_portid1_0_reg.bf.rx_portid << 48) |
+		((a_uint64_t)ptp_rx_portid1_1_reg.bf.rx_portid << 32) |
+		((a_uint64_t)ptp_rx_portid1_2_reg.bf.rx_portid << 16) |
+		ptp_rx_portid1_3_reg.bf.rx_portid;
+
+	port_num = ptp_rx_portid1_4_reg.bf.rx_portid;
+	msgtype = ptp_rx_ts1_5_reg.bf.rx_msg_type;
+	if (pkt_info->clock_identify == clock_id &&
+			pkt_info->port_number == port_num &&
+			pkt_info->msg_type == msgtype)
+	{
+		time->seconds =
+			((a_int64_t)ptp_rx_ts1_0_reg.bf.rx_ts_sec << 32) |
+			((a_int64_t)ptp_rx_ts1_1_reg.bf.rx_ts_sec << 16) |
+			ptp_rx_ts1_2_reg.bf.rx_ts_sec;
+		time->nanoseconds =
+			((a_int32_t)ptp_rx_ts1_3_reg.bf.rx_ts_nsec << 16) |
+			ptp_rx_ts1_4_reg.bf.rx_ts_nsec;
+		time->fracnanoseconds =
+			((a_int32_t)ptp_rx_ts1_5_reg.bf.rx_ts_nfsec << 8) |
+			ptp_rx_ts1_6_reg.bf.rx_ts_nfsec;
+
+		return SW_OK;
+	}
+	return SW_NOT_FOUND;
+}
+
+sw_error_t
+qca808x_phy_ptp_rx_timestamp2_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time)
+{
+	union ptp_rx_seqid2_reg_u ptp_rx_seqid2_reg = {0};
+	union ptp_rx_portid2_0_reg_u ptp_rx_portid2_0_reg = {0};
+	union ptp_rx_portid2_1_reg_u ptp_rx_portid2_1_reg = {0};
+	union ptp_rx_portid2_2_reg_u ptp_rx_portid2_2_reg = {0};
+	union ptp_rx_portid2_3_reg_u ptp_rx_portid2_3_reg = {0};
+	union ptp_rx_portid2_4_reg_u ptp_rx_portid2_4_reg = {0};
+	union ptp_rx_ts2_0_reg_u ptp_rx_ts2_0_reg = {0};
+	union ptp_rx_ts2_1_reg_u ptp_rx_ts2_1_reg = {0};
+	union ptp_rx_ts2_2_reg_u ptp_rx_ts2_2_reg = {0};
+	union ptp_rx_ts2_3_reg_u ptp_rx_ts2_3_reg = {0};
+	union ptp_rx_ts2_4_reg_u ptp_rx_ts2_4_reg = {0};
+	union ptp_rx_ts2_5_reg_u ptp_rx_ts2_5_reg = {0};
+	union ptp_rx_ts2_6_reg_u ptp_rx_ts2_6_reg = {0};
+
+	a_uint64_t clock_id;
+	a_uint32_t port_num, msgtype;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_seqid2_reg_get(dev_id, phy_id, &ptp_rx_seqid2_reg));
+	if (pkt_info->sequence_id != ptp_rx_seqid2_reg.bf.rx_seqid)
+	{
+		return SW_NOT_FOUND;
+	}
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid2_0_reg_get(dev_id,
+				phy_id, &ptp_rx_portid2_0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid2_1_reg_get(dev_id,
+				phy_id, &ptp_rx_portid2_1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid2_2_reg_get(dev_id,
+				phy_id, &ptp_rx_portid2_2_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid2_3_reg_get(dev_id,
+				phy_id, &ptp_rx_portid2_3_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid2_4_reg_get(dev_id,
+				phy_id, &ptp_rx_portid2_4_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts2_0_reg_get(dev_id,
+				phy_id, &ptp_rx_ts2_0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts2_1_reg_get(dev_id,
+				phy_id, &ptp_rx_ts2_1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts2_2_reg_get(dev_id,
+				phy_id, &ptp_rx_ts2_2_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts2_3_reg_get(dev_id,
+				phy_id, &ptp_rx_ts2_3_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts2_4_reg_get(dev_id,
+				phy_id, &ptp_rx_ts2_4_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts2_5_reg_get(dev_id,
+				phy_id, &ptp_rx_ts2_5_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts2_6_reg_get(dev_id,
+				phy_id, &ptp_rx_ts2_6_reg));
+
+	clock_id = ((a_uint64_t)ptp_rx_portid2_0_reg.bf.rx_portid << 48) |
+		((a_uint64_t)ptp_rx_portid2_1_reg.bf.rx_portid << 32) |
+		((a_uint64_t)ptp_rx_portid2_2_reg.bf.rx_portid << 16) |
+		ptp_rx_portid2_3_reg.bf.rx_portid;
+	port_num = ptp_rx_portid2_4_reg.bf.rx_portid;
+	msgtype = ptp_rx_ts2_5_reg.bf.rx_msg_type;
+
+	if (pkt_info->clock_identify == clock_id &&
+			pkt_info->port_number == port_num &&
+			pkt_info->msg_type == msgtype)
+	{
+		time->seconds =
+			((a_int64_t)ptp_rx_ts2_0_reg.bf.rx_ts_sec << 32) |
+			((a_int64_t)ptp_rx_ts2_1_reg.bf.rx_ts_sec << 16) |
+			ptp_rx_ts2_2_reg.bf.rx_ts_sec;
+		time->nanoseconds =
+			((a_int32_t)ptp_rx_ts2_3_reg.bf.rx_ts_nsec << 16) |
+			ptp_rx_ts2_4_reg.bf.rx_ts_nsec;
+		time->fracnanoseconds =
+			((a_int32_t)ptp_rx_ts2_5_reg.bf.rx_ts_nfsec << 8) |
+			ptp_rx_ts2_6_reg.bf.rx_ts_nfsec;
+
+		return SW_OK;
+	}
+	return SW_NOT_FOUND;
+}
+
+sw_error_t
+qca808x_phy_ptp_rx_timestamp3_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time)
+{
+	union ptp_rx_seqid3_reg_u ptp_rx_seqid3_reg = {0};
+	union ptp_rx_portid3_0_reg_u ptp_rx_portid3_0_reg = {0};
+	union ptp_rx_portid3_1_reg_u ptp_rx_portid3_1_reg = {0};
+	union ptp_rx_portid3_2_reg_u ptp_rx_portid3_2_reg = {0};
+	union ptp_rx_portid3_3_reg_u ptp_rx_portid3_3_reg = {0};
+	union ptp_rx_portid3_4_reg_u ptp_rx_portid3_4_reg = {0};
+	union ptp_rx_ts3_0_reg_u ptp_rx_ts3_0_reg = {0};
+	union ptp_rx_ts3_1_reg_u ptp_rx_ts3_1_reg = {0};
+	union ptp_rx_ts3_2_reg_u ptp_rx_ts3_2_reg = {0};
+	union ptp_rx_ts3_3_reg_u ptp_rx_ts3_3_reg = {0};
+	union ptp_rx_ts3_4_reg_u ptp_rx_ts3_4_reg = {0};
+	union ptp_rx_ts3_5_reg_u ptp_rx_ts3_5_reg = {0};
+	union ptp_rx_ts3_6_reg_u ptp_rx_ts3_6_reg = {0};
+
+	a_uint64_t clock_id;
+	a_uint32_t port_num, msgtype;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_seqid3_reg_get(dev_id, phy_id, &ptp_rx_seqid3_reg));
+	if (pkt_info->sequence_id != ptp_rx_seqid3_reg.bf.rx_seqid)
+	{
+		return SW_NOT_FOUND;
+	}
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid3_0_reg_get(dev_id,
+				phy_id, &ptp_rx_portid3_0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid3_1_reg_get(dev_id,
+				phy_id, &ptp_rx_portid3_1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid3_2_reg_get(dev_id,
+				phy_id, &ptp_rx_portid3_2_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid3_3_reg_get(dev_id,
+				phy_id, &ptp_rx_portid3_3_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_portid3_4_reg_get(dev_id,
+				phy_id, &ptp_rx_portid3_4_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts3_0_reg_get(dev_id,
+				phy_id, &ptp_rx_ts3_0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts3_1_reg_get(dev_id,
+				phy_id, &ptp_rx_ts3_1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts3_2_reg_get(dev_id,
+				phy_id, &ptp_rx_ts3_2_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts3_3_reg_get(dev_id,
+				phy_id, &ptp_rx_ts3_3_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts3_4_reg_get(dev_id,
+				phy_id, &ptp_rx_ts3_4_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts3_5_reg_get(dev_id,
+				phy_id, &ptp_rx_ts3_5_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_ts3_6_reg_get(dev_id,
+				phy_id, &ptp_rx_ts3_6_reg));
+
+	clock_id = ((a_uint64_t)ptp_rx_portid3_0_reg.bf.rx_portid << 48) |
+		((a_uint64_t)ptp_rx_portid3_1_reg.bf.rx_portid << 32) |
+		((a_uint64_t)ptp_rx_portid3_2_reg.bf.rx_portid << 16) |
+		ptp_rx_portid3_3_reg.bf.rx_portid;
+	port_num = ptp_rx_portid3_4_reg.bf.rx_portid;
+	msgtype = ptp_rx_ts3_5_reg.bf.rx_msg_type;
+	if (pkt_info->clock_identify == clock_id &&
+			pkt_info->port_number == port_num &&
+			pkt_info->msg_type == msgtype)
+	{
+		time->seconds =
+			((a_int64_t)ptp_rx_ts3_0_reg.bf.rx_ts_sec << 32) |
+			((a_int64_t)ptp_rx_ts3_1_reg.bf.rx_ts_sec << 16) |
+			ptp_rx_ts3_2_reg.bf.rx_ts_sec;
+		time->nanoseconds =
+			((a_int32_t)ptp_rx_ts3_3_reg.bf.rx_ts_nsec << 16) |
+			ptp_rx_ts3_4_reg.bf.rx_ts_nsec;
+		time->fracnanoseconds =
+			((a_int32_t)ptp_rx_ts3_5_reg.bf.rx_ts_nfsec << 8) |
+			ptp_rx_ts3_6_reg.bf.rx_ts_nfsec;
+
+		return SW_OK;
+	}
+	return SW_NOT_FOUND;
+}
+
+sw_error_t
+qca808x_phy_ptp_tx_timestamp0_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time)
+{
+	union ptp_tx_seqid_reg_u ptp_tx_seqid_reg = {0};
+	union ptp_tx_portid0_reg_u ptp_tx_portid0_reg = {0};
+	union ptp_tx_portid1_reg_u ptp_tx_portid1_reg = {0};
+	union ptp_tx_portid2_reg_u ptp_tx_portid2_reg = {0};
+	union ptp_tx_portid3_reg_u ptp_tx_portid3_reg = {0};
+	union ptp_tx_portid4_reg_u ptp_tx_portid4_reg = {0};
+	union ptp_tx_ts0_reg_u ptp_tx_ts0_reg = {0};
+	union ptp_tx_ts1_reg_u ptp_tx_ts1_reg = {0};
+	union ptp_tx_ts2_reg_u ptp_tx_ts2_reg = {0};
+	union ptp_tx_ts3_reg_u ptp_tx_ts3_reg = {0};
+	union ptp_tx_ts4_reg_u ptp_tx_ts4_reg = {0};
+	union ptp_tx_ts5_reg_u ptp_tx_ts5_reg = {0};
+	union ptp_tx_ts6_reg_u ptp_tx_ts6_reg = {0};
+
+	a_uint64_t clock_id;
+	a_uint32_t port_num, msgtype;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_seqid_reg_get(dev_id, phy_id, &ptp_tx_seqid_reg));
+	if (pkt_info->sequence_id != ptp_tx_seqid_reg.bf.tx_seqid)
+	{
+		return SW_NOT_FOUND;
+	}
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_portid0_reg_get(dev_id,
+				phy_id, &ptp_tx_portid0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_portid1_reg_get(dev_id,
+				phy_id, &ptp_tx_portid1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_portid2_reg_get(dev_id,
+				phy_id, &ptp_tx_portid2_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_portid3_reg_get(dev_id,
+				phy_id, &ptp_tx_portid3_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_portid4_reg_get(dev_id,
+				phy_id, &ptp_tx_portid4_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_ts0_reg_get(dev_id,
+				phy_id, &ptp_tx_ts0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_ts1_reg_get(dev_id,
+				phy_id, &ptp_tx_ts1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_ts2_reg_get(dev_id,
+				phy_id, &ptp_tx_ts2_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_ts3_reg_get(dev_id,
+				phy_id, &ptp_tx_ts3_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_ts4_reg_get(dev_id,
+				phy_id, &ptp_tx_ts4_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_ts5_reg_get(dev_id,
+				phy_id, &ptp_tx_ts5_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_ts6_reg_get(dev_id,
+				phy_id, &ptp_tx_ts6_reg));
+	clock_id = ((a_uint64_t)ptp_tx_portid0_reg.bf.tx_portid << 48) |
+		((a_uint64_t)ptp_tx_portid1_reg.bf.tx_portid << 32) |
+		((a_uint64_t)ptp_tx_portid2_reg.bf.tx_portid << 16) |
+		ptp_tx_portid3_reg.bf.tx_portid;
+	port_num = ptp_tx_portid4_reg.bf.tx_portid;
+	msgtype = ptp_tx_ts5_reg.bf.tx_msg_type;
+	if (pkt_info->clock_identify == clock_id &&
+			pkt_info->port_number == port_num &&
+			pkt_info->msg_type == msgtype)
+	{
+		time->seconds =
+			((a_int64_t)ptp_tx_ts0_reg.bf.tx_ts_sec << 32) |
+			((a_int64_t)ptp_tx_ts1_reg.bf.tx_ts_sec << 16) |
+			ptp_tx_ts2_reg.bf.tx_ts_sec;
+		time->nanoseconds =
+			((a_int32_t)ptp_tx_ts3_reg.bf.tx_ts_nsec << 16) |
+			ptp_tx_ts4_reg.bf.tx_ts_nsec;
+		time->fracnanoseconds =
+			((a_int32_t)ptp_tx_ts5_reg.bf.tx_ts_nfsec << 8) |
+			ptp_tx_ts6_reg.bf.tx_ts_nfsec;
+
+		return SW_OK;
+	}
+	return SW_NOT_FOUND;
+}
+
+sw_error_t
+qca808x_phy_ptp_timestamp_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_direction_t direction,
+		fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time)
+{
+	sw_error_t ret = SW_NOT_FOUND;
+	a_uint32_t seq = 0;
+	if (direction == FAL_RX_DIRECTION)
+	{
+		for (seq = 0; seq < 4; seq++) {
+			switch (seq) {
+				case 0:
+					ret = qca808x_phy_ptp_rx_timestamp0_get(dev_id, phy_id,
+							pkt_info, time);
+					if (ret == SW_OK) {
+						return ret;
+					}
+					break;
+				case 1:
+					ret = qca808x_phy_ptp_rx_timestamp1_get(dev_id, phy_id,
+							pkt_info, time);
+					if (ret == SW_OK) {
+						return ret;
+					}
+					break;
+				case 2:
+					ret = qca808x_phy_ptp_rx_timestamp2_get(dev_id, phy_id,
+							pkt_info, time);
+					if (ret == SW_OK) {
+						return ret;
+					}
+					break;
+				case 3:
+					ret = qca808x_phy_ptp_rx_timestamp3_get(dev_id, phy_id,
+							pkt_info, time);
+					if (ret == SW_OK) {
+						return ret;
+					}
+					break;
+				default:
+					break;
+			}
+		}
+	} else {
+		ret = qca808x_phy_ptp_tx_timestamp0_get(dev_id, phy_id, pkt_info, time);
+	}
+
+	return ret;
+}
+
+sw_error_t
+qca808x_phy_ptp_pkt_timestamp_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time)
+{
+	union ptp_in_trig0_reg_u ptp_in_trig0_reg = {0};
+	union ptp_in_trig1_reg_u ptp_in_trig1_reg = {0};
+	union ptp_in_trig2_reg_u ptp_in_trig2_reg = {0};
+	union ptp_in_trig3_reg_u ptp_in_trig3_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_in_trig0_reg_get(dev_id, phy_id, &ptp_in_trig0_reg));
+	ptp_in_trig0_reg.bf.ptp_in_trig_nisec = time->nanoseconds >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_in_trig0_reg_set(dev_id, phy_id, &ptp_in_trig0_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_in_trig1_reg_get(dev_id, phy_id, &ptp_in_trig1_reg));
+	ptp_in_trig1_reg.bf.ptp_in_trig_nisec = time->nanoseconds & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_in_trig1_reg_set(dev_id, phy_id, &ptp_in_trig1_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_in_trig2_reg_get(dev_id, phy_id, &ptp_in_trig2_reg));
+	ptp_in_trig2_reg.bf.ptp_in_trig_nisec = time->fracnanoseconds >> 4;
+	SW_RTN_ON_ERROR(qca808x_ptp_in_trig2_reg_set(dev_id, phy_id, &ptp_in_trig2_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_in_trig3_reg_get(dev_id, phy_id, &ptp_in_trig3_reg));
+	ptp_in_trig3_reg.bf.ptp_in_trig_nisec = time->fracnanoseconds & 0xf;
+	SW_RTN_ON_ERROR(qca808x_ptp_in_trig3_reg_set(dev_id, phy_id, &ptp_in_trig3_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_pkt_timestamp_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time)
+{
+	union ptp_in_trig0_reg_u ptp_in_trig0_reg = {0};
+	union ptp_in_trig1_reg_u ptp_in_trig1_reg = {0};
+	union ptp_in_trig2_reg_u ptp_in_trig2_reg = {0};
+	union ptp_in_trig3_reg_u ptp_in_trig3_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_in_trig0_reg_get(dev_id, phy_id, &ptp_in_trig0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_in_trig1_reg_get(dev_id, phy_id, &ptp_in_trig1_reg));
+	time->nanoseconds = (ptp_in_trig0_reg.bf.ptp_in_trig_nisec << 16) |
+		ptp_in_trig1_reg.bf.ptp_in_trig_nisec;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_in_trig2_reg_get(dev_id, phy_id, &ptp_in_trig2_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_in_trig3_reg_get(dev_id, phy_id, &ptp_in_trig3_reg));
+	time->fracnanoseconds = (ptp_in_trig2_reg.bf.ptp_in_trig_nisec << 4) |
+			(ptp_in_trig3_reg.bf.ptp_in_trig_nisec & 0xf);
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_grandmaster_mode_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_grandmaster_mode_t *gm_mode)
+{
+	union ptp_gm_conf0_reg_u ptp_gm_conf0_reg = {0};
+	union ptp_gm_conf1_reg_u ptp_gm_conf1_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, &ptp_gm_conf0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_gm_conf1_reg_get(dev_id, phy_id, &ptp_gm_conf1_reg));
+	ptp_gm_conf0_reg.bf.grandmaster_mode = gm_mode->grandmaster_mode_en;
+	if (gm_mode->ns_sync_mode == FAL_GM_PPSIN_MODE)
+	{
+		ptp_gm_conf0_reg.bf.gm_pps_sync = PTP_REG_BIT_TRUE;
+		ptp_gm_conf0_reg.bf.gm_pll_mode = PTP_REG_BIT_FALSE;
+	}
+	else if (gm_mode->ns_sync_mode == FAL_GM_HWPLL_MODE)
+	{
+		ptp_gm_conf0_reg.bf.gm_pps_sync = PTP_REG_BIT_FALSE;
+		ptp_gm_conf0_reg.bf.gm_pll_mode = PTP_REG_BIT_TRUE;
+	}
+	else
+	{
+		ptp_gm_conf0_reg.bf.gm_pps_sync = PTP_REG_BIT_FALSE;
+		ptp_gm_conf0_reg.bf.gm_pll_mode = PTP_REG_BIT_FALSE;
+	}
+	ptp_gm_conf0_reg.bf.gm_maxfreq_offset = gm_mode->freq_offset;
+	ptp_gm_conf1_reg.bf.gm_kp_ldn =
+		(gm_mode->right_shift_in_kp << (PTP_GM_CONF1_REG_GM_KP_LDN_LEN-1)) |
+		gm_mode->kp_value;
+	ptp_gm_conf1_reg.bf.gm_ki_ldn =
+		(gm_mode->right_shift_in_ki << (PTP_GM_CONF1_REG_GM_KI_LDN_LEN-1)) |
+		gm_mode->ki_value;
+	SW_RTN_ON_ERROR(qca808x_ptp_gm_conf0_reg_set(dev_id, phy_id, &ptp_gm_conf0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_gm_conf1_reg_set(dev_id, phy_id, &ptp_gm_conf1_reg));
+
+#if defined(IN_LINUX_STD_PTP)
+	if (gm_mode->grandmaster_second_sync_en == A_TRUE) {
+		qca808x_ptp_gm_gps_seconds_sync_enable(dev_id, phy_id, A_TRUE);
+	} else {
+		qca808x_ptp_gm_gps_seconds_sync_enable(dev_id, phy_id, A_FALSE);
+	}
+#endif
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_grandmaster_mode_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_grandmaster_mode_t *gm_mode)
+{
+	union ptp_gm_conf0_reg_u ptp_gm_conf0_reg = {0};
+	union ptp_gm_conf1_reg_u ptp_gm_conf1_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, &ptp_gm_conf0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_gm_conf1_reg_get(dev_id, phy_id, &ptp_gm_conf1_reg));
+	gm_mode->grandmaster_mode_en = ptp_gm_conf0_reg.bf.grandmaster_mode;
+	if (ptp_gm_conf0_reg.bf.gm_pps_sync == 1 && ptp_gm_conf0_reg.bf.gm_pll_mode == 0)
+	{
+		gm_mode->ns_sync_mode = FAL_GM_PPSIN_MODE;
+	}
+	else if (ptp_gm_conf0_reg.bf.gm_pps_sync == 0 && ptp_gm_conf0_reg.bf.gm_pll_mode == 1)
+	{
+		gm_mode->ns_sync_mode = FAL_GM_HWPLL_MODE;
+	}
+	else
+	{
+		gm_mode->ns_sync_mode = FAL_GM_SWPLL_MODE;
+	}
+	gm_mode->freq_offset = ptp_gm_conf0_reg.bf.gm_maxfreq_offset;
+	gm_mode->right_shift_in_kp = ptp_gm_conf1_reg.bf.gm_kp_ldn >> 5;
+	gm_mode->kp_value = ptp_gm_conf1_reg.bf.gm_kp_ldn & 0x1f;
+	gm_mode->right_shift_in_ki = ptp_gm_conf1_reg.bf.gm_ki_ldn >> 5;
+	gm_mode->ki_value = ptp_gm_conf1_reg.bf.gm_ki_ldn & 0x1f;
+
+#if defined(IN_LINUX_STD_PTP)
+	if (qca808x_ptp_gm_gps_seconds_sync_status_get(dev_id, phy_id) == A_TRUE) {
+		gm_mode->grandmaster_second_sync_en = A_TRUE;
+	} else {
+		gm_mode->grandmaster_second_sync_en = A_FALSE;
+	}
+#endif
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_rtc_time_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time)
+{
+	union ptp_rtc0_reg_u ptp_rtc0_reg = {0};
+	union ptp_rtc1_reg_u ptp_rtc1_reg = {0};
+	union ptp_rtc2_reg_u ptp_rtc2_reg = {0};
+	union ptp_rtc3_reg_u ptp_rtc3_reg = {0};
+	union ptp_rtc4_reg_u ptp_rtc4_reg = {0};
+	union ptp_rtc5_reg_u ptp_rtc5_reg = {0};
+	union ptp_rtc6_reg_u ptp_rtc6_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc0_reg_get(dev_id, phy_id, &ptp_rtc0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc1_reg_get(dev_id, phy_id, &ptp_rtc1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc2_reg_get(dev_id, phy_id, &ptp_rtc2_reg));
+	time->seconds = ((a_int64_t)ptp_rtc0_reg.bf.ptp_rtc_sec << 32) |
+			(ptp_rtc1_reg.bf.ptp_rtc_sec << 16) | ptp_rtc2_reg.bf.ptp_rtc_sec;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc3_reg_get(dev_id, phy_id, &ptp_rtc3_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc4_reg_get(dev_id, phy_id, &ptp_rtc4_reg));
+	time->nanoseconds = (ptp_rtc3_reg.bf.ptp_rtc_nisec << 16) | ptp_rtc4_reg.bf.ptp_rtc_nisec;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc5_reg_get(dev_id, phy_id, &ptp_rtc5_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc6_reg_get(dev_id, phy_id, &ptp_rtc6_reg));
+	time->fracnanoseconds = (ptp_rtc5_reg.bf.ptp_rtc_nfsec << 4) |
+		ptp_rtc6_reg.bf.ptp_rtc_nfsec;
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_rtc_time_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time)
+{
+	union ptp_rtc_preloaded0_reg_u ptp_rtc_preloaded0_reg = {0};
+	union ptp_rtc_preloaded1_reg_u ptp_rtc_preloaded1_reg = {0};
+	union ptp_rtc_preloaded2_reg_u ptp_rtc_preloaded2_reg = {0};
+	union ptp_rtc_preloaded3_reg_u ptp_rtc_preloaded3_reg = {0};
+	union ptp_rtc_preloaded4_reg_u ptp_rtc_preloaded4_reg = {0};
+	union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg = {0};
+
+	ptp_rtc_preloaded0_reg.bf.ptp_rtc_preloaded_sec = (time->seconds >> 32) & 0xffff;
+	ptp_rtc_preloaded1_reg.bf.ptp_rtc_preloaded_sec = (time->seconds >> 16) & 0xffff;
+	ptp_rtc_preloaded2_reg.bf.ptp_rtc_preloaded_sec = time->seconds & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_preloaded0_reg_set(dev_id,
+				phy_id, &ptp_rtc_preloaded0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_preloaded1_reg_set(dev_id,
+				phy_id, &ptp_rtc_preloaded1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_preloaded2_reg_set(dev_id,
+				phy_id, &ptp_rtc_preloaded2_reg));
+
+	ptp_rtc_preloaded3_reg.bf.ptp_rtc_preloaded_nisec = time->nanoseconds >> 16;
+	ptp_rtc_preloaded4_reg.bf.ptp_rtc_preloaded_nisec = time->nanoseconds & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_preloaded3_reg_set(dev_id,
+				phy_id, &ptp_rtc_preloaded3_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_preloaded4_reg_set(dev_id,
+				phy_id, &ptp_rtc_preloaded4_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id,
+				phy_id, &ptp_rtc_ext_conf_reg));
+	ptp_rtc_ext_conf_reg.bf.load_rtc = 1;
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_set(dev_id,
+				phy_id, &ptp_rtc_ext_conf_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_rtc_time_clear(a_uint32_t dev_id,
+		a_uint32_t phy_id)
+{
+	union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &ptp_rtc_ext_conf_reg));
+	ptp_rtc_ext_conf_reg.bf.clear_rtc = PTP_REG_BIT_TRUE;
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &ptp_rtc_ext_conf_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_rtc_adjtime_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time)
+{
+	union ptp_rtcoffs0_reg_u ptp_rtcoffs0_reg = {0};
+	union ptp_rtcoffs1_reg_u ptp_rtcoffs1_reg = {0};
+	union ptp_rtcoffs2_reg_u ptp_rtcoffs2_reg = {0};
+	union ptp_rtcoffs3_reg_u ptp_rtcoffs3_reg = {0};
+	union ptp_rtcoffs4_reg_u ptp_rtcoffs4_reg = {0};
+	union ptp_rtcoffs_valid_reg_u ptp_rtcoffs_valid_reg = {0};
+
+	ptp_rtcoffs0_reg.bf.ptp_rtcoffs_nsec = time->nanoseconds >> 16;
+	ptp_rtcoffs1_reg.bf.ptp_rtcoffs_nsec = time->nanoseconds & 0xffff;
+	ptp_rtcoffs2_reg.bf.ptp_rtcoffs_sec = (time->seconds >> 32) & 0xffff;
+	ptp_rtcoffs3_reg.bf.ptp_rtcoffs_sec = (time->seconds >> 16) & 0xffff;
+	ptp_rtcoffs4_reg.bf.ptp_rtcoffs_sec = time->seconds & 0xffff;
+	ptp_rtcoffs_valid_reg.bf.ptp_rtcoffs_valid = 1;
+	SW_RTN_ON_ERROR(qca808x_ptp_rtcoffs0_reg_set(dev_id, phy_id, &ptp_rtcoffs0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtcoffs1_reg_set(dev_id, phy_id, &ptp_rtcoffs1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtcoffs2_reg_set(dev_id, phy_id, &ptp_rtcoffs2_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtcoffs3_reg_set(dev_id, phy_id, &ptp_rtcoffs3_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtcoffs4_reg_set(dev_id, phy_id, &ptp_rtcoffs4_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtcoffs_valid_reg_set(dev_id, phy_id, &ptp_rtcoffs_valid_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_rtc_adjfreq_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time)
+{
+	union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg = {0};
+	union ptp_rtc_inc0_reg_u ptp_rtc_inc0_reg = {0};
+	union ptp_rtc_inc1_reg_u ptp_rtc_inc1_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_inc0_reg_get(dev_id, phy_id, &ptp_rtc_inc0_reg));
+	ptp_rtc_inc0_reg.bf.ptp_rtc_inc_nis = time->nanoseconds & 0x3f;
+	ptp_rtc_inc0_reg.bf.ptp_rtc_inc_nfs = (time->fracnanoseconds >> 16) & 0x3ff;
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_inc0_reg_set(dev_id, phy_id, &ptp_rtc_inc0_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_inc1_reg_get(dev_id, phy_id, &ptp_rtc_inc1_reg));
+	ptp_rtc_inc1_reg.bf.ptp_rtc_inc_nfs = time->fracnanoseconds & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_inc1_reg_set(dev_id, phy_id, &ptp_rtc_inc1_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &ptp_rtc_ext_conf_reg));
+	ptp_rtc_ext_conf_reg.bf.set_incval_valid = PTP_REG_BIT_TRUE;
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &ptp_rtc_ext_conf_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_rtc_adjfreq_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time)
+{
+	union ptp_rtc_inc0_reg_u ptp_rtc_inc0_reg = {0};
+	union ptp_rtc_inc1_reg_u ptp_rtc_inc1_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_inc0_reg_get(dev_id, phy_id, &ptp_rtc_inc0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_inc1_reg_get(dev_id, phy_id, &ptp_rtc_inc1_reg));
+	time->nanoseconds = ptp_rtc_inc0_reg.bf.ptp_rtc_inc_nis;
+	time->fracnanoseconds = (ptp_rtc_inc0_reg.bf.ptp_rtc_inc_nfs << 16) |
+		ptp_rtc_inc1_reg.bf.ptp_rtc_inc_nfs;
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_link_delay_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time)
+{
+	union ptp_link_delay_0_reg_u ptp_link_delay_0_reg = {0};
+	union ptp_link_delay_1_reg_u ptp_link_delay_1_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_link_delay_0_reg_get(dev_id, phy_id, &ptp_link_delay_0_reg));
+	ptp_link_delay_0_reg.bf.link_delay = time->nanoseconds >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_link_delay_0_reg_set(dev_id, phy_id, &ptp_link_delay_0_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_link_delay_1_reg_get(dev_id, phy_id, &ptp_link_delay_1_reg));
+	ptp_link_delay_1_reg.bf.link_delay = time->nanoseconds & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_link_delay_1_reg_set(dev_id, phy_id, &ptp_link_delay_1_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_link_delay_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_time_t *time)
+{
+	union ptp_link_delay_0_reg_u ptp_link_delay_0_reg = {0};
+	union ptp_link_delay_1_reg_u ptp_link_delay_1_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_link_delay_0_reg_get(dev_id, phy_id, &ptp_link_delay_0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_link_delay_1_reg_get(dev_id, phy_id, &ptp_link_delay_1_reg));
+	time->nanoseconds = (ptp_link_delay_0_reg.bf.link_delay << 16) |
+		ptp_link_delay_1_reg.bf.link_delay;
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_security_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_security_t *sec)
+{
+	union ptp_misc_config_reg_u ptp_misc_config_reg = {0};
+	union ptp_main_conf_reg_u ptp_main_conf_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg));
+	ptp_misc_config_reg.bf.ptp_addr_chk_en = sec->address_check_en;
+	ptp_misc_config_reg.bf.ipv6_udp_chk_en = sec->ipv6_udp_checksum_recal_en;
+	ptp_misc_config_reg.bf.ptp_ver_chk_en = sec->version_check_en;
+	ptp_misc_config_reg.bf.ptp_version = sec->ptp_version;
+	SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &ptp_misc_config_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg));
+	ptp_main_conf_reg.bf.ipv4_force_checksum_zero =
+		sec->ipv4_udp_checksum_force_zero_en;
+	ptp_main_conf_reg.bf.ipv6_embed_force_checksum_zero =
+		sec->ipv6_embed_udp_checksum_force_zero_en;
+	SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &ptp_main_conf_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_security_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_security_t *sec)
+{
+	union ptp_misc_config_reg_u ptp_misc_config_reg = {0};
+	union ptp_main_conf_reg_u ptp_main_conf_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg));
+	sec->address_check_en = ptp_misc_config_reg.bf.ptp_addr_chk_en;
+	sec->ipv6_udp_checksum_recal_en = ptp_misc_config_reg.bf.ipv6_udp_chk_en;
+	sec->version_check_en = ptp_misc_config_reg.bf.ptp_ver_chk_en;
+	sec->ptp_version = ptp_misc_config_reg.bf.ptp_version;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg));
+	sec->ipv4_udp_checksum_force_zero_en = ptp_main_conf_reg.bf.ipv4_force_checksum_zero;
+	sec->ipv6_embed_udp_checksum_force_zero_en =
+		ptp_main_conf_reg.bf.ipv6_embed_force_checksum_zero;
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_pps_signal_control_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_pps_signal_control_t *sig_control)
+{
+	union ptp_ppsin_latency_reg_u ptp_ppsin_latency_reg = {0};
+	union ptp_phase_adjust_0_reg_u ptp_phase_adjust_0_reg = {0};
+	union ptp_phase_adjust_1_reg_u ptp_phase_adjust_1_reg = {0};
+	union ptp_pps_pul_width_0_reg_u ptp_pps_pul_width_0_reg = {0};
+	union ptp_pps_pul_width_1_reg_u ptp_pps_pul_width_1_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_ppsin_latency_reg_get(dev_id,
+				phy_id, &ptp_ppsin_latency_reg));
+	ptp_ppsin_latency_reg.bf.ptp_ppsin_latency_sign = sig_control->negative_in_latency;
+	ptp_ppsin_latency_reg.bf.ptp_ppsin_latency_value = sig_control->in_latency;
+	SW_RTN_ON_ERROR(qca808x_ptp_ppsin_latency_reg_set(dev_id,
+				phy_id, &ptp_ppsin_latency_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_phase_adjust_0_reg_get(dev_id,
+				phy_id, &ptp_phase_adjust_0_reg));
+	ptp_phase_adjust_0_reg.bf.phase_value = sig_control->out_phase >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_phase_adjust_0_reg_set(dev_id,
+				phy_id, &ptp_phase_adjust_0_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_phase_adjust_1_reg_get(dev_id,
+				phy_id, &ptp_phase_adjust_1_reg));
+	ptp_phase_adjust_1_reg.bf.phase_value = sig_control->out_phase & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_phase_adjust_1_reg_set(dev_id,
+				phy_id, &ptp_phase_adjust_1_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_pps_pul_width_0_reg_get(dev_id,
+				phy_id, &ptp_pps_pul_width_0_reg));
+	ptp_pps_pul_width_0_reg.bf.pul_value = sig_control->out_pulse_width >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_pps_pul_width_0_reg_set(dev_id,
+				phy_id, &ptp_pps_pul_width_0_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_pps_pul_width_1_reg_get(dev_id,
+				phy_id, &ptp_pps_pul_width_1_reg));
+	ptp_pps_pul_width_1_reg.bf.pul_value = sig_control->out_pulse_width & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_pps_pul_width_1_reg_set(dev_id,
+				phy_id, &ptp_pps_pul_width_1_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_pps_signal_control_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_pps_signal_control_t *sig_control)
+{
+	union ptp_ppsin_latency_reg_u ptp_ppsin_latency_reg = {0};
+	union ptp_phase_adjust_0_reg_u ptp_phase_adjust_0_reg = {0};
+	union ptp_phase_adjust_1_reg_u ptp_phase_adjust_1_reg = {0};
+	union ptp_pps_pul_width_0_reg_u ptp_pps_pul_width_0_reg = {0};
+	union ptp_pps_pul_width_1_reg_u ptp_pps_pul_width_1_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_ppsin_latency_reg_get(dev_id,
+				phy_id, &ptp_ppsin_latency_reg));
+	sig_control->negative_in_latency = ptp_ppsin_latency_reg.bf.ptp_ppsin_latency_sign;
+	sig_control->in_latency = ptp_ppsin_latency_reg.bf.ptp_ppsin_latency_value;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_phase_adjust_0_reg_get(dev_id,
+				phy_id, &ptp_phase_adjust_0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_phase_adjust_1_reg_get(dev_id,
+				phy_id, &ptp_phase_adjust_1_reg));
+	sig_control->out_phase = (ptp_phase_adjust_0_reg.bf.phase_value << 16) |
+			ptp_phase_adjust_1_reg.bf.phase_value;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_pps_pul_width_0_reg_get(dev_id,
+				phy_id, &ptp_pps_pul_width_0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_pps_pul_width_1_reg_get(dev_id,
+				phy_id, &ptp_pps_pul_width_1_reg));
+	sig_control->out_pulse_width = (ptp_pps_pul_width_0_reg.bf.pul_value << 16) |
+			ptp_pps_pul_width_1_reg.bf.pul_value;
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_rx_crc_recalc_enable(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_bool_t status)
+{
+	union ptp_misc_config_reg_u ptp_misc_config_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg));
+	ptp_misc_config_reg.bf.crc_validate_en = status;
+	SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &ptp_misc_config_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_rx_crc_recalc_status_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_bool_t *status)
+{
+	union ptp_misc_config_reg_u ptp_misc_config_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg));
+	*status = ptp_misc_config_reg.bf.crc_validate_en;
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_asym_correction_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_asym_correction_t *asym_cf)
+{
+	union ptp_misc_control_reg_u ptp_misc_control_reg = {0};
+	union ptp_ingress_asymmetry_0_reg_u ptp_ingress_asymmetry_0_reg = {0};
+	union ptp_ingress_asymmetry_1_reg_u ptp_ingress_asymmetry_1_reg = {0};
+	union ptp_egress_asymmetry_0_reg_u ptp_egress_asymmetry_0_reg = {0};
+	union ptp_egress_asymmetry_1_reg_u ptp_egress_asymmetry_1_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_misc_control_reg_get(dev_id,
+				phy_id, &ptp_misc_control_reg));
+	ptp_misc_control_reg.bf.eg_asym_en = asym_cf->eg_asym_en;
+	ptp_misc_control_reg.bf.in_asym_en = asym_cf->in_asym_en;
+	SW_RTN_ON_ERROR(qca808x_ptp_misc_control_reg_set(dev_id,
+				phy_id, &ptp_misc_control_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_ingress_asymmetry_0_reg_get(dev_id,
+				phy_id, &ptp_ingress_asymmetry_0_reg));
+	ptp_ingress_asymmetry_0_reg.bf.in_asym = asym_cf->in_asym_value >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_ingress_asymmetry_0_reg_set(dev_id,
+				phy_id, &ptp_ingress_asymmetry_0_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_ingress_asymmetry_1_reg_get(dev_id,
+				phy_id, &ptp_ingress_asymmetry_1_reg));
+	ptp_ingress_asymmetry_1_reg.bf.in_asym = asym_cf->in_asym_value & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_ingress_asymmetry_1_reg_set(dev_id,
+				phy_id, &ptp_ingress_asymmetry_1_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_egress_asymmetry_0_reg_get(dev_id,
+				phy_id, &ptp_egress_asymmetry_0_reg));
+	ptp_egress_asymmetry_0_reg.bf.eg_asym = asym_cf->eg_asym_value >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_egress_asymmetry_0_reg_get(dev_id,
+				phy_id, &ptp_egress_asymmetry_0_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_egress_asymmetry_1_reg_get(dev_id,
+				phy_id, &ptp_egress_asymmetry_1_reg));
+	ptp_egress_asymmetry_1_reg.bf.eg_asym = asym_cf->eg_asym_value & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_egress_asymmetry_1_reg_set(dev_id,
+				phy_id, &ptp_egress_asymmetry_1_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_asym_correction_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_asym_correction_t* asym_cf)
+{
+	union ptp_misc_control_reg_u ptp_misc_control_reg = {0};
+	union ptp_ingress_asymmetry_0_reg_u ptp_ingress_asymmetry_0_reg = {0};
+	union ptp_ingress_asymmetry_1_reg_u ptp_ingress_asymmetry_1_reg = {0};
+	union ptp_egress_asymmetry_0_reg_u ptp_egress_asymmetry_0_reg = {0};
+	union ptp_egress_asymmetry_1_reg_u ptp_egress_asymmetry_1_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_misc_control_reg_get(dev_id,
+				phy_id, &ptp_misc_control_reg));
+	asym_cf->eg_asym_en = ptp_misc_control_reg.bf.eg_asym_en;
+	asym_cf->in_asym_en = ptp_misc_control_reg.bf.in_asym_en;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_ingress_asymmetry_0_reg_get(dev_id,
+				phy_id, &ptp_ingress_asymmetry_0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_ingress_asymmetry_1_reg_get(dev_id,
+				phy_id, &ptp_ingress_asymmetry_1_reg));
+	asym_cf->in_asym_value = (ptp_ingress_asymmetry_0_reg.bf.in_asym << 16) |
+		ptp_ingress_asymmetry_1_reg.bf.in_asym;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_egress_asymmetry_0_reg_get(dev_id,
+				phy_id, &ptp_egress_asymmetry_0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_egress_asymmetry_1_reg_get(dev_id,
+				phy_id, &ptp_egress_asymmetry_1_reg));
+	asym_cf->eg_asym_value = (ptp_egress_asymmetry_0_reg.bf.eg_asym << 16) |
+		ptp_egress_asymmetry_1_reg.bf.eg_asym;
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_output_waveform_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_output_waveform_t *waveform)
+{
+	union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg = {0};
+	union ptp_freq_waveform_period_0_reg_u ptp_freq_waveform_period_0_reg = {0};
+	union ptp_freq_waveform_period_1_reg_u ptp_freq_waveform_period_1_reg = {0};
+	union ptp_freq_waveform_period_2_reg_u ptp_freq_waveform_period_2_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id,
+				phy_id, &ptp_rtc_ext_conf_reg));
+	if (waveform->waveform_type == FAL_WAVE_FREQ)
+	{
+		ptp_rtc_ext_conf_reg.bf.select_output_waveform =
+			PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_FREQ;
+	}
+	else if (waveform->waveform_type == FAL_PULSE_10MS)
+	{
+		ptp_rtc_ext_conf_reg.bf.select_output_waveform =
+			PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_PULSE_10MS;
+	}
+	else if (waveform->waveform_type == FAL_TRIGGER0_GPIO)
+	{
+		ptp_rtc_ext_conf_reg.bf.select_output_waveform =
+			PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_TRIG0_GPIO;
+	}
+	else
+	{
+		ptp_rtc_ext_conf_reg.bf.select_output_waveform =
+			PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_RXTS_VALID;
+	}
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &ptp_rtc_ext_conf_reg));
+
+	ptp_freq_waveform_period_0_reg.bf.phase_ali = waveform->wave_align_pps_out_en;
+	ptp_freq_waveform_period_0_reg.bf.wave_period = (waveform->wave_period >> 32) & 0x7fff;
+	ptp_freq_waveform_period_1_reg.bf.wave_period = (waveform->wave_period >> 16) & 0xffff;
+	ptp_freq_waveform_period_2_reg.bf.wave_period = waveform->wave_period & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_freq_waveform_period_0_reg_set(dev_id,
+				phy_id, &ptp_freq_waveform_period_0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_freq_waveform_period_1_reg_set(dev_id,
+				phy_id, &ptp_freq_waveform_period_1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_freq_waveform_period_2_reg_set(dev_id,
+				phy_id, &ptp_freq_waveform_period_2_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_output_waveform_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_output_waveform_t *waveform)
+{
+	union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg = {0};
+	union ptp_freq_waveform_period_0_reg_u ptp_freq_waveform_period_0_reg = {0};
+	union ptp_freq_waveform_period_1_reg_u ptp_freq_waveform_period_1_reg = {0};
+	union ptp_freq_waveform_period_2_reg_u ptp_freq_waveform_period_2_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id,
+				phy_id, &ptp_rtc_ext_conf_reg));
+	if (ptp_rtc_ext_conf_reg.bf.select_output_waveform ==
+			PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_FREQ)
+	{
+		waveform->waveform_type = FAL_WAVE_FREQ;
+	}
+	else if (ptp_rtc_ext_conf_reg.bf.select_output_waveform ==
+			PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_PULSE_10MS)
+	{
+		waveform->waveform_type = FAL_PULSE_10MS;
+	}
+	else if (ptp_rtc_ext_conf_reg.bf.select_output_waveform ==
+			PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_TRIG0_GPIO)
+	{
+		waveform->waveform_type = FAL_TRIGGER0_GPIO;
+	}
+	else
+	{
+		waveform->waveform_type = FAL_RX_PTP_STATE;
+	}
+
+	SW_RTN_ON_ERROR(qca808x_ptp_freq_waveform_period_0_reg_get(dev_id,
+				phy_id, &ptp_freq_waveform_period_0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_freq_waveform_period_1_reg_get(dev_id,
+				phy_id, &ptp_freq_waveform_period_1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_freq_waveform_period_2_reg_get(dev_id,
+				phy_id, &ptp_freq_waveform_period_2_reg));
+	waveform->wave_align_pps_out_en = ptp_freq_waveform_period_0_reg.bf.phase_ali;
+	waveform->wave_period = ((a_int64_t)ptp_freq_waveform_period_0_reg.bf.wave_period << 32) |
+		(ptp_freq_waveform_period_1_reg.bf.wave_period  << 16) |
+		ptp_freq_waveform_period_2_reg.bf.wave_period;
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_rtc_time_snapshot_enable(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_bool_t status)
+{
+	union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg= {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &ptp_rtc_ext_conf_reg));
+	ptp_rtc_ext_conf_reg.bf.rtc_read_mode = status;
+	if (status == A_TRUE)
+	{
+		ptp_rtc_ext_conf_reg.bf.rtc_snapshot = PTP_REG_BIT_TRUE;
+	}
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &ptp_rtc_ext_conf_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_rtc_time_snapshot_status_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_bool_t *status)
+{
+	union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg= {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &ptp_rtc_ext_conf_reg));
+	*status = ptp_rtc_ext_conf_reg.bf.rtc_read_mode;
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_increment_sync_from_clock_enable(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_bool_t status)
+{
+	union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &ptp_rtc_ext_conf_reg));
+	ptp_rtc_ext_conf_reg.bf.set_incval_mode = status;
+	if (status == A_TRUE)
+	{
+		ptp_rtc_ext_conf_reg.bf.set_incval_valid = PTP_REG_BIT_TRUE;
+	}
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &ptp_rtc_ext_conf_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_increment_sync_from_clock_status_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_bool_t *status)
+{
+	union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &ptp_rtc_ext_conf_reg));
+	*status = ptp_rtc_ext_conf_reg.bf.set_incval_mode;
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_tod_uart_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_tod_uart_t *tod_uart)
+{
+	union ptp_baud_config_reg_u  ptp_baud_config_reg = {0};
+	union ptp_uart_configuration_reg_u ptp_uart_configuration_reg = {0};
+	union ptp_reset_buffer_reg_u ptp_reset_buffer_reg = {0};
+	union ptp_tx_buffer_write_reg_u ptp_tx_buffer_write_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_baud_config_reg_get(dev_id, phy_id, &ptp_baud_config_reg));
+	ptp_baud_config_reg.bf.baud_rate = tod_uart->baud_config;
+	SW_RTN_ON_ERROR(qca808x_ptp_baud_config_reg_set(dev_id, phy_id, &ptp_baud_config_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_uart_configuration_reg_get(dev_id,
+				phy_id, &ptp_uart_configuration_reg));
+	ptp_uart_configuration_reg.bf.start_polarity = tod_uart->uart_config_bmp & 0x1;
+	ptp_uart_configuration_reg.bf.msb_first =
+	(tod_uart->uart_config_bmp >> PTP_UART_CONFIGURATION_REG_MSB_FIRST_OFFSET) & 0x1;
+	ptp_uart_configuration_reg.bf.parity_en =
+	(tod_uart->uart_config_bmp >> PTP_UART_CONFIGURATION_REG_PARITY_EN_OFFSET) & 0x1;
+	ptp_uart_configuration_reg.bf.auto_tod_out_en =
+	(tod_uart->uart_config_bmp >> PTP_UART_CONFIGURATION_REG_AUTO_TOD_OUT_EN_OFFSET) & 0x1;
+	ptp_uart_configuration_reg.bf.auto_tod_in_en =
+	(tod_uart->uart_config_bmp >> PTP_UART_CONFIGURATION_REG_AUTO_TOD_IN_EN_OFFSET) & 0x1;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_uart_configuration_reg_set(dev_id,
+				phy_id, &ptp_uart_configuration_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_reset_buffer_reg_get(dev_id, phy_id, &ptp_reset_buffer_reg));
+	ptp_reset_buffer_reg.bf.reset = tod_uart->reset_buf_en;
+	SW_RTN_ON_ERROR(qca808x_ptp_reset_buffer_reg_set(dev_id, phy_id, &ptp_reset_buffer_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_buffer_write_reg_get(dev_id,
+				phy_id, &ptp_tx_buffer_write_reg));
+	ptp_tx_buffer_write_reg.bf.tx_buffer = tod_uart->tx_buf_value;
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_buffer_write_reg_set(dev_id,
+				phy_id, &ptp_tx_buffer_write_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_tod_uart_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_tod_uart_t *tod_uart)
+{
+	union ptp_baud_config_reg_u  ptp_baud_config_reg = {0};
+	union ptp_uart_configuration_reg_u ptp_uart_configuration_reg = {0};
+	union ptp_buffer_status_reg_u ptp_buffer_status_reg = {0};
+	union ptp_tx_buffer_write_reg_u ptp_tx_buffer_write_reg = {0};
+	union ptp_rx_buffer_read_reg_u ptp_rx_buffer_read_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_baud_config_reg_get(dev_id, phy_id, &ptp_baud_config_reg));
+	tod_uart->baud_config = ptp_baud_config_reg.bf.baud_rate;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_uart_configuration_reg_get(dev_id,
+				phy_id, &ptp_uart_configuration_reg));
+	tod_uart->uart_config_bmp = ptp_uart_configuration_reg.bf.start_polarity |
+		(ptp_uart_configuration_reg.bf.msb_first <<
+		 PTP_UART_CONFIGURATION_REG_MSB_FIRST_OFFSET) |
+		(ptp_uart_configuration_reg.bf.parity_en <<
+		 PTP_UART_CONFIGURATION_REG_PARITY_EN_OFFSET) |
+		(ptp_uart_configuration_reg.bf.auto_tod_out_en <<
+		 PTP_UART_CONFIGURATION_REG_AUTO_TOD_OUT_EN_OFFSET) |
+		(ptp_uart_configuration_reg.bf.auto_tod_in_en <<
+		 PTP_UART_CONFIGURATION_REG_AUTO_TOD_IN_EN_OFFSET);
+
+	/* reset buffer is self clearing, always read as 0 */
+	tod_uart->reset_buf_en = 0;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &ptp_buffer_status_reg));
+	tod_uart->buf_status_bmp = ptp_buffer_status_reg.bf.tx_buffer_almost_empty |
+		(ptp_buffer_status_reg.bf.tx_buffer_almost_full <<
+		 PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_FULL_OFFSET) |
+		(ptp_buffer_status_reg.bf.tx_buffer_half_full <<
+		 PTP_BUFFER_STATUS_REG_TX_BUFFER_HALF_FULL_OFFSET) |
+		(ptp_buffer_status_reg.bf.tx_buffer_full <<
+		 PTP_BUFFER_STATUS_REG_TX_BUFFER_FULL_OFFSET) |
+		(ptp_buffer_status_reg.bf.rx_buffer_almost_empty <<
+		 PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_EMPTY_OFFSET) |
+		(ptp_buffer_status_reg.bf.rx_buffer_almost_full <<
+		 PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_FULL_OFFSET) |
+		(ptp_buffer_status_reg.bf.rx_buffer_half_full <<
+		 PTP_BUFFER_STATUS_REG_RX_BUFFER_HALF_FULL_OFFSET) |
+		(ptp_buffer_status_reg.bf.rx_buffer_full <<
+		 PTP_BUFFER_STATUS_REG_RX_BUFFER_FULL_OFFSET) |
+		(ptp_buffer_status_reg.bf.rx_buffer_data_present <<
+		 PTP_BUFFER_STATUS_REG_RX_BUFFER_DATA_PRESENT_OFFSET);
+
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_buffer_write_reg_get(dev_id,
+				phy_id, &ptp_tx_buffer_write_reg));
+	tod_uart->tx_buf_value = ptp_tx_buffer_write_reg.bf.tx_buffer;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_buffer_read_reg_get(dev_id,
+				phy_id, &ptp_rx_buffer_read_reg));
+	tod_uart->rx_buf_value = ptp_rx_buffer_read_reg.bf.rx_data;
+
+	return SW_OK;
+}
+
+sw_error_t
+_qca808x_phy_ptp_enhanced_timestamp_engine_rx_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_enhanced_ts_engine_t *ts_engine)
+{
+	union ptp_rx_com_ts_ctrl_reg_u ptp_rx_com_ts_ctrl_reg = {0};
+	union ptp_rx_filt_mac_da0_reg_u ptp_rx_filt_mac_da0_reg = {0};
+	union ptp_rx_filt_mac_da1_reg_u ptp_rx_filt_mac_da1_reg = {0};
+	union ptp_rx_filt_mac_da2_reg_u ptp_rx_filt_mac_da2_reg = {0};
+	union ptp_rx_filt_ipv4_da0_reg_u ptp_rx_filt_ipv4_da0_reg = {0};
+	union ptp_rx_filt_ipv4_da1_reg_u ptp_rx_filt_ipv4_da1_reg = {0};
+	union ptp_rx_filt_ipv6_da0_reg_u ptp_rx_filt_ipv6_da0_reg = {0};
+	union ptp_rx_filt_ipv6_da1_reg_u ptp_rx_filt_ipv6_da1_reg = {0};
+	union ptp_rx_filt_ipv6_da2_reg_u ptp_rx_filt_ipv6_da2_reg = {0};
+	union ptp_rx_filt_ipv6_da3_reg_u ptp_rx_filt_ipv6_da3_reg = {0};
+	union ptp_rx_filt_ipv6_da4_reg_u ptp_rx_filt_ipv6_da4_reg = {0};
+	union ptp_rx_filt_ipv6_da5_reg_u ptp_rx_filt_ipv6_da5_reg = {0};
+	union ptp_rx_filt_ipv6_da6_reg_u ptp_rx_filt_ipv6_da6_reg = {0};
+	union ptp_rx_filt_ipv6_da7_reg_u ptp_rx_filt_ipv6_da7_reg = {0};
+	union ptp_rx_filt_mac_lengthtype_reg_u ptp_rx_filt_mac_lengthtype_reg = {0};
+	union ptp_rx_filt_layer4_protocol_reg_u ptp_rx_filt_layer4_protocol_reg = {0};
+	union ptp_rx_filt_udp_port_reg_u ptp_rx_filt_udp_port_reg = {0};
+
+	union ptp_loc_mac_addr_0_reg_u ptp_loc_mac_addr_0_reg = {0};
+	union ptp_loc_mac_addr_1_reg_u ptp_loc_mac_addr_1_reg = {0};
+	union ptp_loc_mac_addr_2_reg_u ptp_loc_mac_addr_2_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id,
+				phy_id, &ptp_rx_com_ts_ctrl_reg));
+	ptp_rx_com_ts_ctrl_reg.bf.filt_en = ts_engine->filt_en;
+	ptp_rx_com_ts_ctrl_reg.bf.mac_lengthtype_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_rx_com_ts_ctrl_reg.bf.mac_da_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_MAC_DA_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_rx_com_ts_ctrl_reg.bf.mac_ptp_filt_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_rx_com_ts_ctrl_reg.bf.ipv4_layer4_protocol_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_rx_com_ts_ctrl_reg.bf.ipv4_da_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_IPV4_DA_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_rx_com_ts_ctrl_reg.bf.ipv4_ptp_filt_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_rx_com_ts_ctrl_reg.bf.ipv6_next_header_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_rx_com_ts_ctrl_reg.bf.ipv6_da_filt_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_IPV6_DA_FILT_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_rx_com_ts_ctrl_reg.bf.ipv6_ptp_filt_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_rx_com_ts_ctrl_reg.bf.udp_dport_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_UDP_DPORT_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_rx_com_ts_ctrl_reg.bf.udp_ptp_event_filt_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_rx_com_ts_ctrl_reg.bf.y1731_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_Y1731_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_rx_com_ts_ctrl_reg.bf.y1731_insert_ts_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_rx_com_ts_ctrl_reg.bf.y1731_da_chk_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_Y1731_DA_CHK_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id,
+				phy_id, &ptp_rx_com_ts_ctrl_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_lengthtype_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_mac_lengthtype_reg));
+	ptp_rx_filt_mac_lengthtype_reg.bf.length_type = ts_engine->eth_type;
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_lengthtype_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_mac_lengthtype_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da0_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_mac_da0_reg));
+	ptp_rx_filt_mac_da0_reg.bf.mac_addr = (ts_engine->dmac_addr.uc[0] << 8) |
+		ts_engine->dmac_addr.uc[1];
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da0_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_mac_da0_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da1_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_mac_da1_reg));
+	ptp_rx_filt_mac_da1_reg.bf.mac_addr = (ts_engine->dmac_addr.uc[2] << 8) |
+		ts_engine->dmac_addr.uc[3];
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da1_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_mac_da1_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da2_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_mac_da2_reg));
+	ptp_rx_filt_mac_da2_reg.bf.mac_addr = (ts_engine->dmac_addr.uc[4] << 8) |
+		ts_engine->dmac_addr.uc[5];
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da2_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_mac_da2_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_layer4_protocol_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_layer4_protocol_reg));
+	ptp_rx_filt_layer4_protocol_reg.bf.l4_protocol = ts_engine->ipv4_l4_proto;
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_layer4_protocol_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_layer4_protocol_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv4_da0_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv4_da0_reg));
+	ptp_rx_filt_ipv4_da0_reg.bf.ip_addr = ts_engine->ipv4_dip >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv4_da0_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_ipv4_da0_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv4_da1_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv4_da1_reg));
+	ptp_rx_filt_ipv4_da1_reg.bf.ip_addr = ts_engine->ipv4_dip & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv4_da1_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_ipv4_da1_reg));;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da0_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da0_reg));
+	ptp_rx_filt_ipv6_da0_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[0] >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da0_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da0_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da1_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da1_reg));
+	ptp_rx_filt_ipv6_da1_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[0] & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da1_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da1_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da2_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da2_reg));
+	ptp_rx_filt_ipv6_da2_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[1] >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da2_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da2_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da3_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da3_reg));
+	ptp_rx_filt_ipv6_da3_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[1] & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da3_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da3_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da4_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da4_reg));
+	ptp_rx_filt_ipv6_da4_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[2] >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da4_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da4_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da5_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da5_reg));
+	ptp_rx_filt_ipv6_da5_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[2] & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da5_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da5_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da6_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da6_reg));
+	ptp_rx_filt_ipv6_da6_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[3] >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da6_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da6_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da7_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da7_reg));
+	ptp_rx_filt_ipv6_da7_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[3] & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da7_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da7_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_udp_port_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_udp_port_reg));
+	ptp_rx_filt_udp_port_reg.bf.udp_port = ts_engine->udp_dport;
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_udp_port_reg_set(dev_id,
+				phy_id, &ptp_rx_filt_udp_port_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_0_reg_get(dev_id,
+				phy_id, &ptp_loc_mac_addr_0_reg));
+	ptp_loc_mac_addr_0_reg.bf.mac_addr = (ts_engine->y1731_mac_addr.uc[0] << 8) |
+		ts_engine->y1731_mac_addr.uc[1];
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_0_reg_set(dev_id,
+				phy_id, &ptp_loc_mac_addr_0_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_1_reg_get(dev_id,
+				phy_id, &ptp_loc_mac_addr_1_reg));
+	ptp_loc_mac_addr_1_reg.bf.mac_addr = (ts_engine->y1731_mac_addr.uc[2] << 8) |
+		ts_engine->y1731_mac_addr.uc[3];
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_1_reg_set(dev_id,
+				phy_id, &ptp_loc_mac_addr_1_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_2_reg_get(dev_id,
+				phy_id, &ptp_loc_mac_addr_2_reg));
+	ptp_loc_mac_addr_2_reg.bf.mac_addr = (ts_engine->y1731_mac_addr.uc[4] << 8) |
+		ts_engine->y1731_mac_addr.uc[5];
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_2_reg_set(dev_id,
+				phy_id, &ptp_loc_mac_addr_2_reg));
+
+	return SW_OK;
+}
+
+
+sw_error_t
+_qca808x_phy_ptp_enhanced_timestamp_engine_tx_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_enhanced_ts_engine_t *ts_engine)
+{
+	union ptp_tx_com_ts_ctrl_reg_u ptp_tx_com_ts_ctrl_reg = {0};
+	union ptp_tx_filt_mac_da0_reg_u ptp_tx_filt_mac_da0_reg = {0};
+	union ptp_tx_filt_mac_da1_reg_u ptp_tx_filt_mac_da1_reg = {0};
+	union ptp_tx_filt_mac_da2_reg_u ptp_tx_filt_mac_da2_reg = {0};
+	union ptp_tx_filt_ipv4_da0_reg_u ptp_tx_filt_ipv4_da0_reg = {0};
+	union ptp_tx_filt_ipv4_da1_reg_u ptp_tx_filt_ipv4_da1_reg = {0};
+	union ptp_tx_filt_ipv6_da0_reg_u ptp_tx_filt_ipv6_da0_reg = {0};
+	union ptp_tx_filt_ipv6_da1_reg_u ptp_tx_filt_ipv6_da1_reg = {0};
+	union ptp_tx_filt_ipv6_da2_reg_u ptp_tx_filt_ipv6_da2_reg = {0};
+	union ptp_tx_filt_ipv6_da3_reg_u ptp_tx_filt_ipv6_da3_reg = {0};
+	union ptp_tx_filt_ipv6_da4_reg_u ptp_tx_filt_ipv6_da4_reg = {0};
+	union ptp_tx_filt_ipv6_da5_reg_u ptp_tx_filt_ipv6_da5_reg = {0};
+	union ptp_tx_filt_ipv6_da6_reg_u ptp_tx_filt_ipv6_da6_reg = {0};
+	union ptp_tx_filt_ipv6_da7_reg_u ptp_tx_filt_ipv6_da7_reg = {0};
+	union ptp_tx_filt_mac_lengthtype_reg_u ptp_tx_filt_mac_lengthtype_reg = {0};
+	union ptp_tx_filt_layer4_protocol_reg_u ptp_tx_filt_layer4_protocol_reg = {0};
+	union ptp_tx_filt_udp_port_reg_u ptp_tx_filt_udp_port_reg = {0};
+
+	union ptp_loc_mac_addr_0_reg_u ptp_loc_mac_addr_0_reg = {0};
+	union ptp_loc_mac_addr_1_reg_u ptp_loc_mac_addr_1_reg = {0};
+	union ptp_loc_mac_addr_2_reg_u ptp_loc_mac_addr_2_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id,
+				phy_id, &ptp_tx_com_ts_ctrl_reg));
+	ptp_tx_com_ts_ctrl_reg.bf.filt_en = ts_engine->filt_en;
+	ptp_tx_com_ts_ctrl_reg.bf.mac_lengthtype_en = ts_engine->enhance_ts_conf_bmp &
+		PTP_REG_BIT_TRUE;
+	ptp_tx_com_ts_ctrl_reg.bf.mac_da_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_MAC_DA_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_tx_com_ts_ctrl_reg.bf.mac_ptp_filt_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_tx_com_ts_ctrl_reg.bf.ipv4_layer4_protocol_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_tx_com_ts_ctrl_reg.bf.ipv4_da_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_IPV4_DA_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_tx_com_ts_ctrl_reg.bf.ipv4_ptp_filt_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_tx_com_ts_ctrl_reg.bf.ipv6_next_header_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_tx_com_ts_ctrl_reg.bf.ipv6_da_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_IPV6_DA_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_tx_com_ts_ctrl_reg.bf.ipv6_ptp_filt_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_tx_com_ts_ctrl_reg.bf.udp_dport_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_UDP_DPORT_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_tx_com_ts_ctrl_reg.bf.udp_ptp_event_filt_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_tx_com_ts_ctrl_reg.bf.y1731_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_Y1731_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_tx_com_ts_ctrl_reg.bf.y1731_insert_ts_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	ptp_tx_com_ts_ctrl_reg.bf.y1731_sa_chk_en =
+	(ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_Y1731_SA_CHK_EN_OFFSET-1)
+	 ) & PTP_REG_BIT_TRUE;
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id,
+				phy_id, &ptp_tx_com_ts_ctrl_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_lengthtype_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_mac_lengthtype_reg));
+	ptp_tx_filt_mac_lengthtype_reg.bf.length_type = ts_engine->eth_type;
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_lengthtype_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_mac_lengthtype_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da0_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_mac_da0_reg));
+	ptp_tx_filt_mac_da0_reg.bf.mac_addr = (ts_engine->dmac_addr.uc[0] << 8) |
+		ts_engine->dmac_addr.uc[1];
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da0_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_mac_da0_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da1_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_mac_da1_reg));
+	ptp_tx_filt_mac_da1_reg.bf.mac_addr = (ts_engine->dmac_addr.uc[2] << 8) |
+		ts_engine->dmac_addr.uc[3];
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da1_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_mac_da1_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da2_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_mac_da2_reg));
+	ptp_tx_filt_mac_da2_reg.bf.mac_addr = (ts_engine->dmac_addr.uc[4] << 8) |
+		ts_engine->dmac_addr.uc[5];
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da2_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_mac_da2_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_layer4_protocol_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_layer4_protocol_reg));
+	ptp_tx_filt_layer4_protocol_reg.bf.l4_protocol = ts_engine->ipv4_l4_proto;
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_layer4_protocol_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_layer4_protocol_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv4_da0_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv4_da0_reg));
+	ptp_tx_filt_ipv4_da0_reg.bf.ip_addr = ts_engine->ipv4_dip >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv4_da0_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_ipv4_da0_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv4_da1_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv4_da1_reg));
+	ptp_tx_filt_ipv4_da1_reg.bf.ip_addr = ts_engine->ipv4_dip & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv4_da1_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_ipv4_da1_reg));;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da0_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da0_reg));
+	ptp_tx_filt_ipv6_da0_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[0] >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da0_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da0_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da1_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da1_reg));
+	ptp_tx_filt_ipv6_da1_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[0] & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da1_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da1_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da2_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da2_reg));
+	ptp_tx_filt_ipv6_da2_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[1] >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da2_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da2_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da3_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da3_reg));
+	ptp_tx_filt_ipv6_da3_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[1] & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da3_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da3_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da4_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da4_reg));
+	ptp_tx_filt_ipv6_da4_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[2] >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da4_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da4_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da5_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da5_reg));
+	ptp_tx_filt_ipv6_da5_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[2] & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da5_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da5_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da6_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da6_reg));
+	ptp_tx_filt_ipv6_da6_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[3] >> 16;
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da6_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da6_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da7_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da7_reg));
+	ptp_tx_filt_ipv6_da7_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[3] & 0xffff;
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da7_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da7_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_udp_port_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_udp_port_reg));
+	ptp_tx_filt_udp_port_reg.bf.udp_port = ts_engine->udp_dport;
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_udp_port_reg_set(dev_id,
+				phy_id, &ptp_tx_filt_udp_port_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_0_reg_get(dev_id,
+				phy_id, &ptp_loc_mac_addr_0_reg));
+	ptp_loc_mac_addr_0_reg.bf.mac_addr = (ts_engine->y1731_mac_addr.uc[0] << 8) |
+		ts_engine->y1731_mac_addr.uc[1];
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_0_reg_set(dev_id,
+				phy_id, &ptp_loc_mac_addr_0_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_1_reg_get(dev_id,
+				phy_id, &ptp_loc_mac_addr_1_reg));
+	ptp_loc_mac_addr_1_reg.bf.mac_addr = (ts_engine->y1731_mac_addr.uc[2] << 8) |
+		ts_engine->y1731_mac_addr.uc[3];
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_1_reg_set(dev_id,
+				phy_id, &ptp_loc_mac_addr_1_reg));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_2_reg_get(dev_id,
+				phy_id, &ptp_loc_mac_addr_2_reg));
+	ptp_loc_mac_addr_2_reg.bf.mac_addr = (ts_engine->y1731_mac_addr.uc[4] << 8) |
+		ts_engine->y1731_mac_addr.uc[5];
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_2_reg_set(dev_id,
+				phy_id, &ptp_loc_mac_addr_2_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_enhanced_timestamp_engine_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_direction_t direction,
+		fal_ptp_enhanced_ts_engine_t *ts_engine)
+{
+	if (direction == FAL_RX_DIRECTION)
+	{
+		return _qca808x_phy_ptp_enhanced_timestamp_engine_rx_set(dev_id, phy_id, ts_engine);
+	}
+	else
+	{
+		return _qca808x_phy_ptp_enhanced_timestamp_engine_tx_set(dev_id, phy_id, ts_engine);
+	}
+
+	return SW_BAD_PARAM;
+}
+
+sw_error_t
+_qca808x_phy_ptp_enhanced_timestamp_engine_rx_com_ts_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_ptp_enhanced_ts_engine_t *ts_engine)
+{
+	sw_error_t ret = SW_OK;
+
+	union ptp_rx_com_timestamp0_reg_u ptp_rx_com_timestamp0_reg = {0};
+	union ptp_rx_com_timestamp1_reg_u ptp_rx_com_timestamp1_reg = {0};
+	union ptp_rx_com_timestamp2_reg_u ptp_rx_com_timestamp2_reg = {0};
+	union ptp_rx_com_timestamp3_reg_u ptp_rx_com_timestamp3_reg = {0};
+	union ptp_rx_com_timestamp4_reg_u ptp_rx_com_timestamp4_reg = {0};
+	union ptp_rx_com_frac_nano_reg_u ptp_rx_com_frac_nano_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp0_reg_get(dev_id,
+				phy_id, &ptp_rx_com_timestamp0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp1_reg_get(dev_id,
+				phy_id, &ptp_rx_com_timestamp1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp2_reg_get(dev_id,
+				phy_id, &ptp_rx_com_timestamp2_reg));
+	ts_engine->timestamp.seconds =
+		((a_int64_t)ptp_rx_com_timestamp0_reg.bf.com_ts << 32) |
+		(ptp_rx_com_timestamp1_reg.bf.com_ts << 16) | ptp_rx_com_timestamp2_reg.bf.com_ts;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp3_reg_get(dev_id,
+				phy_id, &ptp_rx_com_timestamp3_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp4_reg_get(dev_id,
+				phy_id, &ptp_rx_com_timestamp4_reg));
+	ts_engine->timestamp.nanoseconds = (ptp_rx_com_timestamp3_reg.bf.com_ts << 16) |
+		ptp_rx_com_timestamp4_reg.bf.com_ts;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_frac_nano_reg_get(dev_id,
+				phy_id, &ptp_rx_com_frac_nano_reg));
+	ts_engine->timestamp.fracnanoseconds = ptp_rx_com_frac_nano_reg.bf.frac_nano;
+
+	return ret;
+}
+
+sw_error_t
+_qca808x_phy_ptp_enhanced_timestamp_engine_rx_com_ts_pre_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		fal_ptp_enhanced_ts_engine_t *ts_engine)
+{
+	sw_error_t ret = SW_OK;
+	union ptp_rx_com_timestamp_pre0_reg_u ptp_rx_com_timestamp_pre0_reg = {0};
+	union ptp_rx_com_timestamp_pre1_reg_u ptp_rx_com_timestamp_pre1_reg = {0};
+	union ptp_rx_com_timestamp_pre2_reg_u ptp_rx_com_timestamp_pre2_reg = {0};
+	union ptp_rx_com_timestamp_pre3_reg_u ptp_rx_com_timestamp_pre3_reg = {0};
+	union ptp_rx_com_timestamp_pre4_reg_u ptp_rx_com_timestamp_pre4_reg = {0};
+	union ptp_rx_com_frac_nano_pre_reg_u ptp_rx_com_frac_nano_pre_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp_pre0_reg_get(dev_id,
+				phy_id, &ptp_rx_com_timestamp_pre0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp_pre1_reg_get(dev_id,
+				phy_id, &ptp_rx_com_timestamp_pre1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp_pre2_reg_get(dev_id,
+				phy_id, &ptp_rx_com_timestamp_pre2_reg));
+	ts_engine->timestamp_pre.seconds =
+		((a_int64_t)ptp_rx_com_timestamp_pre0_reg.bf.com_ts_pre << 32) |
+		(ptp_rx_com_timestamp_pre1_reg.bf.com_ts_pre << 16) |
+		ptp_rx_com_timestamp_pre2_reg.bf.com_ts_pre;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp_pre3_reg_get(dev_id,
+				phy_id, &ptp_rx_com_timestamp_pre3_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp_pre4_reg_get(dev_id,
+				phy_id, &ptp_rx_com_timestamp_pre4_reg));
+	ts_engine->timestamp_pre.nanoseconds =
+		(ptp_rx_com_timestamp_pre3_reg.bf.com_ts_pre << 16) |
+		ptp_rx_com_timestamp_pre4_reg.bf.com_ts_pre;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_frac_nano_pre_reg_get(dev_id,
+				phy_id, &ptp_rx_com_frac_nano_pre_reg));
+	ts_engine->timestamp_pre.fracnanoseconds =
+		ptp_rx_com_frac_nano_pre_reg.bf.frac_nano_pre;
+
+	return ret;
+}
+
+sw_error_t
+_qca808x_phy_ptp_enhanced_timestamp_engine_rx_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_enhanced_ts_engine_t *ts_engine)
+{
+	sw_error_t ret = SW_OK;
+	union ptp_rx_com_ts_ctrl_reg_u ctrl_reg = {0};
+	union ptp_rx_filt_mac_da0_reg_u ptp_rx_filt_mac_da0_reg = {0};
+	union ptp_rx_filt_mac_da1_reg_u ptp_rx_filt_mac_da1_reg = {0};
+	union ptp_rx_filt_mac_da2_reg_u ptp_rx_filt_mac_da2_reg = {0};
+	union ptp_rx_filt_ipv4_da0_reg_u ptp_rx_filt_ipv4_da0_reg = {0};
+	union ptp_rx_filt_ipv4_da1_reg_u ptp_rx_filt_ipv4_da1_reg = {0};
+	union ptp_rx_filt_ipv6_da0_reg_u ptp_rx_filt_ipv6_da0_reg = {0};
+	union ptp_rx_filt_ipv6_da1_reg_u ptp_rx_filt_ipv6_da1_reg = {0};
+	union ptp_rx_filt_ipv6_da2_reg_u ptp_rx_filt_ipv6_da2_reg = {0};
+	union ptp_rx_filt_ipv6_da3_reg_u ptp_rx_filt_ipv6_da3_reg = {0};
+	union ptp_rx_filt_ipv6_da4_reg_u ptp_rx_filt_ipv6_da4_reg = {0};
+	union ptp_rx_filt_ipv6_da5_reg_u ptp_rx_filt_ipv6_da5_reg = {0};
+	union ptp_rx_filt_ipv6_da6_reg_u ptp_rx_filt_ipv6_da6_reg = {0};
+	union ptp_rx_filt_ipv6_da7_reg_u ptp_rx_filt_ipv6_da7_reg = {0};
+	union ptp_rx_filt_mac_lengthtype_reg_u ptp_rx_filt_mac_lengthtype_reg = {0};
+	union ptp_rx_filt_layer4_protocol_reg_u ptp_rx_filt_layer4_protocol_reg = {0};
+	union ptp_rx_filt_udp_port_reg_u ptp_rx_filt_udp_port_reg = {0};
+	union ptp_rx_com_ts_status_reg_u ptp_rx_com_ts_status_reg = {0};
+	union ptp_rx_com_ts_status_pre_reg_u ptp_rx_com_ts_status_pre_reg = {0};
+	union ptp_rx_y1731_identify_reg_u ptp_rx_y1731_identify_reg = {0};
+	union ptp_rx_y1731_identify_pre_reg_u ptp_rx_y1731_identify_pre_reg = {0};
+
+	union ptp_loc_mac_addr_0_reg_u ptp_loc_mac_addr_0_reg = {0};
+	union ptp_loc_mac_addr_1_reg_u ptp_loc_mac_addr_1_reg = {0};
+	union ptp_loc_mac_addr_2_reg_u ptp_loc_mac_addr_2_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id,
+				phy_id, &ctrl_reg));
+	ts_engine->filt_en = ctrl_reg.bf.filt_en;
+	ts_engine->enhance_ts_conf_bmp = ctrl_reg.bf.mac_lengthtype_en |
+	(ctrl_reg.bf.mac_da_en << (PTP_RX_COM_TS_CTRL_REG_MAC_DA_EN_OFFSET-1)) |
+	(ctrl_reg.bf.mac_ptp_filt_en << (PTP_RX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_OFFSET-1)) |
+	(ctrl_reg.bf.
+	 ipv4_layer4_protocol_en << (PTP_RX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_OFFSET-1)) |
+	(ctrl_reg.bf.ipv4_da_en << (PTP_RX_COM_TS_CTRL_REG_IPV4_DA_EN_OFFSET-1)) |
+	(ctrl_reg.bf.ipv4_ptp_filt_en << (PTP_RX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_OFFSET-1)) |
+	(ctrl_reg.bf.ipv6_next_header_en << (PTP_RX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_OFFSET-1)) |
+	(ctrl_reg.bf.ipv6_da_filt_en << (PTP_RX_COM_TS_CTRL_REG_IPV6_DA_FILT_EN_OFFSET-1)) |
+	(ctrl_reg.bf.ipv6_ptp_filt_en << (PTP_RX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_OFFSET-1)) |
+	(ctrl_reg.bf.udp_dport_en << (PTP_RX_COM_TS_CTRL_REG_UDP_DPORT_EN_OFFSET-1)) |
+	(ctrl_reg.bf.
+	 udp_ptp_event_filt_en << (PTP_RX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_OFFSET-1)) |
+	(ctrl_reg.bf.y1731_en << (PTP_RX_COM_TS_CTRL_REG_Y1731_EN_OFFSET-1)) |
+	(ctrl_reg.bf.y1731_insert_ts_en << (PTP_RX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_OFFSET-1)) |
+	(ctrl_reg.bf.y1731_da_chk_en << (PTP_RX_COM_TS_CTRL_REG_Y1731_DA_CHK_EN_OFFSET-1));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_lengthtype_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_mac_lengthtype_reg));
+	ts_engine->eth_type = ptp_rx_filt_mac_lengthtype_reg.bf.length_type;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da0_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_mac_da0_reg));
+	ts_engine->dmac_addr.uc[0] = ptp_rx_filt_mac_da0_reg.bf.mac_addr >> 8;
+	ts_engine->dmac_addr.uc[1] = ptp_rx_filt_mac_da0_reg.bf.mac_addr & 0xff;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da1_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_mac_da1_reg));
+	ts_engine->dmac_addr.uc[2] = ptp_rx_filt_mac_da1_reg.bf.mac_addr >> 8;
+	ts_engine->dmac_addr.uc[3] = ptp_rx_filt_mac_da1_reg.bf.mac_addr & 0xff;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da2_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_mac_da2_reg));
+	ts_engine->dmac_addr.uc[4] = ptp_rx_filt_mac_da2_reg.bf.mac_addr >> 8;
+	ts_engine->dmac_addr.uc[5] = ptp_rx_filt_mac_da2_reg.bf.mac_addr & 0xff;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_layer4_protocol_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_layer4_protocol_reg));
+	ts_engine->ipv4_l4_proto = ptp_rx_filt_layer4_protocol_reg.bf.l4_protocol;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv4_da0_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv4_da0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv4_da1_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv4_da1_reg));
+	ts_engine->ipv4_dip = (ptp_rx_filt_ipv4_da0_reg.bf.ip_addr << 16) |
+		ptp_rx_filt_ipv4_da1_reg.bf.ip_addr;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da0_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da1_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da1_reg));
+	ts_engine->ipv6_dip.ul[0] = (ptp_rx_filt_ipv6_da0_reg.bf.ip_addr << 16) |
+		ptp_rx_filt_ipv6_da1_reg.bf.ip_addr;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da2_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da2_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da3_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da3_reg));
+	ts_engine->ipv6_dip.ul[1] = (ptp_rx_filt_ipv6_da2_reg.bf.ip_addr << 16) |
+		ptp_rx_filt_ipv6_da3_reg.bf.ip_addr;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da4_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da4_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da5_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da5_reg));
+	ts_engine->ipv6_dip.ul[2] = (ptp_rx_filt_ipv6_da4_reg.bf.ip_addr << 16) |
+		ptp_rx_filt_ipv6_da5_reg.bf.ip_addr;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da6_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da6_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da7_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_ipv6_da7_reg));
+	ts_engine->ipv6_dip.ul[3] = (ptp_rx_filt_ipv6_da6_reg.bf.ip_addr << 16) |
+		ptp_rx_filt_ipv6_da7_reg.bf.ip_addr;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_udp_port_reg_get(dev_id,
+				phy_id, &ptp_rx_filt_udp_port_reg));
+	ts_engine->udp_dport = ptp_rx_filt_udp_port_reg.bf.udp_port;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_0_reg_get(dev_id,
+				phy_id, &ptp_loc_mac_addr_0_reg));
+	ts_engine->y1731_mac_addr.uc[0] = ptp_loc_mac_addr_0_reg.bf.mac_addr >> 8;
+	ts_engine->y1731_mac_addr.uc[1] = ptp_loc_mac_addr_0_reg.bf.mac_addr & 0xff;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_1_reg_get(dev_id,
+				phy_id, &ptp_loc_mac_addr_1_reg));
+	ts_engine->y1731_mac_addr.uc[2] = ptp_loc_mac_addr_1_reg.bf.mac_addr >> 8;
+	ts_engine->y1731_mac_addr.uc[3] = ptp_loc_mac_addr_1_reg.bf.mac_addr & 0xff;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_2_reg_get(dev_id,
+				phy_id, &ptp_loc_mac_addr_2_reg));
+	ts_engine->y1731_mac_addr.uc[4] = ptp_loc_mac_addr_2_reg.bf.mac_addr >> 8;
+	ts_engine->y1731_mac_addr.uc[5] = ptp_loc_mac_addr_2_reg.bf.mac_addr & 0xff;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_ts_status_reg_get(dev_id,
+				phy_id, &ptp_rx_com_ts_status_reg));
+	ts_engine->enhance_ts_status_bmp = ptp_rx_com_ts_status_reg.bf.mac_lengthtype |
+		(ptp_rx_com_ts_status_reg.bf.mac_da <<
+		 PTP_RX_COM_TS_STATUS_REG_MAC_DA_OFFSET) |
+		(ptp_rx_com_ts_status_reg.bf.mac_ptp_prim_addr <<
+		 PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_OFFSET) |
+		(ptp_rx_com_ts_status_reg.bf.mac_ptp_pdelay_addr <<
+		 PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_OFFSET) |
+		(ptp_rx_com_ts_status_reg.bf.ipv4_layer4_protocol <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_OFFSET) |
+		(ptp_rx_com_ts_status_reg.bf.ipv4_da <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV4_DA_OFFSET) |
+		(ptp_rx_com_ts_status_reg.bf.ipv4_ptp_prim_addr <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_OFFSET) |
+		(ptp_rx_com_ts_status_reg.bf.ipv4_ptp_pdelay_addr <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_OFFSET) |
+		(ptp_rx_com_ts_status_reg.bf.ipv6_next_header <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_OFFSET) |
+		(ptp_rx_com_ts_status_reg.bf.ipv6_da <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV6_DA_OFFSET) |
+		(ptp_rx_com_ts_status_reg.bf.ipv6_ptp_prim_addr <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_OFFSET) |
+		(ptp_rx_com_ts_status_reg.bf.ipv6_ptp_pdelay_addr <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_OFFSET) |
+		(ptp_rx_com_ts_status_reg.bf.udp_dport <<
+		 PTP_RX_COM_TS_STATUS_REG_UDP_DPORT_OFFSET) |
+		(ptp_rx_com_ts_status_reg.bf.udp_ptp_event_dport <<
+		 PTP_RX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_OFFSET) |
+		(ptp_rx_com_ts_status_reg.bf.y1731_mach <<
+		 PTP_RX_COM_TS_STATUS_REG_Y1731_MACH_OFFSET);
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_com_ts_status_pre_reg_get(dev_id,
+				phy_id, &ptp_rx_com_ts_status_pre_reg));
+	ts_engine->enhance_ts_status_pre_bmp = ptp_rx_com_ts_status_pre_reg.bf.mac_lengthtype |
+		(ptp_rx_com_ts_status_pre_reg.bf.mac_da <<
+		 PTP_RX_COM_TS_STATUS_REG_MAC_DA_OFFSET) |
+		(ptp_rx_com_ts_status_pre_reg.bf.mac_ptp_prim_addr <<
+		 PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_OFFSET) |
+		(ptp_rx_com_ts_status_pre_reg.bf.mac_ptp_pdelay_addr <<
+		 PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_OFFSET) |
+		(ptp_rx_com_ts_status_pre_reg.bf.ipv4_layer4_protocol <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_OFFSET) |
+		(ptp_rx_com_ts_status_pre_reg.bf.ipv4_da <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV4_DA_OFFSET) |
+		(ptp_rx_com_ts_status_pre_reg.bf.ipv4_ptp_prim_addr <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_OFFSET) |
+		(ptp_rx_com_ts_status_pre_reg.bf.ipv4_ptp_pdelay_addr <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_OFFSET) |
+		(ptp_rx_com_ts_status_pre_reg.bf.ipv6_next_header <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_OFFSET) |
+		(ptp_rx_com_ts_status_pre_reg.bf.ipv6_da <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV6_DA_OFFSET) |
+		(ptp_rx_com_ts_status_pre_reg.bf.ipv6_ptp_prim_addr <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_OFFSET) |
+		(ptp_rx_com_ts_status_pre_reg.bf.ipv6_ptp_pdelay_addr <<
+		 PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_OFFSET) |
+		(ptp_rx_com_ts_status_pre_reg.bf.udp_dport <<
+		 PTP_RX_COM_TS_STATUS_REG_UDP_DPORT_OFFSET) |
+		(ptp_rx_com_ts_status_pre_reg.bf.udp_ptp_event_dport <<
+		 PTP_RX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_OFFSET) |
+		(ptp_rx_com_ts_status_pre_reg.bf.y1731_mach <<
+		 PTP_RX_COM_TS_STATUS_REG_Y1731_MACH_OFFSET);
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_y1731_identify_reg_get(dev_id,
+				phy_id, &ptp_rx_y1731_identify_reg));
+	ts_engine->y1731_identity = ptp_rx_y1731_identify_reg.bf.identify;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_rx_y1731_identify_pre_reg_get(dev_id,
+				phy_id, &ptp_rx_y1731_identify_pre_reg));
+	ts_engine->y1731_identity_pre = ptp_rx_y1731_identify_pre_reg.bf.identify_pre;
+
+	ret = _qca808x_phy_ptp_enhanced_timestamp_engine_rx_com_ts_get(dev_id, phy_id,
+			ts_engine);
+	if (ret != SW_OK)
+	{
+		return ret;
+	}
+
+	ret = _qca808x_phy_ptp_enhanced_timestamp_engine_rx_com_ts_pre_get(dev_id, phy_id,
+			ts_engine);
+
+	return ret;
+}
+
+sw_error_t
+_qca808x_phy_ptp_enhanced_timestamp_engine_tx_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_enhanced_ts_engine_t *ts_engine)
+{
+	union ptp_tx_com_ts_ctrl_reg_u ctrl_reg = {0};
+	union ptp_tx_filt_mac_da0_reg_u ptp_tx_filt_mac_da0_reg = {0};
+	union ptp_tx_filt_mac_da1_reg_u ptp_tx_filt_mac_da1_reg = {0};
+	union ptp_tx_filt_mac_da2_reg_u ptp_tx_filt_mac_da2_reg = {0};
+	union ptp_tx_filt_ipv4_da0_reg_u ptp_tx_filt_ipv4_da0_reg = {0};
+	union ptp_tx_filt_ipv4_da1_reg_u ptp_tx_filt_ipv4_da1_reg = {0};
+	union ptp_tx_filt_ipv6_da0_reg_u ptp_tx_filt_ipv6_da0_reg = {0};
+	union ptp_tx_filt_ipv6_da1_reg_u ptp_tx_filt_ipv6_da1_reg = {0};
+	union ptp_tx_filt_ipv6_da2_reg_u ptp_tx_filt_ipv6_da2_reg = {0};
+	union ptp_tx_filt_ipv6_da3_reg_u ptp_tx_filt_ipv6_da3_reg = {0};
+	union ptp_tx_filt_ipv6_da4_reg_u ptp_tx_filt_ipv6_da4_reg = {0};
+	union ptp_tx_filt_ipv6_da5_reg_u ptp_tx_filt_ipv6_da5_reg = {0};
+	union ptp_tx_filt_ipv6_da6_reg_u ptp_tx_filt_ipv6_da6_reg = {0};
+	union ptp_tx_filt_ipv6_da7_reg_u ptp_tx_filt_ipv6_da7_reg = {0};
+	union ptp_tx_filt_mac_lengthtype_reg_u ptp_tx_filt_mac_lengthtype_reg = {0};
+	union ptp_tx_filt_layer4_protocol_reg_u ptp_tx_filt_layer4_protocol_reg = {0};
+	union ptp_tx_filt_udp_port_reg_u ptp_tx_filt_udp_port_reg = {0};
+	union ptp_tx_com_ts_status_reg_u ptp_tx_com_ts_status_reg = {0};
+	union ptp_tx_com_timestamp0_reg_u ptp_tx_com_timestamp0_reg = {0};
+	union ptp_tx_com_timestamp1_reg_u ptp_tx_com_timestamp1_reg = {0};
+	union ptp_tx_com_timestamp2_reg_u ptp_tx_com_timestamp2_reg = {0};
+	union ptp_tx_com_timestamp3_reg_u ptp_tx_com_timestamp3_reg = {0};
+	union ptp_tx_com_timestamp4_reg_u ptp_tx_com_timestamp4_reg = {0};
+	union ptp_tx_com_frac_nano_reg_u ptp_tx_com_frac_nano_reg = {0};
+	union ptp_tx_y1731_identify_reg_u ptp_tx_y1731_identify_reg = {0};
+
+	union ptp_loc_mac_addr_0_reg_u ptp_loc_mac_addr_0_reg = {0};
+	union ptp_loc_mac_addr_1_reg_u ptp_loc_mac_addr_1_reg = {0};
+	union ptp_loc_mac_addr_2_reg_u ptp_loc_mac_addr_2_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id,
+				phy_id, &ctrl_reg));
+	ts_engine->filt_en = ctrl_reg.bf.filt_en;
+	ts_engine->enhance_ts_conf_bmp = ctrl_reg.bf.mac_lengthtype_en |
+	(ctrl_reg.bf.mac_da_en << (PTP_TX_COM_TS_CTRL_REG_MAC_DA_EN_OFFSET-1)) |
+	(ctrl_reg.bf.mac_ptp_filt_en << (PTP_TX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_OFFSET-1)) |
+	(ctrl_reg.bf.
+	 ipv4_layer4_protocol_en << (PTP_TX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_OFFSET-1)) |
+	(ctrl_reg.bf.ipv4_da_en << (PTP_TX_COM_TS_CTRL_REG_IPV4_DA_EN_OFFSET-1)) |
+	(ctrl_reg.bf.ipv4_ptp_filt_en << (PTP_TX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_OFFSET-1)) |
+	(ctrl_reg.bf.ipv6_next_header_en << (PTP_TX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_OFFSET-1)) |
+	(ctrl_reg.bf.ipv6_da_en << (PTP_TX_COM_TS_CTRL_REG_IPV6_DA_EN_OFFSET-1)) |
+	(ctrl_reg.bf.ipv6_ptp_filt_en << (PTP_TX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_OFFSET-1)) |
+	(ctrl_reg.bf.udp_dport_en << (PTP_TX_COM_TS_CTRL_REG_UDP_DPORT_EN_OFFSET-1)) |
+	(ctrl_reg.bf.
+	 udp_ptp_event_filt_en << (PTP_TX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_OFFSET-1)) |
+	(ctrl_reg.bf.y1731_en << (PTP_TX_COM_TS_CTRL_REG_Y1731_EN_OFFSET-1)) |
+	(ctrl_reg.bf.y1731_insert_ts_en << (PTP_TX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_OFFSET-1)) |
+	(ctrl_reg.bf.y1731_sa_chk_en << (PTP_TX_COM_TS_CTRL_REG_Y1731_SA_CHK_EN_OFFSET-1));
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_lengthtype_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_mac_lengthtype_reg));
+	ts_engine->eth_type = ptp_tx_filt_mac_lengthtype_reg.bf.length_type;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da0_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_mac_da0_reg));
+	ts_engine->dmac_addr.uc[0] = ptp_tx_filt_mac_da0_reg.bf.mac_addr >> 8;
+	ts_engine->dmac_addr.uc[1] = ptp_tx_filt_mac_da0_reg.bf.mac_addr & 0xff;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da1_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_mac_da1_reg));
+	ts_engine->dmac_addr.uc[2] = ptp_tx_filt_mac_da1_reg.bf.mac_addr >> 8;
+	ts_engine->dmac_addr.uc[3] = ptp_tx_filt_mac_da1_reg.bf.mac_addr & 0xff;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da2_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_mac_da2_reg));
+	ts_engine->dmac_addr.uc[4] = ptp_tx_filt_mac_da2_reg.bf.mac_addr >> 8;
+	ts_engine->dmac_addr.uc[5] = ptp_tx_filt_mac_da2_reg.bf.mac_addr & 0xff;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_layer4_protocol_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_layer4_protocol_reg));
+	ts_engine->ipv4_l4_proto = ptp_tx_filt_layer4_protocol_reg.bf.l4_protocol;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv4_da0_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv4_da0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv4_da1_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv4_da1_reg));
+	ts_engine->ipv4_dip = (ptp_tx_filt_ipv4_da0_reg.bf.ip_addr << 16) |
+		ptp_tx_filt_ipv4_da1_reg.bf.ip_addr;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da0_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da1_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da1_reg));
+	ts_engine->ipv6_dip.ul[0] = (ptp_tx_filt_ipv6_da0_reg.bf.ip_addr << 16) |
+		ptp_tx_filt_ipv6_da1_reg.bf.ip_addr;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da2_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da2_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da3_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da3_reg));
+	ts_engine->ipv6_dip.ul[1] = (ptp_tx_filt_ipv6_da2_reg.bf.ip_addr << 16) |
+		ptp_tx_filt_ipv6_da3_reg.bf.ip_addr;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da4_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da4_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da5_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da5_reg));
+	ts_engine->ipv6_dip.ul[2] = (ptp_tx_filt_ipv6_da4_reg.bf.ip_addr << 16) |
+		ptp_tx_filt_ipv6_da5_reg.bf.ip_addr;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da6_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da6_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da7_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_ipv6_da7_reg));
+	ts_engine->ipv6_dip.ul[3] = (ptp_tx_filt_ipv6_da6_reg.bf.ip_addr << 16) |
+		ptp_tx_filt_ipv6_da7_reg.bf.ip_addr;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_udp_port_reg_get(dev_id,
+				phy_id, &ptp_tx_filt_udp_port_reg));
+	ts_engine->udp_dport = ptp_tx_filt_udp_port_reg.bf.udp_port;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_0_reg_get(dev_id,
+				phy_id, &ptp_loc_mac_addr_0_reg));
+	ts_engine->y1731_mac_addr.uc[0] = ptp_loc_mac_addr_0_reg.bf.mac_addr >> 8;
+	ts_engine->y1731_mac_addr.uc[1] = ptp_loc_mac_addr_0_reg.bf.mac_addr & 0xff;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_1_reg_get(dev_id,
+				phy_id, &ptp_loc_mac_addr_1_reg));
+	ts_engine->y1731_mac_addr.uc[2] = ptp_loc_mac_addr_1_reg.bf.mac_addr >> 8;
+	ts_engine->y1731_mac_addr.uc[3] = ptp_loc_mac_addr_1_reg.bf.mac_addr & 0xff;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_2_reg_get(dev_id,
+				phy_id, &ptp_loc_mac_addr_2_reg));
+	ts_engine->y1731_mac_addr.uc[4] = ptp_loc_mac_addr_2_reg.bf.mac_addr >> 8;
+	ts_engine->y1731_mac_addr.uc[5] = ptp_loc_mac_addr_2_reg.bf.mac_addr & 0xff;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_com_ts_status_reg_get(dev_id,
+				phy_id, &ptp_tx_com_ts_status_reg));
+	ts_engine->enhance_ts_status_bmp = ptp_tx_com_ts_status_reg.bf.mac_lengthtype |
+		(ptp_tx_com_ts_status_reg.bf.mac_da <<
+		 PTP_TX_COM_TS_STATUS_REG_MAC_DA_OFFSET) |
+		(ptp_tx_com_ts_status_reg.bf.mac_ptp_prim_addr <<
+		 PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_OFFSET) |
+		(ptp_tx_com_ts_status_reg.bf.mac_ptp_pdelay_addr <<
+		 PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_OFFSET) |
+		(ptp_tx_com_ts_status_reg.bf.ipv4_layer4_protocol <<
+		 PTP_TX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_OFFSET) |
+		(ptp_tx_com_ts_status_reg.bf.ipv4_da <<
+		 PTP_TX_COM_TS_STATUS_REG_IPV4_DA_OFFSET) |
+		(ptp_tx_com_ts_status_reg.bf.ipv4_ptp_prim_addr <<
+		 PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_OFFSET) |
+		(ptp_tx_com_ts_status_reg.bf.ipv4_ptp_pdelay_addr <<
+		 PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_OFFSET) |
+		(ptp_tx_com_ts_status_reg.bf.ipv6_next_header <<
+		 PTP_TX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_OFFSET) |
+		(ptp_tx_com_ts_status_reg.bf.ipv6_da <<
+		 PTP_TX_COM_TS_STATUS_REG_IPV6_DA_OFFSET) |
+		(ptp_tx_com_ts_status_reg.bf.ipv6_ptp_prim_addr <<
+		 PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_OFFSET) |
+		(ptp_tx_com_ts_status_reg.bf.ipv6_ptp_pdelay_addr <<
+		 PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_OFFSET) |
+		(ptp_tx_com_ts_status_reg.bf.udp_dport <<
+		 PTP_TX_COM_TS_STATUS_REG_UDP_DPORT_OFFSET) |
+		(ptp_tx_com_ts_status_reg.bf.udp_ptp_event_dport <<
+		 PTP_TX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_OFFSET) |
+		(ptp_tx_com_ts_status_reg.bf.y1731_mach <<
+		 PTP_TX_COM_TS_STATUS_REG_Y1731_MACH_OFFSET);
+
+	ts_engine->enhance_ts_status_pre_bmp = 0;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_y1731_identify_reg_get(dev_id,
+				phy_id, &ptp_tx_y1731_identify_reg));
+	ts_engine->y1731_identity = ptp_tx_y1731_identify_reg.bf.identify;
+
+	ts_engine->y1731_identity_pre = 0;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_com_timestamp0_reg_get(dev_id,
+				phy_id, &ptp_tx_com_timestamp0_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_com_timestamp1_reg_get(dev_id,
+				phy_id, &ptp_tx_com_timestamp1_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_com_timestamp2_reg_get(dev_id,
+				phy_id, &ptp_tx_com_timestamp2_reg));
+	ts_engine->timestamp.seconds =
+		((a_int64_t)ptp_tx_com_timestamp0_reg.bf.com_ts << 32) |
+		(ptp_tx_com_timestamp1_reg.bf.com_ts << 16) |
+		ptp_tx_com_timestamp2_reg.bf.com_ts;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_com_timestamp3_reg_get(dev_id,
+				phy_id, &ptp_tx_com_timestamp3_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_com_timestamp4_reg_get(dev_id,
+				phy_id, &ptp_tx_com_timestamp4_reg));
+	ts_engine->timestamp.nanoseconds = (ptp_tx_com_timestamp3_reg.bf.com_ts << 16) |
+		ptp_tx_com_timestamp4_reg.bf.com_ts;
+
+	SW_RTN_ON_ERROR(qca808x_ptp_tx_com_frac_nano_reg_get(dev_id,
+				phy_id, &ptp_tx_com_frac_nano_reg));
+	ts_engine->timestamp.fracnanoseconds = ptp_tx_com_frac_nano_reg.bf.frac_nano;
+
+	ts_engine->timestamp_pre.seconds = 0;
+	ts_engine->timestamp_pre.nanoseconds = 0;
+	ts_engine->timestamp_pre.fracnanoseconds = 0;
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_enhanced_timestamp_engine_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_direction_t direction,
+		fal_ptp_enhanced_ts_engine_t *ts_engine)
+{
+	if (direction == FAL_RX_DIRECTION)
+	{
+		return _qca808x_phy_ptp_enhanced_timestamp_engine_rx_get(dev_id,
+				phy_id, ts_engine);
+	}
+	else
+	{
+		return _qca808x_phy_ptp_enhanced_timestamp_engine_tx_get(dev_id,
+				phy_id, ts_engine);
+	}
+
+	return SW_BAD_PARAM;
+}
+
+sw_error_t
+qca808x_phy_ptp_trigger_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_uint32_t trigger_id,
+		fal_ptp_trigger_t *triger)
+{
+	union ptp_trigger0_config_reg_u ptp_trigger0_config_reg = {0};
+	union ptp_trigger1_config_reg_u ptp_trigger1_config_reg = {0};
+	union ptp_trigger0_timestamp0_reg_u ptp_trigger0_timestamp0_reg = {0};
+	union ptp_trigger0_timestamp1_reg_u ptp_trigger0_timestamp1_reg = {0};
+	union ptp_trigger0_timestamp2_reg_u ptp_trigger0_timestamp2_reg = {0};
+	union ptp_trigger0_timestamp3_reg_u ptp_trigger0_timestamp3_reg = {0};
+	union ptp_trigger0_timestamp4_reg_u ptp_trigger0_timestamp4_reg = {0};
+	union ptp_trigger1_timestamp0_reg_u ptp_trigger1_timestamp0_reg = {0};
+	union ptp_trigger1_timestamp1_reg_u ptp_trigger1_timestamp1_reg = {0};
+	union ptp_trigger1_timestamp2_reg_u ptp_trigger1_timestamp2_reg = {0};
+	union ptp_trigger1_timestamp3_reg_u ptp_trigger1_timestamp3_reg = {0};
+	union ptp_trigger1_timestamp4_reg_u ptp_trigger1_timestamp4_reg = {0};
+
+	if (trigger_id == 0)
+	{
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger0_config_reg_get(dev_id,
+					phy_id, &ptp_trigger0_config_reg));
+		ptp_trigger0_config_reg.bf.status = triger->trigger_conf.trigger_en;
+		ptp_trigger0_config_reg.bf.force_en = triger->trigger_conf.output_force_en;
+		ptp_trigger0_config_reg.bf.force_value = triger->trigger_conf.output_force_value;
+		ptp_trigger0_config_reg.bf.pattern = triger->trigger_conf.patten_select;
+		ptp_trigger0_config_reg.bf.if_late = triger->trigger_conf.late_operation;
+		ptp_trigger0_config_reg.bf.notify = triger->trigger_conf.notify;
+		ptp_trigger0_config_reg.bf.setting = triger->trigger_conf.trigger_effect;
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger0_config_reg_set(dev_id,
+					phy_id, &ptp_trigger0_config_reg));
+
+		ptp_trigger0_timestamp0_reg.bf.ts_sec =
+			(triger->trigger_conf.tim.seconds >> 32) & 0xffff;
+		ptp_trigger0_timestamp1_reg.bf.ts_sec =
+			(triger->trigger_conf.tim.seconds >> 16) & 0xffff;
+		ptp_trigger0_timestamp2_reg.bf.ts_sec =
+			triger->trigger_conf.tim.seconds & 0xffff;
+		ptp_trigger0_timestamp3_reg.bf.ts_nsec =
+			triger->trigger_conf.tim.nanoseconds >> 16;
+		ptp_trigger0_timestamp4_reg.bf.ts_nsec =
+			triger->trigger_conf.tim.nanoseconds & 0xffff;
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp0_reg_set(dev_id,
+					phy_id, &ptp_trigger0_timestamp0_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp1_reg_set(dev_id,
+					phy_id, &ptp_trigger0_timestamp1_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp2_reg_set(dev_id,
+					phy_id, &ptp_trigger0_timestamp2_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp3_reg_set(dev_id,
+					phy_id, &ptp_trigger0_timestamp3_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp4_reg_set(dev_id,
+					phy_id, &ptp_trigger0_timestamp4_reg));
+	} else {
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger1_config_reg_get(dev_id,
+					phy_id, &ptp_trigger1_config_reg));
+		ptp_trigger1_config_reg.bf.status = triger->trigger_conf.trigger_en;
+		ptp_trigger1_config_reg.bf.force_en = triger->trigger_conf.output_force_en;
+		ptp_trigger1_config_reg.bf.force_value = triger->trigger_conf.output_force_value;
+		ptp_trigger1_config_reg.bf.pattern = triger->trigger_conf.patten_select;
+		ptp_trigger1_config_reg.bf.if_late = triger->trigger_conf.late_operation;
+		ptp_trigger1_config_reg.bf.notify = triger->trigger_conf.notify;
+		ptp_trigger1_config_reg.bf.setting = triger->trigger_conf.trigger_effect;
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger1_config_reg_set(dev_id,
+					phy_id, &ptp_trigger1_config_reg));
+
+		ptp_trigger1_timestamp0_reg.bf.ts_sec =
+			(triger->trigger_conf.tim.seconds >> 32) & 0xffff;
+		ptp_trigger1_timestamp1_reg.bf.ts_sec =
+			(triger->trigger_conf.tim.seconds >> 16) & 0xffff;
+		ptp_trigger1_timestamp2_reg.bf.ts_sec =
+			triger->trigger_conf.tim.seconds & 0xffff;
+		ptp_trigger1_timestamp3_reg.bf.ts_nsec =
+			triger->trigger_conf.tim.nanoseconds >> 16;
+		ptp_trigger1_timestamp4_reg.bf.ts_nsec =
+			triger->trigger_conf.tim.nanoseconds & 0xffff;
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp0_reg_set(dev_id,
+					phy_id, &ptp_trigger1_timestamp0_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp1_reg_set(dev_id,
+					phy_id, &ptp_trigger1_timestamp1_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp2_reg_set(dev_id,
+					phy_id, &ptp_trigger1_timestamp2_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp3_reg_set(dev_id,
+					phy_id, &ptp_trigger1_timestamp3_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp4_reg_set(dev_id,
+					phy_id, &ptp_trigger1_timestamp4_reg));
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_trigger_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_uint32_t trigger_id,
+		fal_ptp_trigger_t *triger)
+{
+	union ptp_trigger0_config_reg_u ptp_trigger0_config_reg = {0};
+	union ptp_trigger0_status_reg_u ptp_trigger0_status_reg = {0};
+	union ptp_trigger1_config_reg_u ptp_trigger1_config_reg = {0};
+	union ptp_trigger1_status_reg_u ptp_trigger1_status_reg = {0};
+	union ptp_trigger0_timestamp0_reg_u ptp_trigger0_timestamp0_reg = {0};
+	union ptp_trigger0_timestamp1_reg_u ptp_trigger0_timestamp1_reg = {0};
+	union ptp_trigger0_timestamp2_reg_u ptp_trigger0_timestamp2_reg = {0};
+	union ptp_trigger0_timestamp3_reg_u ptp_trigger0_timestamp3_reg = {0};
+	union ptp_trigger0_timestamp4_reg_u ptp_trigger0_timestamp4_reg = {0};
+	union ptp_trigger1_timestamp0_reg_u ptp_trigger1_timestamp0_reg = {0};
+	union ptp_trigger1_timestamp1_reg_u ptp_trigger1_timestamp1_reg = {0};
+	union ptp_trigger1_timestamp2_reg_u ptp_trigger1_timestamp2_reg = {0};
+	union ptp_trigger1_timestamp3_reg_u ptp_trigger1_timestamp3_reg = {0};
+	union ptp_trigger1_timestamp4_reg_u ptp_trigger1_timestamp4_reg = {0};
+
+	if (trigger_id == 0)
+	{
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger0_config_reg_get(dev_id,
+					phy_id, &ptp_trigger0_config_reg));
+		triger->trigger_conf.trigger_en = ptp_trigger0_config_reg.bf.status;
+		triger->trigger_conf.output_force_en = ptp_trigger0_config_reg.bf.force_en;
+		triger->trigger_conf.output_force_value = ptp_trigger0_config_reg.bf.force_value;
+		triger->trigger_conf.patten_select = ptp_trigger0_config_reg.bf.pattern;
+		triger->trigger_conf.late_operation = ptp_trigger0_config_reg.bf.if_late;
+		triger->trigger_conf.notify = ptp_trigger0_config_reg.bf.notify;
+		triger->trigger_conf.trigger_effect = ptp_trigger0_config_reg.bf.setting;
+
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp0_reg_get(dev_id,
+					phy_id, &ptp_trigger0_timestamp0_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp1_reg_get(dev_id,
+					phy_id, &ptp_trigger0_timestamp1_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp2_reg_get(dev_id,
+					phy_id, &ptp_trigger0_timestamp2_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp3_reg_get(dev_id,
+					phy_id, &ptp_trigger0_timestamp3_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp4_reg_get(dev_id,
+					phy_id, &ptp_trigger0_timestamp4_reg));
+		triger->trigger_conf.tim.seconds =
+			((a_int64_t)ptp_trigger0_timestamp0_reg.bf.ts_sec << 32) |
+			(ptp_trigger0_timestamp1_reg.bf.ts_sec << 16) |
+			ptp_trigger0_timestamp2_reg.bf.ts_sec;
+		triger->trigger_conf.tim.nanoseconds =
+			(ptp_trigger0_timestamp3_reg.bf.ts_nsec << 16) |
+			ptp_trigger0_timestamp4_reg.bf.ts_nsec;
+
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger0_status_reg_get(dev_id,
+					phy_id, &ptp_trigger0_status_reg));
+		triger->trigger_status.trigger_finished = ptp_trigger0_status_reg.bf.finished;
+		triger->trigger_status.trigger_active = ptp_trigger0_status_reg.bf.active;
+		triger->trigger_status.trigger_error = ptp_trigger0_status_reg.bf.error;
+	} else {
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger1_config_reg_get(dev_id,
+					phy_id, &ptp_trigger1_config_reg));
+		triger->trigger_conf.trigger_en = ptp_trigger1_config_reg.bf.status;
+		triger->trigger_conf.output_force_en = ptp_trigger1_config_reg.bf.force_en;
+		triger->trigger_conf.output_force_value = ptp_trigger1_config_reg.bf.force_value;
+		triger->trigger_conf.patten_select = ptp_trigger1_config_reg.bf.pattern;
+		triger->trigger_conf.late_operation = ptp_trigger1_config_reg.bf.if_late;
+		triger->trigger_conf.notify = ptp_trigger1_config_reg.bf.notify;
+		triger->trigger_conf.trigger_effect = ptp_trigger1_config_reg.bf.setting;
+
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp0_reg_get(dev_id,
+					phy_id, &ptp_trigger1_timestamp0_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp1_reg_get(dev_id,
+					phy_id, &ptp_trigger1_timestamp1_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp2_reg_get(dev_id,
+					phy_id, &ptp_trigger1_timestamp2_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp3_reg_get(dev_id,
+					phy_id, &ptp_trigger1_timestamp3_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp4_reg_get(dev_id,
+					phy_id, &ptp_trigger1_timestamp4_reg));
+		triger->trigger_conf.tim.seconds =
+			((a_int64_t)ptp_trigger1_timestamp0_reg.bf.ts_sec << 32) |
+			(ptp_trigger1_timestamp1_reg.bf.ts_sec << 16) |
+			ptp_trigger1_timestamp2_reg.bf.ts_sec;
+		triger->trigger_conf.tim.nanoseconds =
+			(ptp_trigger1_timestamp3_reg.bf.ts_nsec << 16) |
+			ptp_trigger1_timestamp4_reg.bf.ts_nsec;
+
+		SW_RTN_ON_ERROR(qca808x_ptp_trigger1_status_reg_get(dev_id,
+					phy_id, &ptp_trigger1_status_reg));
+		triger->trigger_status.trigger_finished = ptp_trigger1_status_reg.bf.finished;
+		triger->trigger_status.trigger_active = ptp_trigger1_status_reg.bf.active;
+		triger->trigger_status.trigger_error = ptp_trigger1_status_reg.bf.error;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_capture_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_uint32_t capture_id,
+		fal_ptp_capture_t *capture)
+{
+	union ptp_event0_config_reg_u ptp_event0_config_reg = {0};
+	union ptp_event1_config_reg_u ptp_event1_config_reg = {0};
+
+	if (capture_id == 0)
+	{
+		SW_RTN_ON_ERROR(qca808x_ptp_event0_config_reg_get(dev_id,
+					phy_id, &ptp_event0_config_reg));
+		ptp_event0_config_reg.bf.clear_stat = capture->capture_conf.status_clear;
+		ptp_event0_config_reg.bf.notify = capture->capture_conf.notify_event;
+		ptp_event0_config_reg.bf.single_cap = capture->capture_conf.single_multi_select;
+		ptp_event0_config_reg.bf.fall_en = capture->capture_conf.fall_edge_en;
+		ptp_event0_config_reg.bf.rise_en = capture->capture_conf.rise_edge_en;
+		SW_RTN_ON_ERROR(qca808x_ptp_event0_config_reg_set(dev_id,
+					phy_id, &ptp_event0_config_reg));
+	}
+	else
+	{
+		SW_RTN_ON_ERROR(qca808x_ptp_event1_config_reg_get(dev_id,
+					phy_id, &ptp_event1_config_reg));
+		ptp_event1_config_reg.bf.clear_stat = capture->capture_conf.status_clear;
+		ptp_event1_config_reg.bf.notify = capture->capture_conf.notify_event;
+		ptp_event1_config_reg.bf.single_cap = capture->capture_conf.single_multi_select;
+		ptp_event1_config_reg.bf.fall_en = capture->capture_conf.fall_edge_en;
+		ptp_event1_config_reg.bf.rise_en = capture->capture_conf.rise_edge_en;
+		SW_RTN_ON_ERROR(qca808x_ptp_event1_config_reg_set(dev_id,
+					phy_id, &ptp_event1_config_reg));
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_capture_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, a_uint32_t capture_id,
+		fal_ptp_capture_t *capture)
+{
+	union ptp_event0_config_reg_u ptp_event0_config_reg = {0};
+	union ptp_event0_status_reg_u ptp_event0_status_reg = {0};
+	union ptp_event1_config_reg_u ptp_event1_config_reg = {0};
+	union ptp_event1_status_reg_u ptp_event1_status_reg = {0};
+	union ptp_event0_timestamp0_reg_u ptp_event0_timestamp0_reg = {0};
+	union ptp_event0_timestamp1_reg_u ptp_event0_timestamp1_reg = {0};
+	union ptp_event0_timestamp2_reg_u ptp_event0_timestamp2_reg = {0};
+	union ptp_event0_timestamp3_reg_u ptp_event0_timestamp3_reg = {0};
+	union ptp_event0_timestamp4_reg_u ptp_event0_timestamp4_reg = {0};
+	union ptp_event1_timestamp0_reg_u ptp_event1_timestamp0_reg = {0};
+	union ptp_event1_timestamp1_reg_u ptp_event1_timestamp1_reg = {0};
+	union ptp_event1_timestamp2_reg_u ptp_event1_timestamp2_reg = {0};
+	union ptp_event1_timestamp3_reg_u ptp_event1_timestamp3_reg = {0};
+	union ptp_event1_timestamp4_reg_u ptp_event1_timestamp4_reg = {0};
+
+	if (capture_id == 0)
+	{
+		SW_RTN_ON_ERROR(qca808x_ptp_event0_config_reg_get(dev_id,
+					phy_id, &ptp_event0_config_reg));
+		capture->capture_conf.status_clear = ptp_event0_config_reg.bf.clear_stat;
+		capture->capture_conf.notify_event = ptp_event0_config_reg.bf.notify;
+		capture->capture_conf.single_multi_select = ptp_event0_config_reg.bf.single_cap;
+		capture->capture_conf.fall_edge_en = ptp_event0_config_reg.bf.fall_en;
+		capture->capture_conf.rise_edge_en = ptp_event0_config_reg.bf.rise_en;
+
+		SW_RTN_ON_ERROR(qca808x_ptp_event0_status_reg_get(dev_id,
+					phy_id, &ptp_event0_status_reg));
+		capture->capture_status.event_detected = ptp_event0_status_reg.bf.detected;
+		capture->capture_status.fall_rise_edge_detected =
+			ptp_event0_status_reg.bf.dir_detected;
+		capture->capture_status.single_multi_detected = ptp_event0_status_reg.bf.mul_event;
+		capture->capture_status.event_missed_cnt = ptp_event0_status_reg.bf.missed_count;
+
+		SW_RTN_ON_ERROR(qca808x_ptp_event0_timestamp0_reg_get(dev_id,
+					phy_id, &ptp_event0_timestamp0_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_event0_timestamp1_reg_get(dev_id,
+					phy_id, &ptp_event0_timestamp1_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_event0_timestamp2_reg_get(dev_id,
+					phy_id, &ptp_event0_timestamp2_reg));
+		capture->capture_status.tim.seconds =
+			((a_int64_t)ptp_event0_timestamp0_reg.bf.ts_nsec << 32) |
+			(ptp_event0_timestamp1_reg.bf.ts_nsec << 16) |
+			ptp_event0_timestamp2_reg.bf.ts_nsec;
+		SW_RTN_ON_ERROR(qca808x_ptp_event0_timestamp3_reg_get(dev_id,
+					phy_id, &ptp_event0_timestamp3_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_event0_timestamp4_reg_get(dev_id,
+					phy_id, &ptp_event0_timestamp4_reg));
+		capture->capture_status.tim.nanoseconds =
+			(ptp_event0_timestamp3_reg.bf.ts_nsec << 16) |
+			ptp_event0_timestamp4_reg.bf.ts_nsec;
+	} else {
+		SW_RTN_ON_ERROR(qca808x_ptp_event1_config_reg_get(dev_id,
+					phy_id, &ptp_event1_config_reg));
+		capture->capture_conf.status_clear = ptp_event1_config_reg.bf.clear_stat;
+		capture->capture_conf.notify_event = ptp_event1_config_reg.bf.notify;
+		capture->capture_conf.single_multi_select = ptp_event1_config_reg.bf.single_cap;
+		capture->capture_conf.fall_edge_en = ptp_event1_config_reg.bf.fall_en;
+		capture->capture_conf.rise_edge_en = ptp_event1_config_reg.bf.rise_en;
+
+		SW_RTN_ON_ERROR(qca808x_ptp_event1_status_reg_get(dev_id,
+					phy_id, &ptp_event1_status_reg));
+		capture->capture_status.event_detected = ptp_event1_status_reg.bf.detected;
+		capture->capture_status.fall_rise_edge_detected =
+			ptp_event1_status_reg.bf.dir_detected;
+		capture->capture_status.single_multi_detected = ptp_event1_status_reg.bf.mul_event;
+		capture->capture_status.event_missed_cnt = ptp_event1_status_reg.bf.missed_count;
+
+		SW_RTN_ON_ERROR(qca808x_ptp_event1_timestamp0_reg_get(dev_id,
+					phy_id, &ptp_event1_timestamp0_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_event1_timestamp1_reg_get(dev_id,
+					phy_id, &ptp_event1_timestamp1_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_event1_timestamp2_reg_get(dev_id,
+					phy_id, &ptp_event1_timestamp2_reg));
+		capture->capture_status.tim.seconds =
+			((a_int64_t)ptp_event1_timestamp0_reg.bf.ts_nsec << 32) |
+			(ptp_event1_timestamp1_reg.bf.ts_nsec << 16) |
+			ptp_event1_timestamp2_reg.bf.ts_nsec;
+		SW_RTN_ON_ERROR(qca808x_ptp_event1_timestamp3_reg_get(dev_id,
+					phy_id, &ptp_event1_timestamp3_reg));
+		SW_RTN_ON_ERROR(qca808x_ptp_event1_timestamp4_reg_get(dev_id,
+					phy_id, &ptp_event1_timestamp4_reg));
+		capture->capture_status.tim.nanoseconds =
+			(ptp_event1_timestamp3_reg.bf.ts_nsec << 16) |
+			ptp_event1_timestamp4_reg.bf.ts_nsec;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_interrupt_set(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_interrupt_t *interrupt)
+{
+	union ptp_imr_reg_u ptp_imr_reg = {0};
+	union ptp_ext_imr_reg_u ptp_ext_imr_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_imr_reg_get(dev_id, phy_id, &ptp_imr_reg));
+	ptp_imr_reg.bf.mask_bmp &= (~(0x7 << 2)) & 0xffff;
+	ptp_imr_reg.bf.mask_bmp |= (interrupt->intr_mask & 0x7) << 2;
+	SW_RTN_ON_ERROR(qca808x_ptp_imr_reg_set(dev_id, phy_id, &ptp_imr_reg));
+
+	ptp_ext_imr_reg.bf.mask_bmp = interrupt->intr_mask >> 3;
+	SW_RTN_ON_ERROR(qca808x_ptp_ext_imr_reg_set(dev_id, phy_id, &ptp_ext_imr_reg));
+
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_interrupt_get(a_uint32_t dev_id,
+		a_uint32_t phy_id, fal_ptp_interrupt_t *interrupt)
+{
+	union ptp_imr_reg_u ptp_imr_reg = {0};
+	union ptp_isr_reg_u ptp_isr_reg = {0};
+	union ptp_ext_imr_reg_u ptp_ext_imr_reg = {0};
+	union ptp_ext_isr_reg_u ptp_ext_isr_reg = {0};
+
+	SW_RTN_ON_ERROR(qca808x_ptp_imr_reg_get(dev_id, phy_id, &ptp_imr_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_ext_imr_reg_get(dev_id, phy_id, &ptp_ext_imr_reg));
+	interrupt->intr_mask = ((ptp_imr_reg.bf.mask_bmp >> 2) & 0x7) |
+			((ptp_ext_imr_reg.bf.mask_bmp & 0x7ff) << 3);
+
+	SW_RTN_ON_ERROR(qca808x_ptp_isr_reg_get(dev_id, phy_id, &ptp_isr_reg));
+	SW_RTN_ON_ERROR(qca808x_ptp_ext_isr_reg_get(dev_id, phy_id, &ptp_ext_isr_reg));
+	interrupt->intr_status = ((ptp_isr_reg.bf.status_bmp >> 2) & 0x7) |
+			((ptp_ext_isr_reg.bf.status_bmp & 0x7ff) << 3);
+
+	return SW_OK;
+}
+
+void qca808x_phy_ptp_api_ops_init(hsl_phy_ptp_ops_t *ptp_ops)
+{
+	if (!ptp_ops) {
+		return;
+	}
+	ptp_ops->phy_ptp_security_set = qca808x_phy_ptp_security_set;
+	ptp_ops->phy_ptp_link_delay_set = qca808x_phy_ptp_link_delay_set;
+	ptp_ops->phy_ptp_rx_crc_recalc_status_get = qca808x_phy_ptp_rx_crc_recalc_status_get;
+	ptp_ops->phy_ptp_tod_uart_set = qca808x_phy_ptp_tod_uart_set;
+	ptp_ops->phy_ptp_pps_signal_control_set = qca808x_phy_ptp_pps_signal_control_set;
+	ptp_ops->phy_ptp_timestamp_get = qca808x_phy_ptp_timestamp_get;
+	ptp_ops->phy_ptp_asym_correction_get = qca808x_phy_ptp_asym_correction_get;
+	ptp_ops->phy_ptp_capture_set = qca808x_phy_ptp_capture_set;
+	ptp_ops->phy_ptp_rtc_adjfreq_set = qca808x_phy_ptp_rtc_adjfreq_set;
+	ptp_ops->phy_ptp_asym_correction_set = qca808x_phy_ptp_asym_correction_set;
+	ptp_ops->phy_ptp_pkt_timestamp_set = qca808x_phy_ptp_pkt_timestamp_set;
+	ptp_ops->phy_ptp_rtc_time_get = qca808x_phy_ptp_rtc_time_get;
+	ptp_ops->phy_ptp_rtc_time_set = qca808x_phy_ptp_rtc_time_set;
+	ptp_ops->phy_ptp_pkt_timestamp_get = qca808x_phy_ptp_pkt_timestamp_get;
+	ptp_ops->phy_ptp_interrupt_set = qca808x_phy_ptp_interrupt_set;
+	ptp_ops->phy_ptp_trigger_set = qca808x_phy_ptp_trigger_set;
+	ptp_ops->phy_ptp_pps_signal_control_get = qca808x_phy_ptp_pps_signal_control_get;
+	ptp_ops->phy_ptp_capture_get = qca808x_phy_ptp_capture_get;
+	ptp_ops->phy_ptp_rx_crc_recalc_enable = qca808x_phy_ptp_rx_crc_recalc_enable;
+	ptp_ops->phy_ptp_security_get = qca808x_phy_ptp_security_get;
+	ptp_ops->phy_ptp_tod_uart_get = qca808x_phy_ptp_tod_uart_get;
+	ptp_ops->phy_ptp_rtc_time_clear = qca808x_phy_ptp_rtc_time_clear;
+	ptp_ops->phy_ptp_reference_clock_set = qca808x_phy_ptp_reference_clock_set;
+	ptp_ops->phy_ptp_output_waveform_set = qca808x_phy_ptp_output_waveform_set;
+	ptp_ops->phy_ptp_rx_timestamp_mode_set = qca808x_phy_ptp_rx_timestamp_mode_set;
+	ptp_ops->phy_ptp_grandmaster_mode_set = qca808x_phy_ptp_grandmaster_mode_set;
+	ptp_ops->phy_ptp_config_set = qca808x_phy_ptp_config_set;
+	ptp_ops->phy_ptp_trigger_get = qca808x_phy_ptp_trigger_get;
+	ptp_ops->phy_ptp_rtc_adjfreq_get = qca808x_phy_ptp_rtc_adjfreq_get;
+	ptp_ops->phy_ptp_grandmaster_mode_get = qca808x_phy_ptp_grandmaster_mode_get;
+	ptp_ops->phy_ptp_rx_timestamp_mode_get = qca808x_phy_ptp_rx_timestamp_mode_get;
+	ptp_ops->phy_ptp_rtc_adjtime_set = qca808x_phy_ptp_rtc_adjtime_set;
+	ptp_ops->phy_ptp_link_delay_get = qca808x_phy_ptp_link_delay_get;
+	ptp_ops->phy_ptp_config_get = qca808x_phy_ptp_config_get;
+	ptp_ops->phy_ptp_output_waveform_get = qca808x_phy_ptp_output_waveform_get;
+	ptp_ops->phy_ptp_interrupt_get = qca808x_phy_ptp_interrupt_get;
+	ptp_ops->phy_ptp_rtc_time_snapshot_enable = qca808x_phy_ptp_rtc_time_snapshot_enable;
+	ptp_ops->phy_ptp_reference_clock_get = qca808x_phy_ptp_reference_clock_get;
+	ptp_ops->phy_ptp_enhanced_timestamp_engine_set =
+		qca808x_phy_ptp_enhanced_timestamp_engine_set;
+	ptp_ops->phy_ptp_rtc_time_snapshot_status_get =
+		qca808x_phy_ptp_rtc_time_snapshot_status_get;
+	ptp_ops->phy_ptp_enhanced_timestamp_engine_get =
+		qca808x_phy_ptp_enhanced_timestamp_engine_get;
+	ptp_ops->phy_ptp_increment_sync_from_clock_enable =
+		qca808x_phy_ptp_increment_sync_from_clock_enable;
+	ptp_ops->phy_ptp_increment_sync_from_clock_status_get =
+		qca808x_phy_ptp_increment_sync_from_clock_status_get;
+}
diff --git a/qca-ssdk/src/hsl/phy/qca808x_ptp_api.c b/qca-ssdk/src/hsl/phy/qca808x_ptp_api.c
new file mode 100755
index 0000000..e0342e9
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/qca808x_ptp_api.c
@@ -0,0 +1,15319 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl_api.h"
+#include "hsl.h"
+#include "hsl_phy.h"
+#include "ssdk_plat.h"
+#include "qca808x_ptp_reg.h"
+#include "qca808x_ptp_api.h"
+#include "qca808x_phy.h"
+
+
+sw_error_t
+qca808x_phy_ptp_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg, a_uint32_t * val)
+{
+	*val = qca808x_phy_reg_read(dev_id, phy_id, reg);
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg, a_uint32_t val)
+{
+	return qca808x_phy_reg_write(dev_id, phy_id, reg, (a_uint16_t)val);
+}
+
+sw_error_t
+qca808x_phy_ptp_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t mmd_num,
+		a_uint32_t reg, a_uint32_t * val)
+{
+	*val = qca808x_phy_mmd_read(dev_id, phy_id, mmd_num, (a_uint16_t)reg);
+	return SW_OK;
+}
+
+sw_error_t
+qca808x_phy_ptp_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t mmd_num,
+		a_uint32_t reg, a_uint32_t val)
+{
+	return qca808x_phy_mmd_write(dev_id, phy_id, mmd_num, (a_uint16_t)reg, (a_uint16_t)val);
+}
+
+sw_error_t
+qca808x_ptp_imr_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, union ptp_imr_reg_u *value)
+{
+	return qca808x_phy_ptp_reg_read(
+			dev_id,
+			phy_id, PTP_IMR_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_imr_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, union ptp_imr_reg_u *value)
+{
+	return qca808x_phy_ptp_reg_write(
+			dev_id,
+			phy_id, PTP_IMR_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_isr_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, union ptp_isr_reg_u *value)
+{
+	return qca808x_phy_ptp_reg_read(
+			dev_id,
+			phy_id, PTP_ISR_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_isr_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, union ptp_isr_reg_u *value)
+{
+	return qca808x_phy_ptp_reg_write(
+			dev_id,
+			phy_id, PTP_ISR_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_hw_enable_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_hw_enable_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_HW_ENABLE_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_hw_enable_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_hw_enable_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_HW_ENABLE_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_main_conf_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_MAIN_CONF_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_main_conf_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_MAIN_CONF_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid0_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid0_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_0_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_0_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_1_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_1_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_2_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_2_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_3_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_3_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_4_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_4_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid0_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_clk_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_clk_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD7_NUM, PTP_RTC_CLK_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_clk_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_clk_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD7_NUM, PTP_RTC_CLK_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_0_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_0_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_1_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_1_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_2_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_2_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_3_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_3_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_4_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_4_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_5_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_5_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_5_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_5_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_6_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_6_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_6_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts0_6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_6_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_seqid_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_seqid_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_SEQID_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_seqid_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_seqid_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_SEQID_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_portid0_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_portid0_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_portid1_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_portid1_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_portid2_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_portid2_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_portid3_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_portid3_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_portid4_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_portid4_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_portid4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_ts0_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_ts0_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_ts1_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_ts1_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_ts2_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_ts2_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_ts3_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_ts3_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_ts4_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_ts4_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_ts5_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS5_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_ts5_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS5_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_ts6_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS6_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_ts6_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_ts6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS6_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_orig_corr0_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_orig_corr0_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_orig_corr1_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_orig_corr1_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_orig_corr2_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_orig_corr2_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_orig_corr3_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_orig_corr3_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_orig_corr3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_in_trig0_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_in_trig0_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_in_trig1_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_in_trig1_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_in_trig2_reg_get(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_in_trig2_reg_set(a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_in_trig3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_in_trig3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_in_trig3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_latency_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_latency_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_LATENCY_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_latency_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_latency_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_LATENCY_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_inc0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_inc0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_INC0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_inc0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_inc0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_INC0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_inc1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_inc1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_INC1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_inc1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_inc1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_INC1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc5_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC5_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc5_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC5_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc6_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC6_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc6_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC6_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs_valid_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs_valid_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS_VALID_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs_valid_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtcoffs_valid_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS_VALID_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_misc_config_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_MISC_CONFIG_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_misc_config_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_MISC_CONFIG_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_ext_imr_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ext_imr_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EXT_IMR_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_ext_imr_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ext_imr_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EXT_IMR_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_ext_isr_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ext_isr_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EXT_ISR_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_ext_isr_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ext_isr_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EXT_ISR_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_ext_conf_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_EXT_CONF_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_ext_conf_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_EXT_CONF_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rtc_preloaded4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_gm_conf0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_GM_CONF0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_gm_conf0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_GM_CONF0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_gm_conf1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_gm_conf1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_GM_CONF1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_gm_conf1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_gm_conf1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_GM_CONF1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_ts4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_hwpll_inc0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_hwpll_inc0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_HWPLL_INC0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_hwpll_inc0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_hwpll_inc0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_HWPLL_INC0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_hwpll_inc1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_hwpll_inc1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_HWPLL_INC1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_hwpll_inc1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_hwpll_inc1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_HWPLL_INC1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_ppsin_latency_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_latency_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_LATENCY_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_ppsin_latency_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ppsin_latency_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_LATENCY_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_config_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_CONFIG_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_config_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_CONFIG_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_status_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_STATUS_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_status_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_STATUS_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_config_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_CONFIG_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_config_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_CONFIG_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_status_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_STATUS_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_status_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_STATUS_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger0_timestamp4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_trigger1_timestamp4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_event0_config_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_config_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_CONFIG_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_event0_config_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_config_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_CONFIG_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_event0_status_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_status_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_STATUS_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_event0_status_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_status_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_STATUS_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_event1_config_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_config_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_CONFIG_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_event1_config_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_config_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_CONFIG_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_event1_status_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_status_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_STATUS_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_event1_status_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_status_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_STATUS_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event0_timestamp4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_event1_timestamp4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid1_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_5_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_5_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_5_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_5_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_6_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_6_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_6_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts1_6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_6_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid2_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_5_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_5_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_5_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_5_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_6_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_6_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_6_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts2_6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_6_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_seqid3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_portid3_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_5_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_5_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_5_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_5_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_6_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_6_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_6_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_ts3_6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_6_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_imr_reg_mask_bmp_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_imr_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_imr_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mask_bmp;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_imr_reg_mask_bmp_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_imr_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_imr_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mask_bmp = value;
+	ret = qca808x_ptp_imr_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_isr_reg_status_bmp_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_isr_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_isr_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.status_bmp;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_isr_reg_status_bmp_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_isr_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_isr_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.status_bmp = value;
+	ret = qca808x_ptp_isr_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_hw_enable_reg_ptp_hw_enable_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_hw_enable_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_hw_enable_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_hw_enable;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_hw_enable_reg_ptp_hw_enable_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_hw_enable_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_hw_enable_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_hw_enable = value;
+	ret = qca808x_ptp_hw_enable_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ts_attach_mode_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_attach_mode;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ts_attach_mode_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_attach_mode = value;
+	ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ptp_clk_sel_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_clk_sel;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ptp_clk_sel_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_clk_sel = value;
+	ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_disable_1588_phy_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.disable_1588_phy;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_disable_1588_phy_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.disable_1588_phy = value;
+	ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_attach_crc_recal_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.attach_crc_recal;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_attach_crc_recal_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.attach_crc_recal = value;
+	ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ipv4_force_checksum_zero_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv4_force_checksum_zero;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ipv4_force_checksum_zero_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_force_checksum_zero = value;
+	ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ipv6_embed_force_checksum_zero_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_embed_force_checksum_zero;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ipv6_embed_force_checksum_zero_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_embed_force_checksum_zero = value;
+	ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ptp_bypass_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_bypass;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ptp_bypass_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_bypass = value;
+	ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_wol_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.wol_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_wol_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.wol_en = value;
+	ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ptp_clock_mode_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_clock_mode;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_main_conf_reg_ptp_clock_mode_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_main_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_clock_mode = value;
+	ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid0_reg_rx_seqid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_seqid0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_seqid0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_seqid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid0_reg_rx_seqid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_seqid0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_seqid0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_seqid = value;
+	ret = qca808x_ptp_rx_seqid0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_0_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid0_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid0_0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_0_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid0_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid0_0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid0_0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_1_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid0_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid0_1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_1_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid0_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid0_1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid0_1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_2_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid0_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid0_2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_2_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid0_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid0_2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid0_2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_3_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid0_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid0_3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_3_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid0_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid0_3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid0_3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_4_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid0_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid0_4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid0_4_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid0_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid0_4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid0_4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_clk_reg_rtc_clk_selection_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_clk_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_clk_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rtc_clk_selection;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_clk_reg_rtc_clk_selection_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_clk_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_clk_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rtc_clk_selection = value;
+	ret = qca808x_ptp_rtc_clk_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_0_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts0_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_0_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts0_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_sec = value;
+	ret = qca808x_ptp_rx_ts0_0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_1_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts0_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_1_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts0_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_sec = value;
+	ret = qca808x_ptp_rx_ts0_1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_2_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts0_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_2_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts0_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_sec = value;
+	ret = qca808x_ptp_rx_ts0_2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_3_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts0_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_3_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts0_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nsec = value;
+	ret = qca808x_ptp_rx_ts0_3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_4_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts0_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_4_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts0_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nsec = value;
+	ret = qca808x_ptp_rx_ts0_4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_5_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts0_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_5_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nfsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_5_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts0_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_5_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nfsec = value;
+	ret = qca808x_ptp_rx_ts0_5_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_5_reg_rx_msg_type_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts0_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_5_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_msg_type;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_5_reg_rx_msg_type_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts0_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_5_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_msg_type = value;
+	ret = qca808x_ptp_rx_ts0_5_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_6_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts0_6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_6_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nfsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts0_6_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts0_6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts0_6_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nfsec = value;
+	ret = qca808x_ptp_rx_ts0_6_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_seqid_reg_tx_seqid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_seqid_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_seqid_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_seqid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_seqid_reg_tx_seqid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_seqid_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_seqid_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_seqid = value;
+	ret = qca808x_ptp_tx_seqid_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_portid0_reg_tx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_portid0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_portid0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_portid0_reg_tx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_portid0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_portid0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_portid = value;
+	ret = qca808x_ptp_tx_portid0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_portid1_reg_tx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_portid1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_portid1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_portid1_reg_tx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_portid1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_portid1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_portid = value;
+	ret = qca808x_ptp_tx_portid1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_portid2_reg_tx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_portid2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_portid2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_portid2_reg_tx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_portid2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_portid2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_portid = value;
+	ret = qca808x_ptp_tx_portid2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_portid3_reg_tx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_portid3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_portid3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_portid3_reg_tx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_portid3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_portid3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_portid = value;
+	ret = qca808x_ptp_tx_portid3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_portid4_reg_tx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_portid4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_portid4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_portid4_reg_tx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_portid4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_portid4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_portid = value;
+	ret = qca808x_ptp_tx_portid4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts0_reg_tx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_ts0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts0_reg_tx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_ts0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_ts_sec = value;
+	ret = qca808x_ptp_tx_ts0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts1_reg_tx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_ts1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts1_reg_tx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_ts1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_ts_sec = value;
+	ret = qca808x_ptp_tx_ts1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts2_reg_tx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_ts2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts2_reg_tx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_ts2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_ts_sec = value;
+	ret = qca808x_ptp_tx_ts2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts3_reg_tx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_ts3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts3_reg_tx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_ts3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_ts_nsec = value;
+	ret = qca808x_ptp_tx_ts3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts4_reg_tx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_ts4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts4_reg_tx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_ts4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_ts_nsec = value;
+	ret = qca808x_ptp_tx_ts4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts5_reg_tx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_ts5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts5_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_ts_nfsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts5_reg_tx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_ts5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts5_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_ts_nfsec = value;
+	ret = qca808x_ptp_tx_ts5_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts5_reg_tx_msg_type_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_ts5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts5_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_msg_type;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts5_reg_tx_msg_type_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_ts5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts5_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_msg_type = value;
+	ret = qca808x_ptp_tx_ts5_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts6_reg_tx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_ts6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts6_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_ts_nfsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_ts6_reg_tx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_ts6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_ts6_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_ts_nfsec = value;
+	ret = qca808x_ptp_tx_ts6_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_orig_corr0_reg_ptp_orig_corr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_orig_corr0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_orig_corr0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_orig_corr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_orig_corr0_reg_ptp_orig_corr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_orig_corr0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_orig_corr0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_orig_corr = value;
+	ret = qca808x_ptp_orig_corr0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_orig_corr1_reg_ptp_orig_corr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_orig_corr1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_orig_corr1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_orig_corr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_orig_corr1_reg_ptp_orig_corr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_orig_corr1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_orig_corr1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_orig_corr = value;
+	ret = qca808x_ptp_orig_corr1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_orig_corr2_reg_ptp_orig_corr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_orig_corr2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_orig_corr2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_orig_corr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_orig_corr2_reg_ptp_orig_corr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_orig_corr2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_orig_corr2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_orig_corr = value;
+	ret = qca808x_ptp_orig_corr2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_orig_corr3_reg_ptp_orig_corr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_orig_corr3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_orig_corr3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_orig_corr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_orig_corr3_reg_ptp_orig_corr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_orig_corr3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_orig_corr3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_orig_corr = value;
+	ret = qca808x_ptp_orig_corr3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_in_trig0_reg_ptp_in_trig_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_in_trig0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_in_trig0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_in_trig_nisec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_in_trig0_reg_ptp_in_trig_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_in_trig0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_in_trig0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_in_trig_nisec = value;
+	ret = qca808x_ptp_in_trig0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_in_trig1_reg_ptp_in_trig_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_in_trig1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_in_trig1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_in_trig_nisec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_in_trig1_reg_ptp_in_trig_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_in_trig1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_in_trig1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_in_trig_nisec = value;
+	ret = qca808x_ptp_in_trig1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_in_trig2_reg_ptp_in_trig_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_in_trig2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_in_trig2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_in_trig_nisec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_in_trig2_reg_ptp_in_trig_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_in_trig2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_in_trig2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_in_trig_nisec = value;
+	ret = qca808x_ptp_in_trig2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_in_trig3_reg_ptp_in_trig_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_in_trig3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_in_trig3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_in_trig_nisec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_in_trig3_reg_ptp_in_trig_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_in_trig3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_in_trig3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_in_trig_nisec = value;
+	ret = qca808x_ptp_in_trig3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_latency_reg_ptp_tx_latency_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_latency_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_latency_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_tx_latency;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_latency_reg_ptp_tx_latency_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_latency_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_latency_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_tx_latency = value;
+	ret = qca808x_ptp_tx_latency_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nis_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_inc0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_inc0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_inc_nis;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nis_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_inc0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_inc0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_inc_nis = value;
+	ret = qca808x_ptp_rtc_inc0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nfs_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_inc0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_inc0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_inc_nfs;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nfs_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_inc0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_inc0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_inc_nfs = value;
+	ret = qca808x_ptp_rtc_inc0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_inc1_reg_ptp_rtc_inc_nfs_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_inc1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_inc1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_inc_nfs;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_inc1_reg_ptp_rtc_inc_nfs_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_inc1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_inc1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_inc_nfs = value;
+	ret = qca808x_ptp_rtc_inc1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs0_reg_ptp_rtcoffs_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtcoffs0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtcoffs0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtcoffs_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs0_reg_ptp_rtcoffs_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtcoffs0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtcoffs0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtcoffs_nsec = value;
+	ret = qca808x_ptp_rtcoffs0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs1_reg_ptp_rtcoffs_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtcoffs1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtcoffs1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtcoffs_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs1_reg_ptp_rtcoffs_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtcoffs1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtcoffs1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtcoffs_nsec = value;
+	ret = qca808x_ptp_rtcoffs1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs2_reg_ptp_rtcoffs_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtcoffs2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtcoffs2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtcoffs_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs2_reg_ptp_rtcoffs_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtcoffs2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtcoffs2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtcoffs_sec = value;
+	ret = qca808x_ptp_rtcoffs2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs3_reg_ptp_rtcoffs_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtcoffs3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtcoffs3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtcoffs_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs3_reg_ptp_rtcoffs_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtcoffs3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtcoffs3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtcoffs_sec = value;
+	ret = qca808x_ptp_rtcoffs3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs4_reg_ptp_rtcoffs_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtcoffs4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtcoffs4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtcoffs_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs4_reg_ptp_rtcoffs_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtcoffs4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtcoffs4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtcoffs_sec = value;
+	ret = qca808x_ptp_rtcoffs4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc0_reg_ptp_rtc_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc0_reg_ptp_rtc_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_sec = value;
+	ret = qca808x_ptp_rtc0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc1_reg_ptp_rtc_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc1_reg_ptp_rtc_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_sec = value;
+	ret = qca808x_ptp_rtc1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc2_reg_ptp_rtc_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc2_reg_ptp_rtc_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_sec = value;
+	ret = qca808x_ptp_rtc2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc3_reg_ptp_rtc_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_nisec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc3_reg_ptp_rtc_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_nisec = value;
+	ret = qca808x_ptp_rtc3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc4_reg_ptp_rtc_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_nisec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc4_reg_ptp_rtc_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_nisec = value;
+	ret = qca808x_ptp_rtc4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc5_reg_ptp_rtc_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc5_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_nfsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc5_reg_ptp_rtc_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc5_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_nfsec = value;
+	ret = qca808x_ptp_rtc5_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc6_reg_ptp_rtc_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc6_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_nfsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc6_reg_ptp_rtc_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc6_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_nfsec = value;
+	ret = qca808x_ptp_rtc6_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs_valid_reg_ptp_rtcoffs_valid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtcoffs_valid_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtcoffs_valid_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtcoffs_valid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtcoffs_valid_reg_ptp_rtcoffs_valid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtcoffs_valid_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtcoffs_valid_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtcoffs_valid = value;
+	ret = qca808x_ptp_rtcoffs_valid_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ptp_ver_chk_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_ver_chk_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ptp_ver_chk_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_ver_chk_en = value;
+	ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ipv6_udp_chk_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_udp_chk_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ipv6_udp_chk_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_udp_chk_en = value;
+	ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_cf_from_pkt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.cf_from_pkt_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_cf_from_pkt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.cf_from_pkt_en = value;
+	ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_embed_ingress_time_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.embed_ingress_time_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_embed_ingress_time_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.embed_ingress_time_en = value;
+	ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ptp_addr_chk_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_addr_chk_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ptp_addr_chk_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_addr_chk_en = value;
+	ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_crc_validate_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.crc_validate_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_crc_validate_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.crc_validate_en = value;
+	ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_pkt_one_step_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.pkt_one_step_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_pkt_one_step_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pkt_one_step_en = value;
+	ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ptp_version_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_version;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ptp_version_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_version = value;
+	ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_appended_timestamp_size_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.appended_timestamp_size;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_appended_timestamp_size_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.appended_timestamp_size = value;
+	ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ts_rtc_select_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_rtc_select;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_config_reg_ts_rtc_select_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_misc_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_rtc_select = value;
+	ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ext_imr_reg_mask_bmp_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_ext_imr_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ext_imr_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mask_bmp;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ext_imr_reg_mask_bmp_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_ext_imr_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ext_imr_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mask_bmp = value;
+	ret = qca808x_ptp_ext_imr_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ext_isr_reg_status_bmp_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_ext_isr_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ext_isr_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.status_bmp;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ext_isr_reg_status_bmp_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_ext_isr_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ext_isr_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.status_bmp = value;
+	ret = qca808x_ptp_ext_isr_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_rtc_snapshot_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_ext_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rtc_snapshot;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_rtc_snapshot_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_ext_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rtc_snapshot = value;
+	ret = qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_set_incval_mode_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_ext_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.set_incval_mode;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_set_incval_mode_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_ext_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.set_incval_mode = value;
+	ret = qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_load_rtc_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_ext_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.load_rtc;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_load_rtc_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_ext_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.load_rtc = value;
+	ret = qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_clear_rtc_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_ext_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.clear_rtc;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_clear_rtc_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_ext_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.clear_rtc = value;
+	ret = qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_rtc_read_mode_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_ext_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rtc_read_mode;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_rtc_read_mode_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_ext_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rtc_read_mode = value;
+	ret = qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_select_output_waveform_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_ext_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.select_output_waveform;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_select_output_waveform_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_ext_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.select_output_waveform = value;
+	ret = qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_set_incval_valid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_ext_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.set_incval_valid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_ext_conf_reg_set_incval_valid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_ext_conf_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.set_incval_valid = value;
+	ret = qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded0_reg_ptp_rtc_preloaded_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_preloaded0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_preloaded0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_preloaded_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded0_reg_ptp_rtc_preloaded_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_preloaded0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_preloaded0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_preloaded_sec = value;
+	ret = qca808x_ptp_rtc_preloaded0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded1_reg_ptp_rtc_preloaded_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_preloaded1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_preloaded1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_preloaded_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded1_reg_ptp_rtc_preloaded_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_preloaded1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_preloaded1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_preloaded_sec = value;
+	ret = qca808x_ptp_rtc_preloaded1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded2_reg_ptp_rtc_preloaded_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_preloaded2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_preloaded2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_preloaded_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded2_reg_ptp_rtc_preloaded_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_preloaded2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_preloaded2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_preloaded_sec = value;
+	ret = qca808x_ptp_rtc_preloaded2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded3_reg_ptp_rtc_preloaded_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_preloaded3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_preloaded3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_preloaded_nisec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded3_reg_ptp_rtc_preloaded_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_preloaded3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_preloaded3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_preloaded_nisec = value;
+	ret = qca808x_ptp_rtc_preloaded3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded4_reg_ptp_rtc_preloaded_nisec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rtc_preloaded4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_preloaded4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_preloaded_nisec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rtc_preloaded4_reg_ptp_rtc_preloaded_nisec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rtc_preloaded4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rtc_preloaded4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_preloaded_nisec = value;
+	ret = qca808x_ptp_rtc_preloaded4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_gm_pps_sync_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_gm_conf0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.gm_pps_sync;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_gm_pps_sync_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_gm_conf0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.gm_pps_sync = value;
+	ret = qca808x_ptp_gm_conf0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_gm_pll_mode_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_gm_conf0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.gm_pll_mode;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_gm_pll_mode_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_gm_conf0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.gm_pll_mode = value;
+	ret = qca808x_ptp_gm_conf0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_gm_maxfreq_offset_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_gm_conf0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.gm_maxfreq_offset;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_gm_maxfreq_offset_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_gm_conf0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.gm_maxfreq_offset = value;
+	ret = qca808x_ptp_gm_conf0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_grandmaster_mode_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_gm_conf0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.grandmaster_mode;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_gm_conf0_reg_grandmaster_mode_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_gm_conf0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.grandmaster_mode = value;
+	ret = qca808x_ptp_gm_conf0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_gm_conf1_reg_gm_kp_ldn_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_gm_conf1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_gm_conf1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.gm_kp_ldn;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_gm_conf1_reg_gm_kp_ldn_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_gm_conf1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_gm_conf1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.gm_kp_ldn = value;
+	ret = qca808x_ptp_gm_conf1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_gm_conf1_reg_gm_ki_ldn_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_gm_conf1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_gm_conf1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.gm_ki_ldn;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_gm_conf1_reg_gm_ki_ldn_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_gm_conf1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_gm_conf1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.gm_ki_ldn = value;
+	ret = qca808x_ptp_gm_conf1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts0_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_ppsin_ts0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ppsin_ts0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts0_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_ppsin_ts0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ppsin_ts0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_sec = value;
+	ret = qca808x_ptp_ppsin_ts0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts1_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_ppsin_ts1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ppsin_ts1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts1_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_ppsin_ts1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ppsin_ts1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_sec = value;
+	ret = qca808x_ptp_ppsin_ts1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts2_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_ppsin_ts2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ppsin_ts2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts2_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_ppsin_ts2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ppsin_ts2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_sec = value;
+	ret = qca808x_ptp_ppsin_ts2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts3_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_ppsin_ts3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ppsin_ts3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts3_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_ppsin_ts3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ppsin_ts3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nsec = value;
+	ret = qca808x_ptp_ppsin_ts3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts4_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_ppsin_ts4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ppsin_ts4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ppsin_ts4_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_ppsin_ts4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ppsin_ts4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nsec = value;
+	ret = qca808x_ptp_ppsin_ts4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nfs1_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_hwpll_inc0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_hwpll_inc0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_inc_nfs1;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nfs1_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_hwpll_inc0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_hwpll_inc0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_inc_nfs1 = value;
+	ret = qca808x_ptp_hwpll_inc0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nis_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_hwpll_inc0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_hwpll_inc0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_inc_nis;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nis_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_hwpll_inc0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_hwpll_inc0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_inc_nis = value;
+	ret = qca808x_ptp_hwpll_inc0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_hwpll_inc1_reg_ptp_rtc_inc_nfs0_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_hwpll_inc1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_hwpll_inc1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_rtc_inc_nfs0;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_hwpll_inc1_reg_ptp_rtc_inc_nfs0_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_hwpll_inc1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_hwpll_inc1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_rtc_inc_nfs0 = value;
+	ret = qca808x_ptp_hwpll_inc1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_sign_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_ppsin_latency_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ppsin_latency_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_ppsin_latency_sign;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_sign_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_ppsin_latency_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ppsin_latency_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_ppsin_latency_sign = value;
+	ret = qca808x_ptp_ppsin_latency_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_value_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_ppsin_latency_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ppsin_latency_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ptp_ppsin_latency_value;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_value_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_ppsin_latency_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_ppsin_latency_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ptp_ppsin_latency_value = value;
+	ret = qca808x_ptp_ppsin_latency_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_force_value_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.force_value;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_force_value_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.force_value = value;
+	ret = qca808x_ptp_trigger0_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_pattern_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.pattern;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_pattern_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pattern = value;
+	ret = qca808x_ptp_trigger0_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_status_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.status;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_status_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.status = value;
+	ret = qca808x_ptp_trigger0_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_force_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.force_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_force_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.force_en = value;
+	ret = qca808x_ptp_trigger0_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_setting_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.setting;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_setting_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.setting = value;
+	ret = qca808x_ptp_trigger0_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_notify_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.notify;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_notify_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.notify = value;
+	ret = qca808x_ptp_trigger0_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_if_late_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.if_late;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_config_reg_if_late_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.if_late = value;
+	ret = qca808x_ptp_trigger0_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_error_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger0_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.error;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_error_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger0_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.error = value;
+	ret = qca808x_ptp_trigger0_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_active_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger0_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.active;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_active_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger0_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.active = value;
+	ret = qca808x_ptp_trigger0_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_finished_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger0_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.finished;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_status_reg_finished_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger0_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.finished = value;
+	ret = qca808x_ptp_trigger0_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_force_value_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.force_value;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_force_value_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.force_value = value;
+	ret = qca808x_ptp_trigger1_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_pattern_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.pattern;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_pattern_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pattern = value;
+	ret = qca808x_ptp_trigger1_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_status_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.status;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_status_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.status = value;
+	ret = qca808x_ptp_trigger1_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_force_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.force_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_force_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.force_en = value;
+	ret = qca808x_ptp_trigger1_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_setting_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.setting;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_setting_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.setting = value;
+	ret = qca808x_ptp_trigger1_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_notify_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.notify;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_notify_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.notify = value;
+	ret = qca808x_ptp_trigger1_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_if_late_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.if_late;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_config_reg_if_late_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.if_late = value;
+	ret = qca808x_ptp_trigger1_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_error_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger1_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.error;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_error_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger1_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.error = value;
+	ret = qca808x_ptp_trigger1_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_active_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger1_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.active;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_active_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger1_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.active = value;
+	ret = qca808x_ptp_trigger1_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_finished_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger1_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.finished;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_status_reg_finished_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger1_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.finished = value;
+	ret = qca808x_ptp_trigger1_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp0_reg_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger0_timestamp0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_timestamp0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp0_reg_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger0_timestamp0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_timestamp0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_sec = value;
+	ret = qca808x_ptp_trigger0_timestamp0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp1_reg_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger0_timestamp1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_timestamp1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp1_reg_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger0_timestamp1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_timestamp1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_sec = value;
+	ret = qca808x_ptp_trigger0_timestamp1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp2_reg_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger0_timestamp2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_timestamp2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp2_reg_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger0_timestamp2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_timestamp2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_sec = value;
+	ret = qca808x_ptp_trigger0_timestamp2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp3_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger0_timestamp3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_timestamp3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp3_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger0_timestamp3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_timestamp3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_nsec = value;
+	ret = qca808x_ptp_trigger0_timestamp3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp4_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger0_timestamp4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_timestamp4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger0_timestamp4_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger0_timestamp4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger0_timestamp4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_nsec = value;
+	ret = qca808x_ptp_trigger0_timestamp4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp0_reg_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger1_timestamp0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_timestamp0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp0_reg_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger1_timestamp0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_timestamp0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_sec = value;
+	ret = qca808x_ptp_trigger1_timestamp0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp1_reg_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger1_timestamp1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_timestamp1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp1_reg_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger1_timestamp1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_timestamp1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_sec = value;
+	ret = qca808x_ptp_trigger1_timestamp1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp2_reg_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger1_timestamp2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_timestamp2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp2_reg_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger1_timestamp2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_timestamp2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_sec = value;
+	ret = qca808x_ptp_trigger1_timestamp2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp3_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger1_timestamp3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_timestamp3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp3_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger1_timestamp3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_timestamp3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_nsec = value;
+	ret = qca808x_ptp_trigger1_timestamp3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp4_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_trigger1_timestamp4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_timestamp4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_trigger1_timestamp4_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_trigger1_timestamp4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_trigger1_timestamp4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_nsec = value;
+	ret = qca808x_ptp_trigger1_timestamp4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_config_reg_rise_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rise_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_config_reg_rise_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rise_en = value;
+	ret = qca808x_ptp_event0_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_config_reg_single_cap_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.single_cap;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_config_reg_single_cap_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.single_cap = value;
+	ret = qca808x_ptp_event0_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_config_reg_fall_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.fall_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_config_reg_fall_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fall_en = value;
+	ret = qca808x_ptp_event0_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_config_reg_notify_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.notify;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_config_reg_notify_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.notify = value;
+	ret = qca808x_ptp_event0_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_config_reg_clear_stat_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.clear_stat;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_config_reg_clear_stat_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event0_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.clear_stat = value;
+	ret = qca808x_ptp_event0_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_status_reg_mul_event_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event0_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mul_event;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_status_reg_mul_event_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event0_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_event = value;
+	ret = qca808x_ptp_event0_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_status_reg_missed_count_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event0_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.missed_count;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_status_reg_missed_count_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event0_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.missed_count = value;
+	ret = qca808x_ptp_event0_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_status_reg_dir_detected_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event0_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.dir_detected;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_status_reg_dir_detected_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event0_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dir_detected = value;
+	ret = qca808x_ptp_event0_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_status_reg_detected_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event0_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.detected;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_status_reg_detected_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event0_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.detected = value;
+	ret = qca808x_ptp_event0_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_config_reg_rise_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rise_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_config_reg_rise_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rise_en = value;
+	ret = qca808x_ptp_event1_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_config_reg_single_cap_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.single_cap;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_config_reg_single_cap_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.single_cap = value;
+	ret = qca808x_ptp_event1_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_config_reg_fall_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.fall_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_config_reg_fall_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.fall_en = value;
+	ret = qca808x_ptp_event1_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_config_reg_notify_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.notify;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_config_reg_notify_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.notify = value;
+	ret = qca808x_ptp_event1_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_config_reg_clear_stat_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.clear_stat;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_config_reg_clear_stat_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event1_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.clear_stat = value;
+	ret = qca808x_ptp_event1_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_status_reg_mul_event_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event1_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mul_event;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_status_reg_mul_event_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event1_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mul_event = value;
+	ret = qca808x_ptp_event1_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_status_reg_missed_count_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event1_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.missed_count;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_status_reg_missed_count_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event1_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.missed_count = value;
+	ret = qca808x_ptp_event1_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_status_reg_dir_detected_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event1_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.dir_detected;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_status_reg_dir_detected_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event1_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.dir_detected = value;
+	ret = qca808x_ptp_event1_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_status_reg_detected_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event1_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.detected;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_status_reg_detected_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event1_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.detected = value;
+	ret = qca808x_ptp_event1_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp0_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event0_timestamp0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_timestamp0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp0_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event0_timestamp0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_timestamp0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_nsec = value;
+	ret = qca808x_ptp_event0_timestamp0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp1_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event0_timestamp1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_timestamp1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp1_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event0_timestamp1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_timestamp1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_nsec = value;
+	ret = qca808x_ptp_event0_timestamp1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp2_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event0_timestamp2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_timestamp2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp2_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event0_timestamp2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_timestamp2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_nsec = value;
+	ret = qca808x_ptp_event0_timestamp2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp3_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event0_timestamp3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_timestamp3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp3_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event0_timestamp3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_timestamp3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_nsec = value;
+	ret = qca808x_ptp_event0_timestamp3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp4_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event0_timestamp4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_timestamp4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event0_timestamp4_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event0_timestamp4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event0_timestamp4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_nsec = value;
+	ret = qca808x_ptp_event0_timestamp4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp0_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event1_timestamp0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_timestamp0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp0_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event1_timestamp0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_timestamp0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_nsec = value;
+	ret = qca808x_ptp_event1_timestamp0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp1_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event1_timestamp1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_timestamp1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp1_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event1_timestamp1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_timestamp1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_nsec = value;
+	ret = qca808x_ptp_event1_timestamp1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp2_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event1_timestamp2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_timestamp2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp2_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event1_timestamp2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_timestamp2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_nsec = value;
+	ret = qca808x_ptp_event1_timestamp2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp3_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event1_timestamp3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_timestamp3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp3_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event1_timestamp3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_timestamp3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_nsec = value;
+	ret = qca808x_ptp_event1_timestamp3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp4_reg_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_event1_timestamp4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_timestamp4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_event1_timestamp4_reg_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_event1_timestamp4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_event1_timestamp4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ts_nsec = value;
+	ret = qca808x_ptp_event1_timestamp4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid1_reg_rx_seqid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_seqid1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_seqid1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_seqid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid1_reg_rx_seqid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_seqid1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_seqid1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_seqid = value;
+	ret = qca808x_ptp_rx_seqid1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_0_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid1_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid1_0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_0_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid1_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid1_0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid1_0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_1_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid1_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid1_1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_1_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid1_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid1_1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid1_1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_2_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid1_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid1_2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_2_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid1_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid1_2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid1_2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_3_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid1_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid1_3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_3_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid1_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid1_3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid1_3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_4_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid1_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid1_4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid1_4_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid1_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid1_4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid1_4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_0_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts1_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_0_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts1_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_sec = value;
+	ret = qca808x_ptp_rx_ts1_0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_1_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts1_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_1_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts1_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_sec = value;
+	ret = qca808x_ptp_rx_ts1_1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_2_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts1_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_2_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts1_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_sec = value;
+	ret = qca808x_ptp_rx_ts1_2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_3_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts1_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_3_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts1_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nsec = value;
+	ret = qca808x_ptp_rx_ts1_3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_4_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts1_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_4_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts1_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nsec = value;
+	ret = qca808x_ptp_rx_ts1_4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_5_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts1_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_5_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nfsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_5_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts1_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_5_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nfsec = value;
+	ret = qca808x_ptp_rx_ts1_5_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_5_reg_rx_msg_type_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts1_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_5_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_msg_type;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_5_reg_rx_msg_type_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts1_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_5_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_msg_type = value;
+	ret = qca808x_ptp_rx_ts1_5_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_6_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts1_6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_6_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nfsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts1_6_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts1_6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts1_6_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nfsec = value;
+	ret = qca808x_ptp_rx_ts1_6_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid2_reg_rx_seqid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_seqid2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_seqid2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_seqid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid2_reg_rx_seqid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_seqid2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_seqid2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_seqid = value;
+	ret = qca808x_ptp_rx_seqid2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_0_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid2_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid2_0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_0_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid2_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid2_0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid2_0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_1_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid2_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid2_1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_1_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid2_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid2_1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid2_1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_2_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid2_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid2_2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_2_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid2_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid2_2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid2_2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_3_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid2_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid2_3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_3_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid2_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid2_3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid2_3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_4_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid2_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid2_4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid2_4_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid2_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid2_4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid2_4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_0_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts2_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_0_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts2_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_sec = value;
+	ret = qca808x_ptp_rx_ts2_0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_1_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts2_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_1_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts2_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_sec = value;
+	ret = qca808x_ptp_rx_ts2_1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_2_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts2_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_2_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts2_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_sec = value;
+	ret = qca808x_ptp_rx_ts2_2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_3_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts2_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_3_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts2_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nsec = value;
+	ret = qca808x_ptp_rx_ts2_3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_4_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts2_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_4_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts2_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nsec = value;
+	ret = qca808x_ptp_rx_ts2_4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_5_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts2_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_5_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nfsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_5_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts2_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_5_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nfsec = value;
+	ret = qca808x_ptp_rx_ts2_5_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_5_reg_rx_msg_type_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts2_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_5_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_msg_type;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_5_reg_rx_msg_type_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts2_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_5_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_msg_type = value;
+	ret = qca808x_ptp_rx_ts2_5_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_6_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts2_6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_6_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nfsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts2_6_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts2_6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts2_6_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nfsec = value;
+	ret = qca808x_ptp_rx_ts2_6_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid3_reg_rx_seqid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_seqid3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_seqid3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_seqid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_seqid3_reg_rx_seqid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_seqid3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_seqid3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_seqid = value;
+	ret = qca808x_ptp_rx_seqid3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_0_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid3_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid3_0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_0_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid3_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid3_0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid3_0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_1_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid3_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid3_1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_1_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid3_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid3_1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid3_1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_2_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid3_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid3_2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_2_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid3_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid3_2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid3_2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_3_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid3_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid3_3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_3_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid3_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid3_3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid3_3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_4_reg_rx_portid_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_portid3_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid3_4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_portid;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_portid3_4_reg_rx_portid_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_portid3_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_portid3_4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_portid = value;
+	ret = qca808x_ptp_rx_portid3_4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_0_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts3_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_0_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts3_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_sec = value;
+	ret = qca808x_ptp_rx_ts3_0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_1_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts3_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_1_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts3_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_sec = value;
+	ret = qca808x_ptp_rx_ts3_1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_2_reg_rx_ts_sec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts3_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_sec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_2_reg_rx_ts_sec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts3_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_sec = value;
+	ret = qca808x_ptp_rx_ts3_2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_3_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts3_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_3_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts3_3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nsec = value;
+	ret = qca808x_ptp_rx_ts3_3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_4_reg_rx_ts_nsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts3_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_4_reg_rx_ts_nsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts3_4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nsec = value;
+	ret = qca808x_ptp_rx_ts3_4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_5_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts3_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_5_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nfsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_5_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts3_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_5_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nfsec = value;
+	ret = qca808x_ptp_rx_ts3_5_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_5_reg_rx_msg_type_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts3_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_5_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_msg_type;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_5_reg_rx_msg_type_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts3_5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_5_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_msg_type = value;
+	ret = qca808x_ptp_rx_ts3_5_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_6_reg_rx_ts_nfsec_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_ts3_6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_6_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_ts_nfsec;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_ts3_6_reg_rx_ts_nfsec_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_ts3_6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_ts3_6_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_ts_nfsec = value;
+	ret = qca808x_ptp_rx_ts3_6_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_phase_adjust_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_phase_adjust_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_PHASE_ADJUST_0_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+qca808x_ptp_phase_adjust_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_phase_adjust_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_PHASE_ADJUST_0_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+qca808x_ptp_phase_adjust_0_reg_phase_value_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_phase_adjust_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_phase_adjust_0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.phase_value;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_phase_adjust_0_reg_phase_value_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_phase_adjust_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_phase_adjust_0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.phase_value = value;
+	ret = qca808x_ptp_phase_adjust_0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_phase_adjust_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_phase_adjust_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_PHASE_ADJUST_1_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+qca808x_ptp_phase_adjust_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_phase_adjust_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_PHASE_ADJUST_1_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+qca808x_ptp_phase_adjust_1_reg_phase_value_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_phase_adjust_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_phase_adjust_1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.phase_value;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_phase_adjust_1_reg_phase_value_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_phase_adjust_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_phase_adjust_1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.phase_value = value;
+	ret = qca808x_ptp_phase_adjust_1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_pps_pul_width_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_pps_pul_width_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPS_PUL_WIDTH_0_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+qca808x_ptp_pps_pul_width_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_pps_pul_width_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPS_PUL_WIDTH_0_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+qca808x_ptp_pps_pul_width_0_reg_pul_value_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_pps_pul_width_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_pps_pul_width_0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.pul_value;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_pps_pul_width_0_reg_pul_value_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_pps_pul_width_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_pps_pul_width_0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pul_value = value;
+	ret = qca808x_ptp_pps_pul_width_0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_pps_pul_width_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_pps_pul_width_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPS_PUL_WIDTH_1_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+qca808x_ptp_pps_pul_width_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_pps_pul_width_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPS_PUL_WIDTH_1_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+qca808x_ptp_pps_pul_width_1_reg_pul_value_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_pps_pul_width_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_pps_pul_width_1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.pul_value;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_pps_pul_width_1_reg_pul_value_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_pps_pul_width_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_pps_pul_width_1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pul_value = value;
+	ret = qca808x_ptp_pps_pul_width_1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_freq_waveform_period_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_FREQ_WAVEFORM_PERIOD_0_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_freq_waveform_period_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_FREQ_WAVEFORM_PERIOD_0_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_0_reg_wave_period_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_freq_waveform_period_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_freq_waveform_period_0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.wave_period;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_0_reg_wave_period_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_freq_waveform_period_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_freq_waveform_period_0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.wave_period = value;
+	ret = qca808x_ptp_freq_waveform_period_0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_0_reg_phase_ali_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_freq_waveform_period_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_freq_waveform_period_0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.phase_ali;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_0_reg_phase_ali_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_freq_waveform_period_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_freq_waveform_period_0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.phase_ali = value;
+	ret = qca808x_ptp_freq_waveform_period_0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_freq_waveform_period_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_FREQ_WAVEFORM_PERIOD_1_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_freq_waveform_period_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_FREQ_WAVEFORM_PERIOD_1_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_1_reg_wave_period_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_freq_waveform_period_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_freq_waveform_period_1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.wave_period;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_1_reg_wave_period_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_freq_waveform_period_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_freq_waveform_period_1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.wave_period = value;
+	ret = qca808x_ptp_freq_waveform_period_1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_freq_waveform_period_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_FREQ_WAVEFORM_PERIOD_2_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_freq_waveform_period_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_FREQ_WAVEFORM_PERIOD_2_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_2_reg_wave_period_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_freq_waveform_period_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_freq_waveform_period_2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.wave_period;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_freq_waveform_period_2_reg_wave_period_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_freq_waveform_period_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_freq_waveform_period_2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.wave_period = value;
+	ret = qca808x_ptp_freq_waveform_period_2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_ts_ctrl_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TS_CTRL_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_ts_ctrl_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TS_CTRL_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_da0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_DA0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_da0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_DA0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_da1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_DA1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_da1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_DA1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_da2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_DA2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_da2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_DA2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv4_da0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV4_DA0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv4_da0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV4_DA0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv4_da1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV4_DA1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv4_da1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV4_DA1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da5_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA5_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da5_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA5_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da6_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA6_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da6_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA6_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da7_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da7_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA7_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da7_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_ipv6_da7_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA7_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_lengthtype_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_lengthtype_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_LENGTHTYPE_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_lengthtype_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_mac_lengthtype_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_LENGTHTYPE_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_layer4_protocol_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_layer4_protocol_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_LAYER4_PROTOCOL_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_layer4_protocol_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_layer4_protocol_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_LAYER4_PROTOCOL_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_udp_port_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_udp_port_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_UDP_PORT_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_udp_port_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_filt_udp_port_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_UDP_PORT_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_ts_status_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TS_STATUS_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_ts_status_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TS_STATUS_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_frac_nano_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_FRAC_NANO_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_frac_nano_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_FRAC_NANO_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_timestamp_pre4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_pre_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_frac_nano_pre_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_FRAC_NANO_PRE_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_pre_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_frac_nano_pre_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_FRAC_NANO_PRE_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_y1731_identify_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_Y1731_IDENTIFY_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_y1731_identify_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_Y1731_IDENTIFY_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_pre_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_y1731_identify_pre_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_Y1731_IDENTIFY_PRE_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_pre_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_y1731_identify_pre_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_Y1731_IDENTIFY_PRE_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_ts_ctrl_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TS_CTRL_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_ts_ctrl_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TS_CTRL_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_da0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_DA0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_da0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_DA0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_da1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_DA1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_da1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_DA1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_da2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_DA2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_da2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_DA2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv4_da0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV4_DA0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv4_da0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV4_DA0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv4_da1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV4_DA1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv4_da1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV4_DA1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da5_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA5_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da5_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da5_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA5_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da6_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA6_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da6_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da6_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA6_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da7_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da7_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA7_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da7_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_ipv6_da7_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA7_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_lengthtype_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_lengthtype_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_LENGTHTYPE_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_lengthtype_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_mac_lengthtype_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_LENGTHTYPE_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_layer4_protocol_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_layer4_protocol_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_LAYER4_PROTOCOL_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_layer4_protocol_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_layer4_protocol_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_LAYER4_PROTOCOL_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_udp_port_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_udp_port_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_UDP_PORT_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_udp_port_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_filt_udp_port_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_UDP_PORT_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_ts_status_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TS_STATUS_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_ts_status_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TS_STATUS_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP2_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP2_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp3_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP3_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp3_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp3_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP3_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp4_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP4_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp4_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_timestamp4_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP4_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_frac_nano_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_frac_nano_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_FRAC_NANO_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_com_frac_nano_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_com_frac_nano_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_FRAC_NANO_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_y1731_identify_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_y1731_identify_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_Y1731_IDENTIFY_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_y1731_identify_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_y1731_identify_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_Y1731_IDENTIFY_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_y1731_dm_control_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_y1731_dm_control_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_Y1731_DM_CONTROL_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_y1731_dm_control_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_y1731_dm_control_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_Y1731_DM_CONTROL_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_pre_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_ts_status_pre_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TS_STATUS_PRE_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_pre_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_com_ts_status_pre_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TS_STATUS_PRE_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_baud_config_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_baud_config_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_BAUD_CONFIG_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_baud_config_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_baud_config_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_BAUD_CONFIG_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_uart_configuration_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_UART_CONFIGURATION_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_uart_configuration_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_UART_CONFIGURATION_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_reset_buffer_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_reset_buffer_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RESET_BUFFER_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_reset_buffer_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_reset_buffer_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RESET_BUFFER_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_buffer_status_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_BUFFER_STATUS_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_buffer_status_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_BUFFER_STATUS_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_buffer_write_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_buffer_write_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_BUFFER_WRITE_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_tx_buffer_write_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_tx_buffer_write_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_BUFFER_WRITE_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_buffer_read_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_BUFFER_READ_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_rx_buffer_read_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_BUFFER_READ_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_da_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv4_da_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_da_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_da_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_mac_lengthtype_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_lengthtype_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_mac_lengthtype_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_lengthtype_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_y1731_da_chk_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.y1731_da_chk_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_y1731_da_chk_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.y1731_da_chk_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_pw_mac_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.pw_mac_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_pw_mac_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pw_mac_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_udp_ptp_event_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.udp_ptp_event_filt_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_udp_ptp_event_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udp_ptp_event_filt_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_udp_dport_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.udp_dport_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_udp_dport_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udp_dport_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_mac_ptp_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_ptp_filt_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_mac_ptp_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_ptp_filt_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_da_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_da_filt_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_da_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_da_filt_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_next_header_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_next_header_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_next_header_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_next_header_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv4_layer4_protocol_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_layer4_protocol_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_y1731_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.y1731_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_y1731_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.y1731_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.filt_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.filt_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_ptp_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_ptp_filt_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_ptp_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_ptp_filt_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_ptp_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv4_ptp_filt_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_ptp_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_ptp_filt_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_y1731_insert_ts_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.y1731_insert_ts_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_y1731_insert_ts_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.y1731_insert_ts_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_mac_da_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_da_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_ctrl_reg_mac_da_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_da_en = value;
+	ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da0_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_mac_da0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_mac_da0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da0_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_mac_da0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_mac_da0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr = value;
+	ret = qca808x_ptp_rx_filt_mac_da0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da1_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_mac_da1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_mac_da1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da1_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_mac_da1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_mac_da1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr = value;
+	ret = qca808x_ptp_rx_filt_mac_da1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da2_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_mac_da2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_mac_da2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_da2_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_mac_da2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_mac_da2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr = value;
+	ret = qca808x_ptp_rx_filt_mac_da2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da0_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_ipv4_da0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv4_da0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da0_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_ipv4_da0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv4_da0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_rx_filt_ipv4_da0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da1_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_ipv4_da1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv4_da1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv4_da1_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_ipv4_da1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv4_da1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_rx_filt_ipv4_da1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da0_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_ipv6_da0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da0_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_ipv6_da0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_rx_filt_ipv6_da0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da1_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_ipv6_da1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da1_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_ipv6_da1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_rx_filt_ipv6_da1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da2_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_ipv6_da2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da2_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_ipv6_da2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_rx_filt_ipv6_da2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da3_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_ipv6_da3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da3_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_ipv6_da3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_rx_filt_ipv6_da3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da4_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_ipv6_da4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da4_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_ipv6_da4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_rx_filt_ipv6_da4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da5_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_ipv6_da5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da5_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da5_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_ipv6_da5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da5_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_rx_filt_ipv6_da5_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da6_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_ipv6_da6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da6_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da6_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_ipv6_da6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da6_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_rx_filt_ipv6_da6_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da7_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_ipv6_da7_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da7_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_ipv6_da7_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_ipv6_da7_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_ipv6_da7_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_rx_filt_ipv6_da7_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_lengthtype_reg_length_type_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_mac_lengthtype_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_mac_lengthtype_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.length_type;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_mac_lengthtype_reg_length_type_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_mac_lengthtype_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_mac_lengthtype_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.length_type = value;
+	ret = qca808x_ptp_rx_filt_mac_lengthtype_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_layer4_protocol_reg_l4_protocol_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_layer4_protocol_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_layer4_protocol_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.l4_protocol;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_layer4_protocol_reg_l4_protocol_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_layer4_protocol_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_layer4_protocol_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l4_protocol = value;
+	ret = qca808x_ptp_rx_filt_layer4_protocol_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_udp_port_reg_udp_port_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_filt_udp_port_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_udp_port_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.udp_port;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_filt_udp_port_reg_udp_port_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_filt_udp_port_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_filt_udp_port_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udp_port = value;
+	ret = qca808x_ptp_rx_filt_udp_port_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_ptp_pdelay_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_ptp_pdelay_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_ptp_pdelay_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_ptp_pdelay_addr = value;
+	ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_da_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_da;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_da_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_da = value;
+	ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_pdelay_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv4_ptp_pdelay_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_pdelay_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_ptp_pdelay_addr = value;
+	ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_lengthtype_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_lengthtype;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_lengthtype_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_lengthtype = value;
+	ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_udp_dport_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.udp_dport;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_udp_dport_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udp_dport = value;
+	ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_layer4_protocol_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv4_layer4_protocol;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_layer4_protocol_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_layer4_protocol = value;
+	ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_udp_ptp_event_dport_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.udp_ptp_event_dport;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_udp_ptp_event_dport_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udp_ptp_event_dport = value;
+	ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_da_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_da;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_da_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_da = value;
+	ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_prim_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv4_ptp_prim_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_prim_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_ptp_prim_addr = value;
+	ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_da_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv4_da;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv4_da_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_da = value;
+	ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_pdelay_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_ptp_pdelay_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_pdelay_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_ptp_pdelay_addr = value;
+	ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_prim_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_ptp_prim_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_prim_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_ptp_prim_addr = value;
+	ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_next_header_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_next_header;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_ipv6_next_header_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_next_header = value;
+	ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_y1731_mach_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.y1731_mach;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_y1731_mach_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.y1731_mach = value;
+	ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_ptp_prim_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_ptp_prim_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_ts_status_reg_mac_ptp_prim_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_ptp_prim_addr = value;
+	ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp0_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_timestamp0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.com_ts;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp0_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_timestamp0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.com_ts = value;
+	ret = qca808x_ptp_rx_com_timestamp0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp1_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_timestamp1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.com_ts;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp1_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_timestamp1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.com_ts = value;
+	ret = qca808x_ptp_rx_com_timestamp1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp2_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_timestamp2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.com_ts;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp2_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_timestamp2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.com_ts = value;
+	ret = qca808x_ptp_rx_com_timestamp2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp3_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_timestamp3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.com_ts;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp3_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_timestamp3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.com_ts = value;
+	ret = qca808x_ptp_rx_com_timestamp3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp4_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_timestamp4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.com_ts;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp4_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_timestamp4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.com_ts = value;
+	ret = qca808x_ptp_rx_com_timestamp4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_reg_frac_nano_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_frac_nano_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_frac_nano_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.frac_nano;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_reg_frac_nano_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_frac_nano_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_frac_nano_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.frac_nano = value;
+	ret = qca808x_ptp_rx_com_frac_nano_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre0_reg_com_ts_pre_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_timestamp_pre0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp_pre0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.com_ts_pre;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre0_reg_com_ts_pre_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_timestamp_pre0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp_pre0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.com_ts_pre = value;
+	ret = qca808x_ptp_rx_com_timestamp_pre0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre1_reg_com_ts_pre_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_timestamp_pre1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp_pre1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.com_ts_pre;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre1_reg_com_ts_pre_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_timestamp_pre1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp_pre1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.com_ts_pre = value;
+	ret = qca808x_ptp_rx_com_timestamp_pre1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre2_reg_com_ts_pre_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_timestamp_pre2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp_pre2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.com_ts_pre;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre2_reg_com_ts_pre_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_timestamp_pre2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp_pre2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.com_ts_pre = value;
+	ret = qca808x_ptp_rx_com_timestamp_pre2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre3_reg_com_ts_pre_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_timestamp_pre3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp_pre3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.com_ts_pre;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre3_reg_com_ts_pre_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_timestamp_pre3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp_pre3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.com_ts_pre = value;
+	ret = qca808x_ptp_rx_com_timestamp_pre3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre4_reg_com_ts_pre_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_timestamp_pre4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp_pre4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.com_ts_pre;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_timestamp_pre4_reg_com_ts_pre_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_timestamp_pre4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_timestamp_pre4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.com_ts_pre = value;
+	ret = qca808x_ptp_rx_com_timestamp_pre4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_pre_reg_frac_nano_pre_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_com_frac_nano_pre_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_frac_nano_pre_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.frac_nano_pre;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_com_frac_nano_pre_reg_frac_nano_pre_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_com_frac_nano_pre_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_com_frac_nano_pre_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.frac_nano_pre = value;
+	ret = qca808x_ptp_rx_com_frac_nano_pre_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_reg_identify_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_y1731_identify_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_y1731_identify_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.identify;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_reg_identify_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_y1731_identify_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_y1731_identify_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.identify = value;
+	ret = qca808x_ptp_rx_y1731_identify_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_pre_reg_identify_pre_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_y1731_identify_pre_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_y1731_identify_pre_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.identify_pre;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_y1731_identify_pre_reg_identify_pre_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_y1731_identify_pre_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_y1731_identify_pre_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.identify_pre = value;
+	ret = qca808x_ptp_rx_y1731_identify_pre_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_da_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv4_da_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_da_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_da_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_mac_lengthtype_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_lengthtype_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_mac_lengthtype_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_lengthtype_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_da_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_da_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_da_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_da_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_pw_mac_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.pw_mac_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_pw_mac_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.pw_mac_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_udp_ptp_event_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.udp_ptp_event_filt_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_udp_ptp_event_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udp_ptp_event_filt_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_udp_dport_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.udp_dport_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_udp_dport_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udp_dport_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_mac_ptp_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_ptp_filt_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_mac_ptp_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_ptp_filt_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_next_header_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_next_header_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_next_header_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_next_header_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv4_layer4_protocol_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_layer4_protocol_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_y1731_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.y1731_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_y1731_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.y1731_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.filt_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.filt_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_ptp_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_ptp_filt_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_ptp_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_ptp_filt_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_ptp_filt_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv4_ptp_filt_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_ptp_filt_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_ptp_filt_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_y1731_insert_ts_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.y1731_insert_ts_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_y1731_insert_ts_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.y1731_insert_ts_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_mac_da_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_da_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_mac_da_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_da_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_y1731_sa_chk_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.y1731_sa_chk_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_ctrl_reg_y1731_sa_chk_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_ctrl_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.y1731_sa_chk_en = value;
+	ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da0_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_mac_da0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_mac_da0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da0_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_mac_da0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_mac_da0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr = value;
+	ret = qca808x_ptp_tx_filt_mac_da0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da1_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_mac_da1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_mac_da1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da1_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_mac_da1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_mac_da1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr = value;
+	ret = qca808x_ptp_tx_filt_mac_da1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da2_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_mac_da2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_mac_da2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_da2_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_mac_da2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_mac_da2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr = value;
+	ret = qca808x_ptp_tx_filt_mac_da2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da0_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_ipv4_da0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv4_da0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da0_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_ipv4_da0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv4_da0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_tx_filt_ipv4_da0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da1_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_ipv4_da1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv4_da1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv4_da1_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_ipv4_da1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv4_da1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_tx_filt_ipv4_da1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da0_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_ipv6_da0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da0_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_ipv6_da0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_tx_filt_ipv6_da0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da1_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_ipv6_da1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da1_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_ipv6_da1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_tx_filt_ipv6_da1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da2_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_ipv6_da2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da2_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_ipv6_da2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_tx_filt_ipv6_da2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da3_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_ipv6_da3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da3_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_ipv6_da3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_tx_filt_ipv6_da3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da4_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_ipv6_da4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da4_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_ipv6_da4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_tx_filt_ipv6_da4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da5_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_ipv6_da5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da5_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da5_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_ipv6_da5_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da5_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_tx_filt_ipv6_da5_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da6_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_ipv6_da6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da6_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da6_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_ipv6_da6_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da6_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_tx_filt_ipv6_da6_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da7_reg_ip_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_ipv6_da7_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da7_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ip_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_ipv6_da7_reg_ip_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_ipv6_da7_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_ipv6_da7_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ip_addr = value;
+	ret = qca808x_ptp_tx_filt_ipv6_da7_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_lengthtype_reg_length_type_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_mac_lengthtype_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_mac_lengthtype_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.length_type;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_mac_lengthtype_reg_length_type_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_mac_lengthtype_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_mac_lengthtype_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.length_type = value;
+	ret = qca808x_ptp_tx_filt_mac_lengthtype_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_layer4_protocol_reg_l4_protocol_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_layer4_protocol_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_layer4_protocol_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.l4_protocol;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_layer4_protocol_reg_l4_protocol_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_layer4_protocol_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_layer4_protocol_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.l4_protocol = value;
+	ret = qca808x_ptp_tx_filt_layer4_protocol_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_udp_port_reg_udp_port_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_filt_udp_port_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_udp_port_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.udp_port;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_filt_udp_port_reg_udp_port_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_filt_udp_port_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_filt_udp_port_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udp_port = value;
+	ret = qca808x_ptp_tx_filt_udp_port_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_ptp_pdelay_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_ptp_pdelay_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_ptp_pdelay_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_ptp_pdelay_addr = value;
+	ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_da_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_da;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_da_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_da = value;
+	ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_pdelay_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv4_ptp_pdelay_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_pdelay_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_ptp_pdelay_addr = value;
+	ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_lengthtype_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_lengthtype;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_lengthtype_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_lengthtype = value;
+	ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_udp_dport_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.udp_dport;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_udp_dport_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udp_dport = value;
+	ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_layer4_protocol_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv4_layer4_protocol;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_layer4_protocol_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_layer4_protocol = value;
+	ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_udp_ptp_event_dport_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.udp_ptp_event_dport;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_udp_ptp_event_dport_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.udp_ptp_event_dport = value;
+	ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_da_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_da;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_da_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_da = value;
+	ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_prim_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv4_ptp_prim_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_prim_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_ptp_prim_addr = value;
+	ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_da_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv4_da;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv4_da_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv4_da = value;
+	ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_pdelay_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_ptp_pdelay_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_pdelay_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_ptp_pdelay_addr = value;
+	ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_prim_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_ptp_prim_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_prim_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_ptp_prim_addr = value;
+	ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_next_header_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.ipv6_next_header;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_ipv6_next_header_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.ipv6_next_header = value;
+	ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_y1731_mach_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.y1731_mach;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_y1731_mach_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.y1731_mach = value;
+	ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_ptp_prim_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_ptp_prim_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_ts_status_reg_mac_ptp_prim_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_ts_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_ptp_prim_addr = value;
+	ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp0_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_timestamp0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_timestamp0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.com_ts;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp0_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_timestamp0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_timestamp0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.com_ts = value;
+	ret = qca808x_ptp_tx_com_timestamp0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp1_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_timestamp1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_timestamp1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.com_ts;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp1_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_timestamp1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_timestamp1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.com_ts = value;
+	ret = qca808x_ptp_tx_com_timestamp1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp2_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_timestamp2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_timestamp2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.com_ts;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp2_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_timestamp2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_timestamp2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.com_ts = value;
+	ret = qca808x_ptp_tx_com_timestamp2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp3_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_timestamp3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_timestamp3_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.com_ts;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp3_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_timestamp3_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_timestamp3_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.com_ts = value;
+	ret = qca808x_ptp_tx_com_timestamp3_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp4_reg_com_ts_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_timestamp4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_timestamp4_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.com_ts;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_timestamp4_reg_com_ts_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_timestamp4_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_timestamp4_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.com_ts = value;
+	ret = qca808x_ptp_tx_com_timestamp4_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_frac_nano_reg_frac_nano_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_com_frac_nano_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_frac_nano_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.frac_nano;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_com_frac_nano_reg_frac_nano_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_com_frac_nano_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_com_frac_nano_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.frac_nano = value;
+	ret = qca808x_ptp_tx_com_frac_nano_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_y1731_identify_reg_identify_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_y1731_identify_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_y1731_identify_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.identify;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_y1731_identify_reg_identify_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_y1731_identify_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_y1731_identify_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.identify = value;
+	ret = qca808x_ptp_tx_y1731_identify_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_y1731_dm_control_reg_y1731_dmm_lpbk_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_y1731_dm_control_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_y1731_dm_control_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.y1731_dmm_lpbk_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_y1731_dm_control_reg_y1731_dmm_lpbk_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_y1731_dm_control_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_y1731_dm_control_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.y1731_dmm_lpbk_en = value;
+	ret = qca808x_ptp_y1731_dm_control_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_y1731_dm_control_reg_valid_msg_lev_bmp_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_y1731_dm_control_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_y1731_dm_control_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.valid_msg_lev_bmp;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_y1731_dm_control_reg_valid_msg_lev_bmp_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_y1731_dm_control_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_y1731_dm_control_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.valid_msg_lev_bmp = value;
+	ret = qca808x_ptp_y1731_dm_control_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_baud_config_reg_baud_rate_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_baud_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_baud_config_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.baud_rate;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_baud_config_reg_baud_rate_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_baud_config_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_baud_config_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.baud_rate = value;
+	ret = qca808x_ptp_baud_config_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_start_polarity_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value)
+{
+	union ptp_uart_configuration_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.start_polarity;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_start_polarity_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_uart_configuration_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.start_polarity = value;
+	ret = qca808x_ptp_uart_configuration_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_msb_first_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value)
+{
+	union ptp_uart_configuration_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.msb_first;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_msb_first_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_uart_configuration_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.msb_first = value;
+	ret = qca808x_ptp_uart_configuration_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_parity_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value)
+{
+	union ptp_uart_configuration_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.parity_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_parity_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_uart_configuration_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.parity_en = value;
+	ret = qca808x_ptp_uart_configuration_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_auto_tod_out_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value)
+{
+	union ptp_uart_configuration_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.auto_tod_out_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_auto_tod_out_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_uart_configuration_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.auto_tod_out_en = value;
+	ret = qca808x_ptp_uart_configuration_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_auto_tod_in_en_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		unsigned int *value)
+{
+	union ptp_uart_configuration_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.auto_tod_in_en;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_uart_configuration_reg_auto_tod_in_en_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_uart_configuration_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.auto_tod_in_en = value;
+	ret = qca808x_ptp_uart_configuration_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_reset_buffer_reg_reset_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_reset_buffer_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_reset_buffer_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.reset;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_reset_buffer_reg_reset_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_reset_buffer_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_reset_buffer_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.reset = value;
+	ret = qca808x_ptp_reset_buffer_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_almost_empty_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_buffer_almost_empty;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_almost_empty_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_buffer_almost_empty = value;
+	ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_almost_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_buffer_almost_full;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_almost_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_buffer_almost_full = value;
+	ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_half_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_buffer_half_full;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_half_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_buffer_half_full = value;
+	ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_buffer_full;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_tx_buffer_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_buffer_full = value;
+	ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_almost_empty_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_buffer_almost_empty;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_almost_empty_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_buffer_almost_empty = value;
+	ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_almost_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_buffer_almost_full;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_almost_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_buffer_almost_full = value;
+	ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_half_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_buffer_half_full;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_half_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_buffer_half_full = value;
+	ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_buffer_full;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_buffer_full = value;
+	ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_data_present_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_buffer_data_present;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_buffer_status_reg_rx_buffer_data_present_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_buffer_status_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_buffer_data_present = value;
+	ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_buffer_write_reg_tx_buffer_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_tx_buffer_write_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_buffer_write_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.tx_buffer;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_tx_buffer_write_reg_tx_buffer_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_tx_buffer_write_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_tx_buffer_write_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.tx_buffer = value;
+	ret = qca808x_ptp_tx_buffer_write_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_data_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_buffer_read_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_data;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_data_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_buffer_read_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_data = value;
+	ret = qca808x_ptp_rx_buffer_read_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_empty_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_buffer_read_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_buffer_almost_empty;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_empty_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_buffer_read_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_buffer_almost_empty = value;
+	ret = qca808x_ptp_rx_buffer_read_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_buffer_read_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_buffer_almost_full;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_buffer_read_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_buffer_almost_full = value;
+	ret = qca808x_ptp_rx_buffer_read_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_half_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_buffer_read_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_buffer_half_full;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_half_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_buffer_read_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_buffer_half_full = value;
+	ret = qca808x_ptp_rx_buffer_read_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_full_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_buffer_read_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_buffer_full;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_full_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_buffer_read_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_buffer_full = value;
+	ret = qca808x_ptp_rx_buffer_read_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_data_present_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_rx_buffer_read_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.rx_buffer_data_present;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_rx_buffer_read_reg_rx_buffer_data_present_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_rx_buffer_read_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.rx_buffer_data_present = value;
+	ret = qca808x_ptp_rx_buffer_read_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+//
+sw_error_t
+qca808x_ptp_loc_mac_addr_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_loc_mac_addr_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_LOC_MAC_ADDR_0_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_loc_mac_addr_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_LOC_MAC_ADDR_0_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_loc_mac_addr_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_LOC_MAC_ADDR_1_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_loc_mac_addr_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_LOC_MAC_ADDR_1_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_2_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_loc_mac_addr_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_LOC_MAC_ADDR_2_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_2_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_loc_mac_addr_2_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_LOC_MAC_ADDR_2_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_0_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_loc_mac_addr_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_loc_mac_addr_0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_0_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_loc_mac_addr_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_loc_mac_addr_0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr = value;
+	ret = qca808x_ptp_loc_mac_addr_0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_1_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_loc_mac_addr_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_loc_mac_addr_1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_1_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_loc_mac_addr_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_loc_mac_addr_1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr = value;
+	ret = qca808x_ptp_loc_mac_addr_1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_2_reg_mac_addr_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_loc_mac_addr_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_loc_mac_addr_2_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.mac_addr;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_loc_mac_addr_2_reg_mac_addr_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_loc_mac_addr_2_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_loc_mac_addr_2_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.mac_addr = value;
+	ret = qca808x_ptp_loc_mac_addr_2_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_link_delay_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_link_delay_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_LINK_DELAY_0_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+qca808x_ptp_link_delay_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_link_delay_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_LINK_DELAY_0_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+qca808x_ptp_link_delay_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_link_delay_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_LINK_DELAY_1_REG_ADDRESS,
+				&value->val);
+}
+
+sw_error_t
+qca808x_ptp_link_delay_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_link_delay_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+				dev_id,
+				phy_id, QCA808X_PHY_MMD3_NUM, PTP_LINK_DELAY_1_REG_ADDRESS,
+				value->val);
+}
+
+sw_error_t
+qca808x_ptp_link_delay_0_reg_link_delay_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_link_delay_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_link_delay_0_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.link_delay;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_link_delay_0_reg_link_delay_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_link_delay_0_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_link_delay_0_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.link_delay = value;
+	ret = qca808x_ptp_link_delay_0_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_link_delay_1_reg_link_delay_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t *value)
+{
+	union ptp_link_delay_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_link_delay_1_reg_get(dev_id, phy_id, &reg_val);
+	*value = reg_val.bf.link_delay;
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_link_delay_1_reg_link_delay_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		a_uint32_t value)
+{
+	union ptp_link_delay_1_reg_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = qca808x_ptp_link_delay_1_reg_get(dev_id, phy_id, &reg_val);
+	if (SW_OK != ret)
+		return ret;
+	reg_val.bf.link_delay = value;
+	ret = qca808x_ptp_link_delay_1_reg_set(dev_id, phy_id, &reg_val);
+	return ret;
+}
+
+sw_error_t
+qca808x_ptp_misc_control_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_misc_control_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_MISC_CONTROL_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_misc_control_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_misc_control_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_MISC_CONTROL_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_ingress_asymmetry_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ingress_asymmetry_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_INGRESS_ASYMMETRY_0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_ingress_asymmetry_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ingress_asymmetry_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_INGRESS_ASYMMETRY_0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_ingress_asymmetry_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ingress_asymmetry_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_INGRESS_ASYMMETRY_1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_ingress_asymmetry_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_ingress_asymmetry_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_INGRESS_ASYMMETRY_1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_egress_asymmetry_0_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_egress_asymmetry_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EGRESS_ASYMMETRY_0_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_egress_asymmetry_0_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_egress_asymmetry_0_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EGRESS_ASYMMETRY_0_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_egress_asymmetry_1_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_egress_asymmetry_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EGRESS_ASYMMETRY_1_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_egress_asymmetry_1_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_egress_asymmetry_1_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_EGRESS_ASYMMETRY_1_REG_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+qca808x_ptp_backup_reg_get(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_backup_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_read(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_BACKUP_REG_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+qca808x_ptp_backup_reg_set(
+		a_uint32_t dev_id, a_uint32_t phy_id,
+		union ptp_backup_reg_u *value)
+{
+	return qca808x_phy_ptp_mmd_write(
+			dev_id,
+			phy_id, QCA808X_PHY_MMD3_NUM, PTP_BACKUP_REG_ADDRESS,
+			value->val);
+}
+
diff --git a/qca-ssdk/src/hsl/phy/sfp_phy.c b/qca-ssdk/src/hsl/phy/sfp_phy.c
new file mode 100755
index 0000000..6fed5a0
--- /dev/null
+++ b/qca-ssdk/src/hsl/phy/sfp_phy.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) 2018, 2020-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "fal_port_ctrl.h"
+#include "adpt.h"
+#include "hsl_api.h"
+#include "hsl.h"
+#include "sfp_phy.h"
+#include "aos_timer.h"
+#include "hsl_phy.h"
+#include <linux/kconfig.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include "ssdk_plat.h"
+#include "ssdk_phy_i2c.h"
+#include "ssdk_dts.h"
+
+/******************************************************************************
+*
+* sfp_phy_init -
+*
+*/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION (5, 0, 0))
+#define SFP_PHY_FEATURES        (SUPPORTED_FIBRE | \
+                                SUPPORTED_1000baseT_Full | \
+                                SUPPORTED_10000baseT_Full | \
+                                SUPPORTED_Pause | \
+                                SUPPORTED_Asym_Pause) | \
+                                SUPPORTED_2500baseX_Full
+#else
+__ETHTOOL_DECLARE_LINK_MODE_MASK(SFP_PHY_FEATURES) __ro_after_init;
+#endif
+
+static int
+sfp_phy_probe(struct phy_device *pdev)
+{
+	pdev->autoneg = AUTONEG_DISABLE;
+	SSDK_INFO("sfp phy is probed!\n");
+	return 0;
+}
+
+static void
+sfp_phy_remove(struct phy_device *pdev)
+{
+	return;
+}
+
+static int
+sfp_phy_config_aneg(struct phy_device *pdev)
+{
+
+	return 0;
+}
+
+static int
+sfp_phy_aneg_done(struct phy_device *pdev)
+{
+
+	return SFP_ANEG_DONE;
+}
+
+static int
+sfp_read_status(struct phy_device *pdev)
+{
+	fal_port_t port;
+	a_uint32_t addr;
+	struct qca_phy_priv *priv = pdev->priv;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+	addr = pdev->mdio.addr;
+#else
+	addr = pdev->addr;
+#endif
+	port = qca_ssdk_phy_addr_to_port(priv->device_id, addr);
+	pdev->link = priv->port_old_link[port - 1];
+	pdev->speed = priv->port_old_speed[port - 1];
+	pdev->duplex = priv->port_old_duplex[port - 1];
+
+	return 0;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION (5, 0, 0))
+static int
+sfp_phy_update_link(struct phy_device *pdev)
+{
+	int ret;
+
+	ret = sfp_read_status(pdev);
+
+	return ret;
+}
+#endif
+
+static struct phy_driver sfp_phy_driver = {
+	.name		= "QCA SFP",
+	.phy_id		= SFP_PHY,
+	.phy_id_mask = SFP_PHY_MASK,
+	.probe		= sfp_phy_probe,
+	.remove		= sfp_phy_remove,
+	.config_aneg	= sfp_phy_config_aneg,
+	.aneg_done	= sfp_phy_aneg_done,
+	.read_status	= sfp_read_status,
+	.features	= SFP_PHY_FEATURES,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION (5, 0, 0))
+	.update_link	= sfp_phy_update_link,
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+	.mdiodrv.driver	= { .owner = THIS_MODULE },
+#else
+	.driver		= { .owner = THIS_MODULE },
+#endif
+};
+
+int sfp_phy_device_setup(a_uint32_t dev_id, a_uint32_t port, a_uint32_t phy_id)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	struct phy_device *phydev;
+	struct qca_phy_priv *priv;
+	a_uint32_t addr = 0;
+	struct mii_bus *bus;
+
+	priv = ssdk_phy_priv_data_get(dev_id);
+	/*create phy device*/
+#if defined(IN_PHY_I2C_MODE)
+	if (hsl_port_phy_access_type_get(dev_id, port) == PHY_I2C_ACCESS) {
+		addr = qca_ssdk_port_to_phy_mdio_fake_addr(dev_id, port);
+	} else
+#endif
+	{
+		addr = qca_ssdk_port_to_phy_addr(dev_id, port);
+	}
+	bus = ssdk_miibus_get_by_device(dev_id);
+	phydev = phy_device_create(bus, addr, phy_id, false, NULL);
+	if (IS_ERR(phydev) || phydev == NULL) {
+		SSDK_ERROR("Failed to create phy device!\n");
+		return SW_NOT_SUPPORTED;
+	}
+	/*register phy device*/
+	phy_device_register(phydev);
+
+	phydev->priv = priv;
+#endif
+	return 0;
+}
+
+void sfp_phy_device_remove(a_uint32_t dev_id, a_uint32_t port)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	struct phy_device *phydev = NULL;
+	a_uint32_t addr = 0;
+	struct mii_bus *bus;
+
+	bus = ssdk_miibus_get_by_device(dev_id);
+#if defined(IN_PHY_I2C_MODE)
+	if (hsl_port_phy_access_type_get(dev_id, port) == PHY_I2C_ACCESS) {
+		addr = qca_ssdk_port_to_phy_mdio_fake_addr(dev_id, port);
+	} else
+#endif
+	{
+		addr = qca_ssdk_port_to_phy_addr(dev_id, port);
+	}
+
+	if (addr < PHY_MAX_ADDR)
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0))
+		if (bus->mdio_map[addr])
+			phydev = to_phy_device(&bus->mdio_map[addr]->dev);
+#else
+		phydev = bus->phy_map[addr];
+#endif
+	if (phydev)
+		phy_device_remove(phydev);
+#endif
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0))
+static void sfp_features_init(void)
+{
+	const int features[] = {
+		ETHTOOL_LINK_MODE_FIBRE_BIT,
+		ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+		ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
+		ETHTOOL_LINK_MODE_Pause_BIT,
+		ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+	};
+
+	linkmode_set_bit_array(features,
+		ARRAY_SIZE(features),
+		SFP_PHY_FEATURES);
+}
+#endif
+
+int sfp_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp)
+{
+	a_uint32_t port_id = 0;
+
+	SSDK_INFO("sfp phy init for port 0x%x!\n", port_bmp);
+
+	for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++) {
+		if (port_bmp & (0x1 << port_id)) {
+			sfp_phy_device_setup(dev_id, port_id, SFP_PHY);
+		}
+	}
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0))
+	sfp_features_init();
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+	phy_driver_register(&sfp_phy_driver, THIS_MODULE);
+#else
+	phy_driver_register(&sfp_phy_driver);
+#endif
+	return 0;
+}
+
+void sfp_phy_exit(a_uint32_t dev_id, a_uint32_t port_bmp)
+{
+	a_uint32_t port_id = 0;
+
+	phy_driver_unregister(&sfp_phy_driver);
+
+	for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++) {
+		if (port_bmp & (0x1 << port_id)) {
+			sfp_phy_device_remove(dev_id, port_id);
+		}
+	}
+
+}
+
+sw_error_t sfp_phy_interface_get_mode_status(a_uint32_t dev_id,
+	a_uint32_t port_id, fal_port_interface_mode_t *interface_mode_status)
+{
+	sw_error_t rv = SW_OK;
+	a_uint16_t reg_data = 0, sfp_speed = 0;
+
+	rv = qca_phy_i2c_mii_read(dev_id, SFP_E2PROM_ADDR, SFP_SPEED_ADDR,
+		&reg_data);
+	SW_RTN_ON_ERROR(rv);
+	sfp_speed = SFP_TO_SFP_SPEED(reg_data);
+	SSDK_DEBUG("sfp_speed:%d\n", sfp_speed);
+
+	if(sfp_speed >= SFP_SPEED_1000M &&
+		sfp_speed < SFP_SPEED_2500M)
+	{
+		*interface_mode_status =  PORT_SGMII_FIBER;
+	}
+	else if(sfp_speed >= SFP_SPEED_10000M)
+	{
+		*interface_mode_status =  PORT_10GBASE_R;
+	}
+	else if(sfp_speed >= SFP_SPEED_2500M &&
+		sfp_speed < SFP_SPEED_5000M)
+	{
+		struct port_phy_status sfp_status= {0};
+		adpt_api_t *p_api;
+		struct phy_device *phydev;
+
+		rv = hsl_port_phydev_get(dev_id, port_id, &phydev);
+		SW_RTN_ON_ERROR(rv);
+		SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+		rv = p_api->adpt_port_phy_status_get(dev_id, port_id, &sfp_status);
+		SW_RTN_ON_ERROR(rv);
+
+		if (sfp_status.link_status == PORT_LINK_DOWN) {
+			/*autoneg is for different speed switching on one SFP module*/
+			if (phydev->autoneg == AUTONEG_ENABLE) {
+				if (sfp_status.link_status == PORT_LINK_DOWN) {
+					if (*interface_mode_status == PHY_SGMII_BASET) {
+						*interface_mode_status = PORT_SGMII_PLUS;
+					} else {
+						*interface_mode_status = PHY_SGMII_BASET;
+					}
+				}
+			} else {
+				*interface_mode_status = PORT_SGMII_PLUS;
+			}
+			return SW_OK;
+		}
+		if (sfp_status.link_status == PORT_LINK_UP) {
+			/*solution for SFP link up case under 10G-R mode*/
+			if ((*interface_mode_status != PHY_SGMII_BASET) &&
+				(*interface_mode_status != PORT_SGMII_PLUS)) {
+				*interface_mode_status = PORT_SGMII_PLUS;
+			}
+			return SW_OK;
+		}
+	}
+	else
+	{
+		return SW_NOT_SUPPORTED;
+	}
+
+	return SW_OK;
+}
diff --git a/qca-ssdk/src/hsl/scomphy/Makefile b/qca-ssdk/src/hsl/scomphy/Makefile
new file mode 100755
index 0000000..0e6e147
--- /dev/null
+++ b/qca-ssdk/src/hsl/scomphy/Makefile
@@ -0,0 +1,28 @@
+LOC_DIR=src/hsl/scomphy
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=scomphy_reg_access.c scomphy_init.c
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+  SRC_LIST += scomphy_port_ctrl.c
+endif
+
+ifeq (linux, $(OS))
+	ifeq (KSLIB, $(MODULE_TYPE))
+    ifneq (TRUE, $(KERNEL_MODE))
+      SRC_LIST=scomphy_reg_access.c scomphy_init.c
+	  endif
+	endif
+endif
+
+ifeq (, $(findstring SCOMPHY, $(SUPPORT_CHIP)))
+  SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/hsl/scomphy/scomphy_init.c b/qca-ssdk/src/hsl/scomphy/scomphy_init.c
new file mode 100755
index 0000000..7f82807
--- /dev/null
+++ b/qca-ssdk/src/hsl/scomphy/scomphy_init.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup scomphy_init SCOMPHY_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_phy.h"
+#include "hsl_port_prop.h"
+#include "scomphy_port_ctrl.h"
+#include "scomphy_reg_access.h"
+#include "scomphy_init.h"
+
+static ssdk_init_cfg * scomphy_cfg[SW_MAX_NR_DEV] = { 0 };
+
+static sw_error_t
+scomphy_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
+{
+	hsl_port_prop_t p_type;
+	hsl_dev_t *pdev = NULL;
+	fal_port_t port_id;
+	a_uint32_t port_bmp = qca_ssdk_port_bmp_get(dev_id);
+
+	pdev = hsl_dev_ptr_get(dev_id);
+	if (pdev == NULL)
+		return SW_NOT_INITIALIZED;
+
+	/* for port property set, SSDK should not generate some limitations */
+	for (port_id = 1; port_id < SW_MAX_NR_PORT; port_id++)
+	{
+		if((1 << port_id) & port_bmp)
+		{
+			hsl_port_prop_portmap_set(dev_id, port_id);
+
+			for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
+			{
+				SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+			}
+		}
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+scomphy_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode)
+{
+	sw_error_t rv = SW_OK;
+	hsl_dev_t *pdev = NULL;
+	a_uint8_t nr_ports = 0;
+	a_uint32_t port_bmp = qca_ssdk_port_bmp_get(dev_id);
+
+	pdev = hsl_dev_ptr_get(dev_id);
+	if (pdev == NULL)
+		return SW_NOT_INITIALIZED;
+
+	while (port_bmp) {
+		if (port_bmp & 1)
+			nr_ports++;
+		port_bmp >>= 1;
+	}
+
+	pdev->nr_ports = nr_ports;
+	pdev->nr_phy = nr_ports;
+	pdev->cpu_port_nr = 0;
+	pdev->hw_vlan_query = A_TRUE;
+	pdev->cpu_mode = cpu_mode;
+
+	return rv;
+}
+
+
+static sw_error_t
+_scomphy_reset(a_uint32_t dev_id)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_bmp = 0;
+	a_uint8_t port_id = 0;
+
+	HSL_DEV_ID_CHECK(dev_id);
+
+	port_bmp = qca_ssdk_port_bmp_get(dev_id);
+	while (port_bmp) {
+		if (port_bmp & 1)
+			SW_RTN_ON_ERROR(scomphy_port_reset(dev_id, port_id));
+
+		port_bmp >>= 1;
+		port_id++;
+	}
+
+	return rv;
+}
+
+sw_error_t
+scomphy_cleanup(a_uint32_t dev_id)
+{
+	sw_error_t rv = SW_OK;
+
+	if (scomphy_cfg[dev_id])
+	{
+		SW_RTN_ON_ERROR(hsl_port_prop_cleanup_by_dev(dev_id));
+
+		aos_mem_free(scomphy_cfg[dev_id]);
+		scomphy_cfg[dev_id] = NULL;
+	}
+
+	return rv;
+}
+
+/**
+ * @brief reset hsl layer.
+ * @details Comments:
+ *   This operation will reset hsl layer
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_reset(a_uint32_t dev_id)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_reset(dev_id);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Init hsl layer.
+ * @details Comments:
+ *   This operation will init hsl layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+scomphy_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+	HSL_DEV_ID_CHECK(dev_id);
+
+	if (NULL == scomphy_cfg[dev_id])
+	{
+		scomphy_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg));
+	}
+
+	if (NULL == scomphy_cfg[dev_id])
+	{
+		return SW_OUT_OF_MEM;
+	}
+
+	aos_mem_copy(scomphy_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+
+	SW_RTN_ON_ERROR(scomphy_reg_access_init(dev_id, cfg));
+
+	SW_RTN_ON_ERROR(scomphy_dev_init(dev_id, cfg->cpu_mode));
+
+	{
+		sw_error_t rv;
+
+		SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id));
+		SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
+		SW_RTN_ON_ERROR(scomphy_portproperty_init(dev_id, cfg->cpu_mode));
+
+		SCOMPHY_PORT_CTRL_INIT(rv, dev_id);
+
+		{
+			hsl_api_t *p_api;
+
+			SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+			p_api->dev_reset   = scomphy_reset;
+			p_api->dev_clean   = scomphy_cleanup;
+		}
+	}
+
+	return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/scomphy/scomphy_port_ctrl.c b/qca-ssdk/src/hsl/scomphy/scomphy_port_ctrl.c
new file mode 100644
index 0000000..e55dcaa
--- /dev/null
+++ b/qca-ssdk/src/hsl/scomphy/scomphy_port_ctrl.c
@@ -0,0 +1,2078 @@
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*qca808x_start*/
+/**
+ * @defgroup scomphy_port_ctrl SCOMPHY_PORT_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "scomphy_port_ctrl.h"
+#include "hsl_phy.h"
+
+static sw_error_t
+_scomphy_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id,
+		       fal_port_duplex_t duplex)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_duplex_set)
+		return SW_NOT_SUPPORTED;
+
+	if (FAL_DUPLEX_BUTT <= duplex)
+	{
+		return SW_BAD_PARAM;
+	}
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex);
+	SW_RTN_ON_ERROR (rv);
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id,
+		       fal_port_duplex_t * pduplex)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_duplex_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_duplex_get (dev_id, phy_id, pduplex);
+	SW_RTN_ON_ERROR (rv);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_speed_set (a_uint32_t dev_id, fal_port_t port_id,
+		      fal_port_speed_t speed)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_speed_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_speed_set (dev_id, phy_id, speed);
+	SW_RTN_ON_ERROR (rv);
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_speed_get (a_uint32_t dev_id, fal_port_t port_id,
+		      fal_port_speed_t * pspeed)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_speed_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+	rv = phy_drv->phy_speed_get (dev_id, phy_id, pspeed);
+	SW_RTN_ON_ERROR (rv);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * status)
+{
+	a_uint32_t phy_id;
+	sw_error_t rv;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_autoneg_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	*status = phy_drv->phy_autoneg_status_get (dev_id, phy_id);
+
+	return SW_OK;
+}
+
+static sw_error_t
+_scomphy_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_autoneg_enable_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_autoneg_enable_set (dev_id, phy_id);
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_restart_autoneg)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_restart_autoneg (dev_id, phy_id);
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id,
+			    a_uint32_t autoadv)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_autoneg_adv_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_autoneg_adv_set (dev_id, phy_id, autoadv);
+	SW_RTN_ON_ERROR (rv);
+
+	return SW_OK;
+}
+
+static sw_error_t
+_scomphy_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id,
+			    a_uint32_t * autoadv)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_autoneg_adv_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	*autoadv = 0;
+	rv = phy_drv->phy_autoneg_adv_get (dev_id, phy_id, autoadv);
+	SW_RTN_ON_ERROR (rv);
+
+	return SW_OK;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_scomphy_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_powersave_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_powersave_set (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_powersave_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_powersave_get (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_hibernation_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_hibernation_set (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id,
+			  a_bool_t * enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_hibernation_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_hibernation_get (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+		fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_cdt)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_cdt (dev_id, phy_id, mdi_pair, cable_status, cable_len);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_8023az_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_8023az_set (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id,
+		       a_bool_t * enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_8023az_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_8023az_get (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_mdix_set (a_uint32_t dev_id, fal_port_t port_id,
+		     fal_port_mdix_mode_t mode)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_mdix_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_mdix_set (dev_id, phy_id, mode);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id,
+		     fal_port_mdix_mode_t * mode)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_mdix_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_mdix_get (dev_id, phy_id, mode);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			    fal_port_mdix_status_t * mode)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_mdix_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_mdix_status_get (dev_id, phy_id, mode);
+
+	return rv;
+}
+/*qca808x_end*/
+static sw_error_t
+_scomphy_port_combo_prefer_medium_set (a_uint32_t dev_id, fal_port_t port_id,
+				    fal_port_medium_t phy_medium)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_combo_prefer_medium_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_combo_prefer_medium_set (dev_id, phy_id, phy_medium);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_combo_prefer_medium_get (a_uint32_t dev_id, fal_port_t port_id,
+				    fal_port_medium_t * phy_medium)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_combo_prefer_medium_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_combo_prefer_medium_get (dev_id, phy_id, phy_medium);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_combo_medium_status_get (a_uint32_t dev_id, fal_port_t port_id,
+				    fal_port_medium_t * phy_medium)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_combo_medium_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_combo_medium_status_get (dev_id, phy_id, phy_medium);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_combo_fiber_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+				 fal_port_fiber_mode_t fiber_mode)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_combo_fiber_mode_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_combo_fiber_mode_set (dev_id, phy_id, fiber_mode);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_combo_fiber_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+				 fal_port_fiber_mode_t * fiber_mode)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_combo_fiber_mode_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_combo_fiber_mode_get (dev_id, phy_id, fiber_mode);
+
+	return rv;
+}
+/*qca808x_start*/
+static sw_error_t
+_scomphy_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_local_loopback_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_local_loopback_set (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_local_loopback_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_local_loopback_get (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_remote_loopback_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_remote_loopback_set (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t * enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_remote_loopback_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_remote_loopback_get (dev_id, phy_id, enable);
+
+	return rv;
+}
+#endif
+
+static sw_error_t
+_scomphy_port_power_off (a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_power_off)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_power_off(dev_id, phy_id);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_power_on (a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_power_on)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_power_on(dev_id, phy_id);
+
+	return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_scomphy_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_wol_status_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_wol_status_set (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id,
+				a_bool_t * enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_wol_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_wol_status_get (dev_id, phy_id, enable);
+
+	return rv;
+}
+/*qca808x_end*/
+static sw_error_t
+_scomphy_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_interface_mode_t  mode)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_interface_mode_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_interface_mode_set (dev_id, phy_id,mode);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_interface_mode_t * mode)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_interface_mode_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_interface_mode_get (dev_id, phy_id,mode);
+
+	return rv;
+}
+/*qca808x_start*/
+static sw_error_t
+_scomphy_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_interface_mode_t * mode)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_interface_mode_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_interface_mode_status_get (dev_id, phy_id,mode);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id,
+				fal_mac_addr_t * mac)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_magic_frame_mac_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_magic_frame_mac_set (dev_id, phy_id,mac);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id,
+				fal_mac_addr_t * mac)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_magic_frame_mac_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_magic_frame_mac_get (dev_id, phy_id,mac);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_counter_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_counter_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_counter_set (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_counter_get (a_uint32_t dev_id, fal_port_t port_id,
+		       a_bool_t * enable)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_counter_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_counter_get (dev_id, phy_id, enable);
+
+	return rv;
+}
+
+static sw_error_t
+_scomphy_port_counter_show (a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_counter_info_t * counter_info)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_counter_show)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_counter_show (dev_id, phy_id,counter_info);
+
+	return rv;
+}
+#endif
+
+static sw_error_t
+_scomphy_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			    a_bool_t * status)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_link_status_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id))
+	{
+		*status = A_TRUE;
+	}
+	else
+	{
+		*status = A_FALSE;
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+_scomphy_port_reset (a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_reset)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_reset(dev_id, phy_id);
+
+	return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+static sw_error_t
+_scomphy_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id,
+				a_uint16_t * org_id, a_uint16_t * rev_id)
+{
+	sw_error_t rv;
+	a_uint32_t phy_id = 0;
+	hsl_phy_ops_t *phy_drv;
+	a_uint32_t phy_data;
+
+	HSL_DEV_ID_CHECK (dev_id);
+
+	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+	if (NULL == phy_drv->phy_id_get)
+		return SW_NOT_SUPPORTED;
+
+	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+	SW_RTN_ON_ERROR (rv);
+
+	rv = phy_drv->phy_id_get (dev_id, phy_id, &phy_data);
+	SW_RTN_ON_ERROR (rv);
+
+	*org_id = (phy_data >> 16) & 0xffff;
+	*rev_id = phy_data & 0xffff;
+
+	return rv;
+}
+#endif
+
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id,
+		      fal_port_duplex_t duplex)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_duplex_set (dev_id, port_id, duplex);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id,
+		      fal_port_duplex_t * pduplex)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_duplex_get (dev_id, port_id, pduplex);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_speed_set (a_uint32_t dev_id, fal_port_t port_id,
+		     fal_port_speed_t speed)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_speed_set (dev_id, port_id, speed);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_speed_get (a_uint32_t dev_id, fal_port_t port_id,
+		     fal_port_speed_t * pspeed)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_speed_get (dev_id, port_id, pspeed);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * status)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_autoneg_status_get (dev_id, port_id, status);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_autoneg_enable (dev_id, port_id);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_autoneg_restart (dev_id, port_id);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ *   @details  Comments:
+ *   auto negotiation advtisement ability is defined by macro such as
+ *   FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id,
+			   a_uint32_t autoadv)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_autoneg_adv_set (dev_id, port_id, autoadv);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id,
+			   a_uint32_t * autoadv)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_autoneg_adv_get (dev_id, port_id, autoadv);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t enable)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_powersave_set (dev_id, port_id, enable);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t * enable)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_powersave_get (dev_id, port_id, enable);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t enable)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_hibernate_set (dev_id, port_id, enable);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id,
+			 a_bool_t * enable)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_hibernate_get (dev_id, port_id, enable);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Run cable diagnostic test on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mdi_pair mdi pair id
+ * @param[out] cable_status cable status
+ * @param[out] cable_len cable len
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+	       fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_cdt (dev_id, port_id, mdi_pair, cable_status, cable_len);
+	HSL_API_UNLOCK;
+	return rv;
+}
+/**
+ * @brief Set 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_8023az_set (dev_id, port_id, enable);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get 8023az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id,
+		      a_bool_t * enable)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_8023az_get (dev_id, port_id, enable);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Set mdix on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_mdix_set (a_uint32_t dev_id, a_uint32_t phy_id,
+		    fal_port_mdix_mode_t mode)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_mdix_set (dev_id, phy_id, mode);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get mdix configuration on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode
+ * @return SW_OK or error code
+ */
+
+HSL_LOCAL sw_error_t
+scomphy_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id,
+		    fal_port_mdix_mode_t * mode)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_mdix_get (dev_id, port_id, mode);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get mdix status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode
+ * @return SW_OK or error code
+ */
+
+HSL_LOCAL sw_error_t
+scomphy_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			   fal_port_mdix_status_t * mode)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_mdix_status_get (dev_id, port_id, mode);
+	HSL_API_UNLOCK;
+	return rv;
+}
+/*qca808x_end*/
+/**
+ * @brief Set combo prefer medium on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] phy_medium [fiber or copper]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_combo_prefer_medium_set (a_uint32_t dev_id, a_uint32_t phy_id,
+				   fal_port_medium_t phy_medium)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_combo_prefer_medium_set (dev_id, phy_id, phy_medium);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get combo prefer medium on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] phy_medium [fiber or copper]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_combo_prefer_medium_get (a_uint32_t dev_id, a_uint32_t phy_id,
+				   fal_port_medium_t * phy_medium)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_combo_prefer_medium_get (dev_id, phy_id, phy_medium);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get current combo medium status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] phy_medium [fiber or copper]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_combo_medium_status_get (a_uint32_t dev_id, a_uint32_t phy_id,
+				   fal_port_medium_t * phy_medium)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_combo_medium_status_get (dev_id, phy_id, phy_medium);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Set fiber mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] fiber mode [1000bx or 100fx]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_combo_fiber_mode_set (a_uint32_t dev_id, a_uint32_t phy_id,
+				fal_port_fiber_mode_t fiber_mode)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_combo_fiber_mode_set (dev_id, phy_id, fiber_mode);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get fiber mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] fiber mode [1000bx or 100fx]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_combo_fiber_mode_get (a_uint32_t dev_id, a_uint32_t phy_id,
+				fal_port_fiber_mode_t * fiber_mode)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_combo_fiber_mode_get (dev_id, phy_id, fiber_mode);
+	HSL_API_UNLOCK;
+	return rv;
+}
+/*qca808x_start*/
+/**
+ * @brief Set phy local loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t enable)
+{
+	sw_error_t rv;
+	HSL_API_LOCK;
+	rv = _scomphy_port_local_loopback_set (dev_id, port_id, enable);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get phy local loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+			      a_bool_t * enable)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_local_loopback_get (dev_id, port_id, enable);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Set phy remote loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable)
+{
+	sw_error_t rv;
+	HSL_API_LOCK;
+	rv = _scomphy_port_remote_loopback_set (dev_id, port_id, enable);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get phy remote loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_remote_loopback_get (dev_id, port_id, enable);
+	HSL_API_UNLOCK;
+	return rv;
+}
+#endif
+
+/**
+ * @brief phy power off on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_power_off (a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv;
+	HSL_API_LOCK;
+	rv = _scomphy_port_power_off (dev_id, port_id);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief phy power on on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in]
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_power_on (a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv;
+	HSL_API_LOCK;
+	rv = _scomphy_port_power_on (dev_id, port_id);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+/**
+ * @brief Set phy wol enable on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t enable)
+{
+	sw_error_t rv;
+	HSL_API_LOCK;
+	rv = _scomphy_port_wol_status_set (dev_id, port_id, enable);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get phy wol status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_bool_t * enable)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_wol_status_get (dev_id, port_id, enable);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Set phy magic frame mac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mac address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_mac_addr_t * mac)
+{
+	sw_error_t rv;
+	HSL_API_LOCK;
+	rv = _scomphy_port_magic_frame_mac_set (dev_id, port_id, mac);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get phy magic frame mac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mac address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_mac_addr_t * mac)
+{
+	sw_error_t rv;
+	HSL_API_LOCK;
+	rv = _scomphy_port_magic_frame_mac_get (dev_id, port_id, mac);
+	HSL_API_UNLOCK;
+	return rv;
+}
+/*qca808x_end*/
+/**
+ * @brief Set phy interface mode.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] interface mode..
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t  mode)
+{
+	sw_error_t rv;
+	HSL_API_LOCK;
+	rv = _scomphy_port_interface_mode_set (dev_id, port_id, mode);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Set phy interface mode.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] interface mode..
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t  * mode)
+{
+	sw_error_t rv;
+	HSL_API_LOCK;
+	rv = _scomphy_port_interface_mode_get (dev_id, port_id, mode);
+	HSL_API_UNLOCK;
+	return rv;
+}
+/*qca808x_start*/
+/**
+ * @brief Set phy interface mode status.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] interface mode..
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			      fal_port_interface_mode_t  * mode)
+{
+	sw_error_t rv;
+	HSL_API_LOCK;
+	rv = _scomphy_port_interface_mode_status_get (dev_id, port_id, mode);
+	HSL_API_UNLOCK;
+	return rv;
+}
+#endif
+
+/**
+ * @brief Get link status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status link status up (A_TRUE) or down (A_FALSE)
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id,
+			   a_bool_t * status)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _scomphy_port_link_status_get (dev_id, port_id, status);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+/**
+ * @brief Set counter status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_counter_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_counter_set (dev_id, port_id, enable);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get counter status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_counter_get (a_uint32_t dev_id, fal_port_t port_id,
+		      a_bool_t * enable)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_counter_get (dev_id, port_id, enable);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+/**
+ * @brief Get counter statistics  on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] frame counter statistics
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_counter_show(a_uint32_t dev_id, fal_port_t port_id,
+		      fal_port_counter_info_t * counter_info)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_counter_show (dev_id, port_id, counter_info);
+	HSL_API_UNLOCK;
+	return rv;
+}
+#endif
+
+/**
+ * @brief software reset on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in]
+ * @return SW_OK or error code
+ */
+sw_error_t
+scomphy_port_reset (a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv;
+	HSL_API_LOCK;
+	rv = _scomphy_port_reset (dev_id, port_id);
+	HSL_API_UNLOCK;
+	return rv;
+}
+
+#ifndef IN_PORTCONTROL_MINI
+/**
+ * @brief Get phy id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] org_id and rev_id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+scomphy_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_uint16_t * org_id, a_uint16_t * rev_id)
+{
+	sw_error_t rv;
+
+	HSL_API_LOCK;
+	rv = _scomphy_port_phy_id_get (dev_id, port_id, org_id,rev_id);
+	HSL_API_UNLOCK;
+	return rv;
+}
+#endif
+
+sw_error_t
+scomphy_port_ctrl_init(a_uint32_t dev_id)
+{
+	HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+	p_api->port_duplex_get = scomphy_port_duplex_get;
+	p_api->port_duplex_set = scomphy_port_duplex_set;
+	p_api->port_speed_get = scomphy_port_speed_get;
+	p_api->port_speed_set = scomphy_port_speed_set;
+	p_api->port_autoneg_status_get = scomphy_port_autoneg_status_get;
+	p_api->port_autoneg_enable = scomphy_port_autoneg_enable;
+	p_api->port_autoneg_restart = scomphy_port_autoneg_restart;
+	p_api->port_autoneg_adv_get = scomphy_port_autoneg_adv_get;
+	p_api->port_autoneg_adv_set = scomphy_port_autoneg_adv_set;
+#ifndef IN_PORTCONTROL_MINI
+	p_api->port_powersave_set = scomphy_port_powersave_set;
+	p_api->port_powersave_get = scomphy_port_powersave_get;
+	p_api->port_hibernate_set = scomphy_port_hibernate_set;
+	p_api->port_hibernate_get = scomphy_port_hibernate_get;
+	p_api->port_cdt = scomphy_port_cdt;
+	p_api->port_8023az_set = scomphy_port_8023az_set;
+	p_api->port_8023az_get = scomphy_port_8023az_get;
+	p_api->port_mdix_set = scomphy_port_mdix_set;
+	p_api->port_mdix_get = scomphy_port_mdix_get;
+	p_api->port_mdix_status_get = scomphy_port_mdix_status_get;
+/*qca808x_end*/
+	p_api->port_combo_prefer_medium_set = scomphy_port_combo_prefer_medium_set;
+	p_api->port_combo_prefer_medium_get = scomphy_port_combo_prefer_medium_get;
+	p_api->port_combo_medium_status_get = scomphy_port_combo_medium_status_get;
+	p_api->port_combo_fiber_mode_set = scomphy_port_combo_fiber_mode_set;
+	p_api->port_combo_fiber_mode_get = scomphy_port_combo_fiber_mode_get;
+/*qca808x_start*/
+	p_api->port_local_loopback_set = scomphy_port_local_loopback_set;
+	p_api->port_local_loopback_get = scomphy_port_local_loopback_get;
+	p_api->port_remote_loopback_set = scomphy_port_remote_loopback_set;
+	p_api->port_remote_loopback_get = scomphy_port_remote_loopback_get;
+#endif
+	p_api->port_power_off = scomphy_port_power_off;
+	p_api->port_power_on = scomphy_port_power_on;
+#ifndef IN_PORTCONTROL_MINI
+	p_api->port_wol_status_set = scomphy_port_wol_status_set;
+	p_api->port_wol_status_get = scomphy_port_wol_status_get;
+	p_api->port_magic_frame_mac_set = scomphy_port_magic_frame_mac_set;
+	p_api->port_magic_frame_mac_get = scomphy_port_magic_frame_mac_get;
+/*qca808x_end*/
+	p_api->port_interface_mode_set = scomphy_port_interface_mode_set;
+	p_api->port_interface_mode_get = scomphy_port_interface_mode_get;
+/*qca808x_start*/
+	p_api->port_interface_mode_status_get = scomphy_port_interface_mode_status_get;
+	p_api->port_counter_set = scomphy_port_counter_set;
+	p_api->port_counter_get = scomphy_port_counter_get;
+	p_api->port_counter_show = scomphy_port_counter_show;
+#endif
+	p_api->port_link_status_get = scomphy_port_link_status_get;
+	p_api->port_reset = scomphy_port_reset;
+#ifndef IN_PORTCONTROL_MINI
+	p_api->port_phy_id_get = scomphy_port_phy_id_get;
+#endif
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+/*qca808x_end*/
diff --git a/qca-ssdk/src/hsl/scomphy/scomphy_reg_access.c b/qca-ssdk/src/hsl/scomphy/scomphy_reg_access.c
new file mode 100755
index 0000000..ed6f83c
--- /dev/null
+++ b/qca-ssdk/src/hsl/scomphy/scomphy_reg_access.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*qca808x_start*/
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "sd.h"
+#include "scomphy_reg_access.h"
+#include "hsl_phy.h"
+
+#if defined(API_LOCK)
+static aos_lock_t mdio_lock;
+#define MDIO_LOCKER_INIT    aos_lock_init(&mdio_lock)
+#define MDIO_LOCKER_LOCK    aos_lock(&mdio_lock)
+#define MDIO_LOCKER_UNLOCK  aos_unlock(&mdio_lock)
+#else
+#define MDIO_LOCKER_INIT
+#define MDIO_LOCKER_LOCK
+#define MDIO_LOCKER_UNLOCK
+#endif
+
+sw_error_t
+scomphy_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+             a_uint32_t reg, a_uint16_t * value)
+{
+	sw_error_t rv;
+
+	MDIO_LOCKER_LOCK;
+	rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value);
+	MDIO_LOCKER_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+scomphy_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+             a_uint32_t reg, a_uint16_t value)
+{
+	sw_error_t rv;
+
+	MDIO_LOCKER_LOCK;
+	rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value);
+	MDIO_LOCKER_UNLOCK;
+	return rv;
+}
+
+sw_error_t
+scomphy_phy_i2c_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+             a_uint32_t reg, a_uint16_t * value)
+{
+	sw_error_t rv;
+
+	rv = sd_reg_i2c_get(dev_id, phy_addr, reg, value);
+
+	return rv;
+}
+
+sw_error_t
+scomphy_phyi2c_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+             a_uint32_t reg, a_uint16_t value)
+{
+	sw_error_t rv;
+
+	rv = sd_reg_i2c_set(dev_id, phy_addr, reg, value);
+
+	return rv;
+}
+/*qca808x_end*/
+sw_error_t
+scomphy_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+	a_uint8_t *val, a_uint32_t len)
+{
+	sw_error_t rv;
+
+	rv = sd_reg_hdr_get(dev_id, reg_addr, val, len);
+
+	return rv;
+}
+
+sw_error_t
+scomphy_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+	a_uint8_t *val, a_uint32_t len)
+{
+	sw_error_t rv;
+
+	rv = sd_reg_hdr_set(dev_id, reg_addr, val, len);
+
+	return rv;
+}
+
+sw_error_t
+scomphy_uniphy_reg_get(a_uint32_t dev_id, a_uint32_t index,
+	a_uint32_t reg_addr, a_uint8_t *val, a_uint32_t len)
+{
+	sw_error_t rv;
+
+	rv = sd_reg_uniphy_get(dev_id, index, reg_addr, val, len);
+
+	return rv;
+}
+
+sw_error_t
+scomphy_uniphy_reg_set(a_uint32_t dev_id, a_uint32_t index,
+	a_uint32_t reg_addr, a_uint8_t *val, a_uint32_t len)
+{
+	sw_error_t rv;
+
+	rv = sd_reg_uniphy_set(dev_id, index, reg_addr, val, len);
+
+	return rv;
+}
+/*qca808x_start*/
+sw_error_t
+scomphy_reg_access_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+	hsl_api_t *p_api;
+
+	MDIO_LOCKER_INIT;
+
+	SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+	p_api->phy_get = scomphy_phy_get;
+	p_api->phy_set = scomphy_phy_set;
+	p_api->phy_i2c_get = scomphy_phy_i2c_get;
+	p_api->phy_i2c_set = scomphy_phyi2c_set;
+/*qca808x_end*/
+	if(cfg->phy_id == MP_GEPHY)
+	{
+		p_api->reg_get = scomphy_reg_get;
+		p_api->reg_set = scomphy_reg_set;
+		p_api->uniphy_reg_get = scomphy_uniphy_reg_get;
+		p_api->uniphy_reg_set = scomphy_uniphy_reg_set;
+	}
+/*qca808x_start*/
+	return SW_OK;
+}
+/*qca808x_end*/
diff --git a/qca-ssdk/src/hsl/sfp/Makefile b/qca-ssdk/src/hsl/sfp/Makefile
new file mode 100755
index 0000000..550ba4d
--- /dev/null
+++ b/qca-ssdk/src/hsl/sfp/Makefile
@@ -0,0 +1,16 @@
+LOC_DIR=src/hsl/sfp
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=
+
+ifeq (TRUE, $(IN_SFP))
+	SRC_LIST+=sfp.c sfp_access.c
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/hsl/sfp/sfp.c b/qca-ssdk/src/hsl/sfp/sfp.c
new file mode 100644
index 0000000..4f5ca0f
--- /dev/null
+++ b/qca-ssdk/src/hsl/sfp/sfp.c
@@ -0,0 +1,2296 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "sfp_access.h"
+#include "sfp_reg.h"
+
+sw_error_t
+sfp_eeprom_data_get(a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t i2c_addr,
+		a_uint32_t offset, a_uint8_t *buf, a_uint32_t count)
+{
+	return sfp_data_tbl_get(
+			dev_id, index, i2c_addr,
+			offset,
+			buf, count);
+
+}
+
+sw_error_t
+sfp_eeprom_data_set(a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t i2c_addr,
+		a_uint32_t offset, a_uint8_t *buf, a_uint32_t count)
+{
+	return sfp_data_tbl_set(
+			dev_id, index, i2c_addr,
+			offset,
+			buf, count);
+
+}
+
+sw_error_t
+sfp_dev_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_dev_type_u *value)
+{
+	return sfp_data_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_DEV_TYPE_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+sfp_dev_type_ext_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_dev_type_ext_u *value)
+{
+	return sfp_data_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_DEV_TYPE_EXT_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+sfp_dev_connector_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_dev_connector_type_u *value)
+{
+	return sfp_data_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_DEV_CONNECTOR_TYPE_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+sfp_transc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_transc_u *value)
+{
+	return sfp_data_tbl_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_TRANSC_ADDRESS,
+			value->val, 8);
+}
+
+sw_error_t
+sfp_encoding_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_encoding_u *value)
+{
+	return sfp_data_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_ENCODING_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+sfp_br_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_br_u *value)
+{
+	return sfp_data_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_BR_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+sfp_rate_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_rate_u *value)
+{
+	return sfp_data_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_RATE_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+sfp_link_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_link_len_u *value)
+{
+	return sfp_data_tbl_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_LINK_LEN_ADDRESS,
+			value->val, 6);
+}
+
+sw_error_t
+sfp_vendor_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_vendor_u *value)
+{
+	return sfp_data_tbl_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_VENDOR_ADDRESS,
+			value->val, 40);
+}
+
+sw_error_t
+sfp_laser_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_laser_u *value)
+{
+	return sfp_data_tbl_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_LASER_ADDRESS,
+			value->val, 2);
+}
+
+sw_error_t
+sfp_base_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_base_u *value)
+{
+	return sfp_data_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_BASE_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+sfp_option_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_option_u *value)
+{
+	return sfp_data_tbl_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_OPTION_ADDRESS,
+			value->val, 2);
+}
+
+sw_error_t
+sfp_rate_ctrl_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_rate_ctrl_u *value)
+{
+	return sfp_data_tbl_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_RATE_CTRL_ADDRESS,
+			value->val, 2);
+}
+
+sw_error_t
+sfp_vendor_ext_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_vendor_ext_u *value)
+{
+	return sfp_data_tbl_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_VENDOR_EXT_ADDRESS,
+			value->val, 24);
+}
+
+sw_error_t
+sfp_enhanced_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_enhanced_u *value)
+{
+	return sfp_data_tbl_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_ENHANCED_ADDRESS,
+			value->val, 3);
+}
+
+sw_error_t
+sfp_ext_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_ext_u *value)
+{
+	return sfp_data_get(
+			dev_id, index, SFP_EEPROM_BASE_A0,
+			SFP_BASE_ADDR + SFP_EXT_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+sfp_dev_type_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_dev_type_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_dev_type_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.id;
+	return ret;
+}
+
+sw_error_t
+sfp_dev_type_ext_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_dev_type_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_dev_type_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.id;
+	return ret;
+}
+
+sw_error_t
+sfp_dev_connector_type_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_dev_connector_type_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_dev_connector_type_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.code;
+	return ret;
+}
+
+sw_error_t
+sfp_transc_sonet_ccode_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_transc_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_transc_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.sonet_ccode_2;
+	return ret;
+}
+
+sw_error_t
+sfp_transc_fiber_ch_tech_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_transc_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_transc_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.fiber_ch_tech_1;
+	return ret;
+}
+
+sw_error_t
+sfp_transc_sonet_ccode_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_transc_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_transc_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.sonet_ccode_1;
+	return ret;
+}
+
+sw_error_t
+sfp_transc_fiber_ch_speed_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_transc_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_transc_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.fiber_ch_speed;
+	return ret;
+}
+
+sw_error_t
+sfp_transc_fiber_ch_tech_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_transc_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_transc_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.fiber_ch_tech_2;
+	return ret;
+}
+
+sw_error_t
+sfp_transc_cable_tech_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_transc_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_transc_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cable_tech;
+	return ret;
+}
+
+sw_error_t
+sfp_transc_fiber_ch_link_len_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_transc_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_transc_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.fiber_ch_link_len;
+	return ret;
+}
+
+sw_error_t
+sfp_transc_unallocated_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_transc_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_transc_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.unallocated;
+	return ret;
+}
+
+sw_error_t
+sfp_transc_fiber_chan_tm_media_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_transc_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_transc_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.fiber_chan_tm_media;
+	return ret;
+}
+
+sw_error_t
+sfp_transc_escon_ccode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_transc_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_transc_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.escon_ccode;
+	return ret;
+}
+
+sw_error_t
+sfp_transc_infiniband_ccode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_transc_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_transc_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.infiniband_ccode;
+	return ret;
+}
+
+sw_error_t
+sfp_transc_eth_ccode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_transc_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_transc_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.eth_ccode;
+	return ret;
+}
+
+sw_error_t
+sfp_transc_eth_10g_ccode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_transc_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_transc_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.eth_10g_ccode;
+	return ret;
+}
+
+sw_error_t
+sfp_encoding_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_encoding_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_encoding_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.code;
+	return ret;
+}
+
+sw_error_t
+sfp_br_bit_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_br_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_br_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.bit;
+	return ret;
+}
+
+sw_error_t
+sfp_rate_id_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_rate_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_rate_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.id;
+	return ret;
+}
+
+sw_error_t
+sfp_link_len_om3_mode_1m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_link_len_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_link_len_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.om3_mode_1m;
+	return ret;
+}
+
+sw_error_t
+sfp_link_len_single_mode_100m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_link_len_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_link_len_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.single_mode_100m;
+	return ret;
+}
+
+sw_error_t
+sfp_link_len_om2_mode_10m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_link_len_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_link_len_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.om2_mode_10m;
+	return ret;
+}
+
+sw_error_t
+sfp_link_len_copper_mode_1m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_link_len_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_link_len_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.copper_mode_1m;
+	return ret;
+}
+
+sw_error_t
+sfp_link_len_om1_mode_10m_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_link_len_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_link_len_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.om1_mode_10m;
+	return ret;
+}
+
+sw_error_t
+sfp_link_len_single_mode_km_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_link_len_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_link_len_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.single_mode_km;
+	return ret;
+}
+
+sw_error_t
+sfp_vendor_rev_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint8_t value[4])
+{
+	union sfp_vendor_u reg_val;
+	sw_error_t ret = SW_OK;
+	a_uint8_t i;
+
+	ret = sfp_vendor_get(dev_id, index, &reg_val);
+
+	for (i = 0; i < 4; i++) {
+		value[i] = reg_val.val[i];
+	}
+
+	return ret;
+}
+
+sw_error_t
+sfp_vendor_name_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint8_t value[16])
+{
+	union sfp_vendor_u reg_val;
+	sw_error_t ret = SW_OK;
+	a_uint8_t i;
+
+	ret = sfp_vendor_get(dev_id, index, &reg_val);
+
+	for (i = 0; i < 16; i++) {
+		value[i] = reg_val.val[i];
+	}
+
+	return ret;
+}
+
+sw_error_t
+sfp_vendor_oui_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint8_t value[3])
+{
+	union sfp_vendor_u reg_val;
+	sw_error_t ret = SW_OK;
+	a_uint8_t i;
+
+	ret = sfp_vendor_get(dev_id, index, &reg_val);
+
+	for (i = 0; i < 3; i++) {
+		value[i] = reg_val.val[i];
+	}
+
+	return ret;
+}
+
+sw_error_t
+sfp_vendor_pn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint8_t value[16])
+{
+	union sfp_vendor_u reg_val;
+	sw_error_t ret = SW_OK;
+	a_uint8_t i;
+
+	ret = sfp_vendor_get(dev_id, index, &reg_val);
+
+	for (i = 0; i < 16; i++) {
+		value[i] = reg_val.val[i];
+	}
+
+	return ret;
+}
+sw_error_t
+sfp_laser_wavelength_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_laser_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_laser_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.wavelength_0 << 8
+		| reg_val.bf.wavelength_1;
+	return ret;
+}
+
+sw_error_t
+sfp_base_check_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_base_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_base_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.check_code;
+	return ret;
+}
+
+sw_error_t
+sfp_option_linear_recv_output_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_option_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_option_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.linear_recv_output;
+	return ret;
+}
+
+sw_error_t
+sfp_option_pwr_level_declar_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_option_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_option_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pwr_level_declar;
+	return ret;
+}
+
+sw_error_t
+sfp_option_unallocated_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_option_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_option_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.unallocated_1;
+	return ret;
+}
+
+sw_error_t
+sfp_option_unallocated_3_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_option_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_option_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.unallocated_3;
+	return ret;
+}
+
+sw_error_t
+sfp_option_loss_signal_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_option_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_option_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.loss_signal;
+	return ret;
+}
+
+sw_error_t
+sfp_option_rate_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_option_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_option_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rate_sel;
+	return ret;
+}
+
+sw_error_t
+sfp_option_unallocated_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_option_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_option_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.unallocated_2;
+	return ret;
+}
+
+sw_error_t
+sfp_option_loss_invert_signal_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_option_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_option_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.loss_invert_signal;
+	return ret;
+}
+
+sw_error_t
+sfp_option_tx_disable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_option_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_option_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_disable;
+	return ret;
+}
+
+sw_error_t
+sfp_option_cool_transc_declar_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_option_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_option_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cool_transc_declar;
+	return ret;
+}
+
+sw_error_t
+sfp_option_tx_fault_signal_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_option_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_option_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_fault_signal;
+	return ret;
+}
+
+sw_error_t
+sfp_rate_ctrl_upper_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_rate_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_rate_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.upper;
+	return ret;
+}
+
+sw_error_t
+sfp_rate_ctrl_lower_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_rate_ctrl_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_rate_ctrl_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.lower;
+	return ret;
+}
+
+sw_error_t
+sfp_vendor_ext_date_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint8_t value[8])
+{
+	union sfp_vendor_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+	a_uint8_t i;
+
+	ret = sfp_vendor_ext_get(dev_id, index, &reg_val);
+
+	for (i = 0; i < 8; i++) {
+		value[i] = reg_val.val[i];
+	}
+
+	return ret;
+}
+
+sw_error_t
+sfp_vendor_ext_sn_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint8_t value[16])
+{
+	union sfp_vendor_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+	a_uint8_t i;
+
+	ret = sfp_vendor_ext_get(dev_id, index, &reg_val);
+
+	for (i = 0; i < 16; i++) {
+		value[i] = reg_val.val[i];
+	}
+
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_diag_mon_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.diag_mon_flag;
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_rx_los_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_los_op;
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_cmpl_feature_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.cmpl_feature;
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_tx_disable_ctrl_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_disable_ctrl_op;
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_alarm_warning_flag_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.alarm_warning_flag_op;
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_addr_mode_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.addr_mode;
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_unallocated_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.unallocated_op;
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_soft_rate_sel_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.soft_rate_sel_op;
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_external_cal_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.external_cal;
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_internal_cal_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.internal_cal;
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_re_pwr_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.re_pwr_type;
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_soft_rate_ctrl_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.soft_rate_ctrl_op;
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_app_sel_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.app_sel_op;
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_legacy_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.legacy_type;
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_tx_fault_op_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_fault_op;
+	return ret;
+}
+
+sw_error_t
+sfp_enhanced_unallocated_type_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_enhanced_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_enhanced_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.unallocated_type;
+	return ret;
+}
+
+sw_error_t
+sfp_ext_check_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_ext_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_ext_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.check_code;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_diag_threshold_u *value)
+{
+	return sfp_data_tbl_get(
+			dev_id, index, SFP_EEPROM_DIAG_A2,
+			SFP_DIAG_BASE_ADDR + SFP_DIAG_THRESHOLD_ADDRESS,
+			value->val, 40);
+}
+
+sw_error_t
+sfp_diag_cal_const_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_diag_cal_const_u *value)
+{
+	return sfp_data_tbl_get(
+			dev_id, index, SFP_EEPROM_DIAG_A2,
+			SFP_DIAG_BASE_ADDR + SFP_DIAG_CAL_CONST_ADDRESS,
+			value->val, 36);
+}
+
+sw_error_t
+sfp_diag_dmi_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_diag_dmi_u *value)
+{
+	return sfp_data_get(
+			dev_id, index, SFP_EEPROM_DIAG_A2,
+			SFP_DIAG_BASE_ADDR + SFP_DIAG_DMI_ADDRESS,
+			&value->val);
+}
+
+sw_error_t
+sfp_diag_realtime_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_diag_realtime_u *value)
+{
+	return sfp_data_tbl_get(
+			dev_id, index, SFP_EEPROM_DIAG_A2,
+			SFP_DIAG_BASE_ADDR + SFP_DIAG_REALTIME_ADDRESS,
+			value->val, 10);
+}
+
+sw_error_t
+sfp_diag_optional_ctrl_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_diag_optional_ctrl_status_u *value)
+{
+	return sfp_data_get(
+			dev_id, index, SFP_EEPROM_DIAG_A2,
+			SFP_DIAG_BASE_ADDR + SFP_DIAG_OPTIONAL_CTRL_STATUS_ADDRESS,
+			value->val);
+}
+
+sw_error_t
+sfp_diag_flag_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_diag_flag_u *value)
+{
+	return sfp_data_tbl_get(
+			dev_id, index, SFP_EEPROM_DIAG_A2,
+			SFP_DIAG_BASE_ADDR + SFP_DIAG_FLAG_ADDRESS,
+			value->val, 6);
+}
+
+sw_error_t
+sfp_diag_extended_ctrl_status_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		union sfp_diag_extended_ctrl_status_u *value)
+{
+	return sfp_data_tbl_get(
+			dev_id, index, SFP_EEPROM_DIAG_A2,
+			SFP_DIAG_BASE_ADDR + SFP_DIAG_EXTENDED_CTRL_STATUS_ADDRESS,
+			value->val, 2);
+}
+
+sw_error_t
+sfp_diag_threshold_rx_pwr_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pwr_low_alarm_0 << 8 | \
+		 reg_val.bf.rx_pwr_low_alarm_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_rx_pwr_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pwr_high_warning_0 << 8 | \
+		 reg_val.bf.rx_pwr_high_warning_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_temp_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.temp_low_alarm_0 << 8 | \
+		 reg_val.bf.temp_low_alarm_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_vol_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vol_high_alarm_0 << 8 | \
+		 reg_val.bf.vol_high_alarm_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_tx_pwr_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_pwr_high_alarm_0 << 8 | \
+		 reg_val.bf.tx_pwr_high_alarm_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_bias_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.bias_low_alarm_0 << 8 | \
+		 reg_val.bf.bias_low_alarm_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_bias_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.bias_high_alarm_0 << 8 | \
+		 reg_val.bf.bias_high_alarm_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_vol_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vol_low_alarm_0 << 8 | \
+		 reg_val.bf.vol_low_alarm_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_bias_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.bias_high_warning_0 << 8 | \
+		 reg_val.bf.bias_high_warning_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_temp_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.temp_high_warning_0 << 8 | \
+		 reg_val.bf.temp_high_warning_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_rx_pwr_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pwr_low_warning_0 << 8 | \
+		 reg_val.bf.rx_pwr_low_warning_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_vol_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vol_low_warning_0 << 8 | \
+		 reg_val.bf.vol_low_warning_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_tx_pwr_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_pwr_low_alarm_0 << 8 | \
+		 reg_val.bf.tx_pwr_low_alarm_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_bias_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.bias_low_warning_0 << 8 | \
+		 reg_val.bf.bias_low_warning_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_temp_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.temp_high_alarm_0 << 8 | \
+		 reg_val.bf.temp_high_alarm_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_tx_pwr_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_pwr_high_warning_0 << 8 | \
+		 reg_val.bf.tx_pwr_high_warning_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_vol_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vol_high_warning_0 << 8 | \
+		 reg_val.bf.vol_high_warning_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_temp_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.temp_low_warning_0 << 8 | \
+		 reg_val.bf.temp_low_warning_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_rx_pwr_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pwr_high_alarm_0 << 8 | \
+		 reg_val.bf.rx_pwr_high_alarm_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_threshold_tx_pwr_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_threshold_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_threshold_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_pwr_low_warning_0 << 8 | \
+		 reg_val.bf.tx_pwr_low_warning_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_cal_const_rx_pwr_1_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_cal_const_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_cal_const_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pwr_1_0 << 24 | \
+		 reg_val.bf.rx_pwr_1_1 << 16 | \
+		 reg_val.bf.rx_pwr_1_2 << 8 | \
+		 reg_val.bf.rx_pwr_1_3;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_cal_const_t_slope_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_cal_const_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_cal_const_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.t_slope_0 << 8 | \
+		 reg_val.bf.t_slope_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_cal_const_rx_pwr_3_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_cal_const_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_cal_const_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pwr_3_0 << 24 | \
+		 reg_val.bf.rx_pwr_3_1 << 16 | \
+		 reg_val.bf.rx_pwr_3_2 << 8 | \
+		 reg_val.bf.rx_pwr_3_3;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_cal_const_v_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_cal_const_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_cal_const_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.v_offset_0 << 8 | \
+		 reg_val.bf.v_offset_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_cal_const_rx_pwr_2_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_cal_const_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_cal_const_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pwr_2_0 << 24 | \
+		 reg_val.bf.rx_pwr_2_1 << 16 | \
+		 reg_val.bf.rx_pwr_2_2 << 8 | \
+		 reg_val.bf.rx_pwr_2_3;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_cal_const_tx_i_slope_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_cal_const_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_cal_const_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_i_slope_0 << 8 | \
+		 reg_val.bf.tx_i_slope_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_cal_const_tx_i_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_cal_const_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_cal_const_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_i_offset_0 << 8 | \
+		 reg_val.bf.tx_i_offset_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_cal_const_v_slope_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_cal_const_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_cal_const_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.v_slope_0 << 8 | \
+		 reg_val.bf.v_slope_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_cal_const_t_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_cal_const_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_cal_const_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.t_offset_0 << 8 | \
+		 reg_val.bf.t_offset_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_cal_const_tx_pwr_offset_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_cal_const_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_cal_const_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_pwr_offset_0 << 8 | \
+		 reg_val.bf.tx_pwr_offset_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_cal_const_tx_pwr_slope_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_cal_const_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_cal_const_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_pwr_slope_0 << 8 | \
+		 reg_val.bf.tx_pwr_slope_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_cal_const_rx_pwr_4_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_cal_const_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_cal_const_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pwr_4_0 << 24 | \
+		 reg_val.bf.rx_pwr_4_1 << 16 | \
+		 reg_val.bf.rx_pwr_4_2 << 8 | \
+		 reg_val.bf.rx_pwr_4_3;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_cal_const_rx_pwr_0_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_cal_const_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_cal_const_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pwr_0_0 << 24 | \
+		 reg_val.bf.rx_pwr_0_1 << 16 | \
+		 reg_val.bf.rx_pwr_0_2 << 8 | \
+		 reg_val.bf.rx_pwr_0_3;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_dmi_check_code_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_dmi_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_dmi_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.check_code;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_realtime_vcc_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_realtime_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_realtime_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vcc_1 << 8 | \
+		 reg_val.bf.vcc_0;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_realtime_tx_pwr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_realtime_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_realtime_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_pwr_1 << 8 | \
+		 reg_val.bf.tx_pwr_0;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_realtime_tx_bias_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_realtime_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_realtime_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_bias_1 << 8 | \
+		 reg_val.bf.tx_bias_0;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_realtime_rx_pwr_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_realtime_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_realtime_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pwr_1 << 8 | \
+		 reg_val.bf.rx_pwr_0;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_realtime_tmp_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_realtime_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_realtime_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tmp_1 << 8 | \
+		 reg_val.bf.tmp_0;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_optional_ctrl_status_rs_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_optional_ctrl_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_optional_ctrl_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rs;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_optional_ctrl_status_tx_fault_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_optional_ctrl_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_optional_ctrl_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_fault;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_optional_ctrl_status_rx_los_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_optional_ctrl_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_optional_ctrl_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_los;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_optional_ctrl_status_data_ready_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_optional_ctrl_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_optional_ctrl_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.data_ready;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_optional_ctrl_status_soft_rate_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_optional_ctrl_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_optional_ctrl_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.soft_rate_sel;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_optional_ctrl_status_soft_tx_disable_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_optional_ctrl_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_optional_ctrl_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.soft_tx_disable_sel;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_optional_ctrl_status_rate_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_optional_ctrl_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_optional_ctrl_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rate_sel;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_optional_ctrl_status_tx_disable_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_optional_ctrl_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_optional_ctrl_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_disable;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_rx_pwr_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pwr_low_alarm;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_rx_pwr_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pwr_high_warning;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_tx_bias_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_bias_high_alarm;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_tmp_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tmp_high_alarm;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_tmp_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tmp_low_alarm;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_tx_pwr_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_pwr_high_alarm;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_vcc_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vcc_low_warning;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_vcc_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vcc_high_warning;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_rx_pwr_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pwr_low_warning;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_unallocated_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.unallocated_1 << 8 | \
+		 reg_val.bf.unallocated_0;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_tx_bias_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_bias_high_warning;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_vcc_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vcc_low_alarm;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_tx_pwr_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_pwr_low_alarm;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_vcc_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.vcc_high_alarm;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_tmp_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tmp_low_warning;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_tx_bias_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_bias_low_warning;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_tx_bias_low_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_bias_low_alarm;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_tmp_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tmp_high_warning;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_tx_pwr_high_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_pwr_high_warning;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_rx_pwr_high_alarm_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.rx_pwr_high_alarm;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_flag_tx_pwr_low_warning_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_flag_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_flag_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.tx_pwr_low_warning;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_extended_ctrl_status_unallocated_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_extended_ctrl_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_extended_ctrl_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.unallocated_0 << 8
+		| reg_val.bf.unallocated_1;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_extended_ctrl_status_pwr_level_op_state_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_extended_ctrl_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_extended_ctrl_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pwr_level_op_state;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_extended_ctrl_status_soft_rs_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_extended_ctrl_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_extended_ctrl_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.soft_rs_sel;
+	return ret;
+}
+
+sw_error_t
+sfp_diag_extended_ctrl_status_pwr_level_sel_get(
+		a_uint32_t dev_id,
+		a_uint32_t index,
+		a_uint32_t *value)
+{
+	union sfp_diag_extended_ctrl_status_u reg_val;
+	sw_error_t ret = SW_OK;
+
+	ret = sfp_diag_extended_ctrl_status_get(dev_id, index, &reg_val);
+	*value = reg_val.bf.pwr_level_sel;
+	return ret;
+}
+
diff --git a/qca-ssdk/src/hsl/sfp/sfp_access.c b/qca-ssdk/src/hsl/sfp/sfp_access.c
new file mode 100755
index 0000000..4d2e6b5
--- /dev/null
+++ b/qca-ssdk/src/hsl/sfp/sfp_access.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+
+#include "sw.h"
+#include "ssdk_init.h"
+#include "ssdk_phy_i2c.h"
+
+sw_error_t
+sfp_data_tbl_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave,
+		a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count)
+{
+	sw_error_t rv;
+	rv = qca_i2c_data_get(dev_id, i2c_slave, data_addr, buf, count);
+	return rv;
+}
+
+sw_error_t
+sfp_data_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave,
+		a_uint32_t data_addr, a_uint8_t *buf)
+{
+	sw_error_t rv;
+	rv = qca_i2c_data_get(dev_id, i2c_slave, data_addr, buf, 1);
+	return rv;
+}
+
+sw_error_t
+sfp_data_tbl_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave,
+		a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count)
+{
+	sw_error_t rv;
+	rv = qca_i2c_data_set(dev_id, i2c_slave, data_addr, buf, count);
+	return rv;
+}
+
+sw_error_t
+sfp_data_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave,
+		a_uint32_t data_addr, a_uint8_t *buf)
+{
+	sw_error_t rv;
+	rv = qca_i2c_data_set(dev_id, i2c_slave, data_addr, buf, 1);
+	return rv;
+}
diff --git a/qca-ssdk/src/hsl/shiva/Makefile b/qca-ssdk/src/hsl/shiva/Makefile
new file mode 100755
index 0000000..20042ef
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/Makefile
@@ -0,0 +1,84 @@
+LOC_DIR=src/hsl/shiva
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=shiva_reg_access.c shiva_init.c
+
+ifeq (TRUE, $(IN_ACL))
+  SRC_LIST += shiva_acl.c
+endif
+
+ifeq (TRUE, $(IN_FDB))
+  SRC_LIST += shiva_fdb.c
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+  SRC_LIST += shiva_igmp.c
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+  SRC_LIST += shiva_leaky.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+  SRC_LIST += shiva_led.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+  SRC_LIST += shiva_mib.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+  SRC_LIST += shiva_mirror.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+  SRC_LIST += shiva_misc.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+  SRC_LIST += shiva_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+  SRC_LIST += shiva_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+  SRC_LIST += shiva_qos.c
+endif
+
+ifeq (TRUE, $(IN_RATE))
+  SRC_LIST += shiva_rate.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+  SRC_LIST += shiva_stp.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+  SRC_LIST += shiva_vlan.c
+endif
+
+ifeq (TRUE, $(IN_REDUCED_ACL))
+  SRC_LIST += shiva_reduced_acl.c
+endif
+
+ifeq (linux, $(OS))
+	ifeq (KSLIB, $(MODULE_TYPE))
+    ifneq (TRUE, $(KERNEL_MODE))
+      SRC_LIST=shiva_reg_access.c shiva_init.c
+	  endif
+	endif
+endif
+
+ifeq (, $(findstring SHIVA, $(SUPPORT_CHIP)))
+  SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/qca-ssdk/src/hsl/shiva/shiva_acl.c b/qca-ssdk/src/hsl/shiva/shiva_acl.c
new file mode 100755
index 0000000..837047f
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_acl.c
@@ -0,0 +1,3171 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_acl SHIVA_ACL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+#include "shiva_acl.h"
+#include "shiva_reg.h"
+
+//#define SHIVA_ACL_DEBUG
+//#define SHIVA_SW_ENTRY
+//#define SHIVA_ENTRY_DUMP
+
+typedef struct
+{
+    a_uint32_t list_id;
+    a_uint32_t list_pri;
+    a_uint32_t addr;
+    a_uint32_t size;
+    a_uint32_t status;
+    fal_pbmp_t bind_pts;
+} shiva_acl_list_t;
+
+typedef struct
+{
+    a_uint32_t slct[6];
+    a_uint32_t vlu[5];
+    a_uint32_t msk[5];
+    a_uint32_t typ;
+    a_uint32_t len;
+    a_uint32_t act[3];
+} shiva_acl_hw_rule_t;
+
+static shiva_acl_list_t *list_ent[SW_MAX_NR_DEV];
+static shiva_acl_hw_rule_t *hw_rule_ent;
+
+static a_uint32_t filter[SW_MAX_NR_DEV];
+static a_uint32_t filter_snap[SW_MAX_NR_DEV];
+
+#define SHIVA_MAX_LIST 32
+#define SHIVA_MAX_RULE 32
+
+#define ENT_FREE        0x1
+#define ENT_USED        0x2
+
+#define SHIVA_RULE_VLU_ADDR  0x58400
+#define SHIVA_RULE_MSK_ADDR  0x58c00
+#define SHIVA_RULE_LEN_ADDR  0x58818
+#define SHIVA_RULE_TYP_ADDR  0x5881c
+#define SHIVA_RULE_ACT_ADDR  0x58000
+#define SHIVA_RULE_SLCT_ADDR 0x58800
+
+#define SHIVA_MAC_FILTER       1
+#define SHIVA_IP4_FILTER       2
+#define SHIVA_IP6R1_FILTER     3
+#define SHIVA_IP6R2_FILTER     4
+#define SHIVA_IP6R3_FILTER     5
+#define SHIVA_UDF_FILTER       6
+
+#ifdef SHIVA_SW_ENTRY
+static char *flt_vlu_mem = NULL;
+static char *flt_msk_mem = NULL;
+static char *flt_typ_mem = NULL;
+static char *flt_len_mem = NULL;
+static char *act_mem = NULL;
+static char *slct_mem = NULL;
+#endif
+
+static a_bool_t _shiva_acl_zero_addr(const fal_mac_addr_t addr);
+
+static a_bool_t
+_shiva_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask,
+                      a_uint32_t chkvlu);
+
+static sw_error_t
+_shiva_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t * idx);
+
+static sw_error_t
+_shiva_acl_filter_map_get(const shiva_acl_hw_rule_t * rule,
+                          a_uint32_t flt_idx[], a_uint32_t * flt_nr);
+
+static sw_error_t
+_shiva_acl_rule_mac_parse(fal_acl_rule_t * sw,
+                          shiva_acl_hw_rule_t * hw, a_bool_t * b_care);
+
+static sw_error_t
+_shiva_acl_rule_ip4_parse(fal_acl_rule_t * sw,
+                          shiva_acl_hw_rule_t * hw, a_bool_t * b_care);
+
+static sw_error_t
+_shiva_acl_rule_ip6r1_parse(fal_acl_rule_t * sw,
+                            shiva_acl_hw_rule_t * hw, a_bool_t * b_care);
+
+static sw_error_t
+_shiva_acl_rule_ip6r2_parse(fal_acl_rule_t * sw,
+                            shiva_acl_hw_rule_t * hw, a_bool_t * b_care);
+
+static sw_error_t
+_shiva_acl_rule_ip6r3_parse(fal_acl_rule_t * sw,
+                            shiva_acl_hw_rule_t * hw, a_bool_t * b_care);
+
+static sw_error_t
+_shiva_acl_rule_udf_parse(fal_acl_rule_t * sw,
+                          shiva_acl_hw_rule_t * hw, a_bool_t * b_care);
+
+static sw_error_t
+_shiva_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw,
+                        shiva_acl_hw_rule_t * hw);
+
+static sw_error_t
+_shiva_acl_rule_mac_reparse(fal_acl_rule_t * sw,
+                            const shiva_acl_hw_rule_t * hw);
+
+static sw_error_t
+_shiva_acl_rule_ip4_reparse(fal_acl_rule_t * sw,
+                            const shiva_acl_hw_rule_t * hw);
+
+static sw_error_t
+_shiva_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw,
+                              const shiva_acl_hw_rule_t * hw);
+
+static sw_error_t
+_shiva_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw,
+                              const shiva_acl_hw_rule_t * hw);
+
+static sw_error_t
+_shiva_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw,
+                              const shiva_acl_hw_rule_t * hw);
+
+static sw_error_t
+_shiva_acl_rule_action_reparse(fal_acl_rule_t * sw,
+                               const shiva_acl_hw_rule_t * hw);
+
+static sw_error_t
+_shiva_acl_filter_alloc(a_uint32_t dev_id, a_uint32_t * idx);
+
+static void
+_shiva_acl_filter_free(a_uint32_t dev_id, a_uint32_t idx);
+
+static void
+_shiva_acl_filter_snap(a_uint32_t dev_id);
+
+static void
+_shiva_acl_filter_commit(a_uint32_t dev_id);
+
+static sw_error_t
+_shiva_acl_slct_update(shiva_acl_hw_rule_t * hw, a_uint32_t offset,
+                       a_uint32_t flt_idx);
+
+static sw_error_t
+_shiva_acl_filter_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule,
+                        a_uint32_t flt_idx);
+
+static sw_error_t
+_shiva_acl_action_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule,
+                        a_uint32_t act_idx);
+
+static sw_error_t
+_shiva_acl_slct_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule,
+                      a_uint32_t slct_idx);
+
+static sw_error_t
+_shiva_acl_filter_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+                       a_uint32_t flt_idx);
+
+static sw_error_t
+_shiva_acl_action_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+                       a_uint32_t act_idx);
+
+static sw_error_t
+_shiva_acl_slct_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+                     a_uint32_t slct_idx);
+
+static sw_error_t
+_shiva_acl_rule_set(a_uint32_t dev_id, a_uint32_t base_addr,
+                    const shiva_acl_hw_rule_t * hw_rule_ent,
+                    a_uint32_t rule_nr);
+
+static sw_error_t
+_shiva_acl_rule_get(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+                    a_uint32_t * ent_idx, a_uint32_t rule_idx);
+
+static sw_error_t
+_shiva_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+                         shiva_acl_hw_rule_t * hw, a_uint32_t * idx);
+
+static sw_error_t
+_shiva_acl_rule_hw_to_sw(fal_acl_rule_t * sw, const shiva_acl_hw_rule_t * hw,
+                         a_uint32_t ent_idx, a_uint32_t ent_nr);
+
+static sw_error_t
+_shiva_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_slct_idx,
+                     a_uint32_t dst_slct_idx, a_uint32_t size);
+
+static sw_error_t
+_shiva_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t rule_idx,
+                        a_uint32_t size);
+
+static sw_error_t
+_shiva_acl_rule_valid(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t size,
+                      a_uint32_t flag);
+
+static sw_error_t
+_shiva_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr,
+                       a_uint32_t new_addr, a_uint32_t list_id);
+
+static sw_error_t
+_shiva_acl_rule_bind(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t ports);
+
+#ifdef SHIVA_ACL_DEBUG
+static void
+_shiva_acl_list_dump(a_uint32_t dev_id)
+{
+    a_uint32_t i;
+
+    aos_printk("\ndev_id=%d  list control infomation", dev_id);
+    for (i = 0; i < SHIVA_MAX_LIST; i++)
+    {
+        if (ENT_USED == list_ent[dev_id][i].status)
+        {
+            aos_printk("\nlist_id=%d  list_pri=%d  addr=%d  size=%d  idx=%d ",
+                       list_ent[dev_id][i].list_id,
+                       list_ent[dev_id][i].list_pri,
+                       list_ent[dev_id][i].addr, list_ent[dev_id][i].size, i);
+        }
+    }
+    aos_printk("\n");
+}
+#else
+#define _shiva_acl_list_dump(dev_id)
+#endif
+
+static a_bool_t
+_shiva_acl_zero_addr(const fal_mac_addr_t addr)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 6; i++)
+    {
+        if (addr.uc[i])
+        {
+            return A_FALSE;
+        }
+    }
+    return A_TRUE;
+}
+
+static a_bool_t
+_shiva_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask,
+                      a_uint32_t chkvlu)
+{
+    if (FAL_ACL_FIELD_MASK == op)
+    {
+        if (0 == mask)
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_RANGE == op)
+    {
+        if ((0 == val) && (chkvlu == mask))
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_LE == op)
+    {
+        if (chkvlu == val)
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_GE == op)
+    {
+        if (0 == val)
+            return A_FALSE;
+    }
+    else if (FAL_ACL_FIELD_NE == op)
+    {
+        return A_TRUE;
+    }
+
+    return A_TRUE;
+}
+
+static sw_error_t
+_shiva_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t * idx)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < SHIVA_MAX_LIST; i++)
+    {
+        if ((ENT_USED == list_ent[dev_id][i].status)
+                && (list_id == list_ent[dev_id][i].list_id))
+        {
+            *idx = i;
+            return SW_OK;
+        }
+    }
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_shiva_acl_filter_map_get(const shiva_acl_hw_rule_t * rule,
+                          a_uint32_t flt_idx[], a_uint32_t * flt_nr)
+{
+    a_uint32_t flt_en, idx, i = 0;
+
+    SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR0_EN, flt_en, (rule->slct[0]));
+    if (flt_en)
+    {
+        SW_GET_FIELD_BY_REG(RUL_SLCT1, ADDR0, idx, (rule->slct[1]));
+        flt_idx[i] = idx;
+        i++;
+    }
+
+    SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR1_EN, flt_en, (rule->slct[0]));
+    if (flt_en)
+    {
+        SW_GET_FIELD_BY_REG(RUL_SLCT2, ADDR1, idx, (rule->slct[2]));
+        flt_idx[i] = idx;
+        i++;
+    }
+
+    SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR2_EN, flt_en, (rule->slct[0]));
+    if (flt_en)
+    {
+        SW_GET_FIELD_BY_REG(RUL_SLCT3, ADDR2, idx, (rule->slct[3]));
+        flt_idx[i] = idx;
+        i++;
+    }
+
+    SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR3_EN, flt_en, (rule->slct[0]));
+    if (flt_en)
+    {
+        SW_GET_FIELD_BY_REG(RUL_SLCT4, ADDR3, idx, (rule->slct[4]));
+        flt_idx[i] = idx;
+        i++;
+    }
+
+    *flt_nr = i;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_mac_parse(fal_acl_rule_t * sw,
+                          shiva_acl_hw_rule_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i, len = 14;
+
+    *b_care = A_FALSE;
+
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+    aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+    aos_mem_zero(&(hw->len), sizeof (hw->len));
+
+    SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_MAC_FILTER, hw->typ);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+    {
+        if (A_TRUE != _shiva_acl_zero_addr(sw->dest_mac_mask))
+        {
+            *b_care = A_TRUE;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+        }
+
+        SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2],
+                            hw->vlu[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3],
+                            hw->vlu[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4],
+                            hw->vlu[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5],
+                            hw->vlu[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0],
+                            hw->vlu[1]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1],
+                            hw->vlu[1]);
+
+        SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2],
+                            hw->msk[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3],
+                            hw->msk[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4],
+                            hw->msk[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5],
+                            hw->msk[0]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0],
+                            hw->msk[1]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1],
+                            hw->msk[1]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+    {
+        if (A_TRUE != _shiva_acl_zero_addr(sw->src_mac_mask))
+        {
+            *b_care = A_TRUE;
+        }
+
+        for (i = 0; i < 6; i++)
+        {
+            sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+        }
+
+        SW_SET_REG_BY_FIELD(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4],
+                            hw->vlu[1]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5],
+                            hw->vlu[1]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0],
+                            hw->vlu[2]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1],
+                            hw->vlu[2]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2],
+                            hw->vlu[2]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3],
+                            hw->vlu[2]);
+
+        SW_SET_REG_BY_FIELD(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4],
+                            hw->msk[1]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5],
+                            hw->msk[1]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0],
+                            hw->msk[2]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1],
+                            hw->msk[2]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2],
+                            hw->msk[2]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3],
+                            hw->msk[2]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+    {
+        if (0x0 != sw->ethtype_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ethtype_val &= sw->ethtype_mask;
+        SW_SET_REG_BY_FIELD(MAC_RUL_V3, ETHTYPV, sw->ethtype_val, hw->vlu[3]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask, hw->msk[3]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED))
+    {
+        if (0x0 != sw->tagged_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->tagged_val &= sw->tagged_mask;
+        SW_SET_REG_BY_FIELD(MAC_RUL_V4, TAGGEDV, sw->tagged_val, hw->vlu[4]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_V4, TAGGEDM, sw->tagged_mask, hw->vlu[4]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP))
+    {
+        if (0x0 != sw->up_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->up_val &= sw->up_mask;
+        SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANPRIV, sw->up_val, hw->vlu[3]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANPRIM, sw->up_mask, hw->msk[3]);
+    }
+
+    SW_SET_REG_BY_FIELD(MAC_RUL_V4, VIDMSK, 1, hw->vlu[4]);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->vid_op)
+                && (FAL_ACL_FIELD_RANGE != sw->vid_op)
+                && (FAL_ACL_FIELD_LE != sw->vid_op)
+                && (FAL_ACL_FIELD_GE != sw->vid_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_TRUE ==
+                _shiva_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask,
+                                      0xfff))
+        {
+            *b_care = A_TRUE;
+        }
+
+        SW_SET_REG_BY_FIELD(MAC_RUL_V4, VIDMSK, 0, hw->vlu[4]);
+        if (FAL_ACL_FIELD_MASK == sw->vid_op)
+        {
+            sw->vid_val &= sw->vid_mask;
+            SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]);
+            SW_SET_REG_BY_FIELD(MAC_RUL_V4, VIDMSK, 1, hw->vlu[4]);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->vid_op)
+        {
+            SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->vid_op)
+        {
+            SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, 0, hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_val, hw->msk[3]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, 0xfff, hw->msk[3]);
+        }
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI))
+    {
+        if (0x0 != sw->cfi_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->cfi_val &= sw->cfi_mask;
+        SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANCFIV, sw->cfi_val, hw->vlu[3]);
+        SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANCFIM, sw->cfi_mask, hw->msk[3]);
+    }
+
+    SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip4_parse(fal_acl_rule_t * sw,
+                          shiva_acl_hw_rule_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t len = 34;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+    aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+    aos_mem_zero(&(hw->len), sizeof (hw->len));
+
+    SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_IP4_FILTER, hw->typ);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+    {
+        if (0x0 != sw->ip_dscp_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_dscp_val &= sw->ip_dscp_mask;
+        SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val, hw->vlu[2]);
+        SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask, hw->msk[2]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+    {
+        if (0x0 != sw->ip_proto_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_proto_val &= sw->ip_proto_mask;
+        SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val, hw->vlu[2]);
+        SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask,
+                            hw->msk[2]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_SIP))
+    {
+        if (0x0 != sw->src_ip4_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        sw->src_ip4_val &= sw->src_ip4_mask;
+        hw->vlu[1] = sw->src_ip4_val;
+        hw->msk[1] = sw->src_ip4_mask;
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_DIP))
+    {
+        if (0x0 != sw->dest_ip4_mask)
+        {
+            *b_care = A_TRUE;
+        }
+        sw->dest_ip4_val &= sw->dest_ip4_mask;
+        hw->vlu[0] = sw->dest_ip4_val;
+        hw->msk[0] = sw->dest_ip4_mask;
+    }
+
+    SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 1, hw->msk[3]);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _shiva_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+                                      sw->src_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+            {
+                sw->src_l4port_op   = FAL_ACL_FIELD_RANGE;
+                sw->src_l4port_val  = 0;
+                sw->src_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+        len = 38;
+
+        SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 0, hw->msk[3]);
+        if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+        {
+            sw->src_l4port_val &= sw->src_l4port_mask;
+            SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val,
+                                hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask,
+                                hw->msk[3]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 1, hw->msk[3]);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val,
+                                hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask,
+                                hw->msk[3]);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, 0, hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_val,
+                                hw->msk[3]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val,
+                                hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, 0xffff, hw->msk[3]);
+        }
+    }
+
+    SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 1, hw->msk[3]);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _shiva_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+                                      sw->dest_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+            {
+                sw->dest_l4port_op   = FAL_ACL_FIELD_RANGE;
+                sw->dest_l4port_val  = 0;
+                sw->dest_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+        len = 38;
+
+        SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 0, hw->msk[3]);
+        if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+        {
+            sw->dest_l4port_val &= sw->dest_l4port_mask;
+            SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val,
+                                hw->vlu[2]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask,
+                                hw->msk[2]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 1, hw->msk[3]);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val,
+                                hw->vlu[2]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask,
+                                hw->msk[2]);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, 0, hw->vlu[2]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_val,
+                                hw->msk[2]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val,
+                                hw->vlu[2]);
+            SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, 0xffff, hw->msk[2]);
+        }
+    }
+
+    SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip6r1_parse(fal_acl_rule_t * sw,
+                            shiva_acl_hw_rule_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i, len = 54;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+    aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+    aos_mem_zero(&(hw->len), sizeof (hw->len));
+
+    SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_IP6R1_FILTER, hw->typ);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_DIP))
+    {
+        for (i = 0; i < 4; i++)
+        {
+            if (0x0 != sw->dest_ip6_mask.ul[i])
+            {
+                *b_care = A_TRUE;
+            }
+
+            sw->dest_ip6_val.ul[3 - i] &= sw->dest_ip6_mask.ul[3 - i];
+            hw->vlu[i] = sw->dest_ip6_val.ul[3 - i];
+            hw->msk[i] = sw->dest_ip6_mask.ul[3 - i];
+        }
+    }
+
+    SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip6r2_parse(fal_acl_rule_t * sw,
+                            shiva_acl_hw_rule_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i, len = 54;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+    aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+    aos_mem_zero(&(hw->len), sizeof (hw->len));
+
+    SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_IP6R2_FILTER, hw->typ);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_SIP))
+    {
+        for (i = 0; i < 4; i++)
+        {
+            if (0x0 != sw->src_ip6_mask.ul[i])
+            {
+                *b_care = A_TRUE;
+            }
+
+            sw->src_ip6_val.ul[3 - i] &= sw->src_ip6_mask.ul[3 - i];
+            hw->vlu[i] = sw->src_ip6_val.ul[3 - i];
+            hw->msk[i] = sw->src_ip6_mask.ul[3 - i];
+        }
+    }
+
+    SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip6r3_parse(fal_acl_rule_t * sw,
+                            shiva_acl_hw_rule_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t len = 54;
+
+    *b_care = A_FALSE;
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+    aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+    aos_mem_zero(&(hw->len), sizeof (hw->len));
+
+    SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_IP6R3_FILTER, hw->typ);
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL))
+    {
+        if (0x0 != sw->ip6_lable_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip6_lable_val &= sw->ip6_lable_mask;
+        SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val,
+                            hw->vlu[1]);
+        SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask,
+                            hw->msk[1]);
+
+        SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6LABEL2V, (sw->ip6_lable_val >> 16),
+                            hw->vlu[2]);
+        SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6LABEL2M, (sw->ip6_lable_mask >> 16),
+                            hw->msk[2]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+    {
+        if (0x0 != sw->ip_proto_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_proto_val &= sw->ip_proto_mask;
+        SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val,
+                            hw->vlu[0]);
+        SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask,
+                            hw->msk[0]);
+    }
+
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+    {
+        if (0x0 != sw->ip_dscp_mask)
+        {
+            *b_care = A_TRUE;
+        }
+
+        sw->ip_dscp_val &= sw->ip_dscp_mask;
+        SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val, hw->vlu[0]);
+        SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask,
+                            hw->msk[0]);
+    }
+
+    SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 1, hw->msk[3]);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _shiva_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+                                      sw->src_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+            {
+                sw->src_l4port_op   = FAL_ACL_FIELD_RANGE;
+                sw->src_l4port_val  = 0;
+                sw->src_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+        len = 58;
+
+        SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 0, hw->msk[3]);
+        if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+        {
+            sw->src_l4port_val &= sw->src_l4port_mask;
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val,
+                                hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask,
+                                hw->msk[3]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 1, hw->msk[3]);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val,
+                                hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask,
+                                hw->msk[3]);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V3, IP6SPORTV, 0, hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_val,
+                                hw->msk[3]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val,
+                                hw->vlu[3]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM, 0xffff, hw->msk[3]);
+        }
+    }
+
+    SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 1, hw->msk[3]);
+    if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+    {
+        if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+                && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+        {
+            return SW_NOT_SUPPORTED;
+        }
+
+        if (A_FALSE ==
+                _shiva_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+                                      sw->dest_l4port_mask, 0xffff))
+        {
+            if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+            {
+                sw->dest_l4port_op   = FAL_ACL_FIELD_RANGE;
+                sw->dest_l4port_val  = 0;
+                sw->dest_l4port_mask = 0xffff;
+            }
+        }
+        *b_care = A_TRUE;
+        len = 58;
+
+        SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 0, hw->msk[3]);
+        if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+        {
+            sw->dest_l4port_val &= sw->dest_l4port_mask;
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val,
+                                hw->vlu[2]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask,
+                                hw->msk[2]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 1, hw->msk[3]);
+        }
+        else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val,
+                                hw->vlu[2]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask,
+                                hw->msk[2]);
+        }
+        else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+        {
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6DPORTV, 0, hw->vlu[2]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_val,
+                                hw->msk[2]);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val,
+                                hw->vlu[2]);
+            SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6DPORTM, 0xffff, hw->msk[2]);
+        }
+    }
+
+    SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len);
+
+    return SW_OK;
+}
+
+#define SHIVA_MAX_UDF_OFFSET 127
+#define SHIVA_MAX_UDF_LENGTH 16
+
+static sw_error_t
+_shiva_acl_rule_udf_parse(fal_acl_rule_t * sw,
+                          shiva_acl_hw_rule_t * hw, a_bool_t * b_care)
+{
+    a_uint32_t i, len = 0;
+
+    if (FAL_ACL_UDF_TYPE_BUTT <= sw->udf_type)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (SHIVA_MAX_UDF_OFFSET < sw->udf_offset)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (sw->udf_offset % 2)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (SHIVA_MAX_UDF_LENGTH < sw->udf_len)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+    aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+    aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+    aos_mem_zero(&(hw->len), sizeof (hw->len));
+
+    *b_care = A_FALSE;
+
+    SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_UDF_FILTER, hw->typ);
+
+    if (!FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_UDF))
+    {
+        return SW_OK;
+    }
+
+    *b_care = A_TRUE;
+    if (FAL_ACL_UDF_TYPE_L2 == sw->udf_type)
+    {
+        SW_SET_REG_BY_FIELD(UDF_RUL_V4, LAYER_TYP, 0, hw->vlu[4]);
+        len = sw->udf_offset + sw->udf_len;
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(UDF_RUL_V4, LAYER_TYP, 1, hw->vlu[4]);
+        len = 14 + sw->udf_offset + sw->udf_len;
+    }
+    SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len);
+
+    SW_SET_REG_BY_FIELD(UDF_RUL_V4, LAYER_OFFSET, sw->udf_offset, hw->vlu[4]);
+
+    for (i = 0; i < sw->udf_len; i++)
+    {
+        hw->vlu[3 - i / 4] |= ((sw->udf_mask[i] & sw->udf_val[i]) << (24 - 8 * (i % 4)));
+        hw->msk[3 - i / 4] |= ((sw->udf_mask[i]) << (24 - 8 * i));
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw,
+                        shiva_acl_hw_rule_t * hw)
+{
+    aos_mem_zero(&(hw->act[0]), sizeof (hw->act));
+
+    if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+            && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN)))
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    /* FAL_ACL_ACTION_PERMIT need't process */
+
+    /* we should ignore any other action flags when DENY bit is settd. */
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_DENY))
+    {
+        SW_SET_REG_BY_FIELD(ACL_RSLT1, DES_PORT_EN, 1, hw->act[1]);
+        SW_SET_REG_BY_FIELD(ACL_RSLT1, PORT_MEM, 0, hw->act[1]);
+        return SW_OK;
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU))
+    {
+        SW_SET_REG_BY_FIELD(ACL_RSLT2, RDTCPU, 1, hw->act[2]);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU))
+    {
+        SW_SET_REG_BY_FIELD(ACL_RSLT2, CPYCPU, 1, hw->act[2]);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MIRROR))
+    {
+        SW_SET_REG_BY_FIELD(ACL_RSLT1, MIRR_EN, 1, hw->act[1]);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT))
+    {
+        SW_SET_REG_BY_FIELD(ACL_RSLT1, DES_PORT_EN, 1, hw->act[1]);
+        SW_SET_REG_BY_FIELD(ACL_RSLT1, PORT_MEM, sw->ports, hw->act[1]);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_UP))
+    {
+        SW_SET_REG_BY_FIELD(ACL_RSLT1, REMARK_DOT1P, 1, hw->act[1]);
+        SW_SET_REG_BY_FIELD(ACL_RSLT1, DOT1P, sw->up, hw->act[1]);
+    }
+
+    if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE))
+    {
+        SW_SET_REG_BY_FIELD(ACL_RSLT1, REMARK_PRI_QU, 1, hw->act[1]);
+        SW_SET_REG_BY_FIELD(ACL_RSLT1, PRI_QU, sw->queue, hw->act[1]);
+    }
+
+    if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+            || (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN)))
+    {
+
+        SW_SET_REG_BY_FIELD(ACL_RSLT1, CHG_VID_EN, 1, hw->act[1]);
+        SW_SET_REG_BY_FIELD(ACL_RSLT1, VID, sw->vid, hw->act[1]);
+        SW_SET_REG_BY_FIELD(ACL_RSLT1, STAG_CHG_EN, 1, hw->act[1]);
+        if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+        {
+            SW_SET_REG_BY_FIELD(ACL_RSLT1, STAG_CHG_EN, 0, hw->act[1]);
+
+            if (!FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT))
+            {
+                SW_SET_REG_BY_FIELD(ACL_RSLT1, VID_MEM_EN, 1, hw->act[1]);
+                SW_SET_REG_BY_FIELD(ACL_RSLT1, PORT_MEM, sw->ports, hw->act[1]);
+            }
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_mac_reparse(fal_acl_rule_t * sw,
+                            const shiva_acl_hw_rule_t * hw)
+{
+    a_uint32_t mask_en;
+
+    /* destnation mac address */
+    SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2],
+                        hw->vlu[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3],
+                        hw->vlu[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4],
+                        hw->vlu[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5],
+                        hw->vlu[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0],
+                        hw->vlu[1]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1],
+                        hw->vlu[1]);
+
+    SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2],
+                        hw->msk[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3],
+                        hw->msk[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4],
+                        hw->msk[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5],
+                        hw->msk[0]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0],
+                        hw->msk[1]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1],
+                        hw->msk[1]);
+    if (A_FALSE == _shiva_acl_zero_addr(sw->dest_mac_mask))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+    }
+
+    /* source mac address */
+    SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0],
+                        hw->vlu[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1],
+                        hw->vlu[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2],
+                        hw->vlu[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3],
+                        hw->vlu[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4],
+                        hw->vlu[1]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5],
+                        hw->vlu[1]);
+
+    SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0],
+                        hw->msk[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1],
+                        hw->msk[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2],
+                        hw->msk[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3],
+                        hw->msk[2]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4],
+                        hw->msk[1]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5],
+                        hw->msk[1]);
+    if (A_FALSE == _shiva_acl_zero_addr(sw->src_mac_mask))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+    }
+
+    /* ethernet type */
+    SW_GET_FIELD_BY_REG(MAC_RUL_V3, ETHTYPV, sw->ethtype_val, hw->vlu[3]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask, hw->msk[3]);
+    if (0x0 != sw->ethtype_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+    }
+
+    /* packet tagged */
+    SW_GET_FIELD_BY_REG(MAC_RUL_V4, TAGGEDV, sw->tagged_val, hw->vlu[4]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V4, TAGGEDM, sw->tagged_mask, hw->vlu[4]);
+    if (0x0 != sw->tagged_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED);
+    }
+
+    /* vlan priority */
+    SW_GET_FIELD_BY_REG(MAC_RUL_V3, VLANPRIV, sw->up_val, hw->vlu[3]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M3, VLANPRIM, sw->up_mask, hw->msk[3]);
+    if (0x0 != sw->up_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_UP);
+    }
+
+    /* vlanid */
+    SW_GET_FIELD_BY_REG(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_V4, VIDMSK, mask_en, hw->vlu[4]);
+    if (mask_en)
+    {
+        sw->vid_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->vid_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _shiva_acl_field_care(sw->vid_op, (a_uint32_t) sw->vid_val,
+                                  (a_uint32_t) sw->vid_mask, 0xfff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_VID);
+    }
+
+    /* vlan cfi */
+    SW_GET_FIELD_BY_REG(MAC_RUL_V3, VLANCFIV, sw->cfi_val, hw->vlu[3]);
+    SW_GET_FIELD_BY_REG(MAC_RUL_M3, VLANCFIM, sw->cfi_mask, hw->msk[3]);
+    if (0x0 != sw->cfi_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CFI);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip4_reparse(fal_acl_rule_t * sw,
+                            const shiva_acl_hw_rule_t * hw)
+{
+    a_uint32_t mask_en;
+
+    sw->dest_ip4_val = hw->vlu[0];
+    sw->dest_ip4_mask = hw->msk[0];
+    if (0x0 != sw->dest_ip4_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_DIP);
+    }
+
+    sw->src_ip4_val = hw->vlu[1];
+    sw->src_ip4_mask = hw->msk[1];
+    if (0x0 != sw->src_ip4_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_SIP);
+    }
+
+    SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val, hw->vlu[2]);
+    SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask, hw->msk[2]);
+    if (0x0 != sw->ip_proto_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+    }
+
+    SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val, hw->vlu[2]);
+    SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask, hw->msk[2]);
+    if (0x0 != sw->ip_dscp_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+    }
+
+    SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val, hw->vlu[2]);
+    SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask,
+                        hw->msk[2]);
+    SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4DPORTM_EN, mask_en, hw->msk[3]);
+    if (mask_en)
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _shiva_acl_field_care(sw->dest_l4port_op,
+                                  (a_uint32_t) sw->dest_l4port_val,
+                                  (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+    else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+
+    SW_GET_FIELD_BY_REG(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val, hw->vlu[3]);
+    SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask, hw->msk[3]);
+    SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4SPORTM_EN, mask_en, hw->msk[3]);
+    if (mask_en)
+    {
+        sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _shiva_acl_field_care(sw->src_l4port_op,
+                                  (a_uint32_t) sw->src_l4port_val,
+                                  (a_uint32_t) sw->src_l4port_mask, 0xffff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+    }
+    else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw,
+                              const shiva_acl_hw_rule_t * hw)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 4; i++)
+    {
+        sw->dest_ip6_val.ul[i] = hw->vlu[3 - i];
+        sw->dest_ip6_mask.ul[i] = hw->msk[3 - i];
+        if (0x0 != sw->dest_ip6_mask.ul[i])
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_DIP);
+        }
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw,
+                              const shiva_acl_hw_rule_t * hw)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 4; i++)
+    {
+        sw->src_ip6_val.ul[i] = hw->vlu[3 - i];
+        sw->src_ip6_mask.ul[i] = hw->msk[3 - i];
+        if (0x0 != sw->src_ip6_mask.ul[i])
+        {
+            FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_SIP);
+        }
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw,
+                              const shiva_acl_hw_rule_t * hw)
+{
+    a_uint32_t mask_en;
+    a_uint32_t tmp;
+
+    SW_GET_FIELD_BY_REG(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val, hw->vlu[0]);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask, hw->msk[0]);
+    if (0x0 != sw->ip_proto_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+    }
+
+    SW_GET_FIELD_BY_REG(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val, hw->vlu[0]);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask, hw->msk[0]);
+    if (0x0 != sw->ip_dscp_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+    }
+
+    SW_GET_FIELD_BY_REG(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val,
+                        hw->vlu[2]);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask,
+                        hw->msk[2]);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M3, IP6DPORTM_EN, mask_en, hw->msk[3]);
+    if (mask_en)
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _shiva_acl_field_care(sw->dest_l4port_op,
+                                  (a_uint32_t) sw->dest_l4port_val,
+                                  (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+    else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+    }
+
+    SW_GET_FIELD_BY_REG(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val, hw->vlu[3]);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask,
+                        hw->msk[3]);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M3, IP6SPORTM_EN, mask_en, hw->msk[3]);
+    if (mask_en)
+    {
+        sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+    }
+    else
+    {
+        sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+    }
+
+    if (A_TRUE ==
+            _shiva_acl_field_care(sw->src_l4port_op,
+                                  (a_uint32_t) sw->src_l4port_val,
+                                  (a_uint32_t) sw->src_l4port_mask, 0xffff))
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+    }
+    else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+    }
+
+    SW_GET_FIELD_BY_REG(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val, hw->vlu[1]);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask,
+                        hw->msk[1]);
+
+    SW_GET_FIELD_BY_REG(IP6_RUL3_V2, IP6LABEL2V, tmp, hw->vlu[2]);
+    sw->ip6_lable_val |= (tmp << 16);
+    SW_GET_FIELD_BY_REG(IP6_RUL3_M2, IP6LABEL2M, tmp, hw->msk[2]);
+    sw->ip6_lable_mask |= (tmp << 16);
+
+    if (0x0 != sw->ip6_lable_mask)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_udf_reparse(fal_acl_rule_t * sw,
+                            const shiva_acl_hw_rule_t * hw)
+{
+    a_uint32_t i, tmp;
+
+    FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_UDF);
+
+    SW_GET_FIELD_BY_REG(UDF_RUL_V4, LAYER_OFFSET, tmp, hw->vlu[4]);
+    sw->udf_offset = tmp;
+
+    SW_GET_FIELD_BY_REG(UDF_RUL_V4, LAYER_TYP, tmp, hw->vlu[4]);
+    if (tmp)
+    {
+        sw->udf_type = FAL_ACL_UDF_TYPE_L3;
+        sw->udf_len  = hw->len - sw->udf_offset - 14;
+    }
+    else
+    {
+        sw->udf_type = FAL_ACL_UDF_TYPE_L2;
+        sw->udf_len  = hw->len - sw->udf_offset;
+    }
+
+    if (SHIVA_MAX_UDF_LENGTH < sw->udf_len)
+    {
+        return SW_READ_ERROR;
+    }
+
+    for (i = 0; i < sw->udf_len; i++)
+    {
+        sw->udf_val[i]  = ((hw->vlu[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff;
+        sw->udf_mask[i] = ((hw->msk[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_action_reparse(fal_acl_rule_t * sw,
+                               const shiva_acl_hw_rule_t * hw)
+{
+    a_uint32_t data;
+
+    sw->match_cnt = hw->act[0];
+
+    sw->action_flg = 0;
+    SW_GET_FIELD_BY_REG(ACL_RSLT1, DES_PORT_EN, data, (hw->act[1]));
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(ACL_RSLT1, PORT_MEM, data, (hw->act[1]));
+        sw->ports = data;
+
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REDPT);
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_RSLT2, RDTCPU, data, (hw->act[2]));
+    if (1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_RDTCPU);
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_RSLT2, CPYCPU, data, (hw->act[2]));
+    if (1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_CPYCPU);
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_RSLT1, MIRR_EN, data, (hw->act[1]));
+    if (1 == data)
+    {
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MIRROR);
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_RSLT1, REMARK_DOT1P, data, (hw->act[1]));
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(ACL_RSLT1, DOT1P, data, (hw->act[1]));
+        sw->up = data & 0x7;
+
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_UP);
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_RSLT1, REMARK_PRI_QU, data, (hw->act[1]));
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(ACL_RSLT1, PRI_QU, data, (hw->act[1]));
+        sw->queue = data & 0x3;
+
+        FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE);
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_RSLT1, CHG_VID_EN, data, (hw->act[1]));
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(ACL_RSLT1, STAG_CHG_EN, data, (hw->act[1]));
+        if (1 == data)
+        {
+            FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN);
+        }
+        else
+        {
+            FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN);
+            SW_GET_FIELD_BY_REG(ACL_RSLT1, PORT_MEM, data, (hw->act[1]));
+            sw->ports = data;
+        }
+    }
+
+    SW_GET_FIELD_BY_REG(ACL_RSLT1, VID, data, (hw->act[1]));
+    sw->vid = data & 0xfff;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_filter_alloc(a_uint32_t dev_id, a_uint32_t * idx)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < SHIVA_MAX_RULE; i++)
+    {
+        if (0 == (filter_snap[dev_id] & (0x1UL << i)))
+        {
+            filter_snap[dev_id] |= (0x1UL << i);
+            *idx = i;
+            return SW_OK;
+        }
+    }
+    return SW_NO_RESOURCE;
+}
+
+static void
+_shiva_acl_filter_free(a_uint32_t dev_id, a_uint32_t idx)
+{
+    filter_snap[dev_id] &= (~(0x1UL << idx));
+}
+
+static void
+_shiva_acl_filter_snap(a_uint32_t dev_id)
+{
+    filter_snap[dev_id] = filter[dev_id];
+    return;
+}
+
+static void
+_shiva_acl_filter_commit(a_uint32_t dev_id)
+{
+    filter[dev_id] = filter_snap[dev_id];
+    return;
+}
+
+static sw_error_t
+_shiva_acl_slct_update(shiva_acl_hw_rule_t * hw, a_uint32_t offset,
+                       a_uint32_t flt_idx)
+{
+    switch (offset)
+    {
+        case 0:
+            SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR0_EN, 1, hw->slct[0]);
+            SW_SET_REG_BY_FIELD(RUL_SLCT1, ADDR0, flt_idx, hw->slct[1]);
+            break;
+
+        case 1:
+            SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR1_EN, 1, hw->slct[0]);
+            SW_SET_REG_BY_FIELD(RUL_SLCT2, ADDR1, flt_idx, hw->slct[2]);
+            break;
+
+        case 2:
+            SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR2_EN, 1, hw->slct[0]);
+            SW_SET_REG_BY_FIELD(RUL_SLCT3, ADDR2, flt_idx, hw->slct[3]);
+            break;
+
+        case 3:
+            SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR3_EN, 1, hw->slct[0]);
+            SW_SET_REG_BY_FIELD(RUL_SLCT4, ADDR3, flt_idx, hw->slct[4]);
+            break;
+
+        default:
+            return SW_FAIL;
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_filter_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule,
+                        a_uint32_t flt_idx)
+{
+#ifdef SHIVA_SW_ENTRY
+    char *memaddr;
+
+    memaddr = flt_vlu_mem + (flt_idx << 5);
+    aos_mem_copy(memaddr, (char *) &(rule->vlu[0]), sizeof(rule->vlu));
+
+    memaddr = flt_msk_mem + (flt_idx << 5);
+    aos_mem_copy(memaddr, (char *) &(rule->msk[0]), sizeof(rule->vlu));
+
+    memaddr = flt_typ_mem + (flt_idx << 5);
+    aos_mem_copy(memaddr, (char *) &(rule->typ), sizeof(rule->typ));
+
+    memaddr = flt_len_mem + (flt_idx << 5);
+    aos_mem_copy(memaddr, (char *) &(rule->len), sizeof(rule->len));
+
+#else
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    /* set filter value */
+    base = SHIVA_RULE_VLU_ADDR + (flt_idx << 5);
+    for (i = 0; i < (sizeof(rule->vlu) / sizeof(a_uint32_t)); i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(rule->vlu[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* set filter mask */
+    base = SHIVA_RULE_MSK_ADDR + (flt_idx << 5);
+    for (i = 0; i < (sizeof(rule->msk) / sizeof(a_uint32_t)); i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(rule->msk[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* set filter type */
+    addr = SHIVA_RULE_TYP_ADDR + (flt_idx << 5);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(rule->typ)), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* set filter length */
+    addr = SHIVA_RULE_LEN_ADDR + (flt_idx << 5);
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(rule->len)), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef SHIVA_ENTRY_DUMP
+    a_uint32_t j;
+    aos_printk("\n_shiva_acl_filter_write flt_idx = %d type = %d len = %d\n",
+               flt_idx, rule->typ, rule->len);
+    for (j = 0; j < (sizeof(rule->vlu) / sizeof(a_uint32_t)); j++)
+    {
+        aos_printk("%08x  ", rule->vlu[j]);
+    }
+    aos_printk("\n");
+    for (j = 0; j < (sizeof(rule->msk) / sizeof(a_uint32_t)); j++)
+    {
+        aos_printk("%08x  ", rule->msk[j]);
+    }
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_action_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule,
+                        a_uint32_t act_idx)
+{
+#ifdef SHIVA_SW_ENTRY
+    char *memaddr;
+
+    memaddr = act_mem + (act_idx << 5);
+    aos_mem_copy(memaddr, (char *) &(rule->act[0]), sizeof(rule->act));
+
+#else
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    /* set rule action */
+    base = SHIVA_RULE_ACT_ADDR + (act_idx << 5);
+    for (i = 0; i < (sizeof(rule->act) / sizeof(a_uint32_t)); i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(rule->act[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+#endif
+
+#ifdef SHIVA_ENTRY_DUMP
+    a_uint32_t j;
+    aos_printk("\n_shiva_acl_action_write act_idx = %d\n", act_idx);
+    for (j = 0; j < (sizeof(rule->act) / sizeof(a_uint32_t)); j++)
+    {
+        aos_printk("%08x  ", rule->act[j]);
+    }
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_slct_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule,
+                      a_uint32_t slct_idx)
+{
+#ifdef SHIVA_SW_ENTRY
+    char *memaddr;
+
+    memaddr = slct_mem + (slct_idx << 5);
+    aos_mem_copy(memaddr, (char *) &(rule->slct[0]), sizeof(rule->slct));
+
+#else
+    sw_error_t rv;
+    a_uint32_t base, addr;
+    a_uint32_t i;
+
+    base = SHIVA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+    /* set filter address and source ports bitmap*/
+    for (i = 1; i < (sizeof(rule->slct) / sizeof(a_uint32_t)); i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(rule->slct[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* set filter enable */
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(rule->slct[0])),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef SHIVA_ENTRY_DUMP
+    a_uint32_t j;
+    aos_printk("\n_shiva_acl_slct_write slct_idx = %d\n", slct_idx);
+    for (j = 0; j < (sizeof(rule->slct) / sizeof(a_uint32_t)); j++)
+    {
+        aos_printk("%08x  ", rule->slct[j]);
+    }
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_filter_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+                       a_uint32_t flt_idx)
+{
+#ifdef SHIVA_SW_ENTRY
+    char *memaddr;
+
+    memaddr = flt_vlu_mem + (flt_idx << 5);
+    aos_mem_copy((char *) &(rule->vlu[0]), memaddr, 20);
+
+    memaddr = flt_msk_mem + (flt_idx << 5);
+    aos_mem_copy((char *) &(rule->msk[0]), memaddr, 20);
+
+    memaddr = flt_typ_mem + (flt_idx << 5);
+    aos_mem_copy((char *) &(rule->typ), memaddr, 4);
+
+    memaddr = flt_len_mem + (flt_idx << 5);
+    aos_mem_copy((char *) &(rule->len), memaddr, 4);
+
+#else
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    /* get filter value */
+    base = SHIVA_RULE_VLU_ADDR + (flt_idx << 5);
+    for (i = 0; i < (sizeof(rule->vlu) / sizeof(a_uint32_t)); i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(rule->vlu[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* get filter mask */
+    base = SHIVA_RULE_MSK_ADDR + (flt_idx << 5);
+    for (i = 0; i < (sizeof(rule->msk) / sizeof(a_uint32_t)); i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(rule->msk[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* get filter type */
+    addr = SHIVA_RULE_TYP_ADDR + (flt_idx << 5);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(rule->typ)), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* get filter length */
+    addr = SHIVA_RULE_LEN_ADDR + (flt_idx << 5);
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(rule->len)), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef SHIVA_ENTRY_DUMP
+    a_uint32_t j;
+    aos_printk("\n_shiva_acl_filter_read flt_idx = %d type = %d len = %d \n",
+               flt_idx, rule->typ, rule->len);
+    for (j = 0; j < (sizeof(rule->vlu) / sizeof(a_uint32_t)); j++)
+    {
+        aos_printk("%08x  ", rule->vlu[j]);
+    }
+    aos_printk("\n");
+    for (j = 0; j < (sizeof(rule->msk) / sizeof(a_uint32_t)); j++)
+    {
+        aos_printk("%08x  ", rule->msk[j]);
+    }
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_action_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+                       a_uint32_t act_idx)
+{
+#ifdef SHIVA_SW_ENTRY
+    char *memaddr;
+
+    memaddr = act_mem + (act_idx << 5);
+    aos_mem_copy((char *) &(rule->act[0]), memaddr, sizeof(rule->act));
+
+#else
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    /* get rule action */
+    base = SHIVA_RULE_ACT_ADDR + (act_idx << 5);
+    for (i = 0; i < (sizeof(rule->act) / sizeof(a_uint32_t)); i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(rule->act[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+#endif
+
+#ifdef SHIVA_ENTRY_DUMP
+    a_uint32_t j;
+    aos_printk("\n_shiva_acl_action_read act_idx = %d    ", act_idx);
+    for (j = 0; j < (sizeof(rule->act) / sizeof(a_uint32_t)); j++)
+    {
+        aos_printk("%08x  ", rule->act[j]);
+    }
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_slct_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+                     a_uint32_t slct_idx)
+{
+#ifdef SHIVA_SW_ENTRY
+    char *memaddr;
+
+    memaddr = slct_mem + (slct_idx << 5);
+    aos_mem_copy((char *) &(rule->slct[0]), memaddr, sizeof(rule->slct));
+
+#else
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    base = SHIVA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+    /* get filter address and enable and source ports bitmap */
+    for (i = 0; i < (sizeof(rule->slct) / sizeof(a_uint32_t)); i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(rule->slct[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+#endif
+
+#ifdef SHIVA_ENTRY_DUMP
+    a_uint32_t j;
+    aos_printk("\n_shiva_acl_slct_read slct_idx = %d\n", slct_idx);
+    for (j = 0; j < (sizeof(rule->slct) / sizeof(a_uint32_t)); j++)
+    {
+        aos_printk("%08x  ", rule->slct[j]);
+    }
+#endif
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_set(a_uint32_t dev_id, a_uint32_t base_addr,
+                    const shiva_acl_hw_rule_t * rule, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+    a_uint32_t ent_idx, tmp_ent_idx;
+    a_uint32_t i, flt_nr, flt_idx[4] = {0};
+    a_uint32_t act_idx, slct_idx;
+
+    act_idx = base_addr;
+    slct_idx = base_addr;
+    ent_idx = 0;
+    for (i = 0; i < rule_nr; i++)
+    {
+        tmp_ent_idx = ent_idx;
+
+        rv = _shiva_acl_filter_map_get(&rule[ent_idx], flt_idx, &flt_nr);
+        SW_RTN_ON_ERROR(rv);
+
+        if (!flt_nr)
+        {
+            return SW_FAIL;
+        }
+
+        for (i = 0; i < flt_nr; i++)
+        {
+            rv = _shiva_acl_filter_write(dev_id, &(rule[ent_idx]), flt_idx[i]);
+            ent_idx++;
+        }
+
+        rv = _shiva_acl_action_write(dev_id, &(rule[tmp_ent_idx]), act_idx);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _shiva_acl_slct_write(dev_id, &(rule[tmp_ent_idx]), slct_idx);
+        SW_RTN_ON_ERROR(rv);
+
+        act_idx++;
+        slct_idx++;
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_get(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+                    a_uint32_t * ent_idx, a_uint32_t rule_idx)
+{
+    sw_error_t rv;
+    a_uint32_t i = 0, tmp_idx = 0, flt_nr = 0, flt_idx[4] = {0};
+
+    tmp_idx = *ent_idx;
+
+    rv = _shiva_acl_slct_read(dev_id, &rule[tmp_idx], rule_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _shiva_acl_action_read(dev_id, &rule[tmp_idx], rule_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _shiva_acl_filter_map_get(&rule[tmp_idx], flt_idx, &flt_nr);
+    SW_RTN_ON_ERROR(rv);
+
+    for (i = 0; i < flt_nr; i++)
+    {
+        rv = _shiva_acl_filter_read(dev_id, &rule[tmp_idx], flt_idx[i]);
+        SW_RTN_ON_ERROR(rv);
+
+        tmp_idx++;
+    }
+
+    *ent_idx = tmp_idx;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+                         shiva_acl_hw_rule_t * hw, a_uint32_t * idx)
+{
+    sw_error_t rv;
+    a_bool_t b_care;
+    a_bool_t b_valid = A_FALSE;
+    a_uint32_t tmp_idx;
+
+    tmp_idx = *idx;
+    if (FAL_ACL_RULE_MAC == sw->rule_type)
+    {
+        rv = _shiva_acl_rule_udf_parse(sw, &hw[tmp_idx], &b_care);
+        SW_RTN_ON_ERROR(rv);
+        if (A_TRUE == b_care)
+        {
+            tmp_idx++;
+        }
+
+        rv = _shiva_acl_rule_mac_parse(sw, &hw[tmp_idx], &b_care);
+        SW_RTN_ON_ERROR(rv);
+        tmp_idx++;
+    }
+    else if (FAL_ACL_RULE_IP4 == sw->rule_type)
+    {
+        rv = _shiva_acl_rule_udf_parse(sw, &hw[tmp_idx], &b_care);
+        SW_RTN_ON_ERROR(rv);
+        if (A_TRUE == b_care)
+        {
+            tmp_idx++;
+        }
+
+        rv = _shiva_acl_rule_mac_parse(sw, &hw[tmp_idx], &b_care);
+        SW_RTN_ON_ERROR(rv);
+        if (A_TRUE == b_care)
+        {
+            tmp_idx++;
+        }
+
+        rv = _shiva_acl_rule_ip4_parse(sw, &hw[tmp_idx], &b_care);
+        SW_RTN_ON_ERROR(rv);
+        tmp_idx++;
+    }
+    else if (FAL_ACL_RULE_IP6 == sw->rule_type)
+    {
+        rv = _shiva_acl_rule_udf_parse(sw, &hw[tmp_idx], &b_care);
+        SW_RTN_ON_ERROR(rv);
+        if (A_TRUE == b_care)
+        {
+            tmp_idx++;
+        }
+
+        rv = _shiva_acl_rule_mac_parse(sw, &hw[tmp_idx], &b_care);
+        SW_RTN_ON_ERROR(rv);
+        if (A_TRUE == b_care)
+        {
+            tmp_idx++;
+        }
+
+        rv = _shiva_acl_rule_ip6r1_parse(sw, &hw[tmp_idx], &b_care);
+        SW_RTN_ON_ERROR(rv);
+        if (A_TRUE == b_care)
+        {
+            tmp_idx++;
+            b_valid = A_TRUE;
+        }
+
+        rv = _shiva_acl_rule_ip6r2_parse(sw, &hw[tmp_idx], &b_care);
+        SW_RTN_ON_ERROR(rv);
+        if (A_TRUE == b_care)
+        {
+            tmp_idx++;
+            b_valid = A_TRUE;
+        }
+
+        rv = _shiva_acl_rule_ip6r3_parse(sw, &hw[tmp_idx], &b_care);
+        SW_RTN_ON_ERROR(rv);
+        if ((A_TRUE == b_care) || (A_FALSE == b_valid))
+        {
+            tmp_idx++;
+        }
+        else
+        {
+            hw[tmp_idx - 1].len = hw[tmp_idx].len;
+        }
+    }
+    else if (FAL_ACL_RULE_UDF == sw->rule_type)
+    {
+        FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_UDF);
+        rv = _shiva_acl_rule_udf_parse(sw, &hw[tmp_idx], &b_care);
+        SW_RTN_ON_ERROR(rv);
+        tmp_idx++;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    rv = _shiva_acl_action_parse(dev_id, sw, &(hw_rule_ent[*idx]));
+    SW_RTN_ON_ERROR(rv);
+
+    *idx = tmp_idx;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_hw_to_sw(fal_acl_rule_t * sw, const shiva_acl_hw_rule_t * hw,
+                         a_uint32_t ent_idx, a_uint32_t ent_nr)
+{
+    sw_error_t rv;
+    a_uint32_t i, flt_typ;
+    a_bool_t b_mac = A_FALSE, b_ip4 = A_FALSE, b_ip6 = A_FALSE;
+
+    rv = _shiva_acl_rule_action_reparse(sw, &hw[ent_idx]);
+    SW_RTN_ON_ERROR(rv);
+
+    sw->rule_type = FAL_ACL_RULE_UDF;
+    for (i = 0; i < ent_nr; i++)
+    {
+        SW_GET_FIELD_BY_REG(RUL_SLCT7, RULE_TYP, flt_typ, hw[ent_idx + i].typ);
+
+        if (SHIVA_UDF_FILTER == flt_typ)
+        {
+            rv = _shiva_acl_rule_udf_reparse(sw, &hw[ent_idx + i]);
+            SW_RTN_ON_ERROR(rv);
+        }
+        else if (SHIVA_MAC_FILTER == flt_typ)
+        {
+            rv = _shiva_acl_rule_mac_reparse(sw, &hw[ent_idx + i]);
+            SW_RTN_ON_ERROR(rv);
+            b_mac = A_TRUE;
+        }
+        else if (SHIVA_IP4_FILTER == flt_typ)
+        {
+            rv = _shiva_acl_rule_ip4_reparse(sw, &hw[ent_idx + i]);
+            SW_RTN_ON_ERROR(rv);
+            b_ip4 = A_TRUE;
+        }
+        else if (SHIVA_IP6R1_FILTER == flt_typ)
+        {
+            rv = _shiva_acl_rule_ip6r1_reparse(sw, &hw[ent_idx + i]);
+            SW_RTN_ON_ERROR(rv);
+            b_ip6 = A_TRUE;
+        }
+        else if (SHIVA_IP6R2_FILTER == flt_typ)
+        {
+            rv = _shiva_acl_rule_ip6r2_reparse(sw, &hw[ent_idx + i]);
+            SW_RTN_ON_ERROR(rv);
+            b_ip6 = A_TRUE;
+        }
+        else if (SHIVA_IP6R3_FILTER == flt_typ)
+        {
+            rv = _shiva_acl_rule_ip6r3_reparse(sw, &hw[ent_idx + i]);
+            SW_RTN_ON_ERROR(rv);
+            b_ip6 = A_TRUE;
+        }
+        else
+        {
+            return SW_FAIL;
+        }
+    }
+
+    if (A_TRUE == b_mac)
+    {
+        sw->rule_type = FAL_ACL_RULE_MAC;
+    }
+
+    if (A_TRUE == b_ip4)
+    {
+        sw->rule_type = FAL_ACL_RULE_IP4;
+    }
+
+    if (A_TRUE == b_ip6)
+    {
+        sw->rule_type = FAL_ACL_RULE_IP6;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_slct_idx,
+                     a_uint32_t dst_slct_idx, a_uint32_t size)
+{
+    sw_error_t rv;
+    a_uint32_t i;
+    a_int32_t step, src_idx, dst_idx;
+    shiva_acl_hw_rule_t rule;
+
+    if (dst_slct_idx <= src_slct_idx)
+    {
+        src_idx = src_slct_idx & 0x7fffffff;
+        dst_idx = dst_slct_idx & 0x7fffffff;
+        step = 1;
+    }
+    else
+    {
+        src_idx = (src_slct_idx + size - 1) & 0x7fffffff;
+        dst_idx = (dst_slct_idx + size - 1) & 0x7fffffff;
+        step = -1;
+    }
+
+    aos_mem_zero(&rule, sizeof (shiva_acl_hw_rule_t));
+    for (i = 0; i < size; i++)
+    {
+        rv = _shiva_acl_rule_invalid(dev_id, (a_uint32_t) dst_idx, 1);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _shiva_acl_action_read(dev_id, &rule, (a_uint32_t) src_idx);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _shiva_acl_action_write(dev_id, &rule, (a_uint32_t) dst_idx);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _shiva_acl_slct_read(dev_id, &rule, (a_uint32_t) src_idx);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _shiva_acl_slct_write(dev_id, &rule, (a_uint32_t) dst_idx);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _shiva_acl_rule_invalid(dev_id, (a_uint32_t) src_idx, 1);
+        SW_RTN_ON_ERROR(rv);
+
+        src_idx += step;
+        dst_idx += step;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t rule_idx,
+                        a_uint32_t size)
+{
+    sw_error_t rv;
+    a_uint32_t base, flag, i;
+
+    flag = 0;
+    for (i = 0; i < size; i++)
+    {
+        base = SHIVA_RULE_SLCT_ADDR + ((rule_idx + i) << 5);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&flag), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_valid(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t size,
+                      a_uint32_t flag)
+{
+    sw_error_t rv;
+    a_uint32_t base, i;
+
+    for (i = 0; i < size; i++)
+    {
+        base = SHIVA_RULE_SLCT_ADDR + ((rule_idx + i) << 5);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&flag), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr,
+                       a_uint32_t new_addr, a_uint32_t list_id)
+{
+    sw_error_t rv;
+    a_uint32_t idx;
+
+    rv = _shiva_acl_list_loc(dev_id, list_id, &idx);
+    SW_RTN_ON_ERROR(rv);
+
+    if (old_addr != list_ent[dev_id][idx].addr)
+    {
+        return SW_FAIL;
+    }
+
+    list_ent[dev_id][idx].addr = new_addr;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_bind(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t ports)
+{
+    sw_error_t rv;
+    shiva_acl_hw_rule_t rule;
+
+    aos_mem_zero(&rule, sizeof (shiva_acl_hw_rule_t));
+
+    rv = _shiva_acl_slct_read(dev_id, &rule, rule_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _shiva_acl_rule_invalid(dev_id, rule_idx, 1);
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(RUL_SLCT5, SRC_PT, ports, rule.slct[5]);
+
+    rv = _shiva_acl_slct_write(dev_id, &rule, rule_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _shiva_acl_rule_valid(dev_id, rule_idx, 1, rule.slct[0]);
+    return rv;
+}
+
+static sw_error_t
+_shiva_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+                      a_uint32_t list_pri)
+{
+    a_uint32_t i, loc = SHIVA_MAX_LIST;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    for (i = 0; i < SHIVA_MAX_LIST; i++)
+    {
+        if ((ENT_USED == list_ent[dev_id][i].status)
+                && (list_id == list_ent[dev_id][i].list_id))
+        {
+            return SW_ALREADY_EXIST;
+        }
+
+        if (ENT_FREE == list_ent[dev_id][i].status)
+        {
+            loc = i;
+        }
+    }
+
+    if (SHIVA_MAX_LIST == loc)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    aos_mem_zero(&(list_ent[dev_id][loc]), sizeof (shiva_acl_list_t));
+    list_ent[dev_id][loc].list_id = list_id;
+    list_ent[dev_id][loc].list_pri = list_pri;
+    list_ent[dev_id][loc].status = ENT_USED;
+    _shiva_acl_list_dump(dev_id);
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    a_uint32_t list_idx;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    for (list_idx = 0; list_idx < SHIVA_MAX_LIST; list_idx++)
+    {
+        if ((ENT_USED == list_ent[dev_id][list_idx].status)
+                && (list_id == list_ent[dev_id][list_idx].list_id))
+        {
+            break;
+        }
+    }
+
+    if (list_idx >= SHIVA_MAX_LIST)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    if (0 != list_ent[dev_id][list_idx].bind_pts)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (0 != list_ent[dev_id][list_idx].size)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    aos_mem_zero(&(list_ent[dev_id][list_idx]), sizeof (shiva_acl_list_t));
+    list_ent[dev_id][list_idx].status = ENT_FREE;
+    _shiva_acl_list_dump(dev_id);
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+                    a_uint32_t rule_id, a_uint32_t rule_nr,
+                    fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+    a_uint32_t hsl_f_rsc, list_new_size, list_addr;
+    a_uint32_t list_pri, list_idx, load_addr, bind_pts;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((0 == rule_nr) || (NULL == rule))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = hsl_acl_free_rsc_get(dev_id, &hsl_f_rsc);
+    SW_RTN_ON_ERROR(rv);
+    if (hsl_f_rsc < rule_nr)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    rv = _shiva_acl_list_loc(dev_id, list_id, &list_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    if (rule_id != list_ent[dev_id][list_idx].size)
+    {
+        return SW_ALREADY_EXIST;
+    }
+    bind_pts = list_ent[dev_id][list_idx].bind_pts;
+
+    _shiva_acl_filter_snap(dev_id);
+
+    /* parse rule entry and alloc rule resource */
+    {
+        a_uint32_t i, j;
+        a_uint32_t ent_idx, tmp_ent_idx, flt_idx;
+
+        aos_mem_zero(hw_rule_ent,
+                     SHIVA_MAX_RULE * sizeof (shiva_acl_hw_rule_t));
+
+        ent_idx = 0;
+        for (i = 0; i < rule_nr; i++)
+        {
+            tmp_ent_idx = ent_idx;
+            rv = _shiva_acl_rule_sw_to_hw(dev_id, &rule[i],
+                                          &hw_rule_ent[ent_idx], &ent_idx);
+            SW_RTN_ON_ERROR(rv);
+
+            if (4 < (ent_idx - tmp_ent_idx))
+            {
+                return SW_NOT_SUPPORTED;
+            }
+
+            for (j = tmp_ent_idx; j < ent_idx; j++)
+            {
+                rv = _shiva_acl_filter_alloc(dev_id, &flt_idx);
+                SW_RTN_ON_ERROR(rv);
+
+                rv = _shiva_acl_slct_update(&hw_rule_ent[tmp_ent_idx],
+                                            j - tmp_ent_idx, flt_idx);
+                SW_RTN_ON_ERROR(rv);
+            }
+            SW_SET_REG_BY_FIELD(RUL_SLCT5, SRC_PT, bind_pts,
+                                hw_rule_ent[tmp_ent_idx].slct[5]);
+        }
+    }
+
+    /* alloc hardware select entry resource */
+    if (0 == list_ent[dev_id][list_idx].size)
+    {
+        list_new_size = rule_nr;
+        list_pri = list_ent[dev_id][list_idx].list_pri;
+
+        rv = hsl_acl_blk_alloc(dev_id, list_pri, list_new_size, list_id,
+                               &list_addr);
+        SW_RTN_ON_ERROR(rv);
+
+        load_addr = list_addr;
+    }
+    else
+    {
+        list_new_size = list_ent[dev_id][list_idx].size + rule_nr;
+        list_addr = list_ent[dev_id][list_idx].addr;
+
+        rv = hsl_acl_blk_resize(dev_id, list_addr, list_new_size);
+        SW_RTN_ON_ERROR(rv);
+
+        /* must be careful resize opration maybe change list base address */
+        list_addr = list_ent[dev_id][list_idx].addr;
+        load_addr = list_ent[dev_id][list_idx].size + list_addr;
+    }
+
+    /* load acl rule to hardware */
+    rv = _shiva_acl_rule_set(dev_id, load_addr, hw_rule_ent, rule_nr);
+    if (SW_OK != rv)
+    {
+        (void) hsl_acl_blk_resize(dev_id, list_addr,
+                                  list_ent[dev_id][list_idx].size);
+        return rv;
+    }
+
+    /* update software list control information */
+    list_ent[dev_id][list_idx].size = list_new_size;
+    list_ent[dev_id][list_idx].addr = list_addr;
+
+    /* update hardware acl rule resource information */
+    _shiva_acl_filter_commit(dev_id);
+    _shiva_acl_list_dump(dev_id);
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+                       a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+    a_uint32_t flt_idx[4] = {0};
+    a_uint32_t i, j, flt_nr;
+    a_uint32_t list_idx = 0, addr, size, rule_idx, cnt;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _shiva_acl_list_loc(dev_id, list_id, &list_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == rule_nr)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((rule_id + rule_nr) > list_ent[dev_id][list_idx].size)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    _shiva_acl_filter_snap(dev_id);
+
+    /* free hardware filter resource */
+    addr = list_ent[dev_id][list_idx].addr + rule_id;
+    for (i = 0; i < rule_nr; i++)
+    {
+        rv = _shiva_acl_slct_read(dev_id, &hw_rule_ent[0], i + addr);
+        SW_RTN_ON_ERROR(rv);
+
+        rv = _shiva_acl_filter_map_get(&hw_rule_ent[0], flt_idx, &flt_nr);
+        SW_RTN_ON_ERROR(rv);
+
+        for (j = 0; j < flt_nr; j++)
+        {
+            _shiva_acl_filter_free(dev_id, flt_idx[j]);
+        }
+    }
+
+    cnt = list_ent[dev_id][list_idx].size - (rule_id + rule_nr);
+    rule_idx = list_ent[dev_id][list_idx].addr + (rule_id + rule_nr);
+    rv = _shiva_acl_rule_copy(dev_id, rule_idx, rule_idx - rule_nr, cnt);
+    SW_RTN_ON_ERROR(rv);
+
+    addr = list_ent[dev_id][list_idx].addr;
+    size = list_ent[dev_id][list_idx].size;
+    rv = hsl_acl_blk_resize(dev_id, addr, size - rule_nr);
+    SW_RTN_ON_ERROR(rv);
+
+    list_ent[dev_id][list_idx].size -= rule_nr;
+    _shiva_acl_filter_commit(dev_id);
+    _shiva_acl_list_dump(dev_id);
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+                      a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+    a_uint32_t list_idx, ent_idx, tmp_ent_idx, rule_idx;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = _shiva_acl_list_loc(dev_id, list_id, &list_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    if (rule_id >= list_ent[dev_id][list_idx].size)
+    {
+        return SW_NOT_FOUND;
+    }
+
+    aos_mem_zero(rule, sizeof (fal_acl_rule_t));
+
+    ent_idx = 0;
+    tmp_ent_idx = 0;
+    rule_idx = list_ent[dev_id][list_idx].addr + rule_id;
+    rv = _shiva_acl_rule_get(dev_id, hw_rule_ent, &tmp_ent_idx, rule_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = _shiva_acl_rule_hw_to_sw(rule, hw_rule_ent, ent_idx,
+                                  tmp_ent_idx - ent_idx);
+    return rv;
+}
+
+static sw_error_t
+_shiva_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                     fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                     a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+    a_uint32_t i, list_idx, rule_idx, base, ports;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_ACL_DIREC_IN != direc)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACL_BIND_PORT != obj_t)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    rv = _shiva_acl_list_loc(dev_id, list_id, &list_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    if (list_ent[dev_id][list_idx].bind_pts & (0x1 << obj_idx))
+    {
+        return SW_ALREADY_EXIST;
+    }
+
+    base = list_ent[dev_id][list_idx].addr;
+    ports = list_ent[dev_id][list_idx].bind_pts | (0x1 << obj_idx);
+    for (i = 0; i < list_ent[dev_id][list_idx].size; i++)
+    {
+        rule_idx = base + i;
+        rv = _shiva_acl_rule_bind(dev_id, rule_idx, ports);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    list_ent[dev_id][list_idx].bind_pts = ports;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                       fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                       a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+    a_uint32_t i, list_idx, rule_idx, base, ports;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_ACL_DIREC_IN != direc)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_ACL_BIND_PORT != obj_t)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    rv = _shiva_acl_list_loc(dev_id, list_id, &list_idx);
+    SW_RTN_ON_ERROR(rv);
+
+    if (!(list_ent[dev_id][list_idx].bind_pts & (0x1 << obj_idx)))
+    {
+        return SW_NOT_FOUND;
+    }
+
+    base = list_ent[dev_id][list_idx].addr;
+    ports = list_ent[dev_id][list_idx].bind_pts & (~(0x1UL << obj_idx));
+    for (i = 0; i < list_ent[dev_id][list_idx].size; i++)
+    {
+        rule_idx = base + i;
+        rv = _shiva_acl_rule_bind(dev_id, rule_idx, ports);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    list_ent[dev_id][list_idx].bind_pts = ports;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ACL_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ACL_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+shiva_acl_list_dump(a_uint32_t dev_id)
+{
+    a_uint32_t idx;
+
+    aos_printk("\nshiva_acl_list_dump:\n");
+    for (idx = 0; idx < SHIVA_MAX_LIST; idx++)
+    {
+        if (ENT_USED == list_ent[dev_id][idx].status)
+        {
+            aos_printk
+            ("\n[id]:%02d  [pri]:%02d  [size]:%02d  [addr]:%02d  [pts_map]:0x%02x",
+             list_ent[dev_id][idx].list_id, list_ent[dev_id][idx].list_pri,
+             list_ent[dev_id][idx].size, list_ent[dev_id][idx].addr,
+             list_ent[dev_id][idx].bind_pts);
+        }
+    }
+    aos_printk("\n");
+
+    return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+shiva_acl_rule_dump(a_uint32_t dev_id)
+{
+    a_uint32_t slt_idx, flt_nr, i, j;
+    a_uint32_t flt_idx[4] = {0};
+    sw_error_t rv;
+    shiva_acl_hw_rule_t rule;
+
+    aos_printk("\nshiva_acl_rule_dump:\n");
+
+    aos_printk("\nfilter_bitmap:0x%x", filter[dev_id]);
+    for (slt_idx = 0; slt_idx < SHIVA_MAX_RULE; slt_idx++)
+    {
+        aos_mem_zero(&rule, sizeof (shiva_acl_hw_rule_t));
+
+        rv = _shiva_acl_slct_read(dev_id, &rule, slt_idx);
+        if (SW_OK != rv)
+        {
+            continue;
+        }
+
+        rv = _shiva_acl_filter_map_get(&rule, flt_idx, &flt_nr);
+        if (SW_OK != rv)
+        {
+            continue;
+        }
+
+        aos_printk("\nslct_idx=%d  ", slt_idx);
+        for (i = 0; i < flt_nr; i++)
+        {
+            aos_printk("flt%d_idx=%d  ", i, flt_idx[i]);
+        }
+
+        aos_printk("\nslt:");
+        for (i = 0; i < (sizeof(rule.slct)/sizeof(a_uint32_t)); i++)
+        {
+            aos_printk("%08x  ", rule.slct[i]);
+        }
+
+        if (flt_nr)
+        {
+            rv = _shiva_acl_action_read(dev_id, &rule, slt_idx);
+            if (SW_OK != rv)
+            {
+                continue;
+            }
+
+            aos_printk("\nact:");
+            for (i = 0; i < (sizeof(rule.act)/sizeof(a_uint32_t)); i++)
+            {
+                aos_printk("%08x  ", rule.act[i]);
+            }
+
+            for (i = 0; i < flt_nr; i++)
+            {
+                rv = _shiva_acl_filter_read(dev_id, &rule, flt_idx[i]);
+                if (SW_OK != rv)
+                {
+                    continue;
+                }
+
+                aos_printk("\ntyp:%08x  length:%08x", rule.typ, rule.len);
+                aos_printk("\nvlu:");
+                for (j = 0; j < (sizeof(rule.vlu)/sizeof(a_uint32_t)); j++)
+                {
+                    aos_printk("%08x  ", rule.vlu[j]);
+                }
+
+                aos_printk("\nmsk:");
+                for (j = 0; j < (sizeof(rule.msk)/sizeof(a_uint32_t)); j++)
+                {
+                    aos_printk("%08x  ", rule.msk[j]);
+                }
+                aos_printk("\n");
+            }
+        }
+        aos_printk("\n");
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+shiva_acl_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+    a_uint32_t i;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    aos_mem_zero(hw_rule_ent,
+                 (SHIVA_MAX_RULE + 3) * sizeof (shiva_acl_hw_rule_t));
+
+    aos_mem_zero(list_ent[dev_id],
+                 SHIVA_MAX_LIST * sizeof (shiva_acl_list_t));
+
+    for (i = 0; i < SHIVA_MAX_LIST; i++)
+    {
+        list_ent[dev_id][i].status = ENT_FREE;
+    }
+
+    filter[dev_id]      = 0;
+    filter_snap[dev_id] = 0;
+
+    rv = hsl_acl_pool_destroy(dev_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = hsl_acl_pool_creat(dev_id, SHIVA_MAX_LIST, SHIVA_MAX_RULE);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+/**
+ * @brief Creat an acl list
+ * @details  Comments:
+  *     If the priority of a list is more small then the priority is more high,
+ *     that means the list could be first matched.
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] list_pri acl list priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+                     a_uint32_t list_pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_acl_list_creat(dev_id, list_id, list_pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Destroy an acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_acl_list_destroy(dev_id, list_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add one rule or more rules to an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this adding operation in list
+ * @param[in] rule_nr rule number of this adding operation
+ * @param[in] rule rules content of this adding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+                   a_uint32_t rule_id, a_uint32_t rule_nr,
+                   fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete one rule or more rules from an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[in] rule_nr rule number of this deleteing operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+                      a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_acl_rule_delete(dev_id, list_id, rule_id, rule_nr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Query one particular rule in a particular acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[out] rule rule content of this operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+                     a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_acl_rule_query(dev_id, list_id, rule_id, rule);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Bind an acl list to a particular object
+ * @details  Comments:
+ *    If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this binding operation
+ * @param[in] obj_t object type of this binding operation
+ * @param[in] obj_idx object index of this binding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+                    fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                    a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Unbind an acl list from a particular object
+ * @details  Comments:
+  *    If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this unbinding operation
+ * @param[in] obj_t object type of this unbinding operation
+ * @param[in] obj_idx object index of this unbinding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+                      fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+                      a_uint32_t obj_idx)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_acl_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_acl_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+shiva_acl_init(a_uint32_t dev_id)
+{
+    static a_bool_t b_hw_rule = A_FALSE;
+    hsl_acl_func_t *acl_func;
+    shiva_acl_hw_rule_t rule;
+    sw_error_t rv;
+    a_uint32_t i;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == b_hw_rule)
+    {
+        hw_rule_ent = (shiva_acl_hw_rule_t *)
+                      aos_mem_alloc((SHIVA_MAX_RULE +
+                                     3) * sizeof (shiva_acl_hw_rule_t));
+        if (NULL == hw_rule_ent)
+        {
+            return SW_NO_RESOURCE;
+        }
+        aos_mem_zero(hw_rule_ent,
+                     (SHIVA_MAX_RULE + 3) * sizeof (shiva_acl_hw_rule_t));
+        b_hw_rule = A_TRUE;
+    }
+
+    list_ent[dev_id] = (shiva_acl_list_t *)
+                       aos_mem_alloc(SHIVA_MAX_LIST * sizeof (shiva_acl_list_t));
+    if (NULL == list_ent[dev_id])
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(list_ent[dev_id],
+                 SHIVA_MAX_LIST * sizeof (shiva_acl_list_t));
+
+    for (i = 0; i < SHIVA_MAX_LIST; i++)
+    {
+        list_ent[dev_id][i].status = ENT_FREE;
+    }
+
+    filter[dev_id] = 0;
+    filter_snap[dev_id] = 0;
+
+    rv = hsl_acl_pool_creat(dev_id, SHIVA_MAX_LIST, SHIVA_MAX_RULE);
+    SW_RTN_ON_ERROR(rv);
+
+    acl_func = hsl_acl_ptr_get(dev_id);
+    SW_RTN_ON_NULL(acl_func);
+
+    acl_func->acl_rule_copy = _shiva_acl_rule_copy;
+    acl_func->acl_rule_invalid = _shiva_acl_rule_invalid;
+    acl_func->acl_addr_update = _shiva_acl_addr_update;
+
+    /* zero acl hardware memory */
+    aos_mem_zero(&rule, sizeof (shiva_acl_hw_rule_t));
+    for (i = 0; i < SHIVA_MAX_RULE; i++)
+    {
+        rv = _shiva_acl_slct_write(dev_id, &rule, i);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+#ifdef SHIVA_SW_ENTRY
+    flt_vlu_mem = aos_mem_alloc(SHIVA_MAX_RULE * 32);
+    if (NULL == flt_vlu_mem)
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(flt_vlu_mem, SHIVA_MAX_RULE * 32);
+
+    flt_msk_mem = aos_mem_alloc(SHIVA_MAX_RULE * 32);
+    if (NULL == flt_msk_mem)
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(flt_msk_mem, SHIVA_MAX_RULE * 32);
+
+    flt_typ_mem = aos_mem_alloc(SHIVA_MAX_RULE * 4);
+    if (NULL == flt_typ_mem)
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(flt_typ_mem, SHIVA_MAX_RULE * 4);
+
+    flt_len_mem = aos_mem_alloc(SHIVA_MAX_RULE * 4);
+    if (NULL == flt_len_mem)
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(flt_len_mem, SHIVA_MAX_RULE * 4);
+
+    act_mem = aos_mem_alloc(SHIVA_MAX_RULE * 32);
+    if (NULL == act_mem)
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(act_mem, SHIVA_MAX_RULE * 32);
+
+    slct_mem = aos_mem_alloc(SHIVA_MAX_RULE * 32);
+    if (NULL == slct_mem)
+    {
+        return SW_NO_RESOURCE;
+    }
+    aos_mem_zero(slct_mem, SHIVA_MAX_RULE * 32);
+#endif
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->acl_list_creat = shiva_acl_list_creat;
+        p_api->acl_list_destroy = shiva_acl_list_destroy;
+        p_api->acl_list_bind = shiva_acl_list_bind;
+        p_api->acl_list_unbind = shiva_acl_list_unbind;
+        p_api->acl_rule_add = shiva_acl_rule_add;
+        p_api->acl_rule_delete = shiva_acl_rule_delete;
+        p_api->acl_rule_query = shiva_acl_rule_query;
+        p_api->acl_status_set = shiva_acl_status_set;
+        p_api->acl_status_get = shiva_acl_status_get;
+        p_api->acl_list_dump = shiva_acl_list_dump;
+        p_api->acl_rule_dump = shiva_acl_rule_dump;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/shiva/shiva_fdb.c b/qca-ssdk/src/hsl/shiva/shiva_fdb.c
new file mode 100755
index 0000000..5bc43b0
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_fdb.c
@@ -0,0 +1,1135 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_fdb SHIVA_FDB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_fdb.h"
+#include "shiva_reg.h"
+
+#define ARL_FLUSH_ALL             1
+#define ARL_LOAD_ENTRY            2
+#define ARL_PURGE_ENTRY           3
+#define ARL_FLUSH_ALL_UNLOCK      4
+#define ARL_FLUSH_PORT_UNICAST    5
+#define ARL_NEXT_ENTRY            6
+#define ARL_FIND_ENTRY            7
+
+#define ARL_FIRST_ENTRY           1001
+#define ARL_FLUSH_PORT_NO_STATIC  1002
+#define ARL_FLUSH_PORT_AND_STATIC 1003
+
+static a_bool_t
+shiva_fdb_is_zeroaddr(fal_mac_addr_t addr)
+{
+    a_uint32_t i;
+
+    for (i = 0; i < 6; i++)
+    {
+        if (addr.uc[i])
+        {
+            return A_FALSE;
+        }
+    }
+
+    return A_TRUE;
+}
+
+static void
+shiva_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1)
+{
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE2, addr.uc[2], *reg1);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE3, addr.uc[3], *reg1);
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0);
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0);
+
+    return;
+}
+
+static sw_error_t
+shiva_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry,
+                   a_uint32_t reg[])
+{
+    a_uint32_t port;
+
+    if (A_FALSE == entry->portmap_en)
+    {
+        if (A_TRUE !=
+                hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+
+        port = 0x1UL << entry->port.id;
+    }
+    else
+    {
+        if (A_FALSE ==
+                hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+        {
+            return SW_BAD_PARAM;
+        }
+
+        port = entry->port.map;
+    }
+
+    if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]);
+    }
+    else if (FAL_MAC_FRWRD != entry->dacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (FAL_MAC_DROP == entry->sacmd)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, SA_DROP_EN, 1, reg[2]);
+    }
+    else if (FAL_MAC_FRWRD != entry->sacmd)
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    if (A_TRUE == entry->leaky_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]);
+    }
+
+    if (A_TRUE == entry->static_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]);
+    }
+
+    if (A_TRUE == entry->mirror_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, MIRROR_EN, 1, reg[2]);
+    }
+
+    if (A_TRUE == entry->clone_en)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CLONE_EN, 1, reg[2]);
+    }
+
+    if (A_TRUE == entry->cross_pt_state)
+    {
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CROSS_PT, 1, reg[2]);
+    }
+
+    if (A_TRUE == entry->da_pri_en)
+    {
+        hsl_dev_t *p_dev;
+
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI_EN, 1, reg[2]);
+
+        SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+
+        if (entry->da_queue > (p_dev->nr_queue - 1))
+            return SW_BAD_PARAM;
+
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI, entry->da_queue, reg[2]);
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, DES_PORT, port, reg[2]);
+    shiva_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+
+    return SW_OK;
+}
+
+static void
+shiva_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+    a_uint32_t i, data;
+
+    aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+    entry->dacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_CPY_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    entry->sacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, SA_DROP_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->sacmd = FAL_MAC_DROP;
+    }
+
+    entry->leaky_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->leaky_en = A_TRUE;
+    }
+
+    entry->static_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]);
+    if (0xf == data)
+    {
+        entry->static_en = A_TRUE;
+    }
+
+    entry->mirror_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, MIRROR_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+
+    entry->clone_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, CLONE_EN, data, reg[2]);
+    if (1 == data)
+    {
+        entry->clone_en = A_TRUE;
+    }
+
+    entry->da_pri_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI_EN, data, reg[2]);
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI, data, reg[2]);
+        entry->da_pri_en = A_TRUE;
+        entry->da_queue = data & 0x3;
+    }
+
+    entry->cross_pt_state = A_FALSE;
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, CROSS_PT, data, reg[2]);
+    if (1 == data)
+    {
+        entry->cross_pt_state = A_TRUE;
+    }
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, DES_PORT, data, reg[2]);
+
+    entry->portmap_en = A_TRUE;
+    entry->port.map = data;
+
+    for (i = 0; i < 4; i++)
+    {
+        entry->addr.uc[i] = (reg[1] >> ((3 - i) << 3)) & 0xff;
+    }
+
+    for (i = 4; i < 6; i++)
+    {
+        entry->addr.uc[i] = (reg[0] >> ((7 - i) << 3)) & 0xff;
+    }
+
+    return;
+}
+
+static sw_error_t
+shiva_fdb_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    sw_error_t rv;
+    a_uint32_t busy = 1;
+    a_uint32_t full_vio;
+    a_uint32_t i = 1000;
+    a_uint32_t entry;
+    a_uint32_t hwop = op;
+
+    while (busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+                          (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_BUSY;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_BUSY, 1, entry);
+
+    if (ARL_FLUSH_PORT_AND_STATIC == hwop)
+    {
+        hwop = ARL_FLUSH_PORT_UNICAST;
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 1, entry);
+    }
+
+    if (ARL_FLUSH_PORT_NO_STATIC == hwop)
+    {
+        hwop = ARL_FLUSH_PORT_UNICAST;
+        SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 0, entry);
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_FUNC, hwop, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    busy = 1;
+    i = 1000;
+    while (busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+                          (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_FAIL;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_FULL_VIO,
+                      (a_uint8_t *) (&full_vio), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (full_vio)
+    {
+        /* must clear AT_FULL_VOI bit */
+        entry = 0x1000;
+        HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        if (ARL_LOAD_ENTRY == hwop)
+        {
+            return SW_FULL;
+        }
+        else if ((ARL_PURGE_ENTRY == hwop)
+                 || (ARL_FLUSH_PORT_UNICAST == hwop))
+        {
+            return SW_NOT_FOUND;
+        }
+        else
+        {
+            return SW_FAIL;
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+shiva_atu_get(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op)
+{
+    sw_error_t rv;
+    a_uint32_t reg[3] = { 0 };
+    a_uint32_t status = 0;
+    a_uint32_t hwop = op;
+
+    if ((ARL_NEXT_ENTRY == op)
+            || (ARL_FIND_ENTRY == op))
+    {
+        shiva_fdb_fill_addr(entry->addr, &reg[0], &reg[1]);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    /* set status not zero */
+    if (ARL_NEXT_ENTRY == op)
+    {
+        reg[2] = 0xf0000;
+    }
+
+    if (ARL_FIRST_ENTRY == op)
+    {
+        hwop = ARL_NEXT_ENTRY;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = shiva_fdb_commit(dev_id, hwop);
+    SW_RTN_ON_ERROR(rv);
+
+    /* get hardware enrety */
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]);
+
+    shiva_atu_hw_to_sw(reg, entry);
+
+    /* If hardware return back with address and status all zero,
+       that means no other next valid entry in fdb table */
+    if ((A_TRUE == shiva_fdb_is_zeroaddr(entry->addr))
+            && (0 == status))
+    {
+        if (ARL_NEXT_ENTRY == op)
+        {
+            return SW_NO_MORE;
+        }
+        else if ((ARL_FIND_ENTRY == op)
+                 || (ARL_FIRST_ENTRY == op))
+        {
+            return SW_NOT_FOUND;
+        }
+        else
+        {
+            return SW_FAIL;
+        }
+    }
+    else
+    {
+        return SW_OK;
+    }
+}
+
+static sw_error_t
+_shiva_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[3] = { 0, 0, 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = shiva_atu_sw_to_hw(dev_id, entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+                      (a_uint8_t *) (&reg[2]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (&reg[1]),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&reg[0]),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = shiva_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        rv = shiva_fdb_commit(dev_id, ARL_FLUSH_ALL);
+    }
+    else
+    {
+        rv = shiva_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_PORT_NUM, port_id, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_FDB_DEL_STATIC & flag)
+    {
+        rv = shiva_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC);
+    }
+    else
+    {
+        rv = shiva_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC);
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg0 = 0, reg1 = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    shiva_fdb_fill_addr(entry->addr, &reg0, &reg1);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (&reg1),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&reg0),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = shiva_fdb_commit(dev_id, ARL_PURGE_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_shiva_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = shiva_atu_get(dev_id, entry, ARL_FIRST_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_shiva_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    rv = shiva_atu_get(dev_id, entry, ARL_FIND_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_shiva_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEARN_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEARN_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((65535 * 7 < *time) || (7 > *time))
+    {
+        return SW_BAD_PARAM;
+    }
+    data = *time / 7;
+    *time = data * 7;
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *time = data * 7;
+    return SW_OK;
+}
+
+static void
+_shiva_fdb_hw_to_sw(a_uint32_t tbl[3], fal_fdb_entry_t * entry)
+{
+    a_uint32_t i, data;
+
+    aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+    entry->dacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_CPYCPU_EN, data, tbl[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_CPY_TO_CPU;
+    }
+
+    SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_RDTCPU_EN, data, tbl[2]);
+    if (1 == data)
+    {
+        entry->dacmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    entry->leaky_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_LEANKY_EN, data, tbl[2]);
+    if (1 == data)
+    {
+        entry->leaky_en = A_TRUE;
+    }
+
+    entry->static_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_STATUS, data, tbl[2]);
+    if (0xf == data)
+    {
+        entry->static_en = A_TRUE;
+    }
+
+    entry->clone_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_MACCLONE_EN, data, tbl[1]);
+    if (1 == data)
+    {
+        entry->clone_en = A_TRUE;
+    }
+
+    entry->sacmd = FAL_MAC_FRWRD;
+    SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_SADROP_EN, data, tbl[1]);
+    if (1 == data)
+    {
+        entry->sacmd = FAL_MAC_DROP;
+    }
+
+    entry->mirror_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_MIRROR_EN, data, tbl[1]);
+    if (1 == data)
+    {
+        entry->mirror_en = A_TRUE;
+    }
+
+    entry->da_pri_en = A_FALSE;
+    SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_PRIORITY_EN, data, tbl[1]);
+    if (1 == data)
+    {
+        SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_PRIORITY, data, tbl[1]);
+        entry->da_pri_en = A_TRUE;
+        entry->da_queue = data & 0x3;
+    }
+
+    entry->cross_pt_state = A_FALSE;
+    SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_CROSS_STATE, data, tbl[1]);
+    if (1 == data)
+    {
+        entry->cross_pt_state = A_TRUE;
+    }
+
+    SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_DES_PORT, data, tbl[1]);
+    entry->portmap_en = A_TRUE;
+    entry->port.map = data;
+
+    for (i = 2; i < 6; i++)
+    {
+        entry->addr.uc[i] = (tbl[0] >> ((5 - i) << 3)) & 0xff;
+    }
+
+    for (i = 0; i < 2; i++)
+    {
+        entry->addr.uc[i] = (tbl[1] >> ((1 - i) << 3)) & 0xff;
+    }
+}
+
+#define SHIVA_FDB_ENTRY_NUM   1024
+#define SHIVA_FDB_ENTRY_ADDR0 0x30000
+#define SHIVA_FDB_ENTRY_ADDR1 0x30004
+#define SHIVA_FDB_ENTRY_ADDR2 0x30008
+
+static sw_error_t
+_shiva_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry)
+{
+    a_uint32_t index, addr, data, tbl[3] = { 0 };
+    sw_error_t rv;
+
+    if ((NULL == iterator) || (NULL == entry))
+    {
+        return SW_BAD_PTR;
+    }
+
+    if (SHIVA_FDB_ENTRY_NUM == *iterator)
+    {
+        return SW_NO_MORE;
+    }
+
+    if (SHIVA_FDB_ENTRY_NUM < *iterator)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (index = *iterator; index < SHIVA_FDB_ENTRY_NUM; index++)
+    {
+        addr = SHIVA_FDB_ENTRY_ADDR2 + (index << 4);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_STATUS, data, tbl[2]);
+        if (data)
+        {
+            addr = SHIVA_FDB_ENTRY_ADDR0 + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            addr = SHIVA_FDB_ENTRY_ADDR1 + (index << 4);
+            HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                                  (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            _shiva_fdb_hw_to_sw(tbl, entry);
+            break;
+        }
+    }
+
+    if (SHIVA_FDB_ENTRY_NUM == index)
+    {
+        return SW_NO_MORE;
+    }
+
+    *iterator = index + 1;
+    return SW_OK;
+}
+
+/**
+ * @brief Add a Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_fdb_add(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete all Fdb entries
+ *   @details   Comments:
+ *         If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ *       entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_fdb_del_all(dev_id, flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete Fdb entries on a particular port
+ *   @details   Comments:
+ *       If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ *       entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_fdb_del_by_port(dev_id, port_id, flag);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a particular Fdb entry through mac address
+ *   @details   Comments:
+ *       Only addr field in entry is meaning. For IVL learning vid or fid field
+ *       also is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_fdb_del_by_mac(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from particular device
+ * @param[in] dev_id device id
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_fdb_first(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a particular Fdb entry from device through mac address.
+ *    @details  Comments:
+    For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_fdb_find(dev_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address learning status on a particular port.
+ *    @details  Comments:
+ *       This operation will enable or disable dynamic address learning
+ *       feature on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_fdb_port_learn_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address learning status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_fdb_port_learn_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address aging status on particular device.
+ *   @details  Comments:
+ *       This operation will enable or disable dynamic address aging
+ *       feature on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_fdb_age_ctrl_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address aging status on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_fdb_age_ctrl_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dynamic address aging time on a particular device.
+ * @details   Comments:
+ *       This operation will set dynamic address aging time on a particular device.
+ *       The unit of time is second. Because different device has differnet
+ *       hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_fdb_age_time_set(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dynamic address aging time on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_fdb_age_time_get(dev_id, time);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Iterate all fdb entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] iterator fdb entry index if it's zero means get the first entry
+ * @param[out] iterator next valid fdb entry index
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_fdb_iterate(dev_id, iterator, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+shiva_fdb_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->fdb_add = shiva_fdb_add;
+        p_api->fdb_del_all = shiva_fdb_del_all;
+        p_api->fdb_del_by_port = shiva_fdb_del_by_port;
+        p_api->fdb_del_by_mac = shiva_fdb_del_by_mac;
+        p_api->fdb_first = shiva_fdb_first;
+        p_api->fdb_find = shiva_fdb_find;
+        p_api->port_learn_set = shiva_fdb_port_learn_set;
+        p_api->port_learn_get = shiva_fdb_port_learn_get;
+        p_api->age_ctrl_set = shiva_fdb_age_ctrl_set;
+        p_api->age_ctrl_get = shiva_fdb_age_ctrl_get;
+        p_api->age_time_set = shiva_fdb_age_time_set;
+        p_api->age_time_get = shiva_fdb_age_time_get;
+        p_api->fdb_iterate  = shiva_fdb_iterate;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/shiva/shiva_igmp.c b/qca-ssdk/src/hsl/shiva/shiva_igmp.c
new file mode 100755
index 0000000..2427d78
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_igmp.c
@@ -0,0 +1,980 @@
+/*
+ * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_igmp SHIVA_IGMP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_igmp.h"
+#include "shiva_reg.h"
+
+static sw_error_t
+_shiva_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, JOIN_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, JOIN_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_mports_validity_check(dev_id, pts))
+    {
+        return SW_BAD_PARAM;
+    }
+    val = pts;
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *pts = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 0xf;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0xe;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_STATIC,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_STATIC,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0xf == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_LEAKY,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_LEAKY,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_V3_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_V3_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+    hsl_dev_t *p_dev;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 1, entry);
+        SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+        if (queue >= p_dev->nr_queue)
+        {
+            return SW_BAD_PARAM;
+        }
+        SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, queue, entry);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 0, entry);
+        SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, 0, entry);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, QM_CTL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI_EN, data, entry);
+    if (data)
+    {
+        *enable = A_TRUE;
+        SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI, data, entry);
+        *queue  = data;
+    }
+    else
+    {
+        *enable = A_FALSE;
+        *queue  = 0;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set igmp/mld packets snooping status on a particular port.
+ * @details    Comments:
+ *   After enabling igmp/mld snooping feature on a particular port all kinds
+ *   igmp/mld packets received on this port would be acknowledged by hardware.
+ *   Particular forwarding decision could be setted by fal_igmp_mld_cmd_set.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_igmps_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets snooping status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_igmps_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld packets forwarding command on a particular device.
+ * @details    Comments:
+ *    Particular device may only support parts of forwarding commands.
+ *    This operation will take effect only after enabling igmp/mld snooping
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_igmp_mld_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_igmp_mld_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld join packets hardware acknowledgement status on particular port.
+ * @details    Comments:
+ *    After enabling igmp/mld join feature on a particular port hardware will
+ *    dynamic learning or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_igmp_mld_join_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_igmp_mld_join_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @details    Comments:
+ *    After enabling igmp leave feature on a particular port hardware will dynamic
+ *    deleting or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_igmp_mld_leave_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_igmp_mld_leave_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmp/mld router ports on a particular device.
+ * @details     Comments:
+ *    After enabling igmp/mld join/leave feature on a particular port igmp/mld
+ *    join/leave packets received on this port will be forwarded to router ports.
+ * @param[in] dev_id device id
+ * @param[in] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_igmp_mld_rp_set(dev_id, pts);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmp/mld router ports on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_igmp_mld_rp_get(dev_id, pts);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   entry creat hardware will dynamic creat and delete multicast entry,
+ *   otherwise hardware only can change destination ports of existing muticast entry.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_igmp_mld_entry_creat_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_igmp_mld_entry_creat_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the static status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   static status hardware will not age out multicast entry which leardned by hardware,
+ *   otherwise hardware will age out multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_igmp_mld_entry_static_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the static status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_igmp_mld_entry_static_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the leaky status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   leaky status hardware will set leaky flag of multicast entry which leardned by hardware,
+ *   otherwise hardware will not set leaky flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_igmp_mld_entry_leaky_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the leaky status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_igmp_mld_entry_leaky_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @details    Comments:
+ *    After enabling igmp join/leave feature on a particular port hardware will dynamic
+ *    creating or changing multicast entry after receiving igmpv3/mldv2 packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_igmp_mld_entry_v3_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_igmp_mld_entry_v3_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set the queue status of multicast entry which learned by hardware.
+ * @details    Comments:
+ *  After enabling igmp/mld join/leave feature on a particular port if enable
+ *   leaky status hardware will set queue flag of multicast entry which leardned by hardware,
+ *   otherwise hardware will not set queue flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_igmp_mld_entry_queue_set(dev_id, enable, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get the queue status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_igmp_mld_entry_queue_get(dev_id, enable, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+shiva_igmp_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->port_igmps_status_set = shiva_port_igmps_status_set;
+        p_api->port_igmps_status_get = shiva_port_igmps_status_get;
+        p_api->igmp_mld_cmd_set = shiva_igmp_mld_cmd_set;
+        p_api->igmp_mld_cmd_get = shiva_igmp_mld_cmd_get;
+        p_api->port_igmp_join_set = shiva_port_igmp_mld_join_set;
+        p_api->port_igmp_join_get = shiva_port_igmp_mld_join_get;
+        p_api->port_igmp_leave_set = shiva_port_igmp_mld_leave_set;
+        p_api->port_igmp_leave_get = shiva_port_igmp_mld_leave_get;
+        p_api->igmp_rp_set = shiva_igmp_mld_rp_set;
+        p_api->igmp_rp_get = shiva_igmp_mld_rp_get;
+        p_api->igmp_entry_creat_set = shiva_igmp_mld_entry_creat_set;
+        p_api->igmp_entry_creat_get = shiva_igmp_mld_entry_creat_get;
+        p_api->igmp_entry_static_set = shiva_igmp_mld_entry_static_set;
+        p_api->igmp_entry_static_get = shiva_igmp_mld_entry_static_get;
+        p_api->igmp_entry_leaky_set = shiva_igmp_mld_entry_leaky_set;
+        p_api->igmp_entry_leaky_get = shiva_igmp_mld_entry_leaky_get;
+        p_api->igmp_entry_v3_set = shiva_igmp_mld_entry_v3_set;
+        p_api->igmp_entry_v3_get = shiva_igmp_mld_entry_v3_get;
+        p_api->igmp_entry_queue_set = shiva_igmp_mld_entry_queue_set;
+        p_api->igmp_entry_queue_get = shiva_igmp_mld_entry_queue_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/shiva/shiva_init.c b/qca-ssdk/src/hsl/shiva/shiva_init.c
new file mode 100755
index 0000000..1fea80f
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_init.c
@@ -0,0 +1,448 @@
+/*
+ * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_init SHIVA_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_mib.h"
+#include "shiva_port_ctrl.h"
+#include "shiva_portvlan.h"
+#include "shiva_vlan.h"
+#include "shiva_fdb.h"
+#include "shiva_qos.h"
+#include "shiva_mirror.h"
+#include "shiva_stp.h"
+#include "shiva_rate.h"
+#include "shiva_misc.h"
+#include "shiva_leaky.h"
+#include "shiva_igmp.h"
+#include "shiva_acl.h"
+#include "shiva_led.h"
+#include "shiva_reg_access.h"
+#include "shiva_reg.h"
+#include "shiva_init.h"
+#include "f1_phy.h"
+
+static ssdk_init_cfg * shiva_cfg[SW_MAX_NR_DEV] = { 0 };
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+/* For SHIVA there are five internal PHY devices and seven MAC devices.
+   MAC0 always connect to external MAC device.
+   PHY4 can connect to MAC5 or external MAC device.
+   MAC6 always connect to external devices.
+   MAC1..MAC4 connect to internal PHY0..PHY3.
+*/
+static sw_error_t
+shiva_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
+{
+    hsl_port_prop_t p_type;
+    hsl_dev_t *pdev = NULL;
+    fal_port_t port_id;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return SW_NOT_INITIALIZED;
+
+    for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+    {
+        hsl_port_prop_portmap_set(dev_id, port_id);
+
+        for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
+        {
+            if (HSL_NO_CPU == mode)
+            {
+                SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                continue;
+            }
+
+            switch (p_type)
+            {
+                case HSL_PP_PHY:
+                    if (HSL_CPU_1 != mode)
+                    {
+                        if ((port_id != pdev->cpu_port_nr)
+                                && (port_id != (pdev->nr_ports -1))
+                                && (port_id != (pdev->nr_ports -2)))
+                        {
+                            SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                        }
+                    }
+                    else
+                    {
+                        if ((port_id != pdev->cpu_port_nr)
+                                && (port_id != pdev->nr_ports - 1))
+                        {
+                            SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                        }
+                    }
+                    break;
+
+                case HSL_PP_INCL_CPU:
+                    /* include cpu port but exclude wan port in some cases */
+                    if (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 2))))
+                        SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+
+                    break;
+
+                case HSL_PP_EXCL_CPU:
+                    /* exclude cpu port and wan port in some cases */
+                    if ((port_id != pdev->cpu_port_nr)
+                            && (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 2)))))
+                        SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+                    break;
+
+                default:
+                    break;
+            }
+        }
+
+        if (HSL_NO_CPU == mode)
+        {
+            SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+                            (dev_id, port_id, port_id + 1));
+        }
+        else
+        {
+            if (port_id != pdev->cpu_port_nr)
+            {
+                SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+                                (dev_id, port_id, port_id - 1));
+            }
+        }
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+shiva_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    hsl_dev_t *pdev = NULL;
+    a_uint32_t port_id;
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (NULL == pdev)
+    {
+        return SW_NOT_INITIALIZED;
+    }
+
+    for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+    {
+        if (port_id == pdev->cpu_port_nr)
+        {
+            continue;
+        }
+
+        HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data);
+
+        HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+#if 0
+static sw_error_t
+shiva_bist_test(a_uint32_t dev_id)
+{
+    a_uint32_t entry = 0, data, i;
+    sw_error_t rv;
+
+    data = 1;
+    i = 0x1000;
+    while (data && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_INIT_ERROR;
+    }
+
+    entry = 0;
+    SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = 1;
+    i = 0x1000;
+    while (data && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_INIT_ERROR;
+    }
+
+    SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry);
+    if (data)
+    {
+        SW_GET_FIELD_BY_REG(BIST_CTRL, ONE_ERR, data, entry);
+        if (!data)
+        {
+            return SW_INIT_ERROR;
+        }
+
+        SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_ADDR, data, entry);
+
+        entry = 0;
+        SW_SET_REG_BY_FIELD(BIST_RCV, RCV_EN, 1, entry);
+        SW_SET_REG_BY_FIELD(BIST_RCV, RCV_ADDR, data, entry);
+        HSL_REG_ENTRY_SET(rv, dev_id, BIST_RCV, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+    else
+    {
+        return SW_OK;
+    }
+
+    entry = 0;
+    SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry);
+    SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    data = 1;
+    i = 0x1000;
+    while (data && --i)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+                          (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+        aos_udelay(5);
+    }
+
+    if (0 == i)
+    {
+        return SW_INIT_ERROR;
+    }
+
+    SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry);
+    if (data)
+    {
+        return SW_INIT_ERROR;
+    }
+
+    return SW_OK;
+}
+#endif
+#endif
+
+static sw_error_t
+shiva_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode)
+{
+    hsl_dev_t *pdev = NULL;
+
+    pdev = hsl_dev_ptr_get(dev_id);
+    if (pdev == NULL)
+        return SW_NOT_INITIALIZED;
+
+    pdev->nr_ports = 7;
+    pdev->nr_phy = 5;
+    pdev->cpu_port_nr = 0;
+    pdev->nr_vlans = 4096;
+    pdev->hw_vlan_query = A_TRUE;
+    pdev->nr_queue = 4;
+    pdev->cpu_mode = cpu_mode;
+
+    return SW_OK;
+}
+
+
+static sw_error_t
+_shiva_reset(a_uint32_t dev_id)
+{
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    val = 0x1;
+    HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = shiva_hw_init(dev_id, shiva_cfg[dev_id]);
+    SW_RTN_ON_ERROR(rv);
+
+    SHIVA_ACL_RESET(rv, dev_id);
+#endif
+
+    return SW_OK;
+}
+
+sw_error_t
+shiva_cleanup(a_uint32_t dev_id)
+{
+    if (shiva_cfg[dev_id])
+    {
+        aos_mem_free(shiva_cfg[dev_id]);
+        shiva_cfg[dev_id] = NULL;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief reset hsl layer.
+ * @details Comments:
+ *   This operation will reset hsl layer
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_reset(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_reset(dev_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Init hsl layer.
+ * @details Comments:
+ *   This operation will init hsl layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+shiva_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+    sw_error_t rv;
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (NULL == shiva_cfg[dev_id])
+    {
+        shiva_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg));
+    }
+
+    if (NULL == shiva_cfg[dev_id])
+    {
+        return SW_OUT_OF_MEM;
+    }
+
+    aos_mem_copy(shiva_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+
+    SW_RTN_ON_ERROR(shiva_reg_access_init(dev_id, cfg->reg_mode));
+
+    SW_RTN_ON_ERROR(shiva_dev_init(dev_id, cfg->cpu_mode));
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+    {
+/*
+        if(HSL_MDIO == cfg->reg_mode)
+        {
+            SW_RTN_ON_ERROR(shiva_bist_test(dev_id));
+
+            entry = 0x1;
+            HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+                              (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            i = 0x10;
+            do
+            {
+                HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+                                  (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+                SW_RTN_ON_ERROR(rv);
+
+                aos_mdelay(10);
+            }
+            while (entry && --i);
+
+            if (0 == i)
+            {
+                return SW_INIT_ERROR;
+            }
+        }
+*/
+        SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id));
+        SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
+        SW_RTN_ON_ERROR(shiva_portproperty_init(dev_id, cfg->cpu_mode));
+
+        SHIVA_MIB_INIT(rv, dev_id);
+        SHIVA_PORT_CTRL_INIT(rv, dev_id);
+        SHIVA_PORTVLAN_INIT(rv, dev_id);
+        SHIVA_VLAN_INIT(rv, dev_id);
+        SHIVA_FDB_INIT(rv, dev_id);
+        SHIVA_QOS_INIT(rv, dev_id);
+        SHIVA_STP_INIT(rv, dev_id);
+        SHIVA_MIRR_INIT(rv, dev_id);
+        SHIVA_RATE_INIT(rv, dev_id);
+        SHIVA_MISC_INIT(rv, dev_id);
+        SHIVA_LEAKY_INIT(rv, dev_id);
+        SHIVA_IGMP_INIT(rv, dev_id);
+        SHIVA_ACL_INIT(rv, dev_id);
+        SHIVA_LED_INIT(rv, dev_id);
+
+        {
+            hsl_api_t *p_api;
+
+            SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+            p_api->dev_reset   = shiva_reset;
+            p_api->dev_clean   = shiva_cleanup;
+        }
+
+        /*SW_RTN_ON_ERROR(shiva_hw_init(dev_id, cfg));*/
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/shiva/shiva_leaky.c b/qca-ssdk/src/hsl/shiva/shiva_leaky.c
new file mode 100755
index 0000000..c68e66f
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_leaky.c
@@ -0,0 +1,526 @@
+/*
+ * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_leaky SHIVA_LEAKY
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_leaky.h"
+#include "shiva_reg.h"
+
+static sw_error_t
+_shiva_uc_leaky_mode_set(a_uint32_t dev_id,
+                         fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+    {
+        data = 0;
+    }
+    else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_uc_leaky_mode_get(a_uint32_t dev_id,
+                         fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+    }
+    else
+    {
+        *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_mc_leaky_mode_set(a_uint32_t dev_id,
+                         fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+    {
+        data = 0;
+    }
+    else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+    {
+        data = 1;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_mc_leaky_mode_get(a_uint32_t dev_id,
+                         fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+    }
+    else
+    {
+        *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, ARP_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, ARP_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+* @brief Set unicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+shiva_uc_leaky_mode_set(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_uc_leaky_mode_set(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_uc_leaky_mode_get(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_uc_leaky_mode_get(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Set multicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+shiva_mc_leaky_mode_set(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_mc_leaky_mode_set(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mc_leaky_mode_get(a_uint32_t dev_id,
+                        fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_mc_leaky_mode_get(dev_id, ctrl_mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_arp_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_arp_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_uc_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_uc_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_mc_leaky_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_mc_leaky_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+shiva_leaky_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->uc_leaky_mode_set = shiva_uc_leaky_mode_set;
+        p_api->uc_leaky_mode_get = shiva_uc_leaky_mode_get;
+        p_api->mc_leaky_mode_set = shiva_mc_leaky_mode_set;
+        p_api->mc_leaky_mode_get = shiva_mc_leaky_mode_get;
+        p_api->port_arp_leaky_set = shiva_port_arp_leaky_set;
+        p_api->port_arp_leaky_get = shiva_port_arp_leaky_get;
+        p_api->port_uc_leaky_set = shiva_port_uc_leaky_set;
+        p_api->port_uc_leaky_get = shiva_port_uc_leaky_get;
+        p_api->port_mc_leaky_set = shiva_port_mc_leaky_set;
+        p_api->port_mc_leaky_get = shiva_port_mc_leaky_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/shiva/shiva_led.c b/qca-ssdk/src/hsl/shiva/shiva_led.c
new file mode 100755
index 0000000..06bcd31
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_led.c
@@ -0,0 +1,428 @@
+/*
+ * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_led SHIVA_LED
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "shiva_led.h"
+#include "shiva_reg.h"
+
+#define MAX_LED_PATTERN_ID   1
+#define LED_PATTERN_ADDR     0xB0
+
+static sw_error_t
+_shiva_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                            led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    a_uint32_t data = 0, reg = 0, mode;
+    a_uint32_t addr;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (group >= LED_GROUP_BUTT)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (id > MAX_LED_PATTERN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((LED_MAC_PORT_GROUP == group) && (0 != id))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (LED_MAC_PORT_GROUP == group)
+    {
+        addr = LED_PATTERN_ADDR + 8;
+    }
+    else
+    {
+        addr = LED_PATTERN_ADDR + (id << 2);
+    }
+
+    if (LED_ALWAYS_OFF == pattern->mode)
+    {
+        mode = 0;
+    }
+    else if (LED_ALWAYS_BLINK == pattern->mode)
+    {
+        mode = 1;
+    }
+    else if (LED_ALWAYS_ON == pattern->mode)
+    {
+        mode = 2;
+    }
+    else if (LED_PATTERN_MAP_EN == pattern->mode)
+    {
+        mode = 3;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data);
+
+    if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << POWER_ON_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_1000M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_100M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINK_10M_LIGHT_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << COLLISION_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data);
+    }
+
+    if (pattern->map & (1 << LINKUP_OVERRIDE_EN))
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data);
+    }
+
+    if (LED_BLINK_2HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data);
+    }
+    else if (LED_BLINK_4HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data);
+    }
+    else if (LED_BLINK_8HZ == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data);
+    }
+    else if (LED_BLINK_TXRX == pattern->freq)
+    {
+        SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_WAN_PORT_GROUP == group)
+    {
+        reg &= 0xffff;
+        reg |= (data << 16);
+    }
+    else
+    {
+        reg &= 0xffff0000;
+        reg |= data;
+    }
+
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_WAN_PORT_GROUP == group)
+    {
+        return SW_OK;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_LAN_PORT_GROUP == group)
+    {
+        if (id)
+        {
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data);
+        }
+        else
+        {
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data);
+            SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data);
+        }
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(LED_PATTERN, M6_MODE, mode, data);
+        SW_SET_REG_BY_FIELD(LED_PATTERN, M5_MODE, mode, data);
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                            led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    a_uint32_t data = 0, reg = 0, tmp;
+    a_uint32_t addr;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (group >= LED_GROUP_BUTT)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (id > MAX_LED_PATTERN_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((LED_MAC_PORT_GROUP == group) && (0 != id))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t));
+
+    if (LED_MAC_PORT_GROUP == group)
+    {
+        addr = LED_PATTERN_ADDR + 8;
+    }
+    else
+    {
+        addr = LED_PATTERN_ADDR + (id << 2);
+    }
+
+    HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&reg),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (LED_WAN_PORT_GROUP == group)
+    {
+        data = (reg >> 16) & 0xffff;
+    }
+    else
+    {
+        data = reg & 0xffff;
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data);
+    if (0 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_OFF;
+    }
+    else if (1 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_BLINK;
+    }
+    else if (2 == tmp)
+    {
+        pattern->mode = LED_ALWAYS_ON;
+    }
+    else
+    {
+        pattern->mode = LED_PATTERN_MAP_EN;
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << POWER_ON_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_1000M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_100M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINK_10M_LIGHT_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << COLLISION_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << RX_TRAFFIC_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << TX_TRAFFIC_BLINK_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data);
+    if (1 == tmp)
+    {
+        pattern->map |= (1 << LINKUP_OVERRIDE_EN);
+    }
+
+    SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data);
+    if (0 == tmp)
+    {
+        pattern->freq = LED_BLINK_2HZ;
+    }
+    else if (1 == tmp)
+    {
+        pattern->freq = LED_BLINK_4HZ;
+    }
+    else if (2 == tmp)
+    {
+        pattern->freq = LED_BLINK_8HZ;
+    }
+    else
+    {
+        pattern->freq = LED_BLINK_TXRX;
+    }
+
+    return SW_OK;
+}
+
+/**
+* @brief Set led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group  pattern group, lan or wan
+* @param[in] id pattern id
+* @param[in] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+shiva_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+                           led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_led_ctrl_pattern_set(dev_id, group, id, pattern);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+* @brief Get led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group  pattern group, lan or wan
+* @param[in] id pattern id
+* @param[out] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+shiva_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+                           led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_led_ctrl_pattern_get(dev_id, group, id, pattern);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+shiva_led_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+        p_api->led_ctrl_pattern_set = shiva_led_ctrl_pattern_set;
+        p_api->led_ctrl_pattern_get = shiva_led_ctrl_pattern_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/shiva/shiva_mib.c b/qca-ssdk/src/hsl/shiva/shiva_mib.c
new file mode 100755
index 0000000..0122e56
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_mib.c
@@ -0,0 +1,663 @@
+/*
+ * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_mib SHIVA_MIB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_mib.h"
+#include "shiva_reg.h"
+
+static sw_error_t
+_shiva_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                    fal_mib_info_t * mib_info)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFcsErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxAllignErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxRunt = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFragment = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxTooLong = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxOverFlow = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Filtered = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxUnderRun = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxOverSize = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxCollision = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxAbortCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMultiCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxSingalCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxExcDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxLateCol = val;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                    fal_mib_info_t * mib_info)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFcsErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxAllignErr = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxRunt = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxFragment = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Rx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxTooLong = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxGoodByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxBadByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->RxOverFlow = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Filtered = val;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                    fal_mib_info_t * mib_info)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_OUT_OF_RANGE;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxBroad = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxPause = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMulti = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxUnderRun = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx64Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx128Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx256Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx512Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1024Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->Tx1518Byte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMaxByte = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxOverSize = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_lo = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxByte_hi = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxCollision = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxAbortCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxMultiCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxSingalCol = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxExcDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxDefer = val;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    mib_info->TxLateCol = val;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Get mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                   fal_mib_info_t * mib_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_get_mib_info(dev_id, port_id, mib_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get RX mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                   fal_mib_info_t * mib_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_get_rx_mib_info(dev_id, port_id, mib_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get TX mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+                   fal_mib_info_t * mib_info)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_get_tx_mib_info(dev_id, port_id, mib_info);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_mib_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_mib_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+shiva_mib_init(a_uint32_t dev_id)
+{
+#ifndef HSL_STANDALONG
+    hsl_api_t *p_api;
+#endif
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->get_mib_info   = shiva_get_mib_info;
+    p_api->get_rx_mib_info   = shiva_get_rx_mib_info;
+    p_api->get_tx_mib_info   = shiva_get_tx_mib_info;
+    p_api->mib_status_set = shiva_mib_status_set;
+    p_api->mib_status_get = shiva_mib_status_get;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/shiva/shiva_mirror.c b/qca-ssdk/src/hsl/shiva/shiva_mirror.c
new file mode 100755
index 0000000..07e05ec
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_mirror.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_mirror SHIVA_MIRROR
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_mirror.h"
+#include "shiva_reg.h"
+
+static sw_error_t
+_shiva_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+	sw_error_t rv;
+	a_uint32_t val;
+
+	HSL_DEV_ID_CHECK(dev_id);
+	if (port_id != MIRROR_ANALYZER_NONE) {
+		if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) {
+			return SW_BAD_PARAM;
+		}
+	}
+	val = port_id;
+	HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+	return rv;
+}
+
+static sw_error_t
+_shiva_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *port_id = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+/**
+ *   @details  Comments:
+ *   The analysis port works for both ingress and egress mirror.
+ * @brief Set mirror analyzer port on particular a device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_mirr_analysis_port_set(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get mirror analysis port on particular a device.
+ * @param[in] dev_id device id
+ * @param[out] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_mirr_analysis_port_get(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_mirr_port_in_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+                       a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_mirr_port_in_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_mirr_port_eg_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_mirr_port_eg_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+shiva_mirr_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->mirr_analysis_port_set = shiva_mirr_analysis_port_set;
+        p_api->mirr_analysis_port_get = shiva_mirr_analysis_port_get;
+        p_api->mirr_port_in_set = shiva_mirr_port_in_set;
+        p_api->mirr_port_in_get = shiva_mirr_port_in_get;
+        p_api->mirr_port_eg_set = shiva_mirr_port_eg_set;
+        p_api->mirr_port_eg_get = shiva_mirr_port_eg_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/shiva/shiva_misc.c b/qca-ssdk/src/hsl/shiva/shiva_misc.c
new file mode 100755
index 0000000..f5793a2
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_misc.c
@@ -0,0 +1,1749 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_misc SHIVA_MISC
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_misc.h"
+#include "shiva_reg.h"
+
+#define SHIVA_MAX_FRMAE_SIZE      9216
+
+static sw_error_t
+_shiva_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ARP_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_arp_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ARP_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (SHIVA_MAX_FRMAE_SIZE < size)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = size;
+    HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *size = data;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 0, data);
+    }
+    else if (FAL_MAC_DROP == cmd)
+    {
+        SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
+        SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 1, data);
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
+        SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 0, data);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_fwd_cmd_t * action)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+    a_uint32_t port_lock_en, port_drop_en;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_CTL, PORT_LOCK_EN, port_lock_en, data);
+    SW_GET_FIELD_BY_REG(PORT_CTL, LOCK_DROP_EN, port_drop_en, data);
+
+    if (1 == port_lock_en)
+    {
+        if (1 == port_drop_en)
+        {
+            *action = FAL_MAC_DROP;
+        }
+        else
+        {
+            *action = FAL_MAC_RDT_TO_CPU;
+        }
+    }
+    else
+    {
+        *action = FAL_MAC_FRWRD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t)0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t)0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data &= (~((a_uint32_t)0x1 << port_id));
+    }
+    else if (A_FALSE == enable)
+    {
+        data |= (0x1 << port_id);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, field;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    field = reg & (0x1 << port_id);
+    if (field)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_FRWRD == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_FRWRD;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, DHCP_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, DHCP_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ARP_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ARP_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_MAC_CPY_TO_CPU == cmd)
+    {
+        val = 0;
+    }
+    else if (FAL_MAC_RDT_TO_CPU == cmd)
+    {
+        val = 1;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, EAPOL_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, EAPOL_CMD,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == val)
+    {
+        *cmd = FAL_MAC_CPY_TO_CPU;
+    }
+    else
+    {
+        *cmd = FAL_MAC_RDT_TO_CPU;
+    }
+
+    return SW_OK;
+}
+
+#define SHIVA_MAX_PPPOE_SESSION  16
+#define SHIVA_MAX_SESSION_ID     0xffff
+
+static sw_error_t
+_shiva_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, i, valid, cmd, id, entry_idx = 0xffff;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (session_id > SHIVA_MAX_SESSION_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = 0; i < SHIVA_MAX_PPPOE_SESSION; i++)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+        if (!valid)
+        {
+            entry_idx = i;
+        }
+        else if (id == session_id)
+        {
+            return SW_ALREADY_EXIST;
+        }
+    }
+
+    if (0xffff == entry_idx)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 1, reg);
+    if (A_TRUE == strip_hdr)
+    {
+        cmd = 1;
+    }
+    else if (A_FALSE == strip_hdr)
+    {
+        cmd = 0;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+    SW_SET_REG_BY_FIELD(PPPOE_SESSION, STRIP_EN, cmd, reg);
+    SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, session_id, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, entry_idx,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, i, valid, id;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (session_id > SHIVA_MAX_SESSION_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = 0; i < SHIVA_MAX_PPPOE_SESSION; i++)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+        if (valid && (id == session_id))
+        {
+            SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 0, reg);
+            SW_SET_REG_BY_FIELD(PPPOE_SESSION, STRIP_EN, 0, reg);
+            SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, 0, reg);
+            HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, i,
+                              (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+            return rv;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_shiva_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, i, valid, cmd, id;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (session_id > SHIVA_MAX_SESSION_ID)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (i = 0; i < SHIVA_MAX_PPPOE_SESSION; i++)
+    {
+        HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+                          (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+        SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+        if (valid && (id == session_id))
+        {
+            SW_GET_FIELD_BY_REG(PPPOE_SESSION, STRIP_EN, cmd, reg);
+            if (cmd)
+            {
+                *strip_hdr = A_TRUE;
+            }
+            else
+            {
+                *strip_hdr = A_FALSE;
+            }
+            return SW_OK;
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_shiva_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EAPOL_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EAPOL_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, RIP_CPY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_ripv1_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, RIP_CPY_EN,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+#if 0
+static sw_error_t
+_shiva_loop_check_status_set(a_uint32_t dev_id, fal_loop_check_time_t time, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t data, intr;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE == enable)
+    {
+        if (FAL_LOOP_CHECK_1MS == time)
+        {
+            data = 1;
+        }
+        else if (FAL_LOOP_CHECK_10MS == time)
+        {
+            data = 2;
+        }
+        else if (FAL_LOOP_CHECK_100MS == time)
+        {
+            data = 3;
+        }
+        else if (FAL_LOOP_CHECK_500MS == time)
+        {
+            data = 4;
+        }
+        else
+        {
+            return SW_BAD_PARAM;
+        }
+        intr = 1;
+    }
+    else
+    {
+        data = 0;
+        intr = 0;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, LOOP_CHK_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_INT_MASK, 0, GLBM_LOOP_CHECK,
+                      (a_uint8_t *) (&intr), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_loop_check_status_get(a_uint32_t dev_id, fal_loop_check_time_t * time, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t data = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, LOOP_CHK_TIME,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *enable = A_TRUE;
+    *time   = FAL_LOOP_CHECK_1MS;
+    if (0 == data)
+    {
+        *enable = A_FALSE;
+    }
+    else if (2 == data)
+    {
+        *time   = FAL_LOOP_CHECK_10MS;
+    }
+    else if (3 == data)
+    {
+        *time   = FAL_LOOP_CHECK_100MS;
+    }
+    else if (4 == data)
+    {
+        *time   = FAL_LOOP_CHECK_500MS;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_loop_check_info_get(a_uint32_t dev_id, a_uint32_t * old_port_id, a_uint32_t * new_port_id)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, data;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, LOOP_CHECK, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(LOOP_CHECK, NEW_PORT, data, reg);
+    *new_port_id = data;
+
+    SW_GET_FIELD_BY_REG(LOOP_CHECK, OLD_PORT, data, reg);
+    *old_port_id = data;
+
+    return SW_OK;
+}
+#endif
+
+/**
+ * @brief Set arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_arp_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_arp_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_arp_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max frame size which device can received on a particular device.
+ * @details    Comments:
+ * The granularity of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[in] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_frame_max_size_set(dev_id, size);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max frame size which device can received on a particular device.
+ * @details   Comments:
+ *    The unit of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[out] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_frame_max_size_get(dev_id, size);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set forwarding command for packets which source address is unknown on a particular port.
+ * @details Comments:
+ *    Particular device may only support parts of forwarding commands.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_unk_sa_cmd_set(dev_id, port_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get forwarding command for packets which source address is unknown on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_fwd_cmd_t * action)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_unk_sa_cmd_get(dev_id, port_id, action);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown unicast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown unicast packets filter on one port then unknown
+ *   unicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_unk_uc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flooding status of unknown unicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_unk_uc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown multicast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown multicast packets filter on one port then unknown
+ *   multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_unk_mc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/** @brief Get flooding status of unknown multicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_unk_mc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flooding status of broadcast packets on a particular port.
+ * @details  Comments:
+ *   If enable unknown multicast packets filter on one port then unknown
+ *   multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_bc_filter_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/** @brief Get flooding status of broadcast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_bc_filter_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_cpu_port_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_cpu_port_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set pppoe packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling pppoe packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_pppoe_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get pppoe packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_pppoe_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set pppoe packets hardware acknowledgement status on particular device.
+ * @details     comments:
+ *   Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_pppoe_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get pppoe packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_pppoe_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set dhcp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_dhcp_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get dhcp packets hardware acknowledgement status on particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_dhcp_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set arp packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling arp packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_arp_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get arp packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_arp_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set eapol packets forwarding command on a particular device.
+ * @details     comments:
+ *   Particular device may only support parts of forwarding commands.
+ *   Ihis operation will take effect only after enabling eapol packets
+ *   hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_eapol_cmd_set(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get eapol packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_eapol_cmd_get(dev_id, cmd);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a pppoe session entry to a particular device.
+ * @param[in] dev_id device id
+ * @param[in] session_id pppoe session id
+ * @param[in] strip_hdr strip or not strip pppoe header
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_pppoe_session_add(dev_id, session_id, strip_hdr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a pppoe session entry from a particular device.
+ * @param[in] dev_id device id
+ * @param[in] session_id pppoe session id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_pppoe_session_del(dev_id, session_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a pppoe session entry from a particular device.
+ * @param[in] dev_id device id
+ * @param[in] session_id pppoe session id
+ * @param[out] strip_hdr strip or not strip pppoe header
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_pppoe_session_get(dev_id, session_id, strip_hdr);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_eapol_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_eapol_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_ripv1_status_set(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_ripv1_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_ripv1_status_get(dev_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+#if 0
+/**
+ * @brief Set loopback checking status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_loop_check_status_set(a_uint32_t dev_id, fal_loop_check_time_t time, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_loop_check_status_set(dev_id, time, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get loopback checking status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_loop_check_status_get(a_uint32_t dev_id, fal_loop_check_time_t * time, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_loop_check_status_get(dev_id, time, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get loopback checking information on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] old_port_id
+ * @param[in] new_port_id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_loop_check_info_get(a_uint32_t dev_id, a_uint32_t * old_port_id, a_uint32_t * new_port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_loop_check_info_get(dev_id, old_port_id, new_port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+#endif
+
+sw_error_t
+shiva_misc_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->arp_status_set = shiva_arp_status_set;
+        p_api->arp_status_get = shiva_arp_status_get;
+        p_api->frame_max_size_set = shiva_frame_max_size_set;
+        p_api->frame_max_size_get = shiva_frame_max_size_get;
+        p_api->port_unk_sa_cmd_set = shiva_port_unk_sa_cmd_set;
+        p_api->port_unk_sa_cmd_get = shiva_port_unk_sa_cmd_get;
+        p_api->port_unk_uc_filter_set = shiva_port_unk_uc_filter_set;
+        p_api->port_unk_uc_filter_get = shiva_port_unk_uc_filter_get;
+        p_api->port_unk_mc_filter_set = shiva_port_unk_mc_filter_set;
+        p_api->port_unk_mc_filter_get = shiva_port_unk_mc_filter_get;
+        p_api->port_bc_filter_set = shiva_port_bc_filter_set;
+        p_api->port_bc_filter_get = shiva_port_bc_filter_get;
+        p_api->cpu_port_status_set = shiva_cpu_port_status_set;
+        p_api->cpu_port_status_get = shiva_cpu_port_status_get;
+        p_api->pppoe_cmd_set = shiva_pppoe_cmd_set;
+        p_api->pppoe_cmd_get = shiva_pppoe_cmd_get;
+        p_api->pppoe_status_set = shiva_pppoe_status_set;
+        p_api->pppoe_status_get = shiva_pppoe_status_get;
+        p_api->port_dhcp_set = shiva_port_dhcp_set;
+        p_api->port_dhcp_get = shiva_port_dhcp_get;
+        p_api->arp_cmd_set = shiva_arp_cmd_set;
+        p_api->arp_cmd_get = shiva_arp_cmd_get;
+        p_api->eapol_cmd_set = shiva_eapol_cmd_set;
+        p_api->eapol_cmd_get = shiva_eapol_cmd_get;
+        p_api->pppoe_session_add = shiva_pppoe_session_add;
+        p_api->pppoe_session_del = shiva_pppoe_session_del;
+        p_api->pppoe_session_get = shiva_pppoe_session_get;
+        p_api->eapol_status_set = shiva_eapol_status_set;
+        p_api->eapol_status_get = shiva_eapol_status_get;
+        p_api->ripv1_status_set = shiva_ripv1_status_set;
+        p_api->ripv1_status_get = shiva_ripv1_status_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/shiva/shiva_port_ctrl.c b/qca-ssdk/src/hsl/shiva/shiva_port_ctrl.c
new file mode 100755
index 0000000..de5868a
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_port_ctrl.c
@@ -0,0 +1,1384 @@
+/*
+ * Copyright (c) 2012, 2015-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_port_ctrl SHIVA_PORT_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_port_ctrl.h"
+#include "shiva_reg.h"
+#include "hsl_phy.h"
+
+
+static sw_error_t
+_shiva_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_port_duplex_t duplex)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    a_uint32_t reg_save = 0;
+    a_uint32_t reg_val = 0, tmp;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_duplex_set)
+         return SW_NOT_SUPPORTED;
+
+    if (FAL_DUPLEX_BUTT <= duplex)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+	rv = phy_drv->phy_duplex_get(dev_id, phy_id, &tmp);
+	SW_RTN_ON_ERROR(rv);
+	if (tmp == duplex)
+		return SW_OK;
+
+    //save reg value
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+    reg_save = reg_val;
+
+    SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+    //set mac be config by sw   and turn off RX TX MAC_EN
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
+
+    rv = phy_drv->phy_duplex_set(dev_id, phy_id, duplex);
+
+    //retore reg value
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg_save), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_port_duplex_t * pduplex)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_duplex_get)
+         return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_duplex_get(dev_id, phy_id, pduplex);
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_speed_t speed)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_speed_set)
+         return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_SPEED_100 < speed)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = phy_drv->phy_speed_set(dev_id, phy_id, speed);
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id,
+				a_uint16_t * org_id, a_uint16_t * rev_id)
+{
+  sw_error_t rv;
+  a_uint32_t phy_id = 0;
+  hsl_phy_ops_t *phy_drv;
+  a_uint32_t phy_data;
+
+  HSL_DEV_ID_CHECK (dev_id);
+
+  if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
+    {
+      return SW_BAD_PARAM;
+    }
+
+  SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+  if (NULL == phy_drv->phy_id_get)
+    return SW_NOT_SUPPORTED;
+
+  rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
+  SW_RTN_ON_ERROR (rv);
+
+  rv = phy_drv->phy_id_get (dev_id, phy_id, &phy_data);
+  SW_RTN_ON_ERROR (rv);
+
+  *org_id = (phy_data >> 16) & 0xffff;
+  *rev_id = phy_data & 0xffff;
+
+  return rv;
+}
+
+static sw_error_t
+_shiva_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_speed_t * pspeed)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_speed_get)
+         return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_speed_get(dev_id, phy_id, pspeed);
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * status)
+{
+    a_uint32_t phy_id;
+    sw_error_t rv;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_autoneg_status_get)
+         return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *status = phy_drv->phy_autoneg_status_get(dev_id, phy_id);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_autoneg_enable_set)
+	  return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_autoneg_enable_set(dev_id, phy_id);
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_restart_autoneg)
+         return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_restart_autoneg(dev_id, phy_id);
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t autoadv)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_autoneg_adv_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_autoneg_adv_set(dev_id, phy_id, autoadv);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * autoadv)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_autoneg_adv_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *autoadv = 0;
+    rv = phy_drv->phy_autoneg_adv_get(dev_id, phy_id, autoadv);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, HEAD_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, HEAD_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val, force, reg = 0, tmp;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+    if (force)
+    {
+        /* flow control isn't in force mode so can't set */
+        return SW_DISABLE;
+    }
+	tmp = reg;
+
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
+	if (tmp == reg)
+		return SW_OK;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t rx, reg = 0;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg);
+
+    if (1 == rx)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t force, reg;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+    if (force != (a_uint32_t) enable)
+    {
+        return SW_OK;
+    }
+
+    if (A_TRUE == enable)
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 0, reg);
+        SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 0, reg);
+    }
+    else if (A_FALSE == enable)
+    {
+        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg);
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, 0, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t force, reg;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+    if (0 == force)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_powersave_set)
+	 return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_powersave_set(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_powersave_get)
+	 return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_powersave_get(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_hibernation_set)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_hibernation_set(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_hibernation_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_hibernation_get(dev_id, phy_id, enable);
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+                fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_cdt)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    rv = phy_drv->phy_cdt(dev_id, phy_id, mdi_pair, cable_status, cable_len);
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *status)
+{
+    sw_error_t rv;
+    a_uint32_t phy_id = 0;
+    hsl_phy_ops_t *phy_drv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
+    if (NULL == phy_drv->phy_link_status_get)
+        return SW_NOT_SUPPORTED;
+
+    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+    SW_RTN_ON_ERROR(rv);
+
+    *status = phy_drv->phy_link_status_get(dev_id, phy_id);
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t tx_fc_full, tx_fc_half, reg = 0;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+        (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, TX_FLOW_EN, tx_fc_full, reg);
+    SW_GET_FIELD_BY_REG(PORT_STATUS, TX_HALF_FLOW_EN, tx_fc_half, reg);
+    if (TX_FC_FULL_EN == tx_fc_full && TX_FC_HALF_EN == tx_fc_half)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t force, reg = 0, tmp;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != enable && A_FALSE != enable)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+        (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+    if (force)
+    {
+        /* flow control isn't in force mode so can't set */
+        return SW_DISABLE;
+    }
+    tmp = reg;
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, enable, reg);
+    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, enable, reg);
+    if (tmp == reg)
+        return SW_OK;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+        (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+    sw_error_t rv;
+    a_uint32_t rx_fc, reg = 0;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+        (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx_fc, reg);
+    if (RX_FC_EN == rx_fc)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t force, reg = 0, tmp;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != enable && A_FALSE != enable)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+        (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+    if (force)
+    {
+        /* flow control isn't in force mode so can't set */
+        return SW_DISABLE;
+    }
+    tmp = reg;
+
+    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, enable, reg);
+    if (tmp == reg)
+        return SW_OK;
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+        (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    return rv;
+}
+
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_duplex_t duplex)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_duplex_set(dev_id, port_id, duplex);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_port_duplex_t * pduplex)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_duplex_get(dev_id, port_id, pduplex);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_port_speed_t speed)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_speed_set(dev_id, port_id, speed);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get phy id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] org_id and rev_id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id,
+			       a_uint16_t * org_id, a_uint16_t * rev_id)
+{
+  sw_error_t rv;
+
+  HSL_API_LOCK;
+  rv = _shiva_port_phy_id_get (dev_id, port_id, org_id, rev_id);
+  HSL_API_UNLOCK;
+  return rv;
+}
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+                     fal_port_speed_t * pspeed)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_speed_get(dev_id, port_id, pspeed);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_bool_t * status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_autoneg_status_get(dev_id, port_id, status);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_autoneg_enable(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_autoneg_restart(dev_id, port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ *   @details  Comments:
+ *   auto negotiation advtisement ability is defined by macro such as
+ *   FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t autoadv)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_autoneg_adv_set(dev_id, port_id, autoadv);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * autoadv)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_autoneg_adv_get(dev_id, port_id, autoadv);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_hdr_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_hdr_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_flowctrl_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                        a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_flowctrl_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_flowctrl_forcemode_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_flowctrl_forcemode_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_powersave_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_powersave_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_hibernate_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_bool_t *enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_hibernate_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Run cable diagnostic test on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mdi_pair mdi pair id
+ * @param[out] cable_status cable status
+ * @param[out] cable_len cable len
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+               fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get linkstatus on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t *status)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_link_status_get(dev_id, port_id, status);
+    HSL_API_UNLOCK;
+
+    return rv;
+}
+
+/**
+ * @brief Get txfc status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_txfc_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+
+    return rv;
+}
+
+/**
+ * @brief Set tx flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_txfc_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+
+    return rv;
+}
+
+/**
+ * @brief Get rxfc status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_rxfc_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+
+    return rv;
+}
+
+/**
+ * @brief Set rx flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_rxfc_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+shiva_port_ctrl_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->port_duplex_get = shiva_port_duplex_get;
+        p_api->port_duplex_set = shiva_port_duplex_set;
+        p_api->port_speed_get = shiva_port_speed_get;
+        p_api->port_speed_set = shiva_port_speed_set;
+	p_api->port_phy_id_get = shiva_port_phy_id_get;
+        p_api->port_autoneg_status_get = shiva_port_autoneg_status_get;
+        p_api->port_autoneg_enable = shiva_port_autoneg_enable;
+        p_api->port_autoneg_restart = shiva_port_autoneg_restart;
+        p_api->port_autoneg_adv_get = shiva_port_autoneg_adv_get;
+        p_api->port_autoneg_adv_set = shiva_port_autoneg_adv_set;
+        p_api->port_hdr_status_set = shiva_port_hdr_status_set;
+        p_api->port_hdr_status_get = shiva_port_hdr_status_get;
+        p_api->port_flowctrl_set = shiva_port_flowctrl_set;
+        p_api->port_flowctrl_get = shiva_port_flowctrl_get;
+        p_api->port_flowctrl_forcemode_set = shiva_port_flowctrl_forcemode_set;
+        p_api->port_flowctrl_forcemode_get = shiva_port_flowctrl_forcemode_get;
+        p_api->port_powersave_set = shiva_port_powersave_set;
+        p_api->port_powersave_get = shiva_port_powersave_get;
+        p_api->port_hibernate_set = shiva_port_hibernate_set;
+        p_api->port_hibernate_get = shiva_port_hibernate_get;
+        p_api->port_cdt = shiva_port_cdt;
+        p_api->port_link_status_get = shiva_port_link_status_get;
+        p_api->port_txfc_status_get = shiva_port_txfc_status_get;
+        p_api->port_txfc_status_set = shiva_port_txfc_status_set;
+        p_api->port_rxfc_status_get = shiva_port_rxfc_status_get;
+        p_api->port_rxfc_status_set = shiva_port_rxfc_status_set;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/shiva/shiva_portvlan.c b/qca-ssdk/src/hsl/shiva/shiva_portvlan.c
new file mode 100755
index 0000000..b9292b0
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_portvlan.c
@@ -0,0 +1,1859 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_port_vlan SHIVA_PORT_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_portvlan.h"
+#include "shiva_reg.h"
+
+#define MAX_VLAN_ID           4095
+#define SHIVA_MAX_VLAN_TRANS  16
+#define SHIVA_VLAN_TRANS_ADDR 0x59000
+
+static sw_error_t
+_shiva_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_1Q_MODE_BUTT <= port_1qmode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+                      (a_uint8_t *) (&regval[port_1qmode]),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+static sw_error_t
+_shiva_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                       fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK,
+                                  FAL_1Q_CHECK, FAL_1Q_SECURE
+                                };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(pport_1qmode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    *pport_1qmode = retval[regval & 0x3];
+
+    return SW_OK;
+
+}
+
+static sw_error_t
+_shiva_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3};
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_EG_MODE_BUTT <= port_egvlanmode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+                      (a_uint8_t *) (&regval[port_egvlanmode]),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+static sw_error_t
+_shiva_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_1q_egmode_t retval[4] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED,
+                                     FAL_EG_TAGGED, FAL_EG_HYBRID
+                                   };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(pport_egvlanmode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+                      (a_uint8_t *) (&regval), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    *pport_egvlanmode = retval[regval & 0x3];
+
+    return SW_OK;
+
+}
+
+static sw_error_t
+_shiva_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    regval |= (0x1UL << mem_port_id);
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+static sw_error_t
+_shiva_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    regval &= (~(0x1UL << mem_port_id));
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    return rv;
+
+}
+
+static sw_error_t
+_shiva_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_FALSE ==
+            hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) (&mem_port_map),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    *mem_port_map = 0;
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PORT_VID_MEM, (a_uint8_t *) mem_port_map,
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id,
+                      FORCE_DEF_VID, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id,
+                      FORCE_DEF_VID, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id,
+                      FORCE_PVLAN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id,
+                      FORCE_PVLAN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    val = tpid;
+    HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+                      TAG_VALUE, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+                      TAG_VALUE, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *tpid = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pt_invlan_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t regval[FAL_INVLAN_MODE_BUTT] = { 0, 1, 2};
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_INVLAN_MODE_BUTT <= mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, IN_VLAN_MODE,
+                      (a_uint8_t *) (&regval[mode]),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_pt_invlan_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t regval = 0;
+    fal_pt_invlan_mode_t retval[FAL_INVLAN_MODE_BUTT] = { FAL_INVLAN_ADMIT_ALL,
+            FAL_INVLAN_ADMIT_TAGGED, FAL_INVLAN_ADMIT_UNTAGGED
+                                                        };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(mode);
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, IN_VLAN_MODE,
+                      (a_uint8_t *) (&regval),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (regval >= 3)
+    {
+        return SW_FAIL;
+    }
+    *mode = retval[regval & 0x3];
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+                    a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id,
+                      TLS_EN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+                    a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id,
+                      TLS_EN, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PRI_PROPAGATION, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      PRI_PROPAGATION, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t vid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((0 == vid) || (vid > MAX_VLAN_ID))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = vid;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id,
+                      DEF_SVID, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * vid)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id,
+                      DEF_SVID, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+
+    *vid = val & 0xfff;
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t vid)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((0 == vid) || (vid > MAX_VLAN_ID))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = vid;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id,
+                      DEF_CVID, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * vid)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id,
+                      DEF_CVID, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+
+    *vid = val & 0xfff;
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_vlan_propagation_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, p, c;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_VLAN_PROPAGATION_DISABLE == mode)
+    {
+        p = 0;
+        c = 0;
+    }
+    else if (FAL_VLAN_PROPAGATION_CLONE == mode)
+    {
+        p = 1;
+        c = 1;
+    }
+    else if (FAL_VLAN_PROPAGATION_REPLACE == mode)
+    {
+        p = 1;
+        c = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_DOT1AD, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(PORT_DOT1AD, PROPAGATION_EN, p, reg);
+    SW_SET_REG_BY_FIELD(PORT_DOT1AD, CLONE, c, reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PORT_DOT1AD, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 fal_vlan_propagation_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, p, c;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PORT_DOT1AD, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(PORT_DOT1AD, PROPAGATION_EN, p, reg);
+    SW_GET_FIELD_BY_REG(PORT_DOT1AD, CLONE, c, reg);
+
+    if (p)
+    {
+        if (c)
+        {
+            *mode = FAL_VLAN_PROPAGATION_CLONE;
+        }
+        else
+        {
+            *mode = FAL_VLAN_PROPAGATION_REPLACE;
+        }
+    }
+    else
+    {
+        *mode = FAL_VLAN_PROPAGATION_DISABLE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_vlan_trans_read(a_uint32_t dev_id, a_uint32_t entry_idx, fal_pbmp_t * pbmp, fal_vlan_trans_entry_t *entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, addr, table[2] = {0};
+
+    addr = SHIVA_VLAN_TRANS_ADDR + (entry_idx << 3);
+
+    /* get vlan trans table */
+    for (i = 0; i < 2; i++)
+    {
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    if (0x1 & (table[1] >> 4))
+    {
+        entry->o_vid = table[0] & 0xfff;
+        entry->s_vid = (table[0] >> 12) & 0xfff;
+        entry->c_vid = ((table[0] >> 24) & 0xff) | ((table[1] & 0xf) << 8);
+        entry->bi_dir = (~(table[1] >> 5)) & 0x1;
+        *pbmp     =  (table[1] >> 6) & 0x7f;
+        return SW_OK;
+    }
+    else
+    {
+        return SW_EMPTY;
+    }
+}
+
+static sw_error_t
+_shiva_vlan_trans_write(a_uint32_t dev_id, a_uint32_t entry_idx, fal_pbmp_t pbmp, fal_vlan_trans_entry_t entry)
+{
+    sw_error_t rv;
+    a_uint32_t i, addr, table[2] = {0};
+
+    addr = SHIVA_VLAN_TRANS_ADDR + (entry_idx << 3);
+
+    if (0 != pbmp)
+    {
+        table[0]  = entry.o_vid & 0xfff;
+        table[0] |= ((entry.s_vid & 0xfff) << 12);
+        table[0] |= ((entry.c_vid & 0xff) << 24);
+        table[1]  = (entry.c_vid >> 8) & 0xf;
+        table[1] |= (0x1 << 4);
+        table[1] |= (((~(entry.bi_dir))& 0x1) << 5);
+        table[1] |= (pbmp << 6);
+    }
+
+    /* set vlan trans table */
+    for (i = 0; i < 2; i++)
+    {
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+    sw_error_t rv;
+    fal_pbmp_t t_pbmp;
+    a_uint32_t idx, entry_idx = 0xffff, old_idx = 0xffff;
+    fal_vlan_trans_entry_t entry_temp;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (idx = 0; idx < SHIVA_MAX_VLAN_TRANS; idx++)
+    {
+        aos_mem_set(&entry_temp, 0, sizeof(fal_vlan_trans_entry_t));
+        rv = _shiva_vlan_trans_read(dev_id, idx, &t_pbmp, &entry_temp);
+        if (SW_EMPTY == rv)
+        {
+            entry_idx = idx;
+            continue;
+        }
+        SW_RTN_ON_ERROR(rv);
+
+        if (!aos_mem_cmp(&entry_temp, entry, sizeof(fal_vlan_trans_entry_t)))
+        {
+            if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+            {
+                return SW_ALREADY_EXIST;
+            }
+            old_idx = idx;
+            break;
+        }
+    }
+
+    if (0xffff != old_idx)
+    {
+        t_pbmp |= (0x1 << port_id);
+        entry_idx = old_idx;
+    }
+    else if (0xffff != entry_idx)
+    {
+        t_pbmp  = (0x1 << port_id);
+        aos_mem_copy(&entry_temp, entry, sizeof(fal_vlan_trans_entry_t));
+    }
+    else
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    return _shiva_vlan_trans_write(dev_id, entry_idx, t_pbmp, entry_temp);
+}
+
+static sw_error_t
+_shiva_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+    sw_error_t rv;
+    fal_pbmp_t t_pbmp;
+    a_uint32_t idx, entry_idx = 0xffff;
+    fal_vlan_trans_entry_t entry_temp;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (idx = 0; idx < SHIVA_MAX_VLAN_TRANS; idx++)
+    {
+        aos_mem_set(&entry_temp, 0, sizeof(fal_vlan_trans_entry_t));
+        rv = _shiva_vlan_trans_read(dev_id, idx, &t_pbmp, &entry_temp);
+        if (SW_EMPTY == rv)
+        {
+            continue;
+        }
+        SW_RTN_ON_ERROR(rv);
+
+        if ((entry->o_vid == entry_temp.o_vid)
+                && (entry->bi_dir == entry_temp.bi_dir))
+        {
+            if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+            {
+                entry_idx = idx;
+                break;
+            }
+        }
+    }
+
+    if (0xffff != entry_idx)
+    {
+        t_pbmp &= (~(0x1 << port_id));
+    }
+    else
+    {
+        return SW_NOT_FOUND;
+    }
+
+    return _shiva_vlan_trans_write(dev_id, entry_idx, t_pbmp, entry_temp);
+}
+
+static sw_error_t
+_shiva_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+    sw_error_t rv;
+    fal_pbmp_t t_pbmp;
+    a_uint32_t idx;
+    fal_vlan_trans_entry_t entry_temp;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    for (idx = 0; idx < SHIVA_MAX_VLAN_TRANS; idx++)
+    {
+        aos_mem_set(&entry_temp, 0, sizeof(fal_vlan_trans_entry_t));
+        rv = _shiva_vlan_trans_read(dev_id, idx, &t_pbmp, &entry_temp);
+        if (SW_EMPTY == rv)
+        {
+            continue;
+        }
+
+        SW_RTN_ON_ERROR(rv);
+        if ((entry->o_vid == entry_temp.o_vid)
+                && (entry->bi_dir == entry_temp.bi_dir))
+        {
+            if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+            {
+                aos_mem_copy(entry, &entry_temp, sizeof(fal_vlan_trans_entry_t));
+                return SW_OK;
+            }
+        }
+    }
+
+    return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_shiva_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * iterator, fal_vlan_trans_entry_t * entry)
+{
+    a_uint32_t index;
+    sw_error_t rv;
+    fal_vlan_trans_entry_t entry_t;
+    fal_pbmp_t pbmp_t = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((NULL == iterator) || (NULL == entry))
+    {
+        return SW_BAD_PTR;
+    }
+
+    if (SHIVA_MAX_VLAN_TRANS == *iterator)
+    {
+        return SW_NO_MORE;
+    }
+
+    if (SHIVA_MAX_VLAN_TRANS < *iterator)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    aos_mem_set(&entry_t, 0, sizeof(fal_vlan_trans_entry_t));
+    for (index = *iterator; index < SHIVA_MAX_VLAN_TRANS; index++)
+    {
+        rv = _shiva_vlan_trans_read(dev_id, index, &pbmp_t, &entry_t);
+        if (SW_EMPTY == rv)
+        {
+            continue;
+        }
+
+        if (SW_IS_PBMP_MEMBER(pbmp_t, port_id))
+        {
+            aos_mem_copy(entry, &entry_t, sizeof(fal_vlan_trans_entry_t));
+            break;
+        }
+    }
+
+    if (SHIVA_MAX_VLAN_TRANS == index)
+    {
+        return SW_NO_MORE;
+    }
+
+    *iterator = index + 1;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+    sw_error_t rv;
+    a_uint32_t stag = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_QINQ_MODE_BUTT <= mode)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QINQ_STAG_MODE == mode)
+    {
+        stag = 1;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0,
+                      STAG_MODE, (a_uint8_t *) (&stag),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+    sw_error_t rv;
+    a_uint32_t stag = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0,
+                      STAG_MODE, (a_uint8_t *) (&stag),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (stag)
+    {
+        *mode = FAL_QINQ_STAG_MODE;
+    }
+    else
+    {
+        *mode = FAL_QINQ_CTAG_MODE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role)
+{
+    sw_error_t rv;
+    a_uint32_t core = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QINQ_PORT_ROLE_BUTT <= role)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QINQ_CORE_PORT == role)
+    {
+        core = 1;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      COREP_EN, (a_uint8_t *) (&core),
+                      sizeof (a_uint32_t));
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role)
+{
+    sw_error_t rv;
+    a_uint32_t core = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+                      COREP_EN, (a_uint8_t *) (&core),
+                      sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (core)
+    {
+        *role = FAL_QINQ_CORE_PORT;
+    }
+    else
+    {
+        *role = FAL_QINQ_EDGE_PORT;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_pt_1qmode_t port_1qmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_1qmode_set(dev_id, port_id, port_1qmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                      fal_pt_1qmode_t * pport_1qmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_1qmode_get(dev_id, port_id, pport_1qmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_1q_egmode_t port_egvlanmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_portvlan_member_add(dev_id, port_id, mem_port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t mem_port_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_portvlan_member_del(dev_id, port_id, mem_port_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Update member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_pbmp_t mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_portvlan_member_update(dev_id, port_id, mem_port_map);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_pbmp_t * mem_port_map)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_portvlan_member_get(dev_id, port_id, mem_port_map);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_force_default_vid_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_force_default_vid_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_force_portvlan_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_force_portvlan_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_nestvlan_tpid_set(dev_id, tpid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_nestvlan_tpid_get(dev_id, tpid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_invlan_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_invlan_mode_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_pt_invlan_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_invlan_mode_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+                   a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_tls_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+                   a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_tls_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_pri_propagation_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_pri_propagation_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid s-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_default_svid_set(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid s-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_default_svid_get(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid c-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_default_cvid_set(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid c-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+                            a_uint32_t * vid)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_default_cvid_get(dev_id, port_id, vid);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_vlan_propagation_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_vlan_propagation_set(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+                                fal_vlan_propagation_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_vlan_propagation_get(dev_id, port_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Add a vlan translation entry to a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_vlan_trans_add(dev_id, port_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_vlan_trans_del(dev_id, port_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_vlan_trans_get(dev_id, port_id, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Iterate all vlan translation entries from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] iterator translation entry index if it's zero means get the first entry
+ * @param[out] iterator next valid translation entry index
+ * @param[out] entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * iterator, fal_vlan_trans_entry_t * entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_vlan_trans_iterate(dev_id, port_id, iterator, entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qinq_mode_set(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qinq_mode_get(dev_id, mode);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_qinq_role_set(dev_id, port_id, role);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_port_qinq_role_get(dev_id, port_id, role);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+shiva_portvlan_init(a_uint32_t dev_id)
+{
+    a_uint32_t i;
+    sw_error_t rv;
+    fal_vlan_trans_entry_t entry_init;
+    hsl_api_t *p_api;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    aos_mem_set(&entry_init, 0, sizeof(fal_vlan_trans_entry_t));
+    entry_init.bi_dir = A_TRUE;
+
+    for (i = 0; i < SHIVA_MAX_VLAN_TRANS; i++)
+    {
+        rv = _shiva_vlan_trans_write(dev_id, i, 0, entry_init);
+        SW_RTN_ON_ERROR(rv);
+    }
+
+#ifndef HSL_STANDALONG
+
+    SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->port_1qmode_get = shiva_port_1qmode_get;
+    p_api->port_1qmode_set = shiva_port_1qmode_set;
+    p_api->port_egvlanmode_get = shiva_port_egvlanmode_get;
+    p_api->port_egvlanmode_set = shiva_port_egvlanmode_set;
+    p_api->portvlan_member_add = shiva_portvlan_member_add;
+    p_api->portvlan_member_del = shiva_portvlan_member_del;
+    p_api->portvlan_member_update = shiva_portvlan_member_update;
+    p_api->portvlan_member_get = shiva_portvlan_member_get;
+    p_api->port_force_default_vid_set = shiva_port_force_default_vid_set;
+    p_api->port_force_default_vid_get = shiva_port_force_default_vid_get;
+    p_api->port_force_portvlan_set = shiva_port_force_portvlan_set;
+    p_api->port_force_portvlan_get = shiva_port_force_portvlan_get;
+    p_api->nestvlan_tpid_set = shiva_nestvlan_tpid_set;
+    p_api->nestvlan_tpid_get = shiva_nestvlan_tpid_get;
+    p_api->port_invlan_mode_set = shiva_port_invlan_mode_set;
+    p_api->port_invlan_mode_get = shiva_port_invlan_mode_get;
+    p_api->port_tls_set = shiva_port_tls_set;
+    p_api->port_tls_get = shiva_port_tls_get;
+    p_api->port_pri_propagation_set = shiva_port_pri_propagation_set;
+    p_api->port_pri_propagation_get = shiva_port_pri_propagation_get;
+    p_api->port_default_svid_set = shiva_port_default_svid_set;
+    p_api->port_default_svid_get = shiva_port_default_svid_get;
+    p_api->port_default_cvid_set = shiva_port_default_cvid_set;
+    p_api->port_default_cvid_get = shiva_port_default_cvid_get;
+    p_api->port_vlan_propagation_set = shiva_port_vlan_propagation_set;
+    p_api->port_vlan_propagation_get = shiva_port_vlan_propagation_get;
+    p_api->port_vlan_trans_add = shiva_port_vlan_trans_add;
+    p_api->port_vlan_trans_del = shiva_port_vlan_trans_del;
+    p_api->port_vlan_trans_get = shiva_port_vlan_trans_get;
+    p_api->qinq_mode_set = shiva_qinq_mode_set;
+    p_api->qinq_mode_get = shiva_qinq_mode_get;
+    p_api->port_qinq_role_set = shiva_port_qinq_role_set;
+    p_api->port_qinq_role_get = shiva_port_qinq_role_get;
+    p_api->port_vlan_trans_iterate = shiva_port_vlan_trans_iterate;
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/shiva/shiva_qos.c b/qca-ssdk/src/hsl/shiva/shiva_qos.c
new file mode 100755
index 0000000..64221f7
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_qos.c
@@ -0,0 +1,1288 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_qos SHIVA_QOS
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_qos.h"
+#include "shiva_reg.h"
+
+#define SHIVA_QOS_QUEUE_TX_BUFFER_MAX 60
+#define SHIVA_QOS_PORT_TX_BUFFER_MAX  252
+#define SHIVA_QOS_PORT_RX_BUFFER_MAX  60
+
+//#define SHIVA_MIN_QOS_MODE_PRI 0
+#define SHIVA_MAX_QOS_MODE_PRI 3
+
+static sw_error_t
+_shiva_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                   a_bool_t * enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (SHIVA_QOS_QUEUE_TX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = *number / 4;
+    *number = val << 2;
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                               fal_queue_t queue_id, a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    *number = val << 2;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (SHIVA_QOS_PORT_TX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = *number / 4;
+    *number = val << 2;
+    HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *number = val << 2;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (SHIVA_QOS_PORT_RX_BUFFER_MAX < *number)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = *number / 4;
+    *number = val << 2;
+    HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_IN_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * number)
+{
+    a_uint32_t val = 0;
+    sw_error_t rv;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_IN_DESC_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *number = val << 2;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+                           fal_queue_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+    hsl_dev_t *p_dev = NULL;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_DOT1P_MAX < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+    if (p_dev->nr_queue <= queue)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = queue;
+    HSL_REG_FIELD_GEN_SET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2,
+                          (a_uint16_t) (up << 1), (a_uint8_t *) (&val),
+                          sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+                           fal_queue_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_DOT1P_MAX < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GEN_GET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2,
+                          (a_uint16_t) (up << 1), (a_uint8_t *) (&val),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *queue = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+                             fal_queue_t queue)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+    a_uint32_t offsetaddr;
+    a_uint16_t fieldoffset;
+    hsl_dev_t *p_dev = NULL;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_DSCP_MAX < dscp)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+    if (p_dev->nr_queue <= queue)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    offsetaddr = (dscp >> 4) << 2;
+    fieldoffset = (dscp & 0xf) << 1;
+
+    val = queue;
+    HSL_REG_FIELD_GEN_SET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr),
+                          2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+                             fal_queue_t * queue)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+    a_uint32_t offsetaddr;
+    a_uint16_t fieldoffset;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_DSCP_MAX < dscp)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    offsetaddr = (dscp / 16) << 2;
+    fieldoffset = (dscp & 0xf) << 1;
+
+    HSL_REG_FIELD_GEN_GET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr),
+                          2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *queue = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_qos_mode_t mode, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        val = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_PORT_MODE == mode)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                         fal_qos_mode_t mode, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (FAL_QOS_PORT_MODE == mode)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_qos_mode_t mode, a_uint32_t pri)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (SHIVA_MAX_QOS_MODE_PRI < pri)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val);
+    }
+    else if (FAL_QOS_PORT_MODE == mode)
+    {
+        SW_SET_REG_BY_FIELD(PRI_CTL, PORT_PRI_SEL, pri, val);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                             fal_qos_mode_t mode, a_uint32_t * pri)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0, f_val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (FAL_QOS_DA_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_UP_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_DSCP_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry);
+    }
+    else if (FAL_QOS_PORT_MODE == mode)
+    {
+        SW_GET_FIELD_BY_REG(PRI_CTL, PORT_PRI_SEL, f_val, entry);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    *pri = f_val;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t up)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_DOT1P_MAX < up)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    val = up;
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id, ING_PRI,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+                               a_uint32_t * up)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id, ING_PRI,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    *up = val;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                             fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0, val, w[4] = {0};
+    a_int32_t  i, _index;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SCH_SP_MODE == mode)
+    {
+        val   = 0;
+        _index = -1;
+    }
+    else if (FAL_SCH_WRR_MODE == mode)
+    {
+        val   = 3;
+        _index = 3;
+    }
+    else if (FAL_SCH_MIX_MODE == mode)
+    {
+        val   = 1;
+        _index = 2;
+    }
+    else if (FAL_SCH_MIX_PLUS_MODE == mode)
+    {
+        val   = 2;
+        _index = 1;
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    for (i = _index; i >= 0; i--)
+    {
+        if (weight[i] > 0x1f)
+        {
+            return SW_BAD_PARAM;
+        }
+        w[i] = weight[i];
+    }
+
+    HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (&reg),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_SET_REG_BY_FIELD(WRR_CTRL, SCH_MODE, val, reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q3_W, w[3], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q2_W, w[2], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q1_W, w[1], reg);
+    SW_SET_REG_BY_FIELD(WRR_CTRL, Q0_W, w[0], reg);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, WRR_CTRL, port_id,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                             fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+    a_uint32_t val = 0, sch, w[4], i;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (&val),
+                      sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    SW_GET_FIELD_BY_REG(WRR_CTRL, SCH_MODE, sch, val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q3_W, w[3], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q2_W, w[2], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q1_W, w[1], val);
+    SW_GET_FIELD_BY_REG(WRR_CTRL, Q0_W, w[0], val);
+
+    if (0 == sch)
+    {
+        *mode = FAL_SCH_SP_MODE;
+    }
+    else if (1 == sch)
+    {
+        *mode = FAL_SCH_MIX_MODE;
+    }
+    else if (2 == sch)
+    {
+        *mode = FAL_SCH_MIX_PLUS_MODE;
+    }
+    else
+    {
+        *mode = FAL_SCH_WRR_MODE;
+    }
+
+    for (i = 0; i < 6; i++)
+    {
+        weight[i] = 0;
+    }
+
+    for (i = 0; i < 4; i++)
+    {
+        weight[i] = w[i];
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting queue on one particular port.
+ *   @details  Comments:
+ *    If enable queue tx buffer on one port that means each queue of this port
+ *    will have fixed number buffers when transmitting packets. Otherwise they
+ *    share the whole buffers with other queues in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_queue_tx_buf_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting queue on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                  a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_queue_tx_buf_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting port on one particular port.
+ *   @details  Comments:
+    If enable tx buffer on one port that means this port will have fixed
+    number buffers when transmitting packets. Otherwise they will
+    share the whole buffers with other ports in device.
+ *    function will return actual buffer numbers in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_port_tx_buf_status_set(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+                                 a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_port_tx_buf_status_get(dev_id, port_id, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting queue on one particular port.
+ *   @details   Comments:
+    The step of buffer number in SHIVA is 4, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for queue is 4 to 60.
+ *    share the whole buffers with other ports in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting queue on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                              fal_queue_t queue_id, a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting port on one particular port.
+ *   @details   Comments:
+    The step of buffer number in SHIVA is four, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for transmitting port is 4 to 124.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_port_tx_buf_nr_set(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_port_tx_buf_nr_get(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of receiving port on one particular port.
+ *   @details   Comments:
+    The step of buffer number in SHIVA is four, function will return actual
+    buffer numbers in hardware.
+    The buffer number range for receiving port is 4 to 60.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_port_rx_buf_nr_set(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of receiving port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+                             a_uint32_t * number)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_port_rx_buf_nr_get(dev_id, port_id, number);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set user priority to mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dot1p 802.1p
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+                          fal_queue_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_cosmap_up_queue_set(dev_id, up, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get user priority to mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dot1p 802.1p
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+                          fal_queue_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_cosmap_up_queue_get(dev_id, up, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+                            fal_queue_t queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_cosmap_dscp_queue_set(dev_id, dscp, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+                            fal_queue_t * queue)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_cosmap_dscp_queue_get(dev_id, dscp, queue);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qos_mode_t mode, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_port_mode_set(dev_id, port_id, mode, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+                        fal_qos_mode_t mode, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_port_mode_get(dev_id, port_id, mode, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set priority of one particular qos mode on one particular port.
+ *   @details   Comments:
+    If the priority of a mode is more small then the priority is more high.
+    Differnet mode should have differnet priority.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_qos_mode_t mode, a_uint32_t pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get priority of one particular qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_qos_mode_t mode, a_uint32_t * pri)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] up 802.1p
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t up)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_port_default_up_set(dev_id, port_id, up);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] up 802.1p
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+                              a_uint32_t * up)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_port_default_up_get(dev_id, port_id, up);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set traffic scheduling mode on particular one port.
+ *   @details   Comments:
+ *   When scheduling mode is sp the weight is meaningless usually it's zero
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[in] weight[] weight value for each queue when in wrr mode,
+              the max value supported by SHIVA is 0x1f.
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+                            fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_port_sch_mode_set(dev_id, port_id, mode, weight);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get traffic scheduling mode on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] fal_sch_mode_t traffic scheduling mode
+ * @param[out] weight weight value for wrr mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+                            fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_qos_port_sch_mode_get(dev_id, port_id, mode, weight);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+shiva_qos_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->qos_queue_tx_buf_status_set = shiva_qos_queue_tx_buf_status_set;
+        p_api->qos_queue_tx_buf_status_get = shiva_qos_queue_tx_buf_status_get;
+        p_api->qos_port_tx_buf_status_set = shiva_qos_port_tx_buf_status_set;
+        p_api->qos_port_tx_buf_status_get = shiva_qos_port_tx_buf_status_get;
+        p_api->qos_queue_tx_buf_nr_set = shiva_qos_queue_tx_buf_nr_set;
+        p_api->qos_queue_tx_buf_nr_get = shiva_qos_queue_tx_buf_nr_get;
+        p_api->qos_port_tx_buf_nr_set = shiva_qos_port_tx_buf_nr_set;
+        p_api->qos_port_tx_buf_nr_get = shiva_qos_port_tx_buf_nr_get;
+        p_api->qos_port_rx_buf_nr_set = shiva_qos_port_rx_buf_nr_set;
+        p_api->qos_port_rx_buf_nr_get = shiva_qos_port_rx_buf_nr_get;
+        p_api->cosmap_up_queue_set = shiva_cosmap_up_queue_set;
+        p_api->cosmap_up_queue_get = shiva_cosmap_up_queue_get;
+        p_api->cosmap_dscp_queue_set = shiva_cosmap_dscp_queue_set;
+        p_api->cosmap_dscp_queue_get = shiva_cosmap_dscp_queue_get;
+        p_api->qos_port_mode_set = shiva_qos_port_mode_set;
+        p_api->qos_port_mode_get = shiva_qos_port_mode_get;
+        p_api->qos_port_mode_pri_set = shiva_qos_port_mode_pri_set;
+        p_api->qos_port_mode_pri_get = shiva_qos_port_mode_pri_get;
+        p_api->qos_port_default_up_set = shiva_qos_port_default_up_set;
+        p_api->qos_port_default_up_get = shiva_qos_port_default_up_get;
+        p_api->qos_port_sch_mode_set = shiva_qos_port_sch_mode_set;
+        p_api->qos_port_sch_mode_get = shiva_qos_port_sch_mode_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/shiva/shiva_rate.c b/qca-ssdk/src/hsl/shiva/shiva_rate.c
new file mode 100755
index 0000000..e6c64c0
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_rate.c
@@ -0,0 +1,852 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_rate SHIVA_RATE
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_rate.h"
+#include "shiva_reg.h"
+
+#define SHIVA_STORM_MIN_RATE_PPS 1000
+#define SHIVA_STORM_MAX_RATE_PPS (1024 * 1000)
+
+static sw_error_t
+shiva_stormrate_sw_to_hw(a_uint32_t swrate, a_uint32_t * hwrate)
+{
+    a_uint32_t shrnr = 0;
+    a_uint32_t tmp = swrate / 1000;
+
+    if ((SHIVA_STORM_MIN_RATE_PPS > swrate)
+            || (SHIVA_STORM_MAX_RATE_PPS < swrate))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    while ((tmp != 0) && (shrnr < 12))
+    {
+        tmp = tmp >> 1;
+        shrnr++;
+    }
+
+    if (12 == shrnr)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    *hwrate = shrnr;
+    return SW_OK;
+}
+
+static sw_error_t
+shiva_stormrate_hw_to_sw(a_uint32_t hwrate, a_uint32_t * swrate)
+{
+    if (0 == hwrate)
+    {
+        hwrate = 1;
+    }
+
+    if ((1 > hwrate) || (11 < hwrate))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    *swrate = (1 << (hwrate - 1)) * 1000;
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_queue_t queue_id, a_uint32_t * speed,
+                           a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+    a_uint32_t portrl = 0;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+                      (a_uint8_t *) (&portrl), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        if (1 == portrl)
+        {
+            /* already enable port egress rate limit, queue and port
+               egress rate limit can't coexist */
+            return SW_NOT_SUPPORTED;
+        }
+
+        if ((0x7ffe << 5) < *speed)
+        {
+            return SW_BAD_PARAM;
+        }
+        val = *speed >> 5;
+        *speed = val << 5;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0x7fff;
+        *speed = 0;
+        if (1 == portrl)
+        {
+            /* already enable port egress rate limit */
+            return SW_OK;
+        }
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_queue_t queue_id, a_uint32_t * speed,
+                           a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == val)
+    {
+        /* already enable port egress rate limit */
+        *speed = 0;
+        *enable = A_FALSE;
+
+        return SW_OK;
+    }
+
+    if (0 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (1 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (2 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else if (3 == queue_id)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (0x7fff == val)
+    {
+        *enable = A_FALSE;
+    }
+    else
+    {
+        *enable = A_TRUE;
+        *speed = val << 5;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+    a_uint32_t portrl = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+                      (a_uint8_t *) (&portrl), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_FALSE == enable)
+    {
+        *speed = 0;
+
+        /* if port egress rate limit current enable then disable */
+        if (1 == portrl)
+        {
+            val = 0;
+            HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+                              (a_uint8_t *) (&val), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            val = 0x7fff;
+            HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+                              (a_uint8_t *) (&val), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+        }
+
+        rv = SW_OK;
+    }
+    else
+    {
+        if ((0x7ffe << 5) < *speed)
+        {
+            return SW_BAD_PARAM;
+        }
+
+        /* not enable egress port rate limit */
+        if (0 == portrl)
+        {
+            HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE,
+                              (a_uint8_t *) (&val), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            if (0x7fff != val)
+            {
+                /* already enable egress queue0 rate limit, queue and port
+                   egress rate limit can't coexist */
+                return SW_NOT_SUPPORTED;
+            }
+
+            HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE,
+                              (a_uint8_t *) (&val), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            if (0x7fff != val)
+            {
+                /* already enable egress queue1 rate limit, queue and port
+                   egress rate limit can't coexist */
+                return SW_NOT_SUPPORTED;
+            }
+
+            HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE,
+                              (a_uint8_t *) (&val), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            if (0x7fff != val)
+            {
+                /* already enable egress queue2 rate limit, queue and port
+                   egress rate limit can't coexist */
+                return SW_NOT_SUPPORTED;
+            }
+
+            HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+                              (a_uint8_t *) (&val), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+
+            if (0x7fff != val)
+            {
+                /* already enable egress queue3 rate limit, queue and port
+                   egress rate limit can't coexist */
+                return SW_NOT_SUPPORTED;
+            }
+
+            val = 1;
+            HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+                              (a_uint8_t *) (&val), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+        }
+
+        val = *speed >> 5;
+        *speed = val << 5;
+        HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    }
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == val)
+    {
+        *speed = 0;
+        *enable = A_FALSE;
+        return SW_OK;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+    *enable = A_TRUE;
+    *speed = val << 5;
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE == enable)
+    {
+        if ((0x7ffe << 5) < *speed)
+        {
+            return SW_BAD_PARAM;
+        }
+        val = *speed >> 5;
+        *speed = val << 5;
+    }
+    else if (A_FALSE == enable)
+    {
+        val = 0x7fff;
+        *speed = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0x7fff == val)
+    {
+        *enable = A_FALSE;
+        *speed = 0;
+    }
+    else
+    {
+        *enable = A_TRUE;
+        *speed = val << 5;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_storm_type_t storm_type, a_bool_t enable)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    data = 2;
+    HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, UNIT,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (A_TRUE == enable)
+    {
+        data = 1;
+    }
+    else if (A_FALSE == enable)
+    {
+        data = 0;
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_UNICAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, UNI_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_MULTICAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, MUL_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_BROADCAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, BRO_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    if (0 == data)
+    {
+        data = 1;
+        HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+                            fal_storm_type_t storm_type, a_bool_t * enable)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (FAL_UNICAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, UNI_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_MULTICAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, MUL_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else if (FAL_BROADCAST_STORM == storm_type)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, BRO_EN,
+                          (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    }
+    else
+    {
+        return SW_BAD_PARAM;
+    }
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (1 == data)
+    {
+        data = 1;
+        *enable = A_TRUE;
+    }
+    else
+    {
+        *enable = A_FALSE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * rate_in_pps)
+{
+    a_uint32_t data;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    rv = shiva_stormrate_sw_to_hw(*rate_in_pps, &data);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = shiva_stormrate_hw_to_sw(data, rate_in_pps);
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+                           a_uint32_t * rate_in_pps)
+{
+    a_uint32_t data = 0;
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE,
+                      (a_uint8_t *) (&data), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = shiva_stormrate_hw_to_sw(data, rate_in_pps);
+    return rv;
+}
+
+/**
+ * @brief Set queue egress rate limit status on one particular port and queue.
+ *   @details   Comments:
+    The granularity of speed is bps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable queue egress rate limit input parameter speed is meaningless.
+    Egress queue rate limit can't coexist with port egress rate limit.
+    The step of speed is 32kbps.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_queue_t queue_id, a_uint32_t * speed,
+                          a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_rate_queue_egrl_set(dev_id, port_id, queue_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get queue egress rate limit status on one particular port and queue.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                          fal_queue_t queue_id, a_uint32_t * speed,
+                          a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_rate_queue_egrl_get(dev_id, port_id, queue_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port egress rate limit status on one particular port.
+ *   @details   Comments:
+    The granularity of speed is bps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port egress rate limit input parameter speed is meaningless.
+    Egress port rate limit can't coexist with queue egress rate limit.
+    The step of speed is 32kbps.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_rate_port_egrl_set(dev_id, port_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port egress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_rate_port_egrl_get(dev_id, port_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set port ingress rate limit status on one particular port.
+ *   @details   Comments:
+    The granularity of speed is bps.
+    Because of hardware granularity function will return actual speed in hardware.
+    When disable port ingress rate limit input parameter speed is meaningless.
+    The step of speed is 32kbps.
+ *    When disable port ingress rate limit input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t * speed, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_rate_port_inrl_set(dev_id, port_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port ingress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+                         a_uint32_t * speed, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_rate_port_inrl_get(dev_id, port_id, speed, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set particular type storm control status on one particular port.
+ *   @details   Comments:
+ *    When enable one particular packets type storm control this type packets
+ *    speed will be calculated in storm control.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_storm_type_t storm_type, a_bool_t enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_storm_ctrl_frame_set(dev_id, port_id, storm_type, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get particular type storm control status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+                           fal_storm_type_t storm_type, a_bool_t * enable)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_storm_ctrl_frame_get(dev_id, port_id, storm_type, enable);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Set storm control speed on one particular port.
+ *   @details   Comments:
+    Because of hardware granularity function will return actual speed in hardware.
+    The step of speed is kpps.
+    The speed range is from 1k to 1M
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed storm control speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * rate_in_pps)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_storm_ctrl_rate_set(dev_id, port_id, rate_in_pps);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get storm control speed on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed storm control speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+                          a_uint32_t * rate_in_pps)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_storm_ctrl_rate_get(dev_id, port_id, rate_in_pps);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+shiva_rate_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->rate_queue_egrl_set = shiva_rate_queue_egrl_set;
+        p_api->rate_queue_egrl_get = shiva_rate_queue_egrl_get;
+        p_api->rate_port_egrl_set = shiva_rate_port_egrl_set;
+        p_api->rate_port_egrl_get = shiva_rate_port_egrl_get;
+        p_api->rate_port_inrl_set = shiva_rate_port_inrl_set;
+        p_api->rate_port_inrl_get = shiva_rate_port_inrl_get;
+        p_api->storm_ctrl_frame_set = shiva_storm_ctrl_frame_set;
+        p_api->storm_ctrl_frame_get = shiva_storm_ctrl_frame_get;
+        p_api->storm_ctrl_rate_set = shiva_storm_ctrl_rate_set;
+        p_api->storm_ctrl_rate_get = shiva_storm_ctrl_rate_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/shiva/shiva_reduced_acl.c b/qca-ssdk/src/hsl/shiva/shiva_reduced_acl.c
new file mode 100755
index 0000000..eb00629
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_reduced_acl.c
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "shiva_reduced_acl.h"
+#include "hsl.h"
+
+#define SHIVA_RULE_VLU_ADDR  0x58400
+#define SHIVA_RULE_MSK_ADDR  0x58c00
+#define SHIVA_RULE_LEN_ADDR  0x58818
+#define SHIVA_RULE_ACT_ADDR  0x58000
+#define SHIVA_RULE_SLCT_ADDR 0x58800
+
+sw_error_t
+shiva_acl_rule_write(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+                     a_uint32_t msk[8])
+{
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    /* set rule value */
+    base = SHIVA_RULE_VLU_ADDR + (rule_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(vlu[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* set rule mask */
+    base = SHIVA_RULE_MSK_ADDR + (rule_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(msk[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+shiva_acl_action_write(a_uint32_t dev_id, a_uint32_t act_idx,
+                       a_uint32_t act[3])
+{
+    sw_error_t rv;
+    a_uint32_t base, addr, i;
+
+    /* set rule action */
+    base = SHIVA_RULE_ACT_ADDR + (act_idx << 5);
+    for (i = 0; i < 3; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(act[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+shiva_acl_slct_write(a_uint32_t dev_id, a_uint32_t slct_idx,
+                     a_uint32_t slct[8])
+{
+    sw_error_t rv;
+    a_uint32_t base, addr;
+    a_uint32_t i;
+
+    base = SHIVA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+    /* set rule address */
+    for (i = 1; i < 7; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(slct[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* set rule enable */
+    HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+                          (a_uint8_t *) (&(slct[0])),
+                          sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    return SW_OK;
+}
+
+sw_error_t
+shiva_acl_rule_read(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+                    a_uint32_t msk[8])
+{
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    /* get rule value */
+    base = SHIVA_RULE_VLU_ADDR + (rule_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(vlu[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    /* get rule mask */
+    base = SHIVA_RULE_MSK_ADDR + (rule_idx << 5);
+    for (i = 0; i < 5; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(msk[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+shiva_acl_action_read(a_uint32_t dev_id, a_uint32_t act_idx,
+                      a_uint32_t act[3])
+{
+    sw_error_t rv;
+    a_uint32_t base, addr, i;
+
+    /* get rule action */
+    base = SHIVA_RULE_ACT_ADDR + (act_idx << 5);
+    for (i = 0; i < 3; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(act[i])), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+shiva_acl_slct_read(a_uint32_t dev_id, a_uint32_t slct_idx,
+                    a_uint32_t slct[8])
+{
+    sw_error_t rv;
+    a_uint32_t i, base, addr;
+
+    base = SHIVA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+    /* get filter address and enable */
+    for (i = 0; i < 7; i++)
+    {
+        addr = base + (i << 2);
+        HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+                              (a_uint8_t *) (&(slct[i])),
+                              sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+    }
+
+    return SW_OK;
+}
diff --git a/qca-ssdk/src/hsl/shiva/shiva_reg_access.c b/qca-ssdk/src/hsl/shiva/shiva_reg_access.c
new file mode 100755
index 0000000..6a7f57f
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_reg_access.c
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "sd.h"
+#include "shiva_reg_access.h"
+
+static hsl_access_mode reg_mode;
+
+#if defined(API_LOCK)
+static aos_lock_t mdio_lock;
+#define MDIO_LOCKER_INIT    aos_lock_init(&mdio_lock)
+#define MDIO_LOCKER_LOCK    aos_lock(&mdio_lock)
+#define MDIO_LOCKER_UNLOCK  aos_unlock(&mdio_lock)
+#else
+#define MDIO_LOCKER_INIT
+#define MDIO_LOCKER_LOCK
+#define MDIO_LOCKER_UNLOCK
+#endif
+
+static sw_error_t
+_shiva_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                    a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+#if 0
+    /* change reg_addr to 16-bit word address, 32-bit aligned */
+    reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+    /* configure register high address */
+    phy_addr = 0x18;
+    phy_reg = 0x0;
+    phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    /* For some registers such as MIBs, since it is read/clear, we should */
+    /* read the lower 16-bit register then the higher one */
+
+    /* read register in lower address */
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+    SW_RTN_ON_ERROR(rv);
+    reg_val = tmp_val;
+
+    /* read register in higher address */
+    reg_word_addr++;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+    SW_RTN_ON_ERROR(rv);
+    reg_val |= (((a_uint32_t)tmp_val) << 16);
+#else
+    reg_val = sd_reg_mii_get(dev_id, reg_addr);
+#endif
+    aos_mem_copy(value, &reg_val, sizeof (a_uint32_t));
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+                    a_uint32_t value_len)
+{
+    a_uint32_t reg_val = 0;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    aos_mem_copy(&reg_val, value, sizeof (a_uint32_t));
+
+#if 0
+/* change reg_addr to 16-bit word address, 32-bit aligned */
+    reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+    /* configure register high address */
+    phy_addr = 0x18;
+    phy_reg = 0x0;
+    phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    /* For some registers such as ARL and VLAN, since they include BUSY bit */
+    /* in lower address, we should write the higher 16-bit register then the */
+    /* lower one */
+
+    /* write register in higher address */
+    reg_word_addr++;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff);
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+
+    /* write register in lower address */
+    reg_word_addr--;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (a_uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (a_uint16_t) (reg_val & 0xffff);
+    rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+    SW_RTN_ON_ERROR(rv);
+#else
+    sd_reg_mii_set(dev_id, reg_addr, reg_val);
+#endif
+
+    return SW_OK;
+}
+
+sw_error_t
+shiva_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+              a_uint32_t reg, a_uint16_t * value)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value);
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+shiva_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+              a_uint32_t reg, a_uint16_t value)
+{
+    sw_error_t rv;
+
+    MDIO_LOCKER_LOCK;
+    rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value);
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+shiva_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+              a_uint32_t value_len)
+{
+    sw_error_t rv;
+    unsigned long flags;
+
+    MDIO_LOCKER_LOCK;
+    if (HSL_MDIO == reg_mode)
+    {
+        aos_irq_save(flags);
+        rv = _shiva_mdio_reg_get(dev_id, reg_addr, value, value_len);
+        aos_irq_restore(flags);
+    }
+    else
+    {
+        rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len);
+    }
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+shiva_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+              a_uint32_t value_len)
+{
+    sw_error_t rv;
+    unsigned long flags;
+
+    MDIO_LOCKER_LOCK;
+    if (HSL_MDIO == reg_mode)
+    {
+        aos_irq_save(flags);
+        rv = _shiva_mdio_reg_set(dev_id, reg_addr, value, value_len);
+        aos_irq_restore(flags);
+    }
+    else
+    {
+        rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len);
+    }
+    MDIO_LOCKER_UNLOCK;
+
+    return rv;
+}
+
+sw_error_t
+shiva_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+                    a_uint32_t bit_offset, a_uint32_t field_len,
+                    a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val = 0;
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(shiva_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len);
+    return SW_OK;
+}
+
+sw_error_t
+shiva_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+                    a_uint32_t bit_offset, a_uint32_t field_len,
+                    const a_uint8_t value[], a_uint32_t value_len)
+{
+    a_uint32_t reg_val = 0;
+    a_uint32_t field_val = *((a_uint32_t *) value);
+
+    if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+        return SW_OUT_OF_RANGE;
+
+    if (value_len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+    SW_RTN_ON_ERROR(shiva_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len);
+
+    SW_RTN_ON_ERROR(shiva_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+    return SW_OK;
+}
+
+sw_error_t
+shiva_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode)
+{
+    hsl_api_t *p_api;
+
+    MDIO_LOCKER_INIT;
+    reg_mode = mode;
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+    p_api->phy_get = shiva_phy_get;
+    p_api->phy_set = shiva_phy_set;
+    p_api->reg_get = shiva_reg_get;
+    p_api->reg_set = shiva_reg_set;
+    p_api->reg_field_get = shiva_reg_field_get;
+    p_api->reg_field_set = shiva_reg_field_set;
+    p_api->dev_access_set= shiva_access_mode_set;
+
+    return SW_OK;
+}
+
+sw_error_t
+shiva_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode)
+{
+    reg_mode = mode;
+    return SW_OK;
+
+}
+
diff --git a/qca-ssdk/src/hsl/shiva/shiva_stp.c b/qca-ssdk/src/hsl/shiva/shiva_stp.c
new file mode 100755
index 0000000..62c588c
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_stp.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_stp SHIVA_STP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_stp.h"
+#include "shiva_reg.h"
+
+#define SHIVA_PORT_DISABLED      0
+#define SHIVA_STP_BLOCKING       1
+#define SHIVA_STP_LISTENING      2
+#define SHIVA_STP_LEARNING       3
+#define SHIVA_STP_FARWARDING     4
+
+static sw_error_t
+_shiva_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                          fal_port_t port_id, fal_stp_state_t state)
+{
+    sw_error_t rv;
+    a_uint32_t val;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SINGLE_STP_ID != st_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    switch (state)
+    {
+        case FAL_STP_BLOKING:
+            val = SHIVA_STP_BLOCKING;
+            break;
+        case FAL_STP_LISTENING:
+            val = SHIVA_STP_LISTENING;
+            break;
+        case FAL_STP_LEARNING:
+            val = SHIVA_STP_LEARNING;
+            break;
+        case FAL_STP_FARWARDING:
+            val = SHIVA_STP_FARWARDING;
+            break;
+        case FAL_STP_DISABLED:
+            val =  SHIVA_PORT_DISABLED;
+            break;
+        default:
+            return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, PORT_STATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    return rv;
+}
+
+static sw_error_t
+_shiva_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                          fal_port_t port_id, fal_stp_state_t * state)
+{
+    sw_error_t rv;
+    a_uint32_t val = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (FAL_SINGLE_STP_ID != st_id)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+    {
+        return SW_BAD_PARAM;
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, PORT_STATE,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    switch (val)
+    {
+        case SHIVA_STP_BLOCKING:
+            *state = FAL_STP_BLOKING;
+            break;
+        case SHIVA_STP_LISTENING:
+            *state = FAL_STP_LISTENING;
+            break;
+        case SHIVA_STP_LEARNING:
+            *state = FAL_STP_LEARNING;
+            break;
+        case SHIVA_STP_FARWARDING:
+            *state = FAL_STP_FARWARDING;
+            break;
+        case SHIVA_PORT_DISABLED:
+            *state = FAL_STP_DISABLED;
+            break;
+        default:
+            return SW_FAIL;
+    }
+
+    return SW_OK;
+}
+
+/**
+ * @brief Set port stp state on a particular spanning tree and port.
+ *   @details   Comments:
+    SHIVA only support single spanning tree so st_id should be
+    FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[in] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+                         fal_port_t port_id, fal_stp_state_t state)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_stp_port_state_set(dev_id, st_id, port_id, state);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Get port stp state on a particular spanning tree and port.
+ *   @details  Comments:
+    SHIVA only support single spanning tree so st_id should be
+    FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[out] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+                         fal_port_t port_id, fal_stp_state_t * state)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_stp_port_state_get(dev_id, st_id, port_id, state);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+shiva_stp_init(a_uint32_t dev_id)
+{
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+    {
+        hsl_api_t *p_api;
+
+        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+        p_api->stp_port_state_set = shiva_stp_port_state_set;
+        p_api->stp_port_state_get = shiva_stp_port_state_get;
+    }
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/hsl/shiva/shiva_vlan.c b/qca-ssdk/src/hsl/shiva/shiva_vlan.c
new file mode 100755
index 0000000..19dc70f
--- /dev/null
+++ b/qca-ssdk/src/hsl/shiva/shiva_vlan.c
@@ -0,0 +1,524 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup shiva_vlan SHIVA_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_vlan.h"
+#include "shiva_reg.h"
+
+#define MAX_VLAN_ID         4095
+
+#define VLAN_FLUSH          1
+#define VLAN_LOAD_ENTRY     2
+#define VLAN_PURGE_ENTRY    3
+#define VLAN_REMOVE_PORT    4
+#define VLAN_NEXT_ENTRY     5
+#define VLAN_FIND_ENTRY     6
+
+static void
+shiva_vlan_hw_to_sw(const a_uint32_t reg[], fal_vlan_t * vlan_entry)
+{
+    a_uint32_t data;
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]);
+    if (1 == data)
+    {
+        vlan_entry->vid_pri_en = A_TRUE;
+
+        SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]);
+        vlan_entry->vid_pri = data & 0xff;
+    }
+    else
+    {
+        vlan_entry->vid_pri_en = A_FALSE;
+    }
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VLAN_ID, data, reg[0]);
+    vlan_entry->vid = data & 0xffff;
+
+    SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VID_MEM, data, reg[1]);
+    vlan_entry->mem_ports = data;
+
+    return;
+}
+
+static sw_error_t
+shiva_vlan_sw_to_hw(const fal_vlan_t * vlan_entry, a_uint32_t reg[])
+{
+    if (A_TRUE == vlan_entry->vid_pri_en)
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]);
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri, reg[0]);
+    }
+    else
+    {
+        SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]);
+    }
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_entry->vid, reg[0]);
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, reg[1]);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VID_MEM, vlan_entry->mem_ports, reg[1]);
+
+    if (0 != vlan_entry->u_ports)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+shiva_vlan_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+    a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val;
+    sw_error_t rv;
+
+    while (vt_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
+                          (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_BUSY;
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_FUNC, op, val);
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_BUSY, 1, val);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    vt_busy = 1;
+    i = 0x1000;
+    while (vt_busy && --i)
+    {
+        HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
+                          (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        aos_udelay(5);
+    }
+
+    if (i == 0)
+        return SW_FAIL;
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_FULL_VIO,
+                      (a_uint8_t *) (&vt_full), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (vt_full)
+    {
+        val = 0x10;
+        HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                          (a_uint8_t *) (&val), sizeof (a_uint32_t));
+        SW_RTN_ON_ERROR(rv);
+        if (VLAN_LOAD_ENTRY == op)
+        {
+            return SW_OK;
+        }
+        else if (VLAN_PURGE_ENTRY == op)
+        {
+            return SW_NOT_FOUND;
+        }
+    }
+
+    HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_VALID,
+                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    if (!val)
+    {
+        if (VLAN_FIND_ENTRY == op)
+            return SW_NOT_FOUND;
+
+        if (VLAN_NEXT_ENTRY == op)
+            return SW_NO_MORE;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_entry->vid == 0) || (vlan_entry->vid > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    if (A_FALSE == hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU))
+        return SW_BAD_PARAM;
+
+    rv = shiva_vlan_sw_to_hw(vlan_entry, reg);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = shiva_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_shiva_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+    a_uint32_t entry = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    /* set default value for VLAN_TABLE_FUNC0, all 0 except vid */
+    entry = 0;
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, entry);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    /* set default value for VLAN_TABLE_FUNC1, all 0 */
+    entry = 0;
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, entry);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = shiva_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_shiva_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if (vlan_id > MAX_VLAN_ID)
+        return SW_OUT_OF_RANGE;
+
+    aos_mem_zero(p_vlan, sizeof (fal_vlan_t));
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = shiva_vlan_commit(dev_id, VLAN_NEXT_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    shiva_vlan_hw_to_sw(reg, p_vlan);
+
+    if (0 == p_vlan->vid)
+        return SW_NO_MORE;
+    else
+        return SW_OK;
+}
+
+static sw_error_t
+_shiva_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+    a_uint32_t reg[2] = { 0 };
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    aos_mem_zero(p_vlan, sizeof (fal_vlan_t));
+
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = shiva_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg[0]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+                      (a_uint8_t *) (&reg[1]), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    shiva_vlan_hw_to_sw(reg, p_vlan);
+
+    return SW_OK;
+}
+
+static sw_error_t
+_shiva_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                          fal_pbmp_t member, fal_pbmp_t u_member)
+{
+    sw_error_t rv;
+    a_uint32_t reg = 0;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU))
+        return SW_BAD_PARAM;
+
+    if (u_member != 0)
+        return SW_BAD_PARAM;
+
+    /* get vlan entry first */
+    SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg);
+    HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+
+    SW_RTN_ON_ERROR(rv);
+
+    rv = shiva_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+    SW_RTN_ON_ERROR(rv);
+
+    /* set vlan member for VLAN_TABLE_FUNC1 */
+    HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VID_MEM,
+                      (a_uint8_t *) (&member), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = shiva_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+    /* when update port member through LOAD opration, hardware will
+        return VT_FULL_VIO, we should ignore it */
+    if (SW_FULL == rv)
+        rv = SW_OK;
+
+    return rv;
+}
+
+static sw_error_t
+_shiva_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+    a_uint32_t reg;
+
+    HSL_DEV_ID_CHECK(dev_id);
+
+    if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+        return SW_OUT_OF_RANGE;
+
+    reg = (a_int32_t) vlan_id;
+    HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VLAN_ID,
+                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
+    SW_RTN_ON_ERROR(rv);
+
+    rv = shiva_vlan_commit(dev_id, VLAN_PURGE_ENTRY);
+    return rv;
+}
+
+static sw_error_t
+_shiva_vlan_flush(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_DEV_ID_CHECK(dev_id);
+    rv = shiva_vlan_commit(dev_id, VLAN_FLUSH);
+    return rv;
+}
+
+/**
+ * @brief Append a vlan entry on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_entry vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_vlan_entry_append(dev_id, vlan_entry);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Creat a vlan entry through vlan id on a paticular device.
+ *   @details   Comments:
+ *    After this operation the member ports of the created vlan entry are null.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_vlan_create(dev_id, vlan_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Next a vlan entry through vlan id on a paticular device.
+ *   @details   Comments:
+ *    If the value of vid is zero this operation will get the first entry.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_vlan_next(dev_id, vlan_id, p_vlan);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Find a vlan entry through vlan id on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_vlan_find(dev_id, vlan_id, p_vlan);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Update a vlan entry member port through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] member member ports
+ * @param[in] u_member tagged or untagged infomation for member ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+                         fal_pbmp_t member, fal_pbmp_t u_member)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_vlan_member_update(dev_id, vlan_id, member, u_member);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Delete a vlan entry through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_vlan_delete(dev_id, vlan_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+/**
+ * @brief Flush all vlan entries on a paticular device.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_vlan_flush(a_uint32_t dev_id)
+{
+    sw_error_t rv;
+
+    HSL_API_LOCK;
+    rv = _shiva_vlan_flush(dev_id);
+    HSL_API_UNLOCK;
+    return rv;
+}
+
+sw_error_t
+shiva_vlan_init(a_uint32_t dev_id)
+{
+    hsl_api_t *p_api;
+    HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+
+    SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+    p_api->vlan_entry_append = shiva_vlan_entry_append;
+    p_api->vlan_creat = shiva_vlan_create;
+    p_api->vlan_member_update = shiva_vlan_member_update;
+    p_api->vlan_delete = shiva_vlan_delete;
+    p_api->vlan_next = shiva_vlan_next;
+    p_api->vlan_find = shiva_vlan_find;
+    p_api->vlan_flush = shiva_vlan_flush;
+
+#endif
+
+    return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/qca-ssdk/src/init/Makefile b/qca-ssdk/src/init/Makefile
new file mode 100644
index 0000000..e54dd06
--- /dev/null
+++ b/qca-ssdk/src/init/Makefile
@@ -0,0 +1,40 @@
+LOC_DIR=src/init
+LIB=INIT
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=ssdk_init.c ssdk_plat.c ssdk_interrupt.c ssdk_dts.c
+
+ifneq (ISISC, $(CHIP_TYPE))
+	SRC_LIST += ssdk_clk.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+	SRC_LIST += ssdk_led.c
+endif
+
+ifeq (TRUE, $(IN_PHY_I2C_MODE))
+	SRC_LIST += ssdk_phy_i2c.c
+endif
+
+ifneq (,$(findstring HPPE, $(SUPPORT_CHIP)))
+	SRC_LIST += ssdk_hppe.c
+endif
+
+ifneq (,$(findstring SCOMPHY, $(SUPPORT_CHIP)))
+	SRC_LIST += ssdk_scomphy.c
+endif
+
+ifneq (,$(filter MP, $(SUPPORT_CHIP)))
+	SRC_LIST += ssdk_mp.c
+endif
+
+ifeq (TRUE, $(SWCONFIG))
+	SRC_LIST += ssdk_uci.c
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/init/ssdk_clk.c b/qca-ssdk/src/init/ssdk_clk.c
new file mode 100755
index 0000000..a3b39c4
--- /dev/null
+++ b/qca-ssdk/src/init/ssdk_clk.c
@@ -0,0 +1,1305 @@
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "sw.h"
+#include "ssdk_init.h"
+#include "ssdk_plat.h"
+#include "ssdk_clk.h"
+#include "ssdk_dts.h"
+#if defined(HPPE)
+#include "adpt_hppe.h"
+#endif
+#include "fal.h"
+#include <linux/kconfig.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+#include <linux/of.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#endif
+
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+struct device_node *clock_node = NULL;
+static struct clk *uniphy_port_clks[UNIPHYT_CLK_MAX] = {0};
+
+struct device_node *rst_node = NULL;
+struct reset_control *uniphy_rsts[UNIPHY_RST_MAX] = {0};
+struct reset_control *port_rsts[SSDK_MAX_PORT_NUM] = {0};
+
+/* below 3 routines to be used as common */
+void ssdk_clock_rate_set_and_enable(
+	struct device_node *node, a_uint8_t* clock_id, a_uint32_t rate)
+{
+	struct clk *clk;
+
+	if(ssdk_is_emulation(0)){
+		SSDK_INFO("clock_id %s rate %d on emulation platform\n",clock_id, rate);
+		return;
+	}
+
+	clk = of_clk_get_by_name(node, clock_id);
+	if (!IS_ERR(clk)) {
+		if (rate)
+			clk_set_rate(clk, rate);
+
+		clk_prepare_enable(clk);
+	}
+}
+
+void ssdk_gcc_reset(struct reset_control *rst, a_uint32_t action)
+{
+	if(ssdk_is_emulation(0)){
+		SSDK_INFO("action %d on emulation platform\n",action);
+		return;
+	}
+
+	if (action == SSDK_RESET_ASSERT)
+		reset_control_assert(rst);
+	else
+		reset_control_deassert(rst);
+
+}
+#endif
+
+void ssdk_uniphy_reset(
+	a_uint32_t dev_id,
+	enum unphy_rst_type rst_type,
+	a_uint32_t action)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	struct reset_control *rst;
+
+	rst = uniphy_rsts[rst_type];
+	if (IS_ERR(rst)) {
+		SSDK_ERROR("reset(%d) nof exist!\n", rst_type);
+		return;
+	}
+
+	ssdk_gcc_reset(rst, action);
+#endif
+
+}
+
+void ssdk_port_reset(
+	a_uint32_t dev_id,
+	a_uint32_t port_id,
+	a_uint32_t action)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	struct reset_control *rst;
+
+	if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6))
+		return;
+
+	rst = port_rsts[port_id-1];
+	if (IS_ERR(rst)) {
+		SSDK_ERROR("reset(%d) not exist!\n", port_id);
+		return;
+	}
+
+	ssdk_gcc_reset(rst, action);
+#endif
+
+}
+
+void ssdk_uniphy_clock_rate_set(
+	a_uint32_t dev_id,
+	enum unphy_clk_type clock_type,
+	a_uint32_t rate)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	struct clk *uniphy_clk;
+
+	if(ssdk_is_emulation(dev_id)){
+		SSDK_INFO("clock_type %d rate %d on emulation platform\n",
+					clock_type, rate);
+		return;
+	}
+
+	uniphy_clk = uniphy_port_clks[clock_type];
+	if (!IS_ERR(uniphy_clk)) {
+		if (rate)
+			if (clk_set_rate(uniphy_clk, rate))
+				SSDK_INFO("%d set rate=%d fail\n", clock_type, rate);
+	} else
+		SSDK_INFO("%d set rate %x fail!\n", clock_type, rate);
+#endif
+
+}
+
+void ssdk_uniphy_clock_enable(
+	a_uint32_t dev_id,
+	enum unphy_clk_type clock_type,
+	a_bool_t enable)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	struct clk *uniphy_clk;
+
+	if(ssdk_is_emulation(dev_id)){
+		SSDK_INFO("clock_type %d enable %d on emulation platform\n",
+					clock_type, enable);
+		return;
+	}
+
+	uniphy_clk = uniphy_port_clks[clock_type];
+	if (!IS_ERR(uniphy_clk)) {
+		if (enable) {
+			if (clk_prepare_enable(uniphy_clk))
+				SSDK_ERROR("clock enable fail!\n");
+		} else
+			clk_disable_unprepare(uniphy_clk);
+	} else {
+		SSDK_DEBUG("clock_type= %d enable=%d not find\n",
+				clock_type, enable);
+	}
+#endif
+
+}
+
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+#if defined(HPPE) || defined(MP)
+struct clk_uniphy {
+	struct clk_hw hw;
+	u8 uniphy_index;
+	u8 dir;
+	unsigned long rate;
+};
+
+#define to_clk_uniphy(_hw) container_of(_hw, struct clk_uniphy, hw)
+
+static unsigned long
+uniphy_clks_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+	struct clk_uniphy *uniphy = to_clk_uniphy(hw);
+
+	return uniphy->rate;
+}
+
+static int
+uniphy_clks_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
+{
+	/* add logic for checking the current mode */
+	if (req->rate <= UNIPHY_CLK_RATE_125M)
+		req->rate = UNIPHY_CLK_RATE_125M;
+	else
+		req->rate = UNIPHY_CLK_RATE_312M;
+
+	return 0;
+}
+
+static int
+uniphy_clks_set_rate(struct clk_hw *hw, unsigned long rate,
+		     unsigned long parent_rate)
+{
+	struct clk_uniphy *uniphy = to_clk_uniphy(hw);
+
+	if (rate != UNIPHY_CLK_RATE_125M && rate != UNIPHY_CLK_RATE_312M)
+		return -1;
+
+	uniphy->rate = rate;
+
+	return 0;
+}
+
+static const struct clk_ops clk_uniphy_ops = {
+	.recalc_rate = uniphy_clks_recalc_rate,
+	.determine_rate = uniphy_clks_determine_rate,
+	.set_rate = uniphy_clks_set_rate,
+};
+#endif
+
+#if defined(HPPE)
+
+static struct clk_uniphy uniphy0_gcc_rx_clk = {
+                .hw.init = &(struct clk_init_data){
+                        .name = "uniphy0_gcc_rx_clk",
+                        .ops = &clk_uniphy_ops,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0))
+			.flags = CLK_IS_ROOT,
+#endif
+                },
+		.uniphy_index = 0,
+		.dir = UNIPHY_RX,
+		.rate = UNIPHY_DEFAULT_RATE,
+};
+
+static struct clk_uniphy uniphy0_gcc_tx_clk = {
+                .hw.init = &(struct clk_init_data){
+                        .name = "uniphy0_gcc_tx_clk",
+                        .ops = &clk_uniphy_ops,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0))
+			.flags = CLK_IS_ROOT,
+#endif
+                },
+		.uniphy_index = 0,
+		.dir = UNIPHY_TX,
+		.rate = UNIPHY_DEFAULT_RATE,
+};
+
+static struct clk_uniphy uniphy1_gcc_rx_clk = {
+                .hw.init = &(struct clk_init_data){
+                        .name = "uniphy1_gcc_rx_clk",
+                        .ops = &clk_uniphy_ops,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0))
+			.flags = CLK_IS_ROOT,
+#endif
+                },
+		.uniphy_index = 1,
+		.dir = UNIPHY_RX,
+		.rate = UNIPHY_DEFAULT_RATE,
+};
+
+static struct clk_uniphy uniphy1_gcc_tx_clk = {
+                .hw.init = &(struct clk_init_data){
+                        .name = "uniphy1_gcc_tx_clk",
+                        .ops = &clk_uniphy_ops,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0))
+			.flags = CLK_IS_ROOT,
+#endif
+                },
+		.uniphy_index = 1,
+		.dir = UNIPHY_TX,
+		.rate = UNIPHY_DEFAULT_RATE,
+};
+
+static struct clk_uniphy uniphy2_gcc_rx_clk = {
+                .hw.init = &(struct clk_init_data){
+                        .name = "uniphy2_gcc_rx_clk",
+                        .ops = &clk_uniphy_ops,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0))
+			.flags = CLK_IS_ROOT,
+#endif
+                },
+		.uniphy_index = 2,
+		.dir = UNIPHY_RX,
+		.rate = UNIPHY_DEFAULT_RATE,
+};
+
+static struct clk_uniphy uniphy2_gcc_tx_clk = {
+                .hw.init = &(struct clk_init_data){
+                        .name = "uniphy2_gcc_tx_clk",
+                        .ops = &clk_uniphy_ops,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0))
+			.flags = CLK_IS_ROOT,
+#endif
+                },
+		.uniphy_index = 2,
+		.dir = UNIPHY_TX,
+		.rate = UNIPHY_DEFAULT_RATE,
+};
+
+static struct clk_hw *uniphy_raw_clks[SSDK_MAX_UNIPHY_INSTANCE * 2] = {
+	&uniphy0_gcc_rx_clk.hw, &uniphy0_gcc_tx_clk.hw,
+	&uniphy1_gcc_rx_clk.hw, &uniphy1_gcc_tx_clk.hw,
+	&uniphy2_gcc_rx_clk.hw, &uniphy2_gcc_tx_clk.hw,
+};
+
+static char *ppe_clk_ids[UNIPHYT_CLK_MAX] = {
+	NSS_PORT1_RX_CLK,
+	NSS_PORT1_TX_CLK,
+	NSS_PORT2_RX_CLK,
+	NSS_PORT2_TX_CLK,
+	NSS_PORT3_RX_CLK,
+	NSS_PORT3_TX_CLK,
+	NSS_PORT4_RX_CLK,
+	NSS_PORT4_TX_CLK,
+	NSS_PORT5_RX_CLK,
+	NSS_PORT5_TX_CLK,
+	NSS_PORT6_RX_CLK,
+	NSS_PORT6_TX_CLK,
+	UNIPHY0_PORT1_RX_CLK,
+	UNIPHY0_PORT1_TX_CLK,
+	UNIPHY0_PORT2_RX_CLK,
+	UNIPHY0_PORT2_TX_CLK,
+	UNIPHY0_PORT3_RX_CLK,
+	UNIPHY0_PORT3_TX_CLK,
+	UNIPHY0_PORT4_RX_CLK,
+	UNIPHY0_PORT4_TX_CLK,
+	UNIPHY0_PORT5_RX_CLK,
+	UNIPHY0_PORT5_TX_CLK,
+	UNIPHY1_PORT5_RX_CLK,
+	UNIPHY1_PORT5_TX_CLK,
+	UNIPHY2_PORT6_RX_CLK,
+	UNIPHY2_PORT6_TX_CLK,
+	PORT5_RX_SRC,
+	PORT5_TX_SRC
+};
+
+static void ssdk_ppe_uniphy_clock_init(a_uint32_t revision)
+{
+	a_uint32_t i, inst_num;
+	struct clk *clk;
+
+	if (revision == HPPE_REVISION) {
+		inst_num = SSDK_MAX_UNIPHY_INSTANCE;
+	} else {
+		inst_num = SSDK_MAX_UNIPHY_INSTANCE - 1;
+	}
+
+	for (i = 0; i < inst_num * 2; i++) {
+		clk = clk_register(NULL, uniphy_raw_clks[i]);
+		if (IS_ERR(clk))
+			SSDK_ERROR("Clk register %d fail!\n", i);
+	}
+
+	for (i = NSS_PORT1_RX_CLK_E; i < UNIPHYT_CLK_MAX; i++)
+		uniphy_port_clks[i] = of_clk_get_by_name(clock_node,
+							ppe_clk_ids[i]);
+
+	/* enable uniphy and mac clock */
+	for (i = NSS_PORT1_RX_CLK_E; i < PORT5_RX_SRC_E; i++)
+		ssdk_uniphy_clock_enable(0, i, A_TRUE);
+}
+
+static void ssdk_ppe_fixed_clock_init(a_uint32_t revision)
+{
+	/* AHB and sys clk */
+	ssdk_clock_rate_set_and_enable(clock_node, CMN_AHB_CLK, 0);
+	ssdk_clock_rate_set_and_enable(clock_node, CMN_SYS_CLK, 0);
+	ssdk_clock_rate_set_and_enable(clock_node, UNIPHY0_AHB_CLK,
+					UNIPHY_AHB_CLK_RATE);
+	if (revision == HPPE_REVISION) {
+		ssdk_clock_rate_set_and_enable(clock_node,
+					UNIPHY0_SYS_CLK,
+					UNIPHY_SYS_CLK_RATE);
+	} else {
+		ssdk_clock_rate_set_and_enable(clock_node,
+					UNIPHY0_SYS_CLK,
+					CPPE_UNIPHY_SYS_CLK_RATE);
+	}
+	ssdk_clock_rate_set_and_enable(clock_node, UNIPHY1_AHB_CLK,
+					UNIPHY_AHB_CLK_RATE);
+	if (revision == HPPE_REVISION) {
+		ssdk_clock_rate_set_and_enable(clock_node,
+					UNIPHY1_SYS_CLK,
+					UNIPHY_SYS_CLK_RATE);
+	} else {
+		ssdk_clock_rate_set_and_enable(clock_node,
+					UNIPHY1_SYS_CLK,
+					CPPE_UNIPHY_SYS_CLK_RATE);
+	}
+	if (revision == HPPE_REVISION) {
+		ssdk_clock_rate_set_and_enable(clock_node,
+					UNIPHY2_AHB_CLK,
+					UNIPHY_AHB_CLK_RATE);
+		ssdk_clock_rate_set_and_enable(clock_node,
+					UNIPHY2_SYS_CLK,
+					UNIPHY_SYS_CLK_RATE);
+	}
+
+	/* ppe related fixed clock init */
+	ssdk_clock_rate_set_and_enable(clock_node,
+					PORT1_MAC_CLK, PPE_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+					PORT2_MAC_CLK, PPE_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+					PORT3_MAC_CLK, PPE_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+					PORT4_MAC_CLK, PPE_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+					PORT5_MAC_CLK, PPE_CLK_RATE);
+	if (revision == HPPE_REVISION) {
+		ssdk_clock_rate_set_and_enable(clock_node,
+					PORT6_MAC_CLK, PPE_CLK_RATE);
+	}
+	ssdk_clock_rate_set_and_enable(clock_node,
+					NSS_PPE_CLK, PPE_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+					NSS_PPE_CFG_CLK, PPE_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+					NSSNOC_PPE_CLK, PPE_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+					NSSNOC_PPE_CFG_CLK, PPE_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+					NSS_EDMA_CLK, PPE_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+					NSS_EDMA_CFG_CLK, PPE_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+					NSS_PPE_IPE_CLK, PPE_CLK_RATE);
+	if (revision == HPPE_REVISION) {
+		ssdk_clock_rate_set_and_enable(clock_node,
+					NSS_PPE_BTQ_CLK, PPE_CLK_RATE);
+	}
+	ssdk_clock_rate_set_and_enable(clock_node,
+					MDIO_AHB_CLK, MDIO_AHB_RATE);
+	if (revision == HPPE_REVISION) {
+		ssdk_clock_rate_set_and_enable(clock_node,
+					NSSNOC_CLK, NSS_NOC_RATE);
+	} else {
+		ssdk_clock_rate_set_and_enable(clock_node,
+					NSSNOC_CLK, NSSNOC_SNOC_RATE);
+	}
+	ssdk_clock_rate_set_and_enable(clock_node,
+					NSSNOC_SNOC_CLK, NSSNOC_SNOC_RATE);
+	if (revision == HPPE_REVISION) {
+		ssdk_clock_rate_set_and_enable(clock_node,
+					MEM_NOC_NSSAXI_CLK, NSS_AXI_RATE);
+	}
+	ssdk_clock_rate_set_and_enable(clock_node,
+					CRYPTO_PPE_CLK, PPE_CLK_RATE);
+	if (revision == HPPE_REVISION) {
+		ssdk_clock_rate_set_and_enable(clock_node,
+					NSS_IMEM_CLK, NSS_IMEM_RATE);
+	}
+	ssdk_clock_rate_set_and_enable(clock_node,
+					NSS_PTP_REF_CLK, PTP_REF_RARE);
+	if (revision == CPPE_REVISION) {
+		ssdk_clock_rate_set_and_enable(clock_node,
+					SNOC_NSSNOC_CLK, NSSNOC_SNOC_RATE);
+	}
+}
+#endif
+
+#if defined(MP)
+#define TCSR_ETH_ADDR               0x19475C0
+#define TCSR_ETH_SIZE               0x4
+#define TCSR_GEPHY_LDO_BIAS_EN      0
+#define TCSR_ETH_LDO_RDY            0x4
+
+#define GEPHY_LDO_BIAS_EN           0x1
+#define ETH_LDO_RDY                 0x1
+#define CMN_PLL_LOCKED_ADDR         0x9B064
+#define CMN_PLL_LOCKED_SIZE         0x4
+#define CMN_PLL_LOCKED              0x4
+#define MP_RAW_CLOCK_INSTANCE       0x2
+
+static char *mp_rst_ids[MP_BCR_RST_MAX] = {
+	GEHPY_BCR_RESET_ID,
+	UNIPHY_BCR_RESET_ID,
+	GMAC0_BCR_RESET_ID,
+	GMAC1_BCR_RESET_ID,
+	GEPHY_MISC_RESET_ID
+};
+
+static struct clk_uniphy gephy_gcc_rx_clk = {
+	.hw.init = &(struct clk_init_data){
+	.name = "gephy_gcc_rx",
+	.ops = &clk_uniphy_ops,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0))
+	.flags = CLK_IS_ROOT,
+#endif
+	},
+	.uniphy_index = 0,
+	.dir = UNIPHY_RX,
+	.rate = UNIPHY_DEFAULT_RATE,
+};
+
+static struct clk_uniphy gephy_gcc_tx_clk = {
+	.hw.init = &(struct clk_init_data){
+	.name = "gephy_gcc_tx",
+	.ops = &clk_uniphy_ops,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0))
+	.flags = CLK_IS_ROOT,
+#endif
+	},
+	.uniphy_index = 0,
+	.dir = UNIPHY_TX,
+	.rate = UNIPHY_DEFAULT_RATE,
+};
+
+static struct clk_uniphy uniphy_gcc_rx_clk = {
+	.hw.init = &(struct clk_init_data){
+	.name = "uniphy_gcc_rx",
+	.ops = &clk_uniphy_ops,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0))
+	.flags = CLK_IS_ROOT,
+#endif
+	},
+	.uniphy_index = 1,
+	.dir = UNIPHY_RX,
+	.rate = UNIPHY_DEFAULT_RATE,
+};
+
+static struct clk_uniphy uniphy_gcc_tx_clk = {
+	.hw.init = &(struct clk_init_data){
+	.name = "uniphy_gcc_tx",
+	.ops = &clk_uniphy_ops,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0))
+	.flags = CLK_IS_ROOT,
+#endif
+	},
+	.uniphy_index = 1,
+	.dir = UNIPHY_TX,
+	.rate = UNIPHY_DEFAULT_RATE,
+};
+
+static struct clk_hw *mp_raw_clks[MP_RAW_CLOCK_INSTANCE * 2] = {
+	&gephy_gcc_rx_clk.hw, &gephy_gcc_tx_clk.hw,
+	&uniphy_gcc_rx_clk.hw, &uniphy_gcc_tx_clk.hw,
+};
+
+static void ssdk_mp_fixed_clock_init(void)
+{
+	ssdk_clock_rate_set_and_enable(clock_node, CMN_AHB_CLK, 0);
+	ssdk_clock_rate_set_and_enable(clock_node, CMN_SYS_CLK, 0);
+	ssdk_clock_rate_set_and_enable(clock_node, UNIPHY_AHB_CLK,
+				UNIPHY_AHB_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+				UNIPHY_SYS_CLK,
+				MP_UNIPHY_SYS_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+				MDIO0_AHB_CLK, MDIO_AHB_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+				MDIO1_AHB_CLK, MDIO_AHB_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+				GMAC0_CFG_CLK, GMAC_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+				GMAC0_SYS_CLK, GMAC_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+				GMAC1_CFG_CLK, GMAC_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+				GMAC1_SYS_CLK, GMAC_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+				GMAC0_PTP_CLK, GMAC_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+				GMAC1_PTP_CLK, GMAC_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+				SNOC_GMAC0_AHB_CLK, GMAC_CLK_RATE);
+	ssdk_clock_rate_set_and_enable(clock_node,
+				SNOC_GMAC1_AHB_CLK, GMAC_CLK_RATE);
+}
+
+static void ssdk_mp_uniphy_clock_init(void)
+{
+	a_uint32_t i, inst_num;
+	struct clk *clk;
+	struct clk **ports;
+
+	inst_num = sizeof(mp_raw_clks) / sizeof(struct clk_hw *);
+
+	for (i = 0; i < inst_num; i++) {
+		clk = clk_register(NULL, mp_raw_clks[i]);
+		if (IS_ERR(clk))
+			SSDK_ERROR("Clk register %d fail!\n", i);
+	}
+
+	ports = uniphy_port_clks;
+	ports[NSS_PORT1_RX_CLK_E] = of_clk_get_by_name(clock_node,
+					NSS_PORT1_RX_CLK);
+	ports[NSS_PORT1_TX_CLK_E] = of_clk_get_by_name(clock_node,
+					NSS_PORT1_TX_CLK);
+	ports[NSS_PORT2_RX_CLK_E] = of_clk_get_by_name(clock_node,
+					NSS_PORT2_RX_CLK);
+	ports[NSS_PORT2_TX_CLK_E] = of_clk_get_by_name(clock_node,
+					NSS_PORT2_TX_CLK);
+	ports[UNIPHY0_PORT1_RX_CLK_E] = of_clk_get_by_name(clock_node,
+					UNIPHY0_PORT1_RX_CLK);
+	ports[UNIPHY0_PORT1_TX_CLK_E] = of_clk_get_by_name(clock_node,
+					UNIPHY0_PORT1_TX_CLK);
+	ports[UNIPHY1_PORT5_RX_CLK_E] = of_clk_get_by_name(clock_node,
+					UNIPHY1_PORT5_RX_CLK);
+	ports[UNIPHY1_PORT5_TX_CLK_E] = of_clk_get_by_name(clock_node,
+					UNIPHY1_PORT5_TX_CLK);
+}
+
+static void ssdk_mp_uniphy_clock_enable(void)
+{
+	ssdk_uniphy_clock_enable(0, NSS_PORT1_RX_CLK_E, A_TRUE);
+	ssdk_uniphy_clock_enable(0, NSS_PORT1_TX_CLK_E, A_TRUE);
+	ssdk_uniphy_clock_enable(0, NSS_PORT2_RX_CLK_E, A_TRUE);
+	ssdk_uniphy_clock_enable(0, NSS_PORT2_TX_CLK_E, A_TRUE);
+	ssdk_uniphy_clock_enable(0, UNIPHY0_PORT1_RX_CLK_E, A_TRUE);
+	ssdk_uniphy_clock_enable(0, UNIPHY0_PORT1_TX_CLK_E, A_TRUE);
+	ssdk_uniphy_clock_enable(0, UNIPHY1_PORT5_RX_CLK_E, A_TRUE);
+	ssdk_uniphy_clock_enable(0, UNIPHY1_PORT5_TX_CLK_E, A_TRUE);
+}
+
+static void
+ssdk_mp_tcsr_get(a_uint32_t tcsr_offset, a_uint32_t *tcsr_val)
+{
+	void __iomem *tcsr_base = NULL;
+
+	tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE);
+	if (!tcsr_base)
+	{
+		SSDK_ERROR("Failed to map tcsr eth address!\n");
+		return;
+	}
+	*tcsr_val = readl(tcsr_base + tcsr_offset);
+	iounmap(tcsr_base);
+
+	return;
+}
+
+static void
+ssdk_mp_tcsr_set(a_uint32_t tcsr_offset, a_uint32_t tcsr_val)
+{
+	void __iomem *tcsr_base = NULL;
+
+	tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE);
+	if (!tcsr_base)
+	{
+		SSDK_ERROR("Failed to map tcsr eth address!\n");
+		return;
+	}
+	writel(tcsr_val, tcsr_base + tcsr_offset);
+	iounmap(tcsr_base);
+
+	return;
+}
+
+static void
+ssdk_mp_cmnblk_enable(void)
+{
+	a_uint32_t reg_val;
+
+	ssdk_mp_tcsr_get(TCSR_ETH_LDO_RDY, &reg_val);
+	reg_val |= ETH_LDO_RDY;
+	ssdk_mp_tcsr_set(TCSR_ETH_LDO_RDY, reg_val);
+
+	return;
+}
+
+void
+ssdk_mp_gephy_icc_efuse_load_enable(a_bool_t enable)
+{
+	a_uint32_t reg_val;
+
+	ssdk_mp_tcsr_get(TCSR_GEPHY_LDO_BIAS_EN, &reg_val);
+	if(!enable)
+	{
+		reg_val |= GEPHY_LDO_BIAS_EN;
+	}
+	else
+	{
+		reg_val &= ~GEPHY_LDO_BIAS_EN;
+	}
+	ssdk_mp_tcsr_set(TCSR_GEPHY_LDO_BIAS_EN, reg_val);
+}
+
+static a_bool_t
+ssdk_mp_cmnblk_stable_check(void)
+{
+	void __iomem *pll_lock = NULL;
+	a_uint32_t reg_val;
+	int i, loops = 20;
+
+	pll_lock = ioremap_nocache(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE);
+	if (!pll_lock) {
+		SSDK_ERROR("Failed to map CMN PLL LOCK register!\n");
+		return A_FALSE;
+	}
+
+	for (i = 0; i < loops; i++) {
+		reg_val = readl(pll_lock);
+		if (reg_val & CMN_PLL_LOCKED) {
+			break;
+		}
+		msleep(10);
+	}
+
+	iounmap(pll_lock);
+
+	if (i >= loops) {
+		return A_FALSE;
+	} else {
+		return A_TRUE;
+	}
+}
+
+static void
+ssdk_mp_reset_init(void)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	struct reset_control *rst;
+	a_uint32_t i;
+
+	rst_node = of_find_node_by_name(NULL, "ess-switch");
+
+	for (i = 0; i < MP_BCR_RST_MAX; i++) {
+		rst = of_reset_control_get(rst_node, mp_rst_ids[i]);
+		if (IS_ERR(rst)) {
+			SSDK_ERROR("%s not exist!\n", mp_rst_ids[i]);
+			return;
+		}
+		ssdk_gcc_reset(rst, SSDK_RESET_ASSERT);
+		msleep(200);
+		ssdk_gcc_reset(rst, SSDK_RESET_DEASSERT);
+		msleep(200);
+		reset_control_put(rst);
+	}
+
+	i = UNIPHY1_SOFT_RESET_E;
+	uniphy_rsts[i] = of_reset_control_get(rst_node, UNIPHY1_SOFT_RESET_ID);
+
+	SSDK_INFO("MP reset successfully!\n");
+#endif
+}
+
+static void ssdk_cmnblk_pll_src_set(enum cmnblk_pll_src_type pll_source)
+{
+	void __iomem *cmn_pll_src_base = NULL;
+	a_uint32_t reg_val;
+
+	cmn_pll_src_base = ioremap_nocache(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE);
+	if (!cmn_pll_src_base) {
+		SSDK_ERROR("Failed to map cmn pll source address!\n");
+		return;
+	}
+	reg_val = readl(cmn_pll_src_base);
+	reg_val = (reg_val & PLL_CTRL_SRC_MASK) | (pll_source << 0x8);
+	writel(reg_val, cmn_pll_src_base);
+	iounmap(cmn_pll_src_base);
+
+	return;
+}
+#endif
+#endif
+
+#if defined(HPPE) || defined(MP)
+static void ssdk_cmnblk_init(enum cmnblk_clk_type mode)
+{
+	void __iomem *gcc_pll_base = NULL;
+	a_uint32_t reg_val;
+
+	gcc_pll_base = ioremap_nocache(CMN_BLK_ADDR, CMN_BLK_SIZE);
+	if (!gcc_pll_base) {
+		SSDK_ERROR("Failed to map gcc pll address!\n");
+		return;
+	}
+	reg_val = readl(gcc_pll_base + 4);
+
+	switch (mode) {
+		case INTERNAL_48MHZ:
+			reg_val = (reg_val & FREQUENCY_MASK) | INTERNAL_48MHZ_CLOCK;
+			break;
+		case EXTERNAL_50MHZ:
+			reg_val = (reg_val & FREQUENCY_MASK) | EXTERNAL_50MHZ_CLOCK;
+			break;
+		case EXTERNAL_25MHZ:
+			reg_val = (reg_val & FREQUENCY_MASK) | EXTERNAL_25MHZ_CLOCK;
+			break;
+		case EXTERNAL_31250KHZ:
+			reg_val = (reg_val & FREQUENCY_MASK) | EXTERNAL_31250KHZ_CLOCK;
+			break;
+		case EXTERNAL_40MHZ:
+			reg_val = (reg_val & FREQUENCY_MASK) | EXTERNAL_40MHZ_CLOCK;
+			break;
+		case EXTERNAL_48MHZ:
+			reg_val = (reg_val & FREQUENCY_MASK) | EXTERNAL_48MHZ_CLOCK;
+			break;
+#if defined(MP)
+		case INTERNAL_96MHZ:
+			ssdk_cmnblk_pll_src_set(CMN_BLK_PLL_SRC_SEL_FROM_REG);
+			reg_val = (reg_val & PLL_REFCLK_DIV_MASK) | PLL_REFCLK_DIV_2;
+			break;
+#endif
+		default:
+			return;
+	}
+
+	writel(reg_val, gcc_pll_base + 0x4);
+	reg_val = readl(gcc_pll_base);
+	reg_val = reg_val | 0x40;
+	writel(reg_val, gcc_pll_base);
+	msleep(1);
+	reg_val = reg_val & (~0x40);
+	writel(reg_val, gcc_pll_base);
+	msleep(1);
+	writel(0xbf, gcc_pll_base);
+	msleep(1);
+	writel(0xff, gcc_pll_base);
+	msleep(1);
+
+	iounmap(gcc_pll_base);
+}
+
+void ssdk_port_mac_clock_reset(
+	a_uint32_t dev_id,
+	a_uint32_t port_id)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	ssdk_port_reset(dev_id, port_id, SSDK_RESET_ASSERT);
+	msleep(150);
+	ssdk_port_reset(dev_id, port_id, SSDK_RESET_DEASSERT);
+	msleep(150);
+#endif
+	return;
+}
+#endif
+
+#if defined(HPPE)
+static
+void ssdk_uniphy1_clock_source_set(void)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	clk_set_parent(uniphy_port_clks[PORT5_RX_SRC_E],
+			uniphy_raw_clks[2]->clk);
+	clk_set_parent(uniphy_port_clks[PORT5_TX_SRC_E],
+			uniphy_raw_clks[3]->clk);
+#endif
+}
+
+void ssdk_uniphy_raw_clock_reset(a_uint8_t uniphy_index)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	a_uint32_t id;
+
+	if (uniphy_index >= SSDK_MAX_UNIPHY_INSTANCE)
+		return;
+
+	id = uniphy_index*2;
+	if (clk_set_rate(uniphy_raw_clks[id]->clk, UNIPHY_DEFAULT_RATE))
+		SSDK_ERROR("set rate for %d fail!\n", id);
+	if (clk_set_rate(uniphy_raw_clks[id+1]->clk, UNIPHY_DEFAULT_RATE))
+		SSDK_ERROR("set rate for %d fail!\n", id+1);
+#endif
+}
+
+void ssdk_uniphy_raw_clock_set(
+	a_uint8_t uniphy_index,
+	a_uint8_t direction,
+	a_uint32_t clock)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	a_uint32_t old_clock, id, mode;
+
+	if ((uniphy_index >= SSDK_MAX_UNIPHY_INSTANCE) ||
+	     (direction > UNIPHY_TX) ||
+	     (clock != UNIPHY_CLK_RATE_125M &&
+	      clock != UNIPHY_CLK_RATE_312M))
+		return;
+
+	id = uniphy_index*2 + direction;
+	old_clock = clk_get_rate(uniphy_raw_clks[id]->clk);
+
+	if (clock != old_clock) {
+		if (uniphy_index == SSDK_UNIPHY_INSTANCE1) {
+			if (UNIPHY_RX == direction)
+				ssdk_uniphy_clock_rate_set(0,
+						NSS_PORT5_RX_CLK_E,
+						NSS_PORT5_DFLT_RATE);
+			else
+				ssdk_uniphy_clock_rate_set(0,
+						NSS_PORT5_TX_CLK_E,
+						NSS_PORT5_DFLT_RATE);
+		}
+		if (clk_set_rate(uniphy_raw_clks[id]->clk, clock))
+			SSDK_ERROR("set rate: %d fail!\n", clock);
+	}
+
+	mode = ssdk_dt_global_get_mac_mode(0, SSDK_UNIPHY_INSTANCE1);
+	if (((uniphy_index == SSDK_UNIPHY_INSTANCE0) &&
+	     (mode == PORT_INTERFACE_MODE_MAX)) ||
+	    (uniphy_index == SSDK_UNIPHY_INSTANCE1)) {
+		if (clk_set_parent(uniphy_port_clks[PORT5_RX_SRC_E + direction],
+				uniphy_raw_clks[id]->clk))
+			SSDK_ERROR("set parent fail!\n");
+	}
+#endif
+}
+
+void ssdk_uniphy_port5_clock_source_set(void)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	a_uint32_t id, mode, i;
+
+	mode = ssdk_dt_global_get_mac_mode(0, SSDK_UNIPHY_INSTANCE1);
+
+	for (i = UNIPHY_RX; i <= UNIPHY_TX; i++) {
+		if (mode == PORT_INTERFACE_MODE_MAX) {
+			id = SSDK_UNIPHY_INSTANCE0*2 + i;
+		} else {
+			id = SSDK_UNIPHY_INSTANCE1*2 + i;
+		}
+		if (clk_set_parent(uniphy_port_clks[PORT5_RX_SRC_E + i],
+			uniphy_raw_clks[id]->clk)) {
+			SSDK_ERROR("set parent fail!\n");
+		}
+	}
+#endif
+}
+
+static
+void ssdk_gcc_ppe_clock_init(a_uint32_t revision, enum cmnblk_clk_type mode)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	ssdk_ppe_fixed_clock_init(revision);
+	/*fixme for cmn clock init*/
+	ssdk_cmnblk_init(mode);
+	ssdk_ppe_uniphy_clock_init(revision);
+	ssdk_uniphy_port5_clock_source_set();
+#endif
+}
+#endif
+
+#if defined(MP)
+void ssdk_gcc_mp_clock_init(enum cmnblk_clk_type mode)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	ssdk_mp_fixed_clock_init();
+	ssdk_mp_uniphy_clock_init();
+	ssdk_cmnblk_init(mode);
+	msleep(200);
+	ssdk_mp_cmnblk_enable();
+	if (ssdk_mp_cmnblk_stable_check()) {
+		ssdk_mp_reset_init();
+		ssdk_mp_uniphy_clock_enable();
+	} else {
+		SSDK_ERROR("Cmnblock is still not stable!\n");
+	}
+#endif
+}
+
+void ssdk_mp_raw_clock_set(
+	a_uint8_t uniphy_index,
+	a_uint8_t direction,
+	a_uint32_t clock)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	a_uint32_t old_clock, id;
+
+	if ((uniphy_index >= MP_RAW_CLOCK_INSTANCE) ||
+	     (direction > UNIPHY_TX) ||
+	     (clock != UNIPHY_CLK_RATE_125M &&
+	      clock != UNIPHY_CLK_RATE_312M))
+		return;
+
+	if(ssdk_is_emulation(0)){
+		SSDK_INFO("uniphy_index %d direction %d clock %d on emulation platform\n",
+					uniphy_index, direction, clock);
+		return;
+	}
+
+	id = uniphy_index*2 + direction;
+	old_clock = clk_get_rate(mp_raw_clks[id]->clk);
+
+	if (clock != old_clock) {
+		if (clk_set_rate(mp_raw_clks[id]->clk, clock))
+			SSDK_ERROR("set rate: %d fail!\n", clock);
+	}
+#endif
+}
+
+#endif
+
+#if defined(HPPE) || defined(MP)
+void ssdk_gcc_clock_init(void)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	enum cmnblk_clk_type cmnblk_clk_mode = INTERNAL_48MHZ;
+	a_uint8_t *mode = NULL;
+
+	clock_node = of_find_node_by_name(NULL, "ess-switch");
+	if (of_property_read_string(clock_node, "cmnblk_clk",
+				    (const char **)&mode)) {
+		cmnblk_clk_mode = INTERNAL_48MHZ;
+	} else {
+		if (!strcmp(mode, "external_50MHz")) {
+			cmnblk_clk_mode = EXTERNAL_50MHZ;
+		} else if (!strcmp(mode, "external_25MHz")) {
+			cmnblk_clk_mode = EXTERNAL_25MHZ;
+		} else if (!strcmp(mode, "external_31250KHz")) {
+			cmnblk_clk_mode = EXTERNAL_31250KHZ;
+		} else if (!strcmp(mode, "external_40MHz")) {
+			cmnblk_clk_mode = EXTERNAL_40MHZ;
+		} else if (!strcmp(mode, "external_48MHz")) {
+			cmnblk_clk_mode = EXTERNAL_48MHZ;
+		} else if (!strcmp(mode, "internal_96MHz")) {
+			cmnblk_clk_mode = INTERNAL_96MHZ;
+		}
+	}
+
+	if (of_device_is_compatible(clock_node, "qcom,ess-switch-ipq807x")) {
+#if defined(HPPE)
+		ssdk_gcc_ppe_clock_init(HPPE_REVISION, cmnblk_clk_mode);
+#endif
+	} else if (of_device_is_compatible(clock_node,
+			"qcom,ess-switch-ipq60xx")) {
+#if defined(HPPE)
+		ssdk_gcc_ppe_clock_init(CPPE_REVISION, cmnblk_clk_mode);
+#endif
+	} else if (of_device_is_compatible(clock_node,
+			"qcom,ess-switch-ipq50xx")) {
+#if defined(MP)
+		ssdk_gcc_mp_clock_init(cmnblk_clk_mode);
+#endif
+	}
+#endif
+	SSDK_INFO("SSDK gcc clock init successfully!\n");
+}
+
+void
+qca_gcc_uniphy_port_clock_set(
+	a_uint32_t dev_id, a_uint32_t uniphy_index,
+	a_uint32_t port_id, a_bool_t enable)
+{
+
+	if (uniphy_index == SSDK_UNIPHY_INSTANCE2) {
+		ssdk_uniphy_clock_enable(dev_id,
+					UNIPHY2_PORT6_RX_CLK_E, enable);
+		ssdk_uniphy_clock_enable(dev_id,
+					UNIPHY2_PORT6_TX_CLK_E, enable);
+	} else if (uniphy_index == SSDK_UNIPHY_INSTANCE1) {
+		ssdk_uniphy_clock_enable(dev_id,
+					UNIPHY1_PORT5_RX_CLK_E, enable);
+		ssdk_uniphy_clock_enable(dev_id,
+					UNIPHY1_PORT5_TX_CLK_E, enable);
+	} else if (uniphy_index == SSDK_UNIPHY_INSTANCE0) {
+		switch (port_id) {
+			case SSDK_PHYSICAL_PORT1:
+				ssdk_uniphy_clock_enable(dev_id,
+							UNIPHY0_PORT1_RX_CLK_E,
+							enable);
+				ssdk_uniphy_clock_enable(dev_id,
+							UNIPHY0_PORT1_TX_CLK_E,
+							enable);
+				break;
+			case SSDK_PHYSICAL_PORT2:
+				ssdk_uniphy_clock_enable(dev_id,
+							UNIPHY0_PORT2_RX_CLK_E,
+							enable);
+				ssdk_uniphy_clock_enable(dev_id,
+							UNIPHY0_PORT2_TX_CLK_E,
+							enable);
+				break;
+			case SSDK_PHYSICAL_PORT3:
+				ssdk_uniphy_clock_enable(dev_id,
+							UNIPHY0_PORT3_RX_CLK_E,
+							enable);
+				ssdk_uniphy_clock_enable(dev_id,
+							UNIPHY0_PORT3_TX_CLK_E,
+							enable);
+				break;
+			case SSDK_PHYSICAL_PORT4:
+				ssdk_uniphy_clock_enable(dev_id,
+							UNIPHY0_PORT4_RX_CLK_E,
+							enable);
+				ssdk_uniphy_clock_enable(dev_id,
+							UNIPHY0_PORT4_TX_CLK_E,
+							enable);
+				break;
+			case SSDK_PHYSICAL_PORT5:
+				ssdk_uniphy_clock_enable(dev_id,
+							UNIPHY0_PORT5_RX_CLK_E,
+							enable);
+				ssdk_uniphy_clock_enable(dev_id,
+							UNIPHY0_PORT5_TX_CLK_E,
+							enable);
+				break;
+			default:
+				break;
+		}
+	}
+}
+
+void
+qca_gcc_mac_port_clock_set(
+	a_uint32_t dev_id,
+	a_uint32_t port_id,
+	a_bool_t enable)
+{
+
+	switch (port_id) {
+		case SSDK_PHYSICAL_PORT1:
+			ssdk_uniphy_clock_enable(dev_id,
+						NSS_PORT1_RX_CLK_E,
+						enable);
+			ssdk_uniphy_clock_enable(dev_id,
+						NSS_PORT1_TX_CLK_E,
+						enable);
+			break;
+		case SSDK_PHYSICAL_PORT2:
+			ssdk_uniphy_clock_enable(dev_id,
+						NSS_PORT2_RX_CLK_E,
+						enable);
+			ssdk_uniphy_clock_enable(dev_id,
+						NSS_PORT2_TX_CLK_E,
+						enable);
+			break;
+		case SSDK_PHYSICAL_PORT3:
+			ssdk_uniphy_clock_enable(dev_id,
+						NSS_PORT3_RX_CLK_E,
+						enable);
+			ssdk_uniphy_clock_enable(dev_id,
+						NSS_PORT3_TX_CLK_E,
+						enable);
+			break;
+		case SSDK_PHYSICAL_PORT4:
+			ssdk_uniphy_clock_enable(dev_id,
+						NSS_PORT4_RX_CLK_E,
+						enable);
+			ssdk_uniphy_clock_enable(dev_id,
+						NSS_PORT4_TX_CLK_E,
+						enable);
+			break;
+		case SSDK_PHYSICAL_PORT5:
+			ssdk_uniphy_clock_enable(dev_id,
+						NSS_PORT5_RX_CLK_E,
+						enable);
+			ssdk_uniphy_clock_enable(dev_id,
+						NSS_PORT5_TX_CLK_E,
+						enable);
+			break;
+		case SSDK_PHYSICAL_PORT6:
+			ssdk_uniphy_clock_enable(dev_id,
+						NSS_PORT6_RX_CLK_E,
+						enable);
+			ssdk_uniphy_clock_enable(dev_id,
+						NSS_PORT6_TX_CLK_E,
+						enable);
+			break;
+		default:
+			break;
+	}
+}
+
+void
+ssdk_port_speed_clock_set(
+	a_uint32_t dev_id,
+	a_uint32_t port_id,
+	a_uint32_t rate)
+{
+#if defined(HPPE)
+	a_uint32_t mode = 0;
+#endif
+
+               switch (port_id ) {
+		case SSDK_PHYSICAL_PORT1:
+			ssdk_uniphy_clock_rate_set(dev_id,
+					NSS_PORT1_RX_CLK_E, rate);
+			ssdk_uniphy_clock_rate_set(dev_id,
+					NSS_PORT1_TX_CLK_E, rate);
+			break;
+		case SSDK_PHYSICAL_PORT2:
+			ssdk_uniphy_clock_rate_set(dev_id,
+					NSS_PORT2_RX_CLK_E, rate);
+			ssdk_uniphy_clock_rate_set(dev_id,
+					NSS_PORT2_TX_CLK_E, rate);
+			break;
+#if defined(HPPE)
+		case SSDK_PHYSICAL_PORT3:
+			ssdk_uniphy_clock_rate_set(dev_id,
+					NSS_PORT3_RX_CLK_E, rate);
+			ssdk_uniphy_clock_rate_set(dev_id,
+					NSS_PORT3_TX_CLK_E, rate);
+			break;
+		case SSDK_PHYSICAL_PORT4:
+			ssdk_uniphy_clock_rate_set(dev_id,
+					NSS_PORT4_RX_CLK_E, rate);
+			ssdk_uniphy_clock_rate_set(dev_id,
+					NSS_PORT4_TX_CLK_E, rate);
+			break;
+		case SSDK_PHYSICAL_PORT5:
+			ssdk_uniphy_clock_rate_set(dev_id,
+					NSS_PORT5_RX_CLK_E, rate);
+			ssdk_uniphy_clock_rate_set(dev_id,
+					NSS_PORT5_TX_CLK_E, rate);
+			mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1);
+			if (mode != PORT_INTERFACE_MODE_MAX)
+				ssdk_uniphy1_clock_source_set();
+			break;
+		case SSDK_PHYSICAL_PORT6:
+			ssdk_uniphy_clock_rate_set(dev_id,
+					NSS_PORT6_RX_CLK_E, rate);
+			ssdk_uniphy_clock_rate_set(dev_id,
+					NSS_PORT6_TX_CLK_E, rate);
+			break;
+#endif
+		default:
+			break;
+	}
+}
+#endif
+
+#if defined(HPPE)
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+static char *ppe_rst_ids[UNIPHY_RST_MAX] = {
+	UNIPHY0_SOFT_RESET_ID,
+	UNIPHY0_XPCS_RESET_ID,
+	UNIPHY1_SOFT_RESET_ID,
+	UNIPHY1_XPCS_RESET_ID,
+	UNIPHY2_SOFT_RESET_ID,
+	UNIPHY2_XPCS_RESET_ID,
+	UNIPHY0_PORT1_DISABLE_ID,
+	UNIPHY0_PORT2_DISABLE_ID,
+	UNIPHY0_PORT3_DISABLE_ID,
+	UNIPHY0_PORT4_DISABLE_ID,
+	UNIPHY0_PORT5_DISABLE_ID,
+	UNIPHY0_PORT_4_5_RESET_ID,
+	UNIPHY0_PORT_4_RESET_ID
+};
+static char *port_rst_ids[SSDK_MAX_PORT_NUM] = {
+	SSDK_PORT1_RESET_ID,
+	SSDK_PORT2_RESET_ID,
+	SSDK_PORT3_RESET_ID,
+	SSDK_PORT4_RESET_ID,
+	SSDK_PORT5_RESET_ID,
+	SSDK_PORT6_RESET_ID,
+	NULL, NULL
+};
+#endif
+
+void ssdk_ppe_reset_init(void)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+	struct reset_control *rst;
+	a_uint32_t i;
+
+	rst_node = of_find_node_by_name(NULL, "ess-switch");
+	rst = of_reset_control_get(rst_node, PPE_RESET_ID);
+	if (IS_ERR(rst)) {
+		SSDK_ERROR("%s not exist!\n", PPE_RESET_ID);
+		return;
+	}
+
+	ssdk_gcc_reset(rst, SSDK_RESET_ASSERT);
+	msleep(100);
+	ssdk_gcc_reset(rst, SSDK_RESET_DEASSERT);
+	msleep(100);
+	reset_control_put(rst);
+	SSDK_INFO("ppe reset successfully!\n");
+
+	for (i = UNIPHY0_SOFT_RESET_E; i < UNIPHY_RST_MAX; i++)
+		uniphy_rsts[i] = of_reset_control_get(rst_node,
+							ppe_rst_ids[i]);
+
+	for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT7; i++)
+		port_rsts[i-1] = of_reset_control_get(rst_node,
+							port_rst_ids[i-1]);
+#endif
+}
+
+void ssdk_gcc_uniphy_sys_set(a_uint32_t dev_id, a_uint32_t uniphy_index,
+	a_bool_t enable)
+{
+	enum unphy_rst_type rst_type;
+
+	if (of_device_is_compatible(clock_node, "qcom,ess-switch-ipq60xx")){
+		if (uniphy_index > SSDK_UNIPHY_INSTANCE1) {
+			return;
+		}
+	}
+
+	if (uniphy_index == SSDK_UNIPHY_INSTANCE0) {
+		rst_type = UNIPHY0_SOFT_RESET_E;
+	} else if (uniphy_index == SSDK_UNIPHY_INSTANCE1) {
+		rst_type = UNIPHY1_SOFT_RESET_E;
+	} else {
+		rst_type = UNIPHY2_SOFT_RESET_E;
+	}
+
+	if (enable == A_TRUE) {
+		ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_DEASSERT);
+	} else {
+		ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_ASSERT);
+	}
+
+	return;
+}
+#endif
+
diff --git a/qca-ssdk/src/init/ssdk_dts.c b/qca-ssdk/src/init/ssdk_dts.c
new file mode 100755
index 0000000..1710417
--- /dev/null
+++ b/qca-ssdk/src/init/ssdk_dts.c
@@ -0,0 +1,1207 @@
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include <linux/kconfig.h>
+#include <linux/types.h>
+#if defined(CONFIG_OF)
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_mdio.h>
+#include <linux/of_gpio.h>
+#endif
+#include <linux/etherdevice.h>
+#include <linux/clk.h>
+
+#include "ssdk_init.h"
+#include "ssdk_dts.h"
+#include "ssdk_plat.h"
+#include "hsl_phy.h"
+
+static ssdk_dt_global_t ssdk_dt_global = {0};
+#ifdef HPPE
+#ifdef IN_QOS
+a_uint8_t ssdk_tm_tick_mode_get(a_uint32_t dev_id)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return cfg->tm_tick_mode;
+}
+
+ssdk_dt_scheduler_cfg* ssdk_bootup_shceduler_cfg_get(a_uint32_t dev_id)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return &cfg->scheduler_cfg;
+}
+#endif
+#endif
+#ifdef IN_BM
+a_uint8_t ssdk_bm_tick_mode_get(a_uint32_t dev_id)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return cfg->bm_tick_mode;
+}
+#endif
+#ifdef IN_QM
+a_uint16_t ssdk_ucast_queue_start_get(a_uint32_t dev_id, a_uint32_t port)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return cfg->scheduler_cfg.pool[port].ucastq_start;
+}
+#endif
+a_uint32_t ssdk_intf_mac_num_get(void)
+{
+	return ssdk_dt_global.num_intf_mac;
+}
+
+a_uint8_t* ssdk_intf_macaddr_get(a_uint32_t index)
+{
+	return ssdk_dt_global.intf_mac[index].uc;
+}
+
+a_uint32_t ssdk_dt_global_get_mac_mode(a_uint32_t dev_id, a_uint32_t index)
+{
+	if (index == 0) {
+		return ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode;
+	}
+	if (index == 1) {
+		return ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode1;
+	}
+	if (index == 2) {
+		return ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode2;
+	}
+
+	return 0;
+}
+
+a_uint32_t ssdk_dt_global_set_mac_mode(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode)
+{
+	if (index == 0)
+	{
+		 ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode= mode;
+	}
+	if (index == 1)
+	{
+		 ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode1 = mode;
+	}
+	if (index == 2)
+	{
+		 ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode2 = mode;
+	}
+
+	return 0;
+}
+
+a_uint32_t ssdk_cpu_bmp_get(a_uint32_t dev_id)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return cfg->port_cfg.cpu_bmp;
+}
+
+a_uint32_t ssdk_lan_bmp_get(a_uint32_t dev_id)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return cfg->port_cfg.lan_bmp;
+}
+
+a_uint32_t ssdk_wan_bmp_get(a_uint32_t dev_id)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return cfg->port_cfg.wan_bmp;
+}
+
+sw_error_t ssdk_lan_bmp_set(a_uint32_t dev_id, a_uint32_t lan_bmp)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+	cfg->port_cfg.lan_bmp = lan_bmp;
+
+	return SW_OK;
+}
+
+sw_error_t ssdk_wan_bmp_set(a_uint32_t dev_id, a_uint32_t wan_bmp)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+	cfg->port_cfg.wan_bmp = wan_bmp;
+
+	return SW_OK;
+}
+
+a_uint32_t ssdk_inner_bmp_get(a_uint32_t dev_id)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return cfg->port_cfg.inner_bmp;
+}
+
+ssdk_port_phyinfo* ssdk_port_phyinfo_get(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	a_uint32_t i;
+	ssdk_port_phyinfo *phyinfo_tmp = NULL;
+	ssdk_dt_cfg *cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	for (i = 0; i < cfg->phyinfo_num; i++) {
+		if (port_id == cfg->port_phyinfo[i].port_id) {
+			phyinfo_tmp = &cfg->port_phyinfo[i];
+			break;
+		} else if (!(cfg->port_phyinfo[i].phy_features & PHY_F_INIT) &&
+				phyinfo_tmp == NULL) {
+			phyinfo_tmp = &cfg->port_phyinfo[i];
+		}
+	}
+
+	return phyinfo_tmp;
+}
+
+a_bool_t ssdk_port_feature_get(a_uint32_t dev_id, a_uint32_t port_id, phy_features_t feature)
+{
+	ssdk_port_phyinfo *phyinfo = ssdk_port_phyinfo_get(dev_id, port_id);
+	if (phyinfo && (phyinfo->phy_features & feature)) {
+		return A_TRUE;
+	}
+	return A_FALSE;
+}
+
+a_uint32_t ssdk_port_force_speed_get(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	ssdk_port_phyinfo *phyinfo = ssdk_port_phyinfo_get(dev_id, port_id);
+	if (phyinfo && (phyinfo->phy_features & PHY_F_FORCE)) {
+		return phyinfo->port_speed;
+	}
+	return FAL_SPEED_BUTT;
+}
+
+struct mii_bus *
+ssdk_dts_miibus_get(a_uint32_t dev_id, a_uint32_t phy_addr)
+{
+	a_uint32_t i;
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	for (i = 0; i < cfg->phyinfo_num; i++) {
+		if (phy_addr == cfg->port_phyinfo[i].phy_addr ||
+			phy_addr == cfg->port_phyinfo[i].phy_addr+1)
+			return cfg->port_phyinfo[i].miibus;
+	}
+
+	return NULL;
+}
+
+hsl_reg_mode ssdk_switch_reg_access_mode_get(a_uint32_t dev_id)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return cfg->switch_reg_access_mode;
+}
+#ifdef IN_UNIPHY
+hsl_reg_mode ssdk_uniphy_reg_access_mode_get(a_uint32_t dev_id)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return cfg->uniphy_reg_access_mode;
+}
+#endif
+#ifdef DESS
+hsl_reg_mode ssdk_psgmii_reg_access_mode_get(a_uint32_t dev_id)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return cfg->psgmii_reg_access_mode;
+}
+#endif
+void ssdk_switch_reg_map_info_get(a_uint32_t dev_id, ssdk_reg_map_info *info)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	info->base_addr = cfg->switchreg_base_addr;
+	info->size = cfg->switchreg_size;
+}
+#ifdef DESS
+void ssdk_psgmii_reg_map_info_get(a_uint32_t dev_id, ssdk_reg_map_info *info)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	info->base_addr = cfg->psgmiireg_base_addr;
+	info->size = cfg->psgmiireg_size;
+}
+#endif
+#ifdef IN_UNIPHY
+void ssdk_uniphy_reg_map_info_get(a_uint32_t dev_id, ssdk_reg_map_info *info)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	info->base_addr = cfg->uniphyreg_base_addr;
+	info->size = cfg->uniphyreg_size;
+}
+#endif
+a_bool_t ssdk_ess_switch_flag_get(a_uint32_t dev_id)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return cfg->ess_switch_flag;
+}
+
+a_uint32_t ssdk_device_id_get(a_uint32_t index)
+{
+	return ssdk_dt_global.ssdk_dt_switch_nodes[index]->device_id;
+}
+
+struct device_node *ssdk_dts_node_get(a_uint32_t dev_id)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return cfg->of_node;
+}
+
+struct clk *ssdk_dts_essclk_get(a_uint32_t dev_id)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return cfg->ess_clk;
+}
+
+struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id)
+{
+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+
+	return cfg->cmnblk_clk;
+}
+
+#ifndef BOARD_AR71XX
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id,
+		struct device_node *switch_node, ssdk_init_cfg *cfg)
+{
+	const __be32 *mac_mode;
+	a_uint32_t len = 0;
+
+	mac_mode = of_get_property(switch_node, "switch_mac_mode", &len);
+	if (!mac_mode)
+		SSDK_INFO("mac mode doesn't exit!\n");
+	else {
+		cfg->mac_mode = be32_to_cpup(mac_mode);
+		SSDK_INFO("mac mode = 0x%x\n", be32_to_cpup(mac_mode));
+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode = cfg->mac_mode;
+	}
+
+	mac_mode = of_get_property(switch_node, "switch_mac_mode1", &len);
+	if(!mac_mode)
+		SSDK_INFO("mac mode1 doesn't exit!\n");
+	else {
+		cfg->mac_mode1 = be32_to_cpup(mac_mode);
+		SSDK_INFO("mac mode1 = 0x%x\n", be32_to_cpup(mac_mode));
+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode1 = cfg->mac_mode1;
+	}
+
+	mac_mode = of_get_property(switch_node, "switch_mac_mode2", &len);
+	if(!mac_mode)
+		SSDK_INFO("mac mode2 doesn't exit!\n");
+	else {
+		cfg->mac_mode2 = be32_to_cpup(mac_mode);
+		SSDK_INFO("mac mode2 = 0x%x\n", be32_to_cpup(mac_mode));
+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode2 = cfg->mac_mode2;
+	}
+
+	return;
+}
+#ifdef IN_UNIPHY
+static void ssdk_dt_parse_uniphy(a_uint32_t dev_id)
+{
+	struct device_node *uniphy_node = NULL;
+	a_uint32_t len = 0;
+	const __be32 *reg_cfg;
+	ssdk_dt_cfg *cfg;
+
+	/* read uniphy register base and address space */
+	uniphy_node = of_find_node_by_name(NULL, "ess-uniphy");
+	if (!uniphy_node)
+		SSDK_INFO("ess-uniphy DT doesn't exist!\n");
+	else {
+		SSDK_INFO("ess-uniphy DT exist!\n");
+		cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
+		reg_cfg = of_get_property(uniphy_node, "reg", &len);
+		if(!reg_cfg)
+			SSDK_INFO("uniphy reg address doesn't exist!\n");
+		else {
+			cfg->uniphyreg_base_addr = be32_to_cpup(reg_cfg);
+			cfg->uniphyreg_size = be32_to_cpup(reg_cfg + 1);
+		}
+		if (of_property_read_string(uniphy_node, "uniphy_access_mode",
+				            (const char **)&cfg->uniphy_access_mode))
+			SSDK_INFO("uniphy access mode doesn't exist!\n");
+		else {
+			if(!strcmp(cfg->uniphy_access_mode, "local bus"))
+				cfg->uniphy_reg_access_mode = HSL_REG_LOCAL_BUS;
+		}
+	}
+
+	return;
+}
+#endif
+#ifdef HPPE
+#ifdef IN_QOS
+static void ssdk_dt_parse_l1_scheduler_cfg(
+	struct device_node *port_node,
+	a_uint32_t port_id, a_uint32_t dev_id)
+{
+	struct device_node *scheduler_node;
+	struct device_node *child;
+	ssdk_dt_scheduler_cfg *cfg = &(ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->scheduler_cfg);
+	a_uint32_t tmp_cfg[4];
+	const __be32 *paddr;
+	a_uint32_t len, i, sp_id;
+
+	scheduler_node = of_find_node_by_name(port_node, "l1scheduler");
+	if (!scheduler_node) {
+		SSDK_ERROR("cannot find l1scheduler node for port\n");
+		return;
+	}
+	for_each_available_child_of_node(scheduler_node, child) {
+		paddr = of_get_property(child, "sp", &len);
+		len /= sizeof(a_uint32_t);
+		if (!paddr) {
+			SSDK_ERROR("error reading sp property\n");
+			return;
+		}
+		if (of_property_read_u32_array(child,
+				"cfg", tmp_cfg, 4)) {
+			SSDK_ERROR("error reading cfg property!\n");
+			return;
+		}
+		for (i = 0; i < len; i++) {
+			sp_id = be32_to_cpup(paddr+i);
+			if (sp_id >= SSDK_L1SCHEDULER_CFG_MAX) {
+				SSDK_ERROR("Invalid parameter for sp(%d)\n",
+					sp_id);
+				return;
+			}
+			cfg->l1cfg[sp_id].valid = 1;
+			cfg->l1cfg[sp_id].port_id = port_id;
+			cfg->l1cfg[sp_id].cpri = tmp_cfg[0];
+			cfg->l1cfg[sp_id].cdrr_id = tmp_cfg[1];
+			cfg->l1cfg[sp_id].epri = tmp_cfg[2];
+			cfg->l1cfg[sp_id].edrr_id = tmp_cfg[3];
+		}
+	}
+}
+
+static void ssdk_dt_parse_l0_queue_cfg(
+	a_uint32_t dev_id,
+	a_uint32_t port_id,
+	struct device_node *node,
+	a_uint8_t *queue_name,
+	a_uint8_t *loop_name)
+{
+	ssdk_dt_scheduler_cfg *cfg = &(ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->scheduler_cfg);
+	a_uint32_t tmp_cfg[5];
+	const __be32 *paddr;
+	a_uint32_t len, i, queue_id, pri_loop;
+
+	paddr = of_get_property(node, queue_name, &len);
+	len /= sizeof(a_uint32_t);
+	if (!paddr) {
+		SSDK_ERROR("error reading %s property\n", queue_name);
+		return;
+	}
+	if (of_property_read_u32_array(node, "cfg", tmp_cfg, 5)) {
+		SSDK_ERROR("error reading cfg property!\n");
+		return;
+	}
+	if (of_property_read_u32(node, loop_name, &pri_loop)) {
+		for (i = 0; i < len; i++) {
+			queue_id = be32_to_cpup(paddr+i);
+			if (queue_id >= SSDK_L0SCHEDULER_CFG_MAX) {
+				SSDK_ERROR("Invalid parameter for queue(%d)\n",
+					queue_id);
+				return;
+			}
+			cfg->l0cfg[queue_id].valid = 1;
+			cfg->l0cfg[queue_id].port_id = port_id;
+			cfg->l0cfg[queue_id].sp_id = tmp_cfg[0];
+			cfg->l0cfg[queue_id].cpri = tmp_cfg[1];
+			cfg->l0cfg[queue_id].cdrr_id = tmp_cfg[2];
+			cfg->l0cfg[queue_id].epri = tmp_cfg[3];
+			cfg->l0cfg[queue_id].edrr_id = tmp_cfg[4];
+		}
+	} else {
+		/* should one queue for loop */
+		if (len != 1) {
+			SSDK_ERROR("should one queue for loop!\n");
+			return;
+		}
+		queue_id = be32_to_cpup(paddr);
+		if (queue_id >= SSDK_L0SCHEDULER_CFG_MAX) {
+			SSDK_ERROR("Invalid parameter for queue(%d)\n",
+				queue_id);
+			return;
+		}
+		for (i = 0; i < pri_loop; i++) {
+			cfg->l0cfg[queue_id + i].valid = 1;
+			cfg->l0cfg[queue_id + i].port_id = port_id;
+			cfg->l0cfg[queue_id + i].sp_id = tmp_cfg[0] + i/SSDK_SP_MAX_PRIORITY;
+			cfg->l0cfg[queue_id + i].cpri = tmp_cfg[1] + i%SSDK_SP_MAX_PRIORITY;
+			cfg->l0cfg[queue_id + i].cdrr_id = tmp_cfg[2] + i;
+			cfg->l0cfg[queue_id + i].epri = tmp_cfg[3] + i%SSDK_SP_MAX_PRIORITY;
+			cfg->l0cfg[queue_id + i].edrr_id = tmp_cfg[4] + i;
+		}
+	}
+}
+
+static void ssdk_dt_parse_l0_scheduler_cfg(
+	struct device_node *port_node,
+	a_uint32_t port_id, a_uint32_t dev_id)
+{
+	struct device_node *scheduler_node;
+	struct device_node *child;
+
+	scheduler_node = of_find_node_by_name(port_node, "l0scheduler");
+	if (!scheduler_node) {
+		SSDK_ERROR("Can't find l0scheduler node for port\n");
+		return;
+	}
+	for_each_available_child_of_node(scheduler_node, child) {
+		ssdk_dt_parse_l0_queue_cfg(dev_id, port_id, child,
+				"ucast_queue", "ucast_loop_pri");
+		ssdk_dt_parse_l0_queue_cfg(dev_id, port_id, child,
+				"mcast_queue", "mcast_loop_pri");
+	}
+}
+
+static void ssdk_dt_parse_scheduler_resource(
+	struct device_node *port_node,
+	a_uint32_t dev_id, a_uint32_t port_id)
+{
+	a_uint32_t uq[2], mq[2], l0sp[2], l0cdrr[2];
+	a_uint32_t l0edrr[2], l1cdrr[2], l1edrr[2];
+	ssdk_dt_scheduler_cfg *cfg = &(ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->scheduler_cfg);
+
+	if (of_property_read_u32_array(port_node, "ucast_queue", uq, 2)
+		|| of_property_read_u32_array(port_node, "mcast_queue", mq, 2)
+		|| of_property_read_u32_array(port_node, "l0sp", l0sp, 2)
+		|| of_property_read_u32_array(port_node, "l0cdrr", l0cdrr, 2)
+		|| of_property_read_u32_array(port_node, "l0edrr", l0edrr, 2)
+		|| of_property_read_u32_array(port_node, "l1cdrr", l1cdrr, 2)
+		|| of_property_read_u32_array(port_node, "l1edrr", l1edrr, 2)){
+		SSDK_ERROR("error reading port resource scheduler properties\n");
+		return;
+	}
+	cfg->pool[port_id].ucastq_start = uq[0];
+	cfg->pool[port_id].ucastq_end = uq[1];
+	cfg->pool[port_id].mcastq_start = mq[0];
+	cfg->pool[port_id].mcastq_end = mq[1];
+	cfg->pool[port_id].l0sp_start = l0sp[0];
+	cfg->pool[port_id].l0sp_end = l0sp[1];
+	cfg->pool[port_id].l0cdrr_start = l0cdrr[0];
+	cfg->pool[port_id].l0cdrr_end = l0cdrr[1];
+	cfg->pool[port_id].l0edrr_start = l0edrr[0];
+	cfg->pool[port_id].l0edrr_end = l0edrr[1];
+	cfg->pool[port_id].l1cdrr_start = l1cdrr[0];
+	cfg->pool[port_id].l1cdrr_end = l1cdrr[1];
+	cfg->pool[port_id].l1edrr_start = l1edrr[0];
+	cfg->pool[port_id].l1edrr_end = l1edrr[1];
+}
+
+static void ssdk_dt_parse_scheduler_cfg(a_uint32_t dev_id, struct device_node *switch_node)
+{
+	struct device_node *scheduler_node;
+	struct device_node *child;
+	a_uint32_t port_id;
+
+	scheduler_node = of_find_node_by_name(switch_node, "port_scheduler_resource");
+	if (!scheduler_node) {
+		SSDK_ERROR("cannot find port_scheduler_resource node\n");
+		return;
+	}
+	for_each_available_child_of_node(scheduler_node, child) {
+		if (of_property_read_u32(child, "port_id", &port_id)) {
+			SSDK_ERROR("error reading for port_id property!\n");
+			return;
+		}
+		if (port_id >= SSDK_MAX_PORT_NUM) {
+			SSDK_ERROR("invalid parameter for port_id(%d)!\n", port_id);
+			return;
+		}
+		ssdk_dt_parse_scheduler_resource(child, dev_id, port_id);
+	}
+
+	scheduler_node = of_find_node_by_name(switch_node, "port_scheduler_config");
+	if (!scheduler_node) {
+		SSDK_ERROR("cannot find port_scheduler_config node\n");
+		return ;
+	}
+	for_each_available_child_of_node(scheduler_node, child) {
+		if (of_property_read_u32(child, "port_id", &port_id)) {
+			SSDK_ERROR("error reading for port_id property!\n");
+			return;
+		}
+		if (port_id >= SSDK_MAX_PORT_NUM) {
+			SSDK_ERROR("invalid parameter for port_id(%d)!\n", port_id);
+			return;
+		}
+		ssdk_dt_parse_l1_scheduler_cfg(child, port_id, dev_id);
+		ssdk_dt_parse_l0_scheduler_cfg(child, port_id, dev_id);
+	}
+}
+#endif
+#endif
+static sw_error_t ssdk_dt_parse_phy_info(struct device_node *switch_node, a_uint32_t dev_id,
+		ssdk_init_cfg *cfg)
+{
+	struct device_node *phy_info_node, *port_node;
+
+	ssdk_port_phyinfo *port_phyinfo;
+	a_uint8_t forced_duplex;
+	a_uint32_t port_id, phy_addr, phy_i2c_addr, forced_speed, len;
+	const __be32 *paddr;
+	a_bool_t phy_c45, phy_combo, phy_i2c, phy_forced;
+	const char *mac_type = NULL, *media_type = NULL;
+	sw_error_t rv = SW_OK;
+	struct device_node *mdio_node;
+	int phy_reset_gpio = 0;
+	phy_dac_t phy_dac = {0};
+
+	phy_info_node = of_get_child_by_name(switch_node, "qcom,port_phyinfo");
+	if (!phy_info_node) {
+		SSDK_INFO("qcom,port_phyinfo DT doesn't exist!\n");
+		return SW_NOT_FOUND;
+	}
+
+	for_each_available_child_of_node(phy_info_node, port_node) {
+		if (of_property_read_u32(port_node, "port_id", &port_id))
+			return SW_BAD_VALUE;
+
+		/* initialize phy_addr in case of undefined dts field */
+		phy_addr = 0xff;
+		of_property_read_u32(port_node, "phy_address", &phy_addr);
+
+		if (!cfg->port_cfg.wan_bmp) {
+			cfg->port_cfg.wan_bmp = BIT(port_id);
+		} else {
+			cfg->port_cfg.lan_bmp |= BIT(port_id);
+		}
+
+		if (!of_property_read_u32(port_node, "forced-speed", &forced_speed) &&
+			!of_property_read_u8(port_node, "forced-duplex", &forced_duplex)) {
+			phy_forced = A_TRUE;
+		} else {
+			phy_forced = A_FALSE;
+		}
+		paddr = of_get_property(port_node, "phy_dac", &len);
+		if(paddr)
+		{
+			phy_dac.mdac = be32_to_cpup(paddr);
+			phy_dac.edac = be32_to_cpup(paddr+1);
+			hsl_port_phy_dac_set(dev_id, port_id, phy_dac);
+		}
+
+		phy_c45 = of_property_read_bool(port_node,
+				"ethernet-phy-ieee802.3-c45");
+		phy_combo = of_property_read_bool(port_node,
+				"ethernet-phy-combo");
+		mdio_node = of_parse_phandle(port_node, "mdiobus", 0);
+		phy_i2c = of_property_read_bool(port_node, "phy-i2c-mode");
+
+		if (phy_i2c) {
+			SSDK_INFO("[PORT %d] phy-i2c-mode\n", port_id);
+			hsl_port_phy_access_type_set(dev_id, port_id, PHY_I2C_ACCESS);
+			if (of_property_read_u32(port_node, "phy_i2c_address",
+						&phy_i2c_addr)) {
+				return SW_BAD_VALUE;
+			}
+			/* phy_i2c_address is the i2c slave addr */
+			hsl_phy_address_init(dev_id, port_id, phy_i2c_addr);
+			/* phy_address is the mdio addr,
+			 * which is a fake mdio addr in i2c mode */
+			qca_ssdk_phy_mdio_fake_address_set(dev_id, port_id, phy_addr);
+		} else {
+			hsl_phy_address_init(dev_id, port_id, phy_addr);
+		}
+
+		hsl_port_phy_combo_capability_set(dev_id, port_id, phy_combo);
+		hsl_port_phy_c45_capability_set(dev_id, port_id, phy_c45);
+
+		port_phyinfo = ssdk_port_phyinfo_get(dev_id, port_id);
+		if (port_phyinfo) {
+			port_phyinfo->port_id = port_id;
+			port_phyinfo->phy_addr = phy_addr;
+			if (phy_c45) {
+				port_phyinfo->phy_features |= PHY_F_CLAUSE45;
+			}
+
+			if (phy_combo) {
+				port_phyinfo->phy_features |= PHY_F_COMBO;
+			}
+
+			if (phy_i2c) {
+				port_phyinfo->phy_features |= PHY_F_I2C;
+			}
+
+			if (phy_forced) {
+				port_phyinfo->phy_features |= PHY_F_FORCE;
+				port_phyinfo->port_speed = forced_speed;
+				port_phyinfo->port_duplex = forced_duplex;
+			}
+
+			if (!of_property_read_string(port_node, "port_mac_sel", &mac_type))
+			{
+				SSDK_INFO("[PORT %d] port_mac_sel = %s\n", port_id, mac_type);
+				if (!strncmp("QGMAC_PORT", mac_type, 10)) {
+					port_phyinfo->phy_features |= PHY_F_QGMAC;
+				}
+				else if (!strncmp("XGMAC_PORT", mac_type, 10)) {
+					port_phyinfo->phy_features |= PHY_F_XGMAC;
+				}
+			}
+
+			if (!of_property_read_string(port_node, "media-type", &media_type)) {
+				if (!strncmp("sfp", media_type, strlen(media_type))) {
+					port_phyinfo->phy_features |= PHY_F_SFP;
+					SSDK_INFO("[PORT %d] media type is %s\n", port_id, media_type);
+				}
+			}
+
+			port_phyinfo->phy_features |= PHY_F_INIT;
+
+			if (mdio_node)
+			{
+				port_phyinfo->miibus = of_mdio_find_bus(mdio_node);
+				phy_reset_gpio = of_get_named_gpio(mdio_node, "phy-reset-gpio",
+					SSDK_PHY_RESET_GPIO_INDEX);
+				if(phy_reset_gpio > 0)
+				{
+					SSDK_INFO("port%d's phy-reset-gpio is GPIO%d\n", port_id,
+						phy_reset_gpio);
+					hsl_port_phy_reset_gpio_set(dev_id, port_id,
+						(a_uint32_t)phy_reset_gpio);
+				}
+			}
+		}
+	}
+
+	return rv;
+}
+
+static void ssdk_dt_parse_mdio(a_uint32_t dev_id, struct device_node *switch_node,
+		ssdk_init_cfg *cfg)
+{
+	struct device_node *mdio_node = NULL;
+	struct device_node *child = NULL;
+	ssdk_port_phyinfo *port_phyinfo;
+	a_uint32_t len = 0, i = 1;
+	const __be32 *phy_addr;
+	const __be32 *c45_phy;
+
+	/* prefer to get phy info from ess-switch node */
+	if (SW_OK == ssdk_dt_parse_phy_info(switch_node, dev_id, cfg))
+		return;
+
+	mdio_node = of_find_node_by_name(NULL, "mdio");
+
+	if (!mdio_node) {
+		SSDK_INFO("mdio DT doesn't exist!\n");
+	}
+	else {
+		SSDK_INFO("mdio DT exist!\n");
+		for_each_available_child_of_node(mdio_node, child) {
+			phy_addr = of_get_property(child, "reg", &len);
+			if (phy_addr) {
+				hsl_phy_address_init(dev_id, i, be32_to_cpup(phy_addr));
+			}
+
+			c45_phy = of_get_property(child, "compatible", &len);
+			if (c45_phy) {
+				hsl_port_phy_c45_capability_set(dev_id, i, A_TRUE);
+			}
+
+			port_phyinfo = ssdk_port_phyinfo_get(dev_id, i);
+			if (port_phyinfo) {
+				port_phyinfo->port_id = i;
+				if (phy_addr) {
+					port_phyinfo->phy_addr = be32_to_cpup(phy_addr);
+				}
+				if (c45_phy) {
+					port_phyinfo->phy_features |= PHY_F_CLAUSE45;
+				}
+
+				port_phyinfo->phy_features |= PHY_F_INIT;
+			}
+
+			if (!cfg->port_cfg.wan_bmp) {
+				cfg->port_cfg.wan_bmp = BIT(i);
+			} else {
+				cfg->port_cfg.lan_bmp |= BIT(i);
+			}
+
+			i++;
+			if (i >= SW_MAX_NR_PORT) {
+				break;
+			}
+		}
+	}
+	return;
+}
+
+static void ssdk_dt_parse_port_bmp(a_uint32_t dev_id,
+		struct device_node *switch_node, ssdk_init_cfg *cfg)
+{
+	a_uint32_t portbmp = 0;
+
+	if (of_property_read_u32(switch_node, "switch_cpu_bmp", &cfg->port_cfg.cpu_bmp)
+		|| of_property_read_u32(switch_node, "switch_lan_bmp", &cfg->port_cfg.lan_bmp)
+		|| of_property_read_u32(switch_node, "switch_wan_bmp", &cfg->port_cfg.wan_bmp)) {
+		SSDK_INFO("port_bmp doesn't exist!\n");
+		/*
+		 * the bmp maybe initialized already, so just keep ongoing.
+		 */
+	}
+
+	if (!of_property_read_u32(switch_node, "switch_inner_bmp", &cfg->port_cfg.inner_bmp)) {
+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.inner_bmp =
+				cfg->port_cfg.inner_bmp;
+	}
+
+	ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.cpu_bmp = cfg->port_cfg.cpu_bmp;
+	ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.lan_bmp = cfg->port_cfg.lan_bmp;
+	ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.wan_bmp = cfg->port_cfg.wan_bmp;
+
+	portbmp = cfg->port_cfg.lan_bmp | cfg->port_cfg.wan_bmp;
+	qca_ssdk_port_bmp_set(dev_id, portbmp);
+
+	return;
+}
+#ifdef HPPE
+static void ssdk_dt_parse_intf_mac(void)
+{
+	struct device_node *dp_node = NULL;
+	a_uint32_t dp = 0;
+	a_uint8_t *maddr = NULL;
+	char dp_name[8] = {0};
+
+	for (dp = 1; dp <= SSDK_MAX_NR_ETH; dp++) {
+		snprintf(dp_name, sizeof(dp_name), "dp%d", dp);
+		dp_node = of_find_node_by_name(NULL, dp_name);
+		if (!dp_node) {
+			continue;
+		}
+		maddr = (a_uint8_t *)of_get_mac_address(dp_node);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+		if (maddr && is_valid_ether_addr(maddr)) {
+#else
+		if (!IS_ERR(maddr) && is_valid_ether_addr(maddr)) {
+#endif
+			ssdk_dt_global.num_intf_mac++;
+			ether_addr_copy(ssdk_dt_global.intf_mac[dp-1].uc, maddr);
+			SSDK_INFO("%s MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
+				dp_name, maddr[0], maddr[1], maddr[2], maddr[3],
+				maddr[4], maddr[5]);
+		}
+	}
+	return;
+}
+#endif
+#ifdef DESS
+static void ssdk_dt_parse_psgmii(ssdk_dt_cfg *ssdk_dt_priv)
+{
+
+	struct device_node *psgmii_node = NULL;
+	const __be32 *reg_cfg;
+	a_uint32_t len = 0;
+
+	psgmii_node = of_find_node_by_name(NULL, "ess-psgmii");
+	if (!psgmii_node) {
+		SSDK_ERROR("cannot find ess-psgmii node\n");
+		return;
+	}
+
+	SSDK_INFO("ess-psgmii DT exist!\n");
+	reg_cfg = of_get_property(psgmii_node, "reg", &len);
+	if(!reg_cfg) {
+		SSDK_ERROR("%s: error reading device node properties for reg\n",
+			        psgmii_node->name);
+		return;
+	}
+
+	ssdk_dt_priv->psgmiireg_base_addr = be32_to_cpup(reg_cfg);
+	ssdk_dt_priv->psgmiireg_size = be32_to_cpup(reg_cfg + 1);
+	if (of_property_read_string(psgmii_node, "psgmii_access_mode",
+			(const char **)&ssdk_dt_priv->psgmii_reg_access_str)) {
+		SSDK_ERROR("%s: error reading properties for psmgii_access_mode\n",
+			         psgmii_node->name);
+		return;
+	}
+	if(!strcmp(ssdk_dt_priv->psgmii_reg_access_str, "local bus"))
+		ssdk_dt_priv->psgmii_reg_access_mode = HSL_REG_LOCAL_BUS;
+
+	return;
+}
+#endif
+static sw_error_t ssdk_dt_parse_access_mode(struct device_node *switch_node,
+		ssdk_dt_cfg *ssdk_dt_priv)
+{
+	const __be32 *reg_cfg;
+	a_uint32_t len = 0;
+
+	if (of_property_read_string(switch_node, "switch_access_mode",
+			(const char **)&ssdk_dt_priv->reg_access_mode)) {
+		SSDK_ERROR("%s: error reading properties for switch_access_mode\n",
+			        switch_node->name);
+		return SW_BAD_PARAM;
+	}
+
+	SSDK_INFO("switch_access_mode: %s\n", ssdk_dt_priv->reg_access_mode);
+	if(!strcmp(ssdk_dt_priv->reg_access_mode, "local bus")) {
+		ssdk_dt_priv->switch_reg_access_mode = HSL_REG_LOCAL_BUS;
+
+		reg_cfg = of_get_property(switch_node, "reg", &len);
+		if(!reg_cfg) {
+			SSDK_ERROR("%s: error reading properties for reg\n",
+				switch_node->name);
+			return SW_BAD_PARAM;
+		}
+		ssdk_dt_priv->switchreg_base_addr = be32_to_cpup(reg_cfg);
+		ssdk_dt_priv->switchreg_size = be32_to_cpup(reg_cfg + 1);
+
+		SSDK_INFO("switchreg_base_addr: 0x%x\n", ssdk_dt_priv->switchreg_base_addr);
+		SSDK_INFO("switchreg_size: 0x%x\n", ssdk_dt_priv->switchreg_size);
+	}
+	else {
+		ssdk_dt_priv->switch_reg_access_mode = HSL_REG_MDIO;
+	}
+
+	return SW_OK;
+
+}
+#if (defined(DESS) || defined(MP))
+#ifdef IN_LED
+static void ssdk_dt_parse_led(struct device_node *switch_node,
+		ssdk_init_cfg *cfg)
+{
+	struct device_node *child = NULL;
+	const __be32 *led_source, *led_number;
+	a_uint8_t *led_str;
+	a_uint32_t len = 0, i = 0;
+
+	for_each_available_child_of_node(switch_node, child) {
+
+		led_source = of_get_property(child, "source", &len);
+		if (!led_source) {
+			continue;
+		}
+		cfg->led_source_cfg[i].led_source_id = be32_to_cpup(led_source);
+		led_number = of_get_property(child, "led", &len);
+		if (led_number)
+			cfg->led_source_cfg[i].led_num = be32_to_cpup(led_number);
+		if (!of_property_read_string(child, "mode", (const char **)&led_str)) {
+			if (!strcmp(led_str, "normal"))
+			cfg->led_source_cfg[i].led_pattern.mode = LED_PATTERN_MAP_EN;
+			if (!strcmp(led_str, "on"))
+			cfg->led_source_cfg[i].led_pattern.mode = LED_ALWAYS_ON;
+			if (!strcmp(led_str, "blink"))
+			cfg->led_source_cfg[i].led_pattern.mode = LED_ALWAYS_BLINK;
+			if (!strcmp(led_str, "off"))
+			cfg->led_source_cfg[i].led_pattern.mode = LED_ALWAYS_OFF;
+		}
+		if (!of_property_read_string(child, "speed", (const char **)&led_str)) {
+			if (!strcmp(led_str, "10M"))
+			cfg->led_source_cfg[i].led_pattern.map = LED_MAP_10M_SPEED;
+			if (!strcmp(led_str, "100M"))
+			cfg->led_source_cfg[i].led_pattern.map = LED_MAP_100M_SPEED;
+			if (!strcmp(led_str, "1000M"))
+			cfg->led_source_cfg[i].led_pattern.map = LED_MAP_1000M_SPEED;
+			if (!strcmp(led_str, "2500M"))
+			cfg->led_source_cfg[i].led_pattern.map = LED_MAP_2500M_SPEED;
+			if (!strcmp(led_str, "all"))
+			cfg->led_source_cfg[i].led_pattern.map = LED_MAP_ALL_SPEED;
+		}
+		if (!of_property_read_string(child, "freq", (const char **)&led_str)) {
+			if (!strcmp(led_str, "2Hz"))
+			cfg->led_source_cfg[i].led_pattern.freq = LED_BLINK_2HZ;
+			if (!strcmp(led_str, "4Hz"))
+			cfg->led_source_cfg[i].led_pattern.freq = LED_BLINK_4HZ;
+			if (!strcmp(led_str, "8Hz"))
+			cfg->led_source_cfg[i].led_pattern.freq = LED_BLINK_8HZ;
+			if (!strcmp(led_str, "auto"))
+			cfg->led_source_cfg[i].led_pattern.freq = LED_BLINK_TXRX;
+		}
+		if (!of_property_read_string(child, "active", (const char **)&led_str)) {
+			if (!strcmp(led_str, "high"))
+			cfg->led_source_cfg[i].led_pattern.map |= BIT(LED_ACTIVE_HIGH);
+		}
+		if (!of_property_read_string(child, "blink_en", (const char **)&led_str)) {
+			if (!strcmp(led_str, "disable"))
+			cfg->led_source_cfg[i].led_pattern.map &= ~(BIT(RX_TRAFFIC_BLINK_EN)|
+				BIT(TX_TRAFFIC_BLINK_EN));
+		}
+		i++;
+	}
+	cfg->led_source_num = i;
+	SSDK_INFO("current dts led_source_num is %d\n",cfg->led_source_num);
+
+	return;
+}
+#endif
+#endif
+static sw_error_t ssdk_dt_get_switch_node(struct device_node **switch_node,
+		a_uint32_t num)
+{
+	struct device_node *switch_instance = NULL;
+	char ess_switch_name[64] = {0};
+
+	if (num == 0)
+		snprintf(ess_switch_name, sizeof(ess_switch_name), "ess-switch");
+	else
+		snprintf(ess_switch_name, sizeof(ess_switch_name), "ess-switch%d", num);
+
+	/*
+	 * Get reference to ESS SWITCH device node from ess-instance node firstly.
+	 */
+	switch_instance = of_find_node_by_name(NULL, "ess-instance");
+	*switch_node = of_find_node_by_name(switch_instance, ess_switch_name);
+	if (!*switch_node) {
+		SSDK_WARN("cannot find ess-switch node\n");
+		return SW_BAD_PARAM;
+	}
+
+	SSDK_INFO("ess-switch DT exist!\n");
+
+	if (!of_device_is_available(*switch_node))
+	{
+		SSDK_WARN("ess-switch node[%s] is disabled\n", ess_switch_name);
+		return SW_DISABLE;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t ssdk_dt_parse(ssdk_init_cfg *cfg, a_uint32_t num, a_uint32_t *dev_id)
+{
+	sw_error_t rv = SW_OK;
+	struct device_node *switch_node = NULL;
+	ssdk_dt_cfg *ssdk_dt_priv = NULL;
+	a_uint32_t len = 0;
+	const __be32 *device_id;
+
+	rv = ssdk_dt_get_switch_node(&switch_node, num);
+	SW_RTN_ON_ERROR(rv);
+
+	device_id = of_get_property(switch_node, "device_id", &len);
+	if(!device_id)
+		*dev_id = 0;
+	else
+		*dev_id = be32_to_cpup(device_id);
+
+	ssdk_dt_priv = ssdk_dt_global.ssdk_dt_switch_nodes[*dev_id];
+	ssdk_dt_priv->device_id = *dev_id;
+	ssdk_dt_priv->ess_switch_flag = A_TRUE;
+	ssdk_dt_priv->of_node = switch_node;
+	ssdk_dt_priv->ess_clk= ERR_PTR(-ENOENT);
+	ssdk_dt_priv->cmnblk_clk = ERR_PTR(-ENOENT);
+
+	if(of_property_read_bool(switch_node,"qcom,emulation")){
+		ssdk_dt_priv->is_emulation = A_TRUE;
+		SSDK_INFO("RUMI emulation\n");
+	}
+	/* parse common dts info */
+	rv = ssdk_dt_parse_access_mode(switch_node, ssdk_dt_priv);
+	SW_RTN_ON_ERROR(rv);
+	ssdk_dt_parse_mac_mode(*dev_id, switch_node, cfg);
+	ssdk_dt_parse_mdio(*dev_id, switch_node, cfg);
+	ssdk_dt_parse_port_bmp(*dev_id, switch_node, cfg);
+
+	if (of_device_is_compatible(switch_node, "qcom,ess-switch")) {
+		/* DESS chip */
+#ifdef DESS
+#ifdef IN_LED
+		ssdk_dt_parse_led(switch_node, cfg);
+#endif
+		ssdk_dt_parse_psgmii(ssdk_dt_priv);
+
+		ssdk_dt_priv->ess_clk = of_clk_get_by_name(switch_node, "ess_clk");
+		if (IS_ERR(ssdk_dt_priv->ess_clk))
+			SSDK_INFO("ess_clk doesn't exist!\n");
+#endif
+	}
+	else if (of_device_is_compatible(switch_node, "qcom,ess-switch-ipq807x") ||
+		 of_device_is_compatible(switch_node, "qcom,ess-switch-ipq60xx")) {
+		/* HPPE chip */
+#ifdef HPPE
+		a_uint32_t mode = 0;
+#ifdef IN_UNIPHY
+		ssdk_dt_parse_uniphy(*dev_id);
+#endif
+#ifdef IN_QOS
+		ssdk_dt_parse_scheduler_cfg(*dev_id, switch_node);
+#endif
+		ssdk_dt_parse_intf_mac();
+
+		ssdk_dt_priv->cmnblk_clk = of_clk_get_by_name(switch_node, "cmn_ahb_clk");
+		if (!of_property_read_u32(switch_node, "tm_tick_mode", &mode))
+			ssdk_dt_priv->tm_tick_mode = mode;
+#endif
+	}
+	else if (of_device_is_compatible(switch_node, "qcom,ess-switch-ipq50xx")) {
+#ifdef MP
+		ssdk_dt_priv->emu_chip_ver = MP_GEPHY;
+#ifdef IN_UNIPHY
+		ssdk_dt_parse_uniphy(*dev_id);
+#endif
+#ifdef IN_LED
+		ssdk_dt_parse_led(switch_node, cfg);
+#endif
+		ssdk_dt_priv->cmnblk_clk = of_clk_get_by_name(switch_node, "cmn_ahb_clk");
+#endif
+	}
+	else if (of_device_is_compatible(switch_node, "qcom,ess-switch-qca83xx")) {
+		/* s17/s17c chip */
+		SSDK_INFO("switch node is qca83xx!\n");
+	}
+	else {
+		SSDK_WARN("invalid compatible property\n");
+	}
+
+	return SW_OK;
+}
+
+static a_uint32_t ssdk_get_switch_port_nums(a_uint32_t dev_id)
+{
+	struct device_node *child, *mdio_np, *port_np, *switch_np, *switch_instance;
+	a_uint32_t port_count = 0, switch_id = 0;
+
+	switch_instance = of_find_node_by_name(NULL, "ess-instance");
+	if (switch_instance) { /* multi ess-switch */
+		for_each_available_child_of_node(switch_instance, switch_np) {
+			if (of_property_read_u32(switch_np, "device_id", &switch_id) < 0) {
+				switch_id = 0;
+			}
+			if (switch_id == dev_id) {
+				port_np = of_find_node_by_name(switch_np, "qcom,port_phyinfo");
+				if (port_np) {
+					for_each_available_child_of_node(port_np, child)
+						port_count++;
+					break;
+				}
+			}
+		}
+	} else { /* single ess-switch */
+		switch_np = of_find_node_by_name(NULL, "ess-switch");
+		if (switch_np && dev_id == 0) {
+			port_np = of_find_node_by_name(switch_np, "qcom,port_phyinfo");
+			if (port_np) {
+				for_each_available_child_of_node(port_np, child)
+					port_count++;
+			} else {
+				mdio_np = of_find_node_by_name(NULL, "mdio");
+				if (mdio_np) {
+					for_each_available_child_of_node(mdio_np, child)
+						port_count++;
+				}
+			}
+		}
+	}
+
+	return port_count;
+}
+#endif
+#endif
+
+int ssdk_switch_device_num_init(void)
+{
+	struct device_node *switch_instance = NULL;
+	a_uint32_t len = 0, port_n = 0;
+	const __be32 *num_devices;
+	a_uint32_t dev_num = 1, dev_id = 0;
+
+	switch_instance = of_find_node_by_name(NULL, "ess-instance");
+	if (switch_instance) {
+		num_devices = of_get_property(switch_instance, "num_devices", &len);
+		if (num_devices)
+			dev_num = be32_to_cpup(num_devices);
+	}
+
+	ssdk_dt_global.ssdk_dt_switch_nodes = kzalloc(dev_num * sizeof(ssdk_dt_cfg *), GFP_KERNEL);
+	if (ssdk_dt_global.ssdk_dt_switch_nodes == NULL) {
+		return -ENOMEM;
+	}
+
+	for (dev_id = 0; dev_id < dev_num; dev_id++) {
+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id] = kzalloc(sizeof(ssdk_dt_cfg),
+								GFP_KERNEL);
+		if (ssdk_dt_global.ssdk_dt_switch_nodes[dev_id] == NULL) {
+			return -ENOMEM;
+		}
+
+#ifndef BOARD_AR71XX
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+		port_n = ssdk_get_switch_port_nums(dev_id);
+#endif
+#endif
+		if (!port_n) {
+			port_n = SW_MAX_NR_PORT;
+		}
+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_phyinfo = kzalloc(port_n *
+				sizeof(ssdk_port_phyinfo), GFP_KERNEL);
+		if (!ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_phyinfo) {
+			return -ENOMEM;
+		}
+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->phyinfo_num = port_n;
+
+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->switch_reg_access_mode = HSL_REG_MDIO;
+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->psgmii_reg_access_mode = HSL_REG_MDIO;
+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->ess_switch_flag = A_FALSE;
+	}
+
+	ssdk_dt_global.num_devices = dev_num;
+	SSDK_INFO("ess-switch dts node number: %d\n", dev_num);
+
+	return 0;
+}
+
+void ssdk_switch_device_num_exit(void)
+{
+	a_uint32_t dev_id = 0;
+
+	for (dev_id = 0; dev_id < ssdk_dt_global.num_devices; dev_id++) {
+		if (ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_phyinfo) {
+			kfree(ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_phyinfo);
+			ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_phyinfo = NULL;
+		}
+
+		if (ssdk_dt_global.ssdk_dt_switch_nodes[dev_id])
+			kfree(ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]);
+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id] = NULL;
+	}
+
+	if (ssdk_dt_global.ssdk_dt_switch_nodes)
+		kfree(ssdk_dt_global.ssdk_dt_switch_nodes);
+	ssdk_dt_global.ssdk_dt_switch_nodes = NULL;
+
+	ssdk_dt_global.num_devices = 0;
+}
+
+a_uint32_t ssdk_switch_device_num_get(void)
+{
+	return ssdk_dt_global.num_devices;
+}
+
+a_bool_t ssdk_is_emulation(a_uint32_t dev_id)
+{
+	return ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->is_emulation;
+}
+a_uint32_t ssdk_emu_chip_ver_get(a_uint32_t dev_id)
+{
+	return ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->emu_chip_ver;
+}
+
diff --git a/qca-ssdk/src/init/ssdk_hppe.c b/qca-ssdk/src/init/ssdk_hppe.c
new file mode 100755
index 0000000..3c08496
--- /dev/null
+++ b/qca-ssdk/src/init/ssdk_hppe.c
@@ -0,0 +1,1286 @@
+/*
+ * Copyright (c) 2012, 2014-2019, 2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "ssdk_init.h"
+#include "ssdk_dts.h"
+#include "adpt.h"
+#include "adpt_hppe.h"
+#include "fal.h"
+#include "ref_vsi.h"
+#include "ssdk_clk.h"
+#include "hsl_phy.h"
+
+#if defined(IN_VSI)
+static sw_error_t qca_hppe_vsi_hw_init(a_uint32_t dev_id)
+{
+       return ppe_vsi_init(dev_id);
+}
+#endif
+
+#if defined(IN_FDB)
+static sw_error_t qca_hppe_fdb_hw_init(a_uint32_t dev_id)
+{
+	a_uint32_t port = 0;
+	adpt_api_t *p_api;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+	SW_RTN_ON_NULL(p_api->adpt_port_bridge_txmac_set);
+
+	for(port = SSDK_PHYSICAL_PORT0; port <= SSDK_PHYSICAL_PORT7; port++) {
+		if(port == SSDK_PHYSICAL_PORT0) {
+			fal_fdb_port_learning_ctrl_set(dev_id, port, A_FALSE, FAL_MAC_FRWRD);
+			fal_fdb_port_stamove_ctrl_set(dev_id, port, A_FALSE, FAL_MAC_FRWRD);
+		} else {
+			fal_fdb_port_learning_ctrl_set(dev_id, port, A_TRUE, FAL_MAC_FRWRD);
+			fal_fdb_port_stamove_ctrl_set(dev_id, port, A_TRUE, FAL_MAC_FRWRD);
+		}
+		fal_portvlan_member_update(dev_id, port, 0x7f);
+		if (port == SSDK_PHYSICAL_PORT0 || port == SSDK_PHYSICAL_PORT7) {
+			p_api->adpt_port_bridge_txmac_set(dev_id, port, A_TRUE);
+		} else {
+			p_api->adpt_port_bridge_txmac_set(dev_id, port, A_FALSE);
+		}
+		fal_port_promisc_mode_set(dev_id, port, A_TRUE);
+	}
+
+	fal_fdb_aging_ctrl_set(dev_id, A_TRUE);
+	fal_fdb_learning_ctrl_set(dev_id, A_TRUE);
+
+	return SW_OK;
+}
+#endif
+
+#if defined(IN_CTRLPKT)
+#define RFDB_PROFILE_ID_STP 31
+static sw_error_t qca_hppe_ctlpkt_hw_init(a_uint32_t dev_id)
+{
+	fal_mac_addr_t mcast_mac_addr;
+	fal_ctrlpkt_action_t ctrlpkt_action;
+	fal_ctrlpkt_profile_t ctrlpkt_profile;
+	sw_error_t rv = SW_OK;
+
+	memset(&ctrlpkt_action, 0, sizeof(ctrlpkt_action));
+	memset(&ctrlpkt_profile, 0, sizeof(ctrlpkt_profile));
+	memset(&mcast_mac_addr, 0, sizeof(mcast_mac_addr));
+
+	mcast_mac_addr.uc[0] = 0x01;
+	mcast_mac_addr.uc[1] = 0x80;
+	mcast_mac_addr.uc[2] = 0xc2;
+	rv = fal_mgmtctrl_rfdb_profile_set(dev_id, RFDB_PROFILE_ID_STP,
+			&mcast_mac_addr);
+	SW_RTN_ON_ERROR(rv);
+
+	ctrlpkt_action.action = FAL_MAC_RDT_TO_CPU;
+	ctrlpkt_action.in_stp_bypass = A_TRUE;
+
+	ctrlpkt_profile.action = ctrlpkt_action;
+	ctrlpkt_profile.port_map = qca_ssdk_port_bmp_get(dev_id);
+	ctrlpkt_profile.rfdb_profile_bitmap = (1 << RFDB_PROFILE_ID_STP);
+	rv = fal_mgmtctrl_ctrlpkt_profile_add(dev_id, &ctrlpkt_profile);
+
+	return rv;
+}
+#endif
+
+#if defined(IN_PORTCONTROL)
+static sw_error_t
+qca_hppe_portctrl_hw_init(a_uint32_t dev_id)
+{
+	a_uint32_t i = 0;
+	a_uint32_t port_max = SSDK_PHYSICAL_PORT7;
+#if defined(CPPE)
+	fal_loopback_config_t loopback_cfg;
+#endif
+
+	if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+		SSDK_INFO("Cypress PPE port initializing\n");
+		port_max = SSDK_PHYSICAL_PORT6;
+	} else {
+		SSDK_INFO("Hawkeye PPE port initializing\n");
+		port_max = SSDK_PHYSICAL_PORT7;
+	}
+	for(i = SSDK_PHYSICAL_PORT1; i < port_max; i++) {
+		qca_hppe_port_mac_type_set(dev_id, i, PORT_GMAC_TYPE);
+		fal_port_txmac_status_set (dev_id, i, A_FALSE);
+		fal_port_rxmac_status_set (dev_id, i, A_FALSE);
+		fal_port_rxfc_status_set(dev_id, i, A_FALSE);
+		fal_port_txfc_status_set(dev_id, i, A_FALSE);
+		fal_port_max_frame_size_set(dev_id, i, SSDK_MAX_FRAME_SIZE);
+	}
+
+	for(i = SSDK_PHYSICAL_PORT5; i < port_max; i++) {
+		qca_hppe_port_mac_type_set(dev_id, i, PORT_XGMAC_TYPE);
+		fal_port_txmac_status_set (dev_id, i, A_FALSE);
+		fal_port_rxmac_status_set (dev_id, i, A_FALSE);
+		fal_port_rxfc_status_set(dev_id, i, A_FALSE);
+		fal_port_txfc_status_set(dev_id, i, A_FALSE);
+		fal_port_max_frame_size_set(dev_id, i, SSDK_MAX_FRAME_SIZE);
+	}
+
+#if defined(CPPE)
+	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+		loopback_cfg.enable = A_TRUE;
+		loopback_cfg.crc_stripped = A_TRUE;
+		loopback_cfg.loopback_rate = FAL_DEFAULT_LOOPBACK_RATE;  /* Mpps */
+		fal_switch_port_loopback_set(dev_id, SSDK_PHYSICAL_PORT6,
+				&loopback_cfg);
+		fal_port_max_frame_size_set(dev_id, SSDK_PHYSICAL_PORT6,
+				SSDK_MAX_FRAME_SIZE);
+	}
+#endif
+	return SW_OK;
+}
+#endif
+
+#if defined(IN_POLICER)
+static sw_error_t
+qca_hppe_policer_hw_init(a_uint32_t dev_id)
+{
+	a_uint32_t i = 0;
+	fal_policer_frame_type_t frame_type;
+
+	fal_policer_timeslot_set(dev_id, HPPE_POLICER_TIMESLOT_DFT);
+
+	for (i = SSDK_PHYSICAL_PORT0; i <= SSDK_PHYSICAL_PORT7; i++) {
+		fal_port_policer_compensation_byte_set(dev_id, i, 4);
+	}
+
+	/* bypass policer for dropped frame */
+	frame_type = FAL_FRAME_DROPPED;
+	fal_policer_bypass_en_set(dev_id, frame_type, A_TRUE);
+
+	return SW_OK;
+}
+#endif
+
+#if defined(IN_SHAPER)
+static sw_error_t
+qca_hppe_shaper_hw_init(a_uint32_t dev_id)
+{
+	fal_shaper_token_number_t port_token_number, queue_token_number;
+	fal_shaper_token_number_t flow_token_number;
+	a_uint32_t i = 0;
+
+	port_token_number.c_token_number_negative_en = A_FALSE;
+	port_token_number.c_token_number = HPPE_MAX_C_TOKEN_NUM;
+	queue_token_number.c_token_number_negative_en = A_FALSE;
+	queue_token_number.c_token_number = HPPE_MAX_C_TOKEN_NUM;
+	queue_token_number.e_token_number_negative_en = A_FALSE;
+	queue_token_number.e_token_number = HPPE_MAX_E_TOKEN_NUM;
+	flow_token_number.c_token_number_negative_en = A_FALSE;
+	flow_token_number.c_token_number = HPPE_MAX_C_TOKEN_NUM;
+	flow_token_number.e_token_number_negative_en = A_FALSE;
+	flow_token_number.e_token_number = HPPE_MAX_E_TOKEN_NUM;
+
+	for (i = SSDK_PHYSICAL_PORT0; i <= SSDK_PHYSICAL_PORT7; i++) {
+		fal_port_shaper_token_number_set(dev_id, i, &port_token_number);
+	}
+
+	for(i = 0; i < SSDK_L0SCHEDULER_CFG_MAX; i ++) {
+		fal_queue_shaper_token_number_set(dev_id, i, &queue_token_number);
+	}
+
+	for(i = 0; i < SSDK_L1SCHEDULER_CFG_MAX; i ++) {
+		fal_flow_shaper_token_number_set(dev_id, i, &flow_token_number);
+	}
+
+	fal_port_shaper_timeslot_set(dev_id, HPPE_PORT_SHAPER_TIMESLOT_DFT);
+	fal_flow_shaper_timeslot_set(dev_id, HPPE_FLOW_SHAPER_TIMESLOT_DFT);
+	fal_queue_shaper_timeslot_set(dev_id, HPPE_QUEUE_SHAPER_TIMESLOT_DFT);
+	fal_shaper_ipg_preamble_length_set(dev_id,
+				HPPE_SHAPER_IPG_PREAMBLE_LEN_DFT);
+
+	return SW_OK;
+}
+#endif
+
+#if defined(IN_PORTVLAN)
+static sw_error_t
+qca_hppe_portvlan_hw_init(a_uint32_t dev_id)
+{
+	a_uint32_t port_id = 0, vsi_idx = 0;
+	fal_global_qinq_mode_t global_qinq_mode;
+	fal_port_qinq_role_t port_qinq_role;
+	fal_tpid_t in_eg_tpid;
+	fal_vlantag_egress_mode_t vlantag_eg_mode;
+
+	/* configure ingress/egress global QinQ mode as ctag/ctag */
+	global_qinq_mode.mask = 0x3;
+	global_qinq_mode.ingress_mode = FAL_QINQ_CTAG_MODE;
+	global_qinq_mode.egress_mode = FAL_QINQ_CTAG_MODE;
+	fal_global_qinq_mode_set(dev_id, &global_qinq_mode);
+
+	/* configure port0, port7 ingress/egress QinQ role as core/core */
+	port_qinq_role.mask = 0x3;
+	port_qinq_role.ingress_port_role = FAL_QINQ_CORE_PORT;
+	port_qinq_role.egress_port_role = FAL_QINQ_CORE_PORT;
+	fal_port_qinq_mode_set(dev_id, SSDK_PHYSICAL_PORT0, &port_qinq_role);
+	fal_port_qinq_mode_set(dev_id, SSDK_PHYSICAL_PORT7, &port_qinq_role);
+	/* configure port1 - port6 ingress/egress QinQ role as edge/edge */
+	port_qinq_role.mask = 0x3;
+	port_qinq_role.ingress_port_role = FAL_QINQ_EDGE_PORT;
+	port_qinq_role.egress_port_role = FAL_QINQ_EDGE_PORT;
+	for (port_id = SSDK_PHYSICAL_PORT1; port_id <= SSDK_PHYSICAL_PORT6;
+			port_id++) {
+		fal_port_qinq_mode_set(dev_id, port_id, &port_qinq_role);
+	}
+
+	/* configure ingress and egress stpid/ctpid as 0x88a8/0x8100 */
+	in_eg_tpid.mask = 0x3;
+	in_eg_tpid.ctpid = FAL_DEF_VLAN_CTPID;
+	in_eg_tpid.stpid = FAL_DEF_VLAN_STPID;
+	fal_ingress_tpid_set(dev_id, &in_eg_tpid);
+	fal_egress_tpid_set(dev_id, &in_eg_tpid);
+
+	/* configure the port0 - port7 of vsi0 - vsi31 to unmodified */
+	for (vsi_idx = 0; vsi_idx <= FAL_VSI_MAX; vsi_idx++) {
+		for (port_id = SSDK_PHYSICAL_PORT0;
+			port_id <= SSDK_PHYSICAL_PORT7;	port_id++) {
+			fal_port_vsi_egmode_set(dev_id, vsi_idx,
+						port_id, FAL_EG_UNMODIFIED);
+		}
+	}
+
+	vlantag_eg_mode.mask = 0x3;
+	vlantag_eg_mode.stag_mode = FAL_EG_UNTOUCHED;
+	vlantag_eg_mode.ctag_mode = FAL_EG_UNTOUCHED;
+	/*stag/ctag egress mode as untouched/untouched*/
+	fal_port_vlantag_egmode_set(dev_id, SSDK_PHYSICAL_PORT0,
+				&vlantag_eg_mode);
+	fal_port_vlantag_egmode_set(dev_id, SSDK_PHYSICAL_PORT7,
+				&vlantag_eg_mode);
+	/*vsi tag mode control to disable*/
+	fal_port_vlantag_vsi_egmode_enable(dev_id, SSDK_PHYSICAL_PORT0,
+				A_FALSE);
+	fal_port_vlantag_vsi_egmode_enable(dev_id, SSDK_PHYSICAL_PORT7,
+				A_FALSE);
+	/*ingress vlan translation mismatched command as forward*/
+	fal_port_vlan_xlt_miss_cmd_set(dev_id, SSDK_PHYSICAL_PORT0,
+				FAL_MAC_FRWRD);
+
+	vlantag_eg_mode.stag_mode = FAL_EG_UNMODIFIED;
+	vlantag_eg_mode.ctag_mode = FAL_EG_UNMODIFIED;
+	for (port_id = SSDK_PHYSICAL_PORT1; port_id <= SSDK_PHYSICAL_PORT6;
+			port_id++) {
+		/*ingress vlan translation mismatched command as forward*/
+		fal_port_vlan_xlt_miss_cmd_set(dev_id, port_id, FAL_MAC_FRWRD);
+		/*vsi tag mode control to enable*/
+		fal_port_vlantag_vsi_egmode_enable(dev_id, port_id, A_TRUE);
+		/*stag/ctag egress mode as unmodified/unmodified*/
+		fal_port_vlantag_egmode_set(dev_id, port_id, &vlantag_eg_mode);
+	}
+
+	return SW_OK;
+}
+#endif
+
+#if defined(IN_BM) && defined(IN_QOS)
+fal_port_scheduler_cfg_t port_scheduler0_tbl[] = {
+	{0xee, 6, 0},
+	{0xde, 4, 5},
+	{0x9f, 0, 6},
+	{0xbe, 5, 0},
+	{0x7e, 6, 7},
+	{0x5f, 0, 5},
+	{0x9f, 7, 6},
+	{0xbe, 5, 0},
+	{0xfc, 6, 1},
+	{0xdd, 0, 5},
+	{0xde, 1, 0},
+	{0xbe, 5, 6},
+	{0xbb, 0, 2},
+	{0xdb, 6, 5},
+	{0xde, 2, 0},
+	{0xbe, 5, 6},
+	{0x3f, 0, 7},
+	{0x7e, 6, 0},
+	{0xde, 7, 5},
+	{0x9f, 0, 6},
+	{0xb7, 5, 3},
+	{0xf6, 6, 0},
+	{0xde, 3, 5},
+	{0x9f, 0, 6},
+	{0xbe, 5, 0},
+	{0xee, 6, 4},
+	{0xcf, 0, 5},
+	{0x9f, 4, 6},
+	{0xbe, 5, 0},
+	{0x7e, 6, 7},
+	{0x5f, 0, 5},
+	{0xde, 7, 0},
+	{0xbe, 5, 6},
+	{0xbd, 0, 1},
+	{0xdd, 6, 5},
+	{0xde, 1, 0},
+	{0xbe, 5, 6},
+	{0xbb, 0, 2},
+	{0xfa, 6, 0},
+	{0xde, 2, 5},
+	{0x9f, 0, 6},
+	{0x3f, 5, 7},
+	{0x7e, 6, 0},
+	{0xde, 7, 5},
+	{0x9f, 0, 6},
+	{0xb7, 5, 3},
+	{0xf6, 6, 0},
+	{0xde, 3, 5},
+	{0x9f, 0, 6},
+	{0xaf, 5, 4},
+};
+
+fal_port_scheduler_cfg_t port_scheduler1_tbl[] = {
+	{0x30, 5, 6},
+	{0x30, 4, 0},
+	{0x30, 5, 6},
+	{0x11, 0, 5},
+	{0x50, 6, 0},
+	{0x30, 5, 6},
+	{0x21, 0, 4},
+	{0x21, 5, 6},
+	{0x30, 4, 0},
+	{0x50, 6, 5},
+	{0x11, 0, 6},
+	{0x30, 5, 0},
+	{0x30, 4, 6},
+	{0x11, 0, 5},
+	{0x50, 6, 0},
+	{0x30, 5, 6},
+	{0x11, 0, 5},
+	{0x11, 4, 6},
+	{0x30, 5, 0},
+	{0x50, 6, 5},
+	{0x11, 0, 6},
+	{0x30, 5, 0},
+	{0x30, 4, 6},
+	{0x11, 0, 5},
+	{0x50, 6, 0},
+};
+
+fal_port_scheduler_cfg_t cppe_port_scheduler0_tbl[] = {
+	{0xb7, 0, 6},
+	{0xbe, 3, 0},
+	{0xde, 6, 5},
+	{0xdd, 0, 1},
+	{0xbd, 5, 6},
+	{0xbe, 1, 0},
+	{0xee, 6, 4},
+	{0xcf, 0, 5},
+	{0x9f, 4, 6},
+	{0xbe, 5, 0},
+	{0x7e, 6, 7},
+	{0x5f, 0, 5},
+	{0x9f, 7, 6},
+	{0xbe, 5, 0},
+	{0xfa, 6, 2},
+	{0xbb, 0, 6},
+	{0x9f, 2, 5},
+	{0xcf, 6, 4},
+	{0xee, 5, 0},
+	{0xbe, 4, 6},
+	{0x3f, 0, 7},
+	{0x5f, 6, 5},
+	{0xde, 7, 0},
+	{0xbe, 5, 6},
+	{0xb7, 0, 3},
+	{0xe7, 6, 4},
+	{0xee, 3, 0},
+	{0xbe, 4, 6},
+	{0x9f, 0, 5},
+	{0xdd, 6, 1},
+	{0xfc, 5, 0},
+	{0xbe, 1, 6},
+	{0x9f, 0, 5},
+	{0x5f, 6, 7},
+	{0x7e, 5, 0},
+	{0xbe, 7, 6},
+	{0xaf, 0, 4},
+	{0xcf, 6, 5},
+	{0x9f, 4, 6},
+	{0xbe, 5, 0},
+	{0xfa, 6, 2},
+	{0xdb, 0, 5},
+	{0x9f, 2, 6},
+	{0xbe, 5, 0},
+	{0x7e, 6, 7},
+	{0x6f, 0, 4},
+	{0xaf, 7, 6},
+	{0x9f, 4, 5},
+	{0xde, 6, 0},
+	{0xf6, 5, 3},
+};
+
+fal_port_tdm_tick_cfg_t port_tdm0_tbl[] = {
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 1},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 3},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 2},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 4},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 4},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 1},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 3},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 2},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+};
+
+fal_port_tdm_tick_cfg_t cppe_port_tdm0_tbl[] = {
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 4},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 1},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 4},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 2},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 3},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 4},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 4},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 1},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 4},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 2},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 3},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 0},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 4},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 5},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 6},
+	{1, FAL_PORT_TDB_DIR_INGRESS, 7},
+	{1, FAL_PORT_TDB_DIR_EGRESS, 7},
+};
+
+static sw_error_t
+qca_hppe_tdm_hw_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_api;
+	a_uint32_t i = 0;
+	a_uint32_t num;
+	fal_port_tdm_ctrl_t tdm_ctrl;
+	fal_port_scheduler_cfg_t *scheduler_cfg;
+	fal_port_tdm_tick_cfg_t *bm_cfg;
+	a_uint8_t tm_tick_mode, bm_tick_mode;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+	SW_RTN_ON_NULL(p_api->adpt_port_scheduler_cfg_set);
+	SW_RTN_ON_NULL(p_api->adpt_tdm_tick_num_set);
+
+	tm_tick_mode = ssdk_tm_tick_mode_get(dev_id);
+	bm_tick_mode = ssdk_bm_tick_mode_get(dev_id);
+
+	if (tm_tick_mode == 0) {
+		if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+			num = sizeof(cppe_port_scheduler0_tbl) /
+				sizeof(fal_port_scheduler_cfg_t);
+			scheduler_cfg = cppe_port_scheduler0_tbl;
+		} else {
+			num = sizeof(port_scheduler0_tbl) /
+				sizeof(fal_port_scheduler_cfg_t);
+			scheduler_cfg = port_scheduler0_tbl;
+		}
+	} else if (tm_tick_mode == 1) {
+		num = sizeof(port_scheduler1_tbl) / sizeof(fal_port_scheduler_cfg_t);
+		scheduler_cfg = port_scheduler1_tbl;
+	} else {
+		return SW_BAD_VALUE;
+	}
+
+	for (i = 0; i < num; i++) {
+		p_api->adpt_port_scheduler_cfg_set(dev_id, i, &scheduler_cfg[i]);
+	}
+	p_api->adpt_tdm_tick_num_set(dev_id, num);
+
+	SW_RTN_ON_NULL(p_api->adpt_port_tdm_tick_cfg_set);
+	SW_RTN_ON_NULL(p_api->adpt_port_tdm_ctrl_set);
+
+	if (bm_tick_mode == 0) {
+		if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+			num = sizeof(cppe_port_tdm0_tbl) /
+				sizeof(fal_port_tdm_tick_cfg_t);
+			bm_cfg = cppe_port_tdm0_tbl;
+		} else {
+			num = sizeof(port_tdm0_tbl) /
+				sizeof(fal_port_tdm_tick_cfg_t);
+			bm_cfg = port_tdm0_tbl;
+		}
+	} else {
+		return SW_BAD_VALUE;
+	}
+	for (i = 0; i < num; i++) {
+		p_api->adpt_port_tdm_tick_cfg_set(dev_id, i, &bm_cfg[i]);
+	}
+	tdm_ctrl.enable = A_TRUE;
+	tdm_ctrl.offset = A_FALSE;
+	tdm_ctrl.depth = num;
+	p_api->adpt_port_tdm_ctrl_set(dev_id, &tdm_ctrl);
+	SSDK_INFO("tdm setup num=%d\n", num);
+	return SW_OK;
+}
+#endif
+
+#if defined(IN_BM)
+static sw_error_t
+qca_hppe_bm_hw_init(a_uint32_t dev_id)
+{
+	a_uint32_t i = 0;
+	fal_bm_dynamic_cfg_t cfg;
+	a_uint32_t chip_ver = 0;
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+
+	for (i = 0; i <  HPPE_BM_PORT_NUM; i++) {
+		/* enable fc */
+		fal_port_bm_ctrl_set(0, i, A_TRUE);
+		/* map to group 0 */
+		fal_port_bufgroup_map_set(0, i, 0);
+	}
+
+	if (chip_ver == CPPE_REVISION) {
+		fal_bm_bufgroup_buffer_set(dev_id, 0, 1024);
+	} else {
+		fal_bm_bufgroup_buffer_set(dev_id, 0, 1400);
+	}
+
+	/* set reserved buffer */
+	for (i = 0; i < HPPE_BM_PHY_PORT_OFFSET; i++) {
+		fal_bm_port_reserved_buffer_set(dev_id, i, 0, 100);
+	}
+	for (i = HPPE_BM_PHY_PORT_OFFSET; i < HPPE_BM_PORT_NUM-1; i++) {
+		fal_bm_port_reserved_buffer_set(dev_id, i, 0, 128);
+	}
+	if (chip_ver == CPPE_REVISION) {
+		fal_bm_port_reserved_buffer_set(dev_id, HPPE_BM_PORT_NUM -2,
+					0, 40);
+	}
+	fal_bm_port_reserved_buffer_set(dev_id, HPPE_BM_PORT_NUM-1, 0, 40);
+
+	memset(&cfg, 0, sizeof(cfg));
+	cfg.resume_min_thresh = 0;
+	cfg.resume_off = 36;
+	cfg.weight= 4;
+	if (chip_ver == CPPE_REVISION) {
+		cfg.shared_ceiling = 216;
+	} else {
+		cfg.shared_ceiling = 250;
+	}
+	for (i = 0; i < HPPE_BM_PORT_NUM; i++) {
+		fal_bm_port_dynamic_thresh_set(dev_id, i, &cfg);
+	}
+	return SW_OK;
+}
+#endif
+
+#if defined(IN_QM)
+static sw_error_t
+qca_hppe_qm_hw_init(a_uint32_t dev_id)
+{
+	a_uint32_t i;
+	fal_ucast_queue_dest_t queue_dst;
+	fal_ac_obj_t obj;
+	fal_ac_ctrl_t ac_ctrl;
+	fal_ac_group_buffer_t group_buff;
+	fal_ac_dynamic_threshold_t  dthresh_cfg;
+	fal_ac_static_threshold_t sthresh_cfg;
+	a_uint32_t qbase = 0;
+	a_uint32_t chip_ver = 0;
+
+	memset(&queue_dst, 0, sizeof(queue_dst));
+
+	chip_ver = adpt_hppe_chip_revision_get(dev_id);
+
+	/*
+	 * Redirect service code 2 to queue 1
+	 * TODO: keep sync with  NSS
+	 */
+	queue_dst.service_code_en = A_TRUE;
+	queue_dst.service_code = 2;
+	fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 8, 0);
+
+	queue_dst.service_code = 3;
+	fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 128, 8);
+
+	queue_dst.service_code = 4;
+	fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 128, 8);
+
+	queue_dst.service_code = 5;
+	fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 0, 0);
+
+	queue_dst.service_code = 6;
+	fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 8, 0);
+
+	queue_dst.service_code = 7;
+	fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 240, 0);
+
+	queue_dst.service_code_en = A_FALSE;
+	queue_dst.service_code = 0;
+	for(i = 0; i < SSDK_MAX_PORT_NUM; i++) {
+		queue_dst.dst_port = i;
+		qbase = ssdk_ucast_queue_start_get(dev_id, i);
+		fal_ucast_queue_base_profile_set(dev_id, &queue_dst, qbase, i);
+	}
+
+	/*
+	 * Enable PPE source profile 1 and map it to PPE queue 4
+	 */
+	memset(&queue_dst, 0, sizeof(queue_dst));
+	queue_dst.src_profile = 1;
+
+	/*
+	 * Enable service code mapping for profile 1
+	 */
+	queue_dst.service_code_en = A_TRUE;
+	for (i = 0; i < SSDK_MAX_SERVICE_CODE_NUM; i++) {
+		queue_dst.service_code = i;
+
+		if (i == 2 || i == 6) {
+			fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 8, 0);
+		} else if (i == 3 || i == 4) {
+			fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 128, 8);
+		} else {
+			fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 4, 0);
+		}
+	}
+	queue_dst.service_code_en = A_FALSE;
+	queue_dst.service_code = 0;
+
+	/*
+	 * Enable cpu code mapping for profile 1
+	 */
+	queue_dst.cpu_code_en = A_TRUE;
+	for (i = 0; i < SSDK_MAX_CPU_CODE_NUM; i++) {
+		queue_dst.cpu_code = i;
+		fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 4, 0);
+	}
+	queue_dst.cpu_code_en = A_FALSE;
+	queue_dst.cpu_code = 0;
+
+	/*
+	 * Enable destination port mappings for profile 1
+	 */
+	for (i = 0; i < SSDK_MAX_PORT_NUM; i++) {
+		queue_dst.dst_port = i;
+		qbase = ssdk_ucast_queue_start_get(dev_id, i);
+		fal_ucast_queue_base_profile_set(dev_id, &queue_dst, qbase, i);
+	}
+
+	for (i = SSDK_MAX_PORT_NUM; i < SSDK_MAX_VIRTUAL_PORT_NUM; i++) {
+		queue_dst.dst_port = i;
+		fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 4, 0);
+	}
+	queue_dst.dst_port = 0;
+
+	/* queue ac*/
+	ac_ctrl.ac_en = A_TRUE;
+	ac_ctrl.ac_fc_en = A_FALSE;
+	for (i = 0; i < SSDK_L0SCHEDULER_CFG_MAX; i++) {
+		obj.type = FAL_AC_QUEUE;
+		obj.obj_id = i;
+		fal_ac_ctrl_set(dev_id, &obj, &ac_ctrl);
+		fal_ac_queue_group_set(dev_id, i, 0);
+		fal_ac_prealloc_buffer_set(dev_id, &obj, 0);
+	}
+
+	group_buff.prealloc_buffer = 0;
+	if (chip_ver == CPPE_REVISION) {
+		group_buff.total_buffer = 1506;
+	} else {
+		group_buff.total_buffer = 2000;
+	}
+	fal_ac_group_buffer_set(dev_id, 0, &group_buff);
+
+	memset(&dthresh_cfg, 0, sizeof(dthresh_cfg));
+	dthresh_cfg.shared_weight = 4;
+	if (chip_ver == CPPE_REVISION) {
+		dthresh_cfg.ceiling = 216;
+	} else {
+		dthresh_cfg.ceiling = 400;
+	}
+	dthresh_cfg.green_resume_off = 36;
+	for (i = 0; i < SSDK_L0SCHEDULER_UCASTQ_CFG_MAX; i++) {
+		fal_ac_dynamic_threshold_set(dev_id, i, &dthresh_cfg);
+	}
+
+	memset(&sthresh_cfg, 0, sizeof(sthresh_cfg));
+	if (chip_ver == CPPE_REVISION) {
+		sthresh_cfg.green_max = 144;
+	} else {
+		sthresh_cfg.green_max = 250;
+	}
+	sthresh_cfg.green_resume_off = 36;
+	for (i = SSDK_L0SCHEDULER_UCASTQ_CFG_MAX; i < SSDK_L0SCHEDULER_CFG_MAX;
+			i++) {
+		obj.type = FAL_AC_QUEUE;
+		obj.obj_id = i;
+		fal_ac_static_threshold_set(dev_id, &obj, &sthresh_cfg);
+	}
+
+	return SW_OK;
+}
+#endif
+
+#if defined(IN_QOS)
+static sw_error_t
+qca_hppe_qos_scheduler_hw_init(a_uint32_t dev_id)
+{
+	a_uint32_t i = 0;
+	fal_qos_scheduler_cfg_t cfg;
+	fal_queue_bmp_t queue_bmp;
+	fal_qos_group_t group_sel;
+	fal_qos_pri_precedence_t pri_pre;
+	ssdk_dt_scheduler_cfg *dt_cfg = ssdk_bootup_shceduler_cfg_get(dev_id);
+
+	memset(&cfg, 0, sizeof(cfg));
+
+	/* L1 shceduler */
+	for (i = 0; i < SSDK_L1SCHEDULER_CFG_MAX; i++) {
+		if (dt_cfg->l1cfg[i].valid) {
+			cfg.sp_id = dt_cfg->l1cfg[i].port_id;
+			cfg.c_pri = dt_cfg->l1cfg[i].cpri;
+			cfg.e_pri = dt_cfg->l1cfg[i].epri;
+			cfg.c_drr_id = dt_cfg->l1cfg[i].cdrr_id;
+			cfg.e_drr_id = dt_cfg->l1cfg[i].edrr_id;
+			cfg.c_drr_wt = 1;
+			cfg.e_drr_wt = 1;
+			fal_queue_scheduler_set(dev_id, i, 1,
+					dt_cfg->l1cfg[i].port_id, &cfg);
+		}
+	}
+
+	/* L0 shceduler */
+	for (i = 0; i < SSDK_L0SCHEDULER_CFG_MAX; i++) {
+		if (dt_cfg->l0cfg[i].valid) {
+			cfg.sp_id = dt_cfg->l0cfg[i].sp_id;
+			cfg.c_pri = dt_cfg->l0cfg[i].cpri;
+			cfg.e_pri = dt_cfg->l0cfg[i].epri;
+			cfg.c_drr_id = dt_cfg->l0cfg[i].cdrr_id;
+			cfg.e_drr_id = dt_cfg->l0cfg[i].edrr_id;
+			cfg.c_drr_wt = 1;
+			cfg.e_drr_wt = 1;
+			fal_queue_scheduler_set(dev_id, i,
+					0, dt_cfg->l0cfg[i].port_id, &cfg);
+		}
+	}
+
+	/* queue--edma ring mapping*/
+	memset(&queue_bmp, 0, sizeof(queue_bmp));
+	queue_bmp.bmp[0] = 0xF;
+	fal_edma_ring_queue_map_set(dev_id, 0, &queue_bmp);
+	queue_bmp.bmp[0] = 0xF0;
+	fal_edma_ring_queue_map_set(dev_id, 3, &queue_bmp);
+	queue_bmp.bmp[0] = 0xF00;
+	fal_edma_ring_queue_map_set(dev_id, 1, &queue_bmp);
+	queue_bmp.bmp[0] = 0;
+	queue_bmp.bmp[4] = 0xFFFF;
+	fal_edma_ring_queue_map_set(dev_id, 2, &queue_bmp);
+
+	/* chose qos group 0 */
+	group_sel.dscp_group = 0;
+	group_sel.flow_group = 0;
+	group_sel.pcp_group = 0;
+	for (i = SSDK_PHYSICAL_PORT0; i <= SSDK_PHYSICAL_PORT7; i++) {
+		fal_qos_port_group_get(dev_id, i, &group_sel);
+	}
+	/* qos precedence */
+	pri_pre.flow_pri = 4;
+	pri_pre.acl_pri = 2;
+	pri_pre.dscp_pri = 1;
+	pri_pre.pcp_pri = 0;
+	pri_pre.preheader_pri = 3;
+	for (i = SSDK_PHYSICAL_PORT0; i <= SSDK_PHYSICAL_PORT7; i++) {
+		fal_qos_port_pri_precedence_set(dev_id, i, &pri_pre);
+	}
+
+	return SW_OK;
+}
+#endif
+
+
+#if defined(IN_ACL)
+#define LIST_ID_BYP_FDB_LRN 63/*reserved for bypass fdb learning*/
+#define LIST_PRI_BYP_FDB_LRN 32
+
+sw_error_t qca_hppe_acl_byp_intf_mac_learn(a_uint32_t dev_id)
+{
+	a_uint32_t index = 0, num;
+	fal_acl_rule_t rule = { 0 };
+	a_uint8_t* mac;
+	a_uint32_t port_bmp = qca_ssdk_port_bmp_get(dev_id);
+
+	num = ssdk_intf_mac_num_get();
+	if(num == 0){
+		return SW_OK;/*No found interface MAC*/
+	}
+
+	/*Bypass fdb learn*/
+	rule.rule_type = FAL_ACL_RULE_MAC;
+	rule.bypass_bitmap |= (1<<FAL_ACL_BYPASS_FDB_LEARNING);
+	rule.bypass_bitmap |= (1<<FAL_ACL_BYPASS_FDB_REFRESH);
+
+	FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_MAC_SA);
+
+	fal_acl_list_creat(dev_id, LIST_ID_BYP_FDB_LRN, LIST_PRI_BYP_FDB_LRN);
+
+	for (index = 0; index < SSDK_MAX_NR_ETH; index++) {
+		if(index >= num)
+			break;
+		mac = ssdk_intf_macaddr_get(index);
+		memcpy(rule.src_mac_val.uc, mac, 6);
+		memset(rule.src_mac_mask.uc, 0xff, 6);
+		SSDK_DEBUG("%02x:%02x:%02x:%02x:%02x:%02x\n", rule.src_mac_val.uc[0],
+			rule.src_mac_val.uc[1], rule.src_mac_val.uc[2], rule.src_mac_val.uc[3],
+			rule.src_mac_val.uc[4], rule.src_mac_val.uc[5]);
+		fal_acl_rule_add(dev_id, LIST_ID_BYP_FDB_LRN, index, 1, &rule);
+	}
+	fal_acl_list_bind(dev_id, LIST_ID_BYP_FDB_LRN, FAL_ACL_DIREC_IN,
+				FAL_ACL_BIND_PORTBITMAP, port_bmp);
+
+	return SW_OK;
+}
+
+#if defined(IN_PTP)
+sw_error_t qca_hppe_acl_remark_ptp_servcode(a_uint32_t dev_id) {
+#define LIST_ID_L2_TAG_SERVICE_CODE_PTP 58
+#define LIST_ID_L4_TAG_SERVICE_CODE_PTP 59
+#define LIST_PRI_TAG_SERVICE_CODE_PTP   1
+#define PTP_EVENT_PKT_SERVICE_CODE      0x9
+#define PTP_EV_PORT                     319
+#define PTP_MSG_SYNC                    0
+#define PTP_MSG_PRESP                   3
+
+	sw_error_t ret;
+	fal_func_ctrl_t func_ctrl, func_ctrl_old;
+	fal_servcode_config_t servcode_conf;
+	fal_acl_rule_t entry = {0};
+	a_uint32_t index = 0, msg_type = 0;
+	a_uint32_t ptp_port_bmp = 0;
+
+	/* only marking ptp packet with service code for the qca808x phy */
+	ptp_port_bmp = qca_ssdk_phy_type_port_bmp_get(dev_id, QCA808X_PHY_CHIP);
+
+	/* Not found the PHY with ptp feature */
+	if (ptp_port_bmp == 0) {
+		return SW_OK;
+	}
+
+	/* Create PTP ACL L2 list */
+	ret = fal_acl_list_creat(dev_id, LIST_ID_L2_TAG_SERVICE_CODE_PTP,
+			LIST_PRI_TAG_SERVICE_CODE_PTP);
+	SW_RTN_ON_ERROR(ret);
+
+	/* Set up UDF2 profile */
+	ret = fal_acl_udf_profile_set(dev_id, FAL_ACL_UDF_NON_IP, 2, FAL_ACL_UDF_TYPE_L3, 0);
+	SW_RTN_ON_ERROR(ret);
+
+	/* Tag service code for PTP packet */
+	entry.service_code = PTP_EVENT_PKT_SERVICE_CODE;
+	entry.pri = LIST_PRI_TAG_SERVICE_CODE_PTP;
+	FAL_ACTION_FLG_SET(entry.action_flg, FAL_ACL_ACTION_SERVICE_CODE);
+	FAL_ACTION_FLG_SET(entry.action_flg, FAL_ACL_ACTION_PERMIT);
+
+	/* L2 PTP packet */
+	entry.rule_type = FAL_ACL_RULE_MAC;
+
+	/* L2 PTP ethernet type 0x88f7 */
+	entry.ethtype_val = ETH_P_1588;
+	entry.ethtype_mask = 0xffff;
+	FAL_FIELD_FLG_SET(entry.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+
+	for (msg_type = PTP_MSG_SYNC; msg_type <= PTP_MSG_PRESP; msg_type++) {
+		/* L2 UDF2 for msg type */
+		entry.udf2_val = (msg_type << 0x8);
+		entry.udf2_mask = 0x0f00;
+		FAL_FIELD_FLG_SET(entry.field_flg, FAL_ACL_FIELD_UDF2);
+
+		/* Add PTP L2 rule to ACL list */
+		ret = fal_acl_rule_add(dev_id, LIST_ID_L2_TAG_SERVICE_CODE_PTP,
+				index++, 1, &entry);
+		SW_RTN_ON_ERROR(ret);
+	}
+
+	/* Unset L2 PTP ethernet type 0x88f7 */
+	index = 0;
+	FAL_FIELD_FLG_CLR(entry.field_flg, FAL_ACL_FIELD_UDF2);
+	FAL_FIELD_FLG_CLR(entry.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+
+	/* Create PTP ACL L4 list */
+	ret = fal_acl_list_creat(dev_id, LIST_ID_L4_TAG_SERVICE_CODE_PTP,
+			LIST_PRI_TAG_SERVICE_CODE_PTP);
+	SW_RTN_ON_ERROR(ret);
+
+	/* IPv4 PTP packet */
+	entry.rule_type = FAL_ACL_RULE_IP4;
+	entry.is_ip_mask = 1;
+	entry.is_ip_val = A_TRUE;
+	FAL_FIELD_FLG_SET(entry.field_flg, FAL_ACL_FIELD_IP);
+	entry.is_ipv6_mask = 1;
+	entry.is_ipv6_val = A_FALSE;
+	FAL_FIELD_FLG_SET(entry.field_flg, FAL_ACL_FIELD_IPV6);
+
+	/* PTP over UDP protocol */
+	entry.ip_proto_val = IPPROTO_UDP;
+	entry.ip_proto_mask = 0xff;
+	FAL_FIELD_FLG_SET(entry.field_flg, FAL_ACL_FIELD_IP_PROTO);
+
+	/* PTP UDP dest port 319 */
+	entry.dest_l4port_op = FAL_ACL_FIELD_MASK;
+	entry.dest_l4port_val = PTP_EV_PORT;
+	entry.dest_l4port_mask = 0xffff;
+	FAL_FIELD_FLG_SET(entry.field_flg, FAL_ACL_FIELD_L4_DPORT);
+
+	/* Add PTP IPv4 rule to ACL list */
+	ret = fal_acl_rule_add(dev_id, LIST_ID_L4_TAG_SERVICE_CODE_PTP, index++, 1, &entry);
+	SW_RTN_ON_ERROR(ret);
+
+	/* IPv6 PTP packet */
+	entry.rule_type = FAL_ACL_RULE_IP6;
+	entry.is_ipv6_val = A_TRUE;
+
+	/* Add PTP IPv6 rule to ACL list */
+	ret = fal_acl_rule_add(dev_id, LIST_ID_L4_TAG_SERVICE_CODE_PTP, index++, 1, &entry);
+	SW_RTN_ON_ERROR(ret);
+
+	/* Bind PTP ACL list to port bmp */
+	ret = fal_acl_list_bind(dev_id, LIST_ID_L2_TAG_SERVICE_CODE_PTP,
+			FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORTBITMAP, ptp_port_bmp);
+	SW_RTN_ON_ERROR(ret);
+	ret = fal_acl_list_bind(dev_id, LIST_ID_L4_TAG_SERVICE_CODE_PTP,
+			FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORTBITMAP, ptp_port_bmp);
+	SW_RTN_ON_ERROR(ret);
+
+	/* enable service code module temporarily */
+	ret = fal_module_func_ctrl_get(dev_id, FAL_MODULE_SERVCODE, &func_ctrl_old);
+	SW_RTN_ON_ERROR(ret);
+	func_ctrl.bitmap[0] = (1<<FUNC_SERVCODE_CONFIG_SET) | (1<<FUNC_SERVCODE_CONFIG_GET);
+	ret = fal_module_func_ctrl_set(dev_id, FAL_MODULE_SERVCODE, &func_ctrl);
+	SW_RTN_ON_ERROR(ret);
+
+	/* configure the next service code of ptp service code, which
+	 * is needed for EDMA receiving the packet with service code.
+	 */
+	ret = fal_servcode_config_get(dev_id, PTP_EVENT_PKT_SERVICE_CODE, &servcode_conf);
+	SW_RTN_ON_ERROR(ret);
+	servcode_conf.next_service_code = PTP_EVENT_PKT_SERVICE_CODE;
+	ret = fal_servcode_config_set(dev_id, PTP_EVENT_PKT_SERVICE_CODE, &servcode_conf);
+	SW_RTN_ON_ERROR(ret);
+
+	/* restore service code module feature bitmap */
+	ret = fal_module_func_ctrl_set(dev_id, FAL_MODULE_SERVCODE, &func_ctrl_old);
+
+	return ret;
+}
+#endif
+#endif
+
+static sw_error_t
+qca_hppe_interface_mode_init(a_uint32_t dev_id, a_uint32_t mode0, a_uint32_t mode1, a_uint32_t mode2)
+{
+
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+	fal_port_t port_id;
+	a_uint32_t port_max = SSDK_PHYSICAL_PORT7;
+	a_uint32_t index = 0, mode[3] = {mode0, mode1, mode2};
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+	SW_RTN_ON_NULL(p_api->adpt_port_mux_mac_type_set);
+	SW_RTN_ON_NULL(p_api->adpt_uniphy_mode_set);
+
+
+	rv = p_api->adpt_uniphy_mode_set(dev_id, SSDK_UNIPHY_INSTANCE0, mode0);
+	SW_RTN_ON_ERROR(rv);
+
+	rv = p_api->adpt_uniphy_mode_set(dev_id, SSDK_UNIPHY_INSTANCE1, mode1);
+	SW_RTN_ON_ERROR(rv);
+
+	if(adpt_hppe_chip_revision_get(dev_id) == HPPE_REVISION) {
+		rv = p_api->adpt_uniphy_mode_set(dev_id,
+			SSDK_UNIPHY_INSTANCE2, mode2);
+		SW_RTN_ON_ERROR(rv);
+	}
+	for (index = SSDK_UNIPHY_INSTANCE0; index <= SSDK_UNIPHY_INSTANCE2; index ++) {
+		if (mode[index] == PORT_WRAPPER_MAX) {
+			ssdk_gcc_uniphy_sys_set(dev_id, index, A_FALSE);
+		}
+	}
+
+	if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+		port_max = SSDK_PHYSICAL_PORT6;
+	} else {
+		port_max = SSDK_PHYSICAL_PORT7;
+	}
+	for(port_id = SSDK_PHYSICAL_PORT1; port_id < port_max; port_id++) {
+		rv = p_api->adpt_port_mux_mac_type_set(dev_id, port_id, mode0, mode1, mode2);
+		if(rv != SW_OK) {
+			SSDK_ERROR("port_id:%d, mode0:%d, mode1:%d, mode2:%d\n", port_id, mode0, mode1, mode2);
+			break;
+		}
+	}
+
+	return rv;
+}
+
+
+#if defined(IN_FLOW)
+static sw_error_t
+qca_hppe_flow_hw_init(a_uint32_t dev_id)
+{
+	fal_flow_direction_t dir, dir_max;
+	fal_flow_mgmt_t mgmt;
+	sw_error_t rv;
+
+	memset(&mgmt, 0, sizeof(fal_flow_mgmt_t));
+	dir_max = FAL_FLOW_UNKOWN_DIR_DIR;
+
+	/*set redirect to cpu for multicast flow*/
+	for (dir = FAL_FLOW_LAN_TO_LAN_DIR; dir <= dir_max; dir++) {
+		rv = fal_flow_mgmt_get(dev_id, FAL_FLOW_MCAST, dir, &mgmt);
+		SW_RTN_ON_ERROR(rv);
+		mgmt.miss_action = FAL_MAC_RDT_TO_CPU;
+		rv = fal_flow_mgmt_set(dev_id, FAL_FLOW_MCAST, dir, &mgmt);
+		SW_RTN_ON_ERROR(rv);
+	}
+	return SW_OK;
+}
+#endif
+
+sw_error_t qca_hppe_hw_init(ssdk_init_cfg *cfg, a_uint32_t dev_id)
+{
+	sw_error_t rv = SW_OK;
+
+	/* reset ppe */
+	ssdk_ppe_reset_init();
+
+	rv = qca_switch_init(dev_id);
+	SW_RTN_ON_ERROR(rv);
+
+#if defined(IN_BM)
+	rv = qca_hppe_bm_hw_init(dev_id);
+	SW_RTN_ON_ERROR(rv);
+#endif
+#if defined(IN_QM)
+	rv = qca_hppe_qm_hw_init(dev_id);
+	SW_RTN_ON_ERROR(rv);
+#endif
+#if defined(IN_QOS)
+	rv = qca_hppe_qos_scheduler_hw_init(dev_id);
+	SW_RTN_ON_ERROR(rv);
+#endif
+#if defined(IN_BM) && defined(IN_QOS)
+	rv = qca_hppe_tdm_hw_init(dev_id);
+	SW_RTN_ON_ERROR(rv);
+#endif
+#if defined(IN_FDB)
+	rv= qca_hppe_fdb_hw_init(dev_id);
+	SW_RTN_ON_ERROR(rv);
+#endif
+#if defined(IN_VSI)
+	rv= qca_hppe_vsi_hw_init(dev_id);
+	SW_RTN_ON_ERROR(rv);
+#endif
+#if defined(IN_PORTVLAN)
+	rv = qca_hppe_portvlan_hw_init(dev_id);
+	SW_RTN_ON_ERROR(rv);
+#endif
+#if defined(IN_PORTCONTROL)
+	rv = qca_hppe_portctrl_hw_init(dev_id);
+	SW_RTN_ON_ERROR(rv);
+#endif
+#if defined(IN_POLICER)
+	rv = qca_hppe_policer_hw_init(dev_id);
+	SW_RTN_ON_ERROR(rv);
+#endif
+#if defined(IN_SHAPER)
+	rv = qca_hppe_shaper_hw_init(dev_id);
+	SW_RTN_ON_ERROR(rv);
+#endif
+#if defined(IN_FLOW)
+	rv = qca_hppe_flow_hw_init(dev_id);
+	SW_RTN_ON_ERROR(rv);
+#endif
+#if defined(IN_ACL)
+	rv = qca_hppe_acl_byp_intf_mac_learn(dev_id);
+	SW_RTN_ON_ERROR(rv);
+#if defined(IN_PTP)
+	rv = qca_hppe_acl_remark_ptp_servcode(dev_id);
+	SW_RTN_ON_ERROR(rv);
+#endif
+#endif
+	rv = qca_hppe_interface_mode_init(dev_id, cfg->mac_mode, cfg->mac_mode1,
+				cfg->mac_mode2);
+	SW_RTN_ON_ERROR(rv);
+#if defined(IN_CTRLPKT)
+	rv = qca_hppe_ctlpkt_hw_init(dev_id);
+	SW_RTN_ON_ERROR(rv);
+#endif
+
+	return rv;
+}
+
diff --git a/qca-ssdk/src/init/ssdk_init.c b/qca-ssdk/src/init/ssdk_init.c
new file mode 100755
index 0000000..5a01b86
--- /dev/null
+++ b/qca-ssdk/src/init/ssdk_init.c
@@ -0,0 +1,3698 @@
+/*
+ * Copyright (c) 2012, 2014-2021, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*qca808x_start*/
+#include "sw.h"
+#include "ssdk_init.h"
+#include "fal_init.h"
+#include "fal.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_phy.h"
+/*qca808x_end*/
+#include "ssdk_dts.h"
+#include "ssdk_interrupt.h"
+#include <linux/kconfig.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+/*qca808x_start*/
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+/*qca808x_end*/
+//#include <asm/mach-types.h>
+#include <generated/autoconf.h>
+#include <linux/if_arp.h>
+#include <linux/inetdevice.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+/*qca808x_start*/
+#include <linux/phy.h>
+#include <linux/mdio.h>
+/*qca808x_end*/
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+
+#if defined(IN_SWCONFIG)
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#include <linux/switch.h>
+#else
+#include <net/switch.h>
+#endif
+#endif
+
+#if defined(ISIS) ||defined(ISISC) ||defined(GARUDA)
+#include <f1_phy.h>
+#endif
+#if defined(ATHENA) ||defined(SHIVA) ||defined(HORUS)
+#include <f2_phy.h>
+#endif
+#ifdef IN_MALIBU_PHY
+#include <malibu_phy.h>
+#endif
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0))
+/*qca808x_start*/
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_net.h>
+#include <linux/of_address.h>
+#include <linux/reset.h>
+/*qca808x_end*/
+#ifdef BOARD_AR71XX
+#ifdef CONFIG_AR8216_PHY
+#include "drivers/net/phy/ar8327.h"
+#endif
+#include "drivers/net/ethernet/atheros/ag71xx/ag71xx.h"
+#endif
+#elif defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_net.h>
+#include <linux/of_address.h>
+#include <linux/reset.h>
+#else
+#include <linux/ar8216_platform.h>
+#include <drivers/net/phy/ar8216.h>
+#include <drivers/net/ethernet/atheros/ag71xx/ag71xx.h>
+#endif
+/*qca808x_start*/
+#include "ssdk_plat.h"
+/*qca808x_end*/
+#include "ssdk_clk.h"
+#include "ssdk_led.h"
+#include "ref_vlan.h"
+#include "ref_fdb.h"
+#include "ref_mib.h"
+#include "ref_port_ctrl.h"
+#include "ref_misc.h"
+#include "ref_uci.h"
+#include "ref_vsi.h"
+#include "shell.h"
+#ifdef BOARD_AR71XX
+#include "ssdk_uci.h"
+#endif
+/*qca808x_start*/
+#if defined(IN_PHY_I2C_MODE)
+#include "ssdk_phy_i2c.h"
+#endif
+/*qca808x_end*/
+#ifdef IN_IP
+#if defined (CONFIG_NF_FLOW_COOKIE)
+#include "fal_flowcookie.h"
+#ifdef IN_SFE
+#include <shortcut-fe/sfe.h>
+#endif
+#endif
+#endif
+
+#ifdef IN_RFS
+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+#include <linux/if_vlan.h>
+#endif
+#include <qca-rfs/rfs_dev.h>
+#ifdef IN_IP
+#include "fal_rfs.h"
+#endif
+#endif
+#include "adpt.h"
+#ifdef HPPE
+#include "ssdk_hppe.h"
+#endif
+#ifdef SCOMPHY
+#include "ssdk_scomphy.h"
+#endif
+
+#ifdef IN_RFS
+struct rfs_device rfs_dev;
+struct notifier_block ssdk_inet_notifier;
+ssdk_rfs_intf_t rfs_intf_tbl[SSDK_RFS_INTF_MAX] = {{0}};
+#endif
+
+//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+struct notifier_block ssdk_dev_notifier;
+//#endif
+
+
+extern ssdk_chip_type SSDK_CURRENT_CHIP_TYPE;
+extern a_uint32_t hsl_dev_wan_port_get(a_uint32_t dev_id);
+extern void dess_rgmii_sw_mac_polling_task(struct qca_phy_priv *priv);
+extern void qca_ar8327_sw_mac_polling_task(struct qca_phy_priv *priv);
+extern void qca_ar8327_sw_mib_task(struct qca_phy_priv *priv);
+
+//#define PSGMII_DEBUG
+
+#define QCA_QM_WORK_DELAY	100
+#define QCA_QM_ITEM_NUMBER 41
+#define QCA_RGMII_WORK_DELAY	1000
+#define QCA_MAC_SW_SYNC_WORK_DELAY	1000
+#ifdef DESS
+static bool qca_dess_rfs_registered = false;
+#endif
+/*qca808x_start*/
+struct qca_phy_priv **qca_phy_priv_global;
+
+struct qca_phy_priv* ssdk_phy_priv_data_get(a_uint32_t dev_id)
+{
+	if (dev_id >= SW_MAX_NR_DEV || !qca_phy_priv_global)
+		return NULL;
+
+	return qca_phy_priv_global[dev_id];
+}
+/*qca808x_end*/
+
+a_uint32_t hppe_port_type[6] = {0,0,0,0,0,0}; // this variable should be init by ssdk_init
+
+a_uint32_t
+qca_hppe_port_mac_type_get(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	if ((port_id < 1) || (port_id > 6))
+		return 0;
+	return hppe_port_type[port_id - 1];
+}
+
+a_uint32_t
+qca_hppe_port_mac_type_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t port_type)
+{
+	 if ((port_id < 1) || (port_id > 6))
+		 return 0;
+	hppe_port_type[port_id - 1] = port_type;
+
+	return 0;
+}
+
+#ifndef BOARD_AR71XX
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+static void
+ssdk_phy_rgmii_set(struct qca_phy_priv *priv)
+{
+	struct device_node *np = NULL;
+	u32 rgmii_en = 0, tx_delay = 0, rx_delay = 0;
+
+	if (priv->ess_switch_flag == A_TRUE)
+		np = priv->of_node;
+	else
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+		np = priv->phy->mdio.dev.of_node;
+#else
+		np = priv->phy->dev.of_node;
+#endif
+
+	if (!np)
+		return;
+
+	if (!of_property_read_u32(np, "phy_rgmii_en", &rgmii_en)) {
+		a_uint16_t val = 0;
+		/*enable RGMII  mode */
+		qca_ar8327_phy_dbg_read(0, AR8327_PORT5_PHY_ADDR,
+				AR8327_PHY_REG_MODE_SEL, &val);
+		val |= AR8327_PHY_RGMII_MODE;
+		qca_ar8327_phy_dbg_write(0, AR8327_PORT5_PHY_ADDR,
+				AR8327_PHY_REG_MODE_SEL, val);
+		if (!of_property_read_u32(np, "txclk_delay_en", &tx_delay)
+				&& tx_delay == 1) {
+			qca_ar8327_phy_dbg_read(0, AR8327_PORT5_PHY_ADDR,
+					AR8327_PHY_REG_SYS_CTRL, &val);
+			val |= AR8327_PHY_RGMII_TX_DELAY;
+			qca_ar8327_phy_dbg_write(0, AR8327_PORT5_PHY_ADDR,
+					AR8327_PHY_REG_SYS_CTRL, val);
+		}
+		if (!of_property_read_u32(np, "rxclk_delay_en", &rx_delay)
+				&& rx_delay == 1) {
+			qca_ar8327_phy_dbg_read(0, AR8327_PORT5_PHY_ADDR,
+					AR8327_PHY_REG_TEST_CTRL, &val);
+			val |= AR8327_PHY_RGMII_RX_DELAY;
+			qca_ar8327_phy_dbg_write(0, AR8327_PORT5_PHY_ADDR,
+					AR8327_PHY_REG_TEST_CTRL, val);
+		}
+	}
+}
+#else
+static void
+ssdk_phy_rgmii_set(struct qca_phy_priv *priv)
+{
+	struct ar8327_platform_data *plat_data;
+
+	plat_data = priv->phy->dev.platform_data;
+	if (plat_data == NULL) {
+		return;
+	}
+
+	if(plat_data->pad5_cfg) {
+		if(plat_data->pad5_cfg->mode == AR8327_PAD_PHY_RGMII) {
+			a_uint16_t val = 0;
+			/*enable RGMII  mode */
+			priv->phy_dbg_read(0, AR8327_PORT5_PHY_ADDR,
+					AR8327_PHY_REG_MODE_SEL, &val);
+			val |= AR8327_PHY_RGMII_MODE;
+			priv->phy_dbg_write(0, AR8327_PORT5_PHY_ADDR,
+					AR8327_PHY_REG_MODE_SEL, val);
+			if(plat_data->pad5_cfg->txclk_delay_en) {
+				priv->phy_dbg_read(0, AR8327_PORT5_PHY_ADDR,
+						AR8327_PHY_REG_SYS_CTRL, &val);
+				val |= AR8327_PHY_RGMII_TX_DELAY;
+				priv->phy_dbg_write(0, AR8327_PORT5_PHY_ADDR,
+						AR8327_PHY_REG_SYS_CTRL, val);
+			}
+			if(plat_data->pad5_cfg->rxclk_delay_en) {
+				priv->phy_dbg_read(0, AR8327_PORT5_PHY_ADDR,
+						AR8327_PHY_REG_TEST_CTRL, &val);
+				val |= AR8327_PHY_RGMII_RX_DELAY;
+				priv->phy_dbg_write(0, AR8327_PORT5_PHY_ADDR,
+						AR8327_PHY_REG_TEST_CTRL, val);
+			}
+		}
+	}
+}
+#endif
+#endif
+
+
+static void
+qca_ar8327_phy_fixup(struct qca_phy_priv *priv, int phy)
+{
+	switch (priv->revision) {
+	case 1:
+		/* 100m waveform */
+		priv->phy_dbg_write(priv->device_id, phy, 0, 0x02ea);
+		/* turn on giga clock */
+		priv->phy_dbg_write(priv->device_id, phy, 0x3d, 0x68a0);
+		break;
+
+	case 2:
+		priv->phy_mmd_write(priv->device_id, phy, 0x7, 0x3c);
+		priv->phy_mmd_write(priv->device_id, phy, 0x4007, 0x0);
+		/* fallthrough */
+	case 4:
+		if(priv->version == QCA_VER_AR8327)
+		{
+			priv->phy_mmd_write(priv->device_id, phy, 0x3, 0x800d);
+			priv->phy_mmd_write(priv->device_id, phy, 0x4003, 0x803f);
+
+			priv->phy_dbg_write(priv->device_id, phy, 0x3d, 0x6860);
+			priv->phy_dbg_write(priv->device_id, phy, 0x5, 0x2c46);
+			priv->phy_dbg_write(priv->device_id, phy, 0x3c, 0x6000);
+		}
+		break;
+	}
+}
+
+#ifdef IN_PORTVLAN
+static void qca_port_isolate(a_uint32_t dev_id)
+{
+	a_uint32_t port_id, mem_port_id, mem_port_map[AR8327_NUM_PORTS]={0};
+
+	for(port_id = 0; port_id < AR8327_NUM_PORTS; port_id++)
+	{
+		if(port_id == 6)
+			for(mem_port_id = 1; mem_port_id<= 4; mem_port_id++)
+				mem_port_map[port_id]  |= (1 << mem_port_id);
+		else if (port_id == 0)
+			mem_port_map[port_id]  |= (1 << 5);
+		else if (port_id >= 1 && port_id <= 4)
+			mem_port_map[port_id]  |= (1 << 6);
+		else
+			mem_port_map[port_id]  |= 1;
+	}
+
+	for(port_id = 0; port_id < AR8327_NUM_PORTS; port_id++)
+
+		 fal_portvlan_member_update(dev_id, port_id, mem_port_map[port_id]);
+
+}
+
+void ssdk_portvlan_init(a_uint32_t dev_id)
+{
+	a_uint32_t port = 0;
+	a_uint32_t cpu_bmp, lan_bmp, wan_bmp;
+
+	cpu_bmp = ssdk_cpu_bmp_get(dev_id);
+	lan_bmp = ssdk_lan_bmp_get(dev_id);
+	wan_bmp = ssdk_wan_bmp_get(dev_id);
+
+	if (!(cpu_bmp | lan_bmp | wan_bmp)) {
+		qca_port_isolate(dev_id);
+		return;
+	}
+
+	for(port = 0; port < SSDK_MAX_PORT_NUM; port++)
+	{
+		if(cpu_bmp & (1 << port))
+		{
+			fal_portvlan_member_update(dev_id, port, lan_bmp|wan_bmp);
+		}
+		if(lan_bmp & (1 << port))
+		{
+			fal_portvlan_member_update(dev_id, port, (lan_bmp|cpu_bmp)&(~(1<<port)));
+		}
+		if(wan_bmp & (1 << port))
+		{
+			fal_portvlan_member_update(dev_id, port, (wan_bmp|cpu_bmp)&(~(1<<port)));
+		}
+	}
+}
+#endif
+
+sw_error_t
+qca_switch_init(a_uint32_t dev_id)
+{
+#if (defined(DESS) || defined(ISISC) || defined(ISIS)) && defined(IN_QOS)
+	a_uint32_t nr = 0;
+#endif
+	int i = 0;
+
+	/*fal_reset(dev_id);*/
+	/*enable cpu and disable mirror*/
+#ifdef IN_MISC
+	fal_cpu_port_status_set(dev_id, A_TRUE);
+	/* setup MTU */
+	fal_frame_max_size_set(dev_id, 1518);
+#endif
+#ifdef IN_MIB
+	/* Enable MIB counters */
+	fal_mib_status_set(dev_id, A_TRUE);
+	fal_mib_cpukeep_set(dev_id, A_FALSE);
+#endif
+#ifdef IN_IGMP
+	fal_igmp_mld_rp_set(dev_id, 0);
+#endif
+
+	/*enable pppoe for dakota to support RSS*/
+	if (SSDK_CURRENT_CHIP_TYPE == CHIP_DESS) {
+#ifdef DESS
+#ifdef IN_PPPOE
+		fal_pppoe_status_set(dev_id, A_TRUE);
+#endif
+#endif
+	}
+
+	for (i = 0; i < AR8327_NUM_PORTS; i++) {
+		/* forward multicast and broadcast frames to CPU */
+#ifdef IN_MISC
+		fal_port_unk_uc_filter_set(dev_id, i, A_FALSE);
+		fal_port_unk_mc_filter_set(dev_id, i, A_FALSE);
+		fal_port_bc_filter_set(dev_id, i, A_FALSE);
+#endif
+#ifdef IN_PORTVLAN
+		fal_port_default_svid_set(dev_id, i, 0);
+		fal_port_default_cvid_set(dev_id, i, 0);
+		fal_port_1qmode_set(dev_id, i, FAL_1Q_DISABLE);
+		fal_port_egvlanmode_set(dev_id, i, FAL_EG_UNMODIFIED);
+#endif
+
+#ifdef IN_FDB
+		fal_fdb_port_learn_set(dev_id, i, A_TRUE);
+#endif
+#ifdef IN_STP
+		fal_stp_port_state_set(dev_id, 0, i, FAL_STP_FARWARDING);
+#endif
+#ifdef IN_PORTVLAN
+		fal_port_vlan_propagation_set(dev_id, i, FAL_VLAN_PROPAGATION_REPLACE);
+#endif
+#ifdef IN_IGMP
+		fal_port_igmps_status_set(dev_id, i, A_FALSE);
+		fal_port_igmp_mld_join_set(dev_id, i, A_FALSE);
+		fal_port_igmp_mld_leave_set(dev_id, i, A_FALSE);
+		fal_igmp_mld_entry_creat_set(dev_id, A_FALSE);
+		fal_igmp_mld_entry_v3_set(dev_id, A_FALSE);
+#endif
+		if (SSDK_CURRENT_CHIP_TYPE == CHIP_SHIVA) {
+			return SW_OK;
+		} else if (SSDK_CURRENT_CHIP_TYPE == CHIP_DESS) {
+#ifdef DESS
+#ifdef IN_PORTCONTROL
+			fal_port_flowctrl_forcemode_set(dev_id, i, A_FALSE);
+			fal_port_link_forcemode_set(dev_id, i, A_TRUE);
+#endif
+#ifdef IN_QOS
+			nr = 240; /*30*8*/
+			fal_qos_port_tx_buf_nr_set(dev_id, i, &nr);
+			nr = 48; /*6*8*/
+			fal_qos_port_rx_buf_nr_set(dev_id, i, &nr);
+			fal_qos_port_red_en_set(dev_id, i, A_TRUE);
+			nr = 32;
+			fal_qos_queue_tx_buf_nr_set(dev_id, i, 5, &nr);
+			fal_qos_queue_tx_buf_nr_set(dev_id, i, 4, &nr);
+			fal_qos_queue_tx_buf_nr_set(dev_id, i, 3, &nr);
+			fal_qos_queue_tx_buf_nr_set(dev_id, i, 2, &nr);
+			fal_qos_queue_tx_buf_nr_set(dev_id, i, 1, &nr);
+			fal_qos_queue_tx_buf_nr_set(dev_id, i, 0, &nr);
+			if (i != SSDK_PHYSICAL_PORT0)
+				fal_qos_port_mode_set(dev_id, i,
+					FAL_QOS_DSCP_MODE, A_TRUE);
+#endif
+#endif
+		} else if (SSDK_CURRENT_CHIP_TYPE == CHIP_ISISC ||
+			SSDK_CURRENT_CHIP_TYPE == CHIP_ISIS) {
+#if defined(ISISC) || defined(ISIS)
+#ifdef IN_INTERFACECONTROL
+			fal_port_3az_status_set(dev_id, i, A_FALSE);
+#endif
+#ifdef IN_PORTCONTROL
+			fal_port_flowctrl_forcemode_set(dev_id, i, A_TRUE);
+			fal_port_flowctrl_set(dev_id, i, A_FALSE);
+
+			if (i != 0 && i != 6) {
+				fal_port_flowctrl_set(dev_id, i, A_TRUE);
+				fal_port_flowctrl_forcemode_set(dev_id, i, A_FALSE);
+			}
+#endif
+			if (i == 0 || i == 5 || i == 6) {
+#ifdef IN_QOS
+				nr = 240; /*30*8*/
+				fal_qos_port_tx_buf_nr_set(dev_id, i, &nr);
+				nr = 48; /*6*8*/
+				fal_qos_port_rx_buf_nr_set(dev_id, i, &nr);
+				fal_qos_port_red_en_set(dev_id, i, A_TRUE);
+				if (SSDK_CURRENT_CHIP_TYPE == CHIP_ISISC) {
+					nr = 64; /*8*8*/
+				} else if (SSDK_CURRENT_CHIP_TYPE == CHIP_ISIS) {
+					nr = 60;
+				}
+				fal_qos_queue_tx_buf_nr_set(dev_id, i, 5, &nr);
+				nr = 48; /*6*8*/
+				fal_qos_queue_tx_buf_nr_set(dev_id, i, 4, &nr);
+				nr = 32; /*4*8*/
+				fal_qos_queue_tx_buf_nr_set(dev_id, i, 3, &nr);
+				nr = 32; /*4*8*/
+				fal_qos_queue_tx_buf_nr_set(dev_id, i, 2, &nr);
+				nr = 32; /*4*8*/
+				fal_qos_queue_tx_buf_nr_set(dev_id, i, 1, &nr);
+				nr = 24; /*3*8*/
+				fal_qos_queue_tx_buf_nr_set(dev_id, i, 0, &nr);
+#endif
+			} else {
+#ifdef IN_QOS
+				nr = 200; /*25*8*/
+				fal_qos_port_tx_buf_nr_set(dev_id, i, &nr);
+				nr = 48; /*6*8*/
+				fal_qos_port_rx_buf_nr_set(dev_id, i, &nr);
+				fal_qos_port_red_en_set(dev_id, i, A_TRUE);
+				if (SSDK_CURRENT_CHIP_TYPE == CHIP_ISISC) {
+					nr = 64; /*8*8*/
+				} else if (SSDK_CURRENT_CHIP_TYPE == CHIP_ISIS) {
+					nr = 60;
+				}
+				fal_qos_queue_tx_buf_nr_set(dev_id, i, 3, &nr);
+				nr = 48; /*6*8*/
+				fal_qos_queue_tx_buf_nr_set(dev_id, i, 2, &nr);
+				nr = 32; /*4*8*/
+				fal_qos_queue_tx_buf_nr_set(dev_id, i, 1, &nr);
+				nr = 24; /*3*8*/
+				fal_qos_queue_tx_buf_nr_set(dev_id, i, 0, &nr);
+#endif
+			}
+#endif
+		}
+	}
+
+	return SW_OK;
+}
+
+void qca_ar8327_phy_linkdown(a_uint32_t dev_id)
+{
+	int i;
+	a_uint16_t phy_val;
+
+	for (i = 0; i < AR8327_NUM_PHYS; i++) {
+		qca_ar8327_phy_write(dev_id, i, 0x0, 0x0800);	// phy powerdown
+
+		qca_ar8327_phy_dbg_read(dev_id, i, 0x3d, &phy_val);
+		phy_val &= ~0x0040;
+		qca_ar8327_phy_dbg_write(dev_id, i, 0x3d, phy_val);
+
+		/*PHY will stop the tx clock for a while when link is down
+			1. en_anychange  debug port 0xb bit13 = 0  //speed up link down tx_clk
+			2. sel_rst_80us  debug port 0xb bit10 = 0  //speed up speed mode change to 2'b10 tx_clk
+		*/
+		qca_ar8327_phy_dbg_read(dev_id, i, 0xb, &phy_val);
+		phy_val &= ~0x2400;
+		qca_ar8327_phy_dbg_write(dev_id, i, 0xb, phy_val);
+	}
+}
+
+void
+qca_mac_disable(a_uint32_t device_id)
+{
+	hsl_api_t *p_api;
+
+	p_api = hsl_api_ptr_get (device_id);
+	if(p_api
+		&& p_api->interface_mac_pad_set
+		&& p_api->interface_mac_sgmii_set)
+	{
+		p_api->interface_mac_pad_set(device_id,0,0);
+		p_api->interface_mac_pad_set(device_id,5,0);
+		p_api->interface_mac_pad_set(device_id,6,0);
+		p_api->interface_mac_sgmii_set(device_id,AR8327_REG_PAD_SGMII_CTRL_HW_INIT);
+	}
+	else
+	{
+		SSDK_ERROR("API not support \n");
+	}
+}
+
+static void qca_switch_set_mac_force(struct qca_phy_priv *priv)
+{
+	a_uint32_t value, value0, i;
+	if (priv == NULL || (priv->mii_read == NULL) || (priv->mii_write == NULL)) {
+		SSDK_ERROR("In qca_switch_set_mac_force, private data is NULL!\r\n");
+		return;
+	}
+
+	for (i=0; i < AR8327_NUM_PORTS; ++i) {
+		/* b3:2=0,Tx/Rx Mac disable,
+		 b9=0,LINK_EN disable */
+		value0 = priv->mii_read(priv->device_id, AR8327_REG_PORT_STATUS(i));
+		value = value0 & ~(AR8327_PORT_STATUS_LINK_AUTO |
+						AR8327_PORT_STATUS_TXMAC |
+						AR8327_PORT_STATUS_RXMAC);
+		priv->mii_write(priv->device_id, AR8327_REG_PORT_STATUS(i), value);
+
+		/* Force speed to 1000M Full */
+		value = priv->mii_read(priv->device_id, AR8327_REG_PORT_STATUS(i));
+		value &= ~(AR8327_PORT_STATUS_DUPLEX | AR8327_PORT_STATUS_SPEED);
+		value |= AR8327_PORT_SPEED_1000M | AR8327_PORT_STATUS_DUPLEX;
+		priv->mii_write(priv->device_id, AR8327_REG_PORT_STATUS(i), value);
+	}
+	return;
+}
+
+void
+qca_ar8327_phy_enable(struct qca_phy_priv *priv)
+{
+	int i = 0;
+#ifndef BOARD_AR71XX
+        ssdk_phy_rgmii_set(priv);
+#endif
+	for (i = 0; i < AR8327_NUM_PHYS; i++) {
+		a_uint16_t value = 0;
+
+		if (priv->version == QCA_VER_AR8327 || priv->version == QCA_VER_AR8337)
+			qca_ar8327_phy_fixup(priv, i);
+
+		/* start autoneg*/
+		priv->phy_write(priv->device_id, i, MII_ADVERTISE, ADVERTISE_ALL |
+						     ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
+		//phy reg 0x9, b10,1 = Prefer multi-port device (master)
+		priv->phy_write(priv->device_id, i, MII_CTRL1000, (0x0400|ADVERTISE_1000FULL));
+
+		priv->phy_write(priv->device_id, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+
+		priv->phy_dbg_read(priv->device_id, i, 0, &value);
+		value &= (~(1<<12));
+		priv->phy_dbg_write(priv->device_id, i, 0, value);
+
+		msleep(100);
+	}
+}
+void qca_ar8327_sw_soft_reset(struct qca_phy_priv *priv)
+{
+	a_uint32_t value = 0;
+
+	value = priv->mii_read(priv->device_id, AR8327_REG_CTRL);
+	value |= 0x80000000;
+	priv->mii_write(priv->device_id, AR8327_REG_CTRL, value);
+	/*Need wait reset done*/
+	do {
+		udelay(10);
+		value = priv->mii_read(priv->device_id, AR8327_REG_CTRL);
+	} while(value & AR8327_CTRL_RESET);
+	do {
+		udelay(10);
+		value = priv->mii_read(priv->device_id, 0x20);
+	} while ((value & SSDK_GLOBAL_INITIALIZED_STATUS) !=
+			SSDK_GLOBAL_INITIALIZED_STATUS);
+
+	return;
+}
+
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+int qca_ar8327_hw_init(struct qca_phy_priv *priv)
+{
+	struct device_node *np = NULL;
+	const __be32 *paddr;
+	a_uint32_t reg, value, i;
+	a_int32_t len;
+
+	if (priv->ess_switch_flag == A_TRUE)
+		np = priv->of_node;
+	else
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+		np = priv->phy->mdio.dev.of_node;
+#else
+		np = priv->phy->dev.of_node;
+#endif
+
+	if(!np)
+		return -EINVAL;
+
+	/*Before switch software reset, disable PHY and clear  MAC PAD*/
+	qca_ar8327_phy_linkdown(priv->device_id);
+	qca_mac_disable(priv->device_id);
+	msleep(1000);
+
+	/*First software reset S17 chip*/
+	qca_ar8327_sw_soft_reset(priv);
+
+	/*After switch software reset, need disable all ports' MAC with 1000M FULL*/
+	qca_switch_set_mac_force(priv);
+
+	/* Configure switch register from DT information */
+	paddr = of_get_property(np, "qca,ar8327-initvals", &len);
+	if (paddr) {
+		if (len < (2 * sizeof(*paddr))) {
+			SSDK_ERROR("len:%d < 2 * sizeof(*paddr):%zu\n", len, 2 * sizeof(*paddr));
+			return -EINVAL;
+		}
+
+		len /= sizeof(*paddr);
+
+		for (i = 0; i < len - 1; i += 2) {
+			reg = be32_to_cpup(paddr + i);
+			value = be32_to_cpup(paddr + i + 1);
+			priv->mii_write(priv->device_id, reg, value);
+		}
+	}
+
+	value = priv->mii_read(priv->device_id, AR8327_REG_MODULE_EN);
+	value &= ~AR8327_REG_MODULE_EN_QM_ERR;
+	value &= ~AR8327_REG_MODULE_EN_LOOKUP_ERR;
+	priv->mii_write(priv->device_id, AR8327_REG_MODULE_EN, value);
+
+	qca_switch_init(priv->device_id);
+#ifdef IN_PORTVLAN
+	ssdk_portvlan_init(priv->device_id);
+#endif
+	qca_mac_enable_intr(priv);
+	qca_ar8327_phy_enable(priv);
+
+	return 0;
+}
+#else
+static a_uint32_t
+qca_ar8327_get_pad_cfg(struct ar8327_pad_cfg *pad_cfg)
+{
+	a_uint32_t value = 0;
+
+	if (pad_cfg == 0) {
+		return 0;
+    }
+
+    if(pad_cfg->mode == AR8327_PAD_MAC2MAC_MII) {
+		value = AR8327_PAD_CTRL_MAC_MII_EN;
+		if (pad_cfg->rxclk_sel)
+			value |= AR8327_PAD_CTRL_MAC_MII_RXCLK_SEL;
+		if (pad_cfg->txclk_sel)
+			value |= AR8327_PAD_CTRL_MAC_MII_TXCLK_SEL;
+
+    } else if (pad_cfg->mode == AR8327_PAD_MAC2MAC_GMII) {
+		value = AR8327_PAD_CTRL_MAC_GMII_EN;
+		if (pad_cfg->rxclk_sel)
+			value |= AR8327_PAD_CTRL_MAC_GMII_RXCLK_SEL;
+		if (pad_cfg->txclk_sel)
+			value |= AR8327_PAD_CTRL_MAC_GMII_TXCLK_SEL;
+
+    } else if (pad_cfg->mode == AR8327_PAD_MAC_SGMII) {
+		value = AR8327_PAD_CTRL_SGMII_EN;
+
+		/* WAR for AP136 board. */
+		value |= pad_cfg->txclk_delay_sel <<
+		        AR8327_PAD_CTRL_RGMII_TXCLK_DELAY_SEL_S;
+		value |= pad_cfg->rxclk_delay_sel <<
+                AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_SEL_S;
+		if (pad_cfg->rxclk_delay_en)
+			value |= AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_EN;
+		if (pad_cfg->txclk_delay_en)
+			value |= AR8327_PAD_CTRL_RGMII_TXCLK_DELAY_EN;
+
+    } else if (pad_cfg->mode == AR8327_PAD_MAC2PHY_MII) {
+		value = AR8327_PAD_CTRL_PHY_MII_EN;
+		if (pad_cfg->rxclk_sel)
+			value |= AR8327_PAD_CTRL_PHY_MII_RXCLK_SEL;
+		if (pad_cfg->txclk_sel)
+			value |= AR8327_PAD_CTRL_PHY_MII_TXCLK_SEL;
+
+    } else if (pad_cfg->mode == AR8327_PAD_MAC2PHY_GMII) {
+		value = AR8327_PAD_CTRL_PHY_GMII_EN;
+		if (pad_cfg->pipe_rxclk_sel)
+			value |= AR8327_PAD_CTRL_PHY_GMII_PIPE_RXCLK_SEL;
+		if (pad_cfg->rxclk_sel)
+			value |= AR8327_PAD_CTRL_PHY_GMII_RXCLK_SEL;
+		if (pad_cfg->txclk_sel)
+			value |= AR8327_PAD_CTRL_PHY_GMII_TXCLK_SEL;
+
+    } else if (pad_cfg->mode == AR8327_PAD_MAC_RGMII) {
+		value = AR8327_PAD_CTRL_RGMII_EN;
+		value |= pad_cfg->txclk_delay_sel <<
+                 AR8327_PAD_CTRL_RGMII_TXCLK_DELAY_SEL_S;
+		value |= pad_cfg->rxclk_delay_sel <<
+                 AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_SEL_S;
+		if (pad_cfg->rxclk_delay_en)
+			value |= AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_EN;
+		if (pad_cfg->txclk_delay_en)
+			value |= AR8327_PAD_CTRL_RGMII_TXCLK_DELAY_EN;
+
+    } else if (pad_cfg->mode == AR8327_PAD_PHY_GMII) {
+		value = AR8327_PAD_CTRL_PHYX_GMII_EN;
+
+    } else if (pad_cfg->mode == AR8327_PAD_PHY_RGMII) {
+		value = AR8327_PAD_CTRL_PHYX_RGMII_EN;
+
+    } else if (pad_cfg->mode == AR8327_PAD_PHY_MII) {
+		value = AR8327_PAD_CTRL_PHYX_MII_EN;
+
+	} else {
+        value = 0;
+    }
+
+	return value;
+}
+
+#ifndef BOARD_AR71XX
+static a_uint32_t
+qca_ar8327_get_pwr_sel(struct qca_phy_priv *priv,
+                                struct ar8327_platform_data *plat_data)
+{
+	struct ar8327_pad_cfg *cfg = NULL;
+	a_uint32_t value;
+
+	if (!plat_data) {
+		return 0;
+	}
+
+	value = priv->mii_read(priv->device_id, AR8327_REG_PAD_MAC_PWR_SEL);
+
+	cfg = plat_data->pad0_cfg;
+
+	if (cfg && (cfg->mode == AR8327_PAD_MAC_RGMII) &&
+                cfg->rgmii_1_8v) {
+		value |= AR8327_PAD_MAC_PWR_RGMII0_1_8V;
+	}
+
+	cfg = plat_data->pad5_cfg;
+	if (cfg && (cfg->mode == AR8327_PAD_MAC_RGMII) &&
+                cfg->rgmii_1_8v) {
+		value |= AR8327_PAD_MAC_PWR_RGMII1_1_8V;
+	}
+
+	cfg = plat_data->pad6_cfg;
+	if (cfg && (cfg->mode == AR8327_PAD_MAC_RGMII) &&
+               cfg->rgmii_1_8v) {
+		value |= AR8327_PAD_MAC_PWR_RGMII1_1_8V;
+	}
+
+	return value;
+}
+#endif
+
+static a_uint32_t
+qca_ar8327_set_led_cfg(struct qca_phy_priv *priv,
+                              struct ar8327_platform_data *plat_data,
+                              a_uint32_t pos)
+{
+	struct ar8327_led_cfg *led_cfg;
+	a_uint32_t new_pos = pos;
+
+	led_cfg = plat_data->led_cfg;
+	if (led_cfg) {
+		if (led_cfg->open_drain)
+			new_pos |= AR8327_POS_LED_OPEN_EN;
+		else
+			new_pos &= ~AR8327_POS_LED_OPEN_EN;
+
+		priv->mii_write(priv->device_id, AR8327_REG_LED_CTRL_0, led_cfg->led_ctrl0);
+		priv->mii_write(priv->device_id, AR8327_REG_LED_CTRL_1, led_cfg->led_ctrl1);
+		priv->mii_write(priv->device_id, AR8327_REG_LED_CTRL_2, led_cfg->led_ctrl2);
+		priv->mii_write(priv->device_id, AR8327_REG_LED_CTRL_3, led_cfg->led_ctrl3);
+
+		if (new_pos != pos) {
+			new_pos |= AR8327_POS_POWER_ON_SEL;
+		}
+	}
+	return new_pos;
+}
+#ifndef BOARD_AR71XX
+static int
+qca_ar8327_set_sgmii_cfg(struct qca_phy_priv *priv,
+                              struct ar8327_platform_data *plat_data,
+                              a_uint32_t* new_pos)
+{
+	a_uint32_t value = 0;
+
+	/*configure the SGMII*/
+	value = priv->mii_read(priv->device_id, AR8327_REG_PAD_SGMII_CTRL);
+	value &= ~(AR8327_PAD_SGMII_CTRL_MODE_CTRL);
+	value |= ((plat_data->sgmii_cfg->sgmii_mode) <<
+          AR8327_PAD_SGMII_CTRL_MODE_CTRL_S);
+
+	if (priv->version == QCA_VER_AR8337) {
+		value |= (AR8327_PAD_SGMII_CTRL_EN_PLL |
+		     AR8327_PAD_SGMII_CTRL_EN_RX |
+		     AR8327_PAD_SGMII_CTRL_EN_TX);
+	} else {
+		value &= ~(AR8327_PAD_SGMII_CTRL_EN_PLL |
+		       AR8327_PAD_SGMII_CTRL_EN_RX |
+		       AR8327_PAD_SGMII_CTRL_EN_TX);
+	}
+	value |= AR8327_PAD_SGMII_CTRL_EN_SD;
+
+	priv->mii_write(priv->device_id, AR8327_REG_PAD_SGMII_CTRL, value);
+
+	if (plat_data->sgmii_cfg->serdes_aen) {
+		*new_pos &= ~AR8327_POS_SERDES_AEN;
+	} else {
+		*new_pos |= AR8327_POS_SERDES_AEN;
+	}
+	return 0;
+}
+#endif
+
+static int
+qca_ar8327_set_plat_data_cfg(struct qca_phy_priv *priv,
+                              struct ar8327_platform_data *plat_data)
+{
+	a_uint32_t pos, new_pos;
+
+	pos = priv->mii_read(priv->device_id, AR8327_REG_POS);
+
+	new_pos = qca_ar8327_set_led_cfg(priv, plat_data, pos);
+
+#ifndef BOARD_AR71XX
+	/*configure the SGMII*/
+	if (plat_data->sgmii_cfg) {
+		qca_ar8327_set_sgmii_cfg(priv, plat_data, &new_pos);
+	}
+#endif
+
+	priv->mii_write(priv->device_id, AR8327_REG_POS, new_pos);
+
+	return 0;
+}
+
+static int
+qca_ar8327_set_pad_cfg(struct qca_phy_priv *priv,
+                              struct ar8327_platform_data *plat_data)
+{
+	a_uint32_t pad0 = 0, pad5 = 0, pad6 = 0;
+
+	pad0 = qca_ar8327_get_pad_cfg(plat_data->pad0_cfg);
+	priv->mii_write(priv->device_id, AR8327_REG_PAD0_CTRL, pad0);
+
+	pad5 = qca_ar8327_get_pad_cfg(plat_data->pad5_cfg);
+	if(priv->version == QCA_VER_AR8337) {
+	        pad5 |= AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_EN;
+	}
+	priv->mii_write(priv->device_id, AR8327_REG_PAD5_CTRL, pad5);
+
+	pad6 = qca_ar8327_get_pad_cfg(plat_data->pad6_cfg);
+	if(plat_data->pad5_cfg &&
+		(plat_data->pad5_cfg->mode == AR8327_PAD_PHY_RGMII))
+		pad6 |= AR8327_PAD_CTRL_PHYX_RGMII_EN;
+	priv->mii_write(priv->device_id, AR8327_REG_PAD6_CTRL, pad6);
+
+	return 0;
+}
+
+void
+qca_ar8327_port_init(struct qca_phy_priv *priv, a_uint32_t port)
+{
+	struct ar8327_platform_data *plat_data;
+	struct ar8327_port_cfg *port_cfg;
+	a_uint32_t value;
+
+	plat_data = priv->phy->dev.platform_data;
+	if (plat_data == NULL) {
+		return;
+	}
+
+	if (((port == 0) && plat_data->pad0_cfg) ||
+	    ((port == 5) && plat_data->pad5_cfg) ||
+	    ((port == 6) && plat_data->pad6_cfg)) {
+	        switch (port) {
+		        case 0:
+		            port_cfg = &plat_data->cpuport_cfg;
+		            break;
+		        case 5:
+		            port_cfg = &plat_data->port5_cfg;
+		            break;
+		        case 6:
+		            port_cfg = &plat_data->port6_cfg;
+		            break;
+	        }
+	} else {
+	        return;
+	}
+
+	/*disable mac at first*/
+	fal_port_rxmac_status_set(priv->device_id, port, A_FALSE);
+	fal_port_txmac_status_set(priv->device_id, port, A_FALSE);
+	value = port_cfg->duplex ? FAL_FULL_DUPLEX : FAL_HALF_DUPLEX;
+	fal_port_duplex_set(priv->device_id, port, value);
+	value = port_cfg->txpause ? A_TRUE : A_FALSE;
+	fal_port_txfc_status_set(priv->device_id, port, value);
+	value = port_cfg->rxpause ? A_TRUE : A_FALSE;
+	fal_port_rxfc_status_set(priv->device_id, port, value);
+	if(port_cfg->speed == AR8327_PORT_SPEED_10) {
+		value = FAL_SPEED_10;
+	} else if(port_cfg->speed == AR8327_PORT_SPEED_100) {
+		value = FAL_SPEED_100;
+	} else if(port_cfg->speed == AR8327_PORT_SPEED_1000) {
+		value = FAL_SPEED_1000;
+	} else {
+		value = FAL_SPEED_1000;
+	}
+	fal_port_speed_set(priv->device_id, port, value);
+	/*enable mac at last*/
+	udelay(800);
+	fal_port_rxmac_status_set(priv->device_id, port, A_TRUE);
+	fal_port_txmac_status_set(priv->device_id, port, A_TRUE);
+}
+
+int
+qca_ar8327_hw_init(struct qca_phy_priv *priv)
+{
+	struct ar8327_platform_data *plat_data;
+	a_uint32_t i = 0;
+	a_uint32_t value = 0;
+
+	plat_data = priv->phy->dev.platform_data;
+	if (plat_data == NULL) {
+		return -EINVAL;
+	}
+
+	/*Before switch software reset, disable PHY and clear MAC PAD*/
+	qca_ar8327_phy_linkdown(priv->device_id);
+	qca_mac_disable(priv->device_id);
+	udelay(10);
+
+	qca_ar8327_set_plat_data_cfg(priv, plat_data);
+
+	/*mac reset*/
+	priv->mii_write(priv->device_id, AR8327_REG_MAC_SFT_RST, 0x3fff);
+
+	msleep(100);
+
+	/*First software reset S17 chip*/
+	qca_ar8327_sw_soft_reset(priv);
+	udelay(1000);
+
+	/*After switch software reset, need disable all ports' MAC with 1000M FULL*/
+	qca_switch_set_mac_force(priv);
+
+	qca_ar8327_set_pad_cfg(priv, plat_data);
+
+	value = priv->mii_read(priv->device_id, AR8327_REG_MODULE_EN);
+	value &= ~AR8327_REG_MODULE_EN_QM_ERR;
+	value &= ~AR8327_REG_MODULE_EN_LOOKUP_ERR;
+	priv->mii_write(priv->device_id, AR8327_REG_MODULE_EN, value);
+
+	qca_switch_init(priv->device_id);
+
+#ifndef BOARD_AR71XX
+	value = qca_ar8327_get_pwr_sel(priv, plat_data);
+	priv->mii_write(priv->device_id, AR8327_REG_PAD_MAC_PWR_SEL, value);
+#endif
+
+	msleep(1000);
+
+	for (i = 0; i < AR8327_NUM_PORTS; i++) {
+		qca_ar8327_port_init(priv, i);
+	}
+
+	qca_ar8327_phy_enable(priv);
+
+	return 0;
+}
+#endif
+
+#if defined(IN_SWCONFIG)
+#ifndef BOARD_AR71XX
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+static int
+qca_ar8327_sw_get_reg_val(struct switch_dev *dev,
+                                    int reg, int *val)
+{
+	return 0;
+}
+
+static int
+qca_ar8327_sw_set_reg_val(struct switch_dev *dev,
+                                    int reg, int val)
+{
+	return 0;
+}
+#endif
+#endif
+static struct switch_attr qca_ar8327_globals[] = {
+#if defined(IN_VLAN)
+	{
+		.name = "enable_vlan",
+		.description = "Enable 8021q VLAN",
+		.type = SWITCH_TYPE_INT,
+		.set = qca_ar8327_sw_set_vlan,
+		.get = qca_ar8327_sw_get_vlan,
+		.max = 1
+	},
+#endif
+#if defined(IN_MISC)
+	{
+		.name = "max_frame_size",
+		.description = "Set Max frame Size Of Mac",
+		.type = SWITCH_TYPE_INT,
+		.set = qca_ar8327_sw_set_max_frame_size,
+		.get = qca_ar8327_sw_get_max_frame_size,
+		.max = 9018
+	},
+#endif
+#if defined(IN_MIB)
+	{
+		.name = "reset_mibs",
+		.description = "Reset All MIB Counters",
+		.type = SWITCH_TYPE_NOVAL,
+		.set = qca_ar8327_sw_set_reset_mibs,
+	},
+#endif
+#ifdef IN_FDB
+	{
+		.name = "flush_arl",
+		.description = "Flush All ARL table",
+		.type = SWITCH_TYPE_NOVAL,
+		.set = qca_ar8327_sw_atu_flush,
+	},
+	{
+		.name = "dump_arl",
+		.description = "Dump All ARL table",
+		.type = SWITCH_TYPE_STRING,
+		.get = qca_ar8327_sw_atu_dump,
+	},
+#endif
+	{
+		.name = "switch_ext",
+		.description = "Switch extended configuration",
+		.type = SWITCH_TYPE_EXT,
+		.set = qca_ar8327_sw_switch_ext,
+	},
+};
+
+static struct switch_attr qca_ar8327_port[] = {
+#if defined(IN_MIB)
+	{
+		.name = "reset_mib",
+		.description = "Reset Mib Counters",
+		.type = SWITCH_TYPE_NOVAL,
+		.set = qca_ar8327_sw_set_port_reset_mib,
+	},
+	{
+		.name = "mib",
+		.description = "Get Mib Counters",
+		.type = SWITCH_TYPE_STRING,
+		.set = NULL,
+		.get = qca_ar8327_sw_get_port_mib,
+	},
+#endif
+#if defined(IN_PORTCONTROL)
+	{
+		.type = SWITCH_TYPE_INT,
+		.name = "enable_eee",
+		.description = "Enable EEE",
+		.set = qca_ar8327_sw_set_eee,
+		.get = qca_ar8327_sw_get_eee,
+		.max = 1,
+	},
+#endif
+};
+
+#if defined(IN_VLAN)
+static struct switch_attr qca_ar8327_vlan[] = {
+	{
+		.name = "vid",
+		.description = "Configure Vlan Id",
+		.type = SWITCH_TYPE_INT,
+		.set = qca_ar8327_sw_set_vid,
+		.get = qca_ar8327_sw_get_vid,
+		.max = 4094,
+	},
+};
+#endif
+
+const struct switch_dev_ops qca_ar8327_sw_ops = {
+	.attr_global = {
+		.attr = qca_ar8327_globals,
+		.n_attr = ARRAY_SIZE(qca_ar8327_globals),
+	},
+	.attr_port = {
+		.attr = qca_ar8327_port,
+		.n_attr = ARRAY_SIZE(qca_ar8327_port),
+	},
+#if defined(IN_VLAN)
+	.attr_vlan = {
+		.attr = qca_ar8327_vlan,
+		.n_attr = ARRAY_SIZE(qca_ar8327_vlan),
+	},
+	.get_port_pvid = qca_ar8327_sw_get_pvid,
+	.set_port_pvid = qca_ar8327_sw_set_pvid,
+	.get_vlan_ports = qca_ar8327_sw_get_ports,
+	.set_vlan_ports = qca_ar8327_sw_set_ports,
+	.apply_config = qca_ar8327_sw_hw_apply,
+#endif
+#if defined(IN_MISC)
+	.reset_switch = qca_ar8327_sw_reset_switch,
+#endif
+#if defined(IN_PORTCONTROL)
+	.get_port_link = qca_ar8327_sw_get_port_link,
+#endif
+#ifndef BOARD_AR71XX
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+	.get_reg_val = qca_ar8327_sw_get_reg_val,
+	.set_reg_val = qca_ar8327_sw_set_reg_val,
+#endif
+#endif
+};
+#endif
+
+#define SSDK_MIB_CHANGE_WQ
+
+static int
+qca_phy_mib_task(struct qca_phy_priv *priv)
+{
+	qca_ar8327_sw_mib_task(priv);
+	return 0;
+}
+
+static void
+qca_phy_mib_work_task(struct work_struct *work)
+{
+	struct qca_phy_priv *priv = container_of(work, struct qca_phy_priv,
+                                            mib_dwork.work);
+
+	mutex_lock(&priv->mib_lock);
+
+    qca_phy_mib_task(priv);
+
+	mutex_unlock(&priv->mib_lock);
+#ifndef SSDK_MIB_CHANGE_WQ
+	schedule_delayed_work(&priv->mib_dwork,
+			      msecs_to_jiffies(QCA_PHY_MIB_WORK_DELAY));
+#else
+	queue_delayed_work_on(0, system_long_wq, &priv->mib_dwork,
+					msecs_to_jiffies(QCA_PHY_MIB_WORK_DELAY));
+#endif
+}
+
+int
+qca_phy_mib_work_start(struct qca_phy_priv *priv)
+{
+	mutex_init(&priv->mib_lock);
+	if(SW_OK != fal_mib_counter_alloc(priv->device_id, &priv->mib_counters)){
+		SSDK_ERROR("Memory allocation fail\n");
+		return -ENOMEM;
+	}
+
+	INIT_DELAYED_WORK(&priv->mib_dwork, qca_phy_mib_work_task);
+#ifndef SSDK_MIB_CHANGE_WQ
+	schedule_delayed_work(&priv->mib_dwork,
+			               msecs_to_jiffies(QCA_PHY_MIB_WORK_DELAY));
+#else
+	queue_delayed_work_on(0, system_long_wq, &priv->mib_dwork,
+					msecs_to_jiffies(QCA_PHY_MIB_WORK_DELAY));
+#endif
+
+	return 0;
+}
+
+void
+qca_phy_mib_work_stop(struct qca_phy_priv *priv)
+{
+	if(!priv)
+		return;
+	if(priv->mib_counters)
+		kfree(priv->mib_counters);
+	cancel_delayed_work_sync(&priv->mib_dwork);
+}
+
+#define SSDK_QM_CHANGE_WQ
+
+static void
+qm_err_check_work_task_polling(struct work_struct *work)
+{
+	struct qca_phy_priv *priv = container_of(work, struct qca_phy_priv,
+                                            qm_dwork_polling.work);
+
+	mutex_lock(&priv->qm_lock);
+
+	qca_ar8327_sw_mac_polling_task(priv);
+
+	mutex_unlock(&priv->qm_lock);
+
+#ifndef SSDK_QM_CHANGE_WQ
+	schedule_delayed_work(&priv->qm_dwork,
+							msecs_to_jiffies(QCA_QM_WORK_DELAY));
+#else
+	queue_delayed_work_on(0, system_long_wq, &priv->qm_dwork_polling,
+							msecs_to_jiffies(QCA_QM_WORK_DELAY));
+#endif
+}
+
+static int config_gpio(a_uint32_t  gpio_num)
+{
+	int  error;
+
+	if (gpio_is_valid(gpio_num))
+	{
+		error = gpio_request_one(gpio_num, GPIOF_IN, "linkchange");
+		if (error < 0) {
+			SSDK_ERROR("gpio request faild \n");
+			return -1;
+		}
+		gpio_set_debounce(gpio_num, 60000);
+	}
+	else
+	{
+		SSDK_ERROR("gpio is invalid\n");
+		return -1;
+	}
+
+	return 0;
+}
+static int qca_link_polling_select(struct qca_phy_priv *priv)
+{
+	struct device_node *np = NULL;
+	const __be32 *link_polling_required, *link_intr_gpio;
+	a_int32_t len;
+
+	if (priv->ess_switch_flag == A_TRUE)
+		np = priv->of_node;
+	else if(priv->version == QCA_VER_AR8337 || priv->version == QCA_VER_AR8327)
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+		np = priv->phy->mdio.dev.of_node;
+#else
+		np = priv->phy->dev.of_node;
+#endif
+	else
+		SSDK_ERROR("cannot find np node!\n");
+
+	if(!np)
+	{
+		SSDK_ERROR("np is null !\n");
+		return -1;
+	}
+
+	link_polling_required = of_get_property(np, "link-polling-required", &len);
+	if (!link_polling_required )
+	{
+		SSDK_INFO("link-polling-required node does not exist\n");
+		return -1;
+	}
+	priv->link_polling_required  = be32_to_cpup(link_polling_required);
+	if(!priv->link_polling_required)
+	{
+		link_intr_gpio = of_get_property(np, "link-intr-gpio", &len);
+		if (!link_intr_gpio )
+		{
+			SSDK_ERROR("cannot find link-intr-gpio node\n");
+			return -1;
+		}
+		if(config_gpio(be32_to_cpup(link_intr_gpio)))
+			return -1;
+		priv->link_interrupt_no = gpio_to_irq (be32_to_cpup(link_intr_gpio));
+		SSDK_INFO("the interrupt number is:%x\n",priv->link_interrupt_no);
+	}
+
+	return 0;
+}
+
+int
+qm_err_check_work_start(struct qca_phy_priv *priv)
+{
+	/*Only valid for S17c chip*/
+	if (priv->version != QCA_VER_AR8337 &&
+		priv->version != QCA_VER_AR8327 &&
+		priv->version != QCA_VER_DESS)
+	{
+		return 0;
+	}
+
+	mutex_init(&priv->qm_lock);
+	INIT_DELAYED_WORK(&priv->qm_dwork_polling, qm_err_check_work_task_polling);
+#ifndef SSDK_MIB_CHANGE_WQ
+	schedule_delayed_work(&priv->qm_dwork_polling,
+							msecs_to_jiffies(QCA_QM_WORK_DELAY));
+#else
+	queue_delayed_work_on(0, system_long_wq, &priv->qm_dwork_polling,
+							msecs_to_jiffies(QCA_QM_WORK_DELAY));
+#endif
+
+	return 0;
+}
+
+void
+qm_err_check_work_stop(struct qca_phy_priv *priv)
+{
+	/*Only valid for S17c chip*/
+	if (priv->version != QCA_VER_AR8337 &&
+		priv->version != QCA_VER_AR8327 &&
+		priv->version != QCA_VER_DESS) return;
+
+		cancel_delayed_work_sync(&priv->qm_dwork_polling);
+
+}
+#ifdef DESS
+static void
+dess_rgmii_mac_work_task(struct work_struct *work)
+{
+	struct qca_phy_priv *priv = container_of(work, struct qca_phy_priv,
+                                            rgmii_dwork.work);
+
+	mutex_lock(&priv->rgmii_lock);
+
+	dess_rgmii_sw_mac_polling_task(priv);
+
+	mutex_unlock(&priv->rgmii_lock);
+
+	schedule_delayed_work(&priv->rgmii_dwork, msecs_to_jiffies(QCA_RGMII_WORK_DELAY));
+}
+
+int
+dess_rgmii_mac_work_start(struct qca_phy_priv *priv)
+{
+	mutex_init(&priv->rgmii_lock);
+
+	INIT_DELAYED_WORK(&priv->rgmii_dwork, dess_rgmii_mac_work_task);
+
+	schedule_delayed_work(&priv->rgmii_dwork, msecs_to_jiffies(QCA_RGMII_WORK_DELAY));
+
+	return 0;
+}
+
+void
+dess_rgmii_mac_work_stop(struct qca_phy_priv *priv)
+{
+	cancel_delayed_work_sync(&priv->rgmii_dwork);
+}
+#endif
+
+void
+qca_mac_port_status_init(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	if(port_id < SSDK_PHYSICAL_PORT1 || port_id >= SW_MAX_NR_PORT)
+	{
+		SSDK_ERROR("port %d does not support status init\n", port_id);
+		return;
+	}
+	qca_phy_priv_global[dev_id]->port_old_link[port_id - 1] = 0;
+	qca_phy_priv_global[dev_id]->port_old_speed[port_id - 1] = FAL_SPEED_BUTT;
+	qca_phy_priv_global[dev_id]->port_old_duplex[port_id - 1] = FAL_DUPLEX_BUTT;
+	qca_phy_priv_global[dev_id]->port_old_tx_flowctrl[port_id - 1] = A_FALSE;
+	qca_phy_priv_global[dev_id]->port_old_rx_flowctrl[port_id - 1] = A_FALSE;
+	qca_phy_priv_global[dev_id]->port_tx_flowctrl_forcemode[port_id - 1] = A_FALSE;
+	qca_phy_priv_global[dev_id]->port_rx_flowctrl_forcemode[port_id - 1] = A_FALSE;
+}
+
+void
+qca_mac_sw_sync_port_status_init(a_uint32_t dev_id)
+{
+	a_uint32_t port_id;
+
+	for (port_id = SSDK_PHYSICAL_PORT1; port_id < SW_MAX_NR_PORT; port_id ++) {
+		qca_mac_port_status_init(dev_id, port_id);
+	}
+}
+void
+qca_mac_sw_sync_work_task(struct work_struct *work)
+{
+	adpt_api_t *p_adpt_api;
+
+	struct qca_phy_priv *priv = container_of(work, struct qca_phy_priv,
+					mac_sw_sync_dwork.work);
+
+	mutex_lock(&priv->mac_sw_sync_lock);
+
+	 if((p_adpt_api = adpt_api_ptr_get(priv->device_id)) != NULL) {
+		if (NULL == p_adpt_api->adpt_port_polling_sw_sync_set)
+			return;
+		p_adpt_api->adpt_port_polling_sw_sync_set(priv);
+	}
+
+	mutex_unlock(&priv->mac_sw_sync_lock);
+
+	schedule_delayed_work(&priv->mac_sw_sync_dwork,
+					msecs_to_jiffies(QCA_MAC_SW_SYNC_WORK_DELAY));
+}
+
+int
+qca_mac_sw_sync_work_start(struct qca_phy_priv *priv)
+{
+	if ((priv->version != QCA_VER_HPPE) && (priv->version != QCA_VER_SCOMPHY))
+		return 0;
+
+	if (priv->version == QCA_VER_HPPE) {
+		qca_mac_sw_sync_port_status_init(priv->device_id);
+	}
+
+	mutex_init(&priv->mac_sw_sync_lock);
+
+	INIT_DELAYED_WORK(&priv->mac_sw_sync_dwork,
+					qca_mac_sw_sync_work_task);
+	schedule_delayed_work(&priv->mac_sw_sync_dwork,
+					msecs_to_jiffies(QCA_MAC_SW_SYNC_WORK_DELAY));
+
+	return 0;
+}
+
+void
+qca_mac_sw_sync_work_stop(struct qca_phy_priv *priv)
+{
+	if ((priv->version != QCA_VER_HPPE) && (priv->version != QCA_VER_SCOMPHY)) {
+		return;
+	}
+	cancel_delayed_work_sync(&priv->mac_sw_sync_dwork);
+}
+
+void
+qca_mac_sw_sync_work_resume(struct qca_phy_priv *priv)
+{
+	if ((priv->version != QCA_VER_HPPE) && (priv->version != QCA_VER_SCOMPHY)) {
+		return;
+	}
+
+	schedule_delayed_work(&priv->mac_sw_sync_dwork,
+					msecs_to_jiffies(QCA_MAC_SW_SYNC_WORK_DELAY));
+}
+
+int
+qca_phy_id_chip(struct qca_phy_priv *priv)
+{
+	a_uint32_t value, version;
+
+	value = qca_ar8216_mii_read(priv->device_id, AR8327_REG_CTRL);
+	version = value & (AR8327_CTRL_REVISION |
+                AR8327_CTRL_VERSION);
+	priv->version = (version & AR8327_CTRL_VERSION) >>
+                           AR8327_CTRL_VERSION_S;
+	priv->revision = (version & AR8327_CTRL_REVISION);
+
+    if((priv->version == QCA_VER_AR8327) ||
+       (priv->version == QCA_VER_AR8337) ||
+       (priv->version == QCA_VER_AR8227)) {
+		return 0;
+
+    } else {
+		SSDK_ERROR("unsupported QCA device\n");
+		return -ENODEV;
+	}
+}
+
+#if defined(IN_SWCONFIG)
+static int qca_switchdev_register(struct qca_phy_priv *priv)
+{
+	struct switch_dev *sw_dev;
+	int ret = SW_OK;
+	sw_dev = &priv->sw_dev;
+
+	switch (priv->version) {
+		case QCA_VER_AR8227:
+			sw_dev->name = "QCA AR8227";
+			sw_dev->alias = "QCA AR8227";
+			break;
+		case QCA_VER_AR8327:
+			sw_dev->name = "QCA AR8327";
+			sw_dev->alias = "QCA AR8327";
+			break;
+		case QCA_VER_AR8337:
+			sw_dev->name = "QCA AR8337";
+			sw_dev->alias = "QCA AR8337";
+			break;
+		case QCA_VER_DESS:
+			sw_dev->name = "QCA DESS";
+			sw_dev->alias = "QCA DESS";
+			break;
+		case QCA_VER_HPPE:
+			sw_dev->name = "QCA HPPE";
+			sw_dev->alias = "QCA HPPE";
+			break;
+		case QCA_VER_SCOMPHY:
+#ifdef MP
+			if(adapt_scomphy_revision_get(priv->device_id)
+				== MP_GEPHY)
+			{
+				sw_dev->name = "QCA MP";
+				sw_dev->alias = "QCA MP";
+			}
+#endif
+			break;
+		default:
+			sw_dev->name = "unknown switch";
+			sw_dev->alias = "unknown switch";
+			break;
+	}
+
+	sw_dev->ops = &qca_ar8327_sw_ops;
+	sw_dev->vlans = AR8327_MAX_VLANS;
+	sw_dev->ports = priv->ports;
+
+	ret = register_switch(sw_dev, NULL);
+	if (ret != SW_OK) {
+		SSDK_ERROR("register_switch failed for %s\n", sw_dev->name);
+		return ret;
+	}
+
+	return ret;
+}
+#endif
+
+static int
+qca_phy_config_init(struct phy_device *pdev)
+{
+	struct qca_phy_priv *priv = pdev->priv;
+	int ret = 0;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+	if (pdev->mdio.addr != 0) {
+#else
+	if (pdev->addr != 0) {
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+	pdev->supported |= SUPPORTED_1000baseT_Full;
+	pdev->advertising |= ADVERTISED_1000baseT_Full;
+#else
+	linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+			pdev->supported);
+	linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+			pdev->advertising);
+#endif
+
+#ifndef BOARD_AR71XX
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+		ssdk_phy_rgmii_set(priv);
+#endif
+#endif
+		return 0;
+	}
+
+	if (priv == NULL)
+		return -ENOMEM;
+
+	priv->phy = pdev;
+	ret = qca_phy_id_chip(priv);
+	if (ret != 0) {
+		return ret;
+	}
+
+	priv->mii_read = qca_ar8216_mii_read;
+	priv->mii_write = qca_ar8216_mii_write;
+	priv->phy_write = qca_ar8327_phy_write;
+	priv->phy_read = qca_ar8327_phy_read;
+	priv->phy_dbg_write = qca_ar8327_phy_dbg_write;
+	priv->phy_dbg_read = qca_ar8327_phy_dbg_read;
+	priv->phy_mmd_write = qca_ar8327_mmd_write;
+	priv->ports = AR8327_NUM_PORTS;
+
+	ret = qca_link_polling_select(priv);
+	if(ret)
+		priv->link_polling_required = 1;
+	pdev->priv = priv;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+	pdev->supported |= SUPPORTED_1000baseT_Full;
+	pdev->advertising |= ADVERTISED_1000baseT_Full;
+#else
+	linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+			pdev->supported);
+	linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+			pdev->advertising);
+#endif
+
+#if defined(IN_SWCONFIG)
+	ret = qca_switchdev_register(priv);
+	if (ret != SW_OK) {
+		return ret;
+	}
+#endif
+	priv->qca_ssdk_sw_dev_registered = A_TRUE;
+
+	snprintf(priv->link_intr_name, IFNAMSIZ, "switch0");
+
+	ret = qca_ar8327_hw_init(priv);
+	if (ret != 0) {
+		return ret;
+	}
+
+	qca_phy_mib_work_start(priv);
+
+	if(priv->link_polling_required)
+	{
+		SSDK_INFO("polling is selected\n");
+		ret = qm_err_check_work_start(priv);
+		if (ret != 0)
+		{
+			SSDK_ERROR("qm_err_check_work_start failed for chip 0x%02x%02x\n", priv->version, priv->revision);
+			return ret;
+		}
+	}
+	else
+	{
+		SSDK_INFO("interrupt is selected\n");
+		priv->interrupt_flag = IRQF_TRIGGER_LOW;
+		ret = qca_intr_init(priv);
+		if(ret)
+			SSDK_ERROR("the interrupt init faild !\n");
+	}
+
+	return ret;
+}
+
+#if defined(DESS) || defined(HPPE) || defined (ISISC) || defined (ISIS) || defined(MP)
+static int ssdk_switch_register(a_uint32_t dev_id, ssdk_chip_type  chip_type)
+{
+	struct qca_phy_priv *priv;
+	int ret = 0;
+	a_uint32_t chip_id = 0;
+	priv = qca_phy_priv_global[dev_id];
+
+	priv->mii_read = qca_ar8216_mii_read;
+	priv->mii_write = qca_ar8216_mii_write;
+	priv->phy_write = qca_ar8327_phy_write;
+	priv->phy_read = qca_ar8327_phy_read;
+	priv->phy_dbg_write = qca_ar8327_phy_dbg_write;
+	priv->phy_dbg_read = qca_ar8327_phy_dbg_read;
+	priv->phy_mmd_write = qca_ar8327_mmd_write;
+
+	if (chip_type == CHIP_DESS) {
+		priv->ports = 6;
+	} else if ((chip_type == CHIP_ISIS) || (chip_type == CHIP_ISISC)) {
+		priv->ports = 7;
+	} else if (chip_type == CHIP_SCOMPHY) {
+#ifdef MP
+		if(adapt_scomphy_revision_get(priv->device_id) == MP_GEPHY) {
+			/*for ipq50xx, port id is 1 and 2, port 0 is not available*/
+			priv->ports = 3;
+		}
+#endif
+	} else {
+		priv->ports = SSDK_MAX_PORT_NUM;
+	}
+
+#ifdef MP
+	if(chip_type == CHIP_SCOMPHY)
+	{
+		priv->version = QCA_VER_SCOMPHY;
+		SSDK_INFO("Chip version 0x%02x\n", priv->version);
+	}
+	else
+#endif
+	{
+		if (fal_reg_get(dev_id, 0, (a_uint8_t *)&chip_id, 4) == SW_OK) {
+			priv->version = ((chip_id >> 8) & 0xff);
+			priv->revision = (chip_id & 0xff);
+			SSDK_INFO("Chip version 0x%02x%02x\n", priv->version, priv->revision);
+		}
+	}
+
+	mutex_init(&priv->reg_mutex);
+
+#if defined(IN_SWCONFIG)
+	ret = qca_switchdev_register(priv);
+	if (ret != SW_OK) {
+		return ret;
+	}
+#endif
+
+	snprintf(priv->link_intr_name, IFNAMSIZ, "switch%d", dev_id);
+
+	priv->qca_ssdk_sw_dev_registered = A_TRUE;
+	ret = qca_phy_mib_work_start(qca_phy_priv_global[dev_id]);
+	if (ret != 0) {
+			SSDK_ERROR("qca_phy_mib_work_start failed for chip 0x%02x%02x\n", priv->version, priv->revision);
+			return ret;
+	}
+	ret = qca_link_polling_select(priv);
+	if(ret)
+		priv->link_polling_required = 1;
+	if(priv->link_polling_required)
+	{
+		SSDK_INFO("polling is selected\n");
+		ret = qm_err_check_work_start(priv);
+		if (ret != 0)
+		{
+			SSDK_ERROR("qm_err_check_work_start failed for chip 0x%02x%02x\n", priv->version, priv->revision);
+			return ret;
+		}
+	}
+	else
+	{
+		SSDK_INFO("interrupt is selected\n");
+		priv->interrupt_flag = IRQF_TRIGGER_MASK;
+		ret = qca_intr_init(priv);
+		if(ret)
+		{
+			SSDK_ERROR("the interrupt init faild !\n");
+			return ret;
+		}
+	}
+
+#if 0
+#ifdef DESS
+	if ((ssdk_dt_global.mac_mode == PORT_WRAPPER_SGMII0_RGMII5)
+		||(ssdk_dt_global.mac_mode == PORT_WRAPPER_SGMII1_RGMII5)
+		||(ssdk_dt_global.mac_mode == PORT_WRAPPER_SGMII0_RGMII4)
+		||(ssdk_dt_global.mac_mode == PORT_WRAPPER_SGMII1_RGMII4)
+		||(ssdk_dt_global.mac_mode == PORT_WRAPPER_SGMII4_RGMII4)) {
+		ret = dess_rgmii_mac_work_start(priv);
+		if (ret != 0) {
+			SSDK_ERROR("dess_rgmii_mac_work_start failed for chip 0x%02x%02x\n", priv->version, priv->revision);
+			return ret;
+		}
+	}
+#endif
+#endif
+#ifdef HPPE
+	if (priv->version == QCA_VER_HPPE) {
+		ret = qca_mac_sw_sync_work_start(priv);
+		if (ret != 0) {
+			SSDK_ERROR("qca_mac_sw_sync_work_start failed for chip 0x%02x%02x\n",
+				priv->version, priv->revision);
+			return ret;
+		}
+	}
+#endif
+
+	return 0;
+
+}
+
+static int ssdk_switch_unregister(a_uint32_t dev_id)
+{
+	qca_phy_mib_work_stop(qca_phy_priv_global[dev_id]);
+	qm_err_check_work_stop(qca_phy_priv_global[dev_id]);
+#ifdef HPPE
+	qca_mac_sw_sync_work_stop(qca_phy_priv_global[dev_id]);
+#endif
+#if defined(IN_SWCONFIG)
+	unregister_switch(&qca_phy_priv_global[dev_id]->sw_dev);
+#endif
+	return 0;
+}
+#endif
+
+static int
+qca_phy_read_status(struct phy_device *pdev)
+{
+	struct qca_phy_priv *priv = pdev->priv;
+	a_uint32_t port_status;
+	a_uint32_t port_speed;
+	int ret = 0, addr = 0;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+	addr = pdev->mdio.addr;
+#else
+	addr = pdev->addr;
+#endif
+	if (addr != 0) {
+		mutex_lock(&priv->reg_mutex);
+		ret = genphy_read_status(pdev);
+		mutex_unlock(&priv->reg_mutex);
+		return ret;
+	}
+
+	mutex_lock(&priv->reg_mutex);
+	port_status = priv->mii_read(priv->device_id, AR8327_REG_PORT_STATUS(addr));
+	mutex_unlock(&priv->reg_mutex);
+
+	pdev->link = 1;
+	if (port_status & AR8327_PORT_STATUS_LINK_AUTO) {
+		pdev->link = !!(port_status & AR8327_PORT_STATUS_LINK_UP);
+		if (pdev->link == 0) {
+			return ret;
+		}
+	}
+
+	port_speed = (port_status & AR8327_PORT_STATUS_SPEED) >>
+		            AR8327_PORT_STATUS_SPEED_S;
+
+	switch (port_speed) {
+		case AR8327_PORT_SPEED_10M:
+			pdev->speed = SPEED_10;
+			break;
+		case AR8327_PORT_SPEED_100M:
+			pdev->speed = SPEED_100;
+			break;
+		case AR8327_PORT_SPEED_1000M:
+			pdev->speed = SPEED_1000;
+			break;
+		default:
+			pdev->speed = 0;
+			break;
+	}
+
+	if(port_status & AR8327_PORT_STATUS_DUPLEX) {
+		pdev->duplex = DUPLEX_FULL;
+	} else {
+		pdev->duplex = DUPLEX_HALF;
+	}
+
+	pdev->state = PHY_RUNNING;
+	netif_carrier_on(pdev->attached_dev);
+	pdev->adjust_link(pdev->attached_dev);
+
+	return ret;
+}
+
+static int
+qca_phy_config_aneg(struct phy_device *pdev)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+	if (pdev->mdio.addr != 0) {
+#else
+	if (pdev->addr != 0) {
+#endif
+		return genphy_config_aneg(pdev);
+	}
+
+	return 0;
+}
+
+int qca_phy_suspend(struct phy_device *phydev)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+	struct mii_bus *bus = phydev->mdio.bus;
+#else
+	struct mii_bus *bus = phydev->bus;
+#endif
+	int val = 0;
+	int addr;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+	addr = phydev->mdio.addr;
+#else
+	addr = phydev->addr;
+#endif
+
+	val = mdiobus_read(bus, addr, MII_BMCR);
+	return mdiobus_write(bus, addr, MII_BMCR, (u16)(val | BMCR_PDOWN));
+}
+
+int qca_phy_resume(struct phy_device *phydev)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+	struct mii_bus *bus = phydev->mdio.bus;
+#else
+	struct mii_bus *bus = phydev->bus;
+#endif
+	int val = 0;
+	int addr;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+	addr = phydev->mdio.addr;
+#else
+	addr = phydev->addr;
+#endif
+
+	val = mdiobus_read(bus, addr, MII_BMCR);
+	return mdiobus_write(bus, addr, MII_BMCR, (u16)(val & ~BMCR_PDOWN));
+}
+
+static int
+qca_phy_probe(struct phy_device *pdev)
+{
+	struct qca_phy_priv *priv;
+	int ret;
+
+	priv = kzalloc(sizeof(struct qca_phy_priv), GFP_KERNEL);
+	if (priv == NULL) {
+		return -ENOMEM;
+	}
+
+	pdev->priv = priv;
+	priv->phy = pdev;
+	mutex_init(&priv->reg_mutex);
+
+	ret = qca_phy_id_chip(priv);
+	return ret;
+}
+
+static void
+qca_phy_remove(struct phy_device *pdev)
+{
+	struct qca_phy_priv *priv = pdev->priv;
+	int addr;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+	addr = pdev->mdio.addr;
+#else
+	addr = pdev->addr;
+#endif
+
+	if ((addr == 0) && priv && (priv->ports != 0)) {
+		qca_phy_mib_work_stop(priv);
+		qm_err_check_work_stop(priv);
+#if defined(IN_SWCONFIG)
+		if (priv->sw_dev.name != NULL)
+			unregister_switch(&priv->sw_dev);
+#endif
+	}
+
+	if (priv) {
+		kfree(priv);
+    }
+}
+
+static struct phy_driver qca_phy_driver = {
+    .name		= "QCA AR8216 AR8236 AR8316 AR8327 AR8337",
+	.phy_id		= 0x004d0000,
+	.phy_id_mask= 0xffff0000,
+	.probe		= qca_phy_probe,
+	.remove		= qca_phy_remove,
+	.config_init= &qca_phy_config_init,
+	.config_aneg= &qca_phy_config_aneg,
+	.read_status= &qca_phy_read_status,
+	.suspend	= qca_phy_suspend,
+	.resume		= qca_phy_resume,
+	.features	= PHY_BASIC_FEATURES,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+	.mdiodrv.driver		= { .owner = THIS_MODULE },
+#else
+	.driver		= { .owner = THIS_MODULE },
+#endif
+};
+
+#ifndef BOARD_AR71XX
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#ifdef DESS
+struct reset_control *ess_rst = NULL;
+struct reset_control *ess_mac_clock_disable[5] = {NULL,NULL,NULL,NULL,NULL};
+
+void ssdk_ess_reset(void)
+{
+	if (!ess_rst)
+		return;
+	reset_control_assert(ess_rst);
+	mdelay(10);
+	reset_control_deassert(ess_rst);
+	mdelay(100);
+}
+#endif
+
+char ssdk_driver_name[] = "ess_ssdk";
+
+static int ssdk_probe(struct platform_device *pdev)
+{
+	struct device_node *np;
+
+	np = of_node_get(pdev->dev.of_node);
+	if (of_device_is_compatible(np, "qcom,ess-instance"))
+		return of_platform_populate(np, NULL, NULL, &pdev->dev);
+
+#ifdef DESS
+	ess_rst = devm_reset_control_get(&pdev->dev, "ess_rst");
+	ess_mac_clock_disable[0] = devm_reset_control_get(&pdev->dev, "ess_mac1_clk_dis");
+	ess_mac_clock_disable[1] = devm_reset_control_get(&pdev->dev, "ess_mac2_clk_dis");
+	ess_mac_clock_disable[2] = devm_reset_control_get(&pdev->dev, "ess_mac3_clk_dis");
+	ess_mac_clock_disable[3] = devm_reset_control_get(&pdev->dev, "ess_mac4_clk_dis");
+	ess_mac_clock_disable[4] = devm_reset_control_get(&pdev->dev, "ess_mac5_clk_dis");
+
+	if (IS_ERR(ess_rst)) {
+		SSDK_INFO("ess_rst doesn't exist!\n");
+		return 0;
+	}
+	if (!ess_mac_clock_disable[0]) {
+		SSDK_ERROR("ess_mac1_clock_disable fail!\n");
+		return -1;
+	}
+	if (!ess_mac_clock_disable[1]) {
+		SSDK_ERROR("ess_mac2_clock_disable fail!\n");
+		return -1;
+	}
+	if (!ess_mac_clock_disable[2]) {
+		SSDK_ERROR("ess_mac3_clock_disable fail!\n");
+		return -1;
+	}
+	if (!ess_mac_clock_disable[3]) {
+		SSDK_ERROR("ess_mac4_clock_disable fail!\n");
+		return -1;
+	}
+	if (!ess_mac_clock_disable[4]) {
+		SSDK_ERROR("ess_mac5_clock_disable fail!\n");
+		return -1;
+	}
+#endif
+	return 0;
+}
+
+static const struct of_device_id ssdk_of_mtable[] = {
+	{.compatible = "qcom,ess-switch" },
+	{.compatible = "qcom,ess-switch-ipq60xx" },
+	{.compatible = "qcom,ess-switch-ipq807x" },
+	{.compatible = "qcom,ess-instance" },
+	{}
+};
+
+static struct platform_driver ssdk_driver = {
+        .driver = {
+                .name    = ssdk_driver_name,
+                .owner   = THIS_MODULE,
+                .of_match_table = ssdk_of_mtable,
+        },
+        .probe    = ssdk_probe,
+};
+#endif
+#endif
+#ifdef DESS
+static u32 phy_t_status = 0;
+static a_uint16_t modectrl_data = 0;
+void ssdk_malibu_psgmii_and_dakota_dess_reset(a_uint32_t dev_id, a_uint32_t first_phy_addr)
+{
+#ifndef BOARD_AR71XX
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
+	int m = 0, n = 0;
+	a_uint32_t psgmii_phy_addr;
+
+	psgmii_phy_addr = first_phy_addr + 5;
+
+	/*reset Malibu PSGMII and Dakota ESS start*/
+	qca_ar8327_phy_write(dev_id, psgmii_phy_addr, 0x0, 0x005b);/*fix phy psgmii RX 20bit*/
+	qca_ar8327_phy_write(dev_id, psgmii_phy_addr, 0x0, 0x001b);/*reset phy psgmii*/
+	qca_ar8327_phy_write(dev_id, psgmii_phy_addr, 0x0, 0x005b);/*release reset phy psgmii*/
+	/* mdelay(100); this 100ms be replaced with below malibu psgmii calibration process*/
+	/*check malibu psgmii calibration done start*/
+	n = 0;
+	while (n < 100) {
+		u16 status;
+		status = qca_phy_mmd_read(dev_id, psgmii_phy_addr, 1, 0x28);
+		if (status & BIT(0))
+			break;
+		mdelay(10);
+		n++;
+	}
+#ifdef PSGMII_DEBUG
+	if (n >= 100)
+		SSDK_INFO("MALIBU PSGMII PLL_VCO_CALIB NOT READY\n");
+#endif
+	mdelay(50);
+	/*check malibu psgmii calibration done end..*/
+	qca_ar8327_phy_write(dev_id, psgmii_phy_addr, 0x1a, 0x2230);/*freeze phy psgmii RX CDR*/
+
+	ssdk_ess_reset();
+	/*check dakota psgmii calibration done start*/
+	m = 0;
+	while (m < 100) {
+		u32 status = 0;
+		qca_psgmii_reg_read(dev_id, 0xa0, (a_uint8_t *)&status, 4);
+		if (status & BIT(0))
+			break;
+		mdelay(10);
+		m++;
+	}
+#ifdef PSGMII_DEBUG
+	if (m >= 100)
+		SSDK_INFO("DAKOTA PSGMII PLL_VCO_CALIB NOT READY\n");
+#endif
+	mdelay(50);
+	/*check dakota psgmii calibration done end..*/
+	qca_ar8327_phy_write(dev_id, psgmii_phy_addr, 0x1a, 0x3230);/*relesae phy psgmii RX CDR*/
+	qca_ar8327_phy_write(dev_id, psgmii_phy_addr, 0x0, 0x005f);/*release phy psgmii RX 20bit*/
+	mdelay(200);
+#endif
+#endif
+	/*reset Malibu PSGMII and Dakota ESS end*/
+	return;
+}
+
+static void ssdk_psgmii_phy_testing_printf(a_uint32_t phy, u32 tx_ok, u32 rx_ok,
+				u32 tx_counter_error, u32 rx_counter_error)
+{
+	SSDK_INFO("tx_ok = 0x%x, rx_ok = 0x%x, tx_counter_error = 0x%x, rx_counter_error = 0x%x\n",
+			tx_ok, rx_ok, tx_counter_error, rx_counter_error);
+	if (tx_ok== 0x3000 && tx_counter_error == 0)
+		SSDK_INFO("PHY %d single PSGMII test pass\n", phy);
+	else
+		SSDK_ERROR("PHY %d single PSGMII test fail\n", phy);
+	return;
+
+}
+static void ssdk_psgmii_all_phy_testing_printf(a_uint32_t phy, u32 tx_ok, u32 rx_ok,
+				u32 tx_counter_error, u32 rx_counter_error)
+{
+	SSDK_INFO("tx_ok = 0x%x, rx_ok = 0x%x, tx_counter_error = 0x%x, rx_counter_error = 0x%x\n",
+			tx_ok, rx_ok, tx_counter_error, rx_counter_error);
+	if (tx_ok== 0x3000 && tx_counter_error == 0)
+		SSDK_INFO("PHY %d all PSGMII test pass\n", phy);
+	else
+		SSDK_ERROR("PHY %d all PSGMII test fail\n", phy);
+	return;
+
+}
+void ssdk_psgmii_single_phy_testing(a_uint32_t dev_id, a_uint32_t phy, a_bool_t enable)
+{
+	int j = 0;
+
+	u32 tx_counter_ok, tx_counter_error;
+	u32 rx_counter_ok, rx_counter_error;
+	u32 tx_counter_ok_high16;
+	u32 rx_counter_ok_high16;
+	u32 tx_ok, rx_ok;
+	qca_ar8327_phy_write(dev_id, phy, 0x0, 0x9000);
+	qca_ar8327_phy_write(dev_id, phy, 0x0, 0x4140);
+	j = 0;
+	while (j < 100) {
+		u16 status = 0;
+		qca_ar8327_phy_read(dev_id, phy, 0x11, &status);
+		if (status & (1 << 10))
+			break;
+		mdelay(10);
+		j++;
+	}
+	/*add a 300ms delay as qm polling task existing*/
+	if (enable == A_TRUE)
+		mdelay(300);
+
+	/*enable check*/
+	qca_phy_mmd_write(dev_id, phy, 7, 0x8029, 0x0000);
+	qca_phy_mmd_write(dev_id, phy, 7, 0x8029, 0x0003);
+
+	/*start traffic*/
+	qca_phy_mmd_write(dev_id, phy, 7, 0x8020, 0xa000);
+	mdelay(200);
+
+	/*check counter*/
+	tx_counter_ok = qca_phy_mmd_read(dev_id, phy, 7, 0x802e);
+	tx_counter_ok_high16 = qca_phy_mmd_read(dev_id, phy, 7, 0x802d);
+	tx_counter_error = qca_phy_mmd_read(dev_id, phy, 7, 0x802f);
+	rx_counter_ok = qca_phy_mmd_read(dev_id, phy, 7, 0x802b);
+	rx_counter_ok_high16 = qca_phy_mmd_read(dev_id, phy, 7, 0x802a);
+	rx_counter_error = qca_phy_mmd_read(dev_id, phy, 7, 0x802c);
+	tx_ok = tx_counter_ok + (tx_counter_ok_high16<<16);
+	rx_ok = rx_counter_ok + (rx_counter_ok_high16<<16);
+	if (tx_ok== 0x3000 && tx_counter_error == 0) {
+		/*success*/
+		phy_t_status &= (~(1<<phy));
+	} else {
+		phy_t_status |= (1<<phy);
+	}
+
+	if (enable == A_TRUE)
+		ssdk_psgmii_phy_testing_printf(phy, tx_ok, rx_ok,
+				tx_counter_error, rx_counter_error);
+
+	qca_ar8327_phy_write(dev_id, phy, 0x0, 0x1840);
+}
+
+void ssdk_psgmii_all_phy_testing(a_uint32_t dev_id, a_uint32_t first_phy_addr, a_bool_t enable)
+{
+	int j = 0;
+	a_uint32_t phy = 0;
+	qca_ar8327_phy_write(dev_id, 0x1f, 0x0, 0x9000);
+	qca_ar8327_phy_write(dev_id, 0x1f, 0x0, 0x4140);
+	j = 0;
+	while (j < 100) {
+		for (phy = first_phy_addr; phy < first_phy_addr + 5; phy++) {
+			u16 status = 0;
+			qca_ar8327_phy_read(dev_id, phy, 0x11, &status);
+			if (!(status & (1 << 10)))
+				break;
+		}
+
+		if (phy >= (first_phy_addr + 5))
+			break;
+		mdelay(10);
+		j++;
+	}
+	/*add a 300ms delay as qm polling task existing*/
+	if (enable == A_TRUE)
+		mdelay(300);
+
+	/*enable check*/
+	qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8029, 0x0000);
+	qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8029, 0x0003);
+
+	/*start traffic*/
+	qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8020, 0xa000);
+	mdelay(200);
+	for (phy = first_phy_addr; phy < first_phy_addr + 5; phy++) {
+		u32 tx_counter_ok, tx_counter_error;
+		u32 rx_counter_ok, rx_counter_error;
+		u32 tx_counter_ok_high16;
+		u32 rx_counter_ok_high16;
+		u32 tx_ok, rx_ok;
+		/*check counter*/
+		tx_counter_ok = qca_phy_mmd_read(dev_id, phy, 7, 0x802e);
+		tx_counter_ok_high16 = qca_phy_mmd_read(dev_id, phy, 7, 0x802d);
+		tx_counter_error = qca_phy_mmd_read(dev_id, phy, 7, 0x802f);
+		rx_counter_ok = qca_phy_mmd_read(dev_id, phy, 7, 0x802b);
+		rx_counter_ok_high16 = qca_phy_mmd_read(dev_id, phy, 7, 0x802a);
+		rx_counter_error = qca_phy_mmd_read(dev_id, phy, 7, 0x802c);
+		tx_ok = tx_counter_ok + (tx_counter_ok_high16<<16);
+		rx_ok = rx_counter_ok + (rx_counter_ok_high16<<16);
+		if (tx_ok== 0x3000 && tx_counter_error == 0) {
+			/*success*/
+			phy_t_status &= (~(1<<(phy+8)));
+		} else {
+			phy_t_status |= (1<<(phy+8));
+		}
+
+		if (enable == A_TRUE)
+			ssdk_psgmii_all_phy_testing_printf(phy, tx_ok,
+					rx_ok,
+					tx_counter_error, rx_counter_error);
+		}
+	if (enable == A_TRUE)
+		SSDK_INFO("PHY final test result: 0x%x \r\n",phy_t_status);
+
+}
+
+void ssdk_psgmii_get_first_phy_address(a_uint32_t dev_id,
+	a_uint32_t *first_phy_addr)
+{
+	a_uint32_t port_id = 0, phy_addr = 0, phy_cnt = 0;
+	a_uint32_t port_bmp[SW_MAX_NR_DEV] = {0};
+
+	port_bmp[dev_id] = qca_ssdk_phy_type_port_bmp_get(dev_id, MALIBU_PHY_CHIP);
+
+	for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++)
+	{
+		if (port_bmp[dev_id] & (0x1 << port_id))
+		{
+			phy_cnt ++;
+			phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id);
+			if (phy_addr < *first_phy_addr) {
+				*first_phy_addr = phy_addr;
+			}
+		}
+	}
+	if ((phy_cnt == QCA8072_PHY_NUM) && (*first_phy_addr >= 0x3)) {
+		*first_phy_addr = *first_phy_addr - 3;
+	}
+}
+
+void ssdk_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable, a_uint32_t times,
+				a_uint32_t *result)
+{
+	int i = 0;
+	u32 value = 0;
+	a_uint32_t first_phy_addr = MAX_PHY_ADDR + 1, phy = 0;
+
+	ssdk_psgmii_get_first_phy_address(dev_id, &first_phy_addr);
+	if ((first_phy_addr < 0) || (first_phy_addr > MAX_PHY_ADDR)) {
+		return;
+	}
+
+	if (enable == A_FALSE) {
+		ssdk_malibu_psgmii_and_dakota_dess_reset(dev_id, first_phy_addr);
+	}
+
+	qca_ar8327_phy_read(dev_id, first_phy_addr + 4, 0x1f, &modectrl_data);
+	qca_ar8327_phy_write(dev_id, first_phy_addr + 4, 0x1f, 0x8500);/*switch to access MII reg for copper*/
+	for(phy = first_phy_addr; phy < first_phy_addr + 5; phy++) {
+		/*enable phy mdio broadcast write*/
+		qca_phy_mmd_write(dev_id, phy, 7, 0x8028, 0x801f);
+	}
+
+	/* force no link by power down */
+	qca_ar8327_phy_write(dev_id, 0x1f, 0x0, 0x1840);
+
+	/*packet number*/
+	qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8021, 0x3000);
+	qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8062, 0x05e0);
+
+	/*fix mdi status */
+	qca_ar8327_phy_write(dev_id, 0x1f, 0x10, 0x6800);
+
+	for(i = 0; i < times; i++) {
+		phy_t_status = 0;
+
+		for(phy = 0; phy < 5; phy++) {
+			value = readl(qca_phy_priv_global[dev_id]->hw_addr + 0x66c + phy * 0xc);
+			writel((value|(1<<21)), (qca_phy_priv_global[dev_id]->hw_addr + 0x66c + phy * 0xc));
+		}
+
+		for (phy = first_phy_addr; phy < first_phy_addr + 5; phy++) {
+			ssdk_psgmii_single_phy_testing(dev_id, phy, enable);
+		}
+		ssdk_psgmii_all_phy_testing(dev_id, first_phy_addr, enable);
+		if (enable == A_FALSE) {
+			if (phy_t_status) {
+				ssdk_malibu_psgmii_and_dakota_dess_reset(dev_id, first_phy_addr);
+			}
+			else
+			{
+		                break;
+			}
+		}
+	}
+
+	*result = phy_t_status;
+#ifdef PSGMII_DEBUG
+	if (i>=100)
+		SSDK_ERROR("PSGMII cannot recover\n");
+	else
+		SSDK_INFO("PSGMII recovered after %d times reset\n",i);
+#endif
+	/*configuration recover*/
+	/*packet number*/
+	qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8021, 0x0);
+	/*disable check*/
+	qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8029, 0x0);
+	/*disable traffic*/
+	qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8020, 0x0);
+}
+
+
+void clear_self_test_config(a_uint32_t dev_id)
+{
+	u32 value = 0;
+	a_uint32_t first_phy_addr = MAX_PHY_ADDR + 1, phy = 0;
+
+	ssdk_psgmii_get_first_phy_address(dev_id, &first_phy_addr);
+	if ((first_phy_addr < 0) || (first_phy_addr > MAX_PHY_ADDR)) {
+		return;
+	}
+
+	/* disable EEE */
+	/* qca_phy_mmd_write(0, 0x1f, 0x7,  0x3c, 0x0); */
+
+	/*disable phy internal loopback*/
+	qca_ar8327_phy_write(dev_id, 0x1f, 0x10, 0x6860);
+	qca_ar8327_phy_write(dev_id, 0x1f, 0x0, 0x9040);
+
+	for(phy = 0; phy < 5; phy++)
+	{
+		/*disable mac loop back*/
+		value = readl(qca_phy_priv_global[dev_id]->hw_addr+0x66c+phy*0xc);
+		writel((value&(~(1<<21))), (qca_phy_priv_global[dev_id]->hw_addr+0x66c+phy*0xc));
+	}
+
+	for(phy = first_phy_addr; phy < first_phy_addr + 5; phy++)
+	{
+		/*diable phy mdio broadcast write*/
+		qca_phy_mmd_write(dev_id, phy, 7, 0x8028, 0x001f);
+
+	}
+
+	qca_ar8327_phy_write(dev_id, first_phy_addr + 4, 0x1f, modectrl_data);
+
+	/* clear fdb entry */
+	fal_fdb_entry_flush(dev_id,1);
+}
+#endif
+/*qca808x_start*/
+sw_error_t
+ssdk_init(a_uint32_t dev_id, ssdk_init_cfg * cfg)
+{
+	sw_error_t rv;
+
+	rv = fal_init(dev_id, cfg);
+	if (rv != SW_OK)
+		SSDK_ERROR("ssdk fal init failed: %d. \r\n", rv);
+
+	rv = ssdk_phy_driver_init(dev_id, cfg);
+	if (rv != SW_OK)
+		SSDK_ERROR("ssdk phy init failed: %d. \r\n", rv);
+
+	return rv;
+}
+
+sw_error_t
+ssdk_cleanup(void)
+{
+	sw_error_t rv;
+
+	rv = fal_cleanup();
+	rv = ssdk_phy_driver_cleanup();
+
+	return rv;
+}
+/*qca808x_end*/
+
+sw_error_t
+ssdk_hsl_access_mode_set(a_uint32_t dev_id, hsl_access_mode reg_mode)
+{
+    sw_error_t rv;
+
+    rv = hsl_access_mode_set(dev_id, reg_mode);
+    return rv;
+}
+
+void switch_cpuport_setup(a_uint32_t dev_id)
+{
+#ifdef IN_PORTCONTROL
+	//According to HW suggestion, enable CPU port flow control for Dakota
+	fal_port_flowctrl_forcemode_set(dev_id, 0, A_TRUE);
+	fal_port_flowctrl_set(dev_id, 0, A_TRUE);
+	fal_port_duplex_set(dev_id, 0, FAL_FULL_DUPLEX);
+	fal_port_speed_set(dev_id, 0, FAL_SPEED_1000);
+	udelay(10);
+	fal_port_txmac_status_set(dev_id, 0, A_TRUE);
+	fal_port_rxmac_status_set(dev_id, 0, A_TRUE);
+#endif
+}
+#ifdef IN_AQUANTIA_PHY
+#ifdef CONFIG_MDIO
+static struct mdio_if_info ssdk_mdio_ctl;
+#endif
+static struct net_device *ssdk_miireg_netdev = NULL;
+
+static int ssdk_miireg_open(struct net_device *netdev)
+{
+	return 0;
+}
+static int ssdk_miireg_close(struct net_device *netdev)
+{
+	return 0;
+}
+
+static int ssdk_miireg_do_ioctl(struct net_device *netdev,
+			struct ifreq *ifr, int32_t cmd)
+{
+	int ret = -EINVAL;
+#ifdef CONFIG_MDIO
+	struct mii_ioctl_data *mii_data = if_mii(ifr);
+	ret = mdio_mii_ioctl(&ssdk_mdio_ctl, mii_data, cmd);
+#endif
+	return ret;
+}
+
+static const struct net_device_ops ssdk_netdev_ops = {
+	.ndo_open = &ssdk_miireg_open,
+	.ndo_stop = &ssdk_miireg_close,
+	.ndo_do_ioctl = &ssdk_miireg_do_ioctl,
+};
+
+#ifdef CONFIG_MDIO
+extern struct mutex switch_mdio_lock;
+static int ssdk_miireg_ioctl_read(struct net_device *netdev, int phy_addr, int mmd, uint16_t addr)
+{
+	a_uint32_t reg = 0;
+	a_uint16_t val = 0;
+
+	if (MDIO_DEVAD_NONE == mmd) {
+		qca_ar8327_phy_read(0, phy_addr, addr, &val);
+		return (int)val;
+	}
+
+	reg = MII_ADDR_C45 | mmd << 16 | addr;
+	mutex_lock(&switch_mdio_lock);
+	qca_ar8327_phy_read(0, phy_addr, reg, &val);
+	mutex_unlock(&switch_mdio_lock);
+
+	return (int)val;
+}
+
+static int ssdk_miireg_ioctl_write(struct net_device *netdev, int phy_addr, int mmd,
+				uint16_t addr, uint16_t value)
+{
+	a_uint32_t reg = 0;
+
+	if (MDIO_DEVAD_NONE == mmd) {
+		qca_ar8327_phy_write(0, phy_addr, addr, value);
+		return 0;
+	}
+
+	reg = MII_ADDR_C45 | mmd << 16 | addr;
+	mutex_lock(&switch_mdio_lock);
+	qca_ar8327_phy_write(0, phy_addr, reg, value);
+	mutex_unlock(&switch_mdio_lock);
+
+	return 0;
+}
+#endif
+
+static void ssdk_netdev_setup(struct net_device *dev)
+{
+	dev->netdev_ops = &ssdk_netdev_ops;
+}
+static void ssdk_miireg_ioctrl_register(void)
+{
+	if (ssdk_miireg_netdev)
+		return;
+#ifdef CONFIG_MDIO
+	ssdk_mdio_ctl.mdio_read = ssdk_miireg_ioctl_read;
+	ssdk_mdio_ctl.mdio_write = ssdk_miireg_ioctl_write;
+	ssdk_mdio_ctl.mode_support = MDIO_SUPPORTS_C45;
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,0))
+	ssdk_miireg_netdev = alloc_netdev(100, "miireg", 0, ssdk_netdev_setup);
+#else
+	ssdk_miireg_netdev = alloc_netdev(100, "miireg", ssdk_netdev_setup);
+#endif
+	if (ssdk_miireg_netdev)
+		register_netdev(ssdk_miireg_netdev);
+}
+
+static void ssdk_miireg_ioctrl_unregister(void)
+{
+	if (ssdk_miireg_netdev) {
+		unregister_netdev(ssdk_miireg_netdev);
+		kfree(ssdk_miireg_netdev);
+		ssdk_miireg_netdev = NULL;
+	}
+}
+#endif
+static void ssdk_driver_register(a_uint32_t dev_id)
+{
+	hsl_reg_mode reg_mode;
+	a_bool_t flag;
+
+	reg_mode = ssdk_switch_reg_access_mode_get(dev_id);
+
+	if(reg_mode == HSL_REG_LOCAL_BUS) {
+#ifndef BOARD_AR71XX
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+		platform_driver_register(&ssdk_driver);
+#endif
+#endif
+	}
+
+	flag = ssdk_ess_switch_flag_get(dev_id);
+	if(reg_mode == HSL_REG_MDIO && flag == A_FALSE) {
+		if(driver_find(qca_phy_driver.name, &mdio_bus_type)){
+			SSDK_ERROR("QCA PHY driver had been Registered\n");
+			return;
+		}
+
+		SSDK_INFO("Register QCA PHY driver\n");
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+		phy_driver_register(&qca_phy_driver, THIS_MODULE);
+#else
+		phy_driver_register(&qca_phy_driver);
+#endif
+
+#ifdef BOARD_AR71XX
+#if defined(IN_SWCONFIG)
+		ssdk_uci_takeover_init();
+#endif
+
+#ifdef CONFIG_AR8216_PHY
+		ar8327_port_link_notify_register(ssdk_port_link_notify);
+#endif
+		ar7240_port_link_notify_register(ssdk_port_link_notify);
+#endif
+	}
+}
+
+static void ssdk_driver_unregister(a_uint32_t dev_id)
+{
+	hsl_reg_mode reg_mode;
+	a_bool_t flag;
+
+	reg_mode= ssdk_switch_reg_access_mode_get(dev_id);
+	flag = ssdk_ess_switch_flag_get(dev_id);
+	if(reg_mode == HSL_REG_MDIO && flag == A_FALSE) {
+		phy_driver_unregister(&qca_phy_driver);
+
+#if defined(BOARD_AR71XX) && defined(IN_SWCONFIG)
+		ssdk_uci_takeover_exit();
+#endif
+	}
+
+	if (reg_mode == HSL_REG_LOCAL_BUS) {
+#ifndef BOARD_AR71XX
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+		platform_driver_unregister(&ssdk_driver);
+#endif
+#endif
+	}
+}
+/*qca808x_start*/
+static int chip_is_scomphy(a_uint32_t dev_id, ssdk_init_cfg* cfg)
+{
+	int rv = -ENODEV;
+	a_uint32_t phy_id = 0, port_id = 0;
+	a_uint32_t port_bmp = qca_ssdk_port_bmp_get(dev_id);
+	while (port_bmp) {
+		if (port_bmp & 0x1) {
+			phy_id = hsl_phyid_get(dev_id, port_id, cfg);
+			switch (phy_id) {
+/*qca808x_end*/
+				case QCA8030_PHY:
+				case QCA8033_PHY:
+				case QCA8035_PHY:
+				case MP_GEPHY:
+/*qca808x_start*/
+				case QCA8081_PHY_V1_1:
+						cfg->chip_type = CHIP_SCOMPHY;
+						/*MP GEPHY is always the first port*/
+						if(cfg->phy_id == 0)
+						{
+							cfg->phy_id = phy_id;
+						}
+						rv = SW_OK;
+					break;
+				default:
+					break;
+			}
+		}
+		port_bmp >>= 1;
+		port_id++;
+	}
+
+	return rv;
+}
+
+static int chip_ver_get(a_uint32_t dev_id, ssdk_init_cfg* cfg)
+{
+	int rv = SW_OK;
+	a_uint8_t chip_ver = 0;
+	a_uint8_t chip_revision = 0;
+/*qca808x_end*/
+	hsl_reg_mode reg_mode;
+
+	reg_mode= ssdk_switch_reg_access_mode_get(dev_id);
+	if(reg_mode == HSL_REG_MDIO)
+	{
+		chip_ver = (qca_ar8216_mii_read(dev_id, 0)&0xff00)>>8;
+	}
+	else {
+		a_uint32_t reg_val = 0;
+		qca_switch_reg_read(dev_id,0,(a_uint8_t *)&reg_val, 4);
+		chip_ver = (reg_val&0xff00)>>8;
+		chip_revision = reg_val&0xff;
+	}
+/*qca808x_start*/
+	if(chip_ver == QCA_VER_AR8227)
+		cfg->chip_type = CHIP_SHIVA;
+	else if(chip_ver == QCA_VER_AR8337)
+		cfg->chip_type = CHIP_ISISC;
+	else if(chip_ver == QCA_VER_AR8327)
+		cfg->chip_type = CHIP_ISIS;
+	else if(chip_ver == QCA_VER_DESS)
+		cfg->chip_type = CHIP_DESS;
+	else if(chip_ver == QCA_VER_HPPE) {
+		cfg->chip_type = CHIP_HPPE;
+		cfg->chip_revision = chip_revision;
+	}
+	else {
+		/* try single phy without switch connected */
+		rv = chip_is_scomphy(dev_id, cfg);
+	}
+
+	return rv;
+}
+/*qca808x_end*/
+
+#ifdef DESS
+static int ssdk_flow_default_act_init(a_uint32_t dev_id)
+{
+	a_uint32_t vrf_id = 0;
+	fal_flow_type_t type = 0;
+	for(vrf_id = FAL_MIN_VRF_ID; vrf_id <= FAL_MAX_VRF_ID; vrf_id++)
+	{
+		for(type = FAL_FLOW_LAN_TO_LAN; type <= FAL_FLOW_WAN_TO_WAN; type++)
+		{
+#ifdef IN_IP
+#ifndef IN_IP_MINI
+			fal_default_flow_cmd_set(dev_id, vrf_id, type, FAL_DEFAULT_FLOW_ADMIT_ALL);
+#endif
+#endif
+		}
+	}
+
+	return 0;
+}
+static int ssdk_dess_mac_mode_init(a_uint32_t dev_id, a_uint32_t mac_mode)
+{
+	a_uint32_t reg_value;
+	u8  __iomem      *gcc_addr = NULL;
+
+	switch(mac_mode) {
+		case PORT_WRAPPER_PSGMII:
+		case PORT_WRAPPER_PSGMII_FIBER:
+			reg_value = 0x2200;
+			qca_psgmii_reg_write(dev_id, DESS_PSGMII_MODE_CONTROL,
+								(a_uint8_t *)&reg_value, 4);
+			reg_value = 0x8380;
+			qca_psgmii_reg_write(dev_id, DESS_PSGMIIPHY_TX_CONTROL,
+								(a_uint8_t *)&reg_value, 4);
+			break;
+		case PORT_WRAPPER_SGMII0_RGMII5:
+		case PORT_WRAPPER_SGMII1_RGMII5:
+		case PORT_WRAPPER_SGMII0_RGMII4:
+		case PORT_WRAPPER_SGMII1_RGMII4:
+		case PORT_WRAPPER_SGMII4_RGMII4:
+
+		/*config sgmii */
+			if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII5)
+				||(mac_mode == PORT_WRAPPER_SGMII0_RGMII4)) {
+				/*PSGMII channnel 0 as SGMII*/
+				reg_value = 0x2001;
+				fal_psgmii_reg_set(dev_id, 0x1b4,
+								(a_uint8_t *)&reg_value, 4);
+				udelay(1000);
+			}
+			if ((mac_mode == PORT_WRAPPER_SGMII1_RGMII5)
+				||(mac_mode == PORT_WRAPPER_SGMII1_RGMII4)) {
+				/*PSGMII channnel 1 as SGMII*/
+				reg_value = 0x2003;
+				fal_psgmii_reg_set(dev_id, 0x1b4,
+								(a_uint8_t *)&reg_value, 4);
+				udelay(1000);
+			}
+			if ((mac_mode == PORT_WRAPPER_SGMII4_RGMII4)) {
+				/*PSGMII channnel 4 as SGMII*/
+				reg_value = 0x2005;
+				fal_psgmii_reg_set(dev_id, 0x1b4,
+								(a_uint8_t *)&reg_value, 4);
+				udelay(1000);
+			}
+
+			/*clock gen 1*/
+			reg_value = 0xea6;
+			fal_psgmii_reg_set(dev_id, 0x13c,
+							(a_uint8_t *)&reg_value, 4);
+			mdelay(10);
+			/*softreset psgmii, fixme*/
+			gcc_addr = ioremap_nocache(0x1812000, 0x200);
+			if (!gcc_addr) {
+				SSDK_ERROR("gcc map fail!\n");
+				return 0;
+			} else {
+				SSDK_INFO("gcc map success!\n");
+				writel(0x20, gcc_addr+0xc);
+				mdelay(10);
+				writel(0x0, gcc_addr+0xc);
+				mdelay(10);
+				iounmap(gcc_addr);
+			}
+			/*relock pll*/
+			reg_value = 0x2803;
+			fal_psgmii_reg_set(dev_id, DESS_PSGMII_PLL_VCO_RELATED_CONTROL_1,
+							(a_uint8_t *)&reg_value, 4);
+			udelay(1000);
+			reg_value = 0x4ADA;
+			fal_psgmii_reg_set(dev_id, DESS_PSGMII_VCO_CALIBRATION_CONTROL_1,
+							(a_uint8_t *)&reg_value, 4);
+			udelay(1000);
+			reg_value = 0xADA;
+			fal_psgmii_reg_set(dev_id, DESS_PSGMII_VCO_CALIBRATION_CONTROL_1,
+							(a_uint8_t *)&reg_value, 4);
+			udelay(1000);
+
+			/* Reconfig channel 0 as SGMII and re autoneg*/
+			if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII5)
+				||(mac_mode == PORT_WRAPPER_SGMII0_RGMII4)) {
+			/*PSGMII channnel 0 as SGMII*/
+			reg_value = 0x2001;
+			fal_psgmii_reg_set(dev_id, 0x1b4,
+								(a_uint8_t *)&reg_value, 4);
+			udelay(1000);
+			/* restart channel 0 autoneg*/
+			reg_value = 0xc4;
+			fal_psgmii_reg_set(dev_id, 0x1c8,
+							(a_uint8_t *)&reg_value, 4);
+			mdelay(10);
+			reg_value = 0x44;
+			fal_psgmii_reg_set(dev_id, 0x1c8,
+							(a_uint8_t *)&reg_value, 4);
+			mdelay(10);
+			}
+			/* Reconfig channel 1 as SGMII and re autoneg*/
+			if ((mac_mode == PORT_WRAPPER_SGMII1_RGMII5)
+				||(mac_mode == PORT_WRAPPER_SGMII1_RGMII4)) {
+
+			/*PSGMII channnel 1 as SGMII*/
+			reg_value = 0x2003;
+			fal_psgmii_reg_set(dev_id, 0x1b4,
+							(a_uint8_t *)&reg_value, 4);
+			udelay(1000);
+			/* restart channel 1 autoneg*/
+			reg_value = 0xc4;
+			fal_psgmii_reg_set(dev_id, 0x1e0,
+							(a_uint8_t *)&reg_value, 4);
+			mdelay(10);
+			reg_value = 0x44;
+			fal_psgmii_reg_set(dev_id, 0x1e0,
+							(a_uint8_t *)&reg_value, 4);
+			mdelay(10);
+
+			}
+			/* Reconfig channel 4 as SGMII and re autoneg*/
+			if ((mac_mode == PORT_WRAPPER_SGMII4_RGMII4)) {
+			/*PSGMII channnel 4 as SGMII*/
+			reg_value = 0x2005;
+			fal_psgmii_reg_set(dev_id, 0x1b4,
+							(a_uint8_t *)&reg_value, 4);
+			udelay(1000);
+			/* restart channel 4 autoneg*/
+			reg_value = 0xc4;
+			fal_psgmii_reg_set(dev_id, 0x228,
+							(a_uint8_t *)&reg_value, 4);
+			mdelay(10);
+			reg_value = 0x44;
+			fal_psgmii_reg_set(dev_id, 0x228,
+							(a_uint8_t *)&reg_value, 4);
+			mdelay(10);
+			}
+
+		  	/* config RGMII*/
+			reg_value = 0x400;
+			fal_reg_set(dev_id, 0x4, (a_uint8_t *)&reg_value, 4);
+			/* config mac5 RGMII*/
+			if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII5)
+				||(mac_mode == PORT_WRAPPER_SGMII1_RGMII5)) {
+				qca_ar8327_phy_dbg_write(0, 4, 0x5, 0x2d47);
+				qca_ar8327_phy_dbg_write(0, 4, 0xb, 0xbc40);
+				qca_ar8327_phy_dbg_write(0, 4, 0x0, 0x82ee);
+				reg_value = 0x72;
+				qca_switch_reg_write(dev_id, 0x90, (a_uint8_t *)&reg_value, 4);
+			}
+			/* config mac4 RGMII*/
+			if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII4)
+				||(mac_mode == PORT_WRAPPER_SGMII1_RGMII4)
+				||(mac_mode == PORT_WRAPPER_SGMII4_RGMII4)) {
+				qca_ar8327_phy_dbg_write(dev_id, 4, 0x5, 0x2d47);
+				qca_ar8327_phy_dbg_write(dev_id, 4, 0xb, 0xbc40);
+				qca_ar8327_phy_dbg_write(dev_id, 4, 0x0, 0x82ee);
+				reg_value = 0x72;
+				qca_switch_reg_write(dev_id, 0x8c, (a_uint8_t *)&reg_value, 4);
+			}
+			break;
+		case PORT_WRAPPER_PSGMII_RMII0_RMII1:
+		case PORT_WRAPPER_PSGMII_RMII0:
+		case PORT_WRAPPER_PSGMII_RMII1:
+			reg_value = 0x2200;
+			qca_psgmii_reg_write(dev_id, DESS_PSGMII_MODE_CONTROL,
+				(a_uint8_t *)&reg_value, 4);
+			reg_value = 0x8380;
+			qca_psgmii_reg_write(dev_id, DESS_PSGMIIPHY_TX_CONTROL,
+					(a_uint8_t *)&reg_value, 4);
+			/*switch RMII clock source to gcc_ess_clk,ESS_RGMII_CTRL:0x0C000004,dakota rmii1/rmii0 master mode*/
+			if(mac_mode== PORT_WRAPPER_PSGMII_RMII0_RMII1)
+				reg_value = 0x3000000;
+			if(mac_mode== PORT_WRAPPER_PSGMII_RMII0)
+				reg_value = 0x1000000;
+			if(mac_mode== PORT_WRAPPER_PSGMII_RMII1)
+				reg_value = 0x2000000;
+			qca_switch_reg_write(dev_id, 0x4, (a_uint8_t *)&reg_value, 4);
+			/*enable RMII MAC5 100M/full*/
+			if(mac_mode == PORT_WRAPPER_PSGMII_RMII0_RMII1 || mac_mode == PORT_WRAPPER_PSGMII_RMII0)
+			{
+				reg_value = 0x7d;
+				qca_switch_reg_write(dev_id, 0x90, (a_uint8_t *)&reg_value, 4);
+			}
+
+			/*enable RMII MAC4 100M/full*/
+			if(mac_mode == PORT_WRAPPER_PSGMII_RMII0_RMII1 || mac_mode == PORT_WRAPPER_PSGMII_RMII1)
+			{
+				reg_value = 0x7d;
+				qca_switch_reg_write(dev_id, 0x8C, (a_uint8_t *)&reg_value, 4);
+			}
+			/*set QM CONTROL REGISTER FLOW_DROP_CNT as max*/
+			reg_value = 0x7f007f;
+			qca_switch_reg_write(dev_id, 0x808, (a_uint8_t *)&reg_value, 4);
+
+			/*relock PSGMII PLL*/
+			reg_value = 0x2803;
+			fal_psgmii_reg_set(dev_id, DESS_PSGMII_PLL_VCO_RELATED_CONTROL_1,
+							(a_uint8_t *)&reg_value, 4);
+			udelay(1000);
+			reg_value = 0x4ADA;
+			fal_psgmii_reg_set(dev_id, DESS_PSGMII_VCO_CALIBRATION_CONTROL_1,
+							(a_uint8_t *)&reg_value, 4);
+			udelay(1000);
+			reg_value = 0xADA;
+			fal_psgmii_reg_set(dev_id, DESS_PSGMII_VCO_CALIBRATION_CONTROL_1,
+							(a_uint8_t *)&reg_value, 4);
+			udelay(1000);
+			break;
+	}
+
+	return 0;
+}
+
+#ifdef IN_TRUNK
+#define MULTIPLE_WAN_PORT_CNT 2
+#define TRUNK_ID_OF_MULTIPLE_WAN_PORTS 0
+
+static a_bool_t
+ssdk_dess_multiple_wan_port_check(a_uint32_t dev_id,
+	a_uint32_t wan_bitmap)
+{
+	a_uint32_t port_id = SSDK_PHYSICAL_PORT0, wan_ports_cnt = 0;
+
+	for(port_id = SSDK_PHYSICAL_PORT0; port_id < SSDK_MAX_PORT_NUM;
+		port_id++)
+	{
+		if(BIT(port_id) & wan_bitmap)
+		{
+			wan_ports_cnt++;
+		}
+	}
+	if(wan_ports_cnt >= MULTIPLE_WAN_PORT_CNT)
+	{
+		return A_TRUE;
+	}
+	else
+	{
+		return A_FALSE;
+	}
+}
+
+sw_error_t
+ssdk_dess_trunk_init(a_uint32_t dev_id, a_uint32_t wan_bitmap)
+{
+	sw_error_t rv = SW_OK;
+
+	if(ssdk_dess_multiple_wan_port_check(dev_id, wan_bitmap))
+	{
+		rv = fal_trunk_group_set(dev_id, TRUNK_ID_OF_MULTIPLE_WAN_PORTS,
+			A_TRUE, wan_bitmap);
+		SW_RTN_ON_ERROR(rv);
+	}
+
+	return rv;
+}
+#endif
+
+static sw_error_t
+qca_dess_hw_init(ssdk_init_cfg *cfg, a_uint32_t dev_id)
+{
+	a_uint32_t reg_value = 0;
+	hsl_api_t *p_api;
+	a_uint32_t psgmii_result = 0;
+	a_uint32_t mac_mode;
+
+	mac_mode = ssdk_dt_global_get_mac_mode(dev_id, 0);
+	/*Do Malibu self test to fix packet drop issue firstly*/
+	if ((mac_mode == PORT_WRAPPER_PSGMII) ||
+	    (mac_mode == PORT_WRAPPER_PSGMII_FIBER)) {
+		ssdk_psgmii_self_test(dev_id, A_FALSE, 100, &psgmii_result);
+		clear_self_test_config(dev_id);
+	} else {
+#ifndef BOARD_AR71XX
+		ssdk_ess_reset();
+#endif
+	}
+
+	qca_switch_init(dev_id);
+#ifdef IN_PORTVLAN
+	ssdk_portvlan_init(dev_id);
+#endif
+
+#ifdef IN_PORTVLAN
+	fal_port_rxhdr_mode_set(dev_id, 0, FAL_ALL_TYPE_FRAME_EN);
+#endif
+#ifdef IN_IP
+#ifndef IN_IP_MINI
+	fal_ip_route_status_set(dev_id, A_TRUE);
+#endif
+#endif
+
+	ssdk_flow_default_act_init(dev_id);
+
+	/*set normal hash and disable nat/napt*/
+	qca_switch_reg_read(dev_id, 0x0e38, (a_uint8_t *)&reg_value, 4);
+	reg_value = (reg_value|0x1000000|0x8);
+	reg_value &= ~2;
+	qca_switch_reg_write(dev_id, 0x0e38, (a_uint8_t *)&reg_value, 4);
+#ifdef IN_IP
+#ifndef IN_IP_MINI
+	fal_ip_vrf_base_addr_set(dev_id, 0, 0);
+#endif
+#endif
+
+	p_api = hsl_api_ptr_get (dev_id);
+	if (p_api && p_api->port_flowctrl_thresh_set)
+		p_api->port_flowctrl_thresh_set(dev_id, 0, SSDK_PORT0_FC_THRESH_ON_DFLT,
+							SSDK_PORT0_FC_THRESH_OFF_DFLT);
+
+	if (p_api && p_api->ip_glb_lock_time_set)
+		p_api->ip_glb_lock_time_set(dev_id, FAL_GLB_LOCK_TIME_100US);
+
+
+	/*config psgmii,sgmii or rgmii mode for Dakota*/
+	ssdk_dess_mac_mode_init(dev_id, cfg->mac_mode);
+
+#ifdef IN_LED
+	/*add BGA Board led contorl*/
+	ssdk_dess_led_init(cfg);
+#endif
+#ifdef IN_TRUNK
+	SW_RTN_ON_ERROR(ssdk_dess_trunk_init(dev_id, cfg->port_cfg.wan_bmp));
+#endif
+
+	return SW_OK;
+}
+#endif
+/*qca808x_start*/
+static void ssdk_cfg_default_init(ssdk_init_cfg *cfg)
+{
+	memset(cfg, 0, sizeof(ssdk_init_cfg));
+	cfg->cpu_mode = HSL_CPU_1;
+	cfg->nl_prot = 30;
+	cfg->reg_func.mdio_set = qca_ar8327_phy_write;
+	cfg->reg_func.mdio_get = qca_ar8327_phy_read;
+#if defined(IN_PHY_I2C_MODE)
+	cfg->reg_func.i2c_set = qca_phy_i2c_write;
+	cfg->reg_func.i2c_get = qca_phy_i2c_read;
+#endif
+/*qca808x_end*/
+
+	cfg->reg_func.header_reg_set = qca_switch_reg_write;
+	cfg->reg_func.header_reg_get = qca_switch_reg_read;
+	cfg->reg_func.mii_reg_set = qca_ar8216_mii_write;
+	cfg->reg_func.mii_reg_get = qca_ar8216_mii_read;
+/*qca808x_start*/
+}
+/*qca808x_end*/
+
+#ifdef IN_RFS
+#if defined(CONFIG_RFS_ACCEL)
+int ssdk_netdev_rfs_cb(
+		struct net_device *dev,
+		__be32 src, __be32 dst,
+		__be16 sport, __be16 dport,
+		u8 proto, u16 rxq_index, u32 action)
+{
+	return ssdk_rfs_ipct_rule_set(src, dst, sport, dport,
+							proto, rxq_index, action);
+}
+#endif
+
+#ifdef DESS
+a_bool_t ssdk_intf_search(
+	a_uint8_t *mac, a_uint16_t vid,
+	a_uint8_t *ret_index, a_uint8_t *free_index)
+{
+	a_uint8_t  i = 0;
+
+	for (i = 0; i < SSDK_RFS_INTF_MAX; i++) {
+		if (rfs_intf_tbl[i].vid == 0)
+			*free_index = i;
+		if (!memcmp(rfs_intf_tbl[i].macaddr.uc, mac, 6) &&
+			rfs_intf_tbl[i].vid == vid) {
+			/* find it */
+			*ret_index = i;
+			return A_TRUE;
+		}
+	}
+
+	/* Not find the same entry */
+	return A_FALSE;
+}
+
+static a_bool_t ssdk_is_raw_dev(struct net_device *dev)
+{
+	struct device *pdev;
+
+	pdev = dev->dev.parent;
+	if (!pdev)
+		return A_FALSE;
+
+	if (!strstr(dev_name(pdev), "edma"))
+		return A_FALSE;
+	else
+		return A_TRUE;
+}
+
+static a_uint16_t ssdk_raw_dev_vid_get(struct net_device *dev)
+{
+#ifdef CONFIG_RFS_ACCEL
+	const struct net_device_ops *ops;
+
+	ops = dev->netdev_ops;
+	if (!ops ||
+	    !ops->ndo_get_default_vlan_tag) {
+		return 0;
+	}
+	return ops->ndo_get_default_vlan_tag(dev);
+#else
+	return 0;
+#endif
+}
+
+static a_uint16_t ssdk_netdev_vid_get(struct net_device *dev)
+{
+	struct net_device *pdev;
+	a_uint16_t vid = 0;
+
+	if (is_vlan_dev(dev)) {
+		pdev = vlan_dev_real_dev(dev);
+		if (!ssdk_is_raw_dev(pdev)) {
+			SSDK_DEBUG("The device %s is not expected!\n", dev->name);
+			return 0;
+		}
+		vid = vlan_dev_vlan_id(dev);
+	} else if (ssdk_is_raw_dev(dev)) {
+		vid = ssdk_raw_dev_vid_get(dev);
+	} else if (dev->priv_flags & IFF_EBRIDGE) {
+		/* Do nothing for bridge */
+	} else {
+		SSDK_DEBUG("The device %s is not expected!\n", dev->name);
+	}
+
+	return vid;
+}
+
+static void ssdk_rfs_intf_add(struct net_device *dev)
+{
+	a_uint8_t *devmac = NULL;
+	a_uint16_t vid = 0;
+	fal_intf_mac_entry_t intf_entry;
+	sw_error_t rv = 0;
+	a_uint8_t index0, index1;
+
+	/* get vid */
+	vid = ssdk_netdev_vid_get(dev);
+	if (vid == 0)
+		return;
+
+	/*get mac*/
+	devmac = (a_uint8_t*)(dev->dev_addr);
+
+	if (ssdk_intf_search(devmac, vid, &index0, &index1)) {
+		/* already exist, ignore */
+		return;
+	}
+	rfs_intf_tbl[index1].vid = vid;
+	rfs_intf_tbl[index1].if_idx = dev->ifindex;
+	memcpy(&rfs_intf_tbl[index1].macaddr, devmac, ETH_ALEN);
+
+	memset(&intf_entry, 0, sizeof(intf_entry));
+	intf_entry.ip4_route = 1;
+	intf_entry.ip6_route = 1;
+	intf_entry.vid_low = vid;
+	intf_entry.vid_high = vid;
+	memcpy(&intf_entry.mac_addr, devmac, 6);
+	rv = fal_ip_intf_entry_add(0, &intf_entry);
+	if (rv) {
+		SSDK_ERROR("Faled to add intf entry, rv=%d\n", rv);
+		memset(&rfs_intf_tbl[index1], 0, sizeof(ssdk_rfs_intf_t));
+		return;
+	}
+
+	rfs_intf_tbl[index1].hw_idx = intf_entry.entry_id;
+
+}
+
+static void ssdk_rfs_intf_del(struct net_device *dev)
+{
+	a_uint8_t i = 0;
+	fal_intf_mac_entry_t intf_entry;
+	sw_error_t rv = 0;
+
+	for (i = 0; i < SSDK_RFS_INTF_MAX; i++) {
+		if ((rfs_intf_tbl[i].if_idx == dev->ifindex) &&
+		    (rfs_intf_tbl[i].vid != 0)) {
+			intf_entry.entry_id = rfs_intf_tbl[i].hw_idx;
+			rv = fal_ip_intf_entry_del(0, 1, &intf_entry);
+			if (rv) {
+				SSDK_ERROR("Faled to del entry, rv=%d\n", rv);
+			} else {
+				memset(&rfs_intf_tbl[i], 0, sizeof(ssdk_rfs_intf_t));
+			}
+			return;
+		}
+	}
+}
+
+static int ssdk_inet_event(struct notifier_block *this, unsigned long event, void *ptr)
+{
+	struct net_device *dev = ((struct in_ifaddr *)ptr)->ifa_dev->dev;
+
+	/* Ignore the wireless dev */
+#ifdef CONFIG_WIRELESS_EXT
+	if (dev->wireless_handlers)
+		return NOTIFY_DONE;
+	else
+#endif
+		if (dev->ieee80211_ptr)
+			return NOTIFY_DONE;
+
+	switch (event) {
+		case NETDEV_DOWN:
+			ssdk_rfs_intf_del(dev);
+			break;
+		case NETDEV_UP:
+			ssdk_rfs_intf_add(dev);
+			break;
+	}
+	return NOTIFY_DONE;
+}
+#endif
+#endif
+
+//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+static int ssdk_dev_event(struct notifier_block *this, unsigned long event, void *ptr)
+{
+	int rv = 0;
+	ssdk_init_cfg cfg;
+#ifdef MP
+	a_uint32_t port_id = 0, dev_id = 0;
+	struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id);
+	adpt_api_t *p_api = adpt_api_ptr_get(dev_id);
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
+#else
+	struct net_device *dev = (struct net_device *)ptr;
+#endif
+
+	ssdk_cfg_default_init(&cfg);
+	rv = chip_ver_get(0, &cfg);
+	if (rv) {
+		SSDK_ERROR("chip verfion get failed\n");
+		return NOTIFY_DONE;
+	}
+	switch (event) {
+#ifdef IN_RFS
+#if defined(CONFIG_RFS_ACCEL)
+		case NETDEV_UP:
+			if (strstr(dev->name, "eth")) {
+				if (dev->netdev_ops && dev->netdev_ops->ndo_register_rfs_filter) {
+					dev->netdev_ops->ndo_register_rfs_filter(dev,
+						ssdk_netdev_rfs_cb);
+				}
+			}
+			break;
+#endif
+#endif
+		case NETDEV_CHANGEMTU:
+			if(dev->type == ARPHRD_ETHER) {
+				if (cfg.chip_type == CHIP_DESS ||
+					cfg.chip_type == CHIP_ISIS ||
+					cfg.chip_type == CHIP_ISISC) {
+					struct net_device *eth_dev = NULL;
+					unsigned int mtu= 0;
+
+					if(!strcmp(dev->name, "eth0")) {
+						eth_dev = dev_get_by_name(&init_net, "eth1");
+					} else if (!strcmp(dev->name, "eth1")) {
+						eth_dev = dev_get_by_name(&init_net, "eth0");
+					} else {
+						return NOTIFY_DONE;
+					}
+					if (!eth_dev) {
+						return NOTIFY_DONE;
+					}
+					mtu = dev->mtu > eth_dev->mtu ? dev->mtu : eth_dev->mtu;
+#ifdef IN_MISC
+					fal_frame_max_size_set(0, mtu + 18);
+#endif
+					dev_put(eth_dev);
+				}
+			}
+			break;
+#ifdef MP
+		case NETDEV_CHANGE:
+			if ((cfg.chip_type == CHIP_SCOMPHY) &&
+				(cfg.phy_id == MP_GEPHY)) {
+				if ((p_api == NULL) || (p_api->adpt_port_netdev_notify_set == NULL)
+					|| (priv == NULL)) {
+					SSDK_ERROR("Failed to get pointer\n");
+					return NOTIFY_DONE;
+				}
+				if (dev->phydev != NULL) {
+					int addr;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+					addr = dev->phydev->mdio.addr;
+#else
+					addr = dev->phydev->addr;
+#endif
+					port_id = qca_ssdk_phy_addr_to_port(priv->device_id,
+						addr);
+					rv = p_api->adpt_port_netdev_notify_set(priv, port_id);
+					if (rv) {
+						SSDK_ERROR("netdev change notify failed\n");
+						return NOTIFY_DONE;
+					}
+				}
+			}
+			break;
+#endif
+	}
+
+	return NOTIFY_DONE;
+}
+
+#ifdef DESS
+static void qca_dess_rfs_remove(void)
+{
+	/* ssdk_dt_global->switch_reg_access_mode == HSL_REG_LOCAL_BUS */
+	if(qca_dess_rfs_registered){
+#if defined (CONFIG_NF_FLOW_COOKIE)
+#ifdef IN_NAT
+#ifdef IN_SFE
+		sfe_unregister_flow_cookie_cb(ssdk_flow_cookie_set);
+#endif
+#endif
+#endif
+#ifdef IN_RFS
+		rfs_ess_device_unregister(&rfs_dev);
+		unregister_inetaddr_notifier(&ssdk_inet_notifier);
+#if defined(CONFIG_RFS_ACCEL)
+#endif
+#endif
+		qca_dess_rfs_registered = false;
+	}
+
+}
+
+static void qca_dess_rfs_init(void)
+{
+	if (!qca_dess_rfs_registered) {
+#if defined (CONFIG_NF_FLOW_COOKIE)
+#ifdef IN_NAT
+#ifdef IN_SFE
+		sfe_register_flow_cookie_cb(ssdk_flow_cookie_set);
+#endif
+#endif
+#endif
+
+#ifdef IN_RFS
+		memset(&rfs_dev, 0, sizeof(rfs_dev));
+		rfs_dev.name = NULL;
+#ifdef IN_FDB
+		rfs_dev.mac_rule_cb = ssdk_rfs_mac_rule_set;
+#endif
+#ifdef IN_IP
+		rfs_dev.ip4_rule_cb = ssdk_rfs_ip4_rule_set;
+		rfs_dev.ip6_rule_cb = ssdk_rfs_ip6_rule_set;
+#endif
+		rfs_ess_device_register(&rfs_dev);
+#if defined(CONFIG_RFS_ACCEL)
+#endif
+		ssdk_inet_notifier.notifier_call = ssdk_inet_event;
+		ssdk_inet_notifier.priority = 1;
+		register_inetaddr_notifier(&ssdk_inet_notifier);
+#endif
+		qca_dess_rfs_registered = true;
+	}
+}
+#endif
+/*qca808x_start*/
+static void ssdk_free_priv(void)
+{
+	a_uint32_t dev_id, dev_num = 1;
+
+	if(!qca_phy_priv_global) {
+		return;
+	}
+/*qca808x_end*/
+	dev_num = ssdk_switch_device_num_get();
+/*qca808x_start*/
+	for (dev_id = 0; dev_id < dev_num; dev_id++) {
+		if (qca_phy_priv_global[dev_id]) {
+			kfree(qca_phy_priv_global[dev_id]);
+		}
+
+		qca_phy_priv_global[dev_id] = NULL;
+	}
+
+	kfree(qca_phy_priv_global);
+
+	qca_phy_priv_global = NULL;
+/*qca808x_end*/
+	ssdk_switch_device_num_exit();
+/*qca808x_start*/
+}
+
+static int ssdk_alloc_priv(a_uint32_t dev_num)
+{
+	int rev = SW_OK;
+	a_uint32_t dev_id = 0;
+
+	qca_phy_priv_global = kzalloc(dev_num * sizeof(struct qca_phy_priv *), GFP_KERNEL);
+	if (qca_phy_priv_global == NULL) {
+		return -ENOMEM;
+	}
+
+	for (dev_id = 0; dev_id < dev_num; dev_id++) {
+		qca_phy_priv_global[dev_id] = kzalloc(sizeof(struct qca_phy_priv), GFP_KERNEL);
+		if (qca_phy_priv_global[dev_id] == NULL) {
+			return -ENOMEM;
+		}
+/*qca808x_end*/
+		qca_phy_priv_global[dev_id]->qca_ssdk_sw_dev_registered = A_FALSE;
+		qca_phy_priv_global[dev_id]->ess_switch_flag = A_FALSE;
+/*qca808x_start*/
+		qca_ssdk_port_bmp_init(dev_id);
+		qca_ssdk_phy_info_init(dev_id);
+	}
+
+	return rev;
+}
+
+#ifndef SSDK_STR
+#define SSDK_STR "ssdk"
+#endif
+#if defined (ISISC) || defined (ISIS)
+static void qca_ar8327_gpio_reset(struct qca_phy_priv *priv)
+{
+	struct device_node *np = NULL;
+	const __be32 *reset_gpio;
+	a_int32_t len;
+	int gpio_num = 0, ret = 0;
+
+	if (priv->ess_switch_flag == A_TRUE)
+		np = priv->of_node;
+	else
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0))
+		np = priv->phy->mdio.dev.of_node;
+#else
+		np = priv->phy->dev.of_node;
+#endif
+	if(!np)
+		return;
+	gpio_num = of_get_named_gpio(np, "reset_gpio", 0);
+	if(gpio_num < 0)
+	{
+		reset_gpio = of_get_property(np, "reset_gpio", &len);
+		if (!reset_gpio )
+		{
+			SSDK_INFO("reset_gpio node does not exist\n");
+			return;
+		}
+		gpio_num = be32_to_cpup(reset_gpio);
+		if(gpio_num <= 0)
+		{
+			SSDK_INFO("reset gpio doesn't exist\n ");
+			return;
+		}
+	}
+	ret = gpio_request(gpio_num, "reset_gpio");
+	if(ret)
+	{
+		SSDK_ERROR("gpio%d request failed, ret:%d\n", gpio_num, ret);
+		return;
+	}
+	gpio_direction_output(gpio_num, SSDK_GPIO_RESET);
+	msleep(200);
+	gpio_set_value(gpio_num, SSDK_GPIO_RELEASE);
+	SSDK_INFO("GPIO%d reset switch done\n", gpio_num);
+
+	gpio_free(gpio_num);
+
+	return;
+}
+#endif
+static int __init regi_init(void)
+{
+	a_uint32_t num = 0, dev_id = 0, dev_num = 1;
+	ssdk_init_cfg cfg;
+/*qca808x_end*/
+	garuda_init_spec_cfg chip_spec_cfg;
+/*qca808x_start*/
+	int rv = 0;
+/*qca808x_end*/
+	/*init switch device num firstly*/
+	ssdk_switch_device_num_init();
+
+	dev_num = ssdk_switch_device_num_get();
+/*qca808x_start*/
+	rv = ssdk_alloc_priv(dev_num);
+	if (rv)
+		goto out;
+
+	for (num = 0; num < dev_num; num++) {
+		ssdk_cfg_default_init(&cfg);
+/*qca808x_end*/
+#ifndef BOARD_AR71XX
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+		if(SW_DISABLE == ssdk_dt_parse(&cfg, num, &dev_id)) {
+			SSDK_INFO("ess-switch node is unavalilable\n");
+			continue;
+		}
+#endif
+#endif
+
+		/* device id is the array index */
+		qca_phy_priv_global[dev_id]->device_id = ssdk_device_id_get(dev_id);
+		qca_phy_priv_global[dev_id]->ess_switch_flag = ssdk_ess_switch_flag_get(dev_id);
+		qca_phy_priv_global[dev_id]->of_node = ssdk_dts_node_get(dev_id);
+/*qca808x_start*/
+		rv = ssdk_plat_init(&cfg, dev_id);
+		SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV);
+/*qca808x_end*/
+		ssdk_driver_register(dev_id);
+/*qca808x_start*/
+		rv = chip_ver_get(dev_id, &cfg);
+		SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV);
+/*qca808x_end*/
+#ifdef IN_AQUANTIA_PHY
+		ssdk_miireg_ioctrl_register();
+#endif
+		memset(&chip_spec_cfg, 0, sizeof(garuda_init_spec_cfg));
+		cfg.chip_spec_cfg = &chip_spec_cfg;
+/*qca808x_start*/
+		rv = ssdk_init(dev_id, &cfg);
+		SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV);
+/*qca808x_end*/
+
+
+		switch (cfg.chip_type)
+		{
+			case CHIP_ISIS:
+			case CHIP_ISISC:
+#if defined (ISISC) || defined (ISIS)
+				if (qca_phy_priv_global[dev_id]->ess_switch_flag == A_TRUE) {
+					SSDK_INFO("Initializing ISISC!!\n");
+					qca_ar8327_gpio_reset(qca_phy_priv_global[dev_id]);
+					rv = ssdk_switch_register(dev_id, cfg.chip_type);
+					SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV);
+					rv = qca_ar8327_hw_init(qca_phy_priv_global[dev_id]);
+					SSDK_INFO("Initializing ISISC Done!!\n");
+				}
+#endif
+				break;
+			case CHIP_HPPE:
+#if defined(HPPE)
+				SSDK_INFO("Initializing HPPE!!\n");
+				qca_hppe_hw_init(&cfg, dev_id);
+				rv = ssdk_switch_register(dev_id, cfg.chip_type);
+				SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV);
+				SSDK_INFO("Initializing HPPE Done!!\n");
+#endif
+				break;
+
+			case CHIP_DESS:
+#if defined(DESS)
+				SSDK_INFO("Initializing DESS!!\n");
+
+				qca_dess_hw_init(&cfg, dev_id);
+				qca_dess_rfs_init();
+
+				/* Setup Cpu port for Dakota platform. */
+				switch_cpuport_setup(dev_id);
+				rv = ssdk_switch_register(dev_id, cfg.chip_type);
+				SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV);
+				SSDK_INFO("Initializing DESS Done!!\n");
+#endif
+				break;
+
+			case CHIP_SHIVA:
+			case CHIP_ATHENA:
+			case CHIP_GARUDA:
+			case CHIP_HORUS:
+			case CHIP_UNSPECIFIED:
+				break;
+			case CHIP_SCOMPHY:
+#if defined(SCOMPHY)
+					SSDK_INFO("Initializing SCOMPHY!\n");
+					rv = qca_scomphy_hw_init(&cfg, dev_id);
+					SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV);
+#if defined(MP)
+					if(cfg.phy_id == MP_GEPHY)
+					{
+						rv = ssdk_switch_register(dev_id, cfg.chip_type);
+						SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV);
+					}
+#endif
+					SSDK_INFO("Initializing SCOMPHY Done!!\n");
+#endif
+				break;
+		}
+
+			fal_module_func_init(dev_id, &cfg);
+/*qca808x_start*/
+
+	}
+/*qca808x_end*/
+
+	ssdk_sysfs_init();
+
+	if (rv == 0){
+		/* register the notifier later should be ok */
+		ssdk_dev_notifier.notifier_call = ssdk_dev_event;
+		ssdk_dev_notifier.priority = 1;
+		register_netdevice_notifier(&ssdk_dev_notifier);
+	}
+/*qca808x_start*/
+
+out:
+	if (rv == 0)
+		SSDK_INFO("qca-%s module init succeeded!\n", SSDK_STR);
+	else {
+		if (rv == -ENODEV) {
+			rv = 0;
+			SSDK_INFO("qca-%s module init, no device found!\n", SSDK_STR);
+		} else {
+			SSDK_INFO("qca-%s module init failed! (code: %d)\n", SSDK_STR, rv);
+			ssdk_free_priv();
+		}
+	}
+
+	return rv;
+}
+
+static void __exit
+regi_exit(void)
+{
+/*qca808x_end*/
+	a_uint32_t dev_id, dev_num = 1;
+/*qca808x_start*/
+	sw_error_t rv;
+/*qca808x_end*/
+	dev_num = ssdk_switch_device_num_get();
+	for (dev_id = 0; dev_id < dev_num; dev_id++) {
+		ssdk_driver_unregister(dev_id);
+#if defined(DESS) || defined(HPPE) || defined(ISISC) || defined(ISIS) || defined(MP)
+		if (qca_phy_priv_global[dev_id]->qca_ssdk_sw_dev_registered == A_TRUE)
+			ssdk_switch_unregister(dev_id);
+#endif
+	}
+/*qca808x_start*/
+	rv = ssdk_cleanup();
+
+	if (rv == 0)
+		SSDK_INFO("qca-%s module exit  done!\n", SSDK_STR);
+	else
+		SSDK_ERROR("qca-%s module exit failed! (code: %d)\n", SSDK_STR, rv);
+/*qca808x_end*/
+
+#ifdef DESS
+	qca_dess_rfs_remove();
+#endif
+
+	ssdk_sysfs_exit();
+#ifdef IN_AQUANTIA_PHY
+	ssdk_miireg_ioctrl_unregister();
+#endif
+	for (dev_id = 0; dev_id < dev_num; dev_id++) {
+		ssdk_plat_exit(dev_id);
+	}
+
+	unregister_netdevice_notifier(&ssdk_dev_notifier);
+/*qca808x_start*/
+	ssdk_free_priv();
+}
+
+module_init(regi_init);
+module_exit(regi_exit);
+
+MODULE_DESCRIPTION("QCA SSDK Driver");
+MODULE_LICENSE("Dual BSD/GPL");
+/*qca808x_end*/
diff --git a/qca-ssdk/src/init/ssdk_interrupt.c b/qca-ssdk/src/init/ssdk_interrupt.c
new file mode 100755
index 0000000..0e0bac8
--- /dev/null
+++ b/qca-ssdk/src/init/ssdk_interrupt.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "fal_init.h"
+#include "fal_reg_access.h"
+#include "sw.h"
+#include "ssdk_init.h"
+#include "fal_init.h"
+#include <linux/phy.h>
+#include <linux/kernel.h>
+#include <linux/kconfig.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <generated/autoconf.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <linux/if_arp.h>
+#include <linux/inetdevice.h>
+#include <linux/netdevice.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/gpio.h>
+#if defined(ISIS)
+#include <isis/isis_reg.h>
+#elif defined(ISISC)
+#include <isisc/isisc_reg.h>
+#else
+#include <dess/dess_reg.h>
+#endif
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0))
+#include <linux/of.h>
+#elif defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#include <linux/of.h>
+#include <drivers/leds/leds-ipq40xx.h>
+#include <linux/of_platform.h>
+#include <linux/reset.h>
+#else
+#include <linux/ar8216_platform.h>
+#endif
+#include "ssdk_plat.h"
+#include "ref_port_ctrl.h"
+
+#define LINK_CHANGE_INTR  0x8000
+/*phy interrupt enable and status register*/
+#define INTERRUPT_ENABLE_REGISTER  0X12
+#define INTERRUPT_STATUS_REGISTER 0X13
+
+extern void qca_ar8327_sw_mac_polling_task(struct qca_phy_priv *priv);
+
+static int qca_phy_disable_intr(struct qca_phy_priv *priv)
+{
+	a_uint32_t  phy_number = 0;
+	a_uint16_t  value;
+
+	for(phy_number = 0; phy_number < 5;  phy_number++)
+	{
+		value = 0;
+		priv->phy_write(priv->device_id, phy_number, INTERRUPT_ENABLE_REGISTER, value);
+		priv->phy_read(priv->device_id, phy_number, INTERRUPT_STATUS_REGISTER, &value);
+	}
+
+	return 0;
+}
+
+static int qca_mac_disable_intr(struct qca_phy_priv *priv)
+{
+	a_uint32_t data;
+
+	fal_reg_get(priv->device_id, GBL_INT_MASK1_OFFSET, (a_uint8_t *)&data, 4);
+	if (data )
+	{
+		data = 0;
+		fal_reg_set(priv->device_id, GBL_INT_MASK1_OFFSET,(a_uint8_t *)&data, 4);
+	}
+	/*fal_reg_get(0, 0x20, (a_uint8_t *)&data, 4);
+	 if (data )
+	  {
+		   data = 0;
+		   fal_reg_set(0, 0x20,(a_uint8_t *)&data, 4);
+	  }
+
+	fal_reg_get(0, 0x28, (a_uint8_t *)&data, 4);
+	fal_reg_set(0, 0x28,(a_uint8_t *)&data, 4);
+   */
+
+	fal_reg_get(priv->device_id, GBL_INT_STATUS1_OFFSET, (a_uint8_t *)&data, 4);
+	fal_reg_set(priv->device_id, GBL_INT_STATUS1_OFFSET,(a_uint8_t *)&data, 4);
+
+	return 0;
+}
+
+static int qca_phy_enable_intr(struct qca_phy_priv *priv)
+{
+	a_uint16_t  value = 0;
+	a_uint32_t phy_number;
+
+	for(phy_number = 0;  phy_number < 5; phy_number++)
+	{
+		priv->phy_read(priv->device_id, phy_number, INTERRUPT_STATUS_REGISTER, &value);
+		/*enable link change intr*/
+		if( !priv->link_polling_required)
+			value = 0xc00;
+		priv->phy_write(priv->device_id,phy_number, INTERRUPT_ENABLE_REGISTER, value);
+	}
+
+	return 0;
+}
+
+int qca_mac_enable_intr(struct qca_phy_priv *priv)
+{
+	a_uint32_t data = 0;
+
+	/*enable link change intr*/
+	if( !priv->link_polling_required)
+		data = 0x8000;
+	fal_reg_set(priv->device_id, GBL_INT_MASK1_OFFSET, (a_uint8_t *)&data, 4);
+
+	return 0;
+}
+static int qca_phy_clean_intr(struct qca_phy_priv *priv)
+{
+	a_uint32_t phy_number;
+	a_uint16_t value;
+
+	for(phy_number = 0; phy_number < 5; phy_number++)
+		priv->phy_read(priv->device_id, phy_number, INTERRUPT_STATUS_REGISTER, &value);
+
+	return 0;
+}
+
+static int qca_mac_clean_intr(struct qca_phy_priv *priv)
+{
+	a_uint32_t data;
+
+	fal_reg_get(priv->device_id, GBL_INT_STATUS1_OFFSET, (a_uint8_t *) &data, 4);
+	fal_reg_set(priv->device_id,  GBL_INT_STATUS1_OFFSET, (a_uint8_t *)&data, 4);
+
+	return 0;
+}
+
+static void
+qca_link_change_task(struct qca_phy_priv *priv)
+{
+	SSDK_DEBUG("qca_link_change_task is running\n");
+	mutex_lock(&priv->qm_lock);
+	qca_ar8327_sw_mac_polling_task(priv);
+	mutex_unlock(&priv->qm_lock);
+}
+
+static void
+qca_intr_workqueue_task(struct work_struct *work)
+{
+	a_uint32_t data;
+	struct qca_phy_priv *priv = container_of(work, struct qca_phy_priv,  intr_workqueue);
+
+	fal_reg_get(priv->device_id,  GBL_INT_STATUS1_OFFSET, (a_uint8_t*)&data, 4);
+	qca_phy_clean_intr(priv);
+	qca_mac_clean_intr(priv);
+	SSDK_DEBUG("data:%x, priv->version:%x\n", data, priv->version);
+	switch(priv->version)
+	{
+		case QCA_VER_DESS:
+			qca_link_change_task(priv);
+			break;
+		default:
+			if((data &LINK_CHANGE_INTR))
+				qca_link_change_task(priv);
+			break;
+	}
+	enable_irq(priv->link_interrupt_no);
+}
+
+ static irqreturn_t  qca_link_intr_handle(int irq, void *phy_priv)
+ {
+	struct qca_phy_priv *priv = (struct qca_phy_priv *)phy_priv;
+
+	 disable_irq_nosync(irq);
+	 schedule_work(&priv->intr_workqueue);
+        SSDK_DEBUG("irq number is :%x\n",irq);
+
+	 return IRQ_HANDLED;
+ }
+
+ int qca_intr_init(struct qca_phy_priv *priv)
+{
+	SSDK_DEBUG("start to  init the interrupt!\n");
+	mutex_init(&priv->qm_lock);
+	INIT_WORK(&priv->intr_workqueue, qca_intr_workqueue_task);
+	qca_phy_disable_intr(priv);
+	qca_mac_disable_intr(priv);
+	if(request_irq(priv->link_interrupt_no, qca_link_intr_handle, priv->interrupt_flag, priv->link_intr_name, priv))
+		return -1;
+	qca_phy_enable_intr(priv);
+	qca_mac_enable_intr(priv);
+
+	return 0;
+}
+
diff --git a/qca-ssdk/src/init/ssdk_led.c b/qca-ssdk/src/init/ssdk_led.c
new file mode 100644
index 0000000..c5dcd08
--- /dev/null
+++ b/qca-ssdk/src/init/ssdk_led.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2012, 2014-2020, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "sw.h"
+#include "ssdk_init.h"
+#include "ssdk_led.h"
+#include <linux/kconfig.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include "ssdk_plat.h"
+
+#if defined(CONFIG_OF)
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0))
+#include <drivers/leds/leds-ipq.h>
+#endif
+#else
+#include <drivers/leds/leds-ipq40xx.h>
+#endif
+#endif
+
+
+#ifdef DESS
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0))
+static int ssdk_dess_led_source_select(int led_num, enum led_source src_type)
+{
+#if defined(CONFIG_OF)
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0))
+	ipq_led_source_select(led_num, src_type);
+#else
+	ipq40xx_led_source_select(led_num, src_type);
+#endif
+#endif
+	return 0;
+}
+#endif
+
+int ssdk_dess_led_init(ssdk_init_cfg *cfg)
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0))
+	a_uint32_t i,led_num, led_source_id,source_id;
+	led_ctrl_pattern_t  pattern;
+
+	if(cfg->led_source_num != 0) {
+		for (i = 0; i < cfg->led_source_num; i++) {
+
+			led_source_id = cfg->led_source_cfg[i].led_source_id;
+			pattern.mode = cfg->led_source_cfg[i].led_pattern.mode;
+			pattern.map = cfg->led_source_cfg[i].led_pattern.map;
+			pattern.freq = cfg->led_source_cfg[i].led_pattern.freq;
+#ifdef IN_LED
+			fal_led_source_pattern_set(0, led_source_id,&pattern);
+#endif
+			led_num = ((led_source_id -1) /3) + 3;
+			source_id = led_source_id % 3;
+			if (source_id == SRC_SELECTION_1) {
+				if (led_source_id == LED_SRC_ID_1) {
+					 ssdk_dess_led_source_select(led_num,
+						LAN0_1000_LNK_ACTIVITY);
+				}
+				if (led_source_id == LED_SRC_ID_4) {
+					 ssdk_dess_led_source_select(led_num,
+					 	LAN1_1000_LNK_ACTIVITY);
+				}
+				if (led_source_id == LED_SRC_ID_7) {
+					 ssdk_dess_led_source_select(led_num,
+					 	LAN2_1000_LNK_ACTIVITY);
+				}
+				if (led_source_id == LED_SRC_ID_10) {
+					ssdk_dess_led_source_select(led_num,
+						LAN3_1000_LNK_ACTIVITY);
+				}
+				if (led_source_id == LED_SRC_ID_13) {
+					ssdk_dess_led_source_select(led_num,
+						WAN_1000_LNK_ACTIVITY);
+				}
+			}
+			if (source_id == SRC_SELECTION_2) {
+				if (led_source_id == LED_SRC_ID_2) {
+					ssdk_dess_led_source_select(led_num,
+						LAN0_100_LNK_ACTIVITY);
+				}
+				if (led_source_id == LED_SRC_ID_5) {
+					ssdk_dess_led_source_select(led_num,
+						LAN1_100_LNK_ACTIVITY);
+				}
+				if (led_source_id == LED_SRC_ID_8) {
+					ssdk_dess_led_source_select(led_num,
+						LAN2_100_LNK_ACTIVITY);
+				}
+				if (led_source_id == LED_SRC_ID_11) {
+					ssdk_dess_led_source_select(led_num,
+						LAN3_100_LNK_ACTIVITY);
+				}
+				if (led_source_id == LED_SRC_ID_14) {
+					ssdk_dess_led_source_select(led_num,
+						WAN_100_LNK_ACTIVITY);
+				}
+			}
+			if (source_id == SRC_SELECTION_0) {
+				if (led_source_id == LED_SRC_ID_3) {
+					ssdk_dess_led_source_select(led_num,
+						LAN0_10_LNK_ACTIVITY);
+				}
+				if (led_source_id == LED_SRC_ID_6) {
+					ssdk_dess_led_source_select(led_num,
+						LAN1_10_LNK_ACTIVITY);
+				}
+				if (led_source_id == LED_SRC_ID_9) {
+					ssdk_dess_led_source_select(led_num,
+						LAN2_10_LNK_ACTIVITY);
+				}
+				if (led_source_id == LED_SRC_ID_12) {
+					ssdk_dess_led_source_select(led_num,
+						LAN3_10_LNK_ACTIVITY);
+				}
+				if (led_source_id == LED_SRC_ID_15) {
+					ssdk_dess_led_source_select(led_num,
+						WAN_10_LNK_ACTIVITY);
+				}
+			}
+		}
+	}
+#endif
+	return 0;
+}
+#endif
+
+#ifdef IN_LED
+sw_error_t ssdk_led_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+	a_uint32_t src_index = 0, led_src_id = 0;
+	sw_error_t rv = SW_OK;
+	led_ctrl_pattern_t pattern = {0};
+
+	for(src_index = 0; src_index < cfg->led_source_num; src_index++)
+	{
+		pattern.mode = cfg->led_source_cfg[src_index].led_pattern.mode;
+		pattern.map = cfg->led_source_cfg[src_index].led_pattern.map;
+		led_src_id = cfg->led_source_cfg[src_index].led_source_id;
+		SSDK_INFO("ssdk_led_mode:%x, ssdk_led_map:%x, ssdk_led_src_id:%x\n",
+			pattern.mode, pattern.map, led_src_id);
+		rv = fal_led_source_pattern_set(dev_id, led_src_id, &pattern);
+		SW_RTN_ON_ERROR(rv);
+	}
+
+	return SW_OK;
+}
+#endif
diff --git a/qca-ssdk/src/init/ssdk_mp.c b/qca-ssdk/src/init/ssdk_mp.c
new file mode 100644
index 0000000..d28670a
--- /dev/null
+++ b/qca-ssdk/src/init/ssdk_mp.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "ssdk_init.h"
+#include "ssdk_plat.h"
+#include "ssdk_dts.h"
+#include "ssdk_mp.h"
+#include "adpt.h"
+#include "ssdk_led.h"
+#include "ssdk_clk.h"
+
+#ifdef IN_PORTCONTROL
+sw_error_t
+qca_mp_portctrl_hw_init(a_uint32_t dev_id)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t i = 0;
+	fal_port_eee_cfg_t port_eee_cfg;
+	a_bool_t force_port;
+
+	memset(&port_eee_cfg, 0, sizeof(fal_port_eee_cfg_t));
+
+	for (i = SSDK_PHYSICAL_PORT1; i <= SSDK_PHYSICAL_PORT2; i++) {
+		force_port = ssdk_port_feature_get(dev_id, i,
+			PHY_F_FORCE);
+		if (force_port == A_FALSE) {
+			fal_port_txmac_status_set (dev_id, i, A_FALSE);
+			fal_port_rxmac_status_set (dev_id, i, A_FALSE);
+			/* init mac's lpi wake up timer to 70us */
+			port_eee_cfg.lpi_wakeup_timer = MP_LPI_WAKEUP_TIMER;
+			fal_port_interface_eee_cfg_set(dev_id, i, &port_eee_cfg);
+		} else {
+			fal_port_txmac_status_set (dev_id, i, A_TRUE);
+			fal_port_rxmac_status_set (dev_id, i, A_TRUE);
+		}
+		fal_port_rxfc_status_set(dev_id, i, A_FALSE);
+		fal_port_txfc_status_set(dev_id, i, A_FALSE);
+		fal_port_max_frame_size_set(dev_id, i,
+			FAL_DEFAULT_MAX_FRAME_SIZE);
+		fal_port_promisc_mode_set(dev_id, i, A_TRUE);
+		/* init software level port status */
+		qca_mac_port_status_init(dev_id, i);
+		/*enable ICC efuse loading*/
+		ssdk_mp_gephy_icc_efuse_load_enable(A_TRUE);
+	}
+	return rv;
+}
+#endif
+sw_error_t
+qca_mp_interface_mode_init(a_uint32_t dev_id)
+{
+	sw_error_t rv = SW_OK;
+	adpt_api_t *p_api;
+	a_uint32_t i = 0, mode = 0;
+	a_bool_t force_port;
+	a_uint32_t force_speed = 0;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id));
+	SW_RTN_ON_NULL(p_api->adpt_uniphy_mode_set);
+	SW_RTN_ON_NULL(p_api->adpt_port_mac_speed_set);
+	SW_RTN_ON_NULL(p_api->adpt_port_mac_duplex_set);
+
+	mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0);
+
+	rv = p_api->adpt_uniphy_mode_set(dev_id, SSDK_UNIPHY_INSTANCE0,
+				mode);
+	SW_RTN_ON_ERROR(rv);
+
+	for (i = SSDK_PHYSICAL_PORT1; i <= SSDK_PHYSICAL_PORT2; i++) {
+		force_port = ssdk_port_feature_get(dev_id, i, PHY_F_FORCE);
+		if (force_port == A_TRUE) {
+			force_speed = ssdk_port_force_speed_get(dev_id, i);
+			rv = p_api->adpt_port_mac_speed_set(dev_id,
+				i, force_speed);
+		} else {
+			rv = p_api->adpt_port_mac_speed_set(dev_id,
+				i, FAL_SPEED_1000);
+		}
+		SW_RTN_ON_ERROR(rv);
+		rv = p_api->adpt_port_mac_duplex_set(dev_id, i, FAL_FULL_DUPLEX);
+		SW_RTN_ON_ERROR(rv);
+	}
+
+	return rv;
+}
+
+sw_error_t
+qca_mp_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+	sw_error_t rv = SW_OK;
+
+#ifdef IN_PORTCONTROL
+	rv = qca_mp_portctrl_hw_init(dev_id);
+	SW_RTN_ON_ERROR(rv);
+#endif
+#ifdef IN_MIB
+	rv = fal_mib_cpukeep_set(dev_id, A_FALSE);
+	SW_RTN_ON_ERROR(rv);
+#endif
+	rv = qca_mp_interface_mode_init(dev_id);
+	SW_RTN_ON_ERROR(rv)
+#ifdef IN_LED
+	/*init MP led*/
+	rv = ssdk_led_init(dev_id, cfg);
+#endif
+	return rv;
+}
diff --git a/qca-ssdk/src/init/ssdk_phy_i2c.c b/qca-ssdk/src/init/ssdk_phy_i2c.c
new file mode 100755
index 0000000..8d9c5ff
--- /dev/null
+++ b/qca-ssdk/src/init/ssdk_phy_i2c.c
@@ -0,0 +1,462 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+/*qca808x_start*/
+#include "sw.h"
+#include "ssdk_phy_i2c.h"
+#include <linux/i2c.h>
+#include "ssdk_init.h"
+#include "ssdk_plat.h"
+
+#define I2C_RW_LIMIT           8
+#define I2C_ADAPTER_DEFAULT_ID 0
+
+/******************************************************************************
+*
+* _qca_i2c_read - read data per i2c bus
+*
+* read data per i2c bus
+*/
+static inline a_int16_t
+_qca_i2c_read(a_uint32_t i2c_bus_id, a_uint32_t i2c_slave,
+		a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count)
+{
+	a_int16_t ret, i;
+	struct i2c_adapter *adapt;
+	a_uint8_t addrbuf[2];
+	struct i2c_msg msg[2];
+
+	ret =0;
+	i = 0;
+
+	if (data_addr & 0xff00) {
+		addrbuf[i++] = (data_addr >> 8) & 0xff;
+	}
+
+	addrbuf[i++] = data_addr & 0xff;
+
+	if (count > I2C_RW_LIMIT) {
+		count = I2C_RW_LIMIT;
+	}
+
+	/*
+	 * msg for configuring the address
+	 */
+	aos_mem_set(msg, 0, sizeof(msg));
+	msg[0].addr = i2c_slave;
+	msg[0].len = i;
+	msg[0].buf = addrbuf;
+
+	/*
+	 * msg for acquiring data
+	 */
+	msg[1].addr = i2c_slave;
+	msg[1].flags = I2C_M_RD;
+	msg[1].len = count;
+	msg[1].buf = buf;
+
+	adapt = i2c_get_adapter(i2c_bus_id);
+	if (adapt) {
+		ret = i2c_transfer(adapt, msg, ARRAY_SIZE(msg));
+		i2c_put_adapter(adapt);
+	}
+
+	if (ret == ARRAY_SIZE(msg)) {
+		return count;
+	}
+
+	return ret;
+}
+
+/******************************************************************************
+*
+* qca_i2c_data_get - wrapper of reading data per i2c bus
+*
+* wrapper of reading data per i2c bus
+*/
+sw_error_t
+qca_i2c_data_get(a_uint32_t dev_id, a_uint32_t i2c_slave,
+		a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count)
+{
+	a_int16_t ret = 0, cur = 0;
+	a_uint16_t cnt = count;
+
+	while (cnt) {
+		cur = _qca_i2c_read(I2C_ADAPTER_DEFAULT_ID,
+				i2c_slave, data_addr, buf, cnt);
+
+		/* No such i2c_slave device */
+		if (cur == -ENXIO) {
+			return SW_NO_RESOURCE;
+		}
+
+		if (cur <= 0) {
+			break;
+		}
+		/*
+		 * loop to acquire the data from the new
+		 * address based on the returned count.
+		 */
+		cnt -= cur;
+		buf += cur;
+		data_addr += cur;
+		ret += cur;
+	}
+
+	if (ret != count) {
+		return SW_FAIL;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* _qca_i2c_write - write data per i2c bus
+*
+* write data per i2c bus
+*/
+static inline a_int16_t
+_qca_i2c_write(a_uint32_t i2c_bus_id, a_uint32_t i2c_slave,
+		a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count)
+{
+	a_int16_t ret, i;
+	struct i2c_adapter *adapt;
+	struct i2c_msg msg;
+	a_uint8_t i2c_wbuf[I2C_RW_LIMIT+2];
+
+	ret = 0;
+	i = 0;
+
+	if (data_addr & 0xff00) {
+		i2c_wbuf[i++] = (data_addr >> 8) & 0xff;
+	}
+
+	/*
+	 * the write buffer is for saving address
+	 * and the data to sent.
+	 */
+	i2c_wbuf[i++] = data_addr & 0xff;
+
+	if (count > I2C_RW_LIMIT) {
+		count = I2C_RW_LIMIT;
+	}
+	memcpy(&i2c_wbuf[i], buf, count);
+
+	aos_mem_set(&msg, 0, sizeof(msg));
+	msg.addr = i2c_slave;
+	msg.len = i + count;
+	msg.buf = i2c_wbuf;
+
+	adapt = i2c_get_adapter(i2c_bus_id);
+	if (adapt) {
+		ret = i2c_transfer(adapt, &msg, 1);
+		i2c_put_adapter(adapt);
+	}
+
+	if (ret == 1) {
+		return count;
+	}
+
+	return ret;
+}
+
+/******************************************************************************
+*
+* qca_i2c_data_set - wrapper of writting data per i2c bus
+*
+* wrapper of writting data per i2c bus
+*/
+sw_error_t
+qca_i2c_data_set(a_uint32_t dev_id, a_uint32_t i2c_slave,
+		a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count)
+{
+	a_int16_t ret = 0, cur = 0;
+	a_uint16_t cnt = count;
+
+	while (cnt) {
+		cur = _qca_i2c_write(I2C_ADAPTER_DEFAULT_ID,
+				i2c_slave, data_addr, buf, cnt);
+
+		/* No such i2c_slave device */
+		if (cur == -ENXIO) {
+			return SW_NO_RESOURCE;
+		}
+
+		if (cur <= 0) {
+			break;
+		}
+		/*
+		 * loop to write the data to the new
+		 * address based on the returned count.
+		 */
+		cnt -= cur;
+		buf += cur;
+		data_addr += cur;
+		ret += cur;
+	}
+
+	if (ret != count) {
+		return SW_FAIL;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* _qca_phy_i2c_mii_read - mii register i2c read
+*
+* mii register i2c read
+*/
+sw_error_t
+qca_phy_i2c_mii_read(a_uint32_t dev_id, a_uint32_t phy_addr,
+                          a_uint32_t reg_addr, a_uint16_t *reg_data)
+{
+	sw_error_t ret;
+	a_uint8_t rx[2] = { 0 };
+
+	reg_addr &= 0xff;
+
+	ret = qca_i2c_data_get(dev_id, phy_addr,
+			reg_addr, rx, sizeof(rx));
+
+	if (ret == SW_OK) {
+		*reg_data = (rx[0] << 8) | rx[1];
+	} else {
+		*reg_data = 0xffff;
+	}
+
+	return ret;
+}
+
+/******************************************************************************
+*
+* _qca_phy_i2c_mii_write - mii register i2c write
+*
+* mii register i2c write
+*/
+sw_error_t
+qca_phy_i2c_mii_write(a_uint32_t dev_id, a_uint32_t phy_addr,
+                           a_uint32_t reg_addr, a_uint16_t reg_data)
+{
+	sw_error_t ret;
+	a_uint8_t tx[2] = {(reg_data >> 8) & 0xff, reg_data & 0xff};
+
+	reg_addr &= 0xff;
+
+	ret = qca_i2c_data_set(dev_id, phy_addr,
+			reg_addr, tx, sizeof(tx));
+
+	return ret;
+}
+
+#ifdef IN_PHY_I2C_MODE
+/******************************************************************************
+*
+* _qca_phy_i2c_mmd_read - mmd register i2c read
+*
+* mmd register i2c read
+*/
+sw_error_t
+qca_phy_i2c_mmd_read(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint16_t mmd_num,
+                            a_uint32_t reg_addr, a_uint16_t *reg_data)
+{
+	a_uint8_t ret;
+	struct i2c_adapter *adapt;
+	/*
+		TX buffer to send:
+		1st byte: Bit[6](1:MMD 0:MII) Bit[5](1:MMD address 0:MMD data) Bit[4:0](MMD num)
+		2nd byte is high 8bits of reg addr
+		3rd byte is low 8bits of reg addr
+		4th byte: add one extra byte at the end of address writing msg to avoid qca808x
+                          treat it as data writing operation
+	*/
+	a_uint8_t tx[4] = { ((QCA_PHY_I2C_IS_MMD << QCA_PHY_I2C_MMD_OR_MII_SHIFT) |
+		(QCA_PHY_I2C_MMD_IS_ADDR << QCA_PHY_I2C_MMD_ADDR_OR_DATA_SHIFT) | mmd_num),
+		(reg_addr >> 8) & 0xff, reg_addr & 0xff, 0 };
+	/*
+		RX buffer to receive:
+		1st byte is high 8bits of reg data
+		2nd byte is low 8bits of reg data
+	*/
+	a_uint8_t rx[2] = { 0 };
+	struct i2c_msg msg[] = {
+		{ .addr = phy_addr, .flags = 0,
+		  .buf = tx, .len = sizeof(tx) },
+		{ .addr = phy_addr, .flags = I2C_M_RD,
+		  .buf = rx, .len = sizeof(rx) } };
+
+	if((mmd_num != QCA_PHY_MMD1_NUM) && (mmd_num != QCA_PHY_MMD3_NUM) &&
+		(mmd_num != QCA_PHY_MMD7_NUM)) {
+		SSDK_ERROR("wrong MMD number:[%d]\n", mmd_num);
+		return SW_FAIL;
+	}
+
+	adapt = i2c_get_adapter(I2C_ADAPTER_DEFAULT_ID);
+	if (!adapt) {
+		return SW_FAIL;
+	}
+
+	ret = i2c_transfer(adapt, msg, ARRAY_SIZE(msg));
+	*reg_data = (rx[0] << 8) | rx[1];
+
+	i2c_put_adapter(adapt);
+
+	if (ret != ARRAY_SIZE(msg)) {
+		return SW_FAIL;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* _qca_phy_i2c_mmd_write - mmd register i2c write
+*
+* mmd register i2c write
+*/
+sw_error_t
+qca_phy_i2c_mmd_write(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint16_t mmd_num,
+                            a_uint32_t reg_addr, a_uint16_t reg_data)
+{
+	a_uint8_t ret;
+	struct i2c_adapter *adapt;
+	/*
+		First TX buffer to send:
+		1st byte: Bit[6](1:MMD 0:MII) Bit[5](1:MMD address 0:MMD data) Bit[4:0](MMD num)
+		2nd byte is high 8bits of reg addr
+		3rd byte is low 8bits of reg addr
+		4th byte: add one extra byte at the end of address writing msg to avoid qca808x
+                          treat it as data writing operation
+	*/
+	a_uint8_t tx[4] = { ((QCA_PHY_I2C_IS_MMD << QCA_PHY_I2C_MMD_OR_MII_SHIFT) |
+		(QCA_PHY_I2C_MMD_IS_ADDR << QCA_PHY_I2C_MMD_ADDR_OR_DATA_SHIFT) | mmd_num),
+		(reg_addr >> 8) & 0xff, reg_addr & 0xff, 0 };
+
+	/*
+		Second TX buffer to send:
+		1st byte: Bit[6](1:MMD 0:MII) Bit[5](1:MMD address 0:MMD data) Bit[4:0](MMD num)
+		2nd byte is high 8bits of reg data
+		3rd byte is low 8bits of reg data
+	*/
+	a_uint8_t tx2[3] = { ((QCA_PHY_I2C_IS_MMD << QCA_PHY_I2C_MMD_OR_MII_SHIFT) |
+		(QCA_PHY_I2C_MMD_IS_DATA << QCA_PHY_I2C_MMD_ADDR_OR_DATA_SHIFT) | mmd_num),
+		(reg_data >> 8) & 0xff, reg_data & 0xff };
+
+	struct i2c_msg msg[] = {
+		{ .addr = phy_addr, .flags = 0,
+		  .buf = tx, .len = sizeof(tx) },
+		{ .addr = phy_addr, .flags = 0,
+		  .buf = tx2, .len = sizeof(tx2) } };
+
+	if((mmd_num != QCA_PHY_MMD1_NUM) && (mmd_num != QCA_PHY_MMD3_NUM) &&
+		(mmd_num != QCA_PHY_MMD7_NUM)) {
+		SSDK_ERROR("wrong MMD number:[%d]\n", mmd_num);
+		return SW_FAIL;
+	}
+
+	adapt = i2c_get_adapter(I2C_ADAPTER_DEFAULT_ID);
+	if (!adapt) {
+		return SW_FAIL;
+	}
+
+	ret = i2c_transfer(adapt, msg, ARRAY_SIZE(msg));
+
+	i2c_put_adapter(adapt);
+
+	if (ret != ARRAY_SIZE(msg)) {
+		return SW_FAIL;
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca_phy_is_i2c_addr -  check if phy addr is i2c addr
+*
+* check if phy addr is i2c addr
+*/
+a_bool_t
+qca_phy_is_i2c_addr(a_uint32_t phy_addr)
+{
+	if(((phy_addr & QCA_PHY_I2C_DEVADDR_MASK) ==
+					QCA_PHY_I2C_PHYCORE_DEVADDR) ||
+		((phy_addr & QCA_PHY_I2C_DEVADDR_MASK) ==
+					QCA_PHY_I2C_SERDES_DEVADDR)) {
+		return A_TRUE;
+	} else {
+		return A_FALSE;
+	}
+}
+
+/******************************************************************************
+*
+* qca_phy_i2c_read -  PHY register i2c read
+*
+* PHY register i2c read
+*/
+sw_error_t
+qca_phy_i2c_read(a_uint32_t dev_id, a_uint32_t phy_addr,
+                           a_uint32_t reg_addr_c45, a_uint16_t *reg_data)
+{
+	a_uint32_t mmd_num = QCA_PHY_MII_ADDR_C45_MMD_NUM(reg_addr_c45);
+	a_uint32_t reg_addr = QCA_PHY_MII_ADDR_C45_REG_ADDR(reg_addr_c45);
+
+	if(qca_phy_is_i2c_addr(phy_addr) == A_FALSE) {
+		return SW_BAD_PARAM;
+	}
+
+	if(QCA_PHY_MII_ADDR_C45_IS_MMD(reg_addr_c45)) {
+		qca_phy_i2c_mmd_read(dev_id, phy_addr, mmd_num, reg_addr, reg_data);
+
+	} else {
+		qca_phy_i2c_mii_read(dev_id, phy_addr, reg_addr, reg_data);
+	}
+
+	return SW_OK;
+}
+
+/******************************************************************************
+*
+* qca_phy_i2c_write -  PHY register i2c write
+*
+* PHY register i2c write
+*/
+sw_error_t
+qca_phy_i2c_write(a_uint32_t dev_id, a_uint32_t phy_addr,
+                            a_uint32_t reg_addr_c45, a_uint16_t reg_data)
+{
+	a_uint32_t mmd_num = QCA_PHY_MII_ADDR_C45_MMD_NUM(reg_addr_c45);
+	a_uint32_t reg_addr = QCA_PHY_MII_ADDR_C45_REG_ADDR(reg_addr_c45);
+
+	if(qca_phy_is_i2c_addr(phy_addr) == A_FALSE) {
+		return SW_BAD_PARAM;
+	}
+
+	if(QCA_PHY_MII_ADDR_C45_IS_MMD(reg_addr_c45)) {
+		qca_phy_i2c_mmd_write(dev_id, phy_addr, mmd_num, reg_addr, reg_data);
+
+	} else {
+		qca_phy_i2c_mii_write(dev_id, phy_addr, reg_addr, reg_data);
+	}
+
+	return SW_OK;
+}
+/*qca808x_end*/
+EXPORT_SYMBOL(qca_phy_i2c_read);
+EXPORT_SYMBOL(qca_phy_i2c_write);
+/*qca808x_start*/
+#endif
+/*qca808x_start*/
diff --git a/qca-ssdk/src/init/ssdk_plat.c b/qca-ssdk/src/init/ssdk_plat.c
new file mode 100755
index 0000000..1bb8482
--- /dev/null
+++ b/qca-ssdk/src/init/ssdk_plat.c
@@ -0,0 +1,1417 @@
+/*
+ * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+/*qca808x_start*/
+#include "sw.h"
+#include "ssdk_init.h"
+#include "fal_init.h"
+#include "fal.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "ssdk_init.h"
+/*qca808x_end*/
+#include "ssdk_dts.h"
+#if (defined(HPPE) || defined(MP))
+#include "hppe_init.h"
+#endif
+#include <linux/kconfig.h>
+/*qca808x_start*/
+#include <linux/version.h>
+/*qca808x_end*/
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+//#include <asm/mach-types.h>
+#include <generated/autoconf.h>
+#include <linux/if_arp.h>
+#include <linux/inetdevice.h>
+#include <linux/netdevice.h>
+#include <linux/phy.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+
+#if defined(ISIS) ||defined(ISISC) ||defined(GARUDA)
+#include <f1_phy.h>
+#endif
+#if defined(ATHENA) ||defined(SHIVA) ||defined(HORUS)
+#include <f2_phy.h>
+#endif
+#ifdef IN_MALIBU_PHY
+#include <malibu_phy.h>
+#endif
+/*qca808x_start*/
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0))
+#include <linux/of.h>
+#include <linux/of_mdio.h>
+#include <linux/of_platform.h>
+#elif defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#include <linux/of.h>
+#include <linux/of_mdio.h>
+#include <drivers/leds/leds-ipq40xx.h>
+#include <linux/of_platform.h>
+#include <linux/reset.h>
+#else
+#include <linux/ar8216_platform.h>
+#include <drivers/net/phy/ar8216.h>
+#include <drivers/net/ethernet/atheros/ag71xx/ag71xx.h>
+#endif
+#include "ssdk_plat.h"
+/*qca808x_end*/
+#include "ssdk_clk.h"
+#include "ref_vlan.h"
+#include "ref_fdb.h"
+#include "ref_mib.h"
+#include "ref_port_ctrl.h"
+#include "ref_misc.h"
+#include "ref_uci.h"
+#include "shell.h"
+#ifdef BOARD_AR71XX
+#include "ssdk_uci.h"
+#endif
+
+#include "hsl_phy.h"
+#ifdef IN_LINUX_STD_PTP
+#include "qca808x_ptp.h"
+#endif
+
+#ifdef IN_IP
+#if defined (CONFIG_NF_FLOW_COOKIE)
+#include "fal_flowcookie.h"
+#ifdef IN_SFE
+#include <shortcut-fe/sfe.h>
+#endif
+#endif
+#endif
+
+#ifdef IN_RFS
+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+#include <linux/if_vlan.h>
+#endif
+#include <qca-rfs/rfs_dev.h>
+#ifdef IN_IP
+#include "fal_rfs.h"
+#endif
+#endif
+
+#include "adpt.h"
+/*qca808x_start*/
+
+extern struct qca_phy_priv **qca_phy_priv_global;
+extern ssdk_chip_type SSDK_CURRENT_CHIP_TYPE;
+/*qca808x_end*/
+struct mutex switch_mdio_lock;
+
+#ifdef BOARD_IPQ806X
+#define PLATFORM_MDIO_BUS_NAME		"mdio-gpio"
+#endif
+
+#ifdef BOARD_AR71XX
+#define PLATFORM_MDIO_BUS_NAME		"ag71xx-mdio"
+#endif
+/*qca808x_start*/
+#define MDIO_BUS_0					0
+#define MDIO_BUS_1					1
+/*qca808x_end*/
+#define PLATFORM_MDIO_BUS_NUM		MDIO_BUS_0
+
+#define ISIS_CHIP_ID 0x18
+#define ISIS_CHIP_REG 0
+#define SHIVA_CHIP_ID 0x1f
+#define SHIVA_CHIP_REG 0x10
+#define HIGH_ADDR_DFLT	0x200
+
+/*
+ * Using ISIS's address as default
+  */
+static int switch_chip_id = ISIS_CHIP_ID;
+static int switch_chip_reg = ISIS_CHIP_REG;
+
+static int ssdk_dev_id = 0;
+/*qca808x_start*/
+a_uint32_t ssdk_log_level = SSDK_LOG_LEVEL_DEFAULT;
+/*qca808x_end*/
+
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+struct ag71xx_mdio {
+	struct mii_bus		*mii_bus;
+	int			mii_irq[PHY_MAX_ADDR];
+	void __iomem		*mdio_base;
+};
+#endif
+
+#ifdef BOARD_AR71XX
+static uint32_t switch_chip_id_adjuest(a_uint32_t dev_id)
+{
+	uint32_t chip_version = 0;
+	chip_version = (qca_ar8216_mii_read(dev_id, 0)&0xff00)>>8;
+	if((chip_version !=0) && (chip_version !=0xff))
+		return 0;
+
+	switch_chip_id = SHIVA_CHIP_ID;
+	switch_chip_reg = SHIVA_CHIP_REG;
+
+	chip_version = (qca_ar8216_mii_read(dev_id, 0)&0xff00)>>8;
+	printk("chip_version:0x%x\n", chip_version);
+	return 1;
+}
+#endif
+
+static inline void
+split_addr(uint32_t regaddr, uint16_t *r1, uint16_t *r2, uint16_t *page)
+{
+	regaddr >>= 1;
+	*r1 = regaddr & 0x1e;
+
+	regaddr >>= 5;
+	*r2 = regaddr & 0x7;
+
+	regaddr >>= 3;
+	*page = regaddr & 0x3ff;
+}
+
+a_uint32_t
+qca_ar8216_mii_read(a_uint32_t dev_id, a_uint32_t reg)
+{
+	struct mii_bus *bus;
+	uint16_t r1, r2, page;
+	uint16_t lo, hi;
+
+	bus = qca_phy_priv_global[dev_id]->miibus;
+
+	split_addr((uint32_t) reg, &r1, &r2, &page);
+	mutex_lock(&switch_mdio_lock);
+	mdiobus_write(bus, switch_chip_id, switch_chip_reg, page);
+	udelay(100);
+	lo = mdiobus_read(bus, 0x10 | r2, r1);
+	hi = mdiobus_read(bus, 0x10 | r2, r1 + 1);
+	mdiobus_write(bus, switch_chip_id, switch_chip_reg, HIGH_ADDR_DFLT);
+	mutex_unlock(&switch_mdio_lock);
+	return (hi << 16) | lo;
+}
+
+void
+qca_ar8216_mii_write(a_uint32_t dev_id, a_uint32_t reg, a_uint32_t val)
+{
+	struct mii_bus *bus;
+	uint16_t r1, r2, r3;
+	uint16_t lo, hi;
+
+	bus = qca_phy_priv_global[dev_id]->miibus;
+
+	split_addr((a_uint32_t) reg, &r1, &r2, &r3);
+	lo = val & 0xffff;
+	hi = (a_uint16_t) (val >> 16);
+
+	mutex_lock(&switch_mdio_lock);
+	mdiobus_write(bus, switch_chip_id, switch_chip_reg, r3);
+	udelay(100);
+	if(SSDK_CURRENT_CHIP_TYPE != CHIP_SHIVA) {
+		mdiobus_write(bus, 0x10 | r2, r1, lo);
+		mdiobus_write(bus, 0x10 | r2, r1 + 1, hi);
+	} else {
+		mdiobus_write(bus, 0x10 | r2, r1 + 1, hi);
+		mdiobus_write(bus, 0x10 | r2, r1, lo);
+	}
+	mdiobus_write(bus, switch_chip_id, switch_chip_reg, HIGH_ADDR_DFLT);
+	mutex_unlock(&switch_mdio_lock);
+}
+
+/*qca808x_start*/
+a_bool_t
+phy_addr_validation_check(a_uint32_t phy_addr)
+{
+
+	if ((phy_addr > SSDK_PHY_BCAST_ID) || (phy_addr < SSDK_PHY_MIN_ID))
+		return A_FALSE;
+	else
+		return A_TRUE;
+}
+
+static struct mii_bus *
+ssdk_phy_miibus_get(a_uint32_t dev_id, a_uint32_t phy_addr)
+{
+	struct mii_bus *bus = NULL;
+/*qca808x_end*/
+#ifndef BOARD_AR71XX
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+	bus = ssdk_dts_miibus_get(dev_id, phy_addr);
+#endif
+#endif
+/*qca808x_start*/
+	if (!bus)
+		bus = qca_phy_priv_global[dev_id]->miibus;
+
+	return bus;
+}
+
+sw_error_t
+qca_ar8327_phy_read(a_uint32_t dev_id, a_uint32_t phy_addr,
+                           a_uint32_t reg, a_uint16_t* data)
+{
+	struct mii_bus *bus = NULL;
+
+	if (A_TRUE != phy_addr_validation_check (phy_addr))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	bus = ssdk_phy_miibus_get(dev_id, phy_addr);
+	if (!bus)
+		return SW_NOT_SUPPORTED;
+
+	*data = mdiobus_read(bus, phy_addr, reg);
+	return 0;
+}
+
+sw_error_t
+qca_ar8327_phy_write(a_uint32_t dev_id, a_uint32_t phy_addr,
+                            a_uint32_t reg, a_uint16_t data)
+{
+	struct mii_bus *bus = NULL;
+
+	if (A_TRUE != phy_addr_validation_check (phy_addr))
+	{
+		return SW_BAD_PARAM;
+	}
+
+	bus = ssdk_phy_miibus_get(dev_id, phy_addr);
+	if (!bus)
+		return SW_NOT_SUPPORTED;
+
+	mdiobus_write(bus, phy_addr, reg, data);
+	return 0;
+}
+
+void
+qca_ar8327_phy_dbg_write(a_uint32_t dev_id, a_uint32_t phy_addr,
+                                a_uint16_t dbg_addr, a_uint16_t dbg_data)
+{
+	struct mii_bus *bus = NULL;
+
+	if (A_TRUE != phy_addr_validation_check (phy_addr))
+	{
+		return;
+	}
+
+	bus = ssdk_phy_miibus_get(dev_id, phy_addr);
+	if (!bus)
+		return;
+
+	mdiobus_write(bus, phy_addr, QCA_MII_DBG_ADDR, dbg_addr);
+	mdiobus_write(bus, phy_addr, QCA_MII_DBG_DATA, dbg_data);
+}
+
+void
+qca_ar8327_phy_dbg_read(a_uint32_t dev_id, a_uint32_t phy_addr,
+		                a_uint16_t dbg_addr, a_uint16_t *dbg_data)
+{
+	struct mii_bus *bus = NULL;
+
+	if (A_TRUE != phy_addr_validation_check (phy_addr))
+	{
+		return;
+	}
+
+	bus = ssdk_phy_miibus_get(dev_id, phy_addr);
+	if (!bus)
+		return;
+
+	mdiobus_write(bus, phy_addr, QCA_MII_DBG_ADDR, dbg_addr);
+	*dbg_data = mdiobus_read(bus, phy_addr, QCA_MII_DBG_DATA);
+}
+
+
+void
+qca_ar8327_mmd_write(a_uint32_t dev_id, a_uint32_t phy_addr,
+                          a_uint16_t addr, a_uint16_t data)
+{
+	struct mii_bus *bus = NULL;
+
+	if (A_TRUE != phy_addr_validation_check (phy_addr))
+	{
+		return;
+	}
+
+	bus = ssdk_phy_miibus_get(dev_id, phy_addr);
+	if (!bus)
+		return;
+
+	mdiobus_write(bus, phy_addr, QCA_MII_MMD_ADDR, addr);
+	mdiobus_write(bus, phy_addr, QCA_MII_MMD_DATA, data);
+}
+
+void qca_phy_mmd_write(u32 dev_id, u32 phy_id,
+                     u16 mmd_num, u16 reg_id, u16 reg_val)
+{
+	qca_ar8327_phy_write(dev_id, phy_id,
+			QCA_MII_MMD_ADDR, mmd_num);
+	qca_ar8327_phy_write(dev_id, phy_id,
+			QCA_MII_MMD_DATA, reg_id);
+	qca_ar8327_phy_write(dev_id, phy_id,
+			QCA_MII_MMD_ADDR,
+			0x4000 | mmd_num);
+	qca_ar8327_phy_write(dev_id, phy_id,
+		QCA_MII_MMD_DATA, reg_val);
+}
+
+u16 qca_phy_mmd_read(u32 dev_id, u32 phy_id,
+		u16 mmd_num, u16 reg_id)
+{
+	u16 value = 0;
+	qca_ar8327_phy_write(dev_id, phy_id,
+			QCA_MII_MMD_ADDR, mmd_num);
+	qca_ar8327_phy_write(dev_id, phy_id,
+			QCA_MII_MMD_DATA, reg_id);
+	qca_ar8327_phy_write(dev_id, phy_id,
+			QCA_MII_MMD_ADDR,
+			0x4000 | mmd_num);
+	qca_ar8327_phy_read(dev_id, phy_id,
+			QCA_MII_MMD_DATA, &value);
+	return value;
+}
+/*qca808x_end*/
+sw_error_t
+qca_switch_reg_read(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len)
+{
+	uint32_t reg_val = 0;
+
+	if (len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+	if ((reg_addr%4)!= 0)
+	return SW_BAD_PARAM;
+
+	reg_val = readl(qca_phy_priv_global[dev_id]->hw_addr + reg_addr);
+
+	aos_mem_copy(reg_data, &reg_val, sizeof (a_uint32_t));
+	return 0;
+}
+
+sw_error_t
+qca_switch_reg_write(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len)
+{
+	uint32_t reg_val = 0;
+	if (len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+	if ((reg_addr%4)!= 0)
+	return SW_BAD_PARAM;
+
+	aos_mem_copy(&reg_val, reg_data, sizeof (a_uint32_t));
+	writel(reg_val, qca_phy_priv_global[dev_id]->hw_addr + reg_addr);
+	return 0;
+}
+
+sw_error_t
+qca_psgmii_reg_read(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len)
+{
+#ifdef DESS
+	uint32_t reg_val = 0;
+
+	if (len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+	if((reg_addr%4)!=0)
+	return SW_BAD_PARAM;
+
+	if (qca_phy_priv_global[dev_id]->psgmii_hw_addr == NULL)
+		return SW_NOT_SUPPORTED;
+
+	reg_val = readl(qca_phy_priv_global[dev_id]->psgmii_hw_addr + reg_addr);
+
+	aos_mem_copy(reg_data, &reg_val, sizeof (a_uint32_t));
+#endif
+	return 0;
+}
+
+sw_error_t
+qca_psgmii_reg_write(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len)
+{
+#ifdef DESS
+	uint32_t reg_val = 0;
+	if (len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+	if((reg_addr%4)!=0)
+	return SW_BAD_PARAM;
+
+	if (qca_phy_priv_global[dev_id]->psgmii_hw_addr == NULL)
+		return SW_NOT_SUPPORTED;
+
+	aos_mem_copy(&reg_val, reg_data, sizeof (a_uint32_t));
+	writel(reg_val, qca_phy_priv_global[dev_id]->psgmii_hw_addr + reg_addr);
+#endif
+	return 0;
+}
+
+sw_error_t
+qca_uniphy_reg_read(a_uint32_t dev_id, a_uint32_t uniphy_index,
+				a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len)
+{
+#if (defined(HPPE) || defined(MP))
+	uint32_t reg_val = 0;
+	void __iomem *hppe_uniphy_base = NULL;
+	a_uint32_t reg_addr1, reg_addr2;
+
+	if (len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+	if (SSDK_UNIPHY_INSTANCE0 == uniphy_index)
+		hppe_uniphy_base = qca_phy_priv_global[dev_id]->uniphy_hw_addr;
+	else if (SSDK_UNIPHY_INSTANCE1 == uniphy_index)
+		hppe_uniphy_base = qca_phy_priv_global[dev_id]->uniphy_hw_addr + HPPE_UNIPHY_BASE1;
+
+	else if (SSDK_UNIPHY_INSTANCE2 == uniphy_index)
+		hppe_uniphy_base = qca_phy_priv_global[dev_id]->uniphy_hw_addr + HPPE_UNIPHY_BASE2;
+	else
+		return SW_BAD_PARAM;
+
+	if ( reg_addr > HPPE_UNIPHY_MAX_DIRECT_ACCESS_REG)
+	{
+		// uniphy reg indireclty access
+		reg_addr1 = (reg_addr & 0xffffff) >> 8;
+		writel(reg_addr1, hppe_uniphy_base + HPPE_UNIPHY_INDIRECT_REG_ADDR);
+
+		reg_addr2 = reg_addr & HPPE_UNIPHY_INDIRECT_LOW_ADDR;
+		reg_addr = (HPPE_UNIPHY_INDIRECT_DATA << 10) | (reg_addr2 << 2);
+
+		reg_val = readl(hppe_uniphy_base + reg_addr);
+		aos_mem_copy(reg_data, &reg_val, sizeof (a_uint32_t));
+	}
+	else
+	{	// uniphy reg directly access
+		reg_val = readl(hppe_uniphy_base + reg_addr);
+		aos_mem_copy(reg_data, &reg_val, sizeof (a_uint32_t));
+	}
+#endif
+	return 0;
+}
+
+sw_error_t
+qca_uniphy_reg_write(a_uint32_t dev_id, a_uint32_t uniphy_index,
+				a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len)
+{
+#if (defined(HPPE) || defined(MP))
+	void __iomem *hppe_uniphy_base = NULL;
+	a_uint32_t reg_addr1, reg_addr2;
+	uint32_t reg_val = 0;
+
+	if (len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+	if (SSDK_UNIPHY_INSTANCE0 == uniphy_index)
+		hppe_uniphy_base = qca_phy_priv_global[dev_id]->uniphy_hw_addr;
+	else if (SSDK_UNIPHY_INSTANCE1 == uniphy_index)
+		hppe_uniphy_base = qca_phy_priv_global[dev_id]->uniphy_hw_addr + HPPE_UNIPHY_BASE1;
+
+	else if (SSDK_UNIPHY_INSTANCE2 == uniphy_index)
+		hppe_uniphy_base = qca_phy_priv_global[dev_id]->uniphy_hw_addr + HPPE_UNIPHY_BASE2;
+	else
+		return SW_BAD_PARAM;
+
+	if ( reg_addr > HPPE_UNIPHY_MAX_DIRECT_ACCESS_REG)
+	{
+		// uniphy reg indireclty access
+		reg_addr1 = (reg_addr & 0xffffff) >> 8;
+		writel(reg_addr1, hppe_uniphy_base + HPPE_UNIPHY_INDIRECT_REG_ADDR);
+
+		reg_addr2 = reg_addr & HPPE_UNIPHY_INDIRECT_LOW_ADDR;
+		reg_addr = (HPPE_UNIPHY_INDIRECT_DATA << 10) | (reg_addr2 << 2);
+		aos_mem_copy(&reg_val, reg_data, sizeof (a_uint32_t));
+		writel(reg_val, hppe_uniphy_base + reg_addr);
+	}
+	else
+	{	// uniphy reg directly access
+		aos_mem_copy(&reg_val, reg_data, sizeof (a_uint32_t));
+		writel(reg_val, hppe_uniphy_base + reg_addr);
+	}
+#endif
+	return 0;
+}
+#ifndef BOARD_AR71XX
+/*qca808x_start*/
+static int miibus_get(a_uint32_t dev_id)
+{
+/*qca808x_end*/
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+/*qca808x_start*/
+	struct device_node *mdio_node = NULL;
+	struct device_node *switch_node = NULL;
+	struct platform_device *mdio_plat = NULL;
+	struct ipq40xx_mdio_data *mdio_data = NULL;
+	struct qca_phy_priv *priv;
+	hsl_reg_mode reg_mode = HSL_REG_LOCAL_BUS;
+	priv = qca_phy_priv_global[dev_id];
+	switch_node = qca_phy_priv_global[dev_id]->of_node;
+	if (switch_node) {
+		mdio_node = of_parse_phandle(switch_node, "mdio-bus", 0);
+		if (mdio_node) {
+			priv->miibus = of_mdio_find_bus(mdio_node);
+			return 0;
+		}
+	}
+/*qca808x_end*/
+	reg_mode=ssdk_switch_reg_access_mode_get(dev_id);
+/*qca808x_start*/
+	if(reg_mode == HSL_REG_LOCAL_BUS)
+		mdio_node = of_find_compatible_node(NULL, NULL, "qcom,ipq40xx-mdio");
+	else
+		mdio_node = of_find_compatible_node(NULL, NULL, "virtual,mdio-gpio");
+
+	if (!mdio_node) {
+		SSDK_ERROR("No MDIO node found in DTS!\n");
+		return 1;
+	}
+
+	mdio_plat = of_find_device_by_node(mdio_node);
+	if (!mdio_plat) {
+		SSDK_ERROR("cannot find platform device from mdio node\n");
+		return 1;
+	}
+
+	if(reg_mode == HSL_REG_LOCAL_BUS)
+	{
+		mdio_data = dev_get_drvdata(&mdio_plat->dev);
+		if (!mdio_data) {
+			SSDK_ERROR("cannot get mdio_data reference from device data\n");
+			return 1;
+		}
+		priv->miibus = mdio_data->mii_bus;
+	}
+	else
+		priv->miibus = dev_get_drvdata(&mdio_plat->dev);
+
+	if (!priv->miibus) {
+		SSDK_ERROR("cannot get mii bus reference from device data\n");
+		return 1;
+	}
+/*qca808x_end*/
+#else
+	struct device *miidev;
+	char busid[MII_BUS_ID_SIZE];
+	struct qca_phy_priv *priv;
+
+	priv = qca_phy_priv_global[dev_id];
+	snprintf(busid, MII_BUS_ID_SIZE, "%s.%d",
+		PLATFORM_MDIO_BUS_NAME, PLATFORM_MDIO_BUS_NUM);
+
+	miidev = bus_find_device_by_name(&platform_bus_type, NULL, busid);
+	if (!miidev) {
+		SSDK_ERROR("Failed to get miidev\n");
+		return 1;
+	}
+
+	priv->miibus = dev_get_drvdata(miidev);
+
+	if(!priv->miibus){
+		SSDK_ERROR("mdio bus '%s' get FAIL\n", busid);
+		return 1;
+	}
+#endif
+/*qca808x_start*/
+	return 0;
+}
+/*qca808x_end*/
+#else
+static int miibus_get(a_uint32_t dev_id)
+{
+	struct ag71xx_mdio *am;
+	struct qca_phy_priv *priv = qca_phy_priv_global[dev_id];
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+	struct device_node *mdio_node = NULL;
+	struct platform_device *mdio_plat = NULL;
+
+	mdio_node = of_find_compatible_node(NULL, NULL, "qca,ag71xx-mdio");
+	if (!mdio_node) {
+		SSDK_ERROR("No MDIO node found in DTS!\n");
+		return 1;
+	}
+	mdio_plat = of_find_device_by_node(mdio_node);
+	if (!mdio_plat) {
+		SSDK_ERROR("cannot find platform device from mdio node\n");
+		return 1;
+	}
+	am = dev_get_drvdata(&mdio_plat->dev);
+	if (!am) {
+                	SSDK_ERROR("cannot get mdio_data reference from device data\n");
+                	return 1;
+	}
+	priv->miibus = am->mii_bus;
+
+	switch_chip_id_adjuest(dev_id);
+#else
+	struct device *miidev;
+	char busid[MII_BUS_ID_SIZE];
+
+	snprintf(busid, MII_BUS_ID_SIZE, "%s.%d",
+		PLATFORM_MDIO_BUS_NAME, PLATFORM_MDIO_BUS_NUM);
+
+	miidev = bus_find_device_by_name(&platform_bus_type, NULL, busid);
+	if (!miidev) {
+		SSDK_ERROR("Failed to get miidev!\n");
+		return 1;
+	}
+	am = dev_get_drvdata(miidev);
+	priv->miibus = am->mii_bus;
+
+	if(switch_chip_id_adjuest(dev_id)) {
+		snprintf(busid, MII_BUS_ID_SIZE, "%s.%d",
+		PLATFORM_MDIO_BUS_NAME, MDIO_BUS_1);
+
+		miidev = bus_find_device_by_name(&platform_bus_type, NULL, busid);
+		if (!miidev) {
+			SSDK_ERROR("Failed get mii bus\n");
+			return 1;
+		}
+
+		am = dev_get_drvdata(miidev);
+		priv->miibus = am->mii_bus;
+		SSDK_INFO("chip_version:0x%x\n", (qca_ar8216_mii_read(dev_id, 0)&0xff00)>>8);
+	}
+
+	if(!miidev){
+		SSDK_ERROR("mdio bus '%s' get FAIL\n", busid);
+		return 1;
+	}
+#endif
+
+	return 0;
+}
+#endif
+
+struct mii_bus *ssdk_miibus_get_by_device(a_uint32_t dev_id)
+{
+	return qca_phy_priv_global[dev_id]->miibus;
+}
+
+static ssize_t ssdk_dev_id_get(struct device *dev,
+		struct device_attribute *attr,
+		char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = (a_uint32_t)ssdk_dev_id;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t ssdk_dev_id_set(struct device *dev,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+	if (count >= sizeof(num_buf)) return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	ssdk_dev_id = num;
+
+	return count;
+}
+
+static ssize_t ssdk_log_level_get(struct device *dev,
+		struct device_attribute *attr,
+		char *buf)
+{
+	ssize_t count;
+	a_uint32_t num;
+
+	num = ssdk_log_level;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num);
+	return count;
+}
+
+static ssize_t ssdk_log_level_set(struct device *dev,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	char num_buf[12];
+	a_uint32_t num;
+
+	if (count >= sizeof(num_buf))
+		return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+	sscanf(num_buf, "%u", &num);
+
+	ssdk_log_level = (a_uint32_t)num;
+
+	return count;
+}
+
+static ssize_t ssdk_packet_counter_get(struct device *dev,
+		struct device_attribute *attr,
+		char *buf)
+{
+	ssize_t count;
+	adpt_api_t *p_api;
+
+	p_api = adpt_api_ptr_get(ssdk_dev_id);
+	if (p_api == NULL || p_api->adpt_debug_counter_get == NULL)
+	{
+		count = snprintf(buf, (ssize_t)PAGE_SIZE, "Unsupported\n");
+		return count;
+	}
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "\n");
+
+	p_api->adpt_debug_counter_get(A_FALSE);
+
+	return count;
+}
+
+static ssize_t ssdk_packet_counter_set(struct device *dev,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	char num_buf[12];
+	adpt_api_t *p_api;
+
+	p_api = adpt_api_ptr_get(ssdk_dev_id);
+	if (p_api == NULL || p_api->adpt_debug_counter_set == NULL) {
+		SSDK_WARN("Unsupported\n");
+		return count;
+	}
+
+	p_api->adpt_debug_counter_set();
+
+	if (count >= sizeof(num_buf))
+		return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+
+
+	return count;
+}
+
+static ssize_t ssdk_byte_counter_get(struct device *dev,
+		struct device_attribute *attr,
+		char *buf)
+{
+	ssize_t count;
+	adpt_api_t *p_api;
+
+	p_api = adpt_api_ptr_get(ssdk_dev_id);
+	if (p_api == NULL || p_api->adpt_debug_counter_get == NULL)
+	{
+		count = snprintf(buf, (ssize_t)PAGE_SIZE, "Unsupported\n");
+		return count;
+	}
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "\n");
+
+	p_api->adpt_debug_counter_get(A_TRUE);
+
+	return count;
+}
+
+static ssize_t ssdk_byte_counter_set(struct device *dev,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	char num_buf[12];
+	adpt_api_t *p_api;
+
+	p_api = adpt_api_ptr_get(ssdk_dev_id);
+	if (p_api == NULL || p_api->adpt_debug_counter_set == NULL) {
+		SSDK_WARN("Unsupported\n");
+		return count;
+	}
+
+	p_api->adpt_debug_counter_set();
+
+	if (count >= sizeof(num_buf))
+		return 0;
+	memcpy(num_buf, buf, count);
+	num_buf[count] = '\0';
+
+
+	return count;
+}
+
+#ifdef HPPE
+#ifdef IN_QOS
+void ssdk_dts_port_scheduler_dump(a_uint32_t dev_id)
+{
+	a_uint32_t i;
+	ssdk_dt_portscheduler_cfg *portscheduler_cfg;
+	ssdk_dt_scheduler_cfg *scheduler_cfg;
+	a_uint8_t srcmsg[7][16];
+
+	scheduler_cfg = ssdk_bootup_shceduler_cfg_get(dev_id);
+
+	printk("===============================port_scheduler_resource===========================\n");
+	printk("portid     ucastq     mcastq     10sp     10cdrr     10edrr     11cdrr     11edrr\n");
+	for (i = 0; i < SSDK_MAX_PORT_NUM; i++)
+	{
+		portscheduler_cfg = &scheduler_cfg->pool[i];
+		snprintf(srcmsg[0], sizeof(srcmsg[0]), "<%d %d>", portscheduler_cfg->ucastq_start,
+				portscheduler_cfg->ucastq_end);
+		snprintf(srcmsg[1], sizeof(srcmsg[1]), "<%d %d>", portscheduler_cfg->mcastq_start,
+				portscheduler_cfg->mcastq_end);
+		snprintf(srcmsg[2], sizeof(srcmsg[2]), "<%d %d>", portscheduler_cfg->l0sp_start,
+				portscheduler_cfg->l0sp_end);
+		snprintf(srcmsg[3], sizeof(srcmsg[3]), "<%d %d>", portscheduler_cfg->l0cdrr_start,
+				portscheduler_cfg->l0cdrr_end);
+		snprintf(srcmsg[4], sizeof(srcmsg[4]), "<%d %d>", portscheduler_cfg->l0edrr_start,
+				portscheduler_cfg->l0edrr_end);
+		snprintf(srcmsg[5], sizeof(srcmsg[5]), "<%d %d>", portscheduler_cfg->l1cdrr_start,
+				portscheduler_cfg->l1cdrr_end);
+		snprintf(srcmsg[6], sizeof(srcmsg[6]), "<%d %d>", portscheduler_cfg->l1edrr_start,
+				portscheduler_cfg->l1edrr_end);
+		printk("%6d%11s%11s%9s%11s%11s%11s%11s\n", i, srcmsg[0], srcmsg[1], srcmsg[2], srcmsg[3],
+				srcmsg[4], srcmsg[5], srcmsg[6]);
+	}
+}
+
+void ssdk_dts_l0scheduler_dump(a_uint32_t dev_id)
+{
+	a_uint32_t i;
+	ssdk_dt_l0scheduler_cfg *scheduler_cfg;
+	ssdk_dt_scheduler_cfg *cfg;
+
+	cfg = ssdk_bootup_shceduler_cfg_get(dev_id);
+	printk("==========================l0scheduler_cfg===========================\n");
+	printk("queue     portid     cpri     cdrr_id     epri     edrr_id     sp_id\n");
+	for (i = 0; i < SSDK_L0SCHEDULER_CFG_MAX; i++)
+	{
+		scheduler_cfg = &cfg->l0cfg[i];
+		if (scheduler_cfg->valid == 1)
+			printk("%5d%11d%9d%12d%9d%12d%10d\n", i, scheduler_cfg->port_id,
+				scheduler_cfg->cpri, scheduler_cfg->cdrr_id, scheduler_cfg->epri,
+				scheduler_cfg->edrr_id, scheduler_cfg->sp_id);
+	}
+}
+
+void ssdk_dts_l1scheduler_dump(a_uint32_t dev_id)
+{
+	a_uint32_t i;
+	ssdk_dt_l1scheduler_cfg *scheduler_cfg;
+	ssdk_dt_scheduler_cfg *cfg;
+
+	cfg = ssdk_bootup_shceduler_cfg_get(dev_id);
+
+	printk("=====================l1scheduler_cfg=====================\n");
+	printk("flow     portid     cpri     cdrr_id     epri     edrr_id\n");
+	for (i = 0; i < SSDK_L1SCHEDULER_CFG_MAX; i++)
+	{
+		scheduler_cfg = &cfg->l1cfg[i];
+		if (scheduler_cfg->valid == 1)
+			printk("%4d%11d%9d%12d%9d%12d\n", i, scheduler_cfg->port_id,
+				scheduler_cfg->cpri, scheduler_cfg->cdrr_id,
+				scheduler_cfg->epri, scheduler_cfg->edrr_id);
+	}
+}
+#endif
+#endif
+static const a_int8_t *qca_phy_feature_str[QCA_PHY_FEATURE_MAX] = {
+	"PHY_CLAUSE45",
+	"PHY_COMBO",
+	"PHY_QGMAC",
+	"PHY_XGMAC",
+	"PHY_I2C",
+	"PHY_INIT",
+	"PHY_FORCE"
+};
+
+void ssdk_dts_phyinfo_dump(a_uint32_t dev_id)
+{
+	a_uint32_t i, j;
+	ssdk_port_phyinfo *port_phyinfo;
+
+	printk("=====================port phyinfo========================\n");
+	printk("portid     phy_addr     features\n");
+
+	for (i = 0; i <= SSDK_MAX_PORT_NUM; i++) {
+		port_phyinfo = ssdk_port_phyinfo_get(dev_id, i);
+		if (port_phyinfo) {
+			printk("%6d%13d%*s", port_phyinfo->port_id,
+					port_phyinfo->phy_addr, 5, "");
+			for (j = 0; j < QCA_PHY_FEATURE_MAX; j++) {
+				if (port_phyinfo->phy_features & BIT(j) && BIT(j) != PHY_F_INIT) {
+					printk(KERN_CONT "%s ", qca_phy_feature_str[j]);
+					if (BIT(j) == PHY_F_FORCE) {
+						printk(KERN_CONT "(speed: %d, duplex: %s) ",
+								port_phyinfo->port_speed,
+								port_phyinfo->port_duplex > 0 ?
+								"full" : "half");
+					}
+				}
+			}
+			printk(KERN_CONT "\n");
+		}
+	}
+}
+
+static ssize_t ssdk_dts_dump(struct device *dev,
+		struct device_attribute *attr,
+		char *buf)
+{
+	ssize_t count;
+	a_uint32_t dev_id, dev_num;
+	ssdk_reg_map_info map;
+	hsl_reg_mode mode;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "\n");
+
+	dev_num = ssdk_switch_device_num_get();
+	for (dev_id = 0; dev_id < dev_num; dev_id ++)
+	{
+		ssdk_switch_reg_map_info_get(dev_id, &map);
+		mode = ssdk_switch_reg_access_mode_get(dev_id);
+		printk("=======================================================\n");
+		printk("ess-switch\n");
+		printk("        reg = <0x%x 0x%x>\n", map.base_addr, map.size);
+		if (mode == HSL_REG_LOCAL_BUS)
+			printk("        switch_access_mode = <local bus>\n");
+		else if (mode == HSL_REG_MDIO)
+			printk("        switch_access_mode = <mdio bus>\n");
+		else
+			printk("        switch_access_mode = <(null)>\n");
+		printk("        switch_cpu_bmp = <0x%x>\n", ssdk_cpu_bmp_get(dev_id));
+		printk("        switch_lan_bmp = <0x%x>\n", ssdk_lan_bmp_get(dev_id));
+		printk("        switch_wan_bmp = <0x%x>\n", ssdk_wan_bmp_get(dev_id));
+		printk("        switch_inner_bmp = <0x%x>\n", ssdk_inner_bmp_get(dev_id));
+		printk("        switch_mac_mode = <0x%x>\n", ssdk_dt_global_get_mac_mode(dev_id, 0));
+		printk("        switch_mac_mode1 = <0x%x>\n", ssdk_dt_global_get_mac_mode(dev_id, 1));
+		printk("        switch_mac_mode2 = <0x%x>\n", ssdk_dt_global_get_mac_mode(dev_id, 2));
+#ifdef IN_BM
+		printk("        bm_tick_mode = <0x%x>\n", ssdk_bm_tick_mode_get(dev_id));
+#endif
+#ifdef HPPE
+#ifdef IN_QOS
+		printk("        tm_tick_mode = <0x%x>\n", ssdk_tm_tick_mode_get(dev_id));
+#endif
+#endif
+#ifdef DESS
+		printk("ess-psgmii\n");
+		ssdk_psgmii_reg_map_info_get(dev_id, &map);
+		mode = ssdk_psgmii_reg_access_mode_get(dev_id);
+		printk("        reg = <0x%x 0x%x>\n", map.base_addr, map.size);
+		if (mode == HSL_REG_LOCAL_BUS)
+			printk("        psgmii_access_mode = <local bus>\n");
+		else if (mode == HSL_REG_MDIO)
+			printk("        psgmii_access_mode = <mdio bus>\n");
+		else
+			printk("        psgmii_access_mode = <(null)>\n");
+#endif
+#ifdef IN_UNIPHY
+		printk("ess-uniphy\n");
+		ssdk_uniphy_reg_map_info_get(dev_id, &map);
+		mode = ssdk_uniphy_reg_access_mode_get(dev_id);
+		printk("        reg = <0x%x 0x%x>\n", map.base_addr, map.size);
+		if (mode == HSL_REG_LOCAL_BUS)
+			printk("        uniphy_access_mode = <local bus>\n");
+		else if (mode == HSL_REG_MDIO)
+			printk("        uniphy_access_mode = <mdio bus>\n");
+		else
+			printk("        uniphy_access_mode = <(null)>\n");
+#endif
+#ifdef HPPE
+#ifdef IN_QOS
+		printk("\n");
+		ssdk_dts_port_scheduler_dump(dev_id);
+		printk("\n");
+		ssdk_dts_l0scheduler_dump(dev_id);
+		printk("\n");
+		ssdk_dts_l1scheduler_dump(dev_id);
+#endif
+#endif
+		printk("\n");
+		ssdk_dts_phyinfo_dump(dev_id);
+	}
+
+	return count;
+}
+
+static a_uint16_t phy_reg_val = 0;
+static ssize_t ssdk_phy_write_reg_set(struct device *dev,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	char phy_buf[32];
+	char *this_opt;
+	char *options = phy_buf;
+	unsigned int phy_addr, reg_addr, reg_value;
+
+	if (count >= sizeof(phy_buf))
+		return 0;
+	memcpy(phy_buf, buf, count);
+	phy_buf[count] = '\0';
+
+	this_opt = strsep(&options, " ");
+	if (!this_opt)
+		goto fail;
+
+	kstrtouint(this_opt, 0, &phy_addr);
+	if ((options - phy_buf) >= (count - 1))
+		goto fail;
+
+	this_opt = strsep(&options, " ");
+	if (!this_opt)
+		goto fail;
+
+	kstrtouint(this_opt, 0, &reg_addr);
+	if ((options - phy_buf) >= (count - 1))
+		goto fail;
+
+	this_opt = strsep(&options, " ");
+	if (!this_opt)
+		goto fail;
+
+	kstrtouint(this_opt, 0, &reg_value);
+
+	qca_ar8327_phy_write(0, phy_addr, reg_addr, reg_value);
+
+	return count;
+
+fail:
+	printk("Format: phy_addr reg_addr reg_value\n");
+	return -EINVAL;
+}
+
+static ssize_t ssdk_phy_read_reg_get(struct device *dev,
+		struct device_attribute *attr,
+		char *buf)
+{
+	ssize_t count;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "reg_val = 0x%x\n", phy_reg_val);
+	return count;
+}
+
+static ssize_t ssdk_phy_read_reg_set(struct device *dev,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	char phy_buf[32];
+	char *this_opt;
+	char *options = phy_buf;
+	unsigned int phy_addr, reg_addr;
+
+	if (count >= sizeof(phy_buf))
+		return 0;
+	memcpy(phy_buf, buf, count);
+	phy_buf[count] = '\0';
+
+	this_opt = strsep(&options, " ");
+	if (!this_opt)
+		goto fail;
+
+	kstrtouint(this_opt, 0, &phy_addr);
+	if ((options - phy_buf) >= (count - 1))
+		goto fail;
+
+	this_opt = strsep(&options, " ");
+	if (!this_opt)
+		goto fail;
+
+	kstrtouint(this_opt, 0, &reg_addr);
+
+	qca_ar8327_phy_read(0, phy_addr, reg_addr, &phy_reg_val);
+
+	return count;
+
+fail:
+	printk("Format: phy_addr reg_addr\n");
+	return -EINVAL;
+}
+
+#ifdef IN_LINUX_STD_PTP
+static ssize_t ssdk_ptp_counter_get(struct device *dev,
+		struct device_attribute *attr,
+		char *buf)
+{
+	ssize_t count;
+
+	count = snprintf(buf, (ssize_t)PAGE_SIZE, "\n");
+	qca808x_ptp_stat_get();
+	return count;
+}
+
+static ssize_t ssdk_ptp_counter_set(struct device *dev,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	qca808x_ptp_stat_set();
+	return count;
+}
+#endif
+
+static const struct device_attribute ssdk_dev_id_attr =
+	__ATTR(dev_id, 0660, ssdk_dev_id_get, ssdk_dev_id_set);
+static const struct device_attribute ssdk_log_level_attr =
+	__ATTR(log_level, 0660, ssdk_log_level_get, ssdk_log_level_set);
+static const struct device_attribute ssdk_packet_counter_attr =
+	__ATTR(packet_counter, 0660, ssdk_packet_counter_get, ssdk_packet_counter_set);
+static const struct device_attribute ssdk_byte_counter_attr =
+	__ATTR(byte_counter, 0660, ssdk_byte_counter_get, ssdk_byte_counter_set);
+static const struct device_attribute ssdk_dts_dump_attr =
+	__ATTR(dts_dump, 0660, ssdk_dts_dump, NULL);
+static const struct device_attribute ssdk_phy_write_reg_attr =
+	__ATTR(phy_write_reg, 0660, NULL, ssdk_phy_write_reg_set);
+static const struct device_attribute ssdk_phy_read_reg_attr =
+	__ATTR(phy_read_reg, 0660, ssdk_phy_read_reg_get, ssdk_phy_read_reg_set);
+#ifdef IN_LINUX_STD_PTP
+static const struct device_attribute ssdk_ptp_counter_attr =
+	__ATTR(ptp_packet_counter, 0660, ssdk_ptp_counter_get, ssdk_ptp_counter_set);
+#endif
+struct kobject *ssdk_sys = NULL;
+
+int ssdk_sysfs_init (void)
+{
+	int ret = 0;
+
+	/* create /sys/ssdk/ dir */
+	ssdk_sys = kobject_create_and_add("ssdk", NULL);
+	if (!ssdk_sys) {
+		printk("Failed to register SSDK sysfs\n");
+		return ret;
+	}
+
+	/* create /sys/ssdk/dev_id file */
+	ret = sysfs_create_file(ssdk_sys, &ssdk_dev_id_attr.attr);
+	if (ret) {
+		printk("Failed to register SSDK dev id SysFS file\n");
+		goto CLEANUP_1;
+	}
+
+	/* create /sys/ssdk/log_level file */
+	ret = sysfs_create_file(ssdk_sys, &ssdk_log_level_attr.attr);
+	if (ret) {
+		printk("Failed to register SSDK log level SysFS file\n");
+		goto CLEANUP_2;
+	}
+
+	/* create /sys/ssdk/packet_counter file */
+	ret = sysfs_create_file(ssdk_sys, &ssdk_packet_counter_attr.attr);
+	if (ret) {
+		printk("Failed to register SSDK switch counter SysFS file\n");
+		goto CLEANUP_3;
+	}
+
+	/* create /sys/ssdk/byte_counter file */
+	ret = sysfs_create_file(ssdk_sys, &ssdk_byte_counter_attr.attr);
+	if (ret) {
+		printk("Failed to register SSDK switch counter bytes SysFS file\n");
+		goto CLEANUP_4;
+	}
+
+	/* create /sys/ssdk/dts_dump file */
+	ret = sysfs_create_file(ssdk_sys, &ssdk_dts_dump_attr.attr);
+	if (ret) {
+		printk("Failed to register SSDK switch show dts SysFS file\n");
+		goto CLEANUP_5;
+	}
+
+	/* create /sys/ssdk/phy_write_reg file */
+	ret = sysfs_create_file(ssdk_sys, &ssdk_phy_write_reg_attr.attr);
+	if (ret) {
+		printk("Failed to register SSDK phy write reg file\n");
+		goto CLEANUP_6;
+	}
+
+	/* create /sys/ssdk/phy_read_reg file */
+	ret = sysfs_create_file(ssdk_sys, &ssdk_phy_read_reg_attr.attr);
+	if (ret) {
+		printk("Failed to register SSDK phy read reg file\n");
+		goto CLEANUP_7;
+	}
+
+#ifdef IN_LINUX_STD_PTP
+	/* create /sys/ssdk/ptp_packet_counter file */
+	ret = sysfs_create_file(ssdk_sys, &ssdk_ptp_counter_attr.attr);
+	if (ret) {
+		printk("Failed to register SSDK ptp counter file\n");
+		goto CLEANUP_8;
+	}
+#endif
+
+	return 0;
+
+#ifdef IN_LINUX_STD_PTP
+CLEANUP_8:
+	sysfs_remove_file(ssdk_sys, &ssdk_phy_read_reg_attr.attr);
+#endif
+CLEANUP_7:
+	sysfs_remove_file(ssdk_sys, &ssdk_phy_write_reg_attr.attr);
+CLEANUP_6:
+	sysfs_remove_file(ssdk_sys, &ssdk_dts_dump_attr.attr);
+CLEANUP_5:
+	sysfs_remove_file(ssdk_sys, &ssdk_byte_counter_attr.attr);
+CLEANUP_4:
+	sysfs_remove_file(ssdk_sys, &ssdk_packet_counter_attr.attr);
+CLEANUP_3:
+	sysfs_remove_file(ssdk_sys, &ssdk_log_level_attr.attr);
+CLEANUP_2:
+	sysfs_remove_file(ssdk_sys, &ssdk_dev_id_attr.attr);
+CLEANUP_1:
+	kobject_put(ssdk_sys);
+
+	return ret;
+}
+
+void ssdk_sysfs_exit (void)
+{
+#ifdef IN_LINUX_STD_PTP
+	sysfs_remove_file(ssdk_sys, &ssdk_ptp_counter_attr.attr);
+#endif
+	sysfs_remove_file(ssdk_sys, &ssdk_phy_read_reg_attr.attr);
+	sysfs_remove_file(ssdk_sys, &ssdk_phy_write_reg_attr.attr);
+	sysfs_remove_file(ssdk_sys, &ssdk_dts_dump_attr.attr);
+	sysfs_remove_file(ssdk_sys, &ssdk_byte_counter_attr.attr);
+	sysfs_remove_file(ssdk_sys, &ssdk_packet_counter_attr.attr);
+	sysfs_remove_file(ssdk_sys, &ssdk_log_level_attr.attr);
+	sysfs_remove_file(ssdk_sys, &ssdk_dev_id_attr.attr);
+	kobject_put(ssdk_sys);
+}
+
+/*qca808x_start*/
+int
+ssdk_plat_init(ssdk_init_cfg *cfg, a_uint32_t dev_id)
+{
+/*qca808x_end*/
+	hsl_reg_mode reg_mode;
+	ssdk_reg_map_info map;
+	struct clk *  ess_clk;
+	struct clk *  cmn_clk;
+	#ifdef BOARD_AR71XX
+	int rv = 0;
+	#endif
+/*qca808x_start*/
+	printk("ssdk_plat_init start\n");
+/*qca808x_end*/
+	mutex_init(&switch_mdio_lock);
+
+	if(!ssdk_is_emulation(dev_id)){
+/*qca808x_start*/
+		if(miibus_get(dev_id))
+			return -ENODEV;
+/*qca808x_end*/
+	}
+#ifdef IN_UNIPHY
+	reg_mode = ssdk_uniphy_reg_access_mode_get(dev_id);
+	if(reg_mode == HSL_REG_LOCAL_BUS) {
+		ssdk_uniphy_reg_map_info_get(dev_id, &map);
+		qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap_nocache(map.base_addr,
+									map.size);
+		if (!qca_phy_priv_global[dev_id]->uniphy_hw_addr) {
+			SSDK_ERROR("%s ioremap fail.", __func__);
+			cfg->reg_func.uniphy_reg_set = NULL;
+			cfg->reg_func.uniphy_reg_get = NULL;
+			return -1;
+		}
+		cfg->reg_func.uniphy_reg_set = qca_uniphy_reg_write;
+		cfg->reg_func.uniphy_reg_get = qca_uniphy_reg_read;
+	}
+#endif
+	reg_mode = ssdk_switch_reg_access_mode_get(dev_id);
+	if(reg_mode == HSL_REG_LOCAL_BUS) {
+		ssdk_switch_reg_map_info_get(dev_id, &map);
+		qca_phy_priv_global[dev_id]->hw_addr = ioremap_nocache(map.base_addr,
+								map.size);
+		if (!qca_phy_priv_global[dev_id]->hw_addr) {
+			SSDK_ERROR("%s ioremap fail.", __func__);
+			return -1;
+		}
+		ess_clk = ssdk_dts_essclk_get(dev_id);
+		cmn_clk = ssdk_dts_cmnclk_get(dev_id);
+		if (!IS_ERR(ess_clk)) {
+			/* Enable ess clock here */
+			SSDK_INFO("Enable ess clk\n");
+			clk_prepare_enable(ess_clk);
+		} else if (!IS_ERR(cmn_clk)) {
+#if defined(HPPE) || defined(MP)
+			ssdk_gcc_clock_init();
+#endif
+			return 0;
+		}
+
+		cfg->reg_mode = HSL_HEADER;
+	}
+#ifdef DESS
+	reg_mode = ssdk_psgmii_reg_access_mode_get(dev_id);
+	if(reg_mode == HSL_REG_LOCAL_BUS) {
+		ssdk_psgmii_reg_map_info_get(dev_id, &map);
+		if (!request_mem_region(map.base_addr,
+					map.size, "psgmii_mem")) {
+			SSDK_ERROR("%s Unable to request psgmii resource.", __func__);
+			return -1;
+		}
+
+		qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap_nocache(map.base_addr,
+								map.size);
+		if (!qca_phy_priv_global[dev_id]->psgmii_hw_addr) {
+			SSDK_ERROR("%s ioremap fail.", __func__);
+			cfg->reg_func.psgmii_reg_set = NULL;
+			cfg->reg_func.psgmii_reg_get = NULL;
+			return -1;
+		}
+
+		cfg->reg_func.psgmii_reg_set = qca_psgmii_reg_write;
+		cfg->reg_func.psgmii_reg_get = qca_psgmii_reg_read;
+	}
+#endif
+	reg_mode = ssdk_switch_reg_access_mode_get(dev_id);
+	if(reg_mode == HSL_REG_MDIO) {
+		cfg->reg_mode = HSL_MDIO;
+	} else
+		return 0;
+/*qca808x_start*/
+
+	return 0;
+}
+
+void
+ssdk_plat_exit(a_uint32_t dev_id)
+{
+/*qca808x_end*/
+	hsl_reg_mode reg_mode;
+#ifdef DESS
+	ssdk_reg_map_info map;
+#endif
+/*qca808x_start*/
+	printk("ssdk_plat_exit\n");
+/*qca808x_end*/
+	reg_mode = ssdk_switch_reg_access_mode_get(dev_id);
+	if (reg_mode == HSL_REG_LOCAL_BUS) {
+		iounmap(qca_phy_priv_global[dev_id]->hw_addr);
+	}
+#ifdef DESS
+	reg_mode = ssdk_psgmii_reg_access_mode_get(dev_id);
+	if (reg_mode == HSL_REG_LOCAL_BUS) {
+		ssdk_psgmii_reg_map_info_get(dev_id, &map);
+		iounmap(qca_phy_priv_global[dev_id]->psgmii_hw_addr);
+		release_mem_region(map.base_addr,
+                                        map.size);
+	}
+#endif
+#ifdef IN_UNIPHY
+	reg_mode = ssdk_uniphy_reg_access_mode_get(dev_id);
+	if (reg_mode == HSL_REG_LOCAL_BUS) {
+		iounmap(qca_phy_priv_global[dev_id]->uniphy_hw_addr);
+	}
+#endif
+/*qca808x_start*/
+}
+/*qca808x_end*/
+
diff --git a/qca-ssdk/src/init/ssdk_scomphy.c b/qca-ssdk/src/init/ssdk_scomphy.c
new file mode 100644
index 0000000..1561144
--- /dev/null
+++ b/qca-ssdk/src/init/ssdk_scomphy.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "ssdk_init.h"
+
+#ifdef MP
+#include "ssdk_mp.h"
+#include "hsl_phy.h"
+#endif
+
+sw_error_t qca_scomphy_hw_init(ssdk_init_cfg *cfg, a_uint32_t dev_id)
+{
+	sw_error_t rv = SW_OK;
+
+	switch (cfg->phy_id) {
+#ifdef MP
+		case MP_GEPHY:
+			rv = qca_mp_hw_init(dev_id, cfg);
+			SW_RTN_ON_ERROR(rv);
+			break;
+#endif
+		default:
+			break;
+	}
+	return rv;
+}
+
diff --git a/qca-ssdk/src/init/ssdk_uci.c b/qca-ssdk/src/init/ssdk_uci.c
new file mode 100755
index 0000000..aebea64
--- /dev/null
+++ b/qca-ssdk/src/init/ssdk_uci.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/kconfig.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <generated/autoconf.h>
+#include <linux/delay.h>
+#include <linux/phy.h>
+#include <linux/netdevice.h>
+#include <linux/string.h>
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#include <linux/of.h>
+ #include <linux/switch.h>
+#else
+#include <net/switch.h>
+#include <linux/ar8216_platform.h>
+#endif
+#include "sw.h"
+#include "ssdk_init.h"
+#include "ssdk_plat.h"
+
+#ifdef BOARD_AR71XX
+
+struct switch_dev *old_sw_dev = NULL;
+struct net_device	  *sw_attach_dev = NULL;
+struct qca_phy_priv qca_priv;
+
+extern int qca_phy_id_chip(struct qca_phy_priv *priv);
+extern const struct switch_dev_ops qca_ar8327_sw_ops;
+extern int qca_phy_mib_work_start(struct qca_phy_priv *priv);
+extern void qca_phy_mib_work_stop(struct qca_phy_priv *priv);
+
+int
+ssdk_uci_sw_set_vlan(const struct switch_attr *attr,
+                       struct switch_val *val)
+{
+	if(old_sw_dev) {
+		struct switch_dev_ops *ops = old_sw_dev->ops;
+		if(ops) {
+			struct switch_attrlist attr_global = ops->attr_global;
+			int i = 0;
+			struct switch_attr *g_attr = attr_global.attr;
+			for(i = 0; i < attr_global.n_attr; i++) {
+				if(!strcmp(g_attr[i].name, "enable_vlan") &&
+					g_attr[i].set) {
+					g_attr[i].set(old_sw_dev, attr, val);
+					break;
+				}
+			}
+		}
+	}
+	return 0;
+}
+
+int
+ssdk_uci_sw_set_vid(const struct switch_attr *attr,
+                       struct switch_val *val)
+{
+	if(old_sw_dev) {
+		struct switch_dev_ops *ops = old_sw_dev->ops;
+		if(ops) {
+			struct switch_attrlist attr_vlan = ops->attr_vlan;
+			int i = 0;
+			struct switch_attr *v_attr = attr_vlan.attr;
+			for(i = 0; i < attr_vlan.n_attr; i++) {
+				if(!strcmp(v_attr[i].name, "vid") &&
+					v_attr[i].set) {
+					v_attr[i].set(old_sw_dev, attr, val);
+					break;
+				}
+			}
+		}
+	}
+	return 0;
+}
+
+
+int
+ssdk_uci_sw_set_pvid(int port, int vlan)
+{
+	if(old_sw_dev) {
+		struct switch_dev_ops *ops = old_sw_dev->ops;
+		if(ops && ops->set_port_pvid) {
+			ops->set_port_pvid(old_sw_dev, port, vlan);
+		}
+	}
+	return 0;
+}
+
+int
+ssdk_uci_sw_set_ports(struct switch_val *val)
+{
+	if(old_sw_dev) {
+		struct switch_dev_ops *ops = old_sw_dev->ops;
+		if(ops && ops->set_vlan_ports) {
+			ops->set_vlan_ports(old_sw_dev, val);
+		}
+	}
+	return 0;
+}
+
+
+int ssdk_uci_takeover_init()
+{
+	struct qca_phy_priv *priv = &qca_priv;
+	struct switch_dev tmp_dev;
+	struct switch_dev *sdev = NULL;
+	struct net_device *tmp_net = NULL;
+
+	/*only for s27*/
+	if((qca_ar8216_mii_read(0, 0)&0xff00)>>8 != 0x02)
+		return 0;
+
+	memset(&qca_priv, 0, sizeof(qca_priv));
+	mutex_init(&priv->reg_mutex);
+	qca_phy_id_chip(priv);
+	priv->mii_read = qca_ar8216_mii_read;
+	priv->mii_write = qca_ar8216_mii_write;
+	priv->phy_write = qca_ar8327_phy_write;
+	priv->phy_dbg_write = qca_ar8327_phy_dbg_write;
+	priv->phy_dbg_read = qca_ar8327_phy_dbg_read;
+	priv->phy_mmd_write = qca_ar8327_mmd_write;
+
+	priv->sw_dev.ops = &qca_ar8327_sw_ops;
+	priv->sw_dev.name = "QCA AR8327 AR8337";
+	priv->sw_dev.vlans = AR8327_MAX_VLANS;
+	priv->sw_dev.ports = AR8327_NUM_PORTS;
+	memset(&tmp_dev, 0, sizeof(tmp_dev));
+	tmp_dev.ops = &qca_ar8327_sw_ops;
+	tmp_dev.name = "ssdk probe";
+	SSDK_DEBUG("SSDK uci takeover!\n");
+	tmp_net = dev_get_by_name(&init_net, "eth1");
+	if(!tmp_net) {
+		tmp_net = dev_get_by_name(&init_net, "eth0");
+		if(!tmp_net)
+			return 0;
+	}
+	SSDK_DEBUG("using %s\n", tmp_net->name);
+	if(register_switch(&tmp_dev, tmp_net) < 0) {
+		SSDK_ERROR("register temp switch fail!\n");
+		return 0;
+	}
+	list_for_each_entry(sdev, &tmp_dev.dev_list, dev_list) {
+		SSDK_DEBUG("Found %s\n", sdev->name);
+		if(!strcmp(sdev->name, "AR7240/AR9330 built-in switch") ||
+			!strcmp(sdev->name, "AR934X built-in switch")) {
+			int err;
+			/*found*/
+			sw_attach_dev = sdev->netdev;
+			old_sw_dev = sdev;
+			/*unregister openwrt switch device*/
+			unregister_switch(sdev);
+			/*register ours*/
+			SSDK_DEBUG("ssdk register switch, old name %s\n", sdev->name);
+			if(err = register_switch(&priv->sw_dev, sw_attach_dev) < 0) {
+				SSDK_ERROR("ssdk register switch fail %d!\n", err);
+			}
+			break;
+		}
+	}
+	/*anyway should unregister the temp switch dev*/
+	unregister_switch(&tmp_dev);
+	if(sw_attach_dev) {
+		qca_phy_mib_work_start(&qca_priv);
+	}
+	return 0;
+}
+
+void ssdk_uci_takeover_exit()
+{
+	if(sw_attach_dev && old_sw_dev) {
+		unregister_switch(&qca_priv.sw_dev);
+		register_switch(old_sw_dev, sw_attach_dev);
+		qca_phy_mib_work_stop(&qca_priv);
+	}
+}
+
+#endif
+
+
diff --git a/qca-ssdk/src/ref/Makefile b/qca-ssdk/src/ref/Makefile
new file mode 100755
index 0000000..fc2bca7
--- /dev/null
+++ b/qca-ssdk/src/ref/Makefile
@@ -0,0 +1,45 @@
+LOC_DIR=src/ref
+LIB=REF
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST_TMP=ref_uci.c
+SRC_SW_LIST=ref_misc.c ref_uci.c
+
+ifeq (TRUE, $(IN_FDB))
+	SRC_LIST_TMP += ref_fdb.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+	SRC_LIST_TMP += ref_mib.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+	SRC_LIST_TMP += ref_misc.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+	SRC_LIST_TMP += ref_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+	SRC_LIST_TMP += ref_vlan.c
+endif
+
+ifeq (TRUE, $(IN_VSI))
+	SRC_LIST_TMP += ref_vsi.c
+endif
+
+ifeq (FALSE, $(SWCONFIG))
+	SRC_LIST=$(filter-out $(SRC_SW_LIST), $(SRC_LIST_TMP))
+else
+	SRC_LIST=$(SRC_LIST_TMP)
+endif
+
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
+
diff --git a/qca-ssdk/src/ref/ref_fdb.c b/qca-ssdk/src/ref/ref_fdb.c
new file mode 100644
index 0000000..7c1a5fc
--- /dev/null
+++ b/qca-ssdk/src/ref/ref_fdb.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "ssdk_init.h"
+#include "fal_init.h"
+#include "fal_misc.h"
+#include "fal_mib.h"
+#include "fal_port_ctrl.h"
+#include "fal_portvlan.h"
+#include "fal_fdb.h"
+#include "fal_stp.h"
+#include "fal_igmp.h"
+#include "fal_qos.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "ssdk_init.h"
+#include <linux/kconfig.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+//#include <asm/mach-types.h>
+#include <generated/autoconf.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0))
+#include <linux/ar8216_platform.h>
+#endif
+#include <linux/delay.h>
+#include <linux/phy.h>
+#include <linux/netdevice.h>
+#include "ssdk_plat.h"
+#include "ref_vlan.h"
+#include "ref_fdb.h"
+
+
+#if defined(IN_SWCONFIG)
+int
+qca_ar8327_sw_atu_flush(struct switch_dev *dev,
+				const struct switch_attr *attr,
+				struct switch_val *val)
+{
+	struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+	/* 0: dynamic 1:dynamic, static */
+	fal_fdb_entry_flush(priv->device_id, 1);
+
+	return 0;
+}
+
+int
+qca_ar8327_sw_atu_dump(struct switch_dev *dev,
+		       		const struct switch_attr *attr,
+		       		struct switch_val *val)
+{
+	struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+	a_uint32_t rv;
+	char *buf;
+	a_uint32_t len = 0;
+	a_uint32_t i = 0;
+	fal_fdb_op_t option;
+	fal_fdb_entry_t entry;
+	fal_pbmp_t port_bmp = 0;
+	a_uint32_t port_type = 0;
+
+	buf = (char*) priv->buf;
+	memset(buf, 0, 2048);
+	memset(&option, 0, sizeof(fal_fdb_op_t));
+	memset(&entry, 0, sizeof(fal_fdb_entry_t));
+
+	if (priv->version == QCA_VER_AR8227)
+		rv = fal_fdb_entry_getfirst(priv->device_id, &entry);
+	else
+		rv = fal_fdb_entry_extend_getfirst(priv->device_id, &option, &entry);
+	while (!rv)
+    {
+		len += snprintf(buf+len, 2048-len, "MAC: %02x:%02x:%02x:%02x:%02x:%02x ",
+			entry.addr.uc[0],entry.addr.uc[1],entry.addr.uc[2],entry.addr.uc[3],
+			entry.addr.uc[4],entry.addr.uc[5]);
+		if(entry.portmap_en == A_TRUE) {
+			port_bmp = entry.port.map;
+			len += snprintf(buf+len, 2048-len,
+				"PORTMAP: 0x%02x VID: 0x%x STATUS: 0x%x\n",
+				port_bmp, entry.fid, entry.static_en);
+		} else {
+			port_type = FAL_PORT_ID_TYPE(entry.port.id);
+			if(port_type == FAL_PORT_TYPE_PPORT) {
+				port_bmp = 1 << entry.port.id;
+				len += snprintf(buf+len, 2048-len,
+					"PORTMAP: 0x%02x VID: 0x%x STATUS: 0x%x\n",
+					port_bmp, entry.fid, entry.static_en);
+			} else {
+				len += snprintf(buf+len, 2048-len,
+					"DEST_INFO: 0x%02x VID: 0x%x STATUS: 0x%x\n",
+					entry.port.id, entry.fid, entry.static_en);
+			}
+		}
+
+		if (2048-len < 74){
+//			snprintf(buf+len, 2048-len, "Buffer not enough!\n");
+			break;
+		}
+		if (priv->version == QCA_VER_AR8227)
+			rv = fal_fdb_entry_getnext_byindex(priv->device_id, &i, &entry);
+		else
+			rv = fal_fdb_entry_extend_getnext(priv->device_id, &option, &entry);
+    }
+
+	val->value.s = (char*)(priv->buf);
+	val->len = len;
+
+	return 0;
+}
+#endif
+
+#define MAX_PORT 6
+/*
+ * example:
+ * vid=4;
+ * char addr[6] = {0x00, 0x01, 0x02, 0x88, 0x00, 0xaa}
+ *
+ * return value:
+ *  success: 0 - 5
+ *  fail: 0xffffffff
+ */
+fal_port_t
+ref_fdb_get_port_by_mac(unsigned int vid, const char * addr)
+{
+	fal_fdb_entry_t entry;
+	unsigned char i;
+	sw_error_t rv;
+	a_uint32_t dev_id = 0;
+
+	memset(&entry, 0, sizeof(entry));
+	SSDK_DEBUG("the fdb entry with MAC:%x-%x-%x-%x-%x-%x, fid:%d will be searched\n",
+		addr[0], addr[1], addr[2], addr[3], addr[4], addr[5], vid);
+	entry.fid = vid;
+	for (i = 0; i < 6; i++)
+		entry.addr.uc[i] = addr[i];
+	for(dev_id = 0; dev_id < SW_MAX_NR_DEV; dev_id++)
+	{
+		rv = fal_fdb_find(dev_id, &entry);
+		if (rv == SW_OK)
+		{
+			SSDK_DEBUG("device %d have the entry\n", dev_id);
+			break;
+		}
+	}
+	if(rv != SW_OK)
+	{
+		SSDK_DEBUG("the entry cannot be found\n");
+		return 0xffffffff;
+	}
+
+	for (i = 0; i < MAX_PORT; i++)
+	{
+		if (entry.port.id & (0x1 << i))
+		{
+			return i;
+		}
+	}
+	return 0xffffffff;
+}
+
+EXPORT_SYMBOL(ref_fdb_get_port_by_mac);
+
diff --git a/qca-ssdk/src/ref/ref_mib.c b/qca-ssdk/src/ref/ref_mib.c
new file mode 100644
index 0000000..add4e2e
--- /dev/null
+++ b/qca-ssdk/src/ref/ref_mib.c
@@ -0,0 +1,520 @@
+/*
+ * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "ssdk_init.h"
+#include "fal_init.h"
+#include "fal_misc.h"
+#include "fal_mib.h"
+#include "fal_port_ctrl.h"
+#include "fal_portvlan.h"
+#include "fal_fdb.h"
+#include "fal_stp.h"
+#include "fal_igmp.h"
+#include "fal_qos.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "ssdk_init.h"
+#include <linux/kconfig.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+//#include <asm/mach-types.h>
+#include <generated/autoconf.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0))
+#include <linux/ar8216_platform.h>
+#endif
+#include <linux/delay.h>
+#include <linux/phy.h>
+#include <linux/netdevice.h>
+#include "ssdk_plat.h"
+#include "ref_vlan.h"
+
+#if defined(IN_SWCONFIG)
+int
+_qca_ar8327_sw_capture_port_counter(struct switch_dev *dev, int port)
+{
+    fal_mib_info_t  mib_Info;
+    struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+
+    memset(&mib_Info, 0, sizeof(mib_Info));
+    fal_get_mib_info(priv->device_id, port, &mib_Info);
+
+    return 0;
+}
+
+int
+qca_ar8327_sw_set_reset_mibs(struct switch_dev *dev,
+			 						const struct switch_attr *attr,
+			 						struct switch_val *val)
+{
+    int i = 0;
+    int len = 0;
+    struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+    fal_mib_info_t mib_Info;
+    len = dev->ports * QCA_MIB_ITEM_NUMBER *
+             sizeof(*priv->mib_counters);
+
+    mutex_lock(&priv->mib_lock);
+    memset(priv->mib_counters, '\0', len);
+    for (i = 0; i < dev->ports; i++)
+    {
+        fal_get_mib_info(priv->device_id, i, &mib_Info);
+        fal_mib_port_flush_counters(priv->device_id, i);
+    }
+    mutex_unlock(&priv->mib_lock);
+
+    return 0;
+}
+
+int
+qca_ar8327_sw_set_port_reset_mib(struct switch_dev *dev,
+			     					const struct switch_attr *attr,
+			     					struct switch_val *val)
+{
+    int len = 0;
+    struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+    fal_mib_info_t mib_Info;
+    len = QCA_MIB_ITEM_NUMBER * sizeof(*priv->mib_counters);
+
+    mutex_lock(&priv->mib_lock);
+
+    memset(priv->mib_counters + (val->port_vlan * QCA_MIB_ITEM_NUMBER), '\0', len);
+
+    fal_get_mib_info(priv->device_id, val->port_vlan, &mib_Info);
+    fal_mib_port_flush_counters(priv->device_id, val->port_vlan);
+    mutex_unlock(&priv->mib_lock);
+
+    return 0;
+}
+
+#ifdef HPPE
+static int qca_ar8327_sw_print_xgport_mib(struct switch_dev *dev,
+	const struct switch_attr *attr, struct switch_val *val)
+{
+	int port = 0;
+	int len = 0;
+	fal_xgmib_info_t xgmib_info;
+
+	struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+	char *buf = (char *)(priv->buf);
+
+	port = val->port_vlan;
+	if (port >= dev->ports)
+	    return -EINVAL;
+
+	fal_get_xgmib_info(priv->device_id, port, &xgmib_info);
+
+	mutex_lock(&priv->mib_lock);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"XG Port %d MIB counters\n",
+	port);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxFrame", xgmib_info.RxFrame);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxByte", xgmib_info.RxByte);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxByteGood", xgmib_info.RxByteGood);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxBroadGood", xgmib_info.RxBroadGood);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxMultiGood", xgmib_info.RxMultiGood);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxFcsErr", xgmib_info.RxFcsErr);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxRuntErr", xgmib_info.RxRuntErr );
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxJabberError", xgmib_info.RxJabberError);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxUndersizeGood", xgmib_info.RxUndersizeGood);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxOversizeGood", xgmib_info.RxOversizeGood);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "Rx64Byte", xgmib_info.Rx64Byte);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "Rx128Byte", xgmib_info.Rx128Byte);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "Rx256Byte", xgmib_info.Rx256Byte);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "Rx512Byte", xgmib_info.Rx512Byte);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "Rx1024Byte", xgmib_info.Rx1024Byte);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxMaxByte", xgmib_info.RxMaxByte);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxUnicastGood", xgmib_info.RxUnicastGood);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxLengthError", xgmib_info.RxLengthError);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxOutOfRangeError", xgmib_info.RxOutOfRangeError);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxPause", xgmib_info.RxPause);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxOverFlow", xgmib_info.RxOverFlow);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxVLANFrameGoodBad", xgmib_info.RxVLANFrameGoodBad);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxWatchDogError", xgmib_info.RxWatchDogError);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxLPIUsec", xgmib_info.RxLPIUsec);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxLPITran", xgmib_info.RxLPITran);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxDropFrameGoodBad", xgmib_info.RxDropFrameGoodBad);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "RxDropByteGoodBad", xgmib_info.RxDropByteGoodBad);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "TxByte", xgmib_info.TxByte);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "TxFrame", xgmib_info.TxFrame);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "TxBroadGood", xgmib_info.TxBroadGood);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "TxMultiGood", xgmib_info.TxMultiGood);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "Tx64Byte", xgmib_info.Tx64Byte);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "Tx128Byte", xgmib_info.Tx128Byte);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "Tx256Byte", xgmib_info.Tx256Byte);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "Tx512Byte", xgmib_info.Tx512Byte);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "Tx1024Byte", xgmib_info.Tx1024Byte);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "TxMaxByte", xgmib_info.TxMaxByte);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "TxUnicast", xgmib_info.TxUnicast);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "TxMulti", xgmib_info.TxMulti);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "TxBroad", xgmib_info.TxBroad);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "TxUnderFlowError", xgmib_info.TxUnderFlowError);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "TxByteGood", xgmib_info.TxByteGood);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "TxByteGood", xgmib_info.TxByteGood);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "TxPause", xgmib_info.TxPause);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "TxVLANFrameGood", xgmib_info.TxVLANFrameGood);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "TxLPIUsec", xgmib_info.TxLPIUsec);
+
+	len += snprintf(buf + len, sizeof(priv->buf) - len,
+	"%-18s: %llu\n", "TxLPITran", xgmib_info.TxLPITran);
+
+	mutex_unlock(&priv->mib_lock);
+
+	val->value.s = buf;
+	val->len = len;
+
+	return 0;
+}
+#endif
+
+int
+qca_ar8327_sw_get_port_mib(struct switch_dev *dev,
+		       						const struct switch_attr *attr,
+		       						struct switch_val *val)
+{
+    int port = 0;
+    int len = 0;
+    int pos = 0;
+
+    struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+    char *buf = (char *)(priv->buf);
+
+    port = val->port_vlan;
+    if (port >= dev->ports)
+        return -EINVAL;
+#ifdef HPPE
+    if (priv->version == QCA_VER_HPPE &&
+        qca_hppe_port_mac_type_get(priv->device_id, port) == PORT_XGMAC_TYPE)
+    {
+        qca_ar8327_sw_print_xgport_mib(dev, attr, val);
+        return 0;
+    }
+#endif
+    mutex_lock(&priv->mib_lock);
+    _qca_ar8327_sw_capture_port_counter(dev, port);
+    pos = port * (sizeof(fal_mib_counter_t)/sizeof(a_uint64_t));
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "Port %d MIB counters\n",
+                            port);
+
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "RxBroad",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "RxPause",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "RxMulti",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "RxFcsErr",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "RxAlignErr",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "RxRunt",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "RxFragment",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "Rx64Byte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "Rx128Byte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "Rx256Byte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "Rx512Byte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "Rx1024Byte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "Rx1518Byte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "RxMaxByte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "RxTooLong",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "RxGoodByte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "RxBadByte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "RxOverFlow",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "Filtered",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "TxBroad",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "TxPause",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "TxMulti",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "TxUnderRun",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "Tx64Byte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "Tx128Byte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "Tx256Byte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "Tx512Byte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "Tx1024Byte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "Tx1518Byte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "TxMaxByte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "TxOverSize",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "TxByte",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "TxCollision",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "TxAbortCol",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "TxMultiCol",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "TxSingleCol",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "TxExcDefer",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "TxDefer",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "TxLateCol",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "RxUniCast",
+                            priv->mib_counters[pos++]);
+    len += snprintf(buf + len, sizeof(priv->buf) - len,
+                            "%-12s: %llu\n",
+                            "TxUniCast",
+                            priv->mib_counters[pos++]);
+    mutex_unlock(&priv->mib_lock);
+
+    val->value.s = buf;
+    val->len = len;
+
+    return 0;
+}
+#endif
+
+int
+_qca_ar8327_sw_capture_port_tx_counter(struct qca_phy_priv *priv, int port)
+{
+    fal_mib_info_t  mib_Info;
+
+    memset(&mib_Info, 0, sizeof(fal_mib_info_t));
+    fal_get_tx_mib_info(priv->device_id, port, &mib_Info);
+
+    return 0;
+}
+
+int
+_qca_ar8327_sw_capture_port_rx_counter(struct qca_phy_priv *priv, int port)
+{
+    fal_mib_info_t  mib_Info;
+
+    memset(&mib_Info, 0, sizeof(fal_mib_info_t));
+    fal_get_rx_mib_info(priv->device_id, port, &mib_Info);
+    return 0;
+}
+
+void
+qca_ar8327_sw_mib_task(struct qca_phy_priv *priv)
+{
+	static int loop = 0;
+
+	mutex_lock(&priv->reg_mutex);
+	if ((loop % 2) == 0)
+		_qca_ar8327_sw_capture_port_rx_counter(priv, loop/2);
+	else
+		_qca_ar8327_sw_capture_port_tx_counter(priv, loop/2);
+
+	if(++loop == (2 * (priv->ports))) {
+		loop = 0;
+	}
+
+	mutex_unlock(&priv->reg_mutex);
+
+	return;
+}
diff --git a/qca-ssdk/src/ref/ref_misc.c b/qca-ssdk/src/ref/ref_misc.c
new file mode 100755
index 0000000..5e05050
--- /dev/null
+++ b/qca-ssdk/src/ref/ref_misc.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "ssdk_init.h"
+#include "fal_init.h"
+#include "fal_misc.h"
+#include "fal_mib.h"
+#include "fal_port_ctrl.h"
+#include "fal_portvlan.h"
+#include "fal_fdb.h"
+#include "fal_stp.h"
+#include "fal_igmp.h"
+#include "fal_qos.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "ssdk_init.h"
+#include <linux/kconfig.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+//#include <asm/mach-types.h>
+#include <generated/autoconf.h>
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#include <linux/switch.h>
+#else
+#include <net/switch.h>
+#include <linux/ar8216_platform.h>
+#endif
+#include <linux/delay.h>
+#include <linux/phy.h>
+#include <linux/netdevice.h>
+#include "ssdk_plat.h"
+#include "ref_vlan.h"
+#ifdef MP
+#include <adpt.h>
+#include "hsl_phy.h"
+#endif
+
+int
+qca_ar8327_sw_set_max_frame_size(struct switch_dev *dev,
+										const struct switch_attr *attr,
+		   								struct switch_val *val)
+{
+	struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+	a_uint32_t size = val->value.i;
+	a_uint32_t ret;
+	a_uint32_t port_id = SSDK_PHYSICAL_PORT0;
+
+	if (priv->version == QCA_VER_HPPE)
+	{
+		for(port_id = SSDK_PHYSICAL_PORT1; port_id <= SSDK_PHYSICAL_PORT6;
+			port_id++)
+		{
+			ret = fal_port_max_frame_size_set(priv->device_id,
+				port_id, size);
+			if(ret)
+			{
+				return -1;
+			}
+		}
+	}
+	else if (priv->version == QCA_VER_SCOMPHY)
+	{
+#ifdef MP
+		if(adapt_scomphy_revision_get(priv->device_id)
+			== MP_GEPHY)
+		{
+			for(port_id = SSDK_PHYSICAL_PORT1; port_id <= SSDK_PHYSICAL_PORT2;
+				port_id++)
+			{
+				ret = fal_port_max_frame_size_set(priv->device_id,
+					port_id, size);
+				if(ret)
+				{
+					return -1;
+				}
+			}
+		}
+#endif
+	}
+	else
+	{
+		ret = fal_frame_max_size_set(priv->device_id, size);
+		if (ret)
+		{
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+int
+qca_ar8327_sw_get_max_frame_size(struct switch_dev *dev,
+										const struct switch_attr *attr,
+		   								struct switch_val *val)
+{
+	struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+	a_uint32_t size = 0;
+	a_uint32_t ret = 0;
+
+	if (priv->version == QCA_VER_HPPE)
+	{
+		ret = fal_port_max_frame_size_get(priv->device_id,
+			SSDK_PHYSICAL_PORT1, &size);
+	}
+	else if (priv->version == QCA_VER_SCOMPHY)
+	{
+#ifdef MP
+		if(adapt_scomphy_revision_get(priv->device_id)
+			== MP_GEPHY)
+		{
+			ret = fal_port_max_frame_size_get(priv->device_id,
+				SSDK_PHYSICAL_PORT1, &size);
+		}
+#endif
+	}
+	else
+	{
+		ret = fal_frame_max_size_get(priv->device_id, &size);
+	}
+	if (ret){
+		return -1;
+	}
+
+	val->value.i = size;
+
+	return 0;
+}
+
+int
+qca_ar8327_sw_reset_switch(struct switch_dev *dev)
+{
+	struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+	int rv = 0;
+	a_uint32_t mac_mode;
+
+	mutex_lock(&priv->reg_mutex);
+
+	/* flush all vlan translation unit entries */
+	fal_vlan_flush(priv->device_id);
+
+	/* reset VLAN shadow */
+	priv->vlan = 0;
+	memset(priv->vlan_id, 0, sizeof(a_uint16_t) * AR8327_MAX_VLANS);
+	memset(priv->vlan_table, 0, sizeof(a_uint8_t) * AR8327_MAX_VLANS);
+	memset(priv->vlan_tagged, 0, sizeof(a_uint8_t) * AR8327_MAX_VLANS);
+	memset(priv->pvid, 0, sizeof(a_uint16_t) * AR8327_NUM_PORTS);
+
+	mutex_unlock(&priv->reg_mutex);
+
+	priv->init = true;
+	rv += qca_ar8327_sw_hw_apply(dev);
+	priv->init = false;
+
+	mac_mode = ssdk_dt_global_get_mac_mode(priv->device_id, 0);
+	/* set mac5 flowcontol force for RGMII */
+	if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII5)
+		||(mac_mode == PORT_WRAPPER_SGMII1_RGMII5)) {
+		fal_port_flowctrl_forcemode_set(priv->device_id, 5, A_TRUE);
+		fal_port_flowctrl_set(priv->device_id, 5, A_TRUE);
+	}
+	/* set mac4 flowcontol force for RGMII */
+	if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII4)
+		||(mac_mode == PORT_WRAPPER_SGMII1_RGMII4)
+		||(mac_mode == PORT_WRAPPER_SGMII4_RGMII4)) {
+		/*  fix channel4 will recieve packets when enable channel0 as SGMII */
+		if(mac_mode == PORT_WRAPPER_SGMII0_RGMII4) {
+			fal_port_txmac_status_set (priv->device_id, 5, A_FALSE);
+			fal_port_rxmac_status_set (priv->device_id, 5, A_FALSE);
+		}
+		fal_port_flowctrl_forcemode_set(priv->device_id, 4, A_TRUE);
+		fal_port_flowctrl_set(priv->device_id, 4, A_TRUE);
+	}
+
+	return rv;
+}
+
diff --git a/qca-ssdk/src/ref/ref_port_ctrl.c b/qca-ssdk/src/ref/ref_port_ctrl.c
new file mode 100644
index 0000000..b0a0b67
--- /dev/null
+++ b/qca-ssdk/src/ref/ref_port_ctrl.c
@@ -0,0 +1,775 @@
+/*
+ * Copyright (c) 2012, 2016-2017,  The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "ssdk_init.h"
+#include "fal_init.h"
+#include "fal_misc.h"
+#include "fal_mib.h"
+#include "fal_port_ctrl.h"
+#include "fal_portvlan.h"
+#include "fal_fdb.h"
+#include "fal_stp.h"
+#include "fal_igmp.h"
+#include "fal_qos.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_phy.h"
+#include "ssdk_init.h"
+#include <linux/kconfig.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+//#include <asm/mach-types.h>
+#include <generated/autoconf.h>
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#include <linux/reset.h>
+#else
+#include <linux/ar8216_platform.h>
+#endif
+#include <linux/delay.h>
+#include <linux/phy.h>
+#include <linux/netdevice.h>
+#include "ssdk_plat.h"
+#include "ref_vlan.h"
+#include <linux/time.h>
+#include "f1_phy.h"
+#include "ref_port_ctrl.h"
+
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#ifdef DESS
+extern struct reset_control *ess_mac_clock_disable[5];
+#endif
+#endif
+
+#if defined(IN_SWCONFIG)
+int
+qca_ar8327_sw_get_port_link(struct switch_dev *dev, int port,
+			                        struct switch_port_link *link)
+{
+	struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+
+	fal_port_speed_t speed = FAL_SPEED_10;
+	fal_port_duplex_t duplex = FAL_FULL_DUPLEX;
+	fal_port_eee_cfg_t port_eee_cfg = {0};
+	a_bool_t status = 0;
+	a_bool_t tx_fc = 0;
+	a_bool_t rx_fc = 0;
+	sw_error_t ret;
+
+	mutex_lock(&priv->reg_mutex);
+	ret = fal_port_link_status_get(priv->device_id, port, &status);
+	if (ret == SW_OK) {
+		link->link = status;
+	} else {
+		mutex_unlock(&priv->reg_mutex);
+		return 0;
+	}
+
+	ret = fal_port_speed_get(priv->device_id, port, &speed);
+	if (ret == SW_OK) {
+		if (speed == FAL_SPEED_10) {
+			link->speed = SWITCH_PORT_SPEED_10;
+		} else if (speed == FAL_SPEED_100) {
+			link->speed = SWITCH_PORT_SPEED_100;
+		} else if (speed == FAL_SPEED_1000) {
+			link->speed = SWITCH_PORT_SPEED_1000;
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+		} else if (speed == FAL_SPEED_2500) {
+			link->speed = SWITCH_PORT_SPEED_2500;
+		} else if (speed == FAL_SPEED_5000) {
+			link->speed = SWITCH_PORT_SPEED_5000;
+		} else if (speed == FAL_SPEED_10000) {
+			link->speed = SWITCH_PORT_SPEED_10000;
+		#endif
+		} else {
+			link->speed = SWITCH_PORT_SPEED_UNKNOWN;
+		}
+	}
+
+	ret = fal_port_duplex_get(priv->device_id, port, &duplex);
+	if (ret == SW_OK) {
+		if (duplex == FAL_HALF_DUPLEX) {
+			link->duplex = 0; /* HALF */
+		} else if (duplex == FAL_FULL_DUPLEX) {
+			link->duplex = 1; /* FULL */
+		}
+	}
+
+	ret = fal_port_rxfc_status_get(priv->device_id, port, &rx_fc);
+	if (ret == SW_OK) {
+		link->rx_flow = rx_fc;
+	}
+
+	ret = fal_port_txfc_status_get(priv->device_id, port, &tx_fc);
+	if (ret == SW_OK) {
+		link->tx_flow = tx_fc;
+	}
+	ret = fal_port_interface_eee_cfg_get(priv->device_id, port,
+		&port_eee_cfg);
+	if(ret == SW_OK)
+	{
+		link->eee &= ~(ADVERTISED_100baseT_Full || ADVERTISED_1000baseT_Full);
+		if(port_eee_cfg.advertisement & FAL_PHY_EEE_100BASE_T) {
+			link->eee |= ADVERTISED_100baseT_Full;
+		}
+		if(port_eee_cfg.advertisement & FAL_PHY_EEE_1000BASE_T) {
+			link->eee |= ADVERTISED_1000baseT_Full;
+		}
+	}
+	mutex_unlock(&priv->reg_mutex);
+
+	return 0;
+}
+#endif
+
+static int qca_switch_get_qm_status(struct qca_phy_priv *priv, a_uint32_t port_id, a_uint32_t *qm_buffer_err)
+{
+	a_uint32_t reg = 0;
+	a_uint32_t qm_val = 0;
+
+	if (port_id < 0 || port_id > 6) {
+		*qm_buffer_err = 0;
+		return -1;
+	}
+	if (priv->version == 0x14)
+	{
+		if (port_id < 4) {
+			reg = 0x1D;
+			qca_switch_reg_write(priv->device_id, 0x820, (a_uint8_t *)&reg, 4);
+			qca_switch_reg_read(priv->device_id, 0x824, (a_uint8_t *)&qm_val, 4);
+			*qm_buffer_err = (qm_val >> (port_id * 8)) & 0xFF;
+		} else {
+			reg = 0x1E;
+			qca_switch_reg_write(priv->device_id, 0x820, (a_uint8_t *)&reg, 4);
+			qca_switch_reg_read(priv->device_id, 0x824, (a_uint8_t *)&qm_val, 4);
+			*qm_buffer_err = (qm_val >> ((port_id-4) * 8)) & 0xFF;
+		}
+	}
+	if (priv->version == QCA_VER_AR8337 ||
+		priv->version == QCA_VER_AR8327)
+	{
+		if (port_id < 4) {
+			reg = 0x1D;
+			priv->mii_write(priv->device_id, 0x820, reg);
+			qm_val = priv->mii_read(priv->device_id, 0x824);
+			*qm_buffer_err = (qm_val >> (port_id * 8)) & 0xFF;
+		} else {
+			reg = 0x1E;
+			priv->mii_write(priv->device_id, 0x820, reg);
+			qm_val = priv->mii_read(priv->device_id, 0x824);
+			*qm_buffer_err = (qm_val >> ((port_id-4) * 8)) & 0xFF;
+		}
+	}
+
+	return 0;
+}
+
+static int qca_switch_force_mac_1000M_full(struct qca_phy_priv *priv, a_uint32_t port_id)
+{
+	a_uint32_t reg, value = 0;
+
+	if (port_id < 0 || port_id > 6)
+		return -1;
+	if (priv->version == 0x14)
+	{
+		reg = AR8327_REG_PORT_STATUS(port_id);
+		qca_switch_reg_read(priv->device_id, reg, (a_uint8_t *)&value, 4);
+		value &= ~(BIT(6) | BITS(0,2));
+		value |= AR8327_PORT_SPEED_1000M | BIT(6);
+		qca_switch_reg_write(priv->device_id, reg, (a_uint8_t *)&value, 4);
+	}
+	if (priv->version == QCA_VER_AR8337 ||
+		priv->version == QCA_VER_AR8327)
+	{
+		reg = AR8327_REG_PORT_STATUS(port_id);
+		value = priv->mii_read(priv->device_id, reg);
+		value &= ~(BIT(6) | BITS(0,2));
+		value |= AR8327_PORT_SPEED_1000M | BIT(6);
+		priv->mii_write(priv->device_id, reg, value);
+	}
+	return 0;
+}
+
+static int qca_switch_force_mac_status(struct qca_phy_priv *priv, a_uint32_t port_id,a_uint32_t speed,a_uint32_t duplex)
+{
+	a_uint32_t reg, value = 0;
+
+	if (port_id < 1 || port_id > 5)
+		return -1;
+	if (priv->version == 0x14)
+	{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#ifdef DESS
+		/*disable mac clock*/
+		reset_control_assert(ess_mac_clock_disable[port_id -1]);
+		udelay(10);
+		reg = AR8327_REG_PORT_STATUS(port_id);
+		qca_switch_reg_read(priv->device_id,reg,(a_uint8_t*)&value,4);
+		value &= ~(BIT(6) | BITS(0,2));
+		value |= speed | (duplex?BIT(6):0);
+		qca_switch_reg_write(priv->device_id,reg,(a_uint8_t*)&value,4);
+		/*enable mac clock*/
+		reset_control_deassert(ess_mac_clock_disable[port_id -1]);
+#endif
+#endif
+	}
+	if (priv->version == QCA_VER_AR8337 ||
+	priv->version == QCA_VER_AR8327)
+	{
+		reg = AR8327_REG_PORT_STATUS(port_id);
+		value = priv->mii_read(priv->device_id, reg);
+		value &= ~(BIT(6) | BITS(0,2));
+		value |= speed | (duplex?BIT(6):0);
+		priv->mii_write(priv->device_id, reg,value);
+	}
+
+	return 0;
+}
+
+a_bool_t
+qca_ar8327_sw_rgmii_mode_valid(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	a_uint32_t rgmii_mode;
+
+	rgmii_mode = ssdk_dt_global_get_mac_mode(dev_id, 0);
+
+	if(((rgmii_mode == PORT_WRAPPER_SGMII0_RGMII5) ||
+		(rgmii_mode == PORT_WRAPPER_SGMII1_RGMII5)) && (port_id == 5))
+		return A_TRUE;
+
+	if(((rgmii_mode == PORT_WRAPPER_SGMII0_RGMII4) ||
+		(rgmii_mode == PORT_WRAPPER_SGMII1_RGMII4) ||
+		(rgmii_mode == PORT_WRAPPER_SGMII4_RGMII4)) && (port_id == 4))
+		return A_TRUE;
+
+	return A_FALSE;
+}
+
+static int
+qca_switch_get_mac_link(struct qca_phy_priv *priv, a_uint32_t port_id, a_uint32_t *link)
+{
+	a_uint32_t reg, value = 0;
+
+	if (port_id < 0 || port_id > 6)
+		return -1;
+	if (priv->version == 0x14)
+	{
+		reg = AR8327_REG_PORT_STATUS(port_id);
+		qca_switch_reg_read(priv->device_id,reg,(a_uint8_t*)&value,4);
+		*link = (value>>8)&0x1;
+	}
+	if (priv->version == QCA_VER_AR8337 ||
+	priv->version == QCA_VER_AR8327)
+	{
+		reg = AR8327_REG_PORT_STATUS(port_id);
+		value = priv->mii_read(priv->device_id, reg);
+		*link = (value>>8)&0x1;
+	}
+
+	return 0;
+}
+
+
+#define MDI_FROM_PHY_STATUS 1
+#define MDI_FROM_MANUAL 0
+#define PORT_LINK_UP 1
+#define PORT_LINK_DOWN 0
+
+#define QM_NOT_EMPTY  1
+#define QM_EMPTY  0
+
+
+static a_uint32_t phy_current_speed = 2;
+static a_uint32_t phy_current_duplex = 1;
+
+#if defined(IN_VLAN)
+int qca_ar8327_sw_enable_vlan0(a_uint32_t dev_id, a_bool_t enable, a_uint8_t portmap);
+int qca_ar8327_vlan_recovery(struct qca_phy_priv *priv)
+{
+	fal_pbmp_t portmask[AR8327_NUM_PORTS];
+	int i, j;
+	a_uint32_t reg, val;
+	u8 mask ;
+
+	mutex_lock(&priv->reg_mutex);
+
+	memset(portmask, 0, sizeof(portmask));
+	if (!priv->init) {
+		/*Handle VLAN 0 entry*/
+		if (priv->vlan_id[0] == 0 && priv->vlan_table[0] == 0) {
+			qca_ar8327_sw_enable_vlan0(priv->device_id,A_FALSE, 0);
+		}
+
+		/* calculate the port destination masks and load vlans
+		 * into the vlan translation unit */
+		for (j = 0; j < AR8327_MAX_VLANS; j++) {
+			/*
+			//############################# VLAN -1 #########################
+			//## VID=1 VLAN member : P1-t,P2-t,P3-t,P4-t,P5-t, P6-t
+			or 610 000AAAB0
+			or 614 80010002
+			*/
+			if (priv->vlan_id[j]) {
+				/* reg 0x610 VLAN_TABLE_FUNC0_OFFSET*/
+				reg = 0x610;
+				val = 0x00180000;
+				for (i = 0; i < priv->ports; ++i) {
+					mask = (1 << i);
+					portmask[i] |= ~mask & priv->vlan_table[j];
+					if (mask & priv->vlan_table[j])
+					{
+						val |= ((mask & priv->vlan_tagged[j]) ?
+								FAL_EG_TAGGED :
+								FAL_EG_UNTAGGED) << ((i<<1) + 4);
+					}
+					else
+						val |= (0x3) << ((i << 1) + 4);	// not member.
+				}
+				priv->mii_write(priv->device_id, reg, val);
+
+				/* reg 0x614 VLAN_TABLE_FUNC1_OFFSET*/
+				reg = 0x614;
+				val = 0x80000002;	// load en entry
+				val |= priv->vlan_id[j] << 16;
+				priv->mii_write(priv->device_id, reg, val);
+			}
+		}
+
+		/*Hanlde VLAN 0 entry*/
+		if (priv->vlan_id[0] == 0 && priv->vlan_table[0]) {
+			qca_ar8327_sw_enable_vlan0(priv->device_id,A_TRUE, priv->vlan_table[0]);
+		}
+
+	} else {
+#if defined(IN_PORTVLAN)
+		/* vlan disabled: port based vlan used */
+		ssdk_portvlan_init(priv->device_id);
+#endif
+	}
+
+#if defined(IN_PORTVLAN)
+	/* update the port destination mask registers and tag settings */
+	for (i = 0; i < priv->ports; i++) {
+		int pvid;
+		fal_pt_1qmode_t ingressMode;
+		fal_pt_1q_egmode_t egressMode;
+
+		if (priv->vlan) {
+			pvid = priv->vlan_id[priv->pvid[i]];
+			if (priv->vlan_tagged[priv->pvid[i]] & (1 << i)) {
+				egressMode = FAL_EG_TAGGED;
+			} else {
+				egressMode = FAL_EG_UNTAGGED;
+			}
+
+			ingressMode = FAL_1Q_SECURE;
+		} else {
+			pvid = 0;
+			egressMode = FAL_EG_UNTOUCHED;
+			ingressMode = FAL_1Q_DISABLE;
+		}
+
+		/*If VLAN 0 existes, change member port
+		   *egress mode as UNTOUCHED*/
+		if (priv->vlan_id[0] == 0 &&
+			  priv->vlan_table[0] &&
+			  ((0x1 << i) & priv->vlan_table[0]) &&
+			  priv->vlan) {
+			egressMode = FAL_EG_UNTOUCHED;
+		}
+
+		fal_port_1qmode_set(priv->device_id, i, ingressMode);
+		fal_port_egvlanmode_set(priv->device_id, i, egressMode);
+		fal_port_default_cvid_set(priv->device_id, i, pvid);
+		if (!priv->init && priv->vlan) {
+			fal_portvlan_member_update(priv->device_id, i, portmask[i]);
+		}
+	}
+#endif
+
+	mutex_unlock(&priv->reg_mutex);
+
+	return 0;
+}
+#endif
+
+int qca_qm_error_check(struct qca_phy_priv *priv)
+{
+	a_uint32_t value = 0, qm_err_int=0;
+
+	if (priv->version == QCA_VER_AR8337 ||
+		priv->version == QCA_VER_AR8327)
+	{
+		value = priv->mii_read(priv->device_id, 0x24);
+		qm_err_int = value & BIT(14);	// b14-QM_ERR_INT
+
+		if(qm_err_int)
+			return 1;
+
+		priv->mii_write(priv->device_id, 0x820, 0x0);
+		value = priv->mii_read(priv->device_id, 0x824);
+	}
+	if(priv->version==0x14)
+	{
+		qca_switch_reg_read(priv->device_id, 0x24, (a_uint8_t*)&value, 4);
+		qm_err_int = value & BIT(14);	// b14-QM_ERR_INT
+
+		if(qm_err_int)
+			return 1;
+		value = 0;
+		qca_switch_reg_write(priv->device_id, 0x820, (a_uint8_t*)&value, 4);
+		qca_switch_reg_read(priv->device_id, 0x824, (a_uint8_t*)&value, 4);
+	}
+	return value;
+}
+
+void qca_ar8327_phy_linkdown(a_uint32_t dev_id);
+int qca_ar8327_hw_init(struct qca_phy_priv *priv);
+
+int qca_qm_err_recovery(struct qca_phy_priv *priv)
+{
+	memset(priv->port_link_down, 0, sizeof(priv->port_link_down));
+	memset(priv->port_link_up, 0, sizeof(priv->port_link_up));
+	memset(priv->port_old_link, 0, sizeof(priv->port_old_link));
+	memset(priv->port_old_speed, 0, sizeof(priv->port_old_speed));
+	memset(priv->port_old_duplex, 0, sizeof(priv->port_old_duplex));
+	memset(priv->port_old_phy_status, 0, sizeof(priv->port_old_phy_status));
+	memset(priv->port_qm_buf, 0, sizeof(priv->port_qm_buf));
+
+	/* in soft reset recovery procedure */
+	qca_ar8327_phy_linkdown(priv->device_id);
+
+	qca_ar8327_hw_init(priv);
+
+#if defined(IN_VLAN)
+	qca_ar8327_vlan_recovery(priv);
+#endif
+
+	/*To add customerized recovery codes*/
+
+	return 1;
+}
+
+a_bool_t
+qca_ar8327_sw_mac_polling_port_valid(struct qca_phy_priv *priv, a_uint32_t port_id)
+{
+	a_uint32_t mac_mode;
+
+	mac_mode = ssdk_dt_global_get_mac_mode(priv->device_id, 0);
+
+	if( port_id >= AR8327_NUM_PORTS-1 || port_id < 1)
+		return A_FALSE;
+
+	if(((mac_mode == PORT_WRAPPER_SGMII0_RGMII5) ||
+		(mac_mode == PORT_WRAPPER_SGMII1_RGMII5)) && (port_id != 5))
+		return A_FALSE;
+
+	if(((mac_mode == PORT_WRAPPER_SGMII0_RGMII4) ||
+		(mac_mode == PORT_WRAPPER_SGMII1_RGMII4) ||
+		(mac_mode == PORT_WRAPPER_SGMII4_RGMII4)) && (port_id != 4))
+		return A_FALSE;
+
+	return A_TRUE;
+}
+void
+qca_phy_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t *speed_status, a_uint32_t *link_status, a_uint32_t *duplex_status)
+{
+	a_uint16_t port_phy_status;
+	a_uint32_t phy_addr;
+
+	phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id);
+	if (qca_ar8327_sw_rgmii_mode_valid(dev_id, port_id) == A_TRUE)
+		phy_addr = 4;
+
+	qca_ar8327_phy_read(dev_id, phy_addr, F1_PHY_SPEC_STATUS, &port_phy_status);
+	*speed_status = (a_uint32_t)((port_phy_status >> 14) & 0x03);
+	*link_status = (a_uint32_t)((port_phy_status & BIT(10)) >> 10);
+	*duplex_status = (a_uint32_t)((port_phy_status & BIT(13)) >> 13);
+}
+
+/* Initialize notifier list for QCA SSDK */
+static BLOCKING_NOTIFIER_HEAD(ssdk_port_link_notifier_list);
+
+int ssdk_port_link_notify(unsigned char port_id,
+            unsigned char link, unsigned char speed, unsigned char duplex)
+{
+    ssdk_port_status port_status;
+
+    port_status.port_id = port_id;
+    port_status.port_link = link;
+    port_status.speed = speed;
+    port_status.duplex = duplex;
+
+    return blocking_notifier_call_chain(&ssdk_port_link_notifier_list,	0, &port_status);
+}
+
+int ssdk_port_link_notify_register(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_register(&ssdk_port_link_notifier_list, nb);
+}
+EXPORT_SYMBOL(ssdk_port_link_notify_register);
+
+int ssdk_port_link_notify_unregister(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_unregister(&ssdk_port_link_notifier_list, nb);
+}
+EXPORT_SYMBOL(ssdk_port_link_notify_unregister);
+
+
+void
+qca_ar8327_sw_mac_polling_task(struct qca_phy_priv *priv)
+{
+	static int task_count = 0;
+	a_uint32_t i, dev_id = 0;
+	a_uint32_t value;
+	a_uint32_t link = 0, speed = 0, duplex = 0;
+	a_uint32_t qm_buffer_err = 0, phy_addr = 0;
+	a_uint16_t port_phy_status[AR8327_NUM_PORTS] = {0,0,0,0,0,0,0};
+	static a_uint32_t qm_err_cnt[AR8327_NUM_PORTS] = {0,0,0,0,0,0,0};
+
+	static a_uint32_t link_cnt[AR8327_NUM_PORTS] = {0,0,0,0,0,0,0};
+
+	dev_id = priv->device_id;
+
+	/*Only valid for S17c chip*/
+	if (priv->version != QCA_VER_AR8337 &&
+		priv->version != QCA_VER_AR8327 &&
+		priv->version != 0x14)
+		return;
+
+	value = qca_qm_error_check(priv);
+	if(value)
+	{
+		if(priv->version != 0x14)
+			qca_qm_err_recovery(priv);
+		return;
+	}
+
+	++task_count;
+
+	for (i = 1; i < AR8327_NUM_PORTS-1; i++) {
+		phy_addr = qca_ssdk_port_to_phy_addr(dev_id, i);
+		if(qca_ar8327_sw_mac_polling_port_valid(priv, i) == A_FALSE)
+			continue;
+
+		if (qca_ar8327_sw_rgmii_mode_valid(dev_id, i) == A_FALSE)
+			qca_switch_get_mac_link(priv, i, &link);
+		else
+		{
+			qca_phy_status_get(dev_id, i, &speed, &link, &duplex);
+		}
+		if (link != priv->port_old_link[i]) {
+			if (qca_ar8327_sw_rgmii_mode_valid(dev_id, i) == A_FALSE)
+			{
+				qca_phy_status_get(dev_id, i, &speed, &link, &duplex);
+			}
+			++link_cnt[i];
+			/* Up --> Down */
+			if ((priv->port_old_link[i] == PORT_LINK_UP) && (link == PORT_LINK_DOWN)) {
+
+				if (qca_ar8327_sw_rgmii_mode_valid(dev_id, i) == A_TRUE)
+				{
+					fal_port_rxmac_status_set(dev_id, i, A_FALSE);
+					fal_port_txmac_status_set(dev_id, i, A_FALSE);
+				}
+				else
+				{
+					fal_port_link_forcemode_set(dev_id, i, A_TRUE);
+					SSDK_DEBUG("%s, %d, port_id %d link down\n",__FUNCTION__,__LINE__,i);
+				}
+				priv->port_link_down[i]=0;
+				ssdk_port_link_notify(i, 0, 0, 0);
+#ifdef IN_FDB
+				fal_fdb_del_by_port(dev_id, i, 0);/*flush all dynamic fdb of this port*/
+#endif
+				if(priv->version != 0x14){
+					/* Check queue buffer */
+					a_uint16_t value = 0;
+					qm_err_cnt[i] = 0;
+					qca_switch_get_qm_status(priv, i, &qm_buffer_err);
+
+					if (qm_buffer_err) {
+						priv->port_qm_buf[i] = QM_NOT_EMPTY;
+					}
+					else {
+						priv->port_qm_buf[i] = QM_EMPTY;
+
+						/* Force MAC 1000M Full before auto negotiation */
+						qca_switch_force_mac_1000M_full(priv, i);
+						mdelay(10);
+						SSDK_DEBUG("%s, %d, port %d link down\n",__FUNCTION__,__LINE__,i);
+					}
+					qca_ar8327_phy_dbg_read(dev_id, phy_addr, 0, &value);
+					value &= (~(1<<12));
+					qca_ar8327_phy_dbg_write(dev_id, phy_addr, 0, value);
+				}
+			}
+			/* Down --> Up */
+			else if ((priv->port_old_link[i] == PORT_LINK_DOWN) && (link == PORT_LINK_UP)) {
+
+				if (priv->port_link_up[i] < 1) {
+					++(priv->port_link_up[i]);
+					qca_switch_get_qm_status(priv, i, &qm_buffer_err);
+					if (qm_buffer_err) {
+						if(priv->version != 0x14)
+								qca_qm_err_recovery(priv);
+					if(priv->link_polling_required)
+						return;
+					}
+				}
+				if(priv->port_link_up[i] >=1)
+				{
+					priv->port_link_up[i]=0;
+					qca_switch_force_mac_status(priv, i, speed, duplex);
+					udelay(100);
+					if (qca_ar8327_sw_rgmii_mode_valid(dev_id, i) == A_FALSE) {
+						fal_port_link_forcemode_set(dev_id, i, A_FALSE);
+					}
+					else
+					{
+						fal_port_rxmac_status_set(dev_id, i, A_TRUE);
+						fal_port_txmac_status_set(dev_id, i, A_TRUE);
+					}
+					udelay(100);
+					SSDK_DEBUG("%s, %d, port %d link up speed %d, duplex %d\n",__FUNCTION__,__LINE__,i, speed, duplex);
+					ssdk_port_link_notify(i, 1, speed, duplex);
+					if((speed == 0x01) && (priv->version != 0x14))/*PHY is link up 100M*/
+					{
+						a_uint16_t value = 0;
+						qca_ar8327_phy_dbg_read(dev_id, phy_addr, 0, &value);
+						value |= (1<<12);
+						qca_ar8327_phy_dbg_write(dev_id, phy_addr, 0, value);
+					}
+				}
+			}
+			if ((priv->port_link_down[i] == 0)
+				&& (priv->port_link_up[i] == 0)){
+				/* Save the current status */
+				priv->port_old_speed[i] = speed;
+				priv->port_old_link[i] = link;
+				priv->port_old_duplex[i] = duplex;
+				priv->port_old_phy_status[i] = port_phy_status[i];
+			}
+		}
+
+		if (priv->port_qm_buf[i] == QM_NOT_EMPTY) {
+			/* Check QM */
+			qca_switch_get_qm_status(priv, i, &qm_buffer_err);
+			if (qm_buffer_err) {
+				priv->port_qm_buf[i] = QM_NOT_EMPTY;
+				++qm_err_cnt[i];
+			}
+			else {
+				priv->port_qm_buf[i] = QM_EMPTY;
+				qm_err_cnt[i] = 0;
+
+				/* Force MAC 1000M Full before auto negotiation */
+				qca_switch_force_mac_1000M_full(priv, i);
+			}
+		}
+	}
+	return ;
+}
+
+void
+dess_rgmii_sw_mac_polling_task(struct qca_phy_priv *priv)
+{
+	a_uint32_t mac_mode;
+	a_uint16_t phy_spec_status, phy_link_status;
+	a_uint32_t speed, duplex;
+
+	mac_mode = ssdk_dt_global_get_mac_mode(priv->device_id, 0);
+
+	if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII5)
+		||(mac_mode == PORT_WRAPPER_SGMII1_RGMII5)
+		||(mac_mode == PORT_WRAPPER_SGMII0_RGMII4)
+		||(mac_mode == PORT_WRAPPER_SGMII1_RGMII4)
+		||(mac_mode == PORT_WRAPPER_SGMII4_RGMII4)) {
+		qca_ar8327_phy_read(priv->device_id, 4, 0x11, &phy_spec_status);
+		phy_link_status = (a_uint16_t)((phy_spec_status & BIT(10)) >> 10);
+		if (phy_link_status == 1) {
+			speed = (a_uint32_t)((phy_spec_status >> 14) & 0x03);
+			duplex = (a_uint32_t)((phy_spec_status & BIT(13)) >> 13);
+			if ((speed != phy_current_speed) || (duplex != phy_current_duplex)) {
+				if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII5)
+				||(mac_mode == PORT_WRAPPER_SGMII1_RGMII5))
+				qca_switch_force_mac_status(priv, 5,speed,duplex);
+
+				if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII4)
+				||(mac_mode == PORT_WRAPPER_SGMII1_RGMII4)
+				||(mac_mode == PORT_WRAPPER_SGMII4_RGMII4))
+				qca_switch_force_mac_status(priv, 4,speed,duplex);
+			}
+			phy_current_speed = speed;
+			phy_current_duplex = duplex;
+		}
+	}
+
+	return;
+}
+
+#ifdef IN_SWCONFIG
+int qca_ar8327_sw_set_eee(struct switch_dev *dev,
+	const struct switch_attr *attr, struct switch_val *val)
+{
+	sw_error_t rv = SW_OK;
+	struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+	fal_port_eee_cfg_t port_eee_cfg;
+
+	SSDK_DEBUG("configure EEE for dev_id: %d, port %d as %d\n",
+		priv->device_id, val->port_vlan, val->value.i);
+	rv = fal_port_interface_eee_cfg_get(priv->device_id, val->port_vlan, &port_eee_cfg);
+	if(rv != SW_OK)
+	{
+		return -1;
+	}
+	port_eee_cfg.enable = val->value.i;
+	port_eee_cfg.lpi_tx_enable = val->value.i;
+
+	if(port_eee_cfg.enable)
+	{
+		port_eee_cfg.advertisement = FAL_PHY_EEE_100BASE_T | FAL_PHY_EEE_1000BASE_T;
+	}
+	rv = fal_port_interface_eee_cfg_set(priv->device_id, val->port_vlan, &port_eee_cfg);
+	if(rv != SW_OK)
+	{
+		return -1;
+	}
+
+	return 0;
+}
+
+int qca_ar8327_sw_get_eee(struct switch_dev *dev,
+	const struct switch_attr *attr, struct switch_val *val)
+{
+	sw_error_t rv = SW_OK;
+	struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+	fal_port_eee_cfg_t port_eee_cfg;
+
+	SSDK_DEBUG("get EEE for dev_id: %d, port %d\n",
+		priv->device_id, val->port_vlan);
+	rv = fal_port_interface_eee_cfg_get(priv->device_id, val->port_vlan, &port_eee_cfg);
+	if(rv != SW_OK)
+	{
+		return -1;
+	}
+	val->value.i = port_eee_cfg.enable;
+
+	return 0;
+}
+#endif
diff --git a/qca-ssdk/src/ref/ref_uci.c b/qca-ssdk/src/ref/ref_uci.c
new file mode 100755
index 0000000..a429105
--- /dev/null
+++ b/qca-ssdk/src/ref/ref_uci.c
@@ -0,0 +1,11839 @@
+/*
+ * Copyright (c) 2013, 2015, 2017-2019, 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "ssdk_init.h"
+#include "fal_init.h"
+#ifdef IN_MISC
+#include "fal_misc.h"
+#endif
+#ifdef IN_MIB
+#include "fal_mib.h"
+#endif
+#ifdef IN_PORTCONTROL
+#include "fal_port_ctrl.h"
+#endif
+#ifdef IN_PORTVLAN
+#include "fal_portvlan.h"
+#endif
+#ifdef IN_FDB
+#include "fal_fdb.h"
+#endif
+#ifdef IN_STP
+#include "fal_stp.h"
+#endif
+#ifdef IN_IGMP
+#include "fal_igmp.h"
+#endif
+#ifdef IN_QOS
+#include "fal_qos.h"
+#endif
+#ifdef IN_ACL
+#include "fal_acl.h"
+#endif
+#ifdef IN_PPPOE
+#include "fal_pppoe.h"
+#endif
+#ifdef IN_SERVCODE
+#include "fal_servcode.h"
+#endif
+#ifdef IN_CTRLPKT
+#include "fal_ctrlpkt.h"
+#endif
+#ifdef IN_POLICER
+#include "fal_policer.h"
+#endif
+#ifdef IN_SHAPER
+#include "fal_shaper.h"
+#endif
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "ssdk_init.h"
+#include "shell.h"
+#include "shell_io.h"
+#include "shell_sw.h"
+#include <linux/kconfig.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <generated/autoconf.h>
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+#include <linux/switch.h>
+#else
+#include <net/switch.h>
+#include <linux/ar8216_platform.h>
+#endif
+#include <linux/delay.h>
+#include <linux/phy.h>
+#include <linux/netdevice.h>
+#include "ssdk_plat.h"
+#include <linux/string.h>
+#include "ref_uci.h"
+
+#define MOD_NAME_MAX_LEN	32
+#define COMMAND_NAME_MAX_LEN	128
+#define	COMMAND_LINE_MAX_LEN	1024
+#define	SWITCH_CFG_LEN_MAX	64
+char module_name[MOD_NAME_MAX_LEN] = {0};
+char command_name[COMMAND_NAME_MAX_LEN] = {0};
+char whole_command_line[COMMAND_LINE_MAX_LEN] = {0};
+char *val_ptr[SWITCH_CFG_LEN_MAX] = {0};
+static unsigned int parameter_length = 0;
+#ifdef IN_NAT
+static char *vrf_dflt_str = "0";
+static char *lb_dflt_str = "0";
+static char *cookie_dflt_str = "0";
+static char *priority_dflt_str = "no";
+static char *param_dflt_str = " ";
+#endif
+
+#ifdef IN_QOS
+#ifndef IN_QOS_MINI
+static int
+parse_qos_qtxbufsts(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "buffer_limit")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_qtxbufnr(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "queue_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "number")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_pttxbufsts(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "buffer_limit")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_pttxbufnr(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "number")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_ptrxbufnr(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "number")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_ptreden(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "red_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_ptmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_ptmodepri(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "priority")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_ptschmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "weight")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_ptdefaultspri(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "stag_pri")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_ptdefaultcpri(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ctag_pri")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_ptfsprists(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "force_stag_pri_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_ptfcprists(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "force_ctag_pri_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_ptquremark(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "queue_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "table_id")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_ptgroup(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "pcpgroup")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dscpgroup")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "flowgroup")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_ptpri(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "pcpprec")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dscpprec")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "preheaderprec")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "flowprec")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "aclprec")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		}  else if (!strcmp(ext_value_p->option_name, "postaclprec")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		}  else if (!strcmp(ext_value_p->option_name, "pcpprecforce")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		}  else if (!strcmp(ext_value_p->option_name, "dscpprecforce")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_ptremark(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "pcp_change_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dei_change_en")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dscp_change_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+static int
+parse_qos_pcpmap(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "group_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "pcp")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "internalpcp")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "internaldei")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "internalpri")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "internaldscp")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "internaldropprec")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		}  else if (!strcmp(ext_value_p->option_name, "dscpmask")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		}  else if (!strcmp(ext_value_p->option_name, "dscpen")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		}  else if (!strcmp(ext_value_p->option_name, "pcpen")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		}  else if (!strcmp(ext_value_p->option_name, "deien")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		}  else if (!strcmp(ext_value_p->option_name, "prien")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		}  else if (!strcmp(ext_value_p->option_name, "dpen")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		}  else if (!strcmp(ext_value_p->option_name, "qosprec")) {
+			val_ptr[13] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_flowmap(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "group_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "flow_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "internalpcp")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "internaldei")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "internalpri")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "internaldscp")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "internaldropprec")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_dscpmap(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "group_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dscp")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "internalpcp")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "internaldei")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "internalpri")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "internaldscp")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "internaldropprec")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_qscheduler(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "node_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "level")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "spid")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "edrrpri")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cdrrpri")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cdrr_id")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "edrr_id")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "edrrweight")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cdrrweight")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cdrrunit")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "edrrunit")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "drr_frame_mode")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_ringqueue(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "ring_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "queuebmp0")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "queuebmp1")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "queuebmp2")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "queuebmp3")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "queuebmp4")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "queuebmp5")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "queuebmp6")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "queuebmp7")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "queuebmp8")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "queuebmp9")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_dequeue(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "queue_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dequeue_ctrl_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qos_portscheduler(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+#endif
+#endif
+
+#ifdef IN_COSMAP
+static int
+parse_cos_mappri2q(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "pri")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "queue")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_cos_mappri2ehq(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "pri")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "enhance_queue")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+#ifndef IN_COSMAP_MINI
+static int
+parse_cos_mapdscp2pri(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "dscp")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "pri")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_cos_mapdscp2dp(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "dscp")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cfi")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_cos_mapup2pri(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "up")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "pri")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_cos_mapup2dp(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "up")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cfi")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_cos_mapdscp2ehpri(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "dscp")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "pri")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_cos_mapdscp2ehdp(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "dscp")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cfi")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_cos_mapup2ehpri(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "up")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "pri")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_cos_mapup2ehdp(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "up")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cfi")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_cos_mapegremark(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "remark_dscp")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "remark_up")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "remark_dei")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "green_dscp")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellow_dscp")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "green_up")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellow_up")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "green_dei")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellow_dei")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+#endif
+
+#ifdef IN_RATE
+static int
+parse_rate_portpolicer(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "combine_enable")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "byte_based")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "couple_flag")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "color_aware")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "deficit_flag")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "c_bucket_enable")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cir")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cbs")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "c_rate_flag")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "c_meter_interval")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "e_bucket_enable")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "eir")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ebs")) {
+			val_ptr[13] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "e_rate_flag")) {
+			val_ptr[14] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "e_meter_interval")) {
+			val_ptr[15] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_rate_portshaper(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "byte_based")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cir")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cbs")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "eir")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ebs")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_rate_queueshaper(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "queue_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "byte_based")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cir")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cbs")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "eir")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ebs")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_rate_aclpolicer(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "policer_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "counter_mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "byte_based")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "couple_flag")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "color_aware")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "deficit_flag")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cir")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cbs")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "eir")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ebs")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "meter_interval")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_rate_ptaddratebyte(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "add_rate_bytes")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_rate_ptgolflowen(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "golbal_flow_control_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_PORTCONTROL
+#ifndef IN_PORTCONTROL_MINI
+static int
+parse_port_duplex(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "duplex")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_speed(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "speed")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_autoadv(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "auto_adv")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_autonegenable(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_autonegrestart(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+static int
+parse_port_txhdr(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "tx_frame_atheros_header_tag_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_rxhdr(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "rx_frame_atheros_header_tag_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_hdrtype(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "atheros_header_tag_status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "atheros_header_tag_type")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#ifndef IN_PORTCONTROL_MINI
+static int
+parse_port_flowctrl(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "flow_control_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_flowctrlforcemode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "flow_control_force_mode_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_powersave(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "power_save_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_hibernate(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "hibernate_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_txmacstatus(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "tx_mac_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_rxmacstatus(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "rx_mac_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_txfcstatus(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "tx_flow_control_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_rxfcstatus(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "rx_flow_control_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+#ifndef IN_PORTCONTROL_MINI
+static int
+parse_port_bpstatus(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "back_presure_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_linkforcemode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "link_force_mode_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_macloopback(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mac_loopback_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_congedrop(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "queue_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_ringfcthresh(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "ring_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "on_thresh")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "off_thresh")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+
+
+static int
+parse_port_ieee8023az(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_crossover(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_prefermedium(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_fibermode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_localloopback(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_remoteloopback(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_magicframemac(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "macaddr")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_wolstatus(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_interfacemode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_interfacemodeapply(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_poweron(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else {
+			rv = -1;
+			break;
+		}
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_poweroff(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else {
+			rv = -1;
+			break;
+		}
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_reset(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else {
+			rv = -1;
+			break;
+		}
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_interface8023az(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_promiscmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "promisc_mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+static int
+parse_port_eeecfg(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "eee_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "eee_capability")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "lpi_sleep_timer")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "advertisement")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "lpi_tx_en")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "eee_status")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "lpi_wakeup_timer")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "link_partner_advertisement")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else {
+			rv = -1;
+			break;
+		}
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_srcfiltercfg(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "srcfilter_enable")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "srcfilter_mode")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_framemaxsize(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "frame_max_size")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_mtu(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mtusize")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mtuaction")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_mru(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mrusize")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mruaction")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_port_srcfilter(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_switch_port_loopback(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "loopback_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "crc_stripped_en")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "loopback_rate")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+#endif
+#endif
+
+#ifdef IN_PORTVLAN
+static int
+parse_portvlan_ingress(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ingress_vlan_mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_egress(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "egress_vlan_mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_member(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "member")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_forcevid(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "force_vid_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_forcemode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "force_mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_svlantpid(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "stag_tpid")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+static int
+parse_portvlan_defaultsvid(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "default_stag_vid")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+static int
+parse_portvlan_defaultcvid(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "default_ctag_vid")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_globalqinqmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "mask")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ingress_qinq_mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "egress_qinq_mode")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_ptqinqmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "mask")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ingress_qinq_role")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "egress_qinq_role")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#ifdef HPPE
+static int
+parse_portvlan_intpid(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "mask")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ctagtpid")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "stagtpid")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_egtpid(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "mask")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ctagtpid")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "stagtpid")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_ingressfilter(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "membership_filter_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tagged_filter_en")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "untagged_filter_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "priority_tagged_filter_en")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_defaultvlantag(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "direction")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "default_ctag_vid_en")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "default_stag_vid_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "mask")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "default_ctag_vid")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "default_stag_vid")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "default_ctag_pri")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "default_stag_pri")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "default_ctag_dei")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "default_stag_dei")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_tagpropagation(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "direction")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "mask")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "vid_propagation_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "pri_propagation_en")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dei_propagation_en")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_translationmissaction(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "translation_miss_action")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+static int
+parse_portvlan_egmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "mask")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ctag_egress_vlan_mode")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "stag_egress_vlan_mode")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#ifdef HPPE
+static int
+parse_portvlan_vsiegmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "vsi")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "vsi_egress_vlan_mode")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_vsiegmodeen(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "vsi_egress_vlan_mode_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_counter(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "index")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_translationadv(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "direction")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "stagformat")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "svid_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "svid")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "spcp_en")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "spcp")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "sdei_en")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "sdei")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ctagformat")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cvid_en")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cvid")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cpcp_en")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cpcp")) {
+			val_ptr[13] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cdei_en")) {
+			val_ptr[14] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cdei")) {
+			val_ptr[15] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "frame_type_en")) {
+			val_ptr[16] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "frametype")) {
+			val_ptr[17] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "protocol_en")) {
+			val_ptr[18] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "protocol")) {
+			val_ptr[19] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "vsivalid")) {
+			val_ptr[20] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "vsi_en")) {
+			val_ptr[21] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "vsi")) {
+			val_ptr[22] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "swap_svid_cvid")) {
+			val_ptr[23] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "svid_translation_cmd")) {
+			val_ptr[24] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "svidtranslation")) {
+			val_ptr[25] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cvid_translation_cmd")) {
+			val_ptr[26] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cvidtranslation")) {
+			val_ptr[27] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "swap_spcp_cpcp")) {
+			val_ptr[28] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "spcp_translation_en")) {
+			val_ptr[29] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "spcptranslation")) {
+			val_ptr[30] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cpcp_translation_en")) {
+			val_ptr[31] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cpcptranslation")) {
+			val_ptr[32] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "swap_sdei_cdei")) {
+			val_ptr[33] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "sdei_translation_en")) {
+			val_ptr[34] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "sdeitranslation")) {
+			val_ptr[35] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cdei_translation_en")) {
+			val_ptr[36] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cdeitranslation")) {
+			val_ptr[37] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "counter_en")) {
+			val_ptr[38] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "counter_id")) {
+			val_ptr[39] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "vsi_translation_en")) {
+			val_ptr[40] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "vsitranslation")) {
+			val_ptr[41] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+#ifndef IN_PORTVLAN_MINI
+static int
+parse_portvlan_invlan(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ingress_tag_mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_tlsmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "tls_mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_pripropagation(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "vlan_priority_propagation_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+
+
+static int
+parse_portvlan_vlanpropagation(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "vlan_propagation_mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_translation(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "original_vid")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "bi_direction")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "forward_direction")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "reverse_direction")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "svid")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cvid")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "original_vid_is_cvid")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "svid_enable")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cvid_enable")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "one_2_one_vlan")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_qinqmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "qinq_mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_qinqrole(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "qinq_role")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_macvlanxlt(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "egress_mac_based_vlan")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_netiso(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "net_isolate")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_egbypass(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "egress_translation_filter_bypass")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_portvlan_ptvrfid(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "vrf_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+#endif
+
+#ifdef IN_VLAN
+static int
+parse_vlan_entry(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "vlan_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_vlan_member(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "vlan_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "tag_mode")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#ifndef IN_VLAN_MINI
+static int
+parse_vlan_learnsts(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "vlan_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "learn_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+#endif
+
+#ifdef IN_FDB
+#ifndef IN_FDB_MINI
+static int
+parse_fdb_entry(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "addr")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "fid")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "dacmd")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "sacmd")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "dest_port")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "static")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "leaky")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mirror")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "clone")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "queue_override")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cross_pt_state")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "white_list_en")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "load_balance_en")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "load_balance")) {
+			val_ptr[13] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	if(val_ptr[12] == NULL) {
+		val_ptr[12] = "no";
+		parameter_length++;
+	}
+	return rv;
+}
+
+static int
+parse_fdb_resventry(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "addr")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "fid")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "dacmd")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "sacmd")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "dest_port")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "static")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "leaky")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mirror")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "clone")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "queue_override")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cross_pt_state")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "white_list_en")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+static int
+parse_fdb_portlearn(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "learn_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#ifndef IN_FDB_MINI
+static int
+parse_fdb_agectrl(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "aging_status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_fdb_agetime(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "aging_time")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_fdb_vlansmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "vlan_searching_mode")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_fdb_ptlearnlimit(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "learn_limit_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "learn_limit_counter")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_fdb_ptlearnexceedcmd(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "learn_exceed_cmd")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_fdb_learnlimit(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "learn_limit_status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "learn_limit_counter")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_fdb_learnexceedcmd(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "learn_exceed_cmd")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_fdb_ptlearnstatic(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "learn_static_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_fdb_learnctrl(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "learn_status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_fdb_ptlearnctrl(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "learn_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "learnaction")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_fdb_ptstationmove(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "stationmove_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "stationmove_action")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_fdb_ptmaclimitctrl(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "maclimit_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "maclimit_counter")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "maclimit_exceed_action")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+#endif
+
+#ifdef IN_RSS_HASH
+static int
+parse_rsshash_config(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "hash_mode")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "hask_mask")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "hash_fragment_mode")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "hash_seed")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "hash_sip_mix")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "hash_dip_mix")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "hash_protocol_mix")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "hash_sport_mix")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "hash_dport_mix")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "hash_fin_inner")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "hash_fin_outer")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_IGMP
+static int
+parse_igmp_mode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "igmp_mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_igmp_cmd(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "igmp_command")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_igmp_portjoin(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "join_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_igmp_portleave(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "leave_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_igmp_rp(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "route_port_bitmap")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_igmp_createstatus(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "create_status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_igmp_static(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "static_status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_igmp_leaky(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "leaky_status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_igmp_version3(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "version3_status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_igmp_queue(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "queue_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_igmp_ptlearnlimit(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "learn_limit_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "learn_limit_counter")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_igmp_ptlearnexceedcmd(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "learn_exceed_cmd")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_igmp_multi(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "group_type")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "group_ip_addr")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "source_type")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "source_ip_addr")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "portmap")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "vlanid")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_SEC
+static int
+parse_sec_mac(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "item")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "value")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_sec_ip(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "item")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "value")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_sec_ip4(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "item")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "value")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_sec_ip6(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "item")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "value")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_sec_tcp(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "item")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "value")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_sec_udp(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "item")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "value")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_sec_icmp4(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "item")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "value")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_sec_icmp6(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "item")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "value")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#ifdef HPPE
+static int
+parse_sec_expctrl(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "excep_type")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "excep_cmd")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "deacclr_en")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "l3route_only_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "l2fwd_only_en")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "l2flow_en")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "l3flow_en")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "multicast_en")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_sec_l3parser(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "small_ip4ttl")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "small_ip6hoplimit")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_sec_l4parser(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag0")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag0_mask")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag1")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag1_mask")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag2")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag2_mask")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag3")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag3_mask")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag4")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag4_mask")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag5")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag5_mask")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag6")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag6_mask")) {
+			val_ptr[13] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag7")) {
+			val_ptr[14] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcpflag7_mask")) {
+			val_ptr[15] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+#endif
+
+#ifdef IN_MISC
+#ifndef IN_MISC_MINI
+static int
+parse_misc_framemaxsize(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "frame_max_size")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+static int
+parse_misc_ptunkucfilter(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_misc_ptunkmcfilter(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_misc_ptbcfilter(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#ifndef IN_MISC_MINI
+static int
+parse_misc_autoneg(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+static int
+parse_misc_cpuport(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#ifndef IN_MISC_MINI
+static int
+parse_misc_pppoecmd(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "action")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_misc_pppoe(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_misc_ptdhcp(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_misc_arpcmd(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "action")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+static int
+parse_misc_eapolcmd(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "action")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_misc_eapolstatus(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#ifndef IN_MISC_MINI
+static int
+parse_misc_rip(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_misc_ptarpreq(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_misc_ptarpack(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_misc_extendpppoe(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "entry_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "session_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "multicast_session")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "unicast_session")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "vrf_id")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "l3if_index")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "l3if_index_valid")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "smacaddr")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "smacaddr_valid")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_misc_pppoeid(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "index")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "pppoe_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_misc_cpuvid(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_misc_rtdpppoe(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_misc_glomacaddr(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "macaddr")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_misc_framecrc(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_misc_pppoeen(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "l3if_index")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "pppoe_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+#endif
+
+#ifdef IN_IP
+#ifndef IN_IP_MINI
+static int
+parse_ip_hostentry(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	char* vrf_temp = "0";
+	val_ptr[6] = vrf_temp;
+	parameter_length ++;
+	val_ptr[7] = vrf_temp;
+	parameter_length ++;
+	val_ptr[12] = param_dflt_str;
+	parameter_length ++;
+	val_ptr[13] = vrf_temp;
+	parameter_length ++;
+	val_ptr[14] = vrf_temp;
+	parameter_length ++;
+	val_ptr[15] = vrf_temp;
+	parameter_length ++;
+	val_ptr[16] = param_dflt_str;
+	parameter_length ++;
+	val_ptr[17] = param_dflt_str;
+	parameter_length ++;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "entry_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "entry_flags")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "entry_status")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ip_addr")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mac_addr")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "interface_id")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "load_balance_num")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		} else if(!strcmp(ext_value_p->option_name, "vrf_id")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "action")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mirror")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "counter")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "counter_id")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		}  else if (!strcmp(ext_value_p->option_name, "dstinfo")) {
+			val_ptr[13] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		} else if (!strcmp(ext_value_p->option_name, "synctoggle")) {
+			val_ptr[14] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		} else if (!strcmp(ext_value_p->option_name, "lan_wan")) {
+			val_ptr[15] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		} else if (!strcmp(ext_value_p->option_name, "vsi")) {
+			val_ptr[16] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		} else if (!strcmp(ext_value_p->option_name, "sip_addr")) {
+			val_ptr[17] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		} else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_intfentry(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	char* vrf_temp = "0";
+	val_ptr[1] = vrf_temp;
+	parameter_length ++;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "entry_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "vrf_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		} else if(!strcmp(ext_value_p->option_name, "vlan_low")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "vlan_high")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mac_addr")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ipv4_route")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ipv6_route")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_ptarplearn(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_arplearn(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "mode")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_ptipsrcguard(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "source_guard_mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_ptarpsrcguard(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "source_guard_mode")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_routestatus(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_ipunksrc(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "action")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_arpunksrc(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "action")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_agetime(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "age_time")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_wcmphashmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "wcmp_hash_mode")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_defaultflowcmd(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "vrf_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "flow_type")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "flow_cmd")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_defaultrtflowcmd(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "vrf_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "flow_type")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "flow_cmd")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_hostroute(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "entry_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "entry_valid")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "vrf_id")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ip_version")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ip_addr")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "prefix_length")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_defaultroute(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "entry_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "entry_valid")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "vrf_id")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "route_type")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "index")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_vrfbaseaddr(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "vrf_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "base_addr")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_vrfbasemask(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "vrf_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "base_mask")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_rfsip4(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "mac_addr")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ip4_addr")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "vlan_id")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "load_balance")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_rfsip6(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "mac_addr")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ip6_addr")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "vlan_id")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "load_balance")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_vsiarpsg(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "vsi")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_violation_action")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_port_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_svlan_en")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourcegurad_cvlan_en")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceunkown_action")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_en")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_violation_action")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_port_en")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_svlan_en")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_cvlan_en")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceunknown_action")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_vsisg(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "vsi")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_sourcegurad_violation_action")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_port_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_svlan_en")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_cvlan_en")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_sourceunkown_action")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_en")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_violation_action")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_port_en")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_svlan_en")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_cvlan_en")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_sourceunknown_action")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_portarpsg(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_violation_action")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_port_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_svlan_en")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_cvlan_en")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceunkown_action")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_en")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_violation_action")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_port_en")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_svlan_en")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_cvlan_en")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceunkown_action")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_portsg(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_violation_action")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_port_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_svlan_en")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_cvlan_en")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_sourceunkown_action")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_en")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_violation_action")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_port_en")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_svlan_en")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_cvlan_en")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_sourceunkown_action")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_pubip(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "index")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4addr")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_networkroute(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "index")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "type")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "action")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dstinfo")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "lan_wan")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4addr")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4addr_mask")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_intf(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "index")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "mru")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "mtu")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ttl_dec_bypass_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4_unicast_route_en")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6_unicast_route_en")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "icmp_trigger_en")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ttl_exceed_action")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ttl_exceed_deacclr_en")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "macaddr_bitmap")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "macaddr")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_vsiintf(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "vsi")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "l3if_valid")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "l3if_index")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_portintf(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "l3if_valid")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "l3if_index")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_nexthop(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "index")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "type")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "l3if_index")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip_to_me_en")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "pub_ip_index")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "stag_fmt")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "svid")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ctag_fmt")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cvid")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "macaddr")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dnat_ip")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_portmac(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "valid")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "macaddr")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_routemiss(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "action")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_mcmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "vsi")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "l2_ip4_multicast_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "l2_ip4_multicast_mode")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "l2_ip6_multicast_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "l2_ip6_multicast_mode")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ip_globalctrl(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "mru_fail_action")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "mru_deacclr_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "mtu_fail_action")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "mtu_deacclr_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "mtu_nonfrag_fail_action")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "mtu_nonfrag_deacclr_en")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "prefix_bc_action")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "prefix_deacclr_en")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "icmp_redirect_action")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "icmp_redirect_deacclr_en")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "hash_mode_0")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "hash_mode_1")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+#endif
+
+#ifdef IN_NAT
+static int
+parse_nat_natentry(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	val_ptr[4] = vrf_dflt_str;
+	parameter_length ++;
+	val_ptr[12] = param_dflt_str;
+	parameter_length ++;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "entry_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "entry_flags")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "entry_status")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "select_index")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "vrf_id")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		} else if(!strcmp(ext_value_p->option_name, "src_addr")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "translate_addr")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "port_number")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "port_range")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "action")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mirror")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "counter")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "counter_id")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		} else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_nat_naptentry(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	val_ptr[3] = vrf_dflt_str;
+	parameter_length ++;
+	val_ptr[4] = cookie_dflt_str;
+	parameter_length ++;
+	val_ptr[5] = lb_dflt_str;
+	parameter_length ++;
+	val_ptr[15] = param_dflt_str;
+	parameter_length ++;
+	val_ptr[16] = priority_dflt_str;
+	parameter_length ++;
+	val_ptr[17] = param_dflt_str;
+	parameter_length ++;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "entry_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "entry_flags")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "entry_status")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "vrf_id")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		} else if(!strcmp(ext_value_p->option_name, "flow_cookie")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		} else if(!strcmp(ext_value_p->option_name, "load_balance")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		} else if(!strcmp(ext_value_p->option_name, "src_addr")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "dst_addr")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "translate_addr")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "src_port")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "dst_port")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "translate_port")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "action")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mirror")) {
+			val_ptr[13] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "counter")) {
+			val_ptr[14] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "counter_id")) {
+			val_ptr[15] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		}  else if(!strcmp(ext_value_p->option_name, "priority")) {
+			val_ptr[16] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		}  else if(!strcmp(ext_value_p->option_name, "priority_val")) {
+			val_ptr[17] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_nat_flowentry(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	val_ptr[13] = param_dflt_str;
+	parameter_length ++;
+	val_ptr[15] = param_dflt_str;
+	parameter_length ++;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "entry_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "entry_flags")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "entry_status")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "vrf_id")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "flow_cookie")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "load_balance")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "src_addr")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "dst_addr")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "src_port")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "dst_port")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "action")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "mirror")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "counter")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "counter_id")) {
+			val_ptr[13] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		} else if(!strcmp(ext_value_p->option_name, "priority")) {
+			val_ptr[14] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "priority_val")) {
+			val_ptr[15] = (char*)ext_value_p->option_value;
+			parameter_length --;
+		} else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_nat_flowcookie(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "proto")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "src_addr")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "dst_addr")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "src_port")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		}  else if(!strcmp(ext_value_p->option_name, "dst_port")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		}  else if(!strcmp(ext_value_p->option_name, "flow_cookie")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_nat_flowrfs(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "action")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "proto")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "src_addr")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "dst_addr")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "src_port")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		}  else if(!strcmp(ext_value_p->option_name, "dst_port")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		}  else if(!strcmp(ext_value_p->option_name, "flow_rfs")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+
+
+static int
+parse_nat_natstatus(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_nat_naptstatus(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_nat_nathash(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "hash_flag")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_nat_naptmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "napt_mode")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_nat_prvbaseaddr(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "base_addr")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_nat_prvaddrmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_nat_pubaddr(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "entry_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "pub_addr")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_nat_natunksess(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "action")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_nat_prvbasemask(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "base_addr_mask")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_nat_global(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	char *sync_str = "disable";
+	char *portbmp_str = "0x20";
+	val_ptr[1] = sync_str;
+	parameter_length++;
+	val_ptr[2] = portbmp_str;
+	parameter_length++;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else if(!strcmp(ext_value_p->option_name, "sync")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+			parameter_length--;
+		}  else if(!strcmp(ext_value_p->option_name, "portbmp")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+			parameter_length--;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_STP
+static int
+parse_stp_portstate(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "stp_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "stp_status")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_MIRROR
+static int
+parse_mirror_analypt(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "analysis_port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_mirror_ptingress(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "ingress_port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_mirror_ptegress(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "egress_port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_mirror_analycfg(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "direction")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "analysis_port")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "analysis_priority")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_LEAKY
+static int
+parse_leaky_ucmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "unicast_leaky_mode")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_leaky_mcmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "multicast_leaky_mode")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_leaky_arpmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_leaky_ptucmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_leaky_ptmcmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_TRUNK
+static int
+parse_trunk_group(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "trunk_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "trunk_port_bitmap")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_trunk_hashmode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "trunk_hash_mode")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_trunk_failover(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "failover_en")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_MIB
+static int
+parse_mib_status(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_mib_cpukeep(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+	
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_ACL
+static int
+parse_acl_rule(struct switch_val *val, a_uint32_t dev_id)
+{
+	a_uint32_t prio = 0;
+	a_uint32_t i;
+	a_uint32_t portmap = 0;
+	a_uint32_t rule_id = 0;
+	a_uint32_t obj_type = 0;
+	a_uint32_t obj_value = 0;
+	a_uint32_t list_id = 0xffffffff;
+	fal_acl_rule_t  rule;
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	a_uint32_t tmpdata = 0;
+	memset(&rule, 0, sizeof(fal_acl_rule_t));
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "list_id")) {
+			cmd_data_check_uint32((char*)ext_value_p->option_value,
+						&list_id, sizeof(a_uint32_t));
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "rule_id")) {
+			cmd_data_check_uint32((char*)ext_value_p->option_value,
+						&rule_id, sizeof(a_uint32_t));
+			if(rule_id == 0) {
+				printk("ACL rule ID should begin with 1. Please Notice!\r\n");
+			}
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "priority")) {
+			cmd_data_check_uint32((char*)ext_value_p->option_value,
+						&prio, sizeof(a_uint32_t));
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "rule_type")) {
+			cmd_data_check_ruletype((char*)ext_value_p->option_value,
+						&(rule.rule_type), sizeof(a_uint32_t));
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "is_postrouting")) {
+			cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE,
+						&(rule.post_routing), sizeof(rule.post_routing));
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_POST_ROURING_EN);
+		} else if(!strcmp(ext_value_p->option_name, "acl_pool")) {
+			cmd_data_check_integer((char*)ext_value_p->option_value,
+						&(tmpdata), 1, 0);
+			rule.acl_pool = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_RES_CHAIN);
+		} else if(!strcmp(ext_value_p->option_name, "dst_mac_address")) {
+			cmd_data_check_macaddr((char*)ext_value_p->option_value,
+						&(rule.dest_mac_val), sizeof(fal_mac_addr_t));
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_MAC_DA);
+		} else if(!strcmp(ext_value_p->option_name, "dst_mac_address_mask")) {
+			cmd_data_check_macaddr((char*)ext_value_p->option_value,
+						&(rule.dest_mac_mask), sizeof(fal_mac_addr_t));
+		} else if(!strcmp(ext_value_p->option_name, "src_mac_address")) {
+			cmd_data_check_macaddr((char*)ext_value_p->option_value,
+						&(rule.src_mac_val), sizeof(fal_mac_addr_t));
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_MAC_SA);
+		} else if(!strcmp(ext_value_p->option_name, "src_mac_address_mask")) {
+			cmd_data_check_macaddr((char*)ext_value_p->option_value,
+						&(rule.src_mac_mask), sizeof(fal_mac_addr_t));
+		} else if(!strcmp(ext_value_p->option_name, "ethernet_type")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&(tmpdata), sizeof(tmpdata));
+			rule.ethtype_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_MAC_ETHTYPE);
+		} else if(!strcmp(ext_value_p->option_name, "ethernet_type_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&(tmpdata), sizeof(tmpdata));
+			rule.ethtype_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "vlan_id")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.vid_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_MAC_VID);
+		} else if(!strcmp(ext_value_p->option_name, "vlan_id_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.vid_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "vlan_priority")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.up_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_MAC_UP);
+		} else if(!strcmp(ext_value_p->option_name, "vlan_priority_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.up_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "tagged")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.tagged_val = tmpdata;
+			rule.tagged_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_MAC_TAGGED);
+		} else if(!strcmp(ext_value_p->option_name, "tagged_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.tagged_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "cfi")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.cfi_val = tmpdata;
+			rule.cfi_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_MAC_CFI);
+		} else if(!strcmp(ext_value_p->option_name, "ctagged")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.ctagged_val = tmpdata;
+			rule.ctagged_mask = BITS(0,3);
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_MAC_CTAGGED);
+		} else if(!strcmp(ext_value_p->option_name, "ctag_vlan_id")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&(tmpdata), sizeof(tmpdata));
+			rule.ctag_vid_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_MAC_CTAG_VID);
+		} else if(!strcmp(ext_value_p->option_name, "ctag_vlan_id_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.ctag_vid_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "ctag_vlan_priority")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.ctag_pri_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_MAC_CTAG_PRI);
+		} else if(!strcmp(ext_value_p->option_name, "ctag_vlan_priority_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.ctag_pri_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "ctag_cfi")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.ctag_cfi_val = tmpdata;
+			rule.ctag_cfi_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_MAC_CTAG_CFI);
+		} else if(!strcmp(ext_value_p->option_name, "stagged")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.stagged_val = tmpdata;
+			rule.stagged_mask = BITS(0,3);
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_MAC_STAGGED);
+		} else if(!strcmp(ext_value_p->option_name, "stag_vlan_id")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.stag_vid_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_MAC_STAG_VID);
+		} else if(!strcmp(ext_value_p->option_name, "stag_vlan_id_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.stag_vid_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "stag_vlan_priority")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.stag_pri_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_MAC_STAG_PRI);
+		} else if(!strcmp(ext_value_p->option_name, "stag_vlan_priority_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&(tmpdata), sizeof(tmpdata));
+			rule.stag_pri_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "stag_dei")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.stag_dei_val = tmpdata;
+			rule.stag_dei_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_MAC_STAG_DEI);
+		} else if(!strcmp(ext_value_p->option_name, "ipv4_src_address")) {
+			cmd_data_check_ip4addr((char*)ext_value_p->option_value,
+						&(rule.src_ip4_val), 4);
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_IP4_SIP);
+		} else if(!strcmp(ext_value_p->option_name, "ipv4_src_address_mask")) {
+			cmd_data_check_ip4addr((char*)ext_value_p->option_value,
+						&(rule.src_ip4_mask), 4);
+		} else if(!strcmp(ext_value_p->option_name, "ipv4_dst_address")) {
+			cmd_data_check_ip4addr((char*)ext_value_p->option_value,
+						&(rule.dest_ip4_val), 4);
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_IP4_DIP);
+		} else if(!strcmp(ext_value_p->option_name, "ipv4_dst_address_mask")) {
+			cmd_data_check_ip4addr((char*)ext_value_p->option_value,
+						&(rule.dest_ip4_mask), 4);
+		} else if(!strcmp(ext_value_p->option_name, "ipv6_src_address")) {
+			cmd_data_check_ip6addr((char*)ext_value_p->option_value,
+						&(rule.src_ip6_val), 16);
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_IP6_SIP);
+		} else if(!strcmp(ext_value_p->option_name, "ipv6_src_address_mask")) {
+			cmd_data_check_ip6addr((char*)ext_value_p->option_value,
+						&(rule.src_ip6_mask), 16);
+		} else if(!strcmp(ext_value_p->option_name, "ipv6_dst_address")) {
+			cmd_data_check_ip6addr((char*)ext_value_p->option_value,
+						&(rule.dest_ip6_val), 16);
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_IP6_DIP);
+		} else if(!strcmp(ext_value_p->option_name, "ipv6_dst_address_mask")) {
+			cmd_data_check_ip6addr((char*)ext_value_p->option_value,
+						&(rule.dest_ip6_mask), 16);
+		} else if(!strcmp(ext_value_p->option_name, "ipv6_flow_label")) {
+			cmd_data_check_uint32((char*)ext_value_p->option_value,
+						&(rule.ip6_lable_val),
+						sizeof(rule.ip6_lable_val));
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_IP6_LABEL);
+		} else if(!strcmp(ext_value_p->option_name, "ipv6_flow_label_mask")) {
+			cmd_data_check_uint32((char*)ext_value_p->option_value,
+						&(rule.ip6_lable_mask),
+						sizeof(rule.ip6_lable_mask));
+		} else if(!strcmp(ext_value_p->option_name, "ip_protocol")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.ip_proto_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_IP_PROTO);
+		} else if(!strcmp(ext_value_p->option_name, "ip_protocol_mask")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.ip_proto_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "ip_dscp")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.ip_dscp_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_IP_DSCP);
+		} else if(!strcmp(ext_value_p->option_name, "ip_dscp_mask")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.ip_dscp_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "ip_dst_port")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.dest_l4port_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_L4_DPORT);
+			rule.dest_l4port_op = FAL_ACL_FIELD_MASK;
+		} else if(!strcmp(ext_value_p->option_name, "ip_dst_port_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.dest_l4port_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "ip_src_port")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.src_l4port_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_L4_SPORT);
+			rule.src_l4port_op = FAL_ACL_FIELD_MASK;
+		} else if(!strcmp(ext_value_p->option_name, "ip_src_port_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.src_l4port_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "icmp_type")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.icmp_type_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_ICMP_TYPE);
+		} else if(!strcmp(ext_value_p->option_name, "icmp_type_mask")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.icmp_type_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "icmp_code")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.icmp_code_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_ICMP_CODE);
+		} else if(!strcmp(ext_value_p->option_name, "icmp_code_mask")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.icmp_code_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "tcp_flag")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.tcp_flag_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_TCP_FLAG);
+		} else if(!strcmp(ext_value_p->option_name, "tcp_flag_mask")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.tcp_flag_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "ripv1")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.ripv1_val = tmpdata;
+			rule.ripv1_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_RIPV1);
+		} else if(!strcmp(ext_value_p->option_name, "dhcpv4")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.dhcpv4_val = tmpdata;
+			rule.dhcpv4_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_DHCPV4);
+		} else if(!strcmp(ext_value_p->option_name, "dhcpv6")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.dhcpv6_val = tmpdata;
+			rule.dhcpv6_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_DHCPV6);
+		} else if(!strcmp(ext_value_p->option_name, "udf_start")) {
+			cmd_data_check_udf_type((char*)ext_value_p->option_value,
+						&rule.udf_type, sizeof(rule.udf_type));
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_UDF);
+		} else if(!strcmp(ext_value_p->option_name, "udf_offset")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.udf_offset = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "udf_length")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.udf_len = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "udf_value")) {
+			tmpdata = sizeof(rule.udf_val);
+			cmd_data_check_udf_element((char*)ext_value_p->option_value,
+						(a_uint8_t *)&rule.udf_val, (a_uint32_t *)&tmpdata);
+		} else if(!strcmp(ext_value_p->option_name, "udf_mask")) {
+			tmpdata = sizeof(rule.udf_mask);
+			cmd_data_check_udf_element((char*)ext_value_p->option_value,
+						(a_uint8_t *)&rule.udf_mask, (a_uint32_t *)&tmpdata);
+		} else if(!strcmp(ext_value_p->option_name, "is_ip")) {
+			cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE,
+						&(rule.is_ip_val), sizeof(rule.is_ip_val));
+			rule.is_ip_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_IP);
+		} else if(!strcmp(ext_value_p->option_name, "is_ip6")) {
+			cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE,
+						&(rule.is_ipv6_val), sizeof(rule.is_ipv6_val));
+			rule.is_ipv6_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_IPV6);
+		} else if(!strcmp(ext_value_p->option_name, "is_fakemacheader")) {
+			cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE,
+						&(rule.is_fake_mac_header_val), sizeof(rule.is_fake_mac_header_val));
+			rule.is_fake_mac_header_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER);
+		} else if(!strcmp(ext_value_p->option_name, "is_snap")) {
+			cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE,
+						&(rule.is_snap_val), sizeof(rule.is_snap_val));
+			rule.is_snap_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_SNAP);
+		} else if(!strcmp(ext_value_p->option_name, "is_ethernet")) {
+			cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE,
+						&(rule.is_ethernet_val), sizeof(rule.is_ethernet_val));
+			rule.is_ethernet_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_ETHERNET);
+		} else if(!strcmp(ext_value_p->option_name, "is_fragment")) {
+			cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE,
+						&(rule.is_fragement_val), sizeof(rule.is_fragement_val));
+			rule.is_fragement_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_L3_FRAGMENT);
+		} else if(!strcmp(ext_value_p->option_name, "is_ahheader")) {
+			cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE,
+						&(rule.is_ah_header_val), sizeof(rule.is_ah_header_val));
+			rule.is_ah_header_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_AH_HEADER);
+		} else if(!strcmp(ext_value_p->option_name, "is_espheader")) {
+			cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE,
+						&(rule.is_esp_header_val), sizeof(rule.is_esp_header_val));
+			rule.is_esp_header_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_ESP_HEADER);
+		} else if(!strcmp(ext_value_p->option_name, "is_mobilityheader")) {
+			cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE,
+						&(rule.is_mobility_header_val), sizeof(rule.is_mobility_header_val));
+			rule.is_mobility_header_val = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_MOBILITY_HEADER);
+		} else if(!strcmp(ext_value_p->option_name, "is_fragmentheader")) {
+			cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE,
+						&(rule.is_fragment_header_val), sizeof(rule.is_fragment_header_val));
+			rule.is_fragment_header_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_FRAGMENT_HEADER);
+		} else if(!strcmp(ext_value_p->option_name, "is_otherheader")) {
+			cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE,
+						&(rule.is_other_header_val), sizeof(rule.is_other_header_val));
+			rule.is_other_header_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_OTHER_EXT_HEADER);
+		} else if(!strcmp(ext_value_p->option_name, "is_ip4option")) {
+			cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE,
+						&(rule.is_ipv4_option_val), sizeof(rule.is_ipv4_option_val));
+			rule.is_ipv4_option_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_IPV4_OPTION);
+		} else if(!strcmp(ext_value_p->option_name, "is_firstfragment")) {
+			cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE,
+						&(rule.is_first_frag_val), sizeof(rule.is_first_frag_val));
+			rule.is_first_frag_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_FIRST_FRAGMENT);
+		} else if(!strcmp(ext_value_p->option_name, "vsi_valid")) {
+			cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE,
+						&(rule.vsi_valid), sizeof(rule.vsi_valid));
+			rule.vsi_mask = 1;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_VSI_VALID);
+		} else if(!strcmp(ext_value_p->option_name, "vsi")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.vsi = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_VSI);
+		} else if(!strcmp(ext_value_p->option_name, "vsi_mask")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.vsi_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "pppoe_session_id")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.pppoe_sessionid = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_PPPOE_SESSIONID);
+		} else if(!strcmp(ext_value_p->option_name, "pppoe_session_id_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.pppoe_sessionid_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "l3ttl")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.l3_ttl = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_L3_TTL);
+		} else if(!strcmp(ext_value_p->option_name, "l3ttl_mask")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.l3_ttl_mask= tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "l3length")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.l3_length = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_L3_LENGTH);
+		} else if(!strcmp(ext_value_p->option_name, "l3length_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.l3_length_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "l3packettype")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.l3_pkt_type = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_IP_PKT_TYPE);
+		} else if(!strcmp(ext_value_p->option_name, "l3packettype_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.l3_pkt_type_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "user_defined_op0")) {
+			fal_acl_field_op_t op = FAL_ACL_FIELD_MASK;
+			cmd_data_check_fieldop((char*)ext_value_p->option_value,
+						FAL_ACL_FIELD_MASK, &op);
+			printk("%s, %d", (char*)ext_value_p->option_value, op);
+			rule.udf0_op= op;
+		} else if(!strcmp(ext_value_p->option_name, "user_defined_val0")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.udf0_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_UDF0);
+		} else if(!strcmp(ext_value_p->option_name, "user_defined_val0_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.udf0_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "user_defined_op1")) {
+			fal_acl_field_op_t op = FAL_ACL_FIELD_MASK;
+			cmd_data_check_fieldop((char*)ext_value_p->option_value,
+						FAL_ACL_FIELD_MASK, &op);
+			rule.udf1_op= op;
+		} else if(!strcmp(ext_value_p->option_name, "user_defined_val1")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.udf1_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_UDF1);
+		} else if(!strcmp(ext_value_p->option_name, "user_defined_val1_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.udf1_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "user_defined_val2")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.udf2_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_UDF2);
+		} else if(!strcmp(ext_value_p->option_name, "user_defined_val2_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.udf2_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "user_defined_val3")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.udf3_val = tmpdata;
+			FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_UDF3);
+		} else if(!strcmp(ext_value_p->option_name, "user_defined_val3_mask")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.udf3_mask = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "inverse_check_fields")) {
+			if (!strcmp(ext_value_p->option_value, "y") ||
+				!strcmp(ext_value_p->option_value, "yes")) {
+				FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_INVERSE_ALL);
+			} else if(!strcmp(ext_value_p->option_value, "n") ||
+				!strcmp(ext_value_p->option_value, "no")) {
+				FAL_FIELD_FLG_CLR(rule.field_flg,
+					FAL_ACL_FIELD_INVERSE_ALL);
+			}
+		} else if(!strcmp(ext_value_p->option_name, "packet_drop")) {
+			if(!strcmp(ext_value_p->option_value, "y") ||
+				!strcmp(ext_value_p->option_value, "yes")) {
+				FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_DENY);
+			} else if(!strcmp(ext_value_p->option_value, "n") ||
+				!strcmp(ext_value_p->option_value, "no")){
+				FAL_ACTION_FLG_CLR(rule.action_flg,
+					FAL_ACL_ACTION_DENY);
+				FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_PERMIT);
+			}
+		} else if(!strcmp(ext_value_p->option_name, "dscp_of_remark")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.dscp = tmpdata;
+			FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_REMARK_DSCP);
+		}
+#if defined(CPPE)
+		else if(!strcmp(ext_value_p->option_name, "dscp_of_remark_mask")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.dscp_mask = tmpdata;
+		}
+#endif
+		else if(!strcmp(ext_value_p->option_name, "vlan_priority_of_remark")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.up = tmpdata;
+		} else if(!strcmp(ext_value_p->option_name, "queue_of_remark")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+						&tmpdata, sizeof(tmpdata));
+			rule.queue = tmpdata;
+			FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_REMARK_QUEUE);
+		} else if(!strcmp(ext_value_p->option_name, "port_bitmap")) {
+			cmd_data_check_pbmp((char*)ext_value_p->option_value, &portmap, 4);
+		} else if(!strcmp((char*)ext_value_p->option_name, "obj_type")) {
+			cmd_data_check_uint32((char*)ext_value_p->option_value, &obj_type, 4);
+		} else if(!strcmp((char*)ext_value_p->option_name, "obj_value")) {
+			cmd_data_check_uint32((char*)ext_value_p->option_value, &obj_value, 4);
+		} else if(!strcmp((char*)ext_value_p->option_name, "user_defined_field_value")) {
+			cmd_data_check_udf_element((char*)ext_value_p->option_value,
+						(a_uint8_t *)&(rule.udf_val[0]), (a_uint32_t *)&(rule.udf_len));
+			FAL_FIELD_FLG_SET(rule.field_flg,
+					FAL_ACL_FIELD_UDF);
+		} else if(!strcmp(ext_value_p->option_name, "user_defined_field_mask")) {
+			cmd_data_check_udf_element((char*)ext_value_p->option_value,
+						(a_uint8_t *)&(rule.udf_mask[0]), (a_uint32_t *)&(rule.udf_len));
+		} else if(!strcmp(ext_value_p->option_name, "redirect_to_cpu")) {
+			if(!strcmp(ext_value_p->option_value, "y") ||
+				!strcmp(ext_value_p->option_value, "yes")) {
+				FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_RDTCPU);
+			} else if(!strcmp(ext_value_p->option_value, "n") ||
+				!strcmp(ext_value_p->option_value, "no")){
+				FAL_ACTION_FLG_CLR(rule.action_flg,
+					FAL_ACL_ACTION_RDTCPU);
+			}
+		} else if(!strcmp(ext_value_p->option_name, "copy_to_cpu")) {
+			if(!strcmp(ext_value_p->option_value, "y") ||
+				!strcmp(ext_value_p->option_value, "yes")) {
+				FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_CPYCPU);
+			} else if(!strcmp(ext_value_p->option_value, "n") ||
+				!strcmp(ext_value_p->option_value, "no")){
+				FAL_ACTION_FLG_CLR(rule.action_flg,
+					FAL_ACL_ACTION_CPYCPU);
+			}
+		} else if(!strcmp(ext_value_p->option_name, "redirect_to_ports")) {
+			FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_REDPT);
+			cmd_data_check_pbmp((char*)ext_value_p->option_value, &rule.ports, 4);
+		} else if(!strcmp(ext_value_p->option_name, "mirror")) {
+			if(!strcmp(ext_value_p->option_value, "y") ||
+				!strcmp(ext_value_p->option_value, "yes")) {
+				FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_MIRROR);
+			} else if(!strcmp(ext_value_p->option_value, "n") ||
+				!strcmp(ext_value_p->option_value, "no")){
+				FAL_ACTION_FLG_CLR(rule.action_flg,
+					FAL_ACL_ACTION_MIRROR);
+			}
+		} else if(!strcmp(ext_value_p->option_name, "remark_lookup_vid")) {
+			if(!strcmp(ext_value_p->option_value, "y") ||
+				!strcmp(ext_value_p->option_value, "yes")) {
+				FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_REMARK_LOOKUP_VID);
+			} else if(!strcmp(ext_value_p->option_value, "n") ||
+				!strcmp(ext_value_p->option_value, "no")){
+				FAL_ACTION_FLG_CLR(rule.action_flg,
+					FAL_ACL_ACTION_REMARK_LOOKUP_VID);
+			}
+		} else if(!strcmp(ext_value_p->option_name, "stag_vid_of_remark")) {
+			FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_REMARK_STAG_VID);
+			cmd_data_check_uint16((char*)ext_value_p->option_value, (a_uint32_t *)&rule.stag_vid, 4);
+		} else if(!strcmp(ext_value_p->option_name, "stag_priority_of_remark")) {
+			FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_REMARK_STAG_PRI);
+			cmd_data_check_uint16((char*)ext_value_p->option_value, (a_uint32_t *)&rule.stag_pri, 4);
+		} else if(!strcmp(ext_value_p->option_name, "stag_dei_of_remark")) {
+			FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_REMARK_STAG_DEI);
+			cmd_data_check_uint16((char*)ext_value_p->option_value, (a_uint32_t *)&rule.stag_dei, 4);
+		} else if(!strcmp(ext_value_p->option_name, "ctag_vid_of_remark")) {
+			FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_REMARK_CTAG_VID);
+			cmd_data_check_uint16((char*)ext_value_p->option_value, (a_uint32_t *)&rule.ctag_vid, 4);
+		} else if(!strcmp(ext_value_p->option_name, "ctag_priority_of_remark")) {
+			FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_REMARK_CTAG_PRI);
+			cmd_data_check_uint16((char*)ext_value_p->option_value, (a_uint32_t *)&rule.ctag_pri, 4);
+		} else if(!strcmp(ext_value_p->option_name, "ctag_cfi_of_remark")) {
+			FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_REMARK_CTAG_CFI);
+			cmd_data_check_uint16((char*)ext_value_p->option_value, (a_uint32_t *)&rule.ctag_cfi, 4);
+		} else if(!strcmp(ext_value_p->option_name, "action_policer_id")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						(a_uint32_t *)&(rule.policer_ptr), sizeof(a_uint32_t));
+			FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_POLICER_EN);
+		} else if(!strcmp(ext_value_p->option_name, "action_arp_ptr")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						(a_uint32_t *)&(rule.arp_ptr), sizeof(a_uint32_t));
+			FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_ARP_EN);
+		} else if(!strcmp(ext_value_p->option_name, "action_wcmp_ptr")) {
+			cmd_data_check_uint16((char*)ext_value_p->option_value,
+						(a_uint32_t *)&(rule.wcmp_ptr), sizeof(a_uint32_t));
+			FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_WCMP_EN);
+		} else if(!strcmp(ext_value_p->option_name, "action_snat")) {
+			if(!strcmp(ext_value_p->option_value, "y") ||
+				!strcmp(ext_value_p->option_value, "yes")) {
+				FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_POLICY_FORWARD_EN);
+				rule.policy_fwd |= FAL_ACL_POLICY_SNAT;
+			} else if(!strcmp(ext_value_p->option_value, "n") ||
+				!strcmp(ext_value_p->option_value, "no")){
+				rule.policy_fwd &= ~ FAL_ACL_POLICY_SNAT;
+			}
+		} else if(!strcmp(ext_value_p->option_name, "action_dnat")) {
+			if(!strcmp(ext_value_p->option_value, "y") ||
+				!strcmp(ext_value_p->option_value, "yes")) {
+				FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_POLICY_FORWARD_EN);
+				rule.policy_fwd |= FAL_ACL_POLICY_DNAT;
+			} else if(!strcmp(ext_value_p->option_value, "n") ||
+				!strcmp(ext_value_p->option_value, "no")){
+				rule.policy_fwd &= ~ FAL_ACL_POLICY_DNAT;
+			}
+		} else if(!strcmp(ext_value_p->option_name, "bypass_egress_translation")) {
+			if(!strcmp(ext_value_p->option_value, "y") ||
+				!strcmp(ext_value_p->option_value, "yes")) {
+				FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_BYPASS_EGRESS_TRANS);
+			} else if(!strcmp(ext_value_p->option_value, "n") ||
+				!strcmp(ext_value_p->option_value, "no")){
+				FAL_ACTION_FLG_CLR(rule.action_flg,
+					FAL_ACL_ACTION_BYPASS_EGRESS_TRANS);
+			}
+		} else if(!strcmp(ext_value_p->option_name, "interrupt_trigger")) {
+			if(!strcmp(ext_value_p->option_value, "y") ||
+				!strcmp(ext_value_p->option_value, "yes")) {
+				FAL_ACTION_FLG_SET(rule.action_flg,
+					FAL_ACL_ACTION_MATCH_TRIGGER_INTR);
+			} else if(!strcmp(ext_value_p->option_value, "n") ||
+				!strcmp(ext_value_p->option_value, "no")){
+				FAL_ACTION_FLG_CLR(rule.action_flg,
+					FAL_ACL_ACTION_MATCH_TRIGGER_INTR);
+			}
+		} else if(!strcmp(ext_value_p->option_name, "bypass_bitmap")) {
+			cmd_data_check_uint32((char*)ext_value_p->option_value,
+				&(rule.bypass_bitmap), sizeof(rule.bypass_bitmap));
+		} else if(!strcmp(ext_value_p->option_name, "enqueue_priority")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+				&tmpdata, sizeof(tmpdata));
+			rule.enqueue_pri = tmpdata;
+			FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_ENQUEUE_PRI);
+		} else if(!strcmp(ext_value_p->option_name, "stagformat")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+				&tmpdata, sizeof(tmpdata));
+			rule.stag_fmt = tmpdata;
+			FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_REMARK_STAG_VID);
+		} else if(!strcmp(ext_value_p->option_name, "ctagformat")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+				&tmpdata, sizeof(tmpdata));
+			rule.ctag_fmt = tmpdata;
+			FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID);
+		} else if(!strcmp(ext_value_p->option_name, "internaldropprec")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+				&tmpdata, sizeof(tmpdata));
+			rule.int_dp = tmpdata;
+			FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_INT_DP);
+		} else if(!strcmp(ext_value_p->option_name, "servicecode")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+				&tmpdata, sizeof(tmpdata));
+			rule.service_code= tmpdata;
+			FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_SERVICE_CODE);
+		} else if(!strcmp(ext_value_p->option_name, "cpucode")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+				&tmpdata, sizeof(tmpdata));
+			rule.cpu_code = tmpdata;
+			FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_CPU_CODE);
+		} else if(!strcmp(ext_value_p->option_name, "metadata_en")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+				&tmpdata, sizeof(tmpdata));
+			if(tmpdata)
+				FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_METADATA_EN);
+		} else if(!strcmp(ext_value_p->option_name, "synctoggle")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+				&tmpdata, sizeof(tmpdata));
+			if(tmpdata)
+				FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_SYN_TOGGLE);
+		}
+#if defined(CPPE)
+		else if(!strcmp(ext_value_p->option_name, "qos_res_prec")) {
+			cmd_data_check_uint8((char*)ext_value_p->option_value,
+				&tmpdata, sizeof(tmpdata));
+			rule.qos_res_prec = tmpdata;
+		}
+#endif
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+	/*to be compatible with previous version which didn't define list id*/
+	if(0xffffffff == list_id) {
+		list_id = rule_id;
+		rule_id = 0;
+	} else {
+		rule.pri = prio & 0x7;
+		prio = (prio >> 3) & 0x3f;
+	}
+	SSDK_DEBUG("uci set acl list %d, rule %d\n", list_id, rule_id);
+	SSDK_DEBUG("uci set acl portbitmap 0x%x, obj_type %d, obj_value %d\n",
+			portmap, obj_type, obj_value);
+	fal_acl_list_creat(dev_id, list_id, prio);
+	fal_acl_rule_add(dev_id, list_id, rule_id, 1, &rule);
+	/*bind to port bitmap*/
+	if( portmap != 0 ) {
+		for (i = 0; i < AR8327_NUM_PORTS; i++) {
+			fal_acl_list_unbind(dev_id, list_id, 0, 0, i);
+			if (portmap & (0x1 << i)) {
+				rv = fal_acl_list_bind(dev_id, list_id, 0, 0, i);
+				if(rv != SW_OK){
+					SSDK_ERROR("uci set acl fail %d\n", rv);
+				}
+			}
+		}
+	} else {
+		rv = fal_acl_list_bind(dev_id, list_id, 0, obj_type, obj_value);
+		if(rv != SW_OK){
+			SSDK_ERROR("uci set acl fail %d\n", rv);
+		}
+	}
+	fal_acl_status_set(dev_id, A_TRUE);
+
+	return rv;
+}
+
+static int
+parse_acl_udfprofile(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "user_defined_type")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "user_defined_offset")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "user_defined_length")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_acl_udf(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "packet_type")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "index")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "user_defined_type")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "user_defined_offset")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+#endif
+
+#ifdef IN_FLOW
+static int
+parse_flow_entry(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "add_mode")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "entry_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "entrytype")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "host_addr_type")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "host_addr_index")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "protocol")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "age")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "srcintf_valid")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "srcintf_index")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "fwdtype")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "snat_nexthop")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "snat_srcport")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dnat_nexthop")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dnat_dstport")) {
+			val_ptr[13] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "route_nexthop")) {
+			val_ptr[14] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "portvalid")) {
+			val_ptr[15] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "routeport")) {
+			val_ptr[16] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "bridgeport")) {
+			val_ptr[17] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "deacclr_en")) {
+			val_ptr[18] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "copy_tocpu_en")) {
+			val_ptr[19] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "syntoggle")) {
+			val_ptr[20] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "priprofile")) {
+			val_ptr[21] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "sevicecode")) {
+			val_ptr[22] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "iptype")) {
+			val_ptr[23] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4addr")) {
+			val_ptr[26] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "srcport")) {
+			val_ptr[24] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dstport")) {
+			val_ptr[25] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tree_id")) {
+			val_ptr[27] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_flow_status(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "status")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_flow_age(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "agetime")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ageunit")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_flow_mgmt(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "flowtype")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "flowdirection")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "flow_miss_action")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "frag_bypass_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tcp_specific_bypass_en")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "all_bypass_en")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "keysel")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_flow_host(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "add_mode")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "entry_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "entrytype")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "host_addr_type")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "host_addr_index")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "protocol")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "age")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "srcintf_valid")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "srcintf_index")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "fwdtype")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "snat_nexthop")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "snat_srcport")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dnat_nexthop")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dnat_dstport")) {
+			val_ptr[13] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "route_nexthop")) {
+			val_ptr[14] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "portvalid")) {
+			val_ptr[15] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "routeport")) {
+			val_ptr[16] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "bridgeport")) {
+			val_ptr[17] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "deacclr_en")) {
+			val_ptr[18] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "copy_tocpu_en")) {
+			val_ptr[19] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "syntoggle")) {
+			val_ptr[20] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "priprofile")) {
+			val_ptr[21] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "sevicecode")) {
+			val_ptr[22] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "iptype")) {
+			val_ptr[23] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip4addr")) {
+			val_ptr[26] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "srcport")) {
+			val_ptr[24] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dstport")) {
+			val_ptr[25] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "tree_id")) {
+			val_ptr[27] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ipentry_id")) {
+			val_ptr[28] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "entry_flags")) {
+			val_ptr[29] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "entry_status")) {
+			val_ptr[30] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip_addr")) {
+			val_ptr[31] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "mac_addr")) {
+			val_ptr[32] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "interface_id")) {
+			val_ptr[33] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "load_balance_num")) {
+			val_ptr[34] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "vrf_id")) {
+			val_ptr[35] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[36] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "action")) {
+			val_ptr[37] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "mirror")) {
+			val_ptr[38] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "counter")) {
+			val_ptr[39] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "destinfo")) {
+			val_ptr[40] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip_synctoggle")) {
+			val_ptr[41] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "lan_wan")) {
+			val_ptr[42] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_flow_global(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "srcif_check_action")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "srcif_check_deacclr_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "service_loop_en")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "service_loop_action")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "service_loop_deacclr_en")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "flow_deacclr_action")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "sync_mismatch_action")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "sync_mismatch_deacclr_en")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "hash_mode_0")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "hash_mode_1")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_BM
+static int
+parse_bm_ctrl(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "enable")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_bm_portgroupmap(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "group_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_bm_groupbuff(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "group_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "bufnum")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_bm_portrsvbuff(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "prealloc_bufnum")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "react_bufnum")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_bm_portsthresh(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "maxthreshold")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "resume_offset")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_bm_portdthresh(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "weight")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "sharedceiling")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "resumeoffset")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "resume_min_threshold")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+#endif
+
+#ifdef IN_QM
+static int
+parse_qm_ucastqbase(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "srcprofile")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "servicecode_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "servicecode")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cpucode_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cpucode")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "destport")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "queuebase")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "profile")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_ucastpriclass(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "profile")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "priority")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "class")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_mcastpriclass(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "priority")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "class")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_queue(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "queue_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_ucasthash(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "profile")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "rsshash")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "queuehash")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_ucastdflthash(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "queuevalue")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_mcastcpucode(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "cpucode")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "class")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_acctrl(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "type")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "obj_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "admis_ctrl_en")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "admis_flowctrl_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_acprebuffer(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "type")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "obj_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "bufnum")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_acqgroup(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "queue_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "group_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_acsthresh(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "type")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "obj_id")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "color_en")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "wred_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "greenmax")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "green_min_offset")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "yel_max_offset")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "yel_min_offset")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "red_max_offset")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "red_min_offset")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "green_resume_offset")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "yel_resume_offset")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "red_resume_offset")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_acdthresh(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "queue_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "color_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "wred_en")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "sharedweight")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "green_min_offset")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "yel_max_offset")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "yel_min_offset")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "red_max_offset")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "red_min_offset")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "green_resume_off")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "yel_resume_offset")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "red_resume_offset")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ceiling")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_acgbuff(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "group_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "prealloc_bufnum")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "total_bufnum")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_cntctrl(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "cnt_en")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_cnt(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "queue_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_enqueue(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "queue_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "enqueue_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_qm_srcprofile(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "sourceprofile")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+#endif
+
+#ifdef IN_SERVCODE
+static int
+parse_servcode_config(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "servcode_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "destport_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "destport_id")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "bypass_bitmap_0")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "bypass_bitmap_1")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "bypass_bitmap_2")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "direction")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "field_update_bitmap")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "next_servicecode")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "hardwareservices")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "offsetselection")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_servcode_loopcheck(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "loopcheck_en")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_CTRLPKT
+static int
+parse_ctrlpkt_ethernettype(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "profile_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ethernettype")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ctrlpkt_rfdb(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "profile_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "rfdb_macaddr")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_ctrlpkt_appprofile(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_bitmap")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ethtype_profile_bitmap")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "rfdb_profile_bitmap")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "eapol_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "pppoe_en")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "igmp_en")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "arp_request_en")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "arp_reponse_en")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dhcp4_en")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "dhcp6_en")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "mld_en")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6ns_en")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ip6na_en")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ctrlpkt_profile_action")) {
+			val_ptr[13] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "sourceguard_bypass")) {
+			val_ptr[14] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "l2filter_bypass")) {
+			val_ptr[15] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ingress_stp_bypass")) {
+			val_ptr[16] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "ingress_vlan_filter_bypass")) {
+			val_ptr[17] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_POLICER
+static int
+parse_policer_timeslot(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "timeslot")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_policer_fcscompensation(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "fcscompensation_length")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_policer_portentry(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "policer_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "coupling_en")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "colormode")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "frametype")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "metermode")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "meterunit")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cir")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cbs")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "eir")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ebs")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellow_priremark_en")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellow_dropprec_remark_en")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellow_pcpremark_en")) {
+			val_ptr[13] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellow_deiremark_en")) {
+			val_ptr[14] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellowpri")) {
+			val_ptr[15] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellow_dropprec")) {
+			val_ptr[16] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellowpcp")) {
+			val_ptr[17] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellowdei")) {
+			val_ptr[18] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "redaction")) {
+			val_ptr[19] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "red_priremark_en")) {
+			val_ptr[20] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "red_dropprec_remark_en")) {
+			val_ptr[21] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "red_pcpremark_en")) {
+			val_ptr[22] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "red_deiremark_en")) {
+			val_ptr[23] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "redpri")) {
+			val_ptr[24] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "red_dropprec")) {
+			val_ptr[25] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "redpcp")) {
+			val_ptr[26] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "reddei")) {
+			val_ptr[27] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_policer_aclentry(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "index")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "policer_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "coupling_en")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "colormode")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "metermode")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "meterunit")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cir")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cbs")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "eir")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ebs")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellow_priremark_en")) {
+			val_ptr[10] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellow_dropprec_remark_en")) {
+			val_ptr[11] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellow_pcpremark_en")) {
+			val_ptr[12] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellow_deiremark_en")) {
+			val_ptr[13] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellowpri")) {
+			val_ptr[14] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellow_dropprec")) {
+			val_ptr[15] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellowpcp")) {
+			val_ptr[16] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "yellowdei")) {
+			val_ptr[17] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "redaction")) {
+			val_ptr[18] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "red_priremark_en")) {
+			val_ptr[19] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "red_dropprec_remark_en")) {
+			val_ptr[20] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "red_pcpremark_en")) {
+			val_ptr[21] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "red_deiremark_en")) {
+			val_ptr[22] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "redpri")) {
+			val_ptr[23] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "red_dropprec")) {
+			val_ptr[24] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "redpcp")) {
+			val_ptr[25] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "reddei")) {
+			val_ptr[26] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_policer_bypass(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "frame_type")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "bypass_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+#endif
+
+#ifdef IN_SHAPER
+static int
+parse_shaper_porttimeslot(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "timeslot")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_shaper_flowtimeslot(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "timeslot")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_shaper_queuetimeslot(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "timeslot")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_shaper_ipgcompensation(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "ipgcompensation_length")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_shaper_porttoken(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ctoken_negative_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ctokennum")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_shaper_flowtoken(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "flow_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ctoken_negative_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ctokennum")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "etoken_negative_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "etokennum")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_shaper_queuetoken(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "queue_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ctoken_negative_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ctokennum")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "etoken_negative_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "etokennum")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_shaper_portshaper(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "meterunit")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cshaper_en")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cir")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cbs")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "framemode")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_shaper_queueshaper(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "queue_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "coupling_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "meterunit")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cshaper_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cir")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cbs")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "eshaper_en")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "eir")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ebs")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "framemode")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_shaper_flowshaper(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+	switch_ext_p = val->value.ext_val;
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if(!strcmp(ext_value_p->option_name, "flow_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "coupling_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "meterunit")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cshaper_en")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cir")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "cbs")) {
+			val_ptr[5] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "eshaper_en")) {
+			val_ptr[6] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "eir")) {
+			val_ptr[7] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "ebs")) {
+			val_ptr[8] = (char*)ext_value_p->option_value;
+		} else if(!strcmp(ext_value_p->option_name, "framemode")) {
+			val_ptr[9] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_QOS
+static int
+parse_qos(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	#ifndef IN_QOS_MINI
+	if(!strcmp(command_name, "QTxBufSts")) {
+		rv = parse_qos_qtxbufsts(val);
+	} else if(!strcmp(command_name, "QTxBufNr")) {
+		rv = parse_qos_qtxbufnr(val);
+	} else if(!strcmp(command_name, "PtTxBufSts")) {
+		rv = parse_qos_pttxbufsts(val);
+	} else if(!strcmp(command_name, "PtTxBufNr")) {
+		rv = parse_qos_pttxbufnr(val);
+	} else if(!strcmp(command_name, "PtRxBufNr")) {
+		rv = parse_qos_ptrxbufnr(val);
+	} else if(!strcmp(command_name, "PtRedEn")) {
+		rv = parse_qos_ptreden(val);
+	} else if(!strcmp(command_name, "PtMode")) {
+		rv = parse_qos_ptmode(val);
+	} else if(!strcmp(command_name, "PtModePri")) {
+		rv = parse_qos_ptmodepri(val);
+	} else if(!strcmp(command_name, "PtschMode")) {
+		rv = parse_qos_ptschmode(val);
+	} else if(!strcmp(command_name, "PtDefaultSpri")) {
+		rv = parse_qos_ptdefaultspri(val);
+	} else if(!strcmp(command_name, "PtDefaultCpri")) {
+		rv = parse_qos_ptdefaultcpri(val);
+	} else if(!strcmp(command_name, "PtFSpriSts")) {
+		rv = parse_qos_ptfsprists(val);
+	} else if(!strcmp(command_name, "PtFCpriSts")) {
+		rv = parse_qos_ptfcprists(val);
+	} else if(!strcmp(command_name, "PtQuRemark")) {
+		rv = parse_qos_ptquremark(val);
+	} else if (!strcmp(command_name, "Ptgroup")) {
+		rv = parse_qos_ptgroup(val);
+	} else if (!strcmp(command_name, "Ptpriprece")) {
+		rv = parse_qos_ptpri(val);
+	} else if (!strcmp(command_name, "Ptremark")) {
+		rv = parse_qos_ptremark(val);
+	} else if (!strcmp(command_name, "Pcpmap")) {
+		rv = parse_qos_pcpmap(val);
+	} else if (!strcmp(command_name, "Flowmap")) {
+		rv = parse_qos_flowmap(val);
+	} else if (!strcmp(command_name, "Dscpmap")) {
+		rv = parse_qos_dscpmap(val);
+	} else if (!strcmp(command_name, "Qscheduler")) {
+		rv = parse_qos_qscheduler(val);
+	} else if (!strcmp(command_name, "Ringqueue")) {
+		rv = parse_qos_ringqueue(val);
+	} else if (!strcmp(command_name, "Dequeue")) {
+		rv = parse_qos_dequeue(val);
+	} else if (!strcmp(command_name, "Portscheduler")) {
+		rv = parse_qos_portscheduler(val);
+	}
+	#endif
+
+	return rv;
+}
+#endif
+
+#ifdef IN_COSMAP
+static int
+parse_cos(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "Pri2Q")) {
+		rv = parse_cos_mappri2q(val);
+	} else if(!strcmp(command_name, "Pri2Ehq")) {
+		rv = parse_cos_mappri2ehq(val);
+	}
+	#ifndef IN_COSMAP_MINI
+	else if(!strcmp(command_name, "Dscp2Pri")) {
+		rv = parse_cos_mapdscp2pri(val);
+	} else if(!strcmp(command_name, "Dscp2Dp")) {
+		rv = parse_cos_mapdscp2dp(val);
+	} else if(!strcmp(command_name, "Up2Pri")) {
+		rv = parse_cos_mapup2pri(val);
+	} else if(!strcmp(command_name, "Up2Dp")) {
+		rv = parse_cos_mapup2dp(val);
+	} else if(!strcmp(command_name, "Dscp2ehPri")) {
+		rv = parse_cos_mapdscp2ehpri(val);
+	} else if(!strcmp(command_name, "Dscp2ehDp")) {
+		rv = parse_cos_mapdscp2ehdp(val);
+	} else if(!strcmp(command_name, "Up2ehPri")) {
+		rv = parse_cos_mapup2ehpri(val);
+	} else if(!strcmp(command_name, "Up2ehDp")) {
+		rv = parse_cos_mapup2ehdp(val);
+	} else if(!strcmp(command_name, "EgRemark")) {
+		rv = parse_cos_mapegremark(val);
+	}
+	#endif
+
+	return rv;
+}
+#endif
+
+#ifdef IN_RATE
+static int
+parse_rate(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "PortPolicer")) {
+		rv = parse_rate_portpolicer(val);
+	} else if(!strcmp(command_name, "PortShaper")) {
+		rv = parse_rate_portshaper(val);
+	} else if(!strcmp(command_name, "QueueShaper")) {
+		rv = parse_rate_queueshaper(val);
+	} else if(!strcmp(command_name, "AclPolicer")) {
+		rv = parse_rate_aclpolicer(val);
+	} else if(!strcmp(command_name, "PtAddRateByte")) {
+		rv = parse_rate_ptaddratebyte(val);
+	} else if(!strcmp(command_name, "PtGolflowen")) {
+		rv = parse_rate_ptgolflowen(val);
+	} 
+
+	return rv;
+}
+#endif
+
+#ifdef IN_PORTCONTROL
+static int
+parse_port(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "TxHdr")) {
+		rv = parse_port_txhdr(val);
+	} else if(!strcmp(command_name, "RxHdr")) {
+		rv = parse_port_rxhdr(val);
+	} else if(!strcmp(command_name, "HdrType")) {
+		rv = parse_port_hdrtype(val);
+	} 
+	#ifndef IN_PORTCONTROL_MINI
+	else if(!strcmp(command_name, "Duplex")) {
+		rv = parse_port_duplex(val);
+	} else if(!strcmp(command_name, "Speed")) {
+		rv = parse_port_speed(val);
+	} else if(!strcmp(command_name, "AutoAdv")) {
+		rv = parse_port_autoadv(val);
+	} else if(!strcmp(command_name, "AutoNegEnable")) {
+		rv = parse_port_autonegenable(val);
+	} else if(!strcmp(command_name, "AutoNegRestart")) {
+		rv = parse_port_autonegrestart(val);
+	} else if(!strcmp(command_name, "FlowCtrl")) {
+		rv = parse_port_flowctrl(val);
+	} else if(!strcmp(command_name, "FlowCtrlForceMode")) {
+		rv = parse_port_flowctrlforcemode(val);
+	} else if(!strcmp(command_name, "PowerSave")) {
+		rv = parse_port_powersave(val);
+	} else if(!strcmp(command_name, "Hibernate")) {
+		rv = parse_port_hibernate(val);
+	} else if(!strcmp(command_name, "TxMacStatus")) {
+		rv = parse_port_txmacstatus(val);
+	} else if(!strcmp(command_name, "RxMacStatus")) {
+		rv = parse_port_rxmacstatus(val);
+	} else if(!strcmp(command_name, "TxFcStatus")) {
+		rv = parse_port_txfcstatus(val);
+	} else if(!strcmp(command_name, "RxFcStatus")) {
+		rv = parse_port_rxfcstatus(val);
+	} else if(!strcmp(command_name, "BpStatus")) {
+		rv = parse_port_bpstatus(val);
+	} else if(!strcmp(command_name, "LinkForceMode")) {
+		rv = parse_port_linkforcemode(val);
+	} else if(!strcmp(command_name, "MacLoopback")) {
+		rv = parse_port_macloopback(val);
+	} else if(!strcmp(command_name, "CongeDrop")) {
+		rv = parse_port_congedrop(val);
+	} else if(!strcmp(command_name, "RingFcThresh")) {
+		rv = parse_port_ringfcthresh(val);
+	} else if(!strcmp(command_name, "Ieee8023az")) {
+		rv = parse_port_ieee8023az(val);
+	} else if(!strcmp(command_name, "Crossover")) {
+		rv = parse_port_crossover(val);
+	} else if(!strcmp(command_name, "PreferMedium")) {
+		rv = parse_port_prefermedium(val);
+	} else if(!strcmp(command_name, "FiberMode")) {
+		rv = parse_port_fibermode(val);
+	} else if(!strcmp(command_name, "LocalLoopback")) {
+		rv = parse_port_localloopback(val);
+	} else if(!strcmp(command_name, "RemoteLoopback")) {
+		rv = parse_port_remoteloopback(val);
+	} else if(!strcmp(command_name, "MagicFrameMac")) {
+		rv = parse_port_magicframemac(val);
+	} else if(!strcmp(command_name, "Wolstatus")) {
+		rv = parse_port_wolstatus(val);
+	} else if(!strcmp(command_name, "InterfaceMode")) {
+		rv = parse_port_interfacemode(val);
+	} else if(!strcmp(command_name, "InterfaceModeApply")) {
+		rv = parse_port_interfacemodeapply(val);
+	} else if(!strcmp(command_name, "Poweron")) {
+		rv = parse_port_poweron(val);
+	} else if(!strcmp(command_name, "Poweroff")) {
+		rv = parse_port_poweroff(val);
+	} else if(!strcmp(command_name, "Reset")) {
+		rv = parse_port_reset(val);
+	} else if(!strcmp(command_name, "FrameMaxSize")) {
+		rv = parse_port_framemaxsize(val);
+	} else if(!strcmp(command_name, "Mtu")) {
+		rv = parse_port_mtu(val);
+	} else if(!strcmp(command_name, "Mru")) {
+		rv = parse_port_mru(val);
+	} else if(!strcmp(command_name, "Srcfilter")) {
+		rv = parse_port_srcfilter(val);
+	} else if(!strcmp(command_name, "Interface3az")) {
+		rv = parse_port_interface8023az(val);
+	} else if(!strcmp(command_name, "Promiscmode")) {
+		rv = parse_port_promiscmode(val);
+	} else if(!strcmp(command_name, "Eeecfg")) {
+		rv = parse_port_eeecfg(val);
+	}else if(!strcmp(command_name, "Srcfiltercfg")) {
+		rv = parse_port_srcfiltercfg(val);
+	} else if(!strcmp(command_name, "SwitchPortLoopback")) {
+		rv = parse_switch_port_loopback(val);
+	}
+	#endif
+
+	return rv;
+}
+#endif
+
+#ifdef IN_PORTVLAN
+static int
+parse_portvlan(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "Ingress")) {
+		rv = parse_portvlan_ingress(val);
+	} else if(!strcmp(command_name, "Egress")) {
+		rv = parse_portvlan_egress(val);
+	} else if(!strcmp(command_name, "Member")) {
+		rv = parse_portvlan_member(val);
+	} else if(!strcmp(command_name, "ForceVid")) {
+		rv = parse_portvlan_forcevid(val);
+	} else if(!strcmp(command_name, "ForceMode")) {
+		rv = parse_portvlan_forcemode(val);
+	} else if(!strcmp(command_name, "SVlanTPID")) {
+		rv = parse_portvlan_svlantpid(val);
+	} else if(!strcmp(command_name, "DefaultSvid")) {
+		rv = parse_portvlan_defaultsvid(val);
+	} else if(!strcmp(command_name, "DefaultCvid")) {
+		rv = parse_portvlan_defaultcvid(val);
+	} else if (!strcmp(command_name, "GlobalQinQMode")) {
+		rv = parse_portvlan_globalqinqmode(val);
+	} else if (!strcmp(command_name, "PtQinQMode")) {
+		rv = parse_portvlan_ptqinqmode(val);
+#ifdef HPPE
+	} else if (!strcmp(command_name, "InTpid")) {
+		rv = parse_portvlan_intpid(val);
+	} else if (!strcmp(command_name, "EgTpid")) {
+		rv = parse_portvlan_egtpid(val);
+	} else if (!strcmp(command_name, "IngressFilter")) {
+		rv = parse_portvlan_ingressfilter(val);
+	} else if (!strcmp(command_name, "DefaultVlanTag")) {
+		rv = parse_portvlan_defaultvlantag(val);
+	} else if (!strcmp(command_name, "TagPropagation")) {
+		rv = parse_portvlan_tagpropagation(val);
+	} else if (!strcmp(command_name, "TranslationMissAction")) {
+		rv = parse_portvlan_translationmissaction(val);
+#endif
+	} else if (!strcmp(command_name, "EgMode")) {
+		rv = parse_portvlan_egmode(val);
+#ifdef HPPE
+	} else if (!strcmp(command_name, "VsiEgMode")) {
+		rv = parse_portvlan_vsiegmode(val);
+	} else if (!strcmp(command_name, "VsiEgModeEn")) {
+		rv = parse_portvlan_vsiegmodeen(val);
+	} else if (!strcmp(command_name, "Counter")) {
+		rv = parse_portvlan_counter(val);
+	} else if (!strcmp(command_name, "TranslationAdv")) {
+		rv = parse_portvlan_translationadv(val);
+#endif
+	}
+	#ifndef IN_PORTVLAN_MINI
+	else if(!strcmp(command_name, "InVlan")) {
+		rv = parse_portvlan_invlan(val);
+	} else if(!strcmp(command_name, "TlsMode")) {
+		rv = parse_portvlan_tlsmode(val);
+	} else if(!strcmp(command_name, "PriPropagation")) {
+		rv = parse_portvlan_pripropagation(val);
+	} else if(!strcmp(command_name, "VlanPropagation")) {
+		rv = parse_portvlan_vlanpropagation(val);
+	} else if(!strcmp(command_name, "Translation")) {
+		rv = parse_portvlan_translation(val);
+	} else if(!strcmp(command_name, "QinqMode")) {
+		rv = parse_portvlan_qinqmode(val);
+	} else if(!strcmp(command_name, "QinqRole")) {
+		rv = parse_portvlan_qinqrole(val);
+	} else if(!strcmp(command_name, "MacVlanXlt")) {
+		rv = parse_portvlan_macvlanxlt(val);
+	} else if(!strcmp(command_name, "Netiso")) {
+		rv = parse_portvlan_netiso(val);
+	} else if(!strcmp(command_name, "EgBypass")) {
+		rv = parse_portvlan_egbypass(val);
+	} else if(!strcmp(command_name, "Ptvrfid")) {
+		rv = parse_portvlan_ptvrfid(val);
+	} 
+	#endif
+
+	return rv;
+}
+#endif
+
+#ifdef IN_VLAN
+static int
+parse_vlan(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "Entry")) {
+		rv = parse_vlan_entry(val);
+	} else if(!strcmp(command_name, "Member")) {
+		rv = parse_vlan_member(val);
+	}
+	#ifndef IN_VLAN_MINI
+	else if(!strcmp(command_name, "LearnSts")) {
+		rv = parse_vlan_learnsts(val);
+	}
+	#endif
+
+	return rv;
+}
+#endif
+
+#ifdef IN_FDB
+static int
+parse_fdb(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "PortLearn")) {
+		rv = parse_fdb_portlearn(val);
+	}
+	#ifndef IN_FDB_MINI
+	else if(!strcmp(command_name, "Resventry")) {
+		rv = parse_fdb_resventry(val);
+	} else if(!strcmp(command_name, "Entry")) {
+		rv = parse_fdb_entry(val);
+	} else if(!strcmp(command_name, "AgeCtrl")) {
+		rv = parse_fdb_agectrl(val);
+	} else if(!strcmp(command_name, "AgeTime")) {
+		rv = parse_fdb_agetime(val);
+	} else if(!strcmp(command_name, "Vlansmode")) {
+		rv = parse_fdb_vlansmode(val);
+	} else if(!strcmp(command_name, "Ptlearnlimit")) {
+		rv = parse_fdb_ptlearnlimit(val);
+	} else if(!strcmp(command_name, "Ptlearnexceedcmd")) {
+		rv = parse_fdb_ptlearnexceedcmd(val);
+	} else if(!strcmp(command_name, "Learnlimit")) {
+		rv = parse_fdb_learnlimit(val);
+	} else if(!strcmp(command_name, "Learnexceedcmd")) {
+		rv = parse_fdb_learnexceedcmd(val);
+	} else if(!strcmp(command_name, "PtLearnstatic")) {
+		rv = parse_fdb_ptlearnstatic(val);
+	} else if (!strcmp(command_name, "LearnCtrl")) {
+		rv = parse_fdb_learnctrl(val);
+	} else if (!strcmp(command_name, "PtLearnCtrl")) {
+		rv = parse_fdb_ptlearnctrl(val);
+	} else if (!strcmp(command_name, "PtStationMove")) {
+		rv = parse_fdb_ptstationmove(val);
+	} else if (!strcmp(command_name, "PtMacLimitCtrl")) {
+		rv = parse_fdb_ptmaclimitctrl(val);
+	} 
+	#endif
+
+	return rv;
+}
+#endif
+
+#ifdef IN_RSS_HASH
+static int
+parse_rsshash(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if (!strcmp(command_name, "Config")) {
+		rv = parse_rsshash_config(val);
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_IGMP
+static int
+parse_igmp(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "Mode")) {
+		rv = parse_igmp_mode(val);
+	} else if(!strcmp(command_name, "Cmd")) {
+		rv = parse_igmp_cmd(val);
+	} else if(!strcmp(command_name, "PortJoin")) {
+		rv = parse_igmp_portjoin(val);
+	} else if(!strcmp(command_name, "PortLeave")) {
+		rv = parse_igmp_portleave(val);
+	} else if(!strcmp(command_name, "Rp")) {
+		rv = parse_igmp_rp(val);
+	} else if(!strcmp(command_name, "CreateStatus")) {
+		rv = parse_igmp_createstatus(val);
+	} else if(!strcmp(command_name, "Static")) {
+		rv = parse_igmp_static(val);
+	} else if(!strcmp(command_name, "Leaky")) {
+		rv = parse_igmp_leaky(val);
+	} else if(!strcmp(command_name, "Version3")) {
+		rv = parse_igmp_version3(val);
+	} else if(!strcmp(command_name, "Queue")) {
+		rv = parse_igmp_queue(val);
+	} else if(!strcmp(command_name, "Ptlearnlimit")) {
+		rv = parse_igmp_ptlearnlimit(val);
+	} else if(!strcmp(command_name, "Ptlearnexceedcmd")) {
+		rv = parse_igmp_ptlearnexceedcmd(val);
+	} else if(!strcmp(command_name, "Multi")) {
+		rv = parse_igmp_multi(val);
+	} 
+
+	return rv;
+}
+#endif
+
+#ifdef IN_SEC
+static int
+parse_sec(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "Mac")) {
+		rv = parse_sec_mac(val);
+	} else if(!strcmp(command_name, "Ip")) {
+		rv = parse_sec_ip(val);
+	} else if(!strcmp(command_name, "Ip4")) {
+		rv = parse_sec_ip4(val);
+	} else if(!strcmp(command_name, "Ip6")) {
+		rv = parse_sec_ip6(val);
+	} else if(!strcmp(command_name, "Tcp")) {
+		rv = parse_sec_tcp(val);
+	} else if(!strcmp(command_name, "Udp")) {
+		rv = parse_sec_udp(val);
+	} else if(!strcmp(command_name, "Icmp4")) {
+		rv = parse_sec_icmp4(val);
+	} else if(!strcmp(command_name, "Icmp6")) {
+		rv = parse_sec_icmp6(val);
+#ifdef HPPE
+	} else if (!strcmp(command_name, "Expctrl")) {
+		rv = parse_sec_expctrl(val);
+	} else if (!strcmp(command_name, "L3parser")) {
+		rv = parse_sec_l3parser(val);
+	} else if (!strcmp(command_name, "L4parser")) {
+		rv = parse_sec_l4parser(val);
+#endif
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_MISC
+static int
+parse_misc(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "Eapolcmd")) {
+		rv = parse_misc_eapolcmd(val);
+	} else if(!strcmp(command_name, "Eapolstatus")) {
+		rv = parse_misc_eapolstatus(val);
+	} else if(!strcmp(command_name, "CpuPort")) {
+		rv = parse_misc_cpuport(val);
+	} else if(!strcmp(command_name, "PtUnkUcFilter")) {
+		rv = parse_misc_ptunkucfilter(val);
+	} else if(!strcmp(command_name, "PtUnkMcFilter")) {
+		rv = parse_misc_ptunkmcfilter(val);
+	} else if(!strcmp(command_name, "PtBcFilter")) {
+		rv = parse_misc_ptbcfilter(val);
+	}
+	#ifndef IN_MISC_MINI
+	else if(!strcmp(command_name, "CpuVid")) {
+		rv = parse_misc_cpuvid(val);
+	}  else if(!strcmp(command_name, "FrameMaxSize")) {
+		rv = parse_misc_framemaxsize(val);
+	} else if(!strcmp(command_name, "AutoNeg")) {
+		rv = parse_misc_autoneg(val);
+	} else if(!strcmp(command_name, "PppoeCmd")) {
+		rv = parse_misc_pppoecmd(val);
+	} else if(!strcmp(command_name, "Pppoe")) {
+		rv = parse_misc_pppoe(val);
+	} else if(!strcmp(command_name, "PtDhcp")) {
+		rv = parse_misc_ptdhcp(val);
+	} else if(!strcmp(command_name, "Arpcmd")) {
+		rv = parse_misc_arpcmd(val);
+	} else if(!strcmp(command_name, "Rip")) {
+		rv = parse_misc_rip(val);
+	} else if(!strcmp(command_name, "Ptarpreq")) {
+		rv = parse_misc_ptarpreq(val);
+	} else if(!strcmp(command_name, "Ptarpack")) {
+		rv = parse_misc_ptarpack(val);
+	} else if(!strcmp(command_name, "Extendpppoe")) {
+		rv = parse_misc_extendpppoe(val);
+	} else if(!strcmp(command_name, "Pppoeid")) {
+		rv = parse_misc_pppoeid(val);
+	} else if(!strcmp(command_name, "RtdPppoe")) {
+		rv = parse_misc_rtdpppoe(val);
+	} else if(!strcmp(command_name, "GloMacAddr")) {
+		rv = parse_misc_glomacaddr(val);
+	} else if(!strcmp(command_name, "Framecrc")) {
+		rv = parse_misc_framecrc(val);
+	} else if(!strcmp(command_name, "Pppoeen")) {
+		rv = parse_misc_pppoeen(val);
+	}
+	#endif
+
+	return rv;
+}
+#endif
+
+#ifdef IN_IP
+static int
+parse_ip(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+#ifndef IN_IP_MINI
+	if(!strcmp(command_name, "Hostentry")) {
+		rv = parse_ip_hostentry(val);
+	} else if(!strcmp(command_name, "Intfentry")) {
+		rv = parse_ip_intfentry(val);
+	} else if(!strcmp(command_name, "Ptarplearn")) {
+		rv = parse_ip_ptarplearn(val);
+	} else if(!strcmp(command_name, "Arplearn")) {
+		rv = parse_ip_arplearn(val);
+	} else if(!strcmp(command_name, "Ptipsrcguard")) {
+		rv = parse_ip_ptipsrcguard(val);
+	} else if(!strcmp(command_name, "Ptarpsrcguard")) {
+		rv = parse_ip_ptarpsrcguard(val);
+	} else if(!strcmp(command_name, "Routestatus")) {
+		rv = parse_ip_routestatus(val);
+	} else if(!strcmp(command_name, "Ipunksrc")) {
+		rv = parse_ip_ipunksrc(val);
+	} else if(!strcmp(command_name, "Arpunksrc")) {
+		rv = parse_ip_arpunksrc(val);
+	} else if(!strcmp(command_name, "IpAgetime")) {
+		rv = parse_ip_agetime(val);
+	} else if(!strcmp(command_name, "Wcmphashmode")) {
+		rv = parse_ip_wcmphashmode(val);
+	} else if(!strcmp(command_name, "Defaultflowcmd")) {
+		rv = parse_ip_defaultflowcmd(val);
+	} else if(!strcmp(command_name, "Defaultrtflowcmd")) {
+		rv = parse_ip_defaultrtflowcmd(val);
+	} else if(!strcmp(command_name, "HostRoute")) {
+		rv = parse_ip_hostroute(val);
+	} else if(!strcmp(command_name, "DefaultRoute")) {
+		rv = parse_ip_defaultroute(val);
+	} else if(!strcmp(command_name, "Vrfbaseaddr")) {
+		rv = parse_ip_vrfbaseaddr(val);
+	} else if(!strcmp(command_name, "Vrfbasemask")) {
+		rv = parse_ip_vrfbasemask(val);
+	} else if(!strcmp(command_name, "Rfsip4")) {
+		rv = parse_ip_rfsip4(val);
+	} else if(!strcmp(command_name, "Rfsip6")) {
+		rv = parse_ip_rfsip6(val);
+	} else if (!strcmp(command_name, "Vsiarpsg")) {
+		rv = parse_ip_vsiarpsg(val);
+	} else if (!strcmp(command_name, "Vsisg")) {
+		rv = parse_ip_vsisg(val);
+	} else if (!strcmp(command_name, "Portarpsg")) {
+		rv = parse_ip_portarpsg(val);
+	} else if (!strcmp(command_name, "Portsg")) {
+		rv = parse_ip_portsg(val);
+	} else if (!strcmp(command_name, "Pubip")) {
+		rv = parse_ip_pubip(val);
+	} else if (!strcmp(command_name, "Networkroute")) {
+		rv = parse_ip_networkroute(val);
+	} else if (!strcmp(command_name, "Intf")) {
+		rv = parse_ip_intf(val);
+	} else if (!strcmp(command_name, "Vsiintf")) {
+		rv = parse_ip_vsiintf(val);
+	} else if (!strcmp(command_name, "Portintf")) {
+		rv = parse_ip_portintf(val);
+	} else if (!strcmp(command_name, "Nexthop")) {
+		rv = parse_ip_nexthop(val);
+	} else if (!strcmp(command_name, "Portmac")) {
+		rv = parse_ip_portmac(val);
+	} else if (!strcmp(command_name, "Routemiss")) {
+		rv = parse_ip_routemiss(val);
+	} else if (!strcmp(command_name, "Mcmode")) {
+		rv = parse_ip_mcmode(val);
+	} else if (!strcmp(command_name, "Globalctrl")) {
+		rv = parse_ip_globalctrl(val);
+	} else if (!strcmp(command_name, "Hostentry")) {
+		rv = parse_ip_hostentry(val);
+	}
+#endif
+	return rv;
+}
+#endif
+
+#ifdef IN_NAT
+static int
+parse_nat(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "Natentry")) {
+		rv = parse_nat_natentry(val);
+	} else if(!strcmp(command_name, "Naptentry")) {
+		rv = parse_nat_naptentry(val);
+	} else if(!strcmp(command_name, "Flowentry")) {
+		rv = parse_nat_flowentry(val);
+	} else if(!strcmp(command_name, "Flowcookie")) {
+		rv = parse_nat_flowcookie(val);
+	} else if(!strcmp(command_name, "Flowrfs")) {
+		rv = parse_nat_flowrfs(val);
+	} else if(!strcmp(command_name, "Natstatus")) {
+		rv = parse_nat_natstatus(val);
+	} else if(!strcmp(command_name, "Naptstatus")) {
+		rv = parse_nat_naptstatus(val);
+	} else if(!strcmp(command_name, "Nathash")) {
+		rv = parse_nat_nathash(val);
+	} else if(!strcmp(command_name, "Naptmode")) {
+		rv = parse_nat_naptmode(val);
+	} else if(!strcmp(command_name, "Prvbaseaddr")) {
+		rv = parse_nat_prvbaseaddr(val);
+	} else if(!strcmp(command_name, "Prvaddrmode")) {
+		rv = parse_nat_prvaddrmode(val);
+	} else if(!strcmp(command_name, "Pubaddr")) {
+		rv = parse_nat_pubaddr(val);
+	} else if(!strcmp(command_name, "Natunksess")) {
+		rv = parse_nat_natunksess(val);
+	} else if(!strcmp(command_name, "Prvbasemask")) {
+		rv = parse_nat_prvbasemask(val);
+	} else if(!strcmp(command_name, "Global")) {
+		rv = parse_nat_global(val);
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_STP
+static int
+parse_stp(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "PortState")) {
+		rv = parse_stp_portstate(val);
+	} 
+
+	return rv;
+}
+#endif
+
+#ifdef IN_MIRROR
+static int
+parse_mirror(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "AnalyPt")) {
+		rv = parse_mirror_analypt(val);
+	} else if(!strcmp(command_name, "PtIngress")) {
+		rv = parse_mirror_ptingress(val);
+	} else if(!strcmp(command_name, "PtEgress")) {
+		rv = parse_mirror_ptegress(val);
+	} else if (!strcmp(command_name, "AnalyCfg")) {
+		rv = parse_mirror_analycfg(val);
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_LEAKY
+static int
+parse_leaky(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "UcMode")) {
+		rv = parse_leaky_ucmode(val);
+	} else if(!strcmp(command_name, "McMode")) {
+		rv = parse_leaky_mcmode(val);
+	} else if(!strcmp(command_name, "ArpMode")) {
+		rv = parse_leaky_arpmode(val);
+	} else if(!strcmp(command_name, "PtUcMode")) {
+		rv = parse_leaky_ptucmode(val);
+	} else if(!strcmp(command_name, "PtMcMode")) {
+		rv = parse_leaky_ptmcmode(val);
+	} 
+
+	return rv;
+}
+#endif
+
+#ifdef IN_TRUNK
+static int
+parse_trunk(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "Group")) {
+		rv = parse_trunk_group(val);
+	} else if(!strcmp(command_name, "Hashmode")) {
+		rv = parse_trunk_hashmode(val);
+	} else if (!strcmp(command_name, "Failover")) {
+		rv = parse_trunk_failover(val);
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_MIB
+static int
+parse_mib(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "Status")) {
+		rv = parse_mib_status(val);
+	} else if(!strcmp(command_name, "CpuKeep")) {
+		rv = parse_mib_cpukeep(val);
+	} 
+
+	return rv;
+}
+#endif
+
+#ifdef IN_ACL
+static int
+parse_acl(const char *command_name, struct switch_val *val, a_uint32_t dev_id)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "Rule")) {
+		rv = parse_acl_rule(val, dev_id);
+	} else if(!strcmp(command_name, "Udfprofile")) {
+		rv = parse_acl_udfprofile(val);
+	} else if(!strcmp(command_name, "Udf")) {
+		rv = parse_acl_udf(val);
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_FLOW
+static int
+parse_flow(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if (!strcmp(command_name, "Entry")) {
+		rv = parse_flow_entry(val);
+	} else if (!strcmp(command_name, "Status")) {
+		rv = parse_flow_status(val);
+	} else if (!strcmp(command_name, "Agetime")) {
+		rv = parse_flow_age(val);
+	} else if (!strcmp(command_name, "Mgmt")) {
+		rv = parse_flow_mgmt(val);
+	} else if (!strcmp(command_name, "Host")) {
+		rv = parse_flow_host(val);
+	} else if (!strcmp(command_name, "Global")) {
+		rv = parse_flow_global(val);
+	} 
+
+	return rv;
+}
+#endif
+
+#ifdef IN_BM
+static int
+parse_bm(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if (!strcmp(command_name, "Ctrl")) {
+		rv = parse_bm_ctrl(val);
+	} else if (!strcmp(command_name, "Portgroupmap")) {
+		rv = parse_bm_portgroupmap(val);
+	} else if (!strcmp(command_name, "Groupbuff")) {
+		rv = parse_bm_groupbuff(val);
+	} else if (!strcmp(command_name, "Portrsvbuff")) {
+		rv = parse_bm_portrsvbuff(val);
+	} else if (!strcmp(command_name, "Portsthresh")) {
+		rv = parse_bm_portsthresh(val);
+	} else if (!strcmp(command_name, "Portdthresh")) {
+		rv = parse_bm_portdthresh(val);
+	} 
+
+	return rv;
+}
+#endif
+
+#ifdef IN_QM
+static int
+parse_qm(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if (!strcmp(command_name, "Ucastqbase")) {
+		rv = parse_qm_ucastqbase(val);
+	} else if (!strcmp(command_name, "Ucastpriclass")) {
+		rv = parse_qm_ucastpriclass(val);
+	} else if (!strcmp(command_name, "Mcastpriclass")) {
+		rv = parse_qm_mcastpriclass(val);
+	} else if (!strcmp(command_name, "Queue")) {
+		rv = parse_qm_queue(val);
+	} else if (!strcmp(command_name, "Ucasthash")) {
+		rv = parse_qm_ucasthash(val);
+	} else if (!strcmp(command_name, "Ucastdflthash")) {
+		rv = parse_qm_ucastdflthash(val);
+	} else if (!strcmp(command_name, "Mcastcpucode")) {
+		rv = parse_qm_mcastcpucode(val);
+	} else if (!strcmp(command_name, "Acctrl")) {
+		rv = parse_qm_acctrl(val);
+	} else if (!strcmp(command_name, "Acprebuffer")) {
+		rv = parse_qm_acprebuffer(val);
+	} else if (!strcmp(command_name, "Acqgroup")) {
+		rv = parse_qm_acqgroup(val);
+	} else if (!strcmp(command_name, "Acstaticthresh")) {
+		rv = parse_qm_acsthresh(val);
+	} else if (!strcmp(command_name, "Acdynamicthresh")) {
+		rv = parse_qm_acdthresh(val);
+	} else if (!strcmp(command_name, "Acgroupbuff")) {
+		rv = parse_qm_acgbuff(val);
+	} else if (!strcmp(command_name, "Cntctrl")) {
+		rv = parse_qm_cntctrl(val);
+	} else if (!strcmp(command_name, "Cnt")) {
+		rv = parse_qm_cnt(val);
+	} else if (!strcmp(command_name, "Enqueue")) {
+		rv = parse_qm_enqueue(val);
+	} else if (!strcmp(command_name, "Srcprofile")) {
+		rv = parse_qm_srcprofile(val);
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_SERVCODE
+static int
+parse_servcode(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if (!strcmp(command_name, "Config")) {
+		rv = parse_servcode_config(val);
+	} else if (!strcmp(command_name, "Loopcheck")) {
+		rv = parse_servcode_loopcheck(val);
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_CTRLPKT
+static int
+parse_ctrlpkt(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if (!strcmp(command_name, "EthernetType")) {
+		rv = parse_ctrlpkt_ethernettype(val);
+	} else if (!strcmp(command_name, "Rfdb")) {
+		rv = parse_ctrlpkt_rfdb(val);
+	} else if (!strcmp(command_name, "AppProfile")) {
+		rv = parse_ctrlpkt_appprofile(val);
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_POLICER
+static int
+parse_policer(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "Timeslot")) {
+		rv = parse_policer_timeslot(val);
+	} else if(!strcmp(command_name, "Fcscompensation")) {
+		rv = parse_policer_fcscompensation(val);
+	} else if(!strcmp(command_name, "Portentry")) {
+		rv = parse_policer_portentry(val);
+	} else if(!strcmp(command_name, "Aclentry")) {
+		rv = parse_policer_aclentry(val);
+	} else if(!strcmp(command_name, "Bypass")) {
+		rv = parse_policer_bypass(val);
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_SHAPER
+static int
+parse_shaper(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if(!strcmp(command_name, "Porttimeslot")) {
+		rv = parse_shaper_porttimeslot(val);
+	} else if(!strcmp(command_name, "Flowtimeslot")) {
+		rv = parse_shaper_flowtimeslot(val);
+	} else if(!strcmp(command_name, "Queuetimeslot")) {
+		rv = parse_shaper_queuetimeslot(val);
+	} else if(!strcmp(command_name, "Ipgcompensation")) {
+		rv = parse_shaper_ipgcompensation(val);
+	} else if(!strcmp(command_name, "Porttoken")) {
+		rv = parse_shaper_porttoken(val);
+	} else if(!strcmp(command_name, "Flowtoken")) {
+		rv = parse_shaper_flowtoken(val);
+	} else if(!strcmp(command_name, "Queuetoken")) {
+		rv = parse_shaper_queuetoken(val);
+	} else if(!strcmp(command_name, "Portshaper")) {
+		rv = parse_shaper_portshaper(val);
+	} else if(!strcmp(command_name, "Queueshaper")) {
+		rv = parse_shaper_queueshaper(val);
+	} else if(!strcmp(command_name, "Flowshaper")) {
+		rv = parse_shaper_flowshaper(val);
+	}
+
+	return rv;
+}
+#endif
+
+#ifdef IN_VSI
+static int
+parse_vsi_portbasedvsi(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "vsi")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_vsi_vlanbasedvsi(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "port_id")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "svid")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "cvid")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "vsi")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_vsi_learnctrl(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "vsi")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "learn_status")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "learnaction")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_vsi_stationmove(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "vsi")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "stationmove_en")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "stationmove_action")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_vsi_member(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "vsi")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "membership")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "unknown_unicast_membership")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "unknown_multicast_membership")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "broadcast_membership")) {
+			val_ptr[4] = (char*)ext_value_p->option_value;
+		}  else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_vsi(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if (!strcmp(command_name, "Portbasedvsi")) {
+		rv = parse_vsi_portbasedvsi(val);
+	} else if (!strcmp(command_name, "Vlanbasedvsi")) {
+		rv = parse_vsi_vlanbasedvsi(val);
+	} else if (!strcmp(command_name, "Learnctrl")) {
+		rv = parse_vsi_learnctrl(val);
+	} else if (!strcmp(command_name, "Stationmove")) {
+		rv = parse_vsi_stationmove(val);
+	} else if (!strcmp(command_name, "Member")) {
+		rv = parse_vsi_member(val);
+	}
+
+	return rv;
+}
+#endif
+
+static int
+parse_debug_module_func(struct switch_val *val)
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	int rv = 0;
+
+	switch_ext_p = val->value.ext_val;
+	while (switch_ext_p) {
+		ext_value_p = switch_ext_p;
+
+		if (!strcmp(ext_value_p->option_name, "name")) {
+			switch_ext_p = switch_ext_p->next;
+			continue;
+		} else if (!strcmp(ext_value_p->option_name, "module")) {
+			val_ptr[0] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "bitmap0")) {
+			val_ptr[1] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "bitmap1")) {
+			val_ptr[2] = (char*)ext_value_p->option_value;
+		} else if (!strcmp(ext_value_p->option_name, "bitmap2")) {
+			val_ptr[3] = (char*)ext_value_p->option_value;
+		} else {
+			rv = -1;
+			break;
+		}
+
+		parameter_length++;
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	return rv;
+}
+
+static int
+parse_debug(const char *command_name, struct switch_val *val)
+{
+	int rv = -1;
+	if (!strcmp(command_name, "Module_func")) {
+		rv = parse_debug_module_func(val);
+	}
+	return rv;
+}
+
+static int name_transfer(char *name, char *module, char *cmd)
+{
+        char *p;
+        unsigned int i = 0, len = 0;
+
+        p = name + 1;
+        len = strlen(name);
+        for(i=1; i<len; i++) {
+                if(*p>='A'&&*p<='Z')
+			break;
+		p++;
+        }
+
+        if(i<len) {
+		strlcpy(module, name, i+1);
+		strlcpy(cmd, p, COMMAND_NAME_MAX_LEN);
+		return 0;
+        }
+	
+        return -1;
+}
+
+int
+qca_ar8327_sw_switch_ext(struct switch_dev *dev,
+				const struct switch_attr *attr,
+			 	struct switch_val *val) 
+{
+	struct switch_ext *switch_ext_p, *ext_value_p;
+	struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+	unsigned int i = 0;
+	int rv = -1;
+	switch_ext_p = val->value.ext_val;
+
+	memset(whole_command_line, 0, sizeof(whole_command_line));
+	memset(module_name, 0, sizeof(module_name));
+	memset(command_name, 0, sizeof(command_name));
+	while(switch_ext_p) {
+		ext_value_p = switch_ext_p;
+		if(!strcmp(ext_value_p->option_name, "name")) {
+			name_transfer((char*)ext_value_p->option_value, module_name, command_name);
+			SSDK_DEBUG("module_name:%s command_name:%s\n", module_name, command_name);
+			break;
+		}
+		switch_ext_p = switch_ext_p->next;
+	}
+
+	parameter_length = 0;
+
+	if(!strcmp(module_name, "Qos")) {
+#ifdef IN_QOS
+		rv = parse_qos(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Cosmap")) {
+#ifdef IN_COSMAP
+		rv = parse_cos(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Rate")) {
+#ifdef IN_RATE
+		rv = parse_rate(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Port")) {
+#ifdef IN_PORTCONTROL
+		rv = parse_port(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Portvlan")) {
+#ifdef IN_PORTVLAN
+		rv = parse_portvlan(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Vlan")) {
+#ifdef IN_VLAN
+		rv = parse_vlan(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Fdb")) {
+#ifdef IN_FDB
+		rv = parse_fdb(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Rsshash")) {
+#ifdef IN_RSS_HASH
+		rv = parse_rsshash(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Igmp")) {
+#ifdef IN_IGMP
+		rv = parse_igmp(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Sec")) {
+#ifdef IN_SEC
+		rv = parse_sec(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Misc")) {
+#ifdef IN_MISC
+		rv = parse_misc(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Ip")) {
+#ifdef IN_IP
+		rv = parse_ip(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Nat")) {
+#ifdef IN_NAT
+		rv = parse_nat(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Stp")) {
+#ifdef IN_STP
+		rv = parse_stp(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Mirror")) {
+#ifdef IN_MIRROR
+		rv = parse_mirror(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Leaky")) {
+#ifdef IN_LEAKY
+		rv = parse_leaky(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Trunk")) {
+#ifdef IN_TRUNK
+		rv = parse_trunk(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Mib")) {
+#ifdef IN_MIB
+		rv = parse_mib(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Acl")) {
+#ifdef IN_ACL
+		rv = parse_acl(command_name, val, priv->device_id);
+#endif
+	} else if(!strcmp(module_name, "Flow")) {
+#ifdef IN_FLOW
+		rv = parse_flow(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Bm")) {
+#ifdef IN_BM
+		rv = parse_bm(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Qm")) {
+#ifdef IN_QM
+		rv = parse_qm(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Servcode")) {
+#ifdef IN_SERVCODE
+		rv = parse_servcode(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Ctrlpkt")) {
+#ifdef IN_CTRLPKT
+		rv = parse_ctrlpkt(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Policer")) {
+#ifdef IN_POLICER
+		rv = parse_policer(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Shaper")) {
+#ifdef IN_SHAPER
+		rv = parse_shaper(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Vsi")) {
+#ifdef IN_VSI
+		rv = parse_vsi(command_name, val);
+#endif
+	} else if(!strcmp(module_name, "Debug")) {
+		rv = parse_debug(command_name, val);
+	}
+
+	if(!rv) {
+		strlcat(whole_command_line, module_name, sizeof(whole_command_line));
+		strlcat(whole_command_line, " ", sizeof(whole_command_line));
+		strlcat(whole_command_line, command_name, sizeof(whole_command_line));
+		strlcat(whole_command_line, " ", sizeof(whole_command_line));
+		strlcat(whole_command_line, "set", sizeof(whole_command_line));
+		strlcat(whole_command_line, " ", sizeof(whole_command_line));
+		for(i=0; i<parameter_length; i++) {
+			if(val_ptr[i]) {
+				strlcat(whole_command_line, val_ptr[i], sizeof(whole_command_line));
+				strlcat(whole_command_line, " ", sizeof(whole_command_line));
+			}
+
+			val_ptr[i] = NULL;
+		}
+
+		SSDK_DEBUG("command_line:%s\n", whole_command_line);
+
+	}
+	uci_set_devid(priv->device_id);
+	set_talk_mode(0);
+	rv = cmd_run_one(whole_command_line);
+	set_talk_mode(1);
+
+	SSDK_DEBUG("cmd_run_one: ret=%d\r\n", rv);
+
+	return rv;
+}
diff --git a/qca-ssdk/src/ref/ref_vlan.c b/qca-ssdk/src/ref/ref_vlan.c
new file mode 100755
index 0000000..4b99f2c
--- /dev/null
+++ b/qca-ssdk/src/ref/ref_vlan.c
@@ -0,0 +1,562 @@
+/*
+ * Copyright (c) 2012, 2014, 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "ssdk_init.h"
+#include "fal_init.h"
+#include "fal_misc.h"
+#include "fal_mib.h"
+#include "fal_port_ctrl.h"
+#include "fal_portvlan.h"
+#include "fal_fdb.h"
+#include "fal_stp.h"
+#include "fal_igmp.h"
+#include "fal_qos.h"
+#include "fal_acl.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "ssdk_init.h"
+#include "ssdk_dts.h"
+#include "hsl_phy.h"
+#include <linux/kconfig.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+//#include <asm/mach-types.h>
+#include <generated/autoconf.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0))
+#include <linux/ar8216_platform.h>
+#endif
+#include <linux/delay.h>
+#include <linux/phy.h>
+#include <linux/netdevice.h>
+#include "ssdk_plat.h"
+#include "ref_vlan.h"
+#ifdef BOARD_AR71XX
+#include "ssdk_uci.h"
+#endif
+
+
+extern ssdk_chip_type SSDK_CURRENT_CHIP_TYPE;
+
+#if !defined(IN_VLAN_MINI)
+sw_error_t
+qca_lan_wan_cfg_set(a_uint32_t dev_id, qca_lan_wan_cfg_t *lan_wan_cfg)
+{
+	a_uint32_t i = 0, lan_bmp = 0, wan_bmp = 0;
+	sw_error_t rv = SW_OK;
+	fal_vlan_t vlan_entry;
+
+	SW_RTN_ON_NULL(lan_wan_cfg);
+
+	switch (SSDK_CURRENT_CHIP_TYPE) {
+		case CHIP_ISIS:
+		case CHIP_ISISC:
+		case CHIP_DESS:
+			break;
+		default:
+			return SW_NOT_SUPPORTED;
+	}
+
+	fal_vlan_flush(dev_id);
+	aos_mem_set(&vlan_entry, 0, sizeof(vlan_entry));
+
+	if (lan_wan_cfg->lan_only_mode) {
+#if defined(IN_PORTVLAN)
+		while (i < sizeof(lan_wan_cfg->v_port_info)/sizeof(lan_wan_cfg->v_port_info[0])) {
+			if (lan_wan_cfg->v_port_info[i].valid) {
+				/* use the portbased vlan table for forwarding */
+				rv = fal_port_1qmode_set(dev_id,
+						lan_wan_cfg->v_port_info[i].port_id,
+						FAL_1Q_DISABLE);
+				SW_RTN_ON_ERROR(rv);
+				rv = fal_port_egvlanmode_set(dev_id,
+						lan_wan_cfg->v_port_info[i].port_id,
+						FAL_EG_UNMODIFIED);
+				SW_RTN_ON_ERROR(rv);
+				rv = fal_port_default_cvid_set(dev_id,
+						lan_wan_cfg->v_port_info[i].port_id,
+						0);
+				SW_RTN_ON_ERROR(rv);
+				lan_bmp |= (0x1 << lan_wan_cfg->v_port_info[i].port_id);
+			}
+			i++;
+		}
+		/* CPU port 0 configurations */
+		rv = fal_port_1qmode_set(dev_id, SSDK_PORT_CPU, FAL_1Q_DISABLE);
+		SW_RTN_ON_ERROR(rv);
+		rv = fal_port_egvlanmode_set(dev_id, SSDK_PORT_CPU, FAL_EG_UNMODIFIED);
+		SW_RTN_ON_ERROR(rv);
+		rv = fal_port_default_cvid_set(dev_id, SSDK_PORT_CPU, 0);
+		SW_RTN_ON_ERROR(rv);
+		rv = fal_portvlan_member_update(dev_id, SSDK_PORT_CPU, lan_bmp);
+		SW_RTN_ON_ERROR(rv);
+#endif
+	} else {
+		while (i < sizeof(lan_wan_cfg->v_port_info)/sizeof(lan_wan_cfg->v_port_info[0])) {
+			if (lan_wan_cfg->v_port_info[i].valid) {
+				rv = fal_vlan_find(dev_id,
+						lan_wan_cfg->v_port_info[i].vid, &vlan_entry);
+				/* create vlan entry if the vlan entry does not exist */
+				if (rv == SW_NOT_FOUND) {
+					rv = fal_vlan_create(dev_id,
+							lan_wan_cfg->v_port_info[i].vid);
+					SW_RTN_ON_ERROR(rv);
+#if defined(IN_PORTVLAN)
+					rv = fal_port_1qmode_set(dev_id,
+							SSDK_PORT_CPU, FAL_1Q_SECURE);
+					SW_RTN_ON_ERROR(rv);
+#endif
+					rv = fal_vlan_member_add(dev_id,
+							lan_wan_cfg->v_port_info[i].vid,
+							SSDK_PORT_CPU, FAL_EG_TAGGED);
+					SW_RTN_ON_ERROR(rv);
+				}
+				rv = fal_vlan_member_add(dev_id,
+						lan_wan_cfg->v_port_info[i].vid,
+						lan_wan_cfg->v_port_info[i].port_id,
+						FAL_EG_UNTAGGED);
+				SW_RTN_ON_ERROR(rv);
+#if defined(IN_PORTVLAN)
+				rv = fal_port_1qmode_set(dev_id,
+						lan_wan_cfg->v_port_info[i].port_id,
+						FAL_1Q_SECURE);
+				SW_RTN_ON_ERROR(rv);
+
+				rv = fal_port_default_cvid_set(dev_id,
+						lan_wan_cfg->v_port_info[i].port_id,
+						lan_wan_cfg->v_port_info[i].vid);
+				SW_RTN_ON_ERROR(rv);
+#endif
+				if (lan_wan_cfg->v_port_info[i].is_wan_port) {
+					wan_bmp |= (0x1 << lan_wan_cfg->v_port_info[i].port_id);
+				} else {
+					lan_bmp |= (0x1 << lan_wan_cfg->v_port_info[i].port_id);
+				}
+			}
+			i++;
+		}
+	}
+	ssdk_lan_bmp_set(dev_id, lan_bmp);
+	ssdk_wan_bmp_set(dev_id, wan_bmp);
+	qca_ssdk_port_bmp_set(dev_id, lan_bmp|wan_bmp);
+#if defined(DESS) && defined(IN_TRUNK)
+	if(SSDK_CURRENT_CHIP_TYPE == CHIP_DESS) {
+		ssdk_dess_trunk_init(dev_id, wan_bmp);
+	}
+#endif
+#if defined(IN_PORTVLAN)
+	ssdk_portvlan_init(dev_id);
+#endif
+	return rv;
+}
+
+sw_error_t
+qca_lan_wan_cfg_get(a_uint32_t dev_id, qca_lan_wan_cfg_t *lan_wan_cfg)
+{
+	sw_error_t rv = SW_OK;
+	fal_vlan_t vlan_entry;
+	fal_pbmp_t member_pmap, lan_bmp, wan_bmp;
+	a_uint32_t port_id, entry_id, vlan_id;
+
+	SW_RTN_ON_NULL(lan_wan_cfg);
+
+	switch (SSDK_CURRENT_CHIP_TYPE) {
+		case CHIP_ISIS:
+		case CHIP_ISISC:
+		case CHIP_DESS:
+			break;
+		default:
+			return SW_NOT_SUPPORTED;
+	}
+
+	lan_bmp = ssdk_lan_bmp_get(dev_id);
+	wan_bmp = ssdk_wan_bmp_get(dev_id);
+
+	member_pmap = lan_bmp | wan_bmp;
+	vlan_id = FAL_NEXT_ENTRY_FIRST_ID;
+	entry_id = 0;
+
+	while (1) {
+		aos_mem_set(&vlan_entry, 0, sizeof(vlan_entry));
+		rv = fal_vlan_next(dev_id, vlan_id, &vlan_entry);
+		if (rv != SW_OK) {
+			break;
+		}
+
+		/*
+		 * the special port id should be existed only in one vlan entry
+		 * starting from port 1.
+		 */
+		port_id = 1;
+		while (vlan_entry.mem_ports >> port_id) {
+			if (((vlan_entry.mem_ports >> port_id) & 1) &&
+					SW_IS_PBMP_MEMBER(member_pmap, port_id)) {
+				lan_wan_cfg->v_port_info[entry_id].port_id = port_id;
+				lan_wan_cfg->v_port_info[entry_id].vid = vlan_entry.vid;
+				lan_wan_cfg->v_port_info[entry_id].valid = A_TRUE;
+				lan_wan_cfg->v_port_info[entry_id].is_wan_port =
+					SW_IS_PBMP_MEMBER(wan_bmp, port_id) ? A_TRUE : A_FALSE;
+				entry_id++;
+			}
+			port_id++;
+		}
+		vlan_id = vlan_entry.vid;
+	}
+
+	/*
+	 * no vlan entry exists, the portbased vlan used.
+	 */
+#if defined(IN_PORTVLAN)
+	if (entry_id == 0) {
+		lan_wan_cfg->lan_only_mode = A_TRUE;
+		port_id = 1;
+		while (lan_bmp >> port_id) {
+			if ((lan_bmp >> port_id) & 1) {
+				lan_wan_cfg->v_port_info[entry_id].port_id = port_id;
+				lan_wan_cfg->v_port_info[entry_id].vid = 0;
+				lan_wan_cfg->v_port_info[entry_id].is_wan_port = A_FALSE;
+
+				member_pmap = 0;
+#if !defined(IN_PORTVLAN_MINI)
+				fal_portvlan_member_get(dev_id, port_id, &member_pmap);
+#endif
+				lan_wan_cfg->v_port_info[entry_id].valid =
+					member_pmap ? A_TRUE : A_FALSE;
+				entry_id++;
+			}
+			port_id++;
+		}
+	}
+#endif
+	return SW_OK;
+}
+#endif
+
+int
+qca_ar8327_sw_enable_vlan0(a_uint32_t dev_id, a_bool_t enable, a_uint8_t portmap)
+{
+    fal_vlan_t entry;
+    fal_acl_rule_t rule;
+    int i = 0;
+
+    memset(&entry, 0, sizeof(fal_vlan_t));
+    memset(&rule, 0, sizeof(fal_acl_rule_t));
+    for (i = 0; i < AR8327_NUM_PORTS; i ++) {
+        fal_port_tls_set(dev_id, i, A_FALSE);
+        fal_port_vlan_propagation_set(dev_id, i, FAL_VLAN_PROPAGATION_REPLACE);
+    }
+
+    if (enable) {
+        entry.fid = 0;
+        entry.mem_ports = portmap;
+        entry.unmodify_ports = portmap;
+        entry.vid = 0;
+        fal_vlan_entry_append(dev_id, &entry);
+        for (i = 0; i < AR8327_NUM_PORTS; i++) {
+            if (portmap & (0x1 << i)) {
+                fal_port_egvlanmode_set(dev_id, i, FAL_EG_UNTOUCHED);
+                fal_port_tls_set(dev_id, i, A_TRUE);
+                fal_port_vlan_propagation_set(dev_id, i, FAL_VLAN_PROPAGATION_DISABLE);
+                fal_acl_port_udf_profile_set(dev_id, i, FAL_ACL_UDF_TYPE_L2, 12, 4);
+            }
+        }
+
+        fal_acl_list_creat(dev_id, 0, 0);
+        rule.rule_type = FAL_ACL_RULE_UDF;
+        rule.udf_len = 4;
+        rule.udf_val[0] = 0x81;
+        rule.udf_val[1] = 0;
+        rule.udf_val[2] = 0;
+        rule.udf_val[3] = 0;
+        rule.udf_mask[0] = 0xff;
+        rule.udf_mask[1] = 0xff;
+        rule.udf_mask[2] = 0xf;
+        rule.udf_mask[3] = 0xff;
+        FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_UDF);
+        FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID);
+        fal_acl_rule_add(dev_id, 0, 0, 1, &rule);
+        for (i = 0; i < AR8327_NUM_PORTS; i ++) {
+            fal_acl_list_unbind(dev_id, 0, 0, 0, i);
+            if (portmap & (0x1 << i)) {
+                fal_acl_list_bind(dev_id, 0, 0, 0, i);
+            }
+        }
+        fal_acl_status_set(dev_id, A_TRUE);
+    }
+    else {
+        fal_acl_rule_delete(dev_id, 0, 0, 1);
+    }
+
+    return 0;
+}
+
+#if defined(IN_SWCONFIG)
+int
+qca_ar8327_sw_set_vlan(struct switch_dev *dev,
+                       const struct switch_attr *attr,
+                       struct switch_val *val)
+{
+    struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+
+    priv->vlan = !!val->value.i;
+
+    #ifdef BOARD_AR71XX
+    if(SSDK_CURRENT_CHIP_TYPE == CHIP_SHIVA) {
+		ssdk_uci_sw_set_vlan(attr, val);
+    }
+    #endif
+
+    return 0;
+}
+
+int
+qca_ar8327_sw_get_vlan(struct switch_dev *dev,
+                       const struct switch_attr *attr,
+                       struct switch_val *val)
+{
+    struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+
+    val->value.i = priv->vlan;
+
+    return 0;
+}
+
+int
+qca_ar8327_sw_set_vid(struct switch_dev *dev,
+                      const struct switch_attr *attr,
+                      struct switch_val *val)
+{
+    struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+
+    priv->vlan_id[val->port_vlan] = val->value.i;
+
+#ifdef BOARD_AR71XX
+    if(SSDK_CURRENT_CHIP_TYPE == CHIP_SHIVA) {
+		ssdk_uci_sw_set_vid(attr, val);
+    }
+#endif
+
+    return 0;
+}
+
+int
+qca_ar8327_sw_get_vid(struct switch_dev *dev,
+                      const struct switch_attr *attr,
+                      struct switch_val *val)
+{
+    struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+
+    val->value.i = priv->vlan_id[val->port_vlan];
+
+    return 0;
+}
+
+int
+qca_ar8327_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
+{
+    struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+
+    *vlan = priv->pvid[port];
+
+    return 0;
+}
+
+int
+qca_ar8327_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
+{
+    struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+
+    /* make sure no invalid PVIDs get set */
+    if (vlan >= dev->vlans)
+        return -1;
+
+    priv->pvid[port] = vlan;
+
+#ifdef BOARD_AR71XX
+		if(SSDK_CURRENT_CHIP_TYPE == CHIP_SHIVA) {
+			ssdk_uci_sw_set_pvid(port, vlan);
+		}
+#endif
+
+    return 0;
+}
+
+int
+qca_ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
+{
+    struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+    a_uint8_t ports = priv->vlan_table[val->port_vlan];
+    int i;
+
+    val->len = 0;
+    for (i = 0; i < dev->ports; i++) {
+        struct switch_port *p;
+
+        if (!(ports & (1 << i)))
+            continue;
+
+        p = &val->value.ports[val->len++];
+        p->id = i;
+        if (priv->vlan_tagged[val->port_vlan] & (1 << i))
+            p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
+        else
+            p->flags = 0;
+
+        /*Handle for VLAN 0*/
+        if (val->port_vlan == 0)
+            p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
+    }
+
+    return 0;
+}
+
+int
+qca_ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
+{
+    struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+    a_uint8_t *vt = &priv->vlan_table[val->port_vlan];
+    int i;
+
+#ifdef BOARD_AR71XX
+	if(SSDK_CURRENT_CHIP_TYPE == CHIP_SHIVA) {
+		ssdk_uci_sw_set_ports(val);
+	}
+#endif
+
+    /*Handle for VLAN 0*/
+    if (val->port_vlan == 0) {
+        priv->vlan_table[0] = 0;
+        for (i = 0; i < val->len; i++) {
+            struct switch_port *p = &val->value.ports[i];
+            priv->vlan_table[0] |= (1 << p->id);
+        }
+
+        return 0;
+    }
+	if (priv->vlan_id[val->port_vlan] == 0)
+		priv->vlan_id[val->port_vlan] = val->port_vlan;
+    *vt = 0;
+    for (i = 0; i < val->len; i++) {
+        struct switch_port *p = &val->value.ports[i];
+
+        if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
+            priv->vlan_tagged[val->port_vlan] |= (1 << p->id);
+        } else {
+            priv->vlan_tagged[val->port_vlan] &= ~(1 << p->id);
+            priv->pvid[p->id] = val->port_vlan;
+        }
+
+        *vt |= 1 << p->id;
+    }
+
+    return 0;
+}
+
+int
+qca_ar8327_sw_hw_apply(struct switch_dev *dev)
+{
+    struct qca_phy_priv *priv = qca_phy_priv_get(dev);
+    fal_pbmp_t *portmask = NULL;
+    int i, j;
+
+    if (priv->version == QCA_VER_HPPE) {
+        return 0;
+    }
+
+    portmask = aos_mem_alloc(sizeof(fal_pbmp_t) * dev->ports);
+    if (portmask == NULL) {
+        SSDK_ERROR("%s: portmask malloc failed. \n", __func__);
+        return -1;
+    }
+    memset(portmask, 0, sizeof(fal_pbmp_t) * dev->ports);
+
+    mutex_lock(&priv->reg_mutex);
+
+    if (!priv->init) {
+        /*Handle VLAN 0 entry*/
+        if (priv->vlan_id[0] == 0 && priv->vlan_table[0] == 0) {
+            qca_ar8327_sw_enable_vlan0(priv->device_id, A_FALSE, 0);
+        }
+
+        /* calculate the port destination masks and load vlans
+         * into the vlan translation unit */
+        for (j = 0; j < AR8327_MAX_VLANS; j++) {
+            u8 vp = priv->vlan_table[j];
+
+            if (!vp) {
+                fal_vlan_delete(priv->device_id, priv->vlan_id[j]);
+                continue;
+            }
+            fal_vlan_delete(priv->device_id, priv->vlan_id[j]);
+            fal_vlan_create(priv->device_id, priv->vlan_id[j]);
+
+            for (i = 0; i < dev->ports; i++) {
+                u8 mask = (1 << i);
+                if (vp & mask) {
+                    fal_vlan_member_add(priv->device_id, priv->vlan_id[j], i,
+                           (mask & priv->vlan_tagged[j])? FAL_EG_TAGGED : FAL_EG_UNTAGGED);
+                    portmask[i] |= vp & ~mask;
+                }
+            }
+	    	if (SSDK_CURRENT_CHIP_TYPE == CHIP_SHIVA)
+				fal_vlan_member_update(priv->device_id,priv->vlan_id[j],vp,0);
+        }
+
+        /*Hanlde VLAN 0 entry*/
+        if (priv->vlan_id[0] == 0 && priv->vlan_table[0]) {
+            qca_ar8327_sw_enable_vlan0(priv->device_id,A_TRUE, priv->vlan_table[0]);
+        }
+
+    } else {
+	    /* vlan disabled: port based vlan used */
+	    ssdk_portvlan_init(priv->device_id);
+    }
+
+    /* update the port destination mask registers and tag settings */
+    for (i = 0; i < dev->ports; i++) {
+        int pvid;
+        fal_pt_1qmode_t ingressMode;
+        fal_pt_1q_egmode_t egressMode;
+
+        if (priv->vlan) {
+            pvid = priv->vlan_id[priv->pvid[i]];
+            ingressMode = FAL_1Q_SECURE;
+        } else {
+            pvid = 0;
+            ingressMode = FAL_1Q_DISABLE;
+        }
+        egressMode = FAL_EG_UNTOUCHED;
+
+        fal_port_1qmode_set(priv->device_id, i, ingressMode);
+        fal_port_egvlanmode_set(priv->device_id, i, egressMode);
+        fal_port_default_cvid_set(priv->device_id, i, pvid);
+	if (!priv->init && priv->vlan) {
+		fal_portvlan_member_update(priv->device_id, i, portmask[i]);
+	}
+    }
+
+    aos_mem_free(portmask);
+    portmask = NULL;
+
+    mutex_unlock(&priv->reg_mutex);
+
+    return 0;
+}
+#endif
+
+
diff --git a/qca-ssdk/src/ref/ref_vsi.c b/qca-ssdk/src/ref/ref_vsi.c
new file mode 100755
index 0000000..1c7900d
--- /dev/null
+++ b/qca-ssdk/src/ref/ref_vsi.c
@@ -0,0 +1,494 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "ref_vsi.h"
+#include "ssdk_init.h"
+#include "ssdk_plat.h"
+
+#define PPE_VSI_MAX FAL_VSI_MAX
+#define PPE_VSI_RESERVE_MAX 6
+
+static ref_vsi_t ref_vsi_mapping[SW_MAX_NR_DEV][PPE_VSI_MAX+1] ={{{0, 0, NULL},
+								{0, 0, NULL},
+								{0, 0, NULL}}};
+static a_uint32_t default_port_vsi[PPE_VSI_PPORT_NR] = {0, 1, 2, 3, 4, 5, 6};/*PPORT*/
+
+static aos_lock_t ppe_vlan_vsi_lock[SW_MAX_NR_DEV];
+
+static sw_error_t
+_ppe_vsi_member_init(a_uint32_t dev_id, a_uint32_t vsi_id)
+{
+	fal_vsi_member_t vsi_member;
+
+	aos_mem_zero(&vsi_member, sizeof(vsi_member));
+
+	vsi_member.member_ports = 0x1;
+	vsi_member.umc_ports    = 0x1;
+	vsi_member.uuc_ports    = 0x1;
+	vsi_member.bc_ports     = 0x1;
+
+	fal_vsi_member_set(dev_id, vsi_id, &vsi_member);
+
+	return SW_OK;
+}
+
+static sw_error_t
+_ppe_vsi_member_update(a_uint32_t dev_id, a_uint32_t vsi_id,
+				fal_port_t port_id, a_uint32_t op)
+{
+	sw_error_t rv;
+	fal_vsi_member_t vsi_member;
+
+	rv = fal_vsi_member_get( dev_id, vsi_id, &vsi_member);
+	if( rv != SW_OK )
+		return rv;
+	if( PPE_VSI_DEL == op )
+	{
+		vsi_member.member_ports &= (~(1<<port_id));
+		/*vsi_member.bc_ports &= (~(1<<port_id));
+		vsi_member.umc_ports &= (~(1<<port_id));
+		vsi_member.uuc_ports &= (~(1<<port_id));*/
+	}
+	else if( PPE_VSI_ADD == op )
+	{
+		vsi_member.member_ports |= (1<<port_id);
+		/*vsi_member.bc_ports |= (1<<port_id);
+		vsi_member.umc_ports |= (1<<port_id);
+		vsi_member.uuc_ports |= (1<<port_id);*/
+	}
+	rv = fal_vsi_member_set(dev_id, vsi_id, &vsi_member);
+	if( rv != SW_OK )
+		return rv;
+
+	return SW_OK;
+}
+
+static sw_error_t _ppe_vlan_vsi_mapping_add(a_uint32_t dev_id, fal_port_t port_id,
+					a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id)
+{
+	ref_vlan_info_t *p_vsi_info = NULL;
+	sw_error_t rv;
+
+	rv = fal_port_vlan_vsi_set(dev_id, port_id, stag_vid, ctag_vid, vsi_id);
+	if( rv != SW_OK )
+	{
+		SSDK_ERROR("port %d svlan %d cvlan %d vsi %d set fail, rv = %d\n",
+				port_id, stag_vid, ctag_vid, vsi_id, rv);
+		return rv;
+	}
+	rv = _ppe_vsi_member_update(dev_id, vsi_id, port_id, PPE_VSI_ADD);
+	if( rv != SW_OK )
+	{
+		return rv;
+	}
+
+	/*vlan based vsi update*/
+	p_vsi_info = ref_vsi_mapping[dev_id][vsi_id].pHead;
+	while(p_vsi_info != NULL)
+	{
+		if((stag_vid == p_vsi_info->stag_vid) &&
+			(ctag_vid == p_vsi_info->ctag_vid))
+		{
+			p_vsi_info->vport_bitmap |= 1 << port_id;
+			break;
+		}
+		p_vsi_info = p_vsi_info->pNext;
+	}
+
+	if(p_vsi_info == NULL)/*create a new entry if no match*/
+	{
+		SSDK_DEBUG("port %d svlan %d cvlan %d vsi %d create new entry\n",
+				port_id, stag_vid, ctag_vid, vsi_id);
+		p_vsi_info = aos_mem_alloc(sizeof(ref_vlan_info_t));
+		if(p_vsi_info == NULL)
+		{
+			SSDK_ERROR("port %d svlan %d cvlan %d vsi %d aos_mem_alloc fail\n",
+					port_id, stag_vid, ctag_vid, vsi_id);
+			return SW_NO_RESOURCE;
+		}
+		p_vsi_info->vport_bitmap = 1 << port_id;
+		p_vsi_info->stag_vid = stag_vid;
+		p_vsi_info->ctag_vid = ctag_vid;
+		p_vsi_info->pNext = (ref_vsi_mapping[dev_id][vsi_id].pHead);
+		ref_vsi_mapping[dev_id][vsi_id].pHead = p_vsi_info;
+	}
+
+	return rv;
+}
+
+static sw_error_t _ppe_vlan_vsi_mapping_del(a_uint32_t dev_id, fal_port_t port_id,
+					a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id)
+{
+	ref_vlan_info_t *p_vsi_info = NULL;
+	ref_vlan_info_t *p_prev = NULL;
+	sw_error_t rv;
+	a_bool_t in_vsi = 0;
+
+	rv = fal_port_vlan_vsi_set(dev_id, port_id, stag_vid, ctag_vid, PPE_VSI_INVALID);
+	if( rv != SW_OK )
+	{
+		SSDK_ERROR("port %d svlan %d cvlan %d vsi %d set fail, rv = %d\n",
+				port_id, stag_vid, ctag_vid, vsi_id, rv);
+		return rv;
+	}
+
+	/*vlan based vsi update*/
+	p_vsi_info = ref_vsi_mapping[dev_id][vsi_id].pHead;
+	p_prev = p_vsi_info;
+	while(p_vsi_info != NULL)
+	{
+		if(p_vsi_info->vport_bitmap & (1 << port_id))
+		{
+			if((ctag_vid == p_vsi_info->ctag_vid) &&
+				(stag_vid == p_vsi_info->stag_vid))
+			{
+				/*update software data*/
+				p_vsi_info->vport_bitmap &= (~(1 << port_id));
+				if(p_vsi_info->vport_bitmap == 0)/*free node if bitmap is 0*/
+				{
+					if(p_vsi_info == ref_vsi_mapping[dev_id][vsi_id].pHead)
+					{
+						ref_vsi_mapping[dev_id][vsi_id].pHead =
+								p_vsi_info->pNext;
+					}
+					else
+					{
+						p_prev->pNext = p_vsi_info->pNext;
+					}
+					aos_mem_free(p_vsi_info);
+					p_vsi_info = NULL;
+					break;
+				}
+			}
+			else
+			{
+				in_vsi = 1;/*port + another vlan --> vsi*/
+			}
+		}
+		p_prev = p_vsi_info;
+		p_vsi_info = p_vsi_info->pNext;
+	}
+
+	if(in_vsi == 0 &&
+		(!(1 << port_id & ref_vsi_mapping[dev_id][vsi_id].pport_bitmap)))
+	{
+		rv = _ppe_vsi_member_update(dev_id, vsi_id, port_id, PPE_VSI_DEL);
+		if( rv != SW_OK )
+		{
+			SSDK_ERROR("port %d svlan %d cvlan %d vsi %d fail, rv = %d\n",
+					port_id, stag_vid, ctag_vid, vsi_id, rv);
+			return rv;
+		}
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t _ppe_port_vsi_mapping_update(a_uint32_t dev_id,
+					fal_port_t port_id, a_uint32_t vsi_id)
+{
+	ref_vsi_t *p_vsi = NULL;
+	sw_error_t rv;
+	a_uint32_t i = 0;
+
+
+	if(ref_vsi_mapping[dev_id][vsi_id].valid == 0)
+	{
+		SSDK_ERROR("port %d vsi %d entry not found\n", port_id, vsi_id);
+		return SW_NOT_FOUND;
+	}
+
+	/*check port previous vsi*/
+	for( i = 0; i <= PPE_VSI_MAX; i++ )
+	{
+		p_vsi = &(ref_vsi_mapping[dev_id][i]);
+		if(p_vsi->valid != 0 &&	(p_vsi->pport_bitmap & (1 << port_id)))
+		{
+			/*remmove from preious vsi*/
+			rv = _ppe_vsi_member_update(dev_id, i, port_id, PPE_VSI_DEL);
+			if( rv != SW_OK )
+				return rv;
+			p_vsi->pport_bitmap &= (~(1<<port_id));
+		}
+	}
+	SSDK_DEBUG("port %d, vsi %d set\n", port_id, vsi_id);
+
+	/*port based vsi update*/
+	rv = _ppe_vsi_member_update(dev_id, vsi_id, port_id, PPE_VSI_ADD);
+	if( rv != SW_OK )
+		return rv;
+	ref_vsi_mapping[dev_id][vsi_id].pport_bitmap |= 1 << port_id;
+
+	return SW_OK;
+}
+
+
+sw_error_t
+ppe_port_vlan_vsi_set(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id)
+{
+	sw_error_t rv;
+	a_uint32_t cur_vsi = PPE_VSI_INVALID;
+
+	REF_DEV_ID_CHECK(dev_id);
+
+	SSDK_DEBUG("port %d svlan %d cvlan %d vsi %d \n", 
+			port_id, stag_vid, ctag_vid, vsi_id);
+
+	if((vsi_id != PPE_VSI_INVALID) &&
+		(ref_vsi_mapping[dev_id][vsi_id].valid == 0))
+	{
+		SSDK_ERROR("port %d svlan %d cvlan %d vsi %d entry not found\n",
+				port_id, stag_vid, ctag_vid, vsi_id);
+		return SW_NOT_FOUND;
+	}
+
+	ppe_port_vlan_vsi_get(dev_id, port_id, stag_vid, ctag_vid, &cur_vsi);
+	if(cur_vsi == vsi_id)
+		return SW_OK;
+	aos_lock_bh(&ppe_vlan_vsi_lock[dev_id]);
+	if(PPE_VSI_INVALID == vsi_id || cur_vsi != PPE_VSI_INVALID)
+	{
+		SSDK_DEBUG("Deleting port %d svlan %d cvlan %d vsi %d\n",
+				port_id, stag_vid, ctag_vid, cur_vsi);
+		rv = _ppe_vlan_vsi_mapping_del(dev_id, port_id, stag_vid, ctag_vid, cur_vsi);
+		if( rv != SW_OK )
+		{
+			aos_unlock_bh(&ppe_vlan_vsi_lock[dev_id]);
+			return rv;
+		}
+	}
+
+	if(PPE_VSI_INVALID != vsi_id)
+	{
+		SSDK_DEBUG("Adding port %d svlan %d cvlan %d vsi %d\n",
+				port_id, stag_vid, ctag_vid, vsi_id);
+
+		rv = _ppe_vlan_vsi_mapping_add(dev_id, port_id, stag_vid, ctag_vid, vsi_id);
+	}
+	aos_unlock_bh(&ppe_vlan_vsi_lock[dev_id]);
+	return rv;
+}
+
+sw_error_t ppe_port_vlan_vsi_get(a_uint32_t dev_id, fal_port_t port_id,
+		a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t *vsi_id)
+{
+	ref_vlan_info_t *p_vsi_info = NULL;
+	a_uint32_t i = 0;
+
+	SSDK_DEBUG("Getting port %d svlan %d cvlan %d\n", port_id, stag_vid, ctag_vid);
+
+	REF_DEV_ID_CHECK(dev_id);
+	REF_NULL_POINT_CHECK(vsi_id);
+
+	aos_lock_bh(&ppe_vlan_vsi_lock[dev_id]);
+	for( i = 0; i <= PPE_VSI_MAX; i++ )
+	{
+		p_vsi_info = ref_vsi_mapping[dev_id][i].pHead;
+		while(p_vsi_info != NULL)
+		{
+			if((p_vsi_info->vport_bitmap & (1 << port_id)) &&
+				(ctag_vid== p_vsi_info->ctag_vid) &&
+				(stag_vid== p_vsi_info->stag_vid))
+			{
+				*vsi_id = i;
+				SSDK_DEBUG("Returned port %d svlan %d cvlan %d vsi %d\n",
+						port_id, stag_vid, ctag_vid, *vsi_id);
+				aos_unlock_bh(&ppe_vlan_vsi_lock[dev_id]);
+
+				return SW_OK;
+			}
+			p_vsi_info = p_vsi_info->pNext;
+		}
+	}
+	aos_unlock_bh(&ppe_vlan_vsi_lock[dev_id]);
+	return SW_NOT_FOUND;
+}
+
+
+/*called when
+	1. switchdev create physical interface for port
+	2. add physical interface to a bridge*/
+sw_error_t
+ppe_port_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vsi_id)
+{
+	sw_error_t rv = SW_OK;
+
+	REF_DEV_ID_CHECK(dev_id);
+	SSDK_DEBUG("port %d, vsi %d\n", port_id, vsi_id);
+	if(!(FAL_IS_PPORT(port_id)) && !(FAL_IS_VPORT(port_id)))
+		return SW_BAD_VALUE;
+
+	if(vsi_id > PPE_VSI_MAX){
+		SSDK_ERROR("invalid VSI port %d, vsi %d\n", port_id, vsi_id);
+		return SW_BAD_VALUE;
+	}
+
+	if(FAL_IS_PPORT(port_id)){
+		rv = _ppe_port_vsi_mapping_update(dev_id, FAL_PORT_ID_VALUE(port_id), vsi_id);
+		if( rv != SW_OK )
+			return rv;
+	}
+	return rv;
+}
+
+sw_error_t
+ppe_port_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vsi_id)
+{
+	if(FAL_IS_PPORT(port_id))
+	{
+		a_uint32_t i = 0;
+		for( i = 0; i <= PPE_VSI_MAX; i++ )
+		{
+			if((ref_vsi_mapping[dev_id][i].valid != 0)&&
+				(ref_vsi_mapping[dev_id][i].pport_bitmap & (1 << port_id)))
+			{
+				*vsi_id = i;
+				SSDK_DEBUG("returned port %d, vsi %d\n", port_id, *vsi_id);
+				return SW_OK;
+			}
+		}
+	}
+	SSDK_ERROR("VSI is not configured on port %d\n", port_id);
+	return SW_NOT_FOUND;
+}
+
+sw_error_t ppe_vsi_alloc(a_uint32_t dev_id, a_uint32_t *vsi)
+{
+	a_uint32_t vsi_id;
+
+	REF_DEV_ID_CHECK(dev_id);
+	REF_NULL_POINT_CHECK(vsi);
+	SSDK_DEBUG("requesting vsi\n");
+
+	for( vsi_id = PPE_VSI_RESERVE_MAX+1; vsi_id <= PPE_VSI_MAX; vsi_id++ )
+	{
+		if(ref_vsi_mapping[dev_id][vsi_id].valid == 0)
+		{
+			fal_vsi_newaddr_lrn_t newaddr_lrn;
+			fal_vsi_stamove_t stamove;
+			ref_vsi_mapping[dev_id][vsi_id].valid = 1;
+  			ref_vsi_mapping[dev_id][vsi_id].pport_bitmap = 0;
+  			ref_vsi_mapping[dev_id][vsi_id].pHead = NULL;
+			*vsi = vsi_id;
+			_ppe_vsi_member_init(dev_id, vsi_id);
+			newaddr_lrn.lrn_en = 1;
+			newaddr_lrn.action = 0;
+			fal_vsi_newaddr_lrn_set(dev_id, vsi_id, &newaddr_lrn);
+			stamove.stamove_en = 1;
+			stamove.action = 0;
+			fal_vsi_stamove_set(dev_id, vsi_id, &stamove);
+			SSDK_DEBUG("vsi %d allocated\n", *vsi);
+			return SW_OK;
+		}
+	}
+
+	return SW_NO_RESOURCE;
+}
+
+sw_error_t ppe_vsi_free(a_uint32_t dev_id, a_uint32_t vsi_id)
+{
+	ref_vlan_info_t *p_vsi_info = NULL;
+	REF_DEV_ID_CHECK(dev_id);
+
+	if( vsi_id <= PPE_VSI_RESERVE_MAX || vsi_id > PPE_VSI_MAX )
+		return SW_OUT_OF_RANGE;
+
+	p_vsi_info = ref_vsi_mapping[dev_id][vsi_id].pHead;
+	while(p_vsi_info != NULL)
+	{
+		ref_vlan_info_t *ptemp = p_vsi_info;
+		p_vsi_info = p_vsi_info->pNext;
+		SSDK_DEBUG("port 0x%x svlan %d cvlan %d, vsi %d free vsi info\n",
+				ptemp->vport_bitmap, ptemp->stag_vid, ptemp->ctag_vid, vsi_id);
+		aos_mem_free(ptemp);
+	}
+	ref_vsi_mapping[dev_id][vsi_id].valid = 0;
+	ref_vsi_mapping[dev_id][vsi_id].pHead = NULL;
+	ref_vsi_mapping[dev_id][vsi_id].pport_bitmap = 0;
+
+	SSDK_DEBUG("vsi %d released\n", vsi_id);
+
+	return SW_OK;
+}
+
+static void ppe_init_one_vsi(a_uint32_t dev_id, a_uint32_t vsi_id)
+{
+	if(ref_vsi_mapping[dev_id][vsi_id].valid == 0)
+	{
+		ref_vsi_mapping[dev_id][vsi_id].valid = 1;
+		ref_vsi_mapping[dev_id][vsi_id].pport_bitmap = 0;
+		ref_vsi_mapping[dev_id][vsi_id].pHead = NULL;
+		_ppe_vsi_member_init(dev_id, vsi_id);
+	}
+
+	return;
+}
+
+sw_error_t ppe_vsi_init(a_uint32_t dev_id)
+{
+	fal_port_t port_id;
+	fal_vsi_newaddr_lrn_t newaddr_lrn = {0};
+	fal_vsi_stamove_t stamove = {0};
+
+	newaddr_lrn.action = 0;
+	newaddr_lrn.lrn_en = 1;
+	stamove.action = 0;
+	stamove.stamove_en = 1;
+	for(port_id = SSDK_PHYSICAL_PORT1; port_id <= SSDK_PHYSICAL_PORT7; port_id++)
+	{
+		ppe_init_one_vsi(dev_id, default_port_vsi[port_id-1]);
+		fal_vsi_newaddr_lrn_set(dev_id, default_port_vsi[port_id-1], &newaddr_lrn);
+		fal_vsi_stamove_set(dev_id, default_port_vsi[port_id-1], &stamove);
+		/*fal_port_vsi_set(0, port_id, default_port_vsi[port_id-1]);*/
+		ppe_port_vsi_set(dev_id, port_id, default_port_vsi[port_id-1]);
+	}
+
+	aos_lock_init(&ppe_vlan_vsi_lock[dev_id]);
+
+	return SW_OK;
+}
+
+
+sw_error_t ppe_vsi_tbl_dump(a_uint32_t dev_id)
+{
+	a_uint32_t vsi_id;
+	ref_vlan_info_t *p_vsi_info = NULL;
+
+	REF_DEV_ID_CHECK(dev_id);
+	printk("########Software VSI mapping table\n");
+	for( vsi_id = 0; vsi_id <= PPE_VSI_MAX; vsi_id++ )
+	{
+		if(ref_vsi_mapping[dev_id][vsi_id].valid == 0)
+			continue;
+		p_vsi_info = ref_vsi_mapping[dev_id][vsi_id].pHead;
+		printk("vsi %d, port bitmap 0x%x\n",vsi_id, ref_vsi_mapping[dev_id][vsi_id].pport_bitmap);
+		while(p_vsi_info != NULL)
+		{
+			printk("%8s svlan %d, cvlan %d, port bitmap 0x%x\n","",
+				p_vsi_info->stag_vid, p_vsi_info->ctag_vid, p_vsi_info->vport_bitmap);
+			p_vsi_info = p_vsi_info->pNext;
+		}
+	}
+
+	return SW_OK;
+}
+
+EXPORT_SYMBOL(ppe_port_vlan_vsi_set);
+EXPORT_SYMBOL(ppe_port_vlan_vsi_get);
+EXPORT_SYMBOL(ppe_port_vsi_set);
+EXPORT_SYMBOL(ppe_port_vsi_get);
+EXPORT_SYMBOL(ppe_vsi_alloc);
+EXPORT_SYMBOL(ppe_vsi_free);
+
+
diff --git a/qca-ssdk/src/sal/Makefile b/qca-ssdk/src/sal/Makefile
new file mode 100755
index 0000000..805ae0f
--- /dev/null
+++ b/qca-ssdk/src/sal/Makefile
@@ -0,0 +1,12 @@
+LOC_DIR=src/sal
+LIB=SAL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=$(wildcard *.c)
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/sal/sd/Makefile b/qca-ssdk/src/sal/sd/Makefile
new file mode 100755
index 0000000..74c50e2
--- /dev/null
+++ b/qca-ssdk/src/sal/sd/Makefile
@@ -0,0 +1,12 @@
+LOC_DIR=src/sal/sd
+LIB=SAL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=$(wildcard *.c)
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/qca-ssdk/src/sal/sd/linux/Makefile b/qca-ssdk/src/sal/sd/linux/Makefile
new file mode 100755
index 0000000..a038efc
--- /dev/null
+++ b/qca-ssdk/src/sal/sd/linux/Makefile
@@ -0,0 +1,12 @@
+LOC_DIR=src/sal/sd/linux
+LIB=SAL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=$(wildcard *.c)
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/qca-ssdk/src/sal/sd/linux/uk_interface/Makefile b/qca-ssdk/src/sal/sd/linux/uk_interface/Makefile
new file mode 100755
index 0000000..a4bac32
--- /dev/null
+++ b/qca-ssdk/src/sal/sd/linux/uk_interface/Makefile
@@ -0,0 +1,34 @@
+LOC_DIR=src/sal/sd/linux/uk_interface
+LIB=SAL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=
+
+ifeq (TRUE, $(UK_IF))
+ifeq (KSLIB, $(MODULE_TYPE))
+  ifeq (TRUE, $(UK_NETLINK)) 
+    SRC_LIST=sw_api_ks_netlink.c
+  endif
+
+  ifeq (TRUE, $(UK_IOCTL)) 
+    SRC_LIST=sw_api_ks_ioctl.c
+  endif
+endif
+
+ifeq (USLIB, $(MODULE_TYPE))
+  ifeq (TRUE, $(UK_NETLINK)) 
+    SRC_LIST=sw_api_us_netlink.c
+  endif
+
+  ifeq (TRUE, $(UK_IOCTL)) 
+    SRC_LIST=sw_api_us_ioctl.c
+  endif
+endif
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/qca-ssdk/src/sal/sd/linux/uk_interface/sw_api_ks_ioctl.c b/qca-ssdk/src/sal/sd/linux/uk_interface/sw_api_ks_ioctl.c
new file mode 100755
index 0000000..c40e868
--- /dev/null
+++ b/qca-ssdk/src/sal/sd/linux/uk_interface/sw_api_ks_ioctl.c
@@ -0,0 +1,496 @@
+/*
+ * Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#include "sw.h"
+#include "sw_api.h"
+
+#ifdef KVER26 /*Linux Kernel 2.6 */
+#define __USER     __user
+#else /*Linux Kernel 2.4 */
+#include <asm/uaccess.h>
+#define __USER
+#endif /*KVER26 */
+
+#ifdef KVER34
+#include <generated/autoconf.h>
+#include <linux/fs.h>
+#include <linux/export.h>
+#else
+#include <linux/fs.h>
+#include <linux/export.h>
+//#include <net/sock.h>
+#endif
+
+#include <linux/kconfig.h>
+#include <linux/skbuff.h>
+#include <linux/miscdevice.h>
+#include "api_access.h"
+#include "sw_api_ks.h"
+#ifdef KVER32
+#include <asm/uaccess.h>
+#include <linux/module.h>
+#endif
+#include <linux/mutex.h>
+#include "ssdk_init.h"
+#include "ssdk_plat.h"
+
+static int
+switch_open(struct inode * inode,struct file * file);
+
+static int
+switch_close(struct inode * inode, struct file * file);
+
+
+#ifdef KVER32      //for linux3.2
+static long
+switch_ioctl(struct file * file, unsigned int cmd, unsigned long arg);
+#else
+static long
+switch_ioctl(struct inode *inode, struct file * file, unsigned int cmd, unsigned long arg);
+#endif
+
+#ifdef CONFIG_COMPAT
+static long
+switch_compat_ioctl(struct file * file, unsigned int cmd, unsigned long arg);
+#endif
+
+static unsigned long *cmd_buf = NULL;
+
+static struct mutex api_ioctl_lock;
+
+static struct file_operations switch_device_fops =
+{
+    .owner   = THIS_MODULE,
+    .read    = NULL,
+    .write   = NULL,
+    .poll    = NULL,
+    .unlocked_ioctl = switch_ioctl,
+#ifdef CONFIG_COMPAT
+    .compat_ioctl = switch_compat_ioctl,
+#endif
+    .open    = switch_open,
+    .release = switch_close
+};
+
+#ifndef SHELL_DEV
+#define SHELL_DEV "switch_ssdk"
+#endif
+static struct miscdevice switch_device =
+{
+    .minor	= MISC_DYNAMIC_MINOR,
+    .name	= SHELL_DEV,
+    .fops	= &switch_device_fops,
+};
+
+static sw_error_t
+input_parser(sw_api_param_t *p, a_uint32_t nr_param, unsigned long *args)
+{
+    a_uint32_t i = 0, buf_head = nr_param;
+    a_uint32_t offset = sizeof(unsigned long);
+    a_uint32_t credit = sizeof(unsigned long) - 1;
+
+    for (i = 0; i < nr_param; i++)
+    {
+        if (p->param_type & SW_PARAM_PTR)
+        {
+            cmd_buf[i] = (unsigned long) & cmd_buf[buf_head];
+            buf_head += (p->data_size + credit) / offset;
+
+            if (buf_head > (SW_MAX_API_BUF / offset))
+            {
+                SSDK_ERROR("Lengh of command is more than cmd buffer\n");
+                return SW_NO_RESOURCE;
+            }
+
+            if (p->param_type & SW_PARAM_IN)
+            {
+                if (copy_from_user((a_uint8_t*)(cmd_buf[i]), (void __USER *)args[i + 2],
+				((p->data_size + credit) / offset) * offset))
+                {
+                    SSDK_ERROR("copy_from_user fail\n");
+                    return SW_NO_RESOURCE;
+                }
+                SSDK_DEBUG("Input parameter %d: ", i);
+                SSDK_DUMP_BUF(DEBUG, (unsigned long *)cmd_buf[i],
+                                        ((p->data_size + credit) / offset));
+            }
+        }
+        else
+        {
+            cmd_buf[i] = args[i + 2];
+            SSDK_DEBUG("Input parameter %d: %ld\n", i, cmd_buf[i]);
+        }
+        p++;
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+output_parser(sw_api_param_t *p, a_uint32_t nr_param, unsigned long *args)
+{
+    a_uint32_t i =0;
+    a_uint32_t offset = sizeof(unsigned long);
+    a_uint32_t credit = sizeof(unsigned long) - 1;
+
+    for (i = 0; i < nr_param; i++)
+    {
+        if (p->param_type & SW_PARAM_OUT)
+        {
+            SSDK_DEBUG("Output parameter %d: ", i);
+            SSDK_DUMP_BUF(DEBUG, (unsigned long *)cmd_buf[i],
+				((p->data_size + credit) / offset));
+            if (copy_to_user((void __USER *) args[i + 2], (unsigned long *) cmd_buf[i],
+				((p->data_size + credit) / offset) * offset))
+            {
+                SSDK_ERROR("copy_to_user fail\n");
+                return SW_NO_RESOURCE;
+            }
+        }
+        p++;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+sw_api_cmd(unsigned long * args)
+{
+    unsigned long *p = cmd_buf, api_id = args[0], nr_param = 0;
+    sw_error_t(*func) (unsigned long, ...);
+    sw_api_param_t *pp;
+    sw_api_func_t *fp;
+    sw_error_t rv;
+    sw_api_t sw_api;
+
+    SSDK_DEBUG("api_id is %ld\n", api_id);
+    sw_api.api_id = api_id;
+    rv = sw_api_get(&sw_api);
+    SW_OUT_ON_ERROR(rv);
+
+    fp = sw_api.api_fp;
+    pp = sw_api.api_pp;
+    nr_param = sw_api.api_nr;
+
+	/* Clean up cmd_buf */
+	aos_mem_set(cmd_buf, 0, SW_MAX_API_BUF);
+    rv = input_parser(pp, nr_param, args);
+    SW_OUT_ON_ERROR(rv);
+    func = fp->func;
+
+    switch (nr_param)
+    {
+        case 1:
+            rv = (func) (p[0]);
+            break;
+        case 2:
+            rv = (func) (p[0], p[1]);
+            break;
+        case 3:
+            rv = (func) (p[0], p[1], p[2]);
+            break;
+        case 4:
+            rv = (func) (p[0], p[1], p[2], p[3]);
+            break;
+        case 5:
+            rv = (func) (p[0], p[1], p[2], p[3], p[4]);
+            break;
+        case 6:
+            rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5]);
+            break;
+        case 7:
+            rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6]);
+            break;
+        case 8:
+            rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+            break;
+        case 9:
+            rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]);
+            break;
+        case 10:
+            rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5],
+                         p[6], p[7], p[8], p[9]);
+            break;
+        default:
+            rv = SW_OUT_OF_RANGE;
+    }
+
+    SW_OUT_ON_ERROR(rv);
+    rv = output_parser(pp, nr_param, args);
+
+out:
+    return rv;
+}
+
+static int
+switch_open(struct inode * inode,struct file * file)
+{
+    return SW_OK;
+}
+
+static int
+switch_close(struct inode * inode, struct file * file)
+{
+    return SW_OK;
+}
+
+#ifdef KVER32
+static long
+switch_ioctl(struct file * file, unsigned int cmd, unsigned long arg)
+#else
+static long
+switch_ioctl(struct inode *inode, struct file * file, unsigned int cmd, unsigned long arg)
+#endif
+{
+    unsigned long args[SW_MAX_API_PARAM], rtn;
+    sw_error_t rv = SW_NO_RESOURCE;
+    void __user *argp = (void __user *)arg;
+
+    SSDK_DEBUG("Recieved IOCTL call\n");
+    if (copy_from_user(args, argp, sizeof (args)))
+    {
+        SSDK_ERROR("copy_from_user fail\n");
+        return SW_NO_RESOURCE;
+    }
+
+    mutex_lock(&api_ioctl_lock);
+    rv = sw_api_cmd(args);
+    mutex_unlock(&api_ioctl_lock);
+
+    /* return API result to user */
+    rtn = (unsigned long) rv;
+    if (copy_to_user
+            ((void __USER *) args[1],  &rtn, sizeof (unsigned long)))
+    {
+        SSDK_ERROR("copy_to_user fail\n");
+        rv = SW_NO_RESOURCE;
+    }
+
+    return SW_OK;
+}
+
+#ifdef CONFIG_COMPAT
+static sw_error_t
+input_compat_parser(sw_api_param_t *p, a_uint32_t nr_param, compat_ulong_t *args)
+{
+	a_uint32_t i = 0, buf_head = nr_param;
+	a_uint32_t offset = sizeof(unsigned long);
+	a_uint32_t credit = sizeof(unsigned long) - 1;
+
+	for (i = 0; i < nr_param; i++)
+	{
+		if (p->param_type & SW_PARAM_PTR)
+		{
+			cmd_buf[i] = (unsigned long) & cmd_buf[buf_head];
+			buf_head += (p->data_size + credit) / offset;
+
+			if (buf_head > (SW_MAX_API_BUF / offset))
+			{
+				SSDK_ERROR("Lengh of command is more than cmd buffer\n");
+				return SW_NO_RESOURCE;
+			}
+
+			if (p->param_type & SW_PARAM_IN)
+			{
+				if (copy_from_user((a_uint8_t*)(cmd_buf[i]),
+							(void __USER *)compat_ptr(args[i + 2]),
+							((p->data_size + credit) / offset) * offset))
+				{
+					SSDK_ERROR("copy_from_user fail\n");
+					return SW_NO_RESOURCE;
+				}
+				SSDK_DEBUG("Input parameter %d: ", i);
+				SSDK_DUMP_BUF(DEBUG, (unsigned long *)cmd_buf[i],
+						((p->data_size + credit) / offset));
+			}
+		}
+		else
+		{
+			cmd_buf[i] = args[i + 2];
+			SSDK_DEBUG("Input parameter %d: %ld\n", i, cmd_buf[i]);
+		}
+		p++;
+	}
+	return SW_OK;
+}
+
+static sw_error_t
+output_compat_parser(sw_api_param_t *p, a_uint32_t nr_param, compat_ulong_t *args)
+{
+	a_uint32_t i =0;
+	a_uint32_t offset = sizeof(unsigned long);
+	a_uint32_t credit = sizeof(unsigned long) - 1;
+
+	for (i = 0; i < nr_param; i++)
+	{
+		if (p->param_type & SW_PARAM_OUT)
+		{
+			SSDK_DEBUG("Output parameter %d: ", i);
+			SSDK_DUMP_BUF(DEBUG, (unsigned long *)cmd_buf[i],
+					((p->data_size + credit) / offset));
+			if (copy_to_user((void __USER *) compat_ptr(args[i + 2]),
+						(unsigned long *) cmd_buf[i],
+						((p->data_size + credit) / offset) * offset))
+			{
+				SSDK_ERROR("copy_to_user fail\n");
+				return SW_NO_RESOURCE;
+			}
+		}
+		p++;
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+sw_api_compat_cmd(compat_ulong_t * args)
+{
+	unsigned long *p = cmd_buf, api_id = args[0], nr_param = 0;
+	sw_error_t(*func) (unsigned long, ...);
+	sw_api_param_t *pp;
+	sw_api_func_t *fp;
+	sw_error_t rv;
+	sw_api_t sw_api;
+
+	SSDK_DEBUG("api_id is %ld\n", api_id);
+	sw_api.api_id = api_id;
+	rv = sw_api_get(&sw_api);
+	SW_OUT_ON_ERROR(rv);
+
+	fp = sw_api.api_fp;
+	pp = sw_api.api_pp;
+	nr_param = sw_api.api_nr;
+
+	/* Clean up cmd_buf */
+	aos_mem_set(cmd_buf, 0, SW_MAX_API_BUF);
+	rv = input_compat_parser(pp, nr_param, args);
+	SW_OUT_ON_ERROR(rv);
+	func = fp->func;
+
+	switch (nr_param)
+	{
+		case 1:
+			rv = (func) (p[0]);
+			break;
+		case 2:
+			rv = (func) (p[0], p[1]);
+			break;
+		case 3:
+			rv = (func) (p[0], p[1], p[2]);
+			break;
+		case 4:
+			rv = (func) (p[0], p[1], p[2], p[3]);
+			break;
+		case 5:
+			rv = (func) (p[0], p[1], p[2], p[3], p[4]);
+			break;
+		case 6:
+			rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5]);
+			break;
+		case 7:
+			rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6]);
+			break;
+		case 8:
+			rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+			break;
+		case 9:
+			rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]);
+			break;
+		case 10:
+			rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5],
+					p[6], p[7], p[8], p[9]);
+			break;
+		default:
+			rv = SW_OUT_OF_RANGE;
+	}
+
+	SW_OUT_ON_ERROR(rv);
+	rv = output_compat_parser(pp, nr_param, args);
+
+out:
+	return rv;
+}
+
+static long
+switch_compat_ioctl(struct file * file, unsigned int cmd, unsigned long arg)
+{
+	a_uint32_t args[SW_MAX_API_PARAM], rtn;
+	sw_error_t rv = SW_NO_RESOURCE;
+
+	SSDK_DEBUG("Recieved IOCTL call\n");
+	if (copy_from_user(args,  compat_ptr(arg), sizeof (args)))
+	{
+		SSDK_ERROR("copy_from_user fail\n");
+		return SW_NO_RESOURCE;
+	}
+
+	mutex_lock(&api_ioctl_lock);
+	rv = sw_api_compat_cmd(args);
+	mutex_unlock(&api_ioctl_lock);
+
+	/* return API result to user */
+	rtn = (unsigned long) rv;
+	if (copy_to_user
+			((void __USER *) compat_ptr(args[1]),  &rtn, sizeof (unsigned long)))
+	{
+		SSDK_ERROR("copy_to_user fail\n");
+		rv = SW_NO_RESOURCE;
+	}
+
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+sw_uk_init(a_uint32_t nl_prot)
+{
+    if (!cmd_buf)
+    {
+        if((cmd_buf = (unsigned long *) aos_mem_alloc(SW_MAX_API_BUF)) == NULL)
+        {
+            return SW_OUT_OF_MEM;
+        }
+
+#if defined UK_MINOR_DEV
+        switch_device.minor = UK_MINOR_DEV;
+#else
+        switch_device.minor = nl_prot;
+#endif
+
+        if (misc_register(&switch_device))
+        {
+            return SW_INIT_ERROR;
+        }
+
+        mutex_init(&api_ioctl_lock);
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+sw_uk_cleanup(void)
+{
+    if (cmd_buf)
+    {
+        aos_mem_free(cmd_buf);
+        cmd_buf = NULL;
+
+        mutex_destroy(&api_ioctl_lock);
+        misc_deregister(&switch_device);
+    }
+
+    return SW_OK;
+}
+
diff --git a/qca-ssdk/src/sal/sd/linux/uk_interface/sw_api_ks_netlink.c b/qca-ssdk/src/sal/sd/linux/uk_interface/sw_api_ks_netlink.c
new file mode 100755
index 0000000..3ad5da1
--- /dev/null
+++ b/qca-ssdk/src/sal/sd/linux/uk_interface/sw_api_ks_netlink.c
@@ -0,0 +1,789 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#include "sw.h"
+#include "sw_api.h"
+
+#ifdef KVER26 /*Linux Kernel 2.6 */
+#define __USER     __user
+#else /*Linux Kernel 2.4 */
+#include <asm/uaccess.h>
+#define __USER
+#define CLONE_KERNEL    (CLONE_FS | CLONE_FILES | CLONE_SIGHAND)
+#define for_each_process(p) for_each_task(p)
+#endif /*KVER26 */
+#include <net/sock.h>
+#include <linux/skbuff.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include "api_access.h"
+#include "sw_api_ks.h"
+
+#if 0
+#define dprintk(args...) aos_printk(args)
+#else
+#define dprintk(args...)
+#endif
+
+/*configurable value for max creating request of kernel thread*/
+#define PID_THREADS_MAX  32
+
+#define RSV_PID_LOC_0 (0)
+#define RSV_PID_LOC_1 (1)
+
+#define PID_TAB_MAX         PID_THREADS_MAX
+#define PID_TAB_NOT_FOUND   PID_TAB_MAX+1
+
+static pid_t pid_parents[PID_TAB_MAX] = {0};
+static pid_t pid_childs[PID_TAB_MAX] = {0};
+static wait_queue_head_t pid_child_wait[PID_TAB_MAX];
+static struct semaphore pid_tab_sem;
+
+static unsigned long *cmd_buf = NULL;
+static struct semaphore api_sem;
+static struct sock *ssdk_nl_sk = NULL;
+static struct sk_buff * skb_array[PID_TAB_MAX] = {0};
+
+static sw_error_t
+input_parser(sw_api_param_t *p, a_uint32_t nr_param, a_uint32_t *args)
+{
+    a_uint32_t i = 0, buf_head = nr_param;
+
+    for (i = 0; i < nr_param; i++)
+    {
+        if (p->param_type & SW_PARAM_PTR)
+        {
+            cmd_buf[i] = (a_uint32_t) & cmd_buf[buf_head];
+            buf_head += (p->data_size + 3) / 4;
+
+            if (buf_head > (SW_MAX_API_BUF / 4))
+                return SW_NO_RESOURCE;
+
+            if (p->param_type & SW_PARAM_IN)
+            {
+                if (copy_from_user((a_uint8_t*)(cmd_buf[i]), (void __USER *)args[i + 2], ((p->data_size + 3) >> 2) << 2))
+                    return SW_NO_RESOURCE;
+            }
+        }
+        else
+        {
+            cmd_buf[i] = args[i + 2];
+        }
+        p++;
+    }
+    return SW_OK;
+}
+
+static sw_error_t
+output_parser(sw_api_param_t *p, a_uint32_t nr_param, a_uint32_t *args)
+{
+    a_uint32_t i =0;
+
+    for (i = 0; i < nr_param; i++)
+    {
+        if (p->param_type & SW_PARAM_OUT)
+        {
+            if (copy_to_user
+                    ((void __USER *) args[i + 2], (a_uint32_t *) cmd_buf[i], ((p->data_size + 3) >> 2) << 2))
+                return SW_NO_RESOURCE;
+        }
+        p++;
+    }
+
+    return SW_OK;
+}
+
+static sw_error_t
+sw_api_cmd(a_uint32_t * args)
+{
+    a_uint32_t *p = cmd_buf, api_id = args[0], nr_param = 0;
+    sw_error_t(*func) (a_uint32_t, ...);
+    sw_api_param_t *pp;
+    sw_api_func_t *fp;
+    sw_error_t rv;
+    sw_api_t sw_api;
+
+    down(&api_sem);
+
+    sw_api.api_id = api_id;
+    rv = sw_api_get(&sw_api);
+    SW_OUT_ON_ERROR(rv);
+
+    fp = sw_api.api_fp;
+    pp = sw_api.api_pp;
+    nr_param = sw_api.api_nr;
+
+    rv = input_parser(pp, nr_param, args);
+    SW_OUT_ON_ERROR(rv);
+    func = fp->func;
+
+    switch (nr_param)
+    {
+        case 1:
+            rv = (func) (p[0]);
+            break;
+        case 2:
+            rv = (func) (p[0], p[1]);
+            break;
+        case 3:
+            rv = (func) (p[0], p[1], p[2]);
+            break;
+        case 4:
+            rv = (func) (p[0], p[1], p[2], p[3]);
+            break;
+        case 5:
+            rv = (func) (p[0], p[1], p[2], p[3], p[4]);
+            break;
+        case 6:
+            rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5]);
+            break;
+        case 7:
+            rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6]);
+            break;
+        case 8:
+            rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+            break;
+        case 9:
+            rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]);
+            break;
+        case 10:
+            rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5],
+                         p[6], p[7], p[8], p[9]);
+            break;
+        default:
+            rv = SW_OUT_OF_RANGE;
+    }
+
+    SW_OUT_ON_ERROR(rv);
+    rv = output_parser(pp, nr_param, args);
+
+out:
+    up(&api_sem);
+    return rv;
+}
+
+static inline int pid_find(pid_t pid, pid_t pids[])
+{
+    a_uint32_t i, loc = PID_TAB_NOT_FOUND;
+
+    for(i = 0; i< PID_TAB_MAX; i++)
+    {
+        if(pids[i] == pid)
+        {
+            loc = i;
+            break;
+        }
+    }
+    return loc;
+}
+
+static inline a_bool_t  pid_exit(pid_t parent_pid)
+{
+    struct task_struct *p;
+    a_bool_t rtn = A_TRUE;
+
+    for_each_process(p)
+    {
+        if(parent_pid == p->pid)
+        {
+            rtn = A_FALSE;
+            break;
+        }
+    }
+
+    return rtn;
+}
+
+static inline void pid_free(a_uint32_t loc)
+{
+    if (down_interruptible(&pid_tab_sem))
+        return;
+
+    pid_childs[loc] = 0;
+    pid_parents[loc] = 0;
+
+    up(&pid_tab_sem);
+}
+
+static inline a_bool_t pid_full(void)
+{
+    return (pid_find(0, pid_parents) == PID_TAB_NOT_FOUND)?A_TRUE:A_FALSE;
+}
+
+static a_uint32_t pid_find_save (pid_t parent_pid, pid_t child_pid)
+{
+    a_uint32_t loc = PID_TAB_NOT_FOUND;
+
+    if(!parent_pid && !child_pid)
+    {
+        dprintk("child and father can't both zero\n");
+        return loc;
+    }
+
+    if (down_interruptible(&pid_tab_sem))
+        return loc;
+
+    if(!parent_pid)
+    {
+        /*find locate by child_pid*/
+        loc = pid_find(child_pid, pid_childs);
+
+    }
+    else
+    {
+        /*find locate by parent_pid*/
+        loc = pid_find(parent_pid, pid_parents);
+
+        if(child_pid)
+        {
+            loc = pid_find(0, pid_parents);
+
+            if(loc != PID_TAB_NOT_FOUND)
+            {
+                pid_childs[loc] = child_pid;
+                pid_parents[loc] = parent_pid;
+            }
+        }
+    }
+
+    up(&pid_tab_sem);
+    return loc;
+}
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)
+static void
+sw_api_excep_ack(struct sock *sk, pid_t pid)
+{
+    sw_error_t rv = SW_NO_RESOURCE;
+    a_uint32_t args[SW_MAX_API_PARAM], rtn;
+    struct sk_buff *skb, *skb_first = NULL;
+    struct nlmsghdr *nlh = NULL;
+
+    while(1)
+    {
+#ifdef KVER26
+        skb = skb_dequeue(&sk->sk_receive_queue);
+#else
+        skb = skb_dequeue(&sk->receive_queue);
+#endif
+        if (!skb)
+        {
+            dprintk("pid error: skb = null\n");
+            return;
+        }
+
+        nlh = (struct nlmsghdr *)skb->data;
+        if (!nlh)
+        {
+            dprintk("pid error: nlh = null\n");
+            return;
+        }
+
+        if(nlh->nlmsg_pid == pid)
+        {
+            break;
+        }
+
+        if(!skb_first)
+        {
+            skb_first = skb;
+        }
+        else if (skb_first == skb)
+        {
+            dprintk("can't found my skb???\n");
+            return;
+        }
+
+#ifdef KVER26
+        skb_queue_tail(&sk->sk_receive_queue, skb);
+#else
+        skb_queue_tail(&sk->receive_queue, skb);
+#endif
+    }
+
+	if(nlh->nlmsg_len < (SW_MAX_PAYLOAD + sizeof(nlmsghdr)))
+	{
+		dprintk("data length is less than %d bytes\n", SW_MAX_PAYLOAD);
+		SW_OUT_ON_ERROR(SW_ABORTED);
+	}
+    aos_mem_copy(args, NLMSG_DATA(nlh), SW_MAX_PAYLOAD);
+    /* return API result to user */
+    rtn = (a_uint32_t) rv;
+    if (copy_to_user
+            ((void __USER *) args[1], (a_uint32_t *) & rtn, sizeof (a_uint32_t)))
+    {
+        rv = SW_NO_RESOURCE;
+    }
+
+    NETLINK_CB(skb).pid = 0;
+    NETLINK_CB(skb).dst_pid = nlh->nlmsg_pid;
+#ifdef KVER26
+    NETLINK_CB(skb).dst_group = 0;
+#else
+    NETLINK_CB(skb).dst_groups = 0;
+#endif
+
+    netlink_unicast(sk, skb, nlh->nlmsg_pid, MSG_DONTWAIT);
+}
+
+static void
+sw_api_exec(struct sock *sk, pid_t pid)
+{
+    sw_error_t rv = SW_NO_RESOURCE;
+    a_uint32_t args[SW_MAX_API_PARAM], rtn;
+    struct sk_buff *skb, *skb_first = NULL;
+    struct nlmsghdr *nlh = NULL;
+
+    while(1)
+    {
+#ifdef KVER26
+        skb = skb_dequeue(&sk->sk_receive_queue);
+#else
+        skb = skb_dequeue(&sk->receive_queue);
+#endif
+        if (!skb)
+        {
+            dprintk("pid error: skb = null\n");
+            return;
+        }
+
+        nlh = (struct nlmsghdr *)skb->data;
+        if (!nlh)
+        {
+            dprintk("pid error: nlh = null\n");
+            return;
+        }
+
+        if(nlh->nlmsg_pid == pid)
+        {
+            break;
+        }
+
+        if(!skb_first)
+        {
+            skb_first = skb;
+        }
+        else if (skb_first == skb)
+        {
+            dprintk("can't found my skb???\n");
+            return;
+        }
+
+#ifdef KVER26
+        skb_queue_tail(&sk->sk_receive_queue, skb);
+#else
+        skb_queue_tail(&sk->receive_queue, skb);
+#endif
+    }
+
+	if(nlh->nlmsg_len < (SW_MAX_PAYLOAD + sizeof(nlmsghdr)))
+	{
+		dprintk("data length is less than %d bytes\n", SW_MAX_PAYLOAD);
+		SW_OUT_ON_ERROR(SW_ABORTED);
+	}
+    aos_mem_copy(args, NLMSG_DATA(nlh), SW_MAX_PAYLOAD);
+
+    rv = sw_api_cmd(args);
+    /* return API result to user */
+    rtn = (a_uint32_t) rv;
+    if (copy_to_user
+            ((void __USER *) args[1], (a_uint32_t *) & rtn, sizeof (a_uint32_t)))
+    {
+        rv = SW_NO_RESOURCE;
+    }
+
+    NETLINK_CB(skb).pid = 0;
+    NETLINK_CB(skb).dst_pid = nlh->nlmsg_pid;
+#ifdef KVER26
+    NETLINK_CB(skb).dst_group = 0;
+#else
+    NETLINK_CB(skb).dst_groups = 0;
+#endif
+
+    netlink_unicast(sk, skb, nlh->nlmsg_pid, MSG_DONTWAIT);
+}
+
+
+static int sw_api_thread(void *sk)
+{
+    a_uint32_t loc, i;
+    pid_t parent_pid = 0, child_pid = current->pid;
+
+    while ((loc = pid_find_save(parent_pid, child_pid)) == PID_TAB_NOT_FOUND)
+        schedule_timeout(1*HZ);
+
+    parent_pid = pid_parents[loc];
+    dprintk("thread child [%d] find parent [%d] at %d \n", child_pid, parent_pid, loc);
+
+    if ((RSV_PID_LOC_0 == loc) || (RSV_PID_LOC_1 == loc))
+    {
+        for(i=0; ; i++)
+        {
+            if(i && !sleep_on_timeout(&pid_child_wait[loc], (5*HZ)))
+            {
+                if(pid_exit(parent_pid) == A_FALSE)
+                    continue;
+
+                pid_free(loc);
+                dprintk("thread child[%d] exit!\n", child_pid);
+                return 0;
+            }
+
+            sw_api_exec(sk, parent_pid);
+        }
+    }
+    else
+    {
+        sw_api_exec(sk, parent_pid);
+        pid_free(loc);
+    }
+
+    return 0;
+}
+
+static void
+sw_api_netlink(struct sock *sk, int len)
+{
+    pid_t parent_pid = current->pid, child_pid = 0;
+    a_uint32_t loc = pid_find_save (parent_pid, child_pid);
+
+    if(loc == PID_TAB_NOT_FOUND)
+    {
+        if(pid_full())
+        {
+            dprintk("###threads exceed the max [%d] for pid [%d]!###\n", PID_TAB_MAX, parent_pid);
+            sw_api_excep_ack(sk, parent_pid);
+            return;
+        }
+#if 1
+        struct task_struct *p;
+        p = kthread_create(sw_api_thread, (void *)ssdk_nl_sk, "netlink_child");
+        if (IS_ERR(p))
+        {
+            dprintk("thread can't be created for netlink\n");
+            return;
+        }
+        child_pid = p->pid;
+#else
+        if ((child_pid = kernel_thread(sw_api_thread, ssdk_nl_sk, CLONE_KERNEL)) < 0)
+        {
+            dprintk("thread can't be created for netlink\n");
+            return;
+        }
+#endif
+        dprintk("[%d] create child [%d] at %d\n", parent_pid, child_pid, loc);
+        pid_find_save(parent_pid, child_pid);
+        wake_up_process(p);
+    }
+    else
+    {
+        dprintk("[%d] wake up child [%d] at %d\n", parent_pid, pid_childs[loc], loc);
+        wake_up(&pid_child_wait[loc]);
+    }
+
+    return;
+
+}
+
+#else
+
+static void
+sw_api_excep_ack_26_22(struct sk_buff *skb)
+{
+    sw_error_t rv = SW_NO_RESOURCE;
+    a_uint32_t args[SW_MAX_API_PARAM], rtn, size, dst_pid;
+    struct nlmsghdr *nlh = NULL;
+    struct sk_buff *rep;
+
+    nlh = (struct nlmsghdr *)skb->data;
+    if (!nlh)
+    {
+        dprintk("pid error: nlh = null\n");
+        return;
+    }
+    dst_pid = nlh->nlmsg_pid;
+
+	if(nlh->nlmsg_len < (SW_MAX_PAYLOAD + sizeof(nlmsghdr)))
+	{
+		dprintk("data length is less than %d bytes\n", SW_MAX_PAYLOAD);
+		SW_OUT_ON_ERROR(SW_ABORTED);
+	}
+    aos_mem_copy(args, NLMSG_DATA(nlh), SW_MAX_PAYLOAD);
+    /* return API result to user */
+    rtn = (a_uint32_t) rv;
+    if (copy_to_user
+            ((void __USER *) args[1], (a_uint32_t *) & rtn, sizeof (a_uint32_t)))
+    {
+        rv = SW_NO_RESOURCE;
+    }
+
+    size = NLMSG_SPACE(0);
+    rep = alloc_skb(size, GFP_ATOMIC);
+    if (!rep)
+    {
+        dprintk("reply socket buffer allocation error... \n");
+        return;
+    }
+    nlh = nlmsg_put(rep, 0, 0, 0, 0, 0);
+
+    NETLINK_CB(rep).pid = 0;
+    NETLINK_CB(rep).dst_group = 0;
+    netlink_unicast(ssdk_nl_sk, rep, dst_pid, MSG_DONTWAIT);
+}
+
+static void
+sw_api_exec_26_22(pid_t parent_pid)
+{
+    sw_error_t rv = SW_NO_RESOURCE;
+    a_uint32_t loc, args[SW_MAX_API_PARAM], rtn, skblen, nlmsglen, size, dst_pid;
+    struct nlmsghdr *nlh = NULL;
+    struct sk_buff *skb;
+    struct sk_buff *rep;
+
+    loc = pid_find(parent_pid, pid_parents);
+    if (PID_TAB_NOT_FOUND == loc)
+    {
+        dprintk("parent PID not found - (%d)\n", parent_pid);
+        return;
+    }
+
+    skb = skb_array[loc];
+    if (!skb)
+    {
+        dprintk("skb null pointer error\n");
+        return;
+    }
+
+    skblen = skb->len;
+    if (skb->len < sizeof(nlh))
+    {
+        dprintk("skb len error - (%d)\n", skb->len);
+        SW_OUT_ON_ERROR(SW_ABORTED);
+    }
+
+    nlh = (struct nlmsghdr *)skb->data;
+    if (!nlh)
+    {
+        dprintk("pid error: nlh = null\n");
+        SW_OUT_ON_ERROR(SW_ABORTED);
+    }
+
+    nlmsglen = nlh->nlmsg_len;
+    if (nlmsglen < sizeof(*nlh) || skblen < nlmsglen)
+    {
+        dprintk("nlmsglen error - (%d)\n", nlmsglen);
+        SW_OUT_ON_ERROR(SW_ABORTED);
+    }
+    dst_pid = nlh->nlmsg_pid;
+
+	if(nlmsglen < (SW_MAX_PAYLOAD + sizeof(nlmsghdr)))
+	{
+		dprintk("data length is less than %d bytes\n", SW_MAX_PAYLOAD);
+		SW_OUT_ON_ERROR(SW_ABORTED);
+	}
+    aos_mem_copy(args, NLMSG_DATA(nlh), SW_MAX_PAYLOAD);
+    rv = sw_api_cmd(args);
+
+    /* return API result to user */
+    rtn = (a_uint32_t) rv;
+    if (copy_to_user
+            ((void __USER *) args[1], (a_uint32_t *) & rtn, sizeof (a_uint32_t)))
+    {
+        rv = SW_NO_RESOURCE;
+    }
+
+    size = NLMSG_SPACE(0);
+    rep = alloc_skb(size, GFP_ATOMIC);
+    if (!rep)
+    {
+        dprintk("reply socket buffer allocation error... \n");
+        SW_OUT_ON_ERROR(SW_ABORTED);
+    }
+    nlh = nlmsg_put(rep, 0, 0, 0, 0, 0);
+
+    NETLINK_CB(rep).pid = 0;
+    NETLINK_CB(rep).dst_group = 0;
+    netlink_unicast(ssdk_nl_sk, rep, dst_pid, MSG_DONTWAIT);
+
+out:
+    skb_array[loc] = NULL;
+    kfree_skb(skb);
+}
+
+static int
+sw_api_thread_26_22(void * data)
+{
+    a_uint32_t loc, i;
+    pid_t parent_pid = 0, child_pid = current->pid;
+
+    while ((loc = pid_find_save(parent_pid, child_pid)) == PID_TAB_NOT_FOUND)
+        schedule_timeout(1*HZ);
+
+    parent_pid = pid_parents[loc];
+    dprintk("thread child [%d] find parent [%d] at %d \n", child_pid, parent_pid, loc);
+
+    if ((RSV_PID_LOC_0 == loc) || (RSV_PID_LOC_1 == loc))
+    {
+        for(i=0; ; i++)
+        {
+            if(i && !sleep_on_timeout(&pid_child_wait[loc], (5*HZ)))
+            {
+                if(pid_exit(parent_pid) == A_FALSE)
+                    continue;
+
+                pid_free(loc);
+                dprintk("thread child[%d] exit!\n", child_pid);
+                return 0;
+            }
+
+            sw_api_exec_26_22(parent_pid);
+        }
+    }
+    else
+    {
+        sw_api_exec_26_22(parent_pid);
+        pid_free(loc);
+    }
+
+    return 0;
+}
+
+static void
+sw_api_netlink_26_22(struct sk_buff *skb)
+{
+    pid_t parent_pid = current->pid, child_pid = 0;
+    a_uint32_t loc = pid_find_save (parent_pid, child_pid);
+
+    if(loc == PID_TAB_NOT_FOUND)
+    {
+        if(pid_full())
+        {
+            dprintk("###threads exceed the max [%d] for pid [%d]!###\n", PID_TAB_MAX, parent_pid);
+            sw_api_excep_ack_26_22(skb);
+            return;
+        }
+
+        loc = pid_find_save(parent_pid, 0xffffffff);
+
+#if 1
+        struct task_struct *p;
+        p = kthread_create(sw_api_thread_26_22, (void *)ssdk_nl_sk, "netlink_child");
+        if (IS_ERR(p))
+        {
+            dprintk("thread can't be created for netlink\n");
+            return;
+        }
+
+        skb_array[loc] = skb_get(skb);
+        child_pid = p->pid;
+        pid_childs[loc] = child_pid;
+        wake_up_process(p);
+#else
+        if ((child_pid = kernel_thread(sw_api_thread_26_22, NULL, CLONE_KERNEL)) < 0)
+        {
+            dprintk("thread can't be created for netlink\n");
+            return;
+        }
+#endif
+        dprintk("[%d] create child [%d] at %d\n", parent_pid, child_pid, loc);
+    }
+    else
+    {
+        dprintk("[%d] wake up child [%d] at %d\n", parent_pid, pid_childs[loc], loc);
+        skb_array[loc] = skb_get(skb);
+        wake_up(&pid_child_wait[loc]);
+    }
+
+    return;
+}
+#endif
+
+sw_error_t
+sw_uk_init(a_uint32_t nl_prot)
+{
+    a_uint32_t i, protocol;
+
+    if (!cmd_buf)
+    {
+        if((cmd_buf = (a_uint32_t *) aos_mem_alloc(SW_MAX_API_BUF)) == NULL)
+            return SW_OUT_OF_MEM;
+    }
+
+    if (!ssdk_nl_sk)
+    {
+#if defined UK_NL_PROT
+        protocol = UK_NL_PROT;
+#else
+        protocol = nl_prot;
+#endif
+
+#ifdef KVER26
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
+        ssdk_nl_sk = netlink_kernel_create(&init_net, protocol, 0, sw_api_netlink_26_22, NULL, THIS_MODULE);
+#else
+        ssdk_nl_sk = netlink_kernel_create(protocol, 0, sw_api_netlink, THIS_MODULE);
+#endif
+#else
+        ssdk_nl_sk = netlink_kernel_create(protocol, sw_api_netlink);
+#endif
+        if (!ssdk_nl_sk)
+        {
+            dprintk("netlink_kernel_create fail at nl_prot:[%d]\n", protocol);
+            return SW_NO_RESOURCE;
+        }
+        else
+        {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
+            dprintk("netlink_kernel_create succeeded at nl_prot: [%d] (>2.6.22)\n", protocol);
+#else
+            dprintk("netlink_kernel_create succeeded at nl_prot: [%d] (<2.6.22)\n", protocol);
+#endif
+        }
+    }
+
+    init_MUTEX(&pid_tab_sem);
+    init_MUTEX(&api_sem);
+
+    for(i = 0; i < PID_TAB_MAX; i++)
+    {
+        init_waitqueue_head(&pid_child_wait[i]);
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+sw_uk_cleanup(void)
+{
+    if (cmd_buf)
+    {
+        aos_mem_free(cmd_buf);
+        cmd_buf = NULL;
+    }
+
+    if (ssdk_nl_sk)
+    {
+#ifdef KVER26
+        sock_release(ssdk_nl_sk->sk_socket);
+#else
+        sock_release(ssdk_nl_sk->socket);
+#endif
+        ssdk_nl_sk = NULL;
+    }
+
+    return SW_OK;
+}
+
diff --git a/qca-ssdk/src/sal/sd/sd.c b/qca-ssdk/src/sal/sd/sd.c
new file mode 100755
index 0000000..39c0530
--- /dev/null
+++ b/qca-ssdk/src/sal/sd/sd.c
@@ -0,0 +1,371 @@
+/*
+ * Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*qca808x_start*/
+#include "sw.h"
+#include "ssdk_init.h"
+#include "sd.h"
+#include "sw_api.h"
+#if ((!defined(KERNEL_MODULE)) && defined(UK_IF))
+#include "sw_api_us.h"
+#endif
+
+mdio_reg_set ssdk_mdio_set    = NULL;
+mdio_reg_get ssdk_mdio_get    = NULL;
+i2c_reg_set ssdk_i2c_set    = NULL;
+i2c_reg_get ssdk_i2c_get    = NULL;
+/*qca808x_end*/
+hdr_reg_set  ssdk_hdr_reg_set = NULL;
+hdr_reg_get  ssdk_hdr_reg_get = NULL;
+psgmii_reg_set  ssdk_psgmii_reg_set = NULL;
+psgmii_reg_get  ssdk_psgmii_reg_get = NULL;
+uniphy_reg_set  ssdk_uniphy_reg_set = NULL;
+uniphy_reg_get  ssdk_uniphy_reg_get = NULL;
+mii_reg_set	ssdk_mii_reg_set = NULL;
+mii_reg_get	ssdk_mii_reg_get = NULL;
+
+/*qca808x_start*/
+sw_error_t
+sd_reg_mdio_set(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg,
+                a_uint16_t data)
+{
+    sw_error_t rv = SW_OK;
+
+    if (NULL != ssdk_mdio_set)
+    {
+        rv = ssdk_mdio_set(dev_id, phy, reg, data);
+    }
+    else
+    {
+#if ((!defined(KERNEL_MODULE)) && defined(UK_IF))
+        {
+            a_uint32_t args[SW_MAX_API_PARAM];
+
+            args[0] = SW_API_PHY_SET;
+            args[1] = (a_uint32_t) & rv;
+            args[2] = dev_id;
+            args[3] = phy;
+            args[4] = reg;
+            args[5] = data;
+            if (SW_OK != sw_uk_if(args))
+            {
+                return SW_FAIL;
+            }
+        }
+#else
+        return SW_NOT_SUPPORTED;
+#endif
+    }
+
+    return rv;
+}
+
+sw_error_t
+sd_reg_mdio_get(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg, a_uint16_t * data)
+{
+    sw_error_t rv = SW_OK;
+
+    if (NULL != ssdk_mdio_get)
+    {
+        rv = ssdk_mdio_get(dev_id, phy, reg, data);
+    }
+    else
+    {
+#if ((!defined(KERNEL_MODULE)) && defined(UK_IF))
+        {
+            a_uint32_t args[SW_MAX_API_PARAM];
+            a_uint32_t tmp;
+
+            args[0] = SW_API_PHY_GET;
+            args[1] = (a_uint32_t) & rv;
+            args[2] = dev_id;
+            args[3] = phy;
+            args[4] = reg;
+            args[5] = (a_uint32_t) & tmp;
+            if (SW_OK != sw_uk_if(args))
+            {
+                return SW_FAIL;
+            }
+            *data = *((a_uint16_t *)&tmp);
+        }
+#else
+        return SW_NOT_SUPPORTED;
+#endif
+    }
+
+    return rv;
+}
+
+sw_error_t
+sd_reg_i2c_set(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg,
+                a_uint16_t data)
+{
+    sw_error_t rv = SW_OK;
+
+    if (NULL != ssdk_i2c_set)
+    {
+        rv = ssdk_i2c_set(dev_id, phy, reg, data);
+    }
+    else
+    {
+#if ((!defined(KERNEL_MODULE)) && defined(UK_IF))
+        {
+            a_uint32_t args[SW_MAX_API_PARAM];
+
+            args[0] = SW_API_PHY_I2C_SET;
+            args[1] = (a_uint32_t) & rv;
+            args[2] = dev_id;
+            args[3] = phy;
+            args[4] = reg;
+            args[5] = data;
+            if (SW_OK != sw_uk_if(args))
+            {
+                return SW_FAIL;
+            }
+        }
+#else
+        return SW_NOT_SUPPORTED;
+#endif
+    }
+
+    return rv;
+}
+
+sw_error_t
+sd_reg_i2c_get(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg, a_uint16_t * data)
+{
+    sw_error_t rv = SW_OK;
+
+    if (NULL != ssdk_i2c_get)
+    {
+        rv = ssdk_i2c_get(dev_id, phy, reg, data);
+    }
+    else
+    {
+#if ((!defined(KERNEL_MODULE)) && defined(UK_IF))
+        {
+            a_uint32_t args[SW_MAX_API_PARAM];
+            a_uint32_t tmp;
+
+            args[0] = SW_API_PHY_I2C_GET;
+            args[1] = (a_uint32_t) & rv;
+            args[2] = dev_id;
+            args[3] = phy;
+            args[4] = reg;
+            args[5] = (a_uint32_t) & tmp;
+            if (SW_OK != sw_uk_if(args))
+            {
+                return SW_FAIL;
+            }
+            *data = *((a_uint16_t *)&tmp);
+        }
+#else
+        return SW_NOT_SUPPORTED;
+#endif
+    }
+
+    return rv;
+}
+/*qca808x_end*/
+sw_error_t
+sd_reg_hdr_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len)
+{
+    sw_error_t rv;
+
+    if (NULL != ssdk_hdr_reg_set)
+    {
+        rv = ssdk_hdr_reg_set(dev_id, reg_addr, reg_data, len);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    return rv;
+}
+
+sw_error_t
+sd_reg_hdr_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len)
+{
+    sw_error_t rv;
+
+    if (NULL != ssdk_hdr_reg_get)
+    {
+        rv = ssdk_hdr_reg_get(dev_id, reg_addr, reg_data, len);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    return rv;
+}
+
+sw_error_t
+sd_reg_psgmii_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len)
+{
+    sw_error_t rv;
+
+    if (NULL != ssdk_psgmii_reg_set)
+    {
+        rv = ssdk_psgmii_reg_set(dev_id, reg_addr, reg_data, len);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    return rv;
+}
+
+sw_error_t
+sd_reg_psgmii_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len)
+{
+    sw_error_t rv;
+
+    if (NULL != ssdk_psgmii_reg_get)
+    {
+        rv = ssdk_psgmii_reg_get(dev_id, reg_addr, reg_data, len);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    return rv;
+}
+
+sw_error_t
+sd_reg_uniphy_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr,
+		a_uint8_t * reg_data, a_uint32_t len)
+{
+    sw_error_t rv;
+
+    if (NULL != ssdk_uniphy_reg_set)
+    {
+        rv = ssdk_uniphy_reg_set(dev_id, index, reg_addr, reg_data, len);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    return rv;
+}
+
+sw_error_t
+sd_reg_uniphy_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr,
+		a_uint8_t * reg_data, a_uint32_t len)
+{
+    sw_error_t rv;
+
+    if (NULL != ssdk_uniphy_reg_get)
+    {
+        rv = ssdk_uniphy_reg_get(dev_id, index, reg_addr, reg_data, len);
+    }
+    else
+    {
+        return SW_NOT_SUPPORTED;
+    }
+
+    return rv;
+}
+
+void
+sd_reg_mii_set(a_uint32_t dev_id, a_uint32_t reg, a_uint32_t val)
+{
+    if (NULL != ssdk_mii_reg_set)
+    {
+        ssdk_mii_reg_set(dev_id, reg, val);
+    }
+}
+
+a_uint32_t
+sd_reg_mii_get(a_uint32_t dev_id, a_uint32_t reg)
+{
+    a_uint32_t value = 0;
+
+    if (NULL != ssdk_mii_reg_get)
+    {
+        value = ssdk_mii_reg_get(dev_id, reg);
+    }
+
+    return value;
+}
+/*qca808x_start*/
+sw_error_t
+sd_init(a_uint32_t dev_id, ssdk_init_cfg * cfg)
+{
+    if (NULL != cfg->reg_func.mdio_set)
+    {
+        ssdk_mdio_set = cfg->reg_func.mdio_set;
+    }
+
+    if (NULL != cfg->reg_func.mdio_get)
+    {
+        ssdk_mdio_get = cfg->reg_func.mdio_get;
+    }
+
+    if (NULL != cfg->reg_func.i2c_set)
+    {
+        ssdk_i2c_set = cfg->reg_func.i2c_set;
+    }
+
+    if (NULL != cfg->reg_func.i2c_get)
+    {
+        ssdk_i2c_get = cfg->reg_func.i2c_get;
+    }
+/*qca808x_end*/
+    if (NULL != cfg->reg_func.header_reg_set)
+    {
+        ssdk_hdr_reg_set = cfg->reg_func.header_reg_set;
+    }
+
+    if (NULL != cfg->reg_func.header_reg_get)
+    {
+        ssdk_hdr_reg_get = cfg->reg_func.header_reg_get;
+    }
+
+    if (NULL != cfg->reg_func.psgmii_reg_set)
+    {
+        ssdk_psgmii_reg_set = cfg->reg_func.psgmii_reg_set;
+    }
+
+    if (NULL != cfg->reg_func.psgmii_reg_get)
+    {
+        ssdk_psgmii_reg_get = cfg->reg_func.psgmii_reg_get;
+    }
+    if (NULL != cfg->reg_func.uniphy_reg_set)
+    {
+        ssdk_uniphy_reg_set = cfg->reg_func.uniphy_reg_set;
+    }
+
+    if (NULL != cfg->reg_func.uniphy_reg_get)
+    {
+        ssdk_uniphy_reg_get = cfg->reg_func.uniphy_reg_get;
+    }
+
+    if (NULL != cfg->reg_func.mii_reg_set)
+    {
+        ssdk_mii_reg_set = cfg->reg_func.mii_reg_set;
+    }
+
+    if (NULL != cfg->reg_func.mii_reg_get)
+    {
+        ssdk_mii_reg_get = cfg->reg_func.mii_reg_get;
+    }
+/*qca808x_start*/
+    return SW_OK;
+}
+/*qca808x_end*/
diff --git a/qca-ssdk/src/shell_lib/Makefile b/qca-ssdk/src/shell_lib/Makefile
new file mode 100755
index 0000000..2336b4f
--- /dev/null
+++ b/qca-ssdk/src/shell_lib/Makefile
@@ -0,0 +1,12 @@
+LOC_DIR=src/shell_lib
+LIB=SHELIB
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=$(wildcard *.c)
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/qca-ssdk/src/shell_lib/shell.c b/qca-ssdk/src/shell_lib/shell.c
new file mode 100755
index 0000000..e091256
--- /dev/null
+++ b/qca-ssdk/src/shell_lib/shell.c
@@ -0,0 +1,555 @@
+/*
+ * Copyright (c) 2013, 2017, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "shell.h"
+#include "shell_io.h"
+#include "shell_sw.h"
+#include "shell_config.h"
+#include "api_access.h"
+
+unsigned long ioctl_buf[IOCTL_BUF_SIZE];
+unsigned long ioctl_argp[CMDSTR_ARGS_MAX*4];
+
+void
+cmd_print_error(sw_error_t rtn)
+{
+
+}
+
+void
+cmd_print(char *fmt, ...)
+{
+
+}
+
+static sw_error_t
+cmd_input_parser(unsigned long *arg_val, a_uint32_t arg_index, sw_api_param_t *pp)
+{
+    a_int16_t i;
+    unsigned long *pbuf;
+    a_uint16_t rtn_size = 1;
+    sw_api_param_t *pptmp = NULL;;
+
+    pbuf = ioctl_buf + rtn_size;    /*reserve for return value */
+
+    for (i = 0; i < arg_index; i++)
+    {
+        pptmp = pp + i;
+        if (pptmp->param_type & SW_PARAM_PTR)
+        {
+            pbuf += (pptmp->data_size + 3) / 4;
+        }
+    }
+
+    if (pptmp == NULL)
+        return SW_BAD_PTR;
+
+    if ((pbuf - ioctl_buf + (pptmp->data_size + 3) / 4) > (IOCTL_BUF_SIZE/4))
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    *arg_val = (unsigned long) pbuf;
+
+    return SW_OK;
+}
+
+static sw_error_t
+cmd_api_func(sw_api_func_t *fp, a_uint32_t nr_param, unsigned long * args)
+{
+    unsigned long *p = &args[2];
+    sw_error_t rv;
+
+    switch (nr_param)
+    {
+        case 0:
+	{
+            sw_error_t(*func) (void);
+            func = fp->func;
+            rv = (func) ();
+            break;
+	}
+        case 1:
+	{
+            sw_error_t(*func1) (unsigned long);
+            func1 = fp->func;
+            rv = (func1) (p[0]);
+            break;
+	}
+        case 2:
+	{
+            sw_error_t(*func2) (unsigned long, unsigned long);
+            func2 = fp->func;
+            rv = (func2) (p[0], p[1]);
+            break;
+	}
+        case 3:
+	{
+            sw_error_t(*func3) (unsigned long, unsigned long, unsigned long);
+            func3 = fp->func;
+            rv = (func3) (p[0], p[1], p[2]);
+            break;
+	}
+        case 4:
+	{
+            sw_error_t(*func4) (unsigned long, unsigned long, unsigned long, \
+			unsigned long);
+            func4 = fp->func;
+            rv = (func4) (p[0], p[1], p[2], p[3]);
+            break;
+	}
+        case 5:
+	{
+            sw_error_t(*func5) (unsigned long, unsigned long, unsigned long, \
+			unsigned long, unsigned long);
+            func5 = fp->func;
+            rv = (func5) (p[0], p[1], p[2], p[3], p[4]);
+            break;
+	}
+        case 6:
+	{
+            sw_error_t(*func6) (unsigned long, unsigned long, unsigned long, \
+			unsigned long, unsigned long, unsigned long);
+            func6 = fp->func;
+            rv = (func6) (p[0], p[1], p[2], p[3], p[4], p[5]);
+            break;
+	}
+        case 7:
+	{
+            sw_error_t(*func7) (unsigned long, unsigned long, unsigned long, \
+			unsigned long, unsigned long, unsigned long, unsigned long);
+            func7 = fp->func;
+            rv = (func7) (p[0], p[1], p[2], p[3], p[4], p[5], p[6]);
+            break;
+	}
+        case 8:
+	{
+            sw_error_t(*func8) (unsigned long, unsigned long, unsigned long, \
+			unsigned long, unsigned long, unsigned long, unsigned long, \
+			unsigned long);
+            func8 = fp->func;
+            rv = (func8) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+            break;
+	}
+        case 9:
+	{
+            sw_error_t(*func9) (unsigned long, unsigned long, unsigned long, \
+			unsigned long, unsigned long, unsigned long, unsigned long, \
+			unsigned long, unsigned long);
+            func9 = fp->func;
+            rv = (func9) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]);
+            break;
+	}
+        case 10:
+	{
+            sw_error_t(*func10) (unsigned long, unsigned long, unsigned long, \
+			unsigned long, unsigned long, unsigned long, unsigned long, \
+			unsigned long, unsigned long, unsigned long);
+            func10 = fp->func;
+            rv = (func10) (p[0], p[1], p[2], p[3], p[4], p[5],
+                         p[6], p[7], p[8], p[9]);
+            break;
+	}
+        default:
+            rv = SW_OUT_OF_RANGE;
+    }
+
+    *(unsigned long *) args[1] = rv;
+
+    return rv;
+}
+#if 0
+static sw_error_t
+cmd_api_output(sw_api_param_t *pp, a_uint32_t nr_param, a_uint32_t * args)
+{
+    a_uint16_t i;
+    a_uint32_t *pbuf;
+    a_uint16_t rtn_size = 1;
+    sw_error_t rtn = (sw_error_t) (*ioctl_buf);
+    sw_api_param_t *pptmp = NULL;
+
+    if (rtn != SW_OK)
+    {
+        cmd_print_error(rtn);
+        return rtn;
+    }
+
+    pbuf = ioctl_buf + rtn_size;
+    for (i = 0; i < nr_param; i++)
+    {
+        pptmp = pp + i;
+        if (pptmp->param_type & SW_PARAM_PTR)
+        {
+
+            if (pptmp->param_type & SW_PARAM_OUT)
+            {
+
+                sw_data_type_t *data_type;
+                if (!(data_type = cmd_data_type_find(pptmp->data_type)))
+                    return SW_NO_SUCH;
+
+                if (data_type->show_func)
+                {
+                    data_type->show_func(pptmp->param_name, pbuf, pptmp->data_size);
+                }
+                else
+                {
+                    dprintf("\n Error, not define output print function!");
+                }
+            }
+
+            if ((pbuf - ioctl_buf +
+                    (pptmp->data_size + 3) / 4) > (IOCTL_BUF_SIZE/4))
+                return SW_NO_RESOURCE;
+
+            pbuf += (pptmp->data_size + 3) / 4;
+
+        }
+    }
+    return SW_OK;
+}
+#endif
+void
+cmd_strtol(char *str, a_uint32_t * arg_val)
+{
+    if (str[0] == '0' && (str[1] == 'x' || str[1] == 'X'))
+        sscanf(str, "%x", arg_val);
+    else
+        sscanf(str, "%d", arg_val);
+}
+
+static sw_error_t
+cmd_parse_api(char **cmd_str, unsigned long * arg_val)
+{
+    char *tmp_str;
+    a_uint32_t arg_index, arg_start = 2, reserve_index = 1; /*reserve for dev_id */
+    a_uint32_t last_param_in = 0;
+    unsigned long *temp;
+    void *pentry;
+    sw_api_param_t *pptmp = NULL;
+    sw_api_t sw_api;
+    a_uint32_t ignorecnt = 0, jump = 0;
+    sw_data_type_t *data_type;
+    sw_api.api_id = arg_val[0];
+    SW_RTN_ON_ERROR(sw_api_get(&sw_api));
+
+    /*set device id */
+    arg_val[arg_start] = get_devid();
+
+    for (arg_index = reserve_index; arg_index < sw_api.api_nr; arg_index++)
+    {
+        tmp_str = NULL;
+        pptmp = sw_api.api_pp + arg_index;
+
+        if (!(pptmp->param_type & SW_PARAM_IN))
+        {
+            ignorecnt++;
+        }
+
+        if (pptmp->param_type & SW_PARAM_IN)
+        {
+            tmp_str = cmd_str[arg_index - reserve_index - ignorecnt + jump];
+            last_param_in = arg_index;
+            if((pptmp->api_id == 314) && last_param_in == 2) last_param_in = 4;//SW_API_FDB_EXTEND_NEXT wr
+            if((pptmp->api_id == 327) && last_param_in == 2) last_param_in = 4;//SW_API_FDB_EXTEND_FIRST wr
+        }
+        temp = &arg_val[arg_start + arg_index];
+
+        if (!(data_type = cmd_data_type_find(pptmp->data_type)))
+            return SW_NO_SUCH;
+
+        pentry = temp;
+        if (pptmp->param_type & SW_PARAM_PTR)
+        {
+            if (cmd_input_parser(temp, arg_index, sw_api.api_pp) != SW_OK)
+                return SW_NO_RESOURCE;
+
+            pentry = (void *) *temp;
+        }
+
+        if (pptmp->param_type & SW_PARAM_IN)
+        {
+#if 1
+            if(pptmp->param_type & SW_PARAM_PTR)   //quiet mode
+            {
+                if(!get_talk_mode())
+                    set_full_cmdstrp((char **)(cmd_str + (last_param_in - reserve_index) + jump));
+            }
+#endif
+            /*check and convert input param */
+            if (data_type->param_check != NULL)
+            {
+                if (data_type->param_check(tmp_str, (a_uint32_t *)pentry, (a_uint32_t)pptmp->data_size) != SW_OK)
+                    return SW_BAD_PARAM;
+		if(!get_talk_mode() && (pptmp->param_type & SW_PARAM_PTR)) {
+			if (get_jump())
+				jump += get_jump() -1;
+		}
+            }
+        }
+    }
+
+    /*superfluous args */
+    /*
+       if(cmd_str[last_param_in] != NULL)
+       return SW_BAD_PARAM;
+     */
+
+    return SW_OK;
+}
+
+/*user command api*/
+sw_error_t
+cmd_exec_api(unsigned long *arg_val)
+{
+    sw_error_t rv;
+    sw_api_t sw_api;
+
+    sw_api.api_id = arg_val[0];
+    SW_RTN_ON_ERROR(sw_api_get(&sw_api));
+
+    /*save cmd return value */
+    arg_val[1] = (unsigned long) ioctl_buf;
+    /*save set device id */
+    arg_val[2] = get_devid();
+
+    rv = cmd_api_func(sw_api.api_fp, sw_api.api_nr, arg_val);
+    SW_RTN_ON_ERROR(rv);
+
+	#if 0
+    rv = cmd_api_output(sw_api.api_pp, sw_api.api_nr, arg_val);
+    SW_RTN_ON_ERROR(rv);
+	#endif
+
+    return rv;
+}
+
+
+void
+cmd_print_usage (int cmd_index, int cmd_index_sub)
+{
+	#if 0
+    if(GCMD_NAME(cmd_index))
+        dprintf("usage: %s", GCMD_NAME(cmd_index));
+
+    if (GCMD_SUB_NAME(cmd_index, cmd_index_sub))
+        dprintf(" %s", GCMD_SUB_NAME(cmd_index, cmd_index_sub));
+
+    if(GCMD_SUB_ACT(cmd_index, cmd_index_sub) && GCMD_SUB_USAGE(cmd_index, cmd_index_sub))
+        dprintf(" %s %s\n\n", GCMD_SUB_ACT(cmd_index, cmd_index_sub),
+                GCMD_SUB_USAGE(cmd_index, cmd_index_sub));
+	#endif
+}
+/*
+    main function
+    input args:
+        arg_val[0] = cmd_num
+        arg_val[1] = rtn_code
+        arg_val[2] = dev_id
+        arg_val[3] = dbg_cmd_num or other
+*/
+
+/*command string lookup*/
+a_uint32_t
+cmd_lookup(char **cmd_str, int *cmd_index, int *cmd_index_sub)
+{
+    a_uint32_t no, sub_no;
+    a_uint32_t cmd_deepth = 0;
+
+    *cmd_index = GCMD_DESC_NO_MATCH;
+    *cmd_index_sub = GCMD_DESC_NO_MATCH;
+
+    if (cmd_str[0] == NULL)
+        return cmd_deepth;
+
+    for (no = 0; GCMD_DESC_VALID(no); no++)
+    {
+        if (strcasecmp(cmd_str[0], GCMD_NAME(no)))
+            continue;
+
+        for (sub_no = 0; GCMD_SUB_DESC_VALID(no, sub_no); sub_no++)
+        {
+            if (cmd_str[1] != NULL && cmd_str[2] != NULL)
+            {
+
+                if (GCMD_SUB_NAME(no, sub_no) && GCMD_SUB_ACT(no, sub_no)
+                        && !strcasecmp(cmd_str[1], GCMD_SUB_NAME(no, sub_no))
+                        && !strcasecmp(cmd_str[2], GCMD_SUB_ACT(no, sub_no)))
+                {
+                    *cmd_index = no;
+                    *cmd_index_sub = sub_no;
+                    cmd_deepth = 3;
+                    return cmd_deepth;
+                }
+
+                else if (!GCMD_SUB_NAME(no, sub_no) && GCMD_SUB_ACT(no, sub_no)
+                         && !strcasecmp(cmd_str[1], GCMD_SUB_ACT(no, sub_no)))
+                {
+                    *cmd_index = no;
+                    *cmd_index_sub = sub_no;
+                    cmd_deepth = 2;
+                    return cmd_deepth;
+                }
+            }
+            else if (cmd_str[1] != NULL && cmd_str[2] == NULL)
+            {
+
+                if (!GCMD_SUB_NAME(no, sub_no) && GCMD_SUB_ACT(no, sub_no)
+                        && !strcasecmp(cmd_str[1], GCMD_SUB_ACT(no, sub_no)))
+                {
+                    *cmd_index = no;
+                    *cmd_index_sub = sub_no;
+                    cmd_deepth = 2;
+                    return cmd_deepth;
+                }
+            }
+        }
+    }
+
+    return cmd_deepth;
+}
+
+static unsigned long *
+cmd_parse(char *cmd_str, int *cmd_index, int *cmd_index_sub)
+{
+    int cmd_nr = 0;
+    unsigned long *arg_val = ioctl_argp;
+    char *tmp_str[CMDSTR_ARGS_MAX];
+    int rtn_code = 0;
+    int cmd_depth;
+
+    if (cmd_str == NULL)
+        return NULL;
+
+    memset(arg_val, 0, CMDSTR_ARGS_MAX * sizeof (unsigned long));
+
+    /* split string into array */
+    if ((tmp_str[cmd_nr] = (void *) strsep(&cmd_str, " ")) == NULL)
+        return NULL;
+
+    /*handle help */
+    if (!strcasecmp(tmp_str[cmd_nr], "help"))
+    {
+        return NULL;
+    }
+
+    while (tmp_str[cmd_nr])
+    {
+        if (++cmd_nr == 3)
+            break;
+
+        tmp_str[cmd_nr] = (void *) strsep(&cmd_str, " ");
+    }
+
+    /*commond string lookup */
+    cmd_depth = cmd_lookup(tmp_str, cmd_index, cmd_index_sub);
+
+    if (*cmd_index == GCMD_DESC_NO_MATCH || *cmd_index_sub == GCMD_DESC_NO_MATCH)
+    {
+        return NULL;
+    }
+
+    /*parse param */
+    cmd_nr = 0;
+    if (cmd_depth == 2)
+    {
+        tmp_str[cmd_nr] = tmp_str[2];
+        cmd_nr++;
+    }
+
+    tmp_str[cmd_nr] = (void *) strsep(&cmd_str, " ");
+    while (tmp_str[cmd_nr])
+    {
+        if (strcmp(tmp_str[cmd_nr], ""))
+            if (++cmd_nr == CMDSTR_ARGS_MAX)
+                break;
+        tmp_str[cmd_nr] = (void *) strsep(&cmd_str, " ");
+    }
+
+    arg_val[0] = GCMD_SUB_API(*cmd_index, *cmd_index_sub);
+    arg_val[1] = (unsigned long) ioctl_buf;
+
+    if (arg_val[0] < SW_API_MAX)
+    {
+        /*api command parse */
+        rtn_code = cmd_parse_api(tmp_str, arg_val);
+
+    }
+    else
+    {
+        rtn_code = SW_BAD_PARAM;
+    }
+
+    if(rtn_code != SW_OK)
+    {
+        cmd_print_error(rtn_code);
+
+        if(rtn_code == SW_BAD_PARAM)
+            cmd_print_usage(*cmd_index, *cmd_index_sub);
+
+        return NULL;
+    }
+
+    return arg_val;
+}
+
+static int
+cmd_exec(unsigned long *arg_val, int cmd_index, int cmd_index_sub)
+{
+    unsigned long api_id = arg_val[0];
+    sw_error_t rtn = SW_OK;
+
+    if( api_id < SW_API_MAX )
+    {
+        rtn = cmd_exec_api(arg_val);
+
+    }
+    else if ((api_id > SW_API_MAX ) && (api_id < SW_CMD_MAX))
+    {
+    }
+    else
+    {
+        rtn = SW_BAD_PARAM;
+    }
+
+    if(rtn != SW_OK)
+        cmd_print_error(rtn);
+
+    return 0;
+}
+
+int
+cmd_run_one(char *cmd_str)
+{
+    unsigned long *arg_list;
+    int cmd_index = 0, cmd_index_sub = 0;
+
+    if ((arg_list = cmd_parse(cmd_str, &cmd_index, &cmd_index_sub)) != NULL)
+    {
+        cmd_exec(arg_list, cmd_index, cmd_index_sub);
+    }
+
+    return SW_OK;
+}
+
+/* Dummy function to avoid linker complaints */
+void __aeabi_unwind_cpp_pr0(void)
+{
+};
+void __aeabi_unwind_cpp_pr1(void)
+{
+};
+
diff --git a/qca-ssdk/src/shell_lib/shell_config.c b/qca-ssdk/src/shell_lib/shell_config.c
new file mode 100755
index 0000000..1b00daf
--- /dev/null
+++ b/qca-ssdk/src/shell_lib/shell_config.c
@@ -0,0 +1,1513 @@
+/*
+ * Copyright (c) 2013, 2015-2019, 2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "shell_config.h"
+#include "shell_sw.h"
+
+#if 0
+/*cmdline tree descript*/
+struct cmd_des_t gcmd_des[] =
+{
+    /*port ctrl*/
+#ifdef IN_PORTCONTROL
+    {
+        "port", "config port control",
+        {
+            {"duplex", "set", "set duplex mode of a port", "<port_id> <half|full>", SW_API_PT_DUPLEX_SET, NULL},
+            {"speed", "set", "set speed mode of a port", "<port_id> <10|100|1000>", SW_API_PT_SPEED_SET, NULL},
+            {"autoAdv", "set", "set auto-negotiation advertisement of a port", "<port_id> <cap_bitmap>", SW_API_PT_AN_ADV_SET, NULL},
+            {"autoNeg", "enable", "enable auto-negotiation of a port", "<port_id>", SW_API_PT_AN_ENABLE, NULL},
+            {"autoNeg", "restart", "restart auto-negotiation process of a port", "<port_id>", SW_API_PT_AN_RESTART, NULL},
+            {"autoNegenable", "set", "enable auto-negotiation of a port", "<port_id>", SW_API_PT_AN_ENABLE, NULL},
+            {"autoNegrestart", "set", "restart auto-negotiation process of a port", "<port_id>", SW_API_PT_AN_RESTART, NULL},
+            {"header", "set", "set atheros header/tag status of a port", "<port_id> <enable|disable>", SW_API_PT_HDR_SET, NULL},
+            {"txhdr", "set", "set tx frame atheros header/tag status of a port", "<port_id> <noheader|onlymanagement|allframe>", SW_API_PT_TXHDR_SET, NULL},
+            {"rxhdr", "set", "set rx frame atheros header/tag status of a port", "<port_id> <noheader|onlymanagement|allframe>", SW_API_PT_RXHDR_SET, NULL},
+            {"hdrtype", "set", "set atheros header/tag type", "<enable|disable> <type 0x-0xffff>", SW_API_HEADER_TYPE_SET, NULL},
+            {"flowCtrl", "set", "set flow control status of a port", "<port_id> <enable|disable>", SW_API_PT_FLOWCTRL_SET, NULL},
+            {"flowCtrlforcemode", "set", "set flow control force mode of a port", "<port_id> <enable|disable>", SW_API_PT_FLOWCTRL_MODE_SET, NULL},
+            {"powersave", "set", "set powersave status of a port", "<port_id> <enable|disable>", SW_API_PT_POWERSAVE_SET, NULL},
+            {"hibernate", "set", "set hibernate status of a port", "<port_id> <enable|disable>", SW_API_PT_HIBERNATE_SET, NULL},
+            {"cdt", "run", "run cable diagnostic test of a port", "<port_id> <mdi_pair>", SW_API_PT_CDT, NULL},
+            {"txmacstatus", "set", "set txmac status of a port", "<port_id> <enable|disable>", SW_API_TXMAC_STATUS_SET, NULL},
+            {"rxmacstatus", "set", "set rxmac status of a port", "<port_id> <enable|disable>", SW_API_RXMAC_STATUS_SET, NULL},
+            {"txfcstatus", "set", "set tx flow control status of a port", "<port_id> <enable|disable>", SW_API_TXFC_STATUS_SET, NULL},
+            {"rxfcstatus", "set", "set rx flow control status of a port", "<port_id> <enable|disable>", SW_API_RXFC_STATUS_SET, NULL},
+            {"bpstatus", "set", "set back pressure status of a port", "<port_id> <enable|disable>", SW_API_BP_STATUS_SET, NULL},
+            {"linkforcemode", "set", "set link force mode of a port", "<port_id> <enable|disable>", SW_API_PT_LINK_MODE_SET, NULL},
+            {"macLoopback", "set", "set mac level loop back mode of port", "<port_id> <enable|disable>", SW_API_PT_MAC_LOOPBACK_SET, NULL},
+	    {"congedrop", "set", "set congestion drop of port queue", "<port_id> <queue_id> <enable|disable>", SW_API_PT_CONGESTION_DROP_SET, NULL},
+	    {"ringfcthresh", "set", "set flwo ctrl thres of ring", "<ring_id> <on_thres> <off_thres>", SW_API_PT_RING_FLOW_CTRL_THRES_SET, NULL},
+	    {"Ieee8023az", "set", "set 8023az status of a port", "<port_id> <enable|disable>", SW_API_PT_8023AZ_SET, NULL},
+	    {"crossover", "set", "set crossover mode of a port", "<port_id> <auto|mdi|mdix>", SW_API_PT_MDIX_SET, NULL},
+            {"crossover", "get", "get crossover mode of a port", "<port_id>", SW_API_PT_MDIX_GET, NULL},
+            {"crossover", "status", "get current crossover status of a port", "<port_id>", SW_API_PT_MDIX_STATUS_GET, NULL},
+            {"preferMedium", "set", "set prefer medium of a combo port", "<port_id> <copper|fiber>", SW_API_PT_COMBO_PREFER_MEDIUM_SET, NULL},
+            {"preferMedium", "get", "get prefer medium of a combo port", "<port_id>", SW_API_PT_COMBO_PREFER_MEDIUM_GET, NULL},
+            {"mediumType", "get", "get current medium status of a combo port", "<port_id>", SW_API_PT_COMBO_MEDIUM_STATUS_GET, NULL},
+            {"fiberMode", "set", "set fiber mode of a combo fiber port", "<port_id> <100fx|1000bx>", SW_API_PT_COMBO_FIBER_MODE_SET, NULL},
+            {"fiberMode", "get", "get fiber mode of a combo fiber port", "<port_id>", SW_API_PT_COMBO_FIBER_MODE_GET, NULL},
+            {"localLoopback", "set", "set local loopback of a port", "<port_id> <enable|disable>", SW_API_PT_LOCAL_LOOPBACK_SET, NULL},
+            {"localLoopback", "get", "get local loopback of a port", "<port_id>", SW_API_PT_LOCAL_LOOPBACK_GET, NULL},
+            {"remoteLoopback", "set", "set remote loopback of a port", "<port_id> <enable|disable>", SW_API_PT_REMOTE_LOOPBACK_SET, NULL},
+            {"remoteLoopback", "get", "get remote loopback of a port", "<port_id>", SW_API_PT_REMOTE_LOOPBACK_GET, NULL},
+            {"reset", "set", "reset phy of a port", "<port_id>", SW_API_PT_RESET, NULL},
+            {"poweroff", "set", "power off  phy of a port", "<port_id>", SW_API_PT_POWER_OFF, NULL},
+            {"poweron", "set", "power on phy of a port", "<port_id>", SW_API_PT_POWER_ON, NULL},
+            {"magicFrameMac", "set", "set magic frame mac address  of a port", "<port_id> <mac_address>", SW_API_PT_MAGIC_FRAME_MAC_SET, NULL},
+            {"magicFrameMac", "get", "get magic frame mac address  of a port", "<port_id>", SW_API_PT_MAGIC_FRAME_MAC_GET, NULL},
+            {"phyId", "get", "get phy id of a port", "<port_id>", SW_API_PT_PHY_ID_GET, NULL},
+            {"wolstatus", "set", "set wol status of a port", "<port_id> <enable|disable>", SW_API_PT_WOL_STATUS_SET, NULL},
+            {"wolstatus", "get", "get wol status of a port", "<port_id>", SW_API_PT_WOL_STATUS_GET, NULL},
+            {"interfaceMode", "set", "set interface mode of phy", "<port_id> <psgmii_baset|psgmii_bx1000|psgmii_fx100|psgmii_amdet|sgmii_baset>", SW_API_PT_INTERFACE_MODE_SET, NULL},
+            {"interfaceMode", "get", "get interface mode of phy", "<port_id>", SW_API_PT_INTERFACE_MODE_GET, NULL},
+            {"interfaceMode", "status", "get current interface mode of phy", "<port_id>", SW_API_PT_INTERFACE_MODE_STATUS_GET, NULL},
+	        {"counter", "set", "set counter  status of a port", "<port_id> <enable|disable>", SW_API_PT_COUNTER_SET, NULL},
+	        {"counter", "get", "get counter status of a port", "<port_id>", SW_API_PT_COUNTER_GET, NULL},
+	        {"counter", "show", "show counter statistics of a port", "<port_id>", SW_API_PT_COUNTER_SHOW, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL},/*end of desc*/
+        },
+    },
+#endif
+
+    /*vlan*/
+#ifdef IN_VLAN
+    {
+        "vlan", "config VLAN table",
+        {
+            {"entry", "set", "create a VLAN entry", "<vlan_id>", SW_API_VLAN_ADD, NULL},
+            {"entry", "create", "create a VLAN entry", "<vlan_id>", SW_API_VLAN_ADD, NULL},
+            {"entry", "del", "delete a VLAN entryn", "<vlan_id>", SW_API_VLAN_DEL, NULL},
+            {"entry", "update", "update port member of a VLAN entry", "<vlan_id> <member_bitmap> <0>", SW_API_VLAN_MEM_UPDATE, NULL},
+            {"entry", "find", "find a VLAN entry by VLAN id", "<vlan_id>", SW_API_VLAN_FIND, NULL},
+            {"entry", "next", "find next VLAN entry by VLAN id", "<vlan_id>",SW_API_VLAN_NEXT, NULL},
+            {"entry", "append", "append a VLAN entry", "", SW_API_VLAN_APPEND, NULL},
+            {"entry", "flush", "flush all VLAN entries", "",SW_API_VLAN_FLUSH, NULL},
+            {"fid", "set", "set VLAN entry fid", "<vlan_id> <fid>",SW_API_VLAN_FID_SET, NULL},
+            {"member", "set", "add VLAN entry member", "<vlan_id> <port_id> <unmodified|untagged|tagged>",SW_API_VLAN_MEMBER_ADD, NULL},
+            {"member", "add", "add VLAN entry member", "<vlan_id> <port_id> <unmodified|untagged|tagged>",SW_API_VLAN_MEMBER_ADD, NULL},
+            {"member", "del", "del VLAN entry member", "<vlan_id> <port_id>",SW_API_VLAN_MEMBER_DEL, NULL},
+            {"learnsts", "set", "set VLAN entry learn status", "<vlan_id> <enable|disable>",SW_API_VLAN_LEARN_STATE_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /*portvlan*/
+#ifdef IN_PORTVLAN
+    {
+        "portVlan", "config port base VLAN",
+        {
+            {"ingress", "set", "set ingress VLAN mode of a port", "<port_id> <disable|secure|check|fallback>", SW_API_PT_ING_MODE_SET, NULL},
+            {"egress", "set", "set egress VLAN mode of a port", "<port_id> <unmodified|untagged|tagged|hybrid|untouched>", SW_API_PT_EG_MODE_SET, NULL},
+            {"member", "set", "add a member to the port based VLAN of a port", "<port_id> <port_bitmap>", SW_API_PT_VLAN_MEM_UPDATE, NULL},
+            {"member", "add", "add a member to the port based VLAN of a port", "<port_id> <memport_id>", SW_API_PT_VLAN_MEM_ADD, NULL},
+            {"member", "del", "delete a member from the port based VLAN of a port", "<port_id> <memport_id>", SW_API_PT_VLAN_MEM_DEL, NULL},
+            {"member", "update", "update members of the port based VLAN of a port", "<port_id> <port_bitmap>", SW_API_PT_VLAN_MEM_UPDATE, NULL},
+            {"defaultVid", "set", "set default VLAN id of a port", "<port_id> <vid>", SW_API_PT_DEF_VID_SET, NULL},
+            {"forceVid", "set", "set VLAN id enforcement status of a port", "<port_id> <enable|disable>", SW_API_PT_FORCE_DEF_VID_SET, NULL},
+            {"forceMode", "set", "set port based VLAN enforcement status of a port", "<port_id> <enable|disable>", SW_API_PT_FORCE_PORTVLAN_SET, NULL},
+            {"nestVlan", "set", "set nest VLAN status of a port", "<port_id> <enable|disable>", SW_API_PT_NESTVLAN_SET, NULL},
+            {"sVlanTPID", "set", "set service VLAN tpid", "<tpid>", SW_API_NESTVLAN_TPID_SET, NULL},
+            {"invlan", "set", "set port invlan mode", "<port_id> <admit_all|admit_tagged|admit_untagged>", SW_API_PT_IN_VLAN_MODE_SET, NULL},
+            {"tlsMode", "set", "set TLS mode", "<port_id> <enable|disable>", SW_API_PT_TLS_SET, NULL},
+            {"priPropagation", "set", "set priority propagation", "<port_id> <enable|disable>", SW_API_PT_PRI_PROPAGATION_SET, NULL},
+            {"defaultSVid", "set", "set default SVID", "<port_id> <vlan_id>", SW_API_PT_DEF_SVID_SET, NULL},
+            {"defaultCVid", "set", "set default CVID", "<port_id> <vlan_id>", SW_API_PT_DEF_CVID_SET, NULL},
+            {"vlanPropagation", "set", "set vlan propagation", "<port_id> <disable|clone|replace>", SW_API_PT_VLAN_PROPAGATION_SET, NULL},
+            {"translation", "set", "add vlan translation", "<port_id>", SW_API_PT_VLAN_TRANS_ADD, NULL},
+            {"translation", "add", "add vlan translation", "<port_id>", SW_API_PT_VLAN_TRANS_ADD, NULL},
+            {"translation", "del", "del vlan translation", "<port_id>", SW_API_PT_VLAN_TRANS_DEL, NULL},
+            {"translation", "iterate", "iterate vlan translation tables", "<port_id> <iterator>", SW_API_PT_VLAN_TRANS_ITERATE, NULL},
+            {"qinqMode", "set", "set qinq mode", "<ctag|stag>", SW_API_QINQ_MODE_SET, NULL},
+            {"qinqRole", "set", "set qinq role", "<port_id> <edge|core>", SW_API_PT_QINQ_ROLE_SET, NULL},
+            {"macvlanxlt", "set", "set mac vlan xlt status", "<port_id> <enable|disable>", SW_API_PT_MAC_VLAN_XLT_SET, NULL},
+            {"netiso", "set", "enable public/private net isolate", "<enable|disable>", SW_API_NETISOLATE_SET, NULL},
+            {"egbypass", "set", "enable egress translation filter bypass", "<enable|disable>", SW_API_EG_FLTR_BYPASS_EN_SET, NULL},
+            {"ptvrfid", "set", "set port VRF ID", "<port_id> <vrf_id>", SW_API_PT_VRF_ID_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /*fdb*/
+#ifdef IN_FDB
+    {
+        "fdb", "config FDB table",
+        {
+            {"entry", "set", "add a FDB entry", "", SW_API_FDB_ADD, NULL},
+            {"entry", "add", "add a FDB entry", "", SW_API_FDB_ADD, NULL},
+            {"entry", "del", "delete a FDB entry", "", SW_API_FDB_DELMAC, NULL},
+            {"entry", "flush", "flush all FDB entries", "<0:dynamic only|1:dynamic and static>", SW_API_FDB_DELALL, NULL},
+            {"entry", "find", "find a FDB entry", "", SW_API_FDB_FIND, NULL},
+            {"entry", "iterate", "iterate all FDB entries", "<iterator>", SW_API_FDB_ITERATE, NULL},
+            {"entry", "extendnext", "find next FDB entry in extend mode", "", SW_API_FDB_EXTEND_NEXT, NULL},
+            {"entry", "extendfirst", "find first FDB entry in extend mode", "", SW_API_FDB_EXTEND_FIRST, NULL},
+            {"entry", "transfer", "transfer port info in FDB entry", "<old port_id> <new port_id> <fid>", SW_API_FDB_TRANSFER, NULL},
+            {"portEntry", "flush", "flush all FDB entries by a port", "<port_id> <0:dynamic only|1:dynamic and static>", SW_API_FDB_DELPORT, NULL},
+            {"firstEntry", "find", "find the first FDB entry", "", SW_API_FDB_FIRST, NULL},
+            {"nextEntry", "find", "find next FDB entry", "", SW_API_FDB_NEXT, NULL},
+            {"portLearn", "set", "set FDB entry learning status of a port", "<port_id> <enable|disable>", SW_API_FDB_PT_LEARN_SET, NULL},
+            {"ageCtrl", "set", "set FDB entry aging status", "<enable|disable>", SW_API_FDB_AGE_CTRL_SET, NULL},
+            {"vlansmode", "set", "set FDB vlan search mode", "<ivl|svl>", SW_API_FDB_VLAN_IVL_SVL_SET, NULL},
+            {"ageTime", "set", "set FDB entry aging time", "<time:s>", SW_API_FDB_AGE_TIME_SET, NULL},
+            {"ptlearnlimit", "set", "set port FDB entry learn limit", "<port_id> <enable|disable> <limitcounter>", SW_API_PT_FDB_LEARN_LIMIT_SET, NULL},
+            {"ptlearnexceedcmd", "set", "set port forwarding cmd when exceed learn limit", "<port_id> <forward|drop|cpycpu|rdtcpu>", SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, NULL},
+            {"learnlimit", "set", "set FDB entry learn limit", "<enable|disable> <limitcounter>", SW_API_FDB_LEARN_LIMIT_SET, NULL},
+            {"learnexceedcmd", "set", "set forwarding cmd when exceed learn limit", "<forward|drop|cpycpu|rdtcpu>", SW_API_FDB_LEARN_EXCEED_CMD_SET, NULL},
+            {"resventry", "set", "add a reserve FDB entry", "", SW_API_FDB_RESV_ADD, NULL},
+            {"resventry", "add", "add a reserve FDB entry", "", SW_API_FDB_RESV_ADD, NULL},
+            {"resventry", "del", "delete reserve a FDB entry", "", SW_API_FDB_RESV_DEL, NULL},
+            {"resventry", "find", "find a reserve FDB entry", "", SW_API_FDB_RESV_FIND, NULL},
+            {"resventry", "iterate", "iterate all reserve FDB entries", "<iterator>", SW_API_FDB_RESV_ITERATE, NULL},
+            {"ptLearnstatic", "set", "set FDB entry learning static status of a port", "<port_id> <enable|disable>", SW_API_FDB_PT_LEARN_STATIC_SET, NULL},
+            {"port", "add", "add one port to a FDB entry", "<fid> <macaddr> <port_id>", SW_API_FDB_PORT_ADD, NULL},
+            {"port", "del", "del one port from a FDB entry", "<fid> <macaddr> <port_id>", SW_API_FDB_PORT_DEL, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /*acl*/
+#ifdef IN_ACL
+    {
+        "acl", "config ACL",
+        {
+            {"list", "create", "create an ACL list", "<list_id> <priority>", SW_API_ACL_LIST_CREAT, NULL},
+            {"list", "destroy", "destroy an ACL list", "<list_id>", SW_API_ACL_LIST_DESTROY, NULL},
+            {"list", "bind", "bind an ACL list to a port", "<list_id> <0-0:direction> <0-0:objtype> <objindex>", SW_API_ACL_LIST_BIND, NULL},
+            {"list", "unbind", "unbind an ACL list from a port", "<list_id> <0-0:direction> <0-0:objtype> <objindex>", SW_API_ACL_LIST_UNBIND, NULL},
+            {"rule", "add", "add ACL rules to an ACL list", "<list_id> <rule_id> <rule_nr>", SW_API_ACL_RULE_ADD, NULL},
+            {"rule", "del", "delete ACL rules from an ACL list", "<list_id> <rule_id> <rule_nr>", SW_API_ACL_RULE_DELETE, NULL},
+            {"rule", "query", "query a ACL rule", "<list_id> <rule_id>", SW_API_ACL_RULE_QUERY, NULL},
+            {"rule", "active", "active ACL rules in an ACL list", "<list_id> <rule_id> <rule_nr>", SW_API_ACL_RULE_ACTIVE, NULL},
+            {"rule", "deactive", "deactive ACL rules in an ACL list", "<list_id> <rule_id> <rule_nr>", SW_API_ACL_RULE_DEACTIVE, NULL},
+            {"srcfiltersts", "set", "set status of ACL rules source filter", "<rule_id> <enable|disable>", SW_API_ACL_RULE_SRC_FILTER_STS_SET, NULL},
+            {"status", "set", "set status of ACL engine", "<enable|disable>", SW_API_ACL_STATUS_SET, NULL},
+            {"udfprofile", "set", "set port udf profile", "<port_id> <l2/l2snap/l3/l3plus/l4> <offset> <length>", SW_API_ACL_PT_UDF_PROFILE_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /*qos*/
+#ifdef IN_QOS
+    {
+        "qos", "config Qos",
+        {
+#ifndef ISISC
+            {"schMode", "set", "set traffic scheduling mode", "<sp|wrr|mix|mix_plus> <q0,q1,q3,q4>", SW_API_QOS_SCH_MODE_SET, NULL},
+#endif
+            {"qTxBufSts", "set", "set queue tx buffer counting status of a port", "<port_id> <enable|disable>", SW_API_QOS_QU_TX_BUF_ST_SET, NULL},
+#ifdef ISISC
+            {"qTxBufNr", "set", "set queue tx buffer number", "<port_id> <queueid:0-3> <number:0-120>", SW_API_QOS_QU_TX_BUF_NR_SET, NULL},
+#else
+            {"qTxBufNr", "set", "set queue tx buffer number", "<port_id> <queueid:0-3> <number:0-60>", SW_API_QOS_QU_TX_BUF_NR_SET, NULL},
+#endif
+            {"ptTxBufSts", "set", "set port tx buffer counting status of a port", "<port_id> <enable|disable>", SW_API_QOS_PT_TX_BUF_ST_SET, NULL},
+            {"ptRedEn", "set", "set status of port wred of a port", "<port_id> <enable|disable>", SW_API_QOS_PT_RED_EN_SET, NULL},
+#ifdef ISISC
+            {"ptTxBufNr", "set", "set port tx buffer number", "<port_id> <number:0-504>", SW_API_QOS_PT_TX_BUF_NR_SET, NULL},
+#else
+            {"ptTxBufNr", "set", "set port tx buffer number", "<port_id> <number:0-252>", SW_API_QOS_PT_TX_BUF_NR_SET, NULL},
+#endif
+#ifdef ISISC
+            {"ptRxBufNr", "set", "set port rx buffer number", "<port_id> <number:0-120>", SW_API_QOS_PT_RX_BUF_NR_SET, NULL},
+#else
+            {"ptRxBufNr", "set", "set port rx buffer number", "<port_id> <number:0-60>", SW_API_QOS_PT_RX_BUF_NR_SET, NULL},
+#endif
+#ifndef ISISC
+            {"up2q", "set", "set user priority to queue mapping", "<up:0-7> <queueid:0-3>", SW_API_COSMAP_UP_QU_SET, NULL},
+            {"dscp2q", "set", "set dscp to queue mapping", "<dscp:0-63> <queueid:0-3>", SW_API_COSMAP_DSCP_QU_SET, NULL},
+#endif
+#ifdef ISISC
+            {"ptMode", "set", "set Qos mode of a port", "<port_id> <da|up|dscp> <enable|disable>", SW_API_QOS_PT_MODE_SET, NULL},
+            {"ptModePri", "set", "set the priority of Qos modes of a port", "<port_id> <da|up|dscp> <priority:0-3>", SW_API_QOS_PT_MODE_PRI_SET, NULL},
+#else
+            {"ptMode", "set", "set Qos mode of a port", "<port_id> <da|up|dscp|port> <enable|disable>", SW_API_QOS_PT_MODE_SET, NULL},
+            {"ptModePri", "set", "set the priority of Qos modes of a port", "<port_id> <da|up|dscp|port> <priority:0-3>", SW_API_QOS_PT_MODE_PRI_SET, NULL},
+#endif
+#ifndef ISISC
+            {"ptDefaultUp", "set", "set default user priority for received frames of a port", "<port_id> <up:0-7>", SW_API_QOS_PORT_DEF_UP_SET, NULL},
+#endif
+            {"ptschMode", "set", "set port traffic scheduling mode", "<port_id> <sp|wrr|mix|mixplus> <q0,q1,q2,q3,q4,q5>", SW_API_QOS_PORT_SCH_MODE_SET, NULL},
+            {"ptDefaultSpri", "set", "set default stag priority for received frames of a port", "<port_id> <spri:0-7>", SW_API_QOS_PT_DEF_SPRI_SET, NULL},
+            {"ptDefaultCpri", "set", "set default ctag priority for received frames of a port", "<port_id> <cpri:0-7>", SW_API_QOS_PT_DEF_CPRI_SET, NULL},
+            {"ptFSpriSts", "set", "set port force Stag priority status for received frames of a port", "<port_id> <enable|disable>", SW_API_QOS_PT_FORCE_SPRI_ST_SET, NULL},
+            {"ptFCpriSts", "set", "set port force Ctag priority status for received frames of a port", "<port_id> <enable|disable>", SW_API_QOS_PT_FORCE_CPRI_ST_SET, NULL},
+            {"ptQuRemark", "set", "set egress queue based remark", "<port_id> <queue_id> <table_id> <enable|disable>", SW_API_QOS_QUEUE_REMARK_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /*igmp*/
+#ifdef IN_IGMP
+    {
+        "igmp", "config IGMP/MLD",
+        {
+            {"mode", "set", "set IGMP/MLD snooping status of a port", "<port_id> <enable|disable>", SW_API_PT_IGMPS_MODE_SET, NULL},
+            {"cmd", "set", "set IGMP/MLD frames forwarding command", "<forward|drop|cpycpu|rdtcpu>", SW_API_IGMP_MLD_CMD_SET, NULL},
+            {"portJoin", "set", "set IGMP/MLD hardware joining status", "<port_id> <enable|disable>", SW_API_IGMP_PT_JOIN_SET, NULL},
+            {"portLeave", "set", "set IGMP/MLD hardware leaving status", "<port_id> <enable|disable>", SW_API_IGMP_PT_LEAVE_SET, NULL},
+            {"rp", "set", "set IGMP/MLD router ports", "<port_bit_map>", SW_API_IGMP_RP_SET, NULL},
+            {"createStatus", "set", "set IGMP/MLD ability for creating entry", "<enable|disable>", SW_API_IGMP_ENTRY_CREAT_SET, NULL},
+            {"static", "set", "set IGMP/MLD static status for creating entry", "<enable|disable>", SW_API_IGMP_ENTRY_STATIC_SET, NULL},
+            {"leaky", "set", "set IGMP/MLD leaky status for creating entry", "<enable|disable>", SW_API_IGMP_ENTRY_LEAKY_SET, NULL},
+            {"version3", "set", "set IGMP v3/MLD v2 status for creating entry", "<enable|disable>", SW_API_IGMP_ENTRY_V3_SET, NULL},
+            {"queue", "set", "set IGMP/MLD queue status for creating entry", "<enable|disable> <queue_id>", SW_API_IGMP_ENTRY_QUEUE_SET, NULL},
+            {"ptlearnlimit", "set", "set port Multicast entry learn limit", "<port_id> <enable|disable> <limitcounter>", SW_API_PT_IGMP_LEARN_LIMIT_SET, NULL},
+            {"ptlearnexceedcmd", "set", "set port forwarding cmd when exceed multicast learn limit", "<port_id> <forward|drop|cpycpu|rdtcpu>", SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, NULL},
+            {"multi", "set", "set igmp/mld entry", "<entry>", SW_API_IGMP_SG_ENTRY_SET, NULL},
+            {"multi", "clear", "clear igmp/mld entry", "<entry>", SW_API_IGMP_SG_ENTRY_CLEAR, NULL},
+            {"multi", "show", "show all igmp/mld entry", "", SW_API_IGMP_SG_ENTRY_SHOW, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /*leaky*/
+#ifdef IN_LEAKY
+    {
+        "leaky", "config leaky",
+        {
+            {"ucMode", "set", "set unicast packets leaky mode", "<port|fdb>", SW_API_UC_LEAKY_MODE_SET, NULL},
+            {"mcMode", "set", "set multicast packets leaky mode", "<port|fdb>", SW_API_MC_LEAKY_MODE_SET, NULL},
+            {"arpMode", "set", "set arp packets leaky mode", "<port_id> <enable|disable>", SW_API_ARP_LEAKY_MODE_SET, NULL},
+            {"ptUcMode", "set", "set unicast packets leaky status of a port", "<port_id> <enable|disable>", SW_API_PT_UC_LEAKY_MODE_SET, NULL},
+            {"ptMcMode", "set", "set multicast packets leaky status of a port", "<port_id> <enable|disable>", SW_API_PT_MC_LEAKY_MODE_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /*mirror*/
+#ifdef IN_MIRROR
+    {
+        "mirror", "config mirror",
+        {
+            {"analyPt", "set", "set mirror analysis port", "<port_id>", SW_API_MIRROR_ANALY_PT_SET, NULL},
+            {"ptIngress", "set", "set ingress mirror status of a port", "<port_id> <enable|disable>", SW_API_MIRROR_IN_PT_SET, NULL},
+            {"ptEgress", "set", "set egress mirror status of a port", "<port_id> <enable|disable>", SW_API_MIRROR_EG_PT_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /*rate*/
+#ifdef IN_RATE
+    {
+        "rate", "config rate limit",
+        {
+#ifndef ISISC
+            {"qEgress", "set", "set egress rate limit of a queue", "<port_id> <queueid:0-3> <speed:(kbps)> <enable|disable>", SW_API_RATE_QU_EGRL_SET, NULL},
+            {"ptEgress", "set", "set egress rate limit of a port", "<port_id> <speed:(kbps)> <enable|disable>", SW_API_RATE_PT_EGRL_SET, NULL},
+            {"ptIngress", "set", "set ingress rate limit of a port", "<port_id> <speed:(kbps)> <enable|disable>", SW_API_RATE_PT_INRL_SET, NULL},
+            {"stormCtrl", "set", "set storm control status of a particular frame type", "<port_id> <unicast|multicast|broadcast> <enable|disable>", SW_API_STORM_CTRL_FRAME_SET, NULL},
+            {"stormCtrlRate", "set", "set storm ctrl rate", "<port_id> <rate:(packets/s)>", SW_API_STORM_CTRL_RATE_SET, NULL},
+#endif
+            {"portpolicer", "set", "set port policer", "<port_id>", SW_API_RATE_PORT_POLICER_SET, NULL},
+            {"portshaper", "set", "set port egress shaper", "<port_id> <enable|disable>", SW_API_RATE_PORT_SHAPER_SET, NULL},
+            {"queueshaper", "set", "set queue egress shaper", "<port_id> <queue_id> <enable|disable>", SW_API_RATE_QUEUE_SHAPER_SET, NULL},
+            {"aclpolicer", "set", "set acl policer", "<policer_id>", SW_API_RATE_ACL_POLICER_SET, NULL},
+            {"ptAddRateByte", "set", "set add_rate_byte when cal rate ", "<port_id> <number:0-255>", SW_API_RATE_PT_ADDRATEBYTE_SET, NULL},
+            {"ptgolflowen", "set", "set status of port globle flow control", "<port_id> <enable|disable>", SW_API_RATE_PT_GOL_FLOW_EN_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+#ifdef IN_SEC
+#ifdef ISISC
+    {
+        "sec", "config security",
+        {
+            {"mac", "set", "set MAC layer related security", "<resv_vid/invalid_src_addr> <value>", SW_API_SEC_MAC_SET, NULL},
+            {"ip", "set", "set IP layer related security", "<invalid_ver/same_addr/ttl_change_status/ttl_val> <value>", SW_API_SEC_IP_SET, NULL},
+            {"ip4", "set", "set IP4 related security", "<invalid_hl/hdr_opts/invalid_df/frag_offset_min_len/frag_offset_min_size/frag_offset_max_len/invalid_frag_offset/invalid_sip/invalid_dip/invalid_chksum/invalid_pl/df_clear_status/ipid_random_status> <value>", SW_API_SEC_IP4_SET, NULL},
+            {"ip6", "set", "set IP6 related security", "<invalid_dip/invalid_sip/invalid_pl> <value>", SW_API_SEC_IP6_SET, NULL},
+            {"tcp", "set", "set TCP related security", "<blat/invalid_hl/min_hdr_size/invalid_syn/su_block/sp_block/sap_block/xmas_scan/null_scan/sr_block/sf_block/sar_block/rst_scan/rst_with_data/fa_block/pa_block/ua_block/invalid_chksum/invalid_urgptr/invalid_opts> <value>", SW_API_SEC_TCP_SET, NULL},
+            {"udp", "set", "set UDP related security", "<blat/invalid_len/invalid_chksum> <value>", SW_API_SEC_UDP_SET, NULL},
+            {"icmp4", "set", "set ICMP4 related security", "<ping_pl_exceed/ping_frag/ping_max_pl> <value>", SW_API_SEC_ICMP4_SET, NULL},
+            {"icmp6", "set", "set ICMP6 related security", "<ping_pl_exceed/ping_frag/ping_max_pl> <value>", SW_API_SEC_ICMP6_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+#endif
+
+    /*stp*/
+#ifdef IN_STP
+    {
+        "stp", "config STP",
+        {
+            {"portState", "set", "set STP state of a port", "<st_id> <port_id> <disable|block|listen|learn|forward>", SW_API_STP_PT_STATE_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /*mib*/
+#ifdef IN_MIB
+    {
+        "mib", "show MIB statistics information",
+        {
+            {"status", "set", "set mib status", "<enable|disable>",  SW_API_MIB_STATUS_SET, NULL},
+            {"counters",  "flush", "flush counters of a port", "<port_id>", SW_API_PT_MIB_FLUSH_COUNTERS, NULL},
+            {"cpuKeep", "set", "set cpu keep bit", "<enable|disable>",  SW_API_MIB_CPU_KEEP_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /* led */
+#ifdef IN_LED
+    {
+        "led", "set/get led control pattern",
+        {
+            {"ctrlpattern", "set", "set led control pattern", "<group_id> <led_id>", SW_API_LED_PATTERN_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /* cosmap */
+#ifdef IN_COSMAP
+    {
+        "cosmap", "set/get cosmap table",
+        {
+            {"dscp2pri", "set", "set dscp to priority map table", "<dscp> <priority>", SW_API_COSMAP_DSCP_TO_PRI_SET, NULL},
+            {"dscp2dp", "set", "set dscp to dp map table", "<dscp> <dp>", SW_API_COSMAP_DSCP_TO_DP_SET, NULL},
+            {"up2pri", "set", "set dot1p to priority map table", "<up> <priority>", SW_API_COSMAP_UP_TO_PRI_SET, NULL},
+            {"up2dp", "set", "set dot1p to dp map table", "<up> <dp>", SW_API_COSMAP_UP_TO_DP_SET, NULL},
+            {"dscp2ehpri", "set", "set dscp to priority map table for WAN port", "<dscp> <priority>", SW_API_COSMAP_DSCP_TO_EHPRI_SET, NULL},
+            {"dscp2ehdp", "set", "set dscp to dp map table for WAN port", "<dscp> <dp>", SW_API_COSMAP_DSCP_TO_EHDP_SET, NULL},
+            {"up2ehpri", "set", "set dot1p to priority map table for WAN port", "<up> <priority>", SW_API_COSMAP_UP_TO_EHPRI_SET, NULL},
+            {"up2ehdp", "set", "set dot1p to dp map table for WAN port", "<up> <dp>", SW_API_COSMAP_UP_TO_EHDP_SET, NULL},
+            {"pri2q", "set", "set priority to queue mapping", "<priority> <queueid>", SW_API_COSMAP_PRI_TO_QU_SET, NULL},
+            {"pri2ehq", "set", "set priority to enhanced queue mapping", "<priority> <queueid>", SW_API_COSMAP_PRI_TO_EHQU_SET, NULL},
+            {"egRemark", "set", "set egress remark table", "<tableid>", SW_API_COSMAP_EG_REMARK_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /*misc*/
+#ifdef IN_MISC
+    {
+        "misc", "config miscellaneous",
+        {
+#ifndef ISISC
+            {"arp", "set", "set arp packets hardware identification status", "<enable|disable>", SW_API_ARP_STATUS_SET, NULL},
+#endif
+            {"frameMaxSize", "set", "set the maximal received frame size of the device", "<size:byte>", SW_API_FRAME_MAX_SIZE_SET, NULL},
+#ifndef ISISC
+            {"ptUnkSaCmd", "set", "set forwarding command for frames with unknown source address", "<port_id> <forward|drop|cpycpu|rdtcpu>", SW_API_PT_UNK_SA_CMD_SET, NULL},
+#endif
+            {"ptUnkUcFilter", "set", "set flooding status of unknown unicast frames", "<port_id> <enable|disable>", SW_API_PT_UNK_UC_FILTER_SET, NULL},
+            {"ptUnkMcFilter", "set", "set flooding status of unknown multicast frames", "<port_id> <enable|disable>", SW_API_PT_UNK_MC_FILTER_SET, NULL},
+            {"ptBcFilter", "set", "set flooding status of broadcast frames", "<port_id> <enable|disable>", SW_API_PT_BC_FILTER_SET, NULL},
+            {"cpuPort", "set", "set cpu port status", "<enable|disable>", SW_API_CPU_PORT_STATUS_SET, NULL},
+#ifndef ISISC
+            {"bctoCpu", "set", "set broadcast frames to Cpu port status", "<enable|disable>", SW_API_BC_TO_CPU_PORT_SET, NULL},
+#endif
+#ifdef ISISC
+            {"PppoeCmd", "set", "set pppoe frames forwarding command", "<forward|rdtcpu>", SW_API_PPPOE_CMD_SET, NULL},
+#else
+            {"PppoeCmd", "set", "set pppoe frames forwarding command", "<forward|drop|cpycpu|rdtcpu>", SW_API_PPPOE_CMD_SET, NULL},
+#endif
+            {"Pppoe", "set", "set pppoe frames hardware identification status", "<enable|disable>", SW_API_PPPOE_STATUS_SET, NULL},
+            {"ptDhcp", "set", "set dhcp frames hardware identification status", "<port_id> <enable|disable>", SW_API_PT_DHCP_SET, NULL},
+#ifdef ISISC
+            {"arpcmd", "set", "set arp packets forwarding command", "<forward|cpycpu|rdtcpu>", SW_API_ARP_CMD_SET, NULL},
+#else
+            {"arpcmd", "set", "set arp packets forwarding command", "<forward|drop|cpycpu|rdtcpu>", SW_API_ARP_CMD_SET, NULL},
+#endif
+#ifdef ISISC
+            {"eapolcmd", "set", "set eapol packets forwarding command", "<cpycpu|rdtcpu>", SW_API_EAPOL_CMD_SET, NULL},
+#else
+            {"eapolcmd", "set", "set eapol packets forwarding command", "<forward|drop|cpycpu|rdtcpu>", SW_API_EAPOL_CMD_SET, NULL},
+#endif
+#ifndef ISISC
+            {"pppoesession", "add", "add a pppoe session entry", "<session_id> <enable|disable>", SW_API_PPPOE_SESSION_ADD, NULL},
+            {"pppoesession", "del", "del a pppoe session entry", "<session_id>", SW_API_PPPOE_SESSION_DEL, NULL},
+#endif
+            {"eapolstatus", "set", "set eapol frames hardware identification status", "<port_id> <enable|disable>", SW_API_EAPOL_STATUS_SET, NULL},
+            {"rip", "set", "set rip packets copy to cpu status", "<enable|disable>", SW_API_RIPV1_STATUS_SET, NULL},
+            {"ptarpreq", "set", "set arp request packets hardware identification status", "<port_id> <enable|disable>", SW_API_PT_ARP_REQ_STATUS_SET, NULL},
+            {"ptarpack", "set", "set arp ack packets hardware identification status", "<port_id> <enable|disable>", SW_API_PT_ARP_ACK_STATUS_SET, NULL},
+            {"extendpppoe", "set", "add a pppoe session entry", "", SW_API_PPPOE_SESSION_TABLE_ADD, NULL},
+            {"extendpppoe", "add", "add a pppoe session entry", "", SW_API_PPPOE_SESSION_TABLE_ADD, NULL},
+            {"extendpppoe", "del", "del a pppoe session entry", "", SW_API_PPPOE_SESSION_TABLE_DEL, NULL},
+            {"pppoeid", "set", "set a pppoe session id entry", "<index> <id>", SW_API_PPPOE_SESSION_ID_SET, NULL},
+            {"intrmask", "set", "set switch interrupt mask", "<intr_mask>", SW_API_INTR_MASK_SET, NULL},
+            {"intrstatus", "clear", "clear switch interrupt status", "<intr_mask>", SW_API_INTR_STATUS_CLEAR, NULL},
+            {"intrportlinkmask", "set", "set link interrupt mask of a port", "<port_id> <intr_mask>", SW_API_INTR_PORT_LINK_MASK_SET, NULL},
+            {"intrmaskmaclinkchg", "set", "set switch interrupt mask for mac link change", "<port_id> <enable | disable>", SW_API_INTR_MASK_MAC_LINKCHG_SET, NULL},
+            {"intrstatusmaclinkchg", "clear", "clear switch interrupt status for mac link change", "", SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, NULL},
+            {"cpuVid", "set", "set to_cpu vid status", "<enable|disable>", SW_API_CPU_VID_EN_SET, NULL},
+            {"rtdPppoe", "set", "set RM_RTD_PPPOE_EN status", "<enable|disable>", SW_API_RTD_PPPOE_EN_SET, NULL},
+			{"glomacaddr", "set", "set global macaddr", "<macaddr>", SW_API_GLOBAL_MACADDR_SET, NULL},
+			{"lldp", "set", "set lldp frames hardware identification status", "<enable|disable>", SW_API_LLDP_STATUS_SET, NULL},
+			{"framecrc", "set", "set frame crc reserve enable", "<enable|disable>", SW_API_FRAME_CRC_RESERVE_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /* IP */
+#ifdef IN_IP
+    {
+        "ip", "config ip",
+        {
+            {"hostentry", "set", "add host entry", "", SW_API_IP_HOST_ADD, NULL},
+            {"hostentry", "add", "add host entry", "", SW_API_IP_HOST_ADD, NULL},
+            {"hostentry", "del", "del host entry", "<del_mode>", SW_API_IP_HOST_DEL, NULL},
+            {"hostentry", "next", "next host entry", "<next_mode>", SW_API_IP_HOST_NEXT, NULL},
+            {"hostentry", "bindcnt", "bind counter to host entry", "<host entry id> <cnt id> <enable|disable>", SW_API_IP_HOST_COUNTER_BIND, NULL},
+            {"hostentry", "bindpppoe", "bind pppoe to host entry", "<host entry id> <pppoe id> <enable|disable>", SW_API_IP_HOST_PPPOE_BIND, NULL},
+            {"ptarplearn", "set", "set port arp learn flag, bit0 req bit1 ack", "<port_id> <flag>", SW_API_IP_PT_ARP_LEARN_SET, NULL},
+            {"arplearn",   "set", "set arp learn mode", "<learnlocal|learnall>", SW_API_IP_ARP_LEARN_SET, NULL},
+            {"ptipsrcguard",   "set", "set ip source guard mode", "<port_id> <mac_ip|mac_ip_port|mac_ip_vlan|mac_ip_port_vlan|no_guard>", SW_API_IP_SOURCE_GUARD_SET, NULL},
+            {"ptarpsrcguard",  "set", "set arp source guard mode", "<port_id> <mac_ip|mac_ip_port|mac_ip_vlan|mac_ip_port_vlan|no_guard>", SW_API_IP_ARP_GUARD_SET, NULL},
+            {"routestatus", "set", "set ip route status", "<enable|disable>", SW_API_IP_ROUTE_STATUS_SET, NULL},
+            {"intfentry", "set", "add interface mac address", "", SW_API_IP_INTF_ENTRY_ADD, NULL},
+            {"intfentry", "add", "add interface mac address", "", SW_API_IP_INTF_ENTRY_ADD, NULL},
+            {"intfentry", "del", "del interface mac address", "", SW_API_IP_INTF_ENTRY_DEL, NULL},
+            {"ipunksrc", "set", "set ip unkown source command", "<forward|drop|cpycpu|rdtcpu>", SW_API_IP_UNK_SOURCE_CMD_SET, NULL},
+            {"arpunksrc", "set", "set arp unkown source command", "<forward|drop|cpycpu|rdtcpu>", SW_API_ARP_UNK_SOURCE_CMD_SET, NULL},
+            {"ipagetime", "set", "set dynamic ip entry age time", "<time>", SW_API_IP_AGE_TIME_SET, NULL},
+            {"wcmphashmode", "set", "set wcmp hash mode", "<hashmode>", SW_API_WCMP_HASH_MODE_SET, NULL},
+            {"wcmpentry", "set", "set wcmp entry", "<wcmp_id>", SW_API_IP_WCMP_ENTRY_SET, NULL},
+            {"vrfbaseaddr", "set", "set vrf prv base address", "<ip4 addr>", SW_API_IP_VRF_BASE_ADDR_SET, NULL},
+            {"vrfbasemask", "set", "set vrf prv base mask", "<ip4 addr>", SW_API_IP_VRF_BASE_MASK_SET, NULL},
+            {"defaultroute", "set", "set default route entry", "", SW_API_IP_DEFAULT_ROUTE_SET, NULL},
+            {"hostroute", "set", "set host route entry", "", SW_API_IP_HOST_ROUTE_SET, NULL},
+            {"rfsip4", "set", "set rfs ip4", "", SW_API_IP_RFS_IP4_SET, NULL},
+            {"rfsip6", "set", "set rfs ip6", "", SW_API_IP_RFS_IP6_SET, NULL},
+            {"defaultflowcmd", "set", "set default flow command", "<vrf id> <lan2lan|wan2lan|lan2wan|wan2wan> <forward|drop|rdtcpu|admit_all>", SW_API_IP_DEFAULT_FLOW_CMD_SET, NULL},
+            {"defaultrtflowcmd", "set", "set default route flow command", "<vrf id> <lan2lan|wan2lan|lan2wan|wan2wan> <forward|drop|rdtcpu|admit_all>", SW_API_IP_DEFAULT_RT_FLOW_CMD_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /* NAT */
+#ifdef IN_NAT
+    {
+        "nat", "config nat",
+        {
+            {"natentry", "set", "add nat entry", "", SW_API_NAT_ADD, NULL},
+            {"natentry", "add", "add nat entry", "", SW_API_NAT_ADD, NULL},
+            {"natentry", "del", "del nat entry", "<del_mode>", SW_API_NAT_DEL, NULL},
+            {"natentry", "next", "next nat entry", "<next_mode>", SW_API_NAT_NEXT, NULL},
+            {"natentry", "bindcnt", "bind counter to nat entry", "<nat entry id> <cnt id> <enable|disable>", SW_API_NAT_COUNTER_BIND, NULL},
+            {"naptentry", "set", "add napt entry", "", SW_API_NAPT_ADD, NULL},
+            {"naptentry", "add", "add napt entry", "", SW_API_NAPT_ADD, NULL},
+            {"naptentry", "del", "del napt entry", "<del_mode>", SW_API_NAPT_DEL, NULL},
+            {"naptentry", "next", "next napt entry", "<next_mode>", SW_API_NAPT_NEXT, NULL},
+            {"naptentry", "bindcnt", "bind counter to napt entry", "<napt entry id> <cnt id> <enable|disable>", SW_API_NAPT_COUNTER_BIND, NULL},
+            {"natstatus", "set", "set nat status", "<enable|disable>", SW_API_NAT_STATUS_SET, NULL},
+            {"naptstatus", "set", "set napt status", "<enable|disable>", SW_API_NAPT_STATUS_SET, NULL},
+            {"nathash", "set", "set nat hash mode", "<flag>", SW_API_NAT_HASH_MODE_SET, NULL},
+            {"naptmode", "set", "set napt mode", "<fullcone|strictcone|portstrict|synmatric>", SW_API_NAPT_MODE_SET, NULL},
+            {"prvbaseaddr", "set", "set nat prv base address", "<ip4 addr>", SW_API_PRV_BASE_ADDR_SET, NULL},
+            {"prvaddrmode", "set", "set nat prv address map mode", "<enable|disable>", SW_API_PRV_ADDR_MODE_SET, NULL},
+            {"pubaddr", "set", "add pub address", "", SW_API_PUB_ADDR_ENTRY_ADD, NULL},
+            {"pubaddr", "add", "add pub address", "", SW_API_PUB_ADDR_ENTRY_ADD, NULL},
+            {"pubaddr", "del", "del pub address", "<del_mode>", SW_API_PUB_ADDR_ENTRY_DEL, NULL},
+            {"natunksess", "set", "set nat unkown session command", "<forward|drop|cpycpu|rdtcpu>", SW_API_NAT_UNK_SESSION_CMD_SET, NULL},
+            {"prvbasemask", "set", "set nat prv base mask", "<ip4 mask>", SW_API_PRV_BASE_MASK_SET, NULL},
+			{"global", "set", "set global nat function", "<enable|disable> <enable:sync counter|disable:unsync counter>", SW_API_NAT_GLOBAL_SET, NULL},
+			{"flowentry", "set", "add flow entry", "", SW_API_FLOW_ADD, NULL},
+			{"flowentry", "add", "add flow entry", "", SW_API_FLOW_ADD, NULL},
+            {"flowentry", "del", "del flow entry", "<del_mode>", SW_API_FLOW_DEL, NULL},
+			{"flowentry", "next", "next flow entry", "<next_mode>", SW_API_FLOW_NEXT, NULL},
+			{"flowcookie", "set", "set flow cookie", "", SW_API_FLOW_COOKIE_SET, NULL},
+			{"flowrfs", "set", "set flow rfs", "<action>", SW_API_FLOW_RFS_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /*Trunk*/
+#ifdef IN_TRUNK
+    {
+        "trunk", "config trunk",
+        {
+            {"group", "set", "set trunk group member info", "<trunk_id> <disable|enable> <port_bitmap>", SW_API_TRUNK_GROUP_SET, NULL},
+            {"hashmode", "set", "set trunk hash mode", "<hash_mode>", SW_API_TRUNK_HASH_SET, NULL},
+            {"mansa", "set", "set trunk manipulable sa", "<macaddr>", SW_API_TRUNK_MAN_SA_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /*Interface Control*/
+#ifdef IN_INTERFACECONTROL
+    {
+        "interface", "config interface",
+        {
+            {"macmode", "set", "set mac mode info", "<port_id>", SW_API_MAC_MODE_SET, NULL},
+            {"pt3azstatus", "set", "get mac mode info", "<port_id> <enable/disable>", SW_API_PORT_3AZ_STATUS_SET, NULL},
+            {"phymode", "set", "set phy mode info", "<phy_id>", SW_API_PHY_MODE_SET, NULL},
+            {"fx100ctrl", "set", "set fx100 config", "", SW_API_FX100_CTRL_SET, NULL},
+            {"mac06exch", "set", "set mac0 and mac6 exchange status", "<enable/disable>", SW_API_MAC06_EXCH_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+#endif
+
+    /* debug */
+    {
+        "debug", "read/write register",
+        {
+            {"phy", "get", "read phy register", "<ph_id> <reg_addr>", SW_API_PHY_GET, NULL},
+            {"phy", "set", "write phy register", "<ph_id> <reg_addr> <value>", SW_API_PHY_SET, NULL},
+            {"reg", "get", "read switch register", "<reg_addr> <4>", SW_API_REG_GET, NULL},
+            {"reg", "set", "write switch register", "<reg_addr> <value> <4>", SW_API_REG_SET, NULL},
+			{"reg", "dump", "dump switch register group", "<group id> <0-6>", SW_API_REG_DUMP, NULL},
+			{"dbgreg", "dump", "dump switch dbg register group", "", SW_API_DBG_REG_DUMP, NULL},
+            {"field", "get", "read switch register field", "<reg_addr> <offset> <len> <4>", SW_API_REG_FIELD_GET, NULL},
+            {"field", "set", "write switch register field", "<reg_addr> <offset> <len> <value> <4>", SW_API_REG_FIELD_SET, NULL},
+            {"aclList", "dump", "dump all acl list", "", SW_API_ACL_LIST_DUMP, NULL},
+            {"aclRule", "dump", "dump all acl rule", "", SW_API_ACL_RULE_DUMP, NULL},
+            {"device",  "reset", "reset device",     "", SW_API_SWITCH_RESET, NULL},
+            {"ssdk",  "config", "show ssdk configuration",     "", SW_API_SSDK_CFG, NULL},
+            {"preg", "get", "read psgmii register", "<reg_addr> <4>", SW_API_PSGMII_REG_GET, NULL},
+            {"preg", "set", "write psgmii register", "<reg_addr> <value> <4>", SW_API_PSGMII_REG_SET, NULL},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+
+    /*debug*/
+    {
+        "device", "set device id",
+        {
+            {"id", "set", "set device id", "<dev_id>", SW_CMD_SET_DEVID, cmd_set_devid},
+            {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+        },
+    },
+
+    {"help", "type ? get help", {{NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/}},
+
+    {"quit", "type quit/q quit shell", {{NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/}},
+
+    {NULL, NULL, {{NULL, NULL, NULL, NULL, (int)NULL, NULL}}} /*end of desc*/
+};
+#else
+
+#ifdef IN_PORTCONTROL
+struct sub_cmd_des_t g_port_des[] =
+{
+	{"duplex", "set",   SW_API_PT_DUPLEX_SET, NULL},
+	{"speed", "set",   SW_API_PT_SPEED_SET, NULL},
+	{"autoNeg", "enable",   SW_API_PT_AN_ENABLE, NULL},
+	{"autoAdv", "set",   SW_API_PT_AN_ADV_SET, NULL},
+	{"autoNeg", "restart",   SW_API_PT_AN_RESTART, NULL},
+	{"autoNegenable", "set",   SW_API_PT_AN_ENABLE, NULL},
+	{"autoNegrestart", "set",   SW_API_PT_AN_RESTART, NULL},
+	#ifndef IN_PORTCONTROL_MINI
+	{"header", "set",   SW_API_PT_HDR_SET, NULL},
+	#endif
+	{"txhdr", "set",   SW_API_PT_TXHDR_SET, NULL},
+	{"rxhdr", "set",   SW_API_PT_RXHDR_SET, NULL},
+	{"hdrtype", "set",   SW_API_HEADER_TYPE_SET, NULL},
+	{"poweroff", "set",   SW_API_PT_POWER_OFF, NULL},
+	{"poweron", "set",   SW_API_PT_POWER_ON, NULL},
+	#ifndef IN_PORTCONTROL_MINI
+	{"flowCtrl", "set",   SW_API_PT_FLOWCTRL_SET, NULL},
+	{"flowCtrlforcemode", "set",   SW_API_PT_FLOWCTRL_MODE_SET, NULL},
+	{"powersave", "set",   SW_API_PT_POWERSAVE_SET, NULL},
+	{"hibernate", "set",   SW_API_PT_HIBERNATE_SET, NULL},
+	{"cdt", "run",   SW_API_PT_CDT, NULL},
+	{"txmacstatus", "set",   SW_API_TXMAC_STATUS_SET, NULL},
+	{"rxmacstatus", "set",   SW_API_RXMAC_STATUS_SET, NULL},
+	{"txfcstatus", "set",   SW_API_TXFC_STATUS_SET, NULL},
+	{"rxfcstatus", "set",   SW_API_RXFC_STATUS_SET, NULL},
+	{"bpstatus", "set",   SW_API_BP_STATUS_SET, NULL},
+	{"linkforcemode", "set",   SW_API_PT_LINK_MODE_SET, NULL},
+	{"macLoopback", "set",   SW_API_PT_MAC_LOOPBACK_SET, NULL},
+	{"congedrop", "set",   SW_API_PT_CONGESTION_DROP_SET, NULL},
+	{"ringfcthresh", "set",   SW_API_PT_RING_FLOW_CTRL_THRES_SET, NULL},
+	{"Ieee8023az", "set",   SW_API_PT_8023AZ_SET, NULL},
+	{"crossover", "set",   SW_API_PT_MDIX_SET, NULL},
+	{"preferMedium", "set",   SW_API_PT_COMBO_PREFER_MEDIUM_SET, NULL},
+	{"fiberMode", "set",   SW_API_PT_COMBO_FIBER_MODE_SET, NULL},
+	{"localLoopback", "set",   SW_API_PT_LOCAL_LOOPBACK_SET, NULL},
+	{"remoteLoopback", "set",   SW_API_PT_REMOTE_LOOPBACK_SET, NULL},
+	{"reset", "set",   SW_API_PT_RESET, NULL},
+	{"magicFrameMac", "set",   SW_API_PT_MAGIC_FRAME_MAC_SET, NULL},
+	{"wolstatus", "set",   SW_API_PT_WOL_STATUS_SET, NULL},
+	{"interfaceMode", "set",   SW_API_PT_INTERFACE_MODE_SET, NULL},
+	{"InterfaceModeApply", "set",   SW_API_PT_INTERFACE_MODE_APPLY, NULL},
+	{"mtu", "set",   SW_API_PT_MTU_SET, NULL},
+	{"mru", "set",   SW_API_PT_MRU_SET, NULL},
+	{"srcfilter", "set",   SW_API_PT_SOURCE_FILTER_SET, NULL},
+	{"frameMaxSize", "set",   SW_API_PT_FRAME_MAX_SIZE_SET, NULL},
+	{"interface3az", "set", SW_API_PT_INTERFACE_3AZ_STATUS_SET, NULL},
+	{"promiscmode", "set",   SW_API_PT_PROMISC_MODE_SET, NULL},
+	{"eeecfg", "set", SW_API_PT_INTERFACE_EEE_CFG_SET, NULL},
+	{"srcfiltercfg", "set",   SW_API_PT_SOURCE_FILTER_CONFIG_SET, NULL},
+	{"switchportloopback", "set", SW_API_PT_SWITCH_PORT_LOOPBACK_SET, NULL},
+	#endif
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_VLAN
+struct sub_cmd_des_t g_vlan_des[] =
+{
+	{"entry", "set",   SW_API_VLAN_ADD, NULL},
+	{"entry", "create",   SW_API_VLAN_ADD, NULL},
+	{"entry", "del",   SW_API_VLAN_DEL, NULL},
+	{"entry", "update",   SW_API_VLAN_MEM_UPDATE, NULL},
+	{"entry", "append",   SW_API_VLAN_APPEND, NULL},
+	{"entry", "flush",  SW_API_VLAN_FLUSH, NULL},
+	{"fid", "set",  SW_API_VLAN_FID_SET, NULL},
+	{"member", "set",  SW_API_VLAN_MEMBER_ADD, NULL},
+	{"member", "add",  SW_API_VLAN_MEMBER_ADD, NULL},
+	{"member", "del",  SW_API_VLAN_MEMBER_DEL, NULL},
+	#ifndef IN_VLAN_MINI
+	{"learnsts", "set",  SW_API_VLAN_LEARN_STATE_SET, NULL},
+	#endif
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_PORTVLAN
+struct sub_cmd_des_t g_portvlan_des[] =
+{
+	{"ingress", "set",   SW_API_PT_ING_MODE_SET, NULL},
+	{"egress", "set",   SW_API_PT_EG_MODE_SET, NULL},
+	{"member", "set",   SW_API_PT_VLAN_MEM_UPDATE, NULL},
+	{"member", "add",   SW_API_PT_VLAN_MEM_ADD, NULL},
+	{"member", "del",   SW_API_PT_VLAN_MEM_DEL, NULL},
+	{"member", "update",   SW_API_PT_VLAN_MEM_UPDATE, NULL},
+	{"defaultVid", "set",   SW_API_PT_DEF_VID_SET, NULL},
+	{"forceVid", "set",   SW_API_PT_FORCE_DEF_VID_SET, NULL},
+	{"forceMode", "set",   SW_API_PT_FORCE_PORTVLAN_SET, NULL},
+	{"nestVlan", "set",   SW_API_PT_NESTVLAN_SET, NULL},
+	{"sVlanTPID", "set",   SW_API_NESTVLAN_TPID_SET, NULL},
+	{"invlan", "set",   SW_API_PT_IN_VLAN_MODE_SET, NULL},
+	{"globalQinQMode", "set", SW_API_GLOBAL_QINQ_MODE_SET, NULL},
+	{"ptQinQMode", "set", SW_API_PORT_QINQ_MODE_SET, NULL},
+#ifdef HPPE
+	{"inTpid", "set", SW_API_TPID_SET, NULL},
+	{"egTpid", "set", SW_API_EGRESS_TPID_SET, NULL},
+	{"ingressFilter", "set", SW_API_PT_INGRESS_VLAN_FILTER_SET, NULL},
+	{"defaultVlanTag", "set", SW_API_PT_DEFAULT_VLANTAG_SET, NULL},
+	{"tagPropagation", "set", SW_API_PT_TAG_PROPAGATION_SET, NULL},
+	{"translationMissAction", "set", SW_API_PT_VLAN_XLT_MISS_CMD_SET, NULL},
+	{"egMode", "set", SW_API_PT_VLANTAG_EGMODE_SET, NULL},
+	{"vsiEgMode", "set", SW_API_PT_VSI_EGMODE_SET, NULL},
+	{"vsiEgModeEn", "set", SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET, NULL},
+	{"counter", "set", SW_API_PT_VLAN_COUNTER_CLEANUP, NULL},
+	{"translationAdv", "set", SW_API_PT_VLAN_TRANS_ADV_ADD, NULL},
+#endif
+	#ifndef IN_PORTVLAN_MINI
+	{"tlsMode", "set",   SW_API_PT_TLS_SET, NULL},
+	{"priPropagation", "set",   SW_API_PT_PRI_PROPAGATION_SET, NULL},
+	#endif
+	{"defaultSVid", "set",   SW_API_PT_DEF_SVID_SET, NULL},
+	{"defaultCVid", "set",   SW_API_PT_DEF_CVID_SET, NULL},
+	#ifndef IN_PORTVLAN_MINI
+	{"vlanPropagation", "set",   SW_API_PT_VLAN_PROPAGATION_SET, NULL},
+	{"translation", "set",   SW_API_PT_VLAN_TRANS_ADD, NULL},
+	{"translation", "add",   SW_API_PT_VLAN_TRANS_ADD, NULL},
+	{"translation", "del",   SW_API_PT_VLAN_TRANS_DEL, NULL},
+	{"qinqMode", "set",   SW_API_QINQ_MODE_SET, NULL},
+	{"qinqRole", "set",   SW_API_PT_QINQ_ROLE_SET, NULL},
+	{"macvlanxlt", "set",   SW_API_PT_MAC_VLAN_XLT_SET, NULL},
+	{"netiso", "set",   SW_API_NETISOLATE_SET, NULL},
+	{"egbypass", "set",   SW_API_EG_FLTR_BYPASS_EN_SET, NULL},
+	{"ptvrfid", "set",   SW_API_PT_VRF_ID_SET, NULL},
+	#endif
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_FDB
+struct sub_cmd_des_t g_fdb_des[] =
+{
+#ifndef IN_FDB_MINI
+	{"entry", "set",   SW_API_FDB_ADD, NULL},
+	{"entry", "add",   SW_API_FDB_ADD, NULL},
+	{"entry", "del",   SW_API_FDB_DELMAC, NULL},
+	{"entry", "flush",   SW_API_FDB_DELALL, NULL},
+	{"entry", "transfer",   SW_API_FDB_TRANSFER, NULL},
+	{"portEntry", "flush",   SW_API_FDB_DELPORT, NULL},
+	{"firstEntry", "find",   SW_API_FDB_FIRST, NULL},
+	{"nextEntry", "find",   SW_API_FDB_NEXT, NULL},
+#endif
+	{"portLearn", "set",   SW_API_FDB_PT_LEARN_SET, NULL},
+#ifndef IN_FDB_MINI
+	{"ageCtrl", "set",   SW_API_FDB_AGE_CTRL_SET, NULL},
+	{"vlansmode", "set",   SW_API_FDB_VLAN_IVL_SVL_SET, NULL},
+	{"ageTime", "set",   SW_API_FDB_AGE_TIME_SET, NULL},
+	{"ptlearnlimit", "set",   SW_API_PT_FDB_LEARN_LIMIT_SET, NULL},
+	{"ptlearnexceedcmd", "set",   SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, NULL},
+	{"learnlimit", "set",   SW_API_FDB_LEARN_LIMIT_SET, NULL},
+	{"learnexceedcmd", "set",   SW_API_FDB_LEARN_EXCEED_CMD_SET, NULL},
+	{"resventry", "set",   SW_API_FDB_RESV_ADD, NULL},
+	{"resventry", "add",   SW_API_FDB_RESV_ADD, NULL},
+	{"resventry", "del",   SW_API_FDB_RESV_DEL, NULL},
+	{"ptLearnstatic", "set",   SW_API_FDB_PT_LEARN_STATIC_SET, NULL},
+	{"port", "add",   SW_API_FDB_PORT_ADD, NULL},
+	{"port", "del",   SW_API_FDB_PORT_DEL, NULL},
+	{"LearnCtrl", "set", SW_API_FDB_LEARN_CTRL_SET, NULL},
+	{"PtLearnCtrl", "set", SW_API_FDB_PT_NEWADDR_LEARN_SET, NULL},
+	{"PtStationMove", "set", SW_API_FDB_PT_STAMOVE_SET, NULL},
+	{"PtMacLimitCtrl", "set", SW_API_FDB_PT_MACLIMIT_CTRL_SET, NULL},
+        {"fidEntry", "flush", SW_API_FDB_DEL_BY_FID, NULL},
+#endif
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_ACL
+struct sub_cmd_des_t g_acl_des[] =
+{
+	{"list", "create",   SW_API_ACL_LIST_CREAT, NULL},
+	{"list", "destroy",   SW_API_ACL_LIST_DESTROY, NULL},
+	{"list", "bind",   SW_API_ACL_LIST_BIND, NULL},
+	{"list", "unbind",   SW_API_ACL_LIST_UNBIND, NULL},
+	{"rule", "add",   SW_API_ACL_RULE_ADD, NULL},
+	{"rule", "del",   SW_API_ACL_RULE_DELETE, NULL},
+	{"rule", "active",   SW_API_ACL_RULE_ACTIVE, NULL},
+	{"rule", "deactive",   SW_API_ACL_RULE_DEACTIVE, NULL},
+	{"srcfiltersts", "set",   SW_API_ACL_RULE_SRC_FILTER_STS_SET, NULL},
+	{"status", "set",   SW_API_ACL_STATUS_SET, NULL},
+	{"udfprofile", "set",   SW_API_ACL_PT_UDF_PROFILE_SET, NULL},
+	{"udf", "set", SW_API_ACL_UDF_SET, NULL},
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_QOS
+struct sub_cmd_des_t g_qos_des[] =
+{
+#ifndef IN_QOS_MINI
+#ifndef ISISC
+	{"schMode", "set", SW_API_QOS_SCH_MODE_SET, NULL},
+#endif
+	{"qTxBufSts", "set",  SW_API_QOS_QU_TX_BUF_ST_SET, NULL},
+#ifdef ISISC
+	{"qTxBufNr", "set",   SW_API_QOS_QU_TX_BUF_NR_SET, NULL},
+#else
+	{"qTxBufNr", "set",  SW_API_QOS_QU_TX_BUF_NR_SET, NULL},
+#endif
+	{"ptTxBufSts", "set",   SW_API_QOS_PT_TX_BUF_ST_SET, NULL},
+	{"ptRedEn", "set",   SW_API_QOS_PT_RED_EN_SET, NULL},
+#ifdef ISISC
+	{"ptTxBufNr", "set",   SW_API_QOS_PT_TX_BUF_NR_SET, NULL},
+#else
+	{"ptTxBufNr", "set", SW_API_QOS_PT_TX_BUF_NR_SET, NULL},
+#endif
+#ifdef ISISC
+	{"ptRxBufNr", "set",   SW_API_QOS_PT_RX_BUF_NR_SET, NULL},
+#else
+	{"ptRxBufNr", "set", SW_API_QOS_PT_RX_BUF_NR_SET, NULL},
+#endif
+#ifndef ISISC
+	{"up2q", "set", SW_API_COSMAP_UP_QU_SET, NULL},
+	{"dscp2q", "set", SW_API_COSMAP_DSCP_QU_SET, NULL},
+#endif
+#endif
+#ifdef ISISC
+	{"ptMode", "set",   SW_API_QOS_PT_MODE_SET, NULL},
+	{"ptModePri", "set",   SW_API_QOS_PT_MODE_PRI_SET, NULL},
+#else
+	{"ptMode", "set", SW_API_QOS_PT_MODE_SET, NULL},
+	{"ptModePri", "set", SW_API_QOS_PT_MODE_PRI_SET, NULL},
+#endif
+#ifndef IN_QOS_MINI
+#ifndef ISISC
+	{"ptDefaultUp", "set",   SW_API_QOS_PORT_DEF_UP_SET, NULL},
+#endif
+	{"ptschMode", "set",   SW_API_QOS_PORT_SCH_MODE_SET, NULL},
+	{"ptDefaultSpri", "set",   SW_API_QOS_PT_DEF_SPRI_SET, NULL},
+	{"ptDefaultCpri", "set",   SW_API_QOS_PT_DEF_CPRI_SET, NULL},
+	{"ptFSpriSts", "set",   SW_API_QOS_PT_FORCE_SPRI_ST_SET, NULL},
+	{"ptFCpriSts", "set",   SW_API_QOS_PT_FORCE_CPRI_ST_SET, NULL},
+	{"ptQuRemark", "set",   SW_API_QOS_QUEUE_REMARK_SET, NULL},
+	{"ptgroup", "set", SW_API_QOS_PORT_GROUP_SET, NULL},
+	{"ptpriprece", "set", SW_API_QOS_PORT_PRI_SET, NULL},
+	{"ptremark", "set", SW_API_QOS_PORT_REMARK_SET, NULL},
+	{"pcpmap", "set", SW_API_QOS_PCP_MAP_SET, NULL},
+	{"flowmap", "set", SW_API_QOS_FLOW_MAP_SET, NULL},
+	{"dscpmap", "set", SW_API_QOS_DSCP_MAP_SET, NULL},
+	{"qscheduler", "set", SW_API_QOS_QUEUE_SCHEDULER_SET, NULL},
+	{"ringqueue", "set", SW_API_QOS_RING_QUEUE_MAP_SET, NULL},
+	{"dequeue", "set", SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET, NULL},
+	{"portscheduler", "set", SW_API_QOS_PORT_SCHEDULER_CFG_RESET, NULL},
+#endif
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_IGMP
+struct sub_cmd_des_t g_igmp_des[] =
+{
+	{"mode", "set", SW_API_PT_IGMPS_MODE_SET, NULL},
+	{"cmd", "set", SW_API_IGMP_MLD_CMD_SET, NULL},
+	{"portJoin", "set", SW_API_IGMP_PT_JOIN_SET, NULL},
+	{"portLeave", "set", SW_API_IGMP_PT_LEAVE_SET, NULL},
+	{"rp", "set", SW_API_IGMP_RP_SET, NULL},
+	{"createStatus", "set", SW_API_IGMP_ENTRY_CREAT_SET, NULL},
+	{"static", "set", SW_API_IGMP_ENTRY_STATIC_SET, NULL},
+	{"leaky", "set", SW_API_IGMP_ENTRY_LEAKY_SET, NULL},
+	{"version3", "set", SW_API_IGMP_ENTRY_V3_SET, NULL},
+	{"queue", "set", SW_API_IGMP_ENTRY_QUEUE_SET, NULL},
+	{"ptlearnlimit", "set", SW_API_PT_IGMP_LEARN_LIMIT_SET, NULL},
+	{"ptlearnexceedcmd", "set", SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, NULL},
+	{"multi", "set", SW_API_IGMP_SG_ENTRY_SET, NULL},
+	{"multi", "clear", SW_API_IGMP_SG_ENTRY_CLEAR, NULL},
+	{"multi", "show", SW_API_IGMP_SG_ENTRY_SHOW, NULL},
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_LEAKY
+struct sub_cmd_des_t g_leaky_des[] =
+{
+	{"ucMode", "set", SW_API_UC_LEAKY_MODE_SET, NULL},
+	{"mcMode", "set", SW_API_MC_LEAKY_MODE_SET, NULL},
+	{"arpMode", "set", SW_API_ARP_LEAKY_MODE_SET, NULL},
+	{"ptUcMode", "set", SW_API_PT_UC_LEAKY_MODE_SET, NULL},
+	{"ptMcMode", "set", SW_API_PT_MC_LEAKY_MODE_SET, NULL},
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_MIRROR
+struct sub_cmd_des_t g_mirror_des[] =
+{
+	{"analyPt", "set", SW_API_MIRROR_ANALY_PT_SET, NULL},
+	{"ptIngress", "set", SW_API_MIRROR_IN_PT_SET, NULL},
+	{"ptEgress", "set", SW_API_MIRROR_EG_PT_SET, NULL},
+	{"analyCfg", "set", SW_API_MIRROR_ANALYSIS_CONFIG_SET, NULL},
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_RATE
+struct sub_cmd_des_t g_rate_des[] =
+{
+#ifndef ISISC
+	{"qEgress", "set", SW_API_RATE_QU_EGRL_SET, NULL},
+	{"ptEgress", "set", SW_API_RATE_PT_EGRL_SET, NULL},
+	{"ptIngress", "set", SW_API_RATE_PT_INRL_SET, NULL},
+	{"stormCtrl", "set", SW_API_STORM_CTRL_FRAME_SET, NULL},
+	{"stormCtrlRate", "set", SW_API_STORM_CTRL_RATE_SET, NULL},
+#endif
+	{"portpolicer", "set", SW_API_RATE_PORT_POLICER_SET, NULL},
+	{"portshaper", "set", SW_API_RATE_PORT_SHAPER_SET, NULL},
+	{"queueshaper", "set", SW_API_RATE_QUEUE_SHAPER_SET, NULL},
+	{"aclpolicer", "set", SW_API_RATE_ACL_POLICER_SET, NULL},
+	{"ptAddRateByte", "set", SW_API_RATE_PT_ADDRATEBYTE_SET, NULL},
+	{"ptgolflowen", "set", SW_API_RATE_PT_GOL_FLOW_EN_SET, NULL},
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_SEC
+#ifdef ISISC
+struct sub_cmd_des_t g_sec_des[] =
+{
+	{"mac", "set", SW_API_SEC_MAC_SET, NULL},
+	{"ip", "set", SW_API_SEC_IP_SET, NULL},
+	{"ip4", "set", SW_API_SEC_IP4_SET, NULL},
+	{"ip6", "set", SW_API_SEC_IP6_SET, NULL},
+	{"tcp", "set", SW_API_SEC_TCP_SET, NULL},
+	{"udp", "set", SW_API_SEC_UDP_SET, NULL},
+	{"icmp4", "set", SW_API_SEC_ICMP4_SET, NULL},
+	{"icmp6", "set", SW_API_SEC_ICMP6_SET, NULL},
+	{"l3parser", "set", SW_API_SEC_L3_PARSER_CTRL_SET, NULL},
+	{"l4parser", "set", SW_API_SEC_L4_PARSER_CTRL_SET, NULL},
+	{"expctrl", "set", SW_API_SEC_EXP_CTRL_SET, NULL},
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+#endif
+
+#ifdef IN_STP
+struct sub_cmd_des_t g_stp_des[] =
+{
+	{"portState", "set", SW_API_STP_PT_STATE_SET, NULL},
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_MIB
+struct sub_cmd_des_t g_mib_des[] =
+{
+	{"status", "set",    SW_API_MIB_STATUS_SET, NULL},
+            {"counters",  "flush",   SW_API_PT_MIB_FLUSH_COUNTERS, NULL},
+            {"cpuKeep", "set",    SW_API_MIB_CPU_KEEP_SET, NULL},
+            {NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_LED
+struct sub_cmd_des_t g_led_des[] =
+{
+	{"ctrlpattern", "set", SW_API_LED_PATTERN_SET, NULL},
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+
+#ifdef IN_COSMAP
+struct sub_cmd_des_t g_cosmap_des[] =
+{
+#ifndef IN_COSMAP_MINI
+	{"dscp2pri", "set",   SW_API_COSMAP_DSCP_TO_PRI_SET, NULL},
+	{"dscp2dp", "set",   SW_API_COSMAP_DSCP_TO_DP_SET, NULL},
+	{"up2pri", "set",   SW_API_COSMAP_UP_TO_PRI_SET, NULL},
+	{"up2dp", "set",   SW_API_COSMAP_UP_TO_DP_SET, NULL},
+	{"dscp2ehpri", "set",   SW_API_COSMAP_DSCP_TO_EHPRI_SET, NULL},
+	{"dscp2ehdp", "set",   SW_API_COSMAP_DSCP_TO_EHDP_SET, NULL},
+
+	{"up2ehpri", "set",   SW_API_COSMAP_UP_TO_EHPRI_SET, NULL},
+	{"up2ehdp", "set",   SW_API_COSMAP_UP_TO_EHDP_SET, NULL},
+#endif
+	{"pri2q", "set",   SW_API_COSMAP_PRI_TO_QU_SET, NULL},
+	{"pri2ehq", "set",   SW_API_COSMAP_PRI_TO_EHQU_SET, NULL},
+#ifndef IN_COSMAP_MINI
+	{"egRemark", "set",   SW_API_COSMAP_EG_REMARK_SET, NULL},
+#endif
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_MISC
+struct sub_cmd_des_t g_misc_des[] =
+{
+#ifndef ISISC
+	{"arp", "set",   SW_API_ARP_STATUS_SET, NULL},
+#endif
+	{"frameMaxSize", "set",   SW_API_FRAME_MAX_SIZE_SET, NULL},
+#ifndef ISISC
+	{"ptUnkSaCmd", "set", SW_API_PT_UNK_SA_CMD_SET, NULL},
+#endif
+	{"ptUnkUcFilter", "set",   SW_API_PT_UNK_UC_FILTER_SET, NULL},
+	{"ptUnkMcFilter", "set",   SW_API_PT_UNK_MC_FILTER_SET, NULL},
+	{"ptBcFilter", "set",   SW_API_PT_BC_FILTER_SET, NULL},
+	{"cpuPort", "set",   SW_API_CPU_PORT_STATUS_SET, NULL},
+#ifndef ISISC
+	{"bctoCpu", "set", SW_API_BC_TO_CPU_PORT_SET, NULL},
+#endif
+#ifndef IN_MISC_MINI
+	{"ptDhcp", "set",   SW_API_PT_DHCP_SET, NULL},
+#ifdef ISISC
+	{"arpcmd", "set",   SW_API_ARP_CMD_SET, NULL},
+#else
+	{"arpcmd", "set", SW_API_ARP_CMD_SET, NULL},
+#endif
+#endif
+	{"eapolcmd", "set",   SW_API_EAPOL_CMD_SET, NULL},
+	{"eapolstatus", "set",   SW_API_EAPOL_STATUS_SET, NULL},
+#ifndef IN_MISC_MINI
+	{"rip", "set",   SW_API_RIPV1_STATUS_SET, NULL},
+	{"ptarpreq", "set",   SW_API_PT_ARP_REQ_STATUS_SET, NULL},
+	{"ptarpack", "set",   SW_API_PT_ARP_ACK_STATUS_SET, NULL},
+	{"intrmask", "set",   SW_API_INTR_MASK_SET, NULL},
+	{"intrstatus", "clear",   SW_API_INTR_STATUS_CLEAR, NULL},
+	{"intrportlinkmask", "set",   SW_API_INTR_PORT_LINK_MASK_SET, NULL},
+	{"intrmaskmaclinkchg", "set",   SW_API_INTR_MASK_MAC_LINKCHG_SET, NULL},
+	{"intrstatusmaclinkchg", "clear",   SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, NULL},
+	{"cpuVid", "set",   SW_API_CPU_VID_EN_SET, NULL},
+	{"glomacaddr", "set",   SW_API_GLOBAL_MACADDR_SET, NULL},
+	{"lldp", "set",   SW_API_LLDP_STATUS_SET, NULL},
+	{"framecrc", "set",   SW_API_FRAME_CRC_RESERVE_SET, NULL},
+#endif
+#ifdef IN_PPPOE
+	{"pppoesession", "add", SW_API_PPPOE_SESSION_ADD, NULL},
+	{"pppoesession", "del", SW_API_PPPOE_SESSION_DEL, NULL},
+	{"extendpppoe", "set",   SW_API_PPPOE_SESSION_TABLE_ADD, NULL},
+	{"extendpppoe", "add",   SW_API_PPPOE_SESSION_TABLE_ADD, NULL},
+	{"extendpppoe", "del",   SW_API_PPPOE_SESSION_TABLE_DEL, NULL},
+	{"pppoeid", "set",   SW_API_PPPOE_SESSION_ID_SET, NULL},
+	{"PppoeCmd", "set",   SW_API_PPPOE_CMD_SET, NULL},
+	{"PppoeCmd", "set",   SW_API_PPPOE_CMD_SET, NULL},
+	{"rtdPppoe", "set",   SW_API_RTD_PPPOE_EN_SET, NULL},
+	{"Pppoe", "set",   SW_API_PPPOE_STATUS_SET, NULL},
+	{"pppoeen", "set", SW_API_PPPOE_EN_SET, NULL},
+#endif
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_IP
+struct sub_cmd_des_t g_ip_des[] =
+{
+#ifndef IN_IP_MINI
+	{"hostentry", "set", SW_API_IP_HOST_ADD, NULL},
+	{"hostentry", "add", SW_API_IP_HOST_ADD, NULL},
+	{"hostentry", "del", SW_API_IP_HOST_DEL, NULL},
+	{"hostentry", "next", SW_API_IP_HOST_NEXT, NULL},
+	{"hostentry", "bindcnt", SW_API_IP_HOST_COUNTER_BIND, NULL},
+	{"hostentry", "bindpppoe", SW_API_IP_HOST_PPPOE_BIND, NULL},
+	{"ptarplearn", "set", SW_API_IP_PT_ARP_LEARN_SET, NULL},
+	{"arplearn",   "set", SW_API_IP_ARP_LEARN_SET, NULL},
+	{"ptipsrcguard",   "set", SW_API_IP_SOURCE_GUARD_SET, NULL},
+	{"ptarpsrcguard",  "set", SW_API_IP_ARP_GUARD_SET, NULL},
+	{"routestatus", "set", SW_API_IP_ROUTE_STATUS_SET, NULL},
+	{"intfentry", "set", SW_API_IP_INTF_ENTRY_ADD, NULL},
+	{"intfentry", "add", SW_API_IP_INTF_ENTRY_ADD, NULL},
+	{"intfentry", "del", SW_API_IP_INTF_ENTRY_DEL, NULL},
+	{"ipunksrc", "set", SW_API_IP_UNK_SOURCE_CMD_SET, NULL},
+	{"arpunksrc", "set", SW_API_ARP_UNK_SOURCE_CMD_SET, NULL},
+	{"ipagetime", "set", SW_API_IP_AGE_TIME_SET, NULL},
+	{"wcmphashmode", "set", SW_API_WCMP_HASH_MODE_SET, NULL},
+	{"wcmpentry", "set", SW_API_IP_WCMP_ENTRY_SET, NULL},
+	{"vrfbaseaddr", "set", SW_API_IP_VRF_BASE_ADDR_SET, NULL},
+	{"vrfbasemask", "set", SW_API_IP_VRF_BASE_MASK_SET, NULL},
+	{"defaultroute", "set", SW_API_IP_DEFAULT_ROUTE_SET, NULL},
+	{"hostroute", "set", SW_API_IP_HOST_ROUTE_SET, NULL},
+	{"rfsip4", "set", SW_API_IP_RFS_IP4_SET, NULL},
+	{"rfsip6", "set", SW_API_IP_RFS_IP6_SET, NULL},
+	{"defaultflowcmd", "set", SW_API_IP_DEFAULT_FLOW_CMD_SET, NULL},
+	{"defaultrtflowcmd", "set", SW_API_IP_DEFAULT_RT_FLOW_CMD_SET, NULL},
+	{"vsiarpsg", "set",  SW_API_IP_VIS_ARP_SG_CFG_SET, NULL},
+	{"networkroute", "set",  SW_API_IP_NETWORK_ROUTE_ADD, NULL},
+	{"networkroute", "add",  SW_API_IP_NETWORK_ROUTE_ADD, NULL},
+	{"intf", "set",  SW_API_IP_INTF_SET, NULL},
+	{"vsiintf", "set",  SW_API_IP_VSI_INTF_SET, NULL},
+	{"portintf", "set",  SW_API_IP_PORT_INTF_SET, NULL},
+	{"nexthop", "set",  SW_API_IP_NEXTHOP_SET, NULL},
+	{"portsg", "set",  SW_API_IP_PORT_SG_SET, NULL},
+	{"vsisg", "set",  SW_API_IP_VSI_SG_SET, NULL},
+	{"pubip", "set",  SW_API_IP_PUB_IP_SET, NULL},
+	{"portmac", "set",  SW_API_IP_PORT_MAC_SET, NULL},
+	{"routemiss", "set",  SW_API_IP_ROUTE_MISS_SET, NULL},
+	{"portarpsg", "set",  SW_API_IP_PORT_ARP_SG_SET, NULL},
+	{"mcmode", "set",  SW_API_IP_VSI_MC_MODE_SET, NULL},
+	{"globalctrl", "set",  SW_API_GLOBAL_CTRL_SET, NULL},
+#endif
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_FLOW
+struct sub_cmd_des_t g_flow_des[] =
+{
+	{"status", "set", SW_API_FLOW_STATUS_SET, NULL},
+	{"agetime", "set", SW_API_FLOW_AGE_TIMER_SET, NULL},
+	{"mgmt", "set", SW_API_FLOW_CTRL_SET, NULL},
+	{"entry", "add", SW_API_FLOW_ENTRY_ADD, NULL},
+	{"entry", "set", SW_API_FLOW_ENTRY_ADD, NULL},
+	{"entry", "del", SW_API_FLOW_ENTRY_DEL, NULL},
+	{"host", "set", SW_API_FLOW_HOST_ADD, NULL},
+	{"host", "add", SW_API_FLOW_HOST_ADD, NULL},
+	{"host", "del", SW_API_FLOW_HOST_DEL, NULL},
+	{"global", "set", SW_API_FLOW_GLOBAL_CFG_SET, NULL},
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_NAT
+struct sub_cmd_des_t g_nat_des[] =
+{
+	{"natentry", "set", SW_API_NAT_ADD, NULL},
+	{"natentry", "add", SW_API_NAT_ADD, NULL},
+	{"natentry", "del", SW_API_NAT_DEL, NULL},
+	{"natentry", "next", SW_API_NAT_NEXT, NULL},
+	{"natentry", "bindcnt", SW_API_NAT_COUNTER_BIND, NULL},
+	{"naptentry", "set", SW_API_NAPT_ADD, NULL},
+	{"naptentry", "add", SW_API_NAPT_ADD, NULL},
+	{"naptentry", "del", SW_API_NAPT_DEL, NULL},
+	{"naptentry", "next", SW_API_NAPT_NEXT, NULL},
+	{"naptentry", "bindcnt", SW_API_NAPT_COUNTER_BIND, NULL},
+	{"natstatus", "set", SW_API_NAT_STATUS_SET, NULL},
+	{"naptstatus", "set", SW_API_NAPT_STATUS_SET, NULL},
+	{"nathash", "set", SW_API_NAT_HASH_MODE_SET, NULL},
+	{"naptmode", "set", SW_API_NAPT_MODE_SET, NULL},
+	{"prvbaseaddr", "set", SW_API_PRV_BASE_ADDR_SET, NULL},
+	{"prvaddrmode", "set", SW_API_PRV_ADDR_MODE_SET, NULL},
+	{"pubaddr", "set", SW_API_PUB_ADDR_ENTRY_ADD, NULL},
+	{"pubaddr", "add", SW_API_PUB_ADDR_ENTRY_ADD, NULL},
+	{"pubaddr", "del", SW_API_PUB_ADDR_ENTRY_DEL, NULL},
+	{"natunksess", "set", SW_API_NAT_UNK_SESSION_CMD_SET, NULL},
+	{"prvbasemask", "set", SW_API_PRV_BASE_MASK_SET, NULL},
+	{"global", "set", SW_API_NAT_GLOBAL_SET, NULL},
+	{"flowentry", "set", SW_API_FLOW_ADD, NULL},
+	{"flowentry", "add", SW_API_FLOW_ADD, NULL},
+	{"flowentry", "del", SW_API_FLOW_DEL, NULL},
+	{"flowentry", "next", SW_API_FLOW_NEXT, NULL},
+	{"flowcookie", "set", SW_API_FLOW_COOKIE_SET, NULL},
+	{"flowrfs", "set", SW_API_FLOW_RFS_SET, NULL},
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_TRUNK
+struct sub_cmd_des_t g_trunk_des[] =
+{
+	{"group", "set", SW_API_TRUNK_GROUP_SET, NULL},
+	{"hashmode", "set", SW_API_TRUNK_HASH_SET, NULL},
+	{"mansa", "set", SW_API_TRUNK_MAN_SA_SET, NULL},
+	{"failover", "set", SW_API_TRUNK_FAILOVER_EN_SET, NULL},
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_INTERFACECONTROL
+struct sub_cmd_des_t g_interfacecontrol_des[] =
+{
+	{"macmode", "set",   SW_API_MAC_MODE_SET, NULL},
+	{"pt3azstatus", "set",   SW_API_PORT_3AZ_STATUS_SET, NULL},
+	{"phymode", "set",   SW_API_PHY_MODE_SET, NULL},
+	{"fx100ctrl", "set",   SW_API_FX100_CTRL_SET, NULL},
+	{"mac06exch", "set",   SW_API_MAC06_EXCH_SET, NULL},
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+
+#ifdef IN_VSI
+struct sub_cmd_des_t g_vsi_des[] =
+{
+	{"vsi", "alloc", SW_API_VSI_ALLOC, NULL},
+	{"vsi", "free", SW_API_VSI_FREE, NULL},
+	{"portbasedvsi", "set", SW_API_PORT_VSI_SET, NULL},
+	{"vlanbasedvsi", "set", SW_API_PORT_VLAN_VSI_SET, NULL},
+	{"learnctrl", "set", SW_API_VSI_NEWADDR_LRN_SET, NULL},
+	{"stationmove", "set", SW_API_VSI_STAMOVE_SET, NULL},
+	{"member", "set", SW_API_VSI_MEMBER_SET, NULL},
+    {"counter", "cleanup", SW_API_VSI_COUNTER_CLEANUP, NULL},
+	{NULL, NULL, 0, NULL}/*end of desc*/
+};
+#endif
+
+#ifdef IN_POLICER
+struct sub_cmd_des_t g_policer_des[] =
+{
+	{"timeslot", "set",   SW_API_POLICER_TIMESLOT_SET, NULL},
+	{"fcscompensation", "set",   SW_API_POLICER_COMPENSATION_SET, NULL},
+	{"portentry", "set",   SW_API_POLICER_PORT_ENTRY_SET, NULL},
+	{"aclentry", "set",   SW_API_POLICER_ACL_ENTRY_SET, NULL},
+	{"bypass", "set",  SW_API_POLICER_BYPASS_EN_SET, NULL},
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+#ifdef IN_SHAPER
+struct sub_cmd_des_t g_shaper_des[] =
+{
+	{"porttimeslot", "set",   SW_API_PORT_SHAPER_TIMESLOT_SET, NULL},
+	{"flowtimeslot", "set",   SW_API_FLOW_SHAPER_TIMESLOT_SET, NULL},
+	{"queuetimeslot", "set",	 SW_API_QUEUE_SHAPER_TIMESLOT_SET, NULL},
+	{"porttoken", "set",   SW_API_PORT_SHAPER_TOKEN_NUMBER_SET, NULL},
+	{"flowtoken", "set",   SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET, NULL},
+	{"queuetoken", "set",   SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET, NULL},
+	{"portshaper", "set",   SW_API_PORT_SHAPER_SET, NULL},
+	{"flowshaper", "set",   SW_API_FLOW_SHAPER_SET, NULL},
+	{"queueshaper", "set",   SW_API_QUEUE_SHAPER_SET, NULL},
+	{"ipgcompensation", "set",   SW_API_SHAPER_IPG_PRE_SET, NULL},
+	{NULL, NULL,  0, NULL},/*end of desc*/
+};
+#endif
+    /*QM*/
+#ifdef IN_QM
+struct sub_cmd_des_t g_qm_des[] =
+{
+
+    {"ucastqbase", "set", SW_API_UCAST_QUEUE_BASE_PROFILE_SET, NULL},
+    {"ucastpriclass", "set", SW_API_UCAST_PRIORITY_CLASS_SET, NULL},
+    {"mcastpriclass", "set", SW_API_MCAST_PRIORITY_CLASS_SET, NULL},
+    {"queue", "flush", SW_API_QUEUE_FLUSH, NULL},
+    {"queue", "set", SW_API_QUEUE_FLUSH, NULL},
+    {"ucasthash", "set", SW_API_UCAST_HASH_MAP_SET, NULL},
+    {"ucastdflthash", "set", SW_API_UCAST_DFLT_HASH_MAP_SET, NULL},
+    {"mcastcpucode", "set", SW_API_MCAST_CPUCODE_CLASS_SET, NULL},
+    {"acctrl", "set", SW_API_AC_CTRL_SET, NULL},
+    {"acprebuffer", "set", SW_API_AC_PRE_BUFFER_SET, NULL},
+    {"acqgroup", "set", SW_API_QUEUE_GROUP_SET, NULL},
+    {"acstaticthresh", "set", SW_API_STATIC_THRESH_SET, NULL},
+    {"acdynamicthresh", "set", SW_API_DYNAMIC_THRESH_SET, NULL},
+    {"acgroupbuff", "set", SW_API_GOURP_BUFFER_SET, NULL},
+    {"cntctrl", "set", SW_API_QUEUE_CNT_CTRL_SET, NULL},
+    {"cnt", "cleanup", SW_API_QUEUE_CNT_CLEANUP, NULL},
+    {"cnt", "set", SW_API_QUEUE_CNT_CLEANUP, NULL},
+    {"enqueue", "set", SW_API_QM_ENQUEUE_CTRL_SET, NULL},
+    {"srcprofile", "set", SW_API_QM_SOURCE_PROFILE_SET, NULL},
+    {NULL, NULL, 0, NULL},/*end of desc*/
+
+};
+#endif
+
+/*BM*/
+#ifdef IN_BM
+struct sub_cmd_des_t g_bm_des[] =
+{
+
+    {"ctrl", "set", SW_API_BM_CTRL_SET, NULL},
+    {"portgroupmap", "set", SW_API_BM_PORTGROUP_MAP_SET, NULL},
+    {"groupbuff", "set", SW_API_BM_GROUP_BUFFER_SET, NULL},
+    {"portrsvbuff", "set", SW_API_BM_PORT_RSVBUFFER_SET, NULL},
+    {"portsthresh", "set", SW_API_BM_STATIC_THRESH_SET, NULL},
+    {"portdthresh", "set", SW_API_BM_DYNAMIC_THRESH_SET, NULL},
+    {NULL, NULL, 0, NULL},/*end of desc*/
+
+};
+#endif
+
+/*Servcode*/
+#ifdef IN_SERVCODE
+struct sub_cmd_des_t g_servcode_des[] =
+{
+    {"config", "set", SW_API_SERVCODE_CONFIG_SET, NULL},
+    {"loopcheck", "set", SW_API_SERVCODE_LOOPCHECK_EN, NULL},
+    {NULL, NULL, 0, NULL},/*end of desc*/
+};
+#endif
+
+/*rss hash*/
+#ifdef IN_RSS_HASH
+struct sub_cmd_des_t g_rss_hash_des[] =
+{
+    {"config", "set", SW_API_RSS_HASH_CONFIG_SET, NULL},
+    {NULL, NULL, 0, NULL},/*end of desc*/
+};
+#endif
+
+/*Ctrlpkt*/
+#ifdef IN_CTRLPKT
+struct sub_cmd_des_t g_ctrlpkt_des[] =
+{
+    {"ethernetType", "set", SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET, NULL},
+    {"rfdb", "set", SW_API_MGMTCTRL_RFDB_PROFILE_SET, NULL},
+    {"appProfile", "set", SW_API_MGMTCTRL_CTRLPKT_PROFILE_ADD, NULL},
+    {NULL, NULL, 0, NULL},/*end of desc*/
+};
+#endif
+
+struct sub_cmd_des_t g_debug_des[] =
+{
+	{"module_func", "set", SW_API_MODULE_FUNC_CTRL_SET, NULL},
+	{NULL, NULL, 0, NULL},/*end of desc*/
+};
+
+struct cmd_des_t gcmd_des[] =
+{
+    /*port ctrl*/
+#ifdef IN_PORTCONTROL
+    {
+        "port", g_port_des,
+    },
+#endif
+
+    /*vlan*/
+#ifdef IN_VLAN
+    {
+        "vlan", g_vlan_des,
+    },
+#endif
+
+    /*portvlan*/
+#ifdef IN_PORTVLAN
+    {
+        "portVlan", g_portvlan_des,
+    },
+#endif
+
+    /*fdb*/
+#ifdef IN_FDB
+    {
+        "fdb", g_fdb_des,
+    },
+#endif
+
+    /*acl*/
+#ifdef IN_ACL
+    {
+        "acl", g_acl_des,
+    },
+#endif
+
+    /*qos*/
+#ifdef IN_QOS
+    {
+        "qos", g_qos_des,
+    },
+#endif
+
+    /*igmp*/
+#ifdef IN_IGMP
+    {
+        "igmp", g_igmp_des,
+    },
+#endif
+
+    /*leaky*/
+#ifdef IN_LEAKY
+    {
+        "leaky", g_leaky_des,
+    },
+#endif
+
+    /*mirror*/
+#ifdef IN_MIRROR
+    {
+        "mirror", g_mirror_des,
+    },
+#endif
+
+    /*rate*/
+#ifdef IN_RATE
+    {
+        "rate", g_rate_des,
+    },
+#endif
+
+#ifdef IN_SEC
+#ifdef ISISC
+    {
+        "sec", g_sec_des,
+    },
+#endif
+#endif
+
+    /*stp*/
+#ifdef IN_STP
+    {
+        "stp", g_stp_des,
+    },
+#endif
+
+    /*mib*/
+#ifdef IN_MIB
+    {
+        "mib", g_mib_des,
+    },
+#endif
+
+    /* led */
+#ifdef IN_LED
+    {
+        "led", g_led_des,
+    },
+#endif
+
+    /* cosmap */
+#ifdef IN_COSMAP
+    {
+        "cosmap", g_cosmap_des,
+    },
+#endif
+
+    /*misc*/
+#ifdef IN_MISC
+    {
+        "misc", g_misc_des,
+    },
+#endif
+
+    /* IP */
+#ifdef IN_IP
+    {
+        "ip", g_ip_des,
+    },
+#endif
+
+    /* FLOW */
+#ifdef IN_FLOW
+    {
+        "flow", g_flow_des,
+    },
+#endif
+
+    /* NAT */
+#ifdef IN_NAT
+    {
+        "nat", g_nat_des,
+    },
+#endif
+
+    /*Trunk*/
+#ifdef IN_TRUNK
+    {
+        "trunk", g_trunk_des,
+    },
+#endif
+
+    /*Interface Control*/
+#ifdef IN_INTERFACECONTROL
+    {
+        "interface", g_interfacecontrol_des,
+    },
+#endif
+
+#ifdef IN_VSI
+    {
+        "vsi", g_vsi_des,
+    },
+#endif
+
+	/*policer*/
+#ifdef IN_POLICER
+		{
+			"policer", g_policer_des,
+		},
+#endif
+
+     /*shaper*/
+#ifdef IN_SHAPER
+    {
+        "shaper", g_shaper_des,
+    },
+#endif
+        /*qm Control*/
+#ifdef IN_QM
+    {
+        "qm", g_qm_des,
+    },
+#endif
+
+	/*bm Control*/
+#ifdef IN_BM
+    {
+        "bm", g_bm_des,
+    },
+#endif
+
+#ifdef IN_SERVCODE
+    {
+        "servcode", g_servcode_des,
+    },
+#endif
+
+#ifdef IN_RSS_HASH
+    {
+        "rsshash", g_rss_hash_des,
+    },
+#endif
+
+#ifdef IN_CTRLPKT
+    {
+        "ctrlpkt", g_ctrlpkt_des,
+    },
+#endif
+    {
+	"debug", g_debug_des,
+    },
+
+    {NULL, NULL} /*end of desc*/
+};
+
+
+#endif
+
diff --git a/qca-ssdk/src/shell_lib/shell_io.c b/qca-ssdk/src/shell_lib/shell_io.c
new file mode 100644
index 0000000..788d727
--- /dev/null
+++ b/qca-ssdk/src/shell_lib/shell_io.c
@@ -0,0 +1,14042 @@
+/*
+ * Copyright (c) 2013, 2015-2017, 2019, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//#include <stdio.h>
+#include "shell_io.h"
+#include "shell.h"
+
+#define SW_RTN_ON_NULL_PARAM(rtn) \
+    do { if ((rtn) == NULL) return SW_BAD_PARAM; } while(0);
+
+#define DEFAULT_FLAG "default"
+static char **full_cmdstrp;
+static int talk_mode = 1;
+
+#define cmd_data_check_element(info, defval, usage, chk_func, param) \
+{\
+    sw_error_t ret;\
+    do {\
+        cmd = get_sub_cmd(info, defval);\
+        SW_RTN_ON_NULL_PARAM(cmd);\
+        \
+        if (!strncasecmp(cmd, "quit", 4)) {\
+            return SW_BAD_VALUE;\
+        } else if (!strncasecmp(cmd, "help", 4)) {\
+            ret = SW_BAD_VALUE;\
+        } else {\
+            ret = chk_func param; \
+        }\
+    } while (talk_mode && (SW_OK != ret));\
+}
+
+int
+get_talk_mode(void)
+{
+    return talk_mode ;
+}
+
+void
+set_talk_mode(int mode)
+{
+    talk_mode = mode;
+}
+
+char ** full_cmdstrp_bak;
+
+void
+set_full_cmdstrp(char **cmdstrp)
+{
+    full_cmdstrp = cmdstrp;
+    full_cmdstrp_bak = cmdstrp;
+}
+
+int
+get_jump(void)
+{
+    return (full_cmdstrp-full_cmdstrp_bak);
+}
+
+static char *
+get_cmd_buf(char *tag, char *defval)
+{
+    if(!full_cmdstrp || !(*full_cmdstrp))
+    {
+        return NULL;
+    }
+
+    if (!strcasecmp(*(full_cmdstrp), DEFAULT_FLAG))
+    {
+        full_cmdstrp++;
+        return defval;
+    }
+    else
+    {
+        return *(full_cmdstrp++);
+    }
+}
+
+static char *
+get_sub_cmd(char *tag, char *defval)
+{
+    return get_cmd_buf(tag, defval);
+}
+
+
+static inline  a_bool_t
+is_hex(char c)
+{
+    if ((c >= '0' && c <= '9') || (c >= 'a' && c <= 'f')
+            || (c >= 'A' && c <= 'F'))
+        return A_TRUE;
+
+    return A_FALSE;
+}
+
+static inline a_bool_t
+is_dec(char c)
+{
+    if ((c >= '0') && (c <= '9'))
+        return A_TRUE;
+
+    return A_FALSE;
+}
+
+static sw_data_type_t sw_data_type[] =
+{
+    SW_TYPE_DEF(SW_UINT8, (param_check_t)cmd_data_check_uint8, NULL),
+    SW_TYPE_DEF(SW_INT8, NULL, NULL),
+    SW_TYPE_DEF(SW_UINT16, (param_check_t)cmd_data_check_uint16, NULL),
+    SW_TYPE_DEF(SW_INT16, NULL, NULL),
+    SW_TYPE_DEF(SW_UINT32, cmd_data_check_uint32, NULL),
+    SW_TYPE_DEF(SW_INT32, NULL, NULL),
+    SW_TYPE_DEF(SW_UINT64, NULL, NULL),
+    SW_TYPE_DEF(SW_INT64, NULL, NULL),
+#ifdef IN_PORTCONTROL
+    SW_TYPE_DEF(SW_DUPLEX, cmd_data_check_duplex, NULL),
+    SW_TYPE_DEF(SW_SPEED, cmd_data_check_speed, NULL),
+    SW_TYPE_DEF(SW_CAP, cmd_data_check_capable, NULL),
+#ifndef IN_PORTCONTROL_MINI
+    SW_TYPE_DEF(SW_PORT_EEE_CONFIG, (param_check_t)cmd_data_check_port_eee_config, NULL),
+    SW_TYPE_DEF(SW_PORT_LOOPBACK_CONFIG, (param_check_t)cmd_data_check_switch_port_loopback_config, NULL),
+#endif
+#endif
+#ifdef IN_PORTVLAN
+    SW_TYPE_DEF(SW_1QMODE, cmd_data_check_1qmode, NULL),
+    SW_TYPE_DEF(SW_EGMODE, cmd_data_check_egmode, NULL),
+#endif
+#ifdef IN_MIB
+    SW_TYPE_DEF(SW_MIB, NULL, NULL),
+    SW_TYPE_DEF(SW_MIB_CNTR, NULL, NULL),
+    SW_TYPE_DEF(SW_XGMIB, NULL, NULL),
+#endif
+#ifdef IN_VLAN
+    SW_TYPE_DEF(SW_VLAN, (param_check_t)cmd_data_check_vlan, NULL),
+#endif
+    SW_TYPE_DEF(SW_PBMP, cmd_data_check_pbmp, NULL),
+    SW_TYPE_DEF(SW_ENABLE, cmd_data_check_enable, NULL),
+    SW_TYPE_DEF(SW_MACADDR, (param_check_t)cmd_data_check_macaddr, NULL),
+#ifdef IN_FDB
+    SW_TYPE_DEF(SW_FDBENTRY, (param_check_t)cmd_data_check_fdbentry, NULL),
+#ifndef IN_FDB_MINI
+    SW_TYPE_DEF(SW_MACLIMIT_CTRL, (param_check_t)cmd_data_check_maclimit_ctrl, NULL),
+#endif
+#endif
+#ifdef IN_QOS
+#ifndef IN_QOS_MINI
+    SW_TYPE_DEF(SW_SCH, cmd_data_check_qos_sch, NULL),
+    SW_TYPE_DEF(SW_QOS, cmd_data_check_qos_pt, NULL),
+#endif
+#ifndef IN_QOS_MINI
+    SW_TYPE_DEF(SW_PORTGROUP, (param_check_t)cmd_data_check_port_group, NULL),
+    SW_TYPE_DEF(SW_PORTPRI, (param_check_t)cmd_data_check_port_pri, NULL),
+    SW_TYPE_DEF(SW_PORTREMARK, (param_check_t)cmd_data_check_port_remark, NULL),
+    SW_TYPE_DEF(SW_COSMAP, (param_check_t)cmd_data_check_cosmap, NULL),
+    SW_TYPE_DEF(SW_SCHEDULER, (param_check_t)cmd_data_check_queue_scheduler, NULL),
+    SW_TYPE_DEF(SW_QUEUEBMP, (param_check_t)cmd_data_check_ring_queue, NULL),
+#endif
+#endif
+#ifdef IN_RATE
+	SW_TYPE_DEF(SW_STORM, cmd_data_check_storm, NULL),
+#endif
+#ifdef IN_STP
+    SW_TYPE_DEF(SW_STP, cmd_data_check_stp_state, NULL),
+#endif
+#ifdef IN_LEAKY
+    SW_TYPE_DEF(SW_LEAKY, cmd_data_check_leaky, NULL),
+#endif
+    SW_TYPE_DEF(SW_MACCMD, cmd_data_check_maccmd, NULL),
+#ifdef IN_IP
+#ifndef IN_IP_MINI
+    SW_TYPE_DEF(SW_FLOWCMD, cmd_data_check_flowcmd, NULL),
+    SW_TYPE_DEF(SW_FLOWTYPE, cmd_data_check_flowtype, NULL),
+#endif
+#endif
+    SW_TYPE_DEF(SW_UINT_A, cmd_data_check_uinta, NULL),
+#ifdef IN_ACL
+    SW_TYPE_DEF(SW_ACLRULE, NULL, NULL),
+    SW_TYPE_DEF(SW_ACL_UDF_PKT_TYPE, cmd_data_check_udf_pkt_type, NULL),
+    SW_TYPE_DEF(SW_ACL_UDF_TYPE, cmd_data_check_udf_type, NULL),
+#endif
+#ifdef IN_LED
+    SW_TYPE_DEF(SW_LEDPATTERN, (param_check_t)cmd_data_check_ledpattern, NULL),
+#endif
+#ifdef IN_PORTVLAN
+    SW_TYPE_DEF(SW_INVLAN, cmd_data_check_invlan_mode, NULL),
+#ifdef HPPE
+    SW_TYPE_DEF(SW_GLOBAL_QINQMODE, (param_check_t)cmd_data_check_global_qinqmode, NULL),
+    SW_TYPE_DEF(SW_PT_QINQMODE, (param_check_t)cmd_data_check_port_qinqmode, NULL),
+    SW_TYPE_DEF(SW_TPID, (param_check_t)cmd_data_check_tpid, NULL),
+    SW_TYPE_DEF(SW_INGRESS_FILTER, (param_check_t)cmd_data_check_ingress_filter, NULL),
+    SW_TYPE_DEF(SW_PT_VLAN_DIRECTION, cmd_data_check_port_vlan_direction, NULL),
+    SW_TYPE_DEF(SW_PT_DEF_VID_EN, (param_check_t)cmd_data_check_port_default_vid_en, NULL),
+    SW_TYPE_DEF(SW_PT_VLAN_TAG, (param_check_t)cmd_data_check_port_vlan_tag, NULL),
+    SW_TYPE_DEF(SW_TAG_PROPAGATION, (param_check_t)cmd_data_check_tag_propagation, NULL),
+    SW_TYPE_DEF(SW_EGRESS_MODE, (param_check_t)cmd_data_check_egress_mode, NULL),
+    SW_TYPE_DEF(SW_PT_VLAN_TRANS_ADV_RULE,
+		    (param_check_t)cmd_data_check_port_vlan_translation_adv_rule, NULL),
+    SW_TYPE_DEF(SW_PT_VLAN_TRANS_ADV_ACTION,
+		    (param_check_t)cmd_data_check_port_vlan_translation_adv_action, NULL),
+#endif
+#ifndef IN_PORTVLAN_MINI
+    SW_TYPE_DEF(SW_VLANPROPAGATION, cmd_data_check_vlan_propagation, NULL),
+    SW_TYPE_DEF(SW_VLANTRANSLATION, (param_check_t)cmd_data_check_vlan_translation, NULL),
+    SW_TYPE_DEF(SW_QINQMODE, cmd_data_check_qinq_mode, NULL),
+    SW_TYPE_DEF(SW_QINQROLE, cmd_data_check_qinq_role, NULL),
+#endif
+#endif
+    SW_TYPE_DEF(SW_CABLESTATUS, NULL, NULL),
+    SW_TYPE_DEF(SW_CABLELEN, NULL, NULL),
+    SW_TYPE_DEF(SW_SSDK_CFG, NULL, NULL),
+    SW_TYPE_DEF(SW_MODULE, (param_check_t)cmd_data_check_module, NULL),
+    SW_TYPE_DEF(SW_FUNC_CTRL, (param_check_t)cmd_data_check_func_ctrl, NULL),
+#ifdef IN_PORTCONTROL
+    SW_TYPE_DEF(SW_HDRMODE, cmd_data_check_hdrmode, NULL),
+#endif
+#ifdef IN_FDB
+    SW_TYPE_DEF(SW_FDBOPRATION, (param_check_t)cmd_data_check_fdboperation, NULL),
+#endif
+#ifdef IN_PPPOE
+    SW_TYPE_DEF(SW_PPPOE, (param_check_t)cmd_data_check_pppoe, NULL),
+    SW_TYPE_DEF(SW_PPPOE_LESS, (param_check_t)cmd_data_check_pppoe_less, NULL),
+#endif
+#if defined(IN_IP) || defined(IN_NAT)
+    SW_TYPE_DEF(SW_IP_HOSTENTRY, (param_check_t)cmd_data_check_host_entry, NULL),
+    SW_TYPE_DEF(SW_ARP_LEARNMODE, cmd_data_check_arp_learn_mode, NULL),
+    SW_TYPE_DEF(SW_IP_GUARDMODE, cmd_data_check_ip_guard_mode, NULL),
+    SW_TYPE_DEF(SW_NATENTRY, (param_check_t)cmd_data_check_nat_entry, NULL),
+    SW_TYPE_DEF(SW_NAPTENTRY, (param_check_t)cmd_data_check_napt_entry, NULL),
+    SW_TYPE_DEF(SW_FLOWENTRY, (param_check_t)cmd_data_check_flow_entry, NULL),
+    SW_TYPE_DEF(SW_FLOWCOOKIE, (param_check_t)cmd_data_check_flow_cookie, NULL),
+    SW_TYPE_DEF(SW_FLOWRFS, (param_check_t)cmd_data_check_flow_rfs, NULL),
+    SW_TYPE_DEF(SW_NAPTMODE, cmd_data_check_napt_mode, NULL),
+    SW_TYPE_DEF(SW_IP4ADDR, (param_check_t)cmd_data_check_ip4addr, NULL),
+    SW_TYPE_DEF(SW_IP6ADDR, (param_check_t)cmd_data_check_ip6addr, NULL),
+    SW_TYPE_DEF(SW_INTFMACENTRY, (param_check_t)cmd_data_check_intf_mac_entry, NULL),
+    SW_TYPE_DEF(SW_PUBADDRENTRY, (param_check_t)cmd_data_check_pub_addr_entry, NULL),
+#endif
+#ifdef IN_RATE
+    SW_TYPE_DEF(SW_INGPOLICER, (param_check_t)cmd_data_check_port_policer, NULL),
+    SW_TYPE_DEF(SW_EGSHAPER, (param_check_t)cmd_data_check_egress_shaper, NULL),
+    SW_TYPE_DEF(SW_ACLPOLICER, (param_check_t)cmd_data_check_acl_policer, NULL),
+#endif
+    SW_TYPE_DEF(SW_MACCONFIG, NULL, NULL),
+    SW_TYPE_DEF(SW_PHYCONFIG, NULL, NULL),
+#ifdef IN_FDB
+#ifndef IN_FDB_MINI
+    SW_TYPE_DEF(SW_FDBSMODE, cmd_data_check_fdb_smode, NULL),
+#endif
+#endif
+    SW_TYPE_DEF(SW_FX100CONFIG, NULL, NULL),
+#ifdef IN_IGMP
+    SW_TYPE_DEF(SW_SGENTRY, (param_check_t)cmd_data_check_multi, NULL),
+#endif
+#ifdef IN_SEC
+    SW_TYPE_DEF(SW_SEC_MAC, cmd_data_check_sec_mac, NULL),
+    SW_TYPE_DEF(SW_SEC_IP, cmd_data_check_sec_ip, NULL),
+    SW_TYPE_DEF(SW_SEC_IP4, cmd_data_check_sec_ip4, NULL),
+    SW_TYPE_DEF(SW_SEC_IP6, cmd_data_check_sec_ip6, NULL),
+    SW_TYPE_DEF(SW_SEC_TCP, cmd_data_check_sec_tcp, NULL),
+    SW_TYPE_DEF(SW_SEC_UDP, cmd_data_check_sec_udp, NULL),
+    SW_TYPE_DEF(SW_SEC_ICMP4, cmd_data_check_sec_icmp4, NULL),
+    SW_TYPE_DEF(SW_SEC_ICMP6, cmd_data_check_sec_icmp6, NULL),
+#ifdef HPPE
+    SW_TYPE_DEF(SW_L3_PARSER, (param_check_t)cmd_data_check_l3_parser, NULL),
+    SW_TYPE_DEF(SW_L4_PARSER, (param_check_t)cmd_data_check_l4_parser, NULL),
+    SW_TYPE_DEF(SW_EXP_CTRL, (param_check_t)cmd_data_check_exp_ctrl, NULL),
+#endif
+#endif
+#ifdef IN_COSMAP
+#ifndef IN_COSMAP_MINI
+    SW_TYPE_DEF(SW_REMARKENTRY, (param_check_t)cmd_data_check_remark_entry, NULL),
+#endif
+#endif
+#ifdef IN_IP
+#ifndef IN_IP_MINI
+    SW_TYPE_DEF(SW_DEFAULT_ROUTE_ENTRY, (param_check_t)cmd_data_check_default_route_entry, NULL),
+    SW_TYPE_DEF(SW_HOST_ROUTE_ENTRY, (param_check_t)cmd_data_check_host_route_entry, NULL),
+    SW_TYPE_DEF(SW_IP_RFS_IP4, (param_check_t)cmd_data_check_ip4_rfs_entry, NULL),
+    SW_TYPE_DEF(SW_IP_RFS_IP6, (param_check_t)cmd_data_check_ip6_rfs_entry, NULL),
+    SW_TYPE_DEF(SW_ARP_SG_CFG, (param_check_t)cmd_data_check_arp_sg, NULL),
+    SW_TYPE_DEF(SW_IP_NETWORK_ROUTE, (param_check_t)cmd_data_check_network_route, NULL),
+    SW_TYPE_DEF(SW_IP_INTF, (param_check_t)cmd_data_check_intf, NULL),
+    SW_TYPE_DEF(SW_IP_VSI_INTF, (param_check_t)cmd_data_check_vsi_intf, NULL),
+    SW_TYPE_DEF(SW_IP_NEXTHOP, (param_check_t)cmd_data_check_nexthop, NULL),
+    SW_TYPE_DEF(SW_IP_SG, (param_check_t)cmd_data_check_ip_sg, NULL),
+    SW_TYPE_DEF(SW_IP_PUB, (param_check_t)cmd_data_check_ip_pub, NULL),
+    SW_TYPE_DEF(SW_IP_PORTMAC, (param_check_t)cmd_data_check_ip_portmac, NULL),
+    SW_TYPE_DEF(SW_IP_MCMODE, (param_check_t)cmd_data_check_ip_mcmode, NULL),
+    SW_TYPE_DEF(SW_IP_GLOBAL, (param_check_t)cmd_data_check_ip_global, NULL),
+#endif
+#endif
+#ifdef IN_PORTCONTROL
+#ifndef IN_PORTCONTROL_MINI
+    SW_TYPE_DEF(SW_CROSSOVER_MODE, cmd_data_check_crossover_mode, NULL),
+    SW_TYPE_DEF(SW_CROSSOVER_STATUS, cmd_data_check_crossover_status, NULL),
+    SW_TYPE_DEF(SW_PREFER_MEDIUM, cmd_data_check_prefer_medium, NULL),
+    SW_TYPE_DEF(SW_FIBER_MODE, cmd_data_check_fiber_mode, NULL),
+    SW_TYPE_DEF(SW_SRC_FILTER_CONFIG, cmd_data_check_src_filter_config, NULL),
+    SW_TYPE_DEF(SW_MTU_ENTRY, (param_check_t)cmd_data_check_mtu_entry, NULL),
+    SW_TYPE_DEF(SW_MRU_ENTRY, (param_check_t)cmd_data_check_mru_entry, NULL),
+#endif
+#endif
+#ifdef IN_INTERFACECONTROL
+    SW_TYPE_DEF(SW_INTERFACE_MODE, cmd_data_check_interface_mode, NULL),
+#endif
+    SW_TYPE_DEF(SW_COUNTER_INFO, NULL, NULL),
+#ifdef IN_VSI
+    SW_TYPE_DEF(SW_VSI_NEWADDR_LRN, (param_check_t)cmd_data_check_newadr_lrn, NULL),
+    SW_TYPE_DEF(SW_VSI_STAMOVE, (param_check_t)cmd_data_check_stamove, NULL),
+    SW_TYPE_DEF(SW_VSI_MEMBER, (param_check_t)cmd_data_check_vsi_member, NULL),
+    SW_TYPE_DEF(SW_VSI_COUNTER, NULL, NULL),
+#endif
+#ifdef IN_QM
+    SW_TYPE_DEF(SW_STATIC_THRESH, (param_check_t)cmd_data_check_ac_static_thresh, NULL),
+    SW_TYPE_DEF(SW_DYNAMIC_THRESH, (param_check_t)cmd_data_check_ac_dynamic_thresh, NULL),
+    SW_TYPE_DEF(SW_GROUP_BUFFER, (param_check_t)cmd_data_check_ac_group_buff, NULL),
+    SW_TYPE_DEF(SW_AC_CTRL, (param_check_t)cmd_data_check_ac_ctrl, NULL),
+    SW_TYPE_DEF(SW_AC_OBJ, (param_check_t)cmd_data_check_ac_obj, NULL),
+    SW_TYPE_DEF(SW_UCAST_QUEUE_MAP, (param_check_t)cmd_data_check_u_qmap, NULL),
+#endif
+#ifdef IN_BM
+    SW_TYPE_DEF(SW_BMSTHRESH, (param_check_t)cmd_data_check_bm_static_thresh, NULL),
+    SW_TYPE_DEF(SW_BMDTHRESH, (param_check_t)cmd_data_check_bm_dynamic_thresh, NULL),
+#endif
+#ifdef IN_FLOW
+    SW_TYPE_DEF(SW_FLOW_AGE, (param_check_t)cmd_data_check_flow_age, NULL),
+    SW_TYPE_DEF(SW_FLOW_CTRL, (param_check_t)cmd_data_check_flow_ctrl, NULL),
+    SW_TYPE_DEF(SW_FLOW_ENTRY, (param_check_t)cmd_data_check_flow, NULL),
+    SW_TYPE_DEF(SW_FLOW_GLOBAL, (param_check_t)cmd_data_check_flow_global, NULL),
+    SW_TYPE_DEF(SW_FLOW_HOST, (param_check_t)cmd_data_check_flow_host, NULL),
+#endif
+#ifdef IN_PORTCONTROL
+#ifndef IN_PORTCONTROL_MINI
+    SW_TYPE_DEF(SW_MTU_INFO, NULL, NULL),
+    SW_TYPE_DEF(SW_MRU_INFO, NULL, NULL),
+    SW_TYPE_DEF(SW_MTU_ENTRY, (param_check_t)cmd_data_check_mtu_entry, NULL),
+    SW_TYPE_DEF(SW_MRU_ENTRY, (param_check_t)cmd_data_check_mru_entry, NULL),
+#endif
+#endif
+#ifdef IN_SHAPER
+    SW_TYPE_DEF(SW_PORT_SHAPER_TOKEN_CONFIG,
+		    (param_check_t)cmd_data_check_port_shaper_token_config, NULL),
+    SW_TYPE_DEF(SW_SHAPER_TOKEN_CONFIG, (param_check_t)cmd_data_check_shaper_token_config, NULL),
+    SW_TYPE_DEF(SW_PORT_SHAPER_CONFIG, (param_check_t)cmd_data_check_port_shaper_config, NULL),
+    SW_TYPE_DEF(SW_SHAPER_CONFIG, (param_check_t)cmd_data_check_shaper_config, NULL),
+#endif
+
+#ifdef IN_POLICER
+    SW_TYPE_DEF(SW_POLICER_ACL_CONFIG, (param_check_t)cmd_data_check_acl_policer_config, NULL),
+    SW_TYPE_DEF(SW_POLICER_PORT_CONFIG, (param_check_t)cmd_data_check_port_policer_config, NULL),
+    SW_TYPE_DEF(SW_POLICER_CMD_CONFIG, (param_check_t)cmd_data_check_policer_cmd_config, NULL),
+#endif
+#ifdef IN_SERVCODE
+    SW_TYPE_DEF(SW_SERVCODE_CONFIG, (param_check_t)cmd_data_check_servcode_config, NULL),
+#endif
+#ifdef IN_RSS_HASH
+    SW_TYPE_DEF(SW_RSS_HASH_MODE, (param_check_t)cmd_data_check_rss_hash_mode, NULL),
+    SW_TYPE_DEF(SW_RSS_HASH_CONFIG, (param_check_t)cmd_data_check_rss_hash_config, NULL),
+#endif
+#ifdef IN_MIRROR
+    SW_TYPE_DEF(SW_MIRR_DIRECTION, cmd_data_check_mirr_direction, NULL),
+    SW_TYPE_DEF(SW_MIRR_ANALYSIS_CONFIG, (param_check_t)cmd_data_check_mirr_analy_cfg, NULL),
+#endif
+#ifdef IN_CTRLPKT
+    SW_TYPE_DEF(SW_CTRLPKT_PROFILE, (param_check_t)cmd_data_check_ctrlpkt_appprofile, NULL),
+#endif
+};
+
+sw_data_type_t *
+cmd_data_type_find(sw_data_type_e type)
+{
+    a_uint16_t i = 0;
+
+    do
+    {
+        if (type == sw_data_type[i].data_type)
+            return &sw_data_type[i];
+    }
+    while ( ++i < sizeof(sw_data_type)/sizeof(sw_data_type[0]));
+
+    return NULL;
+}
+
+sw_error_t __cmd_data_check_quit_help(char *cmd, char *usage)
+{
+    sw_error_t ret = SW_OK;
+
+    if (!strncasecmp(cmd, "quit", 4)) {
+        return SW_ABORTED;
+    } else if (!strncasecmp(cmd, "help", 4)) {
+        ret = SW_BAD_VALUE;
+    }
+
+    return ret;
+}
+
+sw_error_t __cmd_data_check_complex(char *info, char *defval, char *usage,
+				param_check_t chk_func, void *arg_val,
+				a_uint32_t size)
+{
+    sw_error_t ret;
+    char *cmd;
+
+    do {
+        cmd = get_sub_cmd(info, defval);
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        ret = __cmd_data_check_quit_help(cmd, usage);
+        if (ret == SW_ABORTED)
+            return ret;
+        else if (ret == SW_OK) {
+            ret = chk_func(cmd, arg_val, size);
+        }
+    } while (talk_mode && (SW_OK != ret));
+
+    return SW_OK;
+}
+
+sw_error_t __cmd_data_check_range(char *info, char *defval, char *usage,
+				param_check_range_t chk_func, void *arg_val,
+				a_uint32_t max_val, a_uint32_t min_val)
+{
+    sw_error_t ret;
+    char *cmd;
+
+    do {
+        cmd = get_sub_cmd(info, defval);
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        ret = __cmd_data_check_quit_help(cmd, usage);
+        if (ret == SW_ABORTED)
+            return ret;
+        else if (ret == SW_OK) {
+            ret = chk_func(cmd, arg_val, max_val, min_val);
+        }
+    } while (talk_mode && (SW_OK != ret));
+
+    return SW_OK;
+}
+
+sw_error_t __cmd_data_check_boolean(char *info, char *defval, char *usage,
+				param_check_boolean_t chk_func, a_bool_t def, a_bool_t *val,
+				a_uint32_t size)
+{
+    sw_error_t ret;
+    char *cmd;
+
+    do {
+        cmd = get_sub_cmd(info, defval);
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        ret = __cmd_data_check_quit_help(cmd, usage);
+        if (ret == SW_ABORTED)
+            return ret;
+        else if (ret == SW_OK) {
+            ret = chk_func(cmd, def, val, size);
+        }
+    } while (talk_mode && (SW_OK != ret));
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_uint8(char *cmd_str, a_uint32_t *arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (0 == cmd_str[0])
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (cmd_str[0] == '0' && (cmd_str[1] == 'x' || cmd_str[1] == 'X'))
+        sscanf(cmd_str, "%x", arg_val);
+    else
+        sscanf(cmd_str, "%d", arg_val);
+
+    if (255 < *arg_val)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_uint32(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (0 == cmd_str[0])
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (strspn(cmd_str, "1234567890abcdefABCDEFXx") != strlen(cmd_str)){
+        return SW_BAD_VALUE;
+    }
+
+    if (cmd_str[0] == '0' && (cmd_str[1] == 'x' || cmd_str[1] == 'X'))
+        sscanf(cmd_str, "%x", arg_val);
+    else
+        sscanf(cmd_str, "%d", arg_val);
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_uint16(char *cmd_str, a_uint32_t *arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (0 == cmd_str[0])
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (cmd_str[0] == '0' && (cmd_str[1] == 'x' || cmd_str[1] == 'X'))
+        sscanf(cmd_str, "%x", arg_val);
+    else
+        sscanf(cmd_str, "%d", arg_val);
+
+    if (65535 < *arg_val)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_pbmp(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (cmd_str[0] == '0' && (cmd_str[1] == 'x' || cmd_str[1] == 'X'))
+        sscanf(cmd_str, "%x", arg_val);
+    else
+        sscanf(cmd_str, "%d", arg_val);
+
+    return SW_OK;
+
+}
+
+sw_error_t
+cmd_data_check_enable(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "disable"))
+        *arg_val = FAL_DISABLE;
+    else if (!strcasecmp(cmd_str, "enable"))
+        *arg_val = FAL_ENABLE;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#ifdef IN_PORTCONTROL
+/*port ctrl*/
+sw_error_t
+cmd_data_check_duplex(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "half"))
+        *arg_val = FAL_HALF_DUPLEX;
+    else if (!strcasecmp(cmd_str, "full"))
+        *arg_val = FAL_FULL_DUPLEX;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_speed(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strncasecmp(cmd_str, "10", 3))
+        *arg_val = FAL_SPEED_10;
+    else if (!strncasecmp(cmd_str, "100", 4))
+        *arg_val = FAL_SPEED_100;
+    else if (!strncasecmp(cmd_str, "1000", 5))
+        *arg_val = FAL_SPEED_1000;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_capable(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    cmd_strtol(cmd_str, arg_val);
+    if (*arg_val & (~FAL_PHY_COMBO_ADV_ALL))
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#ifndef IN_PORTCONTROL_MINI
+sw_error_t
+cmd_data_check_port_eee_config(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_port_eee_cfg_t cfg;
+
+    aos_mem_zero(&cfg, sizeof (fal_port_eee_cfg_t));
+
+    do
+    {
+        cmd = get_sub_cmd("eee_enable", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(cfg.enable),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+    do
+    {
+        cmd = get_sub_cmd("eee_capability", "0xffff");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(cfg.capability), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("lpi_sleep_timer", "256");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(cfg.lpi_sleep_timer), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("advertisement", "0xffff");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(cfg.advertisement), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+
+    do
+    {
+        cmd = get_sub_cmd("lpi_tx_enable", "1");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(cfg.lpi_tx_enable), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("eee_status", "0xffff");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(cfg.eee_status), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("lpi_wakeup_timer", "32");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(cfg.lpi_wakeup_timer), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("link_partner_advertisement", "0xffff");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(cfg.link_partner_advertisement), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_port_eee_cfg_t *)val = cfg;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_switch_port_loopback_config(char *cmd_str, void * val,
+	a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_loopback_config_t cfg;
+
+    aos_mem_zero(&cfg, sizeof (fal_loopback_config_t));
+
+    do
+    {
+        cmd = get_sub_cmd("loopback_enable", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(cfg.enable),
+                                        sizeof (a_bool_t));
+            SW_RTN_ON_ERROR(rv);
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("crc_stripped_enable", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(cfg.crc_stripped),
+                                        sizeof (a_bool_t));
+            SW_RTN_ON_ERROR(rv);
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("loopback_rate", "1-0x12c");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(cfg.loopback_rate), sizeof (a_uint32_t));
+            SW_RTN_ON_ERROR(rv);
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_loopback_config_t *)val = cfg;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_crossover_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strncasecmp(cmd_str, "auto", 5))
+        *arg_val = PHY_MDIX_AUTO;
+    else if (!strncasecmp(cmd_str, "mdi", 4))
+        *arg_val = PHY_MDIX_MDI;
+    else if (!strncasecmp(cmd_str, "mdix", 5))
+        *arg_val = PHY_MDIX_MDIX;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_crossover_status(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+    if (!strncasecmp(cmd_str, "mdi", 4))
+        *arg_val = PHY_MDIX_STATUS_MDI;
+    else if (!strncasecmp(cmd_str, "mdix", 5))
+        *arg_val = PHY_MDIX_STATUS_MDIX;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_prefer_medium(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+    if (!strncasecmp(cmd_str, "copper", 7))
+        *arg_val = PHY_MEDIUM_COPPER;
+    else if (!strncasecmp(cmd_str, "fiber", 6))
+        *arg_val = PHY_MEDIUM_FIBER;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_fiber_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+    if (!strncasecmp(cmd_str, "100fx", 6))
+    {
+	*arg_val = PHY_FIBER_100FX;
+    }
+    else if (!strncasecmp(cmd_str, "1000bx", 7))
+    {
+	*arg_val = PHY_FIBER_1000BX;
+    }
+    else if (!strncasecmp(cmd_str, "10g_r", 7))
+    {
+	*arg_val = PHY_FIBER_10G_R;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_source_filter_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+	if (cmd_str == NULL)
+	{
+		return SW_BAD_PARAM;
+	}
+	if (!strncasecmp(cmd_str, "virtual_port", 15))
+	{
+		*arg_val = FAL_SRC_FILTER_MODE_VP;
+	}
+	else if (!strncasecmp(cmd_str, "physical_port", 15))
+	{
+		*arg_val = FAL_SRC_FILTER_MODE_PHYSICAL;
+	}
+	else
+	{
+		return SW_BAD_VALUE;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_src_filter_config(char *cmd_str, a_uint32_t *arg_val, a_uint32_t size)
+{
+	char *cmd;
+	sw_error_t rv;
+	fal_src_filter_config_t src_filter_config;
+
+	aos_mem_zero(&src_filter_config, sizeof (fal_src_filter_config_t));
+
+	do
+	{
+		cmd = get_sub_cmd("src_filter_enable", "enable");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_enable(cmd, &(src_filter_config.src_filter_enable),
+					sizeof (a_bool_t));
+			SW_RTN_ON_ERROR(rv);
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("srcfilter_mode", "virtual_port");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			cmd_data_check_source_filter_mode(cmd, &(src_filter_config.src_filter_mode),
+				sizeof(a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	*(fal_src_filter_config_t *)arg_val = src_filter_config;
+
+	return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_mtu_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_mtu_ctrl_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_mtu_ctrl_t));
+
+    do
+    {
+        cmd = get_sub_cmd("mtu_size", "1514");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.mtu_size), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("mtu_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.action), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_mtu_ctrl_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_mru_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_mru_ctrl_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_mru_ctrl_t));
+
+    do
+    {
+        cmd = get_sub_cmd("mru_size", "1514");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.mru_size), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("mru_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.action), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_mru_ctrl_t *)val = entry;
+    return SW_OK;
+}
+
+#endif
+#endif
+#ifdef IN_INTERFACECONTROL
+sw_error_t
+cmd_data_check_interface_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strncasecmp(cmd_str, "psgmii_baset", 13))
+     {
+	*arg_val = PHY_PSGMII_BASET;
+     }
+    else if (!strncasecmp(cmd_str, "psgmii_bx1000", 14))
+    {
+	*arg_val = PHY_PSGMII_BX1000;
+    }
+    else if (!strncasecmp(cmd_str, "psgmii_fx100", 13))
+    {
+	*arg_val = PHY_PSGMII_FX100;
+    }
+    else if (!strncasecmp(cmd_str, "psgmii_amdet", 13))
+    {
+	*arg_val = PHY_PSGMII_AMDET;
+    }
+    else if (!strncasecmp(cmd_str, "rgmii_amdet", 13))
+    {
+	*arg_val = PORT_RGMII_AMDET;
+    }
+    else if (!strncasecmp(cmd_str, "rgmii_baset", 13))
+    {
+	*arg_val = PORT_RGMII_BASET;
+    }
+    else if (!strncasecmp(cmd_str, "rgmii_bx1000", 13))
+    {
+	*arg_val = PORT_RGMII_BX1000;
+    }
+    else if (!strncasecmp(cmd_str, "rgmii_fx100", 13))
+    {
+	*arg_val = PORT_RGMII_FX100;
+    }
+    else if (!strncasecmp(cmd_str, "sgmii_baset", 13))
+    {
+	*arg_val = PHY_SGMII_BASET;
+    }
+    else if (!strncasecmp(cmd_str, "qsgmii", 13))
+    {
+	*arg_val = PORT_QSGMII;
+    }
+    else if (!strncasecmp(cmd_str, "sgmii_plus", 13))
+    {
+	*arg_val = PORT_SGMII_PLUS;
+    }
+    else if (!strncasecmp(cmd_str, "usxgmii", 13))
+    {
+	*arg_val = PORT_USXGMII;
+    }
+    else if (!strncasecmp(cmd_str, "10gbase_r", 13))
+    {
+	*arg_val = PORT_10GBASE_R;
+    }
+    else if (!strncasecmp(cmd_str, "interfacemode_max", 20))
+    {
+	*arg_val = PORT_INTERFACE_MODE_MAX;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#endif
+/*portvlan*/
+#ifdef IN_PORTVLAN
+sw_error_t
+cmd_data_check_1qmode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "disable"))
+    {
+        *arg_val = FAL_1Q_DISABLE;
+    }
+    else if (!strcasecmp(cmd_str, "secure"))
+    {
+        *arg_val = FAL_1Q_SECURE;
+    }
+    else if (!strcasecmp(cmd_str, "check"))
+    {
+        *arg_val = FAL_1Q_CHECK;
+    }
+    else if (!strcasecmp(cmd_str, "fallback"))
+    {
+        *arg_val = FAL_1Q_FALLBACK;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+
+
+sw_error_t
+cmd_data_check_egmode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "unmodified"))
+    {
+        *arg_val = FAL_EG_UNMODIFIED;
+    }
+    else if (!strcasecmp(cmd_str, "untagged"))
+    {
+        *arg_val = FAL_EG_UNTAGGED;
+    }
+    else if (!strcasecmp(cmd_str, "tagged"))
+    {
+        *arg_val = FAL_EG_TAGGED;
+    }
+    else if (!strcasecmp(cmd_str, "hybrid"))
+    {
+        *arg_val = FAL_EG_HYBRID;
+    }
+    else if (!strcasecmp(cmd_str, "untouched"))
+    {
+        *arg_val = FAL_EG_UNTOUCHED;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#endif
+/*vlan*/
+#ifdef IN_VLAN
+sw_error_t
+cmd_data_check_vlan(char *cmdstr, fal_vlan_t * val, a_uint32_t size)
+{
+    sw_error_t rv;
+    fal_vlan_t entry;
+    a_uint32_t tmp = 0;
+
+    memset(&entry, 0, sizeof (fal_vlan_t));
+
+    rv = __cmd_data_check_complex("vlanid", NULL,
+                        "usage: the range is 0 -- 4095\n",
+                        (param_check_t)cmd_data_check_uint16, &tmp, sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+    entry.vid = tmp & 0xffff;
+
+    rv = __cmd_data_check_complex("fid", NULL,
+                        "usage: the range is 0 -- 4095 or 65535\n",
+                        (param_check_t)cmd_data_check_uint16, &tmp, sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+    entry.fid = tmp & 0xffff;
+
+    rv = __cmd_data_check_complex("port member", "null",
+                        "usage: input port number such as 1,3\n",
+                        (param_check_t)cmd_data_check_portmap, &entry.mem_ports,
+                        sizeof (fal_pbmp_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("tagged member", "null",
+                        "usage: input port number such as 1,3\n",
+                        (param_check_t)cmd_data_check_portmap, &entry.tagged_ports,
+                        sizeof (fal_pbmp_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("untagged member", "null",
+                        "usage: input port number such as 1,3\n",
+                        (param_check_t)cmd_data_check_portmap, &entry.untagged_ports,
+                        sizeof (fal_pbmp_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("unmodify member", "null",
+                        "usage: input port number such as 1,3\n",
+                        (param_check_t)cmd_data_check_portmap, &entry.unmodify_ports,
+                        sizeof (fal_pbmp_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("unmodify member", "null",
+                        "usage: input port number such as 1,3\n",
+                        (param_check_t)cmd_data_check_portmap, &entry.unmodify_ports,
+                        sizeof (fal_pbmp_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("learn disable", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.learn_dis,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("queue override", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.vid_pri_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    if (A_TRUE == entry.vid_pri_en)
+    {
+        rv = __cmd_data_check_complex("queue", NULL,
+                        "usage: input number such as <0/1/2/3>\n",
+                        (param_check_t)cmd_data_check_uint32, &tmp, sizeof (a_uint32_t));
+        if (rv)
+            return rv;
+
+        entry.vid_pri = tmp;
+    }
+
+    *val = entry;
+    return SW_OK;
+}
+#endif
+/*qos*/
+#ifdef IN_QOS
+#ifndef IN_QOS_MINI
+sw_error_t
+cmd_data_check_port_group(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_qos_group_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_qos_group_t));
+
+    do
+    {
+        cmd = get_sub_cmd("pcp_group", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.pcp_group),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("dscp_group", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.dscp_group),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("flow_group", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.flow_group),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_qos_group_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_port_pri(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_qos_pri_precedence_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_qos_pri_precedence_t));
+
+    do
+    {
+        cmd = get_sub_cmd("pcp_pri_prece", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.pcp_pri),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("dscp_pri_prece", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.dscp_pri),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("preheader_pri_prece", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.preheader_pri),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("flow_pri_prece", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.flow_pri),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("acl_pri_prece", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.acl_pri),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("post_acl_pri_prece", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.post_acl_pri),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("pcp_pri_force", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.pcp_pri_force),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("dscp_pri_force", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.dscp_pri_force),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_qos_pri_precedence_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_port_remark(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_qos_remark_enable_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_qos_remark_enable_t));
+
+    do
+    {
+        cmd = get_sub_cmd("pcp_change_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.pcp_change_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("dei_change_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.dei_chage_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("dscp_change_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.dscp_change_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_qos_remark_enable_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_cosmap(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_qos_cosmap_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_qos_cosmap_t));
+
+    do
+    {
+        cmd = get_sub_cmd("internal_pcp", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.internal_pcp),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("internal_dei", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.internal_dei),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("internal_pri", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.internal_pri),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("internal_dscp", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.internal_dscp),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("internal_dp", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.internal_dp),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("dscp_mask", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.dscp_mask),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("dscp_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.dscp_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("pcp_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.pcp_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("dei_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.dei_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("pri_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.pri_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("dp_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.dp_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("qos_prec", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.qos_prec),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_qos_cosmap_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_queue_scheduler(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_qos_scheduler_cfg_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_qos_scheduler_cfg_t));
+
+    do
+    {
+        cmd = get_sub_cmd("sp_id", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.sp_id),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("e_pri", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.e_pri),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("c_pri", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.c_pri),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("e_drr_id", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.e_drr_id),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("c_drr_id", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.c_drr_id),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("e_drr_wt", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.e_drr_wt),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("c_drr_wt", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.c_drr_wt),
+                                       sizeof (a_uint16_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("c_drr_ut", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.c_drr_unit),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("e_drr_ut", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.e_drr_unit),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("drr_frame_mode", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.drr_frame_mode),
+                                       sizeof (a_uint32_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_qos_scheduler_cfg_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ring_queue(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    a_uint32_t i = 0;
+    sw_error_t rv;
+    fal_queue_bmp_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_queue_bmp_t));
+
+    do
+    {
+        cmd = get_sub_cmd("bmp", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.bmp[i]),
+                                       sizeof (a_uint32_t));
+        }
+
+    }
+    while ((talk_mode && (SW_OK != rv)) || (++i < 10));
+
+    *(fal_queue_bmp_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_qos_sch(char *cmdstr, fal_sch_mode_t * val, a_uint32_t size)
+{
+    if (cmdstr == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmdstr, "sp"))
+    {
+        *val = FAL_SCH_SP_MODE;
+    }
+    else if (!strcasecmp(cmdstr, "wrr"))
+    {
+        *val = FAL_SCH_WRR_MODE;
+    }
+    else if (!strcasecmp(cmdstr, "mixplus"))
+    {
+        *val = FAL_SCH_MIX_PLUS_MODE;
+    }
+    else if (!strcasecmp(cmdstr, "mix"))
+    {
+        *val = FAL_SCH_MIX_MODE;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_qos_pt(char *cmdstr, fal_qos_mode_t * val, a_uint32_t size)
+{
+    if (cmdstr == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmdstr, "da"))
+    {
+        *val = FAL_QOS_DA_MODE;
+    }
+    else if (!strcasecmp(cmdstr, "up"))
+    {
+        *val = FAL_QOS_UP_MODE;
+    }
+    else if (!strcasecmp(cmdstr, "dscp"))
+    {
+        *val = FAL_QOS_DSCP_MODE;
+    }
+    else if (!strcasecmp(cmdstr, "port"))
+    {
+        *val = FAL_QOS_PORT_MODE;
+    }
+    else if (!strcasecmp(cmdstr, "flow"))
+    {
+        *val = FAL_QOS_FLOW_MODE;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#endif
+#endif
+
+/*rate*/
+#ifdef IN_RATE
+sw_error_t
+cmd_data_check_storm(char *cmdstr, fal_storm_type_t * val, a_uint32_t size)
+{
+    if (cmdstr == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmdstr, "unicast"))
+    {
+        *val = FAL_UNICAST_STORM;
+    }
+    else if (!strcasecmp(cmdstr, "multicast"))
+    {
+        *val = FAL_MULTICAST_STORM;
+    }
+    else if (!strcasecmp(cmdstr, "broadcast"))
+    {
+        *val = FAL_BROADCAST_STORM;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#endif
+
+/*stp*/
+#ifdef IN_STP
+sw_error_t
+cmd_data_check_stp_state(char *cmdstr, fal_stp_state_t * val, a_uint32_t size)
+{
+    if (cmdstr == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmdstr, "disable"))
+    {
+        *val = FAL_STP_DISABLED;
+    }
+    else if (!strcasecmp(cmdstr, "block"))
+    {
+        *val = FAL_STP_BLOKING;
+    }
+    else if (!strcasecmp(cmdstr, "listen"))
+    {
+        *val = FAL_STP_LISTENING;
+    }
+    else if (!strcasecmp(cmdstr, "learn"))
+    {
+        *val = FAL_STP_LEARNING;
+    }
+    else if (!strcasecmp(cmdstr, "forward"))
+    {
+        *val = FAL_STP_FARWARDING;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#endif
+
+#ifdef IN_LEAKY
+/*general*/
+sw_error_t
+cmd_data_check_leaky(char *cmdstr, fal_leaky_ctrl_mode_t * val, a_uint32_t size)
+{
+    if (cmdstr == NULL)
+        return SW_BAD_VALUE;
+
+    if (!strcasecmp(cmdstr, "port"))
+    {
+        *val = FAL_LEAKY_PORT_CTRL;
+    }
+    else if (!strcasecmp(cmdstr, "fdb"))
+    {
+        *val = FAL_LEAKY_FDB_CTRL;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#endif
+
+sw_error_t
+cmd_data_check_uinta(char *cmdstr, a_uint32_t * val, a_uint32_t size)
+{
+    char *tmp_str = NULL;
+    a_uint32_t *tmp_ptr = val;
+    a_uint32_t i = 0;
+
+    tmp_str = (void *) strsep(&cmdstr, ",");
+
+    while (tmp_str)
+    {
+        if (i >= (size / 4))
+        {
+            return SW_BAD_VALUE;
+        }
+
+        sscanf(tmp_str, "%d", tmp_ptr);
+        tmp_ptr++;
+
+        i++;
+        tmp_str = (void *) strsep(&cmdstr, ",");
+    }
+
+    if (i != (size / 4))
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+
+/*fdb*/
+sw_error_t
+cmd_data_check_maccmd(char *cmdstr, fal_fwd_cmd_t * val, a_uint32_t size)
+{
+    if (NULL == cmdstr)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (0 == cmdstr[0])
+    {
+        *val = FAL_MAC_FRWRD;   //defualt
+    }
+    else if (!strcasecmp(cmdstr, "forward"))
+    {
+        *val = FAL_MAC_FRWRD;
+    }
+    else if (!strcasecmp(cmdstr, "drop"))
+    {
+        *val = FAL_MAC_DROP;
+    }
+    else if (!strcasecmp(cmdstr, "cpycpu"))
+    {
+        *val = FAL_MAC_CPY_TO_CPU;
+    }
+    else if (!strcasecmp(cmdstr, "rdtcpu"))
+    {
+        *val = FAL_MAC_RDT_TO_CPU;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+/*flow*/
+#ifdef IN_IP
+#ifndef IN_IP_MINI
+sw_error_t
+cmd_data_check_flowcmd(char *cmdstr, fal_default_flow_cmd_t * val, a_uint32_t size)
+{
+    if (NULL == cmdstr)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (0 == cmdstr[0])
+    {
+        *val = FAL_DEFAULT_FLOW_FORWARD;   //default
+    }
+    else if (!strcasecmp(cmdstr, "forward"))
+    {
+        *val = FAL_DEFAULT_FLOW_FORWARD;
+    }
+    else if (!strcasecmp(cmdstr, "drop"))
+    {
+        *val = FAL_DEFAULT_FLOW_DROP;
+    }
+    else if (!strcasecmp(cmdstr, "rdtcpu"))
+    {
+        *val = FAL_DEFAULT_FLOW_RDT_TO_CPU;
+    }
+    else if (!strcasecmp(cmdstr, "admit_all"))
+    {
+        *val = FAL_DEFAULT_FLOW_ADMIT_ALL;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_flowtype(char *cmd_str, fal_flow_type_t * arg_val,
+                        a_uint32_t size)
+{
+    if (NULL == cmd_str)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (!strcasecmp(cmd_str, "lan2lan"))
+    {
+        *arg_val = FAL_FLOW_LAN_TO_LAN;
+    }
+    else if (!strcasecmp(cmd_str, "wan2lan"))
+    {
+        *arg_val = FAL_FLOW_WAN_TO_LAN;
+    }
+    else if (!strcasecmp(cmd_str, "lan2wan"))
+    {
+        *arg_val = FAL_FLOW_LAN_TO_WAN;
+    }
+    else if (!strcasecmp(cmd_str, "wan2wan"))
+    {
+        *arg_val = FAL_FLOW_WAN_TO_WAN;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#endif
+#endif
+sw_error_t
+cmd_data_check_confirm(char *cmdstr, a_bool_t def, a_bool_t * val,
+                       a_uint32_t size)
+{
+    if (0 == cmdstr[0])
+    {
+        *val = def;
+    }
+    else if ((!strcasecmp(cmdstr, "yes")) || (!strcasecmp(cmdstr, "y")))
+    {
+        *val = A_TRUE;
+    }
+    else if ((!strcasecmp(cmdstr, "no")) || (!strcasecmp(cmdstr, "n")))
+    {
+        *val = A_FALSE;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_portmap(char *cmdstr, fal_pbmp_t * val, a_uint32_t size)
+{
+    char *tmp = NULL;
+    a_uint32_t i = 0;
+    a_uint32_t port;
+
+    *val = 0;
+    //default input null
+    if(!strcasecmp(cmdstr, "null"))
+    {
+        return SW_OK;
+    }
+
+    tmp = (void *) strsep(&cmdstr, ",");
+    while (tmp)
+    {
+        if (SW_MAX_NR_PORT <= i)
+        {
+            return SW_BAD_VALUE;
+        }
+
+        sscanf(tmp, "%d", &port);
+        if (SW_MAX_NR_PORT <= port)
+        {
+            return SW_BAD_VALUE;
+        }
+
+        *val |= (0x1 << port);
+        tmp = (void *) strsep(&cmdstr, ",");
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_macaddr(char *cmdstr, void *val, a_uint32_t size)
+{
+    char *tmp = NULL;
+    a_uint32_t i = 0, j;
+    a_uint32_t addr;
+    fal_mac_addr_t mac;
+
+    memset(&mac, 0, sizeof (fal_mac_addr_t));
+    if (NULL == cmdstr)
+    {
+        *(fal_mac_addr_t *) val = mac;
+        return SW_BAD_VALUE; /*was: SW_OK;*/
+    }
+
+    if (0 == cmdstr[0])
+    {
+        *(fal_mac_addr_t *) val = mac;
+        return SW_OK;
+    }
+
+    tmp = (void *) strsep(&cmdstr, "-");
+    while (tmp)
+    {
+        if (6 <= i)
+        {
+            return SW_BAD_VALUE;
+        }
+
+        if ((2 < strlen(tmp)) || (0 == strlen(tmp)))
+        {
+            return SW_BAD_VALUE;
+        }
+
+        for (j = 0; j < strlen(tmp); j++)
+        {
+            if (A_FALSE == is_hex(tmp[j]))
+                return SW_BAD_VALUE;
+        }
+
+        sscanf(tmp, "%x", &addr);
+        if (0xff < addr)
+        {
+            return SW_BAD_VALUE;
+        }
+
+        mac.uc[i++] = addr;
+        tmp = (void *) strsep(&cmdstr, "-");
+    }
+
+    if (6 != i)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    *(fal_mac_addr_t *) val = mac;
+    return SW_OK;
+}
+#ifdef IN_FDB
+sw_error_t
+cmd_data_check_fdbentry(char *info, void *val, a_uint32_t size)
+{
+    sw_error_t rv;
+    fal_fdb_entry_t entry;
+    a_uint32_t tmp = 0;
+
+    memset(&entry, 0, sizeof (fal_fdb_entry_t));
+
+    rv = __cmd_data_check_complex("addr", NULL,
+                        "usage: the format is xx-xx-xx-xx-xx-xx \n",
+                        (param_check_t)cmd_data_check_macaddr, &entry.addr,
+                        sizeof (fal_mac_addr_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("fid", "65535",
+                        "usage: the range is 1 -- 4095 or 65535\n",
+                        (param_check_t)cmd_data_check_uint32, &tmp, sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+    entry.fid = tmp & 0xffff;
+
+    rv = __cmd_data_check_complex("dacmd", "forward",
+                        "usage: <forward/drop/cpycpu/rdtcpu>\n",
+                        (param_check_t)cmd_data_check_maccmd, &entry.dacmd,
+                        sizeof (fal_fwd_cmd_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("sacmd", "forward",
+                        "usage: <forward/drop/cpycpu/rdtcpu>\n",
+                        (param_check_t)cmd_data_check_maccmd, &entry.sacmd,
+                        sizeof (fal_fwd_cmd_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("dest port", "null",
+                        "usage: input port number such as 1,3\n",
+                        (param_check_t)cmd_data_check_portmap, &entry.port.map,
+                        sizeof (fal_pbmp_t));
+    if (rv)
+        return rv;
+
+    entry.portmap_en = A_TRUE;
+
+    rv = __cmd_data_check_boolean("static", "yes",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_TRUE, &entry.static_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("leaky", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.leaky_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("mirror", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.mirror_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("clone", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.clone_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("queue override", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE,
+			&entry.da_pri_en, sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    if (A_TRUE == entry.da_pri_en)
+    {
+        rv = __cmd_data_check_complex("queue", NULL,
+                            "usage: input number such as <0/1/2/3>\n",
+                            (param_check_t)cmd_data_check_uint32, &tmp,
+			    sizeof (a_uint32_t));
+        if (rv)
+            return rv;
+        entry.da_queue = tmp;
+    }
+
+    rv = __cmd_data_check_boolean("cross_pt_state", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, 
+			&entry.cross_pt_state, sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("white_list_en", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE,
+			&entry.white_list_en, sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("load_balance_en", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.load_balance_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    if (A_TRUE == entry.load_balance_en)
+    {
+        rv = __cmd_data_check_complex("load_balance", NULL,
+                            "usage: input number such as <0/1/2/3>\n",
+                            (param_check_t)cmd_data_check_uint32, &tmp, sizeof (a_uint32_t));
+        if (rv)
+            return rv;
+        entry.load_balance = tmp;
+    }
+
+    *(fal_fdb_entry_t *) val = entry;
+
+    return SW_OK;
+}
+#ifndef IN_FDB_MINI
+sw_error_t
+cmd_data_check_maclimit_ctrl(char *info, void *val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_maclimit_ctrl_t maclimit_ctrl;
+
+    memset(&maclimit_ctrl, 0, sizeof (fal_maclimit_ctrl_t));
+
+    do
+    {
+        cmd = get_sub_cmd("enable", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &maclimit_ctrl.enable,
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("limit num", "2048");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &maclimit_ctrl.limit_num,
+                                        sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &maclimit_ctrl.action,
+                                        sizeof (fal_fwd_cmd_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_maclimit_ctrl_t *) val = maclimit_ctrl;
+
+    return SW_OK;
+}
+#endif
+#endif
+sw_error_t
+cmd_data_check_integer(char *cmd_str, a_uint32_t * arg_val, a_uint32_t max_val,
+                       a_uint32_t min_val)
+{
+    a_uint32_t tmp;
+    a_uint32_t i;
+
+    if (NULL == cmd_str)
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if (0 == cmd_str[0])
+    {
+        return SW_BAD_PARAM;
+    }
+
+    if ((cmd_str[0] == '0') && ((cmd_str[1] == 'x') || (cmd_str[1] == 'X')))
+    {
+        for (i = 2; i < strlen(cmd_str); i++)
+        {
+            if (A_FALSE == is_hex(cmd_str[i]))
+            {
+                return SW_BAD_VALUE;
+            }
+        }
+        sscanf(cmd_str, "%x", &tmp);
+    }
+    else
+    {
+        for (i = 0; i < strlen(cmd_str); i++)
+        {
+            if (A_FALSE == is_dec(cmd_str[i]))
+            {
+                return SW_BAD_VALUE;
+            }
+        }
+        sscanf(cmd_str, "%d", &tmp);
+    }
+
+    if ((tmp > max_val) || (tmp < min_val))
+        return SW_BAD_PARAM;
+
+    *arg_val = tmp;
+    return SW_OK;
+}
+#ifdef IN_ACL
+sw_error_t
+cmd_data_check_ruletype(char *cmd_str, fal_acl_rule_type_t * arg_val,
+                        a_uint32_t size)
+{
+    if (NULL == cmd_str)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (!strcasecmp(cmd_str, "mac"))
+    {
+        *arg_val = FAL_ACL_RULE_MAC;
+    }
+    else if (!strcasecmp(cmd_str, "ip4"))
+    {
+        *arg_val = FAL_ACL_RULE_IP4;
+    }
+    else if (!strcasecmp(cmd_str, "ip6"))
+    {
+        *arg_val = FAL_ACL_RULE_IP6;
+    }
+    else if (!strcasecmp(cmd_str, "udf"))
+    {
+        *arg_val = FAL_ACL_RULE_UDF;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_udf_pkt_type(char *cmdstr, fal_acl_udf_pkt_type_t * arg_val, a_uint32_t size)
+{
+    if (NULL == cmdstr)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (!strcasecmp(cmdstr, "non-ip"))
+    {
+        *arg_val = FAL_ACL_UDF_NON_IP;
+    }
+    else if (!strcasecmp(cmdstr, "ipv4"))
+    {
+        *arg_val = FAL_ACL_UDF_IP4;
+    }
+    else if (!strcasecmp(cmdstr, "ipv6"))
+    {
+        *arg_val = FAL_ACL_UDF_IP6;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_udf_type(char *cmdstr, fal_acl_udf_type_t * arg_val, a_uint32_t size)
+{
+    if (NULL == cmdstr)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (!strcasecmp(cmdstr, "l2"))
+    {
+        *arg_val = FAL_ACL_UDF_TYPE_L2;
+    }
+    else if (!strcasecmp(cmdstr, "l2snap"))
+    {
+        *arg_val = FAL_ACL_UDF_TYPE_L2_SNAP;
+    }
+    else if (!strcasecmp(cmdstr, "l3"))
+    {
+        *arg_val = FAL_ACL_UDF_TYPE_L3;
+    }
+    else if (!strcasecmp(cmdstr, "l3plus"))
+    {
+        *arg_val = FAL_ACL_UDF_TYPE_L3_PLUS;
+    }
+    else if (!strcasecmp(cmdstr, "l4"))
+    {
+        *arg_val = FAL_ACL_UDF_TYPE_L4;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_udf_element(char *cmdstr, a_uint8_t * val, a_uint32_t * len)
+{
+    char *tmp = NULL;
+    a_uint32_t i = 0, j;
+    a_uint32_t data;
+
+    memset(val, 0, 16);
+    if (NULL == cmdstr)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (0 == cmdstr[0])
+    {
+        return SW_BAD_VALUE;
+    }
+
+    tmp = (void *) strsep(&cmdstr, "-");
+    while (tmp)
+    {
+        if (16 <= i)
+        {
+            return SW_BAD_VALUE;
+        }
+
+        if ((2 < strlen(tmp)) || (0 == strlen(tmp)))
+        {
+            return SW_BAD_VALUE;
+        }
+
+        for (j = 0; j < strlen(tmp); j++)
+        {
+            if (A_FALSE == is_hex(tmp[j]))
+            {
+                return SW_BAD_VALUE;
+            }
+        }
+
+        sscanf(tmp, "%x", &data);
+
+        val[i++] = data & 0xff;
+        tmp = (void *) strsep(&cmdstr, "-");
+    }
+
+    if (0 == i)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    *len = i;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_fieldop(char *cmdstr, fal_acl_field_op_t def,
+                       fal_acl_field_op_t * val)
+{
+    if ('\0' == cmdstr[0])
+    {
+        *val = def;
+    }
+    else if ((!strcasecmp(cmdstr, "mask")) || (!strcasecmp(cmdstr, "m")))
+    {
+        *val = FAL_ACL_FIELD_MASK;
+    }
+    else if ((!strcasecmp(cmdstr, "range")) || (!strcasecmp(cmdstr, "r")))
+    {
+        *val = FAL_ACL_FIELD_RANGE;
+    }
+    else if ((!strcasecmp(cmdstr, "le")) || (!strcasecmp(cmdstr, "l")))
+    {
+        *val = FAL_ACL_FIELD_LE;
+    }
+    else if ((!strcasecmp(cmdstr, "ge")) || (!strcasecmp(cmdstr, "g")))
+    {
+        *val = FAL_ACL_FIELD_GE;
+    }
+    else if ((!strcasecmp(cmdstr, "ne")) || (!strcasecmp(cmdstr, "n")))
+    {
+        *val = FAL_ACL_FIELD_NE;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+
+#endif
+sw_error_t
+cmd_data_check_ip4addr(char *cmdstr, void * val, a_uint32_t size)
+{
+    char *tmp = NULL;
+    a_uint32_t i = 0, j;
+    a_uint32_t addr;
+    fal_ip4_addr_t ip4;
+    char cmd[128] = { 0 };
+	char *str;
+
+    memset(&ip4, 0, sizeof (fal_ip4_addr_t));
+    if (NULL == cmdstr)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (0 == cmdstr[0])
+    {
+        return SW_BAD_VALUE;
+    }
+
+    for (i = 0; i < 128; i++)
+    {
+        if (0 == cmdstr[i])
+        {
+            break;
+        }
+    }
+
+    i++;
+    if (128 < i)
+    {
+        i = 128;
+    }
+
+    memcpy(cmd, cmdstr, i);
+	str = cmd;
+    tmp = (void *) strsep(&str, ".");
+    i = 0;
+    while (tmp)
+    {
+        if (4 <= i)
+        {
+            return SW_BAD_VALUE;
+        }
+
+        if ((3 < strlen(tmp)) || (0 == strlen(tmp)))
+        {
+            return SW_BAD_VALUE;
+        }
+
+        for (j = 0; j < strlen(tmp); j++)
+        {
+            if (A_FALSE == is_dec(tmp[j]))
+            {
+                return SW_BAD_VALUE;
+            }
+        }
+
+        sscanf(tmp, "%d", &addr);
+        if (255 < addr)
+        {
+            return SW_BAD_VALUE;
+        }
+
+        ip4 |= ((addr & 0xff) << (24 - i * 8));
+        i++;
+        tmp = (void *) strsep(&str, ".");
+    }
+
+    if (4 != i)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    *(fal_ip4_addr_t*)val = ip4;
+    return SW_OK;
+}
+
+#ifdef IN_IGMP
+sw_error_t
+cmd_data_check_multi(char *info, void *val, a_uint32_t size)
+{
+    sw_error_t rv;
+    fal_igmp_sg_entry_t entry;
+
+    memset(&entry, 0, sizeof (fal_igmp_sg_entry_t));
+
+    rv = __cmd_data_check_complex("group type", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.group.type),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    if(entry.group.type == 0)
+    {
+        rv = __cmd_data_check_complex("group ip4 addr", "0.0.0.0",
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip4addr, &(entry.group.u.ip4_addr),
+                            4);
+        if (rv)
+            return rv;
+    }
+    else
+    {
+        rv = __cmd_data_check_complex("group ip6 addr", NULL,
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip6addr, &(entry.group.u.ip6_addr),
+                            16);
+        if (rv)
+            return rv;
+
+    }
+
+    rv = __cmd_data_check_complex("source type", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.source.type),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    if(entry.source.type == 0)
+    {
+        rv = __cmd_data_check_complex("source ip4 addr", "0.0.0.0",
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip4addr, &(entry.source.u.ip4_addr),
+                            4);
+        if (rv)
+            return rv;
+    }
+    else
+    {
+        rv = __cmd_data_check_complex("source ip6 addr", NULL,
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip6addr, &(entry.source.u.ip6_addr),
+                            16);
+        if (rv)
+            return rv;
+    }
+
+    rv = __cmd_data_check_complex("portmap", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.port_map),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("vlanid", "0xffff",
+                        "usage: the range is 0 -- 4095 or 65535\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.vlan_id),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    *(fal_igmp_sg_entry_t *)val = entry;
+
+    return SW_OK;
+}
+#endif
+
+sw_error_t
+cmd_data_check_ip6addr(char *cmdstr, void * val, a_uint32_t size)
+{
+    char *tmp = NULL;
+    a_uint32_t j;
+    a_uint32_t i = 0, cnt = 0, rep = 0, loc = 0;
+    a_uint32_t data;
+    a_uint32_t addr[8];
+    fal_ip6_addr_t ip6;
+
+    if (NULL == cmdstr)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (0 == cmdstr[0])
+    {
+        return SW_BAD_VALUE;
+    }
+
+    for (i = 0; i < 8; i++)
+    {
+        addr[i] = 0;
+    }
+
+    for (i = 0; i < strlen(cmdstr); i++)
+    {
+        if (':' == cmdstr[i])
+        {
+            if ((i == (strlen(cmdstr) - 1))
+                    || (0 == i))
+            {
+                return SW_BAD_VALUE;
+            }
+            cnt++;
+
+            if (':' == cmdstr[i - 1])
+            {
+                rep++;
+                loc = cnt - 1;
+            }
+        }
+    }
+
+    if (1 < rep)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    tmp = (void *) strsep(&cmdstr, ":");
+    i = 0;
+    while (tmp)
+    {
+        if (8 <= i)
+        {
+            return SW_BAD_VALUE;
+        }
+
+        if (!strcmp(tmp, "")) {
+                tmp = (void *)strsep(&cmdstr, ":");
+                continue;
+        }
+
+        if ((4 < strlen(tmp)) || (0 == strlen(tmp)))
+        {
+            return SW_BAD_VALUE;
+        }
+
+        for (j = 0; j < strlen(tmp); j++)
+        {
+            if (A_FALSE == is_hex(tmp[j]))
+            {
+                return SW_BAD_VALUE;
+            }
+        }
+
+        sscanf(tmp, "%x", &data);
+        if (65535 < data)
+        {
+            return SW_BAD_VALUE;
+        }
+
+        addr[i++] = data;
+        tmp = (void *) strsep(&cmdstr, ":");
+    }
+
+    if (0 == rep)
+    {
+        if (8 != i)
+        {
+            return SW_BAD_VALUE;
+        }
+    }
+    else
+    {
+        if (8 <= i)
+        {
+            return SW_BAD_VALUE;
+        }
+
+        for (j = i - 1; j >= loc; j--)
+        {
+            addr[8 - i + j] = addr[j];
+            addr[j] = 0;
+        }
+    }
+
+    for (i = 0; i < 4; i++)
+    {
+        ip6.ul[i] = (addr[i * 2] << 16) | addr[i * 2 + 1];
+    }
+
+    *(fal_ip6_addr_t*)val = ip6;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_patternmode(char *cmd_str, led_pattern_mode_t * arg_val,
+                           a_uint32_t size)
+{
+    if (NULL == cmd_str)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (!strcasecmp(cmd_str, "always_off"))
+    {
+        *arg_val = LED_ALWAYS_OFF;
+    }
+    else if (!strcasecmp(cmd_str, "always_blink"))
+    {
+        *arg_val = LED_ALWAYS_BLINK;
+    }
+    else if (!strcasecmp(cmd_str, "always_on"))
+    {
+        *arg_val = LED_ALWAYS_ON;
+    }
+    else  if (!strcasecmp(cmd_str, "map"))
+    {
+        *arg_val = LED_PATTERN_MAP_EN;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#ifdef IN_LED
+sw_error_t
+cmd_data_check_blinkfreq(char *cmd_str, led_blink_freq_t * arg_val,
+                         a_uint32_t size)
+{
+    if (NULL == cmd_str)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (!strcasecmp(cmd_str, "2HZ"))
+    {
+        *arg_val = LED_BLINK_2HZ;
+    }
+    else if (!strcasecmp(cmd_str, "4HZ"))
+    {
+        *arg_val = LED_BLINK_4HZ;
+    }
+    else if (!strcasecmp(cmd_str, "8HZ"))
+    {
+        *arg_val = LED_BLINK_8HZ;
+    }
+    else if (!strcasecmp(cmd_str, "TXRX"))
+    {
+        *arg_val = LED_BLINK_TXRX;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ledpattern(char *info, void * val, a_uint32_t size)
+{
+    led_ctrl_pattern_t pattern;
+    a_uint32_t tmpdata;
+    sw_error_t rv;
+
+    memset(&pattern, 0, sizeof (led_ctrl_pattern_t));
+
+    /* get pattern mode configuration */
+    rv = __cmd_data_check_complex("pattern_mode", NULL,
+                        "usage: <always_off/always_blink/always_on/map>\n",
+                        (param_check_t)cmd_data_check_patternmode, &pattern.mode,
+                        sizeof (led_pattern_mode_t));
+    if (rv)
+        return rv;
+
+    if (LED_PATTERN_MAP_EN == pattern.mode)
+    {
+        rv = __cmd_data_check_boolean("full_duplex_light", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &tmpdata,
+                        sizeof (a_bool_t));
+        if (rv)
+            return rv;
+
+        if (1 == tmpdata)
+        {
+            pattern.map |= (1 << FULL_DUPLEX_LIGHT_EN);
+        }
+
+        rv = __cmd_data_check_boolean("half_duplex_light", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &tmpdata,
+                        sizeof (a_bool_t));
+        if (rv)
+            return rv;
+
+        if (1 == tmpdata)
+        {
+            pattern.map |= (1 << HALF_DUPLEX_LIGHT_EN);
+        }
+
+        rv = __cmd_data_check_boolean("power_on_light", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &tmpdata,
+                        sizeof (a_bool_t));
+        if (rv)
+            return rv;
+
+        if (1 == tmpdata)
+        {
+            pattern.map |= (1 << POWER_ON_LIGHT_EN);
+        }
+
+        rv = __cmd_data_check_boolean("link_1000m_light", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &tmpdata,
+                        sizeof (a_bool_t));
+        if (rv)
+            return rv;
+
+        if (1 == tmpdata)
+        {
+            pattern.map |= (1 << LINK_1000M_LIGHT_EN);
+        }
+
+        rv = __cmd_data_check_boolean("link_100m_light", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &tmpdata,
+                        sizeof (a_bool_t));
+        if (rv)
+            return rv;
+
+        if (1 == tmpdata)
+        {
+            pattern.map |= (1 << LINK_100M_LIGHT_EN);
+        }
+
+        rv = __cmd_data_check_boolean("link_10m_light", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &tmpdata,
+                        sizeof (a_bool_t));
+        if (rv)
+            return rv;
+
+        if (1 == tmpdata)
+        {
+            pattern.map |= (1 << LINK_10M_LIGHT_EN);
+        }
+
+        rv = __cmd_data_check_boolean("conllision_light", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &tmpdata,
+                        sizeof (a_bool_t));
+        if (rv)
+            return rv;
+
+        if (1 == tmpdata)
+        {
+            pattern.map |= (1 << COLLISION_BLINK_EN);
+        }
+
+        rv = __cmd_data_check_boolean("rx_traffic_blink", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &tmpdata,
+                        sizeof (a_bool_t));
+        if (rv)
+            return rv;
+
+        if (1 == tmpdata)
+        {
+            pattern.map |= (1 << RX_TRAFFIC_BLINK_EN);
+        }
+
+        rv = __cmd_data_check_boolean("tx_traffic_blink", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &tmpdata,
+                        sizeof (a_bool_t));
+        if (rv)
+            return rv;
+
+        if (1 == tmpdata)
+        {
+            pattern.map |= (1 << TX_TRAFFIC_BLINK_EN);
+        }
+
+        rv = __cmd_data_check_boolean("linkup_override_light", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &tmpdata,
+                        sizeof (a_bool_t));
+        if (rv)
+            return rv;
+
+        if (1 == tmpdata)
+        {
+            pattern.map |= (1 << LINKUP_OVERRIDE_EN);
+        }
+
+        rv = __cmd_data_check_complex("blink freq", NULL,
+                        "usage: <2HZ/4HZ/8HZ/TXRX> \n",
+                        (param_check_t)cmd_data_check_blinkfreq, &pattern.freq,
+                        sizeof (led_blink_freq_t));
+        if (rv)
+            return rv;
+    }
+
+    *(led_ctrl_pattern_t *)val = pattern;
+
+    return SW_OK;
+}
+#endif
+
+/*Shiva*/
+#ifdef IN_PORTVLAN
+sw_error_t
+cmd_data_check_invlan_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "admit_all"))
+    {
+        *arg_val = FAL_INVLAN_ADMIT_ALL;
+    }
+    else if (!strcasecmp(cmd_str, "admit_tagged"))
+    {
+        *arg_val = FAL_INVLAN_ADMIT_TAGGED;
+    }
+    else if (!strcasecmp(cmd_str, "admit_untagged"))
+    {
+        *arg_val = FAL_INVLAN_ADMIT_UNTAGGED;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#ifdef HPPE
+sw_error_t
+cmd_data_check_global_qinqmode(char *info, void *val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_global_qinq_mode_t *pEntry = (fal_global_qinq_mode_t *)val;
+
+    memset(pEntry, 0, sizeof(fal_global_qinq_mode_t));
+
+    /* get mask */
+    do
+    {
+        cmd = get_sub_cmd("mask", "0x0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(pEntry->mask), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get ingress mode */
+    do
+    {
+        cmd = get_sub_cmd("ingress_qinq_mode", "ctag");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_qinq_mode(cmd, &(pEntry->ingress_mode), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get egress mode */
+    do
+    {
+        cmd = get_sub_cmd("egress_qinq_mode", "ctag");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_qinq_mode(cmd, &(pEntry->egress_mode), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_port_qinqmode(char *info, void *val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_port_qinq_role_t *pEntry = (fal_port_qinq_role_t *)val;
+
+    memset(pEntry, 0, sizeof(fal_port_qinq_role_t));
+
+    /* get mask */
+    do
+    {
+        cmd = get_sub_cmd("mask", "0x0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(pEntry->mask), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get ingress mode */
+    do
+    {
+        cmd = get_sub_cmd("ingress_qinq_role", "edge");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_qinq_role(cmd, &(pEntry->ingress_port_role), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get egress mode */
+    do
+    {
+        cmd = get_sub_cmd("egress_qinq_role", "edge");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_qinq_role(cmd, &(pEntry->egress_port_role), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_tpid(char *info, void *val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_tpid_t *pEntry = (fal_tpid_t *)val;
+    a_uint32_t tmp = 0;
+
+    memset(pEntry, 0, sizeof(fal_tpid_t));
+
+    /* get mask */
+    do
+    {
+        cmd = get_sub_cmd("mask", "0x0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(pEntry->mask), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get ctpid */
+    do
+    {
+        cmd = get_sub_cmd("ctagtpid", "0x8100");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &tmp, sizeof(a_uint32_t));
+
+	     pEntry->ctpid = (a_uint16_t)tmp;
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get stpid */
+    do
+    {
+        cmd = get_sub_cmd("stagtpid", "0x88a8");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &tmp, sizeof(a_uint32_t));
+
+	     pEntry->stpid = (a_uint16_t)tmp;
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ingress_filter(char *info, void *val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_ingress_vlan_filter_t *pEntry = (fal_ingress_vlan_filter_t *)val;
+
+    memset(pEntry, 0, sizeof(fal_ingress_vlan_filter_t));
+
+    /* get in vlan filter */
+    do
+    {
+        cmd = get_sub_cmd("membership_filter_en", "disable");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_enable(cmd, &(pEntry->membership_filter), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get tag filter */
+    do
+    {
+        cmd = get_sub_cmd("tagged_filter_en", "disable");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_enable(cmd, &(pEntry->tagged_filter), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get untag filter */
+    do
+    {
+        cmd = get_sub_cmd("untagged_filter_en", "disable");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_enable(cmd, &(pEntry->untagged_filter), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get priority tag filter */
+    do
+    {
+        cmd = get_sub_cmd("priority_tagged_filter_en", "disable");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_enable(cmd, &(pEntry->priority_filter), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_port_vlan_direction(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "all"))
+    {
+        *arg_val = FAL_PORT_VLAN_ALL;
+    }
+    else if (!strcasecmp(cmd_str, "ingress"))
+    {
+        *arg_val = FAL_PORT_VLAN_INGRESS;
+    }
+    else if (!strcasecmp(cmd_str, "egress"))
+    {
+        *arg_val = FAL_PORT_VLAN_EGRESS;
+    }
+    else
+    {
+        //dprintf("input error \n");
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_port_default_vid_en(char *info, void *val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_port_default_vid_enable_t *pEntry = (fal_port_default_vid_enable_t *)val;
+
+    memset(pEntry, 0, sizeof(fal_port_default_vid_enable_t));
+
+    do
+    {
+        cmd = get_sub_cmd("default_ctag_vid_en", "disable");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_enable(cmd, &(pEntry->default_cvid_en), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("default_stag_vid_en", "disable");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_enable(cmd, &(pEntry->default_svid_en), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_port_vlan_tag(char *info, void *val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_port_vlan_tag_t *pEntry = (fal_port_vlan_tag_t *)val;
+    a_uint32_t tmp = 0;
+
+    memset(pEntry, 0, sizeof(fal_port_vlan_tag_t));
+
+    /* get mask */
+    do
+    {
+        cmd = get_sub_cmd("mask", "0x0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(pEntry->mask), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get cvid */
+    do
+    {
+        cmd = get_sub_cmd("default_ctag_vid", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &tmp, sizeof(a_uint32_t));
+
+	     pEntry->cvid = (a_uint16_t)tmp;
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get svid */
+    do
+    {
+        cmd = get_sub_cmd("default_stag_vid", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &tmp, sizeof(a_uint32_t));
+
+	     pEntry->svid = (a_uint16_t)tmp;
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get cpri */
+    do
+    {
+        cmd = get_sub_cmd("default_ctag_pri", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &tmp, sizeof(a_uint32_t));
+
+	     pEntry->cpri = (a_uint16_t)tmp;
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get spri */
+    do
+    {
+        cmd = get_sub_cmd("default_stag_pri", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &tmp, sizeof(a_uint32_t));
+
+	     pEntry->spri = (a_uint16_t)tmp;
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get cdei */
+    do
+    {
+        cmd = get_sub_cmd("default_ctag_dei", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &tmp, sizeof(a_uint32_t));
+
+	     pEntry->cdei = (a_uint16_t)tmp;
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get sdei */
+    do
+    {
+        cmd = get_sub_cmd("default_stag_dei", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &tmp, sizeof(a_uint32_t));
+
+	     pEntry->sdei = (a_uint16_t)tmp;
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_tag_propagation(char *info, void *val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_vlantag_propagation_t *pEntry = (fal_vlantag_propagation_t *)val;
+
+    memset(pEntry, 0, sizeof(fal_vlantag_propagation_t));
+
+    /* get mask */
+    do
+    {
+        cmd = get_sub_cmd("mask", "0x0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(pEntry->mask), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get vid propagation */
+    do
+    {
+        cmd = get_sub_cmd("vid_propagation_en", "disable");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_vlan_propagation(cmd, (a_uint32_t *) & (pEntry->vid_propagation), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get pri propagation */
+    do
+    {
+        cmd = get_sub_cmd("pri_propagation_en", "disable");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_vlan_propagation(cmd, (a_uint32_t *) & (pEntry->pri_propagation), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get dei propagation */
+    do
+    {
+        cmd = get_sub_cmd("dei_propagation_en", "disable");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_vlan_propagation(cmd, (a_uint32_t *) & (pEntry->dei_propagation), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_egress_mode(char *info, void *val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_vlantag_egress_mode_t *pEntry = (fal_vlantag_egress_mode_t *)val;
+
+    memset(pEntry, 0, sizeof(fal_vlantag_egress_mode_t));
+
+    /* get mask */
+    do
+    {
+        cmd = get_sub_cmd("mask", "0x0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(pEntry->mask), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get ctag mode */
+    do
+    {
+        cmd = get_sub_cmd("ctag_egress_vlan_mode", "unmodified");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_egmode(cmd, (a_uint32_t *) & (pEntry->ctag_mode), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get stag mode */
+    do
+    {
+        cmd = get_sub_cmd("stag_egress_vlan_mode", "unmodified");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_egmode(cmd, (a_uint32_t *) & (pEntry->stag_mode), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_port_vlan_translation_adv_rule(char *info, void *val, a_uint32_t size)
+{
+	char *cmd = NULL;
+	sw_error_t rv;
+	fal_vlan_trans_adv_rule_t *pEntry = (fal_vlan_trans_adv_rule_t *)val;
+
+	memset(pEntry, 0, sizeof(fal_vlan_trans_adv_rule_t));
+
+	do
+	{
+		cmd = get_sub_cmd("stagformat", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(pEntry->s_tagged), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("svid_en", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &(pEntry->s_vid_enable),
+					sizeof (a_bool_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("svid", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &(pEntry->s_vid), sizeof (a_uint32_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("spcp_en", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &(pEntry->s_pcp_enable),
+					sizeof (a_bool_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("spcp", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(pEntry->s_pcp), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("sdei_en", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &(pEntry->s_dei_enable),
+					sizeof (a_bool_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("sdei", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(pEntry->s_dei), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("ctagformat", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(pEntry->c_tagged), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("cvid_en", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &(pEntry->c_vid_enable),
+					sizeof (a_bool_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("cvid", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &(pEntry->c_vid), sizeof (a_uint32_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("cpcp_en", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &(pEntry->c_pcp_enable),
+					sizeof (a_bool_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("cpcp", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(pEntry->c_pcp), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("cdei_en", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &(pEntry->c_dei_enable),
+					sizeof (a_bool_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("cdei", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(pEntry->c_dei), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("frame_type_en", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->frmtype_enable),
+					sizeof (a_bool_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("frametype", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &(pEntry->frmtype), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("protocol_en", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->protocol_enable),
+					sizeof (a_bool_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("protocol", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(pEntry->protocol), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("vsivalid", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->vsi_valid),
+					sizeof (a_bool_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("vsi_en", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->vsi_enable),
+					sizeof (a_bool_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("vsi", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &(pEntry->vsi), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_port_vlan_translation_adv_action(char *info, void *val, a_uint32_t size)
+{
+	char *cmd = NULL;
+	sw_error_t rv;
+	fal_vlan_trans_adv_action_t *pEntry = (fal_vlan_trans_adv_action_t *)val;
+
+	memset(pEntry, 0, sizeof(fal_vlan_trans_adv_action_t));
+
+	do
+	{
+		cmd = get_sub_cmd("swap_svid_cvid", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &(pEntry->swap_svid_cvid),
+					sizeof (a_bool_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("svid_translation_cmd", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &(pEntry->svid_xlt_cmd), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("svidtranslation", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(pEntry->svid_xlt), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("cvid_translation_cmd", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &(pEntry->cvid_xlt_cmd), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("cvidtranslation", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(pEntry->cvid_xlt), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("swap_spcp_cpcp", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &(pEntry->swap_spcp_cpcp),
+					sizeof (a_bool_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("spcp_translation_en", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &(pEntry->spcp_xlt_enable),
+					sizeof (a_bool_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("spcptranslation", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(pEntry->spcp_xlt), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("cpcp_translation_en", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &(pEntry->cpcp_xlt_enable),
+					sizeof (a_bool_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("cpcptranslation", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(pEntry->cpcp_xlt), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("swap_sdei_cdei", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &(pEntry->swap_sdei_cdei),
+					sizeof (a_bool_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("sdei_translation_en", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &(pEntry->sdei_xlt_enable),
+					sizeof (a_bool_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("sdeitranslation", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(pEntry->sdei_xlt), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("cdei_translation_en", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &(pEntry->cdei_xlt_enable),
+					sizeof (a_bool_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("cdeitranslation", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(pEntry->cdei_xlt), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("counter_en", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &(pEntry->counter_enable),
+					sizeof (a_bool_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("counter_id", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(pEntry->counter_id), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("vsi_translation_en", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &(pEntry->vsi_xlt_enable),
+					sizeof (a_bool_t));
+		}
+
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("vsitranslation", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd,
+					(a_uint32_t *)&(pEntry->vsi_xlt), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	return SW_OK;
+}
+#endif
+
+sw_error_t
+cmd_data_check_vlan_propagation(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "disable"))
+    {
+        *arg_val = FAL_VLAN_PROPAGATION_DISABLE;
+    }
+    else if (!strcasecmp(cmd_str, "clone"))
+    {
+        *arg_val = FAL_VLAN_PROPAGATION_CLONE;
+    }
+    else if (!strcasecmp(cmd_str, "replace"))
+    {
+        *arg_val = FAL_VLAN_PROPAGATION_REPLACE;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+#ifndef IN_PORTVLAN_MINI
+sw_error_t
+cmd_data_check_vlan_translation(char *info, fal_vlan_trans_entry_t *val, a_uint32_t size)
+{
+    sw_error_t rv;
+    fal_vlan_trans_entry_t entry;
+
+    memset(&entry, 0, sizeof (fal_vlan_trans_entry_t));
+
+    rv = __cmd_data_check_complex("ovid", "1",
+                        "usage: the range is 0 -- 4095\n",
+                        (param_check_t)cmd_data_check_uint32, &entry.o_vid,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("bi direction", "yes",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_TRUE, &entry.bi_dir,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("forward direction", "yes",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_TRUE, &entry.forward_dir,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("reverse direction", "yes",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_TRUE, &entry.reverse_dir,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("svid ", "1",
+                        "usage: the range is 0 -- 4095\n",
+                        (param_check_t)cmd_data_check_uint32, &entry.s_vid,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("cvid ", "1",
+                        "usage: the range is 0 -- 4095\n",
+                        (param_check_t)cmd_data_check_uint32, &entry.c_vid,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("ovid_is_cvid", "yes",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_TRUE, &entry.o_vid_is_cvid,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("svid_enable", "yes",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_TRUE, &entry.s_vid_enable,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("cvid_enable", "yes",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_TRUE, &entry.c_vid_enable,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("one_2_one_vlan", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.one_2_one_vlan,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    *val = entry;
+    return SW_OK;
+}
+#endif
+
+
+sw_error_t
+cmd_data_check_qinq_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "ctag"))
+    {
+        *arg_val = FAL_QINQ_CTAG_MODE;
+    }
+    else if (!strcasecmp(cmd_str, "stag"))
+    {
+        *arg_val = FAL_QINQ_STAG_MODE;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_qinq_role(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "edge"))
+    {
+        *arg_val = FAL_QINQ_EDGE_PORT;
+    }
+    else if (!strcasecmp(cmd_str, "core"))
+    {
+        *arg_val = FAL_QINQ_CORE_PORT;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#endif
+
+#ifdef IN_PORTCONTROL
+sw_error_t
+cmd_data_check_hdrmode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "noheader"))
+    {
+        *arg_val = FAL_NO_HEADER_EN;
+    }
+    else if (!strcasecmp(cmd_str, "onlymanagement"))
+    {
+        *arg_val = FAL_ONLY_MANAGE_FRAME_EN;
+    }
+    else if (!strcasecmp(cmd_str, "allframe"))
+    {
+        *arg_val = FAL_ALL_TYPE_FRAME_EN;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#endif
+#ifdef IN_FDB
+sw_error_t
+cmd_data_check_fdboperation(char *cmd_str, void * val, a_uint32_t size)
+{
+    sw_error_t rv;
+    fal_fdb_op_t entry;
+
+    memset(&entry, 0, sizeof (fal_fdb_op_t));
+
+    rv = __cmd_data_check_boolean("port_en", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.port_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("fid_en", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.fid_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("multi_en", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.multicast_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    *(fal_fdb_op_t *) val = entry;
+    return SW_OK;
+}
+#endif
+#ifdef IN_PPPOE
+sw_error_t
+cmd_data_check_pppoe(char *cmd_str, void * val, a_uint32_t size)
+{
+    sw_error_t rv;
+    fal_pppoe_session_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_pppoe_session_t));
+
+    rv = __cmd_data_check_complex("entryid", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.entry_id),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("sessionid", "0",
+                        "usage: the range is 0 -- 65535\n",
+                        (param_check_t)cmd_data_check_uint32, &entry.session_id,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("multi_session", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.multi_session,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("uni_session", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.uni_session,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("vrf_id", "0",
+                        "usage: the range is 0 -- 7\n",
+                        (param_check_t)cmd_data_check_uint32, &entry.vrf_id,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("port", "null",
+                        "usage: input port number such as 1,3\n",
+                        cmd_data_check_portmap, &entry.port_bitmap,
+                        sizeof (fal_pbmp_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("l3_interface_index", "0",
+                        "usage: the range is 0 -- 255\n",
+                        cmd_data_check_uint32, &entry.l3_if_index,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("l3_interface_index_valid", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.l3_if_valid,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("smac_addr", NULL,
+                        "usage: the format is xx-xx-xx-xx-xx-xx \n",
+                        (param_check_t)cmd_data_check_macaddr, &(entry.smac_addr),
+                        sizeof (fal_mac_addr_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("smac_valid", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.smac_valid,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    *(fal_pppoe_session_t*)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_pppoe_less(char *cmd_str, void * val, a_uint32_t size)
+{
+    sw_error_t rv;
+    fal_pppoe_session_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_pppoe_session_t));
+
+    rv = __cmd_data_check_complex("sessionid", "0",
+                        "usage: the range is 0 -- 65535\n",
+                        cmd_data_check_uint32, &entry.session_id,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    *(fal_pppoe_session_t*)val = entry;
+    return SW_OK;
+}
+#endif
+
+#if defined(IN_IP) || defined(IN_NAT)
+sw_error_t
+cmd_data_check_host_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+    sw_error_t rv;
+    fal_host_entry_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_host_entry_t));
+
+    rv = __cmd_data_check_complex("entryid", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.entry_id),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("entryflags", "0x1",
+                        "usage: bitmap for host entry\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.flags),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("entrystatus", "0",
+                        "usage: bitmap for host entry\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.status),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    if ((FAL_IP_IP4_ADDR & (entry.flags)) ==  FAL_IP_IP4_ADDR|| 
+		(FAL_IP_IP4_ADDR_MCAST & (entry.flags)) ==  FAL_IP_IP4_ADDR_MCAST)
+    {
+        rv = __cmd_data_check_complex("ip4 addr", NULL,
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip4addr, &(entry.ip4_addr),
+                            4);
+        if (rv)
+            return rv;
+    }
+    else if ((FAL_IP_IP6_ADDR & (entry.flags)) == FAL_IP_IP6_ADDR || 
+		(FAL_IP_IP6_ADDR_MCAST& (entry.flags)) == FAL_IP_IP6_ADDR_MCAST)
+    {
+        rv = __cmd_data_check_complex("ip6 addr", NULL,
+                            "usage: the format is xxxx::xxxx \n",
+                            (param_check_t)cmd_data_check_ip6addr, &(entry.ip6_addr),
+                            16);
+        if (rv)
+            return rv;
+    }
+
+    rv = __cmd_data_check_complex("mac addr", NULL,
+                        "usage: the format is xx-xx-xx-xx-xx-xx \n",
+                        (param_check_t)cmd_data_check_macaddr, &(entry.mac_addr),
+                        sizeof (fal_mac_addr_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("interface id", "0",
+                        "usage: the format is xx-xx-xx-xx-xx-xx \n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.intf_id),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("load_balance num", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.lb_num),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("vrf id", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.vrf_id),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("port id", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.port_id),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("action", "forward",
+                        "usage: <forward/drop/cpycpu/rdtcpu>\n",
+                        (param_check_t)cmd_data_check_maccmd, &(entry.action),
+                        sizeof (fal_fwd_cmd_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("mirror", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.mirror_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("counter", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.counter_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    if (A_TRUE == entry.counter_en)
+    {
+        rv = __cmd_data_check_complex("counter id", "0",
+                            "usage: integer\n",
+                            (param_check_t)cmd_data_check_uint32, &(entry.counter_id),
+                            sizeof (a_uint32_t));
+        if (rv)
+            return rv;
+    }
+
+    rv = __cmd_data_check_complex("dst info", "0",
+                        "usage: integer\n",
+                        cmd_data_check_uint32, &(entry.dst_info),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("sync_toggle", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint8, &(entry.syn_toggle),
+                        sizeof (a_uint8_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("lan_wan", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint8, &(entry.lan_wan),
+                        sizeof (a_uint8_t));
+    if (rv)
+        return rv;
+
+    if ((FAL_IP_IP4_ADDR_MCAST & (entry.flags)) == FAL_IP_IP4_ADDR_MCAST || 
+		(FAL_IP_IP6_ADDR_MCAST& (entry.flags)) == FAL_IP_IP6_ADDR_MCAST) {
+         rv = __cmd_data_check_complex("vsi", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint8, &(entry.mcast_info.vsi),
+                        sizeof (a_uint8_t));
+        if (rv)
+            return rv;
+        if ((FAL_IP_IP4_ADDR_MCAST & (entry.flags)) == FAL_IP_IP4_ADDR_MCAST) {
+		rv = __cmd_data_check_complex("ip4 addr", NULL,
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip4addr, &(entry.mcast_info.sip4_addr),
+                            4);
+            if (rv)
+                return rv;
+        } else {
+            rv = __cmd_data_check_complex("ip6 addr", NULL,
+                            "usage: the format is xxxx::xxxx \n",
+                            (param_check_t)cmd_data_check_ip6addr, &(entry.mcast_info.sip6_addr),
+                            16);
+            if (rv)
+                return rv;
+        }
+    }
+
+    
+
+    *(fal_host_entry_t *)val = entry;
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_arp_learn_mode(char *cmd_str, fal_arp_learn_mode_t * arg_val,
+                              a_uint32_t size)
+{
+    if (NULL == cmd_str)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (!strcasecmp(cmd_str, "learnlocal"))
+    {
+        *arg_val = FAL_ARP_LEARN_LOCAL;
+    }
+    else if (!strcasecmp(cmd_str, "learnall"))
+    {
+        *arg_val = FAL_ARP_LEARN_ALL;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_ip_guard_mode(char *cmd_str, fal_source_guard_mode_t * arg_val, a_uint32_t size)
+{
+    if (NULL == cmd_str)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (!strcasecmp(cmd_str, "mac_ip"))
+    {
+        *arg_val = FAL_MAC_IP_GUARD;
+    }
+    else if (!strcasecmp(cmd_str, "mac_ip_port"))
+    {
+        *arg_val = FAL_MAC_IP_PORT_GUARD;
+    }
+    else if (!strcasecmp(cmd_str, "mac_ip_vlan"))
+    {
+        *arg_val = FAL_MAC_IP_VLAN_GUARD;
+    }
+    else if (!strcasecmp(cmd_str, "mac_ip_port_vlan"))
+    {
+        *arg_val = FAL_MAC_IP_PORT_VLAN_GUARD;
+    }
+    else if (!strcasecmp(cmd_str, "no_guard"))
+    {
+        *arg_val = FAL_NO_SOURCE_GUARD;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+
+
+sw_error_t
+cmd_data_check_nat_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+    sw_error_t rv;
+    a_uint32_t tmp = 0;
+    fal_nat_entry_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_nat_entry_t));
+
+    rv = __cmd_data_check_complex("entryid", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.entry_id),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("entryflags", "0",
+                        "usage: bitmap for host entry\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.flags),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("entrystatus", "0xf",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.status),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("select_idx", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.slct_idx),
+                        sizeof (a_uint32_t));
+
+	if (rv)
+        return rv;
+
+	rv = __cmd_data_check_complex("vrf_id", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.vrf_id),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("src addr", "0.0.0.0",
+                        "usage: the format is xx.xx.xx.xx \n",
+                        (param_check_t)cmd_data_check_ip4addr, &(entry.src_addr),
+                        4);
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("trans addr", "0.0.0.0",
+                        "usage: the format is xx.xx.xx.xx \n",
+                        (param_check_t)cmd_data_check_ip4addr, &(entry.trans_addr),
+                        4);
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("port num", "0",
+                        "usage: 0- 65535\n",
+                        (param_check_t)cmd_data_check_uint16, &tmp, sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+    entry.port_num = tmp & 0xffff;
+
+
+    rv = __cmd_data_check_complex("port range", "0",
+                        "usage: 0- 65535\n",
+                        (param_check_t)cmd_data_check_uint16, &tmp, sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+    entry.port_range = tmp & 0xffff;
+
+    rv = __cmd_data_check_complex("action", "forward",
+                        "usage: <forward/drop/cpycpu/rdtcpu>\n",
+                        (param_check_t)cmd_data_check_maccmd, &entry.action,
+                        sizeof (fal_fwd_cmd_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("mirror", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.mirror_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("counter", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.counter_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    if (A_TRUE == entry.counter_en)
+    {
+        rv = __cmd_data_check_complex("counter id", "0",
+                            "usage: integer\n",
+                            (param_check_t)cmd_data_check_uint32, &(entry.counter_id),
+                            sizeof (a_uint32_t));
+        if (rv)
+            return rv;
+    }
+
+    *(fal_nat_entry_t *)val = entry;
+    return SW_OK;
+}
+
+
+
+sw_error_t
+cmd_data_check_napt_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+    sw_error_t rv;
+    a_uint32_t tmp = 0;
+    fal_napt_entry_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_napt_entry_t));
+
+    rv = __cmd_data_check_complex("entryid", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &entry.entry_id,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("entryflags", "0",
+                        "usage: bitmap for host entry\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.flags),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("entrystatus", "0xf",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.status),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("vrf_id", "0x0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.vrf_id),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("flow_cookie", "0x0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.flow_cookie),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("load_balance", "0x0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.load_balance),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("src addr", "0.0.0.0",
+                        "usage: the format is xx.xx.xx.xx \n",
+                        (param_check_t)cmd_data_check_ip4addr, &(entry.src_addr),
+                        4);
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("dst addr", "0.0.0.0",
+                        "usage: the format is xx.xx.xx.xx \n",
+                        (param_check_t)cmd_data_check_ip4addr, &(entry.dst_addr),
+                        4);
+    if (rv)
+        return rv;
+
+    if (FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & (entry.flags))
+    {
+        rv = __cmd_data_check_complex("trans addr index", "0",
+                            "usage: integer\n",
+                            (param_check_t)cmd_data_check_uint32, &(entry.trans_addr),
+                            sizeof (a_uint32_t));
+        if (rv)
+            return rv;
+    }
+    else
+    {
+        rv = __cmd_data_check_complex("trans addr", "0.0.0.0",
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip4addr, &(entry.trans_addr),
+                            4);
+        if (rv)
+            return rv;
+    }
+
+    rv = __cmd_data_check_complex("src port", "0",
+                        "usage: 0- 65535\n",
+                        (param_check_t)cmd_data_check_uint16, &tmp,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+    entry.src_port = tmp & 0xffff;
+
+    rv = __cmd_data_check_complex("dst port", "0",
+                        "usage: 0- 65535\n",
+                        (param_check_t)cmd_data_check_uint16, &tmp,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+    entry.dst_port = tmp & 0xffff;
+
+    rv = __cmd_data_check_complex("trans port", "0",
+                        "usage: 0- 65535\n",
+                        (param_check_t)cmd_data_check_uint16, &tmp,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+    entry.trans_port = tmp & 0xffff;
+
+    rv = __cmd_data_check_complex("action", "forward",
+                        "usage: <forward/drop/cpycpu/rdtcpu>\n",
+                        (param_check_t)cmd_data_check_maccmd, &(entry.action),
+                        sizeof (fal_fwd_cmd_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("mirror", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.mirror_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+
+    rv = __cmd_data_check_boolean("counter", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.counter_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+
+    if (A_TRUE == entry.counter_en)
+    {
+        rv = __cmd_data_check_complex("counter id", "0",
+                            "usage: integer\n",
+                            (param_check_t)cmd_data_check_uint32, &(entry.counter_id),
+                            sizeof (a_uint32_t));
+        if (rv)
+            return rv;
+    }
+
+	rv = __cmd_data_check_boolean("priority", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.priority_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    if (A_TRUE == entry.priority_en)
+    {
+        rv = __cmd_data_check_complex("priority value", "0",
+                            "usage: integer\n",
+                            (param_check_t)cmd_data_check_uint32, &(entry.priority_val),
+                            sizeof (a_uint32_t));
+        if (rv)
+            return rv;
+    }
+
+    *(fal_napt_entry_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_flow_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+    sw_error_t rv;
+    a_uint32_t tmp = 0;
+    fal_napt_entry_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_napt_entry_t));
+
+    rv = __cmd_data_check_complex("entryid", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &entry.entry_id,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("entryflags", "0",
+                        "usage: bitmap for host entry\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.flags),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("entrystatus", "0xf",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.status),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("vrf_id", "0x0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.vrf_id),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("flow_cookie", "0x0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.flow_cookie),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("load_balance", "0x0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.load_balance),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("src addr", "0.0.0.0",
+                        "usage: the format is xx.xx.xx.xx \n",
+                        (param_check_t)cmd_data_check_ip4addr, &(entry.src_addr),
+                        4);
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("dst addr", "0.0.0.0",
+                        "usage: the format is xx.xx.xx.xx \n",
+                        (param_check_t)cmd_data_check_ip4addr, &(entry.dst_addr),
+                        4);
+    if (rv)
+        return rv;
+
+
+    rv = __cmd_data_check_complex("src port", "0",
+                        "usage: 0- 65535\n",
+                        (param_check_t)cmd_data_check_uint16, &tmp,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+    entry.src_port = tmp & 0xffff;
+
+    rv = __cmd_data_check_complex("dst port", "0",
+                        "usage: 0- 65535\n",
+                        (param_check_t)cmd_data_check_uint16, &tmp,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+    entry.dst_port = tmp & 0xffff;
+
+
+    rv = __cmd_data_check_complex("action", "forward",
+                        "usage: <forward/drop/cpycpu/rdtcpu>\n",
+                        (param_check_t)cmd_data_check_maccmd, &(entry.action),
+                        sizeof (fal_fwd_cmd_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("mirror", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.mirror_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+
+    rv = __cmd_data_check_boolean("counter", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.counter_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+
+    if (A_TRUE == entry.counter_en)
+    {
+        rv = __cmd_data_check_complex("counter id", "0",
+                            "usage: integer\n",
+                            (param_check_t)cmd_data_check_uint32, &(entry.counter_id),
+                            sizeof (a_uint32_t));
+        if (rv)
+            return rv;
+    }
+
+	rv = __cmd_data_check_boolean("priority", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &entry.priority_en,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    if (A_TRUE == entry.priority_en)
+    {
+        rv = __cmd_data_check_complex("priority value", "0",
+                            "usage: integer\n",
+                            (param_check_t)cmd_data_check_uint32, &(entry.priority_val),
+                            sizeof (a_uint32_t));
+        if (rv)
+            return rv;
+    }
+
+    *(fal_napt_entry_t *)val = entry;
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_napt_mode(char *cmd_str, fal_napt_mode_t * arg_val,
+                         a_uint32_t size)
+{
+    if (NULL == cmd_str)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (!strcasecmp(cmd_str, "fullcone"))
+    {
+        *arg_val = FAL_NAPT_FULL_CONE;
+    }
+    else if (!strcasecmp(cmd_str, "strictcone"))
+    {
+        *arg_val = FAL_NAPT_STRICT_CONE;
+    }
+    else if (!strcasecmp(cmd_str, "portstrict"))
+    {
+        *arg_val = FAL_NAPT_PORT_STRICT;
+    }
+    else if (!strcasecmp(cmd_str, "synmatric"))
+    {
+        *arg_val = FAL_NAPT_SYNMETRIC;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_intf_mac_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+    a_uint32_t tmp = 0;
+    sw_error_t rv;
+    fal_intf_mac_entry_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_intf_mac_entry_t));
+
+    rv = __cmd_data_check_complex("entryid", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.entry_id),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("vrf id", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.vrf_id),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("vid low", NULL,
+                        "usage: low vlan id\n",
+                        (param_check_t)cmd_data_check_uint16, &tmp, sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+    entry.vid_low = tmp & 0xffff;
+
+    rv = __cmd_data_check_complex("vid high", NULL,
+                        "usage: high vlan id\n",
+                        (param_check_t)cmd_data_check_uint16, &tmp, sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+    entry.vid_high = tmp & 0xffff;
+
+    rv = __cmd_data_check_complex("mac addr", NULL,
+                        "usage: the format is xx-xx-xx-xx-xx-xx \n",
+                        (param_check_t)cmd_data_check_macaddr, &(entry.mac_addr),
+                        sizeof (fal_mac_addr_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("ip4_route", "yes",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_TRUE, &entry.ip4_route,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("ip6_route", "yes",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_TRUE, &entry.ip6_route,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    *(fal_intf_mac_entry_t *)val = entry;
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_pub_addr_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+    sw_error_t rv;
+    fal_nat_pub_addr_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_nat_pub_addr_t));
+
+    rv = __cmd_data_check_complex("entryid", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.entry_id),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("pub addr", NULL,
+                        "usage: the format is xx.xx.xx.xx \n",
+                        (param_check_t)cmd_data_check_ip4addr, &(entry.pub_addr),
+                        4);
+    if (rv)
+        return rv;
+
+    *(fal_nat_pub_addr_t *)val = entry;
+    return SW_OK;
+}
+#endif
+
+#ifdef IN_RATE
+sw_error_t
+cmd_data_check_egress_shaper(char *cmd_str, void * val, a_uint32_t size)
+{
+    sw_error_t rv;
+    a_bool_t bool = 0;
+    fal_egress_shaper_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_egress_shaper_t));
+
+    rv = __cmd_data_check_boolean("bytebased", "yes",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_TRUE, &bool,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    if (A_TRUE == bool)
+    {
+        entry.meter_unit = FAL_BYTE_BASED;
+    }
+    else
+    {
+        entry.meter_unit = FAL_FRAME_BASED;
+    }
+
+    rv = __cmd_data_check_complex("cir", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.cir),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("cbs", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.cbs),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("eir", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.eir),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("ebs", "0",
+                        "usage: integer\n",
+                        (param_check_t)cmd_data_check_uint32, &(entry.ebs),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    *(fal_egress_shaper_t *)val = entry;
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_acl_policer(char *cmd_str, void * val, a_uint32_t size)
+{
+    sw_error_t rv;
+    a_bool_t bool = A_FALSE;
+    fal_acl_policer_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_acl_policer_t));
+
+    rv = __cmd_data_check_boolean("counter_mode", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &(entry.counter_mode),
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("bytebased", "yes",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_TRUE, &bool,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    if (A_TRUE == bool)
+    {
+        entry.meter_unit = FAL_BYTE_BASED;
+    }
+    else
+    {
+        entry.meter_unit = FAL_FRAME_BASED;
+    }
+
+    if (A_TRUE == entry.counter_mode)
+    {
+        *(fal_acl_policer_t *)val = entry;
+        return SW_OK;
+    }
+
+    rv = __cmd_data_check_boolean("couple_flag", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &(entry.couple_flag),
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("color_aware", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &(entry.color_mode),
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("deficit_flag", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &(entry.deficit_en),
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("cir", "0",
+                        "usage: integer\n",
+                        cmd_data_check_uint32, &(entry.cir),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("cbs", "0",
+                        "usage: integer\n",
+                        cmd_data_check_uint32, &(entry.cbs),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("eir", "0",
+                        "usage: integer\n",
+                        cmd_data_check_uint32, &(entry.eir),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("ebs", "0",
+                        "usage: integer\n",
+                        cmd_data_check_uint32, &(entry.ebs),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("meter_interval", "1ms",
+                        "usage: the format <100us/1ms/10ms/100ms>\n",
+                        (param_check_t)cmd_data_check_policer_timesslot, &(entry.meter_interval),
+                        sizeof (fal_rate_mt_t));
+    if (rv)
+        return rv;
+
+    *(fal_acl_policer_t *)val = entry;
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_policer_timesslot(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strncasecmp(cmd_str, "100us", 5))
+        *arg_val = FAL_RATE_MI_100US;
+    else if (!strncasecmp(cmd_str, "1ms", 3))
+        *arg_val = FAL_RATE_MI_1MS;
+    else if (!strncasecmp(cmd_str, "10ms", 4))
+        *arg_val = FAL_RATE_MI_10MS;
+    else if (!strncasecmp(cmd_str, "100ms", 5))
+        *arg_val = FAL_RATE_MI_100MS;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_port_policer(char *cmd_str, void * val, a_uint32_t size)
+{
+    sw_error_t rv;
+    a_bool_t bool = 0;
+    fal_port_policer_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_port_policer_t));
+
+    rv = __cmd_data_check_boolean("combine_enable", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &(entry.combine_mode),
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("bytebased", "yes",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_TRUE, &bool,
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    if (A_TRUE == bool)
+    {
+        entry.meter_unit = FAL_BYTE_BASED;
+    }
+    else
+    {
+        entry.meter_unit = FAL_FRAME_BASED;
+    }
+
+    rv = __cmd_data_check_boolean("couple_flag", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &(entry.couple_flag),
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("color_aware", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &(entry.color_mode),
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("deficit_flag", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &(entry.deficit_en),
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("c_enable", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &(entry.c_enable),
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("cir", "0",
+                        "usage: integer\n",
+                        cmd_data_check_uint32, &(entry.cir),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("cbs", "0",
+                        "usage: integer\n",
+                        cmd_data_check_uint32, &(entry.cbs),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("c_rate_flag", "0xfe",
+                        "usage: integer\n",
+                        cmd_data_check_uint32, &(entry.c_rate_flag),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("c_meter_interval", "1ms",
+                        "usage: the format <100us/1ms/10ms/100ms>\n",
+                        (param_check_t)cmd_data_check_policer_timesslot, &(entry.c_meter_interval),
+                        sizeof (fal_rate_mt_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_boolean("e_enable", "no",
+                        "usage: <yes/no/y/n>\n",
+                        cmd_data_check_confirm, A_FALSE, &(entry.e_enable),
+                        sizeof (a_bool_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("eir", "0",
+                        "usage: integer\n",
+                        cmd_data_check_uint32, &(entry.eir),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("ebs", "0",
+                        "usage: integer\n",
+                        cmd_data_check_uint32, &(entry.ebs),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("e_rate_flag", "0xfe",
+                        "usage: integer\n",
+                        cmd_data_check_uint32, &(entry.e_rate_flag),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("e_meter_interval", "1ms",
+                        "usage: the format <100us/1ms/10ms/100ms>\n",
+                        (param_check_t)cmd_data_check_policer_timesslot, &(entry.e_meter_interval),
+                        sizeof (fal_rate_mt_t));
+    if (rv)
+        return rv;
+
+    *(fal_port_policer_t *)val = entry;
+    return SW_OK;
+}
+#endif
+#if 0
+sw_error_t
+cmd_data_check_mac_mode(char *cmd_str, fal_interface_mac_mode_t * arg_val,
+                        a_uint32_t size)
+{
+    if (NULL == cmd_str)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (0 == cmd_str[0])
+    {
+        *arg_val = FAL_MAC_MODE_RGMII;
+    }
+    else if (!strcasecmp(cmd_str, "rgmii"))
+    {
+        *arg_val = FAL_MAC_MODE_RGMII;
+    }
+    else if (!strcasecmp(cmd_str, "rmii"))
+    {
+        *arg_val = FAL_MAC_MODE_RMII;
+    }
+    else if (!strcasecmp(cmd_str, "gmii"))
+    {
+        *arg_val = FAL_MAC_MODE_GMII;
+    }
+    else if (!strcasecmp(cmd_str, "mii"))
+    {
+        *arg_val = FAL_MAC_MODE_MII;
+    }
+    else if (!strcasecmp(cmd_str, "sgmii"))
+    {
+        *arg_val = FAL_MAC_MODE_SGMII;
+    }
+    else if (!strcasecmp(cmd_str, "fiber"))
+    {
+        *arg_val = FAL_MAC_MODE_FIBER;
+    }
+    else if (!strcasecmp(cmd_str, "default"))
+    {
+        *arg_val = FAL_MAC_MODE_DEFAULT;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_clock_mode(char *cmd_str, fal_interface_clock_mode_t * arg_val,
+                          a_uint32_t size)
+{
+    if (NULL == cmd_str)
+    {
+        return SW_BAD_VALUE;
+    }
+
+    if (0 == cmd_str[0])
+    {
+        *arg_val = FAL_INTERFACE_CLOCK_MAC_MODE;
+    }
+    if (!strcasecmp(cmd_str, "mac"))
+    {
+        *arg_val = FAL_INTERFACE_CLOCK_MAC_MODE;
+    }
+    else if (!strcasecmp(cmd_str, "phy"))
+    {
+        *arg_val = FAL_INTERFACE_CLOCK_PHY_MODE;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#endif
+#ifdef IN_FDB
+#ifndef IN_FDB_MINI
+sw_error_t
+cmd_data_check_fdb_smode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "ivl"))
+        *arg_val = INVALID_VLAN_IVL;
+    else if (!strcasecmp(cmd_str, "svl"))
+        *arg_val = INVALID_VLAN_SVL;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#endif
+#endif
+#ifdef IN_SEC
+sw_error_t
+cmd_data_check_sec_mac(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "resv_vid"))
+        *arg_val = FAL_NORM_MAC_RESV_VID_CMD;
+    else if (!strcasecmp(cmd_str, "invalid_src_addr"))
+        *arg_val = FAL_NORM_MAC_INVALID_SRC_ADDR_CMD;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_sec_ip(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "invalid_ver"))
+        *arg_val = FAL_NORM_IP_INVALID_VER_CMD;
+    else if (!strcasecmp(cmd_str, "same_addr"))
+        *arg_val = FAL_NROM_IP_SAME_ADDR_CMD;
+    else if (!strcasecmp(cmd_str, "ttl_change_status"))
+        *arg_val = FAL_NROM_IP_TTL_CHANGE_STATUS;
+    else if (!strcasecmp(cmd_str, "ttl_val"))
+        *arg_val = FAL_NROM_IP_TTL_VALUE;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_sec_ip4(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "invalid_hl"))
+        *arg_val = FAL_NROM_IP4_INVALID_HL_CMD;
+    else if (!strcasecmp(cmd_str, "hdr_opts"))
+        *arg_val = FAL_NROM_IP4_HDR_OPTIONS_CMD;
+    else if (!strcasecmp(cmd_str, "invalid_df"))
+        *arg_val = FAL_NROM_IP4_INVALID_DF_CMD;
+    else if (!strcasecmp(cmd_str, "frag_offset_min_len"))
+        *arg_val = FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD;
+    else if (!strcasecmp(cmd_str, "frag_offset_min_size"))
+        *arg_val = FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE;
+    else if (!strcasecmp(cmd_str, "frag_offset_max_len"))
+        *arg_val = FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD;
+    else if (!strcasecmp(cmd_str, "invalid_frag_offset"))
+        *arg_val = FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD;
+    else if (!strcasecmp(cmd_str, "invalid_sip"))
+        *arg_val = FAL_NROM_IP4_INVALID_SIP_CMD;
+    else if (!strcasecmp(cmd_str, "invalid_dip"))
+        *arg_val = FAL_NROM_IP4_INVALID_DIP_CMD;
+    else if (!strcasecmp(cmd_str, "invalid_chksum"))
+        *arg_val = FAL_NROM_IP4_INVALID_CHKSUM_CMD;
+    else if (!strcasecmp(cmd_str, "invalid_pl"))
+        *arg_val = FAL_NROM_IP4_INVALID_PL_CMD;
+    else if (!strcasecmp(cmd_str, "df_clear_status"))
+        *arg_val = FAL_NROM_IP4_DF_CLEAR_STATUS;
+    else if (!strcasecmp(cmd_str, "ipid_random_status"))
+        *arg_val = FAL_NROM_IP4_IPID_RANDOM_STATUS;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_sec_ip6(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "invalid_dip"))
+        *arg_val = FAL_NROM_IP6_INVALID_DIP_CMD;
+    else if (!strcasecmp(cmd_str, "invalid_sip"))
+        *arg_val = FAL_NROM_IP6_INVALID_SIP_CMD;
+    else if (!strcasecmp(cmd_str, "invalid_pl"))
+        *arg_val = FAL_NROM_IP6_INVALID_PL_CMD;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_sec_tcp(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "blat"))
+        *arg_val = FAL_NROM_TCP_BLAT_CMD;
+    else if (!strcasecmp(cmd_str, "invalid_hl"))
+        *arg_val = FAL_NROM_TCP_INVALID_HL_CMD;
+    else if (!strcasecmp(cmd_str, "min_hdr_size"))
+        *arg_val = FAL_NROM_TCP_MIN_HDR_SIZE;
+    else if (!strcasecmp(cmd_str, "invalid_syn"))
+        *arg_val = FAL_NROM_TCP_INVALID_SYN_CMD;
+    else if (!strcasecmp(cmd_str, "su_block"))
+        *arg_val = FAL_NROM_TCP_SU_BLOCK_CMD;
+    else if (!strcasecmp(cmd_str, "sp_block"))
+        *arg_val = FAL_NROM_TCP_SP_BLOCK_CMD;
+    else if (!strcasecmp(cmd_str, "sap_block"))
+        *arg_val = FAL_NROM_TCP_SAP_BLOCK_CMD;
+    else if (!strcasecmp(cmd_str, "xmas_scan"))
+        *arg_val = FAL_NROM_TCP_XMAS_SCAN_CMD;
+    else if (!strcasecmp(cmd_str, "null_scan"))
+        *arg_val = FAL_NROM_TCP_NULL_SCAN_CMD;
+    else if (!strcasecmp(cmd_str, "sr_block"))
+        *arg_val = FAL_NROM_TCP_SR_BLOCK_CMD;
+    else if (!strcasecmp(cmd_str, "sf_block"))
+        *arg_val = FAL_NROM_TCP_SF_BLOCK_CMD;
+    else if (!strcasecmp(cmd_str, "sar_block"))
+        *arg_val = FAL_NROM_TCP_SAR_BLOCK_CMD;
+    else if (!strcasecmp(cmd_str, "rst_scan"))
+        *arg_val = FAL_NROM_TCP_RST_SCAN_CMD;
+    else if (!strcasecmp(cmd_str, "rst_with_data"))
+        *arg_val = FAL_NROM_TCP_RST_WITH_DATA_CMD;
+    else if (!strcasecmp(cmd_str, "fa_block"))
+        *arg_val = FAL_NROM_TCP_FA_BLOCK_CMD;
+    else if (!strcasecmp(cmd_str, "pa_block"))
+        *arg_val = FAL_NROM_TCP_PA_BLOCK_CMD;
+    else if (!strcasecmp(cmd_str, "ua_block"))
+        *arg_val = FAL_NROM_TCP_UA_BLOCK_CMD;
+    else if (!strcasecmp(cmd_str, "invalid_chksum"))
+        *arg_val = FAL_NROM_TCP_INVALID_CHKSUM_CMD;
+    else if (!strcasecmp(cmd_str, "invalid_urgptr"))
+        *arg_val = FAL_NROM_TCP_INVALID_URGPTR_CMD;
+    else if (!strcasecmp(cmd_str, "invalid_opts"))
+        *arg_val = FAL_NROM_TCP_INVALID_OPTIONS_CMD;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_sec_udp(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "blat"))
+        *arg_val = FAL_NROM_UDP_BLAT_CMD;
+    else if (!strcasecmp(cmd_str, "invalid_len"))
+        *arg_val = FAL_NROM_UDP_INVALID_LEN_CMD;
+    else if (!strcasecmp(cmd_str, "invalid_chksum"))
+        *arg_val = FAL_NROM_UDP_INVALID_CHKSUM_CMD;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_sec_icmp4(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "ping_pl_exceed"))
+        *arg_val = FAL_NROM_ICMP4_PING_PL_EXCEED_CMD;
+    else if (!strcasecmp(cmd_str, "ping_frag"))
+        *arg_val = FAL_NROM_ICMP4_PING_FRAG_CMD;
+    else if (!strcasecmp(cmd_str, "ping_max_pl"))
+        *arg_val = FAL_NROM_ICMP4_PING_MAX_PL_VALUE;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_sec_icmp6(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "ping_pl_exceed"))
+        *arg_val = FAL_NROM_ICMP6_PING_PL_EXCEED_CMD;
+    else if (!strcasecmp(cmd_str, "ping_frag"))
+        *arg_val = FAL_NROM_ICMP6_PING_FRAG_CMD;
+    else if (!strcasecmp(cmd_str, "ping_max_pl"))
+        *arg_val = FAL_NROM_ICMP6_PING_MAX_PL_VALUE;
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#ifdef HPPE
+sw_error_t
+cmd_data_check_l3_parser(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    a_uint32_t tmp;
+    sw_error_t rv;
+    fal_l3_excep_parser_ctrl entry;
+
+    aos_mem_zero(&entry, sizeof (fal_l3_excep_parser_ctrl));
+
+    do
+    {
+        cmd = get_sub_cmd("small_ip4ttl", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (a_uint32_t));
+            if (!rv)
+                entry.small_ip4ttl = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("small_ip6hoplimit", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (a_uint32_t));
+            if (!rv)
+                entry.small_ip6hoplimit = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_l3_excep_parser_ctrl *)val = entry;
+    return SW_OK;
+
+}
+
+sw_error_t
+cmd_data_check_l4_parser(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    a_uint32_t tmp;
+    sw_error_t rv;
+    fal_l4_excep_parser_ctrl entry;
+
+    aos_mem_zero(&entry, sizeof (fal_l4_excep_parser_ctrl));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags0", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags[0] = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags_mask0", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags_mask[0] = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags1", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags[1] = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags_mask1", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags_mask[1] = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags2", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags[2] = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags_mask2", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags_mask[2] = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags3", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags[3] = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags_mask3", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags_mask[3] = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags4", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags[4] = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags_mask4", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags_mask[4] = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags5", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags[5] = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags_mask5", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags_mask[5]= tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags6", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags[6] = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags_mask6", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags_mask[6] = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags7", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags[7] = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcp_flags_mask7", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (tmp));
+	entry.tcp_flags_mask[7] = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+
+    *(fal_l4_excep_parser_ctrl *)val = entry;
+    return SW_OK;
+
+}
+
+sw_error_t
+cmd_data_check_exp_ctrl(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_l3_excep_ctrl_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_l3_excep_ctrl_t));
+
+    do
+    {
+        cmd = get_sub_cmd("excep_cmd", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.cmd),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("deacclr_en", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &(entry.deacclr_en),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("l3route_only_en", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &(entry.l3route_only_en),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("l2fwd_only_en", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &(entry.l2fwd_only_en),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("l2flow_en", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &(entry.l2flow_en),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("l3flow_en", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &(entry.l3flow_en),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("multicast_en", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &(entry.multicast_en),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_l3_excep_ctrl_t *)val = entry;
+    return SW_OK;
+}
+#endif
+#endif
+#ifdef IN_COSMAP
+#ifndef IN_COSMAP_MINI
+sw_error_t
+cmd_data_check_remark_entry(char *info, void *val, a_uint32_t size)
+{
+    sw_error_t rv;
+    fal_egress_remark_table_t *pEntry = (fal_egress_remark_table_t *)val;
+    a_uint32_t tmp = 0;
+
+    memset(pEntry, 0, sizeof(fal_egress_remark_table_t));
+
+    /* get remark_dscp */
+    rv = __cmd_data_check_complex("remark dscp", "enable",
+                        "usage: <enable/disable>\n",
+                        (param_check_t)cmd_data_check_enable, &(pEntry->remark_dscp),
+                        sizeof(a_bool_t));
+    if (rv)
+        return rv;
+
+    /* get remark_up */
+    rv = __cmd_data_check_complex("remark up", "enable",
+                        "usage: <enable/disable>\n",
+                        (param_check_t)cmd_data_check_enable, &(pEntry->remark_up),
+                        sizeof(a_bool_t));
+    if (rv)
+        return rv;
+
+    /* get remark_dei */
+    rv = __cmd_data_check_complex("remark dei", "enable",
+                        "usage: <enable/disable>\n",
+                        (param_check_t)cmd_data_check_enable, &(pEntry->remark_dei),
+                        sizeof(a_bool_t));
+    if (rv)
+        return rv;
+
+    /* get g_dscp */
+    rv = __cmd_data_check_range("green dscp", NULL,
+                        "usage: the range is 0 -- 63\n",
+                        cmd_data_check_integer, &tmp, 63, 0);
+    if (rv)
+        return rv;
+    pEntry->g_dscp = tmp;
+
+    /* get y_dscp */
+    rv = __cmd_data_check_range("yellow dscp", NULL,
+                        "usage: the range is 0 -- 63\n",
+                        cmd_data_check_integer, &tmp, 63, 0);
+    if (rv)
+        return rv;
+    pEntry->y_dscp = tmp;
+
+    /* get g_up */
+    rv = __cmd_data_check_range("green up", NULL,
+                        "usage: the range is 0 -- 63\n",
+                        cmd_data_check_integer, &tmp, 7, 0);
+    if (rv)
+        return rv;
+    pEntry->g_up = tmp;
+
+    /* get y_up */
+    rv = __cmd_data_check_range("yellow up", NULL,
+                        "usage: the range is 0 -- 63\n",
+                        cmd_data_check_integer, &tmp, 7, 0);
+    if (rv)
+        return rv;
+    pEntry->y_up = tmp;
+
+    /* get g_dei */
+    rv = __cmd_data_check_range("green dei", NULL,
+                        "usage: the range is 0 -- 1\n",
+                        cmd_data_check_integer, &tmp, 1, 0);
+    if (rv)
+        return rv;
+    pEntry->g_dei = tmp;
+
+    /* get y_dei */
+    rv = __cmd_data_check_range("yellow dei", NULL,
+                        "usage: the range is 0 -- 1\n",
+                        cmd_data_check_integer, &tmp, 1, 0);
+    if (rv)
+        return rv;
+    pEntry->y_dei = tmp;
+
+/*
+    dprintf("remark_dscp=%d, remark_up=%d, g_dscp=%d, y_dscp=%d\n",
+            pEntry->remark_dscp,
+            pEntry->remark_up,
+            pEntry->g_dscp,
+            pEntry->y_dscp);
+
+    *(fal_egress_remark_table_t *) val = entry;
+*/
+    return SW_OK;
+}
+#endif
+#endif
+#ifdef IN_IP
+#ifndef IN_IP_MINI
+sw_error_t
+cmd_data_check_default_route_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_default_route_t entry;
+
+    aos_mem_zero(&entry, sizeof(entry));
+
+    do
+    {
+        cmd = get_sub_cmd("entry valid", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.valid), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("vrf id", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &(entry.vrf_id), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ip version", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &(entry.ip_version), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("route type", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &(entry.droute_type), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("index", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &(entry.index), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_default_route_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_host_route_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_host_route_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_intf_mac_entry_t));
+
+    do
+    {
+        cmd = get_sub_cmd("entry valid", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.valid), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("vrf id", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &(entry.vrf_id), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ip version", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &(entry.ip_version), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    if (entry.ip_version == 0) /*IPv4*/
+    {
+        rv = __cmd_data_check_complex("ip4 addr", NULL,
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip4addr, &(entry.route_addr.ip4_addr),
+                            4);
+        if (rv)
+            return rv;
+    }
+    else if (entry.ip_version == 1) /*IPv6*/
+    {
+        rv = __cmd_data_check_complex("ip6 addr", NULL,
+                            "usage: the format is xxxx::xxxx \n",
+                            (param_check_t)cmd_data_check_ip6addr, &(entry.route_addr.ip6_addr),
+                            16);
+        if (rv)
+            return rv;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    do
+    {
+        cmd = get_sub_cmd("prefix_length", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &(entry.prefix_length), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_host_route_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ip4_rfs_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+	a_uint32_t tmp = 0;
+	sw_error_t rv;
+	fal_ip4_rfs_t entry;
+
+	aos_mem_zero(&entry, sizeof (fal_ip4_rfs_t));
+
+	rv = __cmd_data_check_complex("mac addr", NULL,
+                        "usage: the format is xx-xx-xx-xx-xx-xx \n",
+                        (param_check_t)cmd_data_check_macaddr, &(entry.mac_addr),
+                        sizeof (fal_mac_addr_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("ip4 addr", NULL,
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip4addr, &(entry.ip4_addr),
+                            4);
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("vid", "0",
+                        "usage: the format is xx \n",
+                        cmd_data_check_uint32, &(entry.vid),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("loadbalance", "0",
+                        "usage: the format is xx \n",
+                        cmd_data_check_uint32, &tmp,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+    
+    entry.load_balance = tmp;
+    *(fal_ip4_rfs_t *)val = entry;
+    
+    return SW_OK;
+}
+#endif
+#endif
+#if 0
+sw_error_t
+cmd_data_check_fdb_rfs(char *cmd_str, void * val, a_uint32_t size)
+{
+	char *cmd;
+	a_uint32_t tmp;
+	sw_error_t rv;
+	fal_fdb_rfs_t entry;
+
+	aos_mem_zero(&entry, sizeof (fal_fdb_rfs_t));
+
+	rv = __cmd_data_check_complex("mac addr", NULL,
+                        "usage: the format is xx-xx-xx-xx-xx-xx \n",
+                        cmd_data_check_macaddr, &(entry.addr),
+                        sizeof (fal_mac_addr_t));
+    if (rv)
+        return rv;
+
+	rv = __cmd_data_check_complex("fid", NULL,
+                            "usage: the format is xx\n",
+                            cmd_data_check_uint32, &tmp,
+                            sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+	entry.fid = tmp;
+
+	rv = __cmd_data_check_complex("loadbalance", "0",
+                        "usage: the format is xx \n",
+                        cmd_data_check_uint32, &tmp,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+	entry.load_balance = tmp;
+
+	*(fal_fdb_rfs_t *)val = entry;
+	return SW_OK;
+}
+#endif
+#if defined(IN_IP) || defined(IN_NAT)
+sw_error_t
+cmd_data_check_flow_cookie(char *cmd_str, void * val, a_uint32_t size)
+{
+    sw_error_t rv;
+    fal_flow_cookie_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_flow_cookie_t));
+
+    rv = __cmd_data_check_complex("proto", "0",
+                        "usage: the format is xx \n",
+                        cmd_data_check_uint32, &(entry.proto),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("src addr", NULL,
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip4addr, &(entry.src_addr),
+                            4);
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("dst addr", NULL,
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip4addr, &(entry.dst_addr),
+                            4);
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("src port", "0",
+                        "usage: the format is xx \n",
+                        cmd_data_check_uint32, &(entry.src_port),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("dst port", "0",
+                        "usage: the format is xx \n",
+                        cmd_data_check_uint32, &(entry.dst_port),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("flow cookie", "0",
+                        "usage: the format is xx \n",
+                        cmd_data_check_uint32, &(entry.flow_cookie),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+
+    *(fal_flow_cookie_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_flow_rfs(char *cmd_str, void * val, a_uint32_t size)
+{
+    a_uint32_t tmp = 0;
+    sw_error_t rv;
+    fal_flow_rfs_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_flow_cookie_t));
+
+    rv = __cmd_data_check_complex("proto", "0",
+                        "usage: the format is xx \n",
+                        cmd_data_check_uint32, &(entry.proto),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("src addr", NULL,
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip4addr, &(entry.src_addr),
+                            4);
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("dst addr", NULL,
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip4addr, &(entry.dst_addr),
+                            4);
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("src port", "0",
+                        "usage: the format is xx \n",
+                        cmd_data_check_uint32, &(entry.src_port),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("dst port", "0",
+                        "usage: the format is xx \n",
+                        cmd_data_check_uint32, &(entry.dst_port),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("flow rfs", "0",
+                        "usage: the format is xx \n",
+                        cmd_data_check_uint32, &tmp,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    entry.load_balance = tmp;
+
+
+    *(fal_flow_rfs_t *)val = entry;
+    return SW_OK;
+}
+#endif
+#ifdef IN_IP
+#ifndef IN_IP_MINI
+sw_error_t
+cmd_data_check_ip_global(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    a_uint32_t tmp;
+    sw_error_t rv;
+    fal_ip_global_cfg_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_ip_global_cfg_t));
+
+    do
+    {
+        cmd = get_sub_cmd("mru_fail_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.mru_fail_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("mru_deacclr_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.mru_deacclr_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("mtu_fail_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.mtu_fail_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("mtu_deacclr_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.mtu_deacclr_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("mtu_nonfrag_fail_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.mtu_nonfrag_fail_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("mtu_nonfrag_deacclr_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.mtu_df_deacclr_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("prefix_bc_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.prefix_bc_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("prefix_bc_deacclr_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.prefix_deacclr_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("icmp_rdt_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.icmp_rdt_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("icmp_rdt_deacclr_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.icmp_rdt_deacclr_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("hash_mode_0", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (a_uint32_t));
+            if (!rv)
+                entry.hash_mode_0 = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("hash_mode_1", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (a_uint32_t));
+            if (!rv)
+                entry.hash_mode_1 = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_ip_global_cfg_t *)val = entry;
+    return SW_OK;
+
+}
+
+sw_error_t
+cmd_data_check_ip_mcmode(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_mc_mode_cfg_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_mc_mode_cfg_t));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv4_mc_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.l2_ipv4_mc_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv4_igmpv3_mode", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &(entry.l2_ipv4_mc_mode), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv6_mc_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.l2_ipv6_mc_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv6_mldv2_mode", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &(entry.l2_ipv6_mc_mode), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_mc_mode_cfg_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ip_portmac(char *cmd_str, void * val, a_uint32_t size)
+{
+	char *cmd;
+    sw_error_t rv;
+    fal_macaddr_entry_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_macaddr_entry_t));
+
+    do
+    {
+        cmd = get_sub_cmd("entry_valid", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &(entry.valid), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    rv = __cmd_data_check_complex("mac_addr", NULL,
+                        "usage: the format is xx-xx-xx-xx-xx-xx \n",
+                        (param_check_t)cmd_data_check_macaddr, &(entry.mac_addr),
+                        sizeof (fal_mac_addr_t));
+    if (rv)
+		return rv;
+
+    *(fal_macaddr_entry_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ip_pub(char *cmd_str, void * val, a_uint32_t size)
+{
+    sw_error_t rv;
+    fal_ip_pub_addr_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_ip_pub_addr_t));
+
+    rv = __cmd_data_check_complex(" pub_ip_addr", NULL,
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip4addr, &(entry.pub_ip_addr),
+                            4);
+    if (rv)
+        return rv; 
+
+    *(fal_ip_pub_addr_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ip_sg(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_sg_cfg_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_sg_cfg_t));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv4_sg_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ipv4_sg_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv4_sg_violation_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.ipv4_sg_vio_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv4_sg_port_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ipv4_sg_port_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv4_sg_svlan_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ipv4_sg_svlan_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv4_sg_cvlan_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ipv4_sg_cvlan_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv4_src_unk_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.ipv4_src_unk_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv6_sg_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ipv6_sg_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv6_sg_violation_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.ipv6_sg_vio_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv6_sg_port_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ipv6_sg_port_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv6_sg_svlan_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ipv6_sg_svlan_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv6_sg_cvlan_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ipv6_sg_cvlan_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv6_src_unk_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.ipv6_src_unk_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_sg_cfg_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_nexthop(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_ip_nexthop_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_ip_nexthop_t));
+
+    do
+    {
+        cmd = get_sub_cmd("type", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &(entry.type), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    if (entry.type == 0) {
+		do
+    		{
+		        cmd = get_sub_cmd("vsi", "0");
+		        SW_RTN_ON_NULL_PARAM(cmd);
+
+		        if (!strncasecmp(cmd, "quit", 4))
+		        {
+		            return SW_BAD_VALUE;
+		        }
+		        else if (!strncasecmp(cmd, "help", 4))
+		        {
+		            rv = SW_BAD_VALUE;
+		        }
+		        else
+		        {
+		            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.vsi), sizeof (a_uint8_t));
+		        }
+    		}
+    		while (talk_mode && (SW_OK != rv));
+    } else {
+    		do
+    		{
+		        cmd = get_sub_cmd("port", "0");
+		        SW_RTN_ON_NULL_PARAM(cmd);
+
+		        if (!strncasecmp(cmd, "quit", 4))
+		        {
+		            return SW_BAD_VALUE;
+		        }
+		        else if (!strncasecmp(cmd, "help", 4))
+		        {
+		            rv = SW_BAD_VALUE;
+		        }
+		        else
+		        {
+		            rv = cmd_data_check_uint8(cmd, &(entry.port), sizeof (a_uint8_t));
+		        }
+    		}
+    		while (talk_mode && (SW_OK != rv));
+    }
+
+    do
+    {
+        cmd = get_sub_cmd("if_index", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.if_index), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ip_to_me_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.ip_to_me_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("pub_ip_index", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.pub_ip_index), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("stag_fmt", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.stag_fmt), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("svid", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.svid), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ctag_fmt", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.ctag_fmt), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("cvid", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.cvid), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    rv = __cmd_data_check_complex("mac_addr", NULL,
+    		"usage: the format is xx-xx-xx-xx-xx-xx \n",
+    		(param_check_t)cmd_data_check_macaddr, &(entry.mac_addr),
+    		sizeof (fal_mac_addr_t));
+    if (rv)
+    	return rv;
+
+    rv = __cmd_data_check_complex(" dnat_ip", NULL,
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip4addr, &(entry.dnat_ip),
+                            4);
+    if (rv)
+        return rv;   
+	
+
+    *(fal_ip_nexthop_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_vsi_intf(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_intf_id_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_intf_id_t));
+
+    do
+    {
+        cmd = get_sub_cmd("l3_if_valid", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &(entry.l3_if_valid), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("l3_if_index", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.l3_if_index), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_intf_id_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_intf(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_intf_entry_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_intf_entry_t));
+
+    do
+    {
+        cmd = get_sub_cmd("mru", "0x5dc");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.mru), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("mtu", "0x5dc");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.mtu), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ttl_dec_bypass_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.ttl_dec_bypass_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv4_uc_route_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ipv4_uc_route_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ipv6_uc_route_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ipv6_uc_route_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("icmp_trigger_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.icmp_trigger_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ttl_exceed_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.ttl_exceed_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ttl_exceed_deacclr_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.ttl_exceed_deacclr_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("mac_addr_bitmap", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.mac_addr_bitmap), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    rv = __cmd_data_check_complex("mac_addr", NULL,
+    		"usage: the format is xx-xx-xx-xx-xx-xx \n",
+    		(param_check_t)cmd_data_check_macaddr, &(entry.mac_addr),
+    		sizeof (fal_mac_addr_t));
+    if (rv)
+    	return rv;
+
+    *(fal_intf_entry_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_network_route(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_network_route_entry_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_network_route_entry_t));
+
+    do
+    {
+        cmd = get_sub_cmd("type", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.type), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    if (entry.type == 0) /*IPv4*/
+    {
+        rv = __cmd_data_check_complex("ip4_addr", NULL,
+                        "usage: the format is xx.xx.xx.xx \n",
+                        (param_check_t)cmd_data_check_ip4addr, &(entry.route_addr.ip4_addr),
+                        4);
+	 if (rv)
+	 	return rv;
+    }
+    else if (entry.type == 1) /*IPv6*/
+    {
+	  rv = __cmd_data_check_complex("ip6_addr", NULL,
+                        "usage: the format is xxxx::xxxx \n",
+                        (param_check_t)cmd_data_check_ip6addr, &(entry.route_addr.ip6_addr),
+                        16);
+	 if (rv)
+	 	return rv;
+
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+     if (entry.type == 0) /*IPv4*/
+    {
+        rv = __cmd_data_check_complex("ip4_addr_mask", NULL,
+                            "usage: the format is xx.xx.xx.xx \n",
+                            (param_check_t)cmd_data_check_ip4addr, &(entry.route_addr_mask.ip4_addr_mask),
+                            4);
+        if (rv)
+            return rv;
+    }
+    else if (entry.type == 1) /*IPv6*/
+    {
+        rv = __cmd_data_check_complex("ip6_addr_mask", NULL,
+                            "usage: the format is xxxx::xxxx \n",
+                            (param_check_t)cmd_data_check_ip6addr, &(entry.route_addr_mask.ip6_addr_mask),
+                            16);
+        if (rv)
+            return rv;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    do
+    {
+        cmd = get_sub_cmd("action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("dst_info", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.dst_info), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("lan_wan", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.lan_wan), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_network_route_entry_t *)val = entry;
+    return SW_OK;
+}
+
+
+
+sw_error_t
+cmd_data_check_arp_sg(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_arp_sg_cfg_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_arp_sg_cfg_t));
+
+    do
+    {
+        cmd = get_sub_cmd("arp_sg_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ipv4_arp_sg_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("arp_sg_violation_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.ipv4_arp_sg_vio_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("arp_sg_port_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ipv4_arp_sg_port_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("arp_sg_svlan_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ipv4_arp_sg_svlan_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("arp_sg_cvlan_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ipv4_arp_sg_cvlan_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("arp_sg_unk_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.ipv4_arp_src_unk_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("nd_sg_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ip_nd_sg_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("nd_sg_violation_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.ip_nd_sg_vio_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("nd_sg_port_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ip_nd_sg_port_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("nd_sg_svlan_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ip_nd_sg_svlan_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("nd_sg_cvlan_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ip_nd_sg_cvlan_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("nd_sg_unk_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.ip_nd_src_unk_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_arp_sg_cfg_t *)val = entry;
+    return SW_OK;
+}
+sw_error_t
+cmd_data_check_ip6_rfs_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+    a_uint32_t tmp = 0;
+    sw_error_t rv;
+    fal_ip6_rfs_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_ip4_rfs_t));
+
+    rv = __cmd_data_check_complex("mac addr", NULL,
+                        "usage: the format is xx-xx-xx-xx-xx-xx \n",
+                        (param_check_t)cmd_data_check_macaddr, &(entry.mac_addr),
+                        sizeof (fal_mac_addr_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("ip6 addr", NULL,
+                            "usage: the format is xxxx::xxxx \n",
+                            (param_check_t)cmd_data_check_ip6addr, &(entry.ip6_addr),
+                            16);
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("vid", "0",
+                        "usage: the format is xx \n",
+                        cmd_data_check_uint32, &(entry.vid),
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    rv = __cmd_data_check_complex("loadbalance", "0",
+                        "usage: the format is xx \n",
+                        cmd_data_check_uint32, &tmp,
+                        sizeof (a_uint32_t));
+    if (rv)
+        return rv;
+
+    entry.load_balance = tmp;
+    *(fal_ip6_rfs_t *)val = entry;
+
+    return SW_OK;
+}
+#endif
+#endif
+#ifdef IN_VSI
+sw_error_t
+cmd_data_check_newadr_lrn(char *cmd_str, void * val, a_uint32_t size)
+{
+	char *cmd;
+	fal_vsi_newaddr_lrn_t entry;
+
+	aos_mem_zero(&entry, sizeof (fal_vsi_newaddr_lrn_t));
+
+	cmd_data_check_element("learnstatus_en", "enable", "usage: enable/disable\n",
+			cmd_data_check_enable, (cmd, &(entry.lrn_en), sizeof(entry.lrn_en)));
+
+	cmd_data_check_element("learnaction", "forward", "usage: forward/drop/cpycpu/rdtcpu\n",
+			cmd_data_check_maccmd, (cmd, &(entry.action), sizeof(entry.action)));
+
+	*(fal_vsi_newaddr_lrn_t *)val = entry;
+	return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_stamove(char *cmd_str, void * val, a_uint32_t size)
+{
+	char *cmd;
+	fal_vsi_stamove_t entry;
+
+	aos_mem_zero(&entry, sizeof (fal_vsi_stamove_t));
+
+	cmd_data_check_element("stationmove_en", "enable", "usage: enable/disable\n",
+			cmd_data_check_enable, (cmd, &(entry.stamove_en), sizeof(entry.stamove_en)));
+
+	cmd_data_check_element("stationmove_action", "forward", "usage: forward/drop/cpycpu/rdtcpu\n",
+			cmd_data_check_maccmd, (cmd, &(entry.action), sizeof(entry.action)));
+
+	*(fal_vsi_stamove_t *)val = entry;
+	return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_vsi_member(char *cmd_str, void * val, a_uint32_t size)
+{
+	sw_error_t rv;
+	fal_vsi_member_t entry;
+
+	aos_mem_zero(&entry, sizeof (fal_vsi_member_t));
+
+	rv = __cmd_data_check_complex("membership", 0,
+                        "usage: Bit0-port0 Bit1-port1 ....\n",
+                        cmd_data_check_pbmp, &(entry.member_ports),
+                        sizeof (a_uint32_t));
+	if (rv)
+		return rv;
+
+	rv = __cmd_data_check_complex("unknown_unicast_membership", 0,
+                        "usage: Bit0-port0 Bit1-port1 ....\n",
+                        cmd_data_check_pbmp, &(entry.uuc_ports),
+                        sizeof (a_uint32_t));
+	if (rv)
+		return rv;
+
+	rv = __cmd_data_check_complex("unknown_multicast_membership", 0,
+                        "usage: Bit0-port0 Bit1-port1 ....\n",
+                        cmd_data_check_pbmp, &(entry.umc_ports),
+                        sizeof (a_uint32_t));
+	if (rv)
+		return rv;
+
+	rv = __cmd_data_check_complex("broadcast_membership", 0,
+                        "usage: Bit0-port0 Bit1-port1 ....\n",
+                        cmd_data_check_pbmp, &(entry.bc_ports),
+                        sizeof (a_uint32_t));
+	if (rv)
+		return rv;
+
+	*(fal_vsi_member_t *)val = entry;
+	return SW_OK;
+}
+#endif
+
+#ifdef IN_FLOW
+sw_error_t
+cmd_data_check_flow_global(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    a_uint32_t tmp;
+    sw_error_t rv;
+    fal_flow_global_cfg_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_flow_global_cfg_t));
+
+    do
+    {
+        cmd = get_sub_cmd("src_intf_check_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.src_if_check_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("src_intf_deacclr_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.src_if_check_deacclr_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("service_loop_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.service_loop_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("service_loop_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.service_loop_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("service_loop_deacclr_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.service_loop_deacclr_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("flow_deacclr_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.flow_deacclr_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("sync_mismatch_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.sync_mismatch_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("sync_mismatch_deacclr_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.sync_mismatch_deacclr_en),
+                                       sizeof (a_bool_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("hash_mode_0", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (a_uint32_t));
+            if (!rv)
+                 entry.hash_mode_0 = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("hash_mode_1", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp,
+                                       sizeof (a_uint32_t));
+            if (!rv)
+                entry.hash_mode_1 = tmp;
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_flow_global_cfg_t *)val = entry;
+    return SW_OK;
+
+}
+
+sw_error_t
+cmd_data_check_flow(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_flow_entry_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_flow_entry_t));
+
+    do
+    {
+        cmd = get_sub_cmd("entry_id", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.entry_id), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("entry_type", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.entry_type), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("host_addr_type", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.host_addr_type), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("host_addr_index", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.host_addr_index), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("protocol", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.protocol), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("age", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.age), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("src_intf_valid", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &(entry.src_intf_valid), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("src_intf_index", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.src_intf_index), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("fwd_type", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.fwd_type), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    
+    do
+    {
+        cmd = get_sub_cmd("snat_nexthop", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.snat_nexthop), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("snat_srcport", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.snat_srcport), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("dnat_nexthop", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.dnat_nexthop), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("dnat_dstport", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.dnat_dstport), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("route_nexthop", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.route_nexthop), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("port_valid", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &(entry.port_valid), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("route_port", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.route_port), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("bridge_port", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.bridge_port), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("deacclr", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.deacclr_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("copy tocpu", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.copy_tocpu_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("syn toggle", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.syn_toggle), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("pri profile", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.pri_profile), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("sevice code", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.sevice_code), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ip type", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.ip_type), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("src port", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.src_port), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("dst port", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.dst_port), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    if (entry.entry_type & FAL_FLOW_IP4_5TUPLE_ADDR || entry.entry_type & FAL_FLOW_IP4_3TUPLE_ADDR) {
+        rv = __cmd_data_check_complex("ip addr", NULL,
+		"usage: the format is xx.xx.xx.xx \n",
+		(param_check_t)cmd_data_check_ip4addr, &(entry.flow_ip.ipv4),
+		4);
+        if (rv)
+		return rv;
+		
+    } else if (entry.entry_type & FAL_FLOW_IP6_5TUPLE_ADDR || entry.entry_type & FAL_FLOW_IP6_3TUPLE_ADDR) {
+        rv = __cmd_data_check_complex("ip addr", NULL,
+		"usage: the format is xxxx::xxxx \n",
+		(param_check_t)cmd_data_check_ip6addr, &(entry.flow_ip.ipv6),
+		16);
+        if (rv)
+		return rv;
+    }
+
+    do
+    {
+        cmd = get_sub_cmd("tree id", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.tree_id), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_flow_entry_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_flow_ctrl(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    a_uint32_t tmp;
+    sw_error_t rv;
+    fal_flow_mgmt_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_flow_mgmt_t));
+
+    do
+    {
+        cmd = get_sub_cmd("miss_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, (fal_fwd_cmd_t *)&(entry.miss_action),
+                                       sizeof (fal_fwd_cmd_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("frag_bypass_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.frag_bypass_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("tcpspec_bypass_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.tcp_spec_bypass_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("all_bypass_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.all_bypass_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("key_sel", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, &tmp, sizeof (a_uint32_t));
+            if (!rv)
+                entry.key_sel = tmp;
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_flow_mgmt_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_flow_age(char *cmd_str, void * val, a_uint32_t size)
+{
+	char *cmd;
+    a_uint32_t tmp;
+    sw_error_t rv;
+    fal_flow_age_timer_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_flow_age_timer_t));
+
+    do
+    {
+        cmd = get_sub_cmd("age_time", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &tmp, sizeof (a_uint32_t));
+            if (!rv)
+                entry.age_time = tmp;
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("age_unit", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &tmp, sizeof (a_uint32_t));
+            if (!rv)
+                entry.unit = tmp;
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_flow_age_timer_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_flow_host(char *cmd_str, void * val, a_uint32_t size)
+{
+        fal_flow_host_entry_t *flow_host = (fal_flow_host_entry_t *)val;
+        fal_flow_entry_t *flow_entry = &(flow_host->flow_entry);
+#ifdef IN_IP
+        fal_host_entry_t *host_entry = &(flow_host->host_entry);
+#endif
+
+        cmd_data_check_flow(cmd_str, flow_entry, size);
+#ifdef IN_IP
+        cmd_data_check_host_entry(cmd_str, host_entry, size);
+#endif
+	return SW_OK;
+}
+#endif
+
+#ifdef IN_BM
+sw_error_t
+cmd_data_check_bm_static_thresh(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_bm_static_cfg_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_bm_static_cfg_t));
+
+    do
+    {
+        cmd = get_sub_cmd("max_thresh", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.max_thresh),
+                                       sizeof (a_uint16_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("resume_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.resume_off),
+                                       sizeof (a_uint16_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_bm_static_cfg_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_bm_dynamic_thresh(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_bm_dynamic_cfg_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_bm_dynamic_cfg_t));
+
+    do
+    {
+        cmd = get_sub_cmd("weight", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.weight),
+                                       sizeof (a_uint8_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("shared_ceiling", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.shared_ceiling),
+                                       sizeof (a_uint16_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("resume_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.resume_off),
+                                       sizeof (a_uint16_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("resume_min_thresh", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.resume_min_thresh),
+                                       sizeof (a_uint16_t));
+        }
+
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_bm_dynamic_cfg_t *)val = entry;
+    return SW_OK;
+}
+#endif
+
+#ifdef IN_QM
+sw_error_t
+cmd_data_check_u_qmap(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_ucast_queue_dest_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_ucast_queue_dest_t));
+
+    do
+    {
+        cmd = get_sub_cmd("src_profile", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.src_profile), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("service_code_en", "no");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.service_code_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("service_code", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.service_code), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("cpu_code_en", "no");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.cpu_code_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("cpu_code", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.cpu_code), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("dst_port", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.dst_port), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_ucast_queue_dest_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ac_static_thresh(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_ac_static_threshold_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_ac_static_threshold_t));
+
+    do
+    {
+        cmd = get_sub_cmd("color_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.color_enable), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+
+    do
+    {
+        cmd = get_sub_cmd("wred_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.wred_enable), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("green_max", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.green_max), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("green_min_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.green_min_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("yel_max_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.yel_max_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("yel_min_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.yel_min_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("red_max_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.red_max_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("red_min_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.red_min_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("green_resume_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.green_resume_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("yel_resume_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.yel_resume_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("red_resume_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.red_resume_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+	
+    *(fal_ac_static_threshold_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ac_dynamic_thresh(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    a_uint32_t tmp;
+    sw_error_t rv;
+    fal_ac_dynamic_threshold_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_ac_dynamic_threshold_t));
+
+    do
+    {
+        cmd = get_sub_cmd("color_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.color_enable), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+
+    do
+    {
+        cmd = get_sub_cmd("wred_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.wred_enable), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("shared_weight", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint8(cmd, (a_uint32_t *)&(entry.shared_weight), sizeof (a_uint8_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("green_min_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.green_min_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("yel_max_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.yel_max_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("yel_min_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.yel_min_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("red_max_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.red_max_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("red_min_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.red_min_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("green_resume_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.green_resume_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("yel_resume_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.yel_resume_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("red_resume_off", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.red_resume_off), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ceiling", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, &tmp, sizeof (a_uint32_t));
+            if (!rv)
+                entry.ceiling = tmp;
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+	
+    *(fal_ac_dynamic_threshold_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ac_group_buff(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_ac_group_buffer_t entry;
+
+    do
+    {
+        cmd = get_sub_cmd("prealloc_buffer", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.prealloc_buffer), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("total_buffer", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint16(cmd, (a_uint32_t *)&(entry.total_buffer), sizeof (a_uint16_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_ac_group_buffer_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ac_ctrl(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_ac_ctrl_t entry;
+
+    do
+    {
+        cmd = get_sub_cmd("ac_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ac_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ac_fc_en", "yes");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_TRUE, &(entry.ac_fc_en), sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_ac_ctrl_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ac_obj(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_ac_obj_t entry;
+
+    do
+    {
+        cmd = get_sub_cmd("obj_type", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.type), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("obj_id", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.obj_id), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_ac_obj_t *)val = entry;
+    return SW_OK;
+}
+
+#endif
+
+#ifdef IN_SHAPER
+
+sw_error_t
+cmd_data_check_port_shaper_token_config(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_shaper_token_number_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_shaper_token_number_t));
+
+    do
+    {
+        cmd = get_sub_cmd("ctoken_negative_enable", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.c_token_number_negative_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ctoken_number", "0-0x3FFFFFFF");
+	SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.c_token_number), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_shaper_token_number_t *)val = entry;
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_shaper_token_config(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_shaper_token_number_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_shaper_token_number_t));
+
+    do
+    {
+        cmd = get_sub_cmd("ctoken_negative_enable", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.c_token_number_negative_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ctoken_number", "0-0x3FFFFFFF");
+	SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.c_token_number), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("etoken_negative_enable", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.e_token_number_negative_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+
+    do
+    {
+        cmd = get_sub_cmd("etoken_number", "0-0x3FFFFFFF");
+	SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.e_token_number), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_shaper_token_number_t *)val = entry;
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_port_shaper_config(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_shaper_config_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_shaper_config_t));
+
+    do
+    {
+        cmd = get_sub_cmd("meter_unit", "0-1");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.meter_unit), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("cshaper_enable", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.c_shaper_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("cir", "0");
+	SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.cir), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("cbs", "0");
+	SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.cbs), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+     do
+    {
+        cmd = get_sub_cmd("shaper_frame_mode", "0-2");
+	SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.shaper_frame_mode), sizeof (fal_shaper_frame_mode_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_shaper_config_t *)val = entry;
+    return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_shaper_config(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_shaper_config_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_shaper_config_t));
+
+    do
+    {
+        cmd = get_sub_cmd("couple_enable", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.couple_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("meter_unit", "0-1");
+	SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.meter_unit), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("cshaper_enable", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.c_shaper_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("cir", "0");
+	SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.cir), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("cbs", "0");
+	SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.cbs), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("eshaper_enable", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.e_shaper_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("eir", "0");
+	SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.eir), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ebs", "0");
+	SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.ebs), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("shaper_frame_mode", "0-2");
+	SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.shaper_frame_mode), sizeof (fal_shaper_frame_mode_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_shaper_config_t *)val = entry;
+    return SW_OK;
+}
+
+#endif
+
+#ifdef IN_POLICER
+sw_error_t
+cmd_data_check_port_policer_config(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_policer_config_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_policer_config_t));
+
+    do
+    {
+        cmd = get_sub_cmd("meter_enable", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.meter_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("couple_enable", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.couple_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("color_mode", "0-1");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.color_mode), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("frame_type", "0-0x1f");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.frame_type), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("meter_mode", "0-1");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.meter_mode), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+
+    do
+    {
+        cmd = get_sub_cmd("meter_unit", "0-1");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.meter_unit), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("cir", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.cir), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("cbs", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.cbs), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("eir", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.eir), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ebs", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.ebs), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_policer_config_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_acl_policer_config(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_policer_config_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_policer_config_t));
+
+    do
+    {
+        cmd = get_sub_cmd("meter_enable", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.meter_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("couple_enable", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.couple_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("color_mode", "0-1");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.color_mode), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("meter_mode", "0-1");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.meter_mode), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+
+    do
+    {
+        cmd = get_sub_cmd("meter_unit", "0-1");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.meter_unit), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("cir", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.cir), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("cbs", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.cbs), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("eir", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.eir), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("ebs", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.ebs), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_policer_config_t *)val = entry;
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_policer_cmd_config(char *cmd_str, void * val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_policer_action_t entry;
+
+    aos_mem_zero(&entry, sizeof (fal_policer_action_t));
+
+    do
+    {
+        cmd = get_sub_cmd("yellow_priority_remark", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.yellow_priority_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("yellow_drop_priority_remark", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.yellow_drop_priority_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+
+    do
+    {
+        cmd = get_sub_cmd("yellow_pcp_remark", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.yellow_pcp_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("yellow_dei_remark", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.yellow_dei_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("yellow_priority", "0-15");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.yellow_priority), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("yellow_drop_priority", "0-3");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.yellow_drop_priority), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("yellow_pcp", "0-7");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.yellow_pcp), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("yellow_dei", "0-1");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.yellow_dei), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+       do
+    {
+        cmd = get_sub_cmd("red_action", "drop");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(entry.red_action), sizeof(a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+
+    do
+    {
+        cmd = get_sub_cmd("red_priority_remark", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.red_priority_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("red_drop_priority_remark", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.red_drop_priority_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("red_pcp_remark", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.red_pcp_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("red_dei_remark", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.red_dei_en),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("red_priority", "0-15");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.red_priority), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("red_drop_priority", "0-3");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.red_drop_priority), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("red_pcp", "0-7");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.red_pcp), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("red_dei", "0-1");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(entry.red_dei), sizeof (a_uint32_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    *(fal_policer_action_t *)val = entry;
+    return SW_OK;
+}
+
+#endif
+
+#ifdef IN_SERVCODE
+sw_error_t
+cmd_data_check_servcode_config(char *info, fal_servcode_config_t *val, a_uint32_t size)
+{
+	char *cmd = NULL;
+	sw_error_t rv;
+	fal_servcode_config_t entry;
+
+	memset(&entry, 0, sizeof (fal_servcode_config_t));
+
+	do
+	{
+		cmd = get_sub_cmd("dest_port_valid", "yes");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_TRUE, &entry.dest_port_valid,
+					sizeof (a_bool_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("dest_port_id", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &entry.dest_port_id, sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("bypass_bitmap[0]", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &entry.bypass_bitmap[0], sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("bypass_bitmap[1]", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &entry.bypass_bitmap[1], sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("bypass_bitmap[2]", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &entry.bypass_bitmap[2], sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("direction", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &entry.direction, sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("field_update_bitmap", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &entry.field_update_bitmap, sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("next_service_code", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &entry.next_service_code, sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("hw_services", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &entry.hw_services, sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("offset_sel", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &entry.offset_sel, sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	*val = entry;
+	return SW_OK;
+}
+#endif
+
+#ifdef IN_RSS_HASH
+sw_error_t
+cmd_data_check_rss_hash_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "ipv4v6"))
+    {
+        *arg_val = FAL_RSS_HASH_IPV4V6;
+    }
+    else if (!strcasecmp(cmd_str, "ipv4"))
+    {
+        *arg_val = FAL_RSS_HASH_IPV4ONLY;
+    }
+    else if (!strcasecmp(cmd_str, "ipv6"))
+    {
+        *arg_val = FAL_RSS_HASH_IPV6ONLY;
+    }
+    else
+    {
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_rss_hash_config(char *info, fal_rss_hash_config_t *val, a_uint32_t size)
+{
+	char *cmd = NULL;
+	sw_error_t rv;
+	fal_rss_hash_config_t entry;
+
+	memset(&entry, 0, sizeof (fal_rss_hash_config_t));
+
+	do
+	{
+		cmd = get_sub_cmd("hash_mask", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &entry.hash_mask, sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("hash_fragment_mode", "no");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.hash_fragment_mode,
+					sizeof (a_bool_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("hash_seed", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &entry.hash_seed, sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("hash_sip_mix", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &entry.hash_sip_mix, sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("hash_dip_mix", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &entry.hash_dip_mix, sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("hash_protocol_mix", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(entry.hash_protocol_mix), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("hash_sport_mix", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(entry.hash_sport_mix), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("hash_dport_mix", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, (a_uint32_t *)&(entry.hash_dport_mix), sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("hash_fin_inner", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &entry.hash_fin_inner, sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	do
+	{
+		cmd = get_sub_cmd("hash_fin_outer", "0");
+		SW_RTN_ON_NULL_PARAM(cmd);
+
+		if (!strncasecmp(cmd, "quit", 4))
+		{
+			return SW_BAD_VALUE;
+		}
+		else if (!strncasecmp(cmd, "help", 4))
+		{
+			rv = SW_BAD_VALUE;
+		}
+		else
+		{
+			rv = cmd_data_check_uint32(cmd, &entry.hash_fin_outer, sizeof (a_uint32_t));
+		}
+	}
+	while (talk_mode && (SW_OK != rv));
+
+	*val = entry;
+	return SW_OK;
+}
+#endif
+
+#ifdef IN_MIRROR
+sw_error_t
+cmd_data_check_mirr_analy_cfg(char *info, void *val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_mirr_analysis_config_t *pEntry = (fal_mirr_analysis_config_t *)val;
+
+    memset(pEntry, 0, sizeof(fal_mirr_analysis_config_t));
+
+    do
+    {
+        cmd = get_sub_cmd("analysis_port", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(pEntry->port_id), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    do
+    {
+        cmd = get_sub_cmd("analysis_priority", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &(pEntry->priority), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_mirr_direction(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+    if (cmd_str == NULL)
+        return SW_BAD_PARAM;
+
+    if (!strcasecmp(cmd_str, "both"))
+    {
+        *arg_val = FAL_MIRR_BOTH;
+    }
+    else if (!strcasecmp(cmd_str, "ingress"))
+    {
+        *arg_val = FAL_MIRR_INGRESS;
+    }
+    else if (!strcasecmp(cmd_str, "egress"))
+    {
+        *arg_val = FAL_MIRR_EGRESS;
+    }
+    else
+    {
+        //dprintf("input error \n");
+        return SW_BAD_VALUE;
+    }
+
+    return SW_OK;
+}
+#endif
+
+#ifdef IN_CTRLPKT
+sw_error_t
+cmd_data_check_ctrlpkt_appprofile(char *info, void *val, a_uint32_t size)
+{
+    char *cmd;
+    sw_error_t rv;
+    fal_ctrlpkt_profile_t *pEntry = (fal_ctrlpkt_profile_t *)val;
+    a_uint32_t tmp = 0;
+
+    memset(pEntry, 0, sizeof(fal_ctrlpkt_profile_t));
+
+    /* get port bitmap */
+    do
+    {
+        cmd = get_sub_cmd("port_bitmap", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &tmp, sizeof(a_uint32_t));
+
+	     pEntry->port_map = tmp;
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get ethernet type profile */
+    do
+    {
+        cmd = get_sub_cmd("ethtype_profile_bitmap", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &tmp, sizeof(a_uint32_t));
+
+	     pEntry->ethtype_profile_bitmap = tmp;
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get rfdb profile */
+    do
+    {
+        cmd = get_sub_cmd("rfdb_profile_bitmap", "0");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_uint32(cmd, &tmp, sizeof(a_uint32_t));
+
+	     pEntry->rfdb_profile_bitmap= tmp;
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get mgt_eapol */
+    do
+    {
+        cmd = get_sub_cmd("eapol_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->protocol_types.mgt_eapol),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    /* get mgt_eapol */
+    do
+    {
+        cmd = get_sub_cmd("pppoe_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->protocol_types.mgt_pppoe),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    /* get mgt_igmp */
+    do
+    {
+        cmd = get_sub_cmd("igmp_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->protocol_types.mgt_igmp),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    /* get mgt_arp_req */
+    do
+    {
+        cmd = get_sub_cmd("arp_request_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->protocol_types.mgt_arp_req),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    /* get mgt_arp_rep */
+    do
+    {
+        cmd = get_sub_cmd("arp_response_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->protocol_types.mgt_arp_rep),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    /* get mgt_dhcp4 */
+    do
+    {
+        cmd = get_sub_cmd("dhcp4_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->protocol_types.mgt_dhcp4),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    /* get mgt_dhcp6 */
+    do
+    {
+        cmd = get_sub_cmd("dhcp6_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->protocol_types.mgt_dhcp6),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    /* get mgt_mld */
+    do
+    {
+        cmd = get_sub_cmd("mld_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->protocol_types.mgt_mld),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+
+    /* get mgt_ns */
+    do
+    {
+        cmd = get_sub_cmd("ip6ns_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->protocol_types.mgt_ns),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    /* get mgt_na */
+    do
+    {
+        cmd = get_sub_cmd("ip6na_en", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->protocol_types.mgt_na),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    /* get forward command */
+    do
+    {
+        cmd = get_sub_cmd("ctrlpkt_profile_action", "forward");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_maccmd(cmd, &(pEntry->action.action), sizeof(a_uint32_t));
+        }
+    }while (talk_mode && (SW_OK != rv));
+
+    /* get sg_byp */
+    do
+    {
+        cmd = get_sub_cmd("sourceguard_bypass", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->action.sg_bypass),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    /* get l2_filter_byp */
+    do
+    {
+        cmd = get_sub_cmd("l2filter_bypass", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->action.l2_filter_bypass),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    /* get in_stp_byp */
+    do
+    {
+        cmd = get_sub_cmd("ingress_stp_bypass", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->action.in_stp_bypass),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    /* get in_vlan_fltr_byp */
+    do
+    {
+        cmd = get_sub_cmd("ingress_vlan_filter_bypass", "no");
+        SW_RTN_ON_NULL_PARAM(cmd);
+
+        if (!strncasecmp(cmd, "quit", 4))
+        {
+            return SW_BAD_VALUE;
+        }
+        else if (!strncasecmp(cmd, "help", 4))
+        {
+            rv = SW_BAD_VALUE;
+        }
+        else
+        {
+            rv = cmd_data_check_confirm(cmd, A_FALSE, &(pEntry->action.in_vlan_fltr_bypass),
+                                        sizeof (a_bool_t));
+        }
+    }
+    while (talk_mode && (SW_OK != rv));
+
+    return SW_OK;
+}
+#endif
+
+sw_error_t
+cmd_data_check_module(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+	if (cmd_str == NULL)
+		return SW_BAD_PARAM;
+
+	if (!strcasecmp(cmd_str, "acl")) {
+		*arg_val = FAL_MODULE_ACL;
+	} else if (!strcasecmp(cmd_str, "vsi")) {
+		*arg_val = FAL_MODULE_VSI;
+	} else if (!strcasecmp(cmd_str, "ip")) {
+		*arg_val = FAL_MODULE_IP;
+	} else if (!strcasecmp(cmd_str, "flow")) {
+		*arg_val = FAL_MODULE_FLOW;
+	} else if (!strcasecmp(cmd_str, "qm")) {
+		*arg_val = FAL_MODULE_QM;
+	} else if (!strcasecmp(cmd_str, "qos")) {
+		*arg_val = FAL_MODULE_QOS;
+	} else if (!strcasecmp(cmd_str, "bm")) {
+		*arg_val = FAL_MODULE_BM;
+	} else if (!strcasecmp(cmd_str, "servcode")) {
+		*arg_val = FAL_MODULE_SERVCODE;
+	} else if (!strcasecmp(cmd_str, "rsshash")) {
+		*arg_val = FAL_MODULE_RSS_HASH;
+	} else if (!strcasecmp(cmd_str, "pppoe")) {
+		*arg_val = FAL_MODULE_PPPOE;
+	} else if (!strcasecmp(cmd_str, "portctrl")) {
+		*arg_val = FAL_MODULE_PORTCTRL;
+	} else if (!strcasecmp(cmd_str, "shaper")) {
+		*arg_val = FAL_MODULE_SHAPER;
+	} else if (!strcasecmp(cmd_str, "mib")) {
+		*arg_val = FAL_MODULE_MIB;
+	} else if (!strcasecmp(cmd_str, "mirror")) {
+		*arg_val = FAL_MODULE_MIRROR;
+	} else if (!strcasecmp(cmd_str, "fdb")) {
+		*arg_val = FAL_MODULE_FDB;
+	} else if (!strcasecmp(cmd_str, "stp")) {
+		*arg_val = FAL_MODULE_STP;
+	} else if (!strcasecmp(cmd_str, "sec")) {
+		*arg_val = FAL_MODULE_SEC;
+	} else if (!strcasecmp(cmd_str, "trunk")) {
+		*arg_val = FAL_MODULE_TRUNK;
+	} else if (!strcasecmp(cmd_str, "portvlan")) {
+		*arg_val = FAL_MODULE_PORTVLAN;
+	} else if (!strcasecmp(cmd_str, "ctrlpkt")) {
+		*arg_val = FAL_MODULE_CTRLPKT;
+	} else if (!strcasecmp(cmd_str, "policer")) {
+		*arg_val = FAL_MODULE_POLICER;
+	}
+	else
+	{
+		return SW_BAD_VALUE;
+	}
+
+	return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_func_ctrl(char *cmd_str, void * val, a_uint32_t size)
+{
+	sw_error_t rv;
+	fal_func_ctrl_t entry;
+
+	aos_mem_zero(&entry, sizeof (fal_func_ctrl_t));
+
+	rv = __cmd_data_check_complex("bitmap0", "0",
+			"usage: the format is HEX \n", cmd_data_check_uint32,
+			&(entry.bitmap[0]), sizeof (a_uint32_t));
+	if (rv)
+		return rv;
+
+	rv = __cmd_data_check_complex("bitmap1", "0",
+			"usage: the format is HEX \n", cmd_data_check_uint32,
+			&(entry.bitmap[1]), sizeof (a_uint32_t));
+	if (rv)
+		return rv;
+
+	rv = __cmd_data_check_complex("bitmap2", "0",
+			"usage: the format is HEX \n", cmd_data_check_uint32,
+			&(entry.bitmap[2]), sizeof (a_uint32_t));
+	if (rv)
+		return rv;
+
+	*(fal_func_ctrl_t *)val = entry;
+
+	return SW_OK;
+}
diff --git a/qca-ssdk/src/shell_lib/shell_sw.c b/qca-ssdk/src/shell_lib/shell_sw.c
new file mode 100755
index 0000000..796da33
--- /dev/null
+++ b/qca-ssdk/src/shell_lib/shell_sw.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2013, 2017, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "sw.h"
+#include "sw_error.h"
+#include "shell.h"
+
+static int sw_devid = 0;
+
+sw_error_t
+cmd_set_devid(a_uint32_t *arg_val)
+{
+    if (arg_val[1] >= SW_MAX_NR_DEV)
+    {
+        return SW_FAIL;
+    }
+    sw_devid = arg_val[1];
+
+    return SW_OK;
+}
+
+sw_error_t
+uci_set_devid(a_uint32_t dev_id)
+{
+    if (dev_id >= SW_MAX_NR_DEV)
+    {
+        printk("dev_id should be less than <%d>\n", SW_MAX_NR_DEV);
+        return SW_FAIL;
+    }
+    sw_devid = dev_id;
+
+    return SW_OK;
+}
+
+int
+get_devid(void)
+{
+    return sw_devid;
+}
+
diff --git a/qca-ssdk/src/util/Makefile b/qca-ssdk/src/util/Makefile
new file mode 100755
index 0000000..f909cbb
--- /dev/null
+++ b/qca-ssdk/src/util/Makefile
@@ -0,0 +1,12 @@
+LOC_DIR=src/util
+LIB=UTIL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=$(wildcard *.c)
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/qca-ssdk/src/util/util.c b/qca-ssdk/src/util/util.c
new file mode 100755
index 0000000..ba152b4
--- /dev/null
+++ b/qca-ssdk/src/util/util.c
@@ -0,0 +1,486 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#include "sw.h"
+#include "util.h"
+
+
+static sll_node_t *
+sll_nd_new(sll_head_t * sll)
+{
+    sll_node_t *new_nd;
+
+    if (LL_FIX_NDNR & sll->flag)
+    {
+        if (NULL == sll->free_nd)
+        {
+            new_nd = NULL;
+        }
+        else
+        {
+            new_nd = sll->free_nd;
+            sll->free_nd = sll->free_nd->next;
+        }
+    }
+    else
+    {
+        new_nd = aos_mem_alloc(sizeof (sll_node_t));
+    }
+
+    if (NULL != new_nd)
+    {
+        aos_mem_zero(new_nd, sizeof (sll_node_t));
+    }
+
+    return new_nd;
+}
+
+static void
+sll_nd_free(sll_head_t * sll, sll_node_t * nd)
+{
+    if (LL_FIX_NDNR & sll->flag)
+    {
+        nd->next = sll->free_nd;
+        sll->free_nd = nd;
+    }
+    else
+    {
+        aos_mem_free(nd);
+    }
+    return;
+}
+
+//#define SLL_DENUG
+#ifdef SLL_DENUG
+static void
+sll_nd_dump(sll_head_t * sll, const char * info)
+{
+    sll_node_t * curr;
+
+    if (NULL == sll->nd_dump)
+    {
+        return;
+    }
+
+    aos_printk("\n%s    node number = %d\n", info, sll->nd_nr);
+    curr = sll->fst_nd;
+    while (NULL != curr)
+    {
+        sll->nd_dump(curr->data);
+        curr = curr->next;
+    }
+}
+#else
+#define sll_nd_dump(sll, info)
+#endif
+
+sll_head_t *
+sll_creat(ll_nd_cmp cmp_func, ll_nd_dump dump_func, a_uint32_t flag, a_uint32_t nd_nr)
+{
+    sll_head_t *head;
+    sll_node_t *node;
+    a_uint32_t i, size;
+
+    if (flag & LL_FIX_NDNR)
+    {
+        size = sizeof (sll_head_t) + sizeof (sll_node_t) * nd_nr;
+    }
+    else
+    {
+        size = sizeof (sll_head_t);
+    }
+
+    head = aos_mem_alloc(size);
+    if (NULL == head)
+    {
+        return NULL;
+    }
+    aos_mem_zero(head, size);
+
+    head->fst_nd  = NULL;
+    head->nd_nr   = 0;
+    head->flag    = flag;
+    head->nd_cmp  = cmp_func;
+    head->nd_dump = dump_func;
+    head->free_nd = NULL;
+
+    if (flag & LL_FIX_NDNR)
+    {
+        node = (sll_node_t *) ((a_uint8_t *) head + sizeof (sll_head_t));
+        for (i = 0; i < nd_nr; i++)
+        {
+            node[i].next = head->free_nd;
+            head->free_nd = &(node[i]);
+        }
+    }
+
+    return head;
+}
+
+void
+sll_destroy(sll_head_t * sll)
+{
+    aos_mem_free(sll);
+    return;
+}
+
+void
+sll_lock(sll_head_t * sll)
+{
+    return;
+}
+
+void
+sll_unlock(sll_head_t * sll)
+{
+    return;
+}
+
+void *
+sll_nd_find(const sll_head_t *sll, void *data, a_ulong_t *iterator)
+{
+    sll_node_t *node;
+    ll_cmp_rslt_t rslt;
+
+    node = sll->fst_nd;
+    while (NULL != node)
+    {
+        rslt = sll->nd_cmp(node->data, data);
+        if (LL_CMP_EQUAL == rslt)
+        {
+            *iterator = (a_ulong_t)node;
+            return node->data;
+        }
+
+        if ((LL_CMP_GREATER == rslt) && (sll->flag & LL_IN_ORDER))
+        {
+            return NULL;
+        }
+        node = node->next;
+    }
+
+    return NULL;
+}
+
+void *
+sll_nd_next(const sll_head_t *sll, a_ulong_t *iterator)
+{
+    sll_node_t *curr = NULL;
+
+    if (0 == *iterator)
+    {
+        if (NULL != sll->fst_nd)
+        {
+            curr = sll->fst_nd;
+        }
+    }
+    else
+    {
+        curr = ((sll_node_t *)(*iterator))->next;
+    }
+
+    if (NULL == curr)
+    {
+        return NULL;
+    }
+    else
+    {
+        *iterator = (a_ulong_t)curr;
+        return curr->data;
+    }
+}
+
+sw_error_t
+sll_nd_insert(sll_head_t * sll, void *data)
+{
+    sll_node_t *node = NULL;
+    sll_node_t *curr = NULL;
+    sll_node_t *prev;
+    ll_cmp_rslt_t rslt;
+
+    sll_nd_dump(sll, "sll_nd_insert before insert");
+
+    node = sll_nd_new(sll);
+    if (NULL == node)
+    {
+        return SW_NO_RESOURCE;
+    }
+    node->data = data;
+
+    if ((NULL == sll->fst_nd)
+            || (0 == (sll->flag & LL_IN_ORDER)))
+    {
+        node->next = sll->fst_nd;
+        sll->fst_nd = node;
+        sll->nd_nr++;
+        sll_nd_dump(sll, "sll_nd_insert after insert");
+        return SW_OK;
+    }
+
+    curr = sll->fst_nd;
+    prev = NULL;
+    while (NULL != curr)
+    {
+        rslt = sll->nd_cmp(curr->data, data);
+
+        if (LL_CMP_EQUAL == rslt)
+        {
+            sll_nd_free(sll, node);
+            return SW_ALREADY_EXIST;
+        }
+
+        if (LL_CMP_GREATER == rslt)
+        {
+            break;
+        }
+        prev = curr;
+        curr = curr->next;
+    }
+
+    if (NULL == prev)
+    {
+        node->next = sll->fst_nd;
+        sll->fst_nd = node;
+    }
+    else
+    {
+        prev->next = node;
+        node->next = curr;
+    }
+    sll->nd_nr++;
+
+    sll_nd_dump(sll, "sll_nd_insert after insert");
+    return SW_OK;
+}
+
+sw_error_t
+sll_nd_delete(sll_head_t * sll, void *data)
+{
+    sll_node_t *curr;
+    sll_node_t *prev = NULL;
+    ll_cmp_rslt_t rslt;
+
+    sll_nd_dump(sll, "sll_nd_delete before delete");
+
+    curr = sll->fst_nd;
+    while (NULL != curr)
+    {
+        rslt = sll->nd_cmp(curr->data, data);
+        if (LL_CMP_EQUAL == rslt)
+        {
+            if (NULL != prev)
+            {
+                prev->next = curr->next;
+            }
+            else
+            {
+                sll->fst_nd = curr->next;
+            }
+            sll->nd_nr--;
+            sll_nd_free(sll, curr);
+
+            sll_nd_dump(sll, "sll_nd_delete after delete");
+            return SW_OK;
+        }
+
+        if ((LL_CMP_GREATER == rslt) && (sll->flag & LL_IN_ORDER))
+        {
+            return SW_NOT_FOUND;
+        }
+
+        prev = curr;
+        curr = curr->next;
+    }
+
+    return SW_NOT_FOUND;
+}
+
+
+#define ID_SIZE_U8     0x1
+#define ID_SIZE_U16    0x2
+#define ID_SIZE_U32    0x4
+
+#define ID_NR_IN_U8    256
+#define ID_NR_IN_U16   65536
+
+sid_pool_t *
+sid_pool_creat(a_uint32_t id_nr, a_uint32_t min_id)
+{
+    sid_pool_t * pool;
+    a_uint32_t   size;
+    a_uint32_t   id_size;
+    a_uint32_t   i;
+
+    if (0 == id_nr)
+    {
+        return NULL;
+    }
+
+    pool = aos_mem_alloc(sizeof(sid_pool_t));
+    if (NULL == pool)
+    {
+        return NULL;
+    }
+    aos_mem_zero(pool, sizeof(sid_pool_t));
+
+    pool->id_min     = min_id;
+    pool->id_nr      = id_nr;
+    pool->id_ptr     = 0;
+
+    if (ID_NR_IN_U8 >= id_nr)
+    {
+        size = ((id_nr + 3) >> 2) << 2;
+        id_size = ID_SIZE_U8;
+    }
+    else if (ID_NR_IN_U16 >= id_nr)
+    {
+        size = ((id_nr + 1) >> 1) << 2;
+        id_size = ID_SIZE_U16;
+    }
+    else
+    {
+        size = id_nr << 2;
+        id_size = ID_SIZE_U32;
+    }
+    pool->id_size = id_size;
+
+    pool->id_pool = aos_mem_alloc(size);
+    if (NULL == pool->id_pool)
+    {
+        aos_mem_free(pool);
+        return NULL;
+    }
+    aos_mem_zero(pool->id_pool, size);
+
+    if (ID_SIZE_U8 == id_size)
+    {
+        a_uint8_t *p_id;
+
+        p_id = pool->id_pool;
+        for (i = 0; i < id_nr; i++)
+        {
+            p_id[i] = i;
+        }
+    }
+    else if (ID_SIZE_U16 == id_size)
+    {
+        a_uint16_t *p_id;
+
+        p_id = pool->id_pool;
+        for (i = 0; i < id_nr; i++)
+        {
+            p_id[i] = i;
+        }
+    }
+    else
+    {
+        a_uint32_t *p_id;
+
+        p_id = pool->id_pool;
+        for (i = 0; i < id_nr; i++)
+        {
+            p_id[i] = i;
+        }
+    }
+
+    return pool;
+}
+
+void
+sid_pool_destroy(sid_pool_t * pool)
+{
+    aos_mem_free(pool->id_pool);
+    aos_mem_free(pool);
+    return;
+}
+
+sw_error_t
+sid_pool_id_alloc(sid_pool_t * pool, a_uint32_t * id)
+{
+    if (pool->id_nr <= pool->id_ptr)
+    {
+        return SW_NO_RESOURCE;
+    }
+
+    if (ID_SIZE_U8 == pool->id_size)
+    {
+        a_uint8_t *p_id;
+
+        p_id = pool->id_pool;
+        *id = p_id[pool->id_ptr] + pool->id_min;
+    }
+    else if (ID_SIZE_U16 == pool->id_size)
+    {
+        a_uint16_t *p_id;
+
+        p_id = pool->id_pool;
+        *id = p_id[pool->id_ptr] + pool->id_min;
+    }
+    else
+    {
+        a_uint32_t *p_id;
+
+        p_id = pool->id_pool;
+        *id = p_id[pool->id_ptr] + pool->id_min;
+    }
+
+    pool->id_ptr++;
+    return SW_OK;
+}
+
+sw_error_t
+sid_pool_id_free(sid_pool_t * pool, a_uint32_t id)
+{
+    if (0 == pool->id_ptr)
+    {
+        return SW_FAIL;
+    }
+
+    pool->id_ptr--;
+    if (ID_SIZE_U8 == pool->id_size)
+    {
+        a_uint8_t *p_id;
+
+        if (ID_NR_IN_U8 < (id - id - pool->id_min))
+        {
+            return SW_FAIL;
+        }
+
+        p_id = pool->id_pool;
+        p_id[pool->id_ptr] = id - pool->id_min;
+    }
+    else if (ID_SIZE_U16 == pool->id_size)
+    {
+        a_uint16_t *p_id;
+
+        if (ID_NR_IN_U16 < (id - id - pool->id_min))
+        {
+            return SW_FAIL;
+        }
+
+        p_id = pool->id_pool;
+        p_id[pool->id_ptr] = id - pool->id_min;
+    }
+    else
+    {
+        a_uint32_t *p_id;
+
+        p_id = pool->id_pool;
+        p_id[pool->id_ptr] = id - pool->id_min;
+    }
+
+    return SW_OK;
+}
diff --git a/requirements2.in b/requirements2.in
new file mode 100644
index 0000000..95726dd
--- /dev/null
+++ b/requirements2.in
@@ -0,0 +1,9 @@
+Pygments==2.3.1
+Wand==0.4.4
+docutils==0.15.2
+kerberos==1.3.0
+pycrypto==2.6.1
+PyYAML==5.3
+servo==1
+sphinx_rtd_theme==0.4.3
+sublime==0.1.0
diff --git a/requirements2.txt b/requirements2.txt
new file mode 100644
index 0000000..901c014
--- /dev/null
+++ b/requirements2.txt
@@ -0,0 +1,37 @@
+#
+# This file is autogenerated by pip-compile
+# To update, run:
+#
+#    pip-compile --output-file=requirements2.txt requirements2.in
+#
+alabaster==0.7.12         # via sphinx
+babel==2.8.0              # via sphinx
+certifi==2019.11.28       # via requests
+chardet==3.0.4            # via requests
+click==3.3                # via sublime
+docutils==0.15.2
+idna==2.8                 # via requests
+imagesize==1.2.0          # via sphinx
+jinja2==2.10.3            # via sphinx
+kerberos==1.3.0
+markupsafe==1.1.1         # via jinja2
+packaging==20.0           # via sphinx
+pycrypto==2.6.1
+pygments==2.3.1
+pyparsing==2.4.6          # via packaging
+pytz==2019.3              # via babel
+pyyaml==5.3
+requests==2.22.0          # via sphinx
+servo==1
+six==1.13.0               # via packaging, sphinx
+snowballstemmer==2.0.0    # via sphinx
+sphinx==1.8.5             # via sphinx-rtd-theme
+sphinx_rtd_theme==0.4.3
+sphinxcontrib-websupport==1.1.2  # via sphinx
+sublime==0.1.0
+typing==3.7.4.1           # via sphinx
+urllib3==1.25.7           # via requests
+wand==0.4.4
+
+# The following packages are considered to be unsafe in a requirements file:
+# setuptools
diff --git a/requirements3.in b/requirements3.in
new file mode 100644
index 0000000..cf3c711
--- /dev/null
+++ b/requirements3.in
@@ -0,0 +1,8 @@
+Pygments==2.3.1
+Wand==0.4.4
+docutils==0.15.2
+kerberos==1.3.0
+pycrypto==2.6.1
+PyYAML==5.3
+servo==1
+sublime==0.1.0
diff --git a/requirements3.txt b/requirements3.txt
new file mode 100644
index 0000000..8c68261
--- /dev/null
+++ b/requirements3.txt
@@ -0,0 +1,24 @@
+#
+# This file is autogenerated by pip-compile with python 3.9
+# To update, run:
+#
+#    pip-compile --output-file=requirements3.txt requirements3.in
+#
+click==3.3
+    # via sublime
+docutils==0.15.2
+    # via -r requirements3.in
+kerberos==1.3.0
+    # via -r requirements3.in
+pycrypto==2.6.1
+    # via -r requirements3.in
+pygments==2.3.1
+    # via -r requirements3.in
+pyyaml==5.3
+    # via -r requirements3.in
+servo==1
+    # via -r requirements3.in
+sublime==0.1.0
+    # via -r requirements3.in
+wand==0.4.4
+    # via -r requirements3.in
diff --git a/tools/.gitignore b/tools/.gitignore
new file mode 100644
index 0000000..166bc07
--- /dev/null
+++ b/tools/.gitignore
@@ -0,0 +1,6 @@
+
+# Ignore general build intermediate files
+*.pyc
+
+# don't ignore .gitignore itself
+!.gitignore
diff --git a/tools/elftombn.py b/tools/elftombn.py
new file mode 100755
index 0000000..e0e5d45
--- /dev/null
+++ b/tools/elftombn.py
@@ -0,0 +1,101 @@
+# ==========================================================================
+# Copyright (c) 2017 Qualcomm Technologies, Inc.
+# All Rights Reserved.
+# Confidential and Proprietary - Qualcomm Technologies, Inc.
+# ==========================================================================
+
+from optparse import OptionParser
+import os
+import mbn_tools
+
+##############################################################################
+# main
+##############################################################################
+def main():
+	parser = OptionParser(usage='usage: %prog [options] arguments')
+
+	parser.add_option("-f", "--first_filepath",
+			action="store", type="string", dest="elf_inp_file1",
+			help="First ELF file to merge.")
+
+	parser.add_option("-o", "--output_filepath",
+			action="store", type="string", dest="binary_out",
+			help="Merged filename and path.")
+
+	parser.add_option("-v", "--mbn_version_number",
+			action="store", type="string", dest="mbnv",
+			help="Default MBN version is 3.")
+
+	parser.add_option("-c", "--com compression option",
+			action="store", type="string", dest="compress_method",
+			help="Compression method")
+
+	(options, args) = parser.parse_args()
+	if not options.elf_inp_file1:
+		parser.error('First ELF filename not given')
+
+	if not options.binary_out:
+		parser.error('Output filename not given')
+	if options.mbnv != '6':
+		mbnv = 3
+	else:
+		mbnv = 6
+
+	if options.compress_method:
+		compress_method = options.compress_method
+	else:
+		compress_method = ""
+
+	gen_dict = {}
+
+	elf_inp_file1 = options.elf_inp_file1
+
+	binary_out = options.binary_out
+
+	mbn_type = 'elf'
+	header_format = 'reg'
+	gen_dict['IMAGE_KEY_IMAGE_ID'] = mbn_tools.ImageType.SBL1_IMG
+	gen_dict['IMAGE_KEY_MBN_TYPE'] = mbn_type
+	image_header_secflag = 'non_secure'
+
+	source_base = os.path.splitext(str(binary_out))[0]
+	target_base = os.path.splitext(str(binary_out))[0]
+	source_elf = source_base + "_nohash.elf"
+	target_hash = target_base + ".hash"
+	target_hash_hd = target_base + "_hash.hd"
+	target_phdr_elf = target_base + "_phdr.pbn"
+	target_nonsec = target_base + "_combined_hash.mbn"
+
+	# Create hash table
+	rv = mbn_tools.pboot_gen_elf([],
+			elf_inp_file1,
+			target_hash,
+			compress_method,
+			elf_out_file_name = target_phdr_elf,
+			secure_type = image_header_secflag,
+			mbn_version = mbnv)
+	if rv:
+		raise RuntimeError("Failed to run pboot_gen_elf")
+
+	# Create hash table header
+	rv = mbn_tools.image_header([],
+			gen_dict,
+			target_hash,
+			target_hash_hd,
+			image_header_secflag,
+			elf_file_name = target_phdr_elf,
+			mbn_version = mbnv)
+	if rv:
+		raise RuntimeError("Failed to create image header for hash segment")
+
+	files_to_cat_in_order = [target_hash_hd, target_hash]
+	mbn_tools.concat_files (target_nonsec, files_to_cat_in_order)
+
+	# Add the hash segment into the ELF
+	mbn_tools.pboot_add_hash([],
+			target_phdr_elf,
+			target_nonsec, binary_out)
+
+	return
+
+main()
diff --git a/tools/mbn_tools.py b/tools/mbn_tools.py
new file mode 100755
index 0000000..22bd646
--- /dev/null
+++ b/tools/mbn_tools.py
@@ -0,0 +1,2371 @@
+#===============================================================================
+#
+# MBN TOOLS
+#
+# GENERAL DESCRIPTION
+#    Contains all MBN Utilities for image generation
+#
+# Copyright (c) 2010-2013, 2017 Qualcomm Technologies, Inc.
+# All Rights Reserved.
+# Confidential and Proprietary - Qualcomm Technologies, Inc.
+#
+#-------------------------------------------------------------------------------
+#                      EDIT HISTORY FOR FILE
+#
+#  This section contains comments describing changes made to the module.
+#  Notice that changes are listed in reverse chronological order.
+#
+# when       who     what, where, why
+# --------   ---     ---------------------------------------------------------
+# 04/11/17   an      Updated Copyright
+# 06/06/13   yliong  CR 497042: Signed and encrypted image is corrupted. MRC features.
+# 03/18/13   dhaval  Add support for hashing elf segments with SHA256 and
+#                    sync up to mpss, adsp mbn-tools
+# 01/14/13   kedara  Remove dependency on .builds, cust<bid>.h, targ<bid>.h files
+# 08/30/12   kedara  Add virtual block suppport
+# 02/24/12   dh      Add ssd side effect file names
+# 07/08/11   aus     Added support for image_id in SBL image header as required by PBL
+#                    Sahara mode
+# 10/20/11   dxiang  Clean up
+#===============================================================================
+
+import stat
+import csv
+import itertools
+import struct
+import os
+import subprocess
+import shutil
+import hashlib
+
+#----------------------------------------------------------------------------
+# GLOBAL VARIABLES BEGIN
+#----------------------------------------------------------------------------
+PAD_BYTE_1                = 255             # Padding byte 1s
+PAD_BYTE_0                = 0               # Padding byte 0s
+SHA256_SIGNATURE_SIZE     = 256             # Support SHA256
+MAX_NUM_ROOT_CERTS        = 4               # Maximum number of OEM root certificates
+MI_BOOT_IMG_HDR_SIZE      = 40              # sizeof(mi_boot_image_header_type)
+MI_BOOT_IMG_HDR_SIZE_V6   = 48              # V6 sizeof(mi_boot_image_header_type)
+MI_BOOT_SBL_HDR_SIZE      = 80              # sizeof(sbl_header)
+BOOT_HEADER_LENGTH        = 20              # Boot Header Number of Elements
+SBL_HEADER_LENGTH         = 20              # SBL Header Number of Elements
+FLASH_PARTI_VERSION       = 3               # Flash Partition Version Number
+FLASH_PARTI_VERSION_V6    = 6               # V6 Flash Partition Version Number
+MAX_PHDR_COUNT            = 100             # Maximum allowable program headers
+CERT_CHAIN_ONEROOT_MAXSIZE = 6*1024          # Default Cert Chain Max Size for one root
+VIRTUAL_BLOCK_SIZE        = 131072          # Virtual block size for MCs insertion in SBL1 if ENABLE_VIRTUAL_BLK ON
+MAGIC_COOKIE_LENGTH       = 12              # Length of magic Cookie inserted per VIRTUAL_BLOCK_SIZE
+MIN_IMAGE_SIZE_WITH_PAD   = 256*1024        # Minimum image size for sbl1 Nand based OTA feature
+
+SBL_AARCH64               = 0xF             # Indicate that SBL is a Aarch64 image
+SBL_AARCH32               = 0x0             # Indicate that SBL is a Aarch32 image
+
+# Magic numbers filled in for boot headers
+FLASH_CODE_WORD                       = 0x844BDCD1
+UNIFIED_BOOT_COOKIE_MAGIC_NUMBER      = 0x33836685
+MAGIC_NUM                             = 0x73D71034
+AUTODETECT_PAGE_SIZE_MAGIC_NUM        = 0x7D0B435A
+AUTODETECT_PAGE_SIZE_MAGIC_NUM64      = 0x7D0B5436
+AUTODETECT_PAGE_SIZE_MAGIC_NUM128     = 0x7D0B6577
+SBL_VIRTUAL_BLOCK_MAGIC_NUM           = 0xD48B54C6
+
+# ELF Definitions
+ELF_HDR_COMMON_SIZE       = 24
+ELF32_HDR_SIZE            = 52
+ELF32_PHDR_SIZE           = 32
+ELF64_HDR_SIZE            = 64
+ELF64_PHDR_SIZE           = 56
+ELFINFO_MAG0_INDEX        = 0
+ELFINFO_MAG1_INDEX        = 1
+ELFINFO_MAG2_INDEX        = 2
+ELFINFO_MAG3_INDEX        = 3
+ELFINFO_MAG0              = 127 # 0x7F
+ELFINFO_MAG1              = 69  # E
+ELFINFO_MAG2              = 76  # L
+ELFINFO_MAG3              = 70  # F
+ELFINFO_CLASS_INDEX       = 4
+ELFINFO_CLASS_32          = 1
+ELFINFO_CLASS_64          = 2
+ELFINFO_VERSION_INDEX     = 6
+ELFINFO_VERSION_CURRENT   = 1
+ELF_BLOCK_ALIGN           = 0x1000
+ALIGNVALUE_1MB             = 0x100000
+ALIGNVALUE_4MB             = 0x400000
+
+# ELF Program Header Types
+NULL_TYPE                 = 0x0
+LOAD_TYPE                 = 0x1
+DYNAMIC_TYPE              = 0x2
+INTERP_TYPE               = 0x3
+NOTE_TYPE                 = 0x4
+SHLIB_TYPE                = 0x5
+PHDR_TYPE                 = 0x6
+TLS_TYPE                  = 0x7
+PHDR_ENTR_TYPE            = 0x64000001
+outputdir = "/bin/gzip"
+
+
+"""
+The eight bits between 20 and 27 in the p_flags field in ELF program headers
+is not used by the standard ELF format. We use this byte to hold OS and processor
+specific fields as recommended by ARM.
+
+The bits in this byte are defined as follows:
+
+                   Pool Indx    Segment type     Access type    Page/non page
+  bits in p_flags /-----27-----/----26-24-------/---- 23-21----/------20-------/
+
+After parsing segment description strings in the SCL file, the appropriate segment
+flag values are chosen from the follow definitions. The mask defined below is then
+used to update the existing p_flags field in the program headers with the updated
+values.
+"""
+# Mask for bits 20-27 to parse program header p_flags
+MI_PBT_FLAGS_MASK = 0x0FF00000
+
+# Helper defines to help parse ELF program headers
+MI_PROG_BOOT_DIGEST_SIZE              = 20
+MI_PBT_FLAG_SEGMENT_TYPE_MASK         = 0x07000000
+MI_PBT_FLAG_SEGMENT_TYPE_SHIFT        = 0x18
+MI_PBT_FLAG_PAGE_MODE_MASK            = 0x00100000
+MI_PBT_FLAG_PAGE_MODE_SHIFT           = 0x14
+MI_PBT_FLAG_ACCESS_TYPE_MASK          = 0x00E00000
+MI_PBT_FLAG_ACCESS_TYPE_SHIFT         = 0x15
+MI_PBT_FLAG_POOL_INDEX_MASK           = 0x08000000
+MI_PBT_FLAG_POOL_INDEX_SHIFT          = 0x1B
+
+# Segment Type
+MI_PBT_L4_SEGMENT                     = 0x0
+MI_PBT_AMSS_SEGMENT                   = 0x1
+MI_PBT_HASH_SEGMENT                   = 0x2
+MI_PBT_BOOT_SEGMENT                   = 0x3
+MI_PBT_L4BSP_SEGMENT                  = 0x4
+MI_PBT_SWAPPED_SEGMENT                = 0x5
+MI_PBT_SWAP_POOL_SEGMENT              = 0x6
+MI_PBT_PHDR_SEGMENT                   = 0x7
+
+# Page/Non-Page Type
+MI_PBT_NON_PAGED_SEGMENT              = 0x0
+MI_PBT_PAGED_SEGMENT                  = 0x1
+
+# Access Type
+MI_PBT_RW_SEGMENT                     = 0x0
+MI_PBT_RO_SEGMENT                     = 0x1
+MI_PBT_ZI_SEGMENT                     = 0x2
+MI_PBT_NOTUSED_SEGMENT                = 0x3
+MI_PBT_SHARED_SEGMENT                 = 0x4
+
+# ELF Segment Flag Definitions
+MI_PBT_ELF_AMSS_NON_PAGED_RO_SEGMENT  = 0x01200000
+MI_PBT_ELF_AMSS_PAGED_RO_SEGMENT  = 0x01300000
+MI_PBT_ELF_SWAP_POOL_NON_PAGED_ZI_SEGMENT_INDEX0 = 0x06400000
+MI_PBT_ELF_SWAPPED_PAGED_RO_SEGMENT_INDEX0 = 0x05300000
+MI_PBT_ELF_SWAP_POOL_NON_PAGED_ZI_SEGMENT_INDEX1 = 0x0E400000
+MI_PBT_ELF_SWAPPED_PAGED_RO_SEGMENT_INDEX1 = 0x0D300000
+MI_PBT_ELF_AMSS_NON_PAGED_ZI_SEGMENT = 0x01400000
+MI_PBT_ELF_AMSS_PAGED_ZI_SEGMENT = 0x01500000
+MI_PBT_ELF_AMSS_NON_PAGED_RW_SEGMENT = 0x01000000
+MI_PBT_ELF_AMSS_PAGED_RW_SEGMENT = 0x01100000
+MI_PBT_ELF_AMSS_NON_PAGED_NOTUSED_SEGMENT = 0x01600000
+MI_PBT_ELF_AMSS_PAGED_NOTUSED_SEGMENT = 0x01700000
+MI_PBT_ELF_AMSS_NON_PAGED_SHARED_SEGMENT = 0x01800000
+MI_PBT_ELF_AMSS_PAGED_SHARED_SEGMENT = 0x01900000
+MI_PBT_ELF_HASH_SEGMENT = 0x02200000
+MI_PBT_ELF_BOOT_SEGMENT = 0x03200000
+MI_PBT_ELF_PHDR_SEGMENT = 0x07000000
+MI_PBT_ELF_NON_PAGED_L4BSP_SEGMENT = 0x04000000
+MI_PBT_ELF_PAGED_L4BSP_SEGMENT = 0x04100000
+MI_PBT_ELF_AMSS_RELOCATABLE_IMAGE = 0x8000000
+
+#----------------------------------------------------------------------------
+# GLOBAL VARIABLES END
+#----------------------------------------------------------------------------
+
+#----------------------------------------------------------------------------
+# CLASS DEFINITIONS BEGIN
+#----------------------------------------------------------------------------
+#----------------------------------------------------------------------------
+# OS Type ID Class
+#----------------------------------------------------------------------------
+class OSType:
+    BMP_BOOT_OS        = 0
+    WM_BOOT_OS         = 1
+    ANDROID_BOOT_OS    = 2
+    CHROME_BOOT_OS     = 3
+    SYMBIAN_BOOT_OS    = 4
+    LINUX_BOOT_OS      = 5
+
+#----------------------------------------------------------------------------
+# Image Type ID Class - These values must be kept consistent with mibib.h
+#----------------------------------------------------------------------------
+class ImageType:
+   NONE_IMG           = 0
+   OEM_SBL_IMG        = 1
+   AMSS_IMG           = 2
+   QCSBL_IMG          = 3
+   HASH_IMG           = 4
+   APPSBL_IMG         = 5
+   APPS_IMG           = 6
+   HOSTDL_IMG         = 7
+   DSP1_IMG           = 8
+   FSBL_IMG           = 9
+   DBL_IMG            = 10
+   OSBL_IMG           = 11
+   DSP2_IMG           = 12
+   EHOSTDL_IMG        = 13
+   NANDPRG_IMG        = 14
+   NORPRG_IMG         = 15
+   RAMFS1_IMG         = 16
+   RAMFS2_IMG         = 17
+   ADSP_Q5_IMG        = 18
+   APPS_KERNEL_IMG    = 19
+   BACKUP_RAMFS_IMG   = 20
+   SBL1_IMG           = 21
+   SBL2_IMG           = 22
+   RPM_IMG            = 23
+   SBL3_IMG           = 24
+   TZ_IMG             = 25
+   PSI_IMG            = 32
+
+#----------------------------------------------------------------------------
+# Global Image Type Table
+# Format of the look-up table:
+# KEY -  IMAGE_TYPE string as passed into mbn_builder.py
+# VALUE - [Specific ImageType ID enum, Template key string, MBN Type]
+#----------------------------------------------------------------------------
+image_id_table = {
+   'appsbl': [ImageType.APPSBL_IMG, 'APPSBL_IMG', 'bin'],
+   'dbl': [ImageType.DBL_IMG, 'DBL_IMG', 'bin'],
+   'osbl': [ImageType.OSBL_IMG, 'OSBL_IMG', 'bin'],
+   'amss': [ImageType.AMSS_IMG, 'AMSS_IMG', 'elf'],
+   'amss_mbn': [ImageType.HASH_IMG, 'HASH_IMG', 'elf'],
+   'apps': [ImageType.APPS_IMG, 'APPS_IMG', 'bin'],
+   'hostdl': [ImageType.HOSTDL_IMG, 'HOSTDL_IMG', 'bin'],
+   'ehostdl': [ImageType.EHOSTDL_IMG, 'EHOSTDL_IMG', 'bin'],
+   'emmcbld': [ImageType.EHOSTDL_IMG, 'EMMCBLD_IMG', 'bin'],
+   'qdsp6fw': [ImageType.DSP1_IMG, 'DSP1_IMG', 'elf'],
+   'qdsp6sw': [ImageType.DSP2_IMG, 'DSP2_IMG', 'elf'],
+   'qdsp5': [ImageType.ADSP_Q5_IMG, 'ADSP_Q5_IMG', 'bin'],
+   'tz': [ImageType.TZ_IMG, 'TZ_IMG', 'elf'],
+   'tz_rumi': [ImageType.TZ_IMG, 'TZ_IMG', 'elf'],
+   'tz_virtio': [ImageType.TZ_IMG, 'TZ_IMG', 'elf'],
+   'tzbsp_no_xpu': [ImageType.TZ_IMG, 'TZ_IMG', 'elf'],
+   'tzbsp_with_test': [ImageType.TZ_IMG, 'TZ_IMG', 'elf'],
+   'rpm': [ImageType.RPM_IMG, 'RPM_IMG', 'elf'],
+   'sbl1': [ImageType.SBL1_IMG, 'SBL1_IMG', 'bin'],
+   'sbl2': [ImageType.SBL2_IMG, 'SBL2_IMG', 'bin'],
+   'sbl3': [ImageType.SBL3_IMG, 'SBL3_IMG', 'bin'],
+   'efs1': [ImageType.RAMFS1_IMG, 'RAMFS1_IMG', 'bin'],
+   'efs2': [ImageType.RAMFS2_IMG, 'RAMFS2_IMG', 'bin'],
+   'pmic': [ImageType.PSI_IMG, 'PSI_IMG', 'elf'],
+   # DO NOT add any additional image information
+}
+
+#----------------------------------------------------------------------------
+# Header Class Notes:
+# In order to properly read and write the header structures as binary data,
+# the Python Struct library is used to align and package up the header objects
+# All Struct objects are initialized by a special string with the following
+# notation. These structure objects are then used to decode binary data in order
+# to fill out the appropriate class in Python, or they are used to package up
+# the Python class so that we may write the binary data out.
+#----------------------------------------------------------------------------
+"""
+      Format | C Type         | Python Type | Standard Size
+      -----------------------------------------------------
+    1) 'X's  | char *         | string      | 'X' bytes
+    2) H     | unsigned short | integer     | 2 bytes
+    3) I     | unsigned int   | integer     | 4 bytes
+
+"""
+
+#----------------------------------------------------------------------------
+# ELF Header Class
+#----------------------------------------------------------------------------
+class Elf_Ehdr_common:
+   # Structure object to align and package the ELF Header
+   s = struct.Struct('16sHHI')
+
+   def __init__(self, data):
+      unpacked_data       = (Elf_Ehdr_common.s).unpack(data)
+      self.unpacked_data  = unpacked_data
+      self.e_ident        = unpacked_data[0]
+      self.e_type         = unpacked_data[1]
+      self.e_machine      = unpacked_data[2]
+      self.e_version      = unpacked_data[3]
+
+   def printValues(self):
+      print("ATTRIBUTE / VALUE")
+      for attr, value in self.__dict__.iteritems():
+         print(attr, value)
+
+
+
+#----------------------------------------------------------------------------
+# ELF Header Class
+#----------------------------------------------------------------------------
+class Elf32_Ehdr:
+   # Structure object to align and package the ELF Header
+   s = struct.Struct('16sHHIIIIIHHHHHH')
+
+   def __init__(self, data):
+      unpacked_data       = (Elf32_Ehdr.s).unpack(data)
+      self.unpacked_data  = unpacked_data
+      self.e_ident        = unpacked_data[0]
+      self.e_type         = unpacked_data[1]
+      self.e_machine      = unpacked_data[2]
+      self.e_version      = unpacked_data[3]
+      self.e_entry        = unpacked_data[4]
+      self.e_phoff        = unpacked_data[5]
+      self.e_shoff        = unpacked_data[6]
+      self.e_flags        = unpacked_data[7]
+      self.e_ehsize       = unpacked_data[8]
+      self.e_phentsize    = unpacked_data[9]
+      self.e_phnum        = unpacked_data[10]
+      self.e_shentsize    = unpacked_data[11]
+      self.e_shnum        = unpacked_data[12]
+      self.e_shstrndx     = unpacked_data[13]
+
+   def printValues(self):
+      print("ATTRIBUTE / VALUE")
+      for attr, value in self.__dict__.iteritems():
+         print(attr, value)
+
+   def getPackedData(self):
+      values = [self.e_ident,
+                self.e_type,
+                self.e_machine,
+                self.e_version,
+                self.e_entry,
+                self.e_phoff,
+                self.e_shoff,
+                self.e_flags,
+                self.e_ehsize,
+                self.e_phentsize,
+                self.e_phnum,
+                self.e_shentsize,
+                self.e_shnum,
+                self.e_shstrndx
+               ]
+
+      return (Elf32_Ehdr.s).pack(*values)
+
+#----------------------------------------------------------------------------
+# ELF Program Header Class
+#----------------------------------------------------------------------------
+class Elf32_Phdr:
+
+   # Structure object to align and package the ELF Program Header
+   s = struct.Struct('I' * 8)
+
+   def __init__(self, data):
+      unpacked_data       = (Elf32_Phdr.s).unpack(data)
+      self.unpacked_data  = unpacked_data
+      self.p_type         = unpacked_data[0]
+      self.p_offset       = unpacked_data[1]
+      self.p_vaddr        = unpacked_data[2]
+      self.p_paddr        = unpacked_data[3]
+      self.p_filesz       = unpacked_data[4]
+      self.p_memsz        = unpacked_data[5]
+      self.p_flags        = unpacked_data[6]
+      self.p_align        = unpacked_data[7]
+
+   def printValues(self):
+      print("ATTRIBUTE / VALUE")
+      for attr, value in self.__dict__.iteritems():
+         print(attr, value)
+
+   def getPackedData(self):
+      values = [self.p_type,
+                self.p_offset,
+                self.p_vaddr,
+                self.p_paddr,
+                self.p_filesz,
+                self.p_memsz,
+                self.p_flags,
+                self.p_align
+               ]
+
+      return (Elf32_Phdr.s).pack(*values)
+
+#----------------------------------------------------------------------------
+# ELF Header Class
+#----------------------------------------------------------------------------
+class Elf64_Ehdr:
+   # Structure object to align and package the ELF Header
+   s = struct.Struct('16sHHIQQQIHHHHHH')
+
+   def __init__(self, data):
+      unpacked_data       = (Elf64_Ehdr.s).unpack(data)
+      self.unpacked_data  = unpacked_data
+      self.e_ident        = unpacked_data[0]
+      self.e_type         = unpacked_data[1]
+      self.e_machine      = unpacked_data[2]
+      self.e_version      = unpacked_data[3]
+      self.e_entry        = unpacked_data[4]
+      self.e_phoff        = unpacked_data[5]
+      self.e_shoff        = unpacked_data[6]
+      self.e_flags        = unpacked_data[7]
+      self.e_ehsize       = unpacked_data[8]
+      self.e_phentsize    = unpacked_data[9]
+      self.e_phnum        = unpacked_data[10]
+      self.e_shentsize    = unpacked_data[11]
+      self.e_shnum        = unpacked_data[12]
+      self.e_shstrndx     = unpacked_data[13]
+
+   def printValues(self):
+      print("ATTRIBUTE / VALUE")
+      for attr, value in self.__dict__.iteritems():
+         print(attr, value)
+
+   def getPackedData(self):
+      values = [self.e_ident,
+                self.e_type,
+                self.e_machine,
+                self.e_version,
+                self.e_entry,
+                self.e_phoff,
+                self.e_shoff,
+                self.e_flags,
+                self.e_ehsize,
+                self.e_phentsize,
+                self.e_phnum,
+                self.e_shentsize,
+                self.e_shnum,
+                self.e_shstrndx
+               ]
+
+      return (Elf64_Ehdr.s).pack(*values)
+
+#----------------------------------------------------------------------------
+# ELF Program Header Class
+#----------------------------------------------------------------------------
+class Elf64_Phdr:
+
+   # Structure object to align and package the ELF Program Header
+   s = struct.Struct('IIQQQQQQ')
+
+   def __init__(self, data):
+      unpacked_data       = (Elf64_Phdr.s).unpack(data)
+      self.unpacked_data  = unpacked_data
+      self.p_type         = unpacked_data[0]
+      self.p_flags        = unpacked_data[1]
+      self.p_offset       = unpacked_data[2]
+      self.p_vaddr        = unpacked_data[3]
+      self.p_paddr        = unpacked_data[4]
+      self.p_filesz       = unpacked_data[5]
+      self.p_memsz        = unpacked_data[6]
+      self.p_align        = unpacked_data[7]
+
+   def printValues(self):
+      print("ATTRIBUTE / VALUE")
+      for attr, value in self.__dict__.iteritems():
+         print(attr, value)
+
+   def getPackedData(self):
+      values = [self.p_type,
+                self.p_flags,
+                self.p_offset,
+                self.p_vaddr,
+                self.p_paddr,
+                self.p_filesz,
+                self.p_memsz,
+                self.p_align
+               ]
+
+      return (Elf64_Phdr.s).pack(*values)
+
+
+#----------------------------------------------------------------------------
+# ELF Segment Information Class
+#----------------------------------------------------------------------------
+class SegmentInfo:
+   def __init__(self):
+      self.flag  = 0
+      self.start_addr = 0
+   def printValues(self):
+      print('Flag: ' + str(self.flag))
+      print('Start Address: ' + str(hex(self.start_addr)))
+
+#----------------------------------------------------------------------------
+# Regular Boot Header Class
+#----------------------------------------------------------------------------
+class Boot_Hdr:
+   def __init__(self, init_val):
+      self.image_id = ImageType.NONE_IMG
+      self.flash_parti_ver = FLASH_PARTI_VERSION
+      self.image_src = init_val
+      self.image_dest_ptr = init_val
+      self.image_size = init_val
+      self.code_size = init_val
+      self.sig_ptr = init_val
+      self.sig_size = init_val
+      self.cert_chain_ptr = init_val
+      self.cert_chain_size = init_val
+      self.magic_number1 = init_val
+      self.version = init_val
+      self.OS_type = init_val
+      self.boot_apps_parti_entry = init_val
+      self.boot_apps_size_entry = init_val
+      self.boot_apps_ram_loc = init_val
+      self.reserved_ptr = init_val
+      self.reserved_1 = init_val
+      self.reserved_2 = init_val
+      self.reserved_3 = init_val
+
+   def getLength(self):
+      return BOOT_HEADER_LENGTH
+
+   def writePackedData(self, target, write_full_hdr):
+      values = [self.image_id,
+                self.flash_parti_ver,
+                self.image_src,
+                self.image_dest_ptr,
+                self.image_size,
+                self.code_size ,
+                self.sig_ptr,
+                self.sig_size,
+                self.cert_chain_ptr,
+                self.cert_chain_size,
+                self.magic_number1,
+                self.version,
+                self.OS_type,
+                self.boot_apps_parti_entry,
+                self.boot_apps_size_entry,
+                self.boot_apps_ram_loc,
+                self.reserved_ptr,
+                self.reserved_1,
+                self.reserved_2,
+                self.reserved_3 ]
+
+      # Write 10 entries(40B) or 20 entries(80B) of boot header
+      if write_full_hdr is False:
+         s = struct.Struct('I'* 10)
+         values = values[:10]
+      else:
+         s = struct.Struct('I' * self.getLength())
+
+      packed_data = s.pack(*values)
+
+      fp = OPEN(target,'wb')
+      fp.write(packed_data)
+      fp.close()
+
+      return s.size
+
+#----------------------------------------------------------------------------
+# V6 Regular Boot Header Class
+#----------------------------------------------------------------------------
+class Boot_Hdr_V6:
+   def __init__(self, init_val):
+      self.image_id = ImageType.NONE_IMG
+      self.flash_parti_ver = FLASH_PARTI_VERSION_V6
+      self.qti_sig_size = init_val
+      self.qti_cert_chain_size = init_val
+      self.image_size = init_val
+      self.code_size = init_val
+      self.sig_ptr = init_val
+      self.sig_size = init_val
+      self.cert_chain_ptr = init_val
+      self.cert_chain_size = init_val
+      self.oem_metadata_size = init_val
+      self.qti_metadata_size = init_val
+      self.magic_number1 = init_val
+      self.version = init_val
+      self.OS_type = init_val
+      self.boot_apps_parti_entry = init_val
+      self.boot_apps_size_entry = init_val
+      self.boot_apps_ram_loc = init_val
+      self.reserved_ptr = init_val
+      self.reserved_1 = init_val
+      self.reserved_2 = init_val
+      self.reserved_3 = init_val
+
+   def getLength(self):
+      return BOOT_HEADER_LENGTH
+
+   def writePackedData(self, target, write_full_hdr):
+      values = [self.image_id,
+                self.flash_parti_ver,
+                self.qti_sig_size,
+                self.qti_cert_chain_size,
+                self.image_size,
+                self.code_size ,
+                self.sig_ptr,
+                self.sig_size,
+                self.cert_chain_ptr,
+                self.cert_chain_size,
+                self.oem_metadata_size,
+                self.qti_metadata_size,
+                self.magic_number1,
+                self.version,
+                self.OS_type,
+                self.boot_apps_parti_entry,
+                self.boot_apps_size_entry,
+                self.boot_apps_ram_loc,
+                self.reserved_ptr,
+                self.reserved_1,
+                self.reserved_2,
+                self.reserved_3 ]
+
+      # Write 12 entries(48B) or 20 entries(80B) of boot header
+      if write_full_hdr is False:
+         s = struct.Struct('I'* 12)
+         values = values[:12]
+      else:
+         s = struct.Struct('I' * self.getLength())
+
+      packed_data = s.pack(*values)
+
+      fp = OPEN(target,'wb')
+      fp.write(packed_data)
+      fp.close()
+
+      return s.size
+
+#----------------------------------------------------------------------------
+# SBL Boot Header Class
+#----------------------------------------------------------------------------
+class Sbl_Hdr:
+   def __init__(self, init_val):
+      self.codeword = init_val
+      self.magic = init_val
+      self.image_id = init_val
+      self.reserved_1 = init_val
+      self.reserved_2 = init_val
+      self.image_src = init_val
+      self.image_dest_ptr = init_val
+      self.image_size = init_val
+      self.code_size = init_val
+      self.sig_ptr = init_val
+      self.sig_size = init_val
+      self.cert_chain_ptr = init_val
+      self.cert_chain_size = init_val
+      self.oem_root_cert_sel = init_val
+      self.oem_num_root_certs = init_val
+      self.booting_image_config = init_val
+      self.reserved_6 = init_val
+      self.reserved_7 = init_val
+      self.reserved_8 = init_val
+      self.reserved_9 = init_val
+
+   def getLength(self):
+      return SBL_HEADER_LENGTH
+
+   def writePackedData(self, target):
+      values = [self.codeword,
+                self.magic,
+                self.image_id,
+                self.reserved_1,
+                self.reserved_2,
+                self.image_src,
+                self.image_dest_ptr,
+                self.image_size,
+                self.code_size,
+                self.sig_ptr,
+                self.sig_size,
+                self.cert_chain_ptr,
+                self.cert_chain_size,
+                self.oem_root_cert_sel,
+                self.oem_num_root_certs,
+                self.booting_image_config,
+                self.reserved_6,
+                self.reserved_7,
+                self.reserved_8,
+                self.reserved_9 ]
+
+      s = struct.Struct('I' * self.getLength())
+      packed_data = s.pack(*values)
+
+      fp = OPEN(target,'wb')
+      fp.write(packed_data)
+      fp.close()
+
+      return s.size
+
+#----------------------------------------------------------------------------
+# CLASS DEFINITIONS END
+#----------------------------------------------------------------------------
+
+#------------------------------------------------------------------------------
+# Hooks for Scons
+#------------------------------------------------------------------------------
+def exists(env):
+   return env.Detect('mbn_tools')
+
+def generate(env):
+
+   #----------------------------------------------------------------------------
+   # Generate Global Dictionary
+   #----------------------------------------------------------------------------
+   generate_global_dict(env)
+
+   #----------------------------------------------------------------------------
+   # Assign Build Configurable Values
+   #----------------------------------------------------------------------------
+   init_build_vars(env)
+
+   #----------------------------------------------------------------------------
+   # Add Methods to Environment
+   #----------------------------------------------------------------------------
+   env.AddMethod(filter_dictionary, "FilterDictionary")
+   env.AddMethod(image_auth, "ImageAuth")
+   env.AddMethod(image_header, "ImageHeader")
+   env.AddMethod(pboot_gen_elf, "PBootGenElf")
+   env.AddMethod(pboot_add_hash, "PBootAddHash")
+   env.AddMethod(modify_elf_flags, "ModifyElfFlags")
+   env.AddMethod(generate_code_hash, "GenerateCodeHash")
+   env.AddMethod(insert_SBL1_magicCookie, "InsertSBLMagicCookie")
+   env.AddMethod(modify_relocatable_flags, "ModifyRelocatableFlags")
+
+   #----------------------------------------------------------------------------
+   # Load Encryption Tools and Methods if required
+   #----------------------------------------------------------------------------
+   if 'USES_ENCRYPT_MBN' in env:
+      # Add Encryption Tools to environment
+      env.Tool('pil_encrypt', toolpath = ['${BUILD_ROOT}/core/securemsm/ssd/tools/pil_encrypt'])
+      env.AddMethod(get_ssd_se_fname, "GetSSDSideEffectFileName")
+      env.AddMethod(encrypt_elf_segments, "EncryptElfSegments")
+      env.AddMethod(generate_meta_data, "GenerateMetaData")
+      env.AddMethod(encrypt_mbn, "EncryptMBN")
+   return None
+
+#----------------------------------------------------------------------------
+# BOOT TOOLS BEGIN
+#----------------------------------------------------------------------------
+
+#----------------------------------------------------------------------------
+# generate_meta_data
+#----------------------------------------------------------------------------
+def generate_meta_data(env, meta_out_file_name, add_magic_num = False):
+
+   '''
+   Make call to SSD API to return buffer filled with XML header information.
+   The XML header which we write contains information regarding the algorithms
+   being used along with specific key values which are to be used for encrpytion.
+   '''
+   xml_header = env.SSDGetMetaData(add_magic_num)
+
+   # Initialize
+   xml_target_file = open(meta_out_file_name,'wb')
+   xml_header_size = len(xml_header)
+
+   # Write XML buffer into target file
+   xml_target_file.write(xml_header)
+
+   # Pad if necessary to the maximum size
+   if xml_header_size <= XML_HEADER_MAXSIZE:
+      bytes_to_pad = XML_HEADER_MAXSIZE - xml_header_size
+      pad_file(xml_target_file, bytes_to_pad, PAD_BYTE_1)
+      xml_target_file.close()
+   else:
+      xml_target_file.close()
+      raise RuntimeError("XML Size too large: " + str(xml_header_size))
+
+#----------------------------------------------------------------------------
+# encrypt_mbn
+#----------------------------------------------------------------------------
+def encrypt_mbn(env, mbn_in_file_name, mbn_out_file_name):
+    # Open Files
+    mbn_in_fp = OPEN(mbn_in_file_name, "rb")
+    mbn_out_fp = OPEN(mbn_out_file_name, "wb+")
+
+    # encrypt the input file content and write to output file
+    mbn_file_size = os.path.getsize(mbn_in_file_name)
+    file_buff = mbn_in_fp.read(mbn_file_size)
+    encrypted_buf = env.SSDEncryptSegment(0, file_buff, mbn_file_size)
+    mbn_out_fp.write(encrypted_buf)
+
+    # Close Files
+    mbn_in_fp.close()
+    mbn_out_fp.close()
+
+    # Clean up encryption files
+    env.SSDDeInit()
+
+#----------------------------------------------------------------------------
+# get_ssd_se_fname
+#----------------------------------------------------------------------------
+def get_ssd_se_fname(env):
+   return env.SSDGetSideEffectFileName()
+
+#----------------------------------------------------------------------------
+# encrypt_elf_segments
+#----------------------------------------------------------------------------
+def encrypt_elf_segments(env, elf_in_file_name,
+                              elf_out_file_name):
+
+   # Open Files
+   elf_in_fp = OPEN(elf_in_file_name, "rb")
+   elf_out_fp = OPEN(elf_out_file_name, "wb+")
+
+   # Initialize
+   [elf_header, phdr_table] = preprocess_elf_file(elf_in_file_name)
+   encrypted_seg_counter = 0
+
+   # Copy input file to output file
+   shutil.copyfileobj(elf_in_fp, elf_out_fp, os.path.getsize(elf_in_file_name))
+
+   # Begin ELF segment encryption
+   for i in range(elf_header.e_phnum):
+      curr_phdr = phdr_table[i]
+
+      # Only encrypt segments of LOAD_TYPE. Do not encrypt the hash segment.
+      if curr_phdr.p_type == LOAD_TYPE and \
+         MI_PBT_SEGMENT_TYPE_VALUE(curr_phdr.p_flags) != MI_PBT_HASH_SEGMENT:
+
+         # Read full segment into buffer
+         elf_in_fp.seek(curr_phdr.p_offset)
+         data_len = curr_phdr.p_filesz
+         file_buff = elf_in_fp.read(data_len)
+
+         # Call encryption routine on buffer
+         encrypted_buf = env.SSDEncryptSegment(encrypted_seg_counter, file_buff, data_len)
+         encrypted_seg_counter += 1
+
+         # Write encrypted segment into output file in same location
+         elf_out_fp.seek(curr_phdr.p_offset)
+         elf_out_fp.write(encrypted_buf)
+
+   # Close Files
+   elf_in_fp.close()
+   elf_out_fp.close()
+
+   # Clean up encryption files
+   env.SSDDeInit()
+
+#----------------------------------------------------------------------------
+# image_header
+#----------------------------------------------------------------------------
+def image_header(env, gen_dict,
+                      code_file_name,
+                      output_file_name,
+                      secure_type,
+                      header_format = 'reg',
+                      requires_preamble = False,
+                      preamble_file_name = None,
+                      elf_file_name = None,
+                      write_full_hdr = False,
+                      in_code_size = None,
+                      cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE,
+                      num_of_pages = None,
+                      mbn_version = None):
+
+   # Preliminary checks
+   if (requires_preamble is True) and (preamble_file_name is None):
+      raise RuntimeError("Image Header requires a preamble file")
+
+   if (gen_dict['IMAGE_KEY_MBN_TYPE'] == 'elf') and (elf_file_name is None):
+      raise RuntimeError("ELF Image Headers require an elf file")
+
+   if (in_code_size is None) and (os.path.exists(code_file_name) is False):
+      raise RuntimeError("Code size unavailable, and input file does not exist")
+
+   # Initialize
+   if in_code_size is not None:
+      code_size = in_code_size
+   else:
+      code_size = os.path.getsize(code_file_name)
+
+   image_dest = 0
+   image_source = 0
+
+   # If secure build, set signature and cert chain sizes
+   if secure_type == 'secure':
+      signature_size = SHA256_SIGNATURE_SIZE
+      cert_chain_size = cert_chain_size_in
+      image_size = code_size + cert_chain_size + signature_size
+      if (image_size % 4) != 0:
+         image_size += (4 - (image_size % 4))
+   else:
+      signature_size = 0
+      cert_chain_size = 0
+      image_size = code_size
+
+   # For ELF or hashed images, image destination will be determined from an ELF input file
+   if gen_dict['IMAGE_KEY_MBN_TYPE'] == 'elf':
+      image_dest = get_hash_address(elf_file_name) + MI_BOOT_IMG_HDR_SIZE
+   elif gen_dict['IMAGE_KEY_MBN_TYPE'] == 'bin':
+      image_dest = gen_dict['IMAGE_KEY_IMAGE_DEST']
+      image_source = gen_dict['IMAGE_KEY_IMAGE_SOURCE']
+
+   # Build the header based on format specified
+   if header_format == 'sbl':
+      boot_sbl_header = Sbl_Hdr(init_val = int('0xFFFFFFFF',16))
+      boot_sbl_header.codeword = FLASH_CODE_WORD
+      boot_sbl_header.magic = MAGIC_NUM
+      boot_sbl_header.image_id = gen_dict['IMAGE_KEY_IMAGE_ID']
+      boot_sbl_header.image_src = MI_BOOT_SBL_HDR_SIZE
+      boot_sbl_header.image_dest_ptr = image_dest
+      boot_sbl_header.image_size = image_size
+      boot_sbl_header.code_size = code_size
+      boot_sbl_header.sig_ptr = image_dest + code_size
+      boot_sbl_header.sig_size = signature_size
+      boot_sbl_header.cert_chain_ptr = image_dest + code_size + signature_size
+      boot_sbl_header.cert_chain_size = cert_chain_size
+      boot_sbl_header.oem_root_cert_sel = gen_dict['IMAGE_KEY_OEM_ROOT_CERT_SEL']
+      boot_sbl_header.oem_num_root_certs = gen_dict['IMAGE_KEY_OEM_NUM_ROOT_CERTS']
+      if 'USES_SBL_FOR_AARCH64' in env:
+         boot_sbl_header.booting_image_config = SBL_AARCH64
+      elif 'USES_SBL_FOR_AARCH632' in env:
+         boot_sbl_header.booting_image_config = SBL_AARCH32
+
+      # If preamble is required, output the preamble file and update the boot_sbl_header
+      if requires_preamble is True:
+         boot_sbl_header = image_preamble(gen_dict, preamble_file_name, boot_sbl_header, num_of_pages)
+
+      # Package up the header and write to output file
+      boot_sbl_header.writePackedData(target = output_file_name)
+
+   elif header_format == 'reg' and mbn_version != 6:
+      boot_header = Boot_Hdr(init_val = int('0x0',16))
+      boot_header.image_id = gen_dict['IMAGE_KEY_IMAGE_ID']
+      boot_header.image_src = image_source
+      boot_header.image_dest_ptr = image_dest
+      boot_header.image_size = image_size
+      boot_header.code_size = code_size
+      boot_header.sig_ptr = image_dest + code_size
+      boot_header.sig_size = signature_size
+      boot_header.cert_chain_ptr = image_dest + code_size + signature_size
+      boot_header.cert_chain_size = cert_chain_size
+
+      # Package up the header and write to output file
+      boot_header.writePackedData(target = output_file_name, write_full_hdr = write_full_hdr)
+
+   elif header_format == 'reg' and mbn_version == 6:
+      boot_header = Boot_Hdr_V6(init_val = int('0x0',16))
+      boot_header.image_id = gen_dict['IMAGE_KEY_IMAGE_ID']
+      boot_header.qti_sig_size = 0
+      boot_header.qti_cert_chain_size = 0
+      boot_header.image_size = image_size
+      boot_header.code_size = code_size
+      boot_header.sig_ptr = 0
+      boot_header.sig_size = signature_size
+      boot_header.cert_chain_ptr = 0
+      boot_header.cert_chain_size = cert_chain_size
+      boot_header.oem_metadata_size = 0
+      boot_header.qti_metadata_size = 0
+
+      # Package up the header and write to output file
+      boot_header.writePackedData(target = output_file_name, write_full_hdr = write_full_hdr)
+
+   else:
+      raise RuntimeError("Header format not supported: " + str(header_format))
+   return 0
+
+#----------------------------------------------------------------------------
+# pboot_gen_elf
+#----------------------------------------------------------------------------
+def pboot_gen_elf(env, elf_in_file_name,
+                       hash_out_file_name,
+                       compress_method,
+                       elf_out_file_name,
+                       secure_type = 'non_secure',
+                       hash_seg_max_size = None,
+                       last_phys_addr = None,
+                       append_xml_hdr = False,
+                       cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE,
+                       mbn_version = None):
+   global MI_PROG_BOOT_DIGEST_SIZE
+   iarrPhdrFileLen = []
+   iarrPhdrFileOff = []
+
+   if mbn_version == 6:
+      sha_algo = 'sha384'
+      MI_PROG_BOOT_DIGEST_SIZE = 48
+   elif mbn_version == 3:
+      sha_algo = 'sha256'
+      MI_PROG_BOOT_DIGEST_SIZE = 32
+   else:
+      sha_algo = 'sha1'
+      MI_PROG_BOOT_DIGEST_SIZE = 20
+
+
+   # Open Files
+   elf_in_fp = OPEN(elf_in_file_name, "rb")
+   hash_out_fp = OPEN(hash_out_file_name, "wb+")
+
+   if elf_out_file_name is not None:
+      elf_out_fp = OPEN(elf_out_file_name, "wb+")
+
+   # Initialize
+   [elf_header, phdr_table] = preprocess_elf_file(elf_in_file_name)
+   num_phdrs = elf_header.e_phnum
+   phdr_total_size = num_phdrs * elf_header.e_phentsize
+   phdr_size = elf_header.e_phentsize
+   hashtable_size = 0
+   hashtable_shift = 0
+
+   if compress_method == "com":
+     is_com = True
+   else:
+     is_com = False
+
+   if elf_header.e_ident[ELFINFO_CLASS_INDEX] == ELFINFO_CLASS_64:
+      new_phdr = Elf64_Phdr(b'\0' * ELF64_PHDR_SIZE)
+      elf_header_size = ELF64_HDR_SIZE
+      is_elf64 = True
+   else:
+      new_phdr = Elf32_Phdr(b'\0' * ELF32_PHDR_SIZE)
+      elf_header_size = ELF32_HDR_SIZE
+      is_elf64 = False
+
+   hash = b'\0' * MI_PROG_BOOT_DIGEST_SIZE
+   phdr_start = 0
+   bytes_to_pad = 0
+   hash_seg_end = 0
+
+   # Process program headers if an output elf is specified
+   if elf_out_file_name is not None:
+      # Assert limit on number of program headers in input ELF
+      if num_phdrs > MAX_PHDR_COUNT:
+         raise RuntimeError("Input ELF has exceeded maximum number of program headers")
+
+      # Create new program header for the ELF Header + Program Headers
+      new_phdr.p_type = NULL_TYPE
+      new_phdr.p_flags = MI_PBT_ELF_PHDR_SEGMENT
+
+      # If hash table program header is not found, make sure to include it
+      elf_header.e_phnum += 2
+
+      # Create an empty hash entry for PHDR_TYPE
+      hash_out_fp.write(b'\0' * MI_PROG_BOOT_DIGEST_SIZE)
+      hashtable_size += MI_PROG_BOOT_DIGEST_SIZE
+
+      # Create an empty hash entry for the hash segment itself
+      hash_out_fp.write(b'\0' * MI_PROG_BOOT_DIGEST_SIZE)
+      hashtable_size += MI_PROG_BOOT_DIGEST_SIZE
+
+   # Begin hash table generation
+   for i in range(num_phdrs):
+      curr_phdr = phdr_table[i]
+
+      if (MI_PBT_PAGE_MODE_VALUE(curr_phdr.p_flags) == MI_PBT_PAGED_SEGMENT):
+         seg_offset = curr_phdr.p_offset
+         seg_size = curr_phdr.p_filesz
+         hash_size = 0
+
+         # Check if the vaddr is page aligned
+         off = curr_phdr.p_vaddr & (ELF_BLOCK_ALIGN - 1)
+         if int(off) != 0:
+            seg_size -= (ELF_BLOCK_ALIGN - off)
+            seg_offset += (ELF_BLOCK_ALIGN - off)
+
+         # Seg_size should be page aligned
+         if (seg_size & (ELF_BLOCK_ALIGN - 1)) > 0:
+            raise RuntimeError("seg_size: " + hex(seg_size) + " is not ELF page aligned!")
+
+         off = seg_offset + seg_size
+
+         while seg_offset < off:
+
+            if seg_offset < ELF_BLOCK_ALIGN:
+               hash_size = seg_offset
+            else:
+               hash_size = ELF_BLOCK_ALIGN
+
+            elf_in_fp.seek(seg_offset)
+            fbuf = elf_in_fp.read(hash_size)
+
+            if MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True:
+               hash = generate_hash(fbuf, sha_algo)
+            else:
+               hash = b'\0' * MI_PROG_BOOT_DIGEST_SIZE
+
+            # Write hash to file
+            hash_out_fp.write(hash)
+
+            hashtable_size += MI_PROG_BOOT_DIGEST_SIZE
+            seg_offset += ELF_BLOCK_ALIGN
+
+      # Copy the hash entry for all that are PAGED segments and those that are not the PHDR type. This is for
+      # backward tool compatibility where some images are generated using older exe tools.
+      elif((MI_PBT_PAGE_MODE_VALUE(curr_phdr.p_flags) == MI_PBT_NON_PAGED_SEGMENT) and (curr_phdr.p_type is not PHDR_TYPE)):
+         # Read full hash entry into buffer
+         elf_in_fp.seek(curr_phdr.p_offset)
+         data_len = curr_phdr.p_filesz
+         file_buff = elf_in_fp.read(data_len)
+         if ((is_com == True) and  ((curr_phdr.p_type is LOAD_TYPE) or (curr_phdr.p_type ==  PHDR_ENTR_TYPE))):
+           com_data_len = 0
+           if(data_len > 0):
+             srcfile = "comfile" + str(i)
+             Comfile = "comfile" + str(i) + ".gz"
+
+             src_in_fp = OPEN(srcfile,"wb+")
+             src_in_fp.write(file_buff)
+             src_in_fp.close()
+
+             prc = subprocess.Popen([
+                        outputdir,
+                        '-n',
+                        '-k',
+                        '-S.gz',
+                        '-f',
+                        '-6',
+                        str(srcfile),
+                        ])
+             prc.wait()
+
+             if prc.returncode != 0:
+               print('ERROR: unable to create compressed file Segment for' + str(Comfile))
+             else:
+               com_out_fp = OPEN(Comfile, "rb")
+               com_out_fp.seek(0,2)
+               com_data_len = com_out_fp.tell()
+               iarrPhdrFileLen.append(com_data_len)
+               com_out_fp.close()
+
+             src_in_fp = OPEN(srcfile,"rb")
+             src_in_fp.seek(0,2)
+             data_len = src_in_fp.tell()
+             src_in_fp.seek(0,0)
+             file_buff = src_in_fp.read(data_len)
+             src_in_fp.close()
+           else:
+             iarrPhdrFileLen.append(curr_phdr.p_filesz)
+
+         elif (is_com == True):
+           iarrPhdrFileLen.append(curr_phdr.p_filesz)
+
+         if (MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True) and (data_len > 0):
+            hash = generate_hash(file_buff, sha_algo)
+         else:
+            hash = b'\0' *  MI_PROG_BOOT_DIGEST_SIZE
+
+         # Write hash to file
+         hash_out_fp.write(hash)
+
+         hashtable_size += MI_PROG_BOOT_DIGEST_SIZE
+   # End hash table generation
+
+   # Generate the rest of the ELF output file if specified
+   if elf_out_file_name is not None:
+
+     # Preempt hash table size if necessary
+     if secure_type == 'secure':
+        hashtable_size += (SHA256_SIGNATURE_SIZE + cert_chain_size_in)
+
+     if append_xml_hdr is True:
+        hashtable_size += XML_HEADER_MAXSIZE
+
+     # Initialize the hash table program header
+     if mbn_version == 6:
+         [hash_Phdr, pad_hash_segment, hash_tbl_end_addr, hash_tbl_offset] = \
+                 initialize_hash_phdr(elf_in_file_name, hashtable_size, MI_BOOT_IMG_HDR_SIZE_V6, ELF_BLOCK_ALIGN, is_elf64)
+     else:
+         [hash_Phdr, pad_hash_segment, hash_tbl_end_addr, hash_tbl_offset] = \
+                 initialize_hash_phdr(elf_in_file_name, hashtable_size, MI_BOOT_IMG_HDR_SIZE, ELF_BLOCK_ALIGN, is_elf64)
+
+     # Check if hash segment max size parameter was passed
+     if (hash_seg_max_size is not None):
+         # Error checking for hash segment size validity
+        if hashtable_size > hash_seg_max_size:
+           raise RuntimeError("Hash table exceeds maximum hash segment size: " + hex(hash_seg_max_size))
+        if (hash_seg_max_size & (ELF_BLOCK_ALIGN-1)) != 0:
+           raise RuntimeError("Hash segment size passed is not ELF Block Aligned: " + hex(hash_seg_max_size))
+
+     # Check if hash physical address parameter was passed
+     if last_phys_addr is not None:
+        hash_Phdr.p_vaddr = last_phys_addr
+        hash_Phdr.p_paddr = last_phys_addr
+
+     # Check if hash segment max size was passed
+     if hash_seg_max_size is not None:
+        hash_Phdr.p_memsz = hash_seg_max_size
+
+     # Determine the end of the hash segment, make sure it's block aligned
+     bytes_to_pad = ELF_BLOCK_ALIGN - pad_hash_segment
+     hash_seg_end = hash_tbl_end_addr + bytes_to_pad
+
+     # Check if a shifting is required to accomodate for the hash segment.
+     # Get the minimum offset by going through the program headers.
+     # Note that the program headers in the input file do not contain
+     # the dummy program header for ELF + Program header, and the
+     # program header for the hashtable.
+     min_offset = phdr_table[0].p_offset
+     for i in range(num_phdrs):
+        curr_phdr = phdr_table[i]
+        if curr_phdr.p_offset < min_offset:
+            min_offset = curr_phdr.p_offset
+
+     if min_offset < hash_seg_end:
+        hashtable_shift = hash_seg_end - min_offset
+
+     # Move program headers to after ELF header
+     phdr_start = elf_header_size
+
+     # We copy over no section headers so assign these values to 0 in ELF Header
+     elf_header.e_shnum = 0
+     elf_header.e_shstrndx = 0
+     elf_header.e_shoff = 0
+
+     iprevoff =  hashtable_shift
+     # Output remaining ELF segments
+     for i in range(num_phdrs):
+
+         # Increment the file offset before writing to the destination file
+         curr_phdr = phdr_table[i]
+
+         # We do not copy over program headers of PHDR type, decrement the program
+         # header count and continue the loop
+         if curr_phdr.p_type is PHDR_TYPE:
+            elf_header.e_phnum -= 1
+            continue
+
+         src_offset = curr_phdr.p_offset
+
+         if (is_com == True) :
+           Comfile = "comfile" + str(i) + ".gz"
+
+           if i > 0 :
+             Prev_phdr = phdr_table[i-1]
+             pAlign = curr_phdr.p_align
+             Com_Filsize = iarrPhdrFileLen[i-1]
+           else:
+             pAlign = curr_phdr.p_align
+             Com_Filsize =0
+             iprevoff = iprevoff + curr_phdr.p_offset
+
+           if(pAlign == 0):
+             pAlign = 1
+
+           NextSeg_offset = iprevoff + Com_Filsize
+           NextSeg_Modoffset =  NextSeg_offset & (pAlign -1)
+
+           if(NextSeg_Modoffset) > 0 :
+             NextSeg_offset = NextSeg_offset + (pAlign - NextSeg_Modoffset)
+
+           iprevoff = NextSeg_offset
+           iarrPhdrFileOff.append(iprevoff)
+
+         # Copy the ELF segment
+         #file_copy_offset(elf_in_fp, src_offset, elf_out_fp, curr_phdr.p_offset + hashtable_shift, curr_phdr.p_filesz)
+           if(((curr_phdr.p_type is LOAD_TYPE) or (curr_phdr.p_type == PHDR_ENTR_TYPE))   and (curr_phdr.p_filesz > 0)) :
+             com_out_fp = OPEN(Comfile, "rb")
+             file_copy_offset(com_out_fp,0, elf_out_fp, iarrPhdrFileOff[i], iarrPhdrFileLen[i])
+             com_out_fp.close()
+           elif (curr_phdr.p_filesz > 0):
+             file_copy_offset(elf_in_fp,src_offset,elf_out_fp,iarrPhdrFileOff[i],iarrPhdrFileLen[i])
+         if(is_com == False) and (curr_phdr.p_filesz > 0):
+           file_copy_offset(elf_in_fp, src_offset, elf_out_fp, curr_phdr.p_offset + hashtable_shift, curr_phdr.p_filesz)
+
+     # Output remaining program headers and ELF segments
+     elf_header.e_phoff = phdr_start
+
+     # Output new program headers which we have generated
+     elf_out_fp.seek(phdr_start)
+     new_phdr.p_filesz = elf_header_size + (elf_header.e_phnum * phdr_size)
+     elf_out_fp.write(new_phdr.getPackedData())
+     elf_out_fp.write(hash_Phdr.getPackedData())
+     phdr_start += (2 * phdr_size)
+
+     # Increment the file offset before writing to the destination file
+     for i in range(num_phdrs):
+         curr_phdr = phdr_table[i]
+
+         if curr_phdr.p_type is PHDR_TYPE:
+            continue
+
+         if ((is_com == True) and  ((curr_phdr.p_type is LOAD_TYPE) or (curr_phdr.p_type == PHDR_ENTR_TYPE))):
+           curr_phdr.p_type = curr_phdr.p_type | 0x68000000
+         if (is_com == True):
+           curr_phdr.p_offset = iarrPhdrFileOff[i]
+           curr_phdr.p_filesz = iarrPhdrFileLen[i]
+         else:
+           curr_phdr.p_offset += hashtable_shift
+
+
+         # Copy the program header
+         elf_out_fp.seek(phdr_start)
+         elf_out_fp.write(curr_phdr.getPackedData())
+
+         # Update phdr_start
+         phdr_start += phdr_size
+
+     # Finally, copy the new ELF header to the destination file
+     elf_out_fp.seek(0)
+     elf_out_fp.write(elf_header.getPackedData())
+
+     # Recalculate hash of ELF + program headers and output to hash output file
+     elf_out_fp.seek(0)
+     # Read the elf header
+     elfhdr_buff = elf_out_fp.read(elf_header_size)
+     # Seek to the program header offset listed in elf header.
+     elf_out_fp.seek(elf_header.e_phoff)
+     # Read the program header and compute hash
+     proghdr_buff = elf_out_fp.read(elf_header.e_phnum * phdr_size)
+
+     hash = generate_hash(elfhdr_buff + proghdr_buff, sha_algo)
+
+     # Write hash to file as first hash table entry
+     hash_out_fp.seek(0)
+     hash_out_fp.write(hash)
+
+   # Close files
+   elf_in_fp.close()
+   hash_out_fp.close()
+
+   if elf_out_file_name is not None:
+      elf_out_fp.close()
+
+   return 0
+
+
+#----------------------------------------------------------------------------
+# pboot_add_hash
+#----------------------------------------------------------------------------
+def pboot_add_hash(env, elf_in_file_name,
+                        hash_tbl_file_name,
+                        elf_out_file_name):
+
+   # Open files
+   elf_in_fp = OPEN(elf_in_file_name, "rb")
+   hash_tbl_fp = OPEN(hash_tbl_file_name, "rb")
+   elf_out_fp = OPEN(elf_out_file_name, "wb+")
+
+   # Initialize
+   [elf_header, phdr_table] = preprocess_elf_file(elf_in_file_name)
+
+   hash_size = os.path.getsize(hash_tbl_file_name)
+   hash_segment_found = False
+
+   # Attempt to find the location of the hash program header
+   for i in range(elf_header.e_phnum):
+      curr_phdr = phdr_table[i]
+      if curr_phdr.p_flags == MI_PBT_ELF_HASH_SEGMENT:
+         hash_segment_found = True
+         break
+
+   if hash_segment_found is True:
+      # Copy input file to output file
+      shutil.copyfileobj(elf_in_fp, elf_out_fp, os.path.getsize(elf_in_file_name))
+
+      # Update ELF to insert hash table at corresponding file offset
+      hash_hdr_offset = curr_phdr.p_offset
+      file_copy_offset(hash_tbl_fp, 0, elf_out_fp, hash_hdr_offset, hash_size)
+
+   else:
+      raise RuntimeError("Hash segment program header not found in file " + elf_in_file_name)
+
+   # Close files
+   elf_in_fp.close()
+   hash_tbl_fp.close()
+   elf_out_fp.close()
+
+   return 0
+
+#----------------------------------------------------------------------------
+# image_auth
+#----------------------------------------------------------------------------
+def image_auth(env, *args):
+
+   if len(args) < 7 or len(args) > 8:
+      raise RuntimeError("Usage Invalid")
+
+   # Initialize File Names
+   binary_in            = args[0]
+   signature            = args[1]
+   attestation_cert     = args[2]
+   attestation_ca_cert  = args[3]
+   root_cert            = args[4]
+   cert_chain_out       = args[5]
+   signed_image_out     = args[6]
+   if len(args) == 8:
+     cert_size_max_in   = args[7]
+   else:
+     cert_size_max_in   = CERT_CHAIN_ONEROOT_MAXSIZE
+
+   # Creating list of certificates to support creation of certificate chains
+   # of lenth 1, 2, or 3 certificates
+   cert_list = []
+   num_certs = 0
+   if (os.path.exists(attestation_cert)):
+      cert_list.append(attestation_cert)
+      num_certs = num_certs + 1
+   if (os.path.exists(attestation_ca_cert)):
+      cert_list.append(attestation_ca_cert)
+      num_certs = num_certs + 1
+   if (os.path.exists(root_cert)):
+      cert_list.append(root_cert)
+      num_certs = num_certs + 1
+
+   if (num_certs == 0):
+      raise RuntimeError("Missing file(s) required for signing.\n")
+
+   # Create the Certificate Chain
+   concat_files (cert_chain_out, cert_list)
+
+   # Pad to ensure Certificate Chain Size is CERT_CHAIN_MAX_SIZE
+   cert_size = os.path.getsize(cert_chain_out)
+
+   if cert_size <= cert_size_max_in:
+      bytes_to_pad = cert_size_max_in - cert_size
+      cert_fp = OPEN(cert_chain_out,'ab')
+      pad_file(cert_fp, bytes_to_pad, PAD_BYTE_1)
+      cert_fp.close()
+   else:
+      raise RuntimeError("Certificate Size too large: " + str(cert_size))
+
+   # Create the Final Signed Image File
+   concat_files (signed_image_out, [binary_in, signature, cert_chain_out])
+
+   return 0
+
+#----------------------------------------------------------------------------
+# modify_relocatable_flags
+#----------------------------------------------------------------------------
+def modify_relocatable_flags(env, output_elf ):
+
+   # Offset into program header where the p_flags field is stored
+   phdr_align_flag_offset = 28
+   phdr_reloc_flag_offset = 24
+
+   # Initialize
+   [elf_header, phdr_table] = preprocess_elf_file(output_elf)
+
+   if elf_header.e_ident[ELFINFO_CLASS_INDEX] == ELFINFO_CLASS_64:
+      curr_phdr = Elf64_Phdr('\0' * ELF64_PHDR_SIZE)
+      elf_header_size = ELF64_HDR_SIZE
+      is_elf64 = True
+   else:
+      curr_phdr = Elf32_Phdr('\0' * ELF32_PHDR_SIZE)
+      elf_header_size = ELF32_HDR_SIZE
+      is_elf64 = False
+
+   # Open files
+   elf_in_fp = OPEN(output_elf, "r+")
+
+   # Go to the start of the p_flag entry in the first program header
+   file_offset_align_flag = elf_header.e_phoff + phdr_align_flag_offset
+
+   # Change the align field in the program header in the ELF file
+   elf_in_fp.seek(file_offset_align_flag)
+   curr_phdr = phdr_table[0]
+
+   #default alignment value is 1MB unless otherwise specified
+   if 'USES_RELOC_ALIGN_VALUE_4MB' in env:
+       alignment_value = ALIGNVALUE_4MB
+   else:
+       alignment_value = ALIGNVALUE_1MB
+
+
+
+   #create new alignment value
+   new_align = (curr_phdr.p_align & 0) | alignment_value
+
+   # Create structure to package new flag field
+   s = struct.Struct('I')
+   new_flag_bytes = s.pack(new_align)
+
+   # Write the new flag value and incr ement offset
+   elf_in_fp.write(new_flag_bytes)
+
+   # Go to the start of the p_flag entry in the first program header
+   file_offset_reloc_flag = elf_header.e_phoff + phdr_reloc_flag_offset
+
+   # Change each program header flag in the ELF file with relocatable flag
+   for i in range(elf_header.e_phnum):
+      # Seek to correct location and create new p_flag value
+      elf_in_fp.seek(file_offset_reloc_flag)
+      curr_phdr = phdr_table[i]
+      new_flag = (curr_phdr.p_flags & ~MI_PBT_FLAGS_MASK) | (MI_PBT_ELF_AMSS_RELOCATABLE_IMAGE)
+
+      # Create structure to package new flag field
+      s = struct.Struct('I')
+      new_flag_bytes = s.pack(new_flag)
+
+      # Write the new flag value and increment offset
+      elf_in_fp.write(new_flag_bytes)
+      file_offset_reloc_flag += elf_header.e_phentsize
+
+   # Close files
+   elf_in_fp.close()
+
+
+   return 0
+
+
+#----------------------------------------------------------------------------
+# modify_elf_flags
+#----------------------------------------------------------------------------
+def modify_elf_flags(env, elf_in_file_name,
+                          scl_file_name):
+
+   # Initialize
+   [elf_header, phdr_table] = preprocess_elf_file(elf_in_file_name)
+   segment_list = readSCL(scl_file_name, env['GLOBAL_DICT'])
+
+   if elf_header.e_ident[ELFINFO_CLASS_INDEX] == ELFINFO_CLASS_64:
+     curr_phdr = Elf64_Phdr('\0' * ELF64_PHDR_SIZE)
+     # Offset into program header where the p_flags field is stored
+     phdr_flag_off = 4
+   else:
+     curr_phdr = Elf32_Phdr('\0' * ELF32_PHDR_SIZE)
+     # Offset into program header where the p_flags field is stored
+     phdr_flag_off = 24
+
+   # Open files
+   elf_in_fp = OPEN(elf_in_file_name, "r+")
+
+   # Check for corresponding number of segments
+   if len(segment_list) is not elf_header.e_phnum:
+      raise RuntimeError('SCL file and ELF file have different number of segments!')
+
+   # Go to the start of the p_flag entry in the first program header
+   file_offset = elf_header.e_phoff + phdr_flag_off
+
+   # Change each program header flag in the ELF file based off the SCL file
+   for i in range(elf_header.e_phnum):
+      # Seek to correct location and create new p_flag value
+      elf_in_fp.seek(file_offset)
+      curr_phdr = phdr_table[i]
+      new_flag = (curr_phdr.p_flags & ~MI_PBT_FLAGS_MASK) | (segment_list[i].flag)
+
+      # Create structure to package new flag field
+      s = struct.Struct('I')
+      new_flag_bytes = s.pack(new_flag)
+
+      # Write the new flag value and increment offset
+      elf_in_fp.write(new_flag_bytes)
+      file_offset += elf_header.e_phentsize
+
+   # Close files
+   elf_in_fp.close()
+
+   return 0
+
+#----------------------------------------------------------------------------
+# generate_code_hash
+#----------------------------------------------------------------------------
+def generate_code_hash(env, elf_in_file_name):
+
+   # Initialize
+   [elf_header, phdr_table] = preprocess_elf_file(elf_in_file_name)
+
+   if elf_header.e_ident[ELFINFO_CLASS_INDEX] == ELFINFO_CLASS_64:
+     curr_phdr = Elf64_Phdr('\0' * ELF64_PHDR_SIZE)
+     # Offset into program header where the p_flags field is stored
+     phdr_flag_off = 4
+   else:
+     curr_phdr = Elf32_Phdr('\0' * ELF32_PHDR_SIZE)
+     # Offset into program header where the p_flags field is stored
+     phdr_flag_off = 24
+
+   # Open files
+   elf_in_fp = OPEN(elf_in_file_name, "rb+")
+
+   # Go to the start of the p_flag entry in the first program header
+   file_offset = elf_header.e_phoff + phdr_flag_off
+
+   # XXX Get these from env?
+   DP_CODE_ALIGN = 0x100
+   DP_PAGE_SIZE  = 4096
+   DP_HASH_SIZE  = 32  # SHA-256
+   DP_HASH_MAGIC = 0xC0DEDEC0
+   PH_PERM_RW   = 0x06
+   PH_PERM_RX   = 0x05
+   PH_PERM_RO   = 0x04
+   PH_PERM_MASK = 0x07
+
+   page_size = DP_PAGE_SIZE
+   hash_size = DP_HASH_SIZE
+
+   # First identify the hash segment. It is the first RW section.
+   # Its Align should be 8, and its size a multiple of DP_HASH_SIZE;
+
+   hash_seg_idx = -1
+   for i in range(elf_header.e_phnum):
+      curr_phdr = phdr_table[i]
+
+      if (curr_phdr.p_align == 8 and
+          (curr_phdr.p_flags & PH_PERM_MASK) == PH_PERM_RW and
+          curr_phdr.p_filesz != 0 and (curr_phdr.p_filesz % DP_HASH_SIZE) == 0):
+         hash_seg_idx = i
+         # Validate the contents of the hash segment. It should be
+         # filled with DP_HASH_MAGIC
+         elf_in_fp.seek(curr_phdr.p_offset)
+         hash_data = "";
+         while (len(hash_data) < curr_phdr.p_filesz):
+            hash_data = hash_data + elf_in_fp.read(curr_phdr.p_filesz - len(hash_data))
+
+         hash_data = struct.unpack("I" * (curr_phdr.p_filesz / 4), hash_data)
+
+         for v in hash_data[:]:
+            if (v != DP_HASH_MAGIC):
+               hash_seg_idx = -1
+               break;
+
+         if (hash_seg_idx != -1):
+            break
+
+   if (hash_seg_idx == -1):
+      # return if there is no hash segment.
+      return 0
+
+   hash_phdr = phdr_table[hash_seg_idx]
+
+   # Now find the code segment for the hashes. Look for matching number of pages
+   code_seg_idx = -1
+   code_seg_pages = hash_phdr.p_filesz / DP_HASH_SIZE
+
+   for i in range(elf_header.e_phnum):
+      curr_phdr = phdr_table[i]
+      curr_pages = (curr_phdr.p_filesz + DP_PAGE_SIZE - 1) / DP_PAGE_SIZE
+
+      if (curr_phdr.p_align == DP_CODE_ALIGN and
+          (curr_phdr.p_flags & PH_PERM_MASK) == PH_PERM_RX and
+          curr_pages == code_seg_pages):
+         if (code_seg_idx != -1):
+            raise RuntimeError('Multiple code segments match for: ' + code_seg_pages + ' pages')
+         code_seg_idx = i
+
+   if (code_seg_idx == -1):
+      raise RuntimeError('No matching code segment found')
+
+   code_phdr = phdr_table[code_seg_idx]
+
+   # Now hash the pages in the code segment
+   hashes = []
+   elf_in_fp.seek(code_phdr.p_offset)
+   bytes_left = code_phdr.p_filesz;
+   while (bytes_left > 0):
+      bytes_in_page = min(bytes_left, DP_PAGE_SIZE)
+      page = "";
+      while (len(page) < bytes_in_page):
+         page = page + elf_in_fp.read(bytes_in_page - len(page))
+      if (len(page) < DP_PAGE_SIZE):
+         page = page + (struct.pack('b', 0) * (DP_PAGE_SIZE - len(page)))
+      hashes = hashes + [generate_hash(page, 'sha256')]
+      bytes_left -= bytes_in_page
+
+   # And write them to the hash segment
+   elf_in_fp.seek(hash_phdr.p_offset)
+
+   for h in hashes[:]:
+      elf_in_fp.write(h)
+
+   # Close files
+   elf_in_fp.close()
+
+   return 0
+
+#----------------------------------------------------------------------------
+# BOOT TOOLS END
+#----------------------------------------------------------------------------
+
+#----------------------------------------------------------------------------
+# HELPER FUNCTIONS BEGIN
+#----------------------------------------------------------------------------
+
+#----------------------------------------------------------------------------
+# Create a list to hold all segment information from an input SCL file
+#----------------------------------------------------------------------------
+def readSCL(filename, global_dict):
+
+  scl_fp = OPEN(filename,'r')
+
+  # Initialize
+  file_data = scl_fp.readlines()
+  num_lines = len(file_data)
+  current_line = ''
+  previous_line = ''
+  strip_chars = '(){}[]'
+  i = 0
+  bracket_counter = 0
+  seg_list = []
+
+  # Parse through all lines
+  while i < num_lines:
+
+     # Save the last line read
+     previous_line = current_line
+     current_line = file_data[i]
+
+     # Look for the symbol '{' for the line to read.
+     # Use bracket counter to skip nested '{ }'
+     if ('{' in current_line):
+        if bracket_counter == 0:
+           # Create a new SegmentInfo class and set up tokens
+           new_scl_entry = SegmentInfo()
+           previous_line = previous_line.strip()
+           tokens = previous_line.split(' ')
+
+           # Check that at least two tokens were parsed
+           # Token 1: Segment Name
+           # Token 2: Start Address
+           if len(tokens) < 2:
+              raise RuntimeError('SCL Segment Syntax malformed: ' + previous_line)
+
+           # Get the segment flags corresponding to the segment name description
+           new_scl_entry.flag = getSegmentFlag(tokens[0].strip(strip_chars))
+
+           # Get the start address of the segment based off the SCL string
+           start_addr = tokens[1].strip(strip_chars)
+           try:
+              start_addr_final = eval(start_addr)
+           # Catch NameError and attempt to locate start address from dictionary
+           except NameError:
+              if start_addr in global_dict:
+                 return global_dict[start_addr]
+              else:
+                 raise RuntimeError('Unrecognized start address: ' + start_addr)
+
+           new_scl_entry.start_addr = start_addr_final
+           seg_list.append(new_scl_entry)
+
+        bracket_counter += 1
+     elif '}' in current_line:
+        bracket_counter -= 1
+
+     i+=1
+
+  scl_fp.close()
+  return seg_list
+
+#----------------------------------------------------------------------------
+# Given a string parsed from a SCL file, returns the ELF segment flags
+#----------------------------------------------------------------------------
+def getSegmentFlag(seg_info):
+
+   ret_val = None
+
+   # Define string values for various types of segments
+   RO = "RO"
+   RW = "RW"
+   ZI = "ZI"
+   PAGEABLE = "PAGED"
+   NOTPAGEABLE = "NOTPAGED"
+   SWAPABLE = "SWAPPED"
+   SWAP_POOL = "SWAP_POOL"
+   RESERVED = "RESERVED"
+   HASHTBL = "HASH"
+   SHARED = "SHARED"
+   NOTUSED = "NOTUSED"
+   BOOT_SEGMENT = "BOOT_SEGMENT"
+   CODE = "CODE"
+   L4BSP = "L4BSP"
+   POOL_INDEX_0 = "INDEX_0"
+   POOL_INDEX_1 = "INDEX_1"
+
+   if seg_info is None or len(seg_info) == 0:
+      raise RuntimeError('Invalid segment information passed: ' + seg_info)
+
+   # Conditional checks and assignments of the corresponding segment flag values
+   if NOTPAGEABLE in seg_info:
+      if RO in seg_info:
+         ret_val = MI_PBT_ELF_AMSS_NON_PAGED_RO_SEGMENT
+      elif CODE in seg_info:
+         ret_val = MI_PBT_ELF_AMSS_NON_PAGED_RO_SEGMENT
+      elif ZI in seg_info:
+         if SWAP_POOL in seg_info:
+            if POOL_INDEX_0 in seg_info:
+               ret_val = MI_PBT_ELF_SWAP_POOL_NON_PAGED_ZI_SEGMENT_INDEX0
+            else:
+               ret_val = MI_PBT_ELF_SWAP_POOL_NON_PAGED_ZI_SEGMENT_INDEX1
+         else:
+            ret_val = MI_PBT_ELF_AMSS_NON_PAGED_ZI_SEGMENT
+
+      elif NOTUSED in seg_info:
+         ret_val = MI_PBT_ELF_AMSS_NON_PAGED_NOTUSED_SEGMENT
+
+      elif SHARED in seg_info:
+         ret_val = MI_PBT_ELF_AMSS_NON_PAGED_SHARED_SEGMENT
+      elif HASHTBL in seg_info:
+         ret_val = MI_PBT_ELF_HASH_SEGMENT
+      elif BOOT_SEGMENT in seg_info:
+         ret_val = MI_PBT_ELF_BOOT_SEGMENT
+      elif L4BSP in seg_info:
+         ret_val = MI_PBT_ELF_NON_PAGED_L4BSP_SEGMENT
+      else:
+         ret_val = MI_PBT_ELF_AMSS_NON_PAGED_RW_SEGMENT
+
+   elif PAGEABLE in seg_info:
+      if RO in seg_info or CODE in seg_info:
+         if SWAPABLE in seg_info:
+            if POOL_INDEX_0 in seg_info:
+               ret_val = MI_PBT_ELF_SWAPPED_PAGED_RO_SEGMENT_INDEX0
+            else:
+               ret_val = MI_PBT_ELF_SWAPPED_PAGED_RO_SEGMENT_INDEX1
+         else:
+            ret_val = MI_PBT_ELF_AMSS_PAGED_RO_SEGMENT
+      elif ZI in seg_info:
+         ret_val = MI_PBT_ELF_AMSS_PAGED_ZI_SEGMENT
+
+      elif NOTUSED in seg_info:
+         ret_val = MI_PBT_ELF_AMSS_PAGED_NOTUSED_SEGMENT
+      elif SHARED in seg_info:
+         ret_val = MI_PBT_ELF_AMSS_PAGED_SHARED_SEGMENT
+      elif L4BSP in seg_info:
+         ret_val = MI_PBT_ELF_PAGED_L4BSP_SEGMENT
+      else:
+         ret_val = MI_PBT_ELF_AMSS_PAGED_RW_SEGMENT
+
+   else:
+      raise RuntimeError('The segment name is wrongly defined in the SCL file: ' + seg_info)
+
+   return ret_val
+
+#----------------------------------------------------------------------------
+# Pad a file with specific number of bytes
+# Note: Assumes the fp is seeked to the correct location of padding
+#----------------------------------------------------------------------------
+def pad_file(fp, num_bytes, value):
+
+   if num_bytes < 0:
+      raise RuntimeError("Number of bytes to pad must be greater than zero")
+
+   while num_bytes > 0:
+      fp.write('%c' % value)
+      num_bytes -= 1
+
+   return
+
+#----------------------------------------------------------------------------
+# Concatenates the files listed in 'sources' in order and writes to 'target'
+#----------------------------------------------------------------------------
+def concat_files (target, sources):
+   if type(sources) is not list:
+      sources = [sources]
+
+   target_file = OPEN(target,'wb')
+
+   for fname in sources:
+      file = OPEN(fname,'rb')
+      while True:
+         bin_data = file.read(65536)
+         if not bin_data:
+            break
+         target_file.write(bin_data)
+      file.close()
+   target_file.close()
+
+#----------------------------------------------------------------------------
+# Parse build configurable values and assign to global variables for tools
+#----------------------------------------------------------------------------
+def init_build_vars(env):
+
+   # Maximum size of Certificate Chain used in Secure Boot
+   global CERT_CHAIN_ONEROOT_MAXSIZE
+   CERT_CHAIN_ONEROOT_MAXSIZE = get_dict_value(env['GLOBAL_DICT'], 'CERT_CHAIN_MAXSIZE', (6*1024))
+
+   # Maximum size of the XML Header used in encrypted ELF images
+   global XML_HEADER_MAXSIZE
+   XML_HEADER_MAXSIZE = get_dict_value(env['GLOBAL_DICT'], 'XML_HEADER_MAXSIZE', (2*1024))
+
+#----------------------------------------------------------------------------
+# Generates the global dictionary and add to the environment
+#----------------------------------------------------------------------------
+def generate_global_dict(env):
+
+   # Get file names for 'cust' and 'targ' auto-generated files inside 'build/ms'
+   cust_h = env.subst('CUST${BUILD_ID}.H').lower()
+   targ_h = env.subst('TARG${BUILD_ID}.H').lower()
+   cust_file_name = str(env.FindFile(cust_h, "${INC_ROOT}/build/ms"))
+   targ_file_name = str(env.FindFile(targ_h, "${INC_ROOT}/build/ms"))
+
+   # Check that files are present
+   if (os.path.exists(cust_file_name) is True) and \
+      (os.path.exists(targ_file_name) is True):
+
+      # Populate the dictionary from the auto-generated files
+      global_dict = populate_dictionary(targ_file_name, cust_file_name)
+   else:
+      global_dict = {}
+
+   # Add the dictionary to the environment
+   env.Replace(GLOBAL_DICT = global_dict)
+
+#----------------------------------------------------------------------------
+# Populate the dictionary from a list of input files
+#----------------------------------------------------------------------------
+def populate_dictionary(*args):
+
+   if len(args) < 1:
+      raise RuntimeError("At least 1 file must be specified as an input")
+
+   global_dict = {}
+   Fields = ["Define", "Key", "Value"]
+
+   # For each input file
+   for i in range(len(args)):
+
+      template_file_path = args[i]
+      instream = OPEN(template_file_path, 'r')
+      # Tokenize each line with a white space
+      values = csv.DictReader(instream, Fields, delimiter=" ")
+
+      for values in itertools.izip(values):
+         new_entry = values[0]
+         # Verify the parsed tokens
+         if (new_entry['Define'] == '#define') and \
+            (new_entry['Key'] != None) and \
+            (new_entry['Value'] != None):
+
+            new_key   = new_entry['Key'].strip()
+            new_value = new_entry['Value'].strip()
+
+            # If value pair is empty string, assume feature definition is true
+            if new_value == '':
+               new_value = 'yes'
+
+            # Check for and handle text replacements as we parse
+            if global_dict is not None and len(global_dict.keys()) > 0:
+               for key in global_dict:
+                  new_value = new_value.replace(key, str(global_dict.get(key)))
+
+            # Attempt to evaluate value
+            try:
+               new_value = eval(new_value)
+            # Catch exceptions and do not evaluate
+            except:
+               pass
+
+            # Add to global dictionary
+            global_dict[new_key] = new_value
+      instream.close()
+
+   return global_dict
+
+#----------------------------------------------------------------------------
+# Filter out a generic dictionary from the global dictionary
+#----------------------------------------------------------------------------
+def filter_dictionary(env, global_dict, **kwargs):
+
+   # Check for Image Type
+   # If IMAGE_TYPE parameter is not provided, raise error
+   if not kwargs.has_key('IMAGE_TYPE'):
+      raise RuntimeError("IMAGE_TYPE must be defined to use FilterDictionary.")
+   else:
+      image_type = kwargs.get('IMAGE_TYPE')
+      if type(image_type) is not str:
+         raise RuntimeError("IMAGE_TYPE must be of string type.")
+
+   # Check for Flash Type
+   # If FLASH_TYPE parameter is not provided, default to 'nand'
+   if not kwargs.has_key('FLASH_TYPE'):
+      flash_type = 'nand'
+   else:
+      flash_type = kwargs.get('FLASH_TYPE')
+      if type(flash_type) is not str:
+         raise RuntimeError("FLASH_TYPE must be of string type. ")
+
+   # Check for MBN Type
+   # If MBN_TYPE parameter is not provided, default to 'elf'
+   if not kwargs.has_key('MBN_TYPE'):
+      mbn_type = 'elf'
+   else:
+      mbn_type = kwargs.get('MBN_TYPE')
+      if mbn_type != 'elf' and mbn_type != 'bin':
+         raise RuntimeError("MBN_TYPE currently not supported: " + mbn_type)
+
+   # Check for Image ID
+   # If IMAGE_ID parameter is not provided, default to ID 0
+   if not kwargs.has_key('IMAGE_ID'):
+      image_id = ImageType.NONE_IMG
+   else:
+      image_id = kwargs.get('IMAGE_ID')
+      if type(image_id) is not int:
+         raise RuntimeError("IMAGE_ID must be of integer type.")
+
+   # Initialize
+   gen_dict = {}
+   image_dest = 0
+   image_source = 0
+
+   # Check for image_type
+   if image_type not in image_id_table:
+      id = image_id
+      id_match_str = image_type.upper() + "_IMG"
+      id_mbn_type = mbn_type
+   else:
+      id = image_id_table[image_type][0]
+      id_match_str = image_id_table[image_type][1]
+      id_mbn_type = image_id_table[image_type][2]
+
+   # Handle MBN Type and assign image destination address
+   if id_mbn_type == 'elf':
+      pass
+   elif id_mbn_type == 'bin':
+      template_key_match = 'IMAGE_KEY_' + id_match_str + "_DEST_ADDR"
+      if template_key_match in global_dict:
+         image_dest = global_dict[template_key_match]
+      else:
+         raise RuntimeError("Builds file does not have IMAGE_KEY pair for: " + image_type)
+   else:
+      raise RuntimeError("MBN_TYPE currently not supported: " + mbn_type)
+
+   # Assign generic dictionary key/value pairs
+   gen_dict['IMAGE_KEY_IMAGE_ID'] = id
+   gen_dict['IMAGE_KEY_IMAGE_DEST'] = image_dest
+   gen_dict['IMAGE_KEY_IMAGE_SOURCE'] = image_source
+   gen_dict['IMAGE_KEY_FLASH_TYPE'] = flash_type
+   gen_dict['IMAGE_KEY_MBN_TYPE'] = id_mbn_type
+   gen_dict['IMAGE_KEY_ID_MATCH_STR'] = id_match_str
+   gen_dict['IMAGE_KEY_FLASH_AUTO_DETECT_MAX_PAGE'] = \
+      get_dict_value(global_dict,'FLASH_AUTO_DETECT_MAX_PAGE', 8192)
+   gen_dict['IMAGE_KEY_FLASH_AUTO_DETECT_MIN_PAGE'] = \
+      get_dict_value(global_dict,'FLASH_AUTO_DETECT_MIN_PAGE', 2048)
+   gen_dict['IMAGE_KEY_MAX_SIZE_OF_VERIFY_BUFFER'] = \
+      get_dict_value(global_dict,'MAX_SIZE_OF_VERIFY_BUFFER', 8192)
+   gen_dict['IMAGE_KEY_BOOT_SMALL_PREAMBLE'] = \
+      get_dict_value(global_dict,'BOOT_SMALL_PREAMBLE', 1)
+
+   # Get OEM root certificate select and number
+   oem_root_cert_sel = get_dict_value(global_dict,'OEM_ROOT_CERT_SEL', 1)
+   oem_num_root_certs = get_dict_value(global_dict,'OEM_NUM_ROOT_CERTS', 1)
+
+   # Error checking for OEM configurable values
+   if oem_root_cert_sel in range(1, MAX_NUM_ROOT_CERTS + 1) and \
+      oem_num_root_certs in range(1, MAX_NUM_ROOT_CERTS + 1) and \
+      oem_root_cert_sel <= oem_num_root_certs:
+
+      gen_dict['IMAGE_KEY_OEM_ROOT_CERT_SEL'] = oem_root_cert_sel
+      gen_dict['IMAGE_KEY_OEM_NUM_ROOT_CERTS'] = oem_num_root_certs
+
+   else:
+      raise RuntimeError("Invalid OEM root certificate configuration values")
+
+   # Assign additional dictionary key/values pair as needed by tools.
+
+   return gen_dict
+
+
+#----------------------------------------------------------------------------
+# Get index value from dictionary if exists, otherwise return default
+#----------------------------------------------------------------------------
+def get_dict_value(dict, key_string, default):
+
+   key = 'IMAGE_KEY_' + key_string
+
+   if key in dict:
+      return dict[key]
+   else:
+      return default
+
+#----------------------------------------------------------------------------
+# Preprocess an ELF file and return the ELF Header Object and an
+# array of ELF Program Header Objects
+#----------------------------------------------------------------------------
+def preprocess_elf_file(elf_file_name):
+
+   # Initialize
+   elf_fp = OPEN(elf_file_name, 'rb')
+   elf_header = Elf_Ehdr_common(elf_fp.read(ELF_HDR_COMMON_SIZE))
+
+   if verify_elf_header(elf_header) == False:
+      raise RuntimeError("ELF file failed verification: " + elf_file_name)
+
+   elf_fp.seek(0)
+
+   if elf_header.e_ident[ELFINFO_CLASS_INDEX] == ELFINFO_CLASS_64:
+      elf_header = Elf64_Ehdr(elf_fp.read(ELF64_HDR_SIZE))
+   else:
+      elf_header = Elf32_Ehdr(elf_fp.read(ELF32_HDR_SIZE))
+
+   phdr_table = []
+
+   # Verify ELF header information
+   if verify_elf_header(elf_header) == False:
+      raise RuntimeError("ELF file failed verification: " + elf_file_name)
+
+   # Get program header size
+   phdr_size = elf_header.e_phentsize
+
+   # Find the program header offset
+   file_offset = elf_header.e_phoff
+   elf_fp.seek(file_offset)
+
+   # Read in the program headers
+   for i in range(elf_header.e_phnum):
+      if elf_header.e_ident[ELFINFO_CLASS_INDEX] == ELFINFO_CLASS_64:
+         phdr_table.append(Elf64_Phdr(elf_fp.read(phdr_size)))
+      else:
+         phdr_table.append(Elf32_Phdr(elf_fp.read(phdr_size)))
+
+   elf_fp.close()
+   return [elf_header, phdr_table]
+
+#----------------------------------------------------------------------------
+# Get the hash table address from an input ELF file
+#----------------------------------------------------------------------------
+def get_hash_address(elf_file_name):
+
+   [elf_header, phdr_table] = preprocess_elf_file(elf_file_name)
+
+   last_paddr = 0
+   last_paddr_segment = 0
+
+   # Find the segment with the largest physical address.
+   # Hash segment's physical address will be immediately after this segment.
+   for i in range(elf_header.e_phnum):
+      curr_phdr = phdr_table[i]
+      if curr_phdr.p_paddr > last_paddr:
+         # Skip the demand paging segment as it would be outside the physical RAM location
+         if MI_PBT_SEGMENT_TYPE_VALUE(curr_phdr.p_flags) != MI_PBT_SWAPPED_SEGMENT:
+            last_paddr = curr_phdr.p_paddr;
+            last_paddr_segment = i;
+
+   max_phdr = phdr_table[last_paddr_segment]
+
+   ret_val  = (((max_phdr.p_paddr + max_phdr.p_memsz - 1) & \
+              ~(ELF_BLOCK_ALIGN-1)) + ELF_BLOCK_ALIGN)
+
+   return ret_val
+
+#----------------------------------------------------------------------------
+# Verify ELF header contents from an input ELF file
+#----------------------------------------------------------------------------
+def verify_elf_header(elf_header):
+   if (elf_header.e_ident[ELFINFO_MAG0_INDEX] != ELFINFO_MAG0) or \
+      (elf_header.e_ident[ELFINFO_MAG1_INDEX] != ELFINFO_MAG1) or \
+      (elf_header.e_ident[ELFINFO_MAG2_INDEX] != ELFINFO_MAG2) or \
+      (elf_header.e_ident[ELFINFO_MAG3_INDEX] != ELFINFO_MAG3) or \
+      ((elf_header.e_ident[ELFINFO_CLASS_INDEX] != ELFINFO_CLASS_64) and \
+       (elf_header.e_ident[ELFINFO_CLASS_INDEX] != ELFINFO_CLASS_32)) or \
+      (elf_header.e_ident[ELFINFO_VERSION_INDEX] != ELFINFO_VERSION_CURRENT):
+
+      return False
+   else:
+      return True
+
+#----------------------------------------------------------------------------
+# Perform file copy given offsets and the number of bytes to copy
+#----------------------------------------------------------------------------
+def file_copy_offset(in_fp, in_off, out_fp, out_off, num_bytes):
+   in_fp.seek(in_off)
+   read_in = in_fp.read(num_bytes)
+   out_fp.seek(out_off)
+   out_fp.write(read_in)
+
+   return num_bytes
+
+#----------------------------------------------------------------------------
+# sha1/sha256/sha384 hash routine wrapper
+#----------------------------------------------------------------------------
+def generate_hash(in_buf, sha_algo):
+   # Initialize a SHA object from the Python hash library
+   if sha_algo == 'sha384':
+      m = hashlib.sha384()
+   elif sha_algo == 'sha256':
+      m = hashlib.sha256()
+   else:
+      m = hashlib.sha1()
+
+   # Set the input buffer and return the output digest
+   m.update(in_buf)
+   return m.digest()
+
+#----------------------------------------------------------------------------
+# Initialize the hash program header.
+#----------------------------------------------------------------------------
+def initialize_hash_phdr(elf_in_file_name, hash_tbl_size, hdr_size, hdr_offset, is_elf64):
+   # Set hash header offset to page size boundary. Hash table will be
+   # located at first segment of elf image.
+   hash_hdr_size =  hdr_size
+   hash_hdr_offset = hdr_offset
+   hash_tbl_offset = hash_hdr_offset + hash_hdr_size
+   hash_tbl_end_addr = hash_tbl_offset + hash_tbl_size;
+   pad_hash_segment = (hash_tbl_end_addr) & (ELF_BLOCK_ALIGN-1)
+
+   # Update the hash table program header
+   if is_elf64 is True:
+      hash_Phdr = Elf64_Phdr(b'\0'*ELF64_PHDR_SIZE)
+   else:
+      hash_Phdr = Elf32_Phdr(b'\0'*ELF32_PHDR_SIZE)
+   hash_Phdr.p_flags = MI_PBT_ELF_HASH_SEGMENT
+   hash_Phdr.p_align = ELF_BLOCK_ALIGN
+   hash_Phdr.p_offset = hash_hdr_offset
+   hash_Phdr.p_memsz = hash_hdr_size + hash_tbl_size + (ELF_BLOCK_ALIGN - pad_hash_segment)
+   hash_Phdr.p_filesz = hash_hdr_size + hash_tbl_size
+   hash_Phdr.p_type = NULL_TYPE
+   hash_Phdr.p_vaddr = get_hash_address(elf_in_file_name)
+   hash_Phdr.p_paddr = hash_Phdr.p_vaddr
+
+   return [hash_Phdr, pad_hash_segment, hash_tbl_end_addr, hash_tbl_offset]
+
+#----------------------------------------------------------------------------
+# image_preamble
+#----------------------------------------------------------------------------
+def image_preamble(gen_dict, preamble_file_name, boot_sbl_header, num_of_pages=None):
+   # Generate the preamble file
+   preamble_fp = OPEN(preamble_file_name, 'wb')
+
+   # Initialize
+   max_size_verify = gen_dict['IMAGE_KEY_MAX_SIZE_OF_VERIFY_BUFFER']
+   flash_max_page = gen_dict['IMAGE_KEY_FLASH_AUTO_DETECT_MAX_PAGE']
+   flash_min_page = gen_dict['IMAGE_KEY_FLASH_AUTO_DETECT_MIN_PAGE']
+   autodetectpage = [int('0xFFFFFFFF',16)] * max_size_verify
+
+   # The first three entries in the preamble must include the following values
+   autodetectpage[0] = FLASH_CODE_WORD
+   autodetectpage[1] = MAGIC_NUM
+   if (num_of_pages == 64):
+     autodetectpage[2] = AUTODETECT_PAGE_SIZE_MAGIC_NUM64
+   elif (num_of_pages == 128):
+     autodetectpage[2] = AUTODETECT_PAGE_SIZE_MAGIC_NUM128
+   else:
+     autodetectpage[2] = AUTODETECT_PAGE_SIZE_MAGIC_NUM
+
+   # Package the list into binary data to be written to the preamble
+   s = struct.Struct('I' * max_size_verify)
+   packed_data = s.pack(*autodetectpage)
+
+   # Output preamble pages based on maximum/minimum page size support
+   for i in range(flash_max_page/flash_min_page):
+      preamble_fp.write(packed_data[:flash_min_page])
+
+   # Determine appropriate amount of padding for the preamble and
+   # update the boot_sbl_header accordingly
+   if gen_dict['IMAGE_KEY_BOOT_SMALL_PREAMBLE'] == 1:
+      boot_sbl_header.image_src += (flash_max_page + flash_min_page)
+      amount_to_write = flash_min_page
+   else:
+      boot_sbl_header.image_src += flash_max_page * 2
+      amount_to_write = flash_max_page
+
+   pad_file(preamble_fp, amount_to_write, PAD_BYTE_1)
+   preamble_fp.close()
+
+   return boot_sbl_header
+
+#----------------------------------------------------------------------------
+# Helper functions to parse ELF program headers
+#----------------------------------------------------------------------------
+def MI_PBT_SEGMENT_TYPE_VALUE(x):
+    return ( ((x) & MI_PBT_FLAG_SEGMENT_TYPE_MASK) >> MI_PBT_FLAG_SEGMENT_TYPE_SHIFT )
+
+def MI_PBT_PAGE_MODE_VALUE(x):
+    return ( ((x) & MI_PBT_FLAG_PAGE_MODE_MASK) >> MI_PBT_FLAG_PAGE_MODE_SHIFT )
+
+def MI_PBT_ACCESS_TYPE_VALUE(x):
+    return ( ((x) & MI_PBT_FLAG_ACCESS_TYPE_MASK) >> MI_PBT_FLAG_ACCESS_TYPE_SHIFT )
+
+def MI_PBT_CHECK_FLAG_TYPE(x):
+    return (MI_PBT_SEGMENT_TYPE_VALUE(x) != MI_PBT_HASH_SEGMENT) and \
+           (MI_PBT_ACCESS_TYPE_VALUE(x) != MI_PBT_NOTUSED_SEGMENT) and \
+           (MI_PBT_ACCESS_TYPE_VALUE(x) != MI_PBT_SHARED_SEGMENT)
+
+
+#----------------------------------------------------------------------------
+# Helper functions to open a file and return a valid file object
+#----------------------------------------------------------------------------
+def OPEN(file_name, mode):
+    try:
+       fp = open(file_name, mode)
+    except IOError:
+      raise RuntimeError("The file could not be opened: " + file_name)
+
+    # File open has succeeded with the given mode, return the file object
+    return fp
+
+#----------------------------------------------------------------------------
+# Helper functions to insert MCs in SBL1(Badger) if ENABLE_VIRTUAL_BLK is ON
+#----------------------------------------------------------------------------
+def insert_SBL1_magicCookie (env, target):
+    file = open(target, "rb")
+    #read the file contents
+    filedata = file.read()
+    length = len(filedata)
+    file.close()
+
+    if (length <= VIRTUAL_BLOCK_SIZE):
+        return None
+    else:
+        #remove the previous file
+        os.remove(target)
+        #generate new file for appending target data + required MCs
+        file = open(target, "ab")
+
+        while length > VIRTUAL_BLOCK_SIZE:
+            filedata_till_128kb = filedata[0:VIRTUAL_BLOCK_SIZE]
+            filedata_after_128kb = filedata[VIRTUAL_BLOCK_SIZE:length]
+
+            a = str(hex(FLASH_CODE_WORD))
+            mc1 = chr(int(a[8:10],16)) + chr(int(a[6:8],16)) + chr(int(a[4:6],16)) + chr(int(a[2:4],16))
+
+            b = str(hex(MAGIC_NUM))
+            mc2 = chr(int(b[8:10],16)) + chr(int(b[6:8],16)) + chr(int(b[4:6],16)) + chr(int(b[2:4],16))
+
+            c = str(hex(SBL_VIRTUAL_BLOCK_MAGIC_NUM))
+            mc3 = chr(int(c[8:10],16)) + chr(int(c[6:8],16)) + chr(int(c[4:6],16)) + chr(int(c[2:4],16))
+
+            #MC_inserted_data = filedata_till_128kb + mc1 + mc2 + mc3
+            file.write(filedata_till_128kb)
+
+            MC_inserted_data = mc1 + mc2 + mc3 + filedata_after_128kb
+            #filedata = filedata_after_128kb
+            filedata = MC_inserted_data
+            length = len(filedata)
+
+        #copy the leftover data (<128KB) in output file
+        if length > 0:
+            file.write(filedata)
+
+        #close the final output file
+        file.close()
+    # MC_insertion code end
+
+#----------------------------------------------------------------------------
+# Helper functions to remove MCs in SBL1(Badger)
+#----------------------------------------------------------------------------
+def remove_SBL1_magicCookie (env, target, dest):
+    file = open(target, "rb")
+    #read the file contents
+    filedata = file.read()
+    length = len(filedata)
+    file.close()
+
+    #generate new file for appending target data + required MCs
+    file = open(dest, "ab")
+
+    while length > VIRTUAL_BLOCK_SIZE:
+        filedata_till_128kb = filedata[0:VIRTUAL_BLOCK_SIZE]
+        # skipped 12 byte of Virtual Block Magic Cookie Header
+        filedata_after_128kb = filedata[VIRTUAL_BLOCK_SIZE+MAGIC_COOKIE_LENGTH:length]
+
+        file.write(filedata_till_128kb)
+
+        filedata = filedata_after_128kb
+        length = len(filedata)
+
+    #copy the leftover data (<128KB) in output file
+    if length > 0:
+        file.write(filedata)
+
+    #close the final output file
+    file.close()
+
+    # MC_removal code end
+
+#----------------------------------------------------------------------------
+# Helper functions to pad SBL1 image
+# min_size defaults to 256k
+# If page_size or num_of_pages is set to 0, the variable is unset
+#----------------------------------------------------------------------------
+def pad_SBL1_image (env, target, min_size_with_pad=MIN_IMAGE_SIZE_WITH_PAD, page_size=0, num_of_pages=0):
+    file = open(target, "rb")
+    #read the file contents
+    filedata = file.read()
+    length = len(filedata)
+    file.close()
+
+    multiple = 1
+    alignment = page_size * num_of_pages
+
+    if (length > alignment and alignment > 0):
+      import math
+      multiple = math.ceil(length/float(alignment))
+
+    final_image_size = max(min_size_with_pad, multiple * alignment)
+
+    if length < final_image_size:
+      sbl1_fp = open(target, 'ab')
+      pad_file (sbl1_fp, (final_image_size-length), PAD_BYTE_0)
+      sbl1_fp.close()
+
+   # SBL1 pad code end
+#----------------------------------------------------------------------------
+# HELPER FUNCTIONS END
+#----------------------------------------------------------------------------
+